(0h0)) \n node _T_1452 = asUInt(reset) \n node _T_1453 = eq(_T_1452, UInt<1>(0h0)) \n when _T_1453 : \n node _T_1454 = eq(_T_1451, UInt<1>(0h0)) \n when _T_1454 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_82 \n assert(clock, _T_1451, UInt<1>(0h1), \"\") : assert_82 \n node _T_1455 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_1456 = or(UInt<1>(0h1), _T_1455) \n node _T_1457 = asUInt(reset) \n node _T_1458 = eq(_T_1457, UInt<1>(0h0)) \n when _T_1458 : \n node _T_1459 = eq(_T_1456, UInt<1>(0h0)) \n when _T_1459 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_83 \n assert(clock, _T_1456, UInt<1>(0h1), \"\") : assert_83 \n wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE.bits.corrupt, UInt<1>(0h0) \n connect _WIRE.bits.data, UInt<64>(0h0) \n connect _WIRE.bits.mask, UInt<8>(0h0) \n connect _WIRE.bits.address, UInt<32>(0h0) \n connect _WIRE.bits.source, UInt<4>(0h0) \n connect _WIRE.bits.size, UInt<4>(0h0) \n connect _WIRE.bits.param, UInt<2>(0h0) \n connect _WIRE.bits.opcode, UInt<3>(0h0) \n connect _WIRE.valid, UInt<1>(0h0) \n connect _WIRE.ready, UInt<1>(0h0) \n wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_1.bits, _WIRE.bits \n connect _WIRE_1.valid, _WIRE.valid \n connect _WIRE_1.ready, _WIRE.ready \n node _T_1460 = eq(_WIRE_1.valid, UInt<1>(0h0)) \n node _T_1461 = asUInt(reset) \n node _T_1462 = eq(_T_1461, UInt<1>(0h0)) \n when _T_1462 : \n node _T_1463 = eq(_T_1460, UInt<1>(0h0)) \n when _T_1463 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_84 \n assert(clock, _T_1460, UInt<1>(0h1), \"\") : assert_84 \n wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_2.bits.data, UInt<64>(0h0) \n connect _WIRE_2.bits.address, UInt<32>(0h0) \n connect _WIRE_2.bits.source, UInt<4>(0h0) \n connect _WIRE_2.bits.size, UInt<4>(0h0) \n connect _WIRE_2.bits.param, UInt<3>(0h0) \n connect _WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _WIRE_2.valid, UInt<1>(0h0) \n connect _WIRE_2.ready, UInt<1>(0h0) \n wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_3.bits, _WIRE_2.bits \n connect _WIRE_3.valid, _WIRE_2.valid \n connect _WIRE_3.ready, _WIRE_2.ready \n node _T_1464 = eq(_WIRE_3.valid, UInt<1>(0h0)) \n node _T_1465 = asUInt(reset) \n node _T_1466 = eq(_T_1465, UInt<1>(0h0)) \n when _T_1466 : \n node _T_1467 = eq(_T_1464, UInt<1>(0h0)) \n when _T_1467 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_85 \n assert(clock, _T_1464, UInt<1>(0h1), \"\") : assert_85 \n wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} \n connect _WIRE_4.bits.sink, UInt<3>(0h0) \n connect _WIRE_4.valid, UInt<1>(0h0) \n connect _WIRE_4.ready, UInt<1>(0h0) \n wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} \n connect _WIRE_5.bits, _WIRE_4.bits \n connect _WIRE_5.valid, _WIRE_4.valid \n connect _WIRE_5.ready, _WIRE_4.ready \n node _T_1468 = eq(_WIRE_5.valid, UInt<1>(0h0)) \n node _T_1469 = asUInt(reset) \n node _T_1470 = eq(_T_1469, UInt<1>(0h0)) \n when _T_1470 : \n node _T_1471 = eq(_T_1468, UInt<1>(0h0)) \n when _T_1471 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_86 \n assert(clock, _T_1468, UInt<1>(0h1), \"\") : assert_86 \n node _a_first_T = and(io.in.a.ready, io.in.a.valid) \n node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) \n node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) \n node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) \n node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) \n node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) \n node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) \n node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) \n regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) \n node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) \n node a_first_counter1 = tail(_a_first_counter1_T, 1) \n node a_first = eq(a_first_counter, UInt<1>(0h0)) \n node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) \n node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) \n node a_first_last = or(_a_first_last_T, _a_first_last_T_1) \n node a_first_done = and(a_first_last, _a_first_T) \n node _a_first_count_T = not(a_first_counter1) \n node a_first_count = and(a_first_beats1, _a_first_count_T) \n when _a_first_T : \n node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) \n connect a_first_counter, _a_first_counter_T \n reg opcode : UInt, clock \n reg param : UInt, clock \n reg size : UInt, clock \n reg source : UInt, clock \n reg address : UInt, clock \n node _T_1472 = eq(a_first, UInt<1>(0h0)) \n node _T_1473 = and(io.in.a.valid, _T_1472) \n when _T_1473 : \n node _T_1474 = eq(io.in.a.bits.opcode, opcode) \n node _T_1475 = asUInt(reset) \n node _T_1476 = eq(_T_1475, UInt<1>(0h0)) \n when _T_1476 : \n node _T_1477 = eq(_T_1474, UInt<1>(0h0)) \n when _T_1477 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_87 \n assert(clock, _T_1474, UInt<1>(0h1), \"\") : assert_87 \n node _T_1478 = eq(io.in.a.bits.param, param) \n node _T_1479 = asUInt(reset) \n node _T_1480 = eq(_T_1479, UInt<1>(0h0)) \n when _T_1480 : \n node _T_1481 = eq(_T_1478, UInt<1>(0h0)) \n when _T_1481 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_88 \n assert(clock, _T_1478, UInt<1>(0h1), \"\") : assert_88 \n node _T_1482 = eq(io.in.a.bits.size, size) \n node _T_1483 = asUInt(reset) \n node _T_1484 = eq(_T_1483, UInt<1>(0h0)) \n when _T_1484 : \n node _T_1485 = eq(_T_1482, UInt<1>(0h0)) \n when _T_1485 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_89 \n assert(clock, _T_1482, UInt<1>(0h1), \"\") : assert_89 \n node _T_1486 = eq(io.in.a.bits.source, source) \n node _T_1487 = asUInt(reset) \n node _T_1488 = eq(_T_1487, UInt<1>(0h0)) \n when _T_1488 : \n node _T_1489 = eq(_T_1486, UInt<1>(0h0)) \n when _T_1489 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_90 \n assert(clock, _T_1486, UInt<1>(0h1), \"\") : assert_90 \n node _T_1490 = eq(io.in.a.bits.address, address) \n node _T_1491 = asUInt(reset) \n node _T_1492 = eq(_T_1491, UInt<1>(0h0)) \n when _T_1492 : \n node _T_1493 = eq(_T_1490, UInt<1>(0h0)) \n when _T_1493 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_91 \n assert(clock, _T_1490, UInt<1>(0h1), \"\") : assert_91 \n node _T_1494 = and(io.in.a.ready, io.in.a.valid) \n node _T_1495 = and(_T_1494, a_first) \n when _T_1495 : \n connect opcode, io.in.a.bits.opcode \n connect param, io.in.a.bits.param \n connect size, io.in.a.bits.size \n connect source, io.in.a.bits.source \n connect address, io.in.a.bits.address \n node _d_first_T = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) \n node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) \n node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) \n node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) \n node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) \n regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) \n node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) \n node d_first_counter1 = tail(_d_first_counter1_T, 1) \n node d_first = eq(d_first_counter, UInt<1>(0h0)) \n node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) \n node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) \n node d_first_last = or(_d_first_last_T, _d_first_last_T_1) \n node d_first_done = and(d_first_last, _d_first_T) \n node _d_first_count_T = not(d_first_counter1) \n node d_first_count = and(d_first_beats1, _d_first_count_T) \n when _d_first_T : \n node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) \n connect d_first_counter, _d_first_counter_T \n reg opcode_1 : UInt, clock \n reg param_1 : UInt, clock \n reg size_1 : UInt, clock \n reg source_1 : UInt, clock \n reg sink : UInt, clock \n reg denied : UInt<1>, clock \n node _T_1496 = eq(d_first, UInt<1>(0h0)) \n node _T_1497 = and(io.in.d.valid, _T_1496) \n when _T_1497 : \n node _T_1498 = eq(io.in.d.bits.opcode, opcode_1) \n node _T_1499 = asUInt(reset) \n node _T_1500 = eq(_T_1499, UInt<1>(0h0)) \n when _T_1500 : \n node _T_1501 = eq(_T_1498, UInt<1>(0h0)) \n when _T_1501 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_92 \n assert(clock, _T_1498, UInt<1>(0h1), \"\") : assert_92 \n node _T_1502 = eq(io.in.d.bits.param, param_1) \n node _T_1503 = asUInt(reset) \n node _T_1504 = eq(_T_1503, UInt<1>(0h0)) \n when _T_1504 : \n node _T_1505 = eq(_T_1502, UInt<1>(0h0)) \n when _T_1505 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_93 \n assert(clock, _T_1502, UInt<1>(0h1), \"\") : assert_93 \n node _T_1506 = eq(io.in.d.bits.size, size_1) \n node _T_1507 = asUInt(reset) \n node _T_1508 = eq(_T_1507, UInt<1>(0h0)) \n when _T_1508 : \n node _T_1509 = eq(_T_1506, UInt<1>(0h0)) \n when _T_1509 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_94 \n assert(clock, _T_1506, UInt<1>(0h1), \"\") : assert_94 \n node _T_1510 = eq(io.in.d.bits.source, source_1) \n node _T_1511 = asUInt(reset) \n node _T_1512 = eq(_T_1511, UInt<1>(0h0)) \n when _T_1512 : \n node _T_1513 = eq(_T_1510, UInt<1>(0h0)) \n when _T_1513 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_95 \n assert(clock, _T_1510, UInt<1>(0h1), \"\") : assert_95 \n node _T_1514 = eq(io.in.d.bits.sink, sink) \n node _T_1515 = asUInt(reset) \n node _T_1516 = eq(_T_1515, UInt<1>(0h0)) \n when _T_1516 : \n node _T_1517 = eq(_T_1514, UInt<1>(0h0)) \n when _T_1517 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_96 \n assert(clock, _T_1514, UInt<1>(0h1), \"\") : assert_96 \n node _T_1518 = eq(io.in.d.bits.denied, denied) \n node _T_1519 = asUInt(reset) \n node _T_1520 = eq(_T_1519, UInt<1>(0h0)) \n when _T_1520 : \n node _T_1521 = eq(_T_1518, UInt<1>(0h0)) \n when _T_1521 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_97 \n assert(clock, _T_1518, UInt<1>(0h1), \"\") : assert_97 \n node _T_1522 = and(io.in.d.ready, io.in.d.valid) \n node _T_1523 = and(_T_1522, d_first) \n when _T_1523 : \n connect opcode_1, io.in.d.bits.opcode \n connect param_1, io.in.d.bits.param \n connect size_1, io.in.d.bits.size \n connect source_1, io.in.d.bits.source \n connect sink, io.in.d.bits.sink \n connect denied, io.in.d.bits.denied \n regreset inflight : UInt<16>, clock, reset, UInt<16>(0h0) \n regreset inflight_opcodes : UInt<64>, clock, reset, UInt<64>(0h0) \n regreset inflight_sizes : UInt<128>, clock, reset, UInt<128>(0h0) \n node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) \n node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) \n node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) \n node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) \n node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) \n node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) \n node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) \n node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) \n regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) \n node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) \n node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) \n node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) \n node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) \n node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) \n node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) \n node a_first_done_1 = and(a_first_last_1, _a_first_T_1) \n node _a_first_count_T_1 = not(a_first_counter1_1) \n node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) \n when _a_first_T_1 : \n node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) \n connect a_first_counter_1, _a_first_counter_T_1 \n node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) \n node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) \n node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) \n node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) \n node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) \n regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) \n node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) \n node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) \n node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) \n node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) \n node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) \n node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) \n node d_first_done_1 = and(d_first_last_1, _d_first_T_1) \n node _d_first_count_T_1 = not(d_first_counter1_1) \n node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) \n when _d_first_T_1 : \n node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) \n connect d_first_counter_1, _d_first_counter_T_1 \n wire a_set : UInt<16> \n connect a_set, UInt<16>(0h0) \n wire a_set_wo_ready : UInt<16> \n connect a_set_wo_ready, UInt<16>(0h0) \n wire a_opcodes_set : UInt<64> \n connect a_opcodes_set, UInt<64>(0h0) \n wire a_sizes_set : UInt<128> \n connect a_sizes_set, UInt<128>(0h0) \n wire a_opcode_lookup : UInt<3> \n connect a_opcode_lookup, UInt<3>(0h0) \n node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) \n node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) \n node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) \n node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) \n node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) \n node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) \n connect a_opcode_lookup, _a_opcode_lookup_T_7 \n wire a_size_lookup : UInt<8> \n connect a_size_lookup, UInt<8>(0h0) \n node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) \n node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) \n node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) \n node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) \n node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) \n node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) \n node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) \n node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) \n connect a_size_lookup, _a_size_lookup_T_7 \n wire responseMap : UInt<3>[8] \n connect responseMap[0], UInt<1>(0h0) \n connect responseMap[1], UInt<1>(0h0) \n connect responseMap[2], UInt<1>(0h1) \n connect responseMap[3], UInt<1>(0h1) \n connect responseMap[4], UInt<1>(0h1) \n connect responseMap[5], UInt<2>(0h2) \n connect responseMap[6], UInt<3>(0h4) \n connect responseMap[7], UInt<3>(0h4) \n wire responseMapSecondOption : UInt<3>[8] \n connect responseMapSecondOption[0], UInt<1>(0h0) \n connect responseMapSecondOption[1], UInt<1>(0h0) \n connect responseMapSecondOption[2], UInt<1>(0h1) \n connect responseMapSecondOption[3], UInt<1>(0h1) \n connect responseMapSecondOption[4], UInt<1>(0h1) \n connect responseMapSecondOption[5], UInt<2>(0h2) \n connect responseMapSecondOption[6], UInt<3>(0h5) \n connect responseMapSecondOption[7], UInt<3>(0h4) \n wire a_opcodes_set_interm : UInt<4> \n connect a_opcodes_set_interm, UInt<4>(0h0) \n wire a_sizes_set_interm : UInt<5> \n connect a_sizes_set_interm, UInt<5>(0h0) \n node _T_1524 = and(io.in.a.valid, a_first_1) \n node _T_1525 = and(_T_1524, UInt<1>(0h1)) \n when _T_1525 : \n node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) \n connect a_set_wo_ready, _a_set_wo_ready_T \n node _T_1526 = and(io.in.a.ready, io.in.a.valid) \n node _T_1527 = and(_T_1526, a_first_1) \n node _T_1528 = and(_T_1527, UInt<1>(0h1)) \n when _T_1528 : \n node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) \n connect a_set, _a_set_T \n node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) \n node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) \n connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 \n node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) \n node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) \n connect a_sizes_set_interm, _a_sizes_set_interm_T_1 \n node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) \n node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) \n connect a_opcodes_set, _a_opcodes_set_T_1 \n node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) \n node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) \n connect a_sizes_set, _a_sizes_set_T_1 \n node _T_1529 = dshr(inflight, io.in.a.bits.source) \n node _T_1530 = bits(_T_1529, 0, 0) \n node _T_1531 = eq(_T_1530, UInt<1>(0h0)) \n node _T_1532 = asUInt(reset) \n node _T_1533 = eq(_T_1532, UInt<1>(0h0)) \n when _T_1533 : \n node _T_1534 = eq(_T_1531, UInt<1>(0h0)) \n when _T_1534 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_98 \n assert(clock, _T_1531, UInt<1>(0h1), \"\") : assert_98 \n wire d_clr : UInt<16> \n connect d_clr, UInt<16>(0h0) \n wire d_clr_wo_ready : UInt<16> \n connect d_clr_wo_ready, UInt<16>(0h0) \n wire d_opcodes_clr : UInt<64> \n connect d_opcodes_clr, UInt<64>(0h0) \n wire d_sizes_clr : UInt<128> \n connect d_sizes_clr, UInt<128>(0h0) \n node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_1535 = and(io.in.d.valid, d_first_1) \n node _T_1536 = and(_T_1535, UInt<1>(0h1)) \n node _T_1537 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_1538 = and(_T_1536, _T_1537) \n when _T_1538 : \n node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_wo_ready, _d_clr_wo_ready_T \n node _T_1539 = and(io.in.d.ready, io.in.d.valid) \n node _T_1540 = and(_T_1539, d_first_1) \n node _T_1541 = and(_T_1540, UInt<1>(0h1)) \n node _T_1542 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_1543 = and(_T_1541, _T_1542) \n when _T_1543 : \n node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr, _d_clr_T \n node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) \n node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) \n node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) \n node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) \n connect d_opcodes_clr, _d_opcodes_clr_T_5 \n node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) \n node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) \n node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) \n node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) \n node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) \n node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) \n connect d_sizes_clr, _d_sizes_clr_T_5 \n node _T_1544 = and(io.in.d.valid, d_first_1) \n node _T_1545 = and(_T_1544, UInt<1>(0h1)) \n node _T_1546 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_1547 = and(_T_1545, _T_1546) \n when _T_1547 : \n node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) \n node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) \n node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) \n node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) \n node _T_1548 = dshr(inflight, io.in.d.bits.source) \n node _T_1549 = bits(_T_1548, 0, 0) \n node _T_1550 = or(_T_1549, same_cycle_resp) \n node _T_1551 = asUInt(reset) \n node _T_1552 = eq(_T_1551, UInt<1>(0h0)) \n when _T_1552 : \n node _T_1553 = eq(_T_1550, UInt<1>(0h0)) \n when _T_1553 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_99 \n assert(clock, _T_1550, UInt<1>(0h1), \"\") : assert_99 \n when same_cycle_resp : \n node _T_1554 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) \n node _T_1555 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) \n node _T_1556 = or(_T_1554, _T_1555) \n node _T_1557 = asUInt(reset) \n node _T_1558 = eq(_T_1557, UInt<1>(0h0)) \n when _T_1558 : \n node _T_1559 = eq(_T_1556, UInt<1>(0h0)) \n when _T_1559 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_100 \n assert(clock, _T_1556, UInt<1>(0h1), \"\") : assert_100 \n node _T_1560 = eq(io.in.a.bits.size, io.in.d.bits.size) \n node _T_1561 = asUInt(reset) \n node _T_1562 = eq(_T_1561, UInt<1>(0h0)) \n when _T_1562 : \n node _T_1563 = eq(_T_1560, UInt<1>(0h0)) \n when _T_1563 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_101 \n assert(clock, _T_1560, UInt<1>(0h1), \"\") : assert_101 \n else :\n\n node _T_1564 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) \n node _T_1565 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) \n node _T_1566 = or(_T_1564, _T_1565) \n node _T_1567 = asUInt(reset) \n node _T_1568 = eq(_T_1567, UInt<1>(0h0)) \n when _T_1568 : \n node _T_1569 = eq(_T_1566, UInt<1>(0h0)) \n when _T_1569 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_102 \n assert(clock, _T_1566, UInt<1>(0h1), \"\") : assert_102 \n node _T_1570 = eq(io.in.d.bits.size, a_size_lookup) \n node _T_1571 = asUInt(reset) \n node _T_1572 = eq(_T_1571, UInt<1>(0h0)) \n when _T_1572 : \n node _T_1573 = eq(_T_1570, UInt<1>(0h0)) \n when _T_1573 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_103 \n assert(clock, _T_1570, UInt<1>(0h1), \"\") : assert_103 \n node _T_1574 = and(io.in.d.valid, d_first_1) \n node _T_1575 = and(_T_1574, a_first_1) \n node _T_1576 = and(_T_1575, io.in.a.valid) \n node _T_1577 = eq(io.in.a.bits.source, io.in.d.bits.source) \n node _T_1578 = and(_T_1576, _T_1577) \n node _T_1579 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_1580 = and(_T_1578, _T_1579) \n when _T_1580 : \n node _T_1581 = eq(io.in.d.ready, UInt<1>(0h0)) \n node _T_1582 = or(_T_1581, io.in.a.ready) \n node _T_1583 = asUInt(reset) \n node _T_1584 = eq(_T_1583, UInt<1>(0h0)) \n when _T_1584 : \n node _T_1585 = eq(_T_1582, UInt<1>(0h0)) \n when _T_1585 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: ready check\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_104 \n assert(clock, _T_1582, UInt<1>(0h1), \"\") : assert_104 \n node _T_1586 = neq(a_set_wo_ready, d_clr_wo_ready) \n node _T_1587 = orr(a_set_wo_ready) \n node _T_1588 = eq(_T_1587, UInt<1>(0h0)) \n node _T_1589 = or(_T_1586, _T_1588) \n node _T_1590 = asUInt(reset) \n node _T_1591 = eq(_T_1590, UInt<1>(0h0)) \n when _T_1591 : \n node _T_1592 = eq(_T_1589, UInt<1>(0h0)) \n when _T_1592 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_105 \n assert(clock, _T_1589, UInt<1>(0h1), \"\") : assert_105 \n node _inflight_T = or(inflight, a_set) \n node _inflight_T_1 = not(d_clr) \n node _inflight_T_2 = and(_inflight_T, _inflight_T_1) \n connect inflight, _inflight_T_2 \n node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) \n node _inflight_opcodes_T_1 = not(d_opcodes_clr) \n node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) \n connect inflight_opcodes, _inflight_opcodes_T_2 \n node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) \n node _inflight_sizes_T_1 = not(d_sizes_clr) \n node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) \n connect inflight_sizes, _inflight_sizes_T_2 \n regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) \n inst plusarg_reader of plusarg_reader_46 \n node _T_1593 = orr(inflight) \n node _T_1594 = eq(_T_1593, UInt<1>(0h0)) \n node _T_1595 = eq(plusarg_reader.out, UInt<1>(0h0)) \n node _T_1596 = or(_T_1594, _T_1595) \n node _T_1597 = lt(watchdog, plusarg_reader.out) \n node _T_1598 = or(_T_1596, _T_1597) \n node _T_1599 = asUInt(reset) \n node _T_1600 = eq(_T_1599, UInt<1>(0h0)) \n when _T_1600 : \n node _T_1601 = eq(_T_1598, UInt<1>(0h0)) \n when _T_1601 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_106 \n assert(clock, _T_1598, UInt<1>(0h1), \"\") : assert_106 \n node _watchdog_T = add(watchdog, UInt<1>(0h1)) \n node _watchdog_T_1 = tail(_watchdog_T, 1) \n connect watchdog, _watchdog_T_1 \n node _T_1602 = and(io.in.a.ready, io.in.a.valid) \n node _T_1603 = and(io.in.d.ready, io.in.d.valid) \n node _T_1604 = or(_T_1602, _T_1603) \n when _T_1604 : \n connect watchdog, UInt<1>(0h0) \n regreset inflight_1 : UInt<16>, clock, reset, UInt<16>(0h0) \n regreset inflight_opcodes_1 : UInt<64>, clock, reset, UInt<64>(0h0) \n regreset inflight_sizes_1 : UInt<128>, clock, reset, UInt<128>(0h0) \n wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_first_WIRE.bits.data, UInt<64>(0h0) \n connect _c_first_WIRE.bits.address, UInt<32>(0h0) \n connect _c_first_WIRE.bits.source, UInt<4>(0h0) \n connect _c_first_WIRE.bits.size, UInt<4>(0h0) \n connect _c_first_WIRE.bits.param, UInt<3>(0h0) \n connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_first_WIRE.valid, UInt<1>(0h0) \n connect _c_first_WIRE.ready, UInt<1>(0h0) \n wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_first_WIRE_1.bits, _c_first_WIRE.bits \n connect _c_first_WIRE_1.valid, _c_first_WIRE.valid \n connect _c_first_WIRE_1.ready, _c_first_WIRE.ready \n wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) \n connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) \n connect _c_first_WIRE_2.bits.source, UInt<4>(0h0) \n connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) \n connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) \n connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _c_first_WIRE_2.valid, UInt<1>(0h0) \n connect _c_first_WIRE_2.ready, UInt<1>(0h0) \n wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits \n connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid \n connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready \n node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) \n node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) \n node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) \n node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) \n node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) \n node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) \n node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) \n regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) \n node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) \n node c_first_counter1 = tail(_c_first_counter1_T, 1) \n node c_first = eq(c_first_counter, UInt<1>(0h0)) \n node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) \n node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) \n node c_first_last = or(_c_first_last_T, _c_first_last_T_1) \n node c_first_done = and(c_first_last, _c_first_T) \n node _c_first_count_T = not(c_first_counter1) \n node c_first_count = and(c_first_beats1, _c_first_count_T) \n when _c_first_T : \n node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) \n connect c_first_counter, _c_first_counter_T \n node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) \n node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) \n node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) \n node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) \n node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) \n regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) \n node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) \n node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) \n node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) \n node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) \n node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) \n node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) \n node d_first_done_2 = and(d_first_last_2, _d_first_T_2) \n node _d_first_count_T_2 = not(d_first_counter1_2) \n node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) \n when _d_first_T_2 : \n node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) \n connect d_first_counter_2, _d_first_counter_T_2 \n wire c_set : UInt<16> \n connect c_set, UInt<16>(0h0) \n wire c_set_wo_ready : UInt<16> \n connect c_set_wo_ready, UInt<16>(0h0) \n wire c_opcodes_set : UInt<64> \n connect c_opcodes_set, UInt<64>(0h0) \n wire c_sizes_set : UInt<128> \n connect c_sizes_set, UInt<128>(0h0) \n wire c_opcode_lookup : UInt<4> \n connect c_opcode_lookup, UInt<4>(0h0) \n wire c_size_lookup : UInt<8> \n connect c_size_lookup, UInt<8>(0h0) \n node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) \n node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) \n node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) \n node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) \n node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) \n node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) \n connect c_opcode_lookup, _c_opcode_lookup_T_7 \n node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) \n node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) \n node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) \n node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) \n node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) \n node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) \n node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) \n node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) \n connect c_size_lookup, _c_size_lookup_T_7 \n wire c_opcodes_set_interm : UInt<4> \n connect c_opcodes_set_interm, UInt<4>(0h0) \n wire c_sizes_set_interm : UInt<5> \n connect c_sizes_set_interm, UInt<5>(0h0) \n wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_6.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_6.bits.data, UInt<64>(0h0) \n connect _WIRE_6.bits.address, UInt<32>(0h0) \n connect _WIRE_6.bits.source, UInt<4>(0h0) \n connect _WIRE_6.bits.size, UInt<4>(0h0) \n connect _WIRE_6.bits.param, UInt<3>(0h0) \n connect _WIRE_6.bits.opcode, UInt<3>(0h0) \n connect _WIRE_6.valid, UInt<1>(0h0) \n connect _WIRE_6.ready, UInt<1>(0h0) \n wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_7.bits, _WIRE_6.bits \n connect _WIRE_7.valid, _WIRE_6.valid \n connect _WIRE_7.ready, _WIRE_6.ready \n node _T_1605 = and(_WIRE_7.valid, c_first) \n wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_8.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_8.bits.data, UInt<64>(0h0) \n connect _WIRE_8.bits.address, UInt<32>(0h0) \n connect _WIRE_8.bits.source, UInt<4>(0h0) \n connect _WIRE_8.bits.size, UInt<4>(0h0) \n connect _WIRE_8.bits.param, UInt<3>(0h0) \n connect _WIRE_8.bits.opcode, UInt<3>(0h0) \n connect _WIRE_8.valid, UInt<1>(0h0) \n connect _WIRE_8.ready, UInt<1>(0h0) \n wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_9.bits, _WIRE_8.bits \n connect _WIRE_9.valid, _WIRE_8.valid \n connect _WIRE_9.ready, _WIRE_8.ready \n node _T_1606 = bits(_WIRE_9.bits.opcode, 2, 2) \n node _T_1607 = bits(_WIRE_9.bits.opcode, 1, 1) \n node _T_1608 = and(_T_1606, _T_1607) \n node _T_1609 = and(_T_1605, _T_1608) \n when _T_1609 : \n wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) \n connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) \n connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0) \n connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) \n connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) \n connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) \n connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) \n wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits \n connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid \n connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready \n node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) \n connect c_set_wo_ready, _c_set_wo_ready_T \n wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_10.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_10.bits.data, UInt<64>(0h0) \n connect _WIRE_10.bits.address, UInt<32>(0h0) \n connect _WIRE_10.bits.source, UInt<4>(0h0) \n connect _WIRE_10.bits.size, UInt<4>(0h0) \n connect _WIRE_10.bits.param, UInt<3>(0h0) \n connect _WIRE_10.bits.opcode, UInt<3>(0h0) \n connect _WIRE_10.valid, UInt<1>(0h0) \n connect _WIRE_10.ready, UInt<1>(0h0) \n wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_11.bits, _WIRE_10.bits \n connect _WIRE_11.valid, _WIRE_10.valid \n connect _WIRE_11.ready, _WIRE_10.ready \n node _T_1610 = and(_WIRE_11.ready, _WIRE_11.valid) \n node _T_1611 = and(_T_1610, c_first) \n wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_12.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_12.bits.data, UInt<64>(0h0) \n connect _WIRE_12.bits.address, UInt<32>(0h0) \n connect _WIRE_12.bits.source, UInt<4>(0h0) \n connect _WIRE_12.bits.size, UInt<4>(0h0) \n connect _WIRE_12.bits.param, UInt<3>(0h0) \n connect _WIRE_12.bits.opcode, UInt<3>(0h0) \n connect _WIRE_12.valid, UInt<1>(0h0) \n connect _WIRE_12.ready, UInt<1>(0h0) \n wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_13.bits, _WIRE_12.bits \n connect _WIRE_13.valid, _WIRE_12.valid \n connect _WIRE_13.ready, _WIRE_12.ready \n node _T_1612 = bits(_WIRE_13.bits.opcode, 2, 2) \n node _T_1613 = bits(_WIRE_13.bits.opcode, 1, 1) \n node _T_1614 = and(_T_1612, _T_1613) \n node _T_1615 = and(_T_1611, _T_1614) \n when _T_1615 : \n wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_set_WIRE.bits.data, UInt<64>(0h0) \n connect _c_set_WIRE.bits.address, UInt<32>(0h0) \n connect _c_set_WIRE.bits.source, UInt<4>(0h0) \n connect _c_set_WIRE.bits.size, UInt<4>(0h0) \n connect _c_set_WIRE.bits.param, UInt<3>(0h0) \n connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_set_WIRE.valid, UInt<1>(0h0) \n connect _c_set_WIRE.ready, UInt<1>(0h0) \n wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_set_WIRE_1.bits, _c_set_WIRE.bits \n connect _c_set_WIRE_1.valid, _c_set_WIRE.valid \n connect _c_set_WIRE_1.ready, _c_set_WIRE.ready \n node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) \n connect c_set, _c_set_T \n wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) \n connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) \n wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits \n connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid \n connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready \n node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) \n node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) \n connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 \n wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) \n connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) \n wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits \n connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid \n connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready \n node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) \n node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) \n connect c_sizes_set_interm, _c_sizes_set_interm_T_1 \n wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) \n connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) \n connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0) \n connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) \n connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) \n connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) \n connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) \n wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits \n connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid \n connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready \n node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) \n node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) \n connect c_opcodes_set, _c_opcodes_set_T_1 \n wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) \n connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) \n connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0) \n connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) \n connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) \n connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) \n connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) \n wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits \n connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid \n connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready \n node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) \n node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) \n connect c_sizes_set, _c_sizes_set_T_1 \n wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_14.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_14.bits.data, UInt<64>(0h0) \n connect _WIRE_14.bits.address, UInt<32>(0h0) \n connect _WIRE_14.bits.source, UInt<4>(0h0) \n connect _WIRE_14.bits.size, UInt<4>(0h0) \n connect _WIRE_14.bits.param, UInt<3>(0h0) \n connect _WIRE_14.bits.opcode, UInt<3>(0h0) \n connect _WIRE_14.valid, UInt<1>(0h0) \n connect _WIRE_14.ready, UInt<1>(0h0) \n wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_15.bits, _WIRE_14.bits \n connect _WIRE_15.valid, _WIRE_14.valid \n connect _WIRE_15.ready, _WIRE_14.ready \n node _T_1616 = dshr(inflight_1, _WIRE_15.bits.source) \n node _T_1617 = bits(_T_1616, 0, 0) \n node _T_1618 = eq(_T_1617, UInt<1>(0h0)) \n node _T_1619 = asUInt(reset) \n node _T_1620 = eq(_T_1619, UInt<1>(0h0)) \n when _T_1620 : \n node _T_1621 = eq(_T_1618, UInt<1>(0h0)) \n when _T_1621 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_107 \n assert(clock, _T_1618, UInt<1>(0h1), \"\") : assert_107 \n wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) \n connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) \n connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0) \n connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) \n connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) \n connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) \n connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) \n wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits \n connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid \n connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready \n node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) \n wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) \n connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) \n connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0) \n connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) \n connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) \n connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) \n connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) \n wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits \n connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid \n connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready \n node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) \n node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) \n wire d_clr_1 : UInt<16> \n connect d_clr_1, UInt<16>(0h0) \n wire d_clr_wo_ready_1 : UInt<16> \n connect d_clr_wo_ready_1, UInt<16>(0h0) \n wire d_opcodes_clr_1 : UInt<64> \n connect d_opcodes_clr_1, UInt<64>(0h0) \n wire d_sizes_clr_1 : UInt<128> \n connect d_sizes_clr_1, UInt<128>(0h0) \n node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_1622 = and(io.in.d.valid, d_first_2) \n node _T_1623 = and(_T_1622, UInt<1>(0h1)) \n node _T_1624 = and(_T_1623, d_release_ack_1) \n when _T_1624 : \n node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 \n node _T_1625 = and(io.in.d.ready, io.in.d.valid) \n node _T_1626 = and(_T_1625, d_first_2) \n node _T_1627 = and(_T_1626, UInt<1>(0h1)) \n node _T_1628 = and(_T_1627, d_release_ack_1) \n when _T_1628 : \n node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_1, _d_clr_T_1 \n node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) \n node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) \n node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) \n node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) \n connect d_opcodes_clr_1, _d_opcodes_clr_T_11 \n node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) \n node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) \n node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) \n node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) \n node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) \n node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) \n connect d_sizes_clr_1, _d_sizes_clr_T_11 \n node _T_1629 = and(io.in.d.valid, d_first_2) \n node _T_1630 = and(_T_1629, UInt<1>(0h1)) \n node _T_1631 = and(_T_1630, d_release_ack_1) \n when _T_1631 : \n wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) \n connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) \n connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0) \n connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) \n connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) \n wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits \n connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid \n connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready \n node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) \n wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) \n wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits \n connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid \n connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready \n node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) \n node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) \n node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) \n node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) \n wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) \n wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits \n connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid \n connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready \n node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) \n node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) \n node _T_1632 = dshr(inflight_1, io.in.d.bits.source) \n node _T_1633 = bits(_T_1632, 0, 0) \n node _T_1634 = or(_T_1633, same_cycle_resp_1) \n node _T_1635 = asUInt(reset) \n node _T_1636 = eq(_T_1635, UInt<1>(0h0)) \n when _T_1636 : \n node _T_1637 = eq(_T_1634, UInt<1>(0h0)) \n when _T_1637 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_108 \n assert(clock, _T_1634, UInt<1>(0h1), \"\") : assert_108 \n when same_cycle_resp_1 : \n wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_16.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_16.bits.data, UInt<64>(0h0) \n connect _WIRE_16.bits.address, UInt<32>(0h0) \n connect _WIRE_16.bits.source, UInt<4>(0h0) \n connect _WIRE_16.bits.size, UInt<4>(0h0) \n connect _WIRE_16.bits.param, UInt<3>(0h0) \n connect _WIRE_16.bits.opcode, UInt<3>(0h0) \n connect _WIRE_16.valid, UInt<1>(0h0) \n connect _WIRE_16.ready, UInt<1>(0h0) \n wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_17.bits, _WIRE_16.bits \n connect _WIRE_17.valid, _WIRE_16.valid \n connect _WIRE_17.ready, _WIRE_16.ready \n node _T_1638 = eq(io.in.d.bits.size, _WIRE_17.bits.size) \n node _T_1639 = asUInt(reset) \n node _T_1640 = eq(_T_1639, UInt<1>(0h0)) \n when _T_1640 : \n node _T_1641 = eq(_T_1638, UInt<1>(0h0)) \n when _T_1641 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_109 \n assert(clock, _T_1638, UInt<1>(0h1), \"\") : assert_109 \n else :\n\n node _T_1642 = eq(io.in.d.bits.size, c_size_lookup) \n node _T_1643 = asUInt(reset) \n node _T_1644 = eq(_T_1643, UInt<1>(0h0)) \n when _T_1644 : \n node _T_1645 = eq(_T_1642, UInt<1>(0h0)) \n when _T_1645 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_110 \n assert(clock, _T_1642, UInt<1>(0h1), \"\") : assert_110 \n node _T_1646 = and(io.in.d.valid, d_first_2) \n node _T_1647 = and(_T_1646, c_first) \n wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_18.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_18.bits.data, UInt<64>(0h0) \n connect _WIRE_18.bits.address, UInt<32>(0h0) \n connect _WIRE_18.bits.source, UInt<4>(0h0) \n connect _WIRE_18.bits.size, UInt<4>(0h0) \n connect _WIRE_18.bits.param, UInt<3>(0h0) \n connect _WIRE_18.bits.opcode, UInt<3>(0h0) \n connect _WIRE_18.valid, UInt<1>(0h0) \n connect _WIRE_18.ready, UInt<1>(0h0) \n wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_19.bits, _WIRE_18.bits \n connect _WIRE_19.valid, _WIRE_18.valid \n connect _WIRE_19.ready, _WIRE_18.ready \n node _T_1648 = and(_T_1647, _WIRE_19.valid) \n wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_20.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_20.bits.data, UInt<64>(0h0) \n connect _WIRE_20.bits.address, UInt<32>(0h0) \n connect _WIRE_20.bits.source, UInt<4>(0h0) \n connect _WIRE_20.bits.size, UInt<4>(0h0) \n connect _WIRE_20.bits.param, UInt<3>(0h0) \n connect _WIRE_20.bits.opcode, UInt<3>(0h0) \n connect _WIRE_20.valid, UInt<1>(0h0) \n connect _WIRE_20.ready, UInt<1>(0h0) \n wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_21.bits, _WIRE_20.bits \n connect _WIRE_21.valid, _WIRE_20.valid \n connect _WIRE_21.ready, _WIRE_20.ready \n node _T_1649 = eq(_WIRE_21.bits.source, io.in.d.bits.source) \n node _T_1650 = and(_T_1648, _T_1649) \n node _T_1651 = and(_T_1650, d_release_ack_1) \n node _T_1652 = eq(c_probe_ack, UInt<1>(0h0)) \n node _T_1653 = and(_T_1651, _T_1652) \n when _T_1653 : \n node _T_1654 = eq(io.in.d.ready, UInt<1>(0h0)) \n wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_22.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_22.bits.data, UInt<64>(0h0) \n connect _WIRE_22.bits.address, UInt<32>(0h0) \n connect _WIRE_22.bits.source, UInt<4>(0h0) \n connect _WIRE_22.bits.size, UInt<4>(0h0) \n connect _WIRE_22.bits.param, UInt<3>(0h0) \n connect _WIRE_22.bits.opcode, UInt<3>(0h0) \n connect _WIRE_22.valid, UInt<1>(0h0) \n connect _WIRE_22.ready, UInt<1>(0h0) \n wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_23.bits, _WIRE_22.bits \n connect _WIRE_23.valid, _WIRE_22.valid \n connect _WIRE_23.ready, _WIRE_22.ready \n node _T_1655 = or(_T_1654, _WIRE_23.ready) \n node _T_1656 = asUInt(reset) \n node _T_1657 = eq(_T_1656, UInt<1>(0h0)) \n when _T_1657 : \n node _T_1658 = eq(_T_1655, UInt<1>(0h0)) \n when _T_1658 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: ready check\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_111 \n assert(clock, _T_1655, UInt<1>(0h1), \"\") : assert_111 \n node _T_1659 = orr(c_set_wo_ready) \n when _T_1659 : \n node _T_1660 = neq(c_set_wo_ready, d_clr_wo_ready_1) \n node _T_1661 = asUInt(reset) \n node _T_1662 = eq(_T_1661, UInt<1>(0h0)) \n when _T_1662 : \n node _T_1663 = eq(_T_1660, UInt<1>(0h0)) \n when _T_1663 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_112 \n assert(clock, _T_1660, UInt<1>(0h1), \"\") : assert_112 \n node _inflight_T_3 = or(inflight_1, c_set) \n node _inflight_T_4 = not(d_clr_1) \n node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) \n connect inflight_1, _inflight_T_5 \n node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) \n node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) \n node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) \n connect inflight_opcodes_1, _inflight_opcodes_T_5 \n node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) \n node _inflight_sizes_T_4 = not(d_sizes_clr_1) \n node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) \n connect inflight_sizes_1, _inflight_sizes_T_5 \n regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) \n inst plusarg_reader_1 of plusarg_reader_47 \n node _T_1664 = orr(inflight_1) \n node _T_1665 = eq(_T_1664, UInt<1>(0h0)) \n node _T_1666 = eq(plusarg_reader_1.out, UInt<1>(0h0)) \n node _T_1667 = or(_T_1665, _T_1666) \n node _T_1668 = lt(watchdog_1, plusarg_reader_1.out) \n node _T_1669 = or(_T_1667, _T_1668) \n node _T_1670 = asUInt(reset) \n node _T_1671 = eq(_T_1670, UInt<1>(0h0)) \n when _T_1671 : \n node _T_1672 = eq(_T_1669, UInt<1>(0h0)) \n when _T_1672 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_113 \n assert(clock, _T_1669, UInt<1>(0h1), \"\") : assert_113 \n node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) \n node _watchdog_T_3 = tail(_watchdog_T_2, 1) \n connect watchdog_1, _watchdog_T_3 \n wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_24.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_24.bits.data, UInt<64>(0h0) \n connect _WIRE_24.bits.address, UInt<32>(0h0) \n connect _WIRE_24.bits.source, UInt<4>(0h0) \n connect _WIRE_24.bits.size, UInt<4>(0h0) \n connect _WIRE_24.bits.param, UInt<3>(0h0) \n connect _WIRE_24.bits.opcode, UInt<3>(0h0) \n connect _WIRE_24.valid, UInt<1>(0h0) \n connect _WIRE_24.ready, UInt<1>(0h0) \n wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_25.bits, _WIRE_24.bits \n connect _WIRE_25.valid, _WIRE_24.valid \n connect _WIRE_25.ready, _WIRE_24.ready \n node _T_1673 = and(_WIRE_25.ready, _WIRE_25.valid) \n node _T_1674 = and(io.in.d.ready, io.in.d.valid) \n node _T_1675 = or(_T_1673, _T_1674) \n when _T_1675 : \n connect watchdog_1, UInt<1>(0h0)"},"response":{"kind":"string","value":"module TLMonitor_23(\t// @[Monitor.scala:36:7]\n input clock,\t// @[Monitor.scala:36:7]\n input reset,\t// @[Monitor.scala:36:7]\n input io_in_a_ready,\t// @[Monitor.scala:20:14]\n input io_in_a_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_opcode,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_param,\t// @[Monitor.scala:20:14]\n input [3:0] io_in_a_bits_size,\t// @[Monitor.scala:20:14]\n input [3:0] io_in_a_bits_source,\t// @[Monitor.scala:20:14]\n input [31:0] io_in_a_bits_address,\t// @[Monitor.scala:20:14]\n input [7:0] io_in_a_bits_mask,\t// @[Monitor.scala:20:14]\n input [63:0] io_in_a_bits_data,\t// @[Monitor.scala:20:14]\n input io_in_a_bits_corrupt,\t// @[Monitor.scala:20:14]\n input io_in_d_ready,\t// @[Monitor.scala:20:14]\n input io_in_d_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_d_bits_opcode,\t// @[Monitor.scala:20:14]\n input [1:0] io_in_d_bits_param,\t// @[Monitor.scala:20:14]\n input [3:0] io_in_d_bits_size,\t// @[Monitor.scala:20:14]\n input [3:0] io_in_d_bits_source,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_d_bits_sink,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_denied,\t// @[Monitor.scala:20:14]\n input [63:0] io_in_d_bits_data,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_corrupt\t// @[Monitor.scala:20:14]\n);\n\n wire [31:0] _plusarg_reader_1_out;\t// @[PlusArg.scala:80:11]\n wire [31:0] _plusarg_reader_out;\t// @[PlusArg.scala:80:11]\n wire io_in_a_ready_0 = io_in_a_ready;\t// @[Monitor.scala:36:7]\n wire io_in_a_valid_0 = io_in_a_valid;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param;\t// @[Monitor.scala:36:7]\n wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size;\t// @[Monitor.scala:36:7]\n wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source;\t// @[Monitor.scala:36:7]\n wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address;\t// @[Monitor.scala:36:7]\n wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask;\t// @[Monitor.scala:36:7]\n wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data;\t// @[Monitor.scala:36:7]\n wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt;\t// @[Monitor.scala:36:7]\n wire io_in_d_ready_0 = io_in_d_ready;\t// @[Monitor.scala:36:7]\n wire io_in_d_valid_0 = io_in_d_valid;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode;\t// @[Monitor.scala:36:7]\n wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param;\t// @[Monitor.scala:36:7]\n wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size;\t// @[Monitor.scala:36:7]\n wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_denied_0 = io_in_d_bits_denied;\t// @[Monitor.scala:36:7]\n wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt;\t// @[Monitor.scala:36:7]\n wire _c_first_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_T = 1'h0;\t// @[Decoupled.scala:51:35]\n wire c_first_beats1_opdata = 1'h0;\t// @[Edges.scala:102:36]\n wire _c_first_last_T = 1'h0;\t// @[Edges.scala:232:25]\n wire c_first_done = 1'h0;\t// @[Edges.scala:233:22]\n wire _c_set_wo_ready_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_T = 1'h0;\t// @[Monitor.scala:772:47]\n wire _c_probe_ack_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_T_1 = 1'h0;\t// @[Monitor.scala:772:95]\n wire c_probe_ack = 1'h0;\t// @[Monitor.scala:772:71]\n wire _same_cycle_resp_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_T_3 = 1'h0;\t// @[Monitor.scala:795:44]\n wire _same_cycle_resp_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_T_4 = 1'h0;\t// @[Edges.scala:68:36]\n wire _same_cycle_resp_T_5 = 1'h0;\t// @[Edges.scala:68:51]\n wire _same_cycle_resp_T_6 = 1'h0;\t// @[Edges.scala:68:40]\n wire _same_cycle_resp_T_7 = 1'h0;\t// @[Monitor.scala:795:55]\n wire _same_cycle_resp_WIRE_4_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_5_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire same_cycle_resp_1 = 1'h0;\t// @[Monitor.scala:795:88]\n wire [8:0] c_first_beats1_decode = 9'h0;\t// @[Edges.scala:220:59]\n wire [8:0] c_first_beats1 = 9'h0;\t// @[Edges.scala:221:14]\n wire [8:0] _c_first_count_T = 9'h0;\t// @[Edges.scala:234:27]\n wire [8:0] c_first_count = 9'h0;\t// @[Edges.scala:234:25]\n wire [8:0] _c_first_counter_T = 9'h0;\t// @[Edges.scala:236:21]\n wire _source_ok_T_2 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_4 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_8 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_10 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_14 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_16 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_20 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_22 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_28 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_30 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_34 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_36 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_40 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_42 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_46 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_48 = 1'h1;\t// @[Parameters.scala:57:20]\n wire sink_ok = 1'h1;\t// @[Monitor.scala:309:31]\n wire c_first = 1'h1;\t// @[Edges.scala:231:25]\n wire _c_first_last_T_1 = 1'h1;\t// @[Edges.scala:232:43]\n wire c_first_last = 1'h1;\t// @[Edges.scala:232:33]\n wire [8:0] c_first_counter1 = 9'h1FF;\t// @[Edges.scala:230:28]\n wire [9:0] _c_first_counter1_T = 10'h3FF;\t// @[Edges.scala:230:28]\n wire [63:0] _c_first_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_first_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_first_WIRE_2_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_first_WIRE_3_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] c_opcodes_set = 64'h0;\t// @[Monitor.scala:740:34]\n wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_set_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_set_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_first_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_first_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_first_WIRE_2_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_first_WIRE_3_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_set_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_set_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_first_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_first_WIRE_bits_source = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_first_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_first_WIRE_1_bits_source = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_first_WIRE_2_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_first_WIRE_2_bits_source = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_first_WIRE_3_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_first_WIRE_3_bits_source = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] c_opcodes_set_interm = 4'h0;\t// @[Monitor.scala:754:40]\n wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_set_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_set_WIRE_bits_source = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_set_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_set_WIRE_1_bits_source = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_opcodes_set_interm_T = 4'h0;\t// @[Monitor.scala:765:53]\n wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] responseMap_0 = 3'h0;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_1 = 3'h0;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_0 = 3'h0;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_1 = 3'h0;\t// @[Monitor.scala:644:42]\n wire [2:0] _c_first_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [15:0] _a_size_lookup_T_5 = 16'hFF;\t// @[Monitor.scala:612:57]\n wire [15:0] _d_sizes_clr_T_3 = 16'hFF;\t// @[Monitor.scala:612:57]\n wire [15:0] _c_size_lookup_T_5 = 16'hFF;\t// @[Monitor.scala:724:57]\n wire [15:0] _d_sizes_clr_T_9 = 16'hFF;\t// @[Monitor.scala:724:57]\n wire [16:0] _a_size_lookup_T_4 = 17'hFF;\t// @[Monitor.scala:612:57]\n wire [16:0] _d_sizes_clr_T_2 = 17'hFF;\t// @[Monitor.scala:612:57]\n wire [16:0] _c_size_lookup_T_4 = 17'hFF;\t// @[Monitor.scala:724:57]\n wire [16:0] _d_sizes_clr_T_8 = 17'hFF;\t// @[Monitor.scala:724:57]\n wire [15:0] _a_size_lookup_T_3 = 16'h100;\t// @[Monitor.scala:612:51]\n wire [15:0] _d_sizes_clr_T_1 = 16'h100;\t// @[Monitor.scala:612:51]\n wire [15:0] _c_size_lookup_T_3 = 16'h100;\t// @[Monitor.scala:724:51]\n wire [15:0] _d_sizes_clr_T_7 = 16'h100;\t// @[Monitor.scala:724:51]\n wire [15:0] _a_opcode_lookup_T_5 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _d_opcodes_clr_T_3 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _c_opcode_lookup_T_5 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _d_opcodes_clr_T_9 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _a_opcode_lookup_T_4 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _d_opcodes_clr_T_2 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _c_opcode_lookup_T_4 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _d_opcodes_clr_T_8 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _a_opcode_lookup_T_3 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _d_opcodes_clr_T_1 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _c_opcode_lookup_T_3 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _d_opcodes_clr_T_7 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [131:0] _c_sizes_set_T_1 = 132'h0;\t// @[Monitor.scala:768:52]\n wire [6:0] _c_opcodes_set_T = 7'h0;\t// @[Monitor.scala:767:79]\n wire [6:0] _c_sizes_set_T = 7'h0;\t// @[Monitor.scala:768:77]\n wire [130:0] _c_opcodes_set_T_1 = 131'h0;\t// @[Monitor.scala:767:54]\n wire [4:0] _c_sizes_set_interm_T_1 = 5'h1;\t// @[Monitor.scala:766:59]\n wire [4:0] c_sizes_set_interm = 5'h0;\t// @[Monitor.scala:755:40]\n wire [4:0] _c_sizes_set_interm_T = 5'h0;\t// @[Monitor.scala:766:51]\n wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1;\t// @[Monitor.scala:765:61]\n wire [15:0] _c_set_wo_ready_T = 16'h1;\t// @[OneHot.scala:58:35]\n wire [15:0] _c_set_T = 16'h1;\t// @[OneHot.scala:58:35]\n wire [127:0] c_sizes_set = 128'h0;\t// @[Monitor.scala:741:34]\n wire [15:0] c_set = 16'h0;\t// @[Monitor.scala:738:34]\n wire [15:0] c_set_wo_ready = 16'h0;\t// @[Monitor.scala:739:34]\n wire [11:0] _c_first_beats1_decode_T_2 = 12'h0;\t// @[package.scala:243:46]\n wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF;\t// @[package.scala:243:76]\n wire [26:0] _c_first_beats1_decode_T = 27'hFFF;\t// @[package.scala:243:71]\n wire [2:0] responseMap_6 = 3'h4;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_7 = 3'h4;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_7 = 3'h4;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_6 = 3'h5;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMap_5 = 3'h2;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_5 = 3'h2;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMap_2 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_3 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_4 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_2 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_3 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_4 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [3:0] _a_size_lookup_T_2 = 4'h8;\t// @[Monitor.scala:641:117]\n wire [3:0] _d_sizes_clr_T = 4'h8;\t// @[Monitor.scala:681:48]\n wire [3:0] _c_size_lookup_T_2 = 4'h8;\t// @[Monitor.scala:750:119]\n wire [3:0] _d_sizes_clr_T_6 = 4'h8;\t// @[Monitor.scala:791:48]\n wire [3:0] _a_opcode_lookup_T_2 = 4'h4;\t// @[Monitor.scala:637:123]\n wire [3:0] _d_opcodes_clr_T = 4'h4;\t// @[Monitor.scala:680:48]\n wire [3:0] _c_opcode_lookup_T_2 = 4'h4;\t// @[Monitor.scala:749:123]\n wire [3:0] _d_opcodes_clr_T_6 = 4'h4;\t// @[Monitor.scala:790:48]\n wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0;\t// @[Misc.scala:202:34]\n wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_9 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_10 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_11 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_12 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_13 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_14 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_15 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_16 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_17 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_18 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_19 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_20 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_21 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_22 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_23 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_24 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_25 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_26 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_27 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_28 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_29 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_30 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_31 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_32 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_33 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_34 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_35 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] _source_ok_T = io_in_a_bits_source_0[3:2];\t// @[Monitor.scala:36:7]\n wire [1:0] _source_ok_T_6 = io_in_a_bits_source_0[3:2];\t// @[Monitor.scala:36:7]\n wire [1:0] _source_ok_T_12 = io_in_a_bits_source_0[3:2];\t// @[Monitor.scala:36:7]\n wire [1:0] _source_ok_T_18 = io_in_a_bits_source_0[3:2];\t// @[Monitor.scala:36:7]\n wire _source_ok_T_1 = _source_ok_T == 2'h0;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_3 = _source_ok_T_1;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_5 = _source_ok_T_3;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_0 = _source_ok_T_5;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_7 = _source_ok_T_6 == 2'h1;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_9 = _source_ok_T_7;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_11 = _source_ok_T_9;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_1 = _source_ok_T_11;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_13 = _source_ok_T_12 == 2'h2;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_15 = _source_ok_T_13;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_17 = _source_ok_T_15;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_2 = _source_ok_T_17;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_19 = &_source_ok_T_18;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_21 = _source_ok_T_19;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_23 = _source_ok_T_21;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_3 = _source_ok_T_23;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_24 = _source_ok_WIRE_0 | _source_ok_WIRE_1;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_25 = _source_ok_T_24 | _source_ok_WIRE_2;\t// @[Parameters.scala:1138:31, :1139:46]\n wire source_ok = _source_ok_T_25 | _source_ok_WIRE_3;\t// @[Parameters.scala:1138:31, :1139:46]\n wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0;\t// @[package.scala:243:71]\n wire [26:0] _is_aligned_mask_T;\t// @[package.scala:243:71]\n assign _is_aligned_mask_T = _GEN;\t// @[package.scala:243:71]\n wire [26:0] _a_first_beats1_decode_T;\t// @[package.scala:243:71]\n assign _a_first_beats1_decode_T = _GEN;\t// @[package.scala:243:71]\n wire [26:0] _a_first_beats1_decode_T_3;\t// @[package.scala:243:71]\n assign _a_first_beats1_decode_T_3 = _GEN;\t// @[package.scala:243:71]\n wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1;\t// @[package.scala:243:{46,76}]\n wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask};\t// @[package.scala:243:46]\n wire is_aligned = _is_aligned_T == 32'h0;\t// @[Edges.scala:21:{16,24}]\n wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0];\t// @[OneHot.scala:64:49]\n wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount;\t// @[OneHot.scala:64:49, :65:12]\n wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0];\t// @[OneHot.scala:65:{12,27}]\n wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1};\t// @[OneHot.scala:65:27]\n wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2;\t// @[Misc.scala:206:21]\n wire mask_sub_sub_size = mask_sizeOH[2];\t// @[Misc.scala:202:81, :209:26]\n wire mask_sub_sub_bit = io_in_a_bits_address_0[2];\t// @[Misc.scala:210:26]\n wire mask_sub_sub_1_2 = mask_sub_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire mask_sub_sub_nbit = ~mask_sub_sub_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_sub_sub_0_2 = mask_sub_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T;\t// @[Misc.scala:206:21, :215:{29,38}]\n wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1;\t// @[Misc.scala:206:21, :215:{29,38}]\n wire mask_sub_size = mask_sizeOH[1];\t// @[Misc.scala:202:81, :209:26]\n wire mask_sub_bit = io_in_a_bits_address_0[1];\t// @[Misc.scala:210:26]\n wire mask_sub_nbit = ~mask_sub_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3;\t// @[Misc.scala:215:{29,38}]\n wire mask_size = mask_sizeOH[0];\t// @[Misc.scala:202:81, :209:26]\n wire mask_bit = io_in_a_bits_address_0[0];\t// @[Misc.scala:210:26]\n wire mask_nbit = ~mask_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_eq = mask_sub_0_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T = mask_size & mask_eq;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc = mask_sub_0_1 | _mask_acc_T;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_1 = mask_sub_0_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_1 = mask_size & mask_eq_1;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_2 = mask_sub_1_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_2 = mask_size & mask_eq_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_3 = mask_sub_1_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_3 = mask_size & mask_eq_3;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_4 = mask_sub_2_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_4 = mask_size & mask_eq_4;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_5 = mask_sub_2_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_5 = mask_size & mask_eq_5;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_6 = mask_sub_3_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_6 = mask_size & mask_eq_6;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_7 = mask_sub_3_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_7 = mask_size & mask_eq_7;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7;\t// @[Misc.scala:215:{29,38}]\n wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc};\t// @[Misc.scala:215:29, :222:10]\n wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2};\t// @[Misc.scala:215:29, :222:10]\n wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo};\t// @[Misc.scala:222:10]\n wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4};\t// @[Misc.scala:215:29, :222:10]\n wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6};\t// @[Misc.scala:215:29, :222:10]\n wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo};\t// @[Misc.scala:222:10]\n wire [7:0] mask = {mask_hi, mask_lo};\t// @[Misc.scala:222:10]\n wire [1:0] uncommonBits = _uncommonBits_T[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] _source_ok_T_26 = io_in_d_bits_source_0[3:2];\t// @[Monitor.scala:36:7]\n wire [1:0] _source_ok_T_32 = io_in_d_bits_source_0[3:2];\t// @[Monitor.scala:36:7]\n wire [1:0] _source_ok_T_38 = io_in_d_bits_source_0[3:2];\t// @[Monitor.scala:36:7]\n wire [1:0] _source_ok_T_44 = io_in_d_bits_source_0[3:2];\t// @[Monitor.scala:36:7]\n wire _source_ok_T_27 = _source_ok_T_26 == 2'h0;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_29 = _source_ok_T_27;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_31 = _source_ok_T_29;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_1_0 = _source_ok_T_31;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_33 = _source_ok_T_32 == 2'h1;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_35 = _source_ok_T_33;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_37 = _source_ok_T_35;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_1_1 = _source_ok_T_37;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_39 = _source_ok_T_38 == 2'h2;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_41 = _source_ok_T_39;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_43 = _source_ok_T_41;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_1_2 = _source_ok_T_43;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_45 = &_source_ok_T_44;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_47 = _source_ok_T_45;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_49 = _source_ok_T_47;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_1_3 = _source_ok_T_49;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_50 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_1_2;\t// @[Parameters.scala:1138:31, :1139:46]\n wire source_ok_1 = _source_ok_T_51 | _source_ok_WIRE_1_3;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _T_1602 = io_in_a_ready_0 & io_in_a_valid_0;\t// @[Decoupled.scala:51:35]\n wire _a_first_T;\t// @[Decoupled.scala:51:35]\n assign _a_first_T = _T_1602;\t// @[Decoupled.scala:51:35]\n wire _a_first_T_1;\t// @[Decoupled.scala:51:35]\n assign _a_first_T_1 = _T_1602;\t// @[Decoupled.scala:51:35]\n wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3];\t// @[package.scala:243:46]\n wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2];\t// @[Monitor.scala:36:7]\n wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2];\t// @[Monitor.scala:36:7]\n wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T;\t// @[Edges.scala:92:{28,37}]\n wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0;\t// @[Edges.scala:92:28, :220:59, :221:14]\n reg [8:0] a_first_counter;\t// @[Edges.scala:229:27]\n wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0];\t// @[Edges.scala:230:28]\n wire a_first = a_first_counter == 9'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_last_T = a_first_counter == 9'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _a_first_last_T_1 = a_first_beats1 == 9'h0;\t// @[Edges.scala:221:14, :232:43]\n wire a_first_last = _a_first_last_T | _a_first_last_T_1;\t// @[Edges.scala:232:{25,33,43}]\n wire a_first_done = a_first_last & _a_first_T;\t// @[Decoupled.scala:51:35]\n wire [8:0] _a_first_count_T = ~a_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n reg [2:0] opcode;\t// @[Monitor.scala:387:22]\n reg [2:0] param;\t// @[Monitor.scala:388:22]\n reg [3:0] size;\t// @[Monitor.scala:389:22]\n reg [3:0] source;\t// @[Monitor.scala:390:22]\n reg [31:0] address;\t// @[Monitor.scala:391:22]\n wire _T_1675 = io_in_d_ready_0 & io_in_d_valid_0;\t// @[Decoupled.scala:51:35]\n wire _d_first_T;\t// @[Decoupled.scala:51:35]\n assign _d_first_T = _T_1675;\t// @[Decoupled.scala:51:35]\n wire _d_first_T_1;\t// @[Decoupled.scala:51:35]\n assign _d_first_T_1 = _T_1675;\t// @[Decoupled.scala:51:35]\n wire _d_first_T_2;\t// @[Decoupled.scala:51:35]\n assign _d_first_T_2 = _T_1675;\t// @[Decoupled.scala:51:35]\n wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0;\t// @[package.scala:243:71]\n wire [26:0] _d_first_beats1_decode_T;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T = _GEN_0;\t// @[package.scala:243:71]\n wire [26:0] _d_first_beats1_decode_T_3;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T_3 = _GEN_0;\t// @[package.scala:243:71]\n wire [26:0] _d_first_beats1_decode_T_6;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T_6 = _GEN_0;\t// @[package.scala:243:71]\n wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3];\t// @[package.scala:243:46]\n wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [8:0] d_first_counter;\t// @[Edges.scala:229:27]\n wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0];\t// @[Edges.scala:230:28]\n wire d_first = d_first_counter == 9'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T = d_first_counter == 9'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_1 = d_first_beats1 == 9'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last = _d_first_last_T | _d_first_last_T_1;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done = d_first_last & _d_first_T;\t// @[Decoupled.scala:51:35]\n wire [8:0] _d_first_count_T = ~d_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n reg [2:0] opcode_1;\t// @[Monitor.scala:538:22]\n reg [1:0] param_1;\t// @[Monitor.scala:539:22]\n reg [3:0] size_1;\t// @[Monitor.scala:540:22]\n reg [3:0] source_1;\t// @[Monitor.scala:541:22]\n reg [2:0] sink;\t// @[Monitor.scala:542:22]\n reg denied;\t// @[Monitor.scala:543:22]\n reg [15:0] inflight;\t// @[Monitor.scala:614:27]\n reg [63:0] inflight_opcodes;\t// @[Monitor.scala:616:35]\n reg [127:0] inflight_sizes;\t// @[Monitor.scala:618:33]\n wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4;\t// @[package.scala:243:{46,76}]\n wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3];\t// @[package.scala:243:46]\n wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1;\t// @[Edges.scala:92:{28,37}]\n wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0;\t// @[Edges.scala:92:28, :220:59, :221:14]\n reg [8:0] a_first_counter_1;\t// @[Edges.scala:229:27]\n wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0];\t// @[Edges.scala:230:28]\n wire a_first_1 = a_first_counter_1 == 9'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_last_T_2 = a_first_counter_1 == 9'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0;\t// @[Edges.scala:221:14, :232:43]\n wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3;\t// @[Edges.scala:232:{25,33,43}]\n wire a_first_done_1 = a_first_last_1 & _a_first_T_1;\t// @[Decoupled.scala:51:35]\n wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4;\t// @[package.scala:243:{46,76}]\n wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3];\t// @[package.scala:243:46]\n wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [8:0] d_first_counter_1;\t// @[Edges.scala:229:27]\n wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0];\t// @[Edges.scala:230:28]\n wire d_first_1 = d_first_counter_1 == 9'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T_2 = d_first_counter_1 == 9'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done_1 = d_first_last_1 & _d_first_T_1;\t// @[Decoupled.scala:51:35]\n wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire [15:0] a_set;\t// @[Monitor.scala:626:34]\n wire [15:0] a_set_wo_ready;\t// @[Monitor.scala:627:34]\n wire [63:0] a_opcodes_set;\t// @[Monitor.scala:630:33]\n wire [127:0] a_sizes_set;\t// @[Monitor.scala:632:31]\n wire [2:0] a_opcode_lookup;\t// @[Monitor.scala:635:35]\n wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0};\t// @[Monitor.scala:36:7, :637:69]\n wire [6:0] _a_opcode_lookup_T;\t// @[Monitor.scala:637:69]\n assign _a_opcode_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69]\n wire [6:0] _d_opcodes_clr_T_4;\t// @[Monitor.scala:680:101]\n assign _d_opcodes_clr_T_4 = _GEN_1;\t// @[Monitor.scala:637:69, :680:101]\n wire [6:0] _c_opcode_lookup_T;\t// @[Monitor.scala:749:69]\n assign _c_opcode_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69, :749:69]\n wire [6:0] _d_opcodes_clr_T_10;\t// @[Monitor.scala:790:101]\n assign _d_opcodes_clr_T_10 = _GEN_1;\t// @[Monitor.scala:637:69, :790:101]\n wire [63:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T;\t// @[Monitor.scala:616:35, :637:{44,69}]\n wire [63:0] _a_opcode_lookup_T_6 = {60'h0, _a_opcode_lookup_T_1[3:0]};\t// @[Monitor.scala:637:{44,97}]\n wire [63:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[63:1]};\t// @[Monitor.scala:637:{97,152}]\n assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0];\t// @[Monitor.scala:635:35, :637:{21,152}]\n wire [7:0] a_size_lookup;\t// @[Monitor.scala:639:33]\n wire [6:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0};\t// @[Monitor.scala:36:7, :641:65]\n wire [6:0] _a_size_lookup_T;\t// @[Monitor.scala:641:65]\n assign _a_size_lookup_T = _GEN_2;\t// @[Monitor.scala:641:65]\n wire [6:0] _d_sizes_clr_T_4;\t// @[Monitor.scala:681:99]\n assign _d_sizes_clr_T_4 = _GEN_2;\t// @[Monitor.scala:641:65, :681:99]\n wire [6:0] _c_size_lookup_T;\t// @[Monitor.scala:750:67]\n assign _c_size_lookup_T = _GEN_2;\t// @[Monitor.scala:641:65, :750:67]\n wire [6:0] _d_sizes_clr_T_10;\t// @[Monitor.scala:791:99]\n assign _d_sizes_clr_T_10 = _GEN_2;\t// @[Monitor.scala:641:65, :791:99]\n wire [127:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T;\t// @[Monitor.scala:618:33, :641:{40,65}]\n wire [127:0] _a_size_lookup_T_6 = {120'h0, _a_size_lookup_T_1[7:0]};\t// @[Monitor.scala:641:{40,91}]\n wire [127:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[127:1]};\t// @[Monitor.scala:641:{91,144}]\n assign a_size_lookup = _a_size_lookup_T_7[7:0];\t// @[Monitor.scala:639:33, :641:{19,144}]\n wire [3:0] a_opcodes_set_interm;\t// @[Monitor.scala:646:40]\n wire [4:0] a_sizes_set_interm;\t// @[Monitor.scala:648:38]\n wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1;\t// @[Monitor.scala:36:7, :651:26, :684:44]\n wire [15:0] _GEN_3 = {12'h0, io_in_a_bits_source_0};\t// @[OneHot.scala:58:35]\n wire [15:0] _GEN_4 = 16'h1 << _GEN_3;\t// @[OneHot.scala:58:35]\n wire [15:0] _a_set_wo_ready_T;\t// @[OneHot.scala:58:35]\n assign _a_set_wo_ready_T = _GEN_4;\t// @[OneHot.scala:58:35]\n wire [15:0] _a_set_T;\t// @[OneHot.scala:58:35]\n assign _a_set_T = _GEN_4;\t// @[OneHot.scala:58:35]\n assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 16'h0;\t// @[OneHot.scala:58:35]\n wire _T_1528 = _T_1602 & a_first_1;\t// @[Decoupled.scala:51:35]\n assign a_set = _T_1528 ? _a_set_T : 16'h0;\t// @[OneHot.scala:58:35]\n wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0};\t// @[Monitor.scala:36:7, :657:53]\n wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1};\t// @[Monitor.scala:657:{53,61}]\n assign a_opcodes_set_interm = _T_1528 ? _a_opcodes_set_interm_T_1 : 4'h0;\t// @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]\n wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0};\t// @[Monitor.scala:36:7, :658:51]\n wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1};\t// @[Monitor.scala:658:{51,59}]\n assign a_sizes_set_interm = _T_1528 ? _a_sizes_set_interm_T_1 : 5'h0;\t// @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]\n wire [6:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0};\t// @[Monitor.scala:36:7, :659:79]\n wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T;\t// @[Monitor.scala:646:40, :659:{54,79}]\n assign a_opcodes_set = _T_1528 ? _a_opcodes_set_T_1[63:0] : 64'h0;\t// @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]\n wire [6:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0};\t// @[Monitor.scala:36:7, :660:77]\n wire [131:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T;\t// @[Monitor.scala:648:38, :659:54, :660:{52,77}]\n assign a_sizes_set = _T_1528 ? _a_sizes_set_T_1[127:0] : 128'h0;\t// @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]\n wire [15:0] d_clr;\t// @[Monitor.scala:664:34]\n wire [15:0] d_clr_wo_ready;\t// @[Monitor.scala:665:34]\n wire [63:0] d_opcodes_clr;\t// @[Monitor.scala:668:33]\n wire [127:0] d_sizes_clr;\t// @[Monitor.scala:670:31]\n wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6;\t// @[Monitor.scala:36:7, :673:46]\n wire d_release_ack;\t// @[Monitor.scala:673:46]\n assign d_release_ack = _GEN_5;\t// @[Monitor.scala:673:46]\n wire d_release_ack_1;\t// @[Monitor.scala:783:46]\n assign d_release_ack_1 = _GEN_5;\t// @[Monitor.scala:673:46, :783:46]\n wire _T_1574 = io_in_d_valid_0 & d_first_1;\t// @[Monitor.scala:36:7, :674:26]\n wire [15:0] _GEN_6 = {12'h0, io_in_d_bits_source_0};\t// @[OneHot.scala:58:35]\n wire [15:0] _GEN_7 = 16'h1 << _GEN_6;\t// @[OneHot.scala:58:35]\n wire [15:0] _d_clr_wo_ready_T;\t// @[OneHot.scala:58:35]\n assign _d_clr_wo_ready_T = _GEN_7;\t// @[OneHot.scala:58:35]\n wire [15:0] _d_clr_T;\t// @[OneHot.scala:58:35]\n assign _d_clr_T = _GEN_7;\t// @[OneHot.scala:58:35]\n wire [15:0] _d_clr_wo_ready_T_1;\t// @[OneHot.scala:58:35]\n assign _d_clr_wo_ready_T_1 = _GEN_7;\t// @[OneHot.scala:58:35]\n wire [15:0] _d_clr_T_1;\t// @[OneHot.scala:58:35]\n assign _d_clr_T_1 = _GEN_7;\t// @[OneHot.scala:58:35]\n assign d_clr_wo_ready = _T_1574 & ~d_release_ack ? _d_clr_wo_ready_T : 16'h0;\t// @[OneHot.scala:58:35]\n wire _T_1543 = _T_1675 & d_first_1 & ~d_release_ack;\t// @[Decoupled.scala:51:35]\n assign d_clr = _T_1543 ? _d_clr_T : 16'h0;\t// @[OneHot.scala:58:35]\n wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4;\t// @[Monitor.scala:680:{76,101}]\n assign d_opcodes_clr = _T_1543 ? _d_opcodes_clr_T_5[63:0] : 64'h0;\t// @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]\n wire [142:0] _d_sizes_clr_T_5 = 143'hFF << _d_sizes_clr_T_4;\t// @[Monitor.scala:681:{74,99}]\n assign d_sizes_clr = _T_1543 ? _d_sizes_clr_T_5[127:0] : 128'h0;\t// @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]\n wire _same_cycle_resp_T_1 = _same_cycle_resp_T;\t// @[Monitor.scala:684:{44,55}]\n wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0;\t// @[Monitor.scala:36:7, :684:113]\n wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2;\t// @[Monitor.scala:684:{55,88,113}]\n wire [15:0] _inflight_T = inflight | a_set;\t// @[Monitor.scala:614:27, :626:34, :705:27]\n wire [15:0] _inflight_T_1 = ~d_clr;\t// @[Monitor.scala:664:34, :705:38]\n wire [15:0] _inflight_T_2 = _inflight_T & _inflight_T_1;\t// @[Monitor.scala:705:{27,36,38}]\n wire [63:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set;\t// @[Monitor.scala:616:35, :630:33, :706:43]\n wire [63:0] _inflight_opcodes_T_1 = ~d_opcodes_clr;\t// @[Monitor.scala:668:33, :706:62]\n wire [63:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1;\t// @[Monitor.scala:706:{43,60,62}]\n wire [127:0] _inflight_sizes_T = inflight_sizes | a_sizes_set;\t// @[Monitor.scala:618:33, :632:31, :707:39]\n wire [127:0] _inflight_sizes_T_1 = ~d_sizes_clr;\t// @[Monitor.scala:670:31, :707:56]\n wire [127:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1;\t// @[Monitor.scala:707:{39,54,56}]\n reg [31:0] watchdog;\t// @[Monitor.scala:709:27]\n wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1;\t// @[Monitor.scala:709:27, :714:26]\n wire [31:0] _watchdog_T_1 = _watchdog_T[31:0];\t// @[Monitor.scala:714:26]\n reg [15:0] inflight_1;\t// @[Monitor.scala:726:35]\n wire [15:0] _inflight_T_3 = inflight_1;\t// @[Monitor.scala:726:35, :814:35]\n reg [63:0] inflight_opcodes_1;\t// @[Monitor.scala:727:35]\n wire [63:0] _inflight_opcodes_T_3 = inflight_opcodes_1;\t// @[Monitor.scala:727:35, :815:43]\n reg [127:0] inflight_sizes_1;\t// @[Monitor.scala:728:35]\n wire [127:0] _inflight_sizes_T_3 = inflight_sizes_1;\t// @[Monitor.scala:728:35, :816:41]\n wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7;\t// @[package.scala:243:{46,76}]\n wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3];\t// @[package.scala:243:46]\n wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [8:0] d_first_counter_2;\t// @[Edges.scala:229:27]\n wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0];\t// @[Edges.scala:230:28]\n wire d_first_2 = d_first_counter_2 == 9'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T_4 = d_first_counter_2 == 9'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done_2 = d_first_last_2 & _d_first_T_2;\t// @[Decoupled.scala:51:35]\n wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2;\t// @[Edges.scala:230:28, :234:27]\n wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire [3:0] c_opcode_lookup;\t// @[Monitor.scala:747:35]\n wire [7:0] c_size_lookup;\t// @[Monitor.scala:748:35]\n wire [63:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T;\t// @[Monitor.scala:727:35, :749:{44,69}]\n wire [63:0] _c_opcode_lookup_T_6 = {60'h0, _c_opcode_lookup_T_1[3:0]};\t// @[Monitor.scala:749:{44,97}]\n wire [63:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[63:1]};\t// @[Monitor.scala:749:{97,152}]\n assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0];\t// @[Monitor.scala:747:35, :749:{21,152}]\n wire [127:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T;\t// @[Monitor.scala:728:35, :750:{42,67}]\n wire [127:0] _c_size_lookup_T_6 = {120'h0, _c_size_lookup_T_1[7:0]};\t// @[Monitor.scala:750:{42,93}]\n wire [127:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[127:1]};\t// @[Monitor.scala:750:{93,146}]\n assign c_size_lookup = _c_size_lookup_T_7[7:0];\t// @[Monitor.scala:748:35, :750:{21,146}]\n wire [15:0] d_clr_1;\t// @[Monitor.scala:774:34]\n wire [15:0] d_clr_wo_ready_1;\t// @[Monitor.scala:775:34]\n wire [63:0] d_opcodes_clr_1;\t// @[Monitor.scala:776:34]\n wire [127:0] d_sizes_clr_1;\t// @[Monitor.scala:777:34]\n wire _T_1646 = io_in_d_valid_0 & d_first_2;\t// @[Monitor.scala:36:7, :784:26]\n assign d_clr_wo_ready_1 = _T_1646 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 16'h0;\t// @[OneHot.scala:58:35]\n wire _T_1628 = _T_1675 & d_first_2 & d_release_ack_1;\t// @[Decoupled.scala:51:35]\n assign d_clr_1 = _T_1628 ? _d_clr_T_1 : 16'h0;\t// @[OneHot.scala:58:35]\n wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10;\t// @[Monitor.scala:790:{76,101}]\n assign d_opcodes_clr_1 = _T_1628 ? _d_opcodes_clr_T_11[63:0] : 64'h0;\t// @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]\n wire [142:0] _d_sizes_clr_T_11 = 143'hFF << _d_sizes_clr_T_10;\t// @[Monitor.scala:791:{74,99}]\n assign d_sizes_clr_1 = _T_1628 ? _d_sizes_clr_T_11[127:0] : 128'h0;\t// @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]\n wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0;\t// @[Monitor.scala:36:7, :795:113]\n wire [15:0] _inflight_T_4 = ~d_clr_1;\t// @[Monitor.scala:774:34, :814:46]\n wire [15:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4;\t// @[Monitor.scala:814:{35,44,46}]\n wire [63:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1;\t// @[Monitor.scala:776:34, :815:62]\n wire [63:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4;\t// @[Monitor.scala:815:{43,60,62}]\n wire [127:0] _inflight_sizes_T_4 = ~d_sizes_clr_1;\t// @[Monitor.scala:777:34, :816:58]\n wire [127:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4;\t// @[Monitor.scala:816:{41,56,58}]\n reg [31:0] watchdog_1;\t// @[Monitor.scala:818:27]"}}},{"rowIdx":34383,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module DivUnit_1 : \n input clock : Clock \n input reset : Reset \n output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, pred_data : UInt<1>, kill : UInt<1>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, predicated : UInt<1>, data : UInt<64>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}, addr : UInt<40>, mxcpt : { valid : UInt<1>, bits : UInt<25>}, sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}}}, flip brupdate : { b1 : { resolve_mask : UInt<8>, mispredict_mask : UInt<8>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, bypass : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}[0]} \n\n\n connect io.resp.valid, UInt<1>(0h0) \n invalidate io.resp.bits.sfence.bits.hg \n invalidate io.resp.bits.sfence.bits.hv \n invalidate io.resp.bits.sfence.bits.asid \n invalidate io.resp.bits.sfence.bits.addr \n invalidate io.resp.bits.sfence.bits.rs2 \n invalidate io.resp.bits.sfence.bits.rs1 \n invalidate io.resp.bits.sfence.valid \n invalidate io.resp.bits.mxcpt.bits \n invalidate io.resp.bits.mxcpt.valid \n invalidate io.resp.bits.addr \n invalidate io.resp.bits.fflags.bits.flags \n invalidate io.resp.bits.fflags.bits.uop.debug_tsrc \n invalidate io.resp.bits.fflags.bits.uop.debug_fsrc \n invalidate io.resp.bits.fflags.bits.uop.bp_xcpt_if \n invalidate io.resp.bits.fflags.bits.uop.bp_debug_if \n invalidate io.resp.bits.fflags.bits.uop.xcpt_ma_if \n invalidate io.resp.bits.fflags.bits.uop.xcpt_ae_if \n invalidate io.resp.bits.fflags.bits.uop.xcpt_pf_if \n invalidate io.resp.bits.fflags.bits.uop.fp_single \n invalidate io.resp.bits.fflags.bits.uop.fp_val \n invalidate io.resp.bits.fflags.bits.uop.frs3_en \n invalidate io.resp.bits.fflags.bits.uop.lrs2_rtype \n invalidate io.resp.bits.fflags.bits.uop.lrs1_rtype \n invalidate io.resp.bits.fflags.bits.uop.dst_rtype \n invalidate io.resp.bits.fflags.bits.uop.ldst_val \n invalidate io.resp.bits.fflags.bits.uop.lrs3 \n invalidate io.resp.bits.fflags.bits.uop.lrs2 \n invalidate io.resp.bits.fflags.bits.uop.lrs1 \n invalidate io.resp.bits.fflags.bits.uop.ldst \n invalidate io.resp.bits.fflags.bits.uop.ldst_is_rs1 \n invalidate io.resp.bits.fflags.bits.uop.flush_on_commit \n invalidate io.resp.bits.fflags.bits.uop.is_unique \n invalidate io.resp.bits.fflags.bits.uop.is_sys_pc2epc \n invalidate io.resp.bits.fflags.bits.uop.uses_stq \n invalidate io.resp.bits.fflags.bits.uop.uses_ldq \n invalidate io.resp.bits.fflags.bits.uop.is_amo \n invalidate io.resp.bits.fflags.bits.uop.is_fencei \n invalidate io.resp.bits.fflags.bits.uop.is_fence \n invalidate io.resp.bits.fflags.bits.uop.mem_signed \n invalidate io.resp.bits.fflags.bits.uop.mem_size \n invalidate io.resp.bits.fflags.bits.uop.mem_cmd \n invalidate io.resp.bits.fflags.bits.uop.bypassable \n invalidate io.resp.bits.fflags.bits.uop.exc_cause \n invalidate io.resp.bits.fflags.bits.uop.exception \n invalidate io.resp.bits.fflags.bits.uop.stale_pdst \n invalidate io.resp.bits.fflags.bits.uop.ppred_busy \n invalidate io.resp.bits.fflags.bits.uop.prs3_busy \n invalidate io.resp.bits.fflags.bits.uop.prs2_busy \n invalidate io.resp.bits.fflags.bits.uop.prs1_busy \n invalidate io.resp.bits.fflags.bits.uop.ppred \n invalidate io.resp.bits.fflags.bits.uop.prs3 \n invalidate io.resp.bits.fflags.bits.uop.prs2 \n invalidate io.resp.bits.fflags.bits.uop.prs1 \n invalidate io.resp.bits.fflags.bits.uop.pdst \n invalidate io.resp.bits.fflags.bits.uop.rxq_idx \n invalidate io.resp.bits.fflags.bits.uop.stq_idx \n invalidate io.resp.bits.fflags.bits.uop.ldq_idx \n invalidate io.resp.bits.fflags.bits.uop.rob_idx \n invalidate io.resp.bits.fflags.bits.uop.csr_addr \n invalidate io.resp.bits.fflags.bits.uop.imm_packed \n invalidate io.resp.bits.fflags.bits.uop.taken \n invalidate io.resp.bits.fflags.bits.uop.pc_lob \n invalidate io.resp.bits.fflags.bits.uop.edge_inst \n invalidate io.resp.bits.fflags.bits.uop.ftq_idx \n invalidate io.resp.bits.fflags.bits.uop.br_tag \n invalidate io.resp.bits.fflags.bits.uop.br_mask \n invalidate io.resp.bits.fflags.bits.uop.is_sfb \n invalidate io.resp.bits.fflags.bits.uop.is_jal \n invalidate io.resp.bits.fflags.bits.uop.is_jalr \n invalidate io.resp.bits.fflags.bits.uop.is_br \n invalidate io.resp.bits.fflags.bits.uop.iw_p2_poisoned \n invalidate io.resp.bits.fflags.bits.uop.iw_p1_poisoned \n invalidate io.resp.bits.fflags.bits.uop.iw_state \n invalidate io.resp.bits.fflags.bits.uop.ctrl.is_std \n invalidate io.resp.bits.fflags.bits.uop.ctrl.is_sta \n invalidate io.resp.bits.fflags.bits.uop.ctrl.is_load \n invalidate io.resp.bits.fflags.bits.uop.ctrl.csr_cmd \n invalidate io.resp.bits.fflags.bits.uop.ctrl.fcn_dw \n invalidate io.resp.bits.fflags.bits.uop.ctrl.op_fcn \n invalidate io.resp.bits.fflags.bits.uop.ctrl.imm_sel \n invalidate io.resp.bits.fflags.bits.uop.ctrl.op2_sel \n invalidate io.resp.bits.fflags.bits.uop.ctrl.op1_sel \n invalidate io.resp.bits.fflags.bits.uop.ctrl.br_type \n invalidate io.resp.bits.fflags.bits.uop.fu_code \n invalidate io.resp.bits.fflags.bits.uop.iq_type \n invalidate io.resp.bits.fflags.bits.uop.debug_pc \n invalidate io.resp.bits.fflags.bits.uop.is_rvc \n invalidate io.resp.bits.fflags.bits.uop.debug_inst \n invalidate io.resp.bits.fflags.bits.uop.inst \n invalidate io.resp.bits.fflags.bits.uop.uopc \n invalidate io.resp.bits.fflags.valid \n invalidate io.resp.bits.data \n invalidate io.resp.bits.predicated \n invalidate io.resp.bits.uop.debug_tsrc \n invalidate io.resp.bits.uop.debug_fsrc \n invalidate io.resp.bits.uop.bp_xcpt_if \n invalidate io.resp.bits.uop.bp_debug_if \n invalidate io.resp.bits.uop.xcpt_ma_if \n invalidate io.resp.bits.uop.xcpt_ae_if \n invalidate io.resp.bits.uop.xcpt_pf_if \n invalidate io.resp.bits.uop.fp_single \n invalidate io.resp.bits.uop.fp_val \n invalidate io.resp.bits.uop.frs3_en \n invalidate io.resp.bits.uop.lrs2_rtype \n invalidate io.resp.bits.uop.lrs1_rtype \n invalidate io.resp.bits.uop.dst_rtype \n invalidate io.resp.bits.uop.ldst_val \n invalidate io.resp.bits.uop.lrs3 \n invalidate io.resp.bits.uop.lrs2 \n invalidate io.resp.bits.uop.lrs1 \n invalidate io.resp.bits.uop.ldst \n invalidate io.resp.bits.uop.ldst_is_rs1 \n invalidate io.resp.bits.uop.flush_on_commit \n invalidate io.resp.bits.uop.is_unique \n invalidate io.resp.bits.uop.is_sys_pc2epc \n invalidate io.resp.bits.uop.uses_stq \n invalidate io.resp.bits.uop.uses_ldq \n invalidate io.resp.bits.uop.is_amo \n invalidate io.resp.bits.uop.is_fencei \n invalidate io.resp.bits.uop.is_fence \n invalidate io.resp.bits.uop.mem_signed \n invalidate io.resp.bits.uop.mem_size \n invalidate io.resp.bits.uop.mem_cmd \n invalidate io.resp.bits.uop.bypassable \n invalidate io.resp.bits.uop.exc_cause \n invalidate io.resp.bits.uop.exception \n invalidate io.resp.bits.uop.stale_pdst \n invalidate io.resp.bits.uop.ppred_busy \n invalidate io.resp.bits.uop.prs3_busy \n invalidate io.resp.bits.uop.prs2_busy \n invalidate io.resp.bits.uop.prs1_busy \n invalidate io.resp.bits.uop.ppred \n invalidate io.resp.bits.uop.prs3 \n invalidate io.resp.bits.uop.prs2 \n invalidate io.resp.bits.uop.prs1 \n invalidate io.resp.bits.uop.pdst \n invalidate io.resp.bits.uop.rxq_idx \n invalidate io.resp.bits.uop.stq_idx \n invalidate io.resp.bits.uop.ldq_idx \n invalidate io.resp.bits.uop.rob_idx \n invalidate io.resp.bits.uop.csr_addr \n invalidate io.resp.bits.uop.imm_packed \n invalidate io.resp.bits.uop.taken \n invalidate io.resp.bits.uop.pc_lob \n invalidate io.resp.bits.uop.edge_inst \n invalidate io.resp.bits.uop.ftq_idx \n invalidate io.resp.bits.uop.br_tag \n invalidate io.resp.bits.uop.br_mask \n invalidate io.resp.bits.uop.is_sfb \n invalidate io.resp.bits.uop.is_jal \n invalidate io.resp.bits.uop.is_jalr \n invalidate io.resp.bits.uop.is_br \n invalidate io.resp.bits.uop.iw_p2_poisoned \n invalidate io.resp.bits.uop.iw_p1_poisoned \n invalidate io.resp.bits.uop.iw_state \n invalidate io.resp.bits.uop.ctrl.is_std \n invalidate io.resp.bits.uop.ctrl.is_sta \n invalidate io.resp.bits.uop.ctrl.is_load \n invalidate io.resp.bits.uop.ctrl.csr_cmd \n invalidate io.resp.bits.uop.ctrl.fcn_dw \n invalidate io.resp.bits.uop.ctrl.op_fcn \n invalidate io.resp.bits.uop.ctrl.imm_sel \n invalidate io.resp.bits.uop.ctrl.op2_sel \n invalidate io.resp.bits.uop.ctrl.op1_sel \n invalidate io.resp.bits.uop.ctrl.br_type \n invalidate io.resp.bits.uop.fu_code \n invalidate io.resp.bits.uop.iq_type \n invalidate io.resp.bits.uop.debug_pc \n invalidate io.resp.bits.uop.is_rvc \n invalidate io.resp.bits.uop.debug_inst \n invalidate io.resp.bits.uop.inst \n invalidate io.resp.bits.uop.uopc \n reg r_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock \n wire do_kill : UInt<1> \n connect do_kill, io.req.bits.kill \n node _T = and(io.req.ready, io.req.valid) \n when _T : \n node _do_kill_T = and(io.brupdate.b1.mispredict_mask, io.req.bits.uop.br_mask) \n node _do_kill_T_1 = neq(_do_kill_T, UInt<1>(0h0)) \n node _do_kill_T_2 = or(_do_kill_T_1, io.req.bits.kill) \n connect do_kill, _do_kill_T_2 \n connect r_uop, io.req.bits.uop \n node _r_uop_br_mask_T = not(io.brupdate.b1.resolve_mask) \n node _r_uop_br_mask_T_1 = and(io.req.bits.uop.br_mask, _r_uop_br_mask_T) \n connect r_uop.br_mask, _r_uop_br_mask_T_1 \n else :\n\n node _do_kill_T_3 = and(io.brupdate.b1.mispredict_mask, r_uop.br_mask) \n node _do_kill_T_4 = neq(_do_kill_T_3, UInt<1>(0h0)) \n node _do_kill_T_5 = or(_do_kill_T_4, io.req.bits.kill) \n connect do_kill, _do_kill_T_5 \n node _r_uop_br_mask_T_2 = not(io.brupdate.b1.resolve_mask) \n node _r_uop_br_mask_T_3 = and(r_uop.br_mask, _r_uop_br_mask_T_2) \n connect r_uop.br_mask, _r_uop_br_mask_T_3 \n connect io.resp.bits.uop, r_uop \n inst div of MulDiv_1 \n connect div.clock, clock\n\n connect div.reset, reset\n\n node _div_io_req_valid_T = eq(do_kill, UInt<1>(0h0)) \n node _div_io_req_valid_T_1 = and(io.req.valid, _div_io_req_valid_T) \n connect div.io.req.valid, _div_io_req_valid_T_1 \n connect div.io.req.bits.dw, io.req.bits.uop.ctrl.fcn_dw \n connect div.io.req.bits.fn, io.req.bits.uop.ctrl.op_fcn \n connect div.io.req.bits.in1, io.req.bits.rs1_data \n connect div.io.req.bits.in2, io.req.bits.rs2_data \n invalidate div.io.req.bits.tag \n connect io.req.ready, div.io.req.ready \n connect div.io.kill, do_kill \n node _io_resp_valid_T = eq(do_kill, UInt<1>(0h0)) \n node _io_resp_valid_T_1 = and(div.io.resp.valid, _io_resp_valid_T) \n connect io.resp.valid, _io_resp_valid_T_1 \n connect div.io.resp.ready, io.resp.ready \n connect io.resp.bits.data, div.io.resp.bits.data"},"response":{"kind":"string","value":"module DivUnit_1(\t// @[functional-unit.scala:676:7]\n input clock,\t// @[functional-unit.scala:676:7]\n input reset,\t// @[functional-unit.scala:676:7]\n output io_req_ready,\t// @[functional-unit.scala:168:14]\n input io_req_valid,\t// @[functional-unit.scala:168:14]\n input [6:0] io_req_bits_uop_uopc,\t// @[functional-unit.scala:168:14]\n input [31:0] io_req_bits_uop_inst,\t// @[functional-unit.scala:168:14]\n input [31:0] io_req_bits_uop_debug_inst,\t// @[functional-unit.scala:168:14]\n input io_req_bits_uop_is_rvc,\t// @[functional-unit.scala:168:14]\n input [39:0] io_req_bits_uop_debug_pc,\t// @[functional-unit.scala:168:14]\n input [2:0] io_req_bits_uop_iq_type,\t// @[functional-unit.scala:168:14]\n input [9:0] io_req_bits_uop_fu_code,\t// @[functional-unit.scala:168:14]\n input [3:0] io_req_bits_uop_ctrl_br_type,\t// @[functional-unit.scala:168:14]\n input [1:0] io_req_bits_uop_ctrl_op1_sel,\t// @[functional-unit.scala:168:14]\n input [2:0] io_req_bits_uop_ctrl_op2_sel,\t// @[functional-unit.scala:168:14]\n input [2:0] io_req_bits_uop_ctrl_imm_sel,\t// @[functional-unit.scala:168:14]\n input [4:0] io_req_bits_uop_ctrl_op_fcn,\t// @[functional-unit.scala:168:14]\n input io_req_bits_uop_ctrl_fcn_dw,\t// @[functional-unit.scala:168:14]\n input [2:0] io_req_bits_uop_ctrl_csr_cmd,\t// @[functional-unit.scala:168:14]\n input io_req_bits_uop_ctrl_is_load,\t// @[functional-unit.scala:168:14]\n input io_req_bits_uop_ctrl_is_sta,\t// @[functional-unit.scala:168:14]\n input io_req_bits_uop_ctrl_is_std,\t// @[functional-unit.scala:168:14]\n input [1:0] io_req_bits_uop_iw_state,\t// @[functional-unit.scala:168:14]\n input io_req_bits_uop_iw_p1_poisoned,\t// @[functional-unit.scala:168:14]\n input io_req_bits_uop_iw_p2_poisoned,\t// @[functional-unit.scala:168:14]\n input io_req_bits_uop_is_br,\t// @[functional-unit.scala:168:14]\n input io_req_bits_uop_is_jalr,\t// @[functional-unit.scala:168:14]\n input io_req_bits_uop_is_jal,\t// @[functional-unit.scala:168:14]\n input io_req_bits_uop_is_sfb,\t// @[functional-unit.scala:168:14]\n input [7:0] io_req_bits_uop_br_mask,\t// @[functional-unit.scala:168:14]\n input [2:0] io_req_bits_uop_br_tag,\t// @[functional-unit.scala:168:14]\n input [3:0] io_req_bits_uop_ftq_idx,\t// @[functional-unit.scala:168:14]\n input io_req_bits_uop_edge_inst,\t// @[functional-unit.scala:168:14]\n input [5:0] io_req_bits_uop_pc_lob,\t// @[functional-unit.scala:168:14]\n input io_req_bits_uop_taken,\t// @[functional-unit.scala:168:14]\n input [19:0] io_req_bits_uop_imm_packed,\t// @[functional-unit.scala:168:14]\n input [11:0] io_req_bits_uop_csr_addr,\t// @[functional-unit.scala:168:14]\n input [4:0] io_req_bits_uop_rob_idx,\t// @[functional-unit.scala:168:14]\n input [2:0] io_req_bits_uop_ldq_idx,\t// @[functional-unit.scala:168:14]\n input [2:0] io_req_bits_uop_stq_idx,\t// @[functional-unit.scala:168:14]\n input [1:0] io_req_bits_uop_rxq_idx,\t// @[functional-unit.scala:168:14]\n input [5:0] io_req_bits_uop_pdst,\t// @[functional-unit.scala:168:14]\n input [5:0] io_req_bits_uop_prs1,\t// @[functional-unit.scala:168:14]\n input [5:0] io_req_bits_uop_prs2,\t// @[functional-unit.scala:168:14]\n input [5:0] io_req_bits_uop_prs3,\t// @[functional-unit.scala:168:14]\n input [3:0] io_req_bits_uop_ppred,\t// @[functional-unit.scala:168:14]\n input io_req_bits_uop_prs1_busy,\t// @[functional-unit.scala:168:14]\n input io_req_bits_uop_prs2_busy,\t// @[functional-unit.scala:168:14]\n input io_req_bits_uop_prs3_busy,\t// @[functional-unit.scala:168:14]\n input io_req_bits_uop_ppred_busy,\t// @[functional-unit.scala:168:14]\n input [5:0] io_req_bits_uop_stale_pdst,\t// @[functional-unit.scala:168:14]\n input io_req_bits_uop_exception,\t// @[functional-unit.scala:168:14]\n input [63:0] io_req_bits_uop_exc_cause,\t// @[functional-unit.scala:168:14]\n input io_req_bits_uop_bypassable,\t// @[functional-unit.scala:168:14]\n input [4:0] io_req_bits_uop_mem_cmd,\t// @[functional-unit.scala:168:14]\n input [1:0] io_req_bits_uop_mem_size,\t// @[functional-unit.scala:168:14]\n input io_req_bits_uop_mem_signed,\t// @[functional-unit.scala:168:14]\n input io_req_bits_uop_is_fence,\t// @[functional-unit.scala:168:14]\n input io_req_bits_uop_is_fencei,\t// @[functional-unit.scala:168:14]\n input io_req_bits_uop_is_amo,\t// @[functional-unit.scala:168:14]\n input io_req_bits_uop_uses_ldq,\t// @[functional-unit.scala:168:14]\n input io_req_bits_uop_uses_stq,\t// @[functional-unit.scala:168:14]\n input io_req_bits_uop_is_sys_pc2epc,\t// @[functional-unit.scala:168:14]\n input io_req_bits_uop_is_unique,\t// @[functional-unit.scala:168:14]\n input io_req_bits_uop_flush_on_commit,\t// @[functional-unit.scala:168:14]\n input io_req_bits_uop_ldst_is_rs1,\t// @[functional-unit.scala:168:14]\n input [5:0] io_req_bits_uop_ldst,\t// @[functional-unit.scala:168:14]\n input [5:0] io_req_bits_uop_lrs1,\t// @[functional-unit.scala:168:14]\n input [5:0] io_req_bits_uop_lrs2,\t// @[functional-unit.scala:168:14]\n input [5:0] io_req_bits_uop_lrs3,\t// @[functional-unit.scala:168:14]\n input io_req_bits_uop_ldst_val,\t// @[functional-unit.scala:168:14]\n input [1:0] io_req_bits_uop_dst_rtype,\t// @[functional-unit.scala:168:14]\n input [1:0] io_req_bits_uop_lrs1_rtype,\t// @[functional-unit.scala:168:14]\n input [1:0] io_req_bits_uop_lrs2_rtype,\t// @[functional-unit.scala:168:14]\n input io_req_bits_uop_frs3_en,\t// @[functional-unit.scala:168:14]\n input io_req_bits_uop_fp_val,\t// @[functional-unit.scala:168:14]\n input io_req_bits_uop_fp_single,\t// @[functional-unit.scala:168:14]\n input io_req_bits_uop_xcpt_pf_if,\t// @[functional-unit.scala:168:14]\n input io_req_bits_uop_xcpt_ae_if,\t// @[functional-unit.scala:168:14]\n input io_req_bits_uop_xcpt_ma_if,\t// @[functional-unit.scala:168:14]\n input io_req_bits_uop_bp_debug_if,\t// @[functional-unit.scala:168:14]\n input io_req_bits_uop_bp_xcpt_if,\t// @[functional-unit.scala:168:14]\n input [1:0] io_req_bits_uop_debug_fsrc,\t// @[functional-unit.scala:168:14]\n input [1:0] io_req_bits_uop_debug_tsrc,\t// @[functional-unit.scala:168:14]\n input [63:0] io_req_bits_rs1_data,\t// @[functional-unit.scala:168:14]\n input [63:0] io_req_bits_rs2_data,\t// @[functional-unit.scala:168:14]\n input io_req_bits_kill,\t// @[functional-unit.scala:168:14]\n input io_resp_ready,\t// @[functional-unit.scala:168:14]\n output io_resp_valid,\t// @[functional-unit.scala:168:14]\n output [6:0] io_resp_bits_uop_uopc,\t// @[functional-unit.scala:168:14]\n output [31:0] io_resp_bits_uop_inst,\t// @[functional-unit.scala:168:14]\n output [31:0] io_resp_bits_uop_debug_inst,\t// @[functional-unit.scala:168:14]\n output io_resp_bits_uop_is_rvc,\t// @[functional-unit.scala:168:14]\n output [39:0] io_resp_bits_uop_debug_pc,\t// @[functional-unit.scala:168:14]\n output [2:0] io_resp_bits_uop_iq_type,\t// @[functional-unit.scala:168:14]\n output [9:0] io_resp_bits_uop_fu_code,\t// @[functional-unit.scala:168:14]\n output [3:0] io_resp_bits_uop_ctrl_br_type,\t// @[functional-unit.scala:168:14]\n output [1:0] io_resp_bits_uop_ctrl_op1_sel,\t// @[functional-unit.scala:168:14]\n output [2:0] io_resp_bits_uop_ctrl_op2_sel,\t// @[functional-unit.scala:168:14]\n output [2:0] io_resp_bits_uop_ctrl_imm_sel,\t// @[functional-unit.scala:168:14]\n output [4:0] io_resp_bits_uop_ctrl_op_fcn,\t// @[functional-unit.scala:168:14]\n output io_resp_bits_uop_ctrl_fcn_dw,\t// @[functional-unit.scala:168:14]\n output [2:0] io_resp_bits_uop_ctrl_csr_cmd,\t// @[functional-unit.scala:168:14]\n output io_resp_bits_uop_ctrl_is_load,\t// @[functional-unit.scala:168:14]\n output io_resp_bits_uop_ctrl_is_sta,\t// @[functional-unit.scala:168:14]\n output io_resp_bits_uop_ctrl_is_std,\t// @[functional-unit.scala:168:14]\n output [1:0] io_resp_bits_uop_iw_state,\t// @[functional-unit.scala:168:14]\n output io_resp_bits_uop_iw_p1_poisoned,\t// @[functional-unit.scala:168:14]\n output io_resp_bits_uop_iw_p2_poisoned,\t// @[functional-unit.scala:168:14]\n output io_resp_bits_uop_is_br,\t// @[functional-unit.scala:168:14]\n output io_resp_bits_uop_is_jalr,\t// @[functional-unit.scala:168:14]\n output io_resp_bits_uop_is_jal,\t// @[functional-unit.scala:168:14]\n output io_resp_bits_uop_is_sfb,\t// @[functional-unit.scala:168:14]\n output [7:0] io_resp_bits_uop_br_mask,\t// @[functional-unit.scala:168:14]\n output [2:0] io_resp_bits_uop_br_tag,\t// @[functional-unit.scala:168:14]\n output [3:0] io_resp_bits_uop_ftq_idx,\t// @[functional-unit.scala:168:14]\n output io_resp_bits_uop_edge_inst,\t// @[functional-unit.scala:168:14]\n output [5:0] io_resp_bits_uop_pc_lob,\t// @[functional-unit.scala:168:14]\n output io_resp_bits_uop_taken,\t// @[functional-unit.scala:168:14]\n output [19:0] io_resp_bits_uop_imm_packed,\t// @[functional-unit.scala:168:14]\n output [11:0] io_resp_bits_uop_csr_addr,\t// @[functional-unit.scala:168:14]\n output [4:0] io_resp_bits_uop_rob_idx,\t// @[functional-unit.scala:168:14]\n output [2:0] io_resp_bits_uop_ldq_idx,\t// @[functional-unit.scala:168:14]\n output [2:0] io_resp_bits_uop_stq_idx,\t// @[functional-unit.scala:168:14]\n output [1:0] io_resp_bits_uop_rxq_idx,\t// @[functional-unit.scala:168:14]\n output [5:0] io_resp_bits_uop_pdst,\t// @[functional-unit.scala:168:14]\n output [5:0] io_resp_bits_uop_prs1,\t// @[functional-unit.scala:168:14]\n output [5:0] io_resp_bits_uop_prs2,\t// @[functional-unit.scala:168:14]\n output [5:0] io_resp_bits_uop_prs3,\t// @[functional-unit.scala:168:14]\n output [3:0] io_resp_bits_uop_ppred,\t// @[functional-unit.scala:168:14]\n output io_resp_bits_uop_prs1_busy,\t// @[functional-unit.scala:168:14]\n output io_resp_bits_uop_prs2_busy,\t// @[functional-unit.scala:168:14]\n output io_resp_bits_uop_prs3_busy,\t// @[functional-unit.scala:168:14]\n output io_resp_bits_uop_ppred_busy,\t// @[functional-unit.scala:168:14]\n output [5:0] io_resp_bits_uop_stale_pdst,\t// @[functional-unit.scala:168:14]\n output io_resp_bits_uop_exception,\t// @[functional-unit.scala:168:14]\n output [63:0] io_resp_bits_uop_exc_cause,\t// @[functional-unit.scala:168:14]\n output io_resp_bits_uop_bypassable,\t// @[functional-unit.scala:168:14]\n output [4:0] io_resp_bits_uop_mem_cmd,\t// @[functional-unit.scala:168:14]\n output [1:0] io_resp_bits_uop_mem_size,\t// @[functional-unit.scala:168:14]\n output io_resp_bits_uop_mem_signed,\t// @[functional-unit.scala:168:14]\n output io_resp_bits_uop_is_fence,\t// @[functional-unit.scala:168:14]\n output io_resp_bits_uop_is_fencei,\t// @[functional-unit.scala:168:14]\n output io_resp_bits_uop_is_amo,\t// @[functional-unit.scala:168:14]\n output io_resp_bits_uop_uses_ldq,\t// @[functional-unit.scala:168:14]\n output io_resp_bits_uop_uses_stq,\t// @[functional-unit.scala:168:14]\n output io_resp_bits_uop_is_sys_pc2epc,\t// @[functional-unit.scala:168:14]\n output io_resp_bits_uop_is_unique,\t// @[functional-unit.scala:168:14]\n output io_resp_bits_uop_flush_on_commit,\t// @[functional-unit.scala:168:14]\n output io_resp_bits_uop_ldst_is_rs1,\t// @[functional-unit.scala:168:14]\n output [5:0] io_resp_bits_uop_ldst,\t// @[functional-unit.scala:168:14]\n output [5:0] io_resp_bits_uop_lrs1,\t// @[functional-unit.scala:168:14]\n output [5:0] io_resp_bits_uop_lrs2,\t// @[functional-unit.scala:168:14]\n output [5:0] io_resp_bits_uop_lrs3,\t// @[functional-unit.scala:168:14]\n output io_resp_bits_uop_ldst_val,\t// @[functional-unit.scala:168:14]\n output [1:0] io_resp_bits_uop_dst_rtype,\t// @[functional-unit.scala:168:14]\n output [1:0] io_resp_bits_uop_lrs1_rtype,\t// @[functional-unit.scala:168:14]\n output [1:0] io_resp_bits_uop_lrs2_rtype,\t// @[functional-unit.scala:168:14]\n output io_resp_bits_uop_frs3_en,\t// @[functional-unit.scala:168:14]\n output io_resp_bits_uop_fp_val,\t// @[functional-unit.scala:168:14]\n output io_resp_bits_uop_fp_single,\t// @[functional-unit.scala:168:14]\n output io_resp_bits_uop_xcpt_pf_if,\t// @[functional-unit.scala:168:14]\n output io_resp_bits_uop_xcpt_ae_if,\t// @[functional-unit.scala:168:14]\n output io_resp_bits_uop_xcpt_ma_if,\t// @[functional-unit.scala:168:14]\n output io_resp_bits_uop_bp_debug_if,\t// @[functional-unit.scala:168:14]\n output io_resp_bits_uop_bp_xcpt_if,\t// @[functional-unit.scala:168:14]\n output [1:0] io_resp_bits_uop_debug_fsrc,\t// @[functional-unit.scala:168:14]\n output [1:0] io_resp_bits_uop_debug_tsrc,\t// @[functional-unit.scala:168:14]\n output [63:0] io_resp_bits_data,\t// @[functional-unit.scala:168:14]\n input [7:0] io_brupdate_b1_resolve_mask,\t// @[functional-unit.scala:168:14]\n input [7:0] io_brupdate_b1_mispredict_mask,\t// @[functional-unit.scala:168:14]\n input [6:0] io_brupdate_b2_uop_uopc,\t// @[functional-unit.scala:168:14]\n input [31:0] io_brupdate_b2_uop_inst,\t// @[functional-unit.scala:168:14]\n input [31:0] io_brupdate_b2_uop_debug_inst,\t// @[functional-unit.scala:168:14]\n input io_brupdate_b2_uop_is_rvc,\t// @[functional-unit.scala:168:14]\n input [39:0] io_brupdate_b2_uop_debug_pc,\t// @[functional-unit.scala:168:14]\n input [2:0] io_brupdate_b2_uop_iq_type,\t// @[functional-unit.scala:168:14]\n input [9:0] io_brupdate_b2_uop_fu_code,\t// @[functional-unit.scala:168:14]\n input [3:0] io_brupdate_b2_uop_ctrl_br_type,\t// @[functional-unit.scala:168:14]\n input [1:0] io_brupdate_b2_uop_ctrl_op1_sel,\t// @[functional-unit.scala:168:14]\n input [2:0] io_brupdate_b2_uop_ctrl_op2_sel,\t// @[functional-unit.scala:168:14]\n input [2:0] io_brupdate_b2_uop_ctrl_imm_sel,\t// @[functional-unit.scala:168:14]\n input [4:0] io_brupdate_b2_uop_ctrl_op_fcn,\t// @[functional-unit.scala:168:14]\n input io_brupdate_b2_uop_ctrl_fcn_dw,\t// @[functional-unit.scala:168:14]\n input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd,\t// @[functional-unit.scala:168:14]\n input io_brupdate_b2_uop_ctrl_is_load,\t// @[functional-unit.scala:168:14]\n input io_brupdate_b2_uop_ctrl_is_sta,\t// @[functional-unit.scala:168:14]\n input io_brupdate_b2_uop_ctrl_is_std,\t// @[functional-unit.scala:168:14]\n input [1:0] io_brupdate_b2_uop_iw_state,\t// @[functional-unit.scala:168:14]\n input io_brupdate_b2_uop_iw_p1_poisoned,\t// @[functional-unit.scala:168:14]\n input io_brupdate_b2_uop_iw_p2_poisoned,\t// @[functional-unit.scala:168:14]\n input io_brupdate_b2_uop_is_br,\t// @[functional-unit.scala:168:14]\n input io_brupdate_b2_uop_is_jalr,\t// @[functional-unit.scala:168:14]\n input io_brupdate_b2_uop_is_jal,\t// @[functional-unit.scala:168:14]\n input io_brupdate_b2_uop_is_sfb,\t// @[functional-unit.scala:168:14]\n input [7:0] io_brupdate_b2_uop_br_mask,\t// @[functional-unit.scala:168:14]\n input [2:0] io_brupdate_b2_uop_br_tag,\t// @[functional-unit.scala:168:14]\n input [3:0] io_brupdate_b2_uop_ftq_idx,\t// @[functional-unit.scala:168:14]\n input io_brupdate_b2_uop_edge_inst,\t// @[functional-unit.scala:168:14]\n input [5:0] io_brupdate_b2_uop_pc_lob,\t// @[functional-unit.scala:168:14]\n input io_brupdate_b2_uop_taken,\t// @[functional-unit.scala:168:14]\n input [19:0] io_brupdate_b2_uop_imm_packed,\t// @[functional-unit.scala:168:14]\n input [11:0] io_brupdate_b2_uop_csr_addr,\t// @[functional-unit.scala:168:14]\n input [4:0] io_brupdate_b2_uop_rob_idx,\t// @[functional-unit.scala:168:14]\n input [2:0] io_brupdate_b2_uop_ldq_idx,\t// @[functional-unit.scala:168:14]\n input [2:0] io_brupdate_b2_uop_stq_idx,\t// @[functional-unit.scala:168:14]\n input [1:0] io_brupdate_b2_uop_rxq_idx,\t// @[functional-unit.scala:168:14]\n input [5:0] io_brupdate_b2_uop_pdst,\t// @[functional-unit.scala:168:14]\n input [5:0] io_brupdate_b2_uop_prs1,\t// @[functional-unit.scala:168:14]\n input [5:0] io_brupdate_b2_uop_prs2,\t// @[functional-unit.scala:168:14]\n input [5:0] io_brupdate_b2_uop_prs3,\t// @[functional-unit.scala:168:14]\n input [3:0] io_brupdate_b2_uop_ppred,\t// @[functional-unit.scala:168:14]\n input io_brupdate_b2_uop_prs1_busy,\t// @[functional-unit.scala:168:14]\n input io_brupdate_b2_uop_prs2_busy,\t// @[functional-unit.scala:168:14]\n input io_brupdate_b2_uop_prs3_busy,\t// @[functional-unit.scala:168:14]\n input io_brupdate_b2_uop_ppred_busy,\t// @[functional-unit.scala:168:14]\n input [5:0] io_brupdate_b2_uop_stale_pdst,\t// @[functional-unit.scala:168:14]\n input io_brupdate_b2_uop_exception,\t// @[functional-unit.scala:168:14]\n input [63:0] io_brupdate_b2_uop_exc_cause,\t// @[functional-unit.scala:168:14]\n input io_brupdate_b2_uop_bypassable,\t// @[functional-unit.scala:168:14]\n input [4:0] io_brupdate_b2_uop_mem_cmd,\t// @[functional-unit.scala:168:14]\n input [1:0] io_brupdate_b2_uop_mem_size,\t// @[functional-unit.scala:168:14]\n input io_brupdate_b2_uop_mem_signed,\t// @[functional-unit.scala:168:14]\n input io_brupdate_b2_uop_is_fence,\t// @[functional-unit.scala:168:14]\n input io_brupdate_b2_uop_is_fencei,\t// @[functional-unit.scala:168:14]\n input io_brupdate_b2_uop_is_amo,\t// @[functional-unit.scala:168:14]\n input io_brupdate_b2_uop_uses_ldq,\t// @[functional-unit.scala:168:14]\n input io_brupdate_b2_uop_uses_stq,\t// @[functional-unit.scala:168:14]\n input io_brupdate_b2_uop_is_sys_pc2epc,\t// @[functional-unit.scala:168:14]\n input io_brupdate_b2_uop_is_unique,\t// @[functional-unit.scala:168:14]\n input io_brupdate_b2_uop_flush_on_commit,\t// @[functional-unit.scala:168:14]\n input io_brupdate_b2_uop_ldst_is_rs1,\t// @[functional-unit.scala:168:14]\n input [5:0] io_brupdate_b2_uop_ldst,\t// @[functional-unit.scala:168:14]\n input [5:0] io_brupdate_b2_uop_lrs1,\t// @[functional-unit.scala:168:14]\n input [5:0] io_brupdate_b2_uop_lrs2,\t// @[functional-unit.scala:168:14]\n input [5:0] io_brupdate_b2_uop_lrs3,\t// @[functional-unit.scala:168:14]\n input io_brupdate_b2_uop_ldst_val,\t// @[functional-unit.scala:168:14]\n input [1:0] io_brupdate_b2_uop_dst_rtype,\t// @[functional-unit.scala:168:14]\n input [1:0] io_brupdate_b2_uop_lrs1_rtype,\t// @[functional-unit.scala:168:14]\n input [1:0] io_brupdate_b2_uop_lrs2_rtype,\t// @[functional-unit.scala:168:14]\n input io_brupdate_b2_uop_frs3_en,\t// @[functional-unit.scala:168:14]\n input io_brupdate_b2_uop_fp_val,\t// @[functional-unit.scala:168:14]\n input io_brupdate_b2_uop_fp_single,\t// @[functional-unit.scala:168:14]\n input io_brupdate_b2_uop_xcpt_pf_if,\t// @[functional-unit.scala:168:14]\n input io_brupdate_b2_uop_xcpt_ae_if,\t// @[functional-unit.scala:168:14]\n input io_brupdate_b2_uop_xcpt_ma_if,\t// @[functional-unit.scala:168:14]\n input io_brupdate_b2_uop_bp_debug_if,\t// @[functional-unit.scala:168:14]\n input io_brupdate_b2_uop_bp_xcpt_if,\t// @[functional-unit.scala:168:14]\n input [1:0] io_brupdate_b2_uop_debug_fsrc,\t// @[functional-unit.scala:168:14]\n input [1:0] io_brupdate_b2_uop_debug_tsrc,\t// @[functional-unit.scala:168:14]\n input io_brupdate_b2_valid,\t// @[functional-unit.scala:168:14]\n input io_brupdate_b2_mispredict,\t// @[functional-unit.scala:168:14]\n input io_brupdate_b2_taken,\t// @[functional-unit.scala:168:14]\n input [2:0] io_brupdate_b2_cfi_type,\t// @[functional-unit.scala:168:14]\n input [1:0] io_brupdate_b2_pc_sel,\t// @[functional-unit.scala:168:14]\n input [39:0] io_brupdate_b2_jalr_target,\t// @[functional-unit.scala:168:14]\n input [20:0] io_brupdate_b2_target_offset\t// @[functional-unit.scala:168:14]\n);\n\n wire _div_io_resp_valid;\t// @[functional-unit.scala:682:19]\n wire io_req_valid_0 = io_req_valid;\t// @[functional-unit.scala:676:7]\n wire [6:0] io_req_bits_uop_uopc_0 = io_req_bits_uop_uopc;\t// @[functional-unit.scala:676:7]\n wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst;\t// @[functional-unit.scala:676:7]\n wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst;\t// @[functional-unit.scala:676:7]\n wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc;\t// @[functional-unit.scala:676:7]\n wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc;\t// @[functional-unit.scala:676:7]\n wire [2:0] io_req_bits_uop_iq_type_0 = io_req_bits_uop_iq_type;\t// @[functional-unit.scala:676:7]\n wire [9:0] io_req_bits_uop_fu_code_0 = io_req_bits_uop_fu_code;\t// @[functional-unit.scala:676:7]\n wire [3:0] io_req_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type;\t// @[functional-unit.scala:676:7]\n wire [1:0] io_req_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel;\t// @[functional-unit.scala:676:7]\n wire [2:0] io_req_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel;\t// @[functional-unit.scala:676:7]\n wire [2:0] io_req_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel;\t// @[functional-unit.scala:676:7]\n wire [4:0] io_req_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn;\t// @[functional-unit.scala:676:7]\n wire io_req_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw;\t// @[functional-unit.scala:676:7]\n wire [2:0] io_req_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd;\t// @[functional-unit.scala:676:7]\n wire io_req_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load;\t// @[functional-unit.scala:676:7]\n wire io_req_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta;\t// @[functional-unit.scala:676:7]\n wire io_req_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std;\t// @[functional-unit.scala:676:7]\n wire [1:0] io_req_bits_uop_iw_state_0 = io_req_bits_uop_iw_state;\t// @[functional-unit.scala:676:7]\n wire io_req_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned;\t// @[functional-unit.scala:676:7]\n wire io_req_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned;\t// @[functional-unit.scala:676:7]\n wire io_req_bits_uop_is_br_0 = io_req_bits_uop_is_br;\t// @[functional-unit.scala:676:7]\n wire io_req_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr;\t// @[functional-unit.scala:676:7]\n wire io_req_bits_uop_is_jal_0 = io_req_bits_uop_is_jal;\t// @[functional-unit.scala:676:7]\n wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb;\t// @[functional-unit.scala:676:7]\n wire [7:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask;\t// @[functional-unit.scala:676:7]\n wire [2:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag;\t// @[functional-unit.scala:676:7]\n wire [3:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx;\t// @[functional-unit.scala:676:7]\n wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst;\t// @[functional-unit.scala:676:7]\n wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob;\t// @[functional-unit.scala:676:7]\n wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken;\t// @[functional-unit.scala:676:7]\n wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed;\t// @[functional-unit.scala:676:7]\n wire [11:0] io_req_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr;\t// @[functional-unit.scala:676:7]\n wire [4:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx;\t// @[functional-unit.scala:676:7]\n wire [2:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx;\t// @[functional-unit.scala:676:7]\n wire [2:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx;\t// @[functional-unit.scala:676:7]\n wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx;\t// @[functional-unit.scala:676:7]\n wire [5:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst;\t// @[functional-unit.scala:676:7]\n wire [5:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1;\t// @[functional-unit.scala:676:7]\n wire [5:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2;\t// @[functional-unit.scala:676:7]\n wire [5:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3;\t// @[functional-unit.scala:676:7]\n wire [3:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred;\t// @[functional-unit.scala:676:7]\n wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy;\t// @[functional-unit.scala:676:7]\n wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy;\t// @[functional-unit.scala:676:7]\n wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy;\t// @[functional-unit.scala:676:7]\n wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy;\t// @[functional-unit.scala:676:7]\n wire [5:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst;\t// @[functional-unit.scala:676:7]\n wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception;\t// @[functional-unit.scala:676:7]\n wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause;\t// @[functional-unit.scala:676:7]\n wire io_req_bits_uop_bypassable_0 = io_req_bits_uop_bypassable;\t// @[functional-unit.scala:676:7]\n wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd;\t// @[functional-unit.scala:676:7]\n wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size;\t// @[functional-unit.scala:676:7]\n wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed;\t// @[functional-unit.scala:676:7]\n wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence;\t// @[functional-unit.scala:676:7]\n wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei;\t// @[functional-unit.scala:676:7]\n wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo;\t// @[functional-unit.scala:676:7]\n wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq;\t// @[functional-unit.scala:676:7]\n wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq;\t// @[functional-unit.scala:676:7]\n wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc;\t// @[functional-unit.scala:676:7]\n wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique;\t// @[functional-unit.scala:676:7]\n wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit;\t// @[functional-unit.scala:676:7]\n wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1;\t// @[functional-unit.scala:676:7]\n wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst;\t// @[functional-unit.scala:676:7]\n wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1;\t// @[functional-unit.scala:676:7]\n wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2;\t// @[functional-unit.scala:676:7]\n wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3;\t// @[functional-unit.scala:676:7]\n wire io_req_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val;\t// @[functional-unit.scala:676:7]\n wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype;\t// @[functional-unit.scala:676:7]\n wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype;\t// @[functional-unit.scala:676:7]\n wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype;\t// @[functional-unit.scala:676:7]\n wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en;\t// @[functional-unit.scala:676:7]\n wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val;\t// @[functional-unit.scala:676:7]\n wire io_req_bits_uop_fp_single_0 = io_req_bits_uop_fp_single;\t// @[functional-unit.scala:676:7]\n wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if;\t// @[functional-unit.scala:676:7]\n wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if;\t// @[functional-unit.scala:676:7]\n wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if;\t// @[functional-unit.scala:676:7]\n wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if;\t// @[functional-unit.scala:676:7]\n wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if;\t// @[functional-unit.scala:676:7]\n wire [1:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc;\t// @[functional-unit.scala:676:7]\n wire [1:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc;\t// @[functional-unit.scala:676:7]\n wire [63:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data;\t// @[functional-unit.scala:676:7]\n wire [63:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data;\t// @[functional-unit.scala:676:7]\n wire io_req_bits_kill_0 = io_req_bits_kill;\t// @[functional-unit.scala:676:7]\n wire io_resp_ready_0 = io_resp_ready;\t// @[functional-unit.scala:676:7]\n wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask;\t// @[functional-unit.scala:676:7]\n wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask;\t// @[functional-unit.scala:676:7]\n wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc;\t// @[functional-unit.scala:676:7]\n wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst;\t// @[functional-unit.scala:676:7]\n wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst;\t// @[functional-unit.scala:676:7]\n wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc;\t// @[functional-unit.scala:676:7]\n wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc;\t// @[functional-unit.scala:676:7]\n wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type;\t// @[functional-unit.scala:676:7]\n wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code;\t// @[functional-unit.scala:676:7]\n wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type;\t// @[functional-unit.scala:676:7]\n wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel;\t// @[functional-unit.scala:676:7]\n wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel;\t// @[functional-unit.scala:676:7]\n wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel;\t// @[functional-unit.scala:676:7]\n wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn;\t// @[functional-unit.scala:676:7]\n wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw;\t// @[functional-unit.scala:676:7]\n wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd;\t// @[functional-unit.scala:676:7]\n wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load;\t// @[functional-unit.scala:676:7]\n wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta;\t// @[functional-unit.scala:676:7]\n wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std;\t// @[functional-unit.scala:676:7]\n wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state;\t// @[functional-unit.scala:676:7]\n wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned;\t// @[functional-unit.scala:676:7]\n wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned;\t// @[functional-unit.scala:676:7]\n wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br;\t// @[functional-unit.scala:676:7]\n wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr;\t// @[functional-unit.scala:676:7]\n wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal;\t// @[functional-unit.scala:676:7]\n wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb;\t// @[functional-unit.scala:676:7]\n wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask;\t// @[functional-unit.scala:676:7]\n wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag;\t// @[functional-unit.scala:676:7]\n wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx;\t// @[functional-unit.scala:676:7]\n wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst;\t// @[functional-unit.scala:676:7]\n wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob;\t// @[functional-unit.scala:676:7]\n wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken;\t// @[functional-unit.scala:676:7]\n wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed;\t// @[functional-unit.scala:676:7]\n wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr;\t// @[functional-unit.scala:676:7]\n wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx;\t// @[functional-unit.scala:676:7]\n wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx;\t// @[functional-unit.scala:676:7]\n wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx;\t// @[functional-unit.scala:676:7]\n wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx;\t// @[functional-unit.scala:676:7]\n wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst;\t// @[functional-unit.scala:676:7]\n wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1;\t// @[functional-unit.scala:676:7]\n wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2;\t// @[functional-unit.scala:676:7]\n wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3;\t// @[functional-unit.scala:676:7]\n wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred;\t// @[functional-unit.scala:676:7]\n wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy;\t// @[functional-unit.scala:676:7]\n wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy;\t// @[functional-unit.scala:676:7]\n wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy;\t// @[functional-unit.scala:676:7]\n wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy;\t// @[functional-unit.scala:676:7]\n wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst;\t// @[functional-unit.scala:676:7]\n wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception;\t// @[functional-unit.scala:676:7]\n wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause;\t// @[functional-unit.scala:676:7]\n wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable;\t// @[functional-unit.scala:676:7]\n wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd;\t// @[functional-unit.scala:676:7]\n wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size;\t// @[functional-unit.scala:676:7]\n wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed;\t// @[functional-unit.scala:676:7]\n wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence;\t// @[functional-unit.scala:676:7]\n wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei;\t// @[functional-unit.scala:676:7]\n wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo;\t// @[functional-unit.scala:676:7]\n wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq;\t// @[functional-unit.scala:676:7]\n wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq;\t// @[functional-unit.scala:676:7]\n wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc;\t// @[functional-unit.scala:676:7]\n wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique;\t// @[functional-unit.scala:676:7]\n wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit;\t// @[functional-unit.scala:676:7]\n wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1;\t// @[functional-unit.scala:676:7]\n wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst;\t// @[functional-unit.scala:676:7]\n wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1;\t// @[functional-unit.scala:676:7]\n wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2;\t// @[functional-unit.scala:676:7]\n wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3;\t// @[functional-unit.scala:676:7]\n wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val;\t// @[functional-unit.scala:676:7]\n wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype;\t// @[functional-unit.scala:676:7]\n wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype;\t// @[functional-unit.scala:676:7]\n wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype;\t// @[functional-unit.scala:676:7]\n wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en;\t// @[functional-unit.scala:676:7]\n wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val;\t// @[functional-unit.scala:676:7]\n wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single;\t// @[functional-unit.scala:676:7]\n wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if;\t// @[functional-unit.scala:676:7]\n wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if;\t// @[functional-unit.scala:676:7]\n wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if;\t// @[functional-unit.scala:676:7]\n wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if;\t// @[functional-unit.scala:676:7]\n wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if;\t// @[functional-unit.scala:676:7]\n wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc;\t// @[functional-unit.scala:676:7]\n wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc;\t// @[functional-unit.scala:676:7]\n wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid;\t// @[functional-unit.scala:676:7]\n wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict;\t// @[functional-unit.scala:676:7]\n wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken;\t// @[functional-unit.scala:676:7]\n wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type;\t// @[functional-unit.scala:676:7]\n wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel;\t// @[functional-unit.scala:676:7]\n wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target;\t// @[functional-unit.scala:676:7]\n wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset;\t// @[functional-unit.scala:676:7]\n wire [38:0] io_resp_bits_sfence_bits_addr = 39'h0;\t// @[functional-unit.scala:676:7]\n wire [24:0] io_resp_bits_mxcpt_bits = 25'h0;\t// @[functional-unit.scala:676:7]\n wire [11:0] io_resp_bits_fflags_bits_uop_csr_addr = 12'h0;\t// @[functional-unit.scala:676:7]\n wire [19:0] io_resp_bits_fflags_bits_uop_imm_packed = 20'h0;\t// @[functional-unit.scala:676:7]\n wire [5:0] io_resp_bits_fflags_bits_uop_pc_lob = 6'h0;\t// @[functional-unit.scala:676:7]\n wire [5:0] io_resp_bits_fflags_bits_uop_pdst = 6'h0;\t// @[functional-unit.scala:676:7]\n wire [5:0] io_resp_bits_fflags_bits_uop_prs1 = 6'h0;\t// @[functional-unit.scala:676:7]\n wire [5:0] io_resp_bits_fflags_bits_uop_prs2 = 6'h0;\t// @[functional-unit.scala:676:7]\n wire [5:0] io_resp_bits_fflags_bits_uop_prs3 = 6'h0;\t// @[functional-unit.scala:676:7]\n wire [5:0] io_resp_bits_fflags_bits_uop_stale_pdst = 6'h0;\t// @[functional-unit.scala:676:7]\n wire [5:0] io_resp_bits_fflags_bits_uop_ldst = 6'h0;\t// @[functional-unit.scala:676:7]\n wire [5:0] io_resp_bits_fflags_bits_uop_lrs1 = 6'h0;\t// @[functional-unit.scala:676:7]\n wire [5:0] io_resp_bits_fflags_bits_uop_lrs2 = 6'h0;\t// @[functional-unit.scala:676:7]\n wire [5:0] io_resp_bits_fflags_bits_uop_lrs3 = 6'h0;\t// @[functional-unit.scala:676:7]\n wire [7:0] io_resp_bits_fflags_bits_uop_br_mask = 8'h0;\t// @[functional-unit.scala:676:7]\n wire [4:0] io_resp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0;\t// @[functional-unit.scala:676:7]\n wire [4:0] io_resp_bits_fflags_bits_uop_rob_idx = 5'h0;\t// @[functional-unit.scala:676:7]\n wire [4:0] io_resp_bits_fflags_bits_uop_mem_cmd = 5'h0;\t// @[functional-unit.scala:676:7]\n wire [4:0] io_resp_bits_fflags_bits_flags = 5'h0;\t// @[functional-unit.scala:676:7]\n wire [1:0] io_resp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0;\t// @[functional-unit.scala:676:7]\n wire [1:0] io_resp_bits_fflags_bits_uop_iw_state = 2'h0;\t// @[functional-unit.scala:676:7]\n wire [1:0] io_resp_bits_fflags_bits_uop_rxq_idx = 2'h0;\t// @[functional-unit.scala:676:7]\n wire [1:0] io_resp_bits_fflags_bits_uop_mem_size = 2'h0;\t// @[functional-unit.scala:676:7]\n wire [1:0] io_resp_bits_fflags_bits_uop_dst_rtype = 2'h0;\t// @[functional-unit.scala:676:7]\n wire [1:0] io_resp_bits_fflags_bits_uop_lrs1_rtype = 2'h0;\t// @[functional-unit.scala:676:7]\n wire [1:0] io_resp_bits_fflags_bits_uop_lrs2_rtype = 2'h0;\t// @[functional-unit.scala:676:7]\n wire [1:0] io_resp_bits_fflags_bits_uop_debug_fsrc = 2'h0;\t// @[functional-unit.scala:676:7]\n wire [1:0] io_resp_bits_fflags_bits_uop_debug_tsrc = 2'h0;\t// @[functional-unit.scala:676:7]\n wire [3:0] io_resp_bits_fflags_bits_uop_ctrl_br_type = 4'h0;\t// @[functional-unit.scala:676:7]\n wire [3:0] io_resp_bits_fflags_bits_uop_ftq_idx = 4'h0;\t// @[functional-unit.scala:676:7]\n wire [3:0] io_resp_bits_fflags_bits_uop_ppred = 4'h0;\t// @[functional-unit.scala:676:7]\n wire [9:0] io_resp_bits_fflags_bits_uop_fu_code = 10'h0;\t// @[functional-unit.scala:676:7]\n wire [2:0] io_resp_bits_fflags_bits_uop_iq_type = 3'h0;\t// @[functional-unit.scala:676:7]\n wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0;\t// @[functional-unit.scala:676:7]\n wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0;\t// @[functional-unit.scala:676:7]\n wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0;\t// @[functional-unit.scala:676:7]\n wire [2:0] io_resp_bits_fflags_bits_uop_br_tag = 3'h0;\t// @[functional-unit.scala:676:7]\n wire [2:0] io_resp_bits_fflags_bits_uop_ldq_idx = 3'h0;\t// @[functional-unit.scala:676:7]\n wire [2:0] io_resp_bits_fflags_bits_uop_stq_idx = 3'h0;\t// @[functional-unit.scala:676:7]\n wire [39:0] io_resp_bits_fflags_bits_uop_debug_pc = 40'h0;\t// @[functional-unit.scala:676:7]\n wire [39:0] io_resp_bits_addr = 40'h0;\t// @[functional-unit.scala:676:7]\n wire [31:0] io_resp_bits_fflags_bits_uop_inst = 32'h0;\t// @[functional-unit.scala:676:7]\n wire [31:0] io_resp_bits_fflags_bits_uop_debug_inst = 32'h0;\t// @[functional-unit.scala:676:7]\n wire [6:0] io_resp_bits_fflags_bits_uop_uopc = 7'h0;\t// @[functional-unit.scala:676:7]\n wire io_req_bits_pred_data = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_predicated = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_fflags_valid = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_fflags_bits_uop_is_rvc = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_fflags_bits_uop_ctrl_is_load = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_fflags_bits_uop_ctrl_is_std = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_fflags_bits_uop_is_br = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_fflags_bits_uop_is_jalr = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_fflags_bits_uop_is_jal = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_fflags_bits_uop_is_sfb = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_fflags_bits_uop_edge_inst = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_fflags_bits_uop_taken = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_fflags_bits_uop_prs1_busy = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_fflags_bits_uop_prs2_busy = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_fflags_bits_uop_prs3_busy = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_fflags_bits_uop_ppred_busy = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_fflags_bits_uop_exception = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_fflags_bits_uop_bypassable = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_fflags_bits_uop_mem_signed = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_fflags_bits_uop_is_fence = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_fflags_bits_uop_is_fencei = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_fflags_bits_uop_is_amo = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_fflags_bits_uop_uses_ldq = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_fflags_bits_uop_uses_stq = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_fflags_bits_uop_is_unique = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_fflags_bits_uop_flush_on_commit = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_fflags_bits_uop_ldst_val = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_fflags_bits_uop_frs3_en = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_fflags_bits_uop_fp_val = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_fflags_bits_uop_fp_single = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_fflags_bits_uop_bp_debug_if = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_mxcpt_valid = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_sfence_valid = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_sfence_bits_rs1 = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_sfence_bits_rs2 = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_sfence_bits_asid = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_sfence_bits_hv = 1'h0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_sfence_bits_hg = 1'h0;\t// @[functional-unit.scala:676:7]\n wire [63:0] io_req_bits_rs3_data = 64'h0;\t// @[functional-unit.scala:676:7]\n wire [63:0] io_resp_bits_fflags_bits_uop_exc_cause = 64'h0;\t// @[functional-unit.scala:676:7]\n wire _io_resp_valid_T_1;\t// @[functional-unit.scala:697:44]\n wire io_req_ready_0;\t// @[functional-unit.scala:676:7]\n wire [3:0] io_resp_bits_uop_ctrl_br_type_0;\t// @[functional-unit.scala:676:7]\n wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0;\t// @[functional-unit.scala:676:7]\n wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0;\t// @[functional-unit.scala:676:7]\n wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0;\t// @[functional-unit.scala:676:7]\n wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_uop_ctrl_fcn_dw_0;\t// @[functional-unit.scala:676:7]\n wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_uop_ctrl_is_load_0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_uop_ctrl_is_sta_0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_uop_ctrl_is_std_0;\t// @[functional-unit.scala:676:7]\n wire [6:0] io_resp_bits_uop_uopc_0;\t// @[functional-unit.scala:676:7]\n wire [31:0] io_resp_bits_uop_inst_0;\t// @[functional-unit.scala:676:7]\n wire [31:0] io_resp_bits_uop_debug_inst_0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_uop_is_rvc_0;\t// @[functional-unit.scala:676:7]\n wire [39:0] io_resp_bits_uop_debug_pc_0;\t// @[functional-unit.scala:676:7]\n wire [2:0] io_resp_bits_uop_iq_type_0;\t// @[functional-unit.scala:676:7]\n wire [9:0] io_resp_bits_uop_fu_code_0;\t// @[functional-unit.scala:676:7]\n wire [1:0] io_resp_bits_uop_iw_state_0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_uop_iw_p1_poisoned_0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_uop_iw_p2_poisoned_0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_uop_is_br_0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_uop_is_jalr_0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_uop_is_jal_0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_uop_is_sfb_0;\t// @[functional-unit.scala:676:7]\n wire [7:0] io_resp_bits_uop_br_mask_0;\t// @[functional-unit.scala:676:7]\n wire [2:0] io_resp_bits_uop_br_tag_0;\t// @[functional-unit.scala:676:7]\n wire [3:0] io_resp_bits_uop_ftq_idx_0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_uop_edge_inst_0;\t// @[functional-unit.scala:676:7]\n wire [5:0] io_resp_bits_uop_pc_lob_0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_uop_taken_0;\t// @[functional-unit.scala:676:7]\n wire [19:0] io_resp_bits_uop_imm_packed_0;\t// @[functional-unit.scala:676:7]\n wire [11:0] io_resp_bits_uop_csr_addr_0;\t// @[functional-unit.scala:676:7]\n wire [4:0] io_resp_bits_uop_rob_idx_0;\t// @[functional-unit.scala:676:7]\n wire [2:0] io_resp_bits_uop_ldq_idx_0;\t// @[functional-unit.scala:676:7]\n wire [2:0] io_resp_bits_uop_stq_idx_0;\t// @[functional-unit.scala:676:7]\n wire [1:0] io_resp_bits_uop_rxq_idx_0;\t// @[functional-unit.scala:676:7]\n wire [5:0] io_resp_bits_uop_pdst_0;\t// @[functional-unit.scala:676:7]\n wire [5:0] io_resp_bits_uop_prs1_0;\t// @[functional-unit.scala:676:7]\n wire [5:0] io_resp_bits_uop_prs2_0;\t// @[functional-unit.scala:676:7]\n wire [5:0] io_resp_bits_uop_prs3_0;\t// @[functional-unit.scala:676:7]\n wire [3:0] io_resp_bits_uop_ppred_0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_uop_prs1_busy_0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_uop_prs2_busy_0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_uop_prs3_busy_0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_uop_ppred_busy_0;\t// @[functional-unit.scala:676:7]\n wire [5:0] io_resp_bits_uop_stale_pdst_0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_uop_exception_0;\t// @[functional-unit.scala:676:7]\n wire [63:0] io_resp_bits_uop_exc_cause_0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_uop_bypassable_0;\t// @[functional-unit.scala:676:7]\n wire [4:0] io_resp_bits_uop_mem_cmd_0;\t// @[functional-unit.scala:676:7]\n wire [1:0] io_resp_bits_uop_mem_size_0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_uop_mem_signed_0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_uop_is_fence_0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_uop_is_fencei_0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_uop_is_amo_0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_uop_uses_ldq_0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_uop_uses_stq_0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_uop_is_sys_pc2epc_0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_uop_is_unique_0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_uop_flush_on_commit_0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_uop_ldst_is_rs1_0;\t// @[functional-unit.scala:676:7]\n wire [5:0] io_resp_bits_uop_ldst_0;\t// @[functional-unit.scala:676:7]\n wire [5:0] io_resp_bits_uop_lrs1_0;\t// @[functional-unit.scala:676:7]\n wire [5:0] io_resp_bits_uop_lrs2_0;\t// @[functional-unit.scala:676:7]\n wire [5:0] io_resp_bits_uop_lrs3_0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_uop_ldst_val_0;\t// @[functional-unit.scala:676:7]\n wire [1:0] io_resp_bits_uop_dst_rtype_0;\t// @[functional-unit.scala:676:7]\n wire [1:0] io_resp_bits_uop_lrs1_rtype_0;\t// @[functional-unit.scala:676:7]\n wire [1:0] io_resp_bits_uop_lrs2_rtype_0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_uop_frs3_en_0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_uop_fp_val_0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_uop_fp_single_0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_uop_xcpt_pf_if_0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_uop_xcpt_ae_if_0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_uop_xcpt_ma_if_0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_uop_bp_debug_if_0;\t// @[functional-unit.scala:676:7]\n wire io_resp_bits_uop_bp_xcpt_if_0;\t// @[functional-unit.scala:676:7]\n wire [1:0] io_resp_bits_uop_debug_fsrc_0;\t// @[functional-unit.scala:676:7]\n wire [1:0] io_resp_bits_uop_debug_tsrc_0;\t// @[functional-unit.scala:676:7]\n wire [63:0] io_resp_bits_data_0;\t// @[functional-unit.scala:676:7]\n wire io_resp_valid_0;\t// @[functional-unit.scala:676:7]\n reg [6:0] r_uop_uopc;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_uopc_0 = r_uop_uopc;\t// @[functional-unit.scala:652:18, :676:7]\n reg [31:0] r_uop_inst;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_inst_0 = r_uop_inst;\t// @[functional-unit.scala:652:18, :676:7]\n reg [31:0] r_uop_debug_inst;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_debug_inst_0 = r_uop_debug_inst;\t// @[functional-unit.scala:652:18, :676:7]\n reg r_uop_is_rvc;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_is_rvc_0 = r_uop_is_rvc;\t// @[functional-unit.scala:652:18, :676:7]\n reg [39:0] r_uop_debug_pc;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_debug_pc_0 = r_uop_debug_pc;\t// @[functional-unit.scala:652:18, :676:7]\n reg [2:0] r_uop_iq_type;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_iq_type_0 = r_uop_iq_type;\t// @[functional-unit.scala:652:18, :676:7]\n reg [9:0] r_uop_fu_code;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_fu_code_0 = r_uop_fu_code;\t// @[functional-unit.scala:652:18, :676:7]\n reg [3:0] r_uop_ctrl_br_type;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_ctrl_br_type_0 = r_uop_ctrl_br_type;\t// @[functional-unit.scala:652:18, :676:7]\n reg [1:0] r_uop_ctrl_op1_sel;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_ctrl_op1_sel_0 = r_uop_ctrl_op1_sel;\t// @[functional-unit.scala:652:18, :676:7]\n reg [2:0] r_uop_ctrl_op2_sel;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_ctrl_op2_sel_0 = r_uop_ctrl_op2_sel;\t// @[functional-unit.scala:652:18, :676:7]\n reg [2:0] r_uop_ctrl_imm_sel;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_ctrl_imm_sel_0 = r_uop_ctrl_imm_sel;\t// @[functional-unit.scala:652:18, :676:7]\n reg [4:0] r_uop_ctrl_op_fcn;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_ctrl_op_fcn_0 = r_uop_ctrl_op_fcn;\t// @[functional-unit.scala:652:18, :676:7]\n reg r_uop_ctrl_fcn_dw;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_ctrl_fcn_dw_0 = r_uop_ctrl_fcn_dw;\t// @[functional-unit.scala:652:18, :676:7]\n reg [2:0] r_uop_ctrl_csr_cmd;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_ctrl_csr_cmd_0 = r_uop_ctrl_csr_cmd;\t// @[functional-unit.scala:652:18, :676:7]\n reg r_uop_ctrl_is_load;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_ctrl_is_load_0 = r_uop_ctrl_is_load;\t// @[functional-unit.scala:652:18, :676:7]\n reg r_uop_ctrl_is_sta;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_ctrl_is_sta_0 = r_uop_ctrl_is_sta;\t// @[functional-unit.scala:652:18, :676:7]\n reg r_uop_ctrl_is_std;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_ctrl_is_std_0 = r_uop_ctrl_is_std;\t// @[functional-unit.scala:652:18, :676:7]\n reg [1:0] r_uop_iw_state;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_iw_state_0 = r_uop_iw_state;\t// @[functional-unit.scala:652:18, :676:7]\n reg r_uop_iw_p1_poisoned;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_iw_p1_poisoned_0 = r_uop_iw_p1_poisoned;\t// @[functional-unit.scala:652:18, :676:7]\n reg r_uop_iw_p2_poisoned;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_iw_p2_poisoned_0 = r_uop_iw_p2_poisoned;\t// @[functional-unit.scala:652:18, :676:7]\n reg r_uop_is_br;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_is_br_0 = r_uop_is_br;\t// @[functional-unit.scala:652:18, :676:7]\n reg r_uop_is_jalr;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_is_jalr_0 = r_uop_is_jalr;\t// @[functional-unit.scala:652:18, :676:7]\n reg r_uop_is_jal;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_is_jal_0 = r_uop_is_jal;\t// @[functional-unit.scala:652:18, :676:7]\n reg r_uop_is_sfb;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_is_sfb_0 = r_uop_is_sfb;\t// @[functional-unit.scala:652:18, :676:7]\n reg [7:0] r_uop_br_mask;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_br_mask_0 = r_uop_br_mask;\t// @[functional-unit.scala:652:18, :676:7]\n reg [2:0] r_uop_br_tag;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_br_tag_0 = r_uop_br_tag;\t// @[functional-unit.scala:652:18, :676:7]\n reg [3:0] r_uop_ftq_idx;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_ftq_idx_0 = r_uop_ftq_idx;\t// @[functional-unit.scala:652:18, :676:7]\n reg r_uop_edge_inst;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_edge_inst_0 = r_uop_edge_inst;\t// @[functional-unit.scala:652:18, :676:7]\n reg [5:0] r_uop_pc_lob;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_pc_lob_0 = r_uop_pc_lob;\t// @[functional-unit.scala:652:18, :676:7]\n reg r_uop_taken;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_taken_0 = r_uop_taken;\t// @[functional-unit.scala:652:18, :676:7]\n reg [19:0] r_uop_imm_packed;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_imm_packed_0 = r_uop_imm_packed;\t// @[functional-unit.scala:652:18, :676:7]\n reg [11:0] r_uop_csr_addr;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_csr_addr_0 = r_uop_csr_addr;\t// @[functional-unit.scala:652:18, :676:7]\n reg [4:0] r_uop_rob_idx;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_rob_idx_0 = r_uop_rob_idx;\t// @[functional-unit.scala:652:18, :676:7]\n reg [2:0] r_uop_ldq_idx;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_ldq_idx_0 = r_uop_ldq_idx;\t// @[functional-unit.scala:652:18, :676:7]\n reg [2:0] r_uop_stq_idx;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_stq_idx_0 = r_uop_stq_idx;\t// @[functional-unit.scala:652:18, :676:7]\n reg [1:0] r_uop_rxq_idx;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_rxq_idx_0 = r_uop_rxq_idx;\t// @[functional-unit.scala:652:18, :676:7]\n reg [5:0] r_uop_pdst;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_pdst_0 = r_uop_pdst;\t// @[functional-unit.scala:652:18, :676:7]\n reg [5:0] r_uop_prs1;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_prs1_0 = r_uop_prs1;\t// @[functional-unit.scala:652:18, :676:7]\n reg [5:0] r_uop_prs2;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_prs2_0 = r_uop_prs2;\t// @[functional-unit.scala:652:18, :676:7]\n reg [5:0] r_uop_prs3;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_prs3_0 = r_uop_prs3;\t// @[functional-unit.scala:652:18, :676:7]\n reg [3:0] r_uop_ppred;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_ppred_0 = r_uop_ppred;\t// @[functional-unit.scala:652:18, :676:7]\n reg r_uop_prs1_busy;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_prs1_busy_0 = r_uop_prs1_busy;\t// @[functional-unit.scala:652:18, :676:7]\n reg r_uop_prs2_busy;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_prs2_busy_0 = r_uop_prs2_busy;\t// @[functional-unit.scala:652:18, :676:7]\n reg r_uop_prs3_busy;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_prs3_busy_0 = r_uop_prs3_busy;\t// @[functional-unit.scala:652:18, :676:7]\n reg r_uop_ppred_busy;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_ppred_busy_0 = r_uop_ppred_busy;\t// @[functional-unit.scala:652:18, :676:7]\n reg [5:0] r_uop_stale_pdst;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_stale_pdst_0 = r_uop_stale_pdst;\t// @[functional-unit.scala:652:18, :676:7]\n reg r_uop_exception;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_exception_0 = r_uop_exception;\t// @[functional-unit.scala:652:18, :676:7]\n reg [63:0] r_uop_exc_cause;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_exc_cause_0 = r_uop_exc_cause;\t// @[functional-unit.scala:652:18, :676:7]\n reg r_uop_bypassable;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_bypassable_0 = r_uop_bypassable;\t// @[functional-unit.scala:652:18, :676:7]\n reg [4:0] r_uop_mem_cmd;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_mem_cmd_0 = r_uop_mem_cmd;\t// @[functional-unit.scala:652:18, :676:7]\n reg [1:0] r_uop_mem_size;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_mem_size_0 = r_uop_mem_size;\t// @[functional-unit.scala:652:18, :676:7]\n reg r_uop_mem_signed;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_mem_signed_0 = r_uop_mem_signed;\t// @[functional-unit.scala:652:18, :676:7]\n reg r_uop_is_fence;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_is_fence_0 = r_uop_is_fence;\t// @[functional-unit.scala:652:18, :676:7]\n reg r_uop_is_fencei;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_is_fencei_0 = r_uop_is_fencei;\t// @[functional-unit.scala:652:18, :676:7]\n reg r_uop_is_amo;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_is_amo_0 = r_uop_is_amo;\t// @[functional-unit.scala:652:18, :676:7]\n reg r_uop_uses_ldq;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_uses_ldq_0 = r_uop_uses_ldq;\t// @[functional-unit.scala:652:18, :676:7]\n reg r_uop_uses_stq;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_uses_stq_0 = r_uop_uses_stq;\t// @[functional-unit.scala:652:18, :676:7]\n reg r_uop_is_sys_pc2epc;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_is_sys_pc2epc_0 = r_uop_is_sys_pc2epc;\t// @[functional-unit.scala:652:18, :676:7]\n reg r_uop_is_unique;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_is_unique_0 = r_uop_is_unique;\t// @[functional-unit.scala:652:18, :676:7]\n reg r_uop_flush_on_commit;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_flush_on_commit_0 = r_uop_flush_on_commit;\t// @[functional-unit.scala:652:18, :676:7]\n reg r_uop_ldst_is_rs1;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_ldst_is_rs1_0 = r_uop_ldst_is_rs1;\t// @[functional-unit.scala:652:18, :676:7]\n reg [5:0] r_uop_ldst;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_ldst_0 = r_uop_ldst;\t// @[functional-unit.scala:652:18, :676:7]\n reg [5:0] r_uop_lrs1;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_lrs1_0 = r_uop_lrs1;\t// @[functional-unit.scala:652:18, :676:7]\n reg [5:0] r_uop_lrs2;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_lrs2_0 = r_uop_lrs2;\t// @[functional-unit.scala:652:18, :676:7]\n reg [5:0] r_uop_lrs3;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_lrs3_0 = r_uop_lrs3;\t// @[functional-unit.scala:652:18, :676:7]\n reg r_uop_ldst_val;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_ldst_val_0 = r_uop_ldst_val;\t// @[functional-unit.scala:652:18, :676:7]\n reg [1:0] r_uop_dst_rtype;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_dst_rtype_0 = r_uop_dst_rtype;\t// @[functional-unit.scala:652:18, :676:7]\n reg [1:0] r_uop_lrs1_rtype;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_lrs1_rtype_0 = r_uop_lrs1_rtype;\t// @[functional-unit.scala:652:18, :676:7]\n reg [1:0] r_uop_lrs2_rtype;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_lrs2_rtype_0 = r_uop_lrs2_rtype;\t// @[functional-unit.scala:652:18, :676:7]\n reg r_uop_frs3_en;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_frs3_en_0 = r_uop_frs3_en;\t// @[functional-unit.scala:652:18, :676:7]\n reg r_uop_fp_val;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_fp_val_0 = r_uop_fp_val;\t// @[functional-unit.scala:652:18, :676:7]\n reg r_uop_fp_single;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_fp_single_0 = r_uop_fp_single;\t// @[functional-unit.scala:652:18, :676:7]\n reg r_uop_xcpt_pf_if;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_xcpt_pf_if_0 = r_uop_xcpt_pf_if;\t// @[functional-unit.scala:652:18, :676:7]\n reg r_uop_xcpt_ae_if;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_xcpt_ae_if_0 = r_uop_xcpt_ae_if;\t// @[functional-unit.scala:652:18, :676:7]\n reg r_uop_xcpt_ma_if;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_xcpt_ma_if_0 = r_uop_xcpt_ma_if;\t// @[functional-unit.scala:652:18, :676:7]\n reg r_uop_bp_debug_if;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_bp_debug_if_0 = r_uop_bp_debug_if;\t// @[functional-unit.scala:652:18, :676:7]\n reg r_uop_bp_xcpt_if;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_bp_xcpt_if_0 = r_uop_bp_xcpt_if;\t// @[functional-unit.scala:652:18, :676:7]\n reg [1:0] r_uop_debug_fsrc;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_debug_fsrc_0 = r_uop_debug_fsrc;\t// @[functional-unit.scala:652:18, :676:7]\n reg [1:0] r_uop_debug_tsrc;\t// @[functional-unit.scala:652:18]\n assign io_resp_bits_uop_debug_tsrc_0 = r_uop_debug_tsrc;\t// @[functional-unit.scala:652:18, :676:7]\n wire do_kill;\t// @[functional-unit.scala:654:21]\n wire _T = io_req_ready_0 & io_req_valid_0;\t// @[Decoupled.scala:51:35]\n wire [7:0] _do_kill_T = io_brupdate_b1_mispredict_mask_0 & io_req_bits_uop_br_mask_0;\t// @[util.scala:118:51]\n wire _do_kill_T_1 = |_do_kill_T;\t// @[util.scala:118:{51,59}]\n wire _do_kill_T_2 = _do_kill_T_1 | io_req_bits_kill_0;\t// @[util.scala:118:59]\n wire [7:0] _r_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0;\t// @[util.scala:85:27]\n wire [7:0] _r_uop_br_mask_T_1 = io_req_bits_uop_br_mask_0 & _r_uop_br_mask_T;\t// @[util.scala:85:{25,27}]\n wire [7:0] _do_kill_T_3 = io_brupdate_b1_mispredict_mask_0 & r_uop_br_mask;\t// @[util.scala:118:51]\n wire _do_kill_T_4 = |_do_kill_T_3;\t// @[util.scala:118:{51,59}]\n wire _do_kill_T_5 = _do_kill_T_4 | io_req_bits_kill_0;\t// @[util.scala:118:59]\n assign do_kill = _T ? _do_kill_T_2 : _do_kill_T_5;\t// @[Decoupled.scala:51:35]\n wire [7:0] _r_uop_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0;\t// @[util.scala:85:27]\n wire [7:0] _r_uop_br_mask_T_3 = r_uop_br_mask & _r_uop_br_mask_T_2;\t// @[util.scala:85:{25,27}]\n wire _div_io_req_valid_T = ~do_kill;\t// @[functional-unit.scala:654:21, :685:42]\n wire _div_io_req_valid_T_1 = io_req_valid_0 & _div_io_req_valid_T;\t// @[functional-unit.scala:676:7, :685:{39,42}]\n wire _io_resp_valid_T = ~do_kill;\t// @[functional-unit.scala:654:21, :685:42, :697:47]\n assign _io_resp_valid_T_1 = _div_io_resp_valid & _io_resp_valid_T;\t// @[functional-unit.scala:682:19, :697:{44,47}]\n assign io_resp_valid_0 = _io_resp_valid_T_1;\t// @[functional-unit.scala:676:7, :697:44]\n always @(posedge clock) begin\t// @[functional-unit.scala:676:7]\n if (_T) begin\t// @[Decoupled.scala:51:35]\n r_uop_uopc <= io_req_bits_uop_uopc_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_inst <= io_req_bits_uop_inst_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_debug_inst <= io_req_bits_uop_debug_inst_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_is_rvc <= io_req_bits_uop_is_rvc_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_debug_pc <= io_req_bits_uop_debug_pc_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_iq_type <= io_req_bits_uop_iq_type_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_fu_code <= io_req_bits_uop_fu_code_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_ctrl_br_type <= io_req_bits_uop_ctrl_br_type_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_ctrl_op1_sel <= io_req_bits_uop_ctrl_op1_sel_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_ctrl_op2_sel <= io_req_bits_uop_ctrl_op2_sel_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_ctrl_imm_sel <= io_req_bits_uop_ctrl_imm_sel_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_ctrl_op_fcn <= io_req_bits_uop_ctrl_op_fcn_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_ctrl_fcn_dw <= io_req_bits_uop_ctrl_fcn_dw_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_ctrl_csr_cmd <= io_req_bits_uop_ctrl_csr_cmd_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_ctrl_is_load <= io_req_bits_uop_ctrl_is_load_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_ctrl_is_sta <= io_req_bits_uop_ctrl_is_sta_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_ctrl_is_std <= io_req_bits_uop_ctrl_is_std_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_iw_state <= io_req_bits_uop_iw_state_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_iw_p1_poisoned <= io_req_bits_uop_iw_p1_poisoned_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_iw_p2_poisoned <= io_req_bits_uop_iw_p2_poisoned_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_is_br <= io_req_bits_uop_is_br_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_is_jalr <= io_req_bits_uop_is_jalr_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_is_jal <= io_req_bits_uop_is_jal_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_is_sfb <= io_req_bits_uop_is_sfb_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_br_tag <= io_req_bits_uop_br_tag_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_ftq_idx <= io_req_bits_uop_ftq_idx_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_edge_inst <= io_req_bits_uop_edge_inst_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_pc_lob <= io_req_bits_uop_pc_lob_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_taken <= io_req_bits_uop_taken_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_imm_packed <= io_req_bits_uop_imm_packed_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_csr_addr <= io_req_bits_uop_csr_addr_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_rob_idx <= io_req_bits_uop_rob_idx_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_ldq_idx <= io_req_bits_uop_ldq_idx_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_stq_idx <= io_req_bits_uop_stq_idx_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_rxq_idx <= io_req_bits_uop_rxq_idx_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_pdst <= io_req_bits_uop_pdst_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_prs1 <= io_req_bits_uop_prs1_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_prs2 <= io_req_bits_uop_prs2_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_prs3 <= io_req_bits_uop_prs3_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_ppred <= io_req_bits_uop_ppred_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_prs1_busy <= io_req_bits_uop_prs1_busy_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_prs2_busy <= io_req_bits_uop_prs2_busy_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_prs3_busy <= io_req_bits_uop_prs3_busy_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_ppred_busy <= io_req_bits_uop_ppred_busy_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_stale_pdst <= io_req_bits_uop_stale_pdst_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_exception <= io_req_bits_uop_exception_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_exc_cause <= io_req_bits_uop_exc_cause_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_bypassable <= io_req_bits_uop_bypassable_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_mem_cmd <= io_req_bits_uop_mem_cmd_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_mem_size <= io_req_bits_uop_mem_size_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_mem_signed <= io_req_bits_uop_mem_signed_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_is_fence <= io_req_bits_uop_is_fence_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_is_fencei <= io_req_bits_uop_is_fencei_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_is_amo <= io_req_bits_uop_is_amo_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_uses_ldq <= io_req_bits_uop_uses_ldq_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_uses_stq <= io_req_bits_uop_uses_stq_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_is_sys_pc2epc <= io_req_bits_uop_is_sys_pc2epc_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_is_unique <= io_req_bits_uop_is_unique_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_flush_on_commit <= io_req_bits_uop_flush_on_commit_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_ldst_is_rs1 <= io_req_bits_uop_ldst_is_rs1_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_ldst <= io_req_bits_uop_ldst_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_lrs1 <= io_req_bits_uop_lrs1_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_lrs2 <= io_req_bits_uop_lrs2_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_lrs3 <= io_req_bits_uop_lrs3_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_ldst_val <= io_req_bits_uop_ldst_val_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_dst_rtype <= io_req_bits_uop_dst_rtype_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_lrs1_rtype <= io_req_bits_uop_lrs1_rtype_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_lrs2_rtype <= io_req_bits_uop_lrs2_rtype_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_frs3_en <= io_req_bits_uop_frs3_en_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_fp_val <= io_req_bits_uop_fp_val_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_fp_single <= io_req_bits_uop_fp_single_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_xcpt_pf_if <= io_req_bits_uop_xcpt_pf_if_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_xcpt_ae_if <= io_req_bits_uop_xcpt_ae_if_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_xcpt_ma_if <= io_req_bits_uop_xcpt_ma_if_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_bp_debug_if <= io_req_bits_uop_bp_debug_if_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_bp_xcpt_if <= io_req_bits_uop_bp_xcpt_if_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_debug_fsrc <= io_req_bits_uop_debug_fsrc_0;\t// @[functional-unit.scala:652:18, :676:7]\n r_uop_debug_tsrc <= io_req_bits_uop_debug_tsrc_0;\t// @[functional-unit.scala:652:18, :676:7]\n end\n r_uop_br_mask <= _T ? _r_uop_br_mask_T_1 : _r_uop_br_mask_T_3;\t// @[Decoupled.scala:51:35]\n always @(posedge)\n MulDiv_1 div (\t// @[functional-unit.scala:682:19]\n .clock (clock),\n .reset (reset),\n .io_req_ready (io_req_ready_0),\n .io_req_valid (_div_io_req_valid_T_1),\t// @[functional-unit.scala:685:39]\n .io_req_bits_fn (io_req_bits_uop_ctrl_op_fcn_0),\t// @[functional-unit.scala:676:7]\n .io_req_bits_dw (io_req_bits_uop_ctrl_fcn_dw_0),\t// @[functional-unit.scala:676:7]\n .io_req_bits_in1 (io_req_bits_rs1_data_0),\t// @[functional-unit.scala:676:7]\n .io_req_bits_in2 (io_req_bits_rs2_data_0),\t// @[functional-unit.scala:676:7]\n .io_kill (do_kill),\t// @[functional-unit.scala:654:21]\n .io_resp_ready (io_resp_ready_0),\t// @[functional-unit.scala:676:7]\n .io_resp_valid (_div_io_resp_valid),\n .io_resp_bits_data (io_resp_bits_data_0)\n );\t// @[functional-unit.scala:682:19]\n assign io_req_ready = io_req_ready_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_valid = io_resp_valid_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_uopc = io_resp_bits_uop_uopc_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_inst = io_resp_bits_uop_inst_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_debug_inst = io_resp_bits_uop_debug_inst_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_is_rvc = io_resp_bits_uop_is_rvc_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_debug_pc = io_resp_bits_uop_debug_pc_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_iq_type = io_resp_bits_uop_iq_type_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_fu_code = io_resp_bits_uop_fu_code_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_ctrl_br_type = io_resp_bits_uop_ctrl_br_type_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_ctrl_op1_sel = io_resp_bits_uop_ctrl_op1_sel_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_ctrl_op2_sel = io_resp_bits_uop_ctrl_op2_sel_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_ctrl_imm_sel = io_resp_bits_uop_ctrl_imm_sel_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_ctrl_op_fcn = io_resp_bits_uop_ctrl_op_fcn_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_ctrl_fcn_dw = io_resp_bits_uop_ctrl_fcn_dw_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_ctrl_csr_cmd = io_resp_bits_uop_ctrl_csr_cmd_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_ctrl_is_load = io_resp_bits_uop_ctrl_is_load_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_ctrl_is_sta = io_resp_bits_uop_ctrl_is_sta_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_ctrl_is_std = io_resp_bits_uop_ctrl_is_std_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_iw_state = io_resp_bits_uop_iw_state_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_iw_p1_poisoned = io_resp_bits_uop_iw_p1_poisoned_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_iw_p2_poisoned = io_resp_bits_uop_iw_p2_poisoned_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_is_br = io_resp_bits_uop_is_br_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_is_jalr = io_resp_bits_uop_is_jalr_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_is_jal = io_resp_bits_uop_is_jal_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_is_sfb = io_resp_bits_uop_is_sfb_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_br_mask = io_resp_bits_uop_br_mask_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_br_tag = io_resp_bits_uop_br_tag_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_ftq_idx = io_resp_bits_uop_ftq_idx_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_edge_inst = io_resp_bits_uop_edge_inst_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_pc_lob = io_resp_bits_uop_pc_lob_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_taken = io_resp_bits_uop_taken_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_imm_packed = io_resp_bits_uop_imm_packed_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_csr_addr = io_resp_bits_uop_csr_addr_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_rob_idx = io_resp_bits_uop_rob_idx_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_ldq_idx = io_resp_bits_uop_ldq_idx_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_stq_idx = io_resp_bits_uop_stq_idx_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_rxq_idx = io_resp_bits_uop_rxq_idx_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_pdst = io_resp_bits_uop_pdst_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_prs1 = io_resp_bits_uop_prs1_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_prs2 = io_resp_bits_uop_prs2_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_prs3 = io_resp_bits_uop_prs3_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_ppred = io_resp_bits_uop_ppred_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_prs1_busy = io_resp_bits_uop_prs1_busy_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_prs2_busy = io_resp_bits_uop_prs2_busy_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_prs3_busy = io_resp_bits_uop_prs3_busy_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_ppred_busy = io_resp_bits_uop_ppred_busy_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_stale_pdst = io_resp_bits_uop_stale_pdst_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_exception = io_resp_bits_uop_exception_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_exc_cause = io_resp_bits_uop_exc_cause_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_bypassable = io_resp_bits_uop_bypassable_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_mem_cmd = io_resp_bits_uop_mem_cmd_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_mem_size = io_resp_bits_uop_mem_size_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_mem_signed = io_resp_bits_uop_mem_signed_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_is_fence = io_resp_bits_uop_is_fence_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_is_fencei = io_resp_bits_uop_is_fencei_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_is_amo = io_resp_bits_uop_is_amo_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_uses_ldq = io_resp_bits_uop_uses_ldq_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_uses_stq = io_resp_bits_uop_uses_stq_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_is_sys_pc2epc = io_resp_bits_uop_is_sys_pc2epc_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_is_unique = io_resp_bits_uop_is_unique_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_flush_on_commit = io_resp_bits_uop_flush_on_commit_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_ldst_is_rs1 = io_resp_bits_uop_ldst_is_rs1_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_ldst = io_resp_bits_uop_ldst_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_lrs1 = io_resp_bits_uop_lrs1_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_lrs2 = io_resp_bits_uop_lrs2_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_lrs3 = io_resp_bits_uop_lrs3_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_ldst_val = io_resp_bits_uop_ldst_val_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_dst_rtype = io_resp_bits_uop_dst_rtype_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_lrs1_rtype = io_resp_bits_uop_lrs1_rtype_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_lrs2_rtype = io_resp_bits_uop_lrs2_rtype_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_frs3_en = io_resp_bits_uop_frs3_en_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_fp_val = io_resp_bits_uop_fp_val_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_fp_single = io_resp_bits_uop_fp_single_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_xcpt_pf_if = io_resp_bits_uop_xcpt_pf_if_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_xcpt_ae_if = io_resp_bits_uop_xcpt_ae_if_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_xcpt_ma_if = io_resp_bits_uop_xcpt_ma_if_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_bp_debug_if = io_resp_bits_uop_bp_debug_if_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_bp_xcpt_if = io_resp_bits_uop_bp_xcpt_if_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_debug_fsrc = io_resp_bits_uop_debug_fsrc_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_uop_debug_tsrc = io_resp_bits_uop_debug_tsrc_0;\t// @[functional-unit.scala:676:7]\n assign io_resp_bits_data = io_resp_bits_data_0;\t// @[functional-unit.scala:676:7]\nendmodule"}}},{"rowIdx":34384,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module TilePRCIDomain_1 : \n output auto : { intsink_out_2 : UInt<1>[1], intsink_out_1 : UInt<1>[1], intsink_out_0 : UInt<1>[1], flip intsink_in : { sync : UInt<1>[1]}, element_reset_domain_rockettile_trace_core_source_out : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>}, element_reset_domain_rockettile_trace_source_out : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>}, flip element_reset_domain_rockettile_reset_vector_in : UInt<32>, flip element_reset_domain_rockettile_hartid_in : UInt<3>, flip int_in_clock_xing_in_2 : { sync : UInt<1>[1]}, flip int_in_clock_xing_in_1 : { sync : UInt<1>[1]}, flip int_in_clock_xing_in_0 : { sync : UInt<1>[2]}, tl_master_clock_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip tap_clock_in : { clock : Clock, reset : Reset}} \n output clock : Clock \n output reset : Reset \n\n\n wire childClock : Clock \n wire childReset : Reset \n node _childClock_T = asClock(UInt<1>(0h0)) \n connect childClock, _childClock_T \n invalidate childReset \n inst element_reset_domain of HierarchicalElementResetDomain_1 \n inst clockNode of FixedClockBroadcast_1_3 \n inst buffer of TLBuffer_a32d64s2k3z4c_3 \n connect buffer.clock, childClock\n\n connect buffer.reset, childReset\n\n inst buffer_1 of TLBuffer_5 \n connect buffer_1.clock, childClock\n\n connect buffer_1.reset, childReset\n\n inst intsink of IntSyncAsyncCrossingSink_n1x1_1 \n connect intsink.clock, childClock\n\n connect intsink.reset, childReset\n\n inst intsink_1 of IntSyncSyncCrossingSink_n1x2_1 \n inst intsink_2 of IntSyncSyncCrossingSink_n1x1_5 \n inst intsink_3 of IntSyncSyncCrossingSink_n1x1_6 \n inst intsink_4 of IntSyncSyncCrossingSink_n1x1_7 \n inst intsource of IntSyncCrossingSource_n1x1_3 \n connect intsource.clock, childClock\n\n connect intsource.reset, childReset\n\n inst intsink_5 of IntSyncSyncCrossingSink_n1x1_8 \n inst intsource_1 of IntSyncCrossingSource_n1x1_4 \n connect intsource_1.clock, childClock\n\n connect intsource_1.reset, childReset\n\n inst intsink_6 of IntSyncSyncCrossingSink_n1x1_9 \n inst intsource_2 of IntSyncCrossingSource_n1x1_5 \n connect intsource_2.clock, childClock\n\n connect intsource_2.reset, childReset\n\n wire tapClockNodeOut : { clock : Clock, reset : Reset} \n invalidate tapClockNodeOut.reset \n invalidate tapClockNodeOut.clock \n wire tapClockNodeIn : { clock : Clock, reset : Reset} \n invalidate tapClockNodeIn.reset \n invalidate tapClockNodeIn.clock \n connect tapClockNodeOut, tapClockNodeIn \n wire tlMasterClockXingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} \n invalidate tlMasterClockXingOut.e.bits.sink \n invalidate tlMasterClockXingOut.e.valid \n invalidate tlMasterClockXingOut.e.ready \n invalidate tlMasterClockXingOut.d.bits.corrupt \n invalidate tlMasterClockXingOut.d.bits.data \n invalidate tlMasterClockXingOut.d.bits.denied \n invalidate tlMasterClockXingOut.d.bits.sink \n invalidate tlMasterClockXingOut.d.bits.source \n invalidate tlMasterClockXingOut.d.bits.size \n invalidate tlMasterClockXingOut.d.bits.param \n invalidate tlMasterClockXingOut.d.bits.opcode \n invalidate tlMasterClockXingOut.d.valid \n invalidate tlMasterClockXingOut.d.ready \n invalidate tlMasterClockXingOut.c.bits.corrupt \n invalidate tlMasterClockXingOut.c.bits.data \n invalidate tlMasterClockXingOut.c.bits.address \n invalidate tlMasterClockXingOut.c.bits.source \n invalidate tlMasterClockXingOut.c.bits.size \n invalidate tlMasterClockXingOut.c.bits.param \n invalidate tlMasterClockXingOut.c.bits.opcode \n invalidate tlMasterClockXingOut.c.valid \n invalidate tlMasterClockXingOut.c.ready \n invalidate tlMasterClockXingOut.b.bits.corrupt \n invalidate tlMasterClockXingOut.b.bits.data \n invalidate tlMasterClockXingOut.b.bits.mask \n invalidate tlMasterClockXingOut.b.bits.address \n invalidate tlMasterClockXingOut.b.bits.source \n invalidate tlMasterClockXingOut.b.bits.size \n invalidate tlMasterClockXingOut.b.bits.param \n invalidate tlMasterClockXingOut.b.bits.opcode \n invalidate tlMasterClockXingOut.b.valid \n invalidate tlMasterClockXingOut.b.ready \n invalidate tlMasterClockXingOut.a.bits.corrupt \n invalidate tlMasterClockXingOut.a.bits.data \n invalidate tlMasterClockXingOut.a.bits.mask \n invalidate tlMasterClockXingOut.a.bits.address \n invalidate tlMasterClockXingOut.a.bits.source \n invalidate tlMasterClockXingOut.a.bits.size \n invalidate tlMasterClockXingOut.a.bits.param \n invalidate tlMasterClockXingOut.a.bits.opcode \n invalidate tlMasterClockXingOut.a.valid \n invalidate tlMasterClockXingOut.a.ready \n wire tlMasterClockXingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} \n invalidate tlMasterClockXingIn.e.bits.sink \n invalidate tlMasterClockXingIn.e.valid \n invalidate tlMasterClockXingIn.e.ready \n invalidate tlMasterClockXingIn.d.bits.corrupt \n invalidate tlMasterClockXingIn.d.bits.data \n invalidate tlMasterClockXingIn.d.bits.denied \n invalidate tlMasterClockXingIn.d.bits.sink \n invalidate tlMasterClockXingIn.d.bits.source \n invalidate tlMasterClockXingIn.d.bits.size \n invalidate tlMasterClockXingIn.d.bits.param \n invalidate tlMasterClockXingIn.d.bits.opcode \n invalidate tlMasterClockXingIn.d.valid \n invalidate tlMasterClockXingIn.d.ready \n invalidate tlMasterClockXingIn.c.bits.corrupt \n invalidate tlMasterClockXingIn.c.bits.data \n invalidate tlMasterClockXingIn.c.bits.address \n invalidate tlMasterClockXingIn.c.bits.source \n invalidate tlMasterClockXingIn.c.bits.size \n invalidate tlMasterClockXingIn.c.bits.param \n invalidate tlMasterClockXingIn.c.bits.opcode \n invalidate tlMasterClockXingIn.c.valid \n invalidate tlMasterClockXingIn.c.ready \n invalidate tlMasterClockXingIn.b.bits.corrupt \n invalidate tlMasterClockXingIn.b.bits.data \n invalidate tlMasterClockXingIn.b.bits.mask \n invalidate tlMasterClockXingIn.b.bits.address \n invalidate tlMasterClockXingIn.b.bits.source \n invalidate tlMasterClockXingIn.b.bits.size \n invalidate tlMasterClockXingIn.b.bits.param \n invalidate tlMasterClockXingIn.b.bits.opcode \n invalidate tlMasterClockXingIn.b.valid \n invalidate tlMasterClockXingIn.b.ready \n invalidate tlMasterClockXingIn.a.bits.corrupt \n invalidate tlMasterClockXingIn.a.bits.data \n invalidate tlMasterClockXingIn.a.bits.mask \n invalidate tlMasterClockXingIn.a.bits.address \n invalidate tlMasterClockXingIn.a.bits.source \n invalidate tlMasterClockXingIn.a.bits.size \n invalidate tlMasterClockXingIn.a.bits.param \n invalidate tlMasterClockXingIn.a.bits.opcode \n invalidate tlMasterClockXingIn.a.valid \n invalidate tlMasterClockXingIn.a.ready \n connect tlMasterClockXingOut, tlMasterClockXingIn \n wire intInClockXingOut : { sync : UInt<1>[2]} \n invalidate intInClockXingOut.sync[0] \n invalidate intInClockXingOut.sync[1] \n wire intInClockXingIn : { sync : UInt<1>[2]} \n invalidate intInClockXingIn.sync[0] \n invalidate intInClockXingIn.sync[1] \n connect intInClockXingOut, intInClockXingIn \n wire intInClockXingOut_1 : { sync : UInt<1>[1]} \n invalidate intInClockXingOut_1.sync[0] \n wire intInClockXingIn_1 : { sync : UInt<1>[1]} \n invalidate intInClockXingIn_1.sync[0] \n connect intInClockXingOut_1, intInClockXingIn_1 \n wire intInClockXingOut_2 : { sync : UInt<1>[1]} \n invalidate intInClockXingOut_2.sync[0] \n wire intInClockXingIn_2 : { sync : UInt<1>[1]} \n invalidate intInClockXingIn_2.sync[0] \n connect intInClockXingOut_2, intInClockXingIn_2 \n wire intOutClockXingOut : { sync : UInt<1>[1]} \n invalidate intOutClockXingOut.sync[0] \n wire intOutClockXingIn : { sync : UInt<1>[1]} \n invalidate intOutClockXingIn.sync[0] \n connect intOutClockXingOut, intOutClockXingIn \n wire intOutClockXingOut_1 : { sync : UInt<1>[1]} \n invalidate intOutClockXingOut_1.sync[0] \n wire intOutClockXingIn_1 : { sync : UInt<1>[1]} \n invalidate intOutClockXingIn_1.sync[0] \n connect intOutClockXingOut_1, intOutClockXingIn_1 \n wire intOutClockXingOut_2 : { sync : UInt<1>[1]} \n invalidate intOutClockXingOut_2.sync[0] \n wire intOutClockXingIn_2 : { sync : UInt<1>[1]} \n invalidate intOutClockXingIn_2.sync[0] \n connect intOutClockXingOut_2, intOutClockXingIn_2 \n wire intOutClockXingOut_3 : { sync : UInt<1>[1]} \n invalidate intOutClockXingOut_3.sync[0] \n wire intOutClockXingIn_3 : { sync : UInt<1>[1]} \n invalidate intOutClockXingIn_3.sync[0] \n connect intOutClockXingOut_3, intOutClockXingIn_3 \n wire intOutClockXingOut_4 : { sync : UInt<1>[1]} \n invalidate intOutClockXingOut_4.sync[0] \n wire intOutClockXingIn_4 : { sync : UInt<1>[1]} \n invalidate intOutClockXingIn_4.sync[0] \n connect intOutClockXingOut_4, intOutClockXingIn_4 \n wire intOutClockXingOut_5 : { sync : UInt<1>[1]} \n invalidate intOutClockXingOut_5.sync[0] \n wire intOutClockXingIn_5 : { sync : UInt<1>[1]} \n invalidate intOutClockXingIn_5.sync[0] \n connect intOutClockXingOut_5, intOutClockXingIn_5 \n connect clockNode.auto.anon_in, tapClockNodeOut \n connect element_reset_domain.auto.clock_in, clockNode.auto.anon_out \n connect intsource.auto.in[0], element_reset_domain.auto.rockettile_halt_out[0] \n connect intsource_2.auto.in[0], element_reset_domain.auto.rockettile_cease_out[0] \n connect intsource_1.auto.in[0], element_reset_domain.auto.rockettile_wfi_out[0] \n connect buffer.auto.in, element_reset_domain.auto.rockettile_buffer_out \n connect tlMasterClockXingIn.e.bits, buffer.auto.out.e.bits \n connect tlMasterClockXingIn.e.valid, buffer.auto.out.e.valid \n connect buffer.auto.out.e.ready, tlMasterClockXingIn.e.ready \n connect buffer.auto.out.d, tlMasterClockXingIn.d \n connect tlMasterClockXingIn.c.bits, buffer.auto.out.c.bits \n connect tlMasterClockXingIn.c.valid, buffer.auto.out.c.valid \n connect buffer.auto.out.c.ready, tlMasterClockXingIn.c.ready \n connect buffer.auto.out.b, tlMasterClockXingIn.b \n connect tlMasterClockXingIn.a.bits, buffer.auto.out.a.bits \n connect tlMasterClockXingIn.a.valid, buffer.auto.out.a.valid \n connect buffer.auto.out.a.ready, tlMasterClockXingIn.a.ready \n connect element_reset_domain.auto.rockettile_int_local_in_0[0], intsink.auto.out[0] \n connect element_reset_domain.auto.rockettile_int_local_in_1[0], intsink_1.auto.out[0] \n connect element_reset_domain.auto.rockettile_int_local_in_1[1], intsink_1.auto.out[1] \n connect intsink_1.auto.in.sync[0], intInClockXingOut.sync[0] \n connect intsink_1.auto.in.sync[1], intInClockXingOut.sync[1] \n connect element_reset_domain.auto.rockettile_int_local_in_2[0], intsink_2.auto.out[0] \n connect intsink_2.auto.in.sync[0], intInClockXingOut_1.sync[0] \n connect element_reset_domain.auto.rockettile_int_local_in_3[0], intsink_3.auto.out[0] \n connect intsink_3.auto.in.sync[0], intInClockXingOut_2.sync[0] \n connect intsink_4.auto.in.sync[0], intOutClockXingOut.sync[0] \n connect intOutClockXingIn, intOutClockXingOut_1 \n connect intOutClockXingIn_1, intsource.auto.out \n connect intsink_5.auto.in.sync[0], intOutClockXingOut_2.sync[0] \n connect intOutClockXingIn_2, intOutClockXingOut_3 \n connect intOutClockXingIn_3, intsource_1.auto.out \n connect intsink_6.auto.in.sync[0], intOutClockXingOut_4.sync[0] \n connect intOutClockXingIn_4, intOutClockXingOut_5 \n connect intOutClockXingIn_5, intsource_2.auto.out \n connect tapClockNodeIn, auto.tap_clock_in \n connect auto.tl_master_clock_xing_out, tlMasterClockXingOut \n connect intInClockXingIn, auto.int_in_clock_xing_in_0 \n connect intInClockXingIn_1, auto.int_in_clock_xing_in_1 \n connect intInClockXingIn_2, auto.int_in_clock_xing_in_2 \n connect element_reset_domain.auto.rockettile_hartid_in, auto.element_reset_domain_rockettile_hartid_in \n connect element_reset_domain.auto.rockettile_reset_vector_in, auto.element_reset_domain_rockettile_reset_vector_in \n connect auto.element_reset_domain_rockettile_trace_source_out.time, element_reset_domain.auto.rockettile_trace_source_out.time \n connect auto.element_reset_domain_rockettile_trace_source_out.insns, element_reset_domain.auto.rockettile_trace_source_out.insns \n connect auto.element_reset_domain_rockettile_trace_core_source_out.cause, element_reset_domain.auto.rockettile_trace_core_source_out.cause \n connect auto.element_reset_domain_rockettile_trace_core_source_out.tval, element_reset_domain.auto.rockettile_trace_core_source_out.tval \n connect auto.element_reset_domain_rockettile_trace_core_source_out.priv, element_reset_domain.auto.rockettile_trace_core_source_out.priv \n connect auto.element_reset_domain_rockettile_trace_core_source_out.group, element_reset_domain.auto.rockettile_trace_core_source_out.group \n connect intsink.auto.in.sync[0], auto.intsink_in.sync[0] \n connect auto.intsink_out_0, intsink_4.auto.out \n connect auto.intsink_out_1, intsink_5.auto.out \n connect auto.intsink_out_2, intsink_6.auto.out \n connect childClock, tapClockNodeIn.clock \n connect childReset, tapClockNodeIn.reset \n connect clock, tapClockNodeIn.clock \n connect reset, tapClockNodeIn.reset \n\n\n extmodule plusarg_reader_100 : \n output out : UInt<32>\n\n defname = plusarg_reader\n\n parameter DEFAULT = 0\n\n parameter FORMAT = \"tilelink_timeout=%d\"\n\n parameter WIDTH = 32\n\n\n\n extmodule plusarg_reader_101 : \n output out : UInt<32>\n\n defname = plusarg_reader\n\n parameter DEFAULT = 0\n\n parameter FORMAT = \"tilelink_timeout=%d\"\n\n parameter WIDTH = 32"},"response":{"kind":"string","value":"module TilePRCIDomain_1(\t// @[ClockDomain.scala:14:9]\n output auto_intsink_out_1_0,\t// @[LazyModuleImp.scala:107:25]\n input auto_intsink_in_sync_0,\t// @[LazyModuleImp.scala:107:25]\n output auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid,\t// @[LazyModuleImp.scala:107:25]\n output [39:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv,\t// @[LazyModuleImp.scala:107:25]\n output auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception,\t// @[LazyModuleImp.scala:107:25]\n output auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause,\t// @[LazyModuleImp.scala:107:25]\n output [39:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_element_reset_domain_rockettile_trace_source_out_time,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_element_reset_domain_rockettile_hartid_in,\t// @[LazyModuleImp.scala:107:25]\n input auto_int_in_clock_xing_in_2_sync_0,\t// @[LazyModuleImp.scala:107:25]\n input auto_int_in_clock_xing_in_1_sync_0,\t// @[LazyModuleImp.scala:107:25]\n input auto_int_in_clock_xing_in_0_sync_0,\t// @[LazyModuleImp.scala:107:25]\n input auto_int_in_clock_xing_in_0_sync_1,\t// @[LazyModuleImp.scala:107:25]\n input auto_tl_master_clock_xing_out_a_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_tl_master_clock_xing_out_a_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_tl_master_clock_xing_out_a_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_tl_master_clock_xing_out_a_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_tl_master_clock_xing_out_a_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_tl_master_clock_xing_out_a_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_tl_master_clock_xing_out_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n output [7:0] auto_tl_master_clock_xing_out_a_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_tl_master_clock_xing_out_a_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_tl_master_clock_xing_out_a_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_tl_master_clock_xing_out_b_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_tl_master_clock_xing_out_b_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_tl_master_clock_xing_out_b_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_tl_master_clock_xing_out_b_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_tl_master_clock_xing_out_b_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_tl_master_clock_xing_out_b_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_tl_master_clock_xing_out_b_bits_address,\t// @[LazyModuleImp.scala:107:25]\n input [7:0] auto_tl_master_clock_xing_out_b_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_tl_master_clock_xing_out_b_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_tl_master_clock_xing_out_b_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input auto_tl_master_clock_xing_out_c_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_tl_master_clock_xing_out_c_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_tl_master_clock_xing_out_c_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_tl_master_clock_xing_out_c_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_tl_master_clock_xing_out_c_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_tl_master_clock_xing_out_c_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_tl_master_clock_xing_out_c_bits_address,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_tl_master_clock_xing_out_c_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_tl_master_clock_xing_out_c_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_tl_master_clock_xing_out_d_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_tl_master_clock_xing_out_d_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_tl_master_clock_xing_out_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_tl_master_clock_xing_out_d_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_tl_master_clock_xing_out_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_tl_master_clock_xing_out_d_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_tl_master_clock_xing_out_d_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n input auto_tl_master_clock_xing_out_d_bits_denied,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_tl_master_clock_xing_out_d_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_tl_master_clock_xing_out_d_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input auto_tl_master_clock_xing_out_e_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_tl_master_clock_xing_out_e_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_tl_master_clock_xing_out_e_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n input auto_tap_clock_in_clock,\t// @[LazyModuleImp.scala:107:25]\n input auto_tap_clock_in_reset\t// @[LazyModuleImp.scala:107:25]\n);\n\n wire clockNode_auto_anon_in_reset;\t// @[ClockGroup.scala:104:9]\n wire clockNode_auto_anon_in_clock;\t// @[ClockGroup.scala:104:9]\n wire element_reset_domain_auto_clock_in_reset;\t// @[ClockDomain.scala:14:9]\n wire element_reset_domain_auto_clock_in_clock;\t// @[ClockDomain.scala:14:9]\n wire auto_intsink_in_sync_0_0 = auto_intsink_in_sync_0;\t// @[ClockDomain.scala:14:9]\n wire [2:0] auto_element_reset_domain_rockettile_hartid_in_0 = auto_element_reset_domain_rockettile_hartid_in;\t// @[ClockDomain.scala:14:9]\n wire auto_int_in_clock_xing_in_2_sync_0_0 = auto_int_in_clock_xing_in_2_sync_0;\t// @[ClockDomain.scala:14:9]\n wire auto_int_in_clock_xing_in_1_sync_0_0 = auto_int_in_clock_xing_in_1_sync_0;\t// @[ClockDomain.scala:14:9]\n wire auto_int_in_clock_xing_in_0_sync_0_0 = auto_int_in_clock_xing_in_0_sync_0;\t// @[ClockDomain.scala:14:9]\n wire auto_int_in_clock_xing_in_0_sync_1_0 = auto_int_in_clock_xing_in_0_sync_1;\t// @[ClockDomain.scala:14:9]\n wire auto_tl_master_clock_xing_out_a_ready_0 = auto_tl_master_clock_xing_out_a_ready;\t// @[ClockDomain.scala:14:9]\n wire auto_tl_master_clock_xing_out_b_valid_0 = auto_tl_master_clock_xing_out_b_valid;\t// @[ClockDomain.scala:14:9]\n wire [2:0] auto_tl_master_clock_xing_out_b_bits_opcode_0 = auto_tl_master_clock_xing_out_b_bits_opcode;\t// @[ClockDomain.scala:14:9]\n wire [1:0] auto_tl_master_clock_xing_out_b_bits_param_0 = auto_tl_master_clock_xing_out_b_bits_param;\t// @[ClockDomain.scala:14:9]\n wire [3:0] auto_tl_master_clock_xing_out_b_bits_size_0 = auto_tl_master_clock_xing_out_b_bits_size;\t// @[ClockDomain.scala:14:9]\n wire [1:0] auto_tl_master_clock_xing_out_b_bits_source_0 = auto_tl_master_clock_xing_out_b_bits_source;\t// @[ClockDomain.scala:14:9]\n wire [31:0] auto_tl_master_clock_xing_out_b_bits_address_0 = auto_tl_master_clock_xing_out_b_bits_address;\t// @[ClockDomain.scala:14:9]\n wire [7:0] auto_tl_master_clock_xing_out_b_bits_mask_0 = auto_tl_master_clock_xing_out_b_bits_mask;\t// @[ClockDomain.scala:14:9]\n wire [63:0] auto_tl_master_clock_xing_out_b_bits_data_0 = auto_tl_master_clock_xing_out_b_bits_data;\t// @[ClockDomain.scala:14:9]\n wire auto_tl_master_clock_xing_out_b_bits_corrupt_0 = auto_tl_master_clock_xing_out_b_bits_corrupt;\t// @[ClockDomain.scala:14:9]\n wire auto_tl_master_clock_xing_out_c_ready_0 = auto_tl_master_clock_xing_out_c_ready;\t// @[ClockDomain.scala:14:9]\n wire auto_tl_master_clock_xing_out_d_valid_0 = auto_tl_master_clock_xing_out_d_valid;\t// @[ClockDomain.scala:14:9]\n wire [2:0] auto_tl_master_clock_xing_out_d_bits_opcode_0 = auto_tl_master_clock_xing_out_d_bits_opcode;\t// @[ClockDomain.scala:14:9]\n wire [1:0] auto_tl_master_clock_xing_out_d_bits_param_0 = auto_tl_master_clock_xing_out_d_bits_param;\t// @[ClockDomain.scala:14:9]\n wire [3:0] auto_tl_master_clock_xing_out_d_bits_size_0 = auto_tl_master_clock_xing_out_d_bits_size;\t// @[ClockDomain.scala:14:9]\n wire [1:0] auto_tl_master_clock_xing_out_d_bits_source_0 = auto_tl_master_clock_xing_out_d_bits_source;\t// @[ClockDomain.scala:14:9]\n wire [2:0] auto_tl_master_clock_xing_out_d_bits_sink_0 = auto_tl_master_clock_xing_out_d_bits_sink;\t// @[ClockDomain.scala:14:9]\n wire auto_tl_master_clock_xing_out_d_bits_denied_0 = auto_tl_master_clock_xing_out_d_bits_denied;\t// @[ClockDomain.scala:14:9]\n wire [63:0] auto_tl_master_clock_xing_out_d_bits_data_0 = auto_tl_master_clock_xing_out_d_bits_data;\t// @[ClockDomain.scala:14:9]\n wire auto_tl_master_clock_xing_out_d_bits_corrupt_0 = auto_tl_master_clock_xing_out_d_bits_corrupt;\t// @[ClockDomain.scala:14:9]\n wire auto_tl_master_clock_xing_out_e_ready_0 = auto_tl_master_clock_xing_out_e_ready;\t// @[ClockDomain.scala:14:9]\n wire auto_tap_clock_in_clock_0 = auto_tap_clock_in_clock;\t// @[ClockDomain.scala:14:9]\n wire auto_tap_clock_in_reset_0 = auto_tap_clock_in_reset;\t// @[ClockDomain.scala:14:9]\n wire [31:0] auto_element_reset_domain_rockettile_trace_core_source_out_group_0_iaddr = 32'h0;\t// @[ClockDomain.scala:14:9]\n wire [31:0] auto_element_reset_domain_rockettile_trace_core_source_out_tval = 32'h0;\t// @[ClockDomain.scala:14:9]\n wire [31:0] auto_element_reset_domain_rockettile_trace_core_source_out_cause = 32'h0;\t// @[ClockDomain.scala:14:9]\n wire [31:0] element_reset_domain_auto_rockettile_trace_core_source_out_group_0_iaddr = 32'h0;\t// @[ClockDomain.scala:14:9]\n wire [31:0] element_reset_domain_auto_rockettile_trace_core_source_out_tval = 32'h0;\t// @[ClockDomain.scala:14:9]\n wire [31:0] element_reset_domain_auto_rockettile_trace_core_source_out_cause = 32'h0;\t// @[ClockDomain.scala:14:9]\n wire [3:0] auto_element_reset_domain_rockettile_trace_core_source_out_group_0_itype = 4'h0;\t// @[ClockDomain.scala:14:9]\n wire [3:0] auto_element_reset_domain_rockettile_trace_core_source_out_priv = 4'h0;\t// @[ClockDomain.scala:14:9]\n wire [3:0] element_reset_domain_auto_rockettile_trace_core_source_out_group_0_itype = 4'h0;\t// @[ClockDomain.scala:14:9]\n wire [3:0] element_reset_domain_auto_rockettile_trace_core_source_out_priv = 4'h0;\t// @[ClockDomain.scala:14:9]\n wire [31:0] auto_element_reset_domain_rockettile_reset_vector_in = 32'h10000;\t// @[ClockDomain.scala:14:9]\n wire [31:0] element_reset_domain_auto_rockettile_reset_vector_in = 32'h10000;\t// @[ClockDomain.scala:14:9]\n wire auto_intsink_out_2_0 = 1'h0;\t// @[ClockDomain.scala:14:9]\n wire auto_intsink_out_0_0 = 1'h0;\t// @[ClockDomain.scala:14:9]\n wire auto_element_reset_domain_rockettile_trace_core_source_out_group_0_iretire = 1'h0;\t// @[ClockDomain.scala:14:9]\n wire auto_element_reset_domain_rockettile_trace_core_source_out_group_0_ilastsize = 1'h0;\t// @[ClockDomain.scala:14:9]\n wire _childClock_T = 1'h0;\t// @[LazyModuleImp.scala:160:25]\n wire element_reset_domain_auto_rockettile_buffer_out_a_bits_corrupt = 1'h0;\t// @[ClockDomain.scala:14:9]\n wire element_reset_domain_auto_rockettile_buffer_out_c_bits_corrupt = 1'h0;\t// @[ClockDomain.scala:14:9]\n wire element_reset_domain_auto_rockettile_cease_out_0 = 1'h0;\t// @[ClockDomain.scala:14:9]\n wire element_reset_domain_auto_rockettile_halt_out_0 = 1'h0;\t// @[ClockDomain.scala:14:9]\n wire element_reset_domain_auto_rockettile_trace_core_source_out_group_0_iretire = 1'h0;\t// @[ClockDomain.scala:14:9]\n wire element_reset_domain_auto_rockettile_trace_core_source_out_group_0_ilastsize = 1'h0;\t// @[ClockDomain.scala:14:9]\n wire element_reset_domain__childClock_T = 1'h0;\t// @[LazyModuleImp.scala:160:25]\n wire clockNode_childClock = 1'h0;\t// @[LazyModuleImp.scala:155:31]\n wire clockNode_childReset = 1'h0;\t// @[LazyModuleImp.scala:158:31]\n wire clockNode__childClock_T = 1'h0;\t// @[LazyModuleImp.scala:160:25]\n wire intOutClockXingOut_sync_0 = 1'h0;\t// @[MixedNode.scala:542:17]\n wire intOutClockXingIn_sync_0 = 1'h0;\t// @[MixedNode.scala:551:17]\n wire intOutClockXingOut_1_sync_0 = 1'h0;\t// @[MixedNode.scala:542:17]\n wire intOutClockXingIn_1_sync_0 = 1'h0;\t// @[MixedNode.scala:551:17]\n wire intOutClockXingOut_4_sync_0 = 1'h0;\t// @[MixedNode.scala:542:17]\n wire intOutClockXingIn_4_sync_0 = 1'h0;\t// @[MixedNode.scala:551:17]\n wire intOutClockXingOut_5_sync_0 = 1'h0;\t// @[MixedNode.scala:542:17]\n wire intOutClockXingIn_5_sync_0 = 1'h0;\t// @[MixedNode.scala:551:17]\n wire element_reset_domain_auto_rockettile_trace_source_out_insns_0_valid;\t// @[ClockDomain.scala:14:9]\n wire [39:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_iaddr;\t// @[ClockDomain.scala:14:9]\n wire [31:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_insn;\t// @[ClockDomain.scala:14:9]\n wire [2:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_priv;\t// @[ClockDomain.scala:14:9]\n wire element_reset_domain_auto_rockettile_trace_source_out_insns_0_exception;\t// @[ClockDomain.scala:14:9]\n wire element_reset_domain_auto_rockettile_trace_source_out_insns_0_interrupt;\t// @[ClockDomain.scala:14:9]\n wire [63:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_cause;\t// @[ClockDomain.scala:14:9]\n wire [39:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_tval;\t// @[ClockDomain.scala:14:9]\n wire [63:0] element_reset_domain_auto_rockettile_trace_source_out_time;\t// @[ClockDomain.scala:14:9]\n wire [2:0] element_reset_domain_auto_rockettile_hartid_in = auto_element_reset_domain_rockettile_hartid_in_0;\t// @[ClockDomain.scala:14:9]\n wire intInClockXingIn_2_sync_0 = auto_int_in_clock_xing_in_2_sync_0_0;\t// @[ClockDomain.scala:14:9]\n wire intInClockXingIn_1_sync_0 = auto_int_in_clock_xing_in_1_sync_0_0;\t// @[ClockDomain.scala:14:9]\n wire intInClockXingIn_sync_0 = auto_int_in_clock_xing_in_0_sync_0_0;\t// @[ClockDomain.scala:14:9]\n wire intInClockXingIn_sync_1 = auto_int_in_clock_xing_in_0_sync_1_0;\t// @[ClockDomain.scala:14:9]\n wire tlMasterClockXingOut_a_ready = auto_tl_master_clock_xing_out_a_ready_0;\t// @[ClockDomain.scala:14:9]\n wire tlMasterClockXingOut_a_valid;\t// @[MixedNode.scala:542:17]\n wire [2:0] tlMasterClockXingOut_a_bits_opcode;\t// @[MixedNode.scala:542:17]\n wire [2:0] tlMasterClockXingOut_a_bits_param;\t// @[MixedNode.scala:542:17]\n wire [3:0] tlMasterClockXingOut_a_bits_size;\t// @[MixedNode.scala:542:17]\n wire [1:0] tlMasterClockXingOut_a_bits_source;\t// @[MixedNode.scala:542:17]\n wire [31:0] tlMasterClockXingOut_a_bits_address;\t// @[MixedNode.scala:542:17]\n wire [7:0] tlMasterClockXingOut_a_bits_mask;\t// @[MixedNode.scala:542:17]\n wire [63:0] tlMasterClockXingOut_a_bits_data;\t// @[MixedNode.scala:542:17]\n wire tlMasterClockXingOut_a_bits_corrupt;\t// @[MixedNode.scala:542:17]\n wire tlMasterClockXingOut_b_ready;\t// @[MixedNode.scala:542:17]\n wire tlMasterClockXingOut_b_valid = auto_tl_master_clock_xing_out_b_valid_0;\t// @[ClockDomain.scala:14:9]\n wire [2:0] tlMasterClockXingOut_b_bits_opcode = auto_tl_master_clock_xing_out_b_bits_opcode_0;\t// @[ClockDomain.scala:14:9]\n wire [1:0] tlMasterClockXingOut_b_bits_param = auto_tl_master_clock_xing_out_b_bits_param_0;\t// @[ClockDomain.scala:14:9]\n wire [3:0] tlMasterClockXingOut_b_bits_size = auto_tl_master_clock_xing_out_b_bits_size_0;\t// @[ClockDomain.scala:14:9]\n wire [1:0] tlMasterClockXingOut_b_bits_source = auto_tl_master_clock_xing_out_b_bits_source_0;\t// @[ClockDomain.scala:14:9]\n wire [31:0] tlMasterClockXingOut_b_bits_address = auto_tl_master_clock_xing_out_b_bits_address_0;\t// @[ClockDomain.scala:14:9]\n wire [7:0] tlMasterClockXingOut_b_bits_mask = auto_tl_master_clock_xing_out_b_bits_mask_0;\t// @[ClockDomain.scala:14:9]\n wire [63:0] tlMasterClockXingOut_b_bits_data = auto_tl_master_clock_xing_out_b_bits_data_0;\t// @[ClockDomain.scala:14:9]\n wire tlMasterClockXingOut_b_bits_corrupt = auto_tl_master_clock_xing_out_b_bits_corrupt_0;\t// @[ClockDomain.scala:14:9]\n wire tlMasterClockXingOut_c_ready = auto_tl_master_clock_xing_out_c_ready_0;\t// @[ClockDomain.scala:14:9]\n wire tlMasterClockXingOut_c_valid;\t// @[MixedNode.scala:542:17]\n wire [2:0] tlMasterClockXingOut_c_bits_opcode;\t// @[MixedNode.scala:542:17]\n wire [2:0] tlMasterClockXingOut_c_bits_param;\t// @[MixedNode.scala:542:17]\n wire [3:0] tlMasterClockXingOut_c_bits_size;\t// @[MixedNode.scala:542:17]\n wire [1:0] tlMasterClockXingOut_c_bits_source;\t// @[MixedNode.scala:542:17]\n wire [31:0] tlMasterClockXingOut_c_bits_address;\t// @[MixedNode.scala:542:17]\n wire [63:0] tlMasterClockXingOut_c_bits_data;\t// @[MixedNode.scala:542:17]\n wire tlMasterClockXingOut_c_bits_corrupt;\t// @[MixedNode.scala:542:17]\n wire tlMasterClockXingOut_d_ready;\t// @[MixedNode.scala:542:17]\n wire tlMasterClockXingOut_d_valid = auto_tl_master_clock_xing_out_d_valid_0;\t// @[ClockDomain.scala:14:9]\n wire [2:0] tlMasterClockXingOut_d_bits_opcode = auto_tl_master_clock_xing_out_d_bits_opcode_0;\t// @[ClockDomain.scala:14:9]\n wire [1:0] tlMasterClockXingOut_d_bits_param = auto_tl_master_clock_xing_out_d_bits_param_0;\t// @[ClockDomain.scala:14:9]\n wire [3:0] tlMasterClockXingOut_d_bits_size = auto_tl_master_clock_xing_out_d_bits_size_0;\t// @[ClockDomain.scala:14:9]\n wire [1:0] tlMasterClockXingOut_d_bits_source = auto_tl_master_clock_xing_out_d_bits_source_0;\t// @[ClockDomain.scala:14:9]\n wire [2:0] tlMasterClockXingOut_d_bits_sink = auto_tl_master_clock_xing_out_d_bits_sink_0;\t// @[ClockDomain.scala:14:9]\n wire tlMasterClockXingOut_d_bits_denied = auto_tl_master_clock_xing_out_d_bits_denied_0;\t// @[ClockDomain.scala:14:9]\n wire [63:0] tlMasterClockXingOut_d_bits_data = auto_tl_master_clock_xing_out_d_bits_data_0;\t// @[ClockDomain.scala:14:9]\n wire tlMasterClockXingOut_d_bits_corrupt = auto_tl_master_clock_xing_out_d_bits_corrupt_0;\t// @[ClockDomain.scala:14:9]\n wire tlMasterClockXingOut_e_ready = auto_tl_master_clock_xing_out_e_ready_0;\t// @[ClockDomain.scala:14:9]\n wire tlMasterClockXingOut_e_valid;\t// @[MixedNode.scala:542:17]\n wire [2:0] tlMasterClockXingOut_e_bits_sink;\t// @[MixedNode.scala:542:17]\n wire tapClockNodeIn_clock = auto_tap_clock_in_clock_0;\t// @[ClockDomain.scala:14:9]\n wire tapClockNodeIn_reset = auto_tap_clock_in_reset_0;\t// @[ClockDomain.scala:14:9]\n wire auto_intsink_out_1_0_0;\t// @[ClockDomain.scala:14:9]\n wire auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid_0;\t// @[ClockDomain.scala:14:9]\n wire [39:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr_0;\t// @[ClockDomain.scala:14:9]\n wire [31:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn_0;\t// @[ClockDomain.scala:14:9]\n wire [2:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv_0;\t// @[ClockDomain.scala:14:9]\n wire auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception_0;\t// @[ClockDomain.scala:14:9]\n wire auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt_0;\t// @[ClockDomain.scala:14:9]\n wire [63:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause_0;\t// @[ClockDomain.scala:14:9]\n wire [39:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval_0;\t// @[ClockDomain.scala:14:9]\n wire [63:0] auto_element_reset_domain_rockettile_trace_source_out_time_0;\t// @[ClockDomain.scala:14:9]\n wire [2:0] auto_tl_master_clock_xing_out_a_bits_opcode_0;\t// @[ClockDomain.scala:14:9]\n wire [2:0] auto_tl_master_clock_xing_out_a_bits_param_0;\t// @[ClockDomain.scala:14:9]\n wire [3:0] auto_tl_master_clock_xing_out_a_bits_size_0;\t// @[ClockDomain.scala:14:9]\n wire [1:0] auto_tl_master_clock_xing_out_a_bits_source_0;\t// @[ClockDomain.scala:14:9]\n wire [31:0] auto_tl_master_clock_xing_out_a_bits_address_0;\t// @[ClockDomain.scala:14:9]\n wire [7:0] auto_tl_master_clock_xing_out_a_bits_mask_0;\t// @[ClockDomain.scala:14:9]\n wire [63:0] auto_tl_master_clock_xing_out_a_bits_data_0;\t// @[ClockDomain.scala:14:9]\n wire auto_tl_master_clock_xing_out_a_bits_corrupt_0;\t// @[ClockDomain.scala:14:9]\n wire auto_tl_master_clock_xing_out_a_valid_0;\t// @[ClockDomain.scala:14:9]\n wire auto_tl_master_clock_xing_out_b_ready_0;\t// @[ClockDomain.scala:14:9]\n wire [2:0] auto_tl_master_clock_xing_out_c_bits_opcode_0;\t// @[ClockDomain.scala:14:9]\n wire [2:0] auto_tl_master_clock_xing_out_c_bits_param_0;\t// @[ClockDomain.scala:14:9]\n wire [3:0] auto_tl_master_clock_xing_out_c_bits_size_0;\t// @[ClockDomain.scala:14:9]\n wire [1:0] auto_tl_master_clock_xing_out_c_bits_source_0;\t// @[ClockDomain.scala:14:9]\n wire [31:0] auto_tl_master_clock_xing_out_c_bits_address_0;\t// @[ClockDomain.scala:14:9]\n wire [63:0] auto_tl_master_clock_xing_out_c_bits_data_0;\t// @[ClockDomain.scala:14:9]\n wire auto_tl_master_clock_xing_out_c_bits_corrupt_0;\t// @[ClockDomain.scala:14:9]\n wire auto_tl_master_clock_xing_out_c_valid_0;\t// @[ClockDomain.scala:14:9]\n wire auto_tl_master_clock_xing_out_d_ready_0;\t// @[ClockDomain.scala:14:9]\n wire [2:0] auto_tl_master_clock_xing_out_e_bits_sink_0;\t// @[ClockDomain.scala:14:9]\n wire auto_tl_master_clock_xing_out_e_valid_0;\t// @[ClockDomain.scala:14:9]\n wire childClock;\t// @[LazyModuleImp.scala:155:31]\n wire childReset;\t// @[LazyModuleImp.scala:158:31]\n assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_valid;\t// @[ClockDomain.scala:14:9]\n assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_iaddr;\t// @[ClockDomain.scala:14:9]\n assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_insn;\t// @[ClockDomain.scala:14:9]\n assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_priv;\t// @[ClockDomain.scala:14:9]\n assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_exception;\t// @[ClockDomain.scala:14:9]\n assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_interrupt;\t// @[ClockDomain.scala:14:9]\n assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_cause;\t// @[ClockDomain.scala:14:9]\n assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_tval;\t// @[ClockDomain.scala:14:9]\n assign auto_element_reset_domain_rockettile_trace_source_out_time_0 = element_reset_domain_auto_rockettile_trace_source_out_time;\t// @[ClockDomain.scala:14:9]\n wire clockNode_auto_anon_out_clock;\t// @[ClockGroup.scala:104:9]\n wire element_reset_domain_clockNodeIn_clock = element_reset_domain_auto_clock_in_clock;\t// @[ClockDomain.scala:14:9]\n wire clockNode_auto_anon_out_reset;\t// @[ClockGroup.scala:104:9]\n wire [2:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_opcode;\t// @[ClockDomain.scala:14:9]\n wire [2:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_param;\t// @[ClockDomain.scala:14:9]\n wire [3:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_size;\t// @[ClockDomain.scala:14:9]\n wire [1:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_source;\t// @[ClockDomain.scala:14:9]\n wire [31:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_address;\t// @[ClockDomain.scala:14:9]\n wire [7:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_mask;\t// @[ClockDomain.scala:14:9]\n wire [63:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_data;\t// @[ClockDomain.scala:14:9]\n wire element_reset_domain_clockNodeIn_reset = element_reset_domain_auto_clock_in_reset;\t// @[ClockDomain.scala:14:9]\n wire element_reset_domain_auto_rockettile_buffer_out_a_ready;\t// @[ClockDomain.scala:14:9]\n wire element_reset_domain_auto_rockettile_buffer_out_a_valid;\t// @[ClockDomain.scala:14:9]\n wire [2:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_opcode;\t// @[ClockDomain.scala:14:9]\n wire [1:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_param;\t// @[ClockDomain.scala:14:9]\n wire [3:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_size;\t// @[ClockDomain.scala:14:9]\n wire [1:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_source;\t// @[ClockDomain.scala:14:9]\n wire [31:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_address;\t// @[ClockDomain.scala:14:9]\n wire [7:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_mask;\t// @[ClockDomain.scala:14:9]\n wire [63:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_data;\t// @[ClockDomain.scala:14:9]\n wire element_reset_domain_auto_rockettile_buffer_out_b_bits_corrupt;\t// @[ClockDomain.scala:14:9]\n wire element_reset_domain_auto_rockettile_buffer_out_b_ready;\t// @[ClockDomain.scala:14:9]\n wire element_reset_domain_auto_rockettile_buffer_out_b_valid;\t// @[ClockDomain.scala:14:9]\n wire [2:0] element_reset_domain_auto_rockettile_buffer_out_c_bits_opcode;\t// @[ClockDomain.scala:14:9]\n wire [2:0] element_reset_domain_auto_rockettile_buffer_out_c_bits_param;\t// @[ClockDomain.scala:14:9]\n wire [3:0] element_reset_domain_auto_rockettile_buffer_out_c_bits_size;\t// @[ClockDomain.scala:14:9]\n wire [1:0] element_reset_domain_auto_rockettile_buffer_out_c_bits_source;\t// @[ClockDomain.scala:14:9]\n wire [31:0] element_reset_domain_auto_rockettile_buffer_out_c_bits_address;\t// @[ClockDomain.scala:14:9]\n wire [63:0] element_reset_domain_auto_rockettile_buffer_out_c_bits_data;\t// @[ClockDomain.scala:14:9]\n wire element_reset_domain_auto_rockettile_buffer_out_c_ready;\t// @[ClockDomain.scala:14:9]\n wire element_reset_domain_auto_rockettile_buffer_out_c_valid;\t// @[ClockDomain.scala:14:9]\n wire [2:0] element_reset_domain_auto_rockettile_buffer_out_d_bits_opcode;\t// @[ClockDomain.scala:14:9]\n wire [1:0] element_reset_domain_auto_rockettile_buffer_out_d_bits_param;\t// @[ClockDomain.scala:14:9]\n wire [3:0] element_reset_domain_auto_rockettile_buffer_out_d_bits_size;\t// @[ClockDomain.scala:14:9]\n wire [1:0] element_reset_domain_auto_rockettile_buffer_out_d_bits_source;\t// @[ClockDomain.scala:14:9]\n wire [2:0] element_reset_domain_auto_rockettile_buffer_out_d_bits_sink;\t// @[ClockDomain.scala:14:9]\n wire element_reset_domain_auto_rockettile_buffer_out_d_bits_denied;\t// @[ClockDomain.scala:14:9]\n wire [63:0] element_reset_domain_auto_rockettile_buffer_out_d_bits_data;\t// @[ClockDomain.scala:14:9]\n wire element_reset_domain_auto_rockettile_buffer_out_d_bits_corrupt;\t// @[ClockDomain.scala:14:9]\n wire element_reset_domain_auto_rockettile_buffer_out_d_ready;\t// @[ClockDomain.scala:14:9]\n wire element_reset_domain_auto_rockettile_buffer_out_d_valid;\t// @[ClockDomain.scala:14:9]\n wire [2:0] element_reset_domain_auto_rockettile_buffer_out_e_bits_sink;\t// @[ClockDomain.scala:14:9]\n wire element_reset_domain_auto_rockettile_buffer_out_e_ready;\t// @[ClockDomain.scala:14:9]\n wire element_reset_domain_auto_rockettile_buffer_out_e_valid;\t// @[ClockDomain.scala:14:9]\n wire element_reset_domain_auto_rockettile_wfi_out_0;\t// @[ClockDomain.scala:14:9]\n wire element_reset_domain_auto_rockettile_int_local_in_3_0;\t// @[ClockDomain.scala:14:9]\n wire element_reset_domain_auto_rockettile_int_local_in_2_0;\t// @[ClockDomain.scala:14:9]\n wire element_reset_domain_auto_rockettile_int_local_in_1_0;\t// @[ClockDomain.scala:14:9]\n wire element_reset_domain_auto_rockettile_int_local_in_1_1;\t// @[ClockDomain.scala:14:9]\n wire element_reset_domain_auto_rockettile_int_local_in_0_0;\t// @[ClockDomain.scala:14:9]\n wire element_reset_domain_childClock;\t// @[LazyModuleImp.scala:155:31]\n wire element_reset_domain_childReset;\t// @[LazyModuleImp.scala:158:31]\n assign element_reset_domain_childClock = element_reset_domain_clockNodeIn_clock;\t// @[MixedNode.scala:551:17]\n assign element_reset_domain_childReset = element_reset_domain_clockNodeIn_reset;\t// @[MixedNode.scala:551:17]\n wire tapClockNodeOut_clock;\t// @[MixedNode.scala:542:17]\n wire clockNode_anonIn_clock = clockNode_auto_anon_in_clock;\t// @[ClockGroup.scala:104:9]\n wire tapClockNodeOut_reset;\t// @[MixedNode.scala:542:17]\n wire clockNode_anonOut_clock;\t// @[MixedNode.scala:542:17]\n wire clockNode_anonIn_reset = clockNode_auto_anon_in_reset;\t// @[ClockGroup.scala:104:9]\n assign element_reset_domain_auto_clock_in_clock = clockNode_auto_anon_out_clock;\t// @[ClockGroup.scala:104:9]\n wire clockNode_anonOut_reset;\t// @[MixedNode.scala:542:17]\n assign element_reset_domain_auto_clock_in_reset = clockNode_auto_anon_out_reset;\t// @[ClockGroup.scala:104:9]\n assign clockNode_auto_anon_out_clock = clockNode_anonOut_clock;\t// @[ClockGroup.scala:104:9]\n assign clockNode_auto_anon_out_reset = clockNode_anonOut_reset;\t// @[ClockGroup.scala:104:9]\n assign clockNode_anonOut_clock = clockNode_anonIn_clock;\t// @[MixedNode.scala:542:17, :551:17]\n assign clockNode_anonOut_reset = clockNode_anonIn_reset;\t// @[MixedNode.scala:542:17, :551:17]\n assign clockNode_auto_anon_in_clock = tapClockNodeOut_clock;\t// @[ClockGroup.scala:104:9]\n assign clockNode_auto_anon_in_reset = tapClockNodeOut_reset;\t// @[ClockGroup.scala:104:9]\n assign childClock = tapClockNodeIn_clock;\t// @[MixedNode.scala:551:17]\n assign tapClockNodeOut_clock = tapClockNodeIn_clock;\t// @[MixedNode.scala:542:17, :551:17]\n assign childReset = tapClockNodeIn_reset;\t// @[MixedNode.scala:551:17]\n assign tapClockNodeOut_reset = tapClockNodeIn_reset;\t// @[MixedNode.scala:542:17, :551:17]\n wire tlMasterClockXingIn_a_ready = tlMasterClockXingOut_a_ready;\t// @[MixedNode.scala:542:17, :551:17]\n wire tlMasterClockXingIn_a_valid;\t// @[MixedNode.scala:551:17]\n assign auto_tl_master_clock_xing_out_a_valid_0 = tlMasterClockXingOut_a_valid;\t// @[ClockDomain.scala:14:9]\n wire [2:0] tlMasterClockXingIn_a_bits_opcode;\t// @[MixedNode.scala:551:17]\n assign auto_tl_master_clock_xing_out_a_bits_opcode_0 = tlMasterClockXingOut_a_bits_opcode;\t// @[ClockDomain.scala:14:9]\n wire [2:0] tlMasterClockXingIn_a_bits_param;\t// @[MixedNode.scala:551:17]\n assign auto_tl_master_clock_xing_out_a_bits_param_0 = tlMasterClockXingOut_a_bits_param;\t// @[ClockDomain.scala:14:9]\n wire [3:0] tlMasterClockXingIn_a_bits_size;\t// @[MixedNode.scala:551:17]\n assign auto_tl_master_clock_xing_out_a_bits_size_0 = tlMasterClockXingOut_a_bits_size;\t// @[ClockDomain.scala:14:9]\n wire [1:0] tlMasterClockXingIn_a_bits_source;\t// @[MixedNode.scala:551:17]\n assign auto_tl_master_clock_xing_out_a_bits_source_0 = tlMasterClockXingOut_a_bits_source;\t// @[ClockDomain.scala:14:9]\n wire [31:0] tlMasterClockXingIn_a_bits_address;\t// @[MixedNode.scala:551:17]\n assign auto_tl_master_clock_xing_out_a_bits_address_0 = tlMasterClockXingOut_a_bits_address;\t// @[ClockDomain.scala:14:9]\n wire [7:0] tlMasterClockXingIn_a_bits_mask;\t// @[MixedNode.scala:551:17]\n assign auto_tl_master_clock_xing_out_a_bits_mask_0 = tlMasterClockXingOut_a_bits_mask;\t// @[ClockDomain.scala:14:9]\n wire [63:0] tlMasterClockXingIn_a_bits_data;\t// @[MixedNode.scala:551:17]\n assign auto_tl_master_clock_xing_out_a_bits_data_0 = tlMasterClockXingOut_a_bits_data;\t// @[ClockDomain.scala:14:9]\n wire tlMasterClockXingIn_a_bits_corrupt;\t// @[MixedNode.scala:551:17]\n assign auto_tl_master_clock_xing_out_a_bits_corrupt_0 = tlMasterClockXingOut_a_bits_corrupt;\t// @[ClockDomain.scala:14:9]\n wire tlMasterClockXingIn_b_ready;\t// @[MixedNode.scala:551:17]\n assign auto_tl_master_clock_xing_out_b_ready_0 = tlMasterClockXingOut_b_ready;\t// @[ClockDomain.scala:14:9]\n wire tlMasterClockXingIn_b_valid = tlMasterClockXingOut_b_valid;\t// @[MixedNode.scala:542:17, :551:17]\n wire [2:0] tlMasterClockXingIn_b_bits_opcode = tlMasterClockXingOut_b_bits_opcode;\t// @[MixedNode.scala:542:17, :551:17]\n wire [1:0] tlMasterClockXingIn_b_bits_param = tlMasterClockXingOut_b_bits_param;\t// @[MixedNode.scala:542:17, :551:17]\n wire [3:0] tlMasterClockXingIn_b_bits_size = tlMasterClockXingOut_b_bits_size;\t// @[MixedNode.scala:542:17, :551:17]\n wire [1:0] tlMasterClockXingIn_b_bits_source = tlMasterClockXingOut_b_bits_source;\t// @[MixedNode.scala:542:17, :551:17]\n wire [31:0] tlMasterClockXingIn_b_bits_address = tlMasterClockXingOut_b_bits_address;\t// @[MixedNode.scala:542:17, :551:17]\n wire [7:0] tlMasterClockXingIn_b_bits_mask = tlMasterClockXingOut_b_bits_mask;\t// @[MixedNode.scala:542:17, :551:17]\n wire [63:0] tlMasterClockXingIn_b_bits_data = tlMasterClockXingOut_b_bits_data;\t// @[MixedNode.scala:542:17, :551:17]\n wire tlMasterClockXingIn_b_bits_corrupt = tlMasterClockXingOut_b_bits_corrupt;\t// @[MixedNode.scala:542:17, :551:17]\n wire tlMasterClockXingIn_c_ready = tlMasterClockXingOut_c_ready;\t// @[MixedNode.scala:542:17, :551:17]\n wire tlMasterClockXingIn_c_valid;\t// @[MixedNode.scala:551:17]\n assign auto_tl_master_clock_xing_out_c_valid_0 = tlMasterClockXingOut_c_valid;\t// @[ClockDomain.scala:14:9]\n wire [2:0] tlMasterClockXingIn_c_bits_opcode;\t// @[MixedNode.scala:551:17]\n assign auto_tl_master_clock_xing_out_c_bits_opcode_0 = tlMasterClockXingOut_c_bits_opcode;\t// @[ClockDomain.scala:14:9]\n wire [2:0] tlMasterClockXingIn_c_bits_param;\t// @[MixedNode.scala:551:17]\n assign auto_tl_master_clock_xing_out_c_bits_param_0 = tlMasterClockXingOut_c_bits_param;\t// @[ClockDomain.scala:14:9]\n wire [3:0] tlMasterClockXingIn_c_bits_size;\t// @[MixedNode.scala:551:17]\n assign auto_tl_master_clock_xing_out_c_bits_size_0 = tlMasterClockXingOut_c_bits_size;\t// @[ClockDomain.scala:14:9]\n wire [1:0] tlMasterClockXingIn_c_bits_source;\t// @[MixedNode.scala:551:17]\n assign auto_tl_master_clock_xing_out_c_bits_source_0 = tlMasterClockXingOut_c_bits_source;\t// @[ClockDomain.scala:14:9]\n wire [31:0] tlMasterClockXingIn_c_bits_address;\t// @[MixedNode.scala:551:17]\n assign auto_tl_master_clock_xing_out_c_bits_address_0 = tlMasterClockXingOut_c_bits_address;\t// @[ClockDomain.scala:14:9]\n wire [63:0] tlMasterClockXingIn_c_bits_data;\t// @[MixedNode.scala:551:17]\n assign auto_tl_master_clock_xing_out_c_bits_data_0 = tlMasterClockXingOut_c_bits_data;\t// @[ClockDomain.scala:14:9]\n wire tlMasterClockXingIn_c_bits_corrupt;\t// @[MixedNode.scala:551:17]\n assign auto_tl_master_clock_xing_out_c_bits_corrupt_0 = tlMasterClockXingOut_c_bits_corrupt;\t// @[ClockDomain.scala:14:9]\n wire tlMasterClockXingIn_d_ready;\t// @[MixedNode.scala:551:17]\n assign auto_tl_master_clock_xing_out_d_ready_0 = tlMasterClockXingOut_d_ready;\t// @[ClockDomain.scala:14:9]\n wire tlMasterClockXingIn_d_valid = tlMasterClockXingOut_d_valid;\t// @[MixedNode.scala:542:17, :551:17]\n wire [2:0] tlMasterClockXingIn_d_bits_opcode = tlMasterClockXingOut_d_bits_opcode;\t// @[MixedNode.scala:542:17, :551:17]\n wire [1:0] tlMasterClockXingIn_d_bits_param = tlMasterClockXingOut_d_bits_param;\t// @[MixedNode.scala:542:17, :551:17]\n wire [3:0] tlMasterClockXingIn_d_bits_size = tlMasterClockXingOut_d_bits_size;\t// @[MixedNode.scala:542:17, :551:17]\n wire [1:0] tlMasterClockXingIn_d_bits_source = tlMasterClockXingOut_d_bits_source;\t// @[MixedNode.scala:542:17, :551:17]\n wire [2:0] tlMasterClockXingIn_d_bits_sink = tlMasterClockXingOut_d_bits_sink;\t// @[MixedNode.scala:542:17, :551:17]\n wire tlMasterClockXingIn_d_bits_denied = tlMasterClockXingOut_d_bits_denied;\t// @[MixedNode.scala:542:17, :551:17]\n wire [63:0] tlMasterClockXingIn_d_bits_data = tlMasterClockXingOut_d_bits_data;\t// @[MixedNode.scala:542:17, :551:17]\n wire tlMasterClockXingIn_d_bits_corrupt = tlMasterClockXingOut_d_bits_corrupt;\t// @[MixedNode.scala:542:17, :551:17]\n wire tlMasterClockXingIn_e_ready = tlMasterClockXingOut_e_ready;\t// @[MixedNode.scala:542:17, :551:17]\n wire tlMasterClockXingIn_e_valid;\t// @[MixedNode.scala:551:17]\n assign auto_tl_master_clock_xing_out_e_valid_0 = tlMasterClockXingOut_e_valid;\t// @[ClockDomain.scala:14:9]\n wire [2:0] tlMasterClockXingIn_e_bits_sink;\t// @[MixedNode.scala:551:17]\n assign auto_tl_master_clock_xing_out_e_bits_sink_0 = tlMasterClockXingOut_e_bits_sink;\t// @[ClockDomain.scala:14:9]\n assign tlMasterClockXingOut_a_valid = tlMasterClockXingIn_a_valid;\t// @[MixedNode.scala:542:17, :551:17]\n assign tlMasterClockXingOut_a_bits_opcode = tlMasterClockXingIn_a_bits_opcode;\t// @[MixedNode.scala:542:17, :551:17]\n assign tlMasterClockXingOut_a_bits_param = tlMasterClockXingIn_a_bits_param;\t// @[MixedNode.scala:542:17, :551:17]\n assign tlMasterClockXingOut_a_bits_size = tlMasterClockXingIn_a_bits_size;\t// @[MixedNode.scala:542:17, :551:17]\n assign tlMasterClockXingOut_a_bits_source = tlMasterClockXingIn_a_bits_source;\t// @[MixedNode.scala:542:17, :551:17]\n assign tlMasterClockXingOut_a_bits_address = tlMasterClockXingIn_a_bits_address;\t// @[MixedNode.scala:542:17, :551:17]\n assign tlMasterClockXingOut_a_bits_mask = tlMasterClockXingIn_a_bits_mask;\t// @[MixedNode.scala:542:17, :551:17]\n assign tlMasterClockXingOut_a_bits_data = tlMasterClockXingIn_a_bits_data;\t// @[MixedNode.scala:542:17, :551:17]\n assign tlMasterClockXingOut_a_bits_corrupt = tlMasterClockXingIn_a_bits_corrupt;\t// @[MixedNode.scala:542:17, :551:17]\n assign tlMasterClockXingOut_b_ready = tlMasterClockXingIn_b_ready;\t// @[MixedNode.scala:542:17, :551:17]\n assign tlMasterClockXingOut_c_valid = tlMasterClockXingIn_c_valid;\t// @[MixedNode.scala:542:17, :551:17]\n assign tlMasterClockXingOut_c_bits_opcode = tlMasterClockXingIn_c_bits_opcode;\t// @[MixedNode.scala:542:17, :551:17]\n assign tlMasterClockXingOut_c_bits_param = tlMasterClockXingIn_c_bits_param;\t// @[MixedNode.scala:542:17, :551:17]\n assign tlMasterClockXingOut_c_bits_size = tlMasterClockXingIn_c_bits_size;\t// @[MixedNode.scala:542:17, :551:17]\n assign tlMasterClockXingOut_c_bits_source = tlMasterClockXingIn_c_bits_source;\t// @[MixedNode.scala:542:17, :551:17]\n assign tlMasterClockXingOut_c_bits_address = tlMasterClockXingIn_c_bits_address;\t// @[MixedNode.scala:542:17, :551:17]\n assign tlMasterClockXingOut_c_bits_data = tlMasterClockXingIn_c_bits_data;\t// @[MixedNode.scala:542:17, :551:17]\n assign tlMasterClockXingOut_c_bits_corrupt = tlMasterClockXingIn_c_bits_corrupt;\t// @[MixedNode.scala:542:17, :551:17]\n assign tlMasterClockXingOut_d_ready = tlMasterClockXingIn_d_ready;\t// @[MixedNode.scala:542:17, :551:17]\n assign tlMasterClockXingOut_e_valid = tlMasterClockXingIn_e_valid;\t// @[MixedNode.scala:542:17, :551:17]\n assign tlMasterClockXingOut_e_bits_sink = tlMasterClockXingIn_e_bits_sink;\t// @[MixedNode.scala:542:17, :551:17]\n wire intInClockXingOut_sync_0;\t// @[MixedNode.scala:542:17]\n wire intInClockXingOut_sync_1;\t// @[MixedNode.scala:542:17]\n assign intInClockXingOut_sync_0 = intInClockXingIn_sync_0;\t// @[MixedNode.scala:542:17, :551:17]\n assign intInClockXingOut_sync_1 = intInClockXingIn_sync_1;\t// @[MixedNode.scala:542:17, :551:17]\n wire intInClockXingOut_1_sync_0;\t// @[MixedNode.scala:542:17]\n assign intInClockXingOut_1_sync_0 = intInClockXingIn_1_sync_0;\t// @[MixedNode.scala:542:17, :551:17]\n wire intInClockXingOut_2_sync_0;\t// @[MixedNode.scala:542:17]\n assign intInClockXingOut_2_sync_0 = intInClockXingIn_2_sync_0;\t// @[MixedNode.scala:542:17, :551:17]\n wire intOutClockXingIn_2_sync_0;\t// @[MixedNode.scala:551:17]\n wire intOutClockXingOut_2_sync_0;\t// @[MixedNode.scala:542:17]\n wire intOutClockXingOut_3_sync_0;\t// @[MixedNode.scala:542:17]\n assign intOutClockXingOut_2_sync_0 = intOutClockXingIn_2_sync_0;\t// @[MixedNode.scala:542:17, :551:17]\n wire intOutClockXingIn_3_sync_0;\t// @[MixedNode.scala:551:17]\n assign intOutClockXingIn_2_sync_0 = intOutClockXingOut_3_sync_0;\t// @[MixedNode.scala:542:17, :551:17]\n assign intOutClockXingOut_3_sync_0 = intOutClockXingIn_3_sync_0;\t// @[MixedNode.scala:542:17, :551:17]\n RocketTile_1 element_reset_domain_rockettile (\t// @[HasTiles.scala:164:59]\n .clock (element_reset_domain_childClock),\t// @[LazyModuleImp.scala:155:31]\n .reset (element_reset_domain_childReset),\t// @[LazyModuleImp.scala:158:31]\n .auto_buffer_out_a_ready (element_reset_domain_auto_rockettile_buffer_out_a_ready),\t// @[ClockDomain.scala:14:9]\n .auto_buffer_out_a_valid (element_reset_domain_auto_rockettile_buffer_out_a_valid),\n .auto_buffer_out_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_a_bits_opcode),\n .auto_buffer_out_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_a_bits_param),\n .auto_buffer_out_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_a_bits_size),\n .auto_buffer_out_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_a_bits_source),\n .auto_buffer_out_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_a_bits_address),\n .auto_buffer_out_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_a_bits_mask),\n .auto_buffer_out_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_a_bits_data),\n .auto_buffer_out_b_ready (element_reset_domain_auto_rockettile_buffer_out_b_ready),\n .auto_buffer_out_b_valid (element_reset_domain_auto_rockettile_buffer_out_b_valid),\t// @[ClockDomain.scala:14:9]\n .auto_buffer_out_b_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_b_bits_opcode),\t// @[ClockDomain.scala:14:9]\n .auto_buffer_out_b_bits_param (element_reset_domain_auto_rockettile_buffer_out_b_bits_param),\t// @[ClockDomain.scala:14:9]\n .auto_buffer_out_b_bits_size (element_reset_domain_auto_rockettile_buffer_out_b_bits_size),\t// @[ClockDomain.scala:14:9]\n .auto_buffer_out_b_bits_source (element_reset_domain_auto_rockettile_buffer_out_b_bits_source),\t// @[ClockDomain.scala:14:9]\n .auto_buffer_out_b_bits_address (element_reset_domain_auto_rockettile_buffer_out_b_bits_address),\t// @[ClockDomain.scala:14:9]\n .auto_buffer_out_b_bits_mask (element_reset_domain_auto_rockettile_buffer_out_b_bits_mask),\t// @[ClockDomain.scala:14:9]\n .auto_buffer_out_b_bits_data (element_reset_domain_auto_rockettile_buffer_out_b_bits_data),\t// @[ClockDomain.scala:14:9]\n .auto_buffer_out_b_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_b_bits_corrupt),\t// @[ClockDomain.scala:14:9]\n .auto_buffer_out_c_ready (element_reset_domain_auto_rockettile_buffer_out_c_ready),\t// @[ClockDomain.scala:14:9]\n .auto_buffer_out_c_valid (element_reset_domain_auto_rockettile_buffer_out_c_valid),\n .auto_buffer_out_c_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_c_bits_opcode),\n .auto_buffer_out_c_bits_param (element_reset_domain_auto_rockettile_buffer_out_c_bits_param),\n .auto_buffer_out_c_bits_size (element_reset_domain_auto_rockettile_buffer_out_c_bits_size),\n .auto_buffer_out_c_bits_source (element_reset_domain_auto_rockettile_buffer_out_c_bits_source),\n .auto_buffer_out_c_bits_address (element_reset_domain_auto_rockettile_buffer_out_c_bits_address),\n .auto_buffer_out_c_bits_data (element_reset_domain_auto_rockettile_buffer_out_c_bits_data),\n .auto_buffer_out_d_ready (element_reset_domain_auto_rockettile_buffer_out_d_ready),\n .auto_buffer_out_d_valid (element_reset_domain_auto_rockettile_buffer_out_d_valid),\t// @[ClockDomain.scala:14:9]\n .auto_buffer_out_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_d_bits_opcode),\t// @[ClockDomain.scala:14:9]\n .auto_buffer_out_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_d_bits_param),\t// @[ClockDomain.scala:14:9]\n .auto_buffer_out_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_d_bits_size),\t// @[ClockDomain.scala:14:9]\n .auto_buffer_out_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_d_bits_source),\t// @[ClockDomain.scala:14:9]\n .auto_buffer_out_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_d_bits_sink),\t// @[ClockDomain.scala:14:9]\n .auto_buffer_out_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_d_bits_denied),\t// @[ClockDomain.scala:14:9]\n .auto_buffer_out_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_d_bits_data),\t// @[ClockDomain.scala:14:9]\n .auto_buffer_out_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_d_bits_corrupt),\t// @[ClockDomain.scala:14:9]\n .auto_buffer_out_e_ready (element_reset_domain_auto_rockettile_buffer_out_e_ready),\t// @[ClockDomain.scala:14:9]\n .auto_buffer_out_e_valid (element_reset_domain_auto_rockettile_buffer_out_e_valid),\n .auto_buffer_out_e_bits_sink (element_reset_domain_auto_rockettile_buffer_out_e_bits_sink),\n .auto_wfi_out_0 (element_reset_domain_auto_rockettile_wfi_out_0),\n .auto_int_local_in_3_0 (element_reset_domain_auto_rockettile_int_local_in_3_0),\t// @[ClockDomain.scala:14:9]\n .auto_int_local_in_2_0 (element_reset_domain_auto_rockettile_int_local_in_2_0),\t// @[ClockDomain.scala:14:9]\n .auto_int_local_in_1_0 (element_reset_domain_auto_rockettile_int_local_in_1_0),\t// @[ClockDomain.scala:14:9]\n .auto_int_local_in_1_1 (element_reset_domain_auto_rockettile_int_local_in_1_1),\t// @[ClockDomain.scala:14:9]\n .auto_int_local_in_0_0 (element_reset_domain_auto_rockettile_int_local_in_0_0),\t// @[ClockDomain.scala:14:9]\n .auto_trace_source_out_insns_0_valid (element_reset_domain_auto_rockettile_trace_source_out_insns_0_valid),\n .auto_trace_source_out_insns_0_iaddr (element_reset_domain_auto_rockettile_trace_source_out_insns_0_iaddr),\n .auto_trace_source_out_insns_0_insn (element_reset_domain_auto_rockettile_trace_source_out_insns_0_insn),\n .auto_trace_source_out_insns_0_priv (element_reset_domain_auto_rockettile_trace_source_out_insns_0_priv),\n .auto_trace_source_out_insns_0_exception (element_reset_domain_auto_rockettile_trace_source_out_insns_0_exception),\n .auto_trace_source_out_insns_0_interrupt (element_reset_domain_auto_rockettile_trace_source_out_insns_0_interrupt),\n .auto_trace_source_out_insns_0_cause (element_reset_domain_auto_rockettile_trace_source_out_insns_0_cause),\n .auto_trace_source_out_insns_0_tval (element_reset_domain_auto_rockettile_trace_source_out_insns_0_tval),\n .auto_trace_source_out_time (element_reset_domain_auto_rockettile_trace_source_out_time),\n .auto_hartid_in (element_reset_domain_auto_rockettile_hartid_in)\t// @[ClockDomain.scala:14:9]\n );\t// @[HasTiles.scala:164:59]\n TLBuffer_a32d64s2k3z4c_3 buffer (\t// @[Buffer.scala:75:28]\n .clock (childClock),\t// @[LazyModuleImp.scala:155:31]\n .reset (childReset),\t// @[LazyModuleImp.scala:158:31]\n .auto_in_a_ready (element_reset_domain_auto_rockettile_buffer_out_a_ready),\n .auto_in_a_valid (element_reset_domain_auto_rockettile_buffer_out_a_valid),\t// @[ClockDomain.scala:14:9]\n .auto_in_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_a_bits_opcode),\t// @[ClockDomain.scala:14:9]\n .auto_in_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_a_bits_param),\t// @[ClockDomain.scala:14:9]\n .auto_in_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_a_bits_size),\t// @[ClockDomain.scala:14:9]\n .auto_in_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_a_bits_source),\t// @[ClockDomain.scala:14:9]\n .auto_in_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_a_bits_address),\t// @[ClockDomain.scala:14:9]\n .auto_in_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_a_bits_mask),\t// @[ClockDomain.scala:14:9]\n .auto_in_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_a_bits_data),\t// @[ClockDomain.scala:14:9]\n .auto_in_b_ready (element_reset_domain_auto_rockettile_buffer_out_b_ready),\t// @[ClockDomain.scala:14:9]\n .auto_in_b_valid (element_reset_domain_auto_rockettile_buffer_out_b_valid),\n .auto_in_b_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_b_bits_opcode),\n .auto_in_b_bits_param (element_reset_domain_auto_rockettile_buffer_out_b_bits_param),\n .auto_in_b_bits_size (element_reset_domain_auto_rockettile_buffer_out_b_bits_size),\n .auto_in_b_bits_source (element_reset_domain_auto_rockettile_buffer_out_b_bits_source),\n .auto_in_b_bits_address (element_reset_domain_auto_rockettile_buffer_out_b_bits_address),\n .auto_in_b_bits_mask (element_reset_domain_auto_rockettile_buffer_out_b_bits_mask),\n .auto_in_b_bits_data (element_reset_domain_auto_rockettile_buffer_out_b_bits_data),\n .auto_in_b_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_b_bits_corrupt),\n .auto_in_c_ready (element_reset_domain_auto_rockettile_buffer_out_c_ready),\n .auto_in_c_valid (element_reset_domain_auto_rockettile_buffer_out_c_valid),\t// @[ClockDomain.scala:14:9]\n .auto_in_c_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_c_bits_opcode),\t// @[ClockDomain.scala:14:9]\n .auto_in_c_bits_param (element_reset_domain_auto_rockettile_buffer_out_c_bits_param),\t// @[ClockDomain.scala:14:9]\n .auto_in_c_bits_size (element_reset_domain_auto_rockettile_buffer_out_c_bits_size),\t// @[ClockDomain.scala:14:9]\n .auto_in_c_bits_source (element_reset_domain_auto_rockettile_buffer_out_c_bits_source),\t// @[ClockDomain.scala:14:9]\n .auto_in_c_bits_address (element_reset_domain_auto_rockettile_buffer_out_c_bits_address),\t// @[ClockDomain.scala:14:9]\n .auto_in_c_bits_data (element_reset_domain_auto_rockettile_buffer_out_c_bits_data),\t// @[ClockDomain.scala:14:9]\n .auto_in_d_ready (element_reset_domain_auto_rockettile_buffer_out_d_ready),\t// @[ClockDomain.scala:14:9]\n .auto_in_d_valid (element_reset_domain_auto_rockettile_buffer_out_d_valid),\n .auto_in_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_d_bits_opcode),\n .auto_in_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_d_bits_param),\n .auto_in_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_d_bits_size),\n .auto_in_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_d_bits_source),\n .auto_in_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_d_bits_sink),\n .auto_in_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_d_bits_denied),\n .auto_in_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_d_bits_data),\n .auto_in_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_d_bits_corrupt),\n .auto_in_e_ready (element_reset_domain_auto_rockettile_buffer_out_e_ready),\n .auto_in_e_valid (element_reset_domain_auto_rockettile_buffer_out_e_valid),\t// @[ClockDomain.scala:14:9]\n .auto_in_e_bits_sink (element_reset_domain_auto_rockettile_buffer_out_e_bits_sink),\t// @[ClockDomain.scala:14:9]\n .auto_out_a_ready (tlMasterClockXingIn_a_ready),\t// @[MixedNode.scala:551:17]\n .auto_out_a_valid (tlMasterClockXingIn_a_valid),\n .auto_out_a_bits_opcode (tlMasterClockXingIn_a_bits_opcode),\n .auto_out_a_bits_param (tlMasterClockXingIn_a_bits_param),\n .auto_out_a_bits_size (tlMasterClockXingIn_a_bits_size),\n .auto_out_a_bits_source (tlMasterClockXingIn_a_bits_source),\n .auto_out_a_bits_address (tlMasterClockXingIn_a_bits_address),\n .auto_out_a_bits_mask (tlMasterClockXingIn_a_bits_mask),\n .auto_out_a_bits_data (tlMasterClockXingIn_a_bits_data),\n .auto_out_a_bits_corrupt (tlMasterClockXingIn_a_bits_corrupt),\n .auto_out_b_ready (tlMasterClockXingIn_b_ready),\n .auto_out_b_valid (tlMasterClockXingIn_b_valid),\t// @[MixedNode.scala:551:17]\n .auto_out_b_bits_opcode (tlMasterClockXingIn_b_bits_opcode),\t// @[MixedNode.scala:551:17]\n .auto_out_b_bits_param (tlMasterClockXingIn_b_bits_param),\t// @[MixedNode.scala:551:17]\n .auto_out_b_bits_size (tlMasterClockXingIn_b_bits_size),\t// @[MixedNode.scala:551:17]\n .auto_out_b_bits_source (tlMasterClockXingIn_b_bits_source),\t// @[MixedNode.scala:551:17]\n .auto_out_b_bits_address (tlMasterClockXingIn_b_bits_address),\t// @[MixedNode.scala:551:17]\n .auto_out_b_bits_mask (tlMasterClockXingIn_b_bits_mask),\t// @[MixedNode.scala:551:17]\n .auto_out_b_bits_data (tlMasterClockXingIn_b_bits_data),\t// @[MixedNode.scala:551:17]\n .auto_out_b_bits_corrupt (tlMasterClockXingIn_b_bits_corrupt),\t// @[MixedNode.scala:551:17]\n .auto_out_c_ready (tlMasterClockXingIn_c_ready),\t// @[MixedNode.scala:551:17]\n .auto_out_c_valid (tlMasterClockXingIn_c_valid),\n .auto_out_c_bits_opcode (tlMasterClockXingIn_c_bits_opcode),\n .auto_out_c_bits_param (tlMasterClockXingIn_c_bits_param),\n .auto_out_c_bits_size (tlMasterClockXingIn_c_bits_size),\n .auto_out_c_bits_source (tlMasterClockXingIn_c_bits_source),\n .auto_out_c_bits_address (tlMasterClockXingIn_c_bits_address),\n .auto_out_c_bits_data (tlMasterClockXingIn_c_bits_data),\n .auto_out_c_bits_corrupt (tlMasterClockXingIn_c_bits_corrupt),\n .auto_out_d_ready (tlMasterClockXingIn_d_ready),\n .auto_out_d_valid (tlMasterClockXingIn_d_valid),\t// @[MixedNode.scala:551:17]\n .auto_out_d_bits_opcode (tlMasterClockXingIn_d_bits_opcode),\t// @[MixedNode.scala:551:17]\n .auto_out_d_bits_param (tlMasterClockXingIn_d_bits_param),\t// @[MixedNode.scala:551:17]\n .auto_out_d_bits_size (tlMasterClockXingIn_d_bits_size),\t// @[MixedNode.scala:551:17]\n .auto_out_d_bits_source (tlMasterClockXingIn_d_bits_source),\t// @[MixedNode.scala:551:17]\n .auto_out_d_bits_sink (tlMasterClockXingIn_d_bits_sink),\t// @[MixedNode.scala:551:17]\n .auto_out_d_bits_denied (tlMasterClockXingIn_d_bits_denied),\t// @[MixedNode.scala:551:17]\n .auto_out_d_bits_data (tlMasterClockXingIn_d_bits_data),\t// @[MixedNode.scala:551:17]\n .auto_out_d_bits_corrupt (tlMasterClockXingIn_d_bits_corrupt),\t// @[MixedNode.scala:551:17]\n .auto_out_e_ready (tlMasterClockXingIn_e_ready),\t// @[MixedNode.scala:551:17]\n .auto_out_e_valid (tlMasterClockXingIn_e_valid),\n .auto_out_e_bits_sink (tlMasterClockXingIn_e_bits_sink)\n );\t// @[Buffer.scala:75:28]\n TLBuffer_5 buffer_1 (\t// @[Buffer.scala:75:28]\n .clock (childClock),\t// @[LazyModuleImp.scala:155:31]\n .reset (childReset)\t// @[LazyModuleImp.scala:158:31]\n );\t// @[Buffer.scala:75:28]\n IntSyncAsyncCrossingSink_n1x1_1 intsink (\t// @[Crossing.scala:86:29]\n .clock (childClock),\t// @[LazyModuleImp.scala:155:31]\n .reset (childReset),\t// @[LazyModuleImp.scala:158:31]\n .auto_in_sync_0 (auto_intsink_in_sync_0_0),\t// @[ClockDomain.scala:14:9]\n .auto_out_0 (element_reset_domain_auto_rockettile_int_local_in_0_0)\n );\t// @[Crossing.scala:86:29]\n IntSyncSyncCrossingSink_n1x2_1 intsink_1 (\t// @[Crossing.scala:109:29]\n .auto_in_sync_0 (intInClockXingOut_sync_0),\t// @[MixedNode.scala:542:17]\n .auto_in_sync_1 (intInClockXingOut_sync_1),\t// @[MixedNode.scala:542:17]\n .auto_out_0 (element_reset_domain_auto_rockettile_int_local_in_1_0),\n .auto_out_1 (element_reset_domain_auto_rockettile_int_local_in_1_1)\n );\t// @[Crossing.scala:109:29]\n IntSyncSyncCrossingSink_n1x1_5 intsink_2 (\t// @[Crossing.scala:109:29]\n .auto_in_sync_0 (intInClockXingOut_1_sync_0),\t// @[MixedNode.scala:542:17]\n .auto_out_0 (element_reset_domain_auto_rockettile_int_local_in_2_0)\n );\t// @[Crossing.scala:109:29]\n IntSyncSyncCrossingSink_n1x1_6 intsink_3 (\t// @[Crossing.scala:109:29]\n .auto_in_sync_0 (intInClockXingOut_2_sync_0),\t// @[MixedNode.scala:542:17]\n .auto_out_0 (element_reset_domain_auto_rockettile_int_local_in_3_0)\n );\t// @[Crossing.scala:109:29]\n IntSyncSyncCrossingSink_n1x1_7 intsink_4 ();\t// @[Crossing.scala:109:29]\n IntSyncCrossingSource_n1x1_3 intsource (\t// @[Crossing.scala:29:31]\n .clock (childClock),\t// @[LazyModuleImp.scala:155:31]\n .reset (childReset)\t// @[LazyModuleImp.scala:158:31]\n );\t// @[Crossing.scala:29:31]\n IntSyncSyncCrossingSink_n1x1_8 intsink_5 (\t// @[Crossing.scala:109:29]\n .auto_in_sync_0 (intOutClockXingOut_2_sync_0),\t// @[MixedNode.scala:542:17]\n .auto_out_0 (auto_intsink_out_1_0_0)\n );\t// @[Crossing.scala:109:29]\n IntSyncCrossingSource_n1x1_4 intsource_1 (\t// @[Crossing.scala:29:31]\n .clock (childClock),\t// @[LazyModuleImp.scala:155:31]\n .reset (childReset),\t// @[LazyModuleImp.scala:158:31]\n .auto_in_0 (element_reset_domain_auto_rockettile_wfi_out_0),\t// @[ClockDomain.scala:14:9]\n .auto_out_sync_0 (intOutClockXingIn_3_sync_0)\n );\t// @[Crossing.scala:29:31]\n IntSyncSyncCrossingSink_n1x1_9 intsink_6 ();\t// @[Crossing.scala:109:29]\n IntSyncCrossingSource_n1x1_5 intsource_2 (\t// @[Crossing.scala:29:31]\n .clock (childClock),\t// @[LazyModuleImp.scala:155:31]\n .reset (childReset)\t// @[LazyModuleImp.scala:158:31]\n );\t// @[Crossing.scala:29:31]\n assign auto_intsink_out_1_0 = auto_intsink_out_1_0_0;\t// @[ClockDomain.scala:14:9]\n assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid = auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid_0;\t// @[ClockDomain.scala:14:9]\n assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr = auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr_0;\t// @[ClockDomain.scala:14:9]\n assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn = auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn_0;\t// @[ClockDomain.scala:14:9]\n assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv = auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv_0;\t// @[ClockDomain.scala:14:9]\n assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception = auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception_0;\t// @[ClockDomain.scala:14:9]\n assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt = auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt_0;\t// @[ClockDomain.scala:14:9]\n assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause = auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause_0;\t// @[ClockDomain.scala:14:9]\n assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval = auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval_0;\t// @[ClockDomain.scala:14:9]\n assign auto_element_reset_domain_rockettile_trace_source_out_time = auto_element_reset_domain_rockettile_trace_source_out_time_0;\t// @[ClockDomain.scala:14:9]\n assign auto_tl_master_clock_xing_out_a_valid = auto_tl_master_clock_xing_out_a_valid_0;\t// @[ClockDomain.scala:14:9]\n assign auto_tl_master_clock_xing_out_a_bits_opcode = auto_tl_master_clock_xing_out_a_bits_opcode_0;\t// @[ClockDomain.scala:14:9]\n assign auto_tl_master_clock_xing_out_a_bits_param = auto_tl_master_clock_xing_out_a_bits_param_0;\t// @[ClockDomain.scala:14:9]\n assign auto_tl_master_clock_xing_out_a_bits_size = auto_tl_master_clock_xing_out_a_bits_size_0;\t// @[ClockDomain.scala:14:9]\n assign auto_tl_master_clock_xing_out_a_bits_source = auto_tl_master_clock_xing_out_a_bits_source_0;\t// @[ClockDomain.scala:14:9]\n assign auto_tl_master_clock_xing_out_a_bits_address = auto_tl_master_clock_xing_out_a_bits_address_0;\t// @[ClockDomain.scala:14:9]\n assign auto_tl_master_clock_xing_out_a_bits_mask = auto_tl_master_clock_xing_out_a_bits_mask_0;\t// @[ClockDomain.scala:14:9]\n assign auto_tl_master_clock_xing_out_a_bits_data = auto_tl_master_clock_xing_out_a_bits_data_0;\t// @[ClockDomain.scala:14:9]\n assign auto_tl_master_clock_xing_out_a_bits_corrupt = auto_tl_master_clock_xing_out_a_bits_corrupt_0;\t// @[ClockDomain.scala:14:9]\n assign auto_tl_master_clock_xing_out_b_ready = auto_tl_master_clock_xing_out_b_ready_0;\t// @[ClockDomain.scala:14:9]\n assign auto_tl_master_clock_xing_out_c_valid = auto_tl_master_clock_xing_out_c_valid_0;\t// @[ClockDomain.scala:14:9]\n assign auto_tl_master_clock_xing_out_c_bits_opcode = auto_tl_master_clock_xing_out_c_bits_opcode_0;\t// @[ClockDomain.scala:14:9]\n assign auto_tl_master_clock_xing_out_c_bits_param = auto_tl_master_clock_xing_out_c_bits_param_0;\t// @[ClockDomain.scala:14:9]\n assign auto_tl_master_clock_xing_out_c_bits_size = auto_tl_master_clock_xing_out_c_bits_size_0;\t// @[ClockDomain.scala:14:9]\n assign auto_tl_master_clock_xing_out_c_bits_source = auto_tl_master_clock_xing_out_c_bits_source_0;\t// @[ClockDomain.scala:14:9]\n assign auto_tl_master_clock_xing_out_c_bits_address = auto_tl_master_clock_xing_out_c_bits_address_0;\t// @[ClockDomain.scala:14:9]\n assign auto_tl_master_clock_xing_out_c_bits_data = auto_tl_master_clock_xing_out_c_bits_data_0;\t// @[ClockDomain.scala:14:9]\n assign auto_tl_master_clock_xing_out_c_bits_corrupt = auto_tl_master_clock_xing_out_c_bits_corrupt_0;\t// @[ClockDomain.scala:14:9]\n assign auto_tl_master_clock_xing_out_d_ready = auto_tl_master_clock_xing_out_d_ready_0;\t// @[ClockDomain.scala:14:9]\n assign auto_tl_master_clock_xing_out_e_valid = auto_tl_master_clock_xing_out_e_valid_0;\t// @[ClockDomain.scala:14:9]\n assign auto_tl_master_clock_xing_out_e_bits_sink = auto_tl_master_clock_xing_out_e_bits_sink_0;\t// @[ClockDomain.scala:14:9]\nendmodule"}}},{"rowIdx":34385,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module IntSyncCrossingSource_n1x1_1 : \n input clock : Clock \n input reset : Reset \n output auto : { flip in : UInt<1>[1], out : { sync : UInt<1>[1]}} \n\n\n wire nodeIn : UInt<1>[1] \n invalidate nodeIn[0] \n wire nodeOut : { sync : UInt<1>[1]} \n invalidate nodeOut.sync[0] \n connect auto.out, nodeOut \n connect nodeIn, auto.in \n inst reg of AsyncResetRegVec_w1_i0_1 \n connect reg.clock, clock\n\n connect reg.reset, reset\n\n connect reg.io.d, nodeIn[0] \n connect reg.io.en, UInt<1>(0h1) \n node _T = bits(reg.io.q, 0, 0) \n connect nodeOut.sync[0], _T"},"response":{"kind":"string","value":"module IntSyncCrossingSource_n1x1_1(\t// @[Crossing.scala:41:9]\n input clock,\t// @[Crossing.scala:41:9]\n input reset\t// @[Crossing.scala:41:9]\n);\n\n wire auto_in_0 = 1'h0;\t// @[Crossing.scala:41:9]\n wire auto_out_sync_0 = 1'h0;\t// @[Crossing.scala:41:9]\n wire nodeIn_0 = 1'h0;\t// @[MixedNode.scala:551:17]\n wire nodeOut_sync_0 = 1'h0;\t// @[MixedNode.scala:542:17]\n AsyncResetRegVec_w1_i0_1 reg_0 (\t// @[AsyncResetReg.scala:86:21]\n .clock (clock),\n .reset (reset)\n );\t// @[AsyncResetReg.scala:86:21]\nendmodule"}}},{"rowIdx":34386,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module SwitchArbiter : \n input clock : Clock \n input reset : Reset \n output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}, tail : UInt<1>}}[3], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}, tail : UInt<1>}}[1], chosen_oh : UInt<3>[1]} \n\n\n regreset lock_0 : UInt<3>, clock, reset, UInt<3>(0h0) \n node unassigned_hi = cat(io.in[2].valid, io.in[1].valid) \n node _unassigned_T = cat(unassigned_hi, io.in[0].valid) \n node _unassigned_T_1 = not(lock_0) \n node unassigned = and(_unassigned_T, _unassigned_T_1) \n regreset mask : UInt<3>, clock, reset, UInt<3>(0h0) \n wire choices : UInt<3>[1] \n node _sel_T = not(mask) \n node _sel_T_1 = and(unassigned, _sel_T) \n node _sel_T_2 = cat(unassigned, _sel_T_1) \n node _sel_T_3 = bits(_sel_T_2, 0, 0) \n node _sel_T_4 = bits(_sel_T_2, 1, 1) \n node _sel_T_5 = bits(_sel_T_2, 2, 2) \n node _sel_T_6 = bits(_sel_T_2, 3, 3) \n node _sel_T_7 = bits(_sel_T_2, 4, 4) \n node _sel_T_8 = bits(_sel_T_2, 5, 5) \n node _sel_T_9 = mux(_sel_T_8, UInt<6>(0h20), UInt<6>(0h0)) \n node _sel_T_10 = mux(_sel_T_7, UInt<6>(0h10), _sel_T_9) \n node _sel_T_11 = mux(_sel_T_6, UInt<6>(0h8), _sel_T_10) \n node _sel_T_12 = mux(_sel_T_5, UInt<6>(0h4), _sel_T_11) \n node _sel_T_13 = mux(_sel_T_4, UInt<6>(0h2), _sel_T_12) \n node sel = mux(_sel_T_3, UInt<6>(0h1), _sel_T_13) \n node _choices_0_T = shr(sel, 3) \n node _choices_0_T_1 = or(sel, _choices_0_T) \n connect choices[0], _choices_0_T_1 \n node _T = not(choices[0]) \n node _T_1 = and(unassigned, _T) \n node _T_2 = bits(_T_1, 0, 0) \n node _T_3 = bits(_T_1, 1, 1) \n node _T_4 = bits(_T_1, 2, 2) \n node _T_5 = mux(_T_4, UInt<3>(0h4), UInt<3>(0h0)) \n node _T_6 = mux(_T_3, UInt<3>(0h2), _T_5) \n node _T_7 = mux(_T_2, UInt<3>(0h1), _T_6) \n connect io.in[0].ready, UInt<1>(0h0) \n connect io.in[1].ready, UInt<1>(0h0) \n connect io.in[2].ready, UInt<1>(0h0) \n node in_tails_hi = cat(io.in[2].bits.tail, io.in[1].bits.tail) \n node in_tails = cat(in_tails_hi, io.in[0].bits.tail) \n node _in_valids_T = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _in_valids_T_1 = and(io.in[0].valid, _in_valids_T) \n node _in_valids_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _in_valids_T_3 = and(io.in[1].valid, _in_valids_T_2) \n node _in_valids_T_4 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _in_valids_T_5 = and(io.in[2].valid, _in_valids_T_4) \n node in_valids_hi = cat(_in_valids_T_5, _in_valids_T_3) \n node in_valids = cat(in_valids_hi, _in_valids_T_1) \n node _chosen_T = and(in_valids, lock_0) \n node _chosen_T_1 = not(UInt<3>(0h0)) \n node _chosen_T_2 = and(_chosen_T, _chosen_T_1) \n node _chosen_T_3 = orr(_chosen_T_2) \n node chosen = mux(_chosen_T_3, lock_0, choices[0]) \n connect io.chosen_oh[0], chosen \n node _io_out_0_valid_T = and(in_valids, chosen) \n node _io_out_0_valid_T_1 = orr(_io_out_0_valid_T) \n connect io.out[0].valid, _io_out_0_valid_T_1 \n node _io_out_0_bits_T = bits(chosen, 0, 0) \n node _io_out_0_bits_T_1 = bits(chosen, 1, 1) \n node _io_out_0_bits_T_2 = bits(chosen, 2, 2) \n wire _io_out_0_bits_WIRE : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}, tail : UInt<1>} \n node _io_out_0_bits_T_3 = mux(_io_out_0_bits_T, io.in[0].bits.tail, UInt<1>(0h0)) \n node _io_out_0_bits_T_4 = mux(_io_out_0_bits_T_1, io.in[1].bits.tail, UInt<1>(0h0)) \n node _io_out_0_bits_T_5 = mux(_io_out_0_bits_T_2, io.in[2].bits.tail, UInt<1>(0h0)) \n node _io_out_0_bits_T_6 = or(_io_out_0_bits_T_3, _io_out_0_bits_T_4) \n node _io_out_0_bits_T_7 = or(_io_out_0_bits_T_6, _io_out_0_bits_T_5) \n wire _io_out_0_bits_WIRE_1 : UInt<1> \n connect _io_out_0_bits_WIRE_1, _io_out_0_bits_T_7 \n connect _io_out_0_bits_WIRE.tail, _io_out_0_bits_WIRE_1 \n wire _io_out_0_bits_WIRE_2 : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]} \n wire _io_out_0_bits_WIRE_3 : UInt<1>[3] \n node _io_out_0_bits_T_8 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[0], UInt<1>(0h0)) \n node _io_out_0_bits_T_9 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[0], UInt<1>(0h0)) \n node _io_out_0_bits_T_10 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[0], UInt<1>(0h0)) \n node _io_out_0_bits_T_11 = or(_io_out_0_bits_T_8, _io_out_0_bits_T_9) \n node _io_out_0_bits_T_12 = or(_io_out_0_bits_T_11, _io_out_0_bits_T_10) \n wire _io_out_0_bits_WIRE_4 : UInt<1> \n connect _io_out_0_bits_WIRE_4, _io_out_0_bits_T_12 \n connect _io_out_0_bits_WIRE_3[0], _io_out_0_bits_WIRE_4 \n node _io_out_0_bits_T_13 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[1], UInt<1>(0h0)) \n node _io_out_0_bits_T_14 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[1], UInt<1>(0h0)) \n node _io_out_0_bits_T_15 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[1], UInt<1>(0h0)) \n node _io_out_0_bits_T_16 = or(_io_out_0_bits_T_13, _io_out_0_bits_T_14) \n node _io_out_0_bits_T_17 = or(_io_out_0_bits_T_16, _io_out_0_bits_T_15) \n wire _io_out_0_bits_WIRE_5 : UInt<1> \n connect _io_out_0_bits_WIRE_5, _io_out_0_bits_T_17 \n connect _io_out_0_bits_WIRE_3[1], _io_out_0_bits_WIRE_5 \n node _io_out_0_bits_T_18 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[2], UInt<1>(0h0)) \n node _io_out_0_bits_T_19 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[2], UInt<1>(0h0)) \n node _io_out_0_bits_T_20 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[2], UInt<1>(0h0)) \n node _io_out_0_bits_T_21 = or(_io_out_0_bits_T_18, _io_out_0_bits_T_19) \n node _io_out_0_bits_T_22 = or(_io_out_0_bits_T_21, _io_out_0_bits_T_20) \n wire _io_out_0_bits_WIRE_6 : UInt<1> \n connect _io_out_0_bits_WIRE_6, _io_out_0_bits_T_22 \n connect _io_out_0_bits_WIRE_3[2], _io_out_0_bits_WIRE_6 \n connect _io_out_0_bits_WIRE_2.`0`, _io_out_0_bits_WIRE_3 \n wire _io_out_0_bits_WIRE_7 : UInt<1>[3] \n node _io_out_0_bits_T_23 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[0], UInt<1>(0h0)) \n node _io_out_0_bits_T_24 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[0], UInt<1>(0h0)) \n node _io_out_0_bits_T_25 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`1`[0], UInt<1>(0h0)) \n node _io_out_0_bits_T_26 = or(_io_out_0_bits_T_23, _io_out_0_bits_T_24) \n node _io_out_0_bits_T_27 = or(_io_out_0_bits_T_26, _io_out_0_bits_T_25) \n wire _io_out_0_bits_WIRE_8 : UInt<1> \n connect _io_out_0_bits_WIRE_8, _io_out_0_bits_T_27 \n connect _io_out_0_bits_WIRE_7[0], _io_out_0_bits_WIRE_8 \n node _io_out_0_bits_T_28 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[1], UInt<1>(0h0)) \n node _io_out_0_bits_T_29 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[1], UInt<1>(0h0)) \n node _io_out_0_bits_T_30 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`1`[1], UInt<1>(0h0)) \n node _io_out_0_bits_T_31 = or(_io_out_0_bits_T_28, _io_out_0_bits_T_29) \n node _io_out_0_bits_T_32 = or(_io_out_0_bits_T_31, _io_out_0_bits_T_30) \n wire _io_out_0_bits_WIRE_9 : UInt<1> \n connect _io_out_0_bits_WIRE_9, _io_out_0_bits_T_32 \n connect _io_out_0_bits_WIRE_7[1], _io_out_0_bits_WIRE_9 \n node _io_out_0_bits_T_33 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[2], UInt<1>(0h0)) \n node _io_out_0_bits_T_34 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[2], UInt<1>(0h0)) \n node _io_out_0_bits_T_35 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`1`[2], UInt<1>(0h0)) \n node _io_out_0_bits_T_36 = or(_io_out_0_bits_T_33, _io_out_0_bits_T_34) \n node _io_out_0_bits_T_37 = or(_io_out_0_bits_T_36, _io_out_0_bits_T_35) \n wire _io_out_0_bits_WIRE_10 : UInt<1> \n connect _io_out_0_bits_WIRE_10, _io_out_0_bits_T_37 \n connect _io_out_0_bits_WIRE_7[2], _io_out_0_bits_WIRE_10 \n connect _io_out_0_bits_WIRE_2.`1`, _io_out_0_bits_WIRE_7 \n wire _io_out_0_bits_WIRE_11 : UInt<1>[1] \n node _io_out_0_bits_T_38 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`2`[0], UInt<1>(0h0)) \n node _io_out_0_bits_T_39 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`2`[0], UInt<1>(0h0)) \n node _io_out_0_bits_T_40 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`2`[0], UInt<1>(0h0)) \n node _io_out_0_bits_T_41 = or(_io_out_0_bits_T_38, _io_out_0_bits_T_39) \n node _io_out_0_bits_T_42 = or(_io_out_0_bits_T_41, _io_out_0_bits_T_40) \n wire _io_out_0_bits_WIRE_12 : UInt<1> \n connect _io_out_0_bits_WIRE_12, _io_out_0_bits_T_42 \n connect _io_out_0_bits_WIRE_11[0], _io_out_0_bits_WIRE_12 \n connect _io_out_0_bits_WIRE_2.`2`, _io_out_0_bits_WIRE_11 \n wire _io_out_0_bits_WIRE_13 : UInt<1>[1] \n node _io_out_0_bits_T_43 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`3`[0], UInt<1>(0h0)) \n node _io_out_0_bits_T_44 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`3`[0], UInt<1>(0h0)) \n node _io_out_0_bits_T_45 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`3`[0], UInt<1>(0h0)) \n node _io_out_0_bits_T_46 = or(_io_out_0_bits_T_43, _io_out_0_bits_T_44) \n node _io_out_0_bits_T_47 = or(_io_out_0_bits_T_46, _io_out_0_bits_T_45) \n wire _io_out_0_bits_WIRE_14 : UInt<1> \n connect _io_out_0_bits_WIRE_14, _io_out_0_bits_T_47 \n connect _io_out_0_bits_WIRE_13[0], _io_out_0_bits_WIRE_14 \n connect _io_out_0_bits_WIRE_2.`3`, _io_out_0_bits_WIRE_13 \n wire _io_out_0_bits_WIRE_15 : UInt<1>[1] \n node _io_out_0_bits_T_48 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`4`[0], UInt<1>(0h0)) \n node _io_out_0_bits_T_49 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`4`[0], UInt<1>(0h0)) \n node _io_out_0_bits_T_50 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`4`[0], UInt<1>(0h0)) \n node _io_out_0_bits_T_51 = or(_io_out_0_bits_T_48, _io_out_0_bits_T_49) \n node _io_out_0_bits_T_52 = or(_io_out_0_bits_T_51, _io_out_0_bits_T_50) \n wire _io_out_0_bits_WIRE_16 : UInt<1> \n connect _io_out_0_bits_WIRE_16, _io_out_0_bits_T_52 \n connect _io_out_0_bits_WIRE_15[0], _io_out_0_bits_WIRE_16 \n connect _io_out_0_bits_WIRE_2.`4`, _io_out_0_bits_WIRE_15 \n wire _io_out_0_bits_WIRE_17 : UInt<1>[1] \n node _io_out_0_bits_T_53 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`5`[0], UInt<1>(0h0)) \n node _io_out_0_bits_T_54 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`5`[0], UInt<1>(0h0)) \n node _io_out_0_bits_T_55 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`5`[0], UInt<1>(0h0)) \n node _io_out_0_bits_T_56 = or(_io_out_0_bits_T_53, _io_out_0_bits_T_54) \n node _io_out_0_bits_T_57 = or(_io_out_0_bits_T_56, _io_out_0_bits_T_55) \n wire _io_out_0_bits_WIRE_18 : UInt<1> \n connect _io_out_0_bits_WIRE_18, _io_out_0_bits_T_57 \n connect _io_out_0_bits_WIRE_17[0], _io_out_0_bits_WIRE_18 \n connect _io_out_0_bits_WIRE_2.`5`, _io_out_0_bits_WIRE_17 \n connect _io_out_0_bits_WIRE.vc_sel, _io_out_0_bits_WIRE_2 \n connect io.out[0].bits, _io_out_0_bits_WIRE \n node _T_8 = bits(chosen, 0, 0) \n node _T_9 = and(_T_8, io.out[0].ready) \n when _T_9 : \n connect io.in[0].ready, UInt<1>(0h1) \n node _T_10 = bits(chosen, 1, 1) \n node _T_11 = and(_T_10, io.out[0].ready) \n when _T_11 : \n connect io.in[1].ready, UInt<1>(0h1) \n node _T_12 = bits(chosen, 2, 2) \n node _T_13 = and(_T_12, io.out[0].ready) \n when _T_13 : \n connect io.in[2].ready, UInt<1>(0h1) \n node _T_14 = or(UInt<3>(0h0), chosen) \n node _T_15 = and(io.out[0].ready, io.out[0].valid) \n when _T_15 : \n node _lock_0_T = not(in_tails) \n node _lock_0_T_1 = and(chosen, _lock_0_T) \n connect lock_0, _lock_0_T_1 \n node _T_16 = and(io.out[0].ready, io.out[0].valid) \n when _T_16 : \n node _mask_T = shr(io.chosen_oh[0], 0) \n node _mask_T_1 = shr(io.chosen_oh[0], 1) \n node _mask_T_2 = shr(io.chosen_oh[0], 2) \n node _mask_T_3 = or(_mask_T, _mask_T_1) \n node _mask_T_4 = or(_mask_T_3, _mask_T_2) \n connect mask, _mask_T_4 \n else :\n\n node _mask_T_5 = not(mask) \n node _mask_T_6 = eq(_mask_T_5, UInt<1>(0h0)) \n node _mask_T_7 = shl(mask, 1) \n node _mask_T_8 = or(_mask_T_7, UInt<1>(0h1)) \n node _mask_T_9 = mux(_mask_T_6, UInt<1>(0h0), _mask_T_8) \n connect mask, _mask_T_9"},"response":{"kind":"string","value":"module SwitchArbiter(\t// @[SwitchAllocator.scala:17:7]\n input clock,\t// @[SwitchAllocator.scala:17:7]\n input reset,\t// @[SwitchAllocator.scala:17:7]\n output io_in_0_ready,\t// @[SwitchAllocator.scala:18:14]\n input io_in_0_valid,\t// @[SwitchAllocator.scala:18:14]\n input io_in_0_bits_vc_sel_5_0,\t// @[SwitchAllocator.scala:18:14]\n input io_in_0_bits_vc_sel_4_0,\t// @[SwitchAllocator.scala:18:14]\n input io_in_0_bits_vc_sel_3_0,\t// @[SwitchAllocator.scala:18:14]\n input io_in_0_bits_vc_sel_2_0,\t// @[SwitchAllocator.scala:18:14]\n input io_in_0_bits_tail,\t// @[SwitchAllocator.scala:18:14]\n output io_in_2_ready,\t// @[SwitchAllocator.scala:18:14]\n input io_in_2_valid,\t// @[SwitchAllocator.scala:18:14]\n input io_in_2_bits_vc_sel_5_0,\t// @[SwitchAllocator.scala:18:14]\n input io_in_2_bits_vc_sel_4_0,\t// @[SwitchAllocator.scala:18:14]\n input io_in_2_bits_vc_sel_3_0,\t// @[SwitchAllocator.scala:18:14]\n input io_in_2_bits_vc_sel_2_0,\t// @[SwitchAllocator.scala:18:14]\n input io_in_2_bits_tail,\t// @[SwitchAllocator.scala:18:14]\n input io_out_0_ready,\t// @[SwitchAllocator.scala:18:14]\n output io_out_0_valid,\t// @[SwitchAllocator.scala:18:14]\n output io_out_0_bits_vc_sel_5_0,\t// @[SwitchAllocator.scala:18:14]\n output io_out_0_bits_vc_sel_4_0,\t// @[SwitchAllocator.scala:18:14]\n output io_out_0_bits_vc_sel_3_0,\t// @[SwitchAllocator.scala:18:14]\n output io_out_0_bits_vc_sel_2_0,\t// @[SwitchAllocator.scala:18:14]\n output io_out_0_bits_tail,\t// @[SwitchAllocator.scala:18:14]\n output [2:0] io_chosen_oh_0\t// @[SwitchAllocator.scala:18:14]\n);\n\n reg [2:0] lock_0;\t// @[SwitchAllocator.scala:24:38]\n wire [2:0] unassigned = {io_in_2_valid, 1'h0, io_in_0_valid} & ~lock_0;\t// @[SwitchAllocator.scala:17:7, :24:38, :25:{23,52,54}]\n reg [2:0] mask;\t// @[SwitchAllocator.scala:27:21]\n wire [2:0] _sel_T_1 = unassigned & ~mask;\t// @[SwitchAllocator.scala:25:52, :27:21, :30:{58,60}]\n wire [5:0] sel = _sel_T_1[0] ? 6'h1 : _sel_T_1[1] ? 6'h2 : _sel_T_1[2] ? 6'h4 : unassigned[0] ? 6'h8 : unassigned[1] ? 6'h10 : {unassigned[2], 5'h0};\t// @[OneHot.scala:85:71]\n wire [2:0] in_valids = {io_in_2_valid, 1'h0, io_in_0_valid};\t// @[SwitchAllocator.scala:17:7, :41:24]\n wire [2:0] _chosen_T_2 = in_valids & lock_0;\t// @[SwitchAllocator.scala:24:38, :41:24, :42:33]\n wire [2:0] chosen = (|{_chosen_T_2[2], _chosen_T_2[0]}) ? lock_0 : sel[2:0] | sel[5:3];\t// @[Mux.scala:50:70]\n wire [2:0] _io_out_0_valid_T = in_valids & chosen;\t// @[SwitchAllocator.scala:41:24, :42:21, :44:35]\n wire [1:0] _GEN = {_io_out_0_valid_T[2], _io_out_0_valid_T[0]};\t// @[SwitchAllocator.scala:44:35]\n wire _GEN_0 = io_out_0_ready & (|_GEN);\t// @[Decoupled.scala:51:35]\n wire [1:0] _GEN_1 = chosen[1:0] | chosen[2:1];\t// @[SwitchAllocator.scala:42:21, :58:{55,71}]\n always @(posedge clock) begin\t// @[SwitchAllocator.scala:17:7]\n if (reset) begin\t// @[SwitchAllocator.scala:17:7]\n lock_0 <= 3'h0;\t// @[SwitchAllocator.scala:24:38]\n mask <= 3'h0;\t// @[SwitchAllocator.scala:27:21]\n end\n else begin\t// @[SwitchAllocator.scala:17:7]\n if (_GEN_0)\t// @[Decoupled.scala:51:35]\n lock_0 <= chosen & {~io_in_2_bits_tail, 1'h1, ~io_in_0_bits_tail};\t// @[SwitchAllocator.scala:17:7, :24:38, :39:21, :42:21, :53:{25,27}]\n mask <= _GEN_0 ? {chosen[2], _GEN_1[1], _GEN_1[0] | chosen[2]} : (&mask) ? 3'h0 : {mask[1:0], 1'h1};\t// @[Decoupled.scala:51:35]\n end\n always @(posedge)"}}},{"rowIdx":34387,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module AXI4RAM : \n input clock : Clock \n input reset : Reset \n output auto : { flip in : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<29>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { real_last : UInt<1>}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { real_last : UInt<1>}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<29>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { real_last : UInt<1>}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { real_last : UInt<1>}, last : UInt<1>}}}} \n\n\n wire nodeIn : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<29>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { real_last : UInt<1>}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { real_last : UInt<1>}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<29>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { real_last : UInt<1>}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { real_last : UInt<1>}, last : UInt<1>}}} \n invalidate nodeIn.r.bits.last \n invalidate nodeIn.r.bits.echo.real_last \n invalidate nodeIn.r.bits.resp \n invalidate nodeIn.r.bits.data \n invalidate nodeIn.r.bits.id \n invalidate nodeIn.r.valid \n invalidate nodeIn.r.ready \n invalidate nodeIn.ar.bits.echo.real_last \n invalidate nodeIn.ar.bits.qos \n invalidate nodeIn.ar.bits.prot \n invalidate nodeIn.ar.bits.cache \n invalidate nodeIn.ar.bits.lock \n invalidate nodeIn.ar.bits.burst \n invalidate nodeIn.ar.bits.size \n invalidate nodeIn.ar.bits.len \n invalidate nodeIn.ar.bits.addr \n invalidate nodeIn.ar.bits.id \n invalidate nodeIn.ar.valid \n invalidate nodeIn.ar.ready \n invalidate nodeIn.b.bits.echo.real_last \n invalidate nodeIn.b.bits.resp \n invalidate nodeIn.b.bits.id \n invalidate nodeIn.b.valid \n invalidate nodeIn.b.ready \n invalidate nodeIn.w.bits.last \n invalidate nodeIn.w.bits.strb \n invalidate nodeIn.w.bits.data \n invalidate nodeIn.w.valid \n invalidate nodeIn.w.ready \n invalidate nodeIn.aw.bits.echo.real_last \n invalidate nodeIn.aw.bits.qos \n invalidate nodeIn.aw.bits.prot \n invalidate nodeIn.aw.bits.cache \n invalidate nodeIn.aw.bits.lock \n invalidate nodeIn.aw.bits.burst \n invalidate nodeIn.aw.bits.size \n invalidate nodeIn.aw.bits.len \n invalidate nodeIn.aw.bits.addr \n invalidate nodeIn.aw.bits.id \n invalidate nodeIn.aw.valid \n invalidate nodeIn.aw.ready \n connect nodeIn, auto.in \n smem mem : UInt<8>[8] [67108864] \n node _r_addr_T = shr(nodeIn.ar.bits.addr, 3) \n node _r_addr_T_1 = bits(_r_addr_T, 0, 0) \n node _r_addr_T_2 = bits(_r_addr_T, 1, 1) \n node _r_addr_T_3 = bits(_r_addr_T, 2, 2) \n node _r_addr_T_4 = bits(_r_addr_T, 3, 3) \n node _r_addr_T_5 = bits(_r_addr_T, 4, 4) \n node _r_addr_T_6 = bits(_r_addr_T, 5, 5) \n node _r_addr_T_7 = bits(_r_addr_T, 6, 6) \n node _r_addr_T_8 = bits(_r_addr_T, 7, 7) \n node _r_addr_T_9 = bits(_r_addr_T, 8, 8) \n node _r_addr_T_10 = bits(_r_addr_T, 9, 9) \n node _r_addr_T_11 = bits(_r_addr_T, 10, 10) \n node _r_addr_T_12 = bits(_r_addr_T, 11, 11) \n node _r_addr_T_13 = bits(_r_addr_T, 12, 12) \n node _r_addr_T_14 = bits(_r_addr_T, 13, 13) \n node _r_addr_T_15 = bits(_r_addr_T, 14, 14) \n node _r_addr_T_16 = bits(_r_addr_T, 15, 15) \n node _r_addr_T_17 = bits(_r_addr_T, 16, 16) \n node _r_addr_T_18 = bits(_r_addr_T, 17, 17) \n node _r_addr_T_19 = bits(_r_addr_T, 18, 18) \n node _r_addr_T_20 = bits(_r_addr_T, 19, 19) \n node _r_addr_T_21 = bits(_r_addr_T, 20, 20) \n node _r_addr_T_22 = bits(_r_addr_T, 21, 21) \n node _r_addr_T_23 = bits(_r_addr_T, 22, 22) \n node _r_addr_T_24 = bits(_r_addr_T, 23, 23) \n node _r_addr_T_25 = bits(_r_addr_T, 24, 24) \n node _r_addr_T_26 = bits(_r_addr_T, 25, 25) \n node r_addr_lo_lo_lo_hi = cat(_r_addr_T_3, _r_addr_T_2) \n node r_addr_lo_lo_lo = cat(r_addr_lo_lo_lo_hi, _r_addr_T_1) \n node r_addr_lo_lo_hi_hi = cat(_r_addr_T_6, _r_addr_T_5) \n node r_addr_lo_lo_hi = cat(r_addr_lo_lo_hi_hi, _r_addr_T_4) \n node r_addr_lo_lo = cat(r_addr_lo_lo_hi, r_addr_lo_lo_lo) \n node r_addr_lo_hi_lo_hi = cat(_r_addr_T_9, _r_addr_T_8) \n node r_addr_lo_hi_lo = cat(r_addr_lo_hi_lo_hi, _r_addr_T_7) \n node r_addr_lo_hi_hi_lo = cat(_r_addr_T_11, _r_addr_T_10) \n node r_addr_lo_hi_hi_hi = cat(_r_addr_T_13, _r_addr_T_12) \n node r_addr_lo_hi_hi = cat(r_addr_lo_hi_hi_hi, r_addr_lo_hi_hi_lo) \n node r_addr_lo_hi = cat(r_addr_lo_hi_hi, r_addr_lo_hi_lo) \n node r_addr_lo = cat(r_addr_lo_hi, r_addr_lo_lo) \n node r_addr_hi_lo_lo_hi = cat(_r_addr_T_16, _r_addr_T_15) \n node r_addr_hi_lo_lo = cat(r_addr_hi_lo_lo_hi, _r_addr_T_14) \n node r_addr_hi_lo_hi_hi = cat(_r_addr_T_19, _r_addr_T_18) \n node r_addr_hi_lo_hi = cat(r_addr_hi_lo_hi_hi, _r_addr_T_17) \n node r_addr_hi_lo = cat(r_addr_hi_lo_hi, r_addr_hi_lo_lo) \n node r_addr_hi_hi_lo_hi = cat(_r_addr_T_22, _r_addr_T_21) \n node r_addr_hi_hi_lo = cat(r_addr_hi_hi_lo_hi, _r_addr_T_20) \n node r_addr_hi_hi_hi_lo = cat(_r_addr_T_24, _r_addr_T_23) \n node r_addr_hi_hi_hi_hi = cat(_r_addr_T_26, _r_addr_T_25) \n node r_addr_hi_hi_hi = cat(r_addr_hi_hi_hi_hi, r_addr_hi_hi_hi_lo) \n node r_addr_hi_hi = cat(r_addr_hi_hi_hi, r_addr_hi_hi_lo) \n node r_addr_hi = cat(r_addr_hi_hi, r_addr_hi_lo) \n node r_addr = cat(r_addr_hi, r_addr_lo) \n node _w_addr_T = shr(nodeIn.aw.bits.addr, 3) \n node _w_addr_T_1 = bits(_w_addr_T, 0, 0) \n node _w_addr_T_2 = bits(_w_addr_T, 1, 1) \n node _w_addr_T_3 = bits(_w_addr_T, 2, 2) \n node _w_addr_T_4 = bits(_w_addr_T, 3, 3) \n node _w_addr_T_5 = bits(_w_addr_T, 4, 4) \n node _w_addr_T_6 = bits(_w_addr_T, 5, 5) \n node _w_addr_T_7 = bits(_w_addr_T, 6, 6) \n node _w_addr_T_8 = bits(_w_addr_T, 7, 7) \n node _w_addr_T_9 = bits(_w_addr_T, 8, 8) \n node _w_addr_T_10 = bits(_w_addr_T, 9, 9) \n node _w_addr_T_11 = bits(_w_addr_T, 10, 10) \n node _w_addr_T_12 = bits(_w_addr_T, 11, 11) \n node _w_addr_T_13 = bits(_w_addr_T, 12, 12) \n node _w_addr_T_14 = bits(_w_addr_T, 13, 13) \n node _w_addr_T_15 = bits(_w_addr_T, 14, 14) \n node _w_addr_T_16 = bits(_w_addr_T, 15, 15) \n node _w_addr_T_17 = bits(_w_addr_T, 16, 16) \n node _w_addr_T_18 = bits(_w_addr_T, 17, 17) \n node _w_addr_T_19 = bits(_w_addr_T, 18, 18) \n node _w_addr_T_20 = bits(_w_addr_T, 19, 19) \n node _w_addr_T_21 = bits(_w_addr_T, 20, 20) \n node _w_addr_T_22 = bits(_w_addr_T, 21, 21) \n node _w_addr_T_23 = bits(_w_addr_T, 22, 22) \n node _w_addr_T_24 = bits(_w_addr_T, 23, 23) \n node _w_addr_T_25 = bits(_w_addr_T, 24, 24) \n node _w_addr_T_26 = bits(_w_addr_T, 25, 25) \n node w_addr_lo_lo_lo_hi = cat(_w_addr_T_3, _w_addr_T_2) \n node w_addr_lo_lo_lo = cat(w_addr_lo_lo_lo_hi, _w_addr_T_1) \n node w_addr_lo_lo_hi_hi = cat(_w_addr_T_6, _w_addr_T_5) \n node w_addr_lo_lo_hi = cat(w_addr_lo_lo_hi_hi, _w_addr_T_4) \n node w_addr_lo_lo = cat(w_addr_lo_lo_hi, w_addr_lo_lo_lo) \n node w_addr_lo_hi_lo_hi = cat(_w_addr_T_9, _w_addr_T_8) \n node w_addr_lo_hi_lo = cat(w_addr_lo_hi_lo_hi, _w_addr_T_7) \n node w_addr_lo_hi_hi_lo = cat(_w_addr_T_11, _w_addr_T_10) \n node w_addr_lo_hi_hi_hi = cat(_w_addr_T_13, _w_addr_T_12) \n node w_addr_lo_hi_hi = cat(w_addr_lo_hi_hi_hi, w_addr_lo_hi_hi_lo) \n node w_addr_lo_hi = cat(w_addr_lo_hi_hi, w_addr_lo_hi_lo) \n node w_addr_lo = cat(w_addr_lo_hi, w_addr_lo_lo) \n node w_addr_hi_lo_lo_hi = cat(_w_addr_T_16, _w_addr_T_15) \n node w_addr_hi_lo_lo = cat(w_addr_hi_lo_lo_hi, _w_addr_T_14) \n node w_addr_hi_lo_hi_hi = cat(_w_addr_T_19, _w_addr_T_18) \n node w_addr_hi_lo_hi = cat(w_addr_hi_lo_hi_hi, _w_addr_T_17) \n node w_addr_hi_lo = cat(w_addr_hi_lo_hi, w_addr_hi_lo_lo) \n node w_addr_hi_hi_lo_hi = cat(_w_addr_T_22, _w_addr_T_21) \n node w_addr_hi_hi_lo = cat(w_addr_hi_hi_lo_hi, _w_addr_T_20) \n node w_addr_hi_hi_hi_lo = cat(_w_addr_T_24, _w_addr_T_23) \n node w_addr_hi_hi_hi_hi = cat(_w_addr_T_26, _w_addr_T_25) \n node w_addr_hi_hi_hi = cat(w_addr_hi_hi_hi_hi, w_addr_hi_hi_hi_lo) \n node w_addr_hi_hi = cat(w_addr_hi_hi_hi, w_addr_hi_hi_lo) \n node w_addr_hi = cat(w_addr_hi_hi, w_addr_hi_lo) \n node w_addr = cat(w_addr_hi, w_addr_lo) \n node _r_sel0_T = xor(nodeIn.ar.bits.addr, UInt<1>(0h0)) \n node _r_sel0_T_1 = cvt(_r_sel0_T) \n node _r_sel0_T_2 = and(_r_sel0_T_1, asSInt(UInt<30>(0h20000000))) \n node _r_sel0_T_3 = asSInt(_r_sel0_T_2) \n node r_sel0 = eq(_r_sel0_T_3, asSInt(UInt<1>(0h0))) \n node _w_sel0_T = xor(nodeIn.aw.bits.addr, UInt<1>(0h0)) \n node _w_sel0_T_1 = cvt(_w_sel0_T) \n node _w_sel0_T_2 = and(_w_sel0_T_1, asSInt(UInt<30>(0h20000000))) \n node _w_sel0_T_3 = asSInt(_w_sel0_T_2) \n node w_sel0 = eq(_w_sel0_T_3, asSInt(UInt<1>(0h0))) \n regreset w_full : UInt<1>, clock, reset, UInt<1>(0h0) \n reg w_id : UInt, clock \n reg w_echo : { real_last : UInt<1>}, clock \n reg r_sel1 : UInt<1>, clock \n connect r_sel1, r_sel0 \n reg w_sel1 : UInt<1>, clock \n connect w_sel1, w_sel0 \n node _T = and(nodeIn.b.ready, nodeIn.b.valid) \n when _T : \n connect w_full, UInt<1>(0h0) \n node _T_1 = and(nodeIn.aw.ready, nodeIn.aw.valid) \n when _T_1 : \n connect w_full, UInt<1>(0h1) \n node _T_2 = and(nodeIn.aw.ready, nodeIn.aw.valid) \n when _T_2 : \n connect w_id, nodeIn.aw.bits.id \n connect w_sel1, w_sel0 \n connect w_echo.real_last, nodeIn.aw.bits.echo.real_last \n node _wdata_T = bits(nodeIn.w.bits.data, 7, 0) \n node _wdata_T_1 = bits(nodeIn.w.bits.data, 15, 8) \n node _wdata_T_2 = bits(nodeIn.w.bits.data, 23, 16) \n node _wdata_T_3 = bits(nodeIn.w.bits.data, 31, 24) \n node _wdata_T_4 = bits(nodeIn.w.bits.data, 39, 32) \n node _wdata_T_5 = bits(nodeIn.w.bits.data, 47, 40) \n node _wdata_T_6 = bits(nodeIn.w.bits.data, 55, 48) \n node _wdata_T_7 = bits(nodeIn.w.bits.data, 63, 56) \n wire wdata : UInt<8>[8] \n connect wdata[0], _wdata_T \n connect wdata[1], _wdata_T_1 \n connect wdata[2], _wdata_T_2 \n connect wdata[3], _wdata_T_3 \n connect wdata[4], _wdata_T_4 \n connect wdata[5], _wdata_T_5 \n connect wdata[6], _wdata_T_6 \n connect wdata[7], _wdata_T_7 \n node _T_3 = and(nodeIn.aw.ready, nodeIn.aw.valid) \n node _T_4 = and(_T_3, w_sel0) \n when _T_4 : \n node _T_5 = bits(nodeIn.w.bits.strb, 0, 0) \n node _T_6 = bits(nodeIn.w.bits.strb, 1, 1) \n node _T_7 = bits(nodeIn.w.bits.strb, 2, 2) \n node _T_8 = bits(nodeIn.w.bits.strb, 3, 3) \n node _T_9 = bits(nodeIn.w.bits.strb, 4, 4) \n node _T_10 = bits(nodeIn.w.bits.strb, 5, 5) \n node _T_11 = bits(nodeIn.w.bits.strb, 6, 6) \n node _T_12 = bits(nodeIn.w.bits.strb, 7, 7) \n write mport MPORT = mem[w_addr], clock \n when _T_5 : \n connect MPORT[0], wdata[0] \n when _T_6 : \n connect MPORT[1], wdata[1] \n when _T_7 : \n connect MPORT[2], wdata[2] \n when _T_8 : \n connect MPORT[3], wdata[3] \n when _T_9 : \n connect MPORT[4], wdata[4] \n when _T_10 : \n connect MPORT[5], wdata[5] \n when _T_11 : \n connect MPORT[6], wdata[6] \n when _T_12 : \n connect MPORT[7], wdata[7] \n connect nodeIn.b.valid, w_full \n node _nodeIn_aw_ready_T = eq(w_full, UInt<1>(0h0)) \n node _nodeIn_aw_ready_T_1 = or(nodeIn.b.ready, _nodeIn_aw_ready_T) \n node _nodeIn_aw_ready_T_2 = and(nodeIn.w.valid, _nodeIn_aw_ready_T_1) \n connect nodeIn.aw.ready, _nodeIn_aw_ready_T_2 \n node _nodeIn_w_ready_T = eq(w_full, UInt<1>(0h0)) \n node _nodeIn_w_ready_T_1 = or(nodeIn.b.ready, _nodeIn_w_ready_T) \n node _nodeIn_w_ready_T_2 = and(nodeIn.aw.valid, _nodeIn_w_ready_T_1) \n connect nodeIn.w.ready, _nodeIn_w_ready_T_2 \n connect nodeIn.b.bits.id, w_id \n node _nodeIn_b_bits_resp_T = mux(w_sel1, UInt<2>(0h0), UInt<2>(0h3)) \n connect nodeIn.b.bits.resp, _nodeIn_b_bits_resp_T \n connect nodeIn.b.bits.echo.real_last, w_echo.real_last \n regreset r_full : UInt<1>, clock, reset, UInt<1>(0h0) \n reg r_id : UInt, clock \n reg r_echo : { real_last : UInt<1>}, clock \n node _T_13 = and(nodeIn.r.ready, nodeIn.r.valid) \n when _T_13 : \n connect r_full, UInt<1>(0h0) \n node _T_14 = and(nodeIn.ar.ready, nodeIn.ar.valid) \n when _T_14 : \n connect r_full, UInt<1>(0h1) \n node _T_15 = and(nodeIn.ar.ready, nodeIn.ar.valid) \n when _T_15 : \n connect r_id, nodeIn.ar.bits.id \n connect r_sel1, r_sel0 \n connect r_echo.real_last, nodeIn.ar.bits.echo.real_last \n node ren = and(nodeIn.ar.ready, nodeIn.ar.valid) \n wire _rdata_WIRE : UInt<26> \n invalidate _rdata_WIRE \n when ren : \n connect _rdata_WIRE, r_addr \n read mport rdata_MPORT = mem[_rdata_WIRE], clock \n reg rdata_REG : UInt<1>, clock \n connect rdata_REG, ren \n reg rdata_r : UInt<8>[8], clock \n when rdata_REG : \n connect rdata_r, rdata_MPORT \n node rdata = mux(rdata_REG, rdata_MPORT, rdata_r) \n connect nodeIn.r.valid, r_full \n node _nodeIn_ar_ready_T = eq(r_full, UInt<1>(0h0)) \n node _nodeIn_ar_ready_T_1 = or(nodeIn.r.ready, _nodeIn_ar_ready_T) \n connect nodeIn.ar.ready, _nodeIn_ar_ready_T_1 \n connect nodeIn.r.bits.id, r_id \n node _nodeIn_r_bits_resp_T = mux(UInt<1>(0h0), UInt<2>(0h2), UInt<2>(0h0)) \n node _nodeIn_r_bits_resp_T_1 = mux(r_sel1, _nodeIn_r_bits_resp_T, UInt<2>(0h3)) \n connect nodeIn.r.bits.resp, _nodeIn_r_bits_resp_T_1 \n node nodeIn_r_bits_data_lo_lo = cat(rdata[1], rdata[0]) \n node nodeIn_r_bits_data_lo_hi = cat(rdata[3], rdata[2]) \n node nodeIn_r_bits_data_lo = cat(nodeIn_r_bits_data_lo_hi, nodeIn_r_bits_data_lo_lo) \n node nodeIn_r_bits_data_hi_lo = cat(rdata[5], rdata[4]) \n node nodeIn_r_bits_data_hi_hi = cat(rdata[7], rdata[6]) \n node nodeIn_r_bits_data_hi = cat(nodeIn_r_bits_data_hi_hi, nodeIn_r_bits_data_hi_lo) \n node _nodeIn_r_bits_data_T = cat(nodeIn_r_bits_data_hi, nodeIn_r_bits_data_lo) \n connect nodeIn.r.bits.data, _nodeIn_r_bits_data_T \n connect nodeIn.r.bits.echo.real_last, r_echo.real_last \n connect nodeIn.r.bits.last, UInt<1>(0h1)"},"response":{"kind":"string","value":"module AXI4RAM(\t// @[SRAM.scala:58:9]\n input clock,\t// @[SRAM.scala:58:9]\n input reset,\t// @[SRAM.scala:58:9]\n output auto_in_aw_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_in_aw_valid,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_in_aw_bits_id,\t// @[LazyModuleImp.scala:107:25]\n input [28:0] auto_in_aw_bits_addr,\t// @[LazyModuleImp.scala:107:25]\n input [7:0] auto_in_aw_bits_len,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_in_aw_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_in_aw_bits_burst,\t// @[LazyModuleImp.scala:107:25]\n input auto_in_aw_bits_lock,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_in_aw_bits_cache,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_in_aw_bits_prot,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_in_aw_bits_qos,\t// @[LazyModuleImp.scala:107:25]\n input auto_in_aw_bits_echo_real_last,\t// @[LazyModuleImp.scala:107:25]\n output auto_in_w_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_in_w_valid,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_in_w_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input [7:0] auto_in_w_bits_strb,\t// @[LazyModuleImp.scala:107:25]\n input auto_in_w_bits_last,\t// @[LazyModuleImp.scala:107:25]\n input auto_in_b_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_in_b_valid,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_in_b_bits_id,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_in_b_bits_resp,\t// @[LazyModuleImp.scala:107:25]\n output auto_in_b_bits_echo_real_last,\t// @[LazyModuleImp.scala:107:25]\n output auto_in_ar_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_in_ar_valid,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_in_ar_bits_id,\t// @[LazyModuleImp.scala:107:25]\n input [28:0] auto_in_ar_bits_addr,\t// @[LazyModuleImp.scala:107:25]\n input [7:0] auto_in_ar_bits_len,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_in_ar_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_in_ar_bits_burst,\t// @[LazyModuleImp.scala:107:25]\n input auto_in_ar_bits_lock,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_in_ar_bits_cache,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_in_ar_bits_prot,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_in_ar_bits_qos,\t// @[LazyModuleImp.scala:107:25]\n input auto_in_ar_bits_echo_real_last,\t// @[LazyModuleImp.scala:107:25]\n input auto_in_r_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_in_r_valid,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_in_r_bits_id,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_in_r_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_in_r_bits_resp,\t// @[LazyModuleImp.scala:107:25]\n output auto_in_r_bits_echo_real_last\t// @[LazyModuleImp.scala:107:25]\n);\n\n wire [63:0] _mem_R0_data;\t// @[DescribedSRAM.scala:17:26]\n wire auto_in_aw_valid_0 = auto_in_aw_valid;\t// @[SRAM.scala:58:9]\n wire [3:0] auto_in_aw_bits_id_0 = auto_in_aw_bits_id;\t// @[SRAM.scala:58:9]\n wire [28:0] auto_in_aw_bits_addr_0 = auto_in_aw_bits_addr;\t// @[SRAM.scala:58:9]\n wire [7:0] auto_in_aw_bits_len_0 = auto_in_aw_bits_len;\t// @[SRAM.scala:58:9]\n wire [2:0] auto_in_aw_bits_size_0 = auto_in_aw_bits_size;\t// @[SRAM.scala:58:9]\n wire [1:0] auto_in_aw_bits_burst_0 = auto_in_aw_bits_burst;\t// @[SRAM.scala:58:9]\n wire auto_in_aw_bits_lock_0 = auto_in_aw_bits_lock;\t// @[SRAM.scala:58:9]\n wire [3:0] auto_in_aw_bits_cache_0 = auto_in_aw_bits_cache;\t// @[SRAM.scala:58:9]\n wire [2:0] auto_in_aw_bits_prot_0 = auto_in_aw_bits_prot;\t// @[SRAM.scala:58:9]\n wire [3:0] auto_in_aw_bits_qos_0 = auto_in_aw_bits_qos;\t// @[SRAM.scala:58:9]\n wire auto_in_aw_bits_echo_real_last_0 = auto_in_aw_bits_echo_real_last;\t// @[SRAM.scala:58:9]\n wire auto_in_w_valid_0 = auto_in_w_valid;\t// @[SRAM.scala:58:9]\n wire [63:0] auto_in_w_bits_data_0 = auto_in_w_bits_data;\t// @[SRAM.scala:58:9]\n wire [7:0] auto_in_w_bits_strb_0 = auto_in_w_bits_strb;\t// @[SRAM.scala:58:9]\n wire auto_in_w_bits_last_0 = auto_in_w_bits_last;\t// @[SRAM.scala:58:9]\n wire auto_in_b_ready_0 = auto_in_b_ready;\t// @[SRAM.scala:58:9]\n wire auto_in_ar_valid_0 = auto_in_ar_valid;\t// @[SRAM.scala:58:9]\n wire [3:0] auto_in_ar_bits_id_0 = auto_in_ar_bits_id;\t// @[SRAM.scala:58:9]\n wire [28:0] auto_in_ar_bits_addr_0 = auto_in_ar_bits_addr;\t// @[SRAM.scala:58:9]\n wire [7:0] auto_in_ar_bits_len_0 = auto_in_ar_bits_len;\t// @[SRAM.scala:58:9]\n wire [2:0] auto_in_ar_bits_size_0 = auto_in_ar_bits_size;\t// @[SRAM.scala:58:9]\n wire [1:0] auto_in_ar_bits_burst_0 = auto_in_ar_bits_burst;\t// @[SRAM.scala:58:9]\n wire auto_in_ar_bits_lock_0 = auto_in_ar_bits_lock;\t// @[SRAM.scala:58:9]\n wire [3:0] auto_in_ar_bits_cache_0 = auto_in_ar_bits_cache;\t// @[SRAM.scala:58:9]\n wire [2:0] auto_in_ar_bits_prot_0 = auto_in_ar_bits_prot;\t// @[SRAM.scala:58:9]\n wire [3:0] auto_in_ar_bits_qos_0 = auto_in_ar_bits_qos;\t// @[SRAM.scala:58:9]\n wire auto_in_ar_bits_echo_real_last_0 = auto_in_ar_bits_echo_real_last;\t// @[SRAM.scala:58:9]\n wire auto_in_r_ready_0 = auto_in_r_ready;\t// @[SRAM.scala:58:9]\n wire [1:0] _nodeIn_r_bits_resp_T = 2'h0;\t// @[SRAM.scala:125:38]\n wire auto_in_r_bits_last = 1'h1;\t// @[SRAM.scala:58:9]\n wire nodeIn_aw_ready;\t// @[MixedNode.scala:551:17]\n wire nodeIn_r_bits_last = 1'h1;\t// @[MixedNode.scala:551:17]\n wire nodeIn_aw_valid = auto_in_aw_valid_0;\t// @[SRAM.scala:58:9]\n wire [3:0] nodeIn_aw_bits_id = auto_in_aw_bits_id_0;\t// @[SRAM.scala:58:9]\n wire [28:0] nodeIn_aw_bits_addr = auto_in_aw_bits_addr_0;\t// @[SRAM.scala:58:9]\n wire [7:0] nodeIn_aw_bits_len = auto_in_aw_bits_len_0;\t// @[SRAM.scala:58:9]\n wire [2:0] nodeIn_aw_bits_size = auto_in_aw_bits_size_0;\t// @[SRAM.scala:58:9]\n wire [1:0] nodeIn_aw_bits_burst = auto_in_aw_bits_burst_0;\t// @[SRAM.scala:58:9]\n wire nodeIn_aw_bits_lock = auto_in_aw_bits_lock_0;\t// @[SRAM.scala:58:9]\n wire [3:0] nodeIn_aw_bits_cache = auto_in_aw_bits_cache_0;\t// @[SRAM.scala:58:9]\n wire [2:0] nodeIn_aw_bits_prot = auto_in_aw_bits_prot_0;\t// @[SRAM.scala:58:9]\n wire [3:0] nodeIn_aw_bits_qos = auto_in_aw_bits_qos_0;\t// @[SRAM.scala:58:9]\n wire nodeIn_aw_bits_echo_real_last = auto_in_aw_bits_echo_real_last_0;\t// @[SRAM.scala:58:9]\n wire nodeIn_w_ready;\t// @[MixedNode.scala:551:17]\n wire nodeIn_w_valid = auto_in_w_valid_0;\t// @[SRAM.scala:58:9]\n wire [63:0] nodeIn_w_bits_data = auto_in_w_bits_data_0;\t// @[SRAM.scala:58:9]\n wire [7:0] nodeIn_w_bits_strb = auto_in_w_bits_strb_0;\t// @[SRAM.scala:58:9]\n wire nodeIn_w_bits_last = auto_in_w_bits_last_0;\t// @[SRAM.scala:58:9]\n wire nodeIn_b_ready = auto_in_b_ready_0;\t// @[SRAM.scala:58:9]\n wire nodeIn_b_valid;\t// @[MixedNode.scala:551:17]\n wire [3:0] nodeIn_b_bits_id;\t// @[MixedNode.scala:551:17]\n wire [1:0] nodeIn_b_bits_resp;\t// @[MixedNode.scala:551:17]\n wire nodeIn_b_bits_echo_real_last;\t// @[MixedNode.scala:551:17]\n wire nodeIn_ar_ready;\t// @[MixedNode.scala:551:17]\n wire nodeIn_ar_valid = auto_in_ar_valid_0;\t// @[SRAM.scala:58:9]\n wire [3:0] nodeIn_ar_bits_id = auto_in_ar_bits_id_0;\t// @[SRAM.scala:58:9]\n wire [28:0] nodeIn_ar_bits_addr = auto_in_ar_bits_addr_0;\t// @[SRAM.scala:58:9]\n wire [7:0] nodeIn_ar_bits_len = auto_in_ar_bits_len_0;\t// @[SRAM.scala:58:9]\n wire [2:0] nodeIn_ar_bits_size = auto_in_ar_bits_size_0;\t// @[SRAM.scala:58:9]\n wire [1:0] nodeIn_ar_bits_burst = auto_in_ar_bits_burst_0;\t// @[SRAM.scala:58:9]\n wire nodeIn_ar_bits_lock = auto_in_ar_bits_lock_0;\t// @[SRAM.scala:58:9]\n wire [3:0] nodeIn_ar_bits_cache = auto_in_ar_bits_cache_0;\t// @[SRAM.scala:58:9]\n wire [2:0] nodeIn_ar_bits_prot = auto_in_ar_bits_prot_0;\t// @[SRAM.scala:58:9]\n wire [3:0] nodeIn_ar_bits_qos = auto_in_ar_bits_qos_0;\t// @[SRAM.scala:58:9]\n wire nodeIn_ar_bits_echo_real_last = auto_in_ar_bits_echo_real_last_0;\t// @[SRAM.scala:58:9]\n wire nodeIn_r_ready = auto_in_r_ready_0;\t// @[SRAM.scala:58:9]\n wire nodeIn_r_valid;\t// @[MixedNode.scala:551:17]\n wire [3:0] nodeIn_r_bits_id;\t// @[MixedNode.scala:551:17]\n wire [63:0] nodeIn_r_bits_data;\t// @[MixedNode.scala:551:17]\n wire [1:0] nodeIn_r_bits_resp;\t// @[MixedNode.scala:551:17]\n wire nodeIn_r_bits_echo_real_last;\t// @[MixedNode.scala:551:17]\n wire auto_in_aw_ready_0;\t// @[SRAM.scala:58:9]\n wire auto_in_w_ready_0;\t// @[SRAM.scala:58:9]\n wire auto_in_b_bits_echo_real_last_0;\t// @[SRAM.scala:58:9]\n wire [3:0] auto_in_b_bits_id_0;\t// @[SRAM.scala:58:9]\n wire [1:0] auto_in_b_bits_resp_0;\t// @[SRAM.scala:58:9]\n wire auto_in_b_valid_0;\t// @[SRAM.scala:58:9]\n wire auto_in_ar_ready_0;\t// @[SRAM.scala:58:9]\n wire auto_in_r_bits_echo_real_last_0;\t// @[SRAM.scala:58:9]\n wire [3:0] auto_in_r_bits_id_0;\t// @[SRAM.scala:58:9]\n wire [63:0] auto_in_r_bits_data_0;\t// @[SRAM.scala:58:9]\n wire [1:0] auto_in_r_bits_resp_0;\t// @[SRAM.scala:58:9]\n wire auto_in_r_valid_0;\t// @[SRAM.scala:58:9]\n wire _nodeIn_aw_ready_T_2;\t// @[SRAM.scala:97:32]\n assign auto_in_aw_ready_0 = nodeIn_aw_ready;\t// @[SRAM.scala:58:9]\n wire [28:0] _w_sel0_T = nodeIn_aw_bits_addr;\t// @[Parameters.scala:137:31]\n wire _nodeIn_w_ready_T_2;\t// @[SRAM.scala:98:32]\n assign auto_in_w_ready_0 = nodeIn_w_ready;\t// @[SRAM.scala:58:9]\n assign auto_in_b_valid_0 = nodeIn_b_valid;\t// @[SRAM.scala:58:9]\n assign auto_in_b_bits_id_0 = nodeIn_b_bits_id;\t// @[SRAM.scala:58:9]\n wire [1:0] _nodeIn_b_bits_resp_T;\t// @[SRAM.scala:101:26]\n assign auto_in_b_bits_resp_0 = nodeIn_b_bits_resp;\t// @[SRAM.scala:58:9]\n assign auto_in_b_bits_echo_real_last_0 = nodeIn_b_bits_echo_real_last;\t// @[SRAM.scala:58:9]\n wire _nodeIn_ar_ready_T_1;\t// @[SRAM.scala:122:31]\n assign auto_in_ar_ready_0 = nodeIn_ar_ready;\t// @[SRAM.scala:58:9]\n wire [28:0] _r_sel0_T = nodeIn_ar_bits_addr;\t// @[Parameters.scala:137:31]\n assign auto_in_r_valid_0 = nodeIn_r_valid;\t// @[SRAM.scala:58:9]\n assign auto_in_r_bits_id_0 = nodeIn_r_bits_id;\t// @[SRAM.scala:58:9]\n wire [63:0] _nodeIn_r_bits_data_T;\t// @[SRAM.scala:126:26]\n assign auto_in_r_bits_data_0 = nodeIn_r_bits_data;\t// @[SRAM.scala:58:9]\n wire [1:0] _nodeIn_r_bits_resp_T_1;\t// @[SRAM.scala:125:26]\n assign auto_in_r_bits_resp_0 = nodeIn_r_bits_resp;\t// @[SRAM.scala:58:9]\n assign auto_in_r_bits_echo_real_last_0 = nodeIn_r_bits_echo_real_last;\t// @[SRAM.scala:58:9]\n wire [7:0] wdata_0;\t// @[SRAM.scala:90:45]\n wire [7:0] wdata_1;\t// @[SRAM.scala:90:45]\n wire [7:0] wdata_2;\t// @[SRAM.scala:90:45]\n wire [7:0] wdata_3;\t// @[SRAM.scala:90:45]\n wire [7:0] wdata_4;\t// @[SRAM.scala:90:45]\n wire [7:0] wdata_5;\t// @[SRAM.scala:90:45]\n wire [7:0] wdata_6;\t// @[SRAM.scala:90:45]\n wire [7:0] wdata_7;\t// @[SRAM.scala:90:45]\n wire [25:0] _r_addr_T = nodeIn_ar_bits_addr[28:3];\t// @[SRAM.scala:70:49]\n wire _r_addr_T_1 = _r_addr_T[0];\t// @[SRAM.scala:70:{49,73}]\n wire _r_addr_T_2 = _r_addr_T[1];\t// @[SRAM.scala:70:{49,73}]\n wire _r_addr_T_3 = _r_addr_T[2];\t// @[SRAM.scala:70:{49,73}]\n wire _r_addr_T_4 = _r_addr_T[3];\t// @[SRAM.scala:70:{49,73}]\n wire _r_addr_T_5 = _r_addr_T[4];\t// @[SRAM.scala:70:{49,73}]\n wire _r_addr_T_6 = _r_addr_T[5];\t// @[SRAM.scala:70:{49,73}]\n wire _r_addr_T_7 = _r_addr_T[6];\t// @[SRAM.scala:70:{49,73}]\n wire _r_addr_T_8 = _r_addr_T[7];\t// @[SRAM.scala:70:{49,73}]\n wire _r_addr_T_9 = _r_addr_T[8];\t// @[SRAM.scala:70:{49,73}]\n wire _r_addr_T_10 = _r_addr_T[9];\t// @[SRAM.scala:70:{49,73}]\n wire _r_addr_T_11 = _r_addr_T[10];\t// @[SRAM.scala:70:{49,73}]\n wire _r_addr_T_12 = _r_addr_T[11];\t// @[SRAM.scala:70:{49,73}]\n wire _r_addr_T_13 = _r_addr_T[12];\t// @[SRAM.scala:70:{49,73}]\n wire _r_addr_T_14 = _r_addr_T[13];\t// @[SRAM.scala:70:{49,73}]\n wire _r_addr_T_15 = _r_addr_T[14];\t// @[SRAM.scala:70:{49,73}]\n wire _r_addr_T_16 = _r_addr_T[15];\t// @[SRAM.scala:70:{49,73}]\n wire _r_addr_T_17 = _r_addr_T[16];\t// @[SRAM.scala:70:{49,73}]\n wire _r_addr_T_18 = _r_addr_T[17];\t// @[SRAM.scala:70:{49,73}]\n wire _r_addr_T_19 = _r_addr_T[18];\t// @[SRAM.scala:70:{49,73}]\n wire _r_addr_T_20 = _r_addr_T[19];\t// @[SRAM.scala:70:{49,73}]\n wire _r_addr_T_21 = _r_addr_T[20];\t// @[SRAM.scala:70:{49,73}]\n wire _r_addr_T_22 = _r_addr_T[21];\t// @[SRAM.scala:70:{49,73}]\n wire _r_addr_T_23 = _r_addr_T[22];\t// @[SRAM.scala:70:{49,73}]\n wire _r_addr_T_24 = _r_addr_T[23];\t// @[SRAM.scala:70:{49,73}]\n wire _r_addr_T_25 = _r_addr_T[24];\t// @[SRAM.scala:70:{49,73}]\n wire _r_addr_T_26 = _r_addr_T[25];\t// @[SRAM.scala:70:{49,73}]\n wire [1:0] r_addr_lo_lo_lo_hi = {_r_addr_T_3, _r_addr_T_2};\t// @[SRAM.scala:70:{21,73}]\n wire [2:0] r_addr_lo_lo_lo = {r_addr_lo_lo_lo_hi, _r_addr_T_1};\t// @[SRAM.scala:70:{21,73}]\n wire [1:0] r_addr_lo_lo_hi_hi = {_r_addr_T_6, _r_addr_T_5};\t// @[SRAM.scala:70:{21,73}]\n wire [2:0] r_addr_lo_lo_hi = {r_addr_lo_lo_hi_hi, _r_addr_T_4};\t// @[SRAM.scala:70:{21,73}]\n wire [5:0] r_addr_lo_lo = {r_addr_lo_lo_hi, r_addr_lo_lo_lo};\t// @[SRAM.scala:70:21]\n wire [1:0] r_addr_lo_hi_lo_hi = {_r_addr_T_9, _r_addr_T_8};\t// @[SRAM.scala:70:{21,73}]\n wire [2:0] r_addr_lo_hi_lo = {r_addr_lo_hi_lo_hi, _r_addr_T_7};\t// @[SRAM.scala:70:{21,73}]\n wire [1:0] r_addr_lo_hi_hi_lo = {_r_addr_T_11, _r_addr_T_10};\t// @[SRAM.scala:70:{21,73}]\n wire [1:0] r_addr_lo_hi_hi_hi = {_r_addr_T_13, _r_addr_T_12};\t// @[SRAM.scala:70:{21,73}]\n wire [3:0] r_addr_lo_hi_hi = {r_addr_lo_hi_hi_hi, r_addr_lo_hi_hi_lo};\t// @[SRAM.scala:70:21]\n wire [6:0] r_addr_lo_hi = {r_addr_lo_hi_hi, r_addr_lo_hi_lo};\t// @[SRAM.scala:70:21]\n wire [12:0] r_addr_lo = {r_addr_lo_hi, r_addr_lo_lo};\t// @[SRAM.scala:70:21]\n wire [1:0] r_addr_hi_lo_lo_hi = {_r_addr_T_16, _r_addr_T_15};\t// @[SRAM.scala:70:{21,73}]\n wire [2:0] r_addr_hi_lo_lo = {r_addr_hi_lo_lo_hi, _r_addr_T_14};\t// @[SRAM.scala:70:{21,73}]\n wire [1:0] r_addr_hi_lo_hi_hi = {_r_addr_T_19, _r_addr_T_18};\t// @[SRAM.scala:70:{21,73}]\n wire [2:0] r_addr_hi_lo_hi = {r_addr_hi_lo_hi_hi, _r_addr_T_17};\t// @[SRAM.scala:70:{21,73}]\n wire [5:0] r_addr_hi_lo = {r_addr_hi_lo_hi, r_addr_hi_lo_lo};\t// @[SRAM.scala:70:21]\n wire [1:0] r_addr_hi_hi_lo_hi = {_r_addr_T_22, _r_addr_T_21};\t// @[SRAM.scala:70:{21,73}]\n wire [2:0] r_addr_hi_hi_lo = {r_addr_hi_hi_lo_hi, _r_addr_T_20};\t// @[SRAM.scala:70:{21,73}]\n wire [1:0] r_addr_hi_hi_hi_lo = {_r_addr_T_24, _r_addr_T_23};\t// @[SRAM.scala:70:{21,73}]\n wire [1:0] r_addr_hi_hi_hi_hi = {_r_addr_T_26, _r_addr_T_25};\t// @[SRAM.scala:70:{21,73}]\n wire [3:0] r_addr_hi_hi_hi = {r_addr_hi_hi_hi_hi, r_addr_hi_hi_hi_lo};\t// @[SRAM.scala:70:21]\n wire [6:0] r_addr_hi_hi = {r_addr_hi_hi_hi, r_addr_hi_hi_lo};\t// @[SRAM.scala:70:21]\n wire [12:0] r_addr_hi = {r_addr_hi_hi, r_addr_hi_lo};\t// @[SRAM.scala:70:21]\n wire [25:0] r_addr = {r_addr_hi, r_addr_lo};\t// @[SRAM.scala:70:21]\n wire [25:0] _rdata_WIRE = r_addr;\t// @[package.scala:100:58]\n wire [25:0] _w_addr_T = nodeIn_aw_bits_addr[28:3];\t// @[SRAM.scala:71:49]\n wire _w_addr_T_1 = _w_addr_T[0];\t// @[SRAM.scala:71:{49,73}]\n wire _w_addr_T_2 = _w_addr_T[1];\t// @[SRAM.scala:71:{49,73}]\n wire _w_addr_T_3 = _w_addr_T[2];\t// @[SRAM.scala:71:{49,73}]\n wire _w_addr_T_4 = _w_addr_T[3];\t// @[SRAM.scala:71:{49,73}]\n wire _w_addr_T_5 = _w_addr_T[4];\t// @[SRAM.scala:71:{49,73}]\n wire _w_addr_T_6 = _w_addr_T[5];\t// @[SRAM.scala:71:{49,73}]\n wire _w_addr_T_7 = _w_addr_T[6];\t// @[SRAM.scala:71:{49,73}]\n wire _w_addr_T_8 = _w_addr_T[7];\t// @[SRAM.scala:71:{49,73}]\n wire _w_addr_T_9 = _w_addr_T[8];\t// @[SRAM.scala:71:{49,73}]\n wire _w_addr_T_10 = _w_addr_T[9];\t// @[SRAM.scala:71:{49,73}]\n wire _w_addr_T_11 = _w_addr_T[10];\t// @[SRAM.scala:71:{49,73}]\n wire _w_addr_T_12 = _w_addr_T[11];\t// @[SRAM.scala:71:{49,73}]\n wire _w_addr_T_13 = _w_addr_T[12];\t// @[SRAM.scala:71:{49,73}]\n wire _w_addr_T_14 = _w_addr_T[13];\t// @[SRAM.scala:71:{49,73}]\n wire _w_addr_T_15 = _w_addr_T[14];\t// @[SRAM.scala:71:{49,73}]\n wire _w_addr_T_16 = _w_addr_T[15];\t// @[SRAM.scala:71:{49,73}]\n wire _w_addr_T_17 = _w_addr_T[16];\t// @[SRAM.scala:71:{49,73}]\n wire _w_addr_T_18 = _w_addr_T[17];\t// @[SRAM.scala:71:{49,73}]\n wire _w_addr_T_19 = _w_addr_T[18];\t// @[SRAM.scala:71:{49,73}]\n wire _w_addr_T_20 = _w_addr_T[19];\t// @[SRAM.scala:71:{49,73}]\n wire _w_addr_T_21 = _w_addr_T[20];\t// @[SRAM.scala:71:{49,73}]\n wire _w_addr_T_22 = _w_addr_T[21];\t// @[SRAM.scala:71:{49,73}]\n wire _w_addr_T_23 = _w_addr_T[22];\t// @[SRAM.scala:71:{49,73}]\n wire _w_addr_T_24 = _w_addr_T[23];\t// @[SRAM.scala:71:{49,73}]\n wire _w_addr_T_25 = _w_addr_T[24];\t// @[SRAM.scala:71:{49,73}]\n wire _w_addr_T_26 = _w_addr_T[25];\t// @[SRAM.scala:71:{49,73}]\n wire [1:0] w_addr_lo_lo_lo_hi = {_w_addr_T_3, _w_addr_T_2};\t// @[SRAM.scala:71:{21,73}]\n wire [2:0] w_addr_lo_lo_lo = {w_addr_lo_lo_lo_hi, _w_addr_T_1};\t// @[SRAM.scala:71:{21,73}]\n wire [1:0] w_addr_lo_lo_hi_hi = {_w_addr_T_6, _w_addr_T_5};\t// @[SRAM.scala:71:{21,73}]\n wire [2:0] w_addr_lo_lo_hi = {w_addr_lo_lo_hi_hi, _w_addr_T_4};\t// @[SRAM.scala:71:{21,73}]\n wire [5:0] w_addr_lo_lo = {w_addr_lo_lo_hi, w_addr_lo_lo_lo};\t// @[SRAM.scala:71:21]\n wire [1:0] w_addr_lo_hi_lo_hi = {_w_addr_T_9, _w_addr_T_8};\t// @[SRAM.scala:71:{21,73}]\n wire [2:0] w_addr_lo_hi_lo = {w_addr_lo_hi_lo_hi, _w_addr_T_7};\t// @[SRAM.scala:71:{21,73}]\n wire [1:0] w_addr_lo_hi_hi_lo = {_w_addr_T_11, _w_addr_T_10};\t// @[SRAM.scala:71:{21,73}]\n wire [1:0] w_addr_lo_hi_hi_hi = {_w_addr_T_13, _w_addr_T_12};\t// @[SRAM.scala:71:{21,73}]\n wire [3:0] w_addr_lo_hi_hi = {w_addr_lo_hi_hi_hi, w_addr_lo_hi_hi_lo};\t// @[SRAM.scala:71:21]\n wire [6:0] w_addr_lo_hi = {w_addr_lo_hi_hi, w_addr_lo_hi_lo};\t// @[SRAM.scala:71:21]\n wire [12:0] w_addr_lo = {w_addr_lo_hi, w_addr_lo_lo};\t// @[SRAM.scala:71:21]\n wire [1:0] w_addr_hi_lo_lo_hi = {_w_addr_T_16, _w_addr_T_15};\t// @[SRAM.scala:71:{21,73}]\n wire [2:0] w_addr_hi_lo_lo = {w_addr_hi_lo_lo_hi, _w_addr_T_14};\t// @[SRAM.scala:71:{21,73}]\n wire [1:0] w_addr_hi_lo_hi_hi = {_w_addr_T_19, _w_addr_T_18};\t// @[SRAM.scala:71:{21,73}]\n wire [2:0] w_addr_hi_lo_hi = {w_addr_hi_lo_hi_hi, _w_addr_T_17};\t// @[SRAM.scala:71:{21,73}]\n wire [5:0] w_addr_hi_lo = {w_addr_hi_lo_hi, w_addr_hi_lo_lo};\t// @[SRAM.scala:71:21]\n wire [1:0] w_addr_hi_hi_lo_hi = {_w_addr_T_22, _w_addr_T_21};\t// @[SRAM.scala:71:{21,73}]\n wire [2:0] w_addr_hi_hi_lo = {w_addr_hi_hi_lo_hi, _w_addr_T_20};\t// @[SRAM.scala:71:{21,73}]\n wire [1:0] w_addr_hi_hi_hi_lo = {_w_addr_T_24, _w_addr_T_23};\t// @[SRAM.scala:71:{21,73}]\n wire [1:0] w_addr_hi_hi_hi_hi = {_w_addr_T_26, _w_addr_T_25};\t// @[SRAM.scala:71:{21,73}]\n wire [3:0] w_addr_hi_hi_hi = {w_addr_hi_hi_hi_hi, w_addr_hi_hi_hi_lo};\t// @[SRAM.scala:71:21]\n wire [6:0] w_addr_hi_hi = {w_addr_hi_hi_hi, w_addr_hi_hi_lo};\t// @[SRAM.scala:71:21]\n wire [12:0] w_addr_hi = {w_addr_hi_hi, w_addr_hi_lo};\t// @[SRAM.scala:71:21]\n wire [25:0] w_addr = {w_addr_hi, w_addr_lo};\t// @[SRAM.scala:71:21]\n wire [29:0] _r_sel0_T_1 = {1'h0, _r_sel0_T};\t// @[Parameters.scala:137:{31,41}]\n wire [29:0] _r_sel0_T_2 = _r_sel0_T_1 & 30'h20000000;\t// @[Parameters.scala:137:{41,46}]\n wire [29:0] _r_sel0_T_3 = _r_sel0_T_2;\t// @[Parameters.scala:137:46]\n wire r_sel0 = _r_sel0_T_3 == 30'h0;\t// @[Parameters.scala:137:{46,59}]\n wire [29:0] _w_sel0_T_1 = {1'h0, _w_sel0_T};\t// @[Parameters.scala:137:{31,41}]\n wire [29:0] _w_sel0_T_2 = _w_sel0_T_1 & 30'h20000000;\t// @[Parameters.scala:137:{41,46}]\n wire [29:0] _w_sel0_T_3 = _w_sel0_T_2;\t// @[Parameters.scala:137:46]\n wire w_sel0 = _w_sel0_T_3 == 30'h0;\t// @[Parameters.scala:137:{46,59}]\n reg w_full;\t// @[SRAM.scala:75:25]\n assign nodeIn_b_valid = w_full;\t// @[SRAM.scala:75:25]\n reg [3:0] w_id;\t// @[SRAM.scala:76:21]\n assign nodeIn_b_bits_id = w_id;\t// @[SRAM.scala:76:21]\n reg w_echo_real_last;\t// @[SRAM.scala:77:21]\n assign nodeIn_b_bits_echo_real_last = w_echo_real_last;\t// @[SRAM.scala:77:21]\n reg r_sel1;\t// @[SRAM.scala:78:25]\n reg w_sel1;\t// @[SRAM.scala:79:25]\n wire _T_3 = nodeIn_aw_ready & nodeIn_aw_valid;\t// @[Decoupled.scala:51:35]\n wire [7:0] _wdata_T = nodeIn_w_bits_data[7:0];\t// @[SRAM.scala:90:66]\n assign wdata_0 = _wdata_T;\t// @[SRAM.scala:90:{45,66}]\n wire [7:0] _wdata_T_1 = nodeIn_w_bits_data[15:8];\t// @[SRAM.scala:90:66]\n assign wdata_1 = _wdata_T_1;\t// @[SRAM.scala:90:{45,66}]\n wire [7:0] _wdata_T_2 = nodeIn_w_bits_data[23:16];\t// @[SRAM.scala:90:66]\n assign wdata_2 = _wdata_T_2;\t// @[SRAM.scala:90:{45,66}]\n wire [7:0] _wdata_T_3 = nodeIn_w_bits_data[31:24];\t// @[SRAM.scala:90:66]\n assign wdata_3 = _wdata_T_3;\t// @[SRAM.scala:90:{45,66}]\n wire [7:0] _wdata_T_4 = nodeIn_w_bits_data[39:32];\t// @[SRAM.scala:90:66]\n assign wdata_4 = _wdata_T_4;\t// @[SRAM.scala:90:{45,66}]\n wire [7:0] _wdata_T_5 = nodeIn_w_bits_data[47:40];\t// @[SRAM.scala:90:66]\n assign wdata_5 = _wdata_T_5;\t// @[SRAM.scala:90:{45,66}]\n wire [7:0] _wdata_T_6 = nodeIn_w_bits_data[55:48];\t// @[SRAM.scala:90:66]\n assign wdata_6 = _wdata_T_6;\t// @[SRAM.scala:90:{45,66}]\n wire [7:0] _wdata_T_7 = nodeIn_w_bits_data[63:56];\t// @[SRAM.scala:90:66]\n assign wdata_7 = _wdata_T_7;\t// @[SRAM.scala:90:{45,66}]\n wire _nodeIn_aw_ready_T = ~w_full;\t// @[SRAM.scala:75:25, :97:50]\n wire _nodeIn_aw_ready_T_1 = nodeIn_b_ready | _nodeIn_aw_ready_T;\t// @[SRAM.scala:97:{47,50}]\n assign _nodeIn_aw_ready_T_2 = nodeIn_w_valid & _nodeIn_aw_ready_T_1;\t// @[SRAM.scala:97:{32,47}]\n assign nodeIn_aw_ready = _nodeIn_aw_ready_T_2;\t// @[SRAM.scala:97:32]\n wire _nodeIn_w_ready_T = ~w_full;\t// @[SRAM.scala:75:25, :97:50, :98:50]\n wire _nodeIn_w_ready_T_1 = nodeIn_b_ready | _nodeIn_w_ready_T;\t// @[SRAM.scala:98:{47,50}]\n assign _nodeIn_w_ready_T_2 = nodeIn_aw_valid & _nodeIn_w_ready_T_1;\t// @[SRAM.scala:98:{32,47}]\n assign nodeIn_w_ready = _nodeIn_w_ready_T_2;\t// @[SRAM.scala:98:32]\n assign _nodeIn_b_bits_resp_T = w_sel1 ? 2'h0 : 2'h3;\t// @[SRAM.scala:79:25, :101:26]\n assign nodeIn_b_bits_resp = _nodeIn_b_bits_resp_T;\t// @[SRAM.scala:101:26]\n reg r_full;\t// @[SRAM.scala:104:25]\n assign nodeIn_r_valid = r_full;\t// @[SRAM.scala:104:25]\n reg [3:0] r_id;\t// @[SRAM.scala:105:21]\n assign nodeIn_r_bits_id = r_id;\t// @[SRAM.scala:105:21]\n reg r_echo_real_last;\t// @[SRAM.scala:106:21]\n assign nodeIn_r_bits_echo_real_last = r_echo_real_last;\t// @[SRAM.scala:106:21]\n wire ren = nodeIn_ar_ready & nodeIn_ar_valid;\t// @[Decoupled.scala:51:35]\n reg rdata_REG;\t// @[package.scala:100:91]\n reg [7:0] rdata_r_0;\t// @[package.scala:88:63]\n reg [7:0] rdata_r_1;\t// @[package.scala:88:63]\n reg [7:0] rdata_r_2;\t// @[package.scala:88:63]\n reg [7:0] rdata_r_3;\t// @[package.scala:88:63]\n reg [7:0] rdata_r_4;\t// @[package.scala:88:63]\n reg [7:0] rdata_r_5;\t// @[package.scala:88:63]\n reg [7:0] rdata_r_6;\t// @[package.scala:88:63]\n reg [7:0] rdata_r_7;\t// @[package.scala:88:63]\n wire [7:0] rdata_0 = rdata_REG ? _mem_R0_data[7:0] : rdata_r_0;\t// @[package.scala:88:{42,63}, :100:91]\n wire [7:0] rdata_1 = rdata_REG ? _mem_R0_data[15:8] : rdata_r_1;\t// @[package.scala:88:{42,63}, :100:91]\n wire [7:0] rdata_2 = rdata_REG ? _mem_R0_data[23:16] : rdata_r_2;\t// @[package.scala:88:{42,63}, :100:91]\n wire [7:0] rdata_3 = rdata_REG ? _mem_R0_data[31:24] : rdata_r_3;\t// @[package.scala:88:{42,63}, :100:91]\n wire [7:0] rdata_4 = rdata_REG ? _mem_R0_data[39:32] : rdata_r_4;\t// @[package.scala:88:{42,63}, :100:91]\n wire [7:0] rdata_5 = rdata_REG ? _mem_R0_data[47:40] : rdata_r_5;\t// @[package.scala:88:{42,63}, :100:91]\n wire [7:0] rdata_6 = rdata_REG ? _mem_R0_data[55:48] : rdata_r_6;\t// @[package.scala:88:{42,63}, :100:91]\n wire [7:0] rdata_7 = rdata_REG ? _mem_R0_data[63:56] : rdata_r_7;\t// @[package.scala:88:{42,63}, :100:91]\n wire _nodeIn_ar_ready_T = ~r_full;\t// @[SRAM.scala:104:25, :122:34]\n assign _nodeIn_ar_ready_T_1 = nodeIn_r_ready | _nodeIn_ar_ready_T;\t// @[SRAM.scala:122:{31,34}]\n assign nodeIn_ar_ready = _nodeIn_ar_ready_T_1;\t// @[SRAM.scala:122:31]\n assign _nodeIn_r_bits_resp_T_1 = r_sel1 ? 2'h0 : 2'h3;\t// @[SRAM.scala:78:25, :125:26]\n assign nodeIn_r_bits_resp = _nodeIn_r_bits_resp_T_1;\t// @[SRAM.scala:125:26]\n wire [15:0] nodeIn_r_bits_data_lo_lo = {rdata_1, rdata_0};\t// @[package.scala:88:42]\n wire [15:0] nodeIn_r_bits_data_lo_hi = {rdata_3, rdata_2};\t// @[package.scala:88:42]\n wire [31:0] nodeIn_r_bits_data_lo = {nodeIn_r_bits_data_lo_hi, nodeIn_r_bits_data_lo_lo};\t// @[SRAM.scala:126:26]\n wire [15:0] nodeIn_r_bits_data_hi_lo = {rdata_5, rdata_4};\t// @[package.scala:88:42]\n wire [15:0] nodeIn_r_bits_data_hi_hi = {rdata_7, rdata_6};\t// @[package.scala:88:42]\n wire [31:0] nodeIn_r_bits_data_hi = {nodeIn_r_bits_data_hi_hi, nodeIn_r_bits_data_hi_lo};\t// @[SRAM.scala:126:26]\n assign _nodeIn_r_bits_data_T = {nodeIn_r_bits_data_hi, nodeIn_r_bits_data_lo};\t// @[SRAM.scala:126:26]\n assign nodeIn_r_bits_data = _nodeIn_r_bits_data_T;\t// @[SRAM.scala:126:26]\n always @(posedge clock) begin\t// @[SRAM.scala:58:9]\n if (reset) begin\t// @[SRAM.scala:58:9]\n w_full <= 1'h0;\t// @[SRAM.scala:75:25]\n r_full <= 1'h0;\t// @[SRAM.scala:104:25]\n end\n else begin\t// @[SRAM.scala:58:9]\n w_full <= _T_3 | ~(nodeIn_b_ready & nodeIn_b_valid) & w_full;\t// @[Decoupled.scala:51:35]\n r_full <= ren | ~(nodeIn_r_ready & nodeIn_r_valid) & r_full;\t// @[Decoupled.scala:51:35]\n end\n if (_T_3) begin\t// @[Decoupled.scala:51:35]\n w_id <= nodeIn_aw_bits_id;\t// @[SRAM.scala:76:21]\n w_echo_real_last <= nodeIn_aw_bits_echo_real_last;\t// @[SRAM.scala:77:21]\n end\n r_sel1 <= r_sel0;\t// @[Parameters.scala:137:59]\n w_sel1 <= w_sel0;\t// @[Parameters.scala:137:59]\n if (ren) begin\t// @[Decoupled.scala:51:35]\n r_id <= nodeIn_ar_bits_id;\t// @[SRAM.scala:105:21]\n r_echo_real_last <= nodeIn_ar_bits_echo_real_last;\t// @[SRAM.scala:106:21]\n end\n rdata_REG <= ren;\t// @[Decoupled.scala:51:35]\n if (rdata_REG) begin\t// @[package.scala:100:91]\n rdata_r_0 <= _mem_R0_data[7:0];\t// @[package.scala:88:63]\n rdata_r_1 <= _mem_R0_data[15:8];\t// @[package.scala:88:63]\n rdata_r_2 <= _mem_R0_data[23:16];\t// @[package.scala:88:63]\n rdata_r_3 <= _mem_R0_data[31:24];\t// @[package.scala:88:63]\n rdata_r_4 <= _mem_R0_data[39:32];\t// @[package.scala:88:63]\n rdata_r_5 <= _mem_R0_data[47:40];\t// @[package.scala:88:63]\n rdata_r_6 <= _mem_R0_data[55:48];\t// @[package.scala:88:63]\n rdata_r_7 <= _mem_R0_data[63:56];\t// @[package.scala:88:63]\n end\n always @(posedge)\n mem mem (\t// @[DescribedSRAM.scala:17:26]\n .R0_addr (_rdata_WIRE),\t// @[package.scala:100:58]\n .R0_en (ren),\t// @[Decoupled.scala:51:35]\n .R0_clk (clock),\n .R0_data (_mem_R0_data),\n .W0_addr (w_addr),\t// @[SRAM.scala:71:21]\n .W0_en (_T_3 & w_sel0),\t// @[Decoupled.scala:51:35]\n .W0_clk (clock),\n .W0_data ({wdata_7, wdata_6, wdata_5, wdata_4, wdata_3, wdata_2, wdata_1, wdata_0}),\t// @[DescribedSRAM.scala:17:26]\n .W0_mask (nodeIn_w_bits_strb)\t// @[MixedNode.scala:551:17]\n );\t// @[DescribedSRAM.scala:17:26]\n assign auto_in_aw_ready = auto_in_aw_ready_0;\t// @[SRAM.scala:58:9]\n assign auto_in_w_ready = auto_in_w_ready_0;\t// @[SRAM.scala:58:9]\n assign auto_in_b_valid = auto_in_b_valid_0;\t// @[SRAM.scala:58:9]\n assign auto_in_b_bits_id = auto_in_b_bits_id_0;\t// @[SRAM.scala:58:9]\n assign auto_in_b_bits_resp = auto_in_b_bits_resp_0;\t// @[SRAM.scala:58:9]\n assign auto_in_b_bits_echo_real_last = auto_in_b_bits_echo_real_last_0;\t// @[SRAM.scala:58:9]\n assign auto_in_ar_ready = auto_in_ar_ready_0;\t// @[SRAM.scala:58:9]\n assign auto_in_r_valid = auto_in_r_valid_0;\t// @[SRAM.scala:58:9]\n assign auto_in_r_bits_id = auto_in_r_bits_id_0;\t// @[SRAM.scala:58:9]\n assign auto_in_r_bits_data = auto_in_r_bits_data_0;\t// @[SRAM.scala:58:9]\n assign auto_in_r_bits_resp = auto_in_r_bits_resp_0;\t// @[SRAM.scala:58:9]\n assign auto_in_r_bits_echo_real_last = auto_in_r_bits_echo_real_last_0;\t// @[SRAM.scala:58:9]\nendmodule"}}},{"rowIdx":34388,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module ZstdMatchFinder : \n input clock : Clock \n input reset : Reset \n output io : { l2io : { memloader_userif : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt, size : UInt, data : UInt<256>, cmd : UInt}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>}}, flip no_memops_inflight : UInt<1>}, lit_memwriter_userif : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt, size : UInt, data : UInt<256>, cmd : UInt}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>}}, flip no_memops_inflight : UInt<1>}, seq_memwriter_userif : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt, size : UInt, data : UInt<256>, cmd : UInt}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>}}, flip no_memops_inflight : UInt<1>}}, flip src : { compress_src_info : { flip ready : UInt<1>, valid : UInt<1>, bits : { ip : UInt<64>, isize : UInt<64>}}, compress_src_info2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { ip : UInt<64>, isize : UInt<64>}}}, flip dst : { lit_dst_info : { flip ready : UInt<1>, valid : UInt<1>, bits : { op : UInt<64>, cmpflag : UInt<64>}}, seq_dst_info : { flip ready : UInt<1>, valid : UInt<1>, bits : { op : UInt<64>, cmpflag : UInt<64>}}}, buff_consumed : { lit_consumed_bytes : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, seq_consumed_bytes : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, flip MAX_OFFSET_ALLOWED : UInt<64>, flip RUNTIME_HT_NUM_ENTRIES_LOG2 : UInt<5>, flip ALGORITHM : UInt<1>} \n\n\n node _T = and(io.src.compress_src_info.ready, io.src.compress_src_info.valid) \n when _T : \n regreset loginfo_cycles : UInt<64>, clock, reset, UInt<64>(0h0) \n node _loginfo_cycles_T = add(loginfo_cycles, UInt<1>(0h1)) \n node _loginfo_cycles_T_1 = tail(_loginfo_cycles_T, 1) \n connect loginfo_cycles, _loginfo_cycles_T_1 \n node _T_1 = asUInt(reset) \n node _T_2 = eq(_T_1, UInt<1>(0h0)) \n when _T_2 : \n printf(clock, UInt<1>(0h1), \"cy: %d, \", loginfo_cycles) : printf \n node _T_3 = asUInt(reset) \n node _T_4 = eq(_T_3, UInt<1>(0h0)) \n when _T_4 : \n printf(clock, UInt<1>(0h1), \"MATCHFINDER_SRC_INFO_FIRE\\n\") : printf_1 \n regreset loginfo_cycles_1 : UInt<64>, clock, reset, UInt<64>(0h0) \n node _loginfo_cycles_T_2 = add(loginfo_cycles_1, UInt<1>(0h1)) \n node _loginfo_cycles_T_3 = tail(_loginfo_cycles_T_2, 1) \n connect loginfo_cycles_1, _loginfo_cycles_T_3 \n node _T_5 = asUInt(reset) \n node _T_6 = eq(_T_5, UInt<1>(0h0)) \n when _T_6 : \n printf(clock, UInt<1>(0h1), \"cy: %d, \", loginfo_cycles_1) : printf_2 \n node _T_7 = asUInt(reset) \n node _T_8 = eq(_T_7, UInt<1>(0h0)) \n when _T_8 : \n printf(clock, UInt<1>(0h1), \"addr: 0x%x, size: %d\\n\", io.src.compress_src_info.bits.ip, io.src.compress_src_info.bits.isize) : printf_3 \n node _T_9 = and(io.src.compress_src_info2.ready, io.src.compress_src_info2.valid) \n when _T_9 : \n regreset loginfo_cycles_2 : UInt<64>, clock, reset, UInt<64>(0h0) \n node _loginfo_cycles_T_4 = add(loginfo_cycles_2, UInt<1>(0h1)) \n node _loginfo_cycles_T_5 = tail(_loginfo_cycles_T_4, 1) \n connect loginfo_cycles_2, _loginfo_cycles_T_5 \n node _T_10 = asUInt(reset) \n node _T_11 = eq(_T_10, UInt<1>(0h0)) \n when _T_11 : \n printf(clock, UInt<1>(0h1), \"cy: %d, \", loginfo_cycles_2) : printf_4 \n node _T_12 = asUInt(reset) \n node _T_13 = eq(_T_12, UInt<1>(0h0)) \n when _T_13 : \n printf(clock, UInt<1>(0h1), \"MATCHFINDER_SRC_INFO2_FIRE\\n\") : printf_5 \n regreset loginfo_cycles_3 : UInt<64>, clock, reset, UInt<64>(0h0) \n node _loginfo_cycles_T_6 = add(loginfo_cycles_3, UInt<1>(0h1)) \n node _loginfo_cycles_T_7 = tail(_loginfo_cycles_T_6, 1) \n connect loginfo_cycles_3, _loginfo_cycles_T_7 \n node _T_14 = asUInt(reset) \n node _T_15 = eq(_T_14, UInt<1>(0h0)) \n when _T_15 : \n printf(clock, UInt<1>(0h1), \"cy: %d, \", loginfo_cycles_3) : printf_6 \n node _T_16 = asUInt(reset) \n node _T_17 = eq(_T_16, UInt<1>(0h0)) \n when _T_17 : \n printf(clock, UInt<1>(0h1), \"addr: 0x%x, size: %d\\n\", io.src.compress_src_info2.bits.ip, io.src.compress_src_info2.bits.isize) : printf_7 \n node _T_18 = and(io.dst.lit_dst_info.ready, io.dst.lit_dst_info.valid) \n when _T_18 : \n regreset loginfo_cycles_4 : UInt<64>, clock, reset, UInt<64>(0h0) \n node _loginfo_cycles_T_8 = add(loginfo_cycles_4, UInt<1>(0h1)) \n node _loginfo_cycles_T_9 = tail(_loginfo_cycles_T_8, 1) \n connect loginfo_cycles_4, _loginfo_cycles_T_9 \n node _T_19 = asUInt(reset) \n node _T_20 = eq(_T_19, UInt<1>(0h0)) \n when _T_20 : \n printf(clock, UInt<1>(0h1), \"cy: %d, \", loginfo_cycles_4) : printf_8 \n node _T_21 = asUInt(reset) \n node _T_22 = eq(_T_21, UInt<1>(0h0)) \n when _T_22 : \n printf(clock, UInt<1>(0h1), \"MATCHFINDER_LIT_DST_INFO_FIRE\\n\") : printf_9 \n regreset loginfo_cycles_5 : UInt<64>, clock, reset, UInt<64>(0h0) \n node _loginfo_cycles_T_10 = add(loginfo_cycles_5, UInt<1>(0h1)) \n node _loginfo_cycles_T_11 = tail(_loginfo_cycles_T_10, 1) \n connect loginfo_cycles_5, _loginfo_cycles_T_11 \n node _T_23 = asUInt(reset) \n node _T_24 = eq(_T_23, UInt<1>(0h0)) \n when _T_24 : \n printf(clock, UInt<1>(0h1), \"cy: %d, \", loginfo_cycles_5) : printf_10 \n node _T_25 = asUInt(reset) \n node _T_26 = eq(_T_25, UInt<1>(0h0)) \n when _T_26 : \n printf(clock, UInt<1>(0h1), \"op: 0x%x, cmpflag: 0x%x\\n\", io.dst.lit_dst_info.bits.op, io.dst.lit_dst_info.bits.cmpflag) : printf_11 \n node _T_27 = and(io.dst.seq_dst_info.ready, io.dst.seq_dst_info.valid) \n when _T_27 : \n regreset loginfo_cycles_6 : UInt<64>, clock, reset, UInt<64>(0h0) \n node _loginfo_cycles_T_12 = add(loginfo_cycles_6, UInt<1>(0h1)) \n node _loginfo_cycles_T_13 = tail(_loginfo_cycles_T_12, 1) \n connect loginfo_cycles_6, _loginfo_cycles_T_13 \n node _T_28 = asUInt(reset) \n node _T_29 = eq(_T_28, UInt<1>(0h0)) \n when _T_29 : \n printf(clock, UInt<1>(0h1), \"cy: %d, \", loginfo_cycles_6) : printf_12 \n node _T_30 = asUInt(reset) \n node _T_31 = eq(_T_30, UInt<1>(0h0)) \n when _T_31 : \n printf(clock, UInt<1>(0h1), \"MATCHFINDER_SEQ_DST_INFO_FIRE\\n\") : printf_13 \n regreset loginfo_cycles_7 : UInt<64>, clock, reset, UInt<64>(0h0) \n node _loginfo_cycles_T_14 = add(loginfo_cycles_7, UInt<1>(0h1)) \n node _loginfo_cycles_T_15 = tail(_loginfo_cycles_T_14, 1) \n connect loginfo_cycles_7, _loginfo_cycles_T_15 \n node _T_32 = asUInt(reset) \n node _T_33 = eq(_T_32, UInt<1>(0h0)) \n when _T_33 : \n printf(clock, UInt<1>(0h1), \"cy: %d, \", loginfo_cycles_7) : printf_14 \n node _T_34 = asUInt(reset) \n node _T_35 = eq(_T_34, UInt<1>(0h0)) \n when _T_35 : \n printf(clock, UInt<1>(0h1), \"op: 0x%x, cmpflag: 0x%x\\n\", io.dst.seq_dst_info.bits.op, io.dst.seq_dst_info.bits.cmpflag) : printf_15 \n node _T_36 = and(io.buff_consumed.lit_consumed_bytes.ready, io.buff_consumed.lit_consumed_bytes.valid) \n when _T_36 : \n regreset loginfo_cycles_8 : UInt<64>, clock, reset, UInt<64>(0h0) \n node _loginfo_cycles_T_16 = add(loginfo_cycles_8, UInt<1>(0h1)) \n node _loginfo_cycles_T_17 = tail(_loginfo_cycles_T_16, 1) \n connect loginfo_cycles_8, _loginfo_cycles_T_17 \n node _T_37 = asUInt(reset) \n node _T_38 = eq(_T_37, UInt<1>(0h0)) \n when _T_38 : \n printf(clock, UInt<1>(0h1), \"cy: %d, \", loginfo_cycles_8) : printf_16 \n node _T_39 = asUInt(reset) \n node _T_40 = eq(_T_39, UInt<1>(0h0)) \n when _T_40 : \n printf(clock, UInt<1>(0h1), \"MATCHFINDER_LIT_CONSUMED_BYTES_FIRE\\n\") : printf_17 \n regreset loginfo_cycles_9 : UInt<64>, clock, reset, UInt<64>(0h0) \n node _loginfo_cycles_T_18 = add(loginfo_cycles_9, UInt<1>(0h1)) \n node _loginfo_cycles_T_19 = tail(_loginfo_cycles_T_18, 1) \n connect loginfo_cycles_9, _loginfo_cycles_T_19 \n node _T_41 = asUInt(reset) \n node _T_42 = eq(_T_41, UInt<1>(0h0)) \n when _T_42 : \n printf(clock, UInt<1>(0h1), \"cy: %d, \", loginfo_cycles_9) : printf_18 \n node _T_43 = asUInt(reset) \n node _T_44 = eq(_T_43, UInt<1>(0h0)) \n when _T_44 : \n printf(clock, UInt<1>(0h1), \"consumed_bytes: %d\\n\", io.buff_consumed.lit_consumed_bytes.bits) : printf_19 \n node _T_45 = and(io.buff_consumed.seq_consumed_bytes.ready, io.buff_consumed.seq_consumed_bytes.valid) \n when _T_45 : \n regreset loginfo_cycles_10 : UInt<64>, clock, reset, UInt<64>(0h0) \n node _loginfo_cycles_T_20 = add(loginfo_cycles_10, UInt<1>(0h1)) \n node _loginfo_cycles_T_21 = tail(_loginfo_cycles_T_20, 1) \n connect loginfo_cycles_10, _loginfo_cycles_T_21 \n node _T_46 = asUInt(reset) \n node _T_47 = eq(_T_46, UInt<1>(0h0)) \n when _T_47 : \n printf(clock, UInt<1>(0h1), \"cy: %d, \", loginfo_cycles_10) : printf_20 \n node _T_48 = asUInt(reset) \n node _T_49 = eq(_T_48, UInt<1>(0h0)) \n when _T_49 : \n printf(clock, UInt<1>(0h1), \"MATCHFINDER_SEQ_CONSUMED_BYTES_FIRE\\n\") : printf_21 \n regreset loginfo_cycles_11 : UInt<64>, clock, reset, UInt<64>(0h0) \n node _loginfo_cycles_T_22 = add(loginfo_cycles_11, UInt<1>(0h1)) \n node _loginfo_cycles_T_23 = tail(_loginfo_cycles_T_22, 1) \n connect loginfo_cycles_11, _loginfo_cycles_T_23 \n node _T_50 = asUInt(reset) \n node _T_51 = eq(_T_50, UInt<1>(0h0)) \n when _T_51 : \n printf(clock, UInt<1>(0h1), \"cy: %d, \", loginfo_cycles_11) : printf_22 \n node _T_52 = asUInt(reset) \n node _T_53 = eq(_T_52, UInt<1>(0h0)) \n when _T_53 : \n printf(clock, UInt<1>(0h1), \"consumed_bytes: %d\\n\", io.buff_consumed.seq_consumed_bytes.bits) : printf_23 \n inst memloader of LZ77HashMatcherMemLoader \n connect memloader.clock, clock\n\n connect memloader.reset, reset\n\n connect memloader.io.l2helperUser.no_memops_inflight, io.l2io.memloader_userif.no_memops_inflight \n connect memloader.io.l2helperUser.resp, io.l2io.memloader_userif.resp \n connect io.l2io.memloader_userif.req.bits, memloader.io.l2helperUser.req.bits \n connect io.l2io.memloader_userif.req.valid, memloader.io.l2helperUser.req.valid \n connect memloader.io.l2helperUser.req.ready, io.l2io.memloader_userif.req.ready \n connect memloader.io.src_info, io.src.compress_src_info \n node use_zstd = eq(io.ALGORITHM, UInt<1>(0h0)) \n inst lz77hashmatcher of LZ77HashMatcher \n connect lz77hashmatcher.clock, clock\n\n connect lz77hashmatcher.reset, reset\n\n node _lz77hashmatcher_io_write_snappy_header_T = eq(use_zstd, UInt<1>(0h0)) \n connect lz77hashmatcher.io.write_snappy_header, _lz77hashmatcher_io_write_snappy_header_T \n connect lz77hashmatcher.io.MAX_OFFSET_ALLOWED, io.MAX_OFFSET_ALLOWED \n connect lz77hashmatcher.io.RUNTIME_HT_NUM_ENTRIES_LOG2, io.RUNTIME_HT_NUM_ENTRIES_LOG2 \n connect lz77hashmatcher.io.memloader_in, memloader.io.consumer \n connect lz77hashmatcher.io.memloader_optional_hbsram_in, memloader.io.optional_hbsram_write \n connect lz77hashmatcher.io.src_info, io.src.compress_src_info2 \n inst zstd_litlen_injector of ZstdMatchFinderLitLenInjector \n connect zstd_litlen_injector.clock, clock\n\n connect zstd_litlen_injector.reset, reset\n\n connect zstd_litlen_injector.io.memwrites_in, lz77hashmatcher.io.memwrites_out \n inst seq_memwriter of ZstdMatchFinderMemwriter \n connect seq_memwriter.clock, clock\n\n connect seq_memwriter.reset, reset\n\n connect seq_memwriter.io.memwrites_in, zstd_litlen_injector.io.seq_memwrites_out \n connect seq_memwriter.io.compress_dest_info, io.dst.seq_dst_info \n node _seq_memwriter_io_force_write_T = eq(use_zstd, UInt<1>(0h0)) \n connect seq_memwriter.io.force_write, _seq_memwriter_io_force_write_T \n connect seq_memwriter.io.l2io.no_memops_inflight, io.l2io.seq_memwriter_userif.no_memops_inflight \n connect seq_memwriter.io.l2io.resp, io.l2io.seq_memwriter_userif.resp \n connect io.l2io.seq_memwriter_userif.req.bits, seq_memwriter.io.l2io.req.bits \n connect io.l2io.seq_memwriter_userif.req.valid, seq_memwriter.io.l2io.req.valid \n connect seq_memwriter.io.l2io.req.ready, io.l2io.seq_memwriter_userif.req.ready \n inst lit_memwriter of ZstdMatchFinderMemwriter_1 \n connect lit_memwriter.clock, clock\n\n connect lit_memwriter.reset, reset\n\n connect lit_memwriter.io.memwrites_in, zstd_litlen_injector.io.lit_memwrites_out \n connect lit_memwriter.io.compress_dest_info, io.dst.lit_dst_info \n connect lit_memwriter.io.force_write, UInt<1>(0h0) \n connect lit_memwriter.io.l2io.no_memops_inflight, io.l2io.lit_memwriter_userif.no_memops_inflight \n connect lit_memwriter.io.l2io.resp, io.l2io.lit_memwriter_userif.resp \n connect io.l2io.lit_memwriter_userif.req.bits, lit_memwriter.io.l2io.req.bits \n connect io.l2io.lit_memwriter_userif.req.valid, lit_memwriter.io.l2io.req.valid \n connect lit_memwriter.io.l2io.req.ready, io.l2io.lit_memwriter_userif.req.ready \n connect io.buff_consumed.lit_consumed_bytes.bits, lit_memwriter.io.written_bytes.bits \n connect io.buff_consumed.lit_consumed_bytes.valid, lit_memwriter.io.written_bytes.valid \n connect lit_memwriter.io.written_bytes.ready, io.buff_consumed.lit_consumed_bytes.ready \n connect io.buff_consumed.seq_consumed_bytes.bits, seq_memwriter.io.written_bytes.bits \n connect io.buff_consumed.seq_consumed_bytes.valid, seq_memwriter.io.written_bytes.valid \n connect seq_memwriter.io.written_bytes.ready, io.buff_consumed.seq_consumed_bytes.ready"},"response":{"kind":"string","value":"module ZstdMatchFinder(\t// @[ZstdMatchFinder.scala:48:7]\n input clock,\t// @[ZstdMatchFinder.scala:48:7]\n input reset,\t// @[ZstdMatchFinder.scala:48:7]\n input io_l2io_memloader_userif_req_ready,\t// @[ZstdMatchFinder.scala:49:14]\n output io_l2io_memloader_userif_req_valid,\t// @[ZstdMatchFinder.scala:49:14]\n output [70:0] io_l2io_memloader_userif_req_bits_addr,\t// @[ZstdMatchFinder.scala:49:14]\n output io_l2io_memloader_userif_resp_ready,\t// @[ZstdMatchFinder.scala:49:14]\n input io_l2io_memloader_userif_resp_valid,\t// @[ZstdMatchFinder.scala:49:14]\n input [255:0] io_l2io_memloader_userif_resp_bits_data,\t// @[ZstdMatchFinder.scala:49:14]\n input io_l2io_memloader_userif_no_memops_inflight,\t// @[ZstdMatchFinder.scala:49:14]\n input io_l2io_lit_memwriter_userif_req_ready,\t// @[ZstdMatchFinder.scala:49:14]\n output io_l2io_lit_memwriter_userif_req_valid,\t// @[ZstdMatchFinder.scala:49:14]\n output [63:0] io_l2io_lit_memwriter_userif_req_bits_addr,\t// @[ZstdMatchFinder.scala:49:14]\n output [2:0] io_l2io_lit_memwriter_userif_req_bits_size,\t// @[ZstdMatchFinder.scala:49:14]\n output [255:0] io_l2io_lit_memwriter_userif_req_bits_data,\t// @[ZstdMatchFinder.scala:49:14]\n input io_l2io_lit_memwriter_userif_resp_valid,\t// @[ZstdMatchFinder.scala:49:14]\n input [255:0] io_l2io_lit_memwriter_userif_resp_bits_data,\t// @[ZstdMatchFinder.scala:49:14]\n input io_l2io_lit_memwriter_userif_no_memops_inflight,\t// @[ZstdMatchFinder.scala:49:14]\n input io_l2io_seq_memwriter_userif_req_ready,\t// @[ZstdMatchFinder.scala:49:14]\n output io_l2io_seq_memwriter_userif_req_valid,\t// @[ZstdMatchFinder.scala:49:14]\n output [63:0] io_l2io_seq_memwriter_userif_req_bits_addr,\t// @[ZstdMatchFinder.scala:49:14]\n output [2:0] io_l2io_seq_memwriter_userif_req_bits_size,\t// @[ZstdMatchFinder.scala:49:14]\n output [255:0] io_l2io_seq_memwriter_userif_req_bits_data,\t// @[ZstdMatchFinder.scala:49:14]\n input io_l2io_seq_memwriter_userif_resp_valid,\t// @[ZstdMatchFinder.scala:49:14]\n input [255:0] io_l2io_seq_memwriter_userif_resp_bits_data,\t// @[ZstdMatchFinder.scala:49:14]\n input io_l2io_seq_memwriter_userif_no_memops_inflight,\t// @[ZstdMatchFinder.scala:49:14]\n output io_src_compress_src_info_ready,\t// @[ZstdMatchFinder.scala:49:14]\n input io_src_compress_src_info_valid,\t// @[ZstdMatchFinder.scala:49:14]\n input [63:0] io_src_compress_src_info_bits_ip,\t// @[ZstdMatchFinder.scala:49:14]\n input [63:0] io_src_compress_src_info_bits_isize,\t// @[ZstdMatchFinder.scala:49:14]\n output io_src_compress_src_info2_ready,\t// @[ZstdMatchFinder.scala:49:14]\n input io_src_compress_src_info2_valid,\t// @[ZstdMatchFinder.scala:49:14]\n input [63:0] io_src_compress_src_info2_bits_ip,\t// @[ZstdMatchFinder.scala:49:14]\n input [63:0] io_src_compress_src_info2_bits_isize,\t// @[ZstdMatchFinder.scala:49:14]\n output io_dst_lit_dst_info_ready,\t// @[ZstdMatchFinder.scala:49:14]\n input io_dst_lit_dst_info_valid,\t// @[ZstdMatchFinder.scala:49:14]\n input [63:0] io_dst_lit_dst_info_bits_op,\t// @[ZstdMatchFinder.scala:49:14]\n input [63:0] io_dst_lit_dst_info_bits_cmpflag,\t// @[ZstdMatchFinder.scala:49:14]\n output io_dst_seq_dst_info_ready,\t// @[ZstdMatchFinder.scala:49:14]\n input io_dst_seq_dst_info_valid,\t// @[ZstdMatchFinder.scala:49:14]\n input [63:0] io_dst_seq_dst_info_bits_op,\t// @[ZstdMatchFinder.scala:49:14]\n input [63:0] io_dst_seq_dst_info_bits_cmpflag,\t// @[ZstdMatchFinder.scala:49:14]\n input io_buff_consumed_lit_consumed_bytes_ready,\t// @[ZstdMatchFinder.scala:49:14]\n output io_buff_consumed_lit_consumed_bytes_valid,\t// @[ZstdMatchFinder.scala:49:14]\n output [63:0] io_buff_consumed_lit_consumed_bytes_bits,\t// @[ZstdMatchFinder.scala:49:14]\n input io_buff_consumed_seq_consumed_bytes_ready,\t// @[ZstdMatchFinder.scala:49:14]\n output io_buff_consumed_seq_consumed_bytes_valid,\t// @[ZstdMatchFinder.scala:49:14]\n output [63:0] io_buff_consumed_seq_consumed_bytes_bits,\t// @[ZstdMatchFinder.scala:49:14]\n input [63:0] io_MAX_OFFSET_ALLOWED,\t// @[ZstdMatchFinder.scala:49:14]\n input [4:0] io_RUNTIME_HT_NUM_ENTRIES_LOG2,\t// @[ZstdMatchFinder.scala:49:14]\n input io_ALGORITHM\t// @[ZstdMatchFinder.scala:49:14]\n);\n\n wire _lit_memwriter_io_memwrites_in_ready;\t// @[ZstdMatchFinder.scala:157:31]\n wire _seq_memwriter_io_memwrites_in_ready;\t// @[ZstdMatchFinder.scala:151:31]\n wire _zstd_litlen_injector_io_memwrites_in_ready;\t// @[ZstdMatchFinder.scala:148:38]\n wire _zstd_litlen_injector_io_seq_memwrites_out_valid;\t// @[ZstdMatchFinder.scala:148:38]\n wire [255:0] _zstd_litlen_injector_io_seq_memwrites_out_bits_data;\t// @[ZstdMatchFinder.scala:148:38]\n wire [5:0] _zstd_litlen_injector_io_seq_memwrites_out_bits_validbytes;\t// @[ZstdMatchFinder.scala:148:38]\n wire _zstd_litlen_injector_io_seq_memwrites_out_bits_end_of_message;\t// @[ZstdMatchFinder.scala:148:38]\n wire _zstd_litlen_injector_io_seq_memwrites_out_bits_is_copy;\t// @[ZstdMatchFinder.scala:148:38]\n wire _zstd_litlen_injector_io_seq_memwrites_out_bits_length_header;\t// @[ZstdMatchFinder.scala:148:38]\n wire _zstd_litlen_injector_io_seq_memwrites_out_bits_is_dummy;\t// @[ZstdMatchFinder.scala:148:38]\n wire _zstd_litlen_injector_io_lit_memwrites_out_valid;\t// @[ZstdMatchFinder.scala:148:38]\n wire [255:0] _zstd_litlen_injector_io_lit_memwrites_out_bits_data;\t// @[ZstdMatchFinder.scala:148:38]\n wire [5:0] _zstd_litlen_injector_io_lit_memwrites_out_bits_validbytes;\t// @[ZstdMatchFinder.scala:148:38]\n wire _zstd_litlen_injector_io_lit_memwrites_out_bits_end_of_message;\t// @[ZstdMatchFinder.scala:148:38]\n wire _zstd_litlen_injector_io_lit_memwrites_out_bits_is_copy;\t// @[ZstdMatchFinder.scala:148:38]\n wire _zstd_litlen_injector_io_lit_memwrites_out_bits_length_header;\t// @[ZstdMatchFinder.scala:148:38]\n wire _zstd_litlen_injector_io_lit_memwrites_out_bits_is_dummy;\t// @[ZstdMatchFinder.scala:148:38]\n wire [5:0] _lz77hashmatcher_io_memloader_in_user_consumed_bytes;\t// @[ZstdMatchFinder.scala:87:31]\n wire _lz77hashmatcher_io_memloader_in_output_ready;\t// @[ZstdMatchFinder.scala:87:31]\n wire _lz77hashmatcher_io_memwrites_out_valid;\t// @[ZstdMatchFinder.scala:87:31]\n wire [255:0] _lz77hashmatcher_io_memwrites_out_bits_data;\t// @[ZstdMatchFinder.scala:87:31]\n wire [5:0] _lz77hashmatcher_io_memwrites_out_bits_validbytes;\t// @[ZstdMatchFinder.scala:87:31]\n wire _lz77hashmatcher_io_memwrites_out_bits_end_of_message;\t// @[ZstdMatchFinder.scala:87:31]\n wire _lz77hashmatcher_io_memwrites_out_bits_is_copy;\t// @[ZstdMatchFinder.scala:87:31]\n wire _lz77hashmatcher_io_memwrites_out_bits_length_header;\t// @[ZstdMatchFinder.scala:87:31]\n wire [5:0] _memloader_io_consumer_available_output_bytes;\t// @[ZstdMatchFinder.scala:81:25]\n wire _memloader_io_consumer_output_valid;\t// @[ZstdMatchFinder.scala:81:25]\n wire [255:0] _memloader_io_consumer_output_data;\t// @[ZstdMatchFinder.scala:81:25]\n wire _memloader_io_consumer_output_last_chunk;\t// @[ZstdMatchFinder.scala:81:25]\n wire _memloader_io_optional_hbsram_write_valid;\t// @[ZstdMatchFinder.scala:81:25]\n wire [255:0] _memloader_io_optional_hbsram_write_bits_data;\t// @[ZstdMatchFinder.scala:81:25]\n wire [5:0] _memloader_io_optional_hbsram_write_bits_valid_bytes;\t// @[ZstdMatchFinder.scala:81:25]\n wire io_l2io_memloader_userif_req_ready_0 = io_l2io_memloader_userif_req_ready;\t// @[ZstdMatchFinder.scala:48:7]\n wire io_l2io_memloader_userif_resp_valid_0 = io_l2io_memloader_userif_resp_valid;\t// @[ZstdMatchFinder.scala:48:7]\n wire [255:0] io_l2io_memloader_userif_resp_bits_data_0 = io_l2io_memloader_userif_resp_bits_data;\t// @[ZstdMatchFinder.scala:48:7]\n wire io_l2io_memloader_userif_no_memops_inflight_0 = io_l2io_memloader_userif_no_memops_inflight;\t// @[ZstdMatchFinder.scala:48:7]\n wire io_l2io_lit_memwriter_userif_req_ready_0 = io_l2io_lit_memwriter_userif_req_ready;\t// @[ZstdMatchFinder.scala:48:7]\n wire io_l2io_lit_memwriter_userif_resp_valid_0 = io_l2io_lit_memwriter_userif_resp_valid;\t// @[ZstdMatchFinder.scala:48:7]\n wire [255:0] io_l2io_lit_memwriter_userif_resp_bits_data_0 = io_l2io_lit_memwriter_userif_resp_bits_data;\t// @[ZstdMatchFinder.scala:48:7]\n wire io_l2io_lit_memwriter_userif_no_memops_inflight_0 = io_l2io_lit_memwriter_userif_no_memops_inflight;\t// @[ZstdMatchFinder.scala:48:7]\n wire io_l2io_seq_memwriter_userif_req_ready_0 = io_l2io_seq_memwriter_userif_req_ready;\t// @[ZstdMatchFinder.scala:48:7]\n wire io_l2io_seq_memwriter_userif_resp_valid_0 = io_l2io_seq_memwriter_userif_resp_valid;\t// @[ZstdMatchFinder.scala:48:7]\n wire [255:0] io_l2io_seq_memwriter_userif_resp_bits_data_0 = io_l2io_seq_memwriter_userif_resp_bits_data;\t// @[ZstdMatchFinder.scala:48:7]\n wire io_l2io_seq_memwriter_userif_no_memops_inflight_0 = io_l2io_seq_memwriter_userif_no_memops_inflight;\t// @[ZstdMatchFinder.scala:48:7]\n wire io_src_compress_src_info_valid_0 = io_src_compress_src_info_valid;\t// @[ZstdMatchFinder.scala:48:7]\n wire [63:0] io_src_compress_src_info_bits_ip_0 = io_src_compress_src_info_bits_ip;\t// @[ZstdMatchFinder.scala:48:7]\n wire [63:0] io_src_compress_src_info_bits_isize_0 = io_src_compress_src_info_bits_isize;\t// @[ZstdMatchFinder.scala:48:7]\n wire io_src_compress_src_info2_valid_0 = io_src_compress_src_info2_valid;\t// @[ZstdMatchFinder.scala:48:7]\n wire [63:0] io_src_compress_src_info2_bits_ip_0 = io_src_compress_src_info2_bits_ip;\t// @[ZstdMatchFinder.scala:48:7]\n wire [63:0] io_src_compress_src_info2_bits_isize_0 = io_src_compress_src_info2_bits_isize;\t// @[ZstdMatchFinder.scala:48:7]\n wire io_dst_lit_dst_info_valid_0 = io_dst_lit_dst_info_valid;\t// @[ZstdMatchFinder.scala:48:7]\n wire [63:0] io_dst_lit_dst_info_bits_op_0 = io_dst_lit_dst_info_bits_op;\t// @[ZstdMatchFinder.scala:48:7]\n wire [63:0] io_dst_lit_dst_info_bits_cmpflag_0 = io_dst_lit_dst_info_bits_cmpflag;\t// @[ZstdMatchFinder.scala:48:7]\n wire io_dst_seq_dst_info_valid_0 = io_dst_seq_dst_info_valid;\t// @[ZstdMatchFinder.scala:48:7]\n wire [63:0] io_dst_seq_dst_info_bits_op_0 = io_dst_seq_dst_info_bits_op;\t// @[ZstdMatchFinder.scala:48:7]\n wire [63:0] io_dst_seq_dst_info_bits_cmpflag_0 = io_dst_seq_dst_info_bits_cmpflag;\t// @[ZstdMatchFinder.scala:48:7]\n wire io_buff_consumed_lit_consumed_bytes_ready_0 = io_buff_consumed_lit_consumed_bytes_ready;\t// @[ZstdMatchFinder.scala:48:7]\n wire io_buff_consumed_seq_consumed_bytes_ready_0 = io_buff_consumed_seq_consumed_bytes_ready;\t// @[ZstdMatchFinder.scala:48:7]\n wire [63:0] io_MAX_OFFSET_ALLOWED_0 = io_MAX_OFFSET_ALLOWED;\t// @[ZstdMatchFinder.scala:48:7]\n wire [4:0] io_RUNTIME_HT_NUM_ENTRIES_LOG2_0 = io_RUNTIME_HT_NUM_ENTRIES_LOG2;\t// @[ZstdMatchFinder.scala:48:7]\n wire io_ALGORITHM_0 = io_ALGORITHM;\t// @[ZstdMatchFinder.scala:48:7]\n wire [2:0] io_l2io_memloader_userif_req_bits_size = 3'h5;\t// @[ZstdMatchFinder.scala:48:7]\n wire [255:0] io_l2io_memloader_userif_req_bits_data = 256'h0;\t// @[ZstdMatchFinder.scala:48:7]\n wire io_l2io_memloader_userif_req_bits_cmd = 1'h0;\t// @[ZstdMatchFinder.scala:48:7]\n wire io_l2io_lit_memwriter_userif_req_bits_cmd = 1'h1;\t// @[ZstdMatchFinder.scala:48:7]\n wire io_l2io_lit_memwriter_userif_resp_ready = 1'h1;\t// @[ZstdMatchFinder.scala:48:7]\n wire io_l2io_seq_memwriter_userif_req_bits_cmd = 1'h1;\t// @[ZstdMatchFinder.scala:48:7]\n wire io_l2io_seq_memwriter_userif_resp_ready = 1'h1;\t// @[ZstdMatchFinder.scala:48:7]\n wire [70:0] io_l2io_memloader_userif_req_bits_addr_0;\t// @[ZstdMatchFinder.scala:48:7]\n wire io_l2io_memloader_userif_req_valid_0;\t// @[ZstdMatchFinder.scala:48:7]\n wire io_l2io_memloader_userif_resp_ready_0;\t// @[ZstdMatchFinder.scala:48:7]\n wire [63:0] io_l2io_lit_memwriter_userif_req_bits_addr_0;\t// @[ZstdMatchFinder.scala:48:7]\n wire [2:0] io_l2io_lit_memwriter_userif_req_bits_size_0;\t// @[ZstdMatchFinder.scala:48:7]\n wire [255:0] io_l2io_lit_memwriter_userif_req_bits_data_0;\t// @[ZstdMatchFinder.scala:48:7]\n wire io_l2io_lit_memwriter_userif_req_valid_0;\t// @[ZstdMatchFinder.scala:48:7]\n wire [63:0] io_l2io_seq_memwriter_userif_req_bits_addr_0;\t// @[ZstdMatchFinder.scala:48:7]\n wire [2:0] io_l2io_seq_memwriter_userif_req_bits_size_0;\t// @[ZstdMatchFinder.scala:48:7]\n wire [255:0] io_l2io_seq_memwriter_userif_req_bits_data_0;\t// @[ZstdMatchFinder.scala:48:7]\n wire io_l2io_seq_memwriter_userif_req_valid_0;\t// @[ZstdMatchFinder.scala:48:7]\n wire io_src_compress_src_info_ready_0;\t// @[ZstdMatchFinder.scala:48:7]\n wire io_src_compress_src_info2_ready_0;\t// @[ZstdMatchFinder.scala:48:7]\n wire io_dst_lit_dst_info_ready_0;\t// @[ZstdMatchFinder.scala:48:7]\n wire io_dst_seq_dst_info_ready_0;\t// @[ZstdMatchFinder.scala:48:7]\n wire io_buff_consumed_lit_consumed_bytes_valid_0;\t// @[ZstdMatchFinder.scala:48:7]\n wire [63:0] io_buff_consumed_lit_consumed_bytes_bits_0;\t// @[ZstdMatchFinder.scala:48:7]\n wire io_buff_consumed_seq_consumed_bytes_valid_0;\t// @[ZstdMatchFinder.scala:48:7]\n wire [63:0] io_buff_consumed_seq_consumed_bytes_bits_0;\t// @[ZstdMatchFinder.scala:48:7]\n reg [63:0] loginfo_cycles;\t// @[Util.scala:18:33]\n wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1;\t// @[Util.scala:18:33, :19:38]\n wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0];\t// @[Util.scala:19:38]\n reg [63:0] loginfo_cycles_1;\t// @[Util.scala:18:33]\n wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1;\t// @[Util.scala:18:33, :19:38]\n wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0];\t// @[Util.scala:19:38]\n reg [63:0] loginfo_cycles_2;\t// @[Util.scala:18:33]\n wire [64:0] _loginfo_cycles_T_4 = {1'h0, loginfo_cycles_2} + 65'h1;\t// @[Util.scala:18:33, :19:38]\n wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0];\t// @[Util.scala:19:38]\n reg [63:0] loginfo_cycles_3;\t// @[Util.scala:18:33]\n wire [64:0] _loginfo_cycles_T_6 = {1'h0, loginfo_cycles_3} + 65'h1;\t// @[Util.scala:18:33, :19:38]\n wire [63:0] _loginfo_cycles_T_7 = _loginfo_cycles_T_6[63:0];\t// @[Util.scala:19:38]\n reg [63:0] loginfo_cycles_4;\t// @[Util.scala:18:33]\n wire [64:0] _loginfo_cycles_T_8 = {1'h0, loginfo_cycles_4} + 65'h1;\t// @[Util.scala:18:33, :19:38]\n wire [63:0] _loginfo_cycles_T_9 = _loginfo_cycles_T_8[63:0];\t// @[Util.scala:19:38]\n reg [63:0] loginfo_cycles_5;\t// @[Util.scala:18:33]\n wire [64:0] _loginfo_cycles_T_10 = {1'h0, loginfo_cycles_5} + 65'h1;\t// @[Util.scala:18:33, :19:38]\n wire [63:0] _loginfo_cycles_T_11 = _loginfo_cycles_T_10[63:0];\t// @[Util.scala:19:38]\n reg [63:0] loginfo_cycles_6;\t// @[Util.scala:18:33]\n wire [64:0] _loginfo_cycles_T_12 = {1'h0, loginfo_cycles_6} + 65'h1;\t// @[Util.scala:18:33, :19:38]\n wire [63:0] _loginfo_cycles_T_13 = _loginfo_cycles_T_12[63:0];\t// @[Util.scala:19:38]\n reg [63:0] loginfo_cycles_7;\t// @[Util.scala:18:33]\n wire [64:0] _loginfo_cycles_T_14 = {1'h0, loginfo_cycles_7} + 65'h1;\t// @[Util.scala:18:33, :19:38]\n wire [63:0] _loginfo_cycles_T_15 = _loginfo_cycles_T_14[63:0];\t// @[Util.scala:19:38]\n reg [63:0] loginfo_cycles_8;\t// @[Util.scala:18:33]\n wire [64:0] _loginfo_cycles_T_16 = {1'h0, loginfo_cycles_8} + 65'h1;\t// @[Util.scala:18:33, :19:38]\n wire [63:0] _loginfo_cycles_T_17 = _loginfo_cycles_T_16[63:0];\t// @[Util.scala:19:38]\n reg [63:0] loginfo_cycles_9;\t// @[Util.scala:18:33]\n wire [64:0] _loginfo_cycles_T_18 = {1'h0, loginfo_cycles_9} + 65'h1;\t// @[Util.scala:18:33, :19:38]\n wire [63:0] _loginfo_cycles_T_19 = _loginfo_cycles_T_18[63:0];\t// @[Util.scala:19:38]\n reg [63:0] loginfo_cycles_10;\t// @[Util.scala:18:33]\n wire [64:0] _loginfo_cycles_T_20 = {1'h0, loginfo_cycles_10} + 65'h1;\t// @[Util.scala:18:33, :19:38]\n wire [63:0] _loginfo_cycles_T_21 = _loginfo_cycles_T_20[63:0];\t// @[Util.scala:19:38]\n reg [63:0] loginfo_cycles_11;\t// @[Util.scala:18:33]\n wire [64:0] _loginfo_cycles_T_22 = {1'h0, loginfo_cycles_11} + 65'h1;\t// @[Util.scala:18:33, :19:38]\n wire [63:0] _loginfo_cycles_T_23 = _loginfo_cycles_T_22[63:0];\t// @[Util.scala:19:38]"}}},{"rowIdx":34389,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module TLAtomicAutomata_cbus : \n input clock : Clock \n input reset : Reset \n output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} \n\n\n wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} \n invalidate nodeIn.d.bits.corrupt \n invalidate nodeIn.d.bits.data \n invalidate nodeIn.d.bits.denied \n invalidate nodeIn.d.bits.sink \n invalidate nodeIn.d.bits.source \n invalidate nodeIn.d.bits.size \n invalidate nodeIn.d.bits.param \n invalidate nodeIn.d.bits.opcode \n invalidate nodeIn.d.valid \n invalidate nodeIn.d.ready \n invalidate nodeIn.a.bits.corrupt \n invalidate nodeIn.a.bits.data \n invalidate nodeIn.a.bits.mask \n invalidate nodeIn.a.bits.address \n invalidate nodeIn.a.bits.source \n invalidate nodeIn.a.bits.size \n invalidate nodeIn.a.bits.param \n invalidate nodeIn.a.bits.opcode \n invalidate nodeIn.a.valid \n invalidate nodeIn.a.ready \n inst monitor of TLMonitor_18 \n connect monitor.clock, clock\n\n connect monitor.reset, reset\n\n connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt \n connect monitor.io.in.d.bits.data, nodeIn.d.bits.data \n connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied \n connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink \n connect monitor.io.in.d.bits.source, nodeIn.d.bits.source \n connect monitor.io.in.d.bits.size, nodeIn.d.bits.size \n connect monitor.io.in.d.bits.param, nodeIn.d.bits.param \n connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode \n connect monitor.io.in.d.valid, nodeIn.d.valid \n connect monitor.io.in.d.ready, nodeIn.d.ready \n connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt \n connect monitor.io.in.a.bits.data, nodeIn.a.bits.data \n connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask \n connect monitor.io.in.a.bits.address, nodeIn.a.bits.address \n connect monitor.io.in.a.bits.source, nodeIn.a.bits.source \n connect monitor.io.in.a.bits.size, nodeIn.a.bits.size \n connect monitor.io.in.a.bits.param, nodeIn.a.bits.param \n connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode \n connect monitor.io.in.a.valid, nodeIn.a.valid \n connect monitor.io.in.a.ready, nodeIn.a.ready \n wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} \n invalidate nodeOut.d.bits.corrupt \n invalidate nodeOut.d.bits.data \n invalidate nodeOut.d.bits.denied \n invalidate nodeOut.d.bits.sink \n invalidate nodeOut.d.bits.source \n invalidate nodeOut.d.bits.size \n invalidate nodeOut.d.bits.param \n invalidate nodeOut.d.bits.opcode \n invalidate nodeOut.d.valid \n invalidate nodeOut.d.ready \n invalidate nodeOut.a.bits.corrupt \n invalidate nodeOut.a.bits.data \n invalidate nodeOut.a.bits.mask \n invalidate nodeOut.a.bits.address \n invalidate nodeOut.a.bits.source \n invalidate nodeOut.a.bits.size \n invalidate nodeOut.a.bits.param \n invalidate nodeOut.a.bits.opcode \n invalidate nodeOut.a.valid \n invalidate nodeOut.a.ready \n connect auto.out, nodeOut \n connect nodeIn, auto.in \n wire initval : { state : UInt<2>} \n connect initval.state, UInt<1>(0h0) \n wire _cam_s_WIRE : { state : UInt<2>}[1] \n connect _cam_s_WIRE[0], initval \n regreset cam_s : { state : UInt<2>}[1], clock, reset, _cam_s_WIRE \n reg cam_a : { bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, fifoId : UInt<1>, lut : UInt<4>}[1], clock \n reg cam_d : { data : UInt<64>, denied : UInt<1>, corrupt : UInt<1>}[1], clock \n node cam_free_0 = eq(cam_s[0].state, UInt<1>(0h0)) \n node cam_amo_0 = eq(cam_s[0].state, UInt<2>(0h2)) \n node _cam_abusy_T = eq(cam_s[0].state, UInt<2>(0h3)) \n node _cam_abusy_T_1 = eq(cam_s[0].state, UInt<2>(0h2)) \n node cam_abusy_0 = or(_cam_abusy_T, _cam_abusy_T_1) \n node cam_dmatch_0 = neq(cam_s[0].state, UInt<1>(0h0)) \n node _a_canLogical_T = leq(UInt<1>(0h0), nodeIn.a.bits.size) \n node _a_canLogical_T_1 = leq(nodeIn.a.bits.size, UInt<2>(0h3)) \n node _a_canLogical_T_2 = and(_a_canLogical_T, _a_canLogical_T_1) \n node _a_canLogical_T_3 = or(UInt<1>(0h0), _a_canLogical_T_2) \n node _a_canLogical_T_4 = xor(nodeIn.a.bits.address, UInt<13>(0h1000)) \n node _a_canLogical_T_5 = cvt(_a_canLogical_T_4) \n node _a_canLogical_T_6 = and(_a_canLogical_T_5, asSInt(UInt<33>(0h9a111000))) \n node _a_canLogical_T_7 = asSInt(_a_canLogical_T_6) \n node _a_canLogical_T_8 = eq(_a_canLogical_T_7, asSInt(UInt<1>(0h0))) \n node _a_canLogical_T_9 = xor(nodeIn.a.bits.address, UInt<29>(0h10000000)) \n node _a_canLogical_T_10 = cvt(_a_canLogical_T_9) \n node _a_canLogical_T_11 = and(_a_canLogical_T_10, asSInt(UInt<33>(0h9a111000))) \n node _a_canLogical_T_12 = asSInt(_a_canLogical_T_11) \n node _a_canLogical_T_13 = eq(_a_canLogical_T_12, asSInt(UInt<1>(0h0))) \n node _a_canLogical_T_14 = or(_a_canLogical_T_8, _a_canLogical_T_13) \n node _a_canLogical_T_15 = and(_a_canLogical_T_3, _a_canLogical_T_14) \n node _a_canLogical_T_16 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _a_canLogical_T_17 = xor(nodeIn.a.bits.address, UInt<1>(0h0)) \n node _a_canLogical_T_18 = cvt(_a_canLogical_T_17) \n node _a_canLogical_T_19 = and(_a_canLogical_T_18, asSInt(UInt<33>(0h9a111000))) \n node _a_canLogical_T_20 = asSInt(_a_canLogical_T_19) \n node _a_canLogical_T_21 = eq(_a_canLogical_T_20, asSInt(UInt<1>(0h0))) \n node _a_canLogical_T_22 = xor(nodeIn.a.bits.address, UInt<17>(0h10000)) \n node _a_canLogical_T_23 = cvt(_a_canLogical_T_22) \n node _a_canLogical_T_24 = and(_a_canLogical_T_23, asSInt(UInt<33>(0h9a110000))) \n node _a_canLogical_T_25 = asSInt(_a_canLogical_T_24) \n node _a_canLogical_T_26 = eq(_a_canLogical_T_25, asSInt(UInt<1>(0h0))) \n node _a_canLogical_T_27 = xor(nodeIn.a.bits.address, UInt<21>(0h100000)) \n node _a_canLogical_T_28 = cvt(_a_canLogical_T_27) \n node _a_canLogical_T_29 = and(_a_canLogical_T_28, asSInt(UInt<33>(0h9a101000))) \n node _a_canLogical_T_30 = asSInt(_a_canLogical_T_29) \n node _a_canLogical_T_31 = eq(_a_canLogical_T_30, asSInt(UInt<1>(0h0))) \n node _a_canLogical_T_32 = xor(nodeIn.a.bits.address, UInt<26>(0h2000000)) \n node _a_canLogical_T_33 = cvt(_a_canLogical_T_32) \n node _a_canLogical_T_34 = and(_a_canLogical_T_33, asSInt(UInt<33>(0h9a110000))) \n node _a_canLogical_T_35 = asSInt(_a_canLogical_T_34) \n node _a_canLogical_T_36 = eq(_a_canLogical_T_35, asSInt(UInt<1>(0h0))) \n node _a_canLogical_T_37 = xor(nodeIn.a.bits.address, UInt<28>(0h8000000)) \n node _a_canLogical_T_38 = cvt(_a_canLogical_T_37) \n node _a_canLogical_T_39 = and(_a_canLogical_T_38, asSInt(UInt<33>(0h98000000))) \n node _a_canLogical_T_40 = asSInt(_a_canLogical_T_39) \n node _a_canLogical_T_41 = eq(_a_canLogical_T_40, asSInt(UInt<1>(0h0))) \n node _a_canLogical_T_42 = or(_a_canLogical_T_21, _a_canLogical_T_26) \n node _a_canLogical_T_43 = or(_a_canLogical_T_42, _a_canLogical_T_31) \n node _a_canLogical_T_44 = or(_a_canLogical_T_43, _a_canLogical_T_36) \n node _a_canLogical_T_45 = or(_a_canLogical_T_44, _a_canLogical_T_41) \n node _a_canLogical_T_46 = and(_a_canLogical_T_16, _a_canLogical_T_45) \n node _a_canLogical_T_47 = eq(UInt<2>(0h2), nodeIn.a.bits.size) \n node _a_canLogical_T_48 = or(UInt<1>(0h0), _a_canLogical_T_47) \n node _a_canLogical_T_49 = xor(nodeIn.a.bits.address, UInt<32>(0h80000000)) \n node _a_canLogical_T_50 = cvt(_a_canLogical_T_49) \n node _a_canLogical_T_51 = and(_a_canLogical_T_50, asSInt(UInt<33>(0h9a110000))) \n node _a_canLogical_T_52 = asSInt(_a_canLogical_T_51) \n node _a_canLogical_T_53 = eq(_a_canLogical_T_52, asSInt(UInt<1>(0h0))) \n node _a_canLogical_T_54 = and(_a_canLogical_T_48, _a_canLogical_T_53) \n node _a_canLogical_T_55 = or(UInt<1>(0h0), _a_canLogical_T_15) \n node _a_canLogical_T_56 = or(_a_canLogical_T_55, _a_canLogical_T_46) \n node _a_canLogical_T_57 = or(_a_canLogical_T_56, _a_canLogical_T_54) \n node a_canLogical = and(UInt<1>(0h1), _a_canLogical_T_57) \n node _a_canArithmetic_T = leq(UInt<1>(0h0), nodeIn.a.bits.size) \n node _a_canArithmetic_T_1 = leq(nodeIn.a.bits.size, UInt<2>(0h3)) \n node _a_canArithmetic_T_2 = and(_a_canArithmetic_T, _a_canArithmetic_T_1) \n node _a_canArithmetic_T_3 = or(UInt<1>(0h0), _a_canArithmetic_T_2) \n node _a_canArithmetic_T_4 = xor(nodeIn.a.bits.address, UInt<13>(0h1000)) \n node _a_canArithmetic_T_5 = cvt(_a_canArithmetic_T_4) \n node _a_canArithmetic_T_6 = and(_a_canArithmetic_T_5, asSInt(UInt<33>(0h9a111000))) \n node _a_canArithmetic_T_7 = asSInt(_a_canArithmetic_T_6) \n node _a_canArithmetic_T_8 = eq(_a_canArithmetic_T_7, asSInt(UInt<1>(0h0))) \n node _a_canArithmetic_T_9 = xor(nodeIn.a.bits.address, UInt<29>(0h10000000)) \n node _a_canArithmetic_T_10 = cvt(_a_canArithmetic_T_9) \n node _a_canArithmetic_T_11 = and(_a_canArithmetic_T_10, asSInt(UInt<33>(0h9a111000))) \n node _a_canArithmetic_T_12 = asSInt(_a_canArithmetic_T_11) \n node _a_canArithmetic_T_13 = eq(_a_canArithmetic_T_12, asSInt(UInt<1>(0h0))) \n node _a_canArithmetic_T_14 = or(_a_canArithmetic_T_8, _a_canArithmetic_T_13) \n node _a_canArithmetic_T_15 = and(_a_canArithmetic_T_3, _a_canArithmetic_T_14) \n node _a_canArithmetic_T_16 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _a_canArithmetic_T_17 = xor(nodeIn.a.bits.address, UInt<1>(0h0)) \n node _a_canArithmetic_T_18 = cvt(_a_canArithmetic_T_17) \n node _a_canArithmetic_T_19 = and(_a_canArithmetic_T_18, asSInt(UInt<33>(0h9a111000))) \n node _a_canArithmetic_T_20 = asSInt(_a_canArithmetic_T_19) \n node _a_canArithmetic_T_21 = eq(_a_canArithmetic_T_20, asSInt(UInt<1>(0h0))) \n node _a_canArithmetic_T_22 = xor(nodeIn.a.bits.address, UInt<17>(0h10000)) \n node _a_canArithmetic_T_23 = cvt(_a_canArithmetic_T_22) \n node _a_canArithmetic_T_24 = and(_a_canArithmetic_T_23, asSInt(UInt<33>(0h9a110000))) \n node _a_canArithmetic_T_25 = asSInt(_a_canArithmetic_T_24) \n node _a_canArithmetic_T_26 = eq(_a_canArithmetic_T_25, asSInt(UInt<1>(0h0))) \n node _a_canArithmetic_T_27 = xor(nodeIn.a.bits.address, UInt<21>(0h100000)) \n node _a_canArithmetic_T_28 = cvt(_a_canArithmetic_T_27) \n node _a_canArithmetic_T_29 = and(_a_canArithmetic_T_28, asSInt(UInt<33>(0h9a101000))) \n node _a_canArithmetic_T_30 = asSInt(_a_canArithmetic_T_29) \n node _a_canArithmetic_T_31 = eq(_a_canArithmetic_T_30, asSInt(UInt<1>(0h0))) \n node _a_canArithmetic_T_32 = xor(nodeIn.a.bits.address, UInt<26>(0h2000000)) \n node _a_canArithmetic_T_33 = cvt(_a_canArithmetic_T_32) \n node _a_canArithmetic_T_34 = and(_a_canArithmetic_T_33, asSInt(UInt<33>(0h9a110000))) \n node _a_canArithmetic_T_35 = asSInt(_a_canArithmetic_T_34) \n node _a_canArithmetic_T_36 = eq(_a_canArithmetic_T_35, asSInt(UInt<1>(0h0))) \n node _a_canArithmetic_T_37 = xor(nodeIn.a.bits.address, UInt<28>(0h8000000)) \n node _a_canArithmetic_T_38 = cvt(_a_canArithmetic_T_37) \n node _a_canArithmetic_T_39 = and(_a_canArithmetic_T_38, asSInt(UInt<33>(0h98000000))) \n node _a_canArithmetic_T_40 = asSInt(_a_canArithmetic_T_39) \n node _a_canArithmetic_T_41 = eq(_a_canArithmetic_T_40, asSInt(UInt<1>(0h0))) \n node _a_canArithmetic_T_42 = or(_a_canArithmetic_T_21, _a_canArithmetic_T_26) \n node _a_canArithmetic_T_43 = or(_a_canArithmetic_T_42, _a_canArithmetic_T_31) \n node _a_canArithmetic_T_44 = or(_a_canArithmetic_T_43, _a_canArithmetic_T_36) \n node _a_canArithmetic_T_45 = or(_a_canArithmetic_T_44, _a_canArithmetic_T_41) \n node _a_canArithmetic_T_46 = and(_a_canArithmetic_T_16, _a_canArithmetic_T_45) \n node _a_canArithmetic_T_47 = eq(UInt<2>(0h2), nodeIn.a.bits.size) \n node _a_canArithmetic_T_48 = or(UInt<1>(0h0), _a_canArithmetic_T_47) \n node _a_canArithmetic_T_49 = xor(nodeIn.a.bits.address, UInt<32>(0h80000000)) \n node _a_canArithmetic_T_50 = cvt(_a_canArithmetic_T_49) \n node _a_canArithmetic_T_51 = and(_a_canArithmetic_T_50, asSInt(UInt<33>(0h9a110000))) \n node _a_canArithmetic_T_52 = asSInt(_a_canArithmetic_T_51) \n node _a_canArithmetic_T_53 = eq(_a_canArithmetic_T_52, asSInt(UInt<1>(0h0))) \n node _a_canArithmetic_T_54 = and(_a_canArithmetic_T_48, _a_canArithmetic_T_53) \n node _a_canArithmetic_T_55 = or(UInt<1>(0h0), _a_canArithmetic_T_15) \n node _a_canArithmetic_T_56 = or(_a_canArithmetic_T_55, _a_canArithmetic_T_46) \n node _a_canArithmetic_T_57 = or(_a_canArithmetic_T_56, _a_canArithmetic_T_54) \n node a_canArithmetic = and(UInt<1>(0h1), _a_canArithmetic_T_57) \n node a_isLogical = eq(nodeIn.a.bits.opcode, UInt<2>(0h3)) \n node a_isArithmetic = eq(nodeIn.a.bits.opcode, UInt<2>(0h2)) \n node _a_isSupported_T = mux(a_isArithmetic, a_canArithmetic, UInt<1>(0h1)) \n node a_isSupported = mux(a_isLogical, a_canLogical, _a_isSupported_T) \n node _a_cam_por_put_T = or(UInt<1>(0h0), cam_amo_0) \n node _a_cam_sel_put_T = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node a_cam_sel_put_0 = and(cam_amo_0, _a_cam_sel_put_T) \n node _a_fifoId_T = xor(nodeIn.a.bits.address, UInt<1>(0h0)) \n node _a_fifoId_T_1 = cvt(_a_fifoId_T) \n node _a_fifoId_T_2 = and(_a_fifoId_T_1, asSInt(UInt<1>(0h0))) \n node _a_fifoId_T_3 = asSInt(_a_fifoId_T_2) \n node _a_fifoId_T_4 = eq(_a_fifoId_T_3, asSInt(UInt<1>(0h0))) \n node _a_cam_busy_T = eq(cam_a[0].fifoId, UInt<1>(0h0)) \n node a_cam_busy = and(cam_abusy_0, _a_cam_busy_T) \n node _a_cam_por_free_T = or(UInt<1>(0h0), cam_free_0) \n node _a_cam_sel_free_T = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node a_cam_sel_free_0 = and(cam_free_0, _a_cam_sel_free_T) \n node _indexes_T = bits(cam_a[0].bits.data, 0, 0) \n node _indexes_T_1 = bits(cam_d[0].data, 0, 0) \n node indexes_0 = cat(_indexes_T, _indexes_T_1) \n node _indexes_T_2 = bits(cam_a[0].bits.data, 1, 1) \n node _indexes_T_3 = bits(cam_d[0].data, 1, 1) \n node indexes_1 = cat(_indexes_T_2, _indexes_T_3) \n node _indexes_T_4 = bits(cam_a[0].bits.data, 2, 2) \n node _indexes_T_5 = bits(cam_d[0].data, 2, 2) \n node indexes_2 = cat(_indexes_T_4, _indexes_T_5) \n node _indexes_T_6 = bits(cam_a[0].bits.data, 3, 3) \n node _indexes_T_7 = bits(cam_d[0].data, 3, 3) \n node indexes_3 = cat(_indexes_T_6, _indexes_T_7) \n node _indexes_T_8 = bits(cam_a[0].bits.data, 4, 4) \n node _indexes_T_9 = bits(cam_d[0].data, 4, 4) \n node indexes_4 = cat(_indexes_T_8, _indexes_T_9) \n node _indexes_T_10 = bits(cam_a[0].bits.data, 5, 5) \n node _indexes_T_11 = bits(cam_d[0].data, 5, 5) \n node indexes_5 = cat(_indexes_T_10, _indexes_T_11) \n node _indexes_T_12 = bits(cam_a[0].bits.data, 6, 6) \n node _indexes_T_13 = bits(cam_d[0].data, 6, 6) \n node indexes_6 = cat(_indexes_T_12, _indexes_T_13) \n node _indexes_T_14 = bits(cam_a[0].bits.data, 7, 7) \n node _indexes_T_15 = bits(cam_d[0].data, 7, 7) \n node indexes_7 = cat(_indexes_T_14, _indexes_T_15) \n node _indexes_T_16 = bits(cam_a[0].bits.data, 8, 8) \n node _indexes_T_17 = bits(cam_d[0].data, 8, 8) \n node indexes_8 = cat(_indexes_T_16, _indexes_T_17) \n node _indexes_T_18 = bits(cam_a[0].bits.data, 9, 9) \n node _indexes_T_19 = bits(cam_d[0].data, 9, 9) \n node indexes_9 = cat(_indexes_T_18, _indexes_T_19) \n node _indexes_T_20 = bits(cam_a[0].bits.data, 10, 10) \n node _indexes_T_21 = bits(cam_d[0].data, 10, 10) \n node indexes_10 = cat(_indexes_T_20, _indexes_T_21) \n node _indexes_T_22 = bits(cam_a[0].bits.data, 11, 11) \n node _indexes_T_23 = bits(cam_d[0].data, 11, 11) \n node indexes_11 = cat(_indexes_T_22, _indexes_T_23) \n node _indexes_T_24 = bits(cam_a[0].bits.data, 12, 12) \n node _indexes_T_25 = bits(cam_d[0].data, 12, 12) \n node indexes_12 = cat(_indexes_T_24, _indexes_T_25) \n node _indexes_T_26 = bits(cam_a[0].bits.data, 13, 13) \n node _indexes_T_27 = bits(cam_d[0].data, 13, 13) \n node indexes_13 = cat(_indexes_T_26, _indexes_T_27) \n node _indexes_T_28 = bits(cam_a[0].bits.data, 14, 14) \n node _indexes_T_29 = bits(cam_d[0].data, 14, 14) \n node indexes_14 = cat(_indexes_T_28, _indexes_T_29) \n node _indexes_T_30 = bits(cam_a[0].bits.data, 15, 15) \n node _indexes_T_31 = bits(cam_d[0].data, 15, 15) \n node indexes_15 = cat(_indexes_T_30, _indexes_T_31) \n node _indexes_T_32 = bits(cam_a[0].bits.data, 16, 16) \n node _indexes_T_33 = bits(cam_d[0].data, 16, 16) \n node indexes_16 = cat(_indexes_T_32, _indexes_T_33) \n node _indexes_T_34 = bits(cam_a[0].bits.data, 17, 17) \n node _indexes_T_35 = bits(cam_d[0].data, 17, 17) \n node indexes_17 = cat(_indexes_T_34, _indexes_T_35) \n node _indexes_T_36 = bits(cam_a[0].bits.data, 18, 18) \n node _indexes_T_37 = bits(cam_d[0].data, 18, 18) \n node indexes_18 = cat(_indexes_T_36, _indexes_T_37) \n node _indexes_T_38 = bits(cam_a[0].bits.data, 19, 19) \n node _indexes_T_39 = bits(cam_d[0].data, 19, 19) \n node indexes_19 = cat(_indexes_T_38, _indexes_T_39) \n node _indexes_T_40 = bits(cam_a[0].bits.data, 20, 20) \n node _indexes_T_41 = bits(cam_d[0].data, 20, 20) \n node indexes_20 = cat(_indexes_T_40, _indexes_T_41) \n node _indexes_T_42 = bits(cam_a[0].bits.data, 21, 21) \n node _indexes_T_43 = bits(cam_d[0].data, 21, 21) \n node indexes_21 = cat(_indexes_T_42, _indexes_T_43) \n node _indexes_T_44 = bits(cam_a[0].bits.data, 22, 22) \n node _indexes_T_45 = bits(cam_d[0].data, 22, 22) \n node indexes_22 = cat(_indexes_T_44, _indexes_T_45) \n node _indexes_T_46 = bits(cam_a[0].bits.data, 23, 23) \n node _indexes_T_47 = bits(cam_d[0].data, 23, 23) \n node indexes_23 = cat(_indexes_T_46, _indexes_T_47) \n node _indexes_T_48 = bits(cam_a[0].bits.data, 24, 24) \n node _indexes_T_49 = bits(cam_d[0].data, 24, 24) \n node indexes_24 = cat(_indexes_T_48, _indexes_T_49) \n node _indexes_T_50 = bits(cam_a[0].bits.data, 25, 25) \n node _indexes_T_51 = bits(cam_d[0].data, 25, 25) \n node indexes_25 = cat(_indexes_T_50, _indexes_T_51) \n node _indexes_T_52 = bits(cam_a[0].bits.data, 26, 26) \n node _indexes_T_53 = bits(cam_d[0].data, 26, 26) \n node indexes_26 = cat(_indexes_T_52, _indexes_T_53) \n node _indexes_T_54 = bits(cam_a[0].bits.data, 27, 27) \n node _indexes_T_55 = bits(cam_d[0].data, 27, 27) \n node indexes_27 = cat(_indexes_T_54, _indexes_T_55) \n node _indexes_T_56 = bits(cam_a[0].bits.data, 28, 28) \n node _indexes_T_57 = bits(cam_d[0].data, 28, 28) \n node indexes_28 = cat(_indexes_T_56, _indexes_T_57) \n node _indexes_T_58 = bits(cam_a[0].bits.data, 29, 29) \n node _indexes_T_59 = bits(cam_d[0].data, 29, 29) \n node indexes_29 = cat(_indexes_T_58, _indexes_T_59) \n node _indexes_T_60 = bits(cam_a[0].bits.data, 30, 30) \n node _indexes_T_61 = bits(cam_d[0].data, 30, 30) \n node indexes_30 = cat(_indexes_T_60, _indexes_T_61) \n node _indexes_T_62 = bits(cam_a[0].bits.data, 31, 31) \n node _indexes_T_63 = bits(cam_d[0].data, 31, 31) \n node indexes_31 = cat(_indexes_T_62, _indexes_T_63) \n node _indexes_T_64 = bits(cam_a[0].bits.data, 32, 32) \n node _indexes_T_65 = bits(cam_d[0].data, 32, 32) \n node indexes_32 = cat(_indexes_T_64, _indexes_T_65) \n node _indexes_T_66 = bits(cam_a[0].bits.data, 33, 33) \n node _indexes_T_67 = bits(cam_d[0].data, 33, 33) \n node indexes_33 = cat(_indexes_T_66, _indexes_T_67) \n node _indexes_T_68 = bits(cam_a[0].bits.data, 34, 34) \n node _indexes_T_69 = bits(cam_d[0].data, 34, 34) \n node indexes_34 = cat(_indexes_T_68, _indexes_T_69) \n node _indexes_T_70 = bits(cam_a[0].bits.data, 35, 35) \n node _indexes_T_71 = bits(cam_d[0].data, 35, 35) \n node indexes_35 = cat(_indexes_T_70, _indexes_T_71) \n node _indexes_T_72 = bits(cam_a[0].bits.data, 36, 36) \n node _indexes_T_73 = bits(cam_d[0].data, 36, 36) \n node indexes_36 = cat(_indexes_T_72, _indexes_T_73) \n node _indexes_T_74 = bits(cam_a[0].bits.data, 37, 37) \n node _indexes_T_75 = bits(cam_d[0].data, 37, 37) \n node indexes_37 = cat(_indexes_T_74, _indexes_T_75) \n node _indexes_T_76 = bits(cam_a[0].bits.data, 38, 38) \n node _indexes_T_77 = bits(cam_d[0].data, 38, 38) \n node indexes_38 = cat(_indexes_T_76, _indexes_T_77) \n node _indexes_T_78 = bits(cam_a[0].bits.data, 39, 39) \n node _indexes_T_79 = bits(cam_d[0].data, 39, 39) \n node indexes_39 = cat(_indexes_T_78, _indexes_T_79) \n node _indexes_T_80 = bits(cam_a[0].bits.data, 40, 40) \n node _indexes_T_81 = bits(cam_d[0].data, 40, 40) \n node indexes_40 = cat(_indexes_T_80, _indexes_T_81) \n node _indexes_T_82 = bits(cam_a[0].bits.data, 41, 41) \n node _indexes_T_83 = bits(cam_d[0].data, 41, 41) \n node indexes_41 = cat(_indexes_T_82, _indexes_T_83) \n node _indexes_T_84 = bits(cam_a[0].bits.data, 42, 42) \n node _indexes_T_85 = bits(cam_d[0].data, 42, 42) \n node indexes_42 = cat(_indexes_T_84, _indexes_T_85) \n node _indexes_T_86 = bits(cam_a[0].bits.data, 43, 43) \n node _indexes_T_87 = bits(cam_d[0].data, 43, 43) \n node indexes_43 = cat(_indexes_T_86, _indexes_T_87) \n node _indexes_T_88 = bits(cam_a[0].bits.data, 44, 44) \n node _indexes_T_89 = bits(cam_d[0].data, 44, 44) \n node indexes_44 = cat(_indexes_T_88, _indexes_T_89) \n node _indexes_T_90 = bits(cam_a[0].bits.data, 45, 45) \n node _indexes_T_91 = bits(cam_d[0].data, 45, 45) \n node indexes_45 = cat(_indexes_T_90, _indexes_T_91) \n node _indexes_T_92 = bits(cam_a[0].bits.data, 46, 46) \n node _indexes_T_93 = bits(cam_d[0].data, 46, 46) \n node indexes_46 = cat(_indexes_T_92, _indexes_T_93) \n node _indexes_T_94 = bits(cam_a[0].bits.data, 47, 47) \n node _indexes_T_95 = bits(cam_d[0].data, 47, 47) \n node indexes_47 = cat(_indexes_T_94, _indexes_T_95) \n node _indexes_T_96 = bits(cam_a[0].bits.data, 48, 48) \n node _indexes_T_97 = bits(cam_d[0].data, 48, 48) \n node indexes_48 = cat(_indexes_T_96, _indexes_T_97) \n node _indexes_T_98 = bits(cam_a[0].bits.data, 49, 49) \n node _indexes_T_99 = bits(cam_d[0].data, 49, 49) \n node indexes_49 = cat(_indexes_T_98, _indexes_T_99) \n node _indexes_T_100 = bits(cam_a[0].bits.data, 50, 50) \n node _indexes_T_101 = bits(cam_d[0].data, 50, 50) \n node indexes_50 = cat(_indexes_T_100, _indexes_T_101) \n node _indexes_T_102 = bits(cam_a[0].bits.data, 51, 51) \n node _indexes_T_103 = bits(cam_d[0].data, 51, 51) \n node indexes_51 = cat(_indexes_T_102, _indexes_T_103) \n node _indexes_T_104 = bits(cam_a[0].bits.data, 52, 52) \n node _indexes_T_105 = bits(cam_d[0].data, 52, 52) \n node indexes_52 = cat(_indexes_T_104, _indexes_T_105) \n node _indexes_T_106 = bits(cam_a[0].bits.data, 53, 53) \n node _indexes_T_107 = bits(cam_d[0].data, 53, 53) \n node indexes_53 = cat(_indexes_T_106, _indexes_T_107) \n node _indexes_T_108 = bits(cam_a[0].bits.data, 54, 54) \n node _indexes_T_109 = bits(cam_d[0].data, 54, 54) \n node indexes_54 = cat(_indexes_T_108, _indexes_T_109) \n node _indexes_T_110 = bits(cam_a[0].bits.data, 55, 55) \n node _indexes_T_111 = bits(cam_d[0].data, 55, 55) \n node indexes_55 = cat(_indexes_T_110, _indexes_T_111) \n node _indexes_T_112 = bits(cam_a[0].bits.data, 56, 56) \n node _indexes_T_113 = bits(cam_d[0].data, 56, 56) \n node indexes_56 = cat(_indexes_T_112, _indexes_T_113) \n node _indexes_T_114 = bits(cam_a[0].bits.data, 57, 57) \n node _indexes_T_115 = bits(cam_d[0].data, 57, 57) \n node indexes_57 = cat(_indexes_T_114, _indexes_T_115) \n node _indexes_T_116 = bits(cam_a[0].bits.data, 58, 58) \n node _indexes_T_117 = bits(cam_d[0].data, 58, 58) \n node indexes_58 = cat(_indexes_T_116, _indexes_T_117) \n node _indexes_T_118 = bits(cam_a[0].bits.data, 59, 59) \n node _indexes_T_119 = bits(cam_d[0].data, 59, 59) \n node indexes_59 = cat(_indexes_T_118, _indexes_T_119) \n node _indexes_T_120 = bits(cam_a[0].bits.data, 60, 60) \n node _indexes_T_121 = bits(cam_d[0].data, 60, 60) \n node indexes_60 = cat(_indexes_T_120, _indexes_T_121) \n node _indexes_T_122 = bits(cam_a[0].bits.data, 61, 61) \n node _indexes_T_123 = bits(cam_d[0].data, 61, 61) \n node indexes_61 = cat(_indexes_T_122, _indexes_T_123) \n node _indexes_T_124 = bits(cam_a[0].bits.data, 62, 62) \n node _indexes_T_125 = bits(cam_d[0].data, 62, 62) \n node indexes_62 = cat(_indexes_T_124, _indexes_T_125) \n node _indexes_T_126 = bits(cam_a[0].bits.data, 63, 63) \n node _indexes_T_127 = bits(cam_d[0].data, 63, 63) \n node indexes_63 = cat(_indexes_T_126, _indexes_T_127) \n node _logic_out_T = dshr(cam_a[0].lut, indexes_0) \n node _logic_out_T_1 = bits(_logic_out_T, 0, 0) \n node _logic_out_T_2 = dshr(cam_a[0].lut, indexes_1) \n node _logic_out_T_3 = bits(_logic_out_T_2, 0, 0) \n node _logic_out_T_4 = dshr(cam_a[0].lut, indexes_2) \n node _logic_out_T_5 = bits(_logic_out_T_4, 0, 0) \n node _logic_out_T_6 = dshr(cam_a[0].lut, indexes_3) \n node _logic_out_T_7 = bits(_logic_out_T_6, 0, 0) \n node _logic_out_T_8 = dshr(cam_a[0].lut, indexes_4) \n node _logic_out_T_9 = bits(_logic_out_T_8, 0, 0) \n node _logic_out_T_10 = dshr(cam_a[0].lut, indexes_5) \n node _logic_out_T_11 = bits(_logic_out_T_10, 0, 0) \n node _logic_out_T_12 = dshr(cam_a[0].lut, indexes_6) \n node _logic_out_T_13 = bits(_logic_out_T_12, 0, 0) \n node _logic_out_T_14 = dshr(cam_a[0].lut, indexes_7) \n node _logic_out_T_15 = bits(_logic_out_T_14, 0, 0) \n node _logic_out_T_16 = dshr(cam_a[0].lut, indexes_8) \n node _logic_out_T_17 = bits(_logic_out_T_16, 0, 0) \n node _logic_out_T_18 = dshr(cam_a[0].lut, indexes_9) \n node _logic_out_T_19 = bits(_logic_out_T_18, 0, 0) \n node _logic_out_T_20 = dshr(cam_a[0].lut, indexes_10) \n node _logic_out_T_21 = bits(_logic_out_T_20, 0, 0) \n node _logic_out_T_22 = dshr(cam_a[0].lut, indexes_11) \n node _logic_out_T_23 = bits(_logic_out_T_22, 0, 0) \n node _logic_out_T_24 = dshr(cam_a[0].lut, indexes_12) \n node _logic_out_T_25 = bits(_logic_out_T_24, 0, 0) \n node _logic_out_T_26 = dshr(cam_a[0].lut, indexes_13) \n node _logic_out_T_27 = bits(_logic_out_T_26, 0, 0) \n node _logic_out_T_28 = dshr(cam_a[0].lut, indexes_14) \n node _logic_out_T_29 = bits(_logic_out_T_28, 0, 0) \n node _logic_out_T_30 = dshr(cam_a[0].lut, indexes_15) \n node _logic_out_T_31 = bits(_logic_out_T_30, 0, 0) \n node _logic_out_T_32 = dshr(cam_a[0].lut, indexes_16) \n node _logic_out_T_33 = bits(_logic_out_T_32, 0, 0) \n node _logic_out_T_34 = dshr(cam_a[0].lut, indexes_17) \n node _logic_out_T_35 = bits(_logic_out_T_34, 0, 0) \n node _logic_out_T_36 = dshr(cam_a[0].lut, indexes_18) \n node _logic_out_T_37 = bits(_logic_out_T_36, 0, 0) \n node _logic_out_T_38 = dshr(cam_a[0].lut, indexes_19) \n node _logic_out_T_39 = bits(_logic_out_T_38, 0, 0) \n node _logic_out_T_40 = dshr(cam_a[0].lut, indexes_20) \n node _logic_out_T_41 = bits(_logic_out_T_40, 0, 0) \n node _logic_out_T_42 = dshr(cam_a[0].lut, indexes_21) \n node _logic_out_T_43 = bits(_logic_out_T_42, 0, 0) \n node _logic_out_T_44 = dshr(cam_a[0].lut, indexes_22) \n node _logic_out_T_45 = bits(_logic_out_T_44, 0, 0) \n node _logic_out_T_46 = dshr(cam_a[0].lut, indexes_23) \n node _logic_out_T_47 = bits(_logic_out_T_46, 0, 0) \n node _logic_out_T_48 = dshr(cam_a[0].lut, indexes_24) \n node _logic_out_T_49 = bits(_logic_out_T_48, 0, 0) \n node _logic_out_T_50 = dshr(cam_a[0].lut, indexes_25) \n node _logic_out_T_51 = bits(_logic_out_T_50, 0, 0) \n node _logic_out_T_52 = dshr(cam_a[0].lut, indexes_26) \n node _logic_out_T_53 = bits(_logic_out_T_52, 0, 0) \n node _logic_out_T_54 = dshr(cam_a[0].lut, indexes_27) \n node _logic_out_T_55 = bits(_logic_out_T_54, 0, 0) \n node _logic_out_T_56 = dshr(cam_a[0].lut, indexes_28) \n node _logic_out_T_57 = bits(_logic_out_T_56, 0, 0) \n node _logic_out_T_58 = dshr(cam_a[0].lut, indexes_29) \n node _logic_out_T_59 = bits(_logic_out_T_58, 0, 0) \n node _logic_out_T_60 = dshr(cam_a[0].lut, indexes_30) \n node _logic_out_T_61 = bits(_logic_out_T_60, 0, 0) \n node _logic_out_T_62 = dshr(cam_a[0].lut, indexes_31) \n node _logic_out_T_63 = bits(_logic_out_T_62, 0, 0) \n node _logic_out_T_64 = dshr(cam_a[0].lut, indexes_32) \n node _logic_out_T_65 = bits(_logic_out_T_64, 0, 0) \n node _logic_out_T_66 = dshr(cam_a[0].lut, indexes_33) \n node _logic_out_T_67 = bits(_logic_out_T_66, 0, 0) \n node _logic_out_T_68 = dshr(cam_a[0].lut, indexes_34) \n node _logic_out_T_69 = bits(_logic_out_T_68, 0, 0) \n node _logic_out_T_70 = dshr(cam_a[0].lut, indexes_35) \n node _logic_out_T_71 = bits(_logic_out_T_70, 0, 0) \n node _logic_out_T_72 = dshr(cam_a[0].lut, indexes_36) \n node _logic_out_T_73 = bits(_logic_out_T_72, 0, 0) \n node _logic_out_T_74 = dshr(cam_a[0].lut, indexes_37) \n node _logic_out_T_75 = bits(_logic_out_T_74, 0, 0) \n node _logic_out_T_76 = dshr(cam_a[0].lut, indexes_38) \n node _logic_out_T_77 = bits(_logic_out_T_76, 0, 0) \n node _logic_out_T_78 = dshr(cam_a[0].lut, indexes_39) \n node _logic_out_T_79 = bits(_logic_out_T_78, 0, 0) \n node _logic_out_T_80 = dshr(cam_a[0].lut, indexes_40) \n node _logic_out_T_81 = bits(_logic_out_T_80, 0, 0) \n node _logic_out_T_82 = dshr(cam_a[0].lut, indexes_41) \n node _logic_out_T_83 = bits(_logic_out_T_82, 0, 0) \n node _logic_out_T_84 = dshr(cam_a[0].lut, indexes_42) \n node _logic_out_T_85 = bits(_logic_out_T_84, 0, 0) \n node _logic_out_T_86 = dshr(cam_a[0].lut, indexes_43) \n node _logic_out_T_87 = bits(_logic_out_T_86, 0, 0) \n node _logic_out_T_88 = dshr(cam_a[0].lut, indexes_44) \n node _logic_out_T_89 = bits(_logic_out_T_88, 0, 0) \n node _logic_out_T_90 = dshr(cam_a[0].lut, indexes_45) \n node _logic_out_T_91 = bits(_logic_out_T_90, 0, 0) \n node _logic_out_T_92 = dshr(cam_a[0].lut, indexes_46) \n node _logic_out_T_93 = bits(_logic_out_T_92, 0, 0) \n node _logic_out_T_94 = dshr(cam_a[0].lut, indexes_47) \n node _logic_out_T_95 = bits(_logic_out_T_94, 0, 0) \n node _logic_out_T_96 = dshr(cam_a[0].lut, indexes_48) \n node _logic_out_T_97 = bits(_logic_out_T_96, 0, 0) \n node _logic_out_T_98 = dshr(cam_a[0].lut, indexes_49) \n node _logic_out_T_99 = bits(_logic_out_T_98, 0, 0) \n node _logic_out_T_100 = dshr(cam_a[0].lut, indexes_50) \n node _logic_out_T_101 = bits(_logic_out_T_100, 0, 0) \n node _logic_out_T_102 = dshr(cam_a[0].lut, indexes_51) \n node _logic_out_T_103 = bits(_logic_out_T_102, 0, 0) \n node _logic_out_T_104 = dshr(cam_a[0].lut, indexes_52) \n node _logic_out_T_105 = bits(_logic_out_T_104, 0, 0) \n node _logic_out_T_106 = dshr(cam_a[0].lut, indexes_53) \n node _logic_out_T_107 = bits(_logic_out_T_106, 0, 0) \n node _logic_out_T_108 = dshr(cam_a[0].lut, indexes_54) \n node _logic_out_T_109 = bits(_logic_out_T_108, 0, 0) \n node _logic_out_T_110 = dshr(cam_a[0].lut, indexes_55) \n node _logic_out_T_111 = bits(_logic_out_T_110, 0, 0) \n node _logic_out_T_112 = dshr(cam_a[0].lut, indexes_56) \n node _logic_out_T_113 = bits(_logic_out_T_112, 0, 0) \n node _logic_out_T_114 = dshr(cam_a[0].lut, indexes_57) \n node _logic_out_T_115 = bits(_logic_out_T_114, 0, 0) \n node _logic_out_T_116 = dshr(cam_a[0].lut, indexes_58) \n node _logic_out_T_117 = bits(_logic_out_T_116, 0, 0) \n node _logic_out_T_118 = dshr(cam_a[0].lut, indexes_59) \n node _logic_out_T_119 = bits(_logic_out_T_118, 0, 0) \n node _logic_out_T_120 = dshr(cam_a[0].lut, indexes_60) \n node _logic_out_T_121 = bits(_logic_out_T_120, 0, 0) \n node _logic_out_T_122 = dshr(cam_a[0].lut, indexes_61) \n node _logic_out_T_123 = bits(_logic_out_T_122, 0, 0) \n node _logic_out_T_124 = dshr(cam_a[0].lut, indexes_62) \n node _logic_out_T_125 = bits(_logic_out_T_124, 0, 0) \n node _logic_out_T_126 = dshr(cam_a[0].lut, indexes_63) \n node _logic_out_T_127 = bits(_logic_out_T_126, 0, 0) \n node logic_out_lo_lo_lo_lo_lo = cat(_logic_out_T_3, _logic_out_T_1) \n node logic_out_lo_lo_lo_lo_hi = cat(_logic_out_T_7, _logic_out_T_5) \n node logic_out_lo_lo_lo_lo = cat(logic_out_lo_lo_lo_lo_hi, logic_out_lo_lo_lo_lo_lo) \n node logic_out_lo_lo_lo_hi_lo = cat(_logic_out_T_11, _logic_out_T_9) \n node logic_out_lo_lo_lo_hi_hi = cat(_logic_out_T_15, _logic_out_T_13) \n node logic_out_lo_lo_lo_hi = cat(logic_out_lo_lo_lo_hi_hi, logic_out_lo_lo_lo_hi_lo) \n node logic_out_lo_lo_lo = cat(logic_out_lo_lo_lo_hi, logic_out_lo_lo_lo_lo) \n node logic_out_lo_lo_hi_lo_lo = cat(_logic_out_T_19, _logic_out_T_17) \n node logic_out_lo_lo_hi_lo_hi = cat(_logic_out_T_23, _logic_out_T_21) \n node logic_out_lo_lo_hi_lo = cat(logic_out_lo_lo_hi_lo_hi, logic_out_lo_lo_hi_lo_lo) \n node logic_out_lo_lo_hi_hi_lo = cat(_logic_out_T_27, _logic_out_T_25) \n node logic_out_lo_lo_hi_hi_hi = cat(_logic_out_T_31, _logic_out_T_29) \n node logic_out_lo_lo_hi_hi = cat(logic_out_lo_lo_hi_hi_hi, logic_out_lo_lo_hi_hi_lo) \n node logic_out_lo_lo_hi = cat(logic_out_lo_lo_hi_hi, logic_out_lo_lo_hi_lo) \n node logic_out_lo_lo = cat(logic_out_lo_lo_hi, logic_out_lo_lo_lo) \n node logic_out_lo_hi_lo_lo_lo = cat(_logic_out_T_35, _logic_out_T_33) \n node logic_out_lo_hi_lo_lo_hi = cat(_logic_out_T_39, _logic_out_T_37) \n node logic_out_lo_hi_lo_lo = cat(logic_out_lo_hi_lo_lo_hi, logic_out_lo_hi_lo_lo_lo) \n node logic_out_lo_hi_lo_hi_lo = cat(_logic_out_T_43, _logic_out_T_41) \n node logic_out_lo_hi_lo_hi_hi = cat(_logic_out_T_47, _logic_out_T_45) \n node logic_out_lo_hi_lo_hi = cat(logic_out_lo_hi_lo_hi_hi, logic_out_lo_hi_lo_hi_lo) \n node logic_out_lo_hi_lo = cat(logic_out_lo_hi_lo_hi, logic_out_lo_hi_lo_lo) \n node logic_out_lo_hi_hi_lo_lo = cat(_logic_out_T_51, _logic_out_T_49) \n node logic_out_lo_hi_hi_lo_hi = cat(_logic_out_T_55, _logic_out_T_53) \n node logic_out_lo_hi_hi_lo = cat(logic_out_lo_hi_hi_lo_hi, logic_out_lo_hi_hi_lo_lo) \n node logic_out_lo_hi_hi_hi_lo = cat(_logic_out_T_59, _logic_out_T_57) \n node logic_out_lo_hi_hi_hi_hi = cat(_logic_out_T_63, _logic_out_T_61) \n node logic_out_lo_hi_hi_hi = cat(logic_out_lo_hi_hi_hi_hi, logic_out_lo_hi_hi_hi_lo) \n node logic_out_lo_hi_hi = cat(logic_out_lo_hi_hi_hi, logic_out_lo_hi_hi_lo) \n node logic_out_lo_hi = cat(logic_out_lo_hi_hi, logic_out_lo_hi_lo) \n node logic_out_lo = cat(logic_out_lo_hi, logic_out_lo_lo) \n node logic_out_hi_lo_lo_lo_lo = cat(_logic_out_T_67, _logic_out_T_65) \n node logic_out_hi_lo_lo_lo_hi = cat(_logic_out_T_71, _logic_out_T_69) \n node logic_out_hi_lo_lo_lo = cat(logic_out_hi_lo_lo_lo_hi, logic_out_hi_lo_lo_lo_lo) \n node logic_out_hi_lo_lo_hi_lo = cat(_logic_out_T_75, _logic_out_T_73) \n node logic_out_hi_lo_lo_hi_hi = cat(_logic_out_T_79, _logic_out_T_77) \n node logic_out_hi_lo_lo_hi = cat(logic_out_hi_lo_lo_hi_hi, logic_out_hi_lo_lo_hi_lo) \n node logic_out_hi_lo_lo = cat(logic_out_hi_lo_lo_hi, logic_out_hi_lo_lo_lo) \n node logic_out_hi_lo_hi_lo_lo = cat(_logic_out_T_83, _logic_out_T_81) \n node logic_out_hi_lo_hi_lo_hi = cat(_logic_out_T_87, _logic_out_T_85) \n node logic_out_hi_lo_hi_lo = cat(logic_out_hi_lo_hi_lo_hi, logic_out_hi_lo_hi_lo_lo) \n node logic_out_hi_lo_hi_hi_lo = cat(_logic_out_T_91, _logic_out_T_89) \n node logic_out_hi_lo_hi_hi_hi = cat(_logic_out_T_95, _logic_out_T_93) \n node logic_out_hi_lo_hi_hi = cat(logic_out_hi_lo_hi_hi_hi, logic_out_hi_lo_hi_hi_lo) \n node logic_out_hi_lo_hi = cat(logic_out_hi_lo_hi_hi, logic_out_hi_lo_hi_lo) \n node logic_out_hi_lo = cat(logic_out_hi_lo_hi, logic_out_hi_lo_lo) \n node logic_out_hi_hi_lo_lo_lo = cat(_logic_out_T_99, _logic_out_T_97) \n node logic_out_hi_hi_lo_lo_hi = cat(_logic_out_T_103, _logic_out_T_101) \n node logic_out_hi_hi_lo_lo = cat(logic_out_hi_hi_lo_lo_hi, logic_out_hi_hi_lo_lo_lo) \n node logic_out_hi_hi_lo_hi_lo = cat(_logic_out_T_107, _logic_out_T_105) \n node logic_out_hi_hi_lo_hi_hi = cat(_logic_out_T_111, _logic_out_T_109) \n node logic_out_hi_hi_lo_hi = cat(logic_out_hi_hi_lo_hi_hi, logic_out_hi_hi_lo_hi_lo) \n node logic_out_hi_hi_lo = cat(logic_out_hi_hi_lo_hi, logic_out_hi_hi_lo_lo) \n node logic_out_hi_hi_hi_lo_lo = cat(_logic_out_T_115, _logic_out_T_113) \n node logic_out_hi_hi_hi_lo_hi = cat(_logic_out_T_119, _logic_out_T_117) \n node logic_out_hi_hi_hi_lo = cat(logic_out_hi_hi_hi_lo_hi, logic_out_hi_hi_hi_lo_lo) \n node logic_out_hi_hi_hi_hi_lo = cat(_logic_out_T_123, _logic_out_T_121) \n node logic_out_hi_hi_hi_hi_hi = cat(_logic_out_T_127, _logic_out_T_125) \n node logic_out_hi_hi_hi_hi = cat(logic_out_hi_hi_hi_hi_hi, logic_out_hi_hi_hi_hi_lo) \n node logic_out_hi_hi_hi = cat(logic_out_hi_hi_hi_hi, logic_out_hi_hi_hi_lo) \n node logic_out_hi_hi = cat(logic_out_hi_hi_hi, logic_out_hi_hi_lo) \n node logic_out_hi = cat(logic_out_hi_hi, logic_out_hi_lo) \n node logic_out = cat(logic_out_hi, logic_out_lo) \n node unsigned = bits(cam_a[0].bits.param, 1, 1) \n node take_max = bits(cam_a[0].bits.param, 0, 0) \n node adder = bits(cam_a[0].bits.param, 2, 2) \n node _signSel_T = not(cam_a[0].bits.mask) \n node _signSel_T_1 = shr(cam_a[0].bits.mask, 1) \n node _signSel_T_2 = or(_signSel_T, _signSel_T_1) \n node signSel = not(_signSel_T_2) \n node _signbits_a_T = bits(cam_a[0].bits.data, 7, 7) \n node _signbits_a_T_1 = bits(cam_a[0].bits.data, 15, 15) \n node _signbits_a_T_2 = bits(cam_a[0].bits.data, 23, 23) \n node _signbits_a_T_3 = bits(cam_a[0].bits.data, 31, 31) \n node _signbits_a_T_4 = bits(cam_a[0].bits.data, 39, 39) \n node _signbits_a_T_5 = bits(cam_a[0].bits.data, 47, 47) \n node _signbits_a_T_6 = bits(cam_a[0].bits.data, 55, 55) \n node _signbits_a_T_7 = bits(cam_a[0].bits.data, 63, 63) \n node signbits_a_lo_lo = cat(_signbits_a_T_1, _signbits_a_T) \n node signbits_a_lo_hi = cat(_signbits_a_T_3, _signbits_a_T_2) \n node signbits_a_lo = cat(signbits_a_lo_hi, signbits_a_lo_lo) \n node signbits_a_hi_lo = cat(_signbits_a_T_5, _signbits_a_T_4) \n node signbits_a_hi_hi = cat(_signbits_a_T_7, _signbits_a_T_6) \n node signbits_a_hi = cat(signbits_a_hi_hi, signbits_a_hi_lo) \n node signbits_a = cat(signbits_a_hi, signbits_a_lo) \n node _signbits_d_T = bits(cam_d[0].data, 7, 7) \n node _signbits_d_T_1 = bits(cam_d[0].data, 15, 15) \n node _signbits_d_T_2 = bits(cam_d[0].data, 23, 23) \n node _signbits_d_T_3 = bits(cam_d[0].data, 31, 31) \n node _signbits_d_T_4 = bits(cam_d[0].data, 39, 39) \n node _signbits_d_T_5 = bits(cam_d[0].data, 47, 47) \n node _signbits_d_T_6 = bits(cam_d[0].data, 55, 55) \n node _signbits_d_T_7 = bits(cam_d[0].data, 63, 63) \n node signbits_d_lo_lo = cat(_signbits_d_T_1, _signbits_d_T) \n node signbits_d_lo_hi = cat(_signbits_d_T_3, _signbits_d_T_2) \n node signbits_d_lo = cat(signbits_d_lo_hi, signbits_d_lo_lo) \n node signbits_d_hi_lo = cat(_signbits_d_T_5, _signbits_d_T_4) \n node signbits_d_hi_hi = cat(_signbits_d_T_7, _signbits_d_T_6) \n node signbits_d_hi = cat(signbits_d_hi_hi, signbits_d_hi_lo) \n node signbits_d = cat(signbits_d_hi, signbits_d_lo) \n node _signbit_a_T = and(signbits_a, signSel) \n node _signbit_a_T_1 = shl(_signbit_a_T, 1) \n node signbit_a = bits(_signbit_a_T_1, 7, 0) \n node _signbit_d_T = and(signbits_d, signSel) \n node _signbit_d_T_1 = shl(_signbit_d_T, 1) \n node signbit_d = bits(_signbit_d_T_1, 7, 0) \n node _signext_a_T = shl(signbit_a, 1) \n node _signext_a_T_1 = bits(_signext_a_T, 7, 0) \n node _signext_a_T_2 = or(signbit_a, _signext_a_T_1) \n node _signext_a_T_3 = shl(_signext_a_T_2, 2) \n node _signext_a_T_4 = bits(_signext_a_T_3, 7, 0) \n node _signext_a_T_5 = or(_signext_a_T_2, _signext_a_T_4) \n node _signext_a_T_6 = shl(_signext_a_T_5, 4) \n node _signext_a_T_7 = bits(_signext_a_T_6, 7, 0) \n node _signext_a_T_8 = or(_signext_a_T_5, _signext_a_T_7) \n node _signext_a_T_9 = bits(_signext_a_T_8, 7, 0) \n node _signext_a_T_10 = bits(_signext_a_T_9, 0, 0) \n node _signext_a_T_11 = bits(_signext_a_T_9, 1, 1) \n node _signext_a_T_12 = bits(_signext_a_T_9, 2, 2) \n node _signext_a_T_13 = bits(_signext_a_T_9, 3, 3) \n node _signext_a_T_14 = bits(_signext_a_T_9, 4, 4) \n node _signext_a_T_15 = bits(_signext_a_T_9, 5, 5) \n node _signext_a_T_16 = bits(_signext_a_T_9, 6, 6) \n node _signext_a_T_17 = bits(_signext_a_T_9, 7, 7) \n node _signext_a_T_18 = mux(_signext_a_T_10, UInt<8>(0hff), UInt<8>(0h0)) \n node _signext_a_T_19 = mux(_signext_a_T_11, UInt<8>(0hff), UInt<8>(0h0)) \n node _signext_a_T_20 = mux(_signext_a_T_12, UInt<8>(0hff), UInt<8>(0h0)) \n node _signext_a_T_21 = mux(_signext_a_T_13, UInt<8>(0hff), UInt<8>(0h0)) \n node _signext_a_T_22 = mux(_signext_a_T_14, UInt<8>(0hff), UInt<8>(0h0)) \n node _signext_a_T_23 = mux(_signext_a_T_15, UInt<8>(0hff), UInt<8>(0h0)) \n node _signext_a_T_24 = mux(_signext_a_T_16, UInt<8>(0hff), UInt<8>(0h0)) \n node _signext_a_T_25 = mux(_signext_a_T_17, UInt<8>(0hff), UInt<8>(0h0)) \n node signext_a_lo_lo = cat(_signext_a_T_19, _signext_a_T_18) \n node signext_a_lo_hi = cat(_signext_a_T_21, _signext_a_T_20) \n node signext_a_lo = cat(signext_a_lo_hi, signext_a_lo_lo) \n node signext_a_hi_lo = cat(_signext_a_T_23, _signext_a_T_22) \n node signext_a_hi_hi = cat(_signext_a_T_25, _signext_a_T_24) \n node signext_a_hi = cat(signext_a_hi_hi, signext_a_hi_lo) \n node signext_a = cat(signext_a_hi, signext_a_lo) \n node _signext_d_T = shl(signbit_d, 1) \n node _signext_d_T_1 = bits(_signext_d_T, 7, 0) \n node _signext_d_T_2 = or(signbit_d, _signext_d_T_1) \n node _signext_d_T_3 = shl(_signext_d_T_2, 2) \n node _signext_d_T_4 = bits(_signext_d_T_3, 7, 0) \n node _signext_d_T_5 = or(_signext_d_T_2, _signext_d_T_4) \n node _signext_d_T_6 = shl(_signext_d_T_5, 4) \n node _signext_d_T_7 = bits(_signext_d_T_6, 7, 0) \n node _signext_d_T_8 = or(_signext_d_T_5, _signext_d_T_7) \n node _signext_d_T_9 = bits(_signext_d_T_8, 7, 0) \n node _signext_d_T_10 = bits(_signext_d_T_9, 0, 0) \n node _signext_d_T_11 = bits(_signext_d_T_9, 1, 1) \n node _signext_d_T_12 = bits(_signext_d_T_9, 2, 2) \n node _signext_d_T_13 = bits(_signext_d_T_9, 3, 3) \n node _signext_d_T_14 = bits(_signext_d_T_9, 4, 4) \n node _signext_d_T_15 = bits(_signext_d_T_9, 5, 5) \n node _signext_d_T_16 = bits(_signext_d_T_9, 6, 6) \n node _signext_d_T_17 = bits(_signext_d_T_9, 7, 7) \n node _signext_d_T_18 = mux(_signext_d_T_10, UInt<8>(0hff), UInt<8>(0h0)) \n node _signext_d_T_19 = mux(_signext_d_T_11, UInt<8>(0hff), UInt<8>(0h0)) \n node _signext_d_T_20 = mux(_signext_d_T_12, UInt<8>(0hff), UInt<8>(0h0)) \n node _signext_d_T_21 = mux(_signext_d_T_13, UInt<8>(0hff), UInt<8>(0h0)) \n node _signext_d_T_22 = mux(_signext_d_T_14, UInt<8>(0hff), UInt<8>(0h0)) \n node _signext_d_T_23 = mux(_signext_d_T_15, UInt<8>(0hff), UInt<8>(0h0)) \n node _signext_d_T_24 = mux(_signext_d_T_16, UInt<8>(0hff), UInt<8>(0h0)) \n node _signext_d_T_25 = mux(_signext_d_T_17, UInt<8>(0hff), UInt<8>(0h0)) \n node signext_d_lo_lo = cat(_signext_d_T_19, _signext_d_T_18) \n node signext_d_lo_hi = cat(_signext_d_T_21, _signext_d_T_20) \n node signext_d_lo = cat(signext_d_lo_hi, signext_d_lo_lo) \n node signext_d_hi_lo = cat(_signext_d_T_23, _signext_d_T_22) \n node signext_d_hi_hi = cat(_signext_d_T_25, _signext_d_T_24) \n node signext_d_hi = cat(signext_d_hi_hi, signext_d_hi_lo) \n node signext_d = cat(signext_d_hi, signext_d_lo) \n node _wide_mask_T = bits(cam_a[0].bits.mask, 0, 0) \n node _wide_mask_T_1 = bits(cam_a[0].bits.mask, 1, 1) \n node _wide_mask_T_2 = bits(cam_a[0].bits.mask, 2, 2) \n node _wide_mask_T_3 = bits(cam_a[0].bits.mask, 3, 3) \n node _wide_mask_T_4 = bits(cam_a[0].bits.mask, 4, 4) \n node _wide_mask_T_5 = bits(cam_a[0].bits.mask, 5, 5) \n node _wide_mask_T_6 = bits(cam_a[0].bits.mask, 6, 6) \n node _wide_mask_T_7 = bits(cam_a[0].bits.mask, 7, 7) \n node _wide_mask_T_8 = mux(_wide_mask_T, UInt<8>(0hff), UInt<8>(0h0)) \n node _wide_mask_T_9 = mux(_wide_mask_T_1, UInt<8>(0hff), UInt<8>(0h0)) \n node _wide_mask_T_10 = mux(_wide_mask_T_2, UInt<8>(0hff), UInt<8>(0h0)) \n node _wide_mask_T_11 = mux(_wide_mask_T_3, UInt<8>(0hff), UInt<8>(0h0)) \n node _wide_mask_T_12 = mux(_wide_mask_T_4, UInt<8>(0hff), UInt<8>(0h0)) \n node _wide_mask_T_13 = mux(_wide_mask_T_5, UInt<8>(0hff), UInt<8>(0h0)) \n node _wide_mask_T_14 = mux(_wide_mask_T_6, UInt<8>(0hff), UInt<8>(0h0)) \n node _wide_mask_T_15 = mux(_wide_mask_T_7, UInt<8>(0hff), UInt<8>(0h0)) \n node wide_mask_lo_lo = cat(_wide_mask_T_9, _wide_mask_T_8) \n node wide_mask_lo_hi = cat(_wide_mask_T_11, _wide_mask_T_10) \n node wide_mask_lo = cat(wide_mask_lo_hi, wide_mask_lo_lo) \n node wide_mask_hi_lo = cat(_wide_mask_T_13, _wide_mask_T_12) \n node wide_mask_hi_hi = cat(_wide_mask_T_15, _wide_mask_T_14) \n node wide_mask_hi = cat(wide_mask_hi_hi, wide_mask_hi_lo) \n node wide_mask = cat(wide_mask_hi, wide_mask_lo) \n node _a_a_ext_T = and(cam_a[0].bits.data, wide_mask) \n node a_a_ext = or(_a_a_ext_T, signext_a) \n node _a_d_ext_T = and(cam_d[0].data, wide_mask) \n node a_d_ext = or(_a_d_ext_T, signext_d) \n node _a_d_inv_T = not(a_d_ext) \n node a_d_inv = mux(adder, a_d_ext, _a_d_inv_T) \n node _adder_out_T = add(a_a_ext, a_d_inv) \n node adder_out = tail(_adder_out_T, 1) \n node _a_bigger_uneq_T = bits(a_a_ext, 63, 63) \n node a_bigger_uneq = eq(unsigned, _a_bigger_uneq_T) \n node _a_bigger_T = bits(a_a_ext, 63, 63) \n node _a_bigger_T_1 = bits(a_d_ext, 63, 63) \n node _a_bigger_T_2 = eq(_a_bigger_T, _a_bigger_T_1) \n node _a_bigger_T_3 = bits(adder_out, 63, 63) \n node _a_bigger_T_4 = eq(_a_bigger_T_3, UInt<1>(0h0)) \n node a_bigger = mux(_a_bigger_T_2, _a_bigger_T_4, a_bigger_uneq) \n node pick_a = eq(take_max, a_bigger) \n node _arith_out_T = mux(pick_a, cam_a[0].bits.data, cam_d[0].data) \n node arith_out = mux(adder, adder_out, _arith_out_T) \n node _amo_data_T = bits(cam_a[0].bits.opcode, 0, 0) \n node amo_data = mux(_amo_data_T, logic_out, arith_out) \n wire source_i : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} \n node _a_allow_T = eq(a_cam_busy, UInt<1>(0h0)) \n node _a_allow_T_1 = or(a_isSupported, cam_free_0) \n node a_allow = and(_a_allow_T, _a_allow_T_1) \n node _nodeIn_a_ready_T = and(source_i.ready, a_allow) \n connect nodeIn.a.ready, _nodeIn_a_ready_T \n node _source_i_valid_T = and(nodeIn.a.valid, a_allow) \n connect source_i.valid, _source_i_valid_T \n connect source_i.bits, nodeIn.a.bits \n node _T = eq(a_isSupported, UInt<1>(0h0)) \n when _T : \n connect source_i.bits.opcode, UInt<3>(0h4) \n connect source_i.bits.param, UInt<1>(0h0) \n wire source_c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} \n connect source_c.valid, cam_amo_0 \n node _source_c_bits_T = or(cam_a[0].bits.corrupt, cam_d[0].corrupt) \n node _source_c_bits_legal_T = leq(UInt<1>(0h0), cam_a[0].bits.size) \n node _source_c_bits_legal_T_1 = leq(cam_a[0].bits.size, UInt<4>(0hc)) \n node _source_c_bits_legal_T_2 = and(_source_c_bits_legal_T, _source_c_bits_legal_T_1) \n node _source_c_bits_legal_T_3 = or(UInt<1>(0h0), _source_c_bits_legal_T_2) \n node _source_c_bits_legal_T_4 = xor(cam_a[0].bits.address, UInt<14>(0h3000)) \n node _source_c_bits_legal_T_5 = cvt(_source_c_bits_legal_T_4) \n node _source_c_bits_legal_T_6 = and(_source_c_bits_legal_T_5, asSInt(UInt<33>(0h8a113000))) \n node _source_c_bits_legal_T_7 = asSInt(_source_c_bits_legal_T_6) \n node _source_c_bits_legal_T_8 = eq(_source_c_bits_legal_T_7, asSInt(UInt<1>(0h0))) \n node _source_c_bits_legal_T_9 = and(_source_c_bits_legal_T_3, _source_c_bits_legal_T_8) \n node _source_c_bits_legal_T_10 = leq(UInt<1>(0h0), cam_a[0].bits.size) \n node _source_c_bits_legal_T_11 = leq(cam_a[0].bits.size, UInt<3>(0h6)) \n node _source_c_bits_legal_T_12 = and(_source_c_bits_legal_T_10, _source_c_bits_legal_T_11) \n node _source_c_bits_legal_T_13 = or(UInt<1>(0h0), _source_c_bits_legal_T_12) \n node _source_c_bits_legal_T_14 = xor(cam_a[0].bits.address, UInt<1>(0h0)) \n node _source_c_bits_legal_T_15 = cvt(_source_c_bits_legal_T_14) \n node _source_c_bits_legal_T_16 = and(_source_c_bits_legal_T_15, asSInt(UInt<33>(0h8a112000))) \n node _source_c_bits_legal_T_17 = asSInt(_source_c_bits_legal_T_16) \n node _source_c_bits_legal_T_18 = eq(_source_c_bits_legal_T_17, asSInt(UInt<1>(0h0))) \n node _source_c_bits_legal_T_19 = xor(cam_a[0].bits.address, UInt<21>(0h100000)) \n node _source_c_bits_legal_T_20 = cvt(_source_c_bits_legal_T_19) \n node _source_c_bits_legal_T_21 = and(_source_c_bits_legal_T_20, asSInt(UInt<33>(0h8a103000))) \n node _source_c_bits_legal_T_22 = asSInt(_source_c_bits_legal_T_21) \n node _source_c_bits_legal_T_23 = eq(_source_c_bits_legal_T_22, asSInt(UInt<1>(0h0))) \n node _source_c_bits_legal_T_24 = xor(cam_a[0].bits.address, UInt<26>(0h2000000)) \n node _source_c_bits_legal_T_25 = cvt(_source_c_bits_legal_T_24) \n node _source_c_bits_legal_T_26 = and(_source_c_bits_legal_T_25, asSInt(UInt<33>(0h8a110000))) \n node _source_c_bits_legal_T_27 = asSInt(_source_c_bits_legal_T_26) \n node _source_c_bits_legal_T_28 = eq(_source_c_bits_legal_T_27, asSInt(UInt<1>(0h0))) \n node _source_c_bits_legal_T_29 = xor(cam_a[0].bits.address, UInt<28>(0h8000000)) \n node _source_c_bits_legal_T_30 = cvt(_source_c_bits_legal_T_29) \n node _source_c_bits_legal_T_31 = and(_source_c_bits_legal_T_30, asSInt(UInt<33>(0h88000000))) \n node _source_c_bits_legal_T_32 = asSInt(_source_c_bits_legal_T_31) \n node _source_c_bits_legal_T_33 = eq(_source_c_bits_legal_T_32, asSInt(UInt<1>(0h0))) \n node _source_c_bits_legal_T_34 = xor(cam_a[0].bits.address, UInt<32>(0h80000000)) \n node _source_c_bits_legal_T_35 = cvt(_source_c_bits_legal_T_34) \n node _source_c_bits_legal_T_36 = and(_source_c_bits_legal_T_35, asSInt(UInt<33>(0h8a110000))) \n node _source_c_bits_legal_T_37 = asSInt(_source_c_bits_legal_T_36) \n node _source_c_bits_legal_T_38 = eq(_source_c_bits_legal_T_37, asSInt(UInt<1>(0h0))) \n node _source_c_bits_legal_T_39 = or(_source_c_bits_legal_T_18, _source_c_bits_legal_T_23) \n node _source_c_bits_legal_T_40 = or(_source_c_bits_legal_T_39, _source_c_bits_legal_T_28) \n node _source_c_bits_legal_T_41 = or(_source_c_bits_legal_T_40, _source_c_bits_legal_T_33) \n node _source_c_bits_legal_T_42 = or(_source_c_bits_legal_T_41, _source_c_bits_legal_T_38) \n node _source_c_bits_legal_T_43 = and(_source_c_bits_legal_T_13, _source_c_bits_legal_T_42) \n node _source_c_bits_legal_T_44 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _source_c_bits_legal_T_45 = xor(cam_a[0].bits.address, UInt<17>(0h10000)) \n node _source_c_bits_legal_T_46 = cvt(_source_c_bits_legal_T_45) \n node _source_c_bits_legal_T_47 = and(_source_c_bits_legal_T_46, asSInt(UInt<33>(0h8a110000))) \n node _source_c_bits_legal_T_48 = asSInt(_source_c_bits_legal_T_47) \n node _source_c_bits_legal_T_49 = eq(_source_c_bits_legal_T_48, asSInt(UInt<1>(0h0))) \n node _source_c_bits_legal_T_50 = and(_source_c_bits_legal_T_44, _source_c_bits_legal_T_49) \n node _source_c_bits_legal_T_51 = or(UInt<1>(0h0), _source_c_bits_legal_T_9) \n node _source_c_bits_legal_T_52 = or(_source_c_bits_legal_T_51, _source_c_bits_legal_T_43) \n node source_c_bits_legal = or(_source_c_bits_legal_T_52, _source_c_bits_legal_T_50) \n wire source_c_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} \n connect source_c_bits_a.opcode, UInt<1>(0h0) \n connect source_c_bits_a.param, UInt<1>(0h0) \n connect source_c_bits_a.size, cam_a[0].bits.size \n connect source_c_bits_a.source, cam_a[0].bits.source \n connect source_c_bits_a.address, cam_a[0].bits.address \n node _source_c_bits_a_mask_sizeOH_T = or(cam_a[0].bits.size, UInt<3>(0h0)) \n node source_c_bits_a_mask_sizeOH_shiftAmount = bits(_source_c_bits_a_mask_sizeOH_T, 1, 0) \n node _source_c_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), source_c_bits_a_mask_sizeOH_shiftAmount) \n node _source_c_bits_a_mask_sizeOH_T_2 = bits(_source_c_bits_a_mask_sizeOH_T_1, 2, 0) \n node source_c_bits_a_mask_sizeOH = or(_source_c_bits_a_mask_sizeOH_T_2, UInt<1>(0h1)) \n node source_c_bits_a_mask_sub_sub_sub_0_1 = geq(cam_a[0].bits.size, UInt<2>(0h3)) \n node source_c_bits_a_mask_sub_sub_size = bits(source_c_bits_a_mask_sizeOH, 2, 2) \n node source_c_bits_a_mask_sub_sub_bit = bits(cam_a[0].bits.address, 2, 2) \n node source_c_bits_a_mask_sub_sub_nbit = eq(source_c_bits_a_mask_sub_sub_bit, UInt<1>(0h0)) \n node source_c_bits_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), source_c_bits_a_mask_sub_sub_nbit) \n node _source_c_bits_a_mask_sub_sub_acc_T = and(source_c_bits_a_mask_sub_sub_size, source_c_bits_a_mask_sub_sub_0_2) \n node source_c_bits_a_mask_sub_sub_0_1 = or(source_c_bits_a_mask_sub_sub_sub_0_1, _source_c_bits_a_mask_sub_sub_acc_T) \n node source_c_bits_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), source_c_bits_a_mask_sub_sub_bit) \n node _source_c_bits_a_mask_sub_sub_acc_T_1 = and(source_c_bits_a_mask_sub_sub_size, source_c_bits_a_mask_sub_sub_1_2) \n node source_c_bits_a_mask_sub_sub_1_1 = or(source_c_bits_a_mask_sub_sub_sub_0_1, _source_c_bits_a_mask_sub_sub_acc_T_1) \n node source_c_bits_a_mask_sub_size = bits(source_c_bits_a_mask_sizeOH, 1, 1) \n node source_c_bits_a_mask_sub_bit = bits(cam_a[0].bits.address, 1, 1) \n node source_c_bits_a_mask_sub_nbit = eq(source_c_bits_a_mask_sub_bit, UInt<1>(0h0)) \n node source_c_bits_a_mask_sub_0_2 = and(source_c_bits_a_mask_sub_sub_0_2, source_c_bits_a_mask_sub_nbit) \n node _source_c_bits_a_mask_sub_acc_T = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_0_2) \n node source_c_bits_a_mask_sub_0_1 = or(source_c_bits_a_mask_sub_sub_0_1, _source_c_bits_a_mask_sub_acc_T) \n node source_c_bits_a_mask_sub_1_2 = and(source_c_bits_a_mask_sub_sub_0_2, source_c_bits_a_mask_sub_bit) \n node _source_c_bits_a_mask_sub_acc_T_1 = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_1_2) \n node source_c_bits_a_mask_sub_1_1 = or(source_c_bits_a_mask_sub_sub_0_1, _source_c_bits_a_mask_sub_acc_T_1) \n node source_c_bits_a_mask_sub_2_2 = and(source_c_bits_a_mask_sub_sub_1_2, source_c_bits_a_mask_sub_nbit) \n node _source_c_bits_a_mask_sub_acc_T_2 = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_2_2) \n node source_c_bits_a_mask_sub_2_1 = or(source_c_bits_a_mask_sub_sub_1_1, _source_c_bits_a_mask_sub_acc_T_2) \n node source_c_bits_a_mask_sub_3_2 = and(source_c_bits_a_mask_sub_sub_1_2, source_c_bits_a_mask_sub_bit) \n node _source_c_bits_a_mask_sub_acc_T_3 = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_3_2) \n node source_c_bits_a_mask_sub_3_1 = or(source_c_bits_a_mask_sub_sub_1_1, _source_c_bits_a_mask_sub_acc_T_3) \n node source_c_bits_a_mask_size = bits(source_c_bits_a_mask_sizeOH, 0, 0) \n node source_c_bits_a_mask_bit = bits(cam_a[0].bits.address, 0, 0) \n node source_c_bits_a_mask_nbit = eq(source_c_bits_a_mask_bit, UInt<1>(0h0)) \n node source_c_bits_a_mask_eq = and(source_c_bits_a_mask_sub_0_2, source_c_bits_a_mask_nbit) \n node _source_c_bits_a_mask_acc_T = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq) \n node source_c_bits_a_mask_acc = or(source_c_bits_a_mask_sub_0_1, _source_c_bits_a_mask_acc_T) \n node source_c_bits_a_mask_eq_1 = and(source_c_bits_a_mask_sub_0_2, source_c_bits_a_mask_bit) \n node _source_c_bits_a_mask_acc_T_1 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_1) \n node source_c_bits_a_mask_acc_1 = or(source_c_bits_a_mask_sub_0_1, _source_c_bits_a_mask_acc_T_1) \n node source_c_bits_a_mask_eq_2 = and(source_c_bits_a_mask_sub_1_2, source_c_bits_a_mask_nbit) \n node _source_c_bits_a_mask_acc_T_2 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_2) \n node source_c_bits_a_mask_acc_2 = or(source_c_bits_a_mask_sub_1_1, _source_c_bits_a_mask_acc_T_2) \n node source_c_bits_a_mask_eq_3 = and(source_c_bits_a_mask_sub_1_2, source_c_bits_a_mask_bit) \n node _source_c_bits_a_mask_acc_T_3 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_3) \n node source_c_bits_a_mask_acc_3 = or(source_c_bits_a_mask_sub_1_1, _source_c_bits_a_mask_acc_T_3) \n node source_c_bits_a_mask_eq_4 = and(source_c_bits_a_mask_sub_2_2, source_c_bits_a_mask_nbit) \n node _source_c_bits_a_mask_acc_T_4 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_4) \n node source_c_bits_a_mask_acc_4 = or(source_c_bits_a_mask_sub_2_1, _source_c_bits_a_mask_acc_T_4) \n node source_c_bits_a_mask_eq_5 = and(source_c_bits_a_mask_sub_2_2, source_c_bits_a_mask_bit) \n node _source_c_bits_a_mask_acc_T_5 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_5) \n node source_c_bits_a_mask_acc_5 = or(source_c_bits_a_mask_sub_2_1, _source_c_bits_a_mask_acc_T_5) \n node source_c_bits_a_mask_eq_6 = and(source_c_bits_a_mask_sub_3_2, source_c_bits_a_mask_nbit) \n node _source_c_bits_a_mask_acc_T_6 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_6) \n node source_c_bits_a_mask_acc_6 = or(source_c_bits_a_mask_sub_3_1, _source_c_bits_a_mask_acc_T_6) \n node source_c_bits_a_mask_eq_7 = and(source_c_bits_a_mask_sub_3_2, source_c_bits_a_mask_bit) \n node _source_c_bits_a_mask_acc_T_7 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_7) \n node source_c_bits_a_mask_acc_7 = or(source_c_bits_a_mask_sub_3_1, _source_c_bits_a_mask_acc_T_7) \n node source_c_bits_a_mask_lo_lo = cat(source_c_bits_a_mask_acc_1, source_c_bits_a_mask_acc) \n node source_c_bits_a_mask_lo_hi = cat(source_c_bits_a_mask_acc_3, source_c_bits_a_mask_acc_2) \n node source_c_bits_a_mask_lo = cat(source_c_bits_a_mask_lo_hi, source_c_bits_a_mask_lo_lo) \n node source_c_bits_a_mask_hi_lo = cat(source_c_bits_a_mask_acc_5, source_c_bits_a_mask_acc_4) \n node source_c_bits_a_mask_hi_hi = cat(source_c_bits_a_mask_acc_7, source_c_bits_a_mask_acc_6) \n node source_c_bits_a_mask_hi = cat(source_c_bits_a_mask_hi_hi, source_c_bits_a_mask_hi_lo) \n node _source_c_bits_a_mask_T = cat(source_c_bits_a_mask_hi, source_c_bits_a_mask_lo) \n connect source_c_bits_a.mask, _source_c_bits_a_mask_T \n connect source_c_bits_a.data, amo_data \n connect source_c_bits_a.corrupt, _source_c_bits_T \n connect source_c.bits, source_c_bits_a \n node _decode_T = dshl(UInt<12>(0hfff), nodeIn.a.bits.size) \n node _decode_T_1 = bits(_decode_T, 11, 0) \n node _decode_T_2 = not(_decode_T_1) \n node decode = shr(_decode_T_2, 3) \n node _opdata_T = bits(nodeIn.a.bits.opcode, 2, 2) \n node opdata = eq(_opdata_T, UInt<1>(0h0)) \n node _T_1 = mux(opdata, decode, UInt<1>(0h0)) \n regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) \n node idle = eq(beatsLeft, UInt<1>(0h0)) \n node latch = and(idle, nodeOut.a.ready) \n node _readys_T = cat(source_i.valid, source_c.valid) \n node _readys_T_1 = shl(_readys_T, 1) \n node _readys_T_2 = bits(_readys_T_1, 1, 0) \n node _readys_T_3 = or(_readys_T, _readys_T_2) \n node _readys_T_4 = bits(_readys_T_3, 1, 0) \n node _readys_T_5 = shl(_readys_T_4, 1) \n node _readys_T_6 = bits(_readys_T_5, 1, 0) \n node _readys_T_7 = not(_readys_T_6) \n node _readys_T_8 = bits(_readys_T_7, 0, 0) \n node _readys_T_9 = bits(_readys_T_7, 1, 1) \n wire readys : UInt<1>[2] \n connect readys[0], _readys_T_8 \n connect readys[1], _readys_T_9 \n node _winner_T = and(readys[0], source_c.valid) \n node _winner_T_1 = and(readys[1], source_i.valid) \n wire winner : UInt<1>[2] \n connect winner[0], _winner_T \n connect winner[1], _winner_T_1 \n node prefixOR_1 = or(UInt<1>(0h0), winner[0]) \n node _prefixOR_T = or(prefixOR_1, winner[1]) \n node _T_2 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_3 = eq(winner[0], UInt<1>(0h0)) \n node _T_4 = or(_T_2, _T_3) \n node _T_5 = eq(prefixOR_1, UInt<1>(0h0)) \n node _T_6 = eq(winner[1], UInt<1>(0h0)) \n node _T_7 = or(_T_5, _T_6) \n node _T_8 = and(_T_4, _T_7) \n node _T_9 = asUInt(reset) \n node _T_10 = eq(_T_9, UInt<1>(0h0)) \n when _T_10 : \n node _T_11 = eq(_T_8, UInt<1>(0h0)) \n when _T_11 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\\n\") : printf \n assert(clock, _T_8, UInt<1>(0h1), \"\") : assert \n node _T_12 = or(source_c.valid, source_i.valid) \n node _T_13 = eq(_T_12, UInt<1>(0h0)) \n node _T_14 = or(winner[0], winner[1]) \n node _T_15 = or(_T_13, _T_14) \n node _T_16 = asUInt(reset) \n node _T_17 = eq(_T_16, UInt<1>(0h0)) \n when _T_17 : \n node _T_18 = eq(_T_15, UInt<1>(0h0)) \n when _T_18 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\\n\") : printf_1 \n assert(clock, _T_15, UInt<1>(0h1), \"\") : assert_1 \n node maskedBeats_0 = mux(winner[0], UInt<1>(0h0), UInt<1>(0h0)) \n node maskedBeats_1 = mux(winner[1], _T_1, UInt<1>(0h0)) \n node initBeats = or(maskedBeats_0, maskedBeats_1) \n node _beatsLeft_T = and(nodeOut.a.ready, nodeOut.a.valid) \n node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) \n node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) \n node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) \n connect beatsLeft, _beatsLeft_T_3 \n wire _state_WIRE : UInt<1>[2] \n connect _state_WIRE[0], UInt<1>(0h0) \n connect _state_WIRE[1], UInt<1>(0h0) \n regreset state : UInt<1>[2], clock, reset, _state_WIRE \n node muxState = mux(idle, winner, state) \n connect state, muxState \n node allowed = mux(idle, readys, state) \n node _source_c_ready_T = and(nodeOut.a.ready, allowed[0]) \n connect source_c.ready, _source_c_ready_T \n node _source_i_ready_T = and(nodeOut.a.ready, allowed[1]) \n connect source_i.ready, _source_i_ready_T \n node _nodeOut_a_valid_T = or(source_c.valid, source_i.valid) \n node _nodeOut_a_valid_T_1 = mux(state[0], source_c.valid, UInt<1>(0h0)) \n node _nodeOut_a_valid_T_2 = mux(state[1], source_i.valid, UInt<1>(0h0)) \n node _nodeOut_a_valid_T_3 = or(_nodeOut_a_valid_T_1, _nodeOut_a_valid_T_2) \n wire _nodeOut_a_valid_WIRE : UInt<1> \n connect _nodeOut_a_valid_WIRE, _nodeOut_a_valid_T_3 \n node _nodeOut_a_valid_T_4 = mux(idle, _nodeOut_a_valid_T, _nodeOut_a_valid_WIRE) \n connect nodeOut.a.valid, _nodeOut_a_valid_T_4 \n wire _nodeOut_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} \n node _nodeOut_a_bits_T = mux(muxState[0], source_c.bits.corrupt, UInt<1>(0h0)) \n node _nodeOut_a_bits_T_1 = mux(muxState[1], source_i.bits.corrupt, UInt<1>(0h0)) \n node _nodeOut_a_bits_T_2 = or(_nodeOut_a_bits_T, _nodeOut_a_bits_T_1) \n wire _nodeOut_a_bits_WIRE_1 : UInt<1> \n connect _nodeOut_a_bits_WIRE_1, _nodeOut_a_bits_T_2 \n connect _nodeOut_a_bits_WIRE.corrupt, _nodeOut_a_bits_WIRE_1 \n node _nodeOut_a_bits_T_3 = mux(muxState[0], source_c.bits.data, UInt<1>(0h0)) \n node _nodeOut_a_bits_T_4 = mux(muxState[1], source_i.bits.data, UInt<1>(0h0)) \n node _nodeOut_a_bits_T_5 = or(_nodeOut_a_bits_T_3, _nodeOut_a_bits_T_4) \n wire _nodeOut_a_bits_WIRE_2 : UInt<64> \n connect _nodeOut_a_bits_WIRE_2, _nodeOut_a_bits_T_5 \n connect _nodeOut_a_bits_WIRE.data, _nodeOut_a_bits_WIRE_2 \n node _nodeOut_a_bits_T_6 = mux(muxState[0], source_c.bits.mask, UInt<1>(0h0)) \n node _nodeOut_a_bits_T_7 = mux(muxState[1], source_i.bits.mask, UInt<1>(0h0)) \n node _nodeOut_a_bits_T_8 = or(_nodeOut_a_bits_T_6, _nodeOut_a_bits_T_7) \n wire _nodeOut_a_bits_WIRE_3 : UInt<8> \n connect _nodeOut_a_bits_WIRE_3, _nodeOut_a_bits_T_8 \n connect _nodeOut_a_bits_WIRE.mask, _nodeOut_a_bits_WIRE_3 \n wire _nodeOut_a_bits_WIRE_4 : { } \n connect _nodeOut_a_bits_WIRE.echo, _nodeOut_a_bits_WIRE_4 \n wire _nodeOut_a_bits_WIRE_5 : { } \n connect _nodeOut_a_bits_WIRE.user, _nodeOut_a_bits_WIRE_5 \n node _nodeOut_a_bits_T_9 = mux(muxState[0], source_c.bits.address, UInt<1>(0h0)) \n node _nodeOut_a_bits_T_10 = mux(muxState[1], source_i.bits.address, UInt<1>(0h0)) \n node _nodeOut_a_bits_T_11 = or(_nodeOut_a_bits_T_9, _nodeOut_a_bits_T_10) \n wire _nodeOut_a_bits_WIRE_6 : UInt<32> \n connect _nodeOut_a_bits_WIRE_6, _nodeOut_a_bits_T_11 \n connect _nodeOut_a_bits_WIRE.address, _nodeOut_a_bits_WIRE_6 \n node _nodeOut_a_bits_T_12 = mux(muxState[0], source_c.bits.source, UInt<1>(0h0)) \n node _nodeOut_a_bits_T_13 = mux(muxState[1], source_i.bits.source, UInt<1>(0h0)) \n node _nodeOut_a_bits_T_14 = or(_nodeOut_a_bits_T_12, _nodeOut_a_bits_T_13) \n wire _nodeOut_a_bits_WIRE_7 : UInt<7> \n connect _nodeOut_a_bits_WIRE_7, _nodeOut_a_bits_T_14 \n connect _nodeOut_a_bits_WIRE.source, _nodeOut_a_bits_WIRE_7 \n node _nodeOut_a_bits_T_15 = mux(muxState[0], source_c.bits.size, UInt<1>(0h0)) \n node _nodeOut_a_bits_T_16 = mux(muxState[1], source_i.bits.size, UInt<1>(0h0)) \n node _nodeOut_a_bits_T_17 = or(_nodeOut_a_bits_T_15, _nodeOut_a_bits_T_16) \n wire _nodeOut_a_bits_WIRE_8 : UInt<4> \n connect _nodeOut_a_bits_WIRE_8, _nodeOut_a_bits_T_17 \n connect _nodeOut_a_bits_WIRE.size, _nodeOut_a_bits_WIRE_8 \n node _nodeOut_a_bits_T_18 = mux(muxState[0], source_c.bits.param, UInt<1>(0h0)) \n node _nodeOut_a_bits_T_19 = mux(muxState[1], source_i.bits.param, UInt<1>(0h0)) \n node _nodeOut_a_bits_T_20 = or(_nodeOut_a_bits_T_18, _nodeOut_a_bits_T_19) \n wire _nodeOut_a_bits_WIRE_9 : UInt<3> \n connect _nodeOut_a_bits_WIRE_9, _nodeOut_a_bits_T_20 \n connect _nodeOut_a_bits_WIRE.param, _nodeOut_a_bits_WIRE_9 \n node _nodeOut_a_bits_T_21 = mux(muxState[0], source_c.bits.opcode, UInt<1>(0h0)) \n node _nodeOut_a_bits_T_22 = mux(muxState[1], source_i.bits.opcode, UInt<1>(0h0)) \n node _nodeOut_a_bits_T_23 = or(_nodeOut_a_bits_T_21, _nodeOut_a_bits_T_22) \n wire _nodeOut_a_bits_WIRE_10 : UInt<3> \n connect _nodeOut_a_bits_WIRE_10, _nodeOut_a_bits_T_23 \n connect _nodeOut_a_bits_WIRE.opcode, _nodeOut_a_bits_WIRE_10 \n connect nodeOut.a.bits.corrupt, _nodeOut_a_bits_WIRE.corrupt \n connect nodeOut.a.bits.data, _nodeOut_a_bits_WIRE.data \n connect nodeOut.a.bits.mask, _nodeOut_a_bits_WIRE.mask \n connect nodeOut.a.bits.address, _nodeOut_a_bits_WIRE.address \n connect nodeOut.a.bits.source, _nodeOut_a_bits_WIRE.source \n connect nodeOut.a.bits.size, _nodeOut_a_bits_WIRE.size \n connect nodeOut.a.bits.param, _nodeOut_a_bits_WIRE.param \n connect nodeOut.a.bits.opcode, _nodeOut_a_bits_WIRE.opcode \n node _T_19 = and(source_i.ready, source_i.valid) \n node _T_20 = eq(a_isSupported, UInt<1>(0h0)) \n node _T_21 = and(_T_19, _T_20) \n when _T_21 : \n when a_cam_sel_free_0 : \n connect cam_a[0].fifoId, UInt<1>(0h0) \n connect cam_a[0].bits, nodeIn.a.bits \n node _cam_a_0_lut_T = bits(nodeIn.a.bits.param, 1, 0) \n node _cam_a_0_lut_T_1 = eq(UInt<3>(0h1), _cam_a_0_lut_T) \n node _cam_a_0_lut_T_2 = mux(_cam_a_0_lut_T_1, UInt<4>(0he), UInt<4>(0h8)) \n node _cam_a_0_lut_T_3 = eq(UInt<3>(0h0), _cam_a_0_lut_T) \n node _cam_a_0_lut_T_4 = mux(_cam_a_0_lut_T_3, UInt<3>(0h6), _cam_a_0_lut_T_2) \n node _cam_a_0_lut_T_5 = eq(UInt<3>(0h3), _cam_a_0_lut_T) \n node _cam_a_0_lut_T_6 = mux(_cam_a_0_lut_T_5, UInt<4>(0hc), _cam_a_0_lut_T_4) \n connect cam_a[0].lut, _cam_a_0_lut_T_6 \n when a_cam_sel_free_0 : \n connect cam_s[0].state, UInt<2>(0h3) \n node _T_22 = and(source_c.ready, source_c.valid) \n when _T_22 : \n when a_cam_sel_put_0 : \n connect cam_s[0].state, UInt<1>(0h1) \n node _d_first_T = and(nodeOut.d.ready, nodeOut.d.valid) \n node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), nodeOut.d.bits.size) \n node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) \n node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) \n node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) \n node d_first_beats1_opdata = bits(nodeOut.d.bits.opcode, 0, 0) \n node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) \n regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) \n node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) \n node d_first_counter1 = tail(_d_first_counter1_T, 1) \n node d_first = eq(d_first_counter, UInt<1>(0h0)) \n node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) \n node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) \n node d_first_last = or(_d_first_last_T, _d_first_last_T_1) \n node d_first_done = and(d_first_last, _d_first_T) \n node _d_first_count_T = not(d_first_counter1) \n node d_first_count = and(d_first_beats1, _d_first_count_T) \n when _d_first_T : \n node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) \n connect d_first_counter, _d_first_counter_T \n node d_cam_sel_raw_0 = eq(cam_a[0].bits.source, nodeIn.d.bits.source) \n node d_cam_sel_match_0 = and(d_cam_sel_raw_0, cam_dmatch_0) \n node d_cam_sel_0 = mux(UInt<1>(0h0), a_cam_sel_free_0, d_cam_sel_match_0) \n node d_cam_sel_any = or(UInt<1>(0h0), d_cam_sel_match_0) \n node d_ackd = eq(nodeOut.d.bits.opcode, UInt<1>(0h1)) \n node d_ack = eq(nodeOut.d.bits.opcode, UInt<1>(0h0)) \n node _T_23 = and(nodeOut.d.ready, nodeOut.d.valid) \n node _T_24 = and(_T_23, d_first) \n when _T_24 : \n node _T_25 = and(d_cam_sel_0, d_ackd) \n when _T_25 : \n connect cam_d[0].data, nodeOut.d.bits.data \n connect cam_d[0].denied, nodeOut.d.bits.denied \n connect cam_d[0].corrupt, nodeOut.d.bits.corrupt \n when d_cam_sel_0 : \n node _cam_s_0_state_T = mux(d_ackd, UInt<2>(0h2), UInt<1>(0h0)) \n connect cam_s[0].state, _cam_s_0_state_T \n node _d_drop_T = and(d_first, d_ackd) \n node d_drop = and(_d_drop_T, d_cam_sel_any) \n node _d_replace_T = and(d_first, d_ack) \n node d_replace = and(_d_replace_T, d_cam_sel_match_0) \n node _nodeIn_d_valid_T = eq(d_drop, UInt<1>(0h0)) \n node _nodeIn_d_valid_T_1 = and(nodeOut.d.valid, _nodeIn_d_valid_T) \n connect nodeIn.d.valid, _nodeIn_d_valid_T_1 \n node _nodeOut_d_ready_T = or(nodeIn.d.ready, d_drop) \n connect nodeOut.d.ready, _nodeOut_d_ready_T \n connect nodeIn.d.bits.corrupt, nodeOut.d.bits.corrupt \n connect nodeIn.d.bits.data, nodeOut.d.bits.data \n connect nodeIn.d.bits.denied, nodeOut.d.bits.denied \n connect nodeIn.d.bits.sink, nodeOut.d.bits.sink \n connect nodeIn.d.bits.source, nodeOut.d.bits.source \n connect nodeIn.d.bits.size, nodeOut.d.bits.size \n connect nodeIn.d.bits.param, nodeOut.d.bits.param \n connect nodeIn.d.bits.opcode, nodeOut.d.bits.opcode \n when d_replace : \n connect nodeIn.d.bits.opcode, UInt<1>(0h1) \n connect nodeIn.d.bits.data, cam_d[0].data \n node _nodeIn_d_bits_corrupt_T = or(cam_d[0].corrupt, nodeOut.d.bits.denied) \n connect nodeIn.d.bits.corrupt, _nodeIn_d_bits_corrupt_T \n node _nodeIn_d_bits_denied_T = or(cam_d[0].denied, nodeOut.d.bits.denied) \n connect nodeIn.d.bits.denied, _nodeIn_d_bits_denied_T \n wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE.bits.corrupt, UInt<1>(0h0) \n connect _WIRE.bits.data, UInt<64>(0h0) \n connect _WIRE.bits.mask, UInt<8>(0h0) \n connect _WIRE.bits.address, UInt<32>(0h0) \n connect _WIRE.bits.source, UInt<7>(0h0) \n connect _WIRE.bits.size, UInt<4>(0h0) \n connect _WIRE.bits.param, UInt<2>(0h0) \n connect _WIRE.bits.opcode, UInt<3>(0h0) \n connect _WIRE.valid, UInt<1>(0h0) \n connect _WIRE.ready, UInt<1>(0h0) \n wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_1.bits, _WIRE.bits \n connect _WIRE_1.valid, _WIRE.valid \n connect _WIRE_1.ready, _WIRE.ready \n connect _WIRE_1.valid, UInt<1>(0h0) \n wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_2.bits.data, UInt<64>(0h0) \n connect _WIRE_2.bits.address, UInt<32>(0h0) \n connect _WIRE_2.bits.source, UInt<7>(0h0) \n connect _WIRE_2.bits.size, UInt<4>(0h0) \n connect _WIRE_2.bits.param, UInt<3>(0h0) \n connect _WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _WIRE_2.valid, UInt<1>(0h0) \n connect _WIRE_2.ready, UInt<1>(0h0) \n wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_3.bits, _WIRE_2.bits \n connect _WIRE_3.valid, _WIRE_2.valid \n connect _WIRE_3.ready, _WIRE_2.ready \n connect _WIRE_3.ready, UInt<1>(0h1) \n wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_4.bits.sink, UInt<1>(0h0) \n connect _WIRE_4.valid, UInt<1>(0h0) \n connect _WIRE_4.ready, UInt<1>(0h0) \n wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_5.bits, _WIRE_4.bits \n connect _WIRE_5.valid, _WIRE_4.valid \n connect _WIRE_5.ready, _WIRE_4.ready \n connect _WIRE_5.ready, UInt<1>(0h1) \n wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_6.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_6.bits.data, UInt<64>(0h0) \n connect _WIRE_6.bits.mask, UInt<8>(0h0) \n connect _WIRE_6.bits.address, UInt<32>(0h0) \n connect _WIRE_6.bits.source, UInt<7>(0h0) \n connect _WIRE_6.bits.size, UInt<4>(0h0) \n connect _WIRE_6.bits.param, UInt<2>(0h0) \n connect _WIRE_6.bits.opcode, UInt<3>(0h0) \n connect _WIRE_6.valid, UInt<1>(0h0) \n connect _WIRE_6.ready, UInt<1>(0h0) \n wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_7.bits, _WIRE_6.bits \n connect _WIRE_7.valid, _WIRE_6.valid \n connect _WIRE_7.ready, _WIRE_6.ready \n connect _WIRE_7.ready, UInt<1>(0h1) \n wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_8.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_8.bits.data, UInt<64>(0h0) \n connect _WIRE_8.bits.address, UInt<32>(0h0) \n connect _WIRE_8.bits.source, UInt<7>(0h0) \n connect _WIRE_8.bits.size, UInt<4>(0h0) \n connect _WIRE_8.bits.param, UInt<3>(0h0) \n connect _WIRE_8.bits.opcode, UInt<3>(0h0) \n connect _WIRE_8.valid, UInt<1>(0h0) \n connect _WIRE_8.ready, UInt<1>(0h0) \n wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_9.bits, _WIRE_8.bits \n connect _WIRE_9.valid, _WIRE_8.valid \n connect _WIRE_9.ready, _WIRE_8.ready \n connect _WIRE_9.valid, UInt<1>(0h0) \n wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_10.bits.sink, UInt<1>(0h0) \n connect _WIRE_10.valid, UInt<1>(0h0) \n connect _WIRE_10.ready, UInt<1>(0h0) \n wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_11.bits, _WIRE_10.bits \n connect _WIRE_11.valid, _WIRE_10.valid \n connect _WIRE_11.ready, _WIRE_10.ready \n connect _WIRE_11.valid, UInt<1>(0h0) \n\n\n extmodule plusarg_reader_38 : \n output out : UInt<32>\n\n defname = plusarg_reader\n\n parameter DEFAULT = 0\n\n parameter FORMAT = \"tilelink_timeout=%d\"\n\n parameter WIDTH = 32\n\n\n\n extmodule plusarg_reader_39 : \n output out : UInt<32>\n\n defname = plusarg_reader\n\n parameter DEFAULT = 0\n\n parameter FORMAT = \"tilelink_timeout=%d\"\n\n parameter WIDTH = 32"},"response":{"kind":"string","value":"module TLAtomicAutomata_cbus(\t// @[AtomicAutomata.scala:36:9]\n input clock,\t// @[AtomicAutomata.scala:36:9]\n input reset,\t// @[AtomicAutomata.scala:36:9]\n output auto_in_a_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_in_a_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_in_a_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_in_a_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_in_a_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [6:0] auto_in_a_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_in_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n input [7:0] auto_in_a_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_in_a_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_in_a_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input auto_in_d_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_in_d_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_in_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_in_d_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_in_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [6:0] auto_in_d_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output auto_in_d_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n output auto_in_d_bits_denied,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_in_d_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_in_d_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_a_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_a_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_a_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_a_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_out_a_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [6:0] auto_out_a_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_out_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n output [7:0] auto_out_a_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_out_a_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_a_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_d_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_d_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_out_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_out_d_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_out_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [6:0] auto_out_d_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_d_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_d_bits_denied,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_out_d_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_d_bits_corrupt\t// @[LazyModuleImp.scala:107:25]\n);\n\n wire auto_in_a_valid_0 = auto_in_a_valid;\t// @[AtomicAutomata.scala:36:9]\n wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode;\t// @[AtomicAutomata.scala:36:9]\n wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param;\t// @[AtomicAutomata.scala:36:9]\n wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size;\t// @[AtomicAutomata.scala:36:9]\n wire [6:0] auto_in_a_bits_source_0 = auto_in_a_bits_source;\t// @[AtomicAutomata.scala:36:9]\n wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address;\t// @[AtomicAutomata.scala:36:9]\n wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask;\t// @[AtomicAutomata.scala:36:9]\n wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data;\t// @[AtomicAutomata.scala:36:9]\n wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt;\t// @[AtomicAutomata.scala:36:9]\n wire auto_in_d_ready_0 = auto_in_d_ready;\t// @[AtomicAutomata.scala:36:9]\n wire auto_out_a_ready_0 = auto_out_a_ready;\t// @[AtomicAutomata.scala:36:9]\n wire auto_out_d_valid_0 = auto_out_d_valid;\t// @[AtomicAutomata.scala:36:9]\n wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode;\t// @[AtomicAutomata.scala:36:9]\n wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param;\t// @[AtomicAutomata.scala:36:9]\n wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size;\t// @[AtomicAutomata.scala:36:9]\n wire [6:0] auto_out_d_bits_source_0 = auto_out_d_bits_source;\t// @[AtomicAutomata.scala:36:9]\n wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink;\t// @[AtomicAutomata.scala:36:9]\n wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied;\t// @[AtomicAutomata.scala:36:9]\n wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data;\t// @[AtomicAutomata.scala:36:9]\n wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt;\t// @[AtomicAutomata.scala:36:9]\n wire _a_canLogical_T = 1'h1;\t// @[Parameters.scala:92:28]\n wire _a_canArithmetic_T = 1'h1;\t// @[Parameters.scala:92:28]\n wire _a_cam_sel_put_T = 1'h1;\t// @[AtomicAutomata.scala:103:83]\n wire _a_fifoId_T_4 = 1'h1;\t// @[Parameters.scala:137:59]\n wire _a_cam_busy_T = 1'h1;\t// @[AtomicAutomata.scala:111:60]\n wire _a_cam_sel_free_T = 1'h1;\t// @[AtomicAutomata.scala:116:85]\n wire _source_c_bits_legal_T = 1'h1;\t// @[Parameters.scala:92:28]\n wire _source_c_bits_legal_T_10 = 1'h1;\t// @[Parameters.scala:92:28]\n wire _a_canLogical_T_16 = 1'h0;\t// @[Parameters.scala:684:29]\n wire _a_canLogical_T_46 = 1'h0;\t// @[Parameters.scala:684:54]\n wire _a_canArithmetic_T_16 = 1'h0;\t// @[Parameters.scala:684:29]\n wire _a_canArithmetic_T_46 = 1'h0;\t// @[Parameters.scala:684:54]\n wire _source_c_bits_legal_T_44 = 1'h0;\t// @[Parameters.scala:684:29]\n wire _source_c_bits_legal_T_50 = 1'h0;\t// @[Parameters.scala:684:54]\n wire maskedBeats_0 = 1'h0;\t// @[Arbiter.scala:82:69]\n wire _state_WIRE_0 = 1'h0;\t// @[Arbiter.scala:88:34]\n wire _state_WIRE_1 = 1'h0;\t// @[Arbiter.scala:88:34]\n wire [2:0] source_c_bits_opcode = 3'h0;\t// @[AtomicAutomata.scala:165:28]\n wire [2:0] source_c_bits_param = 3'h0;\t// @[AtomicAutomata.scala:165:28]\n wire [2:0] source_c_bits_a_opcode = 3'h0;\t// @[Edges.scala:480:17]\n wire [2:0] source_c_bits_a_param = 3'h0;\t// @[Edges.scala:480:17]\n wire [2:0] _nodeOut_a_bits_T_18 = 3'h0;\t// @[Mux.scala:30:73]\n wire [2:0] _nodeOut_a_bits_T_21 = 3'h0;\t// @[Mux.scala:30:73]\n wire [32:0] _a_fifoId_T_2 = 33'h0;\t// @[Parameters.scala:137:46]\n wire [32:0] _a_fifoId_T_3 = 33'h0;\t// @[Parameters.scala:137:46]\n wire [1:0] initval_state = 2'h0;\t// @[AtomicAutomata.scala:80:27]\n wire [1:0] _cam_s_WIRE_0_state = 2'h0;\t// @[AtomicAutomata.scala:82:50]\n wire nodeIn_a_ready;\t// @[MixedNode.scala:551:17]\n wire nodeIn_a_valid = auto_in_a_valid_0;\t// @[AtomicAutomata.scala:36:9]\n wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0;\t// @[AtomicAutomata.scala:36:9]\n wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0;\t// @[AtomicAutomata.scala:36:9]\n wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0;\t// @[AtomicAutomata.scala:36:9]\n wire [6:0] nodeIn_a_bits_source = auto_in_a_bits_source_0;\t// @[AtomicAutomata.scala:36:9]\n wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0;\t// @[AtomicAutomata.scala:36:9]\n wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0;\t// @[AtomicAutomata.scala:36:9]\n wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0;\t// @[AtomicAutomata.scala:36:9]\n wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0;\t// @[AtomicAutomata.scala:36:9]\n wire nodeIn_d_ready = auto_in_d_ready_0;\t// @[AtomicAutomata.scala:36:9]\n wire nodeIn_d_valid;\t// @[MixedNode.scala:551:17]\n wire [2:0] nodeIn_d_bits_opcode;\t// @[MixedNode.scala:551:17]\n wire [1:0] nodeIn_d_bits_param;\t// @[MixedNode.scala:551:17]\n wire [3:0] nodeIn_d_bits_size;\t// @[MixedNode.scala:551:17]\n wire [6:0] nodeIn_d_bits_source;\t// @[MixedNode.scala:551:17]\n wire nodeIn_d_bits_sink;\t// @[MixedNode.scala:551:17]\n wire nodeIn_d_bits_denied;\t// @[MixedNode.scala:551:17]\n wire [63:0] nodeIn_d_bits_data;\t// @[MixedNode.scala:551:17]\n wire nodeIn_d_bits_corrupt;\t// @[MixedNode.scala:551:17]\n wire nodeOut_a_ready = auto_out_a_ready_0;\t// @[AtomicAutomata.scala:36:9]\n wire nodeOut_a_valid;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_a_bits_opcode;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_a_bits_param;\t// @[MixedNode.scala:542:17]\n wire [3:0] nodeOut_a_bits_size;\t// @[MixedNode.scala:542:17]\n wire [6:0] nodeOut_a_bits_source;\t// @[MixedNode.scala:542:17]\n wire [31:0] nodeOut_a_bits_address;\t// @[MixedNode.scala:542:17]\n wire [7:0] nodeOut_a_bits_mask;\t// @[MixedNode.scala:542:17]\n wire [63:0] nodeOut_a_bits_data;\t// @[MixedNode.scala:542:17]\n wire nodeOut_a_bits_corrupt;\t// @[MixedNode.scala:542:17]\n wire nodeOut_d_ready;\t// @[MixedNode.scala:542:17]\n wire nodeOut_d_valid = auto_out_d_valid_0;\t// @[AtomicAutomata.scala:36:9]\n wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0;\t// @[AtomicAutomata.scala:36:9]\n wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0;\t// @[AtomicAutomata.scala:36:9]\n wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0;\t// @[AtomicAutomata.scala:36:9]\n wire [6:0] nodeOut_d_bits_source = auto_out_d_bits_source_0;\t// @[AtomicAutomata.scala:36:9]\n wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0;\t// @[AtomicAutomata.scala:36:9]\n wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0;\t// @[AtomicAutomata.scala:36:9]\n wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0;\t// @[AtomicAutomata.scala:36:9]\n wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0;\t// @[AtomicAutomata.scala:36:9]\n wire auto_in_a_ready_0;\t// @[AtomicAutomata.scala:36:9]\n wire [2:0] auto_in_d_bits_opcode_0;\t// @[AtomicAutomata.scala:36:9]\n wire [1:0] auto_in_d_bits_param_0;\t// @[AtomicAutomata.scala:36:9]\n wire [3:0] auto_in_d_bits_size_0;\t// @[AtomicAutomata.scala:36:9]\n wire [6:0] auto_in_d_bits_source_0;\t// @[AtomicAutomata.scala:36:9]\n wire auto_in_d_bits_sink_0;\t// @[AtomicAutomata.scala:36:9]\n wire auto_in_d_bits_denied_0;\t// @[AtomicAutomata.scala:36:9]\n wire [63:0] auto_in_d_bits_data_0;\t// @[AtomicAutomata.scala:36:9]\n wire auto_in_d_bits_corrupt_0;\t// @[AtomicAutomata.scala:36:9]\n wire auto_in_d_valid_0;\t// @[AtomicAutomata.scala:36:9]\n wire [2:0] auto_out_a_bits_opcode_0;\t// @[AtomicAutomata.scala:36:9]\n wire [2:0] auto_out_a_bits_param_0;\t// @[AtomicAutomata.scala:36:9]\n wire [3:0] auto_out_a_bits_size_0;\t// @[AtomicAutomata.scala:36:9]\n wire [6:0] auto_out_a_bits_source_0;\t// @[AtomicAutomata.scala:36:9]\n wire [31:0] auto_out_a_bits_address_0;\t// @[AtomicAutomata.scala:36:9]\n wire [7:0] auto_out_a_bits_mask_0;\t// @[AtomicAutomata.scala:36:9]\n wire [63:0] auto_out_a_bits_data_0;\t// @[AtomicAutomata.scala:36:9]\n wire auto_out_a_bits_corrupt_0;\t// @[AtomicAutomata.scala:36:9]\n wire auto_out_a_valid_0;\t// @[AtomicAutomata.scala:36:9]\n wire auto_out_d_ready_0;\t// @[AtomicAutomata.scala:36:9]\n wire _nodeIn_a_ready_T;\t// @[AtomicAutomata.scala:156:38]\n assign auto_in_a_ready_0 = nodeIn_a_ready;\t// @[AtomicAutomata.scala:36:9]\n wire [3:0] source_i_bits_size = nodeIn_a_bits_size;\t// @[AtomicAutomata.scala:154:28]\n wire [6:0] source_i_bits_source = nodeIn_a_bits_source;\t// @[AtomicAutomata.scala:154:28]\n wire [31:0] _a_canLogical_T_17 = nodeIn_a_bits_address;\t// @[Parameters.scala:137:31]\n wire [31:0] _a_canArithmetic_T_17 = nodeIn_a_bits_address;\t// @[Parameters.scala:137:31]\n wire [31:0] _a_fifoId_T = nodeIn_a_bits_address;\t// @[Parameters.scala:137:31]\n wire [31:0] source_i_bits_address = nodeIn_a_bits_address;\t// @[AtomicAutomata.scala:154:28]\n wire [7:0] source_i_bits_mask = nodeIn_a_bits_mask;\t// @[AtomicAutomata.scala:154:28]\n wire [63:0] source_i_bits_data = nodeIn_a_bits_data;\t// @[AtomicAutomata.scala:154:28]\n wire source_i_bits_corrupt = nodeIn_a_bits_corrupt;\t// @[AtomicAutomata.scala:154:28]\n wire _nodeIn_d_valid_T_1;\t// @[AtomicAutomata.scala:241:35]\n assign auto_in_d_valid_0 = nodeIn_d_valid;\t// @[AtomicAutomata.scala:36:9]\n assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode;\t// @[AtomicAutomata.scala:36:9]\n assign auto_in_d_bits_param_0 = nodeIn_d_bits_param;\t// @[AtomicAutomata.scala:36:9]\n assign auto_in_d_bits_size_0 = nodeIn_d_bits_size;\t// @[AtomicAutomata.scala:36:9]\n assign auto_in_d_bits_source_0 = nodeIn_d_bits_source;\t// @[AtomicAutomata.scala:36:9]\n assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink;\t// @[AtomicAutomata.scala:36:9]\n assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied;\t// @[AtomicAutomata.scala:36:9]\n assign auto_in_d_bits_data_0 = nodeIn_d_bits_data;\t// @[AtomicAutomata.scala:36:9]\n assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt;\t// @[AtomicAutomata.scala:36:9]\n wire _nodeOut_a_valid_T_4;\t// @[Arbiter.scala:96:24]\n assign auto_out_a_valid_0 = nodeOut_a_valid;\t// @[AtomicAutomata.scala:36:9]\n wire [2:0] _nodeOut_a_bits_WIRE_opcode;\t// @[Mux.scala:30:73]\n assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode;\t// @[AtomicAutomata.scala:36:9]\n wire [2:0] _nodeOut_a_bits_WIRE_param;\t// @[Mux.scala:30:73]\n assign auto_out_a_bits_param_0 = nodeOut_a_bits_param;\t// @[AtomicAutomata.scala:36:9]\n wire [3:0] _nodeOut_a_bits_WIRE_size;\t// @[Mux.scala:30:73]\n assign auto_out_a_bits_size_0 = nodeOut_a_bits_size;\t// @[AtomicAutomata.scala:36:9]\n wire [6:0] _nodeOut_a_bits_WIRE_source;\t// @[Mux.scala:30:73]\n assign auto_out_a_bits_source_0 = nodeOut_a_bits_source;\t// @[AtomicAutomata.scala:36:9]\n wire [31:0] _nodeOut_a_bits_WIRE_address;\t// @[Mux.scala:30:73]\n assign auto_out_a_bits_address_0 = nodeOut_a_bits_address;\t// @[AtomicAutomata.scala:36:9]\n wire [7:0] _nodeOut_a_bits_WIRE_mask;\t// @[Mux.scala:30:73]\n assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask;\t// @[AtomicAutomata.scala:36:9]\n wire [63:0] _nodeOut_a_bits_WIRE_data;\t// @[Mux.scala:30:73]\n assign auto_out_a_bits_data_0 = nodeOut_a_bits_data;\t// @[AtomicAutomata.scala:36:9]\n wire _nodeOut_a_bits_WIRE_corrupt;\t// @[Mux.scala:30:73]\n assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt;\t// @[AtomicAutomata.scala:36:9]\n wire _nodeOut_d_ready_T;\t// @[AtomicAutomata.scala:242:35]\n assign auto_out_d_ready_0 = nodeOut_d_ready;\t// @[AtomicAutomata.scala:36:9]\n assign nodeIn_d_bits_param = nodeOut_d_bits_param;\t// @[MixedNode.scala:542:17, :551:17]\n assign nodeIn_d_bits_size = nodeOut_d_bits_size;\t// @[MixedNode.scala:542:17, :551:17]\n assign nodeIn_d_bits_source = nodeOut_d_bits_source;\t// @[MixedNode.scala:542:17, :551:17]\n assign nodeIn_d_bits_sink = nodeOut_d_bits_sink;\t// @[MixedNode.scala:542:17, :551:17]\n reg [1:0] cam_s_0_state;\t// @[AtomicAutomata.scala:82:28]\n reg [2:0] cam_a_0_bits_opcode;\t// @[AtomicAutomata.scala:83:24]\n reg [2:0] cam_a_0_bits_param;\t// @[AtomicAutomata.scala:83:24]\n reg [3:0] cam_a_0_bits_size;\t// @[AtomicAutomata.scala:83:24]\n wire [3:0] source_c_bits_a_size = cam_a_0_bits_size;\t// @[Edges.scala:480:17]\n wire [3:0] _source_c_bits_a_mask_sizeOH_T = cam_a_0_bits_size;\t// @[Misc.scala:202:34]\n reg [6:0] cam_a_0_bits_source;\t// @[AtomicAutomata.scala:83:24]\n wire [6:0] source_c_bits_a_source = cam_a_0_bits_source;\t// @[Edges.scala:480:17]\n reg [31:0] cam_a_0_bits_address;\t// @[AtomicAutomata.scala:83:24]\n wire [31:0] _source_c_bits_legal_T_14 = cam_a_0_bits_address;\t// @[AtomicAutomata.scala:83:24]\n wire [31:0] source_c_bits_a_address = cam_a_0_bits_address;\t// @[Edges.scala:480:17]\n reg [7:0] cam_a_0_bits_mask;\t// @[AtomicAutomata.scala:83:24]\n reg [63:0] cam_a_0_bits_data;\t// @[AtomicAutomata.scala:83:24]\n reg cam_a_0_bits_corrupt;\t// @[AtomicAutomata.scala:83:24]\n reg [3:0] cam_a_0_lut;\t// @[AtomicAutomata.scala:83:24]\n reg [63:0] cam_d_0_data;\t// @[AtomicAutomata.scala:84:24]\n reg cam_d_0_denied;\t// @[AtomicAutomata.scala:84:24]\n reg cam_d_0_corrupt;\t// @[AtomicAutomata.scala:84:24]\n wire cam_free_0 = ~(|cam_s_0_state);\t// @[AtomicAutomata.scala:82:28, :86:44]\n wire _a_cam_por_free_T = cam_free_0;\t// @[AtomicAutomata.scala:86:44, :115:58]\n wire a_cam_sel_free_0 = cam_free_0;\t// @[AtomicAutomata.scala:86:44, :116:82]\n wire _GEN = cam_s_0_state == 2'h2;\t// @[AtomicAutomata.scala:82:28, :87:44]\n wire cam_amo_0;\t// @[AtomicAutomata.scala:87:44]\n assign cam_amo_0 = _GEN;\t// @[AtomicAutomata.scala:87:44]\n wire _cam_abusy_T_1;\t// @[AtomicAutomata.scala:88:68]\n assign _cam_abusy_T_1 = _GEN;\t// @[AtomicAutomata.scala:87:44, :88:68]\n wire _a_cam_por_put_T = cam_amo_0;\t// @[AtomicAutomata.scala:87:44, :102:56]\n wire a_cam_sel_put_0 = cam_amo_0;\t// @[AtomicAutomata.scala:87:44, :103:80]\n wire source_c_valid = cam_amo_0;\t// @[AtomicAutomata.scala:87:44, :165:28]\n wire _cam_abusy_T = &cam_s_0_state;\t// @[AtomicAutomata.scala:82:28, :88:49]\n wire cam_abusy_0 = _cam_abusy_T | _cam_abusy_T_1;\t// @[AtomicAutomata.scala:88:{49,57,68}]\n wire a_cam_busy = cam_abusy_0;\t// @[AtomicAutomata.scala:88:57, :111:96]\n wire cam_dmatch_0 = |cam_s_0_state;\t// @[AtomicAutomata.scala:82:28, :86:44, :89:49]\n wire _GEN_0 = nodeIn_a_bits_size < 4'h4;\t// @[Parameters.scala:92:38]\n wire _a_canLogical_T_1;\t// @[Parameters.scala:92:38]\n assign _a_canLogical_T_1 = _GEN_0;\t// @[Parameters.scala:92:38]\n wire _a_canArithmetic_T_1;\t// @[Parameters.scala:92:38]\n assign _a_canArithmetic_T_1 = _GEN_0;\t// @[Parameters.scala:92:38]\n wire _a_canLogical_T_2 = _a_canLogical_T_1;\t// @[Parameters.scala:92:{33,38}]\n wire _a_canLogical_T_3 = _a_canLogical_T_2;\t// @[Parameters.scala:684:29]\n wire [31:0] _GEN_1 = {nodeIn_a_bits_address[31:13], nodeIn_a_bits_address[12:0] ^ 13'h1000};\t// @[Parameters.scala:137:31]\n wire [31:0] _a_canLogical_T_4;\t// @[Parameters.scala:137:31]\n assign _a_canLogical_T_4 = _GEN_1;\t// @[Parameters.scala:137:31]\n wire [31:0] _a_canArithmetic_T_4;\t// @[Parameters.scala:137:31]\n assign _a_canArithmetic_T_4 = _GEN_1;\t// @[Parameters.scala:137:31]\n wire [32:0] _a_canLogical_T_5 = {1'h0, _a_canLogical_T_4};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _a_canLogical_T_6 = _a_canLogical_T_5 & 33'h9A111000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _a_canLogical_T_7 = _a_canLogical_T_6;\t// @[Parameters.scala:137:46]\n wire _a_canLogical_T_8 = _a_canLogical_T_7 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire [31:0] _GEN_2 = {nodeIn_a_bits_address[31:29], nodeIn_a_bits_address[28:0] ^ 29'h10000000};\t// @[Parameters.scala:137:31]\n wire [31:0] _a_canLogical_T_9;\t// @[Parameters.scala:137:31]\n assign _a_canLogical_T_9 = _GEN_2;\t// @[Parameters.scala:137:31]\n wire [31:0] _a_canArithmetic_T_9;\t// @[Parameters.scala:137:31]\n assign _a_canArithmetic_T_9 = _GEN_2;\t// @[Parameters.scala:137:31]\n wire [32:0] _a_canLogical_T_10 = {1'h0, _a_canLogical_T_9};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _a_canLogical_T_11 = _a_canLogical_T_10 & 33'h9A111000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _a_canLogical_T_12 = _a_canLogical_T_11;\t// @[Parameters.scala:137:46]\n wire _a_canLogical_T_13 = _a_canLogical_T_12 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire _a_canLogical_T_14 = _a_canLogical_T_8 | _a_canLogical_T_13;\t// @[Parameters.scala:685:42]\n wire _a_canLogical_T_15 = _a_canLogical_T_3 & _a_canLogical_T_14;\t// @[Parameters.scala:684:{29,54}, :685:42]\n wire _a_canLogical_T_55 = _a_canLogical_T_15;\t// @[Parameters.scala:684:54, :686:26]\n wire [32:0] _a_canLogical_T_18 = {1'h0, _a_canLogical_T_17};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _a_canLogical_T_19 = _a_canLogical_T_18 & 33'h9A111000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _a_canLogical_T_20 = _a_canLogical_T_19;\t// @[Parameters.scala:137:46]\n wire _a_canLogical_T_21 = _a_canLogical_T_20 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire [31:0] _GEN_3 = {nodeIn_a_bits_address[31:17], nodeIn_a_bits_address[16:0] ^ 17'h10000};\t// @[Parameters.scala:137:31]\n wire [31:0] _a_canLogical_T_22;\t// @[Parameters.scala:137:31]\n assign _a_canLogical_T_22 = _GEN_3;\t// @[Parameters.scala:137:31]\n wire [31:0] _a_canArithmetic_T_22;\t// @[Parameters.scala:137:31]\n assign _a_canArithmetic_T_22 = _GEN_3;\t// @[Parameters.scala:137:31]\n wire [32:0] _a_canLogical_T_23 = {1'h0, _a_canLogical_T_22};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _a_canLogical_T_24 = _a_canLogical_T_23 & 33'h9A110000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _a_canLogical_T_25 = _a_canLogical_T_24;\t// @[Parameters.scala:137:46]\n wire _a_canLogical_T_26 = _a_canLogical_T_25 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire [31:0] _GEN_4 = {nodeIn_a_bits_address[31:21], nodeIn_a_bits_address[20:0] ^ 21'h100000};\t// @[Parameters.scala:137:31]\n wire [31:0] _a_canLogical_T_27;\t// @[Parameters.scala:137:31]\n assign _a_canLogical_T_27 = _GEN_4;\t// @[Parameters.scala:137:31]\n wire [31:0] _a_canArithmetic_T_27;\t// @[Parameters.scala:137:31]\n assign _a_canArithmetic_T_27 = _GEN_4;\t// @[Parameters.scala:137:31]\n wire [32:0] _a_canLogical_T_28 = {1'h0, _a_canLogical_T_27};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _a_canLogical_T_29 = _a_canLogical_T_28 & 33'h9A101000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _a_canLogical_T_30 = _a_canLogical_T_29;\t// @[Parameters.scala:137:46]\n wire _a_canLogical_T_31 = _a_canLogical_T_30 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire [31:0] _GEN_5 = {nodeIn_a_bits_address[31:26], nodeIn_a_bits_address[25:0] ^ 26'h2000000};\t// @[Parameters.scala:137:31]\n wire [31:0] _a_canLogical_T_32;\t// @[Parameters.scala:137:31]\n assign _a_canLogical_T_32 = _GEN_5;\t// @[Parameters.scala:137:31]\n wire [31:0] _a_canArithmetic_T_32;\t// @[Parameters.scala:137:31]\n assign _a_canArithmetic_T_32 = _GEN_5;\t// @[Parameters.scala:137:31]\n wire [32:0] _a_canLogical_T_33 = {1'h0, _a_canLogical_T_32};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _a_canLogical_T_34 = _a_canLogical_T_33 & 33'h9A110000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _a_canLogical_T_35 = _a_canLogical_T_34;\t// @[Parameters.scala:137:46]\n wire _a_canLogical_T_36 = _a_canLogical_T_35 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire [31:0] _GEN_6 = {nodeIn_a_bits_address[31:28], nodeIn_a_bits_address[27:0] ^ 28'h8000000};\t// @[Parameters.scala:137:31]\n wire [31:0] _a_canLogical_T_37;\t// @[Parameters.scala:137:31]\n assign _a_canLogical_T_37 = _GEN_6;\t// @[Parameters.scala:137:31]\n wire [31:0] _a_canArithmetic_T_37;\t// @[Parameters.scala:137:31]\n assign _a_canArithmetic_T_37 = _GEN_6;\t// @[Parameters.scala:137:31]\n wire [32:0] _a_canLogical_T_38 = {1'h0, _a_canLogical_T_37};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _a_canLogical_T_39 = _a_canLogical_T_38 & 33'h98000000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _a_canLogical_T_40 = _a_canLogical_T_39;\t// @[Parameters.scala:137:46]\n wire _a_canLogical_T_41 = _a_canLogical_T_40 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire _a_canLogical_T_42 = _a_canLogical_T_21 | _a_canLogical_T_26;\t// @[Parameters.scala:685:42]\n wire _a_canLogical_T_43 = _a_canLogical_T_42 | _a_canLogical_T_31;\t// @[Parameters.scala:685:42]\n wire _a_canLogical_T_44 = _a_canLogical_T_43 | _a_canLogical_T_36;\t// @[Parameters.scala:685:42]\n wire _a_canLogical_T_45 = _a_canLogical_T_44 | _a_canLogical_T_41;\t// @[Parameters.scala:685:42]\n wire _GEN_7 = nodeIn_a_bits_size == 4'h2;\t// @[Parameters.scala:91:44]\n wire _a_canLogical_T_47;\t// @[Parameters.scala:91:44]\n assign _a_canLogical_T_47 = _GEN_7;\t// @[Parameters.scala:91:44]\n wire _a_canArithmetic_T_47;\t// @[Parameters.scala:91:44]\n assign _a_canArithmetic_T_47 = _GEN_7;\t// @[Parameters.scala:91:44]\n wire _a_canLogical_T_48 = _a_canLogical_T_47;\t// @[Parameters.scala:684:29]\n wire [31:0] _GEN_8 = nodeIn_a_bits_address ^ 32'h80000000;\t// @[Parameters.scala:137:31]\n wire [31:0] _a_canLogical_T_49;\t// @[Parameters.scala:137:31]\n assign _a_canLogical_T_49 = _GEN_8;\t// @[Parameters.scala:137:31]\n wire [31:0] _a_canArithmetic_T_49;\t// @[Parameters.scala:137:31]\n assign _a_canArithmetic_T_49 = _GEN_8;\t// @[Parameters.scala:137:31]\n wire [32:0] _a_canLogical_T_50 = {1'h0, _a_canLogical_T_49};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _a_canLogical_T_51 = _a_canLogical_T_50 & 33'h9A110000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _a_canLogical_T_52 = _a_canLogical_T_51;\t// @[Parameters.scala:137:46]\n wire _a_canLogical_T_53 = _a_canLogical_T_52 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire _a_canLogical_T_54 = _a_canLogical_T_48 & _a_canLogical_T_53;\t// @[Parameters.scala:684:{29,54}]\n wire _a_canLogical_T_56 = _a_canLogical_T_55;\t// @[Parameters.scala:686:26]\n wire _a_canLogical_T_57 = _a_canLogical_T_56 | _a_canLogical_T_54;\t// @[Parameters.scala:684:54, :686:26]\n wire a_canLogical = _a_canLogical_T_57;\t// @[Parameters.scala:686:26]\n wire _a_canArithmetic_T_2 = _a_canArithmetic_T_1;\t// @[Parameters.scala:92:{33,38}]\n wire _a_canArithmetic_T_3 = _a_canArithmetic_T_2;\t// @[Parameters.scala:684:29]\n wire [32:0] _a_canArithmetic_T_5 = {1'h0, _a_canArithmetic_T_4};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _a_canArithmetic_T_6 = _a_canArithmetic_T_5 & 33'h9A111000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _a_canArithmetic_T_7 = _a_canArithmetic_T_6;\t// @[Parameters.scala:137:46]\n wire _a_canArithmetic_T_8 = _a_canArithmetic_T_7 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire [32:0] _a_canArithmetic_T_10 = {1'h0, _a_canArithmetic_T_9};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _a_canArithmetic_T_11 = _a_canArithmetic_T_10 & 33'h9A111000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _a_canArithmetic_T_12 = _a_canArithmetic_T_11;\t// @[Parameters.scala:137:46]\n wire _a_canArithmetic_T_13 = _a_canArithmetic_T_12 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire _a_canArithmetic_T_14 = _a_canArithmetic_T_8 | _a_canArithmetic_T_13;\t// @[Parameters.scala:685:42]\n wire _a_canArithmetic_T_15 = _a_canArithmetic_T_3 & _a_canArithmetic_T_14;\t// @[Parameters.scala:684:{29,54}, :685:42]\n wire _a_canArithmetic_T_55 = _a_canArithmetic_T_15;\t// @[Parameters.scala:684:54, :686:26]\n wire [32:0] _a_canArithmetic_T_18 = {1'h0, _a_canArithmetic_T_17};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _a_canArithmetic_T_19 = _a_canArithmetic_T_18 & 33'h9A111000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _a_canArithmetic_T_20 = _a_canArithmetic_T_19;\t// @[Parameters.scala:137:46]\n wire _a_canArithmetic_T_21 = _a_canArithmetic_T_20 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire [32:0] _a_canArithmetic_T_23 = {1'h0, _a_canArithmetic_T_22};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _a_canArithmetic_T_24 = _a_canArithmetic_T_23 & 33'h9A110000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _a_canArithmetic_T_25 = _a_canArithmetic_T_24;\t// @[Parameters.scala:137:46]\n wire _a_canArithmetic_T_26 = _a_canArithmetic_T_25 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire [32:0] _a_canArithmetic_T_28 = {1'h0, _a_canArithmetic_T_27};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _a_canArithmetic_T_29 = _a_canArithmetic_T_28 & 33'h9A101000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _a_canArithmetic_T_30 = _a_canArithmetic_T_29;\t// @[Parameters.scala:137:46]\n wire _a_canArithmetic_T_31 = _a_canArithmetic_T_30 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire [32:0] _a_canArithmetic_T_33 = {1'h0, _a_canArithmetic_T_32};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _a_canArithmetic_T_34 = _a_canArithmetic_T_33 & 33'h9A110000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _a_canArithmetic_T_35 = _a_canArithmetic_T_34;\t// @[Parameters.scala:137:46]\n wire _a_canArithmetic_T_36 = _a_canArithmetic_T_35 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire [32:0] _a_canArithmetic_T_38 = {1'h0, _a_canArithmetic_T_37};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _a_canArithmetic_T_39 = _a_canArithmetic_T_38 & 33'h98000000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _a_canArithmetic_T_40 = _a_canArithmetic_T_39;\t// @[Parameters.scala:137:46]\n wire _a_canArithmetic_T_41 = _a_canArithmetic_T_40 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire _a_canArithmetic_T_42 = _a_canArithmetic_T_21 | _a_canArithmetic_T_26;\t// @[Parameters.scala:685:42]\n wire _a_canArithmetic_T_43 = _a_canArithmetic_T_42 | _a_canArithmetic_T_31;\t// @[Parameters.scala:685:42]\n wire _a_canArithmetic_T_44 = _a_canArithmetic_T_43 | _a_canArithmetic_T_36;\t// @[Parameters.scala:685:42]\n wire _a_canArithmetic_T_45 = _a_canArithmetic_T_44 | _a_canArithmetic_T_41;\t// @[Parameters.scala:685:42]\n wire _a_canArithmetic_T_48 = _a_canArithmetic_T_47;\t// @[Parameters.scala:684:29]\n wire [32:0] _a_canArithmetic_T_50 = {1'h0, _a_canArithmetic_T_49};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _a_canArithmetic_T_51 = _a_canArithmetic_T_50 & 33'h9A110000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _a_canArithmetic_T_52 = _a_canArithmetic_T_51;\t// @[Parameters.scala:137:46]\n wire _a_canArithmetic_T_53 = _a_canArithmetic_T_52 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire _a_canArithmetic_T_54 = _a_canArithmetic_T_48 & _a_canArithmetic_T_53;\t// @[Parameters.scala:684:{29,54}]\n wire _a_canArithmetic_T_56 = _a_canArithmetic_T_55;\t// @[Parameters.scala:686:26]\n wire _a_canArithmetic_T_57 = _a_canArithmetic_T_56 | _a_canArithmetic_T_54;\t// @[Parameters.scala:684:54, :686:26]\n wire a_canArithmetic = _a_canArithmetic_T_57;\t// @[Parameters.scala:686:26]\n wire a_isLogical = nodeIn_a_bits_opcode == 3'h3;\t// @[AtomicAutomata.scala:96:47]\n wire a_isArithmetic = nodeIn_a_bits_opcode == 3'h2;\t// @[AtomicAutomata.scala:97:47]\n wire _a_isSupported_T = ~a_isArithmetic | a_canArithmetic;\t// @[AtomicAutomata.scala:95:45, :97:47, :98:63]\n wire a_isSupported = a_isLogical ? a_canLogical : _a_isSupported_T;\t// @[AtomicAutomata.scala:94:45, :96:47, :98:{32,63}]\n wire [32:0] _a_fifoId_T_1 = {1'h0, _a_fifoId_T};\t// @[Parameters.scala:137:{31,41}]\n wire _indexes_T = cam_a_0_bits_data[0];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_1 = cam_d_0_data[0];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_0 = {_indexes_T, _indexes_T_1};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_2 = cam_a_0_bits_data[1];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_3 = cam_d_0_data[1];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_1 = {_indexes_T_2, _indexes_T_3};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_4 = cam_a_0_bits_data[2];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_5 = cam_d_0_data[2];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_2 = {_indexes_T_4, _indexes_T_5};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_6 = cam_a_0_bits_data[3];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_7 = cam_d_0_data[3];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_3 = {_indexes_T_6, _indexes_T_7};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_8 = cam_a_0_bits_data[4];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_9 = cam_d_0_data[4];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_4 = {_indexes_T_8, _indexes_T_9};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_10 = cam_a_0_bits_data[5];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_11 = cam_d_0_data[5];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_5 = {_indexes_T_10, _indexes_T_11};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_12 = cam_a_0_bits_data[6];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_13 = cam_d_0_data[6];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_6 = {_indexes_T_12, _indexes_T_13};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_14 = cam_a_0_bits_data[7];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _signbits_a_T = cam_a_0_bits_data[7];\t// @[AtomicAutomata.scala:83:24, :119:63, :128:64]\n wire _indexes_T_15 = cam_d_0_data[7];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire _signbits_d_T = cam_d_0_data[7];\t// @[AtomicAutomata.scala:84:24, :119:73, :129:64]\n wire [1:0] indexes_7 = {_indexes_T_14, _indexes_T_15};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_16 = cam_a_0_bits_data[8];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_17 = cam_d_0_data[8];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_8 = {_indexes_T_16, _indexes_T_17};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_18 = cam_a_0_bits_data[9];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_19 = cam_d_0_data[9];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_9 = {_indexes_T_18, _indexes_T_19};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_20 = cam_a_0_bits_data[10];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_21 = cam_d_0_data[10];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_10 = {_indexes_T_20, _indexes_T_21};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_22 = cam_a_0_bits_data[11];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_23 = cam_d_0_data[11];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_11 = {_indexes_T_22, _indexes_T_23};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_24 = cam_a_0_bits_data[12];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_25 = cam_d_0_data[12];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_12 = {_indexes_T_24, _indexes_T_25};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_26 = cam_a_0_bits_data[13];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_27 = cam_d_0_data[13];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_13 = {_indexes_T_26, _indexes_T_27};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_28 = cam_a_0_bits_data[14];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_29 = cam_d_0_data[14];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_14 = {_indexes_T_28, _indexes_T_29};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_30 = cam_a_0_bits_data[15];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _signbits_a_T_1 = cam_a_0_bits_data[15];\t// @[AtomicAutomata.scala:83:24, :119:63, :128:64]\n wire _indexes_T_31 = cam_d_0_data[15];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire _signbits_d_T_1 = cam_d_0_data[15];\t// @[AtomicAutomata.scala:84:24, :119:73, :129:64]\n wire [1:0] indexes_15 = {_indexes_T_30, _indexes_T_31};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_32 = cam_a_0_bits_data[16];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_33 = cam_d_0_data[16];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_16 = {_indexes_T_32, _indexes_T_33};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_34 = cam_a_0_bits_data[17];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_35 = cam_d_0_data[17];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_17 = {_indexes_T_34, _indexes_T_35};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_36 = cam_a_0_bits_data[18];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_37 = cam_d_0_data[18];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_18 = {_indexes_T_36, _indexes_T_37};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_38 = cam_a_0_bits_data[19];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_39 = cam_d_0_data[19];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_19 = {_indexes_T_38, _indexes_T_39};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_40 = cam_a_0_bits_data[20];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_41 = cam_d_0_data[20];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_20 = {_indexes_T_40, _indexes_T_41};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_42 = cam_a_0_bits_data[21];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_43 = cam_d_0_data[21];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_21 = {_indexes_T_42, _indexes_T_43};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_44 = cam_a_0_bits_data[22];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_45 = cam_d_0_data[22];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_22 = {_indexes_T_44, _indexes_T_45};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_46 = cam_a_0_bits_data[23];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _signbits_a_T_2 = cam_a_0_bits_data[23];\t// @[AtomicAutomata.scala:83:24, :119:63, :128:64]\n wire _indexes_T_47 = cam_d_0_data[23];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire _signbits_d_T_2 = cam_d_0_data[23];\t// @[AtomicAutomata.scala:84:24, :119:73, :129:64]\n wire [1:0] indexes_23 = {_indexes_T_46, _indexes_T_47};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_48 = cam_a_0_bits_data[24];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_49 = cam_d_0_data[24];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_24 = {_indexes_T_48, _indexes_T_49};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_50 = cam_a_0_bits_data[25];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_51 = cam_d_0_data[25];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_25 = {_indexes_T_50, _indexes_T_51};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_52 = cam_a_0_bits_data[26];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_53 = cam_d_0_data[26];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_26 = {_indexes_T_52, _indexes_T_53};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_54 = cam_a_0_bits_data[27];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_55 = cam_d_0_data[27];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_27 = {_indexes_T_54, _indexes_T_55};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_56 = cam_a_0_bits_data[28];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_57 = cam_d_0_data[28];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_28 = {_indexes_T_56, _indexes_T_57};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_58 = cam_a_0_bits_data[29];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_59 = cam_d_0_data[29];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_29 = {_indexes_T_58, _indexes_T_59};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_60 = cam_a_0_bits_data[30];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_61 = cam_d_0_data[30];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_30 = {_indexes_T_60, _indexes_T_61};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_62 = cam_a_0_bits_data[31];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _signbits_a_T_3 = cam_a_0_bits_data[31];\t// @[AtomicAutomata.scala:83:24, :119:63, :128:64]\n wire _indexes_T_63 = cam_d_0_data[31];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire _signbits_d_T_3 = cam_d_0_data[31];\t// @[AtomicAutomata.scala:84:24, :119:73, :129:64]\n wire [1:0] indexes_31 = {_indexes_T_62, _indexes_T_63};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_64 = cam_a_0_bits_data[32];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_65 = cam_d_0_data[32];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_32 = {_indexes_T_64, _indexes_T_65};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_66 = cam_a_0_bits_data[33];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_67 = cam_d_0_data[33];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_33 = {_indexes_T_66, _indexes_T_67};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_68 = cam_a_0_bits_data[34];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_69 = cam_d_0_data[34];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_34 = {_indexes_T_68, _indexes_T_69};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_70 = cam_a_0_bits_data[35];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_71 = cam_d_0_data[35];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_35 = {_indexes_T_70, _indexes_T_71};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_72 = cam_a_0_bits_data[36];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_73 = cam_d_0_data[36];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_36 = {_indexes_T_72, _indexes_T_73};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_74 = cam_a_0_bits_data[37];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_75 = cam_d_0_data[37];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_37 = {_indexes_T_74, _indexes_T_75};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_76 = cam_a_0_bits_data[38];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_77 = cam_d_0_data[38];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_38 = {_indexes_T_76, _indexes_T_77};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_78 = cam_a_0_bits_data[39];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _signbits_a_T_4 = cam_a_0_bits_data[39];\t// @[AtomicAutomata.scala:83:24, :119:63, :128:64]\n wire _indexes_T_79 = cam_d_0_data[39];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire _signbits_d_T_4 = cam_d_0_data[39];\t// @[AtomicAutomata.scala:84:24, :119:73, :129:64]\n wire [1:0] indexes_39 = {_indexes_T_78, _indexes_T_79};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_80 = cam_a_0_bits_data[40];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_81 = cam_d_0_data[40];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_40 = {_indexes_T_80, _indexes_T_81};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_82 = cam_a_0_bits_data[41];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_83 = cam_d_0_data[41];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_41 = {_indexes_T_82, _indexes_T_83};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_84 = cam_a_0_bits_data[42];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_85 = cam_d_0_data[42];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_42 = {_indexes_T_84, _indexes_T_85};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_86 = cam_a_0_bits_data[43];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_87 = cam_d_0_data[43];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_43 = {_indexes_T_86, _indexes_T_87};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_88 = cam_a_0_bits_data[44];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_89 = cam_d_0_data[44];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_44 = {_indexes_T_88, _indexes_T_89};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_90 = cam_a_0_bits_data[45];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_91 = cam_d_0_data[45];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_45 = {_indexes_T_90, _indexes_T_91};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_92 = cam_a_0_bits_data[46];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_93 = cam_d_0_data[46];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_46 = {_indexes_T_92, _indexes_T_93};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_94 = cam_a_0_bits_data[47];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _signbits_a_T_5 = cam_a_0_bits_data[47];\t// @[AtomicAutomata.scala:83:24, :119:63, :128:64]\n wire _indexes_T_95 = cam_d_0_data[47];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire _signbits_d_T_5 = cam_d_0_data[47];\t// @[AtomicAutomata.scala:84:24, :119:73, :129:64]\n wire [1:0] indexes_47 = {_indexes_T_94, _indexes_T_95};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_96 = cam_a_0_bits_data[48];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_97 = cam_d_0_data[48];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_48 = {_indexes_T_96, _indexes_T_97};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_98 = cam_a_0_bits_data[49];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_99 = cam_d_0_data[49];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_49 = {_indexes_T_98, _indexes_T_99};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_100 = cam_a_0_bits_data[50];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_101 = cam_d_0_data[50];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_50 = {_indexes_T_100, _indexes_T_101};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_102 = cam_a_0_bits_data[51];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_103 = cam_d_0_data[51];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_51 = {_indexes_T_102, _indexes_T_103};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_104 = cam_a_0_bits_data[52];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_105 = cam_d_0_data[52];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_52 = {_indexes_T_104, _indexes_T_105};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_106 = cam_a_0_bits_data[53];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_107 = cam_d_0_data[53];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_53 = {_indexes_T_106, _indexes_T_107};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_108 = cam_a_0_bits_data[54];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_109 = cam_d_0_data[54];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_54 = {_indexes_T_108, _indexes_T_109};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_110 = cam_a_0_bits_data[55];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _signbits_a_T_6 = cam_a_0_bits_data[55];\t// @[AtomicAutomata.scala:83:24, :119:63, :128:64]\n wire _indexes_T_111 = cam_d_0_data[55];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire _signbits_d_T_6 = cam_d_0_data[55];\t// @[AtomicAutomata.scala:84:24, :119:73, :129:64]\n wire [1:0] indexes_55 = {_indexes_T_110, _indexes_T_111};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_112 = cam_a_0_bits_data[56];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_113 = cam_d_0_data[56];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_56 = {_indexes_T_112, _indexes_T_113};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_114 = cam_a_0_bits_data[57];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_115 = cam_d_0_data[57];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_57 = {_indexes_T_114, _indexes_T_115};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_116 = cam_a_0_bits_data[58];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_117 = cam_d_0_data[58];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_58 = {_indexes_T_116, _indexes_T_117};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_118 = cam_a_0_bits_data[59];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_119 = cam_d_0_data[59];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_59 = {_indexes_T_118, _indexes_T_119};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_120 = cam_a_0_bits_data[60];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_121 = cam_d_0_data[60];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_60 = {_indexes_T_120, _indexes_T_121};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_122 = cam_a_0_bits_data[61];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_123 = cam_d_0_data[61];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_61 = {_indexes_T_122, _indexes_T_123};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_124 = cam_a_0_bits_data[62];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _indexes_T_125 = cam_d_0_data[62];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire [1:0] indexes_62 = {_indexes_T_124, _indexes_T_125};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire _indexes_T_126 = cam_a_0_bits_data[63];\t// @[AtomicAutomata.scala:83:24, :119:63]\n wire _signbits_a_T_7 = cam_a_0_bits_data[63];\t// @[AtomicAutomata.scala:83:24, :119:63, :128:64]\n wire _indexes_T_127 = cam_d_0_data[63];\t// @[AtomicAutomata.scala:84:24, :119:73]\n wire _signbits_d_T_7 = cam_d_0_data[63];\t// @[AtomicAutomata.scala:84:24, :119:73, :129:64]\n wire [1:0] indexes_63 = {_indexes_T_126, _indexes_T_127};\t// @[AtomicAutomata.scala:119:{59,63,73}]\n wire [3:0] _logic_out_T = cam_a_0_lut >> indexes_0;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_1 = _logic_out_T[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_2 = cam_a_0_lut >> indexes_1;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_3 = _logic_out_T_2[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_4 = cam_a_0_lut >> indexes_2;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_5 = _logic_out_T_4[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_6 = cam_a_0_lut >> indexes_3;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_7 = _logic_out_T_6[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_8 = cam_a_0_lut >> indexes_4;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_9 = _logic_out_T_8[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_10 = cam_a_0_lut >> indexes_5;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_11 = _logic_out_T_10[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_12 = cam_a_0_lut >> indexes_6;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_13 = _logic_out_T_12[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_14 = cam_a_0_lut >> indexes_7;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_15 = _logic_out_T_14[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_16 = cam_a_0_lut >> indexes_8;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_17 = _logic_out_T_16[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_18 = cam_a_0_lut >> indexes_9;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_19 = _logic_out_T_18[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_20 = cam_a_0_lut >> indexes_10;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_21 = _logic_out_T_20[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_22 = cam_a_0_lut >> indexes_11;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_23 = _logic_out_T_22[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_24 = cam_a_0_lut >> indexes_12;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_25 = _logic_out_T_24[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_26 = cam_a_0_lut >> indexes_13;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_27 = _logic_out_T_26[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_28 = cam_a_0_lut >> indexes_14;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_29 = _logic_out_T_28[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_30 = cam_a_0_lut >> indexes_15;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_31 = _logic_out_T_30[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_32 = cam_a_0_lut >> indexes_16;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_33 = _logic_out_T_32[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_34 = cam_a_0_lut >> indexes_17;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_35 = _logic_out_T_34[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_36 = cam_a_0_lut >> indexes_18;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_37 = _logic_out_T_36[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_38 = cam_a_0_lut >> indexes_19;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_39 = _logic_out_T_38[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_40 = cam_a_0_lut >> indexes_20;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_41 = _logic_out_T_40[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_42 = cam_a_0_lut >> indexes_21;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_43 = _logic_out_T_42[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_44 = cam_a_0_lut >> indexes_22;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_45 = _logic_out_T_44[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_46 = cam_a_0_lut >> indexes_23;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_47 = _logic_out_T_46[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_48 = cam_a_0_lut >> indexes_24;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_49 = _logic_out_T_48[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_50 = cam_a_0_lut >> indexes_25;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_51 = _logic_out_T_50[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_52 = cam_a_0_lut >> indexes_26;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_53 = _logic_out_T_52[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_54 = cam_a_0_lut >> indexes_27;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_55 = _logic_out_T_54[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_56 = cam_a_0_lut >> indexes_28;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_57 = _logic_out_T_56[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_58 = cam_a_0_lut >> indexes_29;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_59 = _logic_out_T_58[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_60 = cam_a_0_lut >> indexes_30;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_61 = _logic_out_T_60[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_62 = cam_a_0_lut >> indexes_31;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_63 = _logic_out_T_62[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_64 = cam_a_0_lut >> indexes_32;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_65 = _logic_out_T_64[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_66 = cam_a_0_lut >> indexes_33;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_67 = _logic_out_T_66[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_68 = cam_a_0_lut >> indexes_34;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_69 = _logic_out_T_68[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_70 = cam_a_0_lut >> indexes_35;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_71 = _logic_out_T_70[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_72 = cam_a_0_lut >> indexes_36;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_73 = _logic_out_T_72[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_74 = cam_a_0_lut >> indexes_37;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_75 = _logic_out_T_74[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_76 = cam_a_0_lut >> indexes_38;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_77 = _logic_out_T_76[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_78 = cam_a_0_lut >> indexes_39;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_79 = _logic_out_T_78[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_80 = cam_a_0_lut >> indexes_40;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_81 = _logic_out_T_80[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_82 = cam_a_0_lut >> indexes_41;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_83 = _logic_out_T_82[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_84 = cam_a_0_lut >> indexes_42;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_85 = _logic_out_T_84[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_86 = cam_a_0_lut >> indexes_43;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_87 = _logic_out_T_86[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_88 = cam_a_0_lut >> indexes_44;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_89 = _logic_out_T_88[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_90 = cam_a_0_lut >> indexes_45;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_91 = _logic_out_T_90[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_92 = cam_a_0_lut >> indexes_46;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_93 = _logic_out_T_92[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_94 = cam_a_0_lut >> indexes_47;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_95 = _logic_out_T_94[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_96 = cam_a_0_lut >> indexes_48;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_97 = _logic_out_T_96[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_98 = cam_a_0_lut >> indexes_49;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_99 = _logic_out_T_98[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_100 = cam_a_0_lut >> indexes_50;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_101 = _logic_out_T_100[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_102 = cam_a_0_lut >> indexes_51;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_103 = _logic_out_T_102[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_104 = cam_a_0_lut >> indexes_52;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_105 = _logic_out_T_104[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_106 = cam_a_0_lut >> indexes_53;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_107 = _logic_out_T_106[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_108 = cam_a_0_lut >> indexes_54;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_109 = _logic_out_T_108[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_110 = cam_a_0_lut >> indexes_55;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_111 = _logic_out_T_110[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_112 = cam_a_0_lut >> indexes_56;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_113 = _logic_out_T_112[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_114 = cam_a_0_lut >> indexes_57;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_115 = _logic_out_T_114[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_116 = cam_a_0_lut >> indexes_58;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_117 = _logic_out_T_116[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_118 = cam_a_0_lut >> indexes_59;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_119 = _logic_out_T_118[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_120 = cam_a_0_lut >> indexes_60;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_121 = _logic_out_T_120[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_122 = cam_a_0_lut >> indexes_61;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_123 = _logic_out_T_122[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_124 = cam_a_0_lut >> indexes_62;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_125 = _logic_out_T_124[0];\t// @[AtomicAutomata.scala:120:57]\n wire [3:0] _logic_out_T_126 = cam_a_0_lut >> indexes_63;\t// @[AtomicAutomata.scala:83:24, :119:59, :120:57]\n wire _logic_out_T_127 = _logic_out_T_126[0];\t// @[AtomicAutomata.scala:120:57]\n wire [1:0] logic_out_lo_lo_lo_lo_lo = {_logic_out_T_3, _logic_out_T_1};\t// @[AtomicAutomata.scala:120:{28,57}]\n wire [1:0] logic_out_lo_lo_lo_lo_hi = {_logic_out_T_7, _logic_out_T_5};\t// @[AtomicAutomata.scala:120:{28,57}]\n wire [3:0] logic_out_lo_lo_lo_lo = {logic_out_lo_lo_lo_lo_hi, logic_out_lo_lo_lo_lo_lo};\t// @[AtomicAutomata.scala:120:28]\n wire [1:0] logic_out_lo_lo_lo_hi_lo = {_logic_out_T_11, _logic_out_T_9};\t// @[AtomicAutomata.scala:120:{28,57}]\n wire [1:0] logic_out_lo_lo_lo_hi_hi = {_logic_out_T_15, _logic_out_T_13};\t// @[AtomicAutomata.scala:120:{28,57}]\n wire [3:0] logic_out_lo_lo_lo_hi = {logic_out_lo_lo_lo_hi_hi, logic_out_lo_lo_lo_hi_lo};\t// @[AtomicAutomata.scala:120:28]\n wire [7:0] logic_out_lo_lo_lo = {logic_out_lo_lo_lo_hi, logic_out_lo_lo_lo_lo};\t// @[AtomicAutomata.scala:120:28]\n wire [1:0] logic_out_lo_lo_hi_lo_lo = {_logic_out_T_19, _logic_out_T_17};\t// @[AtomicAutomata.scala:120:{28,57}]\n wire [1:0] logic_out_lo_lo_hi_lo_hi = {_logic_out_T_23, _logic_out_T_21};\t// @[AtomicAutomata.scala:120:{28,57}]\n wire [3:0] logic_out_lo_lo_hi_lo = {logic_out_lo_lo_hi_lo_hi, logic_out_lo_lo_hi_lo_lo};\t// @[AtomicAutomata.scala:120:28]\n wire [1:0] logic_out_lo_lo_hi_hi_lo = {_logic_out_T_27, _logic_out_T_25};\t// @[AtomicAutomata.scala:120:{28,57}]\n wire [1:0] logic_out_lo_lo_hi_hi_hi = {_logic_out_T_31, _logic_out_T_29};\t// @[AtomicAutomata.scala:120:{28,57}]\n wire [3:0] logic_out_lo_lo_hi_hi = {logic_out_lo_lo_hi_hi_hi, logic_out_lo_lo_hi_hi_lo};\t// @[AtomicAutomata.scala:120:28]\n wire [7:0] logic_out_lo_lo_hi = {logic_out_lo_lo_hi_hi, logic_out_lo_lo_hi_lo};\t// @[AtomicAutomata.scala:120:28]\n wire [15:0] logic_out_lo_lo = {logic_out_lo_lo_hi, logic_out_lo_lo_lo};\t// @[AtomicAutomata.scala:120:28]\n wire [1:0] logic_out_lo_hi_lo_lo_lo = {_logic_out_T_35, _logic_out_T_33};\t// @[AtomicAutomata.scala:120:{28,57}]\n wire [1:0] logic_out_lo_hi_lo_lo_hi = {_logic_out_T_39, _logic_out_T_37};\t// @[AtomicAutomata.scala:120:{28,57}]\n wire [3:0] logic_out_lo_hi_lo_lo = {logic_out_lo_hi_lo_lo_hi, logic_out_lo_hi_lo_lo_lo};\t// @[AtomicAutomata.scala:120:28]\n wire [1:0] logic_out_lo_hi_lo_hi_lo = {_logic_out_T_43, _logic_out_T_41};\t// @[AtomicAutomata.scala:120:{28,57}]\n wire [1:0] logic_out_lo_hi_lo_hi_hi = {_logic_out_T_47, _logic_out_T_45};\t// @[AtomicAutomata.scala:120:{28,57}]\n wire [3:0] logic_out_lo_hi_lo_hi = {logic_out_lo_hi_lo_hi_hi, logic_out_lo_hi_lo_hi_lo};\t// @[AtomicAutomata.scala:120:28]\n wire [7:0] logic_out_lo_hi_lo = {logic_out_lo_hi_lo_hi, logic_out_lo_hi_lo_lo};\t// @[AtomicAutomata.scala:120:28]\n wire [1:0] logic_out_lo_hi_hi_lo_lo = {_logic_out_T_51, _logic_out_T_49};\t// @[AtomicAutomata.scala:120:{28,57}]\n wire [1:0] logic_out_lo_hi_hi_lo_hi = {_logic_out_T_55, _logic_out_T_53};\t// @[AtomicAutomata.scala:120:{28,57}]\n wire [3:0] logic_out_lo_hi_hi_lo = {logic_out_lo_hi_hi_lo_hi, logic_out_lo_hi_hi_lo_lo};\t// @[AtomicAutomata.scala:120:28]\n wire [1:0] logic_out_lo_hi_hi_hi_lo = {_logic_out_T_59, _logic_out_T_57};\t// @[AtomicAutomata.scala:120:{28,57}]\n wire [1:0] logic_out_lo_hi_hi_hi_hi = {_logic_out_T_63, _logic_out_T_61};\t// @[AtomicAutomata.scala:120:{28,57}]\n wire [3:0] logic_out_lo_hi_hi_hi = {logic_out_lo_hi_hi_hi_hi, logic_out_lo_hi_hi_hi_lo};\t// @[AtomicAutomata.scala:120:28]\n wire [7:0] logic_out_lo_hi_hi = {logic_out_lo_hi_hi_hi, logic_out_lo_hi_hi_lo};\t// @[AtomicAutomata.scala:120:28]\n wire [15:0] logic_out_lo_hi = {logic_out_lo_hi_hi, logic_out_lo_hi_lo};\t// @[AtomicAutomata.scala:120:28]\n wire [31:0] logic_out_lo = {logic_out_lo_hi, logic_out_lo_lo};\t// @[AtomicAutomata.scala:120:28]\n wire [1:0] logic_out_hi_lo_lo_lo_lo = {_logic_out_T_67, _logic_out_T_65};\t// @[AtomicAutomata.scala:120:{28,57}]\n wire [1:0] logic_out_hi_lo_lo_lo_hi = {_logic_out_T_71, _logic_out_T_69};\t// @[AtomicAutomata.scala:120:{28,57}]\n wire [3:0] logic_out_hi_lo_lo_lo = {logic_out_hi_lo_lo_lo_hi, logic_out_hi_lo_lo_lo_lo};\t// @[AtomicAutomata.scala:120:28]\n wire [1:0] logic_out_hi_lo_lo_hi_lo = {_logic_out_T_75, _logic_out_T_73};\t// @[AtomicAutomata.scala:120:{28,57}]\n wire [1:0] logic_out_hi_lo_lo_hi_hi = {_logic_out_T_79, _logic_out_T_77};\t// @[AtomicAutomata.scala:120:{28,57}]\n wire [3:0] logic_out_hi_lo_lo_hi = {logic_out_hi_lo_lo_hi_hi, logic_out_hi_lo_lo_hi_lo};\t// @[AtomicAutomata.scala:120:28]\n wire [7:0] logic_out_hi_lo_lo = {logic_out_hi_lo_lo_hi, logic_out_hi_lo_lo_lo};\t// @[AtomicAutomata.scala:120:28]\n wire [1:0] logic_out_hi_lo_hi_lo_lo = {_logic_out_T_83, _logic_out_T_81};\t// @[AtomicAutomata.scala:120:{28,57}]\n wire [1:0] logic_out_hi_lo_hi_lo_hi = {_logic_out_T_87, _logic_out_T_85};\t// @[AtomicAutomata.scala:120:{28,57}]\n wire [3:0] logic_out_hi_lo_hi_lo = {logic_out_hi_lo_hi_lo_hi, logic_out_hi_lo_hi_lo_lo};\t// @[AtomicAutomata.scala:120:28]\n wire [1:0] logic_out_hi_lo_hi_hi_lo = {_logic_out_T_91, _logic_out_T_89};\t// @[AtomicAutomata.scala:120:{28,57}]\n wire [1:0] logic_out_hi_lo_hi_hi_hi = {_logic_out_T_95, _logic_out_T_93};\t// @[AtomicAutomata.scala:120:{28,57}]\n wire [3:0] logic_out_hi_lo_hi_hi = {logic_out_hi_lo_hi_hi_hi, logic_out_hi_lo_hi_hi_lo};\t// @[AtomicAutomata.scala:120:28]\n wire [7:0] logic_out_hi_lo_hi = {logic_out_hi_lo_hi_hi, logic_out_hi_lo_hi_lo};\t// @[AtomicAutomata.scala:120:28]\n wire [15:0] logic_out_hi_lo = {logic_out_hi_lo_hi, logic_out_hi_lo_lo};\t// @[AtomicAutomata.scala:120:28]\n wire [1:0] logic_out_hi_hi_lo_lo_lo = {_logic_out_T_99, _logic_out_T_97};\t// @[AtomicAutomata.scala:120:{28,57}]\n wire [1:0] logic_out_hi_hi_lo_lo_hi = {_logic_out_T_103, _logic_out_T_101};\t// @[AtomicAutomata.scala:120:{28,57}]\n wire [3:0] logic_out_hi_hi_lo_lo = {logic_out_hi_hi_lo_lo_hi, logic_out_hi_hi_lo_lo_lo};\t// @[AtomicAutomata.scala:120:28]\n wire [1:0] logic_out_hi_hi_lo_hi_lo = {_logic_out_T_107, _logic_out_T_105};\t// @[AtomicAutomata.scala:120:{28,57}]\n wire [1:0] logic_out_hi_hi_lo_hi_hi = {_logic_out_T_111, _logic_out_T_109};\t// @[AtomicAutomata.scala:120:{28,57}]\n wire [3:0] logic_out_hi_hi_lo_hi = {logic_out_hi_hi_lo_hi_hi, logic_out_hi_hi_lo_hi_lo};\t// @[AtomicAutomata.scala:120:28]\n wire [7:0] logic_out_hi_hi_lo = {logic_out_hi_hi_lo_hi, logic_out_hi_hi_lo_lo};\t// @[AtomicAutomata.scala:120:28]\n wire [1:0] logic_out_hi_hi_hi_lo_lo = {_logic_out_T_115, _logic_out_T_113};\t// @[AtomicAutomata.scala:120:{28,57}]\n wire [1:0] logic_out_hi_hi_hi_lo_hi = {_logic_out_T_119, _logic_out_T_117};\t// @[AtomicAutomata.scala:120:{28,57}]\n wire [3:0] logic_out_hi_hi_hi_lo = {logic_out_hi_hi_hi_lo_hi, logic_out_hi_hi_hi_lo_lo};\t// @[AtomicAutomata.scala:120:28]\n wire [1:0] logic_out_hi_hi_hi_hi_lo = {_logic_out_T_123, _logic_out_T_121};\t// @[AtomicAutomata.scala:120:{28,57}]\n wire [1:0] logic_out_hi_hi_hi_hi_hi = {_logic_out_T_127, _logic_out_T_125};\t// @[AtomicAutomata.scala:120:{28,57}]\n wire [3:0] logic_out_hi_hi_hi_hi = {logic_out_hi_hi_hi_hi_hi, logic_out_hi_hi_hi_hi_lo};\t// @[AtomicAutomata.scala:120:28]\n wire [7:0] logic_out_hi_hi_hi = {logic_out_hi_hi_hi_hi, logic_out_hi_hi_hi_lo};\t// @[AtomicAutomata.scala:120:28]\n wire [15:0] logic_out_hi_hi = {logic_out_hi_hi_hi, logic_out_hi_hi_lo};\t// @[AtomicAutomata.scala:120:28]\n wire [31:0] logic_out_hi = {logic_out_hi_hi, logic_out_hi_lo};\t// @[AtomicAutomata.scala:120:28]\n wire [63:0] logic_out = {logic_out_hi, logic_out_lo};\t// @[AtomicAutomata.scala:120:28]\n wire unsigned_0 = cam_a_0_bits_param[1];\t// @[AtomicAutomata.scala:83:24, :123:42]\n wire take_max = cam_a_0_bits_param[0];\t// @[AtomicAutomata.scala:83:24, :124:42]\n wire adder = cam_a_0_bits_param[2];\t// @[AtomicAutomata.scala:83:24, :125:39]\n wire [7:0] _signSel_T = ~cam_a_0_bits_mask;\t// @[AtomicAutomata.scala:83:24, :127:25]\n wire [6:0] _signSel_T_1 = cam_a_0_bits_mask[7:1];\t// @[AtomicAutomata.scala:83:24, :127:39]\n wire [7:0] _signSel_T_2 = {_signSel_T[7], _signSel_T[6:0] | _signSel_T_1};\t// @[AtomicAutomata.scala:127:{25,31,39}]\n wire [7:0] signSel = ~_signSel_T_2;\t// @[AtomicAutomata.scala:127:{23,31}]\n wire [1:0] signbits_a_lo_lo = {_signbits_a_T_1, _signbits_a_T};\t// @[AtomicAutomata.scala:128:{29,64}]\n wire [1:0] signbits_a_lo_hi = {_signbits_a_T_3, _signbits_a_T_2};\t// @[AtomicAutomata.scala:128:{29,64}]\n wire [3:0] signbits_a_lo = {signbits_a_lo_hi, signbits_a_lo_lo};\t// @[AtomicAutomata.scala:128:29]\n wire [1:0] signbits_a_hi_lo = {_signbits_a_T_5, _signbits_a_T_4};\t// @[AtomicAutomata.scala:128:{29,64}]\n wire [1:0] signbits_a_hi_hi = {_signbits_a_T_7, _signbits_a_T_6};\t// @[AtomicAutomata.scala:128:{29,64}]\n wire [3:0] signbits_a_hi = {signbits_a_hi_hi, signbits_a_hi_lo};\t// @[AtomicAutomata.scala:128:29]\n wire [7:0] signbits_a = {signbits_a_hi, signbits_a_lo};\t// @[AtomicAutomata.scala:128:29]\n wire [1:0] signbits_d_lo_lo = {_signbits_d_T_1, _signbits_d_T};\t// @[AtomicAutomata.scala:129:{29,64}]\n wire [1:0] signbits_d_lo_hi = {_signbits_d_T_3, _signbits_d_T_2};\t// @[AtomicAutomata.scala:129:{29,64}]\n wire [3:0] signbits_d_lo = {signbits_d_lo_hi, signbits_d_lo_lo};\t// @[AtomicAutomata.scala:129:29]\n wire [1:0] signbits_d_hi_lo = {_signbits_d_T_5, _signbits_d_T_4};\t// @[AtomicAutomata.scala:129:{29,64}]\n wire [1:0] signbits_d_hi_hi = {_signbits_d_T_7, _signbits_d_T_6};\t// @[AtomicAutomata.scala:129:{29,64}]\n wire [3:0] signbits_d_hi = {signbits_d_hi_hi, signbits_d_hi_lo};\t// @[AtomicAutomata.scala:129:29]\n wire [7:0] signbits_d = {signbits_d_hi, signbits_d_lo};\t// @[AtomicAutomata.scala:129:29]\n wire [7:0] _signbit_a_T = signbits_a & signSel;\t// @[AtomicAutomata.scala:127:23, :128:29, :131:38]\n wire [8:0] _signbit_a_T_1 = {_signbit_a_T, 1'h0};\t// @[AtomicAutomata.scala:131:{38,49}]\n wire [7:0] signbit_a = _signbit_a_T_1[7:0];\t// @[AtomicAutomata.scala:131:{49,54}]\n wire [7:0] _signbit_d_T = signbits_d & signSel;\t// @[AtomicAutomata.scala:127:23, :129:29, :132:38]\n wire [8:0] _signbit_d_T_1 = {_signbit_d_T, 1'h0};\t// @[AtomicAutomata.scala:132:{38,49}]\n wire [7:0] signbit_d = _signbit_d_T_1[7:0];\t// @[AtomicAutomata.scala:132:{49,54}]\n wire [8:0] _signext_a_T = {signbit_a, 1'h0};\t// @[package.scala:253:48]\n wire [7:0] _signext_a_T_1 = _signext_a_T[7:0];\t// @[package.scala:253:{48,53}]\n wire [7:0] _signext_a_T_2 = signbit_a | _signext_a_T_1;\t// @[package.scala:253:{43,53}]\n wire [9:0] _signext_a_T_3 = {_signext_a_T_2, 2'h0};\t// @[package.scala:253:{43,48}]\n wire [7:0] _signext_a_T_4 = _signext_a_T_3[7:0];\t// @[package.scala:253:{48,53}]\n wire [7:0] _signext_a_T_5 = _signext_a_T_2 | _signext_a_T_4;\t// @[package.scala:253:{43,53}]\n wire [11:0] _signext_a_T_6 = {_signext_a_T_5, 4'h0};\t// @[package.scala:253:{43,48}]\n wire [7:0] _signext_a_T_7 = _signext_a_T_6[7:0];\t// @[package.scala:253:{48,53}]\n wire [7:0] _signext_a_T_8 = _signext_a_T_5 | _signext_a_T_7;\t// @[package.scala:253:{43,53}]\n wire [7:0] _signext_a_T_9 = _signext_a_T_8;\t// @[package.scala:253:43, :254:17]\n wire _signext_a_T_10 = _signext_a_T_9[0];\t// @[package.scala:254:17]\n wire _signext_a_T_11 = _signext_a_T_9[1];\t// @[package.scala:254:17]\n wire _signext_a_T_12 = _signext_a_T_9[2];\t// @[package.scala:254:17]\n wire _signext_a_T_13 = _signext_a_T_9[3];\t// @[package.scala:254:17]\n wire _signext_a_T_14 = _signext_a_T_9[4];\t// @[package.scala:254:17]\n wire _signext_a_T_15 = _signext_a_T_9[5];\t// @[package.scala:254:17]\n wire _signext_a_T_16 = _signext_a_T_9[6];\t// @[package.scala:254:17]\n wire _signext_a_T_17 = _signext_a_T_9[7];\t// @[package.scala:254:17]\n wire [7:0] _signext_a_T_18 = {8{_signext_a_T_10}};\t// @[AtomicAutomata.scala:133:40]\n wire [7:0] _signext_a_T_19 = {8{_signext_a_T_11}};\t// @[AtomicAutomata.scala:133:40]\n wire [7:0] _signext_a_T_20 = {8{_signext_a_T_12}};\t// @[AtomicAutomata.scala:133:40]\n wire [7:0] _signext_a_T_21 = {8{_signext_a_T_13}};\t// @[AtomicAutomata.scala:133:40]\n wire [7:0] _signext_a_T_22 = {8{_signext_a_T_14}};\t// @[AtomicAutomata.scala:133:40]\n wire [7:0] _signext_a_T_23 = {8{_signext_a_T_15}};\t// @[AtomicAutomata.scala:133:40]\n wire [7:0] _signext_a_T_24 = {8{_signext_a_T_16}};\t// @[AtomicAutomata.scala:133:40]\n wire [7:0] _signext_a_T_25 = {8{_signext_a_T_17}};\t// @[AtomicAutomata.scala:133:40]\n wire [15:0] signext_a_lo_lo = {_signext_a_T_19, _signext_a_T_18};\t// @[AtomicAutomata.scala:133:40]\n wire [15:0] signext_a_lo_hi = {_signext_a_T_21, _signext_a_T_20};\t// @[AtomicAutomata.scala:133:40]\n wire [31:0] signext_a_lo = {signext_a_lo_hi, signext_a_lo_lo};\t// @[AtomicAutomata.scala:133:40]\n wire [15:0] signext_a_hi_lo = {_signext_a_T_23, _signext_a_T_22};\t// @[AtomicAutomata.scala:133:40]\n wire [15:0] signext_a_hi_hi = {_signext_a_T_25, _signext_a_T_24};\t// @[AtomicAutomata.scala:133:40]\n wire [31:0] signext_a_hi = {signext_a_hi_hi, signext_a_hi_lo};\t// @[AtomicAutomata.scala:133:40]\n wire [63:0] signext_a = {signext_a_hi, signext_a_lo};\t// @[AtomicAutomata.scala:133:40]\n wire [8:0] _signext_d_T = {signbit_d, 1'h0};\t// @[package.scala:253:48]\n wire [7:0] _signext_d_T_1 = _signext_d_T[7:0];\t// @[package.scala:253:{48,53}]\n wire [7:0] _signext_d_T_2 = signbit_d | _signext_d_T_1;\t// @[package.scala:253:{43,53}]\n wire [9:0] _signext_d_T_3 = {_signext_d_T_2, 2'h0};\t// @[package.scala:253:{43,48}]\n wire [7:0] _signext_d_T_4 = _signext_d_T_3[7:0];\t// @[package.scala:253:{48,53}]\n wire [7:0] _signext_d_T_5 = _signext_d_T_2 | _signext_d_T_4;\t// @[package.scala:253:{43,53}]\n wire [11:0] _signext_d_T_6 = {_signext_d_T_5, 4'h0};\t// @[package.scala:253:{43,48}]\n wire [7:0] _signext_d_T_7 = _signext_d_T_6[7:0];\t// @[package.scala:253:{48,53}]\n wire [7:0] _signext_d_T_8 = _signext_d_T_5 | _signext_d_T_7;\t// @[package.scala:253:{43,53}]\n wire [7:0] _signext_d_T_9 = _signext_d_T_8;\t// @[package.scala:253:43, :254:17]\n wire _signext_d_T_10 = _signext_d_T_9[0];\t// @[package.scala:254:17]\n wire _signext_d_T_11 = _signext_d_T_9[1];\t// @[package.scala:254:17]\n wire _signext_d_T_12 = _signext_d_T_9[2];\t// @[package.scala:254:17]\n wire _signext_d_T_13 = _signext_d_T_9[3];\t// @[package.scala:254:17]\n wire _signext_d_T_14 = _signext_d_T_9[4];\t// @[package.scala:254:17]\n wire _signext_d_T_15 = _signext_d_T_9[5];\t// @[package.scala:254:17]\n wire _signext_d_T_16 = _signext_d_T_9[6];\t// @[package.scala:254:17]\n wire _signext_d_T_17 = _signext_d_T_9[7];\t// @[package.scala:254:17]\n wire [7:0] _signext_d_T_18 = {8{_signext_d_T_10}};\t// @[AtomicAutomata.scala:134:40]\n wire [7:0] _signext_d_T_19 = {8{_signext_d_T_11}};\t// @[AtomicAutomata.scala:134:40]\n wire [7:0] _signext_d_T_20 = {8{_signext_d_T_12}};\t// @[AtomicAutomata.scala:134:40]\n wire [7:0] _signext_d_T_21 = {8{_signext_d_T_13}};\t// @[AtomicAutomata.scala:134:40]\n wire [7:0] _signext_d_T_22 = {8{_signext_d_T_14}};\t// @[AtomicAutomata.scala:134:40]\n wire [7:0] _signext_d_T_23 = {8{_signext_d_T_15}};\t// @[AtomicAutomata.scala:134:40]\n wire [7:0] _signext_d_T_24 = {8{_signext_d_T_16}};\t// @[AtomicAutomata.scala:134:40]\n wire [7:0] _signext_d_T_25 = {8{_signext_d_T_17}};\t// @[AtomicAutomata.scala:134:40]\n wire [15:0] signext_d_lo_lo = {_signext_d_T_19, _signext_d_T_18};\t// @[AtomicAutomata.scala:134:40]\n wire [15:0] signext_d_lo_hi = {_signext_d_T_21, _signext_d_T_20};\t// @[AtomicAutomata.scala:134:40]\n wire [31:0] signext_d_lo = {signext_d_lo_hi, signext_d_lo_lo};\t// @[AtomicAutomata.scala:134:40]\n wire [15:0] signext_d_hi_lo = {_signext_d_T_23, _signext_d_T_22};\t// @[AtomicAutomata.scala:134:40]\n wire [15:0] signext_d_hi_hi = {_signext_d_T_25, _signext_d_T_24};\t// @[AtomicAutomata.scala:134:40]\n wire [31:0] signext_d_hi = {signext_d_hi_hi, signext_d_hi_lo};\t// @[AtomicAutomata.scala:134:40]\n wire [63:0] signext_d = {signext_d_hi, signext_d_lo};\t// @[AtomicAutomata.scala:134:40]\n wire _wide_mask_T = cam_a_0_bits_mask[0];\t// @[AtomicAutomata.scala:83:24, :136:40]\n wire _wide_mask_T_1 = cam_a_0_bits_mask[1];\t// @[AtomicAutomata.scala:83:24, :136:40]\n wire _wide_mask_T_2 = cam_a_0_bits_mask[2];\t// @[AtomicAutomata.scala:83:24, :136:40]\n wire _wide_mask_T_3 = cam_a_0_bits_mask[3];\t// @[AtomicAutomata.scala:83:24, :136:40]\n wire _wide_mask_T_4 = cam_a_0_bits_mask[4];\t// @[AtomicAutomata.scala:83:24, :136:40]\n wire _wide_mask_T_5 = cam_a_0_bits_mask[5];\t// @[AtomicAutomata.scala:83:24, :136:40]\n wire _wide_mask_T_6 = cam_a_0_bits_mask[6];\t// @[AtomicAutomata.scala:83:24, :136:40]\n wire _wide_mask_T_7 = cam_a_0_bits_mask[7];\t// @[AtomicAutomata.scala:83:24, :136:40]\n wire [7:0] _wide_mask_T_8 = {8{_wide_mask_T}};\t// @[AtomicAutomata.scala:136:40]\n wire [7:0] _wide_mask_T_9 = {8{_wide_mask_T_1}};\t// @[AtomicAutomata.scala:136:40]\n wire [7:0] _wide_mask_T_10 = {8{_wide_mask_T_2}};\t// @[AtomicAutomata.scala:136:40]\n wire [7:0] _wide_mask_T_11 = {8{_wide_mask_T_3}};\t// @[AtomicAutomata.scala:136:40]\n wire [7:0] _wide_mask_T_12 = {8{_wide_mask_T_4}};\t// @[AtomicAutomata.scala:136:40]\n wire [7:0] _wide_mask_T_13 = {8{_wide_mask_T_5}};\t// @[AtomicAutomata.scala:136:40]\n wire [7:0] _wide_mask_T_14 = {8{_wide_mask_T_6}};\t// @[AtomicAutomata.scala:136:40]\n wire [7:0] _wide_mask_T_15 = {8{_wide_mask_T_7}};\t// @[AtomicAutomata.scala:136:40]\n wire [15:0] wide_mask_lo_lo = {_wide_mask_T_9, _wide_mask_T_8};\t// @[AtomicAutomata.scala:136:40]\n wire [15:0] wide_mask_lo_hi = {_wide_mask_T_11, _wide_mask_T_10};\t// @[AtomicAutomata.scala:136:40]\n wire [31:0] wide_mask_lo = {wide_mask_lo_hi, wide_mask_lo_lo};\t// @[AtomicAutomata.scala:136:40]\n wire [15:0] wide_mask_hi_lo = {_wide_mask_T_13, _wide_mask_T_12};\t// @[AtomicAutomata.scala:136:40]\n wire [15:0] wide_mask_hi_hi = {_wide_mask_T_15, _wide_mask_T_14};\t// @[AtomicAutomata.scala:136:40]\n wire [31:0] wide_mask_hi = {wide_mask_hi_hi, wide_mask_hi_lo};\t// @[AtomicAutomata.scala:136:40]\n wire [63:0] wide_mask = {wide_mask_hi, wide_mask_lo};\t// @[AtomicAutomata.scala:136:40]\n wire [63:0] _a_a_ext_T = cam_a_0_bits_data & wide_mask;\t// @[AtomicAutomata.scala:83:24, :136:40, :137:28]\n wire [63:0] a_a_ext = _a_a_ext_T | signext_a;\t// @[AtomicAutomata.scala:133:40, :137:{28,41}]\n wire [63:0] _a_d_ext_T = cam_d_0_data & wide_mask;\t// @[AtomicAutomata.scala:84:24, :136:40, :138:28]\n wire [63:0] a_d_ext = _a_d_ext_T | signext_d;\t// @[AtomicAutomata.scala:134:40, :138:{28,41}]\n wire [63:0] _a_d_inv_T = ~a_d_ext;\t// @[AtomicAutomata.scala:138:41, :139:43]\n wire [63:0] a_d_inv = adder ? a_d_ext : _a_d_inv_T;\t// @[AtomicAutomata.scala:125:39, :138:41, :139:{26,43}]\n wire [64:0] _adder_out_T = {1'h0, a_a_ext} + {1'h0, a_d_inv};\t// @[AtomicAutomata.scala:137:41, :139:26, :140:33]\n wire [63:0] adder_out = _adder_out_T[63:0];\t// @[AtomicAutomata.scala:140:33]\n wire _a_bigger_uneq_T = a_a_ext[63];\t// @[AtomicAutomata.scala:137:41, :142:49]\n wire _a_bigger_T = a_a_ext[63];\t// @[AtomicAutomata.scala:137:41, :142:49, :143:35]\n wire a_bigger_uneq = unsigned_0 == _a_bigger_uneq_T;\t// @[AtomicAutomata.scala:123:42, :142:{38,49}]\n wire _a_bigger_T_1 = a_d_ext[63];\t// @[AtomicAutomata.scala:138:41, :143:50]\n wire _a_bigger_T_2 = _a_bigger_T == _a_bigger_T_1;\t// @[AtomicAutomata.scala:143:{35,39,50}]\n wire _a_bigger_T_3 = adder_out[63];\t// @[AtomicAutomata.scala:140:33, :143:65]\n wire _a_bigger_T_4 = ~_a_bigger_T_3;\t// @[AtomicAutomata.scala:143:{55,65}]\n wire a_bigger = _a_bigger_T_2 ? _a_bigger_T_4 : a_bigger_uneq;\t// @[AtomicAutomata.scala:142:38, :143:{27,39,55}]\n wire pick_a = take_max == a_bigger;\t// @[AtomicAutomata.scala:124:42, :143:27, :144:31]\n wire [63:0] _arith_out_T = pick_a ? cam_a_0_bits_data : cam_d_0_data;\t// @[AtomicAutomata.scala:83:24, :84:24, :144:31, :145:50]\n wire [63:0] arith_out = adder ? adder_out : _arith_out_T;\t// @[AtomicAutomata.scala:125:39, :140:33, :145:{28,50}]\n wire _amo_data_T = cam_a_0_bits_opcode[0];\t// @[AtomicAutomata.scala:83:24, :151:34]\n wire [63:0] amo_data = _amo_data_T ? logic_out : arith_out;\t// @[AtomicAutomata.scala:120:28, :145:28, :151:{14,34}]\n wire [63:0] source_c_bits_a_data = amo_data;\t// @[Edges.scala:480:17]\n wire _source_i_ready_T;\t// @[Arbiter.scala:94:31]\n wire _source_i_valid_T;\t// @[AtomicAutomata.scala:157:38]\n wire [2:0] source_i_bits_opcode;\t// @[AtomicAutomata.scala:154:28]\n wire [2:0] source_i_bits_param;\t// @[AtomicAutomata.scala:154:28]\n wire source_i_ready;\t// @[AtomicAutomata.scala:154:28]\n wire source_i_valid;\t// @[AtomicAutomata.scala:154:28]\n wire _a_allow_T = ~a_cam_busy;\t// @[AtomicAutomata.scala:111:96, :155:23]\n wire _a_allow_T_1 = a_isSupported | cam_free_0;\t// @[AtomicAutomata.scala:86:44, :98:32, :155:53]\n wire a_allow = _a_allow_T & _a_allow_T_1;\t// @[AtomicAutomata.scala:155:{23,35,53}]\n assign _nodeIn_a_ready_T = source_i_ready & a_allow;\t// @[AtomicAutomata.scala:154:28, :155:35, :156:38]\n assign nodeIn_a_ready = _nodeIn_a_ready_T;\t// @[AtomicAutomata.scala:156:38]\n assign _source_i_valid_T = nodeIn_a_valid & a_allow;\t// @[AtomicAutomata.scala:155:35, :157:38]\n assign source_i_valid = _source_i_valid_T;\t// @[AtomicAutomata.scala:154:28, :157:38]\n assign source_i_bits_opcode = a_isSupported ? nodeIn_a_bits_opcode : 3'h4;\t// @[AtomicAutomata.scala:98:32, :154:28, :158:24, :159:31, :160:32]\n assign source_i_bits_param = a_isSupported ? nodeIn_a_bits_param : 3'h0;\t// @[AtomicAutomata.scala:98:32, :154:28, :158:24, :159:31, :161:32]\n wire _source_c_ready_T;\t// @[Arbiter.scala:94:31]\n wire [7:0] source_c_bits_a_mask;\t// @[Edges.scala:480:17]\n wire source_c_bits_a_corrupt;\t// @[Edges.scala:480:17]\n wire [3:0] source_c_bits_size;\t// @[AtomicAutomata.scala:165:28]\n wire [6:0] source_c_bits_source;\t// @[AtomicAutomata.scala:165:28]\n wire [31:0] source_c_bits_address;\t// @[AtomicAutomata.scala:165:28]\n wire [7:0] source_c_bits_mask;\t// @[AtomicAutomata.scala:165:28]\n wire [63:0] source_c_bits_data;\t// @[AtomicAutomata.scala:165:28]\n wire source_c_bits_corrupt;\t// @[AtomicAutomata.scala:165:28]\n wire source_c_ready;\t// @[AtomicAutomata.scala:165:28]\n wire _source_c_bits_T = cam_a_0_bits_corrupt | cam_d_0_corrupt;\t// @[AtomicAutomata.scala:83:24, :84:24, :172:45]\n assign source_c_bits_a_corrupt = _source_c_bits_T;\t// @[Edges.scala:480:17]\n wire _source_c_bits_legal_T_1 = cam_a_0_bits_size < 4'hD;\t// @[AtomicAutomata.scala:83:24]\n wire _source_c_bits_legal_T_2 = _source_c_bits_legal_T_1;\t// @[Parameters.scala:92:{33,38}]\n wire _source_c_bits_legal_T_3 = _source_c_bits_legal_T_2;\t// @[Parameters.scala:684:29]\n wire [31:0] _source_c_bits_legal_T_4 = {cam_a_0_bits_address[31:14], cam_a_0_bits_address[13:0] ^ 14'h3000};\t// @[AtomicAutomata.scala:83:24]\n wire [32:0] _source_c_bits_legal_T_5 = {1'h0, _source_c_bits_legal_T_4};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _source_c_bits_legal_T_6 = _source_c_bits_legal_T_5 & 33'h8A113000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _source_c_bits_legal_T_7 = _source_c_bits_legal_T_6;\t// @[Parameters.scala:137:46]\n wire _source_c_bits_legal_T_8 = _source_c_bits_legal_T_7 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire _source_c_bits_legal_T_9 = _source_c_bits_legal_T_3 & _source_c_bits_legal_T_8;\t// @[Parameters.scala:684:{29,54}]\n wire _source_c_bits_legal_T_51 = _source_c_bits_legal_T_9;\t// @[Parameters.scala:684:54, :686:26]\n wire _source_c_bits_legal_T_11 = cam_a_0_bits_size < 4'h7;\t// @[AtomicAutomata.scala:83:24]\n wire _source_c_bits_legal_T_12 = _source_c_bits_legal_T_11;\t// @[Parameters.scala:92:{33,38}]\n wire _source_c_bits_legal_T_13 = _source_c_bits_legal_T_12;\t// @[Parameters.scala:684:29]\n wire [32:0] _source_c_bits_legal_T_15 = {1'h0, _source_c_bits_legal_T_14};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _source_c_bits_legal_T_16 = _source_c_bits_legal_T_15 & 33'h8A112000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _source_c_bits_legal_T_17 = _source_c_bits_legal_T_16;\t// @[Parameters.scala:137:46]\n wire _source_c_bits_legal_T_18 = _source_c_bits_legal_T_17 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire [31:0] _source_c_bits_legal_T_19 = {cam_a_0_bits_address[31:21], cam_a_0_bits_address[20:0] ^ 21'h100000};\t// @[AtomicAutomata.scala:83:24]\n wire [32:0] _source_c_bits_legal_T_20 = {1'h0, _source_c_bits_legal_T_19};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _source_c_bits_legal_T_21 = _source_c_bits_legal_T_20 & 33'h8A103000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _source_c_bits_legal_T_22 = _source_c_bits_legal_T_21;\t// @[Parameters.scala:137:46]\n wire _source_c_bits_legal_T_23 = _source_c_bits_legal_T_22 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire [31:0] _source_c_bits_legal_T_24 = {cam_a_0_bits_address[31:26], cam_a_0_bits_address[25:0] ^ 26'h2000000};\t// @[AtomicAutomata.scala:83:24]\n wire [32:0] _source_c_bits_legal_T_25 = {1'h0, _source_c_bits_legal_T_24};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _source_c_bits_legal_T_26 = _source_c_bits_legal_T_25 & 33'h8A110000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _source_c_bits_legal_T_27 = _source_c_bits_legal_T_26;\t// @[Parameters.scala:137:46]\n wire _source_c_bits_legal_T_28 = _source_c_bits_legal_T_27 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire [31:0] _source_c_bits_legal_T_29 = {cam_a_0_bits_address[31:28], cam_a_0_bits_address[27:0] ^ 28'h8000000};\t// @[AtomicAutomata.scala:83:24]\n wire [32:0] _source_c_bits_legal_T_30 = {1'h0, _source_c_bits_legal_T_29};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _source_c_bits_legal_T_31 = _source_c_bits_legal_T_30 & 33'h88000000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _source_c_bits_legal_T_32 = _source_c_bits_legal_T_31;\t// @[Parameters.scala:137:46]\n wire _source_c_bits_legal_T_33 = _source_c_bits_legal_T_32 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire [31:0] _source_c_bits_legal_T_34 = cam_a_0_bits_address ^ 32'h80000000;\t// @[AtomicAutomata.scala:83:24]\n wire [32:0] _source_c_bits_legal_T_35 = {1'h0, _source_c_bits_legal_T_34};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _source_c_bits_legal_T_36 = _source_c_bits_legal_T_35 & 33'h8A110000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _source_c_bits_legal_T_37 = _source_c_bits_legal_T_36;\t// @[Parameters.scala:137:46]\n wire _source_c_bits_legal_T_38 = _source_c_bits_legal_T_37 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire _source_c_bits_legal_T_39 = _source_c_bits_legal_T_18 | _source_c_bits_legal_T_23;\t// @[Parameters.scala:685:42]\n wire _source_c_bits_legal_T_40 = _source_c_bits_legal_T_39 | _source_c_bits_legal_T_28;\t// @[Parameters.scala:685:42]\n wire _source_c_bits_legal_T_41 = _source_c_bits_legal_T_40 | _source_c_bits_legal_T_33;\t// @[Parameters.scala:685:42]\n wire _source_c_bits_legal_T_42 = _source_c_bits_legal_T_41 | _source_c_bits_legal_T_38;\t// @[Parameters.scala:685:42]\n wire _source_c_bits_legal_T_43 = _source_c_bits_legal_T_13 & _source_c_bits_legal_T_42;\t// @[Parameters.scala:684:{29,54}, :685:42]\n wire [31:0] _source_c_bits_legal_T_45 = {cam_a_0_bits_address[31:17], cam_a_0_bits_address[16:0] ^ 17'h10000};\t// @[AtomicAutomata.scala:83:24]\n wire [32:0] _source_c_bits_legal_T_46 = {1'h0, _source_c_bits_legal_T_45};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _source_c_bits_legal_T_47 = _source_c_bits_legal_T_46 & 33'h8A110000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _source_c_bits_legal_T_48 = _source_c_bits_legal_T_47;\t// @[Parameters.scala:137:46]\n wire _source_c_bits_legal_T_49 = _source_c_bits_legal_T_48 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire _source_c_bits_legal_T_52 = _source_c_bits_legal_T_51 | _source_c_bits_legal_T_43;\t// @[Parameters.scala:684:54, :686:26]\n wire source_c_bits_legal = _source_c_bits_legal_T_52;\t// @[Parameters.scala:686:26]\n assign source_c_bits_size = source_c_bits_a_size;\t// @[Edges.scala:480:17]\n assign source_c_bits_source = source_c_bits_a_source;\t// @[Edges.scala:480:17]\n assign source_c_bits_address = source_c_bits_a_address;\t// @[Edges.scala:480:17]\n wire [7:0] _source_c_bits_a_mask_T;\t// @[Misc.scala:222:10]\n assign source_c_bits_mask = source_c_bits_a_mask;\t// @[Edges.scala:480:17]\n assign source_c_bits_data = source_c_bits_a_data;\t// @[Edges.scala:480:17]\n assign source_c_bits_corrupt = source_c_bits_a_corrupt;\t// @[Edges.scala:480:17]\n wire [1:0] source_c_bits_a_mask_sizeOH_shiftAmount = _source_c_bits_a_mask_sizeOH_T[1:0];\t// @[OneHot.scala:64:49]\n wire [3:0] _source_c_bits_a_mask_sizeOH_T_1 = 4'h1 << source_c_bits_a_mask_sizeOH_shiftAmount;\t// @[OneHot.scala:64:49, :65:12]\n wire [2:0] _source_c_bits_a_mask_sizeOH_T_2 = _source_c_bits_a_mask_sizeOH_T_1[2:0];\t// @[OneHot.scala:65:{12,27}]\n wire [2:0] source_c_bits_a_mask_sizeOH = {_source_c_bits_a_mask_sizeOH_T_2[2:1], 1'h1};\t// @[OneHot.scala:65:27]\n wire source_c_bits_a_mask_sub_sub_sub_0_1 = cam_a_0_bits_size > 4'h2;\t// @[Misc.scala:206:21]\n wire source_c_bits_a_mask_sub_sub_size = source_c_bits_a_mask_sizeOH[2];\t// @[Misc.scala:202:81, :209:26]\n wire source_c_bits_a_mask_sub_sub_bit = cam_a_0_bits_address[2];\t// @[Misc.scala:210:26]\n wire source_c_bits_a_mask_sub_sub_1_2 = source_c_bits_a_mask_sub_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire source_c_bits_a_mask_sub_sub_nbit = ~source_c_bits_a_mask_sub_sub_bit;\t// @[Misc.scala:210:26, :211:20]\n wire source_c_bits_a_mask_sub_sub_0_2 = source_c_bits_a_mask_sub_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _source_c_bits_a_mask_sub_sub_acc_T = source_c_bits_a_mask_sub_sub_size & source_c_bits_a_mask_sub_sub_0_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire source_c_bits_a_mask_sub_sub_0_1 = source_c_bits_a_mask_sub_sub_sub_0_1 | _source_c_bits_a_mask_sub_sub_acc_T;\t// @[Misc.scala:206:21, :215:{29,38}]\n wire _source_c_bits_a_mask_sub_sub_acc_T_1 = source_c_bits_a_mask_sub_sub_size & source_c_bits_a_mask_sub_sub_1_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire source_c_bits_a_mask_sub_sub_1_1 = source_c_bits_a_mask_sub_sub_sub_0_1 | _source_c_bits_a_mask_sub_sub_acc_T_1;\t// @[Misc.scala:206:21, :215:{29,38}]\n wire source_c_bits_a_mask_sub_size = source_c_bits_a_mask_sizeOH[1];\t// @[Misc.scala:202:81, :209:26]\n wire source_c_bits_a_mask_sub_bit = cam_a_0_bits_address[1];\t// @[Misc.scala:210:26]\n wire source_c_bits_a_mask_sub_nbit = ~source_c_bits_a_mask_sub_bit;\t// @[Misc.scala:210:26, :211:20]\n wire source_c_bits_a_mask_sub_0_2 = source_c_bits_a_mask_sub_sub_0_2 & source_c_bits_a_mask_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _source_c_bits_a_mask_sub_acc_T = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_0_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire source_c_bits_a_mask_sub_0_1 = source_c_bits_a_mask_sub_sub_0_1 | _source_c_bits_a_mask_sub_acc_T;\t// @[Misc.scala:215:{29,38}]\n wire source_c_bits_a_mask_sub_1_2 = source_c_bits_a_mask_sub_sub_0_2 & source_c_bits_a_mask_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _source_c_bits_a_mask_sub_acc_T_1 = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_1_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire source_c_bits_a_mask_sub_1_1 = source_c_bits_a_mask_sub_sub_0_1 | _source_c_bits_a_mask_sub_acc_T_1;\t// @[Misc.scala:215:{29,38}]\n wire source_c_bits_a_mask_sub_2_2 = source_c_bits_a_mask_sub_sub_1_2 & source_c_bits_a_mask_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _source_c_bits_a_mask_sub_acc_T_2 = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_2_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire source_c_bits_a_mask_sub_2_1 = source_c_bits_a_mask_sub_sub_1_1 | _source_c_bits_a_mask_sub_acc_T_2;\t// @[Misc.scala:215:{29,38}]\n wire source_c_bits_a_mask_sub_3_2 = source_c_bits_a_mask_sub_sub_1_2 & source_c_bits_a_mask_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _source_c_bits_a_mask_sub_acc_T_3 = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_3_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire source_c_bits_a_mask_sub_3_1 = source_c_bits_a_mask_sub_sub_1_1 | _source_c_bits_a_mask_sub_acc_T_3;\t// @[Misc.scala:215:{29,38}]\n wire source_c_bits_a_mask_size = source_c_bits_a_mask_sizeOH[0];\t// @[Misc.scala:202:81, :209:26]\n wire source_c_bits_a_mask_bit = cam_a_0_bits_address[0];\t// @[Misc.scala:210:26]\n wire source_c_bits_a_mask_nbit = ~source_c_bits_a_mask_bit;\t// @[Misc.scala:210:26, :211:20]\n wire source_c_bits_a_mask_eq = source_c_bits_a_mask_sub_0_2 & source_c_bits_a_mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _source_c_bits_a_mask_acc_T = source_c_bits_a_mask_size & source_c_bits_a_mask_eq;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire source_c_bits_a_mask_acc = source_c_bits_a_mask_sub_0_1 | _source_c_bits_a_mask_acc_T;\t// @[Misc.scala:215:{29,38}]\n wire source_c_bits_a_mask_eq_1 = source_c_bits_a_mask_sub_0_2 & source_c_bits_a_mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _source_c_bits_a_mask_acc_T_1 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_1;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire source_c_bits_a_mask_acc_1 = source_c_bits_a_mask_sub_0_1 | _source_c_bits_a_mask_acc_T_1;\t// @[Misc.scala:215:{29,38}]\n wire source_c_bits_a_mask_eq_2 = source_c_bits_a_mask_sub_1_2 & source_c_bits_a_mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _source_c_bits_a_mask_acc_T_2 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire source_c_bits_a_mask_acc_2 = source_c_bits_a_mask_sub_1_1 | _source_c_bits_a_mask_acc_T_2;\t// @[Misc.scala:215:{29,38}]\n wire source_c_bits_a_mask_eq_3 = source_c_bits_a_mask_sub_1_2 & source_c_bits_a_mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _source_c_bits_a_mask_acc_T_3 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_3;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire source_c_bits_a_mask_acc_3 = source_c_bits_a_mask_sub_1_1 | _source_c_bits_a_mask_acc_T_3;\t// @[Misc.scala:215:{29,38}]\n wire source_c_bits_a_mask_eq_4 = source_c_bits_a_mask_sub_2_2 & source_c_bits_a_mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _source_c_bits_a_mask_acc_T_4 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_4;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire source_c_bits_a_mask_acc_4 = source_c_bits_a_mask_sub_2_1 | _source_c_bits_a_mask_acc_T_4;\t// @[Misc.scala:215:{29,38}]\n wire source_c_bits_a_mask_eq_5 = source_c_bits_a_mask_sub_2_2 & source_c_bits_a_mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _source_c_bits_a_mask_acc_T_5 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_5;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire source_c_bits_a_mask_acc_5 = source_c_bits_a_mask_sub_2_1 | _source_c_bits_a_mask_acc_T_5;\t// @[Misc.scala:215:{29,38}]\n wire source_c_bits_a_mask_eq_6 = source_c_bits_a_mask_sub_3_2 & source_c_bits_a_mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _source_c_bits_a_mask_acc_T_6 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_6;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire source_c_bits_a_mask_acc_6 = source_c_bits_a_mask_sub_3_1 | _source_c_bits_a_mask_acc_T_6;\t// @[Misc.scala:215:{29,38}]\n wire source_c_bits_a_mask_eq_7 = source_c_bits_a_mask_sub_3_2 & source_c_bits_a_mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _source_c_bits_a_mask_acc_T_7 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_7;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire source_c_bits_a_mask_acc_7 = source_c_bits_a_mask_sub_3_1 | _source_c_bits_a_mask_acc_T_7;\t// @[Misc.scala:215:{29,38}]\n wire [1:0] source_c_bits_a_mask_lo_lo = {source_c_bits_a_mask_acc_1, source_c_bits_a_mask_acc};\t// @[Misc.scala:215:29, :222:10]\n wire [1:0] source_c_bits_a_mask_lo_hi = {source_c_bits_a_mask_acc_3, source_c_bits_a_mask_acc_2};\t// @[Misc.scala:215:29, :222:10]\n wire [3:0] source_c_bits_a_mask_lo = {source_c_bits_a_mask_lo_hi, source_c_bits_a_mask_lo_lo};\t// @[Misc.scala:222:10]\n wire [1:0] source_c_bits_a_mask_hi_lo = {source_c_bits_a_mask_acc_5, source_c_bits_a_mask_acc_4};\t// @[Misc.scala:215:29, :222:10]\n wire [1:0] source_c_bits_a_mask_hi_hi = {source_c_bits_a_mask_acc_7, source_c_bits_a_mask_acc_6};\t// @[Misc.scala:215:29, :222:10]\n wire [3:0] source_c_bits_a_mask_hi = {source_c_bits_a_mask_hi_hi, source_c_bits_a_mask_hi_lo};\t// @[Misc.scala:222:10]\n assign _source_c_bits_a_mask_T = {source_c_bits_a_mask_hi, source_c_bits_a_mask_lo};\t// @[Misc.scala:222:10]\n assign source_c_bits_a_mask = _source_c_bits_a_mask_T;\t// @[Misc.scala:222:10]\n wire [26:0] _decode_T = 27'hFFF << nodeIn_a_bits_size;\t// @[package.scala:243:71]\n wire [11:0] _decode_T_1 = _decode_T[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _decode_T_2 = ~_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [8:0] decode = _decode_T_2[11:3];\t// @[package.scala:243:46]\n wire _opdata_T = nodeIn_a_bits_opcode[2];\t// @[Edges.scala:92:37]\n wire opdata = ~_opdata_T;\t// @[Edges.scala:92:{28,37}]\n reg [8:0] beatsLeft;\t// @[Arbiter.scala:60:30]\n wire idle = beatsLeft == 9'h0;\t// @[Arbiter.scala:60:30, :61:28]\n wire latch = idle & nodeOut_a_ready;\t// @[Arbiter.scala:61:28, :62:24]\n wire [1:0] _readys_T = {source_i_valid, source_c_valid};\t// @[AtomicAutomata.scala:154:28, :165:28]\n wire [2:0] _readys_T_1 = {_readys_T, 1'h0};\t// @[package.scala:253:48]\n wire [1:0] _readys_T_2 = _readys_T_1[1:0];\t// @[package.scala:253:{48,53}]\n wire [1:0] _readys_T_3 = _readys_T | _readys_T_2;\t// @[package.scala:253:{43,53}]\n wire [1:0] _readys_T_4 = _readys_T_3;\t// @[package.scala:253:43, :254:17]\n wire [2:0] _readys_T_5 = {_readys_T_4, 1'h0};\t// @[package.scala:254:17]\n wire [1:0] _readys_T_6 = _readys_T_5[1:0];\t// @[Arbiter.scala:16:{78,83}]\n wire [1:0] _readys_T_7 = ~_readys_T_6;\t// @[Arbiter.scala:16:{61,83}]\n wire _readys_T_8 = _readys_T_7[0];\t// @[Arbiter.scala:16:61, :68:76]\n wire readys_0 = _readys_T_8;\t// @[Arbiter.scala:68:{27,76}]\n wire _readys_T_9 = _readys_T_7[1];\t// @[Arbiter.scala:16:61, :68:76]\n wire readys_1 = _readys_T_9;\t// @[Arbiter.scala:68:{27,76}]\n wire _winner_T = readys_0 & source_c_valid;\t// @[AtomicAutomata.scala:165:28]\n wire winner_0 = _winner_T;\t// @[Arbiter.scala:71:{27,69}]\n wire _winner_T_1 = readys_1 & source_i_valid;\t// @[AtomicAutomata.scala:154:28]\n wire winner_1 = _winner_T_1;\t// @[Arbiter.scala:71:{27,69}]\n wire prefixOR_1 = winner_0;\t// @[Arbiter.scala:71:27, :76:48]\n wire _prefixOR_T = prefixOR_1 | winner_1;\t// @[Arbiter.scala:71:27, :76:48]\n wire _nodeOut_a_valid_T = source_c_valid | source_i_valid;\t// @[AtomicAutomata.scala:154:28, :165:28]"}}},{"rowIdx":34390,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module InputUnit_59 : \n input clock : Clock \n input reset : Reset \n output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, flip out_credit_available : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<3>, sa_stall : UInt<3>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}} \n\n\n inst input_buffer of InputBuffer_59 \n connect input_buffer.clock, clock\n\n connect input_buffer.reset, reset\n\n connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id \n connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id \n connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node \n connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id \n connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node \n connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id \n connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload \n connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail \n connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head \n connect input_buffer.io.enq[0].valid, io.in.flit[0].valid \n connect input_buffer.io.deq[0].ready, UInt<1>(0h0) \n connect input_buffer.io.deq[1].ready, UInt<1>(0h0) \n connect input_buffer.io.deq[2].ready, UInt<1>(0h0) \n connect input_buffer.io.deq[3].ready, UInt<1>(0h0) \n connect input_buffer.io.deq[4].ready, UInt<1>(0h0) \n connect input_buffer.io.deq[5].ready, UInt<1>(0h0) \n connect input_buffer.io.deq[6].ready, UInt<1>(0h0) \n connect input_buffer.io.deq[7].ready, UInt<1>(0h0) \n inst route_arbiter of Arbiter8_RouteComputerReq_59 \n connect route_arbiter.clock, clock\n\n connect route_arbiter.reset, reset\n\n connect io.router_req.bits, route_arbiter.io.out.bits \n connect io.router_req.valid, route_arbiter.io.out.valid \n connect route_arbiter.io.out.ready, io.router_req.ready \n reg states : { g : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, fifo_deps : UInt<8>}[8], clock \n node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) \n when _T : \n node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h8)) \n node _T_2 = asUInt(reset) \n node _T_3 = eq(_T_2, UInt<1>(0h0)) \n when _T_3 : \n node _T_4 = eq(_T_1, UInt<1>(0h0)) \n when _T_4 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\\n\") : printf \n assert(clock, _T_1, UInt<1>(0h1), \"\") : assert \n node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) \n node _T_6 = asUInt(reset) \n node _T_7 = eq(_T_6, UInt<1>(0h0)) \n when _T_7 : \n node _T_8 = eq(_T_5, UInt<1>(0h0)) \n when _T_8 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at InputUnit.scala:208 assert(states(id).g === g_i)\\n\") : printf_1 \n assert(clock, _T_5, UInt<1>(0h1), \"\") : assert_1 \n node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<5>(0h1b)) \n node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) \n connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T \n connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) \n connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) \n connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0) \n connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0) \n connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0) \n connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[5], UInt<1>(0h0) \n connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[6], UInt<1>(0h0) \n connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[7], UInt<1>(0h0) \n connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) \n connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0) \n connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0) \n connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[3], UInt<1>(0h0) \n connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[4], UInt<1>(0h0) \n connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[5], UInt<1>(0h0) \n connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[6], UInt<1>(0h0) \n connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[7], UInt<1>(0h0) \n connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0) \n connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0) \n connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[2], UInt<1>(0h0) \n connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[3], UInt<1>(0h0) \n connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[4], UInt<1>(0h0) \n connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[5], UInt<1>(0h0) \n connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[6], UInt<1>(0h0) \n connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[7], UInt<1>(0h0) \n connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0) \n connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[1], UInt<1>(0h0) \n connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[2], UInt<1>(0h0) \n connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[3], UInt<1>(0h0) \n connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[4], UInt<1>(0h0) \n connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[5], UInt<1>(0h0) \n connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[6], UInt<1>(0h0) \n connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[7], UInt<1>(0h0) \n connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow \n node _route_arbiter_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h1)) \n connect route_arbiter.io.in[0].valid, _route_arbiter_io_in_0_valid_T \n connect route_arbiter.io.in[0].bits.flow.egress_node_id, states[0].flow.egress_node_id \n connect route_arbiter.io.in[0].bits.flow.egress_node, states[0].flow.egress_node \n connect route_arbiter.io.in[0].bits.flow.ingress_node_id, states[0].flow.ingress_node_id \n connect route_arbiter.io.in[0].bits.flow.ingress_node, states[0].flow.ingress_node \n connect route_arbiter.io.in[0].bits.flow.vnet_id, states[0].flow.vnet_id \n connect route_arbiter.io.in[0].bits.src_virt_id, UInt<1>(0h0) \n node _T_9 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid) \n when _T_9 : \n connect states[0].g, UInt<3>(0h2) \n node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1)) \n connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T \n connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id \n connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node \n connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id \n connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node \n connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id \n connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1) \n node _T_10 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) \n when _T_10 : \n connect states[1].g, UInt<3>(0h2) \n node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1)) \n connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T \n connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id \n connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node \n connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id \n connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node \n connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id \n connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2) \n node _T_11 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid) \n when _T_11 : \n connect states[2].g, UInt<3>(0h2) \n node _route_arbiter_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h1)) \n connect route_arbiter.io.in[3].valid, _route_arbiter_io_in_3_valid_T \n connect route_arbiter.io.in[3].bits.flow.egress_node_id, states[3].flow.egress_node_id \n connect route_arbiter.io.in[3].bits.flow.egress_node, states[3].flow.egress_node \n connect route_arbiter.io.in[3].bits.flow.ingress_node_id, states[3].flow.ingress_node_id \n connect route_arbiter.io.in[3].bits.flow.ingress_node, states[3].flow.ingress_node \n connect route_arbiter.io.in[3].bits.flow.vnet_id, states[3].flow.vnet_id \n connect route_arbiter.io.in[3].bits.src_virt_id, UInt<2>(0h3) \n node _T_12 = and(route_arbiter.io.in[3].ready, route_arbiter.io.in[3].valid) \n when _T_12 : \n connect states[3].g, UInt<3>(0h2) \n node _route_arbiter_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h1)) \n connect route_arbiter.io.in[4].valid, _route_arbiter_io_in_4_valid_T \n connect route_arbiter.io.in[4].bits.flow.egress_node_id, states[4].flow.egress_node_id \n connect route_arbiter.io.in[4].bits.flow.egress_node, states[4].flow.egress_node \n connect route_arbiter.io.in[4].bits.flow.ingress_node_id, states[4].flow.ingress_node_id \n connect route_arbiter.io.in[4].bits.flow.ingress_node, states[4].flow.ingress_node \n connect route_arbiter.io.in[4].bits.flow.vnet_id, states[4].flow.vnet_id \n connect route_arbiter.io.in[4].bits.src_virt_id, UInt<3>(0h4) \n node _T_13 = and(route_arbiter.io.in[4].ready, route_arbiter.io.in[4].valid) \n when _T_13 : \n connect states[4].g, UInt<3>(0h2) \n node _route_arbiter_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h1)) \n connect route_arbiter.io.in[5].valid, _route_arbiter_io_in_5_valid_T \n connect route_arbiter.io.in[5].bits.flow.egress_node_id, states[5].flow.egress_node_id \n connect route_arbiter.io.in[5].bits.flow.egress_node, states[5].flow.egress_node \n connect route_arbiter.io.in[5].bits.flow.ingress_node_id, states[5].flow.ingress_node_id \n connect route_arbiter.io.in[5].bits.flow.ingress_node, states[5].flow.ingress_node \n connect route_arbiter.io.in[5].bits.flow.vnet_id, states[5].flow.vnet_id \n connect route_arbiter.io.in[5].bits.src_virt_id, UInt<3>(0h5) \n node _T_14 = and(route_arbiter.io.in[5].ready, route_arbiter.io.in[5].valid) \n when _T_14 : \n connect states[5].g, UInt<3>(0h2) \n node _route_arbiter_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h1)) \n connect route_arbiter.io.in[6].valid, _route_arbiter_io_in_6_valid_T \n connect route_arbiter.io.in[6].bits.flow.egress_node_id, states[6].flow.egress_node_id \n connect route_arbiter.io.in[6].bits.flow.egress_node, states[6].flow.egress_node \n connect route_arbiter.io.in[6].bits.flow.ingress_node_id, states[6].flow.ingress_node_id \n connect route_arbiter.io.in[6].bits.flow.ingress_node, states[6].flow.ingress_node \n connect route_arbiter.io.in[6].bits.flow.vnet_id, states[6].flow.vnet_id \n connect route_arbiter.io.in[6].bits.src_virt_id, UInt<3>(0h6) \n node _T_15 = and(route_arbiter.io.in[6].ready, route_arbiter.io.in[6].valid) \n when _T_15 : \n connect states[6].g, UInt<3>(0h2) \n node _route_arbiter_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h1)) \n connect route_arbiter.io.in[7].valid, _route_arbiter_io_in_7_valid_T \n connect route_arbiter.io.in[7].bits.flow.egress_node_id, states[7].flow.egress_node_id \n connect route_arbiter.io.in[7].bits.flow.egress_node, states[7].flow.egress_node \n connect route_arbiter.io.in[7].bits.flow.ingress_node_id, states[7].flow.ingress_node_id \n connect route_arbiter.io.in[7].bits.flow.ingress_node, states[7].flow.ingress_node \n connect route_arbiter.io.in[7].bits.flow.vnet_id, states[7].flow.vnet_id \n connect route_arbiter.io.in[7].bits.src_virt_id, UInt<3>(0h7) \n node _T_16 = and(route_arbiter.io.in[7].ready, route_arbiter.io.in[7].valid) \n when _T_16 : \n connect states[7].g, UInt<3>(0h2) \n node _T_17 = and(io.router_req.ready, io.router_req.valid) \n when _T_17 : \n node _T_18 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) \n node _T_19 = asUInt(reset) \n node _T_20 = eq(_T_19, UInt<1>(0h0)) \n when _T_20 : \n node _T_21 = eq(_T_18, UInt<1>(0h0)) \n when _T_21 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at InputUnit.scala:241 assert(states(id).g === g_r)\\n\") : printf_2 \n assert(clock, _T_18, UInt<1>(0h1), \"\") : assert_2 \n connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) \n node _T_22 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) \n when _T_22 : \n connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` \n connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` \n connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2` \n connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3` \n node _T_23 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) \n when _T_23 : \n connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` \n connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` \n connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2` \n connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3` \n node _T_24 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id) \n when _T_24 : \n connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0` \n connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1` \n connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2` \n connect states[2].vc_sel.`3`, io.router_resp.vc_sel.`3` \n node _T_25 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id) \n when _T_25 : \n connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0` \n connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1` \n connect states[3].vc_sel.`2`, io.router_resp.vc_sel.`2` \n connect states[3].vc_sel.`3`, io.router_resp.vc_sel.`3` \n node _T_26 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id) \n when _T_26 : \n connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0` \n connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1` \n connect states[4].vc_sel.`2`, io.router_resp.vc_sel.`2` \n connect states[4].vc_sel.`3`, io.router_resp.vc_sel.`3` \n node _T_27 = eq(UInt<3>(0h5), io.router_req.bits.src_virt_id) \n when _T_27 : \n connect states[5].vc_sel.`0`, io.router_resp.vc_sel.`0` \n connect states[5].vc_sel.`1`, io.router_resp.vc_sel.`1` \n connect states[5].vc_sel.`2`, io.router_resp.vc_sel.`2` \n connect states[5].vc_sel.`3`, io.router_resp.vc_sel.`3` \n node _T_28 = eq(UInt<3>(0h6), io.router_req.bits.src_virt_id) \n when _T_28 : \n connect states[6].vc_sel.`0`, io.router_resp.vc_sel.`0` \n connect states[6].vc_sel.`1`, io.router_resp.vc_sel.`1` \n connect states[6].vc_sel.`2`, io.router_resp.vc_sel.`2` \n connect states[6].vc_sel.`3`, io.router_resp.vc_sel.`3` \n node _T_29 = eq(UInt<3>(0h7), io.router_req.bits.src_virt_id) \n when _T_29 : \n connect states[7].vc_sel.`0`, io.router_resp.vc_sel.`0` \n connect states[7].vc_sel.`1`, io.router_resp.vc_sel.`1` \n connect states[7].vc_sel.`2`, io.router_resp.vc_sel.`2` \n connect states[7].vc_sel.`3`, io.router_resp.vc_sel.`3` \n regreset mask : UInt<8>, clock, reset, UInt<8>(0h0) \n wire vcalloc_reqs : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}[8] \n wire vcalloc_vals : UInt<1>[8] \n node vcalloc_filter_lo_lo = cat(vcalloc_vals[1], vcalloc_vals[0]) \n node vcalloc_filter_lo_hi = cat(vcalloc_vals[3], vcalloc_vals[2]) \n node vcalloc_filter_lo = cat(vcalloc_filter_lo_hi, vcalloc_filter_lo_lo) \n node vcalloc_filter_hi_lo = cat(vcalloc_vals[5], vcalloc_vals[4]) \n node vcalloc_filter_hi_hi = cat(vcalloc_vals[7], vcalloc_vals[6]) \n node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_filter_hi_lo) \n node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo) \n node vcalloc_filter_lo_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0]) \n node vcalloc_filter_lo_hi_1 = cat(vcalloc_vals[3], vcalloc_vals[2]) \n node vcalloc_filter_lo_1 = cat(vcalloc_filter_lo_hi_1, vcalloc_filter_lo_lo_1) \n node vcalloc_filter_hi_lo_1 = cat(vcalloc_vals[5], vcalloc_vals[4]) \n node vcalloc_filter_hi_hi_1 = cat(vcalloc_vals[7], vcalloc_vals[6]) \n node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_filter_hi_lo_1) \n node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1) \n node _vcalloc_filter_T_2 = not(mask) \n node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) \n node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) \n node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) \n node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) \n node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) \n node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) \n node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4) \n node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5) \n node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6) \n node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7) \n node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8) \n node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9) \n node _vcalloc_filter_T_15 = bits(_vcalloc_filter_T_4, 10, 10) \n node _vcalloc_filter_T_16 = bits(_vcalloc_filter_T_4, 11, 11) \n node _vcalloc_filter_T_17 = bits(_vcalloc_filter_T_4, 12, 12) \n node _vcalloc_filter_T_18 = bits(_vcalloc_filter_T_4, 13, 13) \n node _vcalloc_filter_T_19 = bits(_vcalloc_filter_T_4, 14, 14) \n node _vcalloc_filter_T_20 = bits(_vcalloc_filter_T_4, 15, 15) \n node _vcalloc_filter_T_21 = mux(_vcalloc_filter_T_20, UInt<16>(0h8000), UInt<16>(0h0)) \n node _vcalloc_filter_T_22 = mux(_vcalloc_filter_T_19, UInt<16>(0h4000), _vcalloc_filter_T_21) \n node _vcalloc_filter_T_23 = mux(_vcalloc_filter_T_18, UInt<16>(0h2000), _vcalloc_filter_T_22) \n node _vcalloc_filter_T_24 = mux(_vcalloc_filter_T_17, UInt<16>(0h1000), _vcalloc_filter_T_23) \n node _vcalloc_filter_T_25 = mux(_vcalloc_filter_T_16, UInt<16>(0h800), _vcalloc_filter_T_24) \n node _vcalloc_filter_T_26 = mux(_vcalloc_filter_T_15, UInt<16>(0h400), _vcalloc_filter_T_25) \n node _vcalloc_filter_T_27 = mux(_vcalloc_filter_T_14, UInt<16>(0h200), _vcalloc_filter_T_26) \n node _vcalloc_filter_T_28 = mux(_vcalloc_filter_T_13, UInt<16>(0h100), _vcalloc_filter_T_27) \n node _vcalloc_filter_T_29 = mux(_vcalloc_filter_T_12, UInt<16>(0h80), _vcalloc_filter_T_28) \n node _vcalloc_filter_T_30 = mux(_vcalloc_filter_T_11, UInt<16>(0h40), _vcalloc_filter_T_29) \n node _vcalloc_filter_T_31 = mux(_vcalloc_filter_T_10, UInt<16>(0h20), _vcalloc_filter_T_30) \n node _vcalloc_filter_T_32 = mux(_vcalloc_filter_T_9, UInt<16>(0h10), _vcalloc_filter_T_31) \n node _vcalloc_filter_T_33 = mux(_vcalloc_filter_T_8, UInt<16>(0h8), _vcalloc_filter_T_32) \n node _vcalloc_filter_T_34 = mux(_vcalloc_filter_T_7, UInt<16>(0h4), _vcalloc_filter_T_33) \n node _vcalloc_filter_T_35 = mux(_vcalloc_filter_T_6, UInt<16>(0h2), _vcalloc_filter_T_34) \n node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<16>(0h1), _vcalloc_filter_T_35) \n node _vcalloc_sel_T = bits(vcalloc_filter, 7, 0) \n node _vcalloc_sel_T_1 = shr(vcalloc_filter, 8) \n node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) \n node _T_30 = and(io.router_req.ready, io.router_req.valid) \n when _T_30 : \n node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) \n node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) \n node _mask_T_2 = tail(_mask_T_1, 1) \n connect mask, _mask_T_2 \n else :\n\n node _T_31 = or(vcalloc_vals[0], vcalloc_vals[1]) \n node _T_32 = or(_T_31, vcalloc_vals[2]) \n node _T_33 = or(_T_32, vcalloc_vals[3]) \n node _T_34 = or(_T_33, vcalloc_vals[4]) \n node _T_35 = or(_T_34, vcalloc_vals[5]) \n node _T_36 = or(_T_35, vcalloc_vals[6]) \n node _T_37 = or(_T_36, vcalloc_vals[7]) \n when _T_37 : \n node _mask_T_3 = not(UInt<1>(0h0)) \n node _mask_T_4 = not(UInt<2>(0h0)) \n node _mask_T_5 = not(UInt<3>(0h0)) \n node _mask_T_6 = not(UInt<4>(0h0)) \n node _mask_T_7 = not(UInt<5>(0h0)) \n node _mask_T_8 = not(UInt<6>(0h0)) \n node _mask_T_9 = not(UInt<7>(0h0)) \n node _mask_T_10 = not(UInt<8>(0h0)) \n node _mask_T_11 = bits(vcalloc_sel, 0, 0) \n node _mask_T_12 = bits(vcalloc_sel, 1, 1) \n node _mask_T_13 = bits(vcalloc_sel, 2, 2) \n node _mask_T_14 = bits(vcalloc_sel, 3, 3) \n node _mask_T_15 = bits(vcalloc_sel, 4, 4) \n node _mask_T_16 = bits(vcalloc_sel, 5, 5) \n node _mask_T_17 = bits(vcalloc_sel, 6, 6) \n node _mask_T_18 = bits(vcalloc_sel, 7, 7) \n node _mask_T_19 = mux(_mask_T_11, _mask_T_3, UInt<1>(0h0)) \n node _mask_T_20 = mux(_mask_T_12, _mask_T_4, UInt<1>(0h0)) \n node _mask_T_21 = mux(_mask_T_13, _mask_T_5, UInt<1>(0h0)) \n node _mask_T_22 = mux(_mask_T_14, _mask_T_6, UInt<1>(0h0)) \n node _mask_T_23 = mux(_mask_T_15, _mask_T_7, UInt<1>(0h0)) \n node _mask_T_24 = mux(_mask_T_16, _mask_T_8, UInt<1>(0h0)) \n node _mask_T_25 = mux(_mask_T_17, _mask_T_9, UInt<1>(0h0)) \n node _mask_T_26 = mux(_mask_T_18, _mask_T_10, UInt<1>(0h0)) \n node _mask_T_27 = or(_mask_T_19, _mask_T_20) \n node _mask_T_28 = or(_mask_T_27, _mask_T_21) \n node _mask_T_29 = or(_mask_T_28, _mask_T_22) \n node _mask_T_30 = or(_mask_T_29, _mask_T_23) \n node _mask_T_31 = or(_mask_T_30, _mask_T_24) \n node _mask_T_32 = or(_mask_T_31, _mask_T_25) \n node _mask_T_33 = or(_mask_T_32, _mask_T_26) \n wire _mask_WIRE : UInt<8> \n connect _mask_WIRE, _mask_T_33 \n connect mask, _mask_WIRE \n node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) \n node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2]) \n node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3]) \n node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4]) \n node _io_vcalloc_req_valid_T_4 = or(_io_vcalloc_req_valid_T_3, vcalloc_vals[5]) \n node _io_vcalloc_req_valid_T_5 = or(_io_vcalloc_req_valid_T_4, vcalloc_vals[6]) \n node _io_vcalloc_req_valid_T_6 = or(_io_vcalloc_req_valid_T_5, vcalloc_vals[7]) \n connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_6 \n node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) \n node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) \n node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2) \n node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3) \n node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4) \n node _io_vcalloc_req_bits_T_5 = bits(vcalloc_sel, 5, 5) \n node _io_vcalloc_req_bits_T_6 = bits(vcalloc_sel, 6, 6) \n node _io_vcalloc_req_bits_T_7 = bits(vcalloc_sel, 7, 7) \n wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}} \n wire _io_vcalloc_req_bits_WIRE_1 : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]} \n wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[8] \n node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[0], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[0], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[0], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9) \n node _io_vcalloc_req_bits_T_17 = or(_io_vcalloc_req_bits_T_16, _io_vcalloc_req_bits_T_10) \n node _io_vcalloc_req_bits_T_18 = or(_io_vcalloc_req_bits_T_17, _io_vcalloc_req_bits_T_11) \n node _io_vcalloc_req_bits_T_19 = or(_io_vcalloc_req_bits_T_18, _io_vcalloc_req_bits_T_12) \n node _io_vcalloc_req_bits_T_20 = or(_io_vcalloc_req_bits_T_19, _io_vcalloc_req_bits_T_13) \n node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_14) \n node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_15) \n wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> \n connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_22 \n connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 \n node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_26 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_27 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[1], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[1], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[1], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24) \n node _io_vcalloc_req_bits_T_32 = or(_io_vcalloc_req_bits_T_31, _io_vcalloc_req_bits_T_25) \n node _io_vcalloc_req_bits_T_33 = or(_io_vcalloc_req_bits_T_32, _io_vcalloc_req_bits_T_26) \n node _io_vcalloc_req_bits_T_34 = or(_io_vcalloc_req_bits_T_33, _io_vcalloc_req_bits_T_27) \n node _io_vcalloc_req_bits_T_35 = or(_io_vcalloc_req_bits_T_34, _io_vcalloc_req_bits_T_28) \n node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_35, _io_vcalloc_req_bits_T_29) \n node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_30) \n wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> \n connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_37 \n connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 \n node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_41 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_42 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[2], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[2], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[2], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39) \n node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_40) \n node _io_vcalloc_req_bits_T_48 = or(_io_vcalloc_req_bits_T_47, _io_vcalloc_req_bits_T_41) \n node _io_vcalloc_req_bits_T_49 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_42) \n node _io_vcalloc_req_bits_T_50 = or(_io_vcalloc_req_bits_T_49, _io_vcalloc_req_bits_T_43) \n node _io_vcalloc_req_bits_T_51 = or(_io_vcalloc_req_bits_T_50, _io_vcalloc_req_bits_T_44) \n node _io_vcalloc_req_bits_T_52 = or(_io_vcalloc_req_bits_T_51, _io_vcalloc_req_bits_T_45) \n wire _io_vcalloc_req_bits_WIRE_5 : UInt<1> \n connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_52 \n connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5 \n node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_56 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_57 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_58 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[3], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[3], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[3], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_53, _io_vcalloc_req_bits_T_54) \n node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_55) \n node _io_vcalloc_req_bits_T_63 = or(_io_vcalloc_req_bits_T_62, _io_vcalloc_req_bits_T_56) \n node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_57) \n node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_58) \n node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_59) \n node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_60) \n wire _io_vcalloc_req_bits_WIRE_6 : UInt<1> \n connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_67 \n connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6 \n node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_71 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[4], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[4], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[4], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69) \n node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_76, _io_vcalloc_req_bits_T_70) \n node _io_vcalloc_req_bits_T_78 = or(_io_vcalloc_req_bits_T_77, _io_vcalloc_req_bits_T_71) \n node _io_vcalloc_req_bits_T_79 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_72) \n node _io_vcalloc_req_bits_T_80 = or(_io_vcalloc_req_bits_T_79, _io_vcalloc_req_bits_T_73) \n node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_80, _io_vcalloc_req_bits_T_74) \n node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_75) \n wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> \n connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_82 \n connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7 \n node _io_vcalloc_req_bits_T_83 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[5], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_84 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[5], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_85 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[5], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[5], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[5], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[5], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[5], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[5], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_91 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_84) \n node _io_vcalloc_req_bits_T_92 = or(_io_vcalloc_req_bits_T_91, _io_vcalloc_req_bits_T_85) \n node _io_vcalloc_req_bits_T_93 = or(_io_vcalloc_req_bits_T_92, _io_vcalloc_req_bits_T_86) \n node _io_vcalloc_req_bits_T_94 = or(_io_vcalloc_req_bits_T_93, _io_vcalloc_req_bits_T_87) \n node _io_vcalloc_req_bits_T_95 = or(_io_vcalloc_req_bits_T_94, _io_vcalloc_req_bits_T_88) \n node _io_vcalloc_req_bits_T_96 = or(_io_vcalloc_req_bits_T_95, _io_vcalloc_req_bits_T_89) \n node _io_vcalloc_req_bits_T_97 = or(_io_vcalloc_req_bits_T_96, _io_vcalloc_req_bits_T_90) \n wire _io_vcalloc_req_bits_WIRE_8 : UInt<1> \n connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_97 \n connect _io_vcalloc_req_bits_WIRE_2[5], _io_vcalloc_req_bits_WIRE_8 \n node _io_vcalloc_req_bits_T_98 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[6], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_99 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[6], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_100 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[6], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_101 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[6], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_102 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[6], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_103 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[6], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_104 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[6], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[6], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_106 = or(_io_vcalloc_req_bits_T_98, _io_vcalloc_req_bits_T_99) \n node _io_vcalloc_req_bits_T_107 = or(_io_vcalloc_req_bits_T_106, _io_vcalloc_req_bits_T_100) \n node _io_vcalloc_req_bits_T_108 = or(_io_vcalloc_req_bits_T_107, _io_vcalloc_req_bits_T_101) \n node _io_vcalloc_req_bits_T_109 = or(_io_vcalloc_req_bits_T_108, _io_vcalloc_req_bits_T_102) \n node _io_vcalloc_req_bits_T_110 = or(_io_vcalloc_req_bits_T_109, _io_vcalloc_req_bits_T_103) \n node _io_vcalloc_req_bits_T_111 = or(_io_vcalloc_req_bits_T_110, _io_vcalloc_req_bits_T_104) \n node _io_vcalloc_req_bits_T_112 = or(_io_vcalloc_req_bits_T_111, _io_vcalloc_req_bits_T_105) \n wire _io_vcalloc_req_bits_WIRE_9 : UInt<1> \n connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_112 \n connect _io_vcalloc_req_bits_WIRE_2[6], _io_vcalloc_req_bits_WIRE_9 \n node _io_vcalloc_req_bits_T_113 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[7], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_114 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[7], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_115 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[7], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_116 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[7], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_117 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[7], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_118 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[7], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_119 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[7], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_120 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[7], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_121 = or(_io_vcalloc_req_bits_T_113, _io_vcalloc_req_bits_T_114) \n node _io_vcalloc_req_bits_T_122 = or(_io_vcalloc_req_bits_T_121, _io_vcalloc_req_bits_T_115) \n node _io_vcalloc_req_bits_T_123 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_116) \n node _io_vcalloc_req_bits_T_124 = or(_io_vcalloc_req_bits_T_123, _io_vcalloc_req_bits_T_117) \n node _io_vcalloc_req_bits_T_125 = or(_io_vcalloc_req_bits_T_124, _io_vcalloc_req_bits_T_118) \n node _io_vcalloc_req_bits_T_126 = or(_io_vcalloc_req_bits_T_125, _io_vcalloc_req_bits_T_119) \n node _io_vcalloc_req_bits_T_127 = or(_io_vcalloc_req_bits_T_126, _io_vcalloc_req_bits_T_120) \n wire _io_vcalloc_req_bits_WIRE_10 : UInt<1> \n connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_127 \n connect _io_vcalloc_req_bits_WIRE_2[7], _io_vcalloc_req_bits_WIRE_10 \n connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 \n wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>[8] \n node _io_vcalloc_req_bits_T_128 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_129 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_130 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_133 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[0], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_134 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[0], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_135 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[0], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_128, _io_vcalloc_req_bits_T_129) \n node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_130) \n node _io_vcalloc_req_bits_T_138 = or(_io_vcalloc_req_bits_T_137, _io_vcalloc_req_bits_T_131) \n node _io_vcalloc_req_bits_T_139 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_132) \n node _io_vcalloc_req_bits_T_140 = or(_io_vcalloc_req_bits_T_139, _io_vcalloc_req_bits_T_133) \n node _io_vcalloc_req_bits_T_141 = or(_io_vcalloc_req_bits_T_140, _io_vcalloc_req_bits_T_134) \n node _io_vcalloc_req_bits_T_142 = or(_io_vcalloc_req_bits_T_141, _io_vcalloc_req_bits_T_135) \n wire _io_vcalloc_req_bits_WIRE_12 : UInt<1> \n connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_142 \n connect _io_vcalloc_req_bits_WIRE_11[0], _io_vcalloc_req_bits_WIRE_12 \n node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_144 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_145 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_146 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[1], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_147 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[1], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_148 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[1], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_149 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[1], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_150 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[1], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_151 = or(_io_vcalloc_req_bits_T_143, _io_vcalloc_req_bits_T_144) \n node _io_vcalloc_req_bits_T_152 = or(_io_vcalloc_req_bits_T_151, _io_vcalloc_req_bits_T_145) \n node _io_vcalloc_req_bits_T_153 = or(_io_vcalloc_req_bits_T_152, _io_vcalloc_req_bits_T_146) \n node _io_vcalloc_req_bits_T_154 = or(_io_vcalloc_req_bits_T_153, _io_vcalloc_req_bits_T_147) \n node _io_vcalloc_req_bits_T_155 = or(_io_vcalloc_req_bits_T_154, _io_vcalloc_req_bits_T_148) \n node _io_vcalloc_req_bits_T_156 = or(_io_vcalloc_req_bits_T_155, _io_vcalloc_req_bits_T_149) \n node _io_vcalloc_req_bits_T_157 = or(_io_vcalloc_req_bits_T_156, _io_vcalloc_req_bits_T_150) \n wire _io_vcalloc_req_bits_WIRE_13 : UInt<1> \n connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_157 \n connect _io_vcalloc_req_bits_WIRE_11[1], _io_vcalloc_req_bits_WIRE_13 \n node _io_vcalloc_req_bits_T_158 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_159 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_160 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_161 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[2], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_162 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[2], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_163 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[2], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_164 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[2], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_165 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[2], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_166 = or(_io_vcalloc_req_bits_T_158, _io_vcalloc_req_bits_T_159) \n node _io_vcalloc_req_bits_T_167 = or(_io_vcalloc_req_bits_T_166, _io_vcalloc_req_bits_T_160) \n node _io_vcalloc_req_bits_T_168 = or(_io_vcalloc_req_bits_T_167, _io_vcalloc_req_bits_T_161) \n node _io_vcalloc_req_bits_T_169 = or(_io_vcalloc_req_bits_T_168, _io_vcalloc_req_bits_T_162) \n node _io_vcalloc_req_bits_T_170 = or(_io_vcalloc_req_bits_T_169, _io_vcalloc_req_bits_T_163) \n node _io_vcalloc_req_bits_T_171 = or(_io_vcalloc_req_bits_T_170, _io_vcalloc_req_bits_T_164) \n node _io_vcalloc_req_bits_T_172 = or(_io_vcalloc_req_bits_T_171, _io_vcalloc_req_bits_T_165) \n wire _io_vcalloc_req_bits_WIRE_14 : UInt<1> \n connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_172 \n connect _io_vcalloc_req_bits_WIRE_11[2], _io_vcalloc_req_bits_WIRE_14 \n node _io_vcalloc_req_bits_T_173 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[3], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_174 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[3], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_175 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[3], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_176 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[3], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_177 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[3], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_178 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[3], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_179 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[3], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_180 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[3], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_181 = or(_io_vcalloc_req_bits_T_173, _io_vcalloc_req_bits_T_174) \n node _io_vcalloc_req_bits_T_182 = or(_io_vcalloc_req_bits_T_181, _io_vcalloc_req_bits_T_175) \n node _io_vcalloc_req_bits_T_183 = or(_io_vcalloc_req_bits_T_182, _io_vcalloc_req_bits_T_176) \n node _io_vcalloc_req_bits_T_184 = or(_io_vcalloc_req_bits_T_183, _io_vcalloc_req_bits_T_177) \n node _io_vcalloc_req_bits_T_185 = or(_io_vcalloc_req_bits_T_184, _io_vcalloc_req_bits_T_178) \n node _io_vcalloc_req_bits_T_186 = or(_io_vcalloc_req_bits_T_185, _io_vcalloc_req_bits_T_179) \n node _io_vcalloc_req_bits_T_187 = or(_io_vcalloc_req_bits_T_186, _io_vcalloc_req_bits_T_180) \n wire _io_vcalloc_req_bits_WIRE_15 : UInt<1> \n connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_187 \n connect _io_vcalloc_req_bits_WIRE_11[3], _io_vcalloc_req_bits_WIRE_15 \n node _io_vcalloc_req_bits_T_188 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[4], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_189 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[4], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_190 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[4], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_191 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[4], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_192 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[4], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_193 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[4], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_194 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[4], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_195 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[4], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_196 = or(_io_vcalloc_req_bits_T_188, _io_vcalloc_req_bits_T_189) \n node _io_vcalloc_req_bits_T_197 = or(_io_vcalloc_req_bits_T_196, _io_vcalloc_req_bits_T_190) \n node _io_vcalloc_req_bits_T_198 = or(_io_vcalloc_req_bits_T_197, _io_vcalloc_req_bits_T_191) \n node _io_vcalloc_req_bits_T_199 = or(_io_vcalloc_req_bits_T_198, _io_vcalloc_req_bits_T_192) \n node _io_vcalloc_req_bits_T_200 = or(_io_vcalloc_req_bits_T_199, _io_vcalloc_req_bits_T_193) \n node _io_vcalloc_req_bits_T_201 = or(_io_vcalloc_req_bits_T_200, _io_vcalloc_req_bits_T_194) \n node _io_vcalloc_req_bits_T_202 = or(_io_vcalloc_req_bits_T_201, _io_vcalloc_req_bits_T_195) \n wire _io_vcalloc_req_bits_WIRE_16 : UInt<1> \n connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_202 \n connect _io_vcalloc_req_bits_WIRE_11[4], _io_vcalloc_req_bits_WIRE_16 \n node _io_vcalloc_req_bits_T_203 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[5], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_204 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[5], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_205 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[5], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_206 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[5], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_207 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[5], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_208 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[5], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_209 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[5], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_210 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[5], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_211 = or(_io_vcalloc_req_bits_T_203, _io_vcalloc_req_bits_T_204) \n node _io_vcalloc_req_bits_T_212 = or(_io_vcalloc_req_bits_T_211, _io_vcalloc_req_bits_T_205) \n node _io_vcalloc_req_bits_T_213 = or(_io_vcalloc_req_bits_T_212, _io_vcalloc_req_bits_T_206) \n node _io_vcalloc_req_bits_T_214 = or(_io_vcalloc_req_bits_T_213, _io_vcalloc_req_bits_T_207) \n node _io_vcalloc_req_bits_T_215 = or(_io_vcalloc_req_bits_T_214, _io_vcalloc_req_bits_T_208) \n node _io_vcalloc_req_bits_T_216 = or(_io_vcalloc_req_bits_T_215, _io_vcalloc_req_bits_T_209) \n node _io_vcalloc_req_bits_T_217 = or(_io_vcalloc_req_bits_T_216, _io_vcalloc_req_bits_T_210) \n wire _io_vcalloc_req_bits_WIRE_17 : UInt<1> \n connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_217 \n connect _io_vcalloc_req_bits_WIRE_11[5], _io_vcalloc_req_bits_WIRE_17 \n node _io_vcalloc_req_bits_T_218 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[6], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_219 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[6], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_220 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[6], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_221 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[6], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_222 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[6], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_223 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[6], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_224 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[6], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_225 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[6], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_226 = or(_io_vcalloc_req_bits_T_218, _io_vcalloc_req_bits_T_219) \n node _io_vcalloc_req_bits_T_227 = or(_io_vcalloc_req_bits_T_226, _io_vcalloc_req_bits_T_220) \n node _io_vcalloc_req_bits_T_228 = or(_io_vcalloc_req_bits_T_227, _io_vcalloc_req_bits_T_221) \n node _io_vcalloc_req_bits_T_229 = or(_io_vcalloc_req_bits_T_228, _io_vcalloc_req_bits_T_222) \n node _io_vcalloc_req_bits_T_230 = or(_io_vcalloc_req_bits_T_229, _io_vcalloc_req_bits_T_223) \n node _io_vcalloc_req_bits_T_231 = or(_io_vcalloc_req_bits_T_230, _io_vcalloc_req_bits_T_224) \n node _io_vcalloc_req_bits_T_232 = or(_io_vcalloc_req_bits_T_231, _io_vcalloc_req_bits_T_225) \n wire _io_vcalloc_req_bits_WIRE_18 : UInt<1> \n connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_232 \n connect _io_vcalloc_req_bits_WIRE_11[6], _io_vcalloc_req_bits_WIRE_18 \n node _io_vcalloc_req_bits_T_233 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[7], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_234 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[7], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_235 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[7], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_236 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[7], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_237 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[7], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_238 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[7], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_239 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[7], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_240 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[7], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_241 = or(_io_vcalloc_req_bits_T_233, _io_vcalloc_req_bits_T_234) \n node _io_vcalloc_req_bits_T_242 = or(_io_vcalloc_req_bits_T_241, _io_vcalloc_req_bits_T_235) \n node _io_vcalloc_req_bits_T_243 = or(_io_vcalloc_req_bits_T_242, _io_vcalloc_req_bits_T_236) \n node _io_vcalloc_req_bits_T_244 = or(_io_vcalloc_req_bits_T_243, _io_vcalloc_req_bits_T_237) \n node _io_vcalloc_req_bits_T_245 = or(_io_vcalloc_req_bits_T_244, _io_vcalloc_req_bits_T_238) \n node _io_vcalloc_req_bits_T_246 = or(_io_vcalloc_req_bits_T_245, _io_vcalloc_req_bits_T_239) \n node _io_vcalloc_req_bits_T_247 = or(_io_vcalloc_req_bits_T_246, _io_vcalloc_req_bits_T_240) \n wire _io_vcalloc_req_bits_WIRE_19 : UInt<1> \n connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_247 \n connect _io_vcalloc_req_bits_WIRE_11[7], _io_vcalloc_req_bits_WIRE_19 \n connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_11 \n wire _io_vcalloc_req_bits_WIRE_20 : UInt<1>[8] \n node _io_vcalloc_req_bits_T_248 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_249 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_250 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_251 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[0], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_252 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[0], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_253 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[0], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_254 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[0], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_255 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[0], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_256 = or(_io_vcalloc_req_bits_T_248, _io_vcalloc_req_bits_T_249) \n node _io_vcalloc_req_bits_T_257 = or(_io_vcalloc_req_bits_T_256, _io_vcalloc_req_bits_T_250) \n node _io_vcalloc_req_bits_T_258 = or(_io_vcalloc_req_bits_T_257, _io_vcalloc_req_bits_T_251) \n node _io_vcalloc_req_bits_T_259 = or(_io_vcalloc_req_bits_T_258, _io_vcalloc_req_bits_T_252) \n node _io_vcalloc_req_bits_T_260 = or(_io_vcalloc_req_bits_T_259, _io_vcalloc_req_bits_T_253) \n node _io_vcalloc_req_bits_T_261 = or(_io_vcalloc_req_bits_T_260, _io_vcalloc_req_bits_T_254) \n node _io_vcalloc_req_bits_T_262 = or(_io_vcalloc_req_bits_T_261, _io_vcalloc_req_bits_T_255) \n wire _io_vcalloc_req_bits_WIRE_21 : UInt<1> \n connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_262 \n connect _io_vcalloc_req_bits_WIRE_20[0], _io_vcalloc_req_bits_WIRE_21 \n node _io_vcalloc_req_bits_T_263 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_264 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_265 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[1], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_266 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[1], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_267 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[1], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_268 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[1], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_269 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[1], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_270 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[1], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_271 = or(_io_vcalloc_req_bits_T_263, _io_vcalloc_req_bits_T_264) \n node _io_vcalloc_req_bits_T_272 = or(_io_vcalloc_req_bits_T_271, _io_vcalloc_req_bits_T_265) \n node _io_vcalloc_req_bits_T_273 = or(_io_vcalloc_req_bits_T_272, _io_vcalloc_req_bits_T_266) \n node _io_vcalloc_req_bits_T_274 = or(_io_vcalloc_req_bits_T_273, _io_vcalloc_req_bits_T_267) \n node _io_vcalloc_req_bits_T_275 = or(_io_vcalloc_req_bits_T_274, _io_vcalloc_req_bits_T_268) \n node _io_vcalloc_req_bits_T_276 = or(_io_vcalloc_req_bits_T_275, _io_vcalloc_req_bits_T_269) \n node _io_vcalloc_req_bits_T_277 = or(_io_vcalloc_req_bits_T_276, _io_vcalloc_req_bits_T_270) \n wire _io_vcalloc_req_bits_WIRE_22 : UInt<1> \n connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_277 \n connect _io_vcalloc_req_bits_WIRE_20[1], _io_vcalloc_req_bits_WIRE_22 \n node _io_vcalloc_req_bits_T_278 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[2], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_279 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[2], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_280 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[2], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_281 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[2], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_282 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[2], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_283 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[2], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_284 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[2], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_285 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[2], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_286 = or(_io_vcalloc_req_bits_T_278, _io_vcalloc_req_bits_T_279) \n node _io_vcalloc_req_bits_T_287 = or(_io_vcalloc_req_bits_T_286, _io_vcalloc_req_bits_T_280) \n node _io_vcalloc_req_bits_T_288 = or(_io_vcalloc_req_bits_T_287, _io_vcalloc_req_bits_T_281) \n node _io_vcalloc_req_bits_T_289 = or(_io_vcalloc_req_bits_T_288, _io_vcalloc_req_bits_T_282) \n node _io_vcalloc_req_bits_T_290 = or(_io_vcalloc_req_bits_T_289, _io_vcalloc_req_bits_T_283) \n node _io_vcalloc_req_bits_T_291 = or(_io_vcalloc_req_bits_T_290, _io_vcalloc_req_bits_T_284) \n node _io_vcalloc_req_bits_T_292 = or(_io_vcalloc_req_bits_T_291, _io_vcalloc_req_bits_T_285) \n wire _io_vcalloc_req_bits_WIRE_23 : UInt<1> \n connect _io_vcalloc_req_bits_WIRE_23, _io_vcalloc_req_bits_T_292 \n connect _io_vcalloc_req_bits_WIRE_20[2], _io_vcalloc_req_bits_WIRE_23 \n node _io_vcalloc_req_bits_T_293 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[3], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_294 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[3], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_295 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[3], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_296 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[3], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_297 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[3], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_298 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[3], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_299 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[3], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_300 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[3], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_301 = or(_io_vcalloc_req_bits_T_293, _io_vcalloc_req_bits_T_294) \n node _io_vcalloc_req_bits_T_302 = or(_io_vcalloc_req_bits_T_301, _io_vcalloc_req_bits_T_295) \n node _io_vcalloc_req_bits_T_303 = or(_io_vcalloc_req_bits_T_302, _io_vcalloc_req_bits_T_296) \n node _io_vcalloc_req_bits_T_304 = or(_io_vcalloc_req_bits_T_303, _io_vcalloc_req_bits_T_297) \n node _io_vcalloc_req_bits_T_305 = or(_io_vcalloc_req_bits_T_304, _io_vcalloc_req_bits_T_298) \n node _io_vcalloc_req_bits_T_306 = or(_io_vcalloc_req_bits_T_305, _io_vcalloc_req_bits_T_299) \n node _io_vcalloc_req_bits_T_307 = or(_io_vcalloc_req_bits_T_306, _io_vcalloc_req_bits_T_300) \n wire _io_vcalloc_req_bits_WIRE_24 : UInt<1> \n connect _io_vcalloc_req_bits_WIRE_24, _io_vcalloc_req_bits_T_307 \n connect _io_vcalloc_req_bits_WIRE_20[3], _io_vcalloc_req_bits_WIRE_24 \n node _io_vcalloc_req_bits_T_308 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[4], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_309 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[4], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_310 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[4], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_311 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[4], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_312 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[4], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_313 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[4], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_314 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[4], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_315 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[4], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_316 = or(_io_vcalloc_req_bits_T_308, _io_vcalloc_req_bits_T_309) \n node _io_vcalloc_req_bits_T_317 = or(_io_vcalloc_req_bits_T_316, _io_vcalloc_req_bits_T_310) \n node _io_vcalloc_req_bits_T_318 = or(_io_vcalloc_req_bits_T_317, _io_vcalloc_req_bits_T_311) \n node _io_vcalloc_req_bits_T_319 = or(_io_vcalloc_req_bits_T_318, _io_vcalloc_req_bits_T_312) \n node _io_vcalloc_req_bits_T_320 = or(_io_vcalloc_req_bits_T_319, _io_vcalloc_req_bits_T_313) \n node _io_vcalloc_req_bits_T_321 = or(_io_vcalloc_req_bits_T_320, _io_vcalloc_req_bits_T_314) \n node _io_vcalloc_req_bits_T_322 = or(_io_vcalloc_req_bits_T_321, _io_vcalloc_req_bits_T_315) \n wire _io_vcalloc_req_bits_WIRE_25 : UInt<1> \n connect _io_vcalloc_req_bits_WIRE_25, _io_vcalloc_req_bits_T_322 \n connect _io_vcalloc_req_bits_WIRE_20[4], _io_vcalloc_req_bits_WIRE_25 \n node _io_vcalloc_req_bits_T_323 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[5], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_324 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[5], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_325 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[5], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_326 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[5], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_327 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[5], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_328 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[5], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_329 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[5], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_330 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[5], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_331 = or(_io_vcalloc_req_bits_T_323, _io_vcalloc_req_bits_T_324) \n node _io_vcalloc_req_bits_T_332 = or(_io_vcalloc_req_bits_T_331, _io_vcalloc_req_bits_T_325) \n node _io_vcalloc_req_bits_T_333 = or(_io_vcalloc_req_bits_T_332, _io_vcalloc_req_bits_T_326) \n node _io_vcalloc_req_bits_T_334 = or(_io_vcalloc_req_bits_T_333, _io_vcalloc_req_bits_T_327) \n node _io_vcalloc_req_bits_T_335 = or(_io_vcalloc_req_bits_T_334, _io_vcalloc_req_bits_T_328) \n node _io_vcalloc_req_bits_T_336 = or(_io_vcalloc_req_bits_T_335, _io_vcalloc_req_bits_T_329) \n node _io_vcalloc_req_bits_T_337 = or(_io_vcalloc_req_bits_T_336, _io_vcalloc_req_bits_T_330) \n wire _io_vcalloc_req_bits_WIRE_26 : UInt<1> \n connect _io_vcalloc_req_bits_WIRE_26, _io_vcalloc_req_bits_T_337 \n connect _io_vcalloc_req_bits_WIRE_20[5], _io_vcalloc_req_bits_WIRE_26 \n node _io_vcalloc_req_bits_T_338 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[6], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_339 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[6], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_340 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[6], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_341 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[6], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_342 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[6], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_343 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[6], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_344 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[6], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_345 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[6], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_346 = or(_io_vcalloc_req_bits_T_338, _io_vcalloc_req_bits_T_339) \n node _io_vcalloc_req_bits_T_347 = or(_io_vcalloc_req_bits_T_346, _io_vcalloc_req_bits_T_340) \n node _io_vcalloc_req_bits_T_348 = or(_io_vcalloc_req_bits_T_347, _io_vcalloc_req_bits_T_341) \n node _io_vcalloc_req_bits_T_349 = or(_io_vcalloc_req_bits_T_348, _io_vcalloc_req_bits_T_342) \n node _io_vcalloc_req_bits_T_350 = or(_io_vcalloc_req_bits_T_349, _io_vcalloc_req_bits_T_343) \n node _io_vcalloc_req_bits_T_351 = or(_io_vcalloc_req_bits_T_350, _io_vcalloc_req_bits_T_344) \n node _io_vcalloc_req_bits_T_352 = or(_io_vcalloc_req_bits_T_351, _io_vcalloc_req_bits_T_345) \n wire _io_vcalloc_req_bits_WIRE_27 : UInt<1> \n connect _io_vcalloc_req_bits_WIRE_27, _io_vcalloc_req_bits_T_352 \n connect _io_vcalloc_req_bits_WIRE_20[6], _io_vcalloc_req_bits_WIRE_27 \n node _io_vcalloc_req_bits_T_353 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[7], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_354 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[7], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_355 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[7], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_356 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[7], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_357 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[7], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_358 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[7], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_359 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[7], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_360 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[7], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_361 = or(_io_vcalloc_req_bits_T_353, _io_vcalloc_req_bits_T_354) \n node _io_vcalloc_req_bits_T_362 = or(_io_vcalloc_req_bits_T_361, _io_vcalloc_req_bits_T_355) \n node _io_vcalloc_req_bits_T_363 = or(_io_vcalloc_req_bits_T_362, _io_vcalloc_req_bits_T_356) \n node _io_vcalloc_req_bits_T_364 = or(_io_vcalloc_req_bits_T_363, _io_vcalloc_req_bits_T_357) \n node _io_vcalloc_req_bits_T_365 = or(_io_vcalloc_req_bits_T_364, _io_vcalloc_req_bits_T_358) \n node _io_vcalloc_req_bits_T_366 = or(_io_vcalloc_req_bits_T_365, _io_vcalloc_req_bits_T_359) \n node _io_vcalloc_req_bits_T_367 = or(_io_vcalloc_req_bits_T_366, _io_vcalloc_req_bits_T_360) \n wire _io_vcalloc_req_bits_WIRE_28 : UInt<1> \n connect _io_vcalloc_req_bits_WIRE_28, _io_vcalloc_req_bits_T_367 \n connect _io_vcalloc_req_bits_WIRE_20[7], _io_vcalloc_req_bits_WIRE_28 \n connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_20 \n wire _io_vcalloc_req_bits_WIRE_29 : UInt<1>[8] \n node _io_vcalloc_req_bits_T_368 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_369 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_370 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[0], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_371 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[0], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_372 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[0], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_373 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[0], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_374 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[0], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_375 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[0], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_376 = or(_io_vcalloc_req_bits_T_368, _io_vcalloc_req_bits_T_369) \n node _io_vcalloc_req_bits_T_377 = or(_io_vcalloc_req_bits_T_376, _io_vcalloc_req_bits_T_370) \n node _io_vcalloc_req_bits_T_378 = or(_io_vcalloc_req_bits_T_377, _io_vcalloc_req_bits_T_371) \n node _io_vcalloc_req_bits_T_379 = or(_io_vcalloc_req_bits_T_378, _io_vcalloc_req_bits_T_372) \n node _io_vcalloc_req_bits_T_380 = or(_io_vcalloc_req_bits_T_379, _io_vcalloc_req_bits_T_373) \n node _io_vcalloc_req_bits_T_381 = or(_io_vcalloc_req_bits_T_380, _io_vcalloc_req_bits_T_374) \n node _io_vcalloc_req_bits_T_382 = or(_io_vcalloc_req_bits_T_381, _io_vcalloc_req_bits_T_375) \n wire _io_vcalloc_req_bits_WIRE_30 : UInt<1> \n connect _io_vcalloc_req_bits_WIRE_30, _io_vcalloc_req_bits_T_382 \n connect _io_vcalloc_req_bits_WIRE_29[0], _io_vcalloc_req_bits_WIRE_30 \n node _io_vcalloc_req_bits_T_383 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[1], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_384 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[1], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_385 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[1], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_386 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[1], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_387 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[1], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_388 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[1], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_389 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[1], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_390 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[1], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_391 = or(_io_vcalloc_req_bits_T_383, _io_vcalloc_req_bits_T_384) \n node _io_vcalloc_req_bits_T_392 = or(_io_vcalloc_req_bits_T_391, _io_vcalloc_req_bits_T_385) \n node _io_vcalloc_req_bits_T_393 = or(_io_vcalloc_req_bits_T_392, _io_vcalloc_req_bits_T_386) \n node _io_vcalloc_req_bits_T_394 = or(_io_vcalloc_req_bits_T_393, _io_vcalloc_req_bits_T_387) \n node _io_vcalloc_req_bits_T_395 = or(_io_vcalloc_req_bits_T_394, _io_vcalloc_req_bits_T_388) \n node _io_vcalloc_req_bits_T_396 = or(_io_vcalloc_req_bits_T_395, _io_vcalloc_req_bits_T_389) \n node _io_vcalloc_req_bits_T_397 = or(_io_vcalloc_req_bits_T_396, _io_vcalloc_req_bits_T_390) \n wire _io_vcalloc_req_bits_WIRE_31 : UInt<1> \n connect _io_vcalloc_req_bits_WIRE_31, _io_vcalloc_req_bits_T_397 \n connect _io_vcalloc_req_bits_WIRE_29[1], _io_vcalloc_req_bits_WIRE_31 \n node _io_vcalloc_req_bits_T_398 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[2], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_399 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[2], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_400 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[2], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_401 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[2], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_402 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[2], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_403 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[2], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_404 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[2], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_405 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[2], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_406 = or(_io_vcalloc_req_bits_T_398, _io_vcalloc_req_bits_T_399) \n node _io_vcalloc_req_bits_T_407 = or(_io_vcalloc_req_bits_T_406, _io_vcalloc_req_bits_T_400) \n node _io_vcalloc_req_bits_T_408 = or(_io_vcalloc_req_bits_T_407, _io_vcalloc_req_bits_T_401) \n node _io_vcalloc_req_bits_T_409 = or(_io_vcalloc_req_bits_T_408, _io_vcalloc_req_bits_T_402) \n node _io_vcalloc_req_bits_T_410 = or(_io_vcalloc_req_bits_T_409, _io_vcalloc_req_bits_T_403) \n node _io_vcalloc_req_bits_T_411 = or(_io_vcalloc_req_bits_T_410, _io_vcalloc_req_bits_T_404) \n node _io_vcalloc_req_bits_T_412 = or(_io_vcalloc_req_bits_T_411, _io_vcalloc_req_bits_T_405) \n wire _io_vcalloc_req_bits_WIRE_32 : UInt<1> \n connect _io_vcalloc_req_bits_WIRE_32, _io_vcalloc_req_bits_T_412 \n connect _io_vcalloc_req_bits_WIRE_29[2], _io_vcalloc_req_bits_WIRE_32 \n node _io_vcalloc_req_bits_T_413 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[3], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_414 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[3], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_415 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[3], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_416 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[3], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_417 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[3], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_418 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[3], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_419 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[3], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_420 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[3], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_421 = or(_io_vcalloc_req_bits_T_413, _io_vcalloc_req_bits_T_414) \n node _io_vcalloc_req_bits_T_422 = or(_io_vcalloc_req_bits_T_421, _io_vcalloc_req_bits_T_415) \n node _io_vcalloc_req_bits_T_423 = or(_io_vcalloc_req_bits_T_422, _io_vcalloc_req_bits_T_416) \n node _io_vcalloc_req_bits_T_424 = or(_io_vcalloc_req_bits_T_423, _io_vcalloc_req_bits_T_417) \n node _io_vcalloc_req_bits_T_425 = or(_io_vcalloc_req_bits_T_424, _io_vcalloc_req_bits_T_418) \n node _io_vcalloc_req_bits_T_426 = or(_io_vcalloc_req_bits_T_425, _io_vcalloc_req_bits_T_419) \n node _io_vcalloc_req_bits_T_427 = or(_io_vcalloc_req_bits_T_426, _io_vcalloc_req_bits_T_420) \n wire _io_vcalloc_req_bits_WIRE_33 : UInt<1> \n connect _io_vcalloc_req_bits_WIRE_33, _io_vcalloc_req_bits_T_427 \n connect _io_vcalloc_req_bits_WIRE_29[3], _io_vcalloc_req_bits_WIRE_33 \n node _io_vcalloc_req_bits_T_428 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[4], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_429 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[4], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_430 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[4], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_431 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[4], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_432 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[4], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_433 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[4], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_434 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[4], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_435 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[4], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_436 = or(_io_vcalloc_req_bits_T_428, _io_vcalloc_req_bits_T_429) \n node _io_vcalloc_req_bits_T_437 = or(_io_vcalloc_req_bits_T_436, _io_vcalloc_req_bits_T_430) \n node _io_vcalloc_req_bits_T_438 = or(_io_vcalloc_req_bits_T_437, _io_vcalloc_req_bits_T_431) \n node _io_vcalloc_req_bits_T_439 = or(_io_vcalloc_req_bits_T_438, _io_vcalloc_req_bits_T_432) \n node _io_vcalloc_req_bits_T_440 = or(_io_vcalloc_req_bits_T_439, _io_vcalloc_req_bits_T_433) \n node _io_vcalloc_req_bits_T_441 = or(_io_vcalloc_req_bits_T_440, _io_vcalloc_req_bits_T_434) \n node _io_vcalloc_req_bits_T_442 = or(_io_vcalloc_req_bits_T_441, _io_vcalloc_req_bits_T_435) \n wire _io_vcalloc_req_bits_WIRE_34 : UInt<1> \n connect _io_vcalloc_req_bits_WIRE_34, _io_vcalloc_req_bits_T_442 \n connect _io_vcalloc_req_bits_WIRE_29[4], _io_vcalloc_req_bits_WIRE_34 \n node _io_vcalloc_req_bits_T_443 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[5], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_444 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[5], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_445 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[5], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_446 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[5], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_447 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[5], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_448 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[5], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_449 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[5], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_450 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[5], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_451 = or(_io_vcalloc_req_bits_T_443, _io_vcalloc_req_bits_T_444) \n node _io_vcalloc_req_bits_T_452 = or(_io_vcalloc_req_bits_T_451, _io_vcalloc_req_bits_T_445) \n node _io_vcalloc_req_bits_T_453 = or(_io_vcalloc_req_bits_T_452, _io_vcalloc_req_bits_T_446) \n node _io_vcalloc_req_bits_T_454 = or(_io_vcalloc_req_bits_T_453, _io_vcalloc_req_bits_T_447) \n node _io_vcalloc_req_bits_T_455 = or(_io_vcalloc_req_bits_T_454, _io_vcalloc_req_bits_T_448) \n node _io_vcalloc_req_bits_T_456 = or(_io_vcalloc_req_bits_T_455, _io_vcalloc_req_bits_T_449) \n node _io_vcalloc_req_bits_T_457 = or(_io_vcalloc_req_bits_T_456, _io_vcalloc_req_bits_T_450) \n wire _io_vcalloc_req_bits_WIRE_35 : UInt<1> \n connect _io_vcalloc_req_bits_WIRE_35, _io_vcalloc_req_bits_T_457 \n connect _io_vcalloc_req_bits_WIRE_29[5], _io_vcalloc_req_bits_WIRE_35 \n node _io_vcalloc_req_bits_T_458 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[6], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_459 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[6], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_460 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[6], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_461 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[6], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_462 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[6], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_463 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[6], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_464 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[6], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_465 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[6], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_466 = or(_io_vcalloc_req_bits_T_458, _io_vcalloc_req_bits_T_459) \n node _io_vcalloc_req_bits_T_467 = or(_io_vcalloc_req_bits_T_466, _io_vcalloc_req_bits_T_460) \n node _io_vcalloc_req_bits_T_468 = or(_io_vcalloc_req_bits_T_467, _io_vcalloc_req_bits_T_461) \n node _io_vcalloc_req_bits_T_469 = or(_io_vcalloc_req_bits_T_468, _io_vcalloc_req_bits_T_462) \n node _io_vcalloc_req_bits_T_470 = or(_io_vcalloc_req_bits_T_469, _io_vcalloc_req_bits_T_463) \n node _io_vcalloc_req_bits_T_471 = or(_io_vcalloc_req_bits_T_470, _io_vcalloc_req_bits_T_464) \n node _io_vcalloc_req_bits_T_472 = or(_io_vcalloc_req_bits_T_471, _io_vcalloc_req_bits_T_465) \n wire _io_vcalloc_req_bits_WIRE_36 : UInt<1> \n connect _io_vcalloc_req_bits_WIRE_36, _io_vcalloc_req_bits_T_472 \n connect _io_vcalloc_req_bits_WIRE_29[6], _io_vcalloc_req_bits_WIRE_36 \n node _io_vcalloc_req_bits_T_473 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[7], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_474 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[7], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_475 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[7], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_476 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[7], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_477 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[7], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_478 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[7], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_479 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[7], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_480 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[7], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_481 = or(_io_vcalloc_req_bits_T_473, _io_vcalloc_req_bits_T_474) \n node _io_vcalloc_req_bits_T_482 = or(_io_vcalloc_req_bits_T_481, _io_vcalloc_req_bits_T_475) \n node _io_vcalloc_req_bits_T_483 = or(_io_vcalloc_req_bits_T_482, _io_vcalloc_req_bits_T_476) \n node _io_vcalloc_req_bits_T_484 = or(_io_vcalloc_req_bits_T_483, _io_vcalloc_req_bits_T_477) \n node _io_vcalloc_req_bits_T_485 = or(_io_vcalloc_req_bits_T_484, _io_vcalloc_req_bits_T_478) \n node _io_vcalloc_req_bits_T_486 = or(_io_vcalloc_req_bits_T_485, _io_vcalloc_req_bits_T_479) \n node _io_vcalloc_req_bits_T_487 = or(_io_vcalloc_req_bits_T_486, _io_vcalloc_req_bits_T_480) \n wire _io_vcalloc_req_bits_WIRE_37 : UInt<1> \n connect _io_vcalloc_req_bits_WIRE_37, _io_vcalloc_req_bits_T_487 \n connect _io_vcalloc_req_bits_WIRE_29[7], _io_vcalloc_req_bits_WIRE_37 \n connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_29 \n connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 \n node _io_vcalloc_req_bits_T_488 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_489 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_490 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_491 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_492 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_493 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].in_vc, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_494 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].in_vc, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_495 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].in_vc, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_496 = or(_io_vcalloc_req_bits_T_488, _io_vcalloc_req_bits_T_489) \n node _io_vcalloc_req_bits_T_497 = or(_io_vcalloc_req_bits_T_496, _io_vcalloc_req_bits_T_490) \n node _io_vcalloc_req_bits_T_498 = or(_io_vcalloc_req_bits_T_497, _io_vcalloc_req_bits_T_491) \n node _io_vcalloc_req_bits_T_499 = or(_io_vcalloc_req_bits_T_498, _io_vcalloc_req_bits_T_492) \n node _io_vcalloc_req_bits_T_500 = or(_io_vcalloc_req_bits_T_499, _io_vcalloc_req_bits_T_493) \n node _io_vcalloc_req_bits_T_501 = or(_io_vcalloc_req_bits_T_500, _io_vcalloc_req_bits_T_494) \n node _io_vcalloc_req_bits_T_502 = or(_io_vcalloc_req_bits_T_501, _io_vcalloc_req_bits_T_495) \n wire _io_vcalloc_req_bits_WIRE_38 : UInt<3> \n connect _io_vcalloc_req_bits_WIRE_38, _io_vcalloc_req_bits_T_502 \n connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_38 \n wire _io_vcalloc_req_bits_WIRE_39 : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>} \n node _io_vcalloc_req_bits_T_503 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_504 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_505 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_506 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_507 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_508 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node_id, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_509 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node_id, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_510 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node_id, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_511 = or(_io_vcalloc_req_bits_T_503, _io_vcalloc_req_bits_T_504) \n node _io_vcalloc_req_bits_T_512 = or(_io_vcalloc_req_bits_T_511, _io_vcalloc_req_bits_T_505) \n node _io_vcalloc_req_bits_T_513 = or(_io_vcalloc_req_bits_T_512, _io_vcalloc_req_bits_T_506) \n node _io_vcalloc_req_bits_T_514 = or(_io_vcalloc_req_bits_T_513, _io_vcalloc_req_bits_T_507) \n node _io_vcalloc_req_bits_T_515 = or(_io_vcalloc_req_bits_T_514, _io_vcalloc_req_bits_T_508) \n node _io_vcalloc_req_bits_T_516 = or(_io_vcalloc_req_bits_T_515, _io_vcalloc_req_bits_T_509) \n node _io_vcalloc_req_bits_T_517 = or(_io_vcalloc_req_bits_T_516, _io_vcalloc_req_bits_T_510) \n wire _io_vcalloc_req_bits_WIRE_40 : UInt<2> \n connect _io_vcalloc_req_bits_WIRE_40, _io_vcalloc_req_bits_T_517 \n connect _io_vcalloc_req_bits_WIRE_39.egress_node_id, _io_vcalloc_req_bits_WIRE_40 \n node _io_vcalloc_req_bits_T_518 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_519 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_520 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_521 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_522 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_523 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_524 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_525 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_526 = or(_io_vcalloc_req_bits_T_518, _io_vcalloc_req_bits_T_519) \n node _io_vcalloc_req_bits_T_527 = or(_io_vcalloc_req_bits_T_526, _io_vcalloc_req_bits_T_520) \n node _io_vcalloc_req_bits_T_528 = or(_io_vcalloc_req_bits_T_527, _io_vcalloc_req_bits_T_521) \n node _io_vcalloc_req_bits_T_529 = or(_io_vcalloc_req_bits_T_528, _io_vcalloc_req_bits_T_522) \n node _io_vcalloc_req_bits_T_530 = or(_io_vcalloc_req_bits_T_529, _io_vcalloc_req_bits_T_523) \n node _io_vcalloc_req_bits_T_531 = or(_io_vcalloc_req_bits_T_530, _io_vcalloc_req_bits_T_524) \n node _io_vcalloc_req_bits_T_532 = or(_io_vcalloc_req_bits_T_531, _io_vcalloc_req_bits_T_525) \n wire _io_vcalloc_req_bits_WIRE_41 : UInt<5> \n connect _io_vcalloc_req_bits_WIRE_41, _io_vcalloc_req_bits_T_532 \n connect _io_vcalloc_req_bits_WIRE_39.egress_node, _io_vcalloc_req_bits_WIRE_41 \n node _io_vcalloc_req_bits_T_533 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_534 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_535 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_536 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_537 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_538 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node_id, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_539 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node_id, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_540 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node_id, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_541 = or(_io_vcalloc_req_bits_T_533, _io_vcalloc_req_bits_T_534) \n node _io_vcalloc_req_bits_T_542 = or(_io_vcalloc_req_bits_T_541, _io_vcalloc_req_bits_T_535) \n node _io_vcalloc_req_bits_T_543 = or(_io_vcalloc_req_bits_T_542, _io_vcalloc_req_bits_T_536) \n node _io_vcalloc_req_bits_T_544 = or(_io_vcalloc_req_bits_T_543, _io_vcalloc_req_bits_T_537) \n node _io_vcalloc_req_bits_T_545 = or(_io_vcalloc_req_bits_T_544, _io_vcalloc_req_bits_T_538) \n node _io_vcalloc_req_bits_T_546 = or(_io_vcalloc_req_bits_T_545, _io_vcalloc_req_bits_T_539) \n node _io_vcalloc_req_bits_T_547 = or(_io_vcalloc_req_bits_T_546, _io_vcalloc_req_bits_T_540) \n wire _io_vcalloc_req_bits_WIRE_42 : UInt<2> \n connect _io_vcalloc_req_bits_WIRE_42, _io_vcalloc_req_bits_T_547 \n connect _io_vcalloc_req_bits_WIRE_39.ingress_node_id, _io_vcalloc_req_bits_WIRE_42 \n node _io_vcalloc_req_bits_T_548 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_549 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_550 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_551 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_552 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_553 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_554 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_555 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_556 = or(_io_vcalloc_req_bits_T_548, _io_vcalloc_req_bits_T_549) \n node _io_vcalloc_req_bits_T_557 = or(_io_vcalloc_req_bits_T_556, _io_vcalloc_req_bits_T_550) \n node _io_vcalloc_req_bits_T_558 = or(_io_vcalloc_req_bits_T_557, _io_vcalloc_req_bits_T_551) \n node _io_vcalloc_req_bits_T_559 = or(_io_vcalloc_req_bits_T_558, _io_vcalloc_req_bits_T_552) \n node _io_vcalloc_req_bits_T_560 = or(_io_vcalloc_req_bits_T_559, _io_vcalloc_req_bits_T_553) \n node _io_vcalloc_req_bits_T_561 = or(_io_vcalloc_req_bits_T_560, _io_vcalloc_req_bits_T_554) \n node _io_vcalloc_req_bits_T_562 = or(_io_vcalloc_req_bits_T_561, _io_vcalloc_req_bits_T_555) \n wire _io_vcalloc_req_bits_WIRE_43 : UInt<5> \n connect _io_vcalloc_req_bits_WIRE_43, _io_vcalloc_req_bits_T_562 \n connect _io_vcalloc_req_bits_WIRE_39.ingress_node, _io_vcalloc_req_bits_WIRE_43 \n node _io_vcalloc_req_bits_T_563 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_564 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_565 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_566 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_567 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_568 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.vnet_id, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_569 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.vnet_id, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_570 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.vnet_id, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_571 = or(_io_vcalloc_req_bits_T_563, _io_vcalloc_req_bits_T_564) \n node _io_vcalloc_req_bits_T_572 = or(_io_vcalloc_req_bits_T_571, _io_vcalloc_req_bits_T_565) \n node _io_vcalloc_req_bits_T_573 = or(_io_vcalloc_req_bits_T_572, _io_vcalloc_req_bits_T_566) \n node _io_vcalloc_req_bits_T_574 = or(_io_vcalloc_req_bits_T_573, _io_vcalloc_req_bits_T_567) \n node _io_vcalloc_req_bits_T_575 = or(_io_vcalloc_req_bits_T_574, _io_vcalloc_req_bits_T_568) \n node _io_vcalloc_req_bits_T_576 = or(_io_vcalloc_req_bits_T_575, _io_vcalloc_req_bits_T_569) \n node _io_vcalloc_req_bits_T_577 = or(_io_vcalloc_req_bits_T_576, _io_vcalloc_req_bits_T_570) \n wire _io_vcalloc_req_bits_WIRE_44 : UInt<3> \n connect _io_vcalloc_req_bits_WIRE_44, _io_vcalloc_req_bits_T_577 \n connect _io_vcalloc_req_bits_WIRE_39.vnet_id, _io_vcalloc_req_bits_WIRE_44 \n connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_39 \n connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE \n node _vcalloc_vals_0_T = eq(states[0].g, UInt<3>(0h2)) \n node _vcalloc_vals_0_T_1 = eq(states[0].fifo_deps, UInt<1>(0h0)) \n node _vcalloc_vals_0_T_2 = and(_vcalloc_vals_0_T, _vcalloc_vals_0_T_1) \n connect vcalloc_vals[0], _vcalloc_vals_0_T_2 \n connect vcalloc_reqs[0].in_vc, UInt<1>(0h0) \n connect vcalloc_reqs[0].vc_sel.`0`, states[0].vc_sel.`0` \n connect vcalloc_reqs[0].vc_sel.`1`, states[0].vc_sel.`1` \n connect vcalloc_reqs[0].vc_sel.`2`, states[0].vc_sel.`2` \n connect vcalloc_reqs[0].vc_sel.`3`, states[0].vc_sel.`3` \n connect vcalloc_reqs[0].flow, states[0].flow \n node _T_38 = bits(vcalloc_sel, 0, 0) \n node _T_39 = and(vcalloc_vals[0], _T_38) \n node _T_40 = and(_T_39, io.vcalloc_req.ready) \n when _T_40 : \n connect states[0].g, UInt<3>(0h3) \n node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2)) \n node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0)) \n node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1) \n connect vcalloc_vals[1], _vcalloc_vals_1_T_2 \n connect vcalloc_reqs[1].in_vc, UInt<1>(0h1) \n connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0` \n connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1` \n connect vcalloc_reqs[1].vc_sel.`2`, states[1].vc_sel.`2` \n connect vcalloc_reqs[1].vc_sel.`3`, states[1].vc_sel.`3` \n connect vcalloc_reqs[1].flow, states[1].flow \n node _T_41 = bits(vcalloc_sel, 1, 1) \n node _T_42 = and(vcalloc_vals[1], _T_41) \n node _T_43 = and(_T_42, io.vcalloc_req.ready) \n when _T_43 : \n connect states[1].g, UInt<3>(0h3) \n node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2)) \n node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0)) \n node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1) \n connect vcalloc_vals[2], _vcalloc_vals_2_T_2 \n connect vcalloc_reqs[2].in_vc, UInt<2>(0h2) \n connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0` \n connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1` \n connect vcalloc_reqs[2].vc_sel.`2`, states[2].vc_sel.`2` \n connect vcalloc_reqs[2].vc_sel.`3`, states[2].vc_sel.`3` \n connect vcalloc_reqs[2].flow, states[2].flow \n node _T_44 = bits(vcalloc_sel, 2, 2) \n node _T_45 = and(vcalloc_vals[2], _T_44) \n node _T_46 = and(_T_45, io.vcalloc_req.ready) \n when _T_46 : \n connect states[2].g, UInt<3>(0h3) \n node _vcalloc_vals_3_T = eq(states[3].g, UInt<3>(0h2)) \n node _vcalloc_vals_3_T_1 = eq(states[3].fifo_deps, UInt<1>(0h0)) \n node _vcalloc_vals_3_T_2 = and(_vcalloc_vals_3_T, _vcalloc_vals_3_T_1) \n connect vcalloc_vals[3], _vcalloc_vals_3_T_2 \n connect vcalloc_reqs[3].in_vc, UInt<2>(0h3) \n connect vcalloc_reqs[3].vc_sel.`0`, states[3].vc_sel.`0` \n connect vcalloc_reqs[3].vc_sel.`1`, states[3].vc_sel.`1` \n connect vcalloc_reqs[3].vc_sel.`2`, states[3].vc_sel.`2` \n connect vcalloc_reqs[3].vc_sel.`3`, states[3].vc_sel.`3` \n connect vcalloc_reqs[3].flow, states[3].flow \n node _T_47 = bits(vcalloc_sel, 3, 3) \n node _T_48 = and(vcalloc_vals[3], _T_47) \n node _T_49 = and(_T_48, io.vcalloc_req.ready) \n when _T_49 : \n connect states[3].g, UInt<3>(0h3) \n node _vcalloc_vals_4_T = eq(states[4].g, UInt<3>(0h2)) \n node _vcalloc_vals_4_T_1 = eq(states[4].fifo_deps, UInt<1>(0h0)) \n node _vcalloc_vals_4_T_2 = and(_vcalloc_vals_4_T, _vcalloc_vals_4_T_1) \n connect vcalloc_vals[4], _vcalloc_vals_4_T_2 \n connect vcalloc_reqs[4].in_vc, UInt<3>(0h4) \n connect vcalloc_reqs[4].vc_sel.`0`, states[4].vc_sel.`0` \n connect vcalloc_reqs[4].vc_sel.`1`, states[4].vc_sel.`1` \n connect vcalloc_reqs[4].vc_sel.`2`, states[4].vc_sel.`2` \n connect vcalloc_reqs[4].vc_sel.`3`, states[4].vc_sel.`3` \n connect vcalloc_reqs[4].flow, states[4].flow \n node _T_50 = bits(vcalloc_sel, 4, 4) \n node _T_51 = and(vcalloc_vals[4], _T_50) \n node _T_52 = and(_T_51, io.vcalloc_req.ready) \n when _T_52 : \n connect states[4].g, UInt<3>(0h3) \n node _vcalloc_vals_5_T = eq(states[5].g, UInt<3>(0h2)) \n node _vcalloc_vals_5_T_1 = eq(states[5].fifo_deps, UInt<1>(0h0)) \n node _vcalloc_vals_5_T_2 = and(_vcalloc_vals_5_T, _vcalloc_vals_5_T_1) \n connect vcalloc_vals[5], _vcalloc_vals_5_T_2 \n connect vcalloc_reqs[5].in_vc, UInt<3>(0h5) \n connect vcalloc_reqs[5].vc_sel.`0`, states[5].vc_sel.`0` \n connect vcalloc_reqs[5].vc_sel.`1`, states[5].vc_sel.`1` \n connect vcalloc_reqs[5].vc_sel.`2`, states[5].vc_sel.`2` \n connect vcalloc_reqs[5].vc_sel.`3`, states[5].vc_sel.`3` \n connect vcalloc_reqs[5].flow, states[5].flow \n node _T_53 = bits(vcalloc_sel, 5, 5) \n node _T_54 = and(vcalloc_vals[5], _T_53) \n node _T_55 = and(_T_54, io.vcalloc_req.ready) \n when _T_55 : \n connect states[5].g, UInt<3>(0h3) \n node _vcalloc_vals_6_T = eq(states[6].g, UInt<3>(0h2)) \n node _vcalloc_vals_6_T_1 = eq(states[6].fifo_deps, UInt<1>(0h0)) \n node _vcalloc_vals_6_T_2 = and(_vcalloc_vals_6_T, _vcalloc_vals_6_T_1) \n connect vcalloc_vals[6], _vcalloc_vals_6_T_2 \n connect vcalloc_reqs[6].in_vc, UInt<3>(0h6) \n connect vcalloc_reqs[6].vc_sel.`0`, states[6].vc_sel.`0` \n connect vcalloc_reqs[6].vc_sel.`1`, states[6].vc_sel.`1` \n connect vcalloc_reqs[6].vc_sel.`2`, states[6].vc_sel.`2` \n connect vcalloc_reqs[6].vc_sel.`3`, states[6].vc_sel.`3` \n connect vcalloc_reqs[6].flow, states[6].flow \n node _T_56 = bits(vcalloc_sel, 6, 6) \n node _T_57 = and(vcalloc_vals[6], _T_56) \n node _T_58 = and(_T_57, io.vcalloc_req.ready) \n when _T_58 : \n connect states[6].g, UInt<3>(0h3) \n node _vcalloc_vals_7_T = eq(states[7].g, UInt<3>(0h2)) \n node _vcalloc_vals_7_T_1 = eq(states[7].fifo_deps, UInt<1>(0h0)) \n node _vcalloc_vals_7_T_2 = and(_vcalloc_vals_7_T, _vcalloc_vals_7_T_1) \n connect vcalloc_vals[7], _vcalloc_vals_7_T_2 \n connect vcalloc_reqs[7].in_vc, UInt<3>(0h7) \n connect vcalloc_reqs[7].vc_sel.`0`, states[7].vc_sel.`0` \n connect vcalloc_reqs[7].vc_sel.`1`, states[7].vc_sel.`1` \n connect vcalloc_reqs[7].vc_sel.`2`, states[7].vc_sel.`2` \n connect vcalloc_reqs[7].vc_sel.`3`, states[7].vc_sel.`3` \n connect vcalloc_reqs[7].flow, states[7].flow \n node _T_59 = bits(vcalloc_sel, 7, 7) \n node _T_60 = and(vcalloc_vals[7], _T_59) \n node _T_61 = and(_T_60, io.vcalloc_req.ready) \n when _T_61 : \n connect states[7].g, UInt<3>(0h3) \n node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1]) \n node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) \n node _io_debug_va_stall_T_2 = add(vcalloc_vals[2], vcalloc_vals[3]) \n node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0) \n node _io_debug_va_stall_T_4 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_3) \n node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 2, 0) \n node _io_debug_va_stall_T_6 = add(vcalloc_vals[4], vcalloc_vals[5]) \n node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 1, 0) \n node _io_debug_va_stall_T_8 = add(vcalloc_vals[6], vcalloc_vals[7]) \n node _io_debug_va_stall_T_9 = bits(_io_debug_va_stall_T_8, 1, 0) \n node _io_debug_va_stall_T_10 = add(_io_debug_va_stall_T_7, _io_debug_va_stall_T_9) \n node _io_debug_va_stall_T_11 = bits(_io_debug_va_stall_T_10, 2, 0) \n node _io_debug_va_stall_T_12 = add(_io_debug_va_stall_T_5, _io_debug_va_stall_T_11) \n node _io_debug_va_stall_T_13 = bits(_io_debug_va_stall_T_12, 3, 0) \n node _io_debug_va_stall_T_14 = sub(_io_debug_va_stall_T_13, io.vcalloc_req.ready) \n node _io_debug_va_stall_T_15 = tail(_io_debug_va_stall_T_14, 1) \n connect io.debug.va_stall, _io_debug_va_stall_T_15 \n node _T_62 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) \n when _T_62 : \n node _T_63 = bits(vcalloc_sel, 0, 0) \n when _T_63 : \n connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` \n connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` \n connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` \n connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` \n connect states[0].g, UInt<3>(0h3) \n node _T_64 = eq(states[0].g, UInt<3>(0h2)) \n node _T_65 = asUInt(reset) \n node _T_66 = eq(_T_65, UInt<1>(0h0)) \n when _T_66 : \n node _T_67 = eq(_T_64, UInt<1>(0h0)) \n when _T_67 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at InputUnit.scala:291 assert(states(i).g === g_v)\\n\") : printf_3 \n assert(clock, _T_64, UInt<1>(0h1), \"\") : assert_3 \n node _T_68 = bits(vcalloc_sel, 1, 1) \n when _T_68 : \n connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` \n connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` \n connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` \n connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` \n connect states[1].g, UInt<3>(0h3) \n node _T_69 = eq(states[1].g, UInt<3>(0h2)) \n node _T_70 = asUInt(reset) \n node _T_71 = eq(_T_70, UInt<1>(0h0)) \n when _T_71 : \n node _T_72 = eq(_T_69, UInt<1>(0h0)) \n when _T_72 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at InputUnit.scala:291 assert(states(i).g === g_v)\\n\") : printf_4 \n assert(clock, _T_69, UInt<1>(0h1), \"\") : assert_4 \n node _T_73 = bits(vcalloc_sel, 2, 2) \n when _T_73 : \n connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` \n connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` \n connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` \n connect states[2].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` \n connect states[2].g, UInt<3>(0h3) \n node _T_74 = eq(states[2].g, UInt<3>(0h2)) \n node _T_75 = asUInt(reset) \n node _T_76 = eq(_T_75, UInt<1>(0h0)) \n when _T_76 : \n node _T_77 = eq(_T_74, UInt<1>(0h0)) \n when _T_77 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at InputUnit.scala:291 assert(states(i).g === g_v)\\n\") : printf_5 \n assert(clock, _T_74, UInt<1>(0h1), \"\") : assert_5 \n node _T_78 = bits(vcalloc_sel, 3, 3) \n when _T_78 : \n connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` \n connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` \n connect states[3].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` \n connect states[3].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` \n connect states[3].g, UInt<3>(0h3) \n node _T_79 = eq(states[3].g, UInt<3>(0h2)) \n node _T_80 = asUInt(reset) \n node _T_81 = eq(_T_80, UInt<1>(0h0)) \n when _T_81 : \n node _T_82 = eq(_T_79, UInt<1>(0h0)) \n when _T_82 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at InputUnit.scala:291 assert(states(i).g === g_v)\\n\") : printf_6 \n assert(clock, _T_79, UInt<1>(0h1), \"\") : assert_6 \n node _T_83 = bits(vcalloc_sel, 4, 4) \n when _T_83 : \n connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` \n connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` \n connect states[4].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` \n connect states[4].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` \n connect states[4].g, UInt<3>(0h3) \n node _T_84 = eq(states[4].g, UInt<3>(0h2)) \n node _T_85 = asUInt(reset) \n node _T_86 = eq(_T_85, UInt<1>(0h0)) \n when _T_86 : \n node _T_87 = eq(_T_84, UInt<1>(0h0)) \n when _T_87 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at InputUnit.scala:291 assert(states(i).g === g_v)\\n\") : printf_7 \n assert(clock, _T_84, UInt<1>(0h1), \"\") : assert_7 \n node _T_88 = bits(vcalloc_sel, 5, 5) \n when _T_88 : \n connect states[5].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` \n connect states[5].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` \n connect states[5].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` \n connect states[5].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` \n connect states[5].g, UInt<3>(0h3) \n node _T_89 = eq(states[5].g, UInt<3>(0h2)) \n node _T_90 = asUInt(reset) \n node _T_91 = eq(_T_90, UInt<1>(0h0)) \n when _T_91 : \n node _T_92 = eq(_T_89, UInt<1>(0h0)) \n when _T_92 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at InputUnit.scala:291 assert(states(i).g === g_v)\\n\") : printf_8 \n assert(clock, _T_89, UInt<1>(0h1), \"\") : assert_8 \n node _T_93 = bits(vcalloc_sel, 6, 6) \n when _T_93 : \n connect states[6].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` \n connect states[6].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` \n connect states[6].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` \n connect states[6].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` \n connect states[6].g, UInt<3>(0h3) \n node _T_94 = eq(states[6].g, UInt<3>(0h2)) \n node _T_95 = asUInt(reset) \n node _T_96 = eq(_T_95, UInt<1>(0h0)) \n when _T_96 : \n node _T_97 = eq(_T_94, UInt<1>(0h0)) \n when _T_97 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at InputUnit.scala:291 assert(states(i).g === g_v)\\n\") : printf_9 \n assert(clock, _T_94, UInt<1>(0h1), \"\") : assert_9 \n node _T_98 = bits(vcalloc_sel, 7, 7) \n when _T_98 : \n connect states[7].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` \n connect states[7].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` \n connect states[7].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` \n connect states[7].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` \n connect states[7].g, UInt<3>(0h3) \n node _T_99 = eq(states[7].g, UInt<3>(0h2)) \n node _T_100 = asUInt(reset) \n node _T_101 = eq(_T_100, UInt<1>(0h0)) \n when _T_101 : \n node _T_102 = eq(_T_99, UInt<1>(0h0)) \n when _T_102 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at InputUnit.scala:291 assert(states(i).g === g_v)\\n\") : printf_10 \n assert(clock, _T_99, UInt<1>(0h1), \"\") : assert_10 \n inst salloc_arb of SwitchArbiter_151 \n connect salloc_arb.clock, clock\n\n connect salloc_arb.reset, reset\n\n node credit_available_lo_lo = cat(states[0].vc_sel.`0`[1], states[0].vc_sel.`0`[0]) \n node credit_available_lo_hi = cat(states[0].vc_sel.`0`[3], states[0].vc_sel.`0`[2]) \n node credit_available_lo = cat(credit_available_lo_hi, credit_available_lo_lo) \n node credit_available_hi_lo = cat(states[0].vc_sel.`0`[5], states[0].vc_sel.`0`[4]) \n node credit_available_hi_hi = cat(states[0].vc_sel.`0`[7], states[0].vc_sel.`0`[6]) \n node credit_available_hi = cat(credit_available_hi_hi, credit_available_hi_lo) \n node _credit_available_T = cat(credit_available_hi, credit_available_lo) \n node credit_available_lo_lo_1 = cat(states[0].vc_sel.`1`[1], states[0].vc_sel.`1`[0]) \n node credit_available_lo_hi_1 = cat(states[0].vc_sel.`1`[3], states[0].vc_sel.`1`[2]) \n node credit_available_lo_1 = cat(credit_available_lo_hi_1, credit_available_lo_lo_1) \n node credit_available_hi_lo_1 = cat(states[0].vc_sel.`1`[5], states[0].vc_sel.`1`[4]) \n node credit_available_hi_hi_1 = cat(states[0].vc_sel.`1`[7], states[0].vc_sel.`1`[6]) \n node credit_available_hi_1 = cat(credit_available_hi_hi_1, credit_available_hi_lo_1) \n node _credit_available_T_1 = cat(credit_available_hi_1, credit_available_lo_1) \n node credit_available_lo_lo_2 = cat(states[0].vc_sel.`2`[1], states[0].vc_sel.`2`[0]) \n node credit_available_lo_hi_2 = cat(states[0].vc_sel.`2`[3], states[0].vc_sel.`2`[2]) \n node credit_available_lo_2 = cat(credit_available_lo_hi_2, credit_available_lo_lo_2) \n node credit_available_hi_lo_2 = cat(states[0].vc_sel.`2`[5], states[0].vc_sel.`2`[4]) \n node credit_available_hi_hi_2 = cat(states[0].vc_sel.`2`[7], states[0].vc_sel.`2`[6]) \n node credit_available_hi_2 = cat(credit_available_hi_hi_2, credit_available_hi_lo_2) \n node _credit_available_T_2 = cat(credit_available_hi_2, credit_available_lo_2) \n node credit_available_lo_lo_3 = cat(states[0].vc_sel.`3`[1], states[0].vc_sel.`3`[0]) \n node credit_available_lo_hi_3 = cat(states[0].vc_sel.`3`[3], states[0].vc_sel.`3`[2]) \n node credit_available_lo_3 = cat(credit_available_lo_hi_3, credit_available_lo_lo_3) \n node credit_available_hi_lo_3 = cat(states[0].vc_sel.`3`[5], states[0].vc_sel.`3`[4]) \n node credit_available_hi_hi_3 = cat(states[0].vc_sel.`3`[7], states[0].vc_sel.`3`[6]) \n node credit_available_hi_3 = cat(credit_available_hi_hi_3, credit_available_hi_lo_3) \n node _credit_available_T_3 = cat(credit_available_hi_3, credit_available_lo_3) \n node credit_available_lo_4 = cat(_credit_available_T_1, _credit_available_T) \n node credit_available_hi_4 = cat(_credit_available_T_3, _credit_available_T_2) \n node _credit_available_T_4 = cat(credit_available_hi_4, credit_available_lo_4) \n node credit_available_lo_lo_4 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) \n node credit_available_lo_hi_4 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) \n node credit_available_lo_5 = cat(credit_available_lo_hi_4, credit_available_lo_lo_4) \n node credit_available_hi_lo_4 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) \n node credit_available_hi_hi_4 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) \n node credit_available_hi_5 = cat(credit_available_hi_hi_4, credit_available_hi_lo_4) \n node _credit_available_T_5 = cat(credit_available_hi_5, credit_available_lo_5) \n node credit_available_lo_lo_5 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) \n node credit_available_lo_hi_5 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) \n node credit_available_lo_6 = cat(credit_available_lo_hi_5, credit_available_lo_lo_5) \n node credit_available_hi_lo_5 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) \n node credit_available_hi_hi_5 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) \n node credit_available_hi_6 = cat(credit_available_hi_hi_5, credit_available_hi_lo_5) \n node _credit_available_T_6 = cat(credit_available_hi_6, credit_available_lo_6) \n node credit_available_lo_lo_6 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) \n node credit_available_lo_hi_6 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) \n node credit_available_lo_7 = cat(credit_available_lo_hi_6, credit_available_lo_lo_6) \n node credit_available_hi_lo_6 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) \n node credit_available_hi_hi_6 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) \n node credit_available_hi_7 = cat(credit_available_hi_hi_6, credit_available_hi_lo_6) \n node _credit_available_T_7 = cat(credit_available_hi_7, credit_available_lo_7) \n node credit_available_lo_lo_7 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) \n node credit_available_lo_hi_7 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) \n node credit_available_lo_8 = cat(credit_available_lo_hi_7, credit_available_lo_lo_7) \n node credit_available_hi_lo_7 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) \n node credit_available_hi_hi_7 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) \n node credit_available_hi_8 = cat(credit_available_hi_hi_7, credit_available_hi_lo_7) \n node _credit_available_T_8 = cat(credit_available_hi_8, credit_available_lo_8) \n node credit_available_lo_9 = cat(_credit_available_T_6, _credit_available_T_5) \n node credit_available_hi_9 = cat(_credit_available_T_8, _credit_available_T_7) \n node _credit_available_T_9 = cat(credit_available_hi_9, credit_available_lo_9) \n node _credit_available_T_10 = and(_credit_available_T_4, _credit_available_T_9) \n node credit_available = neq(_credit_available_T_10, UInt<1>(0h0)) \n node _salloc_arb_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h3)) \n node _salloc_arb_io_in_0_valid_T_1 = and(_salloc_arb_io_in_0_valid_T, credit_available) \n node _salloc_arb_io_in_0_valid_T_2 = and(_salloc_arb_io_in_0_valid_T_1, input_buffer.io.deq[0].valid) \n connect salloc_arb.io.in[0].valid, _salloc_arb_io_in_0_valid_T_2 \n connect salloc_arb.io.in[0].bits.vc_sel.`0`[0], states[0].vc_sel.`0`[0] \n connect salloc_arb.io.in[0].bits.vc_sel.`0`[1], states[0].vc_sel.`0`[1] \n connect salloc_arb.io.in[0].bits.vc_sel.`0`[2], states[0].vc_sel.`0`[2] \n connect salloc_arb.io.in[0].bits.vc_sel.`0`[3], states[0].vc_sel.`0`[3] \n connect salloc_arb.io.in[0].bits.vc_sel.`0`[4], states[0].vc_sel.`0`[4] \n connect salloc_arb.io.in[0].bits.vc_sel.`0`[5], states[0].vc_sel.`0`[5] \n connect salloc_arb.io.in[0].bits.vc_sel.`0`[6], states[0].vc_sel.`0`[6] \n connect salloc_arb.io.in[0].bits.vc_sel.`0`[7], states[0].vc_sel.`0`[7] \n connect salloc_arb.io.in[0].bits.vc_sel.`1`[0], states[0].vc_sel.`1`[0] \n connect salloc_arb.io.in[0].bits.vc_sel.`1`[1], states[0].vc_sel.`1`[1] \n connect salloc_arb.io.in[0].bits.vc_sel.`1`[2], states[0].vc_sel.`1`[2] \n connect salloc_arb.io.in[0].bits.vc_sel.`1`[3], states[0].vc_sel.`1`[3] \n connect salloc_arb.io.in[0].bits.vc_sel.`1`[4], states[0].vc_sel.`1`[4] \n connect salloc_arb.io.in[0].bits.vc_sel.`1`[5], states[0].vc_sel.`1`[5] \n connect salloc_arb.io.in[0].bits.vc_sel.`1`[6], states[0].vc_sel.`1`[6] \n connect salloc_arb.io.in[0].bits.vc_sel.`1`[7], states[0].vc_sel.`1`[7] \n connect salloc_arb.io.in[0].bits.vc_sel.`2`[0], states[0].vc_sel.`2`[0] \n connect salloc_arb.io.in[0].bits.vc_sel.`2`[1], states[0].vc_sel.`2`[1] \n connect salloc_arb.io.in[0].bits.vc_sel.`2`[2], states[0].vc_sel.`2`[2] \n connect salloc_arb.io.in[0].bits.vc_sel.`2`[3], states[0].vc_sel.`2`[3] \n connect salloc_arb.io.in[0].bits.vc_sel.`2`[4], states[0].vc_sel.`2`[4] \n connect salloc_arb.io.in[0].bits.vc_sel.`2`[5], states[0].vc_sel.`2`[5] \n connect salloc_arb.io.in[0].bits.vc_sel.`2`[6], states[0].vc_sel.`2`[6] \n connect salloc_arb.io.in[0].bits.vc_sel.`2`[7], states[0].vc_sel.`2`[7] \n connect salloc_arb.io.in[0].bits.vc_sel.`3`[0], states[0].vc_sel.`3`[0] \n connect salloc_arb.io.in[0].bits.vc_sel.`3`[1], states[0].vc_sel.`3`[1] \n connect salloc_arb.io.in[0].bits.vc_sel.`3`[2], states[0].vc_sel.`3`[2] \n connect salloc_arb.io.in[0].bits.vc_sel.`3`[3], states[0].vc_sel.`3`[3] \n connect salloc_arb.io.in[0].bits.vc_sel.`3`[4], states[0].vc_sel.`3`[4] \n connect salloc_arb.io.in[0].bits.vc_sel.`3`[5], states[0].vc_sel.`3`[5] \n connect salloc_arb.io.in[0].bits.vc_sel.`3`[6], states[0].vc_sel.`3`[6] \n connect salloc_arb.io.in[0].bits.vc_sel.`3`[7], states[0].vc_sel.`3`[7] \n connect salloc_arb.io.in[0].bits.tail, input_buffer.io.deq[0].bits.tail \n node _T_103 = and(salloc_arb.io.in[0].ready, salloc_arb.io.in[0].valid) \n node _T_104 = and(_T_103, input_buffer.io.deq[0].bits.tail) \n when _T_104 : \n connect states[0].g, UInt<3>(0h0) \n connect input_buffer.io.deq[0].ready, salloc_arb.io.in[0].ready \n node credit_available_lo_lo_8 = cat(states[1].vc_sel.`0`[1], states[1].vc_sel.`0`[0]) \n node credit_available_lo_hi_8 = cat(states[1].vc_sel.`0`[3], states[1].vc_sel.`0`[2]) \n node credit_available_lo_10 = cat(credit_available_lo_hi_8, credit_available_lo_lo_8) \n node credit_available_hi_lo_8 = cat(states[1].vc_sel.`0`[5], states[1].vc_sel.`0`[4]) \n node credit_available_hi_hi_8 = cat(states[1].vc_sel.`0`[7], states[1].vc_sel.`0`[6]) \n node credit_available_hi_10 = cat(credit_available_hi_hi_8, credit_available_hi_lo_8) \n node _credit_available_T_11 = cat(credit_available_hi_10, credit_available_lo_10) \n node credit_available_lo_lo_9 = cat(states[1].vc_sel.`1`[1], states[1].vc_sel.`1`[0]) \n node credit_available_lo_hi_9 = cat(states[1].vc_sel.`1`[3], states[1].vc_sel.`1`[2]) \n node credit_available_lo_11 = cat(credit_available_lo_hi_9, credit_available_lo_lo_9) \n node credit_available_hi_lo_9 = cat(states[1].vc_sel.`1`[5], states[1].vc_sel.`1`[4]) \n node credit_available_hi_hi_9 = cat(states[1].vc_sel.`1`[7], states[1].vc_sel.`1`[6]) \n node credit_available_hi_11 = cat(credit_available_hi_hi_9, credit_available_hi_lo_9) \n node _credit_available_T_12 = cat(credit_available_hi_11, credit_available_lo_11) \n node credit_available_lo_lo_10 = cat(states[1].vc_sel.`2`[1], states[1].vc_sel.`2`[0]) \n node credit_available_lo_hi_10 = cat(states[1].vc_sel.`2`[3], states[1].vc_sel.`2`[2]) \n node credit_available_lo_12 = cat(credit_available_lo_hi_10, credit_available_lo_lo_10) \n node credit_available_hi_lo_10 = cat(states[1].vc_sel.`2`[5], states[1].vc_sel.`2`[4]) \n node credit_available_hi_hi_10 = cat(states[1].vc_sel.`2`[7], states[1].vc_sel.`2`[6]) \n node credit_available_hi_12 = cat(credit_available_hi_hi_10, credit_available_hi_lo_10) \n node _credit_available_T_13 = cat(credit_available_hi_12, credit_available_lo_12) \n node credit_available_lo_lo_11 = cat(states[1].vc_sel.`3`[1], states[1].vc_sel.`3`[0]) \n node credit_available_lo_hi_11 = cat(states[1].vc_sel.`3`[3], states[1].vc_sel.`3`[2]) \n node credit_available_lo_13 = cat(credit_available_lo_hi_11, credit_available_lo_lo_11) \n node credit_available_hi_lo_11 = cat(states[1].vc_sel.`3`[5], states[1].vc_sel.`3`[4]) \n node credit_available_hi_hi_11 = cat(states[1].vc_sel.`3`[7], states[1].vc_sel.`3`[6]) \n node credit_available_hi_13 = cat(credit_available_hi_hi_11, credit_available_hi_lo_11) \n node _credit_available_T_14 = cat(credit_available_hi_13, credit_available_lo_13) \n node credit_available_lo_14 = cat(_credit_available_T_12, _credit_available_T_11) \n node credit_available_hi_14 = cat(_credit_available_T_14, _credit_available_T_13) \n node _credit_available_T_15 = cat(credit_available_hi_14, credit_available_lo_14) \n node credit_available_lo_lo_12 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) \n node credit_available_lo_hi_12 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) \n node credit_available_lo_15 = cat(credit_available_lo_hi_12, credit_available_lo_lo_12) \n node credit_available_hi_lo_12 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) \n node credit_available_hi_hi_12 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) \n node credit_available_hi_15 = cat(credit_available_hi_hi_12, credit_available_hi_lo_12) \n node _credit_available_T_16 = cat(credit_available_hi_15, credit_available_lo_15) \n node credit_available_lo_lo_13 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) \n node credit_available_lo_hi_13 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) \n node credit_available_lo_16 = cat(credit_available_lo_hi_13, credit_available_lo_lo_13) \n node credit_available_hi_lo_13 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) \n node credit_available_hi_hi_13 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) \n node credit_available_hi_16 = cat(credit_available_hi_hi_13, credit_available_hi_lo_13) \n node _credit_available_T_17 = cat(credit_available_hi_16, credit_available_lo_16) \n node credit_available_lo_lo_14 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) \n node credit_available_lo_hi_14 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) \n node credit_available_lo_17 = cat(credit_available_lo_hi_14, credit_available_lo_lo_14) \n node credit_available_hi_lo_14 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) \n node credit_available_hi_hi_14 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) \n node credit_available_hi_17 = cat(credit_available_hi_hi_14, credit_available_hi_lo_14) \n node _credit_available_T_18 = cat(credit_available_hi_17, credit_available_lo_17) \n node credit_available_lo_lo_15 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) \n node credit_available_lo_hi_15 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) \n node credit_available_lo_18 = cat(credit_available_lo_hi_15, credit_available_lo_lo_15) \n node credit_available_hi_lo_15 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) \n node credit_available_hi_hi_15 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) \n node credit_available_hi_18 = cat(credit_available_hi_hi_15, credit_available_hi_lo_15) \n node _credit_available_T_19 = cat(credit_available_hi_18, credit_available_lo_18) \n node credit_available_lo_19 = cat(_credit_available_T_17, _credit_available_T_16) \n node credit_available_hi_19 = cat(_credit_available_T_19, _credit_available_T_18) \n node _credit_available_T_20 = cat(credit_available_hi_19, credit_available_lo_19) \n node _credit_available_T_21 = and(_credit_available_T_15, _credit_available_T_20) \n node credit_available_1 = neq(_credit_available_T_21, UInt<1>(0h0)) \n node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3)) \n node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available_1) \n node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid) \n connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2 \n connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0] \n connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1] \n connect salloc_arb.io.in[1].bits.vc_sel.`0`[2], states[1].vc_sel.`0`[2] \n connect salloc_arb.io.in[1].bits.vc_sel.`0`[3], states[1].vc_sel.`0`[3] \n connect salloc_arb.io.in[1].bits.vc_sel.`0`[4], states[1].vc_sel.`0`[4] \n connect salloc_arb.io.in[1].bits.vc_sel.`0`[5], states[1].vc_sel.`0`[5] \n connect salloc_arb.io.in[1].bits.vc_sel.`0`[6], states[1].vc_sel.`0`[6] \n connect salloc_arb.io.in[1].bits.vc_sel.`0`[7], states[1].vc_sel.`0`[7] \n connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0] \n connect salloc_arb.io.in[1].bits.vc_sel.`1`[1], states[1].vc_sel.`1`[1] \n connect salloc_arb.io.in[1].bits.vc_sel.`1`[2], states[1].vc_sel.`1`[2] \n connect salloc_arb.io.in[1].bits.vc_sel.`1`[3], states[1].vc_sel.`1`[3] \n connect salloc_arb.io.in[1].bits.vc_sel.`1`[4], states[1].vc_sel.`1`[4] \n connect salloc_arb.io.in[1].bits.vc_sel.`1`[5], states[1].vc_sel.`1`[5] \n connect salloc_arb.io.in[1].bits.vc_sel.`1`[6], states[1].vc_sel.`1`[6] \n connect salloc_arb.io.in[1].bits.vc_sel.`1`[7], states[1].vc_sel.`1`[7] \n connect salloc_arb.io.in[1].bits.vc_sel.`2`[0], states[1].vc_sel.`2`[0] \n connect salloc_arb.io.in[1].bits.vc_sel.`2`[1], states[1].vc_sel.`2`[1] \n connect salloc_arb.io.in[1].bits.vc_sel.`2`[2], states[1].vc_sel.`2`[2] \n connect salloc_arb.io.in[1].bits.vc_sel.`2`[3], states[1].vc_sel.`2`[3] \n connect salloc_arb.io.in[1].bits.vc_sel.`2`[4], states[1].vc_sel.`2`[4] \n connect salloc_arb.io.in[1].bits.vc_sel.`2`[5], states[1].vc_sel.`2`[5] \n connect salloc_arb.io.in[1].bits.vc_sel.`2`[6], states[1].vc_sel.`2`[6] \n connect salloc_arb.io.in[1].bits.vc_sel.`2`[7], states[1].vc_sel.`2`[7] \n connect salloc_arb.io.in[1].bits.vc_sel.`3`[0], states[1].vc_sel.`3`[0] \n connect salloc_arb.io.in[1].bits.vc_sel.`3`[1], states[1].vc_sel.`3`[1] \n connect salloc_arb.io.in[1].bits.vc_sel.`3`[2], states[1].vc_sel.`3`[2] \n connect salloc_arb.io.in[1].bits.vc_sel.`3`[3], states[1].vc_sel.`3`[3] \n connect salloc_arb.io.in[1].bits.vc_sel.`3`[4], states[1].vc_sel.`3`[4] \n connect salloc_arb.io.in[1].bits.vc_sel.`3`[5], states[1].vc_sel.`3`[5] \n connect salloc_arb.io.in[1].bits.vc_sel.`3`[6], states[1].vc_sel.`3`[6] \n connect salloc_arb.io.in[1].bits.vc_sel.`3`[7], states[1].vc_sel.`3`[7] \n connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail \n node _T_105 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid) \n node _T_106 = and(_T_105, input_buffer.io.deq[1].bits.tail) \n when _T_106 : \n connect states[1].g, UInt<3>(0h0) \n connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready \n node credit_available_lo_lo_16 = cat(states[2].vc_sel.`0`[1], states[2].vc_sel.`0`[0]) \n node credit_available_lo_hi_16 = cat(states[2].vc_sel.`0`[3], states[2].vc_sel.`0`[2]) \n node credit_available_lo_20 = cat(credit_available_lo_hi_16, credit_available_lo_lo_16) \n node credit_available_hi_lo_16 = cat(states[2].vc_sel.`0`[5], states[2].vc_sel.`0`[4]) \n node credit_available_hi_hi_16 = cat(states[2].vc_sel.`0`[7], states[2].vc_sel.`0`[6]) \n node credit_available_hi_20 = cat(credit_available_hi_hi_16, credit_available_hi_lo_16) \n node _credit_available_T_22 = cat(credit_available_hi_20, credit_available_lo_20) \n node credit_available_lo_lo_17 = cat(states[2].vc_sel.`1`[1], states[2].vc_sel.`1`[0]) \n node credit_available_lo_hi_17 = cat(states[2].vc_sel.`1`[3], states[2].vc_sel.`1`[2]) \n node credit_available_lo_21 = cat(credit_available_lo_hi_17, credit_available_lo_lo_17) \n node credit_available_hi_lo_17 = cat(states[2].vc_sel.`1`[5], states[2].vc_sel.`1`[4]) \n node credit_available_hi_hi_17 = cat(states[2].vc_sel.`1`[7], states[2].vc_sel.`1`[6]) \n node credit_available_hi_21 = cat(credit_available_hi_hi_17, credit_available_hi_lo_17) \n node _credit_available_T_23 = cat(credit_available_hi_21, credit_available_lo_21) \n node credit_available_lo_lo_18 = cat(states[2].vc_sel.`2`[1], states[2].vc_sel.`2`[0]) \n node credit_available_lo_hi_18 = cat(states[2].vc_sel.`2`[3], states[2].vc_sel.`2`[2]) \n node credit_available_lo_22 = cat(credit_available_lo_hi_18, credit_available_lo_lo_18) \n node credit_available_hi_lo_18 = cat(states[2].vc_sel.`2`[5], states[2].vc_sel.`2`[4]) \n node credit_available_hi_hi_18 = cat(states[2].vc_sel.`2`[7], states[2].vc_sel.`2`[6]) \n node credit_available_hi_22 = cat(credit_available_hi_hi_18, credit_available_hi_lo_18) \n node _credit_available_T_24 = cat(credit_available_hi_22, credit_available_lo_22) \n node credit_available_lo_lo_19 = cat(states[2].vc_sel.`3`[1], states[2].vc_sel.`3`[0]) \n node credit_available_lo_hi_19 = cat(states[2].vc_sel.`3`[3], states[2].vc_sel.`3`[2]) \n node credit_available_lo_23 = cat(credit_available_lo_hi_19, credit_available_lo_lo_19) \n node credit_available_hi_lo_19 = cat(states[2].vc_sel.`3`[5], states[2].vc_sel.`3`[4]) \n node credit_available_hi_hi_19 = cat(states[2].vc_sel.`3`[7], states[2].vc_sel.`3`[6]) \n node credit_available_hi_23 = cat(credit_available_hi_hi_19, credit_available_hi_lo_19) \n node _credit_available_T_25 = cat(credit_available_hi_23, credit_available_lo_23) \n node credit_available_lo_24 = cat(_credit_available_T_23, _credit_available_T_22) \n node credit_available_hi_24 = cat(_credit_available_T_25, _credit_available_T_24) \n node _credit_available_T_26 = cat(credit_available_hi_24, credit_available_lo_24) \n node credit_available_lo_lo_20 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) \n node credit_available_lo_hi_20 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) \n node credit_available_lo_25 = cat(credit_available_lo_hi_20, credit_available_lo_lo_20) \n node credit_available_hi_lo_20 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) \n node credit_available_hi_hi_20 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) \n node credit_available_hi_25 = cat(credit_available_hi_hi_20, credit_available_hi_lo_20) \n node _credit_available_T_27 = cat(credit_available_hi_25, credit_available_lo_25) \n node credit_available_lo_lo_21 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) \n node credit_available_lo_hi_21 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) \n node credit_available_lo_26 = cat(credit_available_lo_hi_21, credit_available_lo_lo_21) \n node credit_available_hi_lo_21 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) \n node credit_available_hi_hi_21 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) \n node credit_available_hi_26 = cat(credit_available_hi_hi_21, credit_available_hi_lo_21) \n node _credit_available_T_28 = cat(credit_available_hi_26, credit_available_lo_26) \n node credit_available_lo_lo_22 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) \n node credit_available_lo_hi_22 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) \n node credit_available_lo_27 = cat(credit_available_lo_hi_22, credit_available_lo_lo_22) \n node credit_available_hi_lo_22 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) \n node credit_available_hi_hi_22 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) \n node credit_available_hi_27 = cat(credit_available_hi_hi_22, credit_available_hi_lo_22) \n node _credit_available_T_29 = cat(credit_available_hi_27, credit_available_lo_27) \n node credit_available_lo_lo_23 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) \n node credit_available_lo_hi_23 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) \n node credit_available_lo_28 = cat(credit_available_lo_hi_23, credit_available_lo_lo_23) \n node credit_available_hi_lo_23 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) \n node credit_available_hi_hi_23 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) \n node credit_available_hi_28 = cat(credit_available_hi_hi_23, credit_available_hi_lo_23) \n node _credit_available_T_30 = cat(credit_available_hi_28, credit_available_lo_28) \n node credit_available_lo_29 = cat(_credit_available_T_28, _credit_available_T_27) \n node credit_available_hi_29 = cat(_credit_available_T_30, _credit_available_T_29) \n node _credit_available_T_31 = cat(credit_available_hi_29, credit_available_lo_29) \n node _credit_available_T_32 = and(_credit_available_T_26, _credit_available_T_31) \n node credit_available_2 = neq(_credit_available_T_32, UInt<1>(0h0)) \n node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3)) \n node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available_2) \n node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid) \n connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2 \n connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0] \n connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1] \n connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2] \n connect salloc_arb.io.in[2].bits.vc_sel.`0`[3], states[2].vc_sel.`0`[3] \n connect salloc_arb.io.in[2].bits.vc_sel.`0`[4], states[2].vc_sel.`0`[4] \n connect salloc_arb.io.in[2].bits.vc_sel.`0`[5], states[2].vc_sel.`0`[5] \n connect salloc_arb.io.in[2].bits.vc_sel.`0`[6], states[2].vc_sel.`0`[6] \n connect salloc_arb.io.in[2].bits.vc_sel.`0`[7], states[2].vc_sel.`0`[7] \n connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0] \n connect salloc_arb.io.in[2].bits.vc_sel.`1`[1], states[2].vc_sel.`1`[1] \n connect salloc_arb.io.in[2].bits.vc_sel.`1`[2], states[2].vc_sel.`1`[2] \n connect salloc_arb.io.in[2].bits.vc_sel.`1`[3], states[2].vc_sel.`1`[3] \n connect salloc_arb.io.in[2].bits.vc_sel.`1`[4], states[2].vc_sel.`1`[4] \n connect salloc_arb.io.in[2].bits.vc_sel.`1`[5], states[2].vc_sel.`1`[5] \n connect salloc_arb.io.in[2].bits.vc_sel.`1`[6], states[2].vc_sel.`1`[6] \n connect salloc_arb.io.in[2].bits.vc_sel.`1`[7], states[2].vc_sel.`1`[7] \n connect salloc_arb.io.in[2].bits.vc_sel.`2`[0], states[2].vc_sel.`2`[0] \n connect salloc_arb.io.in[2].bits.vc_sel.`2`[1], states[2].vc_sel.`2`[1] \n connect salloc_arb.io.in[2].bits.vc_sel.`2`[2], states[2].vc_sel.`2`[2] \n connect salloc_arb.io.in[2].bits.vc_sel.`2`[3], states[2].vc_sel.`2`[3] \n connect salloc_arb.io.in[2].bits.vc_sel.`2`[4], states[2].vc_sel.`2`[4] \n connect salloc_arb.io.in[2].bits.vc_sel.`2`[5], states[2].vc_sel.`2`[5] \n connect salloc_arb.io.in[2].bits.vc_sel.`2`[6], states[2].vc_sel.`2`[6] \n connect salloc_arb.io.in[2].bits.vc_sel.`2`[7], states[2].vc_sel.`2`[7] \n connect salloc_arb.io.in[2].bits.vc_sel.`3`[0], states[2].vc_sel.`3`[0] \n connect salloc_arb.io.in[2].bits.vc_sel.`3`[1], states[2].vc_sel.`3`[1] \n connect salloc_arb.io.in[2].bits.vc_sel.`3`[2], states[2].vc_sel.`3`[2] \n connect salloc_arb.io.in[2].bits.vc_sel.`3`[3], states[2].vc_sel.`3`[3] \n connect salloc_arb.io.in[2].bits.vc_sel.`3`[4], states[2].vc_sel.`3`[4] \n connect salloc_arb.io.in[2].bits.vc_sel.`3`[5], states[2].vc_sel.`3`[5] \n connect salloc_arb.io.in[2].bits.vc_sel.`3`[6], states[2].vc_sel.`3`[6] \n connect salloc_arb.io.in[2].bits.vc_sel.`3`[7], states[2].vc_sel.`3`[7] \n connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail \n node _T_107 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid) \n node _T_108 = and(_T_107, input_buffer.io.deq[2].bits.tail) \n when _T_108 : \n connect states[2].g, UInt<3>(0h0) \n connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready \n node credit_available_lo_lo_24 = cat(states[3].vc_sel.`0`[1], states[3].vc_sel.`0`[0]) \n node credit_available_lo_hi_24 = cat(states[3].vc_sel.`0`[3], states[3].vc_sel.`0`[2]) \n node credit_available_lo_30 = cat(credit_available_lo_hi_24, credit_available_lo_lo_24) \n node credit_available_hi_lo_24 = cat(states[3].vc_sel.`0`[5], states[3].vc_sel.`0`[4]) \n node credit_available_hi_hi_24 = cat(states[3].vc_sel.`0`[7], states[3].vc_sel.`0`[6]) \n node credit_available_hi_30 = cat(credit_available_hi_hi_24, credit_available_hi_lo_24) \n node _credit_available_T_33 = cat(credit_available_hi_30, credit_available_lo_30) \n node credit_available_lo_lo_25 = cat(states[3].vc_sel.`1`[1], states[3].vc_sel.`1`[0]) \n node credit_available_lo_hi_25 = cat(states[3].vc_sel.`1`[3], states[3].vc_sel.`1`[2]) \n node credit_available_lo_31 = cat(credit_available_lo_hi_25, credit_available_lo_lo_25) \n node credit_available_hi_lo_25 = cat(states[3].vc_sel.`1`[5], states[3].vc_sel.`1`[4]) \n node credit_available_hi_hi_25 = cat(states[3].vc_sel.`1`[7], states[3].vc_sel.`1`[6]) \n node credit_available_hi_31 = cat(credit_available_hi_hi_25, credit_available_hi_lo_25) \n node _credit_available_T_34 = cat(credit_available_hi_31, credit_available_lo_31) \n node credit_available_lo_lo_26 = cat(states[3].vc_sel.`2`[1], states[3].vc_sel.`2`[0]) \n node credit_available_lo_hi_26 = cat(states[3].vc_sel.`2`[3], states[3].vc_sel.`2`[2]) \n node credit_available_lo_32 = cat(credit_available_lo_hi_26, credit_available_lo_lo_26) \n node credit_available_hi_lo_26 = cat(states[3].vc_sel.`2`[5], states[3].vc_sel.`2`[4]) \n node credit_available_hi_hi_26 = cat(states[3].vc_sel.`2`[7], states[3].vc_sel.`2`[6]) \n node credit_available_hi_32 = cat(credit_available_hi_hi_26, credit_available_hi_lo_26) \n node _credit_available_T_35 = cat(credit_available_hi_32, credit_available_lo_32) \n node credit_available_lo_lo_27 = cat(states[3].vc_sel.`3`[1], states[3].vc_sel.`3`[0]) \n node credit_available_lo_hi_27 = cat(states[3].vc_sel.`3`[3], states[3].vc_sel.`3`[2]) \n node credit_available_lo_33 = cat(credit_available_lo_hi_27, credit_available_lo_lo_27) \n node credit_available_hi_lo_27 = cat(states[3].vc_sel.`3`[5], states[3].vc_sel.`3`[4]) \n node credit_available_hi_hi_27 = cat(states[3].vc_sel.`3`[7], states[3].vc_sel.`3`[6]) \n node credit_available_hi_33 = cat(credit_available_hi_hi_27, credit_available_hi_lo_27) \n node _credit_available_T_36 = cat(credit_available_hi_33, credit_available_lo_33) \n node credit_available_lo_34 = cat(_credit_available_T_34, _credit_available_T_33) \n node credit_available_hi_34 = cat(_credit_available_T_36, _credit_available_T_35) \n node _credit_available_T_37 = cat(credit_available_hi_34, credit_available_lo_34) \n node credit_available_lo_lo_28 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) \n node credit_available_lo_hi_28 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) \n node credit_available_lo_35 = cat(credit_available_lo_hi_28, credit_available_lo_lo_28) \n node credit_available_hi_lo_28 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) \n node credit_available_hi_hi_28 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) \n node credit_available_hi_35 = cat(credit_available_hi_hi_28, credit_available_hi_lo_28) \n node _credit_available_T_38 = cat(credit_available_hi_35, credit_available_lo_35) \n node credit_available_lo_lo_29 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) \n node credit_available_lo_hi_29 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) \n node credit_available_lo_36 = cat(credit_available_lo_hi_29, credit_available_lo_lo_29) \n node credit_available_hi_lo_29 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) \n node credit_available_hi_hi_29 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) \n node credit_available_hi_36 = cat(credit_available_hi_hi_29, credit_available_hi_lo_29) \n node _credit_available_T_39 = cat(credit_available_hi_36, credit_available_lo_36) \n node credit_available_lo_lo_30 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) \n node credit_available_lo_hi_30 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) \n node credit_available_lo_37 = cat(credit_available_lo_hi_30, credit_available_lo_lo_30) \n node credit_available_hi_lo_30 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) \n node credit_available_hi_hi_30 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) \n node credit_available_hi_37 = cat(credit_available_hi_hi_30, credit_available_hi_lo_30) \n node _credit_available_T_40 = cat(credit_available_hi_37, credit_available_lo_37) \n node credit_available_lo_lo_31 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) \n node credit_available_lo_hi_31 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) \n node credit_available_lo_38 = cat(credit_available_lo_hi_31, credit_available_lo_lo_31) \n node credit_available_hi_lo_31 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) \n node credit_available_hi_hi_31 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) \n node credit_available_hi_38 = cat(credit_available_hi_hi_31, credit_available_hi_lo_31) \n node _credit_available_T_41 = cat(credit_available_hi_38, credit_available_lo_38) \n node credit_available_lo_39 = cat(_credit_available_T_39, _credit_available_T_38) \n node credit_available_hi_39 = cat(_credit_available_T_41, _credit_available_T_40) \n node _credit_available_T_42 = cat(credit_available_hi_39, credit_available_lo_39) \n node _credit_available_T_43 = and(_credit_available_T_37, _credit_available_T_42) \n node credit_available_3 = neq(_credit_available_T_43, UInt<1>(0h0)) \n node _salloc_arb_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h3)) \n node _salloc_arb_io_in_3_valid_T_1 = and(_salloc_arb_io_in_3_valid_T, credit_available_3) \n node _salloc_arb_io_in_3_valid_T_2 = and(_salloc_arb_io_in_3_valid_T_1, input_buffer.io.deq[3].valid) \n connect salloc_arb.io.in[3].valid, _salloc_arb_io_in_3_valid_T_2 \n connect salloc_arb.io.in[3].bits.vc_sel.`0`[0], states[3].vc_sel.`0`[0] \n connect salloc_arb.io.in[3].bits.vc_sel.`0`[1], states[3].vc_sel.`0`[1] \n connect salloc_arb.io.in[3].bits.vc_sel.`0`[2], states[3].vc_sel.`0`[2] \n connect salloc_arb.io.in[3].bits.vc_sel.`0`[3], states[3].vc_sel.`0`[3] \n connect salloc_arb.io.in[3].bits.vc_sel.`0`[4], states[3].vc_sel.`0`[4] \n connect salloc_arb.io.in[3].bits.vc_sel.`0`[5], states[3].vc_sel.`0`[5] \n connect salloc_arb.io.in[3].bits.vc_sel.`0`[6], states[3].vc_sel.`0`[6] \n connect salloc_arb.io.in[3].bits.vc_sel.`0`[7], states[3].vc_sel.`0`[7] \n connect salloc_arb.io.in[3].bits.vc_sel.`1`[0], states[3].vc_sel.`1`[0] \n connect salloc_arb.io.in[3].bits.vc_sel.`1`[1], states[3].vc_sel.`1`[1] \n connect salloc_arb.io.in[3].bits.vc_sel.`1`[2], states[3].vc_sel.`1`[2] \n connect salloc_arb.io.in[3].bits.vc_sel.`1`[3], states[3].vc_sel.`1`[3] \n connect salloc_arb.io.in[3].bits.vc_sel.`1`[4], states[3].vc_sel.`1`[4] \n connect salloc_arb.io.in[3].bits.vc_sel.`1`[5], states[3].vc_sel.`1`[5] \n connect salloc_arb.io.in[3].bits.vc_sel.`1`[6], states[3].vc_sel.`1`[6] \n connect salloc_arb.io.in[3].bits.vc_sel.`1`[7], states[3].vc_sel.`1`[7] \n connect salloc_arb.io.in[3].bits.vc_sel.`2`[0], states[3].vc_sel.`2`[0] \n connect salloc_arb.io.in[3].bits.vc_sel.`2`[1], states[3].vc_sel.`2`[1] \n connect salloc_arb.io.in[3].bits.vc_sel.`2`[2], states[3].vc_sel.`2`[2] \n connect salloc_arb.io.in[3].bits.vc_sel.`2`[3], states[3].vc_sel.`2`[3] \n connect salloc_arb.io.in[3].bits.vc_sel.`2`[4], states[3].vc_sel.`2`[4] \n connect salloc_arb.io.in[3].bits.vc_sel.`2`[5], states[3].vc_sel.`2`[5] \n connect salloc_arb.io.in[3].bits.vc_sel.`2`[6], states[3].vc_sel.`2`[6] \n connect salloc_arb.io.in[3].bits.vc_sel.`2`[7], states[3].vc_sel.`2`[7] \n connect salloc_arb.io.in[3].bits.vc_sel.`3`[0], states[3].vc_sel.`3`[0] \n connect salloc_arb.io.in[3].bits.vc_sel.`3`[1], states[3].vc_sel.`3`[1] \n connect salloc_arb.io.in[3].bits.vc_sel.`3`[2], states[3].vc_sel.`3`[2] \n connect salloc_arb.io.in[3].bits.vc_sel.`3`[3], states[3].vc_sel.`3`[3] \n connect salloc_arb.io.in[3].bits.vc_sel.`3`[4], states[3].vc_sel.`3`[4] \n connect salloc_arb.io.in[3].bits.vc_sel.`3`[5], states[3].vc_sel.`3`[5] \n connect salloc_arb.io.in[3].bits.vc_sel.`3`[6], states[3].vc_sel.`3`[6] \n connect salloc_arb.io.in[3].bits.vc_sel.`3`[7], states[3].vc_sel.`3`[7] \n connect salloc_arb.io.in[3].bits.tail, input_buffer.io.deq[3].bits.tail \n node _T_109 = and(salloc_arb.io.in[3].ready, salloc_arb.io.in[3].valid) \n node _T_110 = and(_T_109, input_buffer.io.deq[3].bits.tail) \n when _T_110 : \n connect states[3].g, UInt<3>(0h0) \n connect input_buffer.io.deq[3].ready, salloc_arb.io.in[3].ready \n node credit_available_lo_lo_32 = cat(states[4].vc_sel.`0`[1], states[4].vc_sel.`0`[0]) \n node credit_available_lo_hi_32 = cat(states[4].vc_sel.`0`[3], states[4].vc_sel.`0`[2]) \n node credit_available_lo_40 = cat(credit_available_lo_hi_32, credit_available_lo_lo_32) \n node credit_available_hi_lo_32 = cat(states[4].vc_sel.`0`[5], states[4].vc_sel.`0`[4]) \n node credit_available_hi_hi_32 = cat(states[4].vc_sel.`0`[7], states[4].vc_sel.`0`[6]) \n node credit_available_hi_40 = cat(credit_available_hi_hi_32, credit_available_hi_lo_32) \n node _credit_available_T_44 = cat(credit_available_hi_40, credit_available_lo_40) \n node credit_available_lo_lo_33 = cat(states[4].vc_sel.`1`[1], states[4].vc_sel.`1`[0]) \n node credit_available_lo_hi_33 = cat(states[4].vc_sel.`1`[3], states[4].vc_sel.`1`[2]) \n node credit_available_lo_41 = cat(credit_available_lo_hi_33, credit_available_lo_lo_33) \n node credit_available_hi_lo_33 = cat(states[4].vc_sel.`1`[5], states[4].vc_sel.`1`[4]) \n node credit_available_hi_hi_33 = cat(states[4].vc_sel.`1`[7], states[4].vc_sel.`1`[6]) \n node credit_available_hi_41 = cat(credit_available_hi_hi_33, credit_available_hi_lo_33) \n node _credit_available_T_45 = cat(credit_available_hi_41, credit_available_lo_41) \n node credit_available_lo_lo_34 = cat(states[4].vc_sel.`2`[1], states[4].vc_sel.`2`[0]) \n node credit_available_lo_hi_34 = cat(states[4].vc_sel.`2`[3], states[4].vc_sel.`2`[2]) \n node credit_available_lo_42 = cat(credit_available_lo_hi_34, credit_available_lo_lo_34) \n node credit_available_hi_lo_34 = cat(states[4].vc_sel.`2`[5], states[4].vc_sel.`2`[4]) \n node credit_available_hi_hi_34 = cat(states[4].vc_sel.`2`[7], states[4].vc_sel.`2`[6]) \n node credit_available_hi_42 = cat(credit_available_hi_hi_34, credit_available_hi_lo_34) \n node _credit_available_T_46 = cat(credit_available_hi_42, credit_available_lo_42) \n node credit_available_lo_lo_35 = cat(states[4].vc_sel.`3`[1], states[4].vc_sel.`3`[0]) \n node credit_available_lo_hi_35 = cat(states[4].vc_sel.`3`[3], states[4].vc_sel.`3`[2]) \n node credit_available_lo_43 = cat(credit_available_lo_hi_35, credit_available_lo_lo_35) \n node credit_available_hi_lo_35 = cat(states[4].vc_sel.`3`[5], states[4].vc_sel.`3`[4]) \n node credit_available_hi_hi_35 = cat(states[4].vc_sel.`3`[7], states[4].vc_sel.`3`[6]) \n node credit_available_hi_43 = cat(credit_available_hi_hi_35, credit_available_hi_lo_35) \n node _credit_available_T_47 = cat(credit_available_hi_43, credit_available_lo_43) \n node credit_available_lo_44 = cat(_credit_available_T_45, _credit_available_T_44) \n node credit_available_hi_44 = cat(_credit_available_T_47, _credit_available_T_46) \n node _credit_available_T_48 = cat(credit_available_hi_44, credit_available_lo_44) \n node credit_available_lo_lo_36 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) \n node credit_available_lo_hi_36 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) \n node credit_available_lo_45 = cat(credit_available_lo_hi_36, credit_available_lo_lo_36) \n node credit_available_hi_lo_36 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) \n node credit_available_hi_hi_36 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) \n node credit_available_hi_45 = cat(credit_available_hi_hi_36, credit_available_hi_lo_36) \n node _credit_available_T_49 = cat(credit_available_hi_45, credit_available_lo_45) \n node credit_available_lo_lo_37 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) \n node credit_available_lo_hi_37 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) \n node credit_available_lo_46 = cat(credit_available_lo_hi_37, credit_available_lo_lo_37) \n node credit_available_hi_lo_37 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) \n node credit_available_hi_hi_37 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) \n node credit_available_hi_46 = cat(credit_available_hi_hi_37, credit_available_hi_lo_37) \n node _credit_available_T_50 = cat(credit_available_hi_46, credit_available_lo_46) \n node credit_available_lo_lo_38 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) \n node credit_available_lo_hi_38 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) \n node credit_available_lo_47 = cat(credit_available_lo_hi_38, credit_available_lo_lo_38) \n node credit_available_hi_lo_38 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) \n node credit_available_hi_hi_38 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) \n node credit_available_hi_47 = cat(credit_available_hi_hi_38, credit_available_hi_lo_38) \n node _credit_available_T_51 = cat(credit_available_hi_47, credit_available_lo_47) \n node credit_available_lo_lo_39 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) \n node credit_available_lo_hi_39 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) \n node credit_available_lo_48 = cat(credit_available_lo_hi_39, credit_available_lo_lo_39) \n node credit_available_hi_lo_39 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) \n node credit_available_hi_hi_39 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) \n node credit_available_hi_48 = cat(credit_available_hi_hi_39, credit_available_hi_lo_39) \n node _credit_available_T_52 = cat(credit_available_hi_48, credit_available_lo_48) \n node credit_available_lo_49 = cat(_credit_available_T_50, _credit_available_T_49) \n node credit_available_hi_49 = cat(_credit_available_T_52, _credit_available_T_51) \n node _credit_available_T_53 = cat(credit_available_hi_49, credit_available_lo_49) \n node _credit_available_T_54 = and(_credit_available_T_48, _credit_available_T_53) \n node credit_available_4 = neq(_credit_available_T_54, UInt<1>(0h0)) \n node _salloc_arb_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h3)) \n node _salloc_arb_io_in_4_valid_T_1 = and(_salloc_arb_io_in_4_valid_T, credit_available_4) \n node _salloc_arb_io_in_4_valid_T_2 = and(_salloc_arb_io_in_4_valid_T_1, input_buffer.io.deq[4].valid) \n connect salloc_arb.io.in[4].valid, _salloc_arb_io_in_4_valid_T_2 \n connect salloc_arb.io.in[4].bits.vc_sel.`0`[0], states[4].vc_sel.`0`[0] \n connect salloc_arb.io.in[4].bits.vc_sel.`0`[1], states[4].vc_sel.`0`[1] \n connect salloc_arb.io.in[4].bits.vc_sel.`0`[2], states[4].vc_sel.`0`[2] \n connect salloc_arb.io.in[4].bits.vc_sel.`0`[3], states[4].vc_sel.`0`[3] \n connect salloc_arb.io.in[4].bits.vc_sel.`0`[4], states[4].vc_sel.`0`[4] \n connect salloc_arb.io.in[4].bits.vc_sel.`0`[5], states[4].vc_sel.`0`[5] \n connect salloc_arb.io.in[4].bits.vc_sel.`0`[6], states[4].vc_sel.`0`[6] \n connect salloc_arb.io.in[4].bits.vc_sel.`0`[7], states[4].vc_sel.`0`[7] \n connect salloc_arb.io.in[4].bits.vc_sel.`1`[0], states[4].vc_sel.`1`[0] \n connect salloc_arb.io.in[4].bits.vc_sel.`1`[1], states[4].vc_sel.`1`[1] \n connect salloc_arb.io.in[4].bits.vc_sel.`1`[2], states[4].vc_sel.`1`[2] \n connect salloc_arb.io.in[4].bits.vc_sel.`1`[3], states[4].vc_sel.`1`[3] \n connect salloc_arb.io.in[4].bits.vc_sel.`1`[4], states[4].vc_sel.`1`[4] \n connect salloc_arb.io.in[4].bits.vc_sel.`1`[5], states[4].vc_sel.`1`[5] \n connect salloc_arb.io.in[4].bits.vc_sel.`1`[6], states[4].vc_sel.`1`[6] \n connect salloc_arb.io.in[4].bits.vc_sel.`1`[7], states[4].vc_sel.`1`[7] \n connect salloc_arb.io.in[4].bits.vc_sel.`2`[0], states[4].vc_sel.`2`[0] \n connect salloc_arb.io.in[4].bits.vc_sel.`2`[1], states[4].vc_sel.`2`[1] \n connect salloc_arb.io.in[4].bits.vc_sel.`2`[2], states[4].vc_sel.`2`[2] \n connect salloc_arb.io.in[4].bits.vc_sel.`2`[3], states[4].vc_sel.`2`[3] \n connect salloc_arb.io.in[4].bits.vc_sel.`2`[4], states[4].vc_sel.`2`[4] \n connect salloc_arb.io.in[4].bits.vc_sel.`2`[5], states[4].vc_sel.`2`[5] \n connect salloc_arb.io.in[4].bits.vc_sel.`2`[6], states[4].vc_sel.`2`[6] \n connect salloc_arb.io.in[4].bits.vc_sel.`2`[7], states[4].vc_sel.`2`[7] \n connect salloc_arb.io.in[4].bits.vc_sel.`3`[0], states[4].vc_sel.`3`[0] \n connect salloc_arb.io.in[4].bits.vc_sel.`3`[1], states[4].vc_sel.`3`[1] \n connect salloc_arb.io.in[4].bits.vc_sel.`3`[2], states[4].vc_sel.`3`[2] \n connect salloc_arb.io.in[4].bits.vc_sel.`3`[3], states[4].vc_sel.`3`[3] \n connect salloc_arb.io.in[4].bits.vc_sel.`3`[4], states[4].vc_sel.`3`[4] \n connect salloc_arb.io.in[4].bits.vc_sel.`3`[5], states[4].vc_sel.`3`[5] \n connect salloc_arb.io.in[4].bits.vc_sel.`3`[6], states[4].vc_sel.`3`[6] \n connect salloc_arb.io.in[4].bits.vc_sel.`3`[7], states[4].vc_sel.`3`[7] \n connect salloc_arb.io.in[4].bits.tail, input_buffer.io.deq[4].bits.tail \n node _T_111 = and(salloc_arb.io.in[4].ready, salloc_arb.io.in[4].valid) \n node _T_112 = and(_T_111, input_buffer.io.deq[4].bits.tail) \n when _T_112 : \n connect states[4].g, UInt<3>(0h0) \n connect input_buffer.io.deq[4].ready, salloc_arb.io.in[4].ready \n node credit_available_lo_lo_40 = cat(states[5].vc_sel.`0`[1], states[5].vc_sel.`0`[0]) \n node credit_available_lo_hi_40 = cat(states[5].vc_sel.`0`[3], states[5].vc_sel.`0`[2]) \n node credit_available_lo_50 = cat(credit_available_lo_hi_40, credit_available_lo_lo_40) \n node credit_available_hi_lo_40 = cat(states[5].vc_sel.`0`[5], states[5].vc_sel.`0`[4]) \n node credit_available_hi_hi_40 = cat(states[5].vc_sel.`0`[7], states[5].vc_sel.`0`[6]) \n node credit_available_hi_50 = cat(credit_available_hi_hi_40, credit_available_hi_lo_40) \n node _credit_available_T_55 = cat(credit_available_hi_50, credit_available_lo_50) \n node credit_available_lo_lo_41 = cat(states[5].vc_sel.`1`[1], states[5].vc_sel.`1`[0]) \n node credit_available_lo_hi_41 = cat(states[5].vc_sel.`1`[3], states[5].vc_sel.`1`[2]) \n node credit_available_lo_51 = cat(credit_available_lo_hi_41, credit_available_lo_lo_41) \n node credit_available_hi_lo_41 = cat(states[5].vc_sel.`1`[5], states[5].vc_sel.`1`[4]) \n node credit_available_hi_hi_41 = cat(states[5].vc_sel.`1`[7], states[5].vc_sel.`1`[6]) \n node credit_available_hi_51 = cat(credit_available_hi_hi_41, credit_available_hi_lo_41) \n node _credit_available_T_56 = cat(credit_available_hi_51, credit_available_lo_51) \n node credit_available_lo_lo_42 = cat(states[5].vc_sel.`2`[1], states[5].vc_sel.`2`[0]) \n node credit_available_lo_hi_42 = cat(states[5].vc_sel.`2`[3], states[5].vc_sel.`2`[2]) \n node credit_available_lo_52 = cat(credit_available_lo_hi_42, credit_available_lo_lo_42) \n node credit_available_hi_lo_42 = cat(states[5].vc_sel.`2`[5], states[5].vc_sel.`2`[4]) \n node credit_available_hi_hi_42 = cat(states[5].vc_sel.`2`[7], states[5].vc_sel.`2`[6]) \n node credit_available_hi_52 = cat(credit_available_hi_hi_42, credit_available_hi_lo_42) \n node _credit_available_T_57 = cat(credit_available_hi_52, credit_available_lo_52) \n node credit_available_lo_lo_43 = cat(states[5].vc_sel.`3`[1], states[5].vc_sel.`3`[0]) \n node credit_available_lo_hi_43 = cat(states[5].vc_sel.`3`[3], states[5].vc_sel.`3`[2]) \n node credit_available_lo_53 = cat(credit_available_lo_hi_43, credit_available_lo_lo_43) \n node credit_available_hi_lo_43 = cat(states[5].vc_sel.`3`[5], states[5].vc_sel.`3`[4]) \n node credit_available_hi_hi_43 = cat(states[5].vc_sel.`3`[7], states[5].vc_sel.`3`[6]) \n node credit_available_hi_53 = cat(credit_available_hi_hi_43, credit_available_hi_lo_43) \n node _credit_available_T_58 = cat(credit_available_hi_53, credit_available_lo_53) \n node credit_available_lo_54 = cat(_credit_available_T_56, _credit_available_T_55) \n node credit_available_hi_54 = cat(_credit_available_T_58, _credit_available_T_57) \n node _credit_available_T_59 = cat(credit_available_hi_54, credit_available_lo_54) \n node credit_available_lo_lo_44 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) \n node credit_available_lo_hi_44 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) \n node credit_available_lo_55 = cat(credit_available_lo_hi_44, credit_available_lo_lo_44) \n node credit_available_hi_lo_44 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) \n node credit_available_hi_hi_44 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) \n node credit_available_hi_55 = cat(credit_available_hi_hi_44, credit_available_hi_lo_44) \n node _credit_available_T_60 = cat(credit_available_hi_55, credit_available_lo_55) \n node credit_available_lo_lo_45 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) \n node credit_available_lo_hi_45 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) \n node credit_available_lo_56 = cat(credit_available_lo_hi_45, credit_available_lo_lo_45) \n node credit_available_hi_lo_45 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) \n node credit_available_hi_hi_45 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) \n node credit_available_hi_56 = cat(credit_available_hi_hi_45, credit_available_hi_lo_45) \n node _credit_available_T_61 = cat(credit_available_hi_56, credit_available_lo_56) \n node credit_available_lo_lo_46 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) \n node credit_available_lo_hi_46 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) \n node credit_available_lo_57 = cat(credit_available_lo_hi_46, credit_available_lo_lo_46) \n node credit_available_hi_lo_46 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) \n node credit_available_hi_hi_46 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) \n node credit_available_hi_57 = cat(credit_available_hi_hi_46, credit_available_hi_lo_46) \n node _credit_available_T_62 = cat(credit_available_hi_57, credit_available_lo_57) \n node credit_available_lo_lo_47 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) \n node credit_available_lo_hi_47 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) \n node credit_available_lo_58 = cat(credit_available_lo_hi_47, credit_available_lo_lo_47) \n node credit_available_hi_lo_47 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) \n node credit_available_hi_hi_47 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) \n node credit_available_hi_58 = cat(credit_available_hi_hi_47, credit_available_hi_lo_47) \n node _credit_available_T_63 = cat(credit_available_hi_58, credit_available_lo_58) \n node credit_available_lo_59 = cat(_credit_available_T_61, _credit_available_T_60) \n node credit_available_hi_59 = cat(_credit_available_T_63, _credit_available_T_62) \n node _credit_available_T_64 = cat(credit_available_hi_59, credit_available_lo_59) \n node _credit_available_T_65 = and(_credit_available_T_59, _credit_available_T_64) \n node credit_available_5 = neq(_credit_available_T_65, UInt<1>(0h0)) \n node _salloc_arb_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h3)) \n node _salloc_arb_io_in_5_valid_T_1 = and(_salloc_arb_io_in_5_valid_T, credit_available_5) \n node _salloc_arb_io_in_5_valid_T_2 = and(_salloc_arb_io_in_5_valid_T_1, input_buffer.io.deq[5].valid) \n connect salloc_arb.io.in[5].valid, _salloc_arb_io_in_5_valid_T_2 \n connect salloc_arb.io.in[5].bits.vc_sel.`0`[0], states[5].vc_sel.`0`[0] \n connect salloc_arb.io.in[5].bits.vc_sel.`0`[1], states[5].vc_sel.`0`[1] \n connect salloc_arb.io.in[5].bits.vc_sel.`0`[2], states[5].vc_sel.`0`[2] \n connect salloc_arb.io.in[5].bits.vc_sel.`0`[3], states[5].vc_sel.`0`[3] \n connect salloc_arb.io.in[5].bits.vc_sel.`0`[4], states[5].vc_sel.`0`[4] \n connect salloc_arb.io.in[5].bits.vc_sel.`0`[5], states[5].vc_sel.`0`[5] \n connect salloc_arb.io.in[5].bits.vc_sel.`0`[6], states[5].vc_sel.`0`[6] \n connect salloc_arb.io.in[5].bits.vc_sel.`0`[7], states[5].vc_sel.`0`[7] \n connect salloc_arb.io.in[5].bits.vc_sel.`1`[0], states[5].vc_sel.`1`[0] \n connect salloc_arb.io.in[5].bits.vc_sel.`1`[1], states[5].vc_sel.`1`[1] \n connect salloc_arb.io.in[5].bits.vc_sel.`1`[2], states[5].vc_sel.`1`[2] \n connect salloc_arb.io.in[5].bits.vc_sel.`1`[3], states[5].vc_sel.`1`[3] \n connect salloc_arb.io.in[5].bits.vc_sel.`1`[4], states[5].vc_sel.`1`[4] \n connect salloc_arb.io.in[5].bits.vc_sel.`1`[5], states[5].vc_sel.`1`[5] \n connect salloc_arb.io.in[5].bits.vc_sel.`1`[6], states[5].vc_sel.`1`[6] \n connect salloc_arb.io.in[5].bits.vc_sel.`1`[7], states[5].vc_sel.`1`[7] \n connect salloc_arb.io.in[5].bits.vc_sel.`2`[0], states[5].vc_sel.`2`[0] \n connect salloc_arb.io.in[5].bits.vc_sel.`2`[1], states[5].vc_sel.`2`[1] \n connect salloc_arb.io.in[5].bits.vc_sel.`2`[2], states[5].vc_sel.`2`[2] \n connect salloc_arb.io.in[5].bits.vc_sel.`2`[3], states[5].vc_sel.`2`[3] \n connect salloc_arb.io.in[5].bits.vc_sel.`2`[4], states[5].vc_sel.`2`[4] \n connect salloc_arb.io.in[5].bits.vc_sel.`2`[5], states[5].vc_sel.`2`[5] \n connect salloc_arb.io.in[5].bits.vc_sel.`2`[6], states[5].vc_sel.`2`[6] \n connect salloc_arb.io.in[5].bits.vc_sel.`2`[7], states[5].vc_sel.`2`[7] \n connect salloc_arb.io.in[5].bits.vc_sel.`3`[0], states[5].vc_sel.`3`[0] \n connect salloc_arb.io.in[5].bits.vc_sel.`3`[1], states[5].vc_sel.`3`[1] \n connect salloc_arb.io.in[5].bits.vc_sel.`3`[2], states[5].vc_sel.`3`[2] \n connect salloc_arb.io.in[5].bits.vc_sel.`3`[3], states[5].vc_sel.`3`[3] \n connect salloc_arb.io.in[5].bits.vc_sel.`3`[4], states[5].vc_sel.`3`[4] \n connect salloc_arb.io.in[5].bits.vc_sel.`3`[5], states[5].vc_sel.`3`[5] \n connect salloc_arb.io.in[5].bits.vc_sel.`3`[6], states[5].vc_sel.`3`[6] \n connect salloc_arb.io.in[5].bits.vc_sel.`3`[7], states[5].vc_sel.`3`[7] \n connect salloc_arb.io.in[5].bits.tail, input_buffer.io.deq[5].bits.tail \n node _T_113 = and(salloc_arb.io.in[5].ready, salloc_arb.io.in[5].valid) \n node _T_114 = and(_T_113, input_buffer.io.deq[5].bits.tail) \n when _T_114 : \n connect states[5].g, UInt<3>(0h0) \n connect input_buffer.io.deq[5].ready, salloc_arb.io.in[5].ready \n node credit_available_lo_lo_48 = cat(states[6].vc_sel.`0`[1], states[6].vc_sel.`0`[0]) \n node credit_available_lo_hi_48 = cat(states[6].vc_sel.`0`[3], states[6].vc_sel.`0`[2]) \n node credit_available_lo_60 = cat(credit_available_lo_hi_48, credit_available_lo_lo_48) \n node credit_available_hi_lo_48 = cat(states[6].vc_sel.`0`[5], states[6].vc_sel.`0`[4]) \n node credit_available_hi_hi_48 = cat(states[6].vc_sel.`0`[7], states[6].vc_sel.`0`[6]) \n node credit_available_hi_60 = cat(credit_available_hi_hi_48, credit_available_hi_lo_48) \n node _credit_available_T_66 = cat(credit_available_hi_60, credit_available_lo_60) \n node credit_available_lo_lo_49 = cat(states[6].vc_sel.`1`[1], states[6].vc_sel.`1`[0]) \n node credit_available_lo_hi_49 = cat(states[6].vc_sel.`1`[3], states[6].vc_sel.`1`[2]) \n node credit_available_lo_61 = cat(credit_available_lo_hi_49, credit_available_lo_lo_49) \n node credit_available_hi_lo_49 = cat(states[6].vc_sel.`1`[5], states[6].vc_sel.`1`[4]) \n node credit_available_hi_hi_49 = cat(states[6].vc_sel.`1`[7], states[6].vc_sel.`1`[6]) \n node credit_available_hi_61 = cat(credit_available_hi_hi_49, credit_available_hi_lo_49) \n node _credit_available_T_67 = cat(credit_available_hi_61, credit_available_lo_61) \n node credit_available_lo_lo_50 = cat(states[6].vc_sel.`2`[1], states[6].vc_sel.`2`[0]) \n node credit_available_lo_hi_50 = cat(states[6].vc_sel.`2`[3], states[6].vc_sel.`2`[2]) \n node credit_available_lo_62 = cat(credit_available_lo_hi_50, credit_available_lo_lo_50) \n node credit_available_hi_lo_50 = cat(states[6].vc_sel.`2`[5], states[6].vc_sel.`2`[4]) \n node credit_available_hi_hi_50 = cat(states[6].vc_sel.`2`[7], states[6].vc_sel.`2`[6]) \n node credit_available_hi_62 = cat(credit_available_hi_hi_50, credit_available_hi_lo_50) \n node _credit_available_T_68 = cat(credit_available_hi_62, credit_available_lo_62) \n node credit_available_lo_lo_51 = cat(states[6].vc_sel.`3`[1], states[6].vc_sel.`3`[0]) \n node credit_available_lo_hi_51 = cat(states[6].vc_sel.`3`[3], states[6].vc_sel.`3`[2]) \n node credit_available_lo_63 = cat(credit_available_lo_hi_51, credit_available_lo_lo_51) \n node credit_available_hi_lo_51 = cat(states[6].vc_sel.`3`[5], states[6].vc_sel.`3`[4]) \n node credit_available_hi_hi_51 = cat(states[6].vc_sel.`3`[7], states[6].vc_sel.`3`[6]) \n node credit_available_hi_63 = cat(credit_available_hi_hi_51, credit_available_hi_lo_51) \n node _credit_available_T_69 = cat(credit_available_hi_63, credit_available_lo_63) \n node credit_available_lo_64 = cat(_credit_available_T_67, _credit_available_T_66) \n node credit_available_hi_64 = cat(_credit_available_T_69, _credit_available_T_68) \n node _credit_available_T_70 = cat(credit_available_hi_64, credit_available_lo_64) \n node credit_available_lo_lo_52 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) \n node credit_available_lo_hi_52 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) \n node credit_available_lo_65 = cat(credit_available_lo_hi_52, credit_available_lo_lo_52) \n node credit_available_hi_lo_52 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) \n node credit_available_hi_hi_52 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) \n node credit_available_hi_65 = cat(credit_available_hi_hi_52, credit_available_hi_lo_52) \n node _credit_available_T_71 = cat(credit_available_hi_65, credit_available_lo_65) \n node credit_available_lo_lo_53 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) \n node credit_available_lo_hi_53 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) \n node credit_available_lo_66 = cat(credit_available_lo_hi_53, credit_available_lo_lo_53) \n node credit_available_hi_lo_53 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) \n node credit_available_hi_hi_53 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) \n node credit_available_hi_66 = cat(credit_available_hi_hi_53, credit_available_hi_lo_53) \n node _credit_available_T_72 = cat(credit_available_hi_66, credit_available_lo_66) \n node credit_available_lo_lo_54 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) \n node credit_available_lo_hi_54 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) \n node credit_available_lo_67 = cat(credit_available_lo_hi_54, credit_available_lo_lo_54) \n node credit_available_hi_lo_54 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) \n node credit_available_hi_hi_54 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) \n node credit_available_hi_67 = cat(credit_available_hi_hi_54, credit_available_hi_lo_54) \n node _credit_available_T_73 = cat(credit_available_hi_67, credit_available_lo_67) \n node credit_available_lo_lo_55 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) \n node credit_available_lo_hi_55 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) \n node credit_available_lo_68 = cat(credit_available_lo_hi_55, credit_available_lo_lo_55) \n node credit_available_hi_lo_55 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) \n node credit_available_hi_hi_55 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) \n node credit_available_hi_68 = cat(credit_available_hi_hi_55, credit_available_hi_lo_55) \n node _credit_available_T_74 = cat(credit_available_hi_68, credit_available_lo_68) \n node credit_available_lo_69 = cat(_credit_available_T_72, _credit_available_T_71) \n node credit_available_hi_69 = cat(_credit_available_T_74, _credit_available_T_73) \n node _credit_available_T_75 = cat(credit_available_hi_69, credit_available_lo_69) \n node _credit_available_T_76 = and(_credit_available_T_70, _credit_available_T_75) \n node credit_available_6 = neq(_credit_available_T_76, UInt<1>(0h0)) \n node _salloc_arb_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h3)) \n node _salloc_arb_io_in_6_valid_T_1 = and(_salloc_arb_io_in_6_valid_T, credit_available_6) \n node _salloc_arb_io_in_6_valid_T_2 = and(_salloc_arb_io_in_6_valid_T_1, input_buffer.io.deq[6].valid) \n connect salloc_arb.io.in[6].valid, _salloc_arb_io_in_6_valid_T_2 \n connect salloc_arb.io.in[6].bits.vc_sel.`0`[0], states[6].vc_sel.`0`[0] \n connect salloc_arb.io.in[6].bits.vc_sel.`0`[1], states[6].vc_sel.`0`[1] \n connect salloc_arb.io.in[6].bits.vc_sel.`0`[2], states[6].vc_sel.`0`[2] \n connect salloc_arb.io.in[6].bits.vc_sel.`0`[3], states[6].vc_sel.`0`[3] \n connect salloc_arb.io.in[6].bits.vc_sel.`0`[4], states[6].vc_sel.`0`[4] \n connect salloc_arb.io.in[6].bits.vc_sel.`0`[5], states[6].vc_sel.`0`[5] \n connect salloc_arb.io.in[6].bits.vc_sel.`0`[6], states[6].vc_sel.`0`[6] \n connect salloc_arb.io.in[6].bits.vc_sel.`0`[7], states[6].vc_sel.`0`[7] \n connect salloc_arb.io.in[6].bits.vc_sel.`1`[0], states[6].vc_sel.`1`[0] \n connect salloc_arb.io.in[6].bits.vc_sel.`1`[1], states[6].vc_sel.`1`[1] \n connect salloc_arb.io.in[6].bits.vc_sel.`1`[2], states[6].vc_sel.`1`[2] \n connect salloc_arb.io.in[6].bits.vc_sel.`1`[3], states[6].vc_sel.`1`[3] \n connect salloc_arb.io.in[6].bits.vc_sel.`1`[4], states[6].vc_sel.`1`[4] \n connect salloc_arb.io.in[6].bits.vc_sel.`1`[5], states[6].vc_sel.`1`[5] \n connect salloc_arb.io.in[6].bits.vc_sel.`1`[6], states[6].vc_sel.`1`[6] \n connect salloc_arb.io.in[6].bits.vc_sel.`1`[7], states[6].vc_sel.`1`[7] \n connect salloc_arb.io.in[6].bits.vc_sel.`2`[0], states[6].vc_sel.`2`[0] \n connect salloc_arb.io.in[6].bits.vc_sel.`2`[1], states[6].vc_sel.`2`[1] \n connect salloc_arb.io.in[6].bits.vc_sel.`2`[2], states[6].vc_sel.`2`[2] \n connect salloc_arb.io.in[6].bits.vc_sel.`2`[3], states[6].vc_sel.`2`[3] \n connect salloc_arb.io.in[6].bits.vc_sel.`2`[4], states[6].vc_sel.`2`[4] \n connect salloc_arb.io.in[6].bits.vc_sel.`2`[5], states[6].vc_sel.`2`[5] \n connect salloc_arb.io.in[6].bits.vc_sel.`2`[6], states[6].vc_sel.`2`[6] \n connect salloc_arb.io.in[6].bits.vc_sel.`2`[7], states[6].vc_sel.`2`[7] \n connect salloc_arb.io.in[6].bits.vc_sel.`3`[0], states[6].vc_sel.`3`[0] \n connect salloc_arb.io.in[6].bits.vc_sel.`3`[1], states[6].vc_sel.`3`[1] \n connect salloc_arb.io.in[6].bits.vc_sel.`3`[2], states[6].vc_sel.`3`[2] \n connect salloc_arb.io.in[6].bits.vc_sel.`3`[3], states[6].vc_sel.`3`[3] \n connect salloc_arb.io.in[6].bits.vc_sel.`3`[4], states[6].vc_sel.`3`[4] \n connect salloc_arb.io.in[6].bits.vc_sel.`3`[5], states[6].vc_sel.`3`[5] \n connect salloc_arb.io.in[6].bits.vc_sel.`3`[6], states[6].vc_sel.`3`[6] \n connect salloc_arb.io.in[6].bits.vc_sel.`3`[7], states[6].vc_sel.`3`[7] \n connect salloc_arb.io.in[6].bits.tail, input_buffer.io.deq[6].bits.tail \n node _T_115 = and(salloc_arb.io.in[6].ready, salloc_arb.io.in[6].valid) \n node _T_116 = and(_T_115, input_buffer.io.deq[6].bits.tail) \n when _T_116 : \n connect states[6].g, UInt<3>(0h0) \n connect input_buffer.io.deq[6].ready, salloc_arb.io.in[6].ready \n node credit_available_lo_lo_56 = cat(states[7].vc_sel.`0`[1], states[7].vc_sel.`0`[0]) \n node credit_available_lo_hi_56 = cat(states[7].vc_sel.`0`[3], states[7].vc_sel.`0`[2]) \n node credit_available_lo_70 = cat(credit_available_lo_hi_56, credit_available_lo_lo_56) \n node credit_available_hi_lo_56 = cat(states[7].vc_sel.`0`[5], states[7].vc_sel.`0`[4]) \n node credit_available_hi_hi_56 = cat(states[7].vc_sel.`0`[7], states[7].vc_sel.`0`[6]) \n node credit_available_hi_70 = cat(credit_available_hi_hi_56, credit_available_hi_lo_56) \n node _credit_available_T_77 = cat(credit_available_hi_70, credit_available_lo_70) \n node credit_available_lo_lo_57 = cat(states[7].vc_sel.`1`[1], states[7].vc_sel.`1`[0]) \n node credit_available_lo_hi_57 = cat(states[7].vc_sel.`1`[3], states[7].vc_sel.`1`[2]) \n node credit_available_lo_71 = cat(credit_available_lo_hi_57, credit_available_lo_lo_57) \n node credit_available_hi_lo_57 = cat(states[7].vc_sel.`1`[5], states[7].vc_sel.`1`[4]) \n node credit_available_hi_hi_57 = cat(states[7].vc_sel.`1`[7], states[7].vc_sel.`1`[6]) \n node credit_available_hi_71 = cat(credit_available_hi_hi_57, credit_available_hi_lo_57) \n node _credit_available_T_78 = cat(credit_available_hi_71, credit_available_lo_71) \n node credit_available_lo_lo_58 = cat(states[7].vc_sel.`2`[1], states[7].vc_sel.`2`[0]) \n node credit_available_lo_hi_58 = cat(states[7].vc_sel.`2`[3], states[7].vc_sel.`2`[2]) \n node credit_available_lo_72 = cat(credit_available_lo_hi_58, credit_available_lo_lo_58) \n node credit_available_hi_lo_58 = cat(states[7].vc_sel.`2`[5], states[7].vc_sel.`2`[4]) \n node credit_available_hi_hi_58 = cat(states[7].vc_sel.`2`[7], states[7].vc_sel.`2`[6]) \n node credit_available_hi_72 = cat(credit_available_hi_hi_58, credit_available_hi_lo_58) \n node _credit_available_T_79 = cat(credit_available_hi_72, credit_available_lo_72) \n node credit_available_lo_lo_59 = cat(states[7].vc_sel.`3`[1], states[7].vc_sel.`3`[0]) \n node credit_available_lo_hi_59 = cat(states[7].vc_sel.`3`[3], states[7].vc_sel.`3`[2]) \n node credit_available_lo_73 = cat(credit_available_lo_hi_59, credit_available_lo_lo_59) \n node credit_available_hi_lo_59 = cat(states[7].vc_sel.`3`[5], states[7].vc_sel.`3`[4]) \n node credit_available_hi_hi_59 = cat(states[7].vc_sel.`3`[7], states[7].vc_sel.`3`[6]) \n node credit_available_hi_73 = cat(credit_available_hi_hi_59, credit_available_hi_lo_59) \n node _credit_available_T_80 = cat(credit_available_hi_73, credit_available_lo_73) \n node credit_available_lo_74 = cat(_credit_available_T_78, _credit_available_T_77) \n node credit_available_hi_74 = cat(_credit_available_T_80, _credit_available_T_79) \n node _credit_available_T_81 = cat(credit_available_hi_74, credit_available_lo_74) \n node credit_available_lo_lo_60 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) \n node credit_available_lo_hi_60 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) \n node credit_available_lo_75 = cat(credit_available_lo_hi_60, credit_available_lo_lo_60) \n node credit_available_hi_lo_60 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) \n node credit_available_hi_hi_60 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) \n node credit_available_hi_75 = cat(credit_available_hi_hi_60, credit_available_hi_lo_60) \n node _credit_available_T_82 = cat(credit_available_hi_75, credit_available_lo_75) \n node credit_available_lo_lo_61 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) \n node credit_available_lo_hi_61 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) \n node credit_available_lo_76 = cat(credit_available_lo_hi_61, credit_available_lo_lo_61) \n node credit_available_hi_lo_61 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) \n node credit_available_hi_hi_61 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) \n node credit_available_hi_76 = cat(credit_available_hi_hi_61, credit_available_hi_lo_61) \n node _credit_available_T_83 = cat(credit_available_hi_76, credit_available_lo_76) \n node credit_available_lo_lo_62 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) \n node credit_available_lo_hi_62 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) \n node credit_available_lo_77 = cat(credit_available_lo_hi_62, credit_available_lo_lo_62) \n node credit_available_hi_lo_62 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) \n node credit_available_hi_hi_62 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) \n node credit_available_hi_77 = cat(credit_available_hi_hi_62, credit_available_hi_lo_62) \n node _credit_available_T_84 = cat(credit_available_hi_77, credit_available_lo_77) \n node credit_available_lo_lo_63 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) \n node credit_available_lo_hi_63 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) \n node credit_available_lo_78 = cat(credit_available_lo_hi_63, credit_available_lo_lo_63) \n node credit_available_hi_lo_63 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) \n node credit_available_hi_hi_63 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) \n node credit_available_hi_78 = cat(credit_available_hi_hi_63, credit_available_hi_lo_63) \n node _credit_available_T_85 = cat(credit_available_hi_78, credit_available_lo_78) \n node credit_available_lo_79 = cat(_credit_available_T_83, _credit_available_T_82) \n node credit_available_hi_79 = cat(_credit_available_T_85, _credit_available_T_84) \n node _credit_available_T_86 = cat(credit_available_hi_79, credit_available_lo_79) \n node _credit_available_T_87 = and(_credit_available_T_81, _credit_available_T_86) \n node credit_available_7 = neq(_credit_available_T_87, UInt<1>(0h0)) \n node _salloc_arb_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h3)) \n node _salloc_arb_io_in_7_valid_T_1 = and(_salloc_arb_io_in_7_valid_T, credit_available_7) \n node _salloc_arb_io_in_7_valid_T_2 = and(_salloc_arb_io_in_7_valid_T_1, input_buffer.io.deq[7].valid) \n connect salloc_arb.io.in[7].valid, _salloc_arb_io_in_7_valid_T_2 \n connect salloc_arb.io.in[7].bits.vc_sel.`0`[0], states[7].vc_sel.`0`[0] \n connect salloc_arb.io.in[7].bits.vc_sel.`0`[1], states[7].vc_sel.`0`[1] \n connect salloc_arb.io.in[7].bits.vc_sel.`0`[2], states[7].vc_sel.`0`[2] \n connect salloc_arb.io.in[7].bits.vc_sel.`0`[3], states[7].vc_sel.`0`[3] \n connect salloc_arb.io.in[7].bits.vc_sel.`0`[4], states[7].vc_sel.`0`[4] \n connect salloc_arb.io.in[7].bits.vc_sel.`0`[5], states[7].vc_sel.`0`[5] \n connect salloc_arb.io.in[7].bits.vc_sel.`0`[6], states[7].vc_sel.`0`[6] \n connect salloc_arb.io.in[7].bits.vc_sel.`0`[7], states[7].vc_sel.`0`[7] \n connect salloc_arb.io.in[7].bits.vc_sel.`1`[0], states[7].vc_sel.`1`[0] \n connect salloc_arb.io.in[7].bits.vc_sel.`1`[1], states[7].vc_sel.`1`[1] \n connect salloc_arb.io.in[7].bits.vc_sel.`1`[2], states[7].vc_sel.`1`[2] \n connect salloc_arb.io.in[7].bits.vc_sel.`1`[3], states[7].vc_sel.`1`[3] \n connect salloc_arb.io.in[7].bits.vc_sel.`1`[4], states[7].vc_sel.`1`[4] \n connect salloc_arb.io.in[7].bits.vc_sel.`1`[5], states[7].vc_sel.`1`[5] \n connect salloc_arb.io.in[7].bits.vc_sel.`1`[6], states[7].vc_sel.`1`[6] \n connect salloc_arb.io.in[7].bits.vc_sel.`1`[7], states[7].vc_sel.`1`[7] \n connect salloc_arb.io.in[7].bits.vc_sel.`2`[0], states[7].vc_sel.`2`[0] \n connect salloc_arb.io.in[7].bits.vc_sel.`2`[1], states[7].vc_sel.`2`[1] \n connect salloc_arb.io.in[7].bits.vc_sel.`2`[2], states[7].vc_sel.`2`[2] \n connect salloc_arb.io.in[7].bits.vc_sel.`2`[3], states[7].vc_sel.`2`[3] \n connect salloc_arb.io.in[7].bits.vc_sel.`2`[4], states[7].vc_sel.`2`[4] \n connect salloc_arb.io.in[7].bits.vc_sel.`2`[5], states[7].vc_sel.`2`[5] \n connect salloc_arb.io.in[7].bits.vc_sel.`2`[6], states[7].vc_sel.`2`[6] \n connect salloc_arb.io.in[7].bits.vc_sel.`2`[7], states[7].vc_sel.`2`[7] \n connect salloc_arb.io.in[7].bits.vc_sel.`3`[0], states[7].vc_sel.`3`[0] \n connect salloc_arb.io.in[7].bits.vc_sel.`3`[1], states[7].vc_sel.`3`[1] \n connect salloc_arb.io.in[7].bits.vc_sel.`3`[2], states[7].vc_sel.`3`[2] \n connect salloc_arb.io.in[7].bits.vc_sel.`3`[3], states[7].vc_sel.`3`[3] \n connect salloc_arb.io.in[7].bits.vc_sel.`3`[4], states[7].vc_sel.`3`[4] \n connect salloc_arb.io.in[7].bits.vc_sel.`3`[5], states[7].vc_sel.`3`[5] \n connect salloc_arb.io.in[7].bits.vc_sel.`3`[6], states[7].vc_sel.`3`[6] \n connect salloc_arb.io.in[7].bits.vc_sel.`3`[7], states[7].vc_sel.`3`[7] \n connect salloc_arb.io.in[7].bits.tail, input_buffer.io.deq[7].bits.tail \n node _T_117 = and(salloc_arb.io.in[7].ready, salloc_arb.io.in[7].valid) \n node _T_118 = and(_T_117, input_buffer.io.deq[7].bits.tail) \n when _T_118 : \n connect states[7].g, UInt<3>(0h0) \n connect input_buffer.io.deq[7].ready, salloc_arb.io.in[7].ready \n node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) \n node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) \n node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) \n node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) \n node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0)) \n node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4) \n node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0)) \n node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6) \n node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0)) \n node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8) \n node _io_debug_sa_stall_T_10 = eq(salloc_arb.io.in[5].ready, UInt<1>(0h0)) \n node _io_debug_sa_stall_T_11 = and(salloc_arb.io.in[5].valid, _io_debug_sa_stall_T_10) \n node _io_debug_sa_stall_T_12 = eq(salloc_arb.io.in[6].ready, UInt<1>(0h0)) \n node _io_debug_sa_stall_T_13 = and(salloc_arb.io.in[6].valid, _io_debug_sa_stall_T_12) \n node _io_debug_sa_stall_T_14 = eq(salloc_arb.io.in[7].ready, UInt<1>(0h0)) \n node _io_debug_sa_stall_T_15 = and(salloc_arb.io.in[7].valid, _io_debug_sa_stall_T_14) \n node _io_debug_sa_stall_T_16 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3) \n node _io_debug_sa_stall_T_17 = bits(_io_debug_sa_stall_T_16, 1, 0) \n node _io_debug_sa_stall_T_18 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_7) \n node _io_debug_sa_stall_T_19 = bits(_io_debug_sa_stall_T_18, 1, 0) \n node _io_debug_sa_stall_T_20 = add(_io_debug_sa_stall_T_17, _io_debug_sa_stall_T_19) \n node _io_debug_sa_stall_T_21 = bits(_io_debug_sa_stall_T_20, 2, 0) \n node _io_debug_sa_stall_T_22 = add(_io_debug_sa_stall_T_9, _io_debug_sa_stall_T_11) \n node _io_debug_sa_stall_T_23 = bits(_io_debug_sa_stall_T_22, 1, 0) \n node _io_debug_sa_stall_T_24 = add(_io_debug_sa_stall_T_13, _io_debug_sa_stall_T_15) \n node _io_debug_sa_stall_T_25 = bits(_io_debug_sa_stall_T_24, 1, 0) \n node _io_debug_sa_stall_T_26 = add(_io_debug_sa_stall_T_23, _io_debug_sa_stall_T_25) \n node _io_debug_sa_stall_T_27 = bits(_io_debug_sa_stall_T_26, 2, 0) \n node _io_debug_sa_stall_T_28 = add(_io_debug_sa_stall_T_21, _io_debug_sa_stall_T_27) \n node _io_debug_sa_stall_T_29 = bits(_io_debug_sa_stall_T_28, 3, 0) \n connect io.debug.sa_stall, _io_debug_sa_stall_T_29 \n connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits \n connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid \n connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready \n when io.block : \n connect salloc_arb.io.out[0].ready, UInt<1>(0h0) \n connect io.salloc_req[0].valid, UInt<1>(0h0) \n reg salloc_outs : { valid : UInt<1>, vid : UInt<3>, out_vid : UInt<3>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], clock \n node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) \n node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) \n connect io.in.credit_return, _io_in_credit_return_T_1 \n node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) \n node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) \n node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) \n node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2) \n node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3) \n node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4) \n node _io_in_vc_free_T_6 = bits(salloc_arb.io.chosen_oh[0], 5, 5) \n node _io_in_vc_free_T_7 = bits(salloc_arb.io.chosen_oh[0], 6, 6) \n node _io_in_vc_free_T_8 = bits(salloc_arb.io.chosen_oh[0], 7, 7) \n node _io_in_vc_free_T_9 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) \n node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) \n node _io_in_vc_free_T_11 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) \n node _io_in_vc_free_T_12 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) \n node _io_in_vc_free_T_13 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) \n node _io_in_vc_free_T_14 = mux(_io_in_vc_free_T_6, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) \n node _io_in_vc_free_T_15 = mux(_io_in_vc_free_T_7, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0)) \n node _io_in_vc_free_T_16 = mux(_io_in_vc_free_T_8, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0)) \n node _io_in_vc_free_T_17 = or(_io_in_vc_free_T_9, _io_in_vc_free_T_10) \n node _io_in_vc_free_T_18 = or(_io_in_vc_free_T_17, _io_in_vc_free_T_11) \n node _io_in_vc_free_T_19 = or(_io_in_vc_free_T_18, _io_in_vc_free_T_12) \n node _io_in_vc_free_T_20 = or(_io_in_vc_free_T_19, _io_in_vc_free_T_13) \n node _io_in_vc_free_T_21 = or(_io_in_vc_free_T_20, _io_in_vc_free_T_14) \n node _io_in_vc_free_T_22 = or(_io_in_vc_free_T_21, _io_in_vc_free_T_15) \n node _io_in_vc_free_T_23 = or(_io_in_vc_free_T_22, _io_in_vc_free_T_16) \n wire _io_in_vc_free_WIRE : UInt<1> \n connect _io_in_vc_free_WIRE, _io_in_vc_free_T_23 \n node _io_in_vc_free_T_24 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) \n node _io_in_vc_free_T_25 = mux(_io_in_vc_free_T_24, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) \n connect io.in.vc_free, _io_in_vc_free_T_25 \n node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) \n connect salloc_outs[0].valid, _salloc_outs_0_valid_T \n node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 7, 4) \n node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 3, 0) \n node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi) \n node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo) \n node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 3, 2) \n node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 1, 0) \n node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1) \n node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1) \n node _salloc_outs_0_vid_T_4 = bits(_salloc_outs_0_vid_T_3, 1, 1) \n node _salloc_outs_0_vid_T_5 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_4) \n node _salloc_outs_0_vid_T_6 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_5) \n connect salloc_outs[0].vid, _salloc_outs_0_vid_T_6 \n node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) \n node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) \n node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) \n node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) \n node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) \n node _vc_sel_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) \n node _vc_sel_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) \n node _vc_sel_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) \n wire vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]} \n wire _vc_sel_WIRE : UInt<1>[8] \n node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) \n node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) \n node _vc_sel_T_10 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0)) \n node _vc_sel_T_11 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0)) \n node _vc_sel_T_12 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0)) \n node _vc_sel_T_13 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[0], UInt<1>(0h0)) \n node _vc_sel_T_14 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[0], UInt<1>(0h0)) \n node _vc_sel_T_15 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[0], UInt<1>(0h0)) \n node _vc_sel_T_16 = or(_vc_sel_T_8, _vc_sel_T_9) \n node _vc_sel_T_17 = or(_vc_sel_T_16, _vc_sel_T_10) \n node _vc_sel_T_18 = or(_vc_sel_T_17, _vc_sel_T_11) \n node _vc_sel_T_19 = or(_vc_sel_T_18, _vc_sel_T_12) \n node _vc_sel_T_20 = or(_vc_sel_T_19, _vc_sel_T_13) \n node _vc_sel_T_21 = or(_vc_sel_T_20, _vc_sel_T_14) \n node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_15) \n wire _vc_sel_WIRE_1 : UInt<1> \n connect _vc_sel_WIRE_1, _vc_sel_T_22 \n connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 \n node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) \n node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) \n node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0)) \n node _vc_sel_T_26 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0)) \n node _vc_sel_T_27 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0)) \n node _vc_sel_T_28 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[1], UInt<1>(0h0)) \n node _vc_sel_T_29 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[1], UInt<1>(0h0)) \n node _vc_sel_T_30 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[1], UInt<1>(0h0)) \n node _vc_sel_T_31 = or(_vc_sel_T_23, _vc_sel_T_24) \n node _vc_sel_T_32 = or(_vc_sel_T_31, _vc_sel_T_25) \n node _vc_sel_T_33 = or(_vc_sel_T_32, _vc_sel_T_26) \n node _vc_sel_T_34 = or(_vc_sel_T_33, _vc_sel_T_27) \n node _vc_sel_T_35 = or(_vc_sel_T_34, _vc_sel_T_28) \n node _vc_sel_T_36 = or(_vc_sel_T_35, _vc_sel_T_29) \n node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_30) \n wire _vc_sel_WIRE_2 : UInt<1> \n connect _vc_sel_WIRE_2, _vc_sel_T_37 \n connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 \n node _vc_sel_T_38 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0)) \n node _vc_sel_T_39 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0)) \n node _vc_sel_T_40 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0)) \n node _vc_sel_T_41 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0)) \n node _vc_sel_T_42 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0)) \n node _vc_sel_T_43 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[2], UInt<1>(0h0)) \n node _vc_sel_T_44 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[2], UInt<1>(0h0)) \n node _vc_sel_T_45 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[2], UInt<1>(0h0)) \n node _vc_sel_T_46 = or(_vc_sel_T_38, _vc_sel_T_39) \n node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_40) \n node _vc_sel_T_48 = or(_vc_sel_T_47, _vc_sel_T_41) \n node _vc_sel_T_49 = or(_vc_sel_T_48, _vc_sel_T_42) \n node _vc_sel_T_50 = or(_vc_sel_T_49, _vc_sel_T_43) \n node _vc_sel_T_51 = or(_vc_sel_T_50, _vc_sel_T_44) \n node _vc_sel_T_52 = or(_vc_sel_T_51, _vc_sel_T_45) \n wire _vc_sel_WIRE_3 : UInt<1> \n connect _vc_sel_WIRE_3, _vc_sel_T_52 \n connect _vc_sel_WIRE[2], _vc_sel_WIRE_3 \n node _vc_sel_T_53 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0)) \n node _vc_sel_T_54 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0)) \n node _vc_sel_T_55 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0)) \n node _vc_sel_T_56 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0)) \n node _vc_sel_T_57 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0)) \n node _vc_sel_T_58 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[3], UInt<1>(0h0)) \n node _vc_sel_T_59 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[3], UInt<1>(0h0)) \n node _vc_sel_T_60 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[3], UInt<1>(0h0)) \n node _vc_sel_T_61 = or(_vc_sel_T_53, _vc_sel_T_54) \n node _vc_sel_T_62 = or(_vc_sel_T_61, _vc_sel_T_55) \n node _vc_sel_T_63 = or(_vc_sel_T_62, _vc_sel_T_56) \n node _vc_sel_T_64 = or(_vc_sel_T_63, _vc_sel_T_57) \n node _vc_sel_T_65 = or(_vc_sel_T_64, _vc_sel_T_58) \n node _vc_sel_T_66 = or(_vc_sel_T_65, _vc_sel_T_59) \n node _vc_sel_T_67 = or(_vc_sel_T_66, _vc_sel_T_60) \n wire _vc_sel_WIRE_4 : UInt<1> \n connect _vc_sel_WIRE_4, _vc_sel_T_67 \n connect _vc_sel_WIRE[3], _vc_sel_WIRE_4 \n node _vc_sel_T_68 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0)) \n node _vc_sel_T_69 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0)) \n node _vc_sel_T_70 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0)) \n node _vc_sel_T_71 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0)) \n node _vc_sel_T_72 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0)) \n node _vc_sel_T_73 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[4], UInt<1>(0h0)) \n node _vc_sel_T_74 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[4], UInt<1>(0h0)) \n node _vc_sel_T_75 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[4], UInt<1>(0h0)) \n node _vc_sel_T_76 = or(_vc_sel_T_68, _vc_sel_T_69) \n node _vc_sel_T_77 = or(_vc_sel_T_76, _vc_sel_T_70) \n node _vc_sel_T_78 = or(_vc_sel_T_77, _vc_sel_T_71) \n node _vc_sel_T_79 = or(_vc_sel_T_78, _vc_sel_T_72) \n node _vc_sel_T_80 = or(_vc_sel_T_79, _vc_sel_T_73) \n node _vc_sel_T_81 = or(_vc_sel_T_80, _vc_sel_T_74) \n node _vc_sel_T_82 = or(_vc_sel_T_81, _vc_sel_T_75) \n wire _vc_sel_WIRE_5 : UInt<1> \n connect _vc_sel_WIRE_5, _vc_sel_T_82 \n connect _vc_sel_WIRE[4], _vc_sel_WIRE_5 \n node _vc_sel_T_83 = mux(_vc_sel_T, states[0].vc_sel.`0`[5], UInt<1>(0h0)) \n node _vc_sel_T_84 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[5], UInt<1>(0h0)) \n node _vc_sel_T_85 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[5], UInt<1>(0h0)) \n node _vc_sel_T_86 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[5], UInt<1>(0h0)) \n node _vc_sel_T_87 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[5], UInt<1>(0h0)) \n node _vc_sel_T_88 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[5], UInt<1>(0h0)) \n node _vc_sel_T_89 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[5], UInt<1>(0h0)) \n node _vc_sel_T_90 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[5], UInt<1>(0h0)) \n node _vc_sel_T_91 = or(_vc_sel_T_83, _vc_sel_T_84) \n node _vc_sel_T_92 = or(_vc_sel_T_91, _vc_sel_T_85) \n node _vc_sel_T_93 = or(_vc_sel_T_92, _vc_sel_T_86) \n node _vc_sel_T_94 = or(_vc_sel_T_93, _vc_sel_T_87) \n node _vc_sel_T_95 = or(_vc_sel_T_94, _vc_sel_T_88) \n node _vc_sel_T_96 = or(_vc_sel_T_95, _vc_sel_T_89) \n node _vc_sel_T_97 = or(_vc_sel_T_96, _vc_sel_T_90) \n wire _vc_sel_WIRE_6 : UInt<1> \n connect _vc_sel_WIRE_6, _vc_sel_T_97 \n connect _vc_sel_WIRE[5], _vc_sel_WIRE_6 \n node _vc_sel_T_98 = mux(_vc_sel_T, states[0].vc_sel.`0`[6], UInt<1>(0h0)) \n node _vc_sel_T_99 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[6], UInt<1>(0h0)) \n node _vc_sel_T_100 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[6], UInt<1>(0h0)) \n node _vc_sel_T_101 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[6], UInt<1>(0h0)) \n node _vc_sel_T_102 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[6], UInt<1>(0h0)) \n node _vc_sel_T_103 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[6], UInt<1>(0h0)) \n node _vc_sel_T_104 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[6], UInt<1>(0h0)) \n node _vc_sel_T_105 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[6], UInt<1>(0h0)) \n node _vc_sel_T_106 = or(_vc_sel_T_98, _vc_sel_T_99) \n node _vc_sel_T_107 = or(_vc_sel_T_106, _vc_sel_T_100) \n node _vc_sel_T_108 = or(_vc_sel_T_107, _vc_sel_T_101) \n node _vc_sel_T_109 = or(_vc_sel_T_108, _vc_sel_T_102) \n node _vc_sel_T_110 = or(_vc_sel_T_109, _vc_sel_T_103) \n node _vc_sel_T_111 = or(_vc_sel_T_110, _vc_sel_T_104) \n node _vc_sel_T_112 = or(_vc_sel_T_111, _vc_sel_T_105) \n wire _vc_sel_WIRE_7 : UInt<1> \n connect _vc_sel_WIRE_7, _vc_sel_T_112 \n connect _vc_sel_WIRE[6], _vc_sel_WIRE_7 \n node _vc_sel_T_113 = mux(_vc_sel_T, states[0].vc_sel.`0`[7], UInt<1>(0h0)) \n node _vc_sel_T_114 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[7], UInt<1>(0h0)) \n node _vc_sel_T_115 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[7], UInt<1>(0h0)) \n node _vc_sel_T_116 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[7], UInt<1>(0h0)) \n node _vc_sel_T_117 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[7], UInt<1>(0h0)) \n node _vc_sel_T_118 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[7], UInt<1>(0h0)) \n node _vc_sel_T_119 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[7], UInt<1>(0h0)) \n node _vc_sel_T_120 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[7], UInt<1>(0h0)) \n node _vc_sel_T_121 = or(_vc_sel_T_113, _vc_sel_T_114) \n node _vc_sel_T_122 = or(_vc_sel_T_121, _vc_sel_T_115) \n node _vc_sel_T_123 = or(_vc_sel_T_122, _vc_sel_T_116) \n node _vc_sel_T_124 = or(_vc_sel_T_123, _vc_sel_T_117) \n node _vc_sel_T_125 = or(_vc_sel_T_124, _vc_sel_T_118) \n node _vc_sel_T_126 = or(_vc_sel_T_125, _vc_sel_T_119) \n node _vc_sel_T_127 = or(_vc_sel_T_126, _vc_sel_T_120) \n wire _vc_sel_WIRE_8 : UInt<1> \n connect _vc_sel_WIRE_8, _vc_sel_T_127 \n connect _vc_sel_WIRE[7], _vc_sel_WIRE_8 \n connect vc_sel.`0`, _vc_sel_WIRE \n wire _vc_sel_WIRE_9 : UInt<1>[8] \n node _vc_sel_T_128 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) \n node _vc_sel_T_129 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) \n node _vc_sel_T_130 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0)) \n node _vc_sel_T_131 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0)) \n node _vc_sel_T_132 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0)) \n node _vc_sel_T_133 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[0], UInt<1>(0h0)) \n node _vc_sel_T_134 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[0], UInt<1>(0h0)) \n node _vc_sel_T_135 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[0], UInt<1>(0h0)) \n node _vc_sel_T_136 = or(_vc_sel_T_128, _vc_sel_T_129) \n node _vc_sel_T_137 = or(_vc_sel_T_136, _vc_sel_T_130) \n node _vc_sel_T_138 = or(_vc_sel_T_137, _vc_sel_T_131) \n node _vc_sel_T_139 = or(_vc_sel_T_138, _vc_sel_T_132) \n node _vc_sel_T_140 = or(_vc_sel_T_139, _vc_sel_T_133) \n node _vc_sel_T_141 = or(_vc_sel_T_140, _vc_sel_T_134) \n node _vc_sel_T_142 = or(_vc_sel_T_141, _vc_sel_T_135) \n wire _vc_sel_WIRE_10 : UInt<1> \n connect _vc_sel_WIRE_10, _vc_sel_T_142 \n connect _vc_sel_WIRE_9[0], _vc_sel_WIRE_10 \n node _vc_sel_T_143 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0)) \n node _vc_sel_T_144 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0)) \n node _vc_sel_T_145 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0)) \n node _vc_sel_T_146 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[1], UInt<1>(0h0)) \n node _vc_sel_T_147 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[1], UInt<1>(0h0)) \n node _vc_sel_T_148 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[1], UInt<1>(0h0)) \n node _vc_sel_T_149 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[1], UInt<1>(0h0)) \n node _vc_sel_T_150 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[1], UInt<1>(0h0)) \n node _vc_sel_T_151 = or(_vc_sel_T_143, _vc_sel_T_144) \n node _vc_sel_T_152 = or(_vc_sel_T_151, _vc_sel_T_145) \n node _vc_sel_T_153 = or(_vc_sel_T_152, _vc_sel_T_146) \n node _vc_sel_T_154 = or(_vc_sel_T_153, _vc_sel_T_147) \n node _vc_sel_T_155 = or(_vc_sel_T_154, _vc_sel_T_148) \n node _vc_sel_T_156 = or(_vc_sel_T_155, _vc_sel_T_149) \n node _vc_sel_T_157 = or(_vc_sel_T_156, _vc_sel_T_150) \n wire _vc_sel_WIRE_11 : UInt<1> \n connect _vc_sel_WIRE_11, _vc_sel_T_157 \n connect _vc_sel_WIRE_9[1], _vc_sel_WIRE_11 \n node _vc_sel_T_158 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0)) \n node _vc_sel_T_159 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0)) \n node _vc_sel_T_160 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0)) \n node _vc_sel_T_161 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[2], UInt<1>(0h0)) \n node _vc_sel_T_162 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[2], UInt<1>(0h0)) \n node _vc_sel_T_163 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[2], UInt<1>(0h0)) \n node _vc_sel_T_164 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[2], UInt<1>(0h0)) \n node _vc_sel_T_165 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[2], UInt<1>(0h0)) \n node _vc_sel_T_166 = or(_vc_sel_T_158, _vc_sel_T_159) \n node _vc_sel_T_167 = or(_vc_sel_T_166, _vc_sel_T_160) \n node _vc_sel_T_168 = or(_vc_sel_T_167, _vc_sel_T_161) \n node _vc_sel_T_169 = or(_vc_sel_T_168, _vc_sel_T_162) \n node _vc_sel_T_170 = or(_vc_sel_T_169, _vc_sel_T_163) \n node _vc_sel_T_171 = or(_vc_sel_T_170, _vc_sel_T_164) \n node _vc_sel_T_172 = or(_vc_sel_T_171, _vc_sel_T_165) \n wire _vc_sel_WIRE_12 : UInt<1> \n connect _vc_sel_WIRE_12, _vc_sel_T_172 \n connect _vc_sel_WIRE_9[2], _vc_sel_WIRE_12 \n node _vc_sel_T_173 = mux(_vc_sel_T, states[0].vc_sel.`1`[3], UInt<1>(0h0)) \n node _vc_sel_T_174 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[3], UInt<1>(0h0)) \n node _vc_sel_T_175 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[3], UInt<1>(0h0)) \n node _vc_sel_T_176 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[3], UInt<1>(0h0)) \n node _vc_sel_T_177 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[3], UInt<1>(0h0)) \n node _vc_sel_T_178 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[3], UInt<1>(0h0)) \n node _vc_sel_T_179 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[3], UInt<1>(0h0)) \n node _vc_sel_T_180 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[3], UInt<1>(0h0)) \n node _vc_sel_T_181 = or(_vc_sel_T_173, _vc_sel_T_174) \n node _vc_sel_T_182 = or(_vc_sel_T_181, _vc_sel_T_175) \n node _vc_sel_T_183 = or(_vc_sel_T_182, _vc_sel_T_176) \n node _vc_sel_T_184 = or(_vc_sel_T_183, _vc_sel_T_177) \n node _vc_sel_T_185 = or(_vc_sel_T_184, _vc_sel_T_178) \n node _vc_sel_T_186 = or(_vc_sel_T_185, _vc_sel_T_179) \n node _vc_sel_T_187 = or(_vc_sel_T_186, _vc_sel_T_180) \n wire _vc_sel_WIRE_13 : UInt<1> \n connect _vc_sel_WIRE_13, _vc_sel_T_187 \n connect _vc_sel_WIRE_9[3], _vc_sel_WIRE_13 \n node _vc_sel_T_188 = mux(_vc_sel_T, states[0].vc_sel.`1`[4], UInt<1>(0h0)) \n node _vc_sel_T_189 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[4], UInt<1>(0h0)) \n node _vc_sel_T_190 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[4], UInt<1>(0h0)) \n node _vc_sel_T_191 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[4], UInt<1>(0h0)) \n node _vc_sel_T_192 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[4], UInt<1>(0h0)) \n node _vc_sel_T_193 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[4], UInt<1>(0h0)) \n node _vc_sel_T_194 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[4], UInt<1>(0h0)) \n node _vc_sel_T_195 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[4], UInt<1>(0h0)) \n node _vc_sel_T_196 = or(_vc_sel_T_188, _vc_sel_T_189) \n node _vc_sel_T_197 = or(_vc_sel_T_196, _vc_sel_T_190) \n node _vc_sel_T_198 = or(_vc_sel_T_197, _vc_sel_T_191) \n node _vc_sel_T_199 = or(_vc_sel_T_198, _vc_sel_T_192) \n node _vc_sel_T_200 = or(_vc_sel_T_199, _vc_sel_T_193) \n node _vc_sel_T_201 = or(_vc_sel_T_200, _vc_sel_T_194) \n node _vc_sel_T_202 = or(_vc_sel_T_201, _vc_sel_T_195) \n wire _vc_sel_WIRE_14 : UInt<1> \n connect _vc_sel_WIRE_14, _vc_sel_T_202 \n connect _vc_sel_WIRE_9[4], _vc_sel_WIRE_14 \n node _vc_sel_T_203 = mux(_vc_sel_T, states[0].vc_sel.`1`[5], UInt<1>(0h0)) \n node _vc_sel_T_204 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[5], UInt<1>(0h0)) \n node _vc_sel_T_205 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[5], UInt<1>(0h0)) \n node _vc_sel_T_206 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[5], UInt<1>(0h0)) \n node _vc_sel_T_207 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[5], UInt<1>(0h0)) \n node _vc_sel_T_208 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[5], UInt<1>(0h0)) \n node _vc_sel_T_209 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[5], UInt<1>(0h0)) \n node _vc_sel_T_210 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[5], UInt<1>(0h0)) \n node _vc_sel_T_211 = or(_vc_sel_T_203, _vc_sel_T_204) \n node _vc_sel_T_212 = or(_vc_sel_T_211, _vc_sel_T_205) \n node _vc_sel_T_213 = or(_vc_sel_T_212, _vc_sel_T_206) \n node _vc_sel_T_214 = or(_vc_sel_T_213, _vc_sel_T_207) \n node _vc_sel_T_215 = or(_vc_sel_T_214, _vc_sel_T_208) \n node _vc_sel_T_216 = or(_vc_sel_T_215, _vc_sel_T_209) \n node _vc_sel_T_217 = or(_vc_sel_T_216, _vc_sel_T_210) \n wire _vc_sel_WIRE_15 : UInt<1> \n connect _vc_sel_WIRE_15, _vc_sel_T_217 \n connect _vc_sel_WIRE_9[5], _vc_sel_WIRE_15 \n node _vc_sel_T_218 = mux(_vc_sel_T, states[0].vc_sel.`1`[6], UInt<1>(0h0)) \n node _vc_sel_T_219 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[6], UInt<1>(0h0)) \n node _vc_sel_T_220 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[6], UInt<1>(0h0)) \n node _vc_sel_T_221 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[6], UInt<1>(0h0)) \n node _vc_sel_T_222 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[6], UInt<1>(0h0)) \n node _vc_sel_T_223 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[6], UInt<1>(0h0)) \n node _vc_sel_T_224 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[6], UInt<1>(0h0)) \n node _vc_sel_T_225 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[6], UInt<1>(0h0)) \n node _vc_sel_T_226 = or(_vc_sel_T_218, _vc_sel_T_219) \n node _vc_sel_T_227 = or(_vc_sel_T_226, _vc_sel_T_220) \n node _vc_sel_T_228 = or(_vc_sel_T_227, _vc_sel_T_221) \n node _vc_sel_T_229 = or(_vc_sel_T_228, _vc_sel_T_222) \n node _vc_sel_T_230 = or(_vc_sel_T_229, _vc_sel_T_223) \n node _vc_sel_T_231 = or(_vc_sel_T_230, _vc_sel_T_224) \n node _vc_sel_T_232 = or(_vc_sel_T_231, _vc_sel_T_225) \n wire _vc_sel_WIRE_16 : UInt<1> \n connect _vc_sel_WIRE_16, _vc_sel_T_232 \n connect _vc_sel_WIRE_9[6], _vc_sel_WIRE_16 \n node _vc_sel_T_233 = mux(_vc_sel_T, states[0].vc_sel.`1`[7], UInt<1>(0h0)) \n node _vc_sel_T_234 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[7], UInt<1>(0h0)) \n node _vc_sel_T_235 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[7], UInt<1>(0h0)) \n node _vc_sel_T_236 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[7], UInt<1>(0h0)) \n node _vc_sel_T_237 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[7], UInt<1>(0h0)) \n node _vc_sel_T_238 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[7], UInt<1>(0h0)) \n node _vc_sel_T_239 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[7], UInt<1>(0h0)) \n node _vc_sel_T_240 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[7], UInt<1>(0h0)) \n node _vc_sel_T_241 = or(_vc_sel_T_233, _vc_sel_T_234) \n node _vc_sel_T_242 = or(_vc_sel_T_241, _vc_sel_T_235) \n node _vc_sel_T_243 = or(_vc_sel_T_242, _vc_sel_T_236) \n node _vc_sel_T_244 = or(_vc_sel_T_243, _vc_sel_T_237) \n node _vc_sel_T_245 = or(_vc_sel_T_244, _vc_sel_T_238) \n node _vc_sel_T_246 = or(_vc_sel_T_245, _vc_sel_T_239) \n node _vc_sel_T_247 = or(_vc_sel_T_246, _vc_sel_T_240) \n wire _vc_sel_WIRE_17 : UInt<1> \n connect _vc_sel_WIRE_17, _vc_sel_T_247 \n connect _vc_sel_WIRE_9[7], _vc_sel_WIRE_17 \n connect vc_sel.`1`, _vc_sel_WIRE_9 \n wire _vc_sel_WIRE_18 : UInt<1>[8] \n node _vc_sel_T_248 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0)) \n node _vc_sel_T_249 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0)) \n node _vc_sel_T_250 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0)) \n node _vc_sel_T_251 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[0], UInt<1>(0h0)) \n node _vc_sel_T_252 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[0], UInt<1>(0h0)) \n node _vc_sel_T_253 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[0], UInt<1>(0h0)) \n node _vc_sel_T_254 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[0], UInt<1>(0h0)) \n node _vc_sel_T_255 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[0], UInt<1>(0h0)) \n node _vc_sel_T_256 = or(_vc_sel_T_248, _vc_sel_T_249) \n node _vc_sel_T_257 = or(_vc_sel_T_256, _vc_sel_T_250) \n node _vc_sel_T_258 = or(_vc_sel_T_257, _vc_sel_T_251) \n node _vc_sel_T_259 = or(_vc_sel_T_258, _vc_sel_T_252) \n node _vc_sel_T_260 = or(_vc_sel_T_259, _vc_sel_T_253) \n node _vc_sel_T_261 = or(_vc_sel_T_260, _vc_sel_T_254) \n node _vc_sel_T_262 = or(_vc_sel_T_261, _vc_sel_T_255) \n wire _vc_sel_WIRE_19 : UInt<1> \n connect _vc_sel_WIRE_19, _vc_sel_T_262 \n connect _vc_sel_WIRE_18[0], _vc_sel_WIRE_19 \n node _vc_sel_T_263 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0)) \n node _vc_sel_T_264 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0)) \n node _vc_sel_T_265 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[1], UInt<1>(0h0)) \n node _vc_sel_T_266 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[1], UInt<1>(0h0)) \n node _vc_sel_T_267 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[1], UInt<1>(0h0)) \n node _vc_sel_T_268 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[1], UInt<1>(0h0)) \n node _vc_sel_T_269 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[1], UInt<1>(0h0)) \n node _vc_sel_T_270 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[1], UInt<1>(0h0)) \n node _vc_sel_T_271 = or(_vc_sel_T_263, _vc_sel_T_264) \n node _vc_sel_T_272 = or(_vc_sel_T_271, _vc_sel_T_265) \n node _vc_sel_T_273 = or(_vc_sel_T_272, _vc_sel_T_266) \n node _vc_sel_T_274 = or(_vc_sel_T_273, _vc_sel_T_267) \n node _vc_sel_T_275 = or(_vc_sel_T_274, _vc_sel_T_268) \n node _vc_sel_T_276 = or(_vc_sel_T_275, _vc_sel_T_269) \n node _vc_sel_T_277 = or(_vc_sel_T_276, _vc_sel_T_270) \n wire _vc_sel_WIRE_20 : UInt<1> \n connect _vc_sel_WIRE_20, _vc_sel_T_277 \n connect _vc_sel_WIRE_18[1], _vc_sel_WIRE_20 \n node _vc_sel_T_278 = mux(_vc_sel_T, states[0].vc_sel.`2`[2], UInt<1>(0h0)) \n node _vc_sel_T_279 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[2], UInt<1>(0h0)) \n node _vc_sel_T_280 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[2], UInt<1>(0h0)) \n node _vc_sel_T_281 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[2], UInt<1>(0h0)) \n node _vc_sel_T_282 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[2], UInt<1>(0h0)) \n node _vc_sel_T_283 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[2], UInt<1>(0h0)) \n node _vc_sel_T_284 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[2], UInt<1>(0h0)) \n node _vc_sel_T_285 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[2], UInt<1>(0h0)) \n node _vc_sel_T_286 = or(_vc_sel_T_278, _vc_sel_T_279) \n node _vc_sel_T_287 = or(_vc_sel_T_286, _vc_sel_T_280) \n node _vc_sel_T_288 = or(_vc_sel_T_287, _vc_sel_T_281) \n node _vc_sel_T_289 = or(_vc_sel_T_288, _vc_sel_T_282) \n node _vc_sel_T_290 = or(_vc_sel_T_289, _vc_sel_T_283) \n node _vc_sel_T_291 = or(_vc_sel_T_290, _vc_sel_T_284) \n node _vc_sel_T_292 = or(_vc_sel_T_291, _vc_sel_T_285) \n wire _vc_sel_WIRE_21 : UInt<1> \n connect _vc_sel_WIRE_21, _vc_sel_T_292 \n connect _vc_sel_WIRE_18[2], _vc_sel_WIRE_21 \n node _vc_sel_T_293 = mux(_vc_sel_T, states[0].vc_sel.`2`[3], UInt<1>(0h0)) \n node _vc_sel_T_294 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[3], UInt<1>(0h0)) \n node _vc_sel_T_295 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[3], UInt<1>(0h0)) \n node _vc_sel_T_296 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[3], UInt<1>(0h0)) \n node _vc_sel_T_297 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[3], UInt<1>(0h0)) \n node _vc_sel_T_298 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[3], UInt<1>(0h0)) \n node _vc_sel_T_299 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[3], UInt<1>(0h0)) \n node _vc_sel_T_300 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[3], UInt<1>(0h0)) \n node _vc_sel_T_301 = or(_vc_sel_T_293, _vc_sel_T_294) \n node _vc_sel_T_302 = or(_vc_sel_T_301, _vc_sel_T_295) \n node _vc_sel_T_303 = or(_vc_sel_T_302, _vc_sel_T_296) \n node _vc_sel_T_304 = or(_vc_sel_T_303, _vc_sel_T_297) \n node _vc_sel_T_305 = or(_vc_sel_T_304, _vc_sel_T_298) \n node _vc_sel_T_306 = or(_vc_sel_T_305, _vc_sel_T_299) \n node _vc_sel_T_307 = or(_vc_sel_T_306, _vc_sel_T_300) \n wire _vc_sel_WIRE_22 : UInt<1> \n connect _vc_sel_WIRE_22, _vc_sel_T_307 \n connect _vc_sel_WIRE_18[3], _vc_sel_WIRE_22 \n node _vc_sel_T_308 = mux(_vc_sel_T, states[0].vc_sel.`2`[4], UInt<1>(0h0)) \n node _vc_sel_T_309 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[4], UInt<1>(0h0)) \n node _vc_sel_T_310 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[4], UInt<1>(0h0)) \n node _vc_sel_T_311 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[4], UInt<1>(0h0)) \n node _vc_sel_T_312 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[4], UInt<1>(0h0)) \n node _vc_sel_T_313 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[4], UInt<1>(0h0)) \n node _vc_sel_T_314 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[4], UInt<1>(0h0)) \n node _vc_sel_T_315 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[4], UInt<1>(0h0)) \n node _vc_sel_T_316 = or(_vc_sel_T_308, _vc_sel_T_309) \n node _vc_sel_T_317 = or(_vc_sel_T_316, _vc_sel_T_310) \n node _vc_sel_T_318 = or(_vc_sel_T_317, _vc_sel_T_311) \n node _vc_sel_T_319 = or(_vc_sel_T_318, _vc_sel_T_312) \n node _vc_sel_T_320 = or(_vc_sel_T_319, _vc_sel_T_313) \n node _vc_sel_T_321 = or(_vc_sel_T_320, _vc_sel_T_314) \n node _vc_sel_T_322 = or(_vc_sel_T_321, _vc_sel_T_315) \n wire _vc_sel_WIRE_23 : UInt<1> \n connect _vc_sel_WIRE_23, _vc_sel_T_322 \n connect _vc_sel_WIRE_18[4], _vc_sel_WIRE_23 \n node _vc_sel_T_323 = mux(_vc_sel_T, states[0].vc_sel.`2`[5], UInt<1>(0h0)) \n node _vc_sel_T_324 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[5], UInt<1>(0h0)) \n node _vc_sel_T_325 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[5], UInt<1>(0h0)) \n node _vc_sel_T_326 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[5], UInt<1>(0h0)) \n node _vc_sel_T_327 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[5], UInt<1>(0h0)) \n node _vc_sel_T_328 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[5], UInt<1>(0h0)) \n node _vc_sel_T_329 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[5], UInt<1>(0h0)) \n node _vc_sel_T_330 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[5], UInt<1>(0h0)) \n node _vc_sel_T_331 = or(_vc_sel_T_323, _vc_sel_T_324) \n node _vc_sel_T_332 = or(_vc_sel_T_331, _vc_sel_T_325) \n node _vc_sel_T_333 = or(_vc_sel_T_332, _vc_sel_T_326) \n node _vc_sel_T_334 = or(_vc_sel_T_333, _vc_sel_T_327) \n node _vc_sel_T_335 = or(_vc_sel_T_334, _vc_sel_T_328) \n node _vc_sel_T_336 = or(_vc_sel_T_335, _vc_sel_T_329) \n node _vc_sel_T_337 = or(_vc_sel_T_336, _vc_sel_T_330) \n wire _vc_sel_WIRE_24 : UInt<1> \n connect _vc_sel_WIRE_24, _vc_sel_T_337 \n connect _vc_sel_WIRE_18[5], _vc_sel_WIRE_24 \n node _vc_sel_T_338 = mux(_vc_sel_T, states[0].vc_sel.`2`[6], UInt<1>(0h0)) \n node _vc_sel_T_339 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[6], UInt<1>(0h0)) \n node _vc_sel_T_340 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[6], UInt<1>(0h0)) \n node _vc_sel_T_341 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[6], UInt<1>(0h0)) \n node _vc_sel_T_342 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[6], UInt<1>(0h0)) \n node _vc_sel_T_343 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[6], UInt<1>(0h0)) \n node _vc_sel_T_344 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[6], UInt<1>(0h0)) \n node _vc_sel_T_345 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[6], UInt<1>(0h0)) \n node _vc_sel_T_346 = or(_vc_sel_T_338, _vc_sel_T_339) \n node _vc_sel_T_347 = or(_vc_sel_T_346, _vc_sel_T_340) \n node _vc_sel_T_348 = or(_vc_sel_T_347, _vc_sel_T_341) \n node _vc_sel_T_349 = or(_vc_sel_T_348, _vc_sel_T_342) \n node _vc_sel_T_350 = or(_vc_sel_T_349, _vc_sel_T_343) \n node _vc_sel_T_351 = or(_vc_sel_T_350, _vc_sel_T_344) \n node _vc_sel_T_352 = or(_vc_sel_T_351, _vc_sel_T_345) \n wire _vc_sel_WIRE_25 : UInt<1> \n connect _vc_sel_WIRE_25, _vc_sel_T_352 \n connect _vc_sel_WIRE_18[6], _vc_sel_WIRE_25 \n node _vc_sel_T_353 = mux(_vc_sel_T, states[0].vc_sel.`2`[7], UInt<1>(0h0)) \n node _vc_sel_T_354 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[7], UInt<1>(0h0)) \n node _vc_sel_T_355 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[7], UInt<1>(0h0)) \n node _vc_sel_T_356 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[7], UInt<1>(0h0)) \n node _vc_sel_T_357 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[7], UInt<1>(0h0)) \n node _vc_sel_T_358 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[7], UInt<1>(0h0)) \n node _vc_sel_T_359 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[7], UInt<1>(0h0)) \n node _vc_sel_T_360 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[7], UInt<1>(0h0)) \n node _vc_sel_T_361 = or(_vc_sel_T_353, _vc_sel_T_354) \n node _vc_sel_T_362 = or(_vc_sel_T_361, _vc_sel_T_355) \n node _vc_sel_T_363 = or(_vc_sel_T_362, _vc_sel_T_356) \n node _vc_sel_T_364 = or(_vc_sel_T_363, _vc_sel_T_357) \n node _vc_sel_T_365 = or(_vc_sel_T_364, _vc_sel_T_358) \n node _vc_sel_T_366 = or(_vc_sel_T_365, _vc_sel_T_359) \n node _vc_sel_T_367 = or(_vc_sel_T_366, _vc_sel_T_360) \n wire _vc_sel_WIRE_26 : UInt<1> \n connect _vc_sel_WIRE_26, _vc_sel_T_367 \n connect _vc_sel_WIRE_18[7], _vc_sel_WIRE_26 \n connect vc_sel.`2`, _vc_sel_WIRE_18 \n wire _vc_sel_WIRE_27 : UInt<1>[8] \n node _vc_sel_T_368 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0)) \n node _vc_sel_T_369 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0)) \n node _vc_sel_T_370 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[0], UInt<1>(0h0)) \n node _vc_sel_T_371 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[0], UInt<1>(0h0)) \n node _vc_sel_T_372 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[0], UInt<1>(0h0)) \n node _vc_sel_T_373 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[0], UInt<1>(0h0)) \n node _vc_sel_T_374 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[0], UInt<1>(0h0)) \n node _vc_sel_T_375 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[0], UInt<1>(0h0)) \n node _vc_sel_T_376 = or(_vc_sel_T_368, _vc_sel_T_369) \n node _vc_sel_T_377 = or(_vc_sel_T_376, _vc_sel_T_370) \n node _vc_sel_T_378 = or(_vc_sel_T_377, _vc_sel_T_371) \n node _vc_sel_T_379 = or(_vc_sel_T_378, _vc_sel_T_372) \n node _vc_sel_T_380 = or(_vc_sel_T_379, _vc_sel_T_373) \n node _vc_sel_T_381 = or(_vc_sel_T_380, _vc_sel_T_374) \n node _vc_sel_T_382 = or(_vc_sel_T_381, _vc_sel_T_375) \n wire _vc_sel_WIRE_28 : UInt<1> \n connect _vc_sel_WIRE_28, _vc_sel_T_382 \n connect _vc_sel_WIRE_27[0], _vc_sel_WIRE_28 \n node _vc_sel_T_383 = mux(_vc_sel_T, states[0].vc_sel.`3`[1], UInt<1>(0h0)) \n node _vc_sel_T_384 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[1], UInt<1>(0h0)) \n node _vc_sel_T_385 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[1], UInt<1>(0h0)) \n node _vc_sel_T_386 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[1], UInt<1>(0h0)) \n node _vc_sel_T_387 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[1], UInt<1>(0h0)) \n node _vc_sel_T_388 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[1], UInt<1>(0h0)) \n node _vc_sel_T_389 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[1], UInt<1>(0h0)) \n node _vc_sel_T_390 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[1], UInt<1>(0h0)) \n node _vc_sel_T_391 = or(_vc_sel_T_383, _vc_sel_T_384) \n node _vc_sel_T_392 = or(_vc_sel_T_391, _vc_sel_T_385) \n node _vc_sel_T_393 = or(_vc_sel_T_392, _vc_sel_T_386) \n node _vc_sel_T_394 = or(_vc_sel_T_393, _vc_sel_T_387) \n node _vc_sel_T_395 = or(_vc_sel_T_394, _vc_sel_T_388) \n node _vc_sel_T_396 = or(_vc_sel_T_395, _vc_sel_T_389) \n node _vc_sel_T_397 = or(_vc_sel_T_396, _vc_sel_T_390) \n wire _vc_sel_WIRE_29 : UInt<1> \n connect _vc_sel_WIRE_29, _vc_sel_T_397 \n connect _vc_sel_WIRE_27[1], _vc_sel_WIRE_29 \n node _vc_sel_T_398 = mux(_vc_sel_T, states[0].vc_sel.`3`[2], UInt<1>(0h0)) \n node _vc_sel_T_399 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[2], UInt<1>(0h0)) \n node _vc_sel_T_400 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[2], UInt<1>(0h0)) \n node _vc_sel_T_401 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[2], UInt<1>(0h0)) \n node _vc_sel_T_402 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[2], UInt<1>(0h0)) \n node _vc_sel_T_403 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[2], UInt<1>(0h0)) \n node _vc_sel_T_404 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[2], UInt<1>(0h0)) \n node _vc_sel_T_405 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[2], UInt<1>(0h0)) \n node _vc_sel_T_406 = or(_vc_sel_T_398, _vc_sel_T_399) \n node _vc_sel_T_407 = or(_vc_sel_T_406, _vc_sel_T_400) \n node _vc_sel_T_408 = or(_vc_sel_T_407, _vc_sel_T_401) \n node _vc_sel_T_409 = or(_vc_sel_T_408, _vc_sel_T_402) \n node _vc_sel_T_410 = or(_vc_sel_T_409, _vc_sel_T_403) \n node _vc_sel_T_411 = or(_vc_sel_T_410, _vc_sel_T_404) \n node _vc_sel_T_412 = or(_vc_sel_T_411, _vc_sel_T_405) \n wire _vc_sel_WIRE_30 : UInt<1> \n connect _vc_sel_WIRE_30, _vc_sel_T_412 \n connect _vc_sel_WIRE_27[2], _vc_sel_WIRE_30 \n node _vc_sel_T_413 = mux(_vc_sel_T, states[0].vc_sel.`3`[3], UInt<1>(0h0)) \n node _vc_sel_T_414 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[3], UInt<1>(0h0)) \n node _vc_sel_T_415 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[3], UInt<1>(0h0)) \n node _vc_sel_T_416 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[3], UInt<1>(0h0)) \n node _vc_sel_T_417 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[3], UInt<1>(0h0)) \n node _vc_sel_T_418 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[3], UInt<1>(0h0)) \n node _vc_sel_T_419 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[3], UInt<1>(0h0)) \n node _vc_sel_T_420 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[3], UInt<1>(0h0)) \n node _vc_sel_T_421 = or(_vc_sel_T_413, _vc_sel_T_414) \n node _vc_sel_T_422 = or(_vc_sel_T_421, _vc_sel_T_415) \n node _vc_sel_T_423 = or(_vc_sel_T_422, _vc_sel_T_416) \n node _vc_sel_T_424 = or(_vc_sel_T_423, _vc_sel_T_417) \n node _vc_sel_T_425 = or(_vc_sel_T_424, _vc_sel_T_418) \n node _vc_sel_T_426 = or(_vc_sel_T_425, _vc_sel_T_419) \n node _vc_sel_T_427 = or(_vc_sel_T_426, _vc_sel_T_420) \n wire _vc_sel_WIRE_31 : UInt<1> \n connect _vc_sel_WIRE_31, _vc_sel_T_427 \n connect _vc_sel_WIRE_27[3], _vc_sel_WIRE_31 \n node _vc_sel_T_428 = mux(_vc_sel_T, states[0].vc_sel.`3`[4], UInt<1>(0h0)) \n node _vc_sel_T_429 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[4], UInt<1>(0h0)) \n node _vc_sel_T_430 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[4], UInt<1>(0h0)) \n node _vc_sel_T_431 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[4], UInt<1>(0h0)) \n node _vc_sel_T_432 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[4], UInt<1>(0h0)) \n node _vc_sel_T_433 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[4], UInt<1>(0h0)) \n node _vc_sel_T_434 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[4], UInt<1>(0h0)) \n node _vc_sel_T_435 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[4], UInt<1>(0h0)) \n node _vc_sel_T_436 = or(_vc_sel_T_428, _vc_sel_T_429) \n node _vc_sel_T_437 = or(_vc_sel_T_436, _vc_sel_T_430) \n node _vc_sel_T_438 = or(_vc_sel_T_437, _vc_sel_T_431) \n node _vc_sel_T_439 = or(_vc_sel_T_438, _vc_sel_T_432) \n node _vc_sel_T_440 = or(_vc_sel_T_439, _vc_sel_T_433) \n node _vc_sel_T_441 = or(_vc_sel_T_440, _vc_sel_T_434) \n node _vc_sel_T_442 = or(_vc_sel_T_441, _vc_sel_T_435) \n wire _vc_sel_WIRE_32 : UInt<1> \n connect _vc_sel_WIRE_32, _vc_sel_T_442 \n connect _vc_sel_WIRE_27[4], _vc_sel_WIRE_32 \n node _vc_sel_T_443 = mux(_vc_sel_T, states[0].vc_sel.`3`[5], UInt<1>(0h0)) \n node _vc_sel_T_444 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[5], UInt<1>(0h0)) \n node _vc_sel_T_445 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[5], UInt<1>(0h0)) \n node _vc_sel_T_446 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[5], UInt<1>(0h0)) \n node _vc_sel_T_447 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[5], UInt<1>(0h0)) \n node _vc_sel_T_448 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[5], UInt<1>(0h0)) \n node _vc_sel_T_449 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[5], UInt<1>(0h0)) \n node _vc_sel_T_450 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[5], UInt<1>(0h0)) \n node _vc_sel_T_451 = or(_vc_sel_T_443, _vc_sel_T_444) \n node _vc_sel_T_452 = or(_vc_sel_T_451, _vc_sel_T_445) \n node _vc_sel_T_453 = or(_vc_sel_T_452, _vc_sel_T_446) \n node _vc_sel_T_454 = or(_vc_sel_T_453, _vc_sel_T_447) \n node _vc_sel_T_455 = or(_vc_sel_T_454, _vc_sel_T_448) \n node _vc_sel_T_456 = or(_vc_sel_T_455, _vc_sel_T_449) \n node _vc_sel_T_457 = or(_vc_sel_T_456, _vc_sel_T_450) \n wire _vc_sel_WIRE_33 : UInt<1> \n connect _vc_sel_WIRE_33, _vc_sel_T_457 \n connect _vc_sel_WIRE_27[5], _vc_sel_WIRE_33 \n node _vc_sel_T_458 = mux(_vc_sel_T, states[0].vc_sel.`3`[6], UInt<1>(0h0)) \n node _vc_sel_T_459 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[6], UInt<1>(0h0)) \n node _vc_sel_T_460 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[6], UInt<1>(0h0)) \n node _vc_sel_T_461 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[6], UInt<1>(0h0)) \n node _vc_sel_T_462 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[6], UInt<1>(0h0)) \n node _vc_sel_T_463 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[6], UInt<1>(0h0)) \n node _vc_sel_T_464 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[6], UInt<1>(0h0)) \n node _vc_sel_T_465 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[6], UInt<1>(0h0)) \n node _vc_sel_T_466 = or(_vc_sel_T_458, _vc_sel_T_459) \n node _vc_sel_T_467 = or(_vc_sel_T_466, _vc_sel_T_460) \n node _vc_sel_T_468 = or(_vc_sel_T_467, _vc_sel_T_461) \n node _vc_sel_T_469 = or(_vc_sel_T_468, _vc_sel_T_462) \n node _vc_sel_T_470 = or(_vc_sel_T_469, _vc_sel_T_463) \n node _vc_sel_T_471 = or(_vc_sel_T_470, _vc_sel_T_464) \n node _vc_sel_T_472 = or(_vc_sel_T_471, _vc_sel_T_465) \n wire _vc_sel_WIRE_34 : UInt<1> \n connect _vc_sel_WIRE_34, _vc_sel_T_472 \n connect _vc_sel_WIRE_27[6], _vc_sel_WIRE_34 \n node _vc_sel_T_473 = mux(_vc_sel_T, states[0].vc_sel.`3`[7], UInt<1>(0h0)) \n node _vc_sel_T_474 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[7], UInt<1>(0h0)) \n node _vc_sel_T_475 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[7], UInt<1>(0h0)) \n node _vc_sel_T_476 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[7], UInt<1>(0h0)) \n node _vc_sel_T_477 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[7], UInt<1>(0h0)) \n node _vc_sel_T_478 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[7], UInt<1>(0h0)) \n node _vc_sel_T_479 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[7], UInt<1>(0h0)) \n node _vc_sel_T_480 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[7], UInt<1>(0h0)) \n node _vc_sel_T_481 = or(_vc_sel_T_473, _vc_sel_T_474) \n node _vc_sel_T_482 = or(_vc_sel_T_481, _vc_sel_T_475) \n node _vc_sel_T_483 = or(_vc_sel_T_482, _vc_sel_T_476) \n node _vc_sel_T_484 = or(_vc_sel_T_483, _vc_sel_T_477) \n node _vc_sel_T_485 = or(_vc_sel_T_484, _vc_sel_T_478) \n node _vc_sel_T_486 = or(_vc_sel_T_485, _vc_sel_T_479) \n node _vc_sel_T_487 = or(_vc_sel_T_486, _vc_sel_T_480) \n wire _vc_sel_WIRE_35 : UInt<1> \n connect _vc_sel_WIRE_35, _vc_sel_T_487 \n connect _vc_sel_WIRE_27[7], _vc_sel_WIRE_35 \n connect vc_sel.`3`, _vc_sel_WIRE_27 \n node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1]) \n node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2]) \n node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3]) \n node _channel_oh_T_3 = or(_channel_oh_T_2, vc_sel.`0`[4]) \n node _channel_oh_T_4 = or(_channel_oh_T_3, vc_sel.`0`[5]) \n node _channel_oh_T_5 = or(_channel_oh_T_4, vc_sel.`0`[6]) \n node channel_oh_0 = or(_channel_oh_T_5, vc_sel.`0`[7]) \n node _channel_oh_T_6 = or(vc_sel.`1`[0], vc_sel.`1`[1]) \n node _channel_oh_T_7 = or(_channel_oh_T_6, vc_sel.`1`[2]) \n node _channel_oh_T_8 = or(_channel_oh_T_7, vc_sel.`1`[3]) \n node _channel_oh_T_9 = or(_channel_oh_T_8, vc_sel.`1`[4]) \n node _channel_oh_T_10 = or(_channel_oh_T_9, vc_sel.`1`[5]) \n node _channel_oh_T_11 = or(_channel_oh_T_10, vc_sel.`1`[6]) \n node channel_oh_1 = or(_channel_oh_T_11, vc_sel.`1`[7]) \n node _channel_oh_T_12 = or(vc_sel.`2`[0], vc_sel.`2`[1]) \n node _channel_oh_T_13 = or(_channel_oh_T_12, vc_sel.`2`[2]) \n node _channel_oh_T_14 = or(_channel_oh_T_13, vc_sel.`2`[3]) \n node _channel_oh_T_15 = or(_channel_oh_T_14, vc_sel.`2`[4]) \n node _channel_oh_T_16 = or(_channel_oh_T_15, vc_sel.`2`[5]) \n node _channel_oh_T_17 = or(_channel_oh_T_16, vc_sel.`2`[6]) \n node channel_oh_2 = or(_channel_oh_T_17, vc_sel.`2`[7]) \n node _channel_oh_T_18 = or(vc_sel.`3`[0], vc_sel.`3`[1]) \n node _channel_oh_T_19 = or(_channel_oh_T_18, vc_sel.`3`[2]) \n node _channel_oh_T_20 = or(_channel_oh_T_19, vc_sel.`3`[3]) \n node _channel_oh_T_21 = or(_channel_oh_T_20, vc_sel.`3`[4]) \n node _channel_oh_T_22 = or(_channel_oh_T_21, vc_sel.`3`[5]) \n node _channel_oh_T_23 = or(_channel_oh_T_22, vc_sel.`3`[6]) \n node channel_oh_3 = or(_channel_oh_T_23, vc_sel.`3`[7]) \n node virt_channel_lo_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0]) \n node virt_channel_lo_hi = cat(vc_sel.`0`[3], vc_sel.`0`[2]) \n node virt_channel_lo = cat(virt_channel_lo_hi, virt_channel_lo_lo) \n node virt_channel_hi_lo = cat(vc_sel.`0`[5], vc_sel.`0`[4]) \n node virt_channel_hi_hi = cat(vc_sel.`0`[7], vc_sel.`0`[6]) \n node virt_channel_hi = cat(virt_channel_hi_hi, virt_channel_hi_lo) \n node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo) \n node virt_channel_hi_1 = bits(_virt_channel_T, 7, 4) \n node virt_channel_lo_1 = bits(_virt_channel_T, 3, 0) \n node _virt_channel_T_1 = orr(virt_channel_hi_1) \n node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1) \n node virt_channel_hi_2 = bits(_virt_channel_T_2, 3, 2) \n node virt_channel_lo_2 = bits(_virt_channel_T_2, 1, 0) \n node _virt_channel_T_3 = orr(virt_channel_hi_2) \n node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2) \n node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1) \n node _virt_channel_T_6 = cat(_virt_channel_T_3, _virt_channel_T_5) \n node _virt_channel_T_7 = cat(_virt_channel_T_1, _virt_channel_T_6) \n node virt_channel_lo_lo_1 = cat(vc_sel.`1`[1], vc_sel.`1`[0]) \n node virt_channel_lo_hi_1 = cat(vc_sel.`1`[3], vc_sel.`1`[2]) \n node virt_channel_lo_3 = cat(virt_channel_lo_hi_1, virt_channel_lo_lo_1) \n node virt_channel_hi_lo_1 = cat(vc_sel.`1`[5], vc_sel.`1`[4]) \n node virt_channel_hi_hi_1 = cat(vc_sel.`1`[7], vc_sel.`1`[6]) \n node virt_channel_hi_3 = cat(virt_channel_hi_hi_1, virt_channel_hi_lo_1) \n node _virt_channel_T_8 = cat(virt_channel_hi_3, virt_channel_lo_3) \n node virt_channel_hi_4 = bits(_virt_channel_T_8, 7, 4) \n node virt_channel_lo_4 = bits(_virt_channel_T_8, 3, 0) \n node _virt_channel_T_9 = orr(virt_channel_hi_4) \n node _virt_channel_T_10 = or(virt_channel_hi_4, virt_channel_lo_4) \n node virt_channel_hi_5 = bits(_virt_channel_T_10, 3, 2) \n node virt_channel_lo_5 = bits(_virt_channel_T_10, 1, 0) \n node _virt_channel_T_11 = orr(virt_channel_hi_5) \n node _virt_channel_T_12 = or(virt_channel_hi_5, virt_channel_lo_5) \n node _virt_channel_T_13 = bits(_virt_channel_T_12, 1, 1) \n node _virt_channel_T_14 = cat(_virt_channel_T_11, _virt_channel_T_13) \n node _virt_channel_T_15 = cat(_virt_channel_T_9, _virt_channel_T_14) \n node virt_channel_lo_lo_2 = cat(vc_sel.`2`[1], vc_sel.`2`[0]) \n node virt_channel_lo_hi_2 = cat(vc_sel.`2`[3], vc_sel.`2`[2]) \n node virt_channel_lo_6 = cat(virt_channel_lo_hi_2, virt_channel_lo_lo_2) \n node virt_channel_hi_lo_2 = cat(vc_sel.`2`[5], vc_sel.`2`[4]) \n node virt_channel_hi_hi_2 = cat(vc_sel.`2`[7], vc_sel.`2`[6]) \n node virt_channel_hi_6 = cat(virt_channel_hi_hi_2, virt_channel_hi_lo_2) \n node _virt_channel_T_16 = cat(virt_channel_hi_6, virt_channel_lo_6) \n node virt_channel_hi_7 = bits(_virt_channel_T_16, 7, 4) \n node virt_channel_lo_7 = bits(_virt_channel_T_16, 3, 0) \n node _virt_channel_T_17 = orr(virt_channel_hi_7) \n node _virt_channel_T_18 = or(virt_channel_hi_7, virt_channel_lo_7) \n node virt_channel_hi_8 = bits(_virt_channel_T_18, 3, 2) \n node virt_channel_lo_8 = bits(_virt_channel_T_18, 1, 0) \n node _virt_channel_T_19 = orr(virt_channel_hi_8) \n node _virt_channel_T_20 = or(virt_channel_hi_8, virt_channel_lo_8) \n node _virt_channel_T_21 = bits(_virt_channel_T_20, 1, 1) \n node _virt_channel_T_22 = cat(_virt_channel_T_19, _virt_channel_T_21) \n node _virt_channel_T_23 = cat(_virt_channel_T_17, _virt_channel_T_22) \n node virt_channel_lo_lo_3 = cat(vc_sel.`3`[1], vc_sel.`3`[0]) \n node virt_channel_lo_hi_3 = cat(vc_sel.`3`[3], vc_sel.`3`[2]) \n node virt_channel_lo_9 = cat(virt_channel_lo_hi_3, virt_channel_lo_lo_3) \n node virt_channel_hi_lo_3 = cat(vc_sel.`3`[5], vc_sel.`3`[4]) \n node virt_channel_hi_hi_3 = cat(vc_sel.`3`[7], vc_sel.`3`[6]) \n node virt_channel_hi_9 = cat(virt_channel_hi_hi_3, virt_channel_hi_lo_3) \n node _virt_channel_T_24 = cat(virt_channel_hi_9, virt_channel_lo_9) \n node virt_channel_hi_10 = bits(_virt_channel_T_24, 7, 4) \n node virt_channel_lo_10 = bits(_virt_channel_T_24, 3, 0) \n node _virt_channel_T_25 = orr(virt_channel_hi_10) \n node _virt_channel_T_26 = or(virt_channel_hi_10, virt_channel_lo_10) \n node virt_channel_hi_11 = bits(_virt_channel_T_26, 3, 2) \n node virt_channel_lo_11 = bits(_virt_channel_T_26, 1, 0) \n node _virt_channel_T_27 = orr(virt_channel_hi_11) \n node _virt_channel_T_28 = or(virt_channel_hi_11, virt_channel_lo_11) \n node _virt_channel_T_29 = bits(_virt_channel_T_28, 1, 1) \n node _virt_channel_T_30 = cat(_virt_channel_T_27, _virt_channel_T_29) \n node _virt_channel_T_31 = cat(_virt_channel_T_25, _virt_channel_T_30) \n node _virt_channel_T_32 = mux(channel_oh_0, _virt_channel_T_7, UInt<1>(0h0)) \n node _virt_channel_T_33 = mux(channel_oh_1, _virt_channel_T_15, UInt<1>(0h0)) \n node _virt_channel_T_34 = mux(channel_oh_2, _virt_channel_T_23, UInt<1>(0h0)) \n node _virt_channel_T_35 = mux(channel_oh_3, _virt_channel_T_31, UInt<1>(0h0)) \n node _virt_channel_T_36 = or(_virt_channel_T_32, _virt_channel_T_33) \n node _virt_channel_T_37 = or(_virt_channel_T_36, _virt_channel_T_34) \n node _virt_channel_T_38 = or(_virt_channel_T_37, _virt_channel_T_35) \n wire virt_channel : UInt<3> \n connect virt_channel, _virt_channel_T_38 \n node _T_119 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) \n when _T_119 : \n connect salloc_outs[0].out_vid, virt_channel \n node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) \n node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) \n node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) \n node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) \n node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) \n node _salloc_outs_0_flit_payload_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) \n node _salloc_outs_0_flit_payload_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) \n node _salloc_outs_0_flit_payload_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) \n node _salloc_outs_0_flit_payload_T_8 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) \n node _salloc_outs_0_flit_payload_T_9 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) \n node _salloc_outs_0_flit_payload_T_10 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0)) \n node _salloc_outs_0_flit_payload_T_11 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0)) \n node _salloc_outs_0_flit_payload_T_12 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0)) \n node _salloc_outs_0_flit_payload_T_13 = mux(_salloc_outs_0_flit_payload_T_5, input_buffer.io.deq[5].bits.payload, UInt<1>(0h0)) \n node _salloc_outs_0_flit_payload_T_14 = mux(_salloc_outs_0_flit_payload_T_6, input_buffer.io.deq[6].bits.payload, UInt<1>(0h0)) \n node _salloc_outs_0_flit_payload_T_15 = mux(_salloc_outs_0_flit_payload_T_7, input_buffer.io.deq[7].bits.payload, UInt<1>(0h0)) \n node _salloc_outs_0_flit_payload_T_16 = or(_salloc_outs_0_flit_payload_T_8, _salloc_outs_0_flit_payload_T_9) \n node _salloc_outs_0_flit_payload_T_17 = or(_salloc_outs_0_flit_payload_T_16, _salloc_outs_0_flit_payload_T_10) \n node _salloc_outs_0_flit_payload_T_18 = or(_salloc_outs_0_flit_payload_T_17, _salloc_outs_0_flit_payload_T_11) \n node _salloc_outs_0_flit_payload_T_19 = or(_salloc_outs_0_flit_payload_T_18, _salloc_outs_0_flit_payload_T_12) \n node _salloc_outs_0_flit_payload_T_20 = or(_salloc_outs_0_flit_payload_T_19, _salloc_outs_0_flit_payload_T_13) \n node _salloc_outs_0_flit_payload_T_21 = or(_salloc_outs_0_flit_payload_T_20, _salloc_outs_0_flit_payload_T_14) \n node _salloc_outs_0_flit_payload_T_22 = or(_salloc_outs_0_flit_payload_T_21, _salloc_outs_0_flit_payload_T_15) \n wire _salloc_outs_0_flit_payload_WIRE : UInt<73> \n connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_22 \n connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE \n node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) \n node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) \n node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) \n node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) \n node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) \n node _salloc_outs_0_flit_head_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) \n node _salloc_outs_0_flit_head_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) \n node _salloc_outs_0_flit_head_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) \n node _salloc_outs_0_flit_head_T_8 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) \n node _salloc_outs_0_flit_head_T_9 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) \n node _salloc_outs_0_flit_head_T_10 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0)) \n node _salloc_outs_0_flit_head_T_11 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0)) \n node _salloc_outs_0_flit_head_T_12 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0)) \n node _salloc_outs_0_flit_head_T_13 = mux(_salloc_outs_0_flit_head_T_5, input_buffer.io.deq[5].bits.head, UInt<1>(0h0)) \n node _salloc_outs_0_flit_head_T_14 = mux(_salloc_outs_0_flit_head_T_6, input_buffer.io.deq[6].bits.head, UInt<1>(0h0)) \n node _salloc_outs_0_flit_head_T_15 = mux(_salloc_outs_0_flit_head_T_7, input_buffer.io.deq[7].bits.head, UInt<1>(0h0)) \n node _salloc_outs_0_flit_head_T_16 = or(_salloc_outs_0_flit_head_T_8, _salloc_outs_0_flit_head_T_9) \n node _salloc_outs_0_flit_head_T_17 = or(_salloc_outs_0_flit_head_T_16, _salloc_outs_0_flit_head_T_10) \n node _salloc_outs_0_flit_head_T_18 = or(_salloc_outs_0_flit_head_T_17, _salloc_outs_0_flit_head_T_11) \n node _salloc_outs_0_flit_head_T_19 = or(_salloc_outs_0_flit_head_T_18, _salloc_outs_0_flit_head_T_12) \n node _salloc_outs_0_flit_head_T_20 = or(_salloc_outs_0_flit_head_T_19, _salloc_outs_0_flit_head_T_13) \n node _salloc_outs_0_flit_head_T_21 = or(_salloc_outs_0_flit_head_T_20, _salloc_outs_0_flit_head_T_14) \n node _salloc_outs_0_flit_head_T_22 = or(_salloc_outs_0_flit_head_T_21, _salloc_outs_0_flit_head_T_15) \n wire _salloc_outs_0_flit_head_WIRE : UInt<1> \n connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_22 \n connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE \n node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) \n node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) \n node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) \n node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) \n node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) \n node _salloc_outs_0_flit_tail_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) \n node _salloc_outs_0_flit_tail_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) \n node _salloc_outs_0_flit_tail_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) \n node _salloc_outs_0_flit_tail_T_8 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) \n node _salloc_outs_0_flit_tail_T_9 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) \n node _salloc_outs_0_flit_tail_T_10 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) \n node _salloc_outs_0_flit_tail_T_11 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) \n node _salloc_outs_0_flit_tail_T_12 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) \n node _salloc_outs_0_flit_tail_T_13 = mux(_salloc_outs_0_flit_tail_T_5, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) \n node _salloc_outs_0_flit_tail_T_14 = mux(_salloc_outs_0_flit_tail_T_6, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0)) \n node _salloc_outs_0_flit_tail_T_15 = mux(_salloc_outs_0_flit_tail_T_7, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0)) \n node _salloc_outs_0_flit_tail_T_16 = or(_salloc_outs_0_flit_tail_T_8, _salloc_outs_0_flit_tail_T_9) \n node _salloc_outs_0_flit_tail_T_17 = or(_salloc_outs_0_flit_tail_T_16, _salloc_outs_0_flit_tail_T_10) \n node _salloc_outs_0_flit_tail_T_18 = or(_salloc_outs_0_flit_tail_T_17, _salloc_outs_0_flit_tail_T_11) \n node _salloc_outs_0_flit_tail_T_19 = or(_salloc_outs_0_flit_tail_T_18, _salloc_outs_0_flit_tail_T_12) \n node _salloc_outs_0_flit_tail_T_20 = or(_salloc_outs_0_flit_tail_T_19, _salloc_outs_0_flit_tail_T_13) \n node _salloc_outs_0_flit_tail_T_21 = or(_salloc_outs_0_flit_tail_T_20, _salloc_outs_0_flit_tail_T_14) \n node _salloc_outs_0_flit_tail_T_22 = or(_salloc_outs_0_flit_tail_T_21, _salloc_outs_0_flit_tail_T_15) \n wire _salloc_outs_0_flit_tail_WIRE : UInt<1> \n connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_22 \n connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE \n node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) \n node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) \n node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) \n node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) \n node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) \n node _salloc_outs_0_flit_flow_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) \n node _salloc_outs_0_flit_flow_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) \n node _salloc_outs_0_flit_flow_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) \n wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>} \n node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node_id, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node_id, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node_id, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9) \n node _salloc_outs_0_flit_flow_T_17 = or(_salloc_outs_0_flit_flow_T_16, _salloc_outs_0_flit_flow_T_10) \n node _salloc_outs_0_flit_flow_T_18 = or(_salloc_outs_0_flit_flow_T_17, _salloc_outs_0_flit_flow_T_11) \n node _salloc_outs_0_flit_flow_T_19 = or(_salloc_outs_0_flit_flow_T_18, _salloc_outs_0_flit_flow_T_12) \n node _salloc_outs_0_flit_flow_T_20 = or(_salloc_outs_0_flit_flow_T_19, _salloc_outs_0_flit_flow_T_13) \n node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_20, _salloc_outs_0_flit_flow_T_14) \n node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_15) \n wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2> \n connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_22 \n connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 \n node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_26 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_27 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_28 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_29 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_30 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_31 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24) \n node _salloc_outs_0_flit_flow_T_32 = or(_salloc_outs_0_flit_flow_T_31, _salloc_outs_0_flit_flow_T_25) \n node _salloc_outs_0_flit_flow_T_33 = or(_salloc_outs_0_flit_flow_T_32, _salloc_outs_0_flit_flow_T_26) \n node _salloc_outs_0_flit_flow_T_34 = or(_salloc_outs_0_flit_flow_T_33, _salloc_outs_0_flit_flow_T_27) \n node _salloc_outs_0_flit_flow_T_35 = or(_salloc_outs_0_flit_flow_T_34, _salloc_outs_0_flit_flow_T_28) \n node _salloc_outs_0_flit_flow_T_36 = or(_salloc_outs_0_flit_flow_T_35, _salloc_outs_0_flit_flow_T_29) \n node _salloc_outs_0_flit_flow_T_37 = or(_salloc_outs_0_flit_flow_T_36, _salloc_outs_0_flit_flow_T_30) \n wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<5> \n connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_37 \n connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 \n node _salloc_outs_0_flit_flow_T_38 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_39 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_40 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_41 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_42 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_43 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node_id, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_44 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node_id, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_45 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node_id, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_38, _salloc_outs_0_flit_flow_T_39) \n node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_40) \n node _salloc_outs_0_flit_flow_T_48 = or(_salloc_outs_0_flit_flow_T_47, _salloc_outs_0_flit_flow_T_41) \n node _salloc_outs_0_flit_flow_T_49 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_42) \n node _salloc_outs_0_flit_flow_T_50 = or(_salloc_outs_0_flit_flow_T_49, _salloc_outs_0_flit_flow_T_43) \n node _salloc_outs_0_flit_flow_T_51 = or(_salloc_outs_0_flit_flow_T_50, _salloc_outs_0_flit_flow_T_44) \n node _salloc_outs_0_flit_flow_T_52 = or(_salloc_outs_0_flit_flow_T_51, _salloc_outs_0_flit_flow_T_45) \n wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2> \n connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_52 \n connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 \n node _salloc_outs_0_flit_flow_T_53 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_54 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_55 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_56 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_57 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_58 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_59 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_60 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_61 = or(_salloc_outs_0_flit_flow_T_53, _salloc_outs_0_flit_flow_T_54) \n node _salloc_outs_0_flit_flow_T_62 = or(_salloc_outs_0_flit_flow_T_61, _salloc_outs_0_flit_flow_T_55) \n node _salloc_outs_0_flit_flow_T_63 = or(_salloc_outs_0_flit_flow_T_62, _salloc_outs_0_flit_flow_T_56) \n node _salloc_outs_0_flit_flow_T_64 = or(_salloc_outs_0_flit_flow_T_63, _salloc_outs_0_flit_flow_T_57) \n node _salloc_outs_0_flit_flow_T_65 = or(_salloc_outs_0_flit_flow_T_64, _salloc_outs_0_flit_flow_T_58) \n node _salloc_outs_0_flit_flow_T_66 = or(_salloc_outs_0_flit_flow_T_65, _salloc_outs_0_flit_flow_T_59) \n node _salloc_outs_0_flit_flow_T_67 = or(_salloc_outs_0_flit_flow_T_66, _salloc_outs_0_flit_flow_T_60) \n wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<5> \n connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_67 \n connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 \n node _salloc_outs_0_flit_flow_T_68 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_69 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_70 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_71 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_72 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_73 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.vnet_id, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_74 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.vnet_id, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_75 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.vnet_id, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_76 = or(_salloc_outs_0_flit_flow_T_68, _salloc_outs_0_flit_flow_T_69) \n node _salloc_outs_0_flit_flow_T_77 = or(_salloc_outs_0_flit_flow_T_76, _salloc_outs_0_flit_flow_T_70) \n node _salloc_outs_0_flit_flow_T_78 = or(_salloc_outs_0_flit_flow_T_77, _salloc_outs_0_flit_flow_T_71) \n node _salloc_outs_0_flit_flow_T_79 = or(_salloc_outs_0_flit_flow_T_78, _salloc_outs_0_flit_flow_T_72) \n node _salloc_outs_0_flit_flow_T_80 = or(_salloc_outs_0_flit_flow_T_79, _salloc_outs_0_flit_flow_T_73) \n node _salloc_outs_0_flit_flow_T_81 = or(_salloc_outs_0_flit_flow_T_80, _salloc_outs_0_flit_flow_T_74) \n node _salloc_outs_0_flit_flow_T_82 = or(_salloc_outs_0_flit_flow_T_81, _salloc_outs_0_flit_flow_T_75) \n wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<3> \n connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_82 \n connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 \n connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE \n else :\n\n invalidate salloc_outs[0].out_vid \n invalidate salloc_outs[0].flit.virt_channel_id \n invalidate salloc_outs[0].flit.flow.egress_node_id \n invalidate salloc_outs[0].flit.flow.egress_node \n invalidate salloc_outs[0].flit.flow.ingress_node_id \n invalidate salloc_outs[0].flit.flow.ingress_node \n invalidate salloc_outs[0].flit.flow.vnet_id \n invalidate salloc_outs[0].flit.payload \n invalidate salloc_outs[0].flit.tail \n invalidate salloc_outs[0].flit.head \n invalidate salloc_outs[0].flit.virt_channel_id \n connect io.out[0].valid, salloc_outs[0].valid \n connect io.out[0].bits.flit, salloc_outs[0].flit \n connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid \n connect states[0].vc_sel.`0`[0], UInt<1>(0h0) \n connect states[0].vc_sel.`0`[1], UInt<1>(0h0) \n connect states[0].vc_sel.`0`[2], UInt<1>(0h0) \n connect states[0].vc_sel.`0`[3], UInt<1>(0h0) \n connect states[0].vc_sel.`0`[4], UInt<1>(0h0) \n connect states[0].vc_sel.`0`[5], UInt<1>(0h0) \n connect states[0].vc_sel.`0`[6], UInt<1>(0h0) \n connect states[0].vc_sel.`0`[7], UInt<1>(0h0) \n connect states[0].vc_sel.`1`[0], UInt<1>(0h0) \n connect states[0].vc_sel.`3`[0], UInt<1>(0h0) \n connect states[0].vc_sel.`3`[1], UInt<1>(0h0) \n connect states[0].vc_sel.`3`[2], UInt<1>(0h0) \n connect states[0].vc_sel.`3`[3], UInt<1>(0h0) \n connect states[0].vc_sel.`3`[4], UInt<1>(0h0) \n connect states[0].vc_sel.`3`[5], UInt<1>(0h0) \n connect states[0].vc_sel.`3`[6], UInt<1>(0h0) \n connect states[0].vc_sel.`3`[7], UInt<1>(0h0) \n connect states[1].vc_sel.`0`[0], UInt<1>(0h0) \n connect states[1].vc_sel.`0`[1], UInt<1>(0h0) \n connect states[1].vc_sel.`0`[2], UInt<1>(0h0) \n connect states[1].vc_sel.`0`[3], UInt<1>(0h0) \n connect states[1].vc_sel.`0`[4], UInt<1>(0h0) \n connect states[1].vc_sel.`0`[5], UInt<1>(0h0) \n connect states[1].vc_sel.`0`[6], UInt<1>(0h0) \n connect states[1].vc_sel.`0`[7], UInt<1>(0h0) \n connect states[1].vc_sel.`1`[0], UInt<1>(0h0) \n connect states[1].vc_sel.`3`[0], UInt<1>(0h0) \n connect states[1].vc_sel.`3`[1], UInt<1>(0h0) \n connect states[1].vc_sel.`3`[2], UInt<1>(0h0) \n connect states[1].vc_sel.`3`[3], UInt<1>(0h0) \n connect states[1].vc_sel.`3`[4], UInt<1>(0h0) \n connect states[1].vc_sel.`3`[5], UInt<1>(0h0) \n connect states[1].vc_sel.`3`[6], UInt<1>(0h0) \n connect states[1].vc_sel.`3`[7], UInt<1>(0h0) \n connect states[2].vc_sel.`0`[0], UInt<1>(0h0) \n connect states[2].vc_sel.`0`[1], UInt<1>(0h0) \n connect states[2].vc_sel.`0`[2], UInt<1>(0h0) \n connect states[2].vc_sel.`0`[3], UInt<1>(0h0) \n connect states[2].vc_sel.`0`[4], UInt<1>(0h0) \n connect states[2].vc_sel.`0`[5], UInt<1>(0h0) \n connect states[2].vc_sel.`0`[6], UInt<1>(0h0) \n connect states[2].vc_sel.`0`[7], UInt<1>(0h0) \n connect states[2].vc_sel.`1`[0], UInt<1>(0h0) \n connect states[2].vc_sel.`3`[0], UInt<1>(0h0) \n connect states[2].vc_sel.`3`[1], UInt<1>(0h0) \n connect states[2].vc_sel.`3`[2], UInt<1>(0h0) \n connect states[2].vc_sel.`3`[3], UInt<1>(0h0) \n connect states[2].vc_sel.`3`[4], UInt<1>(0h0) \n connect states[2].vc_sel.`3`[5], UInt<1>(0h0) \n connect states[2].vc_sel.`3`[6], UInt<1>(0h0) \n connect states[2].vc_sel.`3`[7], UInt<1>(0h0) \n connect states[3].vc_sel.`0`[0], UInt<1>(0h0) \n connect states[3].vc_sel.`0`[1], UInt<1>(0h0) \n connect states[3].vc_sel.`0`[2], UInt<1>(0h0) \n connect states[3].vc_sel.`0`[3], UInt<1>(0h0) \n connect states[3].vc_sel.`0`[4], UInt<1>(0h0) \n connect states[3].vc_sel.`0`[5], UInt<1>(0h0) \n connect states[3].vc_sel.`0`[6], UInt<1>(0h0) \n connect states[3].vc_sel.`0`[7], UInt<1>(0h0) \n connect states[3].vc_sel.`1`[0], UInt<1>(0h0) \n connect states[3].vc_sel.`3`[0], UInt<1>(0h0) \n connect states[3].vc_sel.`3`[1], UInt<1>(0h0) \n connect states[3].vc_sel.`3`[2], UInt<1>(0h0) \n connect states[3].vc_sel.`3`[3], UInt<1>(0h0) \n connect states[3].vc_sel.`3`[4], UInt<1>(0h0) \n connect states[3].vc_sel.`3`[5], UInt<1>(0h0) \n connect states[3].vc_sel.`3`[6], UInt<1>(0h0) \n connect states[3].vc_sel.`3`[7], UInt<1>(0h0) \n connect states[4].vc_sel.`0`[0], UInt<1>(0h0) \n connect states[4].vc_sel.`0`[1], UInt<1>(0h0) \n connect states[4].vc_sel.`0`[2], UInt<1>(0h0) \n connect states[4].vc_sel.`0`[3], UInt<1>(0h0) \n connect states[4].vc_sel.`0`[4], UInt<1>(0h0) \n connect states[4].vc_sel.`0`[5], UInt<1>(0h0) \n connect states[4].vc_sel.`0`[6], UInt<1>(0h0) \n connect states[4].vc_sel.`0`[7], UInt<1>(0h0) \n connect states[4].vc_sel.`1`[0], UInt<1>(0h0) \n connect states[4].vc_sel.`3`[0], UInt<1>(0h0) \n connect states[4].vc_sel.`3`[1], UInt<1>(0h0) \n connect states[4].vc_sel.`3`[2], UInt<1>(0h0) \n connect states[4].vc_sel.`3`[3], UInt<1>(0h0) \n connect states[4].vc_sel.`3`[4], UInt<1>(0h0) \n connect states[4].vc_sel.`3`[5], UInt<1>(0h0) \n connect states[4].vc_sel.`3`[6], UInt<1>(0h0) \n connect states[4].vc_sel.`3`[7], UInt<1>(0h0) \n connect states[5].vc_sel.`0`[0], UInt<1>(0h0) \n connect states[5].vc_sel.`0`[1], UInt<1>(0h0) \n connect states[5].vc_sel.`0`[2], UInt<1>(0h0) \n connect states[5].vc_sel.`0`[3], UInt<1>(0h0) \n connect states[5].vc_sel.`0`[4], UInt<1>(0h0) \n connect states[5].vc_sel.`0`[5], UInt<1>(0h0) \n connect states[5].vc_sel.`0`[6], UInt<1>(0h0) \n connect states[5].vc_sel.`0`[7], UInt<1>(0h0) \n connect states[5].vc_sel.`1`[0], UInt<1>(0h0) \n connect states[5].vc_sel.`3`[0], UInt<1>(0h0) \n connect states[5].vc_sel.`3`[1], UInt<1>(0h0) \n connect states[5].vc_sel.`3`[2], UInt<1>(0h0) \n connect states[5].vc_sel.`3`[3], UInt<1>(0h0) \n connect states[5].vc_sel.`3`[4], UInt<1>(0h0) \n connect states[5].vc_sel.`3`[5], UInt<1>(0h0) \n connect states[5].vc_sel.`3`[6], UInt<1>(0h0) \n connect states[5].vc_sel.`3`[7], UInt<1>(0h0) \n connect states[6].vc_sel.`0`[0], UInt<1>(0h0) \n connect states[6].vc_sel.`0`[1], UInt<1>(0h0) \n connect states[6].vc_sel.`0`[2], UInt<1>(0h0) \n connect states[6].vc_sel.`0`[3], UInt<1>(0h0) \n connect states[6].vc_sel.`0`[4], UInt<1>(0h0) \n connect states[6].vc_sel.`0`[5], UInt<1>(0h0) \n connect states[6].vc_sel.`0`[6], UInt<1>(0h0) \n connect states[6].vc_sel.`0`[7], UInt<1>(0h0) \n connect states[6].vc_sel.`1`[0], UInt<1>(0h0) \n connect states[6].vc_sel.`3`[0], UInt<1>(0h0) \n connect states[6].vc_sel.`3`[1], UInt<1>(0h0) \n connect states[6].vc_sel.`3`[2], UInt<1>(0h0) \n connect states[6].vc_sel.`3`[3], UInt<1>(0h0) \n connect states[6].vc_sel.`3`[4], UInt<1>(0h0) \n connect states[6].vc_sel.`3`[5], UInt<1>(0h0) \n connect states[6].vc_sel.`3`[6], UInt<1>(0h0) \n connect states[6].vc_sel.`3`[7], UInt<1>(0h0) \n connect states[7].vc_sel.`0`[0], UInt<1>(0h0) \n connect states[7].vc_sel.`0`[1], UInt<1>(0h0) \n connect states[7].vc_sel.`0`[2], UInt<1>(0h0) \n connect states[7].vc_sel.`0`[3], UInt<1>(0h0) \n connect states[7].vc_sel.`0`[4], UInt<1>(0h0) \n connect states[7].vc_sel.`0`[5], UInt<1>(0h0) \n connect states[7].vc_sel.`0`[6], UInt<1>(0h0) \n connect states[7].vc_sel.`0`[7], UInt<1>(0h0) \n connect states[7].vc_sel.`1`[0], UInt<1>(0h0) \n connect states[7].vc_sel.`3`[0], UInt<1>(0h0) \n connect states[7].vc_sel.`3`[1], UInt<1>(0h0) \n connect states[7].vc_sel.`3`[2], UInt<1>(0h0) \n connect states[7].vc_sel.`3`[3], UInt<1>(0h0) \n connect states[7].vc_sel.`3`[4], UInt<1>(0h0) \n connect states[7].vc_sel.`3`[5], UInt<1>(0h0) \n connect states[7].vc_sel.`3`[6], UInt<1>(0h0) \n connect states[7].vc_sel.`3`[7], UInt<1>(0h0) \n node _T_120 = asUInt(reset) \n when _T_120 : \n connect states[0].g, UInt<3>(0h0) \n connect states[1].g, UInt<3>(0h0) \n connect states[2].g, UInt<3>(0h0) \n connect states[3].g, UInt<3>(0h0) \n connect states[4].g, UInt<3>(0h0) \n connect states[5].g, UInt<3>(0h0) \n connect states[6].g, UInt<3>(0h0) \n connect states[7].g, UInt<3>(0h0)"},"response":{"kind":"string","value":"module InputUnit_59(\t// @[InputUnit.scala:158:7]\n input clock,\t// @[InputUnit.scala:158:7]\n input reset,\t// @[InputUnit.scala:158:7]\n output [2:0] io_router_req_bits_src_virt_id,\t// @[InputUnit.scala:170:14]\n output [2:0] io_router_req_bits_flow_vnet_id,\t// @[InputUnit.scala:170:14]\n output [4:0] io_router_req_bits_flow_ingress_node,\t// @[InputUnit.scala:170:14]\n output [1:0] io_router_req_bits_flow_ingress_node_id,\t// @[InputUnit.scala:170:14]\n output [4:0] io_router_req_bits_flow_egress_node,\t// @[InputUnit.scala:170:14]\n output [1:0] io_router_req_bits_flow_egress_node_id,\t// @[InputUnit.scala:170:14]\n input io_router_resp_vc_sel_2_0,\t// @[InputUnit.scala:170:14]\n input io_router_resp_vc_sel_2_1,\t// @[InputUnit.scala:170:14]\n input io_router_resp_vc_sel_2_2,\t// @[InputUnit.scala:170:14]\n input io_router_resp_vc_sel_2_3,\t// @[InputUnit.scala:170:14]\n input io_router_resp_vc_sel_2_4,\t// @[InputUnit.scala:170:14]\n input io_router_resp_vc_sel_2_5,\t// @[InputUnit.scala:170:14]\n input io_router_resp_vc_sel_2_6,\t// @[InputUnit.scala:170:14]\n input io_router_resp_vc_sel_2_7,\t// @[InputUnit.scala:170:14]\n input io_router_resp_vc_sel_1_1,\t// @[InputUnit.scala:170:14]\n input io_router_resp_vc_sel_1_2,\t// @[InputUnit.scala:170:14]\n input io_router_resp_vc_sel_1_3,\t// @[InputUnit.scala:170:14]\n input io_router_resp_vc_sel_1_4,\t// @[InputUnit.scala:170:14]\n input io_router_resp_vc_sel_1_5,\t// @[InputUnit.scala:170:14]\n input io_router_resp_vc_sel_1_6,\t// @[InputUnit.scala:170:14]\n input io_router_resp_vc_sel_1_7,\t// @[InputUnit.scala:170:14]\n input io_vcalloc_req_ready,\t// @[InputUnit.scala:170:14]\n output io_vcalloc_req_valid,\t// @[InputUnit.scala:170:14]\n output io_vcalloc_req_bits_vc_sel_2_0,\t// @[InputUnit.scala:170:14]\n output io_vcalloc_req_bits_vc_sel_2_1,\t// @[InputUnit.scala:170:14]\n output io_vcalloc_req_bits_vc_sel_2_2,\t// @[InputUnit.scala:170:14]\n output io_vcalloc_req_bits_vc_sel_2_3,\t// @[InputUnit.scala:170:14]\n output io_vcalloc_req_bits_vc_sel_2_4,\t// @[InputUnit.scala:170:14]\n output io_vcalloc_req_bits_vc_sel_2_5,\t// @[InputUnit.scala:170:14]\n output io_vcalloc_req_bits_vc_sel_2_6,\t// @[InputUnit.scala:170:14]\n output io_vcalloc_req_bits_vc_sel_2_7,\t// @[InputUnit.scala:170:14]\n output io_vcalloc_req_bits_vc_sel_1_1,\t// @[InputUnit.scala:170:14]\n output io_vcalloc_req_bits_vc_sel_1_2,\t// @[InputUnit.scala:170:14]\n output io_vcalloc_req_bits_vc_sel_1_3,\t// @[InputUnit.scala:170:14]\n output io_vcalloc_req_bits_vc_sel_1_4,\t// @[InputUnit.scala:170:14]\n output io_vcalloc_req_bits_vc_sel_1_5,\t// @[InputUnit.scala:170:14]\n output io_vcalloc_req_bits_vc_sel_1_6,\t// @[InputUnit.scala:170:14]\n output io_vcalloc_req_bits_vc_sel_1_7,\t// @[InputUnit.scala:170:14]\n input io_vcalloc_resp_vc_sel_2_0,\t// @[InputUnit.scala:170:14]\n input io_vcalloc_resp_vc_sel_2_1,\t// @[InputUnit.scala:170:14]\n input io_vcalloc_resp_vc_sel_2_2,\t// @[InputUnit.scala:170:14]\n input io_vcalloc_resp_vc_sel_2_3,\t// @[InputUnit.scala:170:14]\n input io_vcalloc_resp_vc_sel_2_4,\t// @[InputUnit.scala:170:14]\n input io_vcalloc_resp_vc_sel_2_5,\t// @[InputUnit.scala:170:14]\n input io_vcalloc_resp_vc_sel_2_6,\t// @[InputUnit.scala:170:14]\n input io_vcalloc_resp_vc_sel_2_7,\t// @[InputUnit.scala:170:14]\n input io_vcalloc_resp_vc_sel_1_1,\t// @[InputUnit.scala:170:14]\n input io_vcalloc_resp_vc_sel_1_2,\t// @[InputUnit.scala:170:14]\n input io_vcalloc_resp_vc_sel_1_3,\t// @[InputUnit.scala:170:14]\n input io_vcalloc_resp_vc_sel_1_4,\t// @[InputUnit.scala:170:14]\n input io_vcalloc_resp_vc_sel_1_5,\t// @[InputUnit.scala:170:14]\n input io_vcalloc_resp_vc_sel_1_6,\t// @[InputUnit.scala:170:14]\n input io_vcalloc_resp_vc_sel_1_7,\t// @[InputUnit.scala:170:14]\n input io_out_credit_available_3_2,\t// @[InputUnit.scala:170:14]\n input io_out_credit_available_3_3,\t// @[InputUnit.scala:170:14]\n input io_out_credit_available_3_4,\t// @[InputUnit.scala:170:14]\n input io_out_credit_available_3_5,\t// @[InputUnit.scala:170:14]\n input io_out_credit_available_3_6,\t// @[InputUnit.scala:170:14]\n input io_out_credit_available_3_7,\t// @[InputUnit.scala:170:14]\n input io_out_credit_available_2_0,\t// @[InputUnit.scala:170:14]\n input io_out_credit_available_2_1,\t// @[InputUnit.scala:170:14]\n input io_out_credit_available_2_2,\t// @[InputUnit.scala:170:14]\n input io_out_credit_available_2_3,\t// @[InputUnit.scala:170:14]\n input io_out_credit_available_2_4,\t// @[InputUnit.scala:170:14]\n input io_out_credit_available_2_5,\t// @[InputUnit.scala:170:14]\n input io_out_credit_available_2_6,\t// @[InputUnit.scala:170:14]\n input io_out_credit_available_2_7,\t// @[InputUnit.scala:170:14]\n input io_out_credit_available_1_1,\t// @[InputUnit.scala:170:14]\n input io_out_credit_available_1_2,\t// @[InputUnit.scala:170:14]\n input io_out_credit_available_1_3,\t// @[InputUnit.scala:170:14]\n input io_out_credit_available_1_4,\t// @[InputUnit.scala:170:14]\n input io_out_credit_available_1_5,\t// @[InputUnit.scala:170:14]\n input io_out_credit_available_1_6,\t// @[InputUnit.scala:170:14]\n input io_out_credit_available_1_7,\t// @[InputUnit.scala:170:14]\n input io_out_credit_available_0_1,\t// @[InputUnit.scala:170:14]\n input io_out_credit_available_0_2,\t// @[InputUnit.scala:170:14]\n input io_out_credit_available_0_3,\t// @[InputUnit.scala:170:14]\n input io_out_credit_available_0_4,\t// @[InputUnit.scala:170:14]\n input io_out_credit_available_0_5,\t// @[InputUnit.scala:170:14]\n input io_out_credit_available_0_6,\t// @[InputUnit.scala:170:14]\n input io_out_credit_available_0_7,\t// @[InputUnit.scala:170:14]\n input io_salloc_req_0_ready,\t// @[InputUnit.scala:170:14]\n output io_salloc_req_0_valid,\t// @[InputUnit.scala:170:14]\n output io_salloc_req_0_bits_vc_sel_3_0,\t// @[InputUnit.scala:170:14]\n output io_salloc_req_0_bits_vc_sel_3_1,\t// @[InputUnit.scala:170:14]\n output io_salloc_req_0_bits_vc_sel_3_2,\t// @[InputUnit.scala:170:14]\n output io_salloc_req_0_bits_vc_sel_3_3,\t// @[InputUnit.scala:170:14]\n output io_salloc_req_0_bits_vc_sel_3_4,\t// @[InputUnit.scala:170:14]\n output io_salloc_req_0_bits_vc_sel_3_5,\t// @[InputUnit.scala:170:14]\n output io_salloc_req_0_bits_vc_sel_3_6,\t// @[InputUnit.scala:170:14]\n output io_salloc_req_0_bits_vc_sel_3_7,\t// @[InputUnit.scala:170:14]\n output io_salloc_req_0_bits_vc_sel_2_0,\t// @[InputUnit.scala:170:14]\n output io_salloc_req_0_bits_vc_sel_2_1,\t// @[InputUnit.scala:170:14]\n output io_salloc_req_0_bits_vc_sel_2_2,\t// @[InputUnit.scala:170:14]\n output io_salloc_req_0_bits_vc_sel_2_3,\t// @[InputUnit.scala:170:14]\n output io_salloc_req_0_bits_vc_sel_2_4,\t// @[InputUnit.scala:170:14]\n output io_salloc_req_0_bits_vc_sel_2_5,\t// @[InputUnit.scala:170:14]\n output io_salloc_req_0_bits_vc_sel_2_6,\t// @[InputUnit.scala:170:14]\n output io_salloc_req_0_bits_vc_sel_2_7,\t// @[InputUnit.scala:170:14]\n output io_salloc_req_0_bits_vc_sel_1_0,\t// @[InputUnit.scala:170:14]\n output io_salloc_req_0_bits_vc_sel_1_1,\t// @[InputUnit.scala:170:14]\n output io_salloc_req_0_bits_vc_sel_1_2,\t// @[InputUnit.scala:170:14]\n output io_salloc_req_0_bits_vc_sel_1_3,\t// @[InputUnit.scala:170:14]\n output io_salloc_req_0_bits_vc_sel_1_4,\t// @[InputUnit.scala:170:14]\n output io_salloc_req_0_bits_vc_sel_1_5,\t// @[InputUnit.scala:170:14]\n output io_salloc_req_0_bits_vc_sel_1_6,\t// @[InputUnit.scala:170:14]\n output io_salloc_req_0_bits_vc_sel_1_7,\t// @[InputUnit.scala:170:14]\n output io_salloc_req_0_bits_vc_sel_0_1,\t// @[InputUnit.scala:170:14]\n output io_salloc_req_0_bits_vc_sel_0_2,\t// @[InputUnit.scala:170:14]\n output io_salloc_req_0_bits_vc_sel_0_3,\t// @[InputUnit.scala:170:14]\n output io_salloc_req_0_bits_vc_sel_0_4,\t// @[InputUnit.scala:170:14]\n output io_salloc_req_0_bits_vc_sel_0_5,\t// @[InputUnit.scala:170:14]\n output io_salloc_req_0_bits_vc_sel_0_6,\t// @[InputUnit.scala:170:14]\n output io_salloc_req_0_bits_vc_sel_0_7,\t// @[InputUnit.scala:170:14]\n output io_salloc_req_0_bits_tail,\t// @[InputUnit.scala:170:14]\n output io_out_0_valid,\t// @[InputUnit.scala:170:14]\n output io_out_0_bits_flit_head,\t// @[InputUnit.scala:170:14]\n output io_out_0_bits_flit_tail,\t// @[InputUnit.scala:170:14]\n output [72:0] io_out_0_bits_flit_payload,\t// @[InputUnit.scala:170:14]\n output [2:0] io_out_0_bits_flit_flow_vnet_id,\t// @[InputUnit.scala:170:14]\n output [4:0] io_out_0_bits_flit_flow_ingress_node,\t// @[InputUnit.scala:170:14]\n output [1:0] io_out_0_bits_flit_flow_ingress_node_id,\t// @[InputUnit.scala:170:14]\n output [4:0] io_out_0_bits_flit_flow_egress_node,\t// @[InputUnit.scala:170:14]\n output [1:0] io_out_0_bits_flit_flow_egress_node_id,\t// @[InputUnit.scala:170:14]\n output [2:0] io_out_0_bits_out_virt_channel,\t// @[InputUnit.scala:170:14]\n output [2:0] io_debug_va_stall,\t// @[InputUnit.scala:170:14]\n output [2:0] io_debug_sa_stall,\t// @[InputUnit.scala:170:14]\n input io_in_flit_0_valid,\t// @[InputUnit.scala:170:14]\n input io_in_flit_0_bits_head,\t// @[InputUnit.scala:170:14]\n input io_in_flit_0_bits_tail,\t// @[InputUnit.scala:170:14]\n input [72:0] io_in_flit_0_bits_payload,\t// @[InputUnit.scala:170:14]\n input [2:0] io_in_flit_0_bits_flow_vnet_id,\t// @[InputUnit.scala:170:14]\n input [4:0] io_in_flit_0_bits_flow_ingress_node,\t// @[InputUnit.scala:170:14]\n input [1:0] io_in_flit_0_bits_flow_ingress_node_id,\t// @[InputUnit.scala:170:14]\n input [4:0] io_in_flit_0_bits_flow_egress_node,\t// @[InputUnit.scala:170:14]\n input [1:0] io_in_flit_0_bits_flow_egress_node_id,\t// @[InputUnit.scala:170:14]\n input [2:0] io_in_flit_0_bits_virt_channel_id,\t// @[InputUnit.scala:170:14]\n output [7:0] io_in_credit_return,\t// @[InputUnit.scala:170:14]\n output [7:0] io_in_vc_free\t// @[InputUnit.scala:170:14]\n);\n\n wire vcalloc_vals_7;\t// @[InputUnit.scala:266:32]\n wire vcalloc_vals_6;\t// @[InputUnit.scala:266:32]\n wire vcalloc_vals_5;\t// @[InputUnit.scala:266:32]\n wire vcalloc_vals_4;\t// @[InputUnit.scala:266:32]\n wire vcalloc_vals_3;\t// @[InputUnit.scala:266:32]\n wire vcalloc_vals_2;\t// @[InputUnit.scala:266:32]\n wire vcalloc_vals_1;\t// @[InputUnit.scala:266:32]\n wire vcalloc_vals_0;\t// @[InputUnit.scala:266:32]\n wire _salloc_arb_io_in_0_ready;\t// @[InputUnit.scala:296:26]\n wire _salloc_arb_io_in_1_ready;\t// @[InputUnit.scala:296:26]\n wire _salloc_arb_io_in_2_ready;\t// @[InputUnit.scala:296:26]\n wire _salloc_arb_io_in_3_ready;\t// @[InputUnit.scala:296:26]\n wire _salloc_arb_io_in_4_ready;\t// @[InputUnit.scala:296:26]\n wire _salloc_arb_io_in_5_ready;\t// @[InputUnit.scala:296:26]\n wire _salloc_arb_io_in_6_ready;\t// @[InputUnit.scala:296:26]\n wire _salloc_arb_io_in_7_ready;\t// @[InputUnit.scala:296:26]\n wire _salloc_arb_io_out_0_valid;\t// @[InputUnit.scala:296:26]\n wire [7:0] _salloc_arb_io_chosen_oh_0;\t// @[InputUnit.scala:296:26]\n wire _route_arbiter_io_in_1_ready;\t// @[InputUnit.scala:187:29]\n wire _route_arbiter_io_in_2_ready;\t// @[InputUnit.scala:187:29]\n wire _route_arbiter_io_in_3_ready;\t// @[InputUnit.scala:187:29]\n wire _route_arbiter_io_in_4_ready;\t// @[InputUnit.scala:187:29]\n wire _route_arbiter_io_in_5_ready;\t// @[InputUnit.scala:187:29]\n wire _route_arbiter_io_in_6_ready;\t// @[InputUnit.scala:187:29]\n wire _route_arbiter_io_in_7_ready;\t// @[InputUnit.scala:187:29]\n wire _route_arbiter_io_out_valid;\t// @[InputUnit.scala:187:29]\n wire [2:0] _route_arbiter_io_out_bits_src_virt_id;\t// @[InputUnit.scala:187:29]\n wire _input_buffer_io_deq_0_valid;\t// @[InputUnit.scala:181:28]\n wire _input_buffer_io_deq_0_bits_head;\t// @[InputUnit.scala:181:28]\n wire _input_buffer_io_deq_0_bits_tail;\t// @[InputUnit.scala:181:28]\n wire [72:0] _input_buffer_io_deq_0_bits_payload;\t// @[InputUnit.scala:181:28]\n wire _input_buffer_io_deq_1_valid;\t// @[InputUnit.scala:181:28]\n wire _input_buffer_io_deq_1_bits_head;\t// @[InputUnit.scala:181:28]\n wire _input_buffer_io_deq_1_bits_tail;\t// @[InputUnit.scala:181:28]\n wire [72:0] _input_buffer_io_deq_1_bits_payload;\t// @[InputUnit.scala:181:28]\n wire _input_buffer_io_deq_2_valid;\t// @[InputUnit.scala:181:28]\n wire _input_buffer_io_deq_2_bits_head;\t// @[InputUnit.scala:181:28]\n wire _input_buffer_io_deq_2_bits_tail;\t// @[InputUnit.scala:181:28]\n wire [72:0] _input_buffer_io_deq_2_bits_payload;\t// @[InputUnit.scala:181:28]\n wire _input_buffer_io_deq_3_valid;\t// @[InputUnit.scala:181:28]\n wire _input_buffer_io_deq_3_bits_head;\t// @[InputUnit.scala:181:28]\n wire _input_buffer_io_deq_3_bits_tail;\t// @[InputUnit.scala:181:28]\n wire [72:0] _input_buffer_io_deq_3_bits_payload;\t// @[InputUnit.scala:181:28]\n wire _input_buffer_io_deq_4_valid;\t// @[InputUnit.scala:181:28]\n wire _input_buffer_io_deq_4_bits_head;\t// @[InputUnit.scala:181:28]\n wire _input_buffer_io_deq_4_bits_tail;\t// @[InputUnit.scala:181:28]\n wire [72:0] _input_buffer_io_deq_4_bits_payload;\t// @[InputUnit.scala:181:28]\n wire _input_buffer_io_deq_5_valid;\t// @[InputUnit.scala:181:28]\n wire _input_buffer_io_deq_5_bits_head;\t// @[InputUnit.scala:181:28]\n wire _input_buffer_io_deq_5_bits_tail;\t// @[InputUnit.scala:181:28]\n wire [72:0] _input_buffer_io_deq_5_bits_payload;\t// @[InputUnit.scala:181:28]\n wire _input_buffer_io_deq_6_valid;\t// @[InputUnit.scala:181:28]\n wire _input_buffer_io_deq_6_bits_head;\t// @[InputUnit.scala:181:28]\n wire _input_buffer_io_deq_6_bits_tail;\t// @[InputUnit.scala:181:28]\n wire [72:0] _input_buffer_io_deq_6_bits_payload;\t// @[InputUnit.scala:181:28]\n wire _input_buffer_io_deq_7_valid;\t// @[InputUnit.scala:181:28]\n wire _input_buffer_io_deq_7_bits_head;\t// @[InputUnit.scala:181:28]\n wire _input_buffer_io_deq_7_bits_tail;\t// @[InputUnit.scala:181:28]\n wire [72:0] _input_buffer_io_deq_7_bits_payload;\t// @[InputUnit.scala:181:28]\n reg [2:0] states_0_g;\t// @[InputUnit.scala:192:19]\n reg states_0_vc_sel_2_0;\t// @[InputUnit.scala:192:19]\n reg states_0_vc_sel_2_1;\t// @[InputUnit.scala:192:19]\n reg states_0_vc_sel_2_2;\t// @[InputUnit.scala:192:19]\n reg states_0_vc_sel_2_3;\t// @[InputUnit.scala:192:19]\n reg states_0_vc_sel_2_4;\t// @[InputUnit.scala:192:19]\n reg states_0_vc_sel_2_5;\t// @[InputUnit.scala:192:19]\n reg states_0_vc_sel_2_6;\t// @[InputUnit.scala:192:19]\n reg states_0_vc_sel_2_7;\t// @[InputUnit.scala:192:19]\n reg states_0_vc_sel_1_1;\t// @[InputUnit.scala:192:19]\n reg states_0_vc_sel_1_2;\t// @[InputUnit.scala:192:19]\n reg states_0_vc_sel_1_3;\t// @[InputUnit.scala:192:19]\n reg states_0_vc_sel_1_4;\t// @[InputUnit.scala:192:19]\n reg states_0_vc_sel_1_5;\t// @[InputUnit.scala:192:19]\n reg states_0_vc_sel_1_6;\t// @[InputUnit.scala:192:19]\n reg states_0_vc_sel_1_7;\t// @[InputUnit.scala:192:19]\n reg [2:0] states_0_flow_vnet_id;\t// @[InputUnit.scala:192:19]\n reg [4:0] states_0_flow_ingress_node;\t// @[InputUnit.scala:192:19]\n reg [1:0] states_0_flow_ingress_node_id;\t// @[InputUnit.scala:192:19]\n reg [4:0] states_0_flow_egress_node;\t// @[InputUnit.scala:192:19]\n reg [1:0] states_0_flow_egress_node_id;\t// @[InputUnit.scala:192:19]\n reg [2:0] states_1_g;\t// @[InputUnit.scala:192:19]\n reg states_1_vc_sel_2_0;\t// @[InputUnit.scala:192:19]\n reg states_1_vc_sel_2_1;\t// @[InputUnit.scala:192:19]\n reg states_1_vc_sel_2_2;\t// @[InputUnit.scala:192:19]\n reg states_1_vc_sel_2_3;\t// @[InputUnit.scala:192:19]\n reg states_1_vc_sel_2_4;\t// @[InputUnit.scala:192:19]\n reg states_1_vc_sel_2_5;\t// @[InputUnit.scala:192:19]\n reg states_1_vc_sel_2_6;\t// @[InputUnit.scala:192:19]\n reg states_1_vc_sel_2_7;\t// @[InputUnit.scala:192:19]\n reg states_1_vc_sel_1_1;\t// @[InputUnit.scala:192:19]\n reg states_1_vc_sel_1_2;\t// @[InputUnit.scala:192:19]\n reg states_1_vc_sel_1_3;\t// @[InputUnit.scala:192:19]\n reg states_1_vc_sel_1_4;\t// @[InputUnit.scala:192:19]\n reg states_1_vc_sel_1_5;\t// @[InputUnit.scala:192:19]\n reg states_1_vc_sel_1_6;\t// @[InputUnit.scala:192:19]\n reg states_1_vc_sel_1_7;\t// @[InputUnit.scala:192:19]\n reg [2:0] states_1_flow_vnet_id;\t// @[InputUnit.scala:192:19]\n reg [4:0] states_1_flow_ingress_node;\t// @[InputUnit.scala:192:19]\n reg [1:0] states_1_flow_ingress_node_id;\t// @[InputUnit.scala:192:19]\n reg [4:0] states_1_flow_egress_node;\t// @[InputUnit.scala:192:19]\n reg [1:0] states_1_flow_egress_node_id;\t// @[InputUnit.scala:192:19]\n reg [2:0] states_2_g;\t// @[InputUnit.scala:192:19]\n reg states_2_vc_sel_2_0;\t// @[InputUnit.scala:192:19]\n reg states_2_vc_sel_2_1;\t// @[InputUnit.scala:192:19]\n reg states_2_vc_sel_2_2;\t// @[InputUnit.scala:192:19]\n reg states_2_vc_sel_2_3;\t// @[InputUnit.scala:192:19]\n reg states_2_vc_sel_2_4;\t// @[InputUnit.scala:192:19]\n reg states_2_vc_sel_2_5;\t// @[InputUnit.scala:192:19]\n reg states_2_vc_sel_2_6;\t// @[InputUnit.scala:192:19]\n reg states_2_vc_sel_2_7;\t// @[InputUnit.scala:192:19]\n reg states_2_vc_sel_1_1;\t// @[InputUnit.scala:192:19]\n reg states_2_vc_sel_1_2;\t// @[InputUnit.scala:192:19]\n reg states_2_vc_sel_1_3;\t// @[InputUnit.scala:192:19]\n reg states_2_vc_sel_1_4;\t// @[InputUnit.scala:192:19]\n reg states_2_vc_sel_1_5;\t// @[InputUnit.scala:192:19]\n reg states_2_vc_sel_1_6;\t// @[InputUnit.scala:192:19]\n reg states_2_vc_sel_1_7;\t// @[InputUnit.scala:192:19]\n reg [2:0] states_2_flow_vnet_id;\t// @[InputUnit.scala:192:19]\n reg [4:0] states_2_flow_ingress_node;\t// @[InputUnit.scala:192:19]\n reg [1:0] states_2_flow_ingress_node_id;\t// @[InputUnit.scala:192:19]\n reg [4:0] states_2_flow_egress_node;\t// @[InputUnit.scala:192:19]\n reg [1:0] states_2_flow_egress_node_id;\t// @[InputUnit.scala:192:19]\n reg [2:0] states_3_g;\t// @[InputUnit.scala:192:19]\n reg states_3_vc_sel_2_0;\t// @[InputUnit.scala:192:19]\n reg states_3_vc_sel_2_1;\t// @[InputUnit.scala:192:19]\n reg states_3_vc_sel_2_2;\t// @[InputUnit.scala:192:19]\n reg states_3_vc_sel_2_3;\t// @[InputUnit.scala:192:19]\n reg states_3_vc_sel_2_4;\t// @[InputUnit.scala:192:19]\n reg states_3_vc_sel_2_5;\t// @[InputUnit.scala:192:19]\n reg states_3_vc_sel_2_6;\t// @[InputUnit.scala:192:19]\n reg states_3_vc_sel_2_7;\t// @[InputUnit.scala:192:19]\n reg states_3_vc_sel_1_1;\t// @[InputUnit.scala:192:19]\n reg states_3_vc_sel_1_2;\t// @[InputUnit.scala:192:19]\n reg states_3_vc_sel_1_3;\t// @[InputUnit.scala:192:19]\n reg states_3_vc_sel_1_4;\t// @[InputUnit.scala:192:19]\n reg states_3_vc_sel_1_5;\t// @[InputUnit.scala:192:19]\n reg states_3_vc_sel_1_6;\t// @[InputUnit.scala:192:19]\n reg states_3_vc_sel_1_7;\t// @[InputUnit.scala:192:19]\n reg [2:0] states_3_flow_vnet_id;\t// @[InputUnit.scala:192:19]\n reg [4:0] states_3_flow_ingress_node;\t// @[InputUnit.scala:192:19]\n reg [1:0] states_3_flow_ingress_node_id;\t// @[InputUnit.scala:192:19]\n reg [4:0] states_3_flow_egress_node;\t// @[InputUnit.scala:192:19]\n reg [1:0] states_3_flow_egress_node_id;\t// @[InputUnit.scala:192:19]\n reg [2:0] states_4_g;\t// @[InputUnit.scala:192:19]\n reg states_4_vc_sel_2_0;\t// @[InputUnit.scala:192:19]\n reg states_4_vc_sel_2_1;\t// @[InputUnit.scala:192:19]\n reg states_4_vc_sel_2_2;\t// @[InputUnit.scala:192:19]\n reg states_4_vc_sel_2_3;\t// @[InputUnit.scala:192:19]\n reg states_4_vc_sel_2_4;\t// @[InputUnit.scala:192:19]\n reg states_4_vc_sel_2_5;\t// @[InputUnit.scala:192:19]\n reg states_4_vc_sel_2_6;\t// @[InputUnit.scala:192:19]\n reg states_4_vc_sel_2_7;\t// @[InputUnit.scala:192:19]\n reg states_4_vc_sel_1_1;\t// @[InputUnit.scala:192:19]\n reg states_4_vc_sel_1_2;\t// @[InputUnit.scala:192:19]\n reg states_4_vc_sel_1_3;\t// @[InputUnit.scala:192:19]\n reg states_4_vc_sel_1_4;\t// @[InputUnit.scala:192:19]\n reg states_4_vc_sel_1_5;\t// @[InputUnit.scala:192:19]\n reg states_4_vc_sel_1_6;\t// @[InputUnit.scala:192:19]\n reg states_4_vc_sel_1_7;\t// @[InputUnit.scala:192:19]\n reg [2:0] states_4_flow_vnet_id;\t// @[InputUnit.scala:192:19]\n reg [4:0] states_4_flow_ingress_node;\t// @[InputUnit.scala:192:19]\n reg [1:0] states_4_flow_ingress_node_id;\t// @[InputUnit.scala:192:19]\n reg [4:0] states_4_flow_egress_node;\t// @[InputUnit.scala:192:19]\n reg [1:0] states_4_flow_egress_node_id;\t// @[InputUnit.scala:192:19]\n reg [2:0] states_5_g;\t// @[InputUnit.scala:192:19]\n reg states_5_vc_sel_2_0;\t// @[InputUnit.scala:192:19]\n reg states_5_vc_sel_2_1;\t// @[InputUnit.scala:192:19]\n reg states_5_vc_sel_2_2;\t// @[InputUnit.scala:192:19]\n reg states_5_vc_sel_2_3;\t// @[InputUnit.scala:192:19]\n reg states_5_vc_sel_2_4;\t// @[InputUnit.scala:192:19]\n reg states_5_vc_sel_2_5;\t// @[InputUnit.scala:192:19]\n reg states_5_vc_sel_2_6;\t// @[InputUnit.scala:192:19]\n reg states_5_vc_sel_2_7;\t// @[InputUnit.scala:192:19]\n reg states_5_vc_sel_1_1;\t// @[InputUnit.scala:192:19]\n reg states_5_vc_sel_1_2;\t// @[InputUnit.scala:192:19]\n reg states_5_vc_sel_1_3;\t// @[InputUnit.scala:192:19]\n reg states_5_vc_sel_1_4;\t// @[InputUnit.scala:192:19]\n reg states_5_vc_sel_1_5;\t// @[InputUnit.scala:192:19]\n reg states_5_vc_sel_1_6;\t// @[InputUnit.scala:192:19]\n reg states_5_vc_sel_1_7;\t// @[InputUnit.scala:192:19]\n reg [2:0] states_5_flow_vnet_id;\t// @[InputUnit.scala:192:19]\n reg [4:0] states_5_flow_ingress_node;\t// @[InputUnit.scala:192:19]\n reg [1:0] states_5_flow_ingress_node_id;\t// @[InputUnit.scala:192:19]\n reg [4:0] states_5_flow_egress_node;\t// @[InputUnit.scala:192:19]\n reg [1:0] states_5_flow_egress_node_id;\t// @[InputUnit.scala:192:19]\n reg [2:0] states_6_g;\t// @[InputUnit.scala:192:19]\n reg states_6_vc_sel_2_0;\t// @[InputUnit.scala:192:19]\n reg states_6_vc_sel_2_1;\t// @[InputUnit.scala:192:19]\n reg states_6_vc_sel_2_2;\t// @[InputUnit.scala:192:19]\n reg states_6_vc_sel_2_3;\t// @[InputUnit.scala:192:19]\n reg states_6_vc_sel_2_4;\t// @[InputUnit.scala:192:19]\n reg states_6_vc_sel_2_5;\t// @[InputUnit.scala:192:19]\n reg states_6_vc_sel_2_6;\t// @[InputUnit.scala:192:19]\n reg states_6_vc_sel_2_7;\t// @[InputUnit.scala:192:19]\n reg states_6_vc_sel_1_1;\t// @[InputUnit.scala:192:19]\n reg states_6_vc_sel_1_2;\t// @[InputUnit.scala:192:19]\n reg states_6_vc_sel_1_3;\t// @[InputUnit.scala:192:19]\n reg states_6_vc_sel_1_4;\t// @[InputUnit.scala:192:19]\n reg states_6_vc_sel_1_5;\t// @[InputUnit.scala:192:19]\n reg states_6_vc_sel_1_6;\t// @[InputUnit.scala:192:19]\n reg states_6_vc_sel_1_7;\t// @[InputUnit.scala:192:19]\n reg [2:0] states_6_flow_vnet_id;\t// @[InputUnit.scala:192:19]\n reg [4:0] states_6_flow_ingress_node;\t// @[InputUnit.scala:192:19]\n reg [1:0] states_6_flow_ingress_node_id;\t// @[InputUnit.scala:192:19]\n reg [4:0] states_6_flow_egress_node;\t// @[InputUnit.scala:192:19]\n reg [1:0] states_6_flow_egress_node_id;\t// @[InputUnit.scala:192:19]\n reg [2:0] states_7_g;\t// @[InputUnit.scala:192:19]\n reg states_7_vc_sel_2_0;\t// @[InputUnit.scala:192:19]\n reg states_7_vc_sel_2_1;\t// @[InputUnit.scala:192:19]\n reg states_7_vc_sel_2_2;\t// @[InputUnit.scala:192:19]\n reg states_7_vc_sel_2_3;\t// @[InputUnit.scala:192:19]\n reg states_7_vc_sel_2_4;\t// @[InputUnit.scala:192:19]\n reg states_7_vc_sel_2_5;\t// @[InputUnit.scala:192:19]\n reg states_7_vc_sel_2_6;\t// @[InputUnit.scala:192:19]\n reg states_7_vc_sel_2_7;\t// @[InputUnit.scala:192:19]\n reg states_7_vc_sel_1_1;\t// @[InputUnit.scala:192:19]\n reg states_7_vc_sel_1_2;\t// @[InputUnit.scala:192:19]\n reg states_7_vc_sel_1_3;\t// @[InputUnit.scala:192:19]\n reg states_7_vc_sel_1_4;\t// @[InputUnit.scala:192:19]\n reg states_7_vc_sel_1_5;\t// @[InputUnit.scala:192:19]\n reg states_7_vc_sel_1_6;\t// @[InputUnit.scala:192:19]\n reg states_7_vc_sel_1_7;\t// @[InputUnit.scala:192:19]\n reg [2:0] states_7_flow_vnet_id;\t// @[InputUnit.scala:192:19]\n reg [4:0] states_7_flow_ingress_node;\t// @[InputUnit.scala:192:19]\n reg [1:0] states_7_flow_ingress_node_id;\t// @[InputUnit.scala:192:19]\n reg [4:0] states_7_flow_egress_node;\t// @[InputUnit.scala:192:19]\n reg [1:0] states_7_flow_egress_node_id;\t// @[InputUnit.scala:192:19]\n wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head;\t// @[InputUnit.scala:205:30]\n wire route_arbiter_io_in_0_valid = states_0_g == 3'h1;\t// @[InputUnit.scala:192:19, :229:22]\n wire route_arbiter_io_in_1_valid = states_1_g == 3'h1;\t// @[InputUnit.scala:192:19, :229:22]\n wire route_arbiter_io_in_2_valid = states_2_g == 3'h1;\t// @[InputUnit.scala:192:19, :229:22]\n wire route_arbiter_io_in_3_valid = states_3_g == 3'h1;\t// @[InputUnit.scala:192:19, :229:22]\n wire route_arbiter_io_in_4_valid = states_4_g == 3'h1;\t// @[InputUnit.scala:192:19, :229:22]\n wire route_arbiter_io_in_5_valid = states_5_g == 3'h1;\t// @[InputUnit.scala:192:19, :229:22]\n wire route_arbiter_io_in_6_valid = states_6_g == 3'h1;\t// @[InputUnit.scala:192:19, :229:22]\n wire route_arbiter_io_in_7_valid = states_7_g == 3'h1;\t// @[InputUnit.scala:192:19, :229:22]\n reg [7:0] mask;\t// @[InputUnit.scala:250:21]\n wire [7:0] _vcalloc_filter_T_3 = {vcalloc_vals_7, vcalloc_vals_6, vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, vcalloc_vals_2, vcalloc_vals_1, vcalloc_vals_0} & ~mask;\t// @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32]\n wire [15:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 16'h1 : _vcalloc_filter_T_3[1] ? 16'h2 : _vcalloc_filter_T_3[2] ? 16'h4 : _vcalloc_filter_T_3[3] ? 16'h8 : _vcalloc_filter_T_3[4] ? 16'h10 : _vcalloc_filter_T_3[5] ? 16'h20 : _vcalloc_filter_T_3[6] ? 16'h40 : _vcalloc_filter_T_3[7] ? 16'h80 : vcalloc_vals_0 ? 16'h100 : vcalloc_vals_1 ? 16'h200 : vcalloc_vals_2 ? 16'h400 : vcalloc_vals_3 ? 16'h800 : vcalloc_vals_4 ? 16'h1000 : vcalloc_vals_5 ? 16'h2000 : vcalloc_vals_6 ? 16'h4000 : {vcalloc_vals_7, 15'h0};\t// @[OneHot.scala:85:71]\n wire [7:0] vcalloc_sel = vcalloc_filter[7:0] | vcalloc_filter[15:8];\t// @[Mux.scala:50:70]\n wire io_vcalloc_req_valid_0 = vcalloc_vals_0 | vcalloc_vals_1 | vcalloc_vals_2 | vcalloc_vals_3 | vcalloc_vals_4 | vcalloc_vals_5 | vcalloc_vals_6 | vcalloc_vals_7;\t// @[package.scala:81:59]\n assign vcalloc_vals_0 = states_0_g == 3'h2;\t// @[InputUnit.scala:192:19, :266:32]\n assign vcalloc_vals_1 = states_1_g == 3'h2;\t// @[InputUnit.scala:192:19, :266:32]\n assign vcalloc_vals_2 = states_2_g == 3'h2;\t// @[InputUnit.scala:192:19, :266:32]\n assign vcalloc_vals_3 = states_3_g == 3'h2;\t// @[InputUnit.scala:192:19, :266:32]\n assign vcalloc_vals_4 = states_4_g == 3'h2;\t// @[InputUnit.scala:192:19, :266:32]\n assign vcalloc_vals_5 = states_5_g == 3'h2;\t// @[InputUnit.scala:192:19, :266:32]\n assign vcalloc_vals_6 = states_6_g == 3'h2;\t// @[InputUnit.scala:192:19, :266:32]\n assign vcalloc_vals_7 = states_7_g == 3'h2;\t// @[InputUnit.scala:192:19, :266:32]\n wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0;\t// @[Decoupled.scala:51:35]\n wire _GEN_1 = _GEN_0 & vcalloc_sel[0];\t// @[Mux.scala:32:36]\n wire _GEN_2 = _GEN_0 & vcalloc_sel[1];\t// @[Mux.scala:32:36]\n wire _GEN_3 = _GEN_0 & vcalloc_sel[2];\t// @[Mux.scala:32:36]\n wire _GEN_4 = _GEN_0 & vcalloc_sel[3];\t// @[Mux.scala:32:36]\n wire _GEN_5 = _GEN_0 & vcalloc_sel[4];\t// @[Mux.scala:32:36]\n wire _GEN_6 = _GEN_0 & vcalloc_sel[5];\t// @[Mux.scala:32:36]\n wire _GEN_7 = _GEN_0 & vcalloc_sel[6];\t// @[Mux.scala:32:36]\n wire _GEN_8 = _GEN_0 & vcalloc_sel[7];\t// @[Mux.scala:32:36]"}}},{"rowIdx":34391,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module MacUnit_212 : \n input clock : Clock \n input reset : Reset \n output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} \n\n\n node _io_out_d_T = mul(io.in_a, io.in_b) \n node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) \n node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) \n node _io_out_d_T_3 = asSInt(_io_out_d_T_2) \n connect io.out_d, _io_out_d_T_3"},"response":{"kind":"string","value":"module MacUnit_212(\t// @[PE.scala:14:7]\n input clock,\t// @[PE.scala:14:7]\n input reset,\t// @[PE.scala:14:7]\n input [7:0] io_in_a,\t// @[PE.scala:16:14]\n input [7:0] io_in_b,\t// @[PE.scala:16:14]\n input [19:0] io_in_c,\t// @[PE.scala:16:14]\n output [19:0] io_out_d\t// @[PE.scala:16:14]\n);\n\n wire [7:0] io_in_a_0 = io_in_a;\t// @[PE.scala:14:7]\n wire [7:0] io_in_b_0 = io_in_b;\t// @[PE.scala:14:7]\n wire [19:0] io_in_c_0 = io_in_c;\t// @[PE.scala:14:7]\n wire [19:0] _io_out_d_T_3;\t// @[Arithmetic.scala:93:54]\n wire [19:0] io_out_d_0;\t// @[PE.scala:14:7]\n wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0};\t// @[PE.scala:14:7]\n wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0};\t// @[PE.scala:14:7]\n wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0];\t// @[Arithmetic.scala:93:54]\n assign _io_out_d_T_3 = _io_out_d_T_2;\t// @[Arithmetic.scala:93:54]\n assign io_out_d_0 = _io_out_d_T_3;\t// @[PE.scala:14:7]\n assign io_out_d = io_out_d_0;\t// @[PE.scala:14:7]\nendmodule"}}},{"rowIdx":34392,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_4 : \n output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} \n\n\n node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) \n node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) \n node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) \n node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) \n node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) \n node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) \n node _roundMagUp_T = and(roundingMode_min, io.in.sign) \n node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) \n node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) \n node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) \n node adjustedSig = shl(io.in.sig, 0) \n node doShiftSigDown1 = bits(adjustedSig, 26, 26) \n wire common_expOut : UInt<9> \n wire common_fractOut : UInt<23> \n wire common_overflow : UInt<1> \n wire common_totalUnderflow : UInt<1> \n wire common_underflow : UInt<1> \n wire common_inexact : UInt<1> \n node _roundMask_T = bits(io.in.sExp, 8, 0) \n node _roundMask_T_1 = not(_roundMask_T) \n node roundMask_msb = bits(_roundMask_T_1, 8, 8) \n node roundMask_lsbs = bits(_roundMask_T_1, 7, 0) \n node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7) \n node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0) \n node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6) \n node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0) \n node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2) \n node _roundMask_T_2 = bits(roundMask_shift, 63, 42) \n node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0) \n node _roundMask_T_4 = shl(UInt<8>(0hff), 8) \n node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4) \n node _roundMask_T_6 = shr(_roundMask_T_3, 8) \n node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) \n node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0) \n node _roundMask_T_9 = shl(_roundMask_T_8, 8) \n node _roundMask_T_10 = not(_roundMask_T_5) \n node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) \n node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) \n node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0) \n node _roundMask_T_14 = shl(_roundMask_T_13, 4) \n node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) \n node _roundMask_T_16 = shr(_roundMask_T_12, 4) \n node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) \n node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0) \n node _roundMask_T_19 = shl(_roundMask_T_18, 4) \n node _roundMask_T_20 = not(_roundMask_T_15) \n node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) \n node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) \n node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0) \n node _roundMask_T_24 = shl(_roundMask_T_23, 2) \n node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) \n node _roundMask_T_26 = shr(_roundMask_T_22, 2) \n node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) \n node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0) \n node _roundMask_T_29 = shl(_roundMask_T_28, 2) \n node _roundMask_T_30 = not(_roundMask_T_25) \n node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) \n node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) \n node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0) \n node _roundMask_T_34 = shl(_roundMask_T_33, 1) \n node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) \n node _roundMask_T_36 = shr(_roundMask_T_32, 1) \n node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) \n node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0) \n node _roundMask_T_39 = shl(_roundMask_T_38, 1) \n node _roundMask_T_40 = not(_roundMask_T_35) \n node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) \n node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) \n node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16) \n node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0) \n node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0) \n node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0) \n node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1) \n node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47) \n node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2) \n node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0) \n node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1) \n node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51) \n node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52) \n node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4) \n node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0) \n node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1) \n node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56) \n node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57) \n node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58) \n node _roundMask_T_60 = not(_roundMask_T_59) \n node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60) \n node _roundMask_T_62 = not(_roundMask_T_61) \n node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7)) \n node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6) \n node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0) \n node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3) \n node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0) \n node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0) \n node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0) \n node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1) \n node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67) \n node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2) \n node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69) \n node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0)) \n node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71) \n node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0)) \n node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1) \n node roundMask = cat(_roundMask_T_74, UInt<2>(0h3)) \n node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) \n node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) \n node _roundPosMask_T = not(shiftedRoundMask) \n node roundPosMask = and(_roundPosMask_T, roundMask) \n node _roundPosBit_T = and(adjustedSig, roundPosMask) \n node roundPosBit = orr(_roundPosBit_T) \n node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) \n node anyRoundExtra = orr(_anyRoundExtra_T) \n node anyRound = or(roundPosBit, anyRoundExtra) \n node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) \n node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) \n node _roundIncr_T_2 = and(roundMagUp, anyRound) \n node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) \n node _roundedSig_T = or(adjustedSig, roundMask) \n node _roundedSig_T_1 = shr(_roundedSig_T, 2) \n node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) \n node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) \n node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) \n node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) \n node _roundedSig_T_6 = shr(roundMask, 1) \n node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) \n node _roundedSig_T_8 = not(_roundedSig_T_7) \n node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) \n node _roundedSig_T_10 = not(roundMask) \n node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) \n node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) \n node _roundedSig_T_13 = and(roundingMode_odd, anyRound) \n node _roundedSig_T_14 = shr(roundPosMask, 1) \n node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) \n node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) \n node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) \n node _sRoundedExp_T = shr(roundedSig, 24) \n node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) \n node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1) \n node _common_expOut_T = bits(sRoundedExp, 8, 0) \n connect common_expOut, _common_expOut_T \n node _common_fractOut_T = bits(roundedSig, 23, 1) \n node _common_fractOut_T_1 = bits(roundedSig, 22, 0) \n node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1) \n connect common_fractOut, _common_fractOut_T_2 \n node _common_overflow_T = shr(sRoundedExp, 7) \n node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) \n connect common_overflow, _common_overflow_T_1 \n node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b))) \n connect common_totalUnderflow, _common_totalUnderflow_T \n node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) \n node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) \n node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) \n node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) \n node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T) \n node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) \n node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) \n node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) \n node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) \n node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) \n node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) \n node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) \n node _roundCarry_T = bits(roundedSig, 25, 25) \n node _roundCarry_T_1 = bits(roundedSig, 24, 24) \n node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1) \n node _common_underflow_T = shr(io.in.sExp, 8) \n node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) \n node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) \n node _common_underflow_T_3 = bits(roundMask, 3, 3) \n node _common_underflow_T_4 = bits(roundMask, 2, 2) \n node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4) \n node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) \n node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) \n node _common_underflow_T_8 = bits(roundMask, 4, 4) \n node _common_underflow_T_9 = bits(roundMask, 3, 3) \n node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9) \n node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) \n node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) \n node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) \n node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) \n node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) \n node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) \n node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) \n node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) \n connect common_underflow, _common_underflow_T_18 \n node _common_inexact_T = or(common_totalUnderflow, anyRound) \n connect common_inexact, _common_inexact_T \n node isNaNOut = or(io.invalidExc, io.in.isNaN) \n node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) \n node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) \n node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) \n node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) \n node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) \n node commonCase = and(_commonCase_T_2, _commonCase_T_3) \n node overflow = and(commonCase, common_overflow) \n node underflow = and(commonCase, common_underflow) \n node _inexact_T = and(commonCase, common_inexact) \n node inexact = or(overflow, _inexact_T) \n node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) \n node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) \n node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) \n node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) \n node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) \n node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) \n node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) \n node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) \n node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) \n node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) \n node _expOut_T = or(io.in.isZero, common_totalUnderflow) \n node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) \n node _expOut_T_2 = not(_expOut_T_1) \n node _expOut_T_3 = and(common_expOut, _expOut_T_2) \n node _expOut_T_4 = not(UInt<9>(0h6b)) \n node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) \n node _expOut_T_6 = not(_expOut_T_5) \n node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) \n node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) \n node _expOut_T_9 = not(_expOut_T_8) \n node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) \n node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) \n node _expOut_T_12 = not(_expOut_T_11) \n node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) \n node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) \n node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) \n node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) \n node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) \n node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) \n node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) \n node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) \n node expOut = or(_expOut_T_19, _expOut_T_20) \n node _fractOut_T = or(isNaNOut, io.in.isZero) \n node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) \n node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) \n node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) \n node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) \n node fractOut = or(_fractOut_T_3, _fractOut_T_4) \n node _io_out_T = cat(signOut, expOut) \n node _io_out_T_1 = cat(_io_out_T, fractOut) \n connect io.out, _io_out_T_1 \n node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) \n node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) \n node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) \n node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) \n connect io.exceptionFlags, _io_exceptionFlags_T_3"},"response":{"kind":"string","value":"module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_4(\t// @[RoundAnyRawFNToRecFN.scala:48:5]\n input io_invalidExc,\t// @[RoundAnyRawFNToRecFN.scala:58:16]\n input io_in_isNaN,\t// @[RoundAnyRawFNToRecFN.scala:58:16]\n input io_in_isInf,\t// @[RoundAnyRawFNToRecFN.scala:58:16]\n input io_in_isZero,\t// @[RoundAnyRawFNToRecFN.scala:58:16]\n input io_in_sign,\t// @[RoundAnyRawFNToRecFN.scala:58:16]\n input [9:0] io_in_sExp,\t// @[RoundAnyRawFNToRecFN.scala:58:16]\n input [26:0] io_in_sig,\t// @[RoundAnyRawFNToRecFN.scala:58:16]\n input [2:0] io_roundingMode,\t// @[RoundAnyRawFNToRecFN.scala:58:16]\n input io_detectTininess,\t// @[RoundAnyRawFNToRecFN.scala:58:16]\n output [32:0] io_out,\t// @[RoundAnyRawFNToRecFN.scala:58:16]\n output [4:0] io_exceptionFlags\t// @[RoundAnyRawFNToRecFN.scala:58:16]\n);\n\n wire io_invalidExc_0 = io_invalidExc;\t// @[RoundAnyRawFNToRecFN.scala:48:5]\n wire io_in_isNaN_0 = io_in_isNaN;\t// @[RoundAnyRawFNToRecFN.scala:48:5]\n wire io_in_isInf_0 = io_in_isInf;\t// @[RoundAnyRawFNToRecFN.scala:48:5]\n wire io_in_isZero_0 = io_in_isZero;\t// @[RoundAnyRawFNToRecFN.scala:48:5]\n wire io_in_sign_0 = io_in_sign;\t// @[RoundAnyRawFNToRecFN.scala:48:5]\n wire [9:0] io_in_sExp_0 = io_in_sExp;\t// @[RoundAnyRawFNToRecFN.scala:48:5]\n wire [26:0] io_in_sig_0 = io_in_sig;\t// @[RoundAnyRawFNToRecFN.scala:48:5]\n wire [2:0] io_roundingMode_0 = io_roundingMode;\t// @[RoundAnyRawFNToRecFN.scala:48:5]\n wire io_detectTininess_0 = io_detectTininess;\t// @[RoundAnyRawFNToRecFN.scala:48:5]\n wire [15:0] _roundMask_T_5 = 16'hFF;\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_4 = 16'hFF00;\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_10 = 16'hFF00;\t// @[primitives.scala:77:20]\n wire [11:0] _roundMask_T_13 = 12'hFF;\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_14 = 16'hFF0;\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_15 = 16'hF0F;\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_20 = 16'hF0F0;\t// @[primitives.scala:77:20]\n wire [13:0] _roundMask_T_23 = 14'hF0F;\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_24 = 16'h3C3C;\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_25 = 16'h3333;\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_30 = 16'hCCCC;\t// @[primitives.scala:77:20]\n wire [14:0] _roundMask_T_33 = 15'h3333;\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_34 = 16'h6666;\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_35 = 16'h5555;\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_40 = 16'hAAAA;\t// @[primitives.scala:77:20]\n wire [8:0] _expOut_T_4 = 9'h194;\t// @[RoundAnyRawFNToRecFN.scala:258:19]\n wire io_infiniteExc = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:48:5]\n wire notNaN_isSpecialInfOut = io_in_isInf_0;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :236:49]\n wire [26:0] adjustedSig = io_in_sig_0;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :114:22]\n wire _common_underflow_T_7 = io_detectTininess_0;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :222:49]\n wire [32:0] _io_out_T_1;\t// @[RoundAnyRawFNToRecFN.scala:286:33]\n wire [4:0] _io_exceptionFlags_T_3;\t// @[RoundAnyRawFNToRecFN.scala:288:66]\n wire [32:0] io_out_0;\t// @[RoundAnyRawFNToRecFN.scala:48:5]\n wire [4:0] io_exceptionFlags_0;\t// @[RoundAnyRawFNToRecFN.scala:48:5]\n wire roundingMode_near_even = io_roundingMode_0 == 3'h0;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :90:53]\n wire roundingMode_minMag = io_roundingMode_0 == 3'h1;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :91:53]\n wire roundingMode_min = io_roundingMode_0 == 3'h2;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :92:53]\n wire roundingMode_max = io_roundingMode_0 == 3'h3;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :93:53]\n wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :94:53]\n wire roundingMode_odd = io_roundingMode_0 == 3'h6;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :95:53]\n wire _roundMagUp_T = roundingMode_min & io_in_sign_0;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27]\n wire _roundMagUp_T_1 = ~io_in_sign_0;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :98:66]\n wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1;\t// @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}]\n wire roundMagUp = _roundMagUp_T | _roundMagUp_T_2;\t// @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}]\n wire doShiftSigDown1 = adjustedSig[26];\t// @[RoundAnyRawFNToRecFN.scala:114:22, :120:57]\n wire [8:0] _common_expOut_T;\t// @[RoundAnyRawFNToRecFN.scala:187:37]\n wire [8:0] common_expOut;\t// @[RoundAnyRawFNToRecFN.scala:122:31]\n wire [22:0] _common_fractOut_T_2;\t// @[RoundAnyRawFNToRecFN.scala:189:16]\n wire [22:0] common_fractOut;\t// @[RoundAnyRawFNToRecFN.scala:123:31]\n wire _common_overflow_T_1;\t// @[RoundAnyRawFNToRecFN.scala:196:50]\n wire common_overflow;\t// @[RoundAnyRawFNToRecFN.scala:124:37]\n wire _common_totalUnderflow_T;\t// @[RoundAnyRawFNToRecFN.scala:200:31]\n wire common_totalUnderflow;\t// @[RoundAnyRawFNToRecFN.scala:125:37]\n wire _common_underflow_T_18;\t// @[RoundAnyRawFNToRecFN.scala:217:40]\n wire common_underflow;\t// @[RoundAnyRawFNToRecFN.scala:126:37]\n wire _common_inexact_T;\t// @[RoundAnyRawFNToRecFN.scala:230:49]\n wire common_inexact;\t// @[RoundAnyRawFNToRecFN.scala:127:37]\n wire [8:0] _roundMask_T = io_in_sExp_0[8:0];\t// @[RoundAnyRawFNToRecFN.scala:48:5, :156:37]\n wire [8:0] _roundMask_T_1 = ~_roundMask_T;\t// @[primitives.scala:52:21]\n wire roundMask_msb = _roundMask_T_1[8];\t// @[primitives.scala:52:21, :58:25]\n wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0];\t// @[primitives.scala:52:21, :59:26]\n wire roundMask_msb_1 = roundMask_lsbs[7];\t// @[primitives.scala:58:25, :59:26]\n wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0];\t// @[primitives.scala:59:26]\n wire roundMask_msb_2 = roundMask_lsbs_1[6];\t// @[primitives.scala:58:25, :59:26]\n wire roundMask_msb_3 = roundMask_lsbs_1[6];\t// @[primitives.scala:58:25, :59:26]\n wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0];\t// @[primitives.scala:59:26]\n wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0];\t// @[primitives.scala:59:26]\n wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2);\t// @[primitives.scala:59:26, :76:56]\n wire [21:0] _roundMask_T_2 = roundMask_shift[63:42];\t// @[primitives.scala:76:56, :78:22]\n wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0];\t// @[primitives.scala:77:20, :78:22]\n wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8];\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6};\t// @[primitives.scala:77:20]\n wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0];\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0};\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00;\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11;\t// @[primitives.scala:77:20]\n wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4];\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F};\t// @[primitives.scala:77:20]\n wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0];\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0};\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0;\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21;\t// @[primitives.scala:77:20]\n wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2];\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333};\t// @[primitives.scala:77:20]\n wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0];\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0};\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC;\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31;\t// @[primitives.scala:77:20]\n wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1];\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555};\t// @[primitives.scala:77:20]\n wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0];\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0};\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA;\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41;\t// @[primitives.scala:77:20]\n wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16];\t// @[primitives.scala:77:20, :78:22]\n wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0];\t// @[primitives.scala:77:20]\n wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0];\t// @[primitives.scala:77:20]\n wire _roundMask_T_46 = _roundMask_T_45[0];\t// @[primitives.scala:77:20]\n wire _roundMask_T_47 = _roundMask_T_45[1];\t// @[primitives.scala:77:20]\n wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47};\t// @[primitives.scala:77:20]\n wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2];\t// @[primitives.scala:77:20]\n wire _roundMask_T_50 = _roundMask_T_49[0];\t// @[primitives.scala:77:20]\n wire _roundMask_T_51 = _roundMask_T_49[1];\t// @[primitives.scala:77:20]\n wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51};\t// @[primitives.scala:77:20]\n wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52};\t// @[primitives.scala:77:20]\n wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4];\t// @[primitives.scala:77:20]\n wire _roundMask_T_55 = _roundMask_T_54[0];\t// @[primitives.scala:77:20]\n wire _roundMask_T_56 = _roundMask_T_54[1];\t// @[primitives.scala:77:20]\n wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56};\t// @[primitives.scala:77:20]\n wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57};\t// @[primitives.scala:77:20]\n wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58};\t// @[primitives.scala:77:20]\n wire [21:0] _roundMask_T_60 = ~_roundMask_T_59;\t// @[primitives.scala:73:32, :77:20]\n wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60;\t// @[primitives.scala:58:25, :73:{21,32}]\n wire [21:0] _roundMask_T_62 = ~_roundMask_T_61;\t// @[primitives.scala:73:{17,21}]\n wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7};\t// @[primitives.scala:68:58, :73:17]\n wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3);\t// @[primitives.scala:59:26, :76:56]\n wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0];\t// @[primitives.scala:76:56, :78:22]\n wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0];\t// @[primitives.scala:77:20, :78:22]\n wire _roundMask_T_66 = _roundMask_T_65[0];\t// @[primitives.scala:77:20]\n wire _roundMask_T_67 = _roundMask_T_65[1];\t// @[primitives.scala:77:20]\n wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67};\t// @[primitives.scala:77:20]\n wire _roundMask_T_69 = _roundMask_T_64[2];\t// @[primitives.scala:77:20, :78:22]\n wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69};\t// @[primitives.scala:77:20]\n wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0;\t// @[primitives.scala:58:25, :62:24, :77:20]\n wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71};\t// @[primitives.scala:58:25, :62:24, :67:24, :68:58]\n wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0;\t// @[primitives.scala:58:25, :62:24, :67:24]\n wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1};\t// @[primitives.scala:62:24]\n wire [26:0] roundMask = {_roundMask_T_74, 2'h3};\t// @[RoundAnyRawFNToRecFN.scala:159:{23,42}]\n wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask};\t// @[RoundAnyRawFNToRecFN.scala:159:42, :162:41]\n wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1];\t// @[RoundAnyRawFNToRecFN.scala:162:{41,53}]\n wire [26:0] _roundPosMask_T = ~shiftedRoundMask;\t// @[RoundAnyRawFNToRecFN.scala:162:53, :163:28]\n wire [26:0] roundPosMask = _roundPosMask_T & roundMask;\t// @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}]\n wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask;\t// @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40]\n wire roundPosBit = |_roundPosBit_T;\t// @[RoundAnyRawFNToRecFN.scala:164:{40,56}]\n wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask;\t// @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42]\n wire anyRoundExtra = |_anyRoundExtra_T;\t// @[RoundAnyRawFNToRecFN.scala:165:{42,62}]\n wire anyRound = roundPosBit | anyRoundExtra;\t// @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36]\n wire _GEN = roundingMode_near_even | roundingMode_near_maxMag;\t// @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38]\n wire _roundIncr_T;\t// @[RoundAnyRawFNToRecFN.scala:169:38]\n assign _roundIncr_T = _GEN;\t// @[RoundAnyRawFNToRecFN.scala:169:38]\n wire _unboundedRange_roundIncr_T;\t// @[RoundAnyRawFNToRecFN.scala:207:38]\n assign _unboundedRange_roundIncr_T = _GEN;\t// @[RoundAnyRawFNToRecFN.scala:169:38, :207:38]\n wire _overflow_roundMagUp_T;\t// @[RoundAnyRawFNToRecFN.scala:243:32]\n assign _overflow_roundMagUp_T = _GEN;\t// @[RoundAnyRawFNToRecFN.scala:169:38, :243:32]\n wire _roundIncr_T_1 = _roundIncr_T & roundPosBit;\t// @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}]\n wire _roundIncr_T_2 = roundMagUp & anyRound;\t// @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29]\n wire roundIncr = _roundIncr_T_1 | _roundIncr_T_2;\t// @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29]\n wire [26:0] _roundedSig_T = adjustedSig | roundMask;\t// @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32]\n wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2];\t// @[RoundAnyRawFNToRecFN.scala:174:{32,44}]\n wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1;\t// @[RoundAnyRawFNToRecFN.scala:174:{44,49}]\n wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit;\t// @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49]\n wire _roundedSig_T_4 = ~anyRoundExtra;\t// @[RoundAnyRawFNToRecFN.scala:165:62, :176:30]\n wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4;\t// @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30]\n wire [25:0] _roundedSig_T_6 = roundMask[26:1];\t// @[RoundAnyRawFNToRecFN.scala:159:42, :177:35]\n wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0;\t// @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35]\n wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7;\t// @[RoundAnyRawFNToRecFN.scala:175:{21,25}]\n wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8;\t// @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21]\n wire [26:0] _roundedSig_T_10 = ~roundMask;\t// @[RoundAnyRawFNToRecFN.scala:159:42, :180:32]\n wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10;\t// @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}]\n wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2];\t// @[RoundAnyRawFNToRecFN.scala:180:{30,43}]\n wire _roundedSig_T_13 = roundingMode_odd & anyRound;\t// @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42]\n wire [25:0] _roundedSig_T_14 = roundPosMask[26:1];\t// @[RoundAnyRawFNToRecFN.scala:163:46, :181:67]\n wire [25:0] _roundedSig_T_15 = _roundedSig_T_13 ? _roundedSig_T_14 : 26'h0;\t// @[RoundAnyRawFNToRecFN.scala:181:{24,42,67}]\n wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} | _roundedSig_T_15;\t// @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24]\n wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16;\t// @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47]\n wire [1:0] _sRoundedExp_T = roundedSig[25:24];\t// @[RoundAnyRawFNToRecFN.scala:173:16, :185:54]\n wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T};\t// @[RoundAnyRawFNToRecFN.scala:185:{54,76}]\n wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1};\t// @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}]\n assign _common_expOut_T = sRoundedExp[8:0];\t// @[RoundAnyRawFNToRecFN.scala:185:40, :187:37]\n assign common_expOut = _common_expOut_T;\t// @[RoundAnyRawFNToRecFN.scala:122:31, :187:37]\n wire [22:0] _common_fractOut_T = roundedSig[23:1];\t// @[RoundAnyRawFNToRecFN.scala:173:16, :190:27]\n wire [22:0] _common_fractOut_T_1 = roundedSig[22:0];\t// @[RoundAnyRawFNToRecFN.scala:173:16, :191:27]\n assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1;\t// @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27]\n assign common_fractOut = _common_fractOut_T_2;\t// @[RoundAnyRawFNToRecFN.scala:123:31, :189:16]\n wire [3:0] _common_overflow_T = sRoundedExp[10:7];\t// @[RoundAnyRawFNToRecFN.scala:185:40, :196:30]\n assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2;\t// @[RoundAnyRawFNToRecFN.scala:196:{30,50}]\n assign common_overflow = _common_overflow_T_1;\t// @[RoundAnyRawFNToRecFN.scala:124:37, :196:50]\n assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B;\t// @[RoundAnyRawFNToRecFN.scala:185:40, :200:31]\n assign common_totalUnderflow = _common_totalUnderflow_T;\t// @[RoundAnyRawFNToRecFN.scala:125:37, :200:31]\n wire _unboundedRange_roundPosBit_T = adjustedSig[2];\t// @[RoundAnyRawFNToRecFN.scala:114:22, :203:45]\n wire _unboundedRange_anyRound_T = adjustedSig[2];\t// @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44]\n wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1];\t// @[RoundAnyRawFNToRecFN.scala:114:22, :203:61]\n wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1;\t// @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}]\n wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T;\t// @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}]\n wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0];\t// @[RoundAnyRawFNToRecFN.scala:114:22, :205:63]\n wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2;\t// @[RoundAnyRawFNToRecFN.scala:205:{63,70}]\n wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3;\t// @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}]\n wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit;\t// @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}]\n wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound;\t// @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29]\n wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 | _unboundedRange_roundIncr_T_2;\t// @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29]\n wire _roundCarry_T = roundedSig[25];\t// @[RoundAnyRawFNToRecFN.scala:173:16, :212:27]\n wire _roundCarry_T_1 = roundedSig[24];\t// @[RoundAnyRawFNToRecFN.scala:173:16, :213:27]\n wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1;\t// @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27]\n wire [1:0] _common_underflow_T = io_in_sExp_0[9:8];\t// @[RoundAnyRawFNToRecFN.scala:48:5, :220:49]\n wire _common_underflow_T_1 = _common_underflow_T != 2'h1;\t// @[RoundAnyRawFNToRecFN.scala:220:{49,64}]\n wire _common_underflow_T_2 = anyRound & _common_underflow_T_1;\t// @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}]\n wire _common_underflow_T_3 = roundMask[3];\t// @[RoundAnyRawFNToRecFN.scala:159:42, :221:57]\n wire _common_underflow_T_9 = roundMask[3];\t// @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49]\n wire _common_underflow_T_4 = roundMask[2];\t// @[RoundAnyRawFNToRecFN.scala:159:42, :221:71]\n wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4;\t// @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}]\n wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5;\t// @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30]\n wire _common_underflow_T_8 = roundMask[4];\t// @[RoundAnyRawFNToRecFN.scala:159:42, :224:49]\n wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9;\t// @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49]\n wire _common_underflow_T_11 = ~_common_underflow_T_10;\t// @[RoundAnyRawFNToRecFN.scala:223:{34,39}]\n wire _common_underflow_T_12 = _common_underflow_T_7 & _common_underflow_T_11;\t// @[RoundAnyRawFNToRecFN.scala:222:{49,77}, :223:34]\n wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry;\t// @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38]\n wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit;\t// @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45]\n wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr;\t// @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}]\n wire _common_underflow_T_16 = ~_common_underflow_T_15;\t// @[RoundAnyRawFNToRecFN.scala:222:27, :227:60]\n wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16;\t// @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27]\n assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17;\t// @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76]\n assign common_underflow = _common_underflow_T_18;\t// @[RoundAnyRawFNToRecFN.scala:126:37, :217:40]\n assign _common_inexact_T = common_totalUnderflow | anyRound;\t// @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49]\n assign common_inexact = _common_inexact_T;\t// @[RoundAnyRawFNToRecFN.scala:127:37, :230:49]\n wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :235:34]\n wire _commonCase_T = ~isNaNOut;\t// @[RoundAnyRawFNToRecFN.scala:235:34, :237:22]\n wire _commonCase_T_1 = ~notNaN_isSpecialInfOut;\t// @[RoundAnyRawFNToRecFN.scala:236:49, :237:36]\n wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1;\t// @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}]\n wire _commonCase_T_3 = ~io_in_isZero_0;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :237:64]\n wire commonCase = _commonCase_T_2 & _commonCase_T_3;\t// @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}]\n wire overflow = commonCase & common_overflow;\t// @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32]\n wire underflow = commonCase & common_underflow;\t// @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32]\n wire _inexact_T = commonCase & common_inexact;\t// @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43]\n wire inexact = overflow | _inexact_T;\t// @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}]\n wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp;\t// @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}]\n wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow;\t// @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20]\n wire _pegMinNonzeroMagOut_T_1 = roundMagUp | roundingMode_odd;\t// @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60]\n wire pegMinNonzeroMagOut = _pegMinNonzeroMagOut_T & _pegMinNonzeroMagOut_T_1;\t// @[RoundAnyRawFNToRecFN.scala:245:{20,45,60}]\n wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp;\t// @[RoundAnyRawFNToRecFN.scala:243:60, :246:42]\n wire pegMaxFiniteMagOut = overflow & _pegMaxFiniteMagOut_T;\t// @[RoundAnyRawFNToRecFN.scala:238:32, :246:{39,42}]\n wire _notNaN_isInfOut_T = overflow & overflow_roundMagUp;\t// @[RoundAnyRawFNToRecFN.scala:238:32, :243:60, :248:45]\n wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T;\t// @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}]\n wire signOut = ~isNaNOut & io_in_sign_0;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22]\n wire _expOut_T = io_in_isZero_0 | common_totalUnderflow;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32]\n wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0;\t// @[RoundAnyRawFNToRecFN.scala:253:{18,32}]\n wire [8:0] _expOut_T_2 = ~_expOut_T_1;\t// @[RoundAnyRawFNToRecFN.scala:253:{14,18}]\n wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2;\t// @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14]\n wire [8:0] _expOut_T_5 = pegMinNonzeroMagOut ? 9'h194 : 9'h0;\t// @[RoundAnyRawFNToRecFN.scala:245:45, :257:18]\n wire [8:0] _expOut_T_6 = ~_expOut_T_5;\t// @[RoundAnyRawFNToRecFN.scala:257:{14,18}]\n wire [8:0] _expOut_T_7 = _expOut_T_3 & _expOut_T_6;\t// @[RoundAnyRawFNToRecFN.scala:252:24, :256:17, :257:14]\n wire [8:0] _expOut_T_8 = {1'h0, pegMaxFiniteMagOut, 7'h0};\t// @[RoundAnyRawFNToRecFN.scala:246:39, :261:18]\n wire [8:0] _expOut_T_9 = ~_expOut_T_8;\t// @[RoundAnyRawFNToRecFN.scala:261:{14,18}]\n wire [8:0] _expOut_T_10 = _expOut_T_7 & _expOut_T_9;\t// @[RoundAnyRawFNToRecFN.scala:256:17, :260:17, :261:14]\n wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0};\t// @[RoundAnyRawFNToRecFN.scala:248:32, :265:18]\n wire [8:0] _expOut_T_12 = ~_expOut_T_11;\t// @[RoundAnyRawFNToRecFN.scala:265:{14,18}]\n wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12;\t// @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14]\n wire [8:0] _expOut_T_14 = pegMinNonzeroMagOut ? 9'h6B : 9'h0;\t// @[RoundAnyRawFNToRecFN.scala:245:45, :269:16]\n wire [8:0] _expOut_T_15 = _expOut_T_13 | _expOut_T_14;\t// @[RoundAnyRawFNToRecFN.scala:264:17, :268:18, :269:16]\n wire [8:0] _expOut_T_16 = pegMaxFiniteMagOut ? 9'h17F : 9'h0;\t// @[RoundAnyRawFNToRecFN.scala:246:39, :273:16]\n wire [8:0] _expOut_T_17 = _expOut_T_15 | _expOut_T_16;\t// @[RoundAnyRawFNToRecFN.scala:268:18, :272:15, :273:16]\n wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0;\t// @[RoundAnyRawFNToRecFN.scala:248:32, :277:16]\n wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18;\t// @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16]\n wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0;\t// @[RoundAnyRawFNToRecFN.scala:235:34, :278:16]\n wire [8:0] expOut = _expOut_T_19 | _expOut_T_20;\t// @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16]\n wire _fractOut_T = isNaNOut | io_in_isZero_0;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22]\n wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow;\t// @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}]\n wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0};\t// @[RoundAnyRawFNToRecFN.scala:235:34, :281:16]\n wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut;\t// @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16]\n wire [22:0] _fractOut_T_4 = {23{pegMaxFiniteMagOut}};\t// @[RoundAnyRawFNToRecFN.scala:246:39, :284:13]\n wire [22:0] fractOut = _fractOut_T_3 | _fractOut_T_4;\t// @[RoundAnyRawFNToRecFN.scala:280:12, :283:11, :284:13]\n wire [9:0] _io_out_T = {signOut, expOut};\t// @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23]\n assign _io_out_T_1 = {_io_out_T, fractOut};\t// @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}]\n assign io_out_0 = _io_out_T_1;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :286:33]\n wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0};\t// @[RoundAnyRawFNToRecFN.scala:48:5, :288:23]\n wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow};\t// @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}]\n wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow};\t// @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}]\n assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact};\t// @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}]\n assign io_exceptionFlags_0 = _io_exceptionFlags_T_3;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :288:66]\n assign io_out = io_out_0;\t// @[RoundAnyRawFNToRecFN.scala:48:5]\n assign io_exceptionFlags = io_exceptionFlags_0;\t// @[RoundAnyRawFNToRecFN.scala:48:5]\nendmodule"}}},{"rowIdx":34393,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module IssueUnitCollapsing_3 : \n input clock : Clock \n input reset : Reset \n output io : { flip dis_uops : { flip ready : UInt<1>, valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}[2], iss_uops : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}[2], flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}}[4], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<2>, flip fu_types : UInt<1>[10][2], flip brupdate : { b1 : { resolve_mask : UInt<12>, mispredict_mask : UInt<12>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip flush_pipeline : UInt<1>, flip squash_grant : UInt<1>, flip tsc_reg : UInt<64>} \n\n\n wire _WIRE : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} \n wire _WIRE_1 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} \n connect _WIRE, io.dis_uops[0].bits \n connect _WIRE.iw_issued, UInt<1>(0h0) \n connect _WIRE.iw_issued_partial_agen, UInt<1>(0h0) \n connect _WIRE.iw_issued_partial_dgen, UInt<1>(0h0) \n connect _WIRE.iw_p1_bypass_hint, UInt<1>(0h0) \n connect _WIRE.iw_p2_bypass_hint, UInt<1>(0h0) \n connect _WIRE.iw_p3_bypass_hint, UInt<1>(0h0) \n node prs1_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, io.dis_uops[0].bits.prs1) \n node prs1_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, io.dis_uops[0].bits.prs1) \n node prs1_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, io.dis_uops[0].bits.prs1) \n node prs1_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, io.dis_uops[0].bits.prs1) \n node prs2_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, io.dis_uops[0].bits.prs2) \n node prs2_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, io.dis_uops[0].bits.prs2) \n node prs2_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, io.dis_uops[0].bits.prs2) \n node prs2_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, io.dis_uops[0].bits.prs2) \n node prs3_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, io.dis_uops[0].bits.prs3) \n node prs3_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, io.dis_uops[0].bits.prs3) \n node prs3_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, io.dis_uops[0].bits.prs3) \n node prs3_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, io.dis_uops[0].bits.prs3) \n node prs1_wakeups_0 = and(io.wakeup_ports[0].valid, prs1_matches_0) \n node prs1_wakeups_1 = and(io.wakeup_ports[1].valid, prs1_matches_1) \n node prs1_wakeups_2 = and(io.wakeup_ports[2].valid, prs1_matches_2) \n node prs1_wakeups_3 = and(io.wakeup_ports[3].valid, prs1_matches_3) \n node prs2_wakeups_0 = and(io.wakeup_ports[0].valid, prs2_matches_0) \n node prs2_wakeups_1 = and(io.wakeup_ports[1].valid, prs2_matches_1) \n node prs2_wakeups_2 = and(io.wakeup_ports[2].valid, prs2_matches_2) \n node prs2_wakeups_3 = and(io.wakeup_ports[3].valid, prs2_matches_3) \n node prs3_wakeups_0 = and(io.wakeup_ports[0].valid, prs3_matches_0) \n node prs3_wakeups_1 = and(io.wakeup_ports[1].valid, prs3_matches_1) \n node prs3_wakeups_2 = and(io.wakeup_ports[2].valid, prs3_matches_2) \n node prs3_wakeups_3 = and(io.wakeup_ports[3].valid, prs3_matches_3) \n node prs1_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0) \n node prs1_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1) \n node prs1_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs1_matches_2) \n node prs1_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs1_matches_3) \n node prs2_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0) \n node prs2_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1) \n node prs2_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs2_matches_2) \n node prs2_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs2_matches_3) \n node _T = or(prs1_wakeups_0, prs1_wakeups_1) \n node _T_1 = or(_T, prs1_wakeups_2) \n node _T_2 = or(_T_1, prs1_wakeups_3) \n when _T_2 : \n connect _WIRE.prs1_busy, UInt<1>(0h0) \n node _T_3 = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) \n node _T_4 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) \n node _T_5 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0)) \n node _T_6 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0)) \n node _T_7 = or(_T_3, _T_4) \n node _T_8 = or(_T_7, _T_5) \n node _T_9 = or(_T_8, _T_6) \n wire _WIRE_2 : UInt<2> \n connect _WIRE_2, _T_9 \n connect _WIRE.iw_p1_speculative_child, _WIRE_2 \n node _T_10 = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) \n node _T_11 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) \n node _T_12 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) \n node _T_13 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) \n node _T_14 = or(_T_10, _T_11) \n node _T_15 = or(_T_14, _T_12) \n node _T_16 = or(_T_15, _T_13) \n wire _WIRE_3 : UInt<1> \n connect _WIRE_3, _T_16 \n connect _WIRE.iw_p1_bypass_hint, _WIRE_3 \n node _T_17 = or(prs1_rebusys_0, prs1_rebusys_1) \n node _T_18 = or(_T_17, prs1_rebusys_2) \n node _T_19 = or(_T_18, prs1_rebusys_3) \n node _T_20 = and(io.child_rebusys, io.dis_uops[0].bits.iw_p1_speculative_child) \n node _T_21 = neq(_T_20, UInt<1>(0h0)) \n node _T_22 = or(_T_19, _T_21) \n when _T_22 : \n node _T_23 = eq(io.dis_uops[0].bits.lrs1_rtype, UInt<2>(0h0)) \n connect _WIRE.prs1_busy, _T_23 \n node _T_24 = or(prs2_wakeups_0, prs2_wakeups_1) \n node _T_25 = or(_T_24, prs2_wakeups_2) \n node _T_26 = or(_T_25, prs2_wakeups_3) \n when _T_26 : \n connect _WIRE.prs2_busy, UInt<1>(0h0) \n node _T_27 = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) \n node _T_28 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) \n node _T_29 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0)) \n node _T_30 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0)) \n node _T_31 = or(_T_27, _T_28) \n node _T_32 = or(_T_31, _T_29) \n node _T_33 = or(_T_32, _T_30) \n wire _WIRE_4 : UInt<2> \n connect _WIRE_4, _T_33 \n connect _WIRE.iw_p2_speculative_child, _WIRE_4 \n node _T_34 = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) \n node _T_35 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) \n node _T_36 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) \n node _T_37 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) \n node _T_38 = or(_T_34, _T_35) \n node _T_39 = or(_T_38, _T_36) \n node _T_40 = or(_T_39, _T_37) \n wire _WIRE_5 : UInt<1> \n connect _WIRE_5, _T_40 \n connect _WIRE.iw_p2_bypass_hint, _WIRE_5 \n node _T_41 = or(prs2_rebusys_0, prs2_rebusys_1) \n node _T_42 = or(_T_41, prs2_rebusys_2) \n node _T_43 = or(_T_42, prs2_rebusys_3) \n node _T_44 = and(io.child_rebusys, io.dis_uops[0].bits.iw_p2_speculative_child) \n node _T_45 = neq(_T_44, UInt<1>(0h0)) \n node _T_46 = or(_T_43, _T_45) \n when _T_46 : \n node _T_47 = eq(io.dis_uops[0].bits.lrs2_rtype, UInt<2>(0h0)) \n connect _WIRE.prs2_busy, _T_47 \n node _T_48 = or(prs3_wakeups_0, prs3_wakeups_1) \n node _T_49 = or(_T_48, prs3_wakeups_2) \n node _T_50 = or(_T_49, prs3_wakeups_3) \n when _T_50 : \n connect _WIRE.prs3_busy, UInt<1>(0h0) \n node _T_51 = mux(prs3_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) \n node _T_52 = mux(prs3_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) \n node _T_53 = mux(prs3_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) \n node _T_54 = mux(prs3_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) \n node _T_55 = or(_T_51, _T_52) \n node _T_56 = or(_T_55, _T_53) \n node _T_57 = or(_T_56, _T_54) \n wire _WIRE_6 : UInt<1> \n connect _WIRE_6, _T_57 \n connect _WIRE.iw_p3_bypass_hint, _WIRE_6 \n node _T_58 = eq(io.pred_wakeup_port.bits, io.dis_uops[0].bits.ppred) \n node _T_59 = and(io.pred_wakeup_port.valid, _T_58) \n when _T_59 : \n connect _WIRE.ppred_busy, UInt<1>(0h0) \n connect _WIRE_1, io.dis_uops[1].bits \n connect _WIRE_1.iw_issued, UInt<1>(0h0) \n connect _WIRE_1.iw_issued_partial_agen, UInt<1>(0h0) \n connect _WIRE_1.iw_issued_partial_dgen, UInt<1>(0h0) \n connect _WIRE_1.iw_p1_bypass_hint, UInt<1>(0h0) \n connect _WIRE_1.iw_p2_bypass_hint, UInt<1>(0h0) \n connect _WIRE_1.iw_p3_bypass_hint, UInt<1>(0h0) \n node prs1_matches_0_1 = eq(io.wakeup_ports[0].bits.uop.pdst, io.dis_uops[1].bits.prs1) \n node prs1_matches_1_1 = eq(io.wakeup_ports[1].bits.uop.pdst, io.dis_uops[1].bits.prs1) \n node prs1_matches_2_1 = eq(io.wakeup_ports[2].bits.uop.pdst, io.dis_uops[1].bits.prs1) \n node prs1_matches_3_1 = eq(io.wakeup_ports[3].bits.uop.pdst, io.dis_uops[1].bits.prs1) \n node prs2_matches_0_1 = eq(io.wakeup_ports[0].bits.uop.pdst, io.dis_uops[1].bits.prs2) \n node prs2_matches_1_1 = eq(io.wakeup_ports[1].bits.uop.pdst, io.dis_uops[1].bits.prs2) \n node prs2_matches_2_1 = eq(io.wakeup_ports[2].bits.uop.pdst, io.dis_uops[1].bits.prs2) \n node prs2_matches_3_1 = eq(io.wakeup_ports[3].bits.uop.pdst, io.dis_uops[1].bits.prs2) \n node prs3_matches_0_1 = eq(io.wakeup_ports[0].bits.uop.pdst, io.dis_uops[1].bits.prs3) \n node prs3_matches_1_1 = eq(io.wakeup_ports[1].bits.uop.pdst, io.dis_uops[1].bits.prs3) \n node prs3_matches_2_1 = eq(io.wakeup_ports[2].bits.uop.pdst, io.dis_uops[1].bits.prs3) \n node prs3_matches_3_1 = eq(io.wakeup_ports[3].bits.uop.pdst, io.dis_uops[1].bits.prs3) \n node prs1_wakeups_0_1 = and(io.wakeup_ports[0].valid, prs1_matches_0_1) \n node prs1_wakeups_1_1 = and(io.wakeup_ports[1].valid, prs1_matches_1_1) \n node prs1_wakeups_2_1 = and(io.wakeup_ports[2].valid, prs1_matches_2_1) \n node prs1_wakeups_3_1 = and(io.wakeup_ports[3].valid, prs1_matches_3_1) \n node prs2_wakeups_0_1 = and(io.wakeup_ports[0].valid, prs2_matches_0_1) \n node prs2_wakeups_1_1 = and(io.wakeup_ports[1].valid, prs2_matches_1_1) \n node prs2_wakeups_2_1 = and(io.wakeup_ports[2].valid, prs2_matches_2_1) \n node prs2_wakeups_3_1 = and(io.wakeup_ports[3].valid, prs2_matches_3_1) \n node prs3_wakeups_0_1 = and(io.wakeup_ports[0].valid, prs3_matches_0_1) \n node prs3_wakeups_1_1 = and(io.wakeup_ports[1].valid, prs3_matches_1_1) \n node prs3_wakeups_2_1 = and(io.wakeup_ports[2].valid, prs3_matches_2_1) \n node prs3_wakeups_3_1 = and(io.wakeup_ports[3].valid, prs3_matches_3_1) \n node prs1_rebusys_0_1 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0_1) \n node prs1_rebusys_1_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1_1) \n node prs1_rebusys_2_1 = and(io.wakeup_ports[2].bits.rebusy, prs1_matches_2_1) \n node prs1_rebusys_3_1 = and(io.wakeup_ports[3].bits.rebusy, prs1_matches_3_1) \n node prs2_rebusys_0_1 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0_1) \n node prs2_rebusys_1_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1_1) \n node prs2_rebusys_2_1 = and(io.wakeup_ports[2].bits.rebusy, prs2_matches_2_1) \n node prs2_rebusys_3_1 = and(io.wakeup_ports[3].bits.rebusy, prs2_matches_3_1) \n node _T_60 = or(prs1_wakeups_0_1, prs1_wakeups_1_1) \n node _T_61 = or(_T_60, prs1_wakeups_2_1) \n node _T_62 = or(_T_61, prs1_wakeups_3_1) \n when _T_62 : \n connect _WIRE_1.prs1_busy, UInt<1>(0h0) \n node _T_63 = mux(prs1_wakeups_0_1, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) \n node _T_64 = mux(prs1_wakeups_1_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) \n node _T_65 = mux(prs1_wakeups_2_1, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0)) \n node _T_66 = mux(prs1_wakeups_3_1, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0)) \n node _T_67 = or(_T_63, _T_64) \n node _T_68 = or(_T_67, _T_65) \n node _T_69 = or(_T_68, _T_66) \n wire _WIRE_7 : UInt<2> \n connect _WIRE_7, _T_69 \n connect _WIRE_1.iw_p1_speculative_child, _WIRE_7 \n node _T_70 = mux(prs1_wakeups_0_1, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) \n node _T_71 = mux(prs1_wakeups_1_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) \n node _T_72 = mux(prs1_wakeups_2_1, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) \n node _T_73 = mux(prs1_wakeups_3_1, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) \n node _T_74 = or(_T_70, _T_71) \n node _T_75 = or(_T_74, _T_72) \n node _T_76 = or(_T_75, _T_73) \n wire _WIRE_8 : UInt<1> \n connect _WIRE_8, _T_76 \n connect _WIRE_1.iw_p1_bypass_hint, _WIRE_8 \n node _T_77 = or(prs1_rebusys_0_1, prs1_rebusys_1_1) \n node _T_78 = or(_T_77, prs1_rebusys_2_1) \n node _T_79 = or(_T_78, prs1_rebusys_3_1) \n node _T_80 = and(io.child_rebusys, io.dis_uops[1].bits.iw_p1_speculative_child) \n node _T_81 = neq(_T_80, UInt<1>(0h0)) \n node _T_82 = or(_T_79, _T_81) \n when _T_82 : \n node _T_83 = eq(io.dis_uops[1].bits.lrs1_rtype, UInt<2>(0h0)) \n connect _WIRE_1.prs1_busy, _T_83 \n node _T_84 = or(prs2_wakeups_0_1, prs2_wakeups_1_1) \n node _T_85 = or(_T_84, prs2_wakeups_2_1) \n node _T_86 = or(_T_85, prs2_wakeups_3_1) \n when _T_86 : \n connect _WIRE_1.prs2_busy, UInt<1>(0h0) \n node _T_87 = mux(prs2_wakeups_0_1, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) \n node _T_88 = mux(prs2_wakeups_1_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) \n node _T_89 = mux(prs2_wakeups_2_1, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0)) \n node _T_90 = mux(prs2_wakeups_3_1, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0)) \n node _T_91 = or(_T_87, _T_88) \n node _T_92 = or(_T_91, _T_89) \n node _T_93 = or(_T_92, _T_90) \n wire _WIRE_9 : UInt<2> \n connect _WIRE_9, _T_93 \n connect _WIRE_1.iw_p2_speculative_child, _WIRE_9 \n node _T_94 = mux(prs2_wakeups_0_1, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) \n node _T_95 = mux(prs2_wakeups_1_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) \n node _T_96 = mux(prs2_wakeups_2_1, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) \n node _T_97 = mux(prs2_wakeups_3_1, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) \n node _T_98 = or(_T_94, _T_95) \n node _T_99 = or(_T_98, _T_96) \n node _T_100 = or(_T_99, _T_97) \n wire _WIRE_10 : UInt<1> \n connect _WIRE_10, _T_100 \n connect _WIRE_1.iw_p2_bypass_hint, _WIRE_10 \n node _T_101 = or(prs2_rebusys_0_1, prs2_rebusys_1_1) \n node _T_102 = or(_T_101, prs2_rebusys_2_1) \n node _T_103 = or(_T_102, prs2_rebusys_3_1) \n node _T_104 = and(io.child_rebusys, io.dis_uops[1].bits.iw_p2_speculative_child) \n node _T_105 = neq(_T_104, UInt<1>(0h0)) \n node _T_106 = or(_T_103, _T_105) \n when _T_106 : \n node _T_107 = eq(io.dis_uops[1].bits.lrs2_rtype, UInt<2>(0h0)) \n connect _WIRE_1.prs2_busy, _T_107 \n node _T_108 = or(prs3_wakeups_0_1, prs3_wakeups_1_1) \n node _T_109 = or(_T_108, prs3_wakeups_2_1) \n node _T_110 = or(_T_109, prs3_wakeups_3_1) \n when _T_110 : \n connect _WIRE_1.prs3_busy, UInt<1>(0h0) \n node _T_111 = mux(prs3_wakeups_0_1, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) \n node _T_112 = mux(prs3_wakeups_1_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) \n node _T_113 = mux(prs3_wakeups_2_1, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) \n node _T_114 = mux(prs3_wakeups_3_1, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) \n node _T_115 = or(_T_111, _T_112) \n node _T_116 = or(_T_115, _T_113) \n node _T_117 = or(_T_116, _T_114) \n wire _WIRE_11 : UInt<1> \n connect _WIRE_11, _T_117 \n connect _WIRE_1.iw_p3_bypass_hint, _WIRE_11 \n node _T_118 = eq(io.pred_wakeup_port.bits, io.dis_uops[1].bits.ppred) \n node _T_119 = and(io.pred_wakeup_port.valid, _T_118) \n when _T_119 : \n connect _WIRE_1.ppred_busy, UInt<1>(0h0) \n inst slots_0 of IssueSlot_36 \n connect slots_0.clock, clock\n\n connect slots_0.reset, reset\n\n inst slots_1 of IssueSlot_37 \n connect slots_1.clock, clock\n\n connect slots_1.reset, reset\n\n inst slots_2 of IssueSlot_38 \n connect slots_2.clock, clock\n\n connect slots_2.reset, reset\n\n inst slots_3 of IssueSlot_39 \n connect slots_3.clock, clock\n\n connect slots_3.reset, reset\n\n inst slots_4 of IssueSlot_40 \n connect slots_4.clock, clock\n\n connect slots_4.reset, reset\n\n inst slots_5 of IssueSlot_41 \n connect slots_5.clock, clock\n\n connect slots_5.reset, reset\n\n inst slots_6 of IssueSlot_42 \n connect slots_6.clock, clock\n\n connect slots_6.reset, reset\n\n inst slots_7 of IssueSlot_43 \n connect slots_7.clock, clock\n\n connect slots_7.reset, reset\n\n inst slots_8 of IssueSlot_44 \n connect slots_8.clock, clock\n\n connect slots_8.reset, reset\n\n inst slots_9 of IssueSlot_45 \n connect slots_9.clock, clock\n\n connect slots_9.reset, reset\n\n inst slots_10 of IssueSlot_46 \n connect slots_10.clock, clock\n\n connect slots_10.reset, reset\n\n inst slots_11 of IssueSlot_47 \n connect slots_11.clock, clock\n\n connect slots_11.reset, reset\n\n inst slots_12 of IssueSlot_48 \n connect slots_12.clock, clock\n\n connect slots_12.reset, reset\n\n inst slots_13 of IssueSlot_49 \n connect slots_13.clock, clock\n\n connect slots_13.reset, reset\n\n inst slots_14 of IssueSlot_50 \n connect slots_14.clock, clock\n\n connect slots_14.reset, reset\n\n inst slots_15 of IssueSlot_51 \n connect slots_15.clock, clock\n\n connect slots_15.reset, reset\n\n inst slots_16 of IssueSlot_52 \n connect slots_16.clock, clock\n\n connect slots_16.reset, reset\n\n inst slots_17 of IssueSlot_53 \n connect slots_17.clock, clock\n\n connect slots_17.reset, reset\n\n inst slots_18 of IssueSlot_54 \n connect slots_18.clock, clock\n\n connect slots_18.reset, reset\n\n inst slots_19 of IssueSlot_55 \n connect slots_19.clock, clock\n\n connect slots_19.reset, reset\n\n wire issue_slots : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, flip grant : UInt<1>, iss_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip in_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip brupdate : { b1 : { resolve_mask : UInt<12>, mispredict_mask : UInt<12>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip kill : UInt<1>, flip clear : UInt<1>, flip squash_grant : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}}[4], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<2>}[20] \n connect slots_0.io.child_rebusys, issue_slots[0].child_rebusys \n connect slots_0.io.pred_wakeup_port.bits, issue_slots[0].pred_wakeup_port.bits \n connect slots_0.io.pred_wakeup_port.valid, issue_slots[0].pred_wakeup_port.valid \n connect slots_0.io.wakeup_ports[0].bits.rebusy, issue_slots[0].wakeup_ports[0].bits.rebusy \n connect slots_0.io.wakeup_ports[0].bits.speculative_mask, issue_slots[0].wakeup_ports[0].bits.speculative_mask \n connect slots_0.io.wakeup_ports[0].bits.bypassable, issue_slots[0].wakeup_ports[0].bits.bypassable \n connect slots_0.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[0].wakeup_ports[0].bits.uop.debug_tsrc \n connect slots_0.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[0].wakeup_ports[0].bits.uop.debug_fsrc \n connect slots_0.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[0].wakeup_ports[0].bits.uop.bp_xcpt_if \n connect slots_0.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[0].wakeup_ports[0].bits.uop.bp_debug_if \n connect slots_0.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[0].wakeup_ports[0].bits.uop.xcpt_ma_if \n connect slots_0.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[0].wakeup_ports[0].bits.uop.xcpt_ae_if \n connect slots_0.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[0].wakeup_ports[0].bits.uop.xcpt_pf_if \n connect slots_0.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[0].wakeup_ports[0].bits.uop.fp_typ \n connect slots_0.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[0].wakeup_ports[0].bits.uop.fp_rm \n connect slots_0.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[0].wakeup_ports[0].bits.uop.fp_val \n connect slots_0.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[0].wakeup_ports[0].bits.uop.fcn_op \n connect slots_0.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[0].wakeup_ports[0].bits.uop.fcn_dw \n connect slots_0.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[0].wakeup_ports[0].bits.uop.frs3_en \n connect slots_0.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[0].wakeup_ports[0].bits.uop.lrs2_rtype \n connect slots_0.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[0].wakeup_ports[0].bits.uop.lrs1_rtype \n connect slots_0.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[0].wakeup_ports[0].bits.uop.dst_rtype \n connect slots_0.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[0].wakeup_ports[0].bits.uop.lrs3 \n connect slots_0.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[0].wakeup_ports[0].bits.uop.lrs2 \n connect slots_0.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[0].wakeup_ports[0].bits.uop.lrs1 \n connect slots_0.io.wakeup_ports[0].bits.uop.ldst, issue_slots[0].wakeup_ports[0].bits.uop.ldst \n connect slots_0.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[0].wakeup_ports[0].bits.uop.ldst_is_rs1 \n connect slots_0.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[0].wakeup_ports[0].bits.uop.csr_cmd \n connect slots_0.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[0].wakeup_ports[0].bits.uop.flush_on_commit \n connect slots_0.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[0].wakeup_ports[0].bits.uop.is_unique \n connect slots_0.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[0].wakeup_ports[0].bits.uop.uses_stq \n connect slots_0.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[0].wakeup_ports[0].bits.uop.uses_ldq \n connect slots_0.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[0].wakeup_ports[0].bits.uop.mem_signed \n connect slots_0.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[0].wakeup_ports[0].bits.uop.mem_size \n connect slots_0.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[0].wakeup_ports[0].bits.uop.mem_cmd \n connect slots_0.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[0].wakeup_ports[0].bits.uop.exc_cause \n connect slots_0.io.wakeup_ports[0].bits.uop.exception, issue_slots[0].wakeup_ports[0].bits.uop.exception \n connect slots_0.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[0].wakeup_ports[0].bits.uop.stale_pdst \n connect slots_0.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[0].wakeup_ports[0].bits.uop.ppred_busy \n connect slots_0.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[0].wakeup_ports[0].bits.uop.prs3_busy \n connect slots_0.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[0].wakeup_ports[0].bits.uop.prs2_busy \n connect slots_0.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[0].wakeup_ports[0].bits.uop.prs1_busy \n connect slots_0.io.wakeup_ports[0].bits.uop.ppred, issue_slots[0].wakeup_ports[0].bits.uop.ppred \n connect slots_0.io.wakeup_ports[0].bits.uop.prs3, issue_slots[0].wakeup_ports[0].bits.uop.prs3 \n connect slots_0.io.wakeup_ports[0].bits.uop.prs2, issue_slots[0].wakeup_ports[0].bits.uop.prs2 \n connect slots_0.io.wakeup_ports[0].bits.uop.prs1, issue_slots[0].wakeup_ports[0].bits.uop.prs1 \n connect slots_0.io.wakeup_ports[0].bits.uop.pdst, issue_slots[0].wakeup_ports[0].bits.uop.pdst \n connect slots_0.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[0].wakeup_ports[0].bits.uop.rxq_idx \n connect slots_0.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[0].wakeup_ports[0].bits.uop.stq_idx \n connect slots_0.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[0].wakeup_ports[0].bits.uop.ldq_idx \n connect slots_0.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[0].wakeup_ports[0].bits.uop.rob_idx \n connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.vec \n connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.wflags \n connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.sqrt \n connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.div \n connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.fma \n connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe \n connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.toint \n connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.fromint \n connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut \n connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn \n connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.swap23 \n connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.swap12 \n connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.ren3 \n connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.ren2 \n connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.ren1 \n connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.wen \n connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.ldst \n connect slots_0.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[0].wakeup_ports[0].bits.uop.op2_sel \n connect slots_0.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[0].wakeup_ports[0].bits.uop.op1_sel \n connect slots_0.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[0].wakeup_ports[0].bits.uop.imm_packed \n connect slots_0.io.wakeup_ports[0].bits.uop.pimm, issue_slots[0].wakeup_ports[0].bits.uop.pimm \n connect slots_0.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[0].wakeup_ports[0].bits.uop.imm_sel \n connect slots_0.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[0].wakeup_ports[0].bits.uop.imm_rename \n connect slots_0.io.wakeup_ports[0].bits.uop.taken, issue_slots[0].wakeup_ports[0].bits.uop.taken \n connect slots_0.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[0].wakeup_ports[0].bits.uop.pc_lob \n connect slots_0.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[0].wakeup_ports[0].bits.uop.edge_inst \n connect slots_0.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[0].wakeup_ports[0].bits.uop.ftq_idx \n connect slots_0.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[0].wakeup_ports[0].bits.uop.is_mov \n connect slots_0.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[0].wakeup_ports[0].bits.uop.is_rocc \n connect slots_0.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[0].wakeup_ports[0].bits.uop.is_sys_pc2epc \n connect slots_0.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[0].wakeup_ports[0].bits.uop.is_eret \n connect slots_0.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[0].wakeup_ports[0].bits.uop.is_amo \n connect slots_0.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[0].wakeup_ports[0].bits.uop.is_sfence \n connect slots_0.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[0].wakeup_ports[0].bits.uop.is_fencei \n connect slots_0.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[0].wakeup_ports[0].bits.uop.is_fence \n connect slots_0.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[0].wakeup_ports[0].bits.uop.is_sfb \n connect slots_0.io.wakeup_ports[0].bits.uop.br_type, issue_slots[0].wakeup_ports[0].bits.uop.br_type \n connect slots_0.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[0].wakeup_ports[0].bits.uop.br_tag \n connect slots_0.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[0].wakeup_ports[0].bits.uop.br_mask \n connect slots_0.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[0].wakeup_ports[0].bits.uop.dis_col_sel \n connect slots_0.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[0].wakeup_ports[0].bits.uop.iw_p3_bypass_hint \n connect slots_0.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[0].wakeup_ports[0].bits.uop.iw_p2_bypass_hint \n connect slots_0.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[0].wakeup_ports[0].bits.uop.iw_p1_bypass_hint \n connect slots_0.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[0].wakeup_ports[0].bits.uop.iw_p2_speculative_child \n connect slots_0.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[0].wakeup_ports[0].bits.uop.iw_p1_speculative_child \n connect slots_0.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[0].wakeup_ports[0].bits.uop.iw_issued_partial_dgen \n connect slots_0.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[0].wakeup_ports[0].bits.uop.iw_issued_partial_agen \n connect slots_0.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[0].wakeup_ports[0].bits.uop.iw_issued \n connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[0] \n connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[1] \n connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[2] \n connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[3] \n connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[4] \n connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[5] \n connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[6] \n connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[7] \n connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[8] \n connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[9] \n connect slots_0.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[0].wakeup_ports[0].bits.uop.iq_type[0] \n connect slots_0.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[0].wakeup_ports[0].bits.uop.iq_type[1] \n connect slots_0.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[0].wakeup_ports[0].bits.uop.iq_type[2] \n connect slots_0.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[0].wakeup_ports[0].bits.uop.iq_type[3] \n connect slots_0.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[0].wakeup_ports[0].bits.uop.debug_pc \n connect slots_0.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[0].wakeup_ports[0].bits.uop.is_rvc \n connect slots_0.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[0].wakeup_ports[0].bits.uop.debug_inst \n connect slots_0.io.wakeup_ports[0].bits.uop.inst, issue_slots[0].wakeup_ports[0].bits.uop.inst \n connect slots_0.io.wakeup_ports[0].valid, issue_slots[0].wakeup_ports[0].valid \n connect slots_0.io.wakeup_ports[1].bits.rebusy, issue_slots[0].wakeup_ports[1].bits.rebusy \n connect slots_0.io.wakeup_ports[1].bits.speculative_mask, issue_slots[0].wakeup_ports[1].bits.speculative_mask \n connect slots_0.io.wakeup_ports[1].bits.bypassable, issue_slots[0].wakeup_ports[1].bits.bypassable \n connect slots_0.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[0].wakeup_ports[1].bits.uop.debug_tsrc \n connect slots_0.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[0].wakeup_ports[1].bits.uop.debug_fsrc \n connect slots_0.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[0].wakeup_ports[1].bits.uop.bp_xcpt_if \n connect slots_0.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[0].wakeup_ports[1].bits.uop.bp_debug_if \n connect slots_0.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[0].wakeup_ports[1].bits.uop.xcpt_ma_if \n connect slots_0.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[0].wakeup_ports[1].bits.uop.xcpt_ae_if \n connect slots_0.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[0].wakeup_ports[1].bits.uop.xcpt_pf_if \n connect slots_0.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[0].wakeup_ports[1].bits.uop.fp_typ \n connect slots_0.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[0].wakeup_ports[1].bits.uop.fp_rm \n connect slots_0.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[0].wakeup_ports[1].bits.uop.fp_val \n connect slots_0.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[0].wakeup_ports[1].bits.uop.fcn_op \n connect slots_0.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[0].wakeup_ports[1].bits.uop.fcn_dw \n connect slots_0.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[0].wakeup_ports[1].bits.uop.frs3_en \n connect slots_0.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[0].wakeup_ports[1].bits.uop.lrs2_rtype \n connect slots_0.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[0].wakeup_ports[1].bits.uop.lrs1_rtype \n connect slots_0.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[0].wakeup_ports[1].bits.uop.dst_rtype \n connect slots_0.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[0].wakeup_ports[1].bits.uop.lrs3 \n connect slots_0.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[0].wakeup_ports[1].bits.uop.lrs2 \n connect slots_0.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[0].wakeup_ports[1].bits.uop.lrs1 \n connect slots_0.io.wakeup_ports[1].bits.uop.ldst, issue_slots[0].wakeup_ports[1].bits.uop.ldst \n connect slots_0.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[0].wakeup_ports[1].bits.uop.ldst_is_rs1 \n connect slots_0.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[0].wakeup_ports[1].bits.uop.csr_cmd \n connect slots_0.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[0].wakeup_ports[1].bits.uop.flush_on_commit \n connect slots_0.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[0].wakeup_ports[1].bits.uop.is_unique \n connect slots_0.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[0].wakeup_ports[1].bits.uop.uses_stq \n connect slots_0.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[0].wakeup_ports[1].bits.uop.uses_ldq \n connect slots_0.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[0].wakeup_ports[1].bits.uop.mem_signed \n connect slots_0.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[0].wakeup_ports[1].bits.uop.mem_size \n connect slots_0.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[0].wakeup_ports[1].bits.uop.mem_cmd \n connect slots_0.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[0].wakeup_ports[1].bits.uop.exc_cause \n connect slots_0.io.wakeup_ports[1].bits.uop.exception, issue_slots[0].wakeup_ports[1].bits.uop.exception \n connect slots_0.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[0].wakeup_ports[1].bits.uop.stale_pdst \n connect slots_0.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[0].wakeup_ports[1].bits.uop.ppred_busy \n connect slots_0.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[0].wakeup_ports[1].bits.uop.prs3_busy \n connect slots_0.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[0].wakeup_ports[1].bits.uop.prs2_busy \n connect slots_0.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[0].wakeup_ports[1].bits.uop.prs1_busy \n connect slots_0.io.wakeup_ports[1].bits.uop.ppred, issue_slots[0].wakeup_ports[1].bits.uop.ppred \n connect slots_0.io.wakeup_ports[1].bits.uop.prs3, issue_slots[0].wakeup_ports[1].bits.uop.prs3 \n connect slots_0.io.wakeup_ports[1].bits.uop.prs2, issue_slots[0].wakeup_ports[1].bits.uop.prs2 \n connect slots_0.io.wakeup_ports[1].bits.uop.prs1, issue_slots[0].wakeup_ports[1].bits.uop.prs1 \n connect slots_0.io.wakeup_ports[1].bits.uop.pdst, issue_slots[0].wakeup_ports[1].bits.uop.pdst \n connect slots_0.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[0].wakeup_ports[1].bits.uop.rxq_idx \n connect slots_0.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[0].wakeup_ports[1].bits.uop.stq_idx \n connect slots_0.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[0].wakeup_ports[1].bits.uop.ldq_idx \n connect slots_0.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[0].wakeup_ports[1].bits.uop.rob_idx \n connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.vec \n connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.wflags \n connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.sqrt \n connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.div \n connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.fma \n connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe \n connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.toint \n connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.fromint \n connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut \n connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn \n connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.swap23 \n connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.swap12 \n connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.ren3 \n connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.ren2 \n connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.ren1 \n connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.wen \n connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.ldst \n connect slots_0.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[0].wakeup_ports[1].bits.uop.op2_sel \n connect slots_0.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[0].wakeup_ports[1].bits.uop.op1_sel \n connect slots_0.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[0].wakeup_ports[1].bits.uop.imm_packed \n connect slots_0.io.wakeup_ports[1].bits.uop.pimm, issue_slots[0].wakeup_ports[1].bits.uop.pimm \n connect slots_0.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[0].wakeup_ports[1].bits.uop.imm_sel \n connect slots_0.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[0].wakeup_ports[1].bits.uop.imm_rename \n connect slots_0.io.wakeup_ports[1].bits.uop.taken, issue_slots[0].wakeup_ports[1].bits.uop.taken \n connect slots_0.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[0].wakeup_ports[1].bits.uop.pc_lob \n connect slots_0.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[0].wakeup_ports[1].bits.uop.edge_inst \n connect slots_0.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[0].wakeup_ports[1].bits.uop.ftq_idx \n connect slots_0.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[0].wakeup_ports[1].bits.uop.is_mov \n connect slots_0.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[0].wakeup_ports[1].bits.uop.is_rocc \n connect slots_0.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[0].wakeup_ports[1].bits.uop.is_sys_pc2epc \n connect slots_0.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[0].wakeup_ports[1].bits.uop.is_eret \n connect slots_0.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[0].wakeup_ports[1].bits.uop.is_amo \n connect slots_0.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[0].wakeup_ports[1].bits.uop.is_sfence \n connect slots_0.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[0].wakeup_ports[1].bits.uop.is_fencei \n connect slots_0.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[0].wakeup_ports[1].bits.uop.is_fence \n connect slots_0.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[0].wakeup_ports[1].bits.uop.is_sfb \n connect slots_0.io.wakeup_ports[1].bits.uop.br_type, issue_slots[0].wakeup_ports[1].bits.uop.br_type \n connect slots_0.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[0].wakeup_ports[1].bits.uop.br_tag \n connect slots_0.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[0].wakeup_ports[1].bits.uop.br_mask \n connect slots_0.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[0].wakeup_ports[1].bits.uop.dis_col_sel \n connect slots_0.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[0].wakeup_ports[1].bits.uop.iw_p3_bypass_hint \n connect slots_0.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[0].wakeup_ports[1].bits.uop.iw_p2_bypass_hint \n connect slots_0.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[0].wakeup_ports[1].bits.uop.iw_p1_bypass_hint \n connect slots_0.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[0].wakeup_ports[1].bits.uop.iw_p2_speculative_child \n connect slots_0.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[0].wakeup_ports[1].bits.uop.iw_p1_speculative_child \n connect slots_0.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[0].wakeup_ports[1].bits.uop.iw_issued_partial_dgen \n connect slots_0.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[0].wakeup_ports[1].bits.uop.iw_issued_partial_agen \n connect slots_0.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[0].wakeup_ports[1].bits.uop.iw_issued \n connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[0] \n connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[1] \n connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[2] \n connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[3] \n connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[4] \n connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[5] \n connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[6] \n connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[7] \n connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[8] \n connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[9] \n connect slots_0.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[0].wakeup_ports[1].bits.uop.iq_type[0] \n connect slots_0.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[0].wakeup_ports[1].bits.uop.iq_type[1] \n connect slots_0.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[0].wakeup_ports[1].bits.uop.iq_type[2] \n connect slots_0.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[0].wakeup_ports[1].bits.uop.iq_type[3] \n connect slots_0.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[0].wakeup_ports[1].bits.uop.debug_pc \n connect slots_0.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[0].wakeup_ports[1].bits.uop.is_rvc \n connect slots_0.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[0].wakeup_ports[1].bits.uop.debug_inst \n connect slots_0.io.wakeup_ports[1].bits.uop.inst, issue_slots[0].wakeup_ports[1].bits.uop.inst \n connect slots_0.io.wakeup_ports[1].valid, issue_slots[0].wakeup_ports[1].valid \n connect slots_0.io.wakeup_ports[2].bits.rebusy, issue_slots[0].wakeup_ports[2].bits.rebusy \n connect slots_0.io.wakeup_ports[2].bits.speculative_mask, issue_slots[0].wakeup_ports[2].bits.speculative_mask \n connect slots_0.io.wakeup_ports[2].bits.bypassable, issue_slots[0].wakeup_ports[2].bits.bypassable \n connect slots_0.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[0].wakeup_ports[2].bits.uop.debug_tsrc \n connect slots_0.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[0].wakeup_ports[2].bits.uop.debug_fsrc \n connect slots_0.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[0].wakeup_ports[2].bits.uop.bp_xcpt_if \n connect slots_0.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[0].wakeup_ports[2].bits.uop.bp_debug_if \n connect slots_0.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[0].wakeup_ports[2].bits.uop.xcpt_ma_if \n connect slots_0.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[0].wakeup_ports[2].bits.uop.xcpt_ae_if \n connect slots_0.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[0].wakeup_ports[2].bits.uop.xcpt_pf_if \n connect slots_0.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[0].wakeup_ports[2].bits.uop.fp_typ \n connect slots_0.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[0].wakeup_ports[2].bits.uop.fp_rm \n connect slots_0.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[0].wakeup_ports[2].bits.uop.fp_val \n connect slots_0.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[0].wakeup_ports[2].bits.uop.fcn_op \n connect slots_0.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[0].wakeup_ports[2].bits.uop.fcn_dw \n connect slots_0.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[0].wakeup_ports[2].bits.uop.frs3_en \n connect slots_0.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[0].wakeup_ports[2].bits.uop.lrs2_rtype \n connect slots_0.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[0].wakeup_ports[2].bits.uop.lrs1_rtype \n connect slots_0.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[0].wakeup_ports[2].bits.uop.dst_rtype \n connect slots_0.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[0].wakeup_ports[2].bits.uop.lrs3 \n connect slots_0.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[0].wakeup_ports[2].bits.uop.lrs2 \n connect slots_0.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[0].wakeup_ports[2].bits.uop.lrs1 \n connect slots_0.io.wakeup_ports[2].bits.uop.ldst, issue_slots[0].wakeup_ports[2].bits.uop.ldst \n connect slots_0.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[0].wakeup_ports[2].bits.uop.ldst_is_rs1 \n connect slots_0.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[0].wakeup_ports[2].bits.uop.csr_cmd \n connect slots_0.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[0].wakeup_ports[2].bits.uop.flush_on_commit \n connect slots_0.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[0].wakeup_ports[2].bits.uop.is_unique \n connect slots_0.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[0].wakeup_ports[2].bits.uop.uses_stq \n connect slots_0.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[0].wakeup_ports[2].bits.uop.uses_ldq \n connect slots_0.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[0].wakeup_ports[2].bits.uop.mem_signed \n connect slots_0.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[0].wakeup_ports[2].bits.uop.mem_size \n connect slots_0.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[0].wakeup_ports[2].bits.uop.mem_cmd \n connect slots_0.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[0].wakeup_ports[2].bits.uop.exc_cause \n connect slots_0.io.wakeup_ports[2].bits.uop.exception, issue_slots[0].wakeup_ports[2].bits.uop.exception \n connect slots_0.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[0].wakeup_ports[2].bits.uop.stale_pdst \n connect slots_0.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[0].wakeup_ports[2].bits.uop.ppred_busy \n connect slots_0.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[0].wakeup_ports[2].bits.uop.prs3_busy \n connect slots_0.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[0].wakeup_ports[2].bits.uop.prs2_busy \n connect slots_0.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[0].wakeup_ports[2].bits.uop.prs1_busy \n connect slots_0.io.wakeup_ports[2].bits.uop.ppred, issue_slots[0].wakeup_ports[2].bits.uop.ppred \n connect slots_0.io.wakeup_ports[2].bits.uop.prs3, issue_slots[0].wakeup_ports[2].bits.uop.prs3 \n connect slots_0.io.wakeup_ports[2].bits.uop.prs2, issue_slots[0].wakeup_ports[2].bits.uop.prs2 \n connect slots_0.io.wakeup_ports[2].bits.uop.prs1, issue_slots[0].wakeup_ports[2].bits.uop.prs1 \n connect slots_0.io.wakeup_ports[2].bits.uop.pdst, issue_slots[0].wakeup_ports[2].bits.uop.pdst \n connect slots_0.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[0].wakeup_ports[2].bits.uop.rxq_idx \n connect slots_0.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[0].wakeup_ports[2].bits.uop.stq_idx \n connect slots_0.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[0].wakeup_ports[2].bits.uop.ldq_idx \n connect slots_0.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[0].wakeup_ports[2].bits.uop.rob_idx \n connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.vec \n connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.wflags \n connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.sqrt \n connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.div \n connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.fma \n connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe \n connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.toint \n connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.fromint \n connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut \n connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn \n connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.swap23 \n connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.swap12 \n connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.ren3 \n connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.ren2 \n connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.ren1 \n connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.wen \n connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.ldst \n connect slots_0.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[0].wakeup_ports[2].bits.uop.op2_sel \n connect slots_0.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[0].wakeup_ports[2].bits.uop.op1_sel \n connect slots_0.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[0].wakeup_ports[2].bits.uop.imm_packed \n connect slots_0.io.wakeup_ports[2].bits.uop.pimm, issue_slots[0].wakeup_ports[2].bits.uop.pimm \n connect slots_0.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[0].wakeup_ports[2].bits.uop.imm_sel \n connect slots_0.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[0].wakeup_ports[2].bits.uop.imm_rename \n connect slots_0.io.wakeup_ports[2].bits.uop.taken, issue_slots[0].wakeup_ports[2].bits.uop.taken \n connect slots_0.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[0].wakeup_ports[2].bits.uop.pc_lob \n connect slots_0.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[0].wakeup_ports[2].bits.uop.edge_inst \n connect slots_0.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[0].wakeup_ports[2].bits.uop.ftq_idx \n connect slots_0.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[0].wakeup_ports[2].bits.uop.is_mov \n connect slots_0.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[0].wakeup_ports[2].bits.uop.is_rocc \n connect slots_0.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[0].wakeup_ports[2].bits.uop.is_sys_pc2epc \n connect slots_0.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[0].wakeup_ports[2].bits.uop.is_eret \n connect slots_0.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[0].wakeup_ports[2].bits.uop.is_amo \n connect slots_0.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[0].wakeup_ports[2].bits.uop.is_sfence \n connect slots_0.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[0].wakeup_ports[2].bits.uop.is_fencei \n connect slots_0.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[0].wakeup_ports[2].bits.uop.is_fence \n connect slots_0.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[0].wakeup_ports[2].bits.uop.is_sfb \n connect slots_0.io.wakeup_ports[2].bits.uop.br_type, issue_slots[0].wakeup_ports[2].bits.uop.br_type \n connect slots_0.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[0].wakeup_ports[2].bits.uop.br_tag \n connect slots_0.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[0].wakeup_ports[2].bits.uop.br_mask \n connect slots_0.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[0].wakeup_ports[2].bits.uop.dis_col_sel \n connect slots_0.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[0].wakeup_ports[2].bits.uop.iw_p3_bypass_hint \n connect slots_0.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[0].wakeup_ports[2].bits.uop.iw_p2_bypass_hint \n connect slots_0.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[0].wakeup_ports[2].bits.uop.iw_p1_bypass_hint \n connect slots_0.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[0].wakeup_ports[2].bits.uop.iw_p2_speculative_child \n connect slots_0.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[0].wakeup_ports[2].bits.uop.iw_p1_speculative_child \n connect slots_0.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[0].wakeup_ports[2].bits.uop.iw_issued_partial_dgen \n connect slots_0.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[0].wakeup_ports[2].bits.uop.iw_issued_partial_agen \n connect slots_0.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[0].wakeup_ports[2].bits.uop.iw_issued \n connect slots_0.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[0].wakeup_ports[2].bits.uop.fu_code[0] \n connect slots_0.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[0].wakeup_ports[2].bits.uop.fu_code[1] \n connect slots_0.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[0].wakeup_ports[2].bits.uop.fu_code[2] \n connect slots_0.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[0].wakeup_ports[2].bits.uop.fu_code[3] \n connect slots_0.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[0].wakeup_ports[2].bits.uop.fu_code[4] \n connect slots_0.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[0].wakeup_ports[2].bits.uop.fu_code[5] \n connect slots_0.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[0].wakeup_ports[2].bits.uop.fu_code[6] \n connect slots_0.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[0].wakeup_ports[2].bits.uop.fu_code[7] \n connect slots_0.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[0].wakeup_ports[2].bits.uop.fu_code[8] \n connect slots_0.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[0].wakeup_ports[2].bits.uop.fu_code[9] \n connect slots_0.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[0].wakeup_ports[2].bits.uop.iq_type[0] \n connect slots_0.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[0].wakeup_ports[2].bits.uop.iq_type[1] \n connect slots_0.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[0].wakeup_ports[2].bits.uop.iq_type[2] \n connect slots_0.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[0].wakeup_ports[2].bits.uop.iq_type[3] \n connect slots_0.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[0].wakeup_ports[2].bits.uop.debug_pc \n connect slots_0.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[0].wakeup_ports[2].bits.uop.is_rvc \n connect slots_0.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[0].wakeup_ports[2].bits.uop.debug_inst \n connect slots_0.io.wakeup_ports[2].bits.uop.inst, issue_slots[0].wakeup_ports[2].bits.uop.inst \n connect slots_0.io.wakeup_ports[2].valid, issue_slots[0].wakeup_ports[2].valid \n connect slots_0.io.wakeup_ports[3].bits.rebusy, issue_slots[0].wakeup_ports[3].bits.rebusy \n connect slots_0.io.wakeup_ports[3].bits.speculative_mask, issue_slots[0].wakeup_ports[3].bits.speculative_mask \n connect slots_0.io.wakeup_ports[3].bits.bypassable, issue_slots[0].wakeup_ports[3].bits.bypassable \n connect slots_0.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[0].wakeup_ports[3].bits.uop.debug_tsrc \n connect slots_0.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[0].wakeup_ports[3].bits.uop.debug_fsrc \n connect slots_0.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[0].wakeup_ports[3].bits.uop.bp_xcpt_if \n connect slots_0.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[0].wakeup_ports[3].bits.uop.bp_debug_if \n connect slots_0.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[0].wakeup_ports[3].bits.uop.xcpt_ma_if \n connect slots_0.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[0].wakeup_ports[3].bits.uop.xcpt_ae_if \n connect slots_0.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[0].wakeup_ports[3].bits.uop.xcpt_pf_if \n connect slots_0.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[0].wakeup_ports[3].bits.uop.fp_typ \n connect slots_0.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[0].wakeup_ports[3].bits.uop.fp_rm \n connect slots_0.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[0].wakeup_ports[3].bits.uop.fp_val \n connect slots_0.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[0].wakeup_ports[3].bits.uop.fcn_op \n connect slots_0.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[0].wakeup_ports[3].bits.uop.fcn_dw \n connect slots_0.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[0].wakeup_ports[3].bits.uop.frs3_en \n connect slots_0.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[0].wakeup_ports[3].bits.uop.lrs2_rtype \n connect slots_0.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[0].wakeup_ports[3].bits.uop.lrs1_rtype \n connect slots_0.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[0].wakeup_ports[3].bits.uop.dst_rtype \n connect slots_0.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[0].wakeup_ports[3].bits.uop.lrs3 \n connect slots_0.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[0].wakeup_ports[3].bits.uop.lrs2 \n connect slots_0.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[0].wakeup_ports[3].bits.uop.lrs1 \n connect slots_0.io.wakeup_ports[3].bits.uop.ldst, issue_slots[0].wakeup_ports[3].bits.uop.ldst \n connect slots_0.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[0].wakeup_ports[3].bits.uop.ldst_is_rs1 \n connect slots_0.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[0].wakeup_ports[3].bits.uop.csr_cmd \n connect slots_0.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[0].wakeup_ports[3].bits.uop.flush_on_commit \n connect slots_0.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[0].wakeup_ports[3].bits.uop.is_unique \n connect slots_0.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[0].wakeup_ports[3].bits.uop.uses_stq \n connect slots_0.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[0].wakeup_ports[3].bits.uop.uses_ldq \n connect slots_0.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[0].wakeup_ports[3].bits.uop.mem_signed \n connect slots_0.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[0].wakeup_ports[3].bits.uop.mem_size \n connect slots_0.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[0].wakeup_ports[3].bits.uop.mem_cmd \n connect slots_0.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[0].wakeup_ports[3].bits.uop.exc_cause \n connect slots_0.io.wakeup_ports[3].bits.uop.exception, issue_slots[0].wakeup_ports[3].bits.uop.exception \n connect slots_0.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[0].wakeup_ports[3].bits.uop.stale_pdst \n connect slots_0.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[0].wakeup_ports[3].bits.uop.ppred_busy \n connect slots_0.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[0].wakeup_ports[3].bits.uop.prs3_busy \n connect slots_0.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[0].wakeup_ports[3].bits.uop.prs2_busy \n connect slots_0.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[0].wakeup_ports[3].bits.uop.prs1_busy \n connect slots_0.io.wakeup_ports[3].bits.uop.ppred, issue_slots[0].wakeup_ports[3].bits.uop.ppred \n connect slots_0.io.wakeup_ports[3].bits.uop.prs3, issue_slots[0].wakeup_ports[3].bits.uop.prs3 \n connect slots_0.io.wakeup_ports[3].bits.uop.prs2, issue_slots[0].wakeup_ports[3].bits.uop.prs2 \n connect slots_0.io.wakeup_ports[3].bits.uop.prs1, issue_slots[0].wakeup_ports[3].bits.uop.prs1 \n connect slots_0.io.wakeup_ports[3].bits.uop.pdst, issue_slots[0].wakeup_ports[3].bits.uop.pdst \n connect slots_0.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[0].wakeup_ports[3].bits.uop.rxq_idx \n connect slots_0.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[0].wakeup_ports[3].bits.uop.stq_idx \n connect slots_0.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[0].wakeup_ports[3].bits.uop.ldq_idx \n connect slots_0.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[0].wakeup_ports[3].bits.uop.rob_idx \n connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.vec \n connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.wflags \n connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.sqrt \n connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.div \n connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.fma \n connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe \n connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.toint \n connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.fromint \n connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut \n connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn \n connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.swap23 \n connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.swap12 \n connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.ren3 \n connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.ren2 \n connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.ren1 \n connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.wen \n connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.ldst \n connect slots_0.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[0].wakeup_ports[3].bits.uop.op2_sel \n connect slots_0.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[0].wakeup_ports[3].bits.uop.op1_sel \n connect slots_0.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[0].wakeup_ports[3].bits.uop.imm_packed \n connect slots_0.io.wakeup_ports[3].bits.uop.pimm, issue_slots[0].wakeup_ports[3].bits.uop.pimm \n connect slots_0.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[0].wakeup_ports[3].bits.uop.imm_sel \n connect slots_0.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[0].wakeup_ports[3].bits.uop.imm_rename \n connect slots_0.io.wakeup_ports[3].bits.uop.taken, issue_slots[0].wakeup_ports[3].bits.uop.taken \n connect slots_0.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[0].wakeup_ports[3].bits.uop.pc_lob \n connect slots_0.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[0].wakeup_ports[3].bits.uop.edge_inst \n connect slots_0.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[0].wakeup_ports[3].bits.uop.ftq_idx \n connect slots_0.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[0].wakeup_ports[3].bits.uop.is_mov \n connect slots_0.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[0].wakeup_ports[3].bits.uop.is_rocc \n connect slots_0.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[0].wakeup_ports[3].bits.uop.is_sys_pc2epc \n connect slots_0.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[0].wakeup_ports[3].bits.uop.is_eret \n connect slots_0.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[0].wakeup_ports[3].bits.uop.is_amo \n connect slots_0.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[0].wakeup_ports[3].bits.uop.is_sfence \n connect slots_0.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[0].wakeup_ports[3].bits.uop.is_fencei \n connect slots_0.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[0].wakeup_ports[3].bits.uop.is_fence \n connect slots_0.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[0].wakeup_ports[3].bits.uop.is_sfb \n connect slots_0.io.wakeup_ports[3].bits.uop.br_type, issue_slots[0].wakeup_ports[3].bits.uop.br_type \n connect slots_0.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[0].wakeup_ports[3].bits.uop.br_tag \n connect slots_0.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[0].wakeup_ports[3].bits.uop.br_mask \n connect slots_0.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[0].wakeup_ports[3].bits.uop.dis_col_sel \n connect slots_0.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[0].wakeup_ports[3].bits.uop.iw_p3_bypass_hint \n connect slots_0.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[0].wakeup_ports[3].bits.uop.iw_p2_bypass_hint \n connect slots_0.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[0].wakeup_ports[3].bits.uop.iw_p1_bypass_hint \n connect slots_0.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[0].wakeup_ports[3].bits.uop.iw_p2_speculative_child \n connect slots_0.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[0].wakeup_ports[3].bits.uop.iw_p1_speculative_child \n connect slots_0.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[0].wakeup_ports[3].bits.uop.iw_issued_partial_dgen \n connect slots_0.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[0].wakeup_ports[3].bits.uop.iw_issued_partial_agen \n connect slots_0.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[0].wakeup_ports[3].bits.uop.iw_issued \n connect slots_0.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[0].wakeup_ports[3].bits.uop.fu_code[0] \n connect slots_0.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[0].wakeup_ports[3].bits.uop.fu_code[1] \n connect slots_0.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[0].wakeup_ports[3].bits.uop.fu_code[2] \n connect slots_0.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[0].wakeup_ports[3].bits.uop.fu_code[3] \n connect slots_0.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[0].wakeup_ports[3].bits.uop.fu_code[4] \n connect slots_0.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[0].wakeup_ports[3].bits.uop.fu_code[5] \n connect slots_0.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[0].wakeup_ports[3].bits.uop.fu_code[6] \n connect slots_0.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[0].wakeup_ports[3].bits.uop.fu_code[7] \n connect slots_0.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[0].wakeup_ports[3].bits.uop.fu_code[8] \n connect slots_0.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[0].wakeup_ports[3].bits.uop.fu_code[9] \n connect slots_0.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[0].wakeup_ports[3].bits.uop.iq_type[0] \n connect slots_0.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[0].wakeup_ports[3].bits.uop.iq_type[1] \n connect slots_0.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[0].wakeup_ports[3].bits.uop.iq_type[2] \n connect slots_0.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[0].wakeup_ports[3].bits.uop.iq_type[3] \n connect slots_0.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[0].wakeup_ports[3].bits.uop.debug_pc \n connect slots_0.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[0].wakeup_ports[3].bits.uop.is_rvc \n connect slots_0.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[0].wakeup_ports[3].bits.uop.debug_inst \n connect slots_0.io.wakeup_ports[3].bits.uop.inst, issue_slots[0].wakeup_ports[3].bits.uop.inst \n connect slots_0.io.wakeup_ports[3].valid, issue_slots[0].wakeup_ports[3].valid \n connect slots_0.io.squash_grant, issue_slots[0].squash_grant \n connect slots_0.io.clear, issue_slots[0].clear \n connect slots_0.io.kill, issue_slots[0].kill \n connect slots_0.io.brupdate.b2.target_offset, issue_slots[0].brupdate.b2.target_offset \n connect slots_0.io.brupdate.b2.jalr_target, issue_slots[0].brupdate.b2.jalr_target \n connect slots_0.io.brupdate.b2.pc_sel, issue_slots[0].brupdate.b2.pc_sel \n connect slots_0.io.brupdate.b2.cfi_type, issue_slots[0].brupdate.b2.cfi_type \n connect slots_0.io.brupdate.b2.taken, issue_slots[0].brupdate.b2.taken \n connect slots_0.io.brupdate.b2.mispredict, issue_slots[0].brupdate.b2.mispredict \n connect slots_0.io.brupdate.b2.uop.debug_tsrc, issue_slots[0].brupdate.b2.uop.debug_tsrc \n connect slots_0.io.brupdate.b2.uop.debug_fsrc, issue_slots[0].brupdate.b2.uop.debug_fsrc \n connect slots_0.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[0].brupdate.b2.uop.bp_xcpt_if \n connect slots_0.io.brupdate.b2.uop.bp_debug_if, issue_slots[0].brupdate.b2.uop.bp_debug_if \n connect slots_0.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[0].brupdate.b2.uop.xcpt_ma_if \n connect slots_0.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[0].brupdate.b2.uop.xcpt_ae_if \n connect slots_0.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[0].brupdate.b2.uop.xcpt_pf_if \n connect slots_0.io.brupdate.b2.uop.fp_typ, issue_slots[0].brupdate.b2.uop.fp_typ \n connect slots_0.io.brupdate.b2.uop.fp_rm, issue_slots[0].brupdate.b2.uop.fp_rm \n connect slots_0.io.brupdate.b2.uop.fp_val, issue_slots[0].brupdate.b2.uop.fp_val \n connect slots_0.io.brupdate.b2.uop.fcn_op, issue_slots[0].brupdate.b2.uop.fcn_op \n connect slots_0.io.brupdate.b2.uop.fcn_dw, issue_slots[0].brupdate.b2.uop.fcn_dw \n connect slots_0.io.brupdate.b2.uop.frs3_en, issue_slots[0].brupdate.b2.uop.frs3_en \n connect slots_0.io.brupdate.b2.uop.lrs2_rtype, issue_slots[0].brupdate.b2.uop.lrs2_rtype \n connect slots_0.io.brupdate.b2.uop.lrs1_rtype, issue_slots[0].brupdate.b2.uop.lrs1_rtype \n connect slots_0.io.brupdate.b2.uop.dst_rtype, issue_slots[0].brupdate.b2.uop.dst_rtype \n connect slots_0.io.brupdate.b2.uop.lrs3, issue_slots[0].brupdate.b2.uop.lrs3 \n connect slots_0.io.brupdate.b2.uop.lrs2, issue_slots[0].brupdate.b2.uop.lrs2 \n connect slots_0.io.brupdate.b2.uop.lrs1, issue_slots[0].brupdate.b2.uop.lrs1 \n connect slots_0.io.brupdate.b2.uop.ldst, issue_slots[0].brupdate.b2.uop.ldst \n connect slots_0.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[0].brupdate.b2.uop.ldst_is_rs1 \n connect slots_0.io.brupdate.b2.uop.csr_cmd, issue_slots[0].brupdate.b2.uop.csr_cmd \n connect slots_0.io.brupdate.b2.uop.flush_on_commit, issue_slots[0].brupdate.b2.uop.flush_on_commit \n connect slots_0.io.brupdate.b2.uop.is_unique, issue_slots[0].brupdate.b2.uop.is_unique \n connect slots_0.io.brupdate.b2.uop.uses_stq, issue_slots[0].brupdate.b2.uop.uses_stq \n connect slots_0.io.brupdate.b2.uop.uses_ldq, issue_slots[0].brupdate.b2.uop.uses_ldq \n connect slots_0.io.brupdate.b2.uop.mem_signed, issue_slots[0].brupdate.b2.uop.mem_signed \n connect slots_0.io.brupdate.b2.uop.mem_size, issue_slots[0].brupdate.b2.uop.mem_size \n connect slots_0.io.brupdate.b2.uop.mem_cmd, issue_slots[0].brupdate.b2.uop.mem_cmd \n connect slots_0.io.brupdate.b2.uop.exc_cause, issue_slots[0].brupdate.b2.uop.exc_cause \n connect slots_0.io.brupdate.b2.uop.exception, issue_slots[0].brupdate.b2.uop.exception \n connect slots_0.io.brupdate.b2.uop.stale_pdst, issue_slots[0].brupdate.b2.uop.stale_pdst \n connect slots_0.io.brupdate.b2.uop.ppred_busy, issue_slots[0].brupdate.b2.uop.ppred_busy \n connect slots_0.io.brupdate.b2.uop.prs3_busy, issue_slots[0].brupdate.b2.uop.prs3_busy \n connect slots_0.io.brupdate.b2.uop.prs2_busy, issue_slots[0].brupdate.b2.uop.prs2_busy \n connect slots_0.io.brupdate.b2.uop.prs1_busy, issue_slots[0].brupdate.b2.uop.prs1_busy \n connect slots_0.io.brupdate.b2.uop.ppred, issue_slots[0].brupdate.b2.uop.ppred \n connect slots_0.io.brupdate.b2.uop.prs3, issue_slots[0].brupdate.b2.uop.prs3 \n connect slots_0.io.brupdate.b2.uop.prs2, issue_slots[0].brupdate.b2.uop.prs2 \n connect slots_0.io.brupdate.b2.uop.prs1, issue_slots[0].brupdate.b2.uop.prs1 \n connect slots_0.io.brupdate.b2.uop.pdst, issue_slots[0].brupdate.b2.uop.pdst \n connect slots_0.io.brupdate.b2.uop.rxq_idx, issue_slots[0].brupdate.b2.uop.rxq_idx \n connect slots_0.io.brupdate.b2.uop.stq_idx, issue_slots[0].brupdate.b2.uop.stq_idx \n connect slots_0.io.brupdate.b2.uop.ldq_idx, issue_slots[0].brupdate.b2.uop.ldq_idx \n connect slots_0.io.brupdate.b2.uop.rob_idx, issue_slots[0].brupdate.b2.uop.rob_idx \n connect slots_0.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[0].brupdate.b2.uop.fp_ctrl.vec \n connect slots_0.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[0].brupdate.b2.uop.fp_ctrl.wflags \n connect slots_0.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[0].brupdate.b2.uop.fp_ctrl.sqrt \n connect slots_0.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[0].brupdate.b2.uop.fp_ctrl.div \n connect slots_0.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[0].brupdate.b2.uop.fp_ctrl.fma \n connect slots_0.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[0].brupdate.b2.uop.fp_ctrl.fastpipe \n connect slots_0.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[0].brupdate.b2.uop.fp_ctrl.toint \n connect slots_0.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[0].brupdate.b2.uop.fp_ctrl.fromint \n connect slots_0.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[0].brupdate.b2.uop.fp_ctrl.typeTagOut \n connect slots_0.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[0].brupdate.b2.uop.fp_ctrl.typeTagIn \n connect slots_0.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[0].brupdate.b2.uop.fp_ctrl.swap23 \n connect slots_0.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[0].brupdate.b2.uop.fp_ctrl.swap12 \n connect slots_0.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[0].brupdate.b2.uop.fp_ctrl.ren3 \n connect slots_0.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[0].brupdate.b2.uop.fp_ctrl.ren2 \n connect slots_0.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[0].brupdate.b2.uop.fp_ctrl.ren1 \n connect slots_0.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[0].brupdate.b2.uop.fp_ctrl.wen \n connect slots_0.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[0].brupdate.b2.uop.fp_ctrl.ldst \n connect slots_0.io.brupdate.b2.uop.op2_sel, issue_slots[0].brupdate.b2.uop.op2_sel \n connect slots_0.io.brupdate.b2.uop.op1_sel, issue_slots[0].brupdate.b2.uop.op1_sel \n connect slots_0.io.brupdate.b2.uop.imm_packed, issue_slots[0].brupdate.b2.uop.imm_packed \n connect slots_0.io.brupdate.b2.uop.pimm, issue_slots[0].brupdate.b2.uop.pimm \n connect slots_0.io.brupdate.b2.uop.imm_sel, issue_slots[0].brupdate.b2.uop.imm_sel \n connect slots_0.io.brupdate.b2.uop.imm_rename, issue_slots[0].brupdate.b2.uop.imm_rename \n connect slots_0.io.brupdate.b2.uop.taken, issue_slots[0].brupdate.b2.uop.taken \n connect slots_0.io.brupdate.b2.uop.pc_lob, issue_slots[0].brupdate.b2.uop.pc_lob \n connect slots_0.io.brupdate.b2.uop.edge_inst, issue_slots[0].brupdate.b2.uop.edge_inst \n connect slots_0.io.brupdate.b2.uop.ftq_idx, issue_slots[0].brupdate.b2.uop.ftq_idx \n connect slots_0.io.brupdate.b2.uop.is_mov, issue_slots[0].brupdate.b2.uop.is_mov \n connect slots_0.io.brupdate.b2.uop.is_rocc, issue_slots[0].brupdate.b2.uop.is_rocc \n connect slots_0.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[0].brupdate.b2.uop.is_sys_pc2epc \n connect slots_0.io.brupdate.b2.uop.is_eret, issue_slots[0].brupdate.b2.uop.is_eret \n connect slots_0.io.brupdate.b2.uop.is_amo, issue_slots[0].brupdate.b2.uop.is_amo \n connect slots_0.io.brupdate.b2.uop.is_sfence, issue_slots[0].brupdate.b2.uop.is_sfence \n connect slots_0.io.brupdate.b2.uop.is_fencei, issue_slots[0].brupdate.b2.uop.is_fencei \n connect slots_0.io.brupdate.b2.uop.is_fence, issue_slots[0].brupdate.b2.uop.is_fence \n connect slots_0.io.brupdate.b2.uop.is_sfb, issue_slots[0].brupdate.b2.uop.is_sfb \n connect slots_0.io.brupdate.b2.uop.br_type, issue_slots[0].brupdate.b2.uop.br_type \n connect slots_0.io.brupdate.b2.uop.br_tag, issue_slots[0].brupdate.b2.uop.br_tag \n connect slots_0.io.brupdate.b2.uop.br_mask, issue_slots[0].brupdate.b2.uop.br_mask \n connect slots_0.io.brupdate.b2.uop.dis_col_sel, issue_slots[0].brupdate.b2.uop.dis_col_sel \n connect slots_0.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[0].brupdate.b2.uop.iw_p3_bypass_hint \n connect slots_0.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[0].brupdate.b2.uop.iw_p2_bypass_hint \n connect slots_0.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[0].brupdate.b2.uop.iw_p1_bypass_hint \n connect slots_0.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[0].brupdate.b2.uop.iw_p2_speculative_child \n connect slots_0.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[0].brupdate.b2.uop.iw_p1_speculative_child \n connect slots_0.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[0].brupdate.b2.uop.iw_issued_partial_dgen \n connect slots_0.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[0].brupdate.b2.uop.iw_issued_partial_agen \n connect slots_0.io.brupdate.b2.uop.iw_issued, issue_slots[0].brupdate.b2.uop.iw_issued \n connect slots_0.io.brupdate.b2.uop.fu_code[0], issue_slots[0].brupdate.b2.uop.fu_code[0] \n connect slots_0.io.brupdate.b2.uop.fu_code[1], issue_slots[0].brupdate.b2.uop.fu_code[1] \n connect slots_0.io.brupdate.b2.uop.fu_code[2], issue_slots[0].brupdate.b2.uop.fu_code[2] \n connect slots_0.io.brupdate.b2.uop.fu_code[3], issue_slots[0].brupdate.b2.uop.fu_code[3] \n connect slots_0.io.brupdate.b2.uop.fu_code[4], issue_slots[0].brupdate.b2.uop.fu_code[4] \n connect slots_0.io.brupdate.b2.uop.fu_code[5], issue_slots[0].brupdate.b2.uop.fu_code[5] \n connect slots_0.io.brupdate.b2.uop.fu_code[6], issue_slots[0].brupdate.b2.uop.fu_code[6] \n connect slots_0.io.brupdate.b2.uop.fu_code[7], issue_slots[0].brupdate.b2.uop.fu_code[7] \n connect slots_0.io.brupdate.b2.uop.fu_code[8], issue_slots[0].brupdate.b2.uop.fu_code[8] \n connect slots_0.io.brupdate.b2.uop.fu_code[9], issue_slots[0].brupdate.b2.uop.fu_code[9] \n connect slots_0.io.brupdate.b2.uop.iq_type[0], issue_slots[0].brupdate.b2.uop.iq_type[0] \n connect slots_0.io.brupdate.b2.uop.iq_type[1], issue_slots[0].brupdate.b2.uop.iq_type[1] \n connect slots_0.io.brupdate.b2.uop.iq_type[2], issue_slots[0].brupdate.b2.uop.iq_type[2] \n connect slots_0.io.brupdate.b2.uop.iq_type[3], issue_slots[0].brupdate.b2.uop.iq_type[3] \n connect slots_0.io.brupdate.b2.uop.debug_pc, issue_slots[0].brupdate.b2.uop.debug_pc \n connect slots_0.io.brupdate.b2.uop.is_rvc, issue_slots[0].brupdate.b2.uop.is_rvc \n connect slots_0.io.brupdate.b2.uop.debug_inst, issue_slots[0].brupdate.b2.uop.debug_inst \n connect slots_0.io.brupdate.b2.uop.inst, issue_slots[0].brupdate.b2.uop.inst \n connect slots_0.io.brupdate.b1.mispredict_mask, issue_slots[0].brupdate.b1.mispredict_mask \n connect slots_0.io.brupdate.b1.resolve_mask, issue_slots[0].brupdate.b1.resolve_mask \n connect issue_slots[0].out_uop.debug_tsrc, slots_0.io.out_uop.debug_tsrc \n connect issue_slots[0].out_uop.debug_fsrc, slots_0.io.out_uop.debug_fsrc \n connect issue_slots[0].out_uop.bp_xcpt_if, slots_0.io.out_uop.bp_xcpt_if \n connect issue_slots[0].out_uop.bp_debug_if, slots_0.io.out_uop.bp_debug_if \n connect issue_slots[0].out_uop.xcpt_ma_if, slots_0.io.out_uop.xcpt_ma_if \n connect issue_slots[0].out_uop.xcpt_ae_if, slots_0.io.out_uop.xcpt_ae_if \n connect issue_slots[0].out_uop.xcpt_pf_if, slots_0.io.out_uop.xcpt_pf_if \n connect issue_slots[0].out_uop.fp_typ, slots_0.io.out_uop.fp_typ \n connect issue_slots[0].out_uop.fp_rm, slots_0.io.out_uop.fp_rm \n connect issue_slots[0].out_uop.fp_val, slots_0.io.out_uop.fp_val \n connect issue_slots[0].out_uop.fcn_op, slots_0.io.out_uop.fcn_op \n connect issue_slots[0].out_uop.fcn_dw, slots_0.io.out_uop.fcn_dw \n connect issue_slots[0].out_uop.frs3_en, slots_0.io.out_uop.frs3_en \n connect issue_slots[0].out_uop.lrs2_rtype, slots_0.io.out_uop.lrs2_rtype \n connect issue_slots[0].out_uop.lrs1_rtype, slots_0.io.out_uop.lrs1_rtype \n connect issue_slots[0].out_uop.dst_rtype, slots_0.io.out_uop.dst_rtype \n connect issue_slots[0].out_uop.lrs3, slots_0.io.out_uop.lrs3 \n connect issue_slots[0].out_uop.lrs2, slots_0.io.out_uop.lrs2 \n connect issue_slots[0].out_uop.lrs1, slots_0.io.out_uop.lrs1 \n connect issue_slots[0].out_uop.ldst, slots_0.io.out_uop.ldst \n connect issue_slots[0].out_uop.ldst_is_rs1, slots_0.io.out_uop.ldst_is_rs1 \n connect issue_slots[0].out_uop.csr_cmd, slots_0.io.out_uop.csr_cmd \n connect issue_slots[0].out_uop.flush_on_commit, slots_0.io.out_uop.flush_on_commit \n connect issue_slots[0].out_uop.is_unique, slots_0.io.out_uop.is_unique \n connect issue_slots[0].out_uop.uses_stq, slots_0.io.out_uop.uses_stq \n connect issue_slots[0].out_uop.uses_ldq, slots_0.io.out_uop.uses_ldq \n connect issue_slots[0].out_uop.mem_signed, slots_0.io.out_uop.mem_signed \n connect issue_slots[0].out_uop.mem_size, slots_0.io.out_uop.mem_size \n connect issue_slots[0].out_uop.mem_cmd, slots_0.io.out_uop.mem_cmd \n connect issue_slots[0].out_uop.exc_cause, slots_0.io.out_uop.exc_cause \n connect issue_slots[0].out_uop.exception, slots_0.io.out_uop.exception \n connect issue_slots[0].out_uop.stale_pdst, slots_0.io.out_uop.stale_pdst \n connect issue_slots[0].out_uop.ppred_busy, slots_0.io.out_uop.ppred_busy \n connect issue_slots[0].out_uop.prs3_busy, slots_0.io.out_uop.prs3_busy \n connect issue_slots[0].out_uop.prs2_busy, slots_0.io.out_uop.prs2_busy \n connect issue_slots[0].out_uop.prs1_busy, slots_0.io.out_uop.prs1_busy \n connect issue_slots[0].out_uop.ppred, slots_0.io.out_uop.ppred \n connect issue_slots[0].out_uop.prs3, slots_0.io.out_uop.prs3 \n connect issue_slots[0].out_uop.prs2, slots_0.io.out_uop.prs2 \n connect issue_slots[0].out_uop.prs1, slots_0.io.out_uop.prs1 \n connect issue_slots[0].out_uop.pdst, slots_0.io.out_uop.pdst \n connect issue_slots[0].out_uop.rxq_idx, slots_0.io.out_uop.rxq_idx \n connect issue_slots[0].out_uop.stq_idx, slots_0.io.out_uop.stq_idx \n connect issue_slots[0].out_uop.ldq_idx, slots_0.io.out_uop.ldq_idx \n connect issue_slots[0].out_uop.rob_idx, slots_0.io.out_uop.rob_idx \n connect issue_slots[0].out_uop.fp_ctrl.vec, slots_0.io.out_uop.fp_ctrl.vec \n connect issue_slots[0].out_uop.fp_ctrl.wflags, slots_0.io.out_uop.fp_ctrl.wflags \n connect issue_slots[0].out_uop.fp_ctrl.sqrt, slots_0.io.out_uop.fp_ctrl.sqrt \n connect issue_slots[0].out_uop.fp_ctrl.div, slots_0.io.out_uop.fp_ctrl.div \n connect issue_slots[0].out_uop.fp_ctrl.fma, slots_0.io.out_uop.fp_ctrl.fma \n connect issue_slots[0].out_uop.fp_ctrl.fastpipe, slots_0.io.out_uop.fp_ctrl.fastpipe \n connect issue_slots[0].out_uop.fp_ctrl.toint, slots_0.io.out_uop.fp_ctrl.toint \n connect issue_slots[0].out_uop.fp_ctrl.fromint, slots_0.io.out_uop.fp_ctrl.fromint \n connect issue_slots[0].out_uop.fp_ctrl.typeTagOut, slots_0.io.out_uop.fp_ctrl.typeTagOut \n connect issue_slots[0].out_uop.fp_ctrl.typeTagIn, slots_0.io.out_uop.fp_ctrl.typeTagIn \n connect issue_slots[0].out_uop.fp_ctrl.swap23, slots_0.io.out_uop.fp_ctrl.swap23 \n connect issue_slots[0].out_uop.fp_ctrl.swap12, slots_0.io.out_uop.fp_ctrl.swap12 \n connect issue_slots[0].out_uop.fp_ctrl.ren3, slots_0.io.out_uop.fp_ctrl.ren3 \n connect issue_slots[0].out_uop.fp_ctrl.ren2, slots_0.io.out_uop.fp_ctrl.ren2 \n connect issue_slots[0].out_uop.fp_ctrl.ren1, slots_0.io.out_uop.fp_ctrl.ren1 \n connect issue_slots[0].out_uop.fp_ctrl.wen, slots_0.io.out_uop.fp_ctrl.wen \n connect issue_slots[0].out_uop.fp_ctrl.ldst, slots_0.io.out_uop.fp_ctrl.ldst \n connect issue_slots[0].out_uop.op2_sel, slots_0.io.out_uop.op2_sel \n connect issue_slots[0].out_uop.op1_sel, slots_0.io.out_uop.op1_sel \n connect issue_slots[0].out_uop.imm_packed, slots_0.io.out_uop.imm_packed \n connect issue_slots[0].out_uop.pimm, slots_0.io.out_uop.pimm \n connect issue_slots[0].out_uop.imm_sel, slots_0.io.out_uop.imm_sel \n connect issue_slots[0].out_uop.imm_rename, slots_0.io.out_uop.imm_rename \n connect issue_slots[0].out_uop.taken, slots_0.io.out_uop.taken \n connect issue_slots[0].out_uop.pc_lob, slots_0.io.out_uop.pc_lob \n connect issue_slots[0].out_uop.edge_inst, slots_0.io.out_uop.edge_inst \n connect issue_slots[0].out_uop.ftq_idx, slots_0.io.out_uop.ftq_idx \n connect issue_slots[0].out_uop.is_mov, slots_0.io.out_uop.is_mov \n connect issue_slots[0].out_uop.is_rocc, slots_0.io.out_uop.is_rocc \n connect issue_slots[0].out_uop.is_sys_pc2epc, slots_0.io.out_uop.is_sys_pc2epc \n connect issue_slots[0].out_uop.is_eret, slots_0.io.out_uop.is_eret \n connect issue_slots[0].out_uop.is_amo, slots_0.io.out_uop.is_amo \n connect issue_slots[0].out_uop.is_sfence, slots_0.io.out_uop.is_sfence \n connect issue_slots[0].out_uop.is_fencei, slots_0.io.out_uop.is_fencei \n connect issue_slots[0].out_uop.is_fence, slots_0.io.out_uop.is_fence \n connect issue_slots[0].out_uop.is_sfb, slots_0.io.out_uop.is_sfb \n connect issue_slots[0].out_uop.br_type, slots_0.io.out_uop.br_type \n connect issue_slots[0].out_uop.br_tag, slots_0.io.out_uop.br_tag \n connect issue_slots[0].out_uop.br_mask, slots_0.io.out_uop.br_mask \n connect issue_slots[0].out_uop.dis_col_sel, slots_0.io.out_uop.dis_col_sel \n connect issue_slots[0].out_uop.iw_p3_bypass_hint, slots_0.io.out_uop.iw_p3_bypass_hint \n connect issue_slots[0].out_uop.iw_p2_bypass_hint, slots_0.io.out_uop.iw_p2_bypass_hint \n connect issue_slots[0].out_uop.iw_p1_bypass_hint, slots_0.io.out_uop.iw_p1_bypass_hint \n connect issue_slots[0].out_uop.iw_p2_speculative_child, slots_0.io.out_uop.iw_p2_speculative_child \n connect issue_slots[0].out_uop.iw_p1_speculative_child, slots_0.io.out_uop.iw_p1_speculative_child \n connect issue_slots[0].out_uop.iw_issued_partial_dgen, slots_0.io.out_uop.iw_issued_partial_dgen \n connect issue_slots[0].out_uop.iw_issued_partial_agen, slots_0.io.out_uop.iw_issued_partial_agen \n connect issue_slots[0].out_uop.iw_issued, slots_0.io.out_uop.iw_issued \n connect issue_slots[0].out_uop.fu_code[0], slots_0.io.out_uop.fu_code[0] \n connect issue_slots[0].out_uop.fu_code[1], slots_0.io.out_uop.fu_code[1] \n connect issue_slots[0].out_uop.fu_code[2], slots_0.io.out_uop.fu_code[2] \n connect issue_slots[0].out_uop.fu_code[3], slots_0.io.out_uop.fu_code[3] \n connect issue_slots[0].out_uop.fu_code[4], slots_0.io.out_uop.fu_code[4] \n connect issue_slots[0].out_uop.fu_code[5], slots_0.io.out_uop.fu_code[5] \n connect issue_slots[0].out_uop.fu_code[6], slots_0.io.out_uop.fu_code[6] \n connect issue_slots[0].out_uop.fu_code[7], slots_0.io.out_uop.fu_code[7] \n connect issue_slots[0].out_uop.fu_code[8], slots_0.io.out_uop.fu_code[8] \n connect issue_slots[0].out_uop.fu_code[9], slots_0.io.out_uop.fu_code[9] \n connect issue_slots[0].out_uop.iq_type[0], slots_0.io.out_uop.iq_type[0] \n connect issue_slots[0].out_uop.iq_type[1], slots_0.io.out_uop.iq_type[1] \n connect issue_slots[0].out_uop.iq_type[2], slots_0.io.out_uop.iq_type[2] \n connect issue_slots[0].out_uop.iq_type[3], slots_0.io.out_uop.iq_type[3] \n connect issue_slots[0].out_uop.debug_pc, slots_0.io.out_uop.debug_pc \n connect issue_slots[0].out_uop.is_rvc, slots_0.io.out_uop.is_rvc \n connect issue_slots[0].out_uop.debug_inst, slots_0.io.out_uop.debug_inst \n connect issue_slots[0].out_uop.inst, slots_0.io.out_uop.inst \n connect slots_0.io.in_uop.bits.debug_tsrc, issue_slots[0].in_uop.bits.debug_tsrc \n connect slots_0.io.in_uop.bits.debug_fsrc, issue_slots[0].in_uop.bits.debug_fsrc \n connect slots_0.io.in_uop.bits.bp_xcpt_if, issue_slots[0].in_uop.bits.bp_xcpt_if \n connect slots_0.io.in_uop.bits.bp_debug_if, issue_slots[0].in_uop.bits.bp_debug_if \n connect slots_0.io.in_uop.bits.xcpt_ma_if, issue_slots[0].in_uop.bits.xcpt_ma_if \n connect slots_0.io.in_uop.bits.xcpt_ae_if, issue_slots[0].in_uop.bits.xcpt_ae_if \n connect slots_0.io.in_uop.bits.xcpt_pf_if, issue_slots[0].in_uop.bits.xcpt_pf_if \n connect slots_0.io.in_uop.bits.fp_typ, issue_slots[0].in_uop.bits.fp_typ \n connect slots_0.io.in_uop.bits.fp_rm, issue_slots[0].in_uop.bits.fp_rm \n connect slots_0.io.in_uop.bits.fp_val, issue_slots[0].in_uop.bits.fp_val \n connect slots_0.io.in_uop.bits.fcn_op, issue_slots[0].in_uop.bits.fcn_op \n connect slots_0.io.in_uop.bits.fcn_dw, issue_slots[0].in_uop.bits.fcn_dw \n connect slots_0.io.in_uop.bits.frs3_en, issue_slots[0].in_uop.bits.frs3_en \n connect slots_0.io.in_uop.bits.lrs2_rtype, issue_slots[0].in_uop.bits.lrs2_rtype \n connect slots_0.io.in_uop.bits.lrs1_rtype, issue_slots[0].in_uop.bits.lrs1_rtype \n connect slots_0.io.in_uop.bits.dst_rtype, issue_slots[0].in_uop.bits.dst_rtype \n connect slots_0.io.in_uop.bits.lrs3, issue_slots[0].in_uop.bits.lrs3 \n connect slots_0.io.in_uop.bits.lrs2, issue_slots[0].in_uop.bits.lrs2 \n connect slots_0.io.in_uop.bits.lrs1, issue_slots[0].in_uop.bits.lrs1 \n connect slots_0.io.in_uop.bits.ldst, issue_slots[0].in_uop.bits.ldst \n connect slots_0.io.in_uop.bits.ldst_is_rs1, issue_slots[0].in_uop.bits.ldst_is_rs1 \n connect slots_0.io.in_uop.bits.csr_cmd, issue_slots[0].in_uop.bits.csr_cmd \n connect slots_0.io.in_uop.bits.flush_on_commit, issue_slots[0].in_uop.bits.flush_on_commit \n connect slots_0.io.in_uop.bits.is_unique, issue_slots[0].in_uop.bits.is_unique \n connect slots_0.io.in_uop.bits.uses_stq, issue_slots[0].in_uop.bits.uses_stq \n connect slots_0.io.in_uop.bits.uses_ldq, issue_slots[0].in_uop.bits.uses_ldq \n connect slots_0.io.in_uop.bits.mem_signed, issue_slots[0].in_uop.bits.mem_signed \n connect slots_0.io.in_uop.bits.mem_size, issue_slots[0].in_uop.bits.mem_size \n connect slots_0.io.in_uop.bits.mem_cmd, issue_slots[0].in_uop.bits.mem_cmd \n connect slots_0.io.in_uop.bits.exc_cause, issue_slots[0].in_uop.bits.exc_cause \n connect slots_0.io.in_uop.bits.exception, issue_slots[0].in_uop.bits.exception \n connect slots_0.io.in_uop.bits.stale_pdst, issue_slots[0].in_uop.bits.stale_pdst \n connect slots_0.io.in_uop.bits.ppred_busy, issue_slots[0].in_uop.bits.ppred_busy \n connect slots_0.io.in_uop.bits.prs3_busy, issue_slots[0].in_uop.bits.prs3_busy \n connect slots_0.io.in_uop.bits.prs2_busy, issue_slots[0].in_uop.bits.prs2_busy \n connect slots_0.io.in_uop.bits.prs1_busy, issue_slots[0].in_uop.bits.prs1_busy \n connect slots_0.io.in_uop.bits.ppred, issue_slots[0].in_uop.bits.ppred \n connect slots_0.io.in_uop.bits.prs3, issue_slots[0].in_uop.bits.prs3 \n connect slots_0.io.in_uop.bits.prs2, issue_slots[0].in_uop.bits.prs2 \n connect slots_0.io.in_uop.bits.prs1, issue_slots[0].in_uop.bits.prs1 \n connect slots_0.io.in_uop.bits.pdst, issue_slots[0].in_uop.bits.pdst \n connect slots_0.io.in_uop.bits.rxq_idx, issue_slots[0].in_uop.bits.rxq_idx \n connect slots_0.io.in_uop.bits.stq_idx, issue_slots[0].in_uop.bits.stq_idx \n connect slots_0.io.in_uop.bits.ldq_idx, issue_slots[0].in_uop.bits.ldq_idx \n connect slots_0.io.in_uop.bits.rob_idx, issue_slots[0].in_uop.bits.rob_idx \n connect slots_0.io.in_uop.bits.fp_ctrl.vec, issue_slots[0].in_uop.bits.fp_ctrl.vec \n connect slots_0.io.in_uop.bits.fp_ctrl.wflags, issue_slots[0].in_uop.bits.fp_ctrl.wflags \n connect slots_0.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[0].in_uop.bits.fp_ctrl.sqrt \n connect slots_0.io.in_uop.bits.fp_ctrl.div, issue_slots[0].in_uop.bits.fp_ctrl.div \n connect slots_0.io.in_uop.bits.fp_ctrl.fma, issue_slots[0].in_uop.bits.fp_ctrl.fma \n connect slots_0.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[0].in_uop.bits.fp_ctrl.fastpipe \n connect slots_0.io.in_uop.bits.fp_ctrl.toint, issue_slots[0].in_uop.bits.fp_ctrl.toint \n connect slots_0.io.in_uop.bits.fp_ctrl.fromint, issue_slots[0].in_uop.bits.fp_ctrl.fromint \n connect slots_0.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[0].in_uop.bits.fp_ctrl.typeTagOut \n connect slots_0.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[0].in_uop.bits.fp_ctrl.typeTagIn \n connect slots_0.io.in_uop.bits.fp_ctrl.swap23, issue_slots[0].in_uop.bits.fp_ctrl.swap23 \n connect slots_0.io.in_uop.bits.fp_ctrl.swap12, issue_slots[0].in_uop.bits.fp_ctrl.swap12 \n connect slots_0.io.in_uop.bits.fp_ctrl.ren3, issue_slots[0].in_uop.bits.fp_ctrl.ren3 \n connect slots_0.io.in_uop.bits.fp_ctrl.ren2, issue_slots[0].in_uop.bits.fp_ctrl.ren2 \n connect slots_0.io.in_uop.bits.fp_ctrl.ren1, issue_slots[0].in_uop.bits.fp_ctrl.ren1 \n connect slots_0.io.in_uop.bits.fp_ctrl.wen, issue_slots[0].in_uop.bits.fp_ctrl.wen \n connect slots_0.io.in_uop.bits.fp_ctrl.ldst, issue_slots[0].in_uop.bits.fp_ctrl.ldst \n connect slots_0.io.in_uop.bits.op2_sel, issue_slots[0].in_uop.bits.op2_sel \n connect slots_0.io.in_uop.bits.op1_sel, issue_slots[0].in_uop.bits.op1_sel \n connect slots_0.io.in_uop.bits.imm_packed, issue_slots[0].in_uop.bits.imm_packed \n connect slots_0.io.in_uop.bits.pimm, issue_slots[0].in_uop.bits.pimm \n connect slots_0.io.in_uop.bits.imm_sel, issue_slots[0].in_uop.bits.imm_sel \n connect slots_0.io.in_uop.bits.imm_rename, issue_slots[0].in_uop.bits.imm_rename \n connect slots_0.io.in_uop.bits.taken, issue_slots[0].in_uop.bits.taken \n connect slots_0.io.in_uop.bits.pc_lob, issue_slots[0].in_uop.bits.pc_lob \n connect slots_0.io.in_uop.bits.edge_inst, issue_slots[0].in_uop.bits.edge_inst \n connect slots_0.io.in_uop.bits.ftq_idx, issue_slots[0].in_uop.bits.ftq_idx \n connect slots_0.io.in_uop.bits.is_mov, issue_slots[0].in_uop.bits.is_mov \n connect slots_0.io.in_uop.bits.is_rocc, issue_slots[0].in_uop.bits.is_rocc \n connect slots_0.io.in_uop.bits.is_sys_pc2epc, issue_slots[0].in_uop.bits.is_sys_pc2epc \n connect slots_0.io.in_uop.bits.is_eret, issue_slots[0].in_uop.bits.is_eret \n connect slots_0.io.in_uop.bits.is_amo, issue_slots[0].in_uop.bits.is_amo \n connect slots_0.io.in_uop.bits.is_sfence, issue_slots[0].in_uop.bits.is_sfence \n connect slots_0.io.in_uop.bits.is_fencei, issue_slots[0].in_uop.bits.is_fencei \n connect slots_0.io.in_uop.bits.is_fence, issue_slots[0].in_uop.bits.is_fence \n connect slots_0.io.in_uop.bits.is_sfb, issue_slots[0].in_uop.bits.is_sfb \n connect slots_0.io.in_uop.bits.br_type, issue_slots[0].in_uop.bits.br_type \n connect slots_0.io.in_uop.bits.br_tag, issue_slots[0].in_uop.bits.br_tag \n connect slots_0.io.in_uop.bits.br_mask, issue_slots[0].in_uop.bits.br_mask \n connect slots_0.io.in_uop.bits.dis_col_sel, issue_slots[0].in_uop.bits.dis_col_sel \n connect slots_0.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[0].in_uop.bits.iw_p3_bypass_hint \n connect slots_0.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[0].in_uop.bits.iw_p2_bypass_hint \n connect slots_0.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[0].in_uop.bits.iw_p1_bypass_hint \n connect slots_0.io.in_uop.bits.iw_p2_speculative_child, issue_slots[0].in_uop.bits.iw_p2_speculative_child \n connect slots_0.io.in_uop.bits.iw_p1_speculative_child, issue_slots[0].in_uop.bits.iw_p1_speculative_child \n connect slots_0.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[0].in_uop.bits.iw_issued_partial_dgen \n connect slots_0.io.in_uop.bits.iw_issued_partial_agen, issue_slots[0].in_uop.bits.iw_issued_partial_agen \n connect slots_0.io.in_uop.bits.iw_issued, issue_slots[0].in_uop.bits.iw_issued \n connect slots_0.io.in_uop.bits.fu_code[0], issue_slots[0].in_uop.bits.fu_code[0] \n connect slots_0.io.in_uop.bits.fu_code[1], issue_slots[0].in_uop.bits.fu_code[1] \n connect slots_0.io.in_uop.bits.fu_code[2], issue_slots[0].in_uop.bits.fu_code[2] \n connect slots_0.io.in_uop.bits.fu_code[3], issue_slots[0].in_uop.bits.fu_code[3] \n connect slots_0.io.in_uop.bits.fu_code[4], issue_slots[0].in_uop.bits.fu_code[4] \n connect slots_0.io.in_uop.bits.fu_code[5], issue_slots[0].in_uop.bits.fu_code[5] \n connect slots_0.io.in_uop.bits.fu_code[6], issue_slots[0].in_uop.bits.fu_code[6] \n connect slots_0.io.in_uop.bits.fu_code[7], issue_slots[0].in_uop.bits.fu_code[7] \n connect slots_0.io.in_uop.bits.fu_code[8], issue_slots[0].in_uop.bits.fu_code[8] \n connect slots_0.io.in_uop.bits.fu_code[9], issue_slots[0].in_uop.bits.fu_code[9] \n connect slots_0.io.in_uop.bits.iq_type[0], issue_slots[0].in_uop.bits.iq_type[0] \n connect slots_0.io.in_uop.bits.iq_type[1], issue_slots[0].in_uop.bits.iq_type[1] \n connect slots_0.io.in_uop.bits.iq_type[2], issue_slots[0].in_uop.bits.iq_type[2] \n connect slots_0.io.in_uop.bits.iq_type[3], issue_slots[0].in_uop.bits.iq_type[3] \n connect slots_0.io.in_uop.bits.debug_pc, issue_slots[0].in_uop.bits.debug_pc \n connect slots_0.io.in_uop.bits.is_rvc, issue_slots[0].in_uop.bits.is_rvc \n connect slots_0.io.in_uop.bits.debug_inst, issue_slots[0].in_uop.bits.debug_inst \n connect slots_0.io.in_uop.bits.inst, issue_slots[0].in_uop.bits.inst \n connect slots_0.io.in_uop.valid, issue_slots[0].in_uop.valid \n connect issue_slots[0].iss_uop.debug_tsrc, slots_0.io.iss_uop.debug_tsrc \n connect issue_slots[0].iss_uop.debug_fsrc, slots_0.io.iss_uop.debug_fsrc \n connect issue_slots[0].iss_uop.bp_xcpt_if, slots_0.io.iss_uop.bp_xcpt_if \n connect issue_slots[0].iss_uop.bp_debug_if, slots_0.io.iss_uop.bp_debug_if \n connect issue_slots[0].iss_uop.xcpt_ma_if, slots_0.io.iss_uop.xcpt_ma_if \n connect issue_slots[0].iss_uop.xcpt_ae_if, slots_0.io.iss_uop.xcpt_ae_if \n connect issue_slots[0].iss_uop.xcpt_pf_if, slots_0.io.iss_uop.xcpt_pf_if \n connect issue_slots[0].iss_uop.fp_typ, slots_0.io.iss_uop.fp_typ \n connect issue_slots[0].iss_uop.fp_rm, slots_0.io.iss_uop.fp_rm \n connect issue_slots[0].iss_uop.fp_val, slots_0.io.iss_uop.fp_val \n connect issue_slots[0].iss_uop.fcn_op, slots_0.io.iss_uop.fcn_op \n connect issue_slots[0].iss_uop.fcn_dw, slots_0.io.iss_uop.fcn_dw \n connect issue_slots[0].iss_uop.frs3_en, slots_0.io.iss_uop.frs3_en \n connect issue_slots[0].iss_uop.lrs2_rtype, slots_0.io.iss_uop.lrs2_rtype \n connect issue_slots[0].iss_uop.lrs1_rtype, slots_0.io.iss_uop.lrs1_rtype \n connect issue_slots[0].iss_uop.dst_rtype, slots_0.io.iss_uop.dst_rtype \n connect issue_slots[0].iss_uop.lrs3, slots_0.io.iss_uop.lrs3 \n connect issue_slots[0].iss_uop.lrs2, slots_0.io.iss_uop.lrs2 \n connect issue_slots[0].iss_uop.lrs1, slots_0.io.iss_uop.lrs1 \n connect issue_slots[0].iss_uop.ldst, slots_0.io.iss_uop.ldst \n connect issue_slots[0].iss_uop.ldst_is_rs1, slots_0.io.iss_uop.ldst_is_rs1 \n connect issue_slots[0].iss_uop.csr_cmd, slots_0.io.iss_uop.csr_cmd \n connect issue_slots[0].iss_uop.flush_on_commit, slots_0.io.iss_uop.flush_on_commit \n connect issue_slots[0].iss_uop.is_unique, slots_0.io.iss_uop.is_unique \n connect issue_slots[0].iss_uop.uses_stq, slots_0.io.iss_uop.uses_stq \n connect issue_slots[0].iss_uop.uses_ldq, slots_0.io.iss_uop.uses_ldq \n connect issue_slots[0].iss_uop.mem_signed, slots_0.io.iss_uop.mem_signed \n connect issue_slots[0].iss_uop.mem_size, slots_0.io.iss_uop.mem_size \n connect issue_slots[0].iss_uop.mem_cmd, slots_0.io.iss_uop.mem_cmd \n connect issue_slots[0].iss_uop.exc_cause, slots_0.io.iss_uop.exc_cause \n connect issue_slots[0].iss_uop.exception, slots_0.io.iss_uop.exception \n connect issue_slots[0].iss_uop.stale_pdst, slots_0.io.iss_uop.stale_pdst \n connect issue_slots[0].iss_uop.ppred_busy, slots_0.io.iss_uop.ppred_busy \n connect issue_slots[0].iss_uop.prs3_busy, slots_0.io.iss_uop.prs3_busy \n connect issue_slots[0].iss_uop.prs2_busy, slots_0.io.iss_uop.prs2_busy \n connect issue_slots[0].iss_uop.prs1_busy, slots_0.io.iss_uop.prs1_busy \n connect issue_slots[0].iss_uop.ppred, slots_0.io.iss_uop.ppred \n connect issue_slots[0].iss_uop.prs3, slots_0.io.iss_uop.prs3 \n connect issue_slots[0].iss_uop.prs2, slots_0.io.iss_uop.prs2 \n connect issue_slots[0].iss_uop.prs1, slots_0.io.iss_uop.prs1 \n connect issue_slots[0].iss_uop.pdst, slots_0.io.iss_uop.pdst \n connect issue_slots[0].iss_uop.rxq_idx, slots_0.io.iss_uop.rxq_idx \n connect issue_slots[0].iss_uop.stq_idx, slots_0.io.iss_uop.stq_idx \n connect issue_slots[0].iss_uop.ldq_idx, slots_0.io.iss_uop.ldq_idx \n connect issue_slots[0].iss_uop.rob_idx, slots_0.io.iss_uop.rob_idx \n connect issue_slots[0].iss_uop.fp_ctrl.vec, slots_0.io.iss_uop.fp_ctrl.vec \n connect issue_slots[0].iss_uop.fp_ctrl.wflags, slots_0.io.iss_uop.fp_ctrl.wflags \n connect issue_slots[0].iss_uop.fp_ctrl.sqrt, slots_0.io.iss_uop.fp_ctrl.sqrt \n connect issue_slots[0].iss_uop.fp_ctrl.div, slots_0.io.iss_uop.fp_ctrl.div \n connect issue_slots[0].iss_uop.fp_ctrl.fma, slots_0.io.iss_uop.fp_ctrl.fma \n connect issue_slots[0].iss_uop.fp_ctrl.fastpipe, slots_0.io.iss_uop.fp_ctrl.fastpipe \n connect issue_slots[0].iss_uop.fp_ctrl.toint, slots_0.io.iss_uop.fp_ctrl.toint \n connect issue_slots[0].iss_uop.fp_ctrl.fromint, slots_0.io.iss_uop.fp_ctrl.fromint \n connect issue_slots[0].iss_uop.fp_ctrl.typeTagOut, slots_0.io.iss_uop.fp_ctrl.typeTagOut \n connect issue_slots[0].iss_uop.fp_ctrl.typeTagIn, slots_0.io.iss_uop.fp_ctrl.typeTagIn \n connect issue_slots[0].iss_uop.fp_ctrl.swap23, slots_0.io.iss_uop.fp_ctrl.swap23 \n connect issue_slots[0].iss_uop.fp_ctrl.swap12, slots_0.io.iss_uop.fp_ctrl.swap12 \n connect issue_slots[0].iss_uop.fp_ctrl.ren3, slots_0.io.iss_uop.fp_ctrl.ren3 \n connect issue_slots[0].iss_uop.fp_ctrl.ren2, slots_0.io.iss_uop.fp_ctrl.ren2 \n connect issue_slots[0].iss_uop.fp_ctrl.ren1, slots_0.io.iss_uop.fp_ctrl.ren1 \n connect issue_slots[0].iss_uop.fp_ctrl.wen, slots_0.io.iss_uop.fp_ctrl.wen \n connect issue_slots[0].iss_uop.fp_ctrl.ldst, slots_0.io.iss_uop.fp_ctrl.ldst \n connect issue_slots[0].iss_uop.op2_sel, slots_0.io.iss_uop.op2_sel \n connect issue_slots[0].iss_uop.op1_sel, slots_0.io.iss_uop.op1_sel \n connect issue_slots[0].iss_uop.imm_packed, slots_0.io.iss_uop.imm_packed \n connect issue_slots[0].iss_uop.pimm, slots_0.io.iss_uop.pimm \n connect issue_slots[0].iss_uop.imm_sel, slots_0.io.iss_uop.imm_sel \n connect issue_slots[0].iss_uop.imm_rename, slots_0.io.iss_uop.imm_rename \n connect issue_slots[0].iss_uop.taken, slots_0.io.iss_uop.taken \n connect issue_slots[0].iss_uop.pc_lob, slots_0.io.iss_uop.pc_lob \n connect issue_slots[0].iss_uop.edge_inst, slots_0.io.iss_uop.edge_inst \n connect issue_slots[0].iss_uop.ftq_idx, slots_0.io.iss_uop.ftq_idx \n connect issue_slots[0].iss_uop.is_mov, slots_0.io.iss_uop.is_mov \n connect issue_slots[0].iss_uop.is_rocc, slots_0.io.iss_uop.is_rocc \n connect issue_slots[0].iss_uop.is_sys_pc2epc, slots_0.io.iss_uop.is_sys_pc2epc \n connect issue_slots[0].iss_uop.is_eret, slots_0.io.iss_uop.is_eret \n connect issue_slots[0].iss_uop.is_amo, slots_0.io.iss_uop.is_amo \n connect issue_slots[0].iss_uop.is_sfence, slots_0.io.iss_uop.is_sfence \n connect issue_slots[0].iss_uop.is_fencei, slots_0.io.iss_uop.is_fencei \n connect issue_slots[0].iss_uop.is_fence, slots_0.io.iss_uop.is_fence \n connect issue_slots[0].iss_uop.is_sfb, slots_0.io.iss_uop.is_sfb \n connect issue_slots[0].iss_uop.br_type, slots_0.io.iss_uop.br_type \n connect issue_slots[0].iss_uop.br_tag, slots_0.io.iss_uop.br_tag \n connect issue_slots[0].iss_uop.br_mask, slots_0.io.iss_uop.br_mask \n connect issue_slots[0].iss_uop.dis_col_sel, slots_0.io.iss_uop.dis_col_sel \n connect issue_slots[0].iss_uop.iw_p3_bypass_hint, slots_0.io.iss_uop.iw_p3_bypass_hint \n connect issue_slots[0].iss_uop.iw_p2_bypass_hint, slots_0.io.iss_uop.iw_p2_bypass_hint \n connect issue_slots[0].iss_uop.iw_p1_bypass_hint, slots_0.io.iss_uop.iw_p1_bypass_hint \n connect issue_slots[0].iss_uop.iw_p2_speculative_child, slots_0.io.iss_uop.iw_p2_speculative_child \n connect issue_slots[0].iss_uop.iw_p1_speculative_child, slots_0.io.iss_uop.iw_p1_speculative_child \n connect issue_slots[0].iss_uop.iw_issued_partial_dgen, slots_0.io.iss_uop.iw_issued_partial_dgen \n connect issue_slots[0].iss_uop.iw_issued_partial_agen, slots_0.io.iss_uop.iw_issued_partial_agen \n connect issue_slots[0].iss_uop.iw_issued, slots_0.io.iss_uop.iw_issued \n connect issue_slots[0].iss_uop.fu_code[0], slots_0.io.iss_uop.fu_code[0] \n connect issue_slots[0].iss_uop.fu_code[1], slots_0.io.iss_uop.fu_code[1] \n connect issue_slots[0].iss_uop.fu_code[2], slots_0.io.iss_uop.fu_code[2] \n connect issue_slots[0].iss_uop.fu_code[3], slots_0.io.iss_uop.fu_code[3] \n connect issue_slots[0].iss_uop.fu_code[4], slots_0.io.iss_uop.fu_code[4] \n connect issue_slots[0].iss_uop.fu_code[5], slots_0.io.iss_uop.fu_code[5] \n connect issue_slots[0].iss_uop.fu_code[6], slots_0.io.iss_uop.fu_code[6] \n connect issue_slots[0].iss_uop.fu_code[7], slots_0.io.iss_uop.fu_code[7] \n connect issue_slots[0].iss_uop.fu_code[8], slots_0.io.iss_uop.fu_code[8] \n connect issue_slots[0].iss_uop.fu_code[9], slots_0.io.iss_uop.fu_code[9] \n connect issue_slots[0].iss_uop.iq_type[0], slots_0.io.iss_uop.iq_type[0] \n connect issue_slots[0].iss_uop.iq_type[1], slots_0.io.iss_uop.iq_type[1] \n connect issue_slots[0].iss_uop.iq_type[2], slots_0.io.iss_uop.iq_type[2] \n connect issue_slots[0].iss_uop.iq_type[3], slots_0.io.iss_uop.iq_type[3] \n connect issue_slots[0].iss_uop.debug_pc, slots_0.io.iss_uop.debug_pc \n connect issue_slots[0].iss_uop.is_rvc, slots_0.io.iss_uop.is_rvc \n connect issue_slots[0].iss_uop.debug_inst, slots_0.io.iss_uop.debug_inst \n connect issue_slots[0].iss_uop.inst, slots_0.io.iss_uop.inst \n connect slots_0.io.grant, issue_slots[0].grant \n connect issue_slots[0].request, slots_0.io.request \n connect issue_slots[0].will_be_valid, slots_0.io.will_be_valid \n connect issue_slots[0].valid, slots_0.io.valid \n connect slots_1.io.child_rebusys, issue_slots[1].child_rebusys \n connect slots_1.io.pred_wakeup_port.bits, issue_slots[1].pred_wakeup_port.bits \n connect slots_1.io.pred_wakeup_port.valid, issue_slots[1].pred_wakeup_port.valid \n connect slots_1.io.wakeup_ports[0].bits.rebusy, issue_slots[1].wakeup_ports[0].bits.rebusy \n connect slots_1.io.wakeup_ports[0].bits.speculative_mask, issue_slots[1].wakeup_ports[0].bits.speculative_mask \n connect slots_1.io.wakeup_ports[0].bits.bypassable, issue_slots[1].wakeup_ports[0].bits.bypassable \n connect slots_1.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[1].wakeup_ports[0].bits.uop.debug_tsrc \n connect slots_1.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[1].wakeup_ports[0].bits.uop.debug_fsrc \n connect slots_1.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[1].wakeup_ports[0].bits.uop.bp_xcpt_if \n connect slots_1.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[1].wakeup_ports[0].bits.uop.bp_debug_if \n connect slots_1.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[1].wakeup_ports[0].bits.uop.xcpt_ma_if \n connect slots_1.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[1].wakeup_ports[0].bits.uop.xcpt_ae_if \n connect slots_1.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[1].wakeup_ports[0].bits.uop.xcpt_pf_if \n connect slots_1.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[1].wakeup_ports[0].bits.uop.fp_typ \n connect slots_1.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[1].wakeup_ports[0].bits.uop.fp_rm \n connect slots_1.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[1].wakeup_ports[0].bits.uop.fp_val \n connect slots_1.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[1].wakeup_ports[0].bits.uop.fcn_op \n connect slots_1.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[1].wakeup_ports[0].bits.uop.fcn_dw \n connect slots_1.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[1].wakeup_ports[0].bits.uop.frs3_en \n connect slots_1.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[1].wakeup_ports[0].bits.uop.lrs2_rtype \n connect slots_1.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[1].wakeup_ports[0].bits.uop.lrs1_rtype \n connect slots_1.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[1].wakeup_ports[0].bits.uop.dst_rtype \n connect slots_1.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[1].wakeup_ports[0].bits.uop.lrs3 \n connect slots_1.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[1].wakeup_ports[0].bits.uop.lrs2 \n connect slots_1.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[1].wakeup_ports[0].bits.uop.lrs1 \n connect slots_1.io.wakeup_ports[0].bits.uop.ldst, issue_slots[1].wakeup_ports[0].bits.uop.ldst \n connect slots_1.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[1].wakeup_ports[0].bits.uop.ldst_is_rs1 \n connect slots_1.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[1].wakeup_ports[0].bits.uop.csr_cmd \n connect slots_1.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[1].wakeup_ports[0].bits.uop.flush_on_commit \n connect slots_1.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[1].wakeup_ports[0].bits.uop.is_unique \n connect slots_1.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[1].wakeup_ports[0].bits.uop.uses_stq \n connect slots_1.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[1].wakeup_ports[0].bits.uop.uses_ldq \n connect slots_1.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[1].wakeup_ports[0].bits.uop.mem_signed \n connect slots_1.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[1].wakeup_ports[0].bits.uop.mem_size \n connect slots_1.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[1].wakeup_ports[0].bits.uop.mem_cmd \n connect slots_1.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[1].wakeup_ports[0].bits.uop.exc_cause \n connect slots_1.io.wakeup_ports[0].bits.uop.exception, issue_slots[1].wakeup_ports[0].bits.uop.exception \n connect slots_1.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[1].wakeup_ports[0].bits.uop.stale_pdst \n connect slots_1.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[1].wakeup_ports[0].bits.uop.ppred_busy \n connect slots_1.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[1].wakeup_ports[0].bits.uop.prs3_busy \n connect slots_1.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[1].wakeup_ports[0].bits.uop.prs2_busy \n connect slots_1.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[1].wakeup_ports[0].bits.uop.prs1_busy \n connect slots_1.io.wakeup_ports[0].bits.uop.ppred, issue_slots[1].wakeup_ports[0].bits.uop.ppred \n connect slots_1.io.wakeup_ports[0].bits.uop.prs3, issue_slots[1].wakeup_ports[0].bits.uop.prs3 \n connect slots_1.io.wakeup_ports[0].bits.uop.prs2, issue_slots[1].wakeup_ports[0].bits.uop.prs2 \n connect slots_1.io.wakeup_ports[0].bits.uop.prs1, issue_slots[1].wakeup_ports[0].bits.uop.prs1 \n connect slots_1.io.wakeup_ports[0].bits.uop.pdst, issue_slots[1].wakeup_ports[0].bits.uop.pdst \n connect slots_1.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[1].wakeup_ports[0].bits.uop.rxq_idx \n connect slots_1.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[1].wakeup_ports[0].bits.uop.stq_idx \n connect slots_1.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[1].wakeup_ports[0].bits.uop.ldq_idx \n connect slots_1.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[1].wakeup_ports[0].bits.uop.rob_idx \n connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.vec \n connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.wflags \n connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.sqrt \n connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.div \n connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.fma \n connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe \n connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.toint \n connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.fromint \n connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut \n connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn \n connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.swap23 \n connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.swap12 \n connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.ren3 \n connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.ren2 \n connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.ren1 \n connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.wen \n connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.ldst \n connect slots_1.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[1].wakeup_ports[0].bits.uop.op2_sel \n connect slots_1.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[1].wakeup_ports[0].bits.uop.op1_sel \n connect slots_1.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[1].wakeup_ports[0].bits.uop.imm_packed \n connect slots_1.io.wakeup_ports[0].bits.uop.pimm, issue_slots[1].wakeup_ports[0].bits.uop.pimm \n connect slots_1.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[1].wakeup_ports[0].bits.uop.imm_sel \n connect slots_1.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[1].wakeup_ports[0].bits.uop.imm_rename \n connect slots_1.io.wakeup_ports[0].bits.uop.taken, issue_slots[1].wakeup_ports[0].bits.uop.taken \n connect slots_1.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[1].wakeup_ports[0].bits.uop.pc_lob \n connect slots_1.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[1].wakeup_ports[0].bits.uop.edge_inst \n connect slots_1.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[1].wakeup_ports[0].bits.uop.ftq_idx \n connect slots_1.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[1].wakeup_ports[0].bits.uop.is_mov \n connect slots_1.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[1].wakeup_ports[0].bits.uop.is_rocc \n connect slots_1.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[1].wakeup_ports[0].bits.uop.is_sys_pc2epc \n connect slots_1.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[1].wakeup_ports[0].bits.uop.is_eret \n connect slots_1.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[1].wakeup_ports[0].bits.uop.is_amo \n connect slots_1.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[1].wakeup_ports[0].bits.uop.is_sfence \n connect slots_1.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[1].wakeup_ports[0].bits.uop.is_fencei \n connect slots_1.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[1].wakeup_ports[0].bits.uop.is_fence \n connect slots_1.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[1].wakeup_ports[0].bits.uop.is_sfb \n connect slots_1.io.wakeup_ports[0].bits.uop.br_type, issue_slots[1].wakeup_ports[0].bits.uop.br_type \n connect slots_1.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[1].wakeup_ports[0].bits.uop.br_tag \n connect slots_1.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[1].wakeup_ports[0].bits.uop.br_mask \n connect slots_1.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[1].wakeup_ports[0].bits.uop.dis_col_sel \n connect slots_1.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[1].wakeup_ports[0].bits.uop.iw_p3_bypass_hint \n connect slots_1.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[1].wakeup_ports[0].bits.uop.iw_p2_bypass_hint \n connect slots_1.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[1].wakeup_ports[0].bits.uop.iw_p1_bypass_hint \n connect slots_1.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[1].wakeup_ports[0].bits.uop.iw_p2_speculative_child \n connect slots_1.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[1].wakeup_ports[0].bits.uop.iw_p1_speculative_child \n connect slots_1.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[1].wakeup_ports[0].bits.uop.iw_issued_partial_dgen \n connect slots_1.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[1].wakeup_ports[0].bits.uop.iw_issued_partial_agen \n connect slots_1.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[1].wakeup_ports[0].bits.uop.iw_issued \n connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[0] \n connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[1] \n connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[2] \n connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[3] \n connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[4] \n connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[5] \n connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[6] \n connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[7] \n connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[8] \n connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[9] \n connect slots_1.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[1].wakeup_ports[0].bits.uop.iq_type[0] \n connect slots_1.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[1].wakeup_ports[0].bits.uop.iq_type[1] \n connect slots_1.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[1].wakeup_ports[0].bits.uop.iq_type[2] \n connect slots_1.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[1].wakeup_ports[0].bits.uop.iq_type[3] \n connect slots_1.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[1].wakeup_ports[0].bits.uop.debug_pc \n connect slots_1.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[1].wakeup_ports[0].bits.uop.is_rvc \n connect slots_1.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[1].wakeup_ports[0].bits.uop.debug_inst \n connect slots_1.io.wakeup_ports[0].bits.uop.inst, issue_slots[1].wakeup_ports[0].bits.uop.inst \n connect slots_1.io.wakeup_ports[0].valid, issue_slots[1].wakeup_ports[0].valid \n connect slots_1.io.wakeup_ports[1].bits.rebusy, issue_slots[1].wakeup_ports[1].bits.rebusy \n connect slots_1.io.wakeup_ports[1].bits.speculative_mask, issue_slots[1].wakeup_ports[1].bits.speculative_mask \n connect slots_1.io.wakeup_ports[1].bits.bypassable, issue_slots[1].wakeup_ports[1].bits.bypassable \n connect slots_1.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[1].wakeup_ports[1].bits.uop.debug_tsrc \n connect slots_1.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[1].wakeup_ports[1].bits.uop.debug_fsrc \n connect slots_1.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[1].wakeup_ports[1].bits.uop.bp_xcpt_if \n connect slots_1.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[1].wakeup_ports[1].bits.uop.bp_debug_if \n connect slots_1.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[1].wakeup_ports[1].bits.uop.xcpt_ma_if \n connect slots_1.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[1].wakeup_ports[1].bits.uop.xcpt_ae_if \n connect slots_1.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[1].wakeup_ports[1].bits.uop.xcpt_pf_if \n connect slots_1.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[1].wakeup_ports[1].bits.uop.fp_typ \n connect slots_1.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[1].wakeup_ports[1].bits.uop.fp_rm \n connect slots_1.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[1].wakeup_ports[1].bits.uop.fp_val \n connect slots_1.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[1].wakeup_ports[1].bits.uop.fcn_op \n connect slots_1.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[1].wakeup_ports[1].bits.uop.fcn_dw \n connect slots_1.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[1].wakeup_ports[1].bits.uop.frs3_en \n connect slots_1.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[1].wakeup_ports[1].bits.uop.lrs2_rtype \n connect slots_1.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[1].wakeup_ports[1].bits.uop.lrs1_rtype \n connect slots_1.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[1].wakeup_ports[1].bits.uop.dst_rtype \n connect slots_1.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[1].wakeup_ports[1].bits.uop.lrs3 \n connect slots_1.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[1].wakeup_ports[1].bits.uop.lrs2 \n connect slots_1.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[1].wakeup_ports[1].bits.uop.lrs1 \n connect slots_1.io.wakeup_ports[1].bits.uop.ldst, issue_slots[1].wakeup_ports[1].bits.uop.ldst \n connect slots_1.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[1].wakeup_ports[1].bits.uop.ldst_is_rs1 \n connect slots_1.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[1].wakeup_ports[1].bits.uop.csr_cmd \n connect slots_1.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[1].wakeup_ports[1].bits.uop.flush_on_commit \n connect slots_1.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[1].wakeup_ports[1].bits.uop.is_unique \n connect slots_1.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[1].wakeup_ports[1].bits.uop.uses_stq \n connect slots_1.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[1].wakeup_ports[1].bits.uop.uses_ldq \n connect slots_1.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[1].wakeup_ports[1].bits.uop.mem_signed \n connect slots_1.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[1].wakeup_ports[1].bits.uop.mem_size \n connect slots_1.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[1].wakeup_ports[1].bits.uop.mem_cmd \n connect slots_1.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[1].wakeup_ports[1].bits.uop.exc_cause \n connect slots_1.io.wakeup_ports[1].bits.uop.exception, issue_slots[1].wakeup_ports[1].bits.uop.exception \n connect slots_1.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[1].wakeup_ports[1].bits.uop.stale_pdst \n connect slots_1.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[1].wakeup_ports[1].bits.uop.ppred_busy \n connect slots_1.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[1].wakeup_ports[1].bits.uop.prs3_busy \n connect slots_1.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[1].wakeup_ports[1].bits.uop.prs2_busy \n connect slots_1.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[1].wakeup_ports[1].bits.uop.prs1_busy \n connect slots_1.io.wakeup_ports[1].bits.uop.ppred, issue_slots[1].wakeup_ports[1].bits.uop.ppred \n connect slots_1.io.wakeup_ports[1].bits.uop.prs3, issue_slots[1].wakeup_ports[1].bits.uop.prs3 \n connect slots_1.io.wakeup_ports[1].bits.uop.prs2, issue_slots[1].wakeup_ports[1].bits.uop.prs2 \n connect slots_1.io.wakeup_ports[1].bits.uop.prs1, issue_slots[1].wakeup_ports[1].bits.uop.prs1 \n connect slots_1.io.wakeup_ports[1].bits.uop.pdst, issue_slots[1].wakeup_ports[1].bits.uop.pdst \n connect slots_1.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[1].wakeup_ports[1].bits.uop.rxq_idx \n connect slots_1.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[1].wakeup_ports[1].bits.uop.stq_idx \n connect slots_1.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[1].wakeup_ports[1].bits.uop.ldq_idx \n connect slots_1.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[1].wakeup_ports[1].bits.uop.rob_idx \n connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.vec \n connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.wflags \n connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.sqrt \n connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.div \n connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.fma \n connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe \n connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.toint \n connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.fromint \n connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut \n connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn \n connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.swap23 \n connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.swap12 \n connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.ren3 \n connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.ren2 \n connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.ren1 \n connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.wen \n connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.ldst \n connect slots_1.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[1].wakeup_ports[1].bits.uop.op2_sel \n connect slots_1.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[1].wakeup_ports[1].bits.uop.op1_sel \n connect slots_1.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[1].wakeup_ports[1].bits.uop.imm_packed \n connect slots_1.io.wakeup_ports[1].bits.uop.pimm, issue_slots[1].wakeup_ports[1].bits.uop.pimm \n connect slots_1.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[1].wakeup_ports[1].bits.uop.imm_sel \n connect slots_1.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[1].wakeup_ports[1].bits.uop.imm_rename \n connect slots_1.io.wakeup_ports[1].bits.uop.taken, issue_slots[1].wakeup_ports[1].bits.uop.taken \n connect slots_1.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[1].wakeup_ports[1].bits.uop.pc_lob \n connect slots_1.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[1].wakeup_ports[1].bits.uop.edge_inst \n connect slots_1.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[1].wakeup_ports[1].bits.uop.ftq_idx \n connect slots_1.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[1].wakeup_ports[1].bits.uop.is_mov \n connect slots_1.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[1].wakeup_ports[1].bits.uop.is_rocc \n connect slots_1.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[1].wakeup_ports[1].bits.uop.is_sys_pc2epc \n connect slots_1.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[1].wakeup_ports[1].bits.uop.is_eret \n connect slots_1.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[1].wakeup_ports[1].bits.uop.is_amo \n connect slots_1.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[1].wakeup_ports[1].bits.uop.is_sfence \n connect slots_1.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[1].wakeup_ports[1].bits.uop.is_fencei \n connect slots_1.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[1].wakeup_ports[1].bits.uop.is_fence \n connect slots_1.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[1].wakeup_ports[1].bits.uop.is_sfb \n connect slots_1.io.wakeup_ports[1].bits.uop.br_type, issue_slots[1].wakeup_ports[1].bits.uop.br_type \n connect slots_1.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[1].wakeup_ports[1].bits.uop.br_tag \n connect slots_1.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[1].wakeup_ports[1].bits.uop.br_mask \n connect slots_1.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[1].wakeup_ports[1].bits.uop.dis_col_sel \n connect slots_1.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[1].wakeup_ports[1].bits.uop.iw_p3_bypass_hint \n connect slots_1.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[1].wakeup_ports[1].bits.uop.iw_p2_bypass_hint \n connect slots_1.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[1].wakeup_ports[1].bits.uop.iw_p1_bypass_hint \n connect slots_1.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[1].wakeup_ports[1].bits.uop.iw_p2_speculative_child \n connect slots_1.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[1].wakeup_ports[1].bits.uop.iw_p1_speculative_child \n connect slots_1.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[1].wakeup_ports[1].bits.uop.iw_issued_partial_dgen \n connect slots_1.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[1].wakeup_ports[1].bits.uop.iw_issued_partial_agen \n connect slots_1.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[1].wakeup_ports[1].bits.uop.iw_issued \n connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[0] \n connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[1] \n connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[2] \n connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[3] \n connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[4] \n connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[5] \n connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[6] \n connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[7] \n connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[8] \n connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[9] \n connect slots_1.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[1].wakeup_ports[1].bits.uop.iq_type[0] \n connect slots_1.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[1].wakeup_ports[1].bits.uop.iq_type[1] \n connect slots_1.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[1].wakeup_ports[1].bits.uop.iq_type[2] \n connect slots_1.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[1].wakeup_ports[1].bits.uop.iq_type[3] \n connect slots_1.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[1].wakeup_ports[1].bits.uop.debug_pc \n connect slots_1.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[1].wakeup_ports[1].bits.uop.is_rvc \n connect slots_1.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[1].wakeup_ports[1].bits.uop.debug_inst \n connect slots_1.io.wakeup_ports[1].bits.uop.inst, issue_slots[1].wakeup_ports[1].bits.uop.inst \n connect slots_1.io.wakeup_ports[1].valid, issue_slots[1].wakeup_ports[1].valid \n connect slots_1.io.wakeup_ports[2].bits.rebusy, issue_slots[1].wakeup_ports[2].bits.rebusy \n connect slots_1.io.wakeup_ports[2].bits.speculative_mask, issue_slots[1].wakeup_ports[2].bits.speculative_mask \n connect slots_1.io.wakeup_ports[2].bits.bypassable, issue_slots[1].wakeup_ports[2].bits.bypassable \n connect slots_1.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[1].wakeup_ports[2].bits.uop.debug_tsrc \n connect slots_1.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[1].wakeup_ports[2].bits.uop.debug_fsrc \n connect slots_1.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[1].wakeup_ports[2].bits.uop.bp_xcpt_if \n connect slots_1.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[1].wakeup_ports[2].bits.uop.bp_debug_if \n connect slots_1.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[1].wakeup_ports[2].bits.uop.xcpt_ma_if \n connect slots_1.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[1].wakeup_ports[2].bits.uop.xcpt_ae_if \n connect slots_1.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[1].wakeup_ports[2].bits.uop.xcpt_pf_if \n connect slots_1.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[1].wakeup_ports[2].bits.uop.fp_typ \n connect slots_1.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[1].wakeup_ports[2].bits.uop.fp_rm \n connect slots_1.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[1].wakeup_ports[2].bits.uop.fp_val \n connect slots_1.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[1].wakeup_ports[2].bits.uop.fcn_op \n connect slots_1.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[1].wakeup_ports[2].bits.uop.fcn_dw \n connect slots_1.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[1].wakeup_ports[2].bits.uop.frs3_en \n connect slots_1.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[1].wakeup_ports[2].bits.uop.lrs2_rtype \n connect slots_1.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[1].wakeup_ports[2].bits.uop.lrs1_rtype \n connect slots_1.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[1].wakeup_ports[2].bits.uop.dst_rtype \n connect slots_1.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[1].wakeup_ports[2].bits.uop.lrs3 \n connect slots_1.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[1].wakeup_ports[2].bits.uop.lrs2 \n connect slots_1.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[1].wakeup_ports[2].bits.uop.lrs1 \n connect slots_1.io.wakeup_ports[2].bits.uop.ldst, issue_slots[1].wakeup_ports[2].bits.uop.ldst \n connect slots_1.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[1].wakeup_ports[2].bits.uop.ldst_is_rs1 \n connect slots_1.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[1].wakeup_ports[2].bits.uop.csr_cmd \n connect slots_1.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[1].wakeup_ports[2].bits.uop.flush_on_commit \n connect slots_1.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[1].wakeup_ports[2].bits.uop.is_unique \n connect slots_1.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[1].wakeup_ports[2].bits.uop.uses_stq \n connect slots_1.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[1].wakeup_ports[2].bits.uop.uses_ldq \n connect slots_1.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[1].wakeup_ports[2].bits.uop.mem_signed \n connect slots_1.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[1].wakeup_ports[2].bits.uop.mem_size \n connect slots_1.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[1].wakeup_ports[2].bits.uop.mem_cmd \n connect slots_1.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[1].wakeup_ports[2].bits.uop.exc_cause \n connect slots_1.io.wakeup_ports[2].bits.uop.exception, issue_slots[1].wakeup_ports[2].bits.uop.exception \n connect slots_1.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[1].wakeup_ports[2].bits.uop.stale_pdst \n connect slots_1.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[1].wakeup_ports[2].bits.uop.ppred_busy \n connect slots_1.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[1].wakeup_ports[2].bits.uop.prs3_busy \n connect slots_1.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[1].wakeup_ports[2].bits.uop.prs2_busy \n connect slots_1.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[1].wakeup_ports[2].bits.uop.prs1_busy \n connect slots_1.io.wakeup_ports[2].bits.uop.ppred, issue_slots[1].wakeup_ports[2].bits.uop.ppred \n connect slots_1.io.wakeup_ports[2].bits.uop.prs3, issue_slots[1].wakeup_ports[2].bits.uop.prs3 \n connect slots_1.io.wakeup_ports[2].bits.uop.prs2, issue_slots[1].wakeup_ports[2].bits.uop.prs2 \n connect slots_1.io.wakeup_ports[2].bits.uop.prs1, issue_slots[1].wakeup_ports[2].bits.uop.prs1 \n connect slots_1.io.wakeup_ports[2].bits.uop.pdst, issue_slots[1].wakeup_ports[2].bits.uop.pdst \n connect slots_1.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[1].wakeup_ports[2].bits.uop.rxq_idx \n connect slots_1.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[1].wakeup_ports[2].bits.uop.stq_idx \n connect slots_1.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[1].wakeup_ports[2].bits.uop.ldq_idx \n connect slots_1.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[1].wakeup_ports[2].bits.uop.rob_idx \n connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.vec \n connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.wflags \n connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.sqrt \n connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.div \n connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.fma \n connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe \n connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.toint \n connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.fromint \n connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut \n connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn \n connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.swap23 \n connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.swap12 \n connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.ren3 \n connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.ren2 \n connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.ren1 \n connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.wen \n connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.ldst \n connect slots_1.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[1].wakeup_ports[2].bits.uop.op2_sel \n connect slots_1.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[1].wakeup_ports[2].bits.uop.op1_sel \n connect slots_1.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[1].wakeup_ports[2].bits.uop.imm_packed \n connect slots_1.io.wakeup_ports[2].bits.uop.pimm, issue_slots[1].wakeup_ports[2].bits.uop.pimm \n connect slots_1.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[1].wakeup_ports[2].bits.uop.imm_sel \n connect slots_1.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[1].wakeup_ports[2].bits.uop.imm_rename \n connect slots_1.io.wakeup_ports[2].bits.uop.taken, issue_slots[1].wakeup_ports[2].bits.uop.taken \n connect slots_1.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[1].wakeup_ports[2].bits.uop.pc_lob \n connect slots_1.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[1].wakeup_ports[2].bits.uop.edge_inst \n connect slots_1.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[1].wakeup_ports[2].bits.uop.ftq_idx \n connect slots_1.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[1].wakeup_ports[2].bits.uop.is_mov \n connect slots_1.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[1].wakeup_ports[2].bits.uop.is_rocc \n connect slots_1.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[1].wakeup_ports[2].bits.uop.is_sys_pc2epc \n connect slots_1.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[1].wakeup_ports[2].bits.uop.is_eret \n connect slots_1.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[1].wakeup_ports[2].bits.uop.is_amo \n connect slots_1.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[1].wakeup_ports[2].bits.uop.is_sfence \n connect slots_1.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[1].wakeup_ports[2].bits.uop.is_fencei \n connect slots_1.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[1].wakeup_ports[2].bits.uop.is_fence \n connect slots_1.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[1].wakeup_ports[2].bits.uop.is_sfb \n connect slots_1.io.wakeup_ports[2].bits.uop.br_type, issue_slots[1].wakeup_ports[2].bits.uop.br_type \n connect slots_1.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[1].wakeup_ports[2].bits.uop.br_tag \n connect slots_1.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[1].wakeup_ports[2].bits.uop.br_mask \n connect slots_1.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[1].wakeup_ports[2].bits.uop.dis_col_sel \n connect slots_1.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[1].wakeup_ports[2].bits.uop.iw_p3_bypass_hint \n connect slots_1.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[1].wakeup_ports[2].bits.uop.iw_p2_bypass_hint \n connect slots_1.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[1].wakeup_ports[2].bits.uop.iw_p1_bypass_hint \n connect slots_1.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[1].wakeup_ports[2].bits.uop.iw_p2_speculative_child \n connect slots_1.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[1].wakeup_ports[2].bits.uop.iw_p1_speculative_child \n connect slots_1.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[1].wakeup_ports[2].bits.uop.iw_issued_partial_dgen \n connect slots_1.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[1].wakeup_ports[2].bits.uop.iw_issued_partial_agen \n connect slots_1.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[1].wakeup_ports[2].bits.uop.iw_issued \n connect slots_1.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[1].wakeup_ports[2].bits.uop.fu_code[0] \n connect slots_1.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[1].wakeup_ports[2].bits.uop.fu_code[1] \n connect slots_1.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[1].wakeup_ports[2].bits.uop.fu_code[2] \n connect slots_1.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[1].wakeup_ports[2].bits.uop.fu_code[3] \n connect slots_1.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[1].wakeup_ports[2].bits.uop.fu_code[4] \n connect slots_1.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[1].wakeup_ports[2].bits.uop.fu_code[5] \n connect slots_1.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[1].wakeup_ports[2].bits.uop.fu_code[6] \n connect slots_1.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[1].wakeup_ports[2].bits.uop.fu_code[7] \n connect slots_1.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[1].wakeup_ports[2].bits.uop.fu_code[8] \n connect slots_1.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[1].wakeup_ports[2].bits.uop.fu_code[9] \n connect slots_1.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[1].wakeup_ports[2].bits.uop.iq_type[0] \n connect slots_1.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[1].wakeup_ports[2].bits.uop.iq_type[1] \n connect slots_1.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[1].wakeup_ports[2].bits.uop.iq_type[2] \n connect slots_1.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[1].wakeup_ports[2].bits.uop.iq_type[3] \n connect slots_1.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[1].wakeup_ports[2].bits.uop.debug_pc \n connect slots_1.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[1].wakeup_ports[2].bits.uop.is_rvc \n connect slots_1.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[1].wakeup_ports[2].bits.uop.debug_inst \n connect slots_1.io.wakeup_ports[2].bits.uop.inst, issue_slots[1].wakeup_ports[2].bits.uop.inst \n connect slots_1.io.wakeup_ports[2].valid, issue_slots[1].wakeup_ports[2].valid \n connect slots_1.io.wakeup_ports[3].bits.rebusy, issue_slots[1].wakeup_ports[3].bits.rebusy \n connect slots_1.io.wakeup_ports[3].bits.speculative_mask, issue_slots[1].wakeup_ports[3].bits.speculative_mask \n connect slots_1.io.wakeup_ports[3].bits.bypassable, issue_slots[1].wakeup_ports[3].bits.bypassable \n connect slots_1.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[1].wakeup_ports[3].bits.uop.debug_tsrc \n connect slots_1.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[1].wakeup_ports[3].bits.uop.debug_fsrc \n connect slots_1.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[1].wakeup_ports[3].bits.uop.bp_xcpt_if \n connect slots_1.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[1].wakeup_ports[3].bits.uop.bp_debug_if \n connect slots_1.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[1].wakeup_ports[3].bits.uop.xcpt_ma_if \n connect slots_1.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[1].wakeup_ports[3].bits.uop.xcpt_ae_if \n connect slots_1.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[1].wakeup_ports[3].bits.uop.xcpt_pf_if \n connect slots_1.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[1].wakeup_ports[3].bits.uop.fp_typ \n connect slots_1.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[1].wakeup_ports[3].bits.uop.fp_rm \n connect slots_1.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[1].wakeup_ports[3].bits.uop.fp_val \n connect slots_1.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[1].wakeup_ports[3].bits.uop.fcn_op \n connect slots_1.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[1].wakeup_ports[3].bits.uop.fcn_dw \n connect slots_1.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[1].wakeup_ports[3].bits.uop.frs3_en \n connect slots_1.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[1].wakeup_ports[3].bits.uop.lrs2_rtype \n connect slots_1.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[1].wakeup_ports[3].bits.uop.lrs1_rtype \n connect slots_1.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[1].wakeup_ports[3].bits.uop.dst_rtype \n connect slots_1.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[1].wakeup_ports[3].bits.uop.lrs3 \n connect slots_1.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[1].wakeup_ports[3].bits.uop.lrs2 \n connect slots_1.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[1].wakeup_ports[3].bits.uop.lrs1 \n connect slots_1.io.wakeup_ports[3].bits.uop.ldst, issue_slots[1].wakeup_ports[3].bits.uop.ldst \n connect slots_1.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[1].wakeup_ports[3].bits.uop.ldst_is_rs1 \n connect slots_1.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[1].wakeup_ports[3].bits.uop.csr_cmd \n connect slots_1.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[1].wakeup_ports[3].bits.uop.flush_on_commit \n connect slots_1.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[1].wakeup_ports[3].bits.uop.is_unique \n connect slots_1.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[1].wakeup_ports[3].bits.uop.uses_stq \n connect slots_1.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[1].wakeup_ports[3].bits.uop.uses_ldq \n connect slots_1.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[1].wakeup_ports[3].bits.uop.mem_signed \n connect slots_1.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[1].wakeup_ports[3].bits.uop.mem_size \n connect slots_1.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[1].wakeup_ports[3].bits.uop.mem_cmd \n connect slots_1.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[1].wakeup_ports[3].bits.uop.exc_cause \n connect slots_1.io.wakeup_ports[3].bits.uop.exception, issue_slots[1].wakeup_ports[3].bits.uop.exception \n connect slots_1.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[1].wakeup_ports[3].bits.uop.stale_pdst \n connect slots_1.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[1].wakeup_ports[3].bits.uop.ppred_busy \n connect slots_1.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[1].wakeup_ports[3].bits.uop.prs3_busy \n connect slots_1.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[1].wakeup_ports[3].bits.uop.prs2_busy \n connect slots_1.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[1].wakeup_ports[3].bits.uop.prs1_busy \n connect slots_1.io.wakeup_ports[3].bits.uop.ppred, issue_slots[1].wakeup_ports[3].bits.uop.ppred \n connect slots_1.io.wakeup_ports[3].bits.uop.prs3, issue_slots[1].wakeup_ports[3].bits.uop.prs3 \n connect slots_1.io.wakeup_ports[3].bits.uop.prs2, issue_slots[1].wakeup_ports[3].bits.uop.prs2 \n connect slots_1.io.wakeup_ports[3].bits.uop.prs1, issue_slots[1].wakeup_ports[3].bits.uop.prs1 \n connect slots_1.io.wakeup_ports[3].bits.uop.pdst, issue_slots[1].wakeup_ports[3].bits.uop.pdst \n connect slots_1.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[1].wakeup_ports[3].bits.uop.rxq_idx \n connect slots_1.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[1].wakeup_ports[3].bits.uop.stq_idx \n connect slots_1.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[1].wakeup_ports[3].bits.uop.ldq_idx \n connect slots_1.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[1].wakeup_ports[3].bits.uop.rob_idx \n connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.vec \n connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.wflags \n connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.sqrt \n connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.div \n connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.fma \n connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe \n connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.toint \n connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.fromint \n connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut \n connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn \n connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.swap23 \n connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.swap12 \n connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.ren3 \n connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.ren2 \n connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.ren1 \n connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.wen \n connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.ldst \n connect slots_1.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[1].wakeup_ports[3].bits.uop.op2_sel \n connect slots_1.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[1].wakeup_ports[3].bits.uop.op1_sel \n connect slots_1.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[1].wakeup_ports[3].bits.uop.imm_packed \n connect slots_1.io.wakeup_ports[3].bits.uop.pimm, issue_slots[1].wakeup_ports[3].bits.uop.pimm \n connect slots_1.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[1].wakeup_ports[3].bits.uop.imm_sel \n connect slots_1.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[1].wakeup_ports[3].bits.uop.imm_rename \n connect slots_1.io.wakeup_ports[3].bits.uop.taken, issue_slots[1].wakeup_ports[3].bits.uop.taken \n connect slots_1.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[1].wakeup_ports[3].bits.uop.pc_lob \n connect slots_1.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[1].wakeup_ports[3].bits.uop.edge_inst \n connect slots_1.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[1].wakeup_ports[3].bits.uop.ftq_idx \n connect slots_1.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[1].wakeup_ports[3].bits.uop.is_mov \n connect slots_1.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[1].wakeup_ports[3].bits.uop.is_rocc \n connect slots_1.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[1].wakeup_ports[3].bits.uop.is_sys_pc2epc \n connect slots_1.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[1].wakeup_ports[3].bits.uop.is_eret \n connect slots_1.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[1].wakeup_ports[3].bits.uop.is_amo \n connect slots_1.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[1].wakeup_ports[3].bits.uop.is_sfence \n connect slots_1.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[1].wakeup_ports[3].bits.uop.is_fencei \n connect slots_1.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[1].wakeup_ports[3].bits.uop.is_fence \n connect slots_1.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[1].wakeup_ports[3].bits.uop.is_sfb \n connect slots_1.io.wakeup_ports[3].bits.uop.br_type, issue_slots[1].wakeup_ports[3].bits.uop.br_type \n connect slots_1.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[1].wakeup_ports[3].bits.uop.br_tag \n connect slots_1.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[1].wakeup_ports[3].bits.uop.br_mask \n connect slots_1.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[1].wakeup_ports[3].bits.uop.dis_col_sel \n connect slots_1.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[1].wakeup_ports[3].bits.uop.iw_p3_bypass_hint \n connect slots_1.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[1].wakeup_ports[3].bits.uop.iw_p2_bypass_hint \n connect slots_1.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[1].wakeup_ports[3].bits.uop.iw_p1_bypass_hint \n connect slots_1.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[1].wakeup_ports[3].bits.uop.iw_p2_speculative_child \n connect slots_1.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[1].wakeup_ports[3].bits.uop.iw_p1_speculative_child \n connect slots_1.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[1].wakeup_ports[3].bits.uop.iw_issued_partial_dgen \n connect slots_1.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[1].wakeup_ports[3].bits.uop.iw_issued_partial_agen \n connect slots_1.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[1].wakeup_ports[3].bits.uop.iw_issued \n connect slots_1.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[1].wakeup_ports[3].bits.uop.fu_code[0] \n connect slots_1.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[1].wakeup_ports[3].bits.uop.fu_code[1] \n connect slots_1.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[1].wakeup_ports[3].bits.uop.fu_code[2] \n connect slots_1.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[1].wakeup_ports[3].bits.uop.fu_code[3] \n connect slots_1.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[1].wakeup_ports[3].bits.uop.fu_code[4] \n connect slots_1.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[1].wakeup_ports[3].bits.uop.fu_code[5] \n connect slots_1.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[1].wakeup_ports[3].bits.uop.fu_code[6] \n connect slots_1.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[1].wakeup_ports[3].bits.uop.fu_code[7] \n connect slots_1.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[1].wakeup_ports[3].bits.uop.fu_code[8] \n connect slots_1.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[1].wakeup_ports[3].bits.uop.fu_code[9] \n connect slots_1.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[1].wakeup_ports[3].bits.uop.iq_type[0] \n connect slots_1.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[1].wakeup_ports[3].bits.uop.iq_type[1] \n connect slots_1.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[1].wakeup_ports[3].bits.uop.iq_type[2] \n connect slots_1.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[1].wakeup_ports[3].bits.uop.iq_type[3] \n connect slots_1.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[1].wakeup_ports[3].bits.uop.debug_pc \n connect slots_1.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[1].wakeup_ports[3].bits.uop.is_rvc \n connect slots_1.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[1].wakeup_ports[3].bits.uop.debug_inst \n connect slots_1.io.wakeup_ports[3].bits.uop.inst, issue_slots[1].wakeup_ports[3].bits.uop.inst \n connect slots_1.io.wakeup_ports[3].valid, issue_slots[1].wakeup_ports[3].valid \n connect slots_1.io.squash_grant, issue_slots[1].squash_grant \n connect slots_1.io.clear, issue_slots[1].clear \n connect slots_1.io.kill, issue_slots[1].kill \n connect slots_1.io.brupdate.b2.target_offset, issue_slots[1].brupdate.b2.target_offset \n connect slots_1.io.brupdate.b2.jalr_target, issue_slots[1].brupdate.b2.jalr_target \n connect slots_1.io.brupdate.b2.pc_sel, issue_slots[1].brupdate.b2.pc_sel \n connect slots_1.io.brupdate.b2.cfi_type, issue_slots[1].brupdate.b2.cfi_type \n connect slots_1.io.brupdate.b2.taken, issue_slots[1].brupdate.b2.taken \n connect slots_1.io.brupdate.b2.mispredict, issue_slots[1].brupdate.b2.mispredict \n connect slots_1.io.brupdate.b2.uop.debug_tsrc, issue_slots[1].brupdate.b2.uop.debug_tsrc \n connect slots_1.io.brupdate.b2.uop.debug_fsrc, issue_slots[1].brupdate.b2.uop.debug_fsrc \n connect slots_1.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[1].brupdate.b2.uop.bp_xcpt_if \n connect slots_1.io.brupdate.b2.uop.bp_debug_if, issue_slots[1].brupdate.b2.uop.bp_debug_if \n connect slots_1.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[1].brupdate.b2.uop.xcpt_ma_if \n connect slots_1.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[1].brupdate.b2.uop.xcpt_ae_if \n connect slots_1.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[1].brupdate.b2.uop.xcpt_pf_if \n connect slots_1.io.brupdate.b2.uop.fp_typ, issue_slots[1].brupdate.b2.uop.fp_typ \n connect slots_1.io.brupdate.b2.uop.fp_rm, issue_slots[1].brupdate.b2.uop.fp_rm \n connect slots_1.io.brupdate.b2.uop.fp_val, issue_slots[1].brupdate.b2.uop.fp_val \n connect slots_1.io.brupdate.b2.uop.fcn_op, issue_slots[1].brupdate.b2.uop.fcn_op \n connect slots_1.io.brupdate.b2.uop.fcn_dw, issue_slots[1].brupdate.b2.uop.fcn_dw \n connect slots_1.io.brupdate.b2.uop.frs3_en, issue_slots[1].brupdate.b2.uop.frs3_en \n connect slots_1.io.brupdate.b2.uop.lrs2_rtype, issue_slots[1].brupdate.b2.uop.lrs2_rtype \n connect slots_1.io.brupdate.b2.uop.lrs1_rtype, issue_slots[1].brupdate.b2.uop.lrs1_rtype \n connect slots_1.io.brupdate.b2.uop.dst_rtype, issue_slots[1].brupdate.b2.uop.dst_rtype \n connect slots_1.io.brupdate.b2.uop.lrs3, issue_slots[1].brupdate.b2.uop.lrs3 \n connect slots_1.io.brupdate.b2.uop.lrs2, issue_slots[1].brupdate.b2.uop.lrs2 \n connect slots_1.io.brupdate.b2.uop.lrs1, issue_slots[1].brupdate.b2.uop.lrs1 \n connect slots_1.io.brupdate.b2.uop.ldst, issue_slots[1].brupdate.b2.uop.ldst \n connect slots_1.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[1].brupdate.b2.uop.ldst_is_rs1 \n connect slots_1.io.brupdate.b2.uop.csr_cmd, issue_slots[1].brupdate.b2.uop.csr_cmd \n connect slots_1.io.brupdate.b2.uop.flush_on_commit, issue_slots[1].brupdate.b2.uop.flush_on_commit \n connect slots_1.io.brupdate.b2.uop.is_unique, issue_slots[1].brupdate.b2.uop.is_unique \n connect slots_1.io.brupdate.b2.uop.uses_stq, issue_slots[1].brupdate.b2.uop.uses_stq \n connect slots_1.io.brupdate.b2.uop.uses_ldq, issue_slots[1].brupdate.b2.uop.uses_ldq \n connect slots_1.io.brupdate.b2.uop.mem_signed, issue_slots[1].brupdate.b2.uop.mem_signed \n connect slots_1.io.brupdate.b2.uop.mem_size, issue_slots[1].brupdate.b2.uop.mem_size \n connect slots_1.io.brupdate.b2.uop.mem_cmd, issue_slots[1].brupdate.b2.uop.mem_cmd \n connect slots_1.io.brupdate.b2.uop.exc_cause, issue_slots[1].brupdate.b2.uop.exc_cause \n connect slots_1.io.brupdate.b2.uop.exception, issue_slots[1].brupdate.b2.uop.exception \n connect slots_1.io.brupdate.b2.uop.stale_pdst, issue_slots[1].brupdate.b2.uop.stale_pdst \n connect slots_1.io.brupdate.b2.uop.ppred_busy, issue_slots[1].brupdate.b2.uop.ppred_busy \n connect slots_1.io.brupdate.b2.uop.prs3_busy, issue_slots[1].brupdate.b2.uop.prs3_busy \n connect slots_1.io.brupdate.b2.uop.prs2_busy, issue_slots[1].brupdate.b2.uop.prs2_busy \n connect slots_1.io.brupdate.b2.uop.prs1_busy, issue_slots[1].brupdate.b2.uop.prs1_busy \n connect slots_1.io.brupdate.b2.uop.ppred, issue_slots[1].brupdate.b2.uop.ppred \n connect slots_1.io.brupdate.b2.uop.prs3, issue_slots[1].brupdate.b2.uop.prs3 \n connect slots_1.io.brupdate.b2.uop.prs2, issue_slots[1].brupdate.b2.uop.prs2 \n connect slots_1.io.brupdate.b2.uop.prs1, issue_slots[1].brupdate.b2.uop.prs1 \n connect slots_1.io.brupdate.b2.uop.pdst, issue_slots[1].brupdate.b2.uop.pdst \n connect slots_1.io.brupdate.b2.uop.rxq_idx, issue_slots[1].brupdate.b2.uop.rxq_idx \n connect slots_1.io.brupdate.b2.uop.stq_idx, issue_slots[1].brupdate.b2.uop.stq_idx \n connect slots_1.io.brupdate.b2.uop.ldq_idx, issue_slots[1].brupdate.b2.uop.ldq_idx \n connect slots_1.io.brupdate.b2.uop.rob_idx, issue_slots[1].brupdate.b2.uop.rob_idx \n connect slots_1.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[1].brupdate.b2.uop.fp_ctrl.vec \n connect slots_1.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[1].brupdate.b2.uop.fp_ctrl.wflags \n connect slots_1.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[1].brupdate.b2.uop.fp_ctrl.sqrt \n connect slots_1.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[1].brupdate.b2.uop.fp_ctrl.div \n connect slots_1.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[1].brupdate.b2.uop.fp_ctrl.fma \n connect slots_1.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[1].brupdate.b2.uop.fp_ctrl.fastpipe \n connect slots_1.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[1].brupdate.b2.uop.fp_ctrl.toint \n connect slots_1.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[1].brupdate.b2.uop.fp_ctrl.fromint \n connect slots_1.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[1].brupdate.b2.uop.fp_ctrl.typeTagOut \n connect slots_1.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[1].brupdate.b2.uop.fp_ctrl.typeTagIn \n connect slots_1.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[1].brupdate.b2.uop.fp_ctrl.swap23 \n connect slots_1.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[1].brupdate.b2.uop.fp_ctrl.swap12 \n connect slots_1.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[1].brupdate.b2.uop.fp_ctrl.ren3 \n connect slots_1.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[1].brupdate.b2.uop.fp_ctrl.ren2 \n connect slots_1.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[1].brupdate.b2.uop.fp_ctrl.ren1 \n connect slots_1.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[1].brupdate.b2.uop.fp_ctrl.wen \n connect slots_1.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[1].brupdate.b2.uop.fp_ctrl.ldst \n connect slots_1.io.brupdate.b2.uop.op2_sel, issue_slots[1].brupdate.b2.uop.op2_sel \n connect slots_1.io.brupdate.b2.uop.op1_sel, issue_slots[1].brupdate.b2.uop.op1_sel \n connect slots_1.io.brupdate.b2.uop.imm_packed, issue_slots[1].brupdate.b2.uop.imm_packed \n connect slots_1.io.brupdate.b2.uop.pimm, issue_slots[1].brupdate.b2.uop.pimm \n connect slots_1.io.brupdate.b2.uop.imm_sel, issue_slots[1].brupdate.b2.uop.imm_sel \n connect slots_1.io.brupdate.b2.uop.imm_rename, issue_slots[1].brupdate.b2.uop.imm_rename \n connect slots_1.io.brupdate.b2.uop.taken, issue_slots[1].brupdate.b2.uop.taken \n connect slots_1.io.brupdate.b2.uop.pc_lob, issue_slots[1].brupdate.b2.uop.pc_lob \n connect slots_1.io.brupdate.b2.uop.edge_inst, issue_slots[1].brupdate.b2.uop.edge_inst \n connect slots_1.io.brupdate.b2.uop.ftq_idx, issue_slots[1].brupdate.b2.uop.ftq_idx \n connect slots_1.io.brupdate.b2.uop.is_mov, issue_slots[1].brupdate.b2.uop.is_mov \n connect slots_1.io.brupdate.b2.uop.is_rocc, issue_slots[1].brupdate.b2.uop.is_rocc \n connect slots_1.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[1].brupdate.b2.uop.is_sys_pc2epc \n connect slots_1.io.brupdate.b2.uop.is_eret, issue_slots[1].brupdate.b2.uop.is_eret \n connect slots_1.io.brupdate.b2.uop.is_amo, issue_slots[1].brupdate.b2.uop.is_amo \n connect slots_1.io.brupdate.b2.uop.is_sfence, issue_slots[1].brupdate.b2.uop.is_sfence \n connect slots_1.io.brupdate.b2.uop.is_fencei, issue_slots[1].brupdate.b2.uop.is_fencei \n connect slots_1.io.brupdate.b2.uop.is_fence, issue_slots[1].brupdate.b2.uop.is_fence \n connect slots_1.io.brupdate.b2.uop.is_sfb, issue_slots[1].brupdate.b2.uop.is_sfb \n connect slots_1.io.brupdate.b2.uop.br_type, issue_slots[1].brupdate.b2.uop.br_type \n connect slots_1.io.brupdate.b2.uop.br_tag, issue_slots[1].brupdate.b2.uop.br_tag \n connect slots_1.io.brupdate.b2.uop.br_mask, issue_slots[1].brupdate.b2.uop.br_mask \n connect slots_1.io.brupdate.b2.uop.dis_col_sel, issue_slots[1].brupdate.b2.uop.dis_col_sel \n connect slots_1.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[1].brupdate.b2.uop.iw_p3_bypass_hint \n connect slots_1.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[1].brupdate.b2.uop.iw_p2_bypass_hint \n connect slots_1.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[1].brupdate.b2.uop.iw_p1_bypass_hint \n connect slots_1.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[1].brupdate.b2.uop.iw_p2_speculative_child \n connect slots_1.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[1].brupdate.b2.uop.iw_p1_speculative_child \n connect slots_1.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[1].brupdate.b2.uop.iw_issued_partial_dgen \n connect slots_1.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[1].brupdate.b2.uop.iw_issued_partial_agen \n connect slots_1.io.brupdate.b2.uop.iw_issued, issue_slots[1].brupdate.b2.uop.iw_issued \n connect slots_1.io.brupdate.b2.uop.fu_code[0], issue_slots[1].brupdate.b2.uop.fu_code[0] \n connect slots_1.io.brupdate.b2.uop.fu_code[1], issue_slots[1].brupdate.b2.uop.fu_code[1] \n connect slots_1.io.brupdate.b2.uop.fu_code[2], issue_slots[1].brupdate.b2.uop.fu_code[2] \n connect slots_1.io.brupdate.b2.uop.fu_code[3], issue_slots[1].brupdate.b2.uop.fu_code[3] \n connect slots_1.io.brupdate.b2.uop.fu_code[4], issue_slots[1].brupdate.b2.uop.fu_code[4] \n connect slots_1.io.brupdate.b2.uop.fu_code[5], issue_slots[1].brupdate.b2.uop.fu_code[5] \n connect slots_1.io.brupdate.b2.uop.fu_code[6], issue_slots[1].brupdate.b2.uop.fu_code[6] \n connect slots_1.io.brupdate.b2.uop.fu_code[7], issue_slots[1].brupdate.b2.uop.fu_code[7] \n connect slots_1.io.brupdate.b2.uop.fu_code[8], issue_slots[1].brupdate.b2.uop.fu_code[8] \n connect slots_1.io.brupdate.b2.uop.fu_code[9], issue_slots[1].brupdate.b2.uop.fu_code[9] \n connect slots_1.io.brupdate.b2.uop.iq_type[0], issue_slots[1].brupdate.b2.uop.iq_type[0] \n connect slots_1.io.brupdate.b2.uop.iq_type[1], issue_slots[1].brupdate.b2.uop.iq_type[1] \n connect slots_1.io.brupdate.b2.uop.iq_type[2], issue_slots[1].brupdate.b2.uop.iq_type[2] \n connect slots_1.io.brupdate.b2.uop.iq_type[3], issue_slots[1].brupdate.b2.uop.iq_type[3] \n connect slots_1.io.brupdate.b2.uop.debug_pc, issue_slots[1].brupdate.b2.uop.debug_pc \n connect slots_1.io.brupdate.b2.uop.is_rvc, issue_slots[1].brupdate.b2.uop.is_rvc \n connect slots_1.io.brupdate.b2.uop.debug_inst, issue_slots[1].brupdate.b2.uop.debug_inst \n connect slots_1.io.brupdate.b2.uop.inst, issue_slots[1].brupdate.b2.uop.inst \n connect slots_1.io.brupdate.b1.mispredict_mask, issue_slots[1].brupdate.b1.mispredict_mask \n connect slots_1.io.brupdate.b1.resolve_mask, issue_slots[1].brupdate.b1.resolve_mask \n connect issue_slots[1].out_uop.debug_tsrc, slots_1.io.out_uop.debug_tsrc \n connect issue_slots[1].out_uop.debug_fsrc, slots_1.io.out_uop.debug_fsrc \n connect issue_slots[1].out_uop.bp_xcpt_if, slots_1.io.out_uop.bp_xcpt_if \n connect issue_slots[1].out_uop.bp_debug_if, slots_1.io.out_uop.bp_debug_if \n connect issue_slots[1].out_uop.xcpt_ma_if, slots_1.io.out_uop.xcpt_ma_if \n connect issue_slots[1].out_uop.xcpt_ae_if, slots_1.io.out_uop.xcpt_ae_if \n connect issue_slots[1].out_uop.xcpt_pf_if, slots_1.io.out_uop.xcpt_pf_if \n connect issue_slots[1].out_uop.fp_typ, slots_1.io.out_uop.fp_typ \n connect issue_slots[1].out_uop.fp_rm, slots_1.io.out_uop.fp_rm \n connect issue_slots[1].out_uop.fp_val, slots_1.io.out_uop.fp_val \n connect issue_slots[1].out_uop.fcn_op, slots_1.io.out_uop.fcn_op \n connect issue_slots[1].out_uop.fcn_dw, slots_1.io.out_uop.fcn_dw \n connect issue_slots[1].out_uop.frs3_en, slots_1.io.out_uop.frs3_en \n connect issue_slots[1].out_uop.lrs2_rtype, slots_1.io.out_uop.lrs2_rtype \n connect issue_slots[1].out_uop.lrs1_rtype, slots_1.io.out_uop.lrs1_rtype \n connect issue_slots[1].out_uop.dst_rtype, slots_1.io.out_uop.dst_rtype \n connect issue_slots[1].out_uop.lrs3, slots_1.io.out_uop.lrs3 \n connect issue_slots[1].out_uop.lrs2, slots_1.io.out_uop.lrs2 \n connect issue_slots[1].out_uop.lrs1, slots_1.io.out_uop.lrs1 \n connect issue_slots[1].out_uop.ldst, slots_1.io.out_uop.ldst \n connect issue_slots[1].out_uop.ldst_is_rs1, slots_1.io.out_uop.ldst_is_rs1 \n connect issue_slots[1].out_uop.csr_cmd, slots_1.io.out_uop.csr_cmd \n connect issue_slots[1].out_uop.flush_on_commit, slots_1.io.out_uop.flush_on_commit \n connect issue_slots[1].out_uop.is_unique, slots_1.io.out_uop.is_unique \n connect issue_slots[1].out_uop.uses_stq, slots_1.io.out_uop.uses_stq \n connect issue_slots[1].out_uop.uses_ldq, slots_1.io.out_uop.uses_ldq \n connect issue_slots[1].out_uop.mem_signed, slots_1.io.out_uop.mem_signed \n connect issue_slots[1].out_uop.mem_size, slots_1.io.out_uop.mem_size \n connect issue_slots[1].out_uop.mem_cmd, slots_1.io.out_uop.mem_cmd \n connect issue_slots[1].out_uop.exc_cause, slots_1.io.out_uop.exc_cause \n connect issue_slots[1].out_uop.exception, slots_1.io.out_uop.exception \n connect issue_slots[1].out_uop.stale_pdst, slots_1.io.out_uop.stale_pdst \n connect issue_slots[1].out_uop.ppred_busy, slots_1.io.out_uop.ppred_busy \n connect issue_slots[1].out_uop.prs3_busy, slots_1.io.out_uop.prs3_busy \n connect issue_slots[1].out_uop.prs2_busy, slots_1.io.out_uop.prs2_busy \n connect issue_slots[1].out_uop.prs1_busy, slots_1.io.out_uop.prs1_busy \n connect issue_slots[1].out_uop.ppred, slots_1.io.out_uop.ppred \n connect issue_slots[1].out_uop.prs3, slots_1.io.out_uop.prs3 \n connect issue_slots[1].out_uop.prs2, slots_1.io.out_uop.prs2 \n connect issue_slots[1].out_uop.prs1, slots_1.io.out_uop.prs1 \n connect issue_slots[1].out_uop.pdst, slots_1.io.out_uop.pdst \n connect issue_slots[1].out_uop.rxq_idx, slots_1.io.out_uop.rxq_idx \n connect issue_slots[1].out_uop.stq_idx, slots_1.io.out_uop.stq_idx \n connect issue_slots[1].out_uop.ldq_idx, slots_1.io.out_uop.ldq_idx \n connect issue_slots[1].out_uop.rob_idx, slots_1.io.out_uop.rob_idx \n connect issue_slots[1].out_uop.fp_ctrl.vec, slots_1.io.out_uop.fp_ctrl.vec \n connect issue_slots[1].out_uop.fp_ctrl.wflags, slots_1.io.out_uop.fp_ctrl.wflags \n connect issue_slots[1].out_uop.fp_ctrl.sqrt, slots_1.io.out_uop.fp_ctrl.sqrt \n connect issue_slots[1].out_uop.fp_ctrl.div, slots_1.io.out_uop.fp_ctrl.div \n connect issue_slots[1].out_uop.fp_ctrl.fma, slots_1.io.out_uop.fp_ctrl.fma \n connect issue_slots[1].out_uop.fp_ctrl.fastpipe, slots_1.io.out_uop.fp_ctrl.fastpipe \n connect issue_slots[1].out_uop.fp_ctrl.toint, slots_1.io.out_uop.fp_ctrl.toint \n connect issue_slots[1].out_uop.fp_ctrl.fromint, slots_1.io.out_uop.fp_ctrl.fromint \n connect issue_slots[1].out_uop.fp_ctrl.typeTagOut, slots_1.io.out_uop.fp_ctrl.typeTagOut \n connect issue_slots[1].out_uop.fp_ctrl.typeTagIn, slots_1.io.out_uop.fp_ctrl.typeTagIn \n connect issue_slots[1].out_uop.fp_ctrl.swap23, slots_1.io.out_uop.fp_ctrl.swap23 \n connect issue_slots[1].out_uop.fp_ctrl.swap12, slots_1.io.out_uop.fp_ctrl.swap12 \n connect issue_slots[1].out_uop.fp_ctrl.ren3, slots_1.io.out_uop.fp_ctrl.ren3 \n connect issue_slots[1].out_uop.fp_ctrl.ren2, slots_1.io.out_uop.fp_ctrl.ren2 \n connect issue_slots[1].out_uop.fp_ctrl.ren1, slots_1.io.out_uop.fp_ctrl.ren1 \n connect issue_slots[1].out_uop.fp_ctrl.wen, slots_1.io.out_uop.fp_ctrl.wen \n connect issue_slots[1].out_uop.fp_ctrl.ldst, slots_1.io.out_uop.fp_ctrl.ldst \n connect issue_slots[1].out_uop.op2_sel, slots_1.io.out_uop.op2_sel \n connect issue_slots[1].out_uop.op1_sel, slots_1.io.out_uop.op1_sel \n connect issue_slots[1].out_uop.imm_packed, slots_1.io.out_uop.imm_packed \n connect issue_slots[1].out_uop.pimm, slots_1.io.out_uop.pimm \n connect issue_slots[1].out_uop.imm_sel, slots_1.io.out_uop.imm_sel \n connect issue_slots[1].out_uop.imm_rename, slots_1.io.out_uop.imm_rename \n connect issue_slots[1].out_uop.taken, slots_1.io.out_uop.taken \n connect issue_slots[1].out_uop.pc_lob, slots_1.io.out_uop.pc_lob \n connect issue_slots[1].out_uop.edge_inst, slots_1.io.out_uop.edge_inst \n connect issue_slots[1].out_uop.ftq_idx, slots_1.io.out_uop.ftq_idx \n connect issue_slots[1].out_uop.is_mov, slots_1.io.out_uop.is_mov \n connect issue_slots[1].out_uop.is_rocc, slots_1.io.out_uop.is_rocc \n connect issue_slots[1].out_uop.is_sys_pc2epc, slots_1.io.out_uop.is_sys_pc2epc \n connect issue_slots[1].out_uop.is_eret, slots_1.io.out_uop.is_eret \n connect issue_slots[1].out_uop.is_amo, slots_1.io.out_uop.is_amo \n connect issue_slots[1].out_uop.is_sfence, slots_1.io.out_uop.is_sfence \n connect issue_slots[1].out_uop.is_fencei, slots_1.io.out_uop.is_fencei \n connect issue_slots[1].out_uop.is_fence, slots_1.io.out_uop.is_fence \n connect issue_slots[1].out_uop.is_sfb, slots_1.io.out_uop.is_sfb \n connect issue_slots[1].out_uop.br_type, slots_1.io.out_uop.br_type \n connect issue_slots[1].out_uop.br_tag, slots_1.io.out_uop.br_tag \n connect issue_slots[1].out_uop.br_mask, slots_1.io.out_uop.br_mask \n connect issue_slots[1].out_uop.dis_col_sel, slots_1.io.out_uop.dis_col_sel \n connect issue_slots[1].out_uop.iw_p3_bypass_hint, slots_1.io.out_uop.iw_p3_bypass_hint \n connect issue_slots[1].out_uop.iw_p2_bypass_hint, slots_1.io.out_uop.iw_p2_bypass_hint \n connect issue_slots[1].out_uop.iw_p1_bypass_hint, slots_1.io.out_uop.iw_p1_bypass_hint \n connect issue_slots[1].out_uop.iw_p2_speculative_child, slots_1.io.out_uop.iw_p2_speculative_child \n connect issue_slots[1].out_uop.iw_p1_speculative_child, slots_1.io.out_uop.iw_p1_speculative_child \n connect issue_slots[1].out_uop.iw_issued_partial_dgen, slots_1.io.out_uop.iw_issued_partial_dgen \n connect issue_slots[1].out_uop.iw_issued_partial_agen, slots_1.io.out_uop.iw_issued_partial_agen \n connect issue_slots[1].out_uop.iw_issued, slots_1.io.out_uop.iw_issued \n connect issue_slots[1].out_uop.fu_code[0], slots_1.io.out_uop.fu_code[0] \n connect issue_slots[1].out_uop.fu_code[1], slots_1.io.out_uop.fu_code[1] \n connect issue_slots[1].out_uop.fu_code[2], slots_1.io.out_uop.fu_code[2] \n connect issue_slots[1].out_uop.fu_code[3], slots_1.io.out_uop.fu_code[3] \n connect issue_slots[1].out_uop.fu_code[4], slots_1.io.out_uop.fu_code[4] \n connect issue_slots[1].out_uop.fu_code[5], slots_1.io.out_uop.fu_code[5] \n connect issue_slots[1].out_uop.fu_code[6], slots_1.io.out_uop.fu_code[6] \n connect issue_slots[1].out_uop.fu_code[7], slots_1.io.out_uop.fu_code[7] \n connect issue_slots[1].out_uop.fu_code[8], slots_1.io.out_uop.fu_code[8] \n connect issue_slots[1].out_uop.fu_code[9], slots_1.io.out_uop.fu_code[9] \n connect issue_slots[1].out_uop.iq_type[0], slots_1.io.out_uop.iq_type[0] \n connect issue_slots[1].out_uop.iq_type[1], slots_1.io.out_uop.iq_type[1] \n connect issue_slots[1].out_uop.iq_type[2], slots_1.io.out_uop.iq_type[2] \n connect issue_slots[1].out_uop.iq_type[3], slots_1.io.out_uop.iq_type[3] \n connect issue_slots[1].out_uop.debug_pc, slots_1.io.out_uop.debug_pc \n connect issue_slots[1].out_uop.is_rvc, slots_1.io.out_uop.is_rvc \n connect issue_slots[1].out_uop.debug_inst, slots_1.io.out_uop.debug_inst \n connect issue_slots[1].out_uop.inst, slots_1.io.out_uop.inst \n connect slots_1.io.in_uop.bits.debug_tsrc, issue_slots[1].in_uop.bits.debug_tsrc \n connect slots_1.io.in_uop.bits.debug_fsrc, issue_slots[1].in_uop.bits.debug_fsrc \n connect slots_1.io.in_uop.bits.bp_xcpt_if, issue_slots[1].in_uop.bits.bp_xcpt_if \n connect slots_1.io.in_uop.bits.bp_debug_if, issue_slots[1].in_uop.bits.bp_debug_if \n connect slots_1.io.in_uop.bits.xcpt_ma_if, issue_slots[1].in_uop.bits.xcpt_ma_if \n connect slots_1.io.in_uop.bits.xcpt_ae_if, issue_slots[1].in_uop.bits.xcpt_ae_if \n connect slots_1.io.in_uop.bits.xcpt_pf_if, issue_slots[1].in_uop.bits.xcpt_pf_if \n connect slots_1.io.in_uop.bits.fp_typ, issue_slots[1].in_uop.bits.fp_typ \n connect slots_1.io.in_uop.bits.fp_rm, issue_slots[1].in_uop.bits.fp_rm \n connect slots_1.io.in_uop.bits.fp_val, issue_slots[1].in_uop.bits.fp_val \n connect slots_1.io.in_uop.bits.fcn_op, issue_slots[1].in_uop.bits.fcn_op \n connect slots_1.io.in_uop.bits.fcn_dw, issue_slots[1].in_uop.bits.fcn_dw \n connect slots_1.io.in_uop.bits.frs3_en, issue_slots[1].in_uop.bits.frs3_en \n connect slots_1.io.in_uop.bits.lrs2_rtype, issue_slots[1].in_uop.bits.lrs2_rtype \n connect slots_1.io.in_uop.bits.lrs1_rtype, issue_slots[1].in_uop.bits.lrs1_rtype \n connect slots_1.io.in_uop.bits.dst_rtype, issue_slots[1].in_uop.bits.dst_rtype \n connect slots_1.io.in_uop.bits.lrs3, issue_slots[1].in_uop.bits.lrs3 \n connect slots_1.io.in_uop.bits.lrs2, issue_slots[1].in_uop.bits.lrs2 \n connect slots_1.io.in_uop.bits.lrs1, issue_slots[1].in_uop.bits.lrs1 \n connect slots_1.io.in_uop.bits.ldst, issue_slots[1].in_uop.bits.ldst \n connect slots_1.io.in_uop.bits.ldst_is_rs1, issue_slots[1].in_uop.bits.ldst_is_rs1 \n connect slots_1.io.in_uop.bits.csr_cmd, issue_slots[1].in_uop.bits.csr_cmd \n connect slots_1.io.in_uop.bits.flush_on_commit, issue_slots[1].in_uop.bits.flush_on_commit \n connect slots_1.io.in_uop.bits.is_unique, issue_slots[1].in_uop.bits.is_unique \n connect slots_1.io.in_uop.bits.uses_stq, issue_slots[1].in_uop.bits.uses_stq \n connect slots_1.io.in_uop.bits.uses_ldq, issue_slots[1].in_uop.bits.uses_ldq \n connect slots_1.io.in_uop.bits.mem_signed, issue_slots[1].in_uop.bits.mem_signed \n connect slots_1.io.in_uop.bits.mem_size, issue_slots[1].in_uop.bits.mem_size \n connect slots_1.io.in_uop.bits.mem_cmd, issue_slots[1].in_uop.bits.mem_cmd \n connect slots_1.io.in_uop.bits.exc_cause, issue_slots[1].in_uop.bits.exc_cause \n connect slots_1.io.in_uop.bits.exception, issue_slots[1].in_uop.bits.exception \n connect slots_1.io.in_uop.bits.stale_pdst, issue_slots[1].in_uop.bits.stale_pdst \n connect slots_1.io.in_uop.bits.ppred_busy, issue_slots[1].in_uop.bits.ppred_busy \n connect slots_1.io.in_uop.bits.prs3_busy, issue_slots[1].in_uop.bits.prs3_busy \n connect slots_1.io.in_uop.bits.prs2_busy, issue_slots[1].in_uop.bits.prs2_busy \n connect slots_1.io.in_uop.bits.prs1_busy, issue_slots[1].in_uop.bits.prs1_busy \n connect slots_1.io.in_uop.bits.ppred, issue_slots[1].in_uop.bits.ppred \n connect slots_1.io.in_uop.bits.prs3, issue_slots[1].in_uop.bits.prs3 \n connect slots_1.io.in_uop.bits.prs2, issue_slots[1].in_uop.bits.prs2 \n connect slots_1.io.in_uop.bits.prs1, issue_slots[1].in_uop.bits.prs1 \n connect slots_1.io.in_uop.bits.pdst, issue_slots[1].in_uop.bits.pdst \n connect slots_1.io.in_uop.bits.rxq_idx, issue_slots[1].in_uop.bits.rxq_idx \n connect slots_1.io.in_uop.bits.stq_idx, issue_slots[1].in_uop.bits.stq_idx \n connect slots_1.io.in_uop.bits.ldq_idx, issue_slots[1].in_uop.bits.ldq_idx \n connect slots_1.io.in_uop.bits.rob_idx, issue_slots[1].in_uop.bits.rob_idx \n connect slots_1.io.in_uop.bits.fp_ctrl.vec, issue_slots[1].in_uop.bits.fp_ctrl.vec \n connect slots_1.io.in_uop.bits.fp_ctrl.wflags, issue_slots[1].in_uop.bits.fp_ctrl.wflags \n connect slots_1.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[1].in_uop.bits.fp_ctrl.sqrt \n connect slots_1.io.in_uop.bits.fp_ctrl.div, issue_slots[1].in_uop.bits.fp_ctrl.div \n connect slots_1.io.in_uop.bits.fp_ctrl.fma, issue_slots[1].in_uop.bits.fp_ctrl.fma \n connect slots_1.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[1].in_uop.bits.fp_ctrl.fastpipe \n connect slots_1.io.in_uop.bits.fp_ctrl.toint, issue_slots[1].in_uop.bits.fp_ctrl.toint \n connect slots_1.io.in_uop.bits.fp_ctrl.fromint, issue_slots[1].in_uop.bits.fp_ctrl.fromint \n connect slots_1.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[1].in_uop.bits.fp_ctrl.typeTagOut \n connect slots_1.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[1].in_uop.bits.fp_ctrl.typeTagIn \n connect slots_1.io.in_uop.bits.fp_ctrl.swap23, issue_slots[1].in_uop.bits.fp_ctrl.swap23 \n connect slots_1.io.in_uop.bits.fp_ctrl.swap12, issue_slots[1].in_uop.bits.fp_ctrl.swap12 \n connect slots_1.io.in_uop.bits.fp_ctrl.ren3, issue_slots[1].in_uop.bits.fp_ctrl.ren3 \n connect slots_1.io.in_uop.bits.fp_ctrl.ren2, issue_slots[1].in_uop.bits.fp_ctrl.ren2 \n connect slots_1.io.in_uop.bits.fp_ctrl.ren1, issue_slots[1].in_uop.bits.fp_ctrl.ren1 \n connect slots_1.io.in_uop.bits.fp_ctrl.wen, issue_slots[1].in_uop.bits.fp_ctrl.wen \n connect slots_1.io.in_uop.bits.fp_ctrl.ldst, issue_slots[1].in_uop.bits.fp_ctrl.ldst \n connect slots_1.io.in_uop.bits.op2_sel, issue_slots[1].in_uop.bits.op2_sel \n connect slots_1.io.in_uop.bits.op1_sel, issue_slots[1].in_uop.bits.op1_sel \n connect slots_1.io.in_uop.bits.imm_packed, issue_slots[1].in_uop.bits.imm_packed \n connect slots_1.io.in_uop.bits.pimm, issue_slots[1].in_uop.bits.pimm \n connect slots_1.io.in_uop.bits.imm_sel, issue_slots[1].in_uop.bits.imm_sel \n connect slots_1.io.in_uop.bits.imm_rename, issue_slots[1].in_uop.bits.imm_rename \n connect slots_1.io.in_uop.bits.taken, issue_slots[1].in_uop.bits.taken \n connect slots_1.io.in_uop.bits.pc_lob, issue_slots[1].in_uop.bits.pc_lob \n connect slots_1.io.in_uop.bits.edge_inst, issue_slots[1].in_uop.bits.edge_inst \n connect slots_1.io.in_uop.bits.ftq_idx, issue_slots[1].in_uop.bits.ftq_idx \n connect slots_1.io.in_uop.bits.is_mov, issue_slots[1].in_uop.bits.is_mov \n connect slots_1.io.in_uop.bits.is_rocc, issue_slots[1].in_uop.bits.is_rocc \n connect slots_1.io.in_uop.bits.is_sys_pc2epc, issue_slots[1].in_uop.bits.is_sys_pc2epc \n connect slots_1.io.in_uop.bits.is_eret, issue_slots[1].in_uop.bits.is_eret \n connect slots_1.io.in_uop.bits.is_amo, issue_slots[1].in_uop.bits.is_amo \n connect slots_1.io.in_uop.bits.is_sfence, issue_slots[1].in_uop.bits.is_sfence \n connect slots_1.io.in_uop.bits.is_fencei, issue_slots[1].in_uop.bits.is_fencei \n connect slots_1.io.in_uop.bits.is_fence, issue_slots[1].in_uop.bits.is_fence \n connect slots_1.io.in_uop.bits.is_sfb, issue_slots[1].in_uop.bits.is_sfb \n connect slots_1.io.in_uop.bits.br_type, issue_slots[1].in_uop.bits.br_type \n connect slots_1.io.in_uop.bits.br_tag, issue_slots[1].in_uop.bits.br_tag \n connect slots_1.io.in_uop.bits.br_mask, issue_slots[1].in_uop.bits.br_mask \n connect slots_1.io.in_uop.bits.dis_col_sel, issue_slots[1].in_uop.bits.dis_col_sel \n connect slots_1.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[1].in_uop.bits.iw_p3_bypass_hint \n connect slots_1.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[1].in_uop.bits.iw_p2_bypass_hint \n connect slots_1.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[1].in_uop.bits.iw_p1_bypass_hint \n connect slots_1.io.in_uop.bits.iw_p2_speculative_child, issue_slots[1].in_uop.bits.iw_p2_speculative_child \n connect slots_1.io.in_uop.bits.iw_p1_speculative_child, issue_slots[1].in_uop.bits.iw_p1_speculative_child \n connect slots_1.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[1].in_uop.bits.iw_issued_partial_dgen \n connect slots_1.io.in_uop.bits.iw_issued_partial_agen, issue_slots[1].in_uop.bits.iw_issued_partial_agen \n connect slots_1.io.in_uop.bits.iw_issued, issue_slots[1].in_uop.bits.iw_issued \n connect slots_1.io.in_uop.bits.fu_code[0], issue_slots[1].in_uop.bits.fu_code[0] \n connect slots_1.io.in_uop.bits.fu_code[1], issue_slots[1].in_uop.bits.fu_code[1] \n connect slots_1.io.in_uop.bits.fu_code[2], issue_slots[1].in_uop.bits.fu_code[2] \n connect slots_1.io.in_uop.bits.fu_code[3], issue_slots[1].in_uop.bits.fu_code[3] \n connect slots_1.io.in_uop.bits.fu_code[4], issue_slots[1].in_uop.bits.fu_code[4] \n connect slots_1.io.in_uop.bits.fu_code[5], issue_slots[1].in_uop.bits.fu_code[5] \n connect slots_1.io.in_uop.bits.fu_code[6], issue_slots[1].in_uop.bits.fu_code[6] \n connect slots_1.io.in_uop.bits.fu_code[7], issue_slots[1].in_uop.bits.fu_code[7] \n connect slots_1.io.in_uop.bits.fu_code[8], issue_slots[1].in_uop.bits.fu_code[8] \n connect slots_1.io.in_uop.bits.fu_code[9], issue_slots[1].in_uop.bits.fu_code[9] \n connect slots_1.io.in_uop.bits.iq_type[0], issue_slots[1].in_uop.bits.iq_type[0] \n connect slots_1.io.in_uop.bits.iq_type[1], issue_slots[1].in_uop.bits.iq_type[1] \n connect slots_1.io.in_uop.bits.iq_type[2], issue_slots[1].in_uop.bits.iq_type[2] \n connect slots_1.io.in_uop.bits.iq_type[3], issue_slots[1].in_uop.bits.iq_type[3] \n connect slots_1.io.in_uop.bits.debug_pc, issue_slots[1].in_uop.bits.debug_pc \n connect slots_1.io.in_uop.bits.is_rvc, issue_slots[1].in_uop.bits.is_rvc \n connect slots_1.io.in_uop.bits.debug_inst, issue_slots[1].in_uop.bits.debug_inst \n connect slots_1.io.in_uop.bits.inst, issue_slots[1].in_uop.bits.inst \n connect slots_1.io.in_uop.valid, issue_slots[1].in_uop.valid \n connect issue_slots[1].iss_uop.debug_tsrc, slots_1.io.iss_uop.debug_tsrc \n connect issue_slots[1].iss_uop.debug_fsrc, slots_1.io.iss_uop.debug_fsrc \n connect issue_slots[1].iss_uop.bp_xcpt_if, slots_1.io.iss_uop.bp_xcpt_if \n connect issue_slots[1].iss_uop.bp_debug_if, slots_1.io.iss_uop.bp_debug_if \n connect issue_slots[1].iss_uop.xcpt_ma_if, slots_1.io.iss_uop.xcpt_ma_if \n connect issue_slots[1].iss_uop.xcpt_ae_if, slots_1.io.iss_uop.xcpt_ae_if \n connect issue_slots[1].iss_uop.xcpt_pf_if, slots_1.io.iss_uop.xcpt_pf_if \n connect issue_slots[1].iss_uop.fp_typ, slots_1.io.iss_uop.fp_typ \n connect issue_slots[1].iss_uop.fp_rm, slots_1.io.iss_uop.fp_rm \n connect issue_slots[1].iss_uop.fp_val, slots_1.io.iss_uop.fp_val \n connect issue_slots[1].iss_uop.fcn_op, slots_1.io.iss_uop.fcn_op \n connect issue_slots[1].iss_uop.fcn_dw, slots_1.io.iss_uop.fcn_dw \n connect issue_slots[1].iss_uop.frs3_en, slots_1.io.iss_uop.frs3_en \n connect issue_slots[1].iss_uop.lrs2_rtype, slots_1.io.iss_uop.lrs2_rtype \n connect issue_slots[1].iss_uop.lrs1_rtype, slots_1.io.iss_uop.lrs1_rtype \n connect issue_slots[1].iss_uop.dst_rtype, slots_1.io.iss_uop.dst_rtype \n connect issue_slots[1].iss_uop.lrs3, slots_1.io.iss_uop.lrs3 \n connect issue_slots[1].iss_uop.lrs2, slots_1.io.iss_uop.lrs2 \n connect issue_slots[1].iss_uop.lrs1, slots_1.io.iss_uop.lrs1 \n connect issue_slots[1].iss_uop.ldst, slots_1.io.iss_uop.ldst \n connect issue_slots[1].iss_uop.ldst_is_rs1, slots_1.io.iss_uop.ldst_is_rs1 \n connect issue_slots[1].iss_uop.csr_cmd, slots_1.io.iss_uop.csr_cmd \n connect issue_slots[1].iss_uop.flush_on_commit, slots_1.io.iss_uop.flush_on_commit \n connect issue_slots[1].iss_uop.is_unique, slots_1.io.iss_uop.is_unique \n connect issue_slots[1].iss_uop.uses_stq, slots_1.io.iss_uop.uses_stq \n connect issue_slots[1].iss_uop.uses_ldq, slots_1.io.iss_uop.uses_ldq \n connect issue_slots[1].iss_uop.mem_signed, slots_1.io.iss_uop.mem_signed \n connect issue_slots[1].iss_uop.mem_size, slots_1.io.iss_uop.mem_size \n connect issue_slots[1].iss_uop.mem_cmd, slots_1.io.iss_uop.mem_cmd \n connect issue_slots[1].iss_uop.exc_cause, slots_1.io.iss_uop.exc_cause \n connect issue_slots[1].iss_uop.exception, slots_1.io.iss_uop.exception \n connect issue_slots[1].iss_uop.stale_pdst, slots_1.io.iss_uop.stale_pdst \n connect issue_slots[1].iss_uop.ppred_busy, slots_1.io.iss_uop.ppred_busy \n connect issue_slots[1].iss_uop.prs3_busy, slots_1.io.iss_uop.prs3_busy \n connect issue_slots[1].iss_uop.prs2_busy, slots_1.io.iss_uop.prs2_busy \n connect issue_slots[1].iss_uop.prs1_busy, slots_1.io.iss_uop.prs1_busy \n connect issue_slots[1].iss_uop.ppred, slots_1.io.iss_uop.ppred \n connect issue_slots[1].iss_uop.prs3, slots_1.io.iss_uop.prs3 \n connect issue_slots[1].iss_uop.prs2, slots_1.io.iss_uop.prs2 \n connect issue_slots[1].iss_uop.prs1, slots_1.io.iss_uop.prs1 \n connect issue_slots[1].iss_uop.pdst, slots_1.io.iss_uop.pdst \n connect issue_slots[1].iss_uop.rxq_idx, slots_1.io.iss_uop.rxq_idx \n connect issue_slots[1].iss_uop.stq_idx, slots_1.io.iss_uop.stq_idx \n connect issue_slots[1].iss_uop.ldq_idx, slots_1.io.iss_uop.ldq_idx \n connect issue_slots[1].iss_uop.rob_idx, slots_1.io.iss_uop.rob_idx \n connect issue_slots[1].iss_uop.fp_ctrl.vec, slots_1.io.iss_uop.fp_ctrl.vec \n connect issue_slots[1].iss_uop.fp_ctrl.wflags, slots_1.io.iss_uop.fp_ctrl.wflags \n connect issue_slots[1].iss_uop.fp_ctrl.sqrt, slots_1.io.iss_uop.fp_ctrl.sqrt \n connect issue_slots[1].iss_uop.fp_ctrl.div, slots_1.io.iss_uop.fp_ctrl.div \n connect issue_slots[1].iss_uop.fp_ctrl.fma, slots_1.io.iss_uop.fp_ctrl.fma \n connect issue_slots[1].iss_uop.fp_ctrl.fastpipe, slots_1.io.iss_uop.fp_ctrl.fastpipe \n connect issue_slots[1].iss_uop.fp_ctrl.toint, slots_1.io.iss_uop.fp_ctrl.toint \n connect issue_slots[1].iss_uop.fp_ctrl.fromint, slots_1.io.iss_uop.fp_ctrl.fromint \n connect issue_slots[1].iss_uop.fp_ctrl.typeTagOut, slots_1.io.iss_uop.fp_ctrl.typeTagOut \n connect issue_slots[1].iss_uop.fp_ctrl.typeTagIn, slots_1.io.iss_uop.fp_ctrl.typeTagIn \n connect issue_slots[1].iss_uop.fp_ctrl.swap23, slots_1.io.iss_uop.fp_ctrl.swap23 \n connect issue_slots[1].iss_uop.fp_ctrl.swap12, slots_1.io.iss_uop.fp_ctrl.swap12 \n connect issue_slots[1].iss_uop.fp_ctrl.ren3, slots_1.io.iss_uop.fp_ctrl.ren3 \n connect issue_slots[1].iss_uop.fp_ctrl.ren2, slots_1.io.iss_uop.fp_ctrl.ren2 \n connect issue_slots[1].iss_uop.fp_ctrl.ren1, slots_1.io.iss_uop.fp_ctrl.ren1 \n connect issue_slots[1].iss_uop.fp_ctrl.wen, slots_1.io.iss_uop.fp_ctrl.wen \n connect issue_slots[1].iss_uop.fp_ctrl.ldst, slots_1.io.iss_uop.fp_ctrl.ldst \n connect issue_slots[1].iss_uop.op2_sel, slots_1.io.iss_uop.op2_sel \n connect issue_slots[1].iss_uop.op1_sel, slots_1.io.iss_uop.op1_sel \n connect issue_slots[1].iss_uop.imm_packed, slots_1.io.iss_uop.imm_packed \n connect issue_slots[1].iss_uop.pimm, slots_1.io.iss_uop.pimm \n connect issue_slots[1].iss_uop.imm_sel, slots_1.io.iss_uop.imm_sel \n connect issue_slots[1].iss_uop.imm_rename, slots_1.io.iss_uop.imm_rename \n connect issue_slots[1].iss_uop.taken, slots_1.io.iss_uop.taken \n connect issue_slots[1].iss_uop.pc_lob, slots_1.io.iss_uop.pc_lob \n connect issue_slots[1].iss_uop.edge_inst, slots_1.io.iss_uop.edge_inst \n connect issue_slots[1].iss_uop.ftq_idx, slots_1.io.iss_uop.ftq_idx \n connect issue_slots[1].iss_uop.is_mov, slots_1.io.iss_uop.is_mov \n connect issue_slots[1].iss_uop.is_rocc, slots_1.io.iss_uop.is_rocc \n connect issue_slots[1].iss_uop.is_sys_pc2epc, slots_1.io.iss_uop.is_sys_pc2epc \n connect issue_slots[1].iss_uop.is_eret, slots_1.io.iss_uop.is_eret \n connect issue_slots[1].iss_uop.is_amo, slots_1.io.iss_uop.is_amo \n connect issue_slots[1].iss_uop.is_sfence, slots_1.io.iss_uop.is_sfence \n connect issue_slots[1].iss_uop.is_fencei, slots_1.io.iss_uop.is_fencei \n connect issue_slots[1].iss_uop.is_fence, slots_1.io.iss_uop.is_fence \n connect issue_slots[1].iss_uop.is_sfb, slots_1.io.iss_uop.is_sfb \n connect issue_slots[1].iss_uop.br_type, slots_1.io.iss_uop.br_type \n connect issue_slots[1].iss_uop.br_tag, slots_1.io.iss_uop.br_tag \n connect issue_slots[1].iss_uop.br_mask, slots_1.io.iss_uop.br_mask \n connect issue_slots[1].iss_uop.dis_col_sel, slots_1.io.iss_uop.dis_col_sel \n connect issue_slots[1].iss_uop.iw_p3_bypass_hint, slots_1.io.iss_uop.iw_p3_bypass_hint \n connect issue_slots[1].iss_uop.iw_p2_bypass_hint, slots_1.io.iss_uop.iw_p2_bypass_hint \n connect issue_slots[1].iss_uop.iw_p1_bypass_hint, slots_1.io.iss_uop.iw_p1_bypass_hint \n connect issue_slots[1].iss_uop.iw_p2_speculative_child, slots_1.io.iss_uop.iw_p2_speculative_child \n connect issue_slots[1].iss_uop.iw_p1_speculative_child, slots_1.io.iss_uop.iw_p1_speculative_child \n connect issue_slots[1].iss_uop.iw_issued_partial_dgen, slots_1.io.iss_uop.iw_issued_partial_dgen \n connect issue_slots[1].iss_uop.iw_issued_partial_agen, slots_1.io.iss_uop.iw_issued_partial_agen \n connect issue_slots[1].iss_uop.iw_issued, slots_1.io.iss_uop.iw_issued \n connect issue_slots[1].iss_uop.fu_code[0], slots_1.io.iss_uop.fu_code[0] \n connect issue_slots[1].iss_uop.fu_code[1], slots_1.io.iss_uop.fu_code[1] \n connect issue_slots[1].iss_uop.fu_code[2], slots_1.io.iss_uop.fu_code[2] \n connect issue_slots[1].iss_uop.fu_code[3], slots_1.io.iss_uop.fu_code[3] \n connect issue_slots[1].iss_uop.fu_code[4], slots_1.io.iss_uop.fu_code[4] \n connect issue_slots[1].iss_uop.fu_code[5], slots_1.io.iss_uop.fu_code[5] \n connect issue_slots[1].iss_uop.fu_code[6], slots_1.io.iss_uop.fu_code[6] \n connect issue_slots[1].iss_uop.fu_code[7], slots_1.io.iss_uop.fu_code[7] \n connect issue_slots[1].iss_uop.fu_code[8], slots_1.io.iss_uop.fu_code[8] \n connect issue_slots[1].iss_uop.fu_code[9], slots_1.io.iss_uop.fu_code[9] \n connect issue_slots[1].iss_uop.iq_type[0], slots_1.io.iss_uop.iq_type[0] \n connect issue_slots[1].iss_uop.iq_type[1], slots_1.io.iss_uop.iq_type[1] \n connect issue_slots[1].iss_uop.iq_type[2], slots_1.io.iss_uop.iq_type[2] \n connect issue_slots[1].iss_uop.iq_type[3], slots_1.io.iss_uop.iq_type[3] \n connect issue_slots[1].iss_uop.debug_pc, slots_1.io.iss_uop.debug_pc \n connect issue_slots[1].iss_uop.is_rvc, slots_1.io.iss_uop.is_rvc \n connect issue_slots[1].iss_uop.debug_inst, slots_1.io.iss_uop.debug_inst \n connect issue_slots[1].iss_uop.inst, slots_1.io.iss_uop.inst \n connect slots_1.io.grant, issue_slots[1].grant \n connect issue_slots[1].request, slots_1.io.request \n connect issue_slots[1].will_be_valid, slots_1.io.will_be_valid \n connect issue_slots[1].valid, slots_1.io.valid \n connect slots_2.io.child_rebusys, issue_slots[2].child_rebusys \n connect slots_2.io.pred_wakeup_port.bits, issue_slots[2].pred_wakeup_port.bits \n connect slots_2.io.pred_wakeup_port.valid, issue_slots[2].pred_wakeup_port.valid \n connect slots_2.io.wakeup_ports[0].bits.rebusy, issue_slots[2].wakeup_ports[0].bits.rebusy \n connect slots_2.io.wakeup_ports[0].bits.speculative_mask, issue_slots[2].wakeup_ports[0].bits.speculative_mask \n connect slots_2.io.wakeup_ports[0].bits.bypassable, issue_slots[2].wakeup_ports[0].bits.bypassable \n connect slots_2.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[2].wakeup_ports[0].bits.uop.debug_tsrc \n connect slots_2.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[2].wakeup_ports[0].bits.uop.debug_fsrc \n connect slots_2.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[2].wakeup_ports[0].bits.uop.bp_xcpt_if \n connect slots_2.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[2].wakeup_ports[0].bits.uop.bp_debug_if \n connect slots_2.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[2].wakeup_ports[0].bits.uop.xcpt_ma_if \n connect slots_2.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[2].wakeup_ports[0].bits.uop.xcpt_ae_if \n connect slots_2.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[2].wakeup_ports[0].bits.uop.xcpt_pf_if \n connect slots_2.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[2].wakeup_ports[0].bits.uop.fp_typ \n connect slots_2.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[2].wakeup_ports[0].bits.uop.fp_rm \n connect slots_2.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[2].wakeup_ports[0].bits.uop.fp_val \n connect slots_2.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[2].wakeup_ports[0].bits.uop.fcn_op \n connect slots_2.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[2].wakeup_ports[0].bits.uop.fcn_dw \n connect slots_2.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[2].wakeup_ports[0].bits.uop.frs3_en \n connect slots_2.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[2].wakeup_ports[0].bits.uop.lrs2_rtype \n connect slots_2.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[2].wakeup_ports[0].bits.uop.lrs1_rtype \n connect slots_2.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[2].wakeup_ports[0].bits.uop.dst_rtype \n connect slots_2.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[2].wakeup_ports[0].bits.uop.lrs3 \n connect slots_2.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[2].wakeup_ports[0].bits.uop.lrs2 \n connect slots_2.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[2].wakeup_ports[0].bits.uop.lrs1 \n connect slots_2.io.wakeup_ports[0].bits.uop.ldst, issue_slots[2].wakeup_ports[0].bits.uop.ldst \n connect slots_2.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[2].wakeup_ports[0].bits.uop.ldst_is_rs1 \n connect slots_2.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[2].wakeup_ports[0].bits.uop.csr_cmd \n connect slots_2.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[2].wakeup_ports[0].bits.uop.flush_on_commit \n connect slots_2.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[2].wakeup_ports[0].bits.uop.is_unique \n connect slots_2.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[2].wakeup_ports[0].bits.uop.uses_stq \n connect slots_2.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[2].wakeup_ports[0].bits.uop.uses_ldq \n connect slots_2.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[2].wakeup_ports[0].bits.uop.mem_signed \n connect slots_2.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[2].wakeup_ports[0].bits.uop.mem_size \n connect slots_2.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[2].wakeup_ports[0].bits.uop.mem_cmd \n connect slots_2.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[2].wakeup_ports[0].bits.uop.exc_cause \n connect slots_2.io.wakeup_ports[0].bits.uop.exception, issue_slots[2].wakeup_ports[0].bits.uop.exception \n connect slots_2.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[2].wakeup_ports[0].bits.uop.stale_pdst \n connect slots_2.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[2].wakeup_ports[0].bits.uop.ppred_busy \n connect slots_2.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[2].wakeup_ports[0].bits.uop.prs3_busy \n connect slots_2.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[2].wakeup_ports[0].bits.uop.prs2_busy \n connect slots_2.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[2].wakeup_ports[0].bits.uop.prs1_busy \n connect slots_2.io.wakeup_ports[0].bits.uop.ppred, issue_slots[2].wakeup_ports[0].bits.uop.ppred \n connect slots_2.io.wakeup_ports[0].bits.uop.prs3, issue_slots[2].wakeup_ports[0].bits.uop.prs3 \n connect slots_2.io.wakeup_ports[0].bits.uop.prs2, issue_slots[2].wakeup_ports[0].bits.uop.prs2 \n connect slots_2.io.wakeup_ports[0].bits.uop.prs1, issue_slots[2].wakeup_ports[0].bits.uop.prs1 \n connect slots_2.io.wakeup_ports[0].bits.uop.pdst, issue_slots[2].wakeup_ports[0].bits.uop.pdst \n connect slots_2.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[2].wakeup_ports[0].bits.uop.rxq_idx \n connect slots_2.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[2].wakeup_ports[0].bits.uop.stq_idx \n connect slots_2.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[2].wakeup_ports[0].bits.uop.ldq_idx \n connect slots_2.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[2].wakeup_ports[0].bits.uop.rob_idx \n connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.vec \n connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.wflags \n connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.sqrt \n connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.div \n connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.fma \n connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe \n connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.toint \n connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.fromint \n connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut \n connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn \n connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.swap23 \n connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.swap12 \n connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.ren3 \n connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.ren2 \n connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.ren1 \n connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.wen \n connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.ldst \n connect slots_2.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[2].wakeup_ports[0].bits.uop.op2_sel \n connect slots_2.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[2].wakeup_ports[0].bits.uop.op1_sel \n connect slots_2.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[2].wakeup_ports[0].bits.uop.imm_packed \n connect slots_2.io.wakeup_ports[0].bits.uop.pimm, issue_slots[2].wakeup_ports[0].bits.uop.pimm \n connect slots_2.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[2].wakeup_ports[0].bits.uop.imm_sel \n connect slots_2.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[2].wakeup_ports[0].bits.uop.imm_rename \n connect slots_2.io.wakeup_ports[0].bits.uop.taken, issue_slots[2].wakeup_ports[0].bits.uop.taken \n connect slots_2.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[2].wakeup_ports[0].bits.uop.pc_lob \n connect slots_2.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[2].wakeup_ports[0].bits.uop.edge_inst \n connect slots_2.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[2].wakeup_ports[0].bits.uop.ftq_idx \n connect slots_2.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[2].wakeup_ports[0].bits.uop.is_mov \n connect slots_2.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[2].wakeup_ports[0].bits.uop.is_rocc \n connect slots_2.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[2].wakeup_ports[0].bits.uop.is_sys_pc2epc \n connect slots_2.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[2].wakeup_ports[0].bits.uop.is_eret \n connect slots_2.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[2].wakeup_ports[0].bits.uop.is_amo \n connect slots_2.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[2].wakeup_ports[0].bits.uop.is_sfence \n connect slots_2.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[2].wakeup_ports[0].bits.uop.is_fencei \n connect slots_2.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[2].wakeup_ports[0].bits.uop.is_fence \n connect slots_2.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[2].wakeup_ports[0].bits.uop.is_sfb \n connect slots_2.io.wakeup_ports[0].bits.uop.br_type, issue_slots[2].wakeup_ports[0].bits.uop.br_type \n connect slots_2.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[2].wakeup_ports[0].bits.uop.br_tag \n connect slots_2.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[2].wakeup_ports[0].bits.uop.br_mask \n connect slots_2.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[2].wakeup_ports[0].bits.uop.dis_col_sel \n connect slots_2.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[2].wakeup_ports[0].bits.uop.iw_p3_bypass_hint \n connect slots_2.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[2].wakeup_ports[0].bits.uop.iw_p2_bypass_hint \n connect slots_2.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[2].wakeup_ports[0].bits.uop.iw_p1_bypass_hint \n connect slots_2.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[2].wakeup_ports[0].bits.uop.iw_p2_speculative_child \n connect slots_2.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[2].wakeup_ports[0].bits.uop.iw_p1_speculative_child \n connect slots_2.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[2].wakeup_ports[0].bits.uop.iw_issued_partial_dgen \n connect slots_2.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[2].wakeup_ports[0].bits.uop.iw_issued_partial_agen \n connect slots_2.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[2].wakeup_ports[0].bits.uop.iw_issued \n connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[0] \n connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[1] \n connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[2] \n connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[3] \n connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[4] \n connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[5] \n connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[6] \n connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[7] \n connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[8] \n connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[9] \n connect slots_2.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[2].wakeup_ports[0].bits.uop.iq_type[0] \n connect slots_2.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[2].wakeup_ports[0].bits.uop.iq_type[1] \n connect slots_2.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[2].wakeup_ports[0].bits.uop.iq_type[2] \n connect slots_2.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[2].wakeup_ports[0].bits.uop.iq_type[3] \n connect slots_2.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[2].wakeup_ports[0].bits.uop.debug_pc \n connect slots_2.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[2].wakeup_ports[0].bits.uop.is_rvc \n connect slots_2.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[2].wakeup_ports[0].bits.uop.debug_inst \n connect slots_2.io.wakeup_ports[0].bits.uop.inst, issue_slots[2].wakeup_ports[0].bits.uop.inst \n connect slots_2.io.wakeup_ports[0].valid, issue_slots[2].wakeup_ports[0].valid \n connect slots_2.io.wakeup_ports[1].bits.rebusy, issue_slots[2].wakeup_ports[1].bits.rebusy \n connect slots_2.io.wakeup_ports[1].bits.speculative_mask, issue_slots[2].wakeup_ports[1].bits.speculative_mask \n connect slots_2.io.wakeup_ports[1].bits.bypassable, issue_slots[2].wakeup_ports[1].bits.bypassable \n connect slots_2.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[2].wakeup_ports[1].bits.uop.debug_tsrc \n connect slots_2.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[2].wakeup_ports[1].bits.uop.debug_fsrc \n connect slots_2.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[2].wakeup_ports[1].bits.uop.bp_xcpt_if \n connect slots_2.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[2].wakeup_ports[1].bits.uop.bp_debug_if \n connect slots_2.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[2].wakeup_ports[1].bits.uop.xcpt_ma_if \n connect slots_2.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[2].wakeup_ports[1].bits.uop.xcpt_ae_if \n connect slots_2.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[2].wakeup_ports[1].bits.uop.xcpt_pf_if \n connect slots_2.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[2].wakeup_ports[1].bits.uop.fp_typ \n connect slots_2.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[2].wakeup_ports[1].bits.uop.fp_rm \n connect slots_2.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[2].wakeup_ports[1].bits.uop.fp_val \n connect slots_2.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[2].wakeup_ports[1].bits.uop.fcn_op \n connect slots_2.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[2].wakeup_ports[1].bits.uop.fcn_dw \n connect slots_2.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[2].wakeup_ports[1].bits.uop.frs3_en \n connect slots_2.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[2].wakeup_ports[1].bits.uop.lrs2_rtype \n connect slots_2.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[2].wakeup_ports[1].bits.uop.lrs1_rtype \n connect slots_2.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[2].wakeup_ports[1].bits.uop.dst_rtype \n connect slots_2.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[2].wakeup_ports[1].bits.uop.lrs3 \n connect slots_2.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[2].wakeup_ports[1].bits.uop.lrs2 \n connect slots_2.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[2].wakeup_ports[1].bits.uop.lrs1 \n connect slots_2.io.wakeup_ports[1].bits.uop.ldst, issue_slots[2].wakeup_ports[1].bits.uop.ldst \n connect slots_2.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[2].wakeup_ports[1].bits.uop.ldst_is_rs1 \n connect slots_2.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[2].wakeup_ports[1].bits.uop.csr_cmd \n connect slots_2.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[2].wakeup_ports[1].bits.uop.flush_on_commit \n connect slots_2.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[2].wakeup_ports[1].bits.uop.is_unique \n connect slots_2.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[2].wakeup_ports[1].bits.uop.uses_stq \n connect slots_2.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[2].wakeup_ports[1].bits.uop.uses_ldq \n connect slots_2.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[2].wakeup_ports[1].bits.uop.mem_signed \n connect slots_2.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[2].wakeup_ports[1].bits.uop.mem_size \n connect slots_2.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[2].wakeup_ports[1].bits.uop.mem_cmd \n connect slots_2.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[2].wakeup_ports[1].bits.uop.exc_cause \n connect slots_2.io.wakeup_ports[1].bits.uop.exception, issue_slots[2].wakeup_ports[1].bits.uop.exception \n connect slots_2.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[2].wakeup_ports[1].bits.uop.stale_pdst \n connect slots_2.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[2].wakeup_ports[1].bits.uop.ppred_busy \n connect slots_2.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[2].wakeup_ports[1].bits.uop.prs3_busy \n connect slots_2.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[2].wakeup_ports[1].bits.uop.prs2_busy \n connect slots_2.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[2].wakeup_ports[1].bits.uop.prs1_busy \n connect slots_2.io.wakeup_ports[1].bits.uop.ppred, issue_slots[2].wakeup_ports[1].bits.uop.ppred \n connect slots_2.io.wakeup_ports[1].bits.uop.prs3, issue_slots[2].wakeup_ports[1].bits.uop.prs3 \n connect slots_2.io.wakeup_ports[1].bits.uop.prs2, issue_slots[2].wakeup_ports[1].bits.uop.prs2 \n connect slots_2.io.wakeup_ports[1].bits.uop.prs1, issue_slots[2].wakeup_ports[1].bits.uop.prs1 \n connect slots_2.io.wakeup_ports[1].bits.uop.pdst, issue_slots[2].wakeup_ports[1].bits.uop.pdst \n connect slots_2.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[2].wakeup_ports[1].bits.uop.rxq_idx \n connect slots_2.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[2].wakeup_ports[1].bits.uop.stq_idx \n connect slots_2.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[2].wakeup_ports[1].bits.uop.ldq_idx \n connect slots_2.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[2].wakeup_ports[1].bits.uop.rob_idx \n connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.vec \n connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.wflags \n connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.sqrt \n connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.div \n connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.fma \n connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe \n connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.toint \n connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.fromint \n connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut \n connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn \n connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.swap23 \n connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.swap12 \n connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.ren3 \n connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.ren2 \n connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.ren1 \n connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.wen \n connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.ldst \n connect slots_2.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[2].wakeup_ports[1].bits.uop.op2_sel \n connect slots_2.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[2].wakeup_ports[1].bits.uop.op1_sel \n connect slots_2.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[2].wakeup_ports[1].bits.uop.imm_packed \n connect slots_2.io.wakeup_ports[1].bits.uop.pimm, issue_slots[2].wakeup_ports[1].bits.uop.pimm \n connect slots_2.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[2].wakeup_ports[1].bits.uop.imm_sel \n connect slots_2.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[2].wakeup_ports[1].bits.uop.imm_rename \n connect slots_2.io.wakeup_ports[1].bits.uop.taken, issue_slots[2].wakeup_ports[1].bits.uop.taken \n connect slots_2.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[2].wakeup_ports[1].bits.uop.pc_lob \n connect slots_2.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[2].wakeup_ports[1].bits.uop.edge_inst \n connect slots_2.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[2].wakeup_ports[1].bits.uop.ftq_idx \n connect slots_2.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[2].wakeup_ports[1].bits.uop.is_mov \n connect slots_2.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[2].wakeup_ports[1].bits.uop.is_rocc \n connect slots_2.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[2].wakeup_ports[1].bits.uop.is_sys_pc2epc \n connect slots_2.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[2].wakeup_ports[1].bits.uop.is_eret \n connect slots_2.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[2].wakeup_ports[1].bits.uop.is_amo \n connect slots_2.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[2].wakeup_ports[1].bits.uop.is_sfence \n connect slots_2.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[2].wakeup_ports[1].bits.uop.is_fencei \n connect slots_2.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[2].wakeup_ports[1].bits.uop.is_fence \n connect slots_2.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[2].wakeup_ports[1].bits.uop.is_sfb \n connect slots_2.io.wakeup_ports[1].bits.uop.br_type, issue_slots[2].wakeup_ports[1].bits.uop.br_type \n connect slots_2.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[2].wakeup_ports[1].bits.uop.br_tag \n connect slots_2.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[2].wakeup_ports[1].bits.uop.br_mask \n connect slots_2.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[2].wakeup_ports[1].bits.uop.dis_col_sel \n connect slots_2.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[2].wakeup_ports[1].bits.uop.iw_p3_bypass_hint \n connect slots_2.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[2].wakeup_ports[1].bits.uop.iw_p2_bypass_hint \n connect slots_2.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[2].wakeup_ports[1].bits.uop.iw_p1_bypass_hint \n connect slots_2.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[2].wakeup_ports[1].bits.uop.iw_p2_speculative_child \n connect slots_2.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[2].wakeup_ports[1].bits.uop.iw_p1_speculative_child \n connect slots_2.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[2].wakeup_ports[1].bits.uop.iw_issued_partial_dgen \n connect slots_2.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[2].wakeup_ports[1].bits.uop.iw_issued_partial_agen \n connect slots_2.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[2].wakeup_ports[1].bits.uop.iw_issued \n connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[0] \n connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[1] \n connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[2] \n connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[3] \n connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[4] \n connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[5] \n connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[6] \n connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[7] \n connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[8] \n connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[9] \n connect slots_2.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[2].wakeup_ports[1].bits.uop.iq_type[0] \n connect slots_2.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[2].wakeup_ports[1].bits.uop.iq_type[1] \n connect slots_2.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[2].wakeup_ports[1].bits.uop.iq_type[2] \n connect slots_2.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[2].wakeup_ports[1].bits.uop.iq_type[3] \n connect slots_2.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[2].wakeup_ports[1].bits.uop.debug_pc \n connect slots_2.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[2].wakeup_ports[1].bits.uop.is_rvc \n connect slots_2.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[2].wakeup_ports[1].bits.uop.debug_inst \n connect slots_2.io.wakeup_ports[1].bits.uop.inst, issue_slots[2].wakeup_ports[1].bits.uop.inst \n connect slots_2.io.wakeup_ports[1].valid, issue_slots[2].wakeup_ports[1].valid \n connect slots_2.io.wakeup_ports[2].bits.rebusy, issue_slots[2].wakeup_ports[2].bits.rebusy \n connect slots_2.io.wakeup_ports[2].bits.speculative_mask, issue_slots[2].wakeup_ports[2].bits.speculative_mask \n connect slots_2.io.wakeup_ports[2].bits.bypassable, issue_slots[2].wakeup_ports[2].bits.bypassable \n connect slots_2.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[2].wakeup_ports[2].bits.uop.debug_tsrc \n connect slots_2.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[2].wakeup_ports[2].bits.uop.debug_fsrc \n connect slots_2.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[2].wakeup_ports[2].bits.uop.bp_xcpt_if \n connect slots_2.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[2].wakeup_ports[2].bits.uop.bp_debug_if \n connect slots_2.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[2].wakeup_ports[2].bits.uop.xcpt_ma_if \n connect slots_2.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[2].wakeup_ports[2].bits.uop.xcpt_ae_if \n connect slots_2.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[2].wakeup_ports[2].bits.uop.xcpt_pf_if \n connect slots_2.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[2].wakeup_ports[2].bits.uop.fp_typ \n connect slots_2.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[2].wakeup_ports[2].bits.uop.fp_rm \n connect slots_2.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[2].wakeup_ports[2].bits.uop.fp_val \n connect slots_2.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[2].wakeup_ports[2].bits.uop.fcn_op \n connect slots_2.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[2].wakeup_ports[2].bits.uop.fcn_dw \n connect slots_2.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[2].wakeup_ports[2].bits.uop.frs3_en \n connect slots_2.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[2].wakeup_ports[2].bits.uop.lrs2_rtype \n connect slots_2.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[2].wakeup_ports[2].bits.uop.lrs1_rtype \n connect slots_2.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[2].wakeup_ports[2].bits.uop.dst_rtype \n connect slots_2.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[2].wakeup_ports[2].bits.uop.lrs3 \n connect slots_2.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[2].wakeup_ports[2].bits.uop.lrs2 \n connect slots_2.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[2].wakeup_ports[2].bits.uop.lrs1 \n connect slots_2.io.wakeup_ports[2].bits.uop.ldst, issue_slots[2].wakeup_ports[2].bits.uop.ldst \n connect slots_2.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[2].wakeup_ports[2].bits.uop.ldst_is_rs1 \n connect slots_2.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[2].wakeup_ports[2].bits.uop.csr_cmd \n connect slots_2.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[2].wakeup_ports[2].bits.uop.flush_on_commit \n connect slots_2.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[2].wakeup_ports[2].bits.uop.is_unique \n connect slots_2.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[2].wakeup_ports[2].bits.uop.uses_stq \n connect slots_2.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[2].wakeup_ports[2].bits.uop.uses_ldq \n connect slots_2.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[2].wakeup_ports[2].bits.uop.mem_signed \n connect slots_2.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[2].wakeup_ports[2].bits.uop.mem_size \n connect slots_2.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[2].wakeup_ports[2].bits.uop.mem_cmd \n connect slots_2.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[2].wakeup_ports[2].bits.uop.exc_cause \n connect slots_2.io.wakeup_ports[2].bits.uop.exception, issue_slots[2].wakeup_ports[2].bits.uop.exception \n connect slots_2.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[2].wakeup_ports[2].bits.uop.stale_pdst \n connect slots_2.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[2].wakeup_ports[2].bits.uop.ppred_busy \n connect slots_2.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[2].wakeup_ports[2].bits.uop.prs3_busy \n connect slots_2.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[2].wakeup_ports[2].bits.uop.prs2_busy \n connect slots_2.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[2].wakeup_ports[2].bits.uop.prs1_busy \n connect slots_2.io.wakeup_ports[2].bits.uop.ppred, issue_slots[2].wakeup_ports[2].bits.uop.ppred \n connect slots_2.io.wakeup_ports[2].bits.uop.prs3, issue_slots[2].wakeup_ports[2].bits.uop.prs3 \n connect slots_2.io.wakeup_ports[2].bits.uop.prs2, issue_slots[2].wakeup_ports[2].bits.uop.prs2 \n connect slots_2.io.wakeup_ports[2].bits.uop.prs1, issue_slots[2].wakeup_ports[2].bits.uop.prs1 \n connect slots_2.io.wakeup_ports[2].bits.uop.pdst, issue_slots[2].wakeup_ports[2].bits.uop.pdst \n connect slots_2.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[2].wakeup_ports[2].bits.uop.rxq_idx \n connect slots_2.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[2].wakeup_ports[2].bits.uop.stq_idx \n connect slots_2.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[2].wakeup_ports[2].bits.uop.ldq_idx \n connect slots_2.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[2].wakeup_ports[2].bits.uop.rob_idx \n connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.vec \n connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.wflags \n connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.sqrt \n connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.div \n connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.fma \n connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe \n connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.toint \n connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.fromint \n connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut \n connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn \n connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.swap23 \n connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.swap12 \n connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.ren3 \n connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.ren2 \n connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.ren1 \n connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.wen \n connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.ldst \n connect slots_2.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[2].wakeup_ports[2].bits.uop.op2_sel \n connect slots_2.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[2].wakeup_ports[2].bits.uop.op1_sel \n connect slots_2.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[2].wakeup_ports[2].bits.uop.imm_packed \n connect slots_2.io.wakeup_ports[2].bits.uop.pimm, issue_slots[2].wakeup_ports[2].bits.uop.pimm \n connect slots_2.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[2].wakeup_ports[2].bits.uop.imm_sel \n connect slots_2.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[2].wakeup_ports[2].bits.uop.imm_rename \n connect slots_2.io.wakeup_ports[2].bits.uop.taken, issue_slots[2].wakeup_ports[2].bits.uop.taken \n connect slots_2.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[2].wakeup_ports[2].bits.uop.pc_lob \n connect slots_2.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[2].wakeup_ports[2].bits.uop.edge_inst \n connect slots_2.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[2].wakeup_ports[2].bits.uop.ftq_idx \n connect slots_2.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[2].wakeup_ports[2].bits.uop.is_mov \n connect slots_2.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[2].wakeup_ports[2].bits.uop.is_rocc \n connect slots_2.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[2].wakeup_ports[2].bits.uop.is_sys_pc2epc \n connect slots_2.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[2].wakeup_ports[2].bits.uop.is_eret \n connect slots_2.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[2].wakeup_ports[2].bits.uop.is_amo \n connect slots_2.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[2].wakeup_ports[2].bits.uop.is_sfence \n connect slots_2.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[2].wakeup_ports[2].bits.uop.is_fencei \n connect slots_2.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[2].wakeup_ports[2].bits.uop.is_fence \n connect slots_2.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[2].wakeup_ports[2].bits.uop.is_sfb \n connect slots_2.io.wakeup_ports[2].bits.uop.br_type, issue_slots[2].wakeup_ports[2].bits.uop.br_type \n connect slots_2.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[2].wakeup_ports[2].bits.uop.br_tag \n connect slots_2.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[2].wakeup_ports[2].bits.uop.br_mask \n connect slots_2.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[2].wakeup_ports[2].bits.uop.dis_col_sel \n connect slots_2.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[2].wakeup_ports[2].bits.uop.iw_p3_bypass_hint \n connect slots_2.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[2].wakeup_ports[2].bits.uop.iw_p2_bypass_hint \n connect slots_2.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[2].wakeup_ports[2].bits.uop.iw_p1_bypass_hint \n connect slots_2.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[2].wakeup_ports[2].bits.uop.iw_p2_speculative_child \n connect slots_2.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[2].wakeup_ports[2].bits.uop.iw_p1_speculative_child \n connect slots_2.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[2].wakeup_ports[2].bits.uop.iw_issued_partial_dgen \n connect slots_2.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[2].wakeup_ports[2].bits.uop.iw_issued_partial_agen \n connect slots_2.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[2].wakeup_ports[2].bits.uop.iw_issued \n connect slots_2.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[2].wakeup_ports[2].bits.uop.fu_code[0] \n connect slots_2.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[2].wakeup_ports[2].bits.uop.fu_code[1] \n connect slots_2.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[2].wakeup_ports[2].bits.uop.fu_code[2] \n connect slots_2.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[2].wakeup_ports[2].bits.uop.fu_code[3] \n connect slots_2.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[2].wakeup_ports[2].bits.uop.fu_code[4] \n connect slots_2.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[2].wakeup_ports[2].bits.uop.fu_code[5] \n connect slots_2.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[2].wakeup_ports[2].bits.uop.fu_code[6] \n connect slots_2.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[2].wakeup_ports[2].bits.uop.fu_code[7] \n connect slots_2.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[2].wakeup_ports[2].bits.uop.fu_code[8] \n connect slots_2.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[2].wakeup_ports[2].bits.uop.fu_code[9] \n connect slots_2.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[2].wakeup_ports[2].bits.uop.iq_type[0] \n connect slots_2.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[2].wakeup_ports[2].bits.uop.iq_type[1] \n connect slots_2.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[2].wakeup_ports[2].bits.uop.iq_type[2] \n connect slots_2.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[2].wakeup_ports[2].bits.uop.iq_type[3] \n connect slots_2.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[2].wakeup_ports[2].bits.uop.debug_pc \n connect slots_2.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[2].wakeup_ports[2].bits.uop.is_rvc \n connect slots_2.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[2].wakeup_ports[2].bits.uop.debug_inst \n connect slots_2.io.wakeup_ports[2].bits.uop.inst, issue_slots[2].wakeup_ports[2].bits.uop.inst \n connect slots_2.io.wakeup_ports[2].valid, issue_slots[2].wakeup_ports[2].valid \n connect slots_2.io.wakeup_ports[3].bits.rebusy, issue_slots[2].wakeup_ports[3].bits.rebusy \n connect slots_2.io.wakeup_ports[3].bits.speculative_mask, issue_slots[2].wakeup_ports[3].bits.speculative_mask \n connect slots_2.io.wakeup_ports[3].bits.bypassable, issue_slots[2].wakeup_ports[3].bits.bypassable \n connect slots_2.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[2].wakeup_ports[3].bits.uop.debug_tsrc \n connect slots_2.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[2].wakeup_ports[3].bits.uop.debug_fsrc \n connect slots_2.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[2].wakeup_ports[3].bits.uop.bp_xcpt_if \n connect slots_2.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[2].wakeup_ports[3].bits.uop.bp_debug_if \n connect slots_2.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[2].wakeup_ports[3].bits.uop.xcpt_ma_if \n connect slots_2.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[2].wakeup_ports[3].bits.uop.xcpt_ae_if \n connect slots_2.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[2].wakeup_ports[3].bits.uop.xcpt_pf_if \n connect slots_2.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[2].wakeup_ports[3].bits.uop.fp_typ \n connect slots_2.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[2].wakeup_ports[3].bits.uop.fp_rm \n connect slots_2.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[2].wakeup_ports[3].bits.uop.fp_val \n connect slots_2.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[2].wakeup_ports[3].bits.uop.fcn_op \n connect slots_2.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[2].wakeup_ports[3].bits.uop.fcn_dw \n connect slots_2.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[2].wakeup_ports[3].bits.uop.frs3_en \n connect slots_2.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[2].wakeup_ports[3].bits.uop.lrs2_rtype \n connect slots_2.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[2].wakeup_ports[3].bits.uop.lrs1_rtype \n connect slots_2.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[2].wakeup_ports[3].bits.uop.dst_rtype \n connect slots_2.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[2].wakeup_ports[3].bits.uop.lrs3 \n connect slots_2.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[2].wakeup_ports[3].bits.uop.lrs2 \n connect slots_2.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[2].wakeup_ports[3].bits.uop.lrs1 \n connect slots_2.io.wakeup_ports[3].bits.uop.ldst, issue_slots[2].wakeup_ports[3].bits.uop.ldst \n connect slots_2.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[2].wakeup_ports[3].bits.uop.ldst_is_rs1 \n connect slots_2.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[2].wakeup_ports[3].bits.uop.csr_cmd \n connect slots_2.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[2].wakeup_ports[3].bits.uop.flush_on_commit \n connect slots_2.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[2].wakeup_ports[3].bits.uop.is_unique \n connect slots_2.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[2].wakeup_ports[3].bits.uop.uses_stq \n connect slots_2.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[2].wakeup_ports[3].bits.uop.uses_ldq \n connect slots_2.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[2].wakeup_ports[3].bits.uop.mem_signed \n connect slots_2.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[2].wakeup_ports[3].bits.uop.mem_size \n connect slots_2.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[2].wakeup_ports[3].bits.uop.mem_cmd \n connect slots_2.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[2].wakeup_ports[3].bits.uop.exc_cause \n connect slots_2.io.wakeup_ports[3].bits.uop.exception, issue_slots[2].wakeup_ports[3].bits.uop.exception \n connect slots_2.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[2].wakeup_ports[3].bits.uop.stale_pdst \n connect slots_2.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[2].wakeup_ports[3].bits.uop.ppred_busy \n connect slots_2.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[2].wakeup_ports[3].bits.uop.prs3_busy \n connect slots_2.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[2].wakeup_ports[3].bits.uop.prs2_busy \n connect slots_2.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[2].wakeup_ports[3].bits.uop.prs1_busy \n connect slots_2.io.wakeup_ports[3].bits.uop.ppred, issue_slots[2].wakeup_ports[3].bits.uop.ppred \n connect slots_2.io.wakeup_ports[3].bits.uop.prs3, issue_slots[2].wakeup_ports[3].bits.uop.prs3 \n connect slots_2.io.wakeup_ports[3].bits.uop.prs2, issue_slots[2].wakeup_ports[3].bits.uop.prs2 \n connect slots_2.io.wakeup_ports[3].bits.uop.prs1, issue_slots[2].wakeup_ports[3].bits.uop.prs1 \n connect slots_2.io.wakeup_ports[3].bits.uop.pdst, issue_slots[2].wakeup_ports[3].bits.uop.pdst \n connect slots_2.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[2].wakeup_ports[3].bits.uop.rxq_idx \n connect slots_2.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[2].wakeup_ports[3].bits.uop.stq_idx \n connect slots_2.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[2].wakeup_ports[3].bits.uop.ldq_idx \n connect slots_2.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[2].wakeup_ports[3].bits.uop.rob_idx \n connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.vec \n connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.wflags \n connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.sqrt \n connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.div \n connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.fma \n connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe \n connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.toint \n connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.fromint \n connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut \n connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn \n connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.swap23 \n connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.swap12 \n connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.ren3 \n connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.ren2 \n connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.ren1 \n connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.wen \n connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.ldst \n connect slots_2.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[2].wakeup_ports[3].bits.uop.op2_sel \n connect slots_2.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[2].wakeup_ports[3].bits.uop.op1_sel \n connect slots_2.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[2].wakeup_ports[3].bits.uop.imm_packed \n connect slots_2.io.wakeup_ports[3].bits.uop.pimm, issue_slots[2].wakeup_ports[3].bits.uop.pimm \n connect slots_2.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[2].wakeup_ports[3].bits.uop.imm_sel \n connect slots_2.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[2].wakeup_ports[3].bits.uop.imm_rename \n connect slots_2.io.wakeup_ports[3].bits.uop.taken, issue_slots[2].wakeup_ports[3].bits.uop.taken \n connect slots_2.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[2].wakeup_ports[3].bits.uop.pc_lob \n connect slots_2.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[2].wakeup_ports[3].bits.uop.edge_inst \n connect slots_2.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[2].wakeup_ports[3].bits.uop.ftq_idx \n connect slots_2.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[2].wakeup_ports[3].bits.uop.is_mov \n connect slots_2.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[2].wakeup_ports[3].bits.uop.is_rocc \n connect slots_2.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[2].wakeup_ports[3].bits.uop.is_sys_pc2epc \n connect slots_2.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[2].wakeup_ports[3].bits.uop.is_eret \n connect slots_2.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[2].wakeup_ports[3].bits.uop.is_amo \n connect slots_2.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[2].wakeup_ports[3].bits.uop.is_sfence \n connect slots_2.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[2].wakeup_ports[3].bits.uop.is_fencei \n connect slots_2.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[2].wakeup_ports[3].bits.uop.is_fence \n connect slots_2.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[2].wakeup_ports[3].bits.uop.is_sfb \n connect slots_2.io.wakeup_ports[3].bits.uop.br_type, issue_slots[2].wakeup_ports[3].bits.uop.br_type \n connect slots_2.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[2].wakeup_ports[3].bits.uop.br_tag \n connect slots_2.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[2].wakeup_ports[3].bits.uop.br_mask \n connect slots_2.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[2].wakeup_ports[3].bits.uop.dis_col_sel \n connect slots_2.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[2].wakeup_ports[3].bits.uop.iw_p3_bypass_hint \n connect slots_2.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[2].wakeup_ports[3].bits.uop.iw_p2_bypass_hint \n connect slots_2.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[2].wakeup_ports[3].bits.uop.iw_p1_bypass_hint \n connect slots_2.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[2].wakeup_ports[3].bits.uop.iw_p2_speculative_child \n connect slots_2.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[2].wakeup_ports[3].bits.uop.iw_p1_speculative_child \n connect slots_2.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[2].wakeup_ports[3].bits.uop.iw_issued_partial_dgen \n connect slots_2.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[2].wakeup_ports[3].bits.uop.iw_issued_partial_agen \n connect slots_2.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[2].wakeup_ports[3].bits.uop.iw_issued \n connect slots_2.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[2].wakeup_ports[3].bits.uop.fu_code[0] \n connect slots_2.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[2].wakeup_ports[3].bits.uop.fu_code[1] \n connect slots_2.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[2].wakeup_ports[3].bits.uop.fu_code[2] \n connect slots_2.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[2].wakeup_ports[3].bits.uop.fu_code[3] \n connect slots_2.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[2].wakeup_ports[3].bits.uop.fu_code[4] \n connect slots_2.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[2].wakeup_ports[3].bits.uop.fu_code[5] \n connect slots_2.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[2].wakeup_ports[3].bits.uop.fu_code[6] \n connect slots_2.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[2].wakeup_ports[3].bits.uop.fu_code[7] \n connect slots_2.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[2].wakeup_ports[3].bits.uop.fu_code[8] \n connect slots_2.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[2].wakeup_ports[3].bits.uop.fu_code[9] \n connect slots_2.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[2].wakeup_ports[3].bits.uop.iq_type[0] \n connect slots_2.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[2].wakeup_ports[3].bits.uop.iq_type[1] \n connect slots_2.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[2].wakeup_ports[3].bits.uop.iq_type[2] \n connect slots_2.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[2].wakeup_ports[3].bits.uop.iq_type[3] \n connect slots_2.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[2].wakeup_ports[3].bits.uop.debug_pc \n connect slots_2.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[2].wakeup_ports[3].bits.uop.is_rvc \n connect slots_2.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[2].wakeup_ports[3].bits.uop.debug_inst \n connect slots_2.io.wakeup_ports[3].bits.uop.inst, issue_slots[2].wakeup_ports[3].bits.uop.inst \n connect slots_2.io.wakeup_ports[3].valid, issue_slots[2].wakeup_ports[3].valid \n connect slots_2.io.squash_grant, issue_slots[2].squash_grant \n connect slots_2.io.clear, issue_slots[2].clear \n connect slots_2.io.kill, issue_slots[2].kill \n connect slots_2.io.brupdate.b2.target_offset, issue_slots[2].brupdate.b2.target_offset \n connect slots_2.io.brupdate.b2.jalr_target, issue_slots[2].brupdate.b2.jalr_target \n connect slots_2.io.brupdate.b2.pc_sel, issue_slots[2].brupdate.b2.pc_sel \n connect slots_2.io.brupdate.b2.cfi_type, issue_slots[2].brupdate.b2.cfi_type \n connect slots_2.io.brupdate.b2.taken, issue_slots[2].brupdate.b2.taken \n connect slots_2.io.brupdate.b2.mispredict, issue_slots[2].brupdate.b2.mispredict \n connect slots_2.io.brupdate.b2.uop.debug_tsrc, issue_slots[2].brupdate.b2.uop.debug_tsrc \n connect slots_2.io.brupdate.b2.uop.debug_fsrc, issue_slots[2].brupdate.b2.uop.debug_fsrc \n connect slots_2.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[2].brupdate.b2.uop.bp_xcpt_if \n connect slots_2.io.brupdate.b2.uop.bp_debug_if, issue_slots[2].brupdate.b2.uop.bp_debug_if \n connect slots_2.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[2].brupdate.b2.uop.xcpt_ma_if \n connect slots_2.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[2].brupdate.b2.uop.xcpt_ae_if \n connect slots_2.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[2].brupdate.b2.uop.xcpt_pf_if \n connect slots_2.io.brupdate.b2.uop.fp_typ, issue_slots[2].brupdate.b2.uop.fp_typ \n connect slots_2.io.brupdate.b2.uop.fp_rm, issue_slots[2].brupdate.b2.uop.fp_rm \n connect slots_2.io.brupdate.b2.uop.fp_val, issue_slots[2].brupdate.b2.uop.fp_val \n connect slots_2.io.brupdate.b2.uop.fcn_op, issue_slots[2].brupdate.b2.uop.fcn_op \n connect slots_2.io.brupdate.b2.uop.fcn_dw, issue_slots[2].brupdate.b2.uop.fcn_dw \n connect slots_2.io.brupdate.b2.uop.frs3_en, issue_slots[2].brupdate.b2.uop.frs3_en \n connect slots_2.io.brupdate.b2.uop.lrs2_rtype, issue_slots[2].brupdate.b2.uop.lrs2_rtype \n connect slots_2.io.brupdate.b2.uop.lrs1_rtype, issue_slots[2].brupdate.b2.uop.lrs1_rtype \n connect slots_2.io.brupdate.b2.uop.dst_rtype, issue_slots[2].brupdate.b2.uop.dst_rtype \n connect slots_2.io.brupdate.b2.uop.lrs3, issue_slots[2].brupdate.b2.uop.lrs3 \n connect slots_2.io.brupdate.b2.uop.lrs2, issue_slots[2].brupdate.b2.uop.lrs2 \n connect slots_2.io.brupdate.b2.uop.lrs1, issue_slots[2].brupdate.b2.uop.lrs1 \n connect slots_2.io.brupdate.b2.uop.ldst, issue_slots[2].brupdate.b2.uop.ldst \n connect slots_2.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[2].brupdate.b2.uop.ldst_is_rs1 \n connect slots_2.io.brupdate.b2.uop.csr_cmd, issue_slots[2].brupdate.b2.uop.csr_cmd \n connect slots_2.io.brupdate.b2.uop.flush_on_commit, issue_slots[2].brupdate.b2.uop.flush_on_commit \n connect slots_2.io.brupdate.b2.uop.is_unique, issue_slots[2].brupdate.b2.uop.is_unique \n connect slots_2.io.brupdate.b2.uop.uses_stq, issue_slots[2].brupdate.b2.uop.uses_stq \n connect slots_2.io.brupdate.b2.uop.uses_ldq, issue_slots[2].brupdate.b2.uop.uses_ldq \n connect slots_2.io.brupdate.b2.uop.mem_signed, issue_slots[2].brupdate.b2.uop.mem_signed \n connect slots_2.io.brupdate.b2.uop.mem_size, issue_slots[2].brupdate.b2.uop.mem_size \n connect slots_2.io.brupdate.b2.uop.mem_cmd, issue_slots[2].brupdate.b2.uop.mem_cmd \n connect slots_2.io.brupdate.b2.uop.exc_cause, issue_slots[2].brupdate.b2.uop.exc_cause \n connect slots_2.io.brupdate.b2.uop.exception, issue_slots[2].brupdate.b2.uop.exception \n connect slots_2.io.brupdate.b2.uop.stale_pdst, issue_slots[2].brupdate.b2.uop.stale_pdst \n connect slots_2.io.brupdate.b2.uop.ppred_busy, issue_slots[2].brupdate.b2.uop.ppred_busy \n connect slots_2.io.brupdate.b2.uop.prs3_busy, issue_slots[2].brupdate.b2.uop.prs3_busy \n connect slots_2.io.brupdate.b2.uop.prs2_busy, issue_slots[2].brupdate.b2.uop.prs2_busy \n connect slots_2.io.brupdate.b2.uop.prs1_busy, issue_slots[2].brupdate.b2.uop.prs1_busy \n connect slots_2.io.brupdate.b2.uop.ppred, issue_slots[2].brupdate.b2.uop.ppred \n connect slots_2.io.brupdate.b2.uop.prs3, issue_slots[2].brupdate.b2.uop.prs3 \n connect slots_2.io.brupdate.b2.uop.prs2, issue_slots[2].brupdate.b2.uop.prs2 \n connect slots_2.io.brupdate.b2.uop.prs1, issue_slots[2].brupdate.b2.uop.prs1 \n connect slots_2.io.brupdate.b2.uop.pdst, issue_slots[2].brupdate.b2.uop.pdst \n connect slots_2.io.brupdate.b2.uop.rxq_idx, issue_slots[2].brupdate.b2.uop.rxq_idx \n connect slots_2.io.brupdate.b2.uop.stq_idx, issue_slots[2].brupdate.b2.uop.stq_idx \n connect slots_2.io.brupdate.b2.uop.ldq_idx, issue_slots[2].brupdate.b2.uop.ldq_idx \n connect slots_2.io.brupdate.b2.uop.rob_idx, issue_slots[2].brupdate.b2.uop.rob_idx \n connect slots_2.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[2].brupdate.b2.uop.fp_ctrl.vec \n connect slots_2.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[2].brupdate.b2.uop.fp_ctrl.wflags \n connect slots_2.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[2].brupdate.b2.uop.fp_ctrl.sqrt \n connect slots_2.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[2].brupdate.b2.uop.fp_ctrl.div \n connect slots_2.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[2].brupdate.b2.uop.fp_ctrl.fma \n connect slots_2.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[2].brupdate.b2.uop.fp_ctrl.fastpipe \n connect slots_2.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[2].brupdate.b2.uop.fp_ctrl.toint \n connect slots_2.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[2].brupdate.b2.uop.fp_ctrl.fromint \n connect slots_2.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[2].brupdate.b2.uop.fp_ctrl.typeTagOut \n connect slots_2.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[2].brupdate.b2.uop.fp_ctrl.typeTagIn \n connect slots_2.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[2].brupdate.b2.uop.fp_ctrl.swap23 \n connect slots_2.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[2].brupdate.b2.uop.fp_ctrl.swap12 \n connect slots_2.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[2].brupdate.b2.uop.fp_ctrl.ren3 \n connect slots_2.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[2].brupdate.b2.uop.fp_ctrl.ren2 \n connect slots_2.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[2].brupdate.b2.uop.fp_ctrl.ren1 \n connect slots_2.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[2].brupdate.b2.uop.fp_ctrl.wen \n connect slots_2.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[2].brupdate.b2.uop.fp_ctrl.ldst \n connect slots_2.io.brupdate.b2.uop.op2_sel, issue_slots[2].brupdate.b2.uop.op2_sel \n connect slots_2.io.brupdate.b2.uop.op1_sel, issue_slots[2].brupdate.b2.uop.op1_sel \n connect slots_2.io.brupdate.b2.uop.imm_packed, issue_slots[2].brupdate.b2.uop.imm_packed \n connect slots_2.io.brupdate.b2.uop.pimm, issue_slots[2].brupdate.b2.uop.pimm \n connect slots_2.io.brupdate.b2.uop.imm_sel, issue_slots[2].brupdate.b2.uop.imm_sel \n connect slots_2.io.brupdate.b2.uop.imm_rename, issue_slots[2].brupdate.b2.uop.imm_rename \n connect slots_2.io.brupdate.b2.uop.taken, issue_slots[2].brupdate.b2.uop.taken \n connect slots_2.io.brupdate.b2.uop.pc_lob, issue_slots[2].brupdate.b2.uop.pc_lob \n connect slots_2.io.brupdate.b2.uop.edge_inst, issue_slots[2].brupdate.b2.uop.edge_inst \n connect slots_2.io.brupdate.b2.uop.ftq_idx, issue_slots[2].brupdate.b2.uop.ftq_idx \n connect slots_2.io.brupdate.b2.uop.is_mov, issue_slots[2].brupdate.b2.uop.is_mov \n connect slots_2.io.brupdate.b2.uop.is_rocc, issue_slots[2].brupdate.b2.uop.is_rocc \n connect slots_2.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[2].brupdate.b2.uop.is_sys_pc2epc \n connect slots_2.io.brupdate.b2.uop.is_eret, issue_slots[2].brupdate.b2.uop.is_eret \n connect slots_2.io.brupdate.b2.uop.is_amo, issue_slots[2].brupdate.b2.uop.is_amo \n connect slots_2.io.brupdate.b2.uop.is_sfence, issue_slots[2].brupdate.b2.uop.is_sfence \n connect slots_2.io.brupdate.b2.uop.is_fencei, issue_slots[2].brupdate.b2.uop.is_fencei \n connect slots_2.io.brupdate.b2.uop.is_fence, issue_slots[2].brupdate.b2.uop.is_fence \n connect slots_2.io.brupdate.b2.uop.is_sfb, issue_slots[2].brupdate.b2.uop.is_sfb \n connect slots_2.io.brupdate.b2.uop.br_type, issue_slots[2].brupdate.b2.uop.br_type \n connect slots_2.io.brupdate.b2.uop.br_tag, issue_slots[2].brupdate.b2.uop.br_tag \n connect slots_2.io.brupdate.b2.uop.br_mask, issue_slots[2].brupdate.b2.uop.br_mask \n connect slots_2.io.brupdate.b2.uop.dis_col_sel, issue_slots[2].brupdate.b2.uop.dis_col_sel \n connect slots_2.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[2].brupdate.b2.uop.iw_p3_bypass_hint \n connect slots_2.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[2].brupdate.b2.uop.iw_p2_bypass_hint \n connect slots_2.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[2].brupdate.b2.uop.iw_p1_bypass_hint \n connect slots_2.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[2].brupdate.b2.uop.iw_p2_speculative_child \n connect slots_2.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[2].brupdate.b2.uop.iw_p1_speculative_child \n connect slots_2.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[2].brupdate.b2.uop.iw_issued_partial_dgen \n connect slots_2.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[2].brupdate.b2.uop.iw_issued_partial_agen \n connect slots_2.io.brupdate.b2.uop.iw_issued, issue_slots[2].brupdate.b2.uop.iw_issued \n connect slots_2.io.brupdate.b2.uop.fu_code[0], issue_slots[2].brupdate.b2.uop.fu_code[0] \n connect slots_2.io.brupdate.b2.uop.fu_code[1], issue_slots[2].brupdate.b2.uop.fu_code[1] \n connect slots_2.io.brupdate.b2.uop.fu_code[2], issue_slots[2].brupdate.b2.uop.fu_code[2] \n connect slots_2.io.brupdate.b2.uop.fu_code[3], issue_slots[2].brupdate.b2.uop.fu_code[3] \n connect slots_2.io.brupdate.b2.uop.fu_code[4], issue_slots[2].brupdate.b2.uop.fu_code[4] \n connect slots_2.io.brupdate.b2.uop.fu_code[5], issue_slots[2].brupdate.b2.uop.fu_code[5] \n connect slots_2.io.brupdate.b2.uop.fu_code[6], issue_slots[2].brupdate.b2.uop.fu_code[6] \n connect slots_2.io.brupdate.b2.uop.fu_code[7], issue_slots[2].brupdate.b2.uop.fu_code[7] \n connect slots_2.io.brupdate.b2.uop.fu_code[8], issue_slots[2].brupdate.b2.uop.fu_code[8] \n connect slots_2.io.brupdate.b2.uop.fu_code[9], issue_slots[2].brupdate.b2.uop.fu_code[9] \n connect slots_2.io.brupdate.b2.uop.iq_type[0], issue_slots[2].brupdate.b2.uop.iq_type[0] \n connect slots_2.io.brupdate.b2.uop.iq_type[1], issue_slots[2].brupdate.b2.uop.iq_type[1] \n connect slots_2.io.brupdate.b2.uop.iq_type[2], issue_slots[2].brupdate.b2.uop.iq_type[2] \n connect slots_2.io.brupdate.b2.uop.iq_type[3], issue_slots[2].brupdate.b2.uop.iq_type[3] \n connect slots_2.io.brupdate.b2.uop.debug_pc, issue_slots[2].brupdate.b2.uop.debug_pc \n connect slots_2.io.brupdate.b2.uop.is_rvc, issue_slots[2].brupdate.b2.uop.is_rvc \n connect slots_2.io.brupdate.b2.uop.debug_inst, issue_slots[2].brupdate.b2.uop.debug_inst \n connect slots_2.io.brupdate.b2.uop.inst, issue_slots[2].brupdate.b2.uop.inst \n connect slots_2.io.brupdate.b1.mispredict_mask, issue_slots[2].brupdate.b1.mispredict_mask \n connect slots_2.io.brupdate.b1.resolve_mask, issue_slots[2].brupdate.b1.resolve_mask \n connect issue_slots[2].out_uop.debug_tsrc, slots_2.io.out_uop.debug_tsrc \n connect issue_slots[2].out_uop.debug_fsrc, slots_2.io.out_uop.debug_fsrc \n connect issue_slots[2].out_uop.bp_xcpt_if, slots_2.io.out_uop.bp_xcpt_if \n connect issue_slots[2].out_uop.bp_debug_if, slots_2.io.out_uop.bp_debug_if \n connect issue_slots[2].out_uop.xcpt_ma_if, slots_2.io.out_uop.xcpt_ma_if \n connect issue_slots[2].out_uop.xcpt_ae_if, slots_2.io.out_uop.xcpt_ae_if \n connect issue_slots[2].out_uop.xcpt_pf_if, slots_2.io.out_uop.xcpt_pf_if \n connect issue_slots[2].out_uop.fp_typ, slots_2.io.out_uop.fp_typ \n connect issue_slots[2].out_uop.fp_rm, slots_2.io.out_uop.fp_rm \n connect issue_slots[2].out_uop.fp_val, slots_2.io.out_uop.fp_val \n connect issue_slots[2].out_uop.fcn_op, slots_2.io.out_uop.fcn_op \n connect issue_slots[2].out_uop.fcn_dw, slots_2.io.out_uop.fcn_dw \n connect issue_slots[2].out_uop.frs3_en, slots_2.io.out_uop.frs3_en \n connect issue_slots[2].out_uop.lrs2_rtype, slots_2.io.out_uop.lrs2_rtype \n connect issue_slots[2].out_uop.lrs1_rtype, slots_2.io.out_uop.lrs1_rtype \n connect issue_slots[2].out_uop.dst_rtype, slots_2.io.out_uop.dst_rtype \n connect issue_slots[2].out_uop.lrs3, slots_2.io.out_uop.lrs3 \n connect issue_slots[2].out_uop.lrs2, slots_2.io.out_uop.lrs2 \n connect issue_slots[2].out_uop.lrs1, slots_2.io.out_uop.lrs1 \n connect issue_slots[2].out_uop.ldst, slots_2.io.out_uop.ldst \n connect issue_slots[2].out_uop.ldst_is_rs1, slots_2.io.out_uop.ldst_is_rs1 \n connect issue_slots[2].out_uop.csr_cmd, slots_2.io.out_uop.csr_cmd \n connect issue_slots[2].out_uop.flush_on_commit, slots_2.io.out_uop.flush_on_commit \n connect issue_slots[2].out_uop.is_unique, slots_2.io.out_uop.is_unique \n connect issue_slots[2].out_uop.uses_stq, slots_2.io.out_uop.uses_stq \n connect issue_slots[2].out_uop.uses_ldq, slots_2.io.out_uop.uses_ldq \n connect issue_slots[2].out_uop.mem_signed, slots_2.io.out_uop.mem_signed \n connect issue_slots[2].out_uop.mem_size, slots_2.io.out_uop.mem_size \n connect issue_slots[2].out_uop.mem_cmd, slots_2.io.out_uop.mem_cmd \n connect issue_slots[2].out_uop.exc_cause, slots_2.io.out_uop.exc_cause \n connect issue_slots[2].out_uop.exception, slots_2.io.out_uop.exception \n connect issue_slots[2].out_uop.stale_pdst, slots_2.io.out_uop.stale_pdst \n connect issue_slots[2].out_uop.ppred_busy, slots_2.io.out_uop.ppred_busy \n connect issue_slots[2].out_uop.prs3_busy, slots_2.io.out_uop.prs3_busy \n connect issue_slots[2].out_uop.prs2_busy, slots_2.io.out_uop.prs2_busy \n connect issue_slots[2].out_uop.prs1_busy, slots_2.io.out_uop.prs1_busy \n connect issue_slots[2].out_uop.ppred, slots_2.io.out_uop.ppred \n connect issue_slots[2].out_uop.prs3, slots_2.io.out_uop.prs3 \n connect issue_slots[2].out_uop.prs2, slots_2.io.out_uop.prs2 \n connect issue_slots[2].out_uop.prs1, slots_2.io.out_uop.prs1 \n connect issue_slots[2].out_uop.pdst, slots_2.io.out_uop.pdst \n connect issue_slots[2].out_uop.rxq_idx, slots_2.io.out_uop.rxq_idx \n connect issue_slots[2].out_uop.stq_idx, slots_2.io.out_uop.stq_idx \n connect issue_slots[2].out_uop.ldq_idx, slots_2.io.out_uop.ldq_idx \n connect issue_slots[2].out_uop.rob_idx, slots_2.io.out_uop.rob_idx \n connect issue_slots[2].out_uop.fp_ctrl.vec, slots_2.io.out_uop.fp_ctrl.vec \n connect issue_slots[2].out_uop.fp_ctrl.wflags, slots_2.io.out_uop.fp_ctrl.wflags \n connect issue_slots[2].out_uop.fp_ctrl.sqrt, slots_2.io.out_uop.fp_ctrl.sqrt \n connect issue_slots[2].out_uop.fp_ctrl.div, slots_2.io.out_uop.fp_ctrl.div \n connect issue_slots[2].out_uop.fp_ctrl.fma, slots_2.io.out_uop.fp_ctrl.fma \n connect issue_slots[2].out_uop.fp_ctrl.fastpipe, slots_2.io.out_uop.fp_ctrl.fastpipe \n connect issue_slots[2].out_uop.fp_ctrl.toint, slots_2.io.out_uop.fp_ctrl.toint \n connect issue_slots[2].out_uop.fp_ctrl.fromint, slots_2.io.out_uop.fp_ctrl.fromint \n connect issue_slots[2].out_uop.fp_ctrl.typeTagOut, slots_2.io.out_uop.fp_ctrl.typeTagOut \n connect issue_slots[2].out_uop.fp_ctrl.typeTagIn, slots_2.io.out_uop.fp_ctrl.typeTagIn \n connect issue_slots[2].out_uop.fp_ctrl.swap23, slots_2.io.out_uop.fp_ctrl.swap23 \n connect issue_slots[2].out_uop.fp_ctrl.swap12, slots_2.io.out_uop.fp_ctrl.swap12 \n connect issue_slots[2].out_uop.fp_ctrl.ren3, slots_2.io.out_uop.fp_ctrl.ren3 \n connect issue_slots[2].out_uop.fp_ctrl.ren2, slots_2.io.out_uop.fp_ctrl.ren2 \n connect issue_slots[2].out_uop.fp_ctrl.ren1, slots_2.io.out_uop.fp_ctrl.ren1 \n connect issue_slots[2].out_uop.fp_ctrl.wen, slots_2.io.out_uop.fp_ctrl.wen \n connect issue_slots[2].out_uop.fp_ctrl.ldst, slots_2.io.out_uop.fp_ctrl.ldst \n connect issue_slots[2].out_uop.op2_sel, slots_2.io.out_uop.op2_sel \n connect issue_slots[2].out_uop.op1_sel, slots_2.io.out_uop.op1_sel \n connect issue_slots[2].out_uop.imm_packed, slots_2.io.out_uop.imm_packed \n connect issue_slots[2].out_uop.pimm, slots_2.io.out_uop.pimm \n connect issue_slots[2].out_uop.imm_sel, slots_2.io.out_uop.imm_sel \n connect issue_slots[2].out_uop.imm_rename, slots_2.io.out_uop.imm_rename \n connect issue_slots[2].out_uop.taken, slots_2.io.out_uop.taken \n connect issue_slots[2].out_uop.pc_lob, slots_2.io.out_uop.pc_lob \n connect issue_slots[2].out_uop.edge_inst, slots_2.io.out_uop.edge_inst \n connect issue_slots[2].out_uop.ftq_idx, slots_2.io.out_uop.ftq_idx \n connect issue_slots[2].out_uop.is_mov, slots_2.io.out_uop.is_mov \n connect issue_slots[2].out_uop.is_rocc, slots_2.io.out_uop.is_rocc \n connect issue_slots[2].out_uop.is_sys_pc2epc, slots_2.io.out_uop.is_sys_pc2epc \n connect issue_slots[2].out_uop.is_eret, slots_2.io.out_uop.is_eret \n connect issue_slots[2].out_uop.is_amo, slots_2.io.out_uop.is_amo \n connect issue_slots[2].out_uop.is_sfence, slots_2.io.out_uop.is_sfence \n connect issue_slots[2].out_uop.is_fencei, slots_2.io.out_uop.is_fencei \n connect issue_slots[2].out_uop.is_fence, slots_2.io.out_uop.is_fence \n connect issue_slots[2].out_uop.is_sfb, slots_2.io.out_uop.is_sfb \n connect issue_slots[2].out_uop.br_type, slots_2.io.out_uop.br_type \n connect issue_slots[2].out_uop.br_tag, slots_2.io.out_uop.br_tag \n connect issue_slots[2].out_uop.br_mask, slots_2.io.out_uop.br_mask \n connect issue_slots[2].out_uop.dis_col_sel, slots_2.io.out_uop.dis_col_sel \n connect issue_slots[2].out_uop.iw_p3_bypass_hint, slots_2.io.out_uop.iw_p3_bypass_hint \n connect issue_slots[2].out_uop.iw_p2_bypass_hint, slots_2.io.out_uop.iw_p2_bypass_hint \n connect issue_slots[2].out_uop.iw_p1_bypass_hint, slots_2.io.out_uop.iw_p1_bypass_hint \n connect issue_slots[2].out_uop.iw_p2_speculative_child, slots_2.io.out_uop.iw_p2_speculative_child \n connect issue_slots[2].out_uop.iw_p1_speculative_child, slots_2.io.out_uop.iw_p1_speculative_child \n connect issue_slots[2].out_uop.iw_issued_partial_dgen, slots_2.io.out_uop.iw_issued_partial_dgen \n connect issue_slots[2].out_uop.iw_issued_partial_agen, slots_2.io.out_uop.iw_issued_partial_agen \n connect issue_slots[2].out_uop.iw_issued, slots_2.io.out_uop.iw_issued \n connect issue_slots[2].out_uop.fu_code[0], slots_2.io.out_uop.fu_code[0] \n connect issue_slots[2].out_uop.fu_code[1], slots_2.io.out_uop.fu_code[1] \n connect issue_slots[2].out_uop.fu_code[2], slots_2.io.out_uop.fu_code[2] \n connect issue_slots[2].out_uop.fu_code[3], slots_2.io.out_uop.fu_code[3] \n connect issue_slots[2].out_uop.fu_code[4], slots_2.io.out_uop.fu_code[4] \n connect issue_slots[2].out_uop.fu_code[5], slots_2.io.out_uop.fu_code[5] \n connect issue_slots[2].out_uop.fu_code[6], slots_2.io.out_uop.fu_code[6] \n connect issue_slots[2].out_uop.fu_code[7], slots_2.io.out_uop.fu_code[7] \n connect issue_slots[2].out_uop.fu_code[8], slots_2.io.out_uop.fu_code[8] \n connect issue_slots[2].out_uop.fu_code[9], slots_2.io.out_uop.fu_code[9] \n connect issue_slots[2].out_uop.iq_type[0], slots_2.io.out_uop.iq_type[0] \n connect issue_slots[2].out_uop.iq_type[1], slots_2.io.out_uop.iq_type[1] \n connect issue_slots[2].out_uop.iq_type[2], slots_2.io.out_uop.iq_type[2] \n connect issue_slots[2].out_uop.iq_type[3], slots_2.io.out_uop.iq_type[3] \n connect issue_slots[2].out_uop.debug_pc, slots_2.io.out_uop.debug_pc \n connect issue_slots[2].out_uop.is_rvc, slots_2.io.out_uop.is_rvc \n connect issue_slots[2].out_uop.debug_inst, slots_2.io.out_uop.debug_inst \n connect issue_slots[2].out_uop.inst, slots_2.io.out_uop.inst \n connect slots_2.io.in_uop.bits.debug_tsrc, issue_slots[2].in_uop.bits.debug_tsrc \n connect slots_2.io.in_uop.bits.debug_fsrc, issue_slots[2].in_uop.bits.debug_fsrc \n connect slots_2.io.in_uop.bits.bp_xcpt_if, issue_slots[2].in_uop.bits.bp_xcpt_if \n connect slots_2.io.in_uop.bits.bp_debug_if, issue_slots[2].in_uop.bits.bp_debug_if \n connect slots_2.io.in_uop.bits.xcpt_ma_if, issue_slots[2].in_uop.bits.xcpt_ma_if \n connect slots_2.io.in_uop.bits.xcpt_ae_if, issue_slots[2].in_uop.bits.xcpt_ae_if \n connect slots_2.io.in_uop.bits.xcpt_pf_if, issue_slots[2].in_uop.bits.xcpt_pf_if \n connect slots_2.io.in_uop.bits.fp_typ, issue_slots[2].in_uop.bits.fp_typ \n connect slots_2.io.in_uop.bits.fp_rm, issue_slots[2].in_uop.bits.fp_rm \n connect slots_2.io.in_uop.bits.fp_val, issue_slots[2].in_uop.bits.fp_val \n connect slots_2.io.in_uop.bits.fcn_op, issue_slots[2].in_uop.bits.fcn_op \n connect slots_2.io.in_uop.bits.fcn_dw, issue_slots[2].in_uop.bits.fcn_dw \n connect slots_2.io.in_uop.bits.frs3_en, issue_slots[2].in_uop.bits.frs3_en \n connect slots_2.io.in_uop.bits.lrs2_rtype, issue_slots[2].in_uop.bits.lrs2_rtype \n connect slots_2.io.in_uop.bits.lrs1_rtype, issue_slots[2].in_uop.bits.lrs1_rtype \n connect slots_2.io.in_uop.bits.dst_rtype, issue_slots[2].in_uop.bits.dst_rtype \n connect slots_2.io.in_uop.bits.lrs3, issue_slots[2].in_uop.bits.lrs3 \n connect slots_2.io.in_uop.bits.lrs2, issue_slots[2].in_uop.bits.lrs2 \n connect slots_2.io.in_uop.bits.lrs1, issue_slots[2].in_uop.bits.lrs1 \n connect slots_2.io.in_uop.bits.ldst, issue_slots[2].in_uop.bits.ldst \n connect slots_2.io.in_uop.bits.ldst_is_rs1, issue_slots[2].in_uop.bits.ldst_is_rs1 \n connect slots_2.io.in_uop.bits.csr_cmd, issue_slots[2].in_uop.bits.csr_cmd \n connect slots_2.io.in_uop.bits.flush_on_commit, issue_slots[2].in_uop.bits.flush_on_commit \n connect slots_2.io.in_uop.bits.is_unique, issue_slots[2].in_uop.bits.is_unique \n connect slots_2.io.in_uop.bits.uses_stq, issue_slots[2].in_uop.bits.uses_stq \n connect slots_2.io.in_uop.bits.uses_ldq, issue_slots[2].in_uop.bits.uses_ldq \n connect slots_2.io.in_uop.bits.mem_signed, issue_slots[2].in_uop.bits.mem_signed \n connect slots_2.io.in_uop.bits.mem_size, issue_slots[2].in_uop.bits.mem_size \n connect slots_2.io.in_uop.bits.mem_cmd, issue_slots[2].in_uop.bits.mem_cmd \n connect slots_2.io.in_uop.bits.exc_cause, issue_slots[2].in_uop.bits.exc_cause \n connect slots_2.io.in_uop.bits.exception, issue_slots[2].in_uop.bits.exception \n connect slots_2.io.in_uop.bits.stale_pdst, issue_slots[2].in_uop.bits.stale_pdst \n connect slots_2.io.in_uop.bits.ppred_busy, issue_slots[2].in_uop.bits.ppred_busy \n connect slots_2.io.in_uop.bits.prs3_busy, issue_slots[2].in_uop.bits.prs3_busy \n connect slots_2.io.in_uop.bits.prs2_busy, issue_slots[2].in_uop.bits.prs2_busy \n connect slots_2.io.in_uop.bits.prs1_busy, issue_slots[2].in_uop.bits.prs1_busy \n connect slots_2.io.in_uop.bits.ppred, issue_slots[2].in_uop.bits.ppred \n connect slots_2.io.in_uop.bits.prs3, issue_slots[2].in_uop.bits.prs3 \n connect slots_2.io.in_uop.bits.prs2, issue_slots[2].in_uop.bits.prs2 \n connect slots_2.io.in_uop.bits.prs1, issue_slots[2].in_uop.bits.prs1 \n connect slots_2.io.in_uop.bits.pdst, issue_slots[2].in_uop.bits.pdst \n connect slots_2.io.in_uop.bits.rxq_idx, issue_slots[2].in_uop.bits.rxq_idx \n connect slots_2.io.in_uop.bits.stq_idx, issue_slots[2].in_uop.bits.stq_idx \n connect slots_2.io.in_uop.bits.ldq_idx, issue_slots[2].in_uop.bits.ldq_idx \n connect slots_2.io.in_uop.bits.rob_idx, issue_slots[2].in_uop.bits.rob_idx \n connect slots_2.io.in_uop.bits.fp_ctrl.vec, issue_slots[2].in_uop.bits.fp_ctrl.vec \n connect slots_2.io.in_uop.bits.fp_ctrl.wflags, issue_slots[2].in_uop.bits.fp_ctrl.wflags \n connect slots_2.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[2].in_uop.bits.fp_ctrl.sqrt \n connect slots_2.io.in_uop.bits.fp_ctrl.div, issue_slots[2].in_uop.bits.fp_ctrl.div \n connect slots_2.io.in_uop.bits.fp_ctrl.fma, issue_slots[2].in_uop.bits.fp_ctrl.fma \n connect slots_2.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[2].in_uop.bits.fp_ctrl.fastpipe \n connect slots_2.io.in_uop.bits.fp_ctrl.toint, issue_slots[2].in_uop.bits.fp_ctrl.toint \n connect slots_2.io.in_uop.bits.fp_ctrl.fromint, issue_slots[2].in_uop.bits.fp_ctrl.fromint \n connect slots_2.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[2].in_uop.bits.fp_ctrl.typeTagOut \n connect slots_2.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[2].in_uop.bits.fp_ctrl.typeTagIn \n connect slots_2.io.in_uop.bits.fp_ctrl.swap23, issue_slots[2].in_uop.bits.fp_ctrl.swap23 \n connect slots_2.io.in_uop.bits.fp_ctrl.swap12, issue_slots[2].in_uop.bits.fp_ctrl.swap12 \n connect slots_2.io.in_uop.bits.fp_ctrl.ren3, issue_slots[2].in_uop.bits.fp_ctrl.ren3 \n connect slots_2.io.in_uop.bits.fp_ctrl.ren2, issue_slots[2].in_uop.bits.fp_ctrl.ren2 \n connect slots_2.io.in_uop.bits.fp_ctrl.ren1, issue_slots[2].in_uop.bits.fp_ctrl.ren1 \n connect slots_2.io.in_uop.bits.fp_ctrl.wen, issue_slots[2].in_uop.bits.fp_ctrl.wen \n connect slots_2.io.in_uop.bits.fp_ctrl.ldst, issue_slots[2].in_uop.bits.fp_ctrl.ldst \n connect slots_2.io.in_uop.bits.op2_sel, issue_slots[2].in_uop.bits.op2_sel \n connect slots_2.io.in_uop.bits.op1_sel, issue_slots[2].in_uop.bits.op1_sel \n connect slots_2.io.in_uop.bits.imm_packed, issue_slots[2].in_uop.bits.imm_packed \n connect slots_2.io.in_uop.bits.pimm, issue_slots[2].in_uop.bits.pimm \n connect slots_2.io.in_uop.bits.imm_sel, issue_slots[2].in_uop.bits.imm_sel \n connect slots_2.io.in_uop.bits.imm_rename, issue_slots[2].in_uop.bits.imm_rename \n connect slots_2.io.in_uop.bits.taken, issue_slots[2].in_uop.bits.taken \n connect slots_2.io.in_uop.bits.pc_lob, issue_slots[2].in_uop.bits.pc_lob \n connect slots_2.io.in_uop.bits.edge_inst, issue_slots[2].in_uop.bits.edge_inst \n connect slots_2.io.in_uop.bits.ftq_idx, issue_slots[2].in_uop.bits.ftq_idx \n connect slots_2.io.in_uop.bits.is_mov, issue_slots[2].in_uop.bits.is_mov \n connect slots_2.io.in_uop.bits.is_rocc, issue_slots[2].in_uop.bits.is_rocc \n connect slots_2.io.in_uop.bits.is_sys_pc2epc, issue_slots[2].in_uop.bits.is_sys_pc2epc \n connect slots_2.io.in_uop.bits.is_eret, issue_slots[2].in_uop.bits.is_eret \n connect slots_2.io.in_uop.bits.is_amo, issue_slots[2].in_uop.bits.is_amo \n connect slots_2.io.in_uop.bits.is_sfence, issue_slots[2].in_uop.bits.is_sfence \n connect slots_2.io.in_uop.bits.is_fencei, issue_slots[2].in_uop.bits.is_fencei \n connect slots_2.io.in_uop.bits.is_fence, issue_slots[2].in_uop.bits.is_fence \n connect slots_2.io.in_uop.bits.is_sfb, issue_slots[2].in_uop.bits.is_sfb \n connect slots_2.io.in_uop.bits.br_type, issue_slots[2].in_uop.bits.br_type \n connect slots_2.io.in_uop.bits.br_tag, issue_slots[2].in_uop.bits.br_tag \n connect slots_2.io.in_uop.bits.br_mask, issue_slots[2].in_uop.bits.br_mask \n connect slots_2.io.in_uop.bits.dis_col_sel, issue_slots[2].in_uop.bits.dis_col_sel \n connect slots_2.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[2].in_uop.bits.iw_p3_bypass_hint \n connect slots_2.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[2].in_uop.bits.iw_p2_bypass_hint \n connect slots_2.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[2].in_uop.bits.iw_p1_bypass_hint \n connect slots_2.io.in_uop.bits.iw_p2_speculative_child, issue_slots[2].in_uop.bits.iw_p2_speculative_child \n connect slots_2.io.in_uop.bits.iw_p1_speculative_child, issue_slots[2].in_uop.bits.iw_p1_speculative_child \n connect slots_2.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[2].in_uop.bits.iw_issued_partial_dgen \n connect slots_2.io.in_uop.bits.iw_issued_partial_agen, issue_slots[2].in_uop.bits.iw_issued_partial_agen \n connect slots_2.io.in_uop.bits.iw_issued, issue_slots[2].in_uop.bits.iw_issued \n connect slots_2.io.in_uop.bits.fu_code[0], issue_slots[2].in_uop.bits.fu_code[0] \n connect slots_2.io.in_uop.bits.fu_code[1], issue_slots[2].in_uop.bits.fu_code[1] \n connect slots_2.io.in_uop.bits.fu_code[2], issue_slots[2].in_uop.bits.fu_code[2] \n connect slots_2.io.in_uop.bits.fu_code[3], issue_slots[2].in_uop.bits.fu_code[3] \n connect slots_2.io.in_uop.bits.fu_code[4], issue_slots[2].in_uop.bits.fu_code[4] \n connect slots_2.io.in_uop.bits.fu_code[5], issue_slots[2].in_uop.bits.fu_code[5] \n connect slots_2.io.in_uop.bits.fu_code[6], issue_slots[2].in_uop.bits.fu_code[6] \n connect slots_2.io.in_uop.bits.fu_code[7], issue_slots[2].in_uop.bits.fu_code[7] \n connect slots_2.io.in_uop.bits.fu_code[8], issue_slots[2].in_uop.bits.fu_code[8] \n connect slots_2.io.in_uop.bits.fu_code[9], issue_slots[2].in_uop.bits.fu_code[9] \n connect slots_2.io.in_uop.bits.iq_type[0], issue_slots[2].in_uop.bits.iq_type[0] \n connect slots_2.io.in_uop.bits.iq_type[1], issue_slots[2].in_uop.bits.iq_type[1] \n connect slots_2.io.in_uop.bits.iq_type[2], issue_slots[2].in_uop.bits.iq_type[2] \n connect slots_2.io.in_uop.bits.iq_type[3], issue_slots[2].in_uop.bits.iq_type[3] \n connect slots_2.io.in_uop.bits.debug_pc, issue_slots[2].in_uop.bits.debug_pc \n connect slots_2.io.in_uop.bits.is_rvc, issue_slots[2].in_uop.bits.is_rvc \n connect slots_2.io.in_uop.bits.debug_inst, issue_slots[2].in_uop.bits.debug_inst \n connect slots_2.io.in_uop.bits.inst, issue_slots[2].in_uop.bits.inst \n connect slots_2.io.in_uop.valid, issue_slots[2].in_uop.valid \n connect issue_slots[2].iss_uop.debug_tsrc, slots_2.io.iss_uop.debug_tsrc \n connect issue_slots[2].iss_uop.debug_fsrc, slots_2.io.iss_uop.debug_fsrc \n connect issue_slots[2].iss_uop.bp_xcpt_if, slots_2.io.iss_uop.bp_xcpt_if \n connect issue_slots[2].iss_uop.bp_debug_if, slots_2.io.iss_uop.bp_debug_if \n connect issue_slots[2].iss_uop.xcpt_ma_if, slots_2.io.iss_uop.xcpt_ma_if \n connect issue_slots[2].iss_uop.xcpt_ae_if, slots_2.io.iss_uop.xcpt_ae_if \n connect issue_slots[2].iss_uop.xcpt_pf_if, slots_2.io.iss_uop.xcpt_pf_if \n connect issue_slots[2].iss_uop.fp_typ, slots_2.io.iss_uop.fp_typ \n connect issue_slots[2].iss_uop.fp_rm, slots_2.io.iss_uop.fp_rm \n connect issue_slots[2].iss_uop.fp_val, slots_2.io.iss_uop.fp_val \n connect issue_slots[2].iss_uop.fcn_op, slots_2.io.iss_uop.fcn_op \n connect issue_slots[2].iss_uop.fcn_dw, slots_2.io.iss_uop.fcn_dw \n connect issue_slots[2].iss_uop.frs3_en, slots_2.io.iss_uop.frs3_en \n connect issue_slots[2].iss_uop.lrs2_rtype, slots_2.io.iss_uop.lrs2_rtype \n connect issue_slots[2].iss_uop.lrs1_rtype, slots_2.io.iss_uop.lrs1_rtype \n connect issue_slots[2].iss_uop.dst_rtype, slots_2.io.iss_uop.dst_rtype \n connect issue_slots[2].iss_uop.lrs3, slots_2.io.iss_uop.lrs3 \n connect issue_slots[2].iss_uop.lrs2, slots_2.io.iss_uop.lrs2 \n connect issue_slots[2].iss_uop.lrs1, slots_2.io.iss_uop.lrs1 \n connect issue_slots[2].iss_uop.ldst, slots_2.io.iss_uop.ldst \n connect issue_slots[2].iss_uop.ldst_is_rs1, slots_2.io.iss_uop.ldst_is_rs1 \n connect issue_slots[2].iss_uop.csr_cmd, slots_2.io.iss_uop.csr_cmd \n connect issue_slots[2].iss_uop.flush_on_commit, slots_2.io.iss_uop.flush_on_commit \n connect issue_slots[2].iss_uop.is_unique, slots_2.io.iss_uop.is_unique \n connect issue_slots[2].iss_uop.uses_stq, slots_2.io.iss_uop.uses_stq \n connect issue_slots[2].iss_uop.uses_ldq, slots_2.io.iss_uop.uses_ldq \n connect issue_slots[2].iss_uop.mem_signed, slots_2.io.iss_uop.mem_signed \n connect issue_slots[2].iss_uop.mem_size, slots_2.io.iss_uop.mem_size \n connect issue_slots[2].iss_uop.mem_cmd, slots_2.io.iss_uop.mem_cmd \n connect issue_slots[2].iss_uop.exc_cause, slots_2.io.iss_uop.exc_cause \n connect issue_slots[2].iss_uop.exception, slots_2.io.iss_uop.exception \n connect issue_slots[2].iss_uop.stale_pdst, slots_2.io.iss_uop.stale_pdst \n connect issue_slots[2].iss_uop.ppred_busy, slots_2.io.iss_uop.ppred_busy \n connect issue_slots[2].iss_uop.prs3_busy, slots_2.io.iss_uop.prs3_busy \n connect issue_slots[2].iss_uop.prs2_busy, slots_2.io.iss_uop.prs2_busy \n connect issue_slots[2].iss_uop.prs1_busy, slots_2.io.iss_uop.prs1_busy \n connect issue_slots[2].iss_uop.ppred, slots_2.io.iss_uop.ppred \n connect issue_slots[2].iss_uop.prs3, slots_2.io.iss_uop.prs3 \n connect issue_slots[2].iss_uop.prs2, slots_2.io.iss_uop.prs2 \n connect issue_slots[2].iss_uop.prs1, slots_2.io.iss_uop.prs1 \n connect issue_slots[2].iss_uop.pdst, slots_2.io.iss_uop.pdst \n connect issue_slots[2].iss_uop.rxq_idx, slots_2.io.iss_uop.rxq_idx \n connect issue_slots[2].iss_uop.stq_idx, slots_2.io.iss_uop.stq_idx \n connect issue_slots[2].iss_uop.ldq_idx, slots_2.io.iss_uop.ldq_idx \n connect issue_slots[2].iss_uop.rob_idx, slots_2.io.iss_uop.rob_idx \n connect issue_slots[2].iss_uop.fp_ctrl.vec, slots_2.io.iss_uop.fp_ctrl.vec \n connect issue_slots[2].iss_uop.fp_ctrl.wflags, slots_2.io.iss_uop.fp_ctrl.wflags \n connect issue_slots[2].iss_uop.fp_ctrl.sqrt, slots_2.io.iss_uop.fp_ctrl.sqrt \n connect issue_slots[2].iss_uop.fp_ctrl.div, slots_2.io.iss_uop.fp_ctrl.div \n connect issue_slots[2].iss_uop.fp_ctrl.fma, slots_2.io.iss_uop.fp_ctrl.fma \n connect issue_slots[2].iss_uop.fp_ctrl.fastpipe, slots_2.io.iss_uop.fp_ctrl.fastpipe \n connect issue_slots[2].iss_uop.fp_ctrl.toint, slots_2.io.iss_uop.fp_ctrl.toint \n connect issue_slots[2].iss_uop.fp_ctrl.fromint, slots_2.io.iss_uop.fp_ctrl.fromint \n connect issue_slots[2].iss_uop.fp_ctrl.typeTagOut, slots_2.io.iss_uop.fp_ctrl.typeTagOut \n connect issue_slots[2].iss_uop.fp_ctrl.typeTagIn, slots_2.io.iss_uop.fp_ctrl.typeTagIn \n connect issue_slots[2].iss_uop.fp_ctrl.swap23, slots_2.io.iss_uop.fp_ctrl.swap23 \n connect issue_slots[2].iss_uop.fp_ctrl.swap12, slots_2.io.iss_uop.fp_ctrl.swap12 \n connect issue_slots[2].iss_uop.fp_ctrl.ren3, slots_2.io.iss_uop.fp_ctrl.ren3 \n connect issue_slots[2].iss_uop.fp_ctrl.ren2, slots_2.io.iss_uop.fp_ctrl.ren2 \n connect issue_slots[2].iss_uop.fp_ctrl.ren1, slots_2.io.iss_uop.fp_ctrl.ren1 \n connect issue_slots[2].iss_uop.fp_ctrl.wen, slots_2.io.iss_uop.fp_ctrl.wen \n connect issue_slots[2].iss_uop.fp_ctrl.ldst, slots_2.io.iss_uop.fp_ctrl.ldst \n connect issue_slots[2].iss_uop.op2_sel, slots_2.io.iss_uop.op2_sel \n connect issue_slots[2].iss_uop.op1_sel, slots_2.io.iss_uop.op1_sel \n connect issue_slots[2].iss_uop.imm_packed, slots_2.io.iss_uop.imm_packed \n connect issue_slots[2].iss_uop.pimm, slots_2.io.iss_uop.pimm \n connect issue_slots[2].iss_uop.imm_sel, slots_2.io.iss_uop.imm_sel \n connect issue_slots[2].iss_uop.imm_rename, slots_2.io.iss_uop.imm_rename \n connect issue_slots[2].iss_uop.taken, slots_2.io.iss_uop.taken \n connect issue_slots[2].iss_uop.pc_lob, slots_2.io.iss_uop.pc_lob \n connect issue_slots[2].iss_uop.edge_inst, slots_2.io.iss_uop.edge_inst \n connect issue_slots[2].iss_uop.ftq_idx, slots_2.io.iss_uop.ftq_idx \n connect issue_slots[2].iss_uop.is_mov, slots_2.io.iss_uop.is_mov \n connect issue_slots[2].iss_uop.is_rocc, slots_2.io.iss_uop.is_rocc \n connect issue_slots[2].iss_uop.is_sys_pc2epc, slots_2.io.iss_uop.is_sys_pc2epc \n connect issue_slots[2].iss_uop.is_eret, slots_2.io.iss_uop.is_eret \n connect issue_slots[2].iss_uop.is_amo, slots_2.io.iss_uop.is_amo \n connect issue_slots[2].iss_uop.is_sfence, slots_2.io.iss_uop.is_sfence \n connect issue_slots[2].iss_uop.is_fencei, slots_2.io.iss_uop.is_fencei \n connect issue_slots[2].iss_uop.is_fence, slots_2.io.iss_uop.is_fence \n connect issue_slots[2].iss_uop.is_sfb, slots_2.io.iss_uop.is_sfb \n connect issue_slots[2].iss_uop.br_type, slots_2.io.iss_uop.br_type \n connect issue_slots[2].iss_uop.br_tag, slots_2.io.iss_uop.br_tag \n connect issue_slots[2].iss_uop.br_mask, slots_2.io.iss_uop.br_mask \n connect issue_slots[2].iss_uop.dis_col_sel, slots_2.io.iss_uop.dis_col_sel \n connect issue_slots[2].iss_uop.iw_p3_bypass_hint, slots_2.io.iss_uop.iw_p3_bypass_hint \n connect issue_slots[2].iss_uop.iw_p2_bypass_hint, slots_2.io.iss_uop.iw_p2_bypass_hint \n connect issue_slots[2].iss_uop.iw_p1_bypass_hint, slots_2.io.iss_uop.iw_p1_bypass_hint \n connect issue_slots[2].iss_uop.iw_p2_speculative_child, slots_2.io.iss_uop.iw_p2_speculative_child \n connect issue_slots[2].iss_uop.iw_p1_speculative_child, slots_2.io.iss_uop.iw_p1_speculative_child \n connect issue_slots[2].iss_uop.iw_issued_partial_dgen, slots_2.io.iss_uop.iw_issued_partial_dgen \n connect issue_slots[2].iss_uop.iw_issued_partial_agen, slots_2.io.iss_uop.iw_issued_partial_agen \n connect issue_slots[2].iss_uop.iw_issued, slots_2.io.iss_uop.iw_issued \n connect issue_slots[2].iss_uop.fu_code[0], slots_2.io.iss_uop.fu_code[0] \n connect issue_slots[2].iss_uop.fu_code[1], slots_2.io.iss_uop.fu_code[1] \n connect issue_slots[2].iss_uop.fu_code[2], slots_2.io.iss_uop.fu_code[2] \n connect issue_slots[2].iss_uop.fu_code[3], slots_2.io.iss_uop.fu_code[3] \n connect issue_slots[2].iss_uop.fu_code[4], slots_2.io.iss_uop.fu_code[4] \n connect issue_slots[2].iss_uop.fu_code[5], slots_2.io.iss_uop.fu_code[5] \n connect issue_slots[2].iss_uop.fu_code[6], slots_2.io.iss_uop.fu_code[6] \n connect issue_slots[2].iss_uop.fu_code[7], slots_2.io.iss_uop.fu_code[7] \n connect issue_slots[2].iss_uop.fu_code[8], slots_2.io.iss_uop.fu_code[8] \n connect issue_slots[2].iss_uop.fu_code[9], slots_2.io.iss_uop.fu_code[9] \n connect issue_slots[2].iss_uop.iq_type[0], slots_2.io.iss_uop.iq_type[0] \n connect issue_slots[2].iss_uop.iq_type[1], slots_2.io.iss_uop.iq_type[1] \n connect issue_slots[2].iss_uop.iq_type[2], slots_2.io.iss_uop.iq_type[2] \n connect issue_slots[2].iss_uop.iq_type[3], slots_2.io.iss_uop.iq_type[3] \n connect issue_slots[2].iss_uop.debug_pc, slots_2.io.iss_uop.debug_pc \n connect issue_slots[2].iss_uop.is_rvc, slots_2.io.iss_uop.is_rvc \n connect issue_slots[2].iss_uop.debug_inst, slots_2.io.iss_uop.debug_inst \n connect issue_slots[2].iss_uop.inst, slots_2.io.iss_uop.inst \n connect slots_2.io.grant, issue_slots[2].grant \n connect issue_slots[2].request, slots_2.io.request \n connect issue_slots[2].will_be_valid, slots_2.io.will_be_valid \n connect issue_slots[2].valid, slots_2.io.valid \n connect slots_3.io.child_rebusys, issue_slots[3].child_rebusys \n connect slots_3.io.pred_wakeup_port.bits, issue_slots[3].pred_wakeup_port.bits \n connect slots_3.io.pred_wakeup_port.valid, issue_slots[3].pred_wakeup_port.valid \n connect slots_3.io.wakeup_ports[0].bits.rebusy, issue_slots[3].wakeup_ports[0].bits.rebusy \n connect slots_3.io.wakeup_ports[0].bits.speculative_mask, issue_slots[3].wakeup_ports[0].bits.speculative_mask \n connect slots_3.io.wakeup_ports[0].bits.bypassable, issue_slots[3].wakeup_ports[0].bits.bypassable \n connect slots_3.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[3].wakeup_ports[0].bits.uop.debug_tsrc \n connect slots_3.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[3].wakeup_ports[0].bits.uop.debug_fsrc \n connect slots_3.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[3].wakeup_ports[0].bits.uop.bp_xcpt_if \n connect slots_3.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[3].wakeup_ports[0].bits.uop.bp_debug_if \n connect slots_3.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[3].wakeup_ports[0].bits.uop.xcpt_ma_if \n connect slots_3.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[3].wakeup_ports[0].bits.uop.xcpt_ae_if \n connect slots_3.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[3].wakeup_ports[0].bits.uop.xcpt_pf_if \n connect slots_3.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[3].wakeup_ports[0].bits.uop.fp_typ \n connect slots_3.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[3].wakeup_ports[0].bits.uop.fp_rm \n connect slots_3.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[3].wakeup_ports[0].bits.uop.fp_val \n connect slots_3.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[3].wakeup_ports[0].bits.uop.fcn_op \n connect slots_3.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[3].wakeup_ports[0].bits.uop.fcn_dw \n connect slots_3.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[3].wakeup_ports[0].bits.uop.frs3_en \n connect slots_3.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[3].wakeup_ports[0].bits.uop.lrs2_rtype \n connect slots_3.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[3].wakeup_ports[0].bits.uop.lrs1_rtype \n connect slots_3.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[3].wakeup_ports[0].bits.uop.dst_rtype \n connect slots_3.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[3].wakeup_ports[0].bits.uop.lrs3 \n connect slots_3.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[3].wakeup_ports[0].bits.uop.lrs2 \n connect slots_3.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[3].wakeup_ports[0].bits.uop.lrs1 \n connect slots_3.io.wakeup_ports[0].bits.uop.ldst, issue_slots[3].wakeup_ports[0].bits.uop.ldst \n connect slots_3.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[3].wakeup_ports[0].bits.uop.ldst_is_rs1 \n connect slots_3.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[3].wakeup_ports[0].bits.uop.csr_cmd \n connect slots_3.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[3].wakeup_ports[0].bits.uop.flush_on_commit \n connect slots_3.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[3].wakeup_ports[0].bits.uop.is_unique \n connect slots_3.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[3].wakeup_ports[0].bits.uop.uses_stq \n connect slots_3.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[3].wakeup_ports[0].bits.uop.uses_ldq \n connect slots_3.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[3].wakeup_ports[0].bits.uop.mem_signed \n connect slots_3.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[3].wakeup_ports[0].bits.uop.mem_size \n connect slots_3.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[3].wakeup_ports[0].bits.uop.mem_cmd \n connect slots_3.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[3].wakeup_ports[0].bits.uop.exc_cause \n connect slots_3.io.wakeup_ports[0].bits.uop.exception, issue_slots[3].wakeup_ports[0].bits.uop.exception \n connect slots_3.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[3].wakeup_ports[0].bits.uop.stale_pdst \n connect slots_3.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[3].wakeup_ports[0].bits.uop.ppred_busy \n connect slots_3.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[3].wakeup_ports[0].bits.uop.prs3_busy \n connect slots_3.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[3].wakeup_ports[0].bits.uop.prs2_busy \n connect slots_3.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[3].wakeup_ports[0].bits.uop.prs1_busy \n connect slots_3.io.wakeup_ports[0].bits.uop.ppred, issue_slots[3].wakeup_ports[0].bits.uop.ppred \n connect slots_3.io.wakeup_ports[0].bits.uop.prs3, issue_slots[3].wakeup_ports[0].bits.uop.prs3 \n connect slots_3.io.wakeup_ports[0].bits.uop.prs2, issue_slots[3].wakeup_ports[0].bits.uop.prs2 \n connect slots_3.io.wakeup_ports[0].bits.uop.prs1, issue_slots[3].wakeup_ports[0].bits.uop.prs1 \n connect slots_3.io.wakeup_ports[0].bits.uop.pdst, issue_slots[3].wakeup_ports[0].bits.uop.pdst \n connect slots_3.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[3].wakeup_ports[0].bits.uop.rxq_idx \n connect slots_3.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[3].wakeup_ports[0].bits.uop.stq_idx \n connect slots_3.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[3].wakeup_ports[0].bits.uop.ldq_idx \n connect slots_3.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[3].wakeup_ports[0].bits.uop.rob_idx \n connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.vec \n connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.wflags \n connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.sqrt \n connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.div \n connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.fma \n connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe \n connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.toint \n connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.fromint \n connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut \n connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn \n connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.swap23 \n connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.swap12 \n connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.ren3 \n connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.ren2 \n connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.ren1 \n connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.wen \n connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.ldst \n connect slots_3.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[3].wakeup_ports[0].bits.uop.op2_sel \n connect slots_3.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[3].wakeup_ports[0].bits.uop.op1_sel \n connect slots_3.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[3].wakeup_ports[0].bits.uop.imm_packed \n connect slots_3.io.wakeup_ports[0].bits.uop.pimm, issue_slots[3].wakeup_ports[0].bits.uop.pimm \n connect slots_3.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[3].wakeup_ports[0].bits.uop.imm_sel \n connect slots_3.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[3].wakeup_ports[0].bits.uop.imm_rename \n connect slots_3.io.wakeup_ports[0].bits.uop.taken, issue_slots[3].wakeup_ports[0].bits.uop.taken \n connect slots_3.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[3].wakeup_ports[0].bits.uop.pc_lob \n connect slots_3.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[3].wakeup_ports[0].bits.uop.edge_inst \n connect slots_3.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[3].wakeup_ports[0].bits.uop.ftq_idx \n connect slots_3.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[3].wakeup_ports[0].bits.uop.is_mov \n connect slots_3.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[3].wakeup_ports[0].bits.uop.is_rocc \n connect slots_3.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[3].wakeup_ports[0].bits.uop.is_sys_pc2epc \n connect slots_3.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[3].wakeup_ports[0].bits.uop.is_eret \n connect slots_3.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[3].wakeup_ports[0].bits.uop.is_amo \n connect slots_3.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[3].wakeup_ports[0].bits.uop.is_sfence \n connect slots_3.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[3].wakeup_ports[0].bits.uop.is_fencei \n connect slots_3.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[3].wakeup_ports[0].bits.uop.is_fence \n connect slots_3.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[3].wakeup_ports[0].bits.uop.is_sfb \n connect slots_3.io.wakeup_ports[0].bits.uop.br_type, issue_slots[3].wakeup_ports[0].bits.uop.br_type \n connect slots_3.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[3].wakeup_ports[0].bits.uop.br_tag \n connect slots_3.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[3].wakeup_ports[0].bits.uop.br_mask \n connect slots_3.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[3].wakeup_ports[0].bits.uop.dis_col_sel \n connect slots_3.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[3].wakeup_ports[0].bits.uop.iw_p3_bypass_hint \n connect slots_3.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[3].wakeup_ports[0].bits.uop.iw_p2_bypass_hint \n connect slots_3.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[3].wakeup_ports[0].bits.uop.iw_p1_bypass_hint \n connect slots_3.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[3].wakeup_ports[0].bits.uop.iw_p2_speculative_child \n connect slots_3.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[3].wakeup_ports[0].bits.uop.iw_p1_speculative_child \n connect slots_3.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[3].wakeup_ports[0].bits.uop.iw_issued_partial_dgen \n connect slots_3.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[3].wakeup_ports[0].bits.uop.iw_issued_partial_agen \n connect slots_3.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[3].wakeup_ports[0].bits.uop.iw_issued \n connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[0] \n connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[1] \n connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[2] \n connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[3] \n connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[4] \n connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[5] \n connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[6] \n connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[7] \n connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[8] \n connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[9] \n connect slots_3.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[3].wakeup_ports[0].bits.uop.iq_type[0] \n connect slots_3.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[3].wakeup_ports[0].bits.uop.iq_type[1] \n connect slots_3.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[3].wakeup_ports[0].bits.uop.iq_type[2] \n connect slots_3.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[3].wakeup_ports[0].bits.uop.iq_type[3] \n connect slots_3.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[3].wakeup_ports[0].bits.uop.debug_pc \n connect slots_3.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[3].wakeup_ports[0].bits.uop.is_rvc \n connect slots_3.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[3].wakeup_ports[0].bits.uop.debug_inst \n connect slots_3.io.wakeup_ports[0].bits.uop.inst, issue_slots[3].wakeup_ports[0].bits.uop.inst \n connect slots_3.io.wakeup_ports[0].valid, issue_slots[3].wakeup_ports[0].valid \n connect slots_3.io.wakeup_ports[1].bits.rebusy, issue_slots[3].wakeup_ports[1].bits.rebusy \n connect slots_3.io.wakeup_ports[1].bits.speculative_mask, issue_slots[3].wakeup_ports[1].bits.speculative_mask \n connect slots_3.io.wakeup_ports[1].bits.bypassable, issue_slots[3].wakeup_ports[1].bits.bypassable \n connect slots_3.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[3].wakeup_ports[1].bits.uop.debug_tsrc \n connect slots_3.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[3].wakeup_ports[1].bits.uop.debug_fsrc \n connect slots_3.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[3].wakeup_ports[1].bits.uop.bp_xcpt_if \n connect slots_3.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[3].wakeup_ports[1].bits.uop.bp_debug_if \n connect slots_3.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[3].wakeup_ports[1].bits.uop.xcpt_ma_if \n connect slots_3.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[3].wakeup_ports[1].bits.uop.xcpt_ae_if \n connect slots_3.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[3].wakeup_ports[1].bits.uop.xcpt_pf_if \n connect slots_3.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[3].wakeup_ports[1].bits.uop.fp_typ \n connect slots_3.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[3].wakeup_ports[1].bits.uop.fp_rm \n connect slots_3.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[3].wakeup_ports[1].bits.uop.fp_val \n connect slots_3.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[3].wakeup_ports[1].bits.uop.fcn_op \n connect slots_3.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[3].wakeup_ports[1].bits.uop.fcn_dw \n connect slots_3.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[3].wakeup_ports[1].bits.uop.frs3_en \n connect slots_3.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[3].wakeup_ports[1].bits.uop.lrs2_rtype \n connect slots_3.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[3].wakeup_ports[1].bits.uop.lrs1_rtype \n connect slots_3.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[3].wakeup_ports[1].bits.uop.dst_rtype \n connect slots_3.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[3].wakeup_ports[1].bits.uop.lrs3 \n connect slots_3.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[3].wakeup_ports[1].bits.uop.lrs2 \n connect slots_3.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[3].wakeup_ports[1].bits.uop.lrs1 \n connect slots_3.io.wakeup_ports[1].bits.uop.ldst, issue_slots[3].wakeup_ports[1].bits.uop.ldst \n connect slots_3.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[3].wakeup_ports[1].bits.uop.ldst_is_rs1 \n connect slots_3.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[3].wakeup_ports[1].bits.uop.csr_cmd \n connect slots_3.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[3].wakeup_ports[1].bits.uop.flush_on_commit \n connect slots_3.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[3].wakeup_ports[1].bits.uop.is_unique \n connect slots_3.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[3].wakeup_ports[1].bits.uop.uses_stq \n connect slots_3.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[3].wakeup_ports[1].bits.uop.uses_ldq \n connect slots_3.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[3].wakeup_ports[1].bits.uop.mem_signed \n connect slots_3.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[3].wakeup_ports[1].bits.uop.mem_size \n connect slots_3.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[3].wakeup_ports[1].bits.uop.mem_cmd \n connect slots_3.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[3].wakeup_ports[1].bits.uop.exc_cause \n connect slots_3.io.wakeup_ports[1].bits.uop.exception, issue_slots[3].wakeup_ports[1].bits.uop.exception \n connect slots_3.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[3].wakeup_ports[1].bits.uop.stale_pdst \n connect slots_3.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[3].wakeup_ports[1].bits.uop.ppred_busy \n connect slots_3.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[3].wakeup_ports[1].bits.uop.prs3_busy \n connect slots_3.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[3].wakeup_ports[1].bits.uop.prs2_busy \n connect slots_3.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[3].wakeup_ports[1].bits.uop.prs1_busy \n connect slots_3.io.wakeup_ports[1].bits.uop.ppred, issue_slots[3].wakeup_ports[1].bits.uop.ppred \n connect slots_3.io.wakeup_ports[1].bits.uop.prs3, issue_slots[3].wakeup_ports[1].bits.uop.prs3 \n connect slots_3.io.wakeup_ports[1].bits.uop.prs2, issue_slots[3].wakeup_ports[1].bits.uop.prs2 \n connect slots_3.io.wakeup_ports[1].bits.uop.prs1, issue_slots[3].wakeup_ports[1].bits.uop.prs1 \n connect slots_3.io.wakeup_ports[1].bits.uop.pdst, issue_slots[3].wakeup_ports[1].bits.uop.pdst \n connect slots_3.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[3].wakeup_ports[1].bits.uop.rxq_idx \n connect slots_3.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[3].wakeup_ports[1].bits.uop.stq_idx \n connect slots_3.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[3].wakeup_ports[1].bits.uop.ldq_idx \n connect slots_3.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[3].wakeup_ports[1].bits.uop.rob_idx \n connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.vec \n connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.wflags \n connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.sqrt \n connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.div \n connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.fma \n connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe \n connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.toint \n connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.fromint \n connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut \n connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn \n connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.swap23 \n connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.swap12 \n connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.ren3 \n connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.ren2 \n connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.ren1 \n connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.wen \n connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.ldst \n connect slots_3.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[3].wakeup_ports[1].bits.uop.op2_sel \n connect slots_3.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[3].wakeup_ports[1].bits.uop.op1_sel \n connect slots_3.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[3].wakeup_ports[1].bits.uop.imm_packed \n connect slots_3.io.wakeup_ports[1].bits.uop.pimm, issue_slots[3].wakeup_ports[1].bits.uop.pimm \n connect slots_3.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[3].wakeup_ports[1].bits.uop.imm_sel \n connect slots_3.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[3].wakeup_ports[1].bits.uop.imm_rename \n connect slots_3.io.wakeup_ports[1].bits.uop.taken, issue_slots[3].wakeup_ports[1].bits.uop.taken \n connect slots_3.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[3].wakeup_ports[1].bits.uop.pc_lob \n connect slots_3.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[3].wakeup_ports[1].bits.uop.edge_inst \n connect slots_3.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[3].wakeup_ports[1].bits.uop.ftq_idx \n connect slots_3.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[3].wakeup_ports[1].bits.uop.is_mov \n connect slots_3.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[3].wakeup_ports[1].bits.uop.is_rocc \n connect slots_3.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[3].wakeup_ports[1].bits.uop.is_sys_pc2epc \n connect slots_3.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[3].wakeup_ports[1].bits.uop.is_eret \n connect slots_3.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[3].wakeup_ports[1].bits.uop.is_amo \n connect slots_3.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[3].wakeup_ports[1].bits.uop.is_sfence \n connect slots_3.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[3].wakeup_ports[1].bits.uop.is_fencei \n connect slots_3.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[3].wakeup_ports[1].bits.uop.is_fence \n connect slots_3.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[3].wakeup_ports[1].bits.uop.is_sfb \n connect slots_3.io.wakeup_ports[1].bits.uop.br_type, issue_slots[3].wakeup_ports[1].bits.uop.br_type \n connect slots_3.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[3].wakeup_ports[1].bits.uop.br_tag \n connect slots_3.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[3].wakeup_ports[1].bits.uop.br_mask \n connect slots_3.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[3].wakeup_ports[1].bits.uop.dis_col_sel \n connect slots_3.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[3].wakeup_ports[1].bits.uop.iw_p3_bypass_hint \n connect slots_3.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[3].wakeup_ports[1].bits.uop.iw_p2_bypass_hint \n connect slots_3.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[3].wakeup_ports[1].bits.uop.iw_p1_bypass_hint \n connect slots_3.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[3].wakeup_ports[1].bits.uop.iw_p2_speculative_child \n connect slots_3.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[3].wakeup_ports[1].bits.uop.iw_p1_speculative_child \n connect slots_3.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[3].wakeup_ports[1].bits.uop.iw_issued_partial_dgen \n connect slots_3.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[3].wakeup_ports[1].bits.uop.iw_issued_partial_agen \n connect slots_3.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[3].wakeup_ports[1].bits.uop.iw_issued \n connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[0] \n connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[1] \n connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[2] \n connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[3] \n connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[4] \n connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[5] \n connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[6] \n connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[7] \n connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[8] \n connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[9] \n connect slots_3.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[3].wakeup_ports[1].bits.uop.iq_type[0] \n connect slots_3.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[3].wakeup_ports[1].bits.uop.iq_type[1] \n connect slots_3.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[3].wakeup_ports[1].bits.uop.iq_type[2] \n connect slots_3.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[3].wakeup_ports[1].bits.uop.iq_type[3] \n connect slots_3.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[3].wakeup_ports[1].bits.uop.debug_pc \n connect slots_3.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[3].wakeup_ports[1].bits.uop.is_rvc \n connect slots_3.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[3].wakeup_ports[1].bits.uop.debug_inst \n connect slots_3.io.wakeup_ports[1].bits.uop.inst, issue_slots[3].wakeup_ports[1].bits.uop.inst \n connect slots_3.io.wakeup_ports[1].valid, issue_slots[3].wakeup_ports[1].valid \n connect slots_3.io.wakeup_ports[2].bits.rebusy, issue_slots[3].wakeup_ports[2].bits.rebusy \n connect slots_3.io.wakeup_ports[2].bits.speculative_mask, issue_slots[3].wakeup_ports[2].bits.speculative_mask \n connect slots_3.io.wakeup_ports[2].bits.bypassable, issue_slots[3].wakeup_ports[2].bits.bypassable \n connect slots_3.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[3].wakeup_ports[2].bits.uop.debug_tsrc \n connect slots_3.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[3].wakeup_ports[2].bits.uop.debug_fsrc \n connect slots_3.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[3].wakeup_ports[2].bits.uop.bp_xcpt_if \n connect slots_3.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[3].wakeup_ports[2].bits.uop.bp_debug_if \n connect slots_3.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[3].wakeup_ports[2].bits.uop.xcpt_ma_if \n connect slots_3.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[3].wakeup_ports[2].bits.uop.xcpt_ae_if \n connect slots_3.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[3].wakeup_ports[2].bits.uop.xcpt_pf_if \n connect slots_3.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[3].wakeup_ports[2].bits.uop.fp_typ \n connect slots_3.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[3].wakeup_ports[2].bits.uop.fp_rm \n connect slots_3.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[3].wakeup_ports[2].bits.uop.fp_val \n connect slots_3.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[3].wakeup_ports[2].bits.uop.fcn_op \n connect slots_3.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[3].wakeup_ports[2].bits.uop.fcn_dw \n connect slots_3.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[3].wakeup_ports[2].bits.uop.frs3_en \n connect slots_3.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[3].wakeup_ports[2].bits.uop.lrs2_rtype \n connect slots_3.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[3].wakeup_ports[2].bits.uop.lrs1_rtype \n connect slots_3.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[3].wakeup_ports[2].bits.uop.dst_rtype \n connect slots_3.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[3].wakeup_ports[2].bits.uop.lrs3 \n connect slots_3.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[3].wakeup_ports[2].bits.uop.lrs2 \n connect slots_3.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[3].wakeup_ports[2].bits.uop.lrs1 \n connect slots_3.io.wakeup_ports[2].bits.uop.ldst, issue_slots[3].wakeup_ports[2].bits.uop.ldst \n connect slots_3.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[3].wakeup_ports[2].bits.uop.ldst_is_rs1 \n connect slots_3.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[3].wakeup_ports[2].bits.uop.csr_cmd \n connect slots_3.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[3].wakeup_ports[2].bits.uop.flush_on_commit \n connect slots_3.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[3].wakeup_ports[2].bits.uop.is_unique \n connect slots_3.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[3].wakeup_ports[2].bits.uop.uses_stq \n connect slots_3.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[3].wakeup_ports[2].bits.uop.uses_ldq \n connect slots_3.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[3].wakeup_ports[2].bits.uop.mem_signed \n connect slots_3.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[3].wakeup_ports[2].bits.uop.mem_size \n connect slots_3.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[3].wakeup_ports[2].bits.uop.mem_cmd \n connect slots_3.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[3].wakeup_ports[2].bits.uop.exc_cause \n connect slots_3.io.wakeup_ports[2].bits.uop.exception, issue_slots[3].wakeup_ports[2].bits.uop.exception \n connect slots_3.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[3].wakeup_ports[2].bits.uop.stale_pdst \n connect slots_3.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[3].wakeup_ports[2].bits.uop.ppred_busy \n connect slots_3.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[3].wakeup_ports[2].bits.uop.prs3_busy \n connect slots_3.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[3].wakeup_ports[2].bits.uop.prs2_busy \n connect slots_3.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[3].wakeup_ports[2].bits.uop.prs1_busy \n connect slots_3.io.wakeup_ports[2].bits.uop.ppred, issue_slots[3].wakeup_ports[2].bits.uop.ppred \n connect slots_3.io.wakeup_ports[2].bits.uop.prs3, issue_slots[3].wakeup_ports[2].bits.uop.prs3 \n connect slots_3.io.wakeup_ports[2].bits.uop.prs2, issue_slots[3].wakeup_ports[2].bits.uop.prs2 \n connect slots_3.io.wakeup_ports[2].bits.uop.prs1, issue_slots[3].wakeup_ports[2].bits.uop.prs1 \n connect slots_3.io.wakeup_ports[2].bits.uop.pdst, issue_slots[3].wakeup_ports[2].bits.uop.pdst \n connect slots_3.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[3].wakeup_ports[2].bits.uop.rxq_idx \n connect slots_3.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[3].wakeup_ports[2].bits.uop.stq_idx \n connect slots_3.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[3].wakeup_ports[2].bits.uop.ldq_idx \n connect slots_3.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[3].wakeup_ports[2].bits.uop.rob_idx \n connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.vec \n connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.wflags \n connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.sqrt \n connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.div \n connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.fma \n connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe \n connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.toint \n connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.fromint \n connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut \n connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn \n connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.swap23 \n connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.swap12 \n connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.ren3 \n connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.ren2 \n connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.ren1 \n connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.wen \n connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.ldst \n connect slots_3.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[3].wakeup_ports[2].bits.uop.op2_sel \n connect slots_3.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[3].wakeup_ports[2].bits.uop.op1_sel \n connect slots_3.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[3].wakeup_ports[2].bits.uop.imm_packed \n connect slots_3.io.wakeup_ports[2].bits.uop.pimm, issue_slots[3].wakeup_ports[2].bits.uop.pimm \n connect slots_3.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[3].wakeup_ports[2].bits.uop.imm_sel \n connect slots_3.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[3].wakeup_ports[2].bits.uop.imm_rename \n connect slots_3.io.wakeup_ports[2].bits.uop.taken, issue_slots[3].wakeup_ports[2].bits.uop.taken \n connect slots_3.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[3].wakeup_ports[2].bits.uop.pc_lob \n connect slots_3.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[3].wakeup_ports[2].bits.uop.edge_inst \n connect slots_3.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[3].wakeup_ports[2].bits.uop.ftq_idx \n connect slots_3.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[3].wakeup_ports[2].bits.uop.is_mov \n connect slots_3.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[3].wakeup_ports[2].bits.uop.is_rocc \n connect slots_3.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[3].wakeup_ports[2].bits.uop.is_sys_pc2epc \n connect slots_3.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[3].wakeup_ports[2].bits.uop.is_eret \n connect slots_3.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[3].wakeup_ports[2].bits.uop.is_amo \n connect slots_3.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[3].wakeup_ports[2].bits.uop.is_sfence \n connect slots_3.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[3].wakeup_ports[2].bits.uop.is_fencei \n connect slots_3.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[3].wakeup_ports[2].bits.uop.is_fence \n connect slots_3.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[3].wakeup_ports[2].bits.uop.is_sfb \n connect slots_3.io.wakeup_ports[2].bits.uop.br_type, issue_slots[3].wakeup_ports[2].bits.uop.br_type \n connect slots_3.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[3].wakeup_ports[2].bits.uop.br_tag \n connect slots_3.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[3].wakeup_ports[2].bits.uop.br_mask \n connect slots_3.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[3].wakeup_ports[2].bits.uop.dis_col_sel \n connect slots_3.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[3].wakeup_ports[2].bits.uop.iw_p3_bypass_hint \n connect slots_3.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[3].wakeup_ports[2].bits.uop.iw_p2_bypass_hint \n connect slots_3.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[3].wakeup_ports[2].bits.uop.iw_p1_bypass_hint \n connect slots_3.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[3].wakeup_ports[2].bits.uop.iw_p2_speculative_child \n connect slots_3.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[3].wakeup_ports[2].bits.uop.iw_p1_speculative_child \n connect slots_3.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[3].wakeup_ports[2].bits.uop.iw_issued_partial_dgen \n connect slots_3.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[3].wakeup_ports[2].bits.uop.iw_issued_partial_agen \n connect slots_3.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[3].wakeup_ports[2].bits.uop.iw_issued \n connect slots_3.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[3].wakeup_ports[2].bits.uop.fu_code[0] \n connect slots_3.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[3].wakeup_ports[2].bits.uop.fu_code[1] \n connect slots_3.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[3].wakeup_ports[2].bits.uop.fu_code[2] \n connect slots_3.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[3].wakeup_ports[2].bits.uop.fu_code[3] \n connect slots_3.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[3].wakeup_ports[2].bits.uop.fu_code[4] \n connect slots_3.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[3].wakeup_ports[2].bits.uop.fu_code[5] \n connect slots_3.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[3].wakeup_ports[2].bits.uop.fu_code[6] \n connect slots_3.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[3].wakeup_ports[2].bits.uop.fu_code[7] \n connect slots_3.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[3].wakeup_ports[2].bits.uop.fu_code[8] \n connect slots_3.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[3].wakeup_ports[2].bits.uop.fu_code[9] \n connect slots_3.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[3].wakeup_ports[2].bits.uop.iq_type[0] \n connect slots_3.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[3].wakeup_ports[2].bits.uop.iq_type[1] \n connect slots_3.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[3].wakeup_ports[2].bits.uop.iq_type[2] \n connect slots_3.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[3].wakeup_ports[2].bits.uop.iq_type[3] \n connect slots_3.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[3].wakeup_ports[2].bits.uop.debug_pc \n connect slots_3.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[3].wakeup_ports[2].bits.uop.is_rvc \n connect slots_3.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[3].wakeup_ports[2].bits.uop.debug_inst \n connect slots_3.io.wakeup_ports[2].bits.uop.inst, issue_slots[3].wakeup_ports[2].bits.uop.inst \n connect slots_3.io.wakeup_ports[2].valid, issue_slots[3].wakeup_ports[2].valid \n connect slots_3.io.wakeup_ports[3].bits.rebusy, issue_slots[3].wakeup_ports[3].bits.rebusy \n connect slots_3.io.wakeup_ports[3].bits.speculative_mask, issue_slots[3].wakeup_ports[3].bits.speculative_mask \n connect slots_3.io.wakeup_ports[3].bits.bypassable, issue_slots[3].wakeup_ports[3].bits.bypassable \n connect slots_3.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[3].wakeup_ports[3].bits.uop.debug_tsrc \n connect slots_3.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[3].wakeup_ports[3].bits.uop.debug_fsrc \n connect slots_3.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[3].wakeup_ports[3].bits.uop.bp_xcpt_if \n connect slots_3.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[3].wakeup_ports[3].bits.uop.bp_debug_if \n connect slots_3.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[3].wakeup_ports[3].bits.uop.xcpt_ma_if \n connect slots_3.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[3].wakeup_ports[3].bits.uop.xcpt_ae_if \n connect slots_3.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[3].wakeup_ports[3].bits.uop.xcpt_pf_if \n connect slots_3.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[3].wakeup_ports[3].bits.uop.fp_typ \n connect slots_3.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[3].wakeup_ports[3].bits.uop.fp_rm \n connect slots_3.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[3].wakeup_ports[3].bits.uop.fp_val \n connect slots_3.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[3].wakeup_ports[3].bits.uop.fcn_op \n connect slots_3.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[3].wakeup_ports[3].bits.uop.fcn_dw \n connect slots_3.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[3].wakeup_ports[3].bits.uop.frs3_en \n connect slots_3.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[3].wakeup_ports[3].bits.uop.lrs2_rtype \n connect slots_3.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[3].wakeup_ports[3].bits.uop.lrs1_rtype \n connect slots_3.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[3].wakeup_ports[3].bits.uop.dst_rtype \n connect slots_3.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[3].wakeup_ports[3].bits.uop.lrs3 \n connect slots_3.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[3].wakeup_ports[3].bits.uop.lrs2 \n connect slots_3.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[3].wakeup_ports[3].bits.uop.lrs1 \n connect slots_3.io.wakeup_ports[3].bits.uop.ldst, issue_slots[3].wakeup_ports[3].bits.uop.ldst \n connect slots_3.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[3].wakeup_ports[3].bits.uop.ldst_is_rs1 \n connect slots_3.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[3].wakeup_ports[3].bits.uop.csr_cmd \n connect slots_3.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[3].wakeup_ports[3].bits.uop.flush_on_commit \n connect slots_3.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[3].wakeup_ports[3].bits.uop.is_unique \n connect slots_3.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[3].wakeup_ports[3].bits.uop.uses_stq \n connect slots_3.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[3].wakeup_ports[3].bits.uop.uses_ldq \n connect slots_3.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[3].wakeup_ports[3].bits.uop.mem_signed \n connect slots_3.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[3].wakeup_ports[3].bits.uop.mem_size \n connect slots_3.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[3].wakeup_ports[3].bits.uop.mem_cmd \n connect slots_3.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[3].wakeup_ports[3].bits.uop.exc_cause \n connect slots_3.io.wakeup_ports[3].bits.uop.exception, issue_slots[3].wakeup_ports[3].bits.uop.exception \n connect slots_3.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[3].wakeup_ports[3].bits.uop.stale_pdst \n connect slots_3.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[3].wakeup_ports[3].bits.uop.ppred_busy \n connect slots_3.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[3].wakeup_ports[3].bits.uop.prs3_busy \n connect slots_3.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[3].wakeup_ports[3].bits.uop.prs2_busy \n connect slots_3.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[3].wakeup_ports[3].bits.uop.prs1_busy \n connect slots_3.io.wakeup_ports[3].bits.uop.ppred, issue_slots[3].wakeup_ports[3].bits.uop.ppred \n connect slots_3.io.wakeup_ports[3].bits.uop.prs3, issue_slots[3].wakeup_ports[3].bits.uop.prs3 \n connect slots_3.io.wakeup_ports[3].bits.uop.prs2, issue_slots[3].wakeup_ports[3].bits.uop.prs2 \n connect slots_3.io.wakeup_ports[3].bits.uop.prs1, issue_slots[3].wakeup_ports[3].bits.uop.prs1 \n connect slots_3.io.wakeup_ports[3].bits.uop.pdst, issue_slots[3].wakeup_ports[3].bits.uop.pdst \n connect slots_3.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[3].wakeup_ports[3].bits.uop.rxq_idx \n connect slots_3.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[3].wakeup_ports[3].bits.uop.stq_idx \n connect slots_3.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[3].wakeup_ports[3].bits.uop.ldq_idx \n connect slots_3.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[3].wakeup_ports[3].bits.uop.rob_idx \n connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.vec \n connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.wflags \n connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.sqrt \n connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.div \n connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.fma \n connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe \n connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.toint \n connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.fromint \n connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut \n connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn \n connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.swap23 \n connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.swap12 \n connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.ren3 \n connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.ren2 \n connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.ren1 \n connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.wen \n connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.ldst \n connect slots_3.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[3].wakeup_ports[3].bits.uop.op2_sel \n connect slots_3.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[3].wakeup_ports[3].bits.uop.op1_sel \n connect slots_3.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[3].wakeup_ports[3].bits.uop.imm_packed \n connect slots_3.io.wakeup_ports[3].bits.uop.pimm, issue_slots[3].wakeup_ports[3].bits.uop.pimm \n connect slots_3.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[3].wakeup_ports[3].bits.uop.imm_sel \n connect slots_3.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[3].wakeup_ports[3].bits.uop.imm_rename \n connect slots_3.io.wakeup_ports[3].bits.uop.taken, issue_slots[3].wakeup_ports[3].bits.uop.taken \n connect slots_3.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[3].wakeup_ports[3].bits.uop.pc_lob \n connect slots_3.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[3].wakeup_ports[3].bits.uop.edge_inst \n connect slots_3.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[3].wakeup_ports[3].bits.uop.ftq_idx \n connect slots_3.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[3].wakeup_ports[3].bits.uop.is_mov \n connect slots_3.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[3].wakeup_ports[3].bits.uop.is_rocc \n connect slots_3.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[3].wakeup_ports[3].bits.uop.is_sys_pc2epc \n connect slots_3.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[3].wakeup_ports[3].bits.uop.is_eret \n connect slots_3.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[3].wakeup_ports[3].bits.uop.is_amo \n connect slots_3.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[3].wakeup_ports[3].bits.uop.is_sfence \n connect slots_3.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[3].wakeup_ports[3].bits.uop.is_fencei \n connect slots_3.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[3].wakeup_ports[3].bits.uop.is_fence \n connect slots_3.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[3].wakeup_ports[3].bits.uop.is_sfb \n connect slots_3.io.wakeup_ports[3].bits.uop.br_type, issue_slots[3].wakeup_ports[3].bits.uop.br_type \n connect slots_3.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[3].wakeup_ports[3].bits.uop.br_tag \n connect slots_3.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[3].wakeup_ports[3].bits.uop.br_mask \n connect slots_3.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[3].wakeup_ports[3].bits.uop.dis_col_sel \n connect slots_3.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[3].wakeup_ports[3].bits.uop.iw_p3_bypass_hint \n connect slots_3.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[3].wakeup_ports[3].bits.uop.iw_p2_bypass_hint \n connect slots_3.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[3].wakeup_ports[3].bits.uop.iw_p1_bypass_hint \n connect slots_3.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[3].wakeup_ports[3].bits.uop.iw_p2_speculative_child \n connect slots_3.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[3].wakeup_ports[3].bits.uop.iw_p1_speculative_child \n connect slots_3.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[3].wakeup_ports[3].bits.uop.iw_issued_partial_dgen \n connect slots_3.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[3].wakeup_ports[3].bits.uop.iw_issued_partial_agen \n connect slots_3.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[3].wakeup_ports[3].bits.uop.iw_issued \n connect slots_3.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[3].wakeup_ports[3].bits.uop.fu_code[0] \n connect slots_3.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[3].wakeup_ports[3].bits.uop.fu_code[1] \n connect slots_3.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[3].wakeup_ports[3].bits.uop.fu_code[2] \n connect slots_3.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[3].wakeup_ports[3].bits.uop.fu_code[3] \n connect slots_3.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[3].wakeup_ports[3].bits.uop.fu_code[4] \n connect slots_3.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[3].wakeup_ports[3].bits.uop.fu_code[5] \n connect slots_3.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[3].wakeup_ports[3].bits.uop.fu_code[6] \n connect slots_3.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[3].wakeup_ports[3].bits.uop.fu_code[7] \n connect slots_3.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[3].wakeup_ports[3].bits.uop.fu_code[8] \n connect slots_3.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[3].wakeup_ports[3].bits.uop.fu_code[9] \n connect slots_3.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[3].wakeup_ports[3].bits.uop.iq_type[0] \n connect slots_3.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[3].wakeup_ports[3].bits.uop.iq_type[1] \n connect slots_3.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[3].wakeup_ports[3].bits.uop.iq_type[2] \n connect slots_3.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[3].wakeup_ports[3].bits.uop.iq_type[3] \n connect slots_3.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[3].wakeup_ports[3].bits.uop.debug_pc \n connect slots_3.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[3].wakeup_ports[3].bits.uop.is_rvc \n connect slots_3.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[3].wakeup_ports[3].bits.uop.debug_inst \n connect slots_3.io.wakeup_ports[3].bits.uop.inst, issue_slots[3].wakeup_ports[3].bits.uop.inst \n connect slots_3.io.wakeup_ports[3].valid, issue_slots[3].wakeup_ports[3].valid \n connect slots_3.io.squash_grant, issue_slots[3].squash_grant \n connect slots_3.io.clear, issue_slots[3].clear \n connect slots_3.io.kill, issue_slots[3].kill \n connect slots_3.io.brupdate.b2.target_offset, issue_slots[3].brupdate.b2.target_offset \n connect slots_3.io.brupdate.b2.jalr_target, issue_slots[3].brupdate.b2.jalr_target \n connect slots_3.io.brupdate.b2.pc_sel, issue_slots[3].brupdate.b2.pc_sel \n connect slots_3.io.brupdate.b2.cfi_type, issue_slots[3].brupdate.b2.cfi_type \n connect slots_3.io.brupdate.b2.taken, issue_slots[3].brupdate.b2.taken \n connect slots_3.io.brupdate.b2.mispredict, issue_slots[3].brupdate.b2.mispredict \n connect slots_3.io.brupdate.b2.uop.debug_tsrc, issue_slots[3].brupdate.b2.uop.debug_tsrc \n connect slots_3.io.brupdate.b2.uop.debug_fsrc, issue_slots[3].brupdate.b2.uop.debug_fsrc \n connect slots_3.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[3].brupdate.b2.uop.bp_xcpt_if \n connect slots_3.io.brupdate.b2.uop.bp_debug_if, issue_slots[3].brupdate.b2.uop.bp_debug_if \n connect slots_3.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[3].brupdate.b2.uop.xcpt_ma_if \n connect slots_3.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[3].brupdate.b2.uop.xcpt_ae_if \n connect slots_3.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[3].brupdate.b2.uop.xcpt_pf_if \n connect slots_3.io.brupdate.b2.uop.fp_typ, issue_slots[3].brupdate.b2.uop.fp_typ \n connect slots_3.io.brupdate.b2.uop.fp_rm, issue_slots[3].brupdate.b2.uop.fp_rm \n connect slots_3.io.brupdate.b2.uop.fp_val, issue_slots[3].brupdate.b2.uop.fp_val \n connect slots_3.io.brupdate.b2.uop.fcn_op, issue_slots[3].brupdate.b2.uop.fcn_op \n connect slots_3.io.brupdate.b2.uop.fcn_dw, issue_slots[3].brupdate.b2.uop.fcn_dw \n connect slots_3.io.brupdate.b2.uop.frs3_en, issue_slots[3].brupdate.b2.uop.frs3_en \n connect slots_3.io.brupdate.b2.uop.lrs2_rtype, issue_slots[3].brupdate.b2.uop.lrs2_rtype \n connect slots_3.io.brupdate.b2.uop.lrs1_rtype, issue_slots[3].brupdate.b2.uop.lrs1_rtype \n connect slots_3.io.brupdate.b2.uop.dst_rtype, issue_slots[3].brupdate.b2.uop.dst_rtype \n connect slots_3.io.brupdate.b2.uop.lrs3, issue_slots[3].brupdate.b2.uop.lrs3 \n connect slots_3.io.brupdate.b2.uop.lrs2, issue_slots[3].brupdate.b2.uop.lrs2 \n connect slots_3.io.brupdate.b2.uop.lrs1, issue_slots[3].brupdate.b2.uop.lrs1 \n connect slots_3.io.brupdate.b2.uop.ldst, issue_slots[3].brupdate.b2.uop.ldst \n connect slots_3.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[3].brupdate.b2.uop.ldst_is_rs1 \n connect slots_3.io.brupdate.b2.uop.csr_cmd, issue_slots[3].brupdate.b2.uop.csr_cmd \n connect slots_3.io.brupdate.b2.uop.flush_on_commit, issue_slots[3].brupdate.b2.uop.flush_on_commit \n connect slots_3.io.brupdate.b2.uop.is_unique, issue_slots[3].brupdate.b2.uop.is_unique \n connect slots_3.io.brupdate.b2.uop.uses_stq, issue_slots[3].brupdate.b2.uop.uses_stq \n connect slots_3.io.brupdate.b2.uop.uses_ldq, issue_slots[3].brupdate.b2.uop.uses_ldq \n connect slots_3.io.brupdate.b2.uop.mem_signed, issue_slots[3].brupdate.b2.uop.mem_signed \n connect slots_3.io.brupdate.b2.uop.mem_size, issue_slots[3].brupdate.b2.uop.mem_size \n connect slots_3.io.brupdate.b2.uop.mem_cmd, issue_slots[3].brupdate.b2.uop.mem_cmd \n connect slots_3.io.brupdate.b2.uop.exc_cause, issue_slots[3].brupdate.b2.uop.exc_cause \n connect slots_3.io.brupdate.b2.uop.exception, issue_slots[3].brupdate.b2.uop.exception \n connect slots_3.io.brupdate.b2.uop.stale_pdst, issue_slots[3].brupdate.b2.uop.stale_pdst \n connect slots_3.io.brupdate.b2.uop.ppred_busy, issue_slots[3].brupdate.b2.uop.ppred_busy \n connect slots_3.io.brupdate.b2.uop.prs3_busy, issue_slots[3].brupdate.b2.uop.prs3_busy \n connect slots_3.io.brupdate.b2.uop.prs2_busy, issue_slots[3].brupdate.b2.uop.prs2_busy \n connect slots_3.io.brupdate.b2.uop.prs1_busy, issue_slots[3].brupdate.b2.uop.prs1_busy \n connect slots_3.io.brupdate.b2.uop.ppred, issue_slots[3].brupdate.b2.uop.ppred \n connect slots_3.io.brupdate.b2.uop.prs3, issue_slots[3].brupdate.b2.uop.prs3 \n connect slots_3.io.brupdate.b2.uop.prs2, issue_slots[3].brupdate.b2.uop.prs2 \n connect slots_3.io.brupdate.b2.uop.prs1, issue_slots[3].brupdate.b2.uop.prs1 \n connect slots_3.io.brupdate.b2.uop.pdst, issue_slots[3].brupdate.b2.uop.pdst \n connect slots_3.io.brupdate.b2.uop.rxq_idx, issue_slots[3].brupdate.b2.uop.rxq_idx \n connect slots_3.io.brupdate.b2.uop.stq_idx, issue_slots[3].brupdate.b2.uop.stq_idx \n connect slots_3.io.brupdate.b2.uop.ldq_idx, issue_slots[3].brupdate.b2.uop.ldq_idx \n connect slots_3.io.brupdate.b2.uop.rob_idx, issue_slots[3].brupdate.b2.uop.rob_idx \n connect slots_3.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[3].brupdate.b2.uop.fp_ctrl.vec \n connect slots_3.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[3].brupdate.b2.uop.fp_ctrl.wflags \n connect slots_3.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[3].brupdate.b2.uop.fp_ctrl.sqrt \n connect slots_3.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[3].brupdate.b2.uop.fp_ctrl.div \n connect slots_3.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[3].brupdate.b2.uop.fp_ctrl.fma \n connect slots_3.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[3].brupdate.b2.uop.fp_ctrl.fastpipe \n connect slots_3.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[3].brupdate.b2.uop.fp_ctrl.toint \n connect slots_3.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[3].brupdate.b2.uop.fp_ctrl.fromint \n connect slots_3.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[3].brupdate.b2.uop.fp_ctrl.typeTagOut \n connect slots_3.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[3].brupdate.b2.uop.fp_ctrl.typeTagIn \n connect slots_3.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[3].brupdate.b2.uop.fp_ctrl.swap23 \n connect slots_3.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[3].brupdate.b2.uop.fp_ctrl.swap12 \n connect slots_3.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[3].brupdate.b2.uop.fp_ctrl.ren3 \n connect slots_3.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[3].brupdate.b2.uop.fp_ctrl.ren2 \n connect slots_3.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[3].brupdate.b2.uop.fp_ctrl.ren1 \n connect slots_3.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[3].brupdate.b2.uop.fp_ctrl.wen \n connect slots_3.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[3].brupdate.b2.uop.fp_ctrl.ldst \n connect slots_3.io.brupdate.b2.uop.op2_sel, issue_slots[3].brupdate.b2.uop.op2_sel \n connect slots_3.io.brupdate.b2.uop.op1_sel, issue_slots[3].brupdate.b2.uop.op1_sel \n connect slots_3.io.brupdate.b2.uop.imm_packed, issue_slots[3].brupdate.b2.uop.imm_packed \n connect slots_3.io.brupdate.b2.uop.pimm, issue_slots[3].brupdate.b2.uop.pimm \n connect slots_3.io.brupdate.b2.uop.imm_sel, issue_slots[3].brupdate.b2.uop.imm_sel \n connect slots_3.io.brupdate.b2.uop.imm_rename, issue_slots[3].brupdate.b2.uop.imm_rename \n connect slots_3.io.brupdate.b2.uop.taken, issue_slots[3].brupdate.b2.uop.taken \n connect slots_3.io.brupdate.b2.uop.pc_lob, issue_slots[3].brupdate.b2.uop.pc_lob \n connect slots_3.io.brupdate.b2.uop.edge_inst, issue_slots[3].brupdate.b2.uop.edge_inst \n connect slots_3.io.brupdate.b2.uop.ftq_idx, issue_slots[3].brupdate.b2.uop.ftq_idx \n connect slots_3.io.brupdate.b2.uop.is_mov, issue_slots[3].brupdate.b2.uop.is_mov \n connect slots_3.io.brupdate.b2.uop.is_rocc, issue_slots[3].brupdate.b2.uop.is_rocc \n connect slots_3.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[3].brupdate.b2.uop.is_sys_pc2epc \n connect slots_3.io.brupdate.b2.uop.is_eret, issue_slots[3].brupdate.b2.uop.is_eret \n connect slots_3.io.brupdate.b2.uop.is_amo, issue_slots[3].brupdate.b2.uop.is_amo \n connect slots_3.io.brupdate.b2.uop.is_sfence, issue_slots[3].brupdate.b2.uop.is_sfence \n connect slots_3.io.brupdate.b2.uop.is_fencei, issue_slots[3].brupdate.b2.uop.is_fencei \n connect slots_3.io.brupdate.b2.uop.is_fence, issue_slots[3].brupdate.b2.uop.is_fence \n connect slots_3.io.brupdate.b2.uop.is_sfb, issue_slots[3].brupdate.b2.uop.is_sfb \n connect slots_3.io.brupdate.b2.uop.br_type, issue_slots[3].brupdate.b2.uop.br_type \n connect slots_3.io.brupdate.b2.uop.br_tag, issue_slots[3].brupdate.b2.uop.br_tag \n connect slots_3.io.brupdate.b2.uop.br_mask, issue_slots[3].brupdate.b2.uop.br_mask \n connect slots_3.io.brupdate.b2.uop.dis_col_sel, issue_slots[3].brupdate.b2.uop.dis_col_sel \n connect slots_3.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[3].brupdate.b2.uop.iw_p3_bypass_hint \n connect slots_3.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[3].brupdate.b2.uop.iw_p2_bypass_hint \n connect slots_3.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[3].brupdate.b2.uop.iw_p1_bypass_hint \n connect slots_3.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[3].brupdate.b2.uop.iw_p2_speculative_child \n connect slots_3.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[3].brupdate.b2.uop.iw_p1_speculative_child \n connect slots_3.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[3].brupdate.b2.uop.iw_issued_partial_dgen \n connect slots_3.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[3].brupdate.b2.uop.iw_issued_partial_agen \n connect slots_3.io.brupdate.b2.uop.iw_issued, issue_slots[3].brupdate.b2.uop.iw_issued \n connect slots_3.io.brupdate.b2.uop.fu_code[0], issue_slots[3].brupdate.b2.uop.fu_code[0] \n connect slots_3.io.brupdate.b2.uop.fu_code[1], issue_slots[3].brupdate.b2.uop.fu_code[1] \n connect slots_3.io.brupdate.b2.uop.fu_code[2], issue_slots[3].brupdate.b2.uop.fu_code[2] \n connect slots_3.io.brupdate.b2.uop.fu_code[3], issue_slots[3].brupdate.b2.uop.fu_code[3] \n connect slots_3.io.brupdate.b2.uop.fu_code[4], issue_slots[3].brupdate.b2.uop.fu_code[4] \n connect slots_3.io.brupdate.b2.uop.fu_code[5], issue_slots[3].brupdate.b2.uop.fu_code[5] \n connect slots_3.io.brupdate.b2.uop.fu_code[6], issue_slots[3].brupdate.b2.uop.fu_code[6] \n connect slots_3.io.brupdate.b2.uop.fu_code[7], issue_slots[3].brupdate.b2.uop.fu_code[7] \n connect slots_3.io.brupdate.b2.uop.fu_code[8], issue_slots[3].brupdate.b2.uop.fu_code[8] \n connect slots_3.io.brupdate.b2.uop.fu_code[9], issue_slots[3].brupdate.b2.uop.fu_code[9] \n connect slots_3.io.brupdate.b2.uop.iq_type[0], issue_slots[3].brupdate.b2.uop.iq_type[0] \n connect slots_3.io.brupdate.b2.uop.iq_type[1], issue_slots[3].brupdate.b2.uop.iq_type[1] \n connect slots_3.io.brupdate.b2.uop.iq_type[2], issue_slots[3].brupdate.b2.uop.iq_type[2] \n connect slots_3.io.brupdate.b2.uop.iq_type[3], issue_slots[3].brupdate.b2.uop.iq_type[3] \n connect slots_3.io.brupdate.b2.uop.debug_pc, issue_slots[3].brupdate.b2.uop.debug_pc \n connect slots_3.io.brupdate.b2.uop.is_rvc, issue_slots[3].brupdate.b2.uop.is_rvc \n connect slots_3.io.brupdate.b2.uop.debug_inst, issue_slots[3].brupdate.b2.uop.debug_inst \n connect slots_3.io.brupdate.b2.uop.inst, issue_slots[3].brupdate.b2.uop.inst \n connect slots_3.io.brupdate.b1.mispredict_mask, issue_slots[3].brupdate.b1.mispredict_mask \n connect slots_3.io.brupdate.b1.resolve_mask, issue_slots[3].brupdate.b1.resolve_mask \n connect issue_slots[3].out_uop.debug_tsrc, slots_3.io.out_uop.debug_tsrc \n connect issue_slots[3].out_uop.debug_fsrc, slots_3.io.out_uop.debug_fsrc \n connect issue_slots[3].out_uop.bp_xcpt_if, slots_3.io.out_uop.bp_xcpt_if \n connect issue_slots[3].out_uop.bp_debug_if, slots_3.io.out_uop.bp_debug_if \n connect issue_slots[3].out_uop.xcpt_ma_if, slots_3.io.out_uop.xcpt_ma_if \n connect issue_slots[3].out_uop.xcpt_ae_if, slots_3.io.out_uop.xcpt_ae_if \n connect issue_slots[3].out_uop.xcpt_pf_if, slots_3.io.out_uop.xcpt_pf_if \n connect issue_slots[3].out_uop.fp_typ, slots_3.io.out_uop.fp_typ \n connect issue_slots[3].out_uop.fp_rm, slots_3.io.out_uop.fp_rm \n connect issue_slots[3].out_uop.fp_val, slots_3.io.out_uop.fp_val \n connect issue_slots[3].out_uop.fcn_op, slots_3.io.out_uop.fcn_op \n connect issue_slots[3].out_uop.fcn_dw, slots_3.io.out_uop.fcn_dw \n connect issue_slots[3].out_uop.frs3_en, slots_3.io.out_uop.frs3_en \n connect issue_slots[3].out_uop.lrs2_rtype, slots_3.io.out_uop.lrs2_rtype \n connect issue_slots[3].out_uop.lrs1_rtype, slots_3.io.out_uop.lrs1_rtype \n connect issue_slots[3].out_uop.dst_rtype, slots_3.io.out_uop.dst_rtype \n connect issue_slots[3].out_uop.lrs3, slots_3.io.out_uop.lrs3 \n connect issue_slots[3].out_uop.lrs2, slots_3.io.out_uop.lrs2 \n connect issue_slots[3].out_uop.lrs1, slots_3.io.out_uop.lrs1 \n connect issue_slots[3].out_uop.ldst, slots_3.io.out_uop.ldst \n connect issue_slots[3].out_uop.ldst_is_rs1, slots_3.io.out_uop.ldst_is_rs1 \n connect issue_slots[3].out_uop.csr_cmd, slots_3.io.out_uop.csr_cmd \n connect issue_slots[3].out_uop.flush_on_commit, slots_3.io.out_uop.flush_on_commit \n connect issue_slots[3].out_uop.is_unique, slots_3.io.out_uop.is_unique \n connect issue_slots[3].out_uop.uses_stq, slots_3.io.out_uop.uses_stq \n connect issue_slots[3].out_uop.uses_ldq, slots_3.io.out_uop.uses_ldq \n connect issue_slots[3].out_uop.mem_signed, slots_3.io.out_uop.mem_signed \n connect issue_slots[3].out_uop.mem_size, slots_3.io.out_uop.mem_size \n connect issue_slots[3].out_uop.mem_cmd, slots_3.io.out_uop.mem_cmd \n connect issue_slots[3].out_uop.exc_cause, slots_3.io.out_uop.exc_cause \n connect issue_slots[3].out_uop.exception, slots_3.io.out_uop.exception \n connect issue_slots[3].out_uop.stale_pdst, slots_3.io.out_uop.stale_pdst \n connect issue_slots[3].out_uop.ppred_busy, slots_3.io.out_uop.ppred_busy \n connect issue_slots[3].out_uop.prs3_busy, slots_3.io.out_uop.prs3_busy \n connect issue_slots[3].out_uop.prs2_busy, slots_3.io.out_uop.prs2_busy \n connect issue_slots[3].out_uop.prs1_busy, slots_3.io.out_uop.prs1_busy \n connect issue_slots[3].out_uop.ppred, slots_3.io.out_uop.ppred \n connect issue_slots[3].out_uop.prs3, slots_3.io.out_uop.prs3 \n connect issue_slots[3].out_uop.prs2, slots_3.io.out_uop.prs2 \n connect issue_slots[3].out_uop.prs1, slots_3.io.out_uop.prs1 \n connect issue_slots[3].out_uop.pdst, slots_3.io.out_uop.pdst \n connect issue_slots[3].out_uop.rxq_idx, slots_3.io.out_uop.rxq_idx \n connect issue_slots[3].out_uop.stq_idx, slots_3.io.out_uop.stq_idx \n connect issue_slots[3].out_uop.ldq_idx, slots_3.io.out_uop.ldq_idx \n connect issue_slots[3].out_uop.rob_idx, slots_3.io.out_uop.rob_idx \n connect issue_slots[3].out_uop.fp_ctrl.vec, slots_3.io.out_uop.fp_ctrl.vec \n connect issue_slots[3].out_uop.fp_ctrl.wflags, slots_3.io.out_uop.fp_ctrl.wflags \n connect issue_slots[3].out_uop.fp_ctrl.sqrt, slots_3.io.out_uop.fp_ctrl.sqrt \n connect issue_slots[3].out_uop.fp_ctrl.div, slots_3.io.out_uop.fp_ctrl.div \n connect issue_slots[3].out_uop.fp_ctrl.fma, slots_3.io.out_uop.fp_ctrl.fma \n connect issue_slots[3].out_uop.fp_ctrl.fastpipe, slots_3.io.out_uop.fp_ctrl.fastpipe \n connect issue_slots[3].out_uop.fp_ctrl.toint, slots_3.io.out_uop.fp_ctrl.toint \n connect issue_slots[3].out_uop.fp_ctrl.fromint, slots_3.io.out_uop.fp_ctrl.fromint \n connect issue_slots[3].out_uop.fp_ctrl.typeTagOut, slots_3.io.out_uop.fp_ctrl.typeTagOut \n connect issue_slots[3].out_uop.fp_ctrl.typeTagIn, slots_3.io.out_uop.fp_ctrl.typeTagIn \n connect issue_slots[3].out_uop.fp_ctrl.swap23, slots_3.io.out_uop.fp_ctrl.swap23 \n connect issue_slots[3].out_uop.fp_ctrl.swap12, slots_3.io.out_uop.fp_ctrl.swap12 \n connect issue_slots[3].out_uop.fp_ctrl.ren3, slots_3.io.out_uop.fp_ctrl.ren3 \n connect issue_slots[3].out_uop.fp_ctrl.ren2, slots_3.io.out_uop.fp_ctrl.ren2 \n connect issue_slots[3].out_uop.fp_ctrl.ren1, slots_3.io.out_uop.fp_ctrl.ren1 \n connect issue_slots[3].out_uop.fp_ctrl.wen, slots_3.io.out_uop.fp_ctrl.wen \n connect issue_slots[3].out_uop.fp_ctrl.ldst, slots_3.io.out_uop.fp_ctrl.ldst \n connect issue_slots[3].out_uop.op2_sel, slots_3.io.out_uop.op2_sel \n connect issue_slots[3].out_uop.op1_sel, slots_3.io.out_uop.op1_sel \n connect issue_slots[3].out_uop.imm_packed, slots_3.io.out_uop.imm_packed \n connect issue_slots[3].out_uop.pimm, slots_3.io.out_uop.pimm \n connect issue_slots[3].out_uop.imm_sel, slots_3.io.out_uop.imm_sel \n connect issue_slots[3].out_uop.imm_rename, slots_3.io.out_uop.imm_rename \n connect issue_slots[3].out_uop.taken, slots_3.io.out_uop.taken \n connect issue_slots[3].out_uop.pc_lob, slots_3.io.out_uop.pc_lob \n connect issue_slots[3].out_uop.edge_inst, slots_3.io.out_uop.edge_inst \n connect issue_slots[3].out_uop.ftq_idx, slots_3.io.out_uop.ftq_idx \n connect issue_slots[3].out_uop.is_mov, slots_3.io.out_uop.is_mov \n connect issue_slots[3].out_uop.is_rocc, slots_3.io.out_uop.is_rocc \n connect issue_slots[3].out_uop.is_sys_pc2epc, slots_3.io.out_uop.is_sys_pc2epc \n connect issue_slots[3].out_uop.is_eret, slots_3.io.out_uop.is_eret \n connect issue_slots[3].out_uop.is_amo, slots_3.io.out_uop.is_amo \n connect issue_slots[3].out_uop.is_sfence, slots_3.io.out_uop.is_sfence \n connect issue_slots[3].out_uop.is_fencei, slots_3.io.out_uop.is_fencei \n connect issue_slots[3].out_uop.is_fence, slots_3.io.out_uop.is_fence \n connect issue_slots[3].out_uop.is_sfb, slots_3.io.out_uop.is_sfb \n connect issue_slots[3].out_uop.br_type, slots_3.io.out_uop.br_type \n connect issue_slots[3].out_uop.br_tag, slots_3.io.out_uop.br_tag \n connect issue_slots[3].out_uop.br_mask, slots_3.io.out_uop.br_mask \n connect issue_slots[3].out_uop.dis_col_sel, slots_3.io.out_uop.dis_col_sel \n connect issue_slots[3].out_uop.iw_p3_bypass_hint, slots_3.io.out_uop.iw_p3_bypass_hint \n connect issue_slots[3].out_uop.iw_p2_bypass_hint, slots_3.io.out_uop.iw_p2_bypass_hint \n connect issue_slots[3].out_uop.iw_p1_bypass_hint, slots_3.io.out_uop.iw_p1_bypass_hint \n connect issue_slots[3].out_uop.iw_p2_speculative_child, slots_3.io.out_uop.iw_p2_speculative_child \n connect issue_slots[3].out_uop.iw_p1_speculative_child, slots_3.io.out_uop.iw_p1_speculative_child \n connect issue_slots[3].out_uop.iw_issued_partial_dgen, slots_3.io.out_uop.iw_issued_partial_dgen \n connect issue_slots[3].out_uop.iw_issued_partial_agen, slots_3.io.out_uop.iw_issued_partial_agen \n connect issue_slots[3].out_uop.iw_issued, slots_3.io.out_uop.iw_issued \n connect issue_slots[3].out_uop.fu_code[0], slots_3.io.out_uop.fu_code[0] \n connect issue_slots[3].out_uop.fu_code[1], slots_3.io.out_uop.fu_code[1] \n connect issue_slots[3].out_uop.fu_code[2], slots_3.io.out_uop.fu_code[2] \n connect issue_slots[3].out_uop.fu_code[3], slots_3.io.out_uop.fu_code[3] \n connect issue_slots[3].out_uop.fu_code[4], slots_3.io.out_uop.fu_code[4] \n connect issue_slots[3].out_uop.fu_code[5], slots_3.io.out_uop.fu_code[5] \n connect issue_slots[3].out_uop.fu_code[6], slots_3.io.out_uop.fu_code[6] \n connect issue_slots[3].out_uop.fu_code[7], slots_3.io.out_uop.fu_code[7] \n connect issue_slots[3].out_uop.fu_code[8], slots_3.io.out_uop.fu_code[8] \n connect issue_slots[3].out_uop.fu_code[9], slots_3.io.out_uop.fu_code[9] \n connect issue_slots[3].out_uop.iq_type[0], slots_3.io.out_uop.iq_type[0] \n connect issue_slots[3].out_uop.iq_type[1], slots_3.io.out_uop.iq_type[1] \n connect issue_slots[3].out_uop.iq_type[2], slots_3.io.out_uop.iq_type[2] \n connect issue_slots[3].out_uop.iq_type[3], slots_3.io.out_uop.iq_type[3] \n connect issue_slots[3].out_uop.debug_pc, slots_3.io.out_uop.debug_pc \n connect issue_slots[3].out_uop.is_rvc, slots_3.io.out_uop.is_rvc \n connect issue_slots[3].out_uop.debug_inst, slots_3.io.out_uop.debug_inst \n connect issue_slots[3].out_uop.inst, slots_3.io.out_uop.inst \n connect slots_3.io.in_uop.bits.debug_tsrc, issue_slots[3].in_uop.bits.debug_tsrc \n connect slots_3.io.in_uop.bits.debug_fsrc, issue_slots[3].in_uop.bits.debug_fsrc \n connect slots_3.io.in_uop.bits.bp_xcpt_if, issue_slots[3].in_uop.bits.bp_xcpt_if \n connect slots_3.io.in_uop.bits.bp_debug_if, issue_slots[3].in_uop.bits.bp_debug_if \n connect slots_3.io.in_uop.bits.xcpt_ma_if, issue_slots[3].in_uop.bits.xcpt_ma_if \n connect slots_3.io.in_uop.bits.xcpt_ae_if, issue_slots[3].in_uop.bits.xcpt_ae_if \n connect slots_3.io.in_uop.bits.xcpt_pf_if, issue_slots[3].in_uop.bits.xcpt_pf_if \n connect slots_3.io.in_uop.bits.fp_typ, issue_slots[3].in_uop.bits.fp_typ \n connect slots_3.io.in_uop.bits.fp_rm, issue_slots[3].in_uop.bits.fp_rm \n connect slots_3.io.in_uop.bits.fp_val, issue_slots[3].in_uop.bits.fp_val \n connect slots_3.io.in_uop.bits.fcn_op, issue_slots[3].in_uop.bits.fcn_op \n connect slots_3.io.in_uop.bits.fcn_dw, issue_slots[3].in_uop.bits.fcn_dw \n connect slots_3.io.in_uop.bits.frs3_en, issue_slots[3].in_uop.bits.frs3_en \n connect slots_3.io.in_uop.bits.lrs2_rtype, issue_slots[3].in_uop.bits.lrs2_rtype \n connect slots_3.io.in_uop.bits.lrs1_rtype, issue_slots[3].in_uop.bits.lrs1_rtype \n connect slots_3.io.in_uop.bits.dst_rtype, issue_slots[3].in_uop.bits.dst_rtype \n connect slots_3.io.in_uop.bits.lrs3, issue_slots[3].in_uop.bits.lrs3 \n connect slots_3.io.in_uop.bits.lrs2, issue_slots[3].in_uop.bits.lrs2 \n connect slots_3.io.in_uop.bits.lrs1, issue_slots[3].in_uop.bits.lrs1 \n connect slots_3.io.in_uop.bits.ldst, issue_slots[3].in_uop.bits.ldst \n connect slots_3.io.in_uop.bits.ldst_is_rs1, issue_slots[3].in_uop.bits.ldst_is_rs1 \n connect slots_3.io.in_uop.bits.csr_cmd, issue_slots[3].in_uop.bits.csr_cmd \n connect slots_3.io.in_uop.bits.flush_on_commit, issue_slots[3].in_uop.bits.flush_on_commit \n connect slots_3.io.in_uop.bits.is_unique, issue_slots[3].in_uop.bits.is_unique \n connect slots_3.io.in_uop.bits.uses_stq, issue_slots[3].in_uop.bits.uses_stq \n connect slots_3.io.in_uop.bits.uses_ldq, issue_slots[3].in_uop.bits.uses_ldq \n connect slots_3.io.in_uop.bits.mem_signed, issue_slots[3].in_uop.bits.mem_signed \n connect slots_3.io.in_uop.bits.mem_size, issue_slots[3].in_uop.bits.mem_size \n connect slots_3.io.in_uop.bits.mem_cmd, issue_slots[3].in_uop.bits.mem_cmd \n connect slots_3.io.in_uop.bits.exc_cause, issue_slots[3].in_uop.bits.exc_cause \n connect slots_3.io.in_uop.bits.exception, issue_slots[3].in_uop.bits.exception \n connect slots_3.io.in_uop.bits.stale_pdst, issue_slots[3].in_uop.bits.stale_pdst \n connect slots_3.io.in_uop.bits.ppred_busy, issue_slots[3].in_uop.bits.ppred_busy \n connect slots_3.io.in_uop.bits.prs3_busy, issue_slots[3].in_uop.bits.prs3_busy \n connect slots_3.io.in_uop.bits.prs2_busy, issue_slots[3].in_uop.bits.prs2_busy \n connect slots_3.io.in_uop.bits.prs1_busy, issue_slots[3].in_uop.bits.prs1_busy \n connect slots_3.io.in_uop.bits.ppred, issue_slots[3].in_uop.bits.ppred \n connect slots_3.io.in_uop.bits.prs3, issue_slots[3].in_uop.bits.prs3 \n connect slots_3.io.in_uop.bits.prs2, issue_slots[3].in_uop.bits.prs2 \n connect slots_3.io.in_uop.bits.prs1, issue_slots[3].in_uop.bits.prs1 \n connect slots_3.io.in_uop.bits.pdst, issue_slots[3].in_uop.bits.pdst \n connect slots_3.io.in_uop.bits.rxq_idx, issue_slots[3].in_uop.bits.rxq_idx \n connect slots_3.io.in_uop.bits.stq_idx, issue_slots[3].in_uop.bits.stq_idx \n connect slots_3.io.in_uop.bits.ldq_idx, issue_slots[3].in_uop.bits.ldq_idx \n connect slots_3.io.in_uop.bits.rob_idx, issue_slots[3].in_uop.bits.rob_idx \n connect slots_3.io.in_uop.bits.fp_ctrl.vec, issue_slots[3].in_uop.bits.fp_ctrl.vec \n connect slots_3.io.in_uop.bits.fp_ctrl.wflags, issue_slots[3].in_uop.bits.fp_ctrl.wflags \n connect slots_3.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[3].in_uop.bits.fp_ctrl.sqrt \n connect slots_3.io.in_uop.bits.fp_ctrl.div, issue_slots[3].in_uop.bits.fp_ctrl.div \n connect slots_3.io.in_uop.bits.fp_ctrl.fma, issue_slots[3].in_uop.bits.fp_ctrl.fma \n connect slots_3.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[3].in_uop.bits.fp_ctrl.fastpipe \n connect slots_3.io.in_uop.bits.fp_ctrl.toint, issue_slots[3].in_uop.bits.fp_ctrl.toint \n connect slots_3.io.in_uop.bits.fp_ctrl.fromint, issue_slots[3].in_uop.bits.fp_ctrl.fromint \n connect slots_3.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[3].in_uop.bits.fp_ctrl.typeTagOut \n connect slots_3.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[3].in_uop.bits.fp_ctrl.typeTagIn \n connect slots_3.io.in_uop.bits.fp_ctrl.swap23, issue_slots[3].in_uop.bits.fp_ctrl.swap23 \n connect slots_3.io.in_uop.bits.fp_ctrl.swap12, issue_slots[3].in_uop.bits.fp_ctrl.swap12 \n connect slots_3.io.in_uop.bits.fp_ctrl.ren3, issue_slots[3].in_uop.bits.fp_ctrl.ren3 \n connect slots_3.io.in_uop.bits.fp_ctrl.ren2, issue_slots[3].in_uop.bits.fp_ctrl.ren2 \n connect slots_3.io.in_uop.bits.fp_ctrl.ren1, issue_slots[3].in_uop.bits.fp_ctrl.ren1 \n connect slots_3.io.in_uop.bits.fp_ctrl.wen, issue_slots[3].in_uop.bits.fp_ctrl.wen \n connect slots_3.io.in_uop.bits.fp_ctrl.ldst, issue_slots[3].in_uop.bits.fp_ctrl.ldst \n connect slots_3.io.in_uop.bits.op2_sel, issue_slots[3].in_uop.bits.op2_sel \n connect slots_3.io.in_uop.bits.op1_sel, issue_slots[3].in_uop.bits.op1_sel \n connect slots_3.io.in_uop.bits.imm_packed, issue_slots[3].in_uop.bits.imm_packed \n connect slots_3.io.in_uop.bits.pimm, issue_slots[3].in_uop.bits.pimm \n connect slots_3.io.in_uop.bits.imm_sel, issue_slots[3].in_uop.bits.imm_sel \n connect slots_3.io.in_uop.bits.imm_rename, issue_slots[3].in_uop.bits.imm_rename \n connect slots_3.io.in_uop.bits.taken, issue_slots[3].in_uop.bits.taken \n connect slots_3.io.in_uop.bits.pc_lob, issue_slots[3].in_uop.bits.pc_lob \n connect slots_3.io.in_uop.bits.edge_inst, issue_slots[3].in_uop.bits.edge_inst \n connect slots_3.io.in_uop.bits.ftq_idx, issue_slots[3].in_uop.bits.ftq_idx \n connect slots_3.io.in_uop.bits.is_mov, issue_slots[3].in_uop.bits.is_mov \n connect slots_3.io.in_uop.bits.is_rocc, issue_slots[3].in_uop.bits.is_rocc \n connect slots_3.io.in_uop.bits.is_sys_pc2epc, issue_slots[3].in_uop.bits.is_sys_pc2epc \n connect slots_3.io.in_uop.bits.is_eret, issue_slots[3].in_uop.bits.is_eret \n connect slots_3.io.in_uop.bits.is_amo, issue_slots[3].in_uop.bits.is_amo \n connect slots_3.io.in_uop.bits.is_sfence, issue_slots[3].in_uop.bits.is_sfence \n connect slots_3.io.in_uop.bits.is_fencei, issue_slots[3].in_uop.bits.is_fencei \n connect slots_3.io.in_uop.bits.is_fence, issue_slots[3].in_uop.bits.is_fence \n connect slots_3.io.in_uop.bits.is_sfb, issue_slots[3].in_uop.bits.is_sfb \n connect slots_3.io.in_uop.bits.br_type, issue_slots[3].in_uop.bits.br_type \n connect slots_3.io.in_uop.bits.br_tag, issue_slots[3].in_uop.bits.br_tag \n connect slots_3.io.in_uop.bits.br_mask, issue_slots[3].in_uop.bits.br_mask \n connect slots_3.io.in_uop.bits.dis_col_sel, issue_slots[3].in_uop.bits.dis_col_sel \n connect slots_3.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[3].in_uop.bits.iw_p3_bypass_hint \n connect slots_3.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[3].in_uop.bits.iw_p2_bypass_hint \n connect slots_3.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[3].in_uop.bits.iw_p1_bypass_hint \n connect slots_3.io.in_uop.bits.iw_p2_speculative_child, issue_slots[3].in_uop.bits.iw_p2_speculative_child \n connect slots_3.io.in_uop.bits.iw_p1_speculative_child, issue_slots[3].in_uop.bits.iw_p1_speculative_child \n connect slots_3.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[3].in_uop.bits.iw_issued_partial_dgen \n connect slots_3.io.in_uop.bits.iw_issued_partial_agen, issue_slots[3].in_uop.bits.iw_issued_partial_agen \n connect slots_3.io.in_uop.bits.iw_issued, issue_slots[3].in_uop.bits.iw_issued \n connect slots_3.io.in_uop.bits.fu_code[0], issue_slots[3].in_uop.bits.fu_code[0] \n connect slots_3.io.in_uop.bits.fu_code[1], issue_slots[3].in_uop.bits.fu_code[1] \n connect slots_3.io.in_uop.bits.fu_code[2], issue_slots[3].in_uop.bits.fu_code[2] \n connect slots_3.io.in_uop.bits.fu_code[3], issue_slots[3].in_uop.bits.fu_code[3] \n connect slots_3.io.in_uop.bits.fu_code[4], issue_slots[3].in_uop.bits.fu_code[4] \n connect slots_3.io.in_uop.bits.fu_code[5], issue_slots[3].in_uop.bits.fu_code[5] \n connect slots_3.io.in_uop.bits.fu_code[6], issue_slots[3].in_uop.bits.fu_code[6] \n connect slots_3.io.in_uop.bits.fu_code[7], issue_slots[3].in_uop.bits.fu_code[7] \n connect slots_3.io.in_uop.bits.fu_code[8], issue_slots[3].in_uop.bits.fu_code[8] \n connect slots_3.io.in_uop.bits.fu_code[9], issue_slots[3].in_uop.bits.fu_code[9] \n connect slots_3.io.in_uop.bits.iq_type[0], issue_slots[3].in_uop.bits.iq_type[0] \n connect slots_3.io.in_uop.bits.iq_type[1], issue_slots[3].in_uop.bits.iq_type[1] \n connect slots_3.io.in_uop.bits.iq_type[2], issue_slots[3].in_uop.bits.iq_type[2] \n connect slots_3.io.in_uop.bits.iq_type[3], issue_slots[3].in_uop.bits.iq_type[3] \n connect slots_3.io.in_uop.bits.debug_pc, issue_slots[3].in_uop.bits.debug_pc \n connect slots_3.io.in_uop.bits.is_rvc, issue_slots[3].in_uop.bits.is_rvc \n connect slots_3.io.in_uop.bits.debug_inst, issue_slots[3].in_uop.bits.debug_inst \n connect slots_3.io.in_uop.bits.inst, issue_slots[3].in_uop.bits.inst \n connect slots_3.io.in_uop.valid, issue_slots[3].in_uop.valid \n connect issue_slots[3].iss_uop.debug_tsrc, slots_3.io.iss_uop.debug_tsrc \n connect issue_slots[3].iss_uop.debug_fsrc, slots_3.io.iss_uop.debug_fsrc \n connect issue_slots[3].iss_uop.bp_xcpt_if, slots_3.io.iss_uop.bp_xcpt_if \n connect issue_slots[3].iss_uop.bp_debug_if, slots_3.io.iss_uop.bp_debug_if \n connect issue_slots[3].iss_uop.xcpt_ma_if, slots_3.io.iss_uop.xcpt_ma_if \n connect issue_slots[3].iss_uop.xcpt_ae_if, slots_3.io.iss_uop.xcpt_ae_if \n connect issue_slots[3].iss_uop.xcpt_pf_if, slots_3.io.iss_uop.xcpt_pf_if \n connect issue_slots[3].iss_uop.fp_typ, slots_3.io.iss_uop.fp_typ \n connect issue_slots[3].iss_uop.fp_rm, slots_3.io.iss_uop.fp_rm \n connect issue_slots[3].iss_uop.fp_val, slots_3.io.iss_uop.fp_val \n connect issue_slots[3].iss_uop.fcn_op, slots_3.io.iss_uop.fcn_op \n connect issue_slots[3].iss_uop.fcn_dw, slots_3.io.iss_uop.fcn_dw \n connect issue_slots[3].iss_uop.frs3_en, slots_3.io.iss_uop.frs3_en \n connect issue_slots[3].iss_uop.lrs2_rtype, slots_3.io.iss_uop.lrs2_rtype \n connect issue_slots[3].iss_uop.lrs1_rtype, slots_3.io.iss_uop.lrs1_rtype \n connect issue_slots[3].iss_uop.dst_rtype, slots_3.io.iss_uop.dst_rtype \n connect issue_slots[3].iss_uop.lrs3, slots_3.io.iss_uop.lrs3 \n connect issue_slots[3].iss_uop.lrs2, slots_3.io.iss_uop.lrs2 \n connect issue_slots[3].iss_uop.lrs1, slots_3.io.iss_uop.lrs1 \n connect issue_slots[3].iss_uop.ldst, slots_3.io.iss_uop.ldst \n connect issue_slots[3].iss_uop.ldst_is_rs1, slots_3.io.iss_uop.ldst_is_rs1 \n connect issue_slots[3].iss_uop.csr_cmd, slots_3.io.iss_uop.csr_cmd \n connect issue_slots[3].iss_uop.flush_on_commit, slots_3.io.iss_uop.flush_on_commit \n connect issue_slots[3].iss_uop.is_unique, slots_3.io.iss_uop.is_unique \n connect issue_slots[3].iss_uop.uses_stq, slots_3.io.iss_uop.uses_stq \n connect issue_slots[3].iss_uop.uses_ldq, slots_3.io.iss_uop.uses_ldq \n connect issue_slots[3].iss_uop.mem_signed, slots_3.io.iss_uop.mem_signed \n connect issue_slots[3].iss_uop.mem_size, slots_3.io.iss_uop.mem_size \n connect issue_slots[3].iss_uop.mem_cmd, slots_3.io.iss_uop.mem_cmd \n connect issue_slots[3].iss_uop.exc_cause, slots_3.io.iss_uop.exc_cause \n connect issue_slots[3].iss_uop.exception, slots_3.io.iss_uop.exception \n connect issue_slots[3].iss_uop.stale_pdst, slots_3.io.iss_uop.stale_pdst \n connect issue_slots[3].iss_uop.ppred_busy, slots_3.io.iss_uop.ppred_busy \n connect issue_slots[3].iss_uop.prs3_busy, slots_3.io.iss_uop.prs3_busy \n connect issue_slots[3].iss_uop.prs2_busy, slots_3.io.iss_uop.prs2_busy \n connect issue_slots[3].iss_uop.prs1_busy, slots_3.io.iss_uop.prs1_busy \n connect issue_slots[3].iss_uop.ppred, slots_3.io.iss_uop.ppred \n connect issue_slots[3].iss_uop.prs3, slots_3.io.iss_uop.prs3 \n connect issue_slots[3].iss_uop.prs2, slots_3.io.iss_uop.prs2 \n connect issue_slots[3].iss_uop.prs1, slots_3.io.iss_uop.prs1 \n connect issue_slots[3].iss_uop.pdst, slots_3.io.iss_uop.pdst \n connect issue_slots[3].iss_uop.rxq_idx, slots_3.io.iss_uop.rxq_idx \n connect issue_slots[3].iss_uop.stq_idx, slots_3.io.iss_uop.stq_idx \n connect issue_slots[3].iss_uop.ldq_idx, slots_3.io.iss_uop.ldq_idx \n connect issue_slots[3].iss_uop.rob_idx, slots_3.io.iss_uop.rob_idx \n connect issue_slots[3].iss_uop.fp_ctrl.vec, slots_3.io.iss_uop.fp_ctrl.vec \n connect issue_slots[3].iss_uop.fp_ctrl.wflags, slots_3.io.iss_uop.fp_ctrl.wflags \n connect issue_slots[3].iss_uop.fp_ctrl.sqrt, slots_3.io.iss_uop.fp_ctrl.sqrt \n connect issue_slots[3].iss_uop.fp_ctrl.div, slots_3.io.iss_uop.fp_ctrl.div \n connect issue_slots[3].iss_uop.fp_ctrl.fma, slots_3.io.iss_uop.fp_ctrl.fma \n connect issue_slots[3].iss_uop.fp_ctrl.fastpipe, slots_3.io.iss_uop.fp_ctrl.fastpipe \n connect issue_slots[3].iss_uop.fp_ctrl.toint, slots_3.io.iss_uop.fp_ctrl.toint \n connect issue_slots[3].iss_uop.fp_ctrl.fromint, slots_3.io.iss_uop.fp_ctrl.fromint \n connect issue_slots[3].iss_uop.fp_ctrl.typeTagOut, slots_3.io.iss_uop.fp_ctrl.typeTagOut \n connect issue_slots[3].iss_uop.fp_ctrl.typeTagIn, slots_3.io.iss_uop.fp_ctrl.typeTagIn \n connect issue_slots[3].iss_uop.fp_ctrl.swap23, slots_3.io.iss_uop.fp_ctrl.swap23 \n connect issue_slots[3].iss_uop.fp_ctrl.swap12, slots_3.io.iss_uop.fp_ctrl.swap12 \n connect issue_slots[3].iss_uop.fp_ctrl.ren3, slots_3.io.iss_uop.fp_ctrl.ren3 \n connect issue_slots[3].iss_uop.fp_ctrl.ren2, slots_3.io.iss_uop.fp_ctrl.ren2 \n connect issue_slots[3].iss_uop.fp_ctrl.ren1, slots_3.io.iss_uop.fp_ctrl.ren1 \n connect issue_slots[3].iss_uop.fp_ctrl.wen, slots_3.io.iss_uop.fp_ctrl.wen \n connect issue_slots[3].iss_uop.fp_ctrl.ldst, slots_3.io.iss_uop.fp_ctrl.ldst \n connect issue_slots[3].iss_uop.op2_sel, slots_3.io.iss_uop.op2_sel \n connect issue_slots[3].iss_uop.op1_sel, slots_3.io.iss_uop.op1_sel \n connect issue_slots[3].iss_uop.imm_packed, slots_3.io.iss_uop.imm_packed \n connect issue_slots[3].iss_uop.pimm, slots_3.io.iss_uop.pimm \n connect issue_slots[3].iss_uop.imm_sel, slots_3.io.iss_uop.imm_sel \n connect issue_slots[3].iss_uop.imm_rename, slots_3.io.iss_uop.imm_rename \n connect issue_slots[3].iss_uop.taken, slots_3.io.iss_uop.taken \n connect issue_slots[3].iss_uop.pc_lob, slots_3.io.iss_uop.pc_lob \n connect issue_slots[3].iss_uop.edge_inst, slots_3.io.iss_uop.edge_inst \n connect issue_slots[3].iss_uop.ftq_idx, slots_3.io.iss_uop.ftq_idx \n connect issue_slots[3].iss_uop.is_mov, slots_3.io.iss_uop.is_mov \n connect issue_slots[3].iss_uop.is_rocc, slots_3.io.iss_uop.is_rocc \n connect issue_slots[3].iss_uop.is_sys_pc2epc, slots_3.io.iss_uop.is_sys_pc2epc \n connect issue_slots[3].iss_uop.is_eret, slots_3.io.iss_uop.is_eret \n connect issue_slots[3].iss_uop.is_amo, slots_3.io.iss_uop.is_amo \n connect issue_slots[3].iss_uop.is_sfence, slots_3.io.iss_uop.is_sfence \n connect issue_slots[3].iss_uop.is_fencei, slots_3.io.iss_uop.is_fencei \n connect issue_slots[3].iss_uop.is_fence, slots_3.io.iss_uop.is_fence \n connect issue_slots[3].iss_uop.is_sfb, slots_3.io.iss_uop.is_sfb \n connect issue_slots[3].iss_uop.br_type, slots_3.io.iss_uop.br_type \n connect issue_slots[3].iss_uop.br_tag, slots_3.io.iss_uop.br_tag \n connect issue_slots[3].iss_uop.br_mask, slots_3.io.iss_uop.br_mask \n connect issue_slots[3].iss_uop.dis_col_sel, slots_3.io.iss_uop.dis_col_sel \n connect issue_slots[3].iss_uop.iw_p3_bypass_hint, slots_3.io.iss_uop.iw_p3_bypass_hint \n connect issue_slots[3].iss_uop.iw_p2_bypass_hint, slots_3.io.iss_uop.iw_p2_bypass_hint \n connect issue_slots[3].iss_uop.iw_p1_bypass_hint, slots_3.io.iss_uop.iw_p1_bypass_hint \n connect issue_slots[3].iss_uop.iw_p2_speculative_child, slots_3.io.iss_uop.iw_p2_speculative_child \n connect issue_slots[3].iss_uop.iw_p1_speculative_child, slots_3.io.iss_uop.iw_p1_speculative_child \n connect issue_slots[3].iss_uop.iw_issued_partial_dgen, slots_3.io.iss_uop.iw_issued_partial_dgen \n connect issue_slots[3].iss_uop.iw_issued_partial_agen, slots_3.io.iss_uop.iw_issued_partial_agen \n connect issue_slots[3].iss_uop.iw_issued, slots_3.io.iss_uop.iw_issued \n connect issue_slots[3].iss_uop.fu_code[0], slots_3.io.iss_uop.fu_code[0] \n connect issue_slots[3].iss_uop.fu_code[1], slots_3.io.iss_uop.fu_code[1] \n connect issue_slots[3].iss_uop.fu_code[2], slots_3.io.iss_uop.fu_code[2] \n connect issue_slots[3].iss_uop.fu_code[3], slots_3.io.iss_uop.fu_code[3] \n connect issue_slots[3].iss_uop.fu_code[4], slots_3.io.iss_uop.fu_code[4] \n connect issue_slots[3].iss_uop.fu_code[5], slots_3.io.iss_uop.fu_code[5] \n connect issue_slots[3].iss_uop.fu_code[6], slots_3.io.iss_uop.fu_code[6] \n connect issue_slots[3].iss_uop.fu_code[7], slots_3.io.iss_uop.fu_code[7] \n connect issue_slots[3].iss_uop.fu_code[8], slots_3.io.iss_uop.fu_code[8] \n connect issue_slots[3].iss_uop.fu_code[9], slots_3.io.iss_uop.fu_code[9] \n connect issue_slots[3].iss_uop.iq_type[0], slots_3.io.iss_uop.iq_type[0] \n connect issue_slots[3].iss_uop.iq_type[1], slots_3.io.iss_uop.iq_type[1] \n connect issue_slots[3].iss_uop.iq_type[2], slots_3.io.iss_uop.iq_type[2] \n connect issue_slots[3].iss_uop.iq_type[3], slots_3.io.iss_uop.iq_type[3] \n connect issue_slots[3].iss_uop.debug_pc, slots_3.io.iss_uop.debug_pc \n connect issue_slots[3].iss_uop.is_rvc, slots_3.io.iss_uop.is_rvc \n connect issue_slots[3].iss_uop.debug_inst, slots_3.io.iss_uop.debug_inst \n connect issue_slots[3].iss_uop.inst, slots_3.io.iss_uop.inst \n connect slots_3.io.grant, issue_slots[3].grant \n connect issue_slots[3].request, slots_3.io.request \n connect issue_slots[3].will_be_valid, slots_3.io.will_be_valid \n connect issue_slots[3].valid, slots_3.io.valid \n connect slots_4.io.child_rebusys, issue_slots[4].child_rebusys \n connect slots_4.io.pred_wakeup_port.bits, issue_slots[4].pred_wakeup_port.bits \n connect slots_4.io.pred_wakeup_port.valid, issue_slots[4].pred_wakeup_port.valid \n connect slots_4.io.wakeup_ports[0].bits.rebusy, issue_slots[4].wakeup_ports[0].bits.rebusy \n connect slots_4.io.wakeup_ports[0].bits.speculative_mask, issue_slots[4].wakeup_ports[0].bits.speculative_mask \n connect slots_4.io.wakeup_ports[0].bits.bypassable, issue_slots[4].wakeup_ports[0].bits.bypassable \n connect slots_4.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[4].wakeup_ports[0].bits.uop.debug_tsrc \n connect slots_4.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[4].wakeup_ports[0].bits.uop.debug_fsrc \n connect slots_4.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[4].wakeup_ports[0].bits.uop.bp_xcpt_if \n connect slots_4.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[4].wakeup_ports[0].bits.uop.bp_debug_if \n connect slots_4.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[4].wakeup_ports[0].bits.uop.xcpt_ma_if \n connect slots_4.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[4].wakeup_ports[0].bits.uop.xcpt_ae_if \n connect slots_4.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[4].wakeup_ports[0].bits.uop.xcpt_pf_if \n connect slots_4.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[4].wakeup_ports[0].bits.uop.fp_typ \n connect slots_4.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[4].wakeup_ports[0].bits.uop.fp_rm \n connect slots_4.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[4].wakeup_ports[0].bits.uop.fp_val \n connect slots_4.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[4].wakeup_ports[0].bits.uop.fcn_op \n connect slots_4.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[4].wakeup_ports[0].bits.uop.fcn_dw \n connect slots_4.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[4].wakeup_ports[0].bits.uop.frs3_en \n connect slots_4.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[4].wakeup_ports[0].bits.uop.lrs2_rtype \n connect slots_4.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[4].wakeup_ports[0].bits.uop.lrs1_rtype \n connect slots_4.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[4].wakeup_ports[0].bits.uop.dst_rtype \n connect slots_4.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[4].wakeup_ports[0].bits.uop.lrs3 \n connect slots_4.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[4].wakeup_ports[0].bits.uop.lrs2 \n connect slots_4.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[4].wakeup_ports[0].bits.uop.lrs1 \n connect slots_4.io.wakeup_ports[0].bits.uop.ldst, issue_slots[4].wakeup_ports[0].bits.uop.ldst \n connect slots_4.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[4].wakeup_ports[0].bits.uop.ldst_is_rs1 \n connect slots_4.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[4].wakeup_ports[0].bits.uop.csr_cmd \n connect slots_4.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[4].wakeup_ports[0].bits.uop.flush_on_commit \n connect slots_4.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[4].wakeup_ports[0].bits.uop.is_unique \n connect slots_4.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[4].wakeup_ports[0].bits.uop.uses_stq \n connect slots_4.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[4].wakeup_ports[0].bits.uop.uses_ldq \n connect slots_4.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[4].wakeup_ports[0].bits.uop.mem_signed \n connect slots_4.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[4].wakeup_ports[0].bits.uop.mem_size \n connect slots_4.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[4].wakeup_ports[0].bits.uop.mem_cmd \n connect slots_4.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[4].wakeup_ports[0].bits.uop.exc_cause \n connect slots_4.io.wakeup_ports[0].bits.uop.exception, issue_slots[4].wakeup_ports[0].bits.uop.exception \n connect slots_4.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[4].wakeup_ports[0].bits.uop.stale_pdst \n connect slots_4.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[4].wakeup_ports[0].bits.uop.ppred_busy \n connect slots_4.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[4].wakeup_ports[0].bits.uop.prs3_busy \n connect slots_4.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[4].wakeup_ports[0].bits.uop.prs2_busy \n connect slots_4.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[4].wakeup_ports[0].bits.uop.prs1_busy \n connect slots_4.io.wakeup_ports[0].bits.uop.ppred, issue_slots[4].wakeup_ports[0].bits.uop.ppred \n connect slots_4.io.wakeup_ports[0].bits.uop.prs3, issue_slots[4].wakeup_ports[0].bits.uop.prs3 \n connect slots_4.io.wakeup_ports[0].bits.uop.prs2, issue_slots[4].wakeup_ports[0].bits.uop.prs2 \n connect slots_4.io.wakeup_ports[0].bits.uop.prs1, issue_slots[4].wakeup_ports[0].bits.uop.prs1 \n connect slots_4.io.wakeup_ports[0].bits.uop.pdst, issue_slots[4].wakeup_ports[0].bits.uop.pdst \n connect slots_4.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[4].wakeup_ports[0].bits.uop.rxq_idx \n connect slots_4.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[4].wakeup_ports[0].bits.uop.stq_idx \n connect slots_4.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[4].wakeup_ports[0].bits.uop.ldq_idx \n connect slots_4.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[4].wakeup_ports[0].bits.uop.rob_idx \n connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.vec \n connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.wflags \n connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.sqrt \n connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.div \n connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.fma \n connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe \n connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.toint \n connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.fromint \n connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut \n connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn \n connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.swap23 \n connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.swap12 \n connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.ren3 \n connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.ren2 \n connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.ren1 \n connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.wen \n connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.ldst \n connect slots_4.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[4].wakeup_ports[0].bits.uop.op2_sel \n connect slots_4.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[4].wakeup_ports[0].bits.uop.op1_sel \n connect slots_4.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[4].wakeup_ports[0].bits.uop.imm_packed \n connect slots_4.io.wakeup_ports[0].bits.uop.pimm, issue_slots[4].wakeup_ports[0].bits.uop.pimm \n connect slots_4.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[4].wakeup_ports[0].bits.uop.imm_sel \n connect slots_4.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[4].wakeup_ports[0].bits.uop.imm_rename \n connect slots_4.io.wakeup_ports[0].bits.uop.taken, issue_slots[4].wakeup_ports[0].bits.uop.taken \n connect slots_4.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[4].wakeup_ports[0].bits.uop.pc_lob \n connect slots_4.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[4].wakeup_ports[0].bits.uop.edge_inst \n connect slots_4.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[4].wakeup_ports[0].bits.uop.ftq_idx \n connect slots_4.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[4].wakeup_ports[0].bits.uop.is_mov \n connect slots_4.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[4].wakeup_ports[0].bits.uop.is_rocc \n connect slots_4.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[4].wakeup_ports[0].bits.uop.is_sys_pc2epc \n connect slots_4.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[4].wakeup_ports[0].bits.uop.is_eret \n connect slots_4.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[4].wakeup_ports[0].bits.uop.is_amo \n connect slots_4.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[4].wakeup_ports[0].bits.uop.is_sfence \n connect slots_4.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[4].wakeup_ports[0].bits.uop.is_fencei \n connect slots_4.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[4].wakeup_ports[0].bits.uop.is_fence \n connect slots_4.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[4].wakeup_ports[0].bits.uop.is_sfb \n connect slots_4.io.wakeup_ports[0].bits.uop.br_type, issue_slots[4].wakeup_ports[0].bits.uop.br_type \n connect slots_4.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[4].wakeup_ports[0].bits.uop.br_tag \n connect slots_4.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[4].wakeup_ports[0].bits.uop.br_mask \n connect slots_4.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[4].wakeup_ports[0].bits.uop.dis_col_sel \n connect slots_4.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[4].wakeup_ports[0].bits.uop.iw_p3_bypass_hint \n connect slots_4.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[4].wakeup_ports[0].bits.uop.iw_p2_bypass_hint \n connect slots_4.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[4].wakeup_ports[0].bits.uop.iw_p1_bypass_hint \n connect slots_4.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[4].wakeup_ports[0].bits.uop.iw_p2_speculative_child \n connect slots_4.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[4].wakeup_ports[0].bits.uop.iw_p1_speculative_child \n connect slots_4.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[4].wakeup_ports[0].bits.uop.iw_issued_partial_dgen \n connect slots_4.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[4].wakeup_ports[0].bits.uop.iw_issued_partial_agen \n connect slots_4.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[4].wakeup_ports[0].bits.uop.iw_issued \n connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[0] \n connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[1] \n connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[2] \n connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[3] \n connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[4] \n connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[5] \n connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[6] \n connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[7] \n connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[8] \n connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[9] \n connect slots_4.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[4].wakeup_ports[0].bits.uop.iq_type[0] \n connect slots_4.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[4].wakeup_ports[0].bits.uop.iq_type[1] \n connect slots_4.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[4].wakeup_ports[0].bits.uop.iq_type[2] \n connect slots_4.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[4].wakeup_ports[0].bits.uop.iq_type[3] \n connect slots_4.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[4].wakeup_ports[0].bits.uop.debug_pc \n connect slots_4.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[4].wakeup_ports[0].bits.uop.is_rvc \n connect slots_4.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[4].wakeup_ports[0].bits.uop.debug_inst \n connect slots_4.io.wakeup_ports[0].bits.uop.inst, issue_slots[4].wakeup_ports[0].bits.uop.inst \n connect slots_4.io.wakeup_ports[0].valid, issue_slots[4].wakeup_ports[0].valid \n connect slots_4.io.wakeup_ports[1].bits.rebusy, issue_slots[4].wakeup_ports[1].bits.rebusy \n connect slots_4.io.wakeup_ports[1].bits.speculative_mask, issue_slots[4].wakeup_ports[1].bits.speculative_mask \n connect slots_4.io.wakeup_ports[1].bits.bypassable, issue_slots[4].wakeup_ports[1].bits.bypassable \n connect slots_4.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[4].wakeup_ports[1].bits.uop.debug_tsrc \n connect slots_4.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[4].wakeup_ports[1].bits.uop.debug_fsrc \n connect slots_4.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[4].wakeup_ports[1].bits.uop.bp_xcpt_if \n connect slots_4.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[4].wakeup_ports[1].bits.uop.bp_debug_if \n connect slots_4.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[4].wakeup_ports[1].bits.uop.xcpt_ma_if \n connect slots_4.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[4].wakeup_ports[1].bits.uop.xcpt_ae_if \n connect slots_4.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[4].wakeup_ports[1].bits.uop.xcpt_pf_if \n connect slots_4.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[4].wakeup_ports[1].bits.uop.fp_typ \n connect slots_4.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[4].wakeup_ports[1].bits.uop.fp_rm \n connect slots_4.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[4].wakeup_ports[1].bits.uop.fp_val \n connect slots_4.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[4].wakeup_ports[1].bits.uop.fcn_op \n connect slots_4.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[4].wakeup_ports[1].bits.uop.fcn_dw \n connect slots_4.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[4].wakeup_ports[1].bits.uop.frs3_en \n connect slots_4.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[4].wakeup_ports[1].bits.uop.lrs2_rtype \n connect slots_4.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[4].wakeup_ports[1].bits.uop.lrs1_rtype \n connect slots_4.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[4].wakeup_ports[1].bits.uop.dst_rtype \n connect slots_4.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[4].wakeup_ports[1].bits.uop.lrs3 \n connect slots_4.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[4].wakeup_ports[1].bits.uop.lrs2 \n connect slots_4.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[4].wakeup_ports[1].bits.uop.lrs1 \n connect slots_4.io.wakeup_ports[1].bits.uop.ldst, issue_slots[4].wakeup_ports[1].bits.uop.ldst \n connect slots_4.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[4].wakeup_ports[1].bits.uop.ldst_is_rs1 \n connect slots_4.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[4].wakeup_ports[1].bits.uop.csr_cmd \n connect slots_4.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[4].wakeup_ports[1].bits.uop.flush_on_commit \n connect slots_4.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[4].wakeup_ports[1].bits.uop.is_unique \n connect slots_4.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[4].wakeup_ports[1].bits.uop.uses_stq \n connect slots_4.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[4].wakeup_ports[1].bits.uop.uses_ldq \n connect slots_4.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[4].wakeup_ports[1].bits.uop.mem_signed \n connect slots_4.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[4].wakeup_ports[1].bits.uop.mem_size \n connect slots_4.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[4].wakeup_ports[1].bits.uop.mem_cmd \n connect slots_4.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[4].wakeup_ports[1].bits.uop.exc_cause \n connect slots_4.io.wakeup_ports[1].bits.uop.exception, issue_slots[4].wakeup_ports[1].bits.uop.exception \n connect slots_4.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[4].wakeup_ports[1].bits.uop.stale_pdst \n connect slots_4.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[4].wakeup_ports[1].bits.uop.ppred_busy \n connect slots_4.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[4].wakeup_ports[1].bits.uop.prs3_busy \n connect slots_4.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[4].wakeup_ports[1].bits.uop.prs2_busy \n connect slots_4.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[4].wakeup_ports[1].bits.uop.prs1_busy \n connect slots_4.io.wakeup_ports[1].bits.uop.ppred, issue_slots[4].wakeup_ports[1].bits.uop.ppred \n connect slots_4.io.wakeup_ports[1].bits.uop.prs3, issue_slots[4].wakeup_ports[1].bits.uop.prs3 \n connect slots_4.io.wakeup_ports[1].bits.uop.prs2, issue_slots[4].wakeup_ports[1].bits.uop.prs2 \n connect slots_4.io.wakeup_ports[1].bits.uop.prs1, issue_slots[4].wakeup_ports[1].bits.uop.prs1 \n connect slots_4.io.wakeup_ports[1].bits.uop.pdst, issue_slots[4].wakeup_ports[1].bits.uop.pdst \n connect slots_4.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[4].wakeup_ports[1].bits.uop.rxq_idx \n connect slots_4.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[4].wakeup_ports[1].bits.uop.stq_idx \n connect slots_4.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[4].wakeup_ports[1].bits.uop.ldq_idx \n connect slots_4.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[4].wakeup_ports[1].bits.uop.rob_idx \n connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.vec \n connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.wflags \n connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.sqrt \n connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.div \n connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.fma \n connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe \n connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.toint \n connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.fromint \n connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut \n connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn \n connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.swap23 \n connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.swap12 \n connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.ren3 \n connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.ren2 \n connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.ren1 \n connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.wen \n connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.ldst \n connect slots_4.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[4].wakeup_ports[1].bits.uop.op2_sel \n connect slots_4.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[4].wakeup_ports[1].bits.uop.op1_sel \n connect slots_4.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[4].wakeup_ports[1].bits.uop.imm_packed \n connect slots_4.io.wakeup_ports[1].bits.uop.pimm, issue_slots[4].wakeup_ports[1].bits.uop.pimm \n connect slots_4.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[4].wakeup_ports[1].bits.uop.imm_sel \n connect slots_4.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[4].wakeup_ports[1].bits.uop.imm_rename \n connect slots_4.io.wakeup_ports[1].bits.uop.taken, issue_slots[4].wakeup_ports[1].bits.uop.taken \n connect slots_4.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[4].wakeup_ports[1].bits.uop.pc_lob \n connect slots_4.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[4].wakeup_ports[1].bits.uop.edge_inst \n connect slots_4.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[4].wakeup_ports[1].bits.uop.ftq_idx \n connect slots_4.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[4].wakeup_ports[1].bits.uop.is_mov \n connect slots_4.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[4].wakeup_ports[1].bits.uop.is_rocc \n connect slots_4.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[4].wakeup_ports[1].bits.uop.is_sys_pc2epc \n connect slots_4.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[4].wakeup_ports[1].bits.uop.is_eret \n connect slots_4.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[4].wakeup_ports[1].bits.uop.is_amo \n connect slots_4.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[4].wakeup_ports[1].bits.uop.is_sfence \n connect slots_4.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[4].wakeup_ports[1].bits.uop.is_fencei \n connect slots_4.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[4].wakeup_ports[1].bits.uop.is_fence \n connect slots_4.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[4].wakeup_ports[1].bits.uop.is_sfb \n connect slots_4.io.wakeup_ports[1].bits.uop.br_type, issue_slots[4].wakeup_ports[1].bits.uop.br_type \n connect slots_4.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[4].wakeup_ports[1].bits.uop.br_tag \n connect slots_4.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[4].wakeup_ports[1].bits.uop.br_mask \n connect slots_4.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[4].wakeup_ports[1].bits.uop.dis_col_sel \n connect slots_4.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[4].wakeup_ports[1].bits.uop.iw_p3_bypass_hint \n connect slots_4.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[4].wakeup_ports[1].bits.uop.iw_p2_bypass_hint \n connect slots_4.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[4].wakeup_ports[1].bits.uop.iw_p1_bypass_hint \n connect slots_4.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[4].wakeup_ports[1].bits.uop.iw_p2_speculative_child \n connect slots_4.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[4].wakeup_ports[1].bits.uop.iw_p1_speculative_child \n connect slots_4.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[4].wakeup_ports[1].bits.uop.iw_issued_partial_dgen \n connect slots_4.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[4].wakeup_ports[1].bits.uop.iw_issued_partial_agen \n connect slots_4.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[4].wakeup_ports[1].bits.uop.iw_issued \n connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[0] \n connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[1] \n connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[2] \n connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[3] \n connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[4] \n connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[5] \n connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[6] \n connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[7] \n connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[8] \n connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[9] \n connect slots_4.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[4].wakeup_ports[1].bits.uop.iq_type[0] \n connect slots_4.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[4].wakeup_ports[1].bits.uop.iq_type[1] \n connect slots_4.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[4].wakeup_ports[1].bits.uop.iq_type[2] \n connect slots_4.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[4].wakeup_ports[1].bits.uop.iq_type[3] \n connect slots_4.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[4].wakeup_ports[1].bits.uop.debug_pc \n connect slots_4.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[4].wakeup_ports[1].bits.uop.is_rvc \n connect slots_4.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[4].wakeup_ports[1].bits.uop.debug_inst \n connect slots_4.io.wakeup_ports[1].bits.uop.inst, issue_slots[4].wakeup_ports[1].bits.uop.inst \n connect slots_4.io.wakeup_ports[1].valid, issue_slots[4].wakeup_ports[1].valid \n connect slots_4.io.wakeup_ports[2].bits.rebusy, issue_slots[4].wakeup_ports[2].bits.rebusy \n connect slots_4.io.wakeup_ports[2].bits.speculative_mask, issue_slots[4].wakeup_ports[2].bits.speculative_mask \n connect slots_4.io.wakeup_ports[2].bits.bypassable, issue_slots[4].wakeup_ports[2].bits.bypassable \n connect slots_4.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[4].wakeup_ports[2].bits.uop.debug_tsrc \n connect slots_4.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[4].wakeup_ports[2].bits.uop.debug_fsrc \n connect slots_4.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[4].wakeup_ports[2].bits.uop.bp_xcpt_if \n connect slots_4.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[4].wakeup_ports[2].bits.uop.bp_debug_if \n connect slots_4.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[4].wakeup_ports[2].bits.uop.xcpt_ma_if \n connect slots_4.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[4].wakeup_ports[2].bits.uop.xcpt_ae_if \n connect slots_4.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[4].wakeup_ports[2].bits.uop.xcpt_pf_if \n connect slots_4.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[4].wakeup_ports[2].bits.uop.fp_typ \n connect slots_4.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[4].wakeup_ports[2].bits.uop.fp_rm \n connect slots_4.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[4].wakeup_ports[2].bits.uop.fp_val \n connect slots_4.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[4].wakeup_ports[2].bits.uop.fcn_op \n connect slots_4.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[4].wakeup_ports[2].bits.uop.fcn_dw \n connect slots_4.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[4].wakeup_ports[2].bits.uop.frs3_en \n connect slots_4.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[4].wakeup_ports[2].bits.uop.lrs2_rtype \n connect slots_4.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[4].wakeup_ports[2].bits.uop.lrs1_rtype \n connect slots_4.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[4].wakeup_ports[2].bits.uop.dst_rtype \n connect slots_4.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[4].wakeup_ports[2].bits.uop.lrs3 \n connect slots_4.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[4].wakeup_ports[2].bits.uop.lrs2 \n connect slots_4.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[4].wakeup_ports[2].bits.uop.lrs1 \n connect slots_4.io.wakeup_ports[2].bits.uop.ldst, issue_slots[4].wakeup_ports[2].bits.uop.ldst \n connect slots_4.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[4].wakeup_ports[2].bits.uop.ldst_is_rs1 \n connect slots_4.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[4].wakeup_ports[2].bits.uop.csr_cmd \n connect slots_4.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[4].wakeup_ports[2].bits.uop.flush_on_commit \n connect slots_4.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[4].wakeup_ports[2].bits.uop.is_unique \n connect slots_4.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[4].wakeup_ports[2].bits.uop.uses_stq \n connect slots_4.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[4].wakeup_ports[2].bits.uop.uses_ldq \n connect slots_4.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[4].wakeup_ports[2].bits.uop.mem_signed \n connect slots_4.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[4].wakeup_ports[2].bits.uop.mem_size \n connect slots_4.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[4].wakeup_ports[2].bits.uop.mem_cmd \n connect slots_4.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[4].wakeup_ports[2].bits.uop.exc_cause \n connect slots_4.io.wakeup_ports[2].bits.uop.exception, issue_slots[4].wakeup_ports[2].bits.uop.exception \n connect slots_4.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[4].wakeup_ports[2].bits.uop.stale_pdst \n connect slots_4.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[4].wakeup_ports[2].bits.uop.ppred_busy \n connect slots_4.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[4].wakeup_ports[2].bits.uop.prs3_busy \n connect slots_4.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[4].wakeup_ports[2].bits.uop.prs2_busy \n connect slots_4.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[4].wakeup_ports[2].bits.uop.prs1_busy \n connect slots_4.io.wakeup_ports[2].bits.uop.ppred, issue_slots[4].wakeup_ports[2].bits.uop.ppred \n connect slots_4.io.wakeup_ports[2].bits.uop.prs3, issue_slots[4].wakeup_ports[2].bits.uop.prs3 \n connect slots_4.io.wakeup_ports[2].bits.uop.prs2, issue_slots[4].wakeup_ports[2].bits.uop.prs2 \n connect slots_4.io.wakeup_ports[2].bits.uop.prs1, issue_slots[4].wakeup_ports[2].bits.uop.prs1 \n connect slots_4.io.wakeup_ports[2].bits.uop.pdst, issue_slots[4].wakeup_ports[2].bits.uop.pdst \n connect slots_4.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[4].wakeup_ports[2].bits.uop.rxq_idx \n connect slots_4.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[4].wakeup_ports[2].bits.uop.stq_idx \n connect slots_4.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[4].wakeup_ports[2].bits.uop.ldq_idx \n connect slots_4.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[4].wakeup_ports[2].bits.uop.rob_idx \n connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.vec \n connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.wflags \n connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.sqrt \n connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.div \n connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.fma \n connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe \n connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.toint \n connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.fromint \n connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut \n connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn \n connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.swap23 \n connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.swap12 \n connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.ren3 \n connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.ren2 \n connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.ren1 \n connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.wen \n connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.ldst \n connect slots_4.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[4].wakeup_ports[2].bits.uop.op2_sel \n connect slots_4.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[4].wakeup_ports[2].bits.uop.op1_sel \n connect slots_4.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[4].wakeup_ports[2].bits.uop.imm_packed \n connect slots_4.io.wakeup_ports[2].bits.uop.pimm, issue_slots[4].wakeup_ports[2].bits.uop.pimm \n connect slots_4.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[4].wakeup_ports[2].bits.uop.imm_sel \n connect slots_4.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[4].wakeup_ports[2].bits.uop.imm_rename \n connect slots_4.io.wakeup_ports[2].bits.uop.taken, issue_slots[4].wakeup_ports[2].bits.uop.taken \n connect slots_4.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[4].wakeup_ports[2].bits.uop.pc_lob \n connect slots_4.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[4].wakeup_ports[2].bits.uop.edge_inst \n connect slots_4.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[4].wakeup_ports[2].bits.uop.ftq_idx \n connect slots_4.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[4].wakeup_ports[2].bits.uop.is_mov \n connect slots_4.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[4].wakeup_ports[2].bits.uop.is_rocc \n connect slots_4.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[4].wakeup_ports[2].bits.uop.is_sys_pc2epc \n connect slots_4.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[4].wakeup_ports[2].bits.uop.is_eret \n connect slots_4.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[4].wakeup_ports[2].bits.uop.is_amo \n connect slots_4.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[4].wakeup_ports[2].bits.uop.is_sfence \n connect slots_4.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[4].wakeup_ports[2].bits.uop.is_fencei \n connect slots_4.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[4].wakeup_ports[2].bits.uop.is_fence \n connect slots_4.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[4].wakeup_ports[2].bits.uop.is_sfb \n connect slots_4.io.wakeup_ports[2].bits.uop.br_type, issue_slots[4].wakeup_ports[2].bits.uop.br_type \n connect slots_4.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[4].wakeup_ports[2].bits.uop.br_tag \n connect slots_4.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[4].wakeup_ports[2].bits.uop.br_mask \n connect slots_4.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[4].wakeup_ports[2].bits.uop.dis_col_sel \n connect slots_4.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[4].wakeup_ports[2].bits.uop.iw_p3_bypass_hint \n connect slots_4.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[4].wakeup_ports[2].bits.uop.iw_p2_bypass_hint \n connect slots_4.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[4].wakeup_ports[2].bits.uop.iw_p1_bypass_hint \n connect slots_4.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[4].wakeup_ports[2].bits.uop.iw_p2_speculative_child \n connect slots_4.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[4].wakeup_ports[2].bits.uop.iw_p1_speculative_child \n connect slots_4.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[4].wakeup_ports[2].bits.uop.iw_issued_partial_dgen \n connect slots_4.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[4].wakeup_ports[2].bits.uop.iw_issued_partial_agen \n connect slots_4.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[4].wakeup_ports[2].bits.uop.iw_issued \n connect slots_4.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[4].wakeup_ports[2].bits.uop.fu_code[0] \n connect slots_4.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[4].wakeup_ports[2].bits.uop.fu_code[1] \n connect slots_4.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[4].wakeup_ports[2].bits.uop.fu_code[2] \n connect slots_4.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[4].wakeup_ports[2].bits.uop.fu_code[3] \n connect slots_4.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[4].wakeup_ports[2].bits.uop.fu_code[4] \n connect slots_4.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[4].wakeup_ports[2].bits.uop.fu_code[5] \n connect slots_4.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[4].wakeup_ports[2].bits.uop.fu_code[6] \n connect slots_4.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[4].wakeup_ports[2].bits.uop.fu_code[7] \n connect slots_4.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[4].wakeup_ports[2].bits.uop.fu_code[8] \n connect slots_4.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[4].wakeup_ports[2].bits.uop.fu_code[9] \n connect slots_4.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[4].wakeup_ports[2].bits.uop.iq_type[0] \n connect slots_4.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[4].wakeup_ports[2].bits.uop.iq_type[1] \n connect slots_4.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[4].wakeup_ports[2].bits.uop.iq_type[2] \n connect slots_4.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[4].wakeup_ports[2].bits.uop.iq_type[3] \n connect slots_4.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[4].wakeup_ports[2].bits.uop.debug_pc \n connect slots_4.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[4].wakeup_ports[2].bits.uop.is_rvc \n connect slots_4.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[4].wakeup_ports[2].bits.uop.debug_inst \n connect slots_4.io.wakeup_ports[2].bits.uop.inst, issue_slots[4].wakeup_ports[2].bits.uop.inst \n connect slots_4.io.wakeup_ports[2].valid, issue_slots[4].wakeup_ports[2].valid \n connect slots_4.io.wakeup_ports[3].bits.rebusy, issue_slots[4].wakeup_ports[3].bits.rebusy \n connect slots_4.io.wakeup_ports[3].bits.speculative_mask, issue_slots[4].wakeup_ports[3].bits.speculative_mask \n connect slots_4.io.wakeup_ports[3].bits.bypassable, issue_slots[4].wakeup_ports[3].bits.bypassable \n connect slots_4.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[4].wakeup_ports[3].bits.uop.debug_tsrc \n connect slots_4.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[4].wakeup_ports[3].bits.uop.debug_fsrc \n connect slots_4.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[4].wakeup_ports[3].bits.uop.bp_xcpt_if \n connect slots_4.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[4].wakeup_ports[3].bits.uop.bp_debug_if \n connect slots_4.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[4].wakeup_ports[3].bits.uop.xcpt_ma_if \n connect slots_4.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[4].wakeup_ports[3].bits.uop.xcpt_ae_if \n connect slots_4.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[4].wakeup_ports[3].bits.uop.xcpt_pf_if \n connect slots_4.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[4].wakeup_ports[3].bits.uop.fp_typ \n connect slots_4.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[4].wakeup_ports[3].bits.uop.fp_rm \n connect slots_4.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[4].wakeup_ports[3].bits.uop.fp_val \n connect slots_4.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[4].wakeup_ports[3].bits.uop.fcn_op \n connect slots_4.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[4].wakeup_ports[3].bits.uop.fcn_dw \n connect slots_4.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[4].wakeup_ports[3].bits.uop.frs3_en \n connect slots_4.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[4].wakeup_ports[3].bits.uop.lrs2_rtype \n connect slots_4.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[4].wakeup_ports[3].bits.uop.lrs1_rtype \n connect slots_4.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[4].wakeup_ports[3].bits.uop.dst_rtype \n connect slots_4.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[4].wakeup_ports[3].bits.uop.lrs3 \n connect slots_4.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[4].wakeup_ports[3].bits.uop.lrs2 \n connect slots_4.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[4].wakeup_ports[3].bits.uop.lrs1 \n connect slots_4.io.wakeup_ports[3].bits.uop.ldst, issue_slots[4].wakeup_ports[3].bits.uop.ldst \n connect slots_4.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[4].wakeup_ports[3].bits.uop.ldst_is_rs1 \n connect slots_4.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[4].wakeup_ports[3].bits.uop.csr_cmd \n connect slots_4.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[4].wakeup_ports[3].bits.uop.flush_on_commit \n connect slots_4.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[4].wakeup_ports[3].bits.uop.is_unique \n connect slots_4.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[4].wakeup_ports[3].bits.uop.uses_stq \n connect slots_4.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[4].wakeup_ports[3].bits.uop.uses_ldq \n connect slots_4.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[4].wakeup_ports[3].bits.uop.mem_signed \n connect slots_4.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[4].wakeup_ports[3].bits.uop.mem_size \n connect slots_4.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[4].wakeup_ports[3].bits.uop.mem_cmd \n connect slots_4.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[4].wakeup_ports[3].bits.uop.exc_cause \n connect slots_4.io.wakeup_ports[3].bits.uop.exception, issue_slots[4].wakeup_ports[3].bits.uop.exception \n connect slots_4.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[4].wakeup_ports[3].bits.uop.stale_pdst \n connect slots_4.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[4].wakeup_ports[3].bits.uop.ppred_busy \n connect slots_4.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[4].wakeup_ports[3].bits.uop.prs3_busy \n connect slots_4.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[4].wakeup_ports[3].bits.uop.prs2_busy \n connect slots_4.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[4].wakeup_ports[3].bits.uop.prs1_busy \n connect slots_4.io.wakeup_ports[3].bits.uop.ppred, issue_slots[4].wakeup_ports[3].bits.uop.ppred \n connect slots_4.io.wakeup_ports[3].bits.uop.prs3, issue_slots[4].wakeup_ports[3].bits.uop.prs3 \n connect slots_4.io.wakeup_ports[3].bits.uop.prs2, issue_slots[4].wakeup_ports[3].bits.uop.prs2 \n connect slots_4.io.wakeup_ports[3].bits.uop.prs1, issue_slots[4].wakeup_ports[3].bits.uop.prs1 \n connect slots_4.io.wakeup_ports[3].bits.uop.pdst, issue_slots[4].wakeup_ports[3].bits.uop.pdst \n connect slots_4.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[4].wakeup_ports[3].bits.uop.rxq_idx \n connect slots_4.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[4].wakeup_ports[3].bits.uop.stq_idx \n connect slots_4.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[4].wakeup_ports[3].bits.uop.ldq_idx \n connect slots_4.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[4].wakeup_ports[3].bits.uop.rob_idx \n connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.vec \n connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.wflags \n connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.sqrt \n connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.div \n connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.fma \n connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe \n connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.toint \n connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.fromint \n connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut \n connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn \n connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.swap23 \n connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.swap12 \n connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.ren3 \n connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.ren2 \n connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.ren1 \n connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.wen \n connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.ldst \n connect slots_4.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[4].wakeup_ports[3].bits.uop.op2_sel \n connect slots_4.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[4].wakeup_ports[3].bits.uop.op1_sel \n connect slots_4.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[4].wakeup_ports[3].bits.uop.imm_packed \n connect slots_4.io.wakeup_ports[3].bits.uop.pimm, issue_slots[4].wakeup_ports[3].bits.uop.pimm \n connect slots_4.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[4].wakeup_ports[3].bits.uop.imm_sel \n connect slots_4.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[4].wakeup_ports[3].bits.uop.imm_rename \n connect slots_4.io.wakeup_ports[3].bits.uop.taken, issue_slots[4].wakeup_ports[3].bits.uop.taken \n connect slots_4.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[4].wakeup_ports[3].bits.uop.pc_lob \n connect slots_4.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[4].wakeup_ports[3].bits.uop.edge_inst \n connect slots_4.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[4].wakeup_ports[3].bits.uop.ftq_idx \n connect slots_4.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[4].wakeup_ports[3].bits.uop.is_mov \n connect slots_4.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[4].wakeup_ports[3].bits.uop.is_rocc \n connect slots_4.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[4].wakeup_ports[3].bits.uop.is_sys_pc2epc \n connect slots_4.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[4].wakeup_ports[3].bits.uop.is_eret \n connect slots_4.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[4].wakeup_ports[3].bits.uop.is_amo \n connect slots_4.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[4].wakeup_ports[3].bits.uop.is_sfence \n connect slots_4.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[4].wakeup_ports[3].bits.uop.is_fencei \n connect slots_4.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[4].wakeup_ports[3].bits.uop.is_fence \n connect slots_4.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[4].wakeup_ports[3].bits.uop.is_sfb \n connect slots_4.io.wakeup_ports[3].bits.uop.br_type, issue_slots[4].wakeup_ports[3].bits.uop.br_type \n connect slots_4.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[4].wakeup_ports[3].bits.uop.br_tag \n connect slots_4.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[4].wakeup_ports[3].bits.uop.br_mask \n connect slots_4.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[4].wakeup_ports[3].bits.uop.dis_col_sel \n connect slots_4.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[4].wakeup_ports[3].bits.uop.iw_p3_bypass_hint \n connect slots_4.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[4].wakeup_ports[3].bits.uop.iw_p2_bypass_hint \n connect slots_4.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[4].wakeup_ports[3].bits.uop.iw_p1_bypass_hint \n connect slots_4.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[4].wakeup_ports[3].bits.uop.iw_p2_speculative_child \n connect slots_4.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[4].wakeup_ports[3].bits.uop.iw_p1_speculative_child \n connect slots_4.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[4].wakeup_ports[3].bits.uop.iw_issued_partial_dgen \n connect slots_4.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[4].wakeup_ports[3].bits.uop.iw_issued_partial_agen \n connect slots_4.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[4].wakeup_ports[3].bits.uop.iw_issued \n connect slots_4.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[4].wakeup_ports[3].bits.uop.fu_code[0] \n connect slots_4.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[4].wakeup_ports[3].bits.uop.fu_code[1] \n connect slots_4.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[4].wakeup_ports[3].bits.uop.fu_code[2] \n connect slots_4.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[4].wakeup_ports[3].bits.uop.fu_code[3] \n connect slots_4.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[4].wakeup_ports[3].bits.uop.fu_code[4] \n connect slots_4.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[4].wakeup_ports[3].bits.uop.fu_code[5] \n connect slots_4.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[4].wakeup_ports[3].bits.uop.fu_code[6] \n connect slots_4.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[4].wakeup_ports[3].bits.uop.fu_code[7] \n connect slots_4.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[4].wakeup_ports[3].bits.uop.fu_code[8] \n connect slots_4.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[4].wakeup_ports[3].bits.uop.fu_code[9] \n connect slots_4.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[4].wakeup_ports[3].bits.uop.iq_type[0] \n connect slots_4.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[4].wakeup_ports[3].bits.uop.iq_type[1] \n connect slots_4.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[4].wakeup_ports[3].bits.uop.iq_type[2] \n connect slots_4.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[4].wakeup_ports[3].bits.uop.iq_type[3] \n connect slots_4.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[4].wakeup_ports[3].bits.uop.debug_pc \n connect slots_4.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[4].wakeup_ports[3].bits.uop.is_rvc \n connect slots_4.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[4].wakeup_ports[3].bits.uop.debug_inst \n connect slots_4.io.wakeup_ports[3].bits.uop.inst, issue_slots[4].wakeup_ports[3].bits.uop.inst \n connect slots_4.io.wakeup_ports[3].valid, issue_slots[4].wakeup_ports[3].valid \n connect slots_4.io.squash_grant, issue_slots[4].squash_grant \n connect slots_4.io.clear, issue_slots[4].clear \n connect slots_4.io.kill, issue_slots[4].kill \n connect slots_4.io.brupdate.b2.target_offset, issue_slots[4].brupdate.b2.target_offset \n connect slots_4.io.brupdate.b2.jalr_target, issue_slots[4].brupdate.b2.jalr_target \n connect slots_4.io.brupdate.b2.pc_sel, issue_slots[4].brupdate.b2.pc_sel \n connect slots_4.io.brupdate.b2.cfi_type, issue_slots[4].brupdate.b2.cfi_type \n connect slots_4.io.brupdate.b2.taken, issue_slots[4].brupdate.b2.taken \n connect slots_4.io.brupdate.b2.mispredict, issue_slots[4].brupdate.b2.mispredict \n connect slots_4.io.brupdate.b2.uop.debug_tsrc, issue_slots[4].brupdate.b2.uop.debug_tsrc \n connect slots_4.io.brupdate.b2.uop.debug_fsrc, issue_slots[4].brupdate.b2.uop.debug_fsrc \n connect slots_4.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[4].brupdate.b2.uop.bp_xcpt_if \n connect slots_4.io.brupdate.b2.uop.bp_debug_if, issue_slots[4].brupdate.b2.uop.bp_debug_if \n connect slots_4.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[4].brupdate.b2.uop.xcpt_ma_if \n connect slots_4.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[4].brupdate.b2.uop.xcpt_ae_if \n connect slots_4.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[4].brupdate.b2.uop.xcpt_pf_if \n connect slots_4.io.brupdate.b2.uop.fp_typ, issue_slots[4].brupdate.b2.uop.fp_typ \n connect slots_4.io.brupdate.b2.uop.fp_rm, issue_slots[4].brupdate.b2.uop.fp_rm \n connect slots_4.io.brupdate.b2.uop.fp_val, issue_slots[4].brupdate.b2.uop.fp_val \n connect slots_4.io.brupdate.b2.uop.fcn_op, issue_slots[4].brupdate.b2.uop.fcn_op \n connect slots_4.io.brupdate.b2.uop.fcn_dw, issue_slots[4].brupdate.b2.uop.fcn_dw \n connect slots_4.io.brupdate.b2.uop.frs3_en, issue_slots[4].brupdate.b2.uop.frs3_en \n connect slots_4.io.brupdate.b2.uop.lrs2_rtype, issue_slots[4].brupdate.b2.uop.lrs2_rtype \n connect slots_4.io.brupdate.b2.uop.lrs1_rtype, issue_slots[4].brupdate.b2.uop.lrs1_rtype \n connect slots_4.io.brupdate.b2.uop.dst_rtype, issue_slots[4].brupdate.b2.uop.dst_rtype \n connect slots_4.io.brupdate.b2.uop.lrs3, issue_slots[4].brupdate.b2.uop.lrs3 \n connect slots_4.io.brupdate.b2.uop.lrs2, issue_slots[4].brupdate.b2.uop.lrs2 \n connect slots_4.io.brupdate.b2.uop.lrs1, issue_slots[4].brupdate.b2.uop.lrs1 \n connect slots_4.io.brupdate.b2.uop.ldst, issue_slots[4].brupdate.b2.uop.ldst \n connect slots_4.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[4].brupdate.b2.uop.ldst_is_rs1 \n connect slots_4.io.brupdate.b2.uop.csr_cmd, issue_slots[4].brupdate.b2.uop.csr_cmd \n connect slots_4.io.brupdate.b2.uop.flush_on_commit, issue_slots[4].brupdate.b2.uop.flush_on_commit \n connect slots_4.io.brupdate.b2.uop.is_unique, issue_slots[4].brupdate.b2.uop.is_unique \n connect slots_4.io.brupdate.b2.uop.uses_stq, issue_slots[4].brupdate.b2.uop.uses_stq \n connect slots_4.io.brupdate.b2.uop.uses_ldq, issue_slots[4].brupdate.b2.uop.uses_ldq \n connect slots_4.io.brupdate.b2.uop.mem_signed, issue_slots[4].brupdate.b2.uop.mem_signed \n connect slots_4.io.brupdate.b2.uop.mem_size, issue_slots[4].brupdate.b2.uop.mem_size \n connect slots_4.io.brupdate.b2.uop.mem_cmd, issue_slots[4].brupdate.b2.uop.mem_cmd \n connect slots_4.io.brupdate.b2.uop.exc_cause, issue_slots[4].brupdate.b2.uop.exc_cause \n connect slots_4.io.brupdate.b2.uop.exception, issue_slots[4].brupdate.b2.uop.exception \n connect slots_4.io.brupdate.b2.uop.stale_pdst, issue_slots[4].brupdate.b2.uop.stale_pdst \n connect slots_4.io.brupdate.b2.uop.ppred_busy, issue_slots[4].brupdate.b2.uop.ppred_busy \n connect slots_4.io.brupdate.b2.uop.prs3_busy, issue_slots[4].brupdate.b2.uop.prs3_busy \n connect slots_4.io.brupdate.b2.uop.prs2_busy, issue_slots[4].brupdate.b2.uop.prs2_busy \n connect slots_4.io.brupdate.b2.uop.prs1_busy, issue_slots[4].brupdate.b2.uop.prs1_busy \n connect slots_4.io.brupdate.b2.uop.ppred, issue_slots[4].brupdate.b2.uop.ppred \n connect slots_4.io.brupdate.b2.uop.prs3, issue_slots[4].brupdate.b2.uop.prs3 \n connect slots_4.io.brupdate.b2.uop.prs2, issue_slots[4].brupdate.b2.uop.prs2 \n connect slots_4.io.brupdate.b2.uop.prs1, issue_slots[4].brupdate.b2.uop.prs1 \n connect slots_4.io.brupdate.b2.uop.pdst, issue_slots[4].brupdate.b2.uop.pdst \n connect slots_4.io.brupdate.b2.uop.rxq_idx, issue_slots[4].brupdate.b2.uop.rxq_idx \n connect slots_4.io.brupdate.b2.uop.stq_idx, issue_slots[4].brupdate.b2.uop.stq_idx \n connect slots_4.io.brupdate.b2.uop.ldq_idx, issue_slots[4].brupdate.b2.uop.ldq_idx \n connect slots_4.io.brupdate.b2.uop.rob_idx, issue_slots[4].brupdate.b2.uop.rob_idx \n connect slots_4.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[4].brupdate.b2.uop.fp_ctrl.vec \n connect slots_4.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[4].brupdate.b2.uop.fp_ctrl.wflags \n connect slots_4.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[4].brupdate.b2.uop.fp_ctrl.sqrt \n connect slots_4.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[4].brupdate.b2.uop.fp_ctrl.div \n connect slots_4.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[4].brupdate.b2.uop.fp_ctrl.fma \n connect slots_4.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[4].brupdate.b2.uop.fp_ctrl.fastpipe \n connect slots_4.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[4].brupdate.b2.uop.fp_ctrl.toint \n connect slots_4.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[4].brupdate.b2.uop.fp_ctrl.fromint \n connect slots_4.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[4].brupdate.b2.uop.fp_ctrl.typeTagOut \n connect slots_4.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[4].brupdate.b2.uop.fp_ctrl.typeTagIn \n connect slots_4.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[4].brupdate.b2.uop.fp_ctrl.swap23 \n connect slots_4.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[4].brupdate.b2.uop.fp_ctrl.swap12 \n connect slots_4.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[4].brupdate.b2.uop.fp_ctrl.ren3 \n connect slots_4.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[4].brupdate.b2.uop.fp_ctrl.ren2 \n connect slots_4.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[4].brupdate.b2.uop.fp_ctrl.ren1 \n connect slots_4.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[4].brupdate.b2.uop.fp_ctrl.wen \n connect slots_4.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[4].brupdate.b2.uop.fp_ctrl.ldst \n connect slots_4.io.brupdate.b2.uop.op2_sel, issue_slots[4].brupdate.b2.uop.op2_sel \n connect slots_4.io.brupdate.b2.uop.op1_sel, issue_slots[4].brupdate.b2.uop.op1_sel \n connect slots_4.io.brupdate.b2.uop.imm_packed, issue_slots[4].brupdate.b2.uop.imm_packed \n connect slots_4.io.brupdate.b2.uop.pimm, issue_slots[4].brupdate.b2.uop.pimm \n connect slots_4.io.brupdate.b2.uop.imm_sel, issue_slots[4].brupdate.b2.uop.imm_sel \n connect slots_4.io.brupdate.b2.uop.imm_rename, issue_slots[4].brupdate.b2.uop.imm_rename \n connect slots_4.io.brupdate.b2.uop.taken, issue_slots[4].brupdate.b2.uop.taken \n connect slots_4.io.brupdate.b2.uop.pc_lob, issue_slots[4].brupdate.b2.uop.pc_lob \n connect slots_4.io.brupdate.b2.uop.edge_inst, issue_slots[4].brupdate.b2.uop.edge_inst \n connect slots_4.io.brupdate.b2.uop.ftq_idx, issue_slots[4].brupdate.b2.uop.ftq_idx \n connect slots_4.io.brupdate.b2.uop.is_mov, issue_slots[4].brupdate.b2.uop.is_mov \n connect slots_4.io.brupdate.b2.uop.is_rocc, issue_slots[4].brupdate.b2.uop.is_rocc \n connect slots_4.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[4].brupdate.b2.uop.is_sys_pc2epc \n connect slots_4.io.brupdate.b2.uop.is_eret, issue_slots[4].brupdate.b2.uop.is_eret \n connect slots_4.io.brupdate.b2.uop.is_amo, issue_slots[4].brupdate.b2.uop.is_amo \n connect slots_4.io.brupdate.b2.uop.is_sfence, issue_slots[4].brupdate.b2.uop.is_sfence \n connect slots_4.io.brupdate.b2.uop.is_fencei, issue_slots[4].brupdate.b2.uop.is_fencei \n connect slots_4.io.brupdate.b2.uop.is_fence, issue_slots[4].brupdate.b2.uop.is_fence \n connect slots_4.io.brupdate.b2.uop.is_sfb, issue_slots[4].brupdate.b2.uop.is_sfb \n connect slots_4.io.brupdate.b2.uop.br_type, issue_slots[4].brupdate.b2.uop.br_type \n connect slots_4.io.brupdate.b2.uop.br_tag, issue_slots[4].brupdate.b2.uop.br_tag \n connect slots_4.io.brupdate.b2.uop.br_mask, issue_slots[4].brupdate.b2.uop.br_mask \n connect slots_4.io.brupdate.b2.uop.dis_col_sel, issue_slots[4].brupdate.b2.uop.dis_col_sel \n connect slots_4.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[4].brupdate.b2.uop.iw_p3_bypass_hint \n connect slots_4.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[4].brupdate.b2.uop.iw_p2_bypass_hint \n connect slots_4.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[4].brupdate.b2.uop.iw_p1_bypass_hint \n connect slots_4.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[4].brupdate.b2.uop.iw_p2_speculative_child \n connect slots_4.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[4].brupdate.b2.uop.iw_p1_speculative_child \n connect slots_4.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[4].brupdate.b2.uop.iw_issued_partial_dgen \n connect slots_4.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[4].brupdate.b2.uop.iw_issued_partial_agen \n connect slots_4.io.brupdate.b2.uop.iw_issued, issue_slots[4].brupdate.b2.uop.iw_issued \n connect slots_4.io.brupdate.b2.uop.fu_code[0], issue_slots[4].brupdate.b2.uop.fu_code[0] \n connect slots_4.io.brupdate.b2.uop.fu_code[1], issue_slots[4].brupdate.b2.uop.fu_code[1] \n connect slots_4.io.brupdate.b2.uop.fu_code[2], issue_slots[4].brupdate.b2.uop.fu_code[2] \n connect slots_4.io.brupdate.b2.uop.fu_code[3], issue_slots[4].brupdate.b2.uop.fu_code[3] \n connect slots_4.io.brupdate.b2.uop.fu_code[4], issue_slots[4].brupdate.b2.uop.fu_code[4] \n connect slots_4.io.brupdate.b2.uop.fu_code[5], issue_slots[4].brupdate.b2.uop.fu_code[5] \n connect slots_4.io.brupdate.b2.uop.fu_code[6], issue_slots[4].brupdate.b2.uop.fu_code[6] \n connect slots_4.io.brupdate.b2.uop.fu_code[7], issue_slots[4].brupdate.b2.uop.fu_code[7] \n connect slots_4.io.brupdate.b2.uop.fu_code[8], issue_slots[4].brupdate.b2.uop.fu_code[8] \n connect slots_4.io.brupdate.b2.uop.fu_code[9], issue_slots[4].brupdate.b2.uop.fu_code[9] \n connect slots_4.io.brupdate.b2.uop.iq_type[0], issue_slots[4].brupdate.b2.uop.iq_type[0] \n connect slots_4.io.brupdate.b2.uop.iq_type[1], issue_slots[4].brupdate.b2.uop.iq_type[1] \n connect slots_4.io.brupdate.b2.uop.iq_type[2], issue_slots[4].brupdate.b2.uop.iq_type[2] \n connect slots_4.io.brupdate.b2.uop.iq_type[3], issue_slots[4].brupdate.b2.uop.iq_type[3] \n connect slots_4.io.brupdate.b2.uop.debug_pc, issue_slots[4].brupdate.b2.uop.debug_pc \n connect slots_4.io.brupdate.b2.uop.is_rvc, issue_slots[4].brupdate.b2.uop.is_rvc \n connect slots_4.io.brupdate.b2.uop.debug_inst, issue_slots[4].brupdate.b2.uop.debug_inst \n connect slots_4.io.brupdate.b2.uop.inst, issue_slots[4].brupdate.b2.uop.inst \n connect slots_4.io.brupdate.b1.mispredict_mask, issue_slots[4].brupdate.b1.mispredict_mask \n connect slots_4.io.brupdate.b1.resolve_mask, issue_slots[4].brupdate.b1.resolve_mask \n connect issue_slots[4].out_uop.debug_tsrc, slots_4.io.out_uop.debug_tsrc \n connect issue_slots[4].out_uop.debug_fsrc, slots_4.io.out_uop.debug_fsrc \n connect issue_slots[4].out_uop.bp_xcpt_if, slots_4.io.out_uop.bp_xcpt_if \n connect issue_slots[4].out_uop.bp_debug_if, slots_4.io.out_uop.bp_debug_if \n connect issue_slots[4].out_uop.xcpt_ma_if, slots_4.io.out_uop.xcpt_ma_if \n connect issue_slots[4].out_uop.xcpt_ae_if, slots_4.io.out_uop.xcpt_ae_if \n connect issue_slots[4].out_uop.xcpt_pf_if, slots_4.io.out_uop.xcpt_pf_if \n connect issue_slots[4].out_uop.fp_typ, slots_4.io.out_uop.fp_typ \n connect issue_slots[4].out_uop.fp_rm, slots_4.io.out_uop.fp_rm \n connect issue_slots[4].out_uop.fp_val, slots_4.io.out_uop.fp_val \n connect issue_slots[4].out_uop.fcn_op, slots_4.io.out_uop.fcn_op \n connect issue_slots[4].out_uop.fcn_dw, slots_4.io.out_uop.fcn_dw \n connect issue_slots[4].out_uop.frs3_en, slots_4.io.out_uop.frs3_en \n connect issue_slots[4].out_uop.lrs2_rtype, slots_4.io.out_uop.lrs2_rtype \n connect issue_slots[4].out_uop.lrs1_rtype, slots_4.io.out_uop.lrs1_rtype \n connect issue_slots[4].out_uop.dst_rtype, slots_4.io.out_uop.dst_rtype \n connect issue_slots[4].out_uop.lrs3, slots_4.io.out_uop.lrs3 \n connect issue_slots[4].out_uop.lrs2, slots_4.io.out_uop.lrs2 \n connect issue_slots[4].out_uop.lrs1, slots_4.io.out_uop.lrs1 \n connect issue_slots[4].out_uop.ldst, slots_4.io.out_uop.ldst \n connect issue_slots[4].out_uop.ldst_is_rs1, slots_4.io.out_uop.ldst_is_rs1 \n connect issue_slots[4].out_uop.csr_cmd, slots_4.io.out_uop.csr_cmd \n connect issue_slots[4].out_uop.flush_on_commit, slots_4.io.out_uop.flush_on_commit \n connect issue_slots[4].out_uop.is_unique, slots_4.io.out_uop.is_unique \n connect issue_slots[4].out_uop.uses_stq, slots_4.io.out_uop.uses_stq \n connect issue_slots[4].out_uop.uses_ldq, slots_4.io.out_uop.uses_ldq \n connect issue_slots[4].out_uop.mem_signed, slots_4.io.out_uop.mem_signed \n connect issue_slots[4].out_uop.mem_size, slots_4.io.out_uop.mem_size \n connect issue_slots[4].out_uop.mem_cmd, slots_4.io.out_uop.mem_cmd \n connect issue_slots[4].out_uop.exc_cause, slots_4.io.out_uop.exc_cause \n connect issue_slots[4].out_uop.exception, slots_4.io.out_uop.exception \n connect issue_slots[4].out_uop.stale_pdst, slots_4.io.out_uop.stale_pdst \n connect issue_slots[4].out_uop.ppred_busy, slots_4.io.out_uop.ppred_busy \n connect issue_slots[4].out_uop.prs3_busy, slots_4.io.out_uop.prs3_busy \n connect issue_slots[4].out_uop.prs2_busy, slots_4.io.out_uop.prs2_busy \n connect issue_slots[4].out_uop.prs1_busy, slots_4.io.out_uop.prs1_busy \n connect issue_slots[4].out_uop.ppred, slots_4.io.out_uop.ppred \n connect issue_slots[4].out_uop.prs3, slots_4.io.out_uop.prs3 \n connect issue_slots[4].out_uop.prs2, slots_4.io.out_uop.prs2 \n connect issue_slots[4].out_uop.prs1, slots_4.io.out_uop.prs1 \n connect issue_slots[4].out_uop.pdst, slots_4.io.out_uop.pdst \n connect issue_slots[4].out_uop.rxq_idx, slots_4.io.out_uop.rxq_idx \n connect issue_slots[4].out_uop.stq_idx, slots_4.io.out_uop.stq_idx \n connect issue_slots[4].out_uop.ldq_idx, slots_4.io.out_uop.ldq_idx \n connect issue_slots[4].out_uop.rob_idx, slots_4.io.out_uop.rob_idx \n connect issue_slots[4].out_uop.fp_ctrl.vec, slots_4.io.out_uop.fp_ctrl.vec \n connect issue_slots[4].out_uop.fp_ctrl.wflags, slots_4.io.out_uop.fp_ctrl.wflags \n connect issue_slots[4].out_uop.fp_ctrl.sqrt, slots_4.io.out_uop.fp_ctrl.sqrt \n connect issue_slots[4].out_uop.fp_ctrl.div, slots_4.io.out_uop.fp_ctrl.div \n connect issue_slots[4].out_uop.fp_ctrl.fma, slots_4.io.out_uop.fp_ctrl.fma \n connect issue_slots[4].out_uop.fp_ctrl.fastpipe, slots_4.io.out_uop.fp_ctrl.fastpipe \n connect issue_slots[4].out_uop.fp_ctrl.toint, slots_4.io.out_uop.fp_ctrl.toint \n connect issue_slots[4].out_uop.fp_ctrl.fromint, slots_4.io.out_uop.fp_ctrl.fromint \n connect issue_slots[4].out_uop.fp_ctrl.typeTagOut, slots_4.io.out_uop.fp_ctrl.typeTagOut \n connect issue_slots[4].out_uop.fp_ctrl.typeTagIn, slots_4.io.out_uop.fp_ctrl.typeTagIn \n connect issue_slots[4].out_uop.fp_ctrl.swap23, slots_4.io.out_uop.fp_ctrl.swap23 \n connect issue_slots[4].out_uop.fp_ctrl.swap12, slots_4.io.out_uop.fp_ctrl.swap12 \n connect issue_slots[4].out_uop.fp_ctrl.ren3, slots_4.io.out_uop.fp_ctrl.ren3 \n connect issue_slots[4].out_uop.fp_ctrl.ren2, slots_4.io.out_uop.fp_ctrl.ren2 \n connect issue_slots[4].out_uop.fp_ctrl.ren1, slots_4.io.out_uop.fp_ctrl.ren1 \n connect issue_slots[4].out_uop.fp_ctrl.wen, slots_4.io.out_uop.fp_ctrl.wen \n connect issue_slots[4].out_uop.fp_ctrl.ldst, slots_4.io.out_uop.fp_ctrl.ldst \n connect issue_slots[4].out_uop.op2_sel, slots_4.io.out_uop.op2_sel \n connect issue_slots[4].out_uop.op1_sel, slots_4.io.out_uop.op1_sel \n connect issue_slots[4].out_uop.imm_packed, slots_4.io.out_uop.imm_packed \n connect issue_slots[4].out_uop.pimm, slots_4.io.out_uop.pimm \n connect issue_slots[4].out_uop.imm_sel, slots_4.io.out_uop.imm_sel \n connect issue_slots[4].out_uop.imm_rename, slots_4.io.out_uop.imm_rename \n connect issue_slots[4].out_uop.taken, slots_4.io.out_uop.taken \n connect issue_slots[4].out_uop.pc_lob, slots_4.io.out_uop.pc_lob \n connect issue_slots[4].out_uop.edge_inst, slots_4.io.out_uop.edge_inst \n connect issue_slots[4].out_uop.ftq_idx, slots_4.io.out_uop.ftq_idx \n connect issue_slots[4].out_uop.is_mov, slots_4.io.out_uop.is_mov \n connect issue_slots[4].out_uop.is_rocc, slots_4.io.out_uop.is_rocc \n connect issue_slots[4].out_uop.is_sys_pc2epc, slots_4.io.out_uop.is_sys_pc2epc \n connect issue_slots[4].out_uop.is_eret, slots_4.io.out_uop.is_eret \n connect issue_slots[4].out_uop.is_amo, slots_4.io.out_uop.is_amo \n connect issue_slots[4].out_uop.is_sfence, slots_4.io.out_uop.is_sfence \n connect issue_slots[4].out_uop.is_fencei, slots_4.io.out_uop.is_fencei \n connect issue_slots[4].out_uop.is_fence, slots_4.io.out_uop.is_fence \n connect issue_slots[4].out_uop.is_sfb, slots_4.io.out_uop.is_sfb \n connect issue_slots[4].out_uop.br_type, slots_4.io.out_uop.br_type \n connect issue_slots[4].out_uop.br_tag, slots_4.io.out_uop.br_tag \n connect issue_slots[4].out_uop.br_mask, slots_4.io.out_uop.br_mask \n connect issue_slots[4].out_uop.dis_col_sel, slots_4.io.out_uop.dis_col_sel \n connect issue_slots[4].out_uop.iw_p3_bypass_hint, slots_4.io.out_uop.iw_p3_bypass_hint \n connect issue_slots[4].out_uop.iw_p2_bypass_hint, slots_4.io.out_uop.iw_p2_bypass_hint \n connect issue_slots[4].out_uop.iw_p1_bypass_hint, slots_4.io.out_uop.iw_p1_bypass_hint \n connect issue_slots[4].out_uop.iw_p2_speculative_child, slots_4.io.out_uop.iw_p2_speculative_child \n connect issue_slots[4].out_uop.iw_p1_speculative_child, slots_4.io.out_uop.iw_p1_speculative_child \n connect issue_slots[4].out_uop.iw_issued_partial_dgen, slots_4.io.out_uop.iw_issued_partial_dgen \n connect issue_slots[4].out_uop.iw_issued_partial_agen, slots_4.io.out_uop.iw_issued_partial_agen \n connect issue_slots[4].out_uop.iw_issued, slots_4.io.out_uop.iw_issued \n connect issue_slots[4].out_uop.fu_code[0], slots_4.io.out_uop.fu_code[0] \n connect issue_slots[4].out_uop.fu_code[1], slots_4.io.out_uop.fu_code[1] \n connect issue_slots[4].out_uop.fu_code[2], slots_4.io.out_uop.fu_code[2] \n connect issue_slots[4].out_uop.fu_code[3], slots_4.io.out_uop.fu_code[3] \n connect issue_slots[4].out_uop.fu_code[4], slots_4.io.out_uop.fu_code[4] \n connect issue_slots[4].out_uop.fu_code[5], slots_4.io.out_uop.fu_code[5] \n connect issue_slots[4].out_uop.fu_code[6], slots_4.io.out_uop.fu_code[6] \n connect issue_slots[4].out_uop.fu_code[7], slots_4.io.out_uop.fu_code[7] \n connect issue_slots[4].out_uop.fu_code[8], slots_4.io.out_uop.fu_code[8] \n connect issue_slots[4].out_uop.fu_code[9], slots_4.io.out_uop.fu_code[9] \n connect issue_slots[4].out_uop.iq_type[0], slots_4.io.out_uop.iq_type[0] \n connect issue_slots[4].out_uop.iq_type[1], slots_4.io.out_uop.iq_type[1] \n connect issue_slots[4].out_uop.iq_type[2], slots_4.io.out_uop.iq_type[2] \n connect issue_slots[4].out_uop.iq_type[3], slots_4.io.out_uop.iq_type[3] \n connect issue_slots[4].out_uop.debug_pc, slots_4.io.out_uop.debug_pc \n connect issue_slots[4].out_uop.is_rvc, slots_4.io.out_uop.is_rvc \n connect issue_slots[4].out_uop.debug_inst, slots_4.io.out_uop.debug_inst \n connect issue_slots[4].out_uop.inst, slots_4.io.out_uop.inst \n connect slots_4.io.in_uop.bits.debug_tsrc, issue_slots[4].in_uop.bits.debug_tsrc \n connect slots_4.io.in_uop.bits.debug_fsrc, issue_slots[4].in_uop.bits.debug_fsrc \n connect slots_4.io.in_uop.bits.bp_xcpt_if, issue_slots[4].in_uop.bits.bp_xcpt_if \n connect slots_4.io.in_uop.bits.bp_debug_if, issue_slots[4].in_uop.bits.bp_debug_if \n connect slots_4.io.in_uop.bits.xcpt_ma_if, issue_slots[4].in_uop.bits.xcpt_ma_if \n connect slots_4.io.in_uop.bits.xcpt_ae_if, issue_slots[4].in_uop.bits.xcpt_ae_if \n connect slots_4.io.in_uop.bits.xcpt_pf_if, issue_slots[4].in_uop.bits.xcpt_pf_if \n connect slots_4.io.in_uop.bits.fp_typ, issue_slots[4].in_uop.bits.fp_typ \n connect slots_4.io.in_uop.bits.fp_rm, issue_slots[4].in_uop.bits.fp_rm \n connect slots_4.io.in_uop.bits.fp_val, issue_slots[4].in_uop.bits.fp_val \n connect slots_4.io.in_uop.bits.fcn_op, issue_slots[4].in_uop.bits.fcn_op \n connect slots_4.io.in_uop.bits.fcn_dw, issue_slots[4].in_uop.bits.fcn_dw \n connect slots_4.io.in_uop.bits.frs3_en, issue_slots[4].in_uop.bits.frs3_en \n connect slots_4.io.in_uop.bits.lrs2_rtype, issue_slots[4].in_uop.bits.lrs2_rtype \n connect slots_4.io.in_uop.bits.lrs1_rtype, issue_slots[4].in_uop.bits.lrs1_rtype \n connect slots_4.io.in_uop.bits.dst_rtype, issue_slots[4].in_uop.bits.dst_rtype \n connect slots_4.io.in_uop.bits.lrs3, issue_slots[4].in_uop.bits.lrs3 \n connect slots_4.io.in_uop.bits.lrs2, issue_slots[4].in_uop.bits.lrs2 \n connect slots_4.io.in_uop.bits.lrs1, issue_slots[4].in_uop.bits.lrs1 \n connect slots_4.io.in_uop.bits.ldst, issue_slots[4].in_uop.bits.ldst \n connect slots_4.io.in_uop.bits.ldst_is_rs1, issue_slots[4].in_uop.bits.ldst_is_rs1 \n connect slots_4.io.in_uop.bits.csr_cmd, issue_slots[4].in_uop.bits.csr_cmd \n connect slots_4.io.in_uop.bits.flush_on_commit, issue_slots[4].in_uop.bits.flush_on_commit \n connect slots_4.io.in_uop.bits.is_unique, issue_slots[4].in_uop.bits.is_unique \n connect slots_4.io.in_uop.bits.uses_stq, issue_slots[4].in_uop.bits.uses_stq \n connect slots_4.io.in_uop.bits.uses_ldq, issue_slots[4].in_uop.bits.uses_ldq \n connect slots_4.io.in_uop.bits.mem_signed, issue_slots[4].in_uop.bits.mem_signed \n connect slots_4.io.in_uop.bits.mem_size, issue_slots[4].in_uop.bits.mem_size \n connect slots_4.io.in_uop.bits.mem_cmd, issue_slots[4].in_uop.bits.mem_cmd \n connect slots_4.io.in_uop.bits.exc_cause, issue_slots[4].in_uop.bits.exc_cause \n connect slots_4.io.in_uop.bits.exception, issue_slots[4].in_uop.bits.exception \n connect slots_4.io.in_uop.bits.stale_pdst, issue_slots[4].in_uop.bits.stale_pdst \n connect slots_4.io.in_uop.bits.ppred_busy, issue_slots[4].in_uop.bits.ppred_busy \n connect slots_4.io.in_uop.bits.prs3_busy, issue_slots[4].in_uop.bits.prs3_busy \n connect slots_4.io.in_uop.bits.prs2_busy, issue_slots[4].in_uop.bits.prs2_busy \n connect slots_4.io.in_uop.bits.prs1_busy, issue_slots[4].in_uop.bits.prs1_busy \n connect slots_4.io.in_uop.bits.ppred, issue_slots[4].in_uop.bits.ppred \n connect slots_4.io.in_uop.bits.prs3, issue_slots[4].in_uop.bits.prs3 \n connect slots_4.io.in_uop.bits.prs2, issue_slots[4].in_uop.bits.prs2 \n connect slots_4.io.in_uop.bits.prs1, issue_slots[4].in_uop.bits.prs1 \n connect slots_4.io.in_uop.bits.pdst, issue_slots[4].in_uop.bits.pdst \n connect slots_4.io.in_uop.bits.rxq_idx, issue_slots[4].in_uop.bits.rxq_idx \n connect slots_4.io.in_uop.bits.stq_idx, issue_slots[4].in_uop.bits.stq_idx \n connect slots_4.io.in_uop.bits.ldq_idx, issue_slots[4].in_uop.bits.ldq_idx \n connect slots_4.io.in_uop.bits.rob_idx, issue_slots[4].in_uop.bits.rob_idx \n connect slots_4.io.in_uop.bits.fp_ctrl.vec, issue_slots[4].in_uop.bits.fp_ctrl.vec \n connect slots_4.io.in_uop.bits.fp_ctrl.wflags, issue_slots[4].in_uop.bits.fp_ctrl.wflags \n connect slots_4.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[4].in_uop.bits.fp_ctrl.sqrt \n connect slots_4.io.in_uop.bits.fp_ctrl.div, issue_slots[4].in_uop.bits.fp_ctrl.div \n connect slots_4.io.in_uop.bits.fp_ctrl.fma, issue_slots[4].in_uop.bits.fp_ctrl.fma \n connect slots_4.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[4].in_uop.bits.fp_ctrl.fastpipe \n connect slots_4.io.in_uop.bits.fp_ctrl.toint, issue_slots[4].in_uop.bits.fp_ctrl.toint \n connect slots_4.io.in_uop.bits.fp_ctrl.fromint, issue_slots[4].in_uop.bits.fp_ctrl.fromint \n connect slots_4.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[4].in_uop.bits.fp_ctrl.typeTagOut \n connect slots_4.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[4].in_uop.bits.fp_ctrl.typeTagIn \n connect slots_4.io.in_uop.bits.fp_ctrl.swap23, issue_slots[4].in_uop.bits.fp_ctrl.swap23 \n connect slots_4.io.in_uop.bits.fp_ctrl.swap12, issue_slots[4].in_uop.bits.fp_ctrl.swap12 \n connect slots_4.io.in_uop.bits.fp_ctrl.ren3, issue_slots[4].in_uop.bits.fp_ctrl.ren3 \n connect slots_4.io.in_uop.bits.fp_ctrl.ren2, issue_slots[4].in_uop.bits.fp_ctrl.ren2 \n connect slots_4.io.in_uop.bits.fp_ctrl.ren1, issue_slots[4].in_uop.bits.fp_ctrl.ren1 \n connect slots_4.io.in_uop.bits.fp_ctrl.wen, issue_slots[4].in_uop.bits.fp_ctrl.wen \n connect slots_4.io.in_uop.bits.fp_ctrl.ldst, issue_slots[4].in_uop.bits.fp_ctrl.ldst \n connect slots_4.io.in_uop.bits.op2_sel, issue_slots[4].in_uop.bits.op2_sel \n connect slots_4.io.in_uop.bits.op1_sel, issue_slots[4].in_uop.bits.op1_sel \n connect slots_4.io.in_uop.bits.imm_packed, issue_slots[4].in_uop.bits.imm_packed \n connect slots_4.io.in_uop.bits.pimm, issue_slots[4].in_uop.bits.pimm \n connect slots_4.io.in_uop.bits.imm_sel, issue_slots[4].in_uop.bits.imm_sel \n connect slots_4.io.in_uop.bits.imm_rename, issue_slots[4].in_uop.bits.imm_rename \n connect slots_4.io.in_uop.bits.taken, issue_slots[4].in_uop.bits.taken \n connect slots_4.io.in_uop.bits.pc_lob, issue_slots[4].in_uop.bits.pc_lob \n connect slots_4.io.in_uop.bits.edge_inst, issue_slots[4].in_uop.bits.edge_inst \n connect slots_4.io.in_uop.bits.ftq_idx, issue_slots[4].in_uop.bits.ftq_idx \n connect slots_4.io.in_uop.bits.is_mov, issue_slots[4].in_uop.bits.is_mov \n connect slots_4.io.in_uop.bits.is_rocc, issue_slots[4].in_uop.bits.is_rocc \n connect slots_4.io.in_uop.bits.is_sys_pc2epc, issue_slots[4].in_uop.bits.is_sys_pc2epc \n connect slots_4.io.in_uop.bits.is_eret, issue_slots[4].in_uop.bits.is_eret \n connect slots_4.io.in_uop.bits.is_amo, issue_slots[4].in_uop.bits.is_amo \n connect slots_4.io.in_uop.bits.is_sfence, issue_slots[4].in_uop.bits.is_sfence \n connect slots_4.io.in_uop.bits.is_fencei, issue_slots[4].in_uop.bits.is_fencei \n connect slots_4.io.in_uop.bits.is_fence, issue_slots[4].in_uop.bits.is_fence \n connect slots_4.io.in_uop.bits.is_sfb, issue_slots[4].in_uop.bits.is_sfb \n connect slots_4.io.in_uop.bits.br_type, issue_slots[4].in_uop.bits.br_type \n connect slots_4.io.in_uop.bits.br_tag, issue_slots[4].in_uop.bits.br_tag \n connect slots_4.io.in_uop.bits.br_mask, issue_slots[4].in_uop.bits.br_mask \n connect slots_4.io.in_uop.bits.dis_col_sel, issue_slots[4].in_uop.bits.dis_col_sel \n connect slots_4.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[4].in_uop.bits.iw_p3_bypass_hint \n connect slots_4.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[4].in_uop.bits.iw_p2_bypass_hint \n connect slots_4.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[4].in_uop.bits.iw_p1_bypass_hint \n connect slots_4.io.in_uop.bits.iw_p2_speculative_child, issue_slots[4].in_uop.bits.iw_p2_speculative_child \n connect slots_4.io.in_uop.bits.iw_p1_speculative_child, issue_slots[4].in_uop.bits.iw_p1_speculative_child \n connect slots_4.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[4].in_uop.bits.iw_issued_partial_dgen \n connect slots_4.io.in_uop.bits.iw_issued_partial_agen, issue_slots[4].in_uop.bits.iw_issued_partial_agen \n connect slots_4.io.in_uop.bits.iw_issued, issue_slots[4].in_uop.bits.iw_issued \n connect slots_4.io.in_uop.bits.fu_code[0], issue_slots[4].in_uop.bits.fu_code[0] \n connect slots_4.io.in_uop.bits.fu_code[1], issue_slots[4].in_uop.bits.fu_code[1] \n connect slots_4.io.in_uop.bits.fu_code[2], issue_slots[4].in_uop.bits.fu_code[2] \n connect slots_4.io.in_uop.bits.fu_code[3], issue_slots[4].in_uop.bits.fu_code[3] \n connect slots_4.io.in_uop.bits.fu_code[4], issue_slots[4].in_uop.bits.fu_code[4] \n connect slots_4.io.in_uop.bits.fu_code[5], issue_slots[4].in_uop.bits.fu_code[5] \n connect slots_4.io.in_uop.bits.fu_code[6], issue_slots[4].in_uop.bits.fu_code[6] \n connect slots_4.io.in_uop.bits.fu_code[7], issue_slots[4].in_uop.bits.fu_code[7] \n connect slots_4.io.in_uop.bits.fu_code[8], issue_slots[4].in_uop.bits.fu_code[8] \n connect slots_4.io.in_uop.bits.fu_code[9], issue_slots[4].in_uop.bits.fu_code[9] \n connect slots_4.io.in_uop.bits.iq_type[0], issue_slots[4].in_uop.bits.iq_type[0] \n connect slots_4.io.in_uop.bits.iq_type[1], issue_slots[4].in_uop.bits.iq_type[1] \n connect slots_4.io.in_uop.bits.iq_type[2], issue_slots[4].in_uop.bits.iq_type[2] \n connect slots_4.io.in_uop.bits.iq_type[3], issue_slots[4].in_uop.bits.iq_type[3] \n connect slots_4.io.in_uop.bits.debug_pc, issue_slots[4].in_uop.bits.debug_pc \n connect slots_4.io.in_uop.bits.is_rvc, issue_slots[4].in_uop.bits.is_rvc \n connect slots_4.io.in_uop.bits.debug_inst, issue_slots[4].in_uop.bits.debug_inst \n connect slots_4.io.in_uop.bits.inst, issue_slots[4].in_uop.bits.inst \n connect slots_4.io.in_uop.valid, issue_slots[4].in_uop.valid \n connect issue_slots[4].iss_uop.debug_tsrc, slots_4.io.iss_uop.debug_tsrc \n connect issue_slots[4].iss_uop.debug_fsrc, slots_4.io.iss_uop.debug_fsrc \n connect issue_slots[4].iss_uop.bp_xcpt_if, slots_4.io.iss_uop.bp_xcpt_if \n connect issue_slots[4].iss_uop.bp_debug_if, slots_4.io.iss_uop.bp_debug_if \n connect issue_slots[4].iss_uop.xcpt_ma_if, slots_4.io.iss_uop.xcpt_ma_if \n connect issue_slots[4].iss_uop.xcpt_ae_if, slots_4.io.iss_uop.xcpt_ae_if \n connect issue_slots[4].iss_uop.xcpt_pf_if, slots_4.io.iss_uop.xcpt_pf_if \n connect issue_slots[4].iss_uop.fp_typ, slots_4.io.iss_uop.fp_typ \n connect issue_slots[4].iss_uop.fp_rm, slots_4.io.iss_uop.fp_rm \n connect issue_slots[4].iss_uop.fp_val, slots_4.io.iss_uop.fp_val \n connect issue_slots[4].iss_uop.fcn_op, slots_4.io.iss_uop.fcn_op \n connect issue_slots[4].iss_uop.fcn_dw, slots_4.io.iss_uop.fcn_dw \n connect issue_slots[4].iss_uop.frs3_en, slots_4.io.iss_uop.frs3_en \n connect issue_slots[4].iss_uop.lrs2_rtype, slots_4.io.iss_uop.lrs2_rtype \n connect issue_slots[4].iss_uop.lrs1_rtype, slots_4.io.iss_uop.lrs1_rtype \n connect issue_slots[4].iss_uop.dst_rtype, slots_4.io.iss_uop.dst_rtype \n connect issue_slots[4].iss_uop.lrs3, slots_4.io.iss_uop.lrs3 \n connect issue_slots[4].iss_uop.lrs2, slots_4.io.iss_uop.lrs2 \n connect issue_slots[4].iss_uop.lrs1, slots_4.io.iss_uop.lrs1 \n connect issue_slots[4].iss_uop.ldst, slots_4.io.iss_uop.ldst \n connect issue_slots[4].iss_uop.ldst_is_rs1, slots_4.io.iss_uop.ldst_is_rs1 \n connect issue_slots[4].iss_uop.csr_cmd, slots_4.io.iss_uop.csr_cmd \n connect issue_slots[4].iss_uop.flush_on_commit, slots_4.io.iss_uop.flush_on_commit \n connect issue_slots[4].iss_uop.is_unique, slots_4.io.iss_uop.is_unique \n connect issue_slots[4].iss_uop.uses_stq, slots_4.io.iss_uop.uses_stq \n connect issue_slots[4].iss_uop.uses_ldq, slots_4.io.iss_uop.uses_ldq \n connect issue_slots[4].iss_uop.mem_signed, slots_4.io.iss_uop.mem_signed \n connect issue_slots[4].iss_uop.mem_size, slots_4.io.iss_uop.mem_size \n connect issue_slots[4].iss_uop.mem_cmd, slots_4.io.iss_uop.mem_cmd \n connect issue_slots[4].iss_uop.exc_cause, slots_4.io.iss_uop.exc_cause \n connect issue_slots[4].iss_uop.exception, slots_4.io.iss_uop.exception \n connect issue_slots[4].iss_uop.stale_pdst, slots_4.io.iss_uop.stale_pdst \n connect issue_slots[4].iss_uop.ppred_busy, slots_4.io.iss_uop.ppred_busy \n connect issue_slots[4].iss_uop.prs3_busy, slots_4.io.iss_uop.prs3_busy \n connect issue_slots[4].iss_uop.prs2_busy, slots_4.io.iss_uop.prs2_busy \n connect issue_slots[4].iss_uop.prs1_busy, slots_4.io.iss_uop.prs1_busy \n connect issue_slots[4].iss_uop.ppred, slots_4.io.iss_uop.ppred \n connect issue_slots[4].iss_uop.prs3, slots_4.io.iss_uop.prs3 \n connect issue_slots[4].iss_uop.prs2, slots_4.io.iss_uop.prs2 \n connect issue_slots[4].iss_uop.prs1, slots_4.io.iss_uop.prs1 \n connect issue_slots[4].iss_uop.pdst, slots_4.io.iss_uop.pdst \n connect issue_slots[4].iss_uop.rxq_idx, slots_4.io.iss_uop.rxq_idx \n connect issue_slots[4].iss_uop.stq_idx, slots_4.io.iss_uop.stq_idx \n connect issue_slots[4].iss_uop.ldq_idx, slots_4.io.iss_uop.ldq_idx \n connect issue_slots[4].iss_uop.rob_idx, slots_4.io.iss_uop.rob_idx \n connect issue_slots[4].iss_uop.fp_ctrl.vec, slots_4.io.iss_uop.fp_ctrl.vec \n connect issue_slots[4].iss_uop.fp_ctrl.wflags, slots_4.io.iss_uop.fp_ctrl.wflags \n connect issue_slots[4].iss_uop.fp_ctrl.sqrt, slots_4.io.iss_uop.fp_ctrl.sqrt \n connect issue_slots[4].iss_uop.fp_ctrl.div, slots_4.io.iss_uop.fp_ctrl.div \n connect issue_slots[4].iss_uop.fp_ctrl.fma, slots_4.io.iss_uop.fp_ctrl.fma \n connect issue_slots[4].iss_uop.fp_ctrl.fastpipe, slots_4.io.iss_uop.fp_ctrl.fastpipe \n connect issue_slots[4].iss_uop.fp_ctrl.toint, slots_4.io.iss_uop.fp_ctrl.toint \n connect issue_slots[4].iss_uop.fp_ctrl.fromint, slots_4.io.iss_uop.fp_ctrl.fromint \n connect issue_slots[4].iss_uop.fp_ctrl.typeTagOut, slots_4.io.iss_uop.fp_ctrl.typeTagOut \n connect issue_slots[4].iss_uop.fp_ctrl.typeTagIn, slots_4.io.iss_uop.fp_ctrl.typeTagIn \n connect issue_slots[4].iss_uop.fp_ctrl.swap23, slots_4.io.iss_uop.fp_ctrl.swap23 \n connect issue_slots[4].iss_uop.fp_ctrl.swap12, slots_4.io.iss_uop.fp_ctrl.swap12 \n connect issue_slots[4].iss_uop.fp_ctrl.ren3, slots_4.io.iss_uop.fp_ctrl.ren3 \n connect issue_slots[4].iss_uop.fp_ctrl.ren2, slots_4.io.iss_uop.fp_ctrl.ren2 \n connect issue_slots[4].iss_uop.fp_ctrl.ren1, slots_4.io.iss_uop.fp_ctrl.ren1 \n connect issue_slots[4].iss_uop.fp_ctrl.wen, slots_4.io.iss_uop.fp_ctrl.wen \n connect issue_slots[4].iss_uop.fp_ctrl.ldst, slots_4.io.iss_uop.fp_ctrl.ldst \n connect issue_slots[4].iss_uop.op2_sel, slots_4.io.iss_uop.op2_sel \n connect issue_slots[4].iss_uop.op1_sel, slots_4.io.iss_uop.op1_sel \n connect issue_slots[4].iss_uop.imm_packed, slots_4.io.iss_uop.imm_packed \n connect issue_slots[4].iss_uop.pimm, slots_4.io.iss_uop.pimm \n connect issue_slots[4].iss_uop.imm_sel, slots_4.io.iss_uop.imm_sel \n connect issue_slots[4].iss_uop.imm_rename, slots_4.io.iss_uop.imm_rename \n connect issue_slots[4].iss_uop.taken, slots_4.io.iss_uop.taken \n connect issue_slots[4].iss_uop.pc_lob, slots_4.io.iss_uop.pc_lob \n connect issue_slots[4].iss_uop.edge_inst, slots_4.io.iss_uop.edge_inst \n connect issue_slots[4].iss_uop.ftq_idx, slots_4.io.iss_uop.ftq_idx \n connect issue_slots[4].iss_uop.is_mov, slots_4.io.iss_uop.is_mov \n connect issue_slots[4].iss_uop.is_rocc, slots_4.io.iss_uop.is_rocc \n connect issue_slots[4].iss_uop.is_sys_pc2epc, slots_4.io.iss_uop.is_sys_pc2epc \n connect issue_slots[4].iss_uop.is_eret, slots_4.io.iss_uop.is_eret \n connect issue_slots[4].iss_uop.is_amo, slots_4.io.iss_uop.is_amo \n connect issue_slots[4].iss_uop.is_sfence, slots_4.io.iss_uop.is_sfence \n connect issue_slots[4].iss_uop.is_fencei, slots_4.io.iss_uop.is_fencei \n connect issue_slots[4].iss_uop.is_fence, slots_4.io.iss_uop.is_fence \n connect issue_slots[4].iss_uop.is_sfb, slots_4.io.iss_uop.is_sfb \n connect issue_slots[4].iss_uop.br_type, slots_4.io.iss_uop.br_type \n connect issue_slots[4].iss_uop.br_tag, slots_4.io.iss_uop.br_tag \n connect issue_slots[4].iss_uop.br_mask, slots_4.io.iss_uop.br_mask \n connect issue_slots[4].iss_uop.dis_col_sel, slots_4.io.iss_uop.dis_col_sel \n connect issue_slots[4].iss_uop.iw_p3_bypass_hint, slots_4.io.iss_uop.iw_p3_bypass_hint \n connect issue_slots[4].iss_uop.iw_p2_bypass_hint, slots_4.io.iss_uop.iw_p2_bypass_hint \n connect issue_slots[4].iss_uop.iw_p1_bypass_hint, slots_4.io.iss_uop.iw_p1_bypass_hint \n connect issue_slots[4].iss_uop.iw_p2_speculative_child, slots_4.io.iss_uop.iw_p2_speculative_child \n connect issue_slots[4].iss_uop.iw_p1_speculative_child, slots_4.io.iss_uop.iw_p1_speculative_child \n connect issue_slots[4].iss_uop.iw_issued_partial_dgen, slots_4.io.iss_uop.iw_issued_partial_dgen \n connect issue_slots[4].iss_uop.iw_issued_partial_agen, slots_4.io.iss_uop.iw_issued_partial_agen \n connect issue_slots[4].iss_uop.iw_issued, slots_4.io.iss_uop.iw_issued \n connect issue_slots[4].iss_uop.fu_code[0], slots_4.io.iss_uop.fu_code[0] \n connect issue_slots[4].iss_uop.fu_code[1], slots_4.io.iss_uop.fu_code[1] \n connect issue_slots[4].iss_uop.fu_code[2], slots_4.io.iss_uop.fu_code[2] \n connect issue_slots[4].iss_uop.fu_code[3], slots_4.io.iss_uop.fu_code[3] \n connect issue_slots[4].iss_uop.fu_code[4], slots_4.io.iss_uop.fu_code[4] \n connect issue_slots[4].iss_uop.fu_code[5], slots_4.io.iss_uop.fu_code[5] \n connect issue_slots[4].iss_uop.fu_code[6], slots_4.io.iss_uop.fu_code[6] \n connect issue_slots[4].iss_uop.fu_code[7], slots_4.io.iss_uop.fu_code[7] \n connect issue_slots[4].iss_uop.fu_code[8], slots_4.io.iss_uop.fu_code[8] \n connect issue_slots[4].iss_uop.fu_code[9], slots_4.io.iss_uop.fu_code[9] \n connect issue_slots[4].iss_uop.iq_type[0], slots_4.io.iss_uop.iq_type[0] \n connect issue_slots[4].iss_uop.iq_type[1], slots_4.io.iss_uop.iq_type[1] \n connect issue_slots[4].iss_uop.iq_type[2], slots_4.io.iss_uop.iq_type[2] \n connect issue_slots[4].iss_uop.iq_type[3], slots_4.io.iss_uop.iq_type[3] \n connect issue_slots[4].iss_uop.debug_pc, slots_4.io.iss_uop.debug_pc \n connect issue_slots[4].iss_uop.is_rvc, slots_4.io.iss_uop.is_rvc \n connect issue_slots[4].iss_uop.debug_inst, slots_4.io.iss_uop.debug_inst \n connect issue_slots[4].iss_uop.inst, slots_4.io.iss_uop.inst \n connect slots_4.io.grant, issue_slots[4].grant \n connect issue_slots[4].request, slots_4.io.request \n connect issue_slots[4].will_be_valid, slots_4.io.will_be_valid \n connect issue_slots[4].valid, slots_4.io.valid \n connect slots_5.io.child_rebusys, issue_slots[5].child_rebusys \n connect slots_5.io.pred_wakeup_port.bits, issue_slots[5].pred_wakeup_port.bits \n connect slots_5.io.pred_wakeup_port.valid, issue_slots[5].pred_wakeup_port.valid \n connect slots_5.io.wakeup_ports[0].bits.rebusy, issue_slots[5].wakeup_ports[0].bits.rebusy \n connect slots_5.io.wakeup_ports[0].bits.speculative_mask, issue_slots[5].wakeup_ports[0].bits.speculative_mask \n connect slots_5.io.wakeup_ports[0].bits.bypassable, issue_slots[5].wakeup_ports[0].bits.bypassable \n connect slots_5.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[5].wakeup_ports[0].bits.uop.debug_tsrc \n connect slots_5.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[5].wakeup_ports[0].bits.uop.debug_fsrc \n connect slots_5.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[5].wakeup_ports[0].bits.uop.bp_xcpt_if \n connect slots_5.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[5].wakeup_ports[0].bits.uop.bp_debug_if \n connect slots_5.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[5].wakeup_ports[0].bits.uop.xcpt_ma_if \n connect slots_5.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[5].wakeup_ports[0].bits.uop.xcpt_ae_if \n connect slots_5.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[5].wakeup_ports[0].bits.uop.xcpt_pf_if \n connect slots_5.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[5].wakeup_ports[0].bits.uop.fp_typ \n connect slots_5.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[5].wakeup_ports[0].bits.uop.fp_rm \n connect slots_5.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[5].wakeup_ports[0].bits.uop.fp_val \n connect slots_5.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[5].wakeup_ports[0].bits.uop.fcn_op \n connect slots_5.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[5].wakeup_ports[0].bits.uop.fcn_dw \n connect slots_5.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[5].wakeup_ports[0].bits.uop.frs3_en \n connect slots_5.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[5].wakeup_ports[0].bits.uop.lrs2_rtype \n connect slots_5.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[5].wakeup_ports[0].bits.uop.lrs1_rtype \n connect slots_5.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[5].wakeup_ports[0].bits.uop.dst_rtype \n connect slots_5.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[5].wakeup_ports[0].bits.uop.lrs3 \n connect slots_5.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[5].wakeup_ports[0].bits.uop.lrs2 \n connect slots_5.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[5].wakeup_ports[0].bits.uop.lrs1 \n connect slots_5.io.wakeup_ports[0].bits.uop.ldst, issue_slots[5].wakeup_ports[0].bits.uop.ldst \n connect slots_5.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[5].wakeup_ports[0].bits.uop.ldst_is_rs1 \n connect slots_5.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[5].wakeup_ports[0].bits.uop.csr_cmd \n connect slots_5.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[5].wakeup_ports[0].bits.uop.flush_on_commit \n connect slots_5.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[5].wakeup_ports[0].bits.uop.is_unique \n connect slots_5.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[5].wakeup_ports[0].bits.uop.uses_stq \n connect slots_5.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[5].wakeup_ports[0].bits.uop.uses_ldq \n connect slots_5.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[5].wakeup_ports[0].bits.uop.mem_signed \n connect slots_5.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[5].wakeup_ports[0].bits.uop.mem_size \n connect slots_5.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[5].wakeup_ports[0].bits.uop.mem_cmd \n connect slots_5.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[5].wakeup_ports[0].bits.uop.exc_cause \n connect slots_5.io.wakeup_ports[0].bits.uop.exception, issue_slots[5].wakeup_ports[0].bits.uop.exception \n connect slots_5.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[5].wakeup_ports[0].bits.uop.stale_pdst \n connect slots_5.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[5].wakeup_ports[0].bits.uop.ppred_busy \n connect slots_5.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[5].wakeup_ports[0].bits.uop.prs3_busy \n connect slots_5.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[5].wakeup_ports[0].bits.uop.prs2_busy \n connect slots_5.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[5].wakeup_ports[0].bits.uop.prs1_busy \n connect slots_5.io.wakeup_ports[0].bits.uop.ppred, issue_slots[5].wakeup_ports[0].bits.uop.ppred \n connect slots_5.io.wakeup_ports[0].bits.uop.prs3, issue_slots[5].wakeup_ports[0].bits.uop.prs3 \n connect slots_5.io.wakeup_ports[0].bits.uop.prs2, issue_slots[5].wakeup_ports[0].bits.uop.prs2 \n connect slots_5.io.wakeup_ports[0].bits.uop.prs1, issue_slots[5].wakeup_ports[0].bits.uop.prs1 \n connect slots_5.io.wakeup_ports[0].bits.uop.pdst, issue_slots[5].wakeup_ports[0].bits.uop.pdst \n connect slots_5.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[5].wakeup_ports[0].bits.uop.rxq_idx \n connect slots_5.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[5].wakeup_ports[0].bits.uop.stq_idx \n connect slots_5.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[5].wakeup_ports[0].bits.uop.ldq_idx \n connect slots_5.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[5].wakeup_ports[0].bits.uop.rob_idx \n connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.vec \n connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.wflags \n connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.sqrt \n connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.div \n connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.fma \n connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe \n connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.toint \n connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.fromint \n connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut \n connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn \n connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.swap23 \n connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.swap12 \n connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.ren3 \n connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.ren2 \n connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.ren1 \n connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.wen \n connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.ldst \n connect slots_5.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[5].wakeup_ports[0].bits.uop.op2_sel \n connect slots_5.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[5].wakeup_ports[0].bits.uop.op1_sel \n connect slots_5.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[5].wakeup_ports[0].bits.uop.imm_packed \n connect slots_5.io.wakeup_ports[0].bits.uop.pimm, issue_slots[5].wakeup_ports[0].bits.uop.pimm \n connect slots_5.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[5].wakeup_ports[0].bits.uop.imm_sel \n connect slots_5.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[5].wakeup_ports[0].bits.uop.imm_rename \n connect slots_5.io.wakeup_ports[0].bits.uop.taken, issue_slots[5].wakeup_ports[0].bits.uop.taken \n connect slots_5.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[5].wakeup_ports[0].bits.uop.pc_lob \n connect slots_5.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[5].wakeup_ports[0].bits.uop.edge_inst \n connect slots_5.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[5].wakeup_ports[0].bits.uop.ftq_idx \n connect slots_5.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[5].wakeup_ports[0].bits.uop.is_mov \n connect slots_5.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[5].wakeup_ports[0].bits.uop.is_rocc \n connect slots_5.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[5].wakeup_ports[0].bits.uop.is_sys_pc2epc \n connect slots_5.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[5].wakeup_ports[0].bits.uop.is_eret \n connect slots_5.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[5].wakeup_ports[0].bits.uop.is_amo \n connect slots_5.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[5].wakeup_ports[0].bits.uop.is_sfence \n connect slots_5.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[5].wakeup_ports[0].bits.uop.is_fencei \n connect slots_5.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[5].wakeup_ports[0].bits.uop.is_fence \n connect slots_5.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[5].wakeup_ports[0].bits.uop.is_sfb \n connect slots_5.io.wakeup_ports[0].bits.uop.br_type, issue_slots[5].wakeup_ports[0].bits.uop.br_type \n connect slots_5.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[5].wakeup_ports[0].bits.uop.br_tag \n connect slots_5.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[5].wakeup_ports[0].bits.uop.br_mask \n connect slots_5.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[5].wakeup_ports[0].bits.uop.dis_col_sel \n connect slots_5.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[5].wakeup_ports[0].bits.uop.iw_p3_bypass_hint \n connect slots_5.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[5].wakeup_ports[0].bits.uop.iw_p2_bypass_hint \n connect slots_5.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[5].wakeup_ports[0].bits.uop.iw_p1_bypass_hint \n connect slots_5.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[5].wakeup_ports[0].bits.uop.iw_p2_speculative_child \n connect slots_5.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[5].wakeup_ports[0].bits.uop.iw_p1_speculative_child \n connect slots_5.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[5].wakeup_ports[0].bits.uop.iw_issued_partial_dgen \n connect slots_5.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[5].wakeup_ports[0].bits.uop.iw_issued_partial_agen \n connect slots_5.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[5].wakeup_ports[0].bits.uop.iw_issued \n connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[0] \n connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[1] \n connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[2] \n connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[3] \n connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[4] \n connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[5] \n connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[6] \n connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[7] \n connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[8] \n connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[9] \n connect slots_5.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[5].wakeup_ports[0].bits.uop.iq_type[0] \n connect slots_5.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[5].wakeup_ports[0].bits.uop.iq_type[1] \n connect slots_5.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[5].wakeup_ports[0].bits.uop.iq_type[2] \n connect slots_5.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[5].wakeup_ports[0].bits.uop.iq_type[3] \n connect slots_5.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[5].wakeup_ports[0].bits.uop.debug_pc \n connect slots_5.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[5].wakeup_ports[0].bits.uop.is_rvc \n connect slots_5.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[5].wakeup_ports[0].bits.uop.debug_inst \n connect slots_5.io.wakeup_ports[0].bits.uop.inst, issue_slots[5].wakeup_ports[0].bits.uop.inst \n connect slots_5.io.wakeup_ports[0].valid, issue_slots[5].wakeup_ports[0].valid \n connect slots_5.io.wakeup_ports[1].bits.rebusy, issue_slots[5].wakeup_ports[1].bits.rebusy \n connect slots_5.io.wakeup_ports[1].bits.speculative_mask, issue_slots[5].wakeup_ports[1].bits.speculative_mask \n connect slots_5.io.wakeup_ports[1].bits.bypassable, issue_slots[5].wakeup_ports[1].bits.bypassable \n connect slots_5.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[5].wakeup_ports[1].bits.uop.debug_tsrc \n connect slots_5.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[5].wakeup_ports[1].bits.uop.debug_fsrc \n connect slots_5.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[5].wakeup_ports[1].bits.uop.bp_xcpt_if \n connect slots_5.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[5].wakeup_ports[1].bits.uop.bp_debug_if \n connect slots_5.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[5].wakeup_ports[1].bits.uop.xcpt_ma_if \n connect slots_5.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[5].wakeup_ports[1].bits.uop.xcpt_ae_if \n connect slots_5.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[5].wakeup_ports[1].bits.uop.xcpt_pf_if \n connect slots_5.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[5].wakeup_ports[1].bits.uop.fp_typ \n connect slots_5.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[5].wakeup_ports[1].bits.uop.fp_rm \n connect slots_5.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[5].wakeup_ports[1].bits.uop.fp_val \n connect slots_5.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[5].wakeup_ports[1].bits.uop.fcn_op \n connect slots_5.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[5].wakeup_ports[1].bits.uop.fcn_dw \n connect slots_5.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[5].wakeup_ports[1].bits.uop.frs3_en \n connect slots_5.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[5].wakeup_ports[1].bits.uop.lrs2_rtype \n connect slots_5.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[5].wakeup_ports[1].bits.uop.lrs1_rtype \n connect slots_5.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[5].wakeup_ports[1].bits.uop.dst_rtype \n connect slots_5.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[5].wakeup_ports[1].bits.uop.lrs3 \n connect slots_5.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[5].wakeup_ports[1].bits.uop.lrs2 \n connect slots_5.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[5].wakeup_ports[1].bits.uop.lrs1 \n connect slots_5.io.wakeup_ports[1].bits.uop.ldst, issue_slots[5].wakeup_ports[1].bits.uop.ldst \n connect slots_5.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[5].wakeup_ports[1].bits.uop.ldst_is_rs1 \n connect slots_5.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[5].wakeup_ports[1].bits.uop.csr_cmd \n connect slots_5.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[5].wakeup_ports[1].bits.uop.flush_on_commit \n connect slots_5.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[5].wakeup_ports[1].bits.uop.is_unique \n connect slots_5.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[5].wakeup_ports[1].bits.uop.uses_stq \n connect slots_5.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[5].wakeup_ports[1].bits.uop.uses_ldq \n connect slots_5.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[5].wakeup_ports[1].bits.uop.mem_signed \n connect slots_5.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[5].wakeup_ports[1].bits.uop.mem_size \n connect slots_5.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[5].wakeup_ports[1].bits.uop.mem_cmd \n connect slots_5.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[5].wakeup_ports[1].bits.uop.exc_cause \n connect slots_5.io.wakeup_ports[1].bits.uop.exception, issue_slots[5].wakeup_ports[1].bits.uop.exception \n connect slots_5.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[5].wakeup_ports[1].bits.uop.stale_pdst \n connect slots_5.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[5].wakeup_ports[1].bits.uop.ppred_busy \n connect slots_5.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[5].wakeup_ports[1].bits.uop.prs3_busy \n connect slots_5.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[5].wakeup_ports[1].bits.uop.prs2_busy \n connect slots_5.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[5].wakeup_ports[1].bits.uop.prs1_busy \n connect slots_5.io.wakeup_ports[1].bits.uop.ppred, issue_slots[5].wakeup_ports[1].bits.uop.ppred \n connect slots_5.io.wakeup_ports[1].bits.uop.prs3, issue_slots[5].wakeup_ports[1].bits.uop.prs3 \n connect slots_5.io.wakeup_ports[1].bits.uop.prs2, issue_slots[5].wakeup_ports[1].bits.uop.prs2 \n connect slots_5.io.wakeup_ports[1].bits.uop.prs1, issue_slots[5].wakeup_ports[1].bits.uop.prs1 \n connect slots_5.io.wakeup_ports[1].bits.uop.pdst, issue_slots[5].wakeup_ports[1].bits.uop.pdst \n connect slots_5.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[5].wakeup_ports[1].bits.uop.rxq_idx \n connect slots_5.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[5].wakeup_ports[1].bits.uop.stq_idx \n connect slots_5.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[5].wakeup_ports[1].bits.uop.ldq_idx \n connect slots_5.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[5].wakeup_ports[1].bits.uop.rob_idx \n connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.vec \n connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.wflags \n connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.sqrt \n connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.div \n connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.fma \n connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe \n connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.toint \n connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.fromint \n connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut \n connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn \n connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.swap23 \n connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.swap12 \n connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.ren3 \n connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.ren2 \n connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.ren1 \n connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.wen \n connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.ldst \n connect slots_5.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[5].wakeup_ports[1].bits.uop.op2_sel \n connect slots_5.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[5].wakeup_ports[1].bits.uop.op1_sel \n connect slots_5.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[5].wakeup_ports[1].bits.uop.imm_packed \n connect slots_5.io.wakeup_ports[1].bits.uop.pimm, issue_slots[5].wakeup_ports[1].bits.uop.pimm \n connect slots_5.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[5].wakeup_ports[1].bits.uop.imm_sel \n connect slots_5.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[5].wakeup_ports[1].bits.uop.imm_rename \n connect slots_5.io.wakeup_ports[1].bits.uop.taken, issue_slots[5].wakeup_ports[1].bits.uop.taken \n connect slots_5.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[5].wakeup_ports[1].bits.uop.pc_lob \n connect slots_5.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[5].wakeup_ports[1].bits.uop.edge_inst \n connect slots_5.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[5].wakeup_ports[1].bits.uop.ftq_idx \n connect slots_5.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[5].wakeup_ports[1].bits.uop.is_mov \n connect slots_5.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[5].wakeup_ports[1].bits.uop.is_rocc \n connect slots_5.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[5].wakeup_ports[1].bits.uop.is_sys_pc2epc \n connect slots_5.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[5].wakeup_ports[1].bits.uop.is_eret \n connect slots_5.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[5].wakeup_ports[1].bits.uop.is_amo \n connect slots_5.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[5].wakeup_ports[1].bits.uop.is_sfence \n connect slots_5.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[5].wakeup_ports[1].bits.uop.is_fencei \n connect slots_5.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[5].wakeup_ports[1].bits.uop.is_fence \n connect slots_5.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[5].wakeup_ports[1].bits.uop.is_sfb \n connect slots_5.io.wakeup_ports[1].bits.uop.br_type, issue_slots[5].wakeup_ports[1].bits.uop.br_type \n connect slots_5.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[5].wakeup_ports[1].bits.uop.br_tag \n connect slots_5.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[5].wakeup_ports[1].bits.uop.br_mask \n connect slots_5.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[5].wakeup_ports[1].bits.uop.dis_col_sel \n connect slots_5.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[5].wakeup_ports[1].bits.uop.iw_p3_bypass_hint \n connect slots_5.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[5].wakeup_ports[1].bits.uop.iw_p2_bypass_hint \n connect slots_5.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[5].wakeup_ports[1].bits.uop.iw_p1_bypass_hint \n connect slots_5.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[5].wakeup_ports[1].bits.uop.iw_p2_speculative_child \n connect slots_5.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[5].wakeup_ports[1].bits.uop.iw_p1_speculative_child \n connect slots_5.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[5].wakeup_ports[1].bits.uop.iw_issued_partial_dgen \n connect slots_5.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[5].wakeup_ports[1].bits.uop.iw_issued_partial_agen \n connect slots_5.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[5].wakeup_ports[1].bits.uop.iw_issued \n connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[0] \n connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[1] \n connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[2] \n connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[3] \n connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[4] \n connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[5] \n connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[6] \n connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[7] \n connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[8] \n connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[9] \n connect slots_5.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[5].wakeup_ports[1].bits.uop.iq_type[0] \n connect slots_5.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[5].wakeup_ports[1].bits.uop.iq_type[1] \n connect slots_5.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[5].wakeup_ports[1].bits.uop.iq_type[2] \n connect slots_5.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[5].wakeup_ports[1].bits.uop.iq_type[3] \n connect slots_5.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[5].wakeup_ports[1].bits.uop.debug_pc \n connect slots_5.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[5].wakeup_ports[1].bits.uop.is_rvc \n connect slots_5.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[5].wakeup_ports[1].bits.uop.debug_inst \n connect slots_5.io.wakeup_ports[1].bits.uop.inst, issue_slots[5].wakeup_ports[1].bits.uop.inst \n connect slots_5.io.wakeup_ports[1].valid, issue_slots[5].wakeup_ports[1].valid \n connect slots_5.io.wakeup_ports[2].bits.rebusy, issue_slots[5].wakeup_ports[2].bits.rebusy \n connect slots_5.io.wakeup_ports[2].bits.speculative_mask, issue_slots[5].wakeup_ports[2].bits.speculative_mask \n connect slots_5.io.wakeup_ports[2].bits.bypassable, issue_slots[5].wakeup_ports[2].bits.bypassable \n connect slots_5.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[5].wakeup_ports[2].bits.uop.debug_tsrc \n connect slots_5.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[5].wakeup_ports[2].bits.uop.debug_fsrc \n connect slots_5.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[5].wakeup_ports[2].bits.uop.bp_xcpt_if \n connect slots_5.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[5].wakeup_ports[2].bits.uop.bp_debug_if \n connect slots_5.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[5].wakeup_ports[2].bits.uop.xcpt_ma_if \n connect slots_5.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[5].wakeup_ports[2].bits.uop.xcpt_ae_if \n connect slots_5.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[5].wakeup_ports[2].bits.uop.xcpt_pf_if \n connect slots_5.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[5].wakeup_ports[2].bits.uop.fp_typ \n connect slots_5.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[5].wakeup_ports[2].bits.uop.fp_rm \n connect slots_5.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[5].wakeup_ports[2].bits.uop.fp_val \n connect slots_5.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[5].wakeup_ports[2].bits.uop.fcn_op \n connect slots_5.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[5].wakeup_ports[2].bits.uop.fcn_dw \n connect slots_5.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[5].wakeup_ports[2].bits.uop.frs3_en \n connect slots_5.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[5].wakeup_ports[2].bits.uop.lrs2_rtype \n connect slots_5.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[5].wakeup_ports[2].bits.uop.lrs1_rtype \n connect slots_5.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[5].wakeup_ports[2].bits.uop.dst_rtype \n connect slots_5.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[5].wakeup_ports[2].bits.uop.lrs3 \n connect slots_5.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[5].wakeup_ports[2].bits.uop.lrs2 \n connect slots_5.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[5].wakeup_ports[2].bits.uop.lrs1 \n connect slots_5.io.wakeup_ports[2].bits.uop.ldst, issue_slots[5].wakeup_ports[2].bits.uop.ldst \n connect slots_5.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[5].wakeup_ports[2].bits.uop.ldst_is_rs1 \n connect slots_5.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[5].wakeup_ports[2].bits.uop.csr_cmd \n connect slots_5.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[5].wakeup_ports[2].bits.uop.flush_on_commit \n connect slots_5.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[5].wakeup_ports[2].bits.uop.is_unique \n connect slots_5.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[5].wakeup_ports[2].bits.uop.uses_stq \n connect slots_5.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[5].wakeup_ports[2].bits.uop.uses_ldq \n connect slots_5.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[5].wakeup_ports[2].bits.uop.mem_signed \n connect slots_5.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[5].wakeup_ports[2].bits.uop.mem_size \n connect slots_5.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[5].wakeup_ports[2].bits.uop.mem_cmd \n connect slots_5.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[5].wakeup_ports[2].bits.uop.exc_cause \n connect slots_5.io.wakeup_ports[2].bits.uop.exception, issue_slots[5].wakeup_ports[2].bits.uop.exception \n connect slots_5.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[5].wakeup_ports[2].bits.uop.stale_pdst \n connect slots_5.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[5].wakeup_ports[2].bits.uop.ppred_busy \n connect slots_5.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[5].wakeup_ports[2].bits.uop.prs3_busy \n connect slots_5.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[5].wakeup_ports[2].bits.uop.prs2_busy \n connect slots_5.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[5].wakeup_ports[2].bits.uop.prs1_busy \n connect slots_5.io.wakeup_ports[2].bits.uop.ppred, issue_slots[5].wakeup_ports[2].bits.uop.ppred \n connect slots_5.io.wakeup_ports[2].bits.uop.prs3, issue_slots[5].wakeup_ports[2].bits.uop.prs3 \n connect slots_5.io.wakeup_ports[2].bits.uop.prs2, issue_slots[5].wakeup_ports[2].bits.uop.prs2 \n connect slots_5.io.wakeup_ports[2].bits.uop.prs1, issue_slots[5].wakeup_ports[2].bits.uop.prs1 \n connect slots_5.io.wakeup_ports[2].bits.uop.pdst, issue_slots[5].wakeup_ports[2].bits.uop.pdst \n connect slots_5.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[5].wakeup_ports[2].bits.uop.rxq_idx \n connect slots_5.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[5].wakeup_ports[2].bits.uop.stq_idx \n connect slots_5.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[5].wakeup_ports[2].bits.uop.ldq_idx \n connect slots_5.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[5].wakeup_ports[2].bits.uop.rob_idx \n connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.vec \n connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.wflags \n connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.sqrt \n connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.div \n connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.fma \n connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe \n connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.toint \n connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.fromint \n connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut \n connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn \n connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.swap23 \n connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.swap12 \n connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.ren3 \n connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.ren2 \n connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.ren1 \n connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.wen \n connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.ldst \n connect slots_5.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[5].wakeup_ports[2].bits.uop.op2_sel \n connect slots_5.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[5].wakeup_ports[2].bits.uop.op1_sel \n connect slots_5.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[5].wakeup_ports[2].bits.uop.imm_packed \n connect slots_5.io.wakeup_ports[2].bits.uop.pimm, issue_slots[5].wakeup_ports[2].bits.uop.pimm \n connect slots_5.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[5].wakeup_ports[2].bits.uop.imm_sel \n connect slots_5.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[5].wakeup_ports[2].bits.uop.imm_rename \n connect slots_5.io.wakeup_ports[2].bits.uop.taken, issue_slots[5].wakeup_ports[2].bits.uop.taken \n connect slots_5.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[5].wakeup_ports[2].bits.uop.pc_lob \n connect slots_5.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[5].wakeup_ports[2].bits.uop.edge_inst \n connect slots_5.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[5].wakeup_ports[2].bits.uop.ftq_idx \n connect slots_5.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[5].wakeup_ports[2].bits.uop.is_mov \n connect slots_5.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[5].wakeup_ports[2].bits.uop.is_rocc \n connect slots_5.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[5].wakeup_ports[2].bits.uop.is_sys_pc2epc \n connect slots_5.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[5].wakeup_ports[2].bits.uop.is_eret \n connect slots_5.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[5].wakeup_ports[2].bits.uop.is_amo \n connect slots_5.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[5].wakeup_ports[2].bits.uop.is_sfence \n connect slots_5.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[5].wakeup_ports[2].bits.uop.is_fencei \n connect slots_5.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[5].wakeup_ports[2].bits.uop.is_fence \n connect slots_5.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[5].wakeup_ports[2].bits.uop.is_sfb \n connect slots_5.io.wakeup_ports[2].bits.uop.br_type, issue_slots[5].wakeup_ports[2].bits.uop.br_type \n connect slots_5.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[5].wakeup_ports[2].bits.uop.br_tag \n connect slots_5.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[5].wakeup_ports[2].bits.uop.br_mask \n connect slots_5.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[5].wakeup_ports[2].bits.uop.dis_col_sel \n connect slots_5.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[5].wakeup_ports[2].bits.uop.iw_p3_bypass_hint \n connect slots_5.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[5].wakeup_ports[2].bits.uop.iw_p2_bypass_hint \n connect slots_5.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[5].wakeup_ports[2].bits.uop.iw_p1_bypass_hint \n connect slots_5.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[5].wakeup_ports[2].bits.uop.iw_p2_speculative_child \n connect slots_5.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[5].wakeup_ports[2].bits.uop.iw_p1_speculative_child \n connect slots_5.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[5].wakeup_ports[2].bits.uop.iw_issued_partial_dgen \n connect slots_5.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[5].wakeup_ports[2].bits.uop.iw_issued_partial_agen \n connect slots_5.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[5].wakeup_ports[2].bits.uop.iw_issued \n connect slots_5.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[5].wakeup_ports[2].bits.uop.fu_code[0] \n connect slots_5.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[5].wakeup_ports[2].bits.uop.fu_code[1] \n connect slots_5.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[5].wakeup_ports[2].bits.uop.fu_code[2] \n connect slots_5.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[5].wakeup_ports[2].bits.uop.fu_code[3] \n connect slots_5.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[5].wakeup_ports[2].bits.uop.fu_code[4] \n connect slots_5.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[5].wakeup_ports[2].bits.uop.fu_code[5] \n connect slots_5.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[5].wakeup_ports[2].bits.uop.fu_code[6] \n connect slots_5.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[5].wakeup_ports[2].bits.uop.fu_code[7] \n connect slots_5.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[5].wakeup_ports[2].bits.uop.fu_code[8] \n connect slots_5.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[5].wakeup_ports[2].bits.uop.fu_code[9] \n connect slots_5.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[5].wakeup_ports[2].bits.uop.iq_type[0] \n connect slots_5.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[5].wakeup_ports[2].bits.uop.iq_type[1] \n connect slots_5.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[5].wakeup_ports[2].bits.uop.iq_type[2] \n connect slots_5.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[5].wakeup_ports[2].bits.uop.iq_type[3] \n connect slots_5.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[5].wakeup_ports[2].bits.uop.debug_pc \n connect slots_5.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[5].wakeup_ports[2].bits.uop.is_rvc \n connect slots_5.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[5].wakeup_ports[2].bits.uop.debug_inst \n connect slots_5.io.wakeup_ports[2].bits.uop.inst, issue_slots[5].wakeup_ports[2].bits.uop.inst \n connect slots_5.io.wakeup_ports[2].valid, issue_slots[5].wakeup_ports[2].valid \n connect slots_5.io.wakeup_ports[3].bits.rebusy, issue_slots[5].wakeup_ports[3].bits.rebusy \n connect slots_5.io.wakeup_ports[3].bits.speculative_mask, issue_slots[5].wakeup_ports[3].bits.speculative_mask \n connect slots_5.io.wakeup_ports[3].bits.bypassable, issue_slots[5].wakeup_ports[3].bits.bypassable \n connect slots_5.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[5].wakeup_ports[3].bits.uop.debug_tsrc \n connect slots_5.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[5].wakeup_ports[3].bits.uop.debug_fsrc \n connect slots_5.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[5].wakeup_ports[3].bits.uop.bp_xcpt_if \n connect slots_5.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[5].wakeup_ports[3].bits.uop.bp_debug_if \n connect slots_5.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[5].wakeup_ports[3].bits.uop.xcpt_ma_if \n connect slots_5.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[5].wakeup_ports[3].bits.uop.xcpt_ae_if \n connect slots_5.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[5].wakeup_ports[3].bits.uop.xcpt_pf_if \n connect slots_5.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[5].wakeup_ports[3].bits.uop.fp_typ \n connect slots_5.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[5].wakeup_ports[3].bits.uop.fp_rm \n connect slots_5.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[5].wakeup_ports[3].bits.uop.fp_val \n connect slots_5.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[5].wakeup_ports[3].bits.uop.fcn_op \n connect slots_5.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[5].wakeup_ports[3].bits.uop.fcn_dw \n connect slots_5.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[5].wakeup_ports[3].bits.uop.frs3_en \n connect slots_5.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[5].wakeup_ports[3].bits.uop.lrs2_rtype \n connect slots_5.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[5].wakeup_ports[3].bits.uop.lrs1_rtype \n connect slots_5.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[5].wakeup_ports[3].bits.uop.dst_rtype \n connect slots_5.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[5].wakeup_ports[3].bits.uop.lrs3 \n connect slots_5.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[5].wakeup_ports[3].bits.uop.lrs2 \n connect slots_5.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[5].wakeup_ports[3].bits.uop.lrs1 \n connect slots_5.io.wakeup_ports[3].bits.uop.ldst, issue_slots[5].wakeup_ports[3].bits.uop.ldst \n connect slots_5.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[5].wakeup_ports[3].bits.uop.ldst_is_rs1 \n connect slots_5.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[5].wakeup_ports[3].bits.uop.csr_cmd \n connect slots_5.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[5].wakeup_ports[3].bits.uop.flush_on_commit \n connect slots_5.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[5].wakeup_ports[3].bits.uop.is_unique \n connect slots_5.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[5].wakeup_ports[3].bits.uop.uses_stq \n connect slots_5.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[5].wakeup_ports[3].bits.uop.uses_ldq \n connect slots_5.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[5].wakeup_ports[3].bits.uop.mem_signed \n connect slots_5.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[5].wakeup_ports[3].bits.uop.mem_size \n connect slots_5.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[5].wakeup_ports[3].bits.uop.mem_cmd \n connect slots_5.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[5].wakeup_ports[3].bits.uop.exc_cause \n connect slots_5.io.wakeup_ports[3].bits.uop.exception, issue_slots[5].wakeup_ports[3].bits.uop.exception \n connect slots_5.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[5].wakeup_ports[3].bits.uop.stale_pdst \n connect slots_5.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[5].wakeup_ports[3].bits.uop.ppred_busy \n connect slots_5.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[5].wakeup_ports[3].bits.uop.prs3_busy \n connect slots_5.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[5].wakeup_ports[3].bits.uop.prs2_busy \n connect slots_5.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[5].wakeup_ports[3].bits.uop.prs1_busy \n connect slots_5.io.wakeup_ports[3].bits.uop.ppred, issue_slots[5].wakeup_ports[3].bits.uop.ppred \n connect slots_5.io.wakeup_ports[3].bits.uop.prs3, issue_slots[5].wakeup_ports[3].bits.uop.prs3 \n connect slots_5.io.wakeup_ports[3].bits.uop.prs2, issue_slots[5].wakeup_ports[3].bits.uop.prs2 \n connect slots_5.io.wakeup_ports[3].bits.uop.prs1, issue_slots[5].wakeup_ports[3].bits.uop.prs1 \n connect slots_5.io.wakeup_ports[3].bits.uop.pdst, issue_slots[5].wakeup_ports[3].bits.uop.pdst \n connect slots_5.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[5].wakeup_ports[3].bits.uop.rxq_idx \n connect slots_5.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[5].wakeup_ports[3].bits.uop.stq_idx \n connect slots_5.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[5].wakeup_ports[3].bits.uop.ldq_idx \n connect slots_5.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[5].wakeup_ports[3].bits.uop.rob_idx \n connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.vec \n connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.wflags \n connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.sqrt \n connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.div \n connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.fma \n connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe \n connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.toint \n connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.fromint \n connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut \n connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn \n connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.swap23 \n connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.swap12 \n connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.ren3 \n connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.ren2 \n connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.ren1 \n connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.wen \n connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.ldst \n connect slots_5.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[5].wakeup_ports[3].bits.uop.op2_sel \n connect slots_5.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[5].wakeup_ports[3].bits.uop.op1_sel \n connect slots_5.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[5].wakeup_ports[3].bits.uop.imm_packed \n connect slots_5.io.wakeup_ports[3].bits.uop.pimm, issue_slots[5].wakeup_ports[3].bits.uop.pimm \n connect slots_5.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[5].wakeup_ports[3].bits.uop.imm_sel \n connect slots_5.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[5].wakeup_ports[3].bits.uop.imm_rename \n connect slots_5.io.wakeup_ports[3].bits.uop.taken, issue_slots[5].wakeup_ports[3].bits.uop.taken \n connect slots_5.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[5].wakeup_ports[3].bits.uop.pc_lob \n connect slots_5.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[5].wakeup_ports[3].bits.uop.edge_inst \n connect slots_5.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[5].wakeup_ports[3].bits.uop.ftq_idx \n connect slots_5.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[5].wakeup_ports[3].bits.uop.is_mov \n connect slots_5.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[5].wakeup_ports[3].bits.uop.is_rocc \n connect slots_5.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[5].wakeup_ports[3].bits.uop.is_sys_pc2epc \n connect slots_5.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[5].wakeup_ports[3].bits.uop.is_eret \n connect slots_5.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[5].wakeup_ports[3].bits.uop.is_amo \n connect slots_5.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[5].wakeup_ports[3].bits.uop.is_sfence \n connect slots_5.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[5].wakeup_ports[3].bits.uop.is_fencei \n connect slots_5.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[5].wakeup_ports[3].bits.uop.is_fence \n connect slots_5.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[5].wakeup_ports[3].bits.uop.is_sfb \n connect slots_5.io.wakeup_ports[3].bits.uop.br_type, issue_slots[5].wakeup_ports[3].bits.uop.br_type \n connect slots_5.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[5].wakeup_ports[3].bits.uop.br_tag \n connect slots_5.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[5].wakeup_ports[3].bits.uop.br_mask \n connect slots_5.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[5].wakeup_ports[3].bits.uop.dis_col_sel \n connect slots_5.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[5].wakeup_ports[3].bits.uop.iw_p3_bypass_hint \n connect slots_5.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[5].wakeup_ports[3].bits.uop.iw_p2_bypass_hint \n connect slots_5.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[5].wakeup_ports[3].bits.uop.iw_p1_bypass_hint \n connect slots_5.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[5].wakeup_ports[3].bits.uop.iw_p2_speculative_child \n connect slots_5.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[5].wakeup_ports[3].bits.uop.iw_p1_speculative_child \n connect slots_5.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[5].wakeup_ports[3].bits.uop.iw_issued_partial_dgen \n connect slots_5.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[5].wakeup_ports[3].bits.uop.iw_issued_partial_agen \n connect slots_5.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[5].wakeup_ports[3].bits.uop.iw_issued \n connect slots_5.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[5].wakeup_ports[3].bits.uop.fu_code[0] \n connect slots_5.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[5].wakeup_ports[3].bits.uop.fu_code[1] \n connect slots_5.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[5].wakeup_ports[3].bits.uop.fu_code[2] \n connect slots_5.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[5].wakeup_ports[3].bits.uop.fu_code[3] \n connect slots_5.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[5].wakeup_ports[3].bits.uop.fu_code[4] \n connect slots_5.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[5].wakeup_ports[3].bits.uop.fu_code[5] \n connect slots_5.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[5].wakeup_ports[3].bits.uop.fu_code[6] \n connect slots_5.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[5].wakeup_ports[3].bits.uop.fu_code[7] \n connect slots_5.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[5].wakeup_ports[3].bits.uop.fu_code[8] \n connect slots_5.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[5].wakeup_ports[3].bits.uop.fu_code[9] \n connect slots_5.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[5].wakeup_ports[3].bits.uop.iq_type[0] \n connect slots_5.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[5].wakeup_ports[3].bits.uop.iq_type[1] \n connect slots_5.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[5].wakeup_ports[3].bits.uop.iq_type[2] \n connect slots_5.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[5].wakeup_ports[3].bits.uop.iq_type[3] \n connect slots_5.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[5].wakeup_ports[3].bits.uop.debug_pc \n connect slots_5.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[5].wakeup_ports[3].bits.uop.is_rvc \n connect slots_5.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[5].wakeup_ports[3].bits.uop.debug_inst \n connect slots_5.io.wakeup_ports[3].bits.uop.inst, issue_slots[5].wakeup_ports[3].bits.uop.inst \n connect slots_5.io.wakeup_ports[3].valid, issue_slots[5].wakeup_ports[3].valid \n connect slots_5.io.squash_grant, issue_slots[5].squash_grant \n connect slots_5.io.clear, issue_slots[5].clear \n connect slots_5.io.kill, issue_slots[5].kill \n connect slots_5.io.brupdate.b2.target_offset, issue_slots[5].brupdate.b2.target_offset \n connect slots_5.io.brupdate.b2.jalr_target, issue_slots[5].brupdate.b2.jalr_target \n connect slots_5.io.brupdate.b2.pc_sel, issue_slots[5].brupdate.b2.pc_sel \n connect slots_5.io.brupdate.b2.cfi_type, issue_slots[5].brupdate.b2.cfi_type \n connect slots_5.io.brupdate.b2.taken, issue_slots[5].brupdate.b2.taken \n connect slots_5.io.brupdate.b2.mispredict, issue_slots[5].brupdate.b2.mispredict \n connect slots_5.io.brupdate.b2.uop.debug_tsrc, issue_slots[5].brupdate.b2.uop.debug_tsrc \n connect slots_5.io.brupdate.b2.uop.debug_fsrc, issue_slots[5].brupdate.b2.uop.debug_fsrc \n connect slots_5.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[5].brupdate.b2.uop.bp_xcpt_if \n connect slots_5.io.brupdate.b2.uop.bp_debug_if, issue_slots[5].brupdate.b2.uop.bp_debug_if \n connect slots_5.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[5].brupdate.b2.uop.xcpt_ma_if \n connect slots_5.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[5].brupdate.b2.uop.xcpt_ae_if \n connect slots_5.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[5].brupdate.b2.uop.xcpt_pf_if \n connect slots_5.io.brupdate.b2.uop.fp_typ, issue_slots[5].brupdate.b2.uop.fp_typ \n connect slots_5.io.brupdate.b2.uop.fp_rm, issue_slots[5].brupdate.b2.uop.fp_rm \n connect slots_5.io.brupdate.b2.uop.fp_val, issue_slots[5].brupdate.b2.uop.fp_val \n connect slots_5.io.brupdate.b2.uop.fcn_op, issue_slots[5].brupdate.b2.uop.fcn_op \n connect slots_5.io.brupdate.b2.uop.fcn_dw, issue_slots[5].brupdate.b2.uop.fcn_dw \n connect slots_5.io.brupdate.b2.uop.frs3_en, issue_slots[5].brupdate.b2.uop.frs3_en \n connect slots_5.io.brupdate.b2.uop.lrs2_rtype, issue_slots[5].brupdate.b2.uop.lrs2_rtype \n connect slots_5.io.brupdate.b2.uop.lrs1_rtype, issue_slots[5].brupdate.b2.uop.lrs1_rtype \n connect slots_5.io.brupdate.b2.uop.dst_rtype, issue_slots[5].brupdate.b2.uop.dst_rtype \n connect slots_5.io.brupdate.b2.uop.lrs3, issue_slots[5].brupdate.b2.uop.lrs3 \n connect slots_5.io.brupdate.b2.uop.lrs2, issue_slots[5].brupdate.b2.uop.lrs2 \n connect slots_5.io.brupdate.b2.uop.lrs1, issue_slots[5].brupdate.b2.uop.lrs1 \n connect slots_5.io.brupdate.b2.uop.ldst, issue_slots[5].brupdate.b2.uop.ldst \n connect slots_5.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[5].brupdate.b2.uop.ldst_is_rs1 \n connect slots_5.io.brupdate.b2.uop.csr_cmd, issue_slots[5].brupdate.b2.uop.csr_cmd \n connect slots_5.io.brupdate.b2.uop.flush_on_commit, issue_slots[5].brupdate.b2.uop.flush_on_commit \n connect slots_5.io.brupdate.b2.uop.is_unique, issue_slots[5].brupdate.b2.uop.is_unique \n connect slots_5.io.brupdate.b2.uop.uses_stq, issue_slots[5].brupdate.b2.uop.uses_stq \n connect slots_5.io.brupdate.b2.uop.uses_ldq, issue_slots[5].brupdate.b2.uop.uses_ldq \n connect slots_5.io.brupdate.b2.uop.mem_signed, issue_slots[5].brupdate.b2.uop.mem_signed \n connect slots_5.io.brupdate.b2.uop.mem_size, issue_slots[5].brupdate.b2.uop.mem_size \n connect slots_5.io.brupdate.b2.uop.mem_cmd, issue_slots[5].brupdate.b2.uop.mem_cmd \n connect slots_5.io.brupdate.b2.uop.exc_cause, issue_slots[5].brupdate.b2.uop.exc_cause \n connect slots_5.io.brupdate.b2.uop.exception, issue_slots[5].brupdate.b2.uop.exception \n connect slots_5.io.brupdate.b2.uop.stale_pdst, issue_slots[5].brupdate.b2.uop.stale_pdst \n connect slots_5.io.brupdate.b2.uop.ppred_busy, issue_slots[5].brupdate.b2.uop.ppred_busy \n connect slots_5.io.brupdate.b2.uop.prs3_busy, issue_slots[5].brupdate.b2.uop.prs3_busy \n connect slots_5.io.brupdate.b2.uop.prs2_busy, issue_slots[5].brupdate.b2.uop.prs2_busy \n connect slots_5.io.brupdate.b2.uop.prs1_busy, issue_slots[5].brupdate.b2.uop.prs1_busy \n connect slots_5.io.brupdate.b2.uop.ppred, issue_slots[5].brupdate.b2.uop.ppred \n connect slots_5.io.brupdate.b2.uop.prs3, issue_slots[5].brupdate.b2.uop.prs3 \n connect slots_5.io.brupdate.b2.uop.prs2, issue_slots[5].brupdate.b2.uop.prs2 \n connect slots_5.io.brupdate.b2.uop.prs1, issue_slots[5].brupdate.b2.uop.prs1 \n connect slots_5.io.brupdate.b2.uop.pdst, issue_slots[5].brupdate.b2.uop.pdst \n connect slots_5.io.brupdate.b2.uop.rxq_idx, issue_slots[5].brupdate.b2.uop.rxq_idx \n connect slots_5.io.brupdate.b2.uop.stq_idx, issue_slots[5].brupdate.b2.uop.stq_idx \n connect slots_5.io.brupdate.b2.uop.ldq_idx, issue_slots[5].brupdate.b2.uop.ldq_idx \n connect slots_5.io.brupdate.b2.uop.rob_idx, issue_slots[5].brupdate.b2.uop.rob_idx \n connect slots_5.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[5].brupdate.b2.uop.fp_ctrl.vec \n connect slots_5.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[5].brupdate.b2.uop.fp_ctrl.wflags \n connect slots_5.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[5].brupdate.b2.uop.fp_ctrl.sqrt \n connect slots_5.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[5].brupdate.b2.uop.fp_ctrl.div \n connect slots_5.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[5].brupdate.b2.uop.fp_ctrl.fma \n connect slots_5.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[5].brupdate.b2.uop.fp_ctrl.fastpipe \n connect slots_5.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[5].brupdate.b2.uop.fp_ctrl.toint \n connect slots_5.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[5].brupdate.b2.uop.fp_ctrl.fromint \n connect slots_5.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[5].brupdate.b2.uop.fp_ctrl.typeTagOut \n connect slots_5.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[5].brupdate.b2.uop.fp_ctrl.typeTagIn \n connect slots_5.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[5].brupdate.b2.uop.fp_ctrl.swap23 \n connect slots_5.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[5].brupdate.b2.uop.fp_ctrl.swap12 \n connect slots_5.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[5].brupdate.b2.uop.fp_ctrl.ren3 \n connect slots_5.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[5].brupdate.b2.uop.fp_ctrl.ren2 \n connect slots_5.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[5].brupdate.b2.uop.fp_ctrl.ren1 \n connect slots_5.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[5].brupdate.b2.uop.fp_ctrl.wen \n connect slots_5.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[5].brupdate.b2.uop.fp_ctrl.ldst \n connect slots_5.io.brupdate.b2.uop.op2_sel, issue_slots[5].brupdate.b2.uop.op2_sel \n connect slots_5.io.brupdate.b2.uop.op1_sel, issue_slots[5].brupdate.b2.uop.op1_sel \n connect slots_5.io.brupdate.b2.uop.imm_packed, issue_slots[5].brupdate.b2.uop.imm_packed \n connect slots_5.io.brupdate.b2.uop.pimm, issue_slots[5].brupdate.b2.uop.pimm \n connect slots_5.io.brupdate.b2.uop.imm_sel, issue_slots[5].brupdate.b2.uop.imm_sel \n connect slots_5.io.brupdate.b2.uop.imm_rename, issue_slots[5].brupdate.b2.uop.imm_rename \n connect slots_5.io.brupdate.b2.uop.taken, issue_slots[5].brupdate.b2.uop.taken \n connect slots_5.io.brupdate.b2.uop.pc_lob, issue_slots[5].brupdate.b2.uop.pc_lob \n connect slots_5.io.brupdate.b2.uop.edge_inst, issue_slots[5].brupdate.b2.uop.edge_inst \n connect slots_5.io.brupdate.b2.uop.ftq_idx, issue_slots[5].brupdate.b2.uop.ftq_idx \n connect slots_5.io.brupdate.b2.uop.is_mov, issue_slots[5].brupdate.b2.uop.is_mov \n connect slots_5.io.brupdate.b2.uop.is_rocc, issue_slots[5].brupdate.b2.uop.is_rocc \n connect slots_5.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[5].brupdate.b2.uop.is_sys_pc2epc \n connect slots_5.io.brupdate.b2.uop.is_eret, issue_slots[5].brupdate.b2.uop.is_eret \n connect slots_5.io.brupdate.b2.uop.is_amo, issue_slots[5].brupdate.b2.uop.is_amo \n connect slots_5.io.brupdate.b2.uop.is_sfence, issue_slots[5].brupdate.b2.uop.is_sfence \n connect slots_5.io.brupdate.b2.uop.is_fencei, issue_slots[5].brupdate.b2.uop.is_fencei \n connect slots_5.io.brupdate.b2.uop.is_fence, issue_slots[5].brupdate.b2.uop.is_fence \n connect slots_5.io.brupdate.b2.uop.is_sfb, issue_slots[5].brupdate.b2.uop.is_sfb \n connect slots_5.io.brupdate.b2.uop.br_type, issue_slots[5].brupdate.b2.uop.br_type \n connect slots_5.io.brupdate.b2.uop.br_tag, issue_slots[5].brupdate.b2.uop.br_tag \n connect slots_5.io.brupdate.b2.uop.br_mask, issue_slots[5].brupdate.b2.uop.br_mask \n connect slots_5.io.brupdate.b2.uop.dis_col_sel, issue_slots[5].brupdate.b2.uop.dis_col_sel \n connect slots_5.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[5].brupdate.b2.uop.iw_p3_bypass_hint \n connect slots_5.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[5].brupdate.b2.uop.iw_p2_bypass_hint \n connect slots_5.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[5].brupdate.b2.uop.iw_p1_bypass_hint \n connect slots_5.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[5].brupdate.b2.uop.iw_p2_speculative_child \n connect slots_5.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[5].brupdate.b2.uop.iw_p1_speculative_child \n connect slots_5.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[5].brupdate.b2.uop.iw_issued_partial_dgen \n connect slots_5.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[5].brupdate.b2.uop.iw_issued_partial_agen \n connect slots_5.io.brupdate.b2.uop.iw_issued, issue_slots[5].brupdate.b2.uop.iw_issued \n connect slots_5.io.brupdate.b2.uop.fu_code[0], issue_slots[5].brupdate.b2.uop.fu_code[0] \n connect slots_5.io.brupdate.b2.uop.fu_code[1], issue_slots[5].brupdate.b2.uop.fu_code[1] \n connect slots_5.io.brupdate.b2.uop.fu_code[2], issue_slots[5].brupdate.b2.uop.fu_code[2] \n connect slots_5.io.brupdate.b2.uop.fu_code[3], issue_slots[5].brupdate.b2.uop.fu_code[3] \n connect slots_5.io.brupdate.b2.uop.fu_code[4], issue_slots[5].brupdate.b2.uop.fu_code[4] \n connect slots_5.io.brupdate.b2.uop.fu_code[5], issue_slots[5].brupdate.b2.uop.fu_code[5] \n connect slots_5.io.brupdate.b2.uop.fu_code[6], issue_slots[5].brupdate.b2.uop.fu_code[6] \n connect slots_5.io.brupdate.b2.uop.fu_code[7], issue_slots[5].brupdate.b2.uop.fu_code[7] \n connect slots_5.io.brupdate.b2.uop.fu_code[8], issue_slots[5].brupdate.b2.uop.fu_code[8] \n connect slots_5.io.brupdate.b2.uop.fu_code[9], issue_slots[5].brupdate.b2.uop.fu_code[9] \n connect slots_5.io.brupdate.b2.uop.iq_type[0], issue_slots[5].brupdate.b2.uop.iq_type[0] \n connect slots_5.io.brupdate.b2.uop.iq_type[1], issue_slots[5].brupdate.b2.uop.iq_type[1] \n connect slots_5.io.brupdate.b2.uop.iq_type[2], issue_slots[5].brupdate.b2.uop.iq_type[2] \n connect slots_5.io.brupdate.b2.uop.iq_type[3], issue_slots[5].brupdate.b2.uop.iq_type[3] \n connect slots_5.io.brupdate.b2.uop.debug_pc, issue_slots[5].brupdate.b2.uop.debug_pc \n connect slots_5.io.brupdate.b2.uop.is_rvc, issue_slots[5].brupdate.b2.uop.is_rvc \n connect slots_5.io.brupdate.b2.uop.debug_inst, issue_slots[5].brupdate.b2.uop.debug_inst \n connect slots_5.io.brupdate.b2.uop.inst, issue_slots[5].brupdate.b2.uop.inst \n connect slots_5.io.brupdate.b1.mispredict_mask, issue_slots[5].brupdate.b1.mispredict_mask \n connect slots_5.io.brupdate.b1.resolve_mask, issue_slots[5].brupdate.b1.resolve_mask \n connect issue_slots[5].out_uop.debug_tsrc, slots_5.io.out_uop.debug_tsrc \n connect issue_slots[5].out_uop.debug_fsrc, slots_5.io.out_uop.debug_fsrc \n connect issue_slots[5].out_uop.bp_xcpt_if, slots_5.io.out_uop.bp_xcpt_if \n connect issue_slots[5].out_uop.bp_debug_if, slots_5.io.out_uop.bp_debug_if \n connect issue_slots[5].out_uop.xcpt_ma_if, slots_5.io.out_uop.xcpt_ma_if \n connect issue_slots[5].out_uop.xcpt_ae_if, slots_5.io.out_uop.xcpt_ae_if \n connect issue_slots[5].out_uop.xcpt_pf_if, slots_5.io.out_uop.xcpt_pf_if \n connect issue_slots[5].out_uop.fp_typ, slots_5.io.out_uop.fp_typ \n connect issue_slots[5].out_uop.fp_rm, slots_5.io.out_uop.fp_rm \n connect issue_slots[5].out_uop.fp_val, slots_5.io.out_uop.fp_val \n connect issue_slots[5].out_uop.fcn_op, slots_5.io.out_uop.fcn_op \n connect issue_slots[5].out_uop.fcn_dw, slots_5.io.out_uop.fcn_dw \n connect issue_slots[5].out_uop.frs3_en, slots_5.io.out_uop.frs3_en \n connect issue_slots[5].out_uop.lrs2_rtype, slots_5.io.out_uop.lrs2_rtype \n connect issue_slots[5].out_uop.lrs1_rtype, slots_5.io.out_uop.lrs1_rtype \n connect issue_slots[5].out_uop.dst_rtype, slots_5.io.out_uop.dst_rtype \n connect issue_slots[5].out_uop.lrs3, slots_5.io.out_uop.lrs3 \n connect issue_slots[5].out_uop.lrs2, slots_5.io.out_uop.lrs2 \n connect issue_slots[5].out_uop.lrs1, slots_5.io.out_uop.lrs1 \n connect issue_slots[5].out_uop.ldst, slots_5.io.out_uop.ldst \n connect issue_slots[5].out_uop.ldst_is_rs1, slots_5.io.out_uop.ldst_is_rs1 \n connect issue_slots[5].out_uop.csr_cmd, slots_5.io.out_uop.csr_cmd \n connect issue_slots[5].out_uop.flush_on_commit, slots_5.io.out_uop.flush_on_commit \n connect issue_slots[5].out_uop.is_unique, slots_5.io.out_uop.is_unique \n connect issue_slots[5].out_uop.uses_stq, slots_5.io.out_uop.uses_stq \n connect issue_slots[5].out_uop.uses_ldq, slots_5.io.out_uop.uses_ldq \n connect issue_slots[5].out_uop.mem_signed, slots_5.io.out_uop.mem_signed \n connect issue_slots[5].out_uop.mem_size, slots_5.io.out_uop.mem_size \n connect issue_slots[5].out_uop.mem_cmd, slots_5.io.out_uop.mem_cmd \n connect issue_slots[5].out_uop.exc_cause, slots_5.io.out_uop.exc_cause \n connect issue_slots[5].out_uop.exception, slots_5.io.out_uop.exception \n connect issue_slots[5].out_uop.stale_pdst, slots_5.io.out_uop.stale_pdst \n connect issue_slots[5].out_uop.ppred_busy, slots_5.io.out_uop.ppred_busy \n connect issue_slots[5].out_uop.prs3_busy, slots_5.io.out_uop.prs3_busy \n connect issue_slots[5].out_uop.prs2_busy, slots_5.io.out_uop.prs2_busy \n connect issue_slots[5].out_uop.prs1_busy, slots_5.io.out_uop.prs1_busy \n connect issue_slots[5].out_uop.ppred, slots_5.io.out_uop.ppred \n connect issue_slots[5].out_uop.prs3, slots_5.io.out_uop.prs3 \n connect issue_slots[5].out_uop.prs2, slots_5.io.out_uop.prs2 \n connect issue_slots[5].out_uop.prs1, slots_5.io.out_uop.prs1 \n connect issue_slots[5].out_uop.pdst, slots_5.io.out_uop.pdst \n connect issue_slots[5].out_uop.rxq_idx, slots_5.io.out_uop.rxq_idx \n connect issue_slots[5].out_uop.stq_idx, slots_5.io.out_uop.stq_idx \n connect issue_slots[5].out_uop.ldq_idx, slots_5.io.out_uop.ldq_idx \n connect issue_slots[5].out_uop.rob_idx, slots_5.io.out_uop.rob_idx \n connect issue_slots[5].out_uop.fp_ctrl.vec, slots_5.io.out_uop.fp_ctrl.vec \n connect issue_slots[5].out_uop.fp_ctrl.wflags, slots_5.io.out_uop.fp_ctrl.wflags \n connect issue_slots[5].out_uop.fp_ctrl.sqrt, slots_5.io.out_uop.fp_ctrl.sqrt \n connect issue_slots[5].out_uop.fp_ctrl.div, slots_5.io.out_uop.fp_ctrl.div \n connect issue_slots[5].out_uop.fp_ctrl.fma, slots_5.io.out_uop.fp_ctrl.fma \n connect issue_slots[5].out_uop.fp_ctrl.fastpipe, slots_5.io.out_uop.fp_ctrl.fastpipe \n connect issue_slots[5].out_uop.fp_ctrl.toint, slots_5.io.out_uop.fp_ctrl.toint \n connect issue_slots[5].out_uop.fp_ctrl.fromint, slots_5.io.out_uop.fp_ctrl.fromint \n connect issue_slots[5].out_uop.fp_ctrl.typeTagOut, slots_5.io.out_uop.fp_ctrl.typeTagOut \n connect issue_slots[5].out_uop.fp_ctrl.typeTagIn, slots_5.io.out_uop.fp_ctrl.typeTagIn \n connect issue_slots[5].out_uop.fp_ctrl.swap23, slots_5.io.out_uop.fp_ctrl.swap23 \n connect issue_slots[5].out_uop.fp_ctrl.swap12, slots_5.io.out_uop.fp_ctrl.swap12 \n connect issue_slots[5].out_uop.fp_ctrl.ren3, slots_5.io.out_uop.fp_ctrl.ren3 \n connect issue_slots[5].out_uop.fp_ctrl.ren2, slots_5.io.out_uop.fp_ctrl.ren2 \n connect issue_slots[5].out_uop.fp_ctrl.ren1, slots_5.io.out_uop.fp_ctrl.ren1 \n connect issue_slots[5].out_uop.fp_ctrl.wen, slots_5.io.out_uop.fp_ctrl.wen \n connect issue_slots[5].out_uop.fp_ctrl.ldst, slots_5.io.out_uop.fp_ctrl.ldst \n connect issue_slots[5].out_uop.op2_sel, slots_5.io.out_uop.op2_sel \n connect issue_slots[5].out_uop.op1_sel, slots_5.io.out_uop.op1_sel \n connect issue_slots[5].out_uop.imm_packed, slots_5.io.out_uop.imm_packed \n connect issue_slots[5].out_uop.pimm, slots_5.io.out_uop.pimm \n connect issue_slots[5].out_uop.imm_sel, slots_5.io.out_uop.imm_sel \n connect issue_slots[5].out_uop.imm_rename, slots_5.io.out_uop.imm_rename \n connect issue_slots[5].out_uop.taken, slots_5.io.out_uop.taken \n connect issue_slots[5].out_uop.pc_lob, slots_5.io.out_uop.pc_lob \n connect issue_slots[5].out_uop.edge_inst, slots_5.io.out_uop.edge_inst \n connect issue_slots[5].out_uop.ftq_idx, slots_5.io.out_uop.ftq_idx \n connect issue_slots[5].out_uop.is_mov, slots_5.io.out_uop.is_mov \n connect issue_slots[5].out_uop.is_rocc, slots_5.io.out_uop.is_rocc \n connect issue_slots[5].out_uop.is_sys_pc2epc, slots_5.io.out_uop.is_sys_pc2epc \n connect issue_slots[5].out_uop.is_eret, slots_5.io.out_uop.is_eret \n connect issue_slots[5].out_uop.is_amo, slots_5.io.out_uop.is_amo \n connect issue_slots[5].out_uop.is_sfence, slots_5.io.out_uop.is_sfence \n connect issue_slots[5].out_uop.is_fencei, slots_5.io.out_uop.is_fencei \n connect issue_slots[5].out_uop.is_fence, slots_5.io.out_uop.is_fence \n connect issue_slots[5].out_uop.is_sfb, slots_5.io.out_uop.is_sfb \n connect issue_slots[5].out_uop.br_type, slots_5.io.out_uop.br_type \n connect issue_slots[5].out_uop.br_tag, slots_5.io.out_uop.br_tag \n connect issue_slots[5].out_uop.br_mask, slots_5.io.out_uop.br_mask \n connect issue_slots[5].out_uop.dis_col_sel, slots_5.io.out_uop.dis_col_sel \n connect issue_slots[5].out_uop.iw_p3_bypass_hint, slots_5.io.out_uop.iw_p3_bypass_hint \n connect issue_slots[5].out_uop.iw_p2_bypass_hint, slots_5.io.out_uop.iw_p2_bypass_hint \n connect issue_slots[5].out_uop.iw_p1_bypass_hint, slots_5.io.out_uop.iw_p1_bypass_hint \n connect issue_slots[5].out_uop.iw_p2_speculative_child, slots_5.io.out_uop.iw_p2_speculative_child \n connect issue_slots[5].out_uop.iw_p1_speculative_child, slots_5.io.out_uop.iw_p1_speculative_child \n connect issue_slots[5].out_uop.iw_issued_partial_dgen, slots_5.io.out_uop.iw_issued_partial_dgen \n connect issue_slots[5].out_uop.iw_issued_partial_agen, slots_5.io.out_uop.iw_issued_partial_agen \n connect issue_slots[5].out_uop.iw_issued, slots_5.io.out_uop.iw_issued \n connect issue_slots[5].out_uop.fu_code[0], slots_5.io.out_uop.fu_code[0] \n connect issue_slots[5].out_uop.fu_code[1], slots_5.io.out_uop.fu_code[1] \n connect issue_slots[5].out_uop.fu_code[2], slots_5.io.out_uop.fu_code[2] \n connect issue_slots[5].out_uop.fu_code[3], slots_5.io.out_uop.fu_code[3] \n connect issue_slots[5].out_uop.fu_code[4], slots_5.io.out_uop.fu_code[4] \n connect issue_slots[5].out_uop.fu_code[5], slots_5.io.out_uop.fu_code[5] \n connect issue_slots[5].out_uop.fu_code[6], slots_5.io.out_uop.fu_code[6] \n connect issue_slots[5].out_uop.fu_code[7], slots_5.io.out_uop.fu_code[7] \n connect issue_slots[5].out_uop.fu_code[8], slots_5.io.out_uop.fu_code[8] \n connect issue_slots[5].out_uop.fu_code[9], slots_5.io.out_uop.fu_code[9] \n connect issue_slots[5].out_uop.iq_type[0], slots_5.io.out_uop.iq_type[0] \n connect issue_slots[5].out_uop.iq_type[1], slots_5.io.out_uop.iq_type[1] \n connect issue_slots[5].out_uop.iq_type[2], slots_5.io.out_uop.iq_type[2] \n connect issue_slots[5].out_uop.iq_type[3], slots_5.io.out_uop.iq_type[3] \n connect issue_slots[5].out_uop.debug_pc, slots_5.io.out_uop.debug_pc \n connect issue_slots[5].out_uop.is_rvc, slots_5.io.out_uop.is_rvc \n connect issue_slots[5].out_uop.debug_inst, slots_5.io.out_uop.debug_inst \n connect issue_slots[5].out_uop.inst, slots_5.io.out_uop.inst \n connect slots_5.io.in_uop.bits.debug_tsrc, issue_slots[5].in_uop.bits.debug_tsrc \n connect slots_5.io.in_uop.bits.debug_fsrc, issue_slots[5].in_uop.bits.debug_fsrc \n connect slots_5.io.in_uop.bits.bp_xcpt_if, issue_slots[5].in_uop.bits.bp_xcpt_if \n connect slots_5.io.in_uop.bits.bp_debug_if, issue_slots[5].in_uop.bits.bp_debug_if \n connect slots_5.io.in_uop.bits.xcpt_ma_if, issue_slots[5].in_uop.bits.xcpt_ma_if \n connect slots_5.io.in_uop.bits.xcpt_ae_if, issue_slots[5].in_uop.bits.xcpt_ae_if \n connect slots_5.io.in_uop.bits.xcpt_pf_if, issue_slots[5].in_uop.bits.xcpt_pf_if \n connect slots_5.io.in_uop.bits.fp_typ, issue_slots[5].in_uop.bits.fp_typ \n connect slots_5.io.in_uop.bits.fp_rm, issue_slots[5].in_uop.bits.fp_rm \n connect slots_5.io.in_uop.bits.fp_val, issue_slots[5].in_uop.bits.fp_val \n connect slots_5.io.in_uop.bits.fcn_op, issue_slots[5].in_uop.bits.fcn_op \n connect slots_5.io.in_uop.bits.fcn_dw, issue_slots[5].in_uop.bits.fcn_dw \n connect slots_5.io.in_uop.bits.frs3_en, issue_slots[5].in_uop.bits.frs3_en \n connect slots_5.io.in_uop.bits.lrs2_rtype, issue_slots[5].in_uop.bits.lrs2_rtype \n connect slots_5.io.in_uop.bits.lrs1_rtype, issue_slots[5].in_uop.bits.lrs1_rtype \n connect slots_5.io.in_uop.bits.dst_rtype, issue_slots[5].in_uop.bits.dst_rtype \n connect slots_5.io.in_uop.bits.lrs3, issue_slots[5].in_uop.bits.lrs3 \n connect slots_5.io.in_uop.bits.lrs2, issue_slots[5].in_uop.bits.lrs2 \n connect slots_5.io.in_uop.bits.lrs1, issue_slots[5].in_uop.bits.lrs1 \n connect slots_5.io.in_uop.bits.ldst, issue_slots[5].in_uop.bits.ldst \n connect slots_5.io.in_uop.bits.ldst_is_rs1, issue_slots[5].in_uop.bits.ldst_is_rs1 \n connect slots_5.io.in_uop.bits.csr_cmd, issue_slots[5].in_uop.bits.csr_cmd \n connect slots_5.io.in_uop.bits.flush_on_commit, issue_slots[5].in_uop.bits.flush_on_commit \n connect slots_5.io.in_uop.bits.is_unique, issue_slots[5].in_uop.bits.is_unique \n connect slots_5.io.in_uop.bits.uses_stq, issue_slots[5].in_uop.bits.uses_stq \n connect slots_5.io.in_uop.bits.uses_ldq, issue_slots[5].in_uop.bits.uses_ldq \n connect slots_5.io.in_uop.bits.mem_signed, issue_slots[5].in_uop.bits.mem_signed \n connect slots_5.io.in_uop.bits.mem_size, issue_slots[5].in_uop.bits.mem_size \n connect slots_5.io.in_uop.bits.mem_cmd, issue_slots[5].in_uop.bits.mem_cmd \n connect slots_5.io.in_uop.bits.exc_cause, issue_slots[5].in_uop.bits.exc_cause \n connect slots_5.io.in_uop.bits.exception, issue_slots[5].in_uop.bits.exception \n connect slots_5.io.in_uop.bits.stale_pdst, issue_slots[5].in_uop.bits.stale_pdst \n connect slots_5.io.in_uop.bits.ppred_busy, issue_slots[5].in_uop.bits.ppred_busy \n connect slots_5.io.in_uop.bits.prs3_busy, issue_slots[5].in_uop.bits.prs3_busy \n connect slots_5.io.in_uop.bits.prs2_busy, issue_slots[5].in_uop.bits.prs2_busy \n connect slots_5.io.in_uop.bits.prs1_busy, issue_slots[5].in_uop.bits.prs1_busy \n connect slots_5.io.in_uop.bits.ppred, issue_slots[5].in_uop.bits.ppred \n connect slots_5.io.in_uop.bits.prs3, issue_slots[5].in_uop.bits.prs3 \n connect slots_5.io.in_uop.bits.prs2, issue_slots[5].in_uop.bits.prs2 \n connect slots_5.io.in_uop.bits.prs1, issue_slots[5].in_uop.bits.prs1 \n connect slots_5.io.in_uop.bits.pdst, issue_slots[5].in_uop.bits.pdst \n connect slots_5.io.in_uop.bits.rxq_idx, issue_slots[5].in_uop.bits.rxq_idx \n connect slots_5.io.in_uop.bits.stq_idx, issue_slots[5].in_uop.bits.stq_idx \n connect slots_5.io.in_uop.bits.ldq_idx, issue_slots[5].in_uop.bits.ldq_idx \n connect slots_5.io.in_uop.bits.rob_idx, issue_slots[5].in_uop.bits.rob_idx \n connect slots_5.io.in_uop.bits.fp_ctrl.vec, issue_slots[5].in_uop.bits.fp_ctrl.vec \n connect slots_5.io.in_uop.bits.fp_ctrl.wflags, issue_slots[5].in_uop.bits.fp_ctrl.wflags \n connect slots_5.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[5].in_uop.bits.fp_ctrl.sqrt \n connect slots_5.io.in_uop.bits.fp_ctrl.div, issue_slots[5].in_uop.bits.fp_ctrl.div \n connect slots_5.io.in_uop.bits.fp_ctrl.fma, issue_slots[5].in_uop.bits.fp_ctrl.fma \n connect slots_5.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[5].in_uop.bits.fp_ctrl.fastpipe \n connect slots_5.io.in_uop.bits.fp_ctrl.toint, issue_slots[5].in_uop.bits.fp_ctrl.toint \n connect slots_5.io.in_uop.bits.fp_ctrl.fromint, issue_slots[5].in_uop.bits.fp_ctrl.fromint \n connect slots_5.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[5].in_uop.bits.fp_ctrl.typeTagOut \n connect slots_5.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[5].in_uop.bits.fp_ctrl.typeTagIn \n connect slots_5.io.in_uop.bits.fp_ctrl.swap23, issue_slots[5].in_uop.bits.fp_ctrl.swap23 \n connect slots_5.io.in_uop.bits.fp_ctrl.swap12, issue_slots[5].in_uop.bits.fp_ctrl.swap12 \n connect slots_5.io.in_uop.bits.fp_ctrl.ren3, issue_slots[5].in_uop.bits.fp_ctrl.ren3 \n connect slots_5.io.in_uop.bits.fp_ctrl.ren2, issue_slots[5].in_uop.bits.fp_ctrl.ren2 \n connect slots_5.io.in_uop.bits.fp_ctrl.ren1, issue_slots[5].in_uop.bits.fp_ctrl.ren1 \n connect slots_5.io.in_uop.bits.fp_ctrl.wen, issue_slots[5].in_uop.bits.fp_ctrl.wen \n connect slots_5.io.in_uop.bits.fp_ctrl.ldst, issue_slots[5].in_uop.bits.fp_ctrl.ldst \n connect slots_5.io.in_uop.bits.op2_sel, issue_slots[5].in_uop.bits.op2_sel \n connect slots_5.io.in_uop.bits.op1_sel, issue_slots[5].in_uop.bits.op1_sel \n connect slots_5.io.in_uop.bits.imm_packed, issue_slots[5].in_uop.bits.imm_packed \n connect slots_5.io.in_uop.bits.pimm, issue_slots[5].in_uop.bits.pimm \n connect slots_5.io.in_uop.bits.imm_sel, issue_slots[5].in_uop.bits.imm_sel \n connect slots_5.io.in_uop.bits.imm_rename, issue_slots[5].in_uop.bits.imm_rename \n connect slots_5.io.in_uop.bits.taken, issue_slots[5].in_uop.bits.taken \n connect slots_5.io.in_uop.bits.pc_lob, issue_slots[5].in_uop.bits.pc_lob \n connect slots_5.io.in_uop.bits.edge_inst, issue_slots[5].in_uop.bits.edge_inst \n connect slots_5.io.in_uop.bits.ftq_idx, issue_slots[5].in_uop.bits.ftq_idx \n connect slots_5.io.in_uop.bits.is_mov, issue_slots[5].in_uop.bits.is_mov \n connect slots_5.io.in_uop.bits.is_rocc, issue_slots[5].in_uop.bits.is_rocc \n connect slots_5.io.in_uop.bits.is_sys_pc2epc, issue_slots[5].in_uop.bits.is_sys_pc2epc \n connect slots_5.io.in_uop.bits.is_eret, issue_slots[5].in_uop.bits.is_eret \n connect slots_5.io.in_uop.bits.is_amo, issue_slots[5].in_uop.bits.is_amo \n connect slots_5.io.in_uop.bits.is_sfence, issue_slots[5].in_uop.bits.is_sfence \n connect slots_5.io.in_uop.bits.is_fencei, issue_slots[5].in_uop.bits.is_fencei \n connect slots_5.io.in_uop.bits.is_fence, issue_slots[5].in_uop.bits.is_fence \n connect slots_5.io.in_uop.bits.is_sfb, issue_slots[5].in_uop.bits.is_sfb \n connect slots_5.io.in_uop.bits.br_type, issue_slots[5].in_uop.bits.br_type \n connect slots_5.io.in_uop.bits.br_tag, issue_slots[5].in_uop.bits.br_tag \n connect slots_5.io.in_uop.bits.br_mask, issue_slots[5].in_uop.bits.br_mask \n connect slots_5.io.in_uop.bits.dis_col_sel, issue_slots[5].in_uop.bits.dis_col_sel \n connect slots_5.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[5].in_uop.bits.iw_p3_bypass_hint \n connect slots_5.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[5].in_uop.bits.iw_p2_bypass_hint \n connect slots_5.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[5].in_uop.bits.iw_p1_bypass_hint \n connect slots_5.io.in_uop.bits.iw_p2_speculative_child, issue_slots[5].in_uop.bits.iw_p2_speculative_child \n connect slots_5.io.in_uop.bits.iw_p1_speculative_child, issue_slots[5].in_uop.bits.iw_p1_speculative_child \n connect slots_5.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[5].in_uop.bits.iw_issued_partial_dgen \n connect slots_5.io.in_uop.bits.iw_issued_partial_agen, issue_slots[5].in_uop.bits.iw_issued_partial_agen \n connect slots_5.io.in_uop.bits.iw_issued, issue_slots[5].in_uop.bits.iw_issued \n connect slots_5.io.in_uop.bits.fu_code[0], issue_slots[5].in_uop.bits.fu_code[0] \n connect slots_5.io.in_uop.bits.fu_code[1], issue_slots[5].in_uop.bits.fu_code[1] \n connect slots_5.io.in_uop.bits.fu_code[2], issue_slots[5].in_uop.bits.fu_code[2] \n connect slots_5.io.in_uop.bits.fu_code[3], issue_slots[5].in_uop.bits.fu_code[3] \n connect slots_5.io.in_uop.bits.fu_code[4], issue_slots[5].in_uop.bits.fu_code[4] \n connect slots_5.io.in_uop.bits.fu_code[5], issue_slots[5].in_uop.bits.fu_code[5] \n connect slots_5.io.in_uop.bits.fu_code[6], issue_slots[5].in_uop.bits.fu_code[6] \n connect slots_5.io.in_uop.bits.fu_code[7], issue_slots[5].in_uop.bits.fu_code[7] \n connect slots_5.io.in_uop.bits.fu_code[8], issue_slots[5].in_uop.bits.fu_code[8] \n connect slots_5.io.in_uop.bits.fu_code[9], issue_slots[5].in_uop.bits.fu_code[9] \n connect slots_5.io.in_uop.bits.iq_type[0], issue_slots[5].in_uop.bits.iq_type[0] \n connect slots_5.io.in_uop.bits.iq_type[1], issue_slots[5].in_uop.bits.iq_type[1] \n connect slots_5.io.in_uop.bits.iq_type[2], issue_slots[5].in_uop.bits.iq_type[2] \n connect slots_5.io.in_uop.bits.iq_type[3], issue_slots[5].in_uop.bits.iq_type[3] \n connect slots_5.io.in_uop.bits.debug_pc, issue_slots[5].in_uop.bits.debug_pc \n connect slots_5.io.in_uop.bits.is_rvc, issue_slots[5].in_uop.bits.is_rvc \n connect slots_5.io.in_uop.bits.debug_inst, issue_slots[5].in_uop.bits.debug_inst \n connect slots_5.io.in_uop.bits.inst, issue_slots[5].in_uop.bits.inst \n connect slots_5.io.in_uop.valid, issue_slots[5].in_uop.valid \n connect issue_slots[5].iss_uop.debug_tsrc, slots_5.io.iss_uop.debug_tsrc \n connect issue_slots[5].iss_uop.debug_fsrc, slots_5.io.iss_uop.debug_fsrc \n connect issue_slots[5].iss_uop.bp_xcpt_if, slots_5.io.iss_uop.bp_xcpt_if \n connect issue_slots[5].iss_uop.bp_debug_if, slots_5.io.iss_uop.bp_debug_if \n connect issue_slots[5].iss_uop.xcpt_ma_if, slots_5.io.iss_uop.xcpt_ma_if \n connect issue_slots[5].iss_uop.xcpt_ae_if, slots_5.io.iss_uop.xcpt_ae_if \n connect issue_slots[5].iss_uop.xcpt_pf_if, slots_5.io.iss_uop.xcpt_pf_if \n connect issue_slots[5].iss_uop.fp_typ, slots_5.io.iss_uop.fp_typ \n connect issue_slots[5].iss_uop.fp_rm, slots_5.io.iss_uop.fp_rm \n connect issue_slots[5].iss_uop.fp_val, slots_5.io.iss_uop.fp_val \n connect issue_slots[5].iss_uop.fcn_op, slots_5.io.iss_uop.fcn_op \n connect issue_slots[5].iss_uop.fcn_dw, slots_5.io.iss_uop.fcn_dw \n connect issue_slots[5].iss_uop.frs3_en, slots_5.io.iss_uop.frs3_en \n connect issue_slots[5].iss_uop.lrs2_rtype, slots_5.io.iss_uop.lrs2_rtype \n connect issue_slots[5].iss_uop.lrs1_rtype, slots_5.io.iss_uop.lrs1_rtype \n connect issue_slots[5].iss_uop.dst_rtype, slots_5.io.iss_uop.dst_rtype \n connect issue_slots[5].iss_uop.lrs3, slots_5.io.iss_uop.lrs3 \n connect issue_slots[5].iss_uop.lrs2, slots_5.io.iss_uop.lrs2 \n connect issue_slots[5].iss_uop.lrs1, slots_5.io.iss_uop.lrs1 \n connect issue_slots[5].iss_uop.ldst, slots_5.io.iss_uop.ldst \n connect issue_slots[5].iss_uop.ldst_is_rs1, slots_5.io.iss_uop.ldst_is_rs1 \n connect issue_slots[5].iss_uop.csr_cmd, slots_5.io.iss_uop.csr_cmd \n connect issue_slots[5].iss_uop.flush_on_commit, slots_5.io.iss_uop.flush_on_commit \n connect issue_slots[5].iss_uop.is_unique, slots_5.io.iss_uop.is_unique \n connect issue_slots[5].iss_uop.uses_stq, slots_5.io.iss_uop.uses_stq \n connect issue_slots[5].iss_uop.uses_ldq, slots_5.io.iss_uop.uses_ldq \n connect issue_slots[5].iss_uop.mem_signed, slots_5.io.iss_uop.mem_signed \n connect issue_slots[5].iss_uop.mem_size, slots_5.io.iss_uop.mem_size \n connect issue_slots[5].iss_uop.mem_cmd, slots_5.io.iss_uop.mem_cmd \n connect issue_slots[5].iss_uop.exc_cause, slots_5.io.iss_uop.exc_cause \n connect issue_slots[5].iss_uop.exception, slots_5.io.iss_uop.exception \n connect issue_slots[5].iss_uop.stale_pdst, slots_5.io.iss_uop.stale_pdst \n connect issue_slots[5].iss_uop.ppred_busy, slots_5.io.iss_uop.ppred_busy \n connect issue_slots[5].iss_uop.prs3_busy, slots_5.io.iss_uop.prs3_busy \n connect issue_slots[5].iss_uop.prs2_busy, slots_5.io.iss_uop.prs2_busy \n connect issue_slots[5].iss_uop.prs1_busy, slots_5.io.iss_uop.prs1_busy \n connect issue_slots[5].iss_uop.ppred, slots_5.io.iss_uop.ppred \n connect issue_slots[5].iss_uop.prs3, slots_5.io.iss_uop.prs3 \n connect issue_slots[5].iss_uop.prs2, slots_5.io.iss_uop.prs2 \n connect issue_slots[5].iss_uop.prs1, slots_5.io.iss_uop.prs1 \n connect issue_slots[5].iss_uop.pdst, slots_5.io.iss_uop.pdst \n connect issue_slots[5].iss_uop.rxq_idx, slots_5.io.iss_uop.rxq_idx \n connect issue_slots[5].iss_uop.stq_idx, slots_5.io.iss_uop.stq_idx \n connect issue_slots[5].iss_uop.ldq_idx, slots_5.io.iss_uop.ldq_idx \n connect issue_slots[5].iss_uop.rob_idx, slots_5.io.iss_uop.rob_idx \n connect issue_slots[5].iss_uop.fp_ctrl.vec, slots_5.io.iss_uop.fp_ctrl.vec \n connect issue_slots[5].iss_uop.fp_ctrl.wflags, slots_5.io.iss_uop.fp_ctrl.wflags \n connect issue_slots[5].iss_uop.fp_ctrl.sqrt, slots_5.io.iss_uop.fp_ctrl.sqrt \n connect issue_slots[5].iss_uop.fp_ctrl.div, slots_5.io.iss_uop.fp_ctrl.div \n connect issue_slots[5].iss_uop.fp_ctrl.fma, slots_5.io.iss_uop.fp_ctrl.fma \n connect issue_slots[5].iss_uop.fp_ctrl.fastpipe, slots_5.io.iss_uop.fp_ctrl.fastpipe \n connect issue_slots[5].iss_uop.fp_ctrl.toint, slots_5.io.iss_uop.fp_ctrl.toint \n connect issue_slots[5].iss_uop.fp_ctrl.fromint, slots_5.io.iss_uop.fp_ctrl.fromint \n connect issue_slots[5].iss_uop.fp_ctrl.typeTagOut, slots_5.io.iss_uop.fp_ctrl.typeTagOut \n connect issue_slots[5].iss_uop.fp_ctrl.typeTagIn, slots_5.io.iss_uop.fp_ctrl.typeTagIn \n connect issue_slots[5].iss_uop.fp_ctrl.swap23, slots_5.io.iss_uop.fp_ctrl.swap23 \n connect issue_slots[5].iss_uop.fp_ctrl.swap12, slots_5.io.iss_uop.fp_ctrl.swap12 \n connect issue_slots[5].iss_uop.fp_ctrl.ren3, slots_5.io.iss_uop.fp_ctrl.ren3 \n connect issue_slots[5].iss_uop.fp_ctrl.ren2, slots_5.io.iss_uop.fp_ctrl.ren2 \n connect issue_slots[5].iss_uop.fp_ctrl.ren1, slots_5.io.iss_uop.fp_ctrl.ren1 \n connect issue_slots[5].iss_uop.fp_ctrl.wen, slots_5.io.iss_uop.fp_ctrl.wen \n connect issue_slots[5].iss_uop.fp_ctrl.ldst, slots_5.io.iss_uop.fp_ctrl.ldst \n connect issue_slots[5].iss_uop.op2_sel, slots_5.io.iss_uop.op2_sel \n connect issue_slots[5].iss_uop.op1_sel, slots_5.io.iss_uop.op1_sel \n connect issue_slots[5].iss_uop.imm_packed, slots_5.io.iss_uop.imm_packed \n connect issue_slots[5].iss_uop.pimm, slots_5.io.iss_uop.pimm \n connect issue_slots[5].iss_uop.imm_sel, slots_5.io.iss_uop.imm_sel \n connect issue_slots[5].iss_uop.imm_rename, slots_5.io.iss_uop.imm_rename \n connect issue_slots[5].iss_uop.taken, slots_5.io.iss_uop.taken \n connect issue_slots[5].iss_uop.pc_lob, slots_5.io.iss_uop.pc_lob \n connect issue_slots[5].iss_uop.edge_inst, slots_5.io.iss_uop.edge_inst \n connect issue_slots[5].iss_uop.ftq_idx, slots_5.io.iss_uop.ftq_idx \n connect issue_slots[5].iss_uop.is_mov, slots_5.io.iss_uop.is_mov \n connect issue_slots[5].iss_uop.is_rocc, slots_5.io.iss_uop.is_rocc \n connect issue_slots[5].iss_uop.is_sys_pc2epc, slots_5.io.iss_uop.is_sys_pc2epc \n connect issue_slots[5].iss_uop.is_eret, slots_5.io.iss_uop.is_eret \n connect issue_slots[5].iss_uop.is_amo, slots_5.io.iss_uop.is_amo \n connect issue_slots[5].iss_uop.is_sfence, slots_5.io.iss_uop.is_sfence \n connect issue_slots[5].iss_uop.is_fencei, slots_5.io.iss_uop.is_fencei \n connect issue_slots[5].iss_uop.is_fence, slots_5.io.iss_uop.is_fence \n connect issue_slots[5].iss_uop.is_sfb, slots_5.io.iss_uop.is_sfb \n connect issue_slots[5].iss_uop.br_type, slots_5.io.iss_uop.br_type \n connect issue_slots[5].iss_uop.br_tag, slots_5.io.iss_uop.br_tag \n connect issue_slots[5].iss_uop.br_mask, slots_5.io.iss_uop.br_mask \n connect issue_slots[5].iss_uop.dis_col_sel, slots_5.io.iss_uop.dis_col_sel \n connect issue_slots[5].iss_uop.iw_p3_bypass_hint, slots_5.io.iss_uop.iw_p3_bypass_hint \n connect issue_slots[5].iss_uop.iw_p2_bypass_hint, slots_5.io.iss_uop.iw_p2_bypass_hint \n connect issue_slots[5].iss_uop.iw_p1_bypass_hint, slots_5.io.iss_uop.iw_p1_bypass_hint \n connect issue_slots[5].iss_uop.iw_p2_speculative_child, slots_5.io.iss_uop.iw_p2_speculative_child \n connect issue_slots[5].iss_uop.iw_p1_speculative_child, slots_5.io.iss_uop.iw_p1_speculative_child \n connect issue_slots[5].iss_uop.iw_issued_partial_dgen, slots_5.io.iss_uop.iw_issued_partial_dgen \n connect issue_slots[5].iss_uop.iw_issued_partial_agen, slots_5.io.iss_uop.iw_issued_partial_agen \n connect issue_slots[5].iss_uop.iw_issued, slots_5.io.iss_uop.iw_issued \n connect issue_slots[5].iss_uop.fu_code[0], slots_5.io.iss_uop.fu_code[0] \n connect issue_slots[5].iss_uop.fu_code[1], slots_5.io.iss_uop.fu_code[1] \n connect issue_slots[5].iss_uop.fu_code[2], slots_5.io.iss_uop.fu_code[2] \n connect issue_slots[5].iss_uop.fu_code[3], slots_5.io.iss_uop.fu_code[3] \n connect issue_slots[5].iss_uop.fu_code[4], slots_5.io.iss_uop.fu_code[4] \n connect issue_slots[5].iss_uop.fu_code[5], slots_5.io.iss_uop.fu_code[5] \n connect issue_slots[5].iss_uop.fu_code[6], slots_5.io.iss_uop.fu_code[6] \n connect issue_slots[5].iss_uop.fu_code[7], slots_5.io.iss_uop.fu_code[7] \n connect issue_slots[5].iss_uop.fu_code[8], slots_5.io.iss_uop.fu_code[8] \n connect issue_slots[5].iss_uop.fu_code[9], slots_5.io.iss_uop.fu_code[9] \n connect issue_slots[5].iss_uop.iq_type[0], slots_5.io.iss_uop.iq_type[0] \n connect issue_slots[5].iss_uop.iq_type[1], slots_5.io.iss_uop.iq_type[1] \n connect issue_slots[5].iss_uop.iq_type[2], slots_5.io.iss_uop.iq_type[2] \n connect issue_slots[5].iss_uop.iq_type[3], slots_5.io.iss_uop.iq_type[3] \n connect issue_slots[5].iss_uop.debug_pc, slots_5.io.iss_uop.debug_pc \n connect issue_slots[5].iss_uop.is_rvc, slots_5.io.iss_uop.is_rvc \n connect issue_slots[5].iss_uop.debug_inst, slots_5.io.iss_uop.debug_inst \n connect issue_slots[5].iss_uop.inst, slots_5.io.iss_uop.inst \n connect slots_5.io.grant, issue_slots[5].grant \n connect issue_slots[5].request, slots_5.io.request \n connect issue_slots[5].will_be_valid, slots_5.io.will_be_valid \n connect issue_slots[5].valid, slots_5.io.valid \n connect slots_6.io.child_rebusys, issue_slots[6].child_rebusys \n connect slots_6.io.pred_wakeup_port.bits, issue_slots[6].pred_wakeup_port.bits \n connect slots_6.io.pred_wakeup_port.valid, issue_slots[6].pred_wakeup_port.valid \n connect slots_6.io.wakeup_ports[0].bits.rebusy, issue_slots[6].wakeup_ports[0].bits.rebusy \n connect slots_6.io.wakeup_ports[0].bits.speculative_mask, issue_slots[6].wakeup_ports[0].bits.speculative_mask \n connect slots_6.io.wakeup_ports[0].bits.bypassable, issue_slots[6].wakeup_ports[0].bits.bypassable \n connect slots_6.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[6].wakeup_ports[0].bits.uop.debug_tsrc \n connect slots_6.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[6].wakeup_ports[0].bits.uop.debug_fsrc \n connect slots_6.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[6].wakeup_ports[0].bits.uop.bp_xcpt_if \n connect slots_6.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[6].wakeup_ports[0].bits.uop.bp_debug_if \n connect slots_6.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[6].wakeup_ports[0].bits.uop.xcpt_ma_if \n connect slots_6.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[6].wakeup_ports[0].bits.uop.xcpt_ae_if \n connect slots_6.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[6].wakeup_ports[0].bits.uop.xcpt_pf_if \n connect slots_6.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[6].wakeup_ports[0].bits.uop.fp_typ \n connect slots_6.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[6].wakeup_ports[0].bits.uop.fp_rm \n connect slots_6.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[6].wakeup_ports[0].bits.uop.fp_val \n connect slots_6.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[6].wakeup_ports[0].bits.uop.fcn_op \n connect slots_6.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[6].wakeup_ports[0].bits.uop.fcn_dw \n connect slots_6.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[6].wakeup_ports[0].bits.uop.frs3_en \n connect slots_6.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[6].wakeup_ports[0].bits.uop.lrs2_rtype \n connect slots_6.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[6].wakeup_ports[0].bits.uop.lrs1_rtype \n connect slots_6.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[6].wakeup_ports[0].bits.uop.dst_rtype \n connect slots_6.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[6].wakeup_ports[0].bits.uop.lrs3 \n connect slots_6.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[6].wakeup_ports[0].bits.uop.lrs2 \n connect slots_6.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[6].wakeup_ports[0].bits.uop.lrs1 \n connect slots_6.io.wakeup_ports[0].bits.uop.ldst, issue_slots[6].wakeup_ports[0].bits.uop.ldst \n connect slots_6.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[6].wakeup_ports[0].bits.uop.ldst_is_rs1 \n connect slots_6.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[6].wakeup_ports[0].bits.uop.csr_cmd \n connect slots_6.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[6].wakeup_ports[0].bits.uop.flush_on_commit \n connect slots_6.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[6].wakeup_ports[0].bits.uop.is_unique \n connect slots_6.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[6].wakeup_ports[0].bits.uop.uses_stq \n connect slots_6.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[6].wakeup_ports[0].bits.uop.uses_ldq \n connect slots_6.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[6].wakeup_ports[0].bits.uop.mem_signed \n connect slots_6.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[6].wakeup_ports[0].bits.uop.mem_size \n connect slots_6.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[6].wakeup_ports[0].bits.uop.mem_cmd \n connect slots_6.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[6].wakeup_ports[0].bits.uop.exc_cause \n connect slots_6.io.wakeup_ports[0].bits.uop.exception, issue_slots[6].wakeup_ports[0].bits.uop.exception \n connect slots_6.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[6].wakeup_ports[0].bits.uop.stale_pdst \n connect slots_6.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[6].wakeup_ports[0].bits.uop.ppred_busy \n connect slots_6.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[6].wakeup_ports[0].bits.uop.prs3_busy \n connect slots_6.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[6].wakeup_ports[0].bits.uop.prs2_busy \n connect slots_6.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[6].wakeup_ports[0].bits.uop.prs1_busy \n connect slots_6.io.wakeup_ports[0].bits.uop.ppred, issue_slots[6].wakeup_ports[0].bits.uop.ppred \n connect slots_6.io.wakeup_ports[0].bits.uop.prs3, issue_slots[6].wakeup_ports[0].bits.uop.prs3 \n connect slots_6.io.wakeup_ports[0].bits.uop.prs2, issue_slots[6].wakeup_ports[0].bits.uop.prs2 \n connect slots_6.io.wakeup_ports[0].bits.uop.prs1, issue_slots[6].wakeup_ports[0].bits.uop.prs1 \n connect slots_6.io.wakeup_ports[0].bits.uop.pdst, issue_slots[6].wakeup_ports[0].bits.uop.pdst \n connect slots_6.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[6].wakeup_ports[0].bits.uop.rxq_idx \n connect slots_6.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[6].wakeup_ports[0].bits.uop.stq_idx \n connect slots_6.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[6].wakeup_ports[0].bits.uop.ldq_idx \n connect slots_6.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[6].wakeup_ports[0].bits.uop.rob_idx \n connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.vec \n connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.wflags \n connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.sqrt \n connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.div \n connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.fma \n connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe \n connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.toint \n connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.fromint \n connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut \n connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn \n connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.swap23 \n connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.swap12 \n connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.ren3 \n connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.ren2 \n connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.ren1 \n connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.wen \n connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.ldst \n connect slots_6.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[6].wakeup_ports[0].bits.uop.op2_sel \n connect slots_6.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[6].wakeup_ports[0].bits.uop.op1_sel \n connect slots_6.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[6].wakeup_ports[0].bits.uop.imm_packed \n connect slots_6.io.wakeup_ports[0].bits.uop.pimm, issue_slots[6].wakeup_ports[0].bits.uop.pimm \n connect slots_6.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[6].wakeup_ports[0].bits.uop.imm_sel \n connect slots_6.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[6].wakeup_ports[0].bits.uop.imm_rename \n connect slots_6.io.wakeup_ports[0].bits.uop.taken, issue_slots[6].wakeup_ports[0].bits.uop.taken \n connect slots_6.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[6].wakeup_ports[0].bits.uop.pc_lob \n connect slots_6.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[6].wakeup_ports[0].bits.uop.edge_inst \n connect slots_6.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[6].wakeup_ports[0].bits.uop.ftq_idx \n connect slots_6.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[6].wakeup_ports[0].bits.uop.is_mov \n connect slots_6.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[6].wakeup_ports[0].bits.uop.is_rocc \n connect slots_6.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[6].wakeup_ports[0].bits.uop.is_sys_pc2epc \n connect slots_6.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[6].wakeup_ports[0].bits.uop.is_eret \n connect slots_6.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[6].wakeup_ports[0].bits.uop.is_amo \n connect slots_6.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[6].wakeup_ports[0].bits.uop.is_sfence \n connect slots_6.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[6].wakeup_ports[0].bits.uop.is_fencei \n connect slots_6.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[6].wakeup_ports[0].bits.uop.is_fence \n connect slots_6.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[6].wakeup_ports[0].bits.uop.is_sfb \n connect slots_6.io.wakeup_ports[0].bits.uop.br_type, issue_slots[6].wakeup_ports[0].bits.uop.br_type \n connect slots_6.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[6].wakeup_ports[0].bits.uop.br_tag \n connect slots_6.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[6].wakeup_ports[0].bits.uop.br_mask \n connect slots_6.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[6].wakeup_ports[0].bits.uop.dis_col_sel \n connect slots_6.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[6].wakeup_ports[0].bits.uop.iw_p3_bypass_hint \n connect slots_6.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[6].wakeup_ports[0].bits.uop.iw_p2_bypass_hint \n connect slots_6.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[6].wakeup_ports[0].bits.uop.iw_p1_bypass_hint \n connect slots_6.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[6].wakeup_ports[0].bits.uop.iw_p2_speculative_child \n connect slots_6.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[6].wakeup_ports[0].bits.uop.iw_p1_speculative_child \n connect slots_6.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[6].wakeup_ports[0].bits.uop.iw_issued_partial_dgen \n connect slots_6.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[6].wakeup_ports[0].bits.uop.iw_issued_partial_agen \n connect slots_6.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[6].wakeup_ports[0].bits.uop.iw_issued \n connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[0] \n connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[1] \n connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[2] \n connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[3] \n connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[4] \n connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[5] \n connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[6] \n connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[7] \n connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[8] \n connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[9] \n connect slots_6.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[6].wakeup_ports[0].bits.uop.iq_type[0] \n connect slots_6.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[6].wakeup_ports[0].bits.uop.iq_type[1] \n connect slots_6.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[6].wakeup_ports[0].bits.uop.iq_type[2] \n connect slots_6.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[6].wakeup_ports[0].bits.uop.iq_type[3] \n connect slots_6.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[6].wakeup_ports[0].bits.uop.debug_pc \n connect slots_6.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[6].wakeup_ports[0].bits.uop.is_rvc \n connect slots_6.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[6].wakeup_ports[0].bits.uop.debug_inst \n connect slots_6.io.wakeup_ports[0].bits.uop.inst, issue_slots[6].wakeup_ports[0].bits.uop.inst \n connect slots_6.io.wakeup_ports[0].valid, issue_slots[6].wakeup_ports[0].valid \n connect slots_6.io.wakeup_ports[1].bits.rebusy, issue_slots[6].wakeup_ports[1].bits.rebusy \n connect slots_6.io.wakeup_ports[1].bits.speculative_mask, issue_slots[6].wakeup_ports[1].bits.speculative_mask \n connect slots_6.io.wakeup_ports[1].bits.bypassable, issue_slots[6].wakeup_ports[1].bits.bypassable \n connect slots_6.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[6].wakeup_ports[1].bits.uop.debug_tsrc \n connect slots_6.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[6].wakeup_ports[1].bits.uop.debug_fsrc \n connect slots_6.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[6].wakeup_ports[1].bits.uop.bp_xcpt_if \n connect slots_6.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[6].wakeup_ports[1].bits.uop.bp_debug_if \n connect slots_6.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[6].wakeup_ports[1].bits.uop.xcpt_ma_if \n connect slots_6.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[6].wakeup_ports[1].bits.uop.xcpt_ae_if \n connect slots_6.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[6].wakeup_ports[1].bits.uop.xcpt_pf_if \n connect slots_6.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[6].wakeup_ports[1].bits.uop.fp_typ \n connect slots_6.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[6].wakeup_ports[1].bits.uop.fp_rm \n connect slots_6.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[6].wakeup_ports[1].bits.uop.fp_val \n connect slots_6.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[6].wakeup_ports[1].bits.uop.fcn_op \n connect slots_6.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[6].wakeup_ports[1].bits.uop.fcn_dw \n connect slots_6.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[6].wakeup_ports[1].bits.uop.frs3_en \n connect slots_6.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[6].wakeup_ports[1].bits.uop.lrs2_rtype \n connect slots_6.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[6].wakeup_ports[1].bits.uop.lrs1_rtype \n connect slots_6.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[6].wakeup_ports[1].bits.uop.dst_rtype \n connect slots_6.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[6].wakeup_ports[1].bits.uop.lrs3 \n connect slots_6.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[6].wakeup_ports[1].bits.uop.lrs2 \n connect slots_6.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[6].wakeup_ports[1].bits.uop.lrs1 \n connect slots_6.io.wakeup_ports[1].bits.uop.ldst, issue_slots[6].wakeup_ports[1].bits.uop.ldst \n connect slots_6.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[6].wakeup_ports[1].bits.uop.ldst_is_rs1 \n connect slots_6.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[6].wakeup_ports[1].bits.uop.csr_cmd \n connect slots_6.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[6].wakeup_ports[1].bits.uop.flush_on_commit \n connect slots_6.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[6].wakeup_ports[1].bits.uop.is_unique \n connect slots_6.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[6].wakeup_ports[1].bits.uop.uses_stq \n connect slots_6.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[6].wakeup_ports[1].bits.uop.uses_ldq \n connect slots_6.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[6].wakeup_ports[1].bits.uop.mem_signed \n connect slots_6.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[6].wakeup_ports[1].bits.uop.mem_size \n connect slots_6.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[6].wakeup_ports[1].bits.uop.mem_cmd \n connect slots_6.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[6].wakeup_ports[1].bits.uop.exc_cause \n connect slots_6.io.wakeup_ports[1].bits.uop.exception, issue_slots[6].wakeup_ports[1].bits.uop.exception \n connect slots_6.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[6].wakeup_ports[1].bits.uop.stale_pdst \n connect slots_6.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[6].wakeup_ports[1].bits.uop.ppred_busy \n connect slots_6.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[6].wakeup_ports[1].bits.uop.prs3_busy \n connect slots_6.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[6].wakeup_ports[1].bits.uop.prs2_busy \n connect slots_6.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[6].wakeup_ports[1].bits.uop.prs1_busy \n connect slots_6.io.wakeup_ports[1].bits.uop.ppred, issue_slots[6].wakeup_ports[1].bits.uop.ppred \n connect slots_6.io.wakeup_ports[1].bits.uop.prs3, issue_slots[6].wakeup_ports[1].bits.uop.prs3 \n connect slots_6.io.wakeup_ports[1].bits.uop.prs2, issue_slots[6].wakeup_ports[1].bits.uop.prs2 \n connect slots_6.io.wakeup_ports[1].bits.uop.prs1, issue_slots[6].wakeup_ports[1].bits.uop.prs1 \n connect slots_6.io.wakeup_ports[1].bits.uop.pdst, issue_slots[6].wakeup_ports[1].bits.uop.pdst \n connect slots_6.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[6].wakeup_ports[1].bits.uop.rxq_idx \n connect slots_6.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[6].wakeup_ports[1].bits.uop.stq_idx \n connect slots_6.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[6].wakeup_ports[1].bits.uop.ldq_idx \n connect slots_6.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[6].wakeup_ports[1].bits.uop.rob_idx \n connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.vec \n connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.wflags \n connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.sqrt \n connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.div \n connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.fma \n connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe \n connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.toint \n connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.fromint \n connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut \n connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn \n connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.swap23 \n connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.swap12 \n connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.ren3 \n connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.ren2 \n connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.ren1 \n connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.wen \n connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.ldst \n connect slots_6.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[6].wakeup_ports[1].bits.uop.op2_sel \n connect slots_6.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[6].wakeup_ports[1].bits.uop.op1_sel \n connect slots_6.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[6].wakeup_ports[1].bits.uop.imm_packed \n connect slots_6.io.wakeup_ports[1].bits.uop.pimm, issue_slots[6].wakeup_ports[1].bits.uop.pimm \n connect slots_6.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[6].wakeup_ports[1].bits.uop.imm_sel \n connect slots_6.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[6].wakeup_ports[1].bits.uop.imm_rename \n connect slots_6.io.wakeup_ports[1].bits.uop.taken, issue_slots[6].wakeup_ports[1].bits.uop.taken \n connect slots_6.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[6].wakeup_ports[1].bits.uop.pc_lob \n connect slots_6.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[6].wakeup_ports[1].bits.uop.edge_inst \n connect slots_6.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[6].wakeup_ports[1].bits.uop.ftq_idx \n connect slots_6.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[6].wakeup_ports[1].bits.uop.is_mov \n connect slots_6.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[6].wakeup_ports[1].bits.uop.is_rocc \n connect slots_6.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[6].wakeup_ports[1].bits.uop.is_sys_pc2epc \n connect slots_6.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[6].wakeup_ports[1].bits.uop.is_eret \n connect slots_6.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[6].wakeup_ports[1].bits.uop.is_amo \n connect slots_6.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[6].wakeup_ports[1].bits.uop.is_sfence \n connect slots_6.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[6].wakeup_ports[1].bits.uop.is_fencei \n connect slots_6.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[6].wakeup_ports[1].bits.uop.is_fence \n connect slots_6.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[6].wakeup_ports[1].bits.uop.is_sfb \n connect slots_6.io.wakeup_ports[1].bits.uop.br_type, issue_slots[6].wakeup_ports[1].bits.uop.br_type \n connect slots_6.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[6].wakeup_ports[1].bits.uop.br_tag \n connect slots_6.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[6].wakeup_ports[1].bits.uop.br_mask \n connect slots_6.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[6].wakeup_ports[1].bits.uop.dis_col_sel \n connect slots_6.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[6].wakeup_ports[1].bits.uop.iw_p3_bypass_hint \n connect slots_6.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[6].wakeup_ports[1].bits.uop.iw_p2_bypass_hint \n connect slots_6.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[6].wakeup_ports[1].bits.uop.iw_p1_bypass_hint \n connect slots_6.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[6].wakeup_ports[1].bits.uop.iw_p2_speculative_child \n connect slots_6.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[6].wakeup_ports[1].bits.uop.iw_p1_speculative_child \n connect slots_6.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[6].wakeup_ports[1].bits.uop.iw_issued_partial_dgen \n connect slots_6.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[6].wakeup_ports[1].bits.uop.iw_issued_partial_agen \n connect slots_6.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[6].wakeup_ports[1].bits.uop.iw_issued \n connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[0] \n connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[1] \n connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[2] \n connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[3] \n connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[4] \n connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[5] \n connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[6] \n connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[7] \n connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[8] \n connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[9] \n connect slots_6.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[6].wakeup_ports[1].bits.uop.iq_type[0] \n connect slots_6.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[6].wakeup_ports[1].bits.uop.iq_type[1] \n connect slots_6.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[6].wakeup_ports[1].bits.uop.iq_type[2] \n connect slots_6.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[6].wakeup_ports[1].bits.uop.iq_type[3] \n connect slots_6.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[6].wakeup_ports[1].bits.uop.debug_pc \n connect slots_6.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[6].wakeup_ports[1].bits.uop.is_rvc \n connect slots_6.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[6].wakeup_ports[1].bits.uop.debug_inst \n connect slots_6.io.wakeup_ports[1].bits.uop.inst, issue_slots[6].wakeup_ports[1].bits.uop.inst \n connect slots_6.io.wakeup_ports[1].valid, issue_slots[6].wakeup_ports[1].valid \n connect slots_6.io.wakeup_ports[2].bits.rebusy, issue_slots[6].wakeup_ports[2].bits.rebusy \n connect slots_6.io.wakeup_ports[2].bits.speculative_mask, issue_slots[6].wakeup_ports[2].bits.speculative_mask \n connect slots_6.io.wakeup_ports[2].bits.bypassable, issue_slots[6].wakeup_ports[2].bits.bypassable \n connect slots_6.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[6].wakeup_ports[2].bits.uop.debug_tsrc \n connect slots_6.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[6].wakeup_ports[2].bits.uop.debug_fsrc \n connect slots_6.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[6].wakeup_ports[2].bits.uop.bp_xcpt_if \n connect slots_6.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[6].wakeup_ports[2].bits.uop.bp_debug_if \n connect slots_6.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[6].wakeup_ports[2].bits.uop.xcpt_ma_if \n connect slots_6.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[6].wakeup_ports[2].bits.uop.xcpt_ae_if \n connect slots_6.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[6].wakeup_ports[2].bits.uop.xcpt_pf_if \n connect slots_6.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[6].wakeup_ports[2].bits.uop.fp_typ \n connect slots_6.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[6].wakeup_ports[2].bits.uop.fp_rm \n connect slots_6.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[6].wakeup_ports[2].bits.uop.fp_val \n connect slots_6.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[6].wakeup_ports[2].bits.uop.fcn_op \n connect slots_6.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[6].wakeup_ports[2].bits.uop.fcn_dw \n connect slots_6.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[6].wakeup_ports[2].bits.uop.frs3_en \n connect slots_6.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[6].wakeup_ports[2].bits.uop.lrs2_rtype \n connect slots_6.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[6].wakeup_ports[2].bits.uop.lrs1_rtype \n connect slots_6.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[6].wakeup_ports[2].bits.uop.dst_rtype \n connect slots_6.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[6].wakeup_ports[2].bits.uop.lrs3 \n connect slots_6.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[6].wakeup_ports[2].bits.uop.lrs2 \n connect slots_6.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[6].wakeup_ports[2].bits.uop.lrs1 \n connect slots_6.io.wakeup_ports[2].bits.uop.ldst, issue_slots[6].wakeup_ports[2].bits.uop.ldst \n connect slots_6.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[6].wakeup_ports[2].bits.uop.ldst_is_rs1 \n connect slots_6.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[6].wakeup_ports[2].bits.uop.csr_cmd \n connect slots_6.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[6].wakeup_ports[2].bits.uop.flush_on_commit \n connect slots_6.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[6].wakeup_ports[2].bits.uop.is_unique \n connect slots_6.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[6].wakeup_ports[2].bits.uop.uses_stq \n connect slots_6.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[6].wakeup_ports[2].bits.uop.uses_ldq \n connect slots_6.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[6].wakeup_ports[2].bits.uop.mem_signed \n connect slots_6.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[6].wakeup_ports[2].bits.uop.mem_size \n connect slots_6.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[6].wakeup_ports[2].bits.uop.mem_cmd \n connect slots_6.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[6].wakeup_ports[2].bits.uop.exc_cause \n connect slots_6.io.wakeup_ports[2].bits.uop.exception, issue_slots[6].wakeup_ports[2].bits.uop.exception \n connect slots_6.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[6].wakeup_ports[2].bits.uop.stale_pdst \n connect slots_6.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[6].wakeup_ports[2].bits.uop.ppred_busy \n connect slots_6.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[6].wakeup_ports[2].bits.uop.prs3_busy \n connect slots_6.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[6].wakeup_ports[2].bits.uop.prs2_busy \n connect slots_6.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[6].wakeup_ports[2].bits.uop.prs1_busy \n connect slots_6.io.wakeup_ports[2].bits.uop.ppred, issue_slots[6].wakeup_ports[2].bits.uop.ppred \n connect slots_6.io.wakeup_ports[2].bits.uop.prs3, issue_slots[6].wakeup_ports[2].bits.uop.prs3 \n connect slots_6.io.wakeup_ports[2].bits.uop.prs2, issue_slots[6].wakeup_ports[2].bits.uop.prs2 \n connect slots_6.io.wakeup_ports[2].bits.uop.prs1, issue_slots[6].wakeup_ports[2].bits.uop.prs1 \n connect slots_6.io.wakeup_ports[2].bits.uop.pdst, issue_slots[6].wakeup_ports[2].bits.uop.pdst \n connect slots_6.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[6].wakeup_ports[2].bits.uop.rxq_idx \n connect slots_6.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[6].wakeup_ports[2].bits.uop.stq_idx \n connect slots_6.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[6].wakeup_ports[2].bits.uop.ldq_idx \n connect slots_6.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[6].wakeup_ports[2].bits.uop.rob_idx \n connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.vec \n connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.wflags \n connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.sqrt \n connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.div \n connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.fma \n connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe \n connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.toint \n connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.fromint \n connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut \n connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn \n connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.swap23 \n connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.swap12 \n connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.ren3 \n connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.ren2 \n connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.ren1 \n connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.wen \n connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.ldst \n connect slots_6.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[6].wakeup_ports[2].bits.uop.op2_sel \n connect slots_6.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[6].wakeup_ports[2].bits.uop.op1_sel \n connect slots_6.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[6].wakeup_ports[2].bits.uop.imm_packed \n connect slots_6.io.wakeup_ports[2].bits.uop.pimm, issue_slots[6].wakeup_ports[2].bits.uop.pimm \n connect slots_6.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[6].wakeup_ports[2].bits.uop.imm_sel \n connect slots_6.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[6].wakeup_ports[2].bits.uop.imm_rename \n connect slots_6.io.wakeup_ports[2].bits.uop.taken, issue_slots[6].wakeup_ports[2].bits.uop.taken \n connect slots_6.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[6].wakeup_ports[2].bits.uop.pc_lob \n connect slots_6.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[6].wakeup_ports[2].bits.uop.edge_inst \n connect slots_6.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[6].wakeup_ports[2].bits.uop.ftq_idx \n connect slots_6.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[6].wakeup_ports[2].bits.uop.is_mov \n connect slots_6.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[6].wakeup_ports[2].bits.uop.is_rocc \n connect slots_6.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[6].wakeup_ports[2].bits.uop.is_sys_pc2epc \n connect slots_6.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[6].wakeup_ports[2].bits.uop.is_eret \n connect slots_6.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[6].wakeup_ports[2].bits.uop.is_amo \n connect slots_6.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[6].wakeup_ports[2].bits.uop.is_sfence \n connect slots_6.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[6].wakeup_ports[2].bits.uop.is_fencei \n connect slots_6.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[6].wakeup_ports[2].bits.uop.is_fence \n connect slots_6.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[6].wakeup_ports[2].bits.uop.is_sfb \n connect slots_6.io.wakeup_ports[2].bits.uop.br_type, issue_slots[6].wakeup_ports[2].bits.uop.br_type \n connect slots_6.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[6].wakeup_ports[2].bits.uop.br_tag \n connect slots_6.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[6].wakeup_ports[2].bits.uop.br_mask \n connect slots_6.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[6].wakeup_ports[2].bits.uop.dis_col_sel \n connect slots_6.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[6].wakeup_ports[2].bits.uop.iw_p3_bypass_hint \n connect slots_6.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[6].wakeup_ports[2].bits.uop.iw_p2_bypass_hint \n connect slots_6.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[6].wakeup_ports[2].bits.uop.iw_p1_bypass_hint \n connect slots_6.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[6].wakeup_ports[2].bits.uop.iw_p2_speculative_child \n connect slots_6.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[6].wakeup_ports[2].bits.uop.iw_p1_speculative_child \n connect slots_6.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[6].wakeup_ports[2].bits.uop.iw_issued_partial_dgen \n connect slots_6.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[6].wakeup_ports[2].bits.uop.iw_issued_partial_agen \n connect slots_6.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[6].wakeup_ports[2].bits.uop.iw_issued \n connect slots_6.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[6].wakeup_ports[2].bits.uop.fu_code[0] \n connect slots_6.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[6].wakeup_ports[2].bits.uop.fu_code[1] \n connect slots_6.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[6].wakeup_ports[2].bits.uop.fu_code[2] \n connect slots_6.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[6].wakeup_ports[2].bits.uop.fu_code[3] \n connect slots_6.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[6].wakeup_ports[2].bits.uop.fu_code[4] \n connect slots_6.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[6].wakeup_ports[2].bits.uop.fu_code[5] \n connect slots_6.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[6].wakeup_ports[2].bits.uop.fu_code[6] \n connect slots_6.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[6].wakeup_ports[2].bits.uop.fu_code[7] \n connect slots_6.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[6].wakeup_ports[2].bits.uop.fu_code[8] \n connect slots_6.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[6].wakeup_ports[2].bits.uop.fu_code[9] \n connect slots_6.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[6].wakeup_ports[2].bits.uop.iq_type[0] \n connect slots_6.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[6].wakeup_ports[2].bits.uop.iq_type[1] \n connect slots_6.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[6].wakeup_ports[2].bits.uop.iq_type[2] \n connect slots_6.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[6].wakeup_ports[2].bits.uop.iq_type[3] \n connect slots_6.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[6].wakeup_ports[2].bits.uop.debug_pc \n connect slots_6.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[6].wakeup_ports[2].bits.uop.is_rvc \n connect slots_6.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[6].wakeup_ports[2].bits.uop.debug_inst \n connect slots_6.io.wakeup_ports[2].bits.uop.inst, issue_slots[6].wakeup_ports[2].bits.uop.inst \n connect slots_6.io.wakeup_ports[2].valid, issue_slots[6].wakeup_ports[2].valid \n connect slots_6.io.wakeup_ports[3].bits.rebusy, issue_slots[6].wakeup_ports[3].bits.rebusy \n connect slots_6.io.wakeup_ports[3].bits.speculative_mask, issue_slots[6].wakeup_ports[3].bits.speculative_mask \n connect slots_6.io.wakeup_ports[3].bits.bypassable, issue_slots[6].wakeup_ports[3].bits.bypassable \n connect slots_6.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[6].wakeup_ports[3].bits.uop.debug_tsrc \n connect slots_6.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[6].wakeup_ports[3].bits.uop.debug_fsrc \n connect slots_6.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[6].wakeup_ports[3].bits.uop.bp_xcpt_if \n connect slots_6.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[6].wakeup_ports[3].bits.uop.bp_debug_if \n connect slots_6.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[6].wakeup_ports[3].bits.uop.xcpt_ma_if \n connect slots_6.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[6].wakeup_ports[3].bits.uop.xcpt_ae_if \n connect slots_6.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[6].wakeup_ports[3].bits.uop.xcpt_pf_if \n connect slots_6.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[6].wakeup_ports[3].bits.uop.fp_typ \n connect slots_6.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[6].wakeup_ports[3].bits.uop.fp_rm \n connect slots_6.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[6].wakeup_ports[3].bits.uop.fp_val \n connect slots_6.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[6].wakeup_ports[3].bits.uop.fcn_op \n connect slots_6.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[6].wakeup_ports[3].bits.uop.fcn_dw \n connect slots_6.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[6].wakeup_ports[3].bits.uop.frs3_en \n connect slots_6.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[6].wakeup_ports[3].bits.uop.lrs2_rtype \n connect slots_6.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[6].wakeup_ports[3].bits.uop.lrs1_rtype \n connect slots_6.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[6].wakeup_ports[3].bits.uop.dst_rtype \n connect slots_6.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[6].wakeup_ports[3].bits.uop.lrs3 \n connect slots_6.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[6].wakeup_ports[3].bits.uop.lrs2 \n connect slots_6.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[6].wakeup_ports[3].bits.uop.lrs1 \n connect slots_6.io.wakeup_ports[3].bits.uop.ldst, issue_slots[6].wakeup_ports[3].bits.uop.ldst \n connect slots_6.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[6].wakeup_ports[3].bits.uop.ldst_is_rs1 \n connect slots_6.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[6].wakeup_ports[3].bits.uop.csr_cmd \n connect slots_6.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[6].wakeup_ports[3].bits.uop.flush_on_commit \n connect slots_6.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[6].wakeup_ports[3].bits.uop.is_unique \n connect slots_6.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[6].wakeup_ports[3].bits.uop.uses_stq \n connect slots_6.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[6].wakeup_ports[3].bits.uop.uses_ldq \n connect slots_6.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[6].wakeup_ports[3].bits.uop.mem_signed \n connect slots_6.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[6].wakeup_ports[3].bits.uop.mem_size \n connect slots_6.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[6].wakeup_ports[3].bits.uop.mem_cmd \n connect slots_6.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[6].wakeup_ports[3].bits.uop.exc_cause \n connect slots_6.io.wakeup_ports[3].bits.uop.exception, issue_slots[6].wakeup_ports[3].bits.uop.exception \n connect slots_6.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[6].wakeup_ports[3].bits.uop.stale_pdst \n connect slots_6.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[6].wakeup_ports[3].bits.uop.ppred_busy \n connect slots_6.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[6].wakeup_ports[3].bits.uop.prs3_busy \n connect slots_6.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[6].wakeup_ports[3].bits.uop.prs2_busy \n connect slots_6.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[6].wakeup_ports[3].bits.uop.prs1_busy \n connect slots_6.io.wakeup_ports[3].bits.uop.ppred, issue_slots[6].wakeup_ports[3].bits.uop.ppred \n connect slots_6.io.wakeup_ports[3].bits.uop.prs3, issue_slots[6].wakeup_ports[3].bits.uop.prs3 \n connect slots_6.io.wakeup_ports[3].bits.uop.prs2, issue_slots[6].wakeup_ports[3].bits.uop.prs2 \n connect slots_6.io.wakeup_ports[3].bits.uop.prs1, issue_slots[6].wakeup_ports[3].bits.uop.prs1 \n connect slots_6.io.wakeup_ports[3].bits.uop.pdst, issue_slots[6].wakeup_ports[3].bits.uop.pdst \n connect slots_6.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[6].wakeup_ports[3].bits.uop.rxq_idx \n connect slots_6.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[6].wakeup_ports[3].bits.uop.stq_idx \n connect slots_6.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[6].wakeup_ports[3].bits.uop.ldq_idx \n connect slots_6.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[6].wakeup_ports[3].bits.uop.rob_idx \n connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.vec \n connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.wflags \n connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.sqrt \n connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.div \n connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.fma \n connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe \n connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.toint \n connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.fromint \n connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut \n connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn \n connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.swap23 \n connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.swap12 \n connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.ren3 \n connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.ren2 \n connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.ren1 \n connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.wen \n connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.ldst \n connect slots_6.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[6].wakeup_ports[3].bits.uop.op2_sel \n connect slots_6.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[6].wakeup_ports[3].bits.uop.op1_sel \n connect slots_6.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[6].wakeup_ports[3].bits.uop.imm_packed \n connect slots_6.io.wakeup_ports[3].bits.uop.pimm, issue_slots[6].wakeup_ports[3].bits.uop.pimm \n connect slots_6.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[6].wakeup_ports[3].bits.uop.imm_sel \n connect slots_6.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[6].wakeup_ports[3].bits.uop.imm_rename \n connect slots_6.io.wakeup_ports[3].bits.uop.taken, issue_slots[6].wakeup_ports[3].bits.uop.taken \n connect slots_6.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[6].wakeup_ports[3].bits.uop.pc_lob \n connect slots_6.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[6].wakeup_ports[3].bits.uop.edge_inst \n connect slots_6.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[6].wakeup_ports[3].bits.uop.ftq_idx \n connect slots_6.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[6].wakeup_ports[3].bits.uop.is_mov \n connect slots_6.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[6].wakeup_ports[3].bits.uop.is_rocc \n connect slots_6.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[6].wakeup_ports[3].bits.uop.is_sys_pc2epc \n connect slots_6.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[6].wakeup_ports[3].bits.uop.is_eret \n connect slots_6.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[6].wakeup_ports[3].bits.uop.is_amo \n connect slots_6.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[6].wakeup_ports[3].bits.uop.is_sfence \n connect slots_6.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[6].wakeup_ports[3].bits.uop.is_fencei \n connect slots_6.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[6].wakeup_ports[3].bits.uop.is_fence \n connect slots_6.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[6].wakeup_ports[3].bits.uop.is_sfb \n connect slots_6.io.wakeup_ports[3].bits.uop.br_type, issue_slots[6].wakeup_ports[3].bits.uop.br_type \n connect slots_6.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[6].wakeup_ports[3].bits.uop.br_tag \n connect slots_6.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[6].wakeup_ports[3].bits.uop.br_mask \n connect slots_6.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[6].wakeup_ports[3].bits.uop.dis_col_sel \n connect slots_6.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[6].wakeup_ports[3].bits.uop.iw_p3_bypass_hint \n connect slots_6.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[6].wakeup_ports[3].bits.uop.iw_p2_bypass_hint \n connect slots_6.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[6].wakeup_ports[3].bits.uop.iw_p1_bypass_hint \n connect slots_6.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[6].wakeup_ports[3].bits.uop.iw_p2_speculative_child \n connect slots_6.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[6].wakeup_ports[3].bits.uop.iw_p1_speculative_child \n connect slots_6.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[6].wakeup_ports[3].bits.uop.iw_issued_partial_dgen \n connect slots_6.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[6].wakeup_ports[3].bits.uop.iw_issued_partial_agen \n connect slots_6.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[6].wakeup_ports[3].bits.uop.iw_issued \n connect slots_6.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[6].wakeup_ports[3].bits.uop.fu_code[0] \n connect slots_6.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[6].wakeup_ports[3].bits.uop.fu_code[1] \n connect slots_6.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[6].wakeup_ports[3].bits.uop.fu_code[2] \n connect slots_6.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[6].wakeup_ports[3].bits.uop.fu_code[3] \n connect slots_6.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[6].wakeup_ports[3].bits.uop.fu_code[4] \n connect slots_6.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[6].wakeup_ports[3].bits.uop.fu_code[5] \n connect slots_6.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[6].wakeup_ports[3].bits.uop.fu_code[6] \n connect slots_6.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[6].wakeup_ports[3].bits.uop.fu_code[7] \n connect slots_6.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[6].wakeup_ports[3].bits.uop.fu_code[8] \n connect slots_6.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[6].wakeup_ports[3].bits.uop.fu_code[9] \n connect slots_6.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[6].wakeup_ports[3].bits.uop.iq_type[0] \n connect slots_6.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[6].wakeup_ports[3].bits.uop.iq_type[1] \n connect slots_6.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[6].wakeup_ports[3].bits.uop.iq_type[2] \n connect slots_6.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[6].wakeup_ports[3].bits.uop.iq_type[3] \n connect slots_6.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[6].wakeup_ports[3].bits.uop.debug_pc \n connect slots_6.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[6].wakeup_ports[3].bits.uop.is_rvc \n connect slots_6.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[6].wakeup_ports[3].bits.uop.debug_inst \n connect slots_6.io.wakeup_ports[3].bits.uop.inst, issue_slots[6].wakeup_ports[3].bits.uop.inst \n connect slots_6.io.wakeup_ports[3].valid, issue_slots[6].wakeup_ports[3].valid \n connect slots_6.io.squash_grant, issue_slots[6].squash_grant \n connect slots_6.io.clear, issue_slots[6].clear \n connect slots_6.io.kill, issue_slots[6].kill \n connect slots_6.io.brupdate.b2.target_offset, issue_slots[6].brupdate.b2.target_offset \n connect slots_6.io.brupdate.b2.jalr_target, issue_slots[6].brupdate.b2.jalr_target \n connect slots_6.io.brupdate.b2.pc_sel, issue_slots[6].brupdate.b2.pc_sel \n connect slots_6.io.brupdate.b2.cfi_type, issue_slots[6].brupdate.b2.cfi_type \n connect slots_6.io.brupdate.b2.taken, issue_slots[6].brupdate.b2.taken \n connect slots_6.io.brupdate.b2.mispredict, issue_slots[6].brupdate.b2.mispredict \n connect slots_6.io.brupdate.b2.uop.debug_tsrc, issue_slots[6].brupdate.b2.uop.debug_tsrc \n connect slots_6.io.brupdate.b2.uop.debug_fsrc, issue_slots[6].brupdate.b2.uop.debug_fsrc \n connect slots_6.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[6].brupdate.b2.uop.bp_xcpt_if \n connect slots_6.io.brupdate.b2.uop.bp_debug_if, issue_slots[6].brupdate.b2.uop.bp_debug_if \n connect slots_6.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[6].brupdate.b2.uop.xcpt_ma_if \n connect slots_6.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[6].brupdate.b2.uop.xcpt_ae_if \n connect slots_6.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[6].brupdate.b2.uop.xcpt_pf_if \n connect slots_6.io.brupdate.b2.uop.fp_typ, issue_slots[6].brupdate.b2.uop.fp_typ \n connect slots_6.io.brupdate.b2.uop.fp_rm, issue_slots[6].brupdate.b2.uop.fp_rm \n connect slots_6.io.brupdate.b2.uop.fp_val, issue_slots[6].brupdate.b2.uop.fp_val \n connect slots_6.io.brupdate.b2.uop.fcn_op, issue_slots[6].brupdate.b2.uop.fcn_op \n connect slots_6.io.brupdate.b2.uop.fcn_dw, issue_slots[6].brupdate.b2.uop.fcn_dw \n connect slots_6.io.brupdate.b2.uop.frs3_en, issue_slots[6].brupdate.b2.uop.frs3_en \n connect slots_6.io.brupdate.b2.uop.lrs2_rtype, issue_slots[6].brupdate.b2.uop.lrs2_rtype \n connect slots_6.io.brupdate.b2.uop.lrs1_rtype, issue_slots[6].brupdate.b2.uop.lrs1_rtype \n connect slots_6.io.brupdate.b2.uop.dst_rtype, issue_slots[6].brupdate.b2.uop.dst_rtype \n connect slots_6.io.brupdate.b2.uop.lrs3, issue_slots[6].brupdate.b2.uop.lrs3 \n connect slots_6.io.brupdate.b2.uop.lrs2, issue_slots[6].brupdate.b2.uop.lrs2 \n connect slots_6.io.brupdate.b2.uop.lrs1, issue_slots[6].brupdate.b2.uop.lrs1 \n connect slots_6.io.brupdate.b2.uop.ldst, issue_slots[6].brupdate.b2.uop.ldst \n connect slots_6.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[6].brupdate.b2.uop.ldst_is_rs1 \n connect slots_6.io.brupdate.b2.uop.csr_cmd, issue_slots[6].brupdate.b2.uop.csr_cmd \n connect slots_6.io.brupdate.b2.uop.flush_on_commit, issue_slots[6].brupdate.b2.uop.flush_on_commit \n connect slots_6.io.brupdate.b2.uop.is_unique, issue_slots[6].brupdate.b2.uop.is_unique \n connect slots_6.io.brupdate.b2.uop.uses_stq, issue_slots[6].brupdate.b2.uop.uses_stq \n connect slots_6.io.brupdate.b2.uop.uses_ldq, issue_slots[6].brupdate.b2.uop.uses_ldq \n connect slots_6.io.brupdate.b2.uop.mem_signed, issue_slots[6].brupdate.b2.uop.mem_signed \n connect slots_6.io.brupdate.b2.uop.mem_size, issue_slots[6].brupdate.b2.uop.mem_size \n connect slots_6.io.brupdate.b2.uop.mem_cmd, issue_slots[6].brupdate.b2.uop.mem_cmd \n connect slots_6.io.brupdate.b2.uop.exc_cause, issue_slots[6].brupdate.b2.uop.exc_cause \n connect slots_6.io.brupdate.b2.uop.exception, issue_slots[6].brupdate.b2.uop.exception \n connect slots_6.io.brupdate.b2.uop.stale_pdst, issue_slots[6].brupdate.b2.uop.stale_pdst \n connect slots_6.io.brupdate.b2.uop.ppred_busy, issue_slots[6].brupdate.b2.uop.ppred_busy \n connect slots_6.io.brupdate.b2.uop.prs3_busy, issue_slots[6].brupdate.b2.uop.prs3_busy \n connect slots_6.io.brupdate.b2.uop.prs2_busy, issue_slots[6].brupdate.b2.uop.prs2_busy \n connect slots_6.io.brupdate.b2.uop.prs1_busy, issue_slots[6].brupdate.b2.uop.prs1_busy \n connect slots_6.io.brupdate.b2.uop.ppred, issue_slots[6].brupdate.b2.uop.ppred \n connect slots_6.io.brupdate.b2.uop.prs3, issue_slots[6].brupdate.b2.uop.prs3 \n connect slots_6.io.brupdate.b2.uop.prs2, issue_slots[6].brupdate.b2.uop.prs2 \n connect slots_6.io.brupdate.b2.uop.prs1, issue_slots[6].brupdate.b2.uop.prs1 \n connect slots_6.io.brupdate.b2.uop.pdst, issue_slots[6].brupdate.b2.uop.pdst \n connect slots_6.io.brupdate.b2.uop.rxq_idx, issue_slots[6].brupdate.b2.uop.rxq_idx \n connect slots_6.io.brupdate.b2.uop.stq_idx, issue_slots[6].brupdate.b2.uop.stq_idx \n connect slots_6.io.brupdate.b2.uop.ldq_idx, issue_slots[6].brupdate.b2.uop.ldq_idx \n connect slots_6.io.brupdate.b2.uop.rob_idx, issue_slots[6].brupdate.b2.uop.rob_idx \n connect slots_6.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[6].brupdate.b2.uop.fp_ctrl.vec \n connect slots_6.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[6].brupdate.b2.uop.fp_ctrl.wflags \n connect slots_6.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[6].brupdate.b2.uop.fp_ctrl.sqrt \n connect slots_6.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[6].brupdate.b2.uop.fp_ctrl.div \n connect slots_6.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[6].brupdate.b2.uop.fp_ctrl.fma \n connect slots_6.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[6].brupdate.b2.uop.fp_ctrl.fastpipe \n connect slots_6.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[6].brupdate.b2.uop.fp_ctrl.toint \n connect slots_6.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[6].brupdate.b2.uop.fp_ctrl.fromint \n connect slots_6.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[6].brupdate.b2.uop.fp_ctrl.typeTagOut \n connect slots_6.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[6].brupdate.b2.uop.fp_ctrl.typeTagIn \n connect slots_6.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[6].brupdate.b2.uop.fp_ctrl.swap23 \n connect slots_6.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[6].brupdate.b2.uop.fp_ctrl.swap12 \n connect slots_6.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[6].brupdate.b2.uop.fp_ctrl.ren3 \n connect slots_6.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[6].brupdate.b2.uop.fp_ctrl.ren2 \n connect slots_6.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[6].brupdate.b2.uop.fp_ctrl.ren1 \n connect slots_6.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[6].brupdate.b2.uop.fp_ctrl.wen \n connect slots_6.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[6].brupdate.b2.uop.fp_ctrl.ldst \n connect slots_6.io.brupdate.b2.uop.op2_sel, issue_slots[6].brupdate.b2.uop.op2_sel \n connect slots_6.io.brupdate.b2.uop.op1_sel, issue_slots[6].brupdate.b2.uop.op1_sel \n connect slots_6.io.brupdate.b2.uop.imm_packed, issue_slots[6].brupdate.b2.uop.imm_packed \n connect slots_6.io.brupdate.b2.uop.pimm, issue_slots[6].brupdate.b2.uop.pimm \n connect slots_6.io.brupdate.b2.uop.imm_sel, issue_slots[6].brupdate.b2.uop.imm_sel \n connect slots_6.io.brupdate.b2.uop.imm_rename, issue_slots[6].brupdate.b2.uop.imm_rename \n connect slots_6.io.brupdate.b2.uop.taken, issue_slots[6].brupdate.b2.uop.taken \n connect slots_6.io.brupdate.b2.uop.pc_lob, issue_slots[6].brupdate.b2.uop.pc_lob \n connect slots_6.io.brupdate.b2.uop.edge_inst, issue_slots[6].brupdate.b2.uop.edge_inst \n connect slots_6.io.brupdate.b2.uop.ftq_idx, issue_slots[6].brupdate.b2.uop.ftq_idx \n connect slots_6.io.brupdate.b2.uop.is_mov, issue_slots[6].brupdate.b2.uop.is_mov \n connect slots_6.io.brupdate.b2.uop.is_rocc, issue_slots[6].brupdate.b2.uop.is_rocc \n connect slots_6.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[6].brupdate.b2.uop.is_sys_pc2epc \n connect slots_6.io.brupdate.b2.uop.is_eret, issue_slots[6].brupdate.b2.uop.is_eret \n connect slots_6.io.brupdate.b2.uop.is_amo, issue_slots[6].brupdate.b2.uop.is_amo \n connect slots_6.io.brupdate.b2.uop.is_sfence, issue_slots[6].brupdate.b2.uop.is_sfence \n connect slots_6.io.brupdate.b2.uop.is_fencei, issue_slots[6].brupdate.b2.uop.is_fencei \n connect slots_6.io.brupdate.b2.uop.is_fence, issue_slots[6].brupdate.b2.uop.is_fence \n connect slots_6.io.brupdate.b2.uop.is_sfb, issue_slots[6].brupdate.b2.uop.is_sfb \n connect slots_6.io.brupdate.b2.uop.br_type, issue_slots[6].brupdate.b2.uop.br_type \n connect slots_6.io.brupdate.b2.uop.br_tag, issue_slots[6].brupdate.b2.uop.br_tag \n connect slots_6.io.brupdate.b2.uop.br_mask, issue_slots[6].brupdate.b2.uop.br_mask \n connect slots_6.io.brupdate.b2.uop.dis_col_sel, issue_slots[6].brupdate.b2.uop.dis_col_sel \n connect slots_6.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[6].brupdate.b2.uop.iw_p3_bypass_hint \n connect slots_6.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[6].brupdate.b2.uop.iw_p2_bypass_hint \n connect slots_6.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[6].brupdate.b2.uop.iw_p1_bypass_hint \n connect slots_6.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[6].brupdate.b2.uop.iw_p2_speculative_child \n connect slots_6.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[6].brupdate.b2.uop.iw_p1_speculative_child \n connect slots_6.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[6].brupdate.b2.uop.iw_issued_partial_dgen \n connect slots_6.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[6].brupdate.b2.uop.iw_issued_partial_agen \n connect slots_6.io.brupdate.b2.uop.iw_issued, issue_slots[6].brupdate.b2.uop.iw_issued \n connect slots_6.io.brupdate.b2.uop.fu_code[0], issue_slots[6].brupdate.b2.uop.fu_code[0] \n connect slots_6.io.brupdate.b2.uop.fu_code[1], issue_slots[6].brupdate.b2.uop.fu_code[1] \n connect slots_6.io.brupdate.b2.uop.fu_code[2], issue_slots[6].brupdate.b2.uop.fu_code[2] \n connect slots_6.io.brupdate.b2.uop.fu_code[3], issue_slots[6].brupdate.b2.uop.fu_code[3] \n connect slots_6.io.brupdate.b2.uop.fu_code[4], issue_slots[6].brupdate.b2.uop.fu_code[4] \n connect slots_6.io.brupdate.b2.uop.fu_code[5], issue_slots[6].brupdate.b2.uop.fu_code[5] \n connect slots_6.io.brupdate.b2.uop.fu_code[6], issue_slots[6].brupdate.b2.uop.fu_code[6] \n connect slots_6.io.brupdate.b2.uop.fu_code[7], issue_slots[6].brupdate.b2.uop.fu_code[7] \n connect slots_6.io.brupdate.b2.uop.fu_code[8], issue_slots[6].brupdate.b2.uop.fu_code[8] \n connect slots_6.io.brupdate.b2.uop.fu_code[9], issue_slots[6].brupdate.b2.uop.fu_code[9] \n connect slots_6.io.brupdate.b2.uop.iq_type[0], issue_slots[6].brupdate.b2.uop.iq_type[0] \n connect slots_6.io.brupdate.b2.uop.iq_type[1], issue_slots[6].brupdate.b2.uop.iq_type[1] \n connect slots_6.io.brupdate.b2.uop.iq_type[2], issue_slots[6].brupdate.b2.uop.iq_type[2] \n connect slots_6.io.brupdate.b2.uop.iq_type[3], issue_slots[6].brupdate.b2.uop.iq_type[3] \n connect slots_6.io.brupdate.b2.uop.debug_pc, issue_slots[6].brupdate.b2.uop.debug_pc \n connect slots_6.io.brupdate.b2.uop.is_rvc, issue_slots[6].brupdate.b2.uop.is_rvc \n connect slots_6.io.brupdate.b2.uop.debug_inst, issue_slots[6].brupdate.b2.uop.debug_inst \n connect slots_6.io.brupdate.b2.uop.inst, issue_slots[6].brupdate.b2.uop.inst \n connect slots_6.io.brupdate.b1.mispredict_mask, issue_slots[6].brupdate.b1.mispredict_mask \n connect slots_6.io.brupdate.b1.resolve_mask, issue_slots[6].brupdate.b1.resolve_mask \n connect issue_slots[6].out_uop.debug_tsrc, slots_6.io.out_uop.debug_tsrc \n connect issue_slots[6].out_uop.debug_fsrc, slots_6.io.out_uop.debug_fsrc \n connect issue_slots[6].out_uop.bp_xcpt_if, slots_6.io.out_uop.bp_xcpt_if \n connect issue_slots[6].out_uop.bp_debug_if, slots_6.io.out_uop.bp_debug_if \n connect issue_slots[6].out_uop.xcpt_ma_if, slots_6.io.out_uop.xcpt_ma_if \n connect issue_slots[6].out_uop.xcpt_ae_if, slots_6.io.out_uop.xcpt_ae_if \n connect issue_slots[6].out_uop.xcpt_pf_if, slots_6.io.out_uop.xcpt_pf_if \n connect issue_slots[6].out_uop.fp_typ, slots_6.io.out_uop.fp_typ \n connect issue_slots[6].out_uop.fp_rm, slots_6.io.out_uop.fp_rm \n connect issue_slots[6].out_uop.fp_val, slots_6.io.out_uop.fp_val \n connect issue_slots[6].out_uop.fcn_op, slots_6.io.out_uop.fcn_op \n connect issue_slots[6].out_uop.fcn_dw, slots_6.io.out_uop.fcn_dw \n connect issue_slots[6].out_uop.frs3_en, slots_6.io.out_uop.frs3_en \n connect issue_slots[6].out_uop.lrs2_rtype, slots_6.io.out_uop.lrs2_rtype \n connect issue_slots[6].out_uop.lrs1_rtype, slots_6.io.out_uop.lrs1_rtype \n connect issue_slots[6].out_uop.dst_rtype, slots_6.io.out_uop.dst_rtype \n connect issue_slots[6].out_uop.lrs3, slots_6.io.out_uop.lrs3 \n connect issue_slots[6].out_uop.lrs2, slots_6.io.out_uop.lrs2 \n connect issue_slots[6].out_uop.lrs1, slots_6.io.out_uop.lrs1 \n connect issue_slots[6].out_uop.ldst, slots_6.io.out_uop.ldst \n connect issue_slots[6].out_uop.ldst_is_rs1, slots_6.io.out_uop.ldst_is_rs1 \n connect issue_slots[6].out_uop.csr_cmd, slots_6.io.out_uop.csr_cmd \n connect issue_slots[6].out_uop.flush_on_commit, slots_6.io.out_uop.flush_on_commit \n connect issue_slots[6].out_uop.is_unique, slots_6.io.out_uop.is_unique \n connect issue_slots[6].out_uop.uses_stq, slots_6.io.out_uop.uses_stq \n connect issue_slots[6].out_uop.uses_ldq, slots_6.io.out_uop.uses_ldq \n connect issue_slots[6].out_uop.mem_signed, slots_6.io.out_uop.mem_signed \n connect issue_slots[6].out_uop.mem_size, slots_6.io.out_uop.mem_size \n connect issue_slots[6].out_uop.mem_cmd, slots_6.io.out_uop.mem_cmd \n connect issue_slots[6].out_uop.exc_cause, slots_6.io.out_uop.exc_cause \n connect issue_slots[6].out_uop.exception, slots_6.io.out_uop.exception \n connect issue_slots[6].out_uop.stale_pdst, slots_6.io.out_uop.stale_pdst \n connect issue_slots[6].out_uop.ppred_busy, slots_6.io.out_uop.ppred_busy \n connect issue_slots[6].out_uop.prs3_busy, slots_6.io.out_uop.prs3_busy \n connect issue_slots[6].out_uop.prs2_busy, slots_6.io.out_uop.prs2_busy \n connect issue_slots[6].out_uop.prs1_busy, slots_6.io.out_uop.prs1_busy \n connect issue_slots[6].out_uop.ppred, slots_6.io.out_uop.ppred \n connect issue_slots[6].out_uop.prs3, slots_6.io.out_uop.prs3 \n connect issue_slots[6].out_uop.prs2, slots_6.io.out_uop.prs2 \n connect issue_slots[6].out_uop.prs1, slots_6.io.out_uop.prs1 \n connect issue_slots[6].out_uop.pdst, slots_6.io.out_uop.pdst \n connect issue_slots[6].out_uop.rxq_idx, slots_6.io.out_uop.rxq_idx \n connect issue_slots[6].out_uop.stq_idx, slots_6.io.out_uop.stq_idx \n connect issue_slots[6].out_uop.ldq_idx, slots_6.io.out_uop.ldq_idx \n connect issue_slots[6].out_uop.rob_idx, slots_6.io.out_uop.rob_idx \n connect issue_slots[6].out_uop.fp_ctrl.vec, slots_6.io.out_uop.fp_ctrl.vec \n connect issue_slots[6].out_uop.fp_ctrl.wflags, slots_6.io.out_uop.fp_ctrl.wflags \n connect issue_slots[6].out_uop.fp_ctrl.sqrt, slots_6.io.out_uop.fp_ctrl.sqrt \n connect issue_slots[6].out_uop.fp_ctrl.div, slots_6.io.out_uop.fp_ctrl.div \n connect issue_slots[6].out_uop.fp_ctrl.fma, slots_6.io.out_uop.fp_ctrl.fma \n connect issue_slots[6].out_uop.fp_ctrl.fastpipe, slots_6.io.out_uop.fp_ctrl.fastpipe \n connect issue_slots[6].out_uop.fp_ctrl.toint, slots_6.io.out_uop.fp_ctrl.toint \n connect issue_slots[6].out_uop.fp_ctrl.fromint, slots_6.io.out_uop.fp_ctrl.fromint \n connect issue_slots[6].out_uop.fp_ctrl.typeTagOut, slots_6.io.out_uop.fp_ctrl.typeTagOut \n connect issue_slots[6].out_uop.fp_ctrl.typeTagIn, slots_6.io.out_uop.fp_ctrl.typeTagIn \n connect issue_slots[6].out_uop.fp_ctrl.swap23, slots_6.io.out_uop.fp_ctrl.swap23 \n connect issue_slots[6].out_uop.fp_ctrl.swap12, slots_6.io.out_uop.fp_ctrl.swap12 \n connect issue_slots[6].out_uop.fp_ctrl.ren3, slots_6.io.out_uop.fp_ctrl.ren3 \n connect issue_slots[6].out_uop.fp_ctrl.ren2, slots_6.io.out_uop.fp_ctrl.ren2 \n connect issue_slots[6].out_uop.fp_ctrl.ren1, slots_6.io.out_uop.fp_ctrl.ren1 \n connect issue_slots[6].out_uop.fp_ctrl.wen, slots_6.io.out_uop.fp_ctrl.wen \n connect issue_slots[6].out_uop.fp_ctrl.ldst, slots_6.io.out_uop.fp_ctrl.ldst \n connect issue_slots[6].out_uop.op2_sel, slots_6.io.out_uop.op2_sel \n connect issue_slots[6].out_uop.op1_sel, slots_6.io.out_uop.op1_sel \n connect issue_slots[6].out_uop.imm_packed, slots_6.io.out_uop.imm_packed \n connect issue_slots[6].out_uop.pimm, slots_6.io.out_uop.pimm \n connect issue_slots[6].out_uop.imm_sel, slots_6.io.out_uop.imm_sel \n connect issue_slots[6].out_uop.imm_rename, slots_6.io.out_uop.imm_rename \n connect issue_slots[6].out_uop.taken, slots_6.io.out_uop.taken \n connect issue_slots[6].out_uop.pc_lob, slots_6.io.out_uop.pc_lob \n connect issue_slots[6].out_uop.edge_inst, slots_6.io.out_uop.edge_inst \n connect issue_slots[6].out_uop.ftq_idx, slots_6.io.out_uop.ftq_idx \n connect issue_slots[6].out_uop.is_mov, slots_6.io.out_uop.is_mov \n connect issue_slots[6].out_uop.is_rocc, slots_6.io.out_uop.is_rocc \n connect issue_slots[6].out_uop.is_sys_pc2epc, slots_6.io.out_uop.is_sys_pc2epc \n connect issue_slots[6].out_uop.is_eret, slots_6.io.out_uop.is_eret \n connect issue_slots[6].out_uop.is_amo, slots_6.io.out_uop.is_amo \n connect issue_slots[6].out_uop.is_sfence, slots_6.io.out_uop.is_sfence \n connect issue_slots[6].out_uop.is_fencei, slots_6.io.out_uop.is_fencei \n connect issue_slots[6].out_uop.is_fence, slots_6.io.out_uop.is_fence \n connect issue_slots[6].out_uop.is_sfb, slots_6.io.out_uop.is_sfb \n connect issue_slots[6].out_uop.br_type, slots_6.io.out_uop.br_type \n connect issue_slots[6].out_uop.br_tag, slots_6.io.out_uop.br_tag \n connect issue_slots[6].out_uop.br_mask, slots_6.io.out_uop.br_mask \n connect issue_slots[6].out_uop.dis_col_sel, slots_6.io.out_uop.dis_col_sel \n connect issue_slots[6].out_uop.iw_p3_bypass_hint, slots_6.io.out_uop.iw_p3_bypass_hint \n connect issue_slots[6].out_uop.iw_p2_bypass_hint, slots_6.io.out_uop.iw_p2_bypass_hint \n connect issue_slots[6].out_uop.iw_p1_bypass_hint, slots_6.io.out_uop.iw_p1_bypass_hint \n connect issue_slots[6].out_uop.iw_p2_speculative_child, slots_6.io.out_uop.iw_p2_speculative_child \n connect issue_slots[6].out_uop.iw_p1_speculative_child, slots_6.io.out_uop.iw_p1_speculative_child \n connect issue_slots[6].out_uop.iw_issued_partial_dgen, slots_6.io.out_uop.iw_issued_partial_dgen \n connect issue_slots[6].out_uop.iw_issued_partial_agen, slots_6.io.out_uop.iw_issued_partial_agen \n connect issue_slots[6].out_uop.iw_issued, slots_6.io.out_uop.iw_issued \n connect issue_slots[6].out_uop.fu_code[0], slots_6.io.out_uop.fu_code[0] \n connect issue_slots[6].out_uop.fu_code[1], slots_6.io.out_uop.fu_code[1] \n connect issue_slots[6].out_uop.fu_code[2], slots_6.io.out_uop.fu_code[2] \n connect issue_slots[6].out_uop.fu_code[3], slots_6.io.out_uop.fu_code[3] \n connect issue_slots[6].out_uop.fu_code[4], slots_6.io.out_uop.fu_code[4] \n connect issue_slots[6].out_uop.fu_code[5], slots_6.io.out_uop.fu_code[5] \n connect issue_slots[6].out_uop.fu_code[6], slots_6.io.out_uop.fu_code[6] \n connect issue_slots[6].out_uop.fu_code[7], slots_6.io.out_uop.fu_code[7] \n connect issue_slots[6].out_uop.fu_code[8], slots_6.io.out_uop.fu_code[8] \n connect issue_slots[6].out_uop.fu_code[9], slots_6.io.out_uop.fu_code[9] \n connect issue_slots[6].out_uop.iq_type[0], slots_6.io.out_uop.iq_type[0] \n connect issue_slots[6].out_uop.iq_type[1], slots_6.io.out_uop.iq_type[1] \n connect issue_slots[6].out_uop.iq_type[2], slots_6.io.out_uop.iq_type[2] \n connect issue_slots[6].out_uop.iq_type[3], slots_6.io.out_uop.iq_type[3] \n connect issue_slots[6].out_uop.debug_pc, slots_6.io.out_uop.debug_pc \n connect issue_slots[6].out_uop.is_rvc, slots_6.io.out_uop.is_rvc \n connect issue_slots[6].out_uop.debug_inst, slots_6.io.out_uop.debug_inst \n connect issue_slots[6].out_uop.inst, slots_6.io.out_uop.inst \n connect slots_6.io.in_uop.bits.debug_tsrc, issue_slots[6].in_uop.bits.debug_tsrc \n connect slots_6.io.in_uop.bits.debug_fsrc, issue_slots[6].in_uop.bits.debug_fsrc \n connect slots_6.io.in_uop.bits.bp_xcpt_if, issue_slots[6].in_uop.bits.bp_xcpt_if \n connect slots_6.io.in_uop.bits.bp_debug_if, issue_slots[6].in_uop.bits.bp_debug_if \n connect slots_6.io.in_uop.bits.xcpt_ma_if, issue_slots[6].in_uop.bits.xcpt_ma_if \n connect slots_6.io.in_uop.bits.xcpt_ae_if, issue_slots[6].in_uop.bits.xcpt_ae_if \n connect slots_6.io.in_uop.bits.xcpt_pf_if, issue_slots[6].in_uop.bits.xcpt_pf_if \n connect slots_6.io.in_uop.bits.fp_typ, issue_slots[6].in_uop.bits.fp_typ \n connect slots_6.io.in_uop.bits.fp_rm, issue_slots[6].in_uop.bits.fp_rm \n connect slots_6.io.in_uop.bits.fp_val, issue_slots[6].in_uop.bits.fp_val \n connect slots_6.io.in_uop.bits.fcn_op, issue_slots[6].in_uop.bits.fcn_op \n connect slots_6.io.in_uop.bits.fcn_dw, issue_slots[6].in_uop.bits.fcn_dw \n connect slots_6.io.in_uop.bits.frs3_en, issue_slots[6].in_uop.bits.frs3_en \n connect slots_6.io.in_uop.bits.lrs2_rtype, issue_slots[6].in_uop.bits.lrs2_rtype \n connect slots_6.io.in_uop.bits.lrs1_rtype, issue_slots[6].in_uop.bits.lrs1_rtype \n connect slots_6.io.in_uop.bits.dst_rtype, issue_slots[6].in_uop.bits.dst_rtype \n connect slots_6.io.in_uop.bits.lrs3, issue_slots[6].in_uop.bits.lrs3 \n connect slots_6.io.in_uop.bits.lrs2, issue_slots[6].in_uop.bits.lrs2 \n connect slots_6.io.in_uop.bits.lrs1, issue_slots[6].in_uop.bits.lrs1 \n connect slots_6.io.in_uop.bits.ldst, issue_slots[6].in_uop.bits.ldst \n connect slots_6.io.in_uop.bits.ldst_is_rs1, issue_slots[6].in_uop.bits.ldst_is_rs1 \n connect slots_6.io.in_uop.bits.csr_cmd, issue_slots[6].in_uop.bits.csr_cmd \n connect slots_6.io.in_uop.bits.flush_on_commit, issue_slots[6].in_uop.bits.flush_on_commit \n connect slots_6.io.in_uop.bits.is_unique, issue_slots[6].in_uop.bits.is_unique \n connect slots_6.io.in_uop.bits.uses_stq, issue_slots[6].in_uop.bits.uses_stq \n connect slots_6.io.in_uop.bits.uses_ldq, issue_slots[6].in_uop.bits.uses_ldq \n connect slots_6.io.in_uop.bits.mem_signed, issue_slots[6].in_uop.bits.mem_signed \n connect slots_6.io.in_uop.bits.mem_size, issue_slots[6].in_uop.bits.mem_size \n connect slots_6.io.in_uop.bits.mem_cmd, issue_slots[6].in_uop.bits.mem_cmd \n connect slots_6.io.in_uop.bits.exc_cause, issue_slots[6].in_uop.bits.exc_cause \n connect slots_6.io.in_uop.bits.exception, issue_slots[6].in_uop.bits.exception \n connect slots_6.io.in_uop.bits.stale_pdst, issue_slots[6].in_uop.bits.stale_pdst \n connect slots_6.io.in_uop.bits.ppred_busy, issue_slots[6].in_uop.bits.ppred_busy \n connect slots_6.io.in_uop.bits.prs3_busy, issue_slots[6].in_uop.bits.prs3_busy \n connect slots_6.io.in_uop.bits.prs2_busy, issue_slots[6].in_uop.bits.prs2_busy \n connect slots_6.io.in_uop.bits.prs1_busy, issue_slots[6].in_uop.bits.prs1_busy \n connect slots_6.io.in_uop.bits.ppred, issue_slots[6].in_uop.bits.ppred \n connect slots_6.io.in_uop.bits.prs3, issue_slots[6].in_uop.bits.prs3 \n connect slots_6.io.in_uop.bits.prs2, issue_slots[6].in_uop.bits.prs2 \n connect slots_6.io.in_uop.bits.prs1, issue_slots[6].in_uop.bits.prs1 \n connect slots_6.io.in_uop.bits.pdst, issue_slots[6].in_uop.bits.pdst \n connect slots_6.io.in_uop.bits.rxq_idx, issue_slots[6].in_uop.bits.rxq_idx \n connect slots_6.io.in_uop.bits.stq_idx, issue_slots[6].in_uop.bits.stq_idx \n connect slots_6.io.in_uop.bits.ldq_idx, issue_slots[6].in_uop.bits.ldq_idx \n connect slots_6.io.in_uop.bits.rob_idx, issue_slots[6].in_uop.bits.rob_idx \n connect slots_6.io.in_uop.bits.fp_ctrl.vec, issue_slots[6].in_uop.bits.fp_ctrl.vec \n connect slots_6.io.in_uop.bits.fp_ctrl.wflags, issue_slots[6].in_uop.bits.fp_ctrl.wflags \n connect slots_6.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[6].in_uop.bits.fp_ctrl.sqrt \n connect slots_6.io.in_uop.bits.fp_ctrl.div, issue_slots[6].in_uop.bits.fp_ctrl.div \n connect slots_6.io.in_uop.bits.fp_ctrl.fma, issue_slots[6].in_uop.bits.fp_ctrl.fma \n connect slots_6.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[6].in_uop.bits.fp_ctrl.fastpipe \n connect slots_6.io.in_uop.bits.fp_ctrl.toint, issue_slots[6].in_uop.bits.fp_ctrl.toint \n connect slots_6.io.in_uop.bits.fp_ctrl.fromint, issue_slots[6].in_uop.bits.fp_ctrl.fromint \n connect slots_6.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[6].in_uop.bits.fp_ctrl.typeTagOut \n connect slots_6.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[6].in_uop.bits.fp_ctrl.typeTagIn \n connect slots_6.io.in_uop.bits.fp_ctrl.swap23, issue_slots[6].in_uop.bits.fp_ctrl.swap23 \n connect slots_6.io.in_uop.bits.fp_ctrl.swap12, issue_slots[6].in_uop.bits.fp_ctrl.swap12 \n connect slots_6.io.in_uop.bits.fp_ctrl.ren3, issue_slots[6].in_uop.bits.fp_ctrl.ren3 \n connect slots_6.io.in_uop.bits.fp_ctrl.ren2, issue_slots[6].in_uop.bits.fp_ctrl.ren2 \n connect slots_6.io.in_uop.bits.fp_ctrl.ren1, issue_slots[6].in_uop.bits.fp_ctrl.ren1 \n connect slots_6.io.in_uop.bits.fp_ctrl.wen, issue_slots[6].in_uop.bits.fp_ctrl.wen \n connect slots_6.io.in_uop.bits.fp_ctrl.ldst, issue_slots[6].in_uop.bits.fp_ctrl.ldst \n connect slots_6.io.in_uop.bits.op2_sel, issue_slots[6].in_uop.bits.op2_sel \n connect slots_6.io.in_uop.bits.op1_sel, issue_slots[6].in_uop.bits.op1_sel \n connect slots_6.io.in_uop.bits.imm_packed, issue_slots[6].in_uop.bits.imm_packed \n connect slots_6.io.in_uop.bits.pimm, issue_slots[6].in_uop.bits.pimm \n connect slots_6.io.in_uop.bits.imm_sel, issue_slots[6].in_uop.bits.imm_sel \n connect slots_6.io.in_uop.bits.imm_rename, issue_slots[6].in_uop.bits.imm_rename \n connect slots_6.io.in_uop.bits.taken, issue_slots[6].in_uop.bits.taken \n connect slots_6.io.in_uop.bits.pc_lob, issue_slots[6].in_uop.bits.pc_lob \n connect slots_6.io.in_uop.bits.edge_inst, issue_slots[6].in_uop.bits.edge_inst \n connect slots_6.io.in_uop.bits.ftq_idx, issue_slots[6].in_uop.bits.ftq_idx \n connect slots_6.io.in_uop.bits.is_mov, issue_slots[6].in_uop.bits.is_mov \n connect slots_6.io.in_uop.bits.is_rocc, issue_slots[6].in_uop.bits.is_rocc \n connect slots_6.io.in_uop.bits.is_sys_pc2epc, issue_slots[6].in_uop.bits.is_sys_pc2epc \n connect slots_6.io.in_uop.bits.is_eret, issue_slots[6].in_uop.bits.is_eret \n connect slots_6.io.in_uop.bits.is_amo, issue_slots[6].in_uop.bits.is_amo \n connect slots_6.io.in_uop.bits.is_sfence, issue_slots[6].in_uop.bits.is_sfence \n connect slots_6.io.in_uop.bits.is_fencei, issue_slots[6].in_uop.bits.is_fencei \n connect slots_6.io.in_uop.bits.is_fence, issue_slots[6].in_uop.bits.is_fence \n connect slots_6.io.in_uop.bits.is_sfb, issue_slots[6].in_uop.bits.is_sfb \n connect slots_6.io.in_uop.bits.br_type, issue_slots[6].in_uop.bits.br_type \n connect slots_6.io.in_uop.bits.br_tag, issue_slots[6].in_uop.bits.br_tag \n connect slots_6.io.in_uop.bits.br_mask, issue_slots[6].in_uop.bits.br_mask \n connect slots_6.io.in_uop.bits.dis_col_sel, issue_slots[6].in_uop.bits.dis_col_sel \n connect slots_6.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[6].in_uop.bits.iw_p3_bypass_hint \n connect slots_6.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[6].in_uop.bits.iw_p2_bypass_hint \n connect slots_6.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[6].in_uop.bits.iw_p1_bypass_hint \n connect slots_6.io.in_uop.bits.iw_p2_speculative_child, issue_slots[6].in_uop.bits.iw_p2_speculative_child \n connect slots_6.io.in_uop.bits.iw_p1_speculative_child, issue_slots[6].in_uop.bits.iw_p1_speculative_child \n connect slots_6.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[6].in_uop.bits.iw_issued_partial_dgen \n connect slots_6.io.in_uop.bits.iw_issued_partial_agen, issue_slots[6].in_uop.bits.iw_issued_partial_agen \n connect slots_6.io.in_uop.bits.iw_issued, issue_slots[6].in_uop.bits.iw_issued \n connect slots_6.io.in_uop.bits.fu_code[0], issue_slots[6].in_uop.bits.fu_code[0] \n connect slots_6.io.in_uop.bits.fu_code[1], issue_slots[6].in_uop.bits.fu_code[1] \n connect slots_6.io.in_uop.bits.fu_code[2], issue_slots[6].in_uop.bits.fu_code[2] \n connect slots_6.io.in_uop.bits.fu_code[3], issue_slots[6].in_uop.bits.fu_code[3] \n connect slots_6.io.in_uop.bits.fu_code[4], issue_slots[6].in_uop.bits.fu_code[4] \n connect slots_6.io.in_uop.bits.fu_code[5], issue_slots[6].in_uop.bits.fu_code[5] \n connect slots_6.io.in_uop.bits.fu_code[6], issue_slots[6].in_uop.bits.fu_code[6] \n connect slots_6.io.in_uop.bits.fu_code[7], issue_slots[6].in_uop.bits.fu_code[7] \n connect slots_6.io.in_uop.bits.fu_code[8], issue_slots[6].in_uop.bits.fu_code[8] \n connect slots_6.io.in_uop.bits.fu_code[9], issue_slots[6].in_uop.bits.fu_code[9] \n connect slots_6.io.in_uop.bits.iq_type[0], issue_slots[6].in_uop.bits.iq_type[0] \n connect slots_6.io.in_uop.bits.iq_type[1], issue_slots[6].in_uop.bits.iq_type[1] \n connect slots_6.io.in_uop.bits.iq_type[2], issue_slots[6].in_uop.bits.iq_type[2] \n connect slots_6.io.in_uop.bits.iq_type[3], issue_slots[6].in_uop.bits.iq_type[3] \n connect slots_6.io.in_uop.bits.debug_pc, issue_slots[6].in_uop.bits.debug_pc \n connect slots_6.io.in_uop.bits.is_rvc, issue_slots[6].in_uop.bits.is_rvc \n connect slots_6.io.in_uop.bits.debug_inst, issue_slots[6].in_uop.bits.debug_inst \n connect slots_6.io.in_uop.bits.inst, issue_slots[6].in_uop.bits.inst \n connect slots_6.io.in_uop.valid, issue_slots[6].in_uop.valid \n connect issue_slots[6].iss_uop.debug_tsrc, slots_6.io.iss_uop.debug_tsrc \n connect issue_slots[6].iss_uop.debug_fsrc, slots_6.io.iss_uop.debug_fsrc \n connect issue_slots[6].iss_uop.bp_xcpt_if, slots_6.io.iss_uop.bp_xcpt_if \n connect issue_slots[6].iss_uop.bp_debug_if, slots_6.io.iss_uop.bp_debug_if \n connect issue_slots[6].iss_uop.xcpt_ma_if, slots_6.io.iss_uop.xcpt_ma_if \n connect issue_slots[6].iss_uop.xcpt_ae_if, slots_6.io.iss_uop.xcpt_ae_if \n connect issue_slots[6].iss_uop.xcpt_pf_if, slots_6.io.iss_uop.xcpt_pf_if \n connect issue_slots[6].iss_uop.fp_typ, slots_6.io.iss_uop.fp_typ \n connect issue_slots[6].iss_uop.fp_rm, slots_6.io.iss_uop.fp_rm \n connect issue_slots[6].iss_uop.fp_val, slots_6.io.iss_uop.fp_val \n connect issue_slots[6].iss_uop.fcn_op, slots_6.io.iss_uop.fcn_op \n connect issue_slots[6].iss_uop.fcn_dw, slots_6.io.iss_uop.fcn_dw \n connect issue_slots[6].iss_uop.frs3_en, slots_6.io.iss_uop.frs3_en \n connect issue_slots[6].iss_uop.lrs2_rtype, slots_6.io.iss_uop.lrs2_rtype \n connect issue_slots[6].iss_uop.lrs1_rtype, slots_6.io.iss_uop.lrs1_rtype \n connect issue_slots[6].iss_uop.dst_rtype, slots_6.io.iss_uop.dst_rtype \n connect issue_slots[6].iss_uop.lrs3, slots_6.io.iss_uop.lrs3 \n connect issue_slots[6].iss_uop.lrs2, slots_6.io.iss_uop.lrs2 \n connect issue_slots[6].iss_uop.lrs1, slots_6.io.iss_uop.lrs1 \n connect issue_slots[6].iss_uop.ldst, slots_6.io.iss_uop.ldst \n connect issue_slots[6].iss_uop.ldst_is_rs1, slots_6.io.iss_uop.ldst_is_rs1 \n connect issue_slots[6].iss_uop.csr_cmd, slots_6.io.iss_uop.csr_cmd \n connect issue_slots[6].iss_uop.flush_on_commit, slots_6.io.iss_uop.flush_on_commit \n connect issue_slots[6].iss_uop.is_unique, slots_6.io.iss_uop.is_unique \n connect issue_slots[6].iss_uop.uses_stq, slots_6.io.iss_uop.uses_stq \n connect issue_slots[6].iss_uop.uses_ldq, slots_6.io.iss_uop.uses_ldq \n connect issue_slots[6].iss_uop.mem_signed, slots_6.io.iss_uop.mem_signed \n connect issue_slots[6].iss_uop.mem_size, slots_6.io.iss_uop.mem_size \n connect issue_slots[6].iss_uop.mem_cmd, slots_6.io.iss_uop.mem_cmd \n connect issue_slots[6].iss_uop.exc_cause, slots_6.io.iss_uop.exc_cause \n connect issue_slots[6].iss_uop.exception, slots_6.io.iss_uop.exception \n connect issue_slots[6].iss_uop.stale_pdst, slots_6.io.iss_uop.stale_pdst \n connect issue_slots[6].iss_uop.ppred_busy, slots_6.io.iss_uop.ppred_busy \n connect issue_slots[6].iss_uop.prs3_busy, slots_6.io.iss_uop.prs3_busy \n connect issue_slots[6].iss_uop.prs2_busy, slots_6.io.iss_uop.prs2_busy \n connect issue_slots[6].iss_uop.prs1_busy, slots_6.io.iss_uop.prs1_busy \n connect issue_slots[6].iss_uop.ppred, slots_6.io.iss_uop.ppred \n connect issue_slots[6].iss_uop.prs3, slots_6.io.iss_uop.prs3 \n connect issue_slots[6].iss_uop.prs2, slots_6.io.iss_uop.prs2 \n connect issue_slots[6].iss_uop.prs1, slots_6.io.iss_uop.prs1 \n connect issue_slots[6].iss_uop.pdst, slots_6.io.iss_uop.pdst \n connect issue_slots[6].iss_uop.rxq_idx, slots_6.io.iss_uop.rxq_idx \n connect issue_slots[6].iss_uop.stq_idx, slots_6.io.iss_uop.stq_idx \n connect issue_slots[6].iss_uop.ldq_idx, slots_6.io.iss_uop.ldq_idx \n connect issue_slots[6].iss_uop.rob_idx, slots_6.io.iss_uop.rob_idx \n connect issue_slots[6].iss_uop.fp_ctrl.vec, slots_6.io.iss_uop.fp_ctrl.vec \n connect issue_slots[6].iss_uop.fp_ctrl.wflags, slots_6.io.iss_uop.fp_ctrl.wflags \n connect issue_slots[6].iss_uop.fp_ctrl.sqrt, slots_6.io.iss_uop.fp_ctrl.sqrt \n connect issue_slots[6].iss_uop.fp_ctrl.div, slots_6.io.iss_uop.fp_ctrl.div \n connect issue_slots[6].iss_uop.fp_ctrl.fma, slots_6.io.iss_uop.fp_ctrl.fma \n connect issue_slots[6].iss_uop.fp_ctrl.fastpipe, slots_6.io.iss_uop.fp_ctrl.fastpipe \n connect issue_slots[6].iss_uop.fp_ctrl.toint, slots_6.io.iss_uop.fp_ctrl.toint \n connect issue_slots[6].iss_uop.fp_ctrl.fromint, slots_6.io.iss_uop.fp_ctrl.fromint \n connect issue_slots[6].iss_uop.fp_ctrl.typeTagOut, slots_6.io.iss_uop.fp_ctrl.typeTagOut \n connect issue_slots[6].iss_uop.fp_ctrl.typeTagIn, slots_6.io.iss_uop.fp_ctrl.typeTagIn \n connect issue_slots[6].iss_uop.fp_ctrl.swap23, slots_6.io.iss_uop.fp_ctrl.swap23 \n connect issue_slots[6].iss_uop.fp_ctrl.swap12, slots_6.io.iss_uop.fp_ctrl.swap12 \n connect issue_slots[6].iss_uop.fp_ctrl.ren3, slots_6.io.iss_uop.fp_ctrl.ren3 \n connect issue_slots[6].iss_uop.fp_ctrl.ren2, slots_6.io.iss_uop.fp_ctrl.ren2 \n connect issue_slots[6].iss_uop.fp_ctrl.ren1, slots_6.io.iss_uop.fp_ctrl.ren1 \n connect issue_slots[6].iss_uop.fp_ctrl.wen, slots_6.io.iss_uop.fp_ctrl.wen \n connect issue_slots[6].iss_uop.fp_ctrl.ldst, slots_6.io.iss_uop.fp_ctrl.ldst \n connect issue_slots[6].iss_uop.op2_sel, slots_6.io.iss_uop.op2_sel \n connect issue_slots[6].iss_uop.op1_sel, slots_6.io.iss_uop.op1_sel \n connect issue_slots[6].iss_uop.imm_packed, slots_6.io.iss_uop.imm_packed \n connect issue_slots[6].iss_uop.pimm, slots_6.io.iss_uop.pimm \n connect issue_slots[6].iss_uop.imm_sel, slots_6.io.iss_uop.imm_sel \n connect issue_slots[6].iss_uop.imm_rename, slots_6.io.iss_uop.imm_rename \n connect issue_slots[6].iss_uop.taken, slots_6.io.iss_uop.taken \n connect issue_slots[6].iss_uop.pc_lob, slots_6.io.iss_uop.pc_lob \n connect issue_slots[6].iss_uop.edge_inst, slots_6.io.iss_uop.edge_inst \n connect issue_slots[6].iss_uop.ftq_idx, slots_6.io.iss_uop.ftq_idx \n connect issue_slots[6].iss_uop.is_mov, slots_6.io.iss_uop.is_mov \n connect issue_slots[6].iss_uop.is_rocc, slots_6.io.iss_uop.is_rocc \n connect issue_slots[6].iss_uop.is_sys_pc2epc, slots_6.io.iss_uop.is_sys_pc2epc \n connect issue_slots[6].iss_uop.is_eret, slots_6.io.iss_uop.is_eret \n connect issue_slots[6].iss_uop.is_amo, slots_6.io.iss_uop.is_amo \n connect issue_slots[6].iss_uop.is_sfence, slots_6.io.iss_uop.is_sfence \n connect issue_slots[6].iss_uop.is_fencei, slots_6.io.iss_uop.is_fencei \n connect issue_slots[6].iss_uop.is_fence, slots_6.io.iss_uop.is_fence \n connect issue_slots[6].iss_uop.is_sfb, slots_6.io.iss_uop.is_sfb \n connect issue_slots[6].iss_uop.br_type, slots_6.io.iss_uop.br_type \n connect issue_slots[6].iss_uop.br_tag, slots_6.io.iss_uop.br_tag \n connect issue_slots[6].iss_uop.br_mask, slots_6.io.iss_uop.br_mask \n connect issue_slots[6].iss_uop.dis_col_sel, slots_6.io.iss_uop.dis_col_sel \n connect issue_slots[6].iss_uop.iw_p3_bypass_hint, slots_6.io.iss_uop.iw_p3_bypass_hint \n connect issue_slots[6].iss_uop.iw_p2_bypass_hint, slots_6.io.iss_uop.iw_p2_bypass_hint \n connect issue_slots[6].iss_uop.iw_p1_bypass_hint, slots_6.io.iss_uop.iw_p1_bypass_hint \n connect issue_slots[6].iss_uop.iw_p2_speculative_child, slots_6.io.iss_uop.iw_p2_speculative_child \n connect issue_slots[6].iss_uop.iw_p1_speculative_child, slots_6.io.iss_uop.iw_p1_speculative_child \n connect issue_slots[6].iss_uop.iw_issued_partial_dgen, slots_6.io.iss_uop.iw_issued_partial_dgen \n connect issue_slots[6].iss_uop.iw_issued_partial_agen, slots_6.io.iss_uop.iw_issued_partial_agen \n connect issue_slots[6].iss_uop.iw_issued, slots_6.io.iss_uop.iw_issued \n connect issue_slots[6].iss_uop.fu_code[0], slots_6.io.iss_uop.fu_code[0] \n connect issue_slots[6].iss_uop.fu_code[1], slots_6.io.iss_uop.fu_code[1] \n connect issue_slots[6].iss_uop.fu_code[2], slots_6.io.iss_uop.fu_code[2] \n connect issue_slots[6].iss_uop.fu_code[3], slots_6.io.iss_uop.fu_code[3] \n connect issue_slots[6].iss_uop.fu_code[4], slots_6.io.iss_uop.fu_code[4] \n connect issue_slots[6].iss_uop.fu_code[5], slots_6.io.iss_uop.fu_code[5] \n connect issue_slots[6].iss_uop.fu_code[6], slots_6.io.iss_uop.fu_code[6] \n connect issue_slots[6].iss_uop.fu_code[7], slots_6.io.iss_uop.fu_code[7] \n connect issue_slots[6].iss_uop.fu_code[8], slots_6.io.iss_uop.fu_code[8] \n connect issue_slots[6].iss_uop.fu_code[9], slots_6.io.iss_uop.fu_code[9] \n connect issue_slots[6].iss_uop.iq_type[0], slots_6.io.iss_uop.iq_type[0] \n connect issue_slots[6].iss_uop.iq_type[1], slots_6.io.iss_uop.iq_type[1] \n connect issue_slots[6].iss_uop.iq_type[2], slots_6.io.iss_uop.iq_type[2] \n connect issue_slots[6].iss_uop.iq_type[3], slots_6.io.iss_uop.iq_type[3] \n connect issue_slots[6].iss_uop.debug_pc, slots_6.io.iss_uop.debug_pc \n connect issue_slots[6].iss_uop.is_rvc, slots_6.io.iss_uop.is_rvc \n connect issue_slots[6].iss_uop.debug_inst, slots_6.io.iss_uop.debug_inst \n connect issue_slots[6].iss_uop.inst, slots_6.io.iss_uop.inst \n connect slots_6.io.grant, issue_slots[6].grant \n connect issue_slots[6].request, slots_6.io.request \n connect issue_slots[6].will_be_valid, slots_6.io.will_be_valid \n connect issue_slots[6].valid, slots_6.io.valid \n connect slots_7.io.child_rebusys, issue_slots[7].child_rebusys \n connect slots_7.io.pred_wakeup_port.bits, issue_slots[7].pred_wakeup_port.bits \n connect slots_7.io.pred_wakeup_port.valid, issue_slots[7].pred_wakeup_port.valid \n connect slots_7.io.wakeup_ports[0].bits.rebusy, issue_slots[7].wakeup_ports[0].bits.rebusy \n connect slots_7.io.wakeup_ports[0].bits.speculative_mask, issue_slots[7].wakeup_ports[0].bits.speculative_mask \n connect slots_7.io.wakeup_ports[0].bits.bypassable, issue_slots[7].wakeup_ports[0].bits.bypassable \n connect slots_7.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[7].wakeup_ports[0].bits.uop.debug_tsrc \n connect slots_7.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[7].wakeup_ports[0].bits.uop.debug_fsrc \n connect slots_7.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[7].wakeup_ports[0].bits.uop.bp_xcpt_if \n connect slots_7.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[7].wakeup_ports[0].bits.uop.bp_debug_if \n connect slots_7.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[7].wakeup_ports[0].bits.uop.xcpt_ma_if \n connect slots_7.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[7].wakeup_ports[0].bits.uop.xcpt_ae_if \n connect slots_7.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[7].wakeup_ports[0].bits.uop.xcpt_pf_if \n connect slots_7.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[7].wakeup_ports[0].bits.uop.fp_typ \n connect slots_7.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[7].wakeup_ports[0].bits.uop.fp_rm \n connect slots_7.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[7].wakeup_ports[0].bits.uop.fp_val \n connect slots_7.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[7].wakeup_ports[0].bits.uop.fcn_op \n connect slots_7.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[7].wakeup_ports[0].bits.uop.fcn_dw \n connect slots_7.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[7].wakeup_ports[0].bits.uop.frs3_en \n connect slots_7.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[7].wakeup_ports[0].bits.uop.lrs2_rtype \n connect slots_7.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[7].wakeup_ports[0].bits.uop.lrs1_rtype \n connect slots_7.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[7].wakeup_ports[0].bits.uop.dst_rtype \n connect slots_7.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[7].wakeup_ports[0].bits.uop.lrs3 \n connect slots_7.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[7].wakeup_ports[0].bits.uop.lrs2 \n connect slots_7.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[7].wakeup_ports[0].bits.uop.lrs1 \n connect slots_7.io.wakeup_ports[0].bits.uop.ldst, issue_slots[7].wakeup_ports[0].bits.uop.ldst \n connect slots_7.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[7].wakeup_ports[0].bits.uop.ldst_is_rs1 \n connect slots_7.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[7].wakeup_ports[0].bits.uop.csr_cmd \n connect slots_7.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[7].wakeup_ports[0].bits.uop.flush_on_commit \n connect slots_7.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[7].wakeup_ports[0].bits.uop.is_unique \n connect slots_7.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[7].wakeup_ports[0].bits.uop.uses_stq \n connect slots_7.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[7].wakeup_ports[0].bits.uop.uses_ldq \n connect slots_7.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[7].wakeup_ports[0].bits.uop.mem_signed \n connect slots_7.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[7].wakeup_ports[0].bits.uop.mem_size \n connect slots_7.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[7].wakeup_ports[0].bits.uop.mem_cmd \n connect slots_7.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[7].wakeup_ports[0].bits.uop.exc_cause \n connect slots_7.io.wakeup_ports[0].bits.uop.exception, issue_slots[7].wakeup_ports[0].bits.uop.exception \n connect slots_7.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[7].wakeup_ports[0].bits.uop.stale_pdst \n connect slots_7.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[7].wakeup_ports[0].bits.uop.ppred_busy \n connect slots_7.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[7].wakeup_ports[0].bits.uop.prs3_busy \n connect slots_7.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[7].wakeup_ports[0].bits.uop.prs2_busy \n connect slots_7.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[7].wakeup_ports[0].bits.uop.prs1_busy \n connect slots_7.io.wakeup_ports[0].bits.uop.ppred, issue_slots[7].wakeup_ports[0].bits.uop.ppred \n connect slots_7.io.wakeup_ports[0].bits.uop.prs3, issue_slots[7].wakeup_ports[0].bits.uop.prs3 \n connect slots_7.io.wakeup_ports[0].bits.uop.prs2, issue_slots[7].wakeup_ports[0].bits.uop.prs2 \n connect slots_7.io.wakeup_ports[0].bits.uop.prs1, issue_slots[7].wakeup_ports[0].bits.uop.prs1 \n connect slots_7.io.wakeup_ports[0].bits.uop.pdst, issue_slots[7].wakeup_ports[0].bits.uop.pdst \n connect slots_7.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[7].wakeup_ports[0].bits.uop.rxq_idx \n connect slots_7.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[7].wakeup_ports[0].bits.uop.stq_idx \n connect slots_7.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[7].wakeup_ports[0].bits.uop.ldq_idx \n connect slots_7.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[7].wakeup_ports[0].bits.uop.rob_idx \n connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.vec \n connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.wflags \n connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.sqrt \n connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.div \n connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.fma \n connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe \n connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.toint \n connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.fromint \n connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut \n connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn \n connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.swap23 \n connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.swap12 \n connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.ren3 \n connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.ren2 \n connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.ren1 \n connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.wen \n connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.ldst \n connect slots_7.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[7].wakeup_ports[0].bits.uop.op2_sel \n connect slots_7.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[7].wakeup_ports[0].bits.uop.op1_sel \n connect slots_7.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[7].wakeup_ports[0].bits.uop.imm_packed \n connect slots_7.io.wakeup_ports[0].bits.uop.pimm, issue_slots[7].wakeup_ports[0].bits.uop.pimm \n connect slots_7.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[7].wakeup_ports[0].bits.uop.imm_sel \n connect slots_7.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[7].wakeup_ports[0].bits.uop.imm_rename \n connect slots_7.io.wakeup_ports[0].bits.uop.taken, issue_slots[7].wakeup_ports[0].bits.uop.taken \n connect slots_7.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[7].wakeup_ports[0].bits.uop.pc_lob \n connect slots_7.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[7].wakeup_ports[0].bits.uop.edge_inst \n connect slots_7.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[7].wakeup_ports[0].bits.uop.ftq_idx \n connect slots_7.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[7].wakeup_ports[0].bits.uop.is_mov \n connect slots_7.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[7].wakeup_ports[0].bits.uop.is_rocc \n connect slots_7.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[7].wakeup_ports[0].bits.uop.is_sys_pc2epc \n connect slots_7.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[7].wakeup_ports[0].bits.uop.is_eret \n connect slots_7.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[7].wakeup_ports[0].bits.uop.is_amo \n connect slots_7.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[7].wakeup_ports[0].bits.uop.is_sfence \n connect slots_7.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[7].wakeup_ports[0].bits.uop.is_fencei \n connect slots_7.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[7].wakeup_ports[0].bits.uop.is_fence \n connect slots_7.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[7].wakeup_ports[0].bits.uop.is_sfb \n connect slots_7.io.wakeup_ports[0].bits.uop.br_type, issue_slots[7].wakeup_ports[0].bits.uop.br_type \n connect slots_7.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[7].wakeup_ports[0].bits.uop.br_tag \n connect slots_7.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[7].wakeup_ports[0].bits.uop.br_mask \n connect slots_7.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[7].wakeup_ports[0].bits.uop.dis_col_sel \n connect slots_7.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[7].wakeup_ports[0].bits.uop.iw_p3_bypass_hint \n connect slots_7.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[7].wakeup_ports[0].bits.uop.iw_p2_bypass_hint \n connect slots_7.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[7].wakeup_ports[0].bits.uop.iw_p1_bypass_hint \n connect slots_7.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[7].wakeup_ports[0].bits.uop.iw_p2_speculative_child \n connect slots_7.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[7].wakeup_ports[0].bits.uop.iw_p1_speculative_child \n connect slots_7.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[7].wakeup_ports[0].bits.uop.iw_issued_partial_dgen \n connect slots_7.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[7].wakeup_ports[0].bits.uop.iw_issued_partial_agen \n connect slots_7.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[7].wakeup_ports[0].bits.uop.iw_issued \n connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[0] \n connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[1] \n connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[2] \n connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[3] \n connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[4] \n connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[5] \n connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[6] \n connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[7] \n connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[8] \n connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[9] \n connect slots_7.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[7].wakeup_ports[0].bits.uop.iq_type[0] \n connect slots_7.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[7].wakeup_ports[0].bits.uop.iq_type[1] \n connect slots_7.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[7].wakeup_ports[0].bits.uop.iq_type[2] \n connect slots_7.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[7].wakeup_ports[0].bits.uop.iq_type[3] \n connect slots_7.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[7].wakeup_ports[0].bits.uop.debug_pc \n connect slots_7.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[7].wakeup_ports[0].bits.uop.is_rvc \n connect slots_7.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[7].wakeup_ports[0].bits.uop.debug_inst \n connect slots_7.io.wakeup_ports[0].bits.uop.inst, issue_slots[7].wakeup_ports[0].bits.uop.inst \n connect slots_7.io.wakeup_ports[0].valid, issue_slots[7].wakeup_ports[0].valid \n connect slots_7.io.wakeup_ports[1].bits.rebusy, issue_slots[7].wakeup_ports[1].bits.rebusy \n connect slots_7.io.wakeup_ports[1].bits.speculative_mask, issue_slots[7].wakeup_ports[1].bits.speculative_mask \n connect slots_7.io.wakeup_ports[1].bits.bypassable, issue_slots[7].wakeup_ports[1].bits.bypassable \n connect slots_7.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[7].wakeup_ports[1].bits.uop.debug_tsrc \n connect slots_7.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[7].wakeup_ports[1].bits.uop.debug_fsrc \n connect slots_7.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[7].wakeup_ports[1].bits.uop.bp_xcpt_if \n connect slots_7.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[7].wakeup_ports[1].bits.uop.bp_debug_if \n connect slots_7.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[7].wakeup_ports[1].bits.uop.xcpt_ma_if \n connect slots_7.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[7].wakeup_ports[1].bits.uop.xcpt_ae_if \n connect slots_7.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[7].wakeup_ports[1].bits.uop.xcpt_pf_if \n connect slots_7.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[7].wakeup_ports[1].bits.uop.fp_typ \n connect slots_7.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[7].wakeup_ports[1].bits.uop.fp_rm \n connect slots_7.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[7].wakeup_ports[1].bits.uop.fp_val \n connect slots_7.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[7].wakeup_ports[1].bits.uop.fcn_op \n connect slots_7.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[7].wakeup_ports[1].bits.uop.fcn_dw \n connect slots_7.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[7].wakeup_ports[1].bits.uop.frs3_en \n connect slots_7.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[7].wakeup_ports[1].bits.uop.lrs2_rtype \n connect slots_7.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[7].wakeup_ports[1].bits.uop.lrs1_rtype \n connect slots_7.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[7].wakeup_ports[1].bits.uop.dst_rtype \n connect slots_7.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[7].wakeup_ports[1].bits.uop.lrs3 \n connect slots_7.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[7].wakeup_ports[1].bits.uop.lrs2 \n connect slots_7.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[7].wakeup_ports[1].bits.uop.lrs1 \n connect slots_7.io.wakeup_ports[1].bits.uop.ldst, issue_slots[7].wakeup_ports[1].bits.uop.ldst \n connect slots_7.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[7].wakeup_ports[1].bits.uop.ldst_is_rs1 \n connect slots_7.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[7].wakeup_ports[1].bits.uop.csr_cmd \n connect slots_7.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[7].wakeup_ports[1].bits.uop.flush_on_commit \n connect slots_7.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[7].wakeup_ports[1].bits.uop.is_unique \n connect slots_7.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[7].wakeup_ports[1].bits.uop.uses_stq \n connect slots_7.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[7].wakeup_ports[1].bits.uop.uses_ldq \n connect slots_7.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[7].wakeup_ports[1].bits.uop.mem_signed \n connect slots_7.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[7].wakeup_ports[1].bits.uop.mem_size \n connect slots_7.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[7].wakeup_ports[1].bits.uop.mem_cmd \n connect slots_7.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[7].wakeup_ports[1].bits.uop.exc_cause \n connect slots_7.io.wakeup_ports[1].bits.uop.exception, issue_slots[7].wakeup_ports[1].bits.uop.exception \n connect slots_7.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[7].wakeup_ports[1].bits.uop.stale_pdst \n connect slots_7.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[7].wakeup_ports[1].bits.uop.ppred_busy \n connect slots_7.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[7].wakeup_ports[1].bits.uop.prs3_busy \n connect slots_7.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[7].wakeup_ports[1].bits.uop.prs2_busy \n connect slots_7.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[7].wakeup_ports[1].bits.uop.prs1_busy \n connect slots_7.io.wakeup_ports[1].bits.uop.ppred, issue_slots[7].wakeup_ports[1].bits.uop.ppred \n connect slots_7.io.wakeup_ports[1].bits.uop.prs3, issue_slots[7].wakeup_ports[1].bits.uop.prs3 \n connect slots_7.io.wakeup_ports[1].bits.uop.prs2, issue_slots[7].wakeup_ports[1].bits.uop.prs2 \n connect slots_7.io.wakeup_ports[1].bits.uop.prs1, issue_slots[7].wakeup_ports[1].bits.uop.prs1 \n connect slots_7.io.wakeup_ports[1].bits.uop.pdst, issue_slots[7].wakeup_ports[1].bits.uop.pdst \n connect slots_7.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[7].wakeup_ports[1].bits.uop.rxq_idx \n connect slots_7.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[7].wakeup_ports[1].bits.uop.stq_idx \n connect slots_7.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[7].wakeup_ports[1].bits.uop.ldq_idx \n connect slots_7.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[7].wakeup_ports[1].bits.uop.rob_idx \n connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.vec \n connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.wflags \n connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.sqrt \n connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.div \n connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.fma \n connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe \n connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.toint \n connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.fromint \n connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut \n connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn \n connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.swap23 \n connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.swap12 \n connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.ren3 \n connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.ren2 \n connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.ren1 \n connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.wen \n connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.ldst \n connect slots_7.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[7].wakeup_ports[1].bits.uop.op2_sel \n connect slots_7.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[7].wakeup_ports[1].bits.uop.op1_sel \n connect slots_7.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[7].wakeup_ports[1].bits.uop.imm_packed \n connect slots_7.io.wakeup_ports[1].bits.uop.pimm, issue_slots[7].wakeup_ports[1].bits.uop.pimm \n connect slots_7.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[7].wakeup_ports[1].bits.uop.imm_sel \n connect slots_7.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[7].wakeup_ports[1].bits.uop.imm_rename \n connect slots_7.io.wakeup_ports[1].bits.uop.taken, issue_slots[7].wakeup_ports[1].bits.uop.taken \n connect slots_7.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[7].wakeup_ports[1].bits.uop.pc_lob \n connect slots_7.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[7].wakeup_ports[1].bits.uop.edge_inst \n connect slots_7.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[7].wakeup_ports[1].bits.uop.ftq_idx \n connect slots_7.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[7].wakeup_ports[1].bits.uop.is_mov \n connect slots_7.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[7].wakeup_ports[1].bits.uop.is_rocc \n connect slots_7.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[7].wakeup_ports[1].bits.uop.is_sys_pc2epc \n connect slots_7.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[7].wakeup_ports[1].bits.uop.is_eret \n connect slots_7.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[7].wakeup_ports[1].bits.uop.is_amo \n connect slots_7.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[7].wakeup_ports[1].bits.uop.is_sfence \n connect slots_7.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[7].wakeup_ports[1].bits.uop.is_fencei \n connect slots_7.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[7].wakeup_ports[1].bits.uop.is_fence \n connect slots_7.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[7].wakeup_ports[1].bits.uop.is_sfb \n connect slots_7.io.wakeup_ports[1].bits.uop.br_type, issue_slots[7].wakeup_ports[1].bits.uop.br_type \n connect slots_7.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[7].wakeup_ports[1].bits.uop.br_tag \n connect slots_7.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[7].wakeup_ports[1].bits.uop.br_mask \n connect slots_7.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[7].wakeup_ports[1].bits.uop.dis_col_sel \n connect slots_7.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[7].wakeup_ports[1].bits.uop.iw_p3_bypass_hint \n connect slots_7.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[7].wakeup_ports[1].bits.uop.iw_p2_bypass_hint \n connect slots_7.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[7].wakeup_ports[1].bits.uop.iw_p1_bypass_hint \n connect slots_7.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[7].wakeup_ports[1].bits.uop.iw_p2_speculative_child \n connect slots_7.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[7].wakeup_ports[1].bits.uop.iw_p1_speculative_child \n connect slots_7.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[7].wakeup_ports[1].bits.uop.iw_issued_partial_dgen \n connect slots_7.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[7].wakeup_ports[1].bits.uop.iw_issued_partial_agen \n connect slots_7.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[7].wakeup_ports[1].bits.uop.iw_issued \n connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[0] \n connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[1] \n connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[2] \n connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[3] \n connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[4] \n connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[5] \n connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[6] \n connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[7] \n connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[8] \n connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[9] \n connect slots_7.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[7].wakeup_ports[1].bits.uop.iq_type[0] \n connect slots_7.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[7].wakeup_ports[1].bits.uop.iq_type[1] \n connect slots_7.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[7].wakeup_ports[1].bits.uop.iq_type[2] \n connect slots_7.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[7].wakeup_ports[1].bits.uop.iq_type[3] \n connect slots_7.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[7].wakeup_ports[1].bits.uop.debug_pc \n connect slots_7.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[7].wakeup_ports[1].bits.uop.is_rvc \n connect slots_7.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[7].wakeup_ports[1].bits.uop.debug_inst \n connect slots_7.io.wakeup_ports[1].bits.uop.inst, issue_slots[7].wakeup_ports[1].bits.uop.inst \n connect slots_7.io.wakeup_ports[1].valid, issue_slots[7].wakeup_ports[1].valid \n connect slots_7.io.wakeup_ports[2].bits.rebusy, issue_slots[7].wakeup_ports[2].bits.rebusy \n connect slots_7.io.wakeup_ports[2].bits.speculative_mask, issue_slots[7].wakeup_ports[2].bits.speculative_mask \n connect slots_7.io.wakeup_ports[2].bits.bypassable, issue_slots[7].wakeup_ports[2].bits.bypassable \n connect slots_7.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[7].wakeup_ports[2].bits.uop.debug_tsrc \n connect slots_7.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[7].wakeup_ports[2].bits.uop.debug_fsrc \n connect slots_7.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[7].wakeup_ports[2].bits.uop.bp_xcpt_if \n connect slots_7.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[7].wakeup_ports[2].bits.uop.bp_debug_if \n connect slots_7.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[7].wakeup_ports[2].bits.uop.xcpt_ma_if \n connect slots_7.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[7].wakeup_ports[2].bits.uop.xcpt_ae_if \n connect slots_7.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[7].wakeup_ports[2].bits.uop.xcpt_pf_if \n connect slots_7.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[7].wakeup_ports[2].bits.uop.fp_typ \n connect slots_7.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[7].wakeup_ports[2].bits.uop.fp_rm \n connect slots_7.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[7].wakeup_ports[2].bits.uop.fp_val \n connect slots_7.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[7].wakeup_ports[2].bits.uop.fcn_op \n connect slots_7.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[7].wakeup_ports[2].bits.uop.fcn_dw \n connect slots_7.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[7].wakeup_ports[2].bits.uop.frs3_en \n connect slots_7.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[7].wakeup_ports[2].bits.uop.lrs2_rtype \n connect slots_7.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[7].wakeup_ports[2].bits.uop.lrs1_rtype \n connect slots_7.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[7].wakeup_ports[2].bits.uop.dst_rtype \n connect slots_7.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[7].wakeup_ports[2].bits.uop.lrs3 \n connect slots_7.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[7].wakeup_ports[2].bits.uop.lrs2 \n connect slots_7.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[7].wakeup_ports[2].bits.uop.lrs1 \n connect slots_7.io.wakeup_ports[2].bits.uop.ldst, issue_slots[7].wakeup_ports[2].bits.uop.ldst \n connect slots_7.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[7].wakeup_ports[2].bits.uop.ldst_is_rs1 \n connect slots_7.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[7].wakeup_ports[2].bits.uop.csr_cmd \n connect slots_7.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[7].wakeup_ports[2].bits.uop.flush_on_commit \n connect slots_7.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[7].wakeup_ports[2].bits.uop.is_unique \n connect slots_7.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[7].wakeup_ports[2].bits.uop.uses_stq \n connect slots_7.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[7].wakeup_ports[2].bits.uop.uses_ldq \n connect slots_7.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[7].wakeup_ports[2].bits.uop.mem_signed \n connect slots_7.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[7].wakeup_ports[2].bits.uop.mem_size \n connect slots_7.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[7].wakeup_ports[2].bits.uop.mem_cmd \n connect slots_7.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[7].wakeup_ports[2].bits.uop.exc_cause \n connect slots_7.io.wakeup_ports[2].bits.uop.exception, issue_slots[7].wakeup_ports[2].bits.uop.exception \n connect slots_7.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[7].wakeup_ports[2].bits.uop.stale_pdst \n connect slots_7.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[7].wakeup_ports[2].bits.uop.ppred_busy \n connect slots_7.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[7].wakeup_ports[2].bits.uop.prs3_busy \n connect slots_7.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[7].wakeup_ports[2].bits.uop.prs2_busy \n connect slots_7.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[7].wakeup_ports[2].bits.uop.prs1_busy \n connect slots_7.io.wakeup_ports[2].bits.uop.ppred, issue_slots[7].wakeup_ports[2].bits.uop.ppred \n connect slots_7.io.wakeup_ports[2].bits.uop.prs3, issue_slots[7].wakeup_ports[2].bits.uop.prs3 \n connect slots_7.io.wakeup_ports[2].bits.uop.prs2, issue_slots[7].wakeup_ports[2].bits.uop.prs2 \n connect slots_7.io.wakeup_ports[2].bits.uop.prs1, issue_slots[7].wakeup_ports[2].bits.uop.prs1 \n connect slots_7.io.wakeup_ports[2].bits.uop.pdst, issue_slots[7].wakeup_ports[2].bits.uop.pdst \n connect slots_7.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[7].wakeup_ports[2].bits.uop.rxq_idx \n connect slots_7.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[7].wakeup_ports[2].bits.uop.stq_idx \n connect slots_7.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[7].wakeup_ports[2].bits.uop.ldq_idx \n connect slots_7.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[7].wakeup_ports[2].bits.uop.rob_idx \n connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.vec \n connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.wflags \n connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.sqrt \n connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.div \n connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.fma \n connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe \n connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.toint \n connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.fromint \n connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut \n connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn \n connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.swap23 \n connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.swap12 \n connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.ren3 \n connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.ren2 \n connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.ren1 \n connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.wen \n connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.ldst \n connect slots_7.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[7].wakeup_ports[2].bits.uop.op2_sel \n connect slots_7.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[7].wakeup_ports[2].bits.uop.op1_sel \n connect slots_7.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[7].wakeup_ports[2].bits.uop.imm_packed \n connect slots_7.io.wakeup_ports[2].bits.uop.pimm, issue_slots[7].wakeup_ports[2].bits.uop.pimm \n connect slots_7.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[7].wakeup_ports[2].bits.uop.imm_sel \n connect slots_7.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[7].wakeup_ports[2].bits.uop.imm_rename \n connect slots_7.io.wakeup_ports[2].bits.uop.taken, issue_slots[7].wakeup_ports[2].bits.uop.taken \n connect slots_7.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[7].wakeup_ports[2].bits.uop.pc_lob \n connect slots_7.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[7].wakeup_ports[2].bits.uop.edge_inst \n connect slots_7.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[7].wakeup_ports[2].bits.uop.ftq_idx \n connect slots_7.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[7].wakeup_ports[2].bits.uop.is_mov \n connect slots_7.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[7].wakeup_ports[2].bits.uop.is_rocc \n connect slots_7.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[7].wakeup_ports[2].bits.uop.is_sys_pc2epc \n connect slots_7.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[7].wakeup_ports[2].bits.uop.is_eret \n connect slots_7.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[7].wakeup_ports[2].bits.uop.is_amo \n connect slots_7.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[7].wakeup_ports[2].bits.uop.is_sfence \n connect slots_7.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[7].wakeup_ports[2].bits.uop.is_fencei \n connect slots_7.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[7].wakeup_ports[2].bits.uop.is_fence \n connect slots_7.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[7].wakeup_ports[2].bits.uop.is_sfb \n connect slots_7.io.wakeup_ports[2].bits.uop.br_type, issue_slots[7].wakeup_ports[2].bits.uop.br_type \n connect slots_7.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[7].wakeup_ports[2].bits.uop.br_tag \n connect slots_7.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[7].wakeup_ports[2].bits.uop.br_mask \n connect slots_7.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[7].wakeup_ports[2].bits.uop.dis_col_sel \n connect slots_7.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[7].wakeup_ports[2].bits.uop.iw_p3_bypass_hint \n connect slots_7.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[7].wakeup_ports[2].bits.uop.iw_p2_bypass_hint \n connect slots_7.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[7].wakeup_ports[2].bits.uop.iw_p1_bypass_hint \n connect slots_7.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[7].wakeup_ports[2].bits.uop.iw_p2_speculative_child \n connect slots_7.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[7].wakeup_ports[2].bits.uop.iw_p1_speculative_child \n connect slots_7.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[7].wakeup_ports[2].bits.uop.iw_issued_partial_dgen \n connect slots_7.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[7].wakeup_ports[2].bits.uop.iw_issued_partial_agen \n connect slots_7.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[7].wakeup_ports[2].bits.uop.iw_issued \n connect slots_7.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[7].wakeup_ports[2].bits.uop.fu_code[0] \n connect slots_7.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[7].wakeup_ports[2].bits.uop.fu_code[1] \n connect slots_7.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[7].wakeup_ports[2].bits.uop.fu_code[2] \n connect slots_7.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[7].wakeup_ports[2].bits.uop.fu_code[3] \n connect slots_7.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[7].wakeup_ports[2].bits.uop.fu_code[4] \n connect slots_7.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[7].wakeup_ports[2].bits.uop.fu_code[5] \n connect slots_7.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[7].wakeup_ports[2].bits.uop.fu_code[6] \n connect slots_7.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[7].wakeup_ports[2].bits.uop.fu_code[7] \n connect slots_7.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[7].wakeup_ports[2].bits.uop.fu_code[8] \n connect slots_7.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[7].wakeup_ports[2].bits.uop.fu_code[9] \n connect slots_7.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[7].wakeup_ports[2].bits.uop.iq_type[0] \n connect slots_7.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[7].wakeup_ports[2].bits.uop.iq_type[1] \n connect slots_7.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[7].wakeup_ports[2].bits.uop.iq_type[2] \n connect slots_7.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[7].wakeup_ports[2].bits.uop.iq_type[3] \n connect slots_7.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[7].wakeup_ports[2].bits.uop.debug_pc \n connect slots_7.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[7].wakeup_ports[2].bits.uop.is_rvc \n connect slots_7.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[7].wakeup_ports[2].bits.uop.debug_inst \n connect slots_7.io.wakeup_ports[2].bits.uop.inst, issue_slots[7].wakeup_ports[2].bits.uop.inst \n connect slots_7.io.wakeup_ports[2].valid, issue_slots[7].wakeup_ports[2].valid \n connect slots_7.io.wakeup_ports[3].bits.rebusy, issue_slots[7].wakeup_ports[3].bits.rebusy \n connect slots_7.io.wakeup_ports[3].bits.speculative_mask, issue_slots[7].wakeup_ports[3].bits.speculative_mask \n connect slots_7.io.wakeup_ports[3].bits.bypassable, issue_slots[7].wakeup_ports[3].bits.bypassable \n connect slots_7.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[7].wakeup_ports[3].bits.uop.debug_tsrc \n connect slots_7.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[7].wakeup_ports[3].bits.uop.debug_fsrc \n connect slots_7.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[7].wakeup_ports[3].bits.uop.bp_xcpt_if \n connect slots_7.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[7].wakeup_ports[3].bits.uop.bp_debug_if \n connect slots_7.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[7].wakeup_ports[3].bits.uop.xcpt_ma_if \n connect slots_7.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[7].wakeup_ports[3].bits.uop.xcpt_ae_if \n connect slots_7.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[7].wakeup_ports[3].bits.uop.xcpt_pf_if \n connect slots_7.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[7].wakeup_ports[3].bits.uop.fp_typ \n connect slots_7.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[7].wakeup_ports[3].bits.uop.fp_rm \n connect slots_7.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[7].wakeup_ports[3].bits.uop.fp_val \n connect slots_7.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[7].wakeup_ports[3].bits.uop.fcn_op \n connect slots_7.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[7].wakeup_ports[3].bits.uop.fcn_dw \n connect slots_7.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[7].wakeup_ports[3].bits.uop.frs3_en \n connect slots_7.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[7].wakeup_ports[3].bits.uop.lrs2_rtype \n connect slots_7.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[7].wakeup_ports[3].bits.uop.lrs1_rtype \n connect slots_7.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[7].wakeup_ports[3].bits.uop.dst_rtype \n connect slots_7.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[7].wakeup_ports[3].bits.uop.lrs3 \n connect slots_7.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[7].wakeup_ports[3].bits.uop.lrs2 \n connect slots_7.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[7].wakeup_ports[3].bits.uop.lrs1 \n connect slots_7.io.wakeup_ports[3].bits.uop.ldst, issue_slots[7].wakeup_ports[3].bits.uop.ldst \n connect slots_7.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[7].wakeup_ports[3].bits.uop.ldst_is_rs1 \n connect slots_7.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[7].wakeup_ports[3].bits.uop.csr_cmd \n connect slots_7.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[7].wakeup_ports[3].bits.uop.flush_on_commit \n connect slots_7.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[7].wakeup_ports[3].bits.uop.is_unique \n connect slots_7.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[7].wakeup_ports[3].bits.uop.uses_stq \n connect slots_7.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[7].wakeup_ports[3].bits.uop.uses_ldq \n connect slots_7.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[7].wakeup_ports[3].bits.uop.mem_signed \n connect slots_7.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[7].wakeup_ports[3].bits.uop.mem_size \n connect slots_7.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[7].wakeup_ports[3].bits.uop.mem_cmd \n connect slots_7.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[7].wakeup_ports[3].bits.uop.exc_cause \n connect slots_7.io.wakeup_ports[3].bits.uop.exception, issue_slots[7].wakeup_ports[3].bits.uop.exception \n connect slots_7.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[7].wakeup_ports[3].bits.uop.stale_pdst \n connect slots_7.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[7].wakeup_ports[3].bits.uop.ppred_busy \n connect slots_7.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[7].wakeup_ports[3].bits.uop.prs3_busy \n connect slots_7.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[7].wakeup_ports[3].bits.uop.prs2_busy \n connect slots_7.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[7].wakeup_ports[3].bits.uop.prs1_busy \n connect slots_7.io.wakeup_ports[3].bits.uop.ppred, issue_slots[7].wakeup_ports[3].bits.uop.ppred \n connect slots_7.io.wakeup_ports[3].bits.uop.prs3, issue_slots[7].wakeup_ports[3].bits.uop.prs3 \n connect slots_7.io.wakeup_ports[3].bits.uop.prs2, issue_slots[7].wakeup_ports[3].bits.uop.prs2 \n connect slots_7.io.wakeup_ports[3].bits.uop.prs1, issue_slots[7].wakeup_ports[3].bits.uop.prs1 \n connect slots_7.io.wakeup_ports[3].bits.uop.pdst, issue_slots[7].wakeup_ports[3].bits.uop.pdst \n connect slots_7.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[7].wakeup_ports[3].bits.uop.rxq_idx \n connect slots_7.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[7].wakeup_ports[3].bits.uop.stq_idx \n connect slots_7.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[7].wakeup_ports[3].bits.uop.ldq_idx \n connect slots_7.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[7].wakeup_ports[3].bits.uop.rob_idx \n connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.vec \n connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.wflags \n connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.sqrt \n connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.div \n connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.fma \n connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe \n connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.toint \n connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.fromint \n connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut \n connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn \n connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.swap23 \n connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.swap12 \n connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.ren3 \n connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.ren2 \n connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.ren1 \n connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.wen \n connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.ldst \n connect slots_7.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[7].wakeup_ports[3].bits.uop.op2_sel \n connect slots_7.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[7].wakeup_ports[3].bits.uop.op1_sel \n connect slots_7.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[7].wakeup_ports[3].bits.uop.imm_packed \n connect slots_7.io.wakeup_ports[3].bits.uop.pimm, issue_slots[7].wakeup_ports[3].bits.uop.pimm \n connect slots_7.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[7].wakeup_ports[3].bits.uop.imm_sel \n connect slots_7.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[7].wakeup_ports[3].bits.uop.imm_rename \n connect slots_7.io.wakeup_ports[3].bits.uop.taken, issue_slots[7].wakeup_ports[3].bits.uop.taken \n connect slots_7.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[7].wakeup_ports[3].bits.uop.pc_lob \n connect slots_7.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[7].wakeup_ports[3].bits.uop.edge_inst \n connect slots_7.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[7].wakeup_ports[3].bits.uop.ftq_idx \n connect slots_7.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[7].wakeup_ports[3].bits.uop.is_mov \n connect slots_7.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[7].wakeup_ports[3].bits.uop.is_rocc \n connect slots_7.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[7].wakeup_ports[3].bits.uop.is_sys_pc2epc \n connect slots_7.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[7].wakeup_ports[3].bits.uop.is_eret \n connect slots_7.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[7].wakeup_ports[3].bits.uop.is_amo \n connect slots_7.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[7].wakeup_ports[3].bits.uop.is_sfence \n connect slots_7.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[7].wakeup_ports[3].bits.uop.is_fencei \n connect slots_7.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[7].wakeup_ports[3].bits.uop.is_fence \n connect slots_7.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[7].wakeup_ports[3].bits.uop.is_sfb \n connect slots_7.io.wakeup_ports[3].bits.uop.br_type, issue_slots[7].wakeup_ports[3].bits.uop.br_type \n connect slots_7.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[7].wakeup_ports[3].bits.uop.br_tag \n connect slots_7.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[7].wakeup_ports[3].bits.uop.br_mask \n connect slots_7.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[7].wakeup_ports[3].bits.uop.dis_col_sel \n connect slots_7.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[7].wakeup_ports[3].bits.uop.iw_p3_bypass_hint \n connect slots_7.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[7].wakeup_ports[3].bits.uop.iw_p2_bypass_hint \n connect slots_7.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[7].wakeup_ports[3].bits.uop.iw_p1_bypass_hint \n connect slots_7.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[7].wakeup_ports[3].bits.uop.iw_p2_speculative_child \n connect slots_7.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[7].wakeup_ports[3].bits.uop.iw_p1_speculative_child \n connect slots_7.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[7].wakeup_ports[3].bits.uop.iw_issued_partial_dgen \n connect slots_7.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[7].wakeup_ports[3].bits.uop.iw_issued_partial_agen \n connect slots_7.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[7].wakeup_ports[3].bits.uop.iw_issued \n connect slots_7.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[7].wakeup_ports[3].bits.uop.fu_code[0] \n connect slots_7.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[7].wakeup_ports[3].bits.uop.fu_code[1] \n connect slots_7.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[7].wakeup_ports[3].bits.uop.fu_code[2] \n connect slots_7.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[7].wakeup_ports[3].bits.uop.fu_code[3] \n connect slots_7.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[7].wakeup_ports[3].bits.uop.fu_code[4] \n connect slots_7.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[7].wakeup_ports[3].bits.uop.fu_code[5] \n connect slots_7.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[7].wakeup_ports[3].bits.uop.fu_code[6] \n connect slots_7.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[7].wakeup_ports[3].bits.uop.fu_code[7] \n connect slots_7.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[7].wakeup_ports[3].bits.uop.fu_code[8] \n connect slots_7.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[7].wakeup_ports[3].bits.uop.fu_code[9] \n connect slots_7.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[7].wakeup_ports[3].bits.uop.iq_type[0] \n connect slots_7.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[7].wakeup_ports[3].bits.uop.iq_type[1] \n connect slots_7.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[7].wakeup_ports[3].bits.uop.iq_type[2] \n connect slots_7.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[7].wakeup_ports[3].bits.uop.iq_type[3] \n connect slots_7.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[7].wakeup_ports[3].bits.uop.debug_pc \n connect slots_7.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[7].wakeup_ports[3].bits.uop.is_rvc \n connect slots_7.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[7].wakeup_ports[3].bits.uop.debug_inst \n connect slots_7.io.wakeup_ports[3].bits.uop.inst, issue_slots[7].wakeup_ports[3].bits.uop.inst \n connect slots_7.io.wakeup_ports[3].valid, issue_slots[7].wakeup_ports[3].valid \n connect slots_7.io.squash_grant, issue_slots[7].squash_grant \n connect slots_7.io.clear, issue_slots[7].clear \n connect slots_7.io.kill, issue_slots[7].kill \n connect slots_7.io.brupdate.b2.target_offset, issue_slots[7].brupdate.b2.target_offset \n connect slots_7.io.brupdate.b2.jalr_target, issue_slots[7].brupdate.b2.jalr_target \n connect slots_7.io.brupdate.b2.pc_sel, issue_slots[7].brupdate.b2.pc_sel \n connect slots_7.io.brupdate.b2.cfi_type, issue_slots[7].brupdate.b2.cfi_type \n connect slots_7.io.brupdate.b2.taken, issue_slots[7].brupdate.b2.taken \n connect slots_7.io.brupdate.b2.mispredict, issue_slots[7].brupdate.b2.mispredict \n connect slots_7.io.brupdate.b2.uop.debug_tsrc, issue_slots[7].brupdate.b2.uop.debug_tsrc \n connect slots_7.io.brupdate.b2.uop.debug_fsrc, issue_slots[7].brupdate.b2.uop.debug_fsrc \n connect slots_7.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[7].brupdate.b2.uop.bp_xcpt_if \n connect slots_7.io.brupdate.b2.uop.bp_debug_if, issue_slots[7].brupdate.b2.uop.bp_debug_if \n connect slots_7.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[7].brupdate.b2.uop.xcpt_ma_if \n connect slots_7.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[7].brupdate.b2.uop.xcpt_ae_if \n connect slots_7.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[7].brupdate.b2.uop.xcpt_pf_if \n connect slots_7.io.brupdate.b2.uop.fp_typ, issue_slots[7].brupdate.b2.uop.fp_typ \n connect slots_7.io.brupdate.b2.uop.fp_rm, issue_slots[7].brupdate.b2.uop.fp_rm \n connect slots_7.io.brupdate.b2.uop.fp_val, issue_slots[7].brupdate.b2.uop.fp_val \n connect slots_7.io.brupdate.b2.uop.fcn_op, issue_slots[7].brupdate.b2.uop.fcn_op \n connect slots_7.io.brupdate.b2.uop.fcn_dw, issue_slots[7].brupdate.b2.uop.fcn_dw \n connect slots_7.io.brupdate.b2.uop.frs3_en, issue_slots[7].brupdate.b2.uop.frs3_en \n connect slots_7.io.brupdate.b2.uop.lrs2_rtype, issue_slots[7].brupdate.b2.uop.lrs2_rtype \n connect slots_7.io.brupdate.b2.uop.lrs1_rtype, issue_slots[7].brupdate.b2.uop.lrs1_rtype \n connect slots_7.io.brupdate.b2.uop.dst_rtype, issue_slots[7].brupdate.b2.uop.dst_rtype \n connect slots_7.io.brupdate.b2.uop.lrs3, issue_slots[7].brupdate.b2.uop.lrs3 \n connect slots_7.io.brupdate.b2.uop.lrs2, issue_slots[7].brupdate.b2.uop.lrs2 \n connect slots_7.io.brupdate.b2.uop.lrs1, issue_slots[7].brupdate.b2.uop.lrs1 \n connect slots_7.io.brupdate.b2.uop.ldst, issue_slots[7].brupdate.b2.uop.ldst \n connect slots_7.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[7].brupdate.b2.uop.ldst_is_rs1 \n connect slots_7.io.brupdate.b2.uop.csr_cmd, issue_slots[7].brupdate.b2.uop.csr_cmd \n connect slots_7.io.brupdate.b2.uop.flush_on_commit, issue_slots[7].brupdate.b2.uop.flush_on_commit \n connect slots_7.io.brupdate.b2.uop.is_unique, issue_slots[7].brupdate.b2.uop.is_unique \n connect slots_7.io.brupdate.b2.uop.uses_stq, issue_slots[7].brupdate.b2.uop.uses_stq \n connect slots_7.io.brupdate.b2.uop.uses_ldq, issue_slots[7].brupdate.b2.uop.uses_ldq \n connect slots_7.io.brupdate.b2.uop.mem_signed, issue_slots[7].brupdate.b2.uop.mem_signed \n connect slots_7.io.brupdate.b2.uop.mem_size, issue_slots[7].brupdate.b2.uop.mem_size \n connect slots_7.io.brupdate.b2.uop.mem_cmd, issue_slots[7].brupdate.b2.uop.mem_cmd \n connect slots_7.io.brupdate.b2.uop.exc_cause, issue_slots[7].brupdate.b2.uop.exc_cause \n connect slots_7.io.brupdate.b2.uop.exception, issue_slots[7].brupdate.b2.uop.exception \n connect slots_7.io.brupdate.b2.uop.stale_pdst, issue_slots[7].brupdate.b2.uop.stale_pdst \n connect slots_7.io.brupdate.b2.uop.ppred_busy, issue_slots[7].brupdate.b2.uop.ppred_busy \n connect slots_7.io.brupdate.b2.uop.prs3_busy, issue_slots[7].brupdate.b2.uop.prs3_busy \n connect slots_7.io.brupdate.b2.uop.prs2_busy, issue_slots[7].brupdate.b2.uop.prs2_busy \n connect slots_7.io.brupdate.b2.uop.prs1_busy, issue_slots[7].brupdate.b2.uop.prs1_busy \n connect slots_7.io.brupdate.b2.uop.ppred, issue_slots[7].brupdate.b2.uop.ppred \n connect slots_7.io.brupdate.b2.uop.prs3, issue_slots[7].brupdate.b2.uop.prs3 \n connect slots_7.io.brupdate.b2.uop.prs2, issue_slots[7].brupdate.b2.uop.prs2 \n connect slots_7.io.brupdate.b2.uop.prs1, issue_slots[7].brupdate.b2.uop.prs1 \n connect slots_7.io.brupdate.b2.uop.pdst, issue_slots[7].brupdate.b2.uop.pdst \n connect slots_7.io.brupdate.b2.uop.rxq_idx, issue_slots[7].brupdate.b2.uop.rxq_idx \n connect slots_7.io.brupdate.b2.uop.stq_idx, issue_slots[7].brupdate.b2.uop.stq_idx \n connect slots_7.io.brupdate.b2.uop.ldq_idx, issue_slots[7].brupdate.b2.uop.ldq_idx \n connect slots_7.io.brupdate.b2.uop.rob_idx, issue_slots[7].brupdate.b2.uop.rob_idx \n connect slots_7.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[7].brupdate.b2.uop.fp_ctrl.vec \n connect slots_7.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[7].brupdate.b2.uop.fp_ctrl.wflags \n connect slots_7.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[7].brupdate.b2.uop.fp_ctrl.sqrt \n connect slots_7.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[7].brupdate.b2.uop.fp_ctrl.div \n connect slots_7.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[7].brupdate.b2.uop.fp_ctrl.fma \n connect slots_7.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[7].brupdate.b2.uop.fp_ctrl.fastpipe \n connect slots_7.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[7].brupdate.b2.uop.fp_ctrl.toint \n connect slots_7.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[7].brupdate.b2.uop.fp_ctrl.fromint \n connect slots_7.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[7].brupdate.b2.uop.fp_ctrl.typeTagOut \n connect slots_7.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[7].brupdate.b2.uop.fp_ctrl.typeTagIn \n connect slots_7.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[7].brupdate.b2.uop.fp_ctrl.swap23 \n connect slots_7.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[7].brupdate.b2.uop.fp_ctrl.swap12 \n connect slots_7.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[7].brupdate.b2.uop.fp_ctrl.ren3 \n connect slots_7.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[7].brupdate.b2.uop.fp_ctrl.ren2 \n connect slots_7.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[7].brupdate.b2.uop.fp_ctrl.ren1 \n connect slots_7.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[7].brupdate.b2.uop.fp_ctrl.wen \n connect slots_7.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[7].brupdate.b2.uop.fp_ctrl.ldst \n connect slots_7.io.brupdate.b2.uop.op2_sel, issue_slots[7].brupdate.b2.uop.op2_sel \n connect slots_7.io.brupdate.b2.uop.op1_sel, issue_slots[7].brupdate.b2.uop.op1_sel \n connect slots_7.io.brupdate.b2.uop.imm_packed, issue_slots[7].brupdate.b2.uop.imm_packed \n connect slots_7.io.brupdate.b2.uop.pimm, issue_slots[7].brupdate.b2.uop.pimm \n connect slots_7.io.brupdate.b2.uop.imm_sel, issue_slots[7].brupdate.b2.uop.imm_sel \n connect slots_7.io.brupdate.b2.uop.imm_rename, issue_slots[7].brupdate.b2.uop.imm_rename \n connect slots_7.io.brupdate.b2.uop.taken, issue_slots[7].brupdate.b2.uop.taken \n connect slots_7.io.brupdate.b2.uop.pc_lob, issue_slots[7].brupdate.b2.uop.pc_lob \n connect slots_7.io.brupdate.b2.uop.edge_inst, issue_slots[7].brupdate.b2.uop.edge_inst \n connect slots_7.io.brupdate.b2.uop.ftq_idx, issue_slots[7].brupdate.b2.uop.ftq_idx \n connect slots_7.io.brupdate.b2.uop.is_mov, issue_slots[7].brupdate.b2.uop.is_mov \n connect slots_7.io.brupdate.b2.uop.is_rocc, issue_slots[7].brupdate.b2.uop.is_rocc \n connect slots_7.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[7].brupdate.b2.uop.is_sys_pc2epc \n connect slots_7.io.brupdate.b2.uop.is_eret, issue_slots[7].brupdate.b2.uop.is_eret \n connect slots_7.io.brupdate.b2.uop.is_amo, issue_slots[7].brupdate.b2.uop.is_amo \n connect slots_7.io.brupdate.b2.uop.is_sfence, issue_slots[7].brupdate.b2.uop.is_sfence \n connect slots_7.io.brupdate.b2.uop.is_fencei, issue_slots[7].brupdate.b2.uop.is_fencei \n connect slots_7.io.brupdate.b2.uop.is_fence, issue_slots[7].brupdate.b2.uop.is_fence \n connect slots_7.io.brupdate.b2.uop.is_sfb, issue_slots[7].brupdate.b2.uop.is_sfb \n connect slots_7.io.brupdate.b2.uop.br_type, issue_slots[7].brupdate.b2.uop.br_type \n connect slots_7.io.brupdate.b2.uop.br_tag, issue_slots[7].brupdate.b2.uop.br_tag \n connect slots_7.io.brupdate.b2.uop.br_mask, issue_slots[7].brupdate.b2.uop.br_mask \n connect slots_7.io.brupdate.b2.uop.dis_col_sel, issue_slots[7].brupdate.b2.uop.dis_col_sel \n connect slots_7.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[7].brupdate.b2.uop.iw_p3_bypass_hint \n connect slots_7.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[7].brupdate.b2.uop.iw_p2_bypass_hint \n connect slots_7.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[7].brupdate.b2.uop.iw_p1_bypass_hint \n connect slots_7.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[7].brupdate.b2.uop.iw_p2_speculative_child \n connect slots_7.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[7].brupdate.b2.uop.iw_p1_speculative_child \n connect slots_7.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[7].brupdate.b2.uop.iw_issued_partial_dgen \n connect slots_7.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[7].brupdate.b2.uop.iw_issued_partial_agen \n connect slots_7.io.brupdate.b2.uop.iw_issued, issue_slots[7].brupdate.b2.uop.iw_issued \n connect slots_7.io.brupdate.b2.uop.fu_code[0], issue_slots[7].brupdate.b2.uop.fu_code[0] \n connect slots_7.io.brupdate.b2.uop.fu_code[1], issue_slots[7].brupdate.b2.uop.fu_code[1] \n connect slots_7.io.brupdate.b2.uop.fu_code[2], issue_slots[7].brupdate.b2.uop.fu_code[2] \n connect slots_7.io.brupdate.b2.uop.fu_code[3], issue_slots[7].brupdate.b2.uop.fu_code[3] \n connect slots_7.io.brupdate.b2.uop.fu_code[4], issue_slots[7].brupdate.b2.uop.fu_code[4] \n connect slots_7.io.brupdate.b2.uop.fu_code[5], issue_slots[7].brupdate.b2.uop.fu_code[5] \n connect slots_7.io.brupdate.b2.uop.fu_code[6], issue_slots[7].brupdate.b2.uop.fu_code[6] \n connect slots_7.io.brupdate.b2.uop.fu_code[7], issue_slots[7].brupdate.b2.uop.fu_code[7] \n connect slots_7.io.brupdate.b2.uop.fu_code[8], issue_slots[7].brupdate.b2.uop.fu_code[8] \n connect slots_7.io.brupdate.b2.uop.fu_code[9], issue_slots[7].brupdate.b2.uop.fu_code[9] \n connect slots_7.io.brupdate.b2.uop.iq_type[0], issue_slots[7].brupdate.b2.uop.iq_type[0] \n connect slots_7.io.brupdate.b2.uop.iq_type[1], issue_slots[7].brupdate.b2.uop.iq_type[1] \n connect slots_7.io.brupdate.b2.uop.iq_type[2], issue_slots[7].brupdate.b2.uop.iq_type[2] \n connect slots_7.io.brupdate.b2.uop.iq_type[3], issue_slots[7].brupdate.b2.uop.iq_type[3] \n connect slots_7.io.brupdate.b2.uop.debug_pc, issue_slots[7].brupdate.b2.uop.debug_pc \n connect slots_7.io.brupdate.b2.uop.is_rvc, issue_slots[7].brupdate.b2.uop.is_rvc \n connect slots_7.io.brupdate.b2.uop.debug_inst, issue_slots[7].brupdate.b2.uop.debug_inst \n connect slots_7.io.brupdate.b2.uop.inst, issue_slots[7].brupdate.b2.uop.inst \n connect slots_7.io.brupdate.b1.mispredict_mask, issue_slots[7].brupdate.b1.mispredict_mask \n connect slots_7.io.brupdate.b1.resolve_mask, issue_slots[7].brupdate.b1.resolve_mask \n connect issue_slots[7].out_uop.debug_tsrc, slots_7.io.out_uop.debug_tsrc \n connect issue_slots[7].out_uop.debug_fsrc, slots_7.io.out_uop.debug_fsrc \n connect issue_slots[7].out_uop.bp_xcpt_if, slots_7.io.out_uop.bp_xcpt_if \n connect issue_slots[7].out_uop.bp_debug_if, slots_7.io.out_uop.bp_debug_if \n connect issue_slots[7].out_uop.xcpt_ma_if, slots_7.io.out_uop.xcpt_ma_if \n connect issue_slots[7].out_uop.xcpt_ae_if, slots_7.io.out_uop.xcpt_ae_if \n connect issue_slots[7].out_uop.xcpt_pf_if, slots_7.io.out_uop.xcpt_pf_if \n connect issue_slots[7].out_uop.fp_typ, slots_7.io.out_uop.fp_typ \n connect issue_slots[7].out_uop.fp_rm, slots_7.io.out_uop.fp_rm \n connect issue_slots[7].out_uop.fp_val, slots_7.io.out_uop.fp_val \n connect issue_slots[7].out_uop.fcn_op, slots_7.io.out_uop.fcn_op \n connect issue_slots[7].out_uop.fcn_dw, slots_7.io.out_uop.fcn_dw \n connect issue_slots[7].out_uop.frs3_en, slots_7.io.out_uop.frs3_en \n connect issue_slots[7].out_uop.lrs2_rtype, slots_7.io.out_uop.lrs2_rtype \n connect issue_slots[7].out_uop.lrs1_rtype, slots_7.io.out_uop.lrs1_rtype \n connect issue_slots[7].out_uop.dst_rtype, slots_7.io.out_uop.dst_rtype \n connect issue_slots[7].out_uop.lrs3, slots_7.io.out_uop.lrs3 \n connect issue_slots[7].out_uop.lrs2, slots_7.io.out_uop.lrs2 \n connect issue_slots[7].out_uop.lrs1, slots_7.io.out_uop.lrs1 \n connect issue_slots[7].out_uop.ldst, slots_7.io.out_uop.ldst \n connect issue_slots[7].out_uop.ldst_is_rs1, slots_7.io.out_uop.ldst_is_rs1 \n connect issue_slots[7].out_uop.csr_cmd, slots_7.io.out_uop.csr_cmd \n connect issue_slots[7].out_uop.flush_on_commit, slots_7.io.out_uop.flush_on_commit \n connect issue_slots[7].out_uop.is_unique, slots_7.io.out_uop.is_unique \n connect issue_slots[7].out_uop.uses_stq, slots_7.io.out_uop.uses_stq \n connect issue_slots[7].out_uop.uses_ldq, slots_7.io.out_uop.uses_ldq \n connect issue_slots[7].out_uop.mem_signed, slots_7.io.out_uop.mem_signed \n connect issue_slots[7].out_uop.mem_size, slots_7.io.out_uop.mem_size \n connect issue_slots[7].out_uop.mem_cmd, slots_7.io.out_uop.mem_cmd \n connect issue_slots[7].out_uop.exc_cause, slots_7.io.out_uop.exc_cause \n connect issue_slots[7].out_uop.exception, slots_7.io.out_uop.exception \n connect issue_slots[7].out_uop.stale_pdst, slots_7.io.out_uop.stale_pdst \n connect issue_slots[7].out_uop.ppred_busy, slots_7.io.out_uop.ppred_busy \n connect issue_slots[7].out_uop.prs3_busy, slots_7.io.out_uop.prs3_busy \n connect issue_slots[7].out_uop.prs2_busy, slots_7.io.out_uop.prs2_busy \n connect issue_slots[7].out_uop.prs1_busy, slots_7.io.out_uop.prs1_busy \n connect issue_slots[7].out_uop.ppred, slots_7.io.out_uop.ppred \n connect issue_slots[7].out_uop.prs3, slots_7.io.out_uop.prs3 \n connect issue_slots[7].out_uop.prs2, slots_7.io.out_uop.prs2 \n connect issue_slots[7].out_uop.prs1, slots_7.io.out_uop.prs1 \n connect issue_slots[7].out_uop.pdst, slots_7.io.out_uop.pdst \n connect issue_slots[7].out_uop.rxq_idx, slots_7.io.out_uop.rxq_idx \n connect issue_slots[7].out_uop.stq_idx, slots_7.io.out_uop.stq_idx \n connect issue_slots[7].out_uop.ldq_idx, slots_7.io.out_uop.ldq_idx \n connect issue_slots[7].out_uop.rob_idx, slots_7.io.out_uop.rob_idx \n connect issue_slots[7].out_uop.fp_ctrl.vec, slots_7.io.out_uop.fp_ctrl.vec \n connect issue_slots[7].out_uop.fp_ctrl.wflags, slots_7.io.out_uop.fp_ctrl.wflags \n connect issue_slots[7].out_uop.fp_ctrl.sqrt, slots_7.io.out_uop.fp_ctrl.sqrt \n connect issue_slots[7].out_uop.fp_ctrl.div, slots_7.io.out_uop.fp_ctrl.div \n connect issue_slots[7].out_uop.fp_ctrl.fma, slots_7.io.out_uop.fp_ctrl.fma \n connect issue_slots[7].out_uop.fp_ctrl.fastpipe, slots_7.io.out_uop.fp_ctrl.fastpipe \n connect issue_slots[7].out_uop.fp_ctrl.toint, slots_7.io.out_uop.fp_ctrl.toint \n connect issue_slots[7].out_uop.fp_ctrl.fromint, slots_7.io.out_uop.fp_ctrl.fromint \n connect issue_slots[7].out_uop.fp_ctrl.typeTagOut, slots_7.io.out_uop.fp_ctrl.typeTagOut \n connect issue_slots[7].out_uop.fp_ctrl.typeTagIn, slots_7.io.out_uop.fp_ctrl.typeTagIn \n connect issue_slots[7].out_uop.fp_ctrl.swap23, slots_7.io.out_uop.fp_ctrl.swap23 \n connect issue_slots[7].out_uop.fp_ctrl.swap12, slots_7.io.out_uop.fp_ctrl.swap12 \n connect issue_slots[7].out_uop.fp_ctrl.ren3, slots_7.io.out_uop.fp_ctrl.ren3 \n connect issue_slots[7].out_uop.fp_ctrl.ren2, slots_7.io.out_uop.fp_ctrl.ren2 \n connect issue_slots[7].out_uop.fp_ctrl.ren1, slots_7.io.out_uop.fp_ctrl.ren1 \n connect issue_slots[7].out_uop.fp_ctrl.wen, slots_7.io.out_uop.fp_ctrl.wen \n connect issue_slots[7].out_uop.fp_ctrl.ldst, slots_7.io.out_uop.fp_ctrl.ldst \n connect issue_slots[7].out_uop.op2_sel, slots_7.io.out_uop.op2_sel \n connect issue_slots[7].out_uop.op1_sel, slots_7.io.out_uop.op1_sel \n connect issue_slots[7].out_uop.imm_packed, slots_7.io.out_uop.imm_packed \n connect issue_slots[7].out_uop.pimm, slots_7.io.out_uop.pimm \n connect issue_slots[7].out_uop.imm_sel, slots_7.io.out_uop.imm_sel \n connect issue_slots[7].out_uop.imm_rename, slots_7.io.out_uop.imm_rename \n connect issue_slots[7].out_uop.taken, slots_7.io.out_uop.taken \n connect issue_slots[7].out_uop.pc_lob, slots_7.io.out_uop.pc_lob \n connect issue_slots[7].out_uop.edge_inst, slots_7.io.out_uop.edge_inst \n connect issue_slots[7].out_uop.ftq_idx, slots_7.io.out_uop.ftq_idx \n connect issue_slots[7].out_uop.is_mov, slots_7.io.out_uop.is_mov \n connect issue_slots[7].out_uop.is_rocc, slots_7.io.out_uop.is_rocc \n connect issue_slots[7].out_uop.is_sys_pc2epc, slots_7.io.out_uop.is_sys_pc2epc \n connect issue_slots[7].out_uop.is_eret, slots_7.io.out_uop.is_eret \n connect issue_slots[7].out_uop.is_amo, slots_7.io.out_uop.is_amo \n connect issue_slots[7].out_uop.is_sfence, slots_7.io.out_uop.is_sfence \n connect issue_slots[7].out_uop.is_fencei, slots_7.io.out_uop.is_fencei \n connect issue_slots[7].out_uop.is_fence, slots_7.io.out_uop.is_fence \n connect issue_slots[7].out_uop.is_sfb, slots_7.io.out_uop.is_sfb \n connect issue_slots[7].out_uop.br_type, slots_7.io.out_uop.br_type \n connect issue_slots[7].out_uop.br_tag, slots_7.io.out_uop.br_tag \n connect issue_slots[7].out_uop.br_mask, slots_7.io.out_uop.br_mask \n connect issue_slots[7].out_uop.dis_col_sel, slots_7.io.out_uop.dis_col_sel \n connect issue_slots[7].out_uop.iw_p3_bypass_hint, slots_7.io.out_uop.iw_p3_bypass_hint \n connect issue_slots[7].out_uop.iw_p2_bypass_hint, slots_7.io.out_uop.iw_p2_bypass_hint \n connect issue_slots[7].out_uop.iw_p1_bypass_hint, slots_7.io.out_uop.iw_p1_bypass_hint \n connect issue_slots[7].out_uop.iw_p2_speculative_child, slots_7.io.out_uop.iw_p2_speculative_child \n connect issue_slots[7].out_uop.iw_p1_speculative_child, slots_7.io.out_uop.iw_p1_speculative_child \n connect issue_slots[7].out_uop.iw_issued_partial_dgen, slots_7.io.out_uop.iw_issued_partial_dgen \n connect issue_slots[7].out_uop.iw_issued_partial_agen, slots_7.io.out_uop.iw_issued_partial_agen \n connect issue_slots[7].out_uop.iw_issued, slots_7.io.out_uop.iw_issued \n connect issue_slots[7].out_uop.fu_code[0], slots_7.io.out_uop.fu_code[0] \n connect issue_slots[7].out_uop.fu_code[1], slots_7.io.out_uop.fu_code[1] \n connect issue_slots[7].out_uop.fu_code[2], slots_7.io.out_uop.fu_code[2] \n connect issue_slots[7].out_uop.fu_code[3], slots_7.io.out_uop.fu_code[3] \n connect issue_slots[7].out_uop.fu_code[4], slots_7.io.out_uop.fu_code[4] \n connect issue_slots[7].out_uop.fu_code[5], slots_7.io.out_uop.fu_code[5] \n connect issue_slots[7].out_uop.fu_code[6], slots_7.io.out_uop.fu_code[6] \n connect issue_slots[7].out_uop.fu_code[7], slots_7.io.out_uop.fu_code[7] \n connect issue_slots[7].out_uop.fu_code[8], slots_7.io.out_uop.fu_code[8] \n connect issue_slots[7].out_uop.fu_code[9], slots_7.io.out_uop.fu_code[9] \n connect issue_slots[7].out_uop.iq_type[0], slots_7.io.out_uop.iq_type[0] \n connect issue_slots[7].out_uop.iq_type[1], slots_7.io.out_uop.iq_type[1] \n connect issue_slots[7].out_uop.iq_type[2], slots_7.io.out_uop.iq_type[2] \n connect issue_slots[7].out_uop.iq_type[3], slots_7.io.out_uop.iq_type[3] \n connect issue_slots[7].out_uop.debug_pc, slots_7.io.out_uop.debug_pc \n connect issue_slots[7].out_uop.is_rvc, slots_7.io.out_uop.is_rvc \n connect issue_slots[7].out_uop.debug_inst, slots_7.io.out_uop.debug_inst \n connect issue_slots[7].out_uop.inst, slots_7.io.out_uop.inst \n connect slots_7.io.in_uop.bits.debug_tsrc, issue_slots[7].in_uop.bits.debug_tsrc \n connect slots_7.io.in_uop.bits.debug_fsrc, issue_slots[7].in_uop.bits.debug_fsrc \n connect slots_7.io.in_uop.bits.bp_xcpt_if, issue_slots[7].in_uop.bits.bp_xcpt_if \n connect slots_7.io.in_uop.bits.bp_debug_if, issue_slots[7].in_uop.bits.bp_debug_if \n connect slots_7.io.in_uop.bits.xcpt_ma_if, issue_slots[7].in_uop.bits.xcpt_ma_if \n connect slots_7.io.in_uop.bits.xcpt_ae_if, issue_slots[7].in_uop.bits.xcpt_ae_if \n connect slots_7.io.in_uop.bits.xcpt_pf_if, issue_slots[7].in_uop.bits.xcpt_pf_if \n connect slots_7.io.in_uop.bits.fp_typ, issue_slots[7].in_uop.bits.fp_typ \n connect slots_7.io.in_uop.bits.fp_rm, issue_slots[7].in_uop.bits.fp_rm \n connect slots_7.io.in_uop.bits.fp_val, issue_slots[7].in_uop.bits.fp_val \n connect slots_7.io.in_uop.bits.fcn_op, issue_slots[7].in_uop.bits.fcn_op \n connect slots_7.io.in_uop.bits.fcn_dw, issue_slots[7].in_uop.bits.fcn_dw \n connect slots_7.io.in_uop.bits.frs3_en, issue_slots[7].in_uop.bits.frs3_en \n connect slots_7.io.in_uop.bits.lrs2_rtype, issue_slots[7].in_uop.bits.lrs2_rtype \n connect slots_7.io.in_uop.bits.lrs1_rtype, issue_slots[7].in_uop.bits.lrs1_rtype \n connect slots_7.io.in_uop.bits.dst_rtype, issue_slots[7].in_uop.bits.dst_rtype \n connect slots_7.io.in_uop.bits.lrs3, issue_slots[7].in_uop.bits.lrs3 \n connect slots_7.io.in_uop.bits.lrs2, issue_slots[7].in_uop.bits.lrs2 \n connect slots_7.io.in_uop.bits.lrs1, issue_slots[7].in_uop.bits.lrs1 \n connect slots_7.io.in_uop.bits.ldst, issue_slots[7].in_uop.bits.ldst \n connect slots_7.io.in_uop.bits.ldst_is_rs1, issue_slots[7].in_uop.bits.ldst_is_rs1 \n connect slots_7.io.in_uop.bits.csr_cmd, issue_slots[7].in_uop.bits.csr_cmd \n connect slots_7.io.in_uop.bits.flush_on_commit, issue_slots[7].in_uop.bits.flush_on_commit \n connect slots_7.io.in_uop.bits.is_unique, issue_slots[7].in_uop.bits.is_unique \n connect slots_7.io.in_uop.bits.uses_stq, issue_slots[7].in_uop.bits.uses_stq \n connect slots_7.io.in_uop.bits.uses_ldq, issue_slots[7].in_uop.bits.uses_ldq \n connect slots_7.io.in_uop.bits.mem_signed, issue_slots[7].in_uop.bits.mem_signed \n connect slots_7.io.in_uop.bits.mem_size, issue_slots[7].in_uop.bits.mem_size \n connect slots_7.io.in_uop.bits.mem_cmd, issue_slots[7].in_uop.bits.mem_cmd \n connect slots_7.io.in_uop.bits.exc_cause, issue_slots[7].in_uop.bits.exc_cause \n connect slots_7.io.in_uop.bits.exception, issue_slots[7].in_uop.bits.exception \n connect slots_7.io.in_uop.bits.stale_pdst, issue_slots[7].in_uop.bits.stale_pdst \n connect slots_7.io.in_uop.bits.ppred_busy, issue_slots[7].in_uop.bits.ppred_busy \n connect slots_7.io.in_uop.bits.prs3_busy, issue_slots[7].in_uop.bits.prs3_busy \n connect slots_7.io.in_uop.bits.prs2_busy, issue_slots[7].in_uop.bits.prs2_busy \n connect slots_7.io.in_uop.bits.prs1_busy, issue_slots[7].in_uop.bits.prs1_busy \n connect slots_7.io.in_uop.bits.ppred, issue_slots[7].in_uop.bits.ppred \n connect slots_7.io.in_uop.bits.prs3, issue_slots[7].in_uop.bits.prs3 \n connect slots_7.io.in_uop.bits.prs2, issue_slots[7].in_uop.bits.prs2 \n connect slots_7.io.in_uop.bits.prs1, issue_slots[7].in_uop.bits.prs1 \n connect slots_7.io.in_uop.bits.pdst, issue_slots[7].in_uop.bits.pdst \n connect slots_7.io.in_uop.bits.rxq_idx, issue_slots[7].in_uop.bits.rxq_idx \n connect slots_7.io.in_uop.bits.stq_idx, issue_slots[7].in_uop.bits.stq_idx \n connect slots_7.io.in_uop.bits.ldq_idx, issue_slots[7].in_uop.bits.ldq_idx \n connect slots_7.io.in_uop.bits.rob_idx, issue_slots[7].in_uop.bits.rob_idx \n connect slots_7.io.in_uop.bits.fp_ctrl.vec, issue_slots[7].in_uop.bits.fp_ctrl.vec \n connect slots_7.io.in_uop.bits.fp_ctrl.wflags, issue_slots[7].in_uop.bits.fp_ctrl.wflags \n connect slots_7.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[7].in_uop.bits.fp_ctrl.sqrt \n connect slots_7.io.in_uop.bits.fp_ctrl.div, issue_slots[7].in_uop.bits.fp_ctrl.div \n connect slots_7.io.in_uop.bits.fp_ctrl.fma, issue_slots[7].in_uop.bits.fp_ctrl.fma \n connect slots_7.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[7].in_uop.bits.fp_ctrl.fastpipe \n connect slots_7.io.in_uop.bits.fp_ctrl.toint, issue_slots[7].in_uop.bits.fp_ctrl.toint \n connect slots_7.io.in_uop.bits.fp_ctrl.fromint, issue_slots[7].in_uop.bits.fp_ctrl.fromint \n connect slots_7.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[7].in_uop.bits.fp_ctrl.typeTagOut \n connect slots_7.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[7].in_uop.bits.fp_ctrl.typeTagIn \n connect slots_7.io.in_uop.bits.fp_ctrl.swap23, issue_slots[7].in_uop.bits.fp_ctrl.swap23 \n connect slots_7.io.in_uop.bits.fp_ctrl.swap12, issue_slots[7].in_uop.bits.fp_ctrl.swap12 \n connect slots_7.io.in_uop.bits.fp_ctrl.ren3, issue_slots[7].in_uop.bits.fp_ctrl.ren3 \n connect slots_7.io.in_uop.bits.fp_ctrl.ren2, issue_slots[7].in_uop.bits.fp_ctrl.ren2 \n connect slots_7.io.in_uop.bits.fp_ctrl.ren1, issue_slots[7].in_uop.bits.fp_ctrl.ren1 \n connect slots_7.io.in_uop.bits.fp_ctrl.wen, issue_slots[7].in_uop.bits.fp_ctrl.wen \n connect slots_7.io.in_uop.bits.fp_ctrl.ldst, issue_slots[7].in_uop.bits.fp_ctrl.ldst \n connect slots_7.io.in_uop.bits.op2_sel, issue_slots[7].in_uop.bits.op2_sel \n connect slots_7.io.in_uop.bits.op1_sel, issue_slots[7].in_uop.bits.op1_sel \n connect slots_7.io.in_uop.bits.imm_packed, issue_slots[7].in_uop.bits.imm_packed \n connect slots_7.io.in_uop.bits.pimm, issue_slots[7].in_uop.bits.pimm \n connect slots_7.io.in_uop.bits.imm_sel, issue_slots[7].in_uop.bits.imm_sel \n connect slots_7.io.in_uop.bits.imm_rename, issue_slots[7].in_uop.bits.imm_rename \n connect slots_7.io.in_uop.bits.taken, issue_slots[7].in_uop.bits.taken \n connect slots_7.io.in_uop.bits.pc_lob, issue_slots[7].in_uop.bits.pc_lob \n connect slots_7.io.in_uop.bits.edge_inst, issue_slots[7].in_uop.bits.edge_inst \n connect slots_7.io.in_uop.bits.ftq_idx, issue_slots[7].in_uop.bits.ftq_idx \n connect slots_7.io.in_uop.bits.is_mov, issue_slots[7].in_uop.bits.is_mov \n connect slots_7.io.in_uop.bits.is_rocc, issue_slots[7].in_uop.bits.is_rocc \n connect slots_7.io.in_uop.bits.is_sys_pc2epc, issue_slots[7].in_uop.bits.is_sys_pc2epc \n connect slots_7.io.in_uop.bits.is_eret, issue_slots[7].in_uop.bits.is_eret \n connect slots_7.io.in_uop.bits.is_amo, issue_slots[7].in_uop.bits.is_amo \n connect slots_7.io.in_uop.bits.is_sfence, issue_slots[7].in_uop.bits.is_sfence \n connect slots_7.io.in_uop.bits.is_fencei, issue_slots[7].in_uop.bits.is_fencei \n connect slots_7.io.in_uop.bits.is_fence, issue_slots[7].in_uop.bits.is_fence \n connect slots_7.io.in_uop.bits.is_sfb, issue_slots[7].in_uop.bits.is_sfb \n connect slots_7.io.in_uop.bits.br_type, issue_slots[7].in_uop.bits.br_type \n connect slots_7.io.in_uop.bits.br_tag, issue_slots[7].in_uop.bits.br_tag \n connect slots_7.io.in_uop.bits.br_mask, issue_slots[7].in_uop.bits.br_mask \n connect slots_7.io.in_uop.bits.dis_col_sel, issue_slots[7].in_uop.bits.dis_col_sel \n connect slots_7.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[7].in_uop.bits.iw_p3_bypass_hint \n connect slots_7.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[7].in_uop.bits.iw_p2_bypass_hint \n connect slots_7.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[7].in_uop.bits.iw_p1_bypass_hint \n connect slots_7.io.in_uop.bits.iw_p2_speculative_child, issue_slots[7].in_uop.bits.iw_p2_speculative_child \n connect slots_7.io.in_uop.bits.iw_p1_speculative_child, issue_slots[7].in_uop.bits.iw_p1_speculative_child \n connect slots_7.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[7].in_uop.bits.iw_issued_partial_dgen \n connect slots_7.io.in_uop.bits.iw_issued_partial_agen, issue_slots[7].in_uop.bits.iw_issued_partial_agen \n connect slots_7.io.in_uop.bits.iw_issued, issue_slots[7].in_uop.bits.iw_issued \n connect slots_7.io.in_uop.bits.fu_code[0], issue_slots[7].in_uop.bits.fu_code[0] \n connect slots_7.io.in_uop.bits.fu_code[1], issue_slots[7].in_uop.bits.fu_code[1] \n connect slots_7.io.in_uop.bits.fu_code[2], issue_slots[7].in_uop.bits.fu_code[2] \n connect slots_7.io.in_uop.bits.fu_code[3], issue_slots[7].in_uop.bits.fu_code[3] \n connect slots_7.io.in_uop.bits.fu_code[4], issue_slots[7].in_uop.bits.fu_code[4] \n connect slots_7.io.in_uop.bits.fu_code[5], issue_slots[7].in_uop.bits.fu_code[5] \n connect slots_7.io.in_uop.bits.fu_code[6], issue_slots[7].in_uop.bits.fu_code[6] \n connect slots_7.io.in_uop.bits.fu_code[7], issue_slots[7].in_uop.bits.fu_code[7] \n connect slots_7.io.in_uop.bits.fu_code[8], issue_slots[7].in_uop.bits.fu_code[8] \n connect slots_7.io.in_uop.bits.fu_code[9], issue_slots[7].in_uop.bits.fu_code[9] \n connect slots_7.io.in_uop.bits.iq_type[0], issue_slots[7].in_uop.bits.iq_type[0] \n connect slots_7.io.in_uop.bits.iq_type[1], issue_slots[7].in_uop.bits.iq_type[1] \n connect slots_7.io.in_uop.bits.iq_type[2], issue_slots[7].in_uop.bits.iq_type[2] \n connect slots_7.io.in_uop.bits.iq_type[3], issue_slots[7].in_uop.bits.iq_type[3] \n connect slots_7.io.in_uop.bits.debug_pc, issue_slots[7].in_uop.bits.debug_pc \n connect slots_7.io.in_uop.bits.is_rvc, issue_slots[7].in_uop.bits.is_rvc \n connect slots_7.io.in_uop.bits.debug_inst, issue_slots[7].in_uop.bits.debug_inst \n connect slots_7.io.in_uop.bits.inst, issue_slots[7].in_uop.bits.inst \n connect slots_7.io.in_uop.valid, issue_slots[7].in_uop.valid \n connect issue_slots[7].iss_uop.debug_tsrc, slots_7.io.iss_uop.debug_tsrc \n connect issue_slots[7].iss_uop.debug_fsrc, slots_7.io.iss_uop.debug_fsrc \n connect issue_slots[7].iss_uop.bp_xcpt_if, slots_7.io.iss_uop.bp_xcpt_if \n connect issue_slots[7].iss_uop.bp_debug_if, slots_7.io.iss_uop.bp_debug_if \n connect issue_slots[7].iss_uop.xcpt_ma_if, slots_7.io.iss_uop.xcpt_ma_if \n connect issue_slots[7].iss_uop.xcpt_ae_if, slots_7.io.iss_uop.xcpt_ae_if \n connect issue_slots[7].iss_uop.xcpt_pf_if, slots_7.io.iss_uop.xcpt_pf_if \n connect issue_slots[7].iss_uop.fp_typ, slots_7.io.iss_uop.fp_typ \n connect issue_slots[7].iss_uop.fp_rm, slots_7.io.iss_uop.fp_rm \n connect issue_slots[7].iss_uop.fp_val, slots_7.io.iss_uop.fp_val \n connect issue_slots[7].iss_uop.fcn_op, slots_7.io.iss_uop.fcn_op \n connect issue_slots[7].iss_uop.fcn_dw, slots_7.io.iss_uop.fcn_dw \n connect issue_slots[7].iss_uop.frs3_en, slots_7.io.iss_uop.frs3_en \n connect issue_slots[7].iss_uop.lrs2_rtype, slots_7.io.iss_uop.lrs2_rtype \n connect issue_slots[7].iss_uop.lrs1_rtype, slots_7.io.iss_uop.lrs1_rtype \n connect issue_slots[7].iss_uop.dst_rtype, slots_7.io.iss_uop.dst_rtype \n connect issue_slots[7].iss_uop.lrs3, slots_7.io.iss_uop.lrs3 \n connect issue_slots[7].iss_uop.lrs2, slots_7.io.iss_uop.lrs2 \n connect issue_slots[7].iss_uop.lrs1, slots_7.io.iss_uop.lrs1 \n connect issue_slots[7].iss_uop.ldst, slots_7.io.iss_uop.ldst \n connect issue_slots[7].iss_uop.ldst_is_rs1, slots_7.io.iss_uop.ldst_is_rs1 \n connect issue_slots[7].iss_uop.csr_cmd, slots_7.io.iss_uop.csr_cmd \n connect issue_slots[7].iss_uop.flush_on_commit, slots_7.io.iss_uop.flush_on_commit \n connect issue_slots[7].iss_uop.is_unique, slots_7.io.iss_uop.is_unique \n connect issue_slots[7].iss_uop.uses_stq, slots_7.io.iss_uop.uses_stq \n connect issue_slots[7].iss_uop.uses_ldq, slots_7.io.iss_uop.uses_ldq \n connect issue_slots[7].iss_uop.mem_signed, slots_7.io.iss_uop.mem_signed \n connect issue_slots[7].iss_uop.mem_size, slots_7.io.iss_uop.mem_size \n connect issue_slots[7].iss_uop.mem_cmd, slots_7.io.iss_uop.mem_cmd \n connect issue_slots[7].iss_uop.exc_cause, slots_7.io.iss_uop.exc_cause \n connect issue_slots[7].iss_uop.exception, slots_7.io.iss_uop.exception \n connect issue_slots[7].iss_uop.stale_pdst, slots_7.io.iss_uop.stale_pdst \n connect issue_slots[7].iss_uop.ppred_busy, slots_7.io.iss_uop.ppred_busy \n connect issue_slots[7].iss_uop.prs3_busy, slots_7.io.iss_uop.prs3_busy \n connect issue_slots[7].iss_uop.prs2_busy, slots_7.io.iss_uop.prs2_busy \n connect issue_slots[7].iss_uop.prs1_busy, slots_7.io.iss_uop.prs1_busy \n connect issue_slots[7].iss_uop.ppred, slots_7.io.iss_uop.ppred \n connect issue_slots[7].iss_uop.prs3, slots_7.io.iss_uop.prs3 \n connect issue_slots[7].iss_uop.prs2, slots_7.io.iss_uop.prs2 \n connect issue_slots[7].iss_uop.prs1, slots_7.io.iss_uop.prs1 \n connect issue_slots[7].iss_uop.pdst, slots_7.io.iss_uop.pdst \n connect issue_slots[7].iss_uop.rxq_idx, slots_7.io.iss_uop.rxq_idx \n connect issue_slots[7].iss_uop.stq_idx, slots_7.io.iss_uop.stq_idx \n connect issue_slots[7].iss_uop.ldq_idx, slots_7.io.iss_uop.ldq_idx \n connect issue_slots[7].iss_uop.rob_idx, slots_7.io.iss_uop.rob_idx \n connect issue_slots[7].iss_uop.fp_ctrl.vec, slots_7.io.iss_uop.fp_ctrl.vec \n connect issue_slots[7].iss_uop.fp_ctrl.wflags, slots_7.io.iss_uop.fp_ctrl.wflags \n connect issue_slots[7].iss_uop.fp_ctrl.sqrt, slots_7.io.iss_uop.fp_ctrl.sqrt \n connect issue_slots[7].iss_uop.fp_ctrl.div, slots_7.io.iss_uop.fp_ctrl.div \n connect issue_slots[7].iss_uop.fp_ctrl.fma, slots_7.io.iss_uop.fp_ctrl.fma \n connect issue_slots[7].iss_uop.fp_ctrl.fastpipe, slots_7.io.iss_uop.fp_ctrl.fastpipe \n connect issue_slots[7].iss_uop.fp_ctrl.toint, slots_7.io.iss_uop.fp_ctrl.toint \n connect issue_slots[7].iss_uop.fp_ctrl.fromint, slots_7.io.iss_uop.fp_ctrl.fromint \n connect issue_slots[7].iss_uop.fp_ctrl.typeTagOut, slots_7.io.iss_uop.fp_ctrl.typeTagOut \n connect issue_slots[7].iss_uop.fp_ctrl.typeTagIn, slots_7.io.iss_uop.fp_ctrl.typeTagIn \n connect issue_slots[7].iss_uop.fp_ctrl.swap23, slots_7.io.iss_uop.fp_ctrl.swap23 \n connect issue_slots[7].iss_uop.fp_ctrl.swap12, slots_7.io.iss_uop.fp_ctrl.swap12 \n connect issue_slots[7].iss_uop.fp_ctrl.ren3, slots_7.io.iss_uop.fp_ctrl.ren3 \n connect issue_slots[7].iss_uop.fp_ctrl.ren2, slots_7.io.iss_uop.fp_ctrl.ren2 \n connect issue_slots[7].iss_uop.fp_ctrl.ren1, slots_7.io.iss_uop.fp_ctrl.ren1 \n connect issue_slots[7].iss_uop.fp_ctrl.wen, slots_7.io.iss_uop.fp_ctrl.wen \n connect issue_slots[7].iss_uop.fp_ctrl.ldst, slots_7.io.iss_uop.fp_ctrl.ldst \n connect issue_slots[7].iss_uop.op2_sel, slots_7.io.iss_uop.op2_sel \n connect issue_slots[7].iss_uop.op1_sel, slots_7.io.iss_uop.op1_sel \n connect issue_slots[7].iss_uop.imm_packed, slots_7.io.iss_uop.imm_packed \n connect issue_slots[7].iss_uop.pimm, slots_7.io.iss_uop.pimm \n connect issue_slots[7].iss_uop.imm_sel, slots_7.io.iss_uop.imm_sel \n connect issue_slots[7].iss_uop.imm_rename, slots_7.io.iss_uop.imm_rename \n connect issue_slots[7].iss_uop.taken, slots_7.io.iss_uop.taken \n connect issue_slots[7].iss_uop.pc_lob, slots_7.io.iss_uop.pc_lob \n connect issue_slots[7].iss_uop.edge_inst, slots_7.io.iss_uop.edge_inst \n connect issue_slots[7].iss_uop.ftq_idx, slots_7.io.iss_uop.ftq_idx \n connect issue_slots[7].iss_uop.is_mov, slots_7.io.iss_uop.is_mov \n connect issue_slots[7].iss_uop.is_rocc, slots_7.io.iss_uop.is_rocc \n connect issue_slots[7].iss_uop.is_sys_pc2epc, slots_7.io.iss_uop.is_sys_pc2epc \n connect issue_slots[7].iss_uop.is_eret, slots_7.io.iss_uop.is_eret \n connect issue_slots[7].iss_uop.is_amo, slots_7.io.iss_uop.is_amo \n connect issue_slots[7].iss_uop.is_sfence, slots_7.io.iss_uop.is_sfence \n connect issue_slots[7].iss_uop.is_fencei, slots_7.io.iss_uop.is_fencei \n connect issue_slots[7].iss_uop.is_fence, slots_7.io.iss_uop.is_fence \n connect issue_slots[7].iss_uop.is_sfb, slots_7.io.iss_uop.is_sfb \n connect issue_slots[7].iss_uop.br_type, slots_7.io.iss_uop.br_type \n connect issue_slots[7].iss_uop.br_tag, slots_7.io.iss_uop.br_tag \n connect issue_slots[7].iss_uop.br_mask, slots_7.io.iss_uop.br_mask \n connect issue_slots[7].iss_uop.dis_col_sel, slots_7.io.iss_uop.dis_col_sel \n connect issue_slots[7].iss_uop.iw_p3_bypass_hint, slots_7.io.iss_uop.iw_p3_bypass_hint \n connect issue_slots[7].iss_uop.iw_p2_bypass_hint, slots_7.io.iss_uop.iw_p2_bypass_hint \n connect issue_slots[7].iss_uop.iw_p1_bypass_hint, slots_7.io.iss_uop.iw_p1_bypass_hint \n connect issue_slots[7].iss_uop.iw_p2_speculative_child, slots_7.io.iss_uop.iw_p2_speculative_child \n connect issue_slots[7].iss_uop.iw_p1_speculative_child, slots_7.io.iss_uop.iw_p1_speculative_child \n connect issue_slots[7].iss_uop.iw_issued_partial_dgen, slots_7.io.iss_uop.iw_issued_partial_dgen \n connect issue_slots[7].iss_uop.iw_issued_partial_agen, slots_7.io.iss_uop.iw_issued_partial_agen \n connect issue_slots[7].iss_uop.iw_issued, slots_7.io.iss_uop.iw_issued \n connect issue_slots[7].iss_uop.fu_code[0], slots_7.io.iss_uop.fu_code[0] \n connect issue_slots[7].iss_uop.fu_code[1], slots_7.io.iss_uop.fu_code[1] \n connect issue_slots[7].iss_uop.fu_code[2], slots_7.io.iss_uop.fu_code[2] \n connect issue_slots[7].iss_uop.fu_code[3], slots_7.io.iss_uop.fu_code[3] \n connect issue_slots[7].iss_uop.fu_code[4], slots_7.io.iss_uop.fu_code[4] \n connect issue_slots[7].iss_uop.fu_code[5], slots_7.io.iss_uop.fu_code[5] \n connect issue_slots[7].iss_uop.fu_code[6], slots_7.io.iss_uop.fu_code[6] \n connect issue_slots[7].iss_uop.fu_code[7], slots_7.io.iss_uop.fu_code[7] \n connect issue_slots[7].iss_uop.fu_code[8], slots_7.io.iss_uop.fu_code[8] \n connect issue_slots[7].iss_uop.fu_code[9], slots_7.io.iss_uop.fu_code[9] \n connect issue_slots[7].iss_uop.iq_type[0], slots_7.io.iss_uop.iq_type[0] \n connect issue_slots[7].iss_uop.iq_type[1], slots_7.io.iss_uop.iq_type[1] \n connect issue_slots[7].iss_uop.iq_type[2], slots_7.io.iss_uop.iq_type[2] \n connect issue_slots[7].iss_uop.iq_type[3], slots_7.io.iss_uop.iq_type[3] \n connect issue_slots[7].iss_uop.debug_pc, slots_7.io.iss_uop.debug_pc \n connect issue_slots[7].iss_uop.is_rvc, slots_7.io.iss_uop.is_rvc \n connect issue_slots[7].iss_uop.debug_inst, slots_7.io.iss_uop.debug_inst \n connect issue_slots[7].iss_uop.inst, slots_7.io.iss_uop.inst \n connect slots_7.io.grant, issue_slots[7].grant \n connect issue_slots[7].request, slots_7.io.request \n connect issue_slots[7].will_be_valid, slots_7.io.will_be_valid \n connect issue_slots[7].valid, slots_7.io.valid \n connect slots_8.io.child_rebusys, issue_slots[8].child_rebusys \n connect slots_8.io.pred_wakeup_port.bits, issue_slots[8].pred_wakeup_port.bits \n connect slots_8.io.pred_wakeup_port.valid, issue_slots[8].pred_wakeup_port.valid \n connect slots_8.io.wakeup_ports[0].bits.rebusy, issue_slots[8].wakeup_ports[0].bits.rebusy \n connect slots_8.io.wakeup_ports[0].bits.speculative_mask, issue_slots[8].wakeup_ports[0].bits.speculative_mask \n connect slots_8.io.wakeup_ports[0].bits.bypassable, issue_slots[8].wakeup_ports[0].bits.bypassable \n connect slots_8.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[8].wakeup_ports[0].bits.uop.debug_tsrc \n connect slots_8.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[8].wakeup_ports[0].bits.uop.debug_fsrc \n connect slots_8.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[8].wakeup_ports[0].bits.uop.bp_xcpt_if \n connect slots_8.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[8].wakeup_ports[0].bits.uop.bp_debug_if \n connect slots_8.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[8].wakeup_ports[0].bits.uop.xcpt_ma_if \n connect slots_8.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[8].wakeup_ports[0].bits.uop.xcpt_ae_if \n connect slots_8.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[8].wakeup_ports[0].bits.uop.xcpt_pf_if \n connect slots_8.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[8].wakeup_ports[0].bits.uop.fp_typ \n connect slots_8.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[8].wakeup_ports[0].bits.uop.fp_rm \n connect slots_8.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[8].wakeup_ports[0].bits.uop.fp_val \n connect slots_8.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[8].wakeup_ports[0].bits.uop.fcn_op \n connect slots_8.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[8].wakeup_ports[0].bits.uop.fcn_dw \n connect slots_8.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[8].wakeup_ports[0].bits.uop.frs3_en \n connect slots_8.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[8].wakeup_ports[0].bits.uop.lrs2_rtype \n connect slots_8.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[8].wakeup_ports[0].bits.uop.lrs1_rtype \n connect slots_8.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[8].wakeup_ports[0].bits.uop.dst_rtype \n connect slots_8.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[8].wakeup_ports[0].bits.uop.lrs3 \n connect slots_8.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[8].wakeup_ports[0].bits.uop.lrs2 \n connect slots_8.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[8].wakeup_ports[0].bits.uop.lrs1 \n connect slots_8.io.wakeup_ports[0].bits.uop.ldst, issue_slots[8].wakeup_ports[0].bits.uop.ldst \n connect slots_8.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[8].wakeup_ports[0].bits.uop.ldst_is_rs1 \n connect slots_8.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[8].wakeup_ports[0].bits.uop.csr_cmd \n connect slots_8.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[8].wakeup_ports[0].bits.uop.flush_on_commit \n connect slots_8.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[8].wakeup_ports[0].bits.uop.is_unique \n connect slots_8.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[8].wakeup_ports[0].bits.uop.uses_stq \n connect slots_8.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[8].wakeup_ports[0].bits.uop.uses_ldq \n connect slots_8.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[8].wakeup_ports[0].bits.uop.mem_signed \n connect slots_8.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[8].wakeup_ports[0].bits.uop.mem_size \n connect slots_8.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[8].wakeup_ports[0].bits.uop.mem_cmd \n connect slots_8.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[8].wakeup_ports[0].bits.uop.exc_cause \n connect slots_8.io.wakeup_ports[0].bits.uop.exception, issue_slots[8].wakeup_ports[0].bits.uop.exception \n connect slots_8.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[8].wakeup_ports[0].bits.uop.stale_pdst \n connect slots_8.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[8].wakeup_ports[0].bits.uop.ppred_busy \n connect slots_8.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[8].wakeup_ports[0].bits.uop.prs3_busy \n connect slots_8.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[8].wakeup_ports[0].bits.uop.prs2_busy \n connect slots_8.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[8].wakeup_ports[0].bits.uop.prs1_busy \n connect slots_8.io.wakeup_ports[0].bits.uop.ppred, issue_slots[8].wakeup_ports[0].bits.uop.ppred \n connect slots_8.io.wakeup_ports[0].bits.uop.prs3, issue_slots[8].wakeup_ports[0].bits.uop.prs3 \n connect slots_8.io.wakeup_ports[0].bits.uop.prs2, issue_slots[8].wakeup_ports[0].bits.uop.prs2 \n connect slots_8.io.wakeup_ports[0].bits.uop.prs1, issue_slots[8].wakeup_ports[0].bits.uop.prs1 \n connect slots_8.io.wakeup_ports[0].bits.uop.pdst, issue_slots[8].wakeup_ports[0].bits.uop.pdst \n connect slots_8.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[8].wakeup_ports[0].bits.uop.rxq_idx \n connect slots_8.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[8].wakeup_ports[0].bits.uop.stq_idx \n connect slots_8.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[8].wakeup_ports[0].bits.uop.ldq_idx \n connect slots_8.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[8].wakeup_ports[0].bits.uop.rob_idx \n connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.vec \n connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.wflags \n connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.sqrt \n connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.div \n connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.fma \n connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe \n connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.toint \n connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.fromint \n connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut \n connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn \n connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.swap23 \n connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.swap12 \n connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.ren3 \n connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.ren2 \n connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.ren1 \n connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.wen \n connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.ldst \n connect slots_8.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[8].wakeup_ports[0].bits.uop.op2_sel \n connect slots_8.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[8].wakeup_ports[0].bits.uop.op1_sel \n connect slots_8.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[8].wakeup_ports[0].bits.uop.imm_packed \n connect slots_8.io.wakeup_ports[0].bits.uop.pimm, issue_slots[8].wakeup_ports[0].bits.uop.pimm \n connect slots_8.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[8].wakeup_ports[0].bits.uop.imm_sel \n connect slots_8.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[8].wakeup_ports[0].bits.uop.imm_rename \n connect slots_8.io.wakeup_ports[0].bits.uop.taken, issue_slots[8].wakeup_ports[0].bits.uop.taken \n connect slots_8.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[8].wakeup_ports[0].bits.uop.pc_lob \n connect slots_8.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[8].wakeup_ports[0].bits.uop.edge_inst \n connect slots_8.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[8].wakeup_ports[0].bits.uop.ftq_idx \n connect slots_8.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[8].wakeup_ports[0].bits.uop.is_mov \n connect slots_8.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[8].wakeup_ports[0].bits.uop.is_rocc \n connect slots_8.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[8].wakeup_ports[0].bits.uop.is_sys_pc2epc \n connect slots_8.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[8].wakeup_ports[0].bits.uop.is_eret \n connect slots_8.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[8].wakeup_ports[0].bits.uop.is_amo \n connect slots_8.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[8].wakeup_ports[0].bits.uop.is_sfence \n connect slots_8.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[8].wakeup_ports[0].bits.uop.is_fencei \n connect slots_8.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[8].wakeup_ports[0].bits.uop.is_fence \n connect slots_8.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[8].wakeup_ports[0].bits.uop.is_sfb \n connect slots_8.io.wakeup_ports[0].bits.uop.br_type, issue_slots[8].wakeup_ports[0].bits.uop.br_type \n connect slots_8.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[8].wakeup_ports[0].bits.uop.br_tag \n connect slots_8.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[8].wakeup_ports[0].bits.uop.br_mask \n connect slots_8.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[8].wakeup_ports[0].bits.uop.dis_col_sel \n connect slots_8.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[8].wakeup_ports[0].bits.uop.iw_p3_bypass_hint \n connect slots_8.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[8].wakeup_ports[0].bits.uop.iw_p2_bypass_hint \n connect slots_8.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[8].wakeup_ports[0].bits.uop.iw_p1_bypass_hint \n connect slots_8.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[8].wakeup_ports[0].bits.uop.iw_p2_speculative_child \n connect slots_8.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[8].wakeup_ports[0].bits.uop.iw_p1_speculative_child \n connect slots_8.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[8].wakeup_ports[0].bits.uop.iw_issued_partial_dgen \n connect slots_8.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[8].wakeup_ports[0].bits.uop.iw_issued_partial_agen \n connect slots_8.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[8].wakeup_ports[0].bits.uop.iw_issued \n connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[0] \n connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[1] \n connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[2] \n connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[3] \n connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[4] \n connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[5] \n connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[6] \n connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[7] \n connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[8] \n connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[9] \n connect slots_8.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[8].wakeup_ports[0].bits.uop.iq_type[0] \n connect slots_8.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[8].wakeup_ports[0].bits.uop.iq_type[1] \n connect slots_8.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[8].wakeup_ports[0].bits.uop.iq_type[2] \n connect slots_8.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[8].wakeup_ports[0].bits.uop.iq_type[3] \n connect slots_8.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[8].wakeup_ports[0].bits.uop.debug_pc \n connect slots_8.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[8].wakeup_ports[0].bits.uop.is_rvc \n connect slots_8.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[8].wakeup_ports[0].bits.uop.debug_inst \n connect slots_8.io.wakeup_ports[0].bits.uop.inst, issue_slots[8].wakeup_ports[0].bits.uop.inst \n connect slots_8.io.wakeup_ports[0].valid, issue_slots[8].wakeup_ports[0].valid \n connect slots_8.io.wakeup_ports[1].bits.rebusy, issue_slots[8].wakeup_ports[1].bits.rebusy \n connect slots_8.io.wakeup_ports[1].bits.speculative_mask, issue_slots[8].wakeup_ports[1].bits.speculative_mask \n connect slots_8.io.wakeup_ports[1].bits.bypassable, issue_slots[8].wakeup_ports[1].bits.bypassable \n connect slots_8.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[8].wakeup_ports[1].bits.uop.debug_tsrc \n connect slots_8.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[8].wakeup_ports[1].bits.uop.debug_fsrc \n connect slots_8.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[8].wakeup_ports[1].bits.uop.bp_xcpt_if \n connect slots_8.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[8].wakeup_ports[1].bits.uop.bp_debug_if \n connect slots_8.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[8].wakeup_ports[1].bits.uop.xcpt_ma_if \n connect slots_8.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[8].wakeup_ports[1].bits.uop.xcpt_ae_if \n connect slots_8.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[8].wakeup_ports[1].bits.uop.xcpt_pf_if \n connect slots_8.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[8].wakeup_ports[1].bits.uop.fp_typ \n connect slots_8.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[8].wakeup_ports[1].bits.uop.fp_rm \n connect slots_8.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[8].wakeup_ports[1].bits.uop.fp_val \n connect slots_8.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[8].wakeup_ports[1].bits.uop.fcn_op \n connect slots_8.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[8].wakeup_ports[1].bits.uop.fcn_dw \n connect slots_8.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[8].wakeup_ports[1].bits.uop.frs3_en \n connect slots_8.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[8].wakeup_ports[1].bits.uop.lrs2_rtype \n connect slots_8.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[8].wakeup_ports[1].bits.uop.lrs1_rtype \n connect slots_8.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[8].wakeup_ports[1].bits.uop.dst_rtype \n connect slots_8.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[8].wakeup_ports[1].bits.uop.lrs3 \n connect slots_8.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[8].wakeup_ports[1].bits.uop.lrs2 \n connect slots_8.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[8].wakeup_ports[1].bits.uop.lrs1 \n connect slots_8.io.wakeup_ports[1].bits.uop.ldst, issue_slots[8].wakeup_ports[1].bits.uop.ldst \n connect slots_8.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[8].wakeup_ports[1].bits.uop.ldst_is_rs1 \n connect slots_8.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[8].wakeup_ports[1].bits.uop.csr_cmd \n connect slots_8.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[8].wakeup_ports[1].bits.uop.flush_on_commit \n connect slots_8.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[8].wakeup_ports[1].bits.uop.is_unique \n connect slots_8.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[8].wakeup_ports[1].bits.uop.uses_stq \n connect slots_8.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[8].wakeup_ports[1].bits.uop.uses_ldq \n connect slots_8.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[8].wakeup_ports[1].bits.uop.mem_signed \n connect slots_8.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[8].wakeup_ports[1].bits.uop.mem_size \n connect slots_8.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[8].wakeup_ports[1].bits.uop.mem_cmd \n connect slots_8.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[8].wakeup_ports[1].bits.uop.exc_cause \n connect slots_8.io.wakeup_ports[1].bits.uop.exception, issue_slots[8].wakeup_ports[1].bits.uop.exception \n connect slots_8.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[8].wakeup_ports[1].bits.uop.stale_pdst \n connect slots_8.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[8].wakeup_ports[1].bits.uop.ppred_busy \n connect slots_8.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[8].wakeup_ports[1].bits.uop.prs3_busy \n connect slots_8.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[8].wakeup_ports[1].bits.uop.prs2_busy \n connect slots_8.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[8].wakeup_ports[1].bits.uop.prs1_busy \n connect slots_8.io.wakeup_ports[1].bits.uop.ppred, issue_slots[8].wakeup_ports[1].bits.uop.ppred \n connect slots_8.io.wakeup_ports[1].bits.uop.prs3, issue_slots[8].wakeup_ports[1].bits.uop.prs3 \n connect slots_8.io.wakeup_ports[1].bits.uop.prs2, issue_slots[8].wakeup_ports[1].bits.uop.prs2 \n connect slots_8.io.wakeup_ports[1].bits.uop.prs1, issue_slots[8].wakeup_ports[1].bits.uop.prs1 \n connect slots_8.io.wakeup_ports[1].bits.uop.pdst, issue_slots[8].wakeup_ports[1].bits.uop.pdst \n connect slots_8.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[8].wakeup_ports[1].bits.uop.rxq_idx \n connect slots_8.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[8].wakeup_ports[1].bits.uop.stq_idx \n connect slots_8.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[8].wakeup_ports[1].bits.uop.ldq_idx \n connect slots_8.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[8].wakeup_ports[1].bits.uop.rob_idx \n connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.vec \n connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.wflags \n connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.sqrt \n connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.div \n connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.fma \n connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe \n connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.toint \n connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.fromint \n connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut \n connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn \n connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.swap23 \n connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.swap12 \n connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.ren3 \n connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.ren2 \n connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.ren1 \n connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.wen \n connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.ldst \n connect slots_8.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[8].wakeup_ports[1].bits.uop.op2_sel \n connect slots_8.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[8].wakeup_ports[1].bits.uop.op1_sel \n connect slots_8.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[8].wakeup_ports[1].bits.uop.imm_packed \n connect slots_8.io.wakeup_ports[1].bits.uop.pimm, issue_slots[8].wakeup_ports[1].bits.uop.pimm \n connect slots_8.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[8].wakeup_ports[1].bits.uop.imm_sel \n connect slots_8.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[8].wakeup_ports[1].bits.uop.imm_rename \n connect slots_8.io.wakeup_ports[1].bits.uop.taken, issue_slots[8].wakeup_ports[1].bits.uop.taken \n connect slots_8.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[8].wakeup_ports[1].bits.uop.pc_lob \n connect slots_8.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[8].wakeup_ports[1].bits.uop.edge_inst \n connect slots_8.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[8].wakeup_ports[1].bits.uop.ftq_idx \n connect slots_8.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[8].wakeup_ports[1].bits.uop.is_mov \n connect slots_8.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[8].wakeup_ports[1].bits.uop.is_rocc \n connect slots_8.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[8].wakeup_ports[1].bits.uop.is_sys_pc2epc \n connect slots_8.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[8].wakeup_ports[1].bits.uop.is_eret \n connect slots_8.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[8].wakeup_ports[1].bits.uop.is_amo \n connect slots_8.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[8].wakeup_ports[1].bits.uop.is_sfence \n connect slots_8.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[8].wakeup_ports[1].bits.uop.is_fencei \n connect slots_8.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[8].wakeup_ports[1].bits.uop.is_fence \n connect slots_8.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[8].wakeup_ports[1].bits.uop.is_sfb \n connect slots_8.io.wakeup_ports[1].bits.uop.br_type, issue_slots[8].wakeup_ports[1].bits.uop.br_type \n connect slots_8.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[8].wakeup_ports[1].bits.uop.br_tag \n connect slots_8.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[8].wakeup_ports[1].bits.uop.br_mask \n connect slots_8.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[8].wakeup_ports[1].bits.uop.dis_col_sel \n connect slots_8.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[8].wakeup_ports[1].bits.uop.iw_p3_bypass_hint \n connect slots_8.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[8].wakeup_ports[1].bits.uop.iw_p2_bypass_hint \n connect slots_8.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[8].wakeup_ports[1].bits.uop.iw_p1_bypass_hint \n connect slots_8.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[8].wakeup_ports[1].bits.uop.iw_p2_speculative_child \n connect slots_8.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[8].wakeup_ports[1].bits.uop.iw_p1_speculative_child \n connect slots_8.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[8].wakeup_ports[1].bits.uop.iw_issued_partial_dgen \n connect slots_8.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[8].wakeup_ports[1].bits.uop.iw_issued_partial_agen \n connect slots_8.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[8].wakeup_ports[1].bits.uop.iw_issued \n connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[0] \n connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[1] \n connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[2] \n connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[3] \n connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[4] \n connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[5] \n connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[6] \n connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[7] \n connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[8] \n connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[9] \n connect slots_8.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[8].wakeup_ports[1].bits.uop.iq_type[0] \n connect slots_8.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[8].wakeup_ports[1].bits.uop.iq_type[1] \n connect slots_8.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[8].wakeup_ports[1].bits.uop.iq_type[2] \n connect slots_8.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[8].wakeup_ports[1].bits.uop.iq_type[3] \n connect slots_8.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[8].wakeup_ports[1].bits.uop.debug_pc \n connect slots_8.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[8].wakeup_ports[1].bits.uop.is_rvc \n connect slots_8.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[8].wakeup_ports[1].bits.uop.debug_inst \n connect slots_8.io.wakeup_ports[1].bits.uop.inst, issue_slots[8].wakeup_ports[1].bits.uop.inst \n connect slots_8.io.wakeup_ports[1].valid, issue_slots[8].wakeup_ports[1].valid \n connect slots_8.io.wakeup_ports[2].bits.rebusy, issue_slots[8].wakeup_ports[2].bits.rebusy \n connect slots_8.io.wakeup_ports[2].bits.speculative_mask, issue_slots[8].wakeup_ports[2].bits.speculative_mask \n connect slots_8.io.wakeup_ports[2].bits.bypassable, issue_slots[8].wakeup_ports[2].bits.bypassable \n connect slots_8.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[8].wakeup_ports[2].bits.uop.debug_tsrc \n connect slots_8.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[8].wakeup_ports[2].bits.uop.debug_fsrc \n connect slots_8.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[8].wakeup_ports[2].bits.uop.bp_xcpt_if \n connect slots_8.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[8].wakeup_ports[2].bits.uop.bp_debug_if \n connect slots_8.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[8].wakeup_ports[2].bits.uop.xcpt_ma_if \n connect slots_8.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[8].wakeup_ports[2].bits.uop.xcpt_ae_if \n connect slots_8.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[8].wakeup_ports[2].bits.uop.xcpt_pf_if \n connect slots_8.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[8].wakeup_ports[2].bits.uop.fp_typ \n connect slots_8.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[8].wakeup_ports[2].bits.uop.fp_rm \n connect slots_8.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[8].wakeup_ports[2].bits.uop.fp_val \n connect slots_8.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[8].wakeup_ports[2].bits.uop.fcn_op \n connect slots_8.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[8].wakeup_ports[2].bits.uop.fcn_dw \n connect slots_8.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[8].wakeup_ports[2].bits.uop.frs3_en \n connect slots_8.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[8].wakeup_ports[2].bits.uop.lrs2_rtype \n connect slots_8.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[8].wakeup_ports[2].bits.uop.lrs1_rtype \n connect slots_8.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[8].wakeup_ports[2].bits.uop.dst_rtype \n connect slots_8.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[8].wakeup_ports[2].bits.uop.lrs3 \n connect slots_8.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[8].wakeup_ports[2].bits.uop.lrs2 \n connect slots_8.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[8].wakeup_ports[2].bits.uop.lrs1 \n connect slots_8.io.wakeup_ports[2].bits.uop.ldst, issue_slots[8].wakeup_ports[2].bits.uop.ldst \n connect slots_8.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[8].wakeup_ports[2].bits.uop.ldst_is_rs1 \n connect slots_8.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[8].wakeup_ports[2].bits.uop.csr_cmd \n connect slots_8.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[8].wakeup_ports[2].bits.uop.flush_on_commit \n connect slots_8.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[8].wakeup_ports[2].bits.uop.is_unique \n connect slots_8.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[8].wakeup_ports[2].bits.uop.uses_stq \n connect slots_8.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[8].wakeup_ports[2].bits.uop.uses_ldq \n connect slots_8.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[8].wakeup_ports[2].bits.uop.mem_signed \n connect slots_8.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[8].wakeup_ports[2].bits.uop.mem_size \n connect slots_8.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[8].wakeup_ports[2].bits.uop.mem_cmd \n connect slots_8.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[8].wakeup_ports[2].bits.uop.exc_cause \n connect slots_8.io.wakeup_ports[2].bits.uop.exception, issue_slots[8].wakeup_ports[2].bits.uop.exception \n connect slots_8.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[8].wakeup_ports[2].bits.uop.stale_pdst \n connect slots_8.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[8].wakeup_ports[2].bits.uop.ppred_busy \n connect slots_8.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[8].wakeup_ports[2].bits.uop.prs3_busy \n connect slots_8.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[8].wakeup_ports[2].bits.uop.prs2_busy \n connect slots_8.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[8].wakeup_ports[2].bits.uop.prs1_busy \n connect slots_8.io.wakeup_ports[2].bits.uop.ppred, issue_slots[8].wakeup_ports[2].bits.uop.ppred \n connect slots_8.io.wakeup_ports[2].bits.uop.prs3, issue_slots[8].wakeup_ports[2].bits.uop.prs3 \n connect slots_8.io.wakeup_ports[2].bits.uop.prs2, issue_slots[8].wakeup_ports[2].bits.uop.prs2 \n connect slots_8.io.wakeup_ports[2].bits.uop.prs1, issue_slots[8].wakeup_ports[2].bits.uop.prs1 \n connect slots_8.io.wakeup_ports[2].bits.uop.pdst, issue_slots[8].wakeup_ports[2].bits.uop.pdst \n connect slots_8.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[8].wakeup_ports[2].bits.uop.rxq_idx \n connect slots_8.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[8].wakeup_ports[2].bits.uop.stq_idx \n connect slots_8.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[8].wakeup_ports[2].bits.uop.ldq_idx \n connect slots_8.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[8].wakeup_ports[2].bits.uop.rob_idx \n connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.vec \n connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.wflags \n connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.sqrt \n connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.div \n connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.fma \n connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe \n connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.toint \n connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.fromint \n connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut \n connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn \n connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.swap23 \n connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.swap12 \n connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.ren3 \n connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.ren2 \n connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.ren1 \n connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.wen \n connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.ldst \n connect slots_8.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[8].wakeup_ports[2].bits.uop.op2_sel \n connect slots_8.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[8].wakeup_ports[2].bits.uop.op1_sel \n connect slots_8.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[8].wakeup_ports[2].bits.uop.imm_packed \n connect slots_8.io.wakeup_ports[2].bits.uop.pimm, issue_slots[8].wakeup_ports[2].bits.uop.pimm \n connect slots_8.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[8].wakeup_ports[2].bits.uop.imm_sel \n connect slots_8.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[8].wakeup_ports[2].bits.uop.imm_rename \n connect slots_8.io.wakeup_ports[2].bits.uop.taken, issue_slots[8].wakeup_ports[2].bits.uop.taken \n connect slots_8.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[8].wakeup_ports[2].bits.uop.pc_lob \n connect slots_8.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[8].wakeup_ports[2].bits.uop.edge_inst \n connect slots_8.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[8].wakeup_ports[2].bits.uop.ftq_idx \n connect slots_8.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[8].wakeup_ports[2].bits.uop.is_mov \n connect slots_8.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[8].wakeup_ports[2].bits.uop.is_rocc \n connect slots_8.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[8].wakeup_ports[2].bits.uop.is_sys_pc2epc \n connect slots_8.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[8].wakeup_ports[2].bits.uop.is_eret \n connect slots_8.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[8].wakeup_ports[2].bits.uop.is_amo \n connect slots_8.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[8].wakeup_ports[2].bits.uop.is_sfence \n connect slots_8.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[8].wakeup_ports[2].bits.uop.is_fencei \n connect slots_8.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[8].wakeup_ports[2].bits.uop.is_fence \n connect slots_8.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[8].wakeup_ports[2].bits.uop.is_sfb \n connect slots_8.io.wakeup_ports[2].bits.uop.br_type, issue_slots[8].wakeup_ports[2].bits.uop.br_type \n connect slots_8.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[8].wakeup_ports[2].bits.uop.br_tag \n connect slots_8.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[8].wakeup_ports[2].bits.uop.br_mask \n connect slots_8.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[8].wakeup_ports[2].bits.uop.dis_col_sel \n connect slots_8.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[8].wakeup_ports[2].bits.uop.iw_p3_bypass_hint \n connect slots_8.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[8].wakeup_ports[2].bits.uop.iw_p2_bypass_hint \n connect slots_8.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[8].wakeup_ports[2].bits.uop.iw_p1_bypass_hint \n connect slots_8.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[8].wakeup_ports[2].bits.uop.iw_p2_speculative_child \n connect slots_8.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[8].wakeup_ports[2].bits.uop.iw_p1_speculative_child \n connect slots_8.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[8].wakeup_ports[2].bits.uop.iw_issued_partial_dgen \n connect slots_8.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[8].wakeup_ports[2].bits.uop.iw_issued_partial_agen \n connect slots_8.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[8].wakeup_ports[2].bits.uop.iw_issued \n connect slots_8.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[8].wakeup_ports[2].bits.uop.fu_code[0] \n connect slots_8.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[8].wakeup_ports[2].bits.uop.fu_code[1] \n connect slots_8.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[8].wakeup_ports[2].bits.uop.fu_code[2] \n connect slots_8.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[8].wakeup_ports[2].bits.uop.fu_code[3] \n connect slots_8.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[8].wakeup_ports[2].bits.uop.fu_code[4] \n connect slots_8.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[8].wakeup_ports[2].bits.uop.fu_code[5] \n connect slots_8.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[8].wakeup_ports[2].bits.uop.fu_code[6] \n connect slots_8.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[8].wakeup_ports[2].bits.uop.fu_code[7] \n connect slots_8.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[8].wakeup_ports[2].bits.uop.fu_code[8] \n connect slots_8.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[8].wakeup_ports[2].bits.uop.fu_code[9] \n connect slots_8.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[8].wakeup_ports[2].bits.uop.iq_type[0] \n connect slots_8.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[8].wakeup_ports[2].bits.uop.iq_type[1] \n connect slots_8.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[8].wakeup_ports[2].bits.uop.iq_type[2] \n connect slots_8.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[8].wakeup_ports[2].bits.uop.iq_type[3] \n connect slots_8.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[8].wakeup_ports[2].bits.uop.debug_pc \n connect slots_8.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[8].wakeup_ports[2].bits.uop.is_rvc \n connect slots_8.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[8].wakeup_ports[2].bits.uop.debug_inst \n connect slots_8.io.wakeup_ports[2].bits.uop.inst, issue_slots[8].wakeup_ports[2].bits.uop.inst \n connect slots_8.io.wakeup_ports[2].valid, issue_slots[8].wakeup_ports[2].valid \n connect slots_8.io.wakeup_ports[3].bits.rebusy, issue_slots[8].wakeup_ports[3].bits.rebusy \n connect slots_8.io.wakeup_ports[3].bits.speculative_mask, issue_slots[8].wakeup_ports[3].bits.speculative_mask \n connect slots_8.io.wakeup_ports[3].bits.bypassable, issue_slots[8].wakeup_ports[3].bits.bypassable \n connect slots_8.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[8].wakeup_ports[3].bits.uop.debug_tsrc \n connect slots_8.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[8].wakeup_ports[3].bits.uop.debug_fsrc \n connect slots_8.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[8].wakeup_ports[3].bits.uop.bp_xcpt_if \n connect slots_8.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[8].wakeup_ports[3].bits.uop.bp_debug_if \n connect slots_8.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[8].wakeup_ports[3].bits.uop.xcpt_ma_if \n connect slots_8.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[8].wakeup_ports[3].bits.uop.xcpt_ae_if \n connect slots_8.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[8].wakeup_ports[3].bits.uop.xcpt_pf_if \n connect slots_8.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[8].wakeup_ports[3].bits.uop.fp_typ \n connect slots_8.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[8].wakeup_ports[3].bits.uop.fp_rm \n connect slots_8.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[8].wakeup_ports[3].bits.uop.fp_val \n connect slots_8.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[8].wakeup_ports[3].bits.uop.fcn_op \n connect slots_8.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[8].wakeup_ports[3].bits.uop.fcn_dw \n connect slots_8.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[8].wakeup_ports[3].bits.uop.frs3_en \n connect slots_8.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[8].wakeup_ports[3].bits.uop.lrs2_rtype \n connect slots_8.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[8].wakeup_ports[3].bits.uop.lrs1_rtype \n connect slots_8.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[8].wakeup_ports[3].bits.uop.dst_rtype \n connect slots_8.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[8].wakeup_ports[3].bits.uop.lrs3 \n connect slots_8.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[8].wakeup_ports[3].bits.uop.lrs2 \n connect slots_8.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[8].wakeup_ports[3].bits.uop.lrs1 \n connect slots_8.io.wakeup_ports[3].bits.uop.ldst, issue_slots[8].wakeup_ports[3].bits.uop.ldst \n connect slots_8.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[8].wakeup_ports[3].bits.uop.ldst_is_rs1 \n connect slots_8.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[8].wakeup_ports[3].bits.uop.csr_cmd \n connect slots_8.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[8].wakeup_ports[3].bits.uop.flush_on_commit \n connect slots_8.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[8].wakeup_ports[3].bits.uop.is_unique \n connect slots_8.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[8].wakeup_ports[3].bits.uop.uses_stq \n connect slots_8.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[8].wakeup_ports[3].bits.uop.uses_ldq \n connect slots_8.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[8].wakeup_ports[3].bits.uop.mem_signed \n connect slots_8.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[8].wakeup_ports[3].bits.uop.mem_size \n connect slots_8.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[8].wakeup_ports[3].bits.uop.mem_cmd \n connect slots_8.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[8].wakeup_ports[3].bits.uop.exc_cause \n connect slots_8.io.wakeup_ports[3].bits.uop.exception, issue_slots[8].wakeup_ports[3].bits.uop.exception \n connect slots_8.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[8].wakeup_ports[3].bits.uop.stale_pdst \n connect slots_8.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[8].wakeup_ports[3].bits.uop.ppred_busy \n connect slots_8.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[8].wakeup_ports[3].bits.uop.prs3_busy \n connect slots_8.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[8].wakeup_ports[3].bits.uop.prs2_busy \n connect slots_8.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[8].wakeup_ports[3].bits.uop.prs1_busy \n connect slots_8.io.wakeup_ports[3].bits.uop.ppred, issue_slots[8].wakeup_ports[3].bits.uop.ppred \n connect slots_8.io.wakeup_ports[3].bits.uop.prs3, issue_slots[8].wakeup_ports[3].bits.uop.prs3 \n connect slots_8.io.wakeup_ports[3].bits.uop.prs2, issue_slots[8].wakeup_ports[3].bits.uop.prs2 \n connect slots_8.io.wakeup_ports[3].bits.uop.prs1, issue_slots[8].wakeup_ports[3].bits.uop.prs1 \n connect slots_8.io.wakeup_ports[3].bits.uop.pdst, issue_slots[8].wakeup_ports[3].bits.uop.pdst \n connect slots_8.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[8].wakeup_ports[3].bits.uop.rxq_idx \n connect slots_8.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[8].wakeup_ports[3].bits.uop.stq_idx \n connect slots_8.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[8].wakeup_ports[3].bits.uop.ldq_idx \n connect slots_8.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[8].wakeup_ports[3].bits.uop.rob_idx \n connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.vec \n connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.wflags \n connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.sqrt \n connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.div \n connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.fma \n connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe \n connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.toint \n connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.fromint \n connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut \n connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn \n connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.swap23 \n connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.swap12 \n connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.ren3 \n connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.ren2 \n connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.ren1 \n connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.wen \n connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.ldst \n connect slots_8.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[8].wakeup_ports[3].bits.uop.op2_sel \n connect slots_8.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[8].wakeup_ports[3].bits.uop.op1_sel \n connect slots_8.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[8].wakeup_ports[3].bits.uop.imm_packed \n connect slots_8.io.wakeup_ports[3].bits.uop.pimm, issue_slots[8].wakeup_ports[3].bits.uop.pimm \n connect slots_8.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[8].wakeup_ports[3].bits.uop.imm_sel \n connect slots_8.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[8].wakeup_ports[3].bits.uop.imm_rename \n connect slots_8.io.wakeup_ports[3].bits.uop.taken, issue_slots[8].wakeup_ports[3].bits.uop.taken \n connect slots_8.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[8].wakeup_ports[3].bits.uop.pc_lob \n connect slots_8.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[8].wakeup_ports[3].bits.uop.edge_inst \n connect slots_8.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[8].wakeup_ports[3].bits.uop.ftq_idx \n connect slots_8.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[8].wakeup_ports[3].bits.uop.is_mov \n connect slots_8.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[8].wakeup_ports[3].bits.uop.is_rocc \n connect slots_8.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[8].wakeup_ports[3].bits.uop.is_sys_pc2epc \n connect slots_8.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[8].wakeup_ports[3].bits.uop.is_eret \n connect slots_8.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[8].wakeup_ports[3].bits.uop.is_amo \n connect slots_8.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[8].wakeup_ports[3].bits.uop.is_sfence \n connect slots_8.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[8].wakeup_ports[3].bits.uop.is_fencei \n connect slots_8.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[8].wakeup_ports[3].bits.uop.is_fence \n connect slots_8.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[8].wakeup_ports[3].bits.uop.is_sfb \n connect slots_8.io.wakeup_ports[3].bits.uop.br_type, issue_slots[8].wakeup_ports[3].bits.uop.br_type \n connect slots_8.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[8].wakeup_ports[3].bits.uop.br_tag \n connect slots_8.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[8].wakeup_ports[3].bits.uop.br_mask \n connect slots_8.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[8].wakeup_ports[3].bits.uop.dis_col_sel \n connect slots_8.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[8].wakeup_ports[3].bits.uop.iw_p3_bypass_hint \n connect slots_8.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[8].wakeup_ports[3].bits.uop.iw_p2_bypass_hint \n connect slots_8.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[8].wakeup_ports[3].bits.uop.iw_p1_bypass_hint \n connect slots_8.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[8].wakeup_ports[3].bits.uop.iw_p2_speculative_child \n connect slots_8.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[8].wakeup_ports[3].bits.uop.iw_p1_speculative_child \n connect slots_8.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[8].wakeup_ports[3].bits.uop.iw_issued_partial_dgen \n connect slots_8.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[8].wakeup_ports[3].bits.uop.iw_issued_partial_agen \n connect slots_8.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[8].wakeup_ports[3].bits.uop.iw_issued \n connect slots_8.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[8].wakeup_ports[3].bits.uop.fu_code[0] \n connect slots_8.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[8].wakeup_ports[3].bits.uop.fu_code[1] \n connect slots_8.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[8].wakeup_ports[3].bits.uop.fu_code[2] \n connect slots_8.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[8].wakeup_ports[3].bits.uop.fu_code[3] \n connect slots_8.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[8].wakeup_ports[3].bits.uop.fu_code[4] \n connect slots_8.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[8].wakeup_ports[3].bits.uop.fu_code[5] \n connect slots_8.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[8].wakeup_ports[3].bits.uop.fu_code[6] \n connect slots_8.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[8].wakeup_ports[3].bits.uop.fu_code[7] \n connect slots_8.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[8].wakeup_ports[3].bits.uop.fu_code[8] \n connect slots_8.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[8].wakeup_ports[3].bits.uop.fu_code[9] \n connect slots_8.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[8].wakeup_ports[3].bits.uop.iq_type[0] \n connect slots_8.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[8].wakeup_ports[3].bits.uop.iq_type[1] \n connect slots_8.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[8].wakeup_ports[3].bits.uop.iq_type[2] \n connect slots_8.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[8].wakeup_ports[3].bits.uop.iq_type[3] \n connect slots_8.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[8].wakeup_ports[3].bits.uop.debug_pc \n connect slots_8.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[8].wakeup_ports[3].bits.uop.is_rvc \n connect slots_8.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[8].wakeup_ports[3].bits.uop.debug_inst \n connect slots_8.io.wakeup_ports[3].bits.uop.inst, issue_slots[8].wakeup_ports[3].bits.uop.inst \n connect slots_8.io.wakeup_ports[3].valid, issue_slots[8].wakeup_ports[3].valid \n connect slots_8.io.squash_grant, issue_slots[8].squash_grant \n connect slots_8.io.clear, issue_slots[8].clear \n connect slots_8.io.kill, issue_slots[8].kill \n connect slots_8.io.brupdate.b2.target_offset, issue_slots[8].brupdate.b2.target_offset \n connect slots_8.io.brupdate.b2.jalr_target, issue_slots[8].brupdate.b2.jalr_target \n connect slots_8.io.brupdate.b2.pc_sel, issue_slots[8].brupdate.b2.pc_sel \n connect slots_8.io.brupdate.b2.cfi_type, issue_slots[8].brupdate.b2.cfi_type \n connect slots_8.io.brupdate.b2.taken, issue_slots[8].brupdate.b2.taken \n connect slots_8.io.brupdate.b2.mispredict, issue_slots[8].brupdate.b2.mispredict \n connect slots_8.io.brupdate.b2.uop.debug_tsrc, issue_slots[8].brupdate.b2.uop.debug_tsrc \n connect slots_8.io.brupdate.b2.uop.debug_fsrc, issue_slots[8].brupdate.b2.uop.debug_fsrc \n connect slots_8.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[8].brupdate.b2.uop.bp_xcpt_if \n connect slots_8.io.brupdate.b2.uop.bp_debug_if, issue_slots[8].brupdate.b2.uop.bp_debug_if \n connect slots_8.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[8].brupdate.b2.uop.xcpt_ma_if \n connect slots_8.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[8].brupdate.b2.uop.xcpt_ae_if \n connect slots_8.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[8].brupdate.b2.uop.xcpt_pf_if \n connect slots_8.io.brupdate.b2.uop.fp_typ, issue_slots[8].brupdate.b2.uop.fp_typ \n connect slots_8.io.brupdate.b2.uop.fp_rm, issue_slots[8].brupdate.b2.uop.fp_rm \n connect slots_8.io.brupdate.b2.uop.fp_val, issue_slots[8].brupdate.b2.uop.fp_val \n connect slots_8.io.brupdate.b2.uop.fcn_op, issue_slots[8].brupdate.b2.uop.fcn_op \n connect slots_8.io.brupdate.b2.uop.fcn_dw, issue_slots[8].brupdate.b2.uop.fcn_dw \n connect slots_8.io.brupdate.b2.uop.frs3_en, issue_slots[8].brupdate.b2.uop.frs3_en \n connect slots_8.io.brupdate.b2.uop.lrs2_rtype, issue_slots[8].brupdate.b2.uop.lrs2_rtype \n connect slots_8.io.brupdate.b2.uop.lrs1_rtype, issue_slots[8].brupdate.b2.uop.lrs1_rtype \n connect slots_8.io.brupdate.b2.uop.dst_rtype, issue_slots[8].brupdate.b2.uop.dst_rtype \n connect slots_8.io.brupdate.b2.uop.lrs3, issue_slots[8].brupdate.b2.uop.lrs3 \n connect slots_8.io.brupdate.b2.uop.lrs2, issue_slots[8].brupdate.b2.uop.lrs2 \n connect slots_8.io.brupdate.b2.uop.lrs1, issue_slots[8].brupdate.b2.uop.lrs1 \n connect slots_8.io.brupdate.b2.uop.ldst, issue_slots[8].brupdate.b2.uop.ldst \n connect slots_8.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[8].brupdate.b2.uop.ldst_is_rs1 \n connect slots_8.io.brupdate.b2.uop.csr_cmd, issue_slots[8].brupdate.b2.uop.csr_cmd \n connect slots_8.io.brupdate.b2.uop.flush_on_commit, issue_slots[8].brupdate.b2.uop.flush_on_commit \n connect slots_8.io.brupdate.b2.uop.is_unique, issue_slots[8].brupdate.b2.uop.is_unique \n connect slots_8.io.brupdate.b2.uop.uses_stq, issue_slots[8].brupdate.b2.uop.uses_stq \n connect slots_8.io.brupdate.b2.uop.uses_ldq, issue_slots[8].brupdate.b2.uop.uses_ldq \n connect slots_8.io.brupdate.b2.uop.mem_signed, issue_slots[8].brupdate.b2.uop.mem_signed \n connect slots_8.io.brupdate.b2.uop.mem_size, issue_slots[8].brupdate.b2.uop.mem_size \n connect slots_8.io.brupdate.b2.uop.mem_cmd, issue_slots[8].brupdate.b2.uop.mem_cmd \n connect slots_8.io.brupdate.b2.uop.exc_cause, issue_slots[8].brupdate.b2.uop.exc_cause \n connect slots_8.io.brupdate.b2.uop.exception, issue_slots[8].brupdate.b2.uop.exception \n connect slots_8.io.brupdate.b2.uop.stale_pdst, issue_slots[8].brupdate.b2.uop.stale_pdst \n connect slots_8.io.brupdate.b2.uop.ppred_busy, issue_slots[8].brupdate.b2.uop.ppred_busy \n connect slots_8.io.brupdate.b2.uop.prs3_busy, issue_slots[8].brupdate.b2.uop.prs3_busy \n connect slots_8.io.brupdate.b2.uop.prs2_busy, issue_slots[8].brupdate.b2.uop.prs2_busy \n connect slots_8.io.brupdate.b2.uop.prs1_busy, issue_slots[8].brupdate.b2.uop.prs1_busy \n connect slots_8.io.brupdate.b2.uop.ppred, issue_slots[8].brupdate.b2.uop.ppred \n connect slots_8.io.brupdate.b2.uop.prs3, issue_slots[8].brupdate.b2.uop.prs3 \n connect slots_8.io.brupdate.b2.uop.prs2, issue_slots[8].brupdate.b2.uop.prs2 \n connect slots_8.io.brupdate.b2.uop.prs1, issue_slots[8].brupdate.b2.uop.prs1 \n connect slots_8.io.brupdate.b2.uop.pdst, issue_slots[8].brupdate.b2.uop.pdst \n connect slots_8.io.brupdate.b2.uop.rxq_idx, issue_slots[8].brupdate.b2.uop.rxq_idx \n connect slots_8.io.brupdate.b2.uop.stq_idx, issue_slots[8].brupdate.b2.uop.stq_idx \n connect slots_8.io.brupdate.b2.uop.ldq_idx, issue_slots[8].brupdate.b2.uop.ldq_idx \n connect slots_8.io.brupdate.b2.uop.rob_idx, issue_slots[8].brupdate.b2.uop.rob_idx \n connect slots_8.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[8].brupdate.b2.uop.fp_ctrl.vec \n connect slots_8.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[8].brupdate.b2.uop.fp_ctrl.wflags \n connect slots_8.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[8].brupdate.b2.uop.fp_ctrl.sqrt \n connect slots_8.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[8].brupdate.b2.uop.fp_ctrl.div \n connect slots_8.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[8].brupdate.b2.uop.fp_ctrl.fma \n connect slots_8.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[8].brupdate.b2.uop.fp_ctrl.fastpipe \n connect slots_8.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[8].brupdate.b2.uop.fp_ctrl.toint \n connect slots_8.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[8].brupdate.b2.uop.fp_ctrl.fromint \n connect slots_8.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[8].brupdate.b2.uop.fp_ctrl.typeTagOut \n connect slots_8.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[8].brupdate.b2.uop.fp_ctrl.typeTagIn \n connect slots_8.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[8].brupdate.b2.uop.fp_ctrl.swap23 \n connect slots_8.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[8].brupdate.b2.uop.fp_ctrl.swap12 \n connect slots_8.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[8].brupdate.b2.uop.fp_ctrl.ren3 \n connect slots_8.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[8].brupdate.b2.uop.fp_ctrl.ren2 \n connect slots_8.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[8].brupdate.b2.uop.fp_ctrl.ren1 \n connect slots_8.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[8].brupdate.b2.uop.fp_ctrl.wen \n connect slots_8.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[8].brupdate.b2.uop.fp_ctrl.ldst \n connect slots_8.io.brupdate.b2.uop.op2_sel, issue_slots[8].brupdate.b2.uop.op2_sel \n connect slots_8.io.brupdate.b2.uop.op1_sel, issue_slots[8].brupdate.b2.uop.op1_sel \n connect slots_8.io.brupdate.b2.uop.imm_packed, issue_slots[8].brupdate.b2.uop.imm_packed \n connect slots_8.io.brupdate.b2.uop.pimm, issue_slots[8].brupdate.b2.uop.pimm \n connect slots_8.io.brupdate.b2.uop.imm_sel, issue_slots[8].brupdate.b2.uop.imm_sel \n connect slots_8.io.brupdate.b2.uop.imm_rename, issue_slots[8].brupdate.b2.uop.imm_rename \n connect slots_8.io.brupdate.b2.uop.taken, issue_slots[8].brupdate.b2.uop.taken \n connect slots_8.io.brupdate.b2.uop.pc_lob, issue_slots[8].brupdate.b2.uop.pc_lob \n connect slots_8.io.brupdate.b2.uop.edge_inst, issue_slots[8].brupdate.b2.uop.edge_inst \n connect slots_8.io.brupdate.b2.uop.ftq_idx, issue_slots[8].brupdate.b2.uop.ftq_idx \n connect slots_8.io.brupdate.b2.uop.is_mov, issue_slots[8].brupdate.b2.uop.is_mov \n connect slots_8.io.brupdate.b2.uop.is_rocc, issue_slots[8].brupdate.b2.uop.is_rocc \n connect slots_8.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[8].brupdate.b2.uop.is_sys_pc2epc \n connect slots_8.io.brupdate.b2.uop.is_eret, issue_slots[8].brupdate.b2.uop.is_eret \n connect slots_8.io.brupdate.b2.uop.is_amo, issue_slots[8].brupdate.b2.uop.is_amo \n connect slots_8.io.brupdate.b2.uop.is_sfence, issue_slots[8].brupdate.b2.uop.is_sfence \n connect slots_8.io.brupdate.b2.uop.is_fencei, issue_slots[8].brupdate.b2.uop.is_fencei \n connect slots_8.io.brupdate.b2.uop.is_fence, issue_slots[8].brupdate.b2.uop.is_fence \n connect slots_8.io.brupdate.b2.uop.is_sfb, issue_slots[8].brupdate.b2.uop.is_sfb \n connect slots_8.io.brupdate.b2.uop.br_type, issue_slots[8].brupdate.b2.uop.br_type \n connect slots_8.io.brupdate.b2.uop.br_tag, issue_slots[8].brupdate.b2.uop.br_tag \n connect slots_8.io.brupdate.b2.uop.br_mask, issue_slots[8].brupdate.b2.uop.br_mask \n connect slots_8.io.brupdate.b2.uop.dis_col_sel, issue_slots[8].brupdate.b2.uop.dis_col_sel \n connect slots_8.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[8].brupdate.b2.uop.iw_p3_bypass_hint \n connect slots_8.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[8].brupdate.b2.uop.iw_p2_bypass_hint \n connect slots_8.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[8].brupdate.b2.uop.iw_p1_bypass_hint \n connect slots_8.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[8].brupdate.b2.uop.iw_p2_speculative_child \n connect slots_8.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[8].brupdate.b2.uop.iw_p1_speculative_child \n connect slots_8.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[8].brupdate.b2.uop.iw_issued_partial_dgen \n connect slots_8.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[8].brupdate.b2.uop.iw_issued_partial_agen \n connect slots_8.io.brupdate.b2.uop.iw_issued, issue_slots[8].brupdate.b2.uop.iw_issued \n connect slots_8.io.brupdate.b2.uop.fu_code[0], issue_slots[8].brupdate.b2.uop.fu_code[0] \n connect slots_8.io.brupdate.b2.uop.fu_code[1], issue_slots[8].brupdate.b2.uop.fu_code[1] \n connect slots_8.io.brupdate.b2.uop.fu_code[2], issue_slots[8].brupdate.b2.uop.fu_code[2] \n connect slots_8.io.brupdate.b2.uop.fu_code[3], issue_slots[8].brupdate.b2.uop.fu_code[3] \n connect slots_8.io.brupdate.b2.uop.fu_code[4], issue_slots[8].brupdate.b2.uop.fu_code[4] \n connect slots_8.io.brupdate.b2.uop.fu_code[5], issue_slots[8].brupdate.b2.uop.fu_code[5] \n connect slots_8.io.brupdate.b2.uop.fu_code[6], issue_slots[8].brupdate.b2.uop.fu_code[6] \n connect slots_8.io.brupdate.b2.uop.fu_code[7], issue_slots[8].brupdate.b2.uop.fu_code[7] \n connect slots_8.io.brupdate.b2.uop.fu_code[8], issue_slots[8].brupdate.b2.uop.fu_code[8] \n connect slots_8.io.brupdate.b2.uop.fu_code[9], issue_slots[8].brupdate.b2.uop.fu_code[9] \n connect slots_8.io.brupdate.b2.uop.iq_type[0], issue_slots[8].brupdate.b2.uop.iq_type[0] \n connect slots_8.io.brupdate.b2.uop.iq_type[1], issue_slots[8].brupdate.b2.uop.iq_type[1] \n connect slots_8.io.brupdate.b2.uop.iq_type[2], issue_slots[8].brupdate.b2.uop.iq_type[2] \n connect slots_8.io.brupdate.b2.uop.iq_type[3], issue_slots[8].brupdate.b2.uop.iq_type[3] \n connect slots_8.io.brupdate.b2.uop.debug_pc, issue_slots[8].brupdate.b2.uop.debug_pc \n connect slots_8.io.brupdate.b2.uop.is_rvc, issue_slots[8].brupdate.b2.uop.is_rvc \n connect slots_8.io.brupdate.b2.uop.debug_inst, issue_slots[8].brupdate.b2.uop.debug_inst \n connect slots_8.io.brupdate.b2.uop.inst, issue_slots[8].brupdate.b2.uop.inst \n connect slots_8.io.brupdate.b1.mispredict_mask, issue_slots[8].brupdate.b1.mispredict_mask \n connect slots_8.io.brupdate.b1.resolve_mask, issue_slots[8].brupdate.b1.resolve_mask \n connect issue_slots[8].out_uop.debug_tsrc, slots_8.io.out_uop.debug_tsrc \n connect issue_slots[8].out_uop.debug_fsrc, slots_8.io.out_uop.debug_fsrc \n connect issue_slots[8].out_uop.bp_xcpt_if, slots_8.io.out_uop.bp_xcpt_if \n connect issue_slots[8].out_uop.bp_debug_if, slots_8.io.out_uop.bp_debug_if \n connect issue_slots[8].out_uop.xcpt_ma_if, slots_8.io.out_uop.xcpt_ma_if \n connect issue_slots[8].out_uop.xcpt_ae_if, slots_8.io.out_uop.xcpt_ae_if \n connect issue_slots[8].out_uop.xcpt_pf_if, slots_8.io.out_uop.xcpt_pf_if \n connect issue_slots[8].out_uop.fp_typ, slots_8.io.out_uop.fp_typ \n connect issue_slots[8].out_uop.fp_rm, slots_8.io.out_uop.fp_rm \n connect issue_slots[8].out_uop.fp_val, slots_8.io.out_uop.fp_val \n connect issue_slots[8].out_uop.fcn_op, slots_8.io.out_uop.fcn_op \n connect issue_slots[8].out_uop.fcn_dw, slots_8.io.out_uop.fcn_dw \n connect issue_slots[8].out_uop.frs3_en, slots_8.io.out_uop.frs3_en \n connect issue_slots[8].out_uop.lrs2_rtype, slots_8.io.out_uop.lrs2_rtype \n connect issue_slots[8].out_uop.lrs1_rtype, slots_8.io.out_uop.lrs1_rtype \n connect issue_slots[8].out_uop.dst_rtype, slots_8.io.out_uop.dst_rtype \n connect issue_slots[8].out_uop.lrs3, slots_8.io.out_uop.lrs3 \n connect issue_slots[8].out_uop.lrs2, slots_8.io.out_uop.lrs2 \n connect issue_slots[8].out_uop.lrs1, slots_8.io.out_uop.lrs1 \n connect issue_slots[8].out_uop.ldst, slots_8.io.out_uop.ldst \n connect issue_slots[8].out_uop.ldst_is_rs1, slots_8.io.out_uop.ldst_is_rs1 \n connect issue_slots[8].out_uop.csr_cmd, slots_8.io.out_uop.csr_cmd \n connect issue_slots[8].out_uop.flush_on_commit, slots_8.io.out_uop.flush_on_commit \n connect issue_slots[8].out_uop.is_unique, slots_8.io.out_uop.is_unique \n connect issue_slots[8].out_uop.uses_stq, slots_8.io.out_uop.uses_stq \n connect issue_slots[8].out_uop.uses_ldq, slots_8.io.out_uop.uses_ldq \n connect issue_slots[8].out_uop.mem_signed, slots_8.io.out_uop.mem_signed \n connect issue_slots[8].out_uop.mem_size, slots_8.io.out_uop.mem_size \n connect issue_slots[8].out_uop.mem_cmd, slots_8.io.out_uop.mem_cmd \n connect issue_slots[8].out_uop.exc_cause, slots_8.io.out_uop.exc_cause \n connect issue_slots[8].out_uop.exception, slots_8.io.out_uop.exception \n connect issue_slots[8].out_uop.stale_pdst, slots_8.io.out_uop.stale_pdst \n connect issue_slots[8].out_uop.ppred_busy, slots_8.io.out_uop.ppred_busy \n connect issue_slots[8].out_uop.prs3_busy, slots_8.io.out_uop.prs3_busy \n connect issue_slots[8].out_uop.prs2_busy, slots_8.io.out_uop.prs2_busy \n connect issue_slots[8].out_uop.prs1_busy, slots_8.io.out_uop.prs1_busy \n connect issue_slots[8].out_uop.ppred, slots_8.io.out_uop.ppred \n connect issue_slots[8].out_uop.prs3, slots_8.io.out_uop.prs3 \n connect issue_slots[8].out_uop.prs2, slots_8.io.out_uop.prs2 \n connect issue_slots[8].out_uop.prs1, slots_8.io.out_uop.prs1 \n connect issue_slots[8].out_uop.pdst, slots_8.io.out_uop.pdst \n connect issue_slots[8].out_uop.rxq_idx, slots_8.io.out_uop.rxq_idx \n connect issue_slots[8].out_uop.stq_idx, slots_8.io.out_uop.stq_idx \n connect issue_slots[8].out_uop.ldq_idx, slots_8.io.out_uop.ldq_idx \n connect issue_slots[8].out_uop.rob_idx, slots_8.io.out_uop.rob_idx \n connect issue_slots[8].out_uop.fp_ctrl.vec, slots_8.io.out_uop.fp_ctrl.vec \n connect issue_slots[8].out_uop.fp_ctrl.wflags, slots_8.io.out_uop.fp_ctrl.wflags \n connect issue_slots[8].out_uop.fp_ctrl.sqrt, slots_8.io.out_uop.fp_ctrl.sqrt \n connect issue_slots[8].out_uop.fp_ctrl.div, slots_8.io.out_uop.fp_ctrl.div \n connect issue_slots[8].out_uop.fp_ctrl.fma, slots_8.io.out_uop.fp_ctrl.fma \n connect issue_slots[8].out_uop.fp_ctrl.fastpipe, slots_8.io.out_uop.fp_ctrl.fastpipe \n connect issue_slots[8].out_uop.fp_ctrl.toint, slots_8.io.out_uop.fp_ctrl.toint \n connect issue_slots[8].out_uop.fp_ctrl.fromint, slots_8.io.out_uop.fp_ctrl.fromint \n connect issue_slots[8].out_uop.fp_ctrl.typeTagOut, slots_8.io.out_uop.fp_ctrl.typeTagOut \n connect issue_slots[8].out_uop.fp_ctrl.typeTagIn, slots_8.io.out_uop.fp_ctrl.typeTagIn \n connect issue_slots[8].out_uop.fp_ctrl.swap23, slots_8.io.out_uop.fp_ctrl.swap23 \n connect issue_slots[8].out_uop.fp_ctrl.swap12, slots_8.io.out_uop.fp_ctrl.swap12 \n connect issue_slots[8].out_uop.fp_ctrl.ren3, slots_8.io.out_uop.fp_ctrl.ren3 \n connect issue_slots[8].out_uop.fp_ctrl.ren2, slots_8.io.out_uop.fp_ctrl.ren2 \n connect issue_slots[8].out_uop.fp_ctrl.ren1, slots_8.io.out_uop.fp_ctrl.ren1 \n connect issue_slots[8].out_uop.fp_ctrl.wen, slots_8.io.out_uop.fp_ctrl.wen \n connect issue_slots[8].out_uop.fp_ctrl.ldst, slots_8.io.out_uop.fp_ctrl.ldst \n connect issue_slots[8].out_uop.op2_sel, slots_8.io.out_uop.op2_sel \n connect issue_slots[8].out_uop.op1_sel, slots_8.io.out_uop.op1_sel \n connect issue_slots[8].out_uop.imm_packed, slots_8.io.out_uop.imm_packed \n connect issue_slots[8].out_uop.pimm, slots_8.io.out_uop.pimm \n connect issue_slots[8].out_uop.imm_sel, slots_8.io.out_uop.imm_sel \n connect issue_slots[8].out_uop.imm_rename, slots_8.io.out_uop.imm_rename \n connect issue_slots[8].out_uop.taken, slots_8.io.out_uop.taken \n connect issue_slots[8].out_uop.pc_lob, slots_8.io.out_uop.pc_lob \n connect issue_slots[8].out_uop.edge_inst, slots_8.io.out_uop.edge_inst \n connect issue_slots[8].out_uop.ftq_idx, slots_8.io.out_uop.ftq_idx \n connect issue_slots[8].out_uop.is_mov, slots_8.io.out_uop.is_mov \n connect issue_slots[8].out_uop.is_rocc, slots_8.io.out_uop.is_rocc \n connect issue_slots[8].out_uop.is_sys_pc2epc, slots_8.io.out_uop.is_sys_pc2epc \n connect issue_slots[8].out_uop.is_eret, slots_8.io.out_uop.is_eret \n connect issue_slots[8].out_uop.is_amo, slots_8.io.out_uop.is_amo \n connect issue_slots[8].out_uop.is_sfence, slots_8.io.out_uop.is_sfence \n connect issue_slots[8].out_uop.is_fencei, slots_8.io.out_uop.is_fencei \n connect issue_slots[8].out_uop.is_fence, slots_8.io.out_uop.is_fence \n connect issue_slots[8].out_uop.is_sfb, slots_8.io.out_uop.is_sfb \n connect issue_slots[8].out_uop.br_type, slots_8.io.out_uop.br_type \n connect issue_slots[8].out_uop.br_tag, slots_8.io.out_uop.br_tag \n connect issue_slots[8].out_uop.br_mask, slots_8.io.out_uop.br_mask \n connect issue_slots[8].out_uop.dis_col_sel, slots_8.io.out_uop.dis_col_sel \n connect issue_slots[8].out_uop.iw_p3_bypass_hint, slots_8.io.out_uop.iw_p3_bypass_hint \n connect issue_slots[8].out_uop.iw_p2_bypass_hint, slots_8.io.out_uop.iw_p2_bypass_hint \n connect issue_slots[8].out_uop.iw_p1_bypass_hint, slots_8.io.out_uop.iw_p1_bypass_hint \n connect issue_slots[8].out_uop.iw_p2_speculative_child, slots_8.io.out_uop.iw_p2_speculative_child \n connect issue_slots[8].out_uop.iw_p1_speculative_child, slots_8.io.out_uop.iw_p1_speculative_child \n connect issue_slots[8].out_uop.iw_issued_partial_dgen, slots_8.io.out_uop.iw_issued_partial_dgen \n connect issue_slots[8].out_uop.iw_issued_partial_agen, slots_8.io.out_uop.iw_issued_partial_agen \n connect issue_slots[8].out_uop.iw_issued, slots_8.io.out_uop.iw_issued \n connect issue_slots[8].out_uop.fu_code[0], slots_8.io.out_uop.fu_code[0] \n connect issue_slots[8].out_uop.fu_code[1], slots_8.io.out_uop.fu_code[1] \n connect issue_slots[8].out_uop.fu_code[2], slots_8.io.out_uop.fu_code[2] \n connect issue_slots[8].out_uop.fu_code[3], slots_8.io.out_uop.fu_code[3] \n connect issue_slots[8].out_uop.fu_code[4], slots_8.io.out_uop.fu_code[4] \n connect issue_slots[8].out_uop.fu_code[5], slots_8.io.out_uop.fu_code[5] \n connect issue_slots[8].out_uop.fu_code[6], slots_8.io.out_uop.fu_code[6] \n connect issue_slots[8].out_uop.fu_code[7], slots_8.io.out_uop.fu_code[7] \n connect issue_slots[8].out_uop.fu_code[8], slots_8.io.out_uop.fu_code[8] \n connect issue_slots[8].out_uop.fu_code[9], slots_8.io.out_uop.fu_code[9] \n connect issue_slots[8].out_uop.iq_type[0], slots_8.io.out_uop.iq_type[0] \n connect issue_slots[8].out_uop.iq_type[1], slots_8.io.out_uop.iq_type[1] \n connect issue_slots[8].out_uop.iq_type[2], slots_8.io.out_uop.iq_type[2] \n connect issue_slots[8].out_uop.iq_type[3], slots_8.io.out_uop.iq_type[3] \n connect issue_slots[8].out_uop.debug_pc, slots_8.io.out_uop.debug_pc \n connect issue_slots[8].out_uop.is_rvc, slots_8.io.out_uop.is_rvc \n connect issue_slots[8].out_uop.debug_inst, slots_8.io.out_uop.debug_inst \n connect issue_slots[8].out_uop.inst, slots_8.io.out_uop.inst \n connect slots_8.io.in_uop.bits.debug_tsrc, issue_slots[8].in_uop.bits.debug_tsrc \n connect slots_8.io.in_uop.bits.debug_fsrc, issue_slots[8].in_uop.bits.debug_fsrc \n connect slots_8.io.in_uop.bits.bp_xcpt_if, issue_slots[8].in_uop.bits.bp_xcpt_if \n connect slots_8.io.in_uop.bits.bp_debug_if, issue_slots[8].in_uop.bits.bp_debug_if \n connect slots_8.io.in_uop.bits.xcpt_ma_if, issue_slots[8].in_uop.bits.xcpt_ma_if \n connect slots_8.io.in_uop.bits.xcpt_ae_if, issue_slots[8].in_uop.bits.xcpt_ae_if \n connect slots_8.io.in_uop.bits.xcpt_pf_if, issue_slots[8].in_uop.bits.xcpt_pf_if \n connect slots_8.io.in_uop.bits.fp_typ, issue_slots[8].in_uop.bits.fp_typ \n connect slots_8.io.in_uop.bits.fp_rm, issue_slots[8].in_uop.bits.fp_rm \n connect slots_8.io.in_uop.bits.fp_val, issue_slots[8].in_uop.bits.fp_val \n connect slots_8.io.in_uop.bits.fcn_op, issue_slots[8].in_uop.bits.fcn_op \n connect slots_8.io.in_uop.bits.fcn_dw, issue_slots[8].in_uop.bits.fcn_dw \n connect slots_8.io.in_uop.bits.frs3_en, issue_slots[8].in_uop.bits.frs3_en \n connect slots_8.io.in_uop.bits.lrs2_rtype, issue_slots[8].in_uop.bits.lrs2_rtype \n connect slots_8.io.in_uop.bits.lrs1_rtype, issue_slots[8].in_uop.bits.lrs1_rtype \n connect slots_8.io.in_uop.bits.dst_rtype, issue_slots[8].in_uop.bits.dst_rtype \n connect slots_8.io.in_uop.bits.lrs3, issue_slots[8].in_uop.bits.lrs3 \n connect slots_8.io.in_uop.bits.lrs2, issue_slots[8].in_uop.bits.lrs2 \n connect slots_8.io.in_uop.bits.lrs1, issue_slots[8].in_uop.bits.lrs1 \n connect slots_8.io.in_uop.bits.ldst, issue_slots[8].in_uop.bits.ldst \n connect slots_8.io.in_uop.bits.ldst_is_rs1, issue_slots[8].in_uop.bits.ldst_is_rs1 \n connect slots_8.io.in_uop.bits.csr_cmd, issue_slots[8].in_uop.bits.csr_cmd \n connect slots_8.io.in_uop.bits.flush_on_commit, issue_slots[8].in_uop.bits.flush_on_commit \n connect slots_8.io.in_uop.bits.is_unique, issue_slots[8].in_uop.bits.is_unique \n connect slots_8.io.in_uop.bits.uses_stq, issue_slots[8].in_uop.bits.uses_stq \n connect slots_8.io.in_uop.bits.uses_ldq, issue_slots[8].in_uop.bits.uses_ldq \n connect slots_8.io.in_uop.bits.mem_signed, issue_slots[8].in_uop.bits.mem_signed \n connect slots_8.io.in_uop.bits.mem_size, issue_slots[8].in_uop.bits.mem_size \n connect slots_8.io.in_uop.bits.mem_cmd, issue_slots[8].in_uop.bits.mem_cmd \n connect slots_8.io.in_uop.bits.exc_cause, issue_slots[8].in_uop.bits.exc_cause \n connect slots_8.io.in_uop.bits.exception, issue_slots[8].in_uop.bits.exception \n connect slots_8.io.in_uop.bits.stale_pdst, issue_slots[8].in_uop.bits.stale_pdst \n connect slots_8.io.in_uop.bits.ppred_busy, issue_slots[8].in_uop.bits.ppred_busy \n connect slots_8.io.in_uop.bits.prs3_busy, issue_slots[8].in_uop.bits.prs3_busy \n connect slots_8.io.in_uop.bits.prs2_busy, issue_slots[8].in_uop.bits.prs2_busy \n connect slots_8.io.in_uop.bits.prs1_busy, issue_slots[8].in_uop.bits.prs1_busy \n connect slots_8.io.in_uop.bits.ppred, issue_slots[8].in_uop.bits.ppred \n connect slots_8.io.in_uop.bits.prs3, issue_slots[8].in_uop.bits.prs3 \n connect slots_8.io.in_uop.bits.prs2, issue_slots[8].in_uop.bits.prs2 \n connect slots_8.io.in_uop.bits.prs1, issue_slots[8].in_uop.bits.prs1 \n connect slots_8.io.in_uop.bits.pdst, issue_slots[8].in_uop.bits.pdst \n connect slots_8.io.in_uop.bits.rxq_idx, issue_slots[8].in_uop.bits.rxq_idx \n connect slots_8.io.in_uop.bits.stq_idx, issue_slots[8].in_uop.bits.stq_idx \n connect slots_8.io.in_uop.bits.ldq_idx, issue_slots[8].in_uop.bits.ldq_idx \n connect slots_8.io.in_uop.bits.rob_idx, issue_slots[8].in_uop.bits.rob_idx \n connect slots_8.io.in_uop.bits.fp_ctrl.vec, issue_slots[8].in_uop.bits.fp_ctrl.vec \n connect slots_8.io.in_uop.bits.fp_ctrl.wflags, issue_slots[8].in_uop.bits.fp_ctrl.wflags \n connect slots_8.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[8].in_uop.bits.fp_ctrl.sqrt \n connect slots_8.io.in_uop.bits.fp_ctrl.div, issue_slots[8].in_uop.bits.fp_ctrl.div \n connect slots_8.io.in_uop.bits.fp_ctrl.fma, issue_slots[8].in_uop.bits.fp_ctrl.fma \n connect slots_8.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[8].in_uop.bits.fp_ctrl.fastpipe \n connect slots_8.io.in_uop.bits.fp_ctrl.toint, issue_slots[8].in_uop.bits.fp_ctrl.toint \n connect slots_8.io.in_uop.bits.fp_ctrl.fromint, issue_slots[8].in_uop.bits.fp_ctrl.fromint \n connect slots_8.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[8].in_uop.bits.fp_ctrl.typeTagOut \n connect slots_8.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[8].in_uop.bits.fp_ctrl.typeTagIn \n connect slots_8.io.in_uop.bits.fp_ctrl.swap23, issue_slots[8].in_uop.bits.fp_ctrl.swap23 \n connect slots_8.io.in_uop.bits.fp_ctrl.swap12, issue_slots[8].in_uop.bits.fp_ctrl.swap12 \n connect slots_8.io.in_uop.bits.fp_ctrl.ren3, issue_slots[8].in_uop.bits.fp_ctrl.ren3 \n connect slots_8.io.in_uop.bits.fp_ctrl.ren2, issue_slots[8].in_uop.bits.fp_ctrl.ren2 \n connect slots_8.io.in_uop.bits.fp_ctrl.ren1, issue_slots[8].in_uop.bits.fp_ctrl.ren1 \n connect slots_8.io.in_uop.bits.fp_ctrl.wen, issue_slots[8].in_uop.bits.fp_ctrl.wen \n connect slots_8.io.in_uop.bits.fp_ctrl.ldst, issue_slots[8].in_uop.bits.fp_ctrl.ldst \n connect slots_8.io.in_uop.bits.op2_sel, issue_slots[8].in_uop.bits.op2_sel \n connect slots_8.io.in_uop.bits.op1_sel, issue_slots[8].in_uop.bits.op1_sel \n connect slots_8.io.in_uop.bits.imm_packed, issue_slots[8].in_uop.bits.imm_packed \n connect slots_8.io.in_uop.bits.pimm, issue_slots[8].in_uop.bits.pimm \n connect slots_8.io.in_uop.bits.imm_sel, issue_slots[8].in_uop.bits.imm_sel \n connect slots_8.io.in_uop.bits.imm_rename, issue_slots[8].in_uop.bits.imm_rename \n connect slots_8.io.in_uop.bits.taken, issue_slots[8].in_uop.bits.taken \n connect slots_8.io.in_uop.bits.pc_lob, issue_slots[8].in_uop.bits.pc_lob \n connect slots_8.io.in_uop.bits.edge_inst, issue_slots[8].in_uop.bits.edge_inst \n connect slots_8.io.in_uop.bits.ftq_idx, issue_slots[8].in_uop.bits.ftq_idx \n connect slots_8.io.in_uop.bits.is_mov, issue_slots[8].in_uop.bits.is_mov \n connect slots_8.io.in_uop.bits.is_rocc, issue_slots[8].in_uop.bits.is_rocc \n connect slots_8.io.in_uop.bits.is_sys_pc2epc, issue_slots[8].in_uop.bits.is_sys_pc2epc \n connect slots_8.io.in_uop.bits.is_eret, issue_slots[8].in_uop.bits.is_eret \n connect slots_8.io.in_uop.bits.is_amo, issue_slots[8].in_uop.bits.is_amo \n connect slots_8.io.in_uop.bits.is_sfence, issue_slots[8].in_uop.bits.is_sfence \n connect slots_8.io.in_uop.bits.is_fencei, issue_slots[8].in_uop.bits.is_fencei \n connect slots_8.io.in_uop.bits.is_fence, issue_slots[8].in_uop.bits.is_fence \n connect slots_8.io.in_uop.bits.is_sfb, issue_slots[8].in_uop.bits.is_sfb \n connect slots_8.io.in_uop.bits.br_type, issue_slots[8].in_uop.bits.br_type \n connect slots_8.io.in_uop.bits.br_tag, issue_slots[8].in_uop.bits.br_tag \n connect slots_8.io.in_uop.bits.br_mask, issue_slots[8].in_uop.bits.br_mask \n connect slots_8.io.in_uop.bits.dis_col_sel, issue_slots[8].in_uop.bits.dis_col_sel \n connect slots_8.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[8].in_uop.bits.iw_p3_bypass_hint \n connect slots_8.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[8].in_uop.bits.iw_p2_bypass_hint \n connect slots_8.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[8].in_uop.bits.iw_p1_bypass_hint \n connect slots_8.io.in_uop.bits.iw_p2_speculative_child, issue_slots[8].in_uop.bits.iw_p2_speculative_child \n connect slots_8.io.in_uop.bits.iw_p1_speculative_child, issue_slots[8].in_uop.bits.iw_p1_speculative_child \n connect slots_8.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[8].in_uop.bits.iw_issued_partial_dgen \n connect slots_8.io.in_uop.bits.iw_issued_partial_agen, issue_slots[8].in_uop.bits.iw_issued_partial_agen \n connect slots_8.io.in_uop.bits.iw_issued, issue_slots[8].in_uop.bits.iw_issued \n connect slots_8.io.in_uop.bits.fu_code[0], issue_slots[8].in_uop.bits.fu_code[0] \n connect slots_8.io.in_uop.bits.fu_code[1], issue_slots[8].in_uop.bits.fu_code[1] \n connect slots_8.io.in_uop.bits.fu_code[2], issue_slots[8].in_uop.bits.fu_code[2] \n connect slots_8.io.in_uop.bits.fu_code[3], issue_slots[8].in_uop.bits.fu_code[3] \n connect slots_8.io.in_uop.bits.fu_code[4], issue_slots[8].in_uop.bits.fu_code[4] \n connect slots_8.io.in_uop.bits.fu_code[5], issue_slots[8].in_uop.bits.fu_code[5] \n connect slots_8.io.in_uop.bits.fu_code[6], issue_slots[8].in_uop.bits.fu_code[6] \n connect slots_8.io.in_uop.bits.fu_code[7], issue_slots[8].in_uop.bits.fu_code[7] \n connect slots_8.io.in_uop.bits.fu_code[8], issue_slots[8].in_uop.bits.fu_code[8] \n connect slots_8.io.in_uop.bits.fu_code[9], issue_slots[8].in_uop.bits.fu_code[9] \n connect slots_8.io.in_uop.bits.iq_type[0], issue_slots[8].in_uop.bits.iq_type[0] \n connect slots_8.io.in_uop.bits.iq_type[1], issue_slots[8].in_uop.bits.iq_type[1] \n connect slots_8.io.in_uop.bits.iq_type[2], issue_slots[8].in_uop.bits.iq_type[2] \n connect slots_8.io.in_uop.bits.iq_type[3], issue_slots[8].in_uop.bits.iq_type[3] \n connect slots_8.io.in_uop.bits.debug_pc, issue_slots[8].in_uop.bits.debug_pc \n connect slots_8.io.in_uop.bits.is_rvc, issue_slots[8].in_uop.bits.is_rvc \n connect slots_8.io.in_uop.bits.debug_inst, issue_slots[8].in_uop.bits.debug_inst \n connect slots_8.io.in_uop.bits.inst, issue_slots[8].in_uop.bits.inst \n connect slots_8.io.in_uop.valid, issue_slots[8].in_uop.valid \n connect issue_slots[8].iss_uop.debug_tsrc, slots_8.io.iss_uop.debug_tsrc \n connect issue_slots[8].iss_uop.debug_fsrc, slots_8.io.iss_uop.debug_fsrc \n connect issue_slots[8].iss_uop.bp_xcpt_if, slots_8.io.iss_uop.bp_xcpt_if \n connect issue_slots[8].iss_uop.bp_debug_if, slots_8.io.iss_uop.bp_debug_if \n connect issue_slots[8].iss_uop.xcpt_ma_if, slots_8.io.iss_uop.xcpt_ma_if \n connect issue_slots[8].iss_uop.xcpt_ae_if, slots_8.io.iss_uop.xcpt_ae_if \n connect issue_slots[8].iss_uop.xcpt_pf_if, slots_8.io.iss_uop.xcpt_pf_if \n connect issue_slots[8].iss_uop.fp_typ, slots_8.io.iss_uop.fp_typ \n connect issue_slots[8].iss_uop.fp_rm, slots_8.io.iss_uop.fp_rm \n connect issue_slots[8].iss_uop.fp_val, slots_8.io.iss_uop.fp_val \n connect issue_slots[8].iss_uop.fcn_op, slots_8.io.iss_uop.fcn_op \n connect issue_slots[8].iss_uop.fcn_dw, slots_8.io.iss_uop.fcn_dw \n connect issue_slots[8].iss_uop.frs3_en, slots_8.io.iss_uop.frs3_en \n connect issue_slots[8].iss_uop.lrs2_rtype, slots_8.io.iss_uop.lrs2_rtype \n connect issue_slots[8].iss_uop.lrs1_rtype, slots_8.io.iss_uop.lrs1_rtype \n connect issue_slots[8].iss_uop.dst_rtype, slots_8.io.iss_uop.dst_rtype \n connect issue_slots[8].iss_uop.lrs3, slots_8.io.iss_uop.lrs3 \n connect issue_slots[8].iss_uop.lrs2, slots_8.io.iss_uop.lrs2 \n connect issue_slots[8].iss_uop.lrs1, slots_8.io.iss_uop.lrs1 \n connect issue_slots[8].iss_uop.ldst, slots_8.io.iss_uop.ldst \n connect issue_slots[8].iss_uop.ldst_is_rs1, slots_8.io.iss_uop.ldst_is_rs1 \n connect issue_slots[8].iss_uop.csr_cmd, slots_8.io.iss_uop.csr_cmd \n connect issue_slots[8].iss_uop.flush_on_commit, slots_8.io.iss_uop.flush_on_commit \n connect issue_slots[8].iss_uop.is_unique, slots_8.io.iss_uop.is_unique \n connect issue_slots[8].iss_uop.uses_stq, slots_8.io.iss_uop.uses_stq \n connect issue_slots[8].iss_uop.uses_ldq, slots_8.io.iss_uop.uses_ldq \n connect issue_slots[8].iss_uop.mem_signed, slots_8.io.iss_uop.mem_signed \n connect issue_slots[8].iss_uop.mem_size, slots_8.io.iss_uop.mem_size \n connect issue_slots[8].iss_uop.mem_cmd, slots_8.io.iss_uop.mem_cmd \n connect issue_slots[8].iss_uop.exc_cause, slots_8.io.iss_uop.exc_cause \n connect issue_slots[8].iss_uop.exception, slots_8.io.iss_uop.exception \n connect issue_slots[8].iss_uop.stale_pdst, slots_8.io.iss_uop.stale_pdst \n connect issue_slots[8].iss_uop.ppred_busy, slots_8.io.iss_uop.ppred_busy \n connect issue_slots[8].iss_uop.prs3_busy, slots_8.io.iss_uop.prs3_busy \n connect issue_slots[8].iss_uop.prs2_busy, slots_8.io.iss_uop.prs2_busy \n connect issue_slots[8].iss_uop.prs1_busy, slots_8.io.iss_uop.prs1_busy \n connect issue_slots[8].iss_uop.ppred, slots_8.io.iss_uop.ppred \n connect issue_slots[8].iss_uop.prs3, slots_8.io.iss_uop.prs3 \n connect issue_slots[8].iss_uop.prs2, slots_8.io.iss_uop.prs2 \n connect issue_slots[8].iss_uop.prs1, slots_8.io.iss_uop.prs1 \n connect issue_slots[8].iss_uop.pdst, slots_8.io.iss_uop.pdst \n connect issue_slots[8].iss_uop.rxq_idx, slots_8.io.iss_uop.rxq_idx \n connect issue_slots[8].iss_uop.stq_idx, slots_8.io.iss_uop.stq_idx \n connect issue_slots[8].iss_uop.ldq_idx, slots_8.io.iss_uop.ldq_idx \n connect issue_slots[8].iss_uop.rob_idx, slots_8.io.iss_uop.rob_idx \n connect issue_slots[8].iss_uop.fp_ctrl.vec, slots_8.io.iss_uop.fp_ctrl.vec \n connect issue_slots[8].iss_uop.fp_ctrl.wflags, slots_8.io.iss_uop.fp_ctrl.wflags \n connect issue_slots[8].iss_uop.fp_ctrl.sqrt, slots_8.io.iss_uop.fp_ctrl.sqrt \n connect issue_slots[8].iss_uop.fp_ctrl.div, slots_8.io.iss_uop.fp_ctrl.div \n connect issue_slots[8].iss_uop.fp_ctrl.fma, slots_8.io.iss_uop.fp_ctrl.fma \n connect issue_slots[8].iss_uop.fp_ctrl.fastpipe, slots_8.io.iss_uop.fp_ctrl.fastpipe \n connect issue_slots[8].iss_uop.fp_ctrl.toint, slots_8.io.iss_uop.fp_ctrl.toint \n connect issue_slots[8].iss_uop.fp_ctrl.fromint, slots_8.io.iss_uop.fp_ctrl.fromint \n connect issue_slots[8].iss_uop.fp_ctrl.typeTagOut, slots_8.io.iss_uop.fp_ctrl.typeTagOut \n connect issue_slots[8].iss_uop.fp_ctrl.typeTagIn, slots_8.io.iss_uop.fp_ctrl.typeTagIn \n connect issue_slots[8].iss_uop.fp_ctrl.swap23, slots_8.io.iss_uop.fp_ctrl.swap23 \n connect issue_slots[8].iss_uop.fp_ctrl.swap12, slots_8.io.iss_uop.fp_ctrl.swap12 \n connect issue_slots[8].iss_uop.fp_ctrl.ren3, slots_8.io.iss_uop.fp_ctrl.ren3 \n connect issue_slots[8].iss_uop.fp_ctrl.ren2, slots_8.io.iss_uop.fp_ctrl.ren2 \n connect issue_slots[8].iss_uop.fp_ctrl.ren1, slots_8.io.iss_uop.fp_ctrl.ren1 \n connect issue_slots[8].iss_uop.fp_ctrl.wen, slots_8.io.iss_uop.fp_ctrl.wen \n connect issue_slots[8].iss_uop.fp_ctrl.ldst, slots_8.io.iss_uop.fp_ctrl.ldst \n connect issue_slots[8].iss_uop.op2_sel, slots_8.io.iss_uop.op2_sel \n connect issue_slots[8].iss_uop.op1_sel, slots_8.io.iss_uop.op1_sel \n connect issue_slots[8].iss_uop.imm_packed, slots_8.io.iss_uop.imm_packed \n connect issue_slots[8].iss_uop.pimm, slots_8.io.iss_uop.pimm \n connect issue_slots[8].iss_uop.imm_sel, slots_8.io.iss_uop.imm_sel \n connect issue_slots[8].iss_uop.imm_rename, slots_8.io.iss_uop.imm_rename \n connect issue_slots[8].iss_uop.taken, slots_8.io.iss_uop.taken \n connect issue_slots[8].iss_uop.pc_lob, slots_8.io.iss_uop.pc_lob \n connect issue_slots[8].iss_uop.edge_inst, slots_8.io.iss_uop.edge_inst \n connect issue_slots[8].iss_uop.ftq_idx, slots_8.io.iss_uop.ftq_idx \n connect issue_slots[8].iss_uop.is_mov, slots_8.io.iss_uop.is_mov \n connect issue_slots[8].iss_uop.is_rocc, slots_8.io.iss_uop.is_rocc \n connect issue_slots[8].iss_uop.is_sys_pc2epc, slots_8.io.iss_uop.is_sys_pc2epc \n connect issue_slots[8].iss_uop.is_eret, slots_8.io.iss_uop.is_eret \n connect issue_slots[8].iss_uop.is_amo, slots_8.io.iss_uop.is_amo \n connect issue_slots[8].iss_uop.is_sfence, slots_8.io.iss_uop.is_sfence \n connect issue_slots[8].iss_uop.is_fencei, slots_8.io.iss_uop.is_fencei \n connect issue_slots[8].iss_uop.is_fence, slots_8.io.iss_uop.is_fence \n connect issue_slots[8].iss_uop.is_sfb, slots_8.io.iss_uop.is_sfb \n connect issue_slots[8].iss_uop.br_type, slots_8.io.iss_uop.br_type \n connect issue_slots[8].iss_uop.br_tag, slots_8.io.iss_uop.br_tag \n connect issue_slots[8].iss_uop.br_mask, slots_8.io.iss_uop.br_mask \n connect issue_slots[8].iss_uop.dis_col_sel, slots_8.io.iss_uop.dis_col_sel \n connect issue_slots[8].iss_uop.iw_p3_bypass_hint, slots_8.io.iss_uop.iw_p3_bypass_hint \n connect issue_slots[8].iss_uop.iw_p2_bypass_hint, slots_8.io.iss_uop.iw_p2_bypass_hint \n connect issue_slots[8].iss_uop.iw_p1_bypass_hint, slots_8.io.iss_uop.iw_p1_bypass_hint \n connect issue_slots[8].iss_uop.iw_p2_speculative_child, slots_8.io.iss_uop.iw_p2_speculative_child \n connect issue_slots[8].iss_uop.iw_p1_speculative_child, slots_8.io.iss_uop.iw_p1_speculative_child \n connect issue_slots[8].iss_uop.iw_issued_partial_dgen, slots_8.io.iss_uop.iw_issued_partial_dgen \n connect issue_slots[8].iss_uop.iw_issued_partial_agen, slots_8.io.iss_uop.iw_issued_partial_agen \n connect issue_slots[8].iss_uop.iw_issued, slots_8.io.iss_uop.iw_issued \n connect issue_slots[8].iss_uop.fu_code[0], slots_8.io.iss_uop.fu_code[0] \n connect issue_slots[8].iss_uop.fu_code[1], slots_8.io.iss_uop.fu_code[1] \n connect issue_slots[8].iss_uop.fu_code[2], slots_8.io.iss_uop.fu_code[2] \n connect issue_slots[8].iss_uop.fu_code[3], slots_8.io.iss_uop.fu_code[3] \n connect issue_slots[8].iss_uop.fu_code[4], slots_8.io.iss_uop.fu_code[4] \n connect issue_slots[8].iss_uop.fu_code[5], slots_8.io.iss_uop.fu_code[5] \n connect issue_slots[8].iss_uop.fu_code[6], slots_8.io.iss_uop.fu_code[6] \n connect issue_slots[8].iss_uop.fu_code[7], slots_8.io.iss_uop.fu_code[7] \n connect issue_slots[8].iss_uop.fu_code[8], slots_8.io.iss_uop.fu_code[8] \n connect issue_slots[8].iss_uop.fu_code[9], slots_8.io.iss_uop.fu_code[9] \n connect issue_slots[8].iss_uop.iq_type[0], slots_8.io.iss_uop.iq_type[0] \n connect issue_slots[8].iss_uop.iq_type[1], slots_8.io.iss_uop.iq_type[1] \n connect issue_slots[8].iss_uop.iq_type[2], slots_8.io.iss_uop.iq_type[2] \n connect issue_slots[8].iss_uop.iq_type[3], slots_8.io.iss_uop.iq_type[3] \n connect issue_slots[8].iss_uop.debug_pc, slots_8.io.iss_uop.debug_pc \n connect issue_slots[8].iss_uop.is_rvc, slots_8.io.iss_uop.is_rvc \n connect issue_slots[8].iss_uop.debug_inst, slots_8.io.iss_uop.debug_inst \n connect issue_slots[8].iss_uop.inst, slots_8.io.iss_uop.inst \n connect slots_8.io.grant, issue_slots[8].grant \n connect issue_slots[8].request, slots_8.io.request \n connect issue_slots[8].will_be_valid, slots_8.io.will_be_valid \n connect issue_slots[8].valid, slots_8.io.valid \n connect slots_9.io.child_rebusys, issue_slots[9].child_rebusys \n connect slots_9.io.pred_wakeup_port.bits, issue_slots[9].pred_wakeup_port.bits \n connect slots_9.io.pred_wakeup_port.valid, issue_slots[9].pred_wakeup_port.valid \n connect slots_9.io.wakeup_ports[0].bits.rebusy, issue_slots[9].wakeup_ports[0].bits.rebusy \n connect slots_9.io.wakeup_ports[0].bits.speculative_mask, issue_slots[9].wakeup_ports[0].bits.speculative_mask \n connect slots_9.io.wakeup_ports[0].bits.bypassable, issue_slots[9].wakeup_ports[0].bits.bypassable \n connect slots_9.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[9].wakeup_ports[0].bits.uop.debug_tsrc \n connect slots_9.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[9].wakeup_ports[0].bits.uop.debug_fsrc \n connect slots_9.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[9].wakeup_ports[0].bits.uop.bp_xcpt_if \n connect slots_9.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[9].wakeup_ports[0].bits.uop.bp_debug_if \n connect slots_9.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[9].wakeup_ports[0].bits.uop.xcpt_ma_if \n connect slots_9.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[9].wakeup_ports[0].bits.uop.xcpt_ae_if \n connect slots_9.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[9].wakeup_ports[0].bits.uop.xcpt_pf_if \n connect slots_9.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[9].wakeup_ports[0].bits.uop.fp_typ \n connect slots_9.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[9].wakeup_ports[0].bits.uop.fp_rm \n connect slots_9.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[9].wakeup_ports[0].bits.uop.fp_val \n connect slots_9.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[9].wakeup_ports[0].bits.uop.fcn_op \n connect slots_9.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[9].wakeup_ports[0].bits.uop.fcn_dw \n connect slots_9.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[9].wakeup_ports[0].bits.uop.frs3_en \n connect slots_9.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[9].wakeup_ports[0].bits.uop.lrs2_rtype \n connect slots_9.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[9].wakeup_ports[0].bits.uop.lrs1_rtype \n connect slots_9.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[9].wakeup_ports[0].bits.uop.dst_rtype \n connect slots_9.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[9].wakeup_ports[0].bits.uop.lrs3 \n connect slots_9.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[9].wakeup_ports[0].bits.uop.lrs2 \n connect slots_9.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[9].wakeup_ports[0].bits.uop.lrs1 \n connect slots_9.io.wakeup_ports[0].bits.uop.ldst, issue_slots[9].wakeup_ports[0].bits.uop.ldst \n connect slots_9.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[9].wakeup_ports[0].bits.uop.ldst_is_rs1 \n connect slots_9.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[9].wakeup_ports[0].bits.uop.csr_cmd \n connect slots_9.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[9].wakeup_ports[0].bits.uop.flush_on_commit \n connect slots_9.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[9].wakeup_ports[0].bits.uop.is_unique \n connect slots_9.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[9].wakeup_ports[0].bits.uop.uses_stq \n connect slots_9.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[9].wakeup_ports[0].bits.uop.uses_ldq \n connect slots_9.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[9].wakeup_ports[0].bits.uop.mem_signed \n connect slots_9.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[9].wakeup_ports[0].bits.uop.mem_size \n connect slots_9.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[9].wakeup_ports[0].bits.uop.mem_cmd \n connect slots_9.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[9].wakeup_ports[0].bits.uop.exc_cause \n connect slots_9.io.wakeup_ports[0].bits.uop.exception, issue_slots[9].wakeup_ports[0].bits.uop.exception \n connect slots_9.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[9].wakeup_ports[0].bits.uop.stale_pdst \n connect slots_9.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[9].wakeup_ports[0].bits.uop.ppred_busy \n connect slots_9.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[9].wakeup_ports[0].bits.uop.prs3_busy \n connect slots_9.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[9].wakeup_ports[0].bits.uop.prs2_busy \n connect slots_9.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[9].wakeup_ports[0].bits.uop.prs1_busy \n connect slots_9.io.wakeup_ports[0].bits.uop.ppred, issue_slots[9].wakeup_ports[0].bits.uop.ppred \n connect slots_9.io.wakeup_ports[0].bits.uop.prs3, issue_slots[9].wakeup_ports[0].bits.uop.prs3 \n connect slots_9.io.wakeup_ports[0].bits.uop.prs2, issue_slots[9].wakeup_ports[0].bits.uop.prs2 \n connect slots_9.io.wakeup_ports[0].bits.uop.prs1, issue_slots[9].wakeup_ports[0].bits.uop.prs1 \n connect slots_9.io.wakeup_ports[0].bits.uop.pdst, issue_slots[9].wakeup_ports[0].bits.uop.pdst \n connect slots_9.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[9].wakeup_ports[0].bits.uop.rxq_idx \n connect slots_9.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[9].wakeup_ports[0].bits.uop.stq_idx \n connect slots_9.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[9].wakeup_ports[0].bits.uop.ldq_idx \n connect slots_9.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[9].wakeup_ports[0].bits.uop.rob_idx \n connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.vec \n connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.wflags \n connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.sqrt \n connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.div \n connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.fma \n connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe \n connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.toint \n connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.fromint \n connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut \n connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn \n connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.swap23 \n connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.swap12 \n connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.ren3 \n connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.ren2 \n connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.ren1 \n connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.wen \n connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.ldst \n connect slots_9.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[9].wakeup_ports[0].bits.uop.op2_sel \n connect slots_9.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[9].wakeup_ports[0].bits.uop.op1_sel \n connect slots_9.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[9].wakeup_ports[0].bits.uop.imm_packed \n connect slots_9.io.wakeup_ports[0].bits.uop.pimm, issue_slots[9].wakeup_ports[0].bits.uop.pimm \n connect slots_9.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[9].wakeup_ports[0].bits.uop.imm_sel \n connect slots_9.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[9].wakeup_ports[0].bits.uop.imm_rename \n connect slots_9.io.wakeup_ports[0].bits.uop.taken, issue_slots[9].wakeup_ports[0].bits.uop.taken \n connect slots_9.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[9].wakeup_ports[0].bits.uop.pc_lob \n connect slots_9.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[9].wakeup_ports[0].bits.uop.edge_inst \n connect slots_9.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[9].wakeup_ports[0].bits.uop.ftq_idx \n connect slots_9.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[9].wakeup_ports[0].bits.uop.is_mov \n connect slots_9.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[9].wakeup_ports[0].bits.uop.is_rocc \n connect slots_9.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[9].wakeup_ports[0].bits.uop.is_sys_pc2epc \n connect slots_9.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[9].wakeup_ports[0].bits.uop.is_eret \n connect slots_9.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[9].wakeup_ports[0].bits.uop.is_amo \n connect slots_9.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[9].wakeup_ports[0].bits.uop.is_sfence \n connect slots_9.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[9].wakeup_ports[0].bits.uop.is_fencei \n connect slots_9.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[9].wakeup_ports[0].bits.uop.is_fence \n connect slots_9.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[9].wakeup_ports[0].bits.uop.is_sfb \n connect slots_9.io.wakeup_ports[0].bits.uop.br_type, issue_slots[9].wakeup_ports[0].bits.uop.br_type \n connect slots_9.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[9].wakeup_ports[0].bits.uop.br_tag \n connect slots_9.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[9].wakeup_ports[0].bits.uop.br_mask \n connect slots_9.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[9].wakeup_ports[0].bits.uop.dis_col_sel \n connect slots_9.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[9].wakeup_ports[0].bits.uop.iw_p3_bypass_hint \n connect slots_9.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[9].wakeup_ports[0].bits.uop.iw_p2_bypass_hint \n connect slots_9.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[9].wakeup_ports[0].bits.uop.iw_p1_bypass_hint \n connect slots_9.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[9].wakeup_ports[0].bits.uop.iw_p2_speculative_child \n connect slots_9.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[9].wakeup_ports[0].bits.uop.iw_p1_speculative_child \n connect slots_9.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[9].wakeup_ports[0].bits.uop.iw_issued_partial_dgen \n connect slots_9.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[9].wakeup_ports[0].bits.uop.iw_issued_partial_agen \n connect slots_9.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[9].wakeup_ports[0].bits.uop.iw_issued \n connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[0] \n connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[1] \n connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[2] \n connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[3] \n connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[4] \n connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[5] \n connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[6] \n connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[7] \n connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[8] \n connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[9] \n connect slots_9.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[9].wakeup_ports[0].bits.uop.iq_type[0] \n connect slots_9.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[9].wakeup_ports[0].bits.uop.iq_type[1] \n connect slots_9.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[9].wakeup_ports[0].bits.uop.iq_type[2] \n connect slots_9.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[9].wakeup_ports[0].bits.uop.iq_type[3] \n connect slots_9.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[9].wakeup_ports[0].bits.uop.debug_pc \n connect slots_9.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[9].wakeup_ports[0].bits.uop.is_rvc \n connect slots_9.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[9].wakeup_ports[0].bits.uop.debug_inst \n connect slots_9.io.wakeup_ports[0].bits.uop.inst, issue_slots[9].wakeup_ports[0].bits.uop.inst \n connect slots_9.io.wakeup_ports[0].valid, issue_slots[9].wakeup_ports[0].valid \n connect slots_9.io.wakeup_ports[1].bits.rebusy, issue_slots[9].wakeup_ports[1].bits.rebusy \n connect slots_9.io.wakeup_ports[1].bits.speculative_mask, issue_slots[9].wakeup_ports[1].bits.speculative_mask \n connect slots_9.io.wakeup_ports[1].bits.bypassable, issue_slots[9].wakeup_ports[1].bits.bypassable \n connect slots_9.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[9].wakeup_ports[1].bits.uop.debug_tsrc \n connect slots_9.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[9].wakeup_ports[1].bits.uop.debug_fsrc \n connect slots_9.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[9].wakeup_ports[1].bits.uop.bp_xcpt_if \n connect slots_9.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[9].wakeup_ports[1].bits.uop.bp_debug_if \n connect slots_9.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[9].wakeup_ports[1].bits.uop.xcpt_ma_if \n connect slots_9.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[9].wakeup_ports[1].bits.uop.xcpt_ae_if \n connect slots_9.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[9].wakeup_ports[1].bits.uop.xcpt_pf_if \n connect slots_9.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[9].wakeup_ports[1].bits.uop.fp_typ \n connect slots_9.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[9].wakeup_ports[1].bits.uop.fp_rm \n connect slots_9.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[9].wakeup_ports[1].bits.uop.fp_val \n connect slots_9.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[9].wakeup_ports[1].bits.uop.fcn_op \n connect slots_9.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[9].wakeup_ports[1].bits.uop.fcn_dw \n connect slots_9.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[9].wakeup_ports[1].bits.uop.frs3_en \n connect slots_9.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[9].wakeup_ports[1].bits.uop.lrs2_rtype \n connect slots_9.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[9].wakeup_ports[1].bits.uop.lrs1_rtype \n connect slots_9.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[9].wakeup_ports[1].bits.uop.dst_rtype \n connect slots_9.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[9].wakeup_ports[1].bits.uop.lrs3 \n connect slots_9.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[9].wakeup_ports[1].bits.uop.lrs2 \n connect slots_9.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[9].wakeup_ports[1].bits.uop.lrs1 \n connect slots_9.io.wakeup_ports[1].bits.uop.ldst, issue_slots[9].wakeup_ports[1].bits.uop.ldst \n connect slots_9.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[9].wakeup_ports[1].bits.uop.ldst_is_rs1 \n connect slots_9.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[9].wakeup_ports[1].bits.uop.csr_cmd \n connect slots_9.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[9].wakeup_ports[1].bits.uop.flush_on_commit \n connect slots_9.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[9].wakeup_ports[1].bits.uop.is_unique \n connect slots_9.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[9].wakeup_ports[1].bits.uop.uses_stq \n connect slots_9.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[9].wakeup_ports[1].bits.uop.uses_ldq \n connect slots_9.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[9].wakeup_ports[1].bits.uop.mem_signed \n connect slots_9.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[9].wakeup_ports[1].bits.uop.mem_size \n connect slots_9.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[9].wakeup_ports[1].bits.uop.mem_cmd \n connect slots_9.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[9].wakeup_ports[1].bits.uop.exc_cause \n connect slots_9.io.wakeup_ports[1].bits.uop.exception, issue_slots[9].wakeup_ports[1].bits.uop.exception \n connect slots_9.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[9].wakeup_ports[1].bits.uop.stale_pdst \n connect slots_9.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[9].wakeup_ports[1].bits.uop.ppred_busy \n connect slots_9.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[9].wakeup_ports[1].bits.uop.prs3_busy \n connect slots_9.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[9].wakeup_ports[1].bits.uop.prs2_busy \n connect slots_9.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[9].wakeup_ports[1].bits.uop.prs1_busy \n connect slots_9.io.wakeup_ports[1].bits.uop.ppred, issue_slots[9].wakeup_ports[1].bits.uop.ppred \n connect slots_9.io.wakeup_ports[1].bits.uop.prs3, issue_slots[9].wakeup_ports[1].bits.uop.prs3 \n connect slots_9.io.wakeup_ports[1].bits.uop.prs2, issue_slots[9].wakeup_ports[1].bits.uop.prs2 \n connect slots_9.io.wakeup_ports[1].bits.uop.prs1, issue_slots[9].wakeup_ports[1].bits.uop.prs1 \n connect slots_9.io.wakeup_ports[1].bits.uop.pdst, issue_slots[9].wakeup_ports[1].bits.uop.pdst \n connect slots_9.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[9].wakeup_ports[1].bits.uop.rxq_idx \n connect slots_9.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[9].wakeup_ports[1].bits.uop.stq_idx \n connect slots_9.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[9].wakeup_ports[1].bits.uop.ldq_idx \n connect slots_9.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[9].wakeup_ports[1].bits.uop.rob_idx \n connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.vec \n connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.wflags \n connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.sqrt \n connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.div \n connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.fma \n connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe \n connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.toint \n connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.fromint \n connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut \n connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn \n connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.swap23 \n connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.swap12 \n connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.ren3 \n connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.ren2 \n connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.ren1 \n connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.wen \n connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.ldst \n connect slots_9.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[9].wakeup_ports[1].bits.uop.op2_sel \n connect slots_9.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[9].wakeup_ports[1].bits.uop.op1_sel \n connect slots_9.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[9].wakeup_ports[1].bits.uop.imm_packed \n connect slots_9.io.wakeup_ports[1].bits.uop.pimm, issue_slots[9].wakeup_ports[1].bits.uop.pimm \n connect slots_9.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[9].wakeup_ports[1].bits.uop.imm_sel \n connect slots_9.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[9].wakeup_ports[1].bits.uop.imm_rename \n connect slots_9.io.wakeup_ports[1].bits.uop.taken, issue_slots[9].wakeup_ports[1].bits.uop.taken \n connect slots_9.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[9].wakeup_ports[1].bits.uop.pc_lob \n connect slots_9.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[9].wakeup_ports[1].bits.uop.edge_inst \n connect slots_9.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[9].wakeup_ports[1].bits.uop.ftq_idx \n connect slots_9.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[9].wakeup_ports[1].bits.uop.is_mov \n connect slots_9.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[9].wakeup_ports[1].bits.uop.is_rocc \n connect slots_9.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[9].wakeup_ports[1].bits.uop.is_sys_pc2epc \n connect slots_9.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[9].wakeup_ports[1].bits.uop.is_eret \n connect slots_9.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[9].wakeup_ports[1].bits.uop.is_amo \n connect slots_9.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[9].wakeup_ports[1].bits.uop.is_sfence \n connect slots_9.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[9].wakeup_ports[1].bits.uop.is_fencei \n connect slots_9.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[9].wakeup_ports[1].bits.uop.is_fence \n connect slots_9.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[9].wakeup_ports[1].bits.uop.is_sfb \n connect slots_9.io.wakeup_ports[1].bits.uop.br_type, issue_slots[9].wakeup_ports[1].bits.uop.br_type \n connect slots_9.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[9].wakeup_ports[1].bits.uop.br_tag \n connect slots_9.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[9].wakeup_ports[1].bits.uop.br_mask \n connect slots_9.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[9].wakeup_ports[1].bits.uop.dis_col_sel \n connect slots_9.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[9].wakeup_ports[1].bits.uop.iw_p3_bypass_hint \n connect slots_9.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[9].wakeup_ports[1].bits.uop.iw_p2_bypass_hint \n connect slots_9.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[9].wakeup_ports[1].bits.uop.iw_p1_bypass_hint \n connect slots_9.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[9].wakeup_ports[1].bits.uop.iw_p2_speculative_child \n connect slots_9.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[9].wakeup_ports[1].bits.uop.iw_p1_speculative_child \n connect slots_9.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[9].wakeup_ports[1].bits.uop.iw_issued_partial_dgen \n connect slots_9.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[9].wakeup_ports[1].bits.uop.iw_issued_partial_agen \n connect slots_9.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[9].wakeup_ports[1].bits.uop.iw_issued \n connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[0] \n connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[1] \n connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[2] \n connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[3] \n connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[4] \n connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[5] \n connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[6] \n connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[7] \n connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[8] \n connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[9] \n connect slots_9.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[9].wakeup_ports[1].bits.uop.iq_type[0] \n connect slots_9.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[9].wakeup_ports[1].bits.uop.iq_type[1] \n connect slots_9.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[9].wakeup_ports[1].bits.uop.iq_type[2] \n connect slots_9.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[9].wakeup_ports[1].bits.uop.iq_type[3] \n connect slots_9.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[9].wakeup_ports[1].bits.uop.debug_pc \n connect slots_9.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[9].wakeup_ports[1].bits.uop.is_rvc \n connect slots_9.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[9].wakeup_ports[1].bits.uop.debug_inst \n connect slots_9.io.wakeup_ports[1].bits.uop.inst, issue_slots[9].wakeup_ports[1].bits.uop.inst \n connect slots_9.io.wakeup_ports[1].valid, issue_slots[9].wakeup_ports[1].valid \n connect slots_9.io.wakeup_ports[2].bits.rebusy, issue_slots[9].wakeup_ports[2].bits.rebusy \n connect slots_9.io.wakeup_ports[2].bits.speculative_mask, issue_slots[9].wakeup_ports[2].bits.speculative_mask \n connect slots_9.io.wakeup_ports[2].bits.bypassable, issue_slots[9].wakeup_ports[2].bits.bypassable \n connect slots_9.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[9].wakeup_ports[2].bits.uop.debug_tsrc \n connect slots_9.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[9].wakeup_ports[2].bits.uop.debug_fsrc \n connect slots_9.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[9].wakeup_ports[2].bits.uop.bp_xcpt_if \n connect slots_9.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[9].wakeup_ports[2].bits.uop.bp_debug_if \n connect slots_9.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[9].wakeup_ports[2].bits.uop.xcpt_ma_if \n connect slots_9.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[9].wakeup_ports[2].bits.uop.xcpt_ae_if \n connect slots_9.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[9].wakeup_ports[2].bits.uop.xcpt_pf_if \n connect slots_9.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[9].wakeup_ports[2].bits.uop.fp_typ \n connect slots_9.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[9].wakeup_ports[2].bits.uop.fp_rm \n connect slots_9.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[9].wakeup_ports[2].bits.uop.fp_val \n connect slots_9.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[9].wakeup_ports[2].bits.uop.fcn_op \n connect slots_9.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[9].wakeup_ports[2].bits.uop.fcn_dw \n connect slots_9.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[9].wakeup_ports[2].bits.uop.frs3_en \n connect slots_9.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[9].wakeup_ports[2].bits.uop.lrs2_rtype \n connect slots_9.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[9].wakeup_ports[2].bits.uop.lrs1_rtype \n connect slots_9.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[9].wakeup_ports[2].bits.uop.dst_rtype \n connect slots_9.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[9].wakeup_ports[2].bits.uop.lrs3 \n connect slots_9.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[9].wakeup_ports[2].bits.uop.lrs2 \n connect slots_9.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[9].wakeup_ports[2].bits.uop.lrs1 \n connect slots_9.io.wakeup_ports[2].bits.uop.ldst, issue_slots[9].wakeup_ports[2].bits.uop.ldst \n connect slots_9.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[9].wakeup_ports[2].bits.uop.ldst_is_rs1 \n connect slots_9.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[9].wakeup_ports[2].bits.uop.csr_cmd \n connect slots_9.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[9].wakeup_ports[2].bits.uop.flush_on_commit \n connect slots_9.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[9].wakeup_ports[2].bits.uop.is_unique \n connect slots_9.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[9].wakeup_ports[2].bits.uop.uses_stq \n connect slots_9.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[9].wakeup_ports[2].bits.uop.uses_ldq \n connect slots_9.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[9].wakeup_ports[2].bits.uop.mem_signed \n connect slots_9.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[9].wakeup_ports[2].bits.uop.mem_size \n connect slots_9.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[9].wakeup_ports[2].bits.uop.mem_cmd \n connect slots_9.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[9].wakeup_ports[2].bits.uop.exc_cause \n connect slots_9.io.wakeup_ports[2].bits.uop.exception, issue_slots[9].wakeup_ports[2].bits.uop.exception \n connect slots_9.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[9].wakeup_ports[2].bits.uop.stale_pdst \n connect slots_9.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[9].wakeup_ports[2].bits.uop.ppred_busy \n connect slots_9.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[9].wakeup_ports[2].bits.uop.prs3_busy \n connect slots_9.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[9].wakeup_ports[2].bits.uop.prs2_busy \n connect slots_9.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[9].wakeup_ports[2].bits.uop.prs1_busy \n connect slots_9.io.wakeup_ports[2].bits.uop.ppred, issue_slots[9].wakeup_ports[2].bits.uop.ppred \n connect slots_9.io.wakeup_ports[2].bits.uop.prs3, issue_slots[9].wakeup_ports[2].bits.uop.prs3 \n connect slots_9.io.wakeup_ports[2].bits.uop.prs2, issue_slots[9].wakeup_ports[2].bits.uop.prs2 \n connect slots_9.io.wakeup_ports[2].bits.uop.prs1, issue_slots[9].wakeup_ports[2].bits.uop.prs1 \n connect slots_9.io.wakeup_ports[2].bits.uop.pdst, issue_slots[9].wakeup_ports[2].bits.uop.pdst \n connect slots_9.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[9].wakeup_ports[2].bits.uop.rxq_idx \n connect slots_9.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[9].wakeup_ports[2].bits.uop.stq_idx \n connect slots_9.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[9].wakeup_ports[2].bits.uop.ldq_idx \n connect slots_9.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[9].wakeup_ports[2].bits.uop.rob_idx \n connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.vec \n connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.wflags \n connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.sqrt \n connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.div \n connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.fma \n connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe \n connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.toint \n connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.fromint \n connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut \n connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn \n connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.swap23 \n connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.swap12 \n connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.ren3 \n connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.ren2 \n connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.ren1 \n connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.wen \n connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.ldst \n connect slots_9.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[9].wakeup_ports[2].bits.uop.op2_sel \n connect slots_9.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[9].wakeup_ports[2].bits.uop.op1_sel \n connect slots_9.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[9].wakeup_ports[2].bits.uop.imm_packed \n connect slots_9.io.wakeup_ports[2].bits.uop.pimm, issue_slots[9].wakeup_ports[2].bits.uop.pimm \n connect slots_9.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[9].wakeup_ports[2].bits.uop.imm_sel \n connect slots_9.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[9].wakeup_ports[2].bits.uop.imm_rename \n connect slots_9.io.wakeup_ports[2].bits.uop.taken, issue_slots[9].wakeup_ports[2].bits.uop.taken \n connect slots_9.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[9].wakeup_ports[2].bits.uop.pc_lob \n connect slots_9.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[9].wakeup_ports[2].bits.uop.edge_inst \n connect slots_9.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[9].wakeup_ports[2].bits.uop.ftq_idx \n connect slots_9.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[9].wakeup_ports[2].bits.uop.is_mov \n connect slots_9.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[9].wakeup_ports[2].bits.uop.is_rocc \n connect slots_9.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[9].wakeup_ports[2].bits.uop.is_sys_pc2epc \n connect slots_9.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[9].wakeup_ports[2].bits.uop.is_eret \n connect slots_9.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[9].wakeup_ports[2].bits.uop.is_amo \n connect slots_9.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[9].wakeup_ports[2].bits.uop.is_sfence \n connect slots_9.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[9].wakeup_ports[2].bits.uop.is_fencei \n connect slots_9.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[9].wakeup_ports[2].bits.uop.is_fence \n connect slots_9.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[9].wakeup_ports[2].bits.uop.is_sfb \n connect slots_9.io.wakeup_ports[2].bits.uop.br_type, issue_slots[9].wakeup_ports[2].bits.uop.br_type \n connect slots_9.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[9].wakeup_ports[2].bits.uop.br_tag \n connect slots_9.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[9].wakeup_ports[2].bits.uop.br_mask \n connect slots_9.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[9].wakeup_ports[2].bits.uop.dis_col_sel \n connect slots_9.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[9].wakeup_ports[2].bits.uop.iw_p3_bypass_hint \n connect slots_9.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[9].wakeup_ports[2].bits.uop.iw_p2_bypass_hint \n connect slots_9.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[9].wakeup_ports[2].bits.uop.iw_p1_bypass_hint \n connect slots_9.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[9].wakeup_ports[2].bits.uop.iw_p2_speculative_child \n connect slots_9.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[9].wakeup_ports[2].bits.uop.iw_p1_speculative_child \n connect slots_9.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[9].wakeup_ports[2].bits.uop.iw_issued_partial_dgen \n connect slots_9.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[9].wakeup_ports[2].bits.uop.iw_issued_partial_agen \n connect slots_9.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[9].wakeup_ports[2].bits.uop.iw_issued \n connect slots_9.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[9].wakeup_ports[2].bits.uop.fu_code[0] \n connect slots_9.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[9].wakeup_ports[2].bits.uop.fu_code[1] \n connect slots_9.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[9].wakeup_ports[2].bits.uop.fu_code[2] \n connect slots_9.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[9].wakeup_ports[2].bits.uop.fu_code[3] \n connect slots_9.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[9].wakeup_ports[2].bits.uop.fu_code[4] \n connect slots_9.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[9].wakeup_ports[2].bits.uop.fu_code[5] \n connect slots_9.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[9].wakeup_ports[2].bits.uop.fu_code[6] \n connect slots_9.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[9].wakeup_ports[2].bits.uop.fu_code[7] \n connect slots_9.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[9].wakeup_ports[2].bits.uop.fu_code[8] \n connect slots_9.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[9].wakeup_ports[2].bits.uop.fu_code[9] \n connect slots_9.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[9].wakeup_ports[2].bits.uop.iq_type[0] \n connect slots_9.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[9].wakeup_ports[2].bits.uop.iq_type[1] \n connect slots_9.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[9].wakeup_ports[2].bits.uop.iq_type[2] \n connect slots_9.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[9].wakeup_ports[2].bits.uop.iq_type[3] \n connect slots_9.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[9].wakeup_ports[2].bits.uop.debug_pc \n connect slots_9.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[9].wakeup_ports[2].bits.uop.is_rvc \n connect slots_9.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[9].wakeup_ports[2].bits.uop.debug_inst \n connect slots_9.io.wakeup_ports[2].bits.uop.inst, issue_slots[9].wakeup_ports[2].bits.uop.inst \n connect slots_9.io.wakeup_ports[2].valid, issue_slots[9].wakeup_ports[2].valid \n connect slots_9.io.wakeup_ports[3].bits.rebusy, issue_slots[9].wakeup_ports[3].bits.rebusy \n connect slots_9.io.wakeup_ports[3].bits.speculative_mask, issue_slots[9].wakeup_ports[3].bits.speculative_mask \n connect slots_9.io.wakeup_ports[3].bits.bypassable, issue_slots[9].wakeup_ports[3].bits.bypassable \n connect slots_9.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[9].wakeup_ports[3].bits.uop.debug_tsrc \n connect slots_9.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[9].wakeup_ports[3].bits.uop.debug_fsrc \n connect slots_9.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[9].wakeup_ports[3].bits.uop.bp_xcpt_if \n connect slots_9.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[9].wakeup_ports[3].bits.uop.bp_debug_if \n connect slots_9.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[9].wakeup_ports[3].bits.uop.xcpt_ma_if \n connect slots_9.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[9].wakeup_ports[3].bits.uop.xcpt_ae_if \n connect slots_9.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[9].wakeup_ports[3].bits.uop.xcpt_pf_if \n connect slots_9.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[9].wakeup_ports[3].bits.uop.fp_typ \n connect slots_9.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[9].wakeup_ports[3].bits.uop.fp_rm \n connect slots_9.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[9].wakeup_ports[3].bits.uop.fp_val \n connect slots_9.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[9].wakeup_ports[3].bits.uop.fcn_op \n connect slots_9.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[9].wakeup_ports[3].bits.uop.fcn_dw \n connect slots_9.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[9].wakeup_ports[3].bits.uop.frs3_en \n connect slots_9.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[9].wakeup_ports[3].bits.uop.lrs2_rtype \n connect slots_9.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[9].wakeup_ports[3].bits.uop.lrs1_rtype \n connect slots_9.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[9].wakeup_ports[3].bits.uop.dst_rtype \n connect slots_9.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[9].wakeup_ports[3].bits.uop.lrs3 \n connect slots_9.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[9].wakeup_ports[3].bits.uop.lrs2 \n connect slots_9.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[9].wakeup_ports[3].bits.uop.lrs1 \n connect slots_9.io.wakeup_ports[3].bits.uop.ldst, issue_slots[9].wakeup_ports[3].bits.uop.ldst \n connect slots_9.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[9].wakeup_ports[3].bits.uop.ldst_is_rs1 \n connect slots_9.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[9].wakeup_ports[3].bits.uop.csr_cmd \n connect slots_9.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[9].wakeup_ports[3].bits.uop.flush_on_commit \n connect slots_9.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[9].wakeup_ports[3].bits.uop.is_unique \n connect slots_9.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[9].wakeup_ports[3].bits.uop.uses_stq \n connect slots_9.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[9].wakeup_ports[3].bits.uop.uses_ldq \n connect slots_9.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[9].wakeup_ports[3].bits.uop.mem_signed \n connect slots_9.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[9].wakeup_ports[3].bits.uop.mem_size \n connect slots_9.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[9].wakeup_ports[3].bits.uop.mem_cmd \n connect slots_9.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[9].wakeup_ports[3].bits.uop.exc_cause \n connect slots_9.io.wakeup_ports[3].bits.uop.exception, issue_slots[9].wakeup_ports[3].bits.uop.exception \n connect slots_9.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[9].wakeup_ports[3].bits.uop.stale_pdst \n connect slots_9.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[9].wakeup_ports[3].bits.uop.ppred_busy \n connect slots_9.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[9].wakeup_ports[3].bits.uop.prs3_busy \n connect slots_9.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[9].wakeup_ports[3].bits.uop.prs2_busy \n connect slots_9.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[9].wakeup_ports[3].bits.uop.prs1_busy \n connect slots_9.io.wakeup_ports[3].bits.uop.ppred, issue_slots[9].wakeup_ports[3].bits.uop.ppred \n connect slots_9.io.wakeup_ports[3].bits.uop.prs3, issue_slots[9].wakeup_ports[3].bits.uop.prs3 \n connect slots_9.io.wakeup_ports[3].bits.uop.prs2, issue_slots[9].wakeup_ports[3].bits.uop.prs2 \n connect slots_9.io.wakeup_ports[3].bits.uop.prs1, issue_slots[9].wakeup_ports[3].bits.uop.prs1 \n connect slots_9.io.wakeup_ports[3].bits.uop.pdst, issue_slots[9].wakeup_ports[3].bits.uop.pdst \n connect slots_9.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[9].wakeup_ports[3].bits.uop.rxq_idx \n connect slots_9.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[9].wakeup_ports[3].bits.uop.stq_idx \n connect slots_9.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[9].wakeup_ports[3].bits.uop.ldq_idx \n connect slots_9.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[9].wakeup_ports[3].bits.uop.rob_idx \n connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.vec \n connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.wflags \n connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.sqrt \n connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.div \n connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.fma \n connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe \n connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.toint \n connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.fromint \n connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut \n connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn \n connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.swap23 \n connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.swap12 \n connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.ren3 \n connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.ren2 \n connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.ren1 \n connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.wen \n connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.ldst \n connect slots_9.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[9].wakeup_ports[3].bits.uop.op2_sel \n connect slots_9.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[9].wakeup_ports[3].bits.uop.op1_sel \n connect slots_9.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[9].wakeup_ports[3].bits.uop.imm_packed \n connect slots_9.io.wakeup_ports[3].bits.uop.pimm, issue_slots[9].wakeup_ports[3].bits.uop.pimm \n connect slots_9.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[9].wakeup_ports[3].bits.uop.imm_sel \n connect slots_9.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[9].wakeup_ports[3].bits.uop.imm_rename \n connect slots_9.io.wakeup_ports[3].bits.uop.taken, issue_slots[9].wakeup_ports[3].bits.uop.taken \n connect slots_9.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[9].wakeup_ports[3].bits.uop.pc_lob \n connect slots_9.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[9].wakeup_ports[3].bits.uop.edge_inst \n connect slots_9.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[9].wakeup_ports[3].bits.uop.ftq_idx \n connect slots_9.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[9].wakeup_ports[3].bits.uop.is_mov \n connect slots_9.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[9].wakeup_ports[3].bits.uop.is_rocc \n connect slots_9.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[9].wakeup_ports[3].bits.uop.is_sys_pc2epc \n connect slots_9.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[9].wakeup_ports[3].bits.uop.is_eret \n connect slots_9.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[9].wakeup_ports[3].bits.uop.is_amo \n connect slots_9.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[9].wakeup_ports[3].bits.uop.is_sfence \n connect slots_9.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[9].wakeup_ports[3].bits.uop.is_fencei \n connect slots_9.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[9].wakeup_ports[3].bits.uop.is_fence \n connect slots_9.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[9].wakeup_ports[3].bits.uop.is_sfb \n connect slots_9.io.wakeup_ports[3].bits.uop.br_type, issue_slots[9].wakeup_ports[3].bits.uop.br_type \n connect slots_9.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[9].wakeup_ports[3].bits.uop.br_tag \n connect slots_9.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[9].wakeup_ports[3].bits.uop.br_mask \n connect slots_9.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[9].wakeup_ports[3].bits.uop.dis_col_sel \n connect slots_9.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[9].wakeup_ports[3].bits.uop.iw_p3_bypass_hint \n connect slots_9.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[9].wakeup_ports[3].bits.uop.iw_p2_bypass_hint \n connect slots_9.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[9].wakeup_ports[3].bits.uop.iw_p1_bypass_hint \n connect slots_9.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[9].wakeup_ports[3].bits.uop.iw_p2_speculative_child \n connect slots_9.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[9].wakeup_ports[3].bits.uop.iw_p1_speculative_child \n connect slots_9.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[9].wakeup_ports[3].bits.uop.iw_issued_partial_dgen \n connect slots_9.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[9].wakeup_ports[3].bits.uop.iw_issued_partial_agen \n connect slots_9.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[9].wakeup_ports[3].bits.uop.iw_issued \n connect slots_9.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[9].wakeup_ports[3].bits.uop.fu_code[0] \n connect slots_9.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[9].wakeup_ports[3].bits.uop.fu_code[1] \n connect slots_9.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[9].wakeup_ports[3].bits.uop.fu_code[2] \n connect slots_9.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[9].wakeup_ports[3].bits.uop.fu_code[3] \n connect slots_9.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[9].wakeup_ports[3].bits.uop.fu_code[4] \n connect slots_9.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[9].wakeup_ports[3].bits.uop.fu_code[5] \n connect slots_9.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[9].wakeup_ports[3].bits.uop.fu_code[6] \n connect slots_9.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[9].wakeup_ports[3].bits.uop.fu_code[7] \n connect slots_9.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[9].wakeup_ports[3].bits.uop.fu_code[8] \n connect slots_9.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[9].wakeup_ports[3].bits.uop.fu_code[9] \n connect slots_9.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[9].wakeup_ports[3].bits.uop.iq_type[0] \n connect slots_9.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[9].wakeup_ports[3].bits.uop.iq_type[1] \n connect slots_9.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[9].wakeup_ports[3].bits.uop.iq_type[2] \n connect slots_9.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[9].wakeup_ports[3].bits.uop.iq_type[3] \n connect slots_9.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[9].wakeup_ports[3].bits.uop.debug_pc \n connect slots_9.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[9].wakeup_ports[3].bits.uop.is_rvc \n connect slots_9.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[9].wakeup_ports[3].bits.uop.debug_inst \n connect slots_9.io.wakeup_ports[3].bits.uop.inst, issue_slots[9].wakeup_ports[3].bits.uop.inst \n connect slots_9.io.wakeup_ports[3].valid, issue_slots[9].wakeup_ports[3].valid \n connect slots_9.io.squash_grant, issue_slots[9].squash_grant \n connect slots_9.io.clear, issue_slots[9].clear \n connect slots_9.io.kill, issue_slots[9].kill \n connect slots_9.io.brupdate.b2.target_offset, issue_slots[9].brupdate.b2.target_offset \n connect slots_9.io.brupdate.b2.jalr_target, issue_slots[9].brupdate.b2.jalr_target \n connect slots_9.io.brupdate.b2.pc_sel, issue_slots[9].brupdate.b2.pc_sel \n connect slots_9.io.brupdate.b2.cfi_type, issue_slots[9].brupdate.b2.cfi_type \n connect slots_9.io.brupdate.b2.taken, issue_slots[9].brupdate.b2.taken \n connect slots_9.io.brupdate.b2.mispredict, issue_slots[9].brupdate.b2.mispredict \n connect slots_9.io.brupdate.b2.uop.debug_tsrc, issue_slots[9].brupdate.b2.uop.debug_tsrc \n connect slots_9.io.brupdate.b2.uop.debug_fsrc, issue_slots[9].brupdate.b2.uop.debug_fsrc \n connect slots_9.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[9].brupdate.b2.uop.bp_xcpt_if \n connect slots_9.io.brupdate.b2.uop.bp_debug_if, issue_slots[9].brupdate.b2.uop.bp_debug_if \n connect slots_9.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[9].brupdate.b2.uop.xcpt_ma_if \n connect slots_9.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[9].brupdate.b2.uop.xcpt_ae_if \n connect slots_9.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[9].brupdate.b2.uop.xcpt_pf_if \n connect slots_9.io.brupdate.b2.uop.fp_typ, issue_slots[9].brupdate.b2.uop.fp_typ \n connect slots_9.io.brupdate.b2.uop.fp_rm, issue_slots[9].brupdate.b2.uop.fp_rm \n connect slots_9.io.brupdate.b2.uop.fp_val, issue_slots[9].brupdate.b2.uop.fp_val \n connect slots_9.io.brupdate.b2.uop.fcn_op, issue_slots[9].brupdate.b2.uop.fcn_op \n connect slots_9.io.brupdate.b2.uop.fcn_dw, issue_slots[9].brupdate.b2.uop.fcn_dw \n connect slots_9.io.brupdate.b2.uop.frs3_en, issue_slots[9].brupdate.b2.uop.frs3_en \n connect slots_9.io.brupdate.b2.uop.lrs2_rtype, issue_slots[9].brupdate.b2.uop.lrs2_rtype \n connect slots_9.io.brupdate.b2.uop.lrs1_rtype, issue_slots[9].brupdate.b2.uop.lrs1_rtype \n connect slots_9.io.brupdate.b2.uop.dst_rtype, issue_slots[9].brupdate.b2.uop.dst_rtype \n connect slots_9.io.brupdate.b2.uop.lrs3, issue_slots[9].brupdate.b2.uop.lrs3 \n connect slots_9.io.brupdate.b2.uop.lrs2, issue_slots[9].brupdate.b2.uop.lrs2 \n connect slots_9.io.brupdate.b2.uop.lrs1, issue_slots[9].brupdate.b2.uop.lrs1 \n connect slots_9.io.brupdate.b2.uop.ldst, issue_slots[9].brupdate.b2.uop.ldst \n connect slots_9.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[9].brupdate.b2.uop.ldst_is_rs1 \n connect slots_9.io.brupdate.b2.uop.csr_cmd, issue_slots[9].brupdate.b2.uop.csr_cmd \n connect slots_9.io.brupdate.b2.uop.flush_on_commit, issue_slots[9].brupdate.b2.uop.flush_on_commit \n connect slots_9.io.brupdate.b2.uop.is_unique, issue_slots[9].brupdate.b2.uop.is_unique \n connect slots_9.io.brupdate.b2.uop.uses_stq, issue_slots[9].brupdate.b2.uop.uses_stq \n connect slots_9.io.brupdate.b2.uop.uses_ldq, issue_slots[9].brupdate.b2.uop.uses_ldq \n connect slots_9.io.brupdate.b2.uop.mem_signed, issue_slots[9].brupdate.b2.uop.mem_signed \n connect slots_9.io.brupdate.b2.uop.mem_size, issue_slots[9].brupdate.b2.uop.mem_size \n connect slots_9.io.brupdate.b2.uop.mem_cmd, issue_slots[9].brupdate.b2.uop.mem_cmd \n connect slots_9.io.brupdate.b2.uop.exc_cause, issue_slots[9].brupdate.b2.uop.exc_cause \n connect slots_9.io.brupdate.b2.uop.exception, issue_slots[9].brupdate.b2.uop.exception \n connect slots_9.io.brupdate.b2.uop.stale_pdst, issue_slots[9].brupdate.b2.uop.stale_pdst \n connect slots_9.io.brupdate.b2.uop.ppred_busy, issue_slots[9].brupdate.b2.uop.ppred_busy \n connect slots_9.io.brupdate.b2.uop.prs3_busy, issue_slots[9].brupdate.b2.uop.prs3_busy \n connect slots_9.io.brupdate.b2.uop.prs2_busy, issue_slots[9].brupdate.b2.uop.prs2_busy \n connect slots_9.io.brupdate.b2.uop.prs1_busy, issue_slots[9].brupdate.b2.uop.prs1_busy \n connect slots_9.io.brupdate.b2.uop.ppred, issue_slots[9].brupdate.b2.uop.ppred \n connect slots_9.io.brupdate.b2.uop.prs3, issue_slots[9].brupdate.b2.uop.prs3 \n connect slots_9.io.brupdate.b2.uop.prs2, issue_slots[9].brupdate.b2.uop.prs2 \n connect slots_9.io.brupdate.b2.uop.prs1, issue_slots[9].brupdate.b2.uop.prs1 \n connect slots_9.io.brupdate.b2.uop.pdst, issue_slots[9].brupdate.b2.uop.pdst \n connect slots_9.io.brupdate.b2.uop.rxq_idx, issue_slots[9].brupdate.b2.uop.rxq_idx \n connect slots_9.io.brupdate.b2.uop.stq_idx, issue_slots[9].brupdate.b2.uop.stq_idx \n connect slots_9.io.brupdate.b2.uop.ldq_idx, issue_slots[9].brupdate.b2.uop.ldq_idx \n connect slots_9.io.brupdate.b2.uop.rob_idx, issue_slots[9].brupdate.b2.uop.rob_idx \n connect slots_9.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[9].brupdate.b2.uop.fp_ctrl.vec \n connect slots_9.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[9].brupdate.b2.uop.fp_ctrl.wflags \n connect slots_9.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[9].brupdate.b2.uop.fp_ctrl.sqrt \n connect slots_9.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[9].brupdate.b2.uop.fp_ctrl.div \n connect slots_9.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[9].brupdate.b2.uop.fp_ctrl.fma \n connect slots_9.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[9].brupdate.b2.uop.fp_ctrl.fastpipe \n connect slots_9.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[9].brupdate.b2.uop.fp_ctrl.toint \n connect slots_9.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[9].brupdate.b2.uop.fp_ctrl.fromint \n connect slots_9.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[9].brupdate.b2.uop.fp_ctrl.typeTagOut \n connect slots_9.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[9].brupdate.b2.uop.fp_ctrl.typeTagIn \n connect slots_9.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[9].brupdate.b2.uop.fp_ctrl.swap23 \n connect slots_9.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[9].brupdate.b2.uop.fp_ctrl.swap12 \n connect slots_9.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[9].brupdate.b2.uop.fp_ctrl.ren3 \n connect slots_9.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[9].brupdate.b2.uop.fp_ctrl.ren2 \n connect slots_9.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[9].brupdate.b2.uop.fp_ctrl.ren1 \n connect slots_9.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[9].brupdate.b2.uop.fp_ctrl.wen \n connect slots_9.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[9].brupdate.b2.uop.fp_ctrl.ldst \n connect slots_9.io.brupdate.b2.uop.op2_sel, issue_slots[9].brupdate.b2.uop.op2_sel \n connect slots_9.io.brupdate.b2.uop.op1_sel, issue_slots[9].brupdate.b2.uop.op1_sel \n connect slots_9.io.brupdate.b2.uop.imm_packed, issue_slots[9].brupdate.b2.uop.imm_packed \n connect slots_9.io.brupdate.b2.uop.pimm, issue_slots[9].brupdate.b2.uop.pimm \n connect slots_9.io.brupdate.b2.uop.imm_sel, issue_slots[9].brupdate.b2.uop.imm_sel \n connect slots_9.io.brupdate.b2.uop.imm_rename, issue_slots[9].brupdate.b2.uop.imm_rename \n connect slots_9.io.brupdate.b2.uop.taken, issue_slots[9].brupdate.b2.uop.taken \n connect slots_9.io.brupdate.b2.uop.pc_lob, issue_slots[9].brupdate.b2.uop.pc_lob \n connect slots_9.io.brupdate.b2.uop.edge_inst, issue_slots[9].brupdate.b2.uop.edge_inst \n connect slots_9.io.brupdate.b2.uop.ftq_idx, issue_slots[9].brupdate.b2.uop.ftq_idx \n connect slots_9.io.brupdate.b2.uop.is_mov, issue_slots[9].brupdate.b2.uop.is_mov \n connect slots_9.io.brupdate.b2.uop.is_rocc, issue_slots[9].brupdate.b2.uop.is_rocc \n connect slots_9.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[9].brupdate.b2.uop.is_sys_pc2epc \n connect slots_9.io.brupdate.b2.uop.is_eret, issue_slots[9].brupdate.b2.uop.is_eret \n connect slots_9.io.brupdate.b2.uop.is_amo, issue_slots[9].brupdate.b2.uop.is_amo \n connect slots_9.io.brupdate.b2.uop.is_sfence, issue_slots[9].brupdate.b2.uop.is_sfence \n connect slots_9.io.brupdate.b2.uop.is_fencei, issue_slots[9].brupdate.b2.uop.is_fencei \n connect slots_9.io.brupdate.b2.uop.is_fence, issue_slots[9].brupdate.b2.uop.is_fence \n connect slots_9.io.brupdate.b2.uop.is_sfb, issue_slots[9].brupdate.b2.uop.is_sfb \n connect slots_9.io.brupdate.b2.uop.br_type, issue_slots[9].brupdate.b2.uop.br_type \n connect slots_9.io.brupdate.b2.uop.br_tag, issue_slots[9].brupdate.b2.uop.br_tag \n connect slots_9.io.brupdate.b2.uop.br_mask, issue_slots[9].brupdate.b2.uop.br_mask \n connect slots_9.io.brupdate.b2.uop.dis_col_sel, issue_slots[9].brupdate.b2.uop.dis_col_sel \n connect slots_9.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[9].brupdate.b2.uop.iw_p3_bypass_hint \n connect slots_9.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[9].brupdate.b2.uop.iw_p2_bypass_hint \n connect slots_9.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[9].brupdate.b2.uop.iw_p1_bypass_hint \n connect slots_9.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[9].brupdate.b2.uop.iw_p2_speculative_child \n connect slots_9.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[9].brupdate.b2.uop.iw_p1_speculative_child \n connect slots_9.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[9].brupdate.b2.uop.iw_issued_partial_dgen \n connect slots_9.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[9].brupdate.b2.uop.iw_issued_partial_agen \n connect slots_9.io.brupdate.b2.uop.iw_issued, issue_slots[9].brupdate.b2.uop.iw_issued \n connect slots_9.io.brupdate.b2.uop.fu_code[0], issue_slots[9].brupdate.b2.uop.fu_code[0] \n connect slots_9.io.brupdate.b2.uop.fu_code[1], issue_slots[9].brupdate.b2.uop.fu_code[1] \n connect slots_9.io.brupdate.b2.uop.fu_code[2], issue_slots[9].brupdate.b2.uop.fu_code[2] \n connect slots_9.io.brupdate.b2.uop.fu_code[3], issue_slots[9].brupdate.b2.uop.fu_code[3] \n connect slots_9.io.brupdate.b2.uop.fu_code[4], issue_slots[9].brupdate.b2.uop.fu_code[4] \n connect slots_9.io.brupdate.b2.uop.fu_code[5], issue_slots[9].brupdate.b2.uop.fu_code[5] \n connect slots_9.io.brupdate.b2.uop.fu_code[6], issue_slots[9].brupdate.b2.uop.fu_code[6] \n connect slots_9.io.brupdate.b2.uop.fu_code[7], issue_slots[9].brupdate.b2.uop.fu_code[7] \n connect slots_9.io.brupdate.b2.uop.fu_code[8], issue_slots[9].brupdate.b2.uop.fu_code[8] \n connect slots_9.io.brupdate.b2.uop.fu_code[9], issue_slots[9].brupdate.b2.uop.fu_code[9] \n connect slots_9.io.brupdate.b2.uop.iq_type[0], issue_slots[9].brupdate.b2.uop.iq_type[0] \n connect slots_9.io.brupdate.b2.uop.iq_type[1], issue_slots[9].brupdate.b2.uop.iq_type[1] \n connect slots_9.io.brupdate.b2.uop.iq_type[2], issue_slots[9].brupdate.b2.uop.iq_type[2] \n connect slots_9.io.brupdate.b2.uop.iq_type[3], issue_slots[9].brupdate.b2.uop.iq_type[3] \n connect slots_9.io.brupdate.b2.uop.debug_pc, issue_slots[9].brupdate.b2.uop.debug_pc \n connect slots_9.io.brupdate.b2.uop.is_rvc, issue_slots[9].brupdate.b2.uop.is_rvc \n connect slots_9.io.brupdate.b2.uop.debug_inst, issue_slots[9].brupdate.b2.uop.debug_inst \n connect slots_9.io.brupdate.b2.uop.inst, issue_slots[9].brupdate.b2.uop.inst \n connect slots_9.io.brupdate.b1.mispredict_mask, issue_slots[9].brupdate.b1.mispredict_mask \n connect slots_9.io.brupdate.b1.resolve_mask, issue_slots[9].brupdate.b1.resolve_mask \n connect issue_slots[9].out_uop.debug_tsrc, slots_9.io.out_uop.debug_tsrc \n connect issue_slots[9].out_uop.debug_fsrc, slots_9.io.out_uop.debug_fsrc \n connect issue_slots[9].out_uop.bp_xcpt_if, slots_9.io.out_uop.bp_xcpt_if \n connect issue_slots[9].out_uop.bp_debug_if, slots_9.io.out_uop.bp_debug_if \n connect issue_slots[9].out_uop.xcpt_ma_if, slots_9.io.out_uop.xcpt_ma_if \n connect issue_slots[9].out_uop.xcpt_ae_if, slots_9.io.out_uop.xcpt_ae_if \n connect issue_slots[9].out_uop.xcpt_pf_if, slots_9.io.out_uop.xcpt_pf_if \n connect issue_slots[9].out_uop.fp_typ, slots_9.io.out_uop.fp_typ \n connect issue_slots[9].out_uop.fp_rm, slots_9.io.out_uop.fp_rm \n connect issue_slots[9].out_uop.fp_val, slots_9.io.out_uop.fp_val \n connect issue_slots[9].out_uop.fcn_op, slots_9.io.out_uop.fcn_op \n connect issue_slots[9].out_uop.fcn_dw, slots_9.io.out_uop.fcn_dw \n connect issue_slots[9].out_uop.frs3_en, slots_9.io.out_uop.frs3_en \n connect issue_slots[9].out_uop.lrs2_rtype, slots_9.io.out_uop.lrs2_rtype \n connect issue_slots[9].out_uop.lrs1_rtype, slots_9.io.out_uop.lrs1_rtype \n connect issue_slots[9].out_uop.dst_rtype, slots_9.io.out_uop.dst_rtype \n connect issue_slots[9].out_uop.lrs3, slots_9.io.out_uop.lrs3 \n connect issue_slots[9].out_uop.lrs2, slots_9.io.out_uop.lrs2 \n connect issue_slots[9].out_uop.lrs1, slots_9.io.out_uop.lrs1 \n connect issue_slots[9].out_uop.ldst, slots_9.io.out_uop.ldst \n connect issue_slots[9].out_uop.ldst_is_rs1, slots_9.io.out_uop.ldst_is_rs1 \n connect issue_slots[9].out_uop.csr_cmd, slots_9.io.out_uop.csr_cmd \n connect issue_slots[9].out_uop.flush_on_commit, slots_9.io.out_uop.flush_on_commit \n connect issue_slots[9].out_uop.is_unique, slots_9.io.out_uop.is_unique \n connect issue_slots[9].out_uop.uses_stq, slots_9.io.out_uop.uses_stq \n connect issue_slots[9].out_uop.uses_ldq, slots_9.io.out_uop.uses_ldq \n connect issue_slots[9].out_uop.mem_signed, slots_9.io.out_uop.mem_signed \n connect issue_slots[9].out_uop.mem_size, slots_9.io.out_uop.mem_size \n connect issue_slots[9].out_uop.mem_cmd, slots_9.io.out_uop.mem_cmd \n connect issue_slots[9].out_uop.exc_cause, slots_9.io.out_uop.exc_cause \n connect issue_slots[9].out_uop.exception, slots_9.io.out_uop.exception \n connect issue_slots[9].out_uop.stale_pdst, slots_9.io.out_uop.stale_pdst \n connect issue_slots[9].out_uop.ppred_busy, slots_9.io.out_uop.ppred_busy \n connect issue_slots[9].out_uop.prs3_busy, slots_9.io.out_uop.prs3_busy \n connect issue_slots[9].out_uop.prs2_busy, slots_9.io.out_uop.prs2_busy \n connect issue_slots[9].out_uop.prs1_busy, slots_9.io.out_uop.prs1_busy \n connect issue_slots[9].out_uop.ppred, slots_9.io.out_uop.ppred \n connect issue_slots[9].out_uop.prs3, slots_9.io.out_uop.prs3 \n connect issue_slots[9].out_uop.prs2, slots_9.io.out_uop.prs2 \n connect issue_slots[9].out_uop.prs1, slots_9.io.out_uop.prs1 \n connect issue_slots[9].out_uop.pdst, slots_9.io.out_uop.pdst \n connect issue_slots[9].out_uop.rxq_idx, slots_9.io.out_uop.rxq_idx \n connect issue_slots[9].out_uop.stq_idx, slots_9.io.out_uop.stq_idx \n connect issue_slots[9].out_uop.ldq_idx, slots_9.io.out_uop.ldq_idx \n connect issue_slots[9].out_uop.rob_idx, slots_9.io.out_uop.rob_idx \n connect issue_slots[9].out_uop.fp_ctrl.vec, slots_9.io.out_uop.fp_ctrl.vec \n connect issue_slots[9].out_uop.fp_ctrl.wflags, slots_9.io.out_uop.fp_ctrl.wflags \n connect issue_slots[9].out_uop.fp_ctrl.sqrt, slots_9.io.out_uop.fp_ctrl.sqrt \n connect issue_slots[9].out_uop.fp_ctrl.div, slots_9.io.out_uop.fp_ctrl.div \n connect issue_slots[9].out_uop.fp_ctrl.fma, slots_9.io.out_uop.fp_ctrl.fma \n connect issue_slots[9].out_uop.fp_ctrl.fastpipe, slots_9.io.out_uop.fp_ctrl.fastpipe \n connect issue_slots[9].out_uop.fp_ctrl.toint, slots_9.io.out_uop.fp_ctrl.toint \n connect issue_slots[9].out_uop.fp_ctrl.fromint, slots_9.io.out_uop.fp_ctrl.fromint \n connect issue_slots[9].out_uop.fp_ctrl.typeTagOut, slots_9.io.out_uop.fp_ctrl.typeTagOut \n connect issue_slots[9].out_uop.fp_ctrl.typeTagIn, slots_9.io.out_uop.fp_ctrl.typeTagIn \n connect issue_slots[9].out_uop.fp_ctrl.swap23, slots_9.io.out_uop.fp_ctrl.swap23 \n connect issue_slots[9].out_uop.fp_ctrl.swap12, slots_9.io.out_uop.fp_ctrl.swap12 \n connect issue_slots[9].out_uop.fp_ctrl.ren3, slots_9.io.out_uop.fp_ctrl.ren3 \n connect issue_slots[9].out_uop.fp_ctrl.ren2, slots_9.io.out_uop.fp_ctrl.ren2 \n connect issue_slots[9].out_uop.fp_ctrl.ren1, slots_9.io.out_uop.fp_ctrl.ren1 \n connect issue_slots[9].out_uop.fp_ctrl.wen, slots_9.io.out_uop.fp_ctrl.wen \n connect issue_slots[9].out_uop.fp_ctrl.ldst, slots_9.io.out_uop.fp_ctrl.ldst \n connect issue_slots[9].out_uop.op2_sel, slots_9.io.out_uop.op2_sel \n connect issue_slots[9].out_uop.op1_sel, slots_9.io.out_uop.op1_sel \n connect issue_slots[9].out_uop.imm_packed, slots_9.io.out_uop.imm_packed \n connect issue_slots[9].out_uop.pimm, slots_9.io.out_uop.pimm \n connect issue_slots[9].out_uop.imm_sel, slots_9.io.out_uop.imm_sel \n connect issue_slots[9].out_uop.imm_rename, slots_9.io.out_uop.imm_rename \n connect issue_slots[9].out_uop.taken, slots_9.io.out_uop.taken \n connect issue_slots[9].out_uop.pc_lob, slots_9.io.out_uop.pc_lob \n connect issue_slots[9].out_uop.edge_inst, slots_9.io.out_uop.edge_inst \n connect issue_slots[9].out_uop.ftq_idx, slots_9.io.out_uop.ftq_idx \n connect issue_slots[9].out_uop.is_mov, slots_9.io.out_uop.is_mov \n connect issue_slots[9].out_uop.is_rocc, slots_9.io.out_uop.is_rocc \n connect issue_slots[9].out_uop.is_sys_pc2epc, slots_9.io.out_uop.is_sys_pc2epc \n connect issue_slots[9].out_uop.is_eret, slots_9.io.out_uop.is_eret \n connect issue_slots[9].out_uop.is_amo, slots_9.io.out_uop.is_amo \n connect issue_slots[9].out_uop.is_sfence, slots_9.io.out_uop.is_sfence \n connect issue_slots[9].out_uop.is_fencei, slots_9.io.out_uop.is_fencei \n connect issue_slots[9].out_uop.is_fence, slots_9.io.out_uop.is_fence \n connect issue_slots[9].out_uop.is_sfb, slots_9.io.out_uop.is_sfb \n connect issue_slots[9].out_uop.br_type, slots_9.io.out_uop.br_type \n connect issue_slots[9].out_uop.br_tag, slots_9.io.out_uop.br_tag \n connect issue_slots[9].out_uop.br_mask, slots_9.io.out_uop.br_mask \n connect issue_slots[9].out_uop.dis_col_sel, slots_9.io.out_uop.dis_col_sel \n connect issue_slots[9].out_uop.iw_p3_bypass_hint, slots_9.io.out_uop.iw_p3_bypass_hint \n connect issue_slots[9].out_uop.iw_p2_bypass_hint, slots_9.io.out_uop.iw_p2_bypass_hint \n connect issue_slots[9].out_uop.iw_p1_bypass_hint, slots_9.io.out_uop.iw_p1_bypass_hint \n connect issue_slots[9].out_uop.iw_p2_speculative_child, slots_9.io.out_uop.iw_p2_speculative_child \n connect issue_slots[9].out_uop.iw_p1_speculative_child, slots_9.io.out_uop.iw_p1_speculative_child \n connect issue_slots[9].out_uop.iw_issued_partial_dgen, slots_9.io.out_uop.iw_issued_partial_dgen \n connect issue_slots[9].out_uop.iw_issued_partial_agen, slots_9.io.out_uop.iw_issued_partial_agen \n connect issue_slots[9].out_uop.iw_issued, slots_9.io.out_uop.iw_issued \n connect issue_slots[9].out_uop.fu_code[0], slots_9.io.out_uop.fu_code[0] \n connect issue_slots[9].out_uop.fu_code[1], slots_9.io.out_uop.fu_code[1] \n connect issue_slots[9].out_uop.fu_code[2], slots_9.io.out_uop.fu_code[2] \n connect issue_slots[9].out_uop.fu_code[3], slots_9.io.out_uop.fu_code[3] \n connect issue_slots[9].out_uop.fu_code[4], slots_9.io.out_uop.fu_code[4] \n connect issue_slots[9].out_uop.fu_code[5], slots_9.io.out_uop.fu_code[5] \n connect issue_slots[9].out_uop.fu_code[6], slots_9.io.out_uop.fu_code[6] \n connect issue_slots[9].out_uop.fu_code[7], slots_9.io.out_uop.fu_code[7] \n connect issue_slots[9].out_uop.fu_code[8], slots_9.io.out_uop.fu_code[8] \n connect issue_slots[9].out_uop.fu_code[9], slots_9.io.out_uop.fu_code[9] \n connect issue_slots[9].out_uop.iq_type[0], slots_9.io.out_uop.iq_type[0] \n connect issue_slots[9].out_uop.iq_type[1], slots_9.io.out_uop.iq_type[1] \n connect issue_slots[9].out_uop.iq_type[2], slots_9.io.out_uop.iq_type[2] \n connect issue_slots[9].out_uop.iq_type[3], slots_9.io.out_uop.iq_type[3] \n connect issue_slots[9].out_uop.debug_pc, slots_9.io.out_uop.debug_pc \n connect issue_slots[9].out_uop.is_rvc, slots_9.io.out_uop.is_rvc \n connect issue_slots[9].out_uop.debug_inst, slots_9.io.out_uop.debug_inst \n connect issue_slots[9].out_uop.inst, slots_9.io.out_uop.inst \n connect slots_9.io.in_uop.bits.debug_tsrc, issue_slots[9].in_uop.bits.debug_tsrc \n connect slots_9.io.in_uop.bits.debug_fsrc, issue_slots[9].in_uop.bits.debug_fsrc \n connect slots_9.io.in_uop.bits.bp_xcpt_if, issue_slots[9].in_uop.bits.bp_xcpt_if \n connect slots_9.io.in_uop.bits.bp_debug_if, issue_slots[9].in_uop.bits.bp_debug_if \n connect slots_9.io.in_uop.bits.xcpt_ma_if, issue_slots[9].in_uop.bits.xcpt_ma_if \n connect slots_9.io.in_uop.bits.xcpt_ae_if, issue_slots[9].in_uop.bits.xcpt_ae_if \n connect slots_9.io.in_uop.bits.xcpt_pf_if, issue_slots[9].in_uop.bits.xcpt_pf_if \n connect slots_9.io.in_uop.bits.fp_typ, issue_slots[9].in_uop.bits.fp_typ \n connect slots_9.io.in_uop.bits.fp_rm, issue_slots[9].in_uop.bits.fp_rm \n connect slots_9.io.in_uop.bits.fp_val, issue_slots[9].in_uop.bits.fp_val \n connect slots_9.io.in_uop.bits.fcn_op, issue_slots[9].in_uop.bits.fcn_op \n connect slots_9.io.in_uop.bits.fcn_dw, issue_slots[9].in_uop.bits.fcn_dw \n connect slots_9.io.in_uop.bits.frs3_en, issue_slots[9].in_uop.bits.frs3_en \n connect slots_9.io.in_uop.bits.lrs2_rtype, issue_slots[9].in_uop.bits.lrs2_rtype \n connect slots_9.io.in_uop.bits.lrs1_rtype, issue_slots[9].in_uop.bits.lrs1_rtype \n connect slots_9.io.in_uop.bits.dst_rtype, issue_slots[9].in_uop.bits.dst_rtype \n connect slots_9.io.in_uop.bits.lrs3, issue_slots[9].in_uop.bits.lrs3 \n connect slots_9.io.in_uop.bits.lrs2, issue_slots[9].in_uop.bits.lrs2 \n connect slots_9.io.in_uop.bits.lrs1, issue_slots[9].in_uop.bits.lrs1 \n connect slots_9.io.in_uop.bits.ldst, issue_slots[9].in_uop.bits.ldst \n connect slots_9.io.in_uop.bits.ldst_is_rs1, issue_slots[9].in_uop.bits.ldst_is_rs1 \n connect slots_9.io.in_uop.bits.csr_cmd, issue_slots[9].in_uop.bits.csr_cmd \n connect slots_9.io.in_uop.bits.flush_on_commit, issue_slots[9].in_uop.bits.flush_on_commit \n connect slots_9.io.in_uop.bits.is_unique, issue_slots[9].in_uop.bits.is_unique \n connect slots_9.io.in_uop.bits.uses_stq, issue_slots[9].in_uop.bits.uses_stq \n connect slots_9.io.in_uop.bits.uses_ldq, issue_slots[9].in_uop.bits.uses_ldq \n connect slots_9.io.in_uop.bits.mem_signed, issue_slots[9].in_uop.bits.mem_signed \n connect slots_9.io.in_uop.bits.mem_size, issue_slots[9].in_uop.bits.mem_size \n connect slots_9.io.in_uop.bits.mem_cmd, issue_slots[9].in_uop.bits.mem_cmd \n connect slots_9.io.in_uop.bits.exc_cause, issue_slots[9].in_uop.bits.exc_cause \n connect slots_9.io.in_uop.bits.exception, issue_slots[9].in_uop.bits.exception \n connect slots_9.io.in_uop.bits.stale_pdst, issue_slots[9].in_uop.bits.stale_pdst \n connect slots_9.io.in_uop.bits.ppred_busy, issue_slots[9].in_uop.bits.ppred_busy \n connect slots_9.io.in_uop.bits.prs3_busy, issue_slots[9].in_uop.bits.prs3_busy \n connect slots_9.io.in_uop.bits.prs2_busy, issue_slots[9].in_uop.bits.prs2_busy \n connect slots_9.io.in_uop.bits.prs1_busy, issue_slots[9].in_uop.bits.prs1_busy \n connect slots_9.io.in_uop.bits.ppred, issue_slots[9].in_uop.bits.ppred \n connect slots_9.io.in_uop.bits.prs3, issue_slots[9].in_uop.bits.prs3 \n connect slots_9.io.in_uop.bits.prs2, issue_slots[9].in_uop.bits.prs2 \n connect slots_9.io.in_uop.bits.prs1, issue_slots[9].in_uop.bits.prs1 \n connect slots_9.io.in_uop.bits.pdst, issue_slots[9].in_uop.bits.pdst \n connect slots_9.io.in_uop.bits.rxq_idx, issue_slots[9].in_uop.bits.rxq_idx \n connect slots_9.io.in_uop.bits.stq_idx, issue_slots[9].in_uop.bits.stq_idx \n connect slots_9.io.in_uop.bits.ldq_idx, issue_slots[9].in_uop.bits.ldq_idx \n connect slots_9.io.in_uop.bits.rob_idx, issue_slots[9].in_uop.bits.rob_idx \n connect slots_9.io.in_uop.bits.fp_ctrl.vec, issue_slots[9].in_uop.bits.fp_ctrl.vec \n connect slots_9.io.in_uop.bits.fp_ctrl.wflags, issue_slots[9].in_uop.bits.fp_ctrl.wflags \n connect slots_9.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[9].in_uop.bits.fp_ctrl.sqrt \n connect slots_9.io.in_uop.bits.fp_ctrl.div, issue_slots[9].in_uop.bits.fp_ctrl.div \n connect slots_9.io.in_uop.bits.fp_ctrl.fma, issue_slots[9].in_uop.bits.fp_ctrl.fma \n connect slots_9.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[9].in_uop.bits.fp_ctrl.fastpipe \n connect slots_9.io.in_uop.bits.fp_ctrl.toint, issue_slots[9].in_uop.bits.fp_ctrl.toint \n connect slots_9.io.in_uop.bits.fp_ctrl.fromint, issue_slots[9].in_uop.bits.fp_ctrl.fromint \n connect slots_9.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[9].in_uop.bits.fp_ctrl.typeTagOut \n connect slots_9.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[9].in_uop.bits.fp_ctrl.typeTagIn \n connect slots_9.io.in_uop.bits.fp_ctrl.swap23, issue_slots[9].in_uop.bits.fp_ctrl.swap23 \n connect slots_9.io.in_uop.bits.fp_ctrl.swap12, issue_slots[9].in_uop.bits.fp_ctrl.swap12 \n connect slots_9.io.in_uop.bits.fp_ctrl.ren3, issue_slots[9].in_uop.bits.fp_ctrl.ren3 \n connect slots_9.io.in_uop.bits.fp_ctrl.ren2, issue_slots[9].in_uop.bits.fp_ctrl.ren2 \n connect slots_9.io.in_uop.bits.fp_ctrl.ren1, issue_slots[9].in_uop.bits.fp_ctrl.ren1 \n connect slots_9.io.in_uop.bits.fp_ctrl.wen, issue_slots[9].in_uop.bits.fp_ctrl.wen \n connect slots_9.io.in_uop.bits.fp_ctrl.ldst, issue_slots[9].in_uop.bits.fp_ctrl.ldst \n connect slots_9.io.in_uop.bits.op2_sel, issue_slots[9].in_uop.bits.op2_sel \n connect slots_9.io.in_uop.bits.op1_sel, issue_slots[9].in_uop.bits.op1_sel \n connect slots_9.io.in_uop.bits.imm_packed, issue_slots[9].in_uop.bits.imm_packed \n connect slots_9.io.in_uop.bits.pimm, issue_slots[9].in_uop.bits.pimm \n connect slots_9.io.in_uop.bits.imm_sel, issue_slots[9].in_uop.bits.imm_sel \n connect slots_9.io.in_uop.bits.imm_rename, issue_slots[9].in_uop.bits.imm_rename \n connect slots_9.io.in_uop.bits.taken, issue_slots[9].in_uop.bits.taken \n connect slots_9.io.in_uop.bits.pc_lob, issue_slots[9].in_uop.bits.pc_lob \n connect slots_9.io.in_uop.bits.edge_inst, issue_slots[9].in_uop.bits.edge_inst \n connect slots_9.io.in_uop.bits.ftq_idx, issue_slots[9].in_uop.bits.ftq_idx \n connect slots_9.io.in_uop.bits.is_mov, issue_slots[9].in_uop.bits.is_mov \n connect slots_9.io.in_uop.bits.is_rocc, issue_slots[9].in_uop.bits.is_rocc \n connect slots_9.io.in_uop.bits.is_sys_pc2epc, issue_slots[9].in_uop.bits.is_sys_pc2epc \n connect slots_9.io.in_uop.bits.is_eret, issue_slots[9].in_uop.bits.is_eret \n connect slots_9.io.in_uop.bits.is_amo, issue_slots[9].in_uop.bits.is_amo \n connect slots_9.io.in_uop.bits.is_sfence, issue_slots[9].in_uop.bits.is_sfence \n connect slots_9.io.in_uop.bits.is_fencei, issue_slots[9].in_uop.bits.is_fencei \n connect slots_9.io.in_uop.bits.is_fence, issue_slots[9].in_uop.bits.is_fence \n connect slots_9.io.in_uop.bits.is_sfb, issue_slots[9].in_uop.bits.is_sfb \n connect slots_9.io.in_uop.bits.br_type, issue_slots[9].in_uop.bits.br_type \n connect slots_9.io.in_uop.bits.br_tag, issue_slots[9].in_uop.bits.br_tag \n connect slots_9.io.in_uop.bits.br_mask, issue_slots[9].in_uop.bits.br_mask \n connect slots_9.io.in_uop.bits.dis_col_sel, issue_slots[9].in_uop.bits.dis_col_sel \n connect slots_9.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[9].in_uop.bits.iw_p3_bypass_hint \n connect slots_9.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[9].in_uop.bits.iw_p2_bypass_hint \n connect slots_9.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[9].in_uop.bits.iw_p1_bypass_hint \n connect slots_9.io.in_uop.bits.iw_p2_speculative_child, issue_slots[9].in_uop.bits.iw_p2_speculative_child \n connect slots_9.io.in_uop.bits.iw_p1_speculative_child, issue_slots[9].in_uop.bits.iw_p1_speculative_child \n connect slots_9.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[9].in_uop.bits.iw_issued_partial_dgen \n connect slots_9.io.in_uop.bits.iw_issued_partial_agen, issue_slots[9].in_uop.bits.iw_issued_partial_agen \n connect slots_9.io.in_uop.bits.iw_issued, issue_slots[9].in_uop.bits.iw_issued \n connect slots_9.io.in_uop.bits.fu_code[0], issue_slots[9].in_uop.bits.fu_code[0] \n connect slots_9.io.in_uop.bits.fu_code[1], issue_slots[9].in_uop.bits.fu_code[1] \n connect slots_9.io.in_uop.bits.fu_code[2], issue_slots[9].in_uop.bits.fu_code[2] \n connect slots_9.io.in_uop.bits.fu_code[3], issue_slots[9].in_uop.bits.fu_code[3] \n connect slots_9.io.in_uop.bits.fu_code[4], issue_slots[9].in_uop.bits.fu_code[4] \n connect slots_9.io.in_uop.bits.fu_code[5], issue_slots[9].in_uop.bits.fu_code[5] \n connect slots_9.io.in_uop.bits.fu_code[6], issue_slots[9].in_uop.bits.fu_code[6] \n connect slots_9.io.in_uop.bits.fu_code[7], issue_slots[9].in_uop.bits.fu_code[7] \n connect slots_9.io.in_uop.bits.fu_code[8], issue_slots[9].in_uop.bits.fu_code[8] \n connect slots_9.io.in_uop.bits.fu_code[9], issue_slots[9].in_uop.bits.fu_code[9] \n connect slots_9.io.in_uop.bits.iq_type[0], issue_slots[9].in_uop.bits.iq_type[0] \n connect slots_9.io.in_uop.bits.iq_type[1], issue_slots[9].in_uop.bits.iq_type[1] \n connect slots_9.io.in_uop.bits.iq_type[2], issue_slots[9].in_uop.bits.iq_type[2] \n connect slots_9.io.in_uop.bits.iq_type[3], issue_slots[9].in_uop.bits.iq_type[3] \n connect slots_9.io.in_uop.bits.debug_pc, issue_slots[9].in_uop.bits.debug_pc \n connect slots_9.io.in_uop.bits.is_rvc, issue_slots[9].in_uop.bits.is_rvc \n connect slots_9.io.in_uop.bits.debug_inst, issue_slots[9].in_uop.bits.debug_inst \n connect slots_9.io.in_uop.bits.inst, issue_slots[9].in_uop.bits.inst \n connect slots_9.io.in_uop.valid, issue_slots[9].in_uop.valid \n connect issue_slots[9].iss_uop.debug_tsrc, slots_9.io.iss_uop.debug_tsrc \n connect issue_slots[9].iss_uop.debug_fsrc, slots_9.io.iss_uop.debug_fsrc \n connect issue_slots[9].iss_uop.bp_xcpt_if, slots_9.io.iss_uop.bp_xcpt_if \n connect issue_slots[9].iss_uop.bp_debug_if, slots_9.io.iss_uop.bp_debug_if \n connect issue_slots[9].iss_uop.xcpt_ma_if, slots_9.io.iss_uop.xcpt_ma_if \n connect issue_slots[9].iss_uop.xcpt_ae_if, slots_9.io.iss_uop.xcpt_ae_if \n connect issue_slots[9].iss_uop.xcpt_pf_if, slots_9.io.iss_uop.xcpt_pf_if \n connect issue_slots[9].iss_uop.fp_typ, slots_9.io.iss_uop.fp_typ \n connect issue_slots[9].iss_uop.fp_rm, slots_9.io.iss_uop.fp_rm \n connect issue_slots[9].iss_uop.fp_val, slots_9.io.iss_uop.fp_val \n connect issue_slots[9].iss_uop.fcn_op, slots_9.io.iss_uop.fcn_op \n connect issue_slots[9].iss_uop.fcn_dw, slots_9.io.iss_uop.fcn_dw \n connect issue_slots[9].iss_uop.frs3_en, slots_9.io.iss_uop.frs3_en \n connect issue_slots[9].iss_uop.lrs2_rtype, slots_9.io.iss_uop.lrs2_rtype \n connect issue_slots[9].iss_uop.lrs1_rtype, slots_9.io.iss_uop.lrs1_rtype \n connect issue_slots[9].iss_uop.dst_rtype, slots_9.io.iss_uop.dst_rtype \n connect issue_slots[9].iss_uop.lrs3, slots_9.io.iss_uop.lrs3 \n connect issue_slots[9].iss_uop.lrs2, slots_9.io.iss_uop.lrs2 \n connect issue_slots[9].iss_uop.lrs1, slots_9.io.iss_uop.lrs1 \n connect issue_slots[9].iss_uop.ldst, slots_9.io.iss_uop.ldst \n connect issue_slots[9].iss_uop.ldst_is_rs1, slots_9.io.iss_uop.ldst_is_rs1 \n connect issue_slots[9].iss_uop.csr_cmd, slots_9.io.iss_uop.csr_cmd \n connect issue_slots[9].iss_uop.flush_on_commit, slots_9.io.iss_uop.flush_on_commit \n connect issue_slots[9].iss_uop.is_unique, slots_9.io.iss_uop.is_unique \n connect issue_slots[9].iss_uop.uses_stq, slots_9.io.iss_uop.uses_stq \n connect issue_slots[9].iss_uop.uses_ldq, slots_9.io.iss_uop.uses_ldq \n connect issue_slots[9].iss_uop.mem_signed, slots_9.io.iss_uop.mem_signed \n connect issue_slots[9].iss_uop.mem_size, slots_9.io.iss_uop.mem_size \n connect issue_slots[9].iss_uop.mem_cmd, slots_9.io.iss_uop.mem_cmd \n connect issue_slots[9].iss_uop.exc_cause, slots_9.io.iss_uop.exc_cause \n connect issue_slots[9].iss_uop.exception, slots_9.io.iss_uop.exception \n connect issue_slots[9].iss_uop.stale_pdst, slots_9.io.iss_uop.stale_pdst \n connect issue_slots[9].iss_uop.ppred_busy, slots_9.io.iss_uop.ppred_busy \n connect issue_slots[9].iss_uop.prs3_busy, slots_9.io.iss_uop.prs3_busy \n connect issue_slots[9].iss_uop.prs2_busy, slots_9.io.iss_uop.prs2_busy \n connect issue_slots[9].iss_uop.prs1_busy, slots_9.io.iss_uop.prs1_busy \n connect issue_slots[9].iss_uop.ppred, slots_9.io.iss_uop.ppred \n connect issue_slots[9].iss_uop.prs3, slots_9.io.iss_uop.prs3 \n connect issue_slots[9].iss_uop.prs2, slots_9.io.iss_uop.prs2 \n connect issue_slots[9].iss_uop.prs1, slots_9.io.iss_uop.prs1 \n connect issue_slots[9].iss_uop.pdst, slots_9.io.iss_uop.pdst \n connect issue_slots[9].iss_uop.rxq_idx, slots_9.io.iss_uop.rxq_idx \n connect issue_slots[9].iss_uop.stq_idx, slots_9.io.iss_uop.stq_idx \n connect issue_slots[9].iss_uop.ldq_idx, slots_9.io.iss_uop.ldq_idx \n connect issue_slots[9].iss_uop.rob_idx, slots_9.io.iss_uop.rob_idx \n connect issue_slots[9].iss_uop.fp_ctrl.vec, slots_9.io.iss_uop.fp_ctrl.vec \n connect issue_slots[9].iss_uop.fp_ctrl.wflags, slots_9.io.iss_uop.fp_ctrl.wflags \n connect issue_slots[9].iss_uop.fp_ctrl.sqrt, slots_9.io.iss_uop.fp_ctrl.sqrt \n connect issue_slots[9].iss_uop.fp_ctrl.div, slots_9.io.iss_uop.fp_ctrl.div \n connect issue_slots[9].iss_uop.fp_ctrl.fma, slots_9.io.iss_uop.fp_ctrl.fma \n connect issue_slots[9].iss_uop.fp_ctrl.fastpipe, slots_9.io.iss_uop.fp_ctrl.fastpipe \n connect issue_slots[9].iss_uop.fp_ctrl.toint, slots_9.io.iss_uop.fp_ctrl.toint \n connect issue_slots[9].iss_uop.fp_ctrl.fromint, slots_9.io.iss_uop.fp_ctrl.fromint \n connect issue_slots[9].iss_uop.fp_ctrl.typeTagOut, slots_9.io.iss_uop.fp_ctrl.typeTagOut \n connect issue_slots[9].iss_uop.fp_ctrl.typeTagIn, slots_9.io.iss_uop.fp_ctrl.typeTagIn \n connect issue_slots[9].iss_uop.fp_ctrl.swap23, slots_9.io.iss_uop.fp_ctrl.swap23 \n connect issue_slots[9].iss_uop.fp_ctrl.swap12, slots_9.io.iss_uop.fp_ctrl.swap12 \n connect issue_slots[9].iss_uop.fp_ctrl.ren3, slots_9.io.iss_uop.fp_ctrl.ren3 \n connect issue_slots[9].iss_uop.fp_ctrl.ren2, slots_9.io.iss_uop.fp_ctrl.ren2 \n connect issue_slots[9].iss_uop.fp_ctrl.ren1, slots_9.io.iss_uop.fp_ctrl.ren1 \n connect issue_slots[9].iss_uop.fp_ctrl.wen, slots_9.io.iss_uop.fp_ctrl.wen \n connect issue_slots[9].iss_uop.fp_ctrl.ldst, slots_9.io.iss_uop.fp_ctrl.ldst \n connect issue_slots[9].iss_uop.op2_sel, slots_9.io.iss_uop.op2_sel \n connect issue_slots[9].iss_uop.op1_sel, slots_9.io.iss_uop.op1_sel \n connect issue_slots[9].iss_uop.imm_packed, slots_9.io.iss_uop.imm_packed \n connect issue_slots[9].iss_uop.pimm, slots_9.io.iss_uop.pimm \n connect issue_slots[9].iss_uop.imm_sel, slots_9.io.iss_uop.imm_sel \n connect issue_slots[9].iss_uop.imm_rename, slots_9.io.iss_uop.imm_rename \n connect issue_slots[9].iss_uop.taken, slots_9.io.iss_uop.taken \n connect issue_slots[9].iss_uop.pc_lob, slots_9.io.iss_uop.pc_lob \n connect issue_slots[9].iss_uop.edge_inst, slots_9.io.iss_uop.edge_inst \n connect issue_slots[9].iss_uop.ftq_idx, slots_9.io.iss_uop.ftq_idx \n connect issue_slots[9].iss_uop.is_mov, slots_9.io.iss_uop.is_mov \n connect issue_slots[9].iss_uop.is_rocc, slots_9.io.iss_uop.is_rocc \n connect issue_slots[9].iss_uop.is_sys_pc2epc, slots_9.io.iss_uop.is_sys_pc2epc \n connect issue_slots[9].iss_uop.is_eret, slots_9.io.iss_uop.is_eret \n connect issue_slots[9].iss_uop.is_amo, slots_9.io.iss_uop.is_amo \n connect issue_slots[9].iss_uop.is_sfence, slots_9.io.iss_uop.is_sfence \n connect issue_slots[9].iss_uop.is_fencei, slots_9.io.iss_uop.is_fencei \n connect issue_slots[9].iss_uop.is_fence, slots_9.io.iss_uop.is_fence \n connect issue_slots[9].iss_uop.is_sfb, slots_9.io.iss_uop.is_sfb \n connect issue_slots[9].iss_uop.br_type, slots_9.io.iss_uop.br_type \n connect issue_slots[9].iss_uop.br_tag, slots_9.io.iss_uop.br_tag \n connect issue_slots[9].iss_uop.br_mask, slots_9.io.iss_uop.br_mask \n connect issue_slots[9].iss_uop.dis_col_sel, slots_9.io.iss_uop.dis_col_sel \n connect issue_slots[9].iss_uop.iw_p3_bypass_hint, slots_9.io.iss_uop.iw_p3_bypass_hint \n connect issue_slots[9].iss_uop.iw_p2_bypass_hint, slots_9.io.iss_uop.iw_p2_bypass_hint \n connect issue_slots[9].iss_uop.iw_p1_bypass_hint, slots_9.io.iss_uop.iw_p1_bypass_hint \n connect issue_slots[9].iss_uop.iw_p2_speculative_child, slots_9.io.iss_uop.iw_p2_speculative_child \n connect issue_slots[9].iss_uop.iw_p1_speculative_child, slots_9.io.iss_uop.iw_p1_speculative_child \n connect issue_slots[9].iss_uop.iw_issued_partial_dgen, slots_9.io.iss_uop.iw_issued_partial_dgen \n connect issue_slots[9].iss_uop.iw_issued_partial_agen, slots_9.io.iss_uop.iw_issued_partial_agen \n connect issue_slots[9].iss_uop.iw_issued, slots_9.io.iss_uop.iw_issued \n connect issue_slots[9].iss_uop.fu_code[0], slots_9.io.iss_uop.fu_code[0] \n connect issue_slots[9].iss_uop.fu_code[1], slots_9.io.iss_uop.fu_code[1] \n connect issue_slots[9].iss_uop.fu_code[2], slots_9.io.iss_uop.fu_code[2] \n connect issue_slots[9].iss_uop.fu_code[3], slots_9.io.iss_uop.fu_code[3] \n connect issue_slots[9].iss_uop.fu_code[4], slots_9.io.iss_uop.fu_code[4] \n connect issue_slots[9].iss_uop.fu_code[5], slots_9.io.iss_uop.fu_code[5] \n connect issue_slots[9].iss_uop.fu_code[6], slots_9.io.iss_uop.fu_code[6] \n connect issue_slots[9].iss_uop.fu_code[7], slots_9.io.iss_uop.fu_code[7] \n connect issue_slots[9].iss_uop.fu_code[8], slots_9.io.iss_uop.fu_code[8] \n connect issue_slots[9].iss_uop.fu_code[9], slots_9.io.iss_uop.fu_code[9] \n connect issue_slots[9].iss_uop.iq_type[0], slots_9.io.iss_uop.iq_type[0] \n connect issue_slots[9].iss_uop.iq_type[1], slots_9.io.iss_uop.iq_type[1] \n connect issue_slots[9].iss_uop.iq_type[2], slots_9.io.iss_uop.iq_type[2] \n connect issue_slots[9].iss_uop.iq_type[3], slots_9.io.iss_uop.iq_type[3] \n connect issue_slots[9].iss_uop.debug_pc, slots_9.io.iss_uop.debug_pc \n connect issue_slots[9].iss_uop.is_rvc, slots_9.io.iss_uop.is_rvc \n connect issue_slots[9].iss_uop.debug_inst, slots_9.io.iss_uop.debug_inst \n connect issue_slots[9].iss_uop.inst, slots_9.io.iss_uop.inst \n connect slots_9.io.grant, issue_slots[9].grant \n connect issue_slots[9].request, slots_9.io.request \n connect issue_slots[9].will_be_valid, slots_9.io.will_be_valid \n connect issue_slots[9].valid, slots_9.io.valid \n connect slots_10.io.child_rebusys, issue_slots[10].child_rebusys \n connect slots_10.io.pred_wakeup_port.bits, issue_slots[10].pred_wakeup_port.bits \n connect slots_10.io.pred_wakeup_port.valid, issue_slots[10].pred_wakeup_port.valid \n connect slots_10.io.wakeup_ports[0].bits.rebusy, issue_slots[10].wakeup_ports[0].bits.rebusy \n connect slots_10.io.wakeup_ports[0].bits.speculative_mask, issue_slots[10].wakeup_ports[0].bits.speculative_mask \n connect slots_10.io.wakeup_ports[0].bits.bypassable, issue_slots[10].wakeup_ports[0].bits.bypassable \n connect slots_10.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[10].wakeup_ports[0].bits.uop.debug_tsrc \n connect slots_10.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[10].wakeup_ports[0].bits.uop.debug_fsrc \n connect slots_10.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[10].wakeup_ports[0].bits.uop.bp_xcpt_if \n connect slots_10.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[10].wakeup_ports[0].bits.uop.bp_debug_if \n connect slots_10.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[10].wakeup_ports[0].bits.uop.xcpt_ma_if \n connect slots_10.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[10].wakeup_ports[0].bits.uop.xcpt_ae_if \n connect slots_10.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[10].wakeup_ports[0].bits.uop.xcpt_pf_if \n connect slots_10.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[10].wakeup_ports[0].bits.uop.fp_typ \n connect slots_10.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[10].wakeup_ports[0].bits.uop.fp_rm \n connect slots_10.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[10].wakeup_ports[0].bits.uop.fp_val \n connect slots_10.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[10].wakeup_ports[0].bits.uop.fcn_op \n connect slots_10.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[10].wakeup_ports[0].bits.uop.fcn_dw \n connect slots_10.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[10].wakeup_ports[0].bits.uop.frs3_en \n connect slots_10.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[10].wakeup_ports[0].bits.uop.lrs2_rtype \n connect slots_10.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[10].wakeup_ports[0].bits.uop.lrs1_rtype \n connect slots_10.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[10].wakeup_ports[0].bits.uop.dst_rtype \n connect slots_10.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[10].wakeup_ports[0].bits.uop.lrs3 \n connect slots_10.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[10].wakeup_ports[0].bits.uop.lrs2 \n connect slots_10.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[10].wakeup_ports[0].bits.uop.lrs1 \n connect slots_10.io.wakeup_ports[0].bits.uop.ldst, issue_slots[10].wakeup_ports[0].bits.uop.ldst \n connect slots_10.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[10].wakeup_ports[0].bits.uop.ldst_is_rs1 \n connect slots_10.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[10].wakeup_ports[0].bits.uop.csr_cmd \n connect slots_10.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[10].wakeup_ports[0].bits.uop.flush_on_commit \n connect slots_10.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[10].wakeup_ports[0].bits.uop.is_unique \n connect slots_10.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[10].wakeup_ports[0].bits.uop.uses_stq \n connect slots_10.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[10].wakeup_ports[0].bits.uop.uses_ldq \n connect slots_10.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[10].wakeup_ports[0].bits.uop.mem_signed \n connect slots_10.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[10].wakeup_ports[0].bits.uop.mem_size \n connect slots_10.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[10].wakeup_ports[0].bits.uop.mem_cmd \n connect slots_10.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[10].wakeup_ports[0].bits.uop.exc_cause \n connect slots_10.io.wakeup_ports[0].bits.uop.exception, issue_slots[10].wakeup_ports[0].bits.uop.exception \n connect slots_10.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[10].wakeup_ports[0].bits.uop.stale_pdst \n connect slots_10.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[10].wakeup_ports[0].bits.uop.ppred_busy \n connect slots_10.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[10].wakeup_ports[0].bits.uop.prs3_busy \n connect slots_10.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[10].wakeup_ports[0].bits.uop.prs2_busy \n connect slots_10.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[10].wakeup_ports[0].bits.uop.prs1_busy \n connect slots_10.io.wakeup_ports[0].bits.uop.ppred, issue_slots[10].wakeup_ports[0].bits.uop.ppred \n connect slots_10.io.wakeup_ports[0].bits.uop.prs3, issue_slots[10].wakeup_ports[0].bits.uop.prs3 \n connect slots_10.io.wakeup_ports[0].bits.uop.prs2, issue_slots[10].wakeup_ports[0].bits.uop.prs2 \n connect slots_10.io.wakeup_ports[0].bits.uop.prs1, issue_slots[10].wakeup_ports[0].bits.uop.prs1 \n connect slots_10.io.wakeup_ports[0].bits.uop.pdst, issue_slots[10].wakeup_ports[0].bits.uop.pdst \n connect slots_10.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[10].wakeup_ports[0].bits.uop.rxq_idx \n connect slots_10.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[10].wakeup_ports[0].bits.uop.stq_idx \n connect slots_10.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[10].wakeup_ports[0].bits.uop.ldq_idx \n connect slots_10.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[10].wakeup_ports[0].bits.uop.rob_idx \n connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.vec \n connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.wflags \n connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.sqrt \n connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.div \n connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.fma \n connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe \n connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.toint \n connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.fromint \n connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut \n connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn \n connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.swap23 \n connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.swap12 \n connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.ren3 \n connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.ren2 \n connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.ren1 \n connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.wen \n connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.ldst \n connect slots_10.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[10].wakeup_ports[0].bits.uop.op2_sel \n connect slots_10.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[10].wakeup_ports[0].bits.uop.op1_sel \n connect slots_10.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[10].wakeup_ports[0].bits.uop.imm_packed \n connect slots_10.io.wakeup_ports[0].bits.uop.pimm, issue_slots[10].wakeup_ports[0].bits.uop.pimm \n connect slots_10.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[10].wakeup_ports[0].bits.uop.imm_sel \n connect slots_10.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[10].wakeup_ports[0].bits.uop.imm_rename \n connect slots_10.io.wakeup_ports[0].bits.uop.taken, issue_slots[10].wakeup_ports[0].bits.uop.taken \n connect slots_10.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[10].wakeup_ports[0].bits.uop.pc_lob \n connect slots_10.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[10].wakeup_ports[0].bits.uop.edge_inst \n connect slots_10.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[10].wakeup_ports[0].bits.uop.ftq_idx \n connect slots_10.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[10].wakeup_ports[0].bits.uop.is_mov \n connect slots_10.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[10].wakeup_ports[0].bits.uop.is_rocc \n connect slots_10.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[10].wakeup_ports[0].bits.uop.is_sys_pc2epc \n connect slots_10.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[10].wakeup_ports[0].bits.uop.is_eret \n connect slots_10.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[10].wakeup_ports[0].bits.uop.is_amo \n connect slots_10.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[10].wakeup_ports[0].bits.uop.is_sfence \n connect slots_10.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[10].wakeup_ports[0].bits.uop.is_fencei \n connect slots_10.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[10].wakeup_ports[0].bits.uop.is_fence \n connect slots_10.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[10].wakeup_ports[0].bits.uop.is_sfb \n connect slots_10.io.wakeup_ports[0].bits.uop.br_type, issue_slots[10].wakeup_ports[0].bits.uop.br_type \n connect slots_10.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[10].wakeup_ports[0].bits.uop.br_tag \n connect slots_10.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[10].wakeup_ports[0].bits.uop.br_mask \n connect slots_10.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[10].wakeup_ports[0].bits.uop.dis_col_sel \n connect slots_10.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[10].wakeup_ports[0].bits.uop.iw_p3_bypass_hint \n connect slots_10.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[10].wakeup_ports[0].bits.uop.iw_p2_bypass_hint \n connect slots_10.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[10].wakeup_ports[0].bits.uop.iw_p1_bypass_hint \n connect slots_10.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[10].wakeup_ports[0].bits.uop.iw_p2_speculative_child \n connect slots_10.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[10].wakeup_ports[0].bits.uop.iw_p1_speculative_child \n connect slots_10.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[10].wakeup_ports[0].bits.uop.iw_issued_partial_dgen \n connect slots_10.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[10].wakeup_ports[0].bits.uop.iw_issued_partial_agen \n connect slots_10.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[10].wakeup_ports[0].bits.uop.iw_issued \n connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[0] \n connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[1] \n connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[2] \n connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[3] \n connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[4] \n connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[5] \n connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[6] \n connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[7] \n connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[8] \n connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[9] \n connect slots_10.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[10].wakeup_ports[0].bits.uop.iq_type[0] \n connect slots_10.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[10].wakeup_ports[0].bits.uop.iq_type[1] \n connect slots_10.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[10].wakeup_ports[0].bits.uop.iq_type[2] \n connect slots_10.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[10].wakeup_ports[0].bits.uop.iq_type[3] \n connect slots_10.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[10].wakeup_ports[0].bits.uop.debug_pc \n connect slots_10.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[10].wakeup_ports[0].bits.uop.is_rvc \n connect slots_10.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[10].wakeup_ports[0].bits.uop.debug_inst \n connect slots_10.io.wakeup_ports[0].bits.uop.inst, issue_slots[10].wakeup_ports[0].bits.uop.inst \n connect slots_10.io.wakeup_ports[0].valid, issue_slots[10].wakeup_ports[0].valid \n connect slots_10.io.wakeup_ports[1].bits.rebusy, issue_slots[10].wakeup_ports[1].bits.rebusy \n connect slots_10.io.wakeup_ports[1].bits.speculative_mask, issue_slots[10].wakeup_ports[1].bits.speculative_mask \n connect slots_10.io.wakeup_ports[1].bits.bypassable, issue_slots[10].wakeup_ports[1].bits.bypassable \n connect slots_10.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[10].wakeup_ports[1].bits.uop.debug_tsrc \n connect slots_10.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[10].wakeup_ports[1].bits.uop.debug_fsrc \n connect slots_10.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[10].wakeup_ports[1].bits.uop.bp_xcpt_if \n connect slots_10.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[10].wakeup_ports[1].bits.uop.bp_debug_if \n connect slots_10.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[10].wakeup_ports[1].bits.uop.xcpt_ma_if \n connect slots_10.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[10].wakeup_ports[1].bits.uop.xcpt_ae_if \n connect slots_10.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[10].wakeup_ports[1].bits.uop.xcpt_pf_if \n connect slots_10.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[10].wakeup_ports[1].bits.uop.fp_typ \n connect slots_10.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[10].wakeup_ports[1].bits.uop.fp_rm \n connect slots_10.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[10].wakeup_ports[1].bits.uop.fp_val \n connect slots_10.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[10].wakeup_ports[1].bits.uop.fcn_op \n connect slots_10.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[10].wakeup_ports[1].bits.uop.fcn_dw \n connect slots_10.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[10].wakeup_ports[1].bits.uop.frs3_en \n connect slots_10.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[10].wakeup_ports[1].bits.uop.lrs2_rtype \n connect slots_10.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[10].wakeup_ports[1].bits.uop.lrs1_rtype \n connect slots_10.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[10].wakeup_ports[1].bits.uop.dst_rtype \n connect slots_10.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[10].wakeup_ports[1].bits.uop.lrs3 \n connect slots_10.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[10].wakeup_ports[1].bits.uop.lrs2 \n connect slots_10.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[10].wakeup_ports[1].bits.uop.lrs1 \n connect slots_10.io.wakeup_ports[1].bits.uop.ldst, issue_slots[10].wakeup_ports[1].bits.uop.ldst \n connect slots_10.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[10].wakeup_ports[1].bits.uop.ldst_is_rs1 \n connect slots_10.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[10].wakeup_ports[1].bits.uop.csr_cmd \n connect slots_10.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[10].wakeup_ports[1].bits.uop.flush_on_commit \n connect slots_10.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[10].wakeup_ports[1].bits.uop.is_unique \n connect slots_10.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[10].wakeup_ports[1].bits.uop.uses_stq \n connect slots_10.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[10].wakeup_ports[1].bits.uop.uses_ldq \n connect slots_10.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[10].wakeup_ports[1].bits.uop.mem_signed \n connect slots_10.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[10].wakeup_ports[1].bits.uop.mem_size \n connect slots_10.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[10].wakeup_ports[1].bits.uop.mem_cmd \n connect slots_10.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[10].wakeup_ports[1].bits.uop.exc_cause \n connect slots_10.io.wakeup_ports[1].bits.uop.exception, issue_slots[10].wakeup_ports[1].bits.uop.exception \n connect slots_10.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[10].wakeup_ports[1].bits.uop.stale_pdst \n connect slots_10.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[10].wakeup_ports[1].bits.uop.ppred_busy \n connect slots_10.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[10].wakeup_ports[1].bits.uop.prs3_busy \n connect slots_10.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[10].wakeup_ports[1].bits.uop.prs2_busy \n connect slots_10.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[10].wakeup_ports[1].bits.uop.prs1_busy \n connect slots_10.io.wakeup_ports[1].bits.uop.ppred, issue_slots[10].wakeup_ports[1].bits.uop.ppred \n connect slots_10.io.wakeup_ports[1].bits.uop.prs3, issue_slots[10].wakeup_ports[1].bits.uop.prs3 \n connect slots_10.io.wakeup_ports[1].bits.uop.prs2, issue_slots[10].wakeup_ports[1].bits.uop.prs2 \n connect slots_10.io.wakeup_ports[1].bits.uop.prs1, issue_slots[10].wakeup_ports[1].bits.uop.prs1 \n connect slots_10.io.wakeup_ports[1].bits.uop.pdst, issue_slots[10].wakeup_ports[1].bits.uop.pdst \n connect slots_10.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[10].wakeup_ports[1].bits.uop.rxq_idx \n connect slots_10.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[10].wakeup_ports[1].bits.uop.stq_idx \n connect slots_10.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[10].wakeup_ports[1].bits.uop.ldq_idx \n connect slots_10.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[10].wakeup_ports[1].bits.uop.rob_idx \n connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.vec \n connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.wflags \n connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.sqrt \n connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.div \n connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.fma \n connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe \n connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.toint \n connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.fromint \n connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut \n connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn \n connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.swap23 \n connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.swap12 \n connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.ren3 \n connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.ren2 \n connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.ren1 \n connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.wen \n connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.ldst \n connect slots_10.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[10].wakeup_ports[1].bits.uop.op2_sel \n connect slots_10.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[10].wakeup_ports[1].bits.uop.op1_sel \n connect slots_10.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[10].wakeup_ports[1].bits.uop.imm_packed \n connect slots_10.io.wakeup_ports[1].bits.uop.pimm, issue_slots[10].wakeup_ports[1].bits.uop.pimm \n connect slots_10.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[10].wakeup_ports[1].bits.uop.imm_sel \n connect slots_10.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[10].wakeup_ports[1].bits.uop.imm_rename \n connect slots_10.io.wakeup_ports[1].bits.uop.taken, issue_slots[10].wakeup_ports[1].bits.uop.taken \n connect slots_10.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[10].wakeup_ports[1].bits.uop.pc_lob \n connect slots_10.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[10].wakeup_ports[1].bits.uop.edge_inst \n connect slots_10.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[10].wakeup_ports[1].bits.uop.ftq_idx \n connect slots_10.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[10].wakeup_ports[1].bits.uop.is_mov \n connect slots_10.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[10].wakeup_ports[1].bits.uop.is_rocc \n connect slots_10.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[10].wakeup_ports[1].bits.uop.is_sys_pc2epc \n connect slots_10.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[10].wakeup_ports[1].bits.uop.is_eret \n connect slots_10.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[10].wakeup_ports[1].bits.uop.is_amo \n connect slots_10.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[10].wakeup_ports[1].bits.uop.is_sfence \n connect slots_10.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[10].wakeup_ports[1].bits.uop.is_fencei \n connect slots_10.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[10].wakeup_ports[1].bits.uop.is_fence \n connect slots_10.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[10].wakeup_ports[1].bits.uop.is_sfb \n connect slots_10.io.wakeup_ports[1].bits.uop.br_type, issue_slots[10].wakeup_ports[1].bits.uop.br_type \n connect slots_10.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[10].wakeup_ports[1].bits.uop.br_tag \n connect slots_10.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[10].wakeup_ports[1].bits.uop.br_mask \n connect slots_10.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[10].wakeup_ports[1].bits.uop.dis_col_sel \n connect slots_10.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[10].wakeup_ports[1].bits.uop.iw_p3_bypass_hint \n connect slots_10.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[10].wakeup_ports[1].bits.uop.iw_p2_bypass_hint \n connect slots_10.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[10].wakeup_ports[1].bits.uop.iw_p1_bypass_hint \n connect slots_10.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[10].wakeup_ports[1].bits.uop.iw_p2_speculative_child \n connect slots_10.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[10].wakeup_ports[1].bits.uop.iw_p1_speculative_child \n connect slots_10.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[10].wakeup_ports[1].bits.uop.iw_issued_partial_dgen \n connect slots_10.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[10].wakeup_ports[1].bits.uop.iw_issued_partial_agen \n connect slots_10.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[10].wakeup_ports[1].bits.uop.iw_issued \n connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[0] \n connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[1] \n connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[2] \n connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[3] \n connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[4] \n connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[5] \n connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[6] \n connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[7] \n connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[8] \n connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[9] \n connect slots_10.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[10].wakeup_ports[1].bits.uop.iq_type[0] \n connect slots_10.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[10].wakeup_ports[1].bits.uop.iq_type[1] \n connect slots_10.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[10].wakeup_ports[1].bits.uop.iq_type[2] \n connect slots_10.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[10].wakeup_ports[1].bits.uop.iq_type[3] \n connect slots_10.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[10].wakeup_ports[1].bits.uop.debug_pc \n connect slots_10.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[10].wakeup_ports[1].bits.uop.is_rvc \n connect slots_10.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[10].wakeup_ports[1].bits.uop.debug_inst \n connect slots_10.io.wakeup_ports[1].bits.uop.inst, issue_slots[10].wakeup_ports[1].bits.uop.inst \n connect slots_10.io.wakeup_ports[1].valid, issue_slots[10].wakeup_ports[1].valid \n connect slots_10.io.wakeup_ports[2].bits.rebusy, issue_slots[10].wakeup_ports[2].bits.rebusy \n connect slots_10.io.wakeup_ports[2].bits.speculative_mask, issue_slots[10].wakeup_ports[2].bits.speculative_mask \n connect slots_10.io.wakeup_ports[2].bits.bypassable, issue_slots[10].wakeup_ports[2].bits.bypassable \n connect slots_10.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[10].wakeup_ports[2].bits.uop.debug_tsrc \n connect slots_10.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[10].wakeup_ports[2].bits.uop.debug_fsrc \n connect slots_10.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[10].wakeup_ports[2].bits.uop.bp_xcpt_if \n connect slots_10.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[10].wakeup_ports[2].bits.uop.bp_debug_if \n connect slots_10.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[10].wakeup_ports[2].bits.uop.xcpt_ma_if \n connect slots_10.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[10].wakeup_ports[2].bits.uop.xcpt_ae_if \n connect slots_10.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[10].wakeup_ports[2].bits.uop.xcpt_pf_if \n connect slots_10.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[10].wakeup_ports[2].bits.uop.fp_typ \n connect slots_10.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[10].wakeup_ports[2].bits.uop.fp_rm \n connect slots_10.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[10].wakeup_ports[2].bits.uop.fp_val \n connect slots_10.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[10].wakeup_ports[2].bits.uop.fcn_op \n connect slots_10.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[10].wakeup_ports[2].bits.uop.fcn_dw \n connect slots_10.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[10].wakeup_ports[2].bits.uop.frs3_en \n connect slots_10.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[10].wakeup_ports[2].bits.uop.lrs2_rtype \n connect slots_10.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[10].wakeup_ports[2].bits.uop.lrs1_rtype \n connect slots_10.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[10].wakeup_ports[2].bits.uop.dst_rtype \n connect slots_10.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[10].wakeup_ports[2].bits.uop.lrs3 \n connect slots_10.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[10].wakeup_ports[2].bits.uop.lrs2 \n connect slots_10.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[10].wakeup_ports[2].bits.uop.lrs1 \n connect slots_10.io.wakeup_ports[2].bits.uop.ldst, issue_slots[10].wakeup_ports[2].bits.uop.ldst \n connect slots_10.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[10].wakeup_ports[2].bits.uop.ldst_is_rs1 \n connect slots_10.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[10].wakeup_ports[2].bits.uop.csr_cmd \n connect slots_10.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[10].wakeup_ports[2].bits.uop.flush_on_commit \n connect slots_10.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[10].wakeup_ports[2].bits.uop.is_unique \n connect slots_10.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[10].wakeup_ports[2].bits.uop.uses_stq \n connect slots_10.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[10].wakeup_ports[2].bits.uop.uses_ldq \n connect slots_10.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[10].wakeup_ports[2].bits.uop.mem_signed \n connect slots_10.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[10].wakeup_ports[2].bits.uop.mem_size \n connect slots_10.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[10].wakeup_ports[2].bits.uop.mem_cmd \n connect slots_10.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[10].wakeup_ports[2].bits.uop.exc_cause \n connect slots_10.io.wakeup_ports[2].bits.uop.exception, issue_slots[10].wakeup_ports[2].bits.uop.exception \n connect slots_10.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[10].wakeup_ports[2].bits.uop.stale_pdst \n connect slots_10.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[10].wakeup_ports[2].bits.uop.ppred_busy \n connect slots_10.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[10].wakeup_ports[2].bits.uop.prs3_busy \n connect slots_10.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[10].wakeup_ports[2].bits.uop.prs2_busy \n connect slots_10.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[10].wakeup_ports[2].bits.uop.prs1_busy \n connect slots_10.io.wakeup_ports[2].bits.uop.ppred, issue_slots[10].wakeup_ports[2].bits.uop.ppred \n connect slots_10.io.wakeup_ports[2].bits.uop.prs3, issue_slots[10].wakeup_ports[2].bits.uop.prs3 \n connect slots_10.io.wakeup_ports[2].bits.uop.prs2, issue_slots[10].wakeup_ports[2].bits.uop.prs2 \n connect slots_10.io.wakeup_ports[2].bits.uop.prs1, issue_slots[10].wakeup_ports[2].bits.uop.prs1 \n connect slots_10.io.wakeup_ports[2].bits.uop.pdst, issue_slots[10].wakeup_ports[2].bits.uop.pdst \n connect slots_10.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[10].wakeup_ports[2].bits.uop.rxq_idx \n connect slots_10.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[10].wakeup_ports[2].bits.uop.stq_idx \n connect slots_10.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[10].wakeup_ports[2].bits.uop.ldq_idx \n connect slots_10.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[10].wakeup_ports[2].bits.uop.rob_idx \n connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.vec \n connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.wflags \n connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.sqrt \n connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.div \n connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.fma \n connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe \n connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.toint \n connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.fromint \n connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut \n connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn \n connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.swap23 \n connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.swap12 \n connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.ren3 \n connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.ren2 \n connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.ren1 \n connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.wen \n connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.ldst \n connect slots_10.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[10].wakeup_ports[2].bits.uop.op2_sel \n connect slots_10.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[10].wakeup_ports[2].bits.uop.op1_sel \n connect slots_10.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[10].wakeup_ports[2].bits.uop.imm_packed \n connect slots_10.io.wakeup_ports[2].bits.uop.pimm, issue_slots[10].wakeup_ports[2].bits.uop.pimm \n connect slots_10.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[10].wakeup_ports[2].bits.uop.imm_sel \n connect slots_10.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[10].wakeup_ports[2].bits.uop.imm_rename \n connect slots_10.io.wakeup_ports[2].bits.uop.taken, issue_slots[10].wakeup_ports[2].bits.uop.taken \n connect slots_10.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[10].wakeup_ports[2].bits.uop.pc_lob \n connect slots_10.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[10].wakeup_ports[2].bits.uop.edge_inst \n connect slots_10.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[10].wakeup_ports[2].bits.uop.ftq_idx \n connect slots_10.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[10].wakeup_ports[2].bits.uop.is_mov \n connect slots_10.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[10].wakeup_ports[2].bits.uop.is_rocc \n connect slots_10.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[10].wakeup_ports[2].bits.uop.is_sys_pc2epc \n connect slots_10.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[10].wakeup_ports[2].bits.uop.is_eret \n connect slots_10.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[10].wakeup_ports[2].bits.uop.is_amo \n connect slots_10.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[10].wakeup_ports[2].bits.uop.is_sfence \n connect slots_10.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[10].wakeup_ports[2].bits.uop.is_fencei \n connect slots_10.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[10].wakeup_ports[2].bits.uop.is_fence \n connect slots_10.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[10].wakeup_ports[2].bits.uop.is_sfb \n connect slots_10.io.wakeup_ports[2].bits.uop.br_type, issue_slots[10].wakeup_ports[2].bits.uop.br_type \n connect slots_10.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[10].wakeup_ports[2].bits.uop.br_tag \n connect slots_10.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[10].wakeup_ports[2].bits.uop.br_mask \n connect slots_10.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[10].wakeup_ports[2].bits.uop.dis_col_sel \n connect slots_10.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[10].wakeup_ports[2].bits.uop.iw_p3_bypass_hint \n connect slots_10.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[10].wakeup_ports[2].bits.uop.iw_p2_bypass_hint \n connect slots_10.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[10].wakeup_ports[2].bits.uop.iw_p1_bypass_hint \n connect slots_10.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[10].wakeup_ports[2].bits.uop.iw_p2_speculative_child \n connect slots_10.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[10].wakeup_ports[2].bits.uop.iw_p1_speculative_child \n connect slots_10.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[10].wakeup_ports[2].bits.uop.iw_issued_partial_dgen \n connect slots_10.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[10].wakeup_ports[2].bits.uop.iw_issued_partial_agen \n connect slots_10.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[10].wakeup_ports[2].bits.uop.iw_issued \n connect slots_10.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[10].wakeup_ports[2].bits.uop.fu_code[0] \n connect slots_10.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[10].wakeup_ports[2].bits.uop.fu_code[1] \n connect slots_10.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[10].wakeup_ports[2].bits.uop.fu_code[2] \n connect slots_10.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[10].wakeup_ports[2].bits.uop.fu_code[3] \n connect slots_10.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[10].wakeup_ports[2].bits.uop.fu_code[4] \n connect slots_10.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[10].wakeup_ports[2].bits.uop.fu_code[5] \n connect slots_10.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[10].wakeup_ports[2].bits.uop.fu_code[6] \n connect slots_10.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[10].wakeup_ports[2].bits.uop.fu_code[7] \n connect slots_10.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[10].wakeup_ports[2].bits.uop.fu_code[8] \n connect slots_10.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[10].wakeup_ports[2].bits.uop.fu_code[9] \n connect slots_10.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[10].wakeup_ports[2].bits.uop.iq_type[0] \n connect slots_10.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[10].wakeup_ports[2].bits.uop.iq_type[1] \n connect slots_10.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[10].wakeup_ports[2].bits.uop.iq_type[2] \n connect slots_10.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[10].wakeup_ports[2].bits.uop.iq_type[3] \n connect slots_10.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[10].wakeup_ports[2].bits.uop.debug_pc \n connect slots_10.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[10].wakeup_ports[2].bits.uop.is_rvc \n connect slots_10.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[10].wakeup_ports[2].bits.uop.debug_inst \n connect slots_10.io.wakeup_ports[2].bits.uop.inst, issue_slots[10].wakeup_ports[2].bits.uop.inst \n connect slots_10.io.wakeup_ports[2].valid, issue_slots[10].wakeup_ports[2].valid \n connect slots_10.io.wakeup_ports[3].bits.rebusy, issue_slots[10].wakeup_ports[3].bits.rebusy \n connect slots_10.io.wakeup_ports[3].bits.speculative_mask, issue_slots[10].wakeup_ports[3].bits.speculative_mask \n connect slots_10.io.wakeup_ports[3].bits.bypassable, issue_slots[10].wakeup_ports[3].bits.bypassable \n connect slots_10.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[10].wakeup_ports[3].bits.uop.debug_tsrc \n connect slots_10.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[10].wakeup_ports[3].bits.uop.debug_fsrc \n connect slots_10.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[10].wakeup_ports[3].bits.uop.bp_xcpt_if \n connect slots_10.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[10].wakeup_ports[3].bits.uop.bp_debug_if \n connect slots_10.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[10].wakeup_ports[3].bits.uop.xcpt_ma_if \n connect slots_10.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[10].wakeup_ports[3].bits.uop.xcpt_ae_if \n connect slots_10.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[10].wakeup_ports[3].bits.uop.xcpt_pf_if \n connect slots_10.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[10].wakeup_ports[3].bits.uop.fp_typ \n connect slots_10.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[10].wakeup_ports[3].bits.uop.fp_rm \n connect slots_10.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[10].wakeup_ports[3].bits.uop.fp_val \n connect slots_10.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[10].wakeup_ports[3].bits.uop.fcn_op \n connect slots_10.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[10].wakeup_ports[3].bits.uop.fcn_dw \n connect slots_10.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[10].wakeup_ports[3].bits.uop.frs3_en \n connect slots_10.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[10].wakeup_ports[3].bits.uop.lrs2_rtype \n connect slots_10.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[10].wakeup_ports[3].bits.uop.lrs1_rtype \n connect slots_10.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[10].wakeup_ports[3].bits.uop.dst_rtype \n connect slots_10.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[10].wakeup_ports[3].bits.uop.lrs3 \n connect slots_10.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[10].wakeup_ports[3].bits.uop.lrs2 \n connect slots_10.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[10].wakeup_ports[3].bits.uop.lrs1 \n connect slots_10.io.wakeup_ports[3].bits.uop.ldst, issue_slots[10].wakeup_ports[3].bits.uop.ldst \n connect slots_10.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[10].wakeup_ports[3].bits.uop.ldst_is_rs1 \n connect slots_10.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[10].wakeup_ports[3].bits.uop.csr_cmd \n connect slots_10.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[10].wakeup_ports[3].bits.uop.flush_on_commit \n connect slots_10.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[10].wakeup_ports[3].bits.uop.is_unique \n connect slots_10.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[10].wakeup_ports[3].bits.uop.uses_stq \n connect slots_10.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[10].wakeup_ports[3].bits.uop.uses_ldq \n connect slots_10.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[10].wakeup_ports[3].bits.uop.mem_signed \n connect slots_10.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[10].wakeup_ports[3].bits.uop.mem_size \n connect slots_10.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[10].wakeup_ports[3].bits.uop.mem_cmd \n connect slots_10.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[10].wakeup_ports[3].bits.uop.exc_cause \n connect slots_10.io.wakeup_ports[3].bits.uop.exception, issue_slots[10].wakeup_ports[3].bits.uop.exception \n connect slots_10.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[10].wakeup_ports[3].bits.uop.stale_pdst \n connect slots_10.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[10].wakeup_ports[3].bits.uop.ppred_busy \n connect slots_10.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[10].wakeup_ports[3].bits.uop.prs3_busy \n connect slots_10.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[10].wakeup_ports[3].bits.uop.prs2_busy \n connect slots_10.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[10].wakeup_ports[3].bits.uop.prs1_busy \n connect slots_10.io.wakeup_ports[3].bits.uop.ppred, issue_slots[10].wakeup_ports[3].bits.uop.ppred \n connect slots_10.io.wakeup_ports[3].bits.uop.prs3, issue_slots[10].wakeup_ports[3].bits.uop.prs3 \n connect slots_10.io.wakeup_ports[3].bits.uop.prs2, issue_slots[10].wakeup_ports[3].bits.uop.prs2 \n connect slots_10.io.wakeup_ports[3].bits.uop.prs1, issue_slots[10].wakeup_ports[3].bits.uop.prs1 \n connect slots_10.io.wakeup_ports[3].bits.uop.pdst, issue_slots[10].wakeup_ports[3].bits.uop.pdst \n connect slots_10.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[10].wakeup_ports[3].bits.uop.rxq_idx \n connect slots_10.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[10].wakeup_ports[3].bits.uop.stq_idx \n connect slots_10.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[10].wakeup_ports[3].bits.uop.ldq_idx \n connect slots_10.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[10].wakeup_ports[3].bits.uop.rob_idx \n connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.vec \n connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.wflags \n connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.sqrt \n connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.div \n connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.fma \n connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe \n connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.toint \n connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.fromint \n connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut \n connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn \n connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.swap23 \n connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.swap12 \n connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.ren3 \n connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.ren2 \n connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.ren1 \n connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.wen \n connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.ldst \n connect slots_10.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[10].wakeup_ports[3].bits.uop.op2_sel \n connect slots_10.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[10].wakeup_ports[3].bits.uop.op1_sel \n connect slots_10.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[10].wakeup_ports[3].bits.uop.imm_packed \n connect slots_10.io.wakeup_ports[3].bits.uop.pimm, issue_slots[10].wakeup_ports[3].bits.uop.pimm \n connect slots_10.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[10].wakeup_ports[3].bits.uop.imm_sel \n connect slots_10.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[10].wakeup_ports[3].bits.uop.imm_rename \n connect slots_10.io.wakeup_ports[3].bits.uop.taken, issue_slots[10].wakeup_ports[3].bits.uop.taken \n connect slots_10.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[10].wakeup_ports[3].bits.uop.pc_lob \n connect slots_10.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[10].wakeup_ports[3].bits.uop.edge_inst \n connect slots_10.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[10].wakeup_ports[3].bits.uop.ftq_idx \n connect slots_10.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[10].wakeup_ports[3].bits.uop.is_mov \n connect slots_10.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[10].wakeup_ports[3].bits.uop.is_rocc \n connect slots_10.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[10].wakeup_ports[3].bits.uop.is_sys_pc2epc \n connect slots_10.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[10].wakeup_ports[3].bits.uop.is_eret \n connect slots_10.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[10].wakeup_ports[3].bits.uop.is_amo \n connect slots_10.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[10].wakeup_ports[3].bits.uop.is_sfence \n connect slots_10.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[10].wakeup_ports[3].bits.uop.is_fencei \n connect slots_10.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[10].wakeup_ports[3].bits.uop.is_fence \n connect slots_10.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[10].wakeup_ports[3].bits.uop.is_sfb \n connect slots_10.io.wakeup_ports[3].bits.uop.br_type, issue_slots[10].wakeup_ports[3].bits.uop.br_type \n connect slots_10.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[10].wakeup_ports[3].bits.uop.br_tag \n connect slots_10.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[10].wakeup_ports[3].bits.uop.br_mask \n connect slots_10.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[10].wakeup_ports[3].bits.uop.dis_col_sel \n connect slots_10.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[10].wakeup_ports[3].bits.uop.iw_p3_bypass_hint \n connect slots_10.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[10].wakeup_ports[3].bits.uop.iw_p2_bypass_hint \n connect slots_10.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[10].wakeup_ports[3].bits.uop.iw_p1_bypass_hint \n connect slots_10.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[10].wakeup_ports[3].bits.uop.iw_p2_speculative_child \n connect slots_10.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[10].wakeup_ports[3].bits.uop.iw_p1_speculative_child \n connect slots_10.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[10].wakeup_ports[3].bits.uop.iw_issued_partial_dgen \n connect slots_10.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[10].wakeup_ports[3].bits.uop.iw_issued_partial_agen \n connect slots_10.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[10].wakeup_ports[3].bits.uop.iw_issued \n connect slots_10.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[10].wakeup_ports[3].bits.uop.fu_code[0] \n connect slots_10.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[10].wakeup_ports[3].bits.uop.fu_code[1] \n connect slots_10.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[10].wakeup_ports[3].bits.uop.fu_code[2] \n connect slots_10.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[10].wakeup_ports[3].bits.uop.fu_code[3] \n connect slots_10.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[10].wakeup_ports[3].bits.uop.fu_code[4] \n connect slots_10.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[10].wakeup_ports[3].bits.uop.fu_code[5] \n connect slots_10.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[10].wakeup_ports[3].bits.uop.fu_code[6] \n connect slots_10.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[10].wakeup_ports[3].bits.uop.fu_code[7] \n connect slots_10.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[10].wakeup_ports[3].bits.uop.fu_code[8] \n connect slots_10.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[10].wakeup_ports[3].bits.uop.fu_code[9] \n connect slots_10.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[10].wakeup_ports[3].bits.uop.iq_type[0] \n connect slots_10.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[10].wakeup_ports[3].bits.uop.iq_type[1] \n connect slots_10.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[10].wakeup_ports[3].bits.uop.iq_type[2] \n connect slots_10.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[10].wakeup_ports[3].bits.uop.iq_type[3] \n connect slots_10.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[10].wakeup_ports[3].bits.uop.debug_pc \n connect slots_10.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[10].wakeup_ports[3].bits.uop.is_rvc \n connect slots_10.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[10].wakeup_ports[3].bits.uop.debug_inst \n connect slots_10.io.wakeup_ports[3].bits.uop.inst, issue_slots[10].wakeup_ports[3].bits.uop.inst \n connect slots_10.io.wakeup_ports[3].valid, issue_slots[10].wakeup_ports[3].valid \n connect slots_10.io.squash_grant, issue_slots[10].squash_grant \n connect slots_10.io.clear, issue_slots[10].clear \n connect slots_10.io.kill, issue_slots[10].kill \n connect slots_10.io.brupdate.b2.target_offset, issue_slots[10].brupdate.b2.target_offset \n connect slots_10.io.brupdate.b2.jalr_target, issue_slots[10].brupdate.b2.jalr_target \n connect slots_10.io.brupdate.b2.pc_sel, issue_slots[10].brupdate.b2.pc_sel \n connect slots_10.io.brupdate.b2.cfi_type, issue_slots[10].brupdate.b2.cfi_type \n connect slots_10.io.brupdate.b2.taken, issue_slots[10].brupdate.b2.taken \n connect slots_10.io.brupdate.b2.mispredict, issue_slots[10].brupdate.b2.mispredict \n connect slots_10.io.brupdate.b2.uop.debug_tsrc, issue_slots[10].brupdate.b2.uop.debug_tsrc \n connect slots_10.io.brupdate.b2.uop.debug_fsrc, issue_slots[10].brupdate.b2.uop.debug_fsrc \n connect slots_10.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[10].brupdate.b2.uop.bp_xcpt_if \n connect slots_10.io.brupdate.b2.uop.bp_debug_if, issue_slots[10].brupdate.b2.uop.bp_debug_if \n connect slots_10.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[10].brupdate.b2.uop.xcpt_ma_if \n connect slots_10.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[10].brupdate.b2.uop.xcpt_ae_if \n connect slots_10.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[10].brupdate.b2.uop.xcpt_pf_if \n connect slots_10.io.brupdate.b2.uop.fp_typ, issue_slots[10].brupdate.b2.uop.fp_typ \n connect slots_10.io.brupdate.b2.uop.fp_rm, issue_slots[10].brupdate.b2.uop.fp_rm \n connect slots_10.io.brupdate.b2.uop.fp_val, issue_slots[10].brupdate.b2.uop.fp_val \n connect slots_10.io.brupdate.b2.uop.fcn_op, issue_slots[10].brupdate.b2.uop.fcn_op \n connect slots_10.io.brupdate.b2.uop.fcn_dw, issue_slots[10].brupdate.b2.uop.fcn_dw \n connect slots_10.io.brupdate.b2.uop.frs3_en, issue_slots[10].brupdate.b2.uop.frs3_en \n connect slots_10.io.brupdate.b2.uop.lrs2_rtype, issue_slots[10].brupdate.b2.uop.lrs2_rtype \n connect slots_10.io.brupdate.b2.uop.lrs1_rtype, issue_slots[10].brupdate.b2.uop.lrs1_rtype \n connect slots_10.io.brupdate.b2.uop.dst_rtype, issue_slots[10].brupdate.b2.uop.dst_rtype \n connect slots_10.io.brupdate.b2.uop.lrs3, issue_slots[10].brupdate.b2.uop.lrs3 \n connect slots_10.io.brupdate.b2.uop.lrs2, issue_slots[10].brupdate.b2.uop.lrs2 \n connect slots_10.io.brupdate.b2.uop.lrs1, issue_slots[10].brupdate.b2.uop.lrs1 \n connect slots_10.io.brupdate.b2.uop.ldst, issue_slots[10].brupdate.b2.uop.ldst \n connect slots_10.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[10].brupdate.b2.uop.ldst_is_rs1 \n connect slots_10.io.brupdate.b2.uop.csr_cmd, issue_slots[10].brupdate.b2.uop.csr_cmd \n connect slots_10.io.brupdate.b2.uop.flush_on_commit, issue_slots[10].brupdate.b2.uop.flush_on_commit \n connect slots_10.io.brupdate.b2.uop.is_unique, issue_slots[10].brupdate.b2.uop.is_unique \n connect slots_10.io.brupdate.b2.uop.uses_stq, issue_slots[10].brupdate.b2.uop.uses_stq \n connect slots_10.io.brupdate.b2.uop.uses_ldq, issue_slots[10].brupdate.b2.uop.uses_ldq \n connect slots_10.io.brupdate.b2.uop.mem_signed, issue_slots[10].brupdate.b2.uop.mem_signed \n connect slots_10.io.brupdate.b2.uop.mem_size, issue_slots[10].brupdate.b2.uop.mem_size \n connect slots_10.io.brupdate.b2.uop.mem_cmd, issue_slots[10].brupdate.b2.uop.mem_cmd \n connect slots_10.io.brupdate.b2.uop.exc_cause, issue_slots[10].brupdate.b2.uop.exc_cause \n connect slots_10.io.brupdate.b2.uop.exception, issue_slots[10].brupdate.b2.uop.exception \n connect slots_10.io.brupdate.b2.uop.stale_pdst, issue_slots[10].brupdate.b2.uop.stale_pdst \n connect slots_10.io.brupdate.b2.uop.ppred_busy, issue_slots[10].brupdate.b2.uop.ppred_busy \n connect slots_10.io.brupdate.b2.uop.prs3_busy, issue_slots[10].brupdate.b2.uop.prs3_busy \n connect slots_10.io.brupdate.b2.uop.prs2_busy, issue_slots[10].brupdate.b2.uop.prs2_busy \n connect slots_10.io.brupdate.b2.uop.prs1_busy, issue_slots[10].brupdate.b2.uop.prs1_busy \n connect slots_10.io.brupdate.b2.uop.ppred, issue_slots[10].brupdate.b2.uop.ppred \n connect slots_10.io.brupdate.b2.uop.prs3, issue_slots[10].brupdate.b2.uop.prs3 \n connect slots_10.io.brupdate.b2.uop.prs2, issue_slots[10].brupdate.b2.uop.prs2 \n connect slots_10.io.brupdate.b2.uop.prs1, issue_slots[10].brupdate.b2.uop.prs1 \n connect slots_10.io.brupdate.b2.uop.pdst, issue_slots[10].brupdate.b2.uop.pdst \n connect slots_10.io.brupdate.b2.uop.rxq_idx, issue_slots[10].brupdate.b2.uop.rxq_idx \n connect slots_10.io.brupdate.b2.uop.stq_idx, issue_slots[10].brupdate.b2.uop.stq_idx \n connect slots_10.io.brupdate.b2.uop.ldq_idx, issue_slots[10].brupdate.b2.uop.ldq_idx \n connect slots_10.io.brupdate.b2.uop.rob_idx, issue_slots[10].brupdate.b2.uop.rob_idx \n connect slots_10.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[10].brupdate.b2.uop.fp_ctrl.vec \n connect slots_10.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[10].brupdate.b2.uop.fp_ctrl.wflags \n connect slots_10.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[10].brupdate.b2.uop.fp_ctrl.sqrt \n connect slots_10.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[10].brupdate.b2.uop.fp_ctrl.div \n connect slots_10.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[10].brupdate.b2.uop.fp_ctrl.fma \n connect slots_10.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[10].brupdate.b2.uop.fp_ctrl.fastpipe \n connect slots_10.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[10].brupdate.b2.uop.fp_ctrl.toint \n connect slots_10.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[10].brupdate.b2.uop.fp_ctrl.fromint \n connect slots_10.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[10].brupdate.b2.uop.fp_ctrl.typeTagOut \n connect slots_10.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[10].brupdate.b2.uop.fp_ctrl.typeTagIn \n connect slots_10.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[10].brupdate.b2.uop.fp_ctrl.swap23 \n connect slots_10.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[10].brupdate.b2.uop.fp_ctrl.swap12 \n connect slots_10.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[10].brupdate.b2.uop.fp_ctrl.ren3 \n connect slots_10.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[10].brupdate.b2.uop.fp_ctrl.ren2 \n connect slots_10.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[10].brupdate.b2.uop.fp_ctrl.ren1 \n connect slots_10.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[10].brupdate.b2.uop.fp_ctrl.wen \n connect slots_10.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[10].brupdate.b2.uop.fp_ctrl.ldst \n connect slots_10.io.brupdate.b2.uop.op2_sel, issue_slots[10].brupdate.b2.uop.op2_sel \n connect slots_10.io.brupdate.b2.uop.op1_sel, issue_slots[10].brupdate.b2.uop.op1_sel \n connect slots_10.io.brupdate.b2.uop.imm_packed, issue_slots[10].brupdate.b2.uop.imm_packed \n connect slots_10.io.brupdate.b2.uop.pimm, issue_slots[10].brupdate.b2.uop.pimm \n connect slots_10.io.brupdate.b2.uop.imm_sel, issue_slots[10].brupdate.b2.uop.imm_sel \n connect slots_10.io.brupdate.b2.uop.imm_rename, issue_slots[10].brupdate.b2.uop.imm_rename \n connect slots_10.io.brupdate.b2.uop.taken, issue_slots[10].brupdate.b2.uop.taken \n connect slots_10.io.brupdate.b2.uop.pc_lob, issue_slots[10].brupdate.b2.uop.pc_lob \n connect slots_10.io.brupdate.b2.uop.edge_inst, issue_slots[10].brupdate.b2.uop.edge_inst \n connect slots_10.io.brupdate.b2.uop.ftq_idx, issue_slots[10].brupdate.b2.uop.ftq_idx \n connect slots_10.io.brupdate.b2.uop.is_mov, issue_slots[10].brupdate.b2.uop.is_mov \n connect slots_10.io.brupdate.b2.uop.is_rocc, issue_slots[10].brupdate.b2.uop.is_rocc \n connect slots_10.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[10].brupdate.b2.uop.is_sys_pc2epc \n connect slots_10.io.brupdate.b2.uop.is_eret, issue_slots[10].brupdate.b2.uop.is_eret \n connect slots_10.io.brupdate.b2.uop.is_amo, issue_slots[10].brupdate.b2.uop.is_amo \n connect slots_10.io.brupdate.b2.uop.is_sfence, issue_slots[10].brupdate.b2.uop.is_sfence \n connect slots_10.io.brupdate.b2.uop.is_fencei, issue_slots[10].brupdate.b2.uop.is_fencei \n connect slots_10.io.brupdate.b2.uop.is_fence, issue_slots[10].brupdate.b2.uop.is_fence \n connect slots_10.io.brupdate.b2.uop.is_sfb, issue_slots[10].brupdate.b2.uop.is_sfb \n connect slots_10.io.brupdate.b2.uop.br_type, issue_slots[10].brupdate.b2.uop.br_type \n connect slots_10.io.brupdate.b2.uop.br_tag, issue_slots[10].brupdate.b2.uop.br_tag \n connect slots_10.io.brupdate.b2.uop.br_mask, issue_slots[10].brupdate.b2.uop.br_mask \n connect slots_10.io.brupdate.b2.uop.dis_col_sel, issue_slots[10].brupdate.b2.uop.dis_col_sel \n connect slots_10.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[10].brupdate.b2.uop.iw_p3_bypass_hint \n connect slots_10.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[10].brupdate.b2.uop.iw_p2_bypass_hint \n connect slots_10.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[10].brupdate.b2.uop.iw_p1_bypass_hint \n connect slots_10.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[10].brupdate.b2.uop.iw_p2_speculative_child \n connect slots_10.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[10].brupdate.b2.uop.iw_p1_speculative_child \n connect slots_10.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[10].brupdate.b2.uop.iw_issued_partial_dgen \n connect slots_10.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[10].brupdate.b2.uop.iw_issued_partial_agen \n connect slots_10.io.brupdate.b2.uop.iw_issued, issue_slots[10].brupdate.b2.uop.iw_issued \n connect slots_10.io.brupdate.b2.uop.fu_code[0], issue_slots[10].brupdate.b2.uop.fu_code[0] \n connect slots_10.io.brupdate.b2.uop.fu_code[1], issue_slots[10].brupdate.b2.uop.fu_code[1] \n connect slots_10.io.brupdate.b2.uop.fu_code[2], issue_slots[10].brupdate.b2.uop.fu_code[2] \n connect slots_10.io.brupdate.b2.uop.fu_code[3], issue_slots[10].brupdate.b2.uop.fu_code[3] \n connect slots_10.io.brupdate.b2.uop.fu_code[4], issue_slots[10].brupdate.b2.uop.fu_code[4] \n connect slots_10.io.brupdate.b2.uop.fu_code[5], issue_slots[10].brupdate.b2.uop.fu_code[5] \n connect slots_10.io.brupdate.b2.uop.fu_code[6], issue_slots[10].brupdate.b2.uop.fu_code[6] \n connect slots_10.io.brupdate.b2.uop.fu_code[7], issue_slots[10].brupdate.b2.uop.fu_code[7] \n connect slots_10.io.brupdate.b2.uop.fu_code[8], issue_slots[10].brupdate.b2.uop.fu_code[8] \n connect slots_10.io.brupdate.b2.uop.fu_code[9], issue_slots[10].brupdate.b2.uop.fu_code[9] \n connect slots_10.io.brupdate.b2.uop.iq_type[0], issue_slots[10].brupdate.b2.uop.iq_type[0] \n connect slots_10.io.brupdate.b2.uop.iq_type[1], issue_slots[10].brupdate.b2.uop.iq_type[1] \n connect slots_10.io.brupdate.b2.uop.iq_type[2], issue_slots[10].brupdate.b2.uop.iq_type[2] \n connect slots_10.io.brupdate.b2.uop.iq_type[3], issue_slots[10].brupdate.b2.uop.iq_type[3] \n connect slots_10.io.brupdate.b2.uop.debug_pc, issue_slots[10].brupdate.b2.uop.debug_pc \n connect slots_10.io.brupdate.b2.uop.is_rvc, issue_slots[10].brupdate.b2.uop.is_rvc \n connect slots_10.io.brupdate.b2.uop.debug_inst, issue_slots[10].brupdate.b2.uop.debug_inst \n connect slots_10.io.brupdate.b2.uop.inst, issue_slots[10].brupdate.b2.uop.inst \n connect slots_10.io.brupdate.b1.mispredict_mask, issue_slots[10].brupdate.b1.mispredict_mask \n connect slots_10.io.brupdate.b1.resolve_mask, issue_slots[10].brupdate.b1.resolve_mask \n connect issue_slots[10].out_uop.debug_tsrc, slots_10.io.out_uop.debug_tsrc \n connect issue_slots[10].out_uop.debug_fsrc, slots_10.io.out_uop.debug_fsrc \n connect issue_slots[10].out_uop.bp_xcpt_if, slots_10.io.out_uop.bp_xcpt_if \n connect issue_slots[10].out_uop.bp_debug_if, slots_10.io.out_uop.bp_debug_if \n connect issue_slots[10].out_uop.xcpt_ma_if, slots_10.io.out_uop.xcpt_ma_if \n connect issue_slots[10].out_uop.xcpt_ae_if, slots_10.io.out_uop.xcpt_ae_if \n connect issue_slots[10].out_uop.xcpt_pf_if, slots_10.io.out_uop.xcpt_pf_if \n connect issue_slots[10].out_uop.fp_typ, slots_10.io.out_uop.fp_typ \n connect issue_slots[10].out_uop.fp_rm, slots_10.io.out_uop.fp_rm \n connect issue_slots[10].out_uop.fp_val, slots_10.io.out_uop.fp_val \n connect issue_slots[10].out_uop.fcn_op, slots_10.io.out_uop.fcn_op \n connect issue_slots[10].out_uop.fcn_dw, slots_10.io.out_uop.fcn_dw \n connect issue_slots[10].out_uop.frs3_en, slots_10.io.out_uop.frs3_en \n connect issue_slots[10].out_uop.lrs2_rtype, slots_10.io.out_uop.lrs2_rtype \n connect issue_slots[10].out_uop.lrs1_rtype, slots_10.io.out_uop.lrs1_rtype \n connect issue_slots[10].out_uop.dst_rtype, slots_10.io.out_uop.dst_rtype \n connect issue_slots[10].out_uop.lrs3, slots_10.io.out_uop.lrs3 \n connect issue_slots[10].out_uop.lrs2, slots_10.io.out_uop.lrs2 \n connect issue_slots[10].out_uop.lrs1, slots_10.io.out_uop.lrs1 \n connect issue_slots[10].out_uop.ldst, slots_10.io.out_uop.ldst \n connect issue_slots[10].out_uop.ldst_is_rs1, slots_10.io.out_uop.ldst_is_rs1 \n connect issue_slots[10].out_uop.csr_cmd, slots_10.io.out_uop.csr_cmd \n connect issue_slots[10].out_uop.flush_on_commit, slots_10.io.out_uop.flush_on_commit \n connect issue_slots[10].out_uop.is_unique, slots_10.io.out_uop.is_unique \n connect issue_slots[10].out_uop.uses_stq, slots_10.io.out_uop.uses_stq \n connect issue_slots[10].out_uop.uses_ldq, slots_10.io.out_uop.uses_ldq \n connect issue_slots[10].out_uop.mem_signed, slots_10.io.out_uop.mem_signed \n connect issue_slots[10].out_uop.mem_size, slots_10.io.out_uop.mem_size \n connect issue_slots[10].out_uop.mem_cmd, slots_10.io.out_uop.mem_cmd \n connect issue_slots[10].out_uop.exc_cause, slots_10.io.out_uop.exc_cause \n connect issue_slots[10].out_uop.exception, slots_10.io.out_uop.exception \n connect issue_slots[10].out_uop.stale_pdst, slots_10.io.out_uop.stale_pdst \n connect issue_slots[10].out_uop.ppred_busy, slots_10.io.out_uop.ppred_busy \n connect issue_slots[10].out_uop.prs3_busy, slots_10.io.out_uop.prs3_busy \n connect issue_slots[10].out_uop.prs2_busy, slots_10.io.out_uop.prs2_busy \n connect issue_slots[10].out_uop.prs1_busy, slots_10.io.out_uop.prs1_busy \n connect issue_slots[10].out_uop.ppred, slots_10.io.out_uop.ppred \n connect issue_slots[10].out_uop.prs3, slots_10.io.out_uop.prs3 \n connect issue_slots[10].out_uop.prs2, slots_10.io.out_uop.prs2 \n connect issue_slots[10].out_uop.prs1, slots_10.io.out_uop.prs1 \n connect issue_slots[10].out_uop.pdst, slots_10.io.out_uop.pdst \n connect issue_slots[10].out_uop.rxq_idx, slots_10.io.out_uop.rxq_idx \n connect issue_slots[10].out_uop.stq_idx, slots_10.io.out_uop.stq_idx \n connect issue_slots[10].out_uop.ldq_idx, slots_10.io.out_uop.ldq_idx \n connect issue_slots[10].out_uop.rob_idx, slots_10.io.out_uop.rob_idx \n connect issue_slots[10].out_uop.fp_ctrl.vec, slots_10.io.out_uop.fp_ctrl.vec \n connect issue_slots[10].out_uop.fp_ctrl.wflags, slots_10.io.out_uop.fp_ctrl.wflags \n connect issue_slots[10].out_uop.fp_ctrl.sqrt, slots_10.io.out_uop.fp_ctrl.sqrt \n connect issue_slots[10].out_uop.fp_ctrl.div, slots_10.io.out_uop.fp_ctrl.div \n connect issue_slots[10].out_uop.fp_ctrl.fma, slots_10.io.out_uop.fp_ctrl.fma \n connect issue_slots[10].out_uop.fp_ctrl.fastpipe, slots_10.io.out_uop.fp_ctrl.fastpipe \n connect issue_slots[10].out_uop.fp_ctrl.toint, slots_10.io.out_uop.fp_ctrl.toint \n connect issue_slots[10].out_uop.fp_ctrl.fromint, slots_10.io.out_uop.fp_ctrl.fromint \n connect issue_slots[10].out_uop.fp_ctrl.typeTagOut, slots_10.io.out_uop.fp_ctrl.typeTagOut \n connect issue_slots[10].out_uop.fp_ctrl.typeTagIn, slots_10.io.out_uop.fp_ctrl.typeTagIn \n connect issue_slots[10].out_uop.fp_ctrl.swap23, slots_10.io.out_uop.fp_ctrl.swap23 \n connect issue_slots[10].out_uop.fp_ctrl.swap12, slots_10.io.out_uop.fp_ctrl.swap12 \n connect issue_slots[10].out_uop.fp_ctrl.ren3, slots_10.io.out_uop.fp_ctrl.ren3 \n connect issue_slots[10].out_uop.fp_ctrl.ren2, slots_10.io.out_uop.fp_ctrl.ren2 \n connect issue_slots[10].out_uop.fp_ctrl.ren1, slots_10.io.out_uop.fp_ctrl.ren1 \n connect issue_slots[10].out_uop.fp_ctrl.wen, slots_10.io.out_uop.fp_ctrl.wen \n connect issue_slots[10].out_uop.fp_ctrl.ldst, slots_10.io.out_uop.fp_ctrl.ldst \n connect issue_slots[10].out_uop.op2_sel, slots_10.io.out_uop.op2_sel \n connect issue_slots[10].out_uop.op1_sel, slots_10.io.out_uop.op1_sel \n connect issue_slots[10].out_uop.imm_packed, slots_10.io.out_uop.imm_packed \n connect issue_slots[10].out_uop.pimm, slots_10.io.out_uop.pimm \n connect issue_slots[10].out_uop.imm_sel, slots_10.io.out_uop.imm_sel \n connect issue_slots[10].out_uop.imm_rename, slots_10.io.out_uop.imm_rename \n connect issue_slots[10].out_uop.taken, slots_10.io.out_uop.taken \n connect issue_slots[10].out_uop.pc_lob, slots_10.io.out_uop.pc_lob \n connect issue_slots[10].out_uop.edge_inst, slots_10.io.out_uop.edge_inst \n connect issue_slots[10].out_uop.ftq_idx, slots_10.io.out_uop.ftq_idx \n connect issue_slots[10].out_uop.is_mov, slots_10.io.out_uop.is_mov \n connect issue_slots[10].out_uop.is_rocc, slots_10.io.out_uop.is_rocc \n connect issue_slots[10].out_uop.is_sys_pc2epc, slots_10.io.out_uop.is_sys_pc2epc \n connect issue_slots[10].out_uop.is_eret, slots_10.io.out_uop.is_eret \n connect issue_slots[10].out_uop.is_amo, slots_10.io.out_uop.is_amo \n connect issue_slots[10].out_uop.is_sfence, slots_10.io.out_uop.is_sfence \n connect issue_slots[10].out_uop.is_fencei, slots_10.io.out_uop.is_fencei \n connect issue_slots[10].out_uop.is_fence, slots_10.io.out_uop.is_fence \n connect issue_slots[10].out_uop.is_sfb, slots_10.io.out_uop.is_sfb \n connect issue_slots[10].out_uop.br_type, slots_10.io.out_uop.br_type \n connect issue_slots[10].out_uop.br_tag, slots_10.io.out_uop.br_tag \n connect issue_slots[10].out_uop.br_mask, slots_10.io.out_uop.br_mask \n connect issue_slots[10].out_uop.dis_col_sel, slots_10.io.out_uop.dis_col_sel \n connect issue_slots[10].out_uop.iw_p3_bypass_hint, slots_10.io.out_uop.iw_p3_bypass_hint \n connect issue_slots[10].out_uop.iw_p2_bypass_hint, slots_10.io.out_uop.iw_p2_bypass_hint \n connect issue_slots[10].out_uop.iw_p1_bypass_hint, slots_10.io.out_uop.iw_p1_bypass_hint \n connect issue_slots[10].out_uop.iw_p2_speculative_child, slots_10.io.out_uop.iw_p2_speculative_child \n connect issue_slots[10].out_uop.iw_p1_speculative_child, slots_10.io.out_uop.iw_p1_speculative_child \n connect issue_slots[10].out_uop.iw_issued_partial_dgen, slots_10.io.out_uop.iw_issued_partial_dgen \n connect issue_slots[10].out_uop.iw_issued_partial_agen, slots_10.io.out_uop.iw_issued_partial_agen \n connect issue_slots[10].out_uop.iw_issued, slots_10.io.out_uop.iw_issued \n connect issue_slots[10].out_uop.fu_code[0], slots_10.io.out_uop.fu_code[0] \n connect issue_slots[10].out_uop.fu_code[1], slots_10.io.out_uop.fu_code[1] \n connect issue_slots[10].out_uop.fu_code[2], slots_10.io.out_uop.fu_code[2] \n connect issue_slots[10].out_uop.fu_code[3], slots_10.io.out_uop.fu_code[3] \n connect issue_slots[10].out_uop.fu_code[4], slots_10.io.out_uop.fu_code[4] \n connect issue_slots[10].out_uop.fu_code[5], slots_10.io.out_uop.fu_code[5] \n connect issue_slots[10].out_uop.fu_code[6], slots_10.io.out_uop.fu_code[6] \n connect issue_slots[10].out_uop.fu_code[7], slots_10.io.out_uop.fu_code[7] \n connect issue_slots[10].out_uop.fu_code[8], slots_10.io.out_uop.fu_code[8] \n connect issue_slots[10].out_uop.fu_code[9], slots_10.io.out_uop.fu_code[9] \n connect issue_slots[10].out_uop.iq_type[0], slots_10.io.out_uop.iq_type[0] \n connect issue_slots[10].out_uop.iq_type[1], slots_10.io.out_uop.iq_type[1] \n connect issue_slots[10].out_uop.iq_type[2], slots_10.io.out_uop.iq_type[2] \n connect issue_slots[10].out_uop.iq_type[3], slots_10.io.out_uop.iq_type[3] \n connect issue_slots[10].out_uop.debug_pc, slots_10.io.out_uop.debug_pc \n connect issue_slots[10].out_uop.is_rvc, slots_10.io.out_uop.is_rvc \n connect issue_slots[10].out_uop.debug_inst, slots_10.io.out_uop.debug_inst \n connect issue_slots[10].out_uop.inst, slots_10.io.out_uop.inst \n connect slots_10.io.in_uop.bits.debug_tsrc, issue_slots[10].in_uop.bits.debug_tsrc \n connect slots_10.io.in_uop.bits.debug_fsrc, issue_slots[10].in_uop.bits.debug_fsrc \n connect slots_10.io.in_uop.bits.bp_xcpt_if, issue_slots[10].in_uop.bits.bp_xcpt_if \n connect slots_10.io.in_uop.bits.bp_debug_if, issue_slots[10].in_uop.bits.bp_debug_if \n connect slots_10.io.in_uop.bits.xcpt_ma_if, issue_slots[10].in_uop.bits.xcpt_ma_if \n connect slots_10.io.in_uop.bits.xcpt_ae_if, issue_slots[10].in_uop.bits.xcpt_ae_if \n connect slots_10.io.in_uop.bits.xcpt_pf_if, issue_slots[10].in_uop.bits.xcpt_pf_if \n connect slots_10.io.in_uop.bits.fp_typ, issue_slots[10].in_uop.bits.fp_typ \n connect slots_10.io.in_uop.bits.fp_rm, issue_slots[10].in_uop.bits.fp_rm \n connect slots_10.io.in_uop.bits.fp_val, issue_slots[10].in_uop.bits.fp_val \n connect slots_10.io.in_uop.bits.fcn_op, issue_slots[10].in_uop.bits.fcn_op \n connect slots_10.io.in_uop.bits.fcn_dw, issue_slots[10].in_uop.bits.fcn_dw \n connect slots_10.io.in_uop.bits.frs3_en, issue_slots[10].in_uop.bits.frs3_en \n connect slots_10.io.in_uop.bits.lrs2_rtype, issue_slots[10].in_uop.bits.lrs2_rtype \n connect slots_10.io.in_uop.bits.lrs1_rtype, issue_slots[10].in_uop.bits.lrs1_rtype \n connect slots_10.io.in_uop.bits.dst_rtype, issue_slots[10].in_uop.bits.dst_rtype \n connect slots_10.io.in_uop.bits.lrs3, issue_slots[10].in_uop.bits.lrs3 \n connect slots_10.io.in_uop.bits.lrs2, issue_slots[10].in_uop.bits.lrs2 \n connect slots_10.io.in_uop.bits.lrs1, issue_slots[10].in_uop.bits.lrs1 \n connect slots_10.io.in_uop.bits.ldst, issue_slots[10].in_uop.bits.ldst \n connect slots_10.io.in_uop.bits.ldst_is_rs1, issue_slots[10].in_uop.bits.ldst_is_rs1 \n connect slots_10.io.in_uop.bits.csr_cmd, issue_slots[10].in_uop.bits.csr_cmd \n connect slots_10.io.in_uop.bits.flush_on_commit, issue_slots[10].in_uop.bits.flush_on_commit \n connect slots_10.io.in_uop.bits.is_unique, issue_slots[10].in_uop.bits.is_unique \n connect slots_10.io.in_uop.bits.uses_stq, issue_slots[10].in_uop.bits.uses_stq \n connect slots_10.io.in_uop.bits.uses_ldq, issue_slots[10].in_uop.bits.uses_ldq \n connect slots_10.io.in_uop.bits.mem_signed, issue_slots[10].in_uop.bits.mem_signed \n connect slots_10.io.in_uop.bits.mem_size, issue_slots[10].in_uop.bits.mem_size \n connect slots_10.io.in_uop.bits.mem_cmd, issue_slots[10].in_uop.bits.mem_cmd \n connect slots_10.io.in_uop.bits.exc_cause, issue_slots[10].in_uop.bits.exc_cause \n connect slots_10.io.in_uop.bits.exception, issue_slots[10].in_uop.bits.exception \n connect slots_10.io.in_uop.bits.stale_pdst, issue_slots[10].in_uop.bits.stale_pdst \n connect slots_10.io.in_uop.bits.ppred_busy, issue_slots[10].in_uop.bits.ppred_busy \n connect slots_10.io.in_uop.bits.prs3_busy, issue_slots[10].in_uop.bits.prs3_busy \n connect slots_10.io.in_uop.bits.prs2_busy, issue_slots[10].in_uop.bits.prs2_busy \n connect slots_10.io.in_uop.bits.prs1_busy, issue_slots[10].in_uop.bits.prs1_busy \n connect slots_10.io.in_uop.bits.ppred, issue_slots[10].in_uop.bits.ppred \n connect slots_10.io.in_uop.bits.prs3, issue_slots[10].in_uop.bits.prs3 \n connect slots_10.io.in_uop.bits.prs2, issue_slots[10].in_uop.bits.prs2 \n connect slots_10.io.in_uop.bits.prs1, issue_slots[10].in_uop.bits.prs1 \n connect slots_10.io.in_uop.bits.pdst, issue_slots[10].in_uop.bits.pdst \n connect slots_10.io.in_uop.bits.rxq_idx, issue_slots[10].in_uop.bits.rxq_idx \n connect slots_10.io.in_uop.bits.stq_idx, issue_slots[10].in_uop.bits.stq_idx \n connect slots_10.io.in_uop.bits.ldq_idx, issue_slots[10].in_uop.bits.ldq_idx \n connect slots_10.io.in_uop.bits.rob_idx, issue_slots[10].in_uop.bits.rob_idx \n connect slots_10.io.in_uop.bits.fp_ctrl.vec, issue_slots[10].in_uop.bits.fp_ctrl.vec \n connect slots_10.io.in_uop.bits.fp_ctrl.wflags, issue_slots[10].in_uop.bits.fp_ctrl.wflags \n connect slots_10.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[10].in_uop.bits.fp_ctrl.sqrt \n connect slots_10.io.in_uop.bits.fp_ctrl.div, issue_slots[10].in_uop.bits.fp_ctrl.div \n connect slots_10.io.in_uop.bits.fp_ctrl.fma, issue_slots[10].in_uop.bits.fp_ctrl.fma \n connect slots_10.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[10].in_uop.bits.fp_ctrl.fastpipe \n connect slots_10.io.in_uop.bits.fp_ctrl.toint, issue_slots[10].in_uop.bits.fp_ctrl.toint \n connect slots_10.io.in_uop.bits.fp_ctrl.fromint, issue_slots[10].in_uop.bits.fp_ctrl.fromint \n connect slots_10.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[10].in_uop.bits.fp_ctrl.typeTagOut \n connect slots_10.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[10].in_uop.bits.fp_ctrl.typeTagIn \n connect slots_10.io.in_uop.bits.fp_ctrl.swap23, issue_slots[10].in_uop.bits.fp_ctrl.swap23 \n connect slots_10.io.in_uop.bits.fp_ctrl.swap12, issue_slots[10].in_uop.bits.fp_ctrl.swap12 \n connect slots_10.io.in_uop.bits.fp_ctrl.ren3, issue_slots[10].in_uop.bits.fp_ctrl.ren3 \n connect slots_10.io.in_uop.bits.fp_ctrl.ren2, issue_slots[10].in_uop.bits.fp_ctrl.ren2 \n connect slots_10.io.in_uop.bits.fp_ctrl.ren1, issue_slots[10].in_uop.bits.fp_ctrl.ren1 \n connect slots_10.io.in_uop.bits.fp_ctrl.wen, issue_slots[10].in_uop.bits.fp_ctrl.wen \n connect slots_10.io.in_uop.bits.fp_ctrl.ldst, issue_slots[10].in_uop.bits.fp_ctrl.ldst \n connect slots_10.io.in_uop.bits.op2_sel, issue_slots[10].in_uop.bits.op2_sel \n connect slots_10.io.in_uop.bits.op1_sel, issue_slots[10].in_uop.bits.op1_sel \n connect slots_10.io.in_uop.bits.imm_packed, issue_slots[10].in_uop.bits.imm_packed \n connect slots_10.io.in_uop.bits.pimm, issue_slots[10].in_uop.bits.pimm \n connect slots_10.io.in_uop.bits.imm_sel, issue_slots[10].in_uop.bits.imm_sel \n connect slots_10.io.in_uop.bits.imm_rename, issue_slots[10].in_uop.bits.imm_rename \n connect slots_10.io.in_uop.bits.taken, issue_slots[10].in_uop.bits.taken \n connect slots_10.io.in_uop.bits.pc_lob, issue_slots[10].in_uop.bits.pc_lob \n connect slots_10.io.in_uop.bits.edge_inst, issue_slots[10].in_uop.bits.edge_inst \n connect slots_10.io.in_uop.bits.ftq_idx, issue_slots[10].in_uop.bits.ftq_idx \n connect slots_10.io.in_uop.bits.is_mov, issue_slots[10].in_uop.bits.is_mov \n connect slots_10.io.in_uop.bits.is_rocc, issue_slots[10].in_uop.bits.is_rocc \n connect slots_10.io.in_uop.bits.is_sys_pc2epc, issue_slots[10].in_uop.bits.is_sys_pc2epc \n connect slots_10.io.in_uop.bits.is_eret, issue_slots[10].in_uop.bits.is_eret \n connect slots_10.io.in_uop.bits.is_amo, issue_slots[10].in_uop.bits.is_amo \n connect slots_10.io.in_uop.bits.is_sfence, issue_slots[10].in_uop.bits.is_sfence \n connect slots_10.io.in_uop.bits.is_fencei, issue_slots[10].in_uop.bits.is_fencei \n connect slots_10.io.in_uop.bits.is_fence, issue_slots[10].in_uop.bits.is_fence \n connect slots_10.io.in_uop.bits.is_sfb, issue_slots[10].in_uop.bits.is_sfb \n connect slots_10.io.in_uop.bits.br_type, issue_slots[10].in_uop.bits.br_type \n connect slots_10.io.in_uop.bits.br_tag, issue_slots[10].in_uop.bits.br_tag \n connect slots_10.io.in_uop.bits.br_mask, issue_slots[10].in_uop.bits.br_mask \n connect slots_10.io.in_uop.bits.dis_col_sel, issue_slots[10].in_uop.bits.dis_col_sel \n connect slots_10.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[10].in_uop.bits.iw_p3_bypass_hint \n connect slots_10.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[10].in_uop.bits.iw_p2_bypass_hint \n connect slots_10.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[10].in_uop.bits.iw_p1_bypass_hint \n connect slots_10.io.in_uop.bits.iw_p2_speculative_child, issue_slots[10].in_uop.bits.iw_p2_speculative_child \n connect slots_10.io.in_uop.bits.iw_p1_speculative_child, issue_slots[10].in_uop.bits.iw_p1_speculative_child \n connect slots_10.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[10].in_uop.bits.iw_issued_partial_dgen \n connect slots_10.io.in_uop.bits.iw_issued_partial_agen, issue_slots[10].in_uop.bits.iw_issued_partial_agen \n connect slots_10.io.in_uop.bits.iw_issued, issue_slots[10].in_uop.bits.iw_issued \n connect slots_10.io.in_uop.bits.fu_code[0], issue_slots[10].in_uop.bits.fu_code[0] \n connect slots_10.io.in_uop.bits.fu_code[1], issue_slots[10].in_uop.bits.fu_code[1] \n connect slots_10.io.in_uop.bits.fu_code[2], issue_slots[10].in_uop.bits.fu_code[2] \n connect slots_10.io.in_uop.bits.fu_code[3], issue_slots[10].in_uop.bits.fu_code[3] \n connect slots_10.io.in_uop.bits.fu_code[4], issue_slots[10].in_uop.bits.fu_code[4] \n connect slots_10.io.in_uop.bits.fu_code[5], issue_slots[10].in_uop.bits.fu_code[5] \n connect slots_10.io.in_uop.bits.fu_code[6], issue_slots[10].in_uop.bits.fu_code[6] \n connect slots_10.io.in_uop.bits.fu_code[7], issue_slots[10].in_uop.bits.fu_code[7] \n connect slots_10.io.in_uop.bits.fu_code[8], issue_slots[10].in_uop.bits.fu_code[8] \n connect slots_10.io.in_uop.bits.fu_code[9], issue_slots[10].in_uop.bits.fu_code[9] \n connect slots_10.io.in_uop.bits.iq_type[0], issue_slots[10].in_uop.bits.iq_type[0] \n connect slots_10.io.in_uop.bits.iq_type[1], issue_slots[10].in_uop.bits.iq_type[1] \n connect slots_10.io.in_uop.bits.iq_type[2], issue_slots[10].in_uop.bits.iq_type[2] \n connect slots_10.io.in_uop.bits.iq_type[3], issue_slots[10].in_uop.bits.iq_type[3] \n connect slots_10.io.in_uop.bits.debug_pc, issue_slots[10].in_uop.bits.debug_pc \n connect slots_10.io.in_uop.bits.is_rvc, issue_slots[10].in_uop.bits.is_rvc \n connect slots_10.io.in_uop.bits.debug_inst, issue_slots[10].in_uop.bits.debug_inst \n connect slots_10.io.in_uop.bits.inst, issue_slots[10].in_uop.bits.inst \n connect slots_10.io.in_uop.valid, issue_slots[10].in_uop.valid \n connect issue_slots[10].iss_uop.debug_tsrc, slots_10.io.iss_uop.debug_tsrc \n connect issue_slots[10].iss_uop.debug_fsrc, slots_10.io.iss_uop.debug_fsrc \n connect issue_slots[10].iss_uop.bp_xcpt_if, slots_10.io.iss_uop.bp_xcpt_if \n connect issue_slots[10].iss_uop.bp_debug_if, slots_10.io.iss_uop.bp_debug_if \n connect issue_slots[10].iss_uop.xcpt_ma_if, slots_10.io.iss_uop.xcpt_ma_if \n connect issue_slots[10].iss_uop.xcpt_ae_if, slots_10.io.iss_uop.xcpt_ae_if \n connect issue_slots[10].iss_uop.xcpt_pf_if, slots_10.io.iss_uop.xcpt_pf_if \n connect issue_slots[10].iss_uop.fp_typ, slots_10.io.iss_uop.fp_typ \n connect issue_slots[10].iss_uop.fp_rm, slots_10.io.iss_uop.fp_rm \n connect issue_slots[10].iss_uop.fp_val, slots_10.io.iss_uop.fp_val \n connect issue_slots[10].iss_uop.fcn_op, slots_10.io.iss_uop.fcn_op \n connect issue_slots[10].iss_uop.fcn_dw, slots_10.io.iss_uop.fcn_dw \n connect issue_slots[10].iss_uop.frs3_en, slots_10.io.iss_uop.frs3_en \n connect issue_slots[10].iss_uop.lrs2_rtype, slots_10.io.iss_uop.lrs2_rtype \n connect issue_slots[10].iss_uop.lrs1_rtype, slots_10.io.iss_uop.lrs1_rtype \n connect issue_slots[10].iss_uop.dst_rtype, slots_10.io.iss_uop.dst_rtype \n connect issue_slots[10].iss_uop.lrs3, slots_10.io.iss_uop.lrs3 \n connect issue_slots[10].iss_uop.lrs2, slots_10.io.iss_uop.lrs2 \n connect issue_slots[10].iss_uop.lrs1, slots_10.io.iss_uop.lrs1 \n connect issue_slots[10].iss_uop.ldst, slots_10.io.iss_uop.ldst \n connect issue_slots[10].iss_uop.ldst_is_rs1, slots_10.io.iss_uop.ldst_is_rs1 \n connect issue_slots[10].iss_uop.csr_cmd, slots_10.io.iss_uop.csr_cmd \n connect issue_slots[10].iss_uop.flush_on_commit, slots_10.io.iss_uop.flush_on_commit \n connect issue_slots[10].iss_uop.is_unique, slots_10.io.iss_uop.is_unique \n connect issue_slots[10].iss_uop.uses_stq, slots_10.io.iss_uop.uses_stq \n connect issue_slots[10].iss_uop.uses_ldq, slots_10.io.iss_uop.uses_ldq \n connect issue_slots[10].iss_uop.mem_signed, slots_10.io.iss_uop.mem_signed \n connect issue_slots[10].iss_uop.mem_size, slots_10.io.iss_uop.mem_size \n connect issue_slots[10].iss_uop.mem_cmd, slots_10.io.iss_uop.mem_cmd \n connect issue_slots[10].iss_uop.exc_cause, slots_10.io.iss_uop.exc_cause \n connect issue_slots[10].iss_uop.exception, slots_10.io.iss_uop.exception \n connect issue_slots[10].iss_uop.stale_pdst, slots_10.io.iss_uop.stale_pdst \n connect issue_slots[10].iss_uop.ppred_busy, slots_10.io.iss_uop.ppred_busy \n connect issue_slots[10].iss_uop.prs3_busy, slots_10.io.iss_uop.prs3_busy \n connect issue_slots[10].iss_uop.prs2_busy, slots_10.io.iss_uop.prs2_busy \n connect issue_slots[10].iss_uop.prs1_busy, slots_10.io.iss_uop.prs1_busy \n connect issue_slots[10].iss_uop.ppred, slots_10.io.iss_uop.ppred \n connect issue_slots[10].iss_uop.prs3, slots_10.io.iss_uop.prs3 \n connect issue_slots[10].iss_uop.prs2, slots_10.io.iss_uop.prs2 \n connect issue_slots[10].iss_uop.prs1, slots_10.io.iss_uop.prs1 \n connect issue_slots[10].iss_uop.pdst, slots_10.io.iss_uop.pdst \n connect issue_slots[10].iss_uop.rxq_idx, slots_10.io.iss_uop.rxq_idx \n connect issue_slots[10].iss_uop.stq_idx, slots_10.io.iss_uop.stq_idx \n connect issue_slots[10].iss_uop.ldq_idx, slots_10.io.iss_uop.ldq_idx \n connect issue_slots[10].iss_uop.rob_idx, slots_10.io.iss_uop.rob_idx \n connect issue_slots[10].iss_uop.fp_ctrl.vec, slots_10.io.iss_uop.fp_ctrl.vec \n connect issue_slots[10].iss_uop.fp_ctrl.wflags, slots_10.io.iss_uop.fp_ctrl.wflags \n connect issue_slots[10].iss_uop.fp_ctrl.sqrt, slots_10.io.iss_uop.fp_ctrl.sqrt \n connect issue_slots[10].iss_uop.fp_ctrl.div, slots_10.io.iss_uop.fp_ctrl.div \n connect issue_slots[10].iss_uop.fp_ctrl.fma, slots_10.io.iss_uop.fp_ctrl.fma \n connect issue_slots[10].iss_uop.fp_ctrl.fastpipe, slots_10.io.iss_uop.fp_ctrl.fastpipe \n connect issue_slots[10].iss_uop.fp_ctrl.toint, slots_10.io.iss_uop.fp_ctrl.toint \n connect issue_slots[10].iss_uop.fp_ctrl.fromint, slots_10.io.iss_uop.fp_ctrl.fromint \n connect issue_slots[10].iss_uop.fp_ctrl.typeTagOut, slots_10.io.iss_uop.fp_ctrl.typeTagOut \n connect issue_slots[10].iss_uop.fp_ctrl.typeTagIn, slots_10.io.iss_uop.fp_ctrl.typeTagIn \n connect issue_slots[10].iss_uop.fp_ctrl.swap23, slots_10.io.iss_uop.fp_ctrl.swap23 \n connect issue_slots[10].iss_uop.fp_ctrl.swap12, slots_10.io.iss_uop.fp_ctrl.swap12 \n connect issue_slots[10].iss_uop.fp_ctrl.ren3, slots_10.io.iss_uop.fp_ctrl.ren3 \n connect issue_slots[10].iss_uop.fp_ctrl.ren2, slots_10.io.iss_uop.fp_ctrl.ren2 \n connect issue_slots[10].iss_uop.fp_ctrl.ren1, slots_10.io.iss_uop.fp_ctrl.ren1 \n connect issue_slots[10].iss_uop.fp_ctrl.wen, slots_10.io.iss_uop.fp_ctrl.wen \n connect issue_slots[10].iss_uop.fp_ctrl.ldst, slots_10.io.iss_uop.fp_ctrl.ldst \n connect issue_slots[10].iss_uop.op2_sel, slots_10.io.iss_uop.op2_sel \n connect issue_slots[10].iss_uop.op1_sel, slots_10.io.iss_uop.op1_sel \n connect issue_slots[10].iss_uop.imm_packed, slots_10.io.iss_uop.imm_packed \n connect issue_slots[10].iss_uop.pimm, slots_10.io.iss_uop.pimm \n connect issue_slots[10].iss_uop.imm_sel, slots_10.io.iss_uop.imm_sel \n connect issue_slots[10].iss_uop.imm_rename, slots_10.io.iss_uop.imm_rename \n connect issue_slots[10].iss_uop.taken, slots_10.io.iss_uop.taken \n connect issue_slots[10].iss_uop.pc_lob, slots_10.io.iss_uop.pc_lob \n connect issue_slots[10].iss_uop.edge_inst, slots_10.io.iss_uop.edge_inst \n connect issue_slots[10].iss_uop.ftq_idx, slots_10.io.iss_uop.ftq_idx \n connect issue_slots[10].iss_uop.is_mov, slots_10.io.iss_uop.is_mov \n connect issue_slots[10].iss_uop.is_rocc, slots_10.io.iss_uop.is_rocc \n connect issue_slots[10].iss_uop.is_sys_pc2epc, slots_10.io.iss_uop.is_sys_pc2epc \n connect issue_slots[10].iss_uop.is_eret, slots_10.io.iss_uop.is_eret \n connect issue_slots[10].iss_uop.is_amo, slots_10.io.iss_uop.is_amo \n connect issue_slots[10].iss_uop.is_sfence, slots_10.io.iss_uop.is_sfence \n connect issue_slots[10].iss_uop.is_fencei, slots_10.io.iss_uop.is_fencei \n connect issue_slots[10].iss_uop.is_fence, slots_10.io.iss_uop.is_fence \n connect issue_slots[10].iss_uop.is_sfb, slots_10.io.iss_uop.is_sfb \n connect issue_slots[10].iss_uop.br_type, slots_10.io.iss_uop.br_type \n connect issue_slots[10].iss_uop.br_tag, slots_10.io.iss_uop.br_tag \n connect issue_slots[10].iss_uop.br_mask, slots_10.io.iss_uop.br_mask \n connect issue_slots[10].iss_uop.dis_col_sel, slots_10.io.iss_uop.dis_col_sel \n connect issue_slots[10].iss_uop.iw_p3_bypass_hint, slots_10.io.iss_uop.iw_p3_bypass_hint \n connect issue_slots[10].iss_uop.iw_p2_bypass_hint, slots_10.io.iss_uop.iw_p2_bypass_hint \n connect issue_slots[10].iss_uop.iw_p1_bypass_hint, slots_10.io.iss_uop.iw_p1_bypass_hint \n connect issue_slots[10].iss_uop.iw_p2_speculative_child, slots_10.io.iss_uop.iw_p2_speculative_child \n connect issue_slots[10].iss_uop.iw_p1_speculative_child, slots_10.io.iss_uop.iw_p1_speculative_child \n connect issue_slots[10].iss_uop.iw_issued_partial_dgen, slots_10.io.iss_uop.iw_issued_partial_dgen \n connect issue_slots[10].iss_uop.iw_issued_partial_agen, slots_10.io.iss_uop.iw_issued_partial_agen \n connect issue_slots[10].iss_uop.iw_issued, slots_10.io.iss_uop.iw_issued \n connect issue_slots[10].iss_uop.fu_code[0], slots_10.io.iss_uop.fu_code[0] \n connect issue_slots[10].iss_uop.fu_code[1], slots_10.io.iss_uop.fu_code[1] \n connect issue_slots[10].iss_uop.fu_code[2], slots_10.io.iss_uop.fu_code[2] \n connect issue_slots[10].iss_uop.fu_code[3], slots_10.io.iss_uop.fu_code[3] \n connect issue_slots[10].iss_uop.fu_code[4], slots_10.io.iss_uop.fu_code[4] \n connect issue_slots[10].iss_uop.fu_code[5], slots_10.io.iss_uop.fu_code[5] \n connect issue_slots[10].iss_uop.fu_code[6], slots_10.io.iss_uop.fu_code[6] \n connect issue_slots[10].iss_uop.fu_code[7], slots_10.io.iss_uop.fu_code[7] \n connect issue_slots[10].iss_uop.fu_code[8], slots_10.io.iss_uop.fu_code[8] \n connect issue_slots[10].iss_uop.fu_code[9], slots_10.io.iss_uop.fu_code[9] \n connect issue_slots[10].iss_uop.iq_type[0], slots_10.io.iss_uop.iq_type[0] \n connect issue_slots[10].iss_uop.iq_type[1], slots_10.io.iss_uop.iq_type[1] \n connect issue_slots[10].iss_uop.iq_type[2], slots_10.io.iss_uop.iq_type[2] \n connect issue_slots[10].iss_uop.iq_type[3], slots_10.io.iss_uop.iq_type[3] \n connect issue_slots[10].iss_uop.debug_pc, slots_10.io.iss_uop.debug_pc \n connect issue_slots[10].iss_uop.is_rvc, slots_10.io.iss_uop.is_rvc \n connect issue_slots[10].iss_uop.debug_inst, slots_10.io.iss_uop.debug_inst \n connect issue_slots[10].iss_uop.inst, slots_10.io.iss_uop.inst \n connect slots_10.io.grant, issue_slots[10].grant \n connect issue_slots[10].request, slots_10.io.request \n connect issue_slots[10].will_be_valid, slots_10.io.will_be_valid \n connect issue_slots[10].valid, slots_10.io.valid \n connect slots_11.io.child_rebusys, issue_slots[11].child_rebusys \n connect slots_11.io.pred_wakeup_port.bits, issue_slots[11].pred_wakeup_port.bits \n connect slots_11.io.pred_wakeup_port.valid, issue_slots[11].pred_wakeup_port.valid \n connect slots_11.io.wakeup_ports[0].bits.rebusy, issue_slots[11].wakeup_ports[0].bits.rebusy \n connect slots_11.io.wakeup_ports[0].bits.speculative_mask, issue_slots[11].wakeup_ports[0].bits.speculative_mask \n connect slots_11.io.wakeup_ports[0].bits.bypassable, issue_slots[11].wakeup_ports[0].bits.bypassable \n connect slots_11.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[11].wakeup_ports[0].bits.uop.debug_tsrc \n connect slots_11.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[11].wakeup_ports[0].bits.uop.debug_fsrc \n connect slots_11.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[11].wakeup_ports[0].bits.uop.bp_xcpt_if \n connect slots_11.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[11].wakeup_ports[0].bits.uop.bp_debug_if \n connect slots_11.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[11].wakeup_ports[0].bits.uop.xcpt_ma_if \n connect slots_11.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[11].wakeup_ports[0].bits.uop.xcpt_ae_if \n connect slots_11.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[11].wakeup_ports[0].bits.uop.xcpt_pf_if \n connect slots_11.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[11].wakeup_ports[0].bits.uop.fp_typ \n connect slots_11.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[11].wakeup_ports[0].bits.uop.fp_rm \n connect slots_11.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[11].wakeup_ports[0].bits.uop.fp_val \n connect slots_11.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[11].wakeup_ports[0].bits.uop.fcn_op \n connect slots_11.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[11].wakeup_ports[0].bits.uop.fcn_dw \n connect slots_11.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[11].wakeup_ports[0].bits.uop.frs3_en \n connect slots_11.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[11].wakeup_ports[0].bits.uop.lrs2_rtype \n connect slots_11.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[11].wakeup_ports[0].bits.uop.lrs1_rtype \n connect slots_11.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[11].wakeup_ports[0].bits.uop.dst_rtype \n connect slots_11.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[11].wakeup_ports[0].bits.uop.lrs3 \n connect slots_11.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[11].wakeup_ports[0].bits.uop.lrs2 \n connect slots_11.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[11].wakeup_ports[0].bits.uop.lrs1 \n connect slots_11.io.wakeup_ports[0].bits.uop.ldst, issue_slots[11].wakeup_ports[0].bits.uop.ldst \n connect slots_11.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[11].wakeup_ports[0].bits.uop.ldst_is_rs1 \n connect slots_11.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[11].wakeup_ports[0].bits.uop.csr_cmd \n connect slots_11.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[11].wakeup_ports[0].bits.uop.flush_on_commit \n connect slots_11.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[11].wakeup_ports[0].bits.uop.is_unique \n connect slots_11.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[11].wakeup_ports[0].bits.uop.uses_stq \n connect slots_11.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[11].wakeup_ports[0].bits.uop.uses_ldq \n connect slots_11.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[11].wakeup_ports[0].bits.uop.mem_signed \n connect slots_11.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[11].wakeup_ports[0].bits.uop.mem_size \n connect slots_11.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[11].wakeup_ports[0].bits.uop.mem_cmd \n connect slots_11.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[11].wakeup_ports[0].bits.uop.exc_cause \n connect slots_11.io.wakeup_ports[0].bits.uop.exception, issue_slots[11].wakeup_ports[0].bits.uop.exception \n connect slots_11.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[11].wakeup_ports[0].bits.uop.stale_pdst \n connect slots_11.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[11].wakeup_ports[0].bits.uop.ppred_busy \n connect slots_11.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[11].wakeup_ports[0].bits.uop.prs3_busy \n connect slots_11.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[11].wakeup_ports[0].bits.uop.prs2_busy \n connect slots_11.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[11].wakeup_ports[0].bits.uop.prs1_busy \n connect slots_11.io.wakeup_ports[0].bits.uop.ppred, issue_slots[11].wakeup_ports[0].bits.uop.ppred \n connect slots_11.io.wakeup_ports[0].bits.uop.prs3, issue_slots[11].wakeup_ports[0].bits.uop.prs3 \n connect slots_11.io.wakeup_ports[0].bits.uop.prs2, issue_slots[11].wakeup_ports[0].bits.uop.prs2 \n connect slots_11.io.wakeup_ports[0].bits.uop.prs1, issue_slots[11].wakeup_ports[0].bits.uop.prs1 \n connect slots_11.io.wakeup_ports[0].bits.uop.pdst, issue_slots[11].wakeup_ports[0].bits.uop.pdst \n connect slots_11.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[11].wakeup_ports[0].bits.uop.rxq_idx \n connect slots_11.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[11].wakeup_ports[0].bits.uop.stq_idx \n connect slots_11.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[11].wakeup_ports[0].bits.uop.ldq_idx \n connect slots_11.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[11].wakeup_ports[0].bits.uop.rob_idx \n connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.vec \n connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.wflags \n connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.sqrt \n connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.div \n connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.fma \n connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe \n connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.toint \n connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.fromint \n connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut \n connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn \n connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.swap23 \n connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.swap12 \n connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.ren3 \n connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.ren2 \n connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.ren1 \n connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.wen \n connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.ldst \n connect slots_11.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[11].wakeup_ports[0].bits.uop.op2_sel \n connect slots_11.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[11].wakeup_ports[0].bits.uop.op1_sel \n connect slots_11.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[11].wakeup_ports[0].bits.uop.imm_packed \n connect slots_11.io.wakeup_ports[0].bits.uop.pimm, issue_slots[11].wakeup_ports[0].bits.uop.pimm \n connect slots_11.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[11].wakeup_ports[0].bits.uop.imm_sel \n connect slots_11.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[11].wakeup_ports[0].bits.uop.imm_rename \n connect slots_11.io.wakeup_ports[0].bits.uop.taken, issue_slots[11].wakeup_ports[0].bits.uop.taken \n connect slots_11.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[11].wakeup_ports[0].bits.uop.pc_lob \n connect slots_11.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[11].wakeup_ports[0].bits.uop.edge_inst \n connect slots_11.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[11].wakeup_ports[0].bits.uop.ftq_idx \n connect slots_11.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[11].wakeup_ports[0].bits.uop.is_mov \n connect slots_11.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[11].wakeup_ports[0].bits.uop.is_rocc \n connect slots_11.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[11].wakeup_ports[0].bits.uop.is_sys_pc2epc \n connect slots_11.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[11].wakeup_ports[0].bits.uop.is_eret \n connect slots_11.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[11].wakeup_ports[0].bits.uop.is_amo \n connect slots_11.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[11].wakeup_ports[0].bits.uop.is_sfence \n connect slots_11.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[11].wakeup_ports[0].bits.uop.is_fencei \n connect slots_11.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[11].wakeup_ports[0].bits.uop.is_fence \n connect slots_11.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[11].wakeup_ports[0].bits.uop.is_sfb \n connect slots_11.io.wakeup_ports[0].bits.uop.br_type, issue_slots[11].wakeup_ports[0].bits.uop.br_type \n connect slots_11.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[11].wakeup_ports[0].bits.uop.br_tag \n connect slots_11.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[11].wakeup_ports[0].bits.uop.br_mask \n connect slots_11.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[11].wakeup_ports[0].bits.uop.dis_col_sel \n connect slots_11.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[11].wakeup_ports[0].bits.uop.iw_p3_bypass_hint \n connect slots_11.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[11].wakeup_ports[0].bits.uop.iw_p2_bypass_hint \n connect slots_11.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[11].wakeup_ports[0].bits.uop.iw_p1_bypass_hint \n connect slots_11.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[11].wakeup_ports[0].bits.uop.iw_p2_speculative_child \n connect slots_11.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[11].wakeup_ports[0].bits.uop.iw_p1_speculative_child \n connect slots_11.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[11].wakeup_ports[0].bits.uop.iw_issued_partial_dgen \n connect slots_11.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[11].wakeup_ports[0].bits.uop.iw_issued_partial_agen \n connect slots_11.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[11].wakeup_ports[0].bits.uop.iw_issued \n connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[0] \n connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[1] \n connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[2] \n connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[3] \n connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[4] \n connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[5] \n connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[6] \n connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[7] \n connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[8] \n connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[9] \n connect slots_11.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[11].wakeup_ports[0].bits.uop.iq_type[0] \n connect slots_11.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[11].wakeup_ports[0].bits.uop.iq_type[1] \n connect slots_11.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[11].wakeup_ports[0].bits.uop.iq_type[2] \n connect slots_11.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[11].wakeup_ports[0].bits.uop.iq_type[3] \n connect slots_11.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[11].wakeup_ports[0].bits.uop.debug_pc \n connect slots_11.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[11].wakeup_ports[0].bits.uop.is_rvc \n connect slots_11.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[11].wakeup_ports[0].bits.uop.debug_inst \n connect slots_11.io.wakeup_ports[0].bits.uop.inst, issue_slots[11].wakeup_ports[0].bits.uop.inst \n connect slots_11.io.wakeup_ports[0].valid, issue_slots[11].wakeup_ports[0].valid \n connect slots_11.io.wakeup_ports[1].bits.rebusy, issue_slots[11].wakeup_ports[1].bits.rebusy \n connect slots_11.io.wakeup_ports[1].bits.speculative_mask, issue_slots[11].wakeup_ports[1].bits.speculative_mask \n connect slots_11.io.wakeup_ports[1].bits.bypassable, issue_slots[11].wakeup_ports[1].bits.bypassable \n connect slots_11.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[11].wakeup_ports[1].bits.uop.debug_tsrc \n connect slots_11.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[11].wakeup_ports[1].bits.uop.debug_fsrc \n connect slots_11.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[11].wakeup_ports[1].bits.uop.bp_xcpt_if \n connect slots_11.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[11].wakeup_ports[1].bits.uop.bp_debug_if \n connect slots_11.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[11].wakeup_ports[1].bits.uop.xcpt_ma_if \n connect slots_11.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[11].wakeup_ports[1].bits.uop.xcpt_ae_if \n connect slots_11.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[11].wakeup_ports[1].bits.uop.xcpt_pf_if \n connect slots_11.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[11].wakeup_ports[1].bits.uop.fp_typ \n connect slots_11.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[11].wakeup_ports[1].bits.uop.fp_rm \n connect slots_11.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[11].wakeup_ports[1].bits.uop.fp_val \n connect slots_11.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[11].wakeup_ports[1].bits.uop.fcn_op \n connect slots_11.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[11].wakeup_ports[1].bits.uop.fcn_dw \n connect slots_11.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[11].wakeup_ports[1].bits.uop.frs3_en \n connect slots_11.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[11].wakeup_ports[1].bits.uop.lrs2_rtype \n connect slots_11.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[11].wakeup_ports[1].bits.uop.lrs1_rtype \n connect slots_11.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[11].wakeup_ports[1].bits.uop.dst_rtype \n connect slots_11.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[11].wakeup_ports[1].bits.uop.lrs3 \n connect slots_11.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[11].wakeup_ports[1].bits.uop.lrs2 \n connect slots_11.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[11].wakeup_ports[1].bits.uop.lrs1 \n connect slots_11.io.wakeup_ports[1].bits.uop.ldst, issue_slots[11].wakeup_ports[1].bits.uop.ldst \n connect slots_11.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[11].wakeup_ports[1].bits.uop.ldst_is_rs1 \n connect slots_11.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[11].wakeup_ports[1].bits.uop.csr_cmd \n connect slots_11.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[11].wakeup_ports[1].bits.uop.flush_on_commit \n connect slots_11.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[11].wakeup_ports[1].bits.uop.is_unique \n connect slots_11.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[11].wakeup_ports[1].bits.uop.uses_stq \n connect slots_11.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[11].wakeup_ports[1].bits.uop.uses_ldq \n connect slots_11.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[11].wakeup_ports[1].bits.uop.mem_signed \n connect slots_11.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[11].wakeup_ports[1].bits.uop.mem_size \n connect slots_11.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[11].wakeup_ports[1].bits.uop.mem_cmd \n connect slots_11.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[11].wakeup_ports[1].bits.uop.exc_cause \n connect slots_11.io.wakeup_ports[1].bits.uop.exception, issue_slots[11].wakeup_ports[1].bits.uop.exception \n connect slots_11.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[11].wakeup_ports[1].bits.uop.stale_pdst \n connect slots_11.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[11].wakeup_ports[1].bits.uop.ppred_busy \n connect slots_11.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[11].wakeup_ports[1].bits.uop.prs3_busy \n connect slots_11.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[11].wakeup_ports[1].bits.uop.prs2_busy \n connect slots_11.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[11].wakeup_ports[1].bits.uop.prs1_busy \n connect slots_11.io.wakeup_ports[1].bits.uop.ppred, issue_slots[11].wakeup_ports[1].bits.uop.ppred \n connect slots_11.io.wakeup_ports[1].bits.uop.prs3, issue_slots[11].wakeup_ports[1].bits.uop.prs3 \n connect slots_11.io.wakeup_ports[1].bits.uop.prs2, issue_slots[11].wakeup_ports[1].bits.uop.prs2 \n connect slots_11.io.wakeup_ports[1].bits.uop.prs1, issue_slots[11].wakeup_ports[1].bits.uop.prs1 \n connect slots_11.io.wakeup_ports[1].bits.uop.pdst, issue_slots[11].wakeup_ports[1].bits.uop.pdst \n connect slots_11.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[11].wakeup_ports[1].bits.uop.rxq_idx \n connect slots_11.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[11].wakeup_ports[1].bits.uop.stq_idx \n connect slots_11.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[11].wakeup_ports[1].bits.uop.ldq_idx \n connect slots_11.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[11].wakeup_ports[1].bits.uop.rob_idx \n connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.vec \n connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.wflags \n connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.sqrt \n connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.div \n connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.fma \n connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe \n connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.toint \n connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.fromint \n connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut \n connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn \n connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.swap23 \n connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.swap12 \n connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.ren3 \n connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.ren2 \n connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.ren1 \n connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.wen \n connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.ldst \n connect slots_11.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[11].wakeup_ports[1].bits.uop.op2_sel \n connect slots_11.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[11].wakeup_ports[1].bits.uop.op1_sel \n connect slots_11.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[11].wakeup_ports[1].bits.uop.imm_packed \n connect slots_11.io.wakeup_ports[1].bits.uop.pimm, issue_slots[11].wakeup_ports[1].bits.uop.pimm \n connect slots_11.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[11].wakeup_ports[1].bits.uop.imm_sel \n connect slots_11.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[11].wakeup_ports[1].bits.uop.imm_rename \n connect slots_11.io.wakeup_ports[1].bits.uop.taken, issue_slots[11].wakeup_ports[1].bits.uop.taken \n connect slots_11.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[11].wakeup_ports[1].bits.uop.pc_lob \n connect slots_11.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[11].wakeup_ports[1].bits.uop.edge_inst \n connect slots_11.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[11].wakeup_ports[1].bits.uop.ftq_idx \n connect slots_11.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[11].wakeup_ports[1].bits.uop.is_mov \n connect slots_11.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[11].wakeup_ports[1].bits.uop.is_rocc \n connect slots_11.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[11].wakeup_ports[1].bits.uop.is_sys_pc2epc \n connect slots_11.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[11].wakeup_ports[1].bits.uop.is_eret \n connect slots_11.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[11].wakeup_ports[1].bits.uop.is_amo \n connect slots_11.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[11].wakeup_ports[1].bits.uop.is_sfence \n connect slots_11.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[11].wakeup_ports[1].bits.uop.is_fencei \n connect slots_11.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[11].wakeup_ports[1].bits.uop.is_fence \n connect slots_11.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[11].wakeup_ports[1].bits.uop.is_sfb \n connect slots_11.io.wakeup_ports[1].bits.uop.br_type, issue_slots[11].wakeup_ports[1].bits.uop.br_type \n connect slots_11.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[11].wakeup_ports[1].bits.uop.br_tag \n connect slots_11.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[11].wakeup_ports[1].bits.uop.br_mask \n connect slots_11.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[11].wakeup_ports[1].bits.uop.dis_col_sel \n connect slots_11.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[11].wakeup_ports[1].bits.uop.iw_p3_bypass_hint \n connect slots_11.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[11].wakeup_ports[1].bits.uop.iw_p2_bypass_hint \n connect slots_11.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[11].wakeup_ports[1].bits.uop.iw_p1_bypass_hint \n connect slots_11.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[11].wakeup_ports[1].bits.uop.iw_p2_speculative_child \n connect slots_11.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[11].wakeup_ports[1].bits.uop.iw_p1_speculative_child \n connect slots_11.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[11].wakeup_ports[1].bits.uop.iw_issued_partial_dgen \n connect slots_11.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[11].wakeup_ports[1].bits.uop.iw_issued_partial_agen \n connect slots_11.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[11].wakeup_ports[1].bits.uop.iw_issued \n connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[0] \n connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[1] \n connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[2] \n connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[3] \n connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[4] \n connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[5] \n connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[6] \n connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[7] \n connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[8] \n connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[9] \n connect slots_11.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[11].wakeup_ports[1].bits.uop.iq_type[0] \n connect slots_11.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[11].wakeup_ports[1].bits.uop.iq_type[1] \n connect slots_11.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[11].wakeup_ports[1].bits.uop.iq_type[2] \n connect slots_11.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[11].wakeup_ports[1].bits.uop.iq_type[3] \n connect slots_11.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[11].wakeup_ports[1].bits.uop.debug_pc \n connect slots_11.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[11].wakeup_ports[1].bits.uop.is_rvc \n connect slots_11.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[11].wakeup_ports[1].bits.uop.debug_inst \n connect slots_11.io.wakeup_ports[1].bits.uop.inst, issue_slots[11].wakeup_ports[1].bits.uop.inst \n connect slots_11.io.wakeup_ports[1].valid, issue_slots[11].wakeup_ports[1].valid \n connect slots_11.io.wakeup_ports[2].bits.rebusy, issue_slots[11].wakeup_ports[2].bits.rebusy \n connect slots_11.io.wakeup_ports[2].bits.speculative_mask, issue_slots[11].wakeup_ports[2].bits.speculative_mask \n connect slots_11.io.wakeup_ports[2].bits.bypassable, issue_slots[11].wakeup_ports[2].bits.bypassable \n connect slots_11.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[11].wakeup_ports[2].bits.uop.debug_tsrc \n connect slots_11.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[11].wakeup_ports[2].bits.uop.debug_fsrc \n connect slots_11.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[11].wakeup_ports[2].bits.uop.bp_xcpt_if \n connect slots_11.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[11].wakeup_ports[2].bits.uop.bp_debug_if \n connect slots_11.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[11].wakeup_ports[2].bits.uop.xcpt_ma_if \n connect slots_11.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[11].wakeup_ports[2].bits.uop.xcpt_ae_if \n connect slots_11.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[11].wakeup_ports[2].bits.uop.xcpt_pf_if \n connect slots_11.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[11].wakeup_ports[2].bits.uop.fp_typ \n connect slots_11.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[11].wakeup_ports[2].bits.uop.fp_rm \n connect slots_11.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[11].wakeup_ports[2].bits.uop.fp_val \n connect slots_11.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[11].wakeup_ports[2].bits.uop.fcn_op \n connect slots_11.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[11].wakeup_ports[2].bits.uop.fcn_dw \n connect slots_11.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[11].wakeup_ports[2].bits.uop.frs3_en \n connect slots_11.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[11].wakeup_ports[2].bits.uop.lrs2_rtype \n connect slots_11.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[11].wakeup_ports[2].bits.uop.lrs1_rtype \n connect slots_11.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[11].wakeup_ports[2].bits.uop.dst_rtype \n connect slots_11.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[11].wakeup_ports[2].bits.uop.lrs3 \n connect slots_11.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[11].wakeup_ports[2].bits.uop.lrs2 \n connect slots_11.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[11].wakeup_ports[2].bits.uop.lrs1 \n connect slots_11.io.wakeup_ports[2].bits.uop.ldst, issue_slots[11].wakeup_ports[2].bits.uop.ldst \n connect slots_11.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[11].wakeup_ports[2].bits.uop.ldst_is_rs1 \n connect slots_11.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[11].wakeup_ports[2].bits.uop.csr_cmd \n connect slots_11.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[11].wakeup_ports[2].bits.uop.flush_on_commit \n connect slots_11.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[11].wakeup_ports[2].bits.uop.is_unique \n connect slots_11.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[11].wakeup_ports[2].bits.uop.uses_stq \n connect slots_11.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[11].wakeup_ports[2].bits.uop.uses_ldq \n connect slots_11.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[11].wakeup_ports[2].bits.uop.mem_signed \n connect slots_11.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[11].wakeup_ports[2].bits.uop.mem_size \n connect slots_11.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[11].wakeup_ports[2].bits.uop.mem_cmd \n connect slots_11.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[11].wakeup_ports[2].bits.uop.exc_cause \n connect slots_11.io.wakeup_ports[2].bits.uop.exception, issue_slots[11].wakeup_ports[2].bits.uop.exception \n connect slots_11.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[11].wakeup_ports[2].bits.uop.stale_pdst \n connect slots_11.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[11].wakeup_ports[2].bits.uop.ppred_busy \n connect slots_11.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[11].wakeup_ports[2].bits.uop.prs3_busy \n connect slots_11.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[11].wakeup_ports[2].bits.uop.prs2_busy \n connect slots_11.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[11].wakeup_ports[2].bits.uop.prs1_busy \n connect slots_11.io.wakeup_ports[2].bits.uop.ppred, issue_slots[11].wakeup_ports[2].bits.uop.ppred \n connect slots_11.io.wakeup_ports[2].bits.uop.prs3, issue_slots[11].wakeup_ports[2].bits.uop.prs3 \n connect slots_11.io.wakeup_ports[2].bits.uop.prs2, issue_slots[11].wakeup_ports[2].bits.uop.prs2 \n connect slots_11.io.wakeup_ports[2].bits.uop.prs1, issue_slots[11].wakeup_ports[2].bits.uop.prs1 \n connect slots_11.io.wakeup_ports[2].bits.uop.pdst, issue_slots[11].wakeup_ports[2].bits.uop.pdst \n connect slots_11.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[11].wakeup_ports[2].bits.uop.rxq_idx \n connect slots_11.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[11].wakeup_ports[2].bits.uop.stq_idx \n connect slots_11.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[11].wakeup_ports[2].bits.uop.ldq_idx \n connect slots_11.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[11].wakeup_ports[2].bits.uop.rob_idx \n connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.vec \n connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.wflags \n connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.sqrt \n connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.div \n connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.fma \n connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe \n connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.toint \n connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.fromint \n connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut \n connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn \n connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.swap23 \n connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.swap12 \n connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.ren3 \n connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.ren2 \n connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.ren1 \n connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.wen \n connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.ldst \n connect slots_11.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[11].wakeup_ports[2].bits.uop.op2_sel \n connect slots_11.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[11].wakeup_ports[2].bits.uop.op1_sel \n connect slots_11.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[11].wakeup_ports[2].bits.uop.imm_packed \n connect slots_11.io.wakeup_ports[2].bits.uop.pimm, issue_slots[11].wakeup_ports[2].bits.uop.pimm \n connect slots_11.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[11].wakeup_ports[2].bits.uop.imm_sel \n connect slots_11.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[11].wakeup_ports[2].bits.uop.imm_rename \n connect slots_11.io.wakeup_ports[2].bits.uop.taken, issue_slots[11].wakeup_ports[2].bits.uop.taken \n connect slots_11.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[11].wakeup_ports[2].bits.uop.pc_lob \n connect slots_11.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[11].wakeup_ports[2].bits.uop.edge_inst \n connect slots_11.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[11].wakeup_ports[2].bits.uop.ftq_idx \n connect slots_11.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[11].wakeup_ports[2].bits.uop.is_mov \n connect slots_11.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[11].wakeup_ports[2].bits.uop.is_rocc \n connect slots_11.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[11].wakeup_ports[2].bits.uop.is_sys_pc2epc \n connect slots_11.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[11].wakeup_ports[2].bits.uop.is_eret \n connect slots_11.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[11].wakeup_ports[2].bits.uop.is_amo \n connect slots_11.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[11].wakeup_ports[2].bits.uop.is_sfence \n connect slots_11.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[11].wakeup_ports[2].bits.uop.is_fencei \n connect slots_11.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[11].wakeup_ports[2].bits.uop.is_fence \n connect slots_11.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[11].wakeup_ports[2].bits.uop.is_sfb \n connect slots_11.io.wakeup_ports[2].bits.uop.br_type, issue_slots[11].wakeup_ports[2].bits.uop.br_type \n connect slots_11.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[11].wakeup_ports[2].bits.uop.br_tag \n connect slots_11.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[11].wakeup_ports[2].bits.uop.br_mask \n connect slots_11.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[11].wakeup_ports[2].bits.uop.dis_col_sel \n connect slots_11.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[11].wakeup_ports[2].bits.uop.iw_p3_bypass_hint \n connect slots_11.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[11].wakeup_ports[2].bits.uop.iw_p2_bypass_hint \n connect slots_11.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[11].wakeup_ports[2].bits.uop.iw_p1_bypass_hint \n connect slots_11.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[11].wakeup_ports[2].bits.uop.iw_p2_speculative_child \n connect slots_11.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[11].wakeup_ports[2].bits.uop.iw_p1_speculative_child \n connect slots_11.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[11].wakeup_ports[2].bits.uop.iw_issued_partial_dgen \n connect slots_11.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[11].wakeup_ports[2].bits.uop.iw_issued_partial_agen \n connect slots_11.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[11].wakeup_ports[2].bits.uop.iw_issued \n connect slots_11.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[11].wakeup_ports[2].bits.uop.fu_code[0] \n connect slots_11.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[11].wakeup_ports[2].bits.uop.fu_code[1] \n connect slots_11.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[11].wakeup_ports[2].bits.uop.fu_code[2] \n connect slots_11.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[11].wakeup_ports[2].bits.uop.fu_code[3] \n connect slots_11.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[11].wakeup_ports[2].bits.uop.fu_code[4] \n connect slots_11.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[11].wakeup_ports[2].bits.uop.fu_code[5] \n connect slots_11.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[11].wakeup_ports[2].bits.uop.fu_code[6] \n connect slots_11.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[11].wakeup_ports[2].bits.uop.fu_code[7] \n connect slots_11.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[11].wakeup_ports[2].bits.uop.fu_code[8] \n connect slots_11.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[11].wakeup_ports[2].bits.uop.fu_code[9] \n connect slots_11.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[11].wakeup_ports[2].bits.uop.iq_type[0] \n connect slots_11.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[11].wakeup_ports[2].bits.uop.iq_type[1] \n connect slots_11.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[11].wakeup_ports[2].bits.uop.iq_type[2] \n connect slots_11.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[11].wakeup_ports[2].bits.uop.iq_type[3] \n connect slots_11.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[11].wakeup_ports[2].bits.uop.debug_pc \n connect slots_11.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[11].wakeup_ports[2].bits.uop.is_rvc \n connect slots_11.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[11].wakeup_ports[2].bits.uop.debug_inst \n connect slots_11.io.wakeup_ports[2].bits.uop.inst, issue_slots[11].wakeup_ports[2].bits.uop.inst \n connect slots_11.io.wakeup_ports[2].valid, issue_slots[11].wakeup_ports[2].valid \n connect slots_11.io.wakeup_ports[3].bits.rebusy, issue_slots[11].wakeup_ports[3].bits.rebusy \n connect slots_11.io.wakeup_ports[3].bits.speculative_mask, issue_slots[11].wakeup_ports[3].bits.speculative_mask \n connect slots_11.io.wakeup_ports[3].bits.bypassable, issue_slots[11].wakeup_ports[3].bits.bypassable \n connect slots_11.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[11].wakeup_ports[3].bits.uop.debug_tsrc \n connect slots_11.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[11].wakeup_ports[3].bits.uop.debug_fsrc \n connect slots_11.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[11].wakeup_ports[3].bits.uop.bp_xcpt_if \n connect slots_11.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[11].wakeup_ports[3].bits.uop.bp_debug_if \n connect slots_11.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[11].wakeup_ports[3].bits.uop.xcpt_ma_if \n connect slots_11.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[11].wakeup_ports[3].bits.uop.xcpt_ae_if \n connect slots_11.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[11].wakeup_ports[3].bits.uop.xcpt_pf_if \n connect slots_11.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[11].wakeup_ports[3].bits.uop.fp_typ \n connect slots_11.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[11].wakeup_ports[3].bits.uop.fp_rm \n connect slots_11.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[11].wakeup_ports[3].bits.uop.fp_val \n connect slots_11.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[11].wakeup_ports[3].bits.uop.fcn_op \n connect slots_11.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[11].wakeup_ports[3].bits.uop.fcn_dw \n connect slots_11.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[11].wakeup_ports[3].bits.uop.frs3_en \n connect slots_11.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[11].wakeup_ports[3].bits.uop.lrs2_rtype \n connect slots_11.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[11].wakeup_ports[3].bits.uop.lrs1_rtype \n connect slots_11.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[11].wakeup_ports[3].bits.uop.dst_rtype \n connect slots_11.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[11].wakeup_ports[3].bits.uop.lrs3 \n connect slots_11.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[11].wakeup_ports[3].bits.uop.lrs2 \n connect slots_11.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[11].wakeup_ports[3].bits.uop.lrs1 \n connect slots_11.io.wakeup_ports[3].bits.uop.ldst, issue_slots[11].wakeup_ports[3].bits.uop.ldst \n connect slots_11.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[11].wakeup_ports[3].bits.uop.ldst_is_rs1 \n connect slots_11.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[11].wakeup_ports[3].bits.uop.csr_cmd \n connect slots_11.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[11].wakeup_ports[3].bits.uop.flush_on_commit \n connect slots_11.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[11].wakeup_ports[3].bits.uop.is_unique \n connect slots_11.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[11].wakeup_ports[3].bits.uop.uses_stq \n connect slots_11.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[11].wakeup_ports[3].bits.uop.uses_ldq \n connect slots_11.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[11].wakeup_ports[3].bits.uop.mem_signed \n connect slots_11.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[11].wakeup_ports[3].bits.uop.mem_size \n connect slots_11.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[11].wakeup_ports[3].bits.uop.mem_cmd \n connect slots_11.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[11].wakeup_ports[3].bits.uop.exc_cause \n connect slots_11.io.wakeup_ports[3].bits.uop.exception, issue_slots[11].wakeup_ports[3].bits.uop.exception \n connect slots_11.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[11].wakeup_ports[3].bits.uop.stale_pdst \n connect slots_11.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[11].wakeup_ports[3].bits.uop.ppred_busy \n connect slots_11.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[11].wakeup_ports[3].bits.uop.prs3_busy \n connect slots_11.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[11].wakeup_ports[3].bits.uop.prs2_busy \n connect slots_11.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[11].wakeup_ports[3].bits.uop.prs1_busy \n connect slots_11.io.wakeup_ports[3].bits.uop.ppred, issue_slots[11].wakeup_ports[3].bits.uop.ppred \n connect slots_11.io.wakeup_ports[3].bits.uop.prs3, issue_slots[11].wakeup_ports[3].bits.uop.prs3 \n connect slots_11.io.wakeup_ports[3].bits.uop.prs2, issue_slots[11].wakeup_ports[3].bits.uop.prs2 \n connect slots_11.io.wakeup_ports[3].bits.uop.prs1, issue_slots[11].wakeup_ports[3].bits.uop.prs1 \n connect slots_11.io.wakeup_ports[3].bits.uop.pdst, issue_slots[11].wakeup_ports[3].bits.uop.pdst \n connect slots_11.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[11].wakeup_ports[3].bits.uop.rxq_idx \n connect slots_11.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[11].wakeup_ports[3].bits.uop.stq_idx \n connect slots_11.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[11].wakeup_ports[3].bits.uop.ldq_idx \n connect slots_11.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[11].wakeup_ports[3].bits.uop.rob_idx \n connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.vec \n connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.wflags \n connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.sqrt \n connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.div \n connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.fma \n connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe \n connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.toint \n connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.fromint \n connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut \n connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn \n connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.swap23 \n connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.swap12 \n connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.ren3 \n connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.ren2 \n connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.ren1 \n connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.wen \n connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.ldst \n connect slots_11.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[11].wakeup_ports[3].bits.uop.op2_sel \n connect slots_11.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[11].wakeup_ports[3].bits.uop.op1_sel \n connect slots_11.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[11].wakeup_ports[3].bits.uop.imm_packed \n connect slots_11.io.wakeup_ports[3].bits.uop.pimm, issue_slots[11].wakeup_ports[3].bits.uop.pimm \n connect slots_11.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[11].wakeup_ports[3].bits.uop.imm_sel \n connect slots_11.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[11].wakeup_ports[3].bits.uop.imm_rename \n connect slots_11.io.wakeup_ports[3].bits.uop.taken, issue_slots[11].wakeup_ports[3].bits.uop.taken \n connect slots_11.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[11].wakeup_ports[3].bits.uop.pc_lob \n connect slots_11.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[11].wakeup_ports[3].bits.uop.edge_inst \n connect slots_11.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[11].wakeup_ports[3].bits.uop.ftq_idx \n connect slots_11.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[11].wakeup_ports[3].bits.uop.is_mov \n connect slots_11.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[11].wakeup_ports[3].bits.uop.is_rocc \n connect slots_11.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[11].wakeup_ports[3].bits.uop.is_sys_pc2epc \n connect slots_11.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[11].wakeup_ports[3].bits.uop.is_eret \n connect slots_11.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[11].wakeup_ports[3].bits.uop.is_amo \n connect slots_11.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[11].wakeup_ports[3].bits.uop.is_sfence \n connect slots_11.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[11].wakeup_ports[3].bits.uop.is_fencei \n connect slots_11.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[11].wakeup_ports[3].bits.uop.is_fence \n connect slots_11.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[11].wakeup_ports[3].bits.uop.is_sfb \n connect slots_11.io.wakeup_ports[3].bits.uop.br_type, issue_slots[11].wakeup_ports[3].bits.uop.br_type \n connect slots_11.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[11].wakeup_ports[3].bits.uop.br_tag \n connect slots_11.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[11].wakeup_ports[3].bits.uop.br_mask \n connect slots_11.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[11].wakeup_ports[3].bits.uop.dis_col_sel \n connect slots_11.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[11].wakeup_ports[3].bits.uop.iw_p3_bypass_hint \n connect slots_11.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[11].wakeup_ports[3].bits.uop.iw_p2_bypass_hint \n connect slots_11.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[11].wakeup_ports[3].bits.uop.iw_p1_bypass_hint \n connect slots_11.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[11].wakeup_ports[3].bits.uop.iw_p2_speculative_child \n connect slots_11.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[11].wakeup_ports[3].bits.uop.iw_p1_speculative_child \n connect slots_11.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[11].wakeup_ports[3].bits.uop.iw_issued_partial_dgen \n connect slots_11.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[11].wakeup_ports[3].bits.uop.iw_issued_partial_agen \n connect slots_11.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[11].wakeup_ports[3].bits.uop.iw_issued \n connect slots_11.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[11].wakeup_ports[3].bits.uop.fu_code[0] \n connect slots_11.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[11].wakeup_ports[3].bits.uop.fu_code[1] \n connect slots_11.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[11].wakeup_ports[3].bits.uop.fu_code[2] \n connect slots_11.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[11].wakeup_ports[3].bits.uop.fu_code[3] \n connect slots_11.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[11].wakeup_ports[3].bits.uop.fu_code[4] \n connect slots_11.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[11].wakeup_ports[3].bits.uop.fu_code[5] \n connect slots_11.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[11].wakeup_ports[3].bits.uop.fu_code[6] \n connect slots_11.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[11].wakeup_ports[3].bits.uop.fu_code[7] \n connect slots_11.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[11].wakeup_ports[3].bits.uop.fu_code[8] \n connect slots_11.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[11].wakeup_ports[3].bits.uop.fu_code[9] \n connect slots_11.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[11].wakeup_ports[3].bits.uop.iq_type[0] \n connect slots_11.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[11].wakeup_ports[3].bits.uop.iq_type[1] \n connect slots_11.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[11].wakeup_ports[3].bits.uop.iq_type[2] \n connect slots_11.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[11].wakeup_ports[3].bits.uop.iq_type[3] \n connect slots_11.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[11].wakeup_ports[3].bits.uop.debug_pc \n connect slots_11.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[11].wakeup_ports[3].bits.uop.is_rvc \n connect slots_11.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[11].wakeup_ports[3].bits.uop.debug_inst \n connect slots_11.io.wakeup_ports[3].bits.uop.inst, issue_slots[11].wakeup_ports[3].bits.uop.inst \n connect slots_11.io.wakeup_ports[3].valid, issue_slots[11].wakeup_ports[3].valid \n connect slots_11.io.squash_grant, issue_slots[11].squash_grant \n connect slots_11.io.clear, issue_slots[11].clear \n connect slots_11.io.kill, issue_slots[11].kill \n connect slots_11.io.brupdate.b2.target_offset, issue_slots[11].brupdate.b2.target_offset \n connect slots_11.io.brupdate.b2.jalr_target, issue_slots[11].brupdate.b2.jalr_target \n connect slots_11.io.brupdate.b2.pc_sel, issue_slots[11].brupdate.b2.pc_sel \n connect slots_11.io.brupdate.b2.cfi_type, issue_slots[11].brupdate.b2.cfi_type \n connect slots_11.io.brupdate.b2.taken, issue_slots[11].brupdate.b2.taken \n connect slots_11.io.brupdate.b2.mispredict, issue_slots[11].brupdate.b2.mispredict \n connect slots_11.io.brupdate.b2.uop.debug_tsrc, issue_slots[11].brupdate.b2.uop.debug_tsrc \n connect slots_11.io.brupdate.b2.uop.debug_fsrc, issue_slots[11].brupdate.b2.uop.debug_fsrc \n connect slots_11.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[11].brupdate.b2.uop.bp_xcpt_if \n connect slots_11.io.brupdate.b2.uop.bp_debug_if, issue_slots[11].brupdate.b2.uop.bp_debug_if \n connect slots_11.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[11].brupdate.b2.uop.xcpt_ma_if \n connect slots_11.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[11].brupdate.b2.uop.xcpt_ae_if \n connect slots_11.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[11].brupdate.b2.uop.xcpt_pf_if \n connect slots_11.io.brupdate.b2.uop.fp_typ, issue_slots[11].brupdate.b2.uop.fp_typ \n connect slots_11.io.brupdate.b2.uop.fp_rm, issue_slots[11].brupdate.b2.uop.fp_rm \n connect slots_11.io.brupdate.b2.uop.fp_val, issue_slots[11].brupdate.b2.uop.fp_val \n connect slots_11.io.brupdate.b2.uop.fcn_op, issue_slots[11].brupdate.b2.uop.fcn_op \n connect slots_11.io.brupdate.b2.uop.fcn_dw, issue_slots[11].brupdate.b2.uop.fcn_dw \n connect slots_11.io.brupdate.b2.uop.frs3_en, issue_slots[11].brupdate.b2.uop.frs3_en \n connect slots_11.io.brupdate.b2.uop.lrs2_rtype, issue_slots[11].brupdate.b2.uop.lrs2_rtype \n connect slots_11.io.brupdate.b2.uop.lrs1_rtype, issue_slots[11].brupdate.b2.uop.lrs1_rtype \n connect slots_11.io.brupdate.b2.uop.dst_rtype, issue_slots[11].brupdate.b2.uop.dst_rtype \n connect slots_11.io.brupdate.b2.uop.lrs3, issue_slots[11].brupdate.b2.uop.lrs3 \n connect slots_11.io.brupdate.b2.uop.lrs2, issue_slots[11].brupdate.b2.uop.lrs2 \n connect slots_11.io.brupdate.b2.uop.lrs1, issue_slots[11].brupdate.b2.uop.lrs1 \n connect slots_11.io.brupdate.b2.uop.ldst, issue_slots[11].brupdate.b2.uop.ldst \n connect slots_11.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[11].brupdate.b2.uop.ldst_is_rs1 \n connect slots_11.io.brupdate.b2.uop.csr_cmd, issue_slots[11].brupdate.b2.uop.csr_cmd \n connect slots_11.io.brupdate.b2.uop.flush_on_commit, issue_slots[11].brupdate.b2.uop.flush_on_commit \n connect slots_11.io.brupdate.b2.uop.is_unique, issue_slots[11].brupdate.b2.uop.is_unique \n connect slots_11.io.brupdate.b2.uop.uses_stq, issue_slots[11].brupdate.b2.uop.uses_stq \n connect slots_11.io.brupdate.b2.uop.uses_ldq, issue_slots[11].brupdate.b2.uop.uses_ldq \n connect slots_11.io.brupdate.b2.uop.mem_signed, issue_slots[11].brupdate.b2.uop.mem_signed \n connect slots_11.io.brupdate.b2.uop.mem_size, issue_slots[11].brupdate.b2.uop.mem_size \n connect slots_11.io.brupdate.b2.uop.mem_cmd, issue_slots[11].brupdate.b2.uop.mem_cmd \n connect slots_11.io.brupdate.b2.uop.exc_cause, issue_slots[11].brupdate.b2.uop.exc_cause \n connect slots_11.io.brupdate.b2.uop.exception, issue_slots[11].brupdate.b2.uop.exception \n connect slots_11.io.brupdate.b2.uop.stale_pdst, issue_slots[11].brupdate.b2.uop.stale_pdst \n connect slots_11.io.brupdate.b2.uop.ppred_busy, issue_slots[11].brupdate.b2.uop.ppred_busy \n connect slots_11.io.brupdate.b2.uop.prs3_busy, issue_slots[11].brupdate.b2.uop.prs3_busy \n connect slots_11.io.brupdate.b2.uop.prs2_busy, issue_slots[11].brupdate.b2.uop.prs2_busy \n connect slots_11.io.brupdate.b2.uop.prs1_busy, issue_slots[11].brupdate.b2.uop.prs1_busy \n connect slots_11.io.brupdate.b2.uop.ppred, issue_slots[11].brupdate.b2.uop.ppred \n connect slots_11.io.brupdate.b2.uop.prs3, issue_slots[11].brupdate.b2.uop.prs3 \n connect slots_11.io.brupdate.b2.uop.prs2, issue_slots[11].brupdate.b2.uop.prs2 \n connect slots_11.io.brupdate.b2.uop.prs1, issue_slots[11].brupdate.b2.uop.prs1 \n connect slots_11.io.brupdate.b2.uop.pdst, issue_slots[11].brupdate.b2.uop.pdst \n connect slots_11.io.brupdate.b2.uop.rxq_idx, issue_slots[11].brupdate.b2.uop.rxq_idx \n connect slots_11.io.brupdate.b2.uop.stq_idx, issue_slots[11].brupdate.b2.uop.stq_idx \n connect slots_11.io.brupdate.b2.uop.ldq_idx, issue_slots[11].brupdate.b2.uop.ldq_idx \n connect slots_11.io.brupdate.b2.uop.rob_idx, issue_slots[11].brupdate.b2.uop.rob_idx \n connect slots_11.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[11].brupdate.b2.uop.fp_ctrl.vec \n connect slots_11.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[11].brupdate.b2.uop.fp_ctrl.wflags \n connect slots_11.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[11].brupdate.b2.uop.fp_ctrl.sqrt \n connect slots_11.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[11].brupdate.b2.uop.fp_ctrl.div \n connect slots_11.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[11].brupdate.b2.uop.fp_ctrl.fma \n connect slots_11.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[11].brupdate.b2.uop.fp_ctrl.fastpipe \n connect slots_11.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[11].brupdate.b2.uop.fp_ctrl.toint \n connect slots_11.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[11].brupdate.b2.uop.fp_ctrl.fromint \n connect slots_11.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[11].brupdate.b2.uop.fp_ctrl.typeTagOut \n connect slots_11.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[11].brupdate.b2.uop.fp_ctrl.typeTagIn \n connect slots_11.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[11].brupdate.b2.uop.fp_ctrl.swap23 \n connect slots_11.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[11].brupdate.b2.uop.fp_ctrl.swap12 \n connect slots_11.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[11].brupdate.b2.uop.fp_ctrl.ren3 \n connect slots_11.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[11].brupdate.b2.uop.fp_ctrl.ren2 \n connect slots_11.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[11].brupdate.b2.uop.fp_ctrl.ren1 \n connect slots_11.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[11].brupdate.b2.uop.fp_ctrl.wen \n connect slots_11.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[11].brupdate.b2.uop.fp_ctrl.ldst \n connect slots_11.io.brupdate.b2.uop.op2_sel, issue_slots[11].brupdate.b2.uop.op2_sel \n connect slots_11.io.brupdate.b2.uop.op1_sel, issue_slots[11].brupdate.b2.uop.op1_sel \n connect slots_11.io.brupdate.b2.uop.imm_packed, issue_slots[11].brupdate.b2.uop.imm_packed \n connect slots_11.io.brupdate.b2.uop.pimm, issue_slots[11].brupdate.b2.uop.pimm \n connect slots_11.io.brupdate.b2.uop.imm_sel, issue_slots[11].brupdate.b2.uop.imm_sel \n connect slots_11.io.brupdate.b2.uop.imm_rename, issue_slots[11].brupdate.b2.uop.imm_rename \n connect slots_11.io.brupdate.b2.uop.taken, issue_slots[11].brupdate.b2.uop.taken \n connect slots_11.io.brupdate.b2.uop.pc_lob, issue_slots[11].brupdate.b2.uop.pc_lob \n connect slots_11.io.brupdate.b2.uop.edge_inst, issue_slots[11].brupdate.b2.uop.edge_inst \n connect slots_11.io.brupdate.b2.uop.ftq_idx, issue_slots[11].brupdate.b2.uop.ftq_idx \n connect slots_11.io.brupdate.b2.uop.is_mov, issue_slots[11].brupdate.b2.uop.is_mov \n connect slots_11.io.brupdate.b2.uop.is_rocc, issue_slots[11].brupdate.b2.uop.is_rocc \n connect slots_11.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[11].brupdate.b2.uop.is_sys_pc2epc \n connect slots_11.io.brupdate.b2.uop.is_eret, issue_slots[11].brupdate.b2.uop.is_eret \n connect slots_11.io.brupdate.b2.uop.is_amo, issue_slots[11].brupdate.b2.uop.is_amo \n connect slots_11.io.brupdate.b2.uop.is_sfence, issue_slots[11].brupdate.b2.uop.is_sfence \n connect slots_11.io.brupdate.b2.uop.is_fencei, issue_slots[11].brupdate.b2.uop.is_fencei \n connect slots_11.io.brupdate.b2.uop.is_fence, issue_slots[11].brupdate.b2.uop.is_fence \n connect slots_11.io.brupdate.b2.uop.is_sfb, issue_slots[11].brupdate.b2.uop.is_sfb \n connect slots_11.io.brupdate.b2.uop.br_type, issue_slots[11].brupdate.b2.uop.br_type \n connect slots_11.io.brupdate.b2.uop.br_tag, issue_slots[11].brupdate.b2.uop.br_tag \n connect slots_11.io.brupdate.b2.uop.br_mask, issue_slots[11].brupdate.b2.uop.br_mask \n connect slots_11.io.brupdate.b2.uop.dis_col_sel, issue_slots[11].brupdate.b2.uop.dis_col_sel \n connect slots_11.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[11].brupdate.b2.uop.iw_p3_bypass_hint \n connect slots_11.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[11].brupdate.b2.uop.iw_p2_bypass_hint \n connect slots_11.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[11].brupdate.b2.uop.iw_p1_bypass_hint \n connect slots_11.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[11].brupdate.b2.uop.iw_p2_speculative_child \n connect slots_11.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[11].brupdate.b2.uop.iw_p1_speculative_child \n connect slots_11.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[11].brupdate.b2.uop.iw_issued_partial_dgen \n connect slots_11.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[11].brupdate.b2.uop.iw_issued_partial_agen \n connect slots_11.io.brupdate.b2.uop.iw_issued, issue_slots[11].brupdate.b2.uop.iw_issued \n connect slots_11.io.brupdate.b2.uop.fu_code[0], issue_slots[11].brupdate.b2.uop.fu_code[0] \n connect slots_11.io.brupdate.b2.uop.fu_code[1], issue_slots[11].brupdate.b2.uop.fu_code[1] \n connect slots_11.io.brupdate.b2.uop.fu_code[2], issue_slots[11].brupdate.b2.uop.fu_code[2] \n connect slots_11.io.brupdate.b2.uop.fu_code[3], issue_slots[11].brupdate.b2.uop.fu_code[3] \n connect slots_11.io.brupdate.b2.uop.fu_code[4], issue_slots[11].brupdate.b2.uop.fu_code[4] \n connect slots_11.io.brupdate.b2.uop.fu_code[5], issue_slots[11].brupdate.b2.uop.fu_code[5] \n connect slots_11.io.brupdate.b2.uop.fu_code[6], issue_slots[11].brupdate.b2.uop.fu_code[6] \n connect slots_11.io.brupdate.b2.uop.fu_code[7], issue_slots[11].brupdate.b2.uop.fu_code[7] \n connect slots_11.io.brupdate.b2.uop.fu_code[8], issue_slots[11].brupdate.b2.uop.fu_code[8] \n connect slots_11.io.brupdate.b2.uop.fu_code[9], issue_slots[11].brupdate.b2.uop.fu_code[9] \n connect slots_11.io.brupdate.b2.uop.iq_type[0], issue_slots[11].brupdate.b2.uop.iq_type[0] \n connect slots_11.io.brupdate.b2.uop.iq_type[1], issue_slots[11].brupdate.b2.uop.iq_type[1] \n connect slots_11.io.brupdate.b2.uop.iq_type[2], issue_slots[11].brupdate.b2.uop.iq_type[2] \n connect slots_11.io.brupdate.b2.uop.iq_type[3], issue_slots[11].brupdate.b2.uop.iq_type[3] \n connect slots_11.io.brupdate.b2.uop.debug_pc, issue_slots[11].brupdate.b2.uop.debug_pc \n connect slots_11.io.brupdate.b2.uop.is_rvc, issue_slots[11].brupdate.b2.uop.is_rvc \n connect slots_11.io.brupdate.b2.uop.debug_inst, issue_slots[11].brupdate.b2.uop.debug_inst \n connect slots_11.io.brupdate.b2.uop.inst, issue_slots[11].brupdate.b2.uop.inst \n connect slots_11.io.brupdate.b1.mispredict_mask, issue_slots[11].brupdate.b1.mispredict_mask \n connect slots_11.io.brupdate.b1.resolve_mask, issue_slots[11].brupdate.b1.resolve_mask \n connect issue_slots[11].out_uop.debug_tsrc, slots_11.io.out_uop.debug_tsrc \n connect issue_slots[11].out_uop.debug_fsrc, slots_11.io.out_uop.debug_fsrc \n connect issue_slots[11].out_uop.bp_xcpt_if, slots_11.io.out_uop.bp_xcpt_if \n connect issue_slots[11].out_uop.bp_debug_if, slots_11.io.out_uop.bp_debug_if \n connect issue_slots[11].out_uop.xcpt_ma_if, slots_11.io.out_uop.xcpt_ma_if \n connect issue_slots[11].out_uop.xcpt_ae_if, slots_11.io.out_uop.xcpt_ae_if \n connect issue_slots[11].out_uop.xcpt_pf_if, slots_11.io.out_uop.xcpt_pf_if \n connect issue_slots[11].out_uop.fp_typ, slots_11.io.out_uop.fp_typ \n connect issue_slots[11].out_uop.fp_rm, slots_11.io.out_uop.fp_rm \n connect issue_slots[11].out_uop.fp_val, slots_11.io.out_uop.fp_val \n connect issue_slots[11].out_uop.fcn_op, slots_11.io.out_uop.fcn_op \n connect issue_slots[11].out_uop.fcn_dw, slots_11.io.out_uop.fcn_dw \n connect issue_slots[11].out_uop.frs3_en, slots_11.io.out_uop.frs3_en \n connect issue_slots[11].out_uop.lrs2_rtype, slots_11.io.out_uop.lrs2_rtype \n connect issue_slots[11].out_uop.lrs1_rtype, slots_11.io.out_uop.lrs1_rtype \n connect issue_slots[11].out_uop.dst_rtype, slots_11.io.out_uop.dst_rtype \n connect issue_slots[11].out_uop.lrs3, slots_11.io.out_uop.lrs3 \n connect issue_slots[11].out_uop.lrs2, slots_11.io.out_uop.lrs2 \n connect issue_slots[11].out_uop.lrs1, slots_11.io.out_uop.lrs1 \n connect issue_slots[11].out_uop.ldst, slots_11.io.out_uop.ldst \n connect issue_slots[11].out_uop.ldst_is_rs1, slots_11.io.out_uop.ldst_is_rs1 \n connect issue_slots[11].out_uop.csr_cmd, slots_11.io.out_uop.csr_cmd \n connect issue_slots[11].out_uop.flush_on_commit, slots_11.io.out_uop.flush_on_commit \n connect issue_slots[11].out_uop.is_unique, slots_11.io.out_uop.is_unique \n connect issue_slots[11].out_uop.uses_stq, slots_11.io.out_uop.uses_stq \n connect issue_slots[11].out_uop.uses_ldq, slots_11.io.out_uop.uses_ldq \n connect issue_slots[11].out_uop.mem_signed, slots_11.io.out_uop.mem_signed \n connect issue_slots[11].out_uop.mem_size, slots_11.io.out_uop.mem_size \n connect issue_slots[11].out_uop.mem_cmd, slots_11.io.out_uop.mem_cmd \n connect issue_slots[11].out_uop.exc_cause, slots_11.io.out_uop.exc_cause \n connect issue_slots[11].out_uop.exception, slots_11.io.out_uop.exception \n connect issue_slots[11].out_uop.stale_pdst, slots_11.io.out_uop.stale_pdst \n connect issue_slots[11].out_uop.ppred_busy, slots_11.io.out_uop.ppred_busy \n connect issue_slots[11].out_uop.prs3_busy, slots_11.io.out_uop.prs3_busy \n connect issue_slots[11].out_uop.prs2_busy, slots_11.io.out_uop.prs2_busy \n connect issue_slots[11].out_uop.prs1_busy, slots_11.io.out_uop.prs1_busy \n connect issue_slots[11].out_uop.ppred, slots_11.io.out_uop.ppred \n connect issue_slots[11].out_uop.prs3, slots_11.io.out_uop.prs3 \n connect issue_slots[11].out_uop.prs2, slots_11.io.out_uop.prs2 \n connect issue_slots[11].out_uop.prs1, slots_11.io.out_uop.prs1 \n connect issue_slots[11].out_uop.pdst, slots_11.io.out_uop.pdst \n connect issue_slots[11].out_uop.rxq_idx, slots_11.io.out_uop.rxq_idx \n connect issue_slots[11].out_uop.stq_idx, slots_11.io.out_uop.stq_idx \n connect issue_slots[11].out_uop.ldq_idx, slots_11.io.out_uop.ldq_idx \n connect issue_slots[11].out_uop.rob_idx, slots_11.io.out_uop.rob_idx \n connect issue_slots[11].out_uop.fp_ctrl.vec, slots_11.io.out_uop.fp_ctrl.vec \n connect issue_slots[11].out_uop.fp_ctrl.wflags, slots_11.io.out_uop.fp_ctrl.wflags \n connect issue_slots[11].out_uop.fp_ctrl.sqrt, slots_11.io.out_uop.fp_ctrl.sqrt \n connect issue_slots[11].out_uop.fp_ctrl.div, slots_11.io.out_uop.fp_ctrl.div \n connect issue_slots[11].out_uop.fp_ctrl.fma, slots_11.io.out_uop.fp_ctrl.fma \n connect issue_slots[11].out_uop.fp_ctrl.fastpipe, slots_11.io.out_uop.fp_ctrl.fastpipe \n connect issue_slots[11].out_uop.fp_ctrl.toint, slots_11.io.out_uop.fp_ctrl.toint \n connect issue_slots[11].out_uop.fp_ctrl.fromint, slots_11.io.out_uop.fp_ctrl.fromint \n connect issue_slots[11].out_uop.fp_ctrl.typeTagOut, slots_11.io.out_uop.fp_ctrl.typeTagOut \n connect issue_slots[11].out_uop.fp_ctrl.typeTagIn, slots_11.io.out_uop.fp_ctrl.typeTagIn \n connect issue_slots[11].out_uop.fp_ctrl.swap23, slots_11.io.out_uop.fp_ctrl.swap23 \n connect issue_slots[11].out_uop.fp_ctrl.swap12, slots_11.io.out_uop.fp_ctrl.swap12 \n connect issue_slots[11].out_uop.fp_ctrl.ren3, slots_11.io.out_uop.fp_ctrl.ren3 \n connect issue_slots[11].out_uop.fp_ctrl.ren2, slots_11.io.out_uop.fp_ctrl.ren2 \n connect issue_slots[11].out_uop.fp_ctrl.ren1, slots_11.io.out_uop.fp_ctrl.ren1 \n connect issue_slots[11].out_uop.fp_ctrl.wen, slots_11.io.out_uop.fp_ctrl.wen \n connect issue_slots[11].out_uop.fp_ctrl.ldst, slots_11.io.out_uop.fp_ctrl.ldst \n connect issue_slots[11].out_uop.op2_sel, slots_11.io.out_uop.op2_sel \n connect issue_slots[11].out_uop.op1_sel, slots_11.io.out_uop.op1_sel \n connect issue_slots[11].out_uop.imm_packed, slots_11.io.out_uop.imm_packed \n connect issue_slots[11].out_uop.pimm, slots_11.io.out_uop.pimm \n connect issue_slots[11].out_uop.imm_sel, slots_11.io.out_uop.imm_sel \n connect issue_slots[11].out_uop.imm_rename, slots_11.io.out_uop.imm_rename \n connect issue_slots[11].out_uop.taken, slots_11.io.out_uop.taken \n connect issue_slots[11].out_uop.pc_lob, slots_11.io.out_uop.pc_lob \n connect issue_slots[11].out_uop.edge_inst, slots_11.io.out_uop.edge_inst \n connect issue_slots[11].out_uop.ftq_idx, slots_11.io.out_uop.ftq_idx \n connect issue_slots[11].out_uop.is_mov, slots_11.io.out_uop.is_mov \n connect issue_slots[11].out_uop.is_rocc, slots_11.io.out_uop.is_rocc \n connect issue_slots[11].out_uop.is_sys_pc2epc, slots_11.io.out_uop.is_sys_pc2epc \n connect issue_slots[11].out_uop.is_eret, slots_11.io.out_uop.is_eret \n connect issue_slots[11].out_uop.is_amo, slots_11.io.out_uop.is_amo \n connect issue_slots[11].out_uop.is_sfence, slots_11.io.out_uop.is_sfence \n connect issue_slots[11].out_uop.is_fencei, slots_11.io.out_uop.is_fencei \n connect issue_slots[11].out_uop.is_fence, slots_11.io.out_uop.is_fence \n connect issue_slots[11].out_uop.is_sfb, slots_11.io.out_uop.is_sfb \n connect issue_slots[11].out_uop.br_type, slots_11.io.out_uop.br_type \n connect issue_slots[11].out_uop.br_tag, slots_11.io.out_uop.br_tag \n connect issue_slots[11].out_uop.br_mask, slots_11.io.out_uop.br_mask \n connect issue_slots[11].out_uop.dis_col_sel, slots_11.io.out_uop.dis_col_sel \n connect issue_slots[11].out_uop.iw_p3_bypass_hint, slots_11.io.out_uop.iw_p3_bypass_hint \n connect issue_slots[11].out_uop.iw_p2_bypass_hint, slots_11.io.out_uop.iw_p2_bypass_hint \n connect issue_slots[11].out_uop.iw_p1_bypass_hint, slots_11.io.out_uop.iw_p1_bypass_hint \n connect issue_slots[11].out_uop.iw_p2_speculative_child, slots_11.io.out_uop.iw_p2_speculative_child \n connect issue_slots[11].out_uop.iw_p1_speculative_child, slots_11.io.out_uop.iw_p1_speculative_child \n connect issue_slots[11].out_uop.iw_issued_partial_dgen, slots_11.io.out_uop.iw_issued_partial_dgen \n connect issue_slots[11].out_uop.iw_issued_partial_agen, slots_11.io.out_uop.iw_issued_partial_agen \n connect issue_slots[11].out_uop.iw_issued, slots_11.io.out_uop.iw_issued \n connect issue_slots[11].out_uop.fu_code[0], slots_11.io.out_uop.fu_code[0] \n connect issue_slots[11].out_uop.fu_code[1], slots_11.io.out_uop.fu_code[1] \n connect issue_slots[11].out_uop.fu_code[2], slots_11.io.out_uop.fu_code[2] \n connect issue_slots[11].out_uop.fu_code[3], slots_11.io.out_uop.fu_code[3] \n connect issue_slots[11].out_uop.fu_code[4], slots_11.io.out_uop.fu_code[4] \n connect issue_slots[11].out_uop.fu_code[5], slots_11.io.out_uop.fu_code[5] \n connect issue_slots[11].out_uop.fu_code[6], slots_11.io.out_uop.fu_code[6] \n connect issue_slots[11].out_uop.fu_code[7], slots_11.io.out_uop.fu_code[7] \n connect issue_slots[11].out_uop.fu_code[8], slots_11.io.out_uop.fu_code[8] \n connect issue_slots[11].out_uop.fu_code[9], slots_11.io.out_uop.fu_code[9] \n connect issue_slots[11].out_uop.iq_type[0], slots_11.io.out_uop.iq_type[0] \n connect issue_slots[11].out_uop.iq_type[1], slots_11.io.out_uop.iq_type[1] \n connect issue_slots[11].out_uop.iq_type[2], slots_11.io.out_uop.iq_type[2] \n connect issue_slots[11].out_uop.iq_type[3], slots_11.io.out_uop.iq_type[3] \n connect issue_slots[11].out_uop.debug_pc, slots_11.io.out_uop.debug_pc \n connect issue_slots[11].out_uop.is_rvc, slots_11.io.out_uop.is_rvc \n connect issue_slots[11].out_uop.debug_inst, slots_11.io.out_uop.debug_inst \n connect issue_slots[11].out_uop.inst, slots_11.io.out_uop.inst \n connect slots_11.io.in_uop.bits.debug_tsrc, issue_slots[11].in_uop.bits.debug_tsrc \n connect slots_11.io.in_uop.bits.debug_fsrc, issue_slots[11].in_uop.bits.debug_fsrc \n connect slots_11.io.in_uop.bits.bp_xcpt_if, issue_slots[11].in_uop.bits.bp_xcpt_if \n connect slots_11.io.in_uop.bits.bp_debug_if, issue_slots[11].in_uop.bits.bp_debug_if \n connect slots_11.io.in_uop.bits.xcpt_ma_if, issue_slots[11].in_uop.bits.xcpt_ma_if \n connect slots_11.io.in_uop.bits.xcpt_ae_if, issue_slots[11].in_uop.bits.xcpt_ae_if \n connect slots_11.io.in_uop.bits.xcpt_pf_if, issue_slots[11].in_uop.bits.xcpt_pf_if \n connect slots_11.io.in_uop.bits.fp_typ, issue_slots[11].in_uop.bits.fp_typ \n connect slots_11.io.in_uop.bits.fp_rm, issue_slots[11].in_uop.bits.fp_rm \n connect slots_11.io.in_uop.bits.fp_val, issue_slots[11].in_uop.bits.fp_val \n connect slots_11.io.in_uop.bits.fcn_op, issue_slots[11].in_uop.bits.fcn_op \n connect slots_11.io.in_uop.bits.fcn_dw, issue_slots[11].in_uop.bits.fcn_dw \n connect slots_11.io.in_uop.bits.frs3_en, issue_slots[11].in_uop.bits.frs3_en \n connect slots_11.io.in_uop.bits.lrs2_rtype, issue_slots[11].in_uop.bits.lrs2_rtype \n connect slots_11.io.in_uop.bits.lrs1_rtype, issue_slots[11].in_uop.bits.lrs1_rtype \n connect slots_11.io.in_uop.bits.dst_rtype, issue_slots[11].in_uop.bits.dst_rtype \n connect slots_11.io.in_uop.bits.lrs3, issue_slots[11].in_uop.bits.lrs3 \n connect slots_11.io.in_uop.bits.lrs2, issue_slots[11].in_uop.bits.lrs2 \n connect slots_11.io.in_uop.bits.lrs1, issue_slots[11].in_uop.bits.lrs1 \n connect slots_11.io.in_uop.bits.ldst, issue_slots[11].in_uop.bits.ldst \n connect slots_11.io.in_uop.bits.ldst_is_rs1, issue_slots[11].in_uop.bits.ldst_is_rs1 \n connect slots_11.io.in_uop.bits.csr_cmd, issue_slots[11].in_uop.bits.csr_cmd \n connect slots_11.io.in_uop.bits.flush_on_commit, issue_slots[11].in_uop.bits.flush_on_commit \n connect slots_11.io.in_uop.bits.is_unique, issue_slots[11].in_uop.bits.is_unique \n connect slots_11.io.in_uop.bits.uses_stq, issue_slots[11].in_uop.bits.uses_stq \n connect slots_11.io.in_uop.bits.uses_ldq, issue_slots[11].in_uop.bits.uses_ldq \n connect slots_11.io.in_uop.bits.mem_signed, issue_slots[11].in_uop.bits.mem_signed \n connect slots_11.io.in_uop.bits.mem_size, issue_slots[11].in_uop.bits.mem_size \n connect slots_11.io.in_uop.bits.mem_cmd, issue_slots[11].in_uop.bits.mem_cmd \n connect slots_11.io.in_uop.bits.exc_cause, issue_slots[11].in_uop.bits.exc_cause \n connect slots_11.io.in_uop.bits.exception, issue_slots[11].in_uop.bits.exception \n connect slots_11.io.in_uop.bits.stale_pdst, issue_slots[11].in_uop.bits.stale_pdst \n connect slots_11.io.in_uop.bits.ppred_busy, issue_slots[11].in_uop.bits.ppred_busy \n connect slots_11.io.in_uop.bits.prs3_busy, issue_slots[11].in_uop.bits.prs3_busy \n connect slots_11.io.in_uop.bits.prs2_busy, issue_slots[11].in_uop.bits.prs2_busy \n connect slots_11.io.in_uop.bits.prs1_busy, issue_slots[11].in_uop.bits.prs1_busy \n connect slots_11.io.in_uop.bits.ppred, issue_slots[11].in_uop.bits.ppred \n connect slots_11.io.in_uop.bits.prs3, issue_slots[11].in_uop.bits.prs3 \n connect slots_11.io.in_uop.bits.prs2, issue_slots[11].in_uop.bits.prs2 \n connect slots_11.io.in_uop.bits.prs1, issue_slots[11].in_uop.bits.prs1 \n connect slots_11.io.in_uop.bits.pdst, issue_slots[11].in_uop.bits.pdst \n connect slots_11.io.in_uop.bits.rxq_idx, issue_slots[11].in_uop.bits.rxq_idx \n connect slots_11.io.in_uop.bits.stq_idx, issue_slots[11].in_uop.bits.stq_idx \n connect slots_11.io.in_uop.bits.ldq_idx, issue_slots[11].in_uop.bits.ldq_idx \n connect slots_11.io.in_uop.bits.rob_idx, issue_slots[11].in_uop.bits.rob_idx \n connect slots_11.io.in_uop.bits.fp_ctrl.vec, issue_slots[11].in_uop.bits.fp_ctrl.vec \n connect slots_11.io.in_uop.bits.fp_ctrl.wflags, issue_slots[11].in_uop.bits.fp_ctrl.wflags \n connect slots_11.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[11].in_uop.bits.fp_ctrl.sqrt \n connect slots_11.io.in_uop.bits.fp_ctrl.div, issue_slots[11].in_uop.bits.fp_ctrl.div \n connect slots_11.io.in_uop.bits.fp_ctrl.fma, issue_slots[11].in_uop.bits.fp_ctrl.fma \n connect slots_11.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[11].in_uop.bits.fp_ctrl.fastpipe \n connect slots_11.io.in_uop.bits.fp_ctrl.toint, issue_slots[11].in_uop.bits.fp_ctrl.toint \n connect slots_11.io.in_uop.bits.fp_ctrl.fromint, issue_slots[11].in_uop.bits.fp_ctrl.fromint \n connect slots_11.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[11].in_uop.bits.fp_ctrl.typeTagOut \n connect slots_11.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[11].in_uop.bits.fp_ctrl.typeTagIn \n connect slots_11.io.in_uop.bits.fp_ctrl.swap23, issue_slots[11].in_uop.bits.fp_ctrl.swap23 \n connect slots_11.io.in_uop.bits.fp_ctrl.swap12, issue_slots[11].in_uop.bits.fp_ctrl.swap12 \n connect slots_11.io.in_uop.bits.fp_ctrl.ren3, issue_slots[11].in_uop.bits.fp_ctrl.ren3 \n connect slots_11.io.in_uop.bits.fp_ctrl.ren2, issue_slots[11].in_uop.bits.fp_ctrl.ren2 \n connect slots_11.io.in_uop.bits.fp_ctrl.ren1, issue_slots[11].in_uop.bits.fp_ctrl.ren1 \n connect slots_11.io.in_uop.bits.fp_ctrl.wen, issue_slots[11].in_uop.bits.fp_ctrl.wen \n connect slots_11.io.in_uop.bits.fp_ctrl.ldst, issue_slots[11].in_uop.bits.fp_ctrl.ldst \n connect slots_11.io.in_uop.bits.op2_sel, issue_slots[11].in_uop.bits.op2_sel \n connect slots_11.io.in_uop.bits.op1_sel, issue_slots[11].in_uop.bits.op1_sel \n connect slots_11.io.in_uop.bits.imm_packed, issue_slots[11].in_uop.bits.imm_packed \n connect slots_11.io.in_uop.bits.pimm, issue_slots[11].in_uop.bits.pimm \n connect slots_11.io.in_uop.bits.imm_sel, issue_slots[11].in_uop.bits.imm_sel \n connect slots_11.io.in_uop.bits.imm_rename, issue_slots[11].in_uop.bits.imm_rename \n connect slots_11.io.in_uop.bits.taken, issue_slots[11].in_uop.bits.taken \n connect slots_11.io.in_uop.bits.pc_lob, issue_slots[11].in_uop.bits.pc_lob \n connect slots_11.io.in_uop.bits.edge_inst, issue_slots[11].in_uop.bits.edge_inst \n connect slots_11.io.in_uop.bits.ftq_idx, issue_slots[11].in_uop.bits.ftq_idx \n connect slots_11.io.in_uop.bits.is_mov, issue_slots[11].in_uop.bits.is_mov \n connect slots_11.io.in_uop.bits.is_rocc, issue_slots[11].in_uop.bits.is_rocc \n connect slots_11.io.in_uop.bits.is_sys_pc2epc, issue_slots[11].in_uop.bits.is_sys_pc2epc \n connect slots_11.io.in_uop.bits.is_eret, issue_slots[11].in_uop.bits.is_eret \n connect slots_11.io.in_uop.bits.is_amo, issue_slots[11].in_uop.bits.is_amo \n connect slots_11.io.in_uop.bits.is_sfence, issue_slots[11].in_uop.bits.is_sfence \n connect slots_11.io.in_uop.bits.is_fencei, issue_slots[11].in_uop.bits.is_fencei \n connect slots_11.io.in_uop.bits.is_fence, issue_slots[11].in_uop.bits.is_fence \n connect slots_11.io.in_uop.bits.is_sfb, issue_slots[11].in_uop.bits.is_sfb \n connect slots_11.io.in_uop.bits.br_type, issue_slots[11].in_uop.bits.br_type \n connect slots_11.io.in_uop.bits.br_tag, issue_slots[11].in_uop.bits.br_tag \n connect slots_11.io.in_uop.bits.br_mask, issue_slots[11].in_uop.bits.br_mask \n connect slots_11.io.in_uop.bits.dis_col_sel, issue_slots[11].in_uop.bits.dis_col_sel \n connect slots_11.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[11].in_uop.bits.iw_p3_bypass_hint \n connect slots_11.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[11].in_uop.bits.iw_p2_bypass_hint \n connect slots_11.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[11].in_uop.bits.iw_p1_bypass_hint \n connect slots_11.io.in_uop.bits.iw_p2_speculative_child, issue_slots[11].in_uop.bits.iw_p2_speculative_child \n connect slots_11.io.in_uop.bits.iw_p1_speculative_child, issue_slots[11].in_uop.bits.iw_p1_speculative_child \n connect slots_11.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[11].in_uop.bits.iw_issued_partial_dgen \n connect slots_11.io.in_uop.bits.iw_issued_partial_agen, issue_slots[11].in_uop.bits.iw_issued_partial_agen \n connect slots_11.io.in_uop.bits.iw_issued, issue_slots[11].in_uop.bits.iw_issued \n connect slots_11.io.in_uop.bits.fu_code[0], issue_slots[11].in_uop.bits.fu_code[0] \n connect slots_11.io.in_uop.bits.fu_code[1], issue_slots[11].in_uop.bits.fu_code[1] \n connect slots_11.io.in_uop.bits.fu_code[2], issue_slots[11].in_uop.bits.fu_code[2] \n connect slots_11.io.in_uop.bits.fu_code[3], issue_slots[11].in_uop.bits.fu_code[3] \n connect slots_11.io.in_uop.bits.fu_code[4], issue_slots[11].in_uop.bits.fu_code[4] \n connect slots_11.io.in_uop.bits.fu_code[5], issue_slots[11].in_uop.bits.fu_code[5] \n connect slots_11.io.in_uop.bits.fu_code[6], issue_slots[11].in_uop.bits.fu_code[6] \n connect slots_11.io.in_uop.bits.fu_code[7], issue_slots[11].in_uop.bits.fu_code[7] \n connect slots_11.io.in_uop.bits.fu_code[8], issue_slots[11].in_uop.bits.fu_code[8] \n connect slots_11.io.in_uop.bits.fu_code[9], issue_slots[11].in_uop.bits.fu_code[9] \n connect slots_11.io.in_uop.bits.iq_type[0], issue_slots[11].in_uop.bits.iq_type[0] \n connect slots_11.io.in_uop.bits.iq_type[1], issue_slots[11].in_uop.bits.iq_type[1] \n connect slots_11.io.in_uop.bits.iq_type[2], issue_slots[11].in_uop.bits.iq_type[2] \n connect slots_11.io.in_uop.bits.iq_type[3], issue_slots[11].in_uop.bits.iq_type[3] \n connect slots_11.io.in_uop.bits.debug_pc, issue_slots[11].in_uop.bits.debug_pc \n connect slots_11.io.in_uop.bits.is_rvc, issue_slots[11].in_uop.bits.is_rvc \n connect slots_11.io.in_uop.bits.debug_inst, issue_slots[11].in_uop.bits.debug_inst \n connect slots_11.io.in_uop.bits.inst, issue_slots[11].in_uop.bits.inst \n connect slots_11.io.in_uop.valid, issue_slots[11].in_uop.valid \n connect issue_slots[11].iss_uop.debug_tsrc, slots_11.io.iss_uop.debug_tsrc \n connect issue_slots[11].iss_uop.debug_fsrc, slots_11.io.iss_uop.debug_fsrc \n connect issue_slots[11].iss_uop.bp_xcpt_if, slots_11.io.iss_uop.bp_xcpt_if \n connect issue_slots[11].iss_uop.bp_debug_if, slots_11.io.iss_uop.bp_debug_if \n connect issue_slots[11].iss_uop.xcpt_ma_if, slots_11.io.iss_uop.xcpt_ma_if \n connect issue_slots[11].iss_uop.xcpt_ae_if, slots_11.io.iss_uop.xcpt_ae_if \n connect issue_slots[11].iss_uop.xcpt_pf_if, slots_11.io.iss_uop.xcpt_pf_if \n connect issue_slots[11].iss_uop.fp_typ, slots_11.io.iss_uop.fp_typ \n connect issue_slots[11].iss_uop.fp_rm, slots_11.io.iss_uop.fp_rm \n connect issue_slots[11].iss_uop.fp_val, slots_11.io.iss_uop.fp_val \n connect issue_slots[11].iss_uop.fcn_op, slots_11.io.iss_uop.fcn_op \n connect issue_slots[11].iss_uop.fcn_dw, slots_11.io.iss_uop.fcn_dw \n connect issue_slots[11].iss_uop.frs3_en, slots_11.io.iss_uop.frs3_en \n connect issue_slots[11].iss_uop.lrs2_rtype, slots_11.io.iss_uop.lrs2_rtype \n connect issue_slots[11].iss_uop.lrs1_rtype, slots_11.io.iss_uop.lrs1_rtype \n connect issue_slots[11].iss_uop.dst_rtype, slots_11.io.iss_uop.dst_rtype \n connect issue_slots[11].iss_uop.lrs3, slots_11.io.iss_uop.lrs3 \n connect issue_slots[11].iss_uop.lrs2, slots_11.io.iss_uop.lrs2 \n connect issue_slots[11].iss_uop.lrs1, slots_11.io.iss_uop.lrs1 \n connect issue_slots[11].iss_uop.ldst, slots_11.io.iss_uop.ldst \n connect issue_slots[11].iss_uop.ldst_is_rs1, slots_11.io.iss_uop.ldst_is_rs1 \n connect issue_slots[11].iss_uop.csr_cmd, slots_11.io.iss_uop.csr_cmd \n connect issue_slots[11].iss_uop.flush_on_commit, slots_11.io.iss_uop.flush_on_commit \n connect issue_slots[11].iss_uop.is_unique, slots_11.io.iss_uop.is_unique \n connect issue_slots[11].iss_uop.uses_stq, slots_11.io.iss_uop.uses_stq \n connect issue_slots[11].iss_uop.uses_ldq, slots_11.io.iss_uop.uses_ldq \n connect issue_slots[11].iss_uop.mem_signed, slots_11.io.iss_uop.mem_signed \n connect issue_slots[11].iss_uop.mem_size, slots_11.io.iss_uop.mem_size \n connect issue_slots[11].iss_uop.mem_cmd, slots_11.io.iss_uop.mem_cmd \n connect issue_slots[11].iss_uop.exc_cause, slots_11.io.iss_uop.exc_cause \n connect issue_slots[11].iss_uop.exception, slots_11.io.iss_uop.exception \n connect issue_slots[11].iss_uop.stale_pdst, slots_11.io.iss_uop.stale_pdst \n connect issue_slots[11].iss_uop.ppred_busy, slots_11.io.iss_uop.ppred_busy \n connect issue_slots[11].iss_uop.prs3_busy, slots_11.io.iss_uop.prs3_busy \n connect issue_slots[11].iss_uop.prs2_busy, slots_11.io.iss_uop.prs2_busy \n connect issue_slots[11].iss_uop.prs1_busy, slots_11.io.iss_uop.prs1_busy \n connect issue_slots[11].iss_uop.ppred, slots_11.io.iss_uop.ppred \n connect issue_slots[11].iss_uop.prs3, slots_11.io.iss_uop.prs3 \n connect issue_slots[11].iss_uop.prs2, slots_11.io.iss_uop.prs2 \n connect issue_slots[11].iss_uop.prs1, slots_11.io.iss_uop.prs1 \n connect issue_slots[11].iss_uop.pdst, slots_11.io.iss_uop.pdst \n connect issue_slots[11].iss_uop.rxq_idx, slots_11.io.iss_uop.rxq_idx \n connect issue_slots[11].iss_uop.stq_idx, slots_11.io.iss_uop.stq_idx \n connect issue_slots[11].iss_uop.ldq_idx, slots_11.io.iss_uop.ldq_idx \n connect issue_slots[11].iss_uop.rob_idx, slots_11.io.iss_uop.rob_idx \n connect issue_slots[11].iss_uop.fp_ctrl.vec, slots_11.io.iss_uop.fp_ctrl.vec \n connect issue_slots[11].iss_uop.fp_ctrl.wflags, slots_11.io.iss_uop.fp_ctrl.wflags \n connect issue_slots[11].iss_uop.fp_ctrl.sqrt, slots_11.io.iss_uop.fp_ctrl.sqrt \n connect issue_slots[11].iss_uop.fp_ctrl.div, slots_11.io.iss_uop.fp_ctrl.div \n connect issue_slots[11].iss_uop.fp_ctrl.fma, slots_11.io.iss_uop.fp_ctrl.fma \n connect issue_slots[11].iss_uop.fp_ctrl.fastpipe, slots_11.io.iss_uop.fp_ctrl.fastpipe \n connect issue_slots[11].iss_uop.fp_ctrl.toint, slots_11.io.iss_uop.fp_ctrl.toint \n connect issue_slots[11].iss_uop.fp_ctrl.fromint, slots_11.io.iss_uop.fp_ctrl.fromint \n connect issue_slots[11].iss_uop.fp_ctrl.typeTagOut, slots_11.io.iss_uop.fp_ctrl.typeTagOut \n connect issue_slots[11].iss_uop.fp_ctrl.typeTagIn, slots_11.io.iss_uop.fp_ctrl.typeTagIn \n connect issue_slots[11].iss_uop.fp_ctrl.swap23, slots_11.io.iss_uop.fp_ctrl.swap23 \n connect issue_slots[11].iss_uop.fp_ctrl.swap12, slots_11.io.iss_uop.fp_ctrl.swap12 \n connect issue_slots[11].iss_uop.fp_ctrl.ren3, slots_11.io.iss_uop.fp_ctrl.ren3 \n connect issue_slots[11].iss_uop.fp_ctrl.ren2, slots_11.io.iss_uop.fp_ctrl.ren2 \n connect issue_slots[11].iss_uop.fp_ctrl.ren1, slots_11.io.iss_uop.fp_ctrl.ren1 \n connect issue_slots[11].iss_uop.fp_ctrl.wen, slots_11.io.iss_uop.fp_ctrl.wen \n connect issue_slots[11].iss_uop.fp_ctrl.ldst, slots_11.io.iss_uop.fp_ctrl.ldst \n connect issue_slots[11].iss_uop.op2_sel, slots_11.io.iss_uop.op2_sel \n connect issue_slots[11].iss_uop.op1_sel, slots_11.io.iss_uop.op1_sel \n connect issue_slots[11].iss_uop.imm_packed, slots_11.io.iss_uop.imm_packed \n connect issue_slots[11].iss_uop.pimm, slots_11.io.iss_uop.pimm \n connect issue_slots[11].iss_uop.imm_sel, slots_11.io.iss_uop.imm_sel \n connect issue_slots[11].iss_uop.imm_rename, slots_11.io.iss_uop.imm_rename \n connect issue_slots[11].iss_uop.taken, slots_11.io.iss_uop.taken \n connect issue_slots[11].iss_uop.pc_lob, slots_11.io.iss_uop.pc_lob \n connect issue_slots[11].iss_uop.edge_inst, slots_11.io.iss_uop.edge_inst \n connect issue_slots[11].iss_uop.ftq_idx, slots_11.io.iss_uop.ftq_idx \n connect issue_slots[11].iss_uop.is_mov, slots_11.io.iss_uop.is_mov \n connect issue_slots[11].iss_uop.is_rocc, slots_11.io.iss_uop.is_rocc \n connect issue_slots[11].iss_uop.is_sys_pc2epc, slots_11.io.iss_uop.is_sys_pc2epc \n connect issue_slots[11].iss_uop.is_eret, slots_11.io.iss_uop.is_eret \n connect issue_slots[11].iss_uop.is_amo, slots_11.io.iss_uop.is_amo \n connect issue_slots[11].iss_uop.is_sfence, slots_11.io.iss_uop.is_sfence \n connect issue_slots[11].iss_uop.is_fencei, slots_11.io.iss_uop.is_fencei \n connect issue_slots[11].iss_uop.is_fence, slots_11.io.iss_uop.is_fence \n connect issue_slots[11].iss_uop.is_sfb, slots_11.io.iss_uop.is_sfb \n connect issue_slots[11].iss_uop.br_type, slots_11.io.iss_uop.br_type \n connect issue_slots[11].iss_uop.br_tag, slots_11.io.iss_uop.br_tag \n connect issue_slots[11].iss_uop.br_mask, slots_11.io.iss_uop.br_mask \n connect issue_slots[11].iss_uop.dis_col_sel, slots_11.io.iss_uop.dis_col_sel \n connect issue_slots[11].iss_uop.iw_p3_bypass_hint, slots_11.io.iss_uop.iw_p3_bypass_hint \n connect issue_slots[11].iss_uop.iw_p2_bypass_hint, slots_11.io.iss_uop.iw_p2_bypass_hint \n connect issue_slots[11].iss_uop.iw_p1_bypass_hint, slots_11.io.iss_uop.iw_p1_bypass_hint \n connect issue_slots[11].iss_uop.iw_p2_speculative_child, slots_11.io.iss_uop.iw_p2_speculative_child \n connect issue_slots[11].iss_uop.iw_p1_speculative_child, slots_11.io.iss_uop.iw_p1_speculative_child \n connect issue_slots[11].iss_uop.iw_issued_partial_dgen, slots_11.io.iss_uop.iw_issued_partial_dgen \n connect issue_slots[11].iss_uop.iw_issued_partial_agen, slots_11.io.iss_uop.iw_issued_partial_agen \n connect issue_slots[11].iss_uop.iw_issued, slots_11.io.iss_uop.iw_issued \n connect issue_slots[11].iss_uop.fu_code[0], slots_11.io.iss_uop.fu_code[0] \n connect issue_slots[11].iss_uop.fu_code[1], slots_11.io.iss_uop.fu_code[1] \n connect issue_slots[11].iss_uop.fu_code[2], slots_11.io.iss_uop.fu_code[2] \n connect issue_slots[11].iss_uop.fu_code[3], slots_11.io.iss_uop.fu_code[3] \n connect issue_slots[11].iss_uop.fu_code[4], slots_11.io.iss_uop.fu_code[4] \n connect issue_slots[11].iss_uop.fu_code[5], slots_11.io.iss_uop.fu_code[5] \n connect issue_slots[11].iss_uop.fu_code[6], slots_11.io.iss_uop.fu_code[6] \n connect issue_slots[11].iss_uop.fu_code[7], slots_11.io.iss_uop.fu_code[7] \n connect issue_slots[11].iss_uop.fu_code[8], slots_11.io.iss_uop.fu_code[8] \n connect issue_slots[11].iss_uop.fu_code[9], slots_11.io.iss_uop.fu_code[9] \n connect issue_slots[11].iss_uop.iq_type[0], slots_11.io.iss_uop.iq_type[0] \n connect issue_slots[11].iss_uop.iq_type[1], slots_11.io.iss_uop.iq_type[1] \n connect issue_slots[11].iss_uop.iq_type[2], slots_11.io.iss_uop.iq_type[2] \n connect issue_slots[11].iss_uop.iq_type[3], slots_11.io.iss_uop.iq_type[3] \n connect issue_slots[11].iss_uop.debug_pc, slots_11.io.iss_uop.debug_pc \n connect issue_slots[11].iss_uop.is_rvc, slots_11.io.iss_uop.is_rvc \n connect issue_slots[11].iss_uop.debug_inst, slots_11.io.iss_uop.debug_inst \n connect issue_slots[11].iss_uop.inst, slots_11.io.iss_uop.inst \n connect slots_11.io.grant, issue_slots[11].grant \n connect issue_slots[11].request, slots_11.io.request \n connect issue_slots[11].will_be_valid, slots_11.io.will_be_valid \n connect issue_slots[11].valid, slots_11.io.valid \n connect slots_12.io.child_rebusys, issue_slots[12].child_rebusys \n connect slots_12.io.pred_wakeup_port.bits, issue_slots[12].pred_wakeup_port.bits \n connect slots_12.io.pred_wakeup_port.valid, issue_slots[12].pred_wakeup_port.valid \n connect slots_12.io.wakeup_ports[0].bits.rebusy, issue_slots[12].wakeup_ports[0].bits.rebusy \n connect slots_12.io.wakeup_ports[0].bits.speculative_mask, issue_slots[12].wakeup_ports[0].bits.speculative_mask \n connect slots_12.io.wakeup_ports[0].bits.bypassable, issue_slots[12].wakeup_ports[0].bits.bypassable \n connect slots_12.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[12].wakeup_ports[0].bits.uop.debug_tsrc \n connect slots_12.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[12].wakeup_ports[0].bits.uop.debug_fsrc \n connect slots_12.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[12].wakeup_ports[0].bits.uop.bp_xcpt_if \n connect slots_12.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[12].wakeup_ports[0].bits.uop.bp_debug_if \n connect slots_12.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[12].wakeup_ports[0].bits.uop.xcpt_ma_if \n connect slots_12.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[12].wakeup_ports[0].bits.uop.xcpt_ae_if \n connect slots_12.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[12].wakeup_ports[0].bits.uop.xcpt_pf_if \n connect slots_12.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[12].wakeup_ports[0].bits.uop.fp_typ \n connect slots_12.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[12].wakeup_ports[0].bits.uop.fp_rm \n connect slots_12.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[12].wakeup_ports[0].bits.uop.fp_val \n connect slots_12.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[12].wakeup_ports[0].bits.uop.fcn_op \n connect slots_12.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[12].wakeup_ports[0].bits.uop.fcn_dw \n connect slots_12.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[12].wakeup_ports[0].bits.uop.frs3_en \n connect slots_12.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[12].wakeup_ports[0].bits.uop.lrs2_rtype \n connect slots_12.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[12].wakeup_ports[0].bits.uop.lrs1_rtype \n connect slots_12.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[12].wakeup_ports[0].bits.uop.dst_rtype \n connect slots_12.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[12].wakeup_ports[0].bits.uop.lrs3 \n connect slots_12.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[12].wakeup_ports[0].bits.uop.lrs2 \n connect slots_12.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[12].wakeup_ports[0].bits.uop.lrs1 \n connect slots_12.io.wakeup_ports[0].bits.uop.ldst, issue_slots[12].wakeup_ports[0].bits.uop.ldst \n connect slots_12.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[12].wakeup_ports[0].bits.uop.ldst_is_rs1 \n connect slots_12.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[12].wakeup_ports[0].bits.uop.csr_cmd \n connect slots_12.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[12].wakeup_ports[0].bits.uop.flush_on_commit \n connect slots_12.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[12].wakeup_ports[0].bits.uop.is_unique \n connect slots_12.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[12].wakeup_ports[0].bits.uop.uses_stq \n connect slots_12.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[12].wakeup_ports[0].bits.uop.uses_ldq \n connect slots_12.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[12].wakeup_ports[0].bits.uop.mem_signed \n connect slots_12.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[12].wakeup_ports[0].bits.uop.mem_size \n connect slots_12.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[12].wakeup_ports[0].bits.uop.mem_cmd \n connect slots_12.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[12].wakeup_ports[0].bits.uop.exc_cause \n connect slots_12.io.wakeup_ports[0].bits.uop.exception, issue_slots[12].wakeup_ports[0].bits.uop.exception \n connect slots_12.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[12].wakeup_ports[0].bits.uop.stale_pdst \n connect slots_12.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[12].wakeup_ports[0].bits.uop.ppred_busy \n connect slots_12.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[12].wakeup_ports[0].bits.uop.prs3_busy \n connect slots_12.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[12].wakeup_ports[0].bits.uop.prs2_busy \n connect slots_12.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[12].wakeup_ports[0].bits.uop.prs1_busy \n connect slots_12.io.wakeup_ports[0].bits.uop.ppred, issue_slots[12].wakeup_ports[0].bits.uop.ppred \n connect slots_12.io.wakeup_ports[0].bits.uop.prs3, issue_slots[12].wakeup_ports[0].bits.uop.prs3 \n connect slots_12.io.wakeup_ports[0].bits.uop.prs2, issue_slots[12].wakeup_ports[0].bits.uop.prs2 \n connect slots_12.io.wakeup_ports[0].bits.uop.prs1, issue_slots[12].wakeup_ports[0].bits.uop.prs1 \n connect slots_12.io.wakeup_ports[0].bits.uop.pdst, issue_slots[12].wakeup_ports[0].bits.uop.pdst \n connect slots_12.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[12].wakeup_ports[0].bits.uop.rxq_idx \n connect slots_12.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[12].wakeup_ports[0].bits.uop.stq_idx \n connect slots_12.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[12].wakeup_ports[0].bits.uop.ldq_idx \n connect slots_12.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[12].wakeup_ports[0].bits.uop.rob_idx \n connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.vec \n connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.wflags \n connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.sqrt \n connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.div \n connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.fma \n connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe \n connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.toint \n connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.fromint \n connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut \n connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn \n connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.swap23 \n connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.swap12 \n connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.ren3 \n connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.ren2 \n connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.ren1 \n connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.wen \n connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.ldst \n connect slots_12.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[12].wakeup_ports[0].bits.uop.op2_sel \n connect slots_12.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[12].wakeup_ports[0].bits.uop.op1_sel \n connect slots_12.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[12].wakeup_ports[0].bits.uop.imm_packed \n connect slots_12.io.wakeup_ports[0].bits.uop.pimm, issue_slots[12].wakeup_ports[0].bits.uop.pimm \n connect slots_12.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[12].wakeup_ports[0].bits.uop.imm_sel \n connect slots_12.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[12].wakeup_ports[0].bits.uop.imm_rename \n connect slots_12.io.wakeup_ports[0].bits.uop.taken, issue_slots[12].wakeup_ports[0].bits.uop.taken \n connect slots_12.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[12].wakeup_ports[0].bits.uop.pc_lob \n connect slots_12.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[12].wakeup_ports[0].bits.uop.edge_inst \n connect slots_12.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[12].wakeup_ports[0].bits.uop.ftq_idx \n connect slots_12.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[12].wakeup_ports[0].bits.uop.is_mov \n connect slots_12.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[12].wakeup_ports[0].bits.uop.is_rocc \n connect slots_12.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[12].wakeup_ports[0].bits.uop.is_sys_pc2epc \n connect slots_12.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[12].wakeup_ports[0].bits.uop.is_eret \n connect slots_12.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[12].wakeup_ports[0].bits.uop.is_amo \n connect slots_12.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[12].wakeup_ports[0].bits.uop.is_sfence \n connect slots_12.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[12].wakeup_ports[0].bits.uop.is_fencei \n connect slots_12.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[12].wakeup_ports[0].bits.uop.is_fence \n connect slots_12.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[12].wakeup_ports[0].bits.uop.is_sfb \n connect slots_12.io.wakeup_ports[0].bits.uop.br_type, issue_slots[12].wakeup_ports[0].bits.uop.br_type \n connect slots_12.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[12].wakeup_ports[0].bits.uop.br_tag \n connect slots_12.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[12].wakeup_ports[0].bits.uop.br_mask \n connect slots_12.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[12].wakeup_ports[0].bits.uop.dis_col_sel \n connect slots_12.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[12].wakeup_ports[0].bits.uop.iw_p3_bypass_hint \n connect slots_12.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[12].wakeup_ports[0].bits.uop.iw_p2_bypass_hint \n connect slots_12.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[12].wakeup_ports[0].bits.uop.iw_p1_bypass_hint \n connect slots_12.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[12].wakeup_ports[0].bits.uop.iw_p2_speculative_child \n connect slots_12.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[12].wakeup_ports[0].bits.uop.iw_p1_speculative_child \n connect slots_12.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[12].wakeup_ports[0].bits.uop.iw_issued_partial_dgen \n connect slots_12.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[12].wakeup_ports[0].bits.uop.iw_issued_partial_agen \n connect slots_12.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[12].wakeup_ports[0].bits.uop.iw_issued \n connect slots_12.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[12].wakeup_ports[0].bits.uop.fu_code[0] \n connect slots_12.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[12].wakeup_ports[0].bits.uop.fu_code[1] \n connect slots_12.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[12].wakeup_ports[0].bits.uop.fu_code[2] \n connect slots_12.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[12].wakeup_ports[0].bits.uop.fu_code[3] \n connect slots_12.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[12].wakeup_ports[0].bits.uop.fu_code[4] \n connect slots_12.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[12].wakeup_ports[0].bits.uop.fu_code[5] \n connect slots_12.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[12].wakeup_ports[0].bits.uop.fu_code[6] \n connect slots_12.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[12].wakeup_ports[0].bits.uop.fu_code[7] \n connect slots_12.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[12].wakeup_ports[0].bits.uop.fu_code[8] \n connect slots_12.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[12].wakeup_ports[0].bits.uop.fu_code[9] \n connect slots_12.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[12].wakeup_ports[0].bits.uop.iq_type[0] \n connect slots_12.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[12].wakeup_ports[0].bits.uop.iq_type[1] \n connect slots_12.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[12].wakeup_ports[0].bits.uop.iq_type[2] \n connect slots_12.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[12].wakeup_ports[0].bits.uop.iq_type[3] \n connect slots_12.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[12].wakeup_ports[0].bits.uop.debug_pc \n connect slots_12.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[12].wakeup_ports[0].bits.uop.is_rvc \n connect slots_12.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[12].wakeup_ports[0].bits.uop.debug_inst \n connect slots_12.io.wakeup_ports[0].bits.uop.inst, issue_slots[12].wakeup_ports[0].bits.uop.inst \n connect slots_12.io.wakeup_ports[0].valid, issue_slots[12].wakeup_ports[0].valid \n connect slots_12.io.wakeup_ports[1].bits.rebusy, issue_slots[12].wakeup_ports[1].bits.rebusy \n connect slots_12.io.wakeup_ports[1].bits.speculative_mask, issue_slots[12].wakeup_ports[1].bits.speculative_mask \n connect slots_12.io.wakeup_ports[1].bits.bypassable, issue_slots[12].wakeup_ports[1].bits.bypassable \n connect slots_12.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[12].wakeup_ports[1].bits.uop.debug_tsrc \n connect slots_12.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[12].wakeup_ports[1].bits.uop.debug_fsrc \n connect slots_12.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[12].wakeup_ports[1].bits.uop.bp_xcpt_if \n connect slots_12.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[12].wakeup_ports[1].bits.uop.bp_debug_if \n connect slots_12.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[12].wakeup_ports[1].bits.uop.xcpt_ma_if \n connect slots_12.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[12].wakeup_ports[1].bits.uop.xcpt_ae_if \n connect slots_12.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[12].wakeup_ports[1].bits.uop.xcpt_pf_if \n connect slots_12.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[12].wakeup_ports[1].bits.uop.fp_typ \n connect slots_12.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[12].wakeup_ports[1].bits.uop.fp_rm \n connect slots_12.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[12].wakeup_ports[1].bits.uop.fp_val \n connect slots_12.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[12].wakeup_ports[1].bits.uop.fcn_op \n connect slots_12.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[12].wakeup_ports[1].bits.uop.fcn_dw \n connect slots_12.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[12].wakeup_ports[1].bits.uop.frs3_en \n connect slots_12.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[12].wakeup_ports[1].bits.uop.lrs2_rtype \n connect slots_12.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[12].wakeup_ports[1].bits.uop.lrs1_rtype \n connect slots_12.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[12].wakeup_ports[1].bits.uop.dst_rtype \n connect slots_12.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[12].wakeup_ports[1].bits.uop.lrs3 \n connect slots_12.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[12].wakeup_ports[1].bits.uop.lrs2 \n connect slots_12.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[12].wakeup_ports[1].bits.uop.lrs1 \n connect slots_12.io.wakeup_ports[1].bits.uop.ldst, issue_slots[12].wakeup_ports[1].bits.uop.ldst \n connect slots_12.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[12].wakeup_ports[1].bits.uop.ldst_is_rs1 \n connect slots_12.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[12].wakeup_ports[1].bits.uop.csr_cmd \n connect slots_12.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[12].wakeup_ports[1].bits.uop.flush_on_commit \n connect slots_12.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[12].wakeup_ports[1].bits.uop.is_unique \n connect slots_12.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[12].wakeup_ports[1].bits.uop.uses_stq \n connect slots_12.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[12].wakeup_ports[1].bits.uop.uses_ldq \n connect slots_12.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[12].wakeup_ports[1].bits.uop.mem_signed \n connect slots_12.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[12].wakeup_ports[1].bits.uop.mem_size \n connect slots_12.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[12].wakeup_ports[1].bits.uop.mem_cmd \n connect slots_12.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[12].wakeup_ports[1].bits.uop.exc_cause \n connect slots_12.io.wakeup_ports[1].bits.uop.exception, issue_slots[12].wakeup_ports[1].bits.uop.exception \n connect slots_12.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[12].wakeup_ports[1].bits.uop.stale_pdst \n connect slots_12.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[12].wakeup_ports[1].bits.uop.ppred_busy \n connect slots_12.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[12].wakeup_ports[1].bits.uop.prs3_busy \n connect slots_12.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[12].wakeup_ports[1].bits.uop.prs2_busy \n connect slots_12.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[12].wakeup_ports[1].bits.uop.prs1_busy \n connect slots_12.io.wakeup_ports[1].bits.uop.ppred, issue_slots[12].wakeup_ports[1].bits.uop.ppred \n connect slots_12.io.wakeup_ports[1].bits.uop.prs3, issue_slots[12].wakeup_ports[1].bits.uop.prs3 \n connect slots_12.io.wakeup_ports[1].bits.uop.prs2, issue_slots[12].wakeup_ports[1].bits.uop.prs2 \n connect slots_12.io.wakeup_ports[1].bits.uop.prs1, issue_slots[12].wakeup_ports[1].bits.uop.prs1 \n connect slots_12.io.wakeup_ports[1].bits.uop.pdst, issue_slots[12].wakeup_ports[1].bits.uop.pdst \n connect slots_12.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[12].wakeup_ports[1].bits.uop.rxq_idx \n connect slots_12.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[12].wakeup_ports[1].bits.uop.stq_idx \n connect slots_12.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[12].wakeup_ports[1].bits.uop.ldq_idx \n connect slots_12.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[12].wakeup_ports[1].bits.uop.rob_idx \n connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.vec \n connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.wflags \n connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.sqrt \n connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.div \n connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.fma \n connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe \n connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.toint \n connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.fromint \n connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut \n connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn \n connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.swap23 \n connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.swap12 \n connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.ren3 \n connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.ren2 \n connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.ren1 \n connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.wen \n connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.ldst \n connect slots_12.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[12].wakeup_ports[1].bits.uop.op2_sel \n connect slots_12.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[12].wakeup_ports[1].bits.uop.op1_sel \n connect slots_12.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[12].wakeup_ports[1].bits.uop.imm_packed \n connect slots_12.io.wakeup_ports[1].bits.uop.pimm, issue_slots[12].wakeup_ports[1].bits.uop.pimm \n connect slots_12.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[12].wakeup_ports[1].bits.uop.imm_sel \n connect slots_12.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[12].wakeup_ports[1].bits.uop.imm_rename \n connect slots_12.io.wakeup_ports[1].bits.uop.taken, issue_slots[12].wakeup_ports[1].bits.uop.taken \n connect slots_12.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[12].wakeup_ports[1].bits.uop.pc_lob \n connect slots_12.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[12].wakeup_ports[1].bits.uop.edge_inst \n connect slots_12.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[12].wakeup_ports[1].bits.uop.ftq_idx \n connect slots_12.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[12].wakeup_ports[1].bits.uop.is_mov \n connect slots_12.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[12].wakeup_ports[1].bits.uop.is_rocc \n connect slots_12.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[12].wakeup_ports[1].bits.uop.is_sys_pc2epc \n connect slots_12.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[12].wakeup_ports[1].bits.uop.is_eret \n connect slots_12.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[12].wakeup_ports[1].bits.uop.is_amo \n connect slots_12.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[12].wakeup_ports[1].bits.uop.is_sfence \n connect slots_12.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[12].wakeup_ports[1].bits.uop.is_fencei \n connect slots_12.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[12].wakeup_ports[1].bits.uop.is_fence \n connect slots_12.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[12].wakeup_ports[1].bits.uop.is_sfb \n connect slots_12.io.wakeup_ports[1].bits.uop.br_type, issue_slots[12].wakeup_ports[1].bits.uop.br_type \n connect slots_12.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[12].wakeup_ports[1].bits.uop.br_tag \n connect slots_12.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[12].wakeup_ports[1].bits.uop.br_mask \n connect slots_12.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[12].wakeup_ports[1].bits.uop.dis_col_sel \n connect slots_12.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[12].wakeup_ports[1].bits.uop.iw_p3_bypass_hint \n connect slots_12.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[12].wakeup_ports[1].bits.uop.iw_p2_bypass_hint \n connect slots_12.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[12].wakeup_ports[1].bits.uop.iw_p1_bypass_hint \n connect slots_12.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[12].wakeup_ports[1].bits.uop.iw_p2_speculative_child \n connect slots_12.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[12].wakeup_ports[1].bits.uop.iw_p1_speculative_child \n connect slots_12.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[12].wakeup_ports[1].bits.uop.iw_issued_partial_dgen \n connect slots_12.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[12].wakeup_ports[1].bits.uop.iw_issued_partial_agen \n connect slots_12.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[12].wakeup_ports[1].bits.uop.iw_issued \n connect slots_12.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[12].wakeup_ports[1].bits.uop.fu_code[0] \n connect slots_12.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[12].wakeup_ports[1].bits.uop.fu_code[1] \n connect slots_12.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[12].wakeup_ports[1].bits.uop.fu_code[2] \n connect slots_12.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[12].wakeup_ports[1].bits.uop.fu_code[3] \n connect slots_12.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[12].wakeup_ports[1].bits.uop.fu_code[4] \n connect slots_12.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[12].wakeup_ports[1].bits.uop.fu_code[5] \n connect slots_12.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[12].wakeup_ports[1].bits.uop.fu_code[6] \n connect slots_12.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[12].wakeup_ports[1].bits.uop.fu_code[7] \n connect slots_12.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[12].wakeup_ports[1].bits.uop.fu_code[8] \n connect slots_12.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[12].wakeup_ports[1].bits.uop.fu_code[9] \n connect slots_12.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[12].wakeup_ports[1].bits.uop.iq_type[0] \n connect slots_12.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[12].wakeup_ports[1].bits.uop.iq_type[1] \n connect slots_12.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[12].wakeup_ports[1].bits.uop.iq_type[2] \n connect slots_12.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[12].wakeup_ports[1].bits.uop.iq_type[3] \n connect slots_12.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[12].wakeup_ports[1].bits.uop.debug_pc \n connect slots_12.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[12].wakeup_ports[1].bits.uop.is_rvc \n connect slots_12.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[12].wakeup_ports[1].bits.uop.debug_inst \n connect slots_12.io.wakeup_ports[1].bits.uop.inst, issue_slots[12].wakeup_ports[1].bits.uop.inst \n connect slots_12.io.wakeup_ports[1].valid, issue_slots[12].wakeup_ports[1].valid \n connect slots_12.io.wakeup_ports[2].bits.rebusy, issue_slots[12].wakeup_ports[2].bits.rebusy \n connect slots_12.io.wakeup_ports[2].bits.speculative_mask, issue_slots[12].wakeup_ports[2].bits.speculative_mask \n connect slots_12.io.wakeup_ports[2].bits.bypassable, issue_slots[12].wakeup_ports[2].bits.bypassable \n connect slots_12.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[12].wakeup_ports[2].bits.uop.debug_tsrc \n connect slots_12.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[12].wakeup_ports[2].bits.uop.debug_fsrc \n connect slots_12.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[12].wakeup_ports[2].bits.uop.bp_xcpt_if \n connect slots_12.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[12].wakeup_ports[2].bits.uop.bp_debug_if \n connect slots_12.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[12].wakeup_ports[2].bits.uop.xcpt_ma_if \n connect slots_12.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[12].wakeup_ports[2].bits.uop.xcpt_ae_if \n connect slots_12.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[12].wakeup_ports[2].bits.uop.xcpt_pf_if \n connect slots_12.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[12].wakeup_ports[2].bits.uop.fp_typ \n connect slots_12.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[12].wakeup_ports[2].bits.uop.fp_rm \n connect slots_12.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[12].wakeup_ports[2].bits.uop.fp_val \n connect slots_12.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[12].wakeup_ports[2].bits.uop.fcn_op \n connect slots_12.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[12].wakeup_ports[2].bits.uop.fcn_dw \n connect slots_12.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[12].wakeup_ports[2].bits.uop.frs3_en \n connect slots_12.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[12].wakeup_ports[2].bits.uop.lrs2_rtype \n connect slots_12.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[12].wakeup_ports[2].bits.uop.lrs1_rtype \n connect slots_12.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[12].wakeup_ports[2].bits.uop.dst_rtype \n connect slots_12.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[12].wakeup_ports[2].bits.uop.lrs3 \n connect slots_12.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[12].wakeup_ports[2].bits.uop.lrs2 \n connect slots_12.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[12].wakeup_ports[2].bits.uop.lrs1 \n connect slots_12.io.wakeup_ports[2].bits.uop.ldst, issue_slots[12].wakeup_ports[2].bits.uop.ldst \n connect slots_12.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[12].wakeup_ports[2].bits.uop.ldst_is_rs1 \n connect slots_12.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[12].wakeup_ports[2].bits.uop.csr_cmd \n connect slots_12.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[12].wakeup_ports[2].bits.uop.flush_on_commit \n connect slots_12.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[12].wakeup_ports[2].bits.uop.is_unique \n connect slots_12.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[12].wakeup_ports[2].bits.uop.uses_stq \n connect slots_12.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[12].wakeup_ports[2].bits.uop.uses_ldq \n connect slots_12.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[12].wakeup_ports[2].bits.uop.mem_signed \n connect slots_12.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[12].wakeup_ports[2].bits.uop.mem_size \n connect slots_12.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[12].wakeup_ports[2].bits.uop.mem_cmd \n connect slots_12.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[12].wakeup_ports[2].bits.uop.exc_cause \n connect slots_12.io.wakeup_ports[2].bits.uop.exception, issue_slots[12].wakeup_ports[2].bits.uop.exception \n connect slots_12.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[12].wakeup_ports[2].bits.uop.stale_pdst \n connect slots_12.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[12].wakeup_ports[2].bits.uop.ppred_busy \n connect slots_12.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[12].wakeup_ports[2].bits.uop.prs3_busy \n connect slots_12.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[12].wakeup_ports[2].bits.uop.prs2_busy \n connect slots_12.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[12].wakeup_ports[2].bits.uop.prs1_busy \n connect slots_12.io.wakeup_ports[2].bits.uop.ppred, issue_slots[12].wakeup_ports[2].bits.uop.ppred \n connect slots_12.io.wakeup_ports[2].bits.uop.prs3, issue_slots[12].wakeup_ports[2].bits.uop.prs3 \n connect slots_12.io.wakeup_ports[2].bits.uop.prs2, issue_slots[12].wakeup_ports[2].bits.uop.prs2 \n connect slots_12.io.wakeup_ports[2].bits.uop.prs1, issue_slots[12].wakeup_ports[2].bits.uop.prs1 \n connect slots_12.io.wakeup_ports[2].bits.uop.pdst, issue_slots[12].wakeup_ports[2].bits.uop.pdst \n connect slots_12.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[12].wakeup_ports[2].bits.uop.rxq_idx \n connect slots_12.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[12].wakeup_ports[2].bits.uop.stq_idx \n connect slots_12.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[12].wakeup_ports[2].bits.uop.ldq_idx \n connect slots_12.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[12].wakeup_ports[2].bits.uop.rob_idx \n connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.vec \n connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.wflags \n connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.sqrt \n connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.div \n connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.fma \n connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe \n connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.toint \n connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.fromint \n connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut \n connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn \n connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.swap23 \n connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.swap12 \n connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.ren3 \n connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.ren2 \n connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.ren1 \n connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.wen \n connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.ldst \n connect slots_12.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[12].wakeup_ports[2].bits.uop.op2_sel \n connect slots_12.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[12].wakeup_ports[2].bits.uop.op1_sel \n connect slots_12.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[12].wakeup_ports[2].bits.uop.imm_packed \n connect slots_12.io.wakeup_ports[2].bits.uop.pimm, issue_slots[12].wakeup_ports[2].bits.uop.pimm \n connect slots_12.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[12].wakeup_ports[2].bits.uop.imm_sel \n connect slots_12.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[12].wakeup_ports[2].bits.uop.imm_rename \n connect slots_12.io.wakeup_ports[2].bits.uop.taken, issue_slots[12].wakeup_ports[2].bits.uop.taken \n connect slots_12.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[12].wakeup_ports[2].bits.uop.pc_lob \n connect slots_12.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[12].wakeup_ports[2].bits.uop.edge_inst \n connect slots_12.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[12].wakeup_ports[2].bits.uop.ftq_idx \n connect slots_12.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[12].wakeup_ports[2].bits.uop.is_mov \n connect slots_12.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[12].wakeup_ports[2].bits.uop.is_rocc \n connect slots_12.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[12].wakeup_ports[2].bits.uop.is_sys_pc2epc \n connect slots_12.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[12].wakeup_ports[2].bits.uop.is_eret \n connect slots_12.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[12].wakeup_ports[2].bits.uop.is_amo \n connect slots_12.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[12].wakeup_ports[2].bits.uop.is_sfence \n connect slots_12.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[12].wakeup_ports[2].bits.uop.is_fencei \n connect slots_12.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[12].wakeup_ports[2].bits.uop.is_fence \n connect slots_12.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[12].wakeup_ports[2].bits.uop.is_sfb \n connect slots_12.io.wakeup_ports[2].bits.uop.br_type, issue_slots[12].wakeup_ports[2].bits.uop.br_type \n connect slots_12.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[12].wakeup_ports[2].bits.uop.br_tag \n connect slots_12.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[12].wakeup_ports[2].bits.uop.br_mask \n connect slots_12.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[12].wakeup_ports[2].bits.uop.dis_col_sel \n connect slots_12.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[12].wakeup_ports[2].bits.uop.iw_p3_bypass_hint \n connect slots_12.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[12].wakeup_ports[2].bits.uop.iw_p2_bypass_hint \n connect slots_12.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[12].wakeup_ports[2].bits.uop.iw_p1_bypass_hint \n connect slots_12.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[12].wakeup_ports[2].bits.uop.iw_p2_speculative_child \n connect slots_12.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[12].wakeup_ports[2].bits.uop.iw_p1_speculative_child \n connect slots_12.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[12].wakeup_ports[2].bits.uop.iw_issued_partial_dgen \n connect slots_12.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[12].wakeup_ports[2].bits.uop.iw_issued_partial_agen \n connect slots_12.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[12].wakeup_ports[2].bits.uop.iw_issued \n connect slots_12.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[12].wakeup_ports[2].bits.uop.fu_code[0] \n connect slots_12.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[12].wakeup_ports[2].bits.uop.fu_code[1] \n connect slots_12.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[12].wakeup_ports[2].bits.uop.fu_code[2] \n connect slots_12.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[12].wakeup_ports[2].bits.uop.fu_code[3] \n connect slots_12.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[12].wakeup_ports[2].bits.uop.fu_code[4] \n connect slots_12.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[12].wakeup_ports[2].bits.uop.fu_code[5] \n connect slots_12.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[12].wakeup_ports[2].bits.uop.fu_code[6] \n connect slots_12.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[12].wakeup_ports[2].bits.uop.fu_code[7] \n connect slots_12.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[12].wakeup_ports[2].bits.uop.fu_code[8] \n connect slots_12.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[12].wakeup_ports[2].bits.uop.fu_code[9] \n connect slots_12.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[12].wakeup_ports[2].bits.uop.iq_type[0] \n connect slots_12.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[12].wakeup_ports[2].bits.uop.iq_type[1] \n connect slots_12.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[12].wakeup_ports[2].bits.uop.iq_type[2] \n connect slots_12.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[12].wakeup_ports[2].bits.uop.iq_type[3] \n connect slots_12.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[12].wakeup_ports[2].bits.uop.debug_pc \n connect slots_12.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[12].wakeup_ports[2].bits.uop.is_rvc \n connect slots_12.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[12].wakeup_ports[2].bits.uop.debug_inst \n connect slots_12.io.wakeup_ports[2].bits.uop.inst, issue_slots[12].wakeup_ports[2].bits.uop.inst \n connect slots_12.io.wakeup_ports[2].valid, issue_slots[12].wakeup_ports[2].valid \n connect slots_12.io.wakeup_ports[3].bits.rebusy, issue_slots[12].wakeup_ports[3].bits.rebusy \n connect slots_12.io.wakeup_ports[3].bits.speculative_mask, issue_slots[12].wakeup_ports[3].bits.speculative_mask \n connect slots_12.io.wakeup_ports[3].bits.bypassable, issue_slots[12].wakeup_ports[3].bits.bypassable \n connect slots_12.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[12].wakeup_ports[3].bits.uop.debug_tsrc \n connect slots_12.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[12].wakeup_ports[3].bits.uop.debug_fsrc \n connect slots_12.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[12].wakeup_ports[3].bits.uop.bp_xcpt_if \n connect slots_12.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[12].wakeup_ports[3].bits.uop.bp_debug_if \n connect slots_12.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[12].wakeup_ports[3].bits.uop.xcpt_ma_if \n connect slots_12.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[12].wakeup_ports[3].bits.uop.xcpt_ae_if \n connect slots_12.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[12].wakeup_ports[3].bits.uop.xcpt_pf_if \n connect slots_12.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[12].wakeup_ports[3].bits.uop.fp_typ \n connect slots_12.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[12].wakeup_ports[3].bits.uop.fp_rm \n connect slots_12.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[12].wakeup_ports[3].bits.uop.fp_val \n connect slots_12.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[12].wakeup_ports[3].bits.uop.fcn_op \n connect slots_12.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[12].wakeup_ports[3].bits.uop.fcn_dw \n connect slots_12.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[12].wakeup_ports[3].bits.uop.frs3_en \n connect slots_12.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[12].wakeup_ports[3].bits.uop.lrs2_rtype \n connect slots_12.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[12].wakeup_ports[3].bits.uop.lrs1_rtype \n connect slots_12.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[12].wakeup_ports[3].bits.uop.dst_rtype \n connect slots_12.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[12].wakeup_ports[3].bits.uop.lrs3 \n connect slots_12.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[12].wakeup_ports[3].bits.uop.lrs2 \n connect slots_12.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[12].wakeup_ports[3].bits.uop.lrs1 \n connect slots_12.io.wakeup_ports[3].bits.uop.ldst, issue_slots[12].wakeup_ports[3].bits.uop.ldst \n connect slots_12.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[12].wakeup_ports[3].bits.uop.ldst_is_rs1 \n connect slots_12.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[12].wakeup_ports[3].bits.uop.csr_cmd \n connect slots_12.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[12].wakeup_ports[3].bits.uop.flush_on_commit \n connect slots_12.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[12].wakeup_ports[3].bits.uop.is_unique \n connect slots_12.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[12].wakeup_ports[3].bits.uop.uses_stq \n connect slots_12.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[12].wakeup_ports[3].bits.uop.uses_ldq \n connect slots_12.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[12].wakeup_ports[3].bits.uop.mem_signed \n connect slots_12.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[12].wakeup_ports[3].bits.uop.mem_size \n connect slots_12.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[12].wakeup_ports[3].bits.uop.mem_cmd \n connect slots_12.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[12].wakeup_ports[3].bits.uop.exc_cause \n connect slots_12.io.wakeup_ports[3].bits.uop.exception, issue_slots[12].wakeup_ports[3].bits.uop.exception \n connect slots_12.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[12].wakeup_ports[3].bits.uop.stale_pdst \n connect slots_12.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[12].wakeup_ports[3].bits.uop.ppred_busy \n connect slots_12.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[12].wakeup_ports[3].bits.uop.prs3_busy \n connect slots_12.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[12].wakeup_ports[3].bits.uop.prs2_busy \n connect slots_12.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[12].wakeup_ports[3].bits.uop.prs1_busy \n connect slots_12.io.wakeup_ports[3].bits.uop.ppred, issue_slots[12].wakeup_ports[3].bits.uop.ppred \n connect slots_12.io.wakeup_ports[3].bits.uop.prs3, issue_slots[12].wakeup_ports[3].bits.uop.prs3 \n connect slots_12.io.wakeup_ports[3].bits.uop.prs2, issue_slots[12].wakeup_ports[3].bits.uop.prs2 \n connect slots_12.io.wakeup_ports[3].bits.uop.prs1, issue_slots[12].wakeup_ports[3].bits.uop.prs1 \n connect slots_12.io.wakeup_ports[3].bits.uop.pdst, issue_slots[12].wakeup_ports[3].bits.uop.pdst \n connect slots_12.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[12].wakeup_ports[3].bits.uop.rxq_idx \n connect slots_12.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[12].wakeup_ports[3].bits.uop.stq_idx \n connect slots_12.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[12].wakeup_ports[3].bits.uop.ldq_idx \n connect slots_12.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[12].wakeup_ports[3].bits.uop.rob_idx \n connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.vec \n connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.wflags \n connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.sqrt \n connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.div \n connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.fma \n connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe \n connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.toint \n connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.fromint \n connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut \n connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn \n connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.swap23 \n connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.swap12 \n connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.ren3 \n connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.ren2 \n connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.ren1 \n connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.wen \n connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.ldst \n connect slots_12.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[12].wakeup_ports[3].bits.uop.op2_sel \n connect slots_12.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[12].wakeup_ports[3].bits.uop.op1_sel \n connect slots_12.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[12].wakeup_ports[3].bits.uop.imm_packed \n connect slots_12.io.wakeup_ports[3].bits.uop.pimm, issue_slots[12].wakeup_ports[3].bits.uop.pimm \n connect slots_12.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[12].wakeup_ports[3].bits.uop.imm_sel \n connect slots_12.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[12].wakeup_ports[3].bits.uop.imm_rename \n connect slots_12.io.wakeup_ports[3].bits.uop.taken, issue_slots[12].wakeup_ports[3].bits.uop.taken \n connect slots_12.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[12].wakeup_ports[3].bits.uop.pc_lob \n connect slots_12.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[12].wakeup_ports[3].bits.uop.edge_inst \n connect slots_12.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[12].wakeup_ports[3].bits.uop.ftq_idx \n connect slots_12.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[12].wakeup_ports[3].bits.uop.is_mov \n connect slots_12.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[12].wakeup_ports[3].bits.uop.is_rocc \n connect slots_12.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[12].wakeup_ports[3].bits.uop.is_sys_pc2epc \n connect slots_12.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[12].wakeup_ports[3].bits.uop.is_eret \n connect slots_12.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[12].wakeup_ports[3].bits.uop.is_amo \n connect slots_12.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[12].wakeup_ports[3].bits.uop.is_sfence \n connect slots_12.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[12].wakeup_ports[3].bits.uop.is_fencei \n connect slots_12.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[12].wakeup_ports[3].bits.uop.is_fence \n connect slots_12.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[12].wakeup_ports[3].bits.uop.is_sfb \n connect slots_12.io.wakeup_ports[3].bits.uop.br_type, issue_slots[12].wakeup_ports[3].bits.uop.br_type \n connect slots_12.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[12].wakeup_ports[3].bits.uop.br_tag \n connect slots_12.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[12].wakeup_ports[3].bits.uop.br_mask \n connect slots_12.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[12].wakeup_ports[3].bits.uop.dis_col_sel \n connect slots_12.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[12].wakeup_ports[3].bits.uop.iw_p3_bypass_hint \n connect slots_12.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[12].wakeup_ports[3].bits.uop.iw_p2_bypass_hint \n connect slots_12.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[12].wakeup_ports[3].bits.uop.iw_p1_bypass_hint \n connect slots_12.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[12].wakeup_ports[3].bits.uop.iw_p2_speculative_child \n connect slots_12.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[12].wakeup_ports[3].bits.uop.iw_p1_speculative_child \n connect slots_12.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[12].wakeup_ports[3].bits.uop.iw_issued_partial_dgen \n connect slots_12.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[12].wakeup_ports[3].bits.uop.iw_issued_partial_agen \n connect slots_12.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[12].wakeup_ports[3].bits.uop.iw_issued \n connect slots_12.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[12].wakeup_ports[3].bits.uop.fu_code[0] \n connect slots_12.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[12].wakeup_ports[3].bits.uop.fu_code[1] \n connect slots_12.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[12].wakeup_ports[3].bits.uop.fu_code[2] \n connect slots_12.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[12].wakeup_ports[3].bits.uop.fu_code[3] \n connect slots_12.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[12].wakeup_ports[3].bits.uop.fu_code[4] \n connect slots_12.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[12].wakeup_ports[3].bits.uop.fu_code[5] \n connect slots_12.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[12].wakeup_ports[3].bits.uop.fu_code[6] \n connect slots_12.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[12].wakeup_ports[3].bits.uop.fu_code[7] \n connect slots_12.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[12].wakeup_ports[3].bits.uop.fu_code[8] \n connect slots_12.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[12].wakeup_ports[3].bits.uop.fu_code[9] \n connect slots_12.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[12].wakeup_ports[3].bits.uop.iq_type[0] \n connect slots_12.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[12].wakeup_ports[3].bits.uop.iq_type[1] \n connect slots_12.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[12].wakeup_ports[3].bits.uop.iq_type[2] \n connect slots_12.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[12].wakeup_ports[3].bits.uop.iq_type[3] \n connect slots_12.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[12].wakeup_ports[3].bits.uop.debug_pc \n connect slots_12.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[12].wakeup_ports[3].bits.uop.is_rvc \n connect slots_12.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[12].wakeup_ports[3].bits.uop.debug_inst \n connect slots_12.io.wakeup_ports[3].bits.uop.inst, issue_slots[12].wakeup_ports[3].bits.uop.inst \n connect slots_12.io.wakeup_ports[3].valid, issue_slots[12].wakeup_ports[3].valid \n connect slots_12.io.squash_grant, issue_slots[12].squash_grant \n connect slots_12.io.clear, issue_slots[12].clear \n connect slots_12.io.kill, issue_slots[12].kill \n connect slots_12.io.brupdate.b2.target_offset, issue_slots[12].brupdate.b2.target_offset \n connect slots_12.io.brupdate.b2.jalr_target, issue_slots[12].brupdate.b2.jalr_target \n connect slots_12.io.brupdate.b2.pc_sel, issue_slots[12].brupdate.b2.pc_sel \n connect slots_12.io.brupdate.b2.cfi_type, issue_slots[12].brupdate.b2.cfi_type \n connect slots_12.io.brupdate.b2.taken, issue_slots[12].brupdate.b2.taken \n connect slots_12.io.brupdate.b2.mispredict, issue_slots[12].brupdate.b2.mispredict \n connect slots_12.io.brupdate.b2.uop.debug_tsrc, issue_slots[12].brupdate.b2.uop.debug_tsrc \n connect slots_12.io.brupdate.b2.uop.debug_fsrc, issue_slots[12].brupdate.b2.uop.debug_fsrc \n connect slots_12.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[12].brupdate.b2.uop.bp_xcpt_if \n connect slots_12.io.brupdate.b2.uop.bp_debug_if, issue_slots[12].brupdate.b2.uop.bp_debug_if \n connect slots_12.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[12].brupdate.b2.uop.xcpt_ma_if \n connect slots_12.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[12].brupdate.b2.uop.xcpt_ae_if \n connect slots_12.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[12].brupdate.b2.uop.xcpt_pf_if \n connect slots_12.io.brupdate.b2.uop.fp_typ, issue_slots[12].brupdate.b2.uop.fp_typ \n connect slots_12.io.brupdate.b2.uop.fp_rm, issue_slots[12].brupdate.b2.uop.fp_rm \n connect slots_12.io.brupdate.b2.uop.fp_val, issue_slots[12].brupdate.b2.uop.fp_val \n connect slots_12.io.brupdate.b2.uop.fcn_op, issue_slots[12].brupdate.b2.uop.fcn_op \n connect slots_12.io.brupdate.b2.uop.fcn_dw, issue_slots[12].brupdate.b2.uop.fcn_dw \n connect slots_12.io.brupdate.b2.uop.frs3_en, issue_slots[12].brupdate.b2.uop.frs3_en \n connect slots_12.io.brupdate.b2.uop.lrs2_rtype, issue_slots[12].brupdate.b2.uop.lrs2_rtype \n connect slots_12.io.brupdate.b2.uop.lrs1_rtype, issue_slots[12].brupdate.b2.uop.lrs1_rtype \n connect slots_12.io.brupdate.b2.uop.dst_rtype, issue_slots[12].brupdate.b2.uop.dst_rtype \n connect slots_12.io.brupdate.b2.uop.lrs3, issue_slots[12].brupdate.b2.uop.lrs3 \n connect slots_12.io.brupdate.b2.uop.lrs2, issue_slots[12].brupdate.b2.uop.lrs2 \n connect slots_12.io.brupdate.b2.uop.lrs1, issue_slots[12].brupdate.b2.uop.lrs1 \n connect slots_12.io.brupdate.b2.uop.ldst, issue_slots[12].brupdate.b2.uop.ldst \n connect slots_12.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[12].brupdate.b2.uop.ldst_is_rs1 \n connect slots_12.io.brupdate.b2.uop.csr_cmd, issue_slots[12].brupdate.b2.uop.csr_cmd \n connect slots_12.io.brupdate.b2.uop.flush_on_commit, issue_slots[12].brupdate.b2.uop.flush_on_commit \n connect slots_12.io.brupdate.b2.uop.is_unique, issue_slots[12].brupdate.b2.uop.is_unique \n connect slots_12.io.brupdate.b2.uop.uses_stq, issue_slots[12].brupdate.b2.uop.uses_stq \n connect slots_12.io.brupdate.b2.uop.uses_ldq, issue_slots[12].brupdate.b2.uop.uses_ldq \n connect slots_12.io.brupdate.b2.uop.mem_signed, issue_slots[12].brupdate.b2.uop.mem_signed \n connect slots_12.io.brupdate.b2.uop.mem_size, issue_slots[12].brupdate.b2.uop.mem_size \n connect slots_12.io.brupdate.b2.uop.mem_cmd, issue_slots[12].brupdate.b2.uop.mem_cmd \n connect slots_12.io.brupdate.b2.uop.exc_cause, issue_slots[12].brupdate.b2.uop.exc_cause \n connect slots_12.io.brupdate.b2.uop.exception, issue_slots[12].brupdate.b2.uop.exception \n connect slots_12.io.brupdate.b2.uop.stale_pdst, issue_slots[12].brupdate.b2.uop.stale_pdst \n connect slots_12.io.brupdate.b2.uop.ppred_busy, issue_slots[12].brupdate.b2.uop.ppred_busy \n connect slots_12.io.brupdate.b2.uop.prs3_busy, issue_slots[12].brupdate.b2.uop.prs3_busy \n connect slots_12.io.brupdate.b2.uop.prs2_busy, issue_slots[12].brupdate.b2.uop.prs2_busy \n connect slots_12.io.brupdate.b2.uop.prs1_busy, issue_slots[12].brupdate.b2.uop.prs1_busy \n connect slots_12.io.brupdate.b2.uop.ppred, issue_slots[12].brupdate.b2.uop.ppred \n connect slots_12.io.brupdate.b2.uop.prs3, issue_slots[12].brupdate.b2.uop.prs3 \n connect slots_12.io.brupdate.b2.uop.prs2, issue_slots[12].brupdate.b2.uop.prs2 \n connect slots_12.io.brupdate.b2.uop.prs1, issue_slots[12].brupdate.b2.uop.prs1 \n connect slots_12.io.brupdate.b2.uop.pdst, issue_slots[12].brupdate.b2.uop.pdst \n connect slots_12.io.brupdate.b2.uop.rxq_idx, issue_slots[12].brupdate.b2.uop.rxq_idx \n connect slots_12.io.brupdate.b2.uop.stq_idx, issue_slots[12].brupdate.b2.uop.stq_idx \n connect slots_12.io.brupdate.b2.uop.ldq_idx, issue_slots[12].brupdate.b2.uop.ldq_idx \n connect slots_12.io.brupdate.b2.uop.rob_idx, issue_slots[12].brupdate.b2.uop.rob_idx \n connect slots_12.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[12].brupdate.b2.uop.fp_ctrl.vec \n connect slots_12.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[12].brupdate.b2.uop.fp_ctrl.wflags \n connect slots_12.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[12].brupdate.b2.uop.fp_ctrl.sqrt \n connect slots_12.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[12].brupdate.b2.uop.fp_ctrl.div \n connect slots_12.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[12].brupdate.b2.uop.fp_ctrl.fma \n connect slots_12.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[12].brupdate.b2.uop.fp_ctrl.fastpipe \n connect slots_12.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[12].brupdate.b2.uop.fp_ctrl.toint \n connect slots_12.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[12].brupdate.b2.uop.fp_ctrl.fromint \n connect slots_12.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[12].brupdate.b2.uop.fp_ctrl.typeTagOut \n connect slots_12.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[12].brupdate.b2.uop.fp_ctrl.typeTagIn \n connect slots_12.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[12].brupdate.b2.uop.fp_ctrl.swap23 \n connect slots_12.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[12].brupdate.b2.uop.fp_ctrl.swap12 \n connect slots_12.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[12].brupdate.b2.uop.fp_ctrl.ren3 \n connect slots_12.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[12].brupdate.b2.uop.fp_ctrl.ren2 \n connect slots_12.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[12].brupdate.b2.uop.fp_ctrl.ren1 \n connect slots_12.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[12].brupdate.b2.uop.fp_ctrl.wen \n connect slots_12.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[12].brupdate.b2.uop.fp_ctrl.ldst \n connect slots_12.io.brupdate.b2.uop.op2_sel, issue_slots[12].brupdate.b2.uop.op2_sel \n connect slots_12.io.brupdate.b2.uop.op1_sel, issue_slots[12].brupdate.b2.uop.op1_sel \n connect slots_12.io.brupdate.b2.uop.imm_packed, issue_slots[12].brupdate.b2.uop.imm_packed \n connect slots_12.io.brupdate.b2.uop.pimm, issue_slots[12].brupdate.b2.uop.pimm \n connect slots_12.io.brupdate.b2.uop.imm_sel, issue_slots[12].brupdate.b2.uop.imm_sel \n connect slots_12.io.brupdate.b2.uop.imm_rename, issue_slots[12].brupdate.b2.uop.imm_rename \n connect slots_12.io.brupdate.b2.uop.taken, issue_slots[12].brupdate.b2.uop.taken \n connect slots_12.io.brupdate.b2.uop.pc_lob, issue_slots[12].brupdate.b2.uop.pc_lob \n connect slots_12.io.brupdate.b2.uop.edge_inst, issue_slots[12].brupdate.b2.uop.edge_inst \n connect slots_12.io.brupdate.b2.uop.ftq_idx, issue_slots[12].brupdate.b2.uop.ftq_idx \n connect slots_12.io.brupdate.b2.uop.is_mov, issue_slots[12].brupdate.b2.uop.is_mov \n connect slots_12.io.brupdate.b2.uop.is_rocc, issue_slots[12].brupdate.b2.uop.is_rocc \n connect slots_12.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[12].brupdate.b2.uop.is_sys_pc2epc \n connect slots_12.io.brupdate.b2.uop.is_eret, issue_slots[12].brupdate.b2.uop.is_eret \n connect slots_12.io.brupdate.b2.uop.is_amo, issue_slots[12].brupdate.b2.uop.is_amo \n connect slots_12.io.brupdate.b2.uop.is_sfence, issue_slots[12].brupdate.b2.uop.is_sfence \n connect slots_12.io.brupdate.b2.uop.is_fencei, issue_slots[12].brupdate.b2.uop.is_fencei \n connect slots_12.io.brupdate.b2.uop.is_fence, issue_slots[12].brupdate.b2.uop.is_fence \n connect slots_12.io.brupdate.b2.uop.is_sfb, issue_slots[12].brupdate.b2.uop.is_sfb \n connect slots_12.io.brupdate.b2.uop.br_type, issue_slots[12].brupdate.b2.uop.br_type \n connect slots_12.io.brupdate.b2.uop.br_tag, issue_slots[12].brupdate.b2.uop.br_tag \n connect slots_12.io.brupdate.b2.uop.br_mask, issue_slots[12].brupdate.b2.uop.br_mask \n connect slots_12.io.brupdate.b2.uop.dis_col_sel, issue_slots[12].brupdate.b2.uop.dis_col_sel \n connect slots_12.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[12].brupdate.b2.uop.iw_p3_bypass_hint \n connect slots_12.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[12].brupdate.b2.uop.iw_p2_bypass_hint \n connect slots_12.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[12].brupdate.b2.uop.iw_p1_bypass_hint \n connect slots_12.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[12].brupdate.b2.uop.iw_p2_speculative_child \n connect slots_12.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[12].brupdate.b2.uop.iw_p1_speculative_child \n connect slots_12.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[12].brupdate.b2.uop.iw_issued_partial_dgen \n connect slots_12.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[12].brupdate.b2.uop.iw_issued_partial_agen \n connect slots_12.io.brupdate.b2.uop.iw_issued, issue_slots[12].brupdate.b2.uop.iw_issued \n connect slots_12.io.brupdate.b2.uop.fu_code[0], issue_slots[12].brupdate.b2.uop.fu_code[0] \n connect slots_12.io.brupdate.b2.uop.fu_code[1], issue_slots[12].brupdate.b2.uop.fu_code[1] \n connect slots_12.io.brupdate.b2.uop.fu_code[2], issue_slots[12].brupdate.b2.uop.fu_code[2] \n connect slots_12.io.brupdate.b2.uop.fu_code[3], issue_slots[12].brupdate.b2.uop.fu_code[3] \n connect slots_12.io.brupdate.b2.uop.fu_code[4], issue_slots[12].brupdate.b2.uop.fu_code[4] \n connect slots_12.io.brupdate.b2.uop.fu_code[5], issue_slots[12].brupdate.b2.uop.fu_code[5] \n connect slots_12.io.brupdate.b2.uop.fu_code[6], issue_slots[12].brupdate.b2.uop.fu_code[6] \n connect slots_12.io.brupdate.b2.uop.fu_code[7], issue_slots[12].brupdate.b2.uop.fu_code[7] \n connect slots_12.io.brupdate.b2.uop.fu_code[8], issue_slots[12].brupdate.b2.uop.fu_code[8] \n connect slots_12.io.brupdate.b2.uop.fu_code[9], issue_slots[12].brupdate.b2.uop.fu_code[9] \n connect slots_12.io.brupdate.b2.uop.iq_type[0], issue_slots[12].brupdate.b2.uop.iq_type[0] \n connect slots_12.io.brupdate.b2.uop.iq_type[1], issue_slots[12].brupdate.b2.uop.iq_type[1] \n connect slots_12.io.brupdate.b2.uop.iq_type[2], issue_slots[12].brupdate.b2.uop.iq_type[2] \n connect slots_12.io.brupdate.b2.uop.iq_type[3], issue_slots[12].brupdate.b2.uop.iq_type[3] \n connect slots_12.io.brupdate.b2.uop.debug_pc, issue_slots[12].brupdate.b2.uop.debug_pc \n connect slots_12.io.brupdate.b2.uop.is_rvc, issue_slots[12].brupdate.b2.uop.is_rvc \n connect slots_12.io.brupdate.b2.uop.debug_inst, issue_slots[12].brupdate.b2.uop.debug_inst \n connect slots_12.io.brupdate.b2.uop.inst, issue_slots[12].brupdate.b2.uop.inst \n connect slots_12.io.brupdate.b1.mispredict_mask, issue_slots[12].brupdate.b1.mispredict_mask \n connect slots_12.io.brupdate.b1.resolve_mask, issue_slots[12].brupdate.b1.resolve_mask \n connect issue_slots[12].out_uop.debug_tsrc, slots_12.io.out_uop.debug_tsrc \n connect issue_slots[12].out_uop.debug_fsrc, slots_12.io.out_uop.debug_fsrc \n connect issue_slots[12].out_uop.bp_xcpt_if, slots_12.io.out_uop.bp_xcpt_if \n connect issue_slots[12].out_uop.bp_debug_if, slots_12.io.out_uop.bp_debug_if \n connect issue_slots[12].out_uop.xcpt_ma_if, slots_12.io.out_uop.xcpt_ma_if \n connect issue_slots[12].out_uop.xcpt_ae_if, slots_12.io.out_uop.xcpt_ae_if \n connect issue_slots[12].out_uop.xcpt_pf_if, slots_12.io.out_uop.xcpt_pf_if \n connect issue_slots[12].out_uop.fp_typ, slots_12.io.out_uop.fp_typ \n connect issue_slots[12].out_uop.fp_rm, slots_12.io.out_uop.fp_rm \n connect issue_slots[12].out_uop.fp_val, slots_12.io.out_uop.fp_val \n connect issue_slots[12].out_uop.fcn_op, slots_12.io.out_uop.fcn_op \n connect issue_slots[12].out_uop.fcn_dw, slots_12.io.out_uop.fcn_dw \n connect issue_slots[12].out_uop.frs3_en, slots_12.io.out_uop.frs3_en \n connect issue_slots[12].out_uop.lrs2_rtype, slots_12.io.out_uop.lrs2_rtype \n connect issue_slots[12].out_uop.lrs1_rtype, slots_12.io.out_uop.lrs1_rtype \n connect issue_slots[12].out_uop.dst_rtype, slots_12.io.out_uop.dst_rtype \n connect issue_slots[12].out_uop.lrs3, slots_12.io.out_uop.lrs3 \n connect issue_slots[12].out_uop.lrs2, slots_12.io.out_uop.lrs2 \n connect issue_slots[12].out_uop.lrs1, slots_12.io.out_uop.lrs1 \n connect issue_slots[12].out_uop.ldst, slots_12.io.out_uop.ldst \n connect issue_slots[12].out_uop.ldst_is_rs1, slots_12.io.out_uop.ldst_is_rs1 \n connect issue_slots[12].out_uop.csr_cmd, slots_12.io.out_uop.csr_cmd \n connect issue_slots[12].out_uop.flush_on_commit, slots_12.io.out_uop.flush_on_commit \n connect issue_slots[12].out_uop.is_unique, slots_12.io.out_uop.is_unique \n connect issue_slots[12].out_uop.uses_stq, slots_12.io.out_uop.uses_stq \n connect issue_slots[12].out_uop.uses_ldq, slots_12.io.out_uop.uses_ldq \n connect issue_slots[12].out_uop.mem_signed, slots_12.io.out_uop.mem_signed \n connect issue_slots[12].out_uop.mem_size, slots_12.io.out_uop.mem_size \n connect issue_slots[12].out_uop.mem_cmd, slots_12.io.out_uop.mem_cmd \n connect issue_slots[12].out_uop.exc_cause, slots_12.io.out_uop.exc_cause \n connect issue_slots[12].out_uop.exception, slots_12.io.out_uop.exception \n connect issue_slots[12].out_uop.stale_pdst, slots_12.io.out_uop.stale_pdst \n connect issue_slots[12].out_uop.ppred_busy, slots_12.io.out_uop.ppred_busy \n connect issue_slots[12].out_uop.prs3_busy, slots_12.io.out_uop.prs3_busy \n connect issue_slots[12].out_uop.prs2_busy, slots_12.io.out_uop.prs2_busy \n connect issue_slots[12].out_uop.prs1_busy, slots_12.io.out_uop.prs1_busy \n connect issue_slots[12].out_uop.ppred, slots_12.io.out_uop.ppred \n connect issue_slots[12].out_uop.prs3, slots_12.io.out_uop.prs3 \n connect issue_slots[12].out_uop.prs2, slots_12.io.out_uop.prs2 \n connect issue_slots[12].out_uop.prs1, slots_12.io.out_uop.prs1 \n connect issue_slots[12].out_uop.pdst, slots_12.io.out_uop.pdst \n connect issue_slots[12].out_uop.rxq_idx, slots_12.io.out_uop.rxq_idx \n connect issue_slots[12].out_uop.stq_idx, slots_12.io.out_uop.stq_idx \n connect issue_slots[12].out_uop.ldq_idx, slots_12.io.out_uop.ldq_idx \n connect issue_slots[12].out_uop.rob_idx, slots_12.io.out_uop.rob_idx \n connect issue_slots[12].out_uop.fp_ctrl.vec, slots_12.io.out_uop.fp_ctrl.vec \n connect issue_slots[12].out_uop.fp_ctrl.wflags, slots_12.io.out_uop.fp_ctrl.wflags \n connect issue_slots[12].out_uop.fp_ctrl.sqrt, slots_12.io.out_uop.fp_ctrl.sqrt \n connect issue_slots[12].out_uop.fp_ctrl.div, slots_12.io.out_uop.fp_ctrl.div \n connect issue_slots[12].out_uop.fp_ctrl.fma, slots_12.io.out_uop.fp_ctrl.fma \n connect issue_slots[12].out_uop.fp_ctrl.fastpipe, slots_12.io.out_uop.fp_ctrl.fastpipe \n connect issue_slots[12].out_uop.fp_ctrl.toint, slots_12.io.out_uop.fp_ctrl.toint \n connect issue_slots[12].out_uop.fp_ctrl.fromint, slots_12.io.out_uop.fp_ctrl.fromint \n connect issue_slots[12].out_uop.fp_ctrl.typeTagOut, slots_12.io.out_uop.fp_ctrl.typeTagOut \n connect issue_slots[12].out_uop.fp_ctrl.typeTagIn, slots_12.io.out_uop.fp_ctrl.typeTagIn \n connect issue_slots[12].out_uop.fp_ctrl.swap23, slots_12.io.out_uop.fp_ctrl.swap23 \n connect issue_slots[12].out_uop.fp_ctrl.swap12, slots_12.io.out_uop.fp_ctrl.swap12 \n connect issue_slots[12].out_uop.fp_ctrl.ren3, slots_12.io.out_uop.fp_ctrl.ren3 \n connect issue_slots[12].out_uop.fp_ctrl.ren2, slots_12.io.out_uop.fp_ctrl.ren2 \n connect issue_slots[12].out_uop.fp_ctrl.ren1, slots_12.io.out_uop.fp_ctrl.ren1 \n connect issue_slots[12].out_uop.fp_ctrl.wen, slots_12.io.out_uop.fp_ctrl.wen \n connect issue_slots[12].out_uop.fp_ctrl.ldst, slots_12.io.out_uop.fp_ctrl.ldst \n connect issue_slots[12].out_uop.op2_sel, slots_12.io.out_uop.op2_sel \n connect issue_slots[12].out_uop.op1_sel, slots_12.io.out_uop.op1_sel \n connect issue_slots[12].out_uop.imm_packed, slots_12.io.out_uop.imm_packed \n connect issue_slots[12].out_uop.pimm, slots_12.io.out_uop.pimm \n connect issue_slots[12].out_uop.imm_sel, slots_12.io.out_uop.imm_sel \n connect issue_slots[12].out_uop.imm_rename, slots_12.io.out_uop.imm_rename \n connect issue_slots[12].out_uop.taken, slots_12.io.out_uop.taken \n connect issue_slots[12].out_uop.pc_lob, slots_12.io.out_uop.pc_lob \n connect issue_slots[12].out_uop.edge_inst, slots_12.io.out_uop.edge_inst \n connect issue_slots[12].out_uop.ftq_idx, slots_12.io.out_uop.ftq_idx \n connect issue_slots[12].out_uop.is_mov, slots_12.io.out_uop.is_mov \n connect issue_slots[12].out_uop.is_rocc, slots_12.io.out_uop.is_rocc \n connect issue_slots[12].out_uop.is_sys_pc2epc, slots_12.io.out_uop.is_sys_pc2epc \n connect issue_slots[12].out_uop.is_eret, slots_12.io.out_uop.is_eret \n connect issue_slots[12].out_uop.is_amo, slots_12.io.out_uop.is_amo \n connect issue_slots[12].out_uop.is_sfence, slots_12.io.out_uop.is_sfence \n connect issue_slots[12].out_uop.is_fencei, slots_12.io.out_uop.is_fencei \n connect issue_slots[12].out_uop.is_fence, slots_12.io.out_uop.is_fence \n connect issue_slots[12].out_uop.is_sfb, slots_12.io.out_uop.is_sfb \n connect issue_slots[12].out_uop.br_type, slots_12.io.out_uop.br_type \n connect issue_slots[12].out_uop.br_tag, slots_12.io.out_uop.br_tag \n connect issue_slots[12].out_uop.br_mask, slots_12.io.out_uop.br_mask \n connect issue_slots[12].out_uop.dis_col_sel, slots_12.io.out_uop.dis_col_sel \n connect issue_slots[12].out_uop.iw_p3_bypass_hint, slots_12.io.out_uop.iw_p3_bypass_hint \n connect issue_slots[12].out_uop.iw_p2_bypass_hint, slots_12.io.out_uop.iw_p2_bypass_hint \n connect issue_slots[12].out_uop.iw_p1_bypass_hint, slots_12.io.out_uop.iw_p1_bypass_hint \n connect issue_slots[12].out_uop.iw_p2_speculative_child, slots_12.io.out_uop.iw_p2_speculative_child \n connect issue_slots[12].out_uop.iw_p1_speculative_child, slots_12.io.out_uop.iw_p1_speculative_child \n connect issue_slots[12].out_uop.iw_issued_partial_dgen, slots_12.io.out_uop.iw_issued_partial_dgen \n connect issue_slots[12].out_uop.iw_issued_partial_agen, slots_12.io.out_uop.iw_issued_partial_agen \n connect issue_slots[12].out_uop.iw_issued, slots_12.io.out_uop.iw_issued \n connect issue_slots[12].out_uop.fu_code[0], slots_12.io.out_uop.fu_code[0] \n connect issue_slots[12].out_uop.fu_code[1], slots_12.io.out_uop.fu_code[1] \n connect issue_slots[12].out_uop.fu_code[2], slots_12.io.out_uop.fu_code[2] \n connect issue_slots[12].out_uop.fu_code[3], slots_12.io.out_uop.fu_code[3] \n connect issue_slots[12].out_uop.fu_code[4], slots_12.io.out_uop.fu_code[4] \n connect issue_slots[12].out_uop.fu_code[5], slots_12.io.out_uop.fu_code[5] \n connect issue_slots[12].out_uop.fu_code[6], slots_12.io.out_uop.fu_code[6] \n connect issue_slots[12].out_uop.fu_code[7], slots_12.io.out_uop.fu_code[7] \n connect issue_slots[12].out_uop.fu_code[8], slots_12.io.out_uop.fu_code[8] \n connect issue_slots[12].out_uop.fu_code[9], slots_12.io.out_uop.fu_code[9] \n connect issue_slots[12].out_uop.iq_type[0], slots_12.io.out_uop.iq_type[0] \n connect issue_slots[12].out_uop.iq_type[1], slots_12.io.out_uop.iq_type[1] \n connect issue_slots[12].out_uop.iq_type[2], slots_12.io.out_uop.iq_type[2] \n connect issue_slots[12].out_uop.iq_type[3], slots_12.io.out_uop.iq_type[3] \n connect issue_slots[12].out_uop.debug_pc, slots_12.io.out_uop.debug_pc \n connect issue_slots[12].out_uop.is_rvc, slots_12.io.out_uop.is_rvc \n connect issue_slots[12].out_uop.debug_inst, slots_12.io.out_uop.debug_inst \n connect issue_slots[12].out_uop.inst, slots_12.io.out_uop.inst \n connect slots_12.io.in_uop.bits.debug_tsrc, issue_slots[12].in_uop.bits.debug_tsrc \n connect slots_12.io.in_uop.bits.debug_fsrc, issue_slots[12].in_uop.bits.debug_fsrc \n connect slots_12.io.in_uop.bits.bp_xcpt_if, issue_slots[12].in_uop.bits.bp_xcpt_if \n connect slots_12.io.in_uop.bits.bp_debug_if, issue_slots[12].in_uop.bits.bp_debug_if \n connect slots_12.io.in_uop.bits.xcpt_ma_if, issue_slots[12].in_uop.bits.xcpt_ma_if \n connect slots_12.io.in_uop.bits.xcpt_ae_if, issue_slots[12].in_uop.bits.xcpt_ae_if \n connect slots_12.io.in_uop.bits.xcpt_pf_if, issue_slots[12].in_uop.bits.xcpt_pf_if \n connect slots_12.io.in_uop.bits.fp_typ, issue_slots[12].in_uop.bits.fp_typ \n connect slots_12.io.in_uop.bits.fp_rm, issue_slots[12].in_uop.bits.fp_rm \n connect slots_12.io.in_uop.bits.fp_val, issue_slots[12].in_uop.bits.fp_val \n connect slots_12.io.in_uop.bits.fcn_op, issue_slots[12].in_uop.bits.fcn_op \n connect slots_12.io.in_uop.bits.fcn_dw, issue_slots[12].in_uop.bits.fcn_dw \n connect slots_12.io.in_uop.bits.frs3_en, issue_slots[12].in_uop.bits.frs3_en \n connect slots_12.io.in_uop.bits.lrs2_rtype, issue_slots[12].in_uop.bits.lrs2_rtype \n connect slots_12.io.in_uop.bits.lrs1_rtype, issue_slots[12].in_uop.bits.lrs1_rtype \n connect slots_12.io.in_uop.bits.dst_rtype, issue_slots[12].in_uop.bits.dst_rtype \n connect slots_12.io.in_uop.bits.lrs3, issue_slots[12].in_uop.bits.lrs3 \n connect slots_12.io.in_uop.bits.lrs2, issue_slots[12].in_uop.bits.lrs2 \n connect slots_12.io.in_uop.bits.lrs1, issue_slots[12].in_uop.bits.lrs1 \n connect slots_12.io.in_uop.bits.ldst, issue_slots[12].in_uop.bits.ldst \n connect slots_12.io.in_uop.bits.ldst_is_rs1, issue_slots[12].in_uop.bits.ldst_is_rs1 \n connect slots_12.io.in_uop.bits.csr_cmd, issue_slots[12].in_uop.bits.csr_cmd \n connect slots_12.io.in_uop.bits.flush_on_commit, issue_slots[12].in_uop.bits.flush_on_commit \n connect slots_12.io.in_uop.bits.is_unique, issue_slots[12].in_uop.bits.is_unique \n connect slots_12.io.in_uop.bits.uses_stq, issue_slots[12].in_uop.bits.uses_stq \n connect slots_12.io.in_uop.bits.uses_ldq, issue_slots[12].in_uop.bits.uses_ldq \n connect slots_12.io.in_uop.bits.mem_signed, issue_slots[12].in_uop.bits.mem_signed \n connect slots_12.io.in_uop.bits.mem_size, issue_slots[12].in_uop.bits.mem_size \n connect slots_12.io.in_uop.bits.mem_cmd, issue_slots[12].in_uop.bits.mem_cmd \n connect slots_12.io.in_uop.bits.exc_cause, issue_slots[12].in_uop.bits.exc_cause \n connect slots_12.io.in_uop.bits.exception, issue_slots[12].in_uop.bits.exception \n connect slots_12.io.in_uop.bits.stale_pdst, issue_slots[12].in_uop.bits.stale_pdst \n connect slots_12.io.in_uop.bits.ppred_busy, issue_slots[12].in_uop.bits.ppred_busy \n connect slots_12.io.in_uop.bits.prs3_busy, issue_slots[12].in_uop.bits.prs3_busy \n connect slots_12.io.in_uop.bits.prs2_busy, issue_slots[12].in_uop.bits.prs2_busy \n connect slots_12.io.in_uop.bits.prs1_busy, issue_slots[12].in_uop.bits.prs1_busy \n connect slots_12.io.in_uop.bits.ppred, issue_slots[12].in_uop.bits.ppred \n connect slots_12.io.in_uop.bits.prs3, issue_slots[12].in_uop.bits.prs3 \n connect slots_12.io.in_uop.bits.prs2, issue_slots[12].in_uop.bits.prs2 \n connect slots_12.io.in_uop.bits.prs1, issue_slots[12].in_uop.bits.prs1 \n connect slots_12.io.in_uop.bits.pdst, issue_slots[12].in_uop.bits.pdst \n connect slots_12.io.in_uop.bits.rxq_idx, issue_slots[12].in_uop.bits.rxq_idx \n connect slots_12.io.in_uop.bits.stq_idx, issue_slots[12].in_uop.bits.stq_idx \n connect slots_12.io.in_uop.bits.ldq_idx, issue_slots[12].in_uop.bits.ldq_idx \n connect slots_12.io.in_uop.bits.rob_idx, issue_slots[12].in_uop.bits.rob_idx \n connect slots_12.io.in_uop.bits.fp_ctrl.vec, issue_slots[12].in_uop.bits.fp_ctrl.vec \n connect slots_12.io.in_uop.bits.fp_ctrl.wflags, issue_slots[12].in_uop.bits.fp_ctrl.wflags \n connect slots_12.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[12].in_uop.bits.fp_ctrl.sqrt \n connect slots_12.io.in_uop.bits.fp_ctrl.div, issue_slots[12].in_uop.bits.fp_ctrl.div \n connect slots_12.io.in_uop.bits.fp_ctrl.fma, issue_slots[12].in_uop.bits.fp_ctrl.fma \n connect slots_12.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[12].in_uop.bits.fp_ctrl.fastpipe \n connect slots_12.io.in_uop.bits.fp_ctrl.toint, issue_slots[12].in_uop.bits.fp_ctrl.toint \n connect slots_12.io.in_uop.bits.fp_ctrl.fromint, issue_slots[12].in_uop.bits.fp_ctrl.fromint \n connect slots_12.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[12].in_uop.bits.fp_ctrl.typeTagOut \n connect slots_12.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[12].in_uop.bits.fp_ctrl.typeTagIn \n connect slots_12.io.in_uop.bits.fp_ctrl.swap23, issue_slots[12].in_uop.bits.fp_ctrl.swap23 \n connect slots_12.io.in_uop.bits.fp_ctrl.swap12, issue_slots[12].in_uop.bits.fp_ctrl.swap12 \n connect slots_12.io.in_uop.bits.fp_ctrl.ren3, issue_slots[12].in_uop.bits.fp_ctrl.ren3 \n connect slots_12.io.in_uop.bits.fp_ctrl.ren2, issue_slots[12].in_uop.bits.fp_ctrl.ren2 \n connect slots_12.io.in_uop.bits.fp_ctrl.ren1, issue_slots[12].in_uop.bits.fp_ctrl.ren1 \n connect slots_12.io.in_uop.bits.fp_ctrl.wen, issue_slots[12].in_uop.bits.fp_ctrl.wen \n connect slots_12.io.in_uop.bits.fp_ctrl.ldst, issue_slots[12].in_uop.bits.fp_ctrl.ldst \n connect slots_12.io.in_uop.bits.op2_sel, issue_slots[12].in_uop.bits.op2_sel \n connect slots_12.io.in_uop.bits.op1_sel, issue_slots[12].in_uop.bits.op1_sel \n connect slots_12.io.in_uop.bits.imm_packed, issue_slots[12].in_uop.bits.imm_packed \n connect slots_12.io.in_uop.bits.pimm, issue_slots[12].in_uop.bits.pimm \n connect slots_12.io.in_uop.bits.imm_sel, issue_slots[12].in_uop.bits.imm_sel \n connect slots_12.io.in_uop.bits.imm_rename, issue_slots[12].in_uop.bits.imm_rename \n connect slots_12.io.in_uop.bits.taken, issue_slots[12].in_uop.bits.taken \n connect slots_12.io.in_uop.bits.pc_lob, issue_slots[12].in_uop.bits.pc_lob \n connect slots_12.io.in_uop.bits.edge_inst, issue_slots[12].in_uop.bits.edge_inst \n connect slots_12.io.in_uop.bits.ftq_idx, issue_slots[12].in_uop.bits.ftq_idx \n connect slots_12.io.in_uop.bits.is_mov, issue_slots[12].in_uop.bits.is_mov \n connect slots_12.io.in_uop.bits.is_rocc, issue_slots[12].in_uop.bits.is_rocc \n connect slots_12.io.in_uop.bits.is_sys_pc2epc, issue_slots[12].in_uop.bits.is_sys_pc2epc \n connect slots_12.io.in_uop.bits.is_eret, issue_slots[12].in_uop.bits.is_eret \n connect slots_12.io.in_uop.bits.is_amo, issue_slots[12].in_uop.bits.is_amo \n connect slots_12.io.in_uop.bits.is_sfence, issue_slots[12].in_uop.bits.is_sfence \n connect slots_12.io.in_uop.bits.is_fencei, issue_slots[12].in_uop.bits.is_fencei \n connect slots_12.io.in_uop.bits.is_fence, issue_slots[12].in_uop.bits.is_fence \n connect slots_12.io.in_uop.bits.is_sfb, issue_slots[12].in_uop.bits.is_sfb \n connect slots_12.io.in_uop.bits.br_type, issue_slots[12].in_uop.bits.br_type \n connect slots_12.io.in_uop.bits.br_tag, issue_slots[12].in_uop.bits.br_tag \n connect slots_12.io.in_uop.bits.br_mask, issue_slots[12].in_uop.bits.br_mask \n connect slots_12.io.in_uop.bits.dis_col_sel, issue_slots[12].in_uop.bits.dis_col_sel \n connect slots_12.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[12].in_uop.bits.iw_p3_bypass_hint \n connect slots_12.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[12].in_uop.bits.iw_p2_bypass_hint \n connect slots_12.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[12].in_uop.bits.iw_p1_bypass_hint \n connect slots_12.io.in_uop.bits.iw_p2_speculative_child, issue_slots[12].in_uop.bits.iw_p2_speculative_child \n connect slots_12.io.in_uop.bits.iw_p1_speculative_child, issue_slots[12].in_uop.bits.iw_p1_speculative_child \n connect slots_12.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[12].in_uop.bits.iw_issued_partial_dgen \n connect slots_12.io.in_uop.bits.iw_issued_partial_agen, issue_slots[12].in_uop.bits.iw_issued_partial_agen \n connect slots_12.io.in_uop.bits.iw_issued, issue_slots[12].in_uop.bits.iw_issued \n connect slots_12.io.in_uop.bits.fu_code[0], issue_slots[12].in_uop.bits.fu_code[0] \n connect slots_12.io.in_uop.bits.fu_code[1], issue_slots[12].in_uop.bits.fu_code[1] \n connect slots_12.io.in_uop.bits.fu_code[2], issue_slots[12].in_uop.bits.fu_code[2] \n connect slots_12.io.in_uop.bits.fu_code[3], issue_slots[12].in_uop.bits.fu_code[3] \n connect slots_12.io.in_uop.bits.fu_code[4], issue_slots[12].in_uop.bits.fu_code[4] \n connect slots_12.io.in_uop.bits.fu_code[5], issue_slots[12].in_uop.bits.fu_code[5] \n connect slots_12.io.in_uop.bits.fu_code[6], issue_slots[12].in_uop.bits.fu_code[6] \n connect slots_12.io.in_uop.bits.fu_code[7], issue_slots[12].in_uop.bits.fu_code[7] \n connect slots_12.io.in_uop.bits.fu_code[8], issue_slots[12].in_uop.bits.fu_code[8] \n connect slots_12.io.in_uop.bits.fu_code[9], issue_slots[12].in_uop.bits.fu_code[9] \n connect slots_12.io.in_uop.bits.iq_type[0], issue_slots[12].in_uop.bits.iq_type[0] \n connect slots_12.io.in_uop.bits.iq_type[1], issue_slots[12].in_uop.bits.iq_type[1] \n connect slots_12.io.in_uop.bits.iq_type[2], issue_slots[12].in_uop.bits.iq_type[2] \n connect slots_12.io.in_uop.bits.iq_type[3], issue_slots[12].in_uop.bits.iq_type[3] \n connect slots_12.io.in_uop.bits.debug_pc, issue_slots[12].in_uop.bits.debug_pc \n connect slots_12.io.in_uop.bits.is_rvc, issue_slots[12].in_uop.bits.is_rvc \n connect slots_12.io.in_uop.bits.debug_inst, issue_slots[12].in_uop.bits.debug_inst \n connect slots_12.io.in_uop.bits.inst, issue_slots[12].in_uop.bits.inst \n connect slots_12.io.in_uop.valid, issue_slots[12].in_uop.valid \n connect issue_slots[12].iss_uop.debug_tsrc, slots_12.io.iss_uop.debug_tsrc \n connect issue_slots[12].iss_uop.debug_fsrc, slots_12.io.iss_uop.debug_fsrc \n connect issue_slots[12].iss_uop.bp_xcpt_if, slots_12.io.iss_uop.bp_xcpt_if \n connect issue_slots[12].iss_uop.bp_debug_if, slots_12.io.iss_uop.bp_debug_if \n connect issue_slots[12].iss_uop.xcpt_ma_if, slots_12.io.iss_uop.xcpt_ma_if \n connect issue_slots[12].iss_uop.xcpt_ae_if, slots_12.io.iss_uop.xcpt_ae_if \n connect issue_slots[12].iss_uop.xcpt_pf_if, slots_12.io.iss_uop.xcpt_pf_if \n connect issue_slots[12].iss_uop.fp_typ, slots_12.io.iss_uop.fp_typ \n connect issue_slots[12].iss_uop.fp_rm, slots_12.io.iss_uop.fp_rm \n connect issue_slots[12].iss_uop.fp_val, slots_12.io.iss_uop.fp_val \n connect issue_slots[12].iss_uop.fcn_op, slots_12.io.iss_uop.fcn_op \n connect issue_slots[12].iss_uop.fcn_dw, slots_12.io.iss_uop.fcn_dw \n connect issue_slots[12].iss_uop.frs3_en, slots_12.io.iss_uop.frs3_en \n connect issue_slots[12].iss_uop.lrs2_rtype, slots_12.io.iss_uop.lrs2_rtype \n connect issue_slots[12].iss_uop.lrs1_rtype, slots_12.io.iss_uop.lrs1_rtype \n connect issue_slots[12].iss_uop.dst_rtype, slots_12.io.iss_uop.dst_rtype \n connect issue_slots[12].iss_uop.lrs3, slots_12.io.iss_uop.lrs3 \n connect issue_slots[12].iss_uop.lrs2, slots_12.io.iss_uop.lrs2 \n connect issue_slots[12].iss_uop.lrs1, slots_12.io.iss_uop.lrs1 \n connect issue_slots[12].iss_uop.ldst, slots_12.io.iss_uop.ldst \n connect issue_slots[12].iss_uop.ldst_is_rs1, slots_12.io.iss_uop.ldst_is_rs1 \n connect issue_slots[12].iss_uop.csr_cmd, slots_12.io.iss_uop.csr_cmd \n connect issue_slots[12].iss_uop.flush_on_commit, slots_12.io.iss_uop.flush_on_commit \n connect issue_slots[12].iss_uop.is_unique, slots_12.io.iss_uop.is_unique \n connect issue_slots[12].iss_uop.uses_stq, slots_12.io.iss_uop.uses_stq \n connect issue_slots[12].iss_uop.uses_ldq, slots_12.io.iss_uop.uses_ldq \n connect issue_slots[12].iss_uop.mem_signed, slots_12.io.iss_uop.mem_signed \n connect issue_slots[12].iss_uop.mem_size, slots_12.io.iss_uop.mem_size \n connect issue_slots[12].iss_uop.mem_cmd, slots_12.io.iss_uop.mem_cmd \n connect issue_slots[12].iss_uop.exc_cause, slots_12.io.iss_uop.exc_cause \n connect issue_slots[12].iss_uop.exception, slots_12.io.iss_uop.exception \n connect issue_slots[12].iss_uop.stale_pdst, slots_12.io.iss_uop.stale_pdst \n connect issue_slots[12].iss_uop.ppred_busy, slots_12.io.iss_uop.ppred_busy \n connect issue_slots[12].iss_uop.prs3_busy, slots_12.io.iss_uop.prs3_busy \n connect issue_slots[12].iss_uop.prs2_busy, slots_12.io.iss_uop.prs2_busy \n connect issue_slots[12].iss_uop.prs1_busy, slots_12.io.iss_uop.prs1_busy \n connect issue_slots[12].iss_uop.ppred, slots_12.io.iss_uop.ppred \n connect issue_slots[12].iss_uop.prs3, slots_12.io.iss_uop.prs3 \n connect issue_slots[12].iss_uop.prs2, slots_12.io.iss_uop.prs2 \n connect issue_slots[12].iss_uop.prs1, slots_12.io.iss_uop.prs1 \n connect issue_slots[12].iss_uop.pdst, slots_12.io.iss_uop.pdst \n connect issue_slots[12].iss_uop.rxq_idx, slots_12.io.iss_uop.rxq_idx \n connect issue_slots[12].iss_uop.stq_idx, slots_12.io.iss_uop.stq_idx \n connect issue_slots[12].iss_uop.ldq_idx, slots_12.io.iss_uop.ldq_idx \n connect issue_slots[12].iss_uop.rob_idx, slots_12.io.iss_uop.rob_idx \n connect issue_slots[12].iss_uop.fp_ctrl.vec, slots_12.io.iss_uop.fp_ctrl.vec \n connect issue_slots[12].iss_uop.fp_ctrl.wflags, slots_12.io.iss_uop.fp_ctrl.wflags \n connect issue_slots[12].iss_uop.fp_ctrl.sqrt, slots_12.io.iss_uop.fp_ctrl.sqrt \n connect issue_slots[12].iss_uop.fp_ctrl.div, slots_12.io.iss_uop.fp_ctrl.div \n connect issue_slots[12].iss_uop.fp_ctrl.fma, slots_12.io.iss_uop.fp_ctrl.fma \n connect issue_slots[12].iss_uop.fp_ctrl.fastpipe, slots_12.io.iss_uop.fp_ctrl.fastpipe \n connect issue_slots[12].iss_uop.fp_ctrl.toint, slots_12.io.iss_uop.fp_ctrl.toint \n connect issue_slots[12].iss_uop.fp_ctrl.fromint, slots_12.io.iss_uop.fp_ctrl.fromint \n connect issue_slots[12].iss_uop.fp_ctrl.typeTagOut, slots_12.io.iss_uop.fp_ctrl.typeTagOut \n connect issue_slots[12].iss_uop.fp_ctrl.typeTagIn, slots_12.io.iss_uop.fp_ctrl.typeTagIn \n connect issue_slots[12].iss_uop.fp_ctrl.swap23, slots_12.io.iss_uop.fp_ctrl.swap23 \n connect issue_slots[12].iss_uop.fp_ctrl.swap12, slots_12.io.iss_uop.fp_ctrl.swap12 \n connect issue_slots[12].iss_uop.fp_ctrl.ren3, slots_12.io.iss_uop.fp_ctrl.ren3 \n connect issue_slots[12].iss_uop.fp_ctrl.ren2, slots_12.io.iss_uop.fp_ctrl.ren2 \n connect issue_slots[12].iss_uop.fp_ctrl.ren1, slots_12.io.iss_uop.fp_ctrl.ren1 \n connect issue_slots[12].iss_uop.fp_ctrl.wen, slots_12.io.iss_uop.fp_ctrl.wen \n connect issue_slots[12].iss_uop.fp_ctrl.ldst, slots_12.io.iss_uop.fp_ctrl.ldst \n connect issue_slots[12].iss_uop.op2_sel, slots_12.io.iss_uop.op2_sel \n connect issue_slots[12].iss_uop.op1_sel, slots_12.io.iss_uop.op1_sel \n connect issue_slots[12].iss_uop.imm_packed, slots_12.io.iss_uop.imm_packed \n connect issue_slots[12].iss_uop.pimm, slots_12.io.iss_uop.pimm \n connect issue_slots[12].iss_uop.imm_sel, slots_12.io.iss_uop.imm_sel \n connect issue_slots[12].iss_uop.imm_rename, slots_12.io.iss_uop.imm_rename \n connect issue_slots[12].iss_uop.taken, slots_12.io.iss_uop.taken \n connect issue_slots[12].iss_uop.pc_lob, slots_12.io.iss_uop.pc_lob \n connect issue_slots[12].iss_uop.edge_inst, slots_12.io.iss_uop.edge_inst \n connect issue_slots[12].iss_uop.ftq_idx, slots_12.io.iss_uop.ftq_idx \n connect issue_slots[12].iss_uop.is_mov, slots_12.io.iss_uop.is_mov \n connect issue_slots[12].iss_uop.is_rocc, slots_12.io.iss_uop.is_rocc \n connect issue_slots[12].iss_uop.is_sys_pc2epc, slots_12.io.iss_uop.is_sys_pc2epc \n connect issue_slots[12].iss_uop.is_eret, slots_12.io.iss_uop.is_eret \n connect issue_slots[12].iss_uop.is_amo, slots_12.io.iss_uop.is_amo \n connect issue_slots[12].iss_uop.is_sfence, slots_12.io.iss_uop.is_sfence \n connect issue_slots[12].iss_uop.is_fencei, slots_12.io.iss_uop.is_fencei \n connect issue_slots[12].iss_uop.is_fence, slots_12.io.iss_uop.is_fence \n connect issue_slots[12].iss_uop.is_sfb, slots_12.io.iss_uop.is_sfb \n connect issue_slots[12].iss_uop.br_type, slots_12.io.iss_uop.br_type \n connect issue_slots[12].iss_uop.br_tag, slots_12.io.iss_uop.br_tag \n connect issue_slots[12].iss_uop.br_mask, slots_12.io.iss_uop.br_mask \n connect issue_slots[12].iss_uop.dis_col_sel, slots_12.io.iss_uop.dis_col_sel \n connect issue_slots[12].iss_uop.iw_p3_bypass_hint, slots_12.io.iss_uop.iw_p3_bypass_hint \n connect issue_slots[12].iss_uop.iw_p2_bypass_hint, slots_12.io.iss_uop.iw_p2_bypass_hint \n connect issue_slots[12].iss_uop.iw_p1_bypass_hint, slots_12.io.iss_uop.iw_p1_bypass_hint \n connect issue_slots[12].iss_uop.iw_p2_speculative_child, slots_12.io.iss_uop.iw_p2_speculative_child \n connect issue_slots[12].iss_uop.iw_p1_speculative_child, slots_12.io.iss_uop.iw_p1_speculative_child \n connect issue_slots[12].iss_uop.iw_issued_partial_dgen, slots_12.io.iss_uop.iw_issued_partial_dgen \n connect issue_slots[12].iss_uop.iw_issued_partial_agen, slots_12.io.iss_uop.iw_issued_partial_agen \n connect issue_slots[12].iss_uop.iw_issued, slots_12.io.iss_uop.iw_issued \n connect issue_slots[12].iss_uop.fu_code[0], slots_12.io.iss_uop.fu_code[0] \n connect issue_slots[12].iss_uop.fu_code[1], slots_12.io.iss_uop.fu_code[1] \n connect issue_slots[12].iss_uop.fu_code[2], slots_12.io.iss_uop.fu_code[2] \n connect issue_slots[12].iss_uop.fu_code[3], slots_12.io.iss_uop.fu_code[3] \n connect issue_slots[12].iss_uop.fu_code[4], slots_12.io.iss_uop.fu_code[4] \n connect issue_slots[12].iss_uop.fu_code[5], slots_12.io.iss_uop.fu_code[5] \n connect issue_slots[12].iss_uop.fu_code[6], slots_12.io.iss_uop.fu_code[6] \n connect issue_slots[12].iss_uop.fu_code[7], slots_12.io.iss_uop.fu_code[7] \n connect issue_slots[12].iss_uop.fu_code[8], slots_12.io.iss_uop.fu_code[8] \n connect issue_slots[12].iss_uop.fu_code[9], slots_12.io.iss_uop.fu_code[9] \n connect issue_slots[12].iss_uop.iq_type[0], slots_12.io.iss_uop.iq_type[0] \n connect issue_slots[12].iss_uop.iq_type[1], slots_12.io.iss_uop.iq_type[1] \n connect issue_slots[12].iss_uop.iq_type[2], slots_12.io.iss_uop.iq_type[2] \n connect issue_slots[12].iss_uop.iq_type[3], slots_12.io.iss_uop.iq_type[3] \n connect issue_slots[12].iss_uop.debug_pc, slots_12.io.iss_uop.debug_pc \n connect issue_slots[12].iss_uop.is_rvc, slots_12.io.iss_uop.is_rvc \n connect issue_slots[12].iss_uop.debug_inst, slots_12.io.iss_uop.debug_inst \n connect issue_slots[12].iss_uop.inst, slots_12.io.iss_uop.inst \n connect slots_12.io.grant, issue_slots[12].grant \n connect issue_slots[12].request, slots_12.io.request \n connect issue_slots[12].will_be_valid, slots_12.io.will_be_valid \n connect issue_slots[12].valid, slots_12.io.valid \n connect slots_13.io.child_rebusys, issue_slots[13].child_rebusys \n connect slots_13.io.pred_wakeup_port.bits, issue_slots[13].pred_wakeup_port.bits \n connect slots_13.io.pred_wakeup_port.valid, issue_slots[13].pred_wakeup_port.valid \n connect slots_13.io.wakeup_ports[0].bits.rebusy, issue_slots[13].wakeup_ports[0].bits.rebusy \n connect slots_13.io.wakeup_ports[0].bits.speculative_mask, issue_slots[13].wakeup_ports[0].bits.speculative_mask \n connect slots_13.io.wakeup_ports[0].bits.bypassable, issue_slots[13].wakeup_ports[0].bits.bypassable \n connect slots_13.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[13].wakeup_ports[0].bits.uop.debug_tsrc \n connect slots_13.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[13].wakeup_ports[0].bits.uop.debug_fsrc \n connect slots_13.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[13].wakeup_ports[0].bits.uop.bp_xcpt_if \n connect slots_13.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[13].wakeup_ports[0].bits.uop.bp_debug_if \n connect slots_13.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[13].wakeup_ports[0].bits.uop.xcpt_ma_if \n connect slots_13.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[13].wakeup_ports[0].bits.uop.xcpt_ae_if \n connect slots_13.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[13].wakeup_ports[0].bits.uop.xcpt_pf_if \n connect slots_13.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[13].wakeup_ports[0].bits.uop.fp_typ \n connect slots_13.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[13].wakeup_ports[0].bits.uop.fp_rm \n connect slots_13.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[13].wakeup_ports[0].bits.uop.fp_val \n connect slots_13.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[13].wakeup_ports[0].bits.uop.fcn_op \n connect slots_13.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[13].wakeup_ports[0].bits.uop.fcn_dw \n connect slots_13.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[13].wakeup_ports[0].bits.uop.frs3_en \n connect slots_13.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[13].wakeup_ports[0].bits.uop.lrs2_rtype \n connect slots_13.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[13].wakeup_ports[0].bits.uop.lrs1_rtype \n connect slots_13.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[13].wakeup_ports[0].bits.uop.dst_rtype \n connect slots_13.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[13].wakeup_ports[0].bits.uop.lrs3 \n connect slots_13.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[13].wakeup_ports[0].bits.uop.lrs2 \n connect slots_13.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[13].wakeup_ports[0].bits.uop.lrs1 \n connect slots_13.io.wakeup_ports[0].bits.uop.ldst, issue_slots[13].wakeup_ports[0].bits.uop.ldst \n connect slots_13.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[13].wakeup_ports[0].bits.uop.ldst_is_rs1 \n connect slots_13.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[13].wakeup_ports[0].bits.uop.csr_cmd \n connect slots_13.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[13].wakeup_ports[0].bits.uop.flush_on_commit \n connect slots_13.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[13].wakeup_ports[0].bits.uop.is_unique \n connect slots_13.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[13].wakeup_ports[0].bits.uop.uses_stq \n connect slots_13.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[13].wakeup_ports[0].bits.uop.uses_ldq \n connect slots_13.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[13].wakeup_ports[0].bits.uop.mem_signed \n connect slots_13.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[13].wakeup_ports[0].bits.uop.mem_size \n connect slots_13.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[13].wakeup_ports[0].bits.uop.mem_cmd \n connect slots_13.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[13].wakeup_ports[0].bits.uop.exc_cause \n connect slots_13.io.wakeup_ports[0].bits.uop.exception, issue_slots[13].wakeup_ports[0].bits.uop.exception \n connect slots_13.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[13].wakeup_ports[0].bits.uop.stale_pdst \n connect slots_13.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[13].wakeup_ports[0].bits.uop.ppred_busy \n connect slots_13.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[13].wakeup_ports[0].bits.uop.prs3_busy \n connect slots_13.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[13].wakeup_ports[0].bits.uop.prs2_busy \n connect slots_13.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[13].wakeup_ports[0].bits.uop.prs1_busy \n connect slots_13.io.wakeup_ports[0].bits.uop.ppred, issue_slots[13].wakeup_ports[0].bits.uop.ppred \n connect slots_13.io.wakeup_ports[0].bits.uop.prs3, issue_slots[13].wakeup_ports[0].bits.uop.prs3 \n connect slots_13.io.wakeup_ports[0].bits.uop.prs2, issue_slots[13].wakeup_ports[0].bits.uop.prs2 \n connect slots_13.io.wakeup_ports[0].bits.uop.prs1, issue_slots[13].wakeup_ports[0].bits.uop.prs1 \n connect slots_13.io.wakeup_ports[0].bits.uop.pdst, issue_slots[13].wakeup_ports[0].bits.uop.pdst \n connect slots_13.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[13].wakeup_ports[0].bits.uop.rxq_idx \n connect slots_13.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[13].wakeup_ports[0].bits.uop.stq_idx \n connect slots_13.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[13].wakeup_ports[0].bits.uop.ldq_idx \n connect slots_13.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[13].wakeup_ports[0].bits.uop.rob_idx \n connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.vec \n connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.wflags \n connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.sqrt \n connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.div \n connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.fma \n connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe \n connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.toint \n connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.fromint \n connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut \n connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn \n connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.swap23 \n connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.swap12 \n connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.ren3 \n connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.ren2 \n connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.ren1 \n connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.wen \n connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.ldst \n connect slots_13.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[13].wakeup_ports[0].bits.uop.op2_sel \n connect slots_13.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[13].wakeup_ports[0].bits.uop.op1_sel \n connect slots_13.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[13].wakeup_ports[0].bits.uop.imm_packed \n connect slots_13.io.wakeup_ports[0].bits.uop.pimm, issue_slots[13].wakeup_ports[0].bits.uop.pimm \n connect slots_13.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[13].wakeup_ports[0].bits.uop.imm_sel \n connect slots_13.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[13].wakeup_ports[0].bits.uop.imm_rename \n connect slots_13.io.wakeup_ports[0].bits.uop.taken, issue_slots[13].wakeup_ports[0].bits.uop.taken \n connect slots_13.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[13].wakeup_ports[0].bits.uop.pc_lob \n connect slots_13.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[13].wakeup_ports[0].bits.uop.edge_inst \n connect slots_13.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[13].wakeup_ports[0].bits.uop.ftq_idx \n connect slots_13.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[13].wakeup_ports[0].bits.uop.is_mov \n connect slots_13.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[13].wakeup_ports[0].bits.uop.is_rocc \n connect slots_13.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[13].wakeup_ports[0].bits.uop.is_sys_pc2epc \n connect slots_13.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[13].wakeup_ports[0].bits.uop.is_eret \n connect slots_13.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[13].wakeup_ports[0].bits.uop.is_amo \n connect slots_13.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[13].wakeup_ports[0].bits.uop.is_sfence \n connect slots_13.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[13].wakeup_ports[0].bits.uop.is_fencei \n connect slots_13.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[13].wakeup_ports[0].bits.uop.is_fence \n connect slots_13.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[13].wakeup_ports[0].bits.uop.is_sfb \n connect slots_13.io.wakeup_ports[0].bits.uop.br_type, issue_slots[13].wakeup_ports[0].bits.uop.br_type \n connect slots_13.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[13].wakeup_ports[0].bits.uop.br_tag \n connect slots_13.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[13].wakeup_ports[0].bits.uop.br_mask \n connect slots_13.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[13].wakeup_ports[0].bits.uop.dis_col_sel \n connect slots_13.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[13].wakeup_ports[0].bits.uop.iw_p3_bypass_hint \n connect slots_13.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[13].wakeup_ports[0].bits.uop.iw_p2_bypass_hint \n connect slots_13.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[13].wakeup_ports[0].bits.uop.iw_p1_bypass_hint \n connect slots_13.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[13].wakeup_ports[0].bits.uop.iw_p2_speculative_child \n connect slots_13.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[13].wakeup_ports[0].bits.uop.iw_p1_speculative_child \n connect slots_13.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[13].wakeup_ports[0].bits.uop.iw_issued_partial_dgen \n connect slots_13.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[13].wakeup_ports[0].bits.uop.iw_issued_partial_agen \n connect slots_13.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[13].wakeup_ports[0].bits.uop.iw_issued \n connect slots_13.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[13].wakeup_ports[0].bits.uop.fu_code[0] \n connect slots_13.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[13].wakeup_ports[0].bits.uop.fu_code[1] \n connect slots_13.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[13].wakeup_ports[0].bits.uop.fu_code[2] \n connect slots_13.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[13].wakeup_ports[0].bits.uop.fu_code[3] \n connect slots_13.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[13].wakeup_ports[0].bits.uop.fu_code[4] \n connect slots_13.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[13].wakeup_ports[0].bits.uop.fu_code[5] \n connect slots_13.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[13].wakeup_ports[0].bits.uop.fu_code[6] \n connect slots_13.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[13].wakeup_ports[0].bits.uop.fu_code[7] \n connect slots_13.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[13].wakeup_ports[0].bits.uop.fu_code[8] \n connect slots_13.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[13].wakeup_ports[0].bits.uop.fu_code[9] \n connect slots_13.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[13].wakeup_ports[0].bits.uop.iq_type[0] \n connect slots_13.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[13].wakeup_ports[0].bits.uop.iq_type[1] \n connect slots_13.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[13].wakeup_ports[0].bits.uop.iq_type[2] \n connect slots_13.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[13].wakeup_ports[0].bits.uop.iq_type[3] \n connect slots_13.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[13].wakeup_ports[0].bits.uop.debug_pc \n connect slots_13.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[13].wakeup_ports[0].bits.uop.is_rvc \n connect slots_13.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[13].wakeup_ports[0].bits.uop.debug_inst \n connect slots_13.io.wakeup_ports[0].bits.uop.inst, issue_slots[13].wakeup_ports[0].bits.uop.inst \n connect slots_13.io.wakeup_ports[0].valid, issue_slots[13].wakeup_ports[0].valid \n connect slots_13.io.wakeup_ports[1].bits.rebusy, issue_slots[13].wakeup_ports[1].bits.rebusy \n connect slots_13.io.wakeup_ports[1].bits.speculative_mask, issue_slots[13].wakeup_ports[1].bits.speculative_mask \n connect slots_13.io.wakeup_ports[1].bits.bypassable, issue_slots[13].wakeup_ports[1].bits.bypassable \n connect slots_13.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[13].wakeup_ports[1].bits.uop.debug_tsrc \n connect slots_13.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[13].wakeup_ports[1].bits.uop.debug_fsrc \n connect slots_13.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[13].wakeup_ports[1].bits.uop.bp_xcpt_if \n connect slots_13.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[13].wakeup_ports[1].bits.uop.bp_debug_if \n connect slots_13.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[13].wakeup_ports[1].bits.uop.xcpt_ma_if \n connect slots_13.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[13].wakeup_ports[1].bits.uop.xcpt_ae_if \n connect slots_13.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[13].wakeup_ports[1].bits.uop.xcpt_pf_if \n connect slots_13.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[13].wakeup_ports[1].bits.uop.fp_typ \n connect slots_13.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[13].wakeup_ports[1].bits.uop.fp_rm \n connect slots_13.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[13].wakeup_ports[1].bits.uop.fp_val \n connect slots_13.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[13].wakeup_ports[1].bits.uop.fcn_op \n connect slots_13.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[13].wakeup_ports[1].bits.uop.fcn_dw \n connect slots_13.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[13].wakeup_ports[1].bits.uop.frs3_en \n connect slots_13.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[13].wakeup_ports[1].bits.uop.lrs2_rtype \n connect slots_13.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[13].wakeup_ports[1].bits.uop.lrs1_rtype \n connect slots_13.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[13].wakeup_ports[1].bits.uop.dst_rtype \n connect slots_13.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[13].wakeup_ports[1].bits.uop.lrs3 \n connect slots_13.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[13].wakeup_ports[1].bits.uop.lrs2 \n connect slots_13.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[13].wakeup_ports[1].bits.uop.lrs1 \n connect slots_13.io.wakeup_ports[1].bits.uop.ldst, issue_slots[13].wakeup_ports[1].bits.uop.ldst \n connect slots_13.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[13].wakeup_ports[1].bits.uop.ldst_is_rs1 \n connect slots_13.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[13].wakeup_ports[1].bits.uop.csr_cmd \n connect slots_13.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[13].wakeup_ports[1].bits.uop.flush_on_commit \n connect slots_13.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[13].wakeup_ports[1].bits.uop.is_unique \n connect slots_13.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[13].wakeup_ports[1].bits.uop.uses_stq \n connect slots_13.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[13].wakeup_ports[1].bits.uop.uses_ldq \n connect slots_13.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[13].wakeup_ports[1].bits.uop.mem_signed \n connect slots_13.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[13].wakeup_ports[1].bits.uop.mem_size \n connect slots_13.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[13].wakeup_ports[1].bits.uop.mem_cmd \n connect slots_13.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[13].wakeup_ports[1].bits.uop.exc_cause \n connect slots_13.io.wakeup_ports[1].bits.uop.exception, issue_slots[13].wakeup_ports[1].bits.uop.exception \n connect slots_13.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[13].wakeup_ports[1].bits.uop.stale_pdst \n connect slots_13.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[13].wakeup_ports[1].bits.uop.ppred_busy \n connect slots_13.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[13].wakeup_ports[1].bits.uop.prs3_busy \n connect slots_13.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[13].wakeup_ports[1].bits.uop.prs2_busy \n connect slots_13.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[13].wakeup_ports[1].bits.uop.prs1_busy \n connect slots_13.io.wakeup_ports[1].bits.uop.ppred, issue_slots[13].wakeup_ports[1].bits.uop.ppred \n connect slots_13.io.wakeup_ports[1].bits.uop.prs3, issue_slots[13].wakeup_ports[1].bits.uop.prs3 \n connect slots_13.io.wakeup_ports[1].bits.uop.prs2, issue_slots[13].wakeup_ports[1].bits.uop.prs2 \n connect slots_13.io.wakeup_ports[1].bits.uop.prs1, issue_slots[13].wakeup_ports[1].bits.uop.prs1 \n connect slots_13.io.wakeup_ports[1].bits.uop.pdst, issue_slots[13].wakeup_ports[1].bits.uop.pdst \n connect slots_13.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[13].wakeup_ports[1].bits.uop.rxq_idx \n connect slots_13.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[13].wakeup_ports[1].bits.uop.stq_idx \n connect slots_13.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[13].wakeup_ports[1].bits.uop.ldq_idx \n connect slots_13.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[13].wakeup_ports[1].bits.uop.rob_idx \n connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.vec \n connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.wflags \n connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.sqrt \n connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.div \n connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.fma \n connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe \n connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.toint \n connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.fromint \n connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut \n connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn \n connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.swap23 \n connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.swap12 \n connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.ren3 \n connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.ren2 \n connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.ren1 \n connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.wen \n connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.ldst \n connect slots_13.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[13].wakeup_ports[1].bits.uop.op2_sel \n connect slots_13.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[13].wakeup_ports[1].bits.uop.op1_sel \n connect slots_13.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[13].wakeup_ports[1].bits.uop.imm_packed \n connect slots_13.io.wakeup_ports[1].bits.uop.pimm, issue_slots[13].wakeup_ports[1].bits.uop.pimm \n connect slots_13.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[13].wakeup_ports[1].bits.uop.imm_sel \n connect slots_13.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[13].wakeup_ports[1].bits.uop.imm_rename \n connect slots_13.io.wakeup_ports[1].bits.uop.taken, issue_slots[13].wakeup_ports[1].bits.uop.taken \n connect slots_13.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[13].wakeup_ports[1].bits.uop.pc_lob \n connect slots_13.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[13].wakeup_ports[1].bits.uop.edge_inst \n connect slots_13.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[13].wakeup_ports[1].bits.uop.ftq_idx \n connect slots_13.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[13].wakeup_ports[1].bits.uop.is_mov \n connect slots_13.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[13].wakeup_ports[1].bits.uop.is_rocc \n connect slots_13.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[13].wakeup_ports[1].bits.uop.is_sys_pc2epc \n connect slots_13.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[13].wakeup_ports[1].bits.uop.is_eret \n connect slots_13.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[13].wakeup_ports[1].bits.uop.is_amo \n connect slots_13.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[13].wakeup_ports[1].bits.uop.is_sfence \n connect slots_13.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[13].wakeup_ports[1].bits.uop.is_fencei \n connect slots_13.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[13].wakeup_ports[1].bits.uop.is_fence \n connect slots_13.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[13].wakeup_ports[1].bits.uop.is_sfb \n connect slots_13.io.wakeup_ports[1].bits.uop.br_type, issue_slots[13].wakeup_ports[1].bits.uop.br_type \n connect slots_13.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[13].wakeup_ports[1].bits.uop.br_tag \n connect slots_13.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[13].wakeup_ports[1].bits.uop.br_mask \n connect slots_13.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[13].wakeup_ports[1].bits.uop.dis_col_sel \n connect slots_13.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[13].wakeup_ports[1].bits.uop.iw_p3_bypass_hint \n connect slots_13.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[13].wakeup_ports[1].bits.uop.iw_p2_bypass_hint \n connect slots_13.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[13].wakeup_ports[1].bits.uop.iw_p1_bypass_hint \n connect slots_13.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[13].wakeup_ports[1].bits.uop.iw_p2_speculative_child \n connect slots_13.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[13].wakeup_ports[1].bits.uop.iw_p1_speculative_child \n connect slots_13.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[13].wakeup_ports[1].bits.uop.iw_issued_partial_dgen \n connect slots_13.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[13].wakeup_ports[1].bits.uop.iw_issued_partial_agen \n connect slots_13.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[13].wakeup_ports[1].bits.uop.iw_issued \n connect slots_13.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[13].wakeup_ports[1].bits.uop.fu_code[0] \n connect slots_13.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[13].wakeup_ports[1].bits.uop.fu_code[1] \n connect slots_13.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[13].wakeup_ports[1].bits.uop.fu_code[2] \n connect slots_13.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[13].wakeup_ports[1].bits.uop.fu_code[3] \n connect slots_13.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[13].wakeup_ports[1].bits.uop.fu_code[4] \n connect slots_13.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[13].wakeup_ports[1].bits.uop.fu_code[5] \n connect slots_13.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[13].wakeup_ports[1].bits.uop.fu_code[6] \n connect slots_13.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[13].wakeup_ports[1].bits.uop.fu_code[7] \n connect slots_13.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[13].wakeup_ports[1].bits.uop.fu_code[8] \n connect slots_13.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[13].wakeup_ports[1].bits.uop.fu_code[9] \n connect slots_13.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[13].wakeup_ports[1].bits.uop.iq_type[0] \n connect slots_13.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[13].wakeup_ports[1].bits.uop.iq_type[1] \n connect slots_13.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[13].wakeup_ports[1].bits.uop.iq_type[2] \n connect slots_13.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[13].wakeup_ports[1].bits.uop.iq_type[3] \n connect slots_13.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[13].wakeup_ports[1].bits.uop.debug_pc \n connect slots_13.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[13].wakeup_ports[1].bits.uop.is_rvc \n connect slots_13.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[13].wakeup_ports[1].bits.uop.debug_inst \n connect slots_13.io.wakeup_ports[1].bits.uop.inst, issue_slots[13].wakeup_ports[1].bits.uop.inst \n connect slots_13.io.wakeup_ports[1].valid, issue_slots[13].wakeup_ports[1].valid \n connect slots_13.io.wakeup_ports[2].bits.rebusy, issue_slots[13].wakeup_ports[2].bits.rebusy \n connect slots_13.io.wakeup_ports[2].bits.speculative_mask, issue_slots[13].wakeup_ports[2].bits.speculative_mask \n connect slots_13.io.wakeup_ports[2].bits.bypassable, issue_slots[13].wakeup_ports[2].bits.bypassable \n connect slots_13.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[13].wakeup_ports[2].bits.uop.debug_tsrc \n connect slots_13.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[13].wakeup_ports[2].bits.uop.debug_fsrc \n connect slots_13.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[13].wakeup_ports[2].bits.uop.bp_xcpt_if \n connect slots_13.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[13].wakeup_ports[2].bits.uop.bp_debug_if \n connect slots_13.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[13].wakeup_ports[2].bits.uop.xcpt_ma_if \n connect slots_13.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[13].wakeup_ports[2].bits.uop.xcpt_ae_if \n connect slots_13.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[13].wakeup_ports[2].bits.uop.xcpt_pf_if \n connect slots_13.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[13].wakeup_ports[2].bits.uop.fp_typ \n connect slots_13.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[13].wakeup_ports[2].bits.uop.fp_rm \n connect slots_13.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[13].wakeup_ports[2].bits.uop.fp_val \n connect slots_13.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[13].wakeup_ports[2].bits.uop.fcn_op \n connect slots_13.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[13].wakeup_ports[2].bits.uop.fcn_dw \n connect slots_13.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[13].wakeup_ports[2].bits.uop.frs3_en \n connect slots_13.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[13].wakeup_ports[2].bits.uop.lrs2_rtype \n connect slots_13.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[13].wakeup_ports[2].bits.uop.lrs1_rtype \n connect slots_13.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[13].wakeup_ports[2].bits.uop.dst_rtype \n connect slots_13.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[13].wakeup_ports[2].bits.uop.lrs3 \n connect slots_13.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[13].wakeup_ports[2].bits.uop.lrs2 \n connect slots_13.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[13].wakeup_ports[2].bits.uop.lrs1 \n connect slots_13.io.wakeup_ports[2].bits.uop.ldst, issue_slots[13].wakeup_ports[2].bits.uop.ldst \n connect slots_13.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[13].wakeup_ports[2].bits.uop.ldst_is_rs1 \n connect slots_13.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[13].wakeup_ports[2].bits.uop.csr_cmd \n connect slots_13.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[13].wakeup_ports[2].bits.uop.flush_on_commit \n connect slots_13.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[13].wakeup_ports[2].bits.uop.is_unique \n connect slots_13.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[13].wakeup_ports[2].bits.uop.uses_stq \n connect slots_13.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[13].wakeup_ports[2].bits.uop.uses_ldq \n connect slots_13.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[13].wakeup_ports[2].bits.uop.mem_signed \n connect slots_13.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[13].wakeup_ports[2].bits.uop.mem_size \n connect slots_13.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[13].wakeup_ports[2].bits.uop.mem_cmd \n connect slots_13.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[13].wakeup_ports[2].bits.uop.exc_cause \n connect slots_13.io.wakeup_ports[2].bits.uop.exception, issue_slots[13].wakeup_ports[2].bits.uop.exception \n connect slots_13.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[13].wakeup_ports[2].bits.uop.stale_pdst \n connect slots_13.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[13].wakeup_ports[2].bits.uop.ppred_busy \n connect slots_13.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[13].wakeup_ports[2].bits.uop.prs3_busy \n connect slots_13.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[13].wakeup_ports[2].bits.uop.prs2_busy \n connect slots_13.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[13].wakeup_ports[2].bits.uop.prs1_busy \n connect slots_13.io.wakeup_ports[2].bits.uop.ppred, issue_slots[13].wakeup_ports[2].bits.uop.ppred \n connect slots_13.io.wakeup_ports[2].bits.uop.prs3, issue_slots[13].wakeup_ports[2].bits.uop.prs3 \n connect slots_13.io.wakeup_ports[2].bits.uop.prs2, issue_slots[13].wakeup_ports[2].bits.uop.prs2 \n connect slots_13.io.wakeup_ports[2].bits.uop.prs1, issue_slots[13].wakeup_ports[2].bits.uop.prs1 \n connect slots_13.io.wakeup_ports[2].bits.uop.pdst, issue_slots[13].wakeup_ports[2].bits.uop.pdst \n connect slots_13.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[13].wakeup_ports[2].bits.uop.rxq_idx \n connect slots_13.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[13].wakeup_ports[2].bits.uop.stq_idx \n connect slots_13.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[13].wakeup_ports[2].bits.uop.ldq_idx \n connect slots_13.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[13].wakeup_ports[2].bits.uop.rob_idx \n connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.vec \n connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.wflags \n connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.sqrt \n connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.div \n connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.fma \n connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe \n connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.toint \n connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.fromint \n connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut \n connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn \n connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.swap23 \n connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.swap12 \n connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.ren3 \n connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.ren2 \n connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.ren1 \n connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.wen \n connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.ldst \n connect slots_13.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[13].wakeup_ports[2].bits.uop.op2_sel \n connect slots_13.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[13].wakeup_ports[2].bits.uop.op1_sel \n connect slots_13.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[13].wakeup_ports[2].bits.uop.imm_packed \n connect slots_13.io.wakeup_ports[2].bits.uop.pimm, issue_slots[13].wakeup_ports[2].bits.uop.pimm \n connect slots_13.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[13].wakeup_ports[2].bits.uop.imm_sel \n connect slots_13.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[13].wakeup_ports[2].bits.uop.imm_rename \n connect slots_13.io.wakeup_ports[2].bits.uop.taken, issue_slots[13].wakeup_ports[2].bits.uop.taken \n connect slots_13.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[13].wakeup_ports[2].bits.uop.pc_lob \n connect slots_13.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[13].wakeup_ports[2].bits.uop.edge_inst \n connect slots_13.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[13].wakeup_ports[2].bits.uop.ftq_idx \n connect slots_13.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[13].wakeup_ports[2].bits.uop.is_mov \n connect slots_13.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[13].wakeup_ports[2].bits.uop.is_rocc \n connect slots_13.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[13].wakeup_ports[2].bits.uop.is_sys_pc2epc \n connect slots_13.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[13].wakeup_ports[2].bits.uop.is_eret \n connect slots_13.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[13].wakeup_ports[2].bits.uop.is_amo \n connect slots_13.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[13].wakeup_ports[2].bits.uop.is_sfence \n connect slots_13.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[13].wakeup_ports[2].bits.uop.is_fencei \n connect slots_13.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[13].wakeup_ports[2].bits.uop.is_fence \n connect slots_13.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[13].wakeup_ports[2].bits.uop.is_sfb \n connect slots_13.io.wakeup_ports[2].bits.uop.br_type, issue_slots[13].wakeup_ports[2].bits.uop.br_type \n connect slots_13.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[13].wakeup_ports[2].bits.uop.br_tag \n connect slots_13.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[13].wakeup_ports[2].bits.uop.br_mask \n connect slots_13.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[13].wakeup_ports[2].bits.uop.dis_col_sel \n connect slots_13.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[13].wakeup_ports[2].bits.uop.iw_p3_bypass_hint \n connect slots_13.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[13].wakeup_ports[2].bits.uop.iw_p2_bypass_hint \n connect slots_13.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[13].wakeup_ports[2].bits.uop.iw_p1_bypass_hint \n connect slots_13.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[13].wakeup_ports[2].bits.uop.iw_p2_speculative_child \n connect slots_13.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[13].wakeup_ports[2].bits.uop.iw_p1_speculative_child \n connect slots_13.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[13].wakeup_ports[2].bits.uop.iw_issued_partial_dgen \n connect slots_13.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[13].wakeup_ports[2].bits.uop.iw_issued_partial_agen \n connect slots_13.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[13].wakeup_ports[2].bits.uop.iw_issued \n connect slots_13.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[13].wakeup_ports[2].bits.uop.fu_code[0] \n connect slots_13.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[13].wakeup_ports[2].bits.uop.fu_code[1] \n connect slots_13.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[13].wakeup_ports[2].bits.uop.fu_code[2] \n connect slots_13.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[13].wakeup_ports[2].bits.uop.fu_code[3] \n connect slots_13.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[13].wakeup_ports[2].bits.uop.fu_code[4] \n connect slots_13.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[13].wakeup_ports[2].bits.uop.fu_code[5] \n connect slots_13.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[13].wakeup_ports[2].bits.uop.fu_code[6] \n connect slots_13.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[13].wakeup_ports[2].bits.uop.fu_code[7] \n connect slots_13.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[13].wakeup_ports[2].bits.uop.fu_code[8] \n connect slots_13.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[13].wakeup_ports[2].bits.uop.fu_code[9] \n connect slots_13.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[13].wakeup_ports[2].bits.uop.iq_type[0] \n connect slots_13.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[13].wakeup_ports[2].bits.uop.iq_type[1] \n connect slots_13.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[13].wakeup_ports[2].bits.uop.iq_type[2] \n connect slots_13.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[13].wakeup_ports[2].bits.uop.iq_type[3] \n connect slots_13.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[13].wakeup_ports[2].bits.uop.debug_pc \n connect slots_13.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[13].wakeup_ports[2].bits.uop.is_rvc \n connect slots_13.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[13].wakeup_ports[2].bits.uop.debug_inst \n connect slots_13.io.wakeup_ports[2].bits.uop.inst, issue_slots[13].wakeup_ports[2].bits.uop.inst \n connect slots_13.io.wakeup_ports[2].valid, issue_slots[13].wakeup_ports[2].valid \n connect slots_13.io.wakeup_ports[3].bits.rebusy, issue_slots[13].wakeup_ports[3].bits.rebusy \n connect slots_13.io.wakeup_ports[3].bits.speculative_mask, issue_slots[13].wakeup_ports[3].bits.speculative_mask \n connect slots_13.io.wakeup_ports[3].bits.bypassable, issue_slots[13].wakeup_ports[3].bits.bypassable \n connect slots_13.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[13].wakeup_ports[3].bits.uop.debug_tsrc \n connect slots_13.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[13].wakeup_ports[3].bits.uop.debug_fsrc \n connect slots_13.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[13].wakeup_ports[3].bits.uop.bp_xcpt_if \n connect slots_13.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[13].wakeup_ports[3].bits.uop.bp_debug_if \n connect slots_13.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[13].wakeup_ports[3].bits.uop.xcpt_ma_if \n connect slots_13.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[13].wakeup_ports[3].bits.uop.xcpt_ae_if \n connect slots_13.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[13].wakeup_ports[3].bits.uop.xcpt_pf_if \n connect slots_13.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[13].wakeup_ports[3].bits.uop.fp_typ \n connect slots_13.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[13].wakeup_ports[3].bits.uop.fp_rm \n connect slots_13.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[13].wakeup_ports[3].bits.uop.fp_val \n connect slots_13.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[13].wakeup_ports[3].bits.uop.fcn_op \n connect slots_13.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[13].wakeup_ports[3].bits.uop.fcn_dw \n connect slots_13.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[13].wakeup_ports[3].bits.uop.frs3_en \n connect slots_13.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[13].wakeup_ports[3].bits.uop.lrs2_rtype \n connect slots_13.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[13].wakeup_ports[3].bits.uop.lrs1_rtype \n connect slots_13.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[13].wakeup_ports[3].bits.uop.dst_rtype \n connect slots_13.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[13].wakeup_ports[3].bits.uop.lrs3 \n connect slots_13.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[13].wakeup_ports[3].bits.uop.lrs2 \n connect slots_13.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[13].wakeup_ports[3].bits.uop.lrs1 \n connect slots_13.io.wakeup_ports[3].bits.uop.ldst, issue_slots[13].wakeup_ports[3].bits.uop.ldst \n connect slots_13.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[13].wakeup_ports[3].bits.uop.ldst_is_rs1 \n connect slots_13.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[13].wakeup_ports[3].bits.uop.csr_cmd \n connect slots_13.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[13].wakeup_ports[3].bits.uop.flush_on_commit \n connect slots_13.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[13].wakeup_ports[3].bits.uop.is_unique \n connect slots_13.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[13].wakeup_ports[3].bits.uop.uses_stq \n connect slots_13.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[13].wakeup_ports[3].bits.uop.uses_ldq \n connect slots_13.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[13].wakeup_ports[3].bits.uop.mem_signed \n connect slots_13.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[13].wakeup_ports[3].bits.uop.mem_size \n connect slots_13.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[13].wakeup_ports[3].bits.uop.mem_cmd \n connect slots_13.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[13].wakeup_ports[3].bits.uop.exc_cause \n connect slots_13.io.wakeup_ports[3].bits.uop.exception, issue_slots[13].wakeup_ports[3].bits.uop.exception \n connect slots_13.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[13].wakeup_ports[3].bits.uop.stale_pdst \n connect slots_13.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[13].wakeup_ports[3].bits.uop.ppred_busy \n connect slots_13.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[13].wakeup_ports[3].bits.uop.prs3_busy \n connect slots_13.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[13].wakeup_ports[3].bits.uop.prs2_busy \n connect slots_13.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[13].wakeup_ports[3].bits.uop.prs1_busy \n connect slots_13.io.wakeup_ports[3].bits.uop.ppred, issue_slots[13].wakeup_ports[3].bits.uop.ppred \n connect slots_13.io.wakeup_ports[3].bits.uop.prs3, issue_slots[13].wakeup_ports[3].bits.uop.prs3 \n connect slots_13.io.wakeup_ports[3].bits.uop.prs2, issue_slots[13].wakeup_ports[3].bits.uop.prs2 \n connect slots_13.io.wakeup_ports[3].bits.uop.prs1, issue_slots[13].wakeup_ports[3].bits.uop.prs1 \n connect slots_13.io.wakeup_ports[3].bits.uop.pdst, issue_slots[13].wakeup_ports[3].bits.uop.pdst \n connect slots_13.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[13].wakeup_ports[3].bits.uop.rxq_idx \n connect slots_13.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[13].wakeup_ports[3].bits.uop.stq_idx \n connect slots_13.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[13].wakeup_ports[3].bits.uop.ldq_idx \n connect slots_13.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[13].wakeup_ports[3].bits.uop.rob_idx \n connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.vec \n connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.wflags \n connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.sqrt \n connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.div \n connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.fma \n connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe \n connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.toint \n connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.fromint \n connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut \n connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn \n connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.swap23 \n connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.swap12 \n connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.ren3 \n connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.ren2 \n connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.ren1 \n connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.wen \n connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.ldst \n connect slots_13.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[13].wakeup_ports[3].bits.uop.op2_sel \n connect slots_13.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[13].wakeup_ports[3].bits.uop.op1_sel \n connect slots_13.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[13].wakeup_ports[3].bits.uop.imm_packed \n connect slots_13.io.wakeup_ports[3].bits.uop.pimm, issue_slots[13].wakeup_ports[3].bits.uop.pimm \n connect slots_13.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[13].wakeup_ports[3].bits.uop.imm_sel \n connect slots_13.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[13].wakeup_ports[3].bits.uop.imm_rename \n connect slots_13.io.wakeup_ports[3].bits.uop.taken, issue_slots[13].wakeup_ports[3].bits.uop.taken \n connect slots_13.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[13].wakeup_ports[3].bits.uop.pc_lob \n connect slots_13.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[13].wakeup_ports[3].bits.uop.edge_inst \n connect slots_13.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[13].wakeup_ports[3].bits.uop.ftq_idx \n connect slots_13.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[13].wakeup_ports[3].bits.uop.is_mov \n connect slots_13.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[13].wakeup_ports[3].bits.uop.is_rocc \n connect slots_13.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[13].wakeup_ports[3].bits.uop.is_sys_pc2epc \n connect slots_13.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[13].wakeup_ports[3].bits.uop.is_eret \n connect slots_13.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[13].wakeup_ports[3].bits.uop.is_amo \n connect slots_13.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[13].wakeup_ports[3].bits.uop.is_sfence \n connect slots_13.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[13].wakeup_ports[3].bits.uop.is_fencei \n connect slots_13.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[13].wakeup_ports[3].bits.uop.is_fence \n connect slots_13.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[13].wakeup_ports[3].bits.uop.is_sfb \n connect slots_13.io.wakeup_ports[3].bits.uop.br_type, issue_slots[13].wakeup_ports[3].bits.uop.br_type \n connect slots_13.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[13].wakeup_ports[3].bits.uop.br_tag \n connect slots_13.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[13].wakeup_ports[3].bits.uop.br_mask \n connect slots_13.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[13].wakeup_ports[3].bits.uop.dis_col_sel \n connect slots_13.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[13].wakeup_ports[3].bits.uop.iw_p3_bypass_hint \n connect slots_13.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[13].wakeup_ports[3].bits.uop.iw_p2_bypass_hint \n connect slots_13.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[13].wakeup_ports[3].bits.uop.iw_p1_bypass_hint \n connect slots_13.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[13].wakeup_ports[3].bits.uop.iw_p2_speculative_child \n connect slots_13.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[13].wakeup_ports[3].bits.uop.iw_p1_speculative_child \n connect slots_13.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[13].wakeup_ports[3].bits.uop.iw_issued_partial_dgen \n connect slots_13.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[13].wakeup_ports[3].bits.uop.iw_issued_partial_agen \n connect slots_13.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[13].wakeup_ports[3].bits.uop.iw_issued \n connect slots_13.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[13].wakeup_ports[3].bits.uop.fu_code[0] \n connect slots_13.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[13].wakeup_ports[3].bits.uop.fu_code[1] \n connect slots_13.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[13].wakeup_ports[3].bits.uop.fu_code[2] \n connect slots_13.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[13].wakeup_ports[3].bits.uop.fu_code[3] \n connect slots_13.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[13].wakeup_ports[3].bits.uop.fu_code[4] \n connect slots_13.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[13].wakeup_ports[3].bits.uop.fu_code[5] \n connect slots_13.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[13].wakeup_ports[3].bits.uop.fu_code[6] \n connect slots_13.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[13].wakeup_ports[3].bits.uop.fu_code[7] \n connect slots_13.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[13].wakeup_ports[3].bits.uop.fu_code[8] \n connect slots_13.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[13].wakeup_ports[3].bits.uop.fu_code[9] \n connect slots_13.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[13].wakeup_ports[3].bits.uop.iq_type[0] \n connect slots_13.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[13].wakeup_ports[3].bits.uop.iq_type[1] \n connect slots_13.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[13].wakeup_ports[3].bits.uop.iq_type[2] \n connect slots_13.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[13].wakeup_ports[3].bits.uop.iq_type[3] \n connect slots_13.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[13].wakeup_ports[3].bits.uop.debug_pc \n connect slots_13.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[13].wakeup_ports[3].bits.uop.is_rvc \n connect slots_13.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[13].wakeup_ports[3].bits.uop.debug_inst \n connect slots_13.io.wakeup_ports[3].bits.uop.inst, issue_slots[13].wakeup_ports[3].bits.uop.inst \n connect slots_13.io.wakeup_ports[3].valid, issue_slots[13].wakeup_ports[3].valid \n connect slots_13.io.squash_grant, issue_slots[13].squash_grant \n connect slots_13.io.clear, issue_slots[13].clear \n connect slots_13.io.kill, issue_slots[13].kill \n connect slots_13.io.brupdate.b2.target_offset, issue_slots[13].brupdate.b2.target_offset \n connect slots_13.io.brupdate.b2.jalr_target, issue_slots[13].brupdate.b2.jalr_target \n connect slots_13.io.brupdate.b2.pc_sel, issue_slots[13].brupdate.b2.pc_sel \n connect slots_13.io.brupdate.b2.cfi_type, issue_slots[13].brupdate.b2.cfi_type \n connect slots_13.io.brupdate.b2.taken, issue_slots[13].brupdate.b2.taken \n connect slots_13.io.brupdate.b2.mispredict, issue_slots[13].brupdate.b2.mispredict \n connect slots_13.io.brupdate.b2.uop.debug_tsrc, issue_slots[13].brupdate.b2.uop.debug_tsrc \n connect slots_13.io.brupdate.b2.uop.debug_fsrc, issue_slots[13].brupdate.b2.uop.debug_fsrc \n connect slots_13.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[13].brupdate.b2.uop.bp_xcpt_if \n connect slots_13.io.brupdate.b2.uop.bp_debug_if, issue_slots[13].brupdate.b2.uop.bp_debug_if \n connect slots_13.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[13].brupdate.b2.uop.xcpt_ma_if \n connect slots_13.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[13].brupdate.b2.uop.xcpt_ae_if \n connect slots_13.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[13].brupdate.b2.uop.xcpt_pf_if \n connect slots_13.io.brupdate.b2.uop.fp_typ, issue_slots[13].brupdate.b2.uop.fp_typ \n connect slots_13.io.brupdate.b2.uop.fp_rm, issue_slots[13].brupdate.b2.uop.fp_rm \n connect slots_13.io.brupdate.b2.uop.fp_val, issue_slots[13].brupdate.b2.uop.fp_val \n connect slots_13.io.brupdate.b2.uop.fcn_op, issue_slots[13].brupdate.b2.uop.fcn_op \n connect slots_13.io.brupdate.b2.uop.fcn_dw, issue_slots[13].brupdate.b2.uop.fcn_dw \n connect slots_13.io.brupdate.b2.uop.frs3_en, issue_slots[13].brupdate.b2.uop.frs3_en \n connect slots_13.io.brupdate.b2.uop.lrs2_rtype, issue_slots[13].brupdate.b2.uop.lrs2_rtype \n connect slots_13.io.brupdate.b2.uop.lrs1_rtype, issue_slots[13].brupdate.b2.uop.lrs1_rtype \n connect slots_13.io.brupdate.b2.uop.dst_rtype, issue_slots[13].brupdate.b2.uop.dst_rtype \n connect slots_13.io.brupdate.b2.uop.lrs3, issue_slots[13].brupdate.b2.uop.lrs3 \n connect slots_13.io.brupdate.b2.uop.lrs2, issue_slots[13].brupdate.b2.uop.lrs2 \n connect slots_13.io.brupdate.b2.uop.lrs1, issue_slots[13].brupdate.b2.uop.lrs1 \n connect slots_13.io.brupdate.b2.uop.ldst, issue_slots[13].brupdate.b2.uop.ldst \n connect slots_13.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[13].brupdate.b2.uop.ldst_is_rs1 \n connect slots_13.io.brupdate.b2.uop.csr_cmd, issue_slots[13].brupdate.b2.uop.csr_cmd \n connect slots_13.io.brupdate.b2.uop.flush_on_commit, issue_slots[13].brupdate.b2.uop.flush_on_commit \n connect slots_13.io.brupdate.b2.uop.is_unique, issue_slots[13].brupdate.b2.uop.is_unique \n connect slots_13.io.brupdate.b2.uop.uses_stq, issue_slots[13].brupdate.b2.uop.uses_stq \n connect slots_13.io.brupdate.b2.uop.uses_ldq, issue_slots[13].brupdate.b2.uop.uses_ldq \n connect slots_13.io.brupdate.b2.uop.mem_signed, issue_slots[13].brupdate.b2.uop.mem_signed \n connect slots_13.io.brupdate.b2.uop.mem_size, issue_slots[13].brupdate.b2.uop.mem_size \n connect slots_13.io.brupdate.b2.uop.mem_cmd, issue_slots[13].brupdate.b2.uop.mem_cmd \n connect slots_13.io.brupdate.b2.uop.exc_cause, issue_slots[13].brupdate.b2.uop.exc_cause \n connect slots_13.io.brupdate.b2.uop.exception, issue_slots[13].brupdate.b2.uop.exception \n connect slots_13.io.brupdate.b2.uop.stale_pdst, issue_slots[13].brupdate.b2.uop.stale_pdst \n connect slots_13.io.brupdate.b2.uop.ppred_busy, issue_slots[13].brupdate.b2.uop.ppred_busy \n connect slots_13.io.brupdate.b2.uop.prs3_busy, issue_slots[13].brupdate.b2.uop.prs3_busy \n connect slots_13.io.brupdate.b2.uop.prs2_busy, issue_slots[13].brupdate.b2.uop.prs2_busy \n connect slots_13.io.brupdate.b2.uop.prs1_busy, issue_slots[13].brupdate.b2.uop.prs1_busy \n connect slots_13.io.brupdate.b2.uop.ppred, issue_slots[13].brupdate.b2.uop.ppred \n connect slots_13.io.brupdate.b2.uop.prs3, issue_slots[13].brupdate.b2.uop.prs3 \n connect slots_13.io.brupdate.b2.uop.prs2, issue_slots[13].brupdate.b2.uop.prs2 \n connect slots_13.io.brupdate.b2.uop.prs1, issue_slots[13].brupdate.b2.uop.prs1 \n connect slots_13.io.brupdate.b2.uop.pdst, issue_slots[13].brupdate.b2.uop.pdst \n connect slots_13.io.brupdate.b2.uop.rxq_idx, issue_slots[13].brupdate.b2.uop.rxq_idx \n connect slots_13.io.brupdate.b2.uop.stq_idx, issue_slots[13].brupdate.b2.uop.stq_idx \n connect slots_13.io.brupdate.b2.uop.ldq_idx, issue_slots[13].brupdate.b2.uop.ldq_idx \n connect slots_13.io.brupdate.b2.uop.rob_idx, issue_slots[13].brupdate.b2.uop.rob_idx \n connect slots_13.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[13].brupdate.b2.uop.fp_ctrl.vec \n connect slots_13.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[13].brupdate.b2.uop.fp_ctrl.wflags \n connect slots_13.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[13].brupdate.b2.uop.fp_ctrl.sqrt \n connect slots_13.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[13].brupdate.b2.uop.fp_ctrl.div \n connect slots_13.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[13].brupdate.b2.uop.fp_ctrl.fma \n connect slots_13.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[13].brupdate.b2.uop.fp_ctrl.fastpipe \n connect slots_13.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[13].brupdate.b2.uop.fp_ctrl.toint \n connect slots_13.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[13].brupdate.b2.uop.fp_ctrl.fromint \n connect slots_13.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[13].brupdate.b2.uop.fp_ctrl.typeTagOut \n connect slots_13.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[13].brupdate.b2.uop.fp_ctrl.typeTagIn \n connect slots_13.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[13].brupdate.b2.uop.fp_ctrl.swap23 \n connect slots_13.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[13].brupdate.b2.uop.fp_ctrl.swap12 \n connect slots_13.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[13].brupdate.b2.uop.fp_ctrl.ren3 \n connect slots_13.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[13].brupdate.b2.uop.fp_ctrl.ren2 \n connect slots_13.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[13].brupdate.b2.uop.fp_ctrl.ren1 \n connect slots_13.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[13].brupdate.b2.uop.fp_ctrl.wen \n connect slots_13.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[13].brupdate.b2.uop.fp_ctrl.ldst \n connect slots_13.io.brupdate.b2.uop.op2_sel, issue_slots[13].brupdate.b2.uop.op2_sel \n connect slots_13.io.brupdate.b2.uop.op1_sel, issue_slots[13].brupdate.b2.uop.op1_sel \n connect slots_13.io.brupdate.b2.uop.imm_packed, issue_slots[13].brupdate.b2.uop.imm_packed \n connect slots_13.io.brupdate.b2.uop.pimm, issue_slots[13].brupdate.b2.uop.pimm \n connect slots_13.io.brupdate.b2.uop.imm_sel, issue_slots[13].brupdate.b2.uop.imm_sel \n connect slots_13.io.brupdate.b2.uop.imm_rename, issue_slots[13].brupdate.b2.uop.imm_rename \n connect slots_13.io.brupdate.b2.uop.taken, issue_slots[13].brupdate.b2.uop.taken \n connect slots_13.io.brupdate.b2.uop.pc_lob, issue_slots[13].brupdate.b2.uop.pc_lob \n connect slots_13.io.brupdate.b2.uop.edge_inst, issue_slots[13].brupdate.b2.uop.edge_inst \n connect slots_13.io.brupdate.b2.uop.ftq_idx, issue_slots[13].brupdate.b2.uop.ftq_idx \n connect slots_13.io.brupdate.b2.uop.is_mov, issue_slots[13].brupdate.b2.uop.is_mov \n connect slots_13.io.brupdate.b2.uop.is_rocc, issue_slots[13].brupdate.b2.uop.is_rocc \n connect slots_13.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[13].brupdate.b2.uop.is_sys_pc2epc \n connect slots_13.io.brupdate.b2.uop.is_eret, issue_slots[13].brupdate.b2.uop.is_eret \n connect slots_13.io.brupdate.b2.uop.is_amo, issue_slots[13].brupdate.b2.uop.is_amo \n connect slots_13.io.brupdate.b2.uop.is_sfence, issue_slots[13].brupdate.b2.uop.is_sfence \n connect slots_13.io.brupdate.b2.uop.is_fencei, issue_slots[13].brupdate.b2.uop.is_fencei \n connect slots_13.io.brupdate.b2.uop.is_fence, issue_slots[13].brupdate.b2.uop.is_fence \n connect slots_13.io.brupdate.b2.uop.is_sfb, issue_slots[13].brupdate.b2.uop.is_sfb \n connect slots_13.io.brupdate.b2.uop.br_type, issue_slots[13].brupdate.b2.uop.br_type \n connect slots_13.io.brupdate.b2.uop.br_tag, issue_slots[13].brupdate.b2.uop.br_tag \n connect slots_13.io.brupdate.b2.uop.br_mask, issue_slots[13].brupdate.b2.uop.br_mask \n connect slots_13.io.brupdate.b2.uop.dis_col_sel, issue_slots[13].brupdate.b2.uop.dis_col_sel \n connect slots_13.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[13].brupdate.b2.uop.iw_p3_bypass_hint \n connect slots_13.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[13].brupdate.b2.uop.iw_p2_bypass_hint \n connect slots_13.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[13].brupdate.b2.uop.iw_p1_bypass_hint \n connect slots_13.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[13].brupdate.b2.uop.iw_p2_speculative_child \n connect slots_13.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[13].brupdate.b2.uop.iw_p1_speculative_child \n connect slots_13.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[13].brupdate.b2.uop.iw_issued_partial_dgen \n connect slots_13.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[13].brupdate.b2.uop.iw_issued_partial_agen \n connect slots_13.io.brupdate.b2.uop.iw_issued, issue_slots[13].brupdate.b2.uop.iw_issued \n connect slots_13.io.brupdate.b2.uop.fu_code[0], issue_slots[13].brupdate.b2.uop.fu_code[0] \n connect slots_13.io.brupdate.b2.uop.fu_code[1], issue_slots[13].brupdate.b2.uop.fu_code[1] \n connect slots_13.io.brupdate.b2.uop.fu_code[2], issue_slots[13].brupdate.b2.uop.fu_code[2] \n connect slots_13.io.brupdate.b2.uop.fu_code[3], issue_slots[13].brupdate.b2.uop.fu_code[3] \n connect slots_13.io.brupdate.b2.uop.fu_code[4], issue_slots[13].brupdate.b2.uop.fu_code[4] \n connect slots_13.io.brupdate.b2.uop.fu_code[5], issue_slots[13].brupdate.b2.uop.fu_code[5] \n connect slots_13.io.brupdate.b2.uop.fu_code[6], issue_slots[13].brupdate.b2.uop.fu_code[6] \n connect slots_13.io.brupdate.b2.uop.fu_code[7], issue_slots[13].brupdate.b2.uop.fu_code[7] \n connect slots_13.io.brupdate.b2.uop.fu_code[8], issue_slots[13].brupdate.b2.uop.fu_code[8] \n connect slots_13.io.brupdate.b2.uop.fu_code[9], issue_slots[13].brupdate.b2.uop.fu_code[9] \n connect slots_13.io.brupdate.b2.uop.iq_type[0], issue_slots[13].brupdate.b2.uop.iq_type[0] \n connect slots_13.io.brupdate.b2.uop.iq_type[1], issue_slots[13].brupdate.b2.uop.iq_type[1] \n connect slots_13.io.brupdate.b2.uop.iq_type[2], issue_slots[13].brupdate.b2.uop.iq_type[2] \n connect slots_13.io.brupdate.b2.uop.iq_type[3], issue_slots[13].brupdate.b2.uop.iq_type[3] \n connect slots_13.io.brupdate.b2.uop.debug_pc, issue_slots[13].brupdate.b2.uop.debug_pc \n connect slots_13.io.brupdate.b2.uop.is_rvc, issue_slots[13].brupdate.b2.uop.is_rvc \n connect slots_13.io.brupdate.b2.uop.debug_inst, issue_slots[13].brupdate.b2.uop.debug_inst \n connect slots_13.io.brupdate.b2.uop.inst, issue_slots[13].brupdate.b2.uop.inst \n connect slots_13.io.brupdate.b1.mispredict_mask, issue_slots[13].brupdate.b1.mispredict_mask \n connect slots_13.io.brupdate.b1.resolve_mask, issue_slots[13].brupdate.b1.resolve_mask \n connect issue_slots[13].out_uop.debug_tsrc, slots_13.io.out_uop.debug_tsrc \n connect issue_slots[13].out_uop.debug_fsrc, slots_13.io.out_uop.debug_fsrc \n connect issue_slots[13].out_uop.bp_xcpt_if, slots_13.io.out_uop.bp_xcpt_if \n connect issue_slots[13].out_uop.bp_debug_if, slots_13.io.out_uop.bp_debug_if \n connect issue_slots[13].out_uop.xcpt_ma_if, slots_13.io.out_uop.xcpt_ma_if \n connect issue_slots[13].out_uop.xcpt_ae_if, slots_13.io.out_uop.xcpt_ae_if \n connect issue_slots[13].out_uop.xcpt_pf_if, slots_13.io.out_uop.xcpt_pf_if \n connect issue_slots[13].out_uop.fp_typ, slots_13.io.out_uop.fp_typ \n connect issue_slots[13].out_uop.fp_rm, slots_13.io.out_uop.fp_rm \n connect issue_slots[13].out_uop.fp_val, slots_13.io.out_uop.fp_val \n connect issue_slots[13].out_uop.fcn_op, slots_13.io.out_uop.fcn_op \n connect issue_slots[13].out_uop.fcn_dw, slots_13.io.out_uop.fcn_dw \n connect issue_slots[13].out_uop.frs3_en, slots_13.io.out_uop.frs3_en \n connect issue_slots[13].out_uop.lrs2_rtype, slots_13.io.out_uop.lrs2_rtype \n connect issue_slots[13].out_uop.lrs1_rtype, slots_13.io.out_uop.lrs1_rtype \n connect issue_slots[13].out_uop.dst_rtype, slots_13.io.out_uop.dst_rtype \n connect issue_slots[13].out_uop.lrs3, slots_13.io.out_uop.lrs3 \n connect issue_slots[13].out_uop.lrs2, slots_13.io.out_uop.lrs2 \n connect issue_slots[13].out_uop.lrs1, slots_13.io.out_uop.lrs1 \n connect issue_slots[13].out_uop.ldst, slots_13.io.out_uop.ldst \n connect issue_slots[13].out_uop.ldst_is_rs1, slots_13.io.out_uop.ldst_is_rs1 \n connect issue_slots[13].out_uop.csr_cmd, slots_13.io.out_uop.csr_cmd \n connect issue_slots[13].out_uop.flush_on_commit, slots_13.io.out_uop.flush_on_commit \n connect issue_slots[13].out_uop.is_unique, slots_13.io.out_uop.is_unique \n connect issue_slots[13].out_uop.uses_stq, slots_13.io.out_uop.uses_stq \n connect issue_slots[13].out_uop.uses_ldq, slots_13.io.out_uop.uses_ldq \n connect issue_slots[13].out_uop.mem_signed, slots_13.io.out_uop.mem_signed \n connect issue_slots[13].out_uop.mem_size, slots_13.io.out_uop.mem_size \n connect issue_slots[13].out_uop.mem_cmd, slots_13.io.out_uop.mem_cmd \n connect issue_slots[13].out_uop.exc_cause, slots_13.io.out_uop.exc_cause \n connect issue_slots[13].out_uop.exception, slots_13.io.out_uop.exception \n connect issue_slots[13].out_uop.stale_pdst, slots_13.io.out_uop.stale_pdst \n connect issue_slots[13].out_uop.ppred_busy, slots_13.io.out_uop.ppred_busy \n connect issue_slots[13].out_uop.prs3_busy, slots_13.io.out_uop.prs3_busy \n connect issue_slots[13].out_uop.prs2_busy, slots_13.io.out_uop.prs2_busy \n connect issue_slots[13].out_uop.prs1_busy, slots_13.io.out_uop.prs1_busy \n connect issue_slots[13].out_uop.ppred, slots_13.io.out_uop.ppred \n connect issue_slots[13].out_uop.prs3, slots_13.io.out_uop.prs3 \n connect issue_slots[13].out_uop.prs2, slots_13.io.out_uop.prs2 \n connect issue_slots[13].out_uop.prs1, slots_13.io.out_uop.prs1 \n connect issue_slots[13].out_uop.pdst, slots_13.io.out_uop.pdst \n connect issue_slots[13].out_uop.rxq_idx, slots_13.io.out_uop.rxq_idx \n connect issue_slots[13].out_uop.stq_idx, slots_13.io.out_uop.stq_idx \n connect issue_slots[13].out_uop.ldq_idx, slots_13.io.out_uop.ldq_idx \n connect issue_slots[13].out_uop.rob_idx, slots_13.io.out_uop.rob_idx \n connect issue_slots[13].out_uop.fp_ctrl.vec, slots_13.io.out_uop.fp_ctrl.vec \n connect issue_slots[13].out_uop.fp_ctrl.wflags, slots_13.io.out_uop.fp_ctrl.wflags \n connect issue_slots[13].out_uop.fp_ctrl.sqrt, slots_13.io.out_uop.fp_ctrl.sqrt \n connect issue_slots[13].out_uop.fp_ctrl.div, slots_13.io.out_uop.fp_ctrl.div \n connect issue_slots[13].out_uop.fp_ctrl.fma, slots_13.io.out_uop.fp_ctrl.fma \n connect issue_slots[13].out_uop.fp_ctrl.fastpipe, slots_13.io.out_uop.fp_ctrl.fastpipe \n connect issue_slots[13].out_uop.fp_ctrl.toint, slots_13.io.out_uop.fp_ctrl.toint \n connect issue_slots[13].out_uop.fp_ctrl.fromint, slots_13.io.out_uop.fp_ctrl.fromint \n connect issue_slots[13].out_uop.fp_ctrl.typeTagOut, slots_13.io.out_uop.fp_ctrl.typeTagOut \n connect issue_slots[13].out_uop.fp_ctrl.typeTagIn, slots_13.io.out_uop.fp_ctrl.typeTagIn \n connect issue_slots[13].out_uop.fp_ctrl.swap23, slots_13.io.out_uop.fp_ctrl.swap23 \n connect issue_slots[13].out_uop.fp_ctrl.swap12, slots_13.io.out_uop.fp_ctrl.swap12 \n connect issue_slots[13].out_uop.fp_ctrl.ren3, slots_13.io.out_uop.fp_ctrl.ren3 \n connect issue_slots[13].out_uop.fp_ctrl.ren2, slots_13.io.out_uop.fp_ctrl.ren2 \n connect issue_slots[13].out_uop.fp_ctrl.ren1, slots_13.io.out_uop.fp_ctrl.ren1 \n connect issue_slots[13].out_uop.fp_ctrl.wen, slots_13.io.out_uop.fp_ctrl.wen \n connect issue_slots[13].out_uop.fp_ctrl.ldst, slots_13.io.out_uop.fp_ctrl.ldst \n connect issue_slots[13].out_uop.op2_sel, slots_13.io.out_uop.op2_sel \n connect issue_slots[13].out_uop.op1_sel, slots_13.io.out_uop.op1_sel \n connect issue_slots[13].out_uop.imm_packed, slots_13.io.out_uop.imm_packed \n connect issue_slots[13].out_uop.pimm, slots_13.io.out_uop.pimm \n connect issue_slots[13].out_uop.imm_sel, slots_13.io.out_uop.imm_sel \n connect issue_slots[13].out_uop.imm_rename, slots_13.io.out_uop.imm_rename \n connect issue_slots[13].out_uop.taken, slots_13.io.out_uop.taken \n connect issue_slots[13].out_uop.pc_lob, slots_13.io.out_uop.pc_lob \n connect issue_slots[13].out_uop.edge_inst, slots_13.io.out_uop.edge_inst \n connect issue_slots[13].out_uop.ftq_idx, slots_13.io.out_uop.ftq_idx \n connect issue_slots[13].out_uop.is_mov, slots_13.io.out_uop.is_mov \n connect issue_slots[13].out_uop.is_rocc, slots_13.io.out_uop.is_rocc \n connect issue_slots[13].out_uop.is_sys_pc2epc, slots_13.io.out_uop.is_sys_pc2epc \n connect issue_slots[13].out_uop.is_eret, slots_13.io.out_uop.is_eret \n connect issue_slots[13].out_uop.is_amo, slots_13.io.out_uop.is_amo \n connect issue_slots[13].out_uop.is_sfence, slots_13.io.out_uop.is_sfence \n connect issue_slots[13].out_uop.is_fencei, slots_13.io.out_uop.is_fencei \n connect issue_slots[13].out_uop.is_fence, slots_13.io.out_uop.is_fence \n connect issue_slots[13].out_uop.is_sfb, slots_13.io.out_uop.is_sfb \n connect issue_slots[13].out_uop.br_type, slots_13.io.out_uop.br_type \n connect issue_slots[13].out_uop.br_tag, slots_13.io.out_uop.br_tag \n connect issue_slots[13].out_uop.br_mask, slots_13.io.out_uop.br_mask \n connect issue_slots[13].out_uop.dis_col_sel, slots_13.io.out_uop.dis_col_sel \n connect issue_slots[13].out_uop.iw_p3_bypass_hint, slots_13.io.out_uop.iw_p3_bypass_hint \n connect issue_slots[13].out_uop.iw_p2_bypass_hint, slots_13.io.out_uop.iw_p2_bypass_hint \n connect issue_slots[13].out_uop.iw_p1_bypass_hint, slots_13.io.out_uop.iw_p1_bypass_hint \n connect issue_slots[13].out_uop.iw_p2_speculative_child, slots_13.io.out_uop.iw_p2_speculative_child \n connect issue_slots[13].out_uop.iw_p1_speculative_child, slots_13.io.out_uop.iw_p1_speculative_child \n connect issue_slots[13].out_uop.iw_issued_partial_dgen, slots_13.io.out_uop.iw_issued_partial_dgen \n connect issue_slots[13].out_uop.iw_issued_partial_agen, slots_13.io.out_uop.iw_issued_partial_agen \n connect issue_slots[13].out_uop.iw_issued, slots_13.io.out_uop.iw_issued \n connect issue_slots[13].out_uop.fu_code[0], slots_13.io.out_uop.fu_code[0] \n connect issue_slots[13].out_uop.fu_code[1], slots_13.io.out_uop.fu_code[1] \n connect issue_slots[13].out_uop.fu_code[2], slots_13.io.out_uop.fu_code[2] \n connect issue_slots[13].out_uop.fu_code[3], slots_13.io.out_uop.fu_code[3] \n connect issue_slots[13].out_uop.fu_code[4], slots_13.io.out_uop.fu_code[4] \n connect issue_slots[13].out_uop.fu_code[5], slots_13.io.out_uop.fu_code[5] \n connect issue_slots[13].out_uop.fu_code[6], slots_13.io.out_uop.fu_code[6] \n connect issue_slots[13].out_uop.fu_code[7], slots_13.io.out_uop.fu_code[7] \n connect issue_slots[13].out_uop.fu_code[8], slots_13.io.out_uop.fu_code[8] \n connect issue_slots[13].out_uop.fu_code[9], slots_13.io.out_uop.fu_code[9] \n connect issue_slots[13].out_uop.iq_type[0], slots_13.io.out_uop.iq_type[0] \n connect issue_slots[13].out_uop.iq_type[1], slots_13.io.out_uop.iq_type[1] \n connect issue_slots[13].out_uop.iq_type[2], slots_13.io.out_uop.iq_type[2] \n connect issue_slots[13].out_uop.iq_type[3], slots_13.io.out_uop.iq_type[3] \n connect issue_slots[13].out_uop.debug_pc, slots_13.io.out_uop.debug_pc \n connect issue_slots[13].out_uop.is_rvc, slots_13.io.out_uop.is_rvc \n connect issue_slots[13].out_uop.debug_inst, slots_13.io.out_uop.debug_inst \n connect issue_slots[13].out_uop.inst, slots_13.io.out_uop.inst \n connect slots_13.io.in_uop.bits.debug_tsrc, issue_slots[13].in_uop.bits.debug_tsrc \n connect slots_13.io.in_uop.bits.debug_fsrc, issue_slots[13].in_uop.bits.debug_fsrc \n connect slots_13.io.in_uop.bits.bp_xcpt_if, issue_slots[13].in_uop.bits.bp_xcpt_if \n connect slots_13.io.in_uop.bits.bp_debug_if, issue_slots[13].in_uop.bits.bp_debug_if \n connect slots_13.io.in_uop.bits.xcpt_ma_if, issue_slots[13].in_uop.bits.xcpt_ma_if \n connect slots_13.io.in_uop.bits.xcpt_ae_if, issue_slots[13].in_uop.bits.xcpt_ae_if \n connect slots_13.io.in_uop.bits.xcpt_pf_if, issue_slots[13].in_uop.bits.xcpt_pf_if \n connect slots_13.io.in_uop.bits.fp_typ, issue_slots[13].in_uop.bits.fp_typ \n connect slots_13.io.in_uop.bits.fp_rm, issue_slots[13].in_uop.bits.fp_rm \n connect slots_13.io.in_uop.bits.fp_val, issue_slots[13].in_uop.bits.fp_val \n connect slots_13.io.in_uop.bits.fcn_op, issue_slots[13].in_uop.bits.fcn_op \n connect slots_13.io.in_uop.bits.fcn_dw, issue_slots[13].in_uop.bits.fcn_dw \n connect slots_13.io.in_uop.bits.frs3_en, issue_slots[13].in_uop.bits.frs3_en \n connect slots_13.io.in_uop.bits.lrs2_rtype, issue_slots[13].in_uop.bits.lrs2_rtype \n connect slots_13.io.in_uop.bits.lrs1_rtype, issue_slots[13].in_uop.bits.lrs1_rtype \n connect slots_13.io.in_uop.bits.dst_rtype, issue_slots[13].in_uop.bits.dst_rtype \n connect slots_13.io.in_uop.bits.lrs3, issue_slots[13].in_uop.bits.lrs3 \n connect slots_13.io.in_uop.bits.lrs2, issue_slots[13].in_uop.bits.lrs2 \n connect slots_13.io.in_uop.bits.lrs1, issue_slots[13].in_uop.bits.lrs1 \n connect slots_13.io.in_uop.bits.ldst, issue_slots[13].in_uop.bits.ldst \n connect slots_13.io.in_uop.bits.ldst_is_rs1, issue_slots[13].in_uop.bits.ldst_is_rs1 \n connect slots_13.io.in_uop.bits.csr_cmd, issue_slots[13].in_uop.bits.csr_cmd \n connect slots_13.io.in_uop.bits.flush_on_commit, issue_slots[13].in_uop.bits.flush_on_commit \n connect slots_13.io.in_uop.bits.is_unique, issue_slots[13].in_uop.bits.is_unique \n connect slots_13.io.in_uop.bits.uses_stq, issue_slots[13].in_uop.bits.uses_stq \n connect slots_13.io.in_uop.bits.uses_ldq, issue_slots[13].in_uop.bits.uses_ldq \n connect slots_13.io.in_uop.bits.mem_signed, issue_slots[13].in_uop.bits.mem_signed \n connect slots_13.io.in_uop.bits.mem_size, issue_slots[13].in_uop.bits.mem_size \n connect slots_13.io.in_uop.bits.mem_cmd, issue_slots[13].in_uop.bits.mem_cmd \n connect slots_13.io.in_uop.bits.exc_cause, issue_slots[13].in_uop.bits.exc_cause \n connect slots_13.io.in_uop.bits.exception, issue_slots[13].in_uop.bits.exception \n connect slots_13.io.in_uop.bits.stale_pdst, issue_slots[13].in_uop.bits.stale_pdst \n connect slots_13.io.in_uop.bits.ppred_busy, issue_slots[13].in_uop.bits.ppred_busy \n connect slots_13.io.in_uop.bits.prs3_busy, issue_slots[13].in_uop.bits.prs3_busy \n connect slots_13.io.in_uop.bits.prs2_busy, issue_slots[13].in_uop.bits.prs2_busy \n connect slots_13.io.in_uop.bits.prs1_busy, issue_slots[13].in_uop.bits.prs1_busy \n connect slots_13.io.in_uop.bits.ppred, issue_slots[13].in_uop.bits.ppred \n connect slots_13.io.in_uop.bits.prs3, issue_slots[13].in_uop.bits.prs3 \n connect slots_13.io.in_uop.bits.prs2, issue_slots[13].in_uop.bits.prs2 \n connect slots_13.io.in_uop.bits.prs1, issue_slots[13].in_uop.bits.prs1 \n connect slots_13.io.in_uop.bits.pdst, issue_slots[13].in_uop.bits.pdst \n connect slots_13.io.in_uop.bits.rxq_idx, issue_slots[13].in_uop.bits.rxq_idx \n connect slots_13.io.in_uop.bits.stq_idx, issue_slots[13].in_uop.bits.stq_idx \n connect slots_13.io.in_uop.bits.ldq_idx, issue_slots[13].in_uop.bits.ldq_idx \n connect slots_13.io.in_uop.bits.rob_idx, issue_slots[13].in_uop.bits.rob_idx \n connect slots_13.io.in_uop.bits.fp_ctrl.vec, issue_slots[13].in_uop.bits.fp_ctrl.vec \n connect slots_13.io.in_uop.bits.fp_ctrl.wflags, issue_slots[13].in_uop.bits.fp_ctrl.wflags \n connect slots_13.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[13].in_uop.bits.fp_ctrl.sqrt \n connect slots_13.io.in_uop.bits.fp_ctrl.div, issue_slots[13].in_uop.bits.fp_ctrl.div \n connect slots_13.io.in_uop.bits.fp_ctrl.fma, issue_slots[13].in_uop.bits.fp_ctrl.fma \n connect slots_13.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[13].in_uop.bits.fp_ctrl.fastpipe \n connect slots_13.io.in_uop.bits.fp_ctrl.toint, issue_slots[13].in_uop.bits.fp_ctrl.toint \n connect slots_13.io.in_uop.bits.fp_ctrl.fromint, issue_slots[13].in_uop.bits.fp_ctrl.fromint \n connect slots_13.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[13].in_uop.bits.fp_ctrl.typeTagOut \n connect slots_13.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[13].in_uop.bits.fp_ctrl.typeTagIn \n connect slots_13.io.in_uop.bits.fp_ctrl.swap23, issue_slots[13].in_uop.bits.fp_ctrl.swap23 \n connect slots_13.io.in_uop.bits.fp_ctrl.swap12, issue_slots[13].in_uop.bits.fp_ctrl.swap12 \n connect slots_13.io.in_uop.bits.fp_ctrl.ren3, issue_slots[13].in_uop.bits.fp_ctrl.ren3 \n connect slots_13.io.in_uop.bits.fp_ctrl.ren2, issue_slots[13].in_uop.bits.fp_ctrl.ren2 \n connect slots_13.io.in_uop.bits.fp_ctrl.ren1, issue_slots[13].in_uop.bits.fp_ctrl.ren1 \n connect slots_13.io.in_uop.bits.fp_ctrl.wen, issue_slots[13].in_uop.bits.fp_ctrl.wen \n connect slots_13.io.in_uop.bits.fp_ctrl.ldst, issue_slots[13].in_uop.bits.fp_ctrl.ldst \n connect slots_13.io.in_uop.bits.op2_sel, issue_slots[13].in_uop.bits.op2_sel \n connect slots_13.io.in_uop.bits.op1_sel, issue_slots[13].in_uop.bits.op1_sel \n connect slots_13.io.in_uop.bits.imm_packed, issue_slots[13].in_uop.bits.imm_packed \n connect slots_13.io.in_uop.bits.pimm, issue_slots[13].in_uop.bits.pimm \n connect slots_13.io.in_uop.bits.imm_sel, issue_slots[13].in_uop.bits.imm_sel \n connect slots_13.io.in_uop.bits.imm_rename, issue_slots[13].in_uop.bits.imm_rename \n connect slots_13.io.in_uop.bits.taken, issue_slots[13].in_uop.bits.taken \n connect slots_13.io.in_uop.bits.pc_lob, issue_slots[13].in_uop.bits.pc_lob \n connect slots_13.io.in_uop.bits.edge_inst, issue_slots[13].in_uop.bits.edge_inst \n connect slots_13.io.in_uop.bits.ftq_idx, issue_slots[13].in_uop.bits.ftq_idx \n connect slots_13.io.in_uop.bits.is_mov, issue_slots[13].in_uop.bits.is_mov \n connect slots_13.io.in_uop.bits.is_rocc, issue_slots[13].in_uop.bits.is_rocc \n connect slots_13.io.in_uop.bits.is_sys_pc2epc, issue_slots[13].in_uop.bits.is_sys_pc2epc \n connect slots_13.io.in_uop.bits.is_eret, issue_slots[13].in_uop.bits.is_eret \n connect slots_13.io.in_uop.bits.is_amo, issue_slots[13].in_uop.bits.is_amo \n connect slots_13.io.in_uop.bits.is_sfence, issue_slots[13].in_uop.bits.is_sfence \n connect slots_13.io.in_uop.bits.is_fencei, issue_slots[13].in_uop.bits.is_fencei \n connect slots_13.io.in_uop.bits.is_fence, issue_slots[13].in_uop.bits.is_fence \n connect slots_13.io.in_uop.bits.is_sfb, issue_slots[13].in_uop.bits.is_sfb \n connect slots_13.io.in_uop.bits.br_type, issue_slots[13].in_uop.bits.br_type \n connect slots_13.io.in_uop.bits.br_tag, issue_slots[13].in_uop.bits.br_tag \n connect slots_13.io.in_uop.bits.br_mask, issue_slots[13].in_uop.bits.br_mask \n connect slots_13.io.in_uop.bits.dis_col_sel, issue_slots[13].in_uop.bits.dis_col_sel \n connect slots_13.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[13].in_uop.bits.iw_p3_bypass_hint \n connect slots_13.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[13].in_uop.bits.iw_p2_bypass_hint \n connect slots_13.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[13].in_uop.bits.iw_p1_bypass_hint \n connect slots_13.io.in_uop.bits.iw_p2_speculative_child, issue_slots[13].in_uop.bits.iw_p2_speculative_child \n connect slots_13.io.in_uop.bits.iw_p1_speculative_child, issue_slots[13].in_uop.bits.iw_p1_speculative_child \n connect slots_13.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[13].in_uop.bits.iw_issued_partial_dgen \n connect slots_13.io.in_uop.bits.iw_issued_partial_agen, issue_slots[13].in_uop.bits.iw_issued_partial_agen \n connect slots_13.io.in_uop.bits.iw_issued, issue_slots[13].in_uop.bits.iw_issued \n connect slots_13.io.in_uop.bits.fu_code[0], issue_slots[13].in_uop.bits.fu_code[0] \n connect slots_13.io.in_uop.bits.fu_code[1], issue_slots[13].in_uop.bits.fu_code[1] \n connect slots_13.io.in_uop.bits.fu_code[2], issue_slots[13].in_uop.bits.fu_code[2] \n connect slots_13.io.in_uop.bits.fu_code[3], issue_slots[13].in_uop.bits.fu_code[3] \n connect slots_13.io.in_uop.bits.fu_code[4], issue_slots[13].in_uop.bits.fu_code[4] \n connect slots_13.io.in_uop.bits.fu_code[5], issue_slots[13].in_uop.bits.fu_code[5] \n connect slots_13.io.in_uop.bits.fu_code[6], issue_slots[13].in_uop.bits.fu_code[6] \n connect slots_13.io.in_uop.bits.fu_code[7], issue_slots[13].in_uop.bits.fu_code[7] \n connect slots_13.io.in_uop.bits.fu_code[8], issue_slots[13].in_uop.bits.fu_code[8] \n connect slots_13.io.in_uop.bits.fu_code[9], issue_slots[13].in_uop.bits.fu_code[9] \n connect slots_13.io.in_uop.bits.iq_type[0], issue_slots[13].in_uop.bits.iq_type[0] \n connect slots_13.io.in_uop.bits.iq_type[1], issue_slots[13].in_uop.bits.iq_type[1] \n connect slots_13.io.in_uop.bits.iq_type[2], issue_slots[13].in_uop.bits.iq_type[2] \n connect slots_13.io.in_uop.bits.iq_type[3], issue_slots[13].in_uop.bits.iq_type[3] \n connect slots_13.io.in_uop.bits.debug_pc, issue_slots[13].in_uop.bits.debug_pc \n connect slots_13.io.in_uop.bits.is_rvc, issue_slots[13].in_uop.bits.is_rvc \n connect slots_13.io.in_uop.bits.debug_inst, issue_slots[13].in_uop.bits.debug_inst \n connect slots_13.io.in_uop.bits.inst, issue_slots[13].in_uop.bits.inst \n connect slots_13.io.in_uop.valid, issue_slots[13].in_uop.valid \n connect issue_slots[13].iss_uop.debug_tsrc, slots_13.io.iss_uop.debug_tsrc \n connect issue_slots[13].iss_uop.debug_fsrc, slots_13.io.iss_uop.debug_fsrc \n connect issue_slots[13].iss_uop.bp_xcpt_if, slots_13.io.iss_uop.bp_xcpt_if \n connect issue_slots[13].iss_uop.bp_debug_if, slots_13.io.iss_uop.bp_debug_if \n connect issue_slots[13].iss_uop.xcpt_ma_if, slots_13.io.iss_uop.xcpt_ma_if \n connect issue_slots[13].iss_uop.xcpt_ae_if, slots_13.io.iss_uop.xcpt_ae_if \n connect issue_slots[13].iss_uop.xcpt_pf_if, slots_13.io.iss_uop.xcpt_pf_if \n connect issue_slots[13].iss_uop.fp_typ, slots_13.io.iss_uop.fp_typ \n connect issue_slots[13].iss_uop.fp_rm, slots_13.io.iss_uop.fp_rm \n connect issue_slots[13].iss_uop.fp_val, slots_13.io.iss_uop.fp_val \n connect issue_slots[13].iss_uop.fcn_op, slots_13.io.iss_uop.fcn_op \n connect issue_slots[13].iss_uop.fcn_dw, slots_13.io.iss_uop.fcn_dw \n connect issue_slots[13].iss_uop.frs3_en, slots_13.io.iss_uop.frs3_en \n connect issue_slots[13].iss_uop.lrs2_rtype, slots_13.io.iss_uop.lrs2_rtype \n connect issue_slots[13].iss_uop.lrs1_rtype, slots_13.io.iss_uop.lrs1_rtype \n connect issue_slots[13].iss_uop.dst_rtype, slots_13.io.iss_uop.dst_rtype \n connect issue_slots[13].iss_uop.lrs3, slots_13.io.iss_uop.lrs3 \n connect issue_slots[13].iss_uop.lrs2, slots_13.io.iss_uop.lrs2 \n connect issue_slots[13].iss_uop.lrs1, slots_13.io.iss_uop.lrs1 \n connect issue_slots[13].iss_uop.ldst, slots_13.io.iss_uop.ldst \n connect issue_slots[13].iss_uop.ldst_is_rs1, slots_13.io.iss_uop.ldst_is_rs1 \n connect issue_slots[13].iss_uop.csr_cmd, slots_13.io.iss_uop.csr_cmd \n connect issue_slots[13].iss_uop.flush_on_commit, slots_13.io.iss_uop.flush_on_commit \n connect issue_slots[13].iss_uop.is_unique, slots_13.io.iss_uop.is_unique \n connect issue_slots[13].iss_uop.uses_stq, slots_13.io.iss_uop.uses_stq \n connect issue_slots[13].iss_uop.uses_ldq, slots_13.io.iss_uop.uses_ldq \n connect issue_slots[13].iss_uop.mem_signed, slots_13.io.iss_uop.mem_signed \n connect issue_slots[13].iss_uop.mem_size, slots_13.io.iss_uop.mem_size \n connect issue_slots[13].iss_uop.mem_cmd, slots_13.io.iss_uop.mem_cmd \n connect issue_slots[13].iss_uop.exc_cause, slots_13.io.iss_uop.exc_cause \n connect issue_slots[13].iss_uop.exception, slots_13.io.iss_uop.exception \n connect issue_slots[13].iss_uop.stale_pdst, slots_13.io.iss_uop.stale_pdst \n connect issue_slots[13].iss_uop.ppred_busy, slots_13.io.iss_uop.ppred_busy \n connect issue_slots[13].iss_uop.prs3_busy, slots_13.io.iss_uop.prs3_busy \n connect issue_slots[13].iss_uop.prs2_busy, slots_13.io.iss_uop.prs2_busy \n connect issue_slots[13].iss_uop.prs1_busy, slots_13.io.iss_uop.prs1_busy \n connect issue_slots[13].iss_uop.ppred, slots_13.io.iss_uop.ppred \n connect issue_slots[13].iss_uop.prs3, slots_13.io.iss_uop.prs3 \n connect issue_slots[13].iss_uop.prs2, slots_13.io.iss_uop.prs2 \n connect issue_slots[13].iss_uop.prs1, slots_13.io.iss_uop.prs1 \n connect issue_slots[13].iss_uop.pdst, slots_13.io.iss_uop.pdst \n connect issue_slots[13].iss_uop.rxq_idx, slots_13.io.iss_uop.rxq_idx \n connect issue_slots[13].iss_uop.stq_idx, slots_13.io.iss_uop.stq_idx \n connect issue_slots[13].iss_uop.ldq_idx, slots_13.io.iss_uop.ldq_idx \n connect issue_slots[13].iss_uop.rob_idx, slots_13.io.iss_uop.rob_idx \n connect issue_slots[13].iss_uop.fp_ctrl.vec, slots_13.io.iss_uop.fp_ctrl.vec \n connect issue_slots[13].iss_uop.fp_ctrl.wflags, slots_13.io.iss_uop.fp_ctrl.wflags \n connect issue_slots[13].iss_uop.fp_ctrl.sqrt, slots_13.io.iss_uop.fp_ctrl.sqrt \n connect issue_slots[13].iss_uop.fp_ctrl.div, slots_13.io.iss_uop.fp_ctrl.div \n connect issue_slots[13].iss_uop.fp_ctrl.fma, slots_13.io.iss_uop.fp_ctrl.fma \n connect issue_slots[13].iss_uop.fp_ctrl.fastpipe, slots_13.io.iss_uop.fp_ctrl.fastpipe \n connect issue_slots[13].iss_uop.fp_ctrl.toint, slots_13.io.iss_uop.fp_ctrl.toint \n connect issue_slots[13].iss_uop.fp_ctrl.fromint, slots_13.io.iss_uop.fp_ctrl.fromint \n connect issue_slots[13].iss_uop.fp_ctrl.typeTagOut, slots_13.io.iss_uop.fp_ctrl.typeTagOut \n connect issue_slots[13].iss_uop.fp_ctrl.typeTagIn, slots_13.io.iss_uop.fp_ctrl.typeTagIn \n connect issue_slots[13].iss_uop.fp_ctrl.swap23, slots_13.io.iss_uop.fp_ctrl.swap23 \n connect issue_slots[13].iss_uop.fp_ctrl.swap12, slots_13.io.iss_uop.fp_ctrl.swap12 \n connect issue_slots[13].iss_uop.fp_ctrl.ren3, slots_13.io.iss_uop.fp_ctrl.ren3 \n connect issue_slots[13].iss_uop.fp_ctrl.ren2, slots_13.io.iss_uop.fp_ctrl.ren2 \n connect issue_slots[13].iss_uop.fp_ctrl.ren1, slots_13.io.iss_uop.fp_ctrl.ren1 \n connect issue_slots[13].iss_uop.fp_ctrl.wen, slots_13.io.iss_uop.fp_ctrl.wen \n connect issue_slots[13].iss_uop.fp_ctrl.ldst, slots_13.io.iss_uop.fp_ctrl.ldst \n connect issue_slots[13].iss_uop.op2_sel, slots_13.io.iss_uop.op2_sel \n connect issue_slots[13].iss_uop.op1_sel, slots_13.io.iss_uop.op1_sel \n connect issue_slots[13].iss_uop.imm_packed, slots_13.io.iss_uop.imm_packed \n connect issue_slots[13].iss_uop.pimm, slots_13.io.iss_uop.pimm \n connect issue_slots[13].iss_uop.imm_sel, slots_13.io.iss_uop.imm_sel \n connect issue_slots[13].iss_uop.imm_rename, slots_13.io.iss_uop.imm_rename \n connect issue_slots[13].iss_uop.taken, slots_13.io.iss_uop.taken \n connect issue_slots[13].iss_uop.pc_lob, slots_13.io.iss_uop.pc_lob \n connect issue_slots[13].iss_uop.edge_inst, slots_13.io.iss_uop.edge_inst \n connect issue_slots[13].iss_uop.ftq_idx, slots_13.io.iss_uop.ftq_idx \n connect issue_slots[13].iss_uop.is_mov, slots_13.io.iss_uop.is_mov \n connect issue_slots[13].iss_uop.is_rocc, slots_13.io.iss_uop.is_rocc \n connect issue_slots[13].iss_uop.is_sys_pc2epc, slots_13.io.iss_uop.is_sys_pc2epc \n connect issue_slots[13].iss_uop.is_eret, slots_13.io.iss_uop.is_eret \n connect issue_slots[13].iss_uop.is_amo, slots_13.io.iss_uop.is_amo \n connect issue_slots[13].iss_uop.is_sfence, slots_13.io.iss_uop.is_sfence \n connect issue_slots[13].iss_uop.is_fencei, slots_13.io.iss_uop.is_fencei \n connect issue_slots[13].iss_uop.is_fence, slots_13.io.iss_uop.is_fence \n connect issue_slots[13].iss_uop.is_sfb, slots_13.io.iss_uop.is_sfb \n connect issue_slots[13].iss_uop.br_type, slots_13.io.iss_uop.br_type \n connect issue_slots[13].iss_uop.br_tag, slots_13.io.iss_uop.br_tag \n connect issue_slots[13].iss_uop.br_mask, slots_13.io.iss_uop.br_mask \n connect issue_slots[13].iss_uop.dis_col_sel, slots_13.io.iss_uop.dis_col_sel \n connect issue_slots[13].iss_uop.iw_p3_bypass_hint, slots_13.io.iss_uop.iw_p3_bypass_hint \n connect issue_slots[13].iss_uop.iw_p2_bypass_hint, slots_13.io.iss_uop.iw_p2_bypass_hint \n connect issue_slots[13].iss_uop.iw_p1_bypass_hint, slots_13.io.iss_uop.iw_p1_bypass_hint \n connect issue_slots[13].iss_uop.iw_p2_speculative_child, slots_13.io.iss_uop.iw_p2_speculative_child \n connect issue_slots[13].iss_uop.iw_p1_speculative_child, slots_13.io.iss_uop.iw_p1_speculative_child \n connect issue_slots[13].iss_uop.iw_issued_partial_dgen, slots_13.io.iss_uop.iw_issued_partial_dgen \n connect issue_slots[13].iss_uop.iw_issued_partial_agen, slots_13.io.iss_uop.iw_issued_partial_agen \n connect issue_slots[13].iss_uop.iw_issued, slots_13.io.iss_uop.iw_issued \n connect issue_slots[13].iss_uop.fu_code[0], slots_13.io.iss_uop.fu_code[0] \n connect issue_slots[13].iss_uop.fu_code[1], slots_13.io.iss_uop.fu_code[1] \n connect issue_slots[13].iss_uop.fu_code[2], slots_13.io.iss_uop.fu_code[2] \n connect issue_slots[13].iss_uop.fu_code[3], slots_13.io.iss_uop.fu_code[3] \n connect issue_slots[13].iss_uop.fu_code[4], slots_13.io.iss_uop.fu_code[4] \n connect issue_slots[13].iss_uop.fu_code[5], slots_13.io.iss_uop.fu_code[5] \n connect issue_slots[13].iss_uop.fu_code[6], slots_13.io.iss_uop.fu_code[6] \n connect issue_slots[13].iss_uop.fu_code[7], slots_13.io.iss_uop.fu_code[7] \n connect issue_slots[13].iss_uop.fu_code[8], slots_13.io.iss_uop.fu_code[8] \n connect issue_slots[13].iss_uop.fu_code[9], slots_13.io.iss_uop.fu_code[9] \n connect issue_slots[13].iss_uop.iq_type[0], slots_13.io.iss_uop.iq_type[0] \n connect issue_slots[13].iss_uop.iq_type[1], slots_13.io.iss_uop.iq_type[1] \n connect issue_slots[13].iss_uop.iq_type[2], slots_13.io.iss_uop.iq_type[2] \n connect issue_slots[13].iss_uop.iq_type[3], slots_13.io.iss_uop.iq_type[3] \n connect issue_slots[13].iss_uop.debug_pc, slots_13.io.iss_uop.debug_pc \n connect issue_slots[13].iss_uop.is_rvc, slots_13.io.iss_uop.is_rvc \n connect issue_slots[13].iss_uop.debug_inst, slots_13.io.iss_uop.debug_inst \n connect issue_slots[13].iss_uop.inst, slots_13.io.iss_uop.inst \n connect slots_13.io.grant, issue_slots[13].grant \n connect issue_slots[13].request, slots_13.io.request \n connect issue_slots[13].will_be_valid, slots_13.io.will_be_valid \n connect issue_slots[13].valid, slots_13.io.valid \n connect slots_14.io.child_rebusys, issue_slots[14].child_rebusys \n connect slots_14.io.pred_wakeup_port.bits, issue_slots[14].pred_wakeup_port.bits \n connect slots_14.io.pred_wakeup_port.valid, issue_slots[14].pred_wakeup_port.valid \n connect slots_14.io.wakeup_ports[0].bits.rebusy, issue_slots[14].wakeup_ports[0].bits.rebusy \n connect slots_14.io.wakeup_ports[0].bits.speculative_mask, issue_slots[14].wakeup_ports[0].bits.speculative_mask \n connect slots_14.io.wakeup_ports[0].bits.bypassable, issue_slots[14].wakeup_ports[0].bits.bypassable \n connect slots_14.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[14].wakeup_ports[0].bits.uop.debug_tsrc \n connect slots_14.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[14].wakeup_ports[0].bits.uop.debug_fsrc \n connect slots_14.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[14].wakeup_ports[0].bits.uop.bp_xcpt_if \n connect slots_14.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[14].wakeup_ports[0].bits.uop.bp_debug_if \n connect slots_14.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[14].wakeup_ports[0].bits.uop.xcpt_ma_if \n connect slots_14.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[14].wakeup_ports[0].bits.uop.xcpt_ae_if \n connect slots_14.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[14].wakeup_ports[0].bits.uop.xcpt_pf_if \n connect slots_14.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[14].wakeup_ports[0].bits.uop.fp_typ \n connect slots_14.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[14].wakeup_ports[0].bits.uop.fp_rm \n connect slots_14.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[14].wakeup_ports[0].bits.uop.fp_val \n connect slots_14.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[14].wakeup_ports[0].bits.uop.fcn_op \n connect slots_14.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[14].wakeup_ports[0].bits.uop.fcn_dw \n connect slots_14.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[14].wakeup_ports[0].bits.uop.frs3_en \n connect slots_14.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[14].wakeup_ports[0].bits.uop.lrs2_rtype \n connect slots_14.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[14].wakeup_ports[0].bits.uop.lrs1_rtype \n connect slots_14.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[14].wakeup_ports[0].bits.uop.dst_rtype \n connect slots_14.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[14].wakeup_ports[0].bits.uop.lrs3 \n connect slots_14.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[14].wakeup_ports[0].bits.uop.lrs2 \n connect slots_14.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[14].wakeup_ports[0].bits.uop.lrs1 \n connect slots_14.io.wakeup_ports[0].bits.uop.ldst, issue_slots[14].wakeup_ports[0].bits.uop.ldst \n connect slots_14.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[14].wakeup_ports[0].bits.uop.ldst_is_rs1 \n connect slots_14.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[14].wakeup_ports[0].bits.uop.csr_cmd \n connect slots_14.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[14].wakeup_ports[0].bits.uop.flush_on_commit \n connect slots_14.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[14].wakeup_ports[0].bits.uop.is_unique \n connect slots_14.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[14].wakeup_ports[0].bits.uop.uses_stq \n connect slots_14.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[14].wakeup_ports[0].bits.uop.uses_ldq \n connect slots_14.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[14].wakeup_ports[0].bits.uop.mem_signed \n connect slots_14.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[14].wakeup_ports[0].bits.uop.mem_size \n connect slots_14.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[14].wakeup_ports[0].bits.uop.mem_cmd \n connect slots_14.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[14].wakeup_ports[0].bits.uop.exc_cause \n connect slots_14.io.wakeup_ports[0].bits.uop.exception, issue_slots[14].wakeup_ports[0].bits.uop.exception \n connect slots_14.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[14].wakeup_ports[0].bits.uop.stale_pdst \n connect slots_14.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[14].wakeup_ports[0].bits.uop.ppred_busy \n connect slots_14.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[14].wakeup_ports[0].bits.uop.prs3_busy \n connect slots_14.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[14].wakeup_ports[0].bits.uop.prs2_busy \n connect slots_14.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[14].wakeup_ports[0].bits.uop.prs1_busy \n connect slots_14.io.wakeup_ports[0].bits.uop.ppred, issue_slots[14].wakeup_ports[0].bits.uop.ppred \n connect slots_14.io.wakeup_ports[0].bits.uop.prs3, issue_slots[14].wakeup_ports[0].bits.uop.prs3 \n connect slots_14.io.wakeup_ports[0].bits.uop.prs2, issue_slots[14].wakeup_ports[0].bits.uop.prs2 \n connect slots_14.io.wakeup_ports[0].bits.uop.prs1, issue_slots[14].wakeup_ports[0].bits.uop.prs1 \n connect slots_14.io.wakeup_ports[0].bits.uop.pdst, issue_slots[14].wakeup_ports[0].bits.uop.pdst \n connect slots_14.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[14].wakeup_ports[0].bits.uop.rxq_idx \n connect slots_14.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[14].wakeup_ports[0].bits.uop.stq_idx \n connect slots_14.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[14].wakeup_ports[0].bits.uop.ldq_idx \n connect slots_14.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[14].wakeup_ports[0].bits.uop.rob_idx \n connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.vec \n connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.wflags \n connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.sqrt \n connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.div \n connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.fma \n connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe \n connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.toint \n connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.fromint \n connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut \n connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn \n connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.swap23 \n connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.swap12 \n connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.ren3 \n connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.ren2 \n connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.ren1 \n connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.wen \n connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.ldst \n connect slots_14.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[14].wakeup_ports[0].bits.uop.op2_sel \n connect slots_14.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[14].wakeup_ports[0].bits.uop.op1_sel \n connect slots_14.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[14].wakeup_ports[0].bits.uop.imm_packed \n connect slots_14.io.wakeup_ports[0].bits.uop.pimm, issue_slots[14].wakeup_ports[0].bits.uop.pimm \n connect slots_14.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[14].wakeup_ports[0].bits.uop.imm_sel \n connect slots_14.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[14].wakeup_ports[0].bits.uop.imm_rename \n connect slots_14.io.wakeup_ports[0].bits.uop.taken, issue_slots[14].wakeup_ports[0].bits.uop.taken \n connect slots_14.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[14].wakeup_ports[0].bits.uop.pc_lob \n connect slots_14.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[14].wakeup_ports[0].bits.uop.edge_inst \n connect slots_14.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[14].wakeup_ports[0].bits.uop.ftq_idx \n connect slots_14.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[14].wakeup_ports[0].bits.uop.is_mov \n connect slots_14.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[14].wakeup_ports[0].bits.uop.is_rocc \n connect slots_14.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[14].wakeup_ports[0].bits.uop.is_sys_pc2epc \n connect slots_14.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[14].wakeup_ports[0].bits.uop.is_eret \n connect slots_14.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[14].wakeup_ports[0].bits.uop.is_amo \n connect slots_14.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[14].wakeup_ports[0].bits.uop.is_sfence \n connect slots_14.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[14].wakeup_ports[0].bits.uop.is_fencei \n connect slots_14.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[14].wakeup_ports[0].bits.uop.is_fence \n connect slots_14.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[14].wakeup_ports[0].bits.uop.is_sfb \n connect slots_14.io.wakeup_ports[0].bits.uop.br_type, issue_slots[14].wakeup_ports[0].bits.uop.br_type \n connect slots_14.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[14].wakeup_ports[0].bits.uop.br_tag \n connect slots_14.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[14].wakeup_ports[0].bits.uop.br_mask \n connect slots_14.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[14].wakeup_ports[0].bits.uop.dis_col_sel \n connect slots_14.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[14].wakeup_ports[0].bits.uop.iw_p3_bypass_hint \n connect slots_14.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[14].wakeup_ports[0].bits.uop.iw_p2_bypass_hint \n connect slots_14.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[14].wakeup_ports[0].bits.uop.iw_p1_bypass_hint \n connect slots_14.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[14].wakeup_ports[0].bits.uop.iw_p2_speculative_child \n connect slots_14.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[14].wakeup_ports[0].bits.uop.iw_p1_speculative_child \n connect slots_14.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[14].wakeup_ports[0].bits.uop.iw_issued_partial_dgen \n connect slots_14.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[14].wakeup_ports[0].bits.uop.iw_issued_partial_agen \n connect slots_14.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[14].wakeup_ports[0].bits.uop.iw_issued \n connect slots_14.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[14].wakeup_ports[0].bits.uop.fu_code[0] \n connect slots_14.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[14].wakeup_ports[0].bits.uop.fu_code[1] \n connect slots_14.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[14].wakeup_ports[0].bits.uop.fu_code[2] \n connect slots_14.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[14].wakeup_ports[0].bits.uop.fu_code[3] \n connect slots_14.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[14].wakeup_ports[0].bits.uop.fu_code[4] \n connect slots_14.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[14].wakeup_ports[0].bits.uop.fu_code[5] \n connect slots_14.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[14].wakeup_ports[0].bits.uop.fu_code[6] \n connect slots_14.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[14].wakeup_ports[0].bits.uop.fu_code[7] \n connect slots_14.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[14].wakeup_ports[0].bits.uop.fu_code[8] \n connect slots_14.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[14].wakeup_ports[0].bits.uop.fu_code[9] \n connect slots_14.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[14].wakeup_ports[0].bits.uop.iq_type[0] \n connect slots_14.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[14].wakeup_ports[0].bits.uop.iq_type[1] \n connect slots_14.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[14].wakeup_ports[0].bits.uop.iq_type[2] \n connect slots_14.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[14].wakeup_ports[0].bits.uop.iq_type[3] \n connect slots_14.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[14].wakeup_ports[0].bits.uop.debug_pc \n connect slots_14.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[14].wakeup_ports[0].bits.uop.is_rvc \n connect slots_14.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[14].wakeup_ports[0].bits.uop.debug_inst \n connect slots_14.io.wakeup_ports[0].bits.uop.inst, issue_slots[14].wakeup_ports[0].bits.uop.inst \n connect slots_14.io.wakeup_ports[0].valid, issue_slots[14].wakeup_ports[0].valid \n connect slots_14.io.wakeup_ports[1].bits.rebusy, issue_slots[14].wakeup_ports[1].bits.rebusy \n connect slots_14.io.wakeup_ports[1].bits.speculative_mask, issue_slots[14].wakeup_ports[1].bits.speculative_mask \n connect slots_14.io.wakeup_ports[1].bits.bypassable, issue_slots[14].wakeup_ports[1].bits.bypassable \n connect slots_14.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[14].wakeup_ports[1].bits.uop.debug_tsrc \n connect slots_14.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[14].wakeup_ports[1].bits.uop.debug_fsrc \n connect slots_14.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[14].wakeup_ports[1].bits.uop.bp_xcpt_if \n connect slots_14.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[14].wakeup_ports[1].bits.uop.bp_debug_if \n connect slots_14.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[14].wakeup_ports[1].bits.uop.xcpt_ma_if \n connect slots_14.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[14].wakeup_ports[1].bits.uop.xcpt_ae_if \n connect slots_14.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[14].wakeup_ports[1].bits.uop.xcpt_pf_if \n connect slots_14.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[14].wakeup_ports[1].bits.uop.fp_typ \n connect slots_14.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[14].wakeup_ports[1].bits.uop.fp_rm \n connect slots_14.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[14].wakeup_ports[1].bits.uop.fp_val \n connect slots_14.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[14].wakeup_ports[1].bits.uop.fcn_op \n connect slots_14.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[14].wakeup_ports[1].bits.uop.fcn_dw \n connect slots_14.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[14].wakeup_ports[1].bits.uop.frs3_en \n connect slots_14.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[14].wakeup_ports[1].bits.uop.lrs2_rtype \n connect slots_14.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[14].wakeup_ports[1].bits.uop.lrs1_rtype \n connect slots_14.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[14].wakeup_ports[1].bits.uop.dst_rtype \n connect slots_14.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[14].wakeup_ports[1].bits.uop.lrs3 \n connect slots_14.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[14].wakeup_ports[1].bits.uop.lrs2 \n connect slots_14.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[14].wakeup_ports[1].bits.uop.lrs1 \n connect slots_14.io.wakeup_ports[1].bits.uop.ldst, issue_slots[14].wakeup_ports[1].bits.uop.ldst \n connect slots_14.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[14].wakeup_ports[1].bits.uop.ldst_is_rs1 \n connect slots_14.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[14].wakeup_ports[1].bits.uop.csr_cmd \n connect slots_14.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[14].wakeup_ports[1].bits.uop.flush_on_commit \n connect slots_14.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[14].wakeup_ports[1].bits.uop.is_unique \n connect slots_14.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[14].wakeup_ports[1].bits.uop.uses_stq \n connect slots_14.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[14].wakeup_ports[1].bits.uop.uses_ldq \n connect slots_14.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[14].wakeup_ports[1].bits.uop.mem_signed \n connect slots_14.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[14].wakeup_ports[1].bits.uop.mem_size \n connect slots_14.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[14].wakeup_ports[1].bits.uop.mem_cmd \n connect slots_14.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[14].wakeup_ports[1].bits.uop.exc_cause \n connect slots_14.io.wakeup_ports[1].bits.uop.exception, issue_slots[14].wakeup_ports[1].bits.uop.exception \n connect slots_14.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[14].wakeup_ports[1].bits.uop.stale_pdst \n connect slots_14.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[14].wakeup_ports[1].bits.uop.ppred_busy \n connect slots_14.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[14].wakeup_ports[1].bits.uop.prs3_busy \n connect slots_14.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[14].wakeup_ports[1].bits.uop.prs2_busy \n connect slots_14.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[14].wakeup_ports[1].bits.uop.prs1_busy \n connect slots_14.io.wakeup_ports[1].bits.uop.ppred, issue_slots[14].wakeup_ports[1].bits.uop.ppred \n connect slots_14.io.wakeup_ports[1].bits.uop.prs3, issue_slots[14].wakeup_ports[1].bits.uop.prs3 \n connect slots_14.io.wakeup_ports[1].bits.uop.prs2, issue_slots[14].wakeup_ports[1].bits.uop.prs2 \n connect slots_14.io.wakeup_ports[1].bits.uop.prs1, issue_slots[14].wakeup_ports[1].bits.uop.prs1 \n connect slots_14.io.wakeup_ports[1].bits.uop.pdst, issue_slots[14].wakeup_ports[1].bits.uop.pdst \n connect slots_14.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[14].wakeup_ports[1].bits.uop.rxq_idx \n connect slots_14.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[14].wakeup_ports[1].bits.uop.stq_idx \n connect slots_14.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[14].wakeup_ports[1].bits.uop.ldq_idx \n connect slots_14.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[14].wakeup_ports[1].bits.uop.rob_idx \n connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.vec \n connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.wflags \n connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.sqrt \n connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.div \n connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.fma \n connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe \n connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.toint \n connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.fromint \n connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut \n connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn \n connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.swap23 \n connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.swap12 \n connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.ren3 \n connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.ren2 \n connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.ren1 \n connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.wen \n connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.ldst \n connect slots_14.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[14].wakeup_ports[1].bits.uop.op2_sel \n connect slots_14.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[14].wakeup_ports[1].bits.uop.op1_sel \n connect slots_14.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[14].wakeup_ports[1].bits.uop.imm_packed \n connect slots_14.io.wakeup_ports[1].bits.uop.pimm, issue_slots[14].wakeup_ports[1].bits.uop.pimm \n connect slots_14.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[14].wakeup_ports[1].bits.uop.imm_sel \n connect slots_14.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[14].wakeup_ports[1].bits.uop.imm_rename \n connect slots_14.io.wakeup_ports[1].bits.uop.taken, issue_slots[14].wakeup_ports[1].bits.uop.taken \n connect slots_14.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[14].wakeup_ports[1].bits.uop.pc_lob \n connect slots_14.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[14].wakeup_ports[1].bits.uop.edge_inst \n connect slots_14.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[14].wakeup_ports[1].bits.uop.ftq_idx \n connect slots_14.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[14].wakeup_ports[1].bits.uop.is_mov \n connect slots_14.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[14].wakeup_ports[1].bits.uop.is_rocc \n connect slots_14.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[14].wakeup_ports[1].bits.uop.is_sys_pc2epc \n connect slots_14.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[14].wakeup_ports[1].bits.uop.is_eret \n connect slots_14.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[14].wakeup_ports[1].bits.uop.is_amo \n connect slots_14.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[14].wakeup_ports[1].bits.uop.is_sfence \n connect slots_14.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[14].wakeup_ports[1].bits.uop.is_fencei \n connect slots_14.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[14].wakeup_ports[1].bits.uop.is_fence \n connect slots_14.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[14].wakeup_ports[1].bits.uop.is_sfb \n connect slots_14.io.wakeup_ports[1].bits.uop.br_type, issue_slots[14].wakeup_ports[1].bits.uop.br_type \n connect slots_14.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[14].wakeup_ports[1].bits.uop.br_tag \n connect slots_14.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[14].wakeup_ports[1].bits.uop.br_mask \n connect slots_14.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[14].wakeup_ports[1].bits.uop.dis_col_sel \n connect slots_14.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[14].wakeup_ports[1].bits.uop.iw_p3_bypass_hint \n connect slots_14.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[14].wakeup_ports[1].bits.uop.iw_p2_bypass_hint \n connect slots_14.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[14].wakeup_ports[1].bits.uop.iw_p1_bypass_hint \n connect slots_14.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[14].wakeup_ports[1].bits.uop.iw_p2_speculative_child \n connect slots_14.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[14].wakeup_ports[1].bits.uop.iw_p1_speculative_child \n connect slots_14.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[14].wakeup_ports[1].bits.uop.iw_issued_partial_dgen \n connect slots_14.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[14].wakeup_ports[1].bits.uop.iw_issued_partial_agen \n connect slots_14.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[14].wakeup_ports[1].bits.uop.iw_issued \n connect slots_14.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[14].wakeup_ports[1].bits.uop.fu_code[0] \n connect slots_14.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[14].wakeup_ports[1].bits.uop.fu_code[1] \n connect slots_14.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[14].wakeup_ports[1].bits.uop.fu_code[2] \n connect slots_14.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[14].wakeup_ports[1].bits.uop.fu_code[3] \n connect slots_14.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[14].wakeup_ports[1].bits.uop.fu_code[4] \n connect slots_14.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[14].wakeup_ports[1].bits.uop.fu_code[5] \n connect slots_14.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[14].wakeup_ports[1].bits.uop.fu_code[6] \n connect slots_14.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[14].wakeup_ports[1].bits.uop.fu_code[7] \n connect slots_14.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[14].wakeup_ports[1].bits.uop.fu_code[8] \n connect slots_14.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[14].wakeup_ports[1].bits.uop.fu_code[9] \n connect slots_14.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[14].wakeup_ports[1].bits.uop.iq_type[0] \n connect slots_14.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[14].wakeup_ports[1].bits.uop.iq_type[1] \n connect slots_14.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[14].wakeup_ports[1].bits.uop.iq_type[2] \n connect slots_14.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[14].wakeup_ports[1].bits.uop.iq_type[3] \n connect slots_14.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[14].wakeup_ports[1].bits.uop.debug_pc \n connect slots_14.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[14].wakeup_ports[1].bits.uop.is_rvc \n connect slots_14.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[14].wakeup_ports[1].bits.uop.debug_inst \n connect slots_14.io.wakeup_ports[1].bits.uop.inst, issue_slots[14].wakeup_ports[1].bits.uop.inst \n connect slots_14.io.wakeup_ports[1].valid, issue_slots[14].wakeup_ports[1].valid \n connect slots_14.io.wakeup_ports[2].bits.rebusy, issue_slots[14].wakeup_ports[2].bits.rebusy \n connect slots_14.io.wakeup_ports[2].bits.speculative_mask, issue_slots[14].wakeup_ports[2].bits.speculative_mask \n connect slots_14.io.wakeup_ports[2].bits.bypassable, issue_slots[14].wakeup_ports[2].bits.bypassable \n connect slots_14.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[14].wakeup_ports[2].bits.uop.debug_tsrc \n connect slots_14.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[14].wakeup_ports[2].bits.uop.debug_fsrc \n connect slots_14.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[14].wakeup_ports[2].bits.uop.bp_xcpt_if \n connect slots_14.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[14].wakeup_ports[2].bits.uop.bp_debug_if \n connect slots_14.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[14].wakeup_ports[2].bits.uop.xcpt_ma_if \n connect slots_14.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[14].wakeup_ports[2].bits.uop.xcpt_ae_if \n connect slots_14.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[14].wakeup_ports[2].bits.uop.xcpt_pf_if \n connect slots_14.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[14].wakeup_ports[2].bits.uop.fp_typ \n connect slots_14.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[14].wakeup_ports[2].bits.uop.fp_rm \n connect slots_14.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[14].wakeup_ports[2].bits.uop.fp_val \n connect slots_14.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[14].wakeup_ports[2].bits.uop.fcn_op \n connect slots_14.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[14].wakeup_ports[2].bits.uop.fcn_dw \n connect slots_14.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[14].wakeup_ports[2].bits.uop.frs3_en \n connect slots_14.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[14].wakeup_ports[2].bits.uop.lrs2_rtype \n connect slots_14.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[14].wakeup_ports[2].bits.uop.lrs1_rtype \n connect slots_14.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[14].wakeup_ports[2].bits.uop.dst_rtype \n connect slots_14.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[14].wakeup_ports[2].bits.uop.lrs3 \n connect slots_14.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[14].wakeup_ports[2].bits.uop.lrs2 \n connect slots_14.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[14].wakeup_ports[2].bits.uop.lrs1 \n connect slots_14.io.wakeup_ports[2].bits.uop.ldst, issue_slots[14].wakeup_ports[2].bits.uop.ldst \n connect slots_14.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[14].wakeup_ports[2].bits.uop.ldst_is_rs1 \n connect slots_14.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[14].wakeup_ports[2].bits.uop.csr_cmd \n connect slots_14.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[14].wakeup_ports[2].bits.uop.flush_on_commit \n connect slots_14.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[14].wakeup_ports[2].bits.uop.is_unique \n connect slots_14.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[14].wakeup_ports[2].bits.uop.uses_stq \n connect slots_14.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[14].wakeup_ports[2].bits.uop.uses_ldq \n connect slots_14.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[14].wakeup_ports[2].bits.uop.mem_signed \n connect slots_14.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[14].wakeup_ports[2].bits.uop.mem_size \n connect slots_14.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[14].wakeup_ports[2].bits.uop.mem_cmd \n connect slots_14.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[14].wakeup_ports[2].bits.uop.exc_cause \n connect slots_14.io.wakeup_ports[2].bits.uop.exception, issue_slots[14].wakeup_ports[2].bits.uop.exception \n connect slots_14.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[14].wakeup_ports[2].bits.uop.stale_pdst \n connect slots_14.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[14].wakeup_ports[2].bits.uop.ppred_busy \n connect slots_14.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[14].wakeup_ports[2].bits.uop.prs3_busy \n connect slots_14.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[14].wakeup_ports[2].bits.uop.prs2_busy \n connect slots_14.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[14].wakeup_ports[2].bits.uop.prs1_busy \n connect slots_14.io.wakeup_ports[2].bits.uop.ppred, issue_slots[14].wakeup_ports[2].bits.uop.ppred \n connect slots_14.io.wakeup_ports[2].bits.uop.prs3, issue_slots[14].wakeup_ports[2].bits.uop.prs3 \n connect slots_14.io.wakeup_ports[2].bits.uop.prs2, issue_slots[14].wakeup_ports[2].bits.uop.prs2 \n connect slots_14.io.wakeup_ports[2].bits.uop.prs1, issue_slots[14].wakeup_ports[2].bits.uop.prs1 \n connect slots_14.io.wakeup_ports[2].bits.uop.pdst, issue_slots[14].wakeup_ports[2].bits.uop.pdst \n connect slots_14.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[14].wakeup_ports[2].bits.uop.rxq_idx \n connect slots_14.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[14].wakeup_ports[2].bits.uop.stq_idx \n connect slots_14.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[14].wakeup_ports[2].bits.uop.ldq_idx \n connect slots_14.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[14].wakeup_ports[2].bits.uop.rob_idx \n connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.vec \n connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.wflags \n connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.sqrt \n connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.div \n connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.fma \n connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe \n connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.toint \n connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.fromint \n connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut \n connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn \n connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.swap23 \n connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.swap12 \n connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.ren3 \n connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.ren2 \n connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.ren1 \n connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.wen \n connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.ldst \n connect slots_14.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[14].wakeup_ports[2].bits.uop.op2_sel \n connect slots_14.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[14].wakeup_ports[2].bits.uop.op1_sel \n connect slots_14.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[14].wakeup_ports[2].bits.uop.imm_packed \n connect slots_14.io.wakeup_ports[2].bits.uop.pimm, issue_slots[14].wakeup_ports[2].bits.uop.pimm \n connect slots_14.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[14].wakeup_ports[2].bits.uop.imm_sel \n connect slots_14.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[14].wakeup_ports[2].bits.uop.imm_rename \n connect slots_14.io.wakeup_ports[2].bits.uop.taken, issue_slots[14].wakeup_ports[2].bits.uop.taken \n connect slots_14.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[14].wakeup_ports[2].bits.uop.pc_lob \n connect slots_14.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[14].wakeup_ports[2].bits.uop.edge_inst \n connect slots_14.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[14].wakeup_ports[2].bits.uop.ftq_idx \n connect slots_14.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[14].wakeup_ports[2].bits.uop.is_mov \n connect slots_14.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[14].wakeup_ports[2].bits.uop.is_rocc \n connect slots_14.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[14].wakeup_ports[2].bits.uop.is_sys_pc2epc \n connect slots_14.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[14].wakeup_ports[2].bits.uop.is_eret \n connect slots_14.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[14].wakeup_ports[2].bits.uop.is_amo \n connect slots_14.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[14].wakeup_ports[2].bits.uop.is_sfence \n connect slots_14.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[14].wakeup_ports[2].bits.uop.is_fencei \n connect slots_14.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[14].wakeup_ports[2].bits.uop.is_fence \n connect slots_14.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[14].wakeup_ports[2].bits.uop.is_sfb \n connect slots_14.io.wakeup_ports[2].bits.uop.br_type, issue_slots[14].wakeup_ports[2].bits.uop.br_type \n connect slots_14.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[14].wakeup_ports[2].bits.uop.br_tag \n connect slots_14.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[14].wakeup_ports[2].bits.uop.br_mask \n connect slots_14.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[14].wakeup_ports[2].bits.uop.dis_col_sel \n connect slots_14.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[14].wakeup_ports[2].bits.uop.iw_p3_bypass_hint \n connect slots_14.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[14].wakeup_ports[2].bits.uop.iw_p2_bypass_hint \n connect slots_14.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[14].wakeup_ports[2].bits.uop.iw_p1_bypass_hint \n connect slots_14.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[14].wakeup_ports[2].bits.uop.iw_p2_speculative_child \n connect slots_14.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[14].wakeup_ports[2].bits.uop.iw_p1_speculative_child \n connect slots_14.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[14].wakeup_ports[2].bits.uop.iw_issued_partial_dgen \n connect slots_14.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[14].wakeup_ports[2].bits.uop.iw_issued_partial_agen \n connect slots_14.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[14].wakeup_ports[2].bits.uop.iw_issued \n connect slots_14.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[14].wakeup_ports[2].bits.uop.fu_code[0] \n connect slots_14.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[14].wakeup_ports[2].bits.uop.fu_code[1] \n connect slots_14.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[14].wakeup_ports[2].bits.uop.fu_code[2] \n connect slots_14.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[14].wakeup_ports[2].bits.uop.fu_code[3] \n connect slots_14.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[14].wakeup_ports[2].bits.uop.fu_code[4] \n connect slots_14.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[14].wakeup_ports[2].bits.uop.fu_code[5] \n connect slots_14.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[14].wakeup_ports[2].bits.uop.fu_code[6] \n connect slots_14.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[14].wakeup_ports[2].bits.uop.fu_code[7] \n connect slots_14.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[14].wakeup_ports[2].bits.uop.fu_code[8] \n connect slots_14.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[14].wakeup_ports[2].bits.uop.fu_code[9] \n connect slots_14.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[14].wakeup_ports[2].bits.uop.iq_type[0] \n connect slots_14.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[14].wakeup_ports[2].bits.uop.iq_type[1] \n connect slots_14.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[14].wakeup_ports[2].bits.uop.iq_type[2] \n connect slots_14.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[14].wakeup_ports[2].bits.uop.iq_type[3] \n connect slots_14.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[14].wakeup_ports[2].bits.uop.debug_pc \n connect slots_14.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[14].wakeup_ports[2].bits.uop.is_rvc \n connect slots_14.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[14].wakeup_ports[2].bits.uop.debug_inst \n connect slots_14.io.wakeup_ports[2].bits.uop.inst, issue_slots[14].wakeup_ports[2].bits.uop.inst \n connect slots_14.io.wakeup_ports[2].valid, issue_slots[14].wakeup_ports[2].valid \n connect slots_14.io.wakeup_ports[3].bits.rebusy, issue_slots[14].wakeup_ports[3].bits.rebusy \n connect slots_14.io.wakeup_ports[3].bits.speculative_mask, issue_slots[14].wakeup_ports[3].bits.speculative_mask \n connect slots_14.io.wakeup_ports[3].bits.bypassable, issue_slots[14].wakeup_ports[3].bits.bypassable \n connect slots_14.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[14].wakeup_ports[3].bits.uop.debug_tsrc \n connect slots_14.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[14].wakeup_ports[3].bits.uop.debug_fsrc \n connect slots_14.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[14].wakeup_ports[3].bits.uop.bp_xcpt_if \n connect slots_14.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[14].wakeup_ports[3].bits.uop.bp_debug_if \n connect slots_14.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[14].wakeup_ports[3].bits.uop.xcpt_ma_if \n connect slots_14.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[14].wakeup_ports[3].bits.uop.xcpt_ae_if \n connect slots_14.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[14].wakeup_ports[3].bits.uop.xcpt_pf_if \n connect slots_14.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[14].wakeup_ports[3].bits.uop.fp_typ \n connect slots_14.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[14].wakeup_ports[3].bits.uop.fp_rm \n connect slots_14.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[14].wakeup_ports[3].bits.uop.fp_val \n connect slots_14.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[14].wakeup_ports[3].bits.uop.fcn_op \n connect slots_14.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[14].wakeup_ports[3].bits.uop.fcn_dw \n connect slots_14.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[14].wakeup_ports[3].bits.uop.frs3_en \n connect slots_14.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[14].wakeup_ports[3].bits.uop.lrs2_rtype \n connect slots_14.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[14].wakeup_ports[3].bits.uop.lrs1_rtype \n connect slots_14.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[14].wakeup_ports[3].bits.uop.dst_rtype \n connect slots_14.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[14].wakeup_ports[3].bits.uop.lrs3 \n connect slots_14.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[14].wakeup_ports[3].bits.uop.lrs2 \n connect slots_14.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[14].wakeup_ports[3].bits.uop.lrs1 \n connect slots_14.io.wakeup_ports[3].bits.uop.ldst, issue_slots[14].wakeup_ports[3].bits.uop.ldst \n connect slots_14.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[14].wakeup_ports[3].bits.uop.ldst_is_rs1 \n connect slots_14.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[14].wakeup_ports[3].bits.uop.csr_cmd \n connect slots_14.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[14].wakeup_ports[3].bits.uop.flush_on_commit \n connect slots_14.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[14].wakeup_ports[3].bits.uop.is_unique \n connect slots_14.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[14].wakeup_ports[3].bits.uop.uses_stq \n connect slots_14.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[14].wakeup_ports[3].bits.uop.uses_ldq \n connect slots_14.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[14].wakeup_ports[3].bits.uop.mem_signed \n connect slots_14.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[14].wakeup_ports[3].bits.uop.mem_size \n connect slots_14.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[14].wakeup_ports[3].bits.uop.mem_cmd \n connect slots_14.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[14].wakeup_ports[3].bits.uop.exc_cause \n connect slots_14.io.wakeup_ports[3].bits.uop.exception, issue_slots[14].wakeup_ports[3].bits.uop.exception \n connect slots_14.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[14].wakeup_ports[3].bits.uop.stale_pdst \n connect slots_14.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[14].wakeup_ports[3].bits.uop.ppred_busy \n connect slots_14.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[14].wakeup_ports[3].bits.uop.prs3_busy \n connect slots_14.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[14].wakeup_ports[3].bits.uop.prs2_busy \n connect slots_14.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[14].wakeup_ports[3].bits.uop.prs1_busy \n connect slots_14.io.wakeup_ports[3].bits.uop.ppred, issue_slots[14].wakeup_ports[3].bits.uop.ppred \n connect slots_14.io.wakeup_ports[3].bits.uop.prs3, issue_slots[14].wakeup_ports[3].bits.uop.prs3 \n connect slots_14.io.wakeup_ports[3].bits.uop.prs2, issue_slots[14].wakeup_ports[3].bits.uop.prs2 \n connect slots_14.io.wakeup_ports[3].bits.uop.prs1, issue_slots[14].wakeup_ports[3].bits.uop.prs1 \n connect slots_14.io.wakeup_ports[3].bits.uop.pdst, issue_slots[14].wakeup_ports[3].bits.uop.pdst \n connect slots_14.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[14].wakeup_ports[3].bits.uop.rxq_idx \n connect slots_14.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[14].wakeup_ports[3].bits.uop.stq_idx \n connect slots_14.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[14].wakeup_ports[3].bits.uop.ldq_idx \n connect slots_14.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[14].wakeup_ports[3].bits.uop.rob_idx \n connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.vec \n connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.wflags \n connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.sqrt \n connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.div \n connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.fma \n connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe \n connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.toint \n connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.fromint \n connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut \n connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn \n connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.swap23 \n connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.swap12 \n connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.ren3 \n connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.ren2 \n connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.ren1 \n connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.wen \n connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.ldst \n connect slots_14.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[14].wakeup_ports[3].bits.uop.op2_sel \n connect slots_14.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[14].wakeup_ports[3].bits.uop.op1_sel \n connect slots_14.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[14].wakeup_ports[3].bits.uop.imm_packed \n connect slots_14.io.wakeup_ports[3].bits.uop.pimm, issue_slots[14].wakeup_ports[3].bits.uop.pimm \n connect slots_14.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[14].wakeup_ports[3].bits.uop.imm_sel \n connect slots_14.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[14].wakeup_ports[3].bits.uop.imm_rename \n connect slots_14.io.wakeup_ports[3].bits.uop.taken, issue_slots[14].wakeup_ports[3].bits.uop.taken \n connect slots_14.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[14].wakeup_ports[3].bits.uop.pc_lob \n connect slots_14.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[14].wakeup_ports[3].bits.uop.edge_inst \n connect slots_14.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[14].wakeup_ports[3].bits.uop.ftq_idx \n connect slots_14.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[14].wakeup_ports[3].bits.uop.is_mov \n connect slots_14.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[14].wakeup_ports[3].bits.uop.is_rocc \n connect slots_14.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[14].wakeup_ports[3].bits.uop.is_sys_pc2epc \n connect slots_14.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[14].wakeup_ports[3].bits.uop.is_eret \n connect slots_14.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[14].wakeup_ports[3].bits.uop.is_amo \n connect slots_14.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[14].wakeup_ports[3].bits.uop.is_sfence \n connect slots_14.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[14].wakeup_ports[3].bits.uop.is_fencei \n connect slots_14.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[14].wakeup_ports[3].bits.uop.is_fence \n connect slots_14.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[14].wakeup_ports[3].bits.uop.is_sfb \n connect slots_14.io.wakeup_ports[3].bits.uop.br_type, issue_slots[14].wakeup_ports[3].bits.uop.br_type \n connect slots_14.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[14].wakeup_ports[3].bits.uop.br_tag \n connect slots_14.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[14].wakeup_ports[3].bits.uop.br_mask \n connect slots_14.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[14].wakeup_ports[3].bits.uop.dis_col_sel \n connect slots_14.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[14].wakeup_ports[3].bits.uop.iw_p3_bypass_hint \n connect slots_14.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[14].wakeup_ports[3].bits.uop.iw_p2_bypass_hint \n connect slots_14.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[14].wakeup_ports[3].bits.uop.iw_p1_bypass_hint \n connect slots_14.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[14].wakeup_ports[3].bits.uop.iw_p2_speculative_child \n connect slots_14.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[14].wakeup_ports[3].bits.uop.iw_p1_speculative_child \n connect slots_14.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[14].wakeup_ports[3].bits.uop.iw_issued_partial_dgen \n connect slots_14.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[14].wakeup_ports[3].bits.uop.iw_issued_partial_agen \n connect slots_14.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[14].wakeup_ports[3].bits.uop.iw_issued \n connect slots_14.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[14].wakeup_ports[3].bits.uop.fu_code[0] \n connect slots_14.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[14].wakeup_ports[3].bits.uop.fu_code[1] \n connect slots_14.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[14].wakeup_ports[3].bits.uop.fu_code[2] \n connect slots_14.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[14].wakeup_ports[3].bits.uop.fu_code[3] \n connect slots_14.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[14].wakeup_ports[3].bits.uop.fu_code[4] \n connect slots_14.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[14].wakeup_ports[3].bits.uop.fu_code[5] \n connect slots_14.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[14].wakeup_ports[3].bits.uop.fu_code[6] \n connect slots_14.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[14].wakeup_ports[3].bits.uop.fu_code[7] \n connect slots_14.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[14].wakeup_ports[3].bits.uop.fu_code[8] \n connect slots_14.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[14].wakeup_ports[3].bits.uop.fu_code[9] \n connect slots_14.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[14].wakeup_ports[3].bits.uop.iq_type[0] \n connect slots_14.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[14].wakeup_ports[3].bits.uop.iq_type[1] \n connect slots_14.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[14].wakeup_ports[3].bits.uop.iq_type[2] \n connect slots_14.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[14].wakeup_ports[3].bits.uop.iq_type[3] \n connect slots_14.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[14].wakeup_ports[3].bits.uop.debug_pc \n connect slots_14.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[14].wakeup_ports[3].bits.uop.is_rvc \n connect slots_14.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[14].wakeup_ports[3].bits.uop.debug_inst \n connect slots_14.io.wakeup_ports[3].bits.uop.inst, issue_slots[14].wakeup_ports[3].bits.uop.inst \n connect slots_14.io.wakeup_ports[3].valid, issue_slots[14].wakeup_ports[3].valid \n connect slots_14.io.squash_grant, issue_slots[14].squash_grant \n connect slots_14.io.clear, issue_slots[14].clear \n connect slots_14.io.kill, issue_slots[14].kill \n connect slots_14.io.brupdate.b2.target_offset, issue_slots[14].brupdate.b2.target_offset \n connect slots_14.io.brupdate.b2.jalr_target, issue_slots[14].brupdate.b2.jalr_target \n connect slots_14.io.brupdate.b2.pc_sel, issue_slots[14].brupdate.b2.pc_sel \n connect slots_14.io.brupdate.b2.cfi_type, issue_slots[14].brupdate.b2.cfi_type \n connect slots_14.io.brupdate.b2.taken, issue_slots[14].brupdate.b2.taken \n connect slots_14.io.brupdate.b2.mispredict, issue_slots[14].brupdate.b2.mispredict \n connect slots_14.io.brupdate.b2.uop.debug_tsrc, issue_slots[14].brupdate.b2.uop.debug_tsrc \n connect slots_14.io.brupdate.b2.uop.debug_fsrc, issue_slots[14].brupdate.b2.uop.debug_fsrc \n connect slots_14.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[14].brupdate.b2.uop.bp_xcpt_if \n connect slots_14.io.brupdate.b2.uop.bp_debug_if, issue_slots[14].brupdate.b2.uop.bp_debug_if \n connect slots_14.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[14].brupdate.b2.uop.xcpt_ma_if \n connect slots_14.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[14].brupdate.b2.uop.xcpt_ae_if \n connect slots_14.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[14].brupdate.b2.uop.xcpt_pf_if \n connect slots_14.io.brupdate.b2.uop.fp_typ, issue_slots[14].brupdate.b2.uop.fp_typ \n connect slots_14.io.brupdate.b2.uop.fp_rm, issue_slots[14].brupdate.b2.uop.fp_rm \n connect slots_14.io.brupdate.b2.uop.fp_val, issue_slots[14].brupdate.b2.uop.fp_val \n connect slots_14.io.brupdate.b2.uop.fcn_op, issue_slots[14].brupdate.b2.uop.fcn_op \n connect slots_14.io.brupdate.b2.uop.fcn_dw, issue_slots[14].brupdate.b2.uop.fcn_dw \n connect slots_14.io.brupdate.b2.uop.frs3_en, issue_slots[14].brupdate.b2.uop.frs3_en \n connect slots_14.io.brupdate.b2.uop.lrs2_rtype, issue_slots[14].brupdate.b2.uop.lrs2_rtype \n connect slots_14.io.brupdate.b2.uop.lrs1_rtype, issue_slots[14].brupdate.b2.uop.lrs1_rtype \n connect slots_14.io.brupdate.b2.uop.dst_rtype, issue_slots[14].brupdate.b2.uop.dst_rtype \n connect slots_14.io.brupdate.b2.uop.lrs3, issue_slots[14].brupdate.b2.uop.lrs3 \n connect slots_14.io.brupdate.b2.uop.lrs2, issue_slots[14].brupdate.b2.uop.lrs2 \n connect slots_14.io.brupdate.b2.uop.lrs1, issue_slots[14].brupdate.b2.uop.lrs1 \n connect slots_14.io.brupdate.b2.uop.ldst, issue_slots[14].brupdate.b2.uop.ldst \n connect slots_14.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[14].brupdate.b2.uop.ldst_is_rs1 \n connect slots_14.io.brupdate.b2.uop.csr_cmd, issue_slots[14].brupdate.b2.uop.csr_cmd \n connect slots_14.io.brupdate.b2.uop.flush_on_commit, issue_slots[14].brupdate.b2.uop.flush_on_commit \n connect slots_14.io.brupdate.b2.uop.is_unique, issue_slots[14].brupdate.b2.uop.is_unique \n connect slots_14.io.brupdate.b2.uop.uses_stq, issue_slots[14].brupdate.b2.uop.uses_stq \n connect slots_14.io.brupdate.b2.uop.uses_ldq, issue_slots[14].brupdate.b2.uop.uses_ldq \n connect slots_14.io.brupdate.b2.uop.mem_signed, issue_slots[14].brupdate.b2.uop.mem_signed \n connect slots_14.io.brupdate.b2.uop.mem_size, issue_slots[14].brupdate.b2.uop.mem_size \n connect slots_14.io.brupdate.b2.uop.mem_cmd, issue_slots[14].brupdate.b2.uop.mem_cmd \n connect slots_14.io.brupdate.b2.uop.exc_cause, issue_slots[14].brupdate.b2.uop.exc_cause \n connect slots_14.io.brupdate.b2.uop.exception, issue_slots[14].brupdate.b2.uop.exception \n connect slots_14.io.brupdate.b2.uop.stale_pdst, issue_slots[14].brupdate.b2.uop.stale_pdst \n connect slots_14.io.brupdate.b2.uop.ppred_busy, issue_slots[14].brupdate.b2.uop.ppred_busy \n connect slots_14.io.brupdate.b2.uop.prs3_busy, issue_slots[14].brupdate.b2.uop.prs3_busy \n connect slots_14.io.brupdate.b2.uop.prs2_busy, issue_slots[14].brupdate.b2.uop.prs2_busy \n connect slots_14.io.brupdate.b2.uop.prs1_busy, issue_slots[14].brupdate.b2.uop.prs1_busy \n connect slots_14.io.brupdate.b2.uop.ppred, issue_slots[14].brupdate.b2.uop.ppred \n connect slots_14.io.brupdate.b2.uop.prs3, issue_slots[14].brupdate.b2.uop.prs3 \n connect slots_14.io.brupdate.b2.uop.prs2, issue_slots[14].brupdate.b2.uop.prs2 \n connect slots_14.io.brupdate.b2.uop.prs1, issue_slots[14].brupdate.b2.uop.prs1 \n connect slots_14.io.brupdate.b2.uop.pdst, issue_slots[14].brupdate.b2.uop.pdst \n connect slots_14.io.brupdate.b2.uop.rxq_idx, issue_slots[14].brupdate.b2.uop.rxq_idx \n connect slots_14.io.brupdate.b2.uop.stq_idx, issue_slots[14].brupdate.b2.uop.stq_idx \n connect slots_14.io.brupdate.b2.uop.ldq_idx, issue_slots[14].brupdate.b2.uop.ldq_idx \n connect slots_14.io.brupdate.b2.uop.rob_idx, issue_slots[14].brupdate.b2.uop.rob_idx \n connect slots_14.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[14].brupdate.b2.uop.fp_ctrl.vec \n connect slots_14.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[14].brupdate.b2.uop.fp_ctrl.wflags \n connect slots_14.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[14].brupdate.b2.uop.fp_ctrl.sqrt \n connect slots_14.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[14].brupdate.b2.uop.fp_ctrl.div \n connect slots_14.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[14].brupdate.b2.uop.fp_ctrl.fma \n connect slots_14.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[14].brupdate.b2.uop.fp_ctrl.fastpipe \n connect slots_14.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[14].brupdate.b2.uop.fp_ctrl.toint \n connect slots_14.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[14].brupdate.b2.uop.fp_ctrl.fromint \n connect slots_14.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[14].brupdate.b2.uop.fp_ctrl.typeTagOut \n connect slots_14.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[14].brupdate.b2.uop.fp_ctrl.typeTagIn \n connect slots_14.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[14].brupdate.b2.uop.fp_ctrl.swap23 \n connect slots_14.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[14].brupdate.b2.uop.fp_ctrl.swap12 \n connect slots_14.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[14].brupdate.b2.uop.fp_ctrl.ren3 \n connect slots_14.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[14].brupdate.b2.uop.fp_ctrl.ren2 \n connect slots_14.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[14].brupdate.b2.uop.fp_ctrl.ren1 \n connect slots_14.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[14].brupdate.b2.uop.fp_ctrl.wen \n connect slots_14.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[14].brupdate.b2.uop.fp_ctrl.ldst \n connect slots_14.io.brupdate.b2.uop.op2_sel, issue_slots[14].brupdate.b2.uop.op2_sel \n connect slots_14.io.brupdate.b2.uop.op1_sel, issue_slots[14].brupdate.b2.uop.op1_sel \n connect slots_14.io.brupdate.b2.uop.imm_packed, issue_slots[14].brupdate.b2.uop.imm_packed \n connect slots_14.io.brupdate.b2.uop.pimm, issue_slots[14].brupdate.b2.uop.pimm \n connect slots_14.io.brupdate.b2.uop.imm_sel, issue_slots[14].brupdate.b2.uop.imm_sel \n connect slots_14.io.brupdate.b2.uop.imm_rename, issue_slots[14].brupdate.b2.uop.imm_rename \n connect slots_14.io.brupdate.b2.uop.taken, issue_slots[14].brupdate.b2.uop.taken \n connect slots_14.io.brupdate.b2.uop.pc_lob, issue_slots[14].brupdate.b2.uop.pc_lob \n connect slots_14.io.brupdate.b2.uop.edge_inst, issue_slots[14].brupdate.b2.uop.edge_inst \n connect slots_14.io.brupdate.b2.uop.ftq_idx, issue_slots[14].brupdate.b2.uop.ftq_idx \n connect slots_14.io.brupdate.b2.uop.is_mov, issue_slots[14].brupdate.b2.uop.is_mov \n connect slots_14.io.brupdate.b2.uop.is_rocc, issue_slots[14].brupdate.b2.uop.is_rocc \n connect slots_14.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[14].brupdate.b2.uop.is_sys_pc2epc \n connect slots_14.io.brupdate.b2.uop.is_eret, issue_slots[14].brupdate.b2.uop.is_eret \n connect slots_14.io.brupdate.b2.uop.is_amo, issue_slots[14].brupdate.b2.uop.is_amo \n connect slots_14.io.brupdate.b2.uop.is_sfence, issue_slots[14].brupdate.b2.uop.is_sfence \n connect slots_14.io.brupdate.b2.uop.is_fencei, issue_slots[14].brupdate.b2.uop.is_fencei \n connect slots_14.io.brupdate.b2.uop.is_fence, issue_slots[14].brupdate.b2.uop.is_fence \n connect slots_14.io.brupdate.b2.uop.is_sfb, issue_slots[14].brupdate.b2.uop.is_sfb \n connect slots_14.io.brupdate.b2.uop.br_type, issue_slots[14].brupdate.b2.uop.br_type \n connect slots_14.io.brupdate.b2.uop.br_tag, issue_slots[14].brupdate.b2.uop.br_tag \n connect slots_14.io.brupdate.b2.uop.br_mask, issue_slots[14].brupdate.b2.uop.br_mask \n connect slots_14.io.brupdate.b2.uop.dis_col_sel, issue_slots[14].brupdate.b2.uop.dis_col_sel \n connect slots_14.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[14].brupdate.b2.uop.iw_p3_bypass_hint \n connect slots_14.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[14].brupdate.b2.uop.iw_p2_bypass_hint \n connect slots_14.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[14].brupdate.b2.uop.iw_p1_bypass_hint \n connect slots_14.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[14].brupdate.b2.uop.iw_p2_speculative_child \n connect slots_14.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[14].brupdate.b2.uop.iw_p1_speculative_child \n connect slots_14.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[14].brupdate.b2.uop.iw_issued_partial_dgen \n connect slots_14.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[14].brupdate.b2.uop.iw_issued_partial_agen \n connect slots_14.io.brupdate.b2.uop.iw_issued, issue_slots[14].brupdate.b2.uop.iw_issued \n connect slots_14.io.brupdate.b2.uop.fu_code[0], issue_slots[14].brupdate.b2.uop.fu_code[0] \n connect slots_14.io.brupdate.b2.uop.fu_code[1], issue_slots[14].brupdate.b2.uop.fu_code[1] \n connect slots_14.io.brupdate.b2.uop.fu_code[2], issue_slots[14].brupdate.b2.uop.fu_code[2] \n connect slots_14.io.brupdate.b2.uop.fu_code[3], issue_slots[14].brupdate.b2.uop.fu_code[3] \n connect slots_14.io.brupdate.b2.uop.fu_code[4], issue_slots[14].brupdate.b2.uop.fu_code[4] \n connect slots_14.io.brupdate.b2.uop.fu_code[5], issue_slots[14].brupdate.b2.uop.fu_code[5] \n connect slots_14.io.brupdate.b2.uop.fu_code[6], issue_slots[14].brupdate.b2.uop.fu_code[6] \n connect slots_14.io.brupdate.b2.uop.fu_code[7], issue_slots[14].brupdate.b2.uop.fu_code[7] \n connect slots_14.io.brupdate.b2.uop.fu_code[8], issue_slots[14].brupdate.b2.uop.fu_code[8] \n connect slots_14.io.brupdate.b2.uop.fu_code[9], issue_slots[14].brupdate.b2.uop.fu_code[9] \n connect slots_14.io.brupdate.b2.uop.iq_type[0], issue_slots[14].brupdate.b2.uop.iq_type[0] \n connect slots_14.io.brupdate.b2.uop.iq_type[1], issue_slots[14].brupdate.b2.uop.iq_type[1] \n connect slots_14.io.brupdate.b2.uop.iq_type[2], issue_slots[14].brupdate.b2.uop.iq_type[2] \n connect slots_14.io.brupdate.b2.uop.iq_type[3], issue_slots[14].brupdate.b2.uop.iq_type[3] \n connect slots_14.io.brupdate.b2.uop.debug_pc, issue_slots[14].brupdate.b2.uop.debug_pc \n connect slots_14.io.brupdate.b2.uop.is_rvc, issue_slots[14].brupdate.b2.uop.is_rvc \n connect slots_14.io.brupdate.b2.uop.debug_inst, issue_slots[14].brupdate.b2.uop.debug_inst \n connect slots_14.io.brupdate.b2.uop.inst, issue_slots[14].brupdate.b2.uop.inst \n connect slots_14.io.brupdate.b1.mispredict_mask, issue_slots[14].brupdate.b1.mispredict_mask \n connect slots_14.io.brupdate.b1.resolve_mask, issue_slots[14].brupdate.b1.resolve_mask \n connect issue_slots[14].out_uop.debug_tsrc, slots_14.io.out_uop.debug_tsrc \n connect issue_slots[14].out_uop.debug_fsrc, slots_14.io.out_uop.debug_fsrc \n connect issue_slots[14].out_uop.bp_xcpt_if, slots_14.io.out_uop.bp_xcpt_if \n connect issue_slots[14].out_uop.bp_debug_if, slots_14.io.out_uop.bp_debug_if \n connect issue_slots[14].out_uop.xcpt_ma_if, slots_14.io.out_uop.xcpt_ma_if \n connect issue_slots[14].out_uop.xcpt_ae_if, slots_14.io.out_uop.xcpt_ae_if \n connect issue_slots[14].out_uop.xcpt_pf_if, slots_14.io.out_uop.xcpt_pf_if \n connect issue_slots[14].out_uop.fp_typ, slots_14.io.out_uop.fp_typ \n connect issue_slots[14].out_uop.fp_rm, slots_14.io.out_uop.fp_rm \n connect issue_slots[14].out_uop.fp_val, slots_14.io.out_uop.fp_val \n connect issue_slots[14].out_uop.fcn_op, slots_14.io.out_uop.fcn_op \n connect issue_slots[14].out_uop.fcn_dw, slots_14.io.out_uop.fcn_dw \n connect issue_slots[14].out_uop.frs3_en, slots_14.io.out_uop.frs3_en \n connect issue_slots[14].out_uop.lrs2_rtype, slots_14.io.out_uop.lrs2_rtype \n connect issue_slots[14].out_uop.lrs1_rtype, slots_14.io.out_uop.lrs1_rtype \n connect issue_slots[14].out_uop.dst_rtype, slots_14.io.out_uop.dst_rtype \n connect issue_slots[14].out_uop.lrs3, slots_14.io.out_uop.lrs3 \n connect issue_slots[14].out_uop.lrs2, slots_14.io.out_uop.lrs2 \n connect issue_slots[14].out_uop.lrs1, slots_14.io.out_uop.lrs1 \n connect issue_slots[14].out_uop.ldst, slots_14.io.out_uop.ldst \n connect issue_slots[14].out_uop.ldst_is_rs1, slots_14.io.out_uop.ldst_is_rs1 \n connect issue_slots[14].out_uop.csr_cmd, slots_14.io.out_uop.csr_cmd \n connect issue_slots[14].out_uop.flush_on_commit, slots_14.io.out_uop.flush_on_commit \n connect issue_slots[14].out_uop.is_unique, slots_14.io.out_uop.is_unique \n connect issue_slots[14].out_uop.uses_stq, slots_14.io.out_uop.uses_stq \n connect issue_slots[14].out_uop.uses_ldq, slots_14.io.out_uop.uses_ldq \n connect issue_slots[14].out_uop.mem_signed, slots_14.io.out_uop.mem_signed \n connect issue_slots[14].out_uop.mem_size, slots_14.io.out_uop.mem_size \n connect issue_slots[14].out_uop.mem_cmd, slots_14.io.out_uop.mem_cmd \n connect issue_slots[14].out_uop.exc_cause, slots_14.io.out_uop.exc_cause \n connect issue_slots[14].out_uop.exception, slots_14.io.out_uop.exception \n connect issue_slots[14].out_uop.stale_pdst, slots_14.io.out_uop.stale_pdst \n connect issue_slots[14].out_uop.ppred_busy, slots_14.io.out_uop.ppred_busy \n connect issue_slots[14].out_uop.prs3_busy, slots_14.io.out_uop.prs3_busy \n connect issue_slots[14].out_uop.prs2_busy, slots_14.io.out_uop.prs2_busy \n connect issue_slots[14].out_uop.prs1_busy, slots_14.io.out_uop.prs1_busy \n connect issue_slots[14].out_uop.ppred, slots_14.io.out_uop.ppred \n connect issue_slots[14].out_uop.prs3, slots_14.io.out_uop.prs3 \n connect issue_slots[14].out_uop.prs2, slots_14.io.out_uop.prs2 \n connect issue_slots[14].out_uop.prs1, slots_14.io.out_uop.prs1 \n connect issue_slots[14].out_uop.pdst, slots_14.io.out_uop.pdst \n connect issue_slots[14].out_uop.rxq_idx, slots_14.io.out_uop.rxq_idx \n connect issue_slots[14].out_uop.stq_idx, slots_14.io.out_uop.stq_idx \n connect issue_slots[14].out_uop.ldq_idx, slots_14.io.out_uop.ldq_idx \n connect issue_slots[14].out_uop.rob_idx, slots_14.io.out_uop.rob_idx \n connect issue_slots[14].out_uop.fp_ctrl.vec, slots_14.io.out_uop.fp_ctrl.vec \n connect issue_slots[14].out_uop.fp_ctrl.wflags, slots_14.io.out_uop.fp_ctrl.wflags \n connect issue_slots[14].out_uop.fp_ctrl.sqrt, slots_14.io.out_uop.fp_ctrl.sqrt \n connect issue_slots[14].out_uop.fp_ctrl.div, slots_14.io.out_uop.fp_ctrl.div \n connect issue_slots[14].out_uop.fp_ctrl.fma, slots_14.io.out_uop.fp_ctrl.fma \n connect issue_slots[14].out_uop.fp_ctrl.fastpipe, slots_14.io.out_uop.fp_ctrl.fastpipe \n connect issue_slots[14].out_uop.fp_ctrl.toint, slots_14.io.out_uop.fp_ctrl.toint \n connect issue_slots[14].out_uop.fp_ctrl.fromint, slots_14.io.out_uop.fp_ctrl.fromint \n connect issue_slots[14].out_uop.fp_ctrl.typeTagOut, slots_14.io.out_uop.fp_ctrl.typeTagOut \n connect issue_slots[14].out_uop.fp_ctrl.typeTagIn, slots_14.io.out_uop.fp_ctrl.typeTagIn \n connect issue_slots[14].out_uop.fp_ctrl.swap23, slots_14.io.out_uop.fp_ctrl.swap23 \n connect issue_slots[14].out_uop.fp_ctrl.swap12, slots_14.io.out_uop.fp_ctrl.swap12 \n connect issue_slots[14].out_uop.fp_ctrl.ren3, slots_14.io.out_uop.fp_ctrl.ren3 \n connect issue_slots[14].out_uop.fp_ctrl.ren2, slots_14.io.out_uop.fp_ctrl.ren2 \n connect issue_slots[14].out_uop.fp_ctrl.ren1, slots_14.io.out_uop.fp_ctrl.ren1 \n connect issue_slots[14].out_uop.fp_ctrl.wen, slots_14.io.out_uop.fp_ctrl.wen \n connect issue_slots[14].out_uop.fp_ctrl.ldst, slots_14.io.out_uop.fp_ctrl.ldst \n connect issue_slots[14].out_uop.op2_sel, slots_14.io.out_uop.op2_sel \n connect issue_slots[14].out_uop.op1_sel, slots_14.io.out_uop.op1_sel \n connect issue_slots[14].out_uop.imm_packed, slots_14.io.out_uop.imm_packed \n connect issue_slots[14].out_uop.pimm, slots_14.io.out_uop.pimm \n connect issue_slots[14].out_uop.imm_sel, slots_14.io.out_uop.imm_sel \n connect issue_slots[14].out_uop.imm_rename, slots_14.io.out_uop.imm_rename \n connect issue_slots[14].out_uop.taken, slots_14.io.out_uop.taken \n connect issue_slots[14].out_uop.pc_lob, slots_14.io.out_uop.pc_lob \n connect issue_slots[14].out_uop.edge_inst, slots_14.io.out_uop.edge_inst \n connect issue_slots[14].out_uop.ftq_idx, slots_14.io.out_uop.ftq_idx \n connect issue_slots[14].out_uop.is_mov, slots_14.io.out_uop.is_mov \n connect issue_slots[14].out_uop.is_rocc, slots_14.io.out_uop.is_rocc \n connect issue_slots[14].out_uop.is_sys_pc2epc, slots_14.io.out_uop.is_sys_pc2epc \n connect issue_slots[14].out_uop.is_eret, slots_14.io.out_uop.is_eret \n connect issue_slots[14].out_uop.is_amo, slots_14.io.out_uop.is_amo \n connect issue_slots[14].out_uop.is_sfence, slots_14.io.out_uop.is_sfence \n connect issue_slots[14].out_uop.is_fencei, slots_14.io.out_uop.is_fencei \n connect issue_slots[14].out_uop.is_fence, slots_14.io.out_uop.is_fence \n connect issue_slots[14].out_uop.is_sfb, slots_14.io.out_uop.is_sfb \n connect issue_slots[14].out_uop.br_type, slots_14.io.out_uop.br_type \n connect issue_slots[14].out_uop.br_tag, slots_14.io.out_uop.br_tag \n connect issue_slots[14].out_uop.br_mask, slots_14.io.out_uop.br_mask \n connect issue_slots[14].out_uop.dis_col_sel, slots_14.io.out_uop.dis_col_sel \n connect issue_slots[14].out_uop.iw_p3_bypass_hint, slots_14.io.out_uop.iw_p3_bypass_hint \n connect issue_slots[14].out_uop.iw_p2_bypass_hint, slots_14.io.out_uop.iw_p2_bypass_hint \n connect issue_slots[14].out_uop.iw_p1_bypass_hint, slots_14.io.out_uop.iw_p1_bypass_hint \n connect issue_slots[14].out_uop.iw_p2_speculative_child, slots_14.io.out_uop.iw_p2_speculative_child \n connect issue_slots[14].out_uop.iw_p1_speculative_child, slots_14.io.out_uop.iw_p1_speculative_child \n connect issue_slots[14].out_uop.iw_issued_partial_dgen, slots_14.io.out_uop.iw_issued_partial_dgen \n connect issue_slots[14].out_uop.iw_issued_partial_agen, slots_14.io.out_uop.iw_issued_partial_agen \n connect issue_slots[14].out_uop.iw_issued, slots_14.io.out_uop.iw_issued \n connect issue_slots[14].out_uop.fu_code[0], slots_14.io.out_uop.fu_code[0] \n connect issue_slots[14].out_uop.fu_code[1], slots_14.io.out_uop.fu_code[1] \n connect issue_slots[14].out_uop.fu_code[2], slots_14.io.out_uop.fu_code[2] \n connect issue_slots[14].out_uop.fu_code[3], slots_14.io.out_uop.fu_code[3] \n connect issue_slots[14].out_uop.fu_code[4], slots_14.io.out_uop.fu_code[4] \n connect issue_slots[14].out_uop.fu_code[5], slots_14.io.out_uop.fu_code[5] \n connect issue_slots[14].out_uop.fu_code[6], slots_14.io.out_uop.fu_code[6] \n connect issue_slots[14].out_uop.fu_code[7], slots_14.io.out_uop.fu_code[7] \n connect issue_slots[14].out_uop.fu_code[8], slots_14.io.out_uop.fu_code[8] \n connect issue_slots[14].out_uop.fu_code[9], slots_14.io.out_uop.fu_code[9] \n connect issue_slots[14].out_uop.iq_type[0], slots_14.io.out_uop.iq_type[0] \n connect issue_slots[14].out_uop.iq_type[1], slots_14.io.out_uop.iq_type[1] \n connect issue_slots[14].out_uop.iq_type[2], slots_14.io.out_uop.iq_type[2] \n connect issue_slots[14].out_uop.iq_type[3], slots_14.io.out_uop.iq_type[3] \n connect issue_slots[14].out_uop.debug_pc, slots_14.io.out_uop.debug_pc \n connect issue_slots[14].out_uop.is_rvc, slots_14.io.out_uop.is_rvc \n connect issue_slots[14].out_uop.debug_inst, slots_14.io.out_uop.debug_inst \n connect issue_slots[14].out_uop.inst, slots_14.io.out_uop.inst \n connect slots_14.io.in_uop.bits.debug_tsrc, issue_slots[14].in_uop.bits.debug_tsrc \n connect slots_14.io.in_uop.bits.debug_fsrc, issue_slots[14].in_uop.bits.debug_fsrc \n connect slots_14.io.in_uop.bits.bp_xcpt_if, issue_slots[14].in_uop.bits.bp_xcpt_if \n connect slots_14.io.in_uop.bits.bp_debug_if, issue_slots[14].in_uop.bits.bp_debug_if \n connect slots_14.io.in_uop.bits.xcpt_ma_if, issue_slots[14].in_uop.bits.xcpt_ma_if \n connect slots_14.io.in_uop.bits.xcpt_ae_if, issue_slots[14].in_uop.bits.xcpt_ae_if \n connect slots_14.io.in_uop.bits.xcpt_pf_if, issue_slots[14].in_uop.bits.xcpt_pf_if \n connect slots_14.io.in_uop.bits.fp_typ, issue_slots[14].in_uop.bits.fp_typ \n connect slots_14.io.in_uop.bits.fp_rm, issue_slots[14].in_uop.bits.fp_rm \n connect slots_14.io.in_uop.bits.fp_val, issue_slots[14].in_uop.bits.fp_val \n connect slots_14.io.in_uop.bits.fcn_op, issue_slots[14].in_uop.bits.fcn_op \n connect slots_14.io.in_uop.bits.fcn_dw, issue_slots[14].in_uop.bits.fcn_dw \n connect slots_14.io.in_uop.bits.frs3_en, issue_slots[14].in_uop.bits.frs3_en \n connect slots_14.io.in_uop.bits.lrs2_rtype, issue_slots[14].in_uop.bits.lrs2_rtype \n connect slots_14.io.in_uop.bits.lrs1_rtype, issue_slots[14].in_uop.bits.lrs1_rtype \n connect slots_14.io.in_uop.bits.dst_rtype, issue_slots[14].in_uop.bits.dst_rtype \n connect slots_14.io.in_uop.bits.lrs3, issue_slots[14].in_uop.bits.lrs3 \n connect slots_14.io.in_uop.bits.lrs2, issue_slots[14].in_uop.bits.lrs2 \n connect slots_14.io.in_uop.bits.lrs1, issue_slots[14].in_uop.bits.lrs1 \n connect slots_14.io.in_uop.bits.ldst, issue_slots[14].in_uop.bits.ldst \n connect slots_14.io.in_uop.bits.ldst_is_rs1, issue_slots[14].in_uop.bits.ldst_is_rs1 \n connect slots_14.io.in_uop.bits.csr_cmd, issue_slots[14].in_uop.bits.csr_cmd \n connect slots_14.io.in_uop.bits.flush_on_commit, issue_slots[14].in_uop.bits.flush_on_commit \n connect slots_14.io.in_uop.bits.is_unique, issue_slots[14].in_uop.bits.is_unique \n connect slots_14.io.in_uop.bits.uses_stq, issue_slots[14].in_uop.bits.uses_stq \n connect slots_14.io.in_uop.bits.uses_ldq, issue_slots[14].in_uop.bits.uses_ldq \n connect slots_14.io.in_uop.bits.mem_signed, issue_slots[14].in_uop.bits.mem_signed \n connect slots_14.io.in_uop.bits.mem_size, issue_slots[14].in_uop.bits.mem_size \n connect slots_14.io.in_uop.bits.mem_cmd, issue_slots[14].in_uop.bits.mem_cmd \n connect slots_14.io.in_uop.bits.exc_cause, issue_slots[14].in_uop.bits.exc_cause \n connect slots_14.io.in_uop.bits.exception, issue_slots[14].in_uop.bits.exception \n connect slots_14.io.in_uop.bits.stale_pdst, issue_slots[14].in_uop.bits.stale_pdst \n connect slots_14.io.in_uop.bits.ppred_busy, issue_slots[14].in_uop.bits.ppred_busy \n connect slots_14.io.in_uop.bits.prs3_busy, issue_slots[14].in_uop.bits.prs3_busy \n connect slots_14.io.in_uop.bits.prs2_busy, issue_slots[14].in_uop.bits.prs2_busy \n connect slots_14.io.in_uop.bits.prs1_busy, issue_slots[14].in_uop.bits.prs1_busy \n connect slots_14.io.in_uop.bits.ppred, issue_slots[14].in_uop.bits.ppred \n connect slots_14.io.in_uop.bits.prs3, issue_slots[14].in_uop.bits.prs3 \n connect slots_14.io.in_uop.bits.prs2, issue_slots[14].in_uop.bits.prs2 \n connect slots_14.io.in_uop.bits.prs1, issue_slots[14].in_uop.bits.prs1 \n connect slots_14.io.in_uop.bits.pdst, issue_slots[14].in_uop.bits.pdst \n connect slots_14.io.in_uop.bits.rxq_idx, issue_slots[14].in_uop.bits.rxq_idx \n connect slots_14.io.in_uop.bits.stq_idx, issue_slots[14].in_uop.bits.stq_idx \n connect slots_14.io.in_uop.bits.ldq_idx, issue_slots[14].in_uop.bits.ldq_idx \n connect slots_14.io.in_uop.bits.rob_idx, issue_slots[14].in_uop.bits.rob_idx \n connect slots_14.io.in_uop.bits.fp_ctrl.vec, issue_slots[14].in_uop.bits.fp_ctrl.vec \n connect slots_14.io.in_uop.bits.fp_ctrl.wflags, issue_slots[14].in_uop.bits.fp_ctrl.wflags \n connect slots_14.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[14].in_uop.bits.fp_ctrl.sqrt \n connect slots_14.io.in_uop.bits.fp_ctrl.div, issue_slots[14].in_uop.bits.fp_ctrl.div \n connect slots_14.io.in_uop.bits.fp_ctrl.fma, issue_slots[14].in_uop.bits.fp_ctrl.fma \n connect slots_14.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[14].in_uop.bits.fp_ctrl.fastpipe \n connect slots_14.io.in_uop.bits.fp_ctrl.toint, issue_slots[14].in_uop.bits.fp_ctrl.toint \n connect slots_14.io.in_uop.bits.fp_ctrl.fromint, issue_slots[14].in_uop.bits.fp_ctrl.fromint \n connect slots_14.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[14].in_uop.bits.fp_ctrl.typeTagOut \n connect slots_14.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[14].in_uop.bits.fp_ctrl.typeTagIn \n connect slots_14.io.in_uop.bits.fp_ctrl.swap23, issue_slots[14].in_uop.bits.fp_ctrl.swap23 \n connect slots_14.io.in_uop.bits.fp_ctrl.swap12, issue_slots[14].in_uop.bits.fp_ctrl.swap12 \n connect slots_14.io.in_uop.bits.fp_ctrl.ren3, issue_slots[14].in_uop.bits.fp_ctrl.ren3 \n connect slots_14.io.in_uop.bits.fp_ctrl.ren2, issue_slots[14].in_uop.bits.fp_ctrl.ren2 \n connect slots_14.io.in_uop.bits.fp_ctrl.ren1, issue_slots[14].in_uop.bits.fp_ctrl.ren1 \n connect slots_14.io.in_uop.bits.fp_ctrl.wen, issue_slots[14].in_uop.bits.fp_ctrl.wen \n connect slots_14.io.in_uop.bits.fp_ctrl.ldst, issue_slots[14].in_uop.bits.fp_ctrl.ldst \n connect slots_14.io.in_uop.bits.op2_sel, issue_slots[14].in_uop.bits.op2_sel \n connect slots_14.io.in_uop.bits.op1_sel, issue_slots[14].in_uop.bits.op1_sel \n connect slots_14.io.in_uop.bits.imm_packed, issue_slots[14].in_uop.bits.imm_packed \n connect slots_14.io.in_uop.bits.pimm, issue_slots[14].in_uop.bits.pimm \n connect slots_14.io.in_uop.bits.imm_sel, issue_slots[14].in_uop.bits.imm_sel \n connect slots_14.io.in_uop.bits.imm_rename, issue_slots[14].in_uop.bits.imm_rename \n connect slots_14.io.in_uop.bits.taken, issue_slots[14].in_uop.bits.taken \n connect slots_14.io.in_uop.bits.pc_lob, issue_slots[14].in_uop.bits.pc_lob \n connect slots_14.io.in_uop.bits.edge_inst, issue_slots[14].in_uop.bits.edge_inst \n connect slots_14.io.in_uop.bits.ftq_idx, issue_slots[14].in_uop.bits.ftq_idx \n connect slots_14.io.in_uop.bits.is_mov, issue_slots[14].in_uop.bits.is_mov \n connect slots_14.io.in_uop.bits.is_rocc, issue_slots[14].in_uop.bits.is_rocc \n connect slots_14.io.in_uop.bits.is_sys_pc2epc, issue_slots[14].in_uop.bits.is_sys_pc2epc \n connect slots_14.io.in_uop.bits.is_eret, issue_slots[14].in_uop.bits.is_eret \n connect slots_14.io.in_uop.bits.is_amo, issue_slots[14].in_uop.bits.is_amo \n connect slots_14.io.in_uop.bits.is_sfence, issue_slots[14].in_uop.bits.is_sfence \n connect slots_14.io.in_uop.bits.is_fencei, issue_slots[14].in_uop.bits.is_fencei \n connect slots_14.io.in_uop.bits.is_fence, issue_slots[14].in_uop.bits.is_fence \n connect slots_14.io.in_uop.bits.is_sfb, issue_slots[14].in_uop.bits.is_sfb \n connect slots_14.io.in_uop.bits.br_type, issue_slots[14].in_uop.bits.br_type \n connect slots_14.io.in_uop.bits.br_tag, issue_slots[14].in_uop.bits.br_tag \n connect slots_14.io.in_uop.bits.br_mask, issue_slots[14].in_uop.bits.br_mask \n connect slots_14.io.in_uop.bits.dis_col_sel, issue_slots[14].in_uop.bits.dis_col_sel \n connect slots_14.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[14].in_uop.bits.iw_p3_bypass_hint \n connect slots_14.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[14].in_uop.bits.iw_p2_bypass_hint \n connect slots_14.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[14].in_uop.bits.iw_p1_bypass_hint \n connect slots_14.io.in_uop.bits.iw_p2_speculative_child, issue_slots[14].in_uop.bits.iw_p2_speculative_child \n connect slots_14.io.in_uop.bits.iw_p1_speculative_child, issue_slots[14].in_uop.bits.iw_p1_speculative_child \n connect slots_14.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[14].in_uop.bits.iw_issued_partial_dgen \n connect slots_14.io.in_uop.bits.iw_issued_partial_agen, issue_slots[14].in_uop.bits.iw_issued_partial_agen \n connect slots_14.io.in_uop.bits.iw_issued, issue_slots[14].in_uop.bits.iw_issued \n connect slots_14.io.in_uop.bits.fu_code[0], issue_slots[14].in_uop.bits.fu_code[0] \n connect slots_14.io.in_uop.bits.fu_code[1], issue_slots[14].in_uop.bits.fu_code[1] \n connect slots_14.io.in_uop.bits.fu_code[2], issue_slots[14].in_uop.bits.fu_code[2] \n connect slots_14.io.in_uop.bits.fu_code[3], issue_slots[14].in_uop.bits.fu_code[3] \n connect slots_14.io.in_uop.bits.fu_code[4], issue_slots[14].in_uop.bits.fu_code[4] \n connect slots_14.io.in_uop.bits.fu_code[5], issue_slots[14].in_uop.bits.fu_code[5] \n connect slots_14.io.in_uop.bits.fu_code[6], issue_slots[14].in_uop.bits.fu_code[6] \n connect slots_14.io.in_uop.bits.fu_code[7], issue_slots[14].in_uop.bits.fu_code[7] \n connect slots_14.io.in_uop.bits.fu_code[8], issue_slots[14].in_uop.bits.fu_code[8] \n connect slots_14.io.in_uop.bits.fu_code[9], issue_slots[14].in_uop.bits.fu_code[9] \n connect slots_14.io.in_uop.bits.iq_type[0], issue_slots[14].in_uop.bits.iq_type[0] \n connect slots_14.io.in_uop.bits.iq_type[1], issue_slots[14].in_uop.bits.iq_type[1] \n connect slots_14.io.in_uop.bits.iq_type[2], issue_slots[14].in_uop.bits.iq_type[2] \n connect slots_14.io.in_uop.bits.iq_type[3], issue_slots[14].in_uop.bits.iq_type[3] \n connect slots_14.io.in_uop.bits.debug_pc, issue_slots[14].in_uop.bits.debug_pc \n connect slots_14.io.in_uop.bits.is_rvc, issue_slots[14].in_uop.bits.is_rvc \n connect slots_14.io.in_uop.bits.debug_inst, issue_slots[14].in_uop.bits.debug_inst \n connect slots_14.io.in_uop.bits.inst, issue_slots[14].in_uop.bits.inst \n connect slots_14.io.in_uop.valid, issue_slots[14].in_uop.valid \n connect issue_slots[14].iss_uop.debug_tsrc, slots_14.io.iss_uop.debug_tsrc \n connect issue_slots[14].iss_uop.debug_fsrc, slots_14.io.iss_uop.debug_fsrc \n connect issue_slots[14].iss_uop.bp_xcpt_if, slots_14.io.iss_uop.bp_xcpt_if \n connect issue_slots[14].iss_uop.bp_debug_if, slots_14.io.iss_uop.bp_debug_if \n connect issue_slots[14].iss_uop.xcpt_ma_if, slots_14.io.iss_uop.xcpt_ma_if \n connect issue_slots[14].iss_uop.xcpt_ae_if, slots_14.io.iss_uop.xcpt_ae_if \n connect issue_slots[14].iss_uop.xcpt_pf_if, slots_14.io.iss_uop.xcpt_pf_if \n connect issue_slots[14].iss_uop.fp_typ, slots_14.io.iss_uop.fp_typ \n connect issue_slots[14].iss_uop.fp_rm, slots_14.io.iss_uop.fp_rm \n connect issue_slots[14].iss_uop.fp_val, slots_14.io.iss_uop.fp_val \n connect issue_slots[14].iss_uop.fcn_op, slots_14.io.iss_uop.fcn_op \n connect issue_slots[14].iss_uop.fcn_dw, slots_14.io.iss_uop.fcn_dw \n connect issue_slots[14].iss_uop.frs3_en, slots_14.io.iss_uop.frs3_en \n connect issue_slots[14].iss_uop.lrs2_rtype, slots_14.io.iss_uop.lrs2_rtype \n connect issue_slots[14].iss_uop.lrs1_rtype, slots_14.io.iss_uop.lrs1_rtype \n connect issue_slots[14].iss_uop.dst_rtype, slots_14.io.iss_uop.dst_rtype \n connect issue_slots[14].iss_uop.lrs3, slots_14.io.iss_uop.lrs3 \n connect issue_slots[14].iss_uop.lrs2, slots_14.io.iss_uop.lrs2 \n connect issue_slots[14].iss_uop.lrs1, slots_14.io.iss_uop.lrs1 \n connect issue_slots[14].iss_uop.ldst, slots_14.io.iss_uop.ldst \n connect issue_slots[14].iss_uop.ldst_is_rs1, slots_14.io.iss_uop.ldst_is_rs1 \n connect issue_slots[14].iss_uop.csr_cmd, slots_14.io.iss_uop.csr_cmd \n connect issue_slots[14].iss_uop.flush_on_commit, slots_14.io.iss_uop.flush_on_commit \n connect issue_slots[14].iss_uop.is_unique, slots_14.io.iss_uop.is_unique \n connect issue_slots[14].iss_uop.uses_stq, slots_14.io.iss_uop.uses_stq \n connect issue_slots[14].iss_uop.uses_ldq, slots_14.io.iss_uop.uses_ldq \n connect issue_slots[14].iss_uop.mem_signed, slots_14.io.iss_uop.mem_signed \n connect issue_slots[14].iss_uop.mem_size, slots_14.io.iss_uop.mem_size \n connect issue_slots[14].iss_uop.mem_cmd, slots_14.io.iss_uop.mem_cmd \n connect issue_slots[14].iss_uop.exc_cause, slots_14.io.iss_uop.exc_cause \n connect issue_slots[14].iss_uop.exception, slots_14.io.iss_uop.exception \n connect issue_slots[14].iss_uop.stale_pdst, slots_14.io.iss_uop.stale_pdst \n connect issue_slots[14].iss_uop.ppred_busy, slots_14.io.iss_uop.ppred_busy \n connect issue_slots[14].iss_uop.prs3_busy, slots_14.io.iss_uop.prs3_busy \n connect issue_slots[14].iss_uop.prs2_busy, slots_14.io.iss_uop.prs2_busy \n connect issue_slots[14].iss_uop.prs1_busy, slots_14.io.iss_uop.prs1_busy \n connect issue_slots[14].iss_uop.ppred, slots_14.io.iss_uop.ppred \n connect issue_slots[14].iss_uop.prs3, slots_14.io.iss_uop.prs3 \n connect issue_slots[14].iss_uop.prs2, slots_14.io.iss_uop.prs2 \n connect issue_slots[14].iss_uop.prs1, slots_14.io.iss_uop.prs1 \n connect issue_slots[14].iss_uop.pdst, slots_14.io.iss_uop.pdst \n connect issue_slots[14].iss_uop.rxq_idx, slots_14.io.iss_uop.rxq_idx \n connect issue_slots[14].iss_uop.stq_idx, slots_14.io.iss_uop.stq_idx \n connect issue_slots[14].iss_uop.ldq_idx, slots_14.io.iss_uop.ldq_idx \n connect issue_slots[14].iss_uop.rob_idx, slots_14.io.iss_uop.rob_idx \n connect issue_slots[14].iss_uop.fp_ctrl.vec, slots_14.io.iss_uop.fp_ctrl.vec \n connect issue_slots[14].iss_uop.fp_ctrl.wflags, slots_14.io.iss_uop.fp_ctrl.wflags \n connect issue_slots[14].iss_uop.fp_ctrl.sqrt, slots_14.io.iss_uop.fp_ctrl.sqrt \n connect issue_slots[14].iss_uop.fp_ctrl.div, slots_14.io.iss_uop.fp_ctrl.div \n connect issue_slots[14].iss_uop.fp_ctrl.fma, slots_14.io.iss_uop.fp_ctrl.fma \n connect issue_slots[14].iss_uop.fp_ctrl.fastpipe, slots_14.io.iss_uop.fp_ctrl.fastpipe \n connect issue_slots[14].iss_uop.fp_ctrl.toint, slots_14.io.iss_uop.fp_ctrl.toint \n connect issue_slots[14].iss_uop.fp_ctrl.fromint, slots_14.io.iss_uop.fp_ctrl.fromint \n connect issue_slots[14].iss_uop.fp_ctrl.typeTagOut, slots_14.io.iss_uop.fp_ctrl.typeTagOut \n connect issue_slots[14].iss_uop.fp_ctrl.typeTagIn, slots_14.io.iss_uop.fp_ctrl.typeTagIn \n connect issue_slots[14].iss_uop.fp_ctrl.swap23, slots_14.io.iss_uop.fp_ctrl.swap23 \n connect issue_slots[14].iss_uop.fp_ctrl.swap12, slots_14.io.iss_uop.fp_ctrl.swap12 \n connect issue_slots[14].iss_uop.fp_ctrl.ren3, slots_14.io.iss_uop.fp_ctrl.ren3 \n connect issue_slots[14].iss_uop.fp_ctrl.ren2, slots_14.io.iss_uop.fp_ctrl.ren2 \n connect issue_slots[14].iss_uop.fp_ctrl.ren1, slots_14.io.iss_uop.fp_ctrl.ren1 \n connect issue_slots[14].iss_uop.fp_ctrl.wen, slots_14.io.iss_uop.fp_ctrl.wen \n connect issue_slots[14].iss_uop.fp_ctrl.ldst, slots_14.io.iss_uop.fp_ctrl.ldst \n connect issue_slots[14].iss_uop.op2_sel, slots_14.io.iss_uop.op2_sel \n connect issue_slots[14].iss_uop.op1_sel, slots_14.io.iss_uop.op1_sel \n connect issue_slots[14].iss_uop.imm_packed, slots_14.io.iss_uop.imm_packed \n connect issue_slots[14].iss_uop.pimm, slots_14.io.iss_uop.pimm \n connect issue_slots[14].iss_uop.imm_sel, slots_14.io.iss_uop.imm_sel \n connect issue_slots[14].iss_uop.imm_rename, slots_14.io.iss_uop.imm_rename \n connect issue_slots[14].iss_uop.taken, slots_14.io.iss_uop.taken \n connect issue_slots[14].iss_uop.pc_lob, slots_14.io.iss_uop.pc_lob \n connect issue_slots[14].iss_uop.edge_inst, slots_14.io.iss_uop.edge_inst \n connect issue_slots[14].iss_uop.ftq_idx, slots_14.io.iss_uop.ftq_idx \n connect issue_slots[14].iss_uop.is_mov, slots_14.io.iss_uop.is_mov \n connect issue_slots[14].iss_uop.is_rocc, slots_14.io.iss_uop.is_rocc \n connect issue_slots[14].iss_uop.is_sys_pc2epc, slots_14.io.iss_uop.is_sys_pc2epc \n connect issue_slots[14].iss_uop.is_eret, slots_14.io.iss_uop.is_eret \n connect issue_slots[14].iss_uop.is_amo, slots_14.io.iss_uop.is_amo \n connect issue_slots[14].iss_uop.is_sfence, slots_14.io.iss_uop.is_sfence \n connect issue_slots[14].iss_uop.is_fencei, slots_14.io.iss_uop.is_fencei \n connect issue_slots[14].iss_uop.is_fence, slots_14.io.iss_uop.is_fence \n connect issue_slots[14].iss_uop.is_sfb, slots_14.io.iss_uop.is_sfb \n connect issue_slots[14].iss_uop.br_type, slots_14.io.iss_uop.br_type \n connect issue_slots[14].iss_uop.br_tag, slots_14.io.iss_uop.br_tag \n connect issue_slots[14].iss_uop.br_mask, slots_14.io.iss_uop.br_mask \n connect issue_slots[14].iss_uop.dis_col_sel, slots_14.io.iss_uop.dis_col_sel \n connect issue_slots[14].iss_uop.iw_p3_bypass_hint, slots_14.io.iss_uop.iw_p3_bypass_hint \n connect issue_slots[14].iss_uop.iw_p2_bypass_hint, slots_14.io.iss_uop.iw_p2_bypass_hint \n connect issue_slots[14].iss_uop.iw_p1_bypass_hint, slots_14.io.iss_uop.iw_p1_bypass_hint \n connect issue_slots[14].iss_uop.iw_p2_speculative_child, slots_14.io.iss_uop.iw_p2_speculative_child \n connect issue_slots[14].iss_uop.iw_p1_speculative_child, slots_14.io.iss_uop.iw_p1_speculative_child \n connect issue_slots[14].iss_uop.iw_issued_partial_dgen, slots_14.io.iss_uop.iw_issued_partial_dgen \n connect issue_slots[14].iss_uop.iw_issued_partial_agen, slots_14.io.iss_uop.iw_issued_partial_agen \n connect issue_slots[14].iss_uop.iw_issued, slots_14.io.iss_uop.iw_issued \n connect issue_slots[14].iss_uop.fu_code[0], slots_14.io.iss_uop.fu_code[0] \n connect issue_slots[14].iss_uop.fu_code[1], slots_14.io.iss_uop.fu_code[1] \n connect issue_slots[14].iss_uop.fu_code[2], slots_14.io.iss_uop.fu_code[2] \n connect issue_slots[14].iss_uop.fu_code[3], slots_14.io.iss_uop.fu_code[3] \n connect issue_slots[14].iss_uop.fu_code[4], slots_14.io.iss_uop.fu_code[4] \n connect issue_slots[14].iss_uop.fu_code[5], slots_14.io.iss_uop.fu_code[5] \n connect issue_slots[14].iss_uop.fu_code[6], slots_14.io.iss_uop.fu_code[6] \n connect issue_slots[14].iss_uop.fu_code[7], slots_14.io.iss_uop.fu_code[7] \n connect issue_slots[14].iss_uop.fu_code[8], slots_14.io.iss_uop.fu_code[8] \n connect issue_slots[14].iss_uop.fu_code[9], slots_14.io.iss_uop.fu_code[9] \n connect issue_slots[14].iss_uop.iq_type[0], slots_14.io.iss_uop.iq_type[0] \n connect issue_slots[14].iss_uop.iq_type[1], slots_14.io.iss_uop.iq_type[1] \n connect issue_slots[14].iss_uop.iq_type[2], slots_14.io.iss_uop.iq_type[2] \n connect issue_slots[14].iss_uop.iq_type[3], slots_14.io.iss_uop.iq_type[3] \n connect issue_slots[14].iss_uop.debug_pc, slots_14.io.iss_uop.debug_pc \n connect issue_slots[14].iss_uop.is_rvc, slots_14.io.iss_uop.is_rvc \n connect issue_slots[14].iss_uop.debug_inst, slots_14.io.iss_uop.debug_inst \n connect issue_slots[14].iss_uop.inst, slots_14.io.iss_uop.inst \n connect slots_14.io.grant, issue_slots[14].grant \n connect issue_slots[14].request, slots_14.io.request \n connect issue_slots[14].will_be_valid, slots_14.io.will_be_valid \n connect issue_slots[14].valid, slots_14.io.valid \n connect slots_15.io.child_rebusys, issue_slots[15].child_rebusys \n connect slots_15.io.pred_wakeup_port.bits, issue_slots[15].pred_wakeup_port.bits \n connect slots_15.io.pred_wakeup_port.valid, issue_slots[15].pred_wakeup_port.valid \n connect slots_15.io.wakeup_ports[0].bits.rebusy, issue_slots[15].wakeup_ports[0].bits.rebusy \n connect slots_15.io.wakeup_ports[0].bits.speculative_mask, issue_slots[15].wakeup_ports[0].bits.speculative_mask \n connect slots_15.io.wakeup_ports[0].bits.bypassable, issue_slots[15].wakeup_ports[0].bits.bypassable \n connect slots_15.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[15].wakeup_ports[0].bits.uop.debug_tsrc \n connect slots_15.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[15].wakeup_ports[0].bits.uop.debug_fsrc \n connect slots_15.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[15].wakeup_ports[0].bits.uop.bp_xcpt_if \n connect slots_15.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[15].wakeup_ports[0].bits.uop.bp_debug_if \n connect slots_15.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[15].wakeup_ports[0].bits.uop.xcpt_ma_if \n connect slots_15.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[15].wakeup_ports[0].bits.uop.xcpt_ae_if \n connect slots_15.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[15].wakeup_ports[0].bits.uop.xcpt_pf_if \n connect slots_15.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[15].wakeup_ports[0].bits.uop.fp_typ \n connect slots_15.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[15].wakeup_ports[0].bits.uop.fp_rm \n connect slots_15.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[15].wakeup_ports[0].bits.uop.fp_val \n connect slots_15.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[15].wakeup_ports[0].bits.uop.fcn_op \n connect slots_15.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[15].wakeup_ports[0].bits.uop.fcn_dw \n connect slots_15.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[15].wakeup_ports[0].bits.uop.frs3_en \n connect slots_15.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[15].wakeup_ports[0].bits.uop.lrs2_rtype \n connect slots_15.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[15].wakeup_ports[0].bits.uop.lrs1_rtype \n connect slots_15.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[15].wakeup_ports[0].bits.uop.dst_rtype \n connect slots_15.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[15].wakeup_ports[0].bits.uop.lrs3 \n connect slots_15.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[15].wakeup_ports[0].bits.uop.lrs2 \n connect slots_15.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[15].wakeup_ports[0].bits.uop.lrs1 \n connect slots_15.io.wakeup_ports[0].bits.uop.ldst, issue_slots[15].wakeup_ports[0].bits.uop.ldst \n connect slots_15.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[15].wakeup_ports[0].bits.uop.ldst_is_rs1 \n connect slots_15.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[15].wakeup_ports[0].bits.uop.csr_cmd \n connect slots_15.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[15].wakeup_ports[0].bits.uop.flush_on_commit \n connect slots_15.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[15].wakeup_ports[0].bits.uop.is_unique \n connect slots_15.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[15].wakeup_ports[0].bits.uop.uses_stq \n connect slots_15.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[15].wakeup_ports[0].bits.uop.uses_ldq \n connect slots_15.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[15].wakeup_ports[0].bits.uop.mem_signed \n connect slots_15.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[15].wakeup_ports[0].bits.uop.mem_size \n connect slots_15.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[15].wakeup_ports[0].bits.uop.mem_cmd \n connect slots_15.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[15].wakeup_ports[0].bits.uop.exc_cause \n connect slots_15.io.wakeup_ports[0].bits.uop.exception, issue_slots[15].wakeup_ports[0].bits.uop.exception \n connect slots_15.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[15].wakeup_ports[0].bits.uop.stale_pdst \n connect slots_15.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[15].wakeup_ports[0].bits.uop.ppred_busy \n connect slots_15.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[15].wakeup_ports[0].bits.uop.prs3_busy \n connect slots_15.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[15].wakeup_ports[0].bits.uop.prs2_busy \n connect slots_15.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[15].wakeup_ports[0].bits.uop.prs1_busy \n connect slots_15.io.wakeup_ports[0].bits.uop.ppred, issue_slots[15].wakeup_ports[0].bits.uop.ppred \n connect slots_15.io.wakeup_ports[0].bits.uop.prs3, issue_slots[15].wakeup_ports[0].bits.uop.prs3 \n connect slots_15.io.wakeup_ports[0].bits.uop.prs2, issue_slots[15].wakeup_ports[0].bits.uop.prs2 \n connect slots_15.io.wakeup_ports[0].bits.uop.prs1, issue_slots[15].wakeup_ports[0].bits.uop.prs1 \n connect slots_15.io.wakeup_ports[0].bits.uop.pdst, issue_slots[15].wakeup_ports[0].bits.uop.pdst \n connect slots_15.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[15].wakeup_ports[0].bits.uop.rxq_idx \n connect slots_15.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[15].wakeup_ports[0].bits.uop.stq_idx \n connect slots_15.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[15].wakeup_ports[0].bits.uop.ldq_idx \n connect slots_15.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[15].wakeup_ports[0].bits.uop.rob_idx \n connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.vec \n connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.wflags \n connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.sqrt \n connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.div \n connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.fma \n connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe \n connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.toint \n connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.fromint \n connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut \n connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn \n connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.swap23 \n connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.swap12 \n connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.ren3 \n connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.ren2 \n connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.ren1 \n connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.wen \n connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.ldst \n connect slots_15.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[15].wakeup_ports[0].bits.uop.op2_sel \n connect slots_15.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[15].wakeup_ports[0].bits.uop.op1_sel \n connect slots_15.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[15].wakeup_ports[0].bits.uop.imm_packed \n connect slots_15.io.wakeup_ports[0].bits.uop.pimm, issue_slots[15].wakeup_ports[0].bits.uop.pimm \n connect slots_15.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[15].wakeup_ports[0].bits.uop.imm_sel \n connect slots_15.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[15].wakeup_ports[0].bits.uop.imm_rename \n connect slots_15.io.wakeup_ports[0].bits.uop.taken, issue_slots[15].wakeup_ports[0].bits.uop.taken \n connect slots_15.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[15].wakeup_ports[0].bits.uop.pc_lob \n connect slots_15.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[15].wakeup_ports[0].bits.uop.edge_inst \n connect slots_15.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[15].wakeup_ports[0].bits.uop.ftq_idx \n connect slots_15.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[15].wakeup_ports[0].bits.uop.is_mov \n connect slots_15.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[15].wakeup_ports[0].bits.uop.is_rocc \n connect slots_15.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[15].wakeup_ports[0].bits.uop.is_sys_pc2epc \n connect slots_15.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[15].wakeup_ports[0].bits.uop.is_eret \n connect slots_15.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[15].wakeup_ports[0].bits.uop.is_amo \n connect slots_15.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[15].wakeup_ports[0].bits.uop.is_sfence \n connect slots_15.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[15].wakeup_ports[0].bits.uop.is_fencei \n connect slots_15.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[15].wakeup_ports[0].bits.uop.is_fence \n connect slots_15.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[15].wakeup_ports[0].bits.uop.is_sfb \n connect slots_15.io.wakeup_ports[0].bits.uop.br_type, issue_slots[15].wakeup_ports[0].bits.uop.br_type \n connect slots_15.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[15].wakeup_ports[0].bits.uop.br_tag \n connect slots_15.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[15].wakeup_ports[0].bits.uop.br_mask \n connect slots_15.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[15].wakeup_ports[0].bits.uop.dis_col_sel \n connect slots_15.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[15].wakeup_ports[0].bits.uop.iw_p3_bypass_hint \n connect slots_15.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[15].wakeup_ports[0].bits.uop.iw_p2_bypass_hint \n connect slots_15.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[15].wakeup_ports[0].bits.uop.iw_p1_bypass_hint \n connect slots_15.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[15].wakeup_ports[0].bits.uop.iw_p2_speculative_child \n connect slots_15.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[15].wakeup_ports[0].bits.uop.iw_p1_speculative_child \n connect slots_15.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[15].wakeup_ports[0].bits.uop.iw_issued_partial_dgen \n connect slots_15.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[15].wakeup_ports[0].bits.uop.iw_issued_partial_agen \n connect slots_15.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[15].wakeup_ports[0].bits.uop.iw_issued \n connect slots_15.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[15].wakeup_ports[0].bits.uop.fu_code[0] \n connect slots_15.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[15].wakeup_ports[0].bits.uop.fu_code[1] \n connect slots_15.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[15].wakeup_ports[0].bits.uop.fu_code[2] \n connect slots_15.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[15].wakeup_ports[0].bits.uop.fu_code[3] \n connect slots_15.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[15].wakeup_ports[0].bits.uop.fu_code[4] \n connect slots_15.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[15].wakeup_ports[0].bits.uop.fu_code[5] \n connect slots_15.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[15].wakeup_ports[0].bits.uop.fu_code[6] \n connect slots_15.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[15].wakeup_ports[0].bits.uop.fu_code[7] \n connect slots_15.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[15].wakeup_ports[0].bits.uop.fu_code[8] \n connect slots_15.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[15].wakeup_ports[0].bits.uop.fu_code[9] \n connect slots_15.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[15].wakeup_ports[0].bits.uop.iq_type[0] \n connect slots_15.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[15].wakeup_ports[0].bits.uop.iq_type[1] \n connect slots_15.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[15].wakeup_ports[0].bits.uop.iq_type[2] \n connect slots_15.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[15].wakeup_ports[0].bits.uop.iq_type[3] \n connect slots_15.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[15].wakeup_ports[0].bits.uop.debug_pc \n connect slots_15.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[15].wakeup_ports[0].bits.uop.is_rvc \n connect slots_15.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[15].wakeup_ports[0].bits.uop.debug_inst \n connect slots_15.io.wakeup_ports[0].bits.uop.inst, issue_slots[15].wakeup_ports[0].bits.uop.inst \n connect slots_15.io.wakeup_ports[0].valid, issue_slots[15].wakeup_ports[0].valid \n connect slots_15.io.wakeup_ports[1].bits.rebusy, issue_slots[15].wakeup_ports[1].bits.rebusy \n connect slots_15.io.wakeup_ports[1].bits.speculative_mask, issue_slots[15].wakeup_ports[1].bits.speculative_mask \n connect slots_15.io.wakeup_ports[1].bits.bypassable, issue_slots[15].wakeup_ports[1].bits.bypassable \n connect slots_15.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[15].wakeup_ports[1].bits.uop.debug_tsrc \n connect slots_15.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[15].wakeup_ports[1].bits.uop.debug_fsrc \n connect slots_15.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[15].wakeup_ports[1].bits.uop.bp_xcpt_if \n connect slots_15.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[15].wakeup_ports[1].bits.uop.bp_debug_if \n connect slots_15.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[15].wakeup_ports[1].bits.uop.xcpt_ma_if \n connect slots_15.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[15].wakeup_ports[1].bits.uop.xcpt_ae_if \n connect slots_15.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[15].wakeup_ports[1].bits.uop.xcpt_pf_if \n connect slots_15.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[15].wakeup_ports[1].bits.uop.fp_typ \n connect slots_15.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[15].wakeup_ports[1].bits.uop.fp_rm \n connect slots_15.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[15].wakeup_ports[1].bits.uop.fp_val \n connect slots_15.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[15].wakeup_ports[1].bits.uop.fcn_op \n connect slots_15.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[15].wakeup_ports[1].bits.uop.fcn_dw \n connect slots_15.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[15].wakeup_ports[1].bits.uop.frs3_en \n connect slots_15.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[15].wakeup_ports[1].bits.uop.lrs2_rtype \n connect slots_15.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[15].wakeup_ports[1].bits.uop.lrs1_rtype \n connect slots_15.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[15].wakeup_ports[1].bits.uop.dst_rtype \n connect slots_15.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[15].wakeup_ports[1].bits.uop.lrs3 \n connect slots_15.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[15].wakeup_ports[1].bits.uop.lrs2 \n connect slots_15.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[15].wakeup_ports[1].bits.uop.lrs1 \n connect slots_15.io.wakeup_ports[1].bits.uop.ldst, issue_slots[15].wakeup_ports[1].bits.uop.ldst \n connect slots_15.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[15].wakeup_ports[1].bits.uop.ldst_is_rs1 \n connect slots_15.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[15].wakeup_ports[1].bits.uop.csr_cmd \n connect slots_15.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[15].wakeup_ports[1].bits.uop.flush_on_commit \n connect slots_15.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[15].wakeup_ports[1].bits.uop.is_unique \n connect slots_15.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[15].wakeup_ports[1].bits.uop.uses_stq \n connect slots_15.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[15].wakeup_ports[1].bits.uop.uses_ldq \n connect slots_15.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[15].wakeup_ports[1].bits.uop.mem_signed \n connect slots_15.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[15].wakeup_ports[1].bits.uop.mem_size \n connect slots_15.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[15].wakeup_ports[1].bits.uop.mem_cmd \n connect slots_15.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[15].wakeup_ports[1].bits.uop.exc_cause \n connect slots_15.io.wakeup_ports[1].bits.uop.exception, issue_slots[15].wakeup_ports[1].bits.uop.exception \n connect slots_15.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[15].wakeup_ports[1].bits.uop.stale_pdst \n connect slots_15.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[15].wakeup_ports[1].bits.uop.ppred_busy \n connect slots_15.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[15].wakeup_ports[1].bits.uop.prs3_busy \n connect slots_15.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[15].wakeup_ports[1].bits.uop.prs2_busy \n connect slots_15.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[15].wakeup_ports[1].bits.uop.prs1_busy \n connect slots_15.io.wakeup_ports[1].bits.uop.ppred, issue_slots[15].wakeup_ports[1].bits.uop.ppred \n connect slots_15.io.wakeup_ports[1].bits.uop.prs3, issue_slots[15].wakeup_ports[1].bits.uop.prs3 \n connect slots_15.io.wakeup_ports[1].bits.uop.prs2, issue_slots[15].wakeup_ports[1].bits.uop.prs2 \n connect slots_15.io.wakeup_ports[1].bits.uop.prs1, issue_slots[15].wakeup_ports[1].bits.uop.prs1 \n connect slots_15.io.wakeup_ports[1].bits.uop.pdst, issue_slots[15].wakeup_ports[1].bits.uop.pdst \n connect slots_15.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[15].wakeup_ports[1].bits.uop.rxq_idx \n connect slots_15.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[15].wakeup_ports[1].bits.uop.stq_idx \n connect slots_15.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[15].wakeup_ports[1].bits.uop.ldq_idx \n connect slots_15.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[15].wakeup_ports[1].bits.uop.rob_idx \n connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.vec \n connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.wflags \n connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.sqrt \n connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.div \n connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.fma \n connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe \n connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.toint \n connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.fromint \n connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut \n connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn \n connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.swap23 \n connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.swap12 \n connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.ren3 \n connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.ren2 \n connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.ren1 \n connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.wen \n connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.ldst \n connect slots_15.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[15].wakeup_ports[1].bits.uop.op2_sel \n connect slots_15.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[15].wakeup_ports[1].bits.uop.op1_sel \n connect slots_15.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[15].wakeup_ports[1].bits.uop.imm_packed \n connect slots_15.io.wakeup_ports[1].bits.uop.pimm, issue_slots[15].wakeup_ports[1].bits.uop.pimm \n connect slots_15.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[15].wakeup_ports[1].bits.uop.imm_sel \n connect slots_15.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[15].wakeup_ports[1].bits.uop.imm_rename \n connect slots_15.io.wakeup_ports[1].bits.uop.taken, issue_slots[15].wakeup_ports[1].bits.uop.taken \n connect slots_15.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[15].wakeup_ports[1].bits.uop.pc_lob \n connect slots_15.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[15].wakeup_ports[1].bits.uop.edge_inst \n connect slots_15.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[15].wakeup_ports[1].bits.uop.ftq_idx \n connect slots_15.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[15].wakeup_ports[1].bits.uop.is_mov \n connect slots_15.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[15].wakeup_ports[1].bits.uop.is_rocc \n connect slots_15.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[15].wakeup_ports[1].bits.uop.is_sys_pc2epc \n connect slots_15.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[15].wakeup_ports[1].bits.uop.is_eret \n connect slots_15.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[15].wakeup_ports[1].bits.uop.is_amo \n connect slots_15.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[15].wakeup_ports[1].bits.uop.is_sfence \n connect slots_15.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[15].wakeup_ports[1].bits.uop.is_fencei \n connect slots_15.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[15].wakeup_ports[1].bits.uop.is_fence \n connect slots_15.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[15].wakeup_ports[1].bits.uop.is_sfb \n connect slots_15.io.wakeup_ports[1].bits.uop.br_type, issue_slots[15].wakeup_ports[1].bits.uop.br_type \n connect slots_15.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[15].wakeup_ports[1].bits.uop.br_tag \n connect slots_15.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[15].wakeup_ports[1].bits.uop.br_mask \n connect slots_15.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[15].wakeup_ports[1].bits.uop.dis_col_sel \n connect slots_15.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[15].wakeup_ports[1].bits.uop.iw_p3_bypass_hint \n connect slots_15.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[15].wakeup_ports[1].bits.uop.iw_p2_bypass_hint \n connect slots_15.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[15].wakeup_ports[1].bits.uop.iw_p1_bypass_hint \n connect slots_15.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[15].wakeup_ports[1].bits.uop.iw_p2_speculative_child \n connect slots_15.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[15].wakeup_ports[1].bits.uop.iw_p1_speculative_child \n connect slots_15.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[15].wakeup_ports[1].bits.uop.iw_issued_partial_dgen \n connect slots_15.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[15].wakeup_ports[1].bits.uop.iw_issued_partial_agen \n connect slots_15.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[15].wakeup_ports[1].bits.uop.iw_issued \n connect slots_15.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[15].wakeup_ports[1].bits.uop.fu_code[0] \n connect slots_15.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[15].wakeup_ports[1].bits.uop.fu_code[1] \n connect slots_15.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[15].wakeup_ports[1].bits.uop.fu_code[2] \n connect slots_15.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[15].wakeup_ports[1].bits.uop.fu_code[3] \n connect slots_15.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[15].wakeup_ports[1].bits.uop.fu_code[4] \n connect slots_15.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[15].wakeup_ports[1].bits.uop.fu_code[5] \n connect slots_15.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[15].wakeup_ports[1].bits.uop.fu_code[6] \n connect slots_15.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[15].wakeup_ports[1].bits.uop.fu_code[7] \n connect slots_15.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[15].wakeup_ports[1].bits.uop.fu_code[8] \n connect slots_15.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[15].wakeup_ports[1].bits.uop.fu_code[9] \n connect slots_15.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[15].wakeup_ports[1].bits.uop.iq_type[0] \n connect slots_15.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[15].wakeup_ports[1].bits.uop.iq_type[1] \n connect slots_15.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[15].wakeup_ports[1].bits.uop.iq_type[2] \n connect slots_15.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[15].wakeup_ports[1].bits.uop.iq_type[3] \n connect slots_15.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[15].wakeup_ports[1].bits.uop.debug_pc \n connect slots_15.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[15].wakeup_ports[1].bits.uop.is_rvc \n connect slots_15.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[15].wakeup_ports[1].bits.uop.debug_inst \n connect slots_15.io.wakeup_ports[1].bits.uop.inst, issue_slots[15].wakeup_ports[1].bits.uop.inst \n connect slots_15.io.wakeup_ports[1].valid, issue_slots[15].wakeup_ports[1].valid \n connect slots_15.io.wakeup_ports[2].bits.rebusy, issue_slots[15].wakeup_ports[2].bits.rebusy \n connect slots_15.io.wakeup_ports[2].bits.speculative_mask, issue_slots[15].wakeup_ports[2].bits.speculative_mask \n connect slots_15.io.wakeup_ports[2].bits.bypassable, issue_slots[15].wakeup_ports[2].bits.bypassable \n connect slots_15.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[15].wakeup_ports[2].bits.uop.debug_tsrc \n connect slots_15.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[15].wakeup_ports[2].bits.uop.debug_fsrc \n connect slots_15.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[15].wakeup_ports[2].bits.uop.bp_xcpt_if \n connect slots_15.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[15].wakeup_ports[2].bits.uop.bp_debug_if \n connect slots_15.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[15].wakeup_ports[2].bits.uop.xcpt_ma_if \n connect slots_15.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[15].wakeup_ports[2].bits.uop.xcpt_ae_if \n connect slots_15.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[15].wakeup_ports[2].bits.uop.xcpt_pf_if \n connect slots_15.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[15].wakeup_ports[2].bits.uop.fp_typ \n connect slots_15.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[15].wakeup_ports[2].bits.uop.fp_rm \n connect slots_15.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[15].wakeup_ports[2].bits.uop.fp_val \n connect slots_15.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[15].wakeup_ports[2].bits.uop.fcn_op \n connect slots_15.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[15].wakeup_ports[2].bits.uop.fcn_dw \n connect slots_15.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[15].wakeup_ports[2].bits.uop.frs3_en \n connect slots_15.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[15].wakeup_ports[2].bits.uop.lrs2_rtype \n connect slots_15.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[15].wakeup_ports[2].bits.uop.lrs1_rtype \n connect slots_15.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[15].wakeup_ports[2].bits.uop.dst_rtype \n connect slots_15.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[15].wakeup_ports[2].bits.uop.lrs3 \n connect slots_15.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[15].wakeup_ports[2].bits.uop.lrs2 \n connect slots_15.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[15].wakeup_ports[2].bits.uop.lrs1 \n connect slots_15.io.wakeup_ports[2].bits.uop.ldst, issue_slots[15].wakeup_ports[2].bits.uop.ldst \n connect slots_15.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[15].wakeup_ports[2].bits.uop.ldst_is_rs1 \n connect slots_15.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[15].wakeup_ports[2].bits.uop.csr_cmd \n connect slots_15.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[15].wakeup_ports[2].bits.uop.flush_on_commit \n connect slots_15.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[15].wakeup_ports[2].bits.uop.is_unique \n connect slots_15.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[15].wakeup_ports[2].bits.uop.uses_stq \n connect slots_15.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[15].wakeup_ports[2].bits.uop.uses_ldq \n connect slots_15.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[15].wakeup_ports[2].bits.uop.mem_signed \n connect slots_15.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[15].wakeup_ports[2].bits.uop.mem_size \n connect slots_15.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[15].wakeup_ports[2].bits.uop.mem_cmd \n connect slots_15.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[15].wakeup_ports[2].bits.uop.exc_cause \n connect slots_15.io.wakeup_ports[2].bits.uop.exception, issue_slots[15].wakeup_ports[2].bits.uop.exception \n connect slots_15.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[15].wakeup_ports[2].bits.uop.stale_pdst \n connect slots_15.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[15].wakeup_ports[2].bits.uop.ppred_busy \n connect slots_15.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[15].wakeup_ports[2].bits.uop.prs3_busy \n connect slots_15.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[15].wakeup_ports[2].bits.uop.prs2_busy \n connect slots_15.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[15].wakeup_ports[2].bits.uop.prs1_busy \n connect slots_15.io.wakeup_ports[2].bits.uop.ppred, issue_slots[15].wakeup_ports[2].bits.uop.ppred \n connect slots_15.io.wakeup_ports[2].bits.uop.prs3, issue_slots[15].wakeup_ports[2].bits.uop.prs3 \n connect slots_15.io.wakeup_ports[2].bits.uop.prs2, issue_slots[15].wakeup_ports[2].bits.uop.prs2 \n connect slots_15.io.wakeup_ports[2].bits.uop.prs1, issue_slots[15].wakeup_ports[2].bits.uop.prs1 \n connect slots_15.io.wakeup_ports[2].bits.uop.pdst, issue_slots[15].wakeup_ports[2].bits.uop.pdst \n connect slots_15.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[15].wakeup_ports[2].bits.uop.rxq_idx \n connect slots_15.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[15].wakeup_ports[2].bits.uop.stq_idx \n connect slots_15.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[15].wakeup_ports[2].bits.uop.ldq_idx \n connect slots_15.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[15].wakeup_ports[2].bits.uop.rob_idx \n connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.vec \n connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.wflags \n connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.sqrt \n connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.div \n connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.fma \n connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe \n connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.toint \n connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.fromint \n connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut \n connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn \n connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.swap23 \n connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.swap12 \n connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.ren3 \n connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.ren2 \n connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.ren1 \n connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.wen \n connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.ldst \n connect slots_15.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[15].wakeup_ports[2].bits.uop.op2_sel \n connect slots_15.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[15].wakeup_ports[2].bits.uop.op1_sel \n connect slots_15.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[15].wakeup_ports[2].bits.uop.imm_packed \n connect slots_15.io.wakeup_ports[2].bits.uop.pimm, issue_slots[15].wakeup_ports[2].bits.uop.pimm \n connect slots_15.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[15].wakeup_ports[2].bits.uop.imm_sel \n connect slots_15.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[15].wakeup_ports[2].bits.uop.imm_rename \n connect slots_15.io.wakeup_ports[2].bits.uop.taken, issue_slots[15].wakeup_ports[2].bits.uop.taken \n connect slots_15.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[15].wakeup_ports[2].bits.uop.pc_lob \n connect slots_15.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[15].wakeup_ports[2].bits.uop.edge_inst \n connect slots_15.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[15].wakeup_ports[2].bits.uop.ftq_idx \n connect slots_15.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[15].wakeup_ports[2].bits.uop.is_mov \n connect slots_15.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[15].wakeup_ports[2].bits.uop.is_rocc \n connect slots_15.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[15].wakeup_ports[2].bits.uop.is_sys_pc2epc \n connect slots_15.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[15].wakeup_ports[2].bits.uop.is_eret \n connect slots_15.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[15].wakeup_ports[2].bits.uop.is_amo \n connect slots_15.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[15].wakeup_ports[2].bits.uop.is_sfence \n connect slots_15.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[15].wakeup_ports[2].bits.uop.is_fencei \n connect slots_15.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[15].wakeup_ports[2].bits.uop.is_fence \n connect slots_15.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[15].wakeup_ports[2].bits.uop.is_sfb \n connect slots_15.io.wakeup_ports[2].bits.uop.br_type, issue_slots[15].wakeup_ports[2].bits.uop.br_type \n connect slots_15.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[15].wakeup_ports[2].bits.uop.br_tag \n connect slots_15.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[15].wakeup_ports[2].bits.uop.br_mask \n connect slots_15.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[15].wakeup_ports[2].bits.uop.dis_col_sel \n connect slots_15.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[15].wakeup_ports[2].bits.uop.iw_p3_bypass_hint \n connect slots_15.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[15].wakeup_ports[2].bits.uop.iw_p2_bypass_hint \n connect slots_15.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[15].wakeup_ports[2].bits.uop.iw_p1_bypass_hint \n connect slots_15.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[15].wakeup_ports[2].bits.uop.iw_p2_speculative_child \n connect slots_15.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[15].wakeup_ports[2].bits.uop.iw_p1_speculative_child \n connect slots_15.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[15].wakeup_ports[2].bits.uop.iw_issued_partial_dgen \n connect slots_15.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[15].wakeup_ports[2].bits.uop.iw_issued_partial_agen \n connect slots_15.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[15].wakeup_ports[2].bits.uop.iw_issued \n connect slots_15.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[15].wakeup_ports[2].bits.uop.fu_code[0] \n connect slots_15.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[15].wakeup_ports[2].bits.uop.fu_code[1] \n connect slots_15.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[15].wakeup_ports[2].bits.uop.fu_code[2] \n connect slots_15.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[15].wakeup_ports[2].bits.uop.fu_code[3] \n connect slots_15.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[15].wakeup_ports[2].bits.uop.fu_code[4] \n connect slots_15.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[15].wakeup_ports[2].bits.uop.fu_code[5] \n connect slots_15.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[15].wakeup_ports[2].bits.uop.fu_code[6] \n connect slots_15.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[15].wakeup_ports[2].bits.uop.fu_code[7] \n connect slots_15.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[15].wakeup_ports[2].bits.uop.fu_code[8] \n connect slots_15.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[15].wakeup_ports[2].bits.uop.fu_code[9] \n connect slots_15.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[15].wakeup_ports[2].bits.uop.iq_type[0] \n connect slots_15.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[15].wakeup_ports[2].bits.uop.iq_type[1] \n connect slots_15.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[15].wakeup_ports[2].bits.uop.iq_type[2] \n connect slots_15.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[15].wakeup_ports[2].bits.uop.iq_type[3] \n connect slots_15.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[15].wakeup_ports[2].bits.uop.debug_pc \n connect slots_15.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[15].wakeup_ports[2].bits.uop.is_rvc \n connect slots_15.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[15].wakeup_ports[2].bits.uop.debug_inst \n connect slots_15.io.wakeup_ports[2].bits.uop.inst, issue_slots[15].wakeup_ports[2].bits.uop.inst \n connect slots_15.io.wakeup_ports[2].valid, issue_slots[15].wakeup_ports[2].valid \n connect slots_15.io.wakeup_ports[3].bits.rebusy, issue_slots[15].wakeup_ports[3].bits.rebusy \n connect slots_15.io.wakeup_ports[3].bits.speculative_mask, issue_slots[15].wakeup_ports[3].bits.speculative_mask \n connect slots_15.io.wakeup_ports[3].bits.bypassable, issue_slots[15].wakeup_ports[3].bits.bypassable \n connect slots_15.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[15].wakeup_ports[3].bits.uop.debug_tsrc \n connect slots_15.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[15].wakeup_ports[3].bits.uop.debug_fsrc \n connect slots_15.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[15].wakeup_ports[3].bits.uop.bp_xcpt_if \n connect slots_15.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[15].wakeup_ports[3].bits.uop.bp_debug_if \n connect slots_15.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[15].wakeup_ports[3].bits.uop.xcpt_ma_if \n connect slots_15.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[15].wakeup_ports[3].bits.uop.xcpt_ae_if \n connect slots_15.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[15].wakeup_ports[3].bits.uop.xcpt_pf_if \n connect slots_15.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[15].wakeup_ports[3].bits.uop.fp_typ \n connect slots_15.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[15].wakeup_ports[3].bits.uop.fp_rm \n connect slots_15.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[15].wakeup_ports[3].bits.uop.fp_val \n connect slots_15.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[15].wakeup_ports[3].bits.uop.fcn_op \n connect slots_15.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[15].wakeup_ports[3].bits.uop.fcn_dw \n connect slots_15.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[15].wakeup_ports[3].bits.uop.frs3_en \n connect slots_15.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[15].wakeup_ports[3].bits.uop.lrs2_rtype \n connect slots_15.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[15].wakeup_ports[3].bits.uop.lrs1_rtype \n connect slots_15.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[15].wakeup_ports[3].bits.uop.dst_rtype \n connect slots_15.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[15].wakeup_ports[3].bits.uop.lrs3 \n connect slots_15.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[15].wakeup_ports[3].bits.uop.lrs2 \n connect slots_15.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[15].wakeup_ports[3].bits.uop.lrs1 \n connect slots_15.io.wakeup_ports[3].bits.uop.ldst, issue_slots[15].wakeup_ports[3].bits.uop.ldst \n connect slots_15.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[15].wakeup_ports[3].bits.uop.ldst_is_rs1 \n connect slots_15.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[15].wakeup_ports[3].bits.uop.csr_cmd \n connect slots_15.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[15].wakeup_ports[3].bits.uop.flush_on_commit \n connect slots_15.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[15].wakeup_ports[3].bits.uop.is_unique \n connect slots_15.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[15].wakeup_ports[3].bits.uop.uses_stq \n connect slots_15.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[15].wakeup_ports[3].bits.uop.uses_ldq \n connect slots_15.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[15].wakeup_ports[3].bits.uop.mem_signed \n connect slots_15.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[15].wakeup_ports[3].bits.uop.mem_size \n connect slots_15.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[15].wakeup_ports[3].bits.uop.mem_cmd \n connect slots_15.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[15].wakeup_ports[3].bits.uop.exc_cause \n connect slots_15.io.wakeup_ports[3].bits.uop.exception, issue_slots[15].wakeup_ports[3].bits.uop.exception \n connect slots_15.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[15].wakeup_ports[3].bits.uop.stale_pdst \n connect slots_15.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[15].wakeup_ports[3].bits.uop.ppred_busy \n connect slots_15.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[15].wakeup_ports[3].bits.uop.prs3_busy \n connect slots_15.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[15].wakeup_ports[3].bits.uop.prs2_busy \n connect slots_15.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[15].wakeup_ports[3].bits.uop.prs1_busy \n connect slots_15.io.wakeup_ports[3].bits.uop.ppred, issue_slots[15].wakeup_ports[3].bits.uop.ppred \n connect slots_15.io.wakeup_ports[3].bits.uop.prs3, issue_slots[15].wakeup_ports[3].bits.uop.prs3 \n connect slots_15.io.wakeup_ports[3].bits.uop.prs2, issue_slots[15].wakeup_ports[3].bits.uop.prs2 \n connect slots_15.io.wakeup_ports[3].bits.uop.prs1, issue_slots[15].wakeup_ports[3].bits.uop.prs1 \n connect slots_15.io.wakeup_ports[3].bits.uop.pdst, issue_slots[15].wakeup_ports[3].bits.uop.pdst \n connect slots_15.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[15].wakeup_ports[3].bits.uop.rxq_idx \n connect slots_15.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[15].wakeup_ports[3].bits.uop.stq_idx \n connect slots_15.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[15].wakeup_ports[3].bits.uop.ldq_idx \n connect slots_15.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[15].wakeup_ports[3].bits.uop.rob_idx \n connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.vec \n connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.wflags \n connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.sqrt \n connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.div \n connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.fma \n connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe \n connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.toint \n connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.fromint \n connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut \n connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn \n connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.swap23 \n connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.swap12 \n connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.ren3 \n connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.ren2 \n connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.ren1 \n connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.wen \n connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.ldst \n connect slots_15.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[15].wakeup_ports[3].bits.uop.op2_sel \n connect slots_15.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[15].wakeup_ports[3].bits.uop.op1_sel \n connect slots_15.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[15].wakeup_ports[3].bits.uop.imm_packed \n connect slots_15.io.wakeup_ports[3].bits.uop.pimm, issue_slots[15].wakeup_ports[3].bits.uop.pimm \n connect slots_15.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[15].wakeup_ports[3].bits.uop.imm_sel \n connect slots_15.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[15].wakeup_ports[3].bits.uop.imm_rename \n connect slots_15.io.wakeup_ports[3].bits.uop.taken, issue_slots[15].wakeup_ports[3].bits.uop.taken \n connect slots_15.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[15].wakeup_ports[3].bits.uop.pc_lob \n connect slots_15.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[15].wakeup_ports[3].bits.uop.edge_inst \n connect slots_15.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[15].wakeup_ports[3].bits.uop.ftq_idx \n connect slots_15.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[15].wakeup_ports[3].bits.uop.is_mov \n connect slots_15.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[15].wakeup_ports[3].bits.uop.is_rocc \n connect slots_15.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[15].wakeup_ports[3].bits.uop.is_sys_pc2epc \n connect slots_15.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[15].wakeup_ports[3].bits.uop.is_eret \n connect slots_15.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[15].wakeup_ports[3].bits.uop.is_amo \n connect slots_15.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[15].wakeup_ports[3].bits.uop.is_sfence \n connect slots_15.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[15].wakeup_ports[3].bits.uop.is_fencei \n connect slots_15.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[15].wakeup_ports[3].bits.uop.is_fence \n connect slots_15.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[15].wakeup_ports[3].bits.uop.is_sfb \n connect slots_15.io.wakeup_ports[3].bits.uop.br_type, issue_slots[15].wakeup_ports[3].bits.uop.br_type \n connect slots_15.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[15].wakeup_ports[3].bits.uop.br_tag \n connect slots_15.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[15].wakeup_ports[3].bits.uop.br_mask \n connect slots_15.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[15].wakeup_ports[3].bits.uop.dis_col_sel \n connect slots_15.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[15].wakeup_ports[3].bits.uop.iw_p3_bypass_hint \n connect slots_15.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[15].wakeup_ports[3].bits.uop.iw_p2_bypass_hint \n connect slots_15.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[15].wakeup_ports[3].bits.uop.iw_p1_bypass_hint \n connect slots_15.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[15].wakeup_ports[3].bits.uop.iw_p2_speculative_child \n connect slots_15.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[15].wakeup_ports[3].bits.uop.iw_p1_speculative_child \n connect slots_15.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[15].wakeup_ports[3].bits.uop.iw_issued_partial_dgen \n connect slots_15.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[15].wakeup_ports[3].bits.uop.iw_issued_partial_agen \n connect slots_15.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[15].wakeup_ports[3].bits.uop.iw_issued \n connect slots_15.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[15].wakeup_ports[3].bits.uop.fu_code[0] \n connect slots_15.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[15].wakeup_ports[3].bits.uop.fu_code[1] \n connect slots_15.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[15].wakeup_ports[3].bits.uop.fu_code[2] \n connect slots_15.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[15].wakeup_ports[3].bits.uop.fu_code[3] \n connect slots_15.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[15].wakeup_ports[3].bits.uop.fu_code[4] \n connect slots_15.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[15].wakeup_ports[3].bits.uop.fu_code[5] \n connect slots_15.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[15].wakeup_ports[3].bits.uop.fu_code[6] \n connect slots_15.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[15].wakeup_ports[3].bits.uop.fu_code[7] \n connect slots_15.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[15].wakeup_ports[3].bits.uop.fu_code[8] \n connect slots_15.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[15].wakeup_ports[3].bits.uop.fu_code[9] \n connect slots_15.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[15].wakeup_ports[3].bits.uop.iq_type[0] \n connect slots_15.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[15].wakeup_ports[3].bits.uop.iq_type[1] \n connect slots_15.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[15].wakeup_ports[3].bits.uop.iq_type[2] \n connect slots_15.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[15].wakeup_ports[3].bits.uop.iq_type[3] \n connect slots_15.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[15].wakeup_ports[3].bits.uop.debug_pc \n connect slots_15.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[15].wakeup_ports[3].bits.uop.is_rvc \n connect slots_15.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[15].wakeup_ports[3].bits.uop.debug_inst \n connect slots_15.io.wakeup_ports[3].bits.uop.inst, issue_slots[15].wakeup_ports[3].bits.uop.inst \n connect slots_15.io.wakeup_ports[3].valid, issue_slots[15].wakeup_ports[3].valid \n connect slots_15.io.squash_grant, issue_slots[15].squash_grant \n connect slots_15.io.clear, issue_slots[15].clear \n connect slots_15.io.kill, issue_slots[15].kill \n connect slots_15.io.brupdate.b2.target_offset, issue_slots[15].brupdate.b2.target_offset \n connect slots_15.io.brupdate.b2.jalr_target, issue_slots[15].brupdate.b2.jalr_target \n connect slots_15.io.brupdate.b2.pc_sel, issue_slots[15].brupdate.b2.pc_sel \n connect slots_15.io.brupdate.b2.cfi_type, issue_slots[15].brupdate.b2.cfi_type \n connect slots_15.io.brupdate.b2.taken, issue_slots[15].brupdate.b2.taken \n connect slots_15.io.brupdate.b2.mispredict, issue_slots[15].brupdate.b2.mispredict \n connect slots_15.io.brupdate.b2.uop.debug_tsrc, issue_slots[15].brupdate.b2.uop.debug_tsrc \n connect slots_15.io.brupdate.b2.uop.debug_fsrc, issue_slots[15].brupdate.b2.uop.debug_fsrc \n connect slots_15.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[15].brupdate.b2.uop.bp_xcpt_if \n connect slots_15.io.brupdate.b2.uop.bp_debug_if, issue_slots[15].brupdate.b2.uop.bp_debug_if \n connect slots_15.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[15].brupdate.b2.uop.xcpt_ma_if \n connect slots_15.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[15].brupdate.b2.uop.xcpt_ae_if \n connect slots_15.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[15].brupdate.b2.uop.xcpt_pf_if \n connect slots_15.io.brupdate.b2.uop.fp_typ, issue_slots[15].brupdate.b2.uop.fp_typ \n connect slots_15.io.brupdate.b2.uop.fp_rm, issue_slots[15].brupdate.b2.uop.fp_rm \n connect slots_15.io.brupdate.b2.uop.fp_val, issue_slots[15].brupdate.b2.uop.fp_val \n connect slots_15.io.brupdate.b2.uop.fcn_op, issue_slots[15].brupdate.b2.uop.fcn_op \n connect slots_15.io.brupdate.b2.uop.fcn_dw, issue_slots[15].brupdate.b2.uop.fcn_dw \n connect slots_15.io.brupdate.b2.uop.frs3_en, issue_slots[15].brupdate.b2.uop.frs3_en \n connect slots_15.io.brupdate.b2.uop.lrs2_rtype, issue_slots[15].brupdate.b2.uop.lrs2_rtype \n connect slots_15.io.brupdate.b2.uop.lrs1_rtype, issue_slots[15].brupdate.b2.uop.lrs1_rtype \n connect slots_15.io.brupdate.b2.uop.dst_rtype, issue_slots[15].brupdate.b2.uop.dst_rtype \n connect slots_15.io.brupdate.b2.uop.lrs3, issue_slots[15].brupdate.b2.uop.lrs3 \n connect slots_15.io.brupdate.b2.uop.lrs2, issue_slots[15].brupdate.b2.uop.lrs2 \n connect slots_15.io.brupdate.b2.uop.lrs1, issue_slots[15].brupdate.b2.uop.lrs1 \n connect slots_15.io.brupdate.b2.uop.ldst, issue_slots[15].brupdate.b2.uop.ldst \n connect slots_15.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[15].brupdate.b2.uop.ldst_is_rs1 \n connect slots_15.io.brupdate.b2.uop.csr_cmd, issue_slots[15].brupdate.b2.uop.csr_cmd \n connect slots_15.io.brupdate.b2.uop.flush_on_commit, issue_slots[15].brupdate.b2.uop.flush_on_commit \n connect slots_15.io.brupdate.b2.uop.is_unique, issue_slots[15].brupdate.b2.uop.is_unique \n connect slots_15.io.brupdate.b2.uop.uses_stq, issue_slots[15].brupdate.b2.uop.uses_stq \n connect slots_15.io.brupdate.b2.uop.uses_ldq, issue_slots[15].brupdate.b2.uop.uses_ldq \n connect slots_15.io.brupdate.b2.uop.mem_signed, issue_slots[15].brupdate.b2.uop.mem_signed \n connect slots_15.io.brupdate.b2.uop.mem_size, issue_slots[15].brupdate.b2.uop.mem_size \n connect slots_15.io.brupdate.b2.uop.mem_cmd, issue_slots[15].brupdate.b2.uop.mem_cmd \n connect slots_15.io.brupdate.b2.uop.exc_cause, issue_slots[15].brupdate.b2.uop.exc_cause \n connect slots_15.io.brupdate.b2.uop.exception, issue_slots[15].brupdate.b2.uop.exception \n connect slots_15.io.brupdate.b2.uop.stale_pdst, issue_slots[15].brupdate.b2.uop.stale_pdst \n connect slots_15.io.brupdate.b2.uop.ppred_busy, issue_slots[15].brupdate.b2.uop.ppred_busy \n connect slots_15.io.brupdate.b2.uop.prs3_busy, issue_slots[15].brupdate.b2.uop.prs3_busy \n connect slots_15.io.brupdate.b2.uop.prs2_busy, issue_slots[15].brupdate.b2.uop.prs2_busy \n connect slots_15.io.brupdate.b2.uop.prs1_busy, issue_slots[15].brupdate.b2.uop.prs1_busy \n connect slots_15.io.brupdate.b2.uop.ppred, issue_slots[15].brupdate.b2.uop.ppred \n connect slots_15.io.brupdate.b2.uop.prs3, issue_slots[15].brupdate.b2.uop.prs3 \n connect slots_15.io.brupdate.b2.uop.prs2, issue_slots[15].brupdate.b2.uop.prs2 \n connect slots_15.io.brupdate.b2.uop.prs1, issue_slots[15].brupdate.b2.uop.prs1 \n connect slots_15.io.brupdate.b2.uop.pdst, issue_slots[15].brupdate.b2.uop.pdst \n connect slots_15.io.brupdate.b2.uop.rxq_idx, issue_slots[15].brupdate.b2.uop.rxq_idx \n connect slots_15.io.brupdate.b2.uop.stq_idx, issue_slots[15].brupdate.b2.uop.stq_idx \n connect slots_15.io.brupdate.b2.uop.ldq_idx, issue_slots[15].brupdate.b2.uop.ldq_idx \n connect slots_15.io.brupdate.b2.uop.rob_idx, issue_slots[15].brupdate.b2.uop.rob_idx \n connect slots_15.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[15].brupdate.b2.uop.fp_ctrl.vec \n connect slots_15.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[15].brupdate.b2.uop.fp_ctrl.wflags \n connect slots_15.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[15].brupdate.b2.uop.fp_ctrl.sqrt \n connect slots_15.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[15].brupdate.b2.uop.fp_ctrl.div \n connect slots_15.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[15].brupdate.b2.uop.fp_ctrl.fma \n connect slots_15.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[15].brupdate.b2.uop.fp_ctrl.fastpipe \n connect slots_15.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[15].brupdate.b2.uop.fp_ctrl.toint \n connect slots_15.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[15].brupdate.b2.uop.fp_ctrl.fromint \n connect slots_15.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[15].brupdate.b2.uop.fp_ctrl.typeTagOut \n connect slots_15.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[15].brupdate.b2.uop.fp_ctrl.typeTagIn \n connect slots_15.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[15].brupdate.b2.uop.fp_ctrl.swap23 \n connect slots_15.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[15].brupdate.b2.uop.fp_ctrl.swap12 \n connect slots_15.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[15].brupdate.b2.uop.fp_ctrl.ren3 \n connect slots_15.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[15].brupdate.b2.uop.fp_ctrl.ren2 \n connect slots_15.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[15].brupdate.b2.uop.fp_ctrl.ren1 \n connect slots_15.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[15].brupdate.b2.uop.fp_ctrl.wen \n connect slots_15.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[15].brupdate.b2.uop.fp_ctrl.ldst \n connect slots_15.io.brupdate.b2.uop.op2_sel, issue_slots[15].brupdate.b2.uop.op2_sel \n connect slots_15.io.brupdate.b2.uop.op1_sel, issue_slots[15].brupdate.b2.uop.op1_sel \n connect slots_15.io.brupdate.b2.uop.imm_packed, issue_slots[15].brupdate.b2.uop.imm_packed \n connect slots_15.io.brupdate.b2.uop.pimm, issue_slots[15].brupdate.b2.uop.pimm \n connect slots_15.io.brupdate.b2.uop.imm_sel, issue_slots[15].brupdate.b2.uop.imm_sel \n connect slots_15.io.brupdate.b2.uop.imm_rename, issue_slots[15].brupdate.b2.uop.imm_rename \n connect slots_15.io.brupdate.b2.uop.taken, issue_slots[15].brupdate.b2.uop.taken \n connect slots_15.io.brupdate.b2.uop.pc_lob, issue_slots[15].brupdate.b2.uop.pc_lob \n connect slots_15.io.brupdate.b2.uop.edge_inst, issue_slots[15].brupdate.b2.uop.edge_inst \n connect slots_15.io.brupdate.b2.uop.ftq_idx, issue_slots[15].brupdate.b2.uop.ftq_idx \n connect slots_15.io.brupdate.b2.uop.is_mov, issue_slots[15].brupdate.b2.uop.is_mov \n connect slots_15.io.brupdate.b2.uop.is_rocc, issue_slots[15].brupdate.b2.uop.is_rocc \n connect slots_15.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[15].brupdate.b2.uop.is_sys_pc2epc \n connect slots_15.io.brupdate.b2.uop.is_eret, issue_slots[15].brupdate.b2.uop.is_eret \n connect slots_15.io.brupdate.b2.uop.is_amo, issue_slots[15].brupdate.b2.uop.is_amo \n connect slots_15.io.brupdate.b2.uop.is_sfence, issue_slots[15].brupdate.b2.uop.is_sfence \n connect slots_15.io.brupdate.b2.uop.is_fencei, issue_slots[15].brupdate.b2.uop.is_fencei \n connect slots_15.io.brupdate.b2.uop.is_fence, issue_slots[15].brupdate.b2.uop.is_fence \n connect slots_15.io.brupdate.b2.uop.is_sfb, issue_slots[15].brupdate.b2.uop.is_sfb \n connect slots_15.io.brupdate.b2.uop.br_type, issue_slots[15].brupdate.b2.uop.br_type \n connect slots_15.io.brupdate.b2.uop.br_tag, issue_slots[15].brupdate.b2.uop.br_tag \n connect slots_15.io.brupdate.b2.uop.br_mask, issue_slots[15].brupdate.b2.uop.br_mask \n connect slots_15.io.brupdate.b2.uop.dis_col_sel, issue_slots[15].brupdate.b2.uop.dis_col_sel \n connect slots_15.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[15].brupdate.b2.uop.iw_p3_bypass_hint \n connect slots_15.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[15].brupdate.b2.uop.iw_p2_bypass_hint \n connect slots_15.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[15].brupdate.b2.uop.iw_p1_bypass_hint \n connect slots_15.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[15].brupdate.b2.uop.iw_p2_speculative_child \n connect slots_15.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[15].brupdate.b2.uop.iw_p1_speculative_child \n connect slots_15.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[15].brupdate.b2.uop.iw_issued_partial_dgen \n connect slots_15.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[15].brupdate.b2.uop.iw_issued_partial_agen \n connect slots_15.io.brupdate.b2.uop.iw_issued, issue_slots[15].brupdate.b2.uop.iw_issued \n connect slots_15.io.brupdate.b2.uop.fu_code[0], issue_slots[15].brupdate.b2.uop.fu_code[0] \n connect slots_15.io.brupdate.b2.uop.fu_code[1], issue_slots[15].brupdate.b2.uop.fu_code[1] \n connect slots_15.io.brupdate.b2.uop.fu_code[2], issue_slots[15].brupdate.b2.uop.fu_code[2] \n connect slots_15.io.brupdate.b2.uop.fu_code[3], issue_slots[15].brupdate.b2.uop.fu_code[3] \n connect slots_15.io.brupdate.b2.uop.fu_code[4], issue_slots[15].brupdate.b2.uop.fu_code[4] \n connect slots_15.io.brupdate.b2.uop.fu_code[5], issue_slots[15].brupdate.b2.uop.fu_code[5] \n connect slots_15.io.brupdate.b2.uop.fu_code[6], issue_slots[15].brupdate.b2.uop.fu_code[6] \n connect slots_15.io.brupdate.b2.uop.fu_code[7], issue_slots[15].brupdate.b2.uop.fu_code[7] \n connect slots_15.io.brupdate.b2.uop.fu_code[8], issue_slots[15].brupdate.b2.uop.fu_code[8] \n connect slots_15.io.brupdate.b2.uop.fu_code[9], issue_slots[15].brupdate.b2.uop.fu_code[9] \n connect slots_15.io.brupdate.b2.uop.iq_type[0], issue_slots[15].brupdate.b2.uop.iq_type[0] \n connect slots_15.io.brupdate.b2.uop.iq_type[1], issue_slots[15].brupdate.b2.uop.iq_type[1] \n connect slots_15.io.brupdate.b2.uop.iq_type[2], issue_slots[15].brupdate.b2.uop.iq_type[2] \n connect slots_15.io.brupdate.b2.uop.iq_type[3], issue_slots[15].brupdate.b2.uop.iq_type[3] \n connect slots_15.io.brupdate.b2.uop.debug_pc, issue_slots[15].brupdate.b2.uop.debug_pc \n connect slots_15.io.brupdate.b2.uop.is_rvc, issue_slots[15].brupdate.b2.uop.is_rvc \n connect slots_15.io.brupdate.b2.uop.debug_inst, issue_slots[15].brupdate.b2.uop.debug_inst \n connect slots_15.io.brupdate.b2.uop.inst, issue_slots[15].brupdate.b2.uop.inst \n connect slots_15.io.brupdate.b1.mispredict_mask, issue_slots[15].brupdate.b1.mispredict_mask \n connect slots_15.io.brupdate.b1.resolve_mask, issue_slots[15].brupdate.b1.resolve_mask \n connect issue_slots[15].out_uop.debug_tsrc, slots_15.io.out_uop.debug_tsrc \n connect issue_slots[15].out_uop.debug_fsrc, slots_15.io.out_uop.debug_fsrc \n connect issue_slots[15].out_uop.bp_xcpt_if, slots_15.io.out_uop.bp_xcpt_if \n connect issue_slots[15].out_uop.bp_debug_if, slots_15.io.out_uop.bp_debug_if \n connect issue_slots[15].out_uop.xcpt_ma_if, slots_15.io.out_uop.xcpt_ma_if \n connect issue_slots[15].out_uop.xcpt_ae_if, slots_15.io.out_uop.xcpt_ae_if \n connect issue_slots[15].out_uop.xcpt_pf_if, slots_15.io.out_uop.xcpt_pf_if \n connect issue_slots[15].out_uop.fp_typ, slots_15.io.out_uop.fp_typ \n connect issue_slots[15].out_uop.fp_rm, slots_15.io.out_uop.fp_rm \n connect issue_slots[15].out_uop.fp_val, slots_15.io.out_uop.fp_val \n connect issue_slots[15].out_uop.fcn_op, slots_15.io.out_uop.fcn_op \n connect issue_slots[15].out_uop.fcn_dw, slots_15.io.out_uop.fcn_dw \n connect issue_slots[15].out_uop.frs3_en, slots_15.io.out_uop.frs3_en \n connect issue_slots[15].out_uop.lrs2_rtype, slots_15.io.out_uop.lrs2_rtype \n connect issue_slots[15].out_uop.lrs1_rtype, slots_15.io.out_uop.lrs1_rtype \n connect issue_slots[15].out_uop.dst_rtype, slots_15.io.out_uop.dst_rtype \n connect issue_slots[15].out_uop.lrs3, slots_15.io.out_uop.lrs3 \n connect issue_slots[15].out_uop.lrs2, slots_15.io.out_uop.lrs2 \n connect issue_slots[15].out_uop.lrs1, slots_15.io.out_uop.lrs1 \n connect issue_slots[15].out_uop.ldst, slots_15.io.out_uop.ldst \n connect issue_slots[15].out_uop.ldst_is_rs1, slots_15.io.out_uop.ldst_is_rs1 \n connect issue_slots[15].out_uop.csr_cmd, slots_15.io.out_uop.csr_cmd \n connect issue_slots[15].out_uop.flush_on_commit, slots_15.io.out_uop.flush_on_commit \n connect issue_slots[15].out_uop.is_unique, slots_15.io.out_uop.is_unique \n connect issue_slots[15].out_uop.uses_stq, slots_15.io.out_uop.uses_stq \n connect issue_slots[15].out_uop.uses_ldq, slots_15.io.out_uop.uses_ldq \n connect issue_slots[15].out_uop.mem_signed, slots_15.io.out_uop.mem_signed \n connect issue_slots[15].out_uop.mem_size, slots_15.io.out_uop.mem_size \n connect issue_slots[15].out_uop.mem_cmd, slots_15.io.out_uop.mem_cmd \n connect issue_slots[15].out_uop.exc_cause, slots_15.io.out_uop.exc_cause \n connect issue_slots[15].out_uop.exception, slots_15.io.out_uop.exception \n connect issue_slots[15].out_uop.stale_pdst, slots_15.io.out_uop.stale_pdst \n connect issue_slots[15].out_uop.ppred_busy, slots_15.io.out_uop.ppred_busy \n connect issue_slots[15].out_uop.prs3_busy, slots_15.io.out_uop.prs3_busy \n connect issue_slots[15].out_uop.prs2_busy, slots_15.io.out_uop.prs2_busy \n connect issue_slots[15].out_uop.prs1_busy, slots_15.io.out_uop.prs1_busy \n connect issue_slots[15].out_uop.ppred, slots_15.io.out_uop.ppred \n connect issue_slots[15].out_uop.prs3, slots_15.io.out_uop.prs3 \n connect issue_slots[15].out_uop.prs2, slots_15.io.out_uop.prs2 \n connect issue_slots[15].out_uop.prs1, slots_15.io.out_uop.prs1 \n connect issue_slots[15].out_uop.pdst, slots_15.io.out_uop.pdst \n connect issue_slots[15].out_uop.rxq_idx, slots_15.io.out_uop.rxq_idx \n connect issue_slots[15].out_uop.stq_idx, slots_15.io.out_uop.stq_idx \n connect issue_slots[15].out_uop.ldq_idx, slots_15.io.out_uop.ldq_idx \n connect issue_slots[15].out_uop.rob_idx, slots_15.io.out_uop.rob_idx \n connect issue_slots[15].out_uop.fp_ctrl.vec, slots_15.io.out_uop.fp_ctrl.vec \n connect issue_slots[15].out_uop.fp_ctrl.wflags, slots_15.io.out_uop.fp_ctrl.wflags \n connect issue_slots[15].out_uop.fp_ctrl.sqrt, slots_15.io.out_uop.fp_ctrl.sqrt \n connect issue_slots[15].out_uop.fp_ctrl.div, slots_15.io.out_uop.fp_ctrl.div \n connect issue_slots[15].out_uop.fp_ctrl.fma, slots_15.io.out_uop.fp_ctrl.fma \n connect issue_slots[15].out_uop.fp_ctrl.fastpipe, slots_15.io.out_uop.fp_ctrl.fastpipe \n connect issue_slots[15].out_uop.fp_ctrl.toint, slots_15.io.out_uop.fp_ctrl.toint \n connect issue_slots[15].out_uop.fp_ctrl.fromint, slots_15.io.out_uop.fp_ctrl.fromint \n connect issue_slots[15].out_uop.fp_ctrl.typeTagOut, slots_15.io.out_uop.fp_ctrl.typeTagOut \n connect issue_slots[15].out_uop.fp_ctrl.typeTagIn, slots_15.io.out_uop.fp_ctrl.typeTagIn \n connect issue_slots[15].out_uop.fp_ctrl.swap23, slots_15.io.out_uop.fp_ctrl.swap23 \n connect issue_slots[15].out_uop.fp_ctrl.swap12, slots_15.io.out_uop.fp_ctrl.swap12 \n connect issue_slots[15].out_uop.fp_ctrl.ren3, slots_15.io.out_uop.fp_ctrl.ren3 \n connect issue_slots[15].out_uop.fp_ctrl.ren2, slots_15.io.out_uop.fp_ctrl.ren2 \n connect issue_slots[15].out_uop.fp_ctrl.ren1, slots_15.io.out_uop.fp_ctrl.ren1 \n connect issue_slots[15].out_uop.fp_ctrl.wen, slots_15.io.out_uop.fp_ctrl.wen \n connect issue_slots[15].out_uop.fp_ctrl.ldst, slots_15.io.out_uop.fp_ctrl.ldst \n connect issue_slots[15].out_uop.op2_sel, slots_15.io.out_uop.op2_sel \n connect issue_slots[15].out_uop.op1_sel, slots_15.io.out_uop.op1_sel \n connect issue_slots[15].out_uop.imm_packed, slots_15.io.out_uop.imm_packed \n connect issue_slots[15].out_uop.pimm, slots_15.io.out_uop.pimm \n connect issue_slots[15].out_uop.imm_sel, slots_15.io.out_uop.imm_sel \n connect issue_slots[15].out_uop.imm_rename, slots_15.io.out_uop.imm_rename \n connect issue_slots[15].out_uop.taken, slots_15.io.out_uop.taken \n connect issue_slots[15].out_uop.pc_lob, slots_15.io.out_uop.pc_lob \n connect issue_slots[15].out_uop.edge_inst, slots_15.io.out_uop.edge_inst \n connect issue_slots[15].out_uop.ftq_idx, slots_15.io.out_uop.ftq_idx \n connect issue_slots[15].out_uop.is_mov, slots_15.io.out_uop.is_mov \n connect issue_slots[15].out_uop.is_rocc, slots_15.io.out_uop.is_rocc \n connect issue_slots[15].out_uop.is_sys_pc2epc, slots_15.io.out_uop.is_sys_pc2epc \n connect issue_slots[15].out_uop.is_eret, slots_15.io.out_uop.is_eret \n connect issue_slots[15].out_uop.is_amo, slots_15.io.out_uop.is_amo \n connect issue_slots[15].out_uop.is_sfence, slots_15.io.out_uop.is_sfence \n connect issue_slots[15].out_uop.is_fencei, slots_15.io.out_uop.is_fencei \n connect issue_slots[15].out_uop.is_fence, slots_15.io.out_uop.is_fence \n connect issue_slots[15].out_uop.is_sfb, slots_15.io.out_uop.is_sfb \n connect issue_slots[15].out_uop.br_type, slots_15.io.out_uop.br_type \n connect issue_slots[15].out_uop.br_tag, slots_15.io.out_uop.br_tag \n connect issue_slots[15].out_uop.br_mask, slots_15.io.out_uop.br_mask \n connect issue_slots[15].out_uop.dis_col_sel, slots_15.io.out_uop.dis_col_sel \n connect issue_slots[15].out_uop.iw_p3_bypass_hint, slots_15.io.out_uop.iw_p3_bypass_hint \n connect issue_slots[15].out_uop.iw_p2_bypass_hint, slots_15.io.out_uop.iw_p2_bypass_hint \n connect issue_slots[15].out_uop.iw_p1_bypass_hint, slots_15.io.out_uop.iw_p1_bypass_hint \n connect issue_slots[15].out_uop.iw_p2_speculative_child, slots_15.io.out_uop.iw_p2_speculative_child \n connect issue_slots[15].out_uop.iw_p1_speculative_child, slots_15.io.out_uop.iw_p1_speculative_child \n connect issue_slots[15].out_uop.iw_issued_partial_dgen, slots_15.io.out_uop.iw_issued_partial_dgen \n connect issue_slots[15].out_uop.iw_issued_partial_agen, slots_15.io.out_uop.iw_issued_partial_agen \n connect issue_slots[15].out_uop.iw_issued, slots_15.io.out_uop.iw_issued \n connect issue_slots[15].out_uop.fu_code[0], slots_15.io.out_uop.fu_code[0] \n connect issue_slots[15].out_uop.fu_code[1], slots_15.io.out_uop.fu_code[1] \n connect issue_slots[15].out_uop.fu_code[2], slots_15.io.out_uop.fu_code[2] \n connect issue_slots[15].out_uop.fu_code[3], slots_15.io.out_uop.fu_code[3] \n connect issue_slots[15].out_uop.fu_code[4], slots_15.io.out_uop.fu_code[4] \n connect issue_slots[15].out_uop.fu_code[5], slots_15.io.out_uop.fu_code[5] \n connect issue_slots[15].out_uop.fu_code[6], slots_15.io.out_uop.fu_code[6] \n connect issue_slots[15].out_uop.fu_code[7], slots_15.io.out_uop.fu_code[7] \n connect issue_slots[15].out_uop.fu_code[8], slots_15.io.out_uop.fu_code[8] \n connect issue_slots[15].out_uop.fu_code[9], slots_15.io.out_uop.fu_code[9] \n connect issue_slots[15].out_uop.iq_type[0], slots_15.io.out_uop.iq_type[0] \n connect issue_slots[15].out_uop.iq_type[1], slots_15.io.out_uop.iq_type[1] \n connect issue_slots[15].out_uop.iq_type[2], slots_15.io.out_uop.iq_type[2] \n connect issue_slots[15].out_uop.iq_type[3], slots_15.io.out_uop.iq_type[3] \n connect issue_slots[15].out_uop.debug_pc, slots_15.io.out_uop.debug_pc \n connect issue_slots[15].out_uop.is_rvc, slots_15.io.out_uop.is_rvc \n connect issue_slots[15].out_uop.debug_inst, slots_15.io.out_uop.debug_inst \n connect issue_slots[15].out_uop.inst, slots_15.io.out_uop.inst \n connect slots_15.io.in_uop.bits.debug_tsrc, issue_slots[15].in_uop.bits.debug_tsrc \n connect slots_15.io.in_uop.bits.debug_fsrc, issue_slots[15].in_uop.bits.debug_fsrc \n connect slots_15.io.in_uop.bits.bp_xcpt_if, issue_slots[15].in_uop.bits.bp_xcpt_if \n connect slots_15.io.in_uop.bits.bp_debug_if, issue_slots[15].in_uop.bits.bp_debug_if \n connect slots_15.io.in_uop.bits.xcpt_ma_if, issue_slots[15].in_uop.bits.xcpt_ma_if \n connect slots_15.io.in_uop.bits.xcpt_ae_if, issue_slots[15].in_uop.bits.xcpt_ae_if \n connect slots_15.io.in_uop.bits.xcpt_pf_if, issue_slots[15].in_uop.bits.xcpt_pf_if \n connect slots_15.io.in_uop.bits.fp_typ, issue_slots[15].in_uop.bits.fp_typ \n connect slots_15.io.in_uop.bits.fp_rm, issue_slots[15].in_uop.bits.fp_rm \n connect slots_15.io.in_uop.bits.fp_val, issue_slots[15].in_uop.bits.fp_val \n connect slots_15.io.in_uop.bits.fcn_op, issue_slots[15].in_uop.bits.fcn_op \n connect slots_15.io.in_uop.bits.fcn_dw, issue_slots[15].in_uop.bits.fcn_dw \n connect slots_15.io.in_uop.bits.frs3_en, issue_slots[15].in_uop.bits.frs3_en \n connect slots_15.io.in_uop.bits.lrs2_rtype, issue_slots[15].in_uop.bits.lrs2_rtype \n connect slots_15.io.in_uop.bits.lrs1_rtype, issue_slots[15].in_uop.bits.lrs1_rtype \n connect slots_15.io.in_uop.bits.dst_rtype, issue_slots[15].in_uop.bits.dst_rtype \n connect slots_15.io.in_uop.bits.lrs3, issue_slots[15].in_uop.bits.lrs3 \n connect slots_15.io.in_uop.bits.lrs2, issue_slots[15].in_uop.bits.lrs2 \n connect slots_15.io.in_uop.bits.lrs1, issue_slots[15].in_uop.bits.lrs1 \n connect slots_15.io.in_uop.bits.ldst, issue_slots[15].in_uop.bits.ldst \n connect slots_15.io.in_uop.bits.ldst_is_rs1, issue_slots[15].in_uop.bits.ldst_is_rs1 \n connect slots_15.io.in_uop.bits.csr_cmd, issue_slots[15].in_uop.bits.csr_cmd \n connect slots_15.io.in_uop.bits.flush_on_commit, issue_slots[15].in_uop.bits.flush_on_commit \n connect slots_15.io.in_uop.bits.is_unique, issue_slots[15].in_uop.bits.is_unique \n connect slots_15.io.in_uop.bits.uses_stq, issue_slots[15].in_uop.bits.uses_stq \n connect slots_15.io.in_uop.bits.uses_ldq, issue_slots[15].in_uop.bits.uses_ldq \n connect slots_15.io.in_uop.bits.mem_signed, issue_slots[15].in_uop.bits.mem_signed \n connect slots_15.io.in_uop.bits.mem_size, issue_slots[15].in_uop.bits.mem_size \n connect slots_15.io.in_uop.bits.mem_cmd, issue_slots[15].in_uop.bits.mem_cmd \n connect slots_15.io.in_uop.bits.exc_cause, issue_slots[15].in_uop.bits.exc_cause \n connect slots_15.io.in_uop.bits.exception, issue_slots[15].in_uop.bits.exception \n connect slots_15.io.in_uop.bits.stale_pdst, issue_slots[15].in_uop.bits.stale_pdst \n connect slots_15.io.in_uop.bits.ppred_busy, issue_slots[15].in_uop.bits.ppred_busy \n connect slots_15.io.in_uop.bits.prs3_busy, issue_slots[15].in_uop.bits.prs3_busy \n connect slots_15.io.in_uop.bits.prs2_busy, issue_slots[15].in_uop.bits.prs2_busy \n connect slots_15.io.in_uop.bits.prs1_busy, issue_slots[15].in_uop.bits.prs1_busy \n connect slots_15.io.in_uop.bits.ppred, issue_slots[15].in_uop.bits.ppred \n connect slots_15.io.in_uop.bits.prs3, issue_slots[15].in_uop.bits.prs3 \n connect slots_15.io.in_uop.bits.prs2, issue_slots[15].in_uop.bits.prs2 \n connect slots_15.io.in_uop.bits.prs1, issue_slots[15].in_uop.bits.prs1 \n connect slots_15.io.in_uop.bits.pdst, issue_slots[15].in_uop.bits.pdst \n connect slots_15.io.in_uop.bits.rxq_idx, issue_slots[15].in_uop.bits.rxq_idx \n connect slots_15.io.in_uop.bits.stq_idx, issue_slots[15].in_uop.bits.stq_idx \n connect slots_15.io.in_uop.bits.ldq_idx, issue_slots[15].in_uop.bits.ldq_idx \n connect slots_15.io.in_uop.bits.rob_idx, issue_slots[15].in_uop.bits.rob_idx \n connect slots_15.io.in_uop.bits.fp_ctrl.vec, issue_slots[15].in_uop.bits.fp_ctrl.vec \n connect slots_15.io.in_uop.bits.fp_ctrl.wflags, issue_slots[15].in_uop.bits.fp_ctrl.wflags \n connect slots_15.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[15].in_uop.bits.fp_ctrl.sqrt \n connect slots_15.io.in_uop.bits.fp_ctrl.div, issue_slots[15].in_uop.bits.fp_ctrl.div \n connect slots_15.io.in_uop.bits.fp_ctrl.fma, issue_slots[15].in_uop.bits.fp_ctrl.fma \n connect slots_15.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[15].in_uop.bits.fp_ctrl.fastpipe \n connect slots_15.io.in_uop.bits.fp_ctrl.toint, issue_slots[15].in_uop.bits.fp_ctrl.toint \n connect slots_15.io.in_uop.bits.fp_ctrl.fromint, issue_slots[15].in_uop.bits.fp_ctrl.fromint \n connect slots_15.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[15].in_uop.bits.fp_ctrl.typeTagOut \n connect slots_15.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[15].in_uop.bits.fp_ctrl.typeTagIn \n connect slots_15.io.in_uop.bits.fp_ctrl.swap23, issue_slots[15].in_uop.bits.fp_ctrl.swap23 \n connect slots_15.io.in_uop.bits.fp_ctrl.swap12, issue_slots[15].in_uop.bits.fp_ctrl.swap12 \n connect slots_15.io.in_uop.bits.fp_ctrl.ren3, issue_slots[15].in_uop.bits.fp_ctrl.ren3 \n connect slots_15.io.in_uop.bits.fp_ctrl.ren2, issue_slots[15].in_uop.bits.fp_ctrl.ren2 \n connect slots_15.io.in_uop.bits.fp_ctrl.ren1, issue_slots[15].in_uop.bits.fp_ctrl.ren1 \n connect slots_15.io.in_uop.bits.fp_ctrl.wen, issue_slots[15].in_uop.bits.fp_ctrl.wen \n connect slots_15.io.in_uop.bits.fp_ctrl.ldst, issue_slots[15].in_uop.bits.fp_ctrl.ldst \n connect slots_15.io.in_uop.bits.op2_sel, issue_slots[15].in_uop.bits.op2_sel \n connect slots_15.io.in_uop.bits.op1_sel, issue_slots[15].in_uop.bits.op1_sel \n connect slots_15.io.in_uop.bits.imm_packed, issue_slots[15].in_uop.bits.imm_packed \n connect slots_15.io.in_uop.bits.pimm, issue_slots[15].in_uop.bits.pimm \n connect slots_15.io.in_uop.bits.imm_sel, issue_slots[15].in_uop.bits.imm_sel \n connect slots_15.io.in_uop.bits.imm_rename, issue_slots[15].in_uop.bits.imm_rename \n connect slots_15.io.in_uop.bits.taken, issue_slots[15].in_uop.bits.taken \n connect slots_15.io.in_uop.bits.pc_lob, issue_slots[15].in_uop.bits.pc_lob \n connect slots_15.io.in_uop.bits.edge_inst, issue_slots[15].in_uop.bits.edge_inst \n connect slots_15.io.in_uop.bits.ftq_idx, issue_slots[15].in_uop.bits.ftq_idx \n connect slots_15.io.in_uop.bits.is_mov, issue_slots[15].in_uop.bits.is_mov \n connect slots_15.io.in_uop.bits.is_rocc, issue_slots[15].in_uop.bits.is_rocc \n connect slots_15.io.in_uop.bits.is_sys_pc2epc, issue_slots[15].in_uop.bits.is_sys_pc2epc \n connect slots_15.io.in_uop.bits.is_eret, issue_slots[15].in_uop.bits.is_eret \n connect slots_15.io.in_uop.bits.is_amo, issue_slots[15].in_uop.bits.is_amo \n connect slots_15.io.in_uop.bits.is_sfence, issue_slots[15].in_uop.bits.is_sfence \n connect slots_15.io.in_uop.bits.is_fencei, issue_slots[15].in_uop.bits.is_fencei \n connect slots_15.io.in_uop.bits.is_fence, issue_slots[15].in_uop.bits.is_fence \n connect slots_15.io.in_uop.bits.is_sfb, issue_slots[15].in_uop.bits.is_sfb \n connect slots_15.io.in_uop.bits.br_type, issue_slots[15].in_uop.bits.br_type \n connect slots_15.io.in_uop.bits.br_tag, issue_slots[15].in_uop.bits.br_tag \n connect slots_15.io.in_uop.bits.br_mask, issue_slots[15].in_uop.bits.br_mask \n connect slots_15.io.in_uop.bits.dis_col_sel, issue_slots[15].in_uop.bits.dis_col_sel \n connect slots_15.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[15].in_uop.bits.iw_p3_bypass_hint \n connect slots_15.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[15].in_uop.bits.iw_p2_bypass_hint \n connect slots_15.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[15].in_uop.bits.iw_p1_bypass_hint \n connect slots_15.io.in_uop.bits.iw_p2_speculative_child, issue_slots[15].in_uop.bits.iw_p2_speculative_child \n connect slots_15.io.in_uop.bits.iw_p1_speculative_child, issue_slots[15].in_uop.bits.iw_p1_speculative_child \n connect slots_15.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[15].in_uop.bits.iw_issued_partial_dgen \n connect slots_15.io.in_uop.bits.iw_issued_partial_agen, issue_slots[15].in_uop.bits.iw_issued_partial_agen \n connect slots_15.io.in_uop.bits.iw_issued, issue_slots[15].in_uop.bits.iw_issued \n connect slots_15.io.in_uop.bits.fu_code[0], issue_slots[15].in_uop.bits.fu_code[0] \n connect slots_15.io.in_uop.bits.fu_code[1], issue_slots[15].in_uop.bits.fu_code[1] \n connect slots_15.io.in_uop.bits.fu_code[2], issue_slots[15].in_uop.bits.fu_code[2] \n connect slots_15.io.in_uop.bits.fu_code[3], issue_slots[15].in_uop.bits.fu_code[3] \n connect slots_15.io.in_uop.bits.fu_code[4], issue_slots[15].in_uop.bits.fu_code[4] \n connect slots_15.io.in_uop.bits.fu_code[5], issue_slots[15].in_uop.bits.fu_code[5] \n connect slots_15.io.in_uop.bits.fu_code[6], issue_slots[15].in_uop.bits.fu_code[6] \n connect slots_15.io.in_uop.bits.fu_code[7], issue_slots[15].in_uop.bits.fu_code[7] \n connect slots_15.io.in_uop.bits.fu_code[8], issue_slots[15].in_uop.bits.fu_code[8] \n connect slots_15.io.in_uop.bits.fu_code[9], issue_slots[15].in_uop.bits.fu_code[9] \n connect slots_15.io.in_uop.bits.iq_type[0], issue_slots[15].in_uop.bits.iq_type[0] \n connect slots_15.io.in_uop.bits.iq_type[1], issue_slots[15].in_uop.bits.iq_type[1] \n connect slots_15.io.in_uop.bits.iq_type[2], issue_slots[15].in_uop.bits.iq_type[2] \n connect slots_15.io.in_uop.bits.iq_type[3], issue_slots[15].in_uop.bits.iq_type[3] \n connect slots_15.io.in_uop.bits.debug_pc, issue_slots[15].in_uop.bits.debug_pc \n connect slots_15.io.in_uop.bits.is_rvc, issue_slots[15].in_uop.bits.is_rvc \n connect slots_15.io.in_uop.bits.debug_inst, issue_slots[15].in_uop.bits.debug_inst \n connect slots_15.io.in_uop.bits.inst, issue_slots[15].in_uop.bits.inst \n connect slots_15.io.in_uop.valid, issue_slots[15].in_uop.valid \n connect issue_slots[15].iss_uop.debug_tsrc, slots_15.io.iss_uop.debug_tsrc \n connect issue_slots[15].iss_uop.debug_fsrc, slots_15.io.iss_uop.debug_fsrc \n connect issue_slots[15].iss_uop.bp_xcpt_if, slots_15.io.iss_uop.bp_xcpt_if \n connect issue_slots[15].iss_uop.bp_debug_if, slots_15.io.iss_uop.bp_debug_if \n connect issue_slots[15].iss_uop.xcpt_ma_if, slots_15.io.iss_uop.xcpt_ma_if \n connect issue_slots[15].iss_uop.xcpt_ae_if, slots_15.io.iss_uop.xcpt_ae_if \n connect issue_slots[15].iss_uop.xcpt_pf_if, slots_15.io.iss_uop.xcpt_pf_if \n connect issue_slots[15].iss_uop.fp_typ, slots_15.io.iss_uop.fp_typ \n connect issue_slots[15].iss_uop.fp_rm, slots_15.io.iss_uop.fp_rm \n connect issue_slots[15].iss_uop.fp_val, slots_15.io.iss_uop.fp_val \n connect issue_slots[15].iss_uop.fcn_op, slots_15.io.iss_uop.fcn_op \n connect issue_slots[15].iss_uop.fcn_dw, slots_15.io.iss_uop.fcn_dw \n connect issue_slots[15].iss_uop.frs3_en, slots_15.io.iss_uop.frs3_en \n connect issue_slots[15].iss_uop.lrs2_rtype, slots_15.io.iss_uop.lrs2_rtype \n connect issue_slots[15].iss_uop.lrs1_rtype, slots_15.io.iss_uop.lrs1_rtype \n connect issue_slots[15].iss_uop.dst_rtype, slots_15.io.iss_uop.dst_rtype \n connect issue_slots[15].iss_uop.lrs3, slots_15.io.iss_uop.lrs3 \n connect issue_slots[15].iss_uop.lrs2, slots_15.io.iss_uop.lrs2 \n connect issue_slots[15].iss_uop.lrs1, slots_15.io.iss_uop.lrs1 \n connect issue_slots[15].iss_uop.ldst, slots_15.io.iss_uop.ldst \n connect issue_slots[15].iss_uop.ldst_is_rs1, slots_15.io.iss_uop.ldst_is_rs1 \n connect issue_slots[15].iss_uop.csr_cmd, slots_15.io.iss_uop.csr_cmd \n connect issue_slots[15].iss_uop.flush_on_commit, slots_15.io.iss_uop.flush_on_commit \n connect issue_slots[15].iss_uop.is_unique, slots_15.io.iss_uop.is_unique \n connect issue_slots[15].iss_uop.uses_stq, slots_15.io.iss_uop.uses_stq \n connect issue_slots[15].iss_uop.uses_ldq, slots_15.io.iss_uop.uses_ldq \n connect issue_slots[15].iss_uop.mem_signed, slots_15.io.iss_uop.mem_signed \n connect issue_slots[15].iss_uop.mem_size, slots_15.io.iss_uop.mem_size \n connect issue_slots[15].iss_uop.mem_cmd, slots_15.io.iss_uop.mem_cmd \n connect issue_slots[15].iss_uop.exc_cause, slots_15.io.iss_uop.exc_cause \n connect issue_slots[15].iss_uop.exception, slots_15.io.iss_uop.exception \n connect issue_slots[15].iss_uop.stale_pdst, slots_15.io.iss_uop.stale_pdst \n connect issue_slots[15].iss_uop.ppred_busy, slots_15.io.iss_uop.ppred_busy \n connect issue_slots[15].iss_uop.prs3_busy, slots_15.io.iss_uop.prs3_busy \n connect issue_slots[15].iss_uop.prs2_busy, slots_15.io.iss_uop.prs2_busy \n connect issue_slots[15].iss_uop.prs1_busy, slots_15.io.iss_uop.prs1_busy \n connect issue_slots[15].iss_uop.ppred, slots_15.io.iss_uop.ppred \n connect issue_slots[15].iss_uop.prs3, slots_15.io.iss_uop.prs3 \n connect issue_slots[15].iss_uop.prs2, slots_15.io.iss_uop.prs2 \n connect issue_slots[15].iss_uop.prs1, slots_15.io.iss_uop.prs1 \n connect issue_slots[15].iss_uop.pdst, slots_15.io.iss_uop.pdst \n connect issue_slots[15].iss_uop.rxq_idx, slots_15.io.iss_uop.rxq_idx \n connect issue_slots[15].iss_uop.stq_idx, slots_15.io.iss_uop.stq_idx \n connect issue_slots[15].iss_uop.ldq_idx, slots_15.io.iss_uop.ldq_idx \n connect issue_slots[15].iss_uop.rob_idx, slots_15.io.iss_uop.rob_idx \n connect issue_slots[15].iss_uop.fp_ctrl.vec, slots_15.io.iss_uop.fp_ctrl.vec \n connect issue_slots[15].iss_uop.fp_ctrl.wflags, slots_15.io.iss_uop.fp_ctrl.wflags \n connect issue_slots[15].iss_uop.fp_ctrl.sqrt, slots_15.io.iss_uop.fp_ctrl.sqrt \n connect issue_slots[15].iss_uop.fp_ctrl.div, slots_15.io.iss_uop.fp_ctrl.div \n connect issue_slots[15].iss_uop.fp_ctrl.fma, slots_15.io.iss_uop.fp_ctrl.fma \n connect issue_slots[15].iss_uop.fp_ctrl.fastpipe, slots_15.io.iss_uop.fp_ctrl.fastpipe \n connect issue_slots[15].iss_uop.fp_ctrl.toint, slots_15.io.iss_uop.fp_ctrl.toint \n connect issue_slots[15].iss_uop.fp_ctrl.fromint, slots_15.io.iss_uop.fp_ctrl.fromint \n connect issue_slots[15].iss_uop.fp_ctrl.typeTagOut, slots_15.io.iss_uop.fp_ctrl.typeTagOut \n connect issue_slots[15].iss_uop.fp_ctrl.typeTagIn, slots_15.io.iss_uop.fp_ctrl.typeTagIn \n connect issue_slots[15].iss_uop.fp_ctrl.swap23, slots_15.io.iss_uop.fp_ctrl.swap23 \n connect issue_slots[15].iss_uop.fp_ctrl.swap12, slots_15.io.iss_uop.fp_ctrl.swap12 \n connect issue_slots[15].iss_uop.fp_ctrl.ren3, slots_15.io.iss_uop.fp_ctrl.ren3 \n connect issue_slots[15].iss_uop.fp_ctrl.ren2, slots_15.io.iss_uop.fp_ctrl.ren2 \n connect issue_slots[15].iss_uop.fp_ctrl.ren1, slots_15.io.iss_uop.fp_ctrl.ren1 \n connect issue_slots[15].iss_uop.fp_ctrl.wen, slots_15.io.iss_uop.fp_ctrl.wen \n connect issue_slots[15].iss_uop.fp_ctrl.ldst, slots_15.io.iss_uop.fp_ctrl.ldst \n connect issue_slots[15].iss_uop.op2_sel, slots_15.io.iss_uop.op2_sel \n connect issue_slots[15].iss_uop.op1_sel, slots_15.io.iss_uop.op1_sel \n connect issue_slots[15].iss_uop.imm_packed, slots_15.io.iss_uop.imm_packed \n connect issue_slots[15].iss_uop.pimm, slots_15.io.iss_uop.pimm \n connect issue_slots[15].iss_uop.imm_sel, slots_15.io.iss_uop.imm_sel \n connect issue_slots[15].iss_uop.imm_rename, slots_15.io.iss_uop.imm_rename \n connect issue_slots[15].iss_uop.taken, slots_15.io.iss_uop.taken \n connect issue_slots[15].iss_uop.pc_lob, slots_15.io.iss_uop.pc_lob \n connect issue_slots[15].iss_uop.edge_inst, slots_15.io.iss_uop.edge_inst \n connect issue_slots[15].iss_uop.ftq_idx, slots_15.io.iss_uop.ftq_idx \n connect issue_slots[15].iss_uop.is_mov, slots_15.io.iss_uop.is_mov \n connect issue_slots[15].iss_uop.is_rocc, slots_15.io.iss_uop.is_rocc \n connect issue_slots[15].iss_uop.is_sys_pc2epc, slots_15.io.iss_uop.is_sys_pc2epc \n connect issue_slots[15].iss_uop.is_eret, slots_15.io.iss_uop.is_eret \n connect issue_slots[15].iss_uop.is_amo, slots_15.io.iss_uop.is_amo \n connect issue_slots[15].iss_uop.is_sfence, slots_15.io.iss_uop.is_sfence \n connect issue_slots[15].iss_uop.is_fencei, slots_15.io.iss_uop.is_fencei \n connect issue_slots[15].iss_uop.is_fence, slots_15.io.iss_uop.is_fence \n connect issue_slots[15].iss_uop.is_sfb, slots_15.io.iss_uop.is_sfb \n connect issue_slots[15].iss_uop.br_type, slots_15.io.iss_uop.br_type \n connect issue_slots[15].iss_uop.br_tag, slots_15.io.iss_uop.br_tag \n connect issue_slots[15].iss_uop.br_mask, slots_15.io.iss_uop.br_mask \n connect issue_slots[15].iss_uop.dis_col_sel, slots_15.io.iss_uop.dis_col_sel \n connect issue_slots[15].iss_uop.iw_p3_bypass_hint, slots_15.io.iss_uop.iw_p3_bypass_hint \n connect issue_slots[15].iss_uop.iw_p2_bypass_hint, slots_15.io.iss_uop.iw_p2_bypass_hint \n connect issue_slots[15].iss_uop.iw_p1_bypass_hint, slots_15.io.iss_uop.iw_p1_bypass_hint \n connect issue_slots[15].iss_uop.iw_p2_speculative_child, slots_15.io.iss_uop.iw_p2_speculative_child \n connect issue_slots[15].iss_uop.iw_p1_speculative_child, slots_15.io.iss_uop.iw_p1_speculative_child \n connect issue_slots[15].iss_uop.iw_issued_partial_dgen, slots_15.io.iss_uop.iw_issued_partial_dgen \n connect issue_slots[15].iss_uop.iw_issued_partial_agen, slots_15.io.iss_uop.iw_issued_partial_agen \n connect issue_slots[15].iss_uop.iw_issued, slots_15.io.iss_uop.iw_issued \n connect issue_slots[15].iss_uop.fu_code[0], slots_15.io.iss_uop.fu_code[0] \n connect issue_slots[15].iss_uop.fu_code[1], slots_15.io.iss_uop.fu_code[1] \n connect issue_slots[15].iss_uop.fu_code[2], slots_15.io.iss_uop.fu_code[2] \n connect issue_slots[15].iss_uop.fu_code[3], slots_15.io.iss_uop.fu_code[3] \n connect issue_slots[15].iss_uop.fu_code[4], slots_15.io.iss_uop.fu_code[4] \n connect issue_slots[15].iss_uop.fu_code[5], slots_15.io.iss_uop.fu_code[5] \n connect issue_slots[15].iss_uop.fu_code[6], slots_15.io.iss_uop.fu_code[6] \n connect issue_slots[15].iss_uop.fu_code[7], slots_15.io.iss_uop.fu_code[7] \n connect issue_slots[15].iss_uop.fu_code[8], slots_15.io.iss_uop.fu_code[8] \n connect issue_slots[15].iss_uop.fu_code[9], slots_15.io.iss_uop.fu_code[9] \n connect issue_slots[15].iss_uop.iq_type[0], slots_15.io.iss_uop.iq_type[0] \n connect issue_slots[15].iss_uop.iq_type[1], slots_15.io.iss_uop.iq_type[1] \n connect issue_slots[15].iss_uop.iq_type[2], slots_15.io.iss_uop.iq_type[2] \n connect issue_slots[15].iss_uop.iq_type[3], slots_15.io.iss_uop.iq_type[3] \n connect issue_slots[15].iss_uop.debug_pc, slots_15.io.iss_uop.debug_pc \n connect issue_slots[15].iss_uop.is_rvc, slots_15.io.iss_uop.is_rvc \n connect issue_slots[15].iss_uop.debug_inst, slots_15.io.iss_uop.debug_inst \n connect issue_slots[15].iss_uop.inst, slots_15.io.iss_uop.inst \n connect slots_15.io.grant, issue_slots[15].grant \n connect issue_slots[15].request, slots_15.io.request \n connect issue_slots[15].will_be_valid, slots_15.io.will_be_valid \n connect issue_slots[15].valid, slots_15.io.valid \n connect slots_16.io.child_rebusys, issue_slots[16].child_rebusys \n connect slots_16.io.pred_wakeup_port.bits, issue_slots[16].pred_wakeup_port.bits \n connect slots_16.io.pred_wakeup_port.valid, issue_slots[16].pred_wakeup_port.valid \n connect slots_16.io.wakeup_ports[0].bits.rebusy, issue_slots[16].wakeup_ports[0].bits.rebusy \n connect slots_16.io.wakeup_ports[0].bits.speculative_mask, issue_slots[16].wakeup_ports[0].bits.speculative_mask \n connect slots_16.io.wakeup_ports[0].bits.bypassable, issue_slots[16].wakeup_ports[0].bits.bypassable \n connect slots_16.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[16].wakeup_ports[0].bits.uop.debug_tsrc \n connect slots_16.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[16].wakeup_ports[0].bits.uop.debug_fsrc \n connect slots_16.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[16].wakeup_ports[0].bits.uop.bp_xcpt_if \n connect slots_16.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[16].wakeup_ports[0].bits.uop.bp_debug_if \n connect slots_16.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[16].wakeup_ports[0].bits.uop.xcpt_ma_if \n connect slots_16.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[16].wakeup_ports[0].bits.uop.xcpt_ae_if \n connect slots_16.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[16].wakeup_ports[0].bits.uop.xcpt_pf_if \n connect slots_16.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[16].wakeup_ports[0].bits.uop.fp_typ \n connect slots_16.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[16].wakeup_ports[0].bits.uop.fp_rm \n connect slots_16.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[16].wakeup_ports[0].bits.uop.fp_val \n connect slots_16.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[16].wakeup_ports[0].bits.uop.fcn_op \n connect slots_16.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[16].wakeup_ports[0].bits.uop.fcn_dw \n connect slots_16.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[16].wakeup_ports[0].bits.uop.frs3_en \n connect slots_16.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[16].wakeup_ports[0].bits.uop.lrs2_rtype \n connect slots_16.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[16].wakeup_ports[0].bits.uop.lrs1_rtype \n connect slots_16.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[16].wakeup_ports[0].bits.uop.dst_rtype \n connect slots_16.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[16].wakeup_ports[0].bits.uop.lrs3 \n connect slots_16.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[16].wakeup_ports[0].bits.uop.lrs2 \n connect slots_16.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[16].wakeup_ports[0].bits.uop.lrs1 \n connect slots_16.io.wakeup_ports[0].bits.uop.ldst, issue_slots[16].wakeup_ports[0].bits.uop.ldst \n connect slots_16.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[16].wakeup_ports[0].bits.uop.ldst_is_rs1 \n connect slots_16.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[16].wakeup_ports[0].bits.uop.csr_cmd \n connect slots_16.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[16].wakeup_ports[0].bits.uop.flush_on_commit \n connect slots_16.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[16].wakeup_ports[0].bits.uop.is_unique \n connect slots_16.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[16].wakeup_ports[0].bits.uop.uses_stq \n connect slots_16.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[16].wakeup_ports[0].bits.uop.uses_ldq \n connect slots_16.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[16].wakeup_ports[0].bits.uop.mem_signed \n connect slots_16.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[16].wakeup_ports[0].bits.uop.mem_size \n connect slots_16.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[16].wakeup_ports[0].bits.uop.mem_cmd \n connect slots_16.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[16].wakeup_ports[0].bits.uop.exc_cause \n connect slots_16.io.wakeup_ports[0].bits.uop.exception, issue_slots[16].wakeup_ports[0].bits.uop.exception \n connect slots_16.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[16].wakeup_ports[0].bits.uop.stale_pdst \n connect slots_16.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[16].wakeup_ports[0].bits.uop.ppred_busy \n connect slots_16.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[16].wakeup_ports[0].bits.uop.prs3_busy \n connect slots_16.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[16].wakeup_ports[0].bits.uop.prs2_busy \n connect slots_16.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[16].wakeup_ports[0].bits.uop.prs1_busy \n connect slots_16.io.wakeup_ports[0].bits.uop.ppred, issue_slots[16].wakeup_ports[0].bits.uop.ppred \n connect slots_16.io.wakeup_ports[0].bits.uop.prs3, issue_slots[16].wakeup_ports[0].bits.uop.prs3 \n connect slots_16.io.wakeup_ports[0].bits.uop.prs2, issue_slots[16].wakeup_ports[0].bits.uop.prs2 \n connect slots_16.io.wakeup_ports[0].bits.uop.prs1, issue_slots[16].wakeup_ports[0].bits.uop.prs1 \n connect slots_16.io.wakeup_ports[0].bits.uop.pdst, issue_slots[16].wakeup_ports[0].bits.uop.pdst \n connect slots_16.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[16].wakeup_ports[0].bits.uop.rxq_idx \n connect slots_16.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[16].wakeup_ports[0].bits.uop.stq_idx \n connect slots_16.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[16].wakeup_ports[0].bits.uop.ldq_idx \n connect slots_16.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[16].wakeup_ports[0].bits.uop.rob_idx \n connect slots_16.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.vec \n connect slots_16.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.wflags \n connect slots_16.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.sqrt \n connect slots_16.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.div \n connect slots_16.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.fma \n connect slots_16.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe \n connect slots_16.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.toint \n connect slots_16.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.fromint \n connect slots_16.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut \n connect slots_16.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn \n connect slots_16.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.swap23 \n connect slots_16.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.swap12 \n connect slots_16.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.ren3 \n connect slots_16.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.ren2 \n connect slots_16.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.ren1 \n connect slots_16.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.wen \n connect slots_16.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.ldst \n connect slots_16.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[16].wakeup_ports[0].bits.uop.op2_sel \n connect slots_16.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[16].wakeup_ports[0].bits.uop.op1_sel \n connect slots_16.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[16].wakeup_ports[0].bits.uop.imm_packed \n connect slots_16.io.wakeup_ports[0].bits.uop.pimm, issue_slots[16].wakeup_ports[0].bits.uop.pimm \n connect slots_16.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[16].wakeup_ports[0].bits.uop.imm_sel \n connect slots_16.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[16].wakeup_ports[0].bits.uop.imm_rename \n connect slots_16.io.wakeup_ports[0].bits.uop.taken, issue_slots[16].wakeup_ports[0].bits.uop.taken \n connect slots_16.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[16].wakeup_ports[0].bits.uop.pc_lob \n connect slots_16.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[16].wakeup_ports[0].bits.uop.edge_inst \n connect slots_16.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[16].wakeup_ports[0].bits.uop.ftq_idx \n connect slots_16.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[16].wakeup_ports[0].bits.uop.is_mov \n connect slots_16.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[16].wakeup_ports[0].bits.uop.is_rocc \n connect slots_16.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[16].wakeup_ports[0].bits.uop.is_sys_pc2epc \n connect slots_16.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[16].wakeup_ports[0].bits.uop.is_eret \n connect slots_16.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[16].wakeup_ports[0].bits.uop.is_amo \n connect slots_16.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[16].wakeup_ports[0].bits.uop.is_sfence \n connect slots_16.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[16].wakeup_ports[0].bits.uop.is_fencei \n connect slots_16.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[16].wakeup_ports[0].bits.uop.is_fence \n connect slots_16.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[16].wakeup_ports[0].bits.uop.is_sfb \n connect slots_16.io.wakeup_ports[0].bits.uop.br_type, issue_slots[16].wakeup_ports[0].bits.uop.br_type \n connect slots_16.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[16].wakeup_ports[0].bits.uop.br_tag \n connect slots_16.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[16].wakeup_ports[0].bits.uop.br_mask \n connect slots_16.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[16].wakeup_ports[0].bits.uop.dis_col_sel \n connect slots_16.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[16].wakeup_ports[0].bits.uop.iw_p3_bypass_hint \n connect slots_16.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[16].wakeup_ports[0].bits.uop.iw_p2_bypass_hint \n connect slots_16.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[16].wakeup_ports[0].bits.uop.iw_p1_bypass_hint \n connect slots_16.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[16].wakeup_ports[0].bits.uop.iw_p2_speculative_child \n connect slots_16.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[16].wakeup_ports[0].bits.uop.iw_p1_speculative_child \n connect slots_16.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[16].wakeup_ports[0].bits.uop.iw_issued_partial_dgen \n connect slots_16.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[16].wakeup_ports[0].bits.uop.iw_issued_partial_agen \n connect slots_16.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[16].wakeup_ports[0].bits.uop.iw_issued \n connect slots_16.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[16].wakeup_ports[0].bits.uop.fu_code[0] \n connect slots_16.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[16].wakeup_ports[0].bits.uop.fu_code[1] \n connect slots_16.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[16].wakeup_ports[0].bits.uop.fu_code[2] \n connect slots_16.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[16].wakeup_ports[0].bits.uop.fu_code[3] \n connect slots_16.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[16].wakeup_ports[0].bits.uop.fu_code[4] \n connect slots_16.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[16].wakeup_ports[0].bits.uop.fu_code[5] \n connect slots_16.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[16].wakeup_ports[0].bits.uop.fu_code[6] \n connect slots_16.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[16].wakeup_ports[0].bits.uop.fu_code[7] \n connect slots_16.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[16].wakeup_ports[0].bits.uop.fu_code[8] \n connect slots_16.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[16].wakeup_ports[0].bits.uop.fu_code[9] \n connect slots_16.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[16].wakeup_ports[0].bits.uop.iq_type[0] \n connect slots_16.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[16].wakeup_ports[0].bits.uop.iq_type[1] \n connect slots_16.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[16].wakeup_ports[0].bits.uop.iq_type[2] \n connect slots_16.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[16].wakeup_ports[0].bits.uop.iq_type[3] \n connect slots_16.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[16].wakeup_ports[0].bits.uop.debug_pc \n connect slots_16.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[16].wakeup_ports[0].bits.uop.is_rvc \n connect slots_16.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[16].wakeup_ports[0].bits.uop.debug_inst \n connect slots_16.io.wakeup_ports[0].bits.uop.inst, issue_slots[16].wakeup_ports[0].bits.uop.inst \n connect slots_16.io.wakeup_ports[0].valid, issue_slots[16].wakeup_ports[0].valid \n connect slots_16.io.wakeup_ports[1].bits.rebusy, issue_slots[16].wakeup_ports[1].bits.rebusy \n connect slots_16.io.wakeup_ports[1].bits.speculative_mask, issue_slots[16].wakeup_ports[1].bits.speculative_mask \n connect slots_16.io.wakeup_ports[1].bits.bypassable, issue_slots[16].wakeup_ports[1].bits.bypassable \n connect slots_16.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[16].wakeup_ports[1].bits.uop.debug_tsrc \n connect slots_16.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[16].wakeup_ports[1].bits.uop.debug_fsrc \n connect slots_16.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[16].wakeup_ports[1].bits.uop.bp_xcpt_if \n connect slots_16.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[16].wakeup_ports[1].bits.uop.bp_debug_if \n connect slots_16.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[16].wakeup_ports[1].bits.uop.xcpt_ma_if \n connect slots_16.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[16].wakeup_ports[1].bits.uop.xcpt_ae_if \n connect slots_16.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[16].wakeup_ports[1].bits.uop.xcpt_pf_if \n connect slots_16.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[16].wakeup_ports[1].bits.uop.fp_typ \n connect slots_16.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[16].wakeup_ports[1].bits.uop.fp_rm \n connect slots_16.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[16].wakeup_ports[1].bits.uop.fp_val \n connect slots_16.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[16].wakeup_ports[1].bits.uop.fcn_op \n connect slots_16.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[16].wakeup_ports[1].bits.uop.fcn_dw \n connect slots_16.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[16].wakeup_ports[1].bits.uop.frs3_en \n connect slots_16.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[16].wakeup_ports[1].bits.uop.lrs2_rtype \n connect slots_16.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[16].wakeup_ports[1].bits.uop.lrs1_rtype \n connect slots_16.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[16].wakeup_ports[1].bits.uop.dst_rtype \n connect slots_16.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[16].wakeup_ports[1].bits.uop.lrs3 \n connect slots_16.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[16].wakeup_ports[1].bits.uop.lrs2 \n connect slots_16.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[16].wakeup_ports[1].bits.uop.lrs1 \n connect slots_16.io.wakeup_ports[1].bits.uop.ldst, issue_slots[16].wakeup_ports[1].bits.uop.ldst \n connect slots_16.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[16].wakeup_ports[1].bits.uop.ldst_is_rs1 \n connect slots_16.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[16].wakeup_ports[1].bits.uop.csr_cmd \n connect slots_16.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[16].wakeup_ports[1].bits.uop.flush_on_commit \n connect slots_16.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[16].wakeup_ports[1].bits.uop.is_unique \n connect slots_16.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[16].wakeup_ports[1].bits.uop.uses_stq \n connect slots_16.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[16].wakeup_ports[1].bits.uop.uses_ldq \n connect slots_16.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[16].wakeup_ports[1].bits.uop.mem_signed \n connect slots_16.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[16].wakeup_ports[1].bits.uop.mem_size \n connect slots_16.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[16].wakeup_ports[1].bits.uop.mem_cmd \n connect slots_16.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[16].wakeup_ports[1].bits.uop.exc_cause \n connect slots_16.io.wakeup_ports[1].bits.uop.exception, issue_slots[16].wakeup_ports[1].bits.uop.exception \n connect slots_16.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[16].wakeup_ports[1].bits.uop.stale_pdst \n connect slots_16.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[16].wakeup_ports[1].bits.uop.ppred_busy \n connect slots_16.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[16].wakeup_ports[1].bits.uop.prs3_busy \n connect slots_16.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[16].wakeup_ports[1].bits.uop.prs2_busy \n connect slots_16.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[16].wakeup_ports[1].bits.uop.prs1_busy \n connect slots_16.io.wakeup_ports[1].bits.uop.ppred, issue_slots[16].wakeup_ports[1].bits.uop.ppred \n connect slots_16.io.wakeup_ports[1].bits.uop.prs3, issue_slots[16].wakeup_ports[1].bits.uop.prs3 \n connect slots_16.io.wakeup_ports[1].bits.uop.prs2, issue_slots[16].wakeup_ports[1].bits.uop.prs2 \n connect slots_16.io.wakeup_ports[1].bits.uop.prs1, issue_slots[16].wakeup_ports[1].bits.uop.prs1 \n connect slots_16.io.wakeup_ports[1].bits.uop.pdst, issue_slots[16].wakeup_ports[1].bits.uop.pdst \n connect slots_16.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[16].wakeup_ports[1].bits.uop.rxq_idx \n connect slots_16.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[16].wakeup_ports[1].bits.uop.stq_idx \n connect slots_16.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[16].wakeup_ports[1].bits.uop.ldq_idx \n connect slots_16.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[16].wakeup_ports[1].bits.uop.rob_idx \n connect slots_16.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.vec \n connect slots_16.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.wflags \n connect slots_16.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.sqrt \n connect slots_16.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.div \n connect slots_16.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.fma \n connect slots_16.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe \n connect slots_16.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.toint \n connect slots_16.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.fromint \n connect slots_16.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut \n connect slots_16.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn \n connect slots_16.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.swap23 \n connect slots_16.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.swap12 \n connect slots_16.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.ren3 \n connect slots_16.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.ren2 \n connect slots_16.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.ren1 \n connect slots_16.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.wen \n connect slots_16.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.ldst \n connect slots_16.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[16].wakeup_ports[1].bits.uop.op2_sel \n connect slots_16.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[16].wakeup_ports[1].bits.uop.op1_sel \n connect slots_16.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[16].wakeup_ports[1].bits.uop.imm_packed \n connect slots_16.io.wakeup_ports[1].bits.uop.pimm, issue_slots[16].wakeup_ports[1].bits.uop.pimm \n connect slots_16.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[16].wakeup_ports[1].bits.uop.imm_sel \n connect slots_16.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[16].wakeup_ports[1].bits.uop.imm_rename \n connect slots_16.io.wakeup_ports[1].bits.uop.taken, issue_slots[16].wakeup_ports[1].bits.uop.taken \n connect slots_16.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[16].wakeup_ports[1].bits.uop.pc_lob \n connect slots_16.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[16].wakeup_ports[1].bits.uop.edge_inst \n connect slots_16.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[16].wakeup_ports[1].bits.uop.ftq_idx \n connect slots_16.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[16].wakeup_ports[1].bits.uop.is_mov \n connect slots_16.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[16].wakeup_ports[1].bits.uop.is_rocc \n connect slots_16.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[16].wakeup_ports[1].bits.uop.is_sys_pc2epc \n connect slots_16.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[16].wakeup_ports[1].bits.uop.is_eret \n connect slots_16.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[16].wakeup_ports[1].bits.uop.is_amo \n connect slots_16.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[16].wakeup_ports[1].bits.uop.is_sfence \n connect slots_16.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[16].wakeup_ports[1].bits.uop.is_fencei \n connect slots_16.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[16].wakeup_ports[1].bits.uop.is_fence \n connect slots_16.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[16].wakeup_ports[1].bits.uop.is_sfb \n connect slots_16.io.wakeup_ports[1].bits.uop.br_type, issue_slots[16].wakeup_ports[1].bits.uop.br_type \n connect slots_16.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[16].wakeup_ports[1].bits.uop.br_tag \n connect slots_16.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[16].wakeup_ports[1].bits.uop.br_mask \n connect slots_16.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[16].wakeup_ports[1].bits.uop.dis_col_sel \n connect slots_16.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[16].wakeup_ports[1].bits.uop.iw_p3_bypass_hint \n connect slots_16.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[16].wakeup_ports[1].bits.uop.iw_p2_bypass_hint \n connect slots_16.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[16].wakeup_ports[1].bits.uop.iw_p1_bypass_hint \n connect slots_16.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[16].wakeup_ports[1].bits.uop.iw_p2_speculative_child \n connect slots_16.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[16].wakeup_ports[1].bits.uop.iw_p1_speculative_child \n connect slots_16.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[16].wakeup_ports[1].bits.uop.iw_issued_partial_dgen \n connect slots_16.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[16].wakeup_ports[1].bits.uop.iw_issued_partial_agen \n connect slots_16.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[16].wakeup_ports[1].bits.uop.iw_issued \n connect slots_16.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[16].wakeup_ports[1].bits.uop.fu_code[0] \n connect slots_16.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[16].wakeup_ports[1].bits.uop.fu_code[1] \n connect slots_16.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[16].wakeup_ports[1].bits.uop.fu_code[2] \n connect slots_16.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[16].wakeup_ports[1].bits.uop.fu_code[3] \n connect slots_16.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[16].wakeup_ports[1].bits.uop.fu_code[4] \n connect slots_16.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[16].wakeup_ports[1].bits.uop.fu_code[5] \n connect slots_16.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[16].wakeup_ports[1].bits.uop.fu_code[6] \n connect slots_16.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[16].wakeup_ports[1].bits.uop.fu_code[7] \n connect slots_16.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[16].wakeup_ports[1].bits.uop.fu_code[8] \n connect slots_16.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[16].wakeup_ports[1].bits.uop.fu_code[9] \n connect slots_16.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[16].wakeup_ports[1].bits.uop.iq_type[0] \n connect slots_16.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[16].wakeup_ports[1].bits.uop.iq_type[1] \n connect slots_16.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[16].wakeup_ports[1].bits.uop.iq_type[2] \n connect slots_16.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[16].wakeup_ports[1].bits.uop.iq_type[3] \n connect slots_16.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[16].wakeup_ports[1].bits.uop.debug_pc \n connect slots_16.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[16].wakeup_ports[1].bits.uop.is_rvc \n connect slots_16.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[16].wakeup_ports[1].bits.uop.debug_inst \n connect slots_16.io.wakeup_ports[1].bits.uop.inst, issue_slots[16].wakeup_ports[1].bits.uop.inst \n connect slots_16.io.wakeup_ports[1].valid, issue_slots[16].wakeup_ports[1].valid \n connect slots_16.io.wakeup_ports[2].bits.rebusy, issue_slots[16].wakeup_ports[2].bits.rebusy \n connect slots_16.io.wakeup_ports[2].bits.speculative_mask, issue_slots[16].wakeup_ports[2].bits.speculative_mask \n connect slots_16.io.wakeup_ports[2].bits.bypassable, issue_slots[16].wakeup_ports[2].bits.bypassable \n connect slots_16.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[16].wakeup_ports[2].bits.uop.debug_tsrc \n connect slots_16.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[16].wakeup_ports[2].bits.uop.debug_fsrc \n connect slots_16.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[16].wakeup_ports[2].bits.uop.bp_xcpt_if \n connect slots_16.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[16].wakeup_ports[2].bits.uop.bp_debug_if \n connect slots_16.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[16].wakeup_ports[2].bits.uop.xcpt_ma_if \n connect slots_16.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[16].wakeup_ports[2].bits.uop.xcpt_ae_if \n connect slots_16.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[16].wakeup_ports[2].bits.uop.xcpt_pf_if \n connect slots_16.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[16].wakeup_ports[2].bits.uop.fp_typ \n connect slots_16.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[16].wakeup_ports[2].bits.uop.fp_rm \n connect slots_16.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[16].wakeup_ports[2].bits.uop.fp_val \n connect slots_16.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[16].wakeup_ports[2].bits.uop.fcn_op \n connect slots_16.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[16].wakeup_ports[2].bits.uop.fcn_dw \n connect slots_16.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[16].wakeup_ports[2].bits.uop.frs3_en \n connect slots_16.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[16].wakeup_ports[2].bits.uop.lrs2_rtype \n connect slots_16.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[16].wakeup_ports[2].bits.uop.lrs1_rtype \n connect slots_16.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[16].wakeup_ports[2].bits.uop.dst_rtype \n connect slots_16.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[16].wakeup_ports[2].bits.uop.lrs3 \n connect slots_16.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[16].wakeup_ports[2].bits.uop.lrs2 \n connect slots_16.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[16].wakeup_ports[2].bits.uop.lrs1 \n connect slots_16.io.wakeup_ports[2].bits.uop.ldst, issue_slots[16].wakeup_ports[2].bits.uop.ldst \n connect slots_16.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[16].wakeup_ports[2].bits.uop.ldst_is_rs1 \n connect slots_16.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[16].wakeup_ports[2].bits.uop.csr_cmd \n connect slots_16.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[16].wakeup_ports[2].bits.uop.flush_on_commit \n connect slots_16.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[16].wakeup_ports[2].bits.uop.is_unique \n connect slots_16.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[16].wakeup_ports[2].bits.uop.uses_stq \n connect slots_16.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[16].wakeup_ports[2].bits.uop.uses_ldq \n connect slots_16.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[16].wakeup_ports[2].bits.uop.mem_signed \n connect slots_16.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[16].wakeup_ports[2].bits.uop.mem_size \n connect slots_16.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[16].wakeup_ports[2].bits.uop.mem_cmd \n connect slots_16.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[16].wakeup_ports[2].bits.uop.exc_cause \n connect slots_16.io.wakeup_ports[2].bits.uop.exception, issue_slots[16].wakeup_ports[2].bits.uop.exception \n connect slots_16.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[16].wakeup_ports[2].bits.uop.stale_pdst \n connect slots_16.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[16].wakeup_ports[2].bits.uop.ppred_busy \n connect slots_16.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[16].wakeup_ports[2].bits.uop.prs3_busy \n connect slots_16.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[16].wakeup_ports[2].bits.uop.prs2_busy \n connect slots_16.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[16].wakeup_ports[2].bits.uop.prs1_busy \n connect slots_16.io.wakeup_ports[2].bits.uop.ppred, issue_slots[16].wakeup_ports[2].bits.uop.ppred \n connect slots_16.io.wakeup_ports[2].bits.uop.prs3, issue_slots[16].wakeup_ports[2].bits.uop.prs3 \n connect slots_16.io.wakeup_ports[2].bits.uop.prs2, issue_slots[16].wakeup_ports[2].bits.uop.prs2 \n connect slots_16.io.wakeup_ports[2].bits.uop.prs1, issue_slots[16].wakeup_ports[2].bits.uop.prs1 \n connect slots_16.io.wakeup_ports[2].bits.uop.pdst, issue_slots[16].wakeup_ports[2].bits.uop.pdst \n connect slots_16.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[16].wakeup_ports[2].bits.uop.rxq_idx \n connect slots_16.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[16].wakeup_ports[2].bits.uop.stq_idx \n connect slots_16.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[16].wakeup_ports[2].bits.uop.ldq_idx \n connect slots_16.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[16].wakeup_ports[2].bits.uop.rob_idx \n connect slots_16.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.vec \n connect slots_16.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.wflags \n connect slots_16.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.sqrt \n connect slots_16.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.div \n connect slots_16.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.fma \n connect slots_16.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe \n connect slots_16.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.toint \n connect slots_16.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.fromint \n connect slots_16.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut \n connect slots_16.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn \n connect slots_16.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.swap23 \n connect slots_16.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.swap12 \n connect slots_16.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.ren3 \n connect slots_16.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.ren2 \n connect slots_16.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.ren1 \n connect slots_16.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.wen \n connect slots_16.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.ldst \n connect slots_16.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[16].wakeup_ports[2].bits.uop.op2_sel \n connect slots_16.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[16].wakeup_ports[2].bits.uop.op1_sel \n connect slots_16.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[16].wakeup_ports[2].bits.uop.imm_packed \n connect slots_16.io.wakeup_ports[2].bits.uop.pimm, issue_slots[16].wakeup_ports[2].bits.uop.pimm \n connect slots_16.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[16].wakeup_ports[2].bits.uop.imm_sel \n connect slots_16.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[16].wakeup_ports[2].bits.uop.imm_rename \n connect slots_16.io.wakeup_ports[2].bits.uop.taken, issue_slots[16].wakeup_ports[2].bits.uop.taken \n connect slots_16.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[16].wakeup_ports[2].bits.uop.pc_lob \n connect slots_16.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[16].wakeup_ports[2].bits.uop.edge_inst \n connect slots_16.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[16].wakeup_ports[2].bits.uop.ftq_idx \n connect slots_16.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[16].wakeup_ports[2].bits.uop.is_mov \n connect slots_16.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[16].wakeup_ports[2].bits.uop.is_rocc \n connect slots_16.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[16].wakeup_ports[2].bits.uop.is_sys_pc2epc \n connect slots_16.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[16].wakeup_ports[2].bits.uop.is_eret \n connect slots_16.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[16].wakeup_ports[2].bits.uop.is_amo \n connect slots_16.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[16].wakeup_ports[2].bits.uop.is_sfence \n connect slots_16.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[16].wakeup_ports[2].bits.uop.is_fencei \n connect slots_16.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[16].wakeup_ports[2].bits.uop.is_fence \n connect slots_16.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[16].wakeup_ports[2].bits.uop.is_sfb \n connect slots_16.io.wakeup_ports[2].bits.uop.br_type, issue_slots[16].wakeup_ports[2].bits.uop.br_type \n connect slots_16.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[16].wakeup_ports[2].bits.uop.br_tag \n connect slots_16.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[16].wakeup_ports[2].bits.uop.br_mask \n connect slots_16.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[16].wakeup_ports[2].bits.uop.dis_col_sel \n connect slots_16.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[16].wakeup_ports[2].bits.uop.iw_p3_bypass_hint \n connect slots_16.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[16].wakeup_ports[2].bits.uop.iw_p2_bypass_hint \n connect slots_16.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[16].wakeup_ports[2].bits.uop.iw_p1_bypass_hint \n connect slots_16.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[16].wakeup_ports[2].bits.uop.iw_p2_speculative_child \n connect slots_16.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[16].wakeup_ports[2].bits.uop.iw_p1_speculative_child \n connect slots_16.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[16].wakeup_ports[2].bits.uop.iw_issued_partial_dgen \n connect slots_16.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[16].wakeup_ports[2].bits.uop.iw_issued_partial_agen \n connect slots_16.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[16].wakeup_ports[2].bits.uop.iw_issued \n connect slots_16.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[16].wakeup_ports[2].bits.uop.fu_code[0] \n connect slots_16.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[16].wakeup_ports[2].bits.uop.fu_code[1] \n connect slots_16.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[16].wakeup_ports[2].bits.uop.fu_code[2] \n connect slots_16.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[16].wakeup_ports[2].bits.uop.fu_code[3] \n connect slots_16.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[16].wakeup_ports[2].bits.uop.fu_code[4] \n connect slots_16.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[16].wakeup_ports[2].bits.uop.fu_code[5] \n connect slots_16.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[16].wakeup_ports[2].bits.uop.fu_code[6] \n connect slots_16.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[16].wakeup_ports[2].bits.uop.fu_code[7] \n connect slots_16.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[16].wakeup_ports[2].bits.uop.fu_code[8] \n connect slots_16.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[16].wakeup_ports[2].bits.uop.fu_code[9] \n connect slots_16.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[16].wakeup_ports[2].bits.uop.iq_type[0] \n connect slots_16.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[16].wakeup_ports[2].bits.uop.iq_type[1] \n connect slots_16.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[16].wakeup_ports[2].bits.uop.iq_type[2] \n connect slots_16.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[16].wakeup_ports[2].bits.uop.iq_type[3] \n connect slots_16.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[16].wakeup_ports[2].bits.uop.debug_pc \n connect slots_16.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[16].wakeup_ports[2].bits.uop.is_rvc \n connect slots_16.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[16].wakeup_ports[2].bits.uop.debug_inst \n connect slots_16.io.wakeup_ports[2].bits.uop.inst, issue_slots[16].wakeup_ports[2].bits.uop.inst \n connect slots_16.io.wakeup_ports[2].valid, issue_slots[16].wakeup_ports[2].valid \n connect slots_16.io.wakeup_ports[3].bits.rebusy, issue_slots[16].wakeup_ports[3].bits.rebusy \n connect slots_16.io.wakeup_ports[3].bits.speculative_mask, issue_slots[16].wakeup_ports[3].bits.speculative_mask \n connect slots_16.io.wakeup_ports[3].bits.bypassable, issue_slots[16].wakeup_ports[3].bits.bypassable \n connect slots_16.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[16].wakeup_ports[3].bits.uop.debug_tsrc \n connect slots_16.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[16].wakeup_ports[3].bits.uop.debug_fsrc \n connect slots_16.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[16].wakeup_ports[3].bits.uop.bp_xcpt_if \n connect slots_16.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[16].wakeup_ports[3].bits.uop.bp_debug_if \n connect slots_16.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[16].wakeup_ports[3].bits.uop.xcpt_ma_if \n connect slots_16.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[16].wakeup_ports[3].bits.uop.xcpt_ae_if \n connect slots_16.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[16].wakeup_ports[3].bits.uop.xcpt_pf_if \n connect slots_16.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[16].wakeup_ports[3].bits.uop.fp_typ \n connect slots_16.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[16].wakeup_ports[3].bits.uop.fp_rm \n connect slots_16.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[16].wakeup_ports[3].bits.uop.fp_val \n connect slots_16.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[16].wakeup_ports[3].bits.uop.fcn_op \n connect slots_16.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[16].wakeup_ports[3].bits.uop.fcn_dw \n connect slots_16.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[16].wakeup_ports[3].bits.uop.frs3_en \n connect slots_16.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[16].wakeup_ports[3].bits.uop.lrs2_rtype \n connect slots_16.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[16].wakeup_ports[3].bits.uop.lrs1_rtype \n connect slots_16.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[16].wakeup_ports[3].bits.uop.dst_rtype \n connect slots_16.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[16].wakeup_ports[3].bits.uop.lrs3 \n connect slots_16.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[16].wakeup_ports[3].bits.uop.lrs2 \n connect slots_16.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[16].wakeup_ports[3].bits.uop.lrs1 \n connect slots_16.io.wakeup_ports[3].bits.uop.ldst, issue_slots[16].wakeup_ports[3].bits.uop.ldst \n connect slots_16.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[16].wakeup_ports[3].bits.uop.ldst_is_rs1 \n connect slots_16.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[16].wakeup_ports[3].bits.uop.csr_cmd \n connect slots_16.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[16].wakeup_ports[3].bits.uop.flush_on_commit \n connect slots_16.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[16].wakeup_ports[3].bits.uop.is_unique \n connect slots_16.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[16].wakeup_ports[3].bits.uop.uses_stq \n connect slots_16.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[16].wakeup_ports[3].bits.uop.uses_ldq \n connect slots_16.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[16].wakeup_ports[3].bits.uop.mem_signed \n connect slots_16.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[16].wakeup_ports[3].bits.uop.mem_size \n connect slots_16.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[16].wakeup_ports[3].bits.uop.mem_cmd \n connect slots_16.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[16].wakeup_ports[3].bits.uop.exc_cause \n connect slots_16.io.wakeup_ports[3].bits.uop.exception, issue_slots[16].wakeup_ports[3].bits.uop.exception \n connect slots_16.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[16].wakeup_ports[3].bits.uop.stale_pdst \n connect slots_16.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[16].wakeup_ports[3].bits.uop.ppred_busy \n connect slots_16.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[16].wakeup_ports[3].bits.uop.prs3_busy \n connect slots_16.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[16].wakeup_ports[3].bits.uop.prs2_busy \n connect slots_16.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[16].wakeup_ports[3].bits.uop.prs1_busy \n connect slots_16.io.wakeup_ports[3].bits.uop.ppred, issue_slots[16].wakeup_ports[3].bits.uop.ppred \n connect slots_16.io.wakeup_ports[3].bits.uop.prs3, issue_slots[16].wakeup_ports[3].bits.uop.prs3 \n connect slots_16.io.wakeup_ports[3].bits.uop.prs2, issue_slots[16].wakeup_ports[3].bits.uop.prs2 \n connect slots_16.io.wakeup_ports[3].bits.uop.prs1, issue_slots[16].wakeup_ports[3].bits.uop.prs1 \n connect slots_16.io.wakeup_ports[3].bits.uop.pdst, issue_slots[16].wakeup_ports[3].bits.uop.pdst \n connect slots_16.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[16].wakeup_ports[3].bits.uop.rxq_idx \n connect slots_16.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[16].wakeup_ports[3].bits.uop.stq_idx \n connect slots_16.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[16].wakeup_ports[3].bits.uop.ldq_idx \n connect slots_16.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[16].wakeup_ports[3].bits.uop.rob_idx \n connect slots_16.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.vec \n connect slots_16.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.wflags \n connect slots_16.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.sqrt \n connect slots_16.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.div \n connect slots_16.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.fma \n connect slots_16.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe \n connect slots_16.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.toint \n connect slots_16.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.fromint \n connect slots_16.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut \n connect slots_16.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn \n connect slots_16.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.swap23 \n connect slots_16.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.swap12 \n connect slots_16.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.ren3 \n connect slots_16.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.ren2 \n connect slots_16.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.ren1 \n connect slots_16.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.wen \n connect slots_16.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.ldst \n connect slots_16.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[16].wakeup_ports[3].bits.uop.op2_sel \n connect slots_16.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[16].wakeup_ports[3].bits.uop.op1_sel \n connect slots_16.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[16].wakeup_ports[3].bits.uop.imm_packed \n connect slots_16.io.wakeup_ports[3].bits.uop.pimm, issue_slots[16].wakeup_ports[3].bits.uop.pimm \n connect slots_16.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[16].wakeup_ports[3].bits.uop.imm_sel \n connect slots_16.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[16].wakeup_ports[3].bits.uop.imm_rename \n connect slots_16.io.wakeup_ports[3].bits.uop.taken, issue_slots[16].wakeup_ports[3].bits.uop.taken \n connect slots_16.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[16].wakeup_ports[3].bits.uop.pc_lob \n connect slots_16.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[16].wakeup_ports[3].bits.uop.edge_inst \n connect slots_16.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[16].wakeup_ports[3].bits.uop.ftq_idx \n connect slots_16.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[16].wakeup_ports[3].bits.uop.is_mov \n connect slots_16.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[16].wakeup_ports[3].bits.uop.is_rocc \n connect slots_16.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[16].wakeup_ports[3].bits.uop.is_sys_pc2epc \n connect slots_16.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[16].wakeup_ports[3].bits.uop.is_eret \n connect slots_16.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[16].wakeup_ports[3].bits.uop.is_amo \n connect slots_16.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[16].wakeup_ports[3].bits.uop.is_sfence \n connect slots_16.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[16].wakeup_ports[3].bits.uop.is_fencei \n connect slots_16.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[16].wakeup_ports[3].bits.uop.is_fence \n connect slots_16.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[16].wakeup_ports[3].bits.uop.is_sfb \n connect slots_16.io.wakeup_ports[3].bits.uop.br_type, issue_slots[16].wakeup_ports[3].bits.uop.br_type \n connect slots_16.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[16].wakeup_ports[3].bits.uop.br_tag \n connect slots_16.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[16].wakeup_ports[3].bits.uop.br_mask \n connect slots_16.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[16].wakeup_ports[3].bits.uop.dis_col_sel \n connect slots_16.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[16].wakeup_ports[3].bits.uop.iw_p3_bypass_hint \n connect slots_16.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[16].wakeup_ports[3].bits.uop.iw_p2_bypass_hint \n connect slots_16.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[16].wakeup_ports[3].bits.uop.iw_p1_bypass_hint \n connect slots_16.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[16].wakeup_ports[3].bits.uop.iw_p2_speculative_child \n connect slots_16.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[16].wakeup_ports[3].bits.uop.iw_p1_speculative_child \n connect slots_16.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[16].wakeup_ports[3].bits.uop.iw_issued_partial_dgen \n connect slots_16.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[16].wakeup_ports[3].bits.uop.iw_issued_partial_agen \n connect slots_16.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[16].wakeup_ports[3].bits.uop.iw_issued \n connect slots_16.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[16].wakeup_ports[3].bits.uop.fu_code[0] \n connect slots_16.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[16].wakeup_ports[3].bits.uop.fu_code[1] \n connect slots_16.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[16].wakeup_ports[3].bits.uop.fu_code[2] \n connect slots_16.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[16].wakeup_ports[3].bits.uop.fu_code[3] \n connect slots_16.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[16].wakeup_ports[3].bits.uop.fu_code[4] \n connect slots_16.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[16].wakeup_ports[3].bits.uop.fu_code[5] \n connect slots_16.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[16].wakeup_ports[3].bits.uop.fu_code[6] \n connect slots_16.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[16].wakeup_ports[3].bits.uop.fu_code[7] \n connect slots_16.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[16].wakeup_ports[3].bits.uop.fu_code[8] \n connect slots_16.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[16].wakeup_ports[3].bits.uop.fu_code[9] \n connect slots_16.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[16].wakeup_ports[3].bits.uop.iq_type[0] \n connect slots_16.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[16].wakeup_ports[3].bits.uop.iq_type[1] \n connect slots_16.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[16].wakeup_ports[3].bits.uop.iq_type[2] \n connect slots_16.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[16].wakeup_ports[3].bits.uop.iq_type[3] \n connect slots_16.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[16].wakeup_ports[3].bits.uop.debug_pc \n connect slots_16.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[16].wakeup_ports[3].bits.uop.is_rvc \n connect slots_16.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[16].wakeup_ports[3].bits.uop.debug_inst \n connect slots_16.io.wakeup_ports[3].bits.uop.inst, issue_slots[16].wakeup_ports[3].bits.uop.inst \n connect slots_16.io.wakeup_ports[3].valid, issue_slots[16].wakeup_ports[3].valid \n connect slots_16.io.squash_grant, issue_slots[16].squash_grant \n connect slots_16.io.clear, issue_slots[16].clear \n connect slots_16.io.kill, issue_slots[16].kill \n connect slots_16.io.brupdate.b2.target_offset, issue_slots[16].brupdate.b2.target_offset \n connect slots_16.io.brupdate.b2.jalr_target, issue_slots[16].brupdate.b2.jalr_target \n connect slots_16.io.brupdate.b2.pc_sel, issue_slots[16].brupdate.b2.pc_sel \n connect slots_16.io.brupdate.b2.cfi_type, issue_slots[16].brupdate.b2.cfi_type \n connect slots_16.io.brupdate.b2.taken, issue_slots[16].brupdate.b2.taken \n connect slots_16.io.brupdate.b2.mispredict, issue_slots[16].brupdate.b2.mispredict \n connect slots_16.io.brupdate.b2.uop.debug_tsrc, issue_slots[16].brupdate.b2.uop.debug_tsrc \n connect slots_16.io.brupdate.b2.uop.debug_fsrc, issue_slots[16].brupdate.b2.uop.debug_fsrc \n connect slots_16.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[16].brupdate.b2.uop.bp_xcpt_if \n connect slots_16.io.brupdate.b2.uop.bp_debug_if, issue_slots[16].brupdate.b2.uop.bp_debug_if \n connect slots_16.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[16].brupdate.b2.uop.xcpt_ma_if \n connect slots_16.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[16].brupdate.b2.uop.xcpt_ae_if \n connect slots_16.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[16].brupdate.b2.uop.xcpt_pf_if \n connect slots_16.io.brupdate.b2.uop.fp_typ, issue_slots[16].brupdate.b2.uop.fp_typ \n connect slots_16.io.brupdate.b2.uop.fp_rm, issue_slots[16].brupdate.b2.uop.fp_rm \n connect slots_16.io.brupdate.b2.uop.fp_val, issue_slots[16].brupdate.b2.uop.fp_val \n connect slots_16.io.brupdate.b2.uop.fcn_op, issue_slots[16].brupdate.b2.uop.fcn_op \n connect slots_16.io.brupdate.b2.uop.fcn_dw, issue_slots[16].brupdate.b2.uop.fcn_dw \n connect slots_16.io.brupdate.b2.uop.frs3_en, issue_slots[16].brupdate.b2.uop.frs3_en \n connect slots_16.io.brupdate.b2.uop.lrs2_rtype, issue_slots[16].brupdate.b2.uop.lrs2_rtype \n connect slots_16.io.brupdate.b2.uop.lrs1_rtype, issue_slots[16].brupdate.b2.uop.lrs1_rtype \n connect slots_16.io.brupdate.b2.uop.dst_rtype, issue_slots[16].brupdate.b2.uop.dst_rtype \n connect slots_16.io.brupdate.b2.uop.lrs3, issue_slots[16].brupdate.b2.uop.lrs3 \n connect slots_16.io.brupdate.b2.uop.lrs2, issue_slots[16].brupdate.b2.uop.lrs2 \n connect slots_16.io.brupdate.b2.uop.lrs1, issue_slots[16].brupdate.b2.uop.lrs1 \n connect slots_16.io.brupdate.b2.uop.ldst, issue_slots[16].brupdate.b2.uop.ldst \n connect slots_16.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[16].brupdate.b2.uop.ldst_is_rs1 \n connect slots_16.io.brupdate.b2.uop.csr_cmd, issue_slots[16].brupdate.b2.uop.csr_cmd \n connect slots_16.io.brupdate.b2.uop.flush_on_commit, issue_slots[16].brupdate.b2.uop.flush_on_commit \n connect slots_16.io.brupdate.b2.uop.is_unique, issue_slots[16].brupdate.b2.uop.is_unique \n connect slots_16.io.brupdate.b2.uop.uses_stq, issue_slots[16].brupdate.b2.uop.uses_stq \n connect slots_16.io.brupdate.b2.uop.uses_ldq, issue_slots[16].brupdate.b2.uop.uses_ldq \n connect slots_16.io.brupdate.b2.uop.mem_signed, issue_slots[16].brupdate.b2.uop.mem_signed \n connect slots_16.io.brupdate.b2.uop.mem_size, issue_slots[16].brupdate.b2.uop.mem_size \n connect slots_16.io.brupdate.b2.uop.mem_cmd, issue_slots[16].brupdate.b2.uop.mem_cmd \n connect slots_16.io.brupdate.b2.uop.exc_cause, issue_slots[16].brupdate.b2.uop.exc_cause \n connect slots_16.io.brupdate.b2.uop.exception, issue_slots[16].brupdate.b2.uop.exception \n connect slots_16.io.brupdate.b2.uop.stale_pdst, issue_slots[16].brupdate.b2.uop.stale_pdst \n connect slots_16.io.brupdate.b2.uop.ppred_busy, issue_slots[16].brupdate.b2.uop.ppred_busy \n connect slots_16.io.brupdate.b2.uop.prs3_busy, issue_slots[16].brupdate.b2.uop.prs3_busy \n connect slots_16.io.brupdate.b2.uop.prs2_busy, issue_slots[16].brupdate.b2.uop.prs2_busy \n connect slots_16.io.brupdate.b2.uop.prs1_busy, issue_slots[16].brupdate.b2.uop.prs1_busy \n connect slots_16.io.brupdate.b2.uop.ppred, issue_slots[16].brupdate.b2.uop.ppred \n connect slots_16.io.brupdate.b2.uop.prs3, issue_slots[16].brupdate.b2.uop.prs3 \n connect slots_16.io.brupdate.b2.uop.prs2, issue_slots[16].brupdate.b2.uop.prs2 \n connect slots_16.io.brupdate.b2.uop.prs1, issue_slots[16].brupdate.b2.uop.prs1 \n connect slots_16.io.brupdate.b2.uop.pdst, issue_slots[16].brupdate.b2.uop.pdst \n connect slots_16.io.brupdate.b2.uop.rxq_idx, issue_slots[16].brupdate.b2.uop.rxq_idx \n connect slots_16.io.brupdate.b2.uop.stq_idx, issue_slots[16].brupdate.b2.uop.stq_idx \n connect slots_16.io.brupdate.b2.uop.ldq_idx, issue_slots[16].brupdate.b2.uop.ldq_idx \n connect slots_16.io.brupdate.b2.uop.rob_idx, issue_slots[16].brupdate.b2.uop.rob_idx \n connect slots_16.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[16].brupdate.b2.uop.fp_ctrl.vec \n connect slots_16.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[16].brupdate.b2.uop.fp_ctrl.wflags \n connect slots_16.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[16].brupdate.b2.uop.fp_ctrl.sqrt \n connect slots_16.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[16].brupdate.b2.uop.fp_ctrl.div \n connect slots_16.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[16].brupdate.b2.uop.fp_ctrl.fma \n connect slots_16.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[16].brupdate.b2.uop.fp_ctrl.fastpipe \n connect slots_16.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[16].brupdate.b2.uop.fp_ctrl.toint \n connect slots_16.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[16].brupdate.b2.uop.fp_ctrl.fromint \n connect slots_16.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[16].brupdate.b2.uop.fp_ctrl.typeTagOut \n connect slots_16.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[16].brupdate.b2.uop.fp_ctrl.typeTagIn \n connect slots_16.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[16].brupdate.b2.uop.fp_ctrl.swap23 \n connect slots_16.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[16].brupdate.b2.uop.fp_ctrl.swap12 \n connect slots_16.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[16].brupdate.b2.uop.fp_ctrl.ren3 \n connect slots_16.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[16].brupdate.b2.uop.fp_ctrl.ren2 \n connect slots_16.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[16].brupdate.b2.uop.fp_ctrl.ren1 \n connect slots_16.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[16].brupdate.b2.uop.fp_ctrl.wen \n connect slots_16.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[16].brupdate.b2.uop.fp_ctrl.ldst \n connect slots_16.io.brupdate.b2.uop.op2_sel, issue_slots[16].brupdate.b2.uop.op2_sel \n connect slots_16.io.brupdate.b2.uop.op1_sel, issue_slots[16].brupdate.b2.uop.op1_sel \n connect slots_16.io.brupdate.b2.uop.imm_packed, issue_slots[16].brupdate.b2.uop.imm_packed \n connect slots_16.io.brupdate.b2.uop.pimm, issue_slots[16].brupdate.b2.uop.pimm \n connect slots_16.io.brupdate.b2.uop.imm_sel, issue_slots[16].brupdate.b2.uop.imm_sel \n connect slots_16.io.brupdate.b2.uop.imm_rename, issue_slots[16].brupdate.b2.uop.imm_rename \n connect slots_16.io.brupdate.b2.uop.taken, issue_slots[16].brupdate.b2.uop.taken \n connect slots_16.io.brupdate.b2.uop.pc_lob, issue_slots[16].brupdate.b2.uop.pc_lob \n connect slots_16.io.brupdate.b2.uop.edge_inst, issue_slots[16].brupdate.b2.uop.edge_inst \n connect slots_16.io.brupdate.b2.uop.ftq_idx, issue_slots[16].brupdate.b2.uop.ftq_idx \n connect slots_16.io.brupdate.b2.uop.is_mov, issue_slots[16].brupdate.b2.uop.is_mov \n connect slots_16.io.brupdate.b2.uop.is_rocc, issue_slots[16].brupdate.b2.uop.is_rocc \n connect slots_16.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[16].brupdate.b2.uop.is_sys_pc2epc \n connect slots_16.io.brupdate.b2.uop.is_eret, issue_slots[16].brupdate.b2.uop.is_eret \n connect slots_16.io.brupdate.b2.uop.is_amo, issue_slots[16].brupdate.b2.uop.is_amo \n connect slots_16.io.brupdate.b2.uop.is_sfence, issue_slots[16].brupdate.b2.uop.is_sfence \n connect slots_16.io.brupdate.b2.uop.is_fencei, issue_slots[16].brupdate.b2.uop.is_fencei \n connect slots_16.io.brupdate.b2.uop.is_fence, issue_slots[16].brupdate.b2.uop.is_fence \n connect slots_16.io.brupdate.b2.uop.is_sfb, issue_slots[16].brupdate.b2.uop.is_sfb \n connect slots_16.io.brupdate.b2.uop.br_type, issue_slots[16].brupdate.b2.uop.br_type \n connect slots_16.io.brupdate.b2.uop.br_tag, issue_slots[16].brupdate.b2.uop.br_tag \n connect slots_16.io.brupdate.b2.uop.br_mask, issue_slots[16].brupdate.b2.uop.br_mask \n connect slots_16.io.brupdate.b2.uop.dis_col_sel, issue_slots[16].brupdate.b2.uop.dis_col_sel \n connect slots_16.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[16].brupdate.b2.uop.iw_p3_bypass_hint \n connect slots_16.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[16].brupdate.b2.uop.iw_p2_bypass_hint \n connect slots_16.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[16].brupdate.b2.uop.iw_p1_bypass_hint \n connect slots_16.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[16].brupdate.b2.uop.iw_p2_speculative_child \n connect slots_16.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[16].brupdate.b2.uop.iw_p1_speculative_child \n connect slots_16.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[16].brupdate.b2.uop.iw_issued_partial_dgen \n connect slots_16.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[16].brupdate.b2.uop.iw_issued_partial_agen \n connect slots_16.io.brupdate.b2.uop.iw_issued, issue_slots[16].brupdate.b2.uop.iw_issued \n connect slots_16.io.brupdate.b2.uop.fu_code[0], issue_slots[16].brupdate.b2.uop.fu_code[0] \n connect slots_16.io.brupdate.b2.uop.fu_code[1], issue_slots[16].brupdate.b2.uop.fu_code[1] \n connect slots_16.io.brupdate.b2.uop.fu_code[2], issue_slots[16].brupdate.b2.uop.fu_code[2] \n connect slots_16.io.brupdate.b2.uop.fu_code[3], issue_slots[16].brupdate.b2.uop.fu_code[3] \n connect slots_16.io.brupdate.b2.uop.fu_code[4], issue_slots[16].brupdate.b2.uop.fu_code[4] \n connect slots_16.io.brupdate.b2.uop.fu_code[5], issue_slots[16].brupdate.b2.uop.fu_code[5] \n connect slots_16.io.brupdate.b2.uop.fu_code[6], issue_slots[16].brupdate.b2.uop.fu_code[6] \n connect slots_16.io.brupdate.b2.uop.fu_code[7], issue_slots[16].brupdate.b2.uop.fu_code[7] \n connect slots_16.io.brupdate.b2.uop.fu_code[8], issue_slots[16].brupdate.b2.uop.fu_code[8] \n connect slots_16.io.brupdate.b2.uop.fu_code[9], issue_slots[16].brupdate.b2.uop.fu_code[9] \n connect slots_16.io.brupdate.b2.uop.iq_type[0], issue_slots[16].brupdate.b2.uop.iq_type[0] \n connect slots_16.io.brupdate.b2.uop.iq_type[1], issue_slots[16].brupdate.b2.uop.iq_type[1] \n connect slots_16.io.brupdate.b2.uop.iq_type[2], issue_slots[16].brupdate.b2.uop.iq_type[2] \n connect slots_16.io.brupdate.b2.uop.iq_type[3], issue_slots[16].brupdate.b2.uop.iq_type[3] \n connect slots_16.io.brupdate.b2.uop.debug_pc, issue_slots[16].brupdate.b2.uop.debug_pc \n connect slots_16.io.brupdate.b2.uop.is_rvc, issue_slots[16].brupdate.b2.uop.is_rvc \n connect slots_16.io.brupdate.b2.uop.debug_inst, issue_slots[16].brupdate.b2.uop.debug_inst \n connect slots_16.io.brupdate.b2.uop.inst, issue_slots[16].brupdate.b2.uop.inst \n connect slots_16.io.brupdate.b1.mispredict_mask, issue_slots[16].brupdate.b1.mispredict_mask \n connect slots_16.io.brupdate.b1.resolve_mask, issue_slots[16].brupdate.b1.resolve_mask \n connect issue_slots[16].out_uop.debug_tsrc, slots_16.io.out_uop.debug_tsrc \n connect issue_slots[16].out_uop.debug_fsrc, slots_16.io.out_uop.debug_fsrc \n connect issue_slots[16].out_uop.bp_xcpt_if, slots_16.io.out_uop.bp_xcpt_if \n connect issue_slots[16].out_uop.bp_debug_if, slots_16.io.out_uop.bp_debug_if \n connect issue_slots[16].out_uop.xcpt_ma_if, slots_16.io.out_uop.xcpt_ma_if \n connect issue_slots[16].out_uop.xcpt_ae_if, slots_16.io.out_uop.xcpt_ae_if \n connect issue_slots[16].out_uop.xcpt_pf_if, slots_16.io.out_uop.xcpt_pf_if \n connect issue_slots[16].out_uop.fp_typ, slots_16.io.out_uop.fp_typ \n connect issue_slots[16].out_uop.fp_rm, slots_16.io.out_uop.fp_rm \n connect issue_slots[16].out_uop.fp_val, slots_16.io.out_uop.fp_val \n connect issue_slots[16].out_uop.fcn_op, slots_16.io.out_uop.fcn_op \n connect issue_slots[16].out_uop.fcn_dw, slots_16.io.out_uop.fcn_dw \n connect issue_slots[16].out_uop.frs3_en, slots_16.io.out_uop.frs3_en \n connect issue_slots[16].out_uop.lrs2_rtype, slots_16.io.out_uop.lrs2_rtype \n connect issue_slots[16].out_uop.lrs1_rtype, slots_16.io.out_uop.lrs1_rtype \n connect issue_slots[16].out_uop.dst_rtype, slots_16.io.out_uop.dst_rtype \n connect issue_slots[16].out_uop.lrs3, slots_16.io.out_uop.lrs3 \n connect issue_slots[16].out_uop.lrs2, slots_16.io.out_uop.lrs2 \n connect issue_slots[16].out_uop.lrs1, slots_16.io.out_uop.lrs1 \n connect issue_slots[16].out_uop.ldst, slots_16.io.out_uop.ldst \n connect issue_slots[16].out_uop.ldst_is_rs1, slots_16.io.out_uop.ldst_is_rs1 \n connect issue_slots[16].out_uop.csr_cmd, slots_16.io.out_uop.csr_cmd \n connect issue_slots[16].out_uop.flush_on_commit, slots_16.io.out_uop.flush_on_commit \n connect issue_slots[16].out_uop.is_unique, slots_16.io.out_uop.is_unique \n connect issue_slots[16].out_uop.uses_stq, slots_16.io.out_uop.uses_stq \n connect issue_slots[16].out_uop.uses_ldq, slots_16.io.out_uop.uses_ldq \n connect issue_slots[16].out_uop.mem_signed, slots_16.io.out_uop.mem_signed \n connect issue_slots[16].out_uop.mem_size, slots_16.io.out_uop.mem_size \n connect issue_slots[16].out_uop.mem_cmd, slots_16.io.out_uop.mem_cmd \n connect issue_slots[16].out_uop.exc_cause, slots_16.io.out_uop.exc_cause \n connect issue_slots[16].out_uop.exception, slots_16.io.out_uop.exception \n connect issue_slots[16].out_uop.stale_pdst, slots_16.io.out_uop.stale_pdst \n connect issue_slots[16].out_uop.ppred_busy, slots_16.io.out_uop.ppred_busy \n connect issue_slots[16].out_uop.prs3_busy, slots_16.io.out_uop.prs3_busy \n connect issue_slots[16].out_uop.prs2_busy, slots_16.io.out_uop.prs2_busy \n connect issue_slots[16].out_uop.prs1_busy, slots_16.io.out_uop.prs1_busy \n connect issue_slots[16].out_uop.ppred, slots_16.io.out_uop.ppred \n connect issue_slots[16].out_uop.prs3, slots_16.io.out_uop.prs3 \n connect issue_slots[16].out_uop.prs2, slots_16.io.out_uop.prs2 \n connect issue_slots[16].out_uop.prs1, slots_16.io.out_uop.prs1 \n connect issue_slots[16].out_uop.pdst, slots_16.io.out_uop.pdst \n connect issue_slots[16].out_uop.rxq_idx, slots_16.io.out_uop.rxq_idx \n connect issue_slots[16].out_uop.stq_idx, slots_16.io.out_uop.stq_idx \n connect issue_slots[16].out_uop.ldq_idx, slots_16.io.out_uop.ldq_idx \n connect issue_slots[16].out_uop.rob_idx, slots_16.io.out_uop.rob_idx \n connect issue_slots[16].out_uop.fp_ctrl.vec, slots_16.io.out_uop.fp_ctrl.vec \n connect issue_slots[16].out_uop.fp_ctrl.wflags, slots_16.io.out_uop.fp_ctrl.wflags \n connect issue_slots[16].out_uop.fp_ctrl.sqrt, slots_16.io.out_uop.fp_ctrl.sqrt \n connect issue_slots[16].out_uop.fp_ctrl.div, slots_16.io.out_uop.fp_ctrl.div \n connect issue_slots[16].out_uop.fp_ctrl.fma, slots_16.io.out_uop.fp_ctrl.fma \n connect issue_slots[16].out_uop.fp_ctrl.fastpipe, slots_16.io.out_uop.fp_ctrl.fastpipe \n connect issue_slots[16].out_uop.fp_ctrl.toint, slots_16.io.out_uop.fp_ctrl.toint \n connect issue_slots[16].out_uop.fp_ctrl.fromint, slots_16.io.out_uop.fp_ctrl.fromint \n connect issue_slots[16].out_uop.fp_ctrl.typeTagOut, slots_16.io.out_uop.fp_ctrl.typeTagOut \n connect issue_slots[16].out_uop.fp_ctrl.typeTagIn, slots_16.io.out_uop.fp_ctrl.typeTagIn \n connect issue_slots[16].out_uop.fp_ctrl.swap23, slots_16.io.out_uop.fp_ctrl.swap23 \n connect issue_slots[16].out_uop.fp_ctrl.swap12, slots_16.io.out_uop.fp_ctrl.swap12 \n connect issue_slots[16].out_uop.fp_ctrl.ren3, slots_16.io.out_uop.fp_ctrl.ren3 \n connect issue_slots[16].out_uop.fp_ctrl.ren2, slots_16.io.out_uop.fp_ctrl.ren2 \n connect issue_slots[16].out_uop.fp_ctrl.ren1, slots_16.io.out_uop.fp_ctrl.ren1 \n connect issue_slots[16].out_uop.fp_ctrl.wen, slots_16.io.out_uop.fp_ctrl.wen \n connect issue_slots[16].out_uop.fp_ctrl.ldst, slots_16.io.out_uop.fp_ctrl.ldst \n connect issue_slots[16].out_uop.op2_sel, slots_16.io.out_uop.op2_sel \n connect issue_slots[16].out_uop.op1_sel, slots_16.io.out_uop.op1_sel \n connect issue_slots[16].out_uop.imm_packed, slots_16.io.out_uop.imm_packed \n connect issue_slots[16].out_uop.pimm, slots_16.io.out_uop.pimm \n connect issue_slots[16].out_uop.imm_sel, slots_16.io.out_uop.imm_sel \n connect issue_slots[16].out_uop.imm_rename, slots_16.io.out_uop.imm_rename \n connect issue_slots[16].out_uop.taken, slots_16.io.out_uop.taken \n connect issue_slots[16].out_uop.pc_lob, slots_16.io.out_uop.pc_lob \n connect issue_slots[16].out_uop.edge_inst, slots_16.io.out_uop.edge_inst \n connect issue_slots[16].out_uop.ftq_idx, slots_16.io.out_uop.ftq_idx \n connect issue_slots[16].out_uop.is_mov, slots_16.io.out_uop.is_mov \n connect issue_slots[16].out_uop.is_rocc, slots_16.io.out_uop.is_rocc \n connect issue_slots[16].out_uop.is_sys_pc2epc, slots_16.io.out_uop.is_sys_pc2epc \n connect issue_slots[16].out_uop.is_eret, slots_16.io.out_uop.is_eret \n connect issue_slots[16].out_uop.is_amo, slots_16.io.out_uop.is_amo \n connect issue_slots[16].out_uop.is_sfence, slots_16.io.out_uop.is_sfence \n connect issue_slots[16].out_uop.is_fencei, slots_16.io.out_uop.is_fencei \n connect issue_slots[16].out_uop.is_fence, slots_16.io.out_uop.is_fence \n connect issue_slots[16].out_uop.is_sfb, slots_16.io.out_uop.is_sfb \n connect issue_slots[16].out_uop.br_type, slots_16.io.out_uop.br_type \n connect issue_slots[16].out_uop.br_tag, slots_16.io.out_uop.br_tag \n connect issue_slots[16].out_uop.br_mask, slots_16.io.out_uop.br_mask \n connect issue_slots[16].out_uop.dis_col_sel, slots_16.io.out_uop.dis_col_sel \n connect issue_slots[16].out_uop.iw_p3_bypass_hint, slots_16.io.out_uop.iw_p3_bypass_hint \n connect issue_slots[16].out_uop.iw_p2_bypass_hint, slots_16.io.out_uop.iw_p2_bypass_hint \n connect issue_slots[16].out_uop.iw_p1_bypass_hint, slots_16.io.out_uop.iw_p1_bypass_hint \n connect issue_slots[16].out_uop.iw_p2_speculative_child, slots_16.io.out_uop.iw_p2_speculative_child \n connect issue_slots[16].out_uop.iw_p1_speculative_child, slots_16.io.out_uop.iw_p1_speculative_child \n connect issue_slots[16].out_uop.iw_issued_partial_dgen, slots_16.io.out_uop.iw_issued_partial_dgen \n connect issue_slots[16].out_uop.iw_issued_partial_agen, slots_16.io.out_uop.iw_issued_partial_agen \n connect issue_slots[16].out_uop.iw_issued, slots_16.io.out_uop.iw_issued \n connect issue_slots[16].out_uop.fu_code[0], slots_16.io.out_uop.fu_code[0] \n connect issue_slots[16].out_uop.fu_code[1], slots_16.io.out_uop.fu_code[1] \n connect issue_slots[16].out_uop.fu_code[2], slots_16.io.out_uop.fu_code[2] \n connect issue_slots[16].out_uop.fu_code[3], slots_16.io.out_uop.fu_code[3] \n connect issue_slots[16].out_uop.fu_code[4], slots_16.io.out_uop.fu_code[4] \n connect issue_slots[16].out_uop.fu_code[5], slots_16.io.out_uop.fu_code[5] \n connect issue_slots[16].out_uop.fu_code[6], slots_16.io.out_uop.fu_code[6] \n connect issue_slots[16].out_uop.fu_code[7], slots_16.io.out_uop.fu_code[7] \n connect issue_slots[16].out_uop.fu_code[8], slots_16.io.out_uop.fu_code[8] \n connect issue_slots[16].out_uop.fu_code[9], slots_16.io.out_uop.fu_code[9] \n connect issue_slots[16].out_uop.iq_type[0], slots_16.io.out_uop.iq_type[0] \n connect issue_slots[16].out_uop.iq_type[1], slots_16.io.out_uop.iq_type[1] \n connect issue_slots[16].out_uop.iq_type[2], slots_16.io.out_uop.iq_type[2] \n connect issue_slots[16].out_uop.iq_type[3], slots_16.io.out_uop.iq_type[3] \n connect issue_slots[16].out_uop.debug_pc, slots_16.io.out_uop.debug_pc \n connect issue_slots[16].out_uop.is_rvc, slots_16.io.out_uop.is_rvc \n connect issue_slots[16].out_uop.debug_inst, slots_16.io.out_uop.debug_inst \n connect issue_slots[16].out_uop.inst, slots_16.io.out_uop.inst \n connect slots_16.io.in_uop.bits.debug_tsrc, issue_slots[16].in_uop.bits.debug_tsrc \n connect slots_16.io.in_uop.bits.debug_fsrc, issue_slots[16].in_uop.bits.debug_fsrc \n connect slots_16.io.in_uop.bits.bp_xcpt_if, issue_slots[16].in_uop.bits.bp_xcpt_if \n connect slots_16.io.in_uop.bits.bp_debug_if, issue_slots[16].in_uop.bits.bp_debug_if \n connect slots_16.io.in_uop.bits.xcpt_ma_if, issue_slots[16].in_uop.bits.xcpt_ma_if \n connect slots_16.io.in_uop.bits.xcpt_ae_if, issue_slots[16].in_uop.bits.xcpt_ae_if \n connect slots_16.io.in_uop.bits.xcpt_pf_if, issue_slots[16].in_uop.bits.xcpt_pf_if \n connect slots_16.io.in_uop.bits.fp_typ, issue_slots[16].in_uop.bits.fp_typ \n connect slots_16.io.in_uop.bits.fp_rm, issue_slots[16].in_uop.bits.fp_rm \n connect slots_16.io.in_uop.bits.fp_val, issue_slots[16].in_uop.bits.fp_val \n connect slots_16.io.in_uop.bits.fcn_op, issue_slots[16].in_uop.bits.fcn_op \n connect slots_16.io.in_uop.bits.fcn_dw, issue_slots[16].in_uop.bits.fcn_dw \n connect slots_16.io.in_uop.bits.frs3_en, issue_slots[16].in_uop.bits.frs3_en \n connect slots_16.io.in_uop.bits.lrs2_rtype, issue_slots[16].in_uop.bits.lrs2_rtype \n connect slots_16.io.in_uop.bits.lrs1_rtype, issue_slots[16].in_uop.bits.lrs1_rtype \n connect slots_16.io.in_uop.bits.dst_rtype, issue_slots[16].in_uop.bits.dst_rtype \n connect slots_16.io.in_uop.bits.lrs3, issue_slots[16].in_uop.bits.lrs3 \n connect slots_16.io.in_uop.bits.lrs2, issue_slots[16].in_uop.bits.lrs2 \n connect slots_16.io.in_uop.bits.lrs1, issue_slots[16].in_uop.bits.lrs1 \n connect slots_16.io.in_uop.bits.ldst, issue_slots[16].in_uop.bits.ldst \n connect slots_16.io.in_uop.bits.ldst_is_rs1, issue_slots[16].in_uop.bits.ldst_is_rs1 \n connect slots_16.io.in_uop.bits.csr_cmd, issue_slots[16].in_uop.bits.csr_cmd \n connect slots_16.io.in_uop.bits.flush_on_commit, issue_slots[16].in_uop.bits.flush_on_commit \n connect slots_16.io.in_uop.bits.is_unique, issue_slots[16].in_uop.bits.is_unique \n connect slots_16.io.in_uop.bits.uses_stq, issue_slots[16].in_uop.bits.uses_stq \n connect slots_16.io.in_uop.bits.uses_ldq, issue_slots[16].in_uop.bits.uses_ldq \n connect slots_16.io.in_uop.bits.mem_signed, issue_slots[16].in_uop.bits.mem_signed \n connect slots_16.io.in_uop.bits.mem_size, issue_slots[16].in_uop.bits.mem_size \n connect slots_16.io.in_uop.bits.mem_cmd, issue_slots[16].in_uop.bits.mem_cmd \n connect slots_16.io.in_uop.bits.exc_cause, issue_slots[16].in_uop.bits.exc_cause \n connect slots_16.io.in_uop.bits.exception, issue_slots[16].in_uop.bits.exception \n connect slots_16.io.in_uop.bits.stale_pdst, issue_slots[16].in_uop.bits.stale_pdst \n connect slots_16.io.in_uop.bits.ppred_busy, issue_slots[16].in_uop.bits.ppred_busy \n connect slots_16.io.in_uop.bits.prs3_busy, issue_slots[16].in_uop.bits.prs3_busy \n connect slots_16.io.in_uop.bits.prs2_busy, issue_slots[16].in_uop.bits.prs2_busy \n connect slots_16.io.in_uop.bits.prs1_busy, issue_slots[16].in_uop.bits.prs1_busy \n connect slots_16.io.in_uop.bits.ppred, issue_slots[16].in_uop.bits.ppred \n connect slots_16.io.in_uop.bits.prs3, issue_slots[16].in_uop.bits.prs3 \n connect slots_16.io.in_uop.bits.prs2, issue_slots[16].in_uop.bits.prs2 \n connect slots_16.io.in_uop.bits.prs1, issue_slots[16].in_uop.bits.prs1 \n connect slots_16.io.in_uop.bits.pdst, issue_slots[16].in_uop.bits.pdst \n connect slots_16.io.in_uop.bits.rxq_idx, issue_slots[16].in_uop.bits.rxq_idx \n connect slots_16.io.in_uop.bits.stq_idx, issue_slots[16].in_uop.bits.stq_idx \n connect slots_16.io.in_uop.bits.ldq_idx, issue_slots[16].in_uop.bits.ldq_idx \n connect slots_16.io.in_uop.bits.rob_idx, issue_slots[16].in_uop.bits.rob_idx \n connect slots_16.io.in_uop.bits.fp_ctrl.vec, issue_slots[16].in_uop.bits.fp_ctrl.vec \n connect slots_16.io.in_uop.bits.fp_ctrl.wflags, issue_slots[16].in_uop.bits.fp_ctrl.wflags \n connect slots_16.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[16].in_uop.bits.fp_ctrl.sqrt \n connect slots_16.io.in_uop.bits.fp_ctrl.div, issue_slots[16].in_uop.bits.fp_ctrl.div \n connect slots_16.io.in_uop.bits.fp_ctrl.fma, issue_slots[16].in_uop.bits.fp_ctrl.fma \n connect slots_16.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[16].in_uop.bits.fp_ctrl.fastpipe \n connect slots_16.io.in_uop.bits.fp_ctrl.toint, issue_slots[16].in_uop.bits.fp_ctrl.toint \n connect slots_16.io.in_uop.bits.fp_ctrl.fromint, issue_slots[16].in_uop.bits.fp_ctrl.fromint \n connect slots_16.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[16].in_uop.bits.fp_ctrl.typeTagOut \n connect slots_16.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[16].in_uop.bits.fp_ctrl.typeTagIn \n connect slots_16.io.in_uop.bits.fp_ctrl.swap23, issue_slots[16].in_uop.bits.fp_ctrl.swap23 \n connect slots_16.io.in_uop.bits.fp_ctrl.swap12, issue_slots[16].in_uop.bits.fp_ctrl.swap12 \n connect slots_16.io.in_uop.bits.fp_ctrl.ren3, issue_slots[16].in_uop.bits.fp_ctrl.ren3 \n connect slots_16.io.in_uop.bits.fp_ctrl.ren2, issue_slots[16].in_uop.bits.fp_ctrl.ren2 \n connect slots_16.io.in_uop.bits.fp_ctrl.ren1, issue_slots[16].in_uop.bits.fp_ctrl.ren1 \n connect slots_16.io.in_uop.bits.fp_ctrl.wen, issue_slots[16].in_uop.bits.fp_ctrl.wen \n connect slots_16.io.in_uop.bits.fp_ctrl.ldst, issue_slots[16].in_uop.bits.fp_ctrl.ldst \n connect slots_16.io.in_uop.bits.op2_sel, issue_slots[16].in_uop.bits.op2_sel \n connect slots_16.io.in_uop.bits.op1_sel, issue_slots[16].in_uop.bits.op1_sel \n connect slots_16.io.in_uop.bits.imm_packed, issue_slots[16].in_uop.bits.imm_packed \n connect slots_16.io.in_uop.bits.pimm, issue_slots[16].in_uop.bits.pimm \n connect slots_16.io.in_uop.bits.imm_sel, issue_slots[16].in_uop.bits.imm_sel \n connect slots_16.io.in_uop.bits.imm_rename, issue_slots[16].in_uop.bits.imm_rename \n connect slots_16.io.in_uop.bits.taken, issue_slots[16].in_uop.bits.taken \n connect slots_16.io.in_uop.bits.pc_lob, issue_slots[16].in_uop.bits.pc_lob \n connect slots_16.io.in_uop.bits.edge_inst, issue_slots[16].in_uop.bits.edge_inst \n connect slots_16.io.in_uop.bits.ftq_idx, issue_slots[16].in_uop.bits.ftq_idx \n connect slots_16.io.in_uop.bits.is_mov, issue_slots[16].in_uop.bits.is_mov \n connect slots_16.io.in_uop.bits.is_rocc, issue_slots[16].in_uop.bits.is_rocc \n connect slots_16.io.in_uop.bits.is_sys_pc2epc, issue_slots[16].in_uop.bits.is_sys_pc2epc \n connect slots_16.io.in_uop.bits.is_eret, issue_slots[16].in_uop.bits.is_eret \n connect slots_16.io.in_uop.bits.is_amo, issue_slots[16].in_uop.bits.is_amo \n connect slots_16.io.in_uop.bits.is_sfence, issue_slots[16].in_uop.bits.is_sfence \n connect slots_16.io.in_uop.bits.is_fencei, issue_slots[16].in_uop.bits.is_fencei \n connect slots_16.io.in_uop.bits.is_fence, issue_slots[16].in_uop.bits.is_fence \n connect slots_16.io.in_uop.bits.is_sfb, issue_slots[16].in_uop.bits.is_sfb \n connect slots_16.io.in_uop.bits.br_type, issue_slots[16].in_uop.bits.br_type \n connect slots_16.io.in_uop.bits.br_tag, issue_slots[16].in_uop.bits.br_tag \n connect slots_16.io.in_uop.bits.br_mask, issue_slots[16].in_uop.bits.br_mask \n connect slots_16.io.in_uop.bits.dis_col_sel, issue_slots[16].in_uop.bits.dis_col_sel \n connect slots_16.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[16].in_uop.bits.iw_p3_bypass_hint \n connect slots_16.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[16].in_uop.bits.iw_p2_bypass_hint \n connect slots_16.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[16].in_uop.bits.iw_p1_bypass_hint \n connect slots_16.io.in_uop.bits.iw_p2_speculative_child, issue_slots[16].in_uop.bits.iw_p2_speculative_child \n connect slots_16.io.in_uop.bits.iw_p1_speculative_child, issue_slots[16].in_uop.bits.iw_p1_speculative_child \n connect slots_16.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[16].in_uop.bits.iw_issued_partial_dgen \n connect slots_16.io.in_uop.bits.iw_issued_partial_agen, issue_slots[16].in_uop.bits.iw_issued_partial_agen \n connect slots_16.io.in_uop.bits.iw_issued, issue_slots[16].in_uop.bits.iw_issued \n connect slots_16.io.in_uop.bits.fu_code[0], issue_slots[16].in_uop.bits.fu_code[0] \n connect slots_16.io.in_uop.bits.fu_code[1], issue_slots[16].in_uop.bits.fu_code[1] \n connect slots_16.io.in_uop.bits.fu_code[2], issue_slots[16].in_uop.bits.fu_code[2] \n connect slots_16.io.in_uop.bits.fu_code[3], issue_slots[16].in_uop.bits.fu_code[3] \n connect slots_16.io.in_uop.bits.fu_code[4], issue_slots[16].in_uop.bits.fu_code[4] \n connect slots_16.io.in_uop.bits.fu_code[5], issue_slots[16].in_uop.bits.fu_code[5] \n connect slots_16.io.in_uop.bits.fu_code[6], issue_slots[16].in_uop.bits.fu_code[6] \n connect slots_16.io.in_uop.bits.fu_code[7], issue_slots[16].in_uop.bits.fu_code[7] \n connect slots_16.io.in_uop.bits.fu_code[8], issue_slots[16].in_uop.bits.fu_code[8] \n connect slots_16.io.in_uop.bits.fu_code[9], issue_slots[16].in_uop.bits.fu_code[9] \n connect slots_16.io.in_uop.bits.iq_type[0], issue_slots[16].in_uop.bits.iq_type[0] \n connect slots_16.io.in_uop.bits.iq_type[1], issue_slots[16].in_uop.bits.iq_type[1] \n connect slots_16.io.in_uop.bits.iq_type[2], issue_slots[16].in_uop.bits.iq_type[2] \n connect slots_16.io.in_uop.bits.iq_type[3], issue_slots[16].in_uop.bits.iq_type[3] \n connect slots_16.io.in_uop.bits.debug_pc, issue_slots[16].in_uop.bits.debug_pc \n connect slots_16.io.in_uop.bits.is_rvc, issue_slots[16].in_uop.bits.is_rvc \n connect slots_16.io.in_uop.bits.debug_inst, issue_slots[16].in_uop.bits.debug_inst \n connect slots_16.io.in_uop.bits.inst, issue_slots[16].in_uop.bits.inst \n connect slots_16.io.in_uop.valid, issue_slots[16].in_uop.valid \n connect issue_slots[16].iss_uop.debug_tsrc, slots_16.io.iss_uop.debug_tsrc \n connect issue_slots[16].iss_uop.debug_fsrc, slots_16.io.iss_uop.debug_fsrc \n connect issue_slots[16].iss_uop.bp_xcpt_if, slots_16.io.iss_uop.bp_xcpt_if \n connect issue_slots[16].iss_uop.bp_debug_if, slots_16.io.iss_uop.bp_debug_if \n connect issue_slots[16].iss_uop.xcpt_ma_if, slots_16.io.iss_uop.xcpt_ma_if \n connect issue_slots[16].iss_uop.xcpt_ae_if, slots_16.io.iss_uop.xcpt_ae_if \n connect issue_slots[16].iss_uop.xcpt_pf_if, slots_16.io.iss_uop.xcpt_pf_if \n connect issue_slots[16].iss_uop.fp_typ, slots_16.io.iss_uop.fp_typ \n connect issue_slots[16].iss_uop.fp_rm, slots_16.io.iss_uop.fp_rm \n connect issue_slots[16].iss_uop.fp_val, slots_16.io.iss_uop.fp_val \n connect issue_slots[16].iss_uop.fcn_op, slots_16.io.iss_uop.fcn_op \n connect issue_slots[16].iss_uop.fcn_dw, slots_16.io.iss_uop.fcn_dw \n connect issue_slots[16].iss_uop.frs3_en, slots_16.io.iss_uop.frs3_en \n connect issue_slots[16].iss_uop.lrs2_rtype, slots_16.io.iss_uop.lrs2_rtype \n connect issue_slots[16].iss_uop.lrs1_rtype, slots_16.io.iss_uop.lrs1_rtype \n connect issue_slots[16].iss_uop.dst_rtype, slots_16.io.iss_uop.dst_rtype \n connect issue_slots[16].iss_uop.lrs3, slots_16.io.iss_uop.lrs3 \n connect issue_slots[16].iss_uop.lrs2, slots_16.io.iss_uop.lrs2 \n connect issue_slots[16].iss_uop.lrs1, slots_16.io.iss_uop.lrs1 \n connect issue_slots[16].iss_uop.ldst, slots_16.io.iss_uop.ldst \n connect issue_slots[16].iss_uop.ldst_is_rs1, slots_16.io.iss_uop.ldst_is_rs1 \n connect issue_slots[16].iss_uop.csr_cmd, slots_16.io.iss_uop.csr_cmd \n connect issue_slots[16].iss_uop.flush_on_commit, slots_16.io.iss_uop.flush_on_commit \n connect issue_slots[16].iss_uop.is_unique, slots_16.io.iss_uop.is_unique \n connect issue_slots[16].iss_uop.uses_stq, slots_16.io.iss_uop.uses_stq \n connect issue_slots[16].iss_uop.uses_ldq, slots_16.io.iss_uop.uses_ldq \n connect issue_slots[16].iss_uop.mem_signed, slots_16.io.iss_uop.mem_signed \n connect issue_slots[16].iss_uop.mem_size, slots_16.io.iss_uop.mem_size \n connect issue_slots[16].iss_uop.mem_cmd, slots_16.io.iss_uop.mem_cmd \n connect issue_slots[16].iss_uop.exc_cause, slots_16.io.iss_uop.exc_cause \n connect issue_slots[16].iss_uop.exception, slots_16.io.iss_uop.exception \n connect issue_slots[16].iss_uop.stale_pdst, slots_16.io.iss_uop.stale_pdst \n connect issue_slots[16].iss_uop.ppred_busy, slots_16.io.iss_uop.ppred_busy \n connect issue_slots[16].iss_uop.prs3_busy, slots_16.io.iss_uop.prs3_busy \n connect issue_slots[16].iss_uop.prs2_busy, slots_16.io.iss_uop.prs2_busy \n connect issue_slots[16].iss_uop.prs1_busy, slots_16.io.iss_uop.prs1_busy \n connect issue_slots[16].iss_uop.ppred, slots_16.io.iss_uop.ppred \n connect issue_slots[16].iss_uop.prs3, slots_16.io.iss_uop.prs3 \n connect issue_slots[16].iss_uop.prs2, slots_16.io.iss_uop.prs2 \n connect issue_slots[16].iss_uop.prs1, slots_16.io.iss_uop.prs1 \n connect issue_slots[16].iss_uop.pdst, slots_16.io.iss_uop.pdst \n connect issue_slots[16].iss_uop.rxq_idx, slots_16.io.iss_uop.rxq_idx \n connect issue_slots[16].iss_uop.stq_idx, slots_16.io.iss_uop.stq_idx \n connect issue_slots[16].iss_uop.ldq_idx, slots_16.io.iss_uop.ldq_idx \n connect issue_slots[16].iss_uop.rob_idx, slots_16.io.iss_uop.rob_idx \n connect issue_slots[16].iss_uop.fp_ctrl.vec, slots_16.io.iss_uop.fp_ctrl.vec \n connect issue_slots[16].iss_uop.fp_ctrl.wflags, slots_16.io.iss_uop.fp_ctrl.wflags \n connect issue_slots[16].iss_uop.fp_ctrl.sqrt, slots_16.io.iss_uop.fp_ctrl.sqrt \n connect issue_slots[16].iss_uop.fp_ctrl.div, slots_16.io.iss_uop.fp_ctrl.div \n connect issue_slots[16].iss_uop.fp_ctrl.fma, slots_16.io.iss_uop.fp_ctrl.fma \n connect issue_slots[16].iss_uop.fp_ctrl.fastpipe, slots_16.io.iss_uop.fp_ctrl.fastpipe \n connect issue_slots[16].iss_uop.fp_ctrl.toint, slots_16.io.iss_uop.fp_ctrl.toint \n connect issue_slots[16].iss_uop.fp_ctrl.fromint, slots_16.io.iss_uop.fp_ctrl.fromint \n connect issue_slots[16].iss_uop.fp_ctrl.typeTagOut, slots_16.io.iss_uop.fp_ctrl.typeTagOut \n connect issue_slots[16].iss_uop.fp_ctrl.typeTagIn, slots_16.io.iss_uop.fp_ctrl.typeTagIn \n connect issue_slots[16].iss_uop.fp_ctrl.swap23, slots_16.io.iss_uop.fp_ctrl.swap23 \n connect issue_slots[16].iss_uop.fp_ctrl.swap12, slots_16.io.iss_uop.fp_ctrl.swap12 \n connect issue_slots[16].iss_uop.fp_ctrl.ren3, slots_16.io.iss_uop.fp_ctrl.ren3 \n connect issue_slots[16].iss_uop.fp_ctrl.ren2, slots_16.io.iss_uop.fp_ctrl.ren2 \n connect issue_slots[16].iss_uop.fp_ctrl.ren1, slots_16.io.iss_uop.fp_ctrl.ren1 \n connect issue_slots[16].iss_uop.fp_ctrl.wen, slots_16.io.iss_uop.fp_ctrl.wen \n connect issue_slots[16].iss_uop.fp_ctrl.ldst, slots_16.io.iss_uop.fp_ctrl.ldst \n connect issue_slots[16].iss_uop.op2_sel, slots_16.io.iss_uop.op2_sel \n connect issue_slots[16].iss_uop.op1_sel, slots_16.io.iss_uop.op1_sel \n connect issue_slots[16].iss_uop.imm_packed, slots_16.io.iss_uop.imm_packed \n connect issue_slots[16].iss_uop.pimm, slots_16.io.iss_uop.pimm \n connect issue_slots[16].iss_uop.imm_sel, slots_16.io.iss_uop.imm_sel \n connect issue_slots[16].iss_uop.imm_rename, slots_16.io.iss_uop.imm_rename \n connect issue_slots[16].iss_uop.taken, slots_16.io.iss_uop.taken \n connect issue_slots[16].iss_uop.pc_lob, slots_16.io.iss_uop.pc_lob \n connect issue_slots[16].iss_uop.edge_inst, slots_16.io.iss_uop.edge_inst \n connect issue_slots[16].iss_uop.ftq_idx, slots_16.io.iss_uop.ftq_idx \n connect issue_slots[16].iss_uop.is_mov, slots_16.io.iss_uop.is_mov \n connect issue_slots[16].iss_uop.is_rocc, slots_16.io.iss_uop.is_rocc \n connect issue_slots[16].iss_uop.is_sys_pc2epc, slots_16.io.iss_uop.is_sys_pc2epc \n connect issue_slots[16].iss_uop.is_eret, slots_16.io.iss_uop.is_eret \n connect issue_slots[16].iss_uop.is_amo, slots_16.io.iss_uop.is_amo \n connect issue_slots[16].iss_uop.is_sfence, slots_16.io.iss_uop.is_sfence \n connect issue_slots[16].iss_uop.is_fencei, slots_16.io.iss_uop.is_fencei \n connect issue_slots[16].iss_uop.is_fence, slots_16.io.iss_uop.is_fence \n connect issue_slots[16].iss_uop.is_sfb, slots_16.io.iss_uop.is_sfb \n connect issue_slots[16].iss_uop.br_type, slots_16.io.iss_uop.br_type \n connect issue_slots[16].iss_uop.br_tag, slots_16.io.iss_uop.br_tag \n connect issue_slots[16].iss_uop.br_mask, slots_16.io.iss_uop.br_mask \n connect issue_slots[16].iss_uop.dis_col_sel, slots_16.io.iss_uop.dis_col_sel \n connect issue_slots[16].iss_uop.iw_p3_bypass_hint, slots_16.io.iss_uop.iw_p3_bypass_hint \n connect issue_slots[16].iss_uop.iw_p2_bypass_hint, slots_16.io.iss_uop.iw_p2_bypass_hint \n connect issue_slots[16].iss_uop.iw_p1_bypass_hint, slots_16.io.iss_uop.iw_p1_bypass_hint \n connect issue_slots[16].iss_uop.iw_p2_speculative_child, slots_16.io.iss_uop.iw_p2_speculative_child \n connect issue_slots[16].iss_uop.iw_p1_speculative_child, slots_16.io.iss_uop.iw_p1_speculative_child \n connect issue_slots[16].iss_uop.iw_issued_partial_dgen, slots_16.io.iss_uop.iw_issued_partial_dgen \n connect issue_slots[16].iss_uop.iw_issued_partial_agen, slots_16.io.iss_uop.iw_issued_partial_agen \n connect issue_slots[16].iss_uop.iw_issued, slots_16.io.iss_uop.iw_issued \n connect issue_slots[16].iss_uop.fu_code[0], slots_16.io.iss_uop.fu_code[0] \n connect issue_slots[16].iss_uop.fu_code[1], slots_16.io.iss_uop.fu_code[1] \n connect issue_slots[16].iss_uop.fu_code[2], slots_16.io.iss_uop.fu_code[2] \n connect issue_slots[16].iss_uop.fu_code[3], slots_16.io.iss_uop.fu_code[3] \n connect issue_slots[16].iss_uop.fu_code[4], slots_16.io.iss_uop.fu_code[4] \n connect issue_slots[16].iss_uop.fu_code[5], slots_16.io.iss_uop.fu_code[5] \n connect issue_slots[16].iss_uop.fu_code[6], slots_16.io.iss_uop.fu_code[6] \n connect issue_slots[16].iss_uop.fu_code[7], slots_16.io.iss_uop.fu_code[7] \n connect issue_slots[16].iss_uop.fu_code[8], slots_16.io.iss_uop.fu_code[8] \n connect issue_slots[16].iss_uop.fu_code[9], slots_16.io.iss_uop.fu_code[9] \n connect issue_slots[16].iss_uop.iq_type[0], slots_16.io.iss_uop.iq_type[0] \n connect issue_slots[16].iss_uop.iq_type[1], slots_16.io.iss_uop.iq_type[1] \n connect issue_slots[16].iss_uop.iq_type[2], slots_16.io.iss_uop.iq_type[2] \n connect issue_slots[16].iss_uop.iq_type[3], slots_16.io.iss_uop.iq_type[3] \n connect issue_slots[16].iss_uop.debug_pc, slots_16.io.iss_uop.debug_pc \n connect issue_slots[16].iss_uop.is_rvc, slots_16.io.iss_uop.is_rvc \n connect issue_slots[16].iss_uop.debug_inst, slots_16.io.iss_uop.debug_inst \n connect issue_slots[16].iss_uop.inst, slots_16.io.iss_uop.inst \n connect slots_16.io.grant, issue_slots[16].grant \n connect issue_slots[16].request, slots_16.io.request \n connect issue_slots[16].will_be_valid, slots_16.io.will_be_valid \n connect issue_slots[16].valid, slots_16.io.valid \n connect slots_17.io.child_rebusys, issue_slots[17].child_rebusys \n connect slots_17.io.pred_wakeup_port.bits, issue_slots[17].pred_wakeup_port.bits \n connect slots_17.io.pred_wakeup_port.valid, issue_slots[17].pred_wakeup_port.valid \n connect slots_17.io.wakeup_ports[0].bits.rebusy, issue_slots[17].wakeup_ports[0].bits.rebusy \n connect slots_17.io.wakeup_ports[0].bits.speculative_mask, issue_slots[17].wakeup_ports[0].bits.speculative_mask \n connect slots_17.io.wakeup_ports[0].bits.bypassable, issue_slots[17].wakeup_ports[0].bits.bypassable \n connect slots_17.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[17].wakeup_ports[0].bits.uop.debug_tsrc \n connect slots_17.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[17].wakeup_ports[0].bits.uop.debug_fsrc \n connect slots_17.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[17].wakeup_ports[0].bits.uop.bp_xcpt_if \n connect slots_17.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[17].wakeup_ports[0].bits.uop.bp_debug_if \n connect slots_17.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[17].wakeup_ports[0].bits.uop.xcpt_ma_if \n connect slots_17.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[17].wakeup_ports[0].bits.uop.xcpt_ae_if \n connect slots_17.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[17].wakeup_ports[0].bits.uop.xcpt_pf_if \n connect slots_17.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[17].wakeup_ports[0].bits.uop.fp_typ \n connect slots_17.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[17].wakeup_ports[0].bits.uop.fp_rm \n connect slots_17.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[17].wakeup_ports[0].bits.uop.fp_val \n connect slots_17.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[17].wakeup_ports[0].bits.uop.fcn_op \n connect slots_17.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[17].wakeup_ports[0].bits.uop.fcn_dw \n connect slots_17.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[17].wakeup_ports[0].bits.uop.frs3_en \n connect slots_17.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[17].wakeup_ports[0].bits.uop.lrs2_rtype \n connect slots_17.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[17].wakeup_ports[0].bits.uop.lrs1_rtype \n connect slots_17.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[17].wakeup_ports[0].bits.uop.dst_rtype \n connect slots_17.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[17].wakeup_ports[0].bits.uop.lrs3 \n connect slots_17.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[17].wakeup_ports[0].bits.uop.lrs2 \n connect slots_17.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[17].wakeup_ports[0].bits.uop.lrs1 \n connect slots_17.io.wakeup_ports[0].bits.uop.ldst, issue_slots[17].wakeup_ports[0].bits.uop.ldst \n connect slots_17.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[17].wakeup_ports[0].bits.uop.ldst_is_rs1 \n connect slots_17.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[17].wakeup_ports[0].bits.uop.csr_cmd \n connect slots_17.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[17].wakeup_ports[0].bits.uop.flush_on_commit \n connect slots_17.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[17].wakeup_ports[0].bits.uop.is_unique \n connect slots_17.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[17].wakeup_ports[0].bits.uop.uses_stq \n connect slots_17.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[17].wakeup_ports[0].bits.uop.uses_ldq \n connect slots_17.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[17].wakeup_ports[0].bits.uop.mem_signed \n connect slots_17.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[17].wakeup_ports[0].bits.uop.mem_size \n connect slots_17.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[17].wakeup_ports[0].bits.uop.mem_cmd \n connect slots_17.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[17].wakeup_ports[0].bits.uop.exc_cause \n connect slots_17.io.wakeup_ports[0].bits.uop.exception, issue_slots[17].wakeup_ports[0].bits.uop.exception \n connect slots_17.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[17].wakeup_ports[0].bits.uop.stale_pdst \n connect slots_17.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[17].wakeup_ports[0].bits.uop.ppred_busy \n connect slots_17.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[17].wakeup_ports[0].bits.uop.prs3_busy \n connect slots_17.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[17].wakeup_ports[0].bits.uop.prs2_busy \n connect slots_17.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[17].wakeup_ports[0].bits.uop.prs1_busy \n connect slots_17.io.wakeup_ports[0].bits.uop.ppred, issue_slots[17].wakeup_ports[0].bits.uop.ppred \n connect slots_17.io.wakeup_ports[0].bits.uop.prs3, issue_slots[17].wakeup_ports[0].bits.uop.prs3 \n connect slots_17.io.wakeup_ports[0].bits.uop.prs2, issue_slots[17].wakeup_ports[0].bits.uop.prs2 \n connect slots_17.io.wakeup_ports[0].bits.uop.prs1, issue_slots[17].wakeup_ports[0].bits.uop.prs1 \n connect slots_17.io.wakeup_ports[0].bits.uop.pdst, issue_slots[17].wakeup_ports[0].bits.uop.pdst \n connect slots_17.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[17].wakeup_ports[0].bits.uop.rxq_idx \n connect slots_17.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[17].wakeup_ports[0].bits.uop.stq_idx \n connect slots_17.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[17].wakeup_ports[0].bits.uop.ldq_idx \n connect slots_17.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[17].wakeup_ports[0].bits.uop.rob_idx \n connect slots_17.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.vec \n connect slots_17.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.wflags \n connect slots_17.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.sqrt \n connect slots_17.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.div \n connect slots_17.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.fma \n connect slots_17.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe \n connect slots_17.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.toint \n connect slots_17.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.fromint \n connect slots_17.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut \n connect slots_17.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn \n connect slots_17.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.swap23 \n connect slots_17.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.swap12 \n connect slots_17.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.ren3 \n connect slots_17.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.ren2 \n connect slots_17.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.ren1 \n connect slots_17.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.wen \n connect slots_17.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.ldst \n connect slots_17.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[17].wakeup_ports[0].bits.uop.op2_sel \n connect slots_17.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[17].wakeup_ports[0].bits.uop.op1_sel \n connect slots_17.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[17].wakeup_ports[0].bits.uop.imm_packed \n connect slots_17.io.wakeup_ports[0].bits.uop.pimm, issue_slots[17].wakeup_ports[0].bits.uop.pimm \n connect slots_17.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[17].wakeup_ports[0].bits.uop.imm_sel \n connect slots_17.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[17].wakeup_ports[0].bits.uop.imm_rename \n connect slots_17.io.wakeup_ports[0].bits.uop.taken, issue_slots[17].wakeup_ports[0].bits.uop.taken \n connect slots_17.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[17].wakeup_ports[0].bits.uop.pc_lob \n connect slots_17.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[17].wakeup_ports[0].bits.uop.edge_inst \n connect slots_17.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[17].wakeup_ports[0].bits.uop.ftq_idx \n connect slots_17.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[17].wakeup_ports[0].bits.uop.is_mov \n connect slots_17.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[17].wakeup_ports[0].bits.uop.is_rocc \n connect slots_17.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[17].wakeup_ports[0].bits.uop.is_sys_pc2epc \n connect slots_17.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[17].wakeup_ports[0].bits.uop.is_eret \n connect slots_17.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[17].wakeup_ports[0].bits.uop.is_amo \n connect slots_17.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[17].wakeup_ports[0].bits.uop.is_sfence \n connect slots_17.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[17].wakeup_ports[0].bits.uop.is_fencei \n connect slots_17.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[17].wakeup_ports[0].bits.uop.is_fence \n connect slots_17.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[17].wakeup_ports[0].bits.uop.is_sfb \n connect slots_17.io.wakeup_ports[0].bits.uop.br_type, issue_slots[17].wakeup_ports[0].bits.uop.br_type \n connect slots_17.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[17].wakeup_ports[0].bits.uop.br_tag \n connect slots_17.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[17].wakeup_ports[0].bits.uop.br_mask \n connect slots_17.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[17].wakeup_ports[0].bits.uop.dis_col_sel \n connect slots_17.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[17].wakeup_ports[0].bits.uop.iw_p3_bypass_hint \n connect slots_17.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[17].wakeup_ports[0].bits.uop.iw_p2_bypass_hint \n connect slots_17.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[17].wakeup_ports[0].bits.uop.iw_p1_bypass_hint \n connect slots_17.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[17].wakeup_ports[0].bits.uop.iw_p2_speculative_child \n connect slots_17.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[17].wakeup_ports[0].bits.uop.iw_p1_speculative_child \n connect slots_17.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[17].wakeup_ports[0].bits.uop.iw_issued_partial_dgen \n connect slots_17.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[17].wakeup_ports[0].bits.uop.iw_issued_partial_agen \n connect slots_17.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[17].wakeup_ports[0].bits.uop.iw_issued \n connect slots_17.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[17].wakeup_ports[0].bits.uop.fu_code[0] \n connect slots_17.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[17].wakeup_ports[0].bits.uop.fu_code[1] \n connect slots_17.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[17].wakeup_ports[0].bits.uop.fu_code[2] \n connect slots_17.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[17].wakeup_ports[0].bits.uop.fu_code[3] \n connect slots_17.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[17].wakeup_ports[0].bits.uop.fu_code[4] \n connect slots_17.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[17].wakeup_ports[0].bits.uop.fu_code[5] \n connect slots_17.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[17].wakeup_ports[0].bits.uop.fu_code[6] \n connect slots_17.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[17].wakeup_ports[0].bits.uop.fu_code[7] \n connect slots_17.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[17].wakeup_ports[0].bits.uop.fu_code[8] \n connect slots_17.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[17].wakeup_ports[0].bits.uop.fu_code[9] \n connect slots_17.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[17].wakeup_ports[0].bits.uop.iq_type[0] \n connect slots_17.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[17].wakeup_ports[0].bits.uop.iq_type[1] \n connect slots_17.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[17].wakeup_ports[0].bits.uop.iq_type[2] \n connect slots_17.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[17].wakeup_ports[0].bits.uop.iq_type[3] \n connect slots_17.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[17].wakeup_ports[0].bits.uop.debug_pc \n connect slots_17.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[17].wakeup_ports[0].bits.uop.is_rvc \n connect slots_17.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[17].wakeup_ports[0].bits.uop.debug_inst \n connect slots_17.io.wakeup_ports[0].bits.uop.inst, issue_slots[17].wakeup_ports[0].bits.uop.inst \n connect slots_17.io.wakeup_ports[0].valid, issue_slots[17].wakeup_ports[0].valid \n connect slots_17.io.wakeup_ports[1].bits.rebusy, issue_slots[17].wakeup_ports[1].bits.rebusy \n connect slots_17.io.wakeup_ports[1].bits.speculative_mask, issue_slots[17].wakeup_ports[1].bits.speculative_mask \n connect slots_17.io.wakeup_ports[1].bits.bypassable, issue_slots[17].wakeup_ports[1].bits.bypassable \n connect slots_17.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[17].wakeup_ports[1].bits.uop.debug_tsrc \n connect slots_17.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[17].wakeup_ports[1].bits.uop.debug_fsrc \n connect slots_17.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[17].wakeup_ports[1].bits.uop.bp_xcpt_if \n connect slots_17.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[17].wakeup_ports[1].bits.uop.bp_debug_if \n connect slots_17.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[17].wakeup_ports[1].bits.uop.xcpt_ma_if \n connect slots_17.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[17].wakeup_ports[1].bits.uop.xcpt_ae_if \n connect slots_17.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[17].wakeup_ports[1].bits.uop.xcpt_pf_if \n connect slots_17.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[17].wakeup_ports[1].bits.uop.fp_typ \n connect slots_17.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[17].wakeup_ports[1].bits.uop.fp_rm \n connect slots_17.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[17].wakeup_ports[1].bits.uop.fp_val \n connect slots_17.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[17].wakeup_ports[1].bits.uop.fcn_op \n connect slots_17.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[17].wakeup_ports[1].bits.uop.fcn_dw \n connect slots_17.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[17].wakeup_ports[1].bits.uop.frs3_en \n connect slots_17.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[17].wakeup_ports[1].bits.uop.lrs2_rtype \n connect slots_17.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[17].wakeup_ports[1].bits.uop.lrs1_rtype \n connect slots_17.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[17].wakeup_ports[1].bits.uop.dst_rtype \n connect slots_17.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[17].wakeup_ports[1].bits.uop.lrs3 \n connect slots_17.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[17].wakeup_ports[1].bits.uop.lrs2 \n connect slots_17.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[17].wakeup_ports[1].bits.uop.lrs1 \n connect slots_17.io.wakeup_ports[1].bits.uop.ldst, issue_slots[17].wakeup_ports[1].bits.uop.ldst \n connect slots_17.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[17].wakeup_ports[1].bits.uop.ldst_is_rs1 \n connect slots_17.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[17].wakeup_ports[1].bits.uop.csr_cmd \n connect slots_17.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[17].wakeup_ports[1].bits.uop.flush_on_commit \n connect slots_17.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[17].wakeup_ports[1].bits.uop.is_unique \n connect slots_17.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[17].wakeup_ports[1].bits.uop.uses_stq \n connect slots_17.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[17].wakeup_ports[1].bits.uop.uses_ldq \n connect slots_17.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[17].wakeup_ports[1].bits.uop.mem_signed \n connect slots_17.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[17].wakeup_ports[1].bits.uop.mem_size \n connect slots_17.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[17].wakeup_ports[1].bits.uop.mem_cmd \n connect slots_17.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[17].wakeup_ports[1].bits.uop.exc_cause \n connect slots_17.io.wakeup_ports[1].bits.uop.exception, issue_slots[17].wakeup_ports[1].bits.uop.exception \n connect slots_17.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[17].wakeup_ports[1].bits.uop.stale_pdst \n connect slots_17.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[17].wakeup_ports[1].bits.uop.ppred_busy \n connect slots_17.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[17].wakeup_ports[1].bits.uop.prs3_busy \n connect slots_17.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[17].wakeup_ports[1].bits.uop.prs2_busy \n connect slots_17.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[17].wakeup_ports[1].bits.uop.prs1_busy \n connect slots_17.io.wakeup_ports[1].bits.uop.ppred, issue_slots[17].wakeup_ports[1].bits.uop.ppred \n connect slots_17.io.wakeup_ports[1].bits.uop.prs3, issue_slots[17].wakeup_ports[1].bits.uop.prs3 \n connect slots_17.io.wakeup_ports[1].bits.uop.prs2, issue_slots[17].wakeup_ports[1].bits.uop.prs2 \n connect slots_17.io.wakeup_ports[1].bits.uop.prs1, issue_slots[17].wakeup_ports[1].bits.uop.prs1 \n connect slots_17.io.wakeup_ports[1].bits.uop.pdst, issue_slots[17].wakeup_ports[1].bits.uop.pdst \n connect slots_17.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[17].wakeup_ports[1].bits.uop.rxq_idx \n connect slots_17.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[17].wakeup_ports[1].bits.uop.stq_idx \n connect slots_17.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[17].wakeup_ports[1].bits.uop.ldq_idx \n connect slots_17.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[17].wakeup_ports[1].bits.uop.rob_idx \n connect slots_17.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.vec \n connect slots_17.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.wflags \n connect slots_17.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.sqrt \n connect slots_17.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.div \n connect slots_17.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.fma \n connect slots_17.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe \n connect slots_17.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.toint \n connect slots_17.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.fromint \n connect slots_17.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut \n connect slots_17.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn \n connect slots_17.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.swap23 \n connect slots_17.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.swap12 \n connect slots_17.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.ren3 \n connect slots_17.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.ren2 \n connect slots_17.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.ren1 \n connect slots_17.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.wen \n connect slots_17.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.ldst \n connect slots_17.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[17].wakeup_ports[1].bits.uop.op2_sel \n connect slots_17.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[17].wakeup_ports[1].bits.uop.op1_sel \n connect slots_17.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[17].wakeup_ports[1].bits.uop.imm_packed \n connect slots_17.io.wakeup_ports[1].bits.uop.pimm, issue_slots[17].wakeup_ports[1].bits.uop.pimm \n connect slots_17.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[17].wakeup_ports[1].bits.uop.imm_sel \n connect slots_17.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[17].wakeup_ports[1].bits.uop.imm_rename \n connect slots_17.io.wakeup_ports[1].bits.uop.taken, issue_slots[17].wakeup_ports[1].bits.uop.taken \n connect slots_17.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[17].wakeup_ports[1].bits.uop.pc_lob \n connect slots_17.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[17].wakeup_ports[1].bits.uop.edge_inst \n connect slots_17.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[17].wakeup_ports[1].bits.uop.ftq_idx \n connect slots_17.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[17].wakeup_ports[1].bits.uop.is_mov \n connect slots_17.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[17].wakeup_ports[1].bits.uop.is_rocc \n connect slots_17.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[17].wakeup_ports[1].bits.uop.is_sys_pc2epc \n connect slots_17.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[17].wakeup_ports[1].bits.uop.is_eret \n connect slots_17.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[17].wakeup_ports[1].bits.uop.is_amo \n connect slots_17.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[17].wakeup_ports[1].bits.uop.is_sfence \n connect slots_17.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[17].wakeup_ports[1].bits.uop.is_fencei \n connect slots_17.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[17].wakeup_ports[1].bits.uop.is_fence \n connect slots_17.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[17].wakeup_ports[1].bits.uop.is_sfb \n connect slots_17.io.wakeup_ports[1].bits.uop.br_type, issue_slots[17].wakeup_ports[1].bits.uop.br_type \n connect slots_17.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[17].wakeup_ports[1].bits.uop.br_tag \n connect slots_17.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[17].wakeup_ports[1].bits.uop.br_mask \n connect slots_17.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[17].wakeup_ports[1].bits.uop.dis_col_sel \n connect slots_17.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[17].wakeup_ports[1].bits.uop.iw_p3_bypass_hint \n connect slots_17.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[17].wakeup_ports[1].bits.uop.iw_p2_bypass_hint \n connect slots_17.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[17].wakeup_ports[1].bits.uop.iw_p1_bypass_hint \n connect slots_17.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[17].wakeup_ports[1].bits.uop.iw_p2_speculative_child \n connect slots_17.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[17].wakeup_ports[1].bits.uop.iw_p1_speculative_child \n connect slots_17.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[17].wakeup_ports[1].bits.uop.iw_issued_partial_dgen \n connect slots_17.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[17].wakeup_ports[1].bits.uop.iw_issued_partial_agen \n connect slots_17.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[17].wakeup_ports[1].bits.uop.iw_issued \n connect slots_17.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[17].wakeup_ports[1].bits.uop.fu_code[0] \n connect slots_17.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[17].wakeup_ports[1].bits.uop.fu_code[1] \n connect slots_17.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[17].wakeup_ports[1].bits.uop.fu_code[2] \n connect slots_17.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[17].wakeup_ports[1].bits.uop.fu_code[3] \n connect slots_17.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[17].wakeup_ports[1].bits.uop.fu_code[4] \n connect slots_17.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[17].wakeup_ports[1].bits.uop.fu_code[5] \n connect slots_17.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[17].wakeup_ports[1].bits.uop.fu_code[6] \n connect slots_17.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[17].wakeup_ports[1].bits.uop.fu_code[7] \n connect slots_17.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[17].wakeup_ports[1].bits.uop.fu_code[8] \n connect slots_17.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[17].wakeup_ports[1].bits.uop.fu_code[9] \n connect slots_17.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[17].wakeup_ports[1].bits.uop.iq_type[0] \n connect slots_17.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[17].wakeup_ports[1].bits.uop.iq_type[1] \n connect slots_17.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[17].wakeup_ports[1].bits.uop.iq_type[2] \n connect slots_17.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[17].wakeup_ports[1].bits.uop.iq_type[3] \n connect slots_17.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[17].wakeup_ports[1].bits.uop.debug_pc \n connect slots_17.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[17].wakeup_ports[1].bits.uop.is_rvc \n connect slots_17.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[17].wakeup_ports[1].bits.uop.debug_inst \n connect slots_17.io.wakeup_ports[1].bits.uop.inst, issue_slots[17].wakeup_ports[1].bits.uop.inst \n connect slots_17.io.wakeup_ports[1].valid, issue_slots[17].wakeup_ports[1].valid \n connect slots_17.io.wakeup_ports[2].bits.rebusy, issue_slots[17].wakeup_ports[2].bits.rebusy \n connect slots_17.io.wakeup_ports[2].bits.speculative_mask, issue_slots[17].wakeup_ports[2].bits.speculative_mask \n connect slots_17.io.wakeup_ports[2].bits.bypassable, issue_slots[17].wakeup_ports[2].bits.bypassable \n connect slots_17.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[17].wakeup_ports[2].bits.uop.debug_tsrc \n connect slots_17.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[17].wakeup_ports[2].bits.uop.debug_fsrc \n connect slots_17.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[17].wakeup_ports[2].bits.uop.bp_xcpt_if \n connect slots_17.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[17].wakeup_ports[2].bits.uop.bp_debug_if \n connect slots_17.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[17].wakeup_ports[2].bits.uop.xcpt_ma_if \n connect slots_17.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[17].wakeup_ports[2].bits.uop.xcpt_ae_if \n connect slots_17.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[17].wakeup_ports[2].bits.uop.xcpt_pf_if \n connect slots_17.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[17].wakeup_ports[2].bits.uop.fp_typ \n connect slots_17.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[17].wakeup_ports[2].bits.uop.fp_rm \n connect slots_17.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[17].wakeup_ports[2].bits.uop.fp_val \n connect slots_17.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[17].wakeup_ports[2].bits.uop.fcn_op \n connect slots_17.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[17].wakeup_ports[2].bits.uop.fcn_dw \n connect slots_17.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[17].wakeup_ports[2].bits.uop.frs3_en \n connect slots_17.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[17].wakeup_ports[2].bits.uop.lrs2_rtype \n connect slots_17.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[17].wakeup_ports[2].bits.uop.lrs1_rtype \n connect slots_17.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[17].wakeup_ports[2].bits.uop.dst_rtype \n connect slots_17.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[17].wakeup_ports[2].bits.uop.lrs3 \n connect slots_17.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[17].wakeup_ports[2].bits.uop.lrs2 \n connect slots_17.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[17].wakeup_ports[2].bits.uop.lrs1 \n connect slots_17.io.wakeup_ports[2].bits.uop.ldst, issue_slots[17].wakeup_ports[2].bits.uop.ldst \n connect slots_17.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[17].wakeup_ports[2].bits.uop.ldst_is_rs1 \n connect slots_17.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[17].wakeup_ports[2].bits.uop.csr_cmd \n connect slots_17.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[17].wakeup_ports[2].bits.uop.flush_on_commit \n connect slots_17.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[17].wakeup_ports[2].bits.uop.is_unique \n connect slots_17.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[17].wakeup_ports[2].bits.uop.uses_stq \n connect slots_17.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[17].wakeup_ports[2].bits.uop.uses_ldq \n connect slots_17.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[17].wakeup_ports[2].bits.uop.mem_signed \n connect slots_17.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[17].wakeup_ports[2].bits.uop.mem_size \n connect slots_17.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[17].wakeup_ports[2].bits.uop.mem_cmd \n connect slots_17.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[17].wakeup_ports[2].bits.uop.exc_cause \n connect slots_17.io.wakeup_ports[2].bits.uop.exception, issue_slots[17].wakeup_ports[2].bits.uop.exception \n connect slots_17.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[17].wakeup_ports[2].bits.uop.stale_pdst \n connect slots_17.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[17].wakeup_ports[2].bits.uop.ppred_busy \n connect slots_17.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[17].wakeup_ports[2].bits.uop.prs3_busy \n connect slots_17.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[17].wakeup_ports[2].bits.uop.prs2_busy \n connect slots_17.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[17].wakeup_ports[2].bits.uop.prs1_busy \n connect slots_17.io.wakeup_ports[2].bits.uop.ppred, issue_slots[17].wakeup_ports[2].bits.uop.ppred \n connect slots_17.io.wakeup_ports[2].bits.uop.prs3, issue_slots[17].wakeup_ports[2].bits.uop.prs3 \n connect slots_17.io.wakeup_ports[2].bits.uop.prs2, issue_slots[17].wakeup_ports[2].bits.uop.prs2 \n connect slots_17.io.wakeup_ports[2].bits.uop.prs1, issue_slots[17].wakeup_ports[2].bits.uop.prs1 \n connect slots_17.io.wakeup_ports[2].bits.uop.pdst, issue_slots[17].wakeup_ports[2].bits.uop.pdst \n connect slots_17.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[17].wakeup_ports[2].bits.uop.rxq_idx \n connect slots_17.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[17].wakeup_ports[2].bits.uop.stq_idx \n connect slots_17.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[17].wakeup_ports[2].bits.uop.ldq_idx \n connect slots_17.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[17].wakeup_ports[2].bits.uop.rob_idx \n connect slots_17.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.vec \n connect slots_17.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.wflags \n connect slots_17.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.sqrt \n connect slots_17.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.div \n connect slots_17.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.fma \n connect slots_17.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe \n connect slots_17.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.toint \n connect slots_17.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.fromint \n connect slots_17.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut \n connect slots_17.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn \n connect slots_17.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.swap23 \n connect slots_17.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.swap12 \n connect slots_17.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.ren3 \n connect slots_17.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.ren2 \n connect slots_17.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.ren1 \n connect slots_17.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.wen \n connect slots_17.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.ldst \n connect slots_17.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[17].wakeup_ports[2].bits.uop.op2_sel \n connect slots_17.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[17].wakeup_ports[2].bits.uop.op1_sel \n connect slots_17.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[17].wakeup_ports[2].bits.uop.imm_packed \n connect slots_17.io.wakeup_ports[2].bits.uop.pimm, issue_slots[17].wakeup_ports[2].bits.uop.pimm \n connect slots_17.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[17].wakeup_ports[2].bits.uop.imm_sel \n connect slots_17.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[17].wakeup_ports[2].bits.uop.imm_rename \n connect slots_17.io.wakeup_ports[2].bits.uop.taken, issue_slots[17].wakeup_ports[2].bits.uop.taken \n connect slots_17.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[17].wakeup_ports[2].bits.uop.pc_lob \n connect slots_17.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[17].wakeup_ports[2].bits.uop.edge_inst \n connect slots_17.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[17].wakeup_ports[2].bits.uop.ftq_idx \n connect slots_17.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[17].wakeup_ports[2].bits.uop.is_mov \n connect slots_17.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[17].wakeup_ports[2].bits.uop.is_rocc \n connect slots_17.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[17].wakeup_ports[2].bits.uop.is_sys_pc2epc \n connect slots_17.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[17].wakeup_ports[2].bits.uop.is_eret \n connect slots_17.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[17].wakeup_ports[2].bits.uop.is_amo \n connect slots_17.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[17].wakeup_ports[2].bits.uop.is_sfence \n connect slots_17.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[17].wakeup_ports[2].bits.uop.is_fencei \n connect slots_17.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[17].wakeup_ports[2].bits.uop.is_fence \n connect slots_17.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[17].wakeup_ports[2].bits.uop.is_sfb \n connect slots_17.io.wakeup_ports[2].bits.uop.br_type, issue_slots[17].wakeup_ports[2].bits.uop.br_type \n connect slots_17.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[17].wakeup_ports[2].bits.uop.br_tag \n connect slots_17.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[17].wakeup_ports[2].bits.uop.br_mask \n connect slots_17.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[17].wakeup_ports[2].bits.uop.dis_col_sel \n connect slots_17.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[17].wakeup_ports[2].bits.uop.iw_p3_bypass_hint \n connect slots_17.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[17].wakeup_ports[2].bits.uop.iw_p2_bypass_hint \n connect slots_17.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[17].wakeup_ports[2].bits.uop.iw_p1_bypass_hint \n connect slots_17.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[17].wakeup_ports[2].bits.uop.iw_p2_speculative_child \n connect slots_17.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[17].wakeup_ports[2].bits.uop.iw_p1_speculative_child \n connect slots_17.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[17].wakeup_ports[2].bits.uop.iw_issued_partial_dgen \n connect slots_17.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[17].wakeup_ports[2].bits.uop.iw_issued_partial_agen \n connect slots_17.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[17].wakeup_ports[2].bits.uop.iw_issued \n connect slots_17.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[17].wakeup_ports[2].bits.uop.fu_code[0] \n connect slots_17.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[17].wakeup_ports[2].bits.uop.fu_code[1] \n connect slots_17.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[17].wakeup_ports[2].bits.uop.fu_code[2] \n connect slots_17.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[17].wakeup_ports[2].bits.uop.fu_code[3] \n connect slots_17.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[17].wakeup_ports[2].bits.uop.fu_code[4] \n connect slots_17.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[17].wakeup_ports[2].bits.uop.fu_code[5] \n connect slots_17.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[17].wakeup_ports[2].bits.uop.fu_code[6] \n connect slots_17.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[17].wakeup_ports[2].bits.uop.fu_code[7] \n connect slots_17.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[17].wakeup_ports[2].bits.uop.fu_code[8] \n connect slots_17.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[17].wakeup_ports[2].bits.uop.fu_code[9] \n connect slots_17.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[17].wakeup_ports[2].bits.uop.iq_type[0] \n connect slots_17.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[17].wakeup_ports[2].bits.uop.iq_type[1] \n connect slots_17.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[17].wakeup_ports[2].bits.uop.iq_type[2] \n connect slots_17.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[17].wakeup_ports[2].bits.uop.iq_type[3] \n connect slots_17.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[17].wakeup_ports[2].bits.uop.debug_pc \n connect slots_17.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[17].wakeup_ports[2].bits.uop.is_rvc \n connect slots_17.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[17].wakeup_ports[2].bits.uop.debug_inst \n connect slots_17.io.wakeup_ports[2].bits.uop.inst, issue_slots[17].wakeup_ports[2].bits.uop.inst \n connect slots_17.io.wakeup_ports[2].valid, issue_slots[17].wakeup_ports[2].valid \n connect slots_17.io.wakeup_ports[3].bits.rebusy, issue_slots[17].wakeup_ports[3].bits.rebusy \n connect slots_17.io.wakeup_ports[3].bits.speculative_mask, issue_slots[17].wakeup_ports[3].bits.speculative_mask \n connect slots_17.io.wakeup_ports[3].bits.bypassable, issue_slots[17].wakeup_ports[3].bits.bypassable \n connect slots_17.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[17].wakeup_ports[3].bits.uop.debug_tsrc \n connect slots_17.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[17].wakeup_ports[3].bits.uop.debug_fsrc \n connect slots_17.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[17].wakeup_ports[3].bits.uop.bp_xcpt_if \n connect slots_17.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[17].wakeup_ports[3].bits.uop.bp_debug_if \n connect slots_17.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[17].wakeup_ports[3].bits.uop.xcpt_ma_if \n connect slots_17.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[17].wakeup_ports[3].bits.uop.xcpt_ae_if \n connect slots_17.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[17].wakeup_ports[3].bits.uop.xcpt_pf_if \n connect slots_17.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[17].wakeup_ports[3].bits.uop.fp_typ \n connect slots_17.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[17].wakeup_ports[3].bits.uop.fp_rm \n connect slots_17.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[17].wakeup_ports[3].bits.uop.fp_val \n connect slots_17.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[17].wakeup_ports[3].bits.uop.fcn_op \n connect slots_17.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[17].wakeup_ports[3].bits.uop.fcn_dw \n connect slots_17.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[17].wakeup_ports[3].bits.uop.frs3_en \n connect slots_17.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[17].wakeup_ports[3].bits.uop.lrs2_rtype \n connect slots_17.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[17].wakeup_ports[3].bits.uop.lrs1_rtype \n connect slots_17.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[17].wakeup_ports[3].bits.uop.dst_rtype \n connect slots_17.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[17].wakeup_ports[3].bits.uop.lrs3 \n connect slots_17.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[17].wakeup_ports[3].bits.uop.lrs2 \n connect slots_17.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[17].wakeup_ports[3].bits.uop.lrs1 \n connect slots_17.io.wakeup_ports[3].bits.uop.ldst, issue_slots[17].wakeup_ports[3].bits.uop.ldst \n connect slots_17.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[17].wakeup_ports[3].bits.uop.ldst_is_rs1 \n connect slots_17.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[17].wakeup_ports[3].bits.uop.csr_cmd \n connect slots_17.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[17].wakeup_ports[3].bits.uop.flush_on_commit \n connect slots_17.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[17].wakeup_ports[3].bits.uop.is_unique \n connect slots_17.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[17].wakeup_ports[3].bits.uop.uses_stq \n connect slots_17.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[17].wakeup_ports[3].bits.uop.uses_ldq \n connect slots_17.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[17].wakeup_ports[3].bits.uop.mem_signed \n connect slots_17.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[17].wakeup_ports[3].bits.uop.mem_size \n connect slots_17.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[17].wakeup_ports[3].bits.uop.mem_cmd \n connect slots_17.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[17].wakeup_ports[3].bits.uop.exc_cause \n connect slots_17.io.wakeup_ports[3].bits.uop.exception, issue_slots[17].wakeup_ports[3].bits.uop.exception \n connect slots_17.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[17].wakeup_ports[3].bits.uop.stale_pdst \n connect slots_17.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[17].wakeup_ports[3].bits.uop.ppred_busy \n connect slots_17.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[17].wakeup_ports[3].bits.uop.prs3_busy \n connect slots_17.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[17].wakeup_ports[3].bits.uop.prs2_busy \n connect slots_17.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[17].wakeup_ports[3].bits.uop.prs1_busy \n connect slots_17.io.wakeup_ports[3].bits.uop.ppred, issue_slots[17].wakeup_ports[3].bits.uop.ppred \n connect slots_17.io.wakeup_ports[3].bits.uop.prs3, issue_slots[17].wakeup_ports[3].bits.uop.prs3 \n connect slots_17.io.wakeup_ports[3].bits.uop.prs2, issue_slots[17].wakeup_ports[3].bits.uop.prs2 \n connect slots_17.io.wakeup_ports[3].bits.uop.prs1, issue_slots[17].wakeup_ports[3].bits.uop.prs1 \n connect slots_17.io.wakeup_ports[3].bits.uop.pdst, issue_slots[17].wakeup_ports[3].bits.uop.pdst \n connect slots_17.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[17].wakeup_ports[3].bits.uop.rxq_idx \n connect slots_17.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[17].wakeup_ports[3].bits.uop.stq_idx \n connect slots_17.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[17].wakeup_ports[3].bits.uop.ldq_idx \n connect slots_17.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[17].wakeup_ports[3].bits.uop.rob_idx \n connect slots_17.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.vec \n connect slots_17.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.wflags \n connect slots_17.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.sqrt \n connect slots_17.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.div \n connect slots_17.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.fma \n connect slots_17.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe \n connect slots_17.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.toint \n connect slots_17.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.fromint \n connect slots_17.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut \n connect slots_17.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn \n connect slots_17.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.swap23 \n connect slots_17.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.swap12 \n connect slots_17.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.ren3 \n connect slots_17.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.ren2 \n connect slots_17.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.ren1 \n connect slots_17.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.wen \n connect slots_17.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.ldst \n connect slots_17.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[17].wakeup_ports[3].bits.uop.op2_sel \n connect slots_17.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[17].wakeup_ports[3].bits.uop.op1_sel \n connect slots_17.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[17].wakeup_ports[3].bits.uop.imm_packed \n connect slots_17.io.wakeup_ports[3].bits.uop.pimm, issue_slots[17].wakeup_ports[3].bits.uop.pimm \n connect slots_17.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[17].wakeup_ports[3].bits.uop.imm_sel \n connect slots_17.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[17].wakeup_ports[3].bits.uop.imm_rename \n connect slots_17.io.wakeup_ports[3].bits.uop.taken, issue_slots[17].wakeup_ports[3].bits.uop.taken \n connect slots_17.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[17].wakeup_ports[3].bits.uop.pc_lob \n connect slots_17.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[17].wakeup_ports[3].bits.uop.edge_inst \n connect slots_17.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[17].wakeup_ports[3].bits.uop.ftq_idx \n connect slots_17.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[17].wakeup_ports[3].bits.uop.is_mov \n connect slots_17.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[17].wakeup_ports[3].bits.uop.is_rocc \n connect slots_17.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[17].wakeup_ports[3].bits.uop.is_sys_pc2epc \n connect slots_17.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[17].wakeup_ports[3].bits.uop.is_eret \n connect slots_17.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[17].wakeup_ports[3].bits.uop.is_amo \n connect slots_17.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[17].wakeup_ports[3].bits.uop.is_sfence \n connect slots_17.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[17].wakeup_ports[3].bits.uop.is_fencei \n connect slots_17.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[17].wakeup_ports[3].bits.uop.is_fence \n connect slots_17.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[17].wakeup_ports[3].bits.uop.is_sfb \n connect slots_17.io.wakeup_ports[3].bits.uop.br_type, issue_slots[17].wakeup_ports[3].bits.uop.br_type \n connect slots_17.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[17].wakeup_ports[3].bits.uop.br_tag \n connect slots_17.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[17].wakeup_ports[3].bits.uop.br_mask \n connect slots_17.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[17].wakeup_ports[3].bits.uop.dis_col_sel \n connect slots_17.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[17].wakeup_ports[3].bits.uop.iw_p3_bypass_hint \n connect slots_17.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[17].wakeup_ports[3].bits.uop.iw_p2_bypass_hint \n connect slots_17.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[17].wakeup_ports[3].bits.uop.iw_p1_bypass_hint \n connect slots_17.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[17].wakeup_ports[3].bits.uop.iw_p2_speculative_child \n connect slots_17.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[17].wakeup_ports[3].bits.uop.iw_p1_speculative_child \n connect slots_17.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[17].wakeup_ports[3].bits.uop.iw_issued_partial_dgen \n connect slots_17.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[17].wakeup_ports[3].bits.uop.iw_issued_partial_agen \n connect slots_17.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[17].wakeup_ports[3].bits.uop.iw_issued \n connect slots_17.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[17].wakeup_ports[3].bits.uop.fu_code[0] \n connect slots_17.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[17].wakeup_ports[3].bits.uop.fu_code[1] \n connect slots_17.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[17].wakeup_ports[3].bits.uop.fu_code[2] \n connect slots_17.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[17].wakeup_ports[3].bits.uop.fu_code[3] \n connect slots_17.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[17].wakeup_ports[3].bits.uop.fu_code[4] \n connect slots_17.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[17].wakeup_ports[3].bits.uop.fu_code[5] \n connect slots_17.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[17].wakeup_ports[3].bits.uop.fu_code[6] \n connect slots_17.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[17].wakeup_ports[3].bits.uop.fu_code[7] \n connect slots_17.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[17].wakeup_ports[3].bits.uop.fu_code[8] \n connect slots_17.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[17].wakeup_ports[3].bits.uop.fu_code[9] \n connect slots_17.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[17].wakeup_ports[3].bits.uop.iq_type[0] \n connect slots_17.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[17].wakeup_ports[3].bits.uop.iq_type[1] \n connect slots_17.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[17].wakeup_ports[3].bits.uop.iq_type[2] \n connect slots_17.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[17].wakeup_ports[3].bits.uop.iq_type[3] \n connect slots_17.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[17].wakeup_ports[3].bits.uop.debug_pc \n connect slots_17.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[17].wakeup_ports[3].bits.uop.is_rvc \n connect slots_17.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[17].wakeup_ports[3].bits.uop.debug_inst \n connect slots_17.io.wakeup_ports[3].bits.uop.inst, issue_slots[17].wakeup_ports[3].bits.uop.inst \n connect slots_17.io.wakeup_ports[3].valid, issue_slots[17].wakeup_ports[3].valid \n connect slots_17.io.squash_grant, issue_slots[17].squash_grant \n connect slots_17.io.clear, issue_slots[17].clear \n connect slots_17.io.kill, issue_slots[17].kill \n connect slots_17.io.brupdate.b2.target_offset, issue_slots[17].brupdate.b2.target_offset \n connect slots_17.io.brupdate.b2.jalr_target, issue_slots[17].brupdate.b2.jalr_target \n connect slots_17.io.brupdate.b2.pc_sel, issue_slots[17].brupdate.b2.pc_sel \n connect slots_17.io.brupdate.b2.cfi_type, issue_slots[17].brupdate.b2.cfi_type \n connect slots_17.io.brupdate.b2.taken, issue_slots[17].brupdate.b2.taken \n connect slots_17.io.brupdate.b2.mispredict, issue_slots[17].brupdate.b2.mispredict \n connect slots_17.io.brupdate.b2.uop.debug_tsrc, issue_slots[17].brupdate.b2.uop.debug_tsrc \n connect slots_17.io.brupdate.b2.uop.debug_fsrc, issue_slots[17].brupdate.b2.uop.debug_fsrc \n connect slots_17.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[17].brupdate.b2.uop.bp_xcpt_if \n connect slots_17.io.brupdate.b2.uop.bp_debug_if, issue_slots[17].brupdate.b2.uop.bp_debug_if \n connect slots_17.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[17].brupdate.b2.uop.xcpt_ma_if \n connect slots_17.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[17].brupdate.b2.uop.xcpt_ae_if \n connect slots_17.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[17].brupdate.b2.uop.xcpt_pf_if \n connect slots_17.io.brupdate.b2.uop.fp_typ, issue_slots[17].brupdate.b2.uop.fp_typ \n connect slots_17.io.brupdate.b2.uop.fp_rm, issue_slots[17].brupdate.b2.uop.fp_rm \n connect slots_17.io.brupdate.b2.uop.fp_val, issue_slots[17].brupdate.b2.uop.fp_val \n connect slots_17.io.brupdate.b2.uop.fcn_op, issue_slots[17].brupdate.b2.uop.fcn_op \n connect slots_17.io.brupdate.b2.uop.fcn_dw, issue_slots[17].brupdate.b2.uop.fcn_dw \n connect slots_17.io.brupdate.b2.uop.frs3_en, issue_slots[17].brupdate.b2.uop.frs3_en \n connect slots_17.io.brupdate.b2.uop.lrs2_rtype, issue_slots[17].brupdate.b2.uop.lrs2_rtype \n connect slots_17.io.brupdate.b2.uop.lrs1_rtype, issue_slots[17].brupdate.b2.uop.lrs1_rtype \n connect slots_17.io.brupdate.b2.uop.dst_rtype, issue_slots[17].brupdate.b2.uop.dst_rtype \n connect slots_17.io.brupdate.b2.uop.lrs3, issue_slots[17].brupdate.b2.uop.lrs3 \n connect slots_17.io.brupdate.b2.uop.lrs2, issue_slots[17].brupdate.b2.uop.lrs2 \n connect slots_17.io.brupdate.b2.uop.lrs1, issue_slots[17].brupdate.b2.uop.lrs1 \n connect slots_17.io.brupdate.b2.uop.ldst, issue_slots[17].brupdate.b2.uop.ldst \n connect slots_17.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[17].brupdate.b2.uop.ldst_is_rs1 \n connect slots_17.io.brupdate.b2.uop.csr_cmd, issue_slots[17].brupdate.b2.uop.csr_cmd \n connect slots_17.io.brupdate.b2.uop.flush_on_commit, issue_slots[17].brupdate.b2.uop.flush_on_commit \n connect slots_17.io.brupdate.b2.uop.is_unique, issue_slots[17].brupdate.b2.uop.is_unique \n connect slots_17.io.brupdate.b2.uop.uses_stq, issue_slots[17].brupdate.b2.uop.uses_stq \n connect slots_17.io.brupdate.b2.uop.uses_ldq, issue_slots[17].brupdate.b2.uop.uses_ldq \n connect slots_17.io.brupdate.b2.uop.mem_signed, issue_slots[17].brupdate.b2.uop.mem_signed \n connect slots_17.io.brupdate.b2.uop.mem_size, issue_slots[17].brupdate.b2.uop.mem_size \n connect slots_17.io.brupdate.b2.uop.mem_cmd, issue_slots[17].brupdate.b2.uop.mem_cmd \n connect slots_17.io.brupdate.b2.uop.exc_cause, issue_slots[17].brupdate.b2.uop.exc_cause \n connect slots_17.io.brupdate.b2.uop.exception, issue_slots[17].brupdate.b2.uop.exception \n connect slots_17.io.brupdate.b2.uop.stale_pdst, issue_slots[17].brupdate.b2.uop.stale_pdst \n connect slots_17.io.brupdate.b2.uop.ppred_busy, issue_slots[17].brupdate.b2.uop.ppred_busy \n connect slots_17.io.brupdate.b2.uop.prs3_busy, issue_slots[17].brupdate.b2.uop.prs3_busy \n connect slots_17.io.brupdate.b2.uop.prs2_busy, issue_slots[17].brupdate.b2.uop.prs2_busy \n connect slots_17.io.brupdate.b2.uop.prs1_busy, issue_slots[17].brupdate.b2.uop.prs1_busy \n connect slots_17.io.brupdate.b2.uop.ppred, issue_slots[17].brupdate.b2.uop.ppred \n connect slots_17.io.brupdate.b2.uop.prs3, issue_slots[17].brupdate.b2.uop.prs3 \n connect slots_17.io.brupdate.b2.uop.prs2, issue_slots[17].brupdate.b2.uop.prs2 \n connect slots_17.io.brupdate.b2.uop.prs1, issue_slots[17].brupdate.b2.uop.prs1 \n connect slots_17.io.brupdate.b2.uop.pdst, issue_slots[17].brupdate.b2.uop.pdst \n connect slots_17.io.brupdate.b2.uop.rxq_idx, issue_slots[17].brupdate.b2.uop.rxq_idx \n connect slots_17.io.brupdate.b2.uop.stq_idx, issue_slots[17].brupdate.b2.uop.stq_idx \n connect slots_17.io.brupdate.b2.uop.ldq_idx, issue_slots[17].brupdate.b2.uop.ldq_idx \n connect slots_17.io.brupdate.b2.uop.rob_idx, issue_slots[17].brupdate.b2.uop.rob_idx \n connect slots_17.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[17].brupdate.b2.uop.fp_ctrl.vec \n connect slots_17.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[17].brupdate.b2.uop.fp_ctrl.wflags \n connect slots_17.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[17].brupdate.b2.uop.fp_ctrl.sqrt \n connect slots_17.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[17].brupdate.b2.uop.fp_ctrl.div \n connect slots_17.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[17].brupdate.b2.uop.fp_ctrl.fma \n connect slots_17.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[17].brupdate.b2.uop.fp_ctrl.fastpipe \n connect slots_17.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[17].brupdate.b2.uop.fp_ctrl.toint \n connect slots_17.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[17].brupdate.b2.uop.fp_ctrl.fromint \n connect slots_17.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[17].brupdate.b2.uop.fp_ctrl.typeTagOut \n connect slots_17.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[17].brupdate.b2.uop.fp_ctrl.typeTagIn \n connect slots_17.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[17].brupdate.b2.uop.fp_ctrl.swap23 \n connect slots_17.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[17].brupdate.b2.uop.fp_ctrl.swap12 \n connect slots_17.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[17].brupdate.b2.uop.fp_ctrl.ren3 \n connect slots_17.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[17].brupdate.b2.uop.fp_ctrl.ren2 \n connect slots_17.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[17].brupdate.b2.uop.fp_ctrl.ren1 \n connect slots_17.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[17].brupdate.b2.uop.fp_ctrl.wen \n connect slots_17.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[17].brupdate.b2.uop.fp_ctrl.ldst \n connect slots_17.io.brupdate.b2.uop.op2_sel, issue_slots[17].brupdate.b2.uop.op2_sel \n connect slots_17.io.brupdate.b2.uop.op1_sel, issue_slots[17].brupdate.b2.uop.op1_sel \n connect slots_17.io.brupdate.b2.uop.imm_packed, issue_slots[17].brupdate.b2.uop.imm_packed \n connect slots_17.io.brupdate.b2.uop.pimm, issue_slots[17].brupdate.b2.uop.pimm \n connect slots_17.io.brupdate.b2.uop.imm_sel, issue_slots[17].brupdate.b2.uop.imm_sel \n connect slots_17.io.brupdate.b2.uop.imm_rename, issue_slots[17].brupdate.b2.uop.imm_rename \n connect slots_17.io.brupdate.b2.uop.taken, issue_slots[17].brupdate.b2.uop.taken \n connect slots_17.io.brupdate.b2.uop.pc_lob, issue_slots[17].brupdate.b2.uop.pc_lob \n connect slots_17.io.brupdate.b2.uop.edge_inst, issue_slots[17].brupdate.b2.uop.edge_inst \n connect slots_17.io.brupdate.b2.uop.ftq_idx, issue_slots[17].brupdate.b2.uop.ftq_idx \n connect slots_17.io.brupdate.b2.uop.is_mov, issue_slots[17].brupdate.b2.uop.is_mov \n connect slots_17.io.brupdate.b2.uop.is_rocc, issue_slots[17].brupdate.b2.uop.is_rocc \n connect slots_17.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[17].brupdate.b2.uop.is_sys_pc2epc \n connect slots_17.io.brupdate.b2.uop.is_eret, issue_slots[17].brupdate.b2.uop.is_eret \n connect slots_17.io.brupdate.b2.uop.is_amo, issue_slots[17].brupdate.b2.uop.is_amo \n connect slots_17.io.brupdate.b2.uop.is_sfence, issue_slots[17].brupdate.b2.uop.is_sfence \n connect slots_17.io.brupdate.b2.uop.is_fencei, issue_slots[17].brupdate.b2.uop.is_fencei \n connect slots_17.io.brupdate.b2.uop.is_fence, issue_slots[17].brupdate.b2.uop.is_fence \n connect slots_17.io.brupdate.b2.uop.is_sfb, issue_slots[17].brupdate.b2.uop.is_sfb \n connect slots_17.io.brupdate.b2.uop.br_type, issue_slots[17].brupdate.b2.uop.br_type \n connect slots_17.io.brupdate.b2.uop.br_tag, issue_slots[17].brupdate.b2.uop.br_tag \n connect slots_17.io.brupdate.b2.uop.br_mask, issue_slots[17].brupdate.b2.uop.br_mask \n connect slots_17.io.brupdate.b2.uop.dis_col_sel, issue_slots[17].brupdate.b2.uop.dis_col_sel \n connect slots_17.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[17].brupdate.b2.uop.iw_p3_bypass_hint \n connect slots_17.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[17].brupdate.b2.uop.iw_p2_bypass_hint \n connect slots_17.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[17].brupdate.b2.uop.iw_p1_bypass_hint \n connect slots_17.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[17].brupdate.b2.uop.iw_p2_speculative_child \n connect slots_17.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[17].brupdate.b2.uop.iw_p1_speculative_child \n connect slots_17.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[17].brupdate.b2.uop.iw_issued_partial_dgen \n connect slots_17.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[17].brupdate.b2.uop.iw_issued_partial_agen \n connect slots_17.io.brupdate.b2.uop.iw_issued, issue_slots[17].brupdate.b2.uop.iw_issued \n connect slots_17.io.brupdate.b2.uop.fu_code[0], issue_slots[17].brupdate.b2.uop.fu_code[0] \n connect slots_17.io.brupdate.b2.uop.fu_code[1], issue_slots[17].brupdate.b2.uop.fu_code[1] \n connect slots_17.io.brupdate.b2.uop.fu_code[2], issue_slots[17].brupdate.b2.uop.fu_code[2] \n connect slots_17.io.brupdate.b2.uop.fu_code[3], issue_slots[17].brupdate.b2.uop.fu_code[3] \n connect slots_17.io.brupdate.b2.uop.fu_code[4], issue_slots[17].brupdate.b2.uop.fu_code[4] \n connect slots_17.io.brupdate.b2.uop.fu_code[5], issue_slots[17].brupdate.b2.uop.fu_code[5] \n connect slots_17.io.brupdate.b2.uop.fu_code[6], issue_slots[17].brupdate.b2.uop.fu_code[6] \n connect slots_17.io.brupdate.b2.uop.fu_code[7], issue_slots[17].brupdate.b2.uop.fu_code[7] \n connect slots_17.io.brupdate.b2.uop.fu_code[8], issue_slots[17].brupdate.b2.uop.fu_code[8] \n connect slots_17.io.brupdate.b2.uop.fu_code[9], issue_slots[17].brupdate.b2.uop.fu_code[9] \n connect slots_17.io.brupdate.b2.uop.iq_type[0], issue_slots[17].brupdate.b2.uop.iq_type[0] \n connect slots_17.io.brupdate.b2.uop.iq_type[1], issue_slots[17].brupdate.b2.uop.iq_type[1] \n connect slots_17.io.brupdate.b2.uop.iq_type[2], issue_slots[17].brupdate.b2.uop.iq_type[2] \n connect slots_17.io.brupdate.b2.uop.iq_type[3], issue_slots[17].brupdate.b2.uop.iq_type[3] \n connect slots_17.io.brupdate.b2.uop.debug_pc, issue_slots[17].brupdate.b2.uop.debug_pc \n connect slots_17.io.brupdate.b2.uop.is_rvc, issue_slots[17].brupdate.b2.uop.is_rvc \n connect slots_17.io.brupdate.b2.uop.debug_inst, issue_slots[17].brupdate.b2.uop.debug_inst \n connect slots_17.io.brupdate.b2.uop.inst, issue_slots[17].brupdate.b2.uop.inst \n connect slots_17.io.brupdate.b1.mispredict_mask, issue_slots[17].brupdate.b1.mispredict_mask \n connect slots_17.io.brupdate.b1.resolve_mask, issue_slots[17].brupdate.b1.resolve_mask \n connect issue_slots[17].out_uop.debug_tsrc, slots_17.io.out_uop.debug_tsrc \n connect issue_slots[17].out_uop.debug_fsrc, slots_17.io.out_uop.debug_fsrc \n connect issue_slots[17].out_uop.bp_xcpt_if, slots_17.io.out_uop.bp_xcpt_if \n connect issue_slots[17].out_uop.bp_debug_if, slots_17.io.out_uop.bp_debug_if \n connect issue_slots[17].out_uop.xcpt_ma_if, slots_17.io.out_uop.xcpt_ma_if \n connect issue_slots[17].out_uop.xcpt_ae_if, slots_17.io.out_uop.xcpt_ae_if \n connect issue_slots[17].out_uop.xcpt_pf_if, slots_17.io.out_uop.xcpt_pf_if \n connect issue_slots[17].out_uop.fp_typ, slots_17.io.out_uop.fp_typ \n connect issue_slots[17].out_uop.fp_rm, slots_17.io.out_uop.fp_rm \n connect issue_slots[17].out_uop.fp_val, slots_17.io.out_uop.fp_val \n connect issue_slots[17].out_uop.fcn_op, slots_17.io.out_uop.fcn_op \n connect issue_slots[17].out_uop.fcn_dw, slots_17.io.out_uop.fcn_dw \n connect issue_slots[17].out_uop.frs3_en, slots_17.io.out_uop.frs3_en \n connect issue_slots[17].out_uop.lrs2_rtype, slots_17.io.out_uop.lrs2_rtype \n connect issue_slots[17].out_uop.lrs1_rtype, slots_17.io.out_uop.lrs1_rtype \n connect issue_slots[17].out_uop.dst_rtype, slots_17.io.out_uop.dst_rtype \n connect issue_slots[17].out_uop.lrs3, slots_17.io.out_uop.lrs3 \n connect issue_slots[17].out_uop.lrs2, slots_17.io.out_uop.lrs2 \n connect issue_slots[17].out_uop.lrs1, slots_17.io.out_uop.lrs1 \n connect issue_slots[17].out_uop.ldst, slots_17.io.out_uop.ldst \n connect issue_slots[17].out_uop.ldst_is_rs1, slots_17.io.out_uop.ldst_is_rs1 \n connect issue_slots[17].out_uop.csr_cmd, slots_17.io.out_uop.csr_cmd \n connect issue_slots[17].out_uop.flush_on_commit, slots_17.io.out_uop.flush_on_commit \n connect issue_slots[17].out_uop.is_unique, slots_17.io.out_uop.is_unique \n connect issue_slots[17].out_uop.uses_stq, slots_17.io.out_uop.uses_stq \n connect issue_slots[17].out_uop.uses_ldq, slots_17.io.out_uop.uses_ldq \n connect issue_slots[17].out_uop.mem_signed, slots_17.io.out_uop.mem_signed \n connect issue_slots[17].out_uop.mem_size, slots_17.io.out_uop.mem_size \n connect issue_slots[17].out_uop.mem_cmd, slots_17.io.out_uop.mem_cmd \n connect issue_slots[17].out_uop.exc_cause, slots_17.io.out_uop.exc_cause \n connect issue_slots[17].out_uop.exception, slots_17.io.out_uop.exception \n connect issue_slots[17].out_uop.stale_pdst, slots_17.io.out_uop.stale_pdst \n connect issue_slots[17].out_uop.ppred_busy, slots_17.io.out_uop.ppred_busy \n connect issue_slots[17].out_uop.prs3_busy, slots_17.io.out_uop.prs3_busy \n connect issue_slots[17].out_uop.prs2_busy, slots_17.io.out_uop.prs2_busy \n connect issue_slots[17].out_uop.prs1_busy, slots_17.io.out_uop.prs1_busy \n connect issue_slots[17].out_uop.ppred, slots_17.io.out_uop.ppred \n connect issue_slots[17].out_uop.prs3, slots_17.io.out_uop.prs3 \n connect issue_slots[17].out_uop.prs2, slots_17.io.out_uop.prs2 \n connect issue_slots[17].out_uop.prs1, slots_17.io.out_uop.prs1 \n connect issue_slots[17].out_uop.pdst, slots_17.io.out_uop.pdst \n connect issue_slots[17].out_uop.rxq_idx, slots_17.io.out_uop.rxq_idx \n connect issue_slots[17].out_uop.stq_idx, slots_17.io.out_uop.stq_idx \n connect issue_slots[17].out_uop.ldq_idx, slots_17.io.out_uop.ldq_idx \n connect issue_slots[17].out_uop.rob_idx, slots_17.io.out_uop.rob_idx \n connect issue_slots[17].out_uop.fp_ctrl.vec, slots_17.io.out_uop.fp_ctrl.vec \n connect issue_slots[17].out_uop.fp_ctrl.wflags, slots_17.io.out_uop.fp_ctrl.wflags \n connect issue_slots[17].out_uop.fp_ctrl.sqrt, slots_17.io.out_uop.fp_ctrl.sqrt \n connect issue_slots[17].out_uop.fp_ctrl.div, slots_17.io.out_uop.fp_ctrl.div \n connect issue_slots[17].out_uop.fp_ctrl.fma, slots_17.io.out_uop.fp_ctrl.fma \n connect issue_slots[17].out_uop.fp_ctrl.fastpipe, slots_17.io.out_uop.fp_ctrl.fastpipe \n connect issue_slots[17].out_uop.fp_ctrl.toint, slots_17.io.out_uop.fp_ctrl.toint \n connect issue_slots[17].out_uop.fp_ctrl.fromint, slots_17.io.out_uop.fp_ctrl.fromint \n connect issue_slots[17].out_uop.fp_ctrl.typeTagOut, slots_17.io.out_uop.fp_ctrl.typeTagOut \n connect issue_slots[17].out_uop.fp_ctrl.typeTagIn, slots_17.io.out_uop.fp_ctrl.typeTagIn \n connect issue_slots[17].out_uop.fp_ctrl.swap23, slots_17.io.out_uop.fp_ctrl.swap23 \n connect issue_slots[17].out_uop.fp_ctrl.swap12, slots_17.io.out_uop.fp_ctrl.swap12 \n connect issue_slots[17].out_uop.fp_ctrl.ren3, slots_17.io.out_uop.fp_ctrl.ren3 \n connect issue_slots[17].out_uop.fp_ctrl.ren2, slots_17.io.out_uop.fp_ctrl.ren2 \n connect issue_slots[17].out_uop.fp_ctrl.ren1, slots_17.io.out_uop.fp_ctrl.ren1 \n connect issue_slots[17].out_uop.fp_ctrl.wen, slots_17.io.out_uop.fp_ctrl.wen \n connect issue_slots[17].out_uop.fp_ctrl.ldst, slots_17.io.out_uop.fp_ctrl.ldst \n connect issue_slots[17].out_uop.op2_sel, slots_17.io.out_uop.op2_sel \n connect issue_slots[17].out_uop.op1_sel, slots_17.io.out_uop.op1_sel \n connect issue_slots[17].out_uop.imm_packed, slots_17.io.out_uop.imm_packed \n connect issue_slots[17].out_uop.pimm, slots_17.io.out_uop.pimm \n connect issue_slots[17].out_uop.imm_sel, slots_17.io.out_uop.imm_sel \n connect issue_slots[17].out_uop.imm_rename, slots_17.io.out_uop.imm_rename \n connect issue_slots[17].out_uop.taken, slots_17.io.out_uop.taken \n connect issue_slots[17].out_uop.pc_lob, slots_17.io.out_uop.pc_lob \n connect issue_slots[17].out_uop.edge_inst, slots_17.io.out_uop.edge_inst \n connect issue_slots[17].out_uop.ftq_idx, slots_17.io.out_uop.ftq_idx \n connect issue_slots[17].out_uop.is_mov, slots_17.io.out_uop.is_mov \n connect issue_slots[17].out_uop.is_rocc, slots_17.io.out_uop.is_rocc \n connect issue_slots[17].out_uop.is_sys_pc2epc, slots_17.io.out_uop.is_sys_pc2epc \n connect issue_slots[17].out_uop.is_eret, slots_17.io.out_uop.is_eret \n connect issue_slots[17].out_uop.is_amo, slots_17.io.out_uop.is_amo \n connect issue_slots[17].out_uop.is_sfence, slots_17.io.out_uop.is_sfence \n connect issue_slots[17].out_uop.is_fencei, slots_17.io.out_uop.is_fencei \n connect issue_slots[17].out_uop.is_fence, slots_17.io.out_uop.is_fence \n connect issue_slots[17].out_uop.is_sfb, slots_17.io.out_uop.is_sfb \n connect issue_slots[17].out_uop.br_type, slots_17.io.out_uop.br_type \n connect issue_slots[17].out_uop.br_tag, slots_17.io.out_uop.br_tag \n connect issue_slots[17].out_uop.br_mask, slots_17.io.out_uop.br_mask \n connect issue_slots[17].out_uop.dis_col_sel, slots_17.io.out_uop.dis_col_sel \n connect issue_slots[17].out_uop.iw_p3_bypass_hint, slots_17.io.out_uop.iw_p3_bypass_hint \n connect issue_slots[17].out_uop.iw_p2_bypass_hint, slots_17.io.out_uop.iw_p2_bypass_hint \n connect issue_slots[17].out_uop.iw_p1_bypass_hint, slots_17.io.out_uop.iw_p1_bypass_hint \n connect issue_slots[17].out_uop.iw_p2_speculative_child, slots_17.io.out_uop.iw_p2_speculative_child \n connect issue_slots[17].out_uop.iw_p1_speculative_child, slots_17.io.out_uop.iw_p1_speculative_child \n connect issue_slots[17].out_uop.iw_issued_partial_dgen, slots_17.io.out_uop.iw_issued_partial_dgen \n connect issue_slots[17].out_uop.iw_issued_partial_agen, slots_17.io.out_uop.iw_issued_partial_agen \n connect issue_slots[17].out_uop.iw_issued, slots_17.io.out_uop.iw_issued \n connect issue_slots[17].out_uop.fu_code[0], slots_17.io.out_uop.fu_code[0] \n connect issue_slots[17].out_uop.fu_code[1], slots_17.io.out_uop.fu_code[1] \n connect issue_slots[17].out_uop.fu_code[2], slots_17.io.out_uop.fu_code[2] \n connect issue_slots[17].out_uop.fu_code[3], slots_17.io.out_uop.fu_code[3] \n connect issue_slots[17].out_uop.fu_code[4], slots_17.io.out_uop.fu_code[4] \n connect issue_slots[17].out_uop.fu_code[5], slots_17.io.out_uop.fu_code[5] \n connect issue_slots[17].out_uop.fu_code[6], slots_17.io.out_uop.fu_code[6] \n connect issue_slots[17].out_uop.fu_code[7], slots_17.io.out_uop.fu_code[7] \n connect issue_slots[17].out_uop.fu_code[8], slots_17.io.out_uop.fu_code[8] \n connect issue_slots[17].out_uop.fu_code[9], slots_17.io.out_uop.fu_code[9] \n connect issue_slots[17].out_uop.iq_type[0], slots_17.io.out_uop.iq_type[0] \n connect issue_slots[17].out_uop.iq_type[1], slots_17.io.out_uop.iq_type[1] \n connect issue_slots[17].out_uop.iq_type[2], slots_17.io.out_uop.iq_type[2] \n connect issue_slots[17].out_uop.iq_type[3], slots_17.io.out_uop.iq_type[3] \n connect issue_slots[17].out_uop.debug_pc, slots_17.io.out_uop.debug_pc \n connect issue_slots[17].out_uop.is_rvc, slots_17.io.out_uop.is_rvc \n connect issue_slots[17].out_uop.debug_inst, slots_17.io.out_uop.debug_inst \n connect issue_slots[17].out_uop.inst, slots_17.io.out_uop.inst \n connect slots_17.io.in_uop.bits.debug_tsrc, issue_slots[17].in_uop.bits.debug_tsrc \n connect slots_17.io.in_uop.bits.debug_fsrc, issue_slots[17].in_uop.bits.debug_fsrc \n connect slots_17.io.in_uop.bits.bp_xcpt_if, issue_slots[17].in_uop.bits.bp_xcpt_if \n connect slots_17.io.in_uop.bits.bp_debug_if, issue_slots[17].in_uop.bits.bp_debug_if \n connect slots_17.io.in_uop.bits.xcpt_ma_if, issue_slots[17].in_uop.bits.xcpt_ma_if \n connect slots_17.io.in_uop.bits.xcpt_ae_if, issue_slots[17].in_uop.bits.xcpt_ae_if \n connect slots_17.io.in_uop.bits.xcpt_pf_if, issue_slots[17].in_uop.bits.xcpt_pf_if \n connect slots_17.io.in_uop.bits.fp_typ, issue_slots[17].in_uop.bits.fp_typ \n connect slots_17.io.in_uop.bits.fp_rm, issue_slots[17].in_uop.bits.fp_rm \n connect slots_17.io.in_uop.bits.fp_val, issue_slots[17].in_uop.bits.fp_val \n connect slots_17.io.in_uop.bits.fcn_op, issue_slots[17].in_uop.bits.fcn_op \n connect slots_17.io.in_uop.bits.fcn_dw, issue_slots[17].in_uop.bits.fcn_dw \n connect slots_17.io.in_uop.bits.frs3_en, issue_slots[17].in_uop.bits.frs3_en \n connect slots_17.io.in_uop.bits.lrs2_rtype, issue_slots[17].in_uop.bits.lrs2_rtype \n connect slots_17.io.in_uop.bits.lrs1_rtype, issue_slots[17].in_uop.bits.lrs1_rtype \n connect slots_17.io.in_uop.bits.dst_rtype, issue_slots[17].in_uop.bits.dst_rtype \n connect slots_17.io.in_uop.bits.lrs3, issue_slots[17].in_uop.bits.lrs3 \n connect slots_17.io.in_uop.bits.lrs2, issue_slots[17].in_uop.bits.lrs2 \n connect slots_17.io.in_uop.bits.lrs1, issue_slots[17].in_uop.bits.lrs1 \n connect slots_17.io.in_uop.bits.ldst, issue_slots[17].in_uop.bits.ldst \n connect slots_17.io.in_uop.bits.ldst_is_rs1, issue_slots[17].in_uop.bits.ldst_is_rs1 \n connect slots_17.io.in_uop.bits.csr_cmd, issue_slots[17].in_uop.bits.csr_cmd \n connect slots_17.io.in_uop.bits.flush_on_commit, issue_slots[17].in_uop.bits.flush_on_commit \n connect slots_17.io.in_uop.bits.is_unique, issue_slots[17].in_uop.bits.is_unique \n connect slots_17.io.in_uop.bits.uses_stq, issue_slots[17].in_uop.bits.uses_stq \n connect slots_17.io.in_uop.bits.uses_ldq, issue_slots[17].in_uop.bits.uses_ldq \n connect slots_17.io.in_uop.bits.mem_signed, issue_slots[17].in_uop.bits.mem_signed \n connect slots_17.io.in_uop.bits.mem_size, issue_slots[17].in_uop.bits.mem_size \n connect slots_17.io.in_uop.bits.mem_cmd, issue_slots[17].in_uop.bits.mem_cmd \n connect slots_17.io.in_uop.bits.exc_cause, issue_slots[17].in_uop.bits.exc_cause \n connect slots_17.io.in_uop.bits.exception, issue_slots[17].in_uop.bits.exception \n connect slots_17.io.in_uop.bits.stale_pdst, issue_slots[17].in_uop.bits.stale_pdst \n connect slots_17.io.in_uop.bits.ppred_busy, issue_slots[17].in_uop.bits.ppred_busy \n connect slots_17.io.in_uop.bits.prs3_busy, issue_slots[17].in_uop.bits.prs3_busy \n connect slots_17.io.in_uop.bits.prs2_busy, issue_slots[17].in_uop.bits.prs2_busy \n connect slots_17.io.in_uop.bits.prs1_busy, issue_slots[17].in_uop.bits.prs1_busy \n connect slots_17.io.in_uop.bits.ppred, issue_slots[17].in_uop.bits.ppred \n connect slots_17.io.in_uop.bits.prs3, issue_slots[17].in_uop.bits.prs3 \n connect slots_17.io.in_uop.bits.prs2, issue_slots[17].in_uop.bits.prs2 \n connect slots_17.io.in_uop.bits.prs1, issue_slots[17].in_uop.bits.prs1 \n connect slots_17.io.in_uop.bits.pdst, issue_slots[17].in_uop.bits.pdst \n connect slots_17.io.in_uop.bits.rxq_idx, issue_slots[17].in_uop.bits.rxq_idx \n connect slots_17.io.in_uop.bits.stq_idx, issue_slots[17].in_uop.bits.stq_idx \n connect slots_17.io.in_uop.bits.ldq_idx, issue_slots[17].in_uop.bits.ldq_idx \n connect slots_17.io.in_uop.bits.rob_idx, issue_slots[17].in_uop.bits.rob_idx \n connect slots_17.io.in_uop.bits.fp_ctrl.vec, issue_slots[17].in_uop.bits.fp_ctrl.vec \n connect slots_17.io.in_uop.bits.fp_ctrl.wflags, issue_slots[17].in_uop.bits.fp_ctrl.wflags \n connect slots_17.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[17].in_uop.bits.fp_ctrl.sqrt \n connect slots_17.io.in_uop.bits.fp_ctrl.div, issue_slots[17].in_uop.bits.fp_ctrl.div \n connect slots_17.io.in_uop.bits.fp_ctrl.fma, issue_slots[17].in_uop.bits.fp_ctrl.fma \n connect slots_17.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[17].in_uop.bits.fp_ctrl.fastpipe \n connect slots_17.io.in_uop.bits.fp_ctrl.toint, issue_slots[17].in_uop.bits.fp_ctrl.toint \n connect slots_17.io.in_uop.bits.fp_ctrl.fromint, issue_slots[17].in_uop.bits.fp_ctrl.fromint \n connect slots_17.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[17].in_uop.bits.fp_ctrl.typeTagOut \n connect slots_17.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[17].in_uop.bits.fp_ctrl.typeTagIn \n connect slots_17.io.in_uop.bits.fp_ctrl.swap23, issue_slots[17].in_uop.bits.fp_ctrl.swap23 \n connect slots_17.io.in_uop.bits.fp_ctrl.swap12, issue_slots[17].in_uop.bits.fp_ctrl.swap12 \n connect slots_17.io.in_uop.bits.fp_ctrl.ren3, issue_slots[17].in_uop.bits.fp_ctrl.ren3 \n connect slots_17.io.in_uop.bits.fp_ctrl.ren2, issue_slots[17].in_uop.bits.fp_ctrl.ren2 \n connect slots_17.io.in_uop.bits.fp_ctrl.ren1, issue_slots[17].in_uop.bits.fp_ctrl.ren1 \n connect slots_17.io.in_uop.bits.fp_ctrl.wen, issue_slots[17].in_uop.bits.fp_ctrl.wen \n connect slots_17.io.in_uop.bits.fp_ctrl.ldst, issue_slots[17].in_uop.bits.fp_ctrl.ldst \n connect slots_17.io.in_uop.bits.op2_sel, issue_slots[17].in_uop.bits.op2_sel \n connect slots_17.io.in_uop.bits.op1_sel, issue_slots[17].in_uop.bits.op1_sel \n connect slots_17.io.in_uop.bits.imm_packed, issue_slots[17].in_uop.bits.imm_packed \n connect slots_17.io.in_uop.bits.pimm, issue_slots[17].in_uop.bits.pimm \n connect slots_17.io.in_uop.bits.imm_sel, issue_slots[17].in_uop.bits.imm_sel \n connect slots_17.io.in_uop.bits.imm_rename, issue_slots[17].in_uop.bits.imm_rename \n connect slots_17.io.in_uop.bits.taken, issue_slots[17].in_uop.bits.taken \n connect slots_17.io.in_uop.bits.pc_lob, issue_slots[17].in_uop.bits.pc_lob \n connect slots_17.io.in_uop.bits.edge_inst, issue_slots[17].in_uop.bits.edge_inst \n connect slots_17.io.in_uop.bits.ftq_idx, issue_slots[17].in_uop.bits.ftq_idx \n connect slots_17.io.in_uop.bits.is_mov, issue_slots[17].in_uop.bits.is_mov \n connect slots_17.io.in_uop.bits.is_rocc, issue_slots[17].in_uop.bits.is_rocc \n connect slots_17.io.in_uop.bits.is_sys_pc2epc, issue_slots[17].in_uop.bits.is_sys_pc2epc \n connect slots_17.io.in_uop.bits.is_eret, issue_slots[17].in_uop.bits.is_eret \n connect slots_17.io.in_uop.bits.is_amo, issue_slots[17].in_uop.bits.is_amo \n connect slots_17.io.in_uop.bits.is_sfence, issue_slots[17].in_uop.bits.is_sfence \n connect slots_17.io.in_uop.bits.is_fencei, issue_slots[17].in_uop.bits.is_fencei \n connect slots_17.io.in_uop.bits.is_fence, issue_slots[17].in_uop.bits.is_fence \n connect slots_17.io.in_uop.bits.is_sfb, issue_slots[17].in_uop.bits.is_sfb \n connect slots_17.io.in_uop.bits.br_type, issue_slots[17].in_uop.bits.br_type \n connect slots_17.io.in_uop.bits.br_tag, issue_slots[17].in_uop.bits.br_tag \n connect slots_17.io.in_uop.bits.br_mask, issue_slots[17].in_uop.bits.br_mask \n connect slots_17.io.in_uop.bits.dis_col_sel, issue_slots[17].in_uop.bits.dis_col_sel \n connect slots_17.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[17].in_uop.bits.iw_p3_bypass_hint \n connect slots_17.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[17].in_uop.bits.iw_p2_bypass_hint \n connect slots_17.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[17].in_uop.bits.iw_p1_bypass_hint \n connect slots_17.io.in_uop.bits.iw_p2_speculative_child, issue_slots[17].in_uop.bits.iw_p2_speculative_child \n connect slots_17.io.in_uop.bits.iw_p1_speculative_child, issue_slots[17].in_uop.bits.iw_p1_speculative_child \n connect slots_17.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[17].in_uop.bits.iw_issued_partial_dgen \n connect slots_17.io.in_uop.bits.iw_issued_partial_agen, issue_slots[17].in_uop.bits.iw_issued_partial_agen \n connect slots_17.io.in_uop.bits.iw_issued, issue_slots[17].in_uop.bits.iw_issued \n connect slots_17.io.in_uop.bits.fu_code[0], issue_slots[17].in_uop.bits.fu_code[0] \n connect slots_17.io.in_uop.bits.fu_code[1], issue_slots[17].in_uop.bits.fu_code[1] \n connect slots_17.io.in_uop.bits.fu_code[2], issue_slots[17].in_uop.bits.fu_code[2] \n connect slots_17.io.in_uop.bits.fu_code[3], issue_slots[17].in_uop.bits.fu_code[3] \n connect slots_17.io.in_uop.bits.fu_code[4], issue_slots[17].in_uop.bits.fu_code[4] \n connect slots_17.io.in_uop.bits.fu_code[5], issue_slots[17].in_uop.bits.fu_code[5] \n connect slots_17.io.in_uop.bits.fu_code[6], issue_slots[17].in_uop.bits.fu_code[6] \n connect slots_17.io.in_uop.bits.fu_code[7], issue_slots[17].in_uop.bits.fu_code[7] \n connect slots_17.io.in_uop.bits.fu_code[8], issue_slots[17].in_uop.bits.fu_code[8] \n connect slots_17.io.in_uop.bits.fu_code[9], issue_slots[17].in_uop.bits.fu_code[9] \n connect slots_17.io.in_uop.bits.iq_type[0], issue_slots[17].in_uop.bits.iq_type[0] \n connect slots_17.io.in_uop.bits.iq_type[1], issue_slots[17].in_uop.bits.iq_type[1] \n connect slots_17.io.in_uop.bits.iq_type[2], issue_slots[17].in_uop.bits.iq_type[2] \n connect slots_17.io.in_uop.bits.iq_type[3], issue_slots[17].in_uop.bits.iq_type[3] \n connect slots_17.io.in_uop.bits.debug_pc, issue_slots[17].in_uop.bits.debug_pc \n connect slots_17.io.in_uop.bits.is_rvc, issue_slots[17].in_uop.bits.is_rvc \n connect slots_17.io.in_uop.bits.debug_inst, issue_slots[17].in_uop.bits.debug_inst \n connect slots_17.io.in_uop.bits.inst, issue_slots[17].in_uop.bits.inst \n connect slots_17.io.in_uop.valid, issue_slots[17].in_uop.valid \n connect issue_slots[17].iss_uop.debug_tsrc, slots_17.io.iss_uop.debug_tsrc \n connect issue_slots[17].iss_uop.debug_fsrc, slots_17.io.iss_uop.debug_fsrc \n connect issue_slots[17].iss_uop.bp_xcpt_if, slots_17.io.iss_uop.bp_xcpt_if \n connect issue_slots[17].iss_uop.bp_debug_if, slots_17.io.iss_uop.bp_debug_if \n connect issue_slots[17].iss_uop.xcpt_ma_if, slots_17.io.iss_uop.xcpt_ma_if \n connect issue_slots[17].iss_uop.xcpt_ae_if, slots_17.io.iss_uop.xcpt_ae_if \n connect issue_slots[17].iss_uop.xcpt_pf_if, slots_17.io.iss_uop.xcpt_pf_if \n connect issue_slots[17].iss_uop.fp_typ, slots_17.io.iss_uop.fp_typ \n connect issue_slots[17].iss_uop.fp_rm, slots_17.io.iss_uop.fp_rm \n connect issue_slots[17].iss_uop.fp_val, slots_17.io.iss_uop.fp_val \n connect issue_slots[17].iss_uop.fcn_op, slots_17.io.iss_uop.fcn_op \n connect issue_slots[17].iss_uop.fcn_dw, slots_17.io.iss_uop.fcn_dw \n connect issue_slots[17].iss_uop.frs3_en, slots_17.io.iss_uop.frs3_en \n connect issue_slots[17].iss_uop.lrs2_rtype, slots_17.io.iss_uop.lrs2_rtype \n connect issue_slots[17].iss_uop.lrs1_rtype, slots_17.io.iss_uop.lrs1_rtype \n connect issue_slots[17].iss_uop.dst_rtype, slots_17.io.iss_uop.dst_rtype \n connect issue_slots[17].iss_uop.lrs3, slots_17.io.iss_uop.lrs3 \n connect issue_slots[17].iss_uop.lrs2, slots_17.io.iss_uop.lrs2 \n connect issue_slots[17].iss_uop.lrs1, slots_17.io.iss_uop.lrs1 \n connect issue_slots[17].iss_uop.ldst, slots_17.io.iss_uop.ldst \n connect issue_slots[17].iss_uop.ldst_is_rs1, slots_17.io.iss_uop.ldst_is_rs1 \n connect issue_slots[17].iss_uop.csr_cmd, slots_17.io.iss_uop.csr_cmd \n connect issue_slots[17].iss_uop.flush_on_commit, slots_17.io.iss_uop.flush_on_commit \n connect issue_slots[17].iss_uop.is_unique, slots_17.io.iss_uop.is_unique \n connect issue_slots[17].iss_uop.uses_stq, slots_17.io.iss_uop.uses_stq \n connect issue_slots[17].iss_uop.uses_ldq, slots_17.io.iss_uop.uses_ldq \n connect issue_slots[17].iss_uop.mem_signed, slots_17.io.iss_uop.mem_signed \n connect issue_slots[17].iss_uop.mem_size, slots_17.io.iss_uop.mem_size \n connect issue_slots[17].iss_uop.mem_cmd, slots_17.io.iss_uop.mem_cmd \n connect issue_slots[17].iss_uop.exc_cause, slots_17.io.iss_uop.exc_cause \n connect issue_slots[17].iss_uop.exception, slots_17.io.iss_uop.exception \n connect issue_slots[17].iss_uop.stale_pdst, slots_17.io.iss_uop.stale_pdst \n connect issue_slots[17].iss_uop.ppred_busy, slots_17.io.iss_uop.ppred_busy \n connect issue_slots[17].iss_uop.prs3_busy, slots_17.io.iss_uop.prs3_busy \n connect issue_slots[17].iss_uop.prs2_busy, slots_17.io.iss_uop.prs2_busy \n connect issue_slots[17].iss_uop.prs1_busy, slots_17.io.iss_uop.prs1_busy \n connect issue_slots[17].iss_uop.ppred, slots_17.io.iss_uop.ppred \n connect issue_slots[17].iss_uop.prs3, slots_17.io.iss_uop.prs3 \n connect issue_slots[17].iss_uop.prs2, slots_17.io.iss_uop.prs2 \n connect issue_slots[17].iss_uop.prs1, slots_17.io.iss_uop.prs1 \n connect issue_slots[17].iss_uop.pdst, slots_17.io.iss_uop.pdst \n connect issue_slots[17].iss_uop.rxq_idx, slots_17.io.iss_uop.rxq_idx \n connect issue_slots[17].iss_uop.stq_idx, slots_17.io.iss_uop.stq_idx \n connect issue_slots[17].iss_uop.ldq_idx, slots_17.io.iss_uop.ldq_idx \n connect issue_slots[17].iss_uop.rob_idx, slots_17.io.iss_uop.rob_idx \n connect issue_slots[17].iss_uop.fp_ctrl.vec, slots_17.io.iss_uop.fp_ctrl.vec \n connect issue_slots[17].iss_uop.fp_ctrl.wflags, slots_17.io.iss_uop.fp_ctrl.wflags \n connect issue_slots[17].iss_uop.fp_ctrl.sqrt, slots_17.io.iss_uop.fp_ctrl.sqrt \n connect issue_slots[17].iss_uop.fp_ctrl.div, slots_17.io.iss_uop.fp_ctrl.div \n connect issue_slots[17].iss_uop.fp_ctrl.fma, slots_17.io.iss_uop.fp_ctrl.fma \n connect issue_slots[17].iss_uop.fp_ctrl.fastpipe, slots_17.io.iss_uop.fp_ctrl.fastpipe \n connect issue_slots[17].iss_uop.fp_ctrl.toint, slots_17.io.iss_uop.fp_ctrl.toint \n connect issue_slots[17].iss_uop.fp_ctrl.fromint, slots_17.io.iss_uop.fp_ctrl.fromint \n connect issue_slots[17].iss_uop.fp_ctrl.typeTagOut, slots_17.io.iss_uop.fp_ctrl.typeTagOut \n connect issue_slots[17].iss_uop.fp_ctrl.typeTagIn, slots_17.io.iss_uop.fp_ctrl.typeTagIn \n connect issue_slots[17].iss_uop.fp_ctrl.swap23, slots_17.io.iss_uop.fp_ctrl.swap23 \n connect issue_slots[17].iss_uop.fp_ctrl.swap12, slots_17.io.iss_uop.fp_ctrl.swap12 \n connect issue_slots[17].iss_uop.fp_ctrl.ren3, slots_17.io.iss_uop.fp_ctrl.ren3 \n connect issue_slots[17].iss_uop.fp_ctrl.ren2, slots_17.io.iss_uop.fp_ctrl.ren2 \n connect issue_slots[17].iss_uop.fp_ctrl.ren1, slots_17.io.iss_uop.fp_ctrl.ren1 \n connect issue_slots[17].iss_uop.fp_ctrl.wen, slots_17.io.iss_uop.fp_ctrl.wen \n connect issue_slots[17].iss_uop.fp_ctrl.ldst, slots_17.io.iss_uop.fp_ctrl.ldst \n connect issue_slots[17].iss_uop.op2_sel, slots_17.io.iss_uop.op2_sel \n connect issue_slots[17].iss_uop.op1_sel, slots_17.io.iss_uop.op1_sel \n connect issue_slots[17].iss_uop.imm_packed, slots_17.io.iss_uop.imm_packed \n connect issue_slots[17].iss_uop.pimm, slots_17.io.iss_uop.pimm \n connect issue_slots[17].iss_uop.imm_sel, slots_17.io.iss_uop.imm_sel \n connect issue_slots[17].iss_uop.imm_rename, slots_17.io.iss_uop.imm_rename \n connect issue_slots[17].iss_uop.taken, slots_17.io.iss_uop.taken \n connect issue_slots[17].iss_uop.pc_lob, slots_17.io.iss_uop.pc_lob \n connect issue_slots[17].iss_uop.edge_inst, slots_17.io.iss_uop.edge_inst \n connect issue_slots[17].iss_uop.ftq_idx, slots_17.io.iss_uop.ftq_idx \n connect issue_slots[17].iss_uop.is_mov, slots_17.io.iss_uop.is_mov \n connect issue_slots[17].iss_uop.is_rocc, slots_17.io.iss_uop.is_rocc \n connect issue_slots[17].iss_uop.is_sys_pc2epc, slots_17.io.iss_uop.is_sys_pc2epc \n connect issue_slots[17].iss_uop.is_eret, slots_17.io.iss_uop.is_eret \n connect issue_slots[17].iss_uop.is_amo, slots_17.io.iss_uop.is_amo \n connect issue_slots[17].iss_uop.is_sfence, slots_17.io.iss_uop.is_sfence \n connect issue_slots[17].iss_uop.is_fencei, slots_17.io.iss_uop.is_fencei \n connect issue_slots[17].iss_uop.is_fence, slots_17.io.iss_uop.is_fence \n connect issue_slots[17].iss_uop.is_sfb, slots_17.io.iss_uop.is_sfb \n connect issue_slots[17].iss_uop.br_type, slots_17.io.iss_uop.br_type \n connect issue_slots[17].iss_uop.br_tag, slots_17.io.iss_uop.br_tag \n connect issue_slots[17].iss_uop.br_mask, slots_17.io.iss_uop.br_mask \n connect issue_slots[17].iss_uop.dis_col_sel, slots_17.io.iss_uop.dis_col_sel \n connect issue_slots[17].iss_uop.iw_p3_bypass_hint, slots_17.io.iss_uop.iw_p3_bypass_hint \n connect issue_slots[17].iss_uop.iw_p2_bypass_hint, slots_17.io.iss_uop.iw_p2_bypass_hint \n connect issue_slots[17].iss_uop.iw_p1_bypass_hint, slots_17.io.iss_uop.iw_p1_bypass_hint \n connect issue_slots[17].iss_uop.iw_p2_speculative_child, slots_17.io.iss_uop.iw_p2_speculative_child \n connect issue_slots[17].iss_uop.iw_p1_speculative_child, slots_17.io.iss_uop.iw_p1_speculative_child \n connect issue_slots[17].iss_uop.iw_issued_partial_dgen, slots_17.io.iss_uop.iw_issued_partial_dgen \n connect issue_slots[17].iss_uop.iw_issued_partial_agen, slots_17.io.iss_uop.iw_issued_partial_agen \n connect issue_slots[17].iss_uop.iw_issued, slots_17.io.iss_uop.iw_issued \n connect issue_slots[17].iss_uop.fu_code[0], slots_17.io.iss_uop.fu_code[0] \n connect issue_slots[17].iss_uop.fu_code[1], slots_17.io.iss_uop.fu_code[1] \n connect issue_slots[17].iss_uop.fu_code[2], slots_17.io.iss_uop.fu_code[2] \n connect issue_slots[17].iss_uop.fu_code[3], slots_17.io.iss_uop.fu_code[3] \n connect issue_slots[17].iss_uop.fu_code[4], slots_17.io.iss_uop.fu_code[4] \n connect issue_slots[17].iss_uop.fu_code[5], slots_17.io.iss_uop.fu_code[5] \n connect issue_slots[17].iss_uop.fu_code[6], slots_17.io.iss_uop.fu_code[6] \n connect issue_slots[17].iss_uop.fu_code[7], slots_17.io.iss_uop.fu_code[7] \n connect issue_slots[17].iss_uop.fu_code[8], slots_17.io.iss_uop.fu_code[8] \n connect issue_slots[17].iss_uop.fu_code[9], slots_17.io.iss_uop.fu_code[9] \n connect issue_slots[17].iss_uop.iq_type[0], slots_17.io.iss_uop.iq_type[0] \n connect issue_slots[17].iss_uop.iq_type[1], slots_17.io.iss_uop.iq_type[1] \n connect issue_slots[17].iss_uop.iq_type[2], slots_17.io.iss_uop.iq_type[2] \n connect issue_slots[17].iss_uop.iq_type[3], slots_17.io.iss_uop.iq_type[3] \n connect issue_slots[17].iss_uop.debug_pc, slots_17.io.iss_uop.debug_pc \n connect issue_slots[17].iss_uop.is_rvc, slots_17.io.iss_uop.is_rvc \n connect issue_slots[17].iss_uop.debug_inst, slots_17.io.iss_uop.debug_inst \n connect issue_slots[17].iss_uop.inst, slots_17.io.iss_uop.inst \n connect slots_17.io.grant, issue_slots[17].grant \n connect issue_slots[17].request, slots_17.io.request \n connect issue_slots[17].will_be_valid, slots_17.io.will_be_valid \n connect issue_slots[17].valid, slots_17.io.valid \n connect slots_18.io.child_rebusys, issue_slots[18].child_rebusys \n connect slots_18.io.pred_wakeup_port.bits, issue_slots[18].pred_wakeup_port.bits \n connect slots_18.io.pred_wakeup_port.valid, issue_slots[18].pred_wakeup_port.valid \n connect slots_18.io.wakeup_ports[0].bits.rebusy, issue_slots[18].wakeup_ports[0].bits.rebusy \n connect slots_18.io.wakeup_ports[0].bits.speculative_mask, issue_slots[18].wakeup_ports[0].bits.speculative_mask \n connect slots_18.io.wakeup_ports[0].bits.bypassable, issue_slots[18].wakeup_ports[0].bits.bypassable \n connect slots_18.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[18].wakeup_ports[0].bits.uop.debug_tsrc \n connect slots_18.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[18].wakeup_ports[0].bits.uop.debug_fsrc \n connect slots_18.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[18].wakeup_ports[0].bits.uop.bp_xcpt_if \n connect slots_18.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[18].wakeup_ports[0].bits.uop.bp_debug_if \n connect slots_18.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[18].wakeup_ports[0].bits.uop.xcpt_ma_if \n connect slots_18.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[18].wakeup_ports[0].bits.uop.xcpt_ae_if \n connect slots_18.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[18].wakeup_ports[0].bits.uop.xcpt_pf_if \n connect slots_18.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[18].wakeup_ports[0].bits.uop.fp_typ \n connect slots_18.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[18].wakeup_ports[0].bits.uop.fp_rm \n connect slots_18.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[18].wakeup_ports[0].bits.uop.fp_val \n connect slots_18.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[18].wakeup_ports[0].bits.uop.fcn_op \n connect slots_18.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[18].wakeup_ports[0].bits.uop.fcn_dw \n connect slots_18.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[18].wakeup_ports[0].bits.uop.frs3_en \n connect slots_18.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[18].wakeup_ports[0].bits.uop.lrs2_rtype \n connect slots_18.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[18].wakeup_ports[0].bits.uop.lrs1_rtype \n connect slots_18.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[18].wakeup_ports[0].bits.uop.dst_rtype \n connect slots_18.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[18].wakeup_ports[0].bits.uop.lrs3 \n connect slots_18.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[18].wakeup_ports[0].bits.uop.lrs2 \n connect slots_18.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[18].wakeup_ports[0].bits.uop.lrs1 \n connect slots_18.io.wakeup_ports[0].bits.uop.ldst, issue_slots[18].wakeup_ports[0].bits.uop.ldst \n connect slots_18.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[18].wakeup_ports[0].bits.uop.ldst_is_rs1 \n connect slots_18.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[18].wakeup_ports[0].bits.uop.csr_cmd \n connect slots_18.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[18].wakeup_ports[0].bits.uop.flush_on_commit \n connect slots_18.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[18].wakeup_ports[0].bits.uop.is_unique \n connect slots_18.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[18].wakeup_ports[0].bits.uop.uses_stq \n connect slots_18.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[18].wakeup_ports[0].bits.uop.uses_ldq \n connect slots_18.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[18].wakeup_ports[0].bits.uop.mem_signed \n connect slots_18.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[18].wakeup_ports[0].bits.uop.mem_size \n connect slots_18.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[18].wakeup_ports[0].bits.uop.mem_cmd \n connect slots_18.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[18].wakeup_ports[0].bits.uop.exc_cause \n connect slots_18.io.wakeup_ports[0].bits.uop.exception, issue_slots[18].wakeup_ports[0].bits.uop.exception \n connect slots_18.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[18].wakeup_ports[0].bits.uop.stale_pdst \n connect slots_18.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[18].wakeup_ports[0].bits.uop.ppred_busy \n connect slots_18.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[18].wakeup_ports[0].bits.uop.prs3_busy \n connect slots_18.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[18].wakeup_ports[0].bits.uop.prs2_busy \n connect slots_18.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[18].wakeup_ports[0].bits.uop.prs1_busy \n connect slots_18.io.wakeup_ports[0].bits.uop.ppred, issue_slots[18].wakeup_ports[0].bits.uop.ppred \n connect slots_18.io.wakeup_ports[0].bits.uop.prs3, issue_slots[18].wakeup_ports[0].bits.uop.prs3 \n connect slots_18.io.wakeup_ports[0].bits.uop.prs2, issue_slots[18].wakeup_ports[0].bits.uop.prs2 \n connect slots_18.io.wakeup_ports[0].bits.uop.prs1, issue_slots[18].wakeup_ports[0].bits.uop.prs1 \n connect slots_18.io.wakeup_ports[0].bits.uop.pdst, issue_slots[18].wakeup_ports[0].bits.uop.pdst \n connect slots_18.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[18].wakeup_ports[0].bits.uop.rxq_idx \n connect slots_18.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[18].wakeup_ports[0].bits.uop.stq_idx \n connect slots_18.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[18].wakeup_ports[0].bits.uop.ldq_idx \n connect slots_18.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[18].wakeup_ports[0].bits.uop.rob_idx \n connect slots_18.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.vec \n connect slots_18.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.wflags \n connect slots_18.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.sqrt \n connect slots_18.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.div \n connect slots_18.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.fma \n connect slots_18.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe \n connect slots_18.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.toint \n connect slots_18.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.fromint \n connect slots_18.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut \n connect slots_18.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn \n connect slots_18.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.swap23 \n connect slots_18.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.swap12 \n connect slots_18.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.ren3 \n connect slots_18.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.ren2 \n connect slots_18.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.ren1 \n connect slots_18.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.wen \n connect slots_18.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.ldst \n connect slots_18.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[18].wakeup_ports[0].bits.uop.op2_sel \n connect slots_18.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[18].wakeup_ports[0].bits.uop.op1_sel \n connect slots_18.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[18].wakeup_ports[0].bits.uop.imm_packed \n connect slots_18.io.wakeup_ports[0].bits.uop.pimm, issue_slots[18].wakeup_ports[0].bits.uop.pimm \n connect slots_18.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[18].wakeup_ports[0].bits.uop.imm_sel \n connect slots_18.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[18].wakeup_ports[0].bits.uop.imm_rename \n connect slots_18.io.wakeup_ports[0].bits.uop.taken, issue_slots[18].wakeup_ports[0].bits.uop.taken \n connect slots_18.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[18].wakeup_ports[0].bits.uop.pc_lob \n connect slots_18.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[18].wakeup_ports[0].bits.uop.edge_inst \n connect slots_18.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[18].wakeup_ports[0].bits.uop.ftq_idx \n connect slots_18.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[18].wakeup_ports[0].bits.uop.is_mov \n connect slots_18.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[18].wakeup_ports[0].bits.uop.is_rocc \n connect slots_18.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[18].wakeup_ports[0].bits.uop.is_sys_pc2epc \n connect slots_18.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[18].wakeup_ports[0].bits.uop.is_eret \n connect slots_18.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[18].wakeup_ports[0].bits.uop.is_amo \n connect slots_18.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[18].wakeup_ports[0].bits.uop.is_sfence \n connect slots_18.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[18].wakeup_ports[0].bits.uop.is_fencei \n connect slots_18.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[18].wakeup_ports[0].bits.uop.is_fence \n connect slots_18.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[18].wakeup_ports[0].bits.uop.is_sfb \n connect slots_18.io.wakeup_ports[0].bits.uop.br_type, issue_slots[18].wakeup_ports[0].bits.uop.br_type \n connect slots_18.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[18].wakeup_ports[0].bits.uop.br_tag \n connect slots_18.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[18].wakeup_ports[0].bits.uop.br_mask \n connect slots_18.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[18].wakeup_ports[0].bits.uop.dis_col_sel \n connect slots_18.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[18].wakeup_ports[0].bits.uop.iw_p3_bypass_hint \n connect slots_18.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[18].wakeup_ports[0].bits.uop.iw_p2_bypass_hint \n connect slots_18.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[18].wakeup_ports[0].bits.uop.iw_p1_bypass_hint \n connect slots_18.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[18].wakeup_ports[0].bits.uop.iw_p2_speculative_child \n connect slots_18.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[18].wakeup_ports[0].bits.uop.iw_p1_speculative_child \n connect slots_18.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[18].wakeup_ports[0].bits.uop.iw_issued_partial_dgen \n connect slots_18.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[18].wakeup_ports[0].bits.uop.iw_issued_partial_agen \n connect slots_18.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[18].wakeup_ports[0].bits.uop.iw_issued \n connect slots_18.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[18].wakeup_ports[0].bits.uop.fu_code[0] \n connect slots_18.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[18].wakeup_ports[0].bits.uop.fu_code[1] \n connect slots_18.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[18].wakeup_ports[0].bits.uop.fu_code[2] \n connect slots_18.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[18].wakeup_ports[0].bits.uop.fu_code[3] \n connect slots_18.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[18].wakeup_ports[0].bits.uop.fu_code[4] \n connect slots_18.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[18].wakeup_ports[0].bits.uop.fu_code[5] \n connect slots_18.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[18].wakeup_ports[0].bits.uop.fu_code[6] \n connect slots_18.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[18].wakeup_ports[0].bits.uop.fu_code[7] \n connect slots_18.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[18].wakeup_ports[0].bits.uop.fu_code[8] \n connect slots_18.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[18].wakeup_ports[0].bits.uop.fu_code[9] \n connect slots_18.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[18].wakeup_ports[0].bits.uop.iq_type[0] \n connect slots_18.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[18].wakeup_ports[0].bits.uop.iq_type[1] \n connect slots_18.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[18].wakeup_ports[0].bits.uop.iq_type[2] \n connect slots_18.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[18].wakeup_ports[0].bits.uop.iq_type[3] \n connect slots_18.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[18].wakeup_ports[0].bits.uop.debug_pc \n connect slots_18.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[18].wakeup_ports[0].bits.uop.is_rvc \n connect slots_18.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[18].wakeup_ports[0].bits.uop.debug_inst \n connect slots_18.io.wakeup_ports[0].bits.uop.inst, issue_slots[18].wakeup_ports[0].bits.uop.inst \n connect slots_18.io.wakeup_ports[0].valid, issue_slots[18].wakeup_ports[0].valid \n connect slots_18.io.wakeup_ports[1].bits.rebusy, issue_slots[18].wakeup_ports[1].bits.rebusy \n connect slots_18.io.wakeup_ports[1].bits.speculative_mask, issue_slots[18].wakeup_ports[1].bits.speculative_mask \n connect slots_18.io.wakeup_ports[1].bits.bypassable, issue_slots[18].wakeup_ports[1].bits.bypassable \n connect slots_18.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[18].wakeup_ports[1].bits.uop.debug_tsrc \n connect slots_18.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[18].wakeup_ports[1].bits.uop.debug_fsrc \n connect slots_18.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[18].wakeup_ports[1].bits.uop.bp_xcpt_if \n connect slots_18.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[18].wakeup_ports[1].bits.uop.bp_debug_if \n connect slots_18.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[18].wakeup_ports[1].bits.uop.xcpt_ma_if \n connect slots_18.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[18].wakeup_ports[1].bits.uop.xcpt_ae_if \n connect slots_18.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[18].wakeup_ports[1].bits.uop.xcpt_pf_if \n connect slots_18.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[18].wakeup_ports[1].bits.uop.fp_typ \n connect slots_18.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[18].wakeup_ports[1].bits.uop.fp_rm \n connect slots_18.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[18].wakeup_ports[1].bits.uop.fp_val \n connect slots_18.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[18].wakeup_ports[1].bits.uop.fcn_op \n connect slots_18.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[18].wakeup_ports[1].bits.uop.fcn_dw \n connect slots_18.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[18].wakeup_ports[1].bits.uop.frs3_en \n connect slots_18.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[18].wakeup_ports[1].bits.uop.lrs2_rtype \n connect slots_18.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[18].wakeup_ports[1].bits.uop.lrs1_rtype \n connect slots_18.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[18].wakeup_ports[1].bits.uop.dst_rtype \n connect slots_18.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[18].wakeup_ports[1].bits.uop.lrs3 \n connect slots_18.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[18].wakeup_ports[1].bits.uop.lrs2 \n connect slots_18.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[18].wakeup_ports[1].bits.uop.lrs1 \n connect slots_18.io.wakeup_ports[1].bits.uop.ldst, issue_slots[18].wakeup_ports[1].bits.uop.ldst \n connect slots_18.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[18].wakeup_ports[1].bits.uop.ldst_is_rs1 \n connect slots_18.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[18].wakeup_ports[1].bits.uop.csr_cmd \n connect slots_18.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[18].wakeup_ports[1].bits.uop.flush_on_commit \n connect slots_18.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[18].wakeup_ports[1].bits.uop.is_unique \n connect slots_18.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[18].wakeup_ports[1].bits.uop.uses_stq \n connect slots_18.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[18].wakeup_ports[1].bits.uop.uses_ldq \n connect slots_18.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[18].wakeup_ports[1].bits.uop.mem_signed \n connect slots_18.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[18].wakeup_ports[1].bits.uop.mem_size \n connect slots_18.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[18].wakeup_ports[1].bits.uop.mem_cmd \n connect slots_18.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[18].wakeup_ports[1].bits.uop.exc_cause \n connect slots_18.io.wakeup_ports[1].bits.uop.exception, issue_slots[18].wakeup_ports[1].bits.uop.exception \n connect slots_18.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[18].wakeup_ports[1].bits.uop.stale_pdst \n connect slots_18.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[18].wakeup_ports[1].bits.uop.ppred_busy \n connect slots_18.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[18].wakeup_ports[1].bits.uop.prs3_busy \n connect slots_18.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[18].wakeup_ports[1].bits.uop.prs2_busy \n connect slots_18.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[18].wakeup_ports[1].bits.uop.prs1_busy \n connect slots_18.io.wakeup_ports[1].bits.uop.ppred, issue_slots[18].wakeup_ports[1].bits.uop.ppred \n connect slots_18.io.wakeup_ports[1].bits.uop.prs3, issue_slots[18].wakeup_ports[1].bits.uop.prs3 \n connect slots_18.io.wakeup_ports[1].bits.uop.prs2, issue_slots[18].wakeup_ports[1].bits.uop.prs2 \n connect slots_18.io.wakeup_ports[1].bits.uop.prs1, issue_slots[18].wakeup_ports[1].bits.uop.prs1 \n connect slots_18.io.wakeup_ports[1].bits.uop.pdst, issue_slots[18].wakeup_ports[1].bits.uop.pdst \n connect slots_18.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[18].wakeup_ports[1].bits.uop.rxq_idx \n connect slots_18.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[18].wakeup_ports[1].bits.uop.stq_idx \n connect slots_18.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[18].wakeup_ports[1].bits.uop.ldq_idx \n connect slots_18.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[18].wakeup_ports[1].bits.uop.rob_idx \n connect slots_18.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.vec \n connect slots_18.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.wflags \n connect slots_18.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.sqrt \n connect slots_18.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.div \n connect slots_18.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.fma \n connect slots_18.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe \n connect slots_18.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.toint \n connect slots_18.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.fromint \n connect slots_18.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut \n connect slots_18.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn \n connect slots_18.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.swap23 \n connect slots_18.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.swap12 \n connect slots_18.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.ren3 \n connect slots_18.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.ren2 \n connect slots_18.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.ren1 \n connect slots_18.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.wen \n connect slots_18.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.ldst \n connect slots_18.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[18].wakeup_ports[1].bits.uop.op2_sel \n connect slots_18.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[18].wakeup_ports[1].bits.uop.op1_sel \n connect slots_18.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[18].wakeup_ports[1].bits.uop.imm_packed \n connect slots_18.io.wakeup_ports[1].bits.uop.pimm, issue_slots[18].wakeup_ports[1].bits.uop.pimm \n connect slots_18.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[18].wakeup_ports[1].bits.uop.imm_sel \n connect slots_18.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[18].wakeup_ports[1].bits.uop.imm_rename \n connect slots_18.io.wakeup_ports[1].bits.uop.taken, issue_slots[18].wakeup_ports[1].bits.uop.taken \n connect slots_18.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[18].wakeup_ports[1].bits.uop.pc_lob \n connect slots_18.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[18].wakeup_ports[1].bits.uop.edge_inst \n connect slots_18.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[18].wakeup_ports[1].bits.uop.ftq_idx \n connect slots_18.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[18].wakeup_ports[1].bits.uop.is_mov \n connect slots_18.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[18].wakeup_ports[1].bits.uop.is_rocc \n connect slots_18.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[18].wakeup_ports[1].bits.uop.is_sys_pc2epc \n connect slots_18.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[18].wakeup_ports[1].bits.uop.is_eret \n connect slots_18.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[18].wakeup_ports[1].bits.uop.is_amo \n connect slots_18.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[18].wakeup_ports[1].bits.uop.is_sfence \n connect slots_18.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[18].wakeup_ports[1].bits.uop.is_fencei \n connect slots_18.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[18].wakeup_ports[1].bits.uop.is_fence \n connect slots_18.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[18].wakeup_ports[1].bits.uop.is_sfb \n connect slots_18.io.wakeup_ports[1].bits.uop.br_type, issue_slots[18].wakeup_ports[1].bits.uop.br_type \n connect slots_18.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[18].wakeup_ports[1].bits.uop.br_tag \n connect slots_18.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[18].wakeup_ports[1].bits.uop.br_mask \n connect slots_18.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[18].wakeup_ports[1].bits.uop.dis_col_sel \n connect slots_18.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[18].wakeup_ports[1].bits.uop.iw_p3_bypass_hint \n connect slots_18.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[18].wakeup_ports[1].bits.uop.iw_p2_bypass_hint \n connect slots_18.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[18].wakeup_ports[1].bits.uop.iw_p1_bypass_hint \n connect slots_18.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[18].wakeup_ports[1].bits.uop.iw_p2_speculative_child \n connect slots_18.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[18].wakeup_ports[1].bits.uop.iw_p1_speculative_child \n connect slots_18.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[18].wakeup_ports[1].bits.uop.iw_issued_partial_dgen \n connect slots_18.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[18].wakeup_ports[1].bits.uop.iw_issued_partial_agen \n connect slots_18.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[18].wakeup_ports[1].bits.uop.iw_issued \n connect slots_18.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[18].wakeup_ports[1].bits.uop.fu_code[0] \n connect slots_18.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[18].wakeup_ports[1].bits.uop.fu_code[1] \n connect slots_18.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[18].wakeup_ports[1].bits.uop.fu_code[2] \n connect slots_18.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[18].wakeup_ports[1].bits.uop.fu_code[3] \n connect slots_18.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[18].wakeup_ports[1].bits.uop.fu_code[4] \n connect slots_18.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[18].wakeup_ports[1].bits.uop.fu_code[5] \n connect slots_18.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[18].wakeup_ports[1].bits.uop.fu_code[6] \n connect slots_18.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[18].wakeup_ports[1].bits.uop.fu_code[7] \n connect slots_18.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[18].wakeup_ports[1].bits.uop.fu_code[8] \n connect slots_18.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[18].wakeup_ports[1].bits.uop.fu_code[9] \n connect slots_18.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[18].wakeup_ports[1].bits.uop.iq_type[0] \n connect slots_18.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[18].wakeup_ports[1].bits.uop.iq_type[1] \n connect slots_18.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[18].wakeup_ports[1].bits.uop.iq_type[2] \n connect slots_18.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[18].wakeup_ports[1].bits.uop.iq_type[3] \n connect slots_18.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[18].wakeup_ports[1].bits.uop.debug_pc \n connect slots_18.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[18].wakeup_ports[1].bits.uop.is_rvc \n connect slots_18.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[18].wakeup_ports[1].bits.uop.debug_inst \n connect slots_18.io.wakeup_ports[1].bits.uop.inst, issue_slots[18].wakeup_ports[1].bits.uop.inst \n connect slots_18.io.wakeup_ports[1].valid, issue_slots[18].wakeup_ports[1].valid \n connect slots_18.io.wakeup_ports[2].bits.rebusy, issue_slots[18].wakeup_ports[2].bits.rebusy \n connect slots_18.io.wakeup_ports[2].bits.speculative_mask, issue_slots[18].wakeup_ports[2].bits.speculative_mask \n connect slots_18.io.wakeup_ports[2].bits.bypassable, issue_slots[18].wakeup_ports[2].bits.bypassable \n connect slots_18.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[18].wakeup_ports[2].bits.uop.debug_tsrc \n connect slots_18.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[18].wakeup_ports[2].bits.uop.debug_fsrc \n connect slots_18.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[18].wakeup_ports[2].bits.uop.bp_xcpt_if \n connect slots_18.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[18].wakeup_ports[2].bits.uop.bp_debug_if \n connect slots_18.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[18].wakeup_ports[2].bits.uop.xcpt_ma_if \n connect slots_18.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[18].wakeup_ports[2].bits.uop.xcpt_ae_if \n connect slots_18.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[18].wakeup_ports[2].bits.uop.xcpt_pf_if \n connect slots_18.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[18].wakeup_ports[2].bits.uop.fp_typ \n connect slots_18.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[18].wakeup_ports[2].bits.uop.fp_rm \n connect slots_18.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[18].wakeup_ports[2].bits.uop.fp_val \n connect slots_18.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[18].wakeup_ports[2].bits.uop.fcn_op \n connect slots_18.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[18].wakeup_ports[2].bits.uop.fcn_dw \n connect slots_18.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[18].wakeup_ports[2].bits.uop.frs3_en \n connect slots_18.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[18].wakeup_ports[2].bits.uop.lrs2_rtype \n connect slots_18.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[18].wakeup_ports[2].bits.uop.lrs1_rtype \n connect slots_18.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[18].wakeup_ports[2].bits.uop.dst_rtype \n connect slots_18.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[18].wakeup_ports[2].bits.uop.lrs3 \n connect slots_18.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[18].wakeup_ports[2].bits.uop.lrs2 \n connect slots_18.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[18].wakeup_ports[2].bits.uop.lrs1 \n connect slots_18.io.wakeup_ports[2].bits.uop.ldst, issue_slots[18].wakeup_ports[2].bits.uop.ldst \n connect slots_18.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[18].wakeup_ports[2].bits.uop.ldst_is_rs1 \n connect slots_18.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[18].wakeup_ports[2].bits.uop.csr_cmd \n connect slots_18.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[18].wakeup_ports[2].bits.uop.flush_on_commit \n connect slots_18.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[18].wakeup_ports[2].bits.uop.is_unique \n connect slots_18.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[18].wakeup_ports[2].bits.uop.uses_stq \n connect slots_18.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[18].wakeup_ports[2].bits.uop.uses_ldq \n connect slots_18.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[18].wakeup_ports[2].bits.uop.mem_signed \n connect slots_18.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[18].wakeup_ports[2].bits.uop.mem_size \n connect slots_18.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[18].wakeup_ports[2].bits.uop.mem_cmd \n connect slots_18.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[18].wakeup_ports[2].bits.uop.exc_cause \n connect slots_18.io.wakeup_ports[2].bits.uop.exception, issue_slots[18].wakeup_ports[2].bits.uop.exception \n connect slots_18.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[18].wakeup_ports[2].bits.uop.stale_pdst \n connect slots_18.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[18].wakeup_ports[2].bits.uop.ppred_busy \n connect slots_18.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[18].wakeup_ports[2].bits.uop.prs3_busy \n connect slots_18.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[18].wakeup_ports[2].bits.uop.prs2_busy \n connect slots_18.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[18].wakeup_ports[2].bits.uop.prs1_busy \n connect slots_18.io.wakeup_ports[2].bits.uop.ppred, issue_slots[18].wakeup_ports[2].bits.uop.ppred \n connect slots_18.io.wakeup_ports[2].bits.uop.prs3, issue_slots[18].wakeup_ports[2].bits.uop.prs3 \n connect slots_18.io.wakeup_ports[2].bits.uop.prs2, issue_slots[18].wakeup_ports[2].bits.uop.prs2 \n connect slots_18.io.wakeup_ports[2].bits.uop.prs1, issue_slots[18].wakeup_ports[2].bits.uop.prs1 \n connect slots_18.io.wakeup_ports[2].bits.uop.pdst, issue_slots[18].wakeup_ports[2].bits.uop.pdst \n connect slots_18.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[18].wakeup_ports[2].bits.uop.rxq_idx \n connect slots_18.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[18].wakeup_ports[2].bits.uop.stq_idx \n connect slots_18.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[18].wakeup_ports[2].bits.uop.ldq_idx \n connect slots_18.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[18].wakeup_ports[2].bits.uop.rob_idx \n connect slots_18.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.vec \n connect slots_18.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.wflags \n connect slots_18.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.sqrt \n connect slots_18.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.div \n connect slots_18.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.fma \n connect slots_18.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe \n connect slots_18.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.toint \n connect slots_18.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.fromint \n connect slots_18.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut \n connect slots_18.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn \n connect slots_18.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.swap23 \n connect slots_18.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.swap12 \n connect slots_18.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.ren3 \n connect slots_18.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.ren2 \n connect slots_18.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.ren1 \n connect slots_18.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.wen \n connect slots_18.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.ldst \n connect slots_18.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[18].wakeup_ports[2].bits.uop.op2_sel \n connect slots_18.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[18].wakeup_ports[2].bits.uop.op1_sel \n connect slots_18.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[18].wakeup_ports[2].bits.uop.imm_packed \n connect slots_18.io.wakeup_ports[2].bits.uop.pimm, issue_slots[18].wakeup_ports[2].bits.uop.pimm \n connect slots_18.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[18].wakeup_ports[2].bits.uop.imm_sel \n connect slots_18.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[18].wakeup_ports[2].bits.uop.imm_rename \n connect slots_18.io.wakeup_ports[2].bits.uop.taken, issue_slots[18].wakeup_ports[2].bits.uop.taken \n connect slots_18.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[18].wakeup_ports[2].bits.uop.pc_lob \n connect slots_18.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[18].wakeup_ports[2].bits.uop.edge_inst \n connect slots_18.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[18].wakeup_ports[2].bits.uop.ftq_idx \n connect slots_18.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[18].wakeup_ports[2].bits.uop.is_mov \n connect slots_18.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[18].wakeup_ports[2].bits.uop.is_rocc \n connect slots_18.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[18].wakeup_ports[2].bits.uop.is_sys_pc2epc \n connect slots_18.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[18].wakeup_ports[2].bits.uop.is_eret \n connect slots_18.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[18].wakeup_ports[2].bits.uop.is_amo \n connect slots_18.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[18].wakeup_ports[2].bits.uop.is_sfence \n connect slots_18.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[18].wakeup_ports[2].bits.uop.is_fencei \n connect slots_18.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[18].wakeup_ports[2].bits.uop.is_fence \n connect slots_18.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[18].wakeup_ports[2].bits.uop.is_sfb \n connect slots_18.io.wakeup_ports[2].bits.uop.br_type, issue_slots[18].wakeup_ports[2].bits.uop.br_type \n connect slots_18.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[18].wakeup_ports[2].bits.uop.br_tag \n connect slots_18.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[18].wakeup_ports[2].bits.uop.br_mask \n connect slots_18.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[18].wakeup_ports[2].bits.uop.dis_col_sel \n connect slots_18.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[18].wakeup_ports[2].bits.uop.iw_p3_bypass_hint \n connect slots_18.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[18].wakeup_ports[2].bits.uop.iw_p2_bypass_hint \n connect slots_18.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[18].wakeup_ports[2].bits.uop.iw_p1_bypass_hint \n connect slots_18.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[18].wakeup_ports[2].bits.uop.iw_p2_speculative_child \n connect slots_18.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[18].wakeup_ports[2].bits.uop.iw_p1_speculative_child \n connect slots_18.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[18].wakeup_ports[2].bits.uop.iw_issued_partial_dgen \n connect slots_18.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[18].wakeup_ports[2].bits.uop.iw_issued_partial_agen \n connect slots_18.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[18].wakeup_ports[2].bits.uop.iw_issued \n connect slots_18.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[18].wakeup_ports[2].bits.uop.fu_code[0] \n connect slots_18.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[18].wakeup_ports[2].bits.uop.fu_code[1] \n connect slots_18.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[18].wakeup_ports[2].bits.uop.fu_code[2] \n connect slots_18.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[18].wakeup_ports[2].bits.uop.fu_code[3] \n connect slots_18.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[18].wakeup_ports[2].bits.uop.fu_code[4] \n connect slots_18.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[18].wakeup_ports[2].bits.uop.fu_code[5] \n connect slots_18.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[18].wakeup_ports[2].bits.uop.fu_code[6] \n connect slots_18.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[18].wakeup_ports[2].bits.uop.fu_code[7] \n connect slots_18.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[18].wakeup_ports[2].bits.uop.fu_code[8] \n connect slots_18.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[18].wakeup_ports[2].bits.uop.fu_code[9] \n connect slots_18.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[18].wakeup_ports[2].bits.uop.iq_type[0] \n connect slots_18.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[18].wakeup_ports[2].bits.uop.iq_type[1] \n connect slots_18.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[18].wakeup_ports[2].bits.uop.iq_type[2] \n connect slots_18.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[18].wakeup_ports[2].bits.uop.iq_type[3] \n connect slots_18.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[18].wakeup_ports[2].bits.uop.debug_pc \n connect slots_18.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[18].wakeup_ports[2].bits.uop.is_rvc \n connect slots_18.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[18].wakeup_ports[2].bits.uop.debug_inst \n connect slots_18.io.wakeup_ports[2].bits.uop.inst, issue_slots[18].wakeup_ports[2].bits.uop.inst \n connect slots_18.io.wakeup_ports[2].valid, issue_slots[18].wakeup_ports[2].valid \n connect slots_18.io.wakeup_ports[3].bits.rebusy, issue_slots[18].wakeup_ports[3].bits.rebusy \n connect slots_18.io.wakeup_ports[3].bits.speculative_mask, issue_slots[18].wakeup_ports[3].bits.speculative_mask \n connect slots_18.io.wakeup_ports[3].bits.bypassable, issue_slots[18].wakeup_ports[3].bits.bypassable \n connect slots_18.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[18].wakeup_ports[3].bits.uop.debug_tsrc \n connect slots_18.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[18].wakeup_ports[3].bits.uop.debug_fsrc \n connect slots_18.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[18].wakeup_ports[3].bits.uop.bp_xcpt_if \n connect slots_18.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[18].wakeup_ports[3].bits.uop.bp_debug_if \n connect slots_18.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[18].wakeup_ports[3].bits.uop.xcpt_ma_if \n connect slots_18.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[18].wakeup_ports[3].bits.uop.xcpt_ae_if \n connect slots_18.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[18].wakeup_ports[3].bits.uop.xcpt_pf_if \n connect slots_18.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[18].wakeup_ports[3].bits.uop.fp_typ \n connect slots_18.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[18].wakeup_ports[3].bits.uop.fp_rm \n connect slots_18.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[18].wakeup_ports[3].bits.uop.fp_val \n connect slots_18.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[18].wakeup_ports[3].bits.uop.fcn_op \n connect slots_18.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[18].wakeup_ports[3].bits.uop.fcn_dw \n connect slots_18.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[18].wakeup_ports[3].bits.uop.frs3_en \n connect slots_18.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[18].wakeup_ports[3].bits.uop.lrs2_rtype \n connect slots_18.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[18].wakeup_ports[3].bits.uop.lrs1_rtype \n connect slots_18.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[18].wakeup_ports[3].bits.uop.dst_rtype \n connect slots_18.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[18].wakeup_ports[3].bits.uop.lrs3 \n connect slots_18.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[18].wakeup_ports[3].bits.uop.lrs2 \n connect slots_18.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[18].wakeup_ports[3].bits.uop.lrs1 \n connect slots_18.io.wakeup_ports[3].bits.uop.ldst, issue_slots[18].wakeup_ports[3].bits.uop.ldst \n connect slots_18.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[18].wakeup_ports[3].bits.uop.ldst_is_rs1 \n connect slots_18.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[18].wakeup_ports[3].bits.uop.csr_cmd \n connect slots_18.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[18].wakeup_ports[3].bits.uop.flush_on_commit \n connect slots_18.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[18].wakeup_ports[3].bits.uop.is_unique \n connect slots_18.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[18].wakeup_ports[3].bits.uop.uses_stq \n connect slots_18.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[18].wakeup_ports[3].bits.uop.uses_ldq \n connect slots_18.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[18].wakeup_ports[3].bits.uop.mem_signed \n connect slots_18.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[18].wakeup_ports[3].bits.uop.mem_size \n connect slots_18.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[18].wakeup_ports[3].bits.uop.mem_cmd \n connect slots_18.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[18].wakeup_ports[3].bits.uop.exc_cause \n connect slots_18.io.wakeup_ports[3].bits.uop.exception, issue_slots[18].wakeup_ports[3].bits.uop.exception \n connect slots_18.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[18].wakeup_ports[3].bits.uop.stale_pdst \n connect slots_18.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[18].wakeup_ports[3].bits.uop.ppred_busy \n connect slots_18.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[18].wakeup_ports[3].bits.uop.prs3_busy \n connect slots_18.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[18].wakeup_ports[3].bits.uop.prs2_busy \n connect slots_18.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[18].wakeup_ports[3].bits.uop.prs1_busy \n connect slots_18.io.wakeup_ports[3].bits.uop.ppred, issue_slots[18].wakeup_ports[3].bits.uop.ppred \n connect slots_18.io.wakeup_ports[3].bits.uop.prs3, issue_slots[18].wakeup_ports[3].bits.uop.prs3 \n connect slots_18.io.wakeup_ports[3].bits.uop.prs2, issue_slots[18].wakeup_ports[3].bits.uop.prs2 \n connect slots_18.io.wakeup_ports[3].bits.uop.prs1, issue_slots[18].wakeup_ports[3].bits.uop.prs1 \n connect slots_18.io.wakeup_ports[3].bits.uop.pdst, issue_slots[18].wakeup_ports[3].bits.uop.pdst \n connect slots_18.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[18].wakeup_ports[3].bits.uop.rxq_idx \n connect slots_18.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[18].wakeup_ports[3].bits.uop.stq_idx \n connect slots_18.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[18].wakeup_ports[3].bits.uop.ldq_idx \n connect slots_18.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[18].wakeup_ports[3].bits.uop.rob_idx \n connect slots_18.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.vec \n connect slots_18.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.wflags \n connect slots_18.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.sqrt \n connect slots_18.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.div \n connect slots_18.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.fma \n connect slots_18.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe \n connect slots_18.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.toint \n connect slots_18.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.fromint \n connect slots_18.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut \n connect slots_18.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn \n connect slots_18.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.swap23 \n connect slots_18.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.swap12 \n connect slots_18.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.ren3 \n connect slots_18.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.ren2 \n connect slots_18.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.ren1 \n connect slots_18.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.wen \n connect slots_18.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.ldst \n connect slots_18.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[18].wakeup_ports[3].bits.uop.op2_sel \n connect slots_18.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[18].wakeup_ports[3].bits.uop.op1_sel \n connect slots_18.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[18].wakeup_ports[3].bits.uop.imm_packed \n connect slots_18.io.wakeup_ports[3].bits.uop.pimm, issue_slots[18].wakeup_ports[3].bits.uop.pimm \n connect slots_18.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[18].wakeup_ports[3].bits.uop.imm_sel \n connect slots_18.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[18].wakeup_ports[3].bits.uop.imm_rename \n connect slots_18.io.wakeup_ports[3].bits.uop.taken, issue_slots[18].wakeup_ports[3].bits.uop.taken \n connect slots_18.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[18].wakeup_ports[3].bits.uop.pc_lob \n connect slots_18.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[18].wakeup_ports[3].bits.uop.edge_inst \n connect slots_18.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[18].wakeup_ports[3].bits.uop.ftq_idx \n connect slots_18.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[18].wakeup_ports[3].bits.uop.is_mov \n connect slots_18.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[18].wakeup_ports[3].bits.uop.is_rocc \n connect slots_18.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[18].wakeup_ports[3].bits.uop.is_sys_pc2epc \n connect slots_18.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[18].wakeup_ports[3].bits.uop.is_eret \n connect slots_18.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[18].wakeup_ports[3].bits.uop.is_amo \n connect slots_18.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[18].wakeup_ports[3].bits.uop.is_sfence \n connect slots_18.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[18].wakeup_ports[3].bits.uop.is_fencei \n connect slots_18.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[18].wakeup_ports[3].bits.uop.is_fence \n connect slots_18.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[18].wakeup_ports[3].bits.uop.is_sfb \n connect slots_18.io.wakeup_ports[3].bits.uop.br_type, issue_slots[18].wakeup_ports[3].bits.uop.br_type \n connect slots_18.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[18].wakeup_ports[3].bits.uop.br_tag \n connect slots_18.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[18].wakeup_ports[3].bits.uop.br_mask \n connect slots_18.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[18].wakeup_ports[3].bits.uop.dis_col_sel \n connect slots_18.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[18].wakeup_ports[3].bits.uop.iw_p3_bypass_hint \n connect slots_18.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[18].wakeup_ports[3].bits.uop.iw_p2_bypass_hint \n connect slots_18.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[18].wakeup_ports[3].bits.uop.iw_p1_bypass_hint \n connect slots_18.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[18].wakeup_ports[3].bits.uop.iw_p2_speculative_child \n connect slots_18.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[18].wakeup_ports[3].bits.uop.iw_p1_speculative_child \n connect slots_18.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[18].wakeup_ports[3].bits.uop.iw_issued_partial_dgen \n connect slots_18.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[18].wakeup_ports[3].bits.uop.iw_issued_partial_agen \n connect slots_18.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[18].wakeup_ports[3].bits.uop.iw_issued \n connect slots_18.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[18].wakeup_ports[3].bits.uop.fu_code[0] \n connect slots_18.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[18].wakeup_ports[3].bits.uop.fu_code[1] \n connect slots_18.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[18].wakeup_ports[3].bits.uop.fu_code[2] \n connect slots_18.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[18].wakeup_ports[3].bits.uop.fu_code[3] \n connect slots_18.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[18].wakeup_ports[3].bits.uop.fu_code[4] \n connect slots_18.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[18].wakeup_ports[3].bits.uop.fu_code[5] \n connect slots_18.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[18].wakeup_ports[3].bits.uop.fu_code[6] \n connect slots_18.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[18].wakeup_ports[3].bits.uop.fu_code[7] \n connect slots_18.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[18].wakeup_ports[3].bits.uop.fu_code[8] \n connect slots_18.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[18].wakeup_ports[3].bits.uop.fu_code[9] \n connect slots_18.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[18].wakeup_ports[3].bits.uop.iq_type[0] \n connect slots_18.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[18].wakeup_ports[3].bits.uop.iq_type[1] \n connect slots_18.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[18].wakeup_ports[3].bits.uop.iq_type[2] \n connect slots_18.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[18].wakeup_ports[3].bits.uop.iq_type[3] \n connect slots_18.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[18].wakeup_ports[3].bits.uop.debug_pc \n connect slots_18.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[18].wakeup_ports[3].bits.uop.is_rvc \n connect slots_18.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[18].wakeup_ports[3].bits.uop.debug_inst \n connect slots_18.io.wakeup_ports[3].bits.uop.inst, issue_slots[18].wakeup_ports[3].bits.uop.inst \n connect slots_18.io.wakeup_ports[3].valid, issue_slots[18].wakeup_ports[3].valid \n connect slots_18.io.squash_grant, issue_slots[18].squash_grant \n connect slots_18.io.clear, issue_slots[18].clear \n connect slots_18.io.kill, issue_slots[18].kill \n connect slots_18.io.brupdate.b2.target_offset, issue_slots[18].brupdate.b2.target_offset \n connect slots_18.io.brupdate.b2.jalr_target, issue_slots[18].brupdate.b2.jalr_target \n connect slots_18.io.brupdate.b2.pc_sel, issue_slots[18].brupdate.b2.pc_sel \n connect slots_18.io.brupdate.b2.cfi_type, issue_slots[18].brupdate.b2.cfi_type \n connect slots_18.io.brupdate.b2.taken, issue_slots[18].brupdate.b2.taken \n connect slots_18.io.brupdate.b2.mispredict, issue_slots[18].brupdate.b2.mispredict \n connect slots_18.io.brupdate.b2.uop.debug_tsrc, issue_slots[18].brupdate.b2.uop.debug_tsrc \n connect slots_18.io.brupdate.b2.uop.debug_fsrc, issue_slots[18].brupdate.b2.uop.debug_fsrc \n connect slots_18.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[18].brupdate.b2.uop.bp_xcpt_if \n connect slots_18.io.brupdate.b2.uop.bp_debug_if, issue_slots[18].brupdate.b2.uop.bp_debug_if \n connect slots_18.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[18].brupdate.b2.uop.xcpt_ma_if \n connect slots_18.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[18].brupdate.b2.uop.xcpt_ae_if \n connect slots_18.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[18].brupdate.b2.uop.xcpt_pf_if \n connect slots_18.io.brupdate.b2.uop.fp_typ, issue_slots[18].brupdate.b2.uop.fp_typ \n connect slots_18.io.brupdate.b2.uop.fp_rm, issue_slots[18].brupdate.b2.uop.fp_rm \n connect slots_18.io.brupdate.b2.uop.fp_val, issue_slots[18].brupdate.b2.uop.fp_val \n connect slots_18.io.brupdate.b2.uop.fcn_op, issue_slots[18].brupdate.b2.uop.fcn_op \n connect slots_18.io.brupdate.b2.uop.fcn_dw, issue_slots[18].brupdate.b2.uop.fcn_dw \n connect slots_18.io.brupdate.b2.uop.frs3_en, issue_slots[18].brupdate.b2.uop.frs3_en \n connect slots_18.io.brupdate.b2.uop.lrs2_rtype, issue_slots[18].brupdate.b2.uop.lrs2_rtype \n connect slots_18.io.brupdate.b2.uop.lrs1_rtype, issue_slots[18].brupdate.b2.uop.lrs1_rtype \n connect slots_18.io.brupdate.b2.uop.dst_rtype, issue_slots[18].brupdate.b2.uop.dst_rtype \n connect slots_18.io.brupdate.b2.uop.lrs3, issue_slots[18].brupdate.b2.uop.lrs3 \n connect slots_18.io.brupdate.b2.uop.lrs2, issue_slots[18].brupdate.b2.uop.lrs2 \n connect slots_18.io.brupdate.b2.uop.lrs1, issue_slots[18].brupdate.b2.uop.lrs1 \n connect slots_18.io.brupdate.b2.uop.ldst, issue_slots[18].brupdate.b2.uop.ldst \n connect slots_18.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[18].brupdate.b2.uop.ldst_is_rs1 \n connect slots_18.io.brupdate.b2.uop.csr_cmd, issue_slots[18].brupdate.b2.uop.csr_cmd \n connect slots_18.io.brupdate.b2.uop.flush_on_commit, issue_slots[18].brupdate.b2.uop.flush_on_commit \n connect slots_18.io.brupdate.b2.uop.is_unique, issue_slots[18].brupdate.b2.uop.is_unique \n connect slots_18.io.brupdate.b2.uop.uses_stq, issue_slots[18].brupdate.b2.uop.uses_stq \n connect slots_18.io.brupdate.b2.uop.uses_ldq, issue_slots[18].brupdate.b2.uop.uses_ldq \n connect slots_18.io.brupdate.b2.uop.mem_signed, issue_slots[18].brupdate.b2.uop.mem_signed \n connect slots_18.io.brupdate.b2.uop.mem_size, issue_slots[18].brupdate.b2.uop.mem_size \n connect slots_18.io.brupdate.b2.uop.mem_cmd, issue_slots[18].brupdate.b2.uop.mem_cmd \n connect slots_18.io.brupdate.b2.uop.exc_cause, issue_slots[18].brupdate.b2.uop.exc_cause \n connect slots_18.io.brupdate.b2.uop.exception, issue_slots[18].brupdate.b2.uop.exception \n connect slots_18.io.brupdate.b2.uop.stale_pdst, issue_slots[18].brupdate.b2.uop.stale_pdst \n connect slots_18.io.brupdate.b2.uop.ppred_busy, issue_slots[18].brupdate.b2.uop.ppred_busy \n connect slots_18.io.brupdate.b2.uop.prs3_busy, issue_slots[18].brupdate.b2.uop.prs3_busy \n connect slots_18.io.brupdate.b2.uop.prs2_busy, issue_slots[18].brupdate.b2.uop.prs2_busy \n connect slots_18.io.brupdate.b2.uop.prs1_busy, issue_slots[18].brupdate.b2.uop.prs1_busy \n connect slots_18.io.brupdate.b2.uop.ppred, issue_slots[18].brupdate.b2.uop.ppred \n connect slots_18.io.brupdate.b2.uop.prs3, issue_slots[18].brupdate.b2.uop.prs3 \n connect slots_18.io.brupdate.b2.uop.prs2, issue_slots[18].brupdate.b2.uop.prs2 \n connect slots_18.io.brupdate.b2.uop.prs1, issue_slots[18].brupdate.b2.uop.prs1 \n connect slots_18.io.brupdate.b2.uop.pdst, issue_slots[18].brupdate.b2.uop.pdst \n connect slots_18.io.brupdate.b2.uop.rxq_idx, issue_slots[18].brupdate.b2.uop.rxq_idx \n connect slots_18.io.brupdate.b2.uop.stq_idx, issue_slots[18].brupdate.b2.uop.stq_idx \n connect slots_18.io.brupdate.b2.uop.ldq_idx, issue_slots[18].brupdate.b2.uop.ldq_idx \n connect slots_18.io.brupdate.b2.uop.rob_idx, issue_slots[18].brupdate.b2.uop.rob_idx \n connect slots_18.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[18].brupdate.b2.uop.fp_ctrl.vec \n connect slots_18.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[18].brupdate.b2.uop.fp_ctrl.wflags \n connect slots_18.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[18].brupdate.b2.uop.fp_ctrl.sqrt \n connect slots_18.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[18].brupdate.b2.uop.fp_ctrl.div \n connect slots_18.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[18].brupdate.b2.uop.fp_ctrl.fma \n connect slots_18.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[18].brupdate.b2.uop.fp_ctrl.fastpipe \n connect slots_18.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[18].brupdate.b2.uop.fp_ctrl.toint \n connect slots_18.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[18].brupdate.b2.uop.fp_ctrl.fromint \n connect slots_18.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[18].brupdate.b2.uop.fp_ctrl.typeTagOut \n connect slots_18.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[18].brupdate.b2.uop.fp_ctrl.typeTagIn \n connect slots_18.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[18].brupdate.b2.uop.fp_ctrl.swap23 \n connect slots_18.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[18].brupdate.b2.uop.fp_ctrl.swap12 \n connect slots_18.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[18].brupdate.b2.uop.fp_ctrl.ren3 \n connect slots_18.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[18].brupdate.b2.uop.fp_ctrl.ren2 \n connect slots_18.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[18].brupdate.b2.uop.fp_ctrl.ren1 \n connect slots_18.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[18].brupdate.b2.uop.fp_ctrl.wen \n connect slots_18.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[18].brupdate.b2.uop.fp_ctrl.ldst \n connect slots_18.io.brupdate.b2.uop.op2_sel, issue_slots[18].brupdate.b2.uop.op2_sel \n connect slots_18.io.brupdate.b2.uop.op1_sel, issue_slots[18].brupdate.b2.uop.op1_sel \n connect slots_18.io.brupdate.b2.uop.imm_packed, issue_slots[18].brupdate.b2.uop.imm_packed \n connect slots_18.io.brupdate.b2.uop.pimm, issue_slots[18].brupdate.b2.uop.pimm \n connect slots_18.io.brupdate.b2.uop.imm_sel, issue_slots[18].brupdate.b2.uop.imm_sel \n connect slots_18.io.brupdate.b2.uop.imm_rename, issue_slots[18].brupdate.b2.uop.imm_rename \n connect slots_18.io.brupdate.b2.uop.taken, issue_slots[18].brupdate.b2.uop.taken \n connect slots_18.io.brupdate.b2.uop.pc_lob, issue_slots[18].brupdate.b2.uop.pc_lob \n connect slots_18.io.brupdate.b2.uop.edge_inst, issue_slots[18].brupdate.b2.uop.edge_inst \n connect slots_18.io.brupdate.b2.uop.ftq_idx, issue_slots[18].brupdate.b2.uop.ftq_idx \n connect slots_18.io.brupdate.b2.uop.is_mov, issue_slots[18].brupdate.b2.uop.is_mov \n connect slots_18.io.brupdate.b2.uop.is_rocc, issue_slots[18].brupdate.b2.uop.is_rocc \n connect slots_18.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[18].brupdate.b2.uop.is_sys_pc2epc \n connect slots_18.io.brupdate.b2.uop.is_eret, issue_slots[18].brupdate.b2.uop.is_eret \n connect slots_18.io.brupdate.b2.uop.is_amo, issue_slots[18].brupdate.b2.uop.is_amo \n connect slots_18.io.brupdate.b2.uop.is_sfence, issue_slots[18].brupdate.b2.uop.is_sfence \n connect slots_18.io.brupdate.b2.uop.is_fencei, issue_slots[18].brupdate.b2.uop.is_fencei \n connect slots_18.io.brupdate.b2.uop.is_fence, issue_slots[18].brupdate.b2.uop.is_fence \n connect slots_18.io.brupdate.b2.uop.is_sfb, issue_slots[18].brupdate.b2.uop.is_sfb \n connect slots_18.io.brupdate.b2.uop.br_type, issue_slots[18].brupdate.b2.uop.br_type \n connect slots_18.io.brupdate.b2.uop.br_tag, issue_slots[18].brupdate.b2.uop.br_tag \n connect slots_18.io.brupdate.b2.uop.br_mask, issue_slots[18].brupdate.b2.uop.br_mask \n connect slots_18.io.brupdate.b2.uop.dis_col_sel, issue_slots[18].brupdate.b2.uop.dis_col_sel \n connect slots_18.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[18].brupdate.b2.uop.iw_p3_bypass_hint \n connect slots_18.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[18].brupdate.b2.uop.iw_p2_bypass_hint \n connect slots_18.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[18].brupdate.b2.uop.iw_p1_bypass_hint \n connect slots_18.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[18].brupdate.b2.uop.iw_p2_speculative_child \n connect slots_18.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[18].brupdate.b2.uop.iw_p1_speculative_child \n connect slots_18.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[18].brupdate.b2.uop.iw_issued_partial_dgen \n connect slots_18.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[18].brupdate.b2.uop.iw_issued_partial_agen \n connect slots_18.io.brupdate.b2.uop.iw_issued, issue_slots[18].brupdate.b2.uop.iw_issued \n connect slots_18.io.brupdate.b2.uop.fu_code[0], issue_slots[18].brupdate.b2.uop.fu_code[0] \n connect slots_18.io.brupdate.b2.uop.fu_code[1], issue_slots[18].brupdate.b2.uop.fu_code[1] \n connect slots_18.io.brupdate.b2.uop.fu_code[2], issue_slots[18].brupdate.b2.uop.fu_code[2] \n connect slots_18.io.brupdate.b2.uop.fu_code[3], issue_slots[18].brupdate.b2.uop.fu_code[3] \n connect slots_18.io.brupdate.b2.uop.fu_code[4], issue_slots[18].brupdate.b2.uop.fu_code[4] \n connect slots_18.io.brupdate.b2.uop.fu_code[5], issue_slots[18].brupdate.b2.uop.fu_code[5] \n connect slots_18.io.brupdate.b2.uop.fu_code[6], issue_slots[18].brupdate.b2.uop.fu_code[6] \n connect slots_18.io.brupdate.b2.uop.fu_code[7], issue_slots[18].brupdate.b2.uop.fu_code[7] \n connect slots_18.io.brupdate.b2.uop.fu_code[8], issue_slots[18].brupdate.b2.uop.fu_code[8] \n connect slots_18.io.brupdate.b2.uop.fu_code[9], issue_slots[18].brupdate.b2.uop.fu_code[9] \n connect slots_18.io.brupdate.b2.uop.iq_type[0], issue_slots[18].brupdate.b2.uop.iq_type[0] \n connect slots_18.io.brupdate.b2.uop.iq_type[1], issue_slots[18].brupdate.b2.uop.iq_type[1] \n connect slots_18.io.brupdate.b2.uop.iq_type[2], issue_slots[18].brupdate.b2.uop.iq_type[2] \n connect slots_18.io.brupdate.b2.uop.iq_type[3], issue_slots[18].brupdate.b2.uop.iq_type[3] \n connect slots_18.io.brupdate.b2.uop.debug_pc, issue_slots[18].brupdate.b2.uop.debug_pc \n connect slots_18.io.brupdate.b2.uop.is_rvc, issue_slots[18].brupdate.b2.uop.is_rvc \n connect slots_18.io.brupdate.b2.uop.debug_inst, issue_slots[18].brupdate.b2.uop.debug_inst \n connect slots_18.io.brupdate.b2.uop.inst, issue_slots[18].brupdate.b2.uop.inst \n connect slots_18.io.brupdate.b1.mispredict_mask, issue_slots[18].brupdate.b1.mispredict_mask \n connect slots_18.io.brupdate.b1.resolve_mask, issue_slots[18].brupdate.b1.resolve_mask \n connect issue_slots[18].out_uop.debug_tsrc, slots_18.io.out_uop.debug_tsrc \n connect issue_slots[18].out_uop.debug_fsrc, slots_18.io.out_uop.debug_fsrc \n connect issue_slots[18].out_uop.bp_xcpt_if, slots_18.io.out_uop.bp_xcpt_if \n connect issue_slots[18].out_uop.bp_debug_if, slots_18.io.out_uop.bp_debug_if \n connect issue_slots[18].out_uop.xcpt_ma_if, slots_18.io.out_uop.xcpt_ma_if \n connect issue_slots[18].out_uop.xcpt_ae_if, slots_18.io.out_uop.xcpt_ae_if \n connect issue_slots[18].out_uop.xcpt_pf_if, slots_18.io.out_uop.xcpt_pf_if \n connect issue_slots[18].out_uop.fp_typ, slots_18.io.out_uop.fp_typ \n connect issue_slots[18].out_uop.fp_rm, slots_18.io.out_uop.fp_rm \n connect issue_slots[18].out_uop.fp_val, slots_18.io.out_uop.fp_val \n connect issue_slots[18].out_uop.fcn_op, slots_18.io.out_uop.fcn_op \n connect issue_slots[18].out_uop.fcn_dw, slots_18.io.out_uop.fcn_dw \n connect issue_slots[18].out_uop.frs3_en, slots_18.io.out_uop.frs3_en \n connect issue_slots[18].out_uop.lrs2_rtype, slots_18.io.out_uop.lrs2_rtype \n connect issue_slots[18].out_uop.lrs1_rtype, slots_18.io.out_uop.lrs1_rtype \n connect issue_slots[18].out_uop.dst_rtype, slots_18.io.out_uop.dst_rtype \n connect issue_slots[18].out_uop.lrs3, slots_18.io.out_uop.lrs3 \n connect issue_slots[18].out_uop.lrs2, slots_18.io.out_uop.lrs2 \n connect issue_slots[18].out_uop.lrs1, slots_18.io.out_uop.lrs1 \n connect issue_slots[18].out_uop.ldst, slots_18.io.out_uop.ldst \n connect issue_slots[18].out_uop.ldst_is_rs1, slots_18.io.out_uop.ldst_is_rs1 \n connect issue_slots[18].out_uop.csr_cmd, slots_18.io.out_uop.csr_cmd \n connect issue_slots[18].out_uop.flush_on_commit, slots_18.io.out_uop.flush_on_commit \n connect issue_slots[18].out_uop.is_unique, slots_18.io.out_uop.is_unique \n connect issue_slots[18].out_uop.uses_stq, slots_18.io.out_uop.uses_stq \n connect issue_slots[18].out_uop.uses_ldq, slots_18.io.out_uop.uses_ldq \n connect issue_slots[18].out_uop.mem_signed, slots_18.io.out_uop.mem_signed \n connect issue_slots[18].out_uop.mem_size, slots_18.io.out_uop.mem_size \n connect issue_slots[18].out_uop.mem_cmd, slots_18.io.out_uop.mem_cmd \n connect issue_slots[18].out_uop.exc_cause, slots_18.io.out_uop.exc_cause \n connect issue_slots[18].out_uop.exception, slots_18.io.out_uop.exception \n connect issue_slots[18].out_uop.stale_pdst, slots_18.io.out_uop.stale_pdst \n connect issue_slots[18].out_uop.ppred_busy, slots_18.io.out_uop.ppred_busy \n connect issue_slots[18].out_uop.prs3_busy, slots_18.io.out_uop.prs3_busy \n connect issue_slots[18].out_uop.prs2_busy, slots_18.io.out_uop.prs2_busy \n connect issue_slots[18].out_uop.prs1_busy, slots_18.io.out_uop.prs1_busy \n connect issue_slots[18].out_uop.ppred, slots_18.io.out_uop.ppred \n connect issue_slots[18].out_uop.prs3, slots_18.io.out_uop.prs3 \n connect issue_slots[18].out_uop.prs2, slots_18.io.out_uop.prs2 \n connect issue_slots[18].out_uop.prs1, slots_18.io.out_uop.prs1 \n connect issue_slots[18].out_uop.pdst, slots_18.io.out_uop.pdst \n connect issue_slots[18].out_uop.rxq_idx, slots_18.io.out_uop.rxq_idx \n connect issue_slots[18].out_uop.stq_idx, slots_18.io.out_uop.stq_idx \n connect issue_slots[18].out_uop.ldq_idx, slots_18.io.out_uop.ldq_idx \n connect issue_slots[18].out_uop.rob_idx, slots_18.io.out_uop.rob_idx \n connect issue_slots[18].out_uop.fp_ctrl.vec, slots_18.io.out_uop.fp_ctrl.vec \n connect issue_slots[18].out_uop.fp_ctrl.wflags, slots_18.io.out_uop.fp_ctrl.wflags \n connect issue_slots[18].out_uop.fp_ctrl.sqrt, slots_18.io.out_uop.fp_ctrl.sqrt \n connect issue_slots[18].out_uop.fp_ctrl.div, slots_18.io.out_uop.fp_ctrl.div \n connect issue_slots[18].out_uop.fp_ctrl.fma, slots_18.io.out_uop.fp_ctrl.fma \n connect issue_slots[18].out_uop.fp_ctrl.fastpipe, slots_18.io.out_uop.fp_ctrl.fastpipe \n connect issue_slots[18].out_uop.fp_ctrl.toint, slots_18.io.out_uop.fp_ctrl.toint \n connect issue_slots[18].out_uop.fp_ctrl.fromint, slots_18.io.out_uop.fp_ctrl.fromint \n connect issue_slots[18].out_uop.fp_ctrl.typeTagOut, slots_18.io.out_uop.fp_ctrl.typeTagOut \n connect issue_slots[18].out_uop.fp_ctrl.typeTagIn, slots_18.io.out_uop.fp_ctrl.typeTagIn \n connect issue_slots[18].out_uop.fp_ctrl.swap23, slots_18.io.out_uop.fp_ctrl.swap23 \n connect issue_slots[18].out_uop.fp_ctrl.swap12, slots_18.io.out_uop.fp_ctrl.swap12 \n connect issue_slots[18].out_uop.fp_ctrl.ren3, slots_18.io.out_uop.fp_ctrl.ren3 \n connect issue_slots[18].out_uop.fp_ctrl.ren2, slots_18.io.out_uop.fp_ctrl.ren2 \n connect issue_slots[18].out_uop.fp_ctrl.ren1, slots_18.io.out_uop.fp_ctrl.ren1 \n connect issue_slots[18].out_uop.fp_ctrl.wen, slots_18.io.out_uop.fp_ctrl.wen \n connect issue_slots[18].out_uop.fp_ctrl.ldst, slots_18.io.out_uop.fp_ctrl.ldst \n connect issue_slots[18].out_uop.op2_sel, slots_18.io.out_uop.op2_sel \n connect issue_slots[18].out_uop.op1_sel, slots_18.io.out_uop.op1_sel \n connect issue_slots[18].out_uop.imm_packed, slots_18.io.out_uop.imm_packed \n connect issue_slots[18].out_uop.pimm, slots_18.io.out_uop.pimm \n connect issue_slots[18].out_uop.imm_sel, slots_18.io.out_uop.imm_sel \n connect issue_slots[18].out_uop.imm_rename, slots_18.io.out_uop.imm_rename \n connect issue_slots[18].out_uop.taken, slots_18.io.out_uop.taken \n connect issue_slots[18].out_uop.pc_lob, slots_18.io.out_uop.pc_lob \n connect issue_slots[18].out_uop.edge_inst, slots_18.io.out_uop.edge_inst \n connect issue_slots[18].out_uop.ftq_idx, slots_18.io.out_uop.ftq_idx \n connect issue_slots[18].out_uop.is_mov, slots_18.io.out_uop.is_mov \n connect issue_slots[18].out_uop.is_rocc, slots_18.io.out_uop.is_rocc \n connect issue_slots[18].out_uop.is_sys_pc2epc, slots_18.io.out_uop.is_sys_pc2epc \n connect issue_slots[18].out_uop.is_eret, slots_18.io.out_uop.is_eret \n connect issue_slots[18].out_uop.is_amo, slots_18.io.out_uop.is_amo \n connect issue_slots[18].out_uop.is_sfence, slots_18.io.out_uop.is_sfence \n connect issue_slots[18].out_uop.is_fencei, slots_18.io.out_uop.is_fencei \n connect issue_slots[18].out_uop.is_fence, slots_18.io.out_uop.is_fence \n connect issue_slots[18].out_uop.is_sfb, slots_18.io.out_uop.is_sfb \n connect issue_slots[18].out_uop.br_type, slots_18.io.out_uop.br_type \n connect issue_slots[18].out_uop.br_tag, slots_18.io.out_uop.br_tag \n connect issue_slots[18].out_uop.br_mask, slots_18.io.out_uop.br_mask \n connect issue_slots[18].out_uop.dis_col_sel, slots_18.io.out_uop.dis_col_sel \n connect issue_slots[18].out_uop.iw_p3_bypass_hint, slots_18.io.out_uop.iw_p3_bypass_hint \n connect issue_slots[18].out_uop.iw_p2_bypass_hint, slots_18.io.out_uop.iw_p2_bypass_hint \n connect issue_slots[18].out_uop.iw_p1_bypass_hint, slots_18.io.out_uop.iw_p1_bypass_hint \n connect issue_slots[18].out_uop.iw_p2_speculative_child, slots_18.io.out_uop.iw_p2_speculative_child \n connect issue_slots[18].out_uop.iw_p1_speculative_child, slots_18.io.out_uop.iw_p1_speculative_child \n connect issue_slots[18].out_uop.iw_issued_partial_dgen, slots_18.io.out_uop.iw_issued_partial_dgen \n connect issue_slots[18].out_uop.iw_issued_partial_agen, slots_18.io.out_uop.iw_issued_partial_agen \n connect issue_slots[18].out_uop.iw_issued, slots_18.io.out_uop.iw_issued \n connect issue_slots[18].out_uop.fu_code[0], slots_18.io.out_uop.fu_code[0] \n connect issue_slots[18].out_uop.fu_code[1], slots_18.io.out_uop.fu_code[1] \n connect issue_slots[18].out_uop.fu_code[2], slots_18.io.out_uop.fu_code[2] \n connect issue_slots[18].out_uop.fu_code[3], slots_18.io.out_uop.fu_code[3] \n connect issue_slots[18].out_uop.fu_code[4], slots_18.io.out_uop.fu_code[4] \n connect issue_slots[18].out_uop.fu_code[5], slots_18.io.out_uop.fu_code[5] \n connect issue_slots[18].out_uop.fu_code[6], slots_18.io.out_uop.fu_code[6] \n connect issue_slots[18].out_uop.fu_code[7], slots_18.io.out_uop.fu_code[7] \n connect issue_slots[18].out_uop.fu_code[8], slots_18.io.out_uop.fu_code[8] \n connect issue_slots[18].out_uop.fu_code[9], slots_18.io.out_uop.fu_code[9] \n connect issue_slots[18].out_uop.iq_type[0], slots_18.io.out_uop.iq_type[0] \n connect issue_slots[18].out_uop.iq_type[1], slots_18.io.out_uop.iq_type[1] \n connect issue_slots[18].out_uop.iq_type[2], slots_18.io.out_uop.iq_type[2] \n connect issue_slots[18].out_uop.iq_type[3], slots_18.io.out_uop.iq_type[3] \n connect issue_slots[18].out_uop.debug_pc, slots_18.io.out_uop.debug_pc \n connect issue_slots[18].out_uop.is_rvc, slots_18.io.out_uop.is_rvc \n connect issue_slots[18].out_uop.debug_inst, slots_18.io.out_uop.debug_inst \n connect issue_slots[18].out_uop.inst, slots_18.io.out_uop.inst \n connect slots_18.io.in_uop.bits.debug_tsrc, issue_slots[18].in_uop.bits.debug_tsrc \n connect slots_18.io.in_uop.bits.debug_fsrc, issue_slots[18].in_uop.bits.debug_fsrc \n connect slots_18.io.in_uop.bits.bp_xcpt_if, issue_slots[18].in_uop.bits.bp_xcpt_if \n connect slots_18.io.in_uop.bits.bp_debug_if, issue_slots[18].in_uop.bits.bp_debug_if \n connect slots_18.io.in_uop.bits.xcpt_ma_if, issue_slots[18].in_uop.bits.xcpt_ma_if \n connect slots_18.io.in_uop.bits.xcpt_ae_if, issue_slots[18].in_uop.bits.xcpt_ae_if \n connect slots_18.io.in_uop.bits.xcpt_pf_if, issue_slots[18].in_uop.bits.xcpt_pf_if \n connect slots_18.io.in_uop.bits.fp_typ, issue_slots[18].in_uop.bits.fp_typ \n connect slots_18.io.in_uop.bits.fp_rm, issue_slots[18].in_uop.bits.fp_rm \n connect slots_18.io.in_uop.bits.fp_val, issue_slots[18].in_uop.bits.fp_val \n connect slots_18.io.in_uop.bits.fcn_op, issue_slots[18].in_uop.bits.fcn_op \n connect slots_18.io.in_uop.bits.fcn_dw, issue_slots[18].in_uop.bits.fcn_dw \n connect slots_18.io.in_uop.bits.frs3_en, issue_slots[18].in_uop.bits.frs3_en \n connect slots_18.io.in_uop.bits.lrs2_rtype, issue_slots[18].in_uop.bits.lrs2_rtype \n connect slots_18.io.in_uop.bits.lrs1_rtype, issue_slots[18].in_uop.bits.lrs1_rtype \n connect slots_18.io.in_uop.bits.dst_rtype, issue_slots[18].in_uop.bits.dst_rtype \n connect slots_18.io.in_uop.bits.lrs3, issue_slots[18].in_uop.bits.lrs3 \n connect slots_18.io.in_uop.bits.lrs2, issue_slots[18].in_uop.bits.lrs2 \n connect slots_18.io.in_uop.bits.lrs1, issue_slots[18].in_uop.bits.lrs1 \n connect slots_18.io.in_uop.bits.ldst, issue_slots[18].in_uop.bits.ldst \n connect slots_18.io.in_uop.bits.ldst_is_rs1, issue_slots[18].in_uop.bits.ldst_is_rs1 \n connect slots_18.io.in_uop.bits.csr_cmd, issue_slots[18].in_uop.bits.csr_cmd \n connect slots_18.io.in_uop.bits.flush_on_commit, issue_slots[18].in_uop.bits.flush_on_commit \n connect slots_18.io.in_uop.bits.is_unique, issue_slots[18].in_uop.bits.is_unique \n connect slots_18.io.in_uop.bits.uses_stq, issue_slots[18].in_uop.bits.uses_stq \n connect slots_18.io.in_uop.bits.uses_ldq, issue_slots[18].in_uop.bits.uses_ldq \n connect slots_18.io.in_uop.bits.mem_signed, issue_slots[18].in_uop.bits.mem_signed \n connect slots_18.io.in_uop.bits.mem_size, issue_slots[18].in_uop.bits.mem_size \n connect slots_18.io.in_uop.bits.mem_cmd, issue_slots[18].in_uop.bits.mem_cmd \n connect slots_18.io.in_uop.bits.exc_cause, issue_slots[18].in_uop.bits.exc_cause \n connect slots_18.io.in_uop.bits.exception, issue_slots[18].in_uop.bits.exception \n connect slots_18.io.in_uop.bits.stale_pdst, issue_slots[18].in_uop.bits.stale_pdst \n connect slots_18.io.in_uop.bits.ppred_busy, issue_slots[18].in_uop.bits.ppred_busy \n connect slots_18.io.in_uop.bits.prs3_busy, issue_slots[18].in_uop.bits.prs3_busy \n connect slots_18.io.in_uop.bits.prs2_busy, issue_slots[18].in_uop.bits.prs2_busy \n connect slots_18.io.in_uop.bits.prs1_busy, issue_slots[18].in_uop.bits.prs1_busy \n connect slots_18.io.in_uop.bits.ppred, issue_slots[18].in_uop.bits.ppred \n connect slots_18.io.in_uop.bits.prs3, issue_slots[18].in_uop.bits.prs3 \n connect slots_18.io.in_uop.bits.prs2, issue_slots[18].in_uop.bits.prs2 \n connect slots_18.io.in_uop.bits.prs1, issue_slots[18].in_uop.bits.prs1 \n connect slots_18.io.in_uop.bits.pdst, issue_slots[18].in_uop.bits.pdst \n connect slots_18.io.in_uop.bits.rxq_idx, issue_slots[18].in_uop.bits.rxq_idx \n connect slots_18.io.in_uop.bits.stq_idx, issue_slots[18].in_uop.bits.stq_idx \n connect slots_18.io.in_uop.bits.ldq_idx, issue_slots[18].in_uop.bits.ldq_idx \n connect slots_18.io.in_uop.bits.rob_idx, issue_slots[18].in_uop.bits.rob_idx \n connect slots_18.io.in_uop.bits.fp_ctrl.vec, issue_slots[18].in_uop.bits.fp_ctrl.vec \n connect slots_18.io.in_uop.bits.fp_ctrl.wflags, issue_slots[18].in_uop.bits.fp_ctrl.wflags \n connect slots_18.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[18].in_uop.bits.fp_ctrl.sqrt \n connect slots_18.io.in_uop.bits.fp_ctrl.div, issue_slots[18].in_uop.bits.fp_ctrl.div \n connect slots_18.io.in_uop.bits.fp_ctrl.fma, issue_slots[18].in_uop.bits.fp_ctrl.fma \n connect slots_18.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[18].in_uop.bits.fp_ctrl.fastpipe \n connect slots_18.io.in_uop.bits.fp_ctrl.toint, issue_slots[18].in_uop.bits.fp_ctrl.toint \n connect slots_18.io.in_uop.bits.fp_ctrl.fromint, issue_slots[18].in_uop.bits.fp_ctrl.fromint \n connect slots_18.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[18].in_uop.bits.fp_ctrl.typeTagOut \n connect slots_18.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[18].in_uop.bits.fp_ctrl.typeTagIn \n connect slots_18.io.in_uop.bits.fp_ctrl.swap23, issue_slots[18].in_uop.bits.fp_ctrl.swap23 \n connect slots_18.io.in_uop.bits.fp_ctrl.swap12, issue_slots[18].in_uop.bits.fp_ctrl.swap12 \n connect slots_18.io.in_uop.bits.fp_ctrl.ren3, issue_slots[18].in_uop.bits.fp_ctrl.ren3 \n connect slots_18.io.in_uop.bits.fp_ctrl.ren2, issue_slots[18].in_uop.bits.fp_ctrl.ren2 \n connect slots_18.io.in_uop.bits.fp_ctrl.ren1, issue_slots[18].in_uop.bits.fp_ctrl.ren1 \n connect slots_18.io.in_uop.bits.fp_ctrl.wen, issue_slots[18].in_uop.bits.fp_ctrl.wen \n connect slots_18.io.in_uop.bits.fp_ctrl.ldst, issue_slots[18].in_uop.bits.fp_ctrl.ldst \n connect slots_18.io.in_uop.bits.op2_sel, issue_slots[18].in_uop.bits.op2_sel \n connect slots_18.io.in_uop.bits.op1_sel, issue_slots[18].in_uop.bits.op1_sel \n connect slots_18.io.in_uop.bits.imm_packed, issue_slots[18].in_uop.bits.imm_packed \n connect slots_18.io.in_uop.bits.pimm, issue_slots[18].in_uop.bits.pimm \n connect slots_18.io.in_uop.bits.imm_sel, issue_slots[18].in_uop.bits.imm_sel \n connect slots_18.io.in_uop.bits.imm_rename, issue_slots[18].in_uop.bits.imm_rename \n connect slots_18.io.in_uop.bits.taken, issue_slots[18].in_uop.bits.taken \n connect slots_18.io.in_uop.bits.pc_lob, issue_slots[18].in_uop.bits.pc_lob \n connect slots_18.io.in_uop.bits.edge_inst, issue_slots[18].in_uop.bits.edge_inst \n connect slots_18.io.in_uop.bits.ftq_idx, issue_slots[18].in_uop.bits.ftq_idx \n connect slots_18.io.in_uop.bits.is_mov, issue_slots[18].in_uop.bits.is_mov \n connect slots_18.io.in_uop.bits.is_rocc, issue_slots[18].in_uop.bits.is_rocc \n connect slots_18.io.in_uop.bits.is_sys_pc2epc, issue_slots[18].in_uop.bits.is_sys_pc2epc \n connect slots_18.io.in_uop.bits.is_eret, issue_slots[18].in_uop.bits.is_eret \n connect slots_18.io.in_uop.bits.is_amo, issue_slots[18].in_uop.bits.is_amo \n connect slots_18.io.in_uop.bits.is_sfence, issue_slots[18].in_uop.bits.is_sfence \n connect slots_18.io.in_uop.bits.is_fencei, issue_slots[18].in_uop.bits.is_fencei \n connect slots_18.io.in_uop.bits.is_fence, issue_slots[18].in_uop.bits.is_fence \n connect slots_18.io.in_uop.bits.is_sfb, issue_slots[18].in_uop.bits.is_sfb \n connect slots_18.io.in_uop.bits.br_type, issue_slots[18].in_uop.bits.br_type \n connect slots_18.io.in_uop.bits.br_tag, issue_slots[18].in_uop.bits.br_tag \n connect slots_18.io.in_uop.bits.br_mask, issue_slots[18].in_uop.bits.br_mask \n connect slots_18.io.in_uop.bits.dis_col_sel, issue_slots[18].in_uop.bits.dis_col_sel \n connect slots_18.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[18].in_uop.bits.iw_p3_bypass_hint \n connect slots_18.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[18].in_uop.bits.iw_p2_bypass_hint \n connect slots_18.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[18].in_uop.bits.iw_p1_bypass_hint \n connect slots_18.io.in_uop.bits.iw_p2_speculative_child, issue_slots[18].in_uop.bits.iw_p2_speculative_child \n connect slots_18.io.in_uop.bits.iw_p1_speculative_child, issue_slots[18].in_uop.bits.iw_p1_speculative_child \n connect slots_18.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[18].in_uop.bits.iw_issued_partial_dgen \n connect slots_18.io.in_uop.bits.iw_issued_partial_agen, issue_slots[18].in_uop.bits.iw_issued_partial_agen \n connect slots_18.io.in_uop.bits.iw_issued, issue_slots[18].in_uop.bits.iw_issued \n connect slots_18.io.in_uop.bits.fu_code[0], issue_slots[18].in_uop.bits.fu_code[0] \n connect slots_18.io.in_uop.bits.fu_code[1], issue_slots[18].in_uop.bits.fu_code[1] \n connect slots_18.io.in_uop.bits.fu_code[2], issue_slots[18].in_uop.bits.fu_code[2] \n connect slots_18.io.in_uop.bits.fu_code[3], issue_slots[18].in_uop.bits.fu_code[3] \n connect slots_18.io.in_uop.bits.fu_code[4], issue_slots[18].in_uop.bits.fu_code[4] \n connect slots_18.io.in_uop.bits.fu_code[5], issue_slots[18].in_uop.bits.fu_code[5] \n connect slots_18.io.in_uop.bits.fu_code[6], issue_slots[18].in_uop.bits.fu_code[6] \n connect slots_18.io.in_uop.bits.fu_code[7], issue_slots[18].in_uop.bits.fu_code[7] \n connect slots_18.io.in_uop.bits.fu_code[8], issue_slots[18].in_uop.bits.fu_code[8] \n connect slots_18.io.in_uop.bits.fu_code[9], issue_slots[18].in_uop.bits.fu_code[9] \n connect slots_18.io.in_uop.bits.iq_type[0], issue_slots[18].in_uop.bits.iq_type[0] \n connect slots_18.io.in_uop.bits.iq_type[1], issue_slots[18].in_uop.bits.iq_type[1] \n connect slots_18.io.in_uop.bits.iq_type[2], issue_slots[18].in_uop.bits.iq_type[2] \n connect slots_18.io.in_uop.bits.iq_type[3], issue_slots[18].in_uop.bits.iq_type[3] \n connect slots_18.io.in_uop.bits.debug_pc, issue_slots[18].in_uop.bits.debug_pc \n connect slots_18.io.in_uop.bits.is_rvc, issue_slots[18].in_uop.bits.is_rvc \n connect slots_18.io.in_uop.bits.debug_inst, issue_slots[18].in_uop.bits.debug_inst \n connect slots_18.io.in_uop.bits.inst, issue_slots[18].in_uop.bits.inst \n connect slots_18.io.in_uop.valid, issue_slots[18].in_uop.valid \n connect issue_slots[18].iss_uop.debug_tsrc, slots_18.io.iss_uop.debug_tsrc \n connect issue_slots[18].iss_uop.debug_fsrc, slots_18.io.iss_uop.debug_fsrc \n connect issue_slots[18].iss_uop.bp_xcpt_if, slots_18.io.iss_uop.bp_xcpt_if \n connect issue_slots[18].iss_uop.bp_debug_if, slots_18.io.iss_uop.bp_debug_if \n connect issue_slots[18].iss_uop.xcpt_ma_if, slots_18.io.iss_uop.xcpt_ma_if \n connect issue_slots[18].iss_uop.xcpt_ae_if, slots_18.io.iss_uop.xcpt_ae_if \n connect issue_slots[18].iss_uop.xcpt_pf_if, slots_18.io.iss_uop.xcpt_pf_if \n connect issue_slots[18].iss_uop.fp_typ, slots_18.io.iss_uop.fp_typ \n connect issue_slots[18].iss_uop.fp_rm, slots_18.io.iss_uop.fp_rm \n connect issue_slots[18].iss_uop.fp_val, slots_18.io.iss_uop.fp_val \n connect issue_slots[18].iss_uop.fcn_op, slots_18.io.iss_uop.fcn_op \n connect issue_slots[18].iss_uop.fcn_dw, slots_18.io.iss_uop.fcn_dw \n connect issue_slots[18].iss_uop.frs3_en, slots_18.io.iss_uop.frs3_en \n connect issue_slots[18].iss_uop.lrs2_rtype, slots_18.io.iss_uop.lrs2_rtype \n connect issue_slots[18].iss_uop.lrs1_rtype, slots_18.io.iss_uop.lrs1_rtype \n connect issue_slots[18].iss_uop.dst_rtype, slots_18.io.iss_uop.dst_rtype \n connect issue_slots[18].iss_uop.lrs3, slots_18.io.iss_uop.lrs3 \n connect issue_slots[18].iss_uop.lrs2, slots_18.io.iss_uop.lrs2 \n connect issue_slots[18].iss_uop.lrs1, slots_18.io.iss_uop.lrs1 \n connect issue_slots[18].iss_uop.ldst, slots_18.io.iss_uop.ldst \n connect issue_slots[18].iss_uop.ldst_is_rs1, slots_18.io.iss_uop.ldst_is_rs1 \n connect issue_slots[18].iss_uop.csr_cmd, slots_18.io.iss_uop.csr_cmd \n connect issue_slots[18].iss_uop.flush_on_commit, slots_18.io.iss_uop.flush_on_commit \n connect issue_slots[18].iss_uop.is_unique, slots_18.io.iss_uop.is_unique \n connect issue_slots[18].iss_uop.uses_stq, slots_18.io.iss_uop.uses_stq \n connect issue_slots[18].iss_uop.uses_ldq, slots_18.io.iss_uop.uses_ldq \n connect issue_slots[18].iss_uop.mem_signed, slots_18.io.iss_uop.mem_signed \n connect issue_slots[18].iss_uop.mem_size, slots_18.io.iss_uop.mem_size \n connect issue_slots[18].iss_uop.mem_cmd, slots_18.io.iss_uop.mem_cmd \n connect issue_slots[18].iss_uop.exc_cause, slots_18.io.iss_uop.exc_cause \n connect issue_slots[18].iss_uop.exception, slots_18.io.iss_uop.exception \n connect issue_slots[18].iss_uop.stale_pdst, slots_18.io.iss_uop.stale_pdst \n connect issue_slots[18].iss_uop.ppred_busy, slots_18.io.iss_uop.ppred_busy \n connect issue_slots[18].iss_uop.prs3_busy, slots_18.io.iss_uop.prs3_busy \n connect issue_slots[18].iss_uop.prs2_busy, slots_18.io.iss_uop.prs2_busy \n connect issue_slots[18].iss_uop.prs1_busy, slots_18.io.iss_uop.prs1_busy \n connect issue_slots[18].iss_uop.ppred, slots_18.io.iss_uop.ppred \n connect issue_slots[18].iss_uop.prs3, slots_18.io.iss_uop.prs3 \n connect issue_slots[18].iss_uop.prs2, slots_18.io.iss_uop.prs2 \n connect issue_slots[18].iss_uop.prs1, slots_18.io.iss_uop.prs1 \n connect issue_slots[18].iss_uop.pdst, slots_18.io.iss_uop.pdst \n connect issue_slots[18].iss_uop.rxq_idx, slots_18.io.iss_uop.rxq_idx \n connect issue_slots[18].iss_uop.stq_idx, slots_18.io.iss_uop.stq_idx \n connect issue_slots[18].iss_uop.ldq_idx, slots_18.io.iss_uop.ldq_idx \n connect issue_slots[18].iss_uop.rob_idx, slots_18.io.iss_uop.rob_idx \n connect issue_slots[18].iss_uop.fp_ctrl.vec, slots_18.io.iss_uop.fp_ctrl.vec \n connect issue_slots[18].iss_uop.fp_ctrl.wflags, slots_18.io.iss_uop.fp_ctrl.wflags \n connect issue_slots[18].iss_uop.fp_ctrl.sqrt, slots_18.io.iss_uop.fp_ctrl.sqrt \n connect issue_slots[18].iss_uop.fp_ctrl.div, slots_18.io.iss_uop.fp_ctrl.div \n connect issue_slots[18].iss_uop.fp_ctrl.fma, slots_18.io.iss_uop.fp_ctrl.fma \n connect issue_slots[18].iss_uop.fp_ctrl.fastpipe, slots_18.io.iss_uop.fp_ctrl.fastpipe \n connect issue_slots[18].iss_uop.fp_ctrl.toint, slots_18.io.iss_uop.fp_ctrl.toint \n connect issue_slots[18].iss_uop.fp_ctrl.fromint, slots_18.io.iss_uop.fp_ctrl.fromint \n connect issue_slots[18].iss_uop.fp_ctrl.typeTagOut, slots_18.io.iss_uop.fp_ctrl.typeTagOut \n connect issue_slots[18].iss_uop.fp_ctrl.typeTagIn, slots_18.io.iss_uop.fp_ctrl.typeTagIn \n connect issue_slots[18].iss_uop.fp_ctrl.swap23, slots_18.io.iss_uop.fp_ctrl.swap23 \n connect issue_slots[18].iss_uop.fp_ctrl.swap12, slots_18.io.iss_uop.fp_ctrl.swap12 \n connect issue_slots[18].iss_uop.fp_ctrl.ren3, slots_18.io.iss_uop.fp_ctrl.ren3 \n connect issue_slots[18].iss_uop.fp_ctrl.ren2, slots_18.io.iss_uop.fp_ctrl.ren2 \n connect issue_slots[18].iss_uop.fp_ctrl.ren1, slots_18.io.iss_uop.fp_ctrl.ren1 \n connect issue_slots[18].iss_uop.fp_ctrl.wen, slots_18.io.iss_uop.fp_ctrl.wen \n connect issue_slots[18].iss_uop.fp_ctrl.ldst, slots_18.io.iss_uop.fp_ctrl.ldst \n connect issue_slots[18].iss_uop.op2_sel, slots_18.io.iss_uop.op2_sel \n connect issue_slots[18].iss_uop.op1_sel, slots_18.io.iss_uop.op1_sel \n connect issue_slots[18].iss_uop.imm_packed, slots_18.io.iss_uop.imm_packed \n connect issue_slots[18].iss_uop.pimm, slots_18.io.iss_uop.pimm \n connect issue_slots[18].iss_uop.imm_sel, slots_18.io.iss_uop.imm_sel \n connect issue_slots[18].iss_uop.imm_rename, slots_18.io.iss_uop.imm_rename \n connect issue_slots[18].iss_uop.taken, slots_18.io.iss_uop.taken \n connect issue_slots[18].iss_uop.pc_lob, slots_18.io.iss_uop.pc_lob \n connect issue_slots[18].iss_uop.edge_inst, slots_18.io.iss_uop.edge_inst \n connect issue_slots[18].iss_uop.ftq_idx, slots_18.io.iss_uop.ftq_idx \n connect issue_slots[18].iss_uop.is_mov, slots_18.io.iss_uop.is_mov \n connect issue_slots[18].iss_uop.is_rocc, slots_18.io.iss_uop.is_rocc \n connect issue_slots[18].iss_uop.is_sys_pc2epc, slots_18.io.iss_uop.is_sys_pc2epc \n connect issue_slots[18].iss_uop.is_eret, slots_18.io.iss_uop.is_eret \n connect issue_slots[18].iss_uop.is_amo, slots_18.io.iss_uop.is_amo \n connect issue_slots[18].iss_uop.is_sfence, slots_18.io.iss_uop.is_sfence \n connect issue_slots[18].iss_uop.is_fencei, slots_18.io.iss_uop.is_fencei \n connect issue_slots[18].iss_uop.is_fence, slots_18.io.iss_uop.is_fence \n connect issue_slots[18].iss_uop.is_sfb, slots_18.io.iss_uop.is_sfb \n connect issue_slots[18].iss_uop.br_type, slots_18.io.iss_uop.br_type \n connect issue_slots[18].iss_uop.br_tag, slots_18.io.iss_uop.br_tag \n connect issue_slots[18].iss_uop.br_mask, slots_18.io.iss_uop.br_mask \n connect issue_slots[18].iss_uop.dis_col_sel, slots_18.io.iss_uop.dis_col_sel \n connect issue_slots[18].iss_uop.iw_p3_bypass_hint, slots_18.io.iss_uop.iw_p3_bypass_hint \n connect issue_slots[18].iss_uop.iw_p2_bypass_hint, slots_18.io.iss_uop.iw_p2_bypass_hint \n connect issue_slots[18].iss_uop.iw_p1_bypass_hint, slots_18.io.iss_uop.iw_p1_bypass_hint \n connect issue_slots[18].iss_uop.iw_p2_speculative_child, slots_18.io.iss_uop.iw_p2_speculative_child \n connect issue_slots[18].iss_uop.iw_p1_speculative_child, slots_18.io.iss_uop.iw_p1_speculative_child \n connect issue_slots[18].iss_uop.iw_issued_partial_dgen, slots_18.io.iss_uop.iw_issued_partial_dgen \n connect issue_slots[18].iss_uop.iw_issued_partial_agen, slots_18.io.iss_uop.iw_issued_partial_agen \n connect issue_slots[18].iss_uop.iw_issued, slots_18.io.iss_uop.iw_issued \n connect issue_slots[18].iss_uop.fu_code[0], slots_18.io.iss_uop.fu_code[0] \n connect issue_slots[18].iss_uop.fu_code[1], slots_18.io.iss_uop.fu_code[1] \n connect issue_slots[18].iss_uop.fu_code[2], slots_18.io.iss_uop.fu_code[2] \n connect issue_slots[18].iss_uop.fu_code[3], slots_18.io.iss_uop.fu_code[3] \n connect issue_slots[18].iss_uop.fu_code[4], slots_18.io.iss_uop.fu_code[4] \n connect issue_slots[18].iss_uop.fu_code[5], slots_18.io.iss_uop.fu_code[5] \n connect issue_slots[18].iss_uop.fu_code[6], slots_18.io.iss_uop.fu_code[6] \n connect issue_slots[18].iss_uop.fu_code[7], slots_18.io.iss_uop.fu_code[7] \n connect issue_slots[18].iss_uop.fu_code[8], slots_18.io.iss_uop.fu_code[8] \n connect issue_slots[18].iss_uop.fu_code[9], slots_18.io.iss_uop.fu_code[9] \n connect issue_slots[18].iss_uop.iq_type[0], slots_18.io.iss_uop.iq_type[0] \n connect issue_slots[18].iss_uop.iq_type[1], slots_18.io.iss_uop.iq_type[1] \n connect issue_slots[18].iss_uop.iq_type[2], slots_18.io.iss_uop.iq_type[2] \n connect issue_slots[18].iss_uop.iq_type[3], slots_18.io.iss_uop.iq_type[3] \n connect issue_slots[18].iss_uop.debug_pc, slots_18.io.iss_uop.debug_pc \n connect issue_slots[18].iss_uop.is_rvc, slots_18.io.iss_uop.is_rvc \n connect issue_slots[18].iss_uop.debug_inst, slots_18.io.iss_uop.debug_inst \n connect issue_slots[18].iss_uop.inst, slots_18.io.iss_uop.inst \n connect slots_18.io.grant, issue_slots[18].grant \n connect issue_slots[18].request, slots_18.io.request \n connect issue_slots[18].will_be_valid, slots_18.io.will_be_valid \n connect issue_slots[18].valid, slots_18.io.valid \n connect slots_19.io.child_rebusys, issue_slots[19].child_rebusys \n connect slots_19.io.pred_wakeup_port.bits, issue_slots[19].pred_wakeup_port.bits \n connect slots_19.io.pred_wakeup_port.valid, issue_slots[19].pred_wakeup_port.valid \n connect slots_19.io.wakeup_ports[0].bits.rebusy, issue_slots[19].wakeup_ports[0].bits.rebusy \n connect slots_19.io.wakeup_ports[0].bits.speculative_mask, issue_slots[19].wakeup_ports[0].bits.speculative_mask \n connect slots_19.io.wakeup_ports[0].bits.bypassable, issue_slots[19].wakeup_ports[0].bits.bypassable \n connect slots_19.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[19].wakeup_ports[0].bits.uop.debug_tsrc \n connect slots_19.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[19].wakeup_ports[0].bits.uop.debug_fsrc \n connect slots_19.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[19].wakeup_ports[0].bits.uop.bp_xcpt_if \n connect slots_19.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[19].wakeup_ports[0].bits.uop.bp_debug_if \n connect slots_19.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[19].wakeup_ports[0].bits.uop.xcpt_ma_if \n connect slots_19.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[19].wakeup_ports[0].bits.uop.xcpt_ae_if \n connect slots_19.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[19].wakeup_ports[0].bits.uop.xcpt_pf_if \n connect slots_19.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[19].wakeup_ports[0].bits.uop.fp_typ \n connect slots_19.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[19].wakeup_ports[0].bits.uop.fp_rm \n connect slots_19.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[19].wakeup_ports[0].bits.uop.fp_val \n connect slots_19.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[19].wakeup_ports[0].bits.uop.fcn_op \n connect slots_19.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[19].wakeup_ports[0].bits.uop.fcn_dw \n connect slots_19.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[19].wakeup_ports[0].bits.uop.frs3_en \n connect slots_19.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[19].wakeup_ports[0].bits.uop.lrs2_rtype \n connect slots_19.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[19].wakeup_ports[0].bits.uop.lrs1_rtype \n connect slots_19.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[19].wakeup_ports[0].bits.uop.dst_rtype \n connect slots_19.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[19].wakeup_ports[0].bits.uop.lrs3 \n connect slots_19.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[19].wakeup_ports[0].bits.uop.lrs2 \n connect slots_19.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[19].wakeup_ports[0].bits.uop.lrs1 \n connect slots_19.io.wakeup_ports[0].bits.uop.ldst, issue_slots[19].wakeup_ports[0].bits.uop.ldst \n connect slots_19.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[19].wakeup_ports[0].bits.uop.ldst_is_rs1 \n connect slots_19.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[19].wakeup_ports[0].bits.uop.csr_cmd \n connect slots_19.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[19].wakeup_ports[0].bits.uop.flush_on_commit \n connect slots_19.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[19].wakeup_ports[0].bits.uop.is_unique \n connect slots_19.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[19].wakeup_ports[0].bits.uop.uses_stq \n connect slots_19.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[19].wakeup_ports[0].bits.uop.uses_ldq \n connect slots_19.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[19].wakeup_ports[0].bits.uop.mem_signed \n connect slots_19.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[19].wakeup_ports[0].bits.uop.mem_size \n connect slots_19.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[19].wakeup_ports[0].bits.uop.mem_cmd \n connect slots_19.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[19].wakeup_ports[0].bits.uop.exc_cause \n connect slots_19.io.wakeup_ports[0].bits.uop.exception, issue_slots[19].wakeup_ports[0].bits.uop.exception \n connect slots_19.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[19].wakeup_ports[0].bits.uop.stale_pdst \n connect slots_19.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[19].wakeup_ports[0].bits.uop.ppred_busy \n connect slots_19.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[19].wakeup_ports[0].bits.uop.prs3_busy \n connect slots_19.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[19].wakeup_ports[0].bits.uop.prs2_busy \n connect slots_19.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[19].wakeup_ports[0].bits.uop.prs1_busy \n connect slots_19.io.wakeup_ports[0].bits.uop.ppred, issue_slots[19].wakeup_ports[0].bits.uop.ppred \n connect slots_19.io.wakeup_ports[0].bits.uop.prs3, issue_slots[19].wakeup_ports[0].bits.uop.prs3 \n connect slots_19.io.wakeup_ports[0].bits.uop.prs2, issue_slots[19].wakeup_ports[0].bits.uop.prs2 \n connect slots_19.io.wakeup_ports[0].bits.uop.prs1, issue_slots[19].wakeup_ports[0].bits.uop.prs1 \n connect slots_19.io.wakeup_ports[0].bits.uop.pdst, issue_slots[19].wakeup_ports[0].bits.uop.pdst \n connect slots_19.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[19].wakeup_ports[0].bits.uop.rxq_idx \n connect slots_19.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[19].wakeup_ports[0].bits.uop.stq_idx \n connect slots_19.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[19].wakeup_ports[0].bits.uop.ldq_idx \n connect slots_19.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[19].wakeup_ports[0].bits.uop.rob_idx \n connect slots_19.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.vec \n connect slots_19.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.wflags \n connect slots_19.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.sqrt \n connect slots_19.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.div \n connect slots_19.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.fma \n connect slots_19.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe \n connect slots_19.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.toint \n connect slots_19.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.fromint \n connect slots_19.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut \n connect slots_19.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn \n connect slots_19.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.swap23 \n connect slots_19.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.swap12 \n connect slots_19.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.ren3 \n connect slots_19.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.ren2 \n connect slots_19.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.ren1 \n connect slots_19.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.wen \n connect slots_19.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.ldst \n connect slots_19.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[19].wakeup_ports[0].bits.uop.op2_sel \n connect slots_19.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[19].wakeup_ports[0].bits.uop.op1_sel \n connect slots_19.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[19].wakeup_ports[0].bits.uop.imm_packed \n connect slots_19.io.wakeup_ports[0].bits.uop.pimm, issue_slots[19].wakeup_ports[0].bits.uop.pimm \n connect slots_19.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[19].wakeup_ports[0].bits.uop.imm_sel \n connect slots_19.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[19].wakeup_ports[0].bits.uop.imm_rename \n connect slots_19.io.wakeup_ports[0].bits.uop.taken, issue_slots[19].wakeup_ports[0].bits.uop.taken \n connect slots_19.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[19].wakeup_ports[0].bits.uop.pc_lob \n connect slots_19.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[19].wakeup_ports[0].bits.uop.edge_inst \n connect slots_19.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[19].wakeup_ports[0].bits.uop.ftq_idx \n connect slots_19.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[19].wakeup_ports[0].bits.uop.is_mov \n connect slots_19.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[19].wakeup_ports[0].bits.uop.is_rocc \n connect slots_19.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[19].wakeup_ports[0].bits.uop.is_sys_pc2epc \n connect slots_19.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[19].wakeup_ports[0].bits.uop.is_eret \n connect slots_19.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[19].wakeup_ports[0].bits.uop.is_amo \n connect slots_19.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[19].wakeup_ports[0].bits.uop.is_sfence \n connect slots_19.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[19].wakeup_ports[0].bits.uop.is_fencei \n connect slots_19.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[19].wakeup_ports[0].bits.uop.is_fence \n connect slots_19.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[19].wakeup_ports[0].bits.uop.is_sfb \n connect slots_19.io.wakeup_ports[0].bits.uop.br_type, issue_slots[19].wakeup_ports[0].bits.uop.br_type \n connect slots_19.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[19].wakeup_ports[0].bits.uop.br_tag \n connect slots_19.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[19].wakeup_ports[0].bits.uop.br_mask \n connect slots_19.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[19].wakeup_ports[0].bits.uop.dis_col_sel \n connect slots_19.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[19].wakeup_ports[0].bits.uop.iw_p3_bypass_hint \n connect slots_19.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[19].wakeup_ports[0].bits.uop.iw_p2_bypass_hint \n connect slots_19.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[19].wakeup_ports[0].bits.uop.iw_p1_bypass_hint \n connect slots_19.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[19].wakeup_ports[0].bits.uop.iw_p2_speculative_child \n connect slots_19.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[19].wakeup_ports[0].bits.uop.iw_p1_speculative_child \n connect slots_19.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[19].wakeup_ports[0].bits.uop.iw_issued_partial_dgen \n connect slots_19.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[19].wakeup_ports[0].bits.uop.iw_issued_partial_agen \n connect slots_19.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[19].wakeup_ports[0].bits.uop.iw_issued \n connect slots_19.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[19].wakeup_ports[0].bits.uop.fu_code[0] \n connect slots_19.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[19].wakeup_ports[0].bits.uop.fu_code[1] \n connect slots_19.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[19].wakeup_ports[0].bits.uop.fu_code[2] \n connect slots_19.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[19].wakeup_ports[0].bits.uop.fu_code[3] \n connect slots_19.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[19].wakeup_ports[0].bits.uop.fu_code[4] \n connect slots_19.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[19].wakeup_ports[0].bits.uop.fu_code[5] \n connect slots_19.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[19].wakeup_ports[0].bits.uop.fu_code[6] \n connect slots_19.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[19].wakeup_ports[0].bits.uop.fu_code[7] \n connect slots_19.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[19].wakeup_ports[0].bits.uop.fu_code[8] \n connect slots_19.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[19].wakeup_ports[0].bits.uop.fu_code[9] \n connect slots_19.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[19].wakeup_ports[0].bits.uop.iq_type[0] \n connect slots_19.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[19].wakeup_ports[0].bits.uop.iq_type[1] \n connect slots_19.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[19].wakeup_ports[0].bits.uop.iq_type[2] \n connect slots_19.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[19].wakeup_ports[0].bits.uop.iq_type[3] \n connect slots_19.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[19].wakeup_ports[0].bits.uop.debug_pc \n connect slots_19.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[19].wakeup_ports[0].bits.uop.is_rvc \n connect slots_19.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[19].wakeup_ports[0].bits.uop.debug_inst \n connect slots_19.io.wakeup_ports[0].bits.uop.inst, issue_slots[19].wakeup_ports[0].bits.uop.inst \n connect slots_19.io.wakeup_ports[0].valid, issue_slots[19].wakeup_ports[0].valid \n connect slots_19.io.wakeup_ports[1].bits.rebusy, issue_slots[19].wakeup_ports[1].bits.rebusy \n connect slots_19.io.wakeup_ports[1].bits.speculative_mask, issue_slots[19].wakeup_ports[1].bits.speculative_mask \n connect slots_19.io.wakeup_ports[1].bits.bypassable, issue_slots[19].wakeup_ports[1].bits.bypassable \n connect slots_19.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[19].wakeup_ports[1].bits.uop.debug_tsrc \n connect slots_19.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[19].wakeup_ports[1].bits.uop.debug_fsrc \n connect slots_19.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[19].wakeup_ports[1].bits.uop.bp_xcpt_if \n connect slots_19.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[19].wakeup_ports[1].bits.uop.bp_debug_if \n connect slots_19.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[19].wakeup_ports[1].bits.uop.xcpt_ma_if \n connect slots_19.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[19].wakeup_ports[1].bits.uop.xcpt_ae_if \n connect slots_19.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[19].wakeup_ports[1].bits.uop.xcpt_pf_if \n connect slots_19.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[19].wakeup_ports[1].bits.uop.fp_typ \n connect slots_19.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[19].wakeup_ports[1].bits.uop.fp_rm \n connect slots_19.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[19].wakeup_ports[1].bits.uop.fp_val \n connect slots_19.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[19].wakeup_ports[1].bits.uop.fcn_op \n connect slots_19.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[19].wakeup_ports[1].bits.uop.fcn_dw \n connect slots_19.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[19].wakeup_ports[1].bits.uop.frs3_en \n connect slots_19.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[19].wakeup_ports[1].bits.uop.lrs2_rtype \n connect slots_19.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[19].wakeup_ports[1].bits.uop.lrs1_rtype \n connect slots_19.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[19].wakeup_ports[1].bits.uop.dst_rtype \n connect slots_19.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[19].wakeup_ports[1].bits.uop.lrs3 \n connect slots_19.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[19].wakeup_ports[1].bits.uop.lrs2 \n connect slots_19.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[19].wakeup_ports[1].bits.uop.lrs1 \n connect slots_19.io.wakeup_ports[1].bits.uop.ldst, issue_slots[19].wakeup_ports[1].bits.uop.ldst \n connect slots_19.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[19].wakeup_ports[1].bits.uop.ldst_is_rs1 \n connect slots_19.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[19].wakeup_ports[1].bits.uop.csr_cmd \n connect slots_19.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[19].wakeup_ports[1].bits.uop.flush_on_commit \n connect slots_19.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[19].wakeup_ports[1].bits.uop.is_unique \n connect slots_19.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[19].wakeup_ports[1].bits.uop.uses_stq \n connect slots_19.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[19].wakeup_ports[1].bits.uop.uses_ldq \n connect slots_19.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[19].wakeup_ports[1].bits.uop.mem_signed \n connect slots_19.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[19].wakeup_ports[1].bits.uop.mem_size \n connect slots_19.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[19].wakeup_ports[1].bits.uop.mem_cmd \n connect slots_19.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[19].wakeup_ports[1].bits.uop.exc_cause \n connect slots_19.io.wakeup_ports[1].bits.uop.exception, issue_slots[19].wakeup_ports[1].bits.uop.exception \n connect slots_19.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[19].wakeup_ports[1].bits.uop.stale_pdst \n connect slots_19.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[19].wakeup_ports[1].bits.uop.ppred_busy \n connect slots_19.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[19].wakeup_ports[1].bits.uop.prs3_busy \n connect slots_19.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[19].wakeup_ports[1].bits.uop.prs2_busy \n connect slots_19.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[19].wakeup_ports[1].bits.uop.prs1_busy \n connect slots_19.io.wakeup_ports[1].bits.uop.ppred, issue_slots[19].wakeup_ports[1].bits.uop.ppred \n connect slots_19.io.wakeup_ports[1].bits.uop.prs3, issue_slots[19].wakeup_ports[1].bits.uop.prs3 \n connect slots_19.io.wakeup_ports[1].bits.uop.prs2, issue_slots[19].wakeup_ports[1].bits.uop.prs2 \n connect slots_19.io.wakeup_ports[1].bits.uop.prs1, issue_slots[19].wakeup_ports[1].bits.uop.prs1 \n connect slots_19.io.wakeup_ports[1].bits.uop.pdst, issue_slots[19].wakeup_ports[1].bits.uop.pdst \n connect slots_19.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[19].wakeup_ports[1].bits.uop.rxq_idx \n connect slots_19.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[19].wakeup_ports[1].bits.uop.stq_idx \n connect slots_19.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[19].wakeup_ports[1].bits.uop.ldq_idx \n connect slots_19.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[19].wakeup_ports[1].bits.uop.rob_idx \n connect slots_19.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.vec \n connect slots_19.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.wflags \n connect slots_19.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.sqrt \n connect slots_19.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.div \n connect slots_19.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.fma \n connect slots_19.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe \n connect slots_19.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.toint \n connect slots_19.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.fromint \n connect slots_19.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut \n connect slots_19.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn \n connect slots_19.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.swap23 \n connect slots_19.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.swap12 \n connect slots_19.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.ren3 \n connect slots_19.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.ren2 \n connect slots_19.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.ren1 \n connect slots_19.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.wen \n connect slots_19.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.ldst \n connect slots_19.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[19].wakeup_ports[1].bits.uop.op2_sel \n connect slots_19.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[19].wakeup_ports[1].bits.uop.op1_sel \n connect slots_19.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[19].wakeup_ports[1].bits.uop.imm_packed \n connect slots_19.io.wakeup_ports[1].bits.uop.pimm, issue_slots[19].wakeup_ports[1].bits.uop.pimm \n connect slots_19.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[19].wakeup_ports[1].bits.uop.imm_sel \n connect slots_19.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[19].wakeup_ports[1].bits.uop.imm_rename \n connect slots_19.io.wakeup_ports[1].bits.uop.taken, issue_slots[19].wakeup_ports[1].bits.uop.taken \n connect slots_19.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[19].wakeup_ports[1].bits.uop.pc_lob \n connect slots_19.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[19].wakeup_ports[1].bits.uop.edge_inst \n connect slots_19.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[19].wakeup_ports[1].bits.uop.ftq_idx \n connect slots_19.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[19].wakeup_ports[1].bits.uop.is_mov \n connect slots_19.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[19].wakeup_ports[1].bits.uop.is_rocc \n connect slots_19.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[19].wakeup_ports[1].bits.uop.is_sys_pc2epc \n connect slots_19.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[19].wakeup_ports[1].bits.uop.is_eret \n connect slots_19.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[19].wakeup_ports[1].bits.uop.is_amo \n connect slots_19.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[19].wakeup_ports[1].bits.uop.is_sfence \n connect slots_19.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[19].wakeup_ports[1].bits.uop.is_fencei \n connect slots_19.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[19].wakeup_ports[1].bits.uop.is_fence \n connect slots_19.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[19].wakeup_ports[1].bits.uop.is_sfb \n connect slots_19.io.wakeup_ports[1].bits.uop.br_type, issue_slots[19].wakeup_ports[1].bits.uop.br_type \n connect slots_19.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[19].wakeup_ports[1].bits.uop.br_tag \n connect slots_19.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[19].wakeup_ports[1].bits.uop.br_mask \n connect slots_19.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[19].wakeup_ports[1].bits.uop.dis_col_sel \n connect slots_19.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[19].wakeup_ports[1].bits.uop.iw_p3_bypass_hint \n connect slots_19.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[19].wakeup_ports[1].bits.uop.iw_p2_bypass_hint \n connect slots_19.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[19].wakeup_ports[1].bits.uop.iw_p1_bypass_hint \n connect slots_19.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[19].wakeup_ports[1].bits.uop.iw_p2_speculative_child \n connect slots_19.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[19].wakeup_ports[1].bits.uop.iw_p1_speculative_child \n connect slots_19.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[19].wakeup_ports[1].bits.uop.iw_issued_partial_dgen \n connect slots_19.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[19].wakeup_ports[1].bits.uop.iw_issued_partial_agen \n connect slots_19.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[19].wakeup_ports[1].bits.uop.iw_issued \n connect slots_19.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[19].wakeup_ports[1].bits.uop.fu_code[0] \n connect slots_19.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[19].wakeup_ports[1].bits.uop.fu_code[1] \n connect slots_19.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[19].wakeup_ports[1].bits.uop.fu_code[2] \n connect slots_19.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[19].wakeup_ports[1].bits.uop.fu_code[3] \n connect slots_19.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[19].wakeup_ports[1].bits.uop.fu_code[4] \n connect slots_19.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[19].wakeup_ports[1].bits.uop.fu_code[5] \n connect slots_19.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[19].wakeup_ports[1].bits.uop.fu_code[6] \n connect slots_19.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[19].wakeup_ports[1].bits.uop.fu_code[7] \n connect slots_19.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[19].wakeup_ports[1].bits.uop.fu_code[8] \n connect slots_19.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[19].wakeup_ports[1].bits.uop.fu_code[9] \n connect slots_19.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[19].wakeup_ports[1].bits.uop.iq_type[0] \n connect slots_19.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[19].wakeup_ports[1].bits.uop.iq_type[1] \n connect slots_19.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[19].wakeup_ports[1].bits.uop.iq_type[2] \n connect slots_19.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[19].wakeup_ports[1].bits.uop.iq_type[3] \n connect slots_19.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[19].wakeup_ports[1].bits.uop.debug_pc \n connect slots_19.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[19].wakeup_ports[1].bits.uop.is_rvc \n connect slots_19.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[19].wakeup_ports[1].bits.uop.debug_inst \n connect slots_19.io.wakeup_ports[1].bits.uop.inst, issue_slots[19].wakeup_ports[1].bits.uop.inst \n connect slots_19.io.wakeup_ports[1].valid, issue_slots[19].wakeup_ports[1].valid \n connect slots_19.io.wakeup_ports[2].bits.rebusy, issue_slots[19].wakeup_ports[2].bits.rebusy \n connect slots_19.io.wakeup_ports[2].bits.speculative_mask, issue_slots[19].wakeup_ports[2].bits.speculative_mask \n connect slots_19.io.wakeup_ports[2].bits.bypassable, issue_slots[19].wakeup_ports[2].bits.bypassable \n connect slots_19.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[19].wakeup_ports[2].bits.uop.debug_tsrc \n connect slots_19.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[19].wakeup_ports[2].bits.uop.debug_fsrc \n connect slots_19.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[19].wakeup_ports[2].bits.uop.bp_xcpt_if \n connect slots_19.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[19].wakeup_ports[2].bits.uop.bp_debug_if \n connect slots_19.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[19].wakeup_ports[2].bits.uop.xcpt_ma_if \n connect slots_19.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[19].wakeup_ports[2].bits.uop.xcpt_ae_if \n connect slots_19.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[19].wakeup_ports[2].bits.uop.xcpt_pf_if \n connect slots_19.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[19].wakeup_ports[2].bits.uop.fp_typ \n connect slots_19.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[19].wakeup_ports[2].bits.uop.fp_rm \n connect slots_19.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[19].wakeup_ports[2].bits.uop.fp_val \n connect slots_19.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[19].wakeup_ports[2].bits.uop.fcn_op \n connect slots_19.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[19].wakeup_ports[2].bits.uop.fcn_dw \n connect slots_19.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[19].wakeup_ports[2].bits.uop.frs3_en \n connect slots_19.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[19].wakeup_ports[2].bits.uop.lrs2_rtype \n connect slots_19.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[19].wakeup_ports[2].bits.uop.lrs1_rtype \n connect slots_19.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[19].wakeup_ports[2].bits.uop.dst_rtype \n connect slots_19.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[19].wakeup_ports[2].bits.uop.lrs3 \n connect slots_19.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[19].wakeup_ports[2].bits.uop.lrs2 \n connect slots_19.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[19].wakeup_ports[2].bits.uop.lrs1 \n connect slots_19.io.wakeup_ports[2].bits.uop.ldst, issue_slots[19].wakeup_ports[2].bits.uop.ldst \n connect slots_19.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[19].wakeup_ports[2].bits.uop.ldst_is_rs1 \n connect slots_19.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[19].wakeup_ports[2].bits.uop.csr_cmd \n connect slots_19.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[19].wakeup_ports[2].bits.uop.flush_on_commit \n connect slots_19.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[19].wakeup_ports[2].bits.uop.is_unique \n connect slots_19.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[19].wakeup_ports[2].bits.uop.uses_stq \n connect slots_19.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[19].wakeup_ports[2].bits.uop.uses_ldq \n connect slots_19.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[19].wakeup_ports[2].bits.uop.mem_signed \n connect slots_19.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[19].wakeup_ports[2].bits.uop.mem_size \n connect slots_19.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[19].wakeup_ports[2].bits.uop.mem_cmd \n connect slots_19.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[19].wakeup_ports[2].bits.uop.exc_cause \n connect slots_19.io.wakeup_ports[2].bits.uop.exception, issue_slots[19].wakeup_ports[2].bits.uop.exception \n connect slots_19.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[19].wakeup_ports[2].bits.uop.stale_pdst \n connect slots_19.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[19].wakeup_ports[2].bits.uop.ppred_busy \n connect slots_19.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[19].wakeup_ports[2].bits.uop.prs3_busy \n connect slots_19.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[19].wakeup_ports[2].bits.uop.prs2_busy \n connect slots_19.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[19].wakeup_ports[2].bits.uop.prs1_busy \n connect slots_19.io.wakeup_ports[2].bits.uop.ppred, issue_slots[19].wakeup_ports[2].bits.uop.ppred \n connect slots_19.io.wakeup_ports[2].bits.uop.prs3, issue_slots[19].wakeup_ports[2].bits.uop.prs3 \n connect slots_19.io.wakeup_ports[2].bits.uop.prs2, issue_slots[19].wakeup_ports[2].bits.uop.prs2 \n connect slots_19.io.wakeup_ports[2].bits.uop.prs1, issue_slots[19].wakeup_ports[2].bits.uop.prs1 \n connect slots_19.io.wakeup_ports[2].bits.uop.pdst, issue_slots[19].wakeup_ports[2].bits.uop.pdst \n connect slots_19.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[19].wakeup_ports[2].bits.uop.rxq_idx \n connect slots_19.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[19].wakeup_ports[2].bits.uop.stq_idx \n connect slots_19.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[19].wakeup_ports[2].bits.uop.ldq_idx \n connect slots_19.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[19].wakeup_ports[2].bits.uop.rob_idx \n connect slots_19.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.vec \n connect slots_19.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.wflags \n connect slots_19.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.sqrt \n connect slots_19.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.div \n connect slots_19.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.fma \n connect slots_19.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe \n connect slots_19.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.toint \n connect slots_19.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.fromint \n connect slots_19.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut \n connect slots_19.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn \n connect slots_19.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.swap23 \n connect slots_19.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.swap12 \n connect slots_19.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.ren3 \n connect slots_19.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.ren2 \n connect slots_19.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.ren1 \n connect slots_19.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.wen \n connect slots_19.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.ldst \n connect slots_19.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[19].wakeup_ports[2].bits.uop.op2_sel \n connect slots_19.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[19].wakeup_ports[2].bits.uop.op1_sel \n connect slots_19.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[19].wakeup_ports[2].bits.uop.imm_packed \n connect slots_19.io.wakeup_ports[2].bits.uop.pimm, issue_slots[19].wakeup_ports[2].bits.uop.pimm \n connect slots_19.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[19].wakeup_ports[2].bits.uop.imm_sel \n connect slots_19.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[19].wakeup_ports[2].bits.uop.imm_rename \n connect slots_19.io.wakeup_ports[2].bits.uop.taken, issue_slots[19].wakeup_ports[2].bits.uop.taken \n connect slots_19.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[19].wakeup_ports[2].bits.uop.pc_lob \n connect slots_19.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[19].wakeup_ports[2].bits.uop.edge_inst \n connect slots_19.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[19].wakeup_ports[2].bits.uop.ftq_idx \n connect slots_19.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[19].wakeup_ports[2].bits.uop.is_mov \n connect slots_19.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[19].wakeup_ports[2].bits.uop.is_rocc \n connect slots_19.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[19].wakeup_ports[2].bits.uop.is_sys_pc2epc \n connect slots_19.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[19].wakeup_ports[2].bits.uop.is_eret \n connect slots_19.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[19].wakeup_ports[2].bits.uop.is_amo \n connect slots_19.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[19].wakeup_ports[2].bits.uop.is_sfence \n connect slots_19.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[19].wakeup_ports[2].bits.uop.is_fencei \n connect slots_19.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[19].wakeup_ports[2].bits.uop.is_fence \n connect slots_19.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[19].wakeup_ports[2].bits.uop.is_sfb \n connect slots_19.io.wakeup_ports[2].bits.uop.br_type, issue_slots[19].wakeup_ports[2].bits.uop.br_type \n connect slots_19.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[19].wakeup_ports[2].bits.uop.br_tag \n connect slots_19.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[19].wakeup_ports[2].bits.uop.br_mask \n connect slots_19.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[19].wakeup_ports[2].bits.uop.dis_col_sel \n connect slots_19.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[19].wakeup_ports[2].bits.uop.iw_p3_bypass_hint \n connect slots_19.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[19].wakeup_ports[2].bits.uop.iw_p2_bypass_hint \n connect slots_19.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[19].wakeup_ports[2].bits.uop.iw_p1_bypass_hint \n connect slots_19.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[19].wakeup_ports[2].bits.uop.iw_p2_speculative_child \n connect slots_19.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[19].wakeup_ports[2].bits.uop.iw_p1_speculative_child \n connect slots_19.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[19].wakeup_ports[2].bits.uop.iw_issued_partial_dgen \n connect slots_19.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[19].wakeup_ports[2].bits.uop.iw_issued_partial_agen \n connect slots_19.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[19].wakeup_ports[2].bits.uop.iw_issued \n connect slots_19.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[19].wakeup_ports[2].bits.uop.fu_code[0] \n connect slots_19.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[19].wakeup_ports[2].bits.uop.fu_code[1] \n connect slots_19.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[19].wakeup_ports[2].bits.uop.fu_code[2] \n connect slots_19.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[19].wakeup_ports[2].bits.uop.fu_code[3] \n connect slots_19.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[19].wakeup_ports[2].bits.uop.fu_code[4] \n connect slots_19.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[19].wakeup_ports[2].bits.uop.fu_code[5] \n connect slots_19.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[19].wakeup_ports[2].bits.uop.fu_code[6] \n connect slots_19.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[19].wakeup_ports[2].bits.uop.fu_code[7] \n connect slots_19.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[19].wakeup_ports[2].bits.uop.fu_code[8] \n connect slots_19.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[19].wakeup_ports[2].bits.uop.fu_code[9] \n connect slots_19.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[19].wakeup_ports[2].bits.uop.iq_type[0] \n connect slots_19.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[19].wakeup_ports[2].bits.uop.iq_type[1] \n connect slots_19.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[19].wakeup_ports[2].bits.uop.iq_type[2] \n connect slots_19.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[19].wakeup_ports[2].bits.uop.iq_type[3] \n connect slots_19.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[19].wakeup_ports[2].bits.uop.debug_pc \n connect slots_19.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[19].wakeup_ports[2].bits.uop.is_rvc \n connect slots_19.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[19].wakeup_ports[2].bits.uop.debug_inst \n connect slots_19.io.wakeup_ports[2].bits.uop.inst, issue_slots[19].wakeup_ports[2].bits.uop.inst \n connect slots_19.io.wakeup_ports[2].valid, issue_slots[19].wakeup_ports[2].valid \n connect slots_19.io.wakeup_ports[3].bits.rebusy, issue_slots[19].wakeup_ports[3].bits.rebusy \n connect slots_19.io.wakeup_ports[3].bits.speculative_mask, issue_slots[19].wakeup_ports[3].bits.speculative_mask \n connect slots_19.io.wakeup_ports[3].bits.bypassable, issue_slots[19].wakeup_ports[3].bits.bypassable \n connect slots_19.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[19].wakeup_ports[3].bits.uop.debug_tsrc \n connect slots_19.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[19].wakeup_ports[3].bits.uop.debug_fsrc \n connect slots_19.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[19].wakeup_ports[3].bits.uop.bp_xcpt_if \n connect slots_19.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[19].wakeup_ports[3].bits.uop.bp_debug_if \n connect slots_19.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[19].wakeup_ports[3].bits.uop.xcpt_ma_if \n connect slots_19.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[19].wakeup_ports[3].bits.uop.xcpt_ae_if \n connect slots_19.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[19].wakeup_ports[3].bits.uop.xcpt_pf_if \n connect slots_19.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[19].wakeup_ports[3].bits.uop.fp_typ \n connect slots_19.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[19].wakeup_ports[3].bits.uop.fp_rm \n connect slots_19.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[19].wakeup_ports[3].bits.uop.fp_val \n connect slots_19.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[19].wakeup_ports[3].bits.uop.fcn_op \n connect slots_19.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[19].wakeup_ports[3].bits.uop.fcn_dw \n connect slots_19.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[19].wakeup_ports[3].bits.uop.frs3_en \n connect slots_19.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[19].wakeup_ports[3].bits.uop.lrs2_rtype \n connect slots_19.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[19].wakeup_ports[3].bits.uop.lrs1_rtype \n connect slots_19.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[19].wakeup_ports[3].bits.uop.dst_rtype \n connect slots_19.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[19].wakeup_ports[3].bits.uop.lrs3 \n connect slots_19.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[19].wakeup_ports[3].bits.uop.lrs2 \n connect slots_19.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[19].wakeup_ports[3].bits.uop.lrs1 \n connect slots_19.io.wakeup_ports[3].bits.uop.ldst, issue_slots[19].wakeup_ports[3].bits.uop.ldst \n connect slots_19.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[19].wakeup_ports[3].bits.uop.ldst_is_rs1 \n connect slots_19.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[19].wakeup_ports[3].bits.uop.csr_cmd \n connect slots_19.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[19].wakeup_ports[3].bits.uop.flush_on_commit \n connect slots_19.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[19].wakeup_ports[3].bits.uop.is_unique \n connect slots_19.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[19].wakeup_ports[3].bits.uop.uses_stq \n connect slots_19.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[19].wakeup_ports[3].bits.uop.uses_ldq \n connect slots_19.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[19].wakeup_ports[3].bits.uop.mem_signed \n connect slots_19.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[19].wakeup_ports[3].bits.uop.mem_size \n connect slots_19.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[19].wakeup_ports[3].bits.uop.mem_cmd \n connect slots_19.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[19].wakeup_ports[3].bits.uop.exc_cause \n connect slots_19.io.wakeup_ports[3].bits.uop.exception, issue_slots[19].wakeup_ports[3].bits.uop.exception \n connect slots_19.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[19].wakeup_ports[3].bits.uop.stale_pdst \n connect slots_19.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[19].wakeup_ports[3].bits.uop.ppred_busy \n connect slots_19.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[19].wakeup_ports[3].bits.uop.prs3_busy \n connect slots_19.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[19].wakeup_ports[3].bits.uop.prs2_busy \n connect slots_19.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[19].wakeup_ports[3].bits.uop.prs1_busy \n connect slots_19.io.wakeup_ports[3].bits.uop.ppred, issue_slots[19].wakeup_ports[3].bits.uop.ppred \n connect slots_19.io.wakeup_ports[3].bits.uop.prs3, issue_slots[19].wakeup_ports[3].bits.uop.prs3 \n connect slots_19.io.wakeup_ports[3].bits.uop.prs2, issue_slots[19].wakeup_ports[3].bits.uop.prs2 \n connect slots_19.io.wakeup_ports[3].bits.uop.prs1, issue_slots[19].wakeup_ports[3].bits.uop.prs1 \n connect slots_19.io.wakeup_ports[3].bits.uop.pdst, issue_slots[19].wakeup_ports[3].bits.uop.pdst \n connect slots_19.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[19].wakeup_ports[3].bits.uop.rxq_idx \n connect slots_19.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[19].wakeup_ports[3].bits.uop.stq_idx \n connect slots_19.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[19].wakeup_ports[3].bits.uop.ldq_idx \n connect slots_19.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[19].wakeup_ports[3].bits.uop.rob_idx \n connect slots_19.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.vec \n connect slots_19.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.wflags \n connect slots_19.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.sqrt \n connect slots_19.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.div \n connect slots_19.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.fma \n connect slots_19.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe \n connect slots_19.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.toint \n connect slots_19.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.fromint \n connect slots_19.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut \n connect slots_19.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn \n connect slots_19.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.swap23 \n connect slots_19.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.swap12 \n connect slots_19.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.ren3 \n connect slots_19.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.ren2 \n connect slots_19.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.ren1 \n connect slots_19.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.wen \n connect slots_19.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.ldst \n connect slots_19.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[19].wakeup_ports[3].bits.uop.op2_sel \n connect slots_19.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[19].wakeup_ports[3].bits.uop.op1_sel \n connect slots_19.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[19].wakeup_ports[3].bits.uop.imm_packed \n connect slots_19.io.wakeup_ports[3].bits.uop.pimm, issue_slots[19].wakeup_ports[3].bits.uop.pimm \n connect slots_19.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[19].wakeup_ports[3].bits.uop.imm_sel \n connect slots_19.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[19].wakeup_ports[3].bits.uop.imm_rename \n connect slots_19.io.wakeup_ports[3].bits.uop.taken, issue_slots[19].wakeup_ports[3].bits.uop.taken \n connect slots_19.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[19].wakeup_ports[3].bits.uop.pc_lob \n connect slots_19.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[19].wakeup_ports[3].bits.uop.edge_inst \n connect slots_19.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[19].wakeup_ports[3].bits.uop.ftq_idx \n connect slots_19.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[19].wakeup_ports[3].bits.uop.is_mov \n connect slots_19.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[19].wakeup_ports[3].bits.uop.is_rocc \n connect slots_19.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[19].wakeup_ports[3].bits.uop.is_sys_pc2epc \n connect slots_19.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[19].wakeup_ports[3].bits.uop.is_eret \n connect slots_19.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[19].wakeup_ports[3].bits.uop.is_amo \n connect slots_19.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[19].wakeup_ports[3].bits.uop.is_sfence \n connect slots_19.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[19].wakeup_ports[3].bits.uop.is_fencei \n connect slots_19.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[19].wakeup_ports[3].bits.uop.is_fence \n connect slots_19.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[19].wakeup_ports[3].bits.uop.is_sfb \n connect slots_19.io.wakeup_ports[3].bits.uop.br_type, issue_slots[19].wakeup_ports[3].bits.uop.br_type \n connect slots_19.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[19].wakeup_ports[3].bits.uop.br_tag \n connect slots_19.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[19].wakeup_ports[3].bits.uop.br_mask \n connect slots_19.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[19].wakeup_ports[3].bits.uop.dis_col_sel \n connect slots_19.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[19].wakeup_ports[3].bits.uop.iw_p3_bypass_hint \n connect slots_19.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[19].wakeup_ports[3].bits.uop.iw_p2_bypass_hint \n connect slots_19.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[19].wakeup_ports[3].bits.uop.iw_p1_bypass_hint \n connect slots_19.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[19].wakeup_ports[3].bits.uop.iw_p2_speculative_child \n connect slots_19.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[19].wakeup_ports[3].bits.uop.iw_p1_speculative_child \n connect slots_19.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[19].wakeup_ports[3].bits.uop.iw_issued_partial_dgen \n connect slots_19.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[19].wakeup_ports[3].bits.uop.iw_issued_partial_agen \n connect slots_19.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[19].wakeup_ports[3].bits.uop.iw_issued \n connect slots_19.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[19].wakeup_ports[3].bits.uop.fu_code[0] \n connect slots_19.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[19].wakeup_ports[3].bits.uop.fu_code[1] \n connect slots_19.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[19].wakeup_ports[3].bits.uop.fu_code[2] \n connect slots_19.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[19].wakeup_ports[3].bits.uop.fu_code[3] \n connect slots_19.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[19].wakeup_ports[3].bits.uop.fu_code[4] \n connect slots_19.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[19].wakeup_ports[3].bits.uop.fu_code[5] \n connect slots_19.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[19].wakeup_ports[3].bits.uop.fu_code[6] \n connect slots_19.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[19].wakeup_ports[3].bits.uop.fu_code[7] \n connect slots_19.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[19].wakeup_ports[3].bits.uop.fu_code[8] \n connect slots_19.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[19].wakeup_ports[3].bits.uop.fu_code[9] \n connect slots_19.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[19].wakeup_ports[3].bits.uop.iq_type[0] \n connect slots_19.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[19].wakeup_ports[3].bits.uop.iq_type[1] \n connect slots_19.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[19].wakeup_ports[3].bits.uop.iq_type[2] \n connect slots_19.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[19].wakeup_ports[3].bits.uop.iq_type[3] \n connect slots_19.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[19].wakeup_ports[3].bits.uop.debug_pc \n connect slots_19.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[19].wakeup_ports[3].bits.uop.is_rvc \n connect slots_19.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[19].wakeup_ports[3].bits.uop.debug_inst \n connect slots_19.io.wakeup_ports[3].bits.uop.inst, issue_slots[19].wakeup_ports[3].bits.uop.inst \n connect slots_19.io.wakeup_ports[3].valid, issue_slots[19].wakeup_ports[3].valid \n connect slots_19.io.squash_grant, issue_slots[19].squash_grant \n connect slots_19.io.clear, issue_slots[19].clear \n connect slots_19.io.kill, issue_slots[19].kill \n connect slots_19.io.brupdate.b2.target_offset, issue_slots[19].brupdate.b2.target_offset \n connect slots_19.io.brupdate.b2.jalr_target, issue_slots[19].brupdate.b2.jalr_target \n connect slots_19.io.brupdate.b2.pc_sel, issue_slots[19].brupdate.b2.pc_sel \n connect slots_19.io.brupdate.b2.cfi_type, issue_slots[19].brupdate.b2.cfi_type \n connect slots_19.io.brupdate.b2.taken, issue_slots[19].brupdate.b2.taken \n connect slots_19.io.brupdate.b2.mispredict, issue_slots[19].brupdate.b2.mispredict \n connect slots_19.io.brupdate.b2.uop.debug_tsrc, issue_slots[19].brupdate.b2.uop.debug_tsrc \n connect slots_19.io.brupdate.b2.uop.debug_fsrc, issue_slots[19].brupdate.b2.uop.debug_fsrc \n connect slots_19.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[19].brupdate.b2.uop.bp_xcpt_if \n connect slots_19.io.brupdate.b2.uop.bp_debug_if, issue_slots[19].brupdate.b2.uop.bp_debug_if \n connect slots_19.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[19].brupdate.b2.uop.xcpt_ma_if \n connect slots_19.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[19].brupdate.b2.uop.xcpt_ae_if \n connect slots_19.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[19].brupdate.b2.uop.xcpt_pf_if \n connect slots_19.io.brupdate.b2.uop.fp_typ, issue_slots[19].brupdate.b2.uop.fp_typ \n connect slots_19.io.brupdate.b2.uop.fp_rm, issue_slots[19].brupdate.b2.uop.fp_rm \n connect slots_19.io.brupdate.b2.uop.fp_val, issue_slots[19].brupdate.b2.uop.fp_val \n connect slots_19.io.brupdate.b2.uop.fcn_op, issue_slots[19].brupdate.b2.uop.fcn_op \n connect slots_19.io.brupdate.b2.uop.fcn_dw, issue_slots[19].brupdate.b2.uop.fcn_dw \n connect slots_19.io.brupdate.b2.uop.frs3_en, issue_slots[19].brupdate.b2.uop.frs3_en \n connect slots_19.io.brupdate.b2.uop.lrs2_rtype, issue_slots[19].brupdate.b2.uop.lrs2_rtype \n connect slots_19.io.brupdate.b2.uop.lrs1_rtype, issue_slots[19].brupdate.b2.uop.lrs1_rtype \n connect slots_19.io.brupdate.b2.uop.dst_rtype, issue_slots[19].brupdate.b2.uop.dst_rtype \n connect slots_19.io.brupdate.b2.uop.lrs3, issue_slots[19].brupdate.b2.uop.lrs3 \n connect slots_19.io.brupdate.b2.uop.lrs2, issue_slots[19].brupdate.b2.uop.lrs2 \n connect slots_19.io.brupdate.b2.uop.lrs1, issue_slots[19].brupdate.b2.uop.lrs1 \n connect slots_19.io.brupdate.b2.uop.ldst, issue_slots[19].brupdate.b2.uop.ldst \n connect slots_19.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[19].brupdate.b2.uop.ldst_is_rs1 \n connect slots_19.io.brupdate.b2.uop.csr_cmd, issue_slots[19].brupdate.b2.uop.csr_cmd \n connect slots_19.io.brupdate.b2.uop.flush_on_commit, issue_slots[19].brupdate.b2.uop.flush_on_commit \n connect slots_19.io.brupdate.b2.uop.is_unique, issue_slots[19].brupdate.b2.uop.is_unique \n connect slots_19.io.brupdate.b2.uop.uses_stq, issue_slots[19].brupdate.b2.uop.uses_stq \n connect slots_19.io.brupdate.b2.uop.uses_ldq, issue_slots[19].brupdate.b2.uop.uses_ldq \n connect slots_19.io.brupdate.b2.uop.mem_signed, issue_slots[19].brupdate.b2.uop.mem_signed \n connect slots_19.io.brupdate.b2.uop.mem_size, issue_slots[19].brupdate.b2.uop.mem_size \n connect slots_19.io.brupdate.b2.uop.mem_cmd, issue_slots[19].brupdate.b2.uop.mem_cmd \n connect slots_19.io.brupdate.b2.uop.exc_cause, issue_slots[19].brupdate.b2.uop.exc_cause \n connect slots_19.io.brupdate.b2.uop.exception, issue_slots[19].brupdate.b2.uop.exception \n connect slots_19.io.brupdate.b2.uop.stale_pdst, issue_slots[19].brupdate.b2.uop.stale_pdst \n connect slots_19.io.brupdate.b2.uop.ppred_busy, issue_slots[19].brupdate.b2.uop.ppred_busy \n connect slots_19.io.brupdate.b2.uop.prs3_busy, issue_slots[19].brupdate.b2.uop.prs3_busy \n connect slots_19.io.brupdate.b2.uop.prs2_busy, issue_slots[19].brupdate.b2.uop.prs2_busy \n connect slots_19.io.brupdate.b2.uop.prs1_busy, issue_slots[19].brupdate.b2.uop.prs1_busy \n connect slots_19.io.brupdate.b2.uop.ppred, issue_slots[19].brupdate.b2.uop.ppred \n connect slots_19.io.brupdate.b2.uop.prs3, issue_slots[19].brupdate.b2.uop.prs3 \n connect slots_19.io.brupdate.b2.uop.prs2, issue_slots[19].brupdate.b2.uop.prs2 \n connect slots_19.io.brupdate.b2.uop.prs1, issue_slots[19].brupdate.b2.uop.prs1 \n connect slots_19.io.brupdate.b2.uop.pdst, issue_slots[19].brupdate.b2.uop.pdst \n connect slots_19.io.brupdate.b2.uop.rxq_idx, issue_slots[19].brupdate.b2.uop.rxq_idx \n connect slots_19.io.brupdate.b2.uop.stq_idx, issue_slots[19].brupdate.b2.uop.stq_idx \n connect slots_19.io.brupdate.b2.uop.ldq_idx, issue_slots[19].brupdate.b2.uop.ldq_idx \n connect slots_19.io.brupdate.b2.uop.rob_idx, issue_slots[19].brupdate.b2.uop.rob_idx \n connect slots_19.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[19].brupdate.b2.uop.fp_ctrl.vec \n connect slots_19.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[19].brupdate.b2.uop.fp_ctrl.wflags \n connect slots_19.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[19].brupdate.b2.uop.fp_ctrl.sqrt \n connect slots_19.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[19].brupdate.b2.uop.fp_ctrl.div \n connect slots_19.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[19].brupdate.b2.uop.fp_ctrl.fma \n connect slots_19.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[19].brupdate.b2.uop.fp_ctrl.fastpipe \n connect slots_19.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[19].brupdate.b2.uop.fp_ctrl.toint \n connect slots_19.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[19].brupdate.b2.uop.fp_ctrl.fromint \n connect slots_19.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[19].brupdate.b2.uop.fp_ctrl.typeTagOut \n connect slots_19.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[19].brupdate.b2.uop.fp_ctrl.typeTagIn \n connect slots_19.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[19].brupdate.b2.uop.fp_ctrl.swap23 \n connect slots_19.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[19].brupdate.b2.uop.fp_ctrl.swap12 \n connect slots_19.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[19].brupdate.b2.uop.fp_ctrl.ren3 \n connect slots_19.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[19].brupdate.b2.uop.fp_ctrl.ren2 \n connect slots_19.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[19].brupdate.b2.uop.fp_ctrl.ren1 \n connect slots_19.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[19].brupdate.b2.uop.fp_ctrl.wen \n connect slots_19.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[19].brupdate.b2.uop.fp_ctrl.ldst \n connect slots_19.io.brupdate.b2.uop.op2_sel, issue_slots[19].brupdate.b2.uop.op2_sel \n connect slots_19.io.brupdate.b2.uop.op1_sel, issue_slots[19].brupdate.b2.uop.op1_sel \n connect slots_19.io.brupdate.b2.uop.imm_packed, issue_slots[19].brupdate.b2.uop.imm_packed \n connect slots_19.io.brupdate.b2.uop.pimm, issue_slots[19].brupdate.b2.uop.pimm \n connect slots_19.io.brupdate.b2.uop.imm_sel, issue_slots[19].brupdate.b2.uop.imm_sel \n connect slots_19.io.brupdate.b2.uop.imm_rename, issue_slots[19].brupdate.b2.uop.imm_rename \n connect slots_19.io.brupdate.b2.uop.taken, issue_slots[19].brupdate.b2.uop.taken \n connect slots_19.io.brupdate.b2.uop.pc_lob, issue_slots[19].brupdate.b2.uop.pc_lob \n connect slots_19.io.brupdate.b2.uop.edge_inst, issue_slots[19].brupdate.b2.uop.edge_inst \n connect slots_19.io.brupdate.b2.uop.ftq_idx, issue_slots[19].brupdate.b2.uop.ftq_idx \n connect slots_19.io.brupdate.b2.uop.is_mov, issue_slots[19].brupdate.b2.uop.is_mov \n connect slots_19.io.brupdate.b2.uop.is_rocc, issue_slots[19].brupdate.b2.uop.is_rocc \n connect slots_19.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[19].brupdate.b2.uop.is_sys_pc2epc \n connect slots_19.io.brupdate.b2.uop.is_eret, issue_slots[19].brupdate.b2.uop.is_eret \n connect slots_19.io.brupdate.b2.uop.is_amo, issue_slots[19].brupdate.b2.uop.is_amo \n connect slots_19.io.brupdate.b2.uop.is_sfence, issue_slots[19].brupdate.b2.uop.is_sfence \n connect slots_19.io.brupdate.b2.uop.is_fencei, issue_slots[19].brupdate.b2.uop.is_fencei \n connect slots_19.io.brupdate.b2.uop.is_fence, issue_slots[19].brupdate.b2.uop.is_fence \n connect slots_19.io.brupdate.b2.uop.is_sfb, issue_slots[19].brupdate.b2.uop.is_sfb \n connect slots_19.io.brupdate.b2.uop.br_type, issue_slots[19].brupdate.b2.uop.br_type \n connect slots_19.io.brupdate.b2.uop.br_tag, issue_slots[19].brupdate.b2.uop.br_tag \n connect slots_19.io.brupdate.b2.uop.br_mask, issue_slots[19].brupdate.b2.uop.br_mask \n connect slots_19.io.brupdate.b2.uop.dis_col_sel, issue_slots[19].brupdate.b2.uop.dis_col_sel \n connect slots_19.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[19].brupdate.b2.uop.iw_p3_bypass_hint \n connect slots_19.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[19].brupdate.b2.uop.iw_p2_bypass_hint \n connect slots_19.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[19].brupdate.b2.uop.iw_p1_bypass_hint \n connect slots_19.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[19].brupdate.b2.uop.iw_p2_speculative_child \n connect slots_19.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[19].brupdate.b2.uop.iw_p1_speculative_child \n connect slots_19.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[19].brupdate.b2.uop.iw_issued_partial_dgen \n connect slots_19.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[19].brupdate.b2.uop.iw_issued_partial_agen \n connect slots_19.io.brupdate.b2.uop.iw_issued, issue_slots[19].brupdate.b2.uop.iw_issued \n connect slots_19.io.brupdate.b2.uop.fu_code[0], issue_slots[19].brupdate.b2.uop.fu_code[0] \n connect slots_19.io.brupdate.b2.uop.fu_code[1], issue_slots[19].brupdate.b2.uop.fu_code[1] \n connect slots_19.io.brupdate.b2.uop.fu_code[2], issue_slots[19].brupdate.b2.uop.fu_code[2] \n connect slots_19.io.brupdate.b2.uop.fu_code[3], issue_slots[19].brupdate.b2.uop.fu_code[3] \n connect slots_19.io.brupdate.b2.uop.fu_code[4], issue_slots[19].brupdate.b2.uop.fu_code[4] \n connect slots_19.io.brupdate.b2.uop.fu_code[5], issue_slots[19].brupdate.b2.uop.fu_code[5] \n connect slots_19.io.brupdate.b2.uop.fu_code[6], issue_slots[19].brupdate.b2.uop.fu_code[6] \n connect slots_19.io.brupdate.b2.uop.fu_code[7], issue_slots[19].brupdate.b2.uop.fu_code[7] \n connect slots_19.io.brupdate.b2.uop.fu_code[8], issue_slots[19].brupdate.b2.uop.fu_code[8] \n connect slots_19.io.brupdate.b2.uop.fu_code[9], issue_slots[19].brupdate.b2.uop.fu_code[9] \n connect slots_19.io.brupdate.b2.uop.iq_type[0], issue_slots[19].brupdate.b2.uop.iq_type[0] \n connect slots_19.io.brupdate.b2.uop.iq_type[1], issue_slots[19].brupdate.b2.uop.iq_type[1] \n connect slots_19.io.brupdate.b2.uop.iq_type[2], issue_slots[19].brupdate.b2.uop.iq_type[2] \n connect slots_19.io.brupdate.b2.uop.iq_type[3], issue_slots[19].brupdate.b2.uop.iq_type[3] \n connect slots_19.io.brupdate.b2.uop.debug_pc, issue_slots[19].brupdate.b2.uop.debug_pc \n connect slots_19.io.brupdate.b2.uop.is_rvc, issue_slots[19].brupdate.b2.uop.is_rvc \n connect slots_19.io.brupdate.b2.uop.debug_inst, issue_slots[19].brupdate.b2.uop.debug_inst \n connect slots_19.io.brupdate.b2.uop.inst, issue_slots[19].brupdate.b2.uop.inst \n connect slots_19.io.brupdate.b1.mispredict_mask, issue_slots[19].brupdate.b1.mispredict_mask \n connect slots_19.io.brupdate.b1.resolve_mask, issue_slots[19].brupdate.b1.resolve_mask \n connect issue_slots[19].out_uop.debug_tsrc, slots_19.io.out_uop.debug_tsrc \n connect issue_slots[19].out_uop.debug_fsrc, slots_19.io.out_uop.debug_fsrc \n connect issue_slots[19].out_uop.bp_xcpt_if, slots_19.io.out_uop.bp_xcpt_if \n connect issue_slots[19].out_uop.bp_debug_if, slots_19.io.out_uop.bp_debug_if \n connect issue_slots[19].out_uop.xcpt_ma_if, slots_19.io.out_uop.xcpt_ma_if \n connect issue_slots[19].out_uop.xcpt_ae_if, slots_19.io.out_uop.xcpt_ae_if \n connect issue_slots[19].out_uop.xcpt_pf_if, slots_19.io.out_uop.xcpt_pf_if \n connect issue_slots[19].out_uop.fp_typ, slots_19.io.out_uop.fp_typ \n connect issue_slots[19].out_uop.fp_rm, slots_19.io.out_uop.fp_rm \n connect issue_slots[19].out_uop.fp_val, slots_19.io.out_uop.fp_val \n connect issue_slots[19].out_uop.fcn_op, slots_19.io.out_uop.fcn_op \n connect issue_slots[19].out_uop.fcn_dw, slots_19.io.out_uop.fcn_dw \n connect issue_slots[19].out_uop.frs3_en, slots_19.io.out_uop.frs3_en \n connect issue_slots[19].out_uop.lrs2_rtype, slots_19.io.out_uop.lrs2_rtype \n connect issue_slots[19].out_uop.lrs1_rtype, slots_19.io.out_uop.lrs1_rtype \n connect issue_slots[19].out_uop.dst_rtype, slots_19.io.out_uop.dst_rtype \n connect issue_slots[19].out_uop.lrs3, slots_19.io.out_uop.lrs3 \n connect issue_slots[19].out_uop.lrs2, slots_19.io.out_uop.lrs2 \n connect issue_slots[19].out_uop.lrs1, slots_19.io.out_uop.lrs1 \n connect issue_slots[19].out_uop.ldst, slots_19.io.out_uop.ldst \n connect issue_slots[19].out_uop.ldst_is_rs1, slots_19.io.out_uop.ldst_is_rs1 \n connect issue_slots[19].out_uop.csr_cmd, slots_19.io.out_uop.csr_cmd \n connect issue_slots[19].out_uop.flush_on_commit, slots_19.io.out_uop.flush_on_commit \n connect issue_slots[19].out_uop.is_unique, slots_19.io.out_uop.is_unique \n connect issue_slots[19].out_uop.uses_stq, slots_19.io.out_uop.uses_stq \n connect issue_slots[19].out_uop.uses_ldq, slots_19.io.out_uop.uses_ldq \n connect issue_slots[19].out_uop.mem_signed, slots_19.io.out_uop.mem_signed \n connect issue_slots[19].out_uop.mem_size, slots_19.io.out_uop.mem_size \n connect issue_slots[19].out_uop.mem_cmd, slots_19.io.out_uop.mem_cmd \n connect issue_slots[19].out_uop.exc_cause, slots_19.io.out_uop.exc_cause \n connect issue_slots[19].out_uop.exception, slots_19.io.out_uop.exception \n connect issue_slots[19].out_uop.stale_pdst, slots_19.io.out_uop.stale_pdst \n connect issue_slots[19].out_uop.ppred_busy, slots_19.io.out_uop.ppred_busy \n connect issue_slots[19].out_uop.prs3_busy, slots_19.io.out_uop.prs3_busy \n connect issue_slots[19].out_uop.prs2_busy, slots_19.io.out_uop.prs2_busy \n connect issue_slots[19].out_uop.prs1_busy, slots_19.io.out_uop.prs1_busy \n connect issue_slots[19].out_uop.ppred, slots_19.io.out_uop.ppred \n connect issue_slots[19].out_uop.prs3, slots_19.io.out_uop.prs3 \n connect issue_slots[19].out_uop.prs2, slots_19.io.out_uop.prs2 \n connect issue_slots[19].out_uop.prs1, slots_19.io.out_uop.prs1 \n connect issue_slots[19].out_uop.pdst, slots_19.io.out_uop.pdst \n connect issue_slots[19].out_uop.rxq_idx, slots_19.io.out_uop.rxq_idx \n connect issue_slots[19].out_uop.stq_idx, slots_19.io.out_uop.stq_idx \n connect issue_slots[19].out_uop.ldq_idx, slots_19.io.out_uop.ldq_idx \n connect issue_slots[19].out_uop.rob_idx, slots_19.io.out_uop.rob_idx \n connect issue_slots[19].out_uop.fp_ctrl.vec, slots_19.io.out_uop.fp_ctrl.vec \n connect issue_slots[19].out_uop.fp_ctrl.wflags, slots_19.io.out_uop.fp_ctrl.wflags \n connect issue_slots[19].out_uop.fp_ctrl.sqrt, slots_19.io.out_uop.fp_ctrl.sqrt \n connect issue_slots[19].out_uop.fp_ctrl.div, slots_19.io.out_uop.fp_ctrl.div \n connect issue_slots[19].out_uop.fp_ctrl.fma, slots_19.io.out_uop.fp_ctrl.fma \n connect issue_slots[19].out_uop.fp_ctrl.fastpipe, slots_19.io.out_uop.fp_ctrl.fastpipe \n connect issue_slots[19].out_uop.fp_ctrl.toint, slots_19.io.out_uop.fp_ctrl.toint \n connect issue_slots[19].out_uop.fp_ctrl.fromint, slots_19.io.out_uop.fp_ctrl.fromint \n connect issue_slots[19].out_uop.fp_ctrl.typeTagOut, slots_19.io.out_uop.fp_ctrl.typeTagOut \n connect issue_slots[19].out_uop.fp_ctrl.typeTagIn, slots_19.io.out_uop.fp_ctrl.typeTagIn \n connect issue_slots[19].out_uop.fp_ctrl.swap23, slots_19.io.out_uop.fp_ctrl.swap23 \n connect issue_slots[19].out_uop.fp_ctrl.swap12, slots_19.io.out_uop.fp_ctrl.swap12 \n connect issue_slots[19].out_uop.fp_ctrl.ren3, slots_19.io.out_uop.fp_ctrl.ren3 \n connect issue_slots[19].out_uop.fp_ctrl.ren2, slots_19.io.out_uop.fp_ctrl.ren2 \n connect issue_slots[19].out_uop.fp_ctrl.ren1, slots_19.io.out_uop.fp_ctrl.ren1 \n connect issue_slots[19].out_uop.fp_ctrl.wen, slots_19.io.out_uop.fp_ctrl.wen \n connect issue_slots[19].out_uop.fp_ctrl.ldst, slots_19.io.out_uop.fp_ctrl.ldst \n connect issue_slots[19].out_uop.op2_sel, slots_19.io.out_uop.op2_sel \n connect issue_slots[19].out_uop.op1_sel, slots_19.io.out_uop.op1_sel \n connect issue_slots[19].out_uop.imm_packed, slots_19.io.out_uop.imm_packed \n connect issue_slots[19].out_uop.pimm, slots_19.io.out_uop.pimm \n connect issue_slots[19].out_uop.imm_sel, slots_19.io.out_uop.imm_sel \n connect issue_slots[19].out_uop.imm_rename, slots_19.io.out_uop.imm_rename \n connect issue_slots[19].out_uop.taken, slots_19.io.out_uop.taken \n connect issue_slots[19].out_uop.pc_lob, slots_19.io.out_uop.pc_lob \n connect issue_slots[19].out_uop.edge_inst, slots_19.io.out_uop.edge_inst \n connect issue_slots[19].out_uop.ftq_idx, slots_19.io.out_uop.ftq_idx \n connect issue_slots[19].out_uop.is_mov, slots_19.io.out_uop.is_mov \n connect issue_slots[19].out_uop.is_rocc, slots_19.io.out_uop.is_rocc \n connect issue_slots[19].out_uop.is_sys_pc2epc, slots_19.io.out_uop.is_sys_pc2epc \n connect issue_slots[19].out_uop.is_eret, slots_19.io.out_uop.is_eret \n connect issue_slots[19].out_uop.is_amo, slots_19.io.out_uop.is_amo \n connect issue_slots[19].out_uop.is_sfence, slots_19.io.out_uop.is_sfence \n connect issue_slots[19].out_uop.is_fencei, slots_19.io.out_uop.is_fencei \n connect issue_slots[19].out_uop.is_fence, slots_19.io.out_uop.is_fence \n connect issue_slots[19].out_uop.is_sfb, slots_19.io.out_uop.is_sfb \n connect issue_slots[19].out_uop.br_type, slots_19.io.out_uop.br_type \n connect issue_slots[19].out_uop.br_tag, slots_19.io.out_uop.br_tag \n connect issue_slots[19].out_uop.br_mask, slots_19.io.out_uop.br_mask \n connect issue_slots[19].out_uop.dis_col_sel, slots_19.io.out_uop.dis_col_sel \n connect issue_slots[19].out_uop.iw_p3_bypass_hint, slots_19.io.out_uop.iw_p3_bypass_hint \n connect issue_slots[19].out_uop.iw_p2_bypass_hint, slots_19.io.out_uop.iw_p2_bypass_hint \n connect issue_slots[19].out_uop.iw_p1_bypass_hint, slots_19.io.out_uop.iw_p1_bypass_hint \n connect issue_slots[19].out_uop.iw_p2_speculative_child, slots_19.io.out_uop.iw_p2_speculative_child \n connect issue_slots[19].out_uop.iw_p1_speculative_child, slots_19.io.out_uop.iw_p1_speculative_child \n connect issue_slots[19].out_uop.iw_issued_partial_dgen, slots_19.io.out_uop.iw_issued_partial_dgen \n connect issue_slots[19].out_uop.iw_issued_partial_agen, slots_19.io.out_uop.iw_issued_partial_agen \n connect issue_slots[19].out_uop.iw_issued, slots_19.io.out_uop.iw_issued \n connect issue_slots[19].out_uop.fu_code[0], slots_19.io.out_uop.fu_code[0] \n connect issue_slots[19].out_uop.fu_code[1], slots_19.io.out_uop.fu_code[1] \n connect issue_slots[19].out_uop.fu_code[2], slots_19.io.out_uop.fu_code[2] \n connect issue_slots[19].out_uop.fu_code[3], slots_19.io.out_uop.fu_code[3] \n connect issue_slots[19].out_uop.fu_code[4], slots_19.io.out_uop.fu_code[4] \n connect issue_slots[19].out_uop.fu_code[5], slots_19.io.out_uop.fu_code[5] \n connect issue_slots[19].out_uop.fu_code[6], slots_19.io.out_uop.fu_code[6] \n connect issue_slots[19].out_uop.fu_code[7], slots_19.io.out_uop.fu_code[7] \n connect issue_slots[19].out_uop.fu_code[8], slots_19.io.out_uop.fu_code[8] \n connect issue_slots[19].out_uop.fu_code[9], slots_19.io.out_uop.fu_code[9] \n connect issue_slots[19].out_uop.iq_type[0], slots_19.io.out_uop.iq_type[0] \n connect issue_slots[19].out_uop.iq_type[1], slots_19.io.out_uop.iq_type[1] \n connect issue_slots[19].out_uop.iq_type[2], slots_19.io.out_uop.iq_type[2] \n connect issue_slots[19].out_uop.iq_type[3], slots_19.io.out_uop.iq_type[3] \n connect issue_slots[19].out_uop.debug_pc, slots_19.io.out_uop.debug_pc \n connect issue_slots[19].out_uop.is_rvc, slots_19.io.out_uop.is_rvc \n connect issue_slots[19].out_uop.debug_inst, slots_19.io.out_uop.debug_inst \n connect issue_slots[19].out_uop.inst, slots_19.io.out_uop.inst \n connect slots_19.io.in_uop.bits.debug_tsrc, issue_slots[19].in_uop.bits.debug_tsrc \n connect slots_19.io.in_uop.bits.debug_fsrc, issue_slots[19].in_uop.bits.debug_fsrc \n connect slots_19.io.in_uop.bits.bp_xcpt_if, issue_slots[19].in_uop.bits.bp_xcpt_if \n connect slots_19.io.in_uop.bits.bp_debug_if, issue_slots[19].in_uop.bits.bp_debug_if \n connect slots_19.io.in_uop.bits.xcpt_ma_if, issue_slots[19].in_uop.bits.xcpt_ma_if \n connect slots_19.io.in_uop.bits.xcpt_ae_if, issue_slots[19].in_uop.bits.xcpt_ae_if \n connect slots_19.io.in_uop.bits.xcpt_pf_if, issue_slots[19].in_uop.bits.xcpt_pf_if \n connect slots_19.io.in_uop.bits.fp_typ, issue_slots[19].in_uop.bits.fp_typ \n connect slots_19.io.in_uop.bits.fp_rm, issue_slots[19].in_uop.bits.fp_rm \n connect slots_19.io.in_uop.bits.fp_val, issue_slots[19].in_uop.bits.fp_val \n connect slots_19.io.in_uop.bits.fcn_op, issue_slots[19].in_uop.bits.fcn_op \n connect slots_19.io.in_uop.bits.fcn_dw, issue_slots[19].in_uop.bits.fcn_dw \n connect slots_19.io.in_uop.bits.frs3_en, issue_slots[19].in_uop.bits.frs3_en \n connect slots_19.io.in_uop.bits.lrs2_rtype, issue_slots[19].in_uop.bits.lrs2_rtype \n connect slots_19.io.in_uop.bits.lrs1_rtype, issue_slots[19].in_uop.bits.lrs1_rtype \n connect slots_19.io.in_uop.bits.dst_rtype, issue_slots[19].in_uop.bits.dst_rtype \n connect slots_19.io.in_uop.bits.lrs3, issue_slots[19].in_uop.bits.lrs3 \n connect slots_19.io.in_uop.bits.lrs2, issue_slots[19].in_uop.bits.lrs2 \n connect slots_19.io.in_uop.bits.lrs1, issue_slots[19].in_uop.bits.lrs1 \n connect slots_19.io.in_uop.bits.ldst, issue_slots[19].in_uop.bits.ldst \n connect slots_19.io.in_uop.bits.ldst_is_rs1, issue_slots[19].in_uop.bits.ldst_is_rs1 \n connect slots_19.io.in_uop.bits.csr_cmd, issue_slots[19].in_uop.bits.csr_cmd \n connect slots_19.io.in_uop.bits.flush_on_commit, issue_slots[19].in_uop.bits.flush_on_commit \n connect slots_19.io.in_uop.bits.is_unique, issue_slots[19].in_uop.bits.is_unique \n connect slots_19.io.in_uop.bits.uses_stq, issue_slots[19].in_uop.bits.uses_stq \n connect slots_19.io.in_uop.bits.uses_ldq, issue_slots[19].in_uop.bits.uses_ldq \n connect slots_19.io.in_uop.bits.mem_signed, issue_slots[19].in_uop.bits.mem_signed \n connect slots_19.io.in_uop.bits.mem_size, issue_slots[19].in_uop.bits.mem_size \n connect slots_19.io.in_uop.bits.mem_cmd, issue_slots[19].in_uop.bits.mem_cmd \n connect slots_19.io.in_uop.bits.exc_cause, issue_slots[19].in_uop.bits.exc_cause \n connect slots_19.io.in_uop.bits.exception, issue_slots[19].in_uop.bits.exception \n connect slots_19.io.in_uop.bits.stale_pdst, issue_slots[19].in_uop.bits.stale_pdst \n connect slots_19.io.in_uop.bits.ppred_busy, issue_slots[19].in_uop.bits.ppred_busy \n connect slots_19.io.in_uop.bits.prs3_busy, issue_slots[19].in_uop.bits.prs3_busy \n connect slots_19.io.in_uop.bits.prs2_busy, issue_slots[19].in_uop.bits.prs2_busy \n connect slots_19.io.in_uop.bits.prs1_busy, issue_slots[19].in_uop.bits.prs1_busy \n connect slots_19.io.in_uop.bits.ppred, issue_slots[19].in_uop.bits.ppred \n connect slots_19.io.in_uop.bits.prs3, issue_slots[19].in_uop.bits.prs3 \n connect slots_19.io.in_uop.bits.prs2, issue_slots[19].in_uop.bits.prs2 \n connect slots_19.io.in_uop.bits.prs1, issue_slots[19].in_uop.bits.prs1 \n connect slots_19.io.in_uop.bits.pdst, issue_slots[19].in_uop.bits.pdst \n connect slots_19.io.in_uop.bits.rxq_idx, issue_slots[19].in_uop.bits.rxq_idx \n connect slots_19.io.in_uop.bits.stq_idx, issue_slots[19].in_uop.bits.stq_idx \n connect slots_19.io.in_uop.bits.ldq_idx, issue_slots[19].in_uop.bits.ldq_idx \n connect slots_19.io.in_uop.bits.rob_idx, issue_slots[19].in_uop.bits.rob_idx \n connect slots_19.io.in_uop.bits.fp_ctrl.vec, issue_slots[19].in_uop.bits.fp_ctrl.vec \n connect slots_19.io.in_uop.bits.fp_ctrl.wflags, issue_slots[19].in_uop.bits.fp_ctrl.wflags \n connect slots_19.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[19].in_uop.bits.fp_ctrl.sqrt \n connect slots_19.io.in_uop.bits.fp_ctrl.div, issue_slots[19].in_uop.bits.fp_ctrl.div \n connect slots_19.io.in_uop.bits.fp_ctrl.fma, issue_slots[19].in_uop.bits.fp_ctrl.fma \n connect slots_19.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[19].in_uop.bits.fp_ctrl.fastpipe \n connect slots_19.io.in_uop.bits.fp_ctrl.toint, issue_slots[19].in_uop.bits.fp_ctrl.toint \n connect slots_19.io.in_uop.bits.fp_ctrl.fromint, issue_slots[19].in_uop.bits.fp_ctrl.fromint \n connect slots_19.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[19].in_uop.bits.fp_ctrl.typeTagOut \n connect slots_19.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[19].in_uop.bits.fp_ctrl.typeTagIn \n connect slots_19.io.in_uop.bits.fp_ctrl.swap23, issue_slots[19].in_uop.bits.fp_ctrl.swap23 \n connect slots_19.io.in_uop.bits.fp_ctrl.swap12, issue_slots[19].in_uop.bits.fp_ctrl.swap12 \n connect slots_19.io.in_uop.bits.fp_ctrl.ren3, issue_slots[19].in_uop.bits.fp_ctrl.ren3 \n connect slots_19.io.in_uop.bits.fp_ctrl.ren2, issue_slots[19].in_uop.bits.fp_ctrl.ren2 \n connect slots_19.io.in_uop.bits.fp_ctrl.ren1, issue_slots[19].in_uop.bits.fp_ctrl.ren1 \n connect slots_19.io.in_uop.bits.fp_ctrl.wen, issue_slots[19].in_uop.bits.fp_ctrl.wen \n connect slots_19.io.in_uop.bits.fp_ctrl.ldst, issue_slots[19].in_uop.bits.fp_ctrl.ldst \n connect slots_19.io.in_uop.bits.op2_sel, issue_slots[19].in_uop.bits.op2_sel \n connect slots_19.io.in_uop.bits.op1_sel, issue_slots[19].in_uop.bits.op1_sel \n connect slots_19.io.in_uop.bits.imm_packed, issue_slots[19].in_uop.bits.imm_packed \n connect slots_19.io.in_uop.bits.pimm, issue_slots[19].in_uop.bits.pimm \n connect slots_19.io.in_uop.bits.imm_sel, issue_slots[19].in_uop.bits.imm_sel \n connect slots_19.io.in_uop.bits.imm_rename, issue_slots[19].in_uop.bits.imm_rename \n connect slots_19.io.in_uop.bits.taken, issue_slots[19].in_uop.bits.taken \n connect slots_19.io.in_uop.bits.pc_lob, issue_slots[19].in_uop.bits.pc_lob \n connect slots_19.io.in_uop.bits.edge_inst, issue_slots[19].in_uop.bits.edge_inst \n connect slots_19.io.in_uop.bits.ftq_idx, issue_slots[19].in_uop.bits.ftq_idx \n connect slots_19.io.in_uop.bits.is_mov, issue_slots[19].in_uop.bits.is_mov \n connect slots_19.io.in_uop.bits.is_rocc, issue_slots[19].in_uop.bits.is_rocc \n connect slots_19.io.in_uop.bits.is_sys_pc2epc, issue_slots[19].in_uop.bits.is_sys_pc2epc \n connect slots_19.io.in_uop.bits.is_eret, issue_slots[19].in_uop.bits.is_eret \n connect slots_19.io.in_uop.bits.is_amo, issue_slots[19].in_uop.bits.is_amo \n connect slots_19.io.in_uop.bits.is_sfence, issue_slots[19].in_uop.bits.is_sfence \n connect slots_19.io.in_uop.bits.is_fencei, issue_slots[19].in_uop.bits.is_fencei \n connect slots_19.io.in_uop.bits.is_fence, issue_slots[19].in_uop.bits.is_fence \n connect slots_19.io.in_uop.bits.is_sfb, issue_slots[19].in_uop.bits.is_sfb \n connect slots_19.io.in_uop.bits.br_type, issue_slots[19].in_uop.bits.br_type \n connect slots_19.io.in_uop.bits.br_tag, issue_slots[19].in_uop.bits.br_tag \n connect slots_19.io.in_uop.bits.br_mask, issue_slots[19].in_uop.bits.br_mask \n connect slots_19.io.in_uop.bits.dis_col_sel, issue_slots[19].in_uop.bits.dis_col_sel \n connect slots_19.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[19].in_uop.bits.iw_p3_bypass_hint \n connect slots_19.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[19].in_uop.bits.iw_p2_bypass_hint \n connect slots_19.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[19].in_uop.bits.iw_p1_bypass_hint \n connect slots_19.io.in_uop.bits.iw_p2_speculative_child, issue_slots[19].in_uop.bits.iw_p2_speculative_child \n connect slots_19.io.in_uop.bits.iw_p1_speculative_child, issue_slots[19].in_uop.bits.iw_p1_speculative_child \n connect slots_19.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[19].in_uop.bits.iw_issued_partial_dgen \n connect slots_19.io.in_uop.bits.iw_issued_partial_agen, issue_slots[19].in_uop.bits.iw_issued_partial_agen \n connect slots_19.io.in_uop.bits.iw_issued, issue_slots[19].in_uop.bits.iw_issued \n connect slots_19.io.in_uop.bits.fu_code[0], issue_slots[19].in_uop.bits.fu_code[0] \n connect slots_19.io.in_uop.bits.fu_code[1], issue_slots[19].in_uop.bits.fu_code[1] \n connect slots_19.io.in_uop.bits.fu_code[2], issue_slots[19].in_uop.bits.fu_code[2] \n connect slots_19.io.in_uop.bits.fu_code[3], issue_slots[19].in_uop.bits.fu_code[3] \n connect slots_19.io.in_uop.bits.fu_code[4], issue_slots[19].in_uop.bits.fu_code[4] \n connect slots_19.io.in_uop.bits.fu_code[5], issue_slots[19].in_uop.bits.fu_code[5] \n connect slots_19.io.in_uop.bits.fu_code[6], issue_slots[19].in_uop.bits.fu_code[6] \n connect slots_19.io.in_uop.bits.fu_code[7], issue_slots[19].in_uop.bits.fu_code[7] \n connect slots_19.io.in_uop.bits.fu_code[8], issue_slots[19].in_uop.bits.fu_code[8] \n connect slots_19.io.in_uop.bits.fu_code[9], issue_slots[19].in_uop.bits.fu_code[9] \n connect slots_19.io.in_uop.bits.iq_type[0], issue_slots[19].in_uop.bits.iq_type[0] \n connect slots_19.io.in_uop.bits.iq_type[1], issue_slots[19].in_uop.bits.iq_type[1] \n connect slots_19.io.in_uop.bits.iq_type[2], issue_slots[19].in_uop.bits.iq_type[2] \n connect slots_19.io.in_uop.bits.iq_type[3], issue_slots[19].in_uop.bits.iq_type[3] \n connect slots_19.io.in_uop.bits.debug_pc, issue_slots[19].in_uop.bits.debug_pc \n connect slots_19.io.in_uop.bits.is_rvc, issue_slots[19].in_uop.bits.is_rvc \n connect slots_19.io.in_uop.bits.debug_inst, issue_slots[19].in_uop.bits.debug_inst \n connect slots_19.io.in_uop.bits.inst, issue_slots[19].in_uop.bits.inst \n connect slots_19.io.in_uop.valid, issue_slots[19].in_uop.valid \n connect issue_slots[19].iss_uop.debug_tsrc, slots_19.io.iss_uop.debug_tsrc \n connect issue_slots[19].iss_uop.debug_fsrc, slots_19.io.iss_uop.debug_fsrc \n connect issue_slots[19].iss_uop.bp_xcpt_if, slots_19.io.iss_uop.bp_xcpt_if \n connect issue_slots[19].iss_uop.bp_debug_if, slots_19.io.iss_uop.bp_debug_if \n connect issue_slots[19].iss_uop.xcpt_ma_if, slots_19.io.iss_uop.xcpt_ma_if \n connect issue_slots[19].iss_uop.xcpt_ae_if, slots_19.io.iss_uop.xcpt_ae_if \n connect issue_slots[19].iss_uop.xcpt_pf_if, slots_19.io.iss_uop.xcpt_pf_if \n connect issue_slots[19].iss_uop.fp_typ, slots_19.io.iss_uop.fp_typ \n connect issue_slots[19].iss_uop.fp_rm, slots_19.io.iss_uop.fp_rm \n connect issue_slots[19].iss_uop.fp_val, slots_19.io.iss_uop.fp_val \n connect issue_slots[19].iss_uop.fcn_op, slots_19.io.iss_uop.fcn_op \n connect issue_slots[19].iss_uop.fcn_dw, slots_19.io.iss_uop.fcn_dw \n connect issue_slots[19].iss_uop.frs3_en, slots_19.io.iss_uop.frs3_en \n connect issue_slots[19].iss_uop.lrs2_rtype, slots_19.io.iss_uop.lrs2_rtype \n connect issue_slots[19].iss_uop.lrs1_rtype, slots_19.io.iss_uop.lrs1_rtype \n connect issue_slots[19].iss_uop.dst_rtype, slots_19.io.iss_uop.dst_rtype \n connect issue_slots[19].iss_uop.lrs3, slots_19.io.iss_uop.lrs3 \n connect issue_slots[19].iss_uop.lrs2, slots_19.io.iss_uop.lrs2 \n connect issue_slots[19].iss_uop.lrs1, slots_19.io.iss_uop.lrs1 \n connect issue_slots[19].iss_uop.ldst, slots_19.io.iss_uop.ldst \n connect issue_slots[19].iss_uop.ldst_is_rs1, slots_19.io.iss_uop.ldst_is_rs1 \n connect issue_slots[19].iss_uop.csr_cmd, slots_19.io.iss_uop.csr_cmd \n connect issue_slots[19].iss_uop.flush_on_commit, slots_19.io.iss_uop.flush_on_commit \n connect issue_slots[19].iss_uop.is_unique, slots_19.io.iss_uop.is_unique \n connect issue_slots[19].iss_uop.uses_stq, slots_19.io.iss_uop.uses_stq \n connect issue_slots[19].iss_uop.uses_ldq, slots_19.io.iss_uop.uses_ldq \n connect issue_slots[19].iss_uop.mem_signed, slots_19.io.iss_uop.mem_signed \n connect issue_slots[19].iss_uop.mem_size, slots_19.io.iss_uop.mem_size \n connect issue_slots[19].iss_uop.mem_cmd, slots_19.io.iss_uop.mem_cmd \n connect issue_slots[19].iss_uop.exc_cause, slots_19.io.iss_uop.exc_cause \n connect issue_slots[19].iss_uop.exception, slots_19.io.iss_uop.exception \n connect issue_slots[19].iss_uop.stale_pdst, slots_19.io.iss_uop.stale_pdst \n connect issue_slots[19].iss_uop.ppred_busy, slots_19.io.iss_uop.ppred_busy \n connect issue_slots[19].iss_uop.prs3_busy, slots_19.io.iss_uop.prs3_busy \n connect issue_slots[19].iss_uop.prs2_busy, slots_19.io.iss_uop.prs2_busy \n connect issue_slots[19].iss_uop.prs1_busy, slots_19.io.iss_uop.prs1_busy \n connect issue_slots[19].iss_uop.ppred, slots_19.io.iss_uop.ppred \n connect issue_slots[19].iss_uop.prs3, slots_19.io.iss_uop.prs3 \n connect issue_slots[19].iss_uop.prs2, slots_19.io.iss_uop.prs2 \n connect issue_slots[19].iss_uop.prs1, slots_19.io.iss_uop.prs1 \n connect issue_slots[19].iss_uop.pdst, slots_19.io.iss_uop.pdst \n connect issue_slots[19].iss_uop.rxq_idx, slots_19.io.iss_uop.rxq_idx \n connect issue_slots[19].iss_uop.stq_idx, slots_19.io.iss_uop.stq_idx \n connect issue_slots[19].iss_uop.ldq_idx, slots_19.io.iss_uop.ldq_idx \n connect issue_slots[19].iss_uop.rob_idx, slots_19.io.iss_uop.rob_idx \n connect issue_slots[19].iss_uop.fp_ctrl.vec, slots_19.io.iss_uop.fp_ctrl.vec \n connect issue_slots[19].iss_uop.fp_ctrl.wflags, slots_19.io.iss_uop.fp_ctrl.wflags \n connect issue_slots[19].iss_uop.fp_ctrl.sqrt, slots_19.io.iss_uop.fp_ctrl.sqrt \n connect issue_slots[19].iss_uop.fp_ctrl.div, slots_19.io.iss_uop.fp_ctrl.div \n connect issue_slots[19].iss_uop.fp_ctrl.fma, slots_19.io.iss_uop.fp_ctrl.fma \n connect issue_slots[19].iss_uop.fp_ctrl.fastpipe, slots_19.io.iss_uop.fp_ctrl.fastpipe \n connect issue_slots[19].iss_uop.fp_ctrl.toint, slots_19.io.iss_uop.fp_ctrl.toint \n connect issue_slots[19].iss_uop.fp_ctrl.fromint, slots_19.io.iss_uop.fp_ctrl.fromint \n connect issue_slots[19].iss_uop.fp_ctrl.typeTagOut, slots_19.io.iss_uop.fp_ctrl.typeTagOut \n connect issue_slots[19].iss_uop.fp_ctrl.typeTagIn, slots_19.io.iss_uop.fp_ctrl.typeTagIn \n connect issue_slots[19].iss_uop.fp_ctrl.swap23, slots_19.io.iss_uop.fp_ctrl.swap23 \n connect issue_slots[19].iss_uop.fp_ctrl.swap12, slots_19.io.iss_uop.fp_ctrl.swap12 \n connect issue_slots[19].iss_uop.fp_ctrl.ren3, slots_19.io.iss_uop.fp_ctrl.ren3 \n connect issue_slots[19].iss_uop.fp_ctrl.ren2, slots_19.io.iss_uop.fp_ctrl.ren2 \n connect issue_slots[19].iss_uop.fp_ctrl.ren1, slots_19.io.iss_uop.fp_ctrl.ren1 \n connect issue_slots[19].iss_uop.fp_ctrl.wen, slots_19.io.iss_uop.fp_ctrl.wen \n connect issue_slots[19].iss_uop.fp_ctrl.ldst, slots_19.io.iss_uop.fp_ctrl.ldst \n connect issue_slots[19].iss_uop.op2_sel, slots_19.io.iss_uop.op2_sel \n connect issue_slots[19].iss_uop.op1_sel, slots_19.io.iss_uop.op1_sel \n connect issue_slots[19].iss_uop.imm_packed, slots_19.io.iss_uop.imm_packed \n connect issue_slots[19].iss_uop.pimm, slots_19.io.iss_uop.pimm \n connect issue_slots[19].iss_uop.imm_sel, slots_19.io.iss_uop.imm_sel \n connect issue_slots[19].iss_uop.imm_rename, slots_19.io.iss_uop.imm_rename \n connect issue_slots[19].iss_uop.taken, slots_19.io.iss_uop.taken \n connect issue_slots[19].iss_uop.pc_lob, slots_19.io.iss_uop.pc_lob \n connect issue_slots[19].iss_uop.edge_inst, slots_19.io.iss_uop.edge_inst \n connect issue_slots[19].iss_uop.ftq_idx, slots_19.io.iss_uop.ftq_idx \n connect issue_slots[19].iss_uop.is_mov, slots_19.io.iss_uop.is_mov \n connect issue_slots[19].iss_uop.is_rocc, slots_19.io.iss_uop.is_rocc \n connect issue_slots[19].iss_uop.is_sys_pc2epc, slots_19.io.iss_uop.is_sys_pc2epc \n connect issue_slots[19].iss_uop.is_eret, slots_19.io.iss_uop.is_eret \n connect issue_slots[19].iss_uop.is_amo, slots_19.io.iss_uop.is_amo \n connect issue_slots[19].iss_uop.is_sfence, slots_19.io.iss_uop.is_sfence \n connect issue_slots[19].iss_uop.is_fencei, slots_19.io.iss_uop.is_fencei \n connect issue_slots[19].iss_uop.is_fence, slots_19.io.iss_uop.is_fence \n connect issue_slots[19].iss_uop.is_sfb, slots_19.io.iss_uop.is_sfb \n connect issue_slots[19].iss_uop.br_type, slots_19.io.iss_uop.br_type \n connect issue_slots[19].iss_uop.br_tag, slots_19.io.iss_uop.br_tag \n connect issue_slots[19].iss_uop.br_mask, slots_19.io.iss_uop.br_mask \n connect issue_slots[19].iss_uop.dis_col_sel, slots_19.io.iss_uop.dis_col_sel \n connect issue_slots[19].iss_uop.iw_p3_bypass_hint, slots_19.io.iss_uop.iw_p3_bypass_hint \n connect issue_slots[19].iss_uop.iw_p2_bypass_hint, slots_19.io.iss_uop.iw_p2_bypass_hint \n connect issue_slots[19].iss_uop.iw_p1_bypass_hint, slots_19.io.iss_uop.iw_p1_bypass_hint \n connect issue_slots[19].iss_uop.iw_p2_speculative_child, slots_19.io.iss_uop.iw_p2_speculative_child \n connect issue_slots[19].iss_uop.iw_p1_speculative_child, slots_19.io.iss_uop.iw_p1_speculative_child \n connect issue_slots[19].iss_uop.iw_issued_partial_dgen, slots_19.io.iss_uop.iw_issued_partial_dgen \n connect issue_slots[19].iss_uop.iw_issued_partial_agen, slots_19.io.iss_uop.iw_issued_partial_agen \n connect issue_slots[19].iss_uop.iw_issued, slots_19.io.iss_uop.iw_issued \n connect issue_slots[19].iss_uop.fu_code[0], slots_19.io.iss_uop.fu_code[0] \n connect issue_slots[19].iss_uop.fu_code[1], slots_19.io.iss_uop.fu_code[1] \n connect issue_slots[19].iss_uop.fu_code[2], slots_19.io.iss_uop.fu_code[2] \n connect issue_slots[19].iss_uop.fu_code[3], slots_19.io.iss_uop.fu_code[3] \n connect issue_slots[19].iss_uop.fu_code[4], slots_19.io.iss_uop.fu_code[4] \n connect issue_slots[19].iss_uop.fu_code[5], slots_19.io.iss_uop.fu_code[5] \n connect issue_slots[19].iss_uop.fu_code[6], slots_19.io.iss_uop.fu_code[6] \n connect issue_slots[19].iss_uop.fu_code[7], slots_19.io.iss_uop.fu_code[7] \n connect issue_slots[19].iss_uop.fu_code[8], slots_19.io.iss_uop.fu_code[8] \n connect issue_slots[19].iss_uop.fu_code[9], slots_19.io.iss_uop.fu_code[9] \n connect issue_slots[19].iss_uop.iq_type[0], slots_19.io.iss_uop.iq_type[0] \n connect issue_slots[19].iss_uop.iq_type[1], slots_19.io.iss_uop.iq_type[1] \n connect issue_slots[19].iss_uop.iq_type[2], slots_19.io.iss_uop.iq_type[2] \n connect issue_slots[19].iss_uop.iq_type[3], slots_19.io.iss_uop.iq_type[3] \n connect issue_slots[19].iss_uop.debug_pc, slots_19.io.iss_uop.debug_pc \n connect issue_slots[19].iss_uop.is_rvc, slots_19.io.iss_uop.is_rvc \n connect issue_slots[19].iss_uop.debug_inst, slots_19.io.iss_uop.debug_inst \n connect issue_slots[19].iss_uop.inst, slots_19.io.iss_uop.inst \n connect slots_19.io.grant, issue_slots[19].grant \n connect issue_slots[19].request, slots_19.io.request \n connect issue_slots[19].will_be_valid, slots_19.io.will_be_valid \n connect issue_slots[19].valid, slots_19.io.valid \n connect issue_slots[0].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy \n connect issue_slots[0].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask \n connect issue_slots[0].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable \n connect issue_slots[0].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc \n connect issue_slots[0].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc \n connect issue_slots[0].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if \n connect issue_slots[0].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if \n connect issue_slots[0].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if \n connect issue_slots[0].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if \n connect issue_slots[0].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if \n connect issue_slots[0].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ \n connect issue_slots[0].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm \n connect issue_slots[0].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val \n connect issue_slots[0].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op \n connect issue_slots[0].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw \n connect issue_slots[0].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en \n connect issue_slots[0].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype \n connect issue_slots[0].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype \n connect issue_slots[0].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype \n connect issue_slots[0].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 \n connect issue_slots[0].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 \n connect issue_slots[0].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 \n connect issue_slots[0].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst \n connect issue_slots[0].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 \n connect issue_slots[0].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd \n connect issue_slots[0].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit \n connect issue_slots[0].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique \n connect issue_slots[0].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq \n connect issue_slots[0].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq \n connect issue_slots[0].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed \n connect issue_slots[0].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size \n connect issue_slots[0].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd \n connect issue_slots[0].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause \n connect issue_slots[0].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception \n connect issue_slots[0].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst \n connect issue_slots[0].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy \n connect issue_slots[0].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy \n connect issue_slots[0].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy \n connect issue_slots[0].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy \n connect issue_slots[0].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred \n connect issue_slots[0].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 \n connect issue_slots[0].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 \n connect issue_slots[0].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 \n connect issue_slots[0].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst \n connect issue_slots[0].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx \n connect issue_slots[0].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx \n connect issue_slots[0].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx \n connect issue_slots[0].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx \n connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec \n connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags \n connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt \n connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div \n connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma \n connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint \n connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint \n connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 \n connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 \n connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 \n connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 \n connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 \n connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen \n connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst \n connect issue_slots[0].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel \n connect issue_slots[0].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel \n connect issue_slots[0].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed \n connect issue_slots[0].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm \n connect issue_slots[0].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel \n connect issue_slots[0].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename \n connect issue_slots[0].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken \n connect issue_slots[0].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob \n connect issue_slots[0].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst \n connect issue_slots[0].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx \n connect issue_slots[0].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov \n connect issue_slots[0].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc \n connect issue_slots[0].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc \n connect issue_slots[0].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret \n connect issue_slots[0].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo \n connect issue_slots[0].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence \n connect issue_slots[0].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei \n connect issue_slots[0].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence \n connect issue_slots[0].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb \n connect issue_slots[0].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type \n connect issue_slots[0].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag \n connect issue_slots[0].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask \n connect issue_slots[0].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel \n connect issue_slots[0].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint \n connect issue_slots[0].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint \n connect issue_slots[0].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint \n connect issue_slots[0].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child \n connect issue_slots[0].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child \n connect issue_slots[0].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen \n connect issue_slots[0].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen \n connect issue_slots[0].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued \n connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] \n connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] \n connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] \n connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] \n connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] \n connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] \n connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] \n connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] \n connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] \n connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] \n connect issue_slots[0].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] \n connect issue_slots[0].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] \n connect issue_slots[0].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] \n connect issue_slots[0].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] \n connect issue_slots[0].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc \n connect issue_slots[0].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc \n connect issue_slots[0].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst \n connect issue_slots[0].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst \n connect issue_slots[0].wakeup_ports[0].valid, io.wakeup_ports[0].valid \n connect issue_slots[0].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy \n connect issue_slots[0].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask \n connect issue_slots[0].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable \n connect issue_slots[0].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc \n connect issue_slots[0].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc \n connect issue_slots[0].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if \n connect issue_slots[0].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if \n connect issue_slots[0].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if \n connect issue_slots[0].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if \n connect issue_slots[0].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if \n connect issue_slots[0].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ \n connect issue_slots[0].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm \n connect issue_slots[0].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val \n connect issue_slots[0].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op \n connect issue_slots[0].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw \n connect issue_slots[0].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en \n connect issue_slots[0].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype \n connect issue_slots[0].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype \n connect issue_slots[0].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype \n connect issue_slots[0].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 \n connect issue_slots[0].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 \n connect issue_slots[0].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 \n connect issue_slots[0].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst \n connect issue_slots[0].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 \n connect issue_slots[0].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd \n connect issue_slots[0].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit \n connect issue_slots[0].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique \n connect issue_slots[0].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq \n connect issue_slots[0].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq \n connect issue_slots[0].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed \n connect issue_slots[0].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size \n connect issue_slots[0].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd \n connect issue_slots[0].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause \n connect issue_slots[0].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception \n connect issue_slots[0].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst \n connect issue_slots[0].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy \n connect issue_slots[0].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy \n connect issue_slots[0].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy \n connect issue_slots[0].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy \n connect issue_slots[0].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred \n connect issue_slots[0].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 \n connect issue_slots[0].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 \n connect issue_slots[0].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 \n connect issue_slots[0].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst \n connect issue_slots[0].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx \n connect issue_slots[0].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx \n connect issue_slots[0].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx \n connect issue_slots[0].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx \n connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec \n connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags \n connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt \n connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div \n connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma \n connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint \n connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint \n connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 \n connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 \n connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 \n connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 \n connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 \n connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen \n connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst \n connect issue_slots[0].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel \n connect issue_slots[0].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel \n connect issue_slots[0].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed \n connect issue_slots[0].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm \n connect issue_slots[0].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel \n connect issue_slots[0].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename \n connect issue_slots[0].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken \n connect issue_slots[0].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob \n connect issue_slots[0].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst \n connect issue_slots[0].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx \n connect issue_slots[0].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov \n connect issue_slots[0].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc \n connect issue_slots[0].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc \n connect issue_slots[0].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret \n connect issue_slots[0].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo \n connect issue_slots[0].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence \n connect issue_slots[0].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei \n connect issue_slots[0].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence \n connect issue_slots[0].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb \n connect issue_slots[0].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type \n connect issue_slots[0].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag \n connect issue_slots[0].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask \n connect issue_slots[0].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel \n connect issue_slots[0].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint \n connect issue_slots[0].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint \n connect issue_slots[0].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint \n connect issue_slots[0].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child \n connect issue_slots[0].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child \n connect issue_slots[0].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen \n connect issue_slots[0].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen \n connect issue_slots[0].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued \n connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] \n connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] \n connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] \n connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] \n connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] \n connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] \n connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] \n connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] \n connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] \n connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] \n connect issue_slots[0].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] \n connect issue_slots[0].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] \n connect issue_slots[0].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] \n connect issue_slots[0].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] \n connect issue_slots[0].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc \n connect issue_slots[0].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc \n connect issue_slots[0].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst \n connect issue_slots[0].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst \n connect issue_slots[0].wakeup_ports[1].valid, io.wakeup_ports[1].valid \n connect issue_slots[0].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy \n connect issue_slots[0].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask \n connect issue_slots[0].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable \n connect issue_slots[0].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc \n connect issue_slots[0].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc \n connect issue_slots[0].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if \n connect issue_slots[0].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if \n connect issue_slots[0].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if \n connect issue_slots[0].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if \n connect issue_slots[0].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if \n connect issue_slots[0].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ \n connect issue_slots[0].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm \n connect issue_slots[0].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val \n connect issue_slots[0].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op \n connect issue_slots[0].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw \n connect issue_slots[0].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en \n connect issue_slots[0].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype \n connect issue_slots[0].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype \n connect issue_slots[0].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype \n connect issue_slots[0].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 \n connect issue_slots[0].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 \n connect issue_slots[0].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 \n connect issue_slots[0].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst \n connect issue_slots[0].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 \n connect issue_slots[0].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd \n connect issue_slots[0].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit \n connect issue_slots[0].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique \n connect issue_slots[0].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq \n connect issue_slots[0].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq \n connect issue_slots[0].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed \n connect issue_slots[0].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size \n connect issue_slots[0].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd \n connect issue_slots[0].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause \n connect issue_slots[0].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception \n connect issue_slots[0].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst \n connect issue_slots[0].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy \n connect issue_slots[0].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy \n connect issue_slots[0].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy \n connect issue_slots[0].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy \n connect issue_slots[0].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred \n connect issue_slots[0].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 \n connect issue_slots[0].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 \n connect issue_slots[0].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 \n connect issue_slots[0].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst \n connect issue_slots[0].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx \n connect issue_slots[0].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx \n connect issue_slots[0].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx \n connect issue_slots[0].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx \n connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec \n connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags \n connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt \n connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div \n connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma \n connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint \n connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint \n connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 \n connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 \n connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 \n connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 \n connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 \n connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen \n connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst \n connect issue_slots[0].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel \n connect issue_slots[0].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel \n connect issue_slots[0].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed \n connect issue_slots[0].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm \n connect issue_slots[0].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel \n connect issue_slots[0].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename \n connect issue_slots[0].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken \n connect issue_slots[0].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob \n connect issue_slots[0].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst \n connect issue_slots[0].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx \n connect issue_slots[0].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov \n connect issue_slots[0].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc \n connect issue_slots[0].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc \n connect issue_slots[0].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret \n connect issue_slots[0].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo \n connect issue_slots[0].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence \n connect issue_slots[0].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei \n connect issue_slots[0].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence \n connect issue_slots[0].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb \n connect issue_slots[0].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type \n connect issue_slots[0].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag \n connect issue_slots[0].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask \n connect issue_slots[0].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel \n connect issue_slots[0].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint \n connect issue_slots[0].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint \n connect issue_slots[0].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint \n connect issue_slots[0].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child \n connect issue_slots[0].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child \n connect issue_slots[0].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen \n connect issue_slots[0].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen \n connect issue_slots[0].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued \n connect issue_slots[0].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] \n connect issue_slots[0].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] \n connect issue_slots[0].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] \n connect issue_slots[0].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] \n connect issue_slots[0].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] \n connect issue_slots[0].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] \n connect issue_slots[0].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] \n connect issue_slots[0].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] \n connect issue_slots[0].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] \n connect issue_slots[0].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] \n connect issue_slots[0].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] \n connect issue_slots[0].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] \n connect issue_slots[0].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] \n connect issue_slots[0].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] \n connect issue_slots[0].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc \n connect issue_slots[0].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc \n connect issue_slots[0].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst \n connect issue_slots[0].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst \n connect issue_slots[0].wakeup_ports[2].valid, io.wakeup_ports[2].valid \n connect issue_slots[0].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy \n connect issue_slots[0].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask \n connect issue_slots[0].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable \n connect issue_slots[0].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc \n connect issue_slots[0].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc \n connect issue_slots[0].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if \n connect issue_slots[0].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if \n connect issue_slots[0].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if \n connect issue_slots[0].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if \n connect issue_slots[0].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if \n connect issue_slots[0].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ \n connect issue_slots[0].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm \n connect issue_slots[0].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val \n connect issue_slots[0].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op \n connect issue_slots[0].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw \n connect issue_slots[0].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en \n connect issue_slots[0].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype \n connect issue_slots[0].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype \n connect issue_slots[0].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype \n connect issue_slots[0].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 \n connect issue_slots[0].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 \n connect issue_slots[0].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 \n connect issue_slots[0].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst \n connect issue_slots[0].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 \n connect issue_slots[0].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd \n connect issue_slots[0].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit \n connect issue_slots[0].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique \n connect issue_slots[0].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq \n connect issue_slots[0].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq \n connect issue_slots[0].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed \n connect issue_slots[0].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size \n connect issue_slots[0].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd \n connect issue_slots[0].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause \n connect issue_slots[0].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception \n connect issue_slots[0].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst \n connect issue_slots[0].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy \n connect issue_slots[0].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy \n connect issue_slots[0].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy \n connect issue_slots[0].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy \n connect issue_slots[0].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred \n connect issue_slots[0].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 \n connect issue_slots[0].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 \n connect issue_slots[0].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 \n connect issue_slots[0].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst \n connect issue_slots[0].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx \n connect issue_slots[0].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx \n connect issue_slots[0].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx \n connect issue_slots[0].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx \n connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec \n connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags \n connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt \n connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div \n connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma \n connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint \n connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint \n connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 \n connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 \n connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 \n connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 \n connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 \n connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen \n connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst \n connect issue_slots[0].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel \n connect issue_slots[0].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel \n connect issue_slots[0].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed \n connect issue_slots[0].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm \n connect issue_slots[0].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel \n connect issue_slots[0].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename \n connect issue_slots[0].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken \n connect issue_slots[0].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob \n connect issue_slots[0].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst \n connect issue_slots[0].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx \n connect issue_slots[0].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov \n connect issue_slots[0].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc \n connect issue_slots[0].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc \n connect issue_slots[0].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret \n connect issue_slots[0].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo \n connect issue_slots[0].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence \n connect issue_slots[0].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei \n connect issue_slots[0].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence \n connect issue_slots[0].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb \n connect issue_slots[0].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type \n connect issue_slots[0].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag \n connect issue_slots[0].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask \n connect issue_slots[0].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel \n connect issue_slots[0].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint \n connect issue_slots[0].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint \n connect issue_slots[0].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint \n connect issue_slots[0].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child \n connect issue_slots[0].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child \n connect issue_slots[0].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen \n connect issue_slots[0].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen \n connect issue_slots[0].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued \n connect issue_slots[0].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] \n connect issue_slots[0].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] \n connect issue_slots[0].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] \n connect issue_slots[0].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] \n connect issue_slots[0].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] \n connect issue_slots[0].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] \n connect issue_slots[0].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] \n connect issue_slots[0].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] \n connect issue_slots[0].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] \n connect issue_slots[0].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] \n connect issue_slots[0].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] \n connect issue_slots[0].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] \n connect issue_slots[0].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] \n connect issue_slots[0].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] \n connect issue_slots[0].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc \n connect issue_slots[0].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc \n connect issue_slots[0].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst \n connect issue_slots[0].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst \n connect issue_slots[0].wakeup_ports[3].valid, io.wakeup_ports[3].valid \n connect issue_slots[0].pred_wakeup_port.bits, io.pred_wakeup_port.bits \n connect issue_slots[0].pred_wakeup_port.valid, io.pred_wakeup_port.valid \n connect issue_slots[0].child_rebusys, io.child_rebusys \n connect issue_slots[0].squash_grant, io.squash_grant \n connect issue_slots[0].brupdate.b2.target_offset, io.brupdate.b2.target_offset \n connect issue_slots[0].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target \n connect issue_slots[0].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel \n connect issue_slots[0].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type \n connect issue_slots[0].brupdate.b2.taken, io.brupdate.b2.taken \n connect issue_slots[0].brupdate.b2.mispredict, io.brupdate.b2.mispredict \n connect issue_slots[0].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc \n connect issue_slots[0].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc \n connect issue_slots[0].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if \n connect issue_slots[0].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if \n connect issue_slots[0].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if \n connect issue_slots[0].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if \n connect issue_slots[0].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if \n connect issue_slots[0].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ \n connect issue_slots[0].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm \n connect issue_slots[0].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val \n connect issue_slots[0].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op \n connect issue_slots[0].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw \n connect issue_slots[0].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en \n connect issue_slots[0].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype \n connect issue_slots[0].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype \n connect issue_slots[0].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype \n connect issue_slots[0].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 \n connect issue_slots[0].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 \n connect issue_slots[0].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 \n connect issue_slots[0].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst \n connect issue_slots[0].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 \n connect issue_slots[0].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd \n connect issue_slots[0].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit \n connect issue_slots[0].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique \n connect issue_slots[0].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq \n connect issue_slots[0].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq \n connect issue_slots[0].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed \n connect issue_slots[0].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size \n connect issue_slots[0].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd \n connect issue_slots[0].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause \n connect issue_slots[0].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception \n connect issue_slots[0].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst \n connect issue_slots[0].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy \n connect issue_slots[0].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy \n connect issue_slots[0].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy \n connect issue_slots[0].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy \n connect issue_slots[0].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred \n connect issue_slots[0].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 \n connect issue_slots[0].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 \n connect issue_slots[0].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 \n connect issue_slots[0].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst \n connect issue_slots[0].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx \n connect issue_slots[0].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx \n connect issue_slots[0].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx \n connect issue_slots[0].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx \n connect issue_slots[0].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec \n connect issue_slots[0].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags \n connect issue_slots[0].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt \n connect issue_slots[0].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div \n connect issue_slots[0].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma \n connect issue_slots[0].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe \n connect issue_slots[0].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint \n connect issue_slots[0].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint \n connect issue_slots[0].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut \n connect issue_slots[0].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn \n connect issue_slots[0].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 \n connect issue_slots[0].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 \n connect issue_slots[0].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 \n connect issue_slots[0].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 \n connect issue_slots[0].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 \n connect issue_slots[0].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen \n connect issue_slots[0].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst \n connect issue_slots[0].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel \n connect issue_slots[0].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel \n connect issue_slots[0].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed \n connect issue_slots[0].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm \n connect issue_slots[0].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel \n connect issue_slots[0].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename \n connect issue_slots[0].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken \n connect issue_slots[0].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob \n connect issue_slots[0].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst \n connect issue_slots[0].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx \n connect issue_slots[0].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov \n connect issue_slots[0].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc \n connect issue_slots[0].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc \n connect issue_slots[0].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret \n connect issue_slots[0].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo \n connect issue_slots[0].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence \n connect issue_slots[0].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei \n connect issue_slots[0].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence \n connect issue_slots[0].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb \n connect issue_slots[0].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type \n connect issue_slots[0].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag \n connect issue_slots[0].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask \n connect issue_slots[0].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel \n connect issue_slots[0].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint \n connect issue_slots[0].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint \n connect issue_slots[0].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint \n connect issue_slots[0].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child \n connect issue_slots[0].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child \n connect issue_slots[0].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen \n connect issue_slots[0].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen \n connect issue_slots[0].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued \n connect issue_slots[0].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] \n connect issue_slots[0].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] \n connect issue_slots[0].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] \n connect issue_slots[0].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] \n connect issue_slots[0].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] \n connect issue_slots[0].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] \n connect issue_slots[0].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] \n connect issue_slots[0].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] \n connect issue_slots[0].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] \n connect issue_slots[0].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] \n connect issue_slots[0].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] \n connect issue_slots[0].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] \n connect issue_slots[0].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] \n connect issue_slots[0].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] \n connect issue_slots[0].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc \n connect issue_slots[0].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc \n connect issue_slots[0].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst \n connect issue_slots[0].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst \n connect issue_slots[0].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask \n connect issue_slots[0].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask \n connect issue_slots[0].kill, io.flush_pipeline \n connect issue_slots[1].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy \n connect issue_slots[1].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask \n connect issue_slots[1].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable \n connect issue_slots[1].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc \n connect issue_slots[1].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc \n connect issue_slots[1].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if \n connect issue_slots[1].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if \n connect issue_slots[1].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if \n connect issue_slots[1].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if \n connect issue_slots[1].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if \n connect issue_slots[1].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ \n connect issue_slots[1].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm \n connect issue_slots[1].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val \n connect issue_slots[1].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op \n connect issue_slots[1].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw \n connect issue_slots[1].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en \n connect issue_slots[1].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype \n connect issue_slots[1].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype \n connect issue_slots[1].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype \n connect issue_slots[1].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 \n connect issue_slots[1].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 \n connect issue_slots[1].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 \n connect issue_slots[1].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst \n connect issue_slots[1].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 \n connect issue_slots[1].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd \n connect issue_slots[1].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit \n connect issue_slots[1].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique \n connect issue_slots[1].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq \n connect issue_slots[1].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq \n connect issue_slots[1].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed \n connect issue_slots[1].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size \n connect issue_slots[1].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd \n connect issue_slots[1].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause \n connect issue_slots[1].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception \n connect issue_slots[1].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst \n connect issue_slots[1].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy \n connect issue_slots[1].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy \n connect issue_slots[1].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy \n connect issue_slots[1].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy \n connect issue_slots[1].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred \n connect issue_slots[1].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 \n connect issue_slots[1].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 \n connect issue_slots[1].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 \n connect issue_slots[1].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst \n connect issue_slots[1].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx \n connect issue_slots[1].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx \n connect issue_slots[1].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx \n connect issue_slots[1].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx \n connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec \n connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags \n connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt \n connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div \n connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma \n connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint \n connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint \n connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 \n connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 \n connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 \n connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 \n connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 \n connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen \n connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst \n connect issue_slots[1].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel \n connect issue_slots[1].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel \n connect issue_slots[1].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed \n connect issue_slots[1].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm \n connect issue_slots[1].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel \n connect issue_slots[1].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename \n connect issue_slots[1].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken \n connect issue_slots[1].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob \n connect issue_slots[1].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst \n connect issue_slots[1].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx \n connect issue_slots[1].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov \n connect issue_slots[1].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc \n connect issue_slots[1].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc \n connect issue_slots[1].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret \n connect issue_slots[1].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo \n connect issue_slots[1].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence \n connect issue_slots[1].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei \n connect issue_slots[1].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence \n connect issue_slots[1].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb \n connect issue_slots[1].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type \n connect issue_slots[1].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag \n connect issue_slots[1].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask \n connect issue_slots[1].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel \n connect issue_slots[1].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint \n connect issue_slots[1].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint \n connect issue_slots[1].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint \n connect issue_slots[1].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child \n connect issue_slots[1].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child \n connect issue_slots[1].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen \n connect issue_slots[1].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen \n connect issue_slots[1].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued \n connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] \n connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] \n connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] \n connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] \n connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] \n connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] \n connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] \n connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] \n connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] \n connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] \n connect issue_slots[1].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] \n connect issue_slots[1].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] \n connect issue_slots[1].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] \n connect issue_slots[1].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] \n connect issue_slots[1].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc \n connect issue_slots[1].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc \n connect issue_slots[1].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst \n connect issue_slots[1].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst \n connect issue_slots[1].wakeup_ports[0].valid, io.wakeup_ports[0].valid \n connect issue_slots[1].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy \n connect issue_slots[1].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask \n connect issue_slots[1].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable \n connect issue_slots[1].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc \n connect issue_slots[1].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc \n connect issue_slots[1].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if \n connect issue_slots[1].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if \n connect issue_slots[1].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if \n connect issue_slots[1].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if \n connect issue_slots[1].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if \n connect issue_slots[1].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ \n connect issue_slots[1].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm \n connect issue_slots[1].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val \n connect issue_slots[1].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op \n connect issue_slots[1].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw \n connect issue_slots[1].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en \n connect issue_slots[1].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype \n connect issue_slots[1].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype \n connect issue_slots[1].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype \n connect issue_slots[1].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 \n connect issue_slots[1].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 \n connect issue_slots[1].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 \n connect issue_slots[1].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst \n connect issue_slots[1].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 \n connect issue_slots[1].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd \n connect issue_slots[1].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit \n connect issue_slots[1].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique \n connect issue_slots[1].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq \n connect issue_slots[1].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq \n connect issue_slots[1].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed \n connect issue_slots[1].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size \n connect issue_slots[1].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd \n connect issue_slots[1].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause \n connect issue_slots[1].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception \n connect issue_slots[1].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst \n connect issue_slots[1].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy \n connect issue_slots[1].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy \n connect issue_slots[1].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy \n connect issue_slots[1].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy \n connect issue_slots[1].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred \n connect issue_slots[1].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 \n connect issue_slots[1].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 \n connect issue_slots[1].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 \n connect issue_slots[1].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst \n connect issue_slots[1].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx \n connect issue_slots[1].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx \n connect issue_slots[1].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx \n connect issue_slots[1].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx \n connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec \n connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags \n connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt \n connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div \n connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma \n connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint \n connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint \n connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 \n connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 \n connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 \n connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 \n connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 \n connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen \n connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst \n connect issue_slots[1].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel \n connect issue_slots[1].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel \n connect issue_slots[1].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed \n connect issue_slots[1].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm \n connect issue_slots[1].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel \n connect issue_slots[1].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename \n connect issue_slots[1].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken \n connect issue_slots[1].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob \n connect issue_slots[1].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst \n connect issue_slots[1].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx \n connect issue_slots[1].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov \n connect issue_slots[1].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc \n connect issue_slots[1].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc \n connect issue_slots[1].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret \n connect issue_slots[1].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo \n connect issue_slots[1].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence \n connect issue_slots[1].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei \n connect issue_slots[1].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence \n connect issue_slots[1].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb \n connect issue_slots[1].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type \n connect issue_slots[1].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag \n connect issue_slots[1].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask \n connect issue_slots[1].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel \n connect issue_slots[1].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint \n connect issue_slots[1].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint \n connect issue_slots[1].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint \n connect issue_slots[1].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child \n connect issue_slots[1].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child \n connect issue_slots[1].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen \n connect issue_slots[1].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen \n connect issue_slots[1].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued \n connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] \n connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] \n connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] \n connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] \n connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] \n connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] \n connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] \n connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] \n connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] \n connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] \n connect issue_slots[1].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] \n connect issue_slots[1].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] \n connect issue_slots[1].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] \n connect issue_slots[1].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] \n connect issue_slots[1].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc \n connect issue_slots[1].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc \n connect issue_slots[1].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst \n connect issue_slots[1].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst \n connect issue_slots[1].wakeup_ports[1].valid, io.wakeup_ports[1].valid \n connect issue_slots[1].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy \n connect issue_slots[1].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask \n connect issue_slots[1].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable \n connect issue_slots[1].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc \n connect issue_slots[1].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc \n connect issue_slots[1].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if \n connect issue_slots[1].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if \n connect issue_slots[1].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if \n connect issue_slots[1].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if \n connect issue_slots[1].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if \n connect issue_slots[1].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ \n connect issue_slots[1].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm \n connect issue_slots[1].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val \n connect issue_slots[1].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op \n connect issue_slots[1].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw \n connect issue_slots[1].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en \n connect issue_slots[1].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype \n connect issue_slots[1].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype \n connect issue_slots[1].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype \n connect issue_slots[1].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 \n connect issue_slots[1].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 \n connect issue_slots[1].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 \n connect issue_slots[1].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst \n connect issue_slots[1].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 \n connect issue_slots[1].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd \n connect issue_slots[1].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit \n connect issue_slots[1].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique \n connect issue_slots[1].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq \n connect issue_slots[1].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq \n connect issue_slots[1].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed \n connect issue_slots[1].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size \n connect issue_slots[1].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd \n connect issue_slots[1].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause \n connect issue_slots[1].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception \n connect issue_slots[1].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst \n connect issue_slots[1].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy \n connect issue_slots[1].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy \n connect issue_slots[1].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy \n connect issue_slots[1].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy \n connect issue_slots[1].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred \n connect issue_slots[1].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 \n connect issue_slots[1].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 \n connect issue_slots[1].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 \n connect issue_slots[1].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst \n connect issue_slots[1].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx \n connect issue_slots[1].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx \n connect issue_slots[1].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx \n connect issue_slots[1].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx \n connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec \n connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags \n connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt \n connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div \n connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma \n connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint \n connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint \n connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 \n connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 \n connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 \n connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 \n connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 \n connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen \n connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst \n connect issue_slots[1].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel \n connect issue_slots[1].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel \n connect issue_slots[1].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed \n connect issue_slots[1].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm \n connect issue_slots[1].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel \n connect issue_slots[1].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename \n connect issue_slots[1].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken \n connect issue_slots[1].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob \n connect issue_slots[1].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst \n connect issue_slots[1].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx \n connect issue_slots[1].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov \n connect issue_slots[1].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc \n connect issue_slots[1].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc \n connect issue_slots[1].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret \n connect issue_slots[1].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo \n connect issue_slots[1].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence \n connect issue_slots[1].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei \n connect issue_slots[1].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence \n connect issue_slots[1].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb \n connect issue_slots[1].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type \n connect issue_slots[1].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag \n connect issue_slots[1].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask \n connect issue_slots[1].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel \n connect issue_slots[1].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint \n connect issue_slots[1].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint \n connect issue_slots[1].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint \n connect issue_slots[1].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child \n connect issue_slots[1].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child \n connect issue_slots[1].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen \n connect issue_slots[1].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen \n connect issue_slots[1].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued \n connect issue_slots[1].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] \n connect issue_slots[1].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] \n connect issue_slots[1].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] \n connect issue_slots[1].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] \n connect issue_slots[1].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] \n connect issue_slots[1].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] \n connect issue_slots[1].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] \n connect issue_slots[1].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] \n connect issue_slots[1].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] \n connect issue_slots[1].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] \n connect issue_slots[1].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] \n connect issue_slots[1].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] \n connect issue_slots[1].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] \n connect issue_slots[1].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] \n connect issue_slots[1].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc \n connect issue_slots[1].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc \n connect issue_slots[1].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst \n connect issue_slots[1].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst \n connect issue_slots[1].wakeup_ports[2].valid, io.wakeup_ports[2].valid \n connect issue_slots[1].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy \n connect issue_slots[1].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask \n connect issue_slots[1].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable \n connect issue_slots[1].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc \n connect issue_slots[1].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc \n connect issue_slots[1].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if \n connect issue_slots[1].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if \n connect issue_slots[1].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if \n connect issue_slots[1].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if \n connect issue_slots[1].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if \n connect issue_slots[1].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ \n connect issue_slots[1].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm \n connect issue_slots[1].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val \n connect issue_slots[1].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op \n connect issue_slots[1].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw \n connect issue_slots[1].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en \n connect issue_slots[1].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype \n connect issue_slots[1].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype \n connect issue_slots[1].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype \n connect issue_slots[1].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 \n connect issue_slots[1].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 \n connect issue_slots[1].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 \n connect issue_slots[1].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst \n connect issue_slots[1].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 \n connect issue_slots[1].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd \n connect issue_slots[1].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit \n connect issue_slots[1].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique \n connect issue_slots[1].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq \n connect issue_slots[1].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq \n connect issue_slots[1].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed \n connect issue_slots[1].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size \n connect issue_slots[1].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd \n connect issue_slots[1].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause \n connect issue_slots[1].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception \n connect issue_slots[1].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst \n connect issue_slots[1].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy \n connect issue_slots[1].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy \n connect issue_slots[1].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy \n connect issue_slots[1].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy \n connect issue_slots[1].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred \n connect issue_slots[1].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 \n connect issue_slots[1].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 \n connect issue_slots[1].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 \n connect issue_slots[1].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst \n connect issue_slots[1].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx \n connect issue_slots[1].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx \n connect issue_slots[1].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx \n connect issue_slots[1].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx \n connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec \n connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags \n connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt \n connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div \n connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma \n connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint \n connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint \n connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 \n connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 \n connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 \n connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 \n connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 \n connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen \n connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst \n connect issue_slots[1].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel \n connect issue_slots[1].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel \n connect issue_slots[1].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed \n connect issue_slots[1].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm \n connect issue_slots[1].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel \n connect issue_slots[1].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename \n connect issue_slots[1].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken \n connect issue_slots[1].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob \n connect issue_slots[1].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst \n connect issue_slots[1].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx \n connect issue_slots[1].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov \n connect issue_slots[1].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc \n connect issue_slots[1].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc \n connect issue_slots[1].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret \n connect issue_slots[1].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo \n connect issue_slots[1].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence \n connect issue_slots[1].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei \n connect issue_slots[1].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence \n connect issue_slots[1].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb \n connect issue_slots[1].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type \n connect issue_slots[1].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag \n connect issue_slots[1].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask \n connect issue_slots[1].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel \n connect issue_slots[1].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint \n connect issue_slots[1].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint \n connect issue_slots[1].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint \n connect issue_slots[1].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child \n connect issue_slots[1].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child \n connect issue_slots[1].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen \n connect issue_slots[1].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen \n connect issue_slots[1].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued \n connect issue_slots[1].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] \n connect issue_slots[1].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] \n connect issue_slots[1].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] \n connect issue_slots[1].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] \n connect issue_slots[1].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] \n connect issue_slots[1].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] \n connect issue_slots[1].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] \n connect issue_slots[1].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] \n connect issue_slots[1].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] \n connect issue_slots[1].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] \n connect issue_slots[1].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] \n connect issue_slots[1].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] \n connect issue_slots[1].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] \n connect issue_slots[1].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] \n connect issue_slots[1].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc \n connect issue_slots[1].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc \n connect issue_slots[1].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst \n connect issue_slots[1].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst \n connect issue_slots[1].wakeup_ports[3].valid, io.wakeup_ports[3].valid \n connect issue_slots[1].pred_wakeup_port.bits, io.pred_wakeup_port.bits \n connect issue_slots[1].pred_wakeup_port.valid, io.pred_wakeup_port.valid \n connect issue_slots[1].child_rebusys, io.child_rebusys \n connect issue_slots[1].squash_grant, io.squash_grant \n connect issue_slots[1].brupdate.b2.target_offset, io.brupdate.b2.target_offset \n connect issue_slots[1].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target \n connect issue_slots[1].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel \n connect issue_slots[1].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type \n connect issue_slots[1].brupdate.b2.taken, io.brupdate.b2.taken \n connect issue_slots[1].brupdate.b2.mispredict, io.brupdate.b2.mispredict \n connect issue_slots[1].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc \n connect issue_slots[1].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc \n connect issue_slots[1].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if \n connect issue_slots[1].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if \n connect issue_slots[1].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if \n connect issue_slots[1].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if \n connect issue_slots[1].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if \n connect issue_slots[1].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ \n connect issue_slots[1].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm \n connect issue_slots[1].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val \n connect issue_slots[1].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op \n connect issue_slots[1].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw \n connect issue_slots[1].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en \n connect issue_slots[1].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype \n connect issue_slots[1].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype \n connect issue_slots[1].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype \n connect issue_slots[1].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 \n connect issue_slots[1].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 \n connect issue_slots[1].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 \n connect issue_slots[1].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst \n connect issue_slots[1].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 \n connect issue_slots[1].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd \n connect issue_slots[1].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit \n connect issue_slots[1].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique \n connect issue_slots[1].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq \n connect issue_slots[1].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq \n connect issue_slots[1].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed \n connect issue_slots[1].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size \n connect issue_slots[1].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd \n connect issue_slots[1].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause \n connect issue_slots[1].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception \n connect issue_slots[1].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst \n connect issue_slots[1].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy \n connect issue_slots[1].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy \n connect issue_slots[1].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy \n connect issue_slots[1].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy \n connect issue_slots[1].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred \n connect issue_slots[1].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 \n connect issue_slots[1].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 \n connect issue_slots[1].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 \n connect issue_slots[1].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst \n connect issue_slots[1].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx \n connect issue_slots[1].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx \n connect issue_slots[1].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx \n connect issue_slots[1].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx \n connect issue_slots[1].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec \n connect issue_slots[1].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags \n connect issue_slots[1].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt \n connect issue_slots[1].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div \n connect issue_slots[1].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma \n connect issue_slots[1].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe \n connect issue_slots[1].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint \n connect issue_slots[1].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint \n connect issue_slots[1].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut \n connect issue_slots[1].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn \n connect issue_slots[1].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 \n connect issue_slots[1].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 \n connect issue_slots[1].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 \n connect issue_slots[1].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 \n connect issue_slots[1].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 \n connect issue_slots[1].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen \n connect issue_slots[1].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst \n connect issue_slots[1].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel \n connect issue_slots[1].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel \n connect issue_slots[1].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed \n connect issue_slots[1].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm \n connect issue_slots[1].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel \n connect issue_slots[1].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename \n connect issue_slots[1].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken \n connect issue_slots[1].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob \n connect issue_slots[1].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst \n connect issue_slots[1].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx \n connect issue_slots[1].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov \n connect issue_slots[1].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc \n connect issue_slots[1].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc \n connect issue_slots[1].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret \n connect issue_slots[1].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo \n connect issue_slots[1].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence \n connect issue_slots[1].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei \n connect issue_slots[1].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence \n connect issue_slots[1].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb \n connect issue_slots[1].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type \n connect issue_slots[1].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag \n connect issue_slots[1].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask \n connect issue_slots[1].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel \n connect issue_slots[1].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint \n connect issue_slots[1].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint \n connect issue_slots[1].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint \n connect issue_slots[1].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child \n connect issue_slots[1].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child \n connect issue_slots[1].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen \n connect issue_slots[1].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen \n connect issue_slots[1].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued \n connect issue_slots[1].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] \n connect issue_slots[1].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] \n connect issue_slots[1].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] \n connect issue_slots[1].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] \n connect issue_slots[1].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] \n connect issue_slots[1].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] \n connect issue_slots[1].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] \n connect issue_slots[1].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] \n connect issue_slots[1].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] \n connect issue_slots[1].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] \n connect issue_slots[1].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] \n connect issue_slots[1].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] \n connect issue_slots[1].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] \n connect issue_slots[1].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] \n connect issue_slots[1].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc \n connect issue_slots[1].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc \n connect issue_slots[1].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst \n connect issue_slots[1].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst \n connect issue_slots[1].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask \n connect issue_slots[1].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask \n connect issue_slots[1].kill, io.flush_pipeline \n connect issue_slots[2].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy \n connect issue_slots[2].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask \n connect issue_slots[2].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable \n connect issue_slots[2].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc \n connect issue_slots[2].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc \n connect issue_slots[2].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if \n connect issue_slots[2].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if \n connect issue_slots[2].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if \n connect issue_slots[2].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if \n connect issue_slots[2].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if \n connect issue_slots[2].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ \n connect issue_slots[2].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm \n connect issue_slots[2].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val \n connect issue_slots[2].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op \n connect issue_slots[2].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw \n connect issue_slots[2].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en \n connect issue_slots[2].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype \n connect issue_slots[2].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype \n connect issue_slots[2].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype \n connect issue_slots[2].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 \n connect issue_slots[2].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 \n connect issue_slots[2].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 \n connect issue_slots[2].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst \n connect issue_slots[2].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 \n connect issue_slots[2].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd \n connect issue_slots[2].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit \n connect issue_slots[2].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique \n connect issue_slots[2].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq \n connect issue_slots[2].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq \n connect issue_slots[2].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed \n connect issue_slots[2].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size \n connect issue_slots[2].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd \n connect issue_slots[2].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause \n connect issue_slots[2].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception \n connect issue_slots[2].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst \n connect issue_slots[2].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy \n connect issue_slots[2].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy \n connect issue_slots[2].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy \n connect issue_slots[2].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy \n connect issue_slots[2].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred \n connect issue_slots[2].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 \n connect issue_slots[2].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 \n connect issue_slots[2].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 \n connect issue_slots[2].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst \n connect issue_slots[2].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx \n connect issue_slots[2].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx \n connect issue_slots[2].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx \n connect issue_slots[2].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx \n connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec \n connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags \n connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt \n connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div \n connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma \n connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint \n connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint \n connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 \n connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 \n connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 \n connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 \n connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 \n connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen \n connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst \n connect issue_slots[2].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel \n connect issue_slots[2].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel \n connect issue_slots[2].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed \n connect issue_slots[2].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm \n connect issue_slots[2].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel \n connect issue_slots[2].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename \n connect issue_slots[2].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken \n connect issue_slots[2].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob \n connect issue_slots[2].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst \n connect issue_slots[2].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx \n connect issue_slots[2].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov \n connect issue_slots[2].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc \n connect issue_slots[2].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc \n connect issue_slots[2].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret \n connect issue_slots[2].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo \n connect issue_slots[2].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence \n connect issue_slots[2].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei \n connect issue_slots[2].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence \n connect issue_slots[2].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb \n connect issue_slots[2].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type \n connect issue_slots[2].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag \n connect issue_slots[2].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask \n connect issue_slots[2].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel \n connect issue_slots[2].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint \n connect issue_slots[2].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint \n connect issue_slots[2].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint \n connect issue_slots[2].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child \n connect issue_slots[2].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child \n connect issue_slots[2].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen \n connect issue_slots[2].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen \n connect issue_slots[2].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued \n connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] \n connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] \n connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] \n connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] \n connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] \n connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] \n connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] \n connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] \n connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] \n connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] \n connect issue_slots[2].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] \n connect issue_slots[2].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] \n connect issue_slots[2].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] \n connect issue_slots[2].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] \n connect issue_slots[2].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc \n connect issue_slots[2].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc \n connect issue_slots[2].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst \n connect issue_slots[2].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst \n connect issue_slots[2].wakeup_ports[0].valid, io.wakeup_ports[0].valid \n connect issue_slots[2].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy \n connect issue_slots[2].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask \n connect issue_slots[2].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable \n connect issue_slots[2].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc \n connect issue_slots[2].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc \n connect issue_slots[2].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if \n connect issue_slots[2].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if \n connect issue_slots[2].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if \n connect issue_slots[2].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if \n connect issue_slots[2].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if \n connect issue_slots[2].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ \n connect issue_slots[2].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm \n connect issue_slots[2].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val \n connect issue_slots[2].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op \n connect issue_slots[2].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw \n connect issue_slots[2].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en \n connect issue_slots[2].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype \n connect issue_slots[2].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype \n connect issue_slots[2].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype \n connect issue_slots[2].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 \n connect issue_slots[2].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 \n connect issue_slots[2].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 \n connect issue_slots[2].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst \n connect issue_slots[2].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 \n connect issue_slots[2].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd \n connect issue_slots[2].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit \n connect issue_slots[2].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique \n connect issue_slots[2].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq \n connect issue_slots[2].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq \n connect issue_slots[2].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed \n connect issue_slots[2].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size \n connect issue_slots[2].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd \n connect issue_slots[2].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause \n connect issue_slots[2].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception \n connect issue_slots[2].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst \n connect issue_slots[2].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy \n connect issue_slots[2].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy \n connect issue_slots[2].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy \n connect issue_slots[2].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy \n connect issue_slots[2].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred \n connect issue_slots[2].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 \n connect issue_slots[2].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 \n connect issue_slots[2].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 \n connect issue_slots[2].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst \n connect issue_slots[2].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx \n connect issue_slots[2].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx \n connect issue_slots[2].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx \n connect issue_slots[2].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx \n connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec \n connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags \n connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt \n connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div \n connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma \n connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint \n connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint \n connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 \n connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 \n connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 \n connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 \n connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 \n connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen \n connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst \n connect issue_slots[2].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel \n connect issue_slots[2].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel \n connect issue_slots[2].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed \n connect issue_slots[2].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm \n connect issue_slots[2].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel \n connect issue_slots[2].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename \n connect issue_slots[2].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken \n connect issue_slots[2].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob \n connect issue_slots[2].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst \n connect issue_slots[2].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx \n connect issue_slots[2].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov \n connect issue_slots[2].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc \n connect issue_slots[2].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc \n connect issue_slots[2].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret \n connect issue_slots[2].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo \n connect issue_slots[2].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence \n connect issue_slots[2].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei \n connect issue_slots[2].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence \n connect issue_slots[2].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb \n connect issue_slots[2].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type \n connect issue_slots[2].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag \n connect issue_slots[2].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask \n connect issue_slots[2].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel \n connect issue_slots[2].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint \n connect issue_slots[2].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint \n connect issue_slots[2].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint \n connect issue_slots[2].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child \n connect issue_slots[2].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child \n connect issue_slots[2].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen \n connect issue_slots[2].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen \n connect issue_slots[2].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued \n connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] \n connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] \n connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] \n connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] \n connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] \n connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] \n connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] \n connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] \n connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] \n connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] \n connect issue_slots[2].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] \n connect issue_slots[2].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] \n connect issue_slots[2].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] \n connect issue_slots[2].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] \n connect issue_slots[2].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc \n connect issue_slots[2].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc \n connect issue_slots[2].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst \n connect issue_slots[2].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst \n connect issue_slots[2].wakeup_ports[1].valid, io.wakeup_ports[1].valid \n connect issue_slots[2].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy \n connect issue_slots[2].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask \n connect issue_slots[2].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable \n connect issue_slots[2].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc \n connect issue_slots[2].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc \n connect issue_slots[2].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if \n connect issue_slots[2].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if \n connect issue_slots[2].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if \n connect issue_slots[2].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if \n connect issue_slots[2].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if \n connect issue_slots[2].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ \n connect issue_slots[2].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm \n connect issue_slots[2].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val \n connect issue_slots[2].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op \n connect issue_slots[2].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw \n connect issue_slots[2].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en \n connect issue_slots[2].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype \n connect issue_slots[2].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype \n connect issue_slots[2].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype \n connect issue_slots[2].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 \n connect issue_slots[2].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 \n connect issue_slots[2].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 \n connect issue_slots[2].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst \n connect issue_slots[2].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 \n connect issue_slots[2].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd \n connect issue_slots[2].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit \n connect issue_slots[2].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique \n connect issue_slots[2].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq \n connect issue_slots[2].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq \n connect issue_slots[2].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed \n connect issue_slots[2].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size \n connect issue_slots[2].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd \n connect issue_slots[2].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause \n connect issue_slots[2].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception \n connect issue_slots[2].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst \n connect issue_slots[2].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy \n connect issue_slots[2].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy \n connect issue_slots[2].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy \n connect issue_slots[2].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy \n connect issue_slots[2].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred \n connect issue_slots[2].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 \n connect issue_slots[2].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 \n connect issue_slots[2].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 \n connect issue_slots[2].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst \n connect issue_slots[2].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx \n connect issue_slots[2].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx \n connect issue_slots[2].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx \n connect issue_slots[2].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx \n connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec \n connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags \n connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt \n connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div \n connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma \n connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint \n connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint \n connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 \n connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 \n connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 \n connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 \n connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 \n connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen \n connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst \n connect issue_slots[2].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel \n connect issue_slots[2].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel \n connect issue_slots[2].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed \n connect issue_slots[2].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm \n connect issue_slots[2].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel \n connect issue_slots[2].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename \n connect issue_slots[2].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken \n connect issue_slots[2].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob \n connect issue_slots[2].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst \n connect issue_slots[2].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx \n connect issue_slots[2].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov \n connect issue_slots[2].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc \n connect issue_slots[2].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc \n connect issue_slots[2].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret \n connect issue_slots[2].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo \n connect issue_slots[2].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence \n connect issue_slots[2].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei \n connect issue_slots[2].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence \n connect issue_slots[2].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb \n connect issue_slots[2].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type \n connect issue_slots[2].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag \n connect issue_slots[2].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask \n connect issue_slots[2].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel \n connect issue_slots[2].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint \n connect issue_slots[2].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint \n connect issue_slots[2].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint \n connect issue_slots[2].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child \n connect issue_slots[2].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child \n connect issue_slots[2].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen \n connect issue_slots[2].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen \n connect issue_slots[2].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued \n connect issue_slots[2].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] \n connect issue_slots[2].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] \n connect issue_slots[2].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] \n connect issue_slots[2].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] \n connect issue_slots[2].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] \n connect issue_slots[2].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] \n connect issue_slots[2].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] \n connect issue_slots[2].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] \n connect issue_slots[2].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] \n connect issue_slots[2].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] \n connect issue_slots[2].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] \n connect issue_slots[2].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] \n connect issue_slots[2].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] \n connect issue_slots[2].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] \n connect issue_slots[2].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc \n connect issue_slots[2].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc \n connect issue_slots[2].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst \n connect issue_slots[2].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst \n connect issue_slots[2].wakeup_ports[2].valid, io.wakeup_ports[2].valid \n connect issue_slots[2].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy \n connect issue_slots[2].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask \n connect issue_slots[2].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable \n connect issue_slots[2].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc \n connect issue_slots[2].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc \n connect issue_slots[2].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if \n connect issue_slots[2].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if \n connect issue_slots[2].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if \n connect issue_slots[2].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if \n connect issue_slots[2].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if \n connect issue_slots[2].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ \n connect issue_slots[2].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm \n connect issue_slots[2].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val \n connect issue_slots[2].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op \n connect issue_slots[2].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw \n connect issue_slots[2].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en \n connect issue_slots[2].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype \n connect issue_slots[2].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype \n connect issue_slots[2].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype \n connect issue_slots[2].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 \n connect issue_slots[2].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 \n connect issue_slots[2].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 \n connect issue_slots[2].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst \n connect issue_slots[2].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 \n connect issue_slots[2].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd \n connect issue_slots[2].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit \n connect issue_slots[2].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique \n connect issue_slots[2].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq \n connect issue_slots[2].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq \n connect issue_slots[2].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed \n connect issue_slots[2].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size \n connect issue_slots[2].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd \n connect issue_slots[2].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause \n connect issue_slots[2].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception \n connect issue_slots[2].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst \n connect issue_slots[2].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy \n connect issue_slots[2].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy \n connect issue_slots[2].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy \n connect issue_slots[2].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy \n connect issue_slots[2].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred \n connect issue_slots[2].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 \n connect issue_slots[2].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 \n connect issue_slots[2].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 \n connect issue_slots[2].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst \n connect issue_slots[2].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx \n connect issue_slots[2].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx \n connect issue_slots[2].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx \n connect issue_slots[2].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx \n connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec \n connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags \n connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt \n connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div \n connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma \n connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint \n connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint \n connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 \n connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 \n connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 \n connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 \n connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 \n connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen \n connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst \n connect issue_slots[2].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel \n connect issue_slots[2].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel \n connect issue_slots[2].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed \n connect issue_slots[2].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm \n connect issue_slots[2].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel \n connect issue_slots[2].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename \n connect issue_slots[2].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken \n connect issue_slots[2].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob \n connect issue_slots[2].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst \n connect issue_slots[2].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx \n connect issue_slots[2].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov \n connect issue_slots[2].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc \n connect issue_slots[2].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc \n connect issue_slots[2].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret \n connect issue_slots[2].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo \n connect issue_slots[2].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence \n connect issue_slots[2].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei \n connect issue_slots[2].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence \n connect issue_slots[2].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb \n connect issue_slots[2].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type \n connect issue_slots[2].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag \n connect issue_slots[2].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask \n connect issue_slots[2].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel \n connect issue_slots[2].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint \n connect issue_slots[2].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint \n connect issue_slots[2].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint \n connect issue_slots[2].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child \n connect issue_slots[2].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child \n connect issue_slots[2].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen \n connect issue_slots[2].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen \n connect issue_slots[2].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued \n connect issue_slots[2].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] \n connect issue_slots[2].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] \n connect issue_slots[2].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] \n connect issue_slots[2].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] \n connect issue_slots[2].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] \n connect issue_slots[2].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] \n connect issue_slots[2].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] \n connect issue_slots[2].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] \n connect issue_slots[2].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] \n connect issue_slots[2].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] \n connect issue_slots[2].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] \n connect issue_slots[2].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] \n connect issue_slots[2].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] \n connect issue_slots[2].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] \n connect issue_slots[2].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc \n connect issue_slots[2].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc \n connect issue_slots[2].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst \n connect issue_slots[2].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst \n connect issue_slots[2].wakeup_ports[3].valid, io.wakeup_ports[3].valid \n connect issue_slots[2].pred_wakeup_port.bits, io.pred_wakeup_port.bits \n connect issue_slots[2].pred_wakeup_port.valid, io.pred_wakeup_port.valid \n connect issue_slots[2].child_rebusys, io.child_rebusys \n connect issue_slots[2].squash_grant, io.squash_grant \n connect issue_slots[2].brupdate.b2.target_offset, io.brupdate.b2.target_offset \n connect issue_slots[2].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target \n connect issue_slots[2].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel \n connect issue_slots[2].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type \n connect issue_slots[2].brupdate.b2.taken, io.brupdate.b2.taken \n connect issue_slots[2].brupdate.b2.mispredict, io.brupdate.b2.mispredict \n connect issue_slots[2].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc \n connect issue_slots[2].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc \n connect issue_slots[2].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if \n connect issue_slots[2].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if \n connect issue_slots[2].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if \n connect issue_slots[2].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if \n connect issue_slots[2].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if \n connect issue_slots[2].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ \n connect issue_slots[2].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm \n connect issue_slots[2].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val \n connect issue_slots[2].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op \n connect issue_slots[2].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw \n connect issue_slots[2].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en \n connect issue_slots[2].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype \n connect issue_slots[2].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype \n connect issue_slots[2].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype \n connect issue_slots[2].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 \n connect issue_slots[2].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 \n connect issue_slots[2].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 \n connect issue_slots[2].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst \n connect issue_slots[2].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 \n connect issue_slots[2].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd \n connect issue_slots[2].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit \n connect issue_slots[2].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique \n connect issue_slots[2].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq \n connect issue_slots[2].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq \n connect issue_slots[2].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed \n connect issue_slots[2].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size \n connect issue_slots[2].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd \n connect issue_slots[2].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause \n connect issue_slots[2].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception \n connect issue_slots[2].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst \n connect issue_slots[2].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy \n connect issue_slots[2].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy \n connect issue_slots[2].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy \n connect issue_slots[2].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy \n connect issue_slots[2].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred \n connect issue_slots[2].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 \n connect issue_slots[2].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 \n connect issue_slots[2].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 \n connect issue_slots[2].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst \n connect issue_slots[2].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx \n connect issue_slots[2].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx \n connect issue_slots[2].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx \n connect issue_slots[2].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx \n connect issue_slots[2].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec \n connect issue_slots[2].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags \n connect issue_slots[2].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt \n connect issue_slots[2].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div \n connect issue_slots[2].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma \n connect issue_slots[2].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe \n connect issue_slots[2].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint \n connect issue_slots[2].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint \n connect issue_slots[2].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut \n connect issue_slots[2].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn \n connect issue_slots[2].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 \n connect issue_slots[2].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 \n connect issue_slots[2].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 \n connect issue_slots[2].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 \n connect issue_slots[2].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 \n connect issue_slots[2].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen \n connect issue_slots[2].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst \n connect issue_slots[2].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel \n connect issue_slots[2].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel \n connect issue_slots[2].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed \n connect issue_slots[2].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm \n connect issue_slots[2].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel \n connect issue_slots[2].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename \n connect issue_slots[2].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken \n connect issue_slots[2].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob \n connect issue_slots[2].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst \n connect issue_slots[2].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx \n connect issue_slots[2].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov \n connect issue_slots[2].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc \n connect issue_slots[2].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc \n connect issue_slots[2].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret \n connect issue_slots[2].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo \n connect issue_slots[2].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence \n connect issue_slots[2].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei \n connect issue_slots[2].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence \n connect issue_slots[2].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb \n connect issue_slots[2].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type \n connect issue_slots[2].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag \n connect issue_slots[2].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask \n connect issue_slots[2].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel \n connect issue_slots[2].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint \n connect issue_slots[2].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint \n connect issue_slots[2].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint \n connect issue_slots[2].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child \n connect issue_slots[2].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child \n connect issue_slots[2].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen \n connect issue_slots[2].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen \n connect issue_slots[2].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued \n connect issue_slots[2].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] \n connect issue_slots[2].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] \n connect issue_slots[2].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] \n connect issue_slots[2].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] \n connect issue_slots[2].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] \n connect issue_slots[2].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] \n connect issue_slots[2].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] \n connect issue_slots[2].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] \n connect issue_slots[2].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] \n connect issue_slots[2].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] \n connect issue_slots[2].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] \n connect issue_slots[2].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] \n connect issue_slots[2].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] \n connect issue_slots[2].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] \n connect issue_slots[2].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc \n connect issue_slots[2].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc \n connect issue_slots[2].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst \n connect issue_slots[2].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst \n connect issue_slots[2].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask \n connect issue_slots[2].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask \n connect issue_slots[2].kill, io.flush_pipeline \n connect issue_slots[3].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy \n connect issue_slots[3].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask \n connect issue_slots[3].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable \n connect issue_slots[3].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc \n connect issue_slots[3].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc \n connect issue_slots[3].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if \n connect issue_slots[3].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if \n connect issue_slots[3].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if \n connect issue_slots[3].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if \n connect issue_slots[3].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if \n connect issue_slots[3].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ \n connect issue_slots[3].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm \n connect issue_slots[3].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val \n connect issue_slots[3].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op \n connect issue_slots[3].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw \n connect issue_slots[3].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en \n connect issue_slots[3].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype \n connect issue_slots[3].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype \n connect issue_slots[3].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype \n connect issue_slots[3].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 \n connect issue_slots[3].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 \n connect issue_slots[3].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 \n connect issue_slots[3].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst \n connect issue_slots[3].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 \n connect issue_slots[3].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd \n connect issue_slots[3].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit \n connect issue_slots[3].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique \n connect issue_slots[3].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq \n connect issue_slots[3].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq \n connect issue_slots[3].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed \n connect issue_slots[3].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size \n connect issue_slots[3].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd \n connect issue_slots[3].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause \n connect issue_slots[3].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception \n connect issue_slots[3].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst \n connect issue_slots[3].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy \n connect issue_slots[3].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy \n connect issue_slots[3].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy \n connect issue_slots[3].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy \n connect issue_slots[3].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred \n connect issue_slots[3].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 \n connect issue_slots[3].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 \n connect issue_slots[3].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 \n connect issue_slots[3].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst \n connect issue_slots[3].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx \n connect issue_slots[3].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx \n connect issue_slots[3].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx \n connect issue_slots[3].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx \n connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec \n connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags \n connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt \n connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div \n connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma \n connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint \n connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint \n connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 \n connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 \n connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 \n connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 \n connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 \n connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen \n connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst \n connect issue_slots[3].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel \n connect issue_slots[3].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel \n connect issue_slots[3].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed \n connect issue_slots[3].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm \n connect issue_slots[3].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel \n connect issue_slots[3].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename \n connect issue_slots[3].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken \n connect issue_slots[3].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob \n connect issue_slots[3].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst \n connect issue_slots[3].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx \n connect issue_slots[3].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov \n connect issue_slots[3].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc \n connect issue_slots[3].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc \n connect issue_slots[3].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret \n connect issue_slots[3].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo \n connect issue_slots[3].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence \n connect issue_slots[3].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei \n connect issue_slots[3].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence \n connect issue_slots[3].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb \n connect issue_slots[3].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type \n connect issue_slots[3].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag \n connect issue_slots[3].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask \n connect issue_slots[3].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel \n connect issue_slots[3].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint \n connect issue_slots[3].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint \n connect issue_slots[3].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint \n connect issue_slots[3].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child \n connect issue_slots[3].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child \n connect issue_slots[3].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen \n connect issue_slots[3].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen \n connect issue_slots[3].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued \n connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] \n connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] \n connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] \n connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] \n connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] \n connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] \n connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] \n connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] \n connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] \n connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] \n connect issue_slots[3].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] \n connect issue_slots[3].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] \n connect issue_slots[3].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] \n connect issue_slots[3].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] \n connect issue_slots[3].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc \n connect issue_slots[3].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc \n connect issue_slots[3].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst \n connect issue_slots[3].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst \n connect issue_slots[3].wakeup_ports[0].valid, io.wakeup_ports[0].valid \n connect issue_slots[3].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy \n connect issue_slots[3].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask \n connect issue_slots[3].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable \n connect issue_slots[3].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc \n connect issue_slots[3].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc \n connect issue_slots[3].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if \n connect issue_slots[3].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if \n connect issue_slots[3].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if \n connect issue_slots[3].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if \n connect issue_slots[3].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if \n connect issue_slots[3].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ \n connect issue_slots[3].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm \n connect issue_slots[3].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val \n connect issue_slots[3].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op \n connect issue_slots[3].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw \n connect issue_slots[3].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en \n connect issue_slots[3].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype \n connect issue_slots[3].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype \n connect issue_slots[3].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype \n connect issue_slots[3].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 \n connect issue_slots[3].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 \n connect issue_slots[3].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 \n connect issue_slots[3].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst \n connect issue_slots[3].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 \n connect issue_slots[3].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd \n connect issue_slots[3].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit \n connect issue_slots[3].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique \n connect issue_slots[3].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq \n connect issue_slots[3].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq \n connect issue_slots[3].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed \n connect issue_slots[3].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size \n connect issue_slots[3].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd \n connect issue_slots[3].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause \n connect issue_slots[3].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception \n connect issue_slots[3].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst \n connect issue_slots[3].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy \n connect issue_slots[3].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy \n connect issue_slots[3].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy \n connect issue_slots[3].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy \n connect issue_slots[3].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred \n connect issue_slots[3].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 \n connect issue_slots[3].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 \n connect issue_slots[3].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 \n connect issue_slots[3].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst \n connect issue_slots[3].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx \n connect issue_slots[3].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx \n connect issue_slots[3].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx \n connect issue_slots[3].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx \n connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec \n connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags \n connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt \n connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div \n connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma \n connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint \n connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint \n connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 \n connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 \n connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 \n connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 \n connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 \n connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen \n connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst \n connect issue_slots[3].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel \n connect issue_slots[3].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel \n connect issue_slots[3].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed \n connect issue_slots[3].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm \n connect issue_slots[3].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel \n connect issue_slots[3].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename \n connect issue_slots[3].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken \n connect issue_slots[3].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob \n connect issue_slots[3].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst \n connect issue_slots[3].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx \n connect issue_slots[3].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov \n connect issue_slots[3].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc \n connect issue_slots[3].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc \n connect issue_slots[3].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret \n connect issue_slots[3].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo \n connect issue_slots[3].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence \n connect issue_slots[3].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei \n connect issue_slots[3].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence \n connect issue_slots[3].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb \n connect issue_slots[3].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type \n connect issue_slots[3].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag \n connect issue_slots[3].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask \n connect issue_slots[3].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel \n connect issue_slots[3].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint \n connect issue_slots[3].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint \n connect issue_slots[3].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint \n connect issue_slots[3].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child \n connect issue_slots[3].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child \n connect issue_slots[3].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen \n connect issue_slots[3].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen \n connect issue_slots[3].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued \n connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] \n connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] \n connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] \n connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] \n connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] \n connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] \n connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] \n connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] \n connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] \n connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] \n connect issue_slots[3].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] \n connect issue_slots[3].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] \n connect issue_slots[3].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] \n connect issue_slots[3].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] \n connect issue_slots[3].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc \n connect issue_slots[3].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc \n connect issue_slots[3].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst \n connect issue_slots[3].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst \n connect issue_slots[3].wakeup_ports[1].valid, io.wakeup_ports[1].valid \n connect issue_slots[3].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy \n connect issue_slots[3].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask \n connect issue_slots[3].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable \n connect issue_slots[3].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc \n connect issue_slots[3].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc \n connect issue_slots[3].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if \n connect issue_slots[3].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if \n connect issue_slots[3].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if \n connect issue_slots[3].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if \n connect issue_slots[3].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if \n connect issue_slots[3].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ \n connect issue_slots[3].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm \n connect issue_slots[3].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val \n connect issue_slots[3].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op \n connect issue_slots[3].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw \n connect issue_slots[3].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en \n connect issue_slots[3].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype \n connect issue_slots[3].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype \n connect issue_slots[3].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype \n connect issue_slots[3].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 \n connect issue_slots[3].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 \n connect issue_slots[3].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 \n connect issue_slots[3].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst \n connect issue_slots[3].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 \n connect issue_slots[3].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd \n connect issue_slots[3].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit \n connect issue_slots[3].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique \n connect issue_slots[3].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq \n connect issue_slots[3].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq \n connect issue_slots[3].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed \n connect issue_slots[3].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size \n connect issue_slots[3].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd \n connect issue_slots[3].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause \n connect issue_slots[3].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception \n connect issue_slots[3].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst \n connect issue_slots[3].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy \n connect issue_slots[3].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy \n connect issue_slots[3].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy \n connect issue_slots[3].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy \n connect issue_slots[3].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred \n connect issue_slots[3].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 \n connect issue_slots[3].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 \n connect issue_slots[3].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 \n connect issue_slots[3].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst \n connect issue_slots[3].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx \n connect issue_slots[3].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx \n connect issue_slots[3].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx \n connect issue_slots[3].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx \n connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec \n connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags \n connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt \n connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div \n connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma \n connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint \n connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint \n connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 \n connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 \n connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 \n connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 \n connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 \n connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen \n connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst \n connect issue_slots[3].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel \n connect issue_slots[3].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel \n connect issue_slots[3].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed \n connect issue_slots[3].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm \n connect issue_slots[3].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel \n connect issue_slots[3].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename \n connect issue_slots[3].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken \n connect issue_slots[3].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob \n connect issue_slots[3].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst \n connect issue_slots[3].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx \n connect issue_slots[3].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov \n connect issue_slots[3].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc \n connect issue_slots[3].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc \n connect issue_slots[3].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret \n connect issue_slots[3].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo \n connect issue_slots[3].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence \n connect issue_slots[3].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei \n connect issue_slots[3].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence \n connect issue_slots[3].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb \n connect issue_slots[3].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type \n connect issue_slots[3].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag \n connect issue_slots[3].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask \n connect issue_slots[3].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel \n connect issue_slots[3].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint \n connect issue_slots[3].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint \n connect issue_slots[3].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint \n connect issue_slots[3].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child \n connect issue_slots[3].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child \n connect issue_slots[3].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen \n connect issue_slots[3].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen \n connect issue_slots[3].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued \n connect issue_slots[3].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] \n connect issue_slots[3].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] \n connect issue_slots[3].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] \n connect issue_slots[3].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] \n connect issue_slots[3].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] \n connect issue_slots[3].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] \n connect issue_slots[3].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] \n connect issue_slots[3].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] \n connect issue_slots[3].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] \n connect issue_slots[3].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] \n connect issue_slots[3].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] \n connect issue_slots[3].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] \n connect issue_slots[3].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] \n connect issue_slots[3].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] \n connect issue_slots[3].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc \n connect issue_slots[3].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc \n connect issue_slots[3].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst \n connect issue_slots[3].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst \n connect issue_slots[3].wakeup_ports[2].valid, io.wakeup_ports[2].valid \n connect issue_slots[3].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy \n connect issue_slots[3].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask \n connect issue_slots[3].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable \n connect issue_slots[3].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc \n connect issue_slots[3].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc \n connect issue_slots[3].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if \n connect issue_slots[3].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if \n connect issue_slots[3].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if \n connect issue_slots[3].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if \n connect issue_slots[3].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if \n connect issue_slots[3].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ \n connect issue_slots[3].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm \n connect issue_slots[3].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val \n connect issue_slots[3].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op \n connect issue_slots[3].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw \n connect issue_slots[3].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en \n connect issue_slots[3].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype \n connect issue_slots[3].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype \n connect issue_slots[3].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype \n connect issue_slots[3].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 \n connect issue_slots[3].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 \n connect issue_slots[3].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 \n connect issue_slots[3].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst \n connect issue_slots[3].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 \n connect issue_slots[3].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd \n connect issue_slots[3].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit \n connect issue_slots[3].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique \n connect issue_slots[3].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq \n connect issue_slots[3].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq \n connect issue_slots[3].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed \n connect issue_slots[3].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size \n connect issue_slots[3].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd \n connect issue_slots[3].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause \n connect issue_slots[3].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception \n connect issue_slots[3].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst \n connect issue_slots[3].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy \n connect issue_slots[3].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy \n connect issue_slots[3].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy \n connect issue_slots[3].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy \n connect issue_slots[3].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred \n connect issue_slots[3].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 \n connect issue_slots[3].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 \n connect issue_slots[3].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 \n connect issue_slots[3].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst \n connect issue_slots[3].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx \n connect issue_slots[3].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx \n connect issue_slots[3].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx \n connect issue_slots[3].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx \n connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec \n connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags \n connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt \n connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div \n connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma \n connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint \n connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint \n connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 \n connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 \n connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 \n connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 \n connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 \n connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen \n connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst \n connect issue_slots[3].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel \n connect issue_slots[3].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel \n connect issue_slots[3].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed \n connect issue_slots[3].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm \n connect issue_slots[3].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel \n connect issue_slots[3].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename \n connect issue_slots[3].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken \n connect issue_slots[3].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob \n connect issue_slots[3].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst \n connect issue_slots[3].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx \n connect issue_slots[3].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov \n connect issue_slots[3].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc \n connect issue_slots[3].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc \n connect issue_slots[3].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret \n connect issue_slots[3].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo \n connect issue_slots[3].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence \n connect issue_slots[3].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei \n connect issue_slots[3].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence \n connect issue_slots[3].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb \n connect issue_slots[3].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type \n connect issue_slots[3].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag \n connect issue_slots[3].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask \n connect issue_slots[3].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel \n connect issue_slots[3].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint \n connect issue_slots[3].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint \n connect issue_slots[3].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint \n connect issue_slots[3].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child \n connect issue_slots[3].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child \n connect issue_slots[3].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen \n connect issue_slots[3].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen \n connect issue_slots[3].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued \n connect issue_slots[3].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] \n connect issue_slots[3].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] \n connect issue_slots[3].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] \n connect issue_slots[3].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] \n connect issue_slots[3].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] \n connect issue_slots[3].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] \n connect issue_slots[3].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] \n connect issue_slots[3].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] \n connect issue_slots[3].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] \n connect issue_slots[3].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] \n connect issue_slots[3].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] \n connect issue_slots[3].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] \n connect issue_slots[3].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] \n connect issue_slots[3].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] \n connect issue_slots[3].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc \n connect issue_slots[3].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc \n connect issue_slots[3].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst \n connect issue_slots[3].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst \n connect issue_slots[3].wakeup_ports[3].valid, io.wakeup_ports[3].valid \n connect issue_slots[3].pred_wakeup_port.bits, io.pred_wakeup_port.bits \n connect issue_slots[3].pred_wakeup_port.valid, io.pred_wakeup_port.valid \n connect issue_slots[3].child_rebusys, io.child_rebusys \n connect issue_slots[3].squash_grant, io.squash_grant \n connect issue_slots[3].brupdate.b2.target_offset, io.brupdate.b2.target_offset \n connect issue_slots[3].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target \n connect issue_slots[3].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel \n connect issue_slots[3].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type \n connect issue_slots[3].brupdate.b2.taken, io.brupdate.b2.taken \n connect issue_slots[3].brupdate.b2.mispredict, io.brupdate.b2.mispredict \n connect issue_slots[3].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc \n connect issue_slots[3].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc \n connect issue_slots[3].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if \n connect issue_slots[3].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if \n connect issue_slots[3].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if \n connect issue_slots[3].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if \n connect issue_slots[3].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if \n connect issue_slots[3].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ \n connect issue_slots[3].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm \n connect issue_slots[3].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val \n connect issue_slots[3].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op \n connect issue_slots[3].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw \n connect issue_slots[3].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en \n connect issue_slots[3].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype \n connect issue_slots[3].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype \n connect issue_slots[3].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype \n connect issue_slots[3].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 \n connect issue_slots[3].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 \n connect issue_slots[3].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 \n connect issue_slots[3].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst \n connect issue_slots[3].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 \n connect issue_slots[3].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd \n connect issue_slots[3].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit \n connect issue_slots[3].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique \n connect issue_slots[3].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq \n connect issue_slots[3].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq \n connect issue_slots[3].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed \n connect issue_slots[3].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size \n connect issue_slots[3].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd \n connect issue_slots[3].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause \n connect issue_slots[3].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception \n connect issue_slots[3].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst \n connect issue_slots[3].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy \n connect issue_slots[3].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy \n connect issue_slots[3].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy \n connect issue_slots[3].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy \n connect issue_slots[3].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred \n connect issue_slots[3].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 \n connect issue_slots[3].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 \n connect issue_slots[3].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 \n connect issue_slots[3].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst \n connect issue_slots[3].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx \n connect issue_slots[3].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx \n connect issue_slots[3].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx \n connect issue_slots[3].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx \n connect issue_slots[3].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec \n connect issue_slots[3].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags \n connect issue_slots[3].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt \n connect issue_slots[3].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div \n connect issue_slots[3].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma \n connect issue_slots[3].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe \n connect issue_slots[3].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint \n connect issue_slots[3].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint \n connect issue_slots[3].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut \n connect issue_slots[3].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn \n connect issue_slots[3].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 \n connect issue_slots[3].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 \n connect issue_slots[3].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 \n connect issue_slots[3].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 \n connect issue_slots[3].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 \n connect issue_slots[3].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen \n connect issue_slots[3].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst \n connect issue_slots[3].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel \n connect issue_slots[3].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel \n connect issue_slots[3].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed \n connect issue_slots[3].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm \n connect issue_slots[3].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel \n connect issue_slots[3].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename \n connect issue_slots[3].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken \n connect issue_slots[3].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob \n connect issue_slots[3].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst \n connect issue_slots[3].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx \n connect issue_slots[3].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov \n connect issue_slots[3].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc \n connect issue_slots[3].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc \n connect issue_slots[3].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret \n connect issue_slots[3].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo \n connect issue_slots[3].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence \n connect issue_slots[3].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei \n connect issue_slots[3].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence \n connect issue_slots[3].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb \n connect issue_slots[3].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type \n connect issue_slots[3].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag \n connect issue_slots[3].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask \n connect issue_slots[3].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel \n connect issue_slots[3].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint \n connect issue_slots[3].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint \n connect issue_slots[3].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint \n connect issue_slots[3].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child \n connect issue_slots[3].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child \n connect issue_slots[3].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen \n connect issue_slots[3].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen \n connect issue_slots[3].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued \n connect issue_slots[3].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] \n connect issue_slots[3].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] \n connect issue_slots[3].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] \n connect issue_slots[3].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] \n connect issue_slots[3].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] \n connect issue_slots[3].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] \n connect issue_slots[3].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] \n connect issue_slots[3].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] \n connect issue_slots[3].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] \n connect issue_slots[3].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] \n connect issue_slots[3].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] \n connect issue_slots[3].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] \n connect issue_slots[3].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] \n connect issue_slots[3].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] \n connect issue_slots[3].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc \n connect issue_slots[3].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc \n connect issue_slots[3].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst \n connect issue_slots[3].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst \n connect issue_slots[3].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask \n connect issue_slots[3].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask \n connect issue_slots[3].kill, io.flush_pipeline \n connect issue_slots[4].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy \n connect issue_slots[4].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask \n connect issue_slots[4].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable \n connect issue_slots[4].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc \n connect issue_slots[4].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc \n connect issue_slots[4].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if \n connect issue_slots[4].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if \n connect issue_slots[4].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if \n connect issue_slots[4].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if \n connect issue_slots[4].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if \n connect issue_slots[4].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ \n connect issue_slots[4].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm \n connect issue_slots[4].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val \n connect issue_slots[4].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op \n connect issue_slots[4].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw \n connect issue_slots[4].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en \n connect issue_slots[4].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype \n connect issue_slots[4].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype \n connect issue_slots[4].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype \n connect issue_slots[4].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 \n connect issue_slots[4].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 \n connect issue_slots[4].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 \n connect issue_slots[4].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst \n connect issue_slots[4].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 \n connect issue_slots[4].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd \n connect issue_slots[4].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit \n connect issue_slots[4].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique \n connect issue_slots[4].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq \n connect issue_slots[4].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq \n connect issue_slots[4].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed \n connect issue_slots[4].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size \n connect issue_slots[4].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd \n connect issue_slots[4].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause \n connect issue_slots[4].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception \n connect issue_slots[4].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst \n connect issue_slots[4].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy \n connect issue_slots[4].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy \n connect issue_slots[4].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy \n connect issue_slots[4].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy \n connect issue_slots[4].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred \n connect issue_slots[4].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 \n connect issue_slots[4].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 \n connect issue_slots[4].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 \n connect issue_slots[4].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst \n connect issue_slots[4].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx \n connect issue_slots[4].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx \n connect issue_slots[4].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx \n connect issue_slots[4].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx \n connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec \n connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags \n connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt \n connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div \n connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma \n connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint \n connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint \n connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 \n connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 \n connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 \n connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 \n connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 \n connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen \n connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst \n connect issue_slots[4].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel \n connect issue_slots[4].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel \n connect issue_slots[4].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed \n connect issue_slots[4].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm \n connect issue_slots[4].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel \n connect issue_slots[4].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename \n connect issue_slots[4].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken \n connect issue_slots[4].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob \n connect issue_slots[4].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst \n connect issue_slots[4].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx \n connect issue_slots[4].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov \n connect issue_slots[4].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc \n connect issue_slots[4].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc \n connect issue_slots[4].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret \n connect issue_slots[4].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo \n connect issue_slots[4].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence \n connect issue_slots[4].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei \n connect issue_slots[4].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence \n connect issue_slots[4].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb \n connect issue_slots[4].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type \n connect issue_slots[4].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag \n connect issue_slots[4].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask \n connect issue_slots[4].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel \n connect issue_slots[4].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint \n connect issue_slots[4].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint \n connect issue_slots[4].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint \n connect issue_slots[4].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child \n connect issue_slots[4].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child \n connect issue_slots[4].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen \n connect issue_slots[4].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen \n connect issue_slots[4].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued \n connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] \n connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] \n connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] \n connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] \n connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] \n connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] \n connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] \n connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] \n connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] \n connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] \n connect issue_slots[4].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] \n connect issue_slots[4].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] \n connect issue_slots[4].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] \n connect issue_slots[4].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] \n connect issue_slots[4].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc \n connect issue_slots[4].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc \n connect issue_slots[4].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst \n connect issue_slots[4].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst \n connect issue_slots[4].wakeup_ports[0].valid, io.wakeup_ports[0].valid \n connect issue_slots[4].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy \n connect issue_slots[4].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask \n connect issue_slots[4].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable \n connect issue_slots[4].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc \n connect issue_slots[4].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc \n connect issue_slots[4].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if \n connect issue_slots[4].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if \n connect issue_slots[4].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if \n connect issue_slots[4].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if \n connect issue_slots[4].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if \n connect issue_slots[4].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ \n connect issue_slots[4].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm \n connect issue_slots[4].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val \n connect issue_slots[4].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op \n connect issue_slots[4].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw \n connect issue_slots[4].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en \n connect issue_slots[4].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype \n connect issue_slots[4].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype \n connect issue_slots[4].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype \n connect issue_slots[4].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 \n connect issue_slots[4].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 \n connect issue_slots[4].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 \n connect issue_slots[4].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst \n connect issue_slots[4].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 \n connect issue_slots[4].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd \n connect issue_slots[4].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit \n connect issue_slots[4].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique \n connect issue_slots[4].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq \n connect issue_slots[4].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq \n connect issue_slots[4].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed \n connect issue_slots[4].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size \n connect issue_slots[4].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd \n connect issue_slots[4].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause \n connect issue_slots[4].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception \n connect issue_slots[4].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst \n connect issue_slots[4].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy \n connect issue_slots[4].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy \n connect issue_slots[4].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy \n connect issue_slots[4].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy \n connect issue_slots[4].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred \n connect issue_slots[4].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 \n connect issue_slots[4].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 \n connect issue_slots[4].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 \n connect issue_slots[4].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst \n connect issue_slots[4].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx \n connect issue_slots[4].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx \n connect issue_slots[4].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx \n connect issue_slots[4].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx \n connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec \n connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags \n connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt \n connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div \n connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma \n connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint \n connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint \n connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 \n connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 \n connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 \n connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 \n connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 \n connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen \n connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst \n connect issue_slots[4].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel \n connect issue_slots[4].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel \n connect issue_slots[4].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed \n connect issue_slots[4].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm \n connect issue_slots[4].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel \n connect issue_slots[4].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename \n connect issue_slots[4].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken \n connect issue_slots[4].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob \n connect issue_slots[4].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst \n connect issue_slots[4].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx \n connect issue_slots[4].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov \n connect issue_slots[4].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc \n connect issue_slots[4].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc \n connect issue_slots[4].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret \n connect issue_slots[4].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo \n connect issue_slots[4].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence \n connect issue_slots[4].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei \n connect issue_slots[4].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence \n connect issue_slots[4].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb \n connect issue_slots[4].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type \n connect issue_slots[4].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag \n connect issue_slots[4].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask \n connect issue_slots[4].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel \n connect issue_slots[4].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint \n connect issue_slots[4].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint \n connect issue_slots[4].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint \n connect issue_slots[4].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child \n connect issue_slots[4].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child \n connect issue_slots[4].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen \n connect issue_slots[4].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen \n connect issue_slots[4].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued \n connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] \n connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] \n connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] \n connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] \n connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] \n connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] \n connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] \n connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] \n connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] \n connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] \n connect issue_slots[4].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] \n connect issue_slots[4].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] \n connect issue_slots[4].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] \n connect issue_slots[4].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] \n connect issue_slots[4].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc \n connect issue_slots[4].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc \n connect issue_slots[4].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst \n connect issue_slots[4].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst \n connect issue_slots[4].wakeup_ports[1].valid, io.wakeup_ports[1].valid \n connect issue_slots[4].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy \n connect issue_slots[4].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask \n connect issue_slots[4].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable \n connect issue_slots[4].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc \n connect issue_slots[4].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc \n connect issue_slots[4].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if \n connect issue_slots[4].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if \n connect issue_slots[4].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if \n connect issue_slots[4].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if \n connect issue_slots[4].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if \n connect issue_slots[4].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ \n connect issue_slots[4].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm \n connect issue_slots[4].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val \n connect issue_slots[4].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op \n connect issue_slots[4].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw \n connect issue_slots[4].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en \n connect issue_slots[4].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype \n connect issue_slots[4].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype \n connect issue_slots[4].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype \n connect issue_slots[4].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 \n connect issue_slots[4].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 \n connect issue_slots[4].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 \n connect issue_slots[4].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst \n connect issue_slots[4].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 \n connect issue_slots[4].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd \n connect issue_slots[4].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit \n connect issue_slots[4].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique \n connect issue_slots[4].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq \n connect issue_slots[4].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq \n connect issue_slots[4].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed \n connect issue_slots[4].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size \n connect issue_slots[4].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd \n connect issue_slots[4].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause \n connect issue_slots[4].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception \n connect issue_slots[4].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst \n connect issue_slots[4].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy \n connect issue_slots[4].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy \n connect issue_slots[4].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy \n connect issue_slots[4].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy \n connect issue_slots[4].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred \n connect issue_slots[4].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 \n connect issue_slots[4].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 \n connect issue_slots[4].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 \n connect issue_slots[4].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst \n connect issue_slots[4].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx \n connect issue_slots[4].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx \n connect issue_slots[4].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx \n connect issue_slots[4].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx \n connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec \n connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags \n connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt \n connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div \n connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma \n connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint \n connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint \n connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 \n connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 \n connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 \n connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 \n connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 \n connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen \n connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst \n connect issue_slots[4].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel \n connect issue_slots[4].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel \n connect issue_slots[4].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed \n connect issue_slots[4].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm \n connect issue_slots[4].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel \n connect issue_slots[4].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename \n connect issue_slots[4].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken \n connect issue_slots[4].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob \n connect issue_slots[4].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst \n connect issue_slots[4].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx \n connect issue_slots[4].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov \n connect issue_slots[4].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc \n connect issue_slots[4].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc \n connect issue_slots[4].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret \n connect issue_slots[4].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo \n connect issue_slots[4].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence \n connect issue_slots[4].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei \n connect issue_slots[4].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence \n connect issue_slots[4].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb \n connect issue_slots[4].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type \n connect issue_slots[4].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag \n connect issue_slots[4].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask \n connect issue_slots[4].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel \n connect issue_slots[4].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint \n connect issue_slots[4].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint \n connect issue_slots[4].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint \n connect issue_slots[4].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child \n connect issue_slots[4].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child \n connect issue_slots[4].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen \n connect issue_slots[4].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen \n connect issue_slots[4].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued \n connect issue_slots[4].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] \n connect issue_slots[4].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] \n connect issue_slots[4].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] \n connect issue_slots[4].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] \n connect issue_slots[4].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] \n connect issue_slots[4].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] \n connect issue_slots[4].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] \n connect issue_slots[4].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] \n connect issue_slots[4].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] \n connect issue_slots[4].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] \n connect issue_slots[4].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] \n connect issue_slots[4].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] \n connect issue_slots[4].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] \n connect issue_slots[4].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] \n connect issue_slots[4].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc \n connect issue_slots[4].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc \n connect issue_slots[4].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst \n connect issue_slots[4].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst \n connect issue_slots[4].wakeup_ports[2].valid, io.wakeup_ports[2].valid \n connect issue_slots[4].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy \n connect issue_slots[4].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask \n connect issue_slots[4].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable \n connect issue_slots[4].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc \n connect issue_slots[4].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc \n connect issue_slots[4].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if \n connect issue_slots[4].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if \n connect issue_slots[4].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if \n connect issue_slots[4].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if \n connect issue_slots[4].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if \n connect issue_slots[4].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ \n connect issue_slots[4].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm \n connect issue_slots[4].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val \n connect issue_slots[4].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op \n connect issue_slots[4].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw \n connect issue_slots[4].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en \n connect issue_slots[4].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype \n connect issue_slots[4].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype \n connect issue_slots[4].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype \n connect issue_slots[4].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 \n connect issue_slots[4].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 \n connect issue_slots[4].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 \n connect issue_slots[4].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst \n connect issue_slots[4].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 \n connect issue_slots[4].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd \n connect issue_slots[4].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit \n connect issue_slots[4].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique \n connect issue_slots[4].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq \n connect issue_slots[4].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq \n connect issue_slots[4].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed \n connect issue_slots[4].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size \n connect issue_slots[4].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd \n connect issue_slots[4].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause \n connect issue_slots[4].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception \n connect issue_slots[4].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst \n connect issue_slots[4].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy \n connect issue_slots[4].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy \n connect issue_slots[4].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy \n connect issue_slots[4].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy \n connect issue_slots[4].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred \n connect issue_slots[4].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 \n connect issue_slots[4].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 \n connect issue_slots[4].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 \n connect issue_slots[4].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst \n connect issue_slots[4].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx \n connect issue_slots[4].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx \n connect issue_slots[4].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx \n connect issue_slots[4].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx \n connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec \n connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags \n connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt \n connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div \n connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma \n connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint \n connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint \n connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 \n connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 \n connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 \n connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 \n connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 \n connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen \n connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst \n connect issue_slots[4].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel \n connect issue_slots[4].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel \n connect issue_slots[4].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed \n connect issue_slots[4].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm \n connect issue_slots[4].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel \n connect issue_slots[4].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename \n connect issue_slots[4].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken \n connect issue_slots[4].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob \n connect issue_slots[4].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst \n connect issue_slots[4].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx \n connect issue_slots[4].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov \n connect issue_slots[4].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc \n connect issue_slots[4].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc \n connect issue_slots[4].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret \n connect issue_slots[4].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo \n connect issue_slots[4].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence \n connect issue_slots[4].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei \n connect issue_slots[4].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence \n connect issue_slots[4].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb \n connect issue_slots[4].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type \n connect issue_slots[4].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag \n connect issue_slots[4].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask \n connect issue_slots[4].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel \n connect issue_slots[4].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint \n connect issue_slots[4].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint \n connect issue_slots[4].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint \n connect issue_slots[4].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child \n connect issue_slots[4].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child \n connect issue_slots[4].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen \n connect issue_slots[4].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen \n connect issue_slots[4].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued \n connect issue_slots[4].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] \n connect issue_slots[4].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] \n connect issue_slots[4].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] \n connect issue_slots[4].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] \n connect issue_slots[4].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] \n connect issue_slots[4].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] \n connect issue_slots[4].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] \n connect issue_slots[4].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] \n connect issue_slots[4].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] \n connect issue_slots[4].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] \n connect issue_slots[4].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] \n connect issue_slots[4].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] \n connect issue_slots[4].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] \n connect issue_slots[4].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] \n connect issue_slots[4].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc \n connect issue_slots[4].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc \n connect issue_slots[4].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst \n connect issue_slots[4].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst \n connect issue_slots[4].wakeup_ports[3].valid, io.wakeup_ports[3].valid \n connect issue_slots[4].pred_wakeup_port.bits, io.pred_wakeup_port.bits \n connect issue_slots[4].pred_wakeup_port.valid, io.pred_wakeup_port.valid \n connect issue_slots[4].child_rebusys, io.child_rebusys \n connect issue_slots[4].squash_grant, io.squash_grant \n connect issue_slots[4].brupdate.b2.target_offset, io.brupdate.b2.target_offset \n connect issue_slots[4].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target \n connect issue_slots[4].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel \n connect issue_slots[4].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type \n connect issue_slots[4].brupdate.b2.taken, io.brupdate.b2.taken \n connect issue_slots[4].brupdate.b2.mispredict, io.brupdate.b2.mispredict \n connect issue_slots[4].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc \n connect issue_slots[4].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc \n connect issue_slots[4].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if \n connect issue_slots[4].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if \n connect issue_slots[4].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if \n connect issue_slots[4].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if \n connect issue_slots[4].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if \n connect issue_slots[4].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ \n connect issue_slots[4].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm \n connect issue_slots[4].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val \n connect issue_slots[4].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op \n connect issue_slots[4].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw \n connect issue_slots[4].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en \n connect issue_slots[4].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype \n connect issue_slots[4].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype \n connect issue_slots[4].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype \n connect issue_slots[4].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 \n connect issue_slots[4].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 \n connect issue_slots[4].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 \n connect issue_slots[4].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst \n connect issue_slots[4].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 \n connect issue_slots[4].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd \n connect issue_slots[4].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit \n connect issue_slots[4].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique \n connect issue_slots[4].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq \n connect issue_slots[4].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq \n connect issue_slots[4].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed \n connect issue_slots[4].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size \n connect issue_slots[4].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd \n connect issue_slots[4].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause \n connect issue_slots[4].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception \n connect issue_slots[4].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst \n connect issue_slots[4].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy \n connect issue_slots[4].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy \n connect issue_slots[4].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy \n connect issue_slots[4].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy \n connect issue_slots[4].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred \n connect issue_slots[4].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 \n connect issue_slots[4].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 \n connect issue_slots[4].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 \n connect issue_slots[4].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst \n connect issue_slots[4].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx \n connect issue_slots[4].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx \n connect issue_slots[4].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx \n connect issue_slots[4].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx \n connect issue_slots[4].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec \n connect issue_slots[4].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags \n connect issue_slots[4].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt \n connect issue_slots[4].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div \n connect issue_slots[4].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma \n connect issue_slots[4].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe \n connect issue_slots[4].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint \n connect issue_slots[4].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint \n connect issue_slots[4].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut \n connect issue_slots[4].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn \n connect issue_slots[4].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 \n connect issue_slots[4].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 \n connect issue_slots[4].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 \n connect issue_slots[4].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 \n connect issue_slots[4].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 \n connect issue_slots[4].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen \n connect issue_slots[4].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst \n connect issue_slots[4].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel \n connect issue_slots[4].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel \n connect issue_slots[4].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed \n connect issue_slots[4].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm \n connect issue_slots[4].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel \n connect issue_slots[4].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename \n connect issue_slots[4].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken \n connect issue_slots[4].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob \n connect issue_slots[4].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst \n connect issue_slots[4].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx \n connect issue_slots[4].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov \n connect issue_slots[4].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc \n connect issue_slots[4].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc \n connect issue_slots[4].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret \n connect issue_slots[4].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo \n connect issue_slots[4].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence \n connect issue_slots[4].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei \n connect issue_slots[4].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence \n connect issue_slots[4].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb \n connect issue_slots[4].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type \n connect issue_slots[4].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag \n connect issue_slots[4].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask \n connect issue_slots[4].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel \n connect issue_slots[4].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint \n connect issue_slots[4].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint \n connect issue_slots[4].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint \n connect issue_slots[4].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child \n connect issue_slots[4].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child \n connect issue_slots[4].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen \n connect issue_slots[4].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen \n connect issue_slots[4].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued \n connect issue_slots[4].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] \n connect issue_slots[4].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] \n connect issue_slots[4].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] \n connect issue_slots[4].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] \n connect issue_slots[4].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] \n connect issue_slots[4].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] \n connect issue_slots[4].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] \n connect issue_slots[4].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] \n connect issue_slots[4].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] \n connect issue_slots[4].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] \n connect issue_slots[4].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] \n connect issue_slots[4].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] \n connect issue_slots[4].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] \n connect issue_slots[4].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] \n connect issue_slots[4].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc \n connect issue_slots[4].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc \n connect issue_slots[4].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst \n connect issue_slots[4].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst \n connect issue_slots[4].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask \n connect issue_slots[4].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask \n connect issue_slots[4].kill, io.flush_pipeline \n connect issue_slots[5].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy \n connect issue_slots[5].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask \n connect issue_slots[5].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable \n connect issue_slots[5].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc \n connect issue_slots[5].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc \n connect issue_slots[5].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if \n connect issue_slots[5].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if \n connect issue_slots[5].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if \n connect issue_slots[5].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if \n connect issue_slots[5].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if \n connect issue_slots[5].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ \n connect issue_slots[5].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm \n connect issue_slots[5].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val \n connect issue_slots[5].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op \n connect issue_slots[5].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw \n connect issue_slots[5].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en \n connect issue_slots[5].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype \n connect issue_slots[5].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype \n connect issue_slots[5].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype \n connect issue_slots[5].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 \n connect issue_slots[5].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 \n connect issue_slots[5].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 \n connect issue_slots[5].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst \n connect issue_slots[5].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 \n connect issue_slots[5].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd \n connect issue_slots[5].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit \n connect issue_slots[5].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique \n connect issue_slots[5].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq \n connect issue_slots[5].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq \n connect issue_slots[5].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed \n connect issue_slots[5].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size \n connect issue_slots[5].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd \n connect issue_slots[5].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause \n connect issue_slots[5].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception \n connect issue_slots[5].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst \n connect issue_slots[5].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy \n connect issue_slots[5].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy \n connect issue_slots[5].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy \n connect issue_slots[5].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy \n connect issue_slots[5].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred \n connect issue_slots[5].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 \n connect issue_slots[5].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 \n connect issue_slots[5].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 \n connect issue_slots[5].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst \n connect issue_slots[5].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx \n connect issue_slots[5].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx \n connect issue_slots[5].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx \n connect issue_slots[5].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx \n connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec \n connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags \n connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt \n connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div \n connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma \n connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint \n connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint \n connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 \n connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 \n connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 \n connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 \n connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 \n connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen \n connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst \n connect issue_slots[5].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel \n connect issue_slots[5].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel \n connect issue_slots[5].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed \n connect issue_slots[5].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm \n connect issue_slots[5].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel \n connect issue_slots[5].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename \n connect issue_slots[5].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken \n connect issue_slots[5].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob \n connect issue_slots[5].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst \n connect issue_slots[5].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx \n connect issue_slots[5].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov \n connect issue_slots[5].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc \n connect issue_slots[5].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc \n connect issue_slots[5].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret \n connect issue_slots[5].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo \n connect issue_slots[5].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence \n connect issue_slots[5].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei \n connect issue_slots[5].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence \n connect issue_slots[5].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb \n connect issue_slots[5].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type \n connect issue_slots[5].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag \n connect issue_slots[5].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask \n connect issue_slots[5].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel \n connect issue_slots[5].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint \n connect issue_slots[5].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint \n connect issue_slots[5].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint \n connect issue_slots[5].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child \n connect issue_slots[5].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child \n connect issue_slots[5].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen \n connect issue_slots[5].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen \n connect issue_slots[5].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued \n connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] \n connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] \n connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] \n connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] \n connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] \n connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] \n connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] \n connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] \n connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] \n connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] \n connect issue_slots[5].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] \n connect issue_slots[5].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] \n connect issue_slots[5].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] \n connect issue_slots[5].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] \n connect issue_slots[5].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc \n connect issue_slots[5].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc \n connect issue_slots[5].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst \n connect issue_slots[5].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst \n connect issue_slots[5].wakeup_ports[0].valid, io.wakeup_ports[0].valid \n connect issue_slots[5].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy \n connect issue_slots[5].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask \n connect issue_slots[5].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable \n connect issue_slots[5].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc \n connect issue_slots[5].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc \n connect issue_slots[5].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if \n connect issue_slots[5].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if \n connect issue_slots[5].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if \n connect issue_slots[5].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if \n connect issue_slots[5].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if \n connect issue_slots[5].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ \n connect issue_slots[5].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm \n connect issue_slots[5].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val \n connect issue_slots[5].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op \n connect issue_slots[5].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw \n connect issue_slots[5].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en \n connect issue_slots[5].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype \n connect issue_slots[5].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype \n connect issue_slots[5].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype \n connect issue_slots[5].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 \n connect issue_slots[5].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 \n connect issue_slots[5].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 \n connect issue_slots[5].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst \n connect issue_slots[5].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 \n connect issue_slots[5].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd \n connect issue_slots[5].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit \n connect issue_slots[5].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique \n connect issue_slots[5].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq \n connect issue_slots[5].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq \n connect issue_slots[5].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed \n connect issue_slots[5].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size \n connect issue_slots[5].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd \n connect issue_slots[5].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause \n connect issue_slots[5].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception \n connect issue_slots[5].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst \n connect issue_slots[5].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy \n connect issue_slots[5].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy \n connect issue_slots[5].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy \n connect issue_slots[5].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy \n connect issue_slots[5].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred \n connect issue_slots[5].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 \n connect issue_slots[5].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 \n connect issue_slots[5].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 \n connect issue_slots[5].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst \n connect issue_slots[5].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx \n connect issue_slots[5].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx \n connect issue_slots[5].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx \n connect issue_slots[5].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx \n connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec \n connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags \n connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt \n connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div \n connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma \n connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint \n connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint \n connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 \n connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 \n connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 \n connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 \n connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 \n connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen \n connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst \n connect issue_slots[5].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel \n connect issue_slots[5].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel \n connect issue_slots[5].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed \n connect issue_slots[5].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm \n connect issue_slots[5].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel \n connect issue_slots[5].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename \n connect issue_slots[5].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken \n connect issue_slots[5].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob \n connect issue_slots[5].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst \n connect issue_slots[5].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx \n connect issue_slots[5].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov \n connect issue_slots[5].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc \n connect issue_slots[5].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc \n connect issue_slots[5].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret \n connect issue_slots[5].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo \n connect issue_slots[5].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence \n connect issue_slots[5].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei \n connect issue_slots[5].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence \n connect issue_slots[5].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb \n connect issue_slots[5].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type \n connect issue_slots[5].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag \n connect issue_slots[5].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask \n connect issue_slots[5].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel \n connect issue_slots[5].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint \n connect issue_slots[5].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint \n connect issue_slots[5].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint \n connect issue_slots[5].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child \n connect issue_slots[5].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child \n connect issue_slots[5].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen \n connect issue_slots[5].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen \n connect issue_slots[5].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued \n connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] \n connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] \n connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] \n connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] \n connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] \n connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] \n connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] \n connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] \n connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] \n connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] \n connect issue_slots[5].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] \n connect issue_slots[5].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] \n connect issue_slots[5].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] \n connect issue_slots[5].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] \n connect issue_slots[5].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc \n connect issue_slots[5].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc \n connect issue_slots[5].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst \n connect issue_slots[5].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst \n connect issue_slots[5].wakeup_ports[1].valid, io.wakeup_ports[1].valid \n connect issue_slots[5].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy \n connect issue_slots[5].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask \n connect issue_slots[5].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable \n connect issue_slots[5].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc \n connect issue_slots[5].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc \n connect issue_slots[5].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if \n connect issue_slots[5].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if \n connect issue_slots[5].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if \n connect issue_slots[5].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if \n connect issue_slots[5].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if \n connect issue_slots[5].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ \n connect issue_slots[5].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm \n connect issue_slots[5].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val \n connect issue_slots[5].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op \n connect issue_slots[5].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw \n connect issue_slots[5].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en \n connect issue_slots[5].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype \n connect issue_slots[5].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype \n connect issue_slots[5].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype \n connect issue_slots[5].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 \n connect issue_slots[5].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 \n connect issue_slots[5].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 \n connect issue_slots[5].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst \n connect issue_slots[5].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 \n connect issue_slots[5].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd \n connect issue_slots[5].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit \n connect issue_slots[5].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique \n connect issue_slots[5].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq \n connect issue_slots[5].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq \n connect issue_slots[5].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed \n connect issue_slots[5].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size \n connect issue_slots[5].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd \n connect issue_slots[5].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause \n connect issue_slots[5].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception \n connect issue_slots[5].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst \n connect issue_slots[5].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy \n connect issue_slots[5].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy \n connect issue_slots[5].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy \n connect issue_slots[5].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy \n connect issue_slots[5].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred \n connect issue_slots[5].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 \n connect issue_slots[5].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 \n connect issue_slots[5].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 \n connect issue_slots[5].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst \n connect issue_slots[5].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx \n connect issue_slots[5].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx \n connect issue_slots[5].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx \n connect issue_slots[5].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx \n connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec \n connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags \n connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt \n connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div \n connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma \n connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint \n connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint \n connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 \n connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 \n connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 \n connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 \n connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 \n connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen \n connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst \n connect issue_slots[5].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel \n connect issue_slots[5].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel \n connect issue_slots[5].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed \n connect issue_slots[5].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm \n connect issue_slots[5].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel \n connect issue_slots[5].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename \n connect issue_slots[5].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken \n connect issue_slots[5].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob \n connect issue_slots[5].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst \n connect issue_slots[5].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx \n connect issue_slots[5].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov \n connect issue_slots[5].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc \n connect issue_slots[5].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc \n connect issue_slots[5].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret \n connect issue_slots[5].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo \n connect issue_slots[5].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence \n connect issue_slots[5].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei \n connect issue_slots[5].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence \n connect issue_slots[5].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb \n connect issue_slots[5].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type \n connect issue_slots[5].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag \n connect issue_slots[5].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask \n connect issue_slots[5].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel \n connect issue_slots[5].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint \n connect issue_slots[5].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint \n connect issue_slots[5].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint \n connect issue_slots[5].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child \n connect issue_slots[5].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child \n connect issue_slots[5].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen \n connect issue_slots[5].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen \n connect issue_slots[5].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued \n connect issue_slots[5].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] \n connect issue_slots[5].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] \n connect issue_slots[5].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] \n connect issue_slots[5].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] \n connect issue_slots[5].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] \n connect issue_slots[5].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] \n connect issue_slots[5].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] \n connect issue_slots[5].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] \n connect issue_slots[5].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] \n connect issue_slots[5].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] \n connect issue_slots[5].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] \n connect issue_slots[5].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] \n connect issue_slots[5].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] \n connect issue_slots[5].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] \n connect issue_slots[5].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc \n connect issue_slots[5].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc \n connect issue_slots[5].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst \n connect issue_slots[5].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst \n connect issue_slots[5].wakeup_ports[2].valid, io.wakeup_ports[2].valid \n connect issue_slots[5].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy \n connect issue_slots[5].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask \n connect issue_slots[5].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable \n connect issue_slots[5].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc \n connect issue_slots[5].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc \n connect issue_slots[5].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if \n connect issue_slots[5].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if \n connect issue_slots[5].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if \n connect issue_slots[5].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if \n connect issue_slots[5].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if \n connect issue_slots[5].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ \n connect issue_slots[5].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm \n connect issue_slots[5].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val \n connect issue_slots[5].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op \n connect issue_slots[5].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw \n connect issue_slots[5].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en \n connect issue_slots[5].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype \n connect issue_slots[5].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype \n connect issue_slots[5].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype \n connect issue_slots[5].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 \n connect issue_slots[5].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 \n connect issue_slots[5].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 \n connect issue_slots[5].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst \n connect issue_slots[5].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 \n connect issue_slots[5].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd \n connect issue_slots[5].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit \n connect issue_slots[5].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique \n connect issue_slots[5].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq \n connect issue_slots[5].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq \n connect issue_slots[5].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed \n connect issue_slots[5].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size \n connect issue_slots[5].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd \n connect issue_slots[5].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause \n connect issue_slots[5].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception \n connect issue_slots[5].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst \n connect issue_slots[5].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy \n connect issue_slots[5].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy \n connect issue_slots[5].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy \n connect issue_slots[5].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy \n connect issue_slots[5].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred \n connect issue_slots[5].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 \n connect issue_slots[5].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 \n connect issue_slots[5].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 \n connect issue_slots[5].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst \n connect issue_slots[5].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx \n connect issue_slots[5].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx \n connect issue_slots[5].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx \n connect issue_slots[5].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx \n connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec \n connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags \n connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt \n connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div \n connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma \n connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint \n connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint \n connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 \n connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 \n connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 \n connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 \n connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 \n connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen \n connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst \n connect issue_slots[5].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel \n connect issue_slots[5].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel \n connect issue_slots[5].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed \n connect issue_slots[5].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm \n connect issue_slots[5].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel \n connect issue_slots[5].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename \n connect issue_slots[5].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken \n connect issue_slots[5].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob \n connect issue_slots[5].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst \n connect issue_slots[5].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx \n connect issue_slots[5].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov \n connect issue_slots[5].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc \n connect issue_slots[5].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc \n connect issue_slots[5].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret \n connect issue_slots[5].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo \n connect issue_slots[5].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence \n connect issue_slots[5].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei \n connect issue_slots[5].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence \n connect issue_slots[5].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb \n connect issue_slots[5].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type \n connect issue_slots[5].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag \n connect issue_slots[5].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask \n connect issue_slots[5].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel \n connect issue_slots[5].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint \n connect issue_slots[5].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint \n connect issue_slots[5].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint \n connect issue_slots[5].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child \n connect issue_slots[5].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child \n connect issue_slots[5].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen \n connect issue_slots[5].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen \n connect issue_slots[5].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued \n connect issue_slots[5].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] \n connect issue_slots[5].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] \n connect issue_slots[5].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] \n connect issue_slots[5].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] \n connect issue_slots[5].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] \n connect issue_slots[5].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] \n connect issue_slots[5].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] \n connect issue_slots[5].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] \n connect issue_slots[5].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] \n connect issue_slots[5].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] \n connect issue_slots[5].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] \n connect issue_slots[5].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] \n connect issue_slots[5].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] \n connect issue_slots[5].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] \n connect issue_slots[5].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc \n connect issue_slots[5].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc \n connect issue_slots[5].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst \n connect issue_slots[5].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst \n connect issue_slots[5].wakeup_ports[3].valid, io.wakeup_ports[3].valid \n connect issue_slots[5].pred_wakeup_port.bits, io.pred_wakeup_port.bits \n connect issue_slots[5].pred_wakeup_port.valid, io.pred_wakeup_port.valid \n connect issue_slots[5].child_rebusys, io.child_rebusys \n connect issue_slots[5].squash_grant, io.squash_grant \n connect issue_slots[5].brupdate.b2.target_offset, io.brupdate.b2.target_offset \n connect issue_slots[5].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target \n connect issue_slots[5].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel \n connect issue_slots[5].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type \n connect issue_slots[5].brupdate.b2.taken, io.brupdate.b2.taken \n connect issue_slots[5].brupdate.b2.mispredict, io.brupdate.b2.mispredict \n connect issue_slots[5].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc \n connect issue_slots[5].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc \n connect issue_slots[5].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if \n connect issue_slots[5].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if \n connect issue_slots[5].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if \n connect issue_slots[5].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if \n connect issue_slots[5].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if \n connect issue_slots[5].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ \n connect issue_slots[5].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm \n connect issue_slots[5].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val \n connect issue_slots[5].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op \n connect issue_slots[5].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw \n connect issue_slots[5].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en \n connect issue_slots[5].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype \n connect issue_slots[5].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype \n connect issue_slots[5].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype \n connect issue_slots[5].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 \n connect issue_slots[5].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 \n connect issue_slots[5].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 \n connect issue_slots[5].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst \n connect issue_slots[5].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 \n connect issue_slots[5].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd \n connect issue_slots[5].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit \n connect issue_slots[5].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique \n connect issue_slots[5].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq \n connect issue_slots[5].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq \n connect issue_slots[5].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed \n connect issue_slots[5].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size \n connect issue_slots[5].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd \n connect issue_slots[5].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause \n connect issue_slots[5].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception \n connect issue_slots[5].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst \n connect issue_slots[5].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy \n connect issue_slots[5].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy \n connect issue_slots[5].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy \n connect issue_slots[5].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy \n connect issue_slots[5].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred \n connect issue_slots[5].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 \n connect issue_slots[5].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 \n connect issue_slots[5].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 \n connect issue_slots[5].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst \n connect issue_slots[5].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx \n connect issue_slots[5].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx \n connect issue_slots[5].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx \n connect issue_slots[5].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx \n connect issue_slots[5].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec \n connect issue_slots[5].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags \n connect issue_slots[5].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt \n connect issue_slots[5].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div \n connect issue_slots[5].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma \n connect issue_slots[5].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe \n connect issue_slots[5].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint \n connect issue_slots[5].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint \n connect issue_slots[5].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut \n connect issue_slots[5].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn \n connect issue_slots[5].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 \n connect issue_slots[5].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 \n connect issue_slots[5].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 \n connect issue_slots[5].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 \n connect issue_slots[5].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 \n connect issue_slots[5].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen \n connect issue_slots[5].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst \n connect issue_slots[5].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel \n connect issue_slots[5].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel \n connect issue_slots[5].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed \n connect issue_slots[5].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm \n connect issue_slots[5].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel \n connect issue_slots[5].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename \n connect issue_slots[5].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken \n connect issue_slots[5].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob \n connect issue_slots[5].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst \n connect issue_slots[5].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx \n connect issue_slots[5].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov \n connect issue_slots[5].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc \n connect issue_slots[5].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc \n connect issue_slots[5].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret \n connect issue_slots[5].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo \n connect issue_slots[5].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence \n connect issue_slots[5].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei \n connect issue_slots[5].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence \n connect issue_slots[5].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb \n connect issue_slots[5].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type \n connect issue_slots[5].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag \n connect issue_slots[5].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask \n connect issue_slots[5].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel \n connect issue_slots[5].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint \n connect issue_slots[5].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint \n connect issue_slots[5].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint \n connect issue_slots[5].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child \n connect issue_slots[5].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child \n connect issue_slots[5].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen \n connect issue_slots[5].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen \n connect issue_slots[5].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued \n connect issue_slots[5].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] \n connect issue_slots[5].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] \n connect issue_slots[5].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] \n connect issue_slots[5].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] \n connect issue_slots[5].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] \n connect issue_slots[5].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] \n connect issue_slots[5].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] \n connect issue_slots[5].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] \n connect issue_slots[5].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] \n connect issue_slots[5].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] \n connect issue_slots[5].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] \n connect issue_slots[5].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] \n connect issue_slots[5].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] \n connect issue_slots[5].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] \n connect issue_slots[5].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc \n connect issue_slots[5].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc \n connect issue_slots[5].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst \n connect issue_slots[5].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst \n connect issue_slots[5].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask \n connect issue_slots[5].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask \n connect issue_slots[5].kill, io.flush_pipeline \n connect issue_slots[6].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy \n connect issue_slots[6].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask \n connect issue_slots[6].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable \n connect issue_slots[6].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc \n connect issue_slots[6].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc \n connect issue_slots[6].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if \n connect issue_slots[6].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if \n connect issue_slots[6].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if \n connect issue_slots[6].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if \n connect issue_slots[6].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if \n connect issue_slots[6].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ \n connect issue_slots[6].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm \n connect issue_slots[6].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val \n connect issue_slots[6].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op \n connect issue_slots[6].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw \n connect issue_slots[6].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en \n connect issue_slots[6].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype \n connect issue_slots[6].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype \n connect issue_slots[6].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype \n connect issue_slots[6].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 \n connect issue_slots[6].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 \n connect issue_slots[6].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 \n connect issue_slots[6].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst \n connect issue_slots[6].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 \n connect issue_slots[6].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd \n connect issue_slots[6].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit \n connect issue_slots[6].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique \n connect issue_slots[6].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq \n connect issue_slots[6].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq \n connect issue_slots[6].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed \n connect issue_slots[6].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size \n connect issue_slots[6].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd \n connect issue_slots[6].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause \n connect issue_slots[6].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception \n connect issue_slots[6].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst \n connect issue_slots[6].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy \n connect issue_slots[6].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy \n connect issue_slots[6].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy \n connect issue_slots[6].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy \n connect issue_slots[6].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred \n connect issue_slots[6].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 \n connect issue_slots[6].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 \n connect issue_slots[6].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 \n connect issue_slots[6].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst \n connect issue_slots[6].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx \n connect issue_slots[6].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx \n connect issue_slots[6].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx \n connect issue_slots[6].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx \n connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec \n connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags \n connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt \n connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div \n connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma \n connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint \n connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint \n connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 \n connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 \n connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 \n connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 \n connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 \n connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen \n connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst \n connect issue_slots[6].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel \n connect issue_slots[6].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel \n connect issue_slots[6].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed \n connect issue_slots[6].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm \n connect issue_slots[6].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel \n connect issue_slots[6].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename \n connect issue_slots[6].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken \n connect issue_slots[6].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob \n connect issue_slots[6].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst \n connect issue_slots[6].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx \n connect issue_slots[6].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov \n connect issue_slots[6].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc \n connect issue_slots[6].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc \n connect issue_slots[6].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret \n connect issue_slots[6].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo \n connect issue_slots[6].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence \n connect issue_slots[6].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei \n connect issue_slots[6].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence \n connect issue_slots[6].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb \n connect issue_slots[6].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type \n connect issue_slots[6].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag \n connect issue_slots[6].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask \n connect issue_slots[6].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel \n connect issue_slots[6].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint \n connect issue_slots[6].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint \n connect issue_slots[6].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint \n connect issue_slots[6].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child \n connect issue_slots[6].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child \n connect issue_slots[6].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen \n connect issue_slots[6].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen \n connect issue_slots[6].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued \n connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] \n connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] \n connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] \n connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] \n connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] \n connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] \n connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] \n connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] \n connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] \n connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] \n connect issue_slots[6].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] \n connect issue_slots[6].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] \n connect issue_slots[6].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] \n connect issue_slots[6].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] \n connect issue_slots[6].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc \n connect issue_slots[6].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc \n connect issue_slots[6].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst \n connect issue_slots[6].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst \n connect issue_slots[6].wakeup_ports[0].valid, io.wakeup_ports[0].valid \n connect issue_slots[6].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy \n connect issue_slots[6].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask \n connect issue_slots[6].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable \n connect issue_slots[6].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc \n connect issue_slots[6].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc \n connect issue_slots[6].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if \n connect issue_slots[6].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if \n connect issue_slots[6].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if \n connect issue_slots[6].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if \n connect issue_slots[6].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if \n connect issue_slots[6].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ \n connect issue_slots[6].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm \n connect issue_slots[6].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val \n connect issue_slots[6].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op \n connect issue_slots[6].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw \n connect issue_slots[6].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en \n connect issue_slots[6].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype \n connect issue_slots[6].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype \n connect issue_slots[6].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype \n connect issue_slots[6].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 \n connect issue_slots[6].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 \n connect issue_slots[6].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 \n connect issue_slots[6].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst \n connect issue_slots[6].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 \n connect issue_slots[6].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd \n connect issue_slots[6].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit \n connect issue_slots[6].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique \n connect issue_slots[6].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq \n connect issue_slots[6].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq \n connect issue_slots[6].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed \n connect issue_slots[6].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size \n connect issue_slots[6].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd \n connect issue_slots[6].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause \n connect issue_slots[6].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception \n connect issue_slots[6].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst \n connect issue_slots[6].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy \n connect issue_slots[6].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy \n connect issue_slots[6].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy \n connect issue_slots[6].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy \n connect issue_slots[6].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred \n connect issue_slots[6].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 \n connect issue_slots[6].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 \n connect issue_slots[6].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 \n connect issue_slots[6].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst \n connect issue_slots[6].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx \n connect issue_slots[6].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx \n connect issue_slots[6].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx \n connect issue_slots[6].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx \n connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec \n connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags \n connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt \n connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div \n connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma \n connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint \n connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint \n connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 \n connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 \n connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 \n connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 \n connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 \n connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen \n connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst \n connect issue_slots[6].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel \n connect issue_slots[6].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel \n connect issue_slots[6].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed \n connect issue_slots[6].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm \n connect issue_slots[6].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel \n connect issue_slots[6].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename \n connect issue_slots[6].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken \n connect issue_slots[6].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob \n connect issue_slots[6].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst \n connect issue_slots[6].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx \n connect issue_slots[6].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov \n connect issue_slots[6].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc \n connect issue_slots[6].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc \n connect issue_slots[6].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret \n connect issue_slots[6].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo \n connect issue_slots[6].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence \n connect issue_slots[6].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei \n connect issue_slots[6].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence \n connect issue_slots[6].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb \n connect issue_slots[6].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type \n connect issue_slots[6].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag \n connect issue_slots[6].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask \n connect issue_slots[6].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel \n connect issue_slots[6].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint \n connect issue_slots[6].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint \n connect issue_slots[6].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint \n connect issue_slots[6].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child \n connect issue_slots[6].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child \n connect issue_slots[6].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen \n connect issue_slots[6].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen \n connect issue_slots[6].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued \n connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] \n connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] \n connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] \n connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] \n connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] \n connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] \n connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] \n connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] \n connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] \n connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] \n connect issue_slots[6].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] \n connect issue_slots[6].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] \n connect issue_slots[6].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] \n connect issue_slots[6].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] \n connect issue_slots[6].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc \n connect issue_slots[6].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc \n connect issue_slots[6].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst \n connect issue_slots[6].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst \n connect issue_slots[6].wakeup_ports[1].valid, io.wakeup_ports[1].valid \n connect issue_slots[6].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy \n connect issue_slots[6].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask \n connect issue_slots[6].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable \n connect issue_slots[6].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc \n connect issue_slots[6].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc \n connect issue_slots[6].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if \n connect issue_slots[6].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if \n connect issue_slots[6].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if \n connect issue_slots[6].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if \n connect issue_slots[6].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if \n connect issue_slots[6].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ \n connect issue_slots[6].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm \n connect issue_slots[6].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val \n connect issue_slots[6].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op \n connect issue_slots[6].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw \n connect issue_slots[6].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en \n connect issue_slots[6].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype \n connect issue_slots[6].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype \n connect issue_slots[6].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype \n connect issue_slots[6].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 \n connect issue_slots[6].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 \n connect issue_slots[6].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 \n connect issue_slots[6].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst \n connect issue_slots[6].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 \n connect issue_slots[6].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd \n connect issue_slots[6].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit \n connect issue_slots[6].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique \n connect issue_slots[6].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq \n connect issue_slots[6].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq \n connect issue_slots[6].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed \n connect issue_slots[6].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size \n connect issue_slots[6].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd \n connect issue_slots[6].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause \n connect issue_slots[6].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception \n connect issue_slots[6].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst \n connect issue_slots[6].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy \n connect issue_slots[6].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy \n connect issue_slots[6].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy \n connect issue_slots[6].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy \n connect issue_slots[6].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred \n connect issue_slots[6].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 \n connect issue_slots[6].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 \n connect issue_slots[6].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 \n connect issue_slots[6].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst \n connect issue_slots[6].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx \n connect issue_slots[6].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx \n connect issue_slots[6].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx \n connect issue_slots[6].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx \n connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec \n connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags \n connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt \n connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div \n connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma \n connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint \n connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint \n connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 \n connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 \n connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 \n connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 \n connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 \n connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen \n connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst \n connect issue_slots[6].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel \n connect issue_slots[6].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel \n connect issue_slots[6].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed \n connect issue_slots[6].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm \n connect issue_slots[6].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel \n connect issue_slots[6].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename \n connect issue_slots[6].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken \n connect issue_slots[6].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob \n connect issue_slots[6].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst \n connect issue_slots[6].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx \n connect issue_slots[6].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov \n connect issue_slots[6].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc \n connect issue_slots[6].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc \n connect issue_slots[6].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret \n connect issue_slots[6].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo \n connect issue_slots[6].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence \n connect issue_slots[6].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei \n connect issue_slots[6].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence \n connect issue_slots[6].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb \n connect issue_slots[6].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type \n connect issue_slots[6].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag \n connect issue_slots[6].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask \n connect issue_slots[6].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel \n connect issue_slots[6].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint \n connect issue_slots[6].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint \n connect issue_slots[6].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint \n connect issue_slots[6].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child \n connect issue_slots[6].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child \n connect issue_slots[6].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen \n connect issue_slots[6].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen \n connect issue_slots[6].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued \n connect issue_slots[6].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] \n connect issue_slots[6].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] \n connect issue_slots[6].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] \n connect issue_slots[6].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] \n connect issue_slots[6].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] \n connect issue_slots[6].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] \n connect issue_slots[6].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] \n connect issue_slots[6].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] \n connect issue_slots[6].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] \n connect issue_slots[6].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] \n connect issue_slots[6].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] \n connect issue_slots[6].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] \n connect issue_slots[6].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] \n connect issue_slots[6].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] \n connect issue_slots[6].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc \n connect issue_slots[6].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc \n connect issue_slots[6].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst \n connect issue_slots[6].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst \n connect issue_slots[6].wakeup_ports[2].valid, io.wakeup_ports[2].valid \n connect issue_slots[6].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy \n connect issue_slots[6].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask \n connect issue_slots[6].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable \n connect issue_slots[6].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc \n connect issue_slots[6].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc \n connect issue_slots[6].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if \n connect issue_slots[6].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if \n connect issue_slots[6].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if \n connect issue_slots[6].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if \n connect issue_slots[6].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if \n connect issue_slots[6].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ \n connect issue_slots[6].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm \n connect issue_slots[6].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val \n connect issue_slots[6].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op \n connect issue_slots[6].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw \n connect issue_slots[6].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en \n connect issue_slots[6].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype \n connect issue_slots[6].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype \n connect issue_slots[6].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype \n connect issue_slots[6].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 \n connect issue_slots[6].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 \n connect issue_slots[6].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 \n connect issue_slots[6].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst \n connect issue_slots[6].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 \n connect issue_slots[6].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd \n connect issue_slots[6].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit \n connect issue_slots[6].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique \n connect issue_slots[6].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq \n connect issue_slots[6].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq \n connect issue_slots[6].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed \n connect issue_slots[6].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size \n connect issue_slots[6].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd \n connect issue_slots[6].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause \n connect issue_slots[6].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception \n connect issue_slots[6].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst \n connect issue_slots[6].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy \n connect issue_slots[6].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy \n connect issue_slots[6].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy \n connect issue_slots[6].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy \n connect issue_slots[6].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred \n connect issue_slots[6].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 \n connect issue_slots[6].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 \n connect issue_slots[6].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 \n connect issue_slots[6].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst \n connect issue_slots[6].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx \n connect issue_slots[6].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx \n connect issue_slots[6].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx \n connect issue_slots[6].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx \n connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec \n connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags \n connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt \n connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div \n connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma \n connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint \n connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint \n connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 \n connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 \n connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 \n connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 \n connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 \n connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen \n connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst \n connect issue_slots[6].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel \n connect issue_slots[6].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel \n connect issue_slots[6].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed \n connect issue_slots[6].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm \n connect issue_slots[6].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel \n connect issue_slots[6].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename \n connect issue_slots[6].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken \n connect issue_slots[6].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob \n connect issue_slots[6].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst \n connect issue_slots[6].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx \n connect issue_slots[6].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov \n connect issue_slots[6].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc \n connect issue_slots[6].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc \n connect issue_slots[6].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret \n connect issue_slots[6].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo \n connect issue_slots[6].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence \n connect issue_slots[6].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei \n connect issue_slots[6].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence \n connect issue_slots[6].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb \n connect issue_slots[6].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type \n connect issue_slots[6].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag \n connect issue_slots[6].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask \n connect issue_slots[6].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel \n connect issue_slots[6].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint \n connect issue_slots[6].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint \n connect issue_slots[6].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint \n connect issue_slots[6].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child \n connect issue_slots[6].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child \n connect issue_slots[6].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen \n connect issue_slots[6].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen \n connect issue_slots[6].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued \n connect issue_slots[6].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] \n connect issue_slots[6].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] \n connect issue_slots[6].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] \n connect issue_slots[6].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] \n connect issue_slots[6].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] \n connect issue_slots[6].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] \n connect issue_slots[6].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] \n connect issue_slots[6].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] \n connect issue_slots[6].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] \n connect issue_slots[6].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] \n connect issue_slots[6].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] \n connect issue_slots[6].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] \n connect issue_slots[6].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] \n connect issue_slots[6].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] \n connect issue_slots[6].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc \n connect issue_slots[6].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc \n connect issue_slots[6].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst \n connect issue_slots[6].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst \n connect issue_slots[6].wakeup_ports[3].valid, io.wakeup_ports[3].valid \n connect issue_slots[6].pred_wakeup_port.bits, io.pred_wakeup_port.bits \n connect issue_slots[6].pred_wakeup_port.valid, io.pred_wakeup_port.valid \n connect issue_slots[6].child_rebusys, io.child_rebusys \n connect issue_slots[6].squash_grant, io.squash_grant \n connect issue_slots[6].brupdate.b2.target_offset, io.brupdate.b2.target_offset \n connect issue_slots[6].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target \n connect issue_slots[6].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel \n connect issue_slots[6].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type \n connect issue_slots[6].brupdate.b2.taken, io.brupdate.b2.taken \n connect issue_slots[6].brupdate.b2.mispredict, io.brupdate.b2.mispredict \n connect issue_slots[6].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc \n connect issue_slots[6].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc \n connect issue_slots[6].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if \n connect issue_slots[6].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if \n connect issue_slots[6].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if \n connect issue_slots[6].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if \n connect issue_slots[6].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if \n connect issue_slots[6].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ \n connect issue_slots[6].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm \n connect issue_slots[6].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val \n connect issue_slots[6].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op \n connect issue_slots[6].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw \n connect issue_slots[6].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en \n connect issue_slots[6].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype \n connect issue_slots[6].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype \n connect issue_slots[6].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype \n connect issue_slots[6].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 \n connect issue_slots[6].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 \n connect issue_slots[6].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 \n connect issue_slots[6].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst \n connect issue_slots[6].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 \n connect issue_slots[6].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd \n connect issue_slots[6].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit \n connect issue_slots[6].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique \n connect issue_slots[6].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq \n connect issue_slots[6].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq \n connect issue_slots[6].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed \n connect issue_slots[6].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size \n connect issue_slots[6].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd \n connect issue_slots[6].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause \n connect issue_slots[6].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception \n connect issue_slots[6].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst \n connect issue_slots[6].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy \n connect issue_slots[6].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy \n connect issue_slots[6].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy \n connect issue_slots[6].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy \n connect issue_slots[6].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred \n connect issue_slots[6].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 \n connect issue_slots[6].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 \n connect issue_slots[6].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 \n connect issue_slots[6].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst \n connect issue_slots[6].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx \n connect issue_slots[6].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx \n connect issue_slots[6].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx \n connect issue_slots[6].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx \n connect issue_slots[6].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec \n connect issue_slots[6].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags \n connect issue_slots[6].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt \n connect issue_slots[6].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div \n connect issue_slots[6].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma \n connect issue_slots[6].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe \n connect issue_slots[6].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint \n connect issue_slots[6].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint \n connect issue_slots[6].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut \n connect issue_slots[6].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn \n connect issue_slots[6].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 \n connect issue_slots[6].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 \n connect issue_slots[6].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 \n connect issue_slots[6].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 \n connect issue_slots[6].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 \n connect issue_slots[6].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen \n connect issue_slots[6].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst \n connect issue_slots[6].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel \n connect issue_slots[6].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel \n connect issue_slots[6].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed \n connect issue_slots[6].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm \n connect issue_slots[6].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel \n connect issue_slots[6].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename \n connect issue_slots[6].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken \n connect issue_slots[6].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob \n connect issue_slots[6].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst \n connect issue_slots[6].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx \n connect issue_slots[6].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov \n connect issue_slots[6].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc \n connect issue_slots[6].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc \n connect issue_slots[6].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret \n connect issue_slots[6].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo \n connect issue_slots[6].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence \n connect issue_slots[6].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei \n connect issue_slots[6].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence \n connect issue_slots[6].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb \n connect issue_slots[6].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type \n connect issue_slots[6].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag \n connect issue_slots[6].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask \n connect issue_slots[6].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel \n connect issue_slots[6].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint \n connect issue_slots[6].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint \n connect issue_slots[6].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint \n connect issue_slots[6].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child \n connect issue_slots[6].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child \n connect issue_slots[6].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen \n connect issue_slots[6].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen \n connect issue_slots[6].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued \n connect issue_slots[6].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] \n connect issue_slots[6].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] \n connect issue_slots[6].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] \n connect issue_slots[6].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] \n connect issue_slots[6].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] \n connect issue_slots[6].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] \n connect issue_slots[6].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] \n connect issue_slots[6].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] \n connect issue_slots[6].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] \n connect issue_slots[6].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] \n connect issue_slots[6].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] \n connect issue_slots[6].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] \n connect issue_slots[6].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] \n connect issue_slots[6].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] \n connect issue_slots[6].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc \n connect issue_slots[6].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc \n connect issue_slots[6].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst \n connect issue_slots[6].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst \n connect issue_slots[6].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask \n connect issue_slots[6].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask \n connect issue_slots[6].kill, io.flush_pipeline \n connect issue_slots[7].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy \n connect issue_slots[7].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask \n connect issue_slots[7].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable \n connect issue_slots[7].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc \n connect issue_slots[7].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc \n connect issue_slots[7].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if \n connect issue_slots[7].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if \n connect issue_slots[7].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if \n connect issue_slots[7].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if \n connect issue_slots[7].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if \n connect issue_slots[7].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ \n connect issue_slots[7].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm \n connect issue_slots[7].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val \n connect issue_slots[7].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op \n connect issue_slots[7].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw \n connect issue_slots[7].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en \n connect issue_slots[7].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype \n connect issue_slots[7].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype \n connect issue_slots[7].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype \n connect issue_slots[7].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 \n connect issue_slots[7].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 \n connect issue_slots[7].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 \n connect issue_slots[7].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst \n connect issue_slots[7].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 \n connect issue_slots[7].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd \n connect issue_slots[7].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit \n connect issue_slots[7].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique \n connect issue_slots[7].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq \n connect issue_slots[7].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq \n connect issue_slots[7].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed \n connect issue_slots[7].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size \n connect issue_slots[7].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd \n connect issue_slots[7].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause \n connect issue_slots[7].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception \n connect issue_slots[7].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst \n connect issue_slots[7].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy \n connect issue_slots[7].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy \n connect issue_slots[7].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy \n connect issue_slots[7].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy \n connect issue_slots[7].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred \n connect issue_slots[7].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 \n connect issue_slots[7].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 \n connect issue_slots[7].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 \n connect issue_slots[7].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst \n connect issue_slots[7].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx \n connect issue_slots[7].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx \n connect issue_slots[7].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx \n connect issue_slots[7].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx \n connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec \n connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags \n connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt \n connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div \n connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma \n connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint \n connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint \n connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 \n connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 \n connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 \n connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 \n connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 \n connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen \n connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst \n connect issue_slots[7].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel \n connect issue_slots[7].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel \n connect issue_slots[7].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed \n connect issue_slots[7].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm \n connect issue_slots[7].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel \n connect issue_slots[7].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename \n connect issue_slots[7].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken \n connect issue_slots[7].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob \n connect issue_slots[7].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst \n connect issue_slots[7].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx \n connect issue_slots[7].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov \n connect issue_slots[7].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc \n connect issue_slots[7].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc \n connect issue_slots[7].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret \n connect issue_slots[7].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo \n connect issue_slots[7].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence \n connect issue_slots[7].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei \n connect issue_slots[7].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence \n connect issue_slots[7].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb \n connect issue_slots[7].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type \n connect issue_slots[7].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag \n connect issue_slots[7].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask \n connect issue_slots[7].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel \n connect issue_slots[7].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint \n connect issue_slots[7].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint \n connect issue_slots[7].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint \n connect issue_slots[7].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child \n connect issue_slots[7].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child \n connect issue_slots[7].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen \n connect issue_slots[7].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen \n connect issue_slots[7].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued \n connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] \n connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] \n connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] \n connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] \n connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] \n connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] \n connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] \n connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] \n connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] \n connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] \n connect issue_slots[7].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] \n connect issue_slots[7].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] \n connect issue_slots[7].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] \n connect issue_slots[7].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] \n connect issue_slots[7].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc \n connect issue_slots[7].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc \n connect issue_slots[7].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst \n connect issue_slots[7].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst \n connect issue_slots[7].wakeup_ports[0].valid, io.wakeup_ports[0].valid \n connect issue_slots[7].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy \n connect issue_slots[7].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask \n connect issue_slots[7].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable \n connect issue_slots[7].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc \n connect issue_slots[7].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc \n connect issue_slots[7].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if \n connect issue_slots[7].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if \n connect issue_slots[7].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if \n connect issue_slots[7].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if \n connect issue_slots[7].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if \n connect issue_slots[7].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ \n connect issue_slots[7].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm \n connect issue_slots[7].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val \n connect issue_slots[7].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op \n connect issue_slots[7].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw \n connect issue_slots[7].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en \n connect issue_slots[7].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype \n connect issue_slots[7].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype \n connect issue_slots[7].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype \n connect issue_slots[7].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 \n connect issue_slots[7].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 \n connect issue_slots[7].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 \n connect issue_slots[7].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst \n connect issue_slots[7].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 \n connect issue_slots[7].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd \n connect issue_slots[7].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit \n connect issue_slots[7].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique \n connect issue_slots[7].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq \n connect issue_slots[7].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq \n connect issue_slots[7].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed \n connect issue_slots[7].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size \n connect issue_slots[7].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd \n connect issue_slots[7].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause \n connect issue_slots[7].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception \n connect issue_slots[7].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst \n connect issue_slots[7].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy \n connect issue_slots[7].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy \n connect issue_slots[7].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy \n connect issue_slots[7].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy \n connect issue_slots[7].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred \n connect issue_slots[7].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 \n connect issue_slots[7].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 \n connect issue_slots[7].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 \n connect issue_slots[7].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst \n connect issue_slots[7].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx \n connect issue_slots[7].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx \n connect issue_slots[7].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx \n connect issue_slots[7].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx \n connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec \n connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags \n connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt \n connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div \n connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma \n connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint \n connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint \n connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 \n connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 \n connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 \n connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 \n connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 \n connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen \n connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst \n connect issue_slots[7].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel \n connect issue_slots[7].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel \n connect issue_slots[7].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed \n connect issue_slots[7].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm \n connect issue_slots[7].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel \n connect issue_slots[7].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename \n connect issue_slots[7].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken \n connect issue_slots[7].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob \n connect issue_slots[7].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst \n connect issue_slots[7].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx \n connect issue_slots[7].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov \n connect issue_slots[7].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc \n connect issue_slots[7].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc \n connect issue_slots[7].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret \n connect issue_slots[7].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo \n connect issue_slots[7].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence \n connect issue_slots[7].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei \n connect issue_slots[7].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence \n connect issue_slots[7].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb \n connect issue_slots[7].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type \n connect issue_slots[7].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag \n connect issue_slots[7].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask \n connect issue_slots[7].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel \n connect issue_slots[7].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint \n connect issue_slots[7].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint \n connect issue_slots[7].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint \n connect issue_slots[7].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child \n connect issue_slots[7].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child \n connect issue_slots[7].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen \n connect issue_slots[7].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen \n connect issue_slots[7].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued \n connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] \n connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] \n connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] \n connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] \n connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] \n connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] \n connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] \n connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] \n connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] \n connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] \n connect issue_slots[7].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] \n connect issue_slots[7].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] \n connect issue_slots[7].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] \n connect issue_slots[7].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] \n connect issue_slots[7].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc \n connect issue_slots[7].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc \n connect issue_slots[7].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst \n connect issue_slots[7].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst \n connect issue_slots[7].wakeup_ports[1].valid, io.wakeup_ports[1].valid \n connect issue_slots[7].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy \n connect issue_slots[7].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask \n connect issue_slots[7].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable \n connect issue_slots[7].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc \n connect issue_slots[7].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc \n connect issue_slots[7].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if \n connect issue_slots[7].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if \n connect issue_slots[7].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if \n connect issue_slots[7].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if \n connect issue_slots[7].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if \n connect issue_slots[7].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ \n connect issue_slots[7].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm \n connect issue_slots[7].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val \n connect issue_slots[7].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op \n connect issue_slots[7].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw \n connect issue_slots[7].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en \n connect issue_slots[7].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype \n connect issue_slots[7].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype \n connect issue_slots[7].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype \n connect issue_slots[7].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 \n connect issue_slots[7].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 \n connect issue_slots[7].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 \n connect issue_slots[7].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst \n connect issue_slots[7].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 \n connect issue_slots[7].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd \n connect issue_slots[7].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit \n connect issue_slots[7].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique \n connect issue_slots[7].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq \n connect issue_slots[7].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq \n connect issue_slots[7].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed \n connect issue_slots[7].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size \n connect issue_slots[7].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd \n connect issue_slots[7].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause \n connect issue_slots[7].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception \n connect issue_slots[7].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst \n connect issue_slots[7].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy \n connect issue_slots[7].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy \n connect issue_slots[7].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy \n connect issue_slots[7].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy \n connect issue_slots[7].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred \n connect issue_slots[7].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 \n connect issue_slots[7].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 \n connect issue_slots[7].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 \n connect issue_slots[7].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst \n connect issue_slots[7].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx \n connect issue_slots[7].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx \n connect issue_slots[7].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx \n connect issue_slots[7].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx \n connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec \n connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags \n connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt \n connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div \n connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma \n connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint \n connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint \n connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 \n connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 \n connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 \n connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 \n connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 \n connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen \n connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst \n connect issue_slots[7].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel \n connect issue_slots[7].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel \n connect issue_slots[7].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed \n connect issue_slots[7].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm \n connect issue_slots[7].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel \n connect issue_slots[7].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename \n connect issue_slots[7].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken \n connect issue_slots[7].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob \n connect issue_slots[7].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst \n connect issue_slots[7].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx \n connect issue_slots[7].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov \n connect issue_slots[7].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc \n connect issue_slots[7].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc \n connect issue_slots[7].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret \n connect issue_slots[7].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo \n connect issue_slots[7].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence \n connect issue_slots[7].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei \n connect issue_slots[7].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence \n connect issue_slots[7].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb \n connect issue_slots[7].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type \n connect issue_slots[7].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag \n connect issue_slots[7].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask \n connect issue_slots[7].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel \n connect issue_slots[7].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint \n connect issue_slots[7].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint \n connect issue_slots[7].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint \n connect issue_slots[7].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child \n connect issue_slots[7].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child \n connect issue_slots[7].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen \n connect issue_slots[7].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen \n connect issue_slots[7].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued \n connect issue_slots[7].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] \n connect issue_slots[7].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] \n connect issue_slots[7].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] \n connect issue_slots[7].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] \n connect issue_slots[7].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] \n connect issue_slots[7].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] \n connect issue_slots[7].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] \n connect issue_slots[7].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] \n connect issue_slots[7].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] \n connect issue_slots[7].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] \n connect issue_slots[7].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] \n connect issue_slots[7].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] \n connect issue_slots[7].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] \n connect issue_slots[7].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] \n connect issue_slots[7].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc \n connect issue_slots[7].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc \n connect issue_slots[7].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst \n connect issue_slots[7].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst \n connect issue_slots[7].wakeup_ports[2].valid, io.wakeup_ports[2].valid \n connect issue_slots[7].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy \n connect issue_slots[7].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask \n connect issue_slots[7].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable \n connect issue_slots[7].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc \n connect issue_slots[7].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc \n connect issue_slots[7].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if \n connect issue_slots[7].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if \n connect issue_slots[7].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if \n connect issue_slots[7].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if \n connect issue_slots[7].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if \n connect issue_slots[7].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ \n connect issue_slots[7].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm \n connect issue_slots[7].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val \n connect issue_slots[7].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op \n connect issue_slots[7].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw \n connect issue_slots[7].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en \n connect issue_slots[7].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype \n connect issue_slots[7].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype \n connect issue_slots[7].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype \n connect issue_slots[7].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 \n connect issue_slots[7].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 \n connect issue_slots[7].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 \n connect issue_slots[7].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst \n connect issue_slots[7].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 \n connect issue_slots[7].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd \n connect issue_slots[7].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit \n connect issue_slots[7].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique \n connect issue_slots[7].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq \n connect issue_slots[7].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq \n connect issue_slots[7].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed \n connect issue_slots[7].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size \n connect issue_slots[7].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd \n connect issue_slots[7].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause \n connect issue_slots[7].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception \n connect issue_slots[7].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst \n connect issue_slots[7].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy \n connect issue_slots[7].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy \n connect issue_slots[7].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy \n connect issue_slots[7].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy \n connect issue_slots[7].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred \n connect issue_slots[7].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 \n connect issue_slots[7].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 \n connect issue_slots[7].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 \n connect issue_slots[7].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst \n connect issue_slots[7].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx \n connect issue_slots[7].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx \n connect issue_slots[7].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx \n connect issue_slots[7].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx \n connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec \n connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags \n connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt \n connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div \n connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma \n connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint \n connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint \n connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 \n connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 \n connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 \n connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 \n connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 \n connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen \n connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst \n connect issue_slots[7].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel \n connect issue_slots[7].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel \n connect issue_slots[7].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed \n connect issue_slots[7].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm \n connect issue_slots[7].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel \n connect issue_slots[7].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename \n connect issue_slots[7].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken \n connect issue_slots[7].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob \n connect issue_slots[7].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst \n connect issue_slots[7].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx \n connect issue_slots[7].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov \n connect issue_slots[7].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc \n connect issue_slots[7].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc \n connect issue_slots[7].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret \n connect issue_slots[7].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo \n connect issue_slots[7].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence \n connect issue_slots[7].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei \n connect issue_slots[7].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence \n connect issue_slots[7].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb \n connect issue_slots[7].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type \n connect issue_slots[7].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag \n connect issue_slots[7].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask \n connect issue_slots[7].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel \n connect issue_slots[7].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint \n connect issue_slots[7].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint \n connect issue_slots[7].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint \n connect issue_slots[7].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child \n connect issue_slots[7].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child \n connect issue_slots[7].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen \n connect issue_slots[7].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen \n connect issue_slots[7].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued \n connect issue_slots[7].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] \n connect issue_slots[7].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] \n connect issue_slots[7].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] \n connect issue_slots[7].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] \n connect issue_slots[7].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] \n connect issue_slots[7].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] \n connect issue_slots[7].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] \n connect issue_slots[7].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] \n connect issue_slots[7].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] \n connect issue_slots[7].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] \n connect issue_slots[7].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] \n connect issue_slots[7].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] \n connect issue_slots[7].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] \n connect issue_slots[7].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] \n connect issue_slots[7].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc \n connect issue_slots[7].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc \n connect issue_slots[7].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst \n connect issue_slots[7].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst \n connect issue_slots[7].wakeup_ports[3].valid, io.wakeup_ports[3].valid \n connect issue_slots[7].pred_wakeup_port.bits, io.pred_wakeup_port.bits \n connect issue_slots[7].pred_wakeup_port.valid, io.pred_wakeup_port.valid \n connect issue_slots[7].child_rebusys, io.child_rebusys \n connect issue_slots[7].squash_grant, io.squash_grant \n connect issue_slots[7].brupdate.b2.target_offset, io.brupdate.b2.target_offset \n connect issue_slots[7].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target \n connect issue_slots[7].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel \n connect issue_slots[7].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type \n connect issue_slots[7].brupdate.b2.taken, io.brupdate.b2.taken \n connect issue_slots[7].brupdate.b2.mispredict, io.brupdate.b2.mispredict \n connect issue_slots[7].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc \n connect issue_slots[7].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc \n connect issue_slots[7].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if \n connect issue_slots[7].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if \n connect issue_slots[7].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if \n connect issue_slots[7].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if \n connect issue_slots[7].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if \n connect issue_slots[7].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ \n connect issue_slots[7].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm \n connect issue_slots[7].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val \n connect issue_slots[7].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op \n connect issue_slots[7].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw \n connect issue_slots[7].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en \n connect issue_slots[7].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype \n connect issue_slots[7].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype \n connect issue_slots[7].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype \n connect issue_slots[7].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 \n connect issue_slots[7].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 \n connect issue_slots[7].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 \n connect issue_slots[7].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst \n connect issue_slots[7].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 \n connect issue_slots[7].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd \n connect issue_slots[7].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit \n connect issue_slots[7].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique \n connect issue_slots[7].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq \n connect issue_slots[7].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq \n connect issue_slots[7].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed \n connect issue_slots[7].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size \n connect issue_slots[7].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd \n connect issue_slots[7].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause \n connect issue_slots[7].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception \n connect issue_slots[7].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst \n connect issue_slots[7].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy \n connect issue_slots[7].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy \n connect issue_slots[7].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy \n connect issue_slots[7].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy \n connect issue_slots[7].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred \n connect issue_slots[7].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 \n connect issue_slots[7].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 \n connect issue_slots[7].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 \n connect issue_slots[7].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst \n connect issue_slots[7].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx \n connect issue_slots[7].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx \n connect issue_slots[7].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx \n connect issue_slots[7].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx \n connect issue_slots[7].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec \n connect issue_slots[7].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags \n connect issue_slots[7].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt \n connect issue_slots[7].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div \n connect issue_slots[7].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma \n connect issue_slots[7].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe \n connect issue_slots[7].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint \n connect issue_slots[7].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint \n connect issue_slots[7].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut \n connect issue_slots[7].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn \n connect issue_slots[7].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 \n connect issue_slots[7].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 \n connect issue_slots[7].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 \n connect issue_slots[7].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 \n connect issue_slots[7].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 \n connect issue_slots[7].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen \n connect issue_slots[7].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst \n connect issue_slots[7].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel \n connect issue_slots[7].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel \n connect issue_slots[7].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed \n connect issue_slots[7].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm \n connect issue_slots[7].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel \n connect issue_slots[7].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename \n connect issue_slots[7].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken \n connect issue_slots[7].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob \n connect issue_slots[7].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst \n connect issue_slots[7].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx \n connect issue_slots[7].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov \n connect issue_slots[7].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc \n connect issue_slots[7].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc \n connect issue_slots[7].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret \n connect issue_slots[7].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo \n connect issue_slots[7].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence \n connect issue_slots[7].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei \n connect issue_slots[7].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence \n connect issue_slots[7].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb \n connect issue_slots[7].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type \n connect issue_slots[7].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag \n connect issue_slots[7].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask \n connect issue_slots[7].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel \n connect issue_slots[7].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint \n connect issue_slots[7].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint \n connect issue_slots[7].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint \n connect issue_slots[7].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child \n connect issue_slots[7].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child \n connect issue_slots[7].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen \n connect issue_slots[7].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen \n connect issue_slots[7].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued \n connect issue_slots[7].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] \n connect issue_slots[7].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] \n connect issue_slots[7].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] \n connect issue_slots[7].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] \n connect issue_slots[7].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] \n connect issue_slots[7].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] \n connect issue_slots[7].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] \n connect issue_slots[7].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] \n connect issue_slots[7].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] \n connect issue_slots[7].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] \n connect issue_slots[7].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] \n connect issue_slots[7].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] \n connect issue_slots[7].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] \n connect issue_slots[7].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] \n connect issue_slots[7].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc \n connect issue_slots[7].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc \n connect issue_slots[7].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst \n connect issue_slots[7].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst \n connect issue_slots[7].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask \n connect issue_slots[7].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask \n connect issue_slots[7].kill, io.flush_pipeline \n connect issue_slots[8].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy \n connect issue_slots[8].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask \n connect issue_slots[8].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable \n connect issue_slots[8].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc \n connect issue_slots[8].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc \n connect issue_slots[8].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if \n connect issue_slots[8].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if \n connect issue_slots[8].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if \n connect issue_slots[8].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if \n connect issue_slots[8].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if \n connect issue_slots[8].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ \n connect issue_slots[8].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm \n connect issue_slots[8].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val \n connect issue_slots[8].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op \n connect issue_slots[8].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw \n connect issue_slots[8].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en \n connect issue_slots[8].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype \n connect issue_slots[8].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype \n connect issue_slots[8].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype \n connect issue_slots[8].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 \n connect issue_slots[8].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 \n connect issue_slots[8].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 \n connect issue_slots[8].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst \n connect issue_slots[8].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 \n connect issue_slots[8].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd \n connect issue_slots[8].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit \n connect issue_slots[8].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique \n connect issue_slots[8].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq \n connect issue_slots[8].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq \n connect issue_slots[8].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed \n connect issue_slots[8].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size \n connect issue_slots[8].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd \n connect issue_slots[8].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause \n connect issue_slots[8].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception \n connect issue_slots[8].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst \n connect issue_slots[8].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy \n connect issue_slots[8].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy \n connect issue_slots[8].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy \n connect issue_slots[8].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy \n connect issue_slots[8].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred \n connect issue_slots[8].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 \n connect issue_slots[8].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 \n connect issue_slots[8].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 \n connect issue_slots[8].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst \n connect issue_slots[8].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx \n connect issue_slots[8].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx \n connect issue_slots[8].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx \n connect issue_slots[8].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx \n connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec \n connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags \n connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt \n connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div \n connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma \n connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint \n connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint \n connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 \n connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 \n connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 \n connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 \n connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 \n connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen \n connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst \n connect issue_slots[8].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel \n connect issue_slots[8].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel \n connect issue_slots[8].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed \n connect issue_slots[8].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm \n connect issue_slots[8].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel \n connect issue_slots[8].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename \n connect issue_slots[8].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken \n connect issue_slots[8].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob \n connect issue_slots[8].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst \n connect issue_slots[8].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx \n connect issue_slots[8].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov \n connect issue_slots[8].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc \n connect issue_slots[8].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc \n connect issue_slots[8].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret \n connect issue_slots[8].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo \n connect issue_slots[8].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence \n connect issue_slots[8].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei \n connect issue_slots[8].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence \n connect issue_slots[8].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb \n connect issue_slots[8].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type \n connect issue_slots[8].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag \n connect issue_slots[8].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask \n connect issue_slots[8].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel \n connect issue_slots[8].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint \n connect issue_slots[8].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint \n connect issue_slots[8].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint \n connect issue_slots[8].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child \n connect issue_slots[8].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child \n connect issue_slots[8].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen \n connect issue_slots[8].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen \n connect issue_slots[8].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued \n connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] \n connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] \n connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] \n connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] \n connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] \n connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] \n connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] \n connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] \n connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] \n connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] \n connect issue_slots[8].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] \n connect issue_slots[8].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] \n connect issue_slots[8].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] \n connect issue_slots[8].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] \n connect issue_slots[8].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc \n connect issue_slots[8].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc \n connect issue_slots[8].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst \n connect issue_slots[8].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst \n connect issue_slots[8].wakeup_ports[0].valid, io.wakeup_ports[0].valid \n connect issue_slots[8].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy \n connect issue_slots[8].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask \n connect issue_slots[8].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable \n connect issue_slots[8].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc \n connect issue_slots[8].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc \n connect issue_slots[8].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if \n connect issue_slots[8].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if \n connect issue_slots[8].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if \n connect issue_slots[8].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if \n connect issue_slots[8].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if \n connect issue_slots[8].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ \n connect issue_slots[8].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm \n connect issue_slots[8].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val \n connect issue_slots[8].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op \n connect issue_slots[8].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw \n connect issue_slots[8].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en \n connect issue_slots[8].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype \n connect issue_slots[8].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype \n connect issue_slots[8].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype \n connect issue_slots[8].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 \n connect issue_slots[8].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 \n connect issue_slots[8].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 \n connect issue_slots[8].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst \n connect issue_slots[8].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 \n connect issue_slots[8].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd \n connect issue_slots[8].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit \n connect issue_slots[8].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique \n connect issue_slots[8].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq \n connect issue_slots[8].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq \n connect issue_slots[8].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed \n connect issue_slots[8].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size \n connect issue_slots[8].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd \n connect issue_slots[8].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause \n connect issue_slots[8].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception \n connect issue_slots[8].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst \n connect issue_slots[8].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy \n connect issue_slots[8].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy \n connect issue_slots[8].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy \n connect issue_slots[8].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy \n connect issue_slots[8].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred \n connect issue_slots[8].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 \n connect issue_slots[8].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 \n connect issue_slots[8].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 \n connect issue_slots[8].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst \n connect issue_slots[8].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx \n connect issue_slots[8].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx \n connect issue_slots[8].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx \n connect issue_slots[8].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx \n connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec \n connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags \n connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt \n connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div \n connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma \n connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint \n connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint \n connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 \n connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 \n connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 \n connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 \n connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 \n connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen \n connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst \n connect issue_slots[8].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel \n connect issue_slots[8].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel \n connect issue_slots[8].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed \n connect issue_slots[8].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm \n connect issue_slots[8].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel \n connect issue_slots[8].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename \n connect issue_slots[8].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken \n connect issue_slots[8].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob \n connect issue_slots[8].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst \n connect issue_slots[8].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx \n connect issue_slots[8].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov \n connect issue_slots[8].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc \n connect issue_slots[8].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc \n connect issue_slots[8].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret \n connect issue_slots[8].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo \n connect issue_slots[8].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence \n connect issue_slots[8].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei \n connect issue_slots[8].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence \n connect issue_slots[8].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb \n connect issue_slots[8].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type \n connect issue_slots[8].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag \n connect issue_slots[8].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask \n connect issue_slots[8].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel \n connect issue_slots[8].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint \n connect issue_slots[8].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint \n connect issue_slots[8].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint \n connect issue_slots[8].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child \n connect issue_slots[8].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child \n connect issue_slots[8].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen \n connect issue_slots[8].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen \n connect issue_slots[8].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued \n connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] \n connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] \n connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] \n connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] \n connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] \n connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] \n connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] \n connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] \n connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] \n connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] \n connect issue_slots[8].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] \n connect issue_slots[8].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] \n connect issue_slots[8].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] \n connect issue_slots[8].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] \n connect issue_slots[8].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc \n connect issue_slots[8].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc \n connect issue_slots[8].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst \n connect issue_slots[8].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst \n connect issue_slots[8].wakeup_ports[1].valid, io.wakeup_ports[1].valid \n connect issue_slots[8].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy \n connect issue_slots[8].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask \n connect issue_slots[8].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable \n connect issue_slots[8].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc \n connect issue_slots[8].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc \n connect issue_slots[8].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if \n connect issue_slots[8].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if \n connect issue_slots[8].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if \n connect issue_slots[8].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if \n connect issue_slots[8].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if \n connect issue_slots[8].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ \n connect issue_slots[8].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm \n connect issue_slots[8].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val \n connect issue_slots[8].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op \n connect issue_slots[8].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw \n connect issue_slots[8].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en \n connect issue_slots[8].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype \n connect issue_slots[8].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype \n connect issue_slots[8].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype \n connect issue_slots[8].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 \n connect issue_slots[8].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 \n connect issue_slots[8].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 \n connect issue_slots[8].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst \n connect issue_slots[8].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 \n connect issue_slots[8].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd \n connect issue_slots[8].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit \n connect issue_slots[8].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique \n connect issue_slots[8].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq \n connect issue_slots[8].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq \n connect issue_slots[8].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed \n connect issue_slots[8].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size \n connect issue_slots[8].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd \n connect issue_slots[8].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause \n connect issue_slots[8].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception \n connect issue_slots[8].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst \n connect issue_slots[8].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy \n connect issue_slots[8].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy \n connect issue_slots[8].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy \n connect issue_slots[8].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy \n connect issue_slots[8].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred \n connect issue_slots[8].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 \n connect issue_slots[8].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 \n connect issue_slots[8].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 \n connect issue_slots[8].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst \n connect issue_slots[8].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx \n connect issue_slots[8].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx \n connect issue_slots[8].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx \n connect issue_slots[8].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx \n connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec \n connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags \n connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt \n connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div \n connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma \n connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint \n connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint \n connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 \n connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 \n connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 \n connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 \n connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 \n connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen \n connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst \n connect issue_slots[8].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel \n connect issue_slots[8].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel \n connect issue_slots[8].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed \n connect issue_slots[8].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm \n connect issue_slots[8].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel \n connect issue_slots[8].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename \n connect issue_slots[8].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken \n connect issue_slots[8].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob \n connect issue_slots[8].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst \n connect issue_slots[8].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx \n connect issue_slots[8].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov \n connect issue_slots[8].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc \n connect issue_slots[8].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc \n connect issue_slots[8].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret \n connect issue_slots[8].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo \n connect issue_slots[8].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence \n connect issue_slots[8].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei \n connect issue_slots[8].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence \n connect issue_slots[8].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb \n connect issue_slots[8].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type \n connect issue_slots[8].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag \n connect issue_slots[8].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask \n connect issue_slots[8].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel \n connect issue_slots[8].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint \n connect issue_slots[8].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint \n connect issue_slots[8].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint \n connect issue_slots[8].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child \n connect issue_slots[8].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child \n connect issue_slots[8].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen \n connect issue_slots[8].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen \n connect issue_slots[8].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued \n connect issue_slots[8].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] \n connect issue_slots[8].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] \n connect issue_slots[8].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] \n connect issue_slots[8].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] \n connect issue_slots[8].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] \n connect issue_slots[8].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] \n connect issue_slots[8].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] \n connect issue_slots[8].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] \n connect issue_slots[8].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] \n connect issue_slots[8].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] \n connect issue_slots[8].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] \n connect issue_slots[8].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] \n connect issue_slots[8].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] \n connect issue_slots[8].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] \n connect issue_slots[8].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc \n connect issue_slots[8].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc \n connect issue_slots[8].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst \n connect issue_slots[8].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst \n connect issue_slots[8].wakeup_ports[2].valid, io.wakeup_ports[2].valid \n connect issue_slots[8].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy \n connect issue_slots[8].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask \n connect issue_slots[8].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable \n connect issue_slots[8].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc \n connect issue_slots[8].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc \n connect issue_slots[8].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if \n connect issue_slots[8].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if \n connect issue_slots[8].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if \n connect issue_slots[8].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if \n connect issue_slots[8].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if \n connect issue_slots[8].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ \n connect issue_slots[8].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm \n connect issue_slots[8].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val \n connect issue_slots[8].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op \n connect issue_slots[8].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw \n connect issue_slots[8].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en \n connect issue_slots[8].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype \n connect issue_slots[8].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype \n connect issue_slots[8].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype \n connect issue_slots[8].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 \n connect issue_slots[8].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 \n connect issue_slots[8].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 \n connect issue_slots[8].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst \n connect issue_slots[8].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 \n connect issue_slots[8].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd \n connect issue_slots[8].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit \n connect issue_slots[8].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique \n connect issue_slots[8].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq \n connect issue_slots[8].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq \n connect issue_slots[8].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed \n connect issue_slots[8].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size \n connect issue_slots[8].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd \n connect issue_slots[8].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause \n connect issue_slots[8].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception \n connect issue_slots[8].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst \n connect issue_slots[8].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy \n connect issue_slots[8].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy \n connect issue_slots[8].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy \n connect issue_slots[8].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy \n connect issue_slots[8].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred \n connect issue_slots[8].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 \n connect issue_slots[8].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 \n connect issue_slots[8].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 \n connect issue_slots[8].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst \n connect issue_slots[8].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx \n connect issue_slots[8].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx \n connect issue_slots[8].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx \n connect issue_slots[8].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx \n connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec \n connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags \n connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt \n connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div \n connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma \n connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint \n connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint \n connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 \n connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 \n connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 \n connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 \n connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 \n connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen \n connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst \n connect issue_slots[8].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel \n connect issue_slots[8].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel \n connect issue_slots[8].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed \n connect issue_slots[8].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm \n connect issue_slots[8].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel \n connect issue_slots[8].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename \n connect issue_slots[8].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken \n connect issue_slots[8].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob \n connect issue_slots[8].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst \n connect issue_slots[8].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx \n connect issue_slots[8].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov \n connect issue_slots[8].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc \n connect issue_slots[8].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc \n connect issue_slots[8].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret \n connect issue_slots[8].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo \n connect issue_slots[8].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence \n connect issue_slots[8].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei \n connect issue_slots[8].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence \n connect issue_slots[8].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb \n connect issue_slots[8].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type \n connect issue_slots[8].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag \n connect issue_slots[8].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask \n connect issue_slots[8].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel \n connect issue_slots[8].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint \n connect issue_slots[8].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint \n connect issue_slots[8].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint \n connect issue_slots[8].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child \n connect issue_slots[8].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child \n connect issue_slots[8].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen \n connect issue_slots[8].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen \n connect issue_slots[8].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued \n connect issue_slots[8].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] \n connect issue_slots[8].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] \n connect issue_slots[8].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] \n connect issue_slots[8].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] \n connect issue_slots[8].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] \n connect issue_slots[8].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] \n connect issue_slots[8].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] \n connect issue_slots[8].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] \n connect issue_slots[8].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] \n connect issue_slots[8].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] \n connect issue_slots[8].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] \n connect issue_slots[8].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] \n connect issue_slots[8].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] \n connect issue_slots[8].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] \n connect issue_slots[8].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc \n connect issue_slots[8].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc \n connect issue_slots[8].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst \n connect issue_slots[8].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst \n connect issue_slots[8].wakeup_ports[3].valid, io.wakeup_ports[3].valid \n connect issue_slots[8].pred_wakeup_port.bits, io.pred_wakeup_port.bits \n connect issue_slots[8].pred_wakeup_port.valid, io.pred_wakeup_port.valid \n connect issue_slots[8].child_rebusys, io.child_rebusys \n connect issue_slots[8].squash_grant, io.squash_grant \n connect issue_slots[8].brupdate.b2.target_offset, io.brupdate.b2.target_offset \n connect issue_slots[8].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target \n connect issue_slots[8].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel \n connect issue_slots[8].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type \n connect issue_slots[8].brupdate.b2.taken, io.brupdate.b2.taken \n connect issue_slots[8].brupdate.b2.mispredict, io.brupdate.b2.mispredict \n connect issue_slots[8].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc \n connect issue_slots[8].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc \n connect issue_slots[8].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if \n connect issue_slots[8].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if \n connect issue_slots[8].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if \n connect issue_slots[8].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if \n connect issue_slots[8].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if \n connect issue_slots[8].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ \n connect issue_slots[8].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm \n connect issue_slots[8].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val \n connect issue_slots[8].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op \n connect issue_slots[8].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw \n connect issue_slots[8].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en \n connect issue_slots[8].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype \n connect issue_slots[8].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype \n connect issue_slots[8].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype \n connect issue_slots[8].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 \n connect issue_slots[8].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 \n connect issue_slots[8].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 \n connect issue_slots[8].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst \n connect issue_slots[8].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 \n connect issue_slots[8].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd \n connect issue_slots[8].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit \n connect issue_slots[8].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique \n connect issue_slots[8].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq \n connect issue_slots[8].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq \n connect issue_slots[8].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed \n connect issue_slots[8].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size \n connect issue_slots[8].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd \n connect issue_slots[8].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause \n connect issue_slots[8].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception \n connect issue_slots[8].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst \n connect issue_slots[8].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy \n connect issue_slots[8].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy \n connect issue_slots[8].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy \n connect issue_slots[8].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy \n connect issue_slots[8].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred \n connect issue_slots[8].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 \n connect issue_slots[8].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 \n connect issue_slots[8].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 \n connect issue_slots[8].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst \n connect issue_slots[8].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx \n connect issue_slots[8].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx \n connect issue_slots[8].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx \n connect issue_slots[8].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx \n connect issue_slots[8].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec \n connect issue_slots[8].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags \n connect issue_slots[8].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt \n connect issue_slots[8].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div \n connect issue_slots[8].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma \n connect issue_slots[8].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe \n connect issue_slots[8].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint \n connect issue_slots[8].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint \n connect issue_slots[8].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut \n connect issue_slots[8].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn \n connect issue_slots[8].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 \n connect issue_slots[8].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 \n connect issue_slots[8].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 \n connect issue_slots[8].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 \n connect issue_slots[8].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 \n connect issue_slots[8].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen \n connect issue_slots[8].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst \n connect issue_slots[8].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel \n connect issue_slots[8].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel \n connect issue_slots[8].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed \n connect issue_slots[8].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm \n connect issue_slots[8].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel \n connect issue_slots[8].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename \n connect issue_slots[8].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken \n connect issue_slots[8].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob \n connect issue_slots[8].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst \n connect issue_slots[8].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx \n connect issue_slots[8].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov \n connect issue_slots[8].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc \n connect issue_slots[8].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc \n connect issue_slots[8].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret \n connect issue_slots[8].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo \n connect issue_slots[8].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence \n connect issue_slots[8].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei \n connect issue_slots[8].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence \n connect issue_slots[8].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb \n connect issue_slots[8].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type \n connect issue_slots[8].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag \n connect issue_slots[8].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask \n connect issue_slots[8].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel \n connect issue_slots[8].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint \n connect issue_slots[8].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint \n connect issue_slots[8].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint \n connect issue_slots[8].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child \n connect issue_slots[8].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child \n connect issue_slots[8].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen \n connect issue_slots[8].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen \n connect issue_slots[8].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued \n connect issue_slots[8].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] \n connect issue_slots[8].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] \n connect issue_slots[8].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] \n connect issue_slots[8].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] \n connect issue_slots[8].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] \n connect issue_slots[8].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] \n connect issue_slots[8].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] \n connect issue_slots[8].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] \n connect issue_slots[8].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] \n connect issue_slots[8].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] \n connect issue_slots[8].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] \n connect issue_slots[8].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] \n connect issue_slots[8].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] \n connect issue_slots[8].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] \n connect issue_slots[8].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc \n connect issue_slots[8].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc \n connect issue_slots[8].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst \n connect issue_slots[8].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst \n connect issue_slots[8].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask \n connect issue_slots[8].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask \n connect issue_slots[8].kill, io.flush_pipeline \n connect issue_slots[9].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy \n connect issue_slots[9].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask \n connect issue_slots[9].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable \n connect issue_slots[9].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc \n connect issue_slots[9].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc \n connect issue_slots[9].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if \n connect issue_slots[9].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if \n connect issue_slots[9].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if \n connect issue_slots[9].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if \n connect issue_slots[9].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if \n connect issue_slots[9].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ \n connect issue_slots[9].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm \n connect issue_slots[9].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val \n connect issue_slots[9].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op \n connect issue_slots[9].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw \n connect issue_slots[9].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en \n connect issue_slots[9].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype \n connect issue_slots[9].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype \n connect issue_slots[9].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype \n connect issue_slots[9].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 \n connect issue_slots[9].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 \n connect issue_slots[9].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 \n connect issue_slots[9].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst \n connect issue_slots[9].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 \n connect issue_slots[9].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd \n connect issue_slots[9].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit \n connect issue_slots[9].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique \n connect issue_slots[9].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq \n connect issue_slots[9].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq \n connect issue_slots[9].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed \n connect issue_slots[9].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size \n connect issue_slots[9].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd \n connect issue_slots[9].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause \n connect issue_slots[9].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception \n connect issue_slots[9].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst \n connect issue_slots[9].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy \n connect issue_slots[9].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy \n connect issue_slots[9].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy \n connect issue_slots[9].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy \n connect issue_slots[9].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred \n connect issue_slots[9].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 \n connect issue_slots[9].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 \n connect issue_slots[9].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 \n connect issue_slots[9].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst \n connect issue_slots[9].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx \n connect issue_slots[9].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx \n connect issue_slots[9].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx \n connect issue_slots[9].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx \n connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec \n connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags \n connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt \n connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div \n connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma \n connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint \n connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint \n connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 \n connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 \n connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 \n connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 \n connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 \n connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen \n connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst \n connect issue_slots[9].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel \n connect issue_slots[9].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel \n connect issue_slots[9].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed \n connect issue_slots[9].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm \n connect issue_slots[9].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel \n connect issue_slots[9].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename \n connect issue_slots[9].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken \n connect issue_slots[9].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob \n connect issue_slots[9].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst \n connect issue_slots[9].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx \n connect issue_slots[9].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov \n connect issue_slots[9].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc \n connect issue_slots[9].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc \n connect issue_slots[9].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret \n connect issue_slots[9].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo \n connect issue_slots[9].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence \n connect issue_slots[9].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei \n connect issue_slots[9].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence \n connect issue_slots[9].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb \n connect issue_slots[9].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type \n connect issue_slots[9].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag \n connect issue_slots[9].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask \n connect issue_slots[9].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel \n connect issue_slots[9].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint \n connect issue_slots[9].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint \n connect issue_slots[9].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint \n connect issue_slots[9].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child \n connect issue_slots[9].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child \n connect issue_slots[9].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen \n connect issue_slots[9].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen \n connect issue_slots[9].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued \n connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] \n connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] \n connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] \n connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] \n connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] \n connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] \n connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] \n connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] \n connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] \n connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] \n connect issue_slots[9].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] \n connect issue_slots[9].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] \n connect issue_slots[9].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] \n connect issue_slots[9].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] \n connect issue_slots[9].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc \n connect issue_slots[9].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc \n connect issue_slots[9].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst \n connect issue_slots[9].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst \n connect issue_slots[9].wakeup_ports[0].valid, io.wakeup_ports[0].valid \n connect issue_slots[9].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy \n connect issue_slots[9].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask \n connect issue_slots[9].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable \n connect issue_slots[9].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc \n connect issue_slots[9].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc \n connect issue_slots[9].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if \n connect issue_slots[9].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if \n connect issue_slots[9].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if \n connect issue_slots[9].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if \n connect issue_slots[9].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if \n connect issue_slots[9].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ \n connect issue_slots[9].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm \n connect issue_slots[9].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val \n connect issue_slots[9].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op \n connect issue_slots[9].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw \n connect issue_slots[9].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en \n connect issue_slots[9].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype \n connect issue_slots[9].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype \n connect issue_slots[9].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype \n connect issue_slots[9].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 \n connect issue_slots[9].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 \n connect issue_slots[9].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 \n connect issue_slots[9].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst \n connect issue_slots[9].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 \n connect issue_slots[9].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd \n connect issue_slots[9].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit \n connect issue_slots[9].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique \n connect issue_slots[9].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq \n connect issue_slots[9].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq \n connect issue_slots[9].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed \n connect issue_slots[9].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size \n connect issue_slots[9].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd \n connect issue_slots[9].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause \n connect issue_slots[9].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception \n connect issue_slots[9].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst \n connect issue_slots[9].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy \n connect issue_slots[9].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy \n connect issue_slots[9].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy \n connect issue_slots[9].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy \n connect issue_slots[9].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred \n connect issue_slots[9].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 \n connect issue_slots[9].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 \n connect issue_slots[9].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 \n connect issue_slots[9].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst \n connect issue_slots[9].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx \n connect issue_slots[9].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx \n connect issue_slots[9].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx \n connect issue_slots[9].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx \n connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec \n connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags \n connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt \n connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div \n connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma \n connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint \n connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint \n connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 \n connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 \n connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 \n connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 \n connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 \n connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen \n connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst \n connect issue_slots[9].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel \n connect issue_slots[9].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel \n connect issue_slots[9].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed \n connect issue_slots[9].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm \n connect issue_slots[9].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel \n connect issue_slots[9].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename \n connect issue_slots[9].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken \n connect issue_slots[9].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob \n connect issue_slots[9].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst \n connect issue_slots[9].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx \n connect issue_slots[9].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov \n connect issue_slots[9].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc \n connect issue_slots[9].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc \n connect issue_slots[9].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret \n connect issue_slots[9].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo \n connect issue_slots[9].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence \n connect issue_slots[9].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei \n connect issue_slots[9].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence \n connect issue_slots[9].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb \n connect issue_slots[9].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type \n connect issue_slots[9].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag \n connect issue_slots[9].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask \n connect issue_slots[9].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel \n connect issue_slots[9].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint \n connect issue_slots[9].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint \n connect issue_slots[9].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint \n connect issue_slots[9].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child \n connect issue_slots[9].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child \n connect issue_slots[9].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen \n connect issue_slots[9].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen \n connect issue_slots[9].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued \n connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] \n connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] \n connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] \n connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] \n connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] \n connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] \n connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] \n connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] \n connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] \n connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] \n connect issue_slots[9].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] \n connect issue_slots[9].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] \n connect issue_slots[9].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] \n connect issue_slots[9].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] \n connect issue_slots[9].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc \n connect issue_slots[9].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc \n connect issue_slots[9].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst \n connect issue_slots[9].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst \n connect issue_slots[9].wakeup_ports[1].valid, io.wakeup_ports[1].valid \n connect issue_slots[9].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy \n connect issue_slots[9].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask \n connect issue_slots[9].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable \n connect issue_slots[9].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc \n connect issue_slots[9].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc \n connect issue_slots[9].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if \n connect issue_slots[9].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if \n connect issue_slots[9].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if \n connect issue_slots[9].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if \n connect issue_slots[9].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if \n connect issue_slots[9].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ \n connect issue_slots[9].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm \n connect issue_slots[9].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val \n connect issue_slots[9].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op \n connect issue_slots[9].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw \n connect issue_slots[9].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en \n connect issue_slots[9].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype \n connect issue_slots[9].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype \n connect issue_slots[9].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype \n connect issue_slots[9].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 \n connect issue_slots[9].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 \n connect issue_slots[9].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 \n connect issue_slots[9].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst \n connect issue_slots[9].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 \n connect issue_slots[9].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd \n connect issue_slots[9].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit \n connect issue_slots[9].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique \n connect issue_slots[9].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq \n connect issue_slots[9].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq \n connect issue_slots[9].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed \n connect issue_slots[9].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size \n connect issue_slots[9].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd \n connect issue_slots[9].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause \n connect issue_slots[9].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception \n connect issue_slots[9].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst \n connect issue_slots[9].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy \n connect issue_slots[9].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy \n connect issue_slots[9].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy \n connect issue_slots[9].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy \n connect issue_slots[9].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred \n connect issue_slots[9].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 \n connect issue_slots[9].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 \n connect issue_slots[9].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 \n connect issue_slots[9].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst \n connect issue_slots[9].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx \n connect issue_slots[9].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx \n connect issue_slots[9].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx \n connect issue_slots[9].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx \n connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec \n connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags \n connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt \n connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div \n connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma \n connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint \n connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint \n connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 \n connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 \n connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 \n connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 \n connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 \n connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen \n connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst \n connect issue_slots[9].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel \n connect issue_slots[9].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel \n connect issue_slots[9].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed \n connect issue_slots[9].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm \n connect issue_slots[9].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel \n connect issue_slots[9].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename \n connect issue_slots[9].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken \n connect issue_slots[9].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob \n connect issue_slots[9].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst \n connect issue_slots[9].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx \n connect issue_slots[9].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov \n connect issue_slots[9].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc \n connect issue_slots[9].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc \n connect issue_slots[9].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret \n connect issue_slots[9].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo \n connect issue_slots[9].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence \n connect issue_slots[9].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei \n connect issue_slots[9].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence \n connect issue_slots[9].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb \n connect issue_slots[9].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type \n connect issue_slots[9].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag \n connect issue_slots[9].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask \n connect issue_slots[9].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel \n connect issue_slots[9].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint \n connect issue_slots[9].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint \n connect issue_slots[9].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint \n connect issue_slots[9].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child \n connect issue_slots[9].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child \n connect issue_slots[9].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen \n connect issue_slots[9].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen \n connect issue_slots[9].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued \n connect issue_slots[9].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] \n connect issue_slots[9].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] \n connect issue_slots[9].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] \n connect issue_slots[9].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] \n connect issue_slots[9].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] \n connect issue_slots[9].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] \n connect issue_slots[9].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] \n connect issue_slots[9].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] \n connect issue_slots[9].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] \n connect issue_slots[9].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] \n connect issue_slots[9].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] \n connect issue_slots[9].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] \n connect issue_slots[9].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] \n connect issue_slots[9].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] \n connect issue_slots[9].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc \n connect issue_slots[9].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc \n connect issue_slots[9].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst \n connect issue_slots[9].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst \n connect issue_slots[9].wakeup_ports[2].valid, io.wakeup_ports[2].valid \n connect issue_slots[9].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy \n connect issue_slots[9].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask \n connect issue_slots[9].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable \n connect issue_slots[9].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc \n connect issue_slots[9].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc \n connect issue_slots[9].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if \n connect issue_slots[9].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if \n connect issue_slots[9].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if \n connect issue_slots[9].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if \n connect issue_slots[9].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if \n connect issue_slots[9].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ \n connect issue_slots[9].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm \n connect issue_slots[9].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val \n connect issue_slots[9].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op \n connect issue_slots[9].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw \n connect issue_slots[9].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en \n connect issue_slots[9].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype \n connect issue_slots[9].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype \n connect issue_slots[9].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype \n connect issue_slots[9].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 \n connect issue_slots[9].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 \n connect issue_slots[9].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 \n connect issue_slots[9].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst \n connect issue_slots[9].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 \n connect issue_slots[9].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd \n connect issue_slots[9].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit \n connect issue_slots[9].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique \n connect issue_slots[9].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq \n connect issue_slots[9].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq \n connect issue_slots[9].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed \n connect issue_slots[9].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size \n connect issue_slots[9].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd \n connect issue_slots[9].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause \n connect issue_slots[9].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception \n connect issue_slots[9].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst \n connect issue_slots[9].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy \n connect issue_slots[9].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy \n connect issue_slots[9].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy \n connect issue_slots[9].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy \n connect issue_slots[9].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred \n connect issue_slots[9].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 \n connect issue_slots[9].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 \n connect issue_slots[9].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 \n connect issue_slots[9].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst \n connect issue_slots[9].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx \n connect issue_slots[9].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx \n connect issue_slots[9].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx \n connect issue_slots[9].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx \n connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec \n connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags \n connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt \n connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div \n connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma \n connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint \n connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint \n connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 \n connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 \n connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 \n connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 \n connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 \n connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen \n connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst \n connect issue_slots[9].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel \n connect issue_slots[9].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel \n connect issue_slots[9].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed \n connect issue_slots[9].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm \n connect issue_slots[9].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel \n connect issue_slots[9].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename \n connect issue_slots[9].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken \n connect issue_slots[9].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob \n connect issue_slots[9].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst \n connect issue_slots[9].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx \n connect issue_slots[9].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov \n connect issue_slots[9].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc \n connect issue_slots[9].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc \n connect issue_slots[9].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret \n connect issue_slots[9].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo \n connect issue_slots[9].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence \n connect issue_slots[9].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei \n connect issue_slots[9].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence \n connect issue_slots[9].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb \n connect issue_slots[9].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type \n connect issue_slots[9].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag \n connect issue_slots[9].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask \n connect issue_slots[9].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel \n connect issue_slots[9].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint \n connect issue_slots[9].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint \n connect issue_slots[9].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint \n connect issue_slots[9].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child \n connect issue_slots[9].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child \n connect issue_slots[9].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen \n connect issue_slots[9].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen \n connect issue_slots[9].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued \n connect issue_slots[9].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] \n connect issue_slots[9].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] \n connect issue_slots[9].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] \n connect issue_slots[9].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] \n connect issue_slots[9].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] \n connect issue_slots[9].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] \n connect issue_slots[9].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] \n connect issue_slots[9].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] \n connect issue_slots[9].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] \n connect issue_slots[9].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] \n connect issue_slots[9].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] \n connect issue_slots[9].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] \n connect issue_slots[9].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] \n connect issue_slots[9].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] \n connect issue_slots[9].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc \n connect issue_slots[9].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc \n connect issue_slots[9].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst \n connect issue_slots[9].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst \n connect issue_slots[9].wakeup_ports[3].valid, io.wakeup_ports[3].valid \n connect issue_slots[9].pred_wakeup_port.bits, io.pred_wakeup_port.bits \n connect issue_slots[9].pred_wakeup_port.valid, io.pred_wakeup_port.valid \n connect issue_slots[9].child_rebusys, io.child_rebusys \n connect issue_slots[9].squash_grant, io.squash_grant \n connect issue_slots[9].brupdate.b2.target_offset, io.brupdate.b2.target_offset \n connect issue_slots[9].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target \n connect issue_slots[9].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel \n connect issue_slots[9].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type \n connect issue_slots[9].brupdate.b2.taken, io.brupdate.b2.taken \n connect issue_slots[9].brupdate.b2.mispredict, io.brupdate.b2.mispredict \n connect issue_slots[9].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc \n connect issue_slots[9].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc \n connect issue_slots[9].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if \n connect issue_slots[9].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if \n connect issue_slots[9].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if \n connect issue_slots[9].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if \n connect issue_slots[9].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if \n connect issue_slots[9].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ \n connect issue_slots[9].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm \n connect issue_slots[9].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val \n connect issue_slots[9].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op \n connect issue_slots[9].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw \n connect issue_slots[9].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en \n connect issue_slots[9].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype \n connect issue_slots[9].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype \n connect issue_slots[9].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype \n connect issue_slots[9].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 \n connect issue_slots[9].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 \n connect issue_slots[9].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 \n connect issue_slots[9].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst \n connect issue_slots[9].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 \n connect issue_slots[9].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd \n connect issue_slots[9].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit \n connect issue_slots[9].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique \n connect issue_slots[9].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq \n connect issue_slots[9].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq \n connect issue_slots[9].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed \n connect issue_slots[9].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size \n connect issue_slots[9].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd \n connect issue_slots[9].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause \n connect issue_slots[9].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception \n connect issue_slots[9].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst \n connect issue_slots[9].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy \n connect issue_slots[9].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy \n connect issue_slots[9].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy \n connect issue_slots[9].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy \n connect issue_slots[9].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred \n connect issue_slots[9].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 \n connect issue_slots[9].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 \n connect issue_slots[9].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 \n connect issue_slots[9].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst \n connect issue_slots[9].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx \n connect issue_slots[9].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx \n connect issue_slots[9].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx \n connect issue_slots[9].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx \n connect issue_slots[9].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec \n connect issue_slots[9].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags \n connect issue_slots[9].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt \n connect issue_slots[9].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div \n connect issue_slots[9].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma \n connect issue_slots[9].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe \n connect issue_slots[9].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint \n connect issue_slots[9].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint \n connect issue_slots[9].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut \n connect issue_slots[9].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn \n connect issue_slots[9].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 \n connect issue_slots[9].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 \n connect issue_slots[9].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 \n connect issue_slots[9].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 \n connect issue_slots[9].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 \n connect issue_slots[9].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen \n connect issue_slots[9].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst \n connect issue_slots[9].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel \n connect issue_slots[9].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel \n connect issue_slots[9].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed \n connect issue_slots[9].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm \n connect issue_slots[9].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel \n connect issue_slots[9].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename \n connect issue_slots[9].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken \n connect issue_slots[9].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob \n connect issue_slots[9].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst \n connect issue_slots[9].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx \n connect issue_slots[9].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov \n connect issue_slots[9].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc \n connect issue_slots[9].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc \n connect issue_slots[9].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret \n connect issue_slots[9].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo \n connect issue_slots[9].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence \n connect issue_slots[9].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei \n connect issue_slots[9].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence \n connect issue_slots[9].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb \n connect issue_slots[9].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type \n connect issue_slots[9].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag \n connect issue_slots[9].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask \n connect issue_slots[9].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel \n connect issue_slots[9].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint \n connect issue_slots[9].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint \n connect issue_slots[9].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint \n connect issue_slots[9].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child \n connect issue_slots[9].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child \n connect issue_slots[9].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen \n connect issue_slots[9].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen \n connect issue_slots[9].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued \n connect issue_slots[9].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] \n connect issue_slots[9].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] \n connect issue_slots[9].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] \n connect issue_slots[9].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] \n connect issue_slots[9].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] \n connect issue_slots[9].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] \n connect issue_slots[9].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] \n connect issue_slots[9].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] \n connect issue_slots[9].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] \n connect issue_slots[9].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] \n connect issue_slots[9].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] \n connect issue_slots[9].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] \n connect issue_slots[9].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] \n connect issue_slots[9].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] \n connect issue_slots[9].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc \n connect issue_slots[9].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc \n connect issue_slots[9].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst \n connect issue_slots[9].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst \n connect issue_slots[9].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask \n connect issue_slots[9].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask \n connect issue_slots[9].kill, io.flush_pipeline \n connect issue_slots[10].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy \n connect issue_slots[10].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask \n connect issue_slots[10].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable \n connect issue_slots[10].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc \n connect issue_slots[10].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc \n connect issue_slots[10].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if \n connect issue_slots[10].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if \n connect issue_slots[10].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if \n connect issue_slots[10].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if \n connect issue_slots[10].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if \n connect issue_slots[10].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ \n connect issue_slots[10].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm \n connect issue_slots[10].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val \n connect issue_slots[10].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op \n connect issue_slots[10].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw \n connect issue_slots[10].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en \n connect issue_slots[10].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype \n connect issue_slots[10].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype \n connect issue_slots[10].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype \n connect issue_slots[10].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 \n connect issue_slots[10].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 \n connect issue_slots[10].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 \n connect issue_slots[10].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst \n connect issue_slots[10].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 \n connect issue_slots[10].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd \n connect issue_slots[10].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit \n connect issue_slots[10].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique \n connect issue_slots[10].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq \n connect issue_slots[10].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq \n connect issue_slots[10].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed \n connect issue_slots[10].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size \n connect issue_slots[10].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd \n connect issue_slots[10].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause \n connect issue_slots[10].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception \n connect issue_slots[10].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst \n connect issue_slots[10].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy \n connect issue_slots[10].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy \n connect issue_slots[10].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy \n connect issue_slots[10].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy \n connect issue_slots[10].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred \n connect issue_slots[10].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 \n connect issue_slots[10].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 \n connect issue_slots[10].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 \n connect issue_slots[10].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst \n connect issue_slots[10].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx \n connect issue_slots[10].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx \n connect issue_slots[10].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx \n connect issue_slots[10].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx \n connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec \n connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags \n connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt \n connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div \n connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma \n connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint \n connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint \n connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 \n connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 \n connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 \n connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 \n connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 \n connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen \n connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst \n connect issue_slots[10].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel \n connect issue_slots[10].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel \n connect issue_slots[10].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed \n connect issue_slots[10].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm \n connect issue_slots[10].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel \n connect issue_slots[10].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename \n connect issue_slots[10].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken \n connect issue_slots[10].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob \n connect issue_slots[10].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst \n connect issue_slots[10].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx \n connect issue_slots[10].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov \n connect issue_slots[10].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc \n connect issue_slots[10].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc \n connect issue_slots[10].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret \n connect issue_slots[10].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo \n connect issue_slots[10].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence \n connect issue_slots[10].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei \n connect issue_slots[10].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence \n connect issue_slots[10].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb \n connect issue_slots[10].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type \n connect issue_slots[10].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag \n connect issue_slots[10].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask \n connect issue_slots[10].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel \n connect issue_slots[10].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint \n connect issue_slots[10].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint \n connect issue_slots[10].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint \n connect issue_slots[10].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child \n connect issue_slots[10].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child \n connect issue_slots[10].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen \n connect issue_slots[10].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen \n connect issue_slots[10].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued \n connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] \n connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] \n connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] \n connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] \n connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] \n connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] \n connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] \n connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] \n connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] \n connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] \n connect issue_slots[10].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] \n connect issue_slots[10].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] \n connect issue_slots[10].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] \n connect issue_slots[10].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] \n connect issue_slots[10].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc \n connect issue_slots[10].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc \n connect issue_slots[10].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst \n connect issue_slots[10].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst \n connect issue_slots[10].wakeup_ports[0].valid, io.wakeup_ports[0].valid \n connect issue_slots[10].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy \n connect issue_slots[10].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask \n connect issue_slots[10].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable \n connect issue_slots[10].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc \n connect issue_slots[10].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc \n connect issue_slots[10].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if \n connect issue_slots[10].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if \n connect issue_slots[10].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if \n connect issue_slots[10].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if \n connect issue_slots[10].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if \n connect issue_slots[10].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ \n connect issue_slots[10].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm \n connect issue_slots[10].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val \n connect issue_slots[10].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op \n connect issue_slots[10].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw \n connect issue_slots[10].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en \n connect issue_slots[10].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype \n connect issue_slots[10].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype \n connect issue_slots[10].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype \n connect issue_slots[10].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 \n connect issue_slots[10].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 \n connect issue_slots[10].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 \n connect issue_slots[10].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst \n connect issue_slots[10].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 \n connect issue_slots[10].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd \n connect issue_slots[10].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit \n connect issue_slots[10].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique \n connect issue_slots[10].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq \n connect issue_slots[10].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq \n connect issue_slots[10].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed \n connect issue_slots[10].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size \n connect issue_slots[10].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd \n connect issue_slots[10].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause \n connect issue_slots[10].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception \n connect issue_slots[10].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst \n connect issue_slots[10].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy \n connect issue_slots[10].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy \n connect issue_slots[10].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy \n connect issue_slots[10].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy \n connect issue_slots[10].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred \n connect issue_slots[10].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 \n connect issue_slots[10].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 \n connect issue_slots[10].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 \n connect issue_slots[10].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst \n connect issue_slots[10].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx \n connect issue_slots[10].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx \n connect issue_slots[10].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx \n connect issue_slots[10].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx \n connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec \n connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags \n connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt \n connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div \n connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma \n connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint \n connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint \n connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 \n connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 \n connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 \n connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 \n connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 \n connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen \n connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst \n connect issue_slots[10].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel \n connect issue_slots[10].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel \n connect issue_slots[10].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed \n connect issue_slots[10].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm \n connect issue_slots[10].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel \n connect issue_slots[10].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename \n connect issue_slots[10].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken \n connect issue_slots[10].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob \n connect issue_slots[10].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst \n connect issue_slots[10].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx \n connect issue_slots[10].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov \n connect issue_slots[10].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc \n connect issue_slots[10].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc \n connect issue_slots[10].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret \n connect issue_slots[10].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo \n connect issue_slots[10].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence \n connect issue_slots[10].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei \n connect issue_slots[10].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence \n connect issue_slots[10].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb \n connect issue_slots[10].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type \n connect issue_slots[10].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag \n connect issue_slots[10].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask \n connect issue_slots[10].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel \n connect issue_slots[10].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint \n connect issue_slots[10].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint \n connect issue_slots[10].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint \n connect issue_slots[10].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child \n connect issue_slots[10].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child \n connect issue_slots[10].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen \n connect issue_slots[10].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen \n connect issue_slots[10].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued \n connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] \n connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] \n connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] \n connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] \n connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] \n connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] \n connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] \n connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] \n connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] \n connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] \n connect issue_slots[10].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] \n connect issue_slots[10].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] \n connect issue_slots[10].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] \n connect issue_slots[10].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] \n connect issue_slots[10].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc \n connect issue_slots[10].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc \n connect issue_slots[10].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst \n connect issue_slots[10].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst \n connect issue_slots[10].wakeup_ports[1].valid, io.wakeup_ports[1].valid \n connect issue_slots[10].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy \n connect issue_slots[10].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask \n connect issue_slots[10].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable \n connect issue_slots[10].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc \n connect issue_slots[10].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc \n connect issue_slots[10].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if \n connect issue_slots[10].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if \n connect issue_slots[10].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if \n connect issue_slots[10].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if \n connect issue_slots[10].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if \n connect issue_slots[10].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ \n connect issue_slots[10].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm \n connect issue_slots[10].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val \n connect issue_slots[10].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op \n connect issue_slots[10].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw \n connect issue_slots[10].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en \n connect issue_slots[10].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype \n connect issue_slots[10].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype \n connect issue_slots[10].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype \n connect issue_slots[10].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 \n connect issue_slots[10].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 \n connect issue_slots[10].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 \n connect issue_slots[10].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst \n connect issue_slots[10].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 \n connect issue_slots[10].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd \n connect issue_slots[10].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit \n connect issue_slots[10].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique \n connect issue_slots[10].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq \n connect issue_slots[10].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq \n connect issue_slots[10].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed \n connect issue_slots[10].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size \n connect issue_slots[10].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd \n connect issue_slots[10].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause \n connect issue_slots[10].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception \n connect issue_slots[10].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst \n connect issue_slots[10].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy \n connect issue_slots[10].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy \n connect issue_slots[10].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy \n connect issue_slots[10].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy \n connect issue_slots[10].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred \n connect issue_slots[10].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 \n connect issue_slots[10].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 \n connect issue_slots[10].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 \n connect issue_slots[10].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst \n connect issue_slots[10].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx \n connect issue_slots[10].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx \n connect issue_slots[10].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx \n connect issue_slots[10].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx \n connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec \n connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags \n connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt \n connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div \n connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma \n connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint \n connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint \n connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 \n connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 \n connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 \n connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 \n connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 \n connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen \n connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst \n connect issue_slots[10].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel \n connect issue_slots[10].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel \n connect issue_slots[10].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed \n connect issue_slots[10].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm \n connect issue_slots[10].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel \n connect issue_slots[10].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename \n connect issue_slots[10].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken \n connect issue_slots[10].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob \n connect issue_slots[10].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst \n connect issue_slots[10].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx \n connect issue_slots[10].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov \n connect issue_slots[10].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc \n connect issue_slots[10].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc \n connect issue_slots[10].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret \n connect issue_slots[10].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo \n connect issue_slots[10].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence \n connect issue_slots[10].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei \n connect issue_slots[10].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence \n connect issue_slots[10].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb \n connect issue_slots[10].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type \n connect issue_slots[10].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag \n connect issue_slots[10].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask \n connect issue_slots[10].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel \n connect issue_slots[10].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint \n connect issue_slots[10].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint \n connect issue_slots[10].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint \n connect issue_slots[10].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child \n connect issue_slots[10].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child \n connect issue_slots[10].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen \n connect issue_slots[10].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen \n connect issue_slots[10].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued \n connect issue_slots[10].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] \n connect issue_slots[10].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] \n connect issue_slots[10].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] \n connect issue_slots[10].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] \n connect issue_slots[10].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] \n connect issue_slots[10].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] \n connect issue_slots[10].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] \n connect issue_slots[10].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] \n connect issue_slots[10].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] \n connect issue_slots[10].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] \n connect issue_slots[10].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] \n connect issue_slots[10].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] \n connect issue_slots[10].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] \n connect issue_slots[10].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] \n connect issue_slots[10].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc \n connect issue_slots[10].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc \n connect issue_slots[10].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst \n connect issue_slots[10].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst \n connect issue_slots[10].wakeup_ports[2].valid, io.wakeup_ports[2].valid \n connect issue_slots[10].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy \n connect issue_slots[10].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask \n connect issue_slots[10].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable \n connect issue_slots[10].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc \n connect issue_slots[10].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc \n connect issue_slots[10].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if \n connect issue_slots[10].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if \n connect issue_slots[10].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if \n connect issue_slots[10].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if \n connect issue_slots[10].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if \n connect issue_slots[10].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ \n connect issue_slots[10].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm \n connect issue_slots[10].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val \n connect issue_slots[10].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op \n connect issue_slots[10].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw \n connect issue_slots[10].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en \n connect issue_slots[10].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype \n connect issue_slots[10].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype \n connect issue_slots[10].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype \n connect issue_slots[10].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 \n connect issue_slots[10].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 \n connect issue_slots[10].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 \n connect issue_slots[10].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst \n connect issue_slots[10].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 \n connect issue_slots[10].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd \n connect issue_slots[10].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit \n connect issue_slots[10].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique \n connect issue_slots[10].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq \n connect issue_slots[10].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq \n connect issue_slots[10].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed \n connect issue_slots[10].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size \n connect issue_slots[10].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd \n connect issue_slots[10].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause \n connect issue_slots[10].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception \n connect issue_slots[10].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst \n connect issue_slots[10].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy \n connect issue_slots[10].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy \n connect issue_slots[10].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy \n connect issue_slots[10].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy \n connect issue_slots[10].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred \n connect issue_slots[10].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 \n connect issue_slots[10].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 \n connect issue_slots[10].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 \n connect issue_slots[10].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst \n connect issue_slots[10].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx \n connect issue_slots[10].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx \n connect issue_slots[10].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx \n connect issue_slots[10].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx \n connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec \n connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags \n connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt \n connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div \n connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma \n connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint \n connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint \n connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 \n connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 \n connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 \n connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 \n connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 \n connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen \n connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst \n connect issue_slots[10].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel \n connect issue_slots[10].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel \n connect issue_slots[10].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed \n connect issue_slots[10].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm \n connect issue_slots[10].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel \n connect issue_slots[10].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename \n connect issue_slots[10].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken \n connect issue_slots[10].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob \n connect issue_slots[10].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst \n connect issue_slots[10].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx \n connect issue_slots[10].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov \n connect issue_slots[10].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc \n connect issue_slots[10].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc \n connect issue_slots[10].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret \n connect issue_slots[10].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo \n connect issue_slots[10].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence \n connect issue_slots[10].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei \n connect issue_slots[10].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence \n connect issue_slots[10].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb \n connect issue_slots[10].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type \n connect issue_slots[10].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag \n connect issue_slots[10].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask \n connect issue_slots[10].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel \n connect issue_slots[10].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint \n connect issue_slots[10].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint \n connect issue_slots[10].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint \n connect issue_slots[10].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child \n connect issue_slots[10].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child \n connect issue_slots[10].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen \n connect issue_slots[10].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen \n connect issue_slots[10].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued \n connect issue_slots[10].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] \n connect issue_slots[10].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] \n connect issue_slots[10].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] \n connect issue_slots[10].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] \n connect issue_slots[10].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] \n connect issue_slots[10].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] \n connect issue_slots[10].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] \n connect issue_slots[10].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] \n connect issue_slots[10].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] \n connect issue_slots[10].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] \n connect issue_slots[10].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] \n connect issue_slots[10].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] \n connect issue_slots[10].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] \n connect issue_slots[10].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] \n connect issue_slots[10].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc \n connect issue_slots[10].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc \n connect issue_slots[10].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst \n connect issue_slots[10].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst \n connect issue_slots[10].wakeup_ports[3].valid, io.wakeup_ports[3].valid \n connect issue_slots[10].pred_wakeup_port.bits, io.pred_wakeup_port.bits \n connect issue_slots[10].pred_wakeup_port.valid, io.pred_wakeup_port.valid \n connect issue_slots[10].child_rebusys, io.child_rebusys \n connect issue_slots[10].squash_grant, io.squash_grant \n connect issue_slots[10].brupdate.b2.target_offset, io.brupdate.b2.target_offset \n connect issue_slots[10].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target \n connect issue_slots[10].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel \n connect issue_slots[10].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type \n connect issue_slots[10].brupdate.b2.taken, io.brupdate.b2.taken \n connect issue_slots[10].brupdate.b2.mispredict, io.brupdate.b2.mispredict \n connect issue_slots[10].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc \n connect issue_slots[10].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc \n connect issue_slots[10].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if \n connect issue_slots[10].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if \n connect issue_slots[10].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if \n connect issue_slots[10].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if \n connect issue_slots[10].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if \n connect issue_slots[10].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ \n connect issue_slots[10].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm \n connect issue_slots[10].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val \n connect issue_slots[10].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op \n connect issue_slots[10].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw \n connect issue_slots[10].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en \n connect issue_slots[10].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype \n connect issue_slots[10].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype \n connect issue_slots[10].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype \n connect issue_slots[10].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 \n connect issue_slots[10].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 \n connect issue_slots[10].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 \n connect issue_slots[10].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst \n connect issue_slots[10].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 \n connect issue_slots[10].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd \n connect issue_slots[10].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit \n connect issue_slots[10].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique \n connect issue_slots[10].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq \n connect issue_slots[10].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq \n connect issue_slots[10].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed \n connect issue_slots[10].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size \n connect issue_slots[10].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd \n connect issue_slots[10].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause \n connect issue_slots[10].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception \n connect issue_slots[10].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst \n connect issue_slots[10].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy \n connect issue_slots[10].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy \n connect issue_slots[10].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy \n connect issue_slots[10].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy \n connect issue_slots[10].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred \n connect issue_slots[10].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 \n connect issue_slots[10].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 \n connect issue_slots[10].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 \n connect issue_slots[10].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst \n connect issue_slots[10].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx \n connect issue_slots[10].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx \n connect issue_slots[10].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx \n connect issue_slots[10].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx \n connect issue_slots[10].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec \n connect issue_slots[10].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags \n connect issue_slots[10].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt \n connect issue_slots[10].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div \n connect issue_slots[10].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma \n connect issue_slots[10].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe \n connect issue_slots[10].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint \n connect issue_slots[10].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint \n connect issue_slots[10].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut \n connect issue_slots[10].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn \n connect issue_slots[10].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 \n connect issue_slots[10].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 \n connect issue_slots[10].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 \n connect issue_slots[10].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 \n connect issue_slots[10].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 \n connect issue_slots[10].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen \n connect issue_slots[10].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst \n connect issue_slots[10].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel \n connect issue_slots[10].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel \n connect issue_slots[10].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed \n connect issue_slots[10].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm \n connect issue_slots[10].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel \n connect issue_slots[10].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename \n connect issue_slots[10].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken \n connect issue_slots[10].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob \n connect issue_slots[10].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst \n connect issue_slots[10].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx \n connect issue_slots[10].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov \n connect issue_slots[10].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc \n connect issue_slots[10].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc \n connect issue_slots[10].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret \n connect issue_slots[10].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo \n connect issue_slots[10].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence \n connect issue_slots[10].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei \n connect issue_slots[10].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence \n connect issue_slots[10].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb \n connect issue_slots[10].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type \n connect issue_slots[10].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag \n connect issue_slots[10].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask \n connect issue_slots[10].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel \n connect issue_slots[10].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint \n connect issue_slots[10].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint \n connect issue_slots[10].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint \n connect issue_slots[10].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child \n connect issue_slots[10].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child \n connect issue_slots[10].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen \n connect issue_slots[10].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen \n connect issue_slots[10].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued \n connect issue_slots[10].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] \n connect issue_slots[10].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] \n connect issue_slots[10].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] \n connect issue_slots[10].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] \n connect issue_slots[10].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] \n connect issue_slots[10].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] \n connect issue_slots[10].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] \n connect issue_slots[10].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] \n connect issue_slots[10].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] \n connect issue_slots[10].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] \n connect issue_slots[10].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] \n connect issue_slots[10].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] \n connect issue_slots[10].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] \n connect issue_slots[10].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] \n connect issue_slots[10].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc \n connect issue_slots[10].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc \n connect issue_slots[10].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst \n connect issue_slots[10].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst \n connect issue_slots[10].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask \n connect issue_slots[10].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask \n connect issue_slots[10].kill, io.flush_pipeline \n connect issue_slots[11].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy \n connect issue_slots[11].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask \n connect issue_slots[11].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable \n connect issue_slots[11].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc \n connect issue_slots[11].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc \n connect issue_slots[11].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if \n connect issue_slots[11].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if \n connect issue_slots[11].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if \n connect issue_slots[11].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if \n connect issue_slots[11].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if \n connect issue_slots[11].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ \n connect issue_slots[11].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm \n connect issue_slots[11].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val \n connect issue_slots[11].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op \n connect issue_slots[11].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw \n connect issue_slots[11].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en \n connect issue_slots[11].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype \n connect issue_slots[11].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype \n connect issue_slots[11].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype \n connect issue_slots[11].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 \n connect issue_slots[11].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 \n connect issue_slots[11].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 \n connect issue_slots[11].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst \n connect issue_slots[11].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 \n connect issue_slots[11].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd \n connect issue_slots[11].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit \n connect issue_slots[11].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique \n connect issue_slots[11].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq \n connect issue_slots[11].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq \n connect issue_slots[11].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed \n connect issue_slots[11].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size \n connect issue_slots[11].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd \n connect issue_slots[11].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause \n connect issue_slots[11].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception \n connect issue_slots[11].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst \n connect issue_slots[11].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy \n connect issue_slots[11].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy \n connect issue_slots[11].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy \n connect issue_slots[11].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy \n connect issue_slots[11].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred \n connect issue_slots[11].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 \n connect issue_slots[11].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 \n connect issue_slots[11].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 \n connect issue_slots[11].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst \n connect issue_slots[11].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx \n connect issue_slots[11].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx \n connect issue_slots[11].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx \n connect issue_slots[11].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx \n connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec \n connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags \n connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt \n connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div \n connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma \n connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint \n connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint \n connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 \n connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 \n connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 \n connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 \n connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 \n connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen \n connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst \n connect issue_slots[11].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel \n connect issue_slots[11].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel \n connect issue_slots[11].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed \n connect issue_slots[11].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm \n connect issue_slots[11].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel \n connect issue_slots[11].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename \n connect issue_slots[11].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken \n connect issue_slots[11].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob \n connect issue_slots[11].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst \n connect issue_slots[11].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx \n connect issue_slots[11].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov \n connect issue_slots[11].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc \n connect issue_slots[11].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc \n connect issue_slots[11].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret \n connect issue_slots[11].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo \n connect issue_slots[11].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence \n connect issue_slots[11].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei \n connect issue_slots[11].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence \n connect issue_slots[11].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb \n connect issue_slots[11].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type \n connect issue_slots[11].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag \n connect issue_slots[11].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask \n connect issue_slots[11].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel \n connect issue_slots[11].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint \n connect issue_slots[11].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint \n connect issue_slots[11].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint \n connect issue_slots[11].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child \n connect issue_slots[11].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child \n connect issue_slots[11].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen \n connect issue_slots[11].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen \n connect issue_slots[11].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued \n connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] \n connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] \n connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] \n connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] \n connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] \n connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] \n connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] \n connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] \n connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] \n connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] \n connect issue_slots[11].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] \n connect issue_slots[11].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] \n connect issue_slots[11].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] \n connect issue_slots[11].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] \n connect issue_slots[11].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc \n connect issue_slots[11].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc \n connect issue_slots[11].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst \n connect issue_slots[11].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst \n connect issue_slots[11].wakeup_ports[0].valid, io.wakeup_ports[0].valid \n connect issue_slots[11].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy \n connect issue_slots[11].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask \n connect issue_slots[11].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable \n connect issue_slots[11].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc \n connect issue_slots[11].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc \n connect issue_slots[11].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if \n connect issue_slots[11].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if \n connect issue_slots[11].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if \n connect issue_slots[11].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if \n connect issue_slots[11].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if \n connect issue_slots[11].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ \n connect issue_slots[11].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm \n connect issue_slots[11].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val \n connect issue_slots[11].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op \n connect issue_slots[11].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw \n connect issue_slots[11].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en \n connect issue_slots[11].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype \n connect issue_slots[11].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype \n connect issue_slots[11].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype \n connect issue_slots[11].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 \n connect issue_slots[11].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 \n connect issue_slots[11].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 \n connect issue_slots[11].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst \n connect issue_slots[11].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 \n connect issue_slots[11].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd \n connect issue_slots[11].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit \n connect issue_slots[11].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique \n connect issue_slots[11].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq \n connect issue_slots[11].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq \n connect issue_slots[11].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed \n connect issue_slots[11].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size \n connect issue_slots[11].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd \n connect issue_slots[11].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause \n connect issue_slots[11].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception \n connect issue_slots[11].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst \n connect issue_slots[11].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy \n connect issue_slots[11].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy \n connect issue_slots[11].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy \n connect issue_slots[11].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy \n connect issue_slots[11].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred \n connect issue_slots[11].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 \n connect issue_slots[11].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 \n connect issue_slots[11].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 \n connect issue_slots[11].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst \n connect issue_slots[11].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx \n connect issue_slots[11].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx \n connect issue_slots[11].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx \n connect issue_slots[11].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx \n connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec \n connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags \n connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt \n connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div \n connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma \n connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint \n connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint \n connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 \n connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 \n connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 \n connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 \n connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 \n connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen \n connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst \n connect issue_slots[11].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel \n connect issue_slots[11].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel \n connect issue_slots[11].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed \n connect issue_slots[11].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm \n connect issue_slots[11].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel \n connect issue_slots[11].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename \n connect issue_slots[11].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken \n connect issue_slots[11].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob \n connect issue_slots[11].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst \n connect issue_slots[11].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx \n connect issue_slots[11].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov \n connect issue_slots[11].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc \n connect issue_slots[11].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc \n connect issue_slots[11].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret \n connect issue_slots[11].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo \n connect issue_slots[11].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence \n connect issue_slots[11].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei \n connect issue_slots[11].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence \n connect issue_slots[11].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb \n connect issue_slots[11].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type \n connect issue_slots[11].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag \n connect issue_slots[11].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask \n connect issue_slots[11].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel \n connect issue_slots[11].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint \n connect issue_slots[11].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint \n connect issue_slots[11].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint \n connect issue_slots[11].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child \n connect issue_slots[11].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child \n connect issue_slots[11].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen \n connect issue_slots[11].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen \n connect issue_slots[11].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued \n connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] \n connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] \n connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] \n connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] \n connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] \n connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] \n connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] \n connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] \n connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] \n connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] \n connect issue_slots[11].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] \n connect issue_slots[11].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] \n connect issue_slots[11].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] \n connect issue_slots[11].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] \n connect issue_slots[11].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc \n connect issue_slots[11].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc \n connect issue_slots[11].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst \n connect issue_slots[11].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst \n connect issue_slots[11].wakeup_ports[1].valid, io.wakeup_ports[1].valid \n connect issue_slots[11].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy \n connect issue_slots[11].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask \n connect issue_slots[11].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable \n connect issue_slots[11].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc \n connect issue_slots[11].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc \n connect issue_slots[11].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if \n connect issue_slots[11].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if \n connect issue_slots[11].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if \n connect issue_slots[11].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if \n connect issue_slots[11].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if \n connect issue_slots[11].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ \n connect issue_slots[11].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm \n connect issue_slots[11].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val \n connect issue_slots[11].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op \n connect issue_slots[11].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw \n connect issue_slots[11].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en \n connect issue_slots[11].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype \n connect issue_slots[11].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype \n connect issue_slots[11].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype \n connect issue_slots[11].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 \n connect issue_slots[11].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 \n connect issue_slots[11].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 \n connect issue_slots[11].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst \n connect issue_slots[11].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 \n connect issue_slots[11].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd \n connect issue_slots[11].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit \n connect issue_slots[11].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique \n connect issue_slots[11].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq \n connect issue_slots[11].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq \n connect issue_slots[11].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed \n connect issue_slots[11].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size \n connect issue_slots[11].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd \n connect issue_slots[11].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause \n connect issue_slots[11].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception \n connect issue_slots[11].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst \n connect issue_slots[11].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy \n connect issue_slots[11].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy \n connect issue_slots[11].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy \n connect issue_slots[11].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy \n connect issue_slots[11].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred \n connect issue_slots[11].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 \n connect issue_slots[11].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 \n connect issue_slots[11].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 \n connect issue_slots[11].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst \n connect issue_slots[11].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx \n connect issue_slots[11].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx \n connect issue_slots[11].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx \n connect issue_slots[11].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx \n connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec \n connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags \n connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt \n connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div \n connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma \n connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint \n connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint \n connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 \n connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 \n connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 \n connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 \n connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 \n connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen \n connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst \n connect issue_slots[11].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel \n connect issue_slots[11].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel \n connect issue_slots[11].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed \n connect issue_slots[11].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm \n connect issue_slots[11].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel \n connect issue_slots[11].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename \n connect issue_slots[11].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken \n connect issue_slots[11].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob \n connect issue_slots[11].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst \n connect issue_slots[11].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx \n connect issue_slots[11].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov \n connect issue_slots[11].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc \n connect issue_slots[11].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc \n connect issue_slots[11].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret \n connect issue_slots[11].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo \n connect issue_slots[11].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence \n connect issue_slots[11].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei \n connect issue_slots[11].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence \n connect issue_slots[11].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb \n connect issue_slots[11].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type \n connect issue_slots[11].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag \n connect issue_slots[11].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask \n connect issue_slots[11].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel \n connect issue_slots[11].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint \n connect issue_slots[11].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint \n connect issue_slots[11].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint \n connect issue_slots[11].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child \n connect issue_slots[11].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child \n connect issue_slots[11].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen \n connect issue_slots[11].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen \n connect issue_slots[11].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued \n connect issue_slots[11].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] \n connect issue_slots[11].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] \n connect issue_slots[11].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] \n connect issue_slots[11].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] \n connect issue_slots[11].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] \n connect issue_slots[11].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] \n connect issue_slots[11].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] \n connect issue_slots[11].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] \n connect issue_slots[11].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] \n connect issue_slots[11].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] \n connect issue_slots[11].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] \n connect issue_slots[11].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] \n connect issue_slots[11].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] \n connect issue_slots[11].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] \n connect issue_slots[11].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc \n connect issue_slots[11].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc \n connect issue_slots[11].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst \n connect issue_slots[11].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst \n connect issue_slots[11].wakeup_ports[2].valid, io.wakeup_ports[2].valid \n connect issue_slots[11].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy \n connect issue_slots[11].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask \n connect issue_slots[11].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable \n connect issue_slots[11].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc \n connect issue_slots[11].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc \n connect issue_slots[11].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if \n connect issue_slots[11].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if \n connect issue_slots[11].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if \n connect issue_slots[11].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if \n connect issue_slots[11].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if \n connect issue_slots[11].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ \n connect issue_slots[11].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm \n connect issue_slots[11].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val \n connect issue_slots[11].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op \n connect issue_slots[11].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw \n connect issue_slots[11].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en \n connect issue_slots[11].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype \n connect issue_slots[11].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype \n connect issue_slots[11].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype \n connect issue_slots[11].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 \n connect issue_slots[11].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 \n connect issue_slots[11].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 \n connect issue_slots[11].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst \n connect issue_slots[11].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 \n connect issue_slots[11].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd \n connect issue_slots[11].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit \n connect issue_slots[11].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique \n connect issue_slots[11].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq \n connect issue_slots[11].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq \n connect issue_slots[11].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed \n connect issue_slots[11].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size \n connect issue_slots[11].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd \n connect issue_slots[11].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause \n connect issue_slots[11].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception \n connect issue_slots[11].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst \n connect issue_slots[11].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy \n connect issue_slots[11].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy \n connect issue_slots[11].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy \n connect issue_slots[11].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy \n connect issue_slots[11].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred \n connect issue_slots[11].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 \n connect issue_slots[11].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 \n connect issue_slots[11].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 \n connect issue_slots[11].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst \n connect issue_slots[11].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx \n connect issue_slots[11].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx \n connect issue_slots[11].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx \n connect issue_slots[11].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx \n connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec \n connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags \n connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt \n connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div \n connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma \n connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint \n connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint \n connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 \n connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 \n connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 \n connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 \n connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 \n connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen \n connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst \n connect issue_slots[11].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel \n connect issue_slots[11].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel \n connect issue_slots[11].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed \n connect issue_slots[11].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm \n connect issue_slots[11].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel \n connect issue_slots[11].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename \n connect issue_slots[11].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken \n connect issue_slots[11].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob \n connect issue_slots[11].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst \n connect issue_slots[11].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx \n connect issue_slots[11].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov \n connect issue_slots[11].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc \n connect issue_slots[11].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc \n connect issue_slots[11].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret \n connect issue_slots[11].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo \n connect issue_slots[11].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence \n connect issue_slots[11].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei \n connect issue_slots[11].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence \n connect issue_slots[11].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb \n connect issue_slots[11].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type \n connect issue_slots[11].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag \n connect issue_slots[11].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask \n connect issue_slots[11].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel \n connect issue_slots[11].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint \n connect issue_slots[11].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint \n connect issue_slots[11].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint \n connect issue_slots[11].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child \n connect issue_slots[11].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child \n connect issue_slots[11].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen \n connect issue_slots[11].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen \n connect issue_slots[11].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued \n connect issue_slots[11].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] \n connect issue_slots[11].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] \n connect issue_slots[11].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] \n connect issue_slots[11].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] \n connect issue_slots[11].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] \n connect issue_slots[11].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] \n connect issue_slots[11].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] \n connect issue_slots[11].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] \n connect issue_slots[11].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] \n connect issue_slots[11].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] \n connect issue_slots[11].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] \n connect issue_slots[11].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] \n connect issue_slots[11].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] \n connect issue_slots[11].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] \n connect issue_slots[11].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc \n connect issue_slots[11].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc \n connect issue_slots[11].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst \n connect issue_slots[11].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst \n connect issue_slots[11].wakeup_ports[3].valid, io.wakeup_ports[3].valid \n connect issue_slots[11].pred_wakeup_port.bits, io.pred_wakeup_port.bits \n connect issue_slots[11].pred_wakeup_port.valid, io.pred_wakeup_port.valid \n connect issue_slots[11].child_rebusys, io.child_rebusys \n connect issue_slots[11].squash_grant, io.squash_grant \n connect issue_slots[11].brupdate.b2.target_offset, io.brupdate.b2.target_offset \n connect issue_slots[11].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target \n connect issue_slots[11].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel \n connect issue_slots[11].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type \n connect issue_slots[11].brupdate.b2.taken, io.brupdate.b2.taken \n connect issue_slots[11].brupdate.b2.mispredict, io.brupdate.b2.mispredict \n connect issue_slots[11].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc \n connect issue_slots[11].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc \n connect issue_slots[11].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if \n connect issue_slots[11].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if \n connect issue_slots[11].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if \n connect issue_slots[11].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if \n connect issue_slots[11].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if \n connect issue_slots[11].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ \n connect issue_slots[11].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm \n connect issue_slots[11].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val \n connect issue_slots[11].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op \n connect issue_slots[11].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw \n connect issue_slots[11].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en \n connect issue_slots[11].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype \n connect issue_slots[11].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype \n connect issue_slots[11].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype \n connect issue_slots[11].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 \n connect issue_slots[11].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 \n connect issue_slots[11].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 \n connect issue_slots[11].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst \n connect issue_slots[11].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 \n connect issue_slots[11].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd \n connect issue_slots[11].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit \n connect issue_slots[11].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique \n connect issue_slots[11].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq \n connect issue_slots[11].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq \n connect issue_slots[11].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed \n connect issue_slots[11].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size \n connect issue_slots[11].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd \n connect issue_slots[11].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause \n connect issue_slots[11].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception \n connect issue_slots[11].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst \n connect issue_slots[11].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy \n connect issue_slots[11].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy \n connect issue_slots[11].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy \n connect issue_slots[11].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy \n connect issue_slots[11].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred \n connect issue_slots[11].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 \n connect issue_slots[11].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 \n connect issue_slots[11].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 \n connect issue_slots[11].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst \n connect issue_slots[11].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx \n connect issue_slots[11].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx \n connect issue_slots[11].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx \n connect issue_slots[11].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx \n connect issue_slots[11].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec \n connect issue_slots[11].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags \n connect issue_slots[11].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt \n connect issue_slots[11].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div \n connect issue_slots[11].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma \n connect issue_slots[11].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe \n connect issue_slots[11].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint \n connect issue_slots[11].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint \n connect issue_slots[11].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut \n connect issue_slots[11].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn \n connect issue_slots[11].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 \n connect issue_slots[11].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 \n connect issue_slots[11].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 \n connect issue_slots[11].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 \n connect issue_slots[11].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 \n connect issue_slots[11].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen \n connect issue_slots[11].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst \n connect issue_slots[11].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel \n connect issue_slots[11].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel \n connect issue_slots[11].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed \n connect issue_slots[11].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm \n connect issue_slots[11].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel \n connect issue_slots[11].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename \n connect issue_slots[11].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken \n connect issue_slots[11].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob \n connect issue_slots[11].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst \n connect issue_slots[11].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx \n connect issue_slots[11].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov \n connect issue_slots[11].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc \n connect issue_slots[11].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc \n connect issue_slots[11].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret \n connect issue_slots[11].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo \n connect issue_slots[11].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence \n connect issue_slots[11].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei \n connect issue_slots[11].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence \n connect issue_slots[11].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb \n connect issue_slots[11].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type \n connect issue_slots[11].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag \n connect issue_slots[11].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask \n connect issue_slots[11].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel \n connect issue_slots[11].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint \n connect issue_slots[11].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint \n connect issue_slots[11].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint \n connect issue_slots[11].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child \n connect issue_slots[11].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child \n connect issue_slots[11].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen \n connect issue_slots[11].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen \n connect issue_slots[11].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued \n connect issue_slots[11].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] \n connect issue_slots[11].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] \n connect issue_slots[11].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] \n connect issue_slots[11].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] \n connect issue_slots[11].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] \n connect issue_slots[11].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] \n connect issue_slots[11].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] \n connect issue_slots[11].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] \n connect issue_slots[11].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] \n connect issue_slots[11].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] \n connect issue_slots[11].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] \n connect issue_slots[11].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] \n connect issue_slots[11].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] \n connect issue_slots[11].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] \n connect issue_slots[11].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc \n connect issue_slots[11].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc \n connect issue_slots[11].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst \n connect issue_slots[11].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst \n connect issue_slots[11].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask \n connect issue_slots[11].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask \n connect issue_slots[11].kill, io.flush_pipeline \n connect issue_slots[12].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy \n connect issue_slots[12].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask \n connect issue_slots[12].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable \n connect issue_slots[12].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc \n connect issue_slots[12].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc \n connect issue_slots[12].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if \n connect issue_slots[12].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if \n connect issue_slots[12].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if \n connect issue_slots[12].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if \n connect issue_slots[12].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if \n connect issue_slots[12].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ \n connect issue_slots[12].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm \n connect issue_slots[12].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val \n connect issue_slots[12].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op \n connect issue_slots[12].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw \n connect issue_slots[12].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en \n connect issue_slots[12].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype \n connect issue_slots[12].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype \n connect issue_slots[12].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype \n connect issue_slots[12].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 \n connect issue_slots[12].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 \n connect issue_slots[12].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 \n connect issue_slots[12].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst \n connect issue_slots[12].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 \n connect issue_slots[12].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd \n connect issue_slots[12].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit \n connect issue_slots[12].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique \n connect issue_slots[12].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq \n connect issue_slots[12].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq \n connect issue_slots[12].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed \n connect issue_slots[12].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size \n connect issue_slots[12].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd \n connect issue_slots[12].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause \n connect issue_slots[12].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception \n connect issue_slots[12].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst \n connect issue_slots[12].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy \n connect issue_slots[12].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy \n connect issue_slots[12].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy \n connect issue_slots[12].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy \n connect issue_slots[12].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred \n connect issue_slots[12].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 \n connect issue_slots[12].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 \n connect issue_slots[12].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 \n connect issue_slots[12].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst \n connect issue_slots[12].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx \n connect issue_slots[12].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx \n connect issue_slots[12].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx \n connect issue_slots[12].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx \n connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec \n connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags \n connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt \n connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div \n connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma \n connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint \n connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint \n connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 \n connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 \n connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 \n connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 \n connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 \n connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen \n connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst \n connect issue_slots[12].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel \n connect issue_slots[12].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel \n connect issue_slots[12].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed \n connect issue_slots[12].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm \n connect issue_slots[12].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel \n connect issue_slots[12].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename \n connect issue_slots[12].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken \n connect issue_slots[12].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob \n connect issue_slots[12].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst \n connect issue_slots[12].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx \n connect issue_slots[12].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov \n connect issue_slots[12].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc \n connect issue_slots[12].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc \n connect issue_slots[12].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret \n connect issue_slots[12].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo \n connect issue_slots[12].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence \n connect issue_slots[12].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei \n connect issue_slots[12].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence \n connect issue_slots[12].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb \n connect issue_slots[12].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type \n connect issue_slots[12].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag \n connect issue_slots[12].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask \n connect issue_slots[12].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel \n connect issue_slots[12].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint \n connect issue_slots[12].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint \n connect issue_slots[12].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint \n connect issue_slots[12].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child \n connect issue_slots[12].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child \n connect issue_slots[12].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen \n connect issue_slots[12].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen \n connect issue_slots[12].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued \n connect issue_slots[12].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] \n connect issue_slots[12].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] \n connect issue_slots[12].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] \n connect issue_slots[12].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] \n connect issue_slots[12].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] \n connect issue_slots[12].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] \n connect issue_slots[12].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] \n connect issue_slots[12].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] \n connect issue_slots[12].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] \n connect issue_slots[12].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] \n connect issue_slots[12].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] \n connect issue_slots[12].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] \n connect issue_slots[12].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] \n connect issue_slots[12].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] \n connect issue_slots[12].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc \n connect issue_slots[12].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc \n connect issue_slots[12].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst \n connect issue_slots[12].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst \n connect issue_slots[12].wakeup_ports[0].valid, io.wakeup_ports[0].valid \n connect issue_slots[12].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy \n connect issue_slots[12].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask \n connect issue_slots[12].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable \n connect issue_slots[12].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc \n connect issue_slots[12].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc \n connect issue_slots[12].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if \n connect issue_slots[12].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if \n connect issue_slots[12].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if \n connect issue_slots[12].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if \n connect issue_slots[12].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if \n connect issue_slots[12].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ \n connect issue_slots[12].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm \n connect issue_slots[12].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val \n connect issue_slots[12].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op \n connect issue_slots[12].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw \n connect issue_slots[12].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en \n connect issue_slots[12].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype \n connect issue_slots[12].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype \n connect issue_slots[12].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype \n connect issue_slots[12].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 \n connect issue_slots[12].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 \n connect issue_slots[12].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 \n connect issue_slots[12].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst \n connect issue_slots[12].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 \n connect issue_slots[12].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd \n connect issue_slots[12].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit \n connect issue_slots[12].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique \n connect issue_slots[12].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq \n connect issue_slots[12].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq \n connect issue_slots[12].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed \n connect issue_slots[12].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size \n connect issue_slots[12].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd \n connect issue_slots[12].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause \n connect issue_slots[12].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception \n connect issue_slots[12].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst \n connect issue_slots[12].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy \n connect issue_slots[12].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy \n connect issue_slots[12].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy \n connect issue_slots[12].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy \n connect issue_slots[12].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred \n connect issue_slots[12].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 \n connect issue_slots[12].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 \n connect issue_slots[12].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 \n connect issue_slots[12].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst \n connect issue_slots[12].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx \n connect issue_slots[12].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx \n connect issue_slots[12].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx \n connect issue_slots[12].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx \n connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec \n connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags \n connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt \n connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div \n connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma \n connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint \n connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint \n connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 \n connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 \n connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 \n connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 \n connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 \n connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen \n connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst \n connect issue_slots[12].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel \n connect issue_slots[12].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel \n connect issue_slots[12].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed \n connect issue_slots[12].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm \n connect issue_slots[12].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel \n connect issue_slots[12].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename \n connect issue_slots[12].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken \n connect issue_slots[12].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob \n connect issue_slots[12].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst \n connect issue_slots[12].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx \n connect issue_slots[12].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov \n connect issue_slots[12].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc \n connect issue_slots[12].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc \n connect issue_slots[12].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret \n connect issue_slots[12].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo \n connect issue_slots[12].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence \n connect issue_slots[12].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei \n connect issue_slots[12].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence \n connect issue_slots[12].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb \n connect issue_slots[12].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type \n connect issue_slots[12].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag \n connect issue_slots[12].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask \n connect issue_slots[12].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel \n connect issue_slots[12].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint \n connect issue_slots[12].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint \n connect issue_slots[12].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint \n connect issue_slots[12].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child \n connect issue_slots[12].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child \n connect issue_slots[12].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen \n connect issue_slots[12].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen \n connect issue_slots[12].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued \n connect issue_slots[12].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] \n connect issue_slots[12].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] \n connect issue_slots[12].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] \n connect issue_slots[12].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] \n connect issue_slots[12].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] \n connect issue_slots[12].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] \n connect issue_slots[12].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] \n connect issue_slots[12].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] \n connect issue_slots[12].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] \n connect issue_slots[12].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] \n connect issue_slots[12].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] \n connect issue_slots[12].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] \n connect issue_slots[12].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] \n connect issue_slots[12].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] \n connect issue_slots[12].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc \n connect issue_slots[12].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc \n connect issue_slots[12].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst \n connect issue_slots[12].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst \n connect issue_slots[12].wakeup_ports[1].valid, io.wakeup_ports[1].valid \n connect issue_slots[12].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy \n connect issue_slots[12].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask \n connect issue_slots[12].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable \n connect issue_slots[12].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc \n connect issue_slots[12].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc \n connect issue_slots[12].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if \n connect issue_slots[12].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if \n connect issue_slots[12].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if \n connect issue_slots[12].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if \n connect issue_slots[12].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if \n connect issue_slots[12].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ \n connect issue_slots[12].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm \n connect issue_slots[12].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val \n connect issue_slots[12].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op \n connect issue_slots[12].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw \n connect issue_slots[12].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en \n connect issue_slots[12].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype \n connect issue_slots[12].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype \n connect issue_slots[12].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype \n connect issue_slots[12].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 \n connect issue_slots[12].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 \n connect issue_slots[12].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 \n connect issue_slots[12].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst \n connect issue_slots[12].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 \n connect issue_slots[12].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd \n connect issue_slots[12].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit \n connect issue_slots[12].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique \n connect issue_slots[12].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq \n connect issue_slots[12].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq \n connect issue_slots[12].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed \n connect issue_slots[12].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size \n connect issue_slots[12].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd \n connect issue_slots[12].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause \n connect issue_slots[12].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception \n connect issue_slots[12].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst \n connect issue_slots[12].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy \n connect issue_slots[12].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy \n connect issue_slots[12].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy \n connect issue_slots[12].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy \n connect issue_slots[12].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred \n connect issue_slots[12].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 \n connect issue_slots[12].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 \n connect issue_slots[12].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 \n connect issue_slots[12].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst \n connect issue_slots[12].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx \n connect issue_slots[12].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx \n connect issue_slots[12].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx \n connect issue_slots[12].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx \n connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec \n connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags \n connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt \n connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div \n connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma \n connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint \n connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint \n connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 \n connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 \n connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 \n connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 \n connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 \n connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen \n connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst \n connect issue_slots[12].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel \n connect issue_slots[12].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel \n connect issue_slots[12].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed \n connect issue_slots[12].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm \n connect issue_slots[12].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel \n connect issue_slots[12].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename \n connect issue_slots[12].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken \n connect issue_slots[12].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob \n connect issue_slots[12].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst \n connect issue_slots[12].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx \n connect issue_slots[12].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov \n connect issue_slots[12].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc \n connect issue_slots[12].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc \n connect issue_slots[12].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret \n connect issue_slots[12].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo \n connect issue_slots[12].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence \n connect issue_slots[12].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei \n connect issue_slots[12].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence \n connect issue_slots[12].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb \n connect issue_slots[12].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type \n connect issue_slots[12].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag \n connect issue_slots[12].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask \n connect issue_slots[12].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel \n connect issue_slots[12].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint \n connect issue_slots[12].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint \n connect issue_slots[12].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint \n connect issue_slots[12].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child \n connect issue_slots[12].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child \n connect issue_slots[12].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen \n connect issue_slots[12].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen \n connect issue_slots[12].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued \n connect issue_slots[12].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] \n connect issue_slots[12].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] \n connect issue_slots[12].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] \n connect issue_slots[12].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] \n connect issue_slots[12].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] \n connect issue_slots[12].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] \n connect issue_slots[12].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] \n connect issue_slots[12].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] \n connect issue_slots[12].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] \n connect issue_slots[12].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] \n connect issue_slots[12].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] \n connect issue_slots[12].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] \n connect issue_slots[12].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] \n connect issue_slots[12].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] \n connect issue_slots[12].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc \n connect issue_slots[12].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc \n connect issue_slots[12].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst \n connect issue_slots[12].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst \n connect issue_slots[12].wakeup_ports[2].valid, io.wakeup_ports[2].valid \n connect issue_slots[12].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy \n connect issue_slots[12].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask \n connect issue_slots[12].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable \n connect issue_slots[12].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc \n connect issue_slots[12].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc \n connect issue_slots[12].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if \n connect issue_slots[12].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if \n connect issue_slots[12].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if \n connect issue_slots[12].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if \n connect issue_slots[12].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if \n connect issue_slots[12].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ \n connect issue_slots[12].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm \n connect issue_slots[12].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val \n connect issue_slots[12].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op \n connect issue_slots[12].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw \n connect issue_slots[12].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en \n connect issue_slots[12].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype \n connect issue_slots[12].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype \n connect issue_slots[12].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype \n connect issue_slots[12].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 \n connect issue_slots[12].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 \n connect issue_slots[12].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 \n connect issue_slots[12].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst \n connect issue_slots[12].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 \n connect issue_slots[12].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd \n connect issue_slots[12].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit \n connect issue_slots[12].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique \n connect issue_slots[12].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq \n connect issue_slots[12].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq \n connect issue_slots[12].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed \n connect issue_slots[12].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size \n connect issue_slots[12].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd \n connect issue_slots[12].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause \n connect issue_slots[12].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception \n connect issue_slots[12].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst \n connect issue_slots[12].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy \n connect issue_slots[12].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy \n connect issue_slots[12].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy \n connect issue_slots[12].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy \n connect issue_slots[12].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred \n connect issue_slots[12].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 \n connect issue_slots[12].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 \n connect issue_slots[12].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 \n connect issue_slots[12].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst \n connect issue_slots[12].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx \n connect issue_slots[12].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx \n connect issue_slots[12].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx \n connect issue_slots[12].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx \n connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec \n connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags \n connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt \n connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div \n connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma \n connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint \n connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint \n connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 \n connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 \n connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 \n connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 \n connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 \n connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen \n connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst \n connect issue_slots[12].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel \n connect issue_slots[12].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel \n connect issue_slots[12].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed \n connect issue_slots[12].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm \n connect issue_slots[12].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel \n connect issue_slots[12].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename \n connect issue_slots[12].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken \n connect issue_slots[12].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob \n connect issue_slots[12].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst \n connect issue_slots[12].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx \n connect issue_slots[12].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov \n connect issue_slots[12].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc \n connect issue_slots[12].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc \n connect issue_slots[12].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret \n connect issue_slots[12].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo \n connect issue_slots[12].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence \n connect issue_slots[12].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei \n connect issue_slots[12].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence \n connect issue_slots[12].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb \n connect issue_slots[12].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type \n connect issue_slots[12].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag \n connect issue_slots[12].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask \n connect issue_slots[12].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel \n connect issue_slots[12].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint \n connect issue_slots[12].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint \n connect issue_slots[12].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint \n connect issue_slots[12].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child \n connect issue_slots[12].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child \n connect issue_slots[12].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen \n connect issue_slots[12].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen \n connect issue_slots[12].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued \n connect issue_slots[12].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] \n connect issue_slots[12].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] \n connect issue_slots[12].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] \n connect issue_slots[12].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] \n connect issue_slots[12].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] \n connect issue_slots[12].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] \n connect issue_slots[12].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] \n connect issue_slots[12].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] \n connect issue_slots[12].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] \n connect issue_slots[12].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] \n connect issue_slots[12].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] \n connect issue_slots[12].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] \n connect issue_slots[12].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] \n connect issue_slots[12].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] \n connect issue_slots[12].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc \n connect issue_slots[12].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc \n connect issue_slots[12].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst \n connect issue_slots[12].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst \n connect issue_slots[12].wakeup_ports[3].valid, io.wakeup_ports[3].valid \n connect issue_slots[12].pred_wakeup_port.bits, io.pred_wakeup_port.bits \n connect issue_slots[12].pred_wakeup_port.valid, io.pred_wakeup_port.valid \n connect issue_slots[12].child_rebusys, io.child_rebusys \n connect issue_slots[12].squash_grant, io.squash_grant \n connect issue_slots[12].brupdate.b2.target_offset, io.brupdate.b2.target_offset \n connect issue_slots[12].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target \n connect issue_slots[12].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel \n connect issue_slots[12].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type \n connect issue_slots[12].brupdate.b2.taken, io.brupdate.b2.taken \n connect issue_slots[12].brupdate.b2.mispredict, io.brupdate.b2.mispredict \n connect issue_slots[12].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc \n connect issue_slots[12].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc \n connect issue_slots[12].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if \n connect issue_slots[12].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if \n connect issue_slots[12].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if \n connect issue_slots[12].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if \n connect issue_slots[12].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if \n connect issue_slots[12].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ \n connect issue_slots[12].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm \n connect issue_slots[12].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val \n connect issue_slots[12].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op \n connect issue_slots[12].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw \n connect issue_slots[12].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en \n connect issue_slots[12].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype \n connect issue_slots[12].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype \n connect issue_slots[12].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype \n connect issue_slots[12].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 \n connect issue_slots[12].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 \n connect issue_slots[12].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 \n connect issue_slots[12].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst \n connect issue_slots[12].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 \n connect issue_slots[12].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd \n connect issue_slots[12].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit \n connect issue_slots[12].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique \n connect issue_slots[12].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq \n connect issue_slots[12].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq \n connect issue_slots[12].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed \n connect issue_slots[12].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size \n connect issue_slots[12].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd \n connect issue_slots[12].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause \n connect issue_slots[12].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception \n connect issue_slots[12].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst \n connect issue_slots[12].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy \n connect issue_slots[12].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy \n connect issue_slots[12].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy \n connect issue_slots[12].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy \n connect issue_slots[12].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred \n connect issue_slots[12].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 \n connect issue_slots[12].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 \n connect issue_slots[12].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 \n connect issue_slots[12].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst \n connect issue_slots[12].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx \n connect issue_slots[12].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx \n connect issue_slots[12].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx \n connect issue_slots[12].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx \n connect issue_slots[12].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec \n connect issue_slots[12].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags \n connect issue_slots[12].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt \n connect issue_slots[12].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div \n connect issue_slots[12].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma \n connect issue_slots[12].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe \n connect issue_slots[12].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint \n connect issue_slots[12].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint \n connect issue_slots[12].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut \n connect issue_slots[12].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn \n connect issue_slots[12].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 \n connect issue_slots[12].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 \n connect issue_slots[12].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 \n connect issue_slots[12].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 \n connect issue_slots[12].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 \n connect issue_slots[12].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen \n connect issue_slots[12].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst \n connect issue_slots[12].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel \n connect issue_slots[12].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel \n connect issue_slots[12].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed \n connect issue_slots[12].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm \n connect issue_slots[12].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel \n connect issue_slots[12].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename \n connect issue_slots[12].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken \n connect issue_slots[12].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob \n connect issue_slots[12].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst \n connect issue_slots[12].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx \n connect issue_slots[12].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov \n connect issue_slots[12].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc \n connect issue_slots[12].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc \n connect issue_slots[12].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret \n connect issue_slots[12].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo \n connect issue_slots[12].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence \n connect issue_slots[12].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei \n connect issue_slots[12].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence \n connect issue_slots[12].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb \n connect issue_slots[12].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type \n connect issue_slots[12].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag \n connect issue_slots[12].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask \n connect issue_slots[12].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel \n connect issue_slots[12].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint \n connect issue_slots[12].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint \n connect issue_slots[12].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint \n connect issue_slots[12].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child \n connect issue_slots[12].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child \n connect issue_slots[12].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen \n connect issue_slots[12].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen \n connect issue_slots[12].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued \n connect issue_slots[12].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] \n connect issue_slots[12].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] \n connect issue_slots[12].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] \n connect issue_slots[12].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] \n connect issue_slots[12].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] \n connect issue_slots[12].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] \n connect issue_slots[12].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] \n connect issue_slots[12].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] \n connect issue_slots[12].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] \n connect issue_slots[12].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] \n connect issue_slots[12].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] \n connect issue_slots[12].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] \n connect issue_slots[12].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] \n connect issue_slots[12].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] \n connect issue_slots[12].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc \n connect issue_slots[12].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc \n connect issue_slots[12].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst \n connect issue_slots[12].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst \n connect issue_slots[12].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask \n connect issue_slots[12].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask \n connect issue_slots[12].kill, io.flush_pipeline \n connect issue_slots[13].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy \n connect issue_slots[13].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask \n connect issue_slots[13].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable \n connect issue_slots[13].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc \n connect issue_slots[13].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc \n connect issue_slots[13].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if \n connect issue_slots[13].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if \n connect issue_slots[13].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if \n connect issue_slots[13].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if \n connect issue_slots[13].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if \n connect issue_slots[13].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ \n connect issue_slots[13].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm \n connect issue_slots[13].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val \n connect issue_slots[13].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op \n connect issue_slots[13].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw \n connect issue_slots[13].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en \n connect issue_slots[13].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype \n connect issue_slots[13].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype \n connect issue_slots[13].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype \n connect issue_slots[13].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 \n connect issue_slots[13].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 \n connect issue_slots[13].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 \n connect issue_slots[13].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst \n connect issue_slots[13].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 \n connect issue_slots[13].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd \n connect issue_slots[13].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit \n connect issue_slots[13].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique \n connect issue_slots[13].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq \n connect issue_slots[13].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq \n connect issue_slots[13].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed \n connect issue_slots[13].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size \n connect issue_slots[13].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd \n connect issue_slots[13].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause \n connect issue_slots[13].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception \n connect issue_slots[13].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst \n connect issue_slots[13].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy \n connect issue_slots[13].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy \n connect issue_slots[13].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy \n connect issue_slots[13].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy \n connect issue_slots[13].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred \n connect issue_slots[13].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 \n connect issue_slots[13].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 \n connect issue_slots[13].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 \n connect issue_slots[13].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst \n connect issue_slots[13].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx \n connect issue_slots[13].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx \n connect issue_slots[13].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx \n connect issue_slots[13].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx \n connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec \n connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags \n connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt \n connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div \n connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma \n connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint \n connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint \n connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 \n connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 \n connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 \n connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 \n connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 \n connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen \n connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst \n connect issue_slots[13].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel \n connect issue_slots[13].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel \n connect issue_slots[13].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed \n connect issue_slots[13].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm \n connect issue_slots[13].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel \n connect issue_slots[13].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename \n connect issue_slots[13].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken \n connect issue_slots[13].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob \n connect issue_slots[13].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst \n connect issue_slots[13].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx \n connect issue_slots[13].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov \n connect issue_slots[13].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc \n connect issue_slots[13].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc \n connect issue_slots[13].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret \n connect issue_slots[13].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo \n connect issue_slots[13].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence \n connect issue_slots[13].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei \n connect issue_slots[13].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence \n connect issue_slots[13].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb \n connect issue_slots[13].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type \n connect issue_slots[13].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag \n connect issue_slots[13].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask \n connect issue_slots[13].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel \n connect issue_slots[13].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint \n connect issue_slots[13].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint \n connect issue_slots[13].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint \n connect issue_slots[13].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child \n connect issue_slots[13].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child \n connect issue_slots[13].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen \n connect issue_slots[13].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen \n connect issue_slots[13].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued \n connect issue_slots[13].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] \n connect issue_slots[13].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] \n connect issue_slots[13].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] \n connect issue_slots[13].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] \n connect issue_slots[13].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] \n connect issue_slots[13].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] \n connect issue_slots[13].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] \n connect issue_slots[13].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] \n connect issue_slots[13].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] \n connect issue_slots[13].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] \n connect issue_slots[13].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] \n connect issue_slots[13].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] \n connect issue_slots[13].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] \n connect issue_slots[13].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] \n connect issue_slots[13].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc \n connect issue_slots[13].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc \n connect issue_slots[13].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst \n connect issue_slots[13].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst \n connect issue_slots[13].wakeup_ports[0].valid, io.wakeup_ports[0].valid \n connect issue_slots[13].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy \n connect issue_slots[13].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask \n connect issue_slots[13].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable \n connect issue_slots[13].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc \n connect issue_slots[13].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc \n connect issue_slots[13].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if \n connect issue_slots[13].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if \n connect issue_slots[13].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if \n connect issue_slots[13].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if \n connect issue_slots[13].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if \n connect issue_slots[13].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ \n connect issue_slots[13].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm \n connect issue_slots[13].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val \n connect issue_slots[13].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op \n connect issue_slots[13].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw \n connect issue_slots[13].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en \n connect issue_slots[13].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype \n connect issue_slots[13].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype \n connect issue_slots[13].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype \n connect issue_slots[13].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 \n connect issue_slots[13].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 \n connect issue_slots[13].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 \n connect issue_slots[13].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst \n connect issue_slots[13].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 \n connect issue_slots[13].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd \n connect issue_slots[13].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit \n connect issue_slots[13].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique \n connect issue_slots[13].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq \n connect issue_slots[13].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq \n connect issue_slots[13].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed \n connect issue_slots[13].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size \n connect issue_slots[13].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd \n connect issue_slots[13].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause \n connect issue_slots[13].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception \n connect issue_slots[13].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst \n connect issue_slots[13].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy \n connect issue_slots[13].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy \n connect issue_slots[13].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy \n connect issue_slots[13].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy \n connect issue_slots[13].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred \n connect issue_slots[13].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 \n connect issue_slots[13].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 \n connect issue_slots[13].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 \n connect issue_slots[13].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst \n connect issue_slots[13].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx \n connect issue_slots[13].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx \n connect issue_slots[13].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx \n connect issue_slots[13].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx \n connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec \n connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags \n connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt \n connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div \n connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma \n connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint \n connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint \n connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 \n connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 \n connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 \n connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 \n connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 \n connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen \n connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst \n connect issue_slots[13].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel \n connect issue_slots[13].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel \n connect issue_slots[13].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed \n connect issue_slots[13].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm \n connect issue_slots[13].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel \n connect issue_slots[13].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename \n connect issue_slots[13].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken \n connect issue_slots[13].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob \n connect issue_slots[13].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst \n connect issue_slots[13].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx \n connect issue_slots[13].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov \n connect issue_slots[13].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc \n connect issue_slots[13].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc \n connect issue_slots[13].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret \n connect issue_slots[13].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo \n connect issue_slots[13].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence \n connect issue_slots[13].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei \n connect issue_slots[13].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence \n connect issue_slots[13].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb \n connect issue_slots[13].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type \n connect issue_slots[13].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag \n connect issue_slots[13].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask \n connect issue_slots[13].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel \n connect issue_slots[13].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint \n connect issue_slots[13].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint \n connect issue_slots[13].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint \n connect issue_slots[13].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child \n connect issue_slots[13].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child \n connect issue_slots[13].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen \n connect issue_slots[13].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen \n connect issue_slots[13].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued \n connect issue_slots[13].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] \n connect issue_slots[13].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] \n connect issue_slots[13].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] \n connect issue_slots[13].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] \n connect issue_slots[13].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] \n connect issue_slots[13].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] \n connect issue_slots[13].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] \n connect issue_slots[13].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] \n connect issue_slots[13].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] \n connect issue_slots[13].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] \n connect issue_slots[13].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] \n connect issue_slots[13].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] \n connect issue_slots[13].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] \n connect issue_slots[13].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] \n connect issue_slots[13].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc \n connect issue_slots[13].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc \n connect issue_slots[13].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst \n connect issue_slots[13].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst \n connect issue_slots[13].wakeup_ports[1].valid, io.wakeup_ports[1].valid \n connect issue_slots[13].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy \n connect issue_slots[13].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask \n connect issue_slots[13].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable \n connect issue_slots[13].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc \n connect issue_slots[13].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc \n connect issue_slots[13].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if \n connect issue_slots[13].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if \n connect issue_slots[13].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if \n connect issue_slots[13].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if \n connect issue_slots[13].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if \n connect issue_slots[13].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ \n connect issue_slots[13].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm \n connect issue_slots[13].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val \n connect issue_slots[13].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op \n connect issue_slots[13].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw \n connect issue_slots[13].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en \n connect issue_slots[13].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype \n connect issue_slots[13].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype \n connect issue_slots[13].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype \n connect issue_slots[13].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 \n connect issue_slots[13].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 \n connect issue_slots[13].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 \n connect issue_slots[13].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst \n connect issue_slots[13].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 \n connect issue_slots[13].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd \n connect issue_slots[13].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit \n connect issue_slots[13].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique \n connect issue_slots[13].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq \n connect issue_slots[13].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq \n connect issue_slots[13].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed \n connect issue_slots[13].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size \n connect issue_slots[13].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd \n connect issue_slots[13].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause \n connect issue_slots[13].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception \n connect issue_slots[13].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst \n connect issue_slots[13].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy \n connect issue_slots[13].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy \n connect issue_slots[13].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy \n connect issue_slots[13].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy \n connect issue_slots[13].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred \n connect issue_slots[13].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 \n connect issue_slots[13].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 \n connect issue_slots[13].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 \n connect issue_slots[13].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst \n connect issue_slots[13].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx \n connect issue_slots[13].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx \n connect issue_slots[13].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx \n connect issue_slots[13].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx \n connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec \n connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags \n connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt \n connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div \n connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma \n connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint \n connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint \n connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 \n connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 \n connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 \n connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 \n connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 \n connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen \n connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst \n connect issue_slots[13].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel \n connect issue_slots[13].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel \n connect issue_slots[13].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed \n connect issue_slots[13].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm \n connect issue_slots[13].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel \n connect issue_slots[13].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename \n connect issue_slots[13].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken \n connect issue_slots[13].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob \n connect issue_slots[13].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst \n connect issue_slots[13].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx \n connect issue_slots[13].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov \n connect issue_slots[13].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc \n connect issue_slots[13].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc \n connect issue_slots[13].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret \n connect issue_slots[13].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo \n connect issue_slots[13].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence \n connect issue_slots[13].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei \n connect issue_slots[13].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence \n connect issue_slots[13].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb \n connect issue_slots[13].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type \n connect issue_slots[13].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag \n connect issue_slots[13].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask \n connect issue_slots[13].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel \n connect issue_slots[13].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint \n connect issue_slots[13].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint \n connect issue_slots[13].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint \n connect issue_slots[13].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child \n connect issue_slots[13].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child \n connect issue_slots[13].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen \n connect issue_slots[13].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen \n connect issue_slots[13].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued \n connect issue_slots[13].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] \n connect issue_slots[13].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] \n connect issue_slots[13].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] \n connect issue_slots[13].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] \n connect issue_slots[13].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] \n connect issue_slots[13].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] \n connect issue_slots[13].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] \n connect issue_slots[13].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] \n connect issue_slots[13].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] \n connect issue_slots[13].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] \n connect issue_slots[13].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] \n connect issue_slots[13].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] \n connect issue_slots[13].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] \n connect issue_slots[13].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] \n connect issue_slots[13].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc \n connect issue_slots[13].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc \n connect issue_slots[13].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst \n connect issue_slots[13].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst \n connect issue_slots[13].wakeup_ports[2].valid, io.wakeup_ports[2].valid \n connect issue_slots[13].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy \n connect issue_slots[13].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask \n connect issue_slots[13].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable \n connect issue_slots[13].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc \n connect issue_slots[13].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc \n connect issue_slots[13].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if \n connect issue_slots[13].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if \n connect issue_slots[13].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if \n connect issue_slots[13].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if \n connect issue_slots[13].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if \n connect issue_slots[13].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ \n connect issue_slots[13].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm \n connect issue_slots[13].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val \n connect issue_slots[13].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op \n connect issue_slots[13].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw \n connect issue_slots[13].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en \n connect issue_slots[13].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype \n connect issue_slots[13].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype \n connect issue_slots[13].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype \n connect issue_slots[13].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 \n connect issue_slots[13].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 \n connect issue_slots[13].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 \n connect issue_slots[13].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst \n connect issue_slots[13].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 \n connect issue_slots[13].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd \n connect issue_slots[13].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit \n connect issue_slots[13].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique \n connect issue_slots[13].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq \n connect issue_slots[13].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq \n connect issue_slots[13].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed \n connect issue_slots[13].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size \n connect issue_slots[13].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd \n connect issue_slots[13].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause \n connect issue_slots[13].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception \n connect issue_slots[13].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst \n connect issue_slots[13].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy \n connect issue_slots[13].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy \n connect issue_slots[13].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy \n connect issue_slots[13].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy \n connect issue_slots[13].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred \n connect issue_slots[13].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 \n connect issue_slots[13].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 \n connect issue_slots[13].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 \n connect issue_slots[13].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst \n connect issue_slots[13].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx \n connect issue_slots[13].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx \n connect issue_slots[13].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx \n connect issue_slots[13].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx \n connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec \n connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags \n connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt \n connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div \n connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma \n connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint \n connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint \n connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 \n connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 \n connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 \n connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 \n connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 \n connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen \n connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst \n connect issue_slots[13].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel \n connect issue_slots[13].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel \n connect issue_slots[13].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed \n connect issue_slots[13].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm \n connect issue_slots[13].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel \n connect issue_slots[13].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename \n connect issue_slots[13].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken \n connect issue_slots[13].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob \n connect issue_slots[13].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst \n connect issue_slots[13].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx \n connect issue_slots[13].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov \n connect issue_slots[13].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc \n connect issue_slots[13].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc \n connect issue_slots[13].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret \n connect issue_slots[13].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo \n connect issue_slots[13].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence \n connect issue_slots[13].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei \n connect issue_slots[13].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence \n connect issue_slots[13].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb \n connect issue_slots[13].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type \n connect issue_slots[13].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag \n connect issue_slots[13].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask \n connect issue_slots[13].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel \n connect issue_slots[13].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint \n connect issue_slots[13].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint \n connect issue_slots[13].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint \n connect issue_slots[13].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child \n connect issue_slots[13].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child \n connect issue_slots[13].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen \n connect issue_slots[13].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen \n connect issue_slots[13].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued \n connect issue_slots[13].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] \n connect issue_slots[13].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] \n connect issue_slots[13].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] \n connect issue_slots[13].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] \n connect issue_slots[13].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] \n connect issue_slots[13].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] \n connect issue_slots[13].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] \n connect issue_slots[13].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] \n connect issue_slots[13].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] \n connect issue_slots[13].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] \n connect issue_slots[13].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] \n connect issue_slots[13].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] \n connect issue_slots[13].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] \n connect issue_slots[13].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] \n connect issue_slots[13].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc \n connect issue_slots[13].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc \n connect issue_slots[13].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst \n connect issue_slots[13].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst \n connect issue_slots[13].wakeup_ports[3].valid, io.wakeup_ports[3].valid \n connect issue_slots[13].pred_wakeup_port.bits, io.pred_wakeup_port.bits \n connect issue_slots[13].pred_wakeup_port.valid, io.pred_wakeup_port.valid \n connect issue_slots[13].child_rebusys, io.child_rebusys \n connect issue_slots[13].squash_grant, io.squash_grant \n connect issue_slots[13].brupdate.b2.target_offset, io.brupdate.b2.target_offset \n connect issue_slots[13].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target \n connect issue_slots[13].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel \n connect issue_slots[13].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type \n connect issue_slots[13].brupdate.b2.taken, io.brupdate.b2.taken \n connect issue_slots[13].brupdate.b2.mispredict, io.brupdate.b2.mispredict \n connect issue_slots[13].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc \n connect issue_slots[13].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc \n connect issue_slots[13].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if \n connect issue_slots[13].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if \n connect issue_slots[13].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if \n connect issue_slots[13].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if \n connect issue_slots[13].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if \n connect issue_slots[13].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ \n connect issue_slots[13].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm \n connect issue_slots[13].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val \n connect issue_slots[13].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op \n connect issue_slots[13].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw \n connect issue_slots[13].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en \n connect issue_slots[13].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype \n connect issue_slots[13].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype \n connect issue_slots[13].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype \n connect issue_slots[13].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 \n connect issue_slots[13].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 \n connect issue_slots[13].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 \n connect issue_slots[13].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst \n connect issue_slots[13].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 \n connect issue_slots[13].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd \n connect issue_slots[13].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit \n connect issue_slots[13].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique \n connect issue_slots[13].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq \n connect issue_slots[13].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq \n connect issue_slots[13].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed \n connect issue_slots[13].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size \n connect issue_slots[13].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd \n connect issue_slots[13].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause \n connect issue_slots[13].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception \n connect issue_slots[13].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst \n connect issue_slots[13].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy \n connect issue_slots[13].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy \n connect issue_slots[13].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy \n connect issue_slots[13].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy \n connect issue_slots[13].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred \n connect issue_slots[13].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 \n connect issue_slots[13].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 \n connect issue_slots[13].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 \n connect issue_slots[13].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst \n connect issue_slots[13].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx \n connect issue_slots[13].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx \n connect issue_slots[13].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx \n connect issue_slots[13].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx \n connect issue_slots[13].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec \n connect issue_slots[13].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags \n connect issue_slots[13].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt \n connect issue_slots[13].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div \n connect issue_slots[13].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma \n connect issue_slots[13].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe \n connect issue_slots[13].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint \n connect issue_slots[13].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint \n connect issue_slots[13].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut \n connect issue_slots[13].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn \n connect issue_slots[13].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 \n connect issue_slots[13].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 \n connect issue_slots[13].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 \n connect issue_slots[13].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 \n connect issue_slots[13].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 \n connect issue_slots[13].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen \n connect issue_slots[13].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst \n connect issue_slots[13].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel \n connect issue_slots[13].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel \n connect issue_slots[13].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed \n connect issue_slots[13].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm \n connect issue_slots[13].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel \n connect issue_slots[13].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename \n connect issue_slots[13].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken \n connect issue_slots[13].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob \n connect issue_slots[13].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst \n connect issue_slots[13].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx \n connect issue_slots[13].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov \n connect issue_slots[13].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc \n connect issue_slots[13].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc \n connect issue_slots[13].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret \n connect issue_slots[13].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo \n connect issue_slots[13].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence \n connect issue_slots[13].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei \n connect issue_slots[13].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence \n connect issue_slots[13].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb \n connect issue_slots[13].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type \n connect issue_slots[13].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag \n connect issue_slots[13].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask \n connect issue_slots[13].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel \n connect issue_slots[13].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint \n connect issue_slots[13].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint \n connect issue_slots[13].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint \n connect issue_slots[13].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child \n connect issue_slots[13].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child \n connect issue_slots[13].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen \n connect issue_slots[13].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen \n connect issue_slots[13].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued \n connect issue_slots[13].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] \n connect issue_slots[13].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] \n connect issue_slots[13].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] \n connect issue_slots[13].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] \n connect issue_slots[13].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] \n connect issue_slots[13].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] \n connect issue_slots[13].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] \n connect issue_slots[13].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] \n connect issue_slots[13].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] \n connect issue_slots[13].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] \n connect issue_slots[13].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] \n connect issue_slots[13].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] \n connect issue_slots[13].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] \n connect issue_slots[13].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] \n connect issue_slots[13].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc \n connect issue_slots[13].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc \n connect issue_slots[13].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst \n connect issue_slots[13].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst \n connect issue_slots[13].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask \n connect issue_slots[13].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask \n connect issue_slots[13].kill, io.flush_pipeline \n connect issue_slots[14].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy \n connect issue_slots[14].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask \n connect issue_slots[14].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable \n connect issue_slots[14].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc \n connect issue_slots[14].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc \n connect issue_slots[14].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if \n connect issue_slots[14].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if \n connect issue_slots[14].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if \n connect issue_slots[14].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if \n connect issue_slots[14].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if \n connect issue_slots[14].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ \n connect issue_slots[14].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm \n connect issue_slots[14].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val \n connect issue_slots[14].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op \n connect issue_slots[14].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw \n connect issue_slots[14].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en \n connect issue_slots[14].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype \n connect issue_slots[14].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype \n connect issue_slots[14].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype \n connect issue_slots[14].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 \n connect issue_slots[14].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 \n connect issue_slots[14].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 \n connect issue_slots[14].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst \n connect issue_slots[14].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 \n connect issue_slots[14].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd \n connect issue_slots[14].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit \n connect issue_slots[14].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique \n connect issue_slots[14].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq \n connect issue_slots[14].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq \n connect issue_slots[14].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed \n connect issue_slots[14].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size \n connect issue_slots[14].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd \n connect issue_slots[14].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause \n connect issue_slots[14].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception \n connect issue_slots[14].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst \n connect issue_slots[14].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy \n connect issue_slots[14].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy \n connect issue_slots[14].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy \n connect issue_slots[14].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy \n connect issue_slots[14].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred \n connect issue_slots[14].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 \n connect issue_slots[14].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 \n connect issue_slots[14].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 \n connect issue_slots[14].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst \n connect issue_slots[14].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx \n connect issue_slots[14].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx \n connect issue_slots[14].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx \n connect issue_slots[14].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx \n connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec \n connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags \n connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt \n connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div \n connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma \n connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint \n connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint \n connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 \n connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 \n connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 \n connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 \n connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 \n connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen \n connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst \n connect issue_slots[14].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel \n connect issue_slots[14].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel \n connect issue_slots[14].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed \n connect issue_slots[14].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm \n connect issue_slots[14].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel \n connect issue_slots[14].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename \n connect issue_slots[14].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken \n connect issue_slots[14].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob \n connect issue_slots[14].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst \n connect issue_slots[14].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx \n connect issue_slots[14].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov \n connect issue_slots[14].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc \n connect issue_slots[14].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc \n connect issue_slots[14].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret \n connect issue_slots[14].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo \n connect issue_slots[14].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence \n connect issue_slots[14].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei \n connect issue_slots[14].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence \n connect issue_slots[14].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb \n connect issue_slots[14].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type \n connect issue_slots[14].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag \n connect issue_slots[14].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask \n connect issue_slots[14].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel \n connect issue_slots[14].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint \n connect issue_slots[14].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint \n connect issue_slots[14].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint \n connect issue_slots[14].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child \n connect issue_slots[14].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child \n connect issue_slots[14].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen \n connect issue_slots[14].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen \n connect issue_slots[14].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued \n connect issue_slots[14].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] \n connect issue_slots[14].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] \n connect issue_slots[14].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] \n connect issue_slots[14].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] \n connect issue_slots[14].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] \n connect issue_slots[14].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] \n connect issue_slots[14].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] \n connect issue_slots[14].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] \n connect issue_slots[14].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] \n connect issue_slots[14].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] \n connect issue_slots[14].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] \n connect issue_slots[14].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] \n connect issue_slots[14].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] \n connect issue_slots[14].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] \n connect issue_slots[14].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc \n connect issue_slots[14].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc \n connect issue_slots[14].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst \n connect issue_slots[14].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst \n connect issue_slots[14].wakeup_ports[0].valid, io.wakeup_ports[0].valid \n connect issue_slots[14].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy \n connect issue_slots[14].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask \n connect issue_slots[14].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable \n connect issue_slots[14].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc \n connect issue_slots[14].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc \n connect issue_slots[14].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if \n connect issue_slots[14].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if \n connect issue_slots[14].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if \n connect issue_slots[14].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if \n connect issue_slots[14].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if \n connect issue_slots[14].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ \n connect issue_slots[14].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm \n connect issue_slots[14].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val \n connect issue_slots[14].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op \n connect issue_slots[14].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw \n connect issue_slots[14].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en \n connect issue_slots[14].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype \n connect issue_slots[14].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype \n connect issue_slots[14].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype \n connect issue_slots[14].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 \n connect issue_slots[14].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 \n connect issue_slots[14].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 \n connect issue_slots[14].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst \n connect issue_slots[14].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 \n connect issue_slots[14].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd \n connect issue_slots[14].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit \n connect issue_slots[14].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique \n connect issue_slots[14].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq \n connect issue_slots[14].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq \n connect issue_slots[14].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed \n connect issue_slots[14].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size \n connect issue_slots[14].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd \n connect issue_slots[14].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause \n connect issue_slots[14].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception \n connect issue_slots[14].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst \n connect issue_slots[14].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy \n connect issue_slots[14].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy \n connect issue_slots[14].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy \n connect issue_slots[14].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy \n connect issue_slots[14].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred \n connect issue_slots[14].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 \n connect issue_slots[14].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 \n connect issue_slots[14].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 \n connect issue_slots[14].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst \n connect issue_slots[14].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx \n connect issue_slots[14].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx \n connect issue_slots[14].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx \n connect issue_slots[14].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx \n connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec \n connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags \n connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt \n connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div \n connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma \n connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint \n connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint \n connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 \n connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 \n connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 \n connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 \n connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 \n connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen \n connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst \n connect issue_slots[14].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel \n connect issue_slots[14].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel \n connect issue_slots[14].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed \n connect issue_slots[14].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm \n connect issue_slots[14].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel \n connect issue_slots[14].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename \n connect issue_slots[14].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken \n connect issue_slots[14].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob \n connect issue_slots[14].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst \n connect issue_slots[14].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx \n connect issue_slots[14].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov \n connect issue_slots[14].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc \n connect issue_slots[14].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc \n connect issue_slots[14].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret \n connect issue_slots[14].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo \n connect issue_slots[14].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence \n connect issue_slots[14].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei \n connect issue_slots[14].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence \n connect issue_slots[14].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb \n connect issue_slots[14].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type \n connect issue_slots[14].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag \n connect issue_slots[14].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask \n connect issue_slots[14].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel \n connect issue_slots[14].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint \n connect issue_slots[14].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint \n connect issue_slots[14].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint \n connect issue_slots[14].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child \n connect issue_slots[14].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child \n connect issue_slots[14].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen \n connect issue_slots[14].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen \n connect issue_slots[14].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued \n connect issue_slots[14].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] \n connect issue_slots[14].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] \n connect issue_slots[14].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] \n connect issue_slots[14].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] \n connect issue_slots[14].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] \n connect issue_slots[14].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] \n connect issue_slots[14].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] \n connect issue_slots[14].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] \n connect issue_slots[14].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] \n connect issue_slots[14].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] \n connect issue_slots[14].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] \n connect issue_slots[14].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] \n connect issue_slots[14].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] \n connect issue_slots[14].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] \n connect issue_slots[14].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc \n connect issue_slots[14].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc \n connect issue_slots[14].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst \n connect issue_slots[14].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst \n connect issue_slots[14].wakeup_ports[1].valid, io.wakeup_ports[1].valid \n connect issue_slots[14].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy \n connect issue_slots[14].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask \n connect issue_slots[14].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable \n connect issue_slots[14].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc \n connect issue_slots[14].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc \n connect issue_slots[14].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if \n connect issue_slots[14].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if \n connect issue_slots[14].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if \n connect issue_slots[14].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if \n connect issue_slots[14].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if \n connect issue_slots[14].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ \n connect issue_slots[14].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm \n connect issue_slots[14].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val \n connect issue_slots[14].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op \n connect issue_slots[14].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw \n connect issue_slots[14].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en \n connect issue_slots[14].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype \n connect issue_slots[14].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype \n connect issue_slots[14].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype \n connect issue_slots[14].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 \n connect issue_slots[14].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 \n connect issue_slots[14].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 \n connect issue_slots[14].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst \n connect issue_slots[14].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 \n connect issue_slots[14].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd \n connect issue_slots[14].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit \n connect issue_slots[14].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique \n connect issue_slots[14].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq \n connect issue_slots[14].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq \n connect issue_slots[14].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed \n connect issue_slots[14].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size \n connect issue_slots[14].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd \n connect issue_slots[14].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause \n connect issue_slots[14].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception \n connect issue_slots[14].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst \n connect issue_slots[14].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy \n connect issue_slots[14].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy \n connect issue_slots[14].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy \n connect issue_slots[14].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy \n connect issue_slots[14].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred \n connect issue_slots[14].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 \n connect issue_slots[14].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 \n connect issue_slots[14].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 \n connect issue_slots[14].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst \n connect issue_slots[14].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx \n connect issue_slots[14].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx \n connect issue_slots[14].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx \n connect issue_slots[14].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx \n connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec \n connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags \n connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt \n connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div \n connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma \n connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint \n connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint \n connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 \n connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 \n connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 \n connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 \n connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 \n connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen \n connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst \n connect issue_slots[14].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel \n connect issue_slots[14].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel \n connect issue_slots[14].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed \n connect issue_slots[14].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm \n connect issue_slots[14].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel \n connect issue_slots[14].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename \n connect issue_slots[14].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken \n connect issue_slots[14].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob \n connect issue_slots[14].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst \n connect issue_slots[14].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx \n connect issue_slots[14].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov \n connect issue_slots[14].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc \n connect issue_slots[14].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc \n connect issue_slots[14].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret \n connect issue_slots[14].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo \n connect issue_slots[14].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence \n connect issue_slots[14].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei \n connect issue_slots[14].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence \n connect issue_slots[14].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb \n connect issue_slots[14].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type \n connect issue_slots[14].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag \n connect issue_slots[14].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask \n connect issue_slots[14].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel \n connect issue_slots[14].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint \n connect issue_slots[14].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint \n connect issue_slots[14].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint \n connect issue_slots[14].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child \n connect issue_slots[14].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child \n connect issue_slots[14].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen \n connect issue_slots[14].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen \n connect issue_slots[14].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued \n connect issue_slots[14].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] \n connect issue_slots[14].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] \n connect issue_slots[14].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] \n connect issue_slots[14].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] \n connect issue_slots[14].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] \n connect issue_slots[14].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] \n connect issue_slots[14].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] \n connect issue_slots[14].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] \n connect issue_slots[14].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] \n connect issue_slots[14].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] \n connect issue_slots[14].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] \n connect issue_slots[14].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] \n connect issue_slots[14].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] \n connect issue_slots[14].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] \n connect issue_slots[14].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc \n connect issue_slots[14].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc \n connect issue_slots[14].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst \n connect issue_slots[14].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst \n connect issue_slots[14].wakeup_ports[2].valid, io.wakeup_ports[2].valid \n connect issue_slots[14].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy \n connect issue_slots[14].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask \n connect issue_slots[14].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable \n connect issue_slots[14].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc \n connect issue_slots[14].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc \n connect issue_slots[14].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if \n connect issue_slots[14].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if \n connect issue_slots[14].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if \n connect issue_slots[14].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if \n connect issue_slots[14].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if \n connect issue_slots[14].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ \n connect issue_slots[14].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm \n connect issue_slots[14].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val \n connect issue_slots[14].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op \n connect issue_slots[14].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw \n connect issue_slots[14].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en \n connect issue_slots[14].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype \n connect issue_slots[14].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype \n connect issue_slots[14].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype \n connect issue_slots[14].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 \n connect issue_slots[14].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 \n connect issue_slots[14].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 \n connect issue_slots[14].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst \n connect issue_slots[14].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 \n connect issue_slots[14].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd \n connect issue_slots[14].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit \n connect issue_slots[14].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique \n connect issue_slots[14].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq \n connect issue_slots[14].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq \n connect issue_slots[14].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed \n connect issue_slots[14].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size \n connect issue_slots[14].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd \n connect issue_slots[14].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause \n connect issue_slots[14].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception \n connect issue_slots[14].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst \n connect issue_slots[14].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy \n connect issue_slots[14].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy \n connect issue_slots[14].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy \n connect issue_slots[14].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy \n connect issue_slots[14].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred \n connect issue_slots[14].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 \n connect issue_slots[14].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 \n connect issue_slots[14].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 \n connect issue_slots[14].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst \n connect issue_slots[14].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx \n connect issue_slots[14].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx \n connect issue_slots[14].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx \n connect issue_slots[14].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx \n connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec \n connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags \n connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt \n connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div \n connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma \n connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint \n connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint \n connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 \n connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 \n connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 \n connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 \n connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 \n connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen \n connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst \n connect issue_slots[14].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel \n connect issue_slots[14].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel \n connect issue_slots[14].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed \n connect issue_slots[14].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm \n connect issue_slots[14].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel \n connect issue_slots[14].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename \n connect issue_slots[14].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken \n connect issue_slots[14].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob \n connect issue_slots[14].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst \n connect issue_slots[14].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx \n connect issue_slots[14].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov \n connect issue_slots[14].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc \n connect issue_slots[14].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc \n connect issue_slots[14].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret \n connect issue_slots[14].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo \n connect issue_slots[14].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence \n connect issue_slots[14].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei \n connect issue_slots[14].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence \n connect issue_slots[14].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb \n connect issue_slots[14].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type \n connect issue_slots[14].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag \n connect issue_slots[14].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask \n connect issue_slots[14].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel \n connect issue_slots[14].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint \n connect issue_slots[14].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint \n connect issue_slots[14].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint \n connect issue_slots[14].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child \n connect issue_slots[14].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child \n connect issue_slots[14].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen \n connect issue_slots[14].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen \n connect issue_slots[14].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued \n connect issue_slots[14].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] \n connect issue_slots[14].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] \n connect issue_slots[14].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] \n connect issue_slots[14].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] \n connect issue_slots[14].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] \n connect issue_slots[14].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] \n connect issue_slots[14].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] \n connect issue_slots[14].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] \n connect issue_slots[14].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] \n connect issue_slots[14].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] \n connect issue_slots[14].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] \n connect issue_slots[14].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] \n connect issue_slots[14].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] \n connect issue_slots[14].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] \n connect issue_slots[14].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc \n connect issue_slots[14].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc \n connect issue_slots[14].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst \n connect issue_slots[14].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst \n connect issue_slots[14].wakeup_ports[3].valid, io.wakeup_ports[3].valid \n connect issue_slots[14].pred_wakeup_port.bits, io.pred_wakeup_port.bits \n connect issue_slots[14].pred_wakeup_port.valid, io.pred_wakeup_port.valid \n connect issue_slots[14].child_rebusys, io.child_rebusys \n connect issue_slots[14].squash_grant, io.squash_grant \n connect issue_slots[14].brupdate.b2.target_offset, io.brupdate.b2.target_offset \n connect issue_slots[14].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target \n connect issue_slots[14].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel \n connect issue_slots[14].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type \n connect issue_slots[14].brupdate.b2.taken, io.brupdate.b2.taken \n connect issue_slots[14].brupdate.b2.mispredict, io.brupdate.b2.mispredict \n connect issue_slots[14].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc \n connect issue_slots[14].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc \n connect issue_slots[14].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if \n connect issue_slots[14].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if \n connect issue_slots[14].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if \n connect issue_slots[14].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if \n connect issue_slots[14].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if \n connect issue_slots[14].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ \n connect issue_slots[14].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm \n connect issue_slots[14].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val \n connect issue_slots[14].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op \n connect issue_slots[14].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw \n connect issue_slots[14].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en \n connect issue_slots[14].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype \n connect issue_slots[14].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype \n connect issue_slots[14].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype \n connect issue_slots[14].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 \n connect issue_slots[14].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 \n connect issue_slots[14].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 \n connect issue_slots[14].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst \n connect issue_slots[14].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 \n connect issue_slots[14].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd \n connect issue_slots[14].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit \n connect issue_slots[14].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique \n connect issue_slots[14].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq \n connect issue_slots[14].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq \n connect issue_slots[14].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed \n connect issue_slots[14].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size \n connect issue_slots[14].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd \n connect issue_slots[14].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause \n connect issue_slots[14].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception \n connect issue_slots[14].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst \n connect issue_slots[14].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy \n connect issue_slots[14].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy \n connect issue_slots[14].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy \n connect issue_slots[14].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy \n connect issue_slots[14].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred \n connect issue_slots[14].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 \n connect issue_slots[14].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 \n connect issue_slots[14].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 \n connect issue_slots[14].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst \n connect issue_slots[14].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx \n connect issue_slots[14].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx \n connect issue_slots[14].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx \n connect issue_slots[14].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx \n connect issue_slots[14].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec \n connect issue_slots[14].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags \n connect issue_slots[14].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt \n connect issue_slots[14].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div \n connect issue_slots[14].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma \n connect issue_slots[14].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe \n connect issue_slots[14].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint \n connect issue_slots[14].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint \n connect issue_slots[14].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut \n connect issue_slots[14].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn \n connect issue_slots[14].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 \n connect issue_slots[14].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 \n connect issue_slots[14].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 \n connect issue_slots[14].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 \n connect issue_slots[14].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 \n connect issue_slots[14].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen \n connect issue_slots[14].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst \n connect issue_slots[14].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel \n connect issue_slots[14].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel \n connect issue_slots[14].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed \n connect issue_slots[14].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm \n connect issue_slots[14].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel \n connect issue_slots[14].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename \n connect issue_slots[14].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken \n connect issue_slots[14].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob \n connect issue_slots[14].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst \n connect issue_slots[14].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx \n connect issue_slots[14].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov \n connect issue_slots[14].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc \n connect issue_slots[14].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc \n connect issue_slots[14].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret \n connect issue_slots[14].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo \n connect issue_slots[14].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence \n connect issue_slots[14].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei \n connect issue_slots[14].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence \n connect issue_slots[14].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb \n connect issue_slots[14].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type \n connect issue_slots[14].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag \n connect issue_slots[14].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask \n connect issue_slots[14].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel \n connect issue_slots[14].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint \n connect issue_slots[14].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint \n connect issue_slots[14].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint \n connect issue_slots[14].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child \n connect issue_slots[14].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child \n connect issue_slots[14].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen \n connect issue_slots[14].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen \n connect issue_slots[14].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued \n connect issue_slots[14].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] \n connect issue_slots[14].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] \n connect issue_slots[14].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] \n connect issue_slots[14].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] \n connect issue_slots[14].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] \n connect issue_slots[14].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] \n connect issue_slots[14].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] \n connect issue_slots[14].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] \n connect issue_slots[14].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] \n connect issue_slots[14].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] \n connect issue_slots[14].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] \n connect issue_slots[14].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] \n connect issue_slots[14].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] \n connect issue_slots[14].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] \n connect issue_slots[14].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc \n connect issue_slots[14].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc \n connect issue_slots[14].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst \n connect issue_slots[14].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst \n connect issue_slots[14].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask \n connect issue_slots[14].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask \n connect issue_slots[14].kill, io.flush_pipeline \n connect issue_slots[15].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy \n connect issue_slots[15].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask \n connect issue_slots[15].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable \n connect issue_slots[15].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc \n connect issue_slots[15].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc \n connect issue_slots[15].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if \n connect issue_slots[15].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if \n connect issue_slots[15].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if \n connect issue_slots[15].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if \n connect issue_slots[15].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if \n connect issue_slots[15].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ \n connect issue_slots[15].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm \n connect issue_slots[15].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val \n connect issue_slots[15].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op \n connect issue_slots[15].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw \n connect issue_slots[15].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en \n connect issue_slots[15].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype \n connect issue_slots[15].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype \n connect issue_slots[15].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype \n connect issue_slots[15].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 \n connect issue_slots[15].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 \n connect issue_slots[15].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 \n connect issue_slots[15].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst \n connect issue_slots[15].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 \n connect issue_slots[15].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd \n connect issue_slots[15].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit \n connect issue_slots[15].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique \n connect issue_slots[15].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq \n connect issue_slots[15].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq \n connect issue_slots[15].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed \n connect issue_slots[15].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size \n connect issue_slots[15].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd \n connect issue_slots[15].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause \n connect issue_slots[15].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception \n connect issue_slots[15].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst \n connect issue_slots[15].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy \n connect issue_slots[15].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy \n connect issue_slots[15].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy \n connect issue_slots[15].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy \n connect issue_slots[15].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred \n connect issue_slots[15].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 \n connect issue_slots[15].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 \n connect issue_slots[15].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 \n connect issue_slots[15].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst \n connect issue_slots[15].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx \n connect issue_slots[15].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx \n connect issue_slots[15].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx \n connect issue_slots[15].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx \n connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec \n connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags \n connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt \n connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div \n connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma \n connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint \n connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint \n connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 \n connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 \n connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 \n connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 \n connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 \n connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen \n connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst \n connect issue_slots[15].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel \n connect issue_slots[15].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel \n connect issue_slots[15].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed \n connect issue_slots[15].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm \n connect issue_slots[15].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel \n connect issue_slots[15].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename \n connect issue_slots[15].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken \n connect issue_slots[15].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob \n connect issue_slots[15].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst \n connect issue_slots[15].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx \n connect issue_slots[15].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov \n connect issue_slots[15].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc \n connect issue_slots[15].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc \n connect issue_slots[15].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret \n connect issue_slots[15].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo \n connect issue_slots[15].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence \n connect issue_slots[15].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei \n connect issue_slots[15].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence \n connect issue_slots[15].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb \n connect issue_slots[15].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type \n connect issue_slots[15].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag \n connect issue_slots[15].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask \n connect issue_slots[15].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel \n connect issue_slots[15].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint \n connect issue_slots[15].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint \n connect issue_slots[15].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint \n connect issue_slots[15].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child \n connect issue_slots[15].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child \n connect issue_slots[15].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen \n connect issue_slots[15].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen \n connect issue_slots[15].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued \n connect issue_slots[15].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] \n connect issue_slots[15].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] \n connect issue_slots[15].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] \n connect issue_slots[15].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] \n connect issue_slots[15].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] \n connect issue_slots[15].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] \n connect issue_slots[15].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] \n connect issue_slots[15].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] \n connect issue_slots[15].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] \n connect issue_slots[15].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] \n connect issue_slots[15].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] \n connect issue_slots[15].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] \n connect issue_slots[15].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] \n connect issue_slots[15].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] \n connect issue_slots[15].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc \n connect issue_slots[15].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc \n connect issue_slots[15].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst \n connect issue_slots[15].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst \n connect issue_slots[15].wakeup_ports[0].valid, io.wakeup_ports[0].valid \n connect issue_slots[15].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy \n connect issue_slots[15].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask \n connect issue_slots[15].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable \n connect issue_slots[15].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc \n connect issue_slots[15].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc \n connect issue_slots[15].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if \n connect issue_slots[15].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if \n connect issue_slots[15].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if \n connect issue_slots[15].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if \n connect issue_slots[15].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if \n connect issue_slots[15].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ \n connect issue_slots[15].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm \n connect issue_slots[15].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val \n connect issue_slots[15].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op \n connect issue_slots[15].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw \n connect issue_slots[15].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en \n connect issue_slots[15].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype \n connect issue_slots[15].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype \n connect issue_slots[15].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype \n connect issue_slots[15].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 \n connect issue_slots[15].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 \n connect issue_slots[15].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 \n connect issue_slots[15].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst \n connect issue_slots[15].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 \n connect issue_slots[15].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd \n connect issue_slots[15].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit \n connect issue_slots[15].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique \n connect issue_slots[15].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq \n connect issue_slots[15].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq \n connect issue_slots[15].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed \n connect issue_slots[15].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size \n connect issue_slots[15].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd \n connect issue_slots[15].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause \n connect issue_slots[15].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception \n connect issue_slots[15].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst \n connect issue_slots[15].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy \n connect issue_slots[15].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy \n connect issue_slots[15].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy \n connect issue_slots[15].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy \n connect issue_slots[15].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred \n connect issue_slots[15].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 \n connect issue_slots[15].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 \n connect issue_slots[15].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 \n connect issue_slots[15].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst \n connect issue_slots[15].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx \n connect issue_slots[15].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx \n connect issue_slots[15].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx \n connect issue_slots[15].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx \n connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec \n connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags \n connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt \n connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div \n connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma \n connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint \n connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint \n connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 \n connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 \n connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 \n connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 \n connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 \n connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen \n connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst \n connect issue_slots[15].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel \n connect issue_slots[15].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel \n connect issue_slots[15].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed \n connect issue_slots[15].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm \n connect issue_slots[15].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel \n connect issue_slots[15].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename \n connect issue_slots[15].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken \n connect issue_slots[15].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob \n connect issue_slots[15].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst \n connect issue_slots[15].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx \n connect issue_slots[15].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov \n connect issue_slots[15].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc \n connect issue_slots[15].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc \n connect issue_slots[15].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret \n connect issue_slots[15].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo \n connect issue_slots[15].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence \n connect issue_slots[15].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei \n connect issue_slots[15].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence \n connect issue_slots[15].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb \n connect issue_slots[15].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type \n connect issue_slots[15].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag \n connect issue_slots[15].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask \n connect issue_slots[15].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel \n connect issue_slots[15].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint \n connect issue_slots[15].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint \n connect issue_slots[15].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint \n connect issue_slots[15].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child \n connect issue_slots[15].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child \n connect issue_slots[15].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen \n connect issue_slots[15].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen \n connect issue_slots[15].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued \n connect issue_slots[15].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] \n connect issue_slots[15].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] \n connect issue_slots[15].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] \n connect issue_slots[15].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] \n connect issue_slots[15].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] \n connect issue_slots[15].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] \n connect issue_slots[15].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] \n connect issue_slots[15].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] \n connect issue_slots[15].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] \n connect issue_slots[15].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] \n connect issue_slots[15].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] \n connect issue_slots[15].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] \n connect issue_slots[15].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] \n connect issue_slots[15].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] \n connect issue_slots[15].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc \n connect issue_slots[15].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc \n connect issue_slots[15].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst \n connect issue_slots[15].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst \n connect issue_slots[15].wakeup_ports[1].valid, io.wakeup_ports[1].valid \n connect issue_slots[15].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy \n connect issue_slots[15].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask \n connect issue_slots[15].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable \n connect issue_slots[15].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc \n connect issue_slots[15].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc \n connect issue_slots[15].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if \n connect issue_slots[15].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if \n connect issue_slots[15].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if \n connect issue_slots[15].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if \n connect issue_slots[15].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if \n connect issue_slots[15].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ \n connect issue_slots[15].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm \n connect issue_slots[15].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val \n connect issue_slots[15].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op \n connect issue_slots[15].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw \n connect issue_slots[15].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en \n connect issue_slots[15].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype \n connect issue_slots[15].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype \n connect issue_slots[15].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype \n connect issue_slots[15].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 \n connect issue_slots[15].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 \n connect issue_slots[15].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 \n connect issue_slots[15].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst \n connect issue_slots[15].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 \n connect issue_slots[15].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd \n connect issue_slots[15].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit \n connect issue_slots[15].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique \n connect issue_slots[15].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq \n connect issue_slots[15].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq \n connect issue_slots[15].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed \n connect issue_slots[15].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size \n connect issue_slots[15].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd \n connect issue_slots[15].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause \n connect issue_slots[15].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception \n connect issue_slots[15].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst \n connect issue_slots[15].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy \n connect issue_slots[15].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy \n connect issue_slots[15].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy \n connect issue_slots[15].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy \n connect issue_slots[15].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred \n connect issue_slots[15].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 \n connect issue_slots[15].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 \n connect issue_slots[15].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 \n connect issue_slots[15].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst \n connect issue_slots[15].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx \n connect issue_slots[15].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx \n connect issue_slots[15].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx \n connect issue_slots[15].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx \n connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec \n connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags \n connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt \n connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div \n connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma \n connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint \n connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint \n connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 \n connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 \n connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 \n connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 \n connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 \n connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen \n connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst \n connect issue_slots[15].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel \n connect issue_slots[15].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel \n connect issue_slots[15].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed \n connect issue_slots[15].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm \n connect issue_slots[15].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel \n connect issue_slots[15].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename \n connect issue_slots[15].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken \n connect issue_slots[15].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob \n connect issue_slots[15].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst \n connect issue_slots[15].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx \n connect issue_slots[15].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov \n connect issue_slots[15].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc \n connect issue_slots[15].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc \n connect issue_slots[15].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret \n connect issue_slots[15].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo \n connect issue_slots[15].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence \n connect issue_slots[15].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei \n connect issue_slots[15].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence \n connect issue_slots[15].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb \n connect issue_slots[15].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type \n connect issue_slots[15].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag \n connect issue_slots[15].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask \n connect issue_slots[15].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel \n connect issue_slots[15].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint \n connect issue_slots[15].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint \n connect issue_slots[15].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint \n connect issue_slots[15].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child \n connect issue_slots[15].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child \n connect issue_slots[15].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen \n connect issue_slots[15].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen \n connect issue_slots[15].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued \n connect issue_slots[15].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] \n connect issue_slots[15].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] \n connect issue_slots[15].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] \n connect issue_slots[15].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] \n connect issue_slots[15].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] \n connect issue_slots[15].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] \n connect issue_slots[15].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] \n connect issue_slots[15].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] \n connect issue_slots[15].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] \n connect issue_slots[15].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] \n connect issue_slots[15].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] \n connect issue_slots[15].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] \n connect issue_slots[15].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] \n connect issue_slots[15].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] \n connect issue_slots[15].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc \n connect issue_slots[15].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc \n connect issue_slots[15].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst \n connect issue_slots[15].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst \n connect issue_slots[15].wakeup_ports[2].valid, io.wakeup_ports[2].valid \n connect issue_slots[15].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy \n connect issue_slots[15].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask \n connect issue_slots[15].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable \n connect issue_slots[15].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc \n connect issue_slots[15].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc \n connect issue_slots[15].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if \n connect issue_slots[15].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if \n connect issue_slots[15].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if \n connect issue_slots[15].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if \n connect issue_slots[15].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if \n connect issue_slots[15].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ \n connect issue_slots[15].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm \n connect issue_slots[15].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val \n connect issue_slots[15].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op \n connect issue_slots[15].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw \n connect issue_slots[15].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en \n connect issue_slots[15].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype \n connect issue_slots[15].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype \n connect issue_slots[15].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype \n connect issue_slots[15].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 \n connect issue_slots[15].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 \n connect issue_slots[15].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 \n connect issue_slots[15].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst \n connect issue_slots[15].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 \n connect issue_slots[15].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd \n connect issue_slots[15].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit \n connect issue_slots[15].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique \n connect issue_slots[15].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq \n connect issue_slots[15].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq \n connect issue_slots[15].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed \n connect issue_slots[15].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size \n connect issue_slots[15].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd \n connect issue_slots[15].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause \n connect issue_slots[15].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception \n connect issue_slots[15].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst \n connect issue_slots[15].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy \n connect issue_slots[15].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy \n connect issue_slots[15].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy \n connect issue_slots[15].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy \n connect issue_slots[15].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred \n connect issue_slots[15].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 \n connect issue_slots[15].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 \n connect issue_slots[15].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 \n connect issue_slots[15].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst \n connect issue_slots[15].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx \n connect issue_slots[15].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx \n connect issue_slots[15].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx \n connect issue_slots[15].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx \n connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec \n connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags \n connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt \n connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div \n connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma \n connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint \n connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint \n connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 \n connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 \n connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 \n connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 \n connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 \n connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen \n connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst \n connect issue_slots[15].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel \n connect issue_slots[15].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel \n connect issue_slots[15].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed \n connect issue_slots[15].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm \n connect issue_slots[15].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel \n connect issue_slots[15].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename \n connect issue_slots[15].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken \n connect issue_slots[15].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob \n connect issue_slots[15].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst \n connect issue_slots[15].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx \n connect issue_slots[15].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov \n connect issue_slots[15].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc \n connect issue_slots[15].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc \n connect issue_slots[15].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret \n connect issue_slots[15].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo \n connect issue_slots[15].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence \n connect issue_slots[15].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei \n connect issue_slots[15].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence \n connect issue_slots[15].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb \n connect issue_slots[15].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type \n connect issue_slots[15].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag \n connect issue_slots[15].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask \n connect issue_slots[15].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel \n connect issue_slots[15].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint \n connect issue_slots[15].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint \n connect issue_slots[15].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint \n connect issue_slots[15].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child \n connect issue_slots[15].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child \n connect issue_slots[15].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen \n connect issue_slots[15].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen \n connect issue_slots[15].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued \n connect issue_slots[15].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] \n connect issue_slots[15].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] \n connect issue_slots[15].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] \n connect issue_slots[15].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] \n connect issue_slots[15].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] \n connect issue_slots[15].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] \n connect issue_slots[15].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] \n connect issue_slots[15].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] \n connect issue_slots[15].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] \n connect issue_slots[15].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] \n connect issue_slots[15].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] \n connect issue_slots[15].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] \n connect issue_slots[15].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] \n connect issue_slots[15].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] \n connect issue_slots[15].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc \n connect issue_slots[15].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc \n connect issue_slots[15].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst \n connect issue_slots[15].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst \n connect issue_slots[15].wakeup_ports[3].valid, io.wakeup_ports[3].valid \n connect issue_slots[15].pred_wakeup_port.bits, io.pred_wakeup_port.bits \n connect issue_slots[15].pred_wakeup_port.valid, io.pred_wakeup_port.valid \n connect issue_slots[15].child_rebusys, io.child_rebusys \n connect issue_slots[15].squash_grant, io.squash_grant \n connect issue_slots[15].brupdate.b2.target_offset, io.brupdate.b2.target_offset \n connect issue_slots[15].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target \n connect issue_slots[15].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel \n connect issue_slots[15].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type \n connect issue_slots[15].brupdate.b2.taken, io.brupdate.b2.taken \n connect issue_slots[15].brupdate.b2.mispredict, io.brupdate.b2.mispredict \n connect issue_slots[15].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc \n connect issue_slots[15].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc \n connect issue_slots[15].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if \n connect issue_slots[15].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if \n connect issue_slots[15].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if \n connect issue_slots[15].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if \n connect issue_slots[15].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if \n connect issue_slots[15].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ \n connect issue_slots[15].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm \n connect issue_slots[15].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val \n connect issue_slots[15].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op \n connect issue_slots[15].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw \n connect issue_slots[15].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en \n connect issue_slots[15].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype \n connect issue_slots[15].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype \n connect issue_slots[15].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype \n connect issue_slots[15].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 \n connect issue_slots[15].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 \n connect issue_slots[15].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 \n connect issue_slots[15].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst \n connect issue_slots[15].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 \n connect issue_slots[15].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd \n connect issue_slots[15].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit \n connect issue_slots[15].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique \n connect issue_slots[15].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq \n connect issue_slots[15].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq \n connect issue_slots[15].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed \n connect issue_slots[15].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size \n connect issue_slots[15].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd \n connect issue_slots[15].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause \n connect issue_slots[15].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception \n connect issue_slots[15].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst \n connect issue_slots[15].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy \n connect issue_slots[15].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy \n connect issue_slots[15].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy \n connect issue_slots[15].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy \n connect issue_slots[15].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred \n connect issue_slots[15].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 \n connect issue_slots[15].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 \n connect issue_slots[15].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 \n connect issue_slots[15].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst \n connect issue_slots[15].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx \n connect issue_slots[15].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx \n connect issue_slots[15].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx \n connect issue_slots[15].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx \n connect issue_slots[15].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec \n connect issue_slots[15].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags \n connect issue_slots[15].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt \n connect issue_slots[15].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div \n connect issue_slots[15].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma \n connect issue_slots[15].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe \n connect issue_slots[15].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint \n connect issue_slots[15].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint \n connect issue_slots[15].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut \n connect issue_slots[15].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn \n connect issue_slots[15].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 \n connect issue_slots[15].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 \n connect issue_slots[15].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 \n connect issue_slots[15].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 \n connect issue_slots[15].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 \n connect issue_slots[15].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen \n connect issue_slots[15].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst \n connect issue_slots[15].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel \n connect issue_slots[15].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel \n connect issue_slots[15].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed \n connect issue_slots[15].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm \n connect issue_slots[15].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel \n connect issue_slots[15].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename \n connect issue_slots[15].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken \n connect issue_slots[15].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob \n connect issue_slots[15].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst \n connect issue_slots[15].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx \n connect issue_slots[15].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov \n connect issue_slots[15].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc \n connect issue_slots[15].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc \n connect issue_slots[15].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret \n connect issue_slots[15].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo \n connect issue_slots[15].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence \n connect issue_slots[15].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei \n connect issue_slots[15].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence \n connect issue_slots[15].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb \n connect issue_slots[15].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type \n connect issue_slots[15].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag \n connect issue_slots[15].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask \n connect issue_slots[15].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel \n connect issue_slots[15].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint \n connect issue_slots[15].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint \n connect issue_slots[15].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint \n connect issue_slots[15].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child \n connect issue_slots[15].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child \n connect issue_slots[15].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen \n connect issue_slots[15].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen \n connect issue_slots[15].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued \n connect issue_slots[15].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] \n connect issue_slots[15].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] \n connect issue_slots[15].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] \n connect issue_slots[15].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] \n connect issue_slots[15].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] \n connect issue_slots[15].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] \n connect issue_slots[15].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] \n connect issue_slots[15].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] \n connect issue_slots[15].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] \n connect issue_slots[15].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] \n connect issue_slots[15].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] \n connect issue_slots[15].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] \n connect issue_slots[15].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] \n connect issue_slots[15].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] \n connect issue_slots[15].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc \n connect issue_slots[15].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc \n connect issue_slots[15].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst \n connect issue_slots[15].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst \n connect issue_slots[15].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask \n connect issue_slots[15].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask \n connect issue_slots[15].kill, io.flush_pipeline \n connect issue_slots[16].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy \n connect issue_slots[16].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask \n connect issue_slots[16].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable \n connect issue_slots[16].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc \n connect issue_slots[16].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc \n connect issue_slots[16].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if \n connect issue_slots[16].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if \n connect issue_slots[16].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if \n connect issue_slots[16].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if \n connect issue_slots[16].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if \n connect issue_slots[16].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ \n connect issue_slots[16].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm \n connect issue_slots[16].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val \n connect issue_slots[16].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op \n connect issue_slots[16].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw \n connect issue_slots[16].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en \n connect issue_slots[16].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype \n connect issue_slots[16].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype \n connect issue_slots[16].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype \n connect issue_slots[16].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 \n connect issue_slots[16].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 \n connect issue_slots[16].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 \n connect issue_slots[16].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst \n connect issue_slots[16].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 \n connect issue_slots[16].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd \n connect issue_slots[16].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit \n connect issue_slots[16].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique \n connect issue_slots[16].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq \n connect issue_slots[16].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq \n connect issue_slots[16].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed \n connect issue_slots[16].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size \n connect issue_slots[16].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd \n connect issue_slots[16].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause \n connect issue_slots[16].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception \n connect issue_slots[16].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst \n connect issue_slots[16].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy \n connect issue_slots[16].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy \n connect issue_slots[16].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy \n connect issue_slots[16].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy \n connect issue_slots[16].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred \n connect issue_slots[16].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 \n connect issue_slots[16].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 \n connect issue_slots[16].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 \n connect issue_slots[16].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst \n connect issue_slots[16].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx \n connect issue_slots[16].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx \n connect issue_slots[16].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx \n connect issue_slots[16].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx \n connect issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec \n connect issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags \n connect issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt \n connect issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div \n connect issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma \n connect issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint \n connect issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint \n connect issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 \n connect issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 \n connect issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 \n connect issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 \n connect issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 \n connect issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen \n connect issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst \n connect issue_slots[16].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel \n connect issue_slots[16].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel \n connect issue_slots[16].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed \n connect issue_slots[16].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm \n connect issue_slots[16].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel \n connect issue_slots[16].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename \n connect issue_slots[16].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken \n connect issue_slots[16].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob \n connect issue_slots[16].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst \n connect issue_slots[16].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx \n connect issue_slots[16].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov \n connect issue_slots[16].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc \n connect issue_slots[16].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc \n connect issue_slots[16].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret \n connect issue_slots[16].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo \n connect issue_slots[16].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence \n connect issue_slots[16].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei \n connect issue_slots[16].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence \n connect issue_slots[16].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb \n connect issue_slots[16].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type \n connect issue_slots[16].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag \n connect issue_slots[16].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask \n connect issue_slots[16].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel \n connect issue_slots[16].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint \n connect issue_slots[16].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint \n connect issue_slots[16].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint \n connect issue_slots[16].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child \n connect issue_slots[16].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child \n connect issue_slots[16].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen \n connect issue_slots[16].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen \n connect issue_slots[16].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued \n connect issue_slots[16].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] \n connect issue_slots[16].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] \n connect issue_slots[16].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] \n connect issue_slots[16].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] \n connect issue_slots[16].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] \n connect issue_slots[16].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] \n connect issue_slots[16].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] \n connect issue_slots[16].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] \n connect issue_slots[16].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] \n connect issue_slots[16].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] \n connect issue_slots[16].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] \n connect issue_slots[16].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] \n connect issue_slots[16].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] \n connect issue_slots[16].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] \n connect issue_slots[16].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc \n connect issue_slots[16].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc \n connect issue_slots[16].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst \n connect issue_slots[16].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst \n connect issue_slots[16].wakeup_ports[0].valid, io.wakeup_ports[0].valid \n connect issue_slots[16].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy \n connect issue_slots[16].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask \n connect issue_slots[16].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable \n connect issue_slots[16].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc \n connect issue_slots[16].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc \n connect issue_slots[16].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if \n connect issue_slots[16].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if \n connect issue_slots[16].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if \n connect issue_slots[16].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if \n connect issue_slots[16].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if \n connect issue_slots[16].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ \n connect issue_slots[16].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm \n connect issue_slots[16].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val \n connect issue_slots[16].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op \n connect issue_slots[16].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw \n connect issue_slots[16].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en \n connect issue_slots[16].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype \n connect issue_slots[16].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype \n connect issue_slots[16].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype \n connect issue_slots[16].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 \n connect issue_slots[16].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 \n connect issue_slots[16].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 \n connect issue_slots[16].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst \n connect issue_slots[16].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 \n connect issue_slots[16].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd \n connect issue_slots[16].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit \n connect issue_slots[16].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique \n connect issue_slots[16].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq \n connect issue_slots[16].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq \n connect issue_slots[16].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed \n connect issue_slots[16].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size \n connect issue_slots[16].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd \n connect issue_slots[16].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause \n connect issue_slots[16].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception \n connect issue_slots[16].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst \n connect issue_slots[16].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy \n connect issue_slots[16].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy \n connect issue_slots[16].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy \n connect issue_slots[16].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy \n connect issue_slots[16].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred \n connect issue_slots[16].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 \n connect issue_slots[16].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 \n connect issue_slots[16].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 \n connect issue_slots[16].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst \n connect issue_slots[16].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx \n connect issue_slots[16].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx \n connect issue_slots[16].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx \n connect issue_slots[16].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx \n connect issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec \n connect issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags \n connect issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt \n connect issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div \n connect issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma \n connect issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint \n connect issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint \n connect issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 \n connect issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 \n connect issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 \n connect issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 \n connect issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 \n connect issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen \n connect issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst \n connect issue_slots[16].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel \n connect issue_slots[16].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel \n connect issue_slots[16].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed \n connect issue_slots[16].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm \n connect issue_slots[16].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel \n connect issue_slots[16].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename \n connect issue_slots[16].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken \n connect issue_slots[16].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob \n connect issue_slots[16].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst \n connect issue_slots[16].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx \n connect issue_slots[16].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov \n connect issue_slots[16].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc \n connect issue_slots[16].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc \n connect issue_slots[16].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret \n connect issue_slots[16].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo \n connect issue_slots[16].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence \n connect issue_slots[16].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei \n connect issue_slots[16].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence \n connect issue_slots[16].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb \n connect issue_slots[16].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type \n connect issue_slots[16].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag \n connect issue_slots[16].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask \n connect issue_slots[16].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel \n connect issue_slots[16].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint \n connect issue_slots[16].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint \n connect issue_slots[16].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint \n connect issue_slots[16].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child \n connect issue_slots[16].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child \n connect issue_slots[16].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen \n connect issue_slots[16].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen \n connect issue_slots[16].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued \n connect issue_slots[16].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] \n connect issue_slots[16].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] \n connect issue_slots[16].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] \n connect issue_slots[16].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] \n connect issue_slots[16].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] \n connect issue_slots[16].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] \n connect issue_slots[16].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] \n connect issue_slots[16].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] \n connect issue_slots[16].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] \n connect issue_slots[16].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] \n connect issue_slots[16].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] \n connect issue_slots[16].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] \n connect issue_slots[16].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] \n connect issue_slots[16].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] \n connect issue_slots[16].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc \n connect issue_slots[16].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc \n connect issue_slots[16].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst \n connect issue_slots[16].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst \n connect issue_slots[16].wakeup_ports[1].valid, io.wakeup_ports[1].valid \n connect issue_slots[16].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy \n connect issue_slots[16].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask \n connect issue_slots[16].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable \n connect issue_slots[16].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc \n connect issue_slots[16].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc \n connect issue_slots[16].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if \n connect issue_slots[16].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if \n connect issue_slots[16].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if \n connect issue_slots[16].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if \n connect issue_slots[16].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if \n connect issue_slots[16].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ \n connect issue_slots[16].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm \n connect issue_slots[16].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val \n connect issue_slots[16].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op \n connect issue_slots[16].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw \n connect issue_slots[16].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en \n connect issue_slots[16].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype \n connect issue_slots[16].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype \n connect issue_slots[16].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype \n connect issue_slots[16].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 \n connect issue_slots[16].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 \n connect issue_slots[16].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 \n connect issue_slots[16].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst \n connect issue_slots[16].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 \n connect issue_slots[16].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd \n connect issue_slots[16].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit \n connect issue_slots[16].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique \n connect issue_slots[16].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq \n connect issue_slots[16].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq \n connect issue_slots[16].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed \n connect issue_slots[16].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size \n connect issue_slots[16].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd \n connect issue_slots[16].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause \n connect issue_slots[16].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception \n connect issue_slots[16].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst \n connect issue_slots[16].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy \n connect issue_slots[16].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy \n connect issue_slots[16].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy \n connect issue_slots[16].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy \n connect issue_slots[16].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred \n connect issue_slots[16].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 \n connect issue_slots[16].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 \n connect issue_slots[16].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 \n connect issue_slots[16].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst \n connect issue_slots[16].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx \n connect issue_slots[16].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx \n connect issue_slots[16].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx \n connect issue_slots[16].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx \n connect issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec \n connect issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags \n connect issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt \n connect issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div \n connect issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma \n connect issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint \n connect issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint \n connect issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 \n connect issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 \n connect issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 \n connect issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 \n connect issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 \n connect issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen \n connect issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst \n connect issue_slots[16].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel \n connect issue_slots[16].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel \n connect issue_slots[16].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed \n connect issue_slots[16].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm \n connect issue_slots[16].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel \n connect issue_slots[16].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename \n connect issue_slots[16].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken \n connect issue_slots[16].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob \n connect issue_slots[16].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst \n connect issue_slots[16].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx \n connect issue_slots[16].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov \n connect issue_slots[16].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc \n connect issue_slots[16].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc \n connect issue_slots[16].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret \n connect issue_slots[16].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo \n connect issue_slots[16].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence \n connect issue_slots[16].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei \n connect issue_slots[16].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence \n connect issue_slots[16].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb \n connect issue_slots[16].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type \n connect issue_slots[16].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag \n connect issue_slots[16].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask \n connect issue_slots[16].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel \n connect issue_slots[16].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint \n connect issue_slots[16].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint \n connect issue_slots[16].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint \n connect issue_slots[16].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child \n connect issue_slots[16].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child \n connect issue_slots[16].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen \n connect issue_slots[16].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen \n connect issue_slots[16].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued \n connect issue_slots[16].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] \n connect issue_slots[16].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] \n connect issue_slots[16].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] \n connect issue_slots[16].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] \n connect issue_slots[16].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] \n connect issue_slots[16].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] \n connect issue_slots[16].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] \n connect issue_slots[16].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] \n connect issue_slots[16].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] \n connect issue_slots[16].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] \n connect issue_slots[16].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] \n connect issue_slots[16].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] \n connect issue_slots[16].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] \n connect issue_slots[16].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] \n connect issue_slots[16].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc \n connect issue_slots[16].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc \n connect issue_slots[16].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst \n connect issue_slots[16].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst \n connect issue_slots[16].wakeup_ports[2].valid, io.wakeup_ports[2].valid \n connect issue_slots[16].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy \n connect issue_slots[16].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask \n connect issue_slots[16].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable \n connect issue_slots[16].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc \n connect issue_slots[16].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc \n connect issue_slots[16].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if \n connect issue_slots[16].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if \n connect issue_slots[16].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if \n connect issue_slots[16].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if \n connect issue_slots[16].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if \n connect issue_slots[16].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ \n connect issue_slots[16].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm \n connect issue_slots[16].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val \n connect issue_slots[16].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op \n connect issue_slots[16].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw \n connect issue_slots[16].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en \n connect issue_slots[16].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype \n connect issue_slots[16].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype \n connect issue_slots[16].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype \n connect issue_slots[16].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 \n connect issue_slots[16].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 \n connect issue_slots[16].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 \n connect issue_slots[16].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst \n connect issue_slots[16].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 \n connect issue_slots[16].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd \n connect issue_slots[16].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit \n connect issue_slots[16].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique \n connect issue_slots[16].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq \n connect issue_slots[16].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq \n connect issue_slots[16].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed \n connect issue_slots[16].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size \n connect issue_slots[16].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd \n connect issue_slots[16].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause \n connect issue_slots[16].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception \n connect issue_slots[16].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst \n connect issue_slots[16].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy \n connect issue_slots[16].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy \n connect issue_slots[16].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy \n connect issue_slots[16].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy \n connect issue_slots[16].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred \n connect issue_slots[16].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 \n connect issue_slots[16].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 \n connect issue_slots[16].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 \n connect issue_slots[16].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst \n connect issue_slots[16].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx \n connect issue_slots[16].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx \n connect issue_slots[16].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx \n connect issue_slots[16].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx \n connect issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec \n connect issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags \n connect issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt \n connect issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div \n connect issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma \n connect issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint \n connect issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint \n connect issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 \n connect issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 \n connect issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 \n connect issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 \n connect issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 \n connect issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen \n connect issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst \n connect issue_slots[16].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel \n connect issue_slots[16].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel \n connect issue_slots[16].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed \n connect issue_slots[16].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm \n connect issue_slots[16].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel \n connect issue_slots[16].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename \n connect issue_slots[16].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken \n connect issue_slots[16].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob \n connect issue_slots[16].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst \n connect issue_slots[16].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx \n connect issue_slots[16].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov \n connect issue_slots[16].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc \n connect issue_slots[16].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc \n connect issue_slots[16].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret \n connect issue_slots[16].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo \n connect issue_slots[16].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence \n connect issue_slots[16].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei \n connect issue_slots[16].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence \n connect issue_slots[16].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb \n connect issue_slots[16].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type \n connect issue_slots[16].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag \n connect issue_slots[16].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask \n connect issue_slots[16].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel \n connect issue_slots[16].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint \n connect issue_slots[16].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint \n connect issue_slots[16].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint \n connect issue_slots[16].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child \n connect issue_slots[16].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child \n connect issue_slots[16].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen \n connect issue_slots[16].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen \n connect issue_slots[16].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued \n connect issue_slots[16].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] \n connect issue_slots[16].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] \n connect issue_slots[16].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] \n connect issue_slots[16].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] \n connect issue_slots[16].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] \n connect issue_slots[16].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] \n connect issue_slots[16].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] \n connect issue_slots[16].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] \n connect issue_slots[16].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] \n connect issue_slots[16].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] \n connect issue_slots[16].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] \n connect issue_slots[16].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] \n connect issue_slots[16].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] \n connect issue_slots[16].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] \n connect issue_slots[16].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc \n connect issue_slots[16].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc \n connect issue_slots[16].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst \n connect issue_slots[16].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst \n connect issue_slots[16].wakeup_ports[3].valid, io.wakeup_ports[3].valid \n connect issue_slots[16].pred_wakeup_port.bits, io.pred_wakeup_port.bits \n connect issue_slots[16].pred_wakeup_port.valid, io.pred_wakeup_port.valid \n connect issue_slots[16].child_rebusys, io.child_rebusys \n connect issue_slots[16].squash_grant, io.squash_grant \n connect issue_slots[16].brupdate.b2.target_offset, io.brupdate.b2.target_offset \n connect issue_slots[16].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target \n connect issue_slots[16].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel \n connect issue_slots[16].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type \n connect issue_slots[16].brupdate.b2.taken, io.brupdate.b2.taken \n connect issue_slots[16].brupdate.b2.mispredict, io.brupdate.b2.mispredict \n connect issue_slots[16].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc \n connect issue_slots[16].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc \n connect issue_slots[16].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if \n connect issue_slots[16].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if \n connect issue_slots[16].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if \n connect issue_slots[16].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if \n connect issue_slots[16].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if \n connect issue_slots[16].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ \n connect issue_slots[16].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm \n connect issue_slots[16].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val \n connect issue_slots[16].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op \n connect issue_slots[16].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw \n connect issue_slots[16].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en \n connect issue_slots[16].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype \n connect issue_slots[16].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype \n connect issue_slots[16].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype \n connect issue_slots[16].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 \n connect issue_slots[16].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 \n connect issue_slots[16].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 \n connect issue_slots[16].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst \n connect issue_slots[16].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 \n connect issue_slots[16].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd \n connect issue_slots[16].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit \n connect issue_slots[16].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique \n connect issue_slots[16].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq \n connect issue_slots[16].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq \n connect issue_slots[16].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed \n connect issue_slots[16].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size \n connect issue_slots[16].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd \n connect issue_slots[16].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause \n connect issue_slots[16].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception \n connect issue_slots[16].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst \n connect issue_slots[16].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy \n connect issue_slots[16].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy \n connect issue_slots[16].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy \n connect issue_slots[16].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy \n connect issue_slots[16].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred \n connect issue_slots[16].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 \n connect issue_slots[16].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 \n connect issue_slots[16].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 \n connect issue_slots[16].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst \n connect issue_slots[16].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx \n connect issue_slots[16].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx \n connect issue_slots[16].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx \n connect issue_slots[16].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx \n connect issue_slots[16].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec \n connect issue_slots[16].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags \n connect issue_slots[16].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt \n connect issue_slots[16].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div \n connect issue_slots[16].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma \n connect issue_slots[16].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe \n connect issue_slots[16].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint \n connect issue_slots[16].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint \n connect issue_slots[16].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut \n connect issue_slots[16].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn \n connect issue_slots[16].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 \n connect issue_slots[16].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 \n connect issue_slots[16].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 \n connect issue_slots[16].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 \n connect issue_slots[16].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 \n connect issue_slots[16].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen \n connect issue_slots[16].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst \n connect issue_slots[16].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel \n connect issue_slots[16].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel \n connect issue_slots[16].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed \n connect issue_slots[16].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm \n connect issue_slots[16].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel \n connect issue_slots[16].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename \n connect issue_slots[16].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken \n connect issue_slots[16].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob \n connect issue_slots[16].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst \n connect issue_slots[16].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx \n connect issue_slots[16].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov \n connect issue_slots[16].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc \n connect issue_slots[16].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc \n connect issue_slots[16].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret \n connect issue_slots[16].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo \n connect issue_slots[16].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence \n connect issue_slots[16].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei \n connect issue_slots[16].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence \n connect issue_slots[16].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb \n connect issue_slots[16].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type \n connect issue_slots[16].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag \n connect issue_slots[16].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask \n connect issue_slots[16].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel \n connect issue_slots[16].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint \n connect issue_slots[16].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint \n connect issue_slots[16].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint \n connect issue_slots[16].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child \n connect issue_slots[16].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child \n connect issue_slots[16].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen \n connect issue_slots[16].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen \n connect issue_slots[16].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued \n connect issue_slots[16].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] \n connect issue_slots[16].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] \n connect issue_slots[16].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] \n connect issue_slots[16].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] \n connect issue_slots[16].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] \n connect issue_slots[16].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] \n connect issue_slots[16].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] \n connect issue_slots[16].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] \n connect issue_slots[16].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] \n connect issue_slots[16].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] \n connect issue_slots[16].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] \n connect issue_slots[16].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] \n connect issue_slots[16].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] \n connect issue_slots[16].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] \n connect issue_slots[16].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc \n connect issue_slots[16].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc \n connect issue_slots[16].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst \n connect issue_slots[16].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst \n connect issue_slots[16].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask \n connect issue_slots[16].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask \n connect issue_slots[16].kill, io.flush_pipeline \n connect issue_slots[17].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy \n connect issue_slots[17].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask \n connect issue_slots[17].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable \n connect issue_slots[17].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc \n connect issue_slots[17].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc \n connect issue_slots[17].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if \n connect issue_slots[17].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if \n connect issue_slots[17].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if \n connect issue_slots[17].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if \n connect issue_slots[17].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if \n connect issue_slots[17].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ \n connect issue_slots[17].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm \n connect issue_slots[17].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val \n connect issue_slots[17].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op \n connect issue_slots[17].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw \n connect issue_slots[17].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en \n connect issue_slots[17].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype \n connect issue_slots[17].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype \n connect issue_slots[17].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype \n connect issue_slots[17].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 \n connect issue_slots[17].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 \n connect issue_slots[17].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 \n connect issue_slots[17].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst \n connect issue_slots[17].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 \n connect issue_slots[17].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd \n connect issue_slots[17].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit \n connect issue_slots[17].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique \n connect issue_slots[17].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq \n connect issue_slots[17].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq \n connect issue_slots[17].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed \n connect issue_slots[17].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size \n connect issue_slots[17].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd \n connect issue_slots[17].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause \n connect issue_slots[17].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception \n connect issue_slots[17].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst \n connect issue_slots[17].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy \n connect issue_slots[17].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy \n connect issue_slots[17].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy \n connect issue_slots[17].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy \n connect issue_slots[17].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred \n connect issue_slots[17].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 \n connect issue_slots[17].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 \n connect issue_slots[17].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 \n connect issue_slots[17].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst \n connect issue_slots[17].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx \n connect issue_slots[17].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx \n connect issue_slots[17].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx \n connect issue_slots[17].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx \n connect issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec \n connect issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags \n connect issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt \n connect issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div \n connect issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma \n connect issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint \n connect issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint \n connect issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 \n connect issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 \n connect issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 \n connect issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 \n connect issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 \n connect issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen \n connect issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst \n connect issue_slots[17].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel \n connect issue_slots[17].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel \n connect issue_slots[17].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed \n connect issue_slots[17].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm \n connect issue_slots[17].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel \n connect issue_slots[17].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename \n connect issue_slots[17].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken \n connect issue_slots[17].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob \n connect issue_slots[17].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst \n connect issue_slots[17].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx \n connect issue_slots[17].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov \n connect issue_slots[17].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc \n connect issue_slots[17].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc \n connect issue_slots[17].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret \n connect issue_slots[17].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo \n connect issue_slots[17].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence \n connect issue_slots[17].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei \n connect issue_slots[17].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence \n connect issue_slots[17].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb \n connect issue_slots[17].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type \n connect issue_slots[17].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag \n connect issue_slots[17].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask \n connect issue_slots[17].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel \n connect issue_slots[17].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint \n connect issue_slots[17].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint \n connect issue_slots[17].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint \n connect issue_slots[17].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child \n connect issue_slots[17].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child \n connect issue_slots[17].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen \n connect issue_slots[17].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen \n connect issue_slots[17].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued \n connect issue_slots[17].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] \n connect issue_slots[17].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] \n connect issue_slots[17].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] \n connect issue_slots[17].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] \n connect issue_slots[17].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] \n connect issue_slots[17].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] \n connect issue_slots[17].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] \n connect issue_slots[17].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] \n connect issue_slots[17].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] \n connect issue_slots[17].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] \n connect issue_slots[17].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] \n connect issue_slots[17].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] \n connect issue_slots[17].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] \n connect issue_slots[17].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] \n connect issue_slots[17].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc \n connect issue_slots[17].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc \n connect issue_slots[17].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst \n connect issue_slots[17].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst \n connect issue_slots[17].wakeup_ports[0].valid, io.wakeup_ports[0].valid \n connect issue_slots[17].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy \n connect issue_slots[17].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask \n connect issue_slots[17].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable \n connect issue_slots[17].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc \n connect issue_slots[17].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc \n connect issue_slots[17].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if \n connect issue_slots[17].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if \n connect issue_slots[17].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if \n connect issue_slots[17].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if \n connect issue_slots[17].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if \n connect issue_slots[17].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ \n connect issue_slots[17].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm \n connect issue_slots[17].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val \n connect issue_slots[17].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op \n connect issue_slots[17].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw \n connect issue_slots[17].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en \n connect issue_slots[17].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype \n connect issue_slots[17].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype \n connect issue_slots[17].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype \n connect issue_slots[17].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 \n connect issue_slots[17].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 \n connect issue_slots[17].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 \n connect issue_slots[17].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst \n connect issue_slots[17].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 \n connect issue_slots[17].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd \n connect issue_slots[17].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit \n connect issue_slots[17].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique \n connect issue_slots[17].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq \n connect issue_slots[17].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq \n connect issue_slots[17].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed \n connect issue_slots[17].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size \n connect issue_slots[17].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd \n connect issue_slots[17].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause \n connect issue_slots[17].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception \n connect issue_slots[17].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst \n connect issue_slots[17].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy \n connect issue_slots[17].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy \n connect issue_slots[17].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy \n connect issue_slots[17].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy \n connect issue_slots[17].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred \n connect issue_slots[17].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 \n connect issue_slots[17].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 \n connect issue_slots[17].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 \n connect issue_slots[17].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst \n connect issue_slots[17].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx \n connect issue_slots[17].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx \n connect issue_slots[17].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx \n connect issue_slots[17].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx \n connect issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec \n connect issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags \n connect issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt \n connect issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div \n connect issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma \n connect issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint \n connect issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint \n connect issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 \n connect issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 \n connect issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 \n connect issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 \n connect issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 \n connect issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen \n connect issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst \n connect issue_slots[17].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel \n connect issue_slots[17].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel \n connect issue_slots[17].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed \n connect issue_slots[17].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm \n connect issue_slots[17].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel \n connect issue_slots[17].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename \n connect issue_slots[17].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken \n connect issue_slots[17].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob \n connect issue_slots[17].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst \n connect issue_slots[17].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx \n connect issue_slots[17].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov \n connect issue_slots[17].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc \n connect issue_slots[17].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc \n connect issue_slots[17].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret \n connect issue_slots[17].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo \n connect issue_slots[17].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence \n connect issue_slots[17].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei \n connect issue_slots[17].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence \n connect issue_slots[17].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb \n connect issue_slots[17].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type \n connect issue_slots[17].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag \n connect issue_slots[17].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask \n connect issue_slots[17].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel \n connect issue_slots[17].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint \n connect issue_slots[17].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint \n connect issue_slots[17].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint \n connect issue_slots[17].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child \n connect issue_slots[17].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child \n connect issue_slots[17].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen \n connect issue_slots[17].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen \n connect issue_slots[17].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued \n connect issue_slots[17].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] \n connect issue_slots[17].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] \n connect issue_slots[17].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] \n connect issue_slots[17].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] \n connect issue_slots[17].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] \n connect issue_slots[17].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] \n connect issue_slots[17].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] \n connect issue_slots[17].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] \n connect issue_slots[17].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] \n connect issue_slots[17].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] \n connect issue_slots[17].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] \n connect issue_slots[17].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] \n connect issue_slots[17].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] \n connect issue_slots[17].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] \n connect issue_slots[17].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc \n connect issue_slots[17].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc \n connect issue_slots[17].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst \n connect issue_slots[17].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst \n connect issue_slots[17].wakeup_ports[1].valid, io.wakeup_ports[1].valid \n connect issue_slots[17].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy \n connect issue_slots[17].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask \n connect issue_slots[17].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable \n connect issue_slots[17].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc \n connect issue_slots[17].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc \n connect issue_slots[17].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if \n connect issue_slots[17].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if \n connect issue_slots[17].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if \n connect issue_slots[17].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if \n connect issue_slots[17].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if \n connect issue_slots[17].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ \n connect issue_slots[17].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm \n connect issue_slots[17].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val \n connect issue_slots[17].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op \n connect issue_slots[17].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw \n connect issue_slots[17].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en \n connect issue_slots[17].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype \n connect issue_slots[17].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype \n connect issue_slots[17].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype \n connect issue_slots[17].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 \n connect issue_slots[17].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 \n connect issue_slots[17].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 \n connect issue_slots[17].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst \n connect issue_slots[17].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 \n connect issue_slots[17].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd \n connect issue_slots[17].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit \n connect issue_slots[17].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique \n connect issue_slots[17].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq \n connect issue_slots[17].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq \n connect issue_slots[17].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed \n connect issue_slots[17].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size \n connect issue_slots[17].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd \n connect issue_slots[17].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause \n connect issue_slots[17].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception \n connect issue_slots[17].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst \n connect issue_slots[17].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy \n connect issue_slots[17].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy \n connect issue_slots[17].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy \n connect issue_slots[17].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy \n connect issue_slots[17].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred \n connect issue_slots[17].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 \n connect issue_slots[17].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 \n connect issue_slots[17].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 \n connect issue_slots[17].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst \n connect issue_slots[17].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx \n connect issue_slots[17].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx \n connect issue_slots[17].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx \n connect issue_slots[17].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx \n connect issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec \n connect issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags \n connect issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt \n connect issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div \n connect issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma \n connect issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint \n connect issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint \n connect issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 \n connect issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 \n connect issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 \n connect issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 \n connect issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 \n connect issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen \n connect issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst \n connect issue_slots[17].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel \n connect issue_slots[17].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel \n connect issue_slots[17].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed \n connect issue_slots[17].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm \n connect issue_slots[17].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel \n connect issue_slots[17].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename \n connect issue_slots[17].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken \n connect issue_slots[17].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob \n connect issue_slots[17].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst \n connect issue_slots[17].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx \n connect issue_slots[17].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov \n connect issue_slots[17].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc \n connect issue_slots[17].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc \n connect issue_slots[17].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret \n connect issue_slots[17].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo \n connect issue_slots[17].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence \n connect issue_slots[17].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei \n connect issue_slots[17].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence \n connect issue_slots[17].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb \n connect issue_slots[17].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type \n connect issue_slots[17].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag \n connect issue_slots[17].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask \n connect issue_slots[17].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel \n connect issue_slots[17].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint \n connect issue_slots[17].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint \n connect issue_slots[17].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint \n connect issue_slots[17].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child \n connect issue_slots[17].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child \n connect issue_slots[17].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen \n connect issue_slots[17].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen \n connect issue_slots[17].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued \n connect issue_slots[17].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] \n connect issue_slots[17].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] \n connect issue_slots[17].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] \n connect issue_slots[17].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] \n connect issue_slots[17].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] \n connect issue_slots[17].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] \n connect issue_slots[17].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] \n connect issue_slots[17].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] \n connect issue_slots[17].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] \n connect issue_slots[17].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] \n connect issue_slots[17].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] \n connect issue_slots[17].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] \n connect issue_slots[17].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] \n connect issue_slots[17].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] \n connect issue_slots[17].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc \n connect issue_slots[17].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc \n connect issue_slots[17].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst \n connect issue_slots[17].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst \n connect issue_slots[17].wakeup_ports[2].valid, io.wakeup_ports[2].valid \n connect issue_slots[17].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy \n connect issue_slots[17].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask \n connect issue_slots[17].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable \n connect issue_slots[17].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc \n connect issue_slots[17].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc \n connect issue_slots[17].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if \n connect issue_slots[17].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if \n connect issue_slots[17].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if \n connect issue_slots[17].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if \n connect issue_slots[17].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if \n connect issue_slots[17].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ \n connect issue_slots[17].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm \n connect issue_slots[17].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val \n connect issue_slots[17].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op \n connect issue_slots[17].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw \n connect issue_slots[17].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en \n connect issue_slots[17].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype \n connect issue_slots[17].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype \n connect issue_slots[17].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype \n connect issue_slots[17].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 \n connect issue_slots[17].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 \n connect issue_slots[17].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 \n connect issue_slots[17].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst \n connect issue_slots[17].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 \n connect issue_slots[17].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd \n connect issue_slots[17].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit \n connect issue_slots[17].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique \n connect issue_slots[17].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq \n connect issue_slots[17].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq \n connect issue_slots[17].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed \n connect issue_slots[17].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size \n connect issue_slots[17].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd \n connect issue_slots[17].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause \n connect issue_slots[17].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception \n connect issue_slots[17].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst \n connect issue_slots[17].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy \n connect issue_slots[17].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy \n connect issue_slots[17].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy \n connect issue_slots[17].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy \n connect issue_slots[17].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred \n connect issue_slots[17].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 \n connect issue_slots[17].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 \n connect issue_slots[17].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 \n connect issue_slots[17].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst \n connect issue_slots[17].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx \n connect issue_slots[17].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx \n connect issue_slots[17].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx \n connect issue_slots[17].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx \n connect issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec \n connect issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags \n connect issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt \n connect issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div \n connect issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma \n connect issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint \n connect issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint \n connect issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 \n connect issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 \n connect issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 \n connect issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 \n connect issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 \n connect issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen \n connect issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst \n connect issue_slots[17].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel \n connect issue_slots[17].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel \n connect issue_slots[17].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed \n connect issue_slots[17].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm \n connect issue_slots[17].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel \n connect issue_slots[17].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename \n connect issue_slots[17].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken \n connect issue_slots[17].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob \n connect issue_slots[17].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst \n connect issue_slots[17].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx \n connect issue_slots[17].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov \n connect issue_slots[17].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc \n connect issue_slots[17].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc \n connect issue_slots[17].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret \n connect issue_slots[17].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo \n connect issue_slots[17].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence \n connect issue_slots[17].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei \n connect issue_slots[17].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence \n connect issue_slots[17].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb \n connect issue_slots[17].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type \n connect issue_slots[17].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag \n connect issue_slots[17].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask \n connect issue_slots[17].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel \n connect issue_slots[17].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint \n connect issue_slots[17].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint \n connect issue_slots[17].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint \n connect issue_slots[17].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child \n connect issue_slots[17].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child \n connect issue_slots[17].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen \n connect issue_slots[17].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen \n connect issue_slots[17].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued \n connect issue_slots[17].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] \n connect issue_slots[17].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] \n connect issue_slots[17].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] \n connect issue_slots[17].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] \n connect issue_slots[17].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] \n connect issue_slots[17].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] \n connect issue_slots[17].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] \n connect issue_slots[17].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] \n connect issue_slots[17].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] \n connect issue_slots[17].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] \n connect issue_slots[17].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] \n connect issue_slots[17].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] \n connect issue_slots[17].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] \n connect issue_slots[17].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] \n connect issue_slots[17].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc \n connect issue_slots[17].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc \n connect issue_slots[17].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst \n connect issue_slots[17].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst \n connect issue_slots[17].wakeup_ports[3].valid, io.wakeup_ports[3].valid \n connect issue_slots[17].pred_wakeup_port.bits, io.pred_wakeup_port.bits \n connect issue_slots[17].pred_wakeup_port.valid, io.pred_wakeup_port.valid \n connect issue_slots[17].child_rebusys, io.child_rebusys \n connect issue_slots[17].squash_grant, io.squash_grant \n connect issue_slots[17].brupdate.b2.target_offset, io.brupdate.b2.target_offset \n connect issue_slots[17].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target \n connect issue_slots[17].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel \n connect issue_slots[17].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type \n connect issue_slots[17].brupdate.b2.taken, io.brupdate.b2.taken \n connect issue_slots[17].brupdate.b2.mispredict, io.brupdate.b2.mispredict \n connect issue_slots[17].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc \n connect issue_slots[17].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc \n connect issue_slots[17].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if \n connect issue_slots[17].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if \n connect issue_slots[17].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if \n connect issue_slots[17].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if \n connect issue_slots[17].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if \n connect issue_slots[17].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ \n connect issue_slots[17].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm \n connect issue_slots[17].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val \n connect issue_slots[17].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op \n connect issue_slots[17].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw \n connect issue_slots[17].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en \n connect issue_slots[17].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype \n connect issue_slots[17].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype \n connect issue_slots[17].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype \n connect issue_slots[17].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 \n connect issue_slots[17].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 \n connect issue_slots[17].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 \n connect issue_slots[17].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst \n connect issue_slots[17].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 \n connect issue_slots[17].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd \n connect issue_slots[17].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit \n connect issue_slots[17].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique \n connect issue_slots[17].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq \n connect issue_slots[17].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq \n connect issue_slots[17].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed \n connect issue_slots[17].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size \n connect issue_slots[17].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd \n connect issue_slots[17].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause \n connect issue_slots[17].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception \n connect issue_slots[17].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst \n connect issue_slots[17].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy \n connect issue_slots[17].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy \n connect issue_slots[17].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy \n connect issue_slots[17].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy \n connect issue_slots[17].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred \n connect issue_slots[17].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 \n connect issue_slots[17].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 \n connect issue_slots[17].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 \n connect issue_slots[17].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst \n connect issue_slots[17].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx \n connect issue_slots[17].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx \n connect issue_slots[17].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx \n connect issue_slots[17].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx \n connect issue_slots[17].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec \n connect issue_slots[17].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags \n connect issue_slots[17].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt \n connect issue_slots[17].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div \n connect issue_slots[17].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma \n connect issue_slots[17].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe \n connect issue_slots[17].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint \n connect issue_slots[17].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint \n connect issue_slots[17].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut \n connect issue_slots[17].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn \n connect issue_slots[17].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 \n connect issue_slots[17].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 \n connect issue_slots[17].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 \n connect issue_slots[17].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 \n connect issue_slots[17].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 \n connect issue_slots[17].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen \n connect issue_slots[17].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst \n connect issue_slots[17].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel \n connect issue_slots[17].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel \n connect issue_slots[17].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed \n connect issue_slots[17].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm \n connect issue_slots[17].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel \n connect issue_slots[17].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename \n connect issue_slots[17].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken \n connect issue_slots[17].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob \n connect issue_slots[17].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst \n connect issue_slots[17].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx \n connect issue_slots[17].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov \n connect issue_slots[17].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc \n connect issue_slots[17].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc \n connect issue_slots[17].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret \n connect issue_slots[17].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo \n connect issue_slots[17].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence \n connect issue_slots[17].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei \n connect issue_slots[17].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence \n connect issue_slots[17].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb \n connect issue_slots[17].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type \n connect issue_slots[17].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag \n connect issue_slots[17].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask \n connect issue_slots[17].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel \n connect issue_slots[17].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint \n connect issue_slots[17].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint \n connect issue_slots[17].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint \n connect issue_slots[17].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child \n connect issue_slots[17].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child \n connect issue_slots[17].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen \n connect issue_slots[17].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen \n connect issue_slots[17].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued \n connect issue_slots[17].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] \n connect issue_slots[17].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] \n connect issue_slots[17].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] \n connect issue_slots[17].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] \n connect issue_slots[17].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] \n connect issue_slots[17].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] \n connect issue_slots[17].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] \n connect issue_slots[17].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] \n connect issue_slots[17].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] \n connect issue_slots[17].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] \n connect issue_slots[17].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] \n connect issue_slots[17].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] \n connect issue_slots[17].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] \n connect issue_slots[17].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] \n connect issue_slots[17].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc \n connect issue_slots[17].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc \n connect issue_slots[17].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst \n connect issue_slots[17].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst \n connect issue_slots[17].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask \n connect issue_slots[17].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask \n connect issue_slots[17].kill, io.flush_pipeline \n connect issue_slots[18].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy \n connect issue_slots[18].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask \n connect issue_slots[18].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable \n connect issue_slots[18].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc \n connect issue_slots[18].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc \n connect issue_slots[18].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if \n connect issue_slots[18].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if \n connect issue_slots[18].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if \n connect issue_slots[18].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if \n connect issue_slots[18].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if \n connect issue_slots[18].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ \n connect issue_slots[18].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm \n connect issue_slots[18].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val \n connect issue_slots[18].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op \n connect issue_slots[18].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw \n connect issue_slots[18].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en \n connect issue_slots[18].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype \n connect issue_slots[18].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype \n connect issue_slots[18].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype \n connect issue_slots[18].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 \n connect issue_slots[18].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 \n connect issue_slots[18].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 \n connect issue_slots[18].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst \n connect issue_slots[18].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 \n connect issue_slots[18].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd \n connect issue_slots[18].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit \n connect issue_slots[18].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique \n connect issue_slots[18].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq \n connect issue_slots[18].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq \n connect issue_slots[18].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed \n connect issue_slots[18].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size \n connect issue_slots[18].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd \n connect issue_slots[18].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause \n connect issue_slots[18].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception \n connect issue_slots[18].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst \n connect issue_slots[18].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy \n connect issue_slots[18].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy \n connect issue_slots[18].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy \n connect issue_slots[18].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy \n connect issue_slots[18].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred \n connect issue_slots[18].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 \n connect issue_slots[18].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 \n connect issue_slots[18].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 \n connect issue_slots[18].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst \n connect issue_slots[18].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx \n connect issue_slots[18].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx \n connect issue_slots[18].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx \n connect issue_slots[18].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx \n connect issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec \n connect issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags \n connect issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt \n connect issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div \n connect issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma \n connect issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint \n connect issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint \n connect issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 \n connect issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 \n connect issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 \n connect issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 \n connect issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 \n connect issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen \n connect issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst \n connect issue_slots[18].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel \n connect issue_slots[18].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel \n connect issue_slots[18].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed \n connect issue_slots[18].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm \n connect issue_slots[18].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel \n connect issue_slots[18].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename \n connect issue_slots[18].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken \n connect issue_slots[18].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob \n connect issue_slots[18].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst \n connect issue_slots[18].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx \n connect issue_slots[18].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov \n connect issue_slots[18].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc \n connect issue_slots[18].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc \n connect issue_slots[18].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret \n connect issue_slots[18].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo \n connect issue_slots[18].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence \n connect issue_slots[18].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei \n connect issue_slots[18].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence \n connect issue_slots[18].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb \n connect issue_slots[18].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type \n connect issue_slots[18].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag \n connect issue_slots[18].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask \n connect issue_slots[18].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel \n connect issue_slots[18].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint \n connect issue_slots[18].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint \n connect issue_slots[18].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint \n connect issue_slots[18].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child \n connect issue_slots[18].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child \n connect issue_slots[18].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen \n connect issue_slots[18].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen \n connect issue_slots[18].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued \n connect issue_slots[18].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] \n connect issue_slots[18].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] \n connect issue_slots[18].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] \n connect issue_slots[18].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] \n connect issue_slots[18].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] \n connect issue_slots[18].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] \n connect issue_slots[18].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] \n connect issue_slots[18].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] \n connect issue_slots[18].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] \n connect issue_slots[18].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] \n connect issue_slots[18].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] \n connect issue_slots[18].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] \n connect issue_slots[18].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] \n connect issue_slots[18].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] \n connect issue_slots[18].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc \n connect issue_slots[18].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc \n connect issue_slots[18].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst \n connect issue_slots[18].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst \n connect issue_slots[18].wakeup_ports[0].valid, io.wakeup_ports[0].valid \n connect issue_slots[18].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy \n connect issue_slots[18].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask \n connect issue_slots[18].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable \n connect issue_slots[18].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc \n connect issue_slots[18].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc \n connect issue_slots[18].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if \n connect issue_slots[18].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if \n connect issue_slots[18].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if \n connect issue_slots[18].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if \n connect issue_slots[18].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if \n connect issue_slots[18].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ \n connect issue_slots[18].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm \n connect issue_slots[18].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val \n connect issue_slots[18].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op \n connect issue_slots[18].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw \n connect issue_slots[18].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en \n connect issue_slots[18].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype \n connect issue_slots[18].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype \n connect issue_slots[18].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype \n connect issue_slots[18].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 \n connect issue_slots[18].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 \n connect issue_slots[18].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 \n connect issue_slots[18].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst \n connect issue_slots[18].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 \n connect issue_slots[18].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd \n connect issue_slots[18].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit \n connect issue_slots[18].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique \n connect issue_slots[18].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq \n connect issue_slots[18].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq \n connect issue_slots[18].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed \n connect issue_slots[18].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size \n connect issue_slots[18].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd \n connect issue_slots[18].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause \n connect issue_slots[18].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception \n connect issue_slots[18].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst \n connect issue_slots[18].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy \n connect issue_slots[18].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy \n connect issue_slots[18].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy \n connect issue_slots[18].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy \n connect issue_slots[18].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred \n connect issue_slots[18].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 \n connect issue_slots[18].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 \n connect issue_slots[18].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 \n connect issue_slots[18].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst \n connect issue_slots[18].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx \n connect issue_slots[18].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx \n connect issue_slots[18].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx \n connect issue_slots[18].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx \n connect issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec \n connect issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags \n connect issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt \n connect issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div \n connect issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma \n connect issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint \n connect issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint \n connect issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 \n connect issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 \n connect issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 \n connect issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 \n connect issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 \n connect issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen \n connect issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst \n connect issue_slots[18].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel \n connect issue_slots[18].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel \n connect issue_slots[18].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed \n connect issue_slots[18].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm \n connect issue_slots[18].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel \n connect issue_slots[18].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename \n connect issue_slots[18].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken \n connect issue_slots[18].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob \n connect issue_slots[18].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst \n connect issue_slots[18].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx \n connect issue_slots[18].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov \n connect issue_slots[18].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc \n connect issue_slots[18].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc \n connect issue_slots[18].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret \n connect issue_slots[18].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo \n connect issue_slots[18].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence \n connect issue_slots[18].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei \n connect issue_slots[18].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence \n connect issue_slots[18].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb \n connect issue_slots[18].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type \n connect issue_slots[18].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag \n connect issue_slots[18].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask \n connect issue_slots[18].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel \n connect issue_slots[18].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint \n connect issue_slots[18].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint \n connect issue_slots[18].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint \n connect issue_slots[18].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child \n connect issue_slots[18].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child \n connect issue_slots[18].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen \n connect issue_slots[18].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen \n connect issue_slots[18].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued \n connect issue_slots[18].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] \n connect issue_slots[18].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] \n connect issue_slots[18].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] \n connect issue_slots[18].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] \n connect issue_slots[18].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] \n connect issue_slots[18].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] \n connect issue_slots[18].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] \n connect issue_slots[18].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] \n connect issue_slots[18].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] \n connect issue_slots[18].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] \n connect issue_slots[18].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] \n connect issue_slots[18].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] \n connect issue_slots[18].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] \n connect issue_slots[18].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] \n connect issue_slots[18].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc \n connect issue_slots[18].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc \n connect issue_slots[18].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst \n connect issue_slots[18].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst \n connect issue_slots[18].wakeup_ports[1].valid, io.wakeup_ports[1].valid \n connect issue_slots[18].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy \n connect issue_slots[18].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask \n connect issue_slots[18].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable \n connect issue_slots[18].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc \n connect issue_slots[18].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc \n connect issue_slots[18].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if \n connect issue_slots[18].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if \n connect issue_slots[18].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if \n connect issue_slots[18].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if \n connect issue_slots[18].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if \n connect issue_slots[18].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ \n connect issue_slots[18].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm \n connect issue_slots[18].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val \n connect issue_slots[18].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op \n connect issue_slots[18].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw \n connect issue_slots[18].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en \n connect issue_slots[18].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype \n connect issue_slots[18].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype \n connect issue_slots[18].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype \n connect issue_slots[18].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 \n connect issue_slots[18].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 \n connect issue_slots[18].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 \n connect issue_slots[18].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst \n connect issue_slots[18].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 \n connect issue_slots[18].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd \n connect issue_slots[18].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit \n connect issue_slots[18].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique \n connect issue_slots[18].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq \n connect issue_slots[18].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq \n connect issue_slots[18].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed \n connect issue_slots[18].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size \n connect issue_slots[18].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd \n connect issue_slots[18].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause \n connect issue_slots[18].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception \n connect issue_slots[18].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst \n connect issue_slots[18].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy \n connect issue_slots[18].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy \n connect issue_slots[18].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy \n connect issue_slots[18].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy \n connect issue_slots[18].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred \n connect issue_slots[18].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 \n connect issue_slots[18].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 \n connect issue_slots[18].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 \n connect issue_slots[18].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst \n connect issue_slots[18].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx \n connect issue_slots[18].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx \n connect issue_slots[18].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx \n connect issue_slots[18].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx \n connect issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec \n connect issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags \n connect issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt \n connect issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div \n connect issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma \n connect issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint \n connect issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint \n connect issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 \n connect issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 \n connect issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 \n connect issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 \n connect issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 \n connect issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen \n connect issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst \n connect issue_slots[18].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel \n connect issue_slots[18].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel \n connect issue_slots[18].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed \n connect issue_slots[18].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm \n connect issue_slots[18].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel \n connect issue_slots[18].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename \n connect issue_slots[18].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken \n connect issue_slots[18].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob \n connect issue_slots[18].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst \n connect issue_slots[18].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx \n connect issue_slots[18].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov \n connect issue_slots[18].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc \n connect issue_slots[18].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc \n connect issue_slots[18].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret \n connect issue_slots[18].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo \n connect issue_slots[18].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence \n connect issue_slots[18].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei \n connect issue_slots[18].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence \n connect issue_slots[18].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb \n connect issue_slots[18].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type \n connect issue_slots[18].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag \n connect issue_slots[18].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask \n connect issue_slots[18].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel \n connect issue_slots[18].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint \n connect issue_slots[18].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint \n connect issue_slots[18].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint \n connect issue_slots[18].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child \n connect issue_slots[18].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child \n connect issue_slots[18].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen \n connect issue_slots[18].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen \n connect issue_slots[18].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued \n connect issue_slots[18].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] \n connect issue_slots[18].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] \n connect issue_slots[18].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] \n connect issue_slots[18].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] \n connect issue_slots[18].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] \n connect issue_slots[18].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] \n connect issue_slots[18].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] \n connect issue_slots[18].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] \n connect issue_slots[18].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] \n connect issue_slots[18].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] \n connect issue_slots[18].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] \n connect issue_slots[18].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] \n connect issue_slots[18].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] \n connect issue_slots[18].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] \n connect issue_slots[18].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc \n connect issue_slots[18].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc \n connect issue_slots[18].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst \n connect issue_slots[18].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst \n connect issue_slots[18].wakeup_ports[2].valid, io.wakeup_ports[2].valid \n connect issue_slots[18].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy \n connect issue_slots[18].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask \n connect issue_slots[18].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable \n connect issue_slots[18].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc \n connect issue_slots[18].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc \n connect issue_slots[18].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if \n connect issue_slots[18].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if \n connect issue_slots[18].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if \n connect issue_slots[18].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if \n connect issue_slots[18].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if \n connect issue_slots[18].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ \n connect issue_slots[18].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm \n connect issue_slots[18].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val \n connect issue_slots[18].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op \n connect issue_slots[18].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw \n connect issue_slots[18].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en \n connect issue_slots[18].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype \n connect issue_slots[18].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype \n connect issue_slots[18].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype \n connect issue_slots[18].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 \n connect issue_slots[18].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 \n connect issue_slots[18].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 \n connect issue_slots[18].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst \n connect issue_slots[18].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 \n connect issue_slots[18].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd \n connect issue_slots[18].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit \n connect issue_slots[18].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique \n connect issue_slots[18].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq \n connect issue_slots[18].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq \n connect issue_slots[18].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed \n connect issue_slots[18].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size \n connect issue_slots[18].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd \n connect issue_slots[18].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause \n connect issue_slots[18].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception \n connect issue_slots[18].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst \n connect issue_slots[18].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy \n connect issue_slots[18].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy \n connect issue_slots[18].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy \n connect issue_slots[18].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy \n connect issue_slots[18].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred \n connect issue_slots[18].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 \n connect issue_slots[18].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 \n connect issue_slots[18].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 \n connect issue_slots[18].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst \n connect issue_slots[18].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx \n connect issue_slots[18].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx \n connect issue_slots[18].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx \n connect issue_slots[18].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx \n connect issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec \n connect issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags \n connect issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt \n connect issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div \n connect issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma \n connect issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint \n connect issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint \n connect issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 \n connect issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 \n connect issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 \n connect issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 \n connect issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 \n connect issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen \n connect issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst \n connect issue_slots[18].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel \n connect issue_slots[18].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel \n connect issue_slots[18].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed \n connect issue_slots[18].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm \n connect issue_slots[18].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel \n connect issue_slots[18].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename \n connect issue_slots[18].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken \n connect issue_slots[18].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob \n connect issue_slots[18].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst \n connect issue_slots[18].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx \n connect issue_slots[18].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov \n connect issue_slots[18].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc \n connect issue_slots[18].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc \n connect issue_slots[18].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret \n connect issue_slots[18].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo \n connect issue_slots[18].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence \n connect issue_slots[18].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei \n connect issue_slots[18].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence \n connect issue_slots[18].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb \n connect issue_slots[18].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type \n connect issue_slots[18].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag \n connect issue_slots[18].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask \n connect issue_slots[18].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel \n connect issue_slots[18].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint \n connect issue_slots[18].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint \n connect issue_slots[18].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint \n connect issue_slots[18].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child \n connect issue_slots[18].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child \n connect issue_slots[18].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen \n connect issue_slots[18].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen \n connect issue_slots[18].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued \n connect issue_slots[18].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] \n connect issue_slots[18].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] \n connect issue_slots[18].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] \n connect issue_slots[18].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] \n connect issue_slots[18].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] \n connect issue_slots[18].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] \n connect issue_slots[18].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] \n connect issue_slots[18].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] \n connect issue_slots[18].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] \n connect issue_slots[18].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] \n connect issue_slots[18].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] \n connect issue_slots[18].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] \n connect issue_slots[18].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] \n connect issue_slots[18].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] \n connect issue_slots[18].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc \n connect issue_slots[18].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc \n connect issue_slots[18].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst \n connect issue_slots[18].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst \n connect issue_slots[18].wakeup_ports[3].valid, io.wakeup_ports[3].valid \n connect issue_slots[18].pred_wakeup_port.bits, io.pred_wakeup_port.bits \n connect issue_slots[18].pred_wakeup_port.valid, io.pred_wakeup_port.valid \n connect issue_slots[18].child_rebusys, io.child_rebusys \n connect issue_slots[18].squash_grant, io.squash_grant \n connect issue_slots[18].brupdate.b2.target_offset, io.brupdate.b2.target_offset \n connect issue_slots[18].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target \n connect issue_slots[18].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel \n connect issue_slots[18].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type \n connect issue_slots[18].brupdate.b2.taken, io.brupdate.b2.taken \n connect issue_slots[18].brupdate.b2.mispredict, io.brupdate.b2.mispredict \n connect issue_slots[18].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc \n connect issue_slots[18].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc \n connect issue_slots[18].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if \n connect issue_slots[18].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if \n connect issue_slots[18].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if \n connect issue_slots[18].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if \n connect issue_slots[18].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if \n connect issue_slots[18].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ \n connect issue_slots[18].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm \n connect issue_slots[18].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val \n connect issue_slots[18].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op \n connect issue_slots[18].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw \n connect issue_slots[18].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en \n connect issue_slots[18].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype \n connect issue_slots[18].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype \n connect issue_slots[18].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype \n connect issue_slots[18].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 \n connect issue_slots[18].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 \n connect issue_slots[18].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 \n connect issue_slots[18].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst \n connect issue_slots[18].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 \n connect issue_slots[18].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd \n connect issue_slots[18].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit \n connect issue_slots[18].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique \n connect issue_slots[18].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq \n connect issue_slots[18].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq \n connect issue_slots[18].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed \n connect issue_slots[18].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size \n connect issue_slots[18].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd \n connect issue_slots[18].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause \n connect issue_slots[18].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception \n connect issue_slots[18].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst \n connect issue_slots[18].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy \n connect issue_slots[18].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy \n connect issue_slots[18].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy \n connect issue_slots[18].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy \n connect issue_slots[18].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred \n connect issue_slots[18].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 \n connect issue_slots[18].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 \n connect issue_slots[18].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 \n connect issue_slots[18].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst \n connect issue_slots[18].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx \n connect issue_slots[18].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx \n connect issue_slots[18].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx \n connect issue_slots[18].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx \n connect issue_slots[18].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec \n connect issue_slots[18].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags \n connect issue_slots[18].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt \n connect issue_slots[18].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div \n connect issue_slots[18].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma \n connect issue_slots[18].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe \n connect issue_slots[18].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint \n connect issue_slots[18].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint \n connect issue_slots[18].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut \n connect issue_slots[18].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn \n connect issue_slots[18].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 \n connect issue_slots[18].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 \n connect issue_slots[18].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 \n connect issue_slots[18].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 \n connect issue_slots[18].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 \n connect issue_slots[18].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen \n connect issue_slots[18].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst \n connect issue_slots[18].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel \n connect issue_slots[18].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel \n connect issue_slots[18].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed \n connect issue_slots[18].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm \n connect issue_slots[18].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel \n connect issue_slots[18].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename \n connect issue_slots[18].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken \n connect issue_slots[18].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob \n connect issue_slots[18].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst \n connect issue_slots[18].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx \n connect issue_slots[18].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov \n connect issue_slots[18].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc \n connect issue_slots[18].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc \n connect issue_slots[18].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret \n connect issue_slots[18].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo \n connect issue_slots[18].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence \n connect issue_slots[18].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei \n connect issue_slots[18].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence \n connect issue_slots[18].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb \n connect issue_slots[18].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type \n connect issue_slots[18].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag \n connect issue_slots[18].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask \n connect issue_slots[18].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel \n connect issue_slots[18].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint \n connect issue_slots[18].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint \n connect issue_slots[18].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint \n connect issue_slots[18].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child \n connect issue_slots[18].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child \n connect issue_slots[18].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen \n connect issue_slots[18].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen \n connect issue_slots[18].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued \n connect issue_slots[18].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] \n connect issue_slots[18].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] \n connect issue_slots[18].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] \n connect issue_slots[18].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] \n connect issue_slots[18].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] \n connect issue_slots[18].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] \n connect issue_slots[18].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] \n connect issue_slots[18].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] \n connect issue_slots[18].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] \n connect issue_slots[18].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] \n connect issue_slots[18].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] \n connect issue_slots[18].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] \n connect issue_slots[18].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] \n connect issue_slots[18].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] \n connect issue_slots[18].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc \n connect issue_slots[18].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc \n connect issue_slots[18].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst \n connect issue_slots[18].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst \n connect issue_slots[18].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask \n connect issue_slots[18].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask \n connect issue_slots[18].kill, io.flush_pipeline \n connect issue_slots[19].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy \n connect issue_slots[19].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask \n connect issue_slots[19].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable \n connect issue_slots[19].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc \n connect issue_slots[19].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc \n connect issue_slots[19].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if \n connect issue_slots[19].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if \n connect issue_slots[19].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if \n connect issue_slots[19].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if \n connect issue_slots[19].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if \n connect issue_slots[19].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ \n connect issue_slots[19].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm \n connect issue_slots[19].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val \n connect issue_slots[19].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op \n connect issue_slots[19].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw \n connect issue_slots[19].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en \n connect issue_slots[19].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype \n connect issue_slots[19].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype \n connect issue_slots[19].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype \n connect issue_slots[19].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 \n connect issue_slots[19].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 \n connect issue_slots[19].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 \n connect issue_slots[19].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst \n connect issue_slots[19].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 \n connect issue_slots[19].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd \n connect issue_slots[19].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit \n connect issue_slots[19].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique \n connect issue_slots[19].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq \n connect issue_slots[19].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq \n connect issue_slots[19].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed \n connect issue_slots[19].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size \n connect issue_slots[19].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd \n connect issue_slots[19].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause \n connect issue_slots[19].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception \n connect issue_slots[19].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst \n connect issue_slots[19].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy \n connect issue_slots[19].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy \n connect issue_slots[19].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy \n connect issue_slots[19].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy \n connect issue_slots[19].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred \n connect issue_slots[19].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 \n connect issue_slots[19].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 \n connect issue_slots[19].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 \n connect issue_slots[19].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst \n connect issue_slots[19].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx \n connect issue_slots[19].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx \n connect issue_slots[19].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx \n connect issue_slots[19].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx \n connect issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec \n connect issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags \n connect issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt \n connect issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div \n connect issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma \n connect issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint \n connect issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint \n connect issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 \n connect issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 \n connect issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 \n connect issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 \n connect issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 \n connect issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen \n connect issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst \n connect issue_slots[19].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel \n connect issue_slots[19].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel \n connect issue_slots[19].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed \n connect issue_slots[19].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm \n connect issue_slots[19].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel \n connect issue_slots[19].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename \n connect issue_slots[19].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken \n connect issue_slots[19].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob \n connect issue_slots[19].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst \n connect issue_slots[19].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx \n connect issue_slots[19].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov \n connect issue_slots[19].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc \n connect issue_slots[19].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc \n connect issue_slots[19].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret \n connect issue_slots[19].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo \n connect issue_slots[19].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence \n connect issue_slots[19].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei \n connect issue_slots[19].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence \n connect issue_slots[19].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb \n connect issue_slots[19].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type \n connect issue_slots[19].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag \n connect issue_slots[19].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask \n connect issue_slots[19].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel \n connect issue_slots[19].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint \n connect issue_slots[19].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint \n connect issue_slots[19].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint \n connect issue_slots[19].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child \n connect issue_slots[19].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child \n connect issue_slots[19].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen \n connect issue_slots[19].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen \n connect issue_slots[19].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued \n connect issue_slots[19].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] \n connect issue_slots[19].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] \n connect issue_slots[19].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] \n connect issue_slots[19].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] \n connect issue_slots[19].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] \n connect issue_slots[19].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] \n connect issue_slots[19].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] \n connect issue_slots[19].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] \n connect issue_slots[19].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] \n connect issue_slots[19].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] \n connect issue_slots[19].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] \n connect issue_slots[19].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] \n connect issue_slots[19].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] \n connect issue_slots[19].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] \n connect issue_slots[19].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc \n connect issue_slots[19].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc \n connect issue_slots[19].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst \n connect issue_slots[19].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst \n connect issue_slots[19].wakeup_ports[0].valid, io.wakeup_ports[0].valid \n connect issue_slots[19].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy \n connect issue_slots[19].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask \n connect issue_slots[19].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable \n connect issue_slots[19].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc \n connect issue_slots[19].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc \n connect issue_slots[19].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if \n connect issue_slots[19].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if \n connect issue_slots[19].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if \n connect issue_slots[19].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if \n connect issue_slots[19].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if \n connect issue_slots[19].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ \n connect issue_slots[19].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm \n connect issue_slots[19].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val \n connect issue_slots[19].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op \n connect issue_slots[19].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw \n connect issue_slots[19].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en \n connect issue_slots[19].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype \n connect issue_slots[19].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype \n connect issue_slots[19].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype \n connect issue_slots[19].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 \n connect issue_slots[19].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 \n connect issue_slots[19].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 \n connect issue_slots[19].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst \n connect issue_slots[19].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 \n connect issue_slots[19].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd \n connect issue_slots[19].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit \n connect issue_slots[19].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique \n connect issue_slots[19].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq \n connect issue_slots[19].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq \n connect issue_slots[19].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed \n connect issue_slots[19].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size \n connect issue_slots[19].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd \n connect issue_slots[19].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause \n connect issue_slots[19].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception \n connect issue_slots[19].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst \n connect issue_slots[19].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy \n connect issue_slots[19].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy \n connect issue_slots[19].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy \n connect issue_slots[19].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy \n connect issue_slots[19].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred \n connect issue_slots[19].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 \n connect issue_slots[19].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 \n connect issue_slots[19].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 \n connect issue_slots[19].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst \n connect issue_slots[19].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx \n connect issue_slots[19].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx \n connect issue_slots[19].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx \n connect issue_slots[19].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx \n connect issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec \n connect issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags \n connect issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt \n connect issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div \n connect issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma \n connect issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint \n connect issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint \n connect issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 \n connect issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 \n connect issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 \n connect issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 \n connect issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 \n connect issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen \n connect issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst \n connect issue_slots[19].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel \n connect issue_slots[19].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel \n connect issue_slots[19].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed \n connect issue_slots[19].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm \n connect issue_slots[19].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel \n connect issue_slots[19].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename \n connect issue_slots[19].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken \n connect issue_slots[19].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob \n connect issue_slots[19].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst \n connect issue_slots[19].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx \n connect issue_slots[19].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov \n connect issue_slots[19].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc \n connect issue_slots[19].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc \n connect issue_slots[19].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret \n connect issue_slots[19].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo \n connect issue_slots[19].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence \n connect issue_slots[19].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei \n connect issue_slots[19].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence \n connect issue_slots[19].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb \n connect issue_slots[19].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type \n connect issue_slots[19].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag \n connect issue_slots[19].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask \n connect issue_slots[19].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel \n connect issue_slots[19].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint \n connect issue_slots[19].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint \n connect issue_slots[19].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint \n connect issue_slots[19].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child \n connect issue_slots[19].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child \n connect issue_slots[19].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen \n connect issue_slots[19].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen \n connect issue_slots[19].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued \n connect issue_slots[19].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] \n connect issue_slots[19].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] \n connect issue_slots[19].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] \n connect issue_slots[19].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] \n connect issue_slots[19].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] \n connect issue_slots[19].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] \n connect issue_slots[19].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] \n connect issue_slots[19].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] \n connect issue_slots[19].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] \n connect issue_slots[19].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] \n connect issue_slots[19].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] \n connect issue_slots[19].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] \n connect issue_slots[19].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] \n connect issue_slots[19].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] \n connect issue_slots[19].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc \n connect issue_slots[19].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc \n connect issue_slots[19].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst \n connect issue_slots[19].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst \n connect issue_slots[19].wakeup_ports[1].valid, io.wakeup_ports[1].valid \n connect issue_slots[19].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy \n connect issue_slots[19].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask \n connect issue_slots[19].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable \n connect issue_slots[19].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc \n connect issue_slots[19].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc \n connect issue_slots[19].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if \n connect issue_slots[19].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if \n connect issue_slots[19].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if \n connect issue_slots[19].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if \n connect issue_slots[19].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if \n connect issue_slots[19].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ \n connect issue_slots[19].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm \n connect issue_slots[19].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val \n connect issue_slots[19].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op \n connect issue_slots[19].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw \n connect issue_slots[19].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en \n connect issue_slots[19].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype \n connect issue_slots[19].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype \n connect issue_slots[19].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype \n connect issue_slots[19].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 \n connect issue_slots[19].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 \n connect issue_slots[19].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 \n connect issue_slots[19].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst \n connect issue_slots[19].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 \n connect issue_slots[19].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd \n connect issue_slots[19].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit \n connect issue_slots[19].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique \n connect issue_slots[19].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq \n connect issue_slots[19].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq \n connect issue_slots[19].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed \n connect issue_slots[19].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size \n connect issue_slots[19].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd \n connect issue_slots[19].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause \n connect issue_slots[19].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception \n connect issue_slots[19].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst \n connect issue_slots[19].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy \n connect issue_slots[19].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy \n connect issue_slots[19].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy \n connect issue_slots[19].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy \n connect issue_slots[19].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred \n connect issue_slots[19].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 \n connect issue_slots[19].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 \n connect issue_slots[19].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 \n connect issue_slots[19].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst \n connect issue_slots[19].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx \n connect issue_slots[19].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx \n connect issue_slots[19].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx \n connect issue_slots[19].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx \n connect issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec \n connect issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags \n connect issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt \n connect issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div \n connect issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma \n connect issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint \n connect issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint \n connect issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 \n connect issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 \n connect issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 \n connect issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 \n connect issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 \n connect issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen \n connect issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst \n connect issue_slots[19].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel \n connect issue_slots[19].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel \n connect issue_slots[19].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed \n connect issue_slots[19].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm \n connect issue_slots[19].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel \n connect issue_slots[19].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename \n connect issue_slots[19].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken \n connect issue_slots[19].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob \n connect issue_slots[19].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst \n connect issue_slots[19].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx \n connect issue_slots[19].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov \n connect issue_slots[19].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc \n connect issue_slots[19].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc \n connect issue_slots[19].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret \n connect issue_slots[19].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo \n connect issue_slots[19].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence \n connect issue_slots[19].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei \n connect issue_slots[19].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence \n connect issue_slots[19].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb \n connect issue_slots[19].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type \n connect issue_slots[19].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag \n connect issue_slots[19].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask \n connect issue_slots[19].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel \n connect issue_slots[19].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint \n connect issue_slots[19].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint \n connect issue_slots[19].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint \n connect issue_slots[19].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child \n connect issue_slots[19].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child \n connect issue_slots[19].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen \n connect issue_slots[19].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen \n connect issue_slots[19].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued \n connect issue_slots[19].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] \n connect issue_slots[19].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] \n connect issue_slots[19].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] \n connect issue_slots[19].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] \n connect issue_slots[19].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] \n connect issue_slots[19].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] \n connect issue_slots[19].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] \n connect issue_slots[19].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] \n connect issue_slots[19].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] \n connect issue_slots[19].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] \n connect issue_slots[19].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] \n connect issue_slots[19].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] \n connect issue_slots[19].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] \n connect issue_slots[19].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] \n connect issue_slots[19].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc \n connect issue_slots[19].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc \n connect issue_slots[19].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst \n connect issue_slots[19].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst \n connect issue_slots[19].wakeup_ports[2].valid, io.wakeup_ports[2].valid \n connect issue_slots[19].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy \n connect issue_slots[19].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask \n connect issue_slots[19].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable \n connect issue_slots[19].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc \n connect issue_slots[19].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc \n connect issue_slots[19].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if \n connect issue_slots[19].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if \n connect issue_slots[19].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if \n connect issue_slots[19].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if \n connect issue_slots[19].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if \n connect issue_slots[19].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ \n connect issue_slots[19].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm \n connect issue_slots[19].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val \n connect issue_slots[19].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op \n connect issue_slots[19].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw \n connect issue_slots[19].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en \n connect issue_slots[19].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype \n connect issue_slots[19].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype \n connect issue_slots[19].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype \n connect issue_slots[19].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 \n connect issue_slots[19].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 \n connect issue_slots[19].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 \n connect issue_slots[19].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst \n connect issue_slots[19].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 \n connect issue_slots[19].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd \n connect issue_slots[19].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit \n connect issue_slots[19].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique \n connect issue_slots[19].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq \n connect issue_slots[19].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq \n connect issue_slots[19].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed \n connect issue_slots[19].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size \n connect issue_slots[19].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd \n connect issue_slots[19].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause \n connect issue_slots[19].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception \n connect issue_slots[19].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst \n connect issue_slots[19].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy \n connect issue_slots[19].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy \n connect issue_slots[19].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy \n connect issue_slots[19].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy \n connect issue_slots[19].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred \n connect issue_slots[19].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 \n connect issue_slots[19].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 \n connect issue_slots[19].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 \n connect issue_slots[19].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst \n connect issue_slots[19].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx \n connect issue_slots[19].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx \n connect issue_slots[19].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx \n connect issue_slots[19].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx \n connect issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec \n connect issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags \n connect issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt \n connect issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div \n connect issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma \n connect issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe \n connect issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint \n connect issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint \n connect issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut \n connect issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn \n connect issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 \n connect issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 \n connect issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 \n connect issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 \n connect issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 \n connect issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen \n connect issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst \n connect issue_slots[19].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel \n connect issue_slots[19].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel \n connect issue_slots[19].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed \n connect issue_slots[19].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm \n connect issue_slots[19].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel \n connect issue_slots[19].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename \n connect issue_slots[19].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken \n connect issue_slots[19].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob \n connect issue_slots[19].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst \n connect issue_slots[19].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx \n connect issue_slots[19].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov \n connect issue_slots[19].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc \n connect issue_slots[19].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc \n connect issue_slots[19].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret \n connect issue_slots[19].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo \n connect issue_slots[19].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence \n connect issue_slots[19].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei \n connect issue_slots[19].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence \n connect issue_slots[19].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb \n connect issue_slots[19].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type \n connect issue_slots[19].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag \n connect issue_slots[19].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask \n connect issue_slots[19].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel \n connect issue_slots[19].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint \n connect issue_slots[19].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint \n connect issue_slots[19].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint \n connect issue_slots[19].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child \n connect issue_slots[19].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child \n connect issue_slots[19].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen \n connect issue_slots[19].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen \n connect issue_slots[19].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued \n connect issue_slots[19].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] \n connect issue_slots[19].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] \n connect issue_slots[19].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] \n connect issue_slots[19].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] \n connect issue_slots[19].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] \n connect issue_slots[19].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] \n connect issue_slots[19].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] \n connect issue_slots[19].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] \n connect issue_slots[19].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] \n connect issue_slots[19].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] \n connect issue_slots[19].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] \n connect issue_slots[19].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] \n connect issue_slots[19].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] \n connect issue_slots[19].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] \n connect issue_slots[19].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc \n connect issue_slots[19].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc \n connect issue_slots[19].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst \n connect issue_slots[19].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst \n connect issue_slots[19].wakeup_ports[3].valid, io.wakeup_ports[3].valid \n connect issue_slots[19].pred_wakeup_port.bits, io.pred_wakeup_port.bits \n connect issue_slots[19].pred_wakeup_port.valid, io.pred_wakeup_port.valid \n connect issue_slots[19].child_rebusys, io.child_rebusys \n connect issue_slots[19].squash_grant, io.squash_grant \n connect issue_slots[19].brupdate.b2.target_offset, io.brupdate.b2.target_offset \n connect issue_slots[19].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target \n connect issue_slots[19].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel \n connect issue_slots[19].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type \n connect issue_slots[19].brupdate.b2.taken, io.brupdate.b2.taken \n connect issue_slots[19].brupdate.b2.mispredict, io.brupdate.b2.mispredict \n connect issue_slots[19].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc \n connect issue_slots[19].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc \n connect issue_slots[19].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if \n connect issue_slots[19].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if \n connect issue_slots[19].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if \n connect issue_slots[19].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if \n connect issue_slots[19].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if \n connect issue_slots[19].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ \n connect issue_slots[19].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm \n connect issue_slots[19].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val \n connect issue_slots[19].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op \n connect issue_slots[19].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw \n connect issue_slots[19].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en \n connect issue_slots[19].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype \n connect issue_slots[19].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype \n connect issue_slots[19].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype \n connect issue_slots[19].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 \n connect issue_slots[19].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 \n connect issue_slots[19].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 \n connect issue_slots[19].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst \n connect issue_slots[19].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 \n connect issue_slots[19].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd \n connect issue_slots[19].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit \n connect issue_slots[19].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique \n connect issue_slots[19].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq \n connect issue_slots[19].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq \n connect issue_slots[19].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed \n connect issue_slots[19].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size \n connect issue_slots[19].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd \n connect issue_slots[19].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause \n connect issue_slots[19].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception \n connect issue_slots[19].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst \n connect issue_slots[19].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy \n connect issue_slots[19].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy \n connect issue_slots[19].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy \n connect issue_slots[19].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy \n connect issue_slots[19].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred \n connect issue_slots[19].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 \n connect issue_slots[19].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 \n connect issue_slots[19].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 \n connect issue_slots[19].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst \n connect issue_slots[19].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx \n connect issue_slots[19].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx \n connect issue_slots[19].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx \n connect issue_slots[19].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx \n connect issue_slots[19].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec \n connect issue_slots[19].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags \n connect issue_slots[19].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt \n connect issue_slots[19].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div \n connect issue_slots[19].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma \n connect issue_slots[19].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe \n connect issue_slots[19].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint \n connect issue_slots[19].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint \n connect issue_slots[19].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut \n connect issue_slots[19].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn \n connect issue_slots[19].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 \n connect issue_slots[19].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 \n connect issue_slots[19].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 \n connect issue_slots[19].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 \n connect issue_slots[19].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 \n connect issue_slots[19].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen \n connect issue_slots[19].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst \n connect issue_slots[19].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel \n connect issue_slots[19].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel \n connect issue_slots[19].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed \n connect issue_slots[19].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm \n connect issue_slots[19].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel \n connect issue_slots[19].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename \n connect issue_slots[19].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken \n connect issue_slots[19].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob \n connect issue_slots[19].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst \n connect issue_slots[19].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx \n connect issue_slots[19].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov \n connect issue_slots[19].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc \n connect issue_slots[19].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc \n connect issue_slots[19].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret \n connect issue_slots[19].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo \n connect issue_slots[19].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence \n connect issue_slots[19].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei \n connect issue_slots[19].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence \n connect issue_slots[19].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb \n connect issue_slots[19].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type \n connect issue_slots[19].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag \n connect issue_slots[19].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask \n connect issue_slots[19].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel \n connect issue_slots[19].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint \n connect issue_slots[19].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint \n connect issue_slots[19].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint \n connect issue_slots[19].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child \n connect issue_slots[19].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child \n connect issue_slots[19].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen \n connect issue_slots[19].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen \n connect issue_slots[19].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued \n connect issue_slots[19].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] \n connect issue_slots[19].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] \n connect issue_slots[19].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] \n connect issue_slots[19].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] \n connect issue_slots[19].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] \n connect issue_slots[19].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] \n connect issue_slots[19].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] \n connect issue_slots[19].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] \n connect issue_slots[19].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] \n connect issue_slots[19].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] \n connect issue_slots[19].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] \n connect issue_slots[19].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] \n connect issue_slots[19].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] \n connect issue_slots[19].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] \n connect issue_slots[19].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc \n connect issue_slots[19].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc \n connect issue_slots[19].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst \n connect issue_slots[19].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst \n connect issue_slots[19].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask \n connect issue_slots[19].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask \n connect issue_slots[19].kill, io.flush_pipeline \n connect io.iss_uops[0].valid, UInt<1>(0h0) \n connect io.iss_uops[1].valid, UInt<1>(0h0) \n node _T_120 = add(issue_slots[0].grant, issue_slots[1].grant) \n node _T_121 = bits(_T_120, 1, 0) \n node _T_122 = add(issue_slots[3].grant, issue_slots[4].grant) \n node _T_123 = bits(_T_122, 1, 0) \n node _T_124 = add(issue_slots[2].grant, _T_123) \n node _T_125 = bits(_T_124, 1, 0) \n node _T_126 = add(_T_121, _T_125) \n node _T_127 = bits(_T_126, 2, 0) \n node _T_128 = add(issue_slots[5].grant, issue_slots[6].grant) \n node _T_129 = bits(_T_128, 1, 0) \n node _T_130 = add(issue_slots[8].grant, issue_slots[9].grant) \n node _T_131 = bits(_T_130, 1, 0) \n node _T_132 = add(issue_slots[7].grant, _T_131) \n node _T_133 = bits(_T_132, 1, 0) \n node _T_134 = add(_T_129, _T_133) \n node _T_135 = bits(_T_134, 2, 0) \n node _T_136 = add(_T_127, _T_135) \n node _T_137 = bits(_T_136, 3, 0) \n node _T_138 = add(issue_slots[10].grant, issue_slots[11].grant) \n node _T_139 = bits(_T_138, 1, 0) \n node _T_140 = add(issue_slots[13].grant, issue_slots[14].grant) \n node _T_141 = bits(_T_140, 1, 0) \n node _T_142 = add(issue_slots[12].grant, _T_141) \n node _T_143 = bits(_T_142, 1, 0) \n node _T_144 = add(_T_139, _T_143) \n node _T_145 = bits(_T_144, 2, 0) \n node _T_146 = add(issue_slots[15].grant, issue_slots[16].grant) \n node _T_147 = bits(_T_146, 1, 0) \n node _T_148 = add(issue_slots[18].grant, issue_slots[19].grant) \n node _T_149 = bits(_T_148, 1, 0) \n node _T_150 = add(issue_slots[17].grant, _T_149) \n node _T_151 = bits(_T_150, 1, 0) \n node _T_152 = add(_T_147, _T_151) \n node _T_153 = bits(_T_152, 2, 0) \n node _T_154 = add(_T_145, _T_153) \n node _T_155 = bits(_T_154, 3, 0) \n node _T_156 = add(_T_137, _T_155) \n node _T_157 = bits(_T_156, 4, 0) \n node _T_158 = leq(_T_157, UInt<2>(0h2)) \n node _T_159 = asUInt(reset) \n node _T_160 = eq(_T_159, UInt<1>(0h0)) \n when _T_160 : \n node _T_161 = eq(_T_158, UInt<1>(0h0)) \n when _T_161 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: [issue] window giving out too many grants.\\n at issue-unit-age-ordered.scala:141 assert (PopCount(issue_slots.map(s => s.grant)) <= issueWidth.U, \\\"[issue] window giving out too many grants.\\\")\\n\") : printf \n assert(clock, _T_158, UInt<1>(0h1), \"\") : assert \n node vacants_0 = eq(issue_slots[0].valid, UInt<1>(0h0)) \n node vacants_1 = eq(issue_slots[1].valid, UInt<1>(0h0)) \n node vacants_2 = eq(issue_slots[2].valid, UInt<1>(0h0)) \n node vacants_3 = eq(issue_slots[3].valid, UInt<1>(0h0)) \n node vacants_4 = eq(issue_slots[4].valid, UInt<1>(0h0)) \n node vacants_5 = eq(issue_slots[5].valid, UInt<1>(0h0)) \n node vacants_6 = eq(issue_slots[6].valid, UInt<1>(0h0)) \n node vacants_7 = eq(issue_slots[7].valid, UInt<1>(0h0)) \n node vacants_8 = eq(issue_slots[8].valid, UInt<1>(0h0)) \n node vacants_9 = eq(issue_slots[9].valid, UInt<1>(0h0)) \n node vacants_10 = eq(issue_slots[10].valid, UInt<1>(0h0)) \n node vacants_11 = eq(issue_slots[11].valid, UInt<1>(0h0)) \n node vacants_12 = eq(issue_slots[12].valid, UInt<1>(0h0)) \n node vacants_13 = eq(issue_slots[13].valid, UInt<1>(0h0)) \n node vacants_14 = eq(issue_slots[14].valid, UInt<1>(0h0)) \n node vacants_15 = eq(issue_slots[15].valid, UInt<1>(0h0)) \n node vacants_16 = eq(issue_slots[16].valid, UInt<1>(0h0)) \n node vacants_17 = eq(issue_slots[17].valid, UInt<1>(0h0)) \n node vacants_18 = eq(issue_slots[18].valid, UInt<1>(0h0)) \n node vacants_19 = eq(issue_slots[19].valid, UInt<1>(0h0)) \n node vacants_20 = eq(io.dis_uops[0].valid, UInt<1>(0h0)) \n node vacants_21 = eq(io.dis_uops[1].valid, UInt<1>(0h0)) \n wire shamts_oh : UInt<2>[22] \n connect shamts_oh[0], UInt<1>(0h0) \n wire shamts_oh_1_next : UInt<2> \n connect shamts_oh_1_next, shamts_oh[0] \n node _shamts_oh_1_T = eq(shamts_oh[0], UInt<1>(0h0)) \n node _shamts_oh_1_T_1 = and(_shamts_oh_1_T, vacants_0) \n when _shamts_oh_1_T_1 : \n connect shamts_oh_1_next, UInt<1>(0h1) \n else :\n\n node _shamts_oh_1_T_2 = bits(shamts_oh[0], 1, 1) \n node _shamts_oh_1_T_3 = eq(_shamts_oh_1_T_2, UInt<1>(0h0)) \n node _shamts_oh_1_T_4 = and(_shamts_oh_1_T_3, vacants_0) \n when _shamts_oh_1_T_4 : \n node _shamts_oh_1_next_T = dshl(shamts_oh[0], UInt<1>(0h1)) \n connect shamts_oh_1_next, _shamts_oh_1_next_T \n connect shamts_oh[1], shamts_oh_1_next \n wire shamts_oh_2_next : UInt<2> \n connect shamts_oh_2_next, shamts_oh[1] \n node _shamts_oh_2_T = eq(shamts_oh[1], UInt<1>(0h0)) \n node _shamts_oh_2_T_1 = and(_shamts_oh_2_T, vacants_1) \n when _shamts_oh_2_T_1 : \n connect shamts_oh_2_next, UInt<1>(0h1) \n else :\n\n node _shamts_oh_2_T_2 = bits(shamts_oh[1], 1, 1) \n node _shamts_oh_2_T_3 = eq(_shamts_oh_2_T_2, UInt<1>(0h0)) \n node _shamts_oh_2_T_4 = and(_shamts_oh_2_T_3, vacants_1) \n when _shamts_oh_2_T_4 : \n node _shamts_oh_2_next_T = dshl(shamts_oh[1], UInt<1>(0h1)) \n connect shamts_oh_2_next, _shamts_oh_2_next_T \n connect shamts_oh[2], shamts_oh_2_next \n wire shamts_oh_3_next : UInt<2> \n connect shamts_oh_3_next, shamts_oh[2] \n node _shamts_oh_3_T = eq(shamts_oh[2], UInt<1>(0h0)) \n node _shamts_oh_3_T_1 = and(_shamts_oh_3_T, vacants_2) \n when _shamts_oh_3_T_1 : \n connect shamts_oh_3_next, UInt<1>(0h1) \n else :\n\n node _shamts_oh_3_T_2 = bits(shamts_oh[2], 1, 1) \n node _shamts_oh_3_T_3 = eq(_shamts_oh_3_T_2, UInt<1>(0h0)) \n node _shamts_oh_3_T_4 = and(_shamts_oh_3_T_3, vacants_2) \n when _shamts_oh_3_T_4 : \n node _shamts_oh_3_next_T = dshl(shamts_oh[2], UInt<1>(0h1)) \n connect shamts_oh_3_next, _shamts_oh_3_next_T \n connect shamts_oh[3], shamts_oh_3_next \n wire shamts_oh_4_next : UInt<2> \n connect shamts_oh_4_next, shamts_oh[3] \n node _shamts_oh_4_T = eq(shamts_oh[3], UInt<1>(0h0)) \n node _shamts_oh_4_T_1 = and(_shamts_oh_4_T, vacants_3) \n when _shamts_oh_4_T_1 : \n connect shamts_oh_4_next, UInt<1>(0h1) \n else :\n\n node _shamts_oh_4_T_2 = bits(shamts_oh[3], 1, 1) \n node _shamts_oh_4_T_3 = eq(_shamts_oh_4_T_2, UInt<1>(0h0)) \n node _shamts_oh_4_T_4 = and(_shamts_oh_4_T_3, vacants_3) \n when _shamts_oh_4_T_4 : \n node _shamts_oh_4_next_T = dshl(shamts_oh[3], UInt<1>(0h1)) \n connect shamts_oh_4_next, _shamts_oh_4_next_T \n connect shamts_oh[4], shamts_oh_4_next \n wire shamts_oh_5_next : UInt<2> \n connect shamts_oh_5_next, shamts_oh[4] \n node _shamts_oh_5_T = eq(shamts_oh[4], UInt<1>(0h0)) \n node _shamts_oh_5_T_1 = and(_shamts_oh_5_T, vacants_4) \n when _shamts_oh_5_T_1 : \n connect shamts_oh_5_next, UInt<1>(0h1) \n else :\n\n node _shamts_oh_5_T_2 = bits(shamts_oh[4], 1, 1) \n node _shamts_oh_5_T_3 = eq(_shamts_oh_5_T_2, UInt<1>(0h0)) \n node _shamts_oh_5_T_4 = and(_shamts_oh_5_T_3, vacants_4) \n when _shamts_oh_5_T_4 : \n node _shamts_oh_5_next_T = dshl(shamts_oh[4], UInt<1>(0h1)) \n connect shamts_oh_5_next, _shamts_oh_5_next_T \n connect shamts_oh[5], shamts_oh_5_next \n wire shamts_oh_6_next : UInt<2> \n connect shamts_oh_6_next, shamts_oh[5] \n node _shamts_oh_6_T = eq(shamts_oh[5], UInt<1>(0h0)) \n node _shamts_oh_6_T_1 = and(_shamts_oh_6_T, vacants_5) \n when _shamts_oh_6_T_1 : \n connect shamts_oh_6_next, UInt<1>(0h1) \n else :\n\n node _shamts_oh_6_T_2 = bits(shamts_oh[5], 1, 1) \n node _shamts_oh_6_T_3 = eq(_shamts_oh_6_T_2, UInt<1>(0h0)) \n node _shamts_oh_6_T_4 = and(_shamts_oh_6_T_3, vacants_5) \n when _shamts_oh_6_T_4 : \n node _shamts_oh_6_next_T = dshl(shamts_oh[5], UInt<1>(0h1)) \n connect shamts_oh_6_next, _shamts_oh_6_next_T \n connect shamts_oh[6], shamts_oh_6_next \n wire shamts_oh_7_next : UInt<2> \n connect shamts_oh_7_next, shamts_oh[6] \n node _shamts_oh_7_T = eq(shamts_oh[6], UInt<1>(0h0)) \n node _shamts_oh_7_T_1 = and(_shamts_oh_7_T, vacants_6) \n when _shamts_oh_7_T_1 : \n connect shamts_oh_7_next, UInt<1>(0h1) \n else :\n\n node _shamts_oh_7_T_2 = bits(shamts_oh[6], 1, 1) \n node _shamts_oh_7_T_3 = eq(_shamts_oh_7_T_2, UInt<1>(0h0)) \n node _shamts_oh_7_T_4 = and(_shamts_oh_7_T_3, vacants_6) \n when _shamts_oh_7_T_4 : \n node _shamts_oh_7_next_T = dshl(shamts_oh[6], UInt<1>(0h1)) \n connect shamts_oh_7_next, _shamts_oh_7_next_T \n connect shamts_oh[7], shamts_oh_7_next \n wire shamts_oh_8_next : UInt<2> \n connect shamts_oh_8_next, shamts_oh[7] \n node _shamts_oh_8_T = eq(shamts_oh[7], UInt<1>(0h0)) \n node _shamts_oh_8_T_1 = and(_shamts_oh_8_T, vacants_7) \n when _shamts_oh_8_T_1 : \n connect shamts_oh_8_next, UInt<1>(0h1) \n else :\n\n node _shamts_oh_8_T_2 = bits(shamts_oh[7], 1, 1) \n node _shamts_oh_8_T_3 = eq(_shamts_oh_8_T_2, UInt<1>(0h0)) \n node _shamts_oh_8_T_4 = and(_shamts_oh_8_T_3, vacants_7) \n when _shamts_oh_8_T_4 : \n node _shamts_oh_8_next_T = dshl(shamts_oh[7], UInt<1>(0h1)) \n connect shamts_oh_8_next, _shamts_oh_8_next_T \n connect shamts_oh[8], shamts_oh_8_next \n wire shamts_oh_9_next : UInt<2> \n connect shamts_oh_9_next, shamts_oh[8] \n node _shamts_oh_9_T = eq(shamts_oh[8], UInt<1>(0h0)) \n node _shamts_oh_9_T_1 = and(_shamts_oh_9_T, vacants_8) \n when _shamts_oh_9_T_1 : \n connect shamts_oh_9_next, UInt<1>(0h1) \n else :\n\n node _shamts_oh_9_T_2 = bits(shamts_oh[8], 1, 1) \n node _shamts_oh_9_T_3 = eq(_shamts_oh_9_T_2, UInt<1>(0h0)) \n node _shamts_oh_9_T_4 = and(_shamts_oh_9_T_3, vacants_8) \n when _shamts_oh_9_T_4 : \n node _shamts_oh_9_next_T = dshl(shamts_oh[8], UInt<1>(0h1)) \n connect shamts_oh_9_next, _shamts_oh_9_next_T \n connect shamts_oh[9], shamts_oh_9_next \n wire shamts_oh_10_next : UInt<2> \n connect shamts_oh_10_next, shamts_oh[9] \n node _shamts_oh_10_T = eq(shamts_oh[9], UInt<1>(0h0)) \n node _shamts_oh_10_T_1 = and(_shamts_oh_10_T, vacants_9) \n when _shamts_oh_10_T_1 : \n connect shamts_oh_10_next, UInt<1>(0h1) \n else :\n\n node _shamts_oh_10_T_2 = bits(shamts_oh[9], 1, 1) \n node _shamts_oh_10_T_3 = eq(_shamts_oh_10_T_2, UInt<1>(0h0)) \n node _shamts_oh_10_T_4 = and(_shamts_oh_10_T_3, vacants_9) \n when _shamts_oh_10_T_4 : \n node _shamts_oh_10_next_T = dshl(shamts_oh[9], UInt<1>(0h1)) \n connect shamts_oh_10_next, _shamts_oh_10_next_T \n connect shamts_oh[10], shamts_oh_10_next \n wire shamts_oh_11_next : UInt<2> \n connect shamts_oh_11_next, shamts_oh[10] \n node _shamts_oh_11_T = eq(shamts_oh[10], UInt<1>(0h0)) \n node _shamts_oh_11_T_1 = and(_shamts_oh_11_T, vacants_10) \n when _shamts_oh_11_T_1 : \n connect shamts_oh_11_next, UInt<1>(0h1) \n else :\n\n node _shamts_oh_11_T_2 = bits(shamts_oh[10], 1, 1) \n node _shamts_oh_11_T_3 = eq(_shamts_oh_11_T_2, UInt<1>(0h0)) \n node _shamts_oh_11_T_4 = and(_shamts_oh_11_T_3, vacants_10) \n when _shamts_oh_11_T_4 : \n node _shamts_oh_11_next_T = dshl(shamts_oh[10], UInt<1>(0h1)) \n connect shamts_oh_11_next, _shamts_oh_11_next_T \n connect shamts_oh[11], shamts_oh_11_next \n wire shamts_oh_12_next : UInt<2> \n connect shamts_oh_12_next, shamts_oh[11] \n node _shamts_oh_12_T = eq(shamts_oh[11], UInt<1>(0h0)) \n node _shamts_oh_12_T_1 = and(_shamts_oh_12_T, vacants_11) \n when _shamts_oh_12_T_1 : \n connect shamts_oh_12_next, UInt<1>(0h1) \n else :\n\n node _shamts_oh_12_T_2 = bits(shamts_oh[11], 1, 1) \n node _shamts_oh_12_T_3 = eq(_shamts_oh_12_T_2, UInt<1>(0h0)) \n node _shamts_oh_12_T_4 = and(_shamts_oh_12_T_3, vacants_11) \n when _shamts_oh_12_T_4 : \n node _shamts_oh_12_next_T = dshl(shamts_oh[11], UInt<1>(0h1)) \n connect shamts_oh_12_next, _shamts_oh_12_next_T \n connect shamts_oh[12], shamts_oh_12_next \n wire shamts_oh_13_next : UInt<2> \n connect shamts_oh_13_next, shamts_oh[12] \n node _shamts_oh_13_T = eq(shamts_oh[12], UInt<1>(0h0)) \n node _shamts_oh_13_T_1 = and(_shamts_oh_13_T, vacants_12) \n when _shamts_oh_13_T_1 : \n connect shamts_oh_13_next, UInt<1>(0h1) \n else :\n\n node _shamts_oh_13_T_2 = bits(shamts_oh[12], 1, 1) \n node _shamts_oh_13_T_3 = eq(_shamts_oh_13_T_2, UInt<1>(0h0)) \n node _shamts_oh_13_T_4 = and(_shamts_oh_13_T_3, vacants_12) \n when _shamts_oh_13_T_4 : \n node _shamts_oh_13_next_T = dshl(shamts_oh[12], UInt<1>(0h1)) \n connect shamts_oh_13_next, _shamts_oh_13_next_T \n connect shamts_oh[13], shamts_oh_13_next \n wire shamts_oh_14_next : UInt<2> \n connect shamts_oh_14_next, shamts_oh[13] \n node _shamts_oh_14_T = eq(shamts_oh[13], UInt<1>(0h0)) \n node _shamts_oh_14_T_1 = and(_shamts_oh_14_T, vacants_13) \n when _shamts_oh_14_T_1 : \n connect shamts_oh_14_next, UInt<1>(0h1) \n else :\n\n node _shamts_oh_14_T_2 = bits(shamts_oh[13], 1, 1) \n node _shamts_oh_14_T_3 = eq(_shamts_oh_14_T_2, UInt<1>(0h0)) \n node _shamts_oh_14_T_4 = and(_shamts_oh_14_T_3, vacants_13) \n when _shamts_oh_14_T_4 : \n node _shamts_oh_14_next_T = dshl(shamts_oh[13], UInt<1>(0h1)) \n connect shamts_oh_14_next, _shamts_oh_14_next_T \n connect shamts_oh[14], shamts_oh_14_next \n wire shamts_oh_15_next : UInt<2> \n connect shamts_oh_15_next, shamts_oh[14] \n node _shamts_oh_15_T = eq(shamts_oh[14], UInt<1>(0h0)) \n node _shamts_oh_15_T_1 = and(_shamts_oh_15_T, vacants_14) \n when _shamts_oh_15_T_1 : \n connect shamts_oh_15_next, UInt<1>(0h1) \n else :\n\n node _shamts_oh_15_T_2 = bits(shamts_oh[14], 1, 1) \n node _shamts_oh_15_T_3 = eq(_shamts_oh_15_T_2, UInt<1>(0h0)) \n node _shamts_oh_15_T_4 = and(_shamts_oh_15_T_3, vacants_14) \n when _shamts_oh_15_T_4 : \n node _shamts_oh_15_next_T = dshl(shamts_oh[14], UInt<1>(0h1)) \n connect shamts_oh_15_next, _shamts_oh_15_next_T \n connect shamts_oh[15], shamts_oh_15_next \n wire shamts_oh_16_next : UInt<2> \n connect shamts_oh_16_next, shamts_oh[15] \n node _shamts_oh_16_T = eq(shamts_oh[15], UInt<1>(0h0)) \n node _shamts_oh_16_T_1 = and(_shamts_oh_16_T, vacants_15) \n when _shamts_oh_16_T_1 : \n connect shamts_oh_16_next, UInt<1>(0h1) \n else :\n\n node _shamts_oh_16_T_2 = bits(shamts_oh[15], 1, 1) \n node _shamts_oh_16_T_3 = eq(_shamts_oh_16_T_2, UInt<1>(0h0)) \n node _shamts_oh_16_T_4 = and(_shamts_oh_16_T_3, vacants_15) \n when _shamts_oh_16_T_4 : \n node _shamts_oh_16_next_T = dshl(shamts_oh[15], UInt<1>(0h1)) \n connect shamts_oh_16_next, _shamts_oh_16_next_T \n connect shamts_oh[16], shamts_oh_16_next \n wire shamts_oh_17_next : UInt<2> \n connect shamts_oh_17_next, shamts_oh[16] \n node _shamts_oh_17_T = eq(shamts_oh[16], UInt<1>(0h0)) \n node _shamts_oh_17_T_1 = and(_shamts_oh_17_T, vacants_16) \n when _shamts_oh_17_T_1 : \n connect shamts_oh_17_next, UInt<1>(0h1) \n else :\n\n node _shamts_oh_17_T_2 = bits(shamts_oh[16], 1, 1) \n node _shamts_oh_17_T_3 = eq(_shamts_oh_17_T_2, UInt<1>(0h0)) \n node _shamts_oh_17_T_4 = and(_shamts_oh_17_T_3, vacants_16) \n when _shamts_oh_17_T_4 : \n node _shamts_oh_17_next_T = dshl(shamts_oh[16], UInt<1>(0h1)) \n connect shamts_oh_17_next, _shamts_oh_17_next_T \n connect shamts_oh[17], shamts_oh_17_next \n wire shamts_oh_18_next : UInt<2> \n connect shamts_oh_18_next, shamts_oh[17] \n node _shamts_oh_18_T = eq(shamts_oh[17], UInt<1>(0h0)) \n node _shamts_oh_18_T_1 = and(_shamts_oh_18_T, vacants_17) \n when _shamts_oh_18_T_1 : \n connect shamts_oh_18_next, UInt<1>(0h1) \n else :\n\n node _shamts_oh_18_T_2 = bits(shamts_oh[17], 1, 1) \n node _shamts_oh_18_T_3 = eq(_shamts_oh_18_T_2, UInt<1>(0h0)) \n node _shamts_oh_18_T_4 = and(_shamts_oh_18_T_3, vacants_17) \n when _shamts_oh_18_T_4 : \n node _shamts_oh_18_next_T = dshl(shamts_oh[17], UInt<1>(0h1)) \n connect shamts_oh_18_next, _shamts_oh_18_next_T \n connect shamts_oh[18], shamts_oh_18_next \n wire shamts_oh_19_next : UInt<2> \n connect shamts_oh_19_next, shamts_oh[18] \n node _shamts_oh_19_T = eq(shamts_oh[18], UInt<1>(0h0)) \n node _shamts_oh_19_T_1 = and(_shamts_oh_19_T, vacants_18) \n when _shamts_oh_19_T_1 : \n connect shamts_oh_19_next, UInt<1>(0h1) \n else :\n\n node _shamts_oh_19_T_2 = bits(shamts_oh[18], 1, 1) \n node _shamts_oh_19_T_3 = eq(_shamts_oh_19_T_2, UInt<1>(0h0)) \n node _shamts_oh_19_T_4 = and(_shamts_oh_19_T_3, vacants_18) \n when _shamts_oh_19_T_4 : \n node _shamts_oh_19_next_T = dshl(shamts_oh[18], UInt<1>(0h1)) \n connect shamts_oh_19_next, _shamts_oh_19_next_T \n connect shamts_oh[19], shamts_oh_19_next \n wire shamts_oh_20_next : UInt<2> \n connect shamts_oh_20_next, shamts_oh[19] \n node _shamts_oh_20_T = eq(shamts_oh[19], UInt<1>(0h0)) \n node _shamts_oh_20_T_1 = and(_shamts_oh_20_T, vacants_19) \n when _shamts_oh_20_T_1 : \n connect shamts_oh_20_next, UInt<1>(0h1) \n else :\n\n node _shamts_oh_20_T_2 = bits(shamts_oh[19], 1, 1) \n node _shamts_oh_20_T_3 = eq(_shamts_oh_20_T_2, UInt<1>(0h0)) \n node _shamts_oh_20_T_4 = and(_shamts_oh_20_T_3, vacants_19) \n when _shamts_oh_20_T_4 : \n node _shamts_oh_20_next_T = dshl(shamts_oh[19], UInt<1>(0h1)) \n connect shamts_oh_20_next, _shamts_oh_20_next_T \n connect shamts_oh[20], shamts_oh_20_next \n wire shamts_oh_21_next : UInt<2> \n connect shamts_oh_21_next, shamts_oh[20] \n node _shamts_oh_21_T = eq(shamts_oh[20], UInt<1>(0h0)) \n node _shamts_oh_21_T_1 = and(_shamts_oh_21_T, vacants_20) \n when _shamts_oh_21_T_1 : \n connect shamts_oh_21_next, UInt<1>(0h1) \n else :\n\n node _shamts_oh_21_T_2 = bits(shamts_oh[20], 1, 1) \n node _shamts_oh_21_T_3 = eq(_shamts_oh_21_T_2, UInt<1>(0h0)) \n node _shamts_oh_21_T_4 = and(_shamts_oh_21_T_3, vacants_20) \n when _shamts_oh_21_T_4 : \n node _shamts_oh_21_next_T = dshl(shamts_oh[20], UInt<1>(0h1)) \n connect shamts_oh_21_next, _shamts_oh_21_next_T \n connect shamts_oh[21], shamts_oh_21_next \n node _will_be_valid_T = eq(_WIRE.exception, UInt<1>(0h0)) \n node _will_be_valid_T_1 = and(io.dis_uops[0].valid, _will_be_valid_T) \n node _will_be_valid_T_2 = eq(_WIRE.is_fence, UInt<1>(0h0)) \n node _will_be_valid_T_3 = and(_will_be_valid_T_1, _will_be_valid_T_2) \n node _will_be_valid_T_4 = eq(_WIRE.is_fencei, UInt<1>(0h0)) \n node will_be_valid_20 = and(_will_be_valid_T_3, _will_be_valid_T_4) \n node _will_be_valid_T_5 = eq(_WIRE_1.exception, UInt<1>(0h0)) \n node _will_be_valid_T_6 = and(io.dis_uops[1].valid, _will_be_valid_T_5) \n node _will_be_valid_T_7 = eq(_WIRE_1.is_fence, UInt<1>(0h0)) \n node _will_be_valid_T_8 = and(_will_be_valid_T_6, _will_be_valid_T_7) \n node _will_be_valid_T_9 = eq(_WIRE_1.is_fencei, UInt<1>(0h0)) \n node will_be_valid_21 = and(_will_be_valid_T_8, _will_be_valid_T_9) \n connect issue_slots[0].in_uop.valid, UInt<1>(0h0) \n connect issue_slots[0].in_uop.bits.debug_tsrc, issue_slots[1].out_uop.debug_tsrc \n connect issue_slots[0].in_uop.bits.debug_fsrc, issue_slots[1].out_uop.debug_fsrc \n connect issue_slots[0].in_uop.bits.bp_xcpt_if, issue_slots[1].out_uop.bp_xcpt_if \n connect issue_slots[0].in_uop.bits.bp_debug_if, issue_slots[1].out_uop.bp_debug_if \n connect issue_slots[0].in_uop.bits.xcpt_ma_if, issue_slots[1].out_uop.xcpt_ma_if \n connect issue_slots[0].in_uop.bits.xcpt_ae_if, issue_slots[1].out_uop.xcpt_ae_if \n connect issue_slots[0].in_uop.bits.xcpt_pf_if, issue_slots[1].out_uop.xcpt_pf_if \n connect issue_slots[0].in_uop.bits.fp_typ, issue_slots[1].out_uop.fp_typ \n connect issue_slots[0].in_uop.bits.fp_rm, issue_slots[1].out_uop.fp_rm \n connect issue_slots[0].in_uop.bits.fp_val, issue_slots[1].out_uop.fp_val \n connect issue_slots[0].in_uop.bits.fcn_op, issue_slots[1].out_uop.fcn_op \n connect issue_slots[0].in_uop.bits.fcn_dw, issue_slots[1].out_uop.fcn_dw \n connect issue_slots[0].in_uop.bits.frs3_en, issue_slots[1].out_uop.frs3_en \n connect issue_slots[0].in_uop.bits.lrs2_rtype, issue_slots[1].out_uop.lrs2_rtype \n connect issue_slots[0].in_uop.bits.lrs1_rtype, issue_slots[1].out_uop.lrs1_rtype \n connect issue_slots[0].in_uop.bits.dst_rtype, issue_slots[1].out_uop.dst_rtype \n connect issue_slots[0].in_uop.bits.lrs3, issue_slots[1].out_uop.lrs3 \n connect issue_slots[0].in_uop.bits.lrs2, issue_slots[1].out_uop.lrs2 \n connect issue_slots[0].in_uop.bits.lrs1, issue_slots[1].out_uop.lrs1 \n connect issue_slots[0].in_uop.bits.ldst, issue_slots[1].out_uop.ldst \n connect issue_slots[0].in_uop.bits.ldst_is_rs1, issue_slots[1].out_uop.ldst_is_rs1 \n connect issue_slots[0].in_uop.bits.csr_cmd, issue_slots[1].out_uop.csr_cmd \n connect issue_slots[0].in_uop.bits.flush_on_commit, issue_slots[1].out_uop.flush_on_commit \n connect issue_slots[0].in_uop.bits.is_unique, issue_slots[1].out_uop.is_unique \n connect issue_slots[0].in_uop.bits.uses_stq, issue_slots[1].out_uop.uses_stq \n connect issue_slots[0].in_uop.bits.uses_ldq, issue_slots[1].out_uop.uses_ldq \n connect issue_slots[0].in_uop.bits.mem_signed, issue_slots[1].out_uop.mem_signed \n connect issue_slots[0].in_uop.bits.mem_size, issue_slots[1].out_uop.mem_size \n connect issue_slots[0].in_uop.bits.mem_cmd, issue_slots[1].out_uop.mem_cmd \n connect issue_slots[0].in_uop.bits.exc_cause, issue_slots[1].out_uop.exc_cause \n connect issue_slots[0].in_uop.bits.exception, issue_slots[1].out_uop.exception \n connect issue_slots[0].in_uop.bits.stale_pdst, issue_slots[1].out_uop.stale_pdst \n connect issue_slots[0].in_uop.bits.ppred_busy, issue_slots[1].out_uop.ppred_busy \n connect issue_slots[0].in_uop.bits.prs3_busy, issue_slots[1].out_uop.prs3_busy \n connect issue_slots[0].in_uop.bits.prs2_busy, issue_slots[1].out_uop.prs2_busy \n connect issue_slots[0].in_uop.bits.prs1_busy, issue_slots[1].out_uop.prs1_busy \n connect issue_slots[0].in_uop.bits.ppred, issue_slots[1].out_uop.ppred \n connect issue_slots[0].in_uop.bits.prs3, issue_slots[1].out_uop.prs3 \n connect issue_slots[0].in_uop.bits.prs2, issue_slots[1].out_uop.prs2 \n connect issue_slots[0].in_uop.bits.prs1, issue_slots[1].out_uop.prs1 \n connect issue_slots[0].in_uop.bits.pdst, issue_slots[1].out_uop.pdst \n connect issue_slots[0].in_uop.bits.rxq_idx, issue_slots[1].out_uop.rxq_idx \n connect issue_slots[0].in_uop.bits.stq_idx, issue_slots[1].out_uop.stq_idx \n connect issue_slots[0].in_uop.bits.ldq_idx, issue_slots[1].out_uop.ldq_idx \n connect issue_slots[0].in_uop.bits.rob_idx, issue_slots[1].out_uop.rob_idx \n connect issue_slots[0].in_uop.bits.fp_ctrl.vec, issue_slots[1].out_uop.fp_ctrl.vec \n connect issue_slots[0].in_uop.bits.fp_ctrl.wflags, issue_slots[1].out_uop.fp_ctrl.wflags \n connect issue_slots[0].in_uop.bits.fp_ctrl.sqrt, issue_slots[1].out_uop.fp_ctrl.sqrt \n connect issue_slots[0].in_uop.bits.fp_ctrl.div, issue_slots[1].out_uop.fp_ctrl.div \n connect issue_slots[0].in_uop.bits.fp_ctrl.fma, issue_slots[1].out_uop.fp_ctrl.fma \n connect issue_slots[0].in_uop.bits.fp_ctrl.fastpipe, issue_slots[1].out_uop.fp_ctrl.fastpipe \n connect issue_slots[0].in_uop.bits.fp_ctrl.toint, issue_slots[1].out_uop.fp_ctrl.toint \n connect issue_slots[0].in_uop.bits.fp_ctrl.fromint, issue_slots[1].out_uop.fp_ctrl.fromint \n connect issue_slots[0].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[1].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[0].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[1].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[0].in_uop.bits.fp_ctrl.swap23, issue_slots[1].out_uop.fp_ctrl.swap23 \n connect issue_slots[0].in_uop.bits.fp_ctrl.swap12, issue_slots[1].out_uop.fp_ctrl.swap12 \n connect issue_slots[0].in_uop.bits.fp_ctrl.ren3, issue_slots[1].out_uop.fp_ctrl.ren3 \n connect issue_slots[0].in_uop.bits.fp_ctrl.ren2, issue_slots[1].out_uop.fp_ctrl.ren2 \n connect issue_slots[0].in_uop.bits.fp_ctrl.ren1, issue_slots[1].out_uop.fp_ctrl.ren1 \n connect issue_slots[0].in_uop.bits.fp_ctrl.wen, issue_slots[1].out_uop.fp_ctrl.wen \n connect issue_slots[0].in_uop.bits.fp_ctrl.ldst, issue_slots[1].out_uop.fp_ctrl.ldst \n connect issue_slots[0].in_uop.bits.op2_sel, issue_slots[1].out_uop.op2_sel \n connect issue_slots[0].in_uop.bits.op1_sel, issue_slots[1].out_uop.op1_sel \n connect issue_slots[0].in_uop.bits.imm_packed, issue_slots[1].out_uop.imm_packed \n connect issue_slots[0].in_uop.bits.pimm, issue_slots[1].out_uop.pimm \n connect issue_slots[0].in_uop.bits.imm_sel, issue_slots[1].out_uop.imm_sel \n connect issue_slots[0].in_uop.bits.imm_rename, issue_slots[1].out_uop.imm_rename \n connect issue_slots[0].in_uop.bits.taken, issue_slots[1].out_uop.taken \n connect issue_slots[0].in_uop.bits.pc_lob, issue_slots[1].out_uop.pc_lob \n connect issue_slots[0].in_uop.bits.edge_inst, issue_slots[1].out_uop.edge_inst \n connect issue_slots[0].in_uop.bits.ftq_idx, issue_slots[1].out_uop.ftq_idx \n connect issue_slots[0].in_uop.bits.is_mov, issue_slots[1].out_uop.is_mov \n connect issue_slots[0].in_uop.bits.is_rocc, issue_slots[1].out_uop.is_rocc \n connect issue_slots[0].in_uop.bits.is_sys_pc2epc, issue_slots[1].out_uop.is_sys_pc2epc \n connect issue_slots[0].in_uop.bits.is_eret, issue_slots[1].out_uop.is_eret \n connect issue_slots[0].in_uop.bits.is_amo, issue_slots[1].out_uop.is_amo \n connect issue_slots[0].in_uop.bits.is_sfence, issue_slots[1].out_uop.is_sfence \n connect issue_slots[0].in_uop.bits.is_fencei, issue_slots[1].out_uop.is_fencei \n connect issue_slots[0].in_uop.bits.is_fence, issue_slots[1].out_uop.is_fence \n connect issue_slots[0].in_uop.bits.is_sfb, issue_slots[1].out_uop.is_sfb \n connect issue_slots[0].in_uop.bits.br_type, issue_slots[1].out_uop.br_type \n connect issue_slots[0].in_uop.bits.br_tag, issue_slots[1].out_uop.br_tag \n connect issue_slots[0].in_uop.bits.br_mask, issue_slots[1].out_uop.br_mask \n connect issue_slots[0].in_uop.bits.dis_col_sel, issue_slots[1].out_uop.dis_col_sel \n connect issue_slots[0].in_uop.bits.iw_p3_bypass_hint, issue_slots[1].out_uop.iw_p3_bypass_hint \n connect issue_slots[0].in_uop.bits.iw_p2_bypass_hint, issue_slots[1].out_uop.iw_p2_bypass_hint \n connect issue_slots[0].in_uop.bits.iw_p1_bypass_hint, issue_slots[1].out_uop.iw_p1_bypass_hint \n connect issue_slots[0].in_uop.bits.iw_p2_speculative_child, issue_slots[1].out_uop.iw_p2_speculative_child \n connect issue_slots[0].in_uop.bits.iw_p1_speculative_child, issue_slots[1].out_uop.iw_p1_speculative_child \n connect issue_slots[0].in_uop.bits.iw_issued_partial_dgen, issue_slots[1].out_uop.iw_issued_partial_dgen \n connect issue_slots[0].in_uop.bits.iw_issued_partial_agen, issue_slots[1].out_uop.iw_issued_partial_agen \n connect issue_slots[0].in_uop.bits.iw_issued, issue_slots[1].out_uop.iw_issued \n connect issue_slots[0].in_uop.bits.fu_code[0], issue_slots[1].out_uop.fu_code[0] \n connect issue_slots[0].in_uop.bits.fu_code[1], issue_slots[1].out_uop.fu_code[1] \n connect issue_slots[0].in_uop.bits.fu_code[2], issue_slots[1].out_uop.fu_code[2] \n connect issue_slots[0].in_uop.bits.fu_code[3], issue_slots[1].out_uop.fu_code[3] \n connect issue_slots[0].in_uop.bits.fu_code[4], issue_slots[1].out_uop.fu_code[4] \n connect issue_slots[0].in_uop.bits.fu_code[5], issue_slots[1].out_uop.fu_code[5] \n connect issue_slots[0].in_uop.bits.fu_code[6], issue_slots[1].out_uop.fu_code[6] \n connect issue_slots[0].in_uop.bits.fu_code[7], issue_slots[1].out_uop.fu_code[7] \n connect issue_slots[0].in_uop.bits.fu_code[8], issue_slots[1].out_uop.fu_code[8] \n connect issue_slots[0].in_uop.bits.fu_code[9], issue_slots[1].out_uop.fu_code[9] \n connect issue_slots[0].in_uop.bits.iq_type[0], issue_slots[1].out_uop.iq_type[0] \n connect issue_slots[0].in_uop.bits.iq_type[1], issue_slots[1].out_uop.iq_type[1] \n connect issue_slots[0].in_uop.bits.iq_type[2], issue_slots[1].out_uop.iq_type[2] \n connect issue_slots[0].in_uop.bits.iq_type[3], issue_slots[1].out_uop.iq_type[3] \n connect issue_slots[0].in_uop.bits.debug_pc, issue_slots[1].out_uop.debug_pc \n connect issue_slots[0].in_uop.bits.is_rvc, issue_slots[1].out_uop.is_rvc \n connect issue_slots[0].in_uop.bits.debug_inst, issue_slots[1].out_uop.debug_inst \n connect issue_slots[0].in_uop.bits.inst, issue_slots[1].out_uop.inst \n node _T_162 = eq(shamts_oh[1], UInt<1>(0h1)) \n when _T_162 : \n connect issue_slots[0].in_uop.valid, issue_slots[1].will_be_valid \n connect issue_slots[0].in_uop.bits.debug_tsrc, issue_slots[1].out_uop.debug_tsrc \n connect issue_slots[0].in_uop.bits.debug_fsrc, issue_slots[1].out_uop.debug_fsrc \n connect issue_slots[0].in_uop.bits.bp_xcpt_if, issue_slots[1].out_uop.bp_xcpt_if \n connect issue_slots[0].in_uop.bits.bp_debug_if, issue_slots[1].out_uop.bp_debug_if \n connect issue_slots[0].in_uop.bits.xcpt_ma_if, issue_slots[1].out_uop.xcpt_ma_if \n connect issue_slots[0].in_uop.bits.xcpt_ae_if, issue_slots[1].out_uop.xcpt_ae_if \n connect issue_slots[0].in_uop.bits.xcpt_pf_if, issue_slots[1].out_uop.xcpt_pf_if \n connect issue_slots[0].in_uop.bits.fp_typ, issue_slots[1].out_uop.fp_typ \n connect issue_slots[0].in_uop.bits.fp_rm, issue_slots[1].out_uop.fp_rm \n connect issue_slots[0].in_uop.bits.fp_val, issue_slots[1].out_uop.fp_val \n connect issue_slots[0].in_uop.bits.fcn_op, issue_slots[1].out_uop.fcn_op \n connect issue_slots[0].in_uop.bits.fcn_dw, issue_slots[1].out_uop.fcn_dw \n connect issue_slots[0].in_uop.bits.frs3_en, issue_slots[1].out_uop.frs3_en \n connect issue_slots[0].in_uop.bits.lrs2_rtype, issue_slots[1].out_uop.lrs2_rtype \n connect issue_slots[0].in_uop.bits.lrs1_rtype, issue_slots[1].out_uop.lrs1_rtype \n connect issue_slots[0].in_uop.bits.dst_rtype, issue_slots[1].out_uop.dst_rtype \n connect issue_slots[0].in_uop.bits.lrs3, issue_slots[1].out_uop.lrs3 \n connect issue_slots[0].in_uop.bits.lrs2, issue_slots[1].out_uop.lrs2 \n connect issue_slots[0].in_uop.bits.lrs1, issue_slots[1].out_uop.lrs1 \n connect issue_slots[0].in_uop.bits.ldst, issue_slots[1].out_uop.ldst \n connect issue_slots[0].in_uop.bits.ldst_is_rs1, issue_slots[1].out_uop.ldst_is_rs1 \n connect issue_slots[0].in_uop.bits.csr_cmd, issue_slots[1].out_uop.csr_cmd \n connect issue_slots[0].in_uop.bits.flush_on_commit, issue_slots[1].out_uop.flush_on_commit \n connect issue_slots[0].in_uop.bits.is_unique, issue_slots[1].out_uop.is_unique \n connect issue_slots[0].in_uop.bits.uses_stq, issue_slots[1].out_uop.uses_stq \n connect issue_slots[0].in_uop.bits.uses_ldq, issue_slots[1].out_uop.uses_ldq \n connect issue_slots[0].in_uop.bits.mem_signed, issue_slots[1].out_uop.mem_signed \n connect issue_slots[0].in_uop.bits.mem_size, issue_slots[1].out_uop.mem_size \n connect issue_slots[0].in_uop.bits.mem_cmd, issue_slots[1].out_uop.mem_cmd \n connect issue_slots[0].in_uop.bits.exc_cause, issue_slots[1].out_uop.exc_cause \n connect issue_slots[0].in_uop.bits.exception, issue_slots[1].out_uop.exception \n connect issue_slots[0].in_uop.bits.stale_pdst, issue_slots[1].out_uop.stale_pdst \n connect issue_slots[0].in_uop.bits.ppred_busy, issue_slots[1].out_uop.ppred_busy \n connect issue_slots[0].in_uop.bits.prs3_busy, issue_slots[1].out_uop.prs3_busy \n connect issue_slots[0].in_uop.bits.prs2_busy, issue_slots[1].out_uop.prs2_busy \n connect issue_slots[0].in_uop.bits.prs1_busy, issue_slots[1].out_uop.prs1_busy \n connect issue_slots[0].in_uop.bits.ppred, issue_slots[1].out_uop.ppred \n connect issue_slots[0].in_uop.bits.prs3, issue_slots[1].out_uop.prs3 \n connect issue_slots[0].in_uop.bits.prs2, issue_slots[1].out_uop.prs2 \n connect issue_slots[0].in_uop.bits.prs1, issue_slots[1].out_uop.prs1 \n connect issue_slots[0].in_uop.bits.pdst, issue_slots[1].out_uop.pdst \n connect issue_slots[0].in_uop.bits.rxq_idx, issue_slots[1].out_uop.rxq_idx \n connect issue_slots[0].in_uop.bits.stq_idx, issue_slots[1].out_uop.stq_idx \n connect issue_slots[0].in_uop.bits.ldq_idx, issue_slots[1].out_uop.ldq_idx \n connect issue_slots[0].in_uop.bits.rob_idx, issue_slots[1].out_uop.rob_idx \n connect issue_slots[0].in_uop.bits.fp_ctrl.vec, issue_slots[1].out_uop.fp_ctrl.vec \n connect issue_slots[0].in_uop.bits.fp_ctrl.wflags, issue_slots[1].out_uop.fp_ctrl.wflags \n connect issue_slots[0].in_uop.bits.fp_ctrl.sqrt, issue_slots[1].out_uop.fp_ctrl.sqrt \n connect issue_slots[0].in_uop.bits.fp_ctrl.div, issue_slots[1].out_uop.fp_ctrl.div \n connect issue_slots[0].in_uop.bits.fp_ctrl.fma, issue_slots[1].out_uop.fp_ctrl.fma \n connect issue_slots[0].in_uop.bits.fp_ctrl.fastpipe, issue_slots[1].out_uop.fp_ctrl.fastpipe \n connect issue_slots[0].in_uop.bits.fp_ctrl.toint, issue_slots[1].out_uop.fp_ctrl.toint \n connect issue_slots[0].in_uop.bits.fp_ctrl.fromint, issue_slots[1].out_uop.fp_ctrl.fromint \n connect issue_slots[0].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[1].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[0].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[1].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[0].in_uop.bits.fp_ctrl.swap23, issue_slots[1].out_uop.fp_ctrl.swap23 \n connect issue_slots[0].in_uop.bits.fp_ctrl.swap12, issue_slots[1].out_uop.fp_ctrl.swap12 \n connect issue_slots[0].in_uop.bits.fp_ctrl.ren3, issue_slots[1].out_uop.fp_ctrl.ren3 \n connect issue_slots[0].in_uop.bits.fp_ctrl.ren2, issue_slots[1].out_uop.fp_ctrl.ren2 \n connect issue_slots[0].in_uop.bits.fp_ctrl.ren1, issue_slots[1].out_uop.fp_ctrl.ren1 \n connect issue_slots[0].in_uop.bits.fp_ctrl.wen, issue_slots[1].out_uop.fp_ctrl.wen \n connect issue_slots[0].in_uop.bits.fp_ctrl.ldst, issue_slots[1].out_uop.fp_ctrl.ldst \n connect issue_slots[0].in_uop.bits.op2_sel, issue_slots[1].out_uop.op2_sel \n connect issue_slots[0].in_uop.bits.op1_sel, issue_slots[1].out_uop.op1_sel \n connect issue_slots[0].in_uop.bits.imm_packed, issue_slots[1].out_uop.imm_packed \n connect issue_slots[0].in_uop.bits.pimm, issue_slots[1].out_uop.pimm \n connect issue_slots[0].in_uop.bits.imm_sel, issue_slots[1].out_uop.imm_sel \n connect issue_slots[0].in_uop.bits.imm_rename, issue_slots[1].out_uop.imm_rename \n connect issue_slots[0].in_uop.bits.taken, issue_slots[1].out_uop.taken \n connect issue_slots[0].in_uop.bits.pc_lob, issue_slots[1].out_uop.pc_lob \n connect issue_slots[0].in_uop.bits.edge_inst, issue_slots[1].out_uop.edge_inst \n connect issue_slots[0].in_uop.bits.ftq_idx, issue_slots[1].out_uop.ftq_idx \n connect issue_slots[0].in_uop.bits.is_mov, issue_slots[1].out_uop.is_mov \n connect issue_slots[0].in_uop.bits.is_rocc, issue_slots[1].out_uop.is_rocc \n connect issue_slots[0].in_uop.bits.is_sys_pc2epc, issue_slots[1].out_uop.is_sys_pc2epc \n connect issue_slots[0].in_uop.bits.is_eret, issue_slots[1].out_uop.is_eret \n connect issue_slots[0].in_uop.bits.is_amo, issue_slots[1].out_uop.is_amo \n connect issue_slots[0].in_uop.bits.is_sfence, issue_slots[1].out_uop.is_sfence \n connect issue_slots[0].in_uop.bits.is_fencei, issue_slots[1].out_uop.is_fencei \n connect issue_slots[0].in_uop.bits.is_fence, issue_slots[1].out_uop.is_fence \n connect issue_slots[0].in_uop.bits.is_sfb, issue_slots[1].out_uop.is_sfb \n connect issue_slots[0].in_uop.bits.br_type, issue_slots[1].out_uop.br_type \n connect issue_slots[0].in_uop.bits.br_tag, issue_slots[1].out_uop.br_tag \n connect issue_slots[0].in_uop.bits.br_mask, issue_slots[1].out_uop.br_mask \n connect issue_slots[0].in_uop.bits.dis_col_sel, issue_slots[1].out_uop.dis_col_sel \n connect issue_slots[0].in_uop.bits.iw_p3_bypass_hint, issue_slots[1].out_uop.iw_p3_bypass_hint \n connect issue_slots[0].in_uop.bits.iw_p2_bypass_hint, issue_slots[1].out_uop.iw_p2_bypass_hint \n connect issue_slots[0].in_uop.bits.iw_p1_bypass_hint, issue_slots[1].out_uop.iw_p1_bypass_hint \n connect issue_slots[0].in_uop.bits.iw_p2_speculative_child, issue_slots[1].out_uop.iw_p2_speculative_child \n connect issue_slots[0].in_uop.bits.iw_p1_speculative_child, issue_slots[1].out_uop.iw_p1_speculative_child \n connect issue_slots[0].in_uop.bits.iw_issued_partial_dgen, issue_slots[1].out_uop.iw_issued_partial_dgen \n connect issue_slots[0].in_uop.bits.iw_issued_partial_agen, issue_slots[1].out_uop.iw_issued_partial_agen \n connect issue_slots[0].in_uop.bits.iw_issued, issue_slots[1].out_uop.iw_issued \n connect issue_slots[0].in_uop.bits.fu_code[0], issue_slots[1].out_uop.fu_code[0] \n connect issue_slots[0].in_uop.bits.fu_code[1], issue_slots[1].out_uop.fu_code[1] \n connect issue_slots[0].in_uop.bits.fu_code[2], issue_slots[1].out_uop.fu_code[2] \n connect issue_slots[0].in_uop.bits.fu_code[3], issue_slots[1].out_uop.fu_code[3] \n connect issue_slots[0].in_uop.bits.fu_code[4], issue_slots[1].out_uop.fu_code[4] \n connect issue_slots[0].in_uop.bits.fu_code[5], issue_slots[1].out_uop.fu_code[5] \n connect issue_slots[0].in_uop.bits.fu_code[6], issue_slots[1].out_uop.fu_code[6] \n connect issue_slots[0].in_uop.bits.fu_code[7], issue_slots[1].out_uop.fu_code[7] \n connect issue_slots[0].in_uop.bits.fu_code[8], issue_slots[1].out_uop.fu_code[8] \n connect issue_slots[0].in_uop.bits.fu_code[9], issue_slots[1].out_uop.fu_code[9] \n connect issue_slots[0].in_uop.bits.iq_type[0], issue_slots[1].out_uop.iq_type[0] \n connect issue_slots[0].in_uop.bits.iq_type[1], issue_slots[1].out_uop.iq_type[1] \n connect issue_slots[0].in_uop.bits.iq_type[2], issue_slots[1].out_uop.iq_type[2] \n connect issue_slots[0].in_uop.bits.iq_type[3], issue_slots[1].out_uop.iq_type[3] \n connect issue_slots[0].in_uop.bits.debug_pc, issue_slots[1].out_uop.debug_pc \n connect issue_slots[0].in_uop.bits.is_rvc, issue_slots[1].out_uop.is_rvc \n connect issue_slots[0].in_uop.bits.debug_inst, issue_slots[1].out_uop.debug_inst \n connect issue_slots[0].in_uop.bits.inst, issue_slots[1].out_uop.inst \n node _T_163 = eq(shamts_oh[2], UInt<2>(0h2)) \n when _T_163 : \n connect issue_slots[0].in_uop.valid, issue_slots[2].will_be_valid \n connect issue_slots[0].in_uop.bits.debug_tsrc, issue_slots[2].out_uop.debug_tsrc \n connect issue_slots[0].in_uop.bits.debug_fsrc, issue_slots[2].out_uop.debug_fsrc \n connect issue_slots[0].in_uop.bits.bp_xcpt_if, issue_slots[2].out_uop.bp_xcpt_if \n connect issue_slots[0].in_uop.bits.bp_debug_if, issue_slots[2].out_uop.bp_debug_if \n connect issue_slots[0].in_uop.bits.xcpt_ma_if, issue_slots[2].out_uop.xcpt_ma_if \n connect issue_slots[0].in_uop.bits.xcpt_ae_if, issue_slots[2].out_uop.xcpt_ae_if \n connect issue_slots[0].in_uop.bits.xcpt_pf_if, issue_slots[2].out_uop.xcpt_pf_if \n connect issue_slots[0].in_uop.bits.fp_typ, issue_slots[2].out_uop.fp_typ \n connect issue_slots[0].in_uop.bits.fp_rm, issue_slots[2].out_uop.fp_rm \n connect issue_slots[0].in_uop.bits.fp_val, issue_slots[2].out_uop.fp_val \n connect issue_slots[0].in_uop.bits.fcn_op, issue_slots[2].out_uop.fcn_op \n connect issue_slots[0].in_uop.bits.fcn_dw, issue_slots[2].out_uop.fcn_dw \n connect issue_slots[0].in_uop.bits.frs3_en, issue_slots[2].out_uop.frs3_en \n connect issue_slots[0].in_uop.bits.lrs2_rtype, issue_slots[2].out_uop.lrs2_rtype \n connect issue_slots[0].in_uop.bits.lrs1_rtype, issue_slots[2].out_uop.lrs1_rtype \n connect issue_slots[0].in_uop.bits.dst_rtype, issue_slots[2].out_uop.dst_rtype \n connect issue_slots[0].in_uop.bits.lrs3, issue_slots[2].out_uop.lrs3 \n connect issue_slots[0].in_uop.bits.lrs2, issue_slots[2].out_uop.lrs2 \n connect issue_slots[0].in_uop.bits.lrs1, issue_slots[2].out_uop.lrs1 \n connect issue_slots[0].in_uop.bits.ldst, issue_slots[2].out_uop.ldst \n connect issue_slots[0].in_uop.bits.ldst_is_rs1, issue_slots[2].out_uop.ldst_is_rs1 \n connect issue_slots[0].in_uop.bits.csr_cmd, issue_slots[2].out_uop.csr_cmd \n connect issue_slots[0].in_uop.bits.flush_on_commit, issue_slots[2].out_uop.flush_on_commit \n connect issue_slots[0].in_uop.bits.is_unique, issue_slots[2].out_uop.is_unique \n connect issue_slots[0].in_uop.bits.uses_stq, issue_slots[2].out_uop.uses_stq \n connect issue_slots[0].in_uop.bits.uses_ldq, issue_slots[2].out_uop.uses_ldq \n connect issue_slots[0].in_uop.bits.mem_signed, issue_slots[2].out_uop.mem_signed \n connect issue_slots[0].in_uop.bits.mem_size, issue_slots[2].out_uop.mem_size \n connect issue_slots[0].in_uop.bits.mem_cmd, issue_slots[2].out_uop.mem_cmd \n connect issue_slots[0].in_uop.bits.exc_cause, issue_slots[2].out_uop.exc_cause \n connect issue_slots[0].in_uop.bits.exception, issue_slots[2].out_uop.exception \n connect issue_slots[0].in_uop.bits.stale_pdst, issue_slots[2].out_uop.stale_pdst \n connect issue_slots[0].in_uop.bits.ppred_busy, issue_slots[2].out_uop.ppred_busy \n connect issue_slots[0].in_uop.bits.prs3_busy, issue_slots[2].out_uop.prs3_busy \n connect issue_slots[0].in_uop.bits.prs2_busy, issue_slots[2].out_uop.prs2_busy \n connect issue_slots[0].in_uop.bits.prs1_busy, issue_slots[2].out_uop.prs1_busy \n connect issue_slots[0].in_uop.bits.ppred, issue_slots[2].out_uop.ppred \n connect issue_slots[0].in_uop.bits.prs3, issue_slots[2].out_uop.prs3 \n connect issue_slots[0].in_uop.bits.prs2, issue_slots[2].out_uop.prs2 \n connect issue_slots[0].in_uop.bits.prs1, issue_slots[2].out_uop.prs1 \n connect issue_slots[0].in_uop.bits.pdst, issue_slots[2].out_uop.pdst \n connect issue_slots[0].in_uop.bits.rxq_idx, issue_slots[2].out_uop.rxq_idx \n connect issue_slots[0].in_uop.bits.stq_idx, issue_slots[2].out_uop.stq_idx \n connect issue_slots[0].in_uop.bits.ldq_idx, issue_slots[2].out_uop.ldq_idx \n connect issue_slots[0].in_uop.bits.rob_idx, issue_slots[2].out_uop.rob_idx \n connect issue_slots[0].in_uop.bits.fp_ctrl.vec, issue_slots[2].out_uop.fp_ctrl.vec \n connect issue_slots[0].in_uop.bits.fp_ctrl.wflags, issue_slots[2].out_uop.fp_ctrl.wflags \n connect issue_slots[0].in_uop.bits.fp_ctrl.sqrt, issue_slots[2].out_uop.fp_ctrl.sqrt \n connect issue_slots[0].in_uop.bits.fp_ctrl.div, issue_slots[2].out_uop.fp_ctrl.div \n connect issue_slots[0].in_uop.bits.fp_ctrl.fma, issue_slots[2].out_uop.fp_ctrl.fma \n connect issue_slots[0].in_uop.bits.fp_ctrl.fastpipe, issue_slots[2].out_uop.fp_ctrl.fastpipe \n connect issue_slots[0].in_uop.bits.fp_ctrl.toint, issue_slots[2].out_uop.fp_ctrl.toint \n connect issue_slots[0].in_uop.bits.fp_ctrl.fromint, issue_slots[2].out_uop.fp_ctrl.fromint \n connect issue_slots[0].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[2].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[0].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[2].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[0].in_uop.bits.fp_ctrl.swap23, issue_slots[2].out_uop.fp_ctrl.swap23 \n connect issue_slots[0].in_uop.bits.fp_ctrl.swap12, issue_slots[2].out_uop.fp_ctrl.swap12 \n connect issue_slots[0].in_uop.bits.fp_ctrl.ren3, issue_slots[2].out_uop.fp_ctrl.ren3 \n connect issue_slots[0].in_uop.bits.fp_ctrl.ren2, issue_slots[2].out_uop.fp_ctrl.ren2 \n connect issue_slots[0].in_uop.bits.fp_ctrl.ren1, issue_slots[2].out_uop.fp_ctrl.ren1 \n connect issue_slots[0].in_uop.bits.fp_ctrl.wen, issue_slots[2].out_uop.fp_ctrl.wen \n connect issue_slots[0].in_uop.bits.fp_ctrl.ldst, issue_slots[2].out_uop.fp_ctrl.ldst \n connect issue_slots[0].in_uop.bits.op2_sel, issue_slots[2].out_uop.op2_sel \n connect issue_slots[0].in_uop.bits.op1_sel, issue_slots[2].out_uop.op1_sel \n connect issue_slots[0].in_uop.bits.imm_packed, issue_slots[2].out_uop.imm_packed \n connect issue_slots[0].in_uop.bits.pimm, issue_slots[2].out_uop.pimm \n connect issue_slots[0].in_uop.bits.imm_sel, issue_slots[2].out_uop.imm_sel \n connect issue_slots[0].in_uop.bits.imm_rename, issue_slots[2].out_uop.imm_rename \n connect issue_slots[0].in_uop.bits.taken, issue_slots[2].out_uop.taken \n connect issue_slots[0].in_uop.bits.pc_lob, issue_slots[2].out_uop.pc_lob \n connect issue_slots[0].in_uop.bits.edge_inst, issue_slots[2].out_uop.edge_inst \n connect issue_slots[0].in_uop.bits.ftq_idx, issue_slots[2].out_uop.ftq_idx \n connect issue_slots[0].in_uop.bits.is_mov, issue_slots[2].out_uop.is_mov \n connect issue_slots[0].in_uop.bits.is_rocc, issue_slots[2].out_uop.is_rocc \n connect issue_slots[0].in_uop.bits.is_sys_pc2epc, issue_slots[2].out_uop.is_sys_pc2epc \n connect issue_slots[0].in_uop.bits.is_eret, issue_slots[2].out_uop.is_eret \n connect issue_slots[0].in_uop.bits.is_amo, issue_slots[2].out_uop.is_amo \n connect issue_slots[0].in_uop.bits.is_sfence, issue_slots[2].out_uop.is_sfence \n connect issue_slots[0].in_uop.bits.is_fencei, issue_slots[2].out_uop.is_fencei \n connect issue_slots[0].in_uop.bits.is_fence, issue_slots[2].out_uop.is_fence \n connect issue_slots[0].in_uop.bits.is_sfb, issue_slots[2].out_uop.is_sfb \n connect issue_slots[0].in_uop.bits.br_type, issue_slots[2].out_uop.br_type \n connect issue_slots[0].in_uop.bits.br_tag, issue_slots[2].out_uop.br_tag \n connect issue_slots[0].in_uop.bits.br_mask, issue_slots[2].out_uop.br_mask \n connect issue_slots[0].in_uop.bits.dis_col_sel, issue_slots[2].out_uop.dis_col_sel \n connect issue_slots[0].in_uop.bits.iw_p3_bypass_hint, issue_slots[2].out_uop.iw_p3_bypass_hint \n connect issue_slots[0].in_uop.bits.iw_p2_bypass_hint, issue_slots[2].out_uop.iw_p2_bypass_hint \n connect issue_slots[0].in_uop.bits.iw_p1_bypass_hint, issue_slots[2].out_uop.iw_p1_bypass_hint \n connect issue_slots[0].in_uop.bits.iw_p2_speculative_child, issue_slots[2].out_uop.iw_p2_speculative_child \n connect issue_slots[0].in_uop.bits.iw_p1_speculative_child, issue_slots[2].out_uop.iw_p1_speculative_child \n connect issue_slots[0].in_uop.bits.iw_issued_partial_dgen, issue_slots[2].out_uop.iw_issued_partial_dgen \n connect issue_slots[0].in_uop.bits.iw_issued_partial_agen, issue_slots[2].out_uop.iw_issued_partial_agen \n connect issue_slots[0].in_uop.bits.iw_issued, issue_slots[2].out_uop.iw_issued \n connect issue_slots[0].in_uop.bits.fu_code[0], issue_slots[2].out_uop.fu_code[0] \n connect issue_slots[0].in_uop.bits.fu_code[1], issue_slots[2].out_uop.fu_code[1] \n connect issue_slots[0].in_uop.bits.fu_code[2], issue_slots[2].out_uop.fu_code[2] \n connect issue_slots[0].in_uop.bits.fu_code[3], issue_slots[2].out_uop.fu_code[3] \n connect issue_slots[0].in_uop.bits.fu_code[4], issue_slots[2].out_uop.fu_code[4] \n connect issue_slots[0].in_uop.bits.fu_code[5], issue_slots[2].out_uop.fu_code[5] \n connect issue_slots[0].in_uop.bits.fu_code[6], issue_slots[2].out_uop.fu_code[6] \n connect issue_slots[0].in_uop.bits.fu_code[7], issue_slots[2].out_uop.fu_code[7] \n connect issue_slots[0].in_uop.bits.fu_code[8], issue_slots[2].out_uop.fu_code[8] \n connect issue_slots[0].in_uop.bits.fu_code[9], issue_slots[2].out_uop.fu_code[9] \n connect issue_slots[0].in_uop.bits.iq_type[0], issue_slots[2].out_uop.iq_type[0] \n connect issue_slots[0].in_uop.bits.iq_type[1], issue_slots[2].out_uop.iq_type[1] \n connect issue_slots[0].in_uop.bits.iq_type[2], issue_slots[2].out_uop.iq_type[2] \n connect issue_slots[0].in_uop.bits.iq_type[3], issue_slots[2].out_uop.iq_type[3] \n connect issue_slots[0].in_uop.bits.debug_pc, issue_slots[2].out_uop.debug_pc \n connect issue_slots[0].in_uop.bits.is_rvc, issue_slots[2].out_uop.is_rvc \n connect issue_slots[0].in_uop.bits.debug_inst, issue_slots[2].out_uop.debug_inst \n connect issue_slots[0].in_uop.bits.inst, issue_slots[2].out_uop.inst \n node _issue_slots_0_clear_T = neq(shamts_oh[0], UInt<1>(0h0)) \n connect issue_slots[0].clear, _issue_slots_0_clear_T \n connect issue_slots[1].in_uop.valid, UInt<1>(0h0) \n connect issue_slots[1].in_uop.bits.debug_tsrc, issue_slots[2].out_uop.debug_tsrc \n connect issue_slots[1].in_uop.bits.debug_fsrc, issue_slots[2].out_uop.debug_fsrc \n connect issue_slots[1].in_uop.bits.bp_xcpt_if, issue_slots[2].out_uop.bp_xcpt_if \n connect issue_slots[1].in_uop.bits.bp_debug_if, issue_slots[2].out_uop.bp_debug_if \n connect issue_slots[1].in_uop.bits.xcpt_ma_if, issue_slots[2].out_uop.xcpt_ma_if \n connect issue_slots[1].in_uop.bits.xcpt_ae_if, issue_slots[2].out_uop.xcpt_ae_if \n connect issue_slots[1].in_uop.bits.xcpt_pf_if, issue_slots[2].out_uop.xcpt_pf_if \n connect issue_slots[1].in_uop.bits.fp_typ, issue_slots[2].out_uop.fp_typ \n connect issue_slots[1].in_uop.bits.fp_rm, issue_slots[2].out_uop.fp_rm \n connect issue_slots[1].in_uop.bits.fp_val, issue_slots[2].out_uop.fp_val \n connect issue_slots[1].in_uop.bits.fcn_op, issue_slots[2].out_uop.fcn_op \n connect issue_slots[1].in_uop.bits.fcn_dw, issue_slots[2].out_uop.fcn_dw \n connect issue_slots[1].in_uop.bits.frs3_en, issue_slots[2].out_uop.frs3_en \n connect issue_slots[1].in_uop.bits.lrs2_rtype, issue_slots[2].out_uop.lrs2_rtype \n connect issue_slots[1].in_uop.bits.lrs1_rtype, issue_slots[2].out_uop.lrs1_rtype \n connect issue_slots[1].in_uop.bits.dst_rtype, issue_slots[2].out_uop.dst_rtype \n connect issue_slots[1].in_uop.bits.lrs3, issue_slots[2].out_uop.lrs3 \n connect issue_slots[1].in_uop.bits.lrs2, issue_slots[2].out_uop.lrs2 \n connect issue_slots[1].in_uop.bits.lrs1, issue_slots[2].out_uop.lrs1 \n connect issue_slots[1].in_uop.bits.ldst, issue_slots[2].out_uop.ldst \n connect issue_slots[1].in_uop.bits.ldst_is_rs1, issue_slots[2].out_uop.ldst_is_rs1 \n connect issue_slots[1].in_uop.bits.csr_cmd, issue_slots[2].out_uop.csr_cmd \n connect issue_slots[1].in_uop.bits.flush_on_commit, issue_slots[2].out_uop.flush_on_commit \n connect issue_slots[1].in_uop.bits.is_unique, issue_slots[2].out_uop.is_unique \n connect issue_slots[1].in_uop.bits.uses_stq, issue_slots[2].out_uop.uses_stq \n connect issue_slots[1].in_uop.bits.uses_ldq, issue_slots[2].out_uop.uses_ldq \n connect issue_slots[1].in_uop.bits.mem_signed, issue_slots[2].out_uop.mem_signed \n connect issue_slots[1].in_uop.bits.mem_size, issue_slots[2].out_uop.mem_size \n connect issue_slots[1].in_uop.bits.mem_cmd, issue_slots[2].out_uop.mem_cmd \n connect issue_slots[1].in_uop.bits.exc_cause, issue_slots[2].out_uop.exc_cause \n connect issue_slots[1].in_uop.bits.exception, issue_slots[2].out_uop.exception \n connect issue_slots[1].in_uop.bits.stale_pdst, issue_slots[2].out_uop.stale_pdst \n connect issue_slots[1].in_uop.bits.ppred_busy, issue_slots[2].out_uop.ppred_busy \n connect issue_slots[1].in_uop.bits.prs3_busy, issue_slots[2].out_uop.prs3_busy \n connect issue_slots[1].in_uop.bits.prs2_busy, issue_slots[2].out_uop.prs2_busy \n connect issue_slots[1].in_uop.bits.prs1_busy, issue_slots[2].out_uop.prs1_busy \n connect issue_slots[1].in_uop.bits.ppred, issue_slots[2].out_uop.ppred \n connect issue_slots[1].in_uop.bits.prs3, issue_slots[2].out_uop.prs3 \n connect issue_slots[1].in_uop.bits.prs2, issue_slots[2].out_uop.prs2 \n connect issue_slots[1].in_uop.bits.prs1, issue_slots[2].out_uop.prs1 \n connect issue_slots[1].in_uop.bits.pdst, issue_slots[2].out_uop.pdst \n connect issue_slots[1].in_uop.bits.rxq_idx, issue_slots[2].out_uop.rxq_idx \n connect issue_slots[1].in_uop.bits.stq_idx, issue_slots[2].out_uop.stq_idx \n connect issue_slots[1].in_uop.bits.ldq_idx, issue_slots[2].out_uop.ldq_idx \n connect issue_slots[1].in_uop.bits.rob_idx, issue_slots[2].out_uop.rob_idx \n connect issue_slots[1].in_uop.bits.fp_ctrl.vec, issue_slots[2].out_uop.fp_ctrl.vec \n connect issue_slots[1].in_uop.bits.fp_ctrl.wflags, issue_slots[2].out_uop.fp_ctrl.wflags \n connect issue_slots[1].in_uop.bits.fp_ctrl.sqrt, issue_slots[2].out_uop.fp_ctrl.sqrt \n connect issue_slots[1].in_uop.bits.fp_ctrl.div, issue_slots[2].out_uop.fp_ctrl.div \n connect issue_slots[1].in_uop.bits.fp_ctrl.fma, issue_slots[2].out_uop.fp_ctrl.fma \n connect issue_slots[1].in_uop.bits.fp_ctrl.fastpipe, issue_slots[2].out_uop.fp_ctrl.fastpipe \n connect issue_slots[1].in_uop.bits.fp_ctrl.toint, issue_slots[2].out_uop.fp_ctrl.toint \n connect issue_slots[1].in_uop.bits.fp_ctrl.fromint, issue_slots[2].out_uop.fp_ctrl.fromint \n connect issue_slots[1].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[2].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[1].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[2].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[1].in_uop.bits.fp_ctrl.swap23, issue_slots[2].out_uop.fp_ctrl.swap23 \n connect issue_slots[1].in_uop.bits.fp_ctrl.swap12, issue_slots[2].out_uop.fp_ctrl.swap12 \n connect issue_slots[1].in_uop.bits.fp_ctrl.ren3, issue_slots[2].out_uop.fp_ctrl.ren3 \n connect issue_slots[1].in_uop.bits.fp_ctrl.ren2, issue_slots[2].out_uop.fp_ctrl.ren2 \n connect issue_slots[1].in_uop.bits.fp_ctrl.ren1, issue_slots[2].out_uop.fp_ctrl.ren1 \n connect issue_slots[1].in_uop.bits.fp_ctrl.wen, issue_slots[2].out_uop.fp_ctrl.wen \n connect issue_slots[1].in_uop.bits.fp_ctrl.ldst, issue_slots[2].out_uop.fp_ctrl.ldst \n connect issue_slots[1].in_uop.bits.op2_sel, issue_slots[2].out_uop.op2_sel \n connect issue_slots[1].in_uop.bits.op1_sel, issue_slots[2].out_uop.op1_sel \n connect issue_slots[1].in_uop.bits.imm_packed, issue_slots[2].out_uop.imm_packed \n connect issue_slots[1].in_uop.bits.pimm, issue_slots[2].out_uop.pimm \n connect issue_slots[1].in_uop.bits.imm_sel, issue_slots[2].out_uop.imm_sel \n connect issue_slots[1].in_uop.bits.imm_rename, issue_slots[2].out_uop.imm_rename \n connect issue_slots[1].in_uop.bits.taken, issue_slots[2].out_uop.taken \n connect issue_slots[1].in_uop.bits.pc_lob, issue_slots[2].out_uop.pc_lob \n connect issue_slots[1].in_uop.bits.edge_inst, issue_slots[2].out_uop.edge_inst \n connect issue_slots[1].in_uop.bits.ftq_idx, issue_slots[2].out_uop.ftq_idx \n connect issue_slots[1].in_uop.bits.is_mov, issue_slots[2].out_uop.is_mov \n connect issue_slots[1].in_uop.bits.is_rocc, issue_slots[2].out_uop.is_rocc \n connect issue_slots[1].in_uop.bits.is_sys_pc2epc, issue_slots[2].out_uop.is_sys_pc2epc \n connect issue_slots[1].in_uop.bits.is_eret, issue_slots[2].out_uop.is_eret \n connect issue_slots[1].in_uop.bits.is_amo, issue_slots[2].out_uop.is_amo \n connect issue_slots[1].in_uop.bits.is_sfence, issue_slots[2].out_uop.is_sfence \n connect issue_slots[1].in_uop.bits.is_fencei, issue_slots[2].out_uop.is_fencei \n connect issue_slots[1].in_uop.bits.is_fence, issue_slots[2].out_uop.is_fence \n connect issue_slots[1].in_uop.bits.is_sfb, issue_slots[2].out_uop.is_sfb \n connect issue_slots[1].in_uop.bits.br_type, issue_slots[2].out_uop.br_type \n connect issue_slots[1].in_uop.bits.br_tag, issue_slots[2].out_uop.br_tag \n connect issue_slots[1].in_uop.bits.br_mask, issue_slots[2].out_uop.br_mask \n connect issue_slots[1].in_uop.bits.dis_col_sel, issue_slots[2].out_uop.dis_col_sel \n connect issue_slots[1].in_uop.bits.iw_p3_bypass_hint, issue_slots[2].out_uop.iw_p3_bypass_hint \n connect issue_slots[1].in_uop.bits.iw_p2_bypass_hint, issue_slots[2].out_uop.iw_p2_bypass_hint \n connect issue_slots[1].in_uop.bits.iw_p1_bypass_hint, issue_slots[2].out_uop.iw_p1_bypass_hint \n connect issue_slots[1].in_uop.bits.iw_p2_speculative_child, issue_slots[2].out_uop.iw_p2_speculative_child \n connect issue_slots[1].in_uop.bits.iw_p1_speculative_child, issue_slots[2].out_uop.iw_p1_speculative_child \n connect issue_slots[1].in_uop.bits.iw_issued_partial_dgen, issue_slots[2].out_uop.iw_issued_partial_dgen \n connect issue_slots[1].in_uop.bits.iw_issued_partial_agen, issue_slots[2].out_uop.iw_issued_partial_agen \n connect issue_slots[1].in_uop.bits.iw_issued, issue_slots[2].out_uop.iw_issued \n connect issue_slots[1].in_uop.bits.fu_code[0], issue_slots[2].out_uop.fu_code[0] \n connect issue_slots[1].in_uop.bits.fu_code[1], issue_slots[2].out_uop.fu_code[1] \n connect issue_slots[1].in_uop.bits.fu_code[2], issue_slots[2].out_uop.fu_code[2] \n connect issue_slots[1].in_uop.bits.fu_code[3], issue_slots[2].out_uop.fu_code[3] \n connect issue_slots[1].in_uop.bits.fu_code[4], issue_slots[2].out_uop.fu_code[4] \n connect issue_slots[1].in_uop.bits.fu_code[5], issue_slots[2].out_uop.fu_code[5] \n connect issue_slots[1].in_uop.bits.fu_code[6], issue_slots[2].out_uop.fu_code[6] \n connect issue_slots[1].in_uop.bits.fu_code[7], issue_slots[2].out_uop.fu_code[7] \n connect issue_slots[1].in_uop.bits.fu_code[8], issue_slots[2].out_uop.fu_code[8] \n connect issue_slots[1].in_uop.bits.fu_code[9], issue_slots[2].out_uop.fu_code[9] \n connect issue_slots[1].in_uop.bits.iq_type[0], issue_slots[2].out_uop.iq_type[0] \n connect issue_slots[1].in_uop.bits.iq_type[1], issue_slots[2].out_uop.iq_type[1] \n connect issue_slots[1].in_uop.bits.iq_type[2], issue_slots[2].out_uop.iq_type[2] \n connect issue_slots[1].in_uop.bits.iq_type[3], issue_slots[2].out_uop.iq_type[3] \n connect issue_slots[1].in_uop.bits.debug_pc, issue_slots[2].out_uop.debug_pc \n connect issue_slots[1].in_uop.bits.is_rvc, issue_slots[2].out_uop.is_rvc \n connect issue_slots[1].in_uop.bits.debug_inst, issue_slots[2].out_uop.debug_inst \n connect issue_slots[1].in_uop.bits.inst, issue_slots[2].out_uop.inst \n node _T_164 = eq(shamts_oh[2], UInt<1>(0h1)) \n when _T_164 : \n connect issue_slots[1].in_uop.valid, issue_slots[2].will_be_valid \n connect issue_slots[1].in_uop.bits.debug_tsrc, issue_slots[2].out_uop.debug_tsrc \n connect issue_slots[1].in_uop.bits.debug_fsrc, issue_slots[2].out_uop.debug_fsrc \n connect issue_slots[1].in_uop.bits.bp_xcpt_if, issue_slots[2].out_uop.bp_xcpt_if \n connect issue_slots[1].in_uop.bits.bp_debug_if, issue_slots[2].out_uop.bp_debug_if \n connect issue_slots[1].in_uop.bits.xcpt_ma_if, issue_slots[2].out_uop.xcpt_ma_if \n connect issue_slots[1].in_uop.bits.xcpt_ae_if, issue_slots[2].out_uop.xcpt_ae_if \n connect issue_slots[1].in_uop.bits.xcpt_pf_if, issue_slots[2].out_uop.xcpt_pf_if \n connect issue_slots[1].in_uop.bits.fp_typ, issue_slots[2].out_uop.fp_typ \n connect issue_slots[1].in_uop.bits.fp_rm, issue_slots[2].out_uop.fp_rm \n connect issue_slots[1].in_uop.bits.fp_val, issue_slots[2].out_uop.fp_val \n connect issue_slots[1].in_uop.bits.fcn_op, issue_slots[2].out_uop.fcn_op \n connect issue_slots[1].in_uop.bits.fcn_dw, issue_slots[2].out_uop.fcn_dw \n connect issue_slots[1].in_uop.bits.frs3_en, issue_slots[2].out_uop.frs3_en \n connect issue_slots[1].in_uop.bits.lrs2_rtype, issue_slots[2].out_uop.lrs2_rtype \n connect issue_slots[1].in_uop.bits.lrs1_rtype, issue_slots[2].out_uop.lrs1_rtype \n connect issue_slots[1].in_uop.bits.dst_rtype, issue_slots[2].out_uop.dst_rtype \n connect issue_slots[1].in_uop.bits.lrs3, issue_slots[2].out_uop.lrs3 \n connect issue_slots[1].in_uop.bits.lrs2, issue_slots[2].out_uop.lrs2 \n connect issue_slots[1].in_uop.bits.lrs1, issue_slots[2].out_uop.lrs1 \n connect issue_slots[1].in_uop.bits.ldst, issue_slots[2].out_uop.ldst \n connect issue_slots[1].in_uop.bits.ldst_is_rs1, issue_slots[2].out_uop.ldst_is_rs1 \n connect issue_slots[1].in_uop.bits.csr_cmd, issue_slots[2].out_uop.csr_cmd \n connect issue_slots[1].in_uop.bits.flush_on_commit, issue_slots[2].out_uop.flush_on_commit \n connect issue_slots[1].in_uop.bits.is_unique, issue_slots[2].out_uop.is_unique \n connect issue_slots[1].in_uop.bits.uses_stq, issue_slots[2].out_uop.uses_stq \n connect issue_slots[1].in_uop.bits.uses_ldq, issue_slots[2].out_uop.uses_ldq \n connect issue_slots[1].in_uop.bits.mem_signed, issue_slots[2].out_uop.mem_signed \n connect issue_slots[1].in_uop.bits.mem_size, issue_slots[2].out_uop.mem_size \n connect issue_slots[1].in_uop.bits.mem_cmd, issue_slots[2].out_uop.mem_cmd \n connect issue_slots[1].in_uop.bits.exc_cause, issue_slots[2].out_uop.exc_cause \n connect issue_slots[1].in_uop.bits.exception, issue_slots[2].out_uop.exception \n connect issue_slots[1].in_uop.bits.stale_pdst, issue_slots[2].out_uop.stale_pdst \n connect issue_slots[1].in_uop.bits.ppred_busy, issue_slots[2].out_uop.ppred_busy \n connect issue_slots[1].in_uop.bits.prs3_busy, issue_slots[2].out_uop.prs3_busy \n connect issue_slots[1].in_uop.bits.prs2_busy, issue_slots[2].out_uop.prs2_busy \n connect issue_slots[1].in_uop.bits.prs1_busy, issue_slots[2].out_uop.prs1_busy \n connect issue_slots[1].in_uop.bits.ppred, issue_slots[2].out_uop.ppred \n connect issue_slots[1].in_uop.bits.prs3, issue_slots[2].out_uop.prs3 \n connect issue_slots[1].in_uop.bits.prs2, issue_slots[2].out_uop.prs2 \n connect issue_slots[1].in_uop.bits.prs1, issue_slots[2].out_uop.prs1 \n connect issue_slots[1].in_uop.bits.pdst, issue_slots[2].out_uop.pdst \n connect issue_slots[1].in_uop.bits.rxq_idx, issue_slots[2].out_uop.rxq_idx \n connect issue_slots[1].in_uop.bits.stq_idx, issue_slots[2].out_uop.stq_idx \n connect issue_slots[1].in_uop.bits.ldq_idx, issue_slots[2].out_uop.ldq_idx \n connect issue_slots[1].in_uop.bits.rob_idx, issue_slots[2].out_uop.rob_idx \n connect issue_slots[1].in_uop.bits.fp_ctrl.vec, issue_slots[2].out_uop.fp_ctrl.vec \n connect issue_slots[1].in_uop.bits.fp_ctrl.wflags, issue_slots[2].out_uop.fp_ctrl.wflags \n connect issue_slots[1].in_uop.bits.fp_ctrl.sqrt, issue_slots[2].out_uop.fp_ctrl.sqrt \n connect issue_slots[1].in_uop.bits.fp_ctrl.div, issue_slots[2].out_uop.fp_ctrl.div \n connect issue_slots[1].in_uop.bits.fp_ctrl.fma, issue_slots[2].out_uop.fp_ctrl.fma \n connect issue_slots[1].in_uop.bits.fp_ctrl.fastpipe, issue_slots[2].out_uop.fp_ctrl.fastpipe \n connect issue_slots[1].in_uop.bits.fp_ctrl.toint, issue_slots[2].out_uop.fp_ctrl.toint \n connect issue_slots[1].in_uop.bits.fp_ctrl.fromint, issue_slots[2].out_uop.fp_ctrl.fromint \n connect issue_slots[1].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[2].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[1].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[2].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[1].in_uop.bits.fp_ctrl.swap23, issue_slots[2].out_uop.fp_ctrl.swap23 \n connect issue_slots[1].in_uop.bits.fp_ctrl.swap12, issue_slots[2].out_uop.fp_ctrl.swap12 \n connect issue_slots[1].in_uop.bits.fp_ctrl.ren3, issue_slots[2].out_uop.fp_ctrl.ren3 \n connect issue_slots[1].in_uop.bits.fp_ctrl.ren2, issue_slots[2].out_uop.fp_ctrl.ren2 \n connect issue_slots[1].in_uop.bits.fp_ctrl.ren1, issue_slots[2].out_uop.fp_ctrl.ren1 \n connect issue_slots[1].in_uop.bits.fp_ctrl.wen, issue_slots[2].out_uop.fp_ctrl.wen \n connect issue_slots[1].in_uop.bits.fp_ctrl.ldst, issue_slots[2].out_uop.fp_ctrl.ldst \n connect issue_slots[1].in_uop.bits.op2_sel, issue_slots[2].out_uop.op2_sel \n connect issue_slots[1].in_uop.bits.op1_sel, issue_slots[2].out_uop.op1_sel \n connect issue_slots[1].in_uop.bits.imm_packed, issue_slots[2].out_uop.imm_packed \n connect issue_slots[1].in_uop.bits.pimm, issue_slots[2].out_uop.pimm \n connect issue_slots[1].in_uop.bits.imm_sel, issue_slots[2].out_uop.imm_sel \n connect issue_slots[1].in_uop.bits.imm_rename, issue_slots[2].out_uop.imm_rename \n connect issue_slots[1].in_uop.bits.taken, issue_slots[2].out_uop.taken \n connect issue_slots[1].in_uop.bits.pc_lob, issue_slots[2].out_uop.pc_lob \n connect issue_slots[1].in_uop.bits.edge_inst, issue_slots[2].out_uop.edge_inst \n connect issue_slots[1].in_uop.bits.ftq_idx, issue_slots[2].out_uop.ftq_idx \n connect issue_slots[1].in_uop.bits.is_mov, issue_slots[2].out_uop.is_mov \n connect issue_slots[1].in_uop.bits.is_rocc, issue_slots[2].out_uop.is_rocc \n connect issue_slots[1].in_uop.bits.is_sys_pc2epc, issue_slots[2].out_uop.is_sys_pc2epc \n connect issue_slots[1].in_uop.bits.is_eret, issue_slots[2].out_uop.is_eret \n connect issue_slots[1].in_uop.bits.is_amo, issue_slots[2].out_uop.is_amo \n connect issue_slots[1].in_uop.bits.is_sfence, issue_slots[2].out_uop.is_sfence \n connect issue_slots[1].in_uop.bits.is_fencei, issue_slots[2].out_uop.is_fencei \n connect issue_slots[1].in_uop.bits.is_fence, issue_slots[2].out_uop.is_fence \n connect issue_slots[1].in_uop.bits.is_sfb, issue_slots[2].out_uop.is_sfb \n connect issue_slots[1].in_uop.bits.br_type, issue_slots[2].out_uop.br_type \n connect issue_slots[1].in_uop.bits.br_tag, issue_slots[2].out_uop.br_tag \n connect issue_slots[1].in_uop.bits.br_mask, issue_slots[2].out_uop.br_mask \n connect issue_slots[1].in_uop.bits.dis_col_sel, issue_slots[2].out_uop.dis_col_sel \n connect issue_slots[1].in_uop.bits.iw_p3_bypass_hint, issue_slots[2].out_uop.iw_p3_bypass_hint \n connect issue_slots[1].in_uop.bits.iw_p2_bypass_hint, issue_slots[2].out_uop.iw_p2_bypass_hint \n connect issue_slots[1].in_uop.bits.iw_p1_bypass_hint, issue_slots[2].out_uop.iw_p1_bypass_hint \n connect issue_slots[1].in_uop.bits.iw_p2_speculative_child, issue_slots[2].out_uop.iw_p2_speculative_child \n connect issue_slots[1].in_uop.bits.iw_p1_speculative_child, issue_slots[2].out_uop.iw_p1_speculative_child \n connect issue_slots[1].in_uop.bits.iw_issued_partial_dgen, issue_slots[2].out_uop.iw_issued_partial_dgen \n connect issue_slots[1].in_uop.bits.iw_issued_partial_agen, issue_slots[2].out_uop.iw_issued_partial_agen \n connect issue_slots[1].in_uop.bits.iw_issued, issue_slots[2].out_uop.iw_issued \n connect issue_slots[1].in_uop.bits.fu_code[0], issue_slots[2].out_uop.fu_code[0] \n connect issue_slots[1].in_uop.bits.fu_code[1], issue_slots[2].out_uop.fu_code[1] \n connect issue_slots[1].in_uop.bits.fu_code[2], issue_slots[2].out_uop.fu_code[2] \n connect issue_slots[1].in_uop.bits.fu_code[3], issue_slots[2].out_uop.fu_code[3] \n connect issue_slots[1].in_uop.bits.fu_code[4], issue_slots[2].out_uop.fu_code[4] \n connect issue_slots[1].in_uop.bits.fu_code[5], issue_slots[2].out_uop.fu_code[5] \n connect issue_slots[1].in_uop.bits.fu_code[6], issue_slots[2].out_uop.fu_code[6] \n connect issue_slots[1].in_uop.bits.fu_code[7], issue_slots[2].out_uop.fu_code[7] \n connect issue_slots[1].in_uop.bits.fu_code[8], issue_slots[2].out_uop.fu_code[8] \n connect issue_slots[1].in_uop.bits.fu_code[9], issue_slots[2].out_uop.fu_code[9] \n connect issue_slots[1].in_uop.bits.iq_type[0], issue_slots[2].out_uop.iq_type[0] \n connect issue_slots[1].in_uop.bits.iq_type[1], issue_slots[2].out_uop.iq_type[1] \n connect issue_slots[1].in_uop.bits.iq_type[2], issue_slots[2].out_uop.iq_type[2] \n connect issue_slots[1].in_uop.bits.iq_type[3], issue_slots[2].out_uop.iq_type[3] \n connect issue_slots[1].in_uop.bits.debug_pc, issue_slots[2].out_uop.debug_pc \n connect issue_slots[1].in_uop.bits.is_rvc, issue_slots[2].out_uop.is_rvc \n connect issue_slots[1].in_uop.bits.debug_inst, issue_slots[2].out_uop.debug_inst \n connect issue_slots[1].in_uop.bits.inst, issue_slots[2].out_uop.inst \n node _T_165 = eq(shamts_oh[3], UInt<2>(0h2)) \n when _T_165 : \n connect issue_slots[1].in_uop.valid, issue_slots[3].will_be_valid \n connect issue_slots[1].in_uop.bits.debug_tsrc, issue_slots[3].out_uop.debug_tsrc \n connect issue_slots[1].in_uop.bits.debug_fsrc, issue_slots[3].out_uop.debug_fsrc \n connect issue_slots[1].in_uop.bits.bp_xcpt_if, issue_slots[3].out_uop.bp_xcpt_if \n connect issue_slots[1].in_uop.bits.bp_debug_if, issue_slots[3].out_uop.bp_debug_if \n connect issue_slots[1].in_uop.bits.xcpt_ma_if, issue_slots[3].out_uop.xcpt_ma_if \n connect issue_slots[1].in_uop.bits.xcpt_ae_if, issue_slots[3].out_uop.xcpt_ae_if \n connect issue_slots[1].in_uop.bits.xcpt_pf_if, issue_slots[3].out_uop.xcpt_pf_if \n connect issue_slots[1].in_uop.bits.fp_typ, issue_slots[3].out_uop.fp_typ \n connect issue_slots[1].in_uop.bits.fp_rm, issue_slots[3].out_uop.fp_rm \n connect issue_slots[1].in_uop.bits.fp_val, issue_slots[3].out_uop.fp_val \n connect issue_slots[1].in_uop.bits.fcn_op, issue_slots[3].out_uop.fcn_op \n connect issue_slots[1].in_uop.bits.fcn_dw, issue_slots[3].out_uop.fcn_dw \n connect issue_slots[1].in_uop.bits.frs3_en, issue_slots[3].out_uop.frs3_en \n connect issue_slots[1].in_uop.bits.lrs2_rtype, issue_slots[3].out_uop.lrs2_rtype \n connect issue_slots[1].in_uop.bits.lrs1_rtype, issue_slots[3].out_uop.lrs1_rtype \n connect issue_slots[1].in_uop.bits.dst_rtype, issue_slots[3].out_uop.dst_rtype \n connect issue_slots[1].in_uop.bits.lrs3, issue_slots[3].out_uop.lrs3 \n connect issue_slots[1].in_uop.bits.lrs2, issue_slots[3].out_uop.lrs2 \n connect issue_slots[1].in_uop.bits.lrs1, issue_slots[3].out_uop.lrs1 \n connect issue_slots[1].in_uop.bits.ldst, issue_slots[3].out_uop.ldst \n connect issue_slots[1].in_uop.bits.ldst_is_rs1, issue_slots[3].out_uop.ldst_is_rs1 \n connect issue_slots[1].in_uop.bits.csr_cmd, issue_slots[3].out_uop.csr_cmd \n connect issue_slots[1].in_uop.bits.flush_on_commit, issue_slots[3].out_uop.flush_on_commit \n connect issue_slots[1].in_uop.bits.is_unique, issue_slots[3].out_uop.is_unique \n connect issue_slots[1].in_uop.bits.uses_stq, issue_slots[3].out_uop.uses_stq \n connect issue_slots[1].in_uop.bits.uses_ldq, issue_slots[3].out_uop.uses_ldq \n connect issue_slots[1].in_uop.bits.mem_signed, issue_slots[3].out_uop.mem_signed \n connect issue_slots[1].in_uop.bits.mem_size, issue_slots[3].out_uop.mem_size \n connect issue_slots[1].in_uop.bits.mem_cmd, issue_slots[3].out_uop.mem_cmd \n connect issue_slots[1].in_uop.bits.exc_cause, issue_slots[3].out_uop.exc_cause \n connect issue_slots[1].in_uop.bits.exception, issue_slots[3].out_uop.exception \n connect issue_slots[1].in_uop.bits.stale_pdst, issue_slots[3].out_uop.stale_pdst \n connect issue_slots[1].in_uop.bits.ppred_busy, issue_slots[3].out_uop.ppred_busy \n connect issue_slots[1].in_uop.bits.prs3_busy, issue_slots[3].out_uop.prs3_busy \n connect issue_slots[1].in_uop.bits.prs2_busy, issue_slots[3].out_uop.prs2_busy \n connect issue_slots[1].in_uop.bits.prs1_busy, issue_slots[3].out_uop.prs1_busy \n connect issue_slots[1].in_uop.bits.ppred, issue_slots[3].out_uop.ppred \n connect issue_slots[1].in_uop.bits.prs3, issue_slots[3].out_uop.prs3 \n connect issue_slots[1].in_uop.bits.prs2, issue_slots[3].out_uop.prs2 \n connect issue_slots[1].in_uop.bits.prs1, issue_slots[3].out_uop.prs1 \n connect issue_slots[1].in_uop.bits.pdst, issue_slots[3].out_uop.pdst \n connect issue_slots[1].in_uop.bits.rxq_idx, issue_slots[3].out_uop.rxq_idx \n connect issue_slots[1].in_uop.bits.stq_idx, issue_slots[3].out_uop.stq_idx \n connect issue_slots[1].in_uop.bits.ldq_idx, issue_slots[3].out_uop.ldq_idx \n connect issue_slots[1].in_uop.bits.rob_idx, issue_slots[3].out_uop.rob_idx \n connect issue_slots[1].in_uop.bits.fp_ctrl.vec, issue_slots[3].out_uop.fp_ctrl.vec \n connect issue_slots[1].in_uop.bits.fp_ctrl.wflags, issue_slots[3].out_uop.fp_ctrl.wflags \n connect issue_slots[1].in_uop.bits.fp_ctrl.sqrt, issue_slots[3].out_uop.fp_ctrl.sqrt \n connect issue_slots[1].in_uop.bits.fp_ctrl.div, issue_slots[3].out_uop.fp_ctrl.div \n connect issue_slots[1].in_uop.bits.fp_ctrl.fma, issue_slots[3].out_uop.fp_ctrl.fma \n connect issue_slots[1].in_uop.bits.fp_ctrl.fastpipe, issue_slots[3].out_uop.fp_ctrl.fastpipe \n connect issue_slots[1].in_uop.bits.fp_ctrl.toint, issue_slots[3].out_uop.fp_ctrl.toint \n connect issue_slots[1].in_uop.bits.fp_ctrl.fromint, issue_slots[3].out_uop.fp_ctrl.fromint \n connect issue_slots[1].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[3].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[1].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[3].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[1].in_uop.bits.fp_ctrl.swap23, issue_slots[3].out_uop.fp_ctrl.swap23 \n connect issue_slots[1].in_uop.bits.fp_ctrl.swap12, issue_slots[3].out_uop.fp_ctrl.swap12 \n connect issue_slots[1].in_uop.bits.fp_ctrl.ren3, issue_slots[3].out_uop.fp_ctrl.ren3 \n connect issue_slots[1].in_uop.bits.fp_ctrl.ren2, issue_slots[3].out_uop.fp_ctrl.ren2 \n connect issue_slots[1].in_uop.bits.fp_ctrl.ren1, issue_slots[3].out_uop.fp_ctrl.ren1 \n connect issue_slots[1].in_uop.bits.fp_ctrl.wen, issue_slots[3].out_uop.fp_ctrl.wen \n connect issue_slots[1].in_uop.bits.fp_ctrl.ldst, issue_slots[3].out_uop.fp_ctrl.ldst \n connect issue_slots[1].in_uop.bits.op2_sel, issue_slots[3].out_uop.op2_sel \n connect issue_slots[1].in_uop.bits.op1_sel, issue_slots[3].out_uop.op1_sel \n connect issue_slots[1].in_uop.bits.imm_packed, issue_slots[3].out_uop.imm_packed \n connect issue_slots[1].in_uop.bits.pimm, issue_slots[3].out_uop.pimm \n connect issue_slots[1].in_uop.bits.imm_sel, issue_slots[3].out_uop.imm_sel \n connect issue_slots[1].in_uop.bits.imm_rename, issue_slots[3].out_uop.imm_rename \n connect issue_slots[1].in_uop.bits.taken, issue_slots[3].out_uop.taken \n connect issue_slots[1].in_uop.bits.pc_lob, issue_slots[3].out_uop.pc_lob \n connect issue_slots[1].in_uop.bits.edge_inst, issue_slots[3].out_uop.edge_inst \n connect issue_slots[1].in_uop.bits.ftq_idx, issue_slots[3].out_uop.ftq_idx \n connect issue_slots[1].in_uop.bits.is_mov, issue_slots[3].out_uop.is_mov \n connect issue_slots[1].in_uop.bits.is_rocc, issue_slots[3].out_uop.is_rocc \n connect issue_slots[1].in_uop.bits.is_sys_pc2epc, issue_slots[3].out_uop.is_sys_pc2epc \n connect issue_slots[1].in_uop.bits.is_eret, issue_slots[3].out_uop.is_eret \n connect issue_slots[1].in_uop.bits.is_amo, issue_slots[3].out_uop.is_amo \n connect issue_slots[1].in_uop.bits.is_sfence, issue_slots[3].out_uop.is_sfence \n connect issue_slots[1].in_uop.bits.is_fencei, issue_slots[3].out_uop.is_fencei \n connect issue_slots[1].in_uop.bits.is_fence, issue_slots[3].out_uop.is_fence \n connect issue_slots[1].in_uop.bits.is_sfb, issue_slots[3].out_uop.is_sfb \n connect issue_slots[1].in_uop.bits.br_type, issue_slots[3].out_uop.br_type \n connect issue_slots[1].in_uop.bits.br_tag, issue_slots[3].out_uop.br_tag \n connect issue_slots[1].in_uop.bits.br_mask, issue_slots[3].out_uop.br_mask \n connect issue_slots[1].in_uop.bits.dis_col_sel, issue_slots[3].out_uop.dis_col_sel \n connect issue_slots[1].in_uop.bits.iw_p3_bypass_hint, issue_slots[3].out_uop.iw_p3_bypass_hint \n connect issue_slots[1].in_uop.bits.iw_p2_bypass_hint, issue_slots[3].out_uop.iw_p2_bypass_hint \n connect issue_slots[1].in_uop.bits.iw_p1_bypass_hint, issue_slots[3].out_uop.iw_p1_bypass_hint \n connect issue_slots[1].in_uop.bits.iw_p2_speculative_child, issue_slots[3].out_uop.iw_p2_speculative_child \n connect issue_slots[1].in_uop.bits.iw_p1_speculative_child, issue_slots[3].out_uop.iw_p1_speculative_child \n connect issue_slots[1].in_uop.bits.iw_issued_partial_dgen, issue_slots[3].out_uop.iw_issued_partial_dgen \n connect issue_slots[1].in_uop.bits.iw_issued_partial_agen, issue_slots[3].out_uop.iw_issued_partial_agen \n connect issue_slots[1].in_uop.bits.iw_issued, issue_slots[3].out_uop.iw_issued \n connect issue_slots[1].in_uop.bits.fu_code[0], issue_slots[3].out_uop.fu_code[0] \n connect issue_slots[1].in_uop.bits.fu_code[1], issue_slots[3].out_uop.fu_code[1] \n connect issue_slots[1].in_uop.bits.fu_code[2], issue_slots[3].out_uop.fu_code[2] \n connect issue_slots[1].in_uop.bits.fu_code[3], issue_slots[3].out_uop.fu_code[3] \n connect issue_slots[1].in_uop.bits.fu_code[4], issue_slots[3].out_uop.fu_code[4] \n connect issue_slots[1].in_uop.bits.fu_code[5], issue_slots[3].out_uop.fu_code[5] \n connect issue_slots[1].in_uop.bits.fu_code[6], issue_slots[3].out_uop.fu_code[6] \n connect issue_slots[1].in_uop.bits.fu_code[7], issue_slots[3].out_uop.fu_code[7] \n connect issue_slots[1].in_uop.bits.fu_code[8], issue_slots[3].out_uop.fu_code[8] \n connect issue_slots[1].in_uop.bits.fu_code[9], issue_slots[3].out_uop.fu_code[9] \n connect issue_slots[1].in_uop.bits.iq_type[0], issue_slots[3].out_uop.iq_type[0] \n connect issue_slots[1].in_uop.bits.iq_type[1], issue_slots[3].out_uop.iq_type[1] \n connect issue_slots[1].in_uop.bits.iq_type[2], issue_slots[3].out_uop.iq_type[2] \n connect issue_slots[1].in_uop.bits.iq_type[3], issue_slots[3].out_uop.iq_type[3] \n connect issue_slots[1].in_uop.bits.debug_pc, issue_slots[3].out_uop.debug_pc \n connect issue_slots[1].in_uop.bits.is_rvc, issue_slots[3].out_uop.is_rvc \n connect issue_slots[1].in_uop.bits.debug_inst, issue_slots[3].out_uop.debug_inst \n connect issue_slots[1].in_uop.bits.inst, issue_slots[3].out_uop.inst \n node _issue_slots_1_clear_T = neq(shamts_oh[1], UInt<1>(0h0)) \n connect issue_slots[1].clear, _issue_slots_1_clear_T \n connect issue_slots[2].in_uop.valid, UInt<1>(0h0) \n connect issue_slots[2].in_uop.bits.debug_tsrc, issue_slots[3].out_uop.debug_tsrc \n connect issue_slots[2].in_uop.bits.debug_fsrc, issue_slots[3].out_uop.debug_fsrc \n connect issue_slots[2].in_uop.bits.bp_xcpt_if, issue_slots[3].out_uop.bp_xcpt_if \n connect issue_slots[2].in_uop.bits.bp_debug_if, issue_slots[3].out_uop.bp_debug_if \n connect issue_slots[2].in_uop.bits.xcpt_ma_if, issue_slots[3].out_uop.xcpt_ma_if \n connect issue_slots[2].in_uop.bits.xcpt_ae_if, issue_slots[3].out_uop.xcpt_ae_if \n connect issue_slots[2].in_uop.bits.xcpt_pf_if, issue_slots[3].out_uop.xcpt_pf_if \n connect issue_slots[2].in_uop.bits.fp_typ, issue_slots[3].out_uop.fp_typ \n connect issue_slots[2].in_uop.bits.fp_rm, issue_slots[3].out_uop.fp_rm \n connect issue_slots[2].in_uop.bits.fp_val, issue_slots[3].out_uop.fp_val \n connect issue_slots[2].in_uop.bits.fcn_op, issue_slots[3].out_uop.fcn_op \n connect issue_slots[2].in_uop.bits.fcn_dw, issue_slots[3].out_uop.fcn_dw \n connect issue_slots[2].in_uop.bits.frs3_en, issue_slots[3].out_uop.frs3_en \n connect issue_slots[2].in_uop.bits.lrs2_rtype, issue_slots[3].out_uop.lrs2_rtype \n connect issue_slots[2].in_uop.bits.lrs1_rtype, issue_slots[3].out_uop.lrs1_rtype \n connect issue_slots[2].in_uop.bits.dst_rtype, issue_slots[3].out_uop.dst_rtype \n connect issue_slots[2].in_uop.bits.lrs3, issue_slots[3].out_uop.lrs3 \n connect issue_slots[2].in_uop.bits.lrs2, issue_slots[3].out_uop.lrs2 \n connect issue_slots[2].in_uop.bits.lrs1, issue_slots[3].out_uop.lrs1 \n connect issue_slots[2].in_uop.bits.ldst, issue_slots[3].out_uop.ldst \n connect issue_slots[2].in_uop.bits.ldst_is_rs1, issue_slots[3].out_uop.ldst_is_rs1 \n connect issue_slots[2].in_uop.bits.csr_cmd, issue_slots[3].out_uop.csr_cmd \n connect issue_slots[2].in_uop.bits.flush_on_commit, issue_slots[3].out_uop.flush_on_commit \n connect issue_slots[2].in_uop.bits.is_unique, issue_slots[3].out_uop.is_unique \n connect issue_slots[2].in_uop.bits.uses_stq, issue_slots[3].out_uop.uses_stq \n connect issue_slots[2].in_uop.bits.uses_ldq, issue_slots[3].out_uop.uses_ldq \n connect issue_slots[2].in_uop.bits.mem_signed, issue_slots[3].out_uop.mem_signed \n connect issue_slots[2].in_uop.bits.mem_size, issue_slots[3].out_uop.mem_size \n connect issue_slots[2].in_uop.bits.mem_cmd, issue_slots[3].out_uop.mem_cmd \n connect issue_slots[2].in_uop.bits.exc_cause, issue_slots[3].out_uop.exc_cause \n connect issue_slots[2].in_uop.bits.exception, issue_slots[3].out_uop.exception \n connect issue_slots[2].in_uop.bits.stale_pdst, issue_slots[3].out_uop.stale_pdst \n connect issue_slots[2].in_uop.bits.ppred_busy, issue_slots[3].out_uop.ppred_busy \n connect issue_slots[2].in_uop.bits.prs3_busy, issue_slots[3].out_uop.prs3_busy \n connect issue_slots[2].in_uop.bits.prs2_busy, issue_slots[3].out_uop.prs2_busy \n connect issue_slots[2].in_uop.bits.prs1_busy, issue_slots[3].out_uop.prs1_busy \n connect issue_slots[2].in_uop.bits.ppred, issue_slots[3].out_uop.ppred \n connect issue_slots[2].in_uop.bits.prs3, issue_slots[3].out_uop.prs3 \n connect issue_slots[2].in_uop.bits.prs2, issue_slots[3].out_uop.prs2 \n connect issue_slots[2].in_uop.bits.prs1, issue_slots[3].out_uop.prs1 \n connect issue_slots[2].in_uop.bits.pdst, issue_slots[3].out_uop.pdst \n connect issue_slots[2].in_uop.bits.rxq_idx, issue_slots[3].out_uop.rxq_idx \n connect issue_slots[2].in_uop.bits.stq_idx, issue_slots[3].out_uop.stq_idx \n connect issue_slots[2].in_uop.bits.ldq_idx, issue_slots[3].out_uop.ldq_idx \n connect issue_slots[2].in_uop.bits.rob_idx, issue_slots[3].out_uop.rob_idx \n connect issue_slots[2].in_uop.bits.fp_ctrl.vec, issue_slots[3].out_uop.fp_ctrl.vec \n connect issue_slots[2].in_uop.bits.fp_ctrl.wflags, issue_slots[3].out_uop.fp_ctrl.wflags \n connect issue_slots[2].in_uop.bits.fp_ctrl.sqrt, issue_slots[3].out_uop.fp_ctrl.sqrt \n connect issue_slots[2].in_uop.bits.fp_ctrl.div, issue_slots[3].out_uop.fp_ctrl.div \n connect issue_slots[2].in_uop.bits.fp_ctrl.fma, issue_slots[3].out_uop.fp_ctrl.fma \n connect issue_slots[2].in_uop.bits.fp_ctrl.fastpipe, issue_slots[3].out_uop.fp_ctrl.fastpipe \n connect issue_slots[2].in_uop.bits.fp_ctrl.toint, issue_slots[3].out_uop.fp_ctrl.toint \n connect issue_slots[2].in_uop.bits.fp_ctrl.fromint, issue_slots[3].out_uop.fp_ctrl.fromint \n connect issue_slots[2].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[3].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[2].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[3].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[2].in_uop.bits.fp_ctrl.swap23, issue_slots[3].out_uop.fp_ctrl.swap23 \n connect issue_slots[2].in_uop.bits.fp_ctrl.swap12, issue_slots[3].out_uop.fp_ctrl.swap12 \n connect issue_slots[2].in_uop.bits.fp_ctrl.ren3, issue_slots[3].out_uop.fp_ctrl.ren3 \n connect issue_slots[2].in_uop.bits.fp_ctrl.ren2, issue_slots[3].out_uop.fp_ctrl.ren2 \n connect issue_slots[2].in_uop.bits.fp_ctrl.ren1, issue_slots[3].out_uop.fp_ctrl.ren1 \n connect issue_slots[2].in_uop.bits.fp_ctrl.wen, issue_slots[3].out_uop.fp_ctrl.wen \n connect issue_slots[2].in_uop.bits.fp_ctrl.ldst, issue_slots[3].out_uop.fp_ctrl.ldst \n connect issue_slots[2].in_uop.bits.op2_sel, issue_slots[3].out_uop.op2_sel \n connect issue_slots[2].in_uop.bits.op1_sel, issue_slots[3].out_uop.op1_sel \n connect issue_slots[2].in_uop.bits.imm_packed, issue_slots[3].out_uop.imm_packed \n connect issue_slots[2].in_uop.bits.pimm, issue_slots[3].out_uop.pimm \n connect issue_slots[2].in_uop.bits.imm_sel, issue_slots[3].out_uop.imm_sel \n connect issue_slots[2].in_uop.bits.imm_rename, issue_slots[3].out_uop.imm_rename \n connect issue_slots[2].in_uop.bits.taken, issue_slots[3].out_uop.taken \n connect issue_slots[2].in_uop.bits.pc_lob, issue_slots[3].out_uop.pc_lob \n connect issue_slots[2].in_uop.bits.edge_inst, issue_slots[3].out_uop.edge_inst \n connect issue_slots[2].in_uop.bits.ftq_idx, issue_slots[3].out_uop.ftq_idx \n connect issue_slots[2].in_uop.bits.is_mov, issue_slots[3].out_uop.is_mov \n connect issue_slots[2].in_uop.bits.is_rocc, issue_slots[3].out_uop.is_rocc \n connect issue_slots[2].in_uop.bits.is_sys_pc2epc, issue_slots[3].out_uop.is_sys_pc2epc \n connect issue_slots[2].in_uop.bits.is_eret, issue_slots[3].out_uop.is_eret \n connect issue_slots[2].in_uop.bits.is_amo, issue_slots[3].out_uop.is_amo \n connect issue_slots[2].in_uop.bits.is_sfence, issue_slots[3].out_uop.is_sfence \n connect issue_slots[2].in_uop.bits.is_fencei, issue_slots[3].out_uop.is_fencei \n connect issue_slots[2].in_uop.bits.is_fence, issue_slots[3].out_uop.is_fence \n connect issue_slots[2].in_uop.bits.is_sfb, issue_slots[3].out_uop.is_sfb \n connect issue_slots[2].in_uop.bits.br_type, issue_slots[3].out_uop.br_type \n connect issue_slots[2].in_uop.bits.br_tag, issue_slots[3].out_uop.br_tag \n connect issue_slots[2].in_uop.bits.br_mask, issue_slots[3].out_uop.br_mask \n connect issue_slots[2].in_uop.bits.dis_col_sel, issue_slots[3].out_uop.dis_col_sel \n connect issue_slots[2].in_uop.bits.iw_p3_bypass_hint, issue_slots[3].out_uop.iw_p3_bypass_hint \n connect issue_slots[2].in_uop.bits.iw_p2_bypass_hint, issue_slots[3].out_uop.iw_p2_bypass_hint \n connect issue_slots[2].in_uop.bits.iw_p1_bypass_hint, issue_slots[3].out_uop.iw_p1_bypass_hint \n connect issue_slots[2].in_uop.bits.iw_p2_speculative_child, issue_slots[3].out_uop.iw_p2_speculative_child \n connect issue_slots[2].in_uop.bits.iw_p1_speculative_child, issue_slots[3].out_uop.iw_p1_speculative_child \n connect issue_slots[2].in_uop.bits.iw_issued_partial_dgen, issue_slots[3].out_uop.iw_issued_partial_dgen \n connect issue_slots[2].in_uop.bits.iw_issued_partial_agen, issue_slots[3].out_uop.iw_issued_partial_agen \n connect issue_slots[2].in_uop.bits.iw_issued, issue_slots[3].out_uop.iw_issued \n connect issue_slots[2].in_uop.bits.fu_code[0], issue_slots[3].out_uop.fu_code[0] \n connect issue_slots[2].in_uop.bits.fu_code[1], issue_slots[3].out_uop.fu_code[1] \n connect issue_slots[2].in_uop.bits.fu_code[2], issue_slots[3].out_uop.fu_code[2] \n connect issue_slots[2].in_uop.bits.fu_code[3], issue_slots[3].out_uop.fu_code[3] \n connect issue_slots[2].in_uop.bits.fu_code[4], issue_slots[3].out_uop.fu_code[4] \n connect issue_slots[2].in_uop.bits.fu_code[5], issue_slots[3].out_uop.fu_code[5] \n connect issue_slots[2].in_uop.bits.fu_code[6], issue_slots[3].out_uop.fu_code[6] \n connect issue_slots[2].in_uop.bits.fu_code[7], issue_slots[3].out_uop.fu_code[7] \n connect issue_slots[2].in_uop.bits.fu_code[8], issue_slots[3].out_uop.fu_code[8] \n connect issue_slots[2].in_uop.bits.fu_code[9], issue_slots[3].out_uop.fu_code[9] \n connect issue_slots[2].in_uop.bits.iq_type[0], issue_slots[3].out_uop.iq_type[0] \n connect issue_slots[2].in_uop.bits.iq_type[1], issue_slots[3].out_uop.iq_type[1] \n connect issue_slots[2].in_uop.bits.iq_type[2], issue_slots[3].out_uop.iq_type[2] \n connect issue_slots[2].in_uop.bits.iq_type[3], issue_slots[3].out_uop.iq_type[3] \n connect issue_slots[2].in_uop.bits.debug_pc, issue_slots[3].out_uop.debug_pc \n connect issue_slots[2].in_uop.bits.is_rvc, issue_slots[3].out_uop.is_rvc \n connect issue_slots[2].in_uop.bits.debug_inst, issue_slots[3].out_uop.debug_inst \n connect issue_slots[2].in_uop.bits.inst, issue_slots[3].out_uop.inst \n node _T_166 = eq(shamts_oh[3], UInt<1>(0h1)) \n when _T_166 : \n connect issue_slots[2].in_uop.valid, issue_slots[3].will_be_valid \n connect issue_slots[2].in_uop.bits.debug_tsrc, issue_slots[3].out_uop.debug_tsrc \n connect issue_slots[2].in_uop.bits.debug_fsrc, issue_slots[3].out_uop.debug_fsrc \n connect issue_slots[2].in_uop.bits.bp_xcpt_if, issue_slots[3].out_uop.bp_xcpt_if \n connect issue_slots[2].in_uop.bits.bp_debug_if, issue_slots[3].out_uop.bp_debug_if \n connect issue_slots[2].in_uop.bits.xcpt_ma_if, issue_slots[3].out_uop.xcpt_ma_if \n connect issue_slots[2].in_uop.bits.xcpt_ae_if, issue_slots[3].out_uop.xcpt_ae_if \n connect issue_slots[2].in_uop.bits.xcpt_pf_if, issue_slots[3].out_uop.xcpt_pf_if \n connect issue_slots[2].in_uop.bits.fp_typ, issue_slots[3].out_uop.fp_typ \n connect issue_slots[2].in_uop.bits.fp_rm, issue_slots[3].out_uop.fp_rm \n connect issue_slots[2].in_uop.bits.fp_val, issue_slots[3].out_uop.fp_val \n connect issue_slots[2].in_uop.bits.fcn_op, issue_slots[3].out_uop.fcn_op \n connect issue_slots[2].in_uop.bits.fcn_dw, issue_slots[3].out_uop.fcn_dw \n connect issue_slots[2].in_uop.bits.frs3_en, issue_slots[3].out_uop.frs3_en \n connect issue_slots[2].in_uop.bits.lrs2_rtype, issue_slots[3].out_uop.lrs2_rtype \n connect issue_slots[2].in_uop.bits.lrs1_rtype, issue_slots[3].out_uop.lrs1_rtype \n connect issue_slots[2].in_uop.bits.dst_rtype, issue_slots[3].out_uop.dst_rtype \n connect issue_slots[2].in_uop.bits.lrs3, issue_slots[3].out_uop.lrs3 \n connect issue_slots[2].in_uop.bits.lrs2, issue_slots[3].out_uop.lrs2 \n connect issue_slots[2].in_uop.bits.lrs1, issue_slots[3].out_uop.lrs1 \n connect issue_slots[2].in_uop.bits.ldst, issue_slots[3].out_uop.ldst \n connect issue_slots[2].in_uop.bits.ldst_is_rs1, issue_slots[3].out_uop.ldst_is_rs1 \n connect issue_slots[2].in_uop.bits.csr_cmd, issue_slots[3].out_uop.csr_cmd \n connect issue_slots[2].in_uop.bits.flush_on_commit, issue_slots[3].out_uop.flush_on_commit \n connect issue_slots[2].in_uop.bits.is_unique, issue_slots[3].out_uop.is_unique \n connect issue_slots[2].in_uop.bits.uses_stq, issue_slots[3].out_uop.uses_stq \n connect issue_slots[2].in_uop.bits.uses_ldq, issue_slots[3].out_uop.uses_ldq \n connect issue_slots[2].in_uop.bits.mem_signed, issue_slots[3].out_uop.mem_signed \n connect issue_slots[2].in_uop.bits.mem_size, issue_slots[3].out_uop.mem_size \n connect issue_slots[2].in_uop.bits.mem_cmd, issue_slots[3].out_uop.mem_cmd \n connect issue_slots[2].in_uop.bits.exc_cause, issue_slots[3].out_uop.exc_cause \n connect issue_slots[2].in_uop.bits.exception, issue_slots[3].out_uop.exception \n connect issue_slots[2].in_uop.bits.stale_pdst, issue_slots[3].out_uop.stale_pdst \n connect issue_slots[2].in_uop.bits.ppred_busy, issue_slots[3].out_uop.ppred_busy \n connect issue_slots[2].in_uop.bits.prs3_busy, issue_slots[3].out_uop.prs3_busy \n connect issue_slots[2].in_uop.bits.prs2_busy, issue_slots[3].out_uop.prs2_busy \n connect issue_slots[2].in_uop.bits.prs1_busy, issue_slots[3].out_uop.prs1_busy \n connect issue_slots[2].in_uop.bits.ppred, issue_slots[3].out_uop.ppred \n connect issue_slots[2].in_uop.bits.prs3, issue_slots[3].out_uop.prs3 \n connect issue_slots[2].in_uop.bits.prs2, issue_slots[3].out_uop.prs2 \n connect issue_slots[2].in_uop.bits.prs1, issue_slots[3].out_uop.prs1 \n connect issue_slots[2].in_uop.bits.pdst, issue_slots[3].out_uop.pdst \n connect issue_slots[2].in_uop.bits.rxq_idx, issue_slots[3].out_uop.rxq_idx \n connect issue_slots[2].in_uop.bits.stq_idx, issue_slots[3].out_uop.stq_idx \n connect issue_slots[2].in_uop.bits.ldq_idx, issue_slots[3].out_uop.ldq_idx \n connect issue_slots[2].in_uop.bits.rob_idx, issue_slots[3].out_uop.rob_idx \n connect issue_slots[2].in_uop.bits.fp_ctrl.vec, issue_slots[3].out_uop.fp_ctrl.vec \n connect issue_slots[2].in_uop.bits.fp_ctrl.wflags, issue_slots[3].out_uop.fp_ctrl.wflags \n connect issue_slots[2].in_uop.bits.fp_ctrl.sqrt, issue_slots[3].out_uop.fp_ctrl.sqrt \n connect issue_slots[2].in_uop.bits.fp_ctrl.div, issue_slots[3].out_uop.fp_ctrl.div \n connect issue_slots[2].in_uop.bits.fp_ctrl.fma, issue_slots[3].out_uop.fp_ctrl.fma \n connect issue_slots[2].in_uop.bits.fp_ctrl.fastpipe, issue_slots[3].out_uop.fp_ctrl.fastpipe \n connect issue_slots[2].in_uop.bits.fp_ctrl.toint, issue_slots[3].out_uop.fp_ctrl.toint \n connect issue_slots[2].in_uop.bits.fp_ctrl.fromint, issue_slots[3].out_uop.fp_ctrl.fromint \n connect issue_slots[2].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[3].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[2].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[3].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[2].in_uop.bits.fp_ctrl.swap23, issue_slots[3].out_uop.fp_ctrl.swap23 \n connect issue_slots[2].in_uop.bits.fp_ctrl.swap12, issue_slots[3].out_uop.fp_ctrl.swap12 \n connect issue_slots[2].in_uop.bits.fp_ctrl.ren3, issue_slots[3].out_uop.fp_ctrl.ren3 \n connect issue_slots[2].in_uop.bits.fp_ctrl.ren2, issue_slots[3].out_uop.fp_ctrl.ren2 \n connect issue_slots[2].in_uop.bits.fp_ctrl.ren1, issue_slots[3].out_uop.fp_ctrl.ren1 \n connect issue_slots[2].in_uop.bits.fp_ctrl.wen, issue_slots[3].out_uop.fp_ctrl.wen \n connect issue_slots[2].in_uop.bits.fp_ctrl.ldst, issue_slots[3].out_uop.fp_ctrl.ldst \n connect issue_slots[2].in_uop.bits.op2_sel, issue_slots[3].out_uop.op2_sel \n connect issue_slots[2].in_uop.bits.op1_sel, issue_slots[3].out_uop.op1_sel \n connect issue_slots[2].in_uop.bits.imm_packed, issue_slots[3].out_uop.imm_packed \n connect issue_slots[2].in_uop.bits.pimm, issue_slots[3].out_uop.pimm \n connect issue_slots[2].in_uop.bits.imm_sel, issue_slots[3].out_uop.imm_sel \n connect issue_slots[2].in_uop.bits.imm_rename, issue_slots[3].out_uop.imm_rename \n connect issue_slots[2].in_uop.bits.taken, issue_slots[3].out_uop.taken \n connect issue_slots[2].in_uop.bits.pc_lob, issue_slots[3].out_uop.pc_lob \n connect issue_slots[2].in_uop.bits.edge_inst, issue_slots[3].out_uop.edge_inst \n connect issue_slots[2].in_uop.bits.ftq_idx, issue_slots[3].out_uop.ftq_idx \n connect issue_slots[2].in_uop.bits.is_mov, issue_slots[3].out_uop.is_mov \n connect issue_slots[2].in_uop.bits.is_rocc, issue_slots[3].out_uop.is_rocc \n connect issue_slots[2].in_uop.bits.is_sys_pc2epc, issue_slots[3].out_uop.is_sys_pc2epc \n connect issue_slots[2].in_uop.bits.is_eret, issue_slots[3].out_uop.is_eret \n connect issue_slots[2].in_uop.bits.is_amo, issue_slots[3].out_uop.is_amo \n connect issue_slots[2].in_uop.bits.is_sfence, issue_slots[3].out_uop.is_sfence \n connect issue_slots[2].in_uop.bits.is_fencei, issue_slots[3].out_uop.is_fencei \n connect issue_slots[2].in_uop.bits.is_fence, issue_slots[3].out_uop.is_fence \n connect issue_slots[2].in_uop.bits.is_sfb, issue_slots[3].out_uop.is_sfb \n connect issue_slots[2].in_uop.bits.br_type, issue_slots[3].out_uop.br_type \n connect issue_slots[2].in_uop.bits.br_tag, issue_slots[3].out_uop.br_tag \n connect issue_slots[2].in_uop.bits.br_mask, issue_slots[3].out_uop.br_mask \n connect issue_slots[2].in_uop.bits.dis_col_sel, issue_slots[3].out_uop.dis_col_sel \n connect issue_slots[2].in_uop.bits.iw_p3_bypass_hint, issue_slots[3].out_uop.iw_p3_bypass_hint \n connect issue_slots[2].in_uop.bits.iw_p2_bypass_hint, issue_slots[3].out_uop.iw_p2_bypass_hint \n connect issue_slots[2].in_uop.bits.iw_p1_bypass_hint, issue_slots[3].out_uop.iw_p1_bypass_hint \n connect issue_slots[2].in_uop.bits.iw_p2_speculative_child, issue_slots[3].out_uop.iw_p2_speculative_child \n connect issue_slots[2].in_uop.bits.iw_p1_speculative_child, issue_slots[3].out_uop.iw_p1_speculative_child \n connect issue_slots[2].in_uop.bits.iw_issued_partial_dgen, issue_slots[3].out_uop.iw_issued_partial_dgen \n connect issue_slots[2].in_uop.bits.iw_issued_partial_agen, issue_slots[3].out_uop.iw_issued_partial_agen \n connect issue_slots[2].in_uop.bits.iw_issued, issue_slots[3].out_uop.iw_issued \n connect issue_slots[2].in_uop.bits.fu_code[0], issue_slots[3].out_uop.fu_code[0] \n connect issue_slots[2].in_uop.bits.fu_code[1], issue_slots[3].out_uop.fu_code[1] \n connect issue_slots[2].in_uop.bits.fu_code[2], issue_slots[3].out_uop.fu_code[2] \n connect issue_slots[2].in_uop.bits.fu_code[3], issue_slots[3].out_uop.fu_code[3] \n connect issue_slots[2].in_uop.bits.fu_code[4], issue_slots[3].out_uop.fu_code[4] \n connect issue_slots[2].in_uop.bits.fu_code[5], issue_slots[3].out_uop.fu_code[5] \n connect issue_slots[2].in_uop.bits.fu_code[6], issue_slots[3].out_uop.fu_code[6] \n connect issue_slots[2].in_uop.bits.fu_code[7], issue_slots[3].out_uop.fu_code[7] \n connect issue_slots[2].in_uop.bits.fu_code[8], issue_slots[3].out_uop.fu_code[8] \n connect issue_slots[2].in_uop.bits.fu_code[9], issue_slots[3].out_uop.fu_code[9] \n connect issue_slots[2].in_uop.bits.iq_type[0], issue_slots[3].out_uop.iq_type[0] \n connect issue_slots[2].in_uop.bits.iq_type[1], issue_slots[3].out_uop.iq_type[1] \n connect issue_slots[2].in_uop.bits.iq_type[2], issue_slots[3].out_uop.iq_type[2] \n connect issue_slots[2].in_uop.bits.iq_type[3], issue_slots[3].out_uop.iq_type[3] \n connect issue_slots[2].in_uop.bits.debug_pc, issue_slots[3].out_uop.debug_pc \n connect issue_slots[2].in_uop.bits.is_rvc, issue_slots[3].out_uop.is_rvc \n connect issue_slots[2].in_uop.bits.debug_inst, issue_slots[3].out_uop.debug_inst \n connect issue_slots[2].in_uop.bits.inst, issue_slots[3].out_uop.inst \n node _T_167 = eq(shamts_oh[4], UInt<2>(0h2)) \n when _T_167 : \n connect issue_slots[2].in_uop.valid, issue_slots[4].will_be_valid \n connect issue_slots[2].in_uop.bits.debug_tsrc, issue_slots[4].out_uop.debug_tsrc \n connect issue_slots[2].in_uop.bits.debug_fsrc, issue_slots[4].out_uop.debug_fsrc \n connect issue_slots[2].in_uop.bits.bp_xcpt_if, issue_slots[4].out_uop.bp_xcpt_if \n connect issue_slots[2].in_uop.bits.bp_debug_if, issue_slots[4].out_uop.bp_debug_if \n connect issue_slots[2].in_uop.bits.xcpt_ma_if, issue_slots[4].out_uop.xcpt_ma_if \n connect issue_slots[2].in_uop.bits.xcpt_ae_if, issue_slots[4].out_uop.xcpt_ae_if \n connect issue_slots[2].in_uop.bits.xcpt_pf_if, issue_slots[4].out_uop.xcpt_pf_if \n connect issue_slots[2].in_uop.bits.fp_typ, issue_slots[4].out_uop.fp_typ \n connect issue_slots[2].in_uop.bits.fp_rm, issue_slots[4].out_uop.fp_rm \n connect issue_slots[2].in_uop.bits.fp_val, issue_slots[4].out_uop.fp_val \n connect issue_slots[2].in_uop.bits.fcn_op, issue_slots[4].out_uop.fcn_op \n connect issue_slots[2].in_uop.bits.fcn_dw, issue_slots[4].out_uop.fcn_dw \n connect issue_slots[2].in_uop.bits.frs3_en, issue_slots[4].out_uop.frs3_en \n connect issue_slots[2].in_uop.bits.lrs2_rtype, issue_slots[4].out_uop.lrs2_rtype \n connect issue_slots[2].in_uop.bits.lrs1_rtype, issue_slots[4].out_uop.lrs1_rtype \n connect issue_slots[2].in_uop.bits.dst_rtype, issue_slots[4].out_uop.dst_rtype \n connect issue_slots[2].in_uop.bits.lrs3, issue_slots[4].out_uop.lrs3 \n connect issue_slots[2].in_uop.bits.lrs2, issue_slots[4].out_uop.lrs2 \n connect issue_slots[2].in_uop.bits.lrs1, issue_slots[4].out_uop.lrs1 \n connect issue_slots[2].in_uop.bits.ldst, issue_slots[4].out_uop.ldst \n connect issue_slots[2].in_uop.bits.ldst_is_rs1, issue_slots[4].out_uop.ldst_is_rs1 \n connect issue_slots[2].in_uop.bits.csr_cmd, issue_slots[4].out_uop.csr_cmd \n connect issue_slots[2].in_uop.bits.flush_on_commit, issue_slots[4].out_uop.flush_on_commit \n connect issue_slots[2].in_uop.bits.is_unique, issue_slots[4].out_uop.is_unique \n connect issue_slots[2].in_uop.bits.uses_stq, issue_slots[4].out_uop.uses_stq \n connect issue_slots[2].in_uop.bits.uses_ldq, issue_slots[4].out_uop.uses_ldq \n connect issue_slots[2].in_uop.bits.mem_signed, issue_slots[4].out_uop.mem_signed \n connect issue_slots[2].in_uop.bits.mem_size, issue_slots[4].out_uop.mem_size \n connect issue_slots[2].in_uop.bits.mem_cmd, issue_slots[4].out_uop.mem_cmd \n connect issue_slots[2].in_uop.bits.exc_cause, issue_slots[4].out_uop.exc_cause \n connect issue_slots[2].in_uop.bits.exception, issue_slots[4].out_uop.exception \n connect issue_slots[2].in_uop.bits.stale_pdst, issue_slots[4].out_uop.stale_pdst \n connect issue_slots[2].in_uop.bits.ppred_busy, issue_slots[4].out_uop.ppred_busy \n connect issue_slots[2].in_uop.bits.prs3_busy, issue_slots[4].out_uop.prs3_busy \n connect issue_slots[2].in_uop.bits.prs2_busy, issue_slots[4].out_uop.prs2_busy \n connect issue_slots[2].in_uop.bits.prs1_busy, issue_slots[4].out_uop.prs1_busy \n connect issue_slots[2].in_uop.bits.ppred, issue_slots[4].out_uop.ppred \n connect issue_slots[2].in_uop.bits.prs3, issue_slots[4].out_uop.prs3 \n connect issue_slots[2].in_uop.bits.prs2, issue_slots[4].out_uop.prs2 \n connect issue_slots[2].in_uop.bits.prs1, issue_slots[4].out_uop.prs1 \n connect issue_slots[2].in_uop.bits.pdst, issue_slots[4].out_uop.pdst \n connect issue_slots[2].in_uop.bits.rxq_idx, issue_slots[4].out_uop.rxq_idx \n connect issue_slots[2].in_uop.bits.stq_idx, issue_slots[4].out_uop.stq_idx \n connect issue_slots[2].in_uop.bits.ldq_idx, issue_slots[4].out_uop.ldq_idx \n connect issue_slots[2].in_uop.bits.rob_idx, issue_slots[4].out_uop.rob_idx \n connect issue_slots[2].in_uop.bits.fp_ctrl.vec, issue_slots[4].out_uop.fp_ctrl.vec \n connect issue_slots[2].in_uop.bits.fp_ctrl.wflags, issue_slots[4].out_uop.fp_ctrl.wflags \n connect issue_slots[2].in_uop.bits.fp_ctrl.sqrt, issue_slots[4].out_uop.fp_ctrl.sqrt \n connect issue_slots[2].in_uop.bits.fp_ctrl.div, issue_slots[4].out_uop.fp_ctrl.div \n connect issue_slots[2].in_uop.bits.fp_ctrl.fma, issue_slots[4].out_uop.fp_ctrl.fma \n connect issue_slots[2].in_uop.bits.fp_ctrl.fastpipe, issue_slots[4].out_uop.fp_ctrl.fastpipe \n connect issue_slots[2].in_uop.bits.fp_ctrl.toint, issue_slots[4].out_uop.fp_ctrl.toint \n connect issue_slots[2].in_uop.bits.fp_ctrl.fromint, issue_slots[4].out_uop.fp_ctrl.fromint \n connect issue_slots[2].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[4].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[2].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[4].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[2].in_uop.bits.fp_ctrl.swap23, issue_slots[4].out_uop.fp_ctrl.swap23 \n connect issue_slots[2].in_uop.bits.fp_ctrl.swap12, issue_slots[4].out_uop.fp_ctrl.swap12 \n connect issue_slots[2].in_uop.bits.fp_ctrl.ren3, issue_slots[4].out_uop.fp_ctrl.ren3 \n connect issue_slots[2].in_uop.bits.fp_ctrl.ren2, issue_slots[4].out_uop.fp_ctrl.ren2 \n connect issue_slots[2].in_uop.bits.fp_ctrl.ren1, issue_slots[4].out_uop.fp_ctrl.ren1 \n connect issue_slots[2].in_uop.bits.fp_ctrl.wen, issue_slots[4].out_uop.fp_ctrl.wen \n connect issue_slots[2].in_uop.bits.fp_ctrl.ldst, issue_slots[4].out_uop.fp_ctrl.ldst \n connect issue_slots[2].in_uop.bits.op2_sel, issue_slots[4].out_uop.op2_sel \n connect issue_slots[2].in_uop.bits.op1_sel, issue_slots[4].out_uop.op1_sel \n connect issue_slots[2].in_uop.bits.imm_packed, issue_slots[4].out_uop.imm_packed \n connect issue_slots[2].in_uop.bits.pimm, issue_slots[4].out_uop.pimm \n connect issue_slots[2].in_uop.bits.imm_sel, issue_slots[4].out_uop.imm_sel \n connect issue_slots[2].in_uop.bits.imm_rename, issue_slots[4].out_uop.imm_rename \n connect issue_slots[2].in_uop.bits.taken, issue_slots[4].out_uop.taken \n connect issue_slots[2].in_uop.bits.pc_lob, issue_slots[4].out_uop.pc_lob \n connect issue_slots[2].in_uop.bits.edge_inst, issue_slots[4].out_uop.edge_inst \n connect issue_slots[2].in_uop.bits.ftq_idx, issue_slots[4].out_uop.ftq_idx \n connect issue_slots[2].in_uop.bits.is_mov, issue_slots[4].out_uop.is_mov \n connect issue_slots[2].in_uop.bits.is_rocc, issue_slots[4].out_uop.is_rocc \n connect issue_slots[2].in_uop.bits.is_sys_pc2epc, issue_slots[4].out_uop.is_sys_pc2epc \n connect issue_slots[2].in_uop.bits.is_eret, issue_slots[4].out_uop.is_eret \n connect issue_slots[2].in_uop.bits.is_amo, issue_slots[4].out_uop.is_amo \n connect issue_slots[2].in_uop.bits.is_sfence, issue_slots[4].out_uop.is_sfence \n connect issue_slots[2].in_uop.bits.is_fencei, issue_slots[4].out_uop.is_fencei \n connect issue_slots[2].in_uop.bits.is_fence, issue_slots[4].out_uop.is_fence \n connect issue_slots[2].in_uop.bits.is_sfb, issue_slots[4].out_uop.is_sfb \n connect issue_slots[2].in_uop.bits.br_type, issue_slots[4].out_uop.br_type \n connect issue_slots[2].in_uop.bits.br_tag, issue_slots[4].out_uop.br_tag \n connect issue_slots[2].in_uop.bits.br_mask, issue_slots[4].out_uop.br_mask \n connect issue_slots[2].in_uop.bits.dis_col_sel, issue_slots[4].out_uop.dis_col_sel \n connect issue_slots[2].in_uop.bits.iw_p3_bypass_hint, issue_slots[4].out_uop.iw_p3_bypass_hint \n connect issue_slots[2].in_uop.bits.iw_p2_bypass_hint, issue_slots[4].out_uop.iw_p2_bypass_hint \n connect issue_slots[2].in_uop.bits.iw_p1_bypass_hint, issue_slots[4].out_uop.iw_p1_bypass_hint \n connect issue_slots[2].in_uop.bits.iw_p2_speculative_child, issue_slots[4].out_uop.iw_p2_speculative_child \n connect issue_slots[2].in_uop.bits.iw_p1_speculative_child, issue_slots[4].out_uop.iw_p1_speculative_child \n connect issue_slots[2].in_uop.bits.iw_issued_partial_dgen, issue_slots[4].out_uop.iw_issued_partial_dgen \n connect issue_slots[2].in_uop.bits.iw_issued_partial_agen, issue_slots[4].out_uop.iw_issued_partial_agen \n connect issue_slots[2].in_uop.bits.iw_issued, issue_slots[4].out_uop.iw_issued \n connect issue_slots[2].in_uop.bits.fu_code[0], issue_slots[4].out_uop.fu_code[0] \n connect issue_slots[2].in_uop.bits.fu_code[1], issue_slots[4].out_uop.fu_code[1] \n connect issue_slots[2].in_uop.bits.fu_code[2], issue_slots[4].out_uop.fu_code[2] \n connect issue_slots[2].in_uop.bits.fu_code[3], issue_slots[4].out_uop.fu_code[3] \n connect issue_slots[2].in_uop.bits.fu_code[4], issue_slots[4].out_uop.fu_code[4] \n connect issue_slots[2].in_uop.bits.fu_code[5], issue_slots[4].out_uop.fu_code[5] \n connect issue_slots[2].in_uop.bits.fu_code[6], issue_slots[4].out_uop.fu_code[6] \n connect issue_slots[2].in_uop.bits.fu_code[7], issue_slots[4].out_uop.fu_code[7] \n connect issue_slots[2].in_uop.bits.fu_code[8], issue_slots[4].out_uop.fu_code[8] \n connect issue_slots[2].in_uop.bits.fu_code[9], issue_slots[4].out_uop.fu_code[9] \n connect issue_slots[2].in_uop.bits.iq_type[0], issue_slots[4].out_uop.iq_type[0] \n connect issue_slots[2].in_uop.bits.iq_type[1], issue_slots[4].out_uop.iq_type[1] \n connect issue_slots[2].in_uop.bits.iq_type[2], issue_slots[4].out_uop.iq_type[2] \n connect issue_slots[2].in_uop.bits.iq_type[3], issue_slots[4].out_uop.iq_type[3] \n connect issue_slots[2].in_uop.bits.debug_pc, issue_slots[4].out_uop.debug_pc \n connect issue_slots[2].in_uop.bits.is_rvc, issue_slots[4].out_uop.is_rvc \n connect issue_slots[2].in_uop.bits.debug_inst, issue_slots[4].out_uop.debug_inst \n connect issue_slots[2].in_uop.bits.inst, issue_slots[4].out_uop.inst \n node _issue_slots_2_clear_T = neq(shamts_oh[2], UInt<1>(0h0)) \n connect issue_slots[2].clear, _issue_slots_2_clear_T \n connect issue_slots[3].in_uop.valid, UInt<1>(0h0) \n connect issue_slots[3].in_uop.bits.debug_tsrc, issue_slots[4].out_uop.debug_tsrc \n connect issue_slots[3].in_uop.bits.debug_fsrc, issue_slots[4].out_uop.debug_fsrc \n connect issue_slots[3].in_uop.bits.bp_xcpt_if, issue_slots[4].out_uop.bp_xcpt_if \n connect issue_slots[3].in_uop.bits.bp_debug_if, issue_slots[4].out_uop.bp_debug_if \n connect issue_slots[3].in_uop.bits.xcpt_ma_if, issue_slots[4].out_uop.xcpt_ma_if \n connect issue_slots[3].in_uop.bits.xcpt_ae_if, issue_slots[4].out_uop.xcpt_ae_if \n connect issue_slots[3].in_uop.bits.xcpt_pf_if, issue_slots[4].out_uop.xcpt_pf_if \n connect issue_slots[3].in_uop.bits.fp_typ, issue_slots[4].out_uop.fp_typ \n connect issue_slots[3].in_uop.bits.fp_rm, issue_slots[4].out_uop.fp_rm \n connect issue_slots[3].in_uop.bits.fp_val, issue_slots[4].out_uop.fp_val \n connect issue_slots[3].in_uop.bits.fcn_op, issue_slots[4].out_uop.fcn_op \n connect issue_slots[3].in_uop.bits.fcn_dw, issue_slots[4].out_uop.fcn_dw \n connect issue_slots[3].in_uop.bits.frs3_en, issue_slots[4].out_uop.frs3_en \n connect issue_slots[3].in_uop.bits.lrs2_rtype, issue_slots[4].out_uop.lrs2_rtype \n connect issue_slots[3].in_uop.bits.lrs1_rtype, issue_slots[4].out_uop.lrs1_rtype \n connect issue_slots[3].in_uop.bits.dst_rtype, issue_slots[4].out_uop.dst_rtype \n connect issue_slots[3].in_uop.bits.lrs3, issue_slots[4].out_uop.lrs3 \n connect issue_slots[3].in_uop.bits.lrs2, issue_slots[4].out_uop.lrs2 \n connect issue_slots[3].in_uop.bits.lrs1, issue_slots[4].out_uop.lrs1 \n connect issue_slots[3].in_uop.bits.ldst, issue_slots[4].out_uop.ldst \n connect issue_slots[3].in_uop.bits.ldst_is_rs1, issue_slots[4].out_uop.ldst_is_rs1 \n connect issue_slots[3].in_uop.bits.csr_cmd, issue_slots[4].out_uop.csr_cmd \n connect issue_slots[3].in_uop.bits.flush_on_commit, issue_slots[4].out_uop.flush_on_commit \n connect issue_slots[3].in_uop.bits.is_unique, issue_slots[4].out_uop.is_unique \n connect issue_slots[3].in_uop.bits.uses_stq, issue_slots[4].out_uop.uses_stq \n connect issue_slots[3].in_uop.bits.uses_ldq, issue_slots[4].out_uop.uses_ldq \n connect issue_slots[3].in_uop.bits.mem_signed, issue_slots[4].out_uop.mem_signed \n connect issue_slots[3].in_uop.bits.mem_size, issue_slots[4].out_uop.mem_size \n connect issue_slots[3].in_uop.bits.mem_cmd, issue_slots[4].out_uop.mem_cmd \n connect issue_slots[3].in_uop.bits.exc_cause, issue_slots[4].out_uop.exc_cause \n connect issue_slots[3].in_uop.bits.exception, issue_slots[4].out_uop.exception \n connect issue_slots[3].in_uop.bits.stale_pdst, issue_slots[4].out_uop.stale_pdst \n connect issue_slots[3].in_uop.bits.ppred_busy, issue_slots[4].out_uop.ppred_busy \n connect issue_slots[3].in_uop.bits.prs3_busy, issue_slots[4].out_uop.prs3_busy \n connect issue_slots[3].in_uop.bits.prs2_busy, issue_slots[4].out_uop.prs2_busy \n connect issue_slots[3].in_uop.bits.prs1_busy, issue_slots[4].out_uop.prs1_busy \n connect issue_slots[3].in_uop.bits.ppred, issue_slots[4].out_uop.ppred \n connect issue_slots[3].in_uop.bits.prs3, issue_slots[4].out_uop.prs3 \n connect issue_slots[3].in_uop.bits.prs2, issue_slots[4].out_uop.prs2 \n connect issue_slots[3].in_uop.bits.prs1, issue_slots[4].out_uop.prs1 \n connect issue_slots[3].in_uop.bits.pdst, issue_slots[4].out_uop.pdst \n connect issue_slots[3].in_uop.bits.rxq_idx, issue_slots[4].out_uop.rxq_idx \n connect issue_slots[3].in_uop.bits.stq_idx, issue_slots[4].out_uop.stq_idx \n connect issue_slots[3].in_uop.bits.ldq_idx, issue_slots[4].out_uop.ldq_idx \n connect issue_slots[3].in_uop.bits.rob_idx, issue_slots[4].out_uop.rob_idx \n connect issue_slots[3].in_uop.bits.fp_ctrl.vec, issue_slots[4].out_uop.fp_ctrl.vec \n connect issue_slots[3].in_uop.bits.fp_ctrl.wflags, issue_slots[4].out_uop.fp_ctrl.wflags \n connect issue_slots[3].in_uop.bits.fp_ctrl.sqrt, issue_slots[4].out_uop.fp_ctrl.sqrt \n connect issue_slots[3].in_uop.bits.fp_ctrl.div, issue_slots[4].out_uop.fp_ctrl.div \n connect issue_slots[3].in_uop.bits.fp_ctrl.fma, issue_slots[4].out_uop.fp_ctrl.fma \n connect issue_slots[3].in_uop.bits.fp_ctrl.fastpipe, issue_slots[4].out_uop.fp_ctrl.fastpipe \n connect issue_slots[3].in_uop.bits.fp_ctrl.toint, issue_slots[4].out_uop.fp_ctrl.toint \n connect issue_slots[3].in_uop.bits.fp_ctrl.fromint, issue_slots[4].out_uop.fp_ctrl.fromint \n connect issue_slots[3].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[4].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[3].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[4].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[3].in_uop.bits.fp_ctrl.swap23, issue_slots[4].out_uop.fp_ctrl.swap23 \n connect issue_slots[3].in_uop.bits.fp_ctrl.swap12, issue_slots[4].out_uop.fp_ctrl.swap12 \n connect issue_slots[3].in_uop.bits.fp_ctrl.ren3, issue_slots[4].out_uop.fp_ctrl.ren3 \n connect issue_slots[3].in_uop.bits.fp_ctrl.ren2, issue_slots[4].out_uop.fp_ctrl.ren2 \n connect issue_slots[3].in_uop.bits.fp_ctrl.ren1, issue_slots[4].out_uop.fp_ctrl.ren1 \n connect issue_slots[3].in_uop.bits.fp_ctrl.wen, issue_slots[4].out_uop.fp_ctrl.wen \n connect issue_slots[3].in_uop.bits.fp_ctrl.ldst, issue_slots[4].out_uop.fp_ctrl.ldst \n connect issue_slots[3].in_uop.bits.op2_sel, issue_slots[4].out_uop.op2_sel \n connect issue_slots[3].in_uop.bits.op1_sel, issue_slots[4].out_uop.op1_sel \n connect issue_slots[3].in_uop.bits.imm_packed, issue_slots[4].out_uop.imm_packed \n connect issue_slots[3].in_uop.bits.pimm, issue_slots[4].out_uop.pimm \n connect issue_slots[3].in_uop.bits.imm_sel, issue_slots[4].out_uop.imm_sel \n connect issue_slots[3].in_uop.bits.imm_rename, issue_slots[4].out_uop.imm_rename \n connect issue_slots[3].in_uop.bits.taken, issue_slots[4].out_uop.taken \n connect issue_slots[3].in_uop.bits.pc_lob, issue_slots[4].out_uop.pc_lob \n connect issue_slots[3].in_uop.bits.edge_inst, issue_slots[4].out_uop.edge_inst \n connect issue_slots[3].in_uop.bits.ftq_idx, issue_slots[4].out_uop.ftq_idx \n connect issue_slots[3].in_uop.bits.is_mov, issue_slots[4].out_uop.is_mov \n connect issue_slots[3].in_uop.bits.is_rocc, issue_slots[4].out_uop.is_rocc \n connect issue_slots[3].in_uop.bits.is_sys_pc2epc, issue_slots[4].out_uop.is_sys_pc2epc \n connect issue_slots[3].in_uop.bits.is_eret, issue_slots[4].out_uop.is_eret \n connect issue_slots[3].in_uop.bits.is_amo, issue_slots[4].out_uop.is_amo \n connect issue_slots[3].in_uop.bits.is_sfence, issue_slots[4].out_uop.is_sfence \n connect issue_slots[3].in_uop.bits.is_fencei, issue_slots[4].out_uop.is_fencei \n connect issue_slots[3].in_uop.bits.is_fence, issue_slots[4].out_uop.is_fence \n connect issue_slots[3].in_uop.bits.is_sfb, issue_slots[4].out_uop.is_sfb \n connect issue_slots[3].in_uop.bits.br_type, issue_slots[4].out_uop.br_type \n connect issue_slots[3].in_uop.bits.br_tag, issue_slots[4].out_uop.br_tag \n connect issue_slots[3].in_uop.bits.br_mask, issue_slots[4].out_uop.br_mask \n connect issue_slots[3].in_uop.bits.dis_col_sel, issue_slots[4].out_uop.dis_col_sel \n connect issue_slots[3].in_uop.bits.iw_p3_bypass_hint, issue_slots[4].out_uop.iw_p3_bypass_hint \n connect issue_slots[3].in_uop.bits.iw_p2_bypass_hint, issue_slots[4].out_uop.iw_p2_bypass_hint \n connect issue_slots[3].in_uop.bits.iw_p1_bypass_hint, issue_slots[4].out_uop.iw_p1_bypass_hint \n connect issue_slots[3].in_uop.bits.iw_p2_speculative_child, issue_slots[4].out_uop.iw_p2_speculative_child \n connect issue_slots[3].in_uop.bits.iw_p1_speculative_child, issue_slots[4].out_uop.iw_p1_speculative_child \n connect issue_slots[3].in_uop.bits.iw_issued_partial_dgen, issue_slots[4].out_uop.iw_issued_partial_dgen \n connect issue_slots[3].in_uop.bits.iw_issued_partial_agen, issue_slots[4].out_uop.iw_issued_partial_agen \n connect issue_slots[3].in_uop.bits.iw_issued, issue_slots[4].out_uop.iw_issued \n connect issue_slots[3].in_uop.bits.fu_code[0], issue_slots[4].out_uop.fu_code[0] \n connect issue_slots[3].in_uop.bits.fu_code[1], issue_slots[4].out_uop.fu_code[1] \n connect issue_slots[3].in_uop.bits.fu_code[2], issue_slots[4].out_uop.fu_code[2] \n connect issue_slots[3].in_uop.bits.fu_code[3], issue_slots[4].out_uop.fu_code[3] \n connect issue_slots[3].in_uop.bits.fu_code[4], issue_slots[4].out_uop.fu_code[4] \n connect issue_slots[3].in_uop.bits.fu_code[5], issue_slots[4].out_uop.fu_code[5] \n connect issue_slots[3].in_uop.bits.fu_code[6], issue_slots[4].out_uop.fu_code[6] \n connect issue_slots[3].in_uop.bits.fu_code[7], issue_slots[4].out_uop.fu_code[7] \n connect issue_slots[3].in_uop.bits.fu_code[8], issue_slots[4].out_uop.fu_code[8] \n connect issue_slots[3].in_uop.bits.fu_code[9], issue_slots[4].out_uop.fu_code[9] \n connect issue_slots[3].in_uop.bits.iq_type[0], issue_slots[4].out_uop.iq_type[0] \n connect issue_slots[3].in_uop.bits.iq_type[1], issue_slots[4].out_uop.iq_type[1] \n connect issue_slots[3].in_uop.bits.iq_type[2], issue_slots[4].out_uop.iq_type[2] \n connect issue_slots[3].in_uop.bits.iq_type[3], issue_slots[4].out_uop.iq_type[3] \n connect issue_slots[3].in_uop.bits.debug_pc, issue_slots[4].out_uop.debug_pc \n connect issue_slots[3].in_uop.bits.is_rvc, issue_slots[4].out_uop.is_rvc \n connect issue_slots[3].in_uop.bits.debug_inst, issue_slots[4].out_uop.debug_inst \n connect issue_slots[3].in_uop.bits.inst, issue_slots[4].out_uop.inst \n node _T_168 = eq(shamts_oh[4], UInt<1>(0h1)) \n when _T_168 : \n connect issue_slots[3].in_uop.valid, issue_slots[4].will_be_valid \n connect issue_slots[3].in_uop.bits.debug_tsrc, issue_slots[4].out_uop.debug_tsrc \n connect issue_slots[3].in_uop.bits.debug_fsrc, issue_slots[4].out_uop.debug_fsrc \n connect issue_slots[3].in_uop.bits.bp_xcpt_if, issue_slots[4].out_uop.bp_xcpt_if \n connect issue_slots[3].in_uop.bits.bp_debug_if, issue_slots[4].out_uop.bp_debug_if \n connect issue_slots[3].in_uop.bits.xcpt_ma_if, issue_slots[4].out_uop.xcpt_ma_if \n connect issue_slots[3].in_uop.bits.xcpt_ae_if, issue_slots[4].out_uop.xcpt_ae_if \n connect issue_slots[3].in_uop.bits.xcpt_pf_if, issue_slots[4].out_uop.xcpt_pf_if \n connect issue_slots[3].in_uop.bits.fp_typ, issue_slots[4].out_uop.fp_typ \n connect issue_slots[3].in_uop.bits.fp_rm, issue_slots[4].out_uop.fp_rm \n connect issue_slots[3].in_uop.bits.fp_val, issue_slots[4].out_uop.fp_val \n connect issue_slots[3].in_uop.bits.fcn_op, issue_slots[4].out_uop.fcn_op \n connect issue_slots[3].in_uop.bits.fcn_dw, issue_slots[4].out_uop.fcn_dw \n connect issue_slots[3].in_uop.bits.frs3_en, issue_slots[4].out_uop.frs3_en \n connect issue_slots[3].in_uop.bits.lrs2_rtype, issue_slots[4].out_uop.lrs2_rtype \n connect issue_slots[3].in_uop.bits.lrs1_rtype, issue_slots[4].out_uop.lrs1_rtype \n connect issue_slots[3].in_uop.bits.dst_rtype, issue_slots[4].out_uop.dst_rtype \n connect issue_slots[3].in_uop.bits.lrs3, issue_slots[4].out_uop.lrs3 \n connect issue_slots[3].in_uop.bits.lrs2, issue_slots[4].out_uop.lrs2 \n connect issue_slots[3].in_uop.bits.lrs1, issue_slots[4].out_uop.lrs1 \n connect issue_slots[3].in_uop.bits.ldst, issue_slots[4].out_uop.ldst \n connect issue_slots[3].in_uop.bits.ldst_is_rs1, issue_slots[4].out_uop.ldst_is_rs1 \n connect issue_slots[3].in_uop.bits.csr_cmd, issue_slots[4].out_uop.csr_cmd \n connect issue_slots[3].in_uop.bits.flush_on_commit, issue_slots[4].out_uop.flush_on_commit \n connect issue_slots[3].in_uop.bits.is_unique, issue_slots[4].out_uop.is_unique \n connect issue_slots[3].in_uop.bits.uses_stq, issue_slots[4].out_uop.uses_stq \n connect issue_slots[3].in_uop.bits.uses_ldq, issue_slots[4].out_uop.uses_ldq \n connect issue_slots[3].in_uop.bits.mem_signed, issue_slots[4].out_uop.mem_signed \n connect issue_slots[3].in_uop.bits.mem_size, issue_slots[4].out_uop.mem_size \n connect issue_slots[3].in_uop.bits.mem_cmd, issue_slots[4].out_uop.mem_cmd \n connect issue_slots[3].in_uop.bits.exc_cause, issue_slots[4].out_uop.exc_cause \n connect issue_slots[3].in_uop.bits.exception, issue_slots[4].out_uop.exception \n connect issue_slots[3].in_uop.bits.stale_pdst, issue_slots[4].out_uop.stale_pdst \n connect issue_slots[3].in_uop.bits.ppred_busy, issue_slots[4].out_uop.ppred_busy \n connect issue_slots[3].in_uop.bits.prs3_busy, issue_slots[4].out_uop.prs3_busy \n connect issue_slots[3].in_uop.bits.prs2_busy, issue_slots[4].out_uop.prs2_busy \n connect issue_slots[3].in_uop.bits.prs1_busy, issue_slots[4].out_uop.prs1_busy \n connect issue_slots[3].in_uop.bits.ppred, issue_slots[4].out_uop.ppred \n connect issue_slots[3].in_uop.bits.prs3, issue_slots[4].out_uop.prs3 \n connect issue_slots[3].in_uop.bits.prs2, issue_slots[4].out_uop.prs2 \n connect issue_slots[3].in_uop.bits.prs1, issue_slots[4].out_uop.prs1 \n connect issue_slots[3].in_uop.bits.pdst, issue_slots[4].out_uop.pdst \n connect issue_slots[3].in_uop.bits.rxq_idx, issue_slots[4].out_uop.rxq_idx \n connect issue_slots[3].in_uop.bits.stq_idx, issue_slots[4].out_uop.stq_idx \n connect issue_slots[3].in_uop.bits.ldq_idx, issue_slots[4].out_uop.ldq_idx \n connect issue_slots[3].in_uop.bits.rob_idx, issue_slots[4].out_uop.rob_idx \n connect issue_slots[3].in_uop.bits.fp_ctrl.vec, issue_slots[4].out_uop.fp_ctrl.vec \n connect issue_slots[3].in_uop.bits.fp_ctrl.wflags, issue_slots[4].out_uop.fp_ctrl.wflags \n connect issue_slots[3].in_uop.bits.fp_ctrl.sqrt, issue_slots[4].out_uop.fp_ctrl.sqrt \n connect issue_slots[3].in_uop.bits.fp_ctrl.div, issue_slots[4].out_uop.fp_ctrl.div \n connect issue_slots[3].in_uop.bits.fp_ctrl.fma, issue_slots[4].out_uop.fp_ctrl.fma \n connect issue_slots[3].in_uop.bits.fp_ctrl.fastpipe, issue_slots[4].out_uop.fp_ctrl.fastpipe \n connect issue_slots[3].in_uop.bits.fp_ctrl.toint, issue_slots[4].out_uop.fp_ctrl.toint \n connect issue_slots[3].in_uop.bits.fp_ctrl.fromint, issue_slots[4].out_uop.fp_ctrl.fromint \n connect issue_slots[3].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[4].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[3].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[4].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[3].in_uop.bits.fp_ctrl.swap23, issue_slots[4].out_uop.fp_ctrl.swap23 \n connect issue_slots[3].in_uop.bits.fp_ctrl.swap12, issue_slots[4].out_uop.fp_ctrl.swap12 \n connect issue_slots[3].in_uop.bits.fp_ctrl.ren3, issue_slots[4].out_uop.fp_ctrl.ren3 \n connect issue_slots[3].in_uop.bits.fp_ctrl.ren2, issue_slots[4].out_uop.fp_ctrl.ren2 \n connect issue_slots[3].in_uop.bits.fp_ctrl.ren1, issue_slots[4].out_uop.fp_ctrl.ren1 \n connect issue_slots[3].in_uop.bits.fp_ctrl.wen, issue_slots[4].out_uop.fp_ctrl.wen \n connect issue_slots[3].in_uop.bits.fp_ctrl.ldst, issue_slots[4].out_uop.fp_ctrl.ldst \n connect issue_slots[3].in_uop.bits.op2_sel, issue_slots[4].out_uop.op2_sel \n connect issue_slots[3].in_uop.bits.op1_sel, issue_slots[4].out_uop.op1_sel \n connect issue_slots[3].in_uop.bits.imm_packed, issue_slots[4].out_uop.imm_packed \n connect issue_slots[3].in_uop.bits.pimm, issue_slots[4].out_uop.pimm \n connect issue_slots[3].in_uop.bits.imm_sel, issue_slots[4].out_uop.imm_sel \n connect issue_slots[3].in_uop.bits.imm_rename, issue_slots[4].out_uop.imm_rename \n connect issue_slots[3].in_uop.bits.taken, issue_slots[4].out_uop.taken \n connect issue_slots[3].in_uop.bits.pc_lob, issue_slots[4].out_uop.pc_lob \n connect issue_slots[3].in_uop.bits.edge_inst, issue_slots[4].out_uop.edge_inst \n connect issue_slots[3].in_uop.bits.ftq_idx, issue_slots[4].out_uop.ftq_idx \n connect issue_slots[3].in_uop.bits.is_mov, issue_slots[4].out_uop.is_mov \n connect issue_slots[3].in_uop.bits.is_rocc, issue_slots[4].out_uop.is_rocc \n connect issue_slots[3].in_uop.bits.is_sys_pc2epc, issue_slots[4].out_uop.is_sys_pc2epc \n connect issue_slots[3].in_uop.bits.is_eret, issue_slots[4].out_uop.is_eret \n connect issue_slots[3].in_uop.bits.is_amo, issue_slots[4].out_uop.is_amo \n connect issue_slots[3].in_uop.bits.is_sfence, issue_slots[4].out_uop.is_sfence \n connect issue_slots[3].in_uop.bits.is_fencei, issue_slots[4].out_uop.is_fencei \n connect issue_slots[3].in_uop.bits.is_fence, issue_slots[4].out_uop.is_fence \n connect issue_slots[3].in_uop.bits.is_sfb, issue_slots[4].out_uop.is_sfb \n connect issue_slots[3].in_uop.bits.br_type, issue_slots[4].out_uop.br_type \n connect issue_slots[3].in_uop.bits.br_tag, issue_slots[4].out_uop.br_tag \n connect issue_slots[3].in_uop.bits.br_mask, issue_slots[4].out_uop.br_mask \n connect issue_slots[3].in_uop.bits.dis_col_sel, issue_slots[4].out_uop.dis_col_sel \n connect issue_slots[3].in_uop.bits.iw_p3_bypass_hint, issue_slots[4].out_uop.iw_p3_bypass_hint \n connect issue_slots[3].in_uop.bits.iw_p2_bypass_hint, issue_slots[4].out_uop.iw_p2_bypass_hint \n connect issue_slots[3].in_uop.bits.iw_p1_bypass_hint, issue_slots[4].out_uop.iw_p1_bypass_hint \n connect issue_slots[3].in_uop.bits.iw_p2_speculative_child, issue_slots[4].out_uop.iw_p2_speculative_child \n connect issue_slots[3].in_uop.bits.iw_p1_speculative_child, issue_slots[4].out_uop.iw_p1_speculative_child \n connect issue_slots[3].in_uop.bits.iw_issued_partial_dgen, issue_slots[4].out_uop.iw_issued_partial_dgen \n connect issue_slots[3].in_uop.bits.iw_issued_partial_agen, issue_slots[4].out_uop.iw_issued_partial_agen \n connect issue_slots[3].in_uop.bits.iw_issued, issue_slots[4].out_uop.iw_issued \n connect issue_slots[3].in_uop.bits.fu_code[0], issue_slots[4].out_uop.fu_code[0] \n connect issue_slots[3].in_uop.bits.fu_code[1], issue_slots[4].out_uop.fu_code[1] \n connect issue_slots[3].in_uop.bits.fu_code[2], issue_slots[4].out_uop.fu_code[2] \n connect issue_slots[3].in_uop.bits.fu_code[3], issue_slots[4].out_uop.fu_code[3] \n connect issue_slots[3].in_uop.bits.fu_code[4], issue_slots[4].out_uop.fu_code[4] \n connect issue_slots[3].in_uop.bits.fu_code[5], issue_slots[4].out_uop.fu_code[5] \n connect issue_slots[3].in_uop.bits.fu_code[6], issue_slots[4].out_uop.fu_code[6] \n connect issue_slots[3].in_uop.bits.fu_code[7], issue_slots[4].out_uop.fu_code[7] \n connect issue_slots[3].in_uop.bits.fu_code[8], issue_slots[4].out_uop.fu_code[8] \n connect issue_slots[3].in_uop.bits.fu_code[9], issue_slots[4].out_uop.fu_code[9] \n connect issue_slots[3].in_uop.bits.iq_type[0], issue_slots[4].out_uop.iq_type[0] \n connect issue_slots[3].in_uop.bits.iq_type[1], issue_slots[4].out_uop.iq_type[1] \n connect issue_slots[3].in_uop.bits.iq_type[2], issue_slots[4].out_uop.iq_type[2] \n connect issue_slots[3].in_uop.bits.iq_type[3], issue_slots[4].out_uop.iq_type[3] \n connect issue_slots[3].in_uop.bits.debug_pc, issue_slots[4].out_uop.debug_pc \n connect issue_slots[3].in_uop.bits.is_rvc, issue_slots[4].out_uop.is_rvc \n connect issue_slots[3].in_uop.bits.debug_inst, issue_slots[4].out_uop.debug_inst \n connect issue_slots[3].in_uop.bits.inst, issue_slots[4].out_uop.inst \n node _T_169 = eq(shamts_oh[5], UInt<2>(0h2)) \n when _T_169 : \n connect issue_slots[3].in_uop.valid, issue_slots[5].will_be_valid \n connect issue_slots[3].in_uop.bits.debug_tsrc, issue_slots[5].out_uop.debug_tsrc \n connect issue_slots[3].in_uop.bits.debug_fsrc, issue_slots[5].out_uop.debug_fsrc \n connect issue_slots[3].in_uop.bits.bp_xcpt_if, issue_slots[5].out_uop.bp_xcpt_if \n connect issue_slots[3].in_uop.bits.bp_debug_if, issue_slots[5].out_uop.bp_debug_if \n connect issue_slots[3].in_uop.bits.xcpt_ma_if, issue_slots[5].out_uop.xcpt_ma_if \n connect issue_slots[3].in_uop.bits.xcpt_ae_if, issue_slots[5].out_uop.xcpt_ae_if \n connect issue_slots[3].in_uop.bits.xcpt_pf_if, issue_slots[5].out_uop.xcpt_pf_if \n connect issue_slots[3].in_uop.bits.fp_typ, issue_slots[5].out_uop.fp_typ \n connect issue_slots[3].in_uop.bits.fp_rm, issue_slots[5].out_uop.fp_rm \n connect issue_slots[3].in_uop.bits.fp_val, issue_slots[5].out_uop.fp_val \n connect issue_slots[3].in_uop.bits.fcn_op, issue_slots[5].out_uop.fcn_op \n connect issue_slots[3].in_uop.bits.fcn_dw, issue_slots[5].out_uop.fcn_dw \n connect issue_slots[3].in_uop.bits.frs3_en, issue_slots[5].out_uop.frs3_en \n connect issue_slots[3].in_uop.bits.lrs2_rtype, issue_slots[5].out_uop.lrs2_rtype \n connect issue_slots[3].in_uop.bits.lrs1_rtype, issue_slots[5].out_uop.lrs1_rtype \n connect issue_slots[3].in_uop.bits.dst_rtype, issue_slots[5].out_uop.dst_rtype \n connect issue_slots[3].in_uop.bits.lrs3, issue_slots[5].out_uop.lrs3 \n connect issue_slots[3].in_uop.bits.lrs2, issue_slots[5].out_uop.lrs2 \n connect issue_slots[3].in_uop.bits.lrs1, issue_slots[5].out_uop.lrs1 \n connect issue_slots[3].in_uop.bits.ldst, issue_slots[5].out_uop.ldst \n connect issue_slots[3].in_uop.bits.ldst_is_rs1, issue_slots[5].out_uop.ldst_is_rs1 \n connect issue_slots[3].in_uop.bits.csr_cmd, issue_slots[5].out_uop.csr_cmd \n connect issue_slots[3].in_uop.bits.flush_on_commit, issue_slots[5].out_uop.flush_on_commit \n connect issue_slots[3].in_uop.bits.is_unique, issue_slots[5].out_uop.is_unique \n connect issue_slots[3].in_uop.bits.uses_stq, issue_slots[5].out_uop.uses_stq \n connect issue_slots[3].in_uop.bits.uses_ldq, issue_slots[5].out_uop.uses_ldq \n connect issue_slots[3].in_uop.bits.mem_signed, issue_slots[5].out_uop.mem_signed \n connect issue_slots[3].in_uop.bits.mem_size, issue_slots[5].out_uop.mem_size \n connect issue_slots[3].in_uop.bits.mem_cmd, issue_slots[5].out_uop.mem_cmd \n connect issue_slots[3].in_uop.bits.exc_cause, issue_slots[5].out_uop.exc_cause \n connect issue_slots[3].in_uop.bits.exception, issue_slots[5].out_uop.exception \n connect issue_slots[3].in_uop.bits.stale_pdst, issue_slots[5].out_uop.stale_pdst \n connect issue_slots[3].in_uop.bits.ppred_busy, issue_slots[5].out_uop.ppred_busy \n connect issue_slots[3].in_uop.bits.prs3_busy, issue_slots[5].out_uop.prs3_busy \n connect issue_slots[3].in_uop.bits.prs2_busy, issue_slots[5].out_uop.prs2_busy \n connect issue_slots[3].in_uop.bits.prs1_busy, issue_slots[5].out_uop.prs1_busy \n connect issue_slots[3].in_uop.bits.ppred, issue_slots[5].out_uop.ppred \n connect issue_slots[3].in_uop.bits.prs3, issue_slots[5].out_uop.prs3 \n connect issue_slots[3].in_uop.bits.prs2, issue_slots[5].out_uop.prs2 \n connect issue_slots[3].in_uop.bits.prs1, issue_slots[5].out_uop.prs1 \n connect issue_slots[3].in_uop.bits.pdst, issue_slots[5].out_uop.pdst \n connect issue_slots[3].in_uop.bits.rxq_idx, issue_slots[5].out_uop.rxq_idx \n connect issue_slots[3].in_uop.bits.stq_idx, issue_slots[5].out_uop.stq_idx \n connect issue_slots[3].in_uop.bits.ldq_idx, issue_slots[5].out_uop.ldq_idx \n connect issue_slots[3].in_uop.bits.rob_idx, issue_slots[5].out_uop.rob_idx \n connect issue_slots[3].in_uop.bits.fp_ctrl.vec, issue_slots[5].out_uop.fp_ctrl.vec \n connect issue_slots[3].in_uop.bits.fp_ctrl.wflags, issue_slots[5].out_uop.fp_ctrl.wflags \n connect issue_slots[3].in_uop.bits.fp_ctrl.sqrt, issue_slots[5].out_uop.fp_ctrl.sqrt \n connect issue_slots[3].in_uop.bits.fp_ctrl.div, issue_slots[5].out_uop.fp_ctrl.div \n connect issue_slots[3].in_uop.bits.fp_ctrl.fma, issue_slots[5].out_uop.fp_ctrl.fma \n connect issue_slots[3].in_uop.bits.fp_ctrl.fastpipe, issue_slots[5].out_uop.fp_ctrl.fastpipe \n connect issue_slots[3].in_uop.bits.fp_ctrl.toint, issue_slots[5].out_uop.fp_ctrl.toint \n connect issue_slots[3].in_uop.bits.fp_ctrl.fromint, issue_slots[5].out_uop.fp_ctrl.fromint \n connect issue_slots[3].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[5].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[3].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[5].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[3].in_uop.bits.fp_ctrl.swap23, issue_slots[5].out_uop.fp_ctrl.swap23 \n connect issue_slots[3].in_uop.bits.fp_ctrl.swap12, issue_slots[5].out_uop.fp_ctrl.swap12 \n connect issue_slots[3].in_uop.bits.fp_ctrl.ren3, issue_slots[5].out_uop.fp_ctrl.ren3 \n connect issue_slots[3].in_uop.bits.fp_ctrl.ren2, issue_slots[5].out_uop.fp_ctrl.ren2 \n connect issue_slots[3].in_uop.bits.fp_ctrl.ren1, issue_slots[5].out_uop.fp_ctrl.ren1 \n connect issue_slots[3].in_uop.bits.fp_ctrl.wen, issue_slots[5].out_uop.fp_ctrl.wen \n connect issue_slots[3].in_uop.bits.fp_ctrl.ldst, issue_slots[5].out_uop.fp_ctrl.ldst \n connect issue_slots[3].in_uop.bits.op2_sel, issue_slots[5].out_uop.op2_sel \n connect issue_slots[3].in_uop.bits.op1_sel, issue_slots[5].out_uop.op1_sel \n connect issue_slots[3].in_uop.bits.imm_packed, issue_slots[5].out_uop.imm_packed \n connect issue_slots[3].in_uop.bits.pimm, issue_slots[5].out_uop.pimm \n connect issue_slots[3].in_uop.bits.imm_sel, issue_slots[5].out_uop.imm_sel \n connect issue_slots[3].in_uop.bits.imm_rename, issue_slots[5].out_uop.imm_rename \n connect issue_slots[3].in_uop.bits.taken, issue_slots[5].out_uop.taken \n connect issue_slots[3].in_uop.bits.pc_lob, issue_slots[5].out_uop.pc_lob \n connect issue_slots[3].in_uop.bits.edge_inst, issue_slots[5].out_uop.edge_inst \n connect issue_slots[3].in_uop.bits.ftq_idx, issue_slots[5].out_uop.ftq_idx \n connect issue_slots[3].in_uop.bits.is_mov, issue_slots[5].out_uop.is_mov \n connect issue_slots[3].in_uop.bits.is_rocc, issue_slots[5].out_uop.is_rocc \n connect issue_slots[3].in_uop.bits.is_sys_pc2epc, issue_slots[5].out_uop.is_sys_pc2epc \n connect issue_slots[3].in_uop.bits.is_eret, issue_slots[5].out_uop.is_eret \n connect issue_slots[3].in_uop.bits.is_amo, issue_slots[5].out_uop.is_amo \n connect issue_slots[3].in_uop.bits.is_sfence, issue_slots[5].out_uop.is_sfence \n connect issue_slots[3].in_uop.bits.is_fencei, issue_slots[5].out_uop.is_fencei \n connect issue_slots[3].in_uop.bits.is_fence, issue_slots[5].out_uop.is_fence \n connect issue_slots[3].in_uop.bits.is_sfb, issue_slots[5].out_uop.is_sfb \n connect issue_slots[3].in_uop.bits.br_type, issue_slots[5].out_uop.br_type \n connect issue_slots[3].in_uop.bits.br_tag, issue_slots[5].out_uop.br_tag \n connect issue_slots[3].in_uop.bits.br_mask, issue_slots[5].out_uop.br_mask \n connect issue_slots[3].in_uop.bits.dis_col_sel, issue_slots[5].out_uop.dis_col_sel \n connect issue_slots[3].in_uop.bits.iw_p3_bypass_hint, issue_slots[5].out_uop.iw_p3_bypass_hint \n connect issue_slots[3].in_uop.bits.iw_p2_bypass_hint, issue_slots[5].out_uop.iw_p2_bypass_hint \n connect issue_slots[3].in_uop.bits.iw_p1_bypass_hint, issue_slots[5].out_uop.iw_p1_bypass_hint \n connect issue_slots[3].in_uop.bits.iw_p2_speculative_child, issue_slots[5].out_uop.iw_p2_speculative_child \n connect issue_slots[3].in_uop.bits.iw_p1_speculative_child, issue_slots[5].out_uop.iw_p1_speculative_child \n connect issue_slots[3].in_uop.bits.iw_issued_partial_dgen, issue_slots[5].out_uop.iw_issued_partial_dgen \n connect issue_slots[3].in_uop.bits.iw_issued_partial_agen, issue_slots[5].out_uop.iw_issued_partial_agen \n connect issue_slots[3].in_uop.bits.iw_issued, issue_slots[5].out_uop.iw_issued \n connect issue_slots[3].in_uop.bits.fu_code[0], issue_slots[5].out_uop.fu_code[0] \n connect issue_slots[3].in_uop.bits.fu_code[1], issue_slots[5].out_uop.fu_code[1] \n connect issue_slots[3].in_uop.bits.fu_code[2], issue_slots[5].out_uop.fu_code[2] \n connect issue_slots[3].in_uop.bits.fu_code[3], issue_slots[5].out_uop.fu_code[3] \n connect issue_slots[3].in_uop.bits.fu_code[4], issue_slots[5].out_uop.fu_code[4] \n connect issue_slots[3].in_uop.bits.fu_code[5], issue_slots[5].out_uop.fu_code[5] \n connect issue_slots[3].in_uop.bits.fu_code[6], issue_slots[5].out_uop.fu_code[6] \n connect issue_slots[3].in_uop.bits.fu_code[7], issue_slots[5].out_uop.fu_code[7] \n connect issue_slots[3].in_uop.bits.fu_code[8], issue_slots[5].out_uop.fu_code[8] \n connect issue_slots[3].in_uop.bits.fu_code[9], issue_slots[5].out_uop.fu_code[9] \n connect issue_slots[3].in_uop.bits.iq_type[0], issue_slots[5].out_uop.iq_type[0] \n connect issue_slots[3].in_uop.bits.iq_type[1], issue_slots[5].out_uop.iq_type[1] \n connect issue_slots[3].in_uop.bits.iq_type[2], issue_slots[5].out_uop.iq_type[2] \n connect issue_slots[3].in_uop.bits.iq_type[3], issue_slots[5].out_uop.iq_type[3] \n connect issue_slots[3].in_uop.bits.debug_pc, issue_slots[5].out_uop.debug_pc \n connect issue_slots[3].in_uop.bits.is_rvc, issue_slots[5].out_uop.is_rvc \n connect issue_slots[3].in_uop.bits.debug_inst, issue_slots[5].out_uop.debug_inst \n connect issue_slots[3].in_uop.bits.inst, issue_slots[5].out_uop.inst \n node _issue_slots_3_clear_T = neq(shamts_oh[3], UInt<1>(0h0)) \n connect issue_slots[3].clear, _issue_slots_3_clear_T \n connect issue_slots[4].in_uop.valid, UInt<1>(0h0) \n connect issue_slots[4].in_uop.bits.debug_tsrc, issue_slots[5].out_uop.debug_tsrc \n connect issue_slots[4].in_uop.bits.debug_fsrc, issue_slots[5].out_uop.debug_fsrc \n connect issue_slots[4].in_uop.bits.bp_xcpt_if, issue_slots[5].out_uop.bp_xcpt_if \n connect issue_slots[4].in_uop.bits.bp_debug_if, issue_slots[5].out_uop.bp_debug_if \n connect issue_slots[4].in_uop.bits.xcpt_ma_if, issue_slots[5].out_uop.xcpt_ma_if \n connect issue_slots[4].in_uop.bits.xcpt_ae_if, issue_slots[5].out_uop.xcpt_ae_if \n connect issue_slots[4].in_uop.bits.xcpt_pf_if, issue_slots[5].out_uop.xcpt_pf_if \n connect issue_slots[4].in_uop.bits.fp_typ, issue_slots[5].out_uop.fp_typ \n connect issue_slots[4].in_uop.bits.fp_rm, issue_slots[5].out_uop.fp_rm \n connect issue_slots[4].in_uop.bits.fp_val, issue_slots[5].out_uop.fp_val \n connect issue_slots[4].in_uop.bits.fcn_op, issue_slots[5].out_uop.fcn_op \n connect issue_slots[4].in_uop.bits.fcn_dw, issue_slots[5].out_uop.fcn_dw \n connect issue_slots[4].in_uop.bits.frs3_en, issue_slots[5].out_uop.frs3_en \n connect issue_slots[4].in_uop.bits.lrs2_rtype, issue_slots[5].out_uop.lrs2_rtype \n connect issue_slots[4].in_uop.bits.lrs1_rtype, issue_slots[5].out_uop.lrs1_rtype \n connect issue_slots[4].in_uop.bits.dst_rtype, issue_slots[5].out_uop.dst_rtype \n connect issue_slots[4].in_uop.bits.lrs3, issue_slots[5].out_uop.lrs3 \n connect issue_slots[4].in_uop.bits.lrs2, issue_slots[5].out_uop.lrs2 \n connect issue_slots[4].in_uop.bits.lrs1, issue_slots[5].out_uop.lrs1 \n connect issue_slots[4].in_uop.bits.ldst, issue_slots[5].out_uop.ldst \n connect issue_slots[4].in_uop.bits.ldst_is_rs1, issue_slots[5].out_uop.ldst_is_rs1 \n connect issue_slots[4].in_uop.bits.csr_cmd, issue_slots[5].out_uop.csr_cmd \n connect issue_slots[4].in_uop.bits.flush_on_commit, issue_slots[5].out_uop.flush_on_commit \n connect issue_slots[4].in_uop.bits.is_unique, issue_slots[5].out_uop.is_unique \n connect issue_slots[4].in_uop.bits.uses_stq, issue_slots[5].out_uop.uses_stq \n connect issue_slots[4].in_uop.bits.uses_ldq, issue_slots[5].out_uop.uses_ldq \n connect issue_slots[4].in_uop.bits.mem_signed, issue_slots[5].out_uop.mem_signed \n connect issue_slots[4].in_uop.bits.mem_size, issue_slots[5].out_uop.mem_size \n connect issue_slots[4].in_uop.bits.mem_cmd, issue_slots[5].out_uop.mem_cmd \n connect issue_slots[4].in_uop.bits.exc_cause, issue_slots[5].out_uop.exc_cause \n connect issue_slots[4].in_uop.bits.exception, issue_slots[5].out_uop.exception \n connect issue_slots[4].in_uop.bits.stale_pdst, issue_slots[5].out_uop.stale_pdst \n connect issue_slots[4].in_uop.bits.ppred_busy, issue_slots[5].out_uop.ppred_busy \n connect issue_slots[4].in_uop.bits.prs3_busy, issue_slots[5].out_uop.prs3_busy \n connect issue_slots[4].in_uop.bits.prs2_busy, issue_slots[5].out_uop.prs2_busy \n connect issue_slots[4].in_uop.bits.prs1_busy, issue_slots[5].out_uop.prs1_busy \n connect issue_slots[4].in_uop.bits.ppred, issue_slots[5].out_uop.ppred \n connect issue_slots[4].in_uop.bits.prs3, issue_slots[5].out_uop.prs3 \n connect issue_slots[4].in_uop.bits.prs2, issue_slots[5].out_uop.prs2 \n connect issue_slots[4].in_uop.bits.prs1, issue_slots[5].out_uop.prs1 \n connect issue_slots[4].in_uop.bits.pdst, issue_slots[5].out_uop.pdst \n connect issue_slots[4].in_uop.bits.rxq_idx, issue_slots[5].out_uop.rxq_idx \n connect issue_slots[4].in_uop.bits.stq_idx, issue_slots[5].out_uop.stq_idx \n connect issue_slots[4].in_uop.bits.ldq_idx, issue_slots[5].out_uop.ldq_idx \n connect issue_slots[4].in_uop.bits.rob_idx, issue_slots[5].out_uop.rob_idx \n connect issue_slots[4].in_uop.bits.fp_ctrl.vec, issue_slots[5].out_uop.fp_ctrl.vec \n connect issue_slots[4].in_uop.bits.fp_ctrl.wflags, issue_slots[5].out_uop.fp_ctrl.wflags \n connect issue_slots[4].in_uop.bits.fp_ctrl.sqrt, issue_slots[5].out_uop.fp_ctrl.sqrt \n connect issue_slots[4].in_uop.bits.fp_ctrl.div, issue_slots[5].out_uop.fp_ctrl.div \n connect issue_slots[4].in_uop.bits.fp_ctrl.fma, issue_slots[5].out_uop.fp_ctrl.fma \n connect issue_slots[4].in_uop.bits.fp_ctrl.fastpipe, issue_slots[5].out_uop.fp_ctrl.fastpipe \n connect issue_slots[4].in_uop.bits.fp_ctrl.toint, issue_slots[5].out_uop.fp_ctrl.toint \n connect issue_slots[4].in_uop.bits.fp_ctrl.fromint, issue_slots[5].out_uop.fp_ctrl.fromint \n connect issue_slots[4].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[5].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[4].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[5].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[4].in_uop.bits.fp_ctrl.swap23, issue_slots[5].out_uop.fp_ctrl.swap23 \n connect issue_slots[4].in_uop.bits.fp_ctrl.swap12, issue_slots[5].out_uop.fp_ctrl.swap12 \n connect issue_slots[4].in_uop.bits.fp_ctrl.ren3, issue_slots[5].out_uop.fp_ctrl.ren3 \n connect issue_slots[4].in_uop.bits.fp_ctrl.ren2, issue_slots[5].out_uop.fp_ctrl.ren2 \n connect issue_slots[4].in_uop.bits.fp_ctrl.ren1, issue_slots[5].out_uop.fp_ctrl.ren1 \n connect issue_slots[4].in_uop.bits.fp_ctrl.wen, issue_slots[5].out_uop.fp_ctrl.wen \n connect issue_slots[4].in_uop.bits.fp_ctrl.ldst, issue_slots[5].out_uop.fp_ctrl.ldst \n connect issue_slots[4].in_uop.bits.op2_sel, issue_slots[5].out_uop.op2_sel \n connect issue_slots[4].in_uop.bits.op1_sel, issue_slots[5].out_uop.op1_sel \n connect issue_slots[4].in_uop.bits.imm_packed, issue_slots[5].out_uop.imm_packed \n connect issue_slots[4].in_uop.bits.pimm, issue_slots[5].out_uop.pimm \n connect issue_slots[4].in_uop.bits.imm_sel, issue_slots[5].out_uop.imm_sel \n connect issue_slots[4].in_uop.bits.imm_rename, issue_slots[5].out_uop.imm_rename \n connect issue_slots[4].in_uop.bits.taken, issue_slots[5].out_uop.taken \n connect issue_slots[4].in_uop.bits.pc_lob, issue_slots[5].out_uop.pc_lob \n connect issue_slots[4].in_uop.bits.edge_inst, issue_slots[5].out_uop.edge_inst \n connect issue_slots[4].in_uop.bits.ftq_idx, issue_slots[5].out_uop.ftq_idx \n connect issue_slots[4].in_uop.bits.is_mov, issue_slots[5].out_uop.is_mov \n connect issue_slots[4].in_uop.bits.is_rocc, issue_slots[5].out_uop.is_rocc \n connect issue_slots[4].in_uop.bits.is_sys_pc2epc, issue_slots[5].out_uop.is_sys_pc2epc \n connect issue_slots[4].in_uop.bits.is_eret, issue_slots[5].out_uop.is_eret \n connect issue_slots[4].in_uop.bits.is_amo, issue_slots[5].out_uop.is_amo \n connect issue_slots[4].in_uop.bits.is_sfence, issue_slots[5].out_uop.is_sfence \n connect issue_slots[4].in_uop.bits.is_fencei, issue_slots[5].out_uop.is_fencei \n connect issue_slots[4].in_uop.bits.is_fence, issue_slots[5].out_uop.is_fence \n connect issue_slots[4].in_uop.bits.is_sfb, issue_slots[5].out_uop.is_sfb \n connect issue_slots[4].in_uop.bits.br_type, issue_slots[5].out_uop.br_type \n connect issue_slots[4].in_uop.bits.br_tag, issue_slots[5].out_uop.br_tag \n connect issue_slots[4].in_uop.bits.br_mask, issue_slots[5].out_uop.br_mask \n connect issue_slots[4].in_uop.bits.dis_col_sel, issue_slots[5].out_uop.dis_col_sel \n connect issue_slots[4].in_uop.bits.iw_p3_bypass_hint, issue_slots[5].out_uop.iw_p3_bypass_hint \n connect issue_slots[4].in_uop.bits.iw_p2_bypass_hint, issue_slots[5].out_uop.iw_p2_bypass_hint \n connect issue_slots[4].in_uop.bits.iw_p1_bypass_hint, issue_slots[5].out_uop.iw_p1_bypass_hint \n connect issue_slots[4].in_uop.bits.iw_p2_speculative_child, issue_slots[5].out_uop.iw_p2_speculative_child \n connect issue_slots[4].in_uop.bits.iw_p1_speculative_child, issue_slots[5].out_uop.iw_p1_speculative_child \n connect issue_slots[4].in_uop.bits.iw_issued_partial_dgen, issue_slots[5].out_uop.iw_issued_partial_dgen \n connect issue_slots[4].in_uop.bits.iw_issued_partial_agen, issue_slots[5].out_uop.iw_issued_partial_agen \n connect issue_slots[4].in_uop.bits.iw_issued, issue_slots[5].out_uop.iw_issued \n connect issue_slots[4].in_uop.bits.fu_code[0], issue_slots[5].out_uop.fu_code[0] \n connect issue_slots[4].in_uop.bits.fu_code[1], issue_slots[5].out_uop.fu_code[1] \n connect issue_slots[4].in_uop.bits.fu_code[2], issue_slots[5].out_uop.fu_code[2] \n connect issue_slots[4].in_uop.bits.fu_code[3], issue_slots[5].out_uop.fu_code[3] \n connect issue_slots[4].in_uop.bits.fu_code[4], issue_slots[5].out_uop.fu_code[4] \n connect issue_slots[4].in_uop.bits.fu_code[5], issue_slots[5].out_uop.fu_code[5] \n connect issue_slots[4].in_uop.bits.fu_code[6], issue_slots[5].out_uop.fu_code[6] \n connect issue_slots[4].in_uop.bits.fu_code[7], issue_slots[5].out_uop.fu_code[7] \n connect issue_slots[4].in_uop.bits.fu_code[8], issue_slots[5].out_uop.fu_code[8] \n connect issue_slots[4].in_uop.bits.fu_code[9], issue_slots[5].out_uop.fu_code[9] \n connect issue_slots[4].in_uop.bits.iq_type[0], issue_slots[5].out_uop.iq_type[0] \n connect issue_slots[4].in_uop.bits.iq_type[1], issue_slots[5].out_uop.iq_type[1] \n connect issue_slots[4].in_uop.bits.iq_type[2], issue_slots[5].out_uop.iq_type[2] \n connect issue_slots[4].in_uop.bits.iq_type[3], issue_slots[5].out_uop.iq_type[3] \n connect issue_slots[4].in_uop.bits.debug_pc, issue_slots[5].out_uop.debug_pc \n connect issue_slots[4].in_uop.bits.is_rvc, issue_slots[5].out_uop.is_rvc \n connect issue_slots[4].in_uop.bits.debug_inst, issue_slots[5].out_uop.debug_inst \n connect issue_slots[4].in_uop.bits.inst, issue_slots[5].out_uop.inst \n node _T_170 = eq(shamts_oh[5], UInt<1>(0h1)) \n when _T_170 : \n connect issue_slots[4].in_uop.valid, issue_slots[5].will_be_valid \n connect issue_slots[4].in_uop.bits.debug_tsrc, issue_slots[5].out_uop.debug_tsrc \n connect issue_slots[4].in_uop.bits.debug_fsrc, issue_slots[5].out_uop.debug_fsrc \n connect issue_slots[4].in_uop.bits.bp_xcpt_if, issue_slots[5].out_uop.bp_xcpt_if \n connect issue_slots[4].in_uop.bits.bp_debug_if, issue_slots[5].out_uop.bp_debug_if \n connect issue_slots[4].in_uop.bits.xcpt_ma_if, issue_slots[5].out_uop.xcpt_ma_if \n connect issue_slots[4].in_uop.bits.xcpt_ae_if, issue_slots[5].out_uop.xcpt_ae_if \n connect issue_slots[4].in_uop.bits.xcpt_pf_if, issue_slots[5].out_uop.xcpt_pf_if \n connect issue_slots[4].in_uop.bits.fp_typ, issue_slots[5].out_uop.fp_typ \n connect issue_slots[4].in_uop.bits.fp_rm, issue_slots[5].out_uop.fp_rm \n connect issue_slots[4].in_uop.bits.fp_val, issue_slots[5].out_uop.fp_val \n connect issue_slots[4].in_uop.bits.fcn_op, issue_slots[5].out_uop.fcn_op \n connect issue_slots[4].in_uop.bits.fcn_dw, issue_slots[5].out_uop.fcn_dw \n connect issue_slots[4].in_uop.bits.frs3_en, issue_slots[5].out_uop.frs3_en \n connect issue_slots[4].in_uop.bits.lrs2_rtype, issue_slots[5].out_uop.lrs2_rtype \n connect issue_slots[4].in_uop.bits.lrs1_rtype, issue_slots[5].out_uop.lrs1_rtype \n connect issue_slots[4].in_uop.bits.dst_rtype, issue_slots[5].out_uop.dst_rtype \n connect issue_slots[4].in_uop.bits.lrs3, issue_slots[5].out_uop.lrs3 \n connect issue_slots[4].in_uop.bits.lrs2, issue_slots[5].out_uop.lrs2 \n connect issue_slots[4].in_uop.bits.lrs1, issue_slots[5].out_uop.lrs1 \n connect issue_slots[4].in_uop.bits.ldst, issue_slots[5].out_uop.ldst \n connect issue_slots[4].in_uop.bits.ldst_is_rs1, issue_slots[5].out_uop.ldst_is_rs1 \n connect issue_slots[4].in_uop.bits.csr_cmd, issue_slots[5].out_uop.csr_cmd \n connect issue_slots[4].in_uop.bits.flush_on_commit, issue_slots[5].out_uop.flush_on_commit \n connect issue_slots[4].in_uop.bits.is_unique, issue_slots[5].out_uop.is_unique \n connect issue_slots[4].in_uop.bits.uses_stq, issue_slots[5].out_uop.uses_stq \n connect issue_slots[4].in_uop.bits.uses_ldq, issue_slots[5].out_uop.uses_ldq \n connect issue_slots[4].in_uop.bits.mem_signed, issue_slots[5].out_uop.mem_signed \n connect issue_slots[4].in_uop.bits.mem_size, issue_slots[5].out_uop.mem_size \n connect issue_slots[4].in_uop.bits.mem_cmd, issue_slots[5].out_uop.mem_cmd \n connect issue_slots[4].in_uop.bits.exc_cause, issue_slots[5].out_uop.exc_cause \n connect issue_slots[4].in_uop.bits.exception, issue_slots[5].out_uop.exception \n connect issue_slots[4].in_uop.bits.stale_pdst, issue_slots[5].out_uop.stale_pdst \n connect issue_slots[4].in_uop.bits.ppred_busy, issue_slots[5].out_uop.ppred_busy \n connect issue_slots[4].in_uop.bits.prs3_busy, issue_slots[5].out_uop.prs3_busy \n connect issue_slots[4].in_uop.bits.prs2_busy, issue_slots[5].out_uop.prs2_busy \n connect issue_slots[4].in_uop.bits.prs1_busy, issue_slots[5].out_uop.prs1_busy \n connect issue_slots[4].in_uop.bits.ppred, issue_slots[5].out_uop.ppred \n connect issue_slots[4].in_uop.bits.prs3, issue_slots[5].out_uop.prs3 \n connect issue_slots[4].in_uop.bits.prs2, issue_slots[5].out_uop.prs2 \n connect issue_slots[4].in_uop.bits.prs1, issue_slots[5].out_uop.prs1 \n connect issue_slots[4].in_uop.bits.pdst, issue_slots[5].out_uop.pdst \n connect issue_slots[4].in_uop.bits.rxq_idx, issue_slots[5].out_uop.rxq_idx \n connect issue_slots[4].in_uop.bits.stq_idx, issue_slots[5].out_uop.stq_idx \n connect issue_slots[4].in_uop.bits.ldq_idx, issue_slots[5].out_uop.ldq_idx \n connect issue_slots[4].in_uop.bits.rob_idx, issue_slots[5].out_uop.rob_idx \n connect issue_slots[4].in_uop.bits.fp_ctrl.vec, issue_slots[5].out_uop.fp_ctrl.vec \n connect issue_slots[4].in_uop.bits.fp_ctrl.wflags, issue_slots[5].out_uop.fp_ctrl.wflags \n connect issue_slots[4].in_uop.bits.fp_ctrl.sqrt, issue_slots[5].out_uop.fp_ctrl.sqrt \n connect issue_slots[4].in_uop.bits.fp_ctrl.div, issue_slots[5].out_uop.fp_ctrl.div \n connect issue_slots[4].in_uop.bits.fp_ctrl.fma, issue_slots[5].out_uop.fp_ctrl.fma \n connect issue_slots[4].in_uop.bits.fp_ctrl.fastpipe, issue_slots[5].out_uop.fp_ctrl.fastpipe \n connect issue_slots[4].in_uop.bits.fp_ctrl.toint, issue_slots[5].out_uop.fp_ctrl.toint \n connect issue_slots[4].in_uop.bits.fp_ctrl.fromint, issue_slots[5].out_uop.fp_ctrl.fromint \n connect issue_slots[4].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[5].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[4].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[5].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[4].in_uop.bits.fp_ctrl.swap23, issue_slots[5].out_uop.fp_ctrl.swap23 \n connect issue_slots[4].in_uop.bits.fp_ctrl.swap12, issue_slots[5].out_uop.fp_ctrl.swap12 \n connect issue_slots[4].in_uop.bits.fp_ctrl.ren3, issue_slots[5].out_uop.fp_ctrl.ren3 \n connect issue_slots[4].in_uop.bits.fp_ctrl.ren2, issue_slots[5].out_uop.fp_ctrl.ren2 \n connect issue_slots[4].in_uop.bits.fp_ctrl.ren1, issue_slots[5].out_uop.fp_ctrl.ren1 \n connect issue_slots[4].in_uop.bits.fp_ctrl.wen, issue_slots[5].out_uop.fp_ctrl.wen \n connect issue_slots[4].in_uop.bits.fp_ctrl.ldst, issue_slots[5].out_uop.fp_ctrl.ldst \n connect issue_slots[4].in_uop.bits.op2_sel, issue_slots[5].out_uop.op2_sel \n connect issue_slots[4].in_uop.bits.op1_sel, issue_slots[5].out_uop.op1_sel \n connect issue_slots[4].in_uop.bits.imm_packed, issue_slots[5].out_uop.imm_packed \n connect issue_slots[4].in_uop.bits.pimm, issue_slots[5].out_uop.pimm \n connect issue_slots[4].in_uop.bits.imm_sel, issue_slots[5].out_uop.imm_sel \n connect issue_slots[4].in_uop.bits.imm_rename, issue_slots[5].out_uop.imm_rename \n connect issue_slots[4].in_uop.bits.taken, issue_slots[5].out_uop.taken \n connect issue_slots[4].in_uop.bits.pc_lob, issue_slots[5].out_uop.pc_lob \n connect issue_slots[4].in_uop.bits.edge_inst, issue_slots[5].out_uop.edge_inst \n connect issue_slots[4].in_uop.bits.ftq_idx, issue_slots[5].out_uop.ftq_idx \n connect issue_slots[4].in_uop.bits.is_mov, issue_slots[5].out_uop.is_mov \n connect issue_slots[4].in_uop.bits.is_rocc, issue_slots[5].out_uop.is_rocc \n connect issue_slots[4].in_uop.bits.is_sys_pc2epc, issue_slots[5].out_uop.is_sys_pc2epc \n connect issue_slots[4].in_uop.bits.is_eret, issue_slots[5].out_uop.is_eret \n connect issue_slots[4].in_uop.bits.is_amo, issue_slots[5].out_uop.is_amo \n connect issue_slots[4].in_uop.bits.is_sfence, issue_slots[5].out_uop.is_sfence \n connect issue_slots[4].in_uop.bits.is_fencei, issue_slots[5].out_uop.is_fencei \n connect issue_slots[4].in_uop.bits.is_fence, issue_slots[5].out_uop.is_fence \n connect issue_slots[4].in_uop.bits.is_sfb, issue_slots[5].out_uop.is_sfb \n connect issue_slots[4].in_uop.bits.br_type, issue_slots[5].out_uop.br_type \n connect issue_slots[4].in_uop.bits.br_tag, issue_slots[5].out_uop.br_tag \n connect issue_slots[4].in_uop.bits.br_mask, issue_slots[5].out_uop.br_mask \n connect issue_slots[4].in_uop.bits.dis_col_sel, issue_slots[5].out_uop.dis_col_sel \n connect issue_slots[4].in_uop.bits.iw_p3_bypass_hint, issue_slots[5].out_uop.iw_p3_bypass_hint \n connect issue_slots[4].in_uop.bits.iw_p2_bypass_hint, issue_slots[5].out_uop.iw_p2_bypass_hint \n connect issue_slots[4].in_uop.bits.iw_p1_bypass_hint, issue_slots[5].out_uop.iw_p1_bypass_hint \n connect issue_slots[4].in_uop.bits.iw_p2_speculative_child, issue_slots[5].out_uop.iw_p2_speculative_child \n connect issue_slots[4].in_uop.bits.iw_p1_speculative_child, issue_slots[5].out_uop.iw_p1_speculative_child \n connect issue_slots[4].in_uop.bits.iw_issued_partial_dgen, issue_slots[5].out_uop.iw_issued_partial_dgen \n connect issue_slots[4].in_uop.bits.iw_issued_partial_agen, issue_slots[5].out_uop.iw_issued_partial_agen \n connect issue_slots[4].in_uop.bits.iw_issued, issue_slots[5].out_uop.iw_issued \n connect issue_slots[4].in_uop.bits.fu_code[0], issue_slots[5].out_uop.fu_code[0] \n connect issue_slots[4].in_uop.bits.fu_code[1], issue_slots[5].out_uop.fu_code[1] \n connect issue_slots[4].in_uop.bits.fu_code[2], issue_slots[5].out_uop.fu_code[2] \n connect issue_slots[4].in_uop.bits.fu_code[3], issue_slots[5].out_uop.fu_code[3] \n connect issue_slots[4].in_uop.bits.fu_code[4], issue_slots[5].out_uop.fu_code[4] \n connect issue_slots[4].in_uop.bits.fu_code[5], issue_slots[5].out_uop.fu_code[5] \n connect issue_slots[4].in_uop.bits.fu_code[6], issue_slots[5].out_uop.fu_code[6] \n connect issue_slots[4].in_uop.bits.fu_code[7], issue_slots[5].out_uop.fu_code[7] \n connect issue_slots[4].in_uop.bits.fu_code[8], issue_slots[5].out_uop.fu_code[8] \n connect issue_slots[4].in_uop.bits.fu_code[9], issue_slots[5].out_uop.fu_code[9] \n connect issue_slots[4].in_uop.bits.iq_type[0], issue_slots[5].out_uop.iq_type[0] \n connect issue_slots[4].in_uop.bits.iq_type[1], issue_slots[5].out_uop.iq_type[1] \n connect issue_slots[4].in_uop.bits.iq_type[2], issue_slots[5].out_uop.iq_type[2] \n connect issue_slots[4].in_uop.bits.iq_type[3], issue_slots[5].out_uop.iq_type[3] \n connect issue_slots[4].in_uop.bits.debug_pc, issue_slots[5].out_uop.debug_pc \n connect issue_slots[4].in_uop.bits.is_rvc, issue_slots[5].out_uop.is_rvc \n connect issue_slots[4].in_uop.bits.debug_inst, issue_slots[5].out_uop.debug_inst \n connect issue_slots[4].in_uop.bits.inst, issue_slots[5].out_uop.inst \n node _T_171 = eq(shamts_oh[6], UInt<2>(0h2)) \n when _T_171 : \n connect issue_slots[4].in_uop.valid, issue_slots[6].will_be_valid \n connect issue_slots[4].in_uop.bits.debug_tsrc, issue_slots[6].out_uop.debug_tsrc \n connect issue_slots[4].in_uop.bits.debug_fsrc, issue_slots[6].out_uop.debug_fsrc \n connect issue_slots[4].in_uop.bits.bp_xcpt_if, issue_slots[6].out_uop.bp_xcpt_if \n connect issue_slots[4].in_uop.bits.bp_debug_if, issue_slots[6].out_uop.bp_debug_if \n connect issue_slots[4].in_uop.bits.xcpt_ma_if, issue_slots[6].out_uop.xcpt_ma_if \n connect issue_slots[4].in_uop.bits.xcpt_ae_if, issue_slots[6].out_uop.xcpt_ae_if \n connect issue_slots[4].in_uop.bits.xcpt_pf_if, issue_slots[6].out_uop.xcpt_pf_if \n connect issue_slots[4].in_uop.bits.fp_typ, issue_slots[6].out_uop.fp_typ \n connect issue_slots[4].in_uop.bits.fp_rm, issue_slots[6].out_uop.fp_rm \n connect issue_slots[4].in_uop.bits.fp_val, issue_slots[6].out_uop.fp_val \n connect issue_slots[4].in_uop.bits.fcn_op, issue_slots[6].out_uop.fcn_op \n connect issue_slots[4].in_uop.bits.fcn_dw, issue_slots[6].out_uop.fcn_dw \n connect issue_slots[4].in_uop.bits.frs3_en, issue_slots[6].out_uop.frs3_en \n connect issue_slots[4].in_uop.bits.lrs2_rtype, issue_slots[6].out_uop.lrs2_rtype \n connect issue_slots[4].in_uop.bits.lrs1_rtype, issue_slots[6].out_uop.lrs1_rtype \n connect issue_slots[4].in_uop.bits.dst_rtype, issue_slots[6].out_uop.dst_rtype \n connect issue_slots[4].in_uop.bits.lrs3, issue_slots[6].out_uop.lrs3 \n connect issue_slots[4].in_uop.bits.lrs2, issue_slots[6].out_uop.lrs2 \n connect issue_slots[4].in_uop.bits.lrs1, issue_slots[6].out_uop.lrs1 \n connect issue_slots[4].in_uop.bits.ldst, issue_slots[6].out_uop.ldst \n connect issue_slots[4].in_uop.bits.ldst_is_rs1, issue_slots[6].out_uop.ldst_is_rs1 \n connect issue_slots[4].in_uop.bits.csr_cmd, issue_slots[6].out_uop.csr_cmd \n connect issue_slots[4].in_uop.bits.flush_on_commit, issue_slots[6].out_uop.flush_on_commit \n connect issue_slots[4].in_uop.bits.is_unique, issue_slots[6].out_uop.is_unique \n connect issue_slots[4].in_uop.bits.uses_stq, issue_slots[6].out_uop.uses_stq \n connect issue_slots[4].in_uop.bits.uses_ldq, issue_slots[6].out_uop.uses_ldq \n connect issue_slots[4].in_uop.bits.mem_signed, issue_slots[6].out_uop.mem_signed \n connect issue_slots[4].in_uop.bits.mem_size, issue_slots[6].out_uop.mem_size \n connect issue_slots[4].in_uop.bits.mem_cmd, issue_slots[6].out_uop.mem_cmd \n connect issue_slots[4].in_uop.bits.exc_cause, issue_slots[6].out_uop.exc_cause \n connect issue_slots[4].in_uop.bits.exception, issue_slots[6].out_uop.exception \n connect issue_slots[4].in_uop.bits.stale_pdst, issue_slots[6].out_uop.stale_pdst \n connect issue_slots[4].in_uop.bits.ppred_busy, issue_slots[6].out_uop.ppred_busy \n connect issue_slots[4].in_uop.bits.prs3_busy, issue_slots[6].out_uop.prs3_busy \n connect issue_slots[4].in_uop.bits.prs2_busy, issue_slots[6].out_uop.prs2_busy \n connect issue_slots[4].in_uop.bits.prs1_busy, issue_slots[6].out_uop.prs1_busy \n connect issue_slots[4].in_uop.bits.ppred, issue_slots[6].out_uop.ppred \n connect issue_slots[4].in_uop.bits.prs3, issue_slots[6].out_uop.prs3 \n connect issue_slots[4].in_uop.bits.prs2, issue_slots[6].out_uop.prs2 \n connect issue_slots[4].in_uop.bits.prs1, issue_slots[6].out_uop.prs1 \n connect issue_slots[4].in_uop.bits.pdst, issue_slots[6].out_uop.pdst \n connect issue_slots[4].in_uop.bits.rxq_idx, issue_slots[6].out_uop.rxq_idx \n connect issue_slots[4].in_uop.bits.stq_idx, issue_slots[6].out_uop.stq_idx \n connect issue_slots[4].in_uop.bits.ldq_idx, issue_slots[6].out_uop.ldq_idx \n connect issue_slots[4].in_uop.bits.rob_idx, issue_slots[6].out_uop.rob_idx \n connect issue_slots[4].in_uop.bits.fp_ctrl.vec, issue_slots[6].out_uop.fp_ctrl.vec \n connect issue_slots[4].in_uop.bits.fp_ctrl.wflags, issue_slots[6].out_uop.fp_ctrl.wflags \n connect issue_slots[4].in_uop.bits.fp_ctrl.sqrt, issue_slots[6].out_uop.fp_ctrl.sqrt \n connect issue_slots[4].in_uop.bits.fp_ctrl.div, issue_slots[6].out_uop.fp_ctrl.div \n connect issue_slots[4].in_uop.bits.fp_ctrl.fma, issue_slots[6].out_uop.fp_ctrl.fma \n connect issue_slots[4].in_uop.bits.fp_ctrl.fastpipe, issue_slots[6].out_uop.fp_ctrl.fastpipe \n connect issue_slots[4].in_uop.bits.fp_ctrl.toint, issue_slots[6].out_uop.fp_ctrl.toint \n connect issue_slots[4].in_uop.bits.fp_ctrl.fromint, issue_slots[6].out_uop.fp_ctrl.fromint \n connect issue_slots[4].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[6].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[4].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[6].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[4].in_uop.bits.fp_ctrl.swap23, issue_slots[6].out_uop.fp_ctrl.swap23 \n connect issue_slots[4].in_uop.bits.fp_ctrl.swap12, issue_slots[6].out_uop.fp_ctrl.swap12 \n connect issue_slots[4].in_uop.bits.fp_ctrl.ren3, issue_slots[6].out_uop.fp_ctrl.ren3 \n connect issue_slots[4].in_uop.bits.fp_ctrl.ren2, issue_slots[6].out_uop.fp_ctrl.ren2 \n connect issue_slots[4].in_uop.bits.fp_ctrl.ren1, issue_slots[6].out_uop.fp_ctrl.ren1 \n connect issue_slots[4].in_uop.bits.fp_ctrl.wen, issue_slots[6].out_uop.fp_ctrl.wen \n connect issue_slots[4].in_uop.bits.fp_ctrl.ldst, issue_slots[6].out_uop.fp_ctrl.ldst \n connect issue_slots[4].in_uop.bits.op2_sel, issue_slots[6].out_uop.op2_sel \n connect issue_slots[4].in_uop.bits.op1_sel, issue_slots[6].out_uop.op1_sel \n connect issue_slots[4].in_uop.bits.imm_packed, issue_slots[6].out_uop.imm_packed \n connect issue_slots[4].in_uop.bits.pimm, issue_slots[6].out_uop.pimm \n connect issue_slots[4].in_uop.bits.imm_sel, issue_slots[6].out_uop.imm_sel \n connect issue_slots[4].in_uop.bits.imm_rename, issue_slots[6].out_uop.imm_rename \n connect issue_slots[4].in_uop.bits.taken, issue_slots[6].out_uop.taken \n connect issue_slots[4].in_uop.bits.pc_lob, issue_slots[6].out_uop.pc_lob \n connect issue_slots[4].in_uop.bits.edge_inst, issue_slots[6].out_uop.edge_inst \n connect issue_slots[4].in_uop.bits.ftq_idx, issue_slots[6].out_uop.ftq_idx \n connect issue_slots[4].in_uop.bits.is_mov, issue_slots[6].out_uop.is_mov \n connect issue_slots[4].in_uop.bits.is_rocc, issue_slots[6].out_uop.is_rocc \n connect issue_slots[4].in_uop.bits.is_sys_pc2epc, issue_slots[6].out_uop.is_sys_pc2epc \n connect issue_slots[4].in_uop.bits.is_eret, issue_slots[6].out_uop.is_eret \n connect issue_slots[4].in_uop.bits.is_amo, issue_slots[6].out_uop.is_amo \n connect issue_slots[4].in_uop.bits.is_sfence, issue_slots[6].out_uop.is_sfence \n connect issue_slots[4].in_uop.bits.is_fencei, issue_slots[6].out_uop.is_fencei \n connect issue_slots[4].in_uop.bits.is_fence, issue_slots[6].out_uop.is_fence \n connect issue_slots[4].in_uop.bits.is_sfb, issue_slots[6].out_uop.is_sfb \n connect issue_slots[4].in_uop.bits.br_type, issue_slots[6].out_uop.br_type \n connect issue_slots[4].in_uop.bits.br_tag, issue_slots[6].out_uop.br_tag \n connect issue_slots[4].in_uop.bits.br_mask, issue_slots[6].out_uop.br_mask \n connect issue_slots[4].in_uop.bits.dis_col_sel, issue_slots[6].out_uop.dis_col_sel \n connect issue_slots[4].in_uop.bits.iw_p3_bypass_hint, issue_slots[6].out_uop.iw_p3_bypass_hint \n connect issue_slots[4].in_uop.bits.iw_p2_bypass_hint, issue_slots[6].out_uop.iw_p2_bypass_hint \n connect issue_slots[4].in_uop.bits.iw_p1_bypass_hint, issue_slots[6].out_uop.iw_p1_bypass_hint \n connect issue_slots[4].in_uop.bits.iw_p2_speculative_child, issue_slots[6].out_uop.iw_p2_speculative_child \n connect issue_slots[4].in_uop.bits.iw_p1_speculative_child, issue_slots[6].out_uop.iw_p1_speculative_child \n connect issue_slots[4].in_uop.bits.iw_issued_partial_dgen, issue_slots[6].out_uop.iw_issued_partial_dgen \n connect issue_slots[4].in_uop.bits.iw_issued_partial_agen, issue_slots[6].out_uop.iw_issued_partial_agen \n connect issue_slots[4].in_uop.bits.iw_issued, issue_slots[6].out_uop.iw_issued \n connect issue_slots[4].in_uop.bits.fu_code[0], issue_slots[6].out_uop.fu_code[0] \n connect issue_slots[4].in_uop.bits.fu_code[1], issue_slots[6].out_uop.fu_code[1] \n connect issue_slots[4].in_uop.bits.fu_code[2], issue_slots[6].out_uop.fu_code[2] \n connect issue_slots[4].in_uop.bits.fu_code[3], issue_slots[6].out_uop.fu_code[3] \n connect issue_slots[4].in_uop.bits.fu_code[4], issue_slots[6].out_uop.fu_code[4] \n connect issue_slots[4].in_uop.bits.fu_code[5], issue_slots[6].out_uop.fu_code[5] \n connect issue_slots[4].in_uop.bits.fu_code[6], issue_slots[6].out_uop.fu_code[6] \n connect issue_slots[4].in_uop.bits.fu_code[7], issue_slots[6].out_uop.fu_code[7] \n connect issue_slots[4].in_uop.bits.fu_code[8], issue_slots[6].out_uop.fu_code[8] \n connect issue_slots[4].in_uop.bits.fu_code[9], issue_slots[6].out_uop.fu_code[9] \n connect issue_slots[4].in_uop.bits.iq_type[0], issue_slots[6].out_uop.iq_type[0] \n connect issue_slots[4].in_uop.bits.iq_type[1], issue_slots[6].out_uop.iq_type[1] \n connect issue_slots[4].in_uop.bits.iq_type[2], issue_slots[6].out_uop.iq_type[2] \n connect issue_slots[4].in_uop.bits.iq_type[3], issue_slots[6].out_uop.iq_type[3] \n connect issue_slots[4].in_uop.bits.debug_pc, issue_slots[6].out_uop.debug_pc \n connect issue_slots[4].in_uop.bits.is_rvc, issue_slots[6].out_uop.is_rvc \n connect issue_slots[4].in_uop.bits.debug_inst, issue_slots[6].out_uop.debug_inst \n connect issue_slots[4].in_uop.bits.inst, issue_slots[6].out_uop.inst \n node _issue_slots_4_clear_T = neq(shamts_oh[4], UInt<1>(0h0)) \n connect issue_slots[4].clear, _issue_slots_4_clear_T \n connect issue_slots[5].in_uop.valid, UInt<1>(0h0) \n connect issue_slots[5].in_uop.bits.debug_tsrc, issue_slots[6].out_uop.debug_tsrc \n connect issue_slots[5].in_uop.bits.debug_fsrc, issue_slots[6].out_uop.debug_fsrc \n connect issue_slots[5].in_uop.bits.bp_xcpt_if, issue_slots[6].out_uop.bp_xcpt_if \n connect issue_slots[5].in_uop.bits.bp_debug_if, issue_slots[6].out_uop.bp_debug_if \n connect issue_slots[5].in_uop.bits.xcpt_ma_if, issue_slots[6].out_uop.xcpt_ma_if \n connect issue_slots[5].in_uop.bits.xcpt_ae_if, issue_slots[6].out_uop.xcpt_ae_if \n connect issue_slots[5].in_uop.bits.xcpt_pf_if, issue_slots[6].out_uop.xcpt_pf_if \n connect issue_slots[5].in_uop.bits.fp_typ, issue_slots[6].out_uop.fp_typ \n connect issue_slots[5].in_uop.bits.fp_rm, issue_slots[6].out_uop.fp_rm \n connect issue_slots[5].in_uop.bits.fp_val, issue_slots[6].out_uop.fp_val \n connect issue_slots[5].in_uop.bits.fcn_op, issue_slots[6].out_uop.fcn_op \n connect issue_slots[5].in_uop.bits.fcn_dw, issue_slots[6].out_uop.fcn_dw \n connect issue_slots[5].in_uop.bits.frs3_en, issue_slots[6].out_uop.frs3_en \n connect issue_slots[5].in_uop.bits.lrs2_rtype, issue_slots[6].out_uop.lrs2_rtype \n connect issue_slots[5].in_uop.bits.lrs1_rtype, issue_slots[6].out_uop.lrs1_rtype \n connect issue_slots[5].in_uop.bits.dst_rtype, issue_slots[6].out_uop.dst_rtype \n connect issue_slots[5].in_uop.bits.lrs3, issue_slots[6].out_uop.lrs3 \n connect issue_slots[5].in_uop.bits.lrs2, issue_slots[6].out_uop.lrs2 \n connect issue_slots[5].in_uop.bits.lrs1, issue_slots[6].out_uop.lrs1 \n connect issue_slots[5].in_uop.bits.ldst, issue_slots[6].out_uop.ldst \n connect issue_slots[5].in_uop.bits.ldst_is_rs1, issue_slots[6].out_uop.ldst_is_rs1 \n connect issue_slots[5].in_uop.bits.csr_cmd, issue_slots[6].out_uop.csr_cmd \n connect issue_slots[5].in_uop.bits.flush_on_commit, issue_slots[6].out_uop.flush_on_commit \n connect issue_slots[5].in_uop.bits.is_unique, issue_slots[6].out_uop.is_unique \n connect issue_slots[5].in_uop.bits.uses_stq, issue_slots[6].out_uop.uses_stq \n connect issue_slots[5].in_uop.bits.uses_ldq, issue_slots[6].out_uop.uses_ldq \n connect issue_slots[5].in_uop.bits.mem_signed, issue_slots[6].out_uop.mem_signed \n connect issue_slots[5].in_uop.bits.mem_size, issue_slots[6].out_uop.mem_size \n connect issue_slots[5].in_uop.bits.mem_cmd, issue_slots[6].out_uop.mem_cmd \n connect issue_slots[5].in_uop.bits.exc_cause, issue_slots[6].out_uop.exc_cause \n connect issue_slots[5].in_uop.bits.exception, issue_slots[6].out_uop.exception \n connect issue_slots[5].in_uop.bits.stale_pdst, issue_slots[6].out_uop.stale_pdst \n connect issue_slots[5].in_uop.bits.ppred_busy, issue_slots[6].out_uop.ppred_busy \n connect issue_slots[5].in_uop.bits.prs3_busy, issue_slots[6].out_uop.prs3_busy \n connect issue_slots[5].in_uop.bits.prs2_busy, issue_slots[6].out_uop.prs2_busy \n connect issue_slots[5].in_uop.bits.prs1_busy, issue_slots[6].out_uop.prs1_busy \n connect issue_slots[5].in_uop.bits.ppred, issue_slots[6].out_uop.ppred \n connect issue_slots[5].in_uop.bits.prs3, issue_slots[6].out_uop.prs3 \n connect issue_slots[5].in_uop.bits.prs2, issue_slots[6].out_uop.prs2 \n connect issue_slots[5].in_uop.bits.prs1, issue_slots[6].out_uop.prs1 \n connect issue_slots[5].in_uop.bits.pdst, issue_slots[6].out_uop.pdst \n connect issue_slots[5].in_uop.bits.rxq_idx, issue_slots[6].out_uop.rxq_idx \n connect issue_slots[5].in_uop.bits.stq_idx, issue_slots[6].out_uop.stq_idx \n connect issue_slots[5].in_uop.bits.ldq_idx, issue_slots[6].out_uop.ldq_idx \n connect issue_slots[5].in_uop.bits.rob_idx, issue_slots[6].out_uop.rob_idx \n connect issue_slots[5].in_uop.bits.fp_ctrl.vec, issue_slots[6].out_uop.fp_ctrl.vec \n connect issue_slots[5].in_uop.bits.fp_ctrl.wflags, issue_slots[6].out_uop.fp_ctrl.wflags \n connect issue_slots[5].in_uop.bits.fp_ctrl.sqrt, issue_slots[6].out_uop.fp_ctrl.sqrt \n connect issue_slots[5].in_uop.bits.fp_ctrl.div, issue_slots[6].out_uop.fp_ctrl.div \n connect issue_slots[5].in_uop.bits.fp_ctrl.fma, issue_slots[6].out_uop.fp_ctrl.fma \n connect issue_slots[5].in_uop.bits.fp_ctrl.fastpipe, issue_slots[6].out_uop.fp_ctrl.fastpipe \n connect issue_slots[5].in_uop.bits.fp_ctrl.toint, issue_slots[6].out_uop.fp_ctrl.toint \n connect issue_slots[5].in_uop.bits.fp_ctrl.fromint, issue_slots[6].out_uop.fp_ctrl.fromint \n connect issue_slots[5].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[6].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[5].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[6].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[5].in_uop.bits.fp_ctrl.swap23, issue_slots[6].out_uop.fp_ctrl.swap23 \n connect issue_slots[5].in_uop.bits.fp_ctrl.swap12, issue_slots[6].out_uop.fp_ctrl.swap12 \n connect issue_slots[5].in_uop.bits.fp_ctrl.ren3, issue_slots[6].out_uop.fp_ctrl.ren3 \n connect issue_slots[5].in_uop.bits.fp_ctrl.ren2, issue_slots[6].out_uop.fp_ctrl.ren2 \n connect issue_slots[5].in_uop.bits.fp_ctrl.ren1, issue_slots[6].out_uop.fp_ctrl.ren1 \n connect issue_slots[5].in_uop.bits.fp_ctrl.wen, issue_slots[6].out_uop.fp_ctrl.wen \n connect issue_slots[5].in_uop.bits.fp_ctrl.ldst, issue_slots[6].out_uop.fp_ctrl.ldst \n connect issue_slots[5].in_uop.bits.op2_sel, issue_slots[6].out_uop.op2_sel \n connect issue_slots[5].in_uop.bits.op1_sel, issue_slots[6].out_uop.op1_sel \n connect issue_slots[5].in_uop.bits.imm_packed, issue_slots[6].out_uop.imm_packed \n connect issue_slots[5].in_uop.bits.pimm, issue_slots[6].out_uop.pimm \n connect issue_slots[5].in_uop.bits.imm_sel, issue_slots[6].out_uop.imm_sel \n connect issue_slots[5].in_uop.bits.imm_rename, issue_slots[6].out_uop.imm_rename \n connect issue_slots[5].in_uop.bits.taken, issue_slots[6].out_uop.taken \n connect issue_slots[5].in_uop.bits.pc_lob, issue_slots[6].out_uop.pc_lob \n connect issue_slots[5].in_uop.bits.edge_inst, issue_slots[6].out_uop.edge_inst \n connect issue_slots[5].in_uop.bits.ftq_idx, issue_slots[6].out_uop.ftq_idx \n connect issue_slots[5].in_uop.bits.is_mov, issue_slots[6].out_uop.is_mov \n connect issue_slots[5].in_uop.bits.is_rocc, issue_slots[6].out_uop.is_rocc \n connect issue_slots[5].in_uop.bits.is_sys_pc2epc, issue_slots[6].out_uop.is_sys_pc2epc \n connect issue_slots[5].in_uop.bits.is_eret, issue_slots[6].out_uop.is_eret \n connect issue_slots[5].in_uop.bits.is_amo, issue_slots[6].out_uop.is_amo \n connect issue_slots[5].in_uop.bits.is_sfence, issue_slots[6].out_uop.is_sfence \n connect issue_slots[5].in_uop.bits.is_fencei, issue_slots[6].out_uop.is_fencei \n connect issue_slots[5].in_uop.bits.is_fence, issue_slots[6].out_uop.is_fence \n connect issue_slots[5].in_uop.bits.is_sfb, issue_slots[6].out_uop.is_sfb \n connect issue_slots[5].in_uop.bits.br_type, issue_slots[6].out_uop.br_type \n connect issue_slots[5].in_uop.bits.br_tag, issue_slots[6].out_uop.br_tag \n connect issue_slots[5].in_uop.bits.br_mask, issue_slots[6].out_uop.br_mask \n connect issue_slots[5].in_uop.bits.dis_col_sel, issue_slots[6].out_uop.dis_col_sel \n connect issue_slots[5].in_uop.bits.iw_p3_bypass_hint, issue_slots[6].out_uop.iw_p3_bypass_hint \n connect issue_slots[5].in_uop.bits.iw_p2_bypass_hint, issue_slots[6].out_uop.iw_p2_bypass_hint \n connect issue_slots[5].in_uop.bits.iw_p1_bypass_hint, issue_slots[6].out_uop.iw_p1_bypass_hint \n connect issue_slots[5].in_uop.bits.iw_p2_speculative_child, issue_slots[6].out_uop.iw_p2_speculative_child \n connect issue_slots[5].in_uop.bits.iw_p1_speculative_child, issue_slots[6].out_uop.iw_p1_speculative_child \n connect issue_slots[5].in_uop.bits.iw_issued_partial_dgen, issue_slots[6].out_uop.iw_issued_partial_dgen \n connect issue_slots[5].in_uop.bits.iw_issued_partial_agen, issue_slots[6].out_uop.iw_issued_partial_agen \n connect issue_slots[5].in_uop.bits.iw_issued, issue_slots[6].out_uop.iw_issued \n connect issue_slots[5].in_uop.bits.fu_code[0], issue_slots[6].out_uop.fu_code[0] \n connect issue_slots[5].in_uop.bits.fu_code[1], issue_slots[6].out_uop.fu_code[1] \n connect issue_slots[5].in_uop.bits.fu_code[2], issue_slots[6].out_uop.fu_code[2] \n connect issue_slots[5].in_uop.bits.fu_code[3], issue_slots[6].out_uop.fu_code[3] \n connect issue_slots[5].in_uop.bits.fu_code[4], issue_slots[6].out_uop.fu_code[4] \n connect issue_slots[5].in_uop.bits.fu_code[5], issue_slots[6].out_uop.fu_code[5] \n connect issue_slots[5].in_uop.bits.fu_code[6], issue_slots[6].out_uop.fu_code[6] \n connect issue_slots[5].in_uop.bits.fu_code[7], issue_slots[6].out_uop.fu_code[7] \n connect issue_slots[5].in_uop.bits.fu_code[8], issue_slots[6].out_uop.fu_code[8] \n connect issue_slots[5].in_uop.bits.fu_code[9], issue_slots[6].out_uop.fu_code[9] \n connect issue_slots[5].in_uop.bits.iq_type[0], issue_slots[6].out_uop.iq_type[0] \n connect issue_slots[5].in_uop.bits.iq_type[1], issue_slots[6].out_uop.iq_type[1] \n connect issue_slots[5].in_uop.bits.iq_type[2], issue_slots[6].out_uop.iq_type[2] \n connect issue_slots[5].in_uop.bits.iq_type[3], issue_slots[6].out_uop.iq_type[3] \n connect issue_slots[5].in_uop.bits.debug_pc, issue_slots[6].out_uop.debug_pc \n connect issue_slots[5].in_uop.bits.is_rvc, issue_slots[6].out_uop.is_rvc \n connect issue_slots[5].in_uop.bits.debug_inst, issue_slots[6].out_uop.debug_inst \n connect issue_slots[5].in_uop.bits.inst, issue_slots[6].out_uop.inst \n node _T_172 = eq(shamts_oh[6], UInt<1>(0h1)) \n when _T_172 : \n connect issue_slots[5].in_uop.valid, issue_slots[6].will_be_valid \n connect issue_slots[5].in_uop.bits.debug_tsrc, issue_slots[6].out_uop.debug_tsrc \n connect issue_slots[5].in_uop.bits.debug_fsrc, issue_slots[6].out_uop.debug_fsrc \n connect issue_slots[5].in_uop.bits.bp_xcpt_if, issue_slots[6].out_uop.bp_xcpt_if \n connect issue_slots[5].in_uop.bits.bp_debug_if, issue_slots[6].out_uop.bp_debug_if \n connect issue_slots[5].in_uop.bits.xcpt_ma_if, issue_slots[6].out_uop.xcpt_ma_if \n connect issue_slots[5].in_uop.bits.xcpt_ae_if, issue_slots[6].out_uop.xcpt_ae_if \n connect issue_slots[5].in_uop.bits.xcpt_pf_if, issue_slots[6].out_uop.xcpt_pf_if \n connect issue_slots[5].in_uop.bits.fp_typ, issue_slots[6].out_uop.fp_typ \n connect issue_slots[5].in_uop.bits.fp_rm, issue_slots[6].out_uop.fp_rm \n connect issue_slots[5].in_uop.bits.fp_val, issue_slots[6].out_uop.fp_val \n connect issue_slots[5].in_uop.bits.fcn_op, issue_slots[6].out_uop.fcn_op \n connect issue_slots[5].in_uop.bits.fcn_dw, issue_slots[6].out_uop.fcn_dw \n connect issue_slots[5].in_uop.bits.frs3_en, issue_slots[6].out_uop.frs3_en \n connect issue_slots[5].in_uop.bits.lrs2_rtype, issue_slots[6].out_uop.lrs2_rtype \n connect issue_slots[5].in_uop.bits.lrs1_rtype, issue_slots[6].out_uop.lrs1_rtype \n connect issue_slots[5].in_uop.bits.dst_rtype, issue_slots[6].out_uop.dst_rtype \n connect issue_slots[5].in_uop.bits.lrs3, issue_slots[6].out_uop.lrs3 \n connect issue_slots[5].in_uop.bits.lrs2, issue_slots[6].out_uop.lrs2 \n connect issue_slots[5].in_uop.bits.lrs1, issue_slots[6].out_uop.lrs1 \n connect issue_slots[5].in_uop.bits.ldst, issue_slots[6].out_uop.ldst \n connect issue_slots[5].in_uop.bits.ldst_is_rs1, issue_slots[6].out_uop.ldst_is_rs1 \n connect issue_slots[5].in_uop.bits.csr_cmd, issue_slots[6].out_uop.csr_cmd \n connect issue_slots[5].in_uop.bits.flush_on_commit, issue_slots[6].out_uop.flush_on_commit \n connect issue_slots[5].in_uop.bits.is_unique, issue_slots[6].out_uop.is_unique \n connect issue_slots[5].in_uop.bits.uses_stq, issue_slots[6].out_uop.uses_stq \n connect issue_slots[5].in_uop.bits.uses_ldq, issue_slots[6].out_uop.uses_ldq \n connect issue_slots[5].in_uop.bits.mem_signed, issue_slots[6].out_uop.mem_signed \n connect issue_slots[5].in_uop.bits.mem_size, issue_slots[6].out_uop.mem_size \n connect issue_slots[5].in_uop.bits.mem_cmd, issue_slots[6].out_uop.mem_cmd \n connect issue_slots[5].in_uop.bits.exc_cause, issue_slots[6].out_uop.exc_cause \n connect issue_slots[5].in_uop.bits.exception, issue_slots[6].out_uop.exception \n connect issue_slots[5].in_uop.bits.stale_pdst, issue_slots[6].out_uop.stale_pdst \n connect issue_slots[5].in_uop.bits.ppred_busy, issue_slots[6].out_uop.ppred_busy \n connect issue_slots[5].in_uop.bits.prs3_busy, issue_slots[6].out_uop.prs3_busy \n connect issue_slots[5].in_uop.bits.prs2_busy, issue_slots[6].out_uop.prs2_busy \n connect issue_slots[5].in_uop.bits.prs1_busy, issue_slots[6].out_uop.prs1_busy \n connect issue_slots[5].in_uop.bits.ppred, issue_slots[6].out_uop.ppred \n connect issue_slots[5].in_uop.bits.prs3, issue_slots[6].out_uop.prs3 \n connect issue_slots[5].in_uop.bits.prs2, issue_slots[6].out_uop.prs2 \n connect issue_slots[5].in_uop.bits.prs1, issue_slots[6].out_uop.prs1 \n connect issue_slots[5].in_uop.bits.pdst, issue_slots[6].out_uop.pdst \n connect issue_slots[5].in_uop.bits.rxq_idx, issue_slots[6].out_uop.rxq_idx \n connect issue_slots[5].in_uop.bits.stq_idx, issue_slots[6].out_uop.stq_idx \n connect issue_slots[5].in_uop.bits.ldq_idx, issue_slots[6].out_uop.ldq_idx \n connect issue_slots[5].in_uop.bits.rob_idx, issue_slots[6].out_uop.rob_idx \n connect issue_slots[5].in_uop.bits.fp_ctrl.vec, issue_slots[6].out_uop.fp_ctrl.vec \n connect issue_slots[5].in_uop.bits.fp_ctrl.wflags, issue_slots[6].out_uop.fp_ctrl.wflags \n connect issue_slots[5].in_uop.bits.fp_ctrl.sqrt, issue_slots[6].out_uop.fp_ctrl.sqrt \n connect issue_slots[5].in_uop.bits.fp_ctrl.div, issue_slots[6].out_uop.fp_ctrl.div \n connect issue_slots[5].in_uop.bits.fp_ctrl.fma, issue_slots[6].out_uop.fp_ctrl.fma \n connect issue_slots[5].in_uop.bits.fp_ctrl.fastpipe, issue_slots[6].out_uop.fp_ctrl.fastpipe \n connect issue_slots[5].in_uop.bits.fp_ctrl.toint, issue_slots[6].out_uop.fp_ctrl.toint \n connect issue_slots[5].in_uop.bits.fp_ctrl.fromint, issue_slots[6].out_uop.fp_ctrl.fromint \n connect issue_slots[5].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[6].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[5].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[6].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[5].in_uop.bits.fp_ctrl.swap23, issue_slots[6].out_uop.fp_ctrl.swap23 \n connect issue_slots[5].in_uop.bits.fp_ctrl.swap12, issue_slots[6].out_uop.fp_ctrl.swap12 \n connect issue_slots[5].in_uop.bits.fp_ctrl.ren3, issue_slots[6].out_uop.fp_ctrl.ren3 \n connect issue_slots[5].in_uop.bits.fp_ctrl.ren2, issue_slots[6].out_uop.fp_ctrl.ren2 \n connect issue_slots[5].in_uop.bits.fp_ctrl.ren1, issue_slots[6].out_uop.fp_ctrl.ren1 \n connect issue_slots[5].in_uop.bits.fp_ctrl.wen, issue_slots[6].out_uop.fp_ctrl.wen \n connect issue_slots[5].in_uop.bits.fp_ctrl.ldst, issue_slots[6].out_uop.fp_ctrl.ldst \n connect issue_slots[5].in_uop.bits.op2_sel, issue_slots[6].out_uop.op2_sel \n connect issue_slots[5].in_uop.bits.op1_sel, issue_slots[6].out_uop.op1_sel \n connect issue_slots[5].in_uop.bits.imm_packed, issue_slots[6].out_uop.imm_packed \n connect issue_slots[5].in_uop.bits.pimm, issue_slots[6].out_uop.pimm \n connect issue_slots[5].in_uop.bits.imm_sel, issue_slots[6].out_uop.imm_sel \n connect issue_slots[5].in_uop.bits.imm_rename, issue_slots[6].out_uop.imm_rename \n connect issue_slots[5].in_uop.bits.taken, issue_slots[6].out_uop.taken \n connect issue_slots[5].in_uop.bits.pc_lob, issue_slots[6].out_uop.pc_lob \n connect issue_slots[5].in_uop.bits.edge_inst, issue_slots[6].out_uop.edge_inst \n connect issue_slots[5].in_uop.bits.ftq_idx, issue_slots[6].out_uop.ftq_idx \n connect issue_slots[5].in_uop.bits.is_mov, issue_slots[6].out_uop.is_mov \n connect issue_slots[5].in_uop.bits.is_rocc, issue_slots[6].out_uop.is_rocc \n connect issue_slots[5].in_uop.bits.is_sys_pc2epc, issue_slots[6].out_uop.is_sys_pc2epc \n connect issue_slots[5].in_uop.bits.is_eret, issue_slots[6].out_uop.is_eret \n connect issue_slots[5].in_uop.bits.is_amo, issue_slots[6].out_uop.is_amo \n connect issue_slots[5].in_uop.bits.is_sfence, issue_slots[6].out_uop.is_sfence \n connect issue_slots[5].in_uop.bits.is_fencei, issue_slots[6].out_uop.is_fencei \n connect issue_slots[5].in_uop.bits.is_fence, issue_slots[6].out_uop.is_fence \n connect issue_slots[5].in_uop.bits.is_sfb, issue_slots[6].out_uop.is_sfb \n connect issue_slots[5].in_uop.bits.br_type, issue_slots[6].out_uop.br_type \n connect issue_slots[5].in_uop.bits.br_tag, issue_slots[6].out_uop.br_tag \n connect issue_slots[5].in_uop.bits.br_mask, issue_slots[6].out_uop.br_mask \n connect issue_slots[5].in_uop.bits.dis_col_sel, issue_slots[6].out_uop.dis_col_sel \n connect issue_slots[5].in_uop.bits.iw_p3_bypass_hint, issue_slots[6].out_uop.iw_p3_bypass_hint \n connect issue_slots[5].in_uop.bits.iw_p2_bypass_hint, issue_slots[6].out_uop.iw_p2_bypass_hint \n connect issue_slots[5].in_uop.bits.iw_p1_bypass_hint, issue_slots[6].out_uop.iw_p1_bypass_hint \n connect issue_slots[5].in_uop.bits.iw_p2_speculative_child, issue_slots[6].out_uop.iw_p2_speculative_child \n connect issue_slots[5].in_uop.bits.iw_p1_speculative_child, issue_slots[6].out_uop.iw_p1_speculative_child \n connect issue_slots[5].in_uop.bits.iw_issued_partial_dgen, issue_slots[6].out_uop.iw_issued_partial_dgen \n connect issue_slots[5].in_uop.bits.iw_issued_partial_agen, issue_slots[6].out_uop.iw_issued_partial_agen \n connect issue_slots[5].in_uop.bits.iw_issued, issue_slots[6].out_uop.iw_issued \n connect issue_slots[5].in_uop.bits.fu_code[0], issue_slots[6].out_uop.fu_code[0] \n connect issue_slots[5].in_uop.bits.fu_code[1], issue_slots[6].out_uop.fu_code[1] \n connect issue_slots[5].in_uop.bits.fu_code[2], issue_slots[6].out_uop.fu_code[2] \n connect issue_slots[5].in_uop.bits.fu_code[3], issue_slots[6].out_uop.fu_code[3] \n connect issue_slots[5].in_uop.bits.fu_code[4], issue_slots[6].out_uop.fu_code[4] \n connect issue_slots[5].in_uop.bits.fu_code[5], issue_slots[6].out_uop.fu_code[5] \n connect issue_slots[5].in_uop.bits.fu_code[6], issue_slots[6].out_uop.fu_code[6] \n connect issue_slots[5].in_uop.bits.fu_code[7], issue_slots[6].out_uop.fu_code[7] \n connect issue_slots[5].in_uop.bits.fu_code[8], issue_slots[6].out_uop.fu_code[8] \n connect issue_slots[5].in_uop.bits.fu_code[9], issue_slots[6].out_uop.fu_code[9] \n connect issue_slots[5].in_uop.bits.iq_type[0], issue_slots[6].out_uop.iq_type[0] \n connect issue_slots[5].in_uop.bits.iq_type[1], issue_slots[6].out_uop.iq_type[1] \n connect issue_slots[5].in_uop.bits.iq_type[2], issue_slots[6].out_uop.iq_type[2] \n connect issue_slots[5].in_uop.bits.iq_type[3], issue_slots[6].out_uop.iq_type[3] \n connect issue_slots[5].in_uop.bits.debug_pc, issue_slots[6].out_uop.debug_pc \n connect issue_slots[5].in_uop.bits.is_rvc, issue_slots[6].out_uop.is_rvc \n connect issue_slots[5].in_uop.bits.debug_inst, issue_slots[6].out_uop.debug_inst \n connect issue_slots[5].in_uop.bits.inst, issue_slots[6].out_uop.inst \n node _T_173 = eq(shamts_oh[7], UInt<2>(0h2)) \n when _T_173 : \n connect issue_slots[5].in_uop.valid, issue_slots[7].will_be_valid \n connect issue_slots[5].in_uop.bits.debug_tsrc, issue_slots[7].out_uop.debug_tsrc \n connect issue_slots[5].in_uop.bits.debug_fsrc, issue_slots[7].out_uop.debug_fsrc \n connect issue_slots[5].in_uop.bits.bp_xcpt_if, issue_slots[7].out_uop.bp_xcpt_if \n connect issue_slots[5].in_uop.bits.bp_debug_if, issue_slots[7].out_uop.bp_debug_if \n connect issue_slots[5].in_uop.bits.xcpt_ma_if, issue_slots[7].out_uop.xcpt_ma_if \n connect issue_slots[5].in_uop.bits.xcpt_ae_if, issue_slots[7].out_uop.xcpt_ae_if \n connect issue_slots[5].in_uop.bits.xcpt_pf_if, issue_slots[7].out_uop.xcpt_pf_if \n connect issue_slots[5].in_uop.bits.fp_typ, issue_slots[7].out_uop.fp_typ \n connect issue_slots[5].in_uop.bits.fp_rm, issue_slots[7].out_uop.fp_rm \n connect issue_slots[5].in_uop.bits.fp_val, issue_slots[7].out_uop.fp_val \n connect issue_slots[5].in_uop.bits.fcn_op, issue_slots[7].out_uop.fcn_op \n connect issue_slots[5].in_uop.bits.fcn_dw, issue_slots[7].out_uop.fcn_dw \n connect issue_slots[5].in_uop.bits.frs3_en, issue_slots[7].out_uop.frs3_en \n connect issue_slots[5].in_uop.bits.lrs2_rtype, issue_slots[7].out_uop.lrs2_rtype \n connect issue_slots[5].in_uop.bits.lrs1_rtype, issue_slots[7].out_uop.lrs1_rtype \n connect issue_slots[5].in_uop.bits.dst_rtype, issue_slots[7].out_uop.dst_rtype \n connect issue_slots[5].in_uop.bits.lrs3, issue_slots[7].out_uop.lrs3 \n connect issue_slots[5].in_uop.bits.lrs2, issue_slots[7].out_uop.lrs2 \n connect issue_slots[5].in_uop.bits.lrs1, issue_slots[7].out_uop.lrs1 \n connect issue_slots[5].in_uop.bits.ldst, issue_slots[7].out_uop.ldst \n connect issue_slots[5].in_uop.bits.ldst_is_rs1, issue_slots[7].out_uop.ldst_is_rs1 \n connect issue_slots[5].in_uop.bits.csr_cmd, issue_slots[7].out_uop.csr_cmd \n connect issue_slots[5].in_uop.bits.flush_on_commit, issue_slots[7].out_uop.flush_on_commit \n connect issue_slots[5].in_uop.bits.is_unique, issue_slots[7].out_uop.is_unique \n connect issue_slots[5].in_uop.bits.uses_stq, issue_slots[7].out_uop.uses_stq \n connect issue_slots[5].in_uop.bits.uses_ldq, issue_slots[7].out_uop.uses_ldq \n connect issue_slots[5].in_uop.bits.mem_signed, issue_slots[7].out_uop.mem_signed \n connect issue_slots[5].in_uop.bits.mem_size, issue_slots[7].out_uop.mem_size \n connect issue_slots[5].in_uop.bits.mem_cmd, issue_slots[7].out_uop.mem_cmd \n connect issue_slots[5].in_uop.bits.exc_cause, issue_slots[7].out_uop.exc_cause \n connect issue_slots[5].in_uop.bits.exception, issue_slots[7].out_uop.exception \n connect issue_slots[5].in_uop.bits.stale_pdst, issue_slots[7].out_uop.stale_pdst \n connect issue_slots[5].in_uop.bits.ppred_busy, issue_slots[7].out_uop.ppred_busy \n connect issue_slots[5].in_uop.bits.prs3_busy, issue_slots[7].out_uop.prs3_busy \n connect issue_slots[5].in_uop.bits.prs2_busy, issue_slots[7].out_uop.prs2_busy \n connect issue_slots[5].in_uop.bits.prs1_busy, issue_slots[7].out_uop.prs1_busy \n connect issue_slots[5].in_uop.bits.ppred, issue_slots[7].out_uop.ppred \n connect issue_slots[5].in_uop.bits.prs3, issue_slots[7].out_uop.prs3 \n connect issue_slots[5].in_uop.bits.prs2, issue_slots[7].out_uop.prs2 \n connect issue_slots[5].in_uop.bits.prs1, issue_slots[7].out_uop.prs1 \n connect issue_slots[5].in_uop.bits.pdst, issue_slots[7].out_uop.pdst \n connect issue_slots[5].in_uop.bits.rxq_idx, issue_slots[7].out_uop.rxq_idx \n connect issue_slots[5].in_uop.bits.stq_idx, issue_slots[7].out_uop.stq_idx \n connect issue_slots[5].in_uop.bits.ldq_idx, issue_slots[7].out_uop.ldq_idx \n connect issue_slots[5].in_uop.bits.rob_idx, issue_slots[7].out_uop.rob_idx \n connect issue_slots[5].in_uop.bits.fp_ctrl.vec, issue_slots[7].out_uop.fp_ctrl.vec \n connect issue_slots[5].in_uop.bits.fp_ctrl.wflags, issue_slots[7].out_uop.fp_ctrl.wflags \n connect issue_slots[5].in_uop.bits.fp_ctrl.sqrt, issue_slots[7].out_uop.fp_ctrl.sqrt \n connect issue_slots[5].in_uop.bits.fp_ctrl.div, issue_slots[7].out_uop.fp_ctrl.div \n connect issue_slots[5].in_uop.bits.fp_ctrl.fma, issue_slots[7].out_uop.fp_ctrl.fma \n connect issue_slots[5].in_uop.bits.fp_ctrl.fastpipe, issue_slots[7].out_uop.fp_ctrl.fastpipe \n connect issue_slots[5].in_uop.bits.fp_ctrl.toint, issue_slots[7].out_uop.fp_ctrl.toint \n connect issue_slots[5].in_uop.bits.fp_ctrl.fromint, issue_slots[7].out_uop.fp_ctrl.fromint \n connect issue_slots[5].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[7].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[5].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[7].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[5].in_uop.bits.fp_ctrl.swap23, issue_slots[7].out_uop.fp_ctrl.swap23 \n connect issue_slots[5].in_uop.bits.fp_ctrl.swap12, issue_slots[7].out_uop.fp_ctrl.swap12 \n connect issue_slots[5].in_uop.bits.fp_ctrl.ren3, issue_slots[7].out_uop.fp_ctrl.ren3 \n connect issue_slots[5].in_uop.bits.fp_ctrl.ren2, issue_slots[7].out_uop.fp_ctrl.ren2 \n connect issue_slots[5].in_uop.bits.fp_ctrl.ren1, issue_slots[7].out_uop.fp_ctrl.ren1 \n connect issue_slots[5].in_uop.bits.fp_ctrl.wen, issue_slots[7].out_uop.fp_ctrl.wen \n connect issue_slots[5].in_uop.bits.fp_ctrl.ldst, issue_slots[7].out_uop.fp_ctrl.ldst \n connect issue_slots[5].in_uop.bits.op2_sel, issue_slots[7].out_uop.op2_sel \n connect issue_slots[5].in_uop.bits.op1_sel, issue_slots[7].out_uop.op1_sel \n connect issue_slots[5].in_uop.bits.imm_packed, issue_slots[7].out_uop.imm_packed \n connect issue_slots[5].in_uop.bits.pimm, issue_slots[7].out_uop.pimm \n connect issue_slots[5].in_uop.bits.imm_sel, issue_slots[7].out_uop.imm_sel \n connect issue_slots[5].in_uop.bits.imm_rename, issue_slots[7].out_uop.imm_rename \n connect issue_slots[5].in_uop.bits.taken, issue_slots[7].out_uop.taken \n connect issue_slots[5].in_uop.bits.pc_lob, issue_slots[7].out_uop.pc_lob \n connect issue_slots[5].in_uop.bits.edge_inst, issue_slots[7].out_uop.edge_inst \n connect issue_slots[5].in_uop.bits.ftq_idx, issue_slots[7].out_uop.ftq_idx \n connect issue_slots[5].in_uop.bits.is_mov, issue_slots[7].out_uop.is_mov \n connect issue_slots[5].in_uop.bits.is_rocc, issue_slots[7].out_uop.is_rocc \n connect issue_slots[5].in_uop.bits.is_sys_pc2epc, issue_slots[7].out_uop.is_sys_pc2epc \n connect issue_slots[5].in_uop.bits.is_eret, issue_slots[7].out_uop.is_eret \n connect issue_slots[5].in_uop.bits.is_amo, issue_slots[7].out_uop.is_amo \n connect issue_slots[5].in_uop.bits.is_sfence, issue_slots[7].out_uop.is_sfence \n connect issue_slots[5].in_uop.bits.is_fencei, issue_slots[7].out_uop.is_fencei \n connect issue_slots[5].in_uop.bits.is_fence, issue_slots[7].out_uop.is_fence \n connect issue_slots[5].in_uop.bits.is_sfb, issue_slots[7].out_uop.is_sfb \n connect issue_slots[5].in_uop.bits.br_type, issue_slots[7].out_uop.br_type \n connect issue_slots[5].in_uop.bits.br_tag, issue_slots[7].out_uop.br_tag \n connect issue_slots[5].in_uop.bits.br_mask, issue_slots[7].out_uop.br_mask \n connect issue_slots[5].in_uop.bits.dis_col_sel, issue_slots[7].out_uop.dis_col_sel \n connect issue_slots[5].in_uop.bits.iw_p3_bypass_hint, issue_slots[7].out_uop.iw_p3_bypass_hint \n connect issue_slots[5].in_uop.bits.iw_p2_bypass_hint, issue_slots[7].out_uop.iw_p2_bypass_hint \n connect issue_slots[5].in_uop.bits.iw_p1_bypass_hint, issue_slots[7].out_uop.iw_p1_bypass_hint \n connect issue_slots[5].in_uop.bits.iw_p2_speculative_child, issue_slots[7].out_uop.iw_p2_speculative_child \n connect issue_slots[5].in_uop.bits.iw_p1_speculative_child, issue_slots[7].out_uop.iw_p1_speculative_child \n connect issue_slots[5].in_uop.bits.iw_issued_partial_dgen, issue_slots[7].out_uop.iw_issued_partial_dgen \n connect issue_slots[5].in_uop.bits.iw_issued_partial_agen, issue_slots[7].out_uop.iw_issued_partial_agen \n connect issue_slots[5].in_uop.bits.iw_issued, issue_slots[7].out_uop.iw_issued \n connect issue_slots[5].in_uop.bits.fu_code[0], issue_slots[7].out_uop.fu_code[0] \n connect issue_slots[5].in_uop.bits.fu_code[1], issue_slots[7].out_uop.fu_code[1] \n connect issue_slots[5].in_uop.bits.fu_code[2], issue_slots[7].out_uop.fu_code[2] \n connect issue_slots[5].in_uop.bits.fu_code[3], issue_slots[7].out_uop.fu_code[3] \n connect issue_slots[5].in_uop.bits.fu_code[4], issue_slots[7].out_uop.fu_code[4] \n connect issue_slots[5].in_uop.bits.fu_code[5], issue_slots[7].out_uop.fu_code[5] \n connect issue_slots[5].in_uop.bits.fu_code[6], issue_slots[7].out_uop.fu_code[6] \n connect issue_slots[5].in_uop.bits.fu_code[7], issue_slots[7].out_uop.fu_code[7] \n connect issue_slots[5].in_uop.bits.fu_code[8], issue_slots[7].out_uop.fu_code[8] \n connect issue_slots[5].in_uop.bits.fu_code[9], issue_slots[7].out_uop.fu_code[9] \n connect issue_slots[5].in_uop.bits.iq_type[0], issue_slots[7].out_uop.iq_type[0] \n connect issue_slots[5].in_uop.bits.iq_type[1], issue_slots[7].out_uop.iq_type[1] \n connect issue_slots[5].in_uop.bits.iq_type[2], issue_slots[7].out_uop.iq_type[2] \n connect issue_slots[5].in_uop.bits.iq_type[3], issue_slots[7].out_uop.iq_type[3] \n connect issue_slots[5].in_uop.bits.debug_pc, issue_slots[7].out_uop.debug_pc \n connect issue_slots[5].in_uop.bits.is_rvc, issue_slots[7].out_uop.is_rvc \n connect issue_slots[5].in_uop.bits.debug_inst, issue_slots[7].out_uop.debug_inst \n connect issue_slots[5].in_uop.bits.inst, issue_slots[7].out_uop.inst \n node _issue_slots_5_clear_T = neq(shamts_oh[5], UInt<1>(0h0)) \n connect issue_slots[5].clear, _issue_slots_5_clear_T \n connect issue_slots[6].in_uop.valid, UInt<1>(0h0) \n connect issue_slots[6].in_uop.bits.debug_tsrc, issue_slots[7].out_uop.debug_tsrc \n connect issue_slots[6].in_uop.bits.debug_fsrc, issue_slots[7].out_uop.debug_fsrc \n connect issue_slots[6].in_uop.bits.bp_xcpt_if, issue_slots[7].out_uop.bp_xcpt_if \n connect issue_slots[6].in_uop.bits.bp_debug_if, issue_slots[7].out_uop.bp_debug_if \n connect issue_slots[6].in_uop.bits.xcpt_ma_if, issue_slots[7].out_uop.xcpt_ma_if \n connect issue_slots[6].in_uop.bits.xcpt_ae_if, issue_slots[7].out_uop.xcpt_ae_if \n connect issue_slots[6].in_uop.bits.xcpt_pf_if, issue_slots[7].out_uop.xcpt_pf_if \n connect issue_slots[6].in_uop.bits.fp_typ, issue_slots[7].out_uop.fp_typ \n connect issue_slots[6].in_uop.bits.fp_rm, issue_slots[7].out_uop.fp_rm \n connect issue_slots[6].in_uop.bits.fp_val, issue_slots[7].out_uop.fp_val \n connect issue_slots[6].in_uop.bits.fcn_op, issue_slots[7].out_uop.fcn_op \n connect issue_slots[6].in_uop.bits.fcn_dw, issue_slots[7].out_uop.fcn_dw \n connect issue_slots[6].in_uop.bits.frs3_en, issue_slots[7].out_uop.frs3_en \n connect issue_slots[6].in_uop.bits.lrs2_rtype, issue_slots[7].out_uop.lrs2_rtype \n connect issue_slots[6].in_uop.bits.lrs1_rtype, issue_slots[7].out_uop.lrs1_rtype \n connect issue_slots[6].in_uop.bits.dst_rtype, issue_slots[7].out_uop.dst_rtype \n connect issue_slots[6].in_uop.bits.lrs3, issue_slots[7].out_uop.lrs3 \n connect issue_slots[6].in_uop.bits.lrs2, issue_slots[7].out_uop.lrs2 \n connect issue_slots[6].in_uop.bits.lrs1, issue_slots[7].out_uop.lrs1 \n connect issue_slots[6].in_uop.bits.ldst, issue_slots[7].out_uop.ldst \n connect issue_slots[6].in_uop.bits.ldst_is_rs1, issue_slots[7].out_uop.ldst_is_rs1 \n connect issue_slots[6].in_uop.bits.csr_cmd, issue_slots[7].out_uop.csr_cmd \n connect issue_slots[6].in_uop.bits.flush_on_commit, issue_slots[7].out_uop.flush_on_commit \n connect issue_slots[6].in_uop.bits.is_unique, issue_slots[7].out_uop.is_unique \n connect issue_slots[6].in_uop.bits.uses_stq, issue_slots[7].out_uop.uses_stq \n connect issue_slots[6].in_uop.bits.uses_ldq, issue_slots[7].out_uop.uses_ldq \n connect issue_slots[6].in_uop.bits.mem_signed, issue_slots[7].out_uop.mem_signed \n connect issue_slots[6].in_uop.bits.mem_size, issue_slots[7].out_uop.mem_size \n connect issue_slots[6].in_uop.bits.mem_cmd, issue_slots[7].out_uop.mem_cmd \n connect issue_slots[6].in_uop.bits.exc_cause, issue_slots[7].out_uop.exc_cause \n connect issue_slots[6].in_uop.bits.exception, issue_slots[7].out_uop.exception \n connect issue_slots[6].in_uop.bits.stale_pdst, issue_slots[7].out_uop.stale_pdst \n connect issue_slots[6].in_uop.bits.ppred_busy, issue_slots[7].out_uop.ppred_busy \n connect issue_slots[6].in_uop.bits.prs3_busy, issue_slots[7].out_uop.prs3_busy \n connect issue_slots[6].in_uop.bits.prs2_busy, issue_slots[7].out_uop.prs2_busy \n connect issue_slots[6].in_uop.bits.prs1_busy, issue_slots[7].out_uop.prs1_busy \n connect issue_slots[6].in_uop.bits.ppred, issue_slots[7].out_uop.ppred \n connect issue_slots[6].in_uop.bits.prs3, issue_slots[7].out_uop.prs3 \n connect issue_slots[6].in_uop.bits.prs2, issue_slots[7].out_uop.prs2 \n connect issue_slots[6].in_uop.bits.prs1, issue_slots[7].out_uop.prs1 \n connect issue_slots[6].in_uop.bits.pdst, issue_slots[7].out_uop.pdst \n connect issue_slots[6].in_uop.bits.rxq_idx, issue_slots[7].out_uop.rxq_idx \n connect issue_slots[6].in_uop.bits.stq_idx, issue_slots[7].out_uop.stq_idx \n connect issue_slots[6].in_uop.bits.ldq_idx, issue_slots[7].out_uop.ldq_idx \n connect issue_slots[6].in_uop.bits.rob_idx, issue_slots[7].out_uop.rob_idx \n connect issue_slots[6].in_uop.bits.fp_ctrl.vec, issue_slots[7].out_uop.fp_ctrl.vec \n connect issue_slots[6].in_uop.bits.fp_ctrl.wflags, issue_slots[7].out_uop.fp_ctrl.wflags \n connect issue_slots[6].in_uop.bits.fp_ctrl.sqrt, issue_slots[7].out_uop.fp_ctrl.sqrt \n connect issue_slots[6].in_uop.bits.fp_ctrl.div, issue_slots[7].out_uop.fp_ctrl.div \n connect issue_slots[6].in_uop.bits.fp_ctrl.fma, issue_slots[7].out_uop.fp_ctrl.fma \n connect issue_slots[6].in_uop.bits.fp_ctrl.fastpipe, issue_slots[7].out_uop.fp_ctrl.fastpipe \n connect issue_slots[6].in_uop.bits.fp_ctrl.toint, issue_slots[7].out_uop.fp_ctrl.toint \n connect issue_slots[6].in_uop.bits.fp_ctrl.fromint, issue_slots[7].out_uop.fp_ctrl.fromint \n connect issue_slots[6].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[7].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[6].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[7].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[6].in_uop.bits.fp_ctrl.swap23, issue_slots[7].out_uop.fp_ctrl.swap23 \n connect issue_slots[6].in_uop.bits.fp_ctrl.swap12, issue_slots[7].out_uop.fp_ctrl.swap12 \n connect issue_slots[6].in_uop.bits.fp_ctrl.ren3, issue_slots[7].out_uop.fp_ctrl.ren3 \n connect issue_slots[6].in_uop.bits.fp_ctrl.ren2, issue_slots[7].out_uop.fp_ctrl.ren2 \n connect issue_slots[6].in_uop.bits.fp_ctrl.ren1, issue_slots[7].out_uop.fp_ctrl.ren1 \n connect issue_slots[6].in_uop.bits.fp_ctrl.wen, issue_slots[7].out_uop.fp_ctrl.wen \n connect issue_slots[6].in_uop.bits.fp_ctrl.ldst, issue_slots[7].out_uop.fp_ctrl.ldst \n connect issue_slots[6].in_uop.bits.op2_sel, issue_slots[7].out_uop.op2_sel \n connect issue_slots[6].in_uop.bits.op1_sel, issue_slots[7].out_uop.op1_sel \n connect issue_slots[6].in_uop.bits.imm_packed, issue_slots[7].out_uop.imm_packed \n connect issue_slots[6].in_uop.bits.pimm, issue_slots[7].out_uop.pimm \n connect issue_slots[6].in_uop.bits.imm_sel, issue_slots[7].out_uop.imm_sel \n connect issue_slots[6].in_uop.bits.imm_rename, issue_slots[7].out_uop.imm_rename \n connect issue_slots[6].in_uop.bits.taken, issue_slots[7].out_uop.taken \n connect issue_slots[6].in_uop.bits.pc_lob, issue_slots[7].out_uop.pc_lob \n connect issue_slots[6].in_uop.bits.edge_inst, issue_slots[7].out_uop.edge_inst \n connect issue_slots[6].in_uop.bits.ftq_idx, issue_slots[7].out_uop.ftq_idx \n connect issue_slots[6].in_uop.bits.is_mov, issue_slots[7].out_uop.is_mov \n connect issue_slots[6].in_uop.bits.is_rocc, issue_slots[7].out_uop.is_rocc \n connect issue_slots[6].in_uop.bits.is_sys_pc2epc, issue_slots[7].out_uop.is_sys_pc2epc \n connect issue_slots[6].in_uop.bits.is_eret, issue_slots[7].out_uop.is_eret \n connect issue_slots[6].in_uop.bits.is_amo, issue_slots[7].out_uop.is_amo \n connect issue_slots[6].in_uop.bits.is_sfence, issue_slots[7].out_uop.is_sfence \n connect issue_slots[6].in_uop.bits.is_fencei, issue_slots[7].out_uop.is_fencei \n connect issue_slots[6].in_uop.bits.is_fence, issue_slots[7].out_uop.is_fence \n connect issue_slots[6].in_uop.bits.is_sfb, issue_slots[7].out_uop.is_sfb \n connect issue_slots[6].in_uop.bits.br_type, issue_slots[7].out_uop.br_type \n connect issue_slots[6].in_uop.bits.br_tag, issue_slots[7].out_uop.br_tag \n connect issue_slots[6].in_uop.bits.br_mask, issue_slots[7].out_uop.br_mask \n connect issue_slots[6].in_uop.bits.dis_col_sel, issue_slots[7].out_uop.dis_col_sel \n connect issue_slots[6].in_uop.bits.iw_p3_bypass_hint, issue_slots[7].out_uop.iw_p3_bypass_hint \n connect issue_slots[6].in_uop.bits.iw_p2_bypass_hint, issue_slots[7].out_uop.iw_p2_bypass_hint \n connect issue_slots[6].in_uop.bits.iw_p1_bypass_hint, issue_slots[7].out_uop.iw_p1_bypass_hint \n connect issue_slots[6].in_uop.bits.iw_p2_speculative_child, issue_slots[7].out_uop.iw_p2_speculative_child \n connect issue_slots[6].in_uop.bits.iw_p1_speculative_child, issue_slots[7].out_uop.iw_p1_speculative_child \n connect issue_slots[6].in_uop.bits.iw_issued_partial_dgen, issue_slots[7].out_uop.iw_issued_partial_dgen \n connect issue_slots[6].in_uop.bits.iw_issued_partial_agen, issue_slots[7].out_uop.iw_issued_partial_agen \n connect issue_slots[6].in_uop.bits.iw_issued, issue_slots[7].out_uop.iw_issued \n connect issue_slots[6].in_uop.bits.fu_code[0], issue_slots[7].out_uop.fu_code[0] \n connect issue_slots[6].in_uop.bits.fu_code[1], issue_slots[7].out_uop.fu_code[1] \n connect issue_slots[6].in_uop.bits.fu_code[2], issue_slots[7].out_uop.fu_code[2] \n connect issue_slots[6].in_uop.bits.fu_code[3], issue_slots[7].out_uop.fu_code[3] \n connect issue_slots[6].in_uop.bits.fu_code[4], issue_slots[7].out_uop.fu_code[4] \n connect issue_slots[6].in_uop.bits.fu_code[5], issue_slots[7].out_uop.fu_code[5] \n connect issue_slots[6].in_uop.bits.fu_code[6], issue_slots[7].out_uop.fu_code[6] \n connect issue_slots[6].in_uop.bits.fu_code[7], issue_slots[7].out_uop.fu_code[7] \n connect issue_slots[6].in_uop.bits.fu_code[8], issue_slots[7].out_uop.fu_code[8] \n connect issue_slots[6].in_uop.bits.fu_code[9], issue_slots[7].out_uop.fu_code[9] \n connect issue_slots[6].in_uop.bits.iq_type[0], issue_slots[7].out_uop.iq_type[0] \n connect issue_slots[6].in_uop.bits.iq_type[1], issue_slots[7].out_uop.iq_type[1] \n connect issue_slots[6].in_uop.bits.iq_type[2], issue_slots[7].out_uop.iq_type[2] \n connect issue_slots[6].in_uop.bits.iq_type[3], issue_slots[7].out_uop.iq_type[3] \n connect issue_slots[6].in_uop.bits.debug_pc, issue_slots[7].out_uop.debug_pc \n connect issue_slots[6].in_uop.bits.is_rvc, issue_slots[7].out_uop.is_rvc \n connect issue_slots[6].in_uop.bits.debug_inst, issue_slots[7].out_uop.debug_inst \n connect issue_slots[6].in_uop.bits.inst, issue_slots[7].out_uop.inst \n node _T_174 = eq(shamts_oh[7], UInt<1>(0h1)) \n when _T_174 : \n connect issue_slots[6].in_uop.valid, issue_slots[7].will_be_valid \n connect issue_slots[6].in_uop.bits.debug_tsrc, issue_slots[7].out_uop.debug_tsrc \n connect issue_slots[6].in_uop.bits.debug_fsrc, issue_slots[7].out_uop.debug_fsrc \n connect issue_slots[6].in_uop.bits.bp_xcpt_if, issue_slots[7].out_uop.bp_xcpt_if \n connect issue_slots[6].in_uop.bits.bp_debug_if, issue_slots[7].out_uop.bp_debug_if \n connect issue_slots[6].in_uop.bits.xcpt_ma_if, issue_slots[7].out_uop.xcpt_ma_if \n connect issue_slots[6].in_uop.bits.xcpt_ae_if, issue_slots[7].out_uop.xcpt_ae_if \n connect issue_slots[6].in_uop.bits.xcpt_pf_if, issue_slots[7].out_uop.xcpt_pf_if \n connect issue_slots[6].in_uop.bits.fp_typ, issue_slots[7].out_uop.fp_typ \n connect issue_slots[6].in_uop.bits.fp_rm, issue_slots[7].out_uop.fp_rm \n connect issue_slots[6].in_uop.bits.fp_val, issue_slots[7].out_uop.fp_val \n connect issue_slots[6].in_uop.bits.fcn_op, issue_slots[7].out_uop.fcn_op \n connect issue_slots[6].in_uop.bits.fcn_dw, issue_slots[7].out_uop.fcn_dw \n connect issue_slots[6].in_uop.bits.frs3_en, issue_slots[7].out_uop.frs3_en \n connect issue_slots[6].in_uop.bits.lrs2_rtype, issue_slots[7].out_uop.lrs2_rtype \n connect issue_slots[6].in_uop.bits.lrs1_rtype, issue_slots[7].out_uop.lrs1_rtype \n connect issue_slots[6].in_uop.bits.dst_rtype, issue_slots[7].out_uop.dst_rtype \n connect issue_slots[6].in_uop.bits.lrs3, issue_slots[7].out_uop.lrs3 \n connect issue_slots[6].in_uop.bits.lrs2, issue_slots[7].out_uop.lrs2 \n connect issue_slots[6].in_uop.bits.lrs1, issue_slots[7].out_uop.lrs1 \n connect issue_slots[6].in_uop.bits.ldst, issue_slots[7].out_uop.ldst \n connect issue_slots[6].in_uop.bits.ldst_is_rs1, issue_slots[7].out_uop.ldst_is_rs1 \n connect issue_slots[6].in_uop.bits.csr_cmd, issue_slots[7].out_uop.csr_cmd \n connect issue_slots[6].in_uop.bits.flush_on_commit, issue_slots[7].out_uop.flush_on_commit \n connect issue_slots[6].in_uop.bits.is_unique, issue_slots[7].out_uop.is_unique \n connect issue_slots[6].in_uop.bits.uses_stq, issue_slots[7].out_uop.uses_stq \n connect issue_slots[6].in_uop.bits.uses_ldq, issue_slots[7].out_uop.uses_ldq \n connect issue_slots[6].in_uop.bits.mem_signed, issue_slots[7].out_uop.mem_signed \n connect issue_slots[6].in_uop.bits.mem_size, issue_slots[7].out_uop.mem_size \n connect issue_slots[6].in_uop.bits.mem_cmd, issue_slots[7].out_uop.mem_cmd \n connect issue_slots[6].in_uop.bits.exc_cause, issue_slots[7].out_uop.exc_cause \n connect issue_slots[6].in_uop.bits.exception, issue_slots[7].out_uop.exception \n connect issue_slots[6].in_uop.bits.stale_pdst, issue_slots[7].out_uop.stale_pdst \n connect issue_slots[6].in_uop.bits.ppred_busy, issue_slots[7].out_uop.ppred_busy \n connect issue_slots[6].in_uop.bits.prs3_busy, issue_slots[7].out_uop.prs3_busy \n connect issue_slots[6].in_uop.bits.prs2_busy, issue_slots[7].out_uop.prs2_busy \n connect issue_slots[6].in_uop.bits.prs1_busy, issue_slots[7].out_uop.prs1_busy \n connect issue_slots[6].in_uop.bits.ppred, issue_slots[7].out_uop.ppred \n connect issue_slots[6].in_uop.bits.prs3, issue_slots[7].out_uop.prs3 \n connect issue_slots[6].in_uop.bits.prs2, issue_slots[7].out_uop.prs2 \n connect issue_slots[6].in_uop.bits.prs1, issue_slots[7].out_uop.prs1 \n connect issue_slots[6].in_uop.bits.pdst, issue_slots[7].out_uop.pdst \n connect issue_slots[6].in_uop.bits.rxq_idx, issue_slots[7].out_uop.rxq_idx \n connect issue_slots[6].in_uop.bits.stq_idx, issue_slots[7].out_uop.stq_idx \n connect issue_slots[6].in_uop.bits.ldq_idx, issue_slots[7].out_uop.ldq_idx \n connect issue_slots[6].in_uop.bits.rob_idx, issue_slots[7].out_uop.rob_idx \n connect issue_slots[6].in_uop.bits.fp_ctrl.vec, issue_slots[7].out_uop.fp_ctrl.vec \n connect issue_slots[6].in_uop.bits.fp_ctrl.wflags, issue_slots[7].out_uop.fp_ctrl.wflags \n connect issue_slots[6].in_uop.bits.fp_ctrl.sqrt, issue_slots[7].out_uop.fp_ctrl.sqrt \n connect issue_slots[6].in_uop.bits.fp_ctrl.div, issue_slots[7].out_uop.fp_ctrl.div \n connect issue_slots[6].in_uop.bits.fp_ctrl.fma, issue_slots[7].out_uop.fp_ctrl.fma \n connect issue_slots[6].in_uop.bits.fp_ctrl.fastpipe, issue_slots[7].out_uop.fp_ctrl.fastpipe \n connect issue_slots[6].in_uop.bits.fp_ctrl.toint, issue_slots[7].out_uop.fp_ctrl.toint \n connect issue_slots[6].in_uop.bits.fp_ctrl.fromint, issue_slots[7].out_uop.fp_ctrl.fromint \n connect issue_slots[6].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[7].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[6].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[7].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[6].in_uop.bits.fp_ctrl.swap23, issue_slots[7].out_uop.fp_ctrl.swap23 \n connect issue_slots[6].in_uop.bits.fp_ctrl.swap12, issue_slots[7].out_uop.fp_ctrl.swap12 \n connect issue_slots[6].in_uop.bits.fp_ctrl.ren3, issue_slots[7].out_uop.fp_ctrl.ren3 \n connect issue_slots[6].in_uop.bits.fp_ctrl.ren2, issue_slots[7].out_uop.fp_ctrl.ren2 \n connect issue_slots[6].in_uop.bits.fp_ctrl.ren1, issue_slots[7].out_uop.fp_ctrl.ren1 \n connect issue_slots[6].in_uop.bits.fp_ctrl.wen, issue_slots[7].out_uop.fp_ctrl.wen \n connect issue_slots[6].in_uop.bits.fp_ctrl.ldst, issue_slots[7].out_uop.fp_ctrl.ldst \n connect issue_slots[6].in_uop.bits.op2_sel, issue_slots[7].out_uop.op2_sel \n connect issue_slots[6].in_uop.bits.op1_sel, issue_slots[7].out_uop.op1_sel \n connect issue_slots[6].in_uop.bits.imm_packed, issue_slots[7].out_uop.imm_packed \n connect issue_slots[6].in_uop.bits.pimm, issue_slots[7].out_uop.pimm \n connect issue_slots[6].in_uop.bits.imm_sel, issue_slots[7].out_uop.imm_sel \n connect issue_slots[6].in_uop.bits.imm_rename, issue_slots[7].out_uop.imm_rename \n connect issue_slots[6].in_uop.bits.taken, issue_slots[7].out_uop.taken \n connect issue_slots[6].in_uop.bits.pc_lob, issue_slots[7].out_uop.pc_lob \n connect issue_slots[6].in_uop.bits.edge_inst, issue_slots[7].out_uop.edge_inst \n connect issue_slots[6].in_uop.bits.ftq_idx, issue_slots[7].out_uop.ftq_idx \n connect issue_slots[6].in_uop.bits.is_mov, issue_slots[7].out_uop.is_mov \n connect issue_slots[6].in_uop.bits.is_rocc, issue_slots[7].out_uop.is_rocc \n connect issue_slots[6].in_uop.bits.is_sys_pc2epc, issue_slots[7].out_uop.is_sys_pc2epc \n connect issue_slots[6].in_uop.bits.is_eret, issue_slots[7].out_uop.is_eret \n connect issue_slots[6].in_uop.bits.is_amo, issue_slots[7].out_uop.is_amo \n connect issue_slots[6].in_uop.bits.is_sfence, issue_slots[7].out_uop.is_sfence \n connect issue_slots[6].in_uop.bits.is_fencei, issue_slots[7].out_uop.is_fencei \n connect issue_slots[6].in_uop.bits.is_fence, issue_slots[7].out_uop.is_fence \n connect issue_slots[6].in_uop.bits.is_sfb, issue_slots[7].out_uop.is_sfb \n connect issue_slots[6].in_uop.bits.br_type, issue_slots[7].out_uop.br_type \n connect issue_slots[6].in_uop.bits.br_tag, issue_slots[7].out_uop.br_tag \n connect issue_slots[6].in_uop.bits.br_mask, issue_slots[7].out_uop.br_mask \n connect issue_slots[6].in_uop.bits.dis_col_sel, issue_slots[7].out_uop.dis_col_sel \n connect issue_slots[6].in_uop.bits.iw_p3_bypass_hint, issue_slots[7].out_uop.iw_p3_bypass_hint \n connect issue_slots[6].in_uop.bits.iw_p2_bypass_hint, issue_slots[7].out_uop.iw_p2_bypass_hint \n connect issue_slots[6].in_uop.bits.iw_p1_bypass_hint, issue_slots[7].out_uop.iw_p1_bypass_hint \n connect issue_slots[6].in_uop.bits.iw_p2_speculative_child, issue_slots[7].out_uop.iw_p2_speculative_child \n connect issue_slots[6].in_uop.bits.iw_p1_speculative_child, issue_slots[7].out_uop.iw_p1_speculative_child \n connect issue_slots[6].in_uop.bits.iw_issued_partial_dgen, issue_slots[7].out_uop.iw_issued_partial_dgen \n connect issue_slots[6].in_uop.bits.iw_issued_partial_agen, issue_slots[7].out_uop.iw_issued_partial_agen \n connect issue_slots[6].in_uop.bits.iw_issued, issue_slots[7].out_uop.iw_issued \n connect issue_slots[6].in_uop.bits.fu_code[0], issue_slots[7].out_uop.fu_code[0] \n connect issue_slots[6].in_uop.bits.fu_code[1], issue_slots[7].out_uop.fu_code[1] \n connect issue_slots[6].in_uop.bits.fu_code[2], issue_slots[7].out_uop.fu_code[2] \n connect issue_slots[6].in_uop.bits.fu_code[3], issue_slots[7].out_uop.fu_code[3] \n connect issue_slots[6].in_uop.bits.fu_code[4], issue_slots[7].out_uop.fu_code[4] \n connect issue_slots[6].in_uop.bits.fu_code[5], issue_slots[7].out_uop.fu_code[5] \n connect issue_slots[6].in_uop.bits.fu_code[6], issue_slots[7].out_uop.fu_code[6] \n connect issue_slots[6].in_uop.bits.fu_code[7], issue_slots[7].out_uop.fu_code[7] \n connect issue_slots[6].in_uop.bits.fu_code[8], issue_slots[7].out_uop.fu_code[8] \n connect issue_slots[6].in_uop.bits.fu_code[9], issue_slots[7].out_uop.fu_code[9] \n connect issue_slots[6].in_uop.bits.iq_type[0], issue_slots[7].out_uop.iq_type[0] \n connect issue_slots[6].in_uop.bits.iq_type[1], issue_slots[7].out_uop.iq_type[1] \n connect issue_slots[6].in_uop.bits.iq_type[2], issue_slots[7].out_uop.iq_type[2] \n connect issue_slots[6].in_uop.bits.iq_type[3], issue_slots[7].out_uop.iq_type[3] \n connect issue_slots[6].in_uop.bits.debug_pc, issue_slots[7].out_uop.debug_pc \n connect issue_slots[6].in_uop.bits.is_rvc, issue_slots[7].out_uop.is_rvc \n connect issue_slots[6].in_uop.bits.debug_inst, issue_slots[7].out_uop.debug_inst \n connect issue_slots[6].in_uop.bits.inst, issue_slots[7].out_uop.inst \n node _T_175 = eq(shamts_oh[8], UInt<2>(0h2)) \n when _T_175 : \n connect issue_slots[6].in_uop.valid, issue_slots[8].will_be_valid \n connect issue_slots[6].in_uop.bits.debug_tsrc, issue_slots[8].out_uop.debug_tsrc \n connect issue_slots[6].in_uop.bits.debug_fsrc, issue_slots[8].out_uop.debug_fsrc \n connect issue_slots[6].in_uop.bits.bp_xcpt_if, issue_slots[8].out_uop.bp_xcpt_if \n connect issue_slots[6].in_uop.bits.bp_debug_if, issue_slots[8].out_uop.bp_debug_if \n connect issue_slots[6].in_uop.bits.xcpt_ma_if, issue_slots[8].out_uop.xcpt_ma_if \n connect issue_slots[6].in_uop.bits.xcpt_ae_if, issue_slots[8].out_uop.xcpt_ae_if \n connect issue_slots[6].in_uop.bits.xcpt_pf_if, issue_slots[8].out_uop.xcpt_pf_if \n connect issue_slots[6].in_uop.bits.fp_typ, issue_slots[8].out_uop.fp_typ \n connect issue_slots[6].in_uop.bits.fp_rm, issue_slots[8].out_uop.fp_rm \n connect issue_slots[6].in_uop.bits.fp_val, issue_slots[8].out_uop.fp_val \n connect issue_slots[6].in_uop.bits.fcn_op, issue_slots[8].out_uop.fcn_op \n connect issue_slots[6].in_uop.bits.fcn_dw, issue_slots[8].out_uop.fcn_dw \n connect issue_slots[6].in_uop.bits.frs3_en, issue_slots[8].out_uop.frs3_en \n connect issue_slots[6].in_uop.bits.lrs2_rtype, issue_slots[8].out_uop.lrs2_rtype \n connect issue_slots[6].in_uop.bits.lrs1_rtype, issue_slots[8].out_uop.lrs1_rtype \n connect issue_slots[6].in_uop.bits.dst_rtype, issue_slots[8].out_uop.dst_rtype \n connect issue_slots[6].in_uop.bits.lrs3, issue_slots[8].out_uop.lrs3 \n connect issue_slots[6].in_uop.bits.lrs2, issue_slots[8].out_uop.lrs2 \n connect issue_slots[6].in_uop.bits.lrs1, issue_slots[8].out_uop.lrs1 \n connect issue_slots[6].in_uop.bits.ldst, issue_slots[8].out_uop.ldst \n connect issue_slots[6].in_uop.bits.ldst_is_rs1, issue_slots[8].out_uop.ldst_is_rs1 \n connect issue_slots[6].in_uop.bits.csr_cmd, issue_slots[8].out_uop.csr_cmd \n connect issue_slots[6].in_uop.bits.flush_on_commit, issue_slots[8].out_uop.flush_on_commit \n connect issue_slots[6].in_uop.bits.is_unique, issue_slots[8].out_uop.is_unique \n connect issue_slots[6].in_uop.bits.uses_stq, issue_slots[8].out_uop.uses_stq \n connect issue_slots[6].in_uop.bits.uses_ldq, issue_slots[8].out_uop.uses_ldq \n connect issue_slots[6].in_uop.bits.mem_signed, issue_slots[8].out_uop.mem_signed \n connect issue_slots[6].in_uop.bits.mem_size, issue_slots[8].out_uop.mem_size \n connect issue_slots[6].in_uop.bits.mem_cmd, issue_slots[8].out_uop.mem_cmd \n connect issue_slots[6].in_uop.bits.exc_cause, issue_slots[8].out_uop.exc_cause \n connect issue_slots[6].in_uop.bits.exception, issue_slots[8].out_uop.exception \n connect issue_slots[6].in_uop.bits.stale_pdst, issue_slots[8].out_uop.stale_pdst \n connect issue_slots[6].in_uop.bits.ppred_busy, issue_slots[8].out_uop.ppred_busy \n connect issue_slots[6].in_uop.bits.prs3_busy, issue_slots[8].out_uop.prs3_busy \n connect issue_slots[6].in_uop.bits.prs2_busy, issue_slots[8].out_uop.prs2_busy \n connect issue_slots[6].in_uop.bits.prs1_busy, issue_slots[8].out_uop.prs1_busy \n connect issue_slots[6].in_uop.bits.ppred, issue_slots[8].out_uop.ppred \n connect issue_slots[6].in_uop.bits.prs3, issue_slots[8].out_uop.prs3 \n connect issue_slots[6].in_uop.bits.prs2, issue_slots[8].out_uop.prs2 \n connect issue_slots[6].in_uop.bits.prs1, issue_slots[8].out_uop.prs1 \n connect issue_slots[6].in_uop.bits.pdst, issue_slots[8].out_uop.pdst \n connect issue_slots[6].in_uop.bits.rxq_idx, issue_slots[8].out_uop.rxq_idx \n connect issue_slots[6].in_uop.bits.stq_idx, issue_slots[8].out_uop.stq_idx \n connect issue_slots[6].in_uop.bits.ldq_idx, issue_slots[8].out_uop.ldq_idx \n connect issue_slots[6].in_uop.bits.rob_idx, issue_slots[8].out_uop.rob_idx \n connect issue_slots[6].in_uop.bits.fp_ctrl.vec, issue_slots[8].out_uop.fp_ctrl.vec \n connect issue_slots[6].in_uop.bits.fp_ctrl.wflags, issue_slots[8].out_uop.fp_ctrl.wflags \n connect issue_slots[6].in_uop.bits.fp_ctrl.sqrt, issue_slots[8].out_uop.fp_ctrl.sqrt \n connect issue_slots[6].in_uop.bits.fp_ctrl.div, issue_slots[8].out_uop.fp_ctrl.div \n connect issue_slots[6].in_uop.bits.fp_ctrl.fma, issue_slots[8].out_uop.fp_ctrl.fma \n connect issue_slots[6].in_uop.bits.fp_ctrl.fastpipe, issue_slots[8].out_uop.fp_ctrl.fastpipe \n connect issue_slots[6].in_uop.bits.fp_ctrl.toint, issue_slots[8].out_uop.fp_ctrl.toint \n connect issue_slots[6].in_uop.bits.fp_ctrl.fromint, issue_slots[8].out_uop.fp_ctrl.fromint \n connect issue_slots[6].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[8].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[6].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[8].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[6].in_uop.bits.fp_ctrl.swap23, issue_slots[8].out_uop.fp_ctrl.swap23 \n connect issue_slots[6].in_uop.bits.fp_ctrl.swap12, issue_slots[8].out_uop.fp_ctrl.swap12 \n connect issue_slots[6].in_uop.bits.fp_ctrl.ren3, issue_slots[8].out_uop.fp_ctrl.ren3 \n connect issue_slots[6].in_uop.bits.fp_ctrl.ren2, issue_slots[8].out_uop.fp_ctrl.ren2 \n connect issue_slots[6].in_uop.bits.fp_ctrl.ren1, issue_slots[8].out_uop.fp_ctrl.ren1 \n connect issue_slots[6].in_uop.bits.fp_ctrl.wen, issue_slots[8].out_uop.fp_ctrl.wen \n connect issue_slots[6].in_uop.bits.fp_ctrl.ldst, issue_slots[8].out_uop.fp_ctrl.ldst \n connect issue_slots[6].in_uop.bits.op2_sel, issue_slots[8].out_uop.op2_sel \n connect issue_slots[6].in_uop.bits.op1_sel, issue_slots[8].out_uop.op1_sel \n connect issue_slots[6].in_uop.bits.imm_packed, issue_slots[8].out_uop.imm_packed \n connect issue_slots[6].in_uop.bits.pimm, issue_slots[8].out_uop.pimm \n connect issue_slots[6].in_uop.bits.imm_sel, issue_slots[8].out_uop.imm_sel \n connect issue_slots[6].in_uop.bits.imm_rename, issue_slots[8].out_uop.imm_rename \n connect issue_slots[6].in_uop.bits.taken, issue_slots[8].out_uop.taken \n connect issue_slots[6].in_uop.bits.pc_lob, issue_slots[8].out_uop.pc_lob \n connect issue_slots[6].in_uop.bits.edge_inst, issue_slots[8].out_uop.edge_inst \n connect issue_slots[6].in_uop.bits.ftq_idx, issue_slots[8].out_uop.ftq_idx \n connect issue_slots[6].in_uop.bits.is_mov, issue_slots[8].out_uop.is_mov \n connect issue_slots[6].in_uop.bits.is_rocc, issue_slots[8].out_uop.is_rocc \n connect issue_slots[6].in_uop.bits.is_sys_pc2epc, issue_slots[8].out_uop.is_sys_pc2epc \n connect issue_slots[6].in_uop.bits.is_eret, issue_slots[8].out_uop.is_eret \n connect issue_slots[6].in_uop.bits.is_amo, issue_slots[8].out_uop.is_amo \n connect issue_slots[6].in_uop.bits.is_sfence, issue_slots[8].out_uop.is_sfence \n connect issue_slots[6].in_uop.bits.is_fencei, issue_slots[8].out_uop.is_fencei \n connect issue_slots[6].in_uop.bits.is_fence, issue_slots[8].out_uop.is_fence \n connect issue_slots[6].in_uop.bits.is_sfb, issue_slots[8].out_uop.is_sfb \n connect issue_slots[6].in_uop.bits.br_type, issue_slots[8].out_uop.br_type \n connect issue_slots[6].in_uop.bits.br_tag, issue_slots[8].out_uop.br_tag \n connect issue_slots[6].in_uop.bits.br_mask, issue_slots[8].out_uop.br_mask \n connect issue_slots[6].in_uop.bits.dis_col_sel, issue_slots[8].out_uop.dis_col_sel \n connect issue_slots[6].in_uop.bits.iw_p3_bypass_hint, issue_slots[8].out_uop.iw_p3_bypass_hint \n connect issue_slots[6].in_uop.bits.iw_p2_bypass_hint, issue_slots[8].out_uop.iw_p2_bypass_hint \n connect issue_slots[6].in_uop.bits.iw_p1_bypass_hint, issue_slots[8].out_uop.iw_p1_bypass_hint \n connect issue_slots[6].in_uop.bits.iw_p2_speculative_child, issue_slots[8].out_uop.iw_p2_speculative_child \n connect issue_slots[6].in_uop.bits.iw_p1_speculative_child, issue_slots[8].out_uop.iw_p1_speculative_child \n connect issue_slots[6].in_uop.bits.iw_issued_partial_dgen, issue_slots[8].out_uop.iw_issued_partial_dgen \n connect issue_slots[6].in_uop.bits.iw_issued_partial_agen, issue_slots[8].out_uop.iw_issued_partial_agen \n connect issue_slots[6].in_uop.bits.iw_issued, issue_slots[8].out_uop.iw_issued \n connect issue_slots[6].in_uop.bits.fu_code[0], issue_slots[8].out_uop.fu_code[0] \n connect issue_slots[6].in_uop.bits.fu_code[1], issue_slots[8].out_uop.fu_code[1] \n connect issue_slots[6].in_uop.bits.fu_code[2], issue_slots[8].out_uop.fu_code[2] \n connect issue_slots[6].in_uop.bits.fu_code[3], issue_slots[8].out_uop.fu_code[3] \n connect issue_slots[6].in_uop.bits.fu_code[4], issue_slots[8].out_uop.fu_code[4] \n connect issue_slots[6].in_uop.bits.fu_code[5], issue_slots[8].out_uop.fu_code[5] \n connect issue_slots[6].in_uop.bits.fu_code[6], issue_slots[8].out_uop.fu_code[6] \n connect issue_slots[6].in_uop.bits.fu_code[7], issue_slots[8].out_uop.fu_code[7] \n connect issue_slots[6].in_uop.bits.fu_code[8], issue_slots[8].out_uop.fu_code[8] \n connect issue_slots[6].in_uop.bits.fu_code[9], issue_slots[8].out_uop.fu_code[9] \n connect issue_slots[6].in_uop.bits.iq_type[0], issue_slots[8].out_uop.iq_type[0] \n connect issue_slots[6].in_uop.bits.iq_type[1], issue_slots[8].out_uop.iq_type[1] \n connect issue_slots[6].in_uop.bits.iq_type[2], issue_slots[8].out_uop.iq_type[2] \n connect issue_slots[6].in_uop.bits.iq_type[3], issue_slots[8].out_uop.iq_type[3] \n connect issue_slots[6].in_uop.bits.debug_pc, issue_slots[8].out_uop.debug_pc \n connect issue_slots[6].in_uop.bits.is_rvc, issue_slots[8].out_uop.is_rvc \n connect issue_slots[6].in_uop.bits.debug_inst, issue_slots[8].out_uop.debug_inst \n connect issue_slots[6].in_uop.bits.inst, issue_slots[8].out_uop.inst \n node _issue_slots_6_clear_T = neq(shamts_oh[6], UInt<1>(0h0)) \n connect issue_slots[6].clear, _issue_slots_6_clear_T \n connect issue_slots[7].in_uop.valid, UInt<1>(0h0) \n connect issue_slots[7].in_uop.bits.debug_tsrc, issue_slots[8].out_uop.debug_tsrc \n connect issue_slots[7].in_uop.bits.debug_fsrc, issue_slots[8].out_uop.debug_fsrc \n connect issue_slots[7].in_uop.bits.bp_xcpt_if, issue_slots[8].out_uop.bp_xcpt_if \n connect issue_slots[7].in_uop.bits.bp_debug_if, issue_slots[8].out_uop.bp_debug_if \n connect issue_slots[7].in_uop.bits.xcpt_ma_if, issue_slots[8].out_uop.xcpt_ma_if \n connect issue_slots[7].in_uop.bits.xcpt_ae_if, issue_slots[8].out_uop.xcpt_ae_if \n connect issue_slots[7].in_uop.bits.xcpt_pf_if, issue_slots[8].out_uop.xcpt_pf_if \n connect issue_slots[7].in_uop.bits.fp_typ, issue_slots[8].out_uop.fp_typ \n connect issue_slots[7].in_uop.bits.fp_rm, issue_slots[8].out_uop.fp_rm \n connect issue_slots[7].in_uop.bits.fp_val, issue_slots[8].out_uop.fp_val \n connect issue_slots[7].in_uop.bits.fcn_op, issue_slots[8].out_uop.fcn_op \n connect issue_slots[7].in_uop.bits.fcn_dw, issue_slots[8].out_uop.fcn_dw \n connect issue_slots[7].in_uop.bits.frs3_en, issue_slots[8].out_uop.frs3_en \n connect issue_slots[7].in_uop.bits.lrs2_rtype, issue_slots[8].out_uop.lrs2_rtype \n connect issue_slots[7].in_uop.bits.lrs1_rtype, issue_slots[8].out_uop.lrs1_rtype \n connect issue_slots[7].in_uop.bits.dst_rtype, issue_slots[8].out_uop.dst_rtype \n connect issue_slots[7].in_uop.bits.lrs3, issue_slots[8].out_uop.lrs3 \n connect issue_slots[7].in_uop.bits.lrs2, issue_slots[8].out_uop.lrs2 \n connect issue_slots[7].in_uop.bits.lrs1, issue_slots[8].out_uop.lrs1 \n connect issue_slots[7].in_uop.bits.ldst, issue_slots[8].out_uop.ldst \n connect issue_slots[7].in_uop.bits.ldst_is_rs1, issue_slots[8].out_uop.ldst_is_rs1 \n connect issue_slots[7].in_uop.bits.csr_cmd, issue_slots[8].out_uop.csr_cmd \n connect issue_slots[7].in_uop.bits.flush_on_commit, issue_slots[8].out_uop.flush_on_commit \n connect issue_slots[7].in_uop.bits.is_unique, issue_slots[8].out_uop.is_unique \n connect issue_slots[7].in_uop.bits.uses_stq, issue_slots[8].out_uop.uses_stq \n connect issue_slots[7].in_uop.bits.uses_ldq, issue_slots[8].out_uop.uses_ldq \n connect issue_slots[7].in_uop.bits.mem_signed, issue_slots[8].out_uop.mem_signed \n connect issue_slots[7].in_uop.bits.mem_size, issue_slots[8].out_uop.mem_size \n connect issue_slots[7].in_uop.bits.mem_cmd, issue_slots[8].out_uop.mem_cmd \n connect issue_slots[7].in_uop.bits.exc_cause, issue_slots[8].out_uop.exc_cause \n connect issue_slots[7].in_uop.bits.exception, issue_slots[8].out_uop.exception \n connect issue_slots[7].in_uop.bits.stale_pdst, issue_slots[8].out_uop.stale_pdst \n connect issue_slots[7].in_uop.bits.ppred_busy, issue_slots[8].out_uop.ppred_busy \n connect issue_slots[7].in_uop.bits.prs3_busy, issue_slots[8].out_uop.prs3_busy \n connect issue_slots[7].in_uop.bits.prs2_busy, issue_slots[8].out_uop.prs2_busy \n connect issue_slots[7].in_uop.bits.prs1_busy, issue_slots[8].out_uop.prs1_busy \n connect issue_slots[7].in_uop.bits.ppred, issue_slots[8].out_uop.ppred \n connect issue_slots[7].in_uop.bits.prs3, issue_slots[8].out_uop.prs3 \n connect issue_slots[7].in_uop.bits.prs2, issue_slots[8].out_uop.prs2 \n connect issue_slots[7].in_uop.bits.prs1, issue_slots[8].out_uop.prs1 \n connect issue_slots[7].in_uop.bits.pdst, issue_slots[8].out_uop.pdst \n connect issue_slots[7].in_uop.bits.rxq_idx, issue_slots[8].out_uop.rxq_idx \n connect issue_slots[7].in_uop.bits.stq_idx, issue_slots[8].out_uop.stq_idx \n connect issue_slots[7].in_uop.bits.ldq_idx, issue_slots[8].out_uop.ldq_idx \n connect issue_slots[7].in_uop.bits.rob_idx, issue_slots[8].out_uop.rob_idx \n connect issue_slots[7].in_uop.bits.fp_ctrl.vec, issue_slots[8].out_uop.fp_ctrl.vec \n connect issue_slots[7].in_uop.bits.fp_ctrl.wflags, issue_slots[8].out_uop.fp_ctrl.wflags \n connect issue_slots[7].in_uop.bits.fp_ctrl.sqrt, issue_slots[8].out_uop.fp_ctrl.sqrt \n connect issue_slots[7].in_uop.bits.fp_ctrl.div, issue_slots[8].out_uop.fp_ctrl.div \n connect issue_slots[7].in_uop.bits.fp_ctrl.fma, issue_slots[8].out_uop.fp_ctrl.fma \n connect issue_slots[7].in_uop.bits.fp_ctrl.fastpipe, issue_slots[8].out_uop.fp_ctrl.fastpipe \n connect issue_slots[7].in_uop.bits.fp_ctrl.toint, issue_slots[8].out_uop.fp_ctrl.toint \n connect issue_slots[7].in_uop.bits.fp_ctrl.fromint, issue_slots[8].out_uop.fp_ctrl.fromint \n connect issue_slots[7].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[8].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[7].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[8].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[7].in_uop.bits.fp_ctrl.swap23, issue_slots[8].out_uop.fp_ctrl.swap23 \n connect issue_slots[7].in_uop.bits.fp_ctrl.swap12, issue_slots[8].out_uop.fp_ctrl.swap12 \n connect issue_slots[7].in_uop.bits.fp_ctrl.ren3, issue_slots[8].out_uop.fp_ctrl.ren3 \n connect issue_slots[7].in_uop.bits.fp_ctrl.ren2, issue_slots[8].out_uop.fp_ctrl.ren2 \n connect issue_slots[7].in_uop.bits.fp_ctrl.ren1, issue_slots[8].out_uop.fp_ctrl.ren1 \n connect issue_slots[7].in_uop.bits.fp_ctrl.wen, issue_slots[8].out_uop.fp_ctrl.wen \n connect issue_slots[7].in_uop.bits.fp_ctrl.ldst, issue_slots[8].out_uop.fp_ctrl.ldst \n connect issue_slots[7].in_uop.bits.op2_sel, issue_slots[8].out_uop.op2_sel \n connect issue_slots[7].in_uop.bits.op1_sel, issue_slots[8].out_uop.op1_sel \n connect issue_slots[7].in_uop.bits.imm_packed, issue_slots[8].out_uop.imm_packed \n connect issue_slots[7].in_uop.bits.pimm, issue_slots[8].out_uop.pimm \n connect issue_slots[7].in_uop.bits.imm_sel, issue_slots[8].out_uop.imm_sel \n connect issue_slots[7].in_uop.bits.imm_rename, issue_slots[8].out_uop.imm_rename \n connect issue_slots[7].in_uop.bits.taken, issue_slots[8].out_uop.taken \n connect issue_slots[7].in_uop.bits.pc_lob, issue_slots[8].out_uop.pc_lob \n connect issue_slots[7].in_uop.bits.edge_inst, issue_slots[8].out_uop.edge_inst \n connect issue_slots[7].in_uop.bits.ftq_idx, issue_slots[8].out_uop.ftq_idx \n connect issue_slots[7].in_uop.bits.is_mov, issue_slots[8].out_uop.is_mov \n connect issue_slots[7].in_uop.bits.is_rocc, issue_slots[8].out_uop.is_rocc \n connect issue_slots[7].in_uop.bits.is_sys_pc2epc, issue_slots[8].out_uop.is_sys_pc2epc \n connect issue_slots[7].in_uop.bits.is_eret, issue_slots[8].out_uop.is_eret \n connect issue_slots[7].in_uop.bits.is_amo, issue_slots[8].out_uop.is_amo \n connect issue_slots[7].in_uop.bits.is_sfence, issue_slots[8].out_uop.is_sfence \n connect issue_slots[7].in_uop.bits.is_fencei, issue_slots[8].out_uop.is_fencei \n connect issue_slots[7].in_uop.bits.is_fence, issue_slots[8].out_uop.is_fence \n connect issue_slots[7].in_uop.bits.is_sfb, issue_slots[8].out_uop.is_sfb \n connect issue_slots[7].in_uop.bits.br_type, issue_slots[8].out_uop.br_type \n connect issue_slots[7].in_uop.bits.br_tag, issue_slots[8].out_uop.br_tag \n connect issue_slots[7].in_uop.bits.br_mask, issue_slots[8].out_uop.br_mask \n connect issue_slots[7].in_uop.bits.dis_col_sel, issue_slots[8].out_uop.dis_col_sel \n connect issue_slots[7].in_uop.bits.iw_p3_bypass_hint, issue_slots[8].out_uop.iw_p3_bypass_hint \n connect issue_slots[7].in_uop.bits.iw_p2_bypass_hint, issue_slots[8].out_uop.iw_p2_bypass_hint \n connect issue_slots[7].in_uop.bits.iw_p1_bypass_hint, issue_slots[8].out_uop.iw_p1_bypass_hint \n connect issue_slots[7].in_uop.bits.iw_p2_speculative_child, issue_slots[8].out_uop.iw_p2_speculative_child \n connect issue_slots[7].in_uop.bits.iw_p1_speculative_child, issue_slots[8].out_uop.iw_p1_speculative_child \n connect issue_slots[7].in_uop.bits.iw_issued_partial_dgen, issue_slots[8].out_uop.iw_issued_partial_dgen \n connect issue_slots[7].in_uop.bits.iw_issued_partial_agen, issue_slots[8].out_uop.iw_issued_partial_agen \n connect issue_slots[7].in_uop.bits.iw_issued, issue_slots[8].out_uop.iw_issued \n connect issue_slots[7].in_uop.bits.fu_code[0], issue_slots[8].out_uop.fu_code[0] \n connect issue_slots[7].in_uop.bits.fu_code[1], issue_slots[8].out_uop.fu_code[1] \n connect issue_slots[7].in_uop.bits.fu_code[2], issue_slots[8].out_uop.fu_code[2] \n connect issue_slots[7].in_uop.bits.fu_code[3], issue_slots[8].out_uop.fu_code[3] \n connect issue_slots[7].in_uop.bits.fu_code[4], issue_slots[8].out_uop.fu_code[4] \n connect issue_slots[7].in_uop.bits.fu_code[5], issue_slots[8].out_uop.fu_code[5] \n connect issue_slots[7].in_uop.bits.fu_code[6], issue_slots[8].out_uop.fu_code[6] \n connect issue_slots[7].in_uop.bits.fu_code[7], issue_slots[8].out_uop.fu_code[7] \n connect issue_slots[7].in_uop.bits.fu_code[8], issue_slots[8].out_uop.fu_code[8] \n connect issue_slots[7].in_uop.bits.fu_code[9], issue_slots[8].out_uop.fu_code[9] \n connect issue_slots[7].in_uop.bits.iq_type[0], issue_slots[8].out_uop.iq_type[0] \n connect issue_slots[7].in_uop.bits.iq_type[1], issue_slots[8].out_uop.iq_type[1] \n connect issue_slots[7].in_uop.bits.iq_type[2], issue_slots[8].out_uop.iq_type[2] \n connect issue_slots[7].in_uop.bits.iq_type[3], issue_slots[8].out_uop.iq_type[3] \n connect issue_slots[7].in_uop.bits.debug_pc, issue_slots[8].out_uop.debug_pc \n connect issue_slots[7].in_uop.bits.is_rvc, issue_slots[8].out_uop.is_rvc \n connect issue_slots[7].in_uop.bits.debug_inst, issue_slots[8].out_uop.debug_inst \n connect issue_slots[7].in_uop.bits.inst, issue_slots[8].out_uop.inst \n node _T_176 = eq(shamts_oh[8], UInt<1>(0h1)) \n when _T_176 : \n connect issue_slots[7].in_uop.valid, issue_slots[8].will_be_valid \n connect issue_slots[7].in_uop.bits.debug_tsrc, issue_slots[8].out_uop.debug_tsrc \n connect issue_slots[7].in_uop.bits.debug_fsrc, issue_slots[8].out_uop.debug_fsrc \n connect issue_slots[7].in_uop.bits.bp_xcpt_if, issue_slots[8].out_uop.bp_xcpt_if \n connect issue_slots[7].in_uop.bits.bp_debug_if, issue_slots[8].out_uop.bp_debug_if \n connect issue_slots[7].in_uop.bits.xcpt_ma_if, issue_slots[8].out_uop.xcpt_ma_if \n connect issue_slots[7].in_uop.bits.xcpt_ae_if, issue_slots[8].out_uop.xcpt_ae_if \n connect issue_slots[7].in_uop.bits.xcpt_pf_if, issue_slots[8].out_uop.xcpt_pf_if \n connect issue_slots[7].in_uop.bits.fp_typ, issue_slots[8].out_uop.fp_typ \n connect issue_slots[7].in_uop.bits.fp_rm, issue_slots[8].out_uop.fp_rm \n connect issue_slots[7].in_uop.bits.fp_val, issue_slots[8].out_uop.fp_val \n connect issue_slots[7].in_uop.bits.fcn_op, issue_slots[8].out_uop.fcn_op \n connect issue_slots[7].in_uop.bits.fcn_dw, issue_slots[8].out_uop.fcn_dw \n connect issue_slots[7].in_uop.bits.frs3_en, issue_slots[8].out_uop.frs3_en \n connect issue_slots[7].in_uop.bits.lrs2_rtype, issue_slots[8].out_uop.lrs2_rtype \n connect issue_slots[7].in_uop.bits.lrs1_rtype, issue_slots[8].out_uop.lrs1_rtype \n connect issue_slots[7].in_uop.bits.dst_rtype, issue_slots[8].out_uop.dst_rtype \n connect issue_slots[7].in_uop.bits.lrs3, issue_slots[8].out_uop.lrs3 \n connect issue_slots[7].in_uop.bits.lrs2, issue_slots[8].out_uop.lrs2 \n connect issue_slots[7].in_uop.bits.lrs1, issue_slots[8].out_uop.lrs1 \n connect issue_slots[7].in_uop.bits.ldst, issue_slots[8].out_uop.ldst \n connect issue_slots[7].in_uop.bits.ldst_is_rs1, issue_slots[8].out_uop.ldst_is_rs1 \n connect issue_slots[7].in_uop.bits.csr_cmd, issue_slots[8].out_uop.csr_cmd \n connect issue_slots[7].in_uop.bits.flush_on_commit, issue_slots[8].out_uop.flush_on_commit \n connect issue_slots[7].in_uop.bits.is_unique, issue_slots[8].out_uop.is_unique \n connect issue_slots[7].in_uop.bits.uses_stq, issue_slots[8].out_uop.uses_stq \n connect issue_slots[7].in_uop.bits.uses_ldq, issue_slots[8].out_uop.uses_ldq \n connect issue_slots[7].in_uop.bits.mem_signed, issue_slots[8].out_uop.mem_signed \n connect issue_slots[7].in_uop.bits.mem_size, issue_slots[8].out_uop.mem_size \n connect issue_slots[7].in_uop.bits.mem_cmd, issue_slots[8].out_uop.mem_cmd \n connect issue_slots[7].in_uop.bits.exc_cause, issue_slots[8].out_uop.exc_cause \n connect issue_slots[7].in_uop.bits.exception, issue_slots[8].out_uop.exception \n connect issue_slots[7].in_uop.bits.stale_pdst, issue_slots[8].out_uop.stale_pdst \n connect issue_slots[7].in_uop.bits.ppred_busy, issue_slots[8].out_uop.ppred_busy \n connect issue_slots[7].in_uop.bits.prs3_busy, issue_slots[8].out_uop.prs3_busy \n connect issue_slots[7].in_uop.bits.prs2_busy, issue_slots[8].out_uop.prs2_busy \n connect issue_slots[7].in_uop.bits.prs1_busy, issue_slots[8].out_uop.prs1_busy \n connect issue_slots[7].in_uop.bits.ppred, issue_slots[8].out_uop.ppred \n connect issue_slots[7].in_uop.bits.prs3, issue_slots[8].out_uop.prs3 \n connect issue_slots[7].in_uop.bits.prs2, issue_slots[8].out_uop.prs2 \n connect issue_slots[7].in_uop.bits.prs1, issue_slots[8].out_uop.prs1 \n connect issue_slots[7].in_uop.bits.pdst, issue_slots[8].out_uop.pdst \n connect issue_slots[7].in_uop.bits.rxq_idx, issue_slots[8].out_uop.rxq_idx \n connect issue_slots[7].in_uop.bits.stq_idx, issue_slots[8].out_uop.stq_idx \n connect issue_slots[7].in_uop.bits.ldq_idx, issue_slots[8].out_uop.ldq_idx \n connect issue_slots[7].in_uop.bits.rob_idx, issue_slots[8].out_uop.rob_idx \n connect issue_slots[7].in_uop.bits.fp_ctrl.vec, issue_slots[8].out_uop.fp_ctrl.vec \n connect issue_slots[7].in_uop.bits.fp_ctrl.wflags, issue_slots[8].out_uop.fp_ctrl.wflags \n connect issue_slots[7].in_uop.bits.fp_ctrl.sqrt, issue_slots[8].out_uop.fp_ctrl.sqrt \n connect issue_slots[7].in_uop.bits.fp_ctrl.div, issue_slots[8].out_uop.fp_ctrl.div \n connect issue_slots[7].in_uop.bits.fp_ctrl.fma, issue_slots[8].out_uop.fp_ctrl.fma \n connect issue_slots[7].in_uop.bits.fp_ctrl.fastpipe, issue_slots[8].out_uop.fp_ctrl.fastpipe \n connect issue_slots[7].in_uop.bits.fp_ctrl.toint, issue_slots[8].out_uop.fp_ctrl.toint \n connect issue_slots[7].in_uop.bits.fp_ctrl.fromint, issue_slots[8].out_uop.fp_ctrl.fromint \n connect issue_slots[7].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[8].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[7].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[8].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[7].in_uop.bits.fp_ctrl.swap23, issue_slots[8].out_uop.fp_ctrl.swap23 \n connect issue_slots[7].in_uop.bits.fp_ctrl.swap12, issue_slots[8].out_uop.fp_ctrl.swap12 \n connect issue_slots[7].in_uop.bits.fp_ctrl.ren3, issue_slots[8].out_uop.fp_ctrl.ren3 \n connect issue_slots[7].in_uop.bits.fp_ctrl.ren2, issue_slots[8].out_uop.fp_ctrl.ren2 \n connect issue_slots[7].in_uop.bits.fp_ctrl.ren1, issue_slots[8].out_uop.fp_ctrl.ren1 \n connect issue_slots[7].in_uop.bits.fp_ctrl.wen, issue_slots[8].out_uop.fp_ctrl.wen \n connect issue_slots[7].in_uop.bits.fp_ctrl.ldst, issue_slots[8].out_uop.fp_ctrl.ldst \n connect issue_slots[7].in_uop.bits.op2_sel, issue_slots[8].out_uop.op2_sel \n connect issue_slots[7].in_uop.bits.op1_sel, issue_slots[8].out_uop.op1_sel \n connect issue_slots[7].in_uop.bits.imm_packed, issue_slots[8].out_uop.imm_packed \n connect issue_slots[7].in_uop.bits.pimm, issue_slots[8].out_uop.pimm \n connect issue_slots[7].in_uop.bits.imm_sel, issue_slots[8].out_uop.imm_sel \n connect issue_slots[7].in_uop.bits.imm_rename, issue_slots[8].out_uop.imm_rename \n connect issue_slots[7].in_uop.bits.taken, issue_slots[8].out_uop.taken \n connect issue_slots[7].in_uop.bits.pc_lob, issue_slots[8].out_uop.pc_lob \n connect issue_slots[7].in_uop.bits.edge_inst, issue_slots[8].out_uop.edge_inst \n connect issue_slots[7].in_uop.bits.ftq_idx, issue_slots[8].out_uop.ftq_idx \n connect issue_slots[7].in_uop.bits.is_mov, issue_slots[8].out_uop.is_mov \n connect issue_slots[7].in_uop.bits.is_rocc, issue_slots[8].out_uop.is_rocc \n connect issue_slots[7].in_uop.bits.is_sys_pc2epc, issue_slots[8].out_uop.is_sys_pc2epc \n connect issue_slots[7].in_uop.bits.is_eret, issue_slots[8].out_uop.is_eret \n connect issue_slots[7].in_uop.bits.is_amo, issue_slots[8].out_uop.is_amo \n connect issue_slots[7].in_uop.bits.is_sfence, issue_slots[8].out_uop.is_sfence \n connect issue_slots[7].in_uop.bits.is_fencei, issue_slots[8].out_uop.is_fencei \n connect issue_slots[7].in_uop.bits.is_fence, issue_slots[8].out_uop.is_fence \n connect issue_slots[7].in_uop.bits.is_sfb, issue_slots[8].out_uop.is_sfb \n connect issue_slots[7].in_uop.bits.br_type, issue_slots[8].out_uop.br_type \n connect issue_slots[7].in_uop.bits.br_tag, issue_slots[8].out_uop.br_tag \n connect issue_slots[7].in_uop.bits.br_mask, issue_slots[8].out_uop.br_mask \n connect issue_slots[7].in_uop.bits.dis_col_sel, issue_slots[8].out_uop.dis_col_sel \n connect issue_slots[7].in_uop.bits.iw_p3_bypass_hint, issue_slots[8].out_uop.iw_p3_bypass_hint \n connect issue_slots[7].in_uop.bits.iw_p2_bypass_hint, issue_slots[8].out_uop.iw_p2_bypass_hint \n connect issue_slots[7].in_uop.bits.iw_p1_bypass_hint, issue_slots[8].out_uop.iw_p1_bypass_hint \n connect issue_slots[7].in_uop.bits.iw_p2_speculative_child, issue_slots[8].out_uop.iw_p2_speculative_child \n connect issue_slots[7].in_uop.bits.iw_p1_speculative_child, issue_slots[8].out_uop.iw_p1_speculative_child \n connect issue_slots[7].in_uop.bits.iw_issued_partial_dgen, issue_slots[8].out_uop.iw_issued_partial_dgen \n connect issue_slots[7].in_uop.bits.iw_issued_partial_agen, issue_slots[8].out_uop.iw_issued_partial_agen \n connect issue_slots[7].in_uop.bits.iw_issued, issue_slots[8].out_uop.iw_issued \n connect issue_slots[7].in_uop.bits.fu_code[0], issue_slots[8].out_uop.fu_code[0] \n connect issue_slots[7].in_uop.bits.fu_code[1], issue_slots[8].out_uop.fu_code[1] \n connect issue_slots[7].in_uop.bits.fu_code[2], issue_slots[8].out_uop.fu_code[2] \n connect issue_slots[7].in_uop.bits.fu_code[3], issue_slots[8].out_uop.fu_code[3] \n connect issue_slots[7].in_uop.bits.fu_code[4], issue_slots[8].out_uop.fu_code[4] \n connect issue_slots[7].in_uop.bits.fu_code[5], issue_slots[8].out_uop.fu_code[5] \n connect issue_slots[7].in_uop.bits.fu_code[6], issue_slots[8].out_uop.fu_code[6] \n connect issue_slots[7].in_uop.bits.fu_code[7], issue_slots[8].out_uop.fu_code[7] \n connect issue_slots[7].in_uop.bits.fu_code[8], issue_slots[8].out_uop.fu_code[8] \n connect issue_slots[7].in_uop.bits.fu_code[9], issue_slots[8].out_uop.fu_code[9] \n connect issue_slots[7].in_uop.bits.iq_type[0], issue_slots[8].out_uop.iq_type[0] \n connect issue_slots[7].in_uop.bits.iq_type[1], issue_slots[8].out_uop.iq_type[1] \n connect issue_slots[7].in_uop.bits.iq_type[2], issue_slots[8].out_uop.iq_type[2] \n connect issue_slots[7].in_uop.bits.iq_type[3], issue_slots[8].out_uop.iq_type[3] \n connect issue_slots[7].in_uop.bits.debug_pc, issue_slots[8].out_uop.debug_pc \n connect issue_slots[7].in_uop.bits.is_rvc, issue_slots[8].out_uop.is_rvc \n connect issue_slots[7].in_uop.bits.debug_inst, issue_slots[8].out_uop.debug_inst \n connect issue_slots[7].in_uop.bits.inst, issue_slots[8].out_uop.inst \n node _T_177 = eq(shamts_oh[9], UInt<2>(0h2)) \n when _T_177 : \n connect issue_slots[7].in_uop.valid, issue_slots[9].will_be_valid \n connect issue_slots[7].in_uop.bits.debug_tsrc, issue_slots[9].out_uop.debug_tsrc \n connect issue_slots[7].in_uop.bits.debug_fsrc, issue_slots[9].out_uop.debug_fsrc \n connect issue_slots[7].in_uop.bits.bp_xcpt_if, issue_slots[9].out_uop.bp_xcpt_if \n connect issue_slots[7].in_uop.bits.bp_debug_if, issue_slots[9].out_uop.bp_debug_if \n connect issue_slots[7].in_uop.bits.xcpt_ma_if, issue_slots[9].out_uop.xcpt_ma_if \n connect issue_slots[7].in_uop.bits.xcpt_ae_if, issue_slots[9].out_uop.xcpt_ae_if \n connect issue_slots[7].in_uop.bits.xcpt_pf_if, issue_slots[9].out_uop.xcpt_pf_if \n connect issue_slots[7].in_uop.bits.fp_typ, issue_slots[9].out_uop.fp_typ \n connect issue_slots[7].in_uop.bits.fp_rm, issue_slots[9].out_uop.fp_rm \n connect issue_slots[7].in_uop.bits.fp_val, issue_slots[9].out_uop.fp_val \n connect issue_slots[7].in_uop.bits.fcn_op, issue_slots[9].out_uop.fcn_op \n connect issue_slots[7].in_uop.bits.fcn_dw, issue_slots[9].out_uop.fcn_dw \n connect issue_slots[7].in_uop.bits.frs3_en, issue_slots[9].out_uop.frs3_en \n connect issue_slots[7].in_uop.bits.lrs2_rtype, issue_slots[9].out_uop.lrs2_rtype \n connect issue_slots[7].in_uop.bits.lrs1_rtype, issue_slots[9].out_uop.lrs1_rtype \n connect issue_slots[7].in_uop.bits.dst_rtype, issue_slots[9].out_uop.dst_rtype \n connect issue_slots[7].in_uop.bits.lrs3, issue_slots[9].out_uop.lrs3 \n connect issue_slots[7].in_uop.bits.lrs2, issue_slots[9].out_uop.lrs2 \n connect issue_slots[7].in_uop.bits.lrs1, issue_slots[9].out_uop.lrs1 \n connect issue_slots[7].in_uop.bits.ldst, issue_slots[9].out_uop.ldst \n connect issue_slots[7].in_uop.bits.ldst_is_rs1, issue_slots[9].out_uop.ldst_is_rs1 \n connect issue_slots[7].in_uop.bits.csr_cmd, issue_slots[9].out_uop.csr_cmd \n connect issue_slots[7].in_uop.bits.flush_on_commit, issue_slots[9].out_uop.flush_on_commit \n connect issue_slots[7].in_uop.bits.is_unique, issue_slots[9].out_uop.is_unique \n connect issue_slots[7].in_uop.bits.uses_stq, issue_slots[9].out_uop.uses_stq \n connect issue_slots[7].in_uop.bits.uses_ldq, issue_slots[9].out_uop.uses_ldq \n connect issue_slots[7].in_uop.bits.mem_signed, issue_slots[9].out_uop.mem_signed \n connect issue_slots[7].in_uop.bits.mem_size, issue_slots[9].out_uop.mem_size \n connect issue_slots[7].in_uop.bits.mem_cmd, issue_slots[9].out_uop.mem_cmd \n connect issue_slots[7].in_uop.bits.exc_cause, issue_slots[9].out_uop.exc_cause \n connect issue_slots[7].in_uop.bits.exception, issue_slots[9].out_uop.exception \n connect issue_slots[7].in_uop.bits.stale_pdst, issue_slots[9].out_uop.stale_pdst \n connect issue_slots[7].in_uop.bits.ppred_busy, issue_slots[9].out_uop.ppred_busy \n connect issue_slots[7].in_uop.bits.prs3_busy, issue_slots[9].out_uop.prs3_busy \n connect issue_slots[7].in_uop.bits.prs2_busy, issue_slots[9].out_uop.prs2_busy \n connect issue_slots[7].in_uop.bits.prs1_busy, issue_slots[9].out_uop.prs1_busy \n connect issue_slots[7].in_uop.bits.ppred, issue_slots[9].out_uop.ppred \n connect issue_slots[7].in_uop.bits.prs3, issue_slots[9].out_uop.prs3 \n connect issue_slots[7].in_uop.bits.prs2, issue_slots[9].out_uop.prs2 \n connect issue_slots[7].in_uop.bits.prs1, issue_slots[9].out_uop.prs1 \n connect issue_slots[7].in_uop.bits.pdst, issue_slots[9].out_uop.pdst \n connect issue_slots[7].in_uop.bits.rxq_idx, issue_slots[9].out_uop.rxq_idx \n connect issue_slots[7].in_uop.bits.stq_idx, issue_slots[9].out_uop.stq_idx \n connect issue_slots[7].in_uop.bits.ldq_idx, issue_slots[9].out_uop.ldq_idx \n connect issue_slots[7].in_uop.bits.rob_idx, issue_slots[9].out_uop.rob_idx \n connect issue_slots[7].in_uop.bits.fp_ctrl.vec, issue_slots[9].out_uop.fp_ctrl.vec \n connect issue_slots[7].in_uop.bits.fp_ctrl.wflags, issue_slots[9].out_uop.fp_ctrl.wflags \n connect issue_slots[7].in_uop.bits.fp_ctrl.sqrt, issue_slots[9].out_uop.fp_ctrl.sqrt \n connect issue_slots[7].in_uop.bits.fp_ctrl.div, issue_slots[9].out_uop.fp_ctrl.div \n connect issue_slots[7].in_uop.bits.fp_ctrl.fma, issue_slots[9].out_uop.fp_ctrl.fma \n connect issue_slots[7].in_uop.bits.fp_ctrl.fastpipe, issue_slots[9].out_uop.fp_ctrl.fastpipe \n connect issue_slots[7].in_uop.bits.fp_ctrl.toint, issue_slots[9].out_uop.fp_ctrl.toint \n connect issue_slots[7].in_uop.bits.fp_ctrl.fromint, issue_slots[9].out_uop.fp_ctrl.fromint \n connect issue_slots[7].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[9].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[7].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[9].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[7].in_uop.bits.fp_ctrl.swap23, issue_slots[9].out_uop.fp_ctrl.swap23 \n connect issue_slots[7].in_uop.bits.fp_ctrl.swap12, issue_slots[9].out_uop.fp_ctrl.swap12 \n connect issue_slots[7].in_uop.bits.fp_ctrl.ren3, issue_slots[9].out_uop.fp_ctrl.ren3 \n connect issue_slots[7].in_uop.bits.fp_ctrl.ren2, issue_slots[9].out_uop.fp_ctrl.ren2 \n connect issue_slots[7].in_uop.bits.fp_ctrl.ren1, issue_slots[9].out_uop.fp_ctrl.ren1 \n connect issue_slots[7].in_uop.bits.fp_ctrl.wen, issue_slots[9].out_uop.fp_ctrl.wen \n connect issue_slots[7].in_uop.bits.fp_ctrl.ldst, issue_slots[9].out_uop.fp_ctrl.ldst \n connect issue_slots[7].in_uop.bits.op2_sel, issue_slots[9].out_uop.op2_sel \n connect issue_slots[7].in_uop.bits.op1_sel, issue_slots[9].out_uop.op1_sel \n connect issue_slots[7].in_uop.bits.imm_packed, issue_slots[9].out_uop.imm_packed \n connect issue_slots[7].in_uop.bits.pimm, issue_slots[9].out_uop.pimm \n connect issue_slots[7].in_uop.bits.imm_sel, issue_slots[9].out_uop.imm_sel \n connect issue_slots[7].in_uop.bits.imm_rename, issue_slots[9].out_uop.imm_rename \n connect issue_slots[7].in_uop.bits.taken, issue_slots[9].out_uop.taken \n connect issue_slots[7].in_uop.bits.pc_lob, issue_slots[9].out_uop.pc_lob \n connect issue_slots[7].in_uop.bits.edge_inst, issue_slots[9].out_uop.edge_inst \n connect issue_slots[7].in_uop.bits.ftq_idx, issue_slots[9].out_uop.ftq_idx \n connect issue_slots[7].in_uop.bits.is_mov, issue_slots[9].out_uop.is_mov \n connect issue_slots[7].in_uop.bits.is_rocc, issue_slots[9].out_uop.is_rocc \n connect issue_slots[7].in_uop.bits.is_sys_pc2epc, issue_slots[9].out_uop.is_sys_pc2epc \n connect issue_slots[7].in_uop.bits.is_eret, issue_slots[9].out_uop.is_eret \n connect issue_slots[7].in_uop.bits.is_amo, issue_slots[9].out_uop.is_amo \n connect issue_slots[7].in_uop.bits.is_sfence, issue_slots[9].out_uop.is_sfence \n connect issue_slots[7].in_uop.bits.is_fencei, issue_slots[9].out_uop.is_fencei \n connect issue_slots[7].in_uop.bits.is_fence, issue_slots[9].out_uop.is_fence \n connect issue_slots[7].in_uop.bits.is_sfb, issue_slots[9].out_uop.is_sfb \n connect issue_slots[7].in_uop.bits.br_type, issue_slots[9].out_uop.br_type \n connect issue_slots[7].in_uop.bits.br_tag, issue_slots[9].out_uop.br_tag \n connect issue_slots[7].in_uop.bits.br_mask, issue_slots[9].out_uop.br_mask \n connect issue_slots[7].in_uop.bits.dis_col_sel, issue_slots[9].out_uop.dis_col_sel \n connect issue_slots[7].in_uop.bits.iw_p3_bypass_hint, issue_slots[9].out_uop.iw_p3_bypass_hint \n connect issue_slots[7].in_uop.bits.iw_p2_bypass_hint, issue_slots[9].out_uop.iw_p2_bypass_hint \n connect issue_slots[7].in_uop.bits.iw_p1_bypass_hint, issue_slots[9].out_uop.iw_p1_bypass_hint \n connect issue_slots[7].in_uop.bits.iw_p2_speculative_child, issue_slots[9].out_uop.iw_p2_speculative_child \n connect issue_slots[7].in_uop.bits.iw_p1_speculative_child, issue_slots[9].out_uop.iw_p1_speculative_child \n connect issue_slots[7].in_uop.bits.iw_issued_partial_dgen, issue_slots[9].out_uop.iw_issued_partial_dgen \n connect issue_slots[7].in_uop.bits.iw_issued_partial_agen, issue_slots[9].out_uop.iw_issued_partial_agen \n connect issue_slots[7].in_uop.bits.iw_issued, issue_slots[9].out_uop.iw_issued \n connect issue_slots[7].in_uop.bits.fu_code[0], issue_slots[9].out_uop.fu_code[0] \n connect issue_slots[7].in_uop.bits.fu_code[1], issue_slots[9].out_uop.fu_code[1] \n connect issue_slots[7].in_uop.bits.fu_code[2], issue_slots[9].out_uop.fu_code[2] \n connect issue_slots[7].in_uop.bits.fu_code[3], issue_slots[9].out_uop.fu_code[3] \n connect issue_slots[7].in_uop.bits.fu_code[4], issue_slots[9].out_uop.fu_code[4] \n connect issue_slots[7].in_uop.bits.fu_code[5], issue_slots[9].out_uop.fu_code[5] \n connect issue_slots[7].in_uop.bits.fu_code[6], issue_slots[9].out_uop.fu_code[6] \n connect issue_slots[7].in_uop.bits.fu_code[7], issue_slots[9].out_uop.fu_code[7] \n connect issue_slots[7].in_uop.bits.fu_code[8], issue_slots[9].out_uop.fu_code[8] \n connect issue_slots[7].in_uop.bits.fu_code[9], issue_slots[9].out_uop.fu_code[9] \n connect issue_slots[7].in_uop.bits.iq_type[0], issue_slots[9].out_uop.iq_type[0] \n connect issue_slots[7].in_uop.bits.iq_type[1], issue_slots[9].out_uop.iq_type[1] \n connect issue_slots[7].in_uop.bits.iq_type[2], issue_slots[9].out_uop.iq_type[2] \n connect issue_slots[7].in_uop.bits.iq_type[3], issue_slots[9].out_uop.iq_type[3] \n connect issue_slots[7].in_uop.bits.debug_pc, issue_slots[9].out_uop.debug_pc \n connect issue_slots[7].in_uop.bits.is_rvc, issue_slots[9].out_uop.is_rvc \n connect issue_slots[7].in_uop.bits.debug_inst, issue_slots[9].out_uop.debug_inst \n connect issue_slots[7].in_uop.bits.inst, issue_slots[9].out_uop.inst \n node _issue_slots_7_clear_T = neq(shamts_oh[7], UInt<1>(0h0)) \n connect issue_slots[7].clear, _issue_slots_7_clear_T \n connect issue_slots[8].in_uop.valid, UInt<1>(0h0) \n connect issue_slots[8].in_uop.bits.debug_tsrc, issue_slots[9].out_uop.debug_tsrc \n connect issue_slots[8].in_uop.bits.debug_fsrc, issue_slots[9].out_uop.debug_fsrc \n connect issue_slots[8].in_uop.bits.bp_xcpt_if, issue_slots[9].out_uop.bp_xcpt_if \n connect issue_slots[8].in_uop.bits.bp_debug_if, issue_slots[9].out_uop.bp_debug_if \n connect issue_slots[8].in_uop.bits.xcpt_ma_if, issue_slots[9].out_uop.xcpt_ma_if \n connect issue_slots[8].in_uop.bits.xcpt_ae_if, issue_slots[9].out_uop.xcpt_ae_if \n connect issue_slots[8].in_uop.bits.xcpt_pf_if, issue_slots[9].out_uop.xcpt_pf_if \n connect issue_slots[8].in_uop.bits.fp_typ, issue_slots[9].out_uop.fp_typ \n connect issue_slots[8].in_uop.bits.fp_rm, issue_slots[9].out_uop.fp_rm \n connect issue_slots[8].in_uop.bits.fp_val, issue_slots[9].out_uop.fp_val \n connect issue_slots[8].in_uop.bits.fcn_op, issue_slots[9].out_uop.fcn_op \n connect issue_slots[8].in_uop.bits.fcn_dw, issue_slots[9].out_uop.fcn_dw \n connect issue_slots[8].in_uop.bits.frs3_en, issue_slots[9].out_uop.frs3_en \n connect issue_slots[8].in_uop.bits.lrs2_rtype, issue_slots[9].out_uop.lrs2_rtype \n connect issue_slots[8].in_uop.bits.lrs1_rtype, issue_slots[9].out_uop.lrs1_rtype \n connect issue_slots[8].in_uop.bits.dst_rtype, issue_slots[9].out_uop.dst_rtype \n connect issue_slots[8].in_uop.bits.lrs3, issue_slots[9].out_uop.lrs3 \n connect issue_slots[8].in_uop.bits.lrs2, issue_slots[9].out_uop.lrs2 \n connect issue_slots[8].in_uop.bits.lrs1, issue_slots[9].out_uop.lrs1 \n connect issue_slots[8].in_uop.bits.ldst, issue_slots[9].out_uop.ldst \n connect issue_slots[8].in_uop.bits.ldst_is_rs1, issue_slots[9].out_uop.ldst_is_rs1 \n connect issue_slots[8].in_uop.bits.csr_cmd, issue_slots[9].out_uop.csr_cmd \n connect issue_slots[8].in_uop.bits.flush_on_commit, issue_slots[9].out_uop.flush_on_commit \n connect issue_slots[8].in_uop.bits.is_unique, issue_slots[9].out_uop.is_unique \n connect issue_slots[8].in_uop.bits.uses_stq, issue_slots[9].out_uop.uses_stq \n connect issue_slots[8].in_uop.bits.uses_ldq, issue_slots[9].out_uop.uses_ldq \n connect issue_slots[8].in_uop.bits.mem_signed, issue_slots[9].out_uop.mem_signed \n connect issue_slots[8].in_uop.bits.mem_size, issue_slots[9].out_uop.mem_size \n connect issue_slots[8].in_uop.bits.mem_cmd, issue_slots[9].out_uop.mem_cmd \n connect issue_slots[8].in_uop.bits.exc_cause, issue_slots[9].out_uop.exc_cause \n connect issue_slots[8].in_uop.bits.exception, issue_slots[9].out_uop.exception \n connect issue_slots[8].in_uop.bits.stale_pdst, issue_slots[9].out_uop.stale_pdst \n connect issue_slots[8].in_uop.bits.ppred_busy, issue_slots[9].out_uop.ppred_busy \n connect issue_slots[8].in_uop.bits.prs3_busy, issue_slots[9].out_uop.prs3_busy \n connect issue_slots[8].in_uop.bits.prs2_busy, issue_slots[9].out_uop.prs2_busy \n connect issue_slots[8].in_uop.bits.prs1_busy, issue_slots[9].out_uop.prs1_busy \n connect issue_slots[8].in_uop.bits.ppred, issue_slots[9].out_uop.ppred \n connect issue_slots[8].in_uop.bits.prs3, issue_slots[9].out_uop.prs3 \n connect issue_slots[8].in_uop.bits.prs2, issue_slots[9].out_uop.prs2 \n connect issue_slots[8].in_uop.bits.prs1, issue_slots[9].out_uop.prs1 \n connect issue_slots[8].in_uop.bits.pdst, issue_slots[9].out_uop.pdst \n connect issue_slots[8].in_uop.bits.rxq_idx, issue_slots[9].out_uop.rxq_idx \n connect issue_slots[8].in_uop.bits.stq_idx, issue_slots[9].out_uop.stq_idx \n connect issue_slots[8].in_uop.bits.ldq_idx, issue_slots[9].out_uop.ldq_idx \n connect issue_slots[8].in_uop.bits.rob_idx, issue_slots[9].out_uop.rob_idx \n connect issue_slots[8].in_uop.bits.fp_ctrl.vec, issue_slots[9].out_uop.fp_ctrl.vec \n connect issue_slots[8].in_uop.bits.fp_ctrl.wflags, issue_slots[9].out_uop.fp_ctrl.wflags \n connect issue_slots[8].in_uop.bits.fp_ctrl.sqrt, issue_slots[9].out_uop.fp_ctrl.sqrt \n connect issue_slots[8].in_uop.bits.fp_ctrl.div, issue_slots[9].out_uop.fp_ctrl.div \n connect issue_slots[8].in_uop.bits.fp_ctrl.fma, issue_slots[9].out_uop.fp_ctrl.fma \n connect issue_slots[8].in_uop.bits.fp_ctrl.fastpipe, issue_slots[9].out_uop.fp_ctrl.fastpipe \n connect issue_slots[8].in_uop.bits.fp_ctrl.toint, issue_slots[9].out_uop.fp_ctrl.toint \n connect issue_slots[8].in_uop.bits.fp_ctrl.fromint, issue_slots[9].out_uop.fp_ctrl.fromint \n connect issue_slots[8].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[9].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[8].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[9].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[8].in_uop.bits.fp_ctrl.swap23, issue_slots[9].out_uop.fp_ctrl.swap23 \n connect issue_slots[8].in_uop.bits.fp_ctrl.swap12, issue_slots[9].out_uop.fp_ctrl.swap12 \n connect issue_slots[8].in_uop.bits.fp_ctrl.ren3, issue_slots[9].out_uop.fp_ctrl.ren3 \n connect issue_slots[8].in_uop.bits.fp_ctrl.ren2, issue_slots[9].out_uop.fp_ctrl.ren2 \n connect issue_slots[8].in_uop.bits.fp_ctrl.ren1, issue_slots[9].out_uop.fp_ctrl.ren1 \n connect issue_slots[8].in_uop.bits.fp_ctrl.wen, issue_slots[9].out_uop.fp_ctrl.wen \n connect issue_slots[8].in_uop.bits.fp_ctrl.ldst, issue_slots[9].out_uop.fp_ctrl.ldst \n connect issue_slots[8].in_uop.bits.op2_sel, issue_slots[9].out_uop.op2_sel \n connect issue_slots[8].in_uop.bits.op1_sel, issue_slots[9].out_uop.op1_sel \n connect issue_slots[8].in_uop.bits.imm_packed, issue_slots[9].out_uop.imm_packed \n connect issue_slots[8].in_uop.bits.pimm, issue_slots[9].out_uop.pimm \n connect issue_slots[8].in_uop.bits.imm_sel, issue_slots[9].out_uop.imm_sel \n connect issue_slots[8].in_uop.bits.imm_rename, issue_slots[9].out_uop.imm_rename \n connect issue_slots[8].in_uop.bits.taken, issue_slots[9].out_uop.taken \n connect issue_slots[8].in_uop.bits.pc_lob, issue_slots[9].out_uop.pc_lob \n connect issue_slots[8].in_uop.bits.edge_inst, issue_slots[9].out_uop.edge_inst \n connect issue_slots[8].in_uop.bits.ftq_idx, issue_slots[9].out_uop.ftq_idx \n connect issue_slots[8].in_uop.bits.is_mov, issue_slots[9].out_uop.is_mov \n connect issue_slots[8].in_uop.bits.is_rocc, issue_slots[9].out_uop.is_rocc \n connect issue_slots[8].in_uop.bits.is_sys_pc2epc, issue_slots[9].out_uop.is_sys_pc2epc \n connect issue_slots[8].in_uop.bits.is_eret, issue_slots[9].out_uop.is_eret \n connect issue_slots[8].in_uop.bits.is_amo, issue_slots[9].out_uop.is_amo \n connect issue_slots[8].in_uop.bits.is_sfence, issue_slots[9].out_uop.is_sfence \n connect issue_slots[8].in_uop.bits.is_fencei, issue_slots[9].out_uop.is_fencei \n connect issue_slots[8].in_uop.bits.is_fence, issue_slots[9].out_uop.is_fence \n connect issue_slots[8].in_uop.bits.is_sfb, issue_slots[9].out_uop.is_sfb \n connect issue_slots[8].in_uop.bits.br_type, issue_slots[9].out_uop.br_type \n connect issue_slots[8].in_uop.bits.br_tag, issue_slots[9].out_uop.br_tag \n connect issue_slots[8].in_uop.bits.br_mask, issue_slots[9].out_uop.br_mask \n connect issue_slots[8].in_uop.bits.dis_col_sel, issue_slots[9].out_uop.dis_col_sel \n connect issue_slots[8].in_uop.bits.iw_p3_bypass_hint, issue_slots[9].out_uop.iw_p3_bypass_hint \n connect issue_slots[8].in_uop.bits.iw_p2_bypass_hint, issue_slots[9].out_uop.iw_p2_bypass_hint \n connect issue_slots[8].in_uop.bits.iw_p1_bypass_hint, issue_slots[9].out_uop.iw_p1_bypass_hint \n connect issue_slots[8].in_uop.bits.iw_p2_speculative_child, issue_slots[9].out_uop.iw_p2_speculative_child \n connect issue_slots[8].in_uop.bits.iw_p1_speculative_child, issue_slots[9].out_uop.iw_p1_speculative_child \n connect issue_slots[8].in_uop.bits.iw_issued_partial_dgen, issue_slots[9].out_uop.iw_issued_partial_dgen \n connect issue_slots[8].in_uop.bits.iw_issued_partial_agen, issue_slots[9].out_uop.iw_issued_partial_agen \n connect issue_slots[8].in_uop.bits.iw_issued, issue_slots[9].out_uop.iw_issued \n connect issue_slots[8].in_uop.bits.fu_code[0], issue_slots[9].out_uop.fu_code[0] \n connect issue_slots[8].in_uop.bits.fu_code[1], issue_slots[9].out_uop.fu_code[1] \n connect issue_slots[8].in_uop.bits.fu_code[2], issue_slots[9].out_uop.fu_code[2] \n connect issue_slots[8].in_uop.bits.fu_code[3], issue_slots[9].out_uop.fu_code[3] \n connect issue_slots[8].in_uop.bits.fu_code[4], issue_slots[9].out_uop.fu_code[4] \n connect issue_slots[8].in_uop.bits.fu_code[5], issue_slots[9].out_uop.fu_code[5] \n connect issue_slots[8].in_uop.bits.fu_code[6], issue_slots[9].out_uop.fu_code[6] \n connect issue_slots[8].in_uop.bits.fu_code[7], issue_slots[9].out_uop.fu_code[7] \n connect issue_slots[8].in_uop.bits.fu_code[8], issue_slots[9].out_uop.fu_code[8] \n connect issue_slots[8].in_uop.bits.fu_code[9], issue_slots[9].out_uop.fu_code[9] \n connect issue_slots[8].in_uop.bits.iq_type[0], issue_slots[9].out_uop.iq_type[0] \n connect issue_slots[8].in_uop.bits.iq_type[1], issue_slots[9].out_uop.iq_type[1] \n connect issue_slots[8].in_uop.bits.iq_type[2], issue_slots[9].out_uop.iq_type[2] \n connect issue_slots[8].in_uop.bits.iq_type[3], issue_slots[9].out_uop.iq_type[3] \n connect issue_slots[8].in_uop.bits.debug_pc, issue_slots[9].out_uop.debug_pc \n connect issue_slots[8].in_uop.bits.is_rvc, issue_slots[9].out_uop.is_rvc \n connect issue_slots[8].in_uop.bits.debug_inst, issue_slots[9].out_uop.debug_inst \n connect issue_slots[8].in_uop.bits.inst, issue_slots[9].out_uop.inst \n node _T_178 = eq(shamts_oh[9], UInt<1>(0h1)) \n when _T_178 : \n connect issue_slots[8].in_uop.valid, issue_slots[9].will_be_valid \n connect issue_slots[8].in_uop.bits.debug_tsrc, issue_slots[9].out_uop.debug_tsrc \n connect issue_slots[8].in_uop.bits.debug_fsrc, issue_slots[9].out_uop.debug_fsrc \n connect issue_slots[8].in_uop.bits.bp_xcpt_if, issue_slots[9].out_uop.bp_xcpt_if \n connect issue_slots[8].in_uop.bits.bp_debug_if, issue_slots[9].out_uop.bp_debug_if \n connect issue_slots[8].in_uop.bits.xcpt_ma_if, issue_slots[9].out_uop.xcpt_ma_if \n connect issue_slots[8].in_uop.bits.xcpt_ae_if, issue_slots[9].out_uop.xcpt_ae_if \n connect issue_slots[8].in_uop.bits.xcpt_pf_if, issue_slots[9].out_uop.xcpt_pf_if \n connect issue_slots[8].in_uop.bits.fp_typ, issue_slots[9].out_uop.fp_typ \n connect issue_slots[8].in_uop.bits.fp_rm, issue_slots[9].out_uop.fp_rm \n connect issue_slots[8].in_uop.bits.fp_val, issue_slots[9].out_uop.fp_val \n connect issue_slots[8].in_uop.bits.fcn_op, issue_slots[9].out_uop.fcn_op \n connect issue_slots[8].in_uop.bits.fcn_dw, issue_slots[9].out_uop.fcn_dw \n connect issue_slots[8].in_uop.bits.frs3_en, issue_slots[9].out_uop.frs3_en \n connect issue_slots[8].in_uop.bits.lrs2_rtype, issue_slots[9].out_uop.lrs2_rtype \n connect issue_slots[8].in_uop.bits.lrs1_rtype, issue_slots[9].out_uop.lrs1_rtype \n connect issue_slots[8].in_uop.bits.dst_rtype, issue_slots[9].out_uop.dst_rtype \n connect issue_slots[8].in_uop.bits.lrs3, issue_slots[9].out_uop.lrs3 \n connect issue_slots[8].in_uop.bits.lrs2, issue_slots[9].out_uop.lrs2 \n connect issue_slots[8].in_uop.bits.lrs1, issue_slots[9].out_uop.lrs1 \n connect issue_slots[8].in_uop.bits.ldst, issue_slots[9].out_uop.ldst \n connect issue_slots[8].in_uop.bits.ldst_is_rs1, issue_slots[9].out_uop.ldst_is_rs1 \n connect issue_slots[8].in_uop.bits.csr_cmd, issue_slots[9].out_uop.csr_cmd \n connect issue_slots[8].in_uop.bits.flush_on_commit, issue_slots[9].out_uop.flush_on_commit \n connect issue_slots[8].in_uop.bits.is_unique, issue_slots[9].out_uop.is_unique \n connect issue_slots[8].in_uop.bits.uses_stq, issue_slots[9].out_uop.uses_stq \n connect issue_slots[8].in_uop.bits.uses_ldq, issue_slots[9].out_uop.uses_ldq \n connect issue_slots[8].in_uop.bits.mem_signed, issue_slots[9].out_uop.mem_signed \n connect issue_slots[8].in_uop.bits.mem_size, issue_slots[9].out_uop.mem_size \n connect issue_slots[8].in_uop.bits.mem_cmd, issue_slots[9].out_uop.mem_cmd \n connect issue_slots[8].in_uop.bits.exc_cause, issue_slots[9].out_uop.exc_cause \n connect issue_slots[8].in_uop.bits.exception, issue_slots[9].out_uop.exception \n connect issue_slots[8].in_uop.bits.stale_pdst, issue_slots[9].out_uop.stale_pdst \n connect issue_slots[8].in_uop.bits.ppred_busy, issue_slots[9].out_uop.ppred_busy \n connect issue_slots[8].in_uop.bits.prs3_busy, issue_slots[9].out_uop.prs3_busy \n connect issue_slots[8].in_uop.bits.prs2_busy, issue_slots[9].out_uop.prs2_busy \n connect issue_slots[8].in_uop.bits.prs1_busy, issue_slots[9].out_uop.prs1_busy \n connect issue_slots[8].in_uop.bits.ppred, issue_slots[9].out_uop.ppred \n connect issue_slots[8].in_uop.bits.prs3, issue_slots[9].out_uop.prs3 \n connect issue_slots[8].in_uop.bits.prs2, issue_slots[9].out_uop.prs2 \n connect issue_slots[8].in_uop.bits.prs1, issue_slots[9].out_uop.prs1 \n connect issue_slots[8].in_uop.bits.pdst, issue_slots[9].out_uop.pdst \n connect issue_slots[8].in_uop.bits.rxq_idx, issue_slots[9].out_uop.rxq_idx \n connect issue_slots[8].in_uop.bits.stq_idx, issue_slots[9].out_uop.stq_idx \n connect issue_slots[8].in_uop.bits.ldq_idx, issue_slots[9].out_uop.ldq_idx \n connect issue_slots[8].in_uop.bits.rob_idx, issue_slots[9].out_uop.rob_idx \n connect issue_slots[8].in_uop.bits.fp_ctrl.vec, issue_slots[9].out_uop.fp_ctrl.vec \n connect issue_slots[8].in_uop.bits.fp_ctrl.wflags, issue_slots[9].out_uop.fp_ctrl.wflags \n connect issue_slots[8].in_uop.bits.fp_ctrl.sqrt, issue_slots[9].out_uop.fp_ctrl.sqrt \n connect issue_slots[8].in_uop.bits.fp_ctrl.div, issue_slots[9].out_uop.fp_ctrl.div \n connect issue_slots[8].in_uop.bits.fp_ctrl.fma, issue_slots[9].out_uop.fp_ctrl.fma \n connect issue_slots[8].in_uop.bits.fp_ctrl.fastpipe, issue_slots[9].out_uop.fp_ctrl.fastpipe \n connect issue_slots[8].in_uop.bits.fp_ctrl.toint, issue_slots[9].out_uop.fp_ctrl.toint \n connect issue_slots[8].in_uop.bits.fp_ctrl.fromint, issue_slots[9].out_uop.fp_ctrl.fromint \n connect issue_slots[8].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[9].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[8].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[9].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[8].in_uop.bits.fp_ctrl.swap23, issue_slots[9].out_uop.fp_ctrl.swap23 \n connect issue_slots[8].in_uop.bits.fp_ctrl.swap12, issue_slots[9].out_uop.fp_ctrl.swap12 \n connect issue_slots[8].in_uop.bits.fp_ctrl.ren3, issue_slots[9].out_uop.fp_ctrl.ren3 \n connect issue_slots[8].in_uop.bits.fp_ctrl.ren2, issue_slots[9].out_uop.fp_ctrl.ren2 \n connect issue_slots[8].in_uop.bits.fp_ctrl.ren1, issue_slots[9].out_uop.fp_ctrl.ren1 \n connect issue_slots[8].in_uop.bits.fp_ctrl.wen, issue_slots[9].out_uop.fp_ctrl.wen \n connect issue_slots[8].in_uop.bits.fp_ctrl.ldst, issue_slots[9].out_uop.fp_ctrl.ldst \n connect issue_slots[8].in_uop.bits.op2_sel, issue_slots[9].out_uop.op2_sel \n connect issue_slots[8].in_uop.bits.op1_sel, issue_slots[9].out_uop.op1_sel \n connect issue_slots[8].in_uop.bits.imm_packed, issue_slots[9].out_uop.imm_packed \n connect issue_slots[8].in_uop.bits.pimm, issue_slots[9].out_uop.pimm \n connect issue_slots[8].in_uop.bits.imm_sel, issue_slots[9].out_uop.imm_sel \n connect issue_slots[8].in_uop.bits.imm_rename, issue_slots[9].out_uop.imm_rename \n connect issue_slots[8].in_uop.bits.taken, issue_slots[9].out_uop.taken \n connect issue_slots[8].in_uop.bits.pc_lob, issue_slots[9].out_uop.pc_lob \n connect issue_slots[8].in_uop.bits.edge_inst, issue_slots[9].out_uop.edge_inst \n connect issue_slots[8].in_uop.bits.ftq_idx, issue_slots[9].out_uop.ftq_idx \n connect issue_slots[8].in_uop.bits.is_mov, issue_slots[9].out_uop.is_mov \n connect issue_slots[8].in_uop.bits.is_rocc, issue_slots[9].out_uop.is_rocc \n connect issue_slots[8].in_uop.bits.is_sys_pc2epc, issue_slots[9].out_uop.is_sys_pc2epc \n connect issue_slots[8].in_uop.bits.is_eret, issue_slots[9].out_uop.is_eret \n connect issue_slots[8].in_uop.bits.is_amo, issue_slots[9].out_uop.is_amo \n connect issue_slots[8].in_uop.bits.is_sfence, issue_slots[9].out_uop.is_sfence \n connect issue_slots[8].in_uop.bits.is_fencei, issue_slots[9].out_uop.is_fencei \n connect issue_slots[8].in_uop.bits.is_fence, issue_slots[9].out_uop.is_fence \n connect issue_slots[8].in_uop.bits.is_sfb, issue_slots[9].out_uop.is_sfb \n connect issue_slots[8].in_uop.bits.br_type, issue_slots[9].out_uop.br_type \n connect issue_slots[8].in_uop.bits.br_tag, issue_slots[9].out_uop.br_tag \n connect issue_slots[8].in_uop.bits.br_mask, issue_slots[9].out_uop.br_mask \n connect issue_slots[8].in_uop.bits.dis_col_sel, issue_slots[9].out_uop.dis_col_sel \n connect issue_slots[8].in_uop.bits.iw_p3_bypass_hint, issue_slots[9].out_uop.iw_p3_bypass_hint \n connect issue_slots[8].in_uop.bits.iw_p2_bypass_hint, issue_slots[9].out_uop.iw_p2_bypass_hint \n connect issue_slots[8].in_uop.bits.iw_p1_bypass_hint, issue_slots[9].out_uop.iw_p1_bypass_hint \n connect issue_slots[8].in_uop.bits.iw_p2_speculative_child, issue_slots[9].out_uop.iw_p2_speculative_child \n connect issue_slots[8].in_uop.bits.iw_p1_speculative_child, issue_slots[9].out_uop.iw_p1_speculative_child \n connect issue_slots[8].in_uop.bits.iw_issued_partial_dgen, issue_slots[9].out_uop.iw_issued_partial_dgen \n connect issue_slots[8].in_uop.bits.iw_issued_partial_agen, issue_slots[9].out_uop.iw_issued_partial_agen \n connect issue_slots[8].in_uop.bits.iw_issued, issue_slots[9].out_uop.iw_issued \n connect issue_slots[8].in_uop.bits.fu_code[0], issue_slots[9].out_uop.fu_code[0] \n connect issue_slots[8].in_uop.bits.fu_code[1], issue_slots[9].out_uop.fu_code[1] \n connect issue_slots[8].in_uop.bits.fu_code[2], issue_slots[9].out_uop.fu_code[2] \n connect issue_slots[8].in_uop.bits.fu_code[3], issue_slots[9].out_uop.fu_code[3] \n connect issue_slots[8].in_uop.bits.fu_code[4], issue_slots[9].out_uop.fu_code[4] \n connect issue_slots[8].in_uop.bits.fu_code[5], issue_slots[9].out_uop.fu_code[5] \n connect issue_slots[8].in_uop.bits.fu_code[6], issue_slots[9].out_uop.fu_code[6] \n connect issue_slots[8].in_uop.bits.fu_code[7], issue_slots[9].out_uop.fu_code[7] \n connect issue_slots[8].in_uop.bits.fu_code[8], issue_slots[9].out_uop.fu_code[8] \n connect issue_slots[8].in_uop.bits.fu_code[9], issue_slots[9].out_uop.fu_code[9] \n connect issue_slots[8].in_uop.bits.iq_type[0], issue_slots[9].out_uop.iq_type[0] \n connect issue_slots[8].in_uop.bits.iq_type[1], issue_slots[9].out_uop.iq_type[1] \n connect issue_slots[8].in_uop.bits.iq_type[2], issue_slots[9].out_uop.iq_type[2] \n connect issue_slots[8].in_uop.bits.iq_type[3], issue_slots[9].out_uop.iq_type[3] \n connect issue_slots[8].in_uop.bits.debug_pc, issue_slots[9].out_uop.debug_pc \n connect issue_slots[8].in_uop.bits.is_rvc, issue_slots[9].out_uop.is_rvc \n connect issue_slots[8].in_uop.bits.debug_inst, issue_slots[9].out_uop.debug_inst \n connect issue_slots[8].in_uop.bits.inst, issue_slots[9].out_uop.inst \n node _T_179 = eq(shamts_oh[10], UInt<2>(0h2)) \n when _T_179 : \n connect issue_slots[8].in_uop.valid, issue_slots[10].will_be_valid \n connect issue_slots[8].in_uop.bits.debug_tsrc, issue_slots[10].out_uop.debug_tsrc \n connect issue_slots[8].in_uop.bits.debug_fsrc, issue_slots[10].out_uop.debug_fsrc \n connect issue_slots[8].in_uop.bits.bp_xcpt_if, issue_slots[10].out_uop.bp_xcpt_if \n connect issue_slots[8].in_uop.bits.bp_debug_if, issue_slots[10].out_uop.bp_debug_if \n connect issue_slots[8].in_uop.bits.xcpt_ma_if, issue_slots[10].out_uop.xcpt_ma_if \n connect issue_slots[8].in_uop.bits.xcpt_ae_if, issue_slots[10].out_uop.xcpt_ae_if \n connect issue_slots[8].in_uop.bits.xcpt_pf_if, issue_slots[10].out_uop.xcpt_pf_if \n connect issue_slots[8].in_uop.bits.fp_typ, issue_slots[10].out_uop.fp_typ \n connect issue_slots[8].in_uop.bits.fp_rm, issue_slots[10].out_uop.fp_rm \n connect issue_slots[8].in_uop.bits.fp_val, issue_slots[10].out_uop.fp_val \n connect issue_slots[8].in_uop.bits.fcn_op, issue_slots[10].out_uop.fcn_op \n connect issue_slots[8].in_uop.bits.fcn_dw, issue_slots[10].out_uop.fcn_dw \n connect issue_slots[8].in_uop.bits.frs3_en, issue_slots[10].out_uop.frs3_en \n connect issue_slots[8].in_uop.bits.lrs2_rtype, issue_slots[10].out_uop.lrs2_rtype \n connect issue_slots[8].in_uop.bits.lrs1_rtype, issue_slots[10].out_uop.lrs1_rtype \n connect issue_slots[8].in_uop.bits.dst_rtype, issue_slots[10].out_uop.dst_rtype \n connect issue_slots[8].in_uop.bits.lrs3, issue_slots[10].out_uop.lrs3 \n connect issue_slots[8].in_uop.bits.lrs2, issue_slots[10].out_uop.lrs2 \n connect issue_slots[8].in_uop.bits.lrs1, issue_slots[10].out_uop.lrs1 \n connect issue_slots[8].in_uop.bits.ldst, issue_slots[10].out_uop.ldst \n connect issue_slots[8].in_uop.bits.ldst_is_rs1, issue_slots[10].out_uop.ldst_is_rs1 \n connect issue_slots[8].in_uop.bits.csr_cmd, issue_slots[10].out_uop.csr_cmd \n connect issue_slots[8].in_uop.bits.flush_on_commit, issue_slots[10].out_uop.flush_on_commit \n connect issue_slots[8].in_uop.bits.is_unique, issue_slots[10].out_uop.is_unique \n connect issue_slots[8].in_uop.bits.uses_stq, issue_slots[10].out_uop.uses_stq \n connect issue_slots[8].in_uop.bits.uses_ldq, issue_slots[10].out_uop.uses_ldq \n connect issue_slots[8].in_uop.bits.mem_signed, issue_slots[10].out_uop.mem_signed \n connect issue_slots[8].in_uop.bits.mem_size, issue_slots[10].out_uop.mem_size \n connect issue_slots[8].in_uop.bits.mem_cmd, issue_slots[10].out_uop.mem_cmd \n connect issue_slots[8].in_uop.bits.exc_cause, issue_slots[10].out_uop.exc_cause \n connect issue_slots[8].in_uop.bits.exception, issue_slots[10].out_uop.exception \n connect issue_slots[8].in_uop.bits.stale_pdst, issue_slots[10].out_uop.stale_pdst \n connect issue_slots[8].in_uop.bits.ppred_busy, issue_slots[10].out_uop.ppred_busy \n connect issue_slots[8].in_uop.bits.prs3_busy, issue_slots[10].out_uop.prs3_busy \n connect issue_slots[8].in_uop.bits.prs2_busy, issue_slots[10].out_uop.prs2_busy \n connect issue_slots[8].in_uop.bits.prs1_busy, issue_slots[10].out_uop.prs1_busy \n connect issue_slots[8].in_uop.bits.ppred, issue_slots[10].out_uop.ppred \n connect issue_slots[8].in_uop.bits.prs3, issue_slots[10].out_uop.prs3 \n connect issue_slots[8].in_uop.bits.prs2, issue_slots[10].out_uop.prs2 \n connect issue_slots[8].in_uop.bits.prs1, issue_slots[10].out_uop.prs1 \n connect issue_slots[8].in_uop.bits.pdst, issue_slots[10].out_uop.pdst \n connect issue_slots[8].in_uop.bits.rxq_idx, issue_slots[10].out_uop.rxq_idx \n connect issue_slots[8].in_uop.bits.stq_idx, issue_slots[10].out_uop.stq_idx \n connect issue_slots[8].in_uop.bits.ldq_idx, issue_slots[10].out_uop.ldq_idx \n connect issue_slots[8].in_uop.bits.rob_idx, issue_slots[10].out_uop.rob_idx \n connect issue_slots[8].in_uop.bits.fp_ctrl.vec, issue_slots[10].out_uop.fp_ctrl.vec \n connect issue_slots[8].in_uop.bits.fp_ctrl.wflags, issue_slots[10].out_uop.fp_ctrl.wflags \n connect issue_slots[8].in_uop.bits.fp_ctrl.sqrt, issue_slots[10].out_uop.fp_ctrl.sqrt \n connect issue_slots[8].in_uop.bits.fp_ctrl.div, issue_slots[10].out_uop.fp_ctrl.div \n connect issue_slots[8].in_uop.bits.fp_ctrl.fma, issue_slots[10].out_uop.fp_ctrl.fma \n connect issue_slots[8].in_uop.bits.fp_ctrl.fastpipe, issue_slots[10].out_uop.fp_ctrl.fastpipe \n connect issue_slots[8].in_uop.bits.fp_ctrl.toint, issue_slots[10].out_uop.fp_ctrl.toint \n connect issue_slots[8].in_uop.bits.fp_ctrl.fromint, issue_slots[10].out_uop.fp_ctrl.fromint \n connect issue_slots[8].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[10].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[8].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[10].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[8].in_uop.bits.fp_ctrl.swap23, issue_slots[10].out_uop.fp_ctrl.swap23 \n connect issue_slots[8].in_uop.bits.fp_ctrl.swap12, issue_slots[10].out_uop.fp_ctrl.swap12 \n connect issue_slots[8].in_uop.bits.fp_ctrl.ren3, issue_slots[10].out_uop.fp_ctrl.ren3 \n connect issue_slots[8].in_uop.bits.fp_ctrl.ren2, issue_slots[10].out_uop.fp_ctrl.ren2 \n connect issue_slots[8].in_uop.bits.fp_ctrl.ren1, issue_slots[10].out_uop.fp_ctrl.ren1 \n connect issue_slots[8].in_uop.bits.fp_ctrl.wen, issue_slots[10].out_uop.fp_ctrl.wen \n connect issue_slots[8].in_uop.bits.fp_ctrl.ldst, issue_slots[10].out_uop.fp_ctrl.ldst \n connect issue_slots[8].in_uop.bits.op2_sel, issue_slots[10].out_uop.op2_sel \n connect issue_slots[8].in_uop.bits.op1_sel, issue_slots[10].out_uop.op1_sel \n connect issue_slots[8].in_uop.bits.imm_packed, issue_slots[10].out_uop.imm_packed \n connect issue_slots[8].in_uop.bits.pimm, issue_slots[10].out_uop.pimm \n connect issue_slots[8].in_uop.bits.imm_sel, issue_slots[10].out_uop.imm_sel \n connect issue_slots[8].in_uop.bits.imm_rename, issue_slots[10].out_uop.imm_rename \n connect issue_slots[8].in_uop.bits.taken, issue_slots[10].out_uop.taken \n connect issue_slots[8].in_uop.bits.pc_lob, issue_slots[10].out_uop.pc_lob \n connect issue_slots[8].in_uop.bits.edge_inst, issue_slots[10].out_uop.edge_inst \n connect issue_slots[8].in_uop.bits.ftq_idx, issue_slots[10].out_uop.ftq_idx \n connect issue_slots[8].in_uop.bits.is_mov, issue_slots[10].out_uop.is_mov \n connect issue_slots[8].in_uop.bits.is_rocc, issue_slots[10].out_uop.is_rocc \n connect issue_slots[8].in_uop.bits.is_sys_pc2epc, issue_slots[10].out_uop.is_sys_pc2epc \n connect issue_slots[8].in_uop.bits.is_eret, issue_slots[10].out_uop.is_eret \n connect issue_slots[8].in_uop.bits.is_amo, issue_slots[10].out_uop.is_amo \n connect issue_slots[8].in_uop.bits.is_sfence, issue_slots[10].out_uop.is_sfence \n connect issue_slots[8].in_uop.bits.is_fencei, issue_slots[10].out_uop.is_fencei \n connect issue_slots[8].in_uop.bits.is_fence, issue_slots[10].out_uop.is_fence \n connect issue_slots[8].in_uop.bits.is_sfb, issue_slots[10].out_uop.is_sfb \n connect issue_slots[8].in_uop.bits.br_type, issue_slots[10].out_uop.br_type \n connect issue_slots[8].in_uop.bits.br_tag, issue_slots[10].out_uop.br_tag \n connect issue_slots[8].in_uop.bits.br_mask, issue_slots[10].out_uop.br_mask \n connect issue_slots[8].in_uop.bits.dis_col_sel, issue_slots[10].out_uop.dis_col_sel \n connect issue_slots[8].in_uop.bits.iw_p3_bypass_hint, issue_slots[10].out_uop.iw_p3_bypass_hint \n connect issue_slots[8].in_uop.bits.iw_p2_bypass_hint, issue_slots[10].out_uop.iw_p2_bypass_hint \n connect issue_slots[8].in_uop.bits.iw_p1_bypass_hint, issue_slots[10].out_uop.iw_p1_bypass_hint \n connect issue_slots[8].in_uop.bits.iw_p2_speculative_child, issue_slots[10].out_uop.iw_p2_speculative_child \n connect issue_slots[8].in_uop.bits.iw_p1_speculative_child, issue_slots[10].out_uop.iw_p1_speculative_child \n connect issue_slots[8].in_uop.bits.iw_issued_partial_dgen, issue_slots[10].out_uop.iw_issued_partial_dgen \n connect issue_slots[8].in_uop.bits.iw_issued_partial_agen, issue_slots[10].out_uop.iw_issued_partial_agen \n connect issue_slots[8].in_uop.bits.iw_issued, issue_slots[10].out_uop.iw_issued \n connect issue_slots[8].in_uop.bits.fu_code[0], issue_slots[10].out_uop.fu_code[0] \n connect issue_slots[8].in_uop.bits.fu_code[1], issue_slots[10].out_uop.fu_code[1] \n connect issue_slots[8].in_uop.bits.fu_code[2], issue_slots[10].out_uop.fu_code[2] \n connect issue_slots[8].in_uop.bits.fu_code[3], issue_slots[10].out_uop.fu_code[3] \n connect issue_slots[8].in_uop.bits.fu_code[4], issue_slots[10].out_uop.fu_code[4] \n connect issue_slots[8].in_uop.bits.fu_code[5], issue_slots[10].out_uop.fu_code[5] \n connect issue_slots[8].in_uop.bits.fu_code[6], issue_slots[10].out_uop.fu_code[6] \n connect issue_slots[8].in_uop.bits.fu_code[7], issue_slots[10].out_uop.fu_code[7] \n connect issue_slots[8].in_uop.bits.fu_code[8], issue_slots[10].out_uop.fu_code[8] \n connect issue_slots[8].in_uop.bits.fu_code[9], issue_slots[10].out_uop.fu_code[9] \n connect issue_slots[8].in_uop.bits.iq_type[0], issue_slots[10].out_uop.iq_type[0] \n connect issue_slots[8].in_uop.bits.iq_type[1], issue_slots[10].out_uop.iq_type[1] \n connect issue_slots[8].in_uop.bits.iq_type[2], issue_slots[10].out_uop.iq_type[2] \n connect issue_slots[8].in_uop.bits.iq_type[3], issue_slots[10].out_uop.iq_type[3] \n connect issue_slots[8].in_uop.bits.debug_pc, issue_slots[10].out_uop.debug_pc \n connect issue_slots[8].in_uop.bits.is_rvc, issue_slots[10].out_uop.is_rvc \n connect issue_slots[8].in_uop.bits.debug_inst, issue_slots[10].out_uop.debug_inst \n connect issue_slots[8].in_uop.bits.inst, issue_slots[10].out_uop.inst \n node _issue_slots_8_clear_T = neq(shamts_oh[8], UInt<1>(0h0)) \n connect issue_slots[8].clear, _issue_slots_8_clear_T \n connect issue_slots[9].in_uop.valid, UInt<1>(0h0) \n connect issue_slots[9].in_uop.bits.debug_tsrc, issue_slots[10].out_uop.debug_tsrc \n connect issue_slots[9].in_uop.bits.debug_fsrc, issue_slots[10].out_uop.debug_fsrc \n connect issue_slots[9].in_uop.bits.bp_xcpt_if, issue_slots[10].out_uop.bp_xcpt_if \n connect issue_slots[9].in_uop.bits.bp_debug_if, issue_slots[10].out_uop.bp_debug_if \n connect issue_slots[9].in_uop.bits.xcpt_ma_if, issue_slots[10].out_uop.xcpt_ma_if \n connect issue_slots[9].in_uop.bits.xcpt_ae_if, issue_slots[10].out_uop.xcpt_ae_if \n connect issue_slots[9].in_uop.bits.xcpt_pf_if, issue_slots[10].out_uop.xcpt_pf_if \n connect issue_slots[9].in_uop.bits.fp_typ, issue_slots[10].out_uop.fp_typ \n connect issue_slots[9].in_uop.bits.fp_rm, issue_slots[10].out_uop.fp_rm \n connect issue_slots[9].in_uop.bits.fp_val, issue_slots[10].out_uop.fp_val \n connect issue_slots[9].in_uop.bits.fcn_op, issue_slots[10].out_uop.fcn_op \n connect issue_slots[9].in_uop.bits.fcn_dw, issue_slots[10].out_uop.fcn_dw \n connect issue_slots[9].in_uop.bits.frs3_en, issue_slots[10].out_uop.frs3_en \n connect issue_slots[9].in_uop.bits.lrs2_rtype, issue_slots[10].out_uop.lrs2_rtype \n connect issue_slots[9].in_uop.bits.lrs1_rtype, issue_slots[10].out_uop.lrs1_rtype \n connect issue_slots[9].in_uop.bits.dst_rtype, issue_slots[10].out_uop.dst_rtype \n connect issue_slots[9].in_uop.bits.lrs3, issue_slots[10].out_uop.lrs3 \n connect issue_slots[9].in_uop.bits.lrs2, issue_slots[10].out_uop.lrs2 \n connect issue_slots[9].in_uop.bits.lrs1, issue_slots[10].out_uop.lrs1 \n connect issue_slots[9].in_uop.bits.ldst, issue_slots[10].out_uop.ldst \n connect issue_slots[9].in_uop.bits.ldst_is_rs1, issue_slots[10].out_uop.ldst_is_rs1 \n connect issue_slots[9].in_uop.bits.csr_cmd, issue_slots[10].out_uop.csr_cmd \n connect issue_slots[9].in_uop.bits.flush_on_commit, issue_slots[10].out_uop.flush_on_commit \n connect issue_slots[9].in_uop.bits.is_unique, issue_slots[10].out_uop.is_unique \n connect issue_slots[9].in_uop.bits.uses_stq, issue_slots[10].out_uop.uses_stq \n connect issue_slots[9].in_uop.bits.uses_ldq, issue_slots[10].out_uop.uses_ldq \n connect issue_slots[9].in_uop.bits.mem_signed, issue_slots[10].out_uop.mem_signed \n connect issue_slots[9].in_uop.bits.mem_size, issue_slots[10].out_uop.mem_size \n connect issue_slots[9].in_uop.bits.mem_cmd, issue_slots[10].out_uop.mem_cmd \n connect issue_slots[9].in_uop.bits.exc_cause, issue_slots[10].out_uop.exc_cause \n connect issue_slots[9].in_uop.bits.exception, issue_slots[10].out_uop.exception \n connect issue_slots[9].in_uop.bits.stale_pdst, issue_slots[10].out_uop.stale_pdst \n connect issue_slots[9].in_uop.bits.ppred_busy, issue_slots[10].out_uop.ppred_busy \n connect issue_slots[9].in_uop.bits.prs3_busy, issue_slots[10].out_uop.prs3_busy \n connect issue_slots[9].in_uop.bits.prs2_busy, issue_slots[10].out_uop.prs2_busy \n connect issue_slots[9].in_uop.bits.prs1_busy, issue_slots[10].out_uop.prs1_busy \n connect issue_slots[9].in_uop.bits.ppred, issue_slots[10].out_uop.ppred \n connect issue_slots[9].in_uop.bits.prs3, issue_slots[10].out_uop.prs3 \n connect issue_slots[9].in_uop.bits.prs2, issue_slots[10].out_uop.prs2 \n connect issue_slots[9].in_uop.bits.prs1, issue_slots[10].out_uop.prs1 \n connect issue_slots[9].in_uop.bits.pdst, issue_slots[10].out_uop.pdst \n connect issue_slots[9].in_uop.bits.rxq_idx, issue_slots[10].out_uop.rxq_idx \n connect issue_slots[9].in_uop.bits.stq_idx, issue_slots[10].out_uop.stq_idx \n connect issue_slots[9].in_uop.bits.ldq_idx, issue_slots[10].out_uop.ldq_idx \n connect issue_slots[9].in_uop.bits.rob_idx, issue_slots[10].out_uop.rob_idx \n connect issue_slots[9].in_uop.bits.fp_ctrl.vec, issue_slots[10].out_uop.fp_ctrl.vec \n connect issue_slots[9].in_uop.bits.fp_ctrl.wflags, issue_slots[10].out_uop.fp_ctrl.wflags \n connect issue_slots[9].in_uop.bits.fp_ctrl.sqrt, issue_slots[10].out_uop.fp_ctrl.sqrt \n connect issue_slots[9].in_uop.bits.fp_ctrl.div, issue_slots[10].out_uop.fp_ctrl.div \n connect issue_slots[9].in_uop.bits.fp_ctrl.fma, issue_slots[10].out_uop.fp_ctrl.fma \n connect issue_slots[9].in_uop.bits.fp_ctrl.fastpipe, issue_slots[10].out_uop.fp_ctrl.fastpipe \n connect issue_slots[9].in_uop.bits.fp_ctrl.toint, issue_slots[10].out_uop.fp_ctrl.toint \n connect issue_slots[9].in_uop.bits.fp_ctrl.fromint, issue_slots[10].out_uop.fp_ctrl.fromint \n connect issue_slots[9].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[10].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[9].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[10].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[9].in_uop.bits.fp_ctrl.swap23, issue_slots[10].out_uop.fp_ctrl.swap23 \n connect issue_slots[9].in_uop.bits.fp_ctrl.swap12, issue_slots[10].out_uop.fp_ctrl.swap12 \n connect issue_slots[9].in_uop.bits.fp_ctrl.ren3, issue_slots[10].out_uop.fp_ctrl.ren3 \n connect issue_slots[9].in_uop.bits.fp_ctrl.ren2, issue_slots[10].out_uop.fp_ctrl.ren2 \n connect issue_slots[9].in_uop.bits.fp_ctrl.ren1, issue_slots[10].out_uop.fp_ctrl.ren1 \n connect issue_slots[9].in_uop.bits.fp_ctrl.wen, issue_slots[10].out_uop.fp_ctrl.wen \n connect issue_slots[9].in_uop.bits.fp_ctrl.ldst, issue_slots[10].out_uop.fp_ctrl.ldst \n connect issue_slots[9].in_uop.bits.op2_sel, issue_slots[10].out_uop.op2_sel \n connect issue_slots[9].in_uop.bits.op1_sel, issue_slots[10].out_uop.op1_sel \n connect issue_slots[9].in_uop.bits.imm_packed, issue_slots[10].out_uop.imm_packed \n connect issue_slots[9].in_uop.bits.pimm, issue_slots[10].out_uop.pimm \n connect issue_slots[9].in_uop.bits.imm_sel, issue_slots[10].out_uop.imm_sel \n connect issue_slots[9].in_uop.bits.imm_rename, issue_slots[10].out_uop.imm_rename \n connect issue_slots[9].in_uop.bits.taken, issue_slots[10].out_uop.taken \n connect issue_slots[9].in_uop.bits.pc_lob, issue_slots[10].out_uop.pc_lob \n connect issue_slots[9].in_uop.bits.edge_inst, issue_slots[10].out_uop.edge_inst \n connect issue_slots[9].in_uop.bits.ftq_idx, issue_slots[10].out_uop.ftq_idx \n connect issue_slots[9].in_uop.bits.is_mov, issue_slots[10].out_uop.is_mov \n connect issue_slots[9].in_uop.bits.is_rocc, issue_slots[10].out_uop.is_rocc \n connect issue_slots[9].in_uop.bits.is_sys_pc2epc, issue_slots[10].out_uop.is_sys_pc2epc \n connect issue_slots[9].in_uop.bits.is_eret, issue_slots[10].out_uop.is_eret \n connect issue_slots[9].in_uop.bits.is_amo, issue_slots[10].out_uop.is_amo \n connect issue_slots[9].in_uop.bits.is_sfence, issue_slots[10].out_uop.is_sfence \n connect issue_slots[9].in_uop.bits.is_fencei, issue_slots[10].out_uop.is_fencei \n connect issue_slots[9].in_uop.bits.is_fence, issue_slots[10].out_uop.is_fence \n connect issue_slots[9].in_uop.bits.is_sfb, issue_slots[10].out_uop.is_sfb \n connect issue_slots[9].in_uop.bits.br_type, issue_slots[10].out_uop.br_type \n connect issue_slots[9].in_uop.bits.br_tag, issue_slots[10].out_uop.br_tag \n connect issue_slots[9].in_uop.bits.br_mask, issue_slots[10].out_uop.br_mask \n connect issue_slots[9].in_uop.bits.dis_col_sel, issue_slots[10].out_uop.dis_col_sel \n connect issue_slots[9].in_uop.bits.iw_p3_bypass_hint, issue_slots[10].out_uop.iw_p3_bypass_hint \n connect issue_slots[9].in_uop.bits.iw_p2_bypass_hint, issue_slots[10].out_uop.iw_p2_bypass_hint \n connect issue_slots[9].in_uop.bits.iw_p1_bypass_hint, issue_slots[10].out_uop.iw_p1_bypass_hint \n connect issue_slots[9].in_uop.bits.iw_p2_speculative_child, issue_slots[10].out_uop.iw_p2_speculative_child \n connect issue_slots[9].in_uop.bits.iw_p1_speculative_child, issue_slots[10].out_uop.iw_p1_speculative_child \n connect issue_slots[9].in_uop.bits.iw_issued_partial_dgen, issue_slots[10].out_uop.iw_issued_partial_dgen \n connect issue_slots[9].in_uop.bits.iw_issued_partial_agen, issue_slots[10].out_uop.iw_issued_partial_agen \n connect issue_slots[9].in_uop.bits.iw_issued, issue_slots[10].out_uop.iw_issued \n connect issue_slots[9].in_uop.bits.fu_code[0], issue_slots[10].out_uop.fu_code[0] \n connect issue_slots[9].in_uop.bits.fu_code[1], issue_slots[10].out_uop.fu_code[1] \n connect issue_slots[9].in_uop.bits.fu_code[2], issue_slots[10].out_uop.fu_code[2] \n connect issue_slots[9].in_uop.bits.fu_code[3], issue_slots[10].out_uop.fu_code[3] \n connect issue_slots[9].in_uop.bits.fu_code[4], issue_slots[10].out_uop.fu_code[4] \n connect issue_slots[9].in_uop.bits.fu_code[5], issue_slots[10].out_uop.fu_code[5] \n connect issue_slots[9].in_uop.bits.fu_code[6], issue_slots[10].out_uop.fu_code[6] \n connect issue_slots[9].in_uop.bits.fu_code[7], issue_slots[10].out_uop.fu_code[7] \n connect issue_slots[9].in_uop.bits.fu_code[8], issue_slots[10].out_uop.fu_code[8] \n connect issue_slots[9].in_uop.bits.fu_code[9], issue_slots[10].out_uop.fu_code[9] \n connect issue_slots[9].in_uop.bits.iq_type[0], issue_slots[10].out_uop.iq_type[0] \n connect issue_slots[9].in_uop.bits.iq_type[1], issue_slots[10].out_uop.iq_type[1] \n connect issue_slots[9].in_uop.bits.iq_type[2], issue_slots[10].out_uop.iq_type[2] \n connect issue_slots[9].in_uop.bits.iq_type[3], issue_slots[10].out_uop.iq_type[3] \n connect issue_slots[9].in_uop.bits.debug_pc, issue_slots[10].out_uop.debug_pc \n connect issue_slots[9].in_uop.bits.is_rvc, issue_slots[10].out_uop.is_rvc \n connect issue_slots[9].in_uop.bits.debug_inst, issue_slots[10].out_uop.debug_inst \n connect issue_slots[9].in_uop.bits.inst, issue_slots[10].out_uop.inst \n node _T_180 = eq(shamts_oh[10], UInt<1>(0h1)) \n when _T_180 : \n connect issue_slots[9].in_uop.valid, issue_slots[10].will_be_valid \n connect issue_slots[9].in_uop.bits.debug_tsrc, issue_slots[10].out_uop.debug_tsrc \n connect issue_slots[9].in_uop.bits.debug_fsrc, issue_slots[10].out_uop.debug_fsrc \n connect issue_slots[9].in_uop.bits.bp_xcpt_if, issue_slots[10].out_uop.bp_xcpt_if \n connect issue_slots[9].in_uop.bits.bp_debug_if, issue_slots[10].out_uop.bp_debug_if \n connect issue_slots[9].in_uop.bits.xcpt_ma_if, issue_slots[10].out_uop.xcpt_ma_if \n connect issue_slots[9].in_uop.bits.xcpt_ae_if, issue_slots[10].out_uop.xcpt_ae_if \n connect issue_slots[9].in_uop.bits.xcpt_pf_if, issue_slots[10].out_uop.xcpt_pf_if \n connect issue_slots[9].in_uop.bits.fp_typ, issue_slots[10].out_uop.fp_typ \n connect issue_slots[9].in_uop.bits.fp_rm, issue_slots[10].out_uop.fp_rm \n connect issue_slots[9].in_uop.bits.fp_val, issue_slots[10].out_uop.fp_val \n connect issue_slots[9].in_uop.bits.fcn_op, issue_slots[10].out_uop.fcn_op \n connect issue_slots[9].in_uop.bits.fcn_dw, issue_slots[10].out_uop.fcn_dw \n connect issue_slots[9].in_uop.bits.frs3_en, issue_slots[10].out_uop.frs3_en \n connect issue_slots[9].in_uop.bits.lrs2_rtype, issue_slots[10].out_uop.lrs2_rtype \n connect issue_slots[9].in_uop.bits.lrs1_rtype, issue_slots[10].out_uop.lrs1_rtype \n connect issue_slots[9].in_uop.bits.dst_rtype, issue_slots[10].out_uop.dst_rtype \n connect issue_slots[9].in_uop.bits.lrs3, issue_slots[10].out_uop.lrs3 \n connect issue_slots[9].in_uop.bits.lrs2, issue_slots[10].out_uop.lrs2 \n connect issue_slots[9].in_uop.bits.lrs1, issue_slots[10].out_uop.lrs1 \n connect issue_slots[9].in_uop.bits.ldst, issue_slots[10].out_uop.ldst \n connect issue_slots[9].in_uop.bits.ldst_is_rs1, issue_slots[10].out_uop.ldst_is_rs1 \n connect issue_slots[9].in_uop.bits.csr_cmd, issue_slots[10].out_uop.csr_cmd \n connect issue_slots[9].in_uop.bits.flush_on_commit, issue_slots[10].out_uop.flush_on_commit \n connect issue_slots[9].in_uop.bits.is_unique, issue_slots[10].out_uop.is_unique \n connect issue_slots[9].in_uop.bits.uses_stq, issue_slots[10].out_uop.uses_stq \n connect issue_slots[9].in_uop.bits.uses_ldq, issue_slots[10].out_uop.uses_ldq \n connect issue_slots[9].in_uop.bits.mem_signed, issue_slots[10].out_uop.mem_signed \n connect issue_slots[9].in_uop.bits.mem_size, issue_slots[10].out_uop.mem_size \n connect issue_slots[9].in_uop.bits.mem_cmd, issue_slots[10].out_uop.mem_cmd \n connect issue_slots[9].in_uop.bits.exc_cause, issue_slots[10].out_uop.exc_cause \n connect issue_slots[9].in_uop.bits.exception, issue_slots[10].out_uop.exception \n connect issue_slots[9].in_uop.bits.stale_pdst, issue_slots[10].out_uop.stale_pdst \n connect issue_slots[9].in_uop.bits.ppred_busy, issue_slots[10].out_uop.ppred_busy \n connect issue_slots[9].in_uop.bits.prs3_busy, issue_slots[10].out_uop.prs3_busy \n connect issue_slots[9].in_uop.bits.prs2_busy, issue_slots[10].out_uop.prs2_busy \n connect issue_slots[9].in_uop.bits.prs1_busy, issue_slots[10].out_uop.prs1_busy \n connect issue_slots[9].in_uop.bits.ppred, issue_slots[10].out_uop.ppred \n connect issue_slots[9].in_uop.bits.prs3, issue_slots[10].out_uop.prs3 \n connect issue_slots[9].in_uop.bits.prs2, issue_slots[10].out_uop.prs2 \n connect issue_slots[9].in_uop.bits.prs1, issue_slots[10].out_uop.prs1 \n connect issue_slots[9].in_uop.bits.pdst, issue_slots[10].out_uop.pdst \n connect issue_slots[9].in_uop.bits.rxq_idx, issue_slots[10].out_uop.rxq_idx \n connect issue_slots[9].in_uop.bits.stq_idx, issue_slots[10].out_uop.stq_idx \n connect issue_slots[9].in_uop.bits.ldq_idx, issue_slots[10].out_uop.ldq_idx \n connect issue_slots[9].in_uop.bits.rob_idx, issue_slots[10].out_uop.rob_idx \n connect issue_slots[9].in_uop.bits.fp_ctrl.vec, issue_slots[10].out_uop.fp_ctrl.vec \n connect issue_slots[9].in_uop.bits.fp_ctrl.wflags, issue_slots[10].out_uop.fp_ctrl.wflags \n connect issue_slots[9].in_uop.bits.fp_ctrl.sqrt, issue_slots[10].out_uop.fp_ctrl.sqrt \n connect issue_slots[9].in_uop.bits.fp_ctrl.div, issue_slots[10].out_uop.fp_ctrl.div \n connect issue_slots[9].in_uop.bits.fp_ctrl.fma, issue_slots[10].out_uop.fp_ctrl.fma \n connect issue_slots[9].in_uop.bits.fp_ctrl.fastpipe, issue_slots[10].out_uop.fp_ctrl.fastpipe \n connect issue_slots[9].in_uop.bits.fp_ctrl.toint, issue_slots[10].out_uop.fp_ctrl.toint \n connect issue_slots[9].in_uop.bits.fp_ctrl.fromint, issue_slots[10].out_uop.fp_ctrl.fromint \n connect issue_slots[9].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[10].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[9].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[10].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[9].in_uop.bits.fp_ctrl.swap23, issue_slots[10].out_uop.fp_ctrl.swap23 \n connect issue_slots[9].in_uop.bits.fp_ctrl.swap12, issue_slots[10].out_uop.fp_ctrl.swap12 \n connect issue_slots[9].in_uop.bits.fp_ctrl.ren3, issue_slots[10].out_uop.fp_ctrl.ren3 \n connect issue_slots[9].in_uop.bits.fp_ctrl.ren2, issue_slots[10].out_uop.fp_ctrl.ren2 \n connect issue_slots[9].in_uop.bits.fp_ctrl.ren1, issue_slots[10].out_uop.fp_ctrl.ren1 \n connect issue_slots[9].in_uop.bits.fp_ctrl.wen, issue_slots[10].out_uop.fp_ctrl.wen \n connect issue_slots[9].in_uop.bits.fp_ctrl.ldst, issue_slots[10].out_uop.fp_ctrl.ldst \n connect issue_slots[9].in_uop.bits.op2_sel, issue_slots[10].out_uop.op2_sel \n connect issue_slots[9].in_uop.bits.op1_sel, issue_slots[10].out_uop.op1_sel \n connect issue_slots[9].in_uop.bits.imm_packed, issue_slots[10].out_uop.imm_packed \n connect issue_slots[9].in_uop.bits.pimm, issue_slots[10].out_uop.pimm \n connect issue_slots[9].in_uop.bits.imm_sel, issue_slots[10].out_uop.imm_sel \n connect issue_slots[9].in_uop.bits.imm_rename, issue_slots[10].out_uop.imm_rename \n connect issue_slots[9].in_uop.bits.taken, issue_slots[10].out_uop.taken \n connect issue_slots[9].in_uop.bits.pc_lob, issue_slots[10].out_uop.pc_lob \n connect issue_slots[9].in_uop.bits.edge_inst, issue_slots[10].out_uop.edge_inst \n connect issue_slots[9].in_uop.bits.ftq_idx, issue_slots[10].out_uop.ftq_idx \n connect issue_slots[9].in_uop.bits.is_mov, issue_slots[10].out_uop.is_mov \n connect issue_slots[9].in_uop.bits.is_rocc, issue_slots[10].out_uop.is_rocc \n connect issue_slots[9].in_uop.bits.is_sys_pc2epc, issue_slots[10].out_uop.is_sys_pc2epc \n connect issue_slots[9].in_uop.bits.is_eret, issue_slots[10].out_uop.is_eret \n connect issue_slots[9].in_uop.bits.is_amo, issue_slots[10].out_uop.is_amo \n connect issue_slots[9].in_uop.bits.is_sfence, issue_slots[10].out_uop.is_sfence \n connect issue_slots[9].in_uop.bits.is_fencei, issue_slots[10].out_uop.is_fencei \n connect issue_slots[9].in_uop.bits.is_fence, issue_slots[10].out_uop.is_fence \n connect issue_slots[9].in_uop.bits.is_sfb, issue_slots[10].out_uop.is_sfb \n connect issue_slots[9].in_uop.bits.br_type, issue_slots[10].out_uop.br_type \n connect issue_slots[9].in_uop.bits.br_tag, issue_slots[10].out_uop.br_tag \n connect issue_slots[9].in_uop.bits.br_mask, issue_slots[10].out_uop.br_mask \n connect issue_slots[9].in_uop.bits.dis_col_sel, issue_slots[10].out_uop.dis_col_sel \n connect issue_slots[9].in_uop.bits.iw_p3_bypass_hint, issue_slots[10].out_uop.iw_p3_bypass_hint \n connect issue_slots[9].in_uop.bits.iw_p2_bypass_hint, issue_slots[10].out_uop.iw_p2_bypass_hint \n connect issue_slots[9].in_uop.bits.iw_p1_bypass_hint, issue_slots[10].out_uop.iw_p1_bypass_hint \n connect issue_slots[9].in_uop.bits.iw_p2_speculative_child, issue_slots[10].out_uop.iw_p2_speculative_child \n connect issue_slots[9].in_uop.bits.iw_p1_speculative_child, issue_slots[10].out_uop.iw_p1_speculative_child \n connect issue_slots[9].in_uop.bits.iw_issued_partial_dgen, issue_slots[10].out_uop.iw_issued_partial_dgen \n connect issue_slots[9].in_uop.bits.iw_issued_partial_agen, issue_slots[10].out_uop.iw_issued_partial_agen \n connect issue_slots[9].in_uop.bits.iw_issued, issue_slots[10].out_uop.iw_issued \n connect issue_slots[9].in_uop.bits.fu_code[0], issue_slots[10].out_uop.fu_code[0] \n connect issue_slots[9].in_uop.bits.fu_code[1], issue_slots[10].out_uop.fu_code[1] \n connect issue_slots[9].in_uop.bits.fu_code[2], issue_slots[10].out_uop.fu_code[2] \n connect issue_slots[9].in_uop.bits.fu_code[3], issue_slots[10].out_uop.fu_code[3] \n connect issue_slots[9].in_uop.bits.fu_code[4], issue_slots[10].out_uop.fu_code[4] \n connect issue_slots[9].in_uop.bits.fu_code[5], issue_slots[10].out_uop.fu_code[5] \n connect issue_slots[9].in_uop.bits.fu_code[6], issue_slots[10].out_uop.fu_code[6] \n connect issue_slots[9].in_uop.bits.fu_code[7], issue_slots[10].out_uop.fu_code[7] \n connect issue_slots[9].in_uop.bits.fu_code[8], issue_slots[10].out_uop.fu_code[8] \n connect issue_slots[9].in_uop.bits.fu_code[9], issue_slots[10].out_uop.fu_code[9] \n connect issue_slots[9].in_uop.bits.iq_type[0], issue_slots[10].out_uop.iq_type[0] \n connect issue_slots[9].in_uop.bits.iq_type[1], issue_slots[10].out_uop.iq_type[1] \n connect issue_slots[9].in_uop.bits.iq_type[2], issue_slots[10].out_uop.iq_type[2] \n connect issue_slots[9].in_uop.bits.iq_type[3], issue_slots[10].out_uop.iq_type[3] \n connect issue_slots[9].in_uop.bits.debug_pc, issue_slots[10].out_uop.debug_pc \n connect issue_slots[9].in_uop.bits.is_rvc, issue_slots[10].out_uop.is_rvc \n connect issue_slots[9].in_uop.bits.debug_inst, issue_slots[10].out_uop.debug_inst \n connect issue_slots[9].in_uop.bits.inst, issue_slots[10].out_uop.inst \n node _T_181 = eq(shamts_oh[11], UInt<2>(0h2)) \n when _T_181 : \n connect issue_slots[9].in_uop.valid, issue_slots[11].will_be_valid \n connect issue_slots[9].in_uop.bits.debug_tsrc, issue_slots[11].out_uop.debug_tsrc \n connect issue_slots[9].in_uop.bits.debug_fsrc, issue_slots[11].out_uop.debug_fsrc \n connect issue_slots[9].in_uop.bits.bp_xcpt_if, issue_slots[11].out_uop.bp_xcpt_if \n connect issue_slots[9].in_uop.bits.bp_debug_if, issue_slots[11].out_uop.bp_debug_if \n connect issue_slots[9].in_uop.bits.xcpt_ma_if, issue_slots[11].out_uop.xcpt_ma_if \n connect issue_slots[9].in_uop.bits.xcpt_ae_if, issue_slots[11].out_uop.xcpt_ae_if \n connect issue_slots[9].in_uop.bits.xcpt_pf_if, issue_slots[11].out_uop.xcpt_pf_if \n connect issue_slots[9].in_uop.bits.fp_typ, issue_slots[11].out_uop.fp_typ \n connect issue_slots[9].in_uop.bits.fp_rm, issue_slots[11].out_uop.fp_rm \n connect issue_slots[9].in_uop.bits.fp_val, issue_slots[11].out_uop.fp_val \n connect issue_slots[9].in_uop.bits.fcn_op, issue_slots[11].out_uop.fcn_op \n connect issue_slots[9].in_uop.bits.fcn_dw, issue_slots[11].out_uop.fcn_dw \n connect issue_slots[9].in_uop.bits.frs3_en, issue_slots[11].out_uop.frs3_en \n connect issue_slots[9].in_uop.bits.lrs2_rtype, issue_slots[11].out_uop.lrs2_rtype \n connect issue_slots[9].in_uop.bits.lrs1_rtype, issue_slots[11].out_uop.lrs1_rtype \n connect issue_slots[9].in_uop.bits.dst_rtype, issue_slots[11].out_uop.dst_rtype \n connect issue_slots[9].in_uop.bits.lrs3, issue_slots[11].out_uop.lrs3 \n connect issue_slots[9].in_uop.bits.lrs2, issue_slots[11].out_uop.lrs2 \n connect issue_slots[9].in_uop.bits.lrs1, issue_slots[11].out_uop.lrs1 \n connect issue_slots[9].in_uop.bits.ldst, issue_slots[11].out_uop.ldst \n connect issue_slots[9].in_uop.bits.ldst_is_rs1, issue_slots[11].out_uop.ldst_is_rs1 \n connect issue_slots[9].in_uop.bits.csr_cmd, issue_slots[11].out_uop.csr_cmd \n connect issue_slots[9].in_uop.bits.flush_on_commit, issue_slots[11].out_uop.flush_on_commit \n connect issue_slots[9].in_uop.bits.is_unique, issue_slots[11].out_uop.is_unique \n connect issue_slots[9].in_uop.bits.uses_stq, issue_slots[11].out_uop.uses_stq \n connect issue_slots[9].in_uop.bits.uses_ldq, issue_slots[11].out_uop.uses_ldq \n connect issue_slots[9].in_uop.bits.mem_signed, issue_slots[11].out_uop.mem_signed \n connect issue_slots[9].in_uop.bits.mem_size, issue_slots[11].out_uop.mem_size \n connect issue_slots[9].in_uop.bits.mem_cmd, issue_slots[11].out_uop.mem_cmd \n connect issue_slots[9].in_uop.bits.exc_cause, issue_slots[11].out_uop.exc_cause \n connect issue_slots[9].in_uop.bits.exception, issue_slots[11].out_uop.exception \n connect issue_slots[9].in_uop.bits.stale_pdst, issue_slots[11].out_uop.stale_pdst \n connect issue_slots[9].in_uop.bits.ppred_busy, issue_slots[11].out_uop.ppred_busy \n connect issue_slots[9].in_uop.bits.prs3_busy, issue_slots[11].out_uop.prs3_busy \n connect issue_slots[9].in_uop.bits.prs2_busy, issue_slots[11].out_uop.prs2_busy \n connect issue_slots[9].in_uop.bits.prs1_busy, issue_slots[11].out_uop.prs1_busy \n connect issue_slots[9].in_uop.bits.ppred, issue_slots[11].out_uop.ppred \n connect issue_slots[9].in_uop.bits.prs3, issue_slots[11].out_uop.prs3 \n connect issue_slots[9].in_uop.bits.prs2, issue_slots[11].out_uop.prs2 \n connect issue_slots[9].in_uop.bits.prs1, issue_slots[11].out_uop.prs1 \n connect issue_slots[9].in_uop.bits.pdst, issue_slots[11].out_uop.pdst \n connect issue_slots[9].in_uop.bits.rxq_idx, issue_slots[11].out_uop.rxq_idx \n connect issue_slots[9].in_uop.bits.stq_idx, issue_slots[11].out_uop.stq_idx \n connect issue_slots[9].in_uop.bits.ldq_idx, issue_slots[11].out_uop.ldq_idx \n connect issue_slots[9].in_uop.bits.rob_idx, issue_slots[11].out_uop.rob_idx \n connect issue_slots[9].in_uop.bits.fp_ctrl.vec, issue_slots[11].out_uop.fp_ctrl.vec \n connect issue_slots[9].in_uop.bits.fp_ctrl.wflags, issue_slots[11].out_uop.fp_ctrl.wflags \n connect issue_slots[9].in_uop.bits.fp_ctrl.sqrt, issue_slots[11].out_uop.fp_ctrl.sqrt \n connect issue_slots[9].in_uop.bits.fp_ctrl.div, issue_slots[11].out_uop.fp_ctrl.div \n connect issue_slots[9].in_uop.bits.fp_ctrl.fma, issue_slots[11].out_uop.fp_ctrl.fma \n connect issue_slots[9].in_uop.bits.fp_ctrl.fastpipe, issue_slots[11].out_uop.fp_ctrl.fastpipe \n connect issue_slots[9].in_uop.bits.fp_ctrl.toint, issue_slots[11].out_uop.fp_ctrl.toint \n connect issue_slots[9].in_uop.bits.fp_ctrl.fromint, issue_slots[11].out_uop.fp_ctrl.fromint \n connect issue_slots[9].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[11].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[9].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[11].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[9].in_uop.bits.fp_ctrl.swap23, issue_slots[11].out_uop.fp_ctrl.swap23 \n connect issue_slots[9].in_uop.bits.fp_ctrl.swap12, issue_slots[11].out_uop.fp_ctrl.swap12 \n connect issue_slots[9].in_uop.bits.fp_ctrl.ren3, issue_slots[11].out_uop.fp_ctrl.ren3 \n connect issue_slots[9].in_uop.bits.fp_ctrl.ren2, issue_slots[11].out_uop.fp_ctrl.ren2 \n connect issue_slots[9].in_uop.bits.fp_ctrl.ren1, issue_slots[11].out_uop.fp_ctrl.ren1 \n connect issue_slots[9].in_uop.bits.fp_ctrl.wen, issue_slots[11].out_uop.fp_ctrl.wen \n connect issue_slots[9].in_uop.bits.fp_ctrl.ldst, issue_slots[11].out_uop.fp_ctrl.ldst \n connect issue_slots[9].in_uop.bits.op2_sel, issue_slots[11].out_uop.op2_sel \n connect issue_slots[9].in_uop.bits.op1_sel, issue_slots[11].out_uop.op1_sel \n connect issue_slots[9].in_uop.bits.imm_packed, issue_slots[11].out_uop.imm_packed \n connect issue_slots[9].in_uop.bits.pimm, issue_slots[11].out_uop.pimm \n connect issue_slots[9].in_uop.bits.imm_sel, issue_slots[11].out_uop.imm_sel \n connect issue_slots[9].in_uop.bits.imm_rename, issue_slots[11].out_uop.imm_rename \n connect issue_slots[9].in_uop.bits.taken, issue_slots[11].out_uop.taken \n connect issue_slots[9].in_uop.bits.pc_lob, issue_slots[11].out_uop.pc_lob \n connect issue_slots[9].in_uop.bits.edge_inst, issue_slots[11].out_uop.edge_inst \n connect issue_slots[9].in_uop.bits.ftq_idx, issue_slots[11].out_uop.ftq_idx \n connect issue_slots[9].in_uop.bits.is_mov, issue_slots[11].out_uop.is_mov \n connect issue_slots[9].in_uop.bits.is_rocc, issue_slots[11].out_uop.is_rocc \n connect issue_slots[9].in_uop.bits.is_sys_pc2epc, issue_slots[11].out_uop.is_sys_pc2epc \n connect issue_slots[9].in_uop.bits.is_eret, issue_slots[11].out_uop.is_eret \n connect issue_slots[9].in_uop.bits.is_amo, issue_slots[11].out_uop.is_amo \n connect issue_slots[9].in_uop.bits.is_sfence, issue_slots[11].out_uop.is_sfence \n connect issue_slots[9].in_uop.bits.is_fencei, issue_slots[11].out_uop.is_fencei \n connect issue_slots[9].in_uop.bits.is_fence, issue_slots[11].out_uop.is_fence \n connect issue_slots[9].in_uop.bits.is_sfb, issue_slots[11].out_uop.is_sfb \n connect issue_slots[9].in_uop.bits.br_type, issue_slots[11].out_uop.br_type \n connect issue_slots[9].in_uop.bits.br_tag, issue_slots[11].out_uop.br_tag \n connect issue_slots[9].in_uop.bits.br_mask, issue_slots[11].out_uop.br_mask \n connect issue_slots[9].in_uop.bits.dis_col_sel, issue_slots[11].out_uop.dis_col_sel \n connect issue_slots[9].in_uop.bits.iw_p3_bypass_hint, issue_slots[11].out_uop.iw_p3_bypass_hint \n connect issue_slots[9].in_uop.bits.iw_p2_bypass_hint, issue_slots[11].out_uop.iw_p2_bypass_hint \n connect issue_slots[9].in_uop.bits.iw_p1_bypass_hint, issue_slots[11].out_uop.iw_p1_bypass_hint \n connect issue_slots[9].in_uop.bits.iw_p2_speculative_child, issue_slots[11].out_uop.iw_p2_speculative_child \n connect issue_slots[9].in_uop.bits.iw_p1_speculative_child, issue_slots[11].out_uop.iw_p1_speculative_child \n connect issue_slots[9].in_uop.bits.iw_issued_partial_dgen, issue_slots[11].out_uop.iw_issued_partial_dgen \n connect issue_slots[9].in_uop.bits.iw_issued_partial_agen, issue_slots[11].out_uop.iw_issued_partial_agen \n connect issue_slots[9].in_uop.bits.iw_issued, issue_slots[11].out_uop.iw_issued \n connect issue_slots[9].in_uop.bits.fu_code[0], issue_slots[11].out_uop.fu_code[0] \n connect issue_slots[9].in_uop.bits.fu_code[1], issue_slots[11].out_uop.fu_code[1] \n connect issue_slots[9].in_uop.bits.fu_code[2], issue_slots[11].out_uop.fu_code[2] \n connect issue_slots[9].in_uop.bits.fu_code[3], issue_slots[11].out_uop.fu_code[3] \n connect issue_slots[9].in_uop.bits.fu_code[4], issue_slots[11].out_uop.fu_code[4] \n connect issue_slots[9].in_uop.bits.fu_code[5], issue_slots[11].out_uop.fu_code[5] \n connect issue_slots[9].in_uop.bits.fu_code[6], issue_slots[11].out_uop.fu_code[6] \n connect issue_slots[9].in_uop.bits.fu_code[7], issue_slots[11].out_uop.fu_code[7] \n connect issue_slots[9].in_uop.bits.fu_code[8], issue_slots[11].out_uop.fu_code[8] \n connect issue_slots[9].in_uop.bits.fu_code[9], issue_slots[11].out_uop.fu_code[9] \n connect issue_slots[9].in_uop.bits.iq_type[0], issue_slots[11].out_uop.iq_type[0] \n connect issue_slots[9].in_uop.bits.iq_type[1], issue_slots[11].out_uop.iq_type[1] \n connect issue_slots[9].in_uop.bits.iq_type[2], issue_slots[11].out_uop.iq_type[2] \n connect issue_slots[9].in_uop.bits.iq_type[3], issue_slots[11].out_uop.iq_type[3] \n connect issue_slots[9].in_uop.bits.debug_pc, issue_slots[11].out_uop.debug_pc \n connect issue_slots[9].in_uop.bits.is_rvc, issue_slots[11].out_uop.is_rvc \n connect issue_slots[9].in_uop.bits.debug_inst, issue_slots[11].out_uop.debug_inst \n connect issue_slots[9].in_uop.bits.inst, issue_slots[11].out_uop.inst \n node _issue_slots_9_clear_T = neq(shamts_oh[9], UInt<1>(0h0)) \n connect issue_slots[9].clear, _issue_slots_9_clear_T \n connect issue_slots[10].in_uop.valid, UInt<1>(0h0) \n connect issue_slots[10].in_uop.bits.debug_tsrc, issue_slots[11].out_uop.debug_tsrc \n connect issue_slots[10].in_uop.bits.debug_fsrc, issue_slots[11].out_uop.debug_fsrc \n connect issue_slots[10].in_uop.bits.bp_xcpt_if, issue_slots[11].out_uop.bp_xcpt_if \n connect issue_slots[10].in_uop.bits.bp_debug_if, issue_slots[11].out_uop.bp_debug_if \n connect issue_slots[10].in_uop.bits.xcpt_ma_if, issue_slots[11].out_uop.xcpt_ma_if \n connect issue_slots[10].in_uop.bits.xcpt_ae_if, issue_slots[11].out_uop.xcpt_ae_if \n connect issue_slots[10].in_uop.bits.xcpt_pf_if, issue_slots[11].out_uop.xcpt_pf_if \n connect issue_slots[10].in_uop.bits.fp_typ, issue_slots[11].out_uop.fp_typ \n connect issue_slots[10].in_uop.bits.fp_rm, issue_slots[11].out_uop.fp_rm \n connect issue_slots[10].in_uop.bits.fp_val, issue_slots[11].out_uop.fp_val \n connect issue_slots[10].in_uop.bits.fcn_op, issue_slots[11].out_uop.fcn_op \n connect issue_slots[10].in_uop.bits.fcn_dw, issue_slots[11].out_uop.fcn_dw \n connect issue_slots[10].in_uop.bits.frs3_en, issue_slots[11].out_uop.frs3_en \n connect issue_slots[10].in_uop.bits.lrs2_rtype, issue_slots[11].out_uop.lrs2_rtype \n connect issue_slots[10].in_uop.bits.lrs1_rtype, issue_slots[11].out_uop.lrs1_rtype \n connect issue_slots[10].in_uop.bits.dst_rtype, issue_slots[11].out_uop.dst_rtype \n connect issue_slots[10].in_uop.bits.lrs3, issue_slots[11].out_uop.lrs3 \n connect issue_slots[10].in_uop.bits.lrs2, issue_slots[11].out_uop.lrs2 \n connect issue_slots[10].in_uop.bits.lrs1, issue_slots[11].out_uop.lrs1 \n connect issue_slots[10].in_uop.bits.ldst, issue_slots[11].out_uop.ldst \n connect issue_slots[10].in_uop.bits.ldst_is_rs1, issue_slots[11].out_uop.ldst_is_rs1 \n connect issue_slots[10].in_uop.bits.csr_cmd, issue_slots[11].out_uop.csr_cmd \n connect issue_slots[10].in_uop.bits.flush_on_commit, issue_slots[11].out_uop.flush_on_commit \n connect issue_slots[10].in_uop.bits.is_unique, issue_slots[11].out_uop.is_unique \n connect issue_slots[10].in_uop.bits.uses_stq, issue_slots[11].out_uop.uses_stq \n connect issue_slots[10].in_uop.bits.uses_ldq, issue_slots[11].out_uop.uses_ldq \n connect issue_slots[10].in_uop.bits.mem_signed, issue_slots[11].out_uop.mem_signed \n connect issue_slots[10].in_uop.bits.mem_size, issue_slots[11].out_uop.mem_size \n connect issue_slots[10].in_uop.bits.mem_cmd, issue_slots[11].out_uop.mem_cmd \n connect issue_slots[10].in_uop.bits.exc_cause, issue_slots[11].out_uop.exc_cause \n connect issue_slots[10].in_uop.bits.exception, issue_slots[11].out_uop.exception \n connect issue_slots[10].in_uop.bits.stale_pdst, issue_slots[11].out_uop.stale_pdst \n connect issue_slots[10].in_uop.bits.ppred_busy, issue_slots[11].out_uop.ppred_busy \n connect issue_slots[10].in_uop.bits.prs3_busy, issue_slots[11].out_uop.prs3_busy \n connect issue_slots[10].in_uop.bits.prs2_busy, issue_slots[11].out_uop.prs2_busy \n connect issue_slots[10].in_uop.bits.prs1_busy, issue_slots[11].out_uop.prs1_busy \n connect issue_slots[10].in_uop.bits.ppred, issue_slots[11].out_uop.ppred \n connect issue_slots[10].in_uop.bits.prs3, issue_slots[11].out_uop.prs3 \n connect issue_slots[10].in_uop.bits.prs2, issue_slots[11].out_uop.prs2 \n connect issue_slots[10].in_uop.bits.prs1, issue_slots[11].out_uop.prs1 \n connect issue_slots[10].in_uop.bits.pdst, issue_slots[11].out_uop.pdst \n connect issue_slots[10].in_uop.bits.rxq_idx, issue_slots[11].out_uop.rxq_idx \n connect issue_slots[10].in_uop.bits.stq_idx, issue_slots[11].out_uop.stq_idx \n connect issue_slots[10].in_uop.bits.ldq_idx, issue_slots[11].out_uop.ldq_idx \n connect issue_slots[10].in_uop.bits.rob_idx, issue_slots[11].out_uop.rob_idx \n connect issue_slots[10].in_uop.bits.fp_ctrl.vec, issue_slots[11].out_uop.fp_ctrl.vec \n connect issue_slots[10].in_uop.bits.fp_ctrl.wflags, issue_slots[11].out_uop.fp_ctrl.wflags \n connect issue_slots[10].in_uop.bits.fp_ctrl.sqrt, issue_slots[11].out_uop.fp_ctrl.sqrt \n connect issue_slots[10].in_uop.bits.fp_ctrl.div, issue_slots[11].out_uop.fp_ctrl.div \n connect issue_slots[10].in_uop.bits.fp_ctrl.fma, issue_slots[11].out_uop.fp_ctrl.fma \n connect issue_slots[10].in_uop.bits.fp_ctrl.fastpipe, issue_slots[11].out_uop.fp_ctrl.fastpipe \n connect issue_slots[10].in_uop.bits.fp_ctrl.toint, issue_slots[11].out_uop.fp_ctrl.toint \n connect issue_slots[10].in_uop.bits.fp_ctrl.fromint, issue_slots[11].out_uop.fp_ctrl.fromint \n connect issue_slots[10].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[11].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[10].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[11].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[10].in_uop.bits.fp_ctrl.swap23, issue_slots[11].out_uop.fp_ctrl.swap23 \n connect issue_slots[10].in_uop.bits.fp_ctrl.swap12, issue_slots[11].out_uop.fp_ctrl.swap12 \n connect issue_slots[10].in_uop.bits.fp_ctrl.ren3, issue_slots[11].out_uop.fp_ctrl.ren3 \n connect issue_slots[10].in_uop.bits.fp_ctrl.ren2, issue_slots[11].out_uop.fp_ctrl.ren2 \n connect issue_slots[10].in_uop.bits.fp_ctrl.ren1, issue_slots[11].out_uop.fp_ctrl.ren1 \n connect issue_slots[10].in_uop.bits.fp_ctrl.wen, issue_slots[11].out_uop.fp_ctrl.wen \n connect issue_slots[10].in_uop.bits.fp_ctrl.ldst, issue_slots[11].out_uop.fp_ctrl.ldst \n connect issue_slots[10].in_uop.bits.op2_sel, issue_slots[11].out_uop.op2_sel \n connect issue_slots[10].in_uop.bits.op1_sel, issue_slots[11].out_uop.op1_sel \n connect issue_slots[10].in_uop.bits.imm_packed, issue_slots[11].out_uop.imm_packed \n connect issue_slots[10].in_uop.bits.pimm, issue_slots[11].out_uop.pimm \n connect issue_slots[10].in_uop.bits.imm_sel, issue_slots[11].out_uop.imm_sel \n connect issue_slots[10].in_uop.bits.imm_rename, issue_slots[11].out_uop.imm_rename \n connect issue_slots[10].in_uop.bits.taken, issue_slots[11].out_uop.taken \n connect issue_slots[10].in_uop.bits.pc_lob, issue_slots[11].out_uop.pc_lob \n connect issue_slots[10].in_uop.bits.edge_inst, issue_slots[11].out_uop.edge_inst \n connect issue_slots[10].in_uop.bits.ftq_idx, issue_slots[11].out_uop.ftq_idx \n connect issue_slots[10].in_uop.bits.is_mov, issue_slots[11].out_uop.is_mov \n connect issue_slots[10].in_uop.bits.is_rocc, issue_slots[11].out_uop.is_rocc \n connect issue_slots[10].in_uop.bits.is_sys_pc2epc, issue_slots[11].out_uop.is_sys_pc2epc \n connect issue_slots[10].in_uop.bits.is_eret, issue_slots[11].out_uop.is_eret \n connect issue_slots[10].in_uop.bits.is_amo, issue_slots[11].out_uop.is_amo \n connect issue_slots[10].in_uop.bits.is_sfence, issue_slots[11].out_uop.is_sfence \n connect issue_slots[10].in_uop.bits.is_fencei, issue_slots[11].out_uop.is_fencei \n connect issue_slots[10].in_uop.bits.is_fence, issue_slots[11].out_uop.is_fence \n connect issue_slots[10].in_uop.bits.is_sfb, issue_slots[11].out_uop.is_sfb \n connect issue_slots[10].in_uop.bits.br_type, issue_slots[11].out_uop.br_type \n connect issue_slots[10].in_uop.bits.br_tag, issue_slots[11].out_uop.br_tag \n connect issue_slots[10].in_uop.bits.br_mask, issue_slots[11].out_uop.br_mask \n connect issue_slots[10].in_uop.bits.dis_col_sel, issue_slots[11].out_uop.dis_col_sel \n connect issue_slots[10].in_uop.bits.iw_p3_bypass_hint, issue_slots[11].out_uop.iw_p3_bypass_hint \n connect issue_slots[10].in_uop.bits.iw_p2_bypass_hint, issue_slots[11].out_uop.iw_p2_bypass_hint \n connect issue_slots[10].in_uop.bits.iw_p1_bypass_hint, issue_slots[11].out_uop.iw_p1_bypass_hint \n connect issue_slots[10].in_uop.bits.iw_p2_speculative_child, issue_slots[11].out_uop.iw_p2_speculative_child \n connect issue_slots[10].in_uop.bits.iw_p1_speculative_child, issue_slots[11].out_uop.iw_p1_speculative_child \n connect issue_slots[10].in_uop.bits.iw_issued_partial_dgen, issue_slots[11].out_uop.iw_issued_partial_dgen \n connect issue_slots[10].in_uop.bits.iw_issued_partial_agen, issue_slots[11].out_uop.iw_issued_partial_agen \n connect issue_slots[10].in_uop.bits.iw_issued, issue_slots[11].out_uop.iw_issued \n connect issue_slots[10].in_uop.bits.fu_code[0], issue_slots[11].out_uop.fu_code[0] \n connect issue_slots[10].in_uop.bits.fu_code[1], issue_slots[11].out_uop.fu_code[1] \n connect issue_slots[10].in_uop.bits.fu_code[2], issue_slots[11].out_uop.fu_code[2] \n connect issue_slots[10].in_uop.bits.fu_code[3], issue_slots[11].out_uop.fu_code[3] \n connect issue_slots[10].in_uop.bits.fu_code[4], issue_slots[11].out_uop.fu_code[4] \n connect issue_slots[10].in_uop.bits.fu_code[5], issue_slots[11].out_uop.fu_code[5] \n connect issue_slots[10].in_uop.bits.fu_code[6], issue_slots[11].out_uop.fu_code[6] \n connect issue_slots[10].in_uop.bits.fu_code[7], issue_slots[11].out_uop.fu_code[7] \n connect issue_slots[10].in_uop.bits.fu_code[8], issue_slots[11].out_uop.fu_code[8] \n connect issue_slots[10].in_uop.bits.fu_code[9], issue_slots[11].out_uop.fu_code[9] \n connect issue_slots[10].in_uop.bits.iq_type[0], issue_slots[11].out_uop.iq_type[0] \n connect issue_slots[10].in_uop.bits.iq_type[1], issue_slots[11].out_uop.iq_type[1] \n connect issue_slots[10].in_uop.bits.iq_type[2], issue_slots[11].out_uop.iq_type[2] \n connect issue_slots[10].in_uop.bits.iq_type[3], issue_slots[11].out_uop.iq_type[3] \n connect issue_slots[10].in_uop.bits.debug_pc, issue_slots[11].out_uop.debug_pc \n connect issue_slots[10].in_uop.bits.is_rvc, issue_slots[11].out_uop.is_rvc \n connect issue_slots[10].in_uop.bits.debug_inst, issue_slots[11].out_uop.debug_inst \n connect issue_slots[10].in_uop.bits.inst, issue_slots[11].out_uop.inst \n node _T_182 = eq(shamts_oh[11], UInt<1>(0h1)) \n when _T_182 : \n connect issue_slots[10].in_uop.valid, issue_slots[11].will_be_valid \n connect issue_slots[10].in_uop.bits.debug_tsrc, issue_slots[11].out_uop.debug_tsrc \n connect issue_slots[10].in_uop.bits.debug_fsrc, issue_slots[11].out_uop.debug_fsrc \n connect issue_slots[10].in_uop.bits.bp_xcpt_if, issue_slots[11].out_uop.bp_xcpt_if \n connect issue_slots[10].in_uop.bits.bp_debug_if, issue_slots[11].out_uop.bp_debug_if \n connect issue_slots[10].in_uop.bits.xcpt_ma_if, issue_slots[11].out_uop.xcpt_ma_if \n connect issue_slots[10].in_uop.bits.xcpt_ae_if, issue_slots[11].out_uop.xcpt_ae_if \n connect issue_slots[10].in_uop.bits.xcpt_pf_if, issue_slots[11].out_uop.xcpt_pf_if \n connect issue_slots[10].in_uop.bits.fp_typ, issue_slots[11].out_uop.fp_typ \n connect issue_slots[10].in_uop.bits.fp_rm, issue_slots[11].out_uop.fp_rm \n connect issue_slots[10].in_uop.bits.fp_val, issue_slots[11].out_uop.fp_val \n connect issue_slots[10].in_uop.bits.fcn_op, issue_slots[11].out_uop.fcn_op \n connect issue_slots[10].in_uop.bits.fcn_dw, issue_slots[11].out_uop.fcn_dw \n connect issue_slots[10].in_uop.bits.frs3_en, issue_slots[11].out_uop.frs3_en \n connect issue_slots[10].in_uop.bits.lrs2_rtype, issue_slots[11].out_uop.lrs2_rtype \n connect issue_slots[10].in_uop.bits.lrs1_rtype, issue_slots[11].out_uop.lrs1_rtype \n connect issue_slots[10].in_uop.bits.dst_rtype, issue_slots[11].out_uop.dst_rtype \n connect issue_slots[10].in_uop.bits.lrs3, issue_slots[11].out_uop.lrs3 \n connect issue_slots[10].in_uop.bits.lrs2, issue_slots[11].out_uop.lrs2 \n connect issue_slots[10].in_uop.bits.lrs1, issue_slots[11].out_uop.lrs1 \n connect issue_slots[10].in_uop.bits.ldst, issue_slots[11].out_uop.ldst \n connect issue_slots[10].in_uop.bits.ldst_is_rs1, issue_slots[11].out_uop.ldst_is_rs1 \n connect issue_slots[10].in_uop.bits.csr_cmd, issue_slots[11].out_uop.csr_cmd \n connect issue_slots[10].in_uop.bits.flush_on_commit, issue_slots[11].out_uop.flush_on_commit \n connect issue_slots[10].in_uop.bits.is_unique, issue_slots[11].out_uop.is_unique \n connect issue_slots[10].in_uop.bits.uses_stq, issue_slots[11].out_uop.uses_stq \n connect issue_slots[10].in_uop.bits.uses_ldq, issue_slots[11].out_uop.uses_ldq \n connect issue_slots[10].in_uop.bits.mem_signed, issue_slots[11].out_uop.mem_signed \n connect issue_slots[10].in_uop.bits.mem_size, issue_slots[11].out_uop.mem_size \n connect issue_slots[10].in_uop.bits.mem_cmd, issue_slots[11].out_uop.mem_cmd \n connect issue_slots[10].in_uop.bits.exc_cause, issue_slots[11].out_uop.exc_cause \n connect issue_slots[10].in_uop.bits.exception, issue_slots[11].out_uop.exception \n connect issue_slots[10].in_uop.bits.stale_pdst, issue_slots[11].out_uop.stale_pdst \n connect issue_slots[10].in_uop.bits.ppred_busy, issue_slots[11].out_uop.ppred_busy \n connect issue_slots[10].in_uop.bits.prs3_busy, issue_slots[11].out_uop.prs3_busy \n connect issue_slots[10].in_uop.bits.prs2_busy, issue_slots[11].out_uop.prs2_busy \n connect issue_slots[10].in_uop.bits.prs1_busy, issue_slots[11].out_uop.prs1_busy \n connect issue_slots[10].in_uop.bits.ppred, issue_slots[11].out_uop.ppred \n connect issue_slots[10].in_uop.bits.prs3, issue_slots[11].out_uop.prs3 \n connect issue_slots[10].in_uop.bits.prs2, issue_slots[11].out_uop.prs2 \n connect issue_slots[10].in_uop.bits.prs1, issue_slots[11].out_uop.prs1 \n connect issue_slots[10].in_uop.bits.pdst, issue_slots[11].out_uop.pdst \n connect issue_slots[10].in_uop.bits.rxq_idx, issue_slots[11].out_uop.rxq_idx \n connect issue_slots[10].in_uop.bits.stq_idx, issue_slots[11].out_uop.stq_idx \n connect issue_slots[10].in_uop.bits.ldq_idx, issue_slots[11].out_uop.ldq_idx \n connect issue_slots[10].in_uop.bits.rob_idx, issue_slots[11].out_uop.rob_idx \n connect issue_slots[10].in_uop.bits.fp_ctrl.vec, issue_slots[11].out_uop.fp_ctrl.vec \n connect issue_slots[10].in_uop.bits.fp_ctrl.wflags, issue_slots[11].out_uop.fp_ctrl.wflags \n connect issue_slots[10].in_uop.bits.fp_ctrl.sqrt, issue_slots[11].out_uop.fp_ctrl.sqrt \n connect issue_slots[10].in_uop.bits.fp_ctrl.div, issue_slots[11].out_uop.fp_ctrl.div \n connect issue_slots[10].in_uop.bits.fp_ctrl.fma, issue_slots[11].out_uop.fp_ctrl.fma \n connect issue_slots[10].in_uop.bits.fp_ctrl.fastpipe, issue_slots[11].out_uop.fp_ctrl.fastpipe \n connect issue_slots[10].in_uop.bits.fp_ctrl.toint, issue_slots[11].out_uop.fp_ctrl.toint \n connect issue_slots[10].in_uop.bits.fp_ctrl.fromint, issue_slots[11].out_uop.fp_ctrl.fromint \n connect issue_slots[10].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[11].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[10].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[11].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[10].in_uop.bits.fp_ctrl.swap23, issue_slots[11].out_uop.fp_ctrl.swap23 \n connect issue_slots[10].in_uop.bits.fp_ctrl.swap12, issue_slots[11].out_uop.fp_ctrl.swap12 \n connect issue_slots[10].in_uop.bits.fp_ctrl.ren3, issue_slots[11].out_uop.fp_ctrl.ren3 \n connect issue_slots[10].in_uop.bits.fp_ctrl.ren2, issue_slots[11].out_uop.fp_ctrl.ren2 \n connect issue_slots[10].in_uop.bits.fp_ctrl.ren1, issue_slots[11].out_uop.fp_ctrl.ren1 \n connect issue_slots[10].in_uop.bits.fp_ctrl.wen, issue_slots[11].out_uop.fp_ctrl.wen \n connect issue_slots[10].in_uop.bits.fp_ctrl.ldst, issue_slots[11].out_uop.fp_ctrl.ldst \n connect issue_slots[10].in_uop.bits.op2_sel, issue_slots[11].out_uop.op2_sel \n connect issue_slots[10].in_uop.bits.op1_sel, issue_slots[11].out_uop.op1_sel \n connect issue_slots[10].in_uop.bits.imm_packed, issue_slots[11].out_uop.imm_packed \n connect issue_slots[10].in_uop.bits.pimm, issue_slots[11].out_uop.pimm \n connect issue_slots[10].in_uop.bits.imm_sel, issue_slots[11].out_uop.imm_sel \n connect issue_slots[10].in_uop.bits.imm_rename, issue_slots[11].out_uop.imm_rename \n connect issue_slots[10].in_uop.bits.taken, issue_slots[11].out_uop.taken \n connect issue_slots[10].in_uop.bits.pc_lob, issue_slots[11].out_uop.pc_lob \n connect issue_slots[10].in_uop.bits.edge_inst, issue_slots[11].out_uop.edge_inst \n connect issue_slots[10].in_uop.bits.ftq_idx, issue_slots[11].out_uop.ftq_idx \n connect issue_slots[10].in_uop.bits.is_mov, issue_slots[11].out_uop.is_mov \n connect issue_slots[10].in_uop.bits.is_rocc, issue_slots[11].out_uop.is_rocc \n connect issue_slots[10].in_uop.bits.is_sys_pc2epc, issue_slots[11].out_uop.is_sys_pc2epc \n connect issue_slots[10].in_uop.bits.is_eret, issue_slots[11].out_uop.is_eret \n connect issue_slots[10].in_uop.bits.is_amo, issue_slots[11].out_uop.is_amo \n connect issue_slots[10].in_uop.bits.is_sfence, issue_slots[11].out_uop.is_sfence \n connect issue_slots[10].in_uop.bits.is_fencei, issue_slots[11].out_uop.is_fencei \n connect issue_slots[10].in_uop.bits.is_fence, issue_slots[11].out_uop.is_fence \n connect issue_slots[10].in_uop.bits.is_sfb, issue_slots[11].out_uop.is_sfb \n connect issue_slots[10].in_uop.bits.br_type, issue_slots[11].out_uop.br_type \n connect issue_slots[10].in_uop.bits.br_tag, issue_slots[11].out_uop.br_tag \n connect issue_slots[10].in_uop.bits.br_mask, issue_slots[11].out_uop.br_mask \n connect issue_slots[10].in_uop.bits.dis_col_sel, issue_slots[11].out_uop.dis_col_sel \n connect issue_slots[10].in_uop.bits.iw_p3_bypass_hint, issue_slots[11].out_uop.iw_p3_bypass_hint \n connect issue_slots[10].in_uop.bits.iw_p2_bypass_hint, issue_slots[11].out_uop.iw_p2_bypass_hint \n connect issue_slots[10].in_uop.bits.iw_p1_bypass_hint, issue_slots[11].out_uop.iw_p1_bypass_hint \n connect issue_slots[10].in_uop.bits.iw_p2_speculative_child, issue_slots[11].out_uop.iw_p2_speculative_child \n connect issue_slots[10].in_uop.bits.iw_p1_speculative_child, issue_slots[11].out_uop.iw_p1_speculative_child \n connect issue_slots[10].in_uop.bits.iw_issued_partial_dgen, issue_slots[11].out_uop.iw_issued_partial_dgen \n connect issue_slots[10].in_uop.bits.iw_issued_partial_agen, issue_slots[11].out_uop.iw_issued_partial_agen \n connect issue_slots[10].in_uop.bits.iw_issued, issue_slots[11].out_uop.iw_issued \n connect issue_slots[10].in_uop.bits.fu_code[0], issue_slots[11].out_uop.fu_code[0] \n connect issue_slots[10].in_uop.bits.fu_code[1], issue_slots[11].out_uop.fu_code[1] \n connect issue_slots[10].in_uop.bits.fu_code[2], issue_slots[11].out_uop.fu_code[2] \n connect issue_slots[10].in_uop.bits.fu_code[3], issue_slots[11].out_uop.fu_code[3] \n connect issue_slots[10].in_uop.bits.fu_code[4], issue_slots[11].out_uop.fu_code[4] \n connect issue_slots[10].in_uop.bits.fu_code[5], issue_slots[11].out_uop.fu_code[5] \n connect issue_slots[10].in_uop.bits.fu_code[6], issue_slots[11].out_uop.fu_code[6] \n connect issue_slots[10].in_uop.bits.fu_code[7], issue_slots[11].out_uop.fu_code[7] \n connect issue_slots[10].in_uop.bits.fu_code[8], issue_slots[11].out_uop.fu_code[8] \n connect issue_slots[10].in_uop.bits.fu_code[9], issue_slots[11].out_uop.fu_code[9] \n connect issue_slots[10].in_uop.bits.iq_type[0], issue_slots[11].out_uop.iq_type[0] \n connect issue_slots[10].in_uop.bits.iq_type[1], issue_slots[11].out_uop.iq_type[1] \n connect issue_slots[10].in_uop.bits.iq_type[2], issue_slots[11].out_uop.iq_type[2] \n connect issue_slots[10].in_uop.bits.iq_type[3], issue_slots[11].out_uop.iq_type[3] \n connect issue_slots[10].in_uop.bits.debug_pc, issue_slots[11].out_uop.debug_pc \n connect issue_slots[10].in_uop.bits.is_rvc, issue_slots[11].out_uop.is_rvc \n connect issue_slots[10].in_uop.bits.debug_inst, issue_slots[11].out_uop.debug_inst \n connect issue_slots[10].in_uop.bits.inst, issue_slots[11].out_uop.inst \n node _T_183 = eq(shamts_oh[12], UInt<2>(0h2)) \n when _T_183 : \n connect issue_slots[10].in_uop.valid, issue_slots[12].will_be_valid \n connect issue_slots[10].in_uop.bits.debug_tsrc, issue_slots[12].out_uop.debug_tsrc \n connect issue_slots[10].in_uop.bits.debug_fsrc, issue_slots[12].out_uop.debug_fsrc \n connect issue_slots[10].in_uop.bits.bp_xcpt_if, issue_slots[12].out_uop.bp_xcpt_if \n connect issue_slots[10].in_uop.bits.bp_debug_if, issue_slots[12].out_uop.bp_debug_if \n connect issue_slots[10].in_uop.bits.xcpt_ma_if, issue_slots[12].out_uop.xcpt_ma_if \n connect issue_slots[10].in_uop.bits.xcpt_ae_if, issue_slots[12].out_uop.xcpt_ae_if \n connect issue_slots[10].in_uop.bits.xcpt_pf_if, issue_slots[12].out_uop.xcpt_pf_if \n connect issue_slots[10].in_uop.bits.fp_typ, issue_slots[12].out_uop.fp_typ \n connect issue_slots[10].in_uop.bits.fp_rm, issue_slots[12].out_uop.fp_rm \n connect issue_slots[10].in_uop.bits.fp_val, issue_slots[12].out_uop.fp_val \n connect issue_slots[10].in_uop.bits.fcn_op, issue_slots[12].out_uop.fcn_op \n connect issue_slots[10].in_uop.bits.fcn_dw, issue_slots[12].out_uop.fcn_dw \n connect issue_slots[10].in_uop.bits.frs3_en, issue_slots[12].out_uop.frs3_en \n connect issue_slots[10].in_uop.bits.lrs2_rtype, issue_slots[12].out_uop.lrs2_rtype \n connect issue_slots[10].in_uop.bits.lrs1_rtype, issue_slots[12].out_uop.lrs1_rtype \n connect issue_slots[10].in_uop.bits.dst_rtype, issue_slots[12].out_uop.dst_rtype \n connect issue_slots[10].in_uop.bits.lrs3, issue_slots[12].out_uop.lrs3 \n connect issue_slots[10].in_uop.bits.lrs2, issue_slots[12].out_uop.lrs2 \n connect issue_slots[10].in_uop.bits.lrs1, issue_slots[12].out_uop.lrs1 \n connect issue_slots[10].in_uop.bits.ldst, issue_slots[12].out_uop.ldst \n connect issue_slots[10].in_uop.bits.ldst_is_rs1, issue_slots[12].out_uop.ldst_is_rs1 \n connect issue_slots[10].in_uop.bits.csr_cmd, issue_slots[12].out_uop.csr_cmd \n connect issue_slots[10].in_uop.bits.flush_on_commit, issue_slots[12].out_uop.flush_on_commit \n connect issue_slots[10].in_uop.bits.is_unique, issue_slots[12].out_uop.is_unique \n connect issue_slots[10].in_uop.bits.uses_stq, issue_slots[12].out_uop.uses_stq \n connect issue_slots[10].in_uop.bits.uses_ldq, issue_slots[12].out_uop.uses_ldq \n connect issue_slots[10].in_uop.bits.mem_signed, issue_slots[12].out_uop.mem_signed \n connect issue_slots[10].in_uop.bits.mem_size, issue_slots[12].out_uop.mem_size \n connect issue_slots[10].in_uop.bits.mem_cmd, issue_slots[12].out_uop.mem_cmd \n connect issue_slots[10].in_uop.bits.exc_cause, issue_slots[12].out_uop.exc_cause \n connect issue_slots[10].in_uop.bits.exception, issue_slots[12].out_uop.exception \n connect issue_slots[10].in_uop.bits.stale_pdst, issue_slots[12].out_uop.stale_pdst \n connect issue_slots[10].in_uop.bits.ppred_busy, issue_slots[12].out_uop.ppred_busy \n connect issue_slots[10].in_uop.bits.prs3_busy, issue_slots[12].out_uop.prs3_busy \n connect issue_slots[10].in_uop.bits.prs2_busy, issue_slots[12].out_uop.prs2_busy \n connect issue_slots[10].in_uop.bits.prs1_busy, issue_slots[12].out_uop.prs1_busy \n connect issue_slots[10].in_uop.bits.ppred, issue_slots[12].out_uop.ppred \n connect issue_slots[10].in_uop.bits.prs3, issue_slots[12].out_uop.prs3 \n connect issue_slots[10].in_uop.bits.prs2, issue_slots[12].out_uop.prs2 \n connect issue_slots[10].in_uop.bits.prs1, issue_slots[12].out_uop.prs1 \n connect issue_slots[10].in_uop.bits.pdst, issue_slots[12].out_uop.pdst \n connect issue_slots[10].in_uop.bits.rxq_idx, issue_slots[12].out_uop.rxq_idx \n connect issue_slots[10].in_uop.bits.stq_idx, issue_slots[12].out_uop.stq_idx \n connect issue_slots[10].in_uop.bits.ldq_idx, issue_slots[12].out_uop.ldq_idx \n connect issue_slots[10].in_uop.bits.rob_idx, issue_slots[12].out_uop.rob_idx \n connect issue_slots[10].in_uop.bits.fp_ctrl.vec, issue_slots[12].out_uop.fp_ctrl.vec \n connect issue_slots[10].in_uop.bits.fp_ctrl.wflags, issue_slots[12].out_uop.fp_ctrl.wflags \n connect issue_slots[10].in_uop.bits.fp_ctrl.sqrt, issue_slots[12].out_uop.fp_ctrl.sqrt \n connect issue_slots[10].in_uop.bits.fp_ctrl.div, issue_slots[12].out_uop.fp_ctrl.div \n connect issue_slots[10].in_uop.bits.fp_ctrl.fma, issue_slots[12].out_uop.fp_ctrl.fma \n connect issue_slots[10].in_uop.bits.fp_ctrl.fastpipe, issue_slots[12].out_uop.fp_ctrl.fastpipe \n connect issue_slots[10].in_uop.bits.fp_ctrl.toint, issue_slots[12].out_uop.fp_ctrl.toint \n connect issue_slots[10].in_uop.bits.fp_ctrl.fromint, issue_slots[12].out_uop.fp_ctrl.fromint \n connect issue_slots[10].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[12].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[10].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[12].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[10].in_uop.bits.fp_ctrl.swap23, issue_slots[12].out_uop.fp_ctrl.swap23 \n connect issue_slots[10].in_uop.bits.fp_ctrl.swap12, issue_slots[12].out_uop.fp_ctrl.swap12 \n connect issue_slots[10].in_uop.bits.fp_ctrl.ren3, issue_slots[12].out_uop.fp_ctrl.ren3 \n connect issue_slots[10].in_uop.bits.fp_ctrl.ren2, issue_slots[12].out_uop.fp_ctrl.ren2 \n connect issue_slots[10].in_uop.bits.fp_ctrl.ren1, issue_slots[12].out_uop.fp_ctrl.ren1 \n connect issue_slots[10].in_uop.bits.fp_ctrl.wen, issue_slots[12].out_uop.fp_ctrl.wen \n connect issue_slots[10].in_uop.bits.fp_ctrl.ldst, issue_slots[12].out_uop.fp_ctrl.ldst \n connect issue_slots[10].in_uop.bits.op2_sel, issue_slots[12].out_uop.op2_sel \n connect issue_slots[10].in_uop.bits.op1_sel, issue_slots[12].out_uop.op1_sel \n connect issue_slots[10].in_uop.bits.imm_packed, issue_slots[12].out_uop.imm_packed \n connect issue_slots[10].in_uop.bits.pimm, issue_slots[12].out_uop.pimm \n connect issue_slots[10].in_uop.bits.imm_sel, issue_slots[12].out_uop.imm_sel \n connect issue_slots[10].in_uop.bits.imm_rename, issue_slots[12].out_uop.imm_rename \n connect issue_slots[10].in_uop.bits.taken, issue_slots[12].out_uop.taken \n connect issue_slots[10].in_uop.bits.pc_lob, issue_slots[12].out_uop.pc_lob \n connect issue_slots[10].in_uop.bits.edge_inst, issue_slots[12].out_uop.edge_inst \n connect issue_slots[10].in_uop.bits.ftq_idx, issue_slots[12].out_uop.ftq_idx \n connect issue_slots[10].in_uop.bits.is_mov, issue_slots[12].out_uop.is_mov \n connect issue_slots[10].in_uop.bits.is_rocc, issue_slots[12].out_uop.is_rocc \n connect issue_slots[10].in_uop.bits.is_sys_pc2epc, issue_slots[12].out_uop.is_sys_pc2epc \n connect issue_slots[10].in_uop.bits.is_eret, issue_slots[12].out_uop.is_eret \n connect issue_slots[10].in_uop.bits.is_amo, issue_slots[12].out_uop.is_amo \n connect issue_slots[10].in_uop.bits.is_sfence, issue_slots[12].out_uop.is_sfence \n connect issue_slots[10].in_uop.bits.is_fencei, issue_slots[12].out_uop.is_fencei \n connect issue_slots[10].in_uop.bits.is_fence, issue_slots[12].out_uop.is_fence \n connect issue_slots[10].in_uop.bits.is_sfb, issue_slots[12].out_uop.is_sfb \n connect issue_slots[10].in_uop.bits.br_type, issue_slots[12].out_uop.br_type \n connect issue_slots[10].in_uop.bits.br_tag, issue_slots[12].out_uop.br_tag \n connect issue_slots[10].in_uop.bits.br_mask, issue_slots[12].out_uop.br_mask \n connect issue_slots[10].in_uop.bits.dis_col_sel, issue_slots[12].out_uop.dis_col_sel \n connect issue_slots[10].in_uop.bits.iw_p3_bypass_hint, issue_slots[12].out_uop.iw_p3_bypass_hint \n connect issue_slots[10].in_uop.bits.iw_p2_bypass_hint, issue_slots[12].out_uop.iw_p2_bypass_hint \n connect issue_slots[10].in_uop.bits.iw_p1_bypass_hint, issue_slots[12].out_uop.iw_p1_bypass_hint \n connect issue_slots[10].in_uop.bits.iw_p2_speculative_child, issue_slots[12].out_uop.iw_p2_speculative_child \n connect issue_slots[10].in_uop.bits.iw_p1_speculative_child, issue_slots[12].out_uop.iw_p1_speculative_child \n connect issue_slots[10].in_uop.bits.iw_issued_partial_dgen, issue_slots[12].out_uop.iw_issued_partial_dgen \n connect issue_slots[10].in_uop.bits.iw_issued_partial_agen, issue_slots[12].out_uop.iw_issued_partial_agen \n connect issue_slots[10].in_uop.bits.iw_issued, issue_slots[12].out_uop.iw_issued \n connect issue_slots[10].in_uop.bits.fu_code[0], issue_slots[12].out_uop.fu_code[0] \n connect issue_slots[10].in_uop.bits.fu_code[1], issue_slots[12].out_uop.fu_code[1] \n connect issue_slots[10].in_uop.bits.fu_code[2], issue_slots[12].out_uop.fu_code[2] \n connect issue_slots[10].in_uop.bits.fu_code[3], issue_slots[12].out_uop.fu_code[3] \n connect issue_slots[10].in_uop.bits.fu_code[4], issue_slots[12].out_uop.fu_code[4] \n connect issue_slots[10].in_uop.bits.fu_code[5], issue_slots[12].out_uop.fu_code[5] \n connect issue_slots[10].in_uop.bits.fu_code[6], issue_slots[12].out_uop.fu_code[6] \n connect issue_slots[10].in_uop.bits.fu_code[7], issue_slots[12].out_uop.fu_code[7] \n connect issue_slots[10].in_uop.bits.fu_code[8], issue_slots[12].out_uop.fu_code[8] \n connect issue_slots[10].in_uop.bits.fu_code[9], issue_slots[12].out_uop.fu_code[9] \n connect issue_slots[10].in_uop.bits.iq_type[0], issue_slots[12].out_uop.iq_type[0] \n connect issue_slots[10].in_uop.bits.iq_type[1], issue_slots[12].out_uop.iq_type[1] \n connect issue_slots[10].in_uop.bits.iq_type[2], issue_slots[12].out_uop.iq_type[2] \n connect issue_slots[10].in_uop.bits.iq_type[3], issue_slots[12].out_uop.iq_type[3] \n connect issue_slots[10].in_uop.bits.debug_pc, issue_slots[12].out_uop.debug_pc \n connect issue_slots[10].in_uop.bits.is_rvc, issue_slots[12].out_uop.is_rvc \n connect issue_slots[10].in_uop.bits.debug_inst, issue_slots[12].out_uop.debug_inst \n connect issue_slots[10].in_uop.bits.inst, issue_slots[12].out_uop.inst \n node _issue_slots_10_clear_T = neq(shamts_oh[10], UInt<1>(0h0)) \n connect issue_slots[10].clear, _issue_slots_10_clear_T \n connect issue_slots[11].in_uop.valid, UInt<1>(0h0) \n connect issue_slots[11].in_uop.bits.debug_tsrc, issue_slots[12].out_uop.debug_tsrc \n connect issue_slots[11].in_uop.bits.debug_fsrc, issue_slots[12].out_uop.debug_fsrc \n connect issue_slots[11].in_uop.bits.bp_xcpt_if, issue_slots[12].out_uop.bp_xcpt_if \n connect issue_slots[11].in_uop.bits.bp_debug_if, issue_slots[12].out_uop.bp_debug_if \n connect issue_slots[11].in_uop.bits.xcpt_ma_if, issue_slots[12].out_uop.xcpt_ma_if \n connect issue_slots[11].in_uop.bits.xcpt_ae_if, issue_slots[12].out_uop.xcpt_ae_if \n connect issue_slots[11].in_uop.bits.xcpt_pf_if, issue_slots[12].out_uop.xcpt_pf_if \n connect issue_slots[11].in_uop.bits.fp_typ, issue_slots[12].out_uop.fp_typ \n connect issue_slots[11].in_uop.bits.fp_rm, issue_slots[12].out_uop.fp_rm \n connect issue_slots[11].in_uop.bits.fp_val, issue_slots[12].out_uop.fp_val \n connect issue_slots[11].in_uop.bits.fcn_op, issue_slots[12].out_uop.fcn_op \n connect issue_slots[11].in_uop.bits.fcn_dw, issue_slots[12].out_uop.fcn_dw \n connect issue_slots[11].in_uop.bits.frs3_en, issue_slots[12].out_uop.frs3_en \n connect issue_slots[11].in_uop.bits.lrs2_rtype, issue_slots[12].out_uop.lrs2_rtype \n connect issue_slots[11].in_uop.bits.lrs1_rtype, issue_slots[12].out_uop.lrs1_rtype \n connect issue_slots[11].in_uop.bits.dst_rtype, issue_slots[12].out_uop.dst_rtype \n connect issue_slots[11].in_uop.bits.lrs3, issue_slots[12].out_uop.lrs3 \n connect issue_slots[11].in_uop.bits.lrs2, issue_slots[12].out_uop.lrs2 \n connect issue_slots[11].in_uop.bits.lrs1, issue_slots[12].out_uop.lrs1 \n connect issue_slots[11].in_uop.bits.ldst, issue_slots[12].out_uop.ldst \n connect issue_slots[11].in_uop.bits.ldst_is_rs1, issue_slots[12].out_uop.ldst_is_rs1 \n connect issue_slots[11].in_uop.bits.csr_cmd, issue_slots[12].out_uop.csr_cmd \n connect issue_slots[11].in_uop.bits.flush_on_commit, issue_slots[12].out_uop.flush_on_commit \n connect issue_slots[11].in_uop.bits.is_unique, issue_slots[12].out_uop.is_unique \n connect issue_slots[11].in_uop.bits.uses_stq, issue_slots[12].out_uop.uses_stq \n connect issue_slots[11].in_uop.bits.uses_ldq, issue_slots[12].out_uop.uses_ldq \n connect issue_slots[11].in_uop.bits.mem_signed, issue_slots[12].out_uop.mem_signed \n connect issue_slots[11].in_uop.bits.mem_size, issue_slots[12].out_uop.mem_size \n connect issue_slots[11].in_uop.bits.mem_cmd, issue_slots[12].out_uop.mem_cmd \n connect issue_slots[11].in_uop.bits.exc_cause, issue_slots[12].out_uop.exc_cause \n connect issue_slots[11].in_uop.bits.exception, issue_slots[12].out_uop.exception \n connect issue_slots[11].in_uop.bits.stale_pdst, issue_slots[12].out_uop.stale_pdst \n connect issue_slots[11].in_uop.bits.ppred_busy, issue_slots[12].out_uop.ppred_busy \n connect issue_slots[11].in_uop.bits.prs3_busy, issue_slots[12].out_uop.prs3_busy \n connect issue_slots[11].in_uop.bits.prs2_busy, issue_slots[12].out_uop.prs2_busy \n connect issue_slots[11].in_uop.bits.prs1_busy, issue_slots[12].out_uop.prs1_busy \n connect issue_slots[11].in_uop.bits.ppred, issue_slots[12].out_uop.ppred \n connect issue_slots[11].in_uop.bits.prs3, issue_slots[12].out_uop.prs3 \n connect issue_slots[11].in_uop.bits.prs2, issue_slots[12].out_uop.prs2 \n connect issue_slots[11].in_uop.bits.prs1, issue_slots[12].out_uop.prs1 \n connect issue_slots[11].in_uop.bits.pdst, issue_slots[12].out_uop.pdst \n connect issue_slots[11].in_uop.bits.rxq_idx, issue_slots[12].out_uop.rxq_idx \n connect issue_slots[11].in_uop.bits.stq_idx, issue_slots[12].out_uop.stq_idx \n connect issue_slots[11].in_uop.bits.ldq_idx, issue_slots[12].out_uop.ldq_idx \n connect issue_slots[11].in_uop.bits.rob_idx, issue_slots[12].out_uop.rob_idx \n connect issue_slots[11].in_uop.bits.fp_ctrl.vec, issue_slots[12].out_uop.fp_ctrl.vec \n connect issue_slots[11].in_uop.bits.fp_ctrl.wflags, issue_slots[12].out_uop.fp_ctrl.wflags \n connect issue_slots[11].in_uop.bits.fp_ctrl.sqrt, issue_slots[12].out_uop.fp_ctrl.sqrt \n connect issue_slots[11].in_uop.bits.fp_ctrl.div, issue_slots[12].out_uop.fp_ctrl.div \n connect issue_slots[11].in_uop.bits.fp_ctrl.fma, issue_slots[12].out_uop.fp_ctrl.fma \n connect issue_slots[11].in_uop.bits.fp_ctrl.fastpipe, issue_slots[12].out_uop.fp_ctrl.fastpipe \n connect issue_slots[11].in_uop.bits.fp_ctrl.toint, issue_slots[12].out_uop.fp_ctrl.toint \n connect issue_slots[11].in_uop.bits.fp_ctrl.fromint, issue_slots[12].out_uop.fp_ctrl.fromint \n connect issue_slots[11].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[12].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[11].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[12].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[11].in_uop.bits.fp_ctrl.swap23, issue_slots[12].out_uop.fp_ctrl.swap23 \n connect issue_slots[11].in_uop.bits.fp_ctrl.swap12, issue_slots[12].out_uop.fp_ctrl.swap12 \n connect issue_slots[11].in_uop.bits.fp_ctrl.ren3, issue_slots[12].out_uop.fp_ctrl.ren3 \n connect issue_slots[11].in_uop.bits.fp_ctrl.ren2, issue_slots[12].out_uop.fp_ctrl.ren2 \n connect issue_slots[11].in_uop.bits.fp_ctrl.ren1, issue_slots[12].out_uop.fp_ctrl.ren1 \n connect issue_slots[11].in_uop.bits.fp_ctrl.wen, issue_slots[12].out_uop.fp_ctrl.wen \n connect issue_slots[11].in_uop.bits.fp_ctrl.ldst, issue_slots[12].out_uop.fp_ctrl.ldst \n connect issue_slots[11].in_uop.bits.op2_sel, issue_slots[12].out_uop.op2_sel \n connect issue_slots[11].in_uop.bits.op1_sel, issue_slots[12].out_uop.op1_sel \n connect issue_slots[11].in_uop.bits.imm_packed, issue_slots[12].out_uop.imm_packed \n connect issue_slots[11].in_uop.bits.pimm, issue_slots[12].out_uop.pimm \n connect issue_slots[11].in_uop.bits.imm_sel, issue_slots[12].out_uop.imm_sel \n connect issue_slots[11].in_uop.bits.imm_rename, issue_slots[12].out_uop.imm_rename \n connect issue_slots[11].in_uop.bits.taken, issue_slots[12].out_uop.taken \n connect issue_slots[11].in_uop.bits.pc_lob, issue_slots[12].out_uop.pc_lob \n connect issue_slots[11].in_uop.bits.edge_inst, issue_slots[12].out_uop.edge_inst \n connect issue_slots[11].in_uop.bits.ftq_idx, issue_slots[12].out_uop.ftq_idx \n connect issue_slots[11].in_uop.bits.is_mov, issue_slots[12].out_uop.is_mov \n connect issue_slots[11].in_uop.bits.is_rocc, issue_slots[12].out_uop.is_rocc \n connect issue_slots[11].in_uop.bits.is_sys_pc2epc, issue_slots[12].out_uop.is_sys_pc2epc \n connect issue_slots[11].in_uop.bits.is_eret, issue_slots[12].out_uop.is_eret \n connect issue_slots[11].in_uop.bits.is_amo, issue_slots[12].out_uop.is_amo \n connect issue_slots[11].in_uop.bits.is_sfence, issue_slots[12].out_uop.is_sfence \n connect issue_slots[11].in_uop.bits.is_fencei, issue_slots[12].out_uop.is_fencei \n connect issue_slots[11].in_uop.bits.is_fence, issue_slots[12].out_uop.is_fence \n connect issue_slots[11].in_uop.bits.is_sfb, issue_slots[12].out_uop.is_sfb \n connect issue_slots[11].in_uop.bits.br_type, issue_slots[12].out_uop.br_type \n connect issue_slots[11].in_uop.bits.br_tag, issue_slots[12].out_uop.br_tag \n connect issue_slots[11].in_uop.bits.br_mask, issue_slots[12].out_uop.br_mask \n connect issue_slots[11].in_uop.bits.dis_col_sel, issue_slots[12].out_uop.dis_col_sel \n connect issue_slots[11].in_uop.bits.iw_p3_bypass_hint, issue_slots[12].out_uop.iw_p3_bypass_hint \n connect issue_slots[11].in_uop.bits.iw_p2_bypass_hint, issue_slots[12].out_uop.iw_p2_bypass_hint \n connect issue_slots[11].in_uop.bits.iw_p1_bypass_hint, issue_slots[12].out_uop.iw_p1_bypass_hint \n connect issue_slots[11].in_uop.bits.iw_p2_speculative_child, issue_slots[12].out_uop.iw_p2_speculative_child \n connect issue_slots[11].in_uop.bits.iw_p1_speculative_child, issue_slots[12].out_uop.iw_p1_speculative_child \n connect issue_slots[11].in_uop.bits.iw_issued_partial_dgen, issue_slots[12].out_uop.iw_issued_partial_dgen \n connect issue_slots[11].in_uop.bits.iw_issued_partial_agen, issue_slots[12].out_uop.iw_issued_partial_agen \n connect issue_slots[11].in_uop.bits.iw_issued, issue_slots[12].out_uop.iw_issued \n connect issue_slots[11].in_uop.bits.fu_code[0], issue_slots[12].out_uop.fu_code[0] \n connect issue_slots[11].in_uop.bits.fu_code[1], issue_slots[12].out_uop.fu_code[1] \n connect issue_slots[11].in_uop.bits.fu_code[2], issue_slots[12].out_uop.fu_code[2] \n connect issue_slots[11].in_uop.bits.fu_code[3], issue_slots[12].out_uop.fu_code[3] \n connect issue_slots[11].in_uop.bits.fu_code[4], issue_slots[12].out_uop.fu_code[4] \n connect issue_slots[11].in_uop.bits.fu_code[5], issue_slots[12].out_uop.fu_code[5] \n connect issue_slots[11].in_uop.bits.fu_code[6], issue_slots[12].out_uop.fu_code[6] \n connect issue_slots[11].in_uop.bits.fu_code[7], issue_slots[12].out_uop.fu_code[7] \n connect issue_slots[11].in_uop.bits.fu_code[8], issue_slots[12].out_uop.fu_code[8] \n connect issue_slots[11].in_uop.bits.fu_code[9], issue_slots[12].out_uop.fu_code[9] \n connect issue_slots[11].in_uop.bits.iq_type[0], issue_slots[12].out_uop.iq_type[0] \n connect issue_slots[11].in_uop.bits.iq_type[1], issue_slots[12].out_uop.iq_type[1] \n connect issue_slots[11].in_uop.bits.iq_type[2], issue_slots[12].out_uop.iq_type[2] \n connect issue_slots[11].in_uop.bits.iq_type[3], issue_slots[12].out_uop.iq_type[3] \n connect issue_slots[11].in_uop.bits.debug_pc, issue_slots[12].out_uop.debug_pc \n connect issue_slots[11].in_uop.bits.is_rvc, issue_slots[12].out_uop.is_rvc \n connect issue_slots[11].in_uop.bits.debug_inst, issue_slots[12].out_uop.debug_inst \n connect issue_slots[11].in_uop.bits.inst, issue_slots[12].out_uop.inst \n node _T_184 = eq(shamts_oh[12], UInt<1>(0h1)) \n when _T_184 : \n connect issue_slots[11].in_uop.valid, issue_slots[12].will_be_valid \n connect issue_slots[11].in_uop.bits.debug_tsrc, issue_slots[12].out_uop.debug_tsrc \n connect issue_slots[11].in_uop.bits.debug_fsrc, issue_slots[12].out_uop.debug_fsrc \n connect issue_slots[11].in_uop.bits.bp_xcpt_if, issue_slots[12].out_uop.bp_xcpt_if \n connect issue_slots[11].in_uop.bits.bp_debug_if, issue_slots[12].out_uop.bp_debug_if \n connect issue_slots[11].in_uop.bits.xcpt_ma_if, issue_slots[12].out_uop.xcpt_ma_if \n connect issue_slots[11].in_uop.bits.xcpt_ae_if, issue_slots[12].out_uop.xcpt_ae_if \n connect issue_slots[11].in_uop.bits.xcpt_pf_if, issue_slots[12].out_uop.xcpt_pf_if \n connect issue_slots[11].in_uop.bits.fp_typ, issue_slots[12].out_uop.fp_typ \n connect issue_slots[11].in_uop.bits.fp_rm, issue_slots[12].out_uop.fp_rm \n connect issue_slots[11].in_uop.bits.fp_val, issue_slots[12].out_uop.fp_val \n connect issue_slots[11].in_uop.bits.fcn_op, issue_slots[12].out_uop.fcn_op \n connect issue_slots[11].in_uop.bits.fcn_dw, issue_slots[12].out_uop.fcn_dw \n connect issue_slots[11].in_uop.bits.frs3_en, issue_slots[12].out_uop.frs3_en \n connect issue_slots[11].in_uop.bits.lrs2_rtype, issue_slots[12].out_uop.lrs2_rtype \n connect issue_slots[11].in_uop.bits.lrs1_rtype, issue_slots[12].out_uop.lrs1_rtype \n connect issue_slots[11].in_uop.bits.dst_rtype, issue_slots[12].out_uop.dst_rtype \n connect issue_slots[11].in_uop.bits.lrs3, issue_slots[12].out_uop.lrs3 \n connect issue_slots[11].in_uop.bits.lrs2, issue_slots[12].out_uop.lrs2 \n connect issue_slots[11].in_uop.bits.lrs1, issue_slots[12].out_uop.lrs1 \n connect issue_slots[11].in_uop.bits.ldst, issue_slots[12].out_uop.ldst \n connect issue_slots[11].in_uop.bits.ldst_is_rs1, issue_slots[12].out_uop.ldst_is_rs1 \n connect issue_slots[11].in_uop.bits.csr_cmd, issue_slots[12].out_uop.csr_cmd \n connect issue_slots[11].in_uop.bits.flush_on_commit, issue_slots[12].out_uop.flush_on_commit \n connect issue_slots[11].in_uop.bits.is_unique, issue_slots[12].out_uop.is_unique \n connect issue_slots[11].in_uop.bits.uses_stq, issue_slots[12].out_uop.uses_stq \n connect issue_slots[11].in_uop.bits.uses_ldq, issue_slots[12].out_uop.uses_ldq \n connect issue_slots[11].in_uop.bits.mem_signed, issue_slots[12].out_uop.mem_signed \n connect issue_slots[11].in_uop.bits.mem_size, issue_slots[12].out_uop.mem_size \n connect issue_slots[11].in_uop.bits.mem_cmd, issue_slots[12].out_uop.mem_cmd \n connect issue_slots[11].in_uop.bits.exc_cause, issue_slots[12].out_uop.exc_cause \n connect issue_slots[11].in_uop.bits.exception, issue_slots[12].out_uop.exception \n connect issue_slots[11].in_uop.bits.stale_pdst, issue_slots[12].out_uop.stale_pdst \n connect issue_slots[11].in_uop.bits.ppred_busy, issue_slots[12].out_uop.ppred_busy \n connect issue_slots[11].in_uop.bits.prs3_busy, issue_slots[12].out_uop.prs3_busy \n connect issue_slots[11].in_uop.bits.prs2_busy, issue_slots[12].out_uop.prs2_busy \n connect issue_slots[11].in_uop.bits.prs1_busy, issue_slots[12].out_uop.prs1_busy \n connect issue_slots[11].in_uop.bits.ppred, issue_slots[12].out_uop.ppred \n connect issue_slots[11].in_uop.bits.prs3, issue_slots[12].out_uop.prs3 \n connect issue_slots[11].in_uop.bits.prs2, issue_slots[12].out_uop.prs2 \n connect issue_slots[11].in_uop.bits.prs1, issue_slots[12].out_uop.prs1 \n connect issue_slots[11].in_uop.bits.pdst, issue_slots[12].out_uop.pdst \n connect issue_slots[11].in_uop.bits.rxq_idx, issue_slots[12].out_uop.rxq_idx \n connect issue_slots[11].in_uop.bits.stq_idx, issue_slots[12].out_uop.stq_idx \n connect issue_slots[11].in_uop.bits.ldq_idx, issue_slots[12].out_uop.ldq_idx \n connect issue_slots[11].in_uop.bits.rob_idx, issue_slots[12].out_uop.rob_idx \n connect issue_slots[11].in_uop.bits.fp_ctrl.vec, issue_slots[12].out_uop.fp_ctrl.vec \n connect issue_slots[11].in_uop.bits.fp_ctrl.wflags, issue_slots[12].out_uop.fp_ctrl.wflags \n connect issue_slots[11].in_uop.bits.fp_ctrl.sqrt, issue_slots[12].out_uop.fp_ctrl.sqrt \n connect issue_slots[11].in_uop.bits.fp_ctrl.div, issue_slots[12].out_uop.fp_ctrl.div \n connect issue_slots[11].in_uop.bits.fp_ctrl.fma, issue_slots[12].out_uop.fp_ctrl.fma \n connect issue_slots[11].in_uop.bits.fp_ctrl.fastpipe, issue_slots[12].out_uop.fp_ctrl.fastpipe \n connect issue_slots[11].in_uop.bits.fp_ctrl.toint, issue_slots[12].out_uop.fp_ctrl.toint \n connect issue_slots[11].in_uop.bits.fp_ctrl.fromint, issue_slots[12].out_uop.fp_ctrl.fromint \n connect issue_slots[11].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[12].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[11].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[12].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[11].in_uop.bits.fp_ctrl.swap23, issue_slots[12].out_uop.fp_ctrl.swap23 \n connect issue_slots[11].in_uop.bits.fp_ctrl.swap12, issue_slots[12].out_uop.fp_ctrl.swap12 \n connect issue_slots[11].in_uop.bits.fp_ctrl.ren3, issue_slots[12].out_uop.fp_ctrl.ren3 \n connect issue_slots[11].in_uop.bits.fp_ctrl.ren2, issue_slots[12].out_uop.fp_ctrl.ren2 \n connect issue_slots[11].in_uop.bits.fp_ctrl.ren1, issue_slots[12].out_uop.fp_ctrl.ren1 \n connect issue_slots[11].in_uop.bits.fp_ctrl.wen, issue_slots[12].out_uop.fp_ctrl.wen \n connect issue_slots[11].in_uop.bits.fp_ctrl.ldst, issue_slots[12].out_uop.fp_ctrl.ldst \n connect issue_slots[11].in_uop.bits.op2_sel, issue_slots[12].out_uop.op2_sel \n connect issue_slots[11].in_uop.bits.op1_sel, issue_slots[12].out_uop.op1_sel \n connect issue_slots[11].in_uop.bits.imm_packed, issue_slots[12].out_uop.imm_packed \n connect issue_slots[11].in_uop.bits.pimm, issue_slots[12].out_uop.pimm \n connect issue_slots[11].in_uop.bits.imm_sel, issue_slots[12].out_uop.imm_sel \n connect issue_slots[11].in_uop.bits.imm_rename, issue_slots[12].out_uop.imm_rename \n connect issue_slots[11].in_uop.bits.taken, issue_slots[12].out_uop.taken \n connect issue_slots[11].in_uop.bits.pc_lob, issue_slots[12].out_uop.pc_lob \n connect issue_slots[11].in_uop.bits.edge_inst, issue_slots[12].out_uop.edge_inst \n connect issue_slots[11].in_uop.bits.ftq_idx, issue_slots[12].out_uop.ftq_idx \n connect issue_slots[11].in_uop.bits.is_mov, issue_slots[12].out_uop.is_mov \n connect issue_slots[11].in_uop.bits.is_rocc, issue_slots[12].out_uop.is_rocc \n connect issue_slots[11].in_uop.bits.is_sys_pc2epc, issue_slots[12].out_uop.is_sys_pc2epc \n connect issue_slots[11].in_uop.bits.is_eret, issue_slots[12].out_uop.is_eret \n connect issue_slots[11].in_uop.bits.is_amo, issue_slots[12].out_uop.is_amo \n connect issue_slots[11].in_uop.bits.is_sfence, issue_slots[12].out_uop.is_sfence \n connect issue_slots[11].in_uop.bits.is_fencei, issue_slots[12].out_uop.is_fencei \n connect issue_slots[11].in_uop.bits.is_fence, issue_slots[12].out_uop.is_fence \n connect issue_slots[11].in_uop.bits.is_sfb, issue_slots[12].out_uop.is_sfb \n connect issue_slots[11].in_uop.bits.br_type, issue_slots[12].out_uop.br_type \n connect issue_slots[11].in_uop.bits.br_tag, issue_slots[12].out_uop.br_tag \n connect issue_slots[11].in_uop.bits.br_mask, issue_slots[12].out_uop.br_mask \n connect issue_slots[11].in_uop.bits.dis_col_sel, issue_slots[12].out_uop.dis_col_sel \n connect issue_slots[11].in_uop.bits.iw_p3_bypass_hint, issue_slots[12].out_uop.iw_p3_bypass_hint \n connect issue_slots[11].in_uop.bits.iw_p2_bypass_hint, issue_slots[12].out_uop.iw_p2_bypass_hint \n connect issue_slots[11].in_uop.bits.iw_p1_bypass_hint, issue_slots[12].out_uop.iw_p1_bypass_hint \n connect issue_slots[11].in_uop.bits.iw_p2_speculative_child, issue_slots[12].out_uop.iw_p2_speculative_child \n connect issue_slots[11].in_uop.bits.iw_p1_speculative_child, issue_slots[12].out_uop.iw_p1_speculative_child \n connect issue_slots[11].in_uop.bits.iw_issued_partial_dgen, issue_slots[12].out_uop.iw_issued_partial_dgen \n connect issue_slots[11].in_uop.bits.iw_issued_partial_agen, issue_slots[12].out_uop.iw_issued_partial_agen \n connect issue_slots[11].in_uop.bits.iw_issued, issue_slots[12].out_uop.iw_issued \n connect issue_slots[11].in_uop.bits.fu_code[0], issue_slots[12].out_uop.fu_code[0] \n connect issue_slots[11].in_uop.bits.fu_code[1], issue_slots[12].out_uop.fu_code[1] \n connect issue_slots[11].in_uop.bits.fu_code[2], issue_slots[12].out_uop.fu_code[2] \n connect issue_slots[11].in_uop.bits.fu_code[3], issue_slots[12].out_uop.fu_code[3] \n connect issue_slots[11].in_uop.bits.fu_code[4], issue_slots[12].out_uop.fu_code[4] \n connect issue_slots[11].in_uop.bits.fu_code[5], issue_slots[12].out_uop.fu_code[5] \n connect issue_slots[11].in_uop.bits.fu_code[6], issue_slots[12].out_uop.fu_code[6] \n connect issue_slots[11].in_uop.bits.fu_code[7], issue_slots[12].out_uop.fu_code[7] \n connect issue_slots[11].in_uop.bits.fu_code[8], issue_slots[12].out_uop.fu_code[8] \n connect issue_slots[11].in_uop.bits.fu_code[9], issue_slots[12].out_uop.fu_code[9] \n connect issue_slots[11].in_uop.bits.iq_type[0], issue_slots[12].out_uop.iq_type[0] \n connect issue_slots[11].in_uop.bits.iq_type[1], issue_slots[12].out_uop.iq_type[1] \n connect issue_slots[11].in_uop.bits.iq_type[2], issue_slots[12].out_uop.iq_type[2] \n connect issue_slots[11].in_uop.bits.iq_type[3], issue_slots[12].out_uop.iq_type[3] \n connect issue_slots[11].in_uop.bits.debug_pc, issue_slots[12].out_uop.debug_pc \n connect issue_slots[11].in_uop.bits.is_rvc, issue_slots[12].out_uop.is_rvc \n connect issue_slots[11].in_uop.bits.debug_inst, issue_slots[12].out_uop.debug_inst \n connect issue_slots[11].in_uop.bits.inst, issue_slots[12].out_uop.inst \n node _T_185 = eq(shamts_oh[13], UInt<2>(0h2)) \n when _T_185 : \n connect issue_slots[11].in_uop.valid, issue_slots[13].will_be_valid \n connect issue_slots[11].in_uop.bits.debug_tsrc, issue_slots[13].out_uop.debug_tsrc \n connect issue_slots[11].in_uop.bits.debug_fsrc, issue_slots[13].out_uop.debug_fsrc \n connect issue_slots[11].in_uop.bits.bp_xcpt_if, issue_slots[13].out_uop.bp_xcpt_if \n connect issue_slots[11].in_uop.bits.bp_debug_if, issue_slots[13].out_uop.bp_debug_if \n connect issue_slots[11].in_uop.bits.xcpt_ma_if, issue_slots[13].out_uop.xcpt_ma_if \n connect issue_slots[11].in_uop.bits.xcpt_ae_if, issue_slots[13].out_uop.xcpt_ae_if \n connect issue_slots[11].in_uop.bits.xcpt_pf_if, issue_slots[13].out_uop.xcpt_pf_if \n connect issue_slots[11].in_uop.bits.fp_typ, issue_slots[13].out_uop.fp_typ \n connect issue_slots[11].in_uop.bits.fp_rm, issue_slots[13].out_uop.fp_rm \n connect issue_slots[11].in_uop.bits.fp_val, issue_slots[13].out_uop.fp_val \n connect issue_slots[11].in_uop.bits.fcn_op, issue_slots[13].out_uop.fcn_op \n connect issue_slots[11].in_uop.bits.fcn_dw, issue_slots[13].out_uop.fcn_dw \n connect issue_slots[11].in_uop.bits.frs3_en, issue_slots[13].out_uop.frs3_en \n connect issue_slots[11].in_uop.bits.lrs2_rtype, issue_slots[13].out_uop.lrs2_rtype \n connect issue_slots[11].in_uop.bits.lrs1_rtype, issue_slots[13].out_uop.lrs1_rtype \n connect issue_slots[11].in_uop.bits.dst_rtype, issue_slots[13].out_uop.dst_rtype \n connect issue_slots[11].in_uop.bits.lrs3, issue_slots[13].out_uop.lrs3 \n connect issue_slots[11].in_uop.bits.lrs2, issue_slots[13].out_uop.lrs2 \n connect issue_slots[11].in_uop.bits.lrs1, issue_slots[13].out_uop.lrs1 \n connect issue_slots[11].in_uop.bits.ldst, issue_slots[13].out_uop.ldst \n connect issue_slots[11].in_uop.bits.ldst_is_rs1, issue_slots[13].out_uop.ldst_is_rs1 \n connect issue_slots[11].in_uop.bits.csr_cmd, issue_slots[13].out_uop.csr_cmd \n connect issue_slots[11].in_uop.bits.flush_on_commit, issue_slots[13].out_uop.flush_on_commit \n connect issue_slots[11].in_uop.bits.is_unique, issue_slots[13].out_uop.is_unique \n connect issue_slots[11].in_uop.bits.uses_stq, issue_slots[13].out_uop.uses_stq \n connect issue_slots[11].in_uop.bits.uses_ldq, issue_slots[13].out_uop.uses_ldq \n connect issue_slots[11].in_uop.bits.mem_signed, issue_slots[13].out_uop.mem_signed \n connect issue_slots[11].in_uop.bits.mem_size, issue_slots[13].out_uop.mem_size \n connect issue_slots[11].in_uop.bits.mem_cmd, issue_slots[13].out_uop.mem_cmd \n connect issue_slots[11].in_uop.bits.exc_cause, issue_slots[13].out_uop.exc_cause \n connect issue_slots[11].in_uop.bits.exception, issue_slots[13].out_uop.exception \n connect issue_slots[11].in_uop.bits.stale_pdst, issue_slots[13].out_uop.stale_pdst \n connect issue_slots[11].in_uop.bits.ppred_busy, issue_slots[13].out_uop.ppred_busy \n connect issue_slots[11].in_uop.bits.prs3_busy, issue_slots[13].out_uop.prs3_busy \n connect issue_slots[11].in_uop.bits.prs2_busy, issue_slots[13].out_uop.prs2_busy \n connect issue_slots[11].in_uop.bits.prs1_busy, issue_slots[13].out_uop.prs1_busy \n connect issue_slots[11].in_uop.bits.ppred, issue_slots[13].out_uop.ppred \n connect issue_slots[11].in_uop.bits.prs3, issue_slots[13].out_uop.prs3 \n connect issue_slots[11].in_uop.bits.prs2, issue_slots[13].out_uop.prs2 \n connect issue_slots[11].in_uop.bits.prs1, issue_slots[13].out_uop.prs1 \n connect issue_slots[11].in_uop.bits.pdst, issue_slots[13].out_uop.pdst \n connect issue_slots[11].in_uop.bits.rxq_idx, issue_slots[13].out_uop.rxq_idx \n connect issue_slots[11].in_uop.bits.stq_idx, issue_slots[13].out_uop.stq_idx \n connect issue_slots[11].in_uop.bits.ldq_idx, issue_slots[13].out_uop.ldq_idx \n connect issue_slots[11].in_uop.bits.rob_idx, issue_slots[13].out_uop.rob_idx \n connect issue_slots[11].in_uop.bits.fp_ctrl.vec, issue_slots[13].out_uop.fp_ctrl.vec \n connect issue_slots[11].in_uop.bits.fp_ctrl.wflags, issue_slots[13].out_uop.fp_ctrl.wflags \n connect issue_slots[11].in_uop.bits.fp_ctrl.sqrt, issue_slots[13].out_uop.fp_ctrl.sqrt \n connect issue_slots[11].in_uop.bits.fp_ctrl.div, issue_slots[13].out_uop.fp_ctrl.div \n connect issue_slots[11].in_uop.bits.fp_ctrl.fma, issue_slots[13].out_uop.fp_ctrl.fma \n connect issue_slots[11].in_uop.bits.fp_ctrl.fastpipe, issue_slots[13].out_uop.fp_ctrl.fastpipe \n connect issue_slots[11].in_uop.bits.fp_ctrl.toint, issue_slots[13].out_uop.fp_ctrl.toint \n connect issue_slots[11].in_uop.bits.fp_ctrl.fromint, issue_slots[13].out_uop.fp_ctrl.fromint \n connect issue_slots[11].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[13].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[11].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[13].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[11].in_uop.bits.fp_ctrl.swap23, issue_slots[13].out_uop.fp_ctrl.swap23 \n connect issue_slots[11].in_uop.bits.fp_ctrl.swap12, issue_slots[13].out_uop.fp_ctrl.swap12 \n connect issue_slots[11].in_uop.bits.fp_ctrl.ren3, issue_slots[13].out_uop.fp_ctrl.ren3 \n connect issue_slots[11].in_uop.bits.fp_ctrl.ren2, issue_slots[13].out_uop.fp_ctrl.ren2 \n connect issue_slots[11].in_uop.bits.fp_ctrl.ren1, issue_slots[13].out_uop.fp_ctrl.ren1 \n connect issue_slots[11].in_uop.bits.fp_ctrl.wen, issue_slots[13].out_uop.fp_ctrl.wen \n connect issue_slots[11].in_uop.bits.fp_ctrl.ldst, issue_slots[13].out_uop.fp_ctrl.ldst \n connect issue_slots[11].in_uop.bits.op2_sel, issue_slots[13].out_uop.op2_sel \n connect issue_slots[11].in_uop.bits.op1_sel, issue_slots[13].out_uop.op1_sel \n connect issue_slots[11].in_uop.bits.imm_packed, issue_slots[13].out_uop.imm_packed \n connect issue_slots[11].in_uop.bits.pimm, issue_slots[13].out_uop.pimm \n connect issue_slots[11].in_uop.bits.imm_sel, issue_slots[13].out_uop.imm_sel \n connect issue_slots[11].in_uop.bits.imm_rename, issue_slots[13].out_uop.imm_rename \n connect issue_slots[11].in_uop.bits.taken, issue_slots[13].out_uop.taken \n connect issue_slots[11].in_uop.bits.pc_lob, issue_slots[13].out_uop.pc_lob \n connect issue_slots[11].in_uop.bits.edge_inst, issue_slots[13].out_uop.edge_inst \n connect issue_slots[11].in_uop.bits.ftq_idx, issue_slots[13].out_uop.ftq_idx \n connect issue_slots[11].in_uop.bits.is_mov, issue_slots[13].out_uop.is_mov \n connect issue_slots[11].in_uop.bits.is_rocc, issue_slots[13].out_uop.is_rocc \n connect issue_slots[11].in_uop.bits.is_sys_pc2epc, issue_slots[13].out_uop.is_sys_pc2epc \n connect issue_slots[11].in_uop.bits.is_eret, issue_slots[13].out_uop.is_eret \n connect issue_slots[11].in_uop.bits.is_amo, issue_slots[13].out_uop.is_amo \n connect issue_slots[11].in_uop.bits.is_sfence, issue_slots[13].out_uop.is_sfence \n connect issue_slots[11].in_uop.bits.is_fencei, issue_slots[13].out_uop.is_fencei \n connect issue_slots[11].in_uop.bits.is_fence, issue_slots[13].out_uop.is_fence \n connect issue_slots[11].in_uop.bits.is_sfb, issue_slots[13].out_uop.is_sfb \n connect issue_slots[11].in_uop.bits.br_type, issue_slots[13].out_uop.br_type \n connect issue_slots[11].in_uop.bits.br_tag, issue_slots[13].out_uop.br_tag \n connect issue_slots[11].in_uop.bits.br_mask, issue_slots[13].out_uop.br_mask \n connect issue_slots[11].in_uop.bits.dis_col_sel, issue_slots[13].out_uop.dis_col_sel \n connect issue_slots[11].in_uop.bits.iw_p3_bypass_hint, issue_slots[13].out_uop.iw_p3_bypass_hint \n connect issue_slots[11].in_uop.bits.iw_p2_bypass_hint, issue_slots[13].out_uop.iw_p2_bypass_hint \n connect issue_slots[11].in_uop.bits.iw_p1_bypass_hint, issue_slots[13].out_uop.iw_p1_bypass_hint \n connect issue_slots[11].in_uop.bits.iw_p2_speculative_child, issue_slots[13].out_uop.iw_p2_speculative_child \n connect issue_slots[11].in_uop.bits.iw_p1_speculative_child, issue_slots[13].out_uop.iw_p1_speculative_child \n connect issue_slots[11].in_uop.bits.iw_issued_partial_dgen, issue_slots[13].out_uop.iw_issued_partial_dgen \n connect issue_slots[11].in_uop.bits.iw_issued_partial_agen, issue_slots[13].out_uop.iw_issued_partial_agen \n connect issue_slots[11].in_uop.bits.iw_issued, issue_slots[13].out_uop.iw_issued \n connect issue_slots[11].in_uop.bits.fu_code[0], issue_slots[13].out_uop.fu_code[0] \n connect issue_slots[11].in_uop.bits.fu_code[1], issue_slots[13].out_uop.fu_code[1] \n connect issue_slots[11].in_uop.bits.fu_code[2], issue_slots[13].out_uop.fu_code[2] \n connect issue_slots[11].in_uop.bits.fu_code[3], issue_slots[13].out_uop.fu_code[3] \n connect issue_slots[11].in_uop.bits.fu_code[4], issue_slots[13].out_uop.fu_code[4] \n connect issue_slots[11].in_uop.bits.fu_code[5], issue_slots[13].out_uop.fu_code[5] \n connect issue_slots[11].in_uop.bits.fu_code[6], issue_slots[13].out_uop.fu_code[6] \n connect issue_slots[11].in_uop.bits.fu_code[7], issue_slots[13].out_uop.fu_code[7] \n connect issue_slots[11].in_uop.bits.fu_code[8], issue_slots[13].out_uop.fu_code[8] \n connect issue_slots[11].in_uop.bits.fu_code[9], issue_slots[13].out_uop.fu_code[9] \n connect issue_slots[11].in_uop.bits.iq_type[0], issue_slots[13].out_uop.iq_type[0] \n connect issue_slots[11].in_uop.bits.iq_type[1], issue_slots[13].out_uop.iq_type[1] \n connect issue_slots[11].in_uop.bits.iq_type[2], issue_slots[13].out_uop.iq_type[2] \n connect issue_slots[11].in_uop.bits.iq_type[3], issue_slots[13].out_uop.iq_type[3] \n connect issue_slots[11].in_uop.bits.debug_pc, issue_slots[13].out_uop.debug_pc \n connect issue_slots[11].in_uop.bits.is_rvc, issue_slots[13].out_uop.is_rvc \n connect issue_slots[11].in_uop.bits.debug_inst, issue_slots[13].out_uop.debug_inst \n connect issue_slots[11].in_uop.bits.inst, issue_slots[13].out_uop.inst \n node _issue_slots_11_clear_T = neq(shamts_oh[11], UInt<1>(0h0)) \n connect issue_slots[11].clear, _issue_slots_11_clear_T \n connect issue_slots[12].in_uop.valid, UInt<1>(0h0) \n connect issue_slots[12].in_uop.bits.debug_tsrc, issue_slots[13].out_uop.debug_tsrc \n connect issue_slots[12].in_uop.bits.debug_fsrc, issue_slots[13].out_uop.debug_fsrc \n connect issue_slots[12].in_uop.bits.bp_xcpt_if, issue_slots[13].out_uop.bp_xcpt_if \n connect issue_slots[12].in_uop.bits.bp_debug_if, issue_slots[13].out_uop.bp_debug_if \n connect issue_slots[12].in_uop.bits.xcpt_ma_if, issue_slots[13].out_uop.xcpt_ma_if \n connect issue_slots[12].in_uop.bits.xcpt_ae_if, issue_slots[13].out_uop.xcpt_ae_if \n connect issue_slots[12].in_uop.bits.xcpt_pf_if, issue_slots[13].out_uop.xcpt_pf_if \n connect issue_slots[12].in_uop.bits.fp_typ, issue_slots[13].out_uop.fp_typ \n connect issue_slots[12].in_uop.bits.fp_rm, issue_slots[13].out_uop.fp_rm \n connect issue_slots[12].in_uop.bits.fp_val, issue_slots[13].out_uop.fp_val \n connect issue_slots[12].in_uop.bits.fcn_op, issue_slots[13].out_uop.fcn_op \n connect issue_slots[12].in_uop.bits.fcn_dw, issue_slots[13].out_uop.fcn_dw \n connect issue_slots[12].in_uop.bits.frs3_en, issue_slots[13].out_uop.frs3_en \n connect issue_slots[12].in_uop.bits.lrs2_rtype, issue_slots[13].out_uop.lrs2_rtype \n connect issue_slots[12].in_uop.bits.lrs1_rtype, issue_slots[13].out_uop.lrs1_rtype \n connect issue_slots[12].in_uop.bits.dst_rtype, issue_slots[13].out_uop.dst_rtype \n connect issue_slots[12].in_uop.bits.lrs3, issue_slots[13].out_uop.lrs3 \n connect issue_slots[12].in_uop.bits.lrs2, issue_slots[13].out_uop.lrs2 \n connect issue_slots[12].in_uop.bits.lrs1, issue_slots[13].out_uop.lrs1 \n connect issue_slots[12].in_uop.bits.ldst, issue_slots[13].out_uop.ldst \n connect issue_slots[12].in_uop.bits.ldst_is_rs1, issue_slots[13].out_uop.ldst_is_rs1 \n connect issue_slots[12].in_uop.bits.csr_cmd, issue_slots[13].out_uop.csr_cmd \n connect issue_slots[12].in_uop.bits.flush_on_commit, issue_slots[13].out_uop.flush_on_commit \n connect issue_slots[12].in_uop.bits.is_unique, issue_slots[13].out_uop.is_unique \n connect issue_slots[12].in_uop.bits.uses_stq, issue_slots[13].out_uop.uses_stq \n connect issue_slots[12].in_uop.bits.uses_ldq, issue_slots[13].out_uop.uses_ldq \n connect issue_slots[12].in_uop.bits.mem_signed, issue_slots[13].out_uop.mem_signed \n connect issue_slots[12].in_uop.bits.mem_size, issue_slots[13].out_uop.mem_size \n connect issue_slots[12].in_uop.bits.mem_cmd, issue_slots[13].out_uop.mem_cmd \n connect issue_slots[12].in_uop.bits.exc_cause, issue_slots[13].out_uop.exc_cause \n connect issue_slots[12].in_uop.bits.exception, issue_slots[13].out_uop.exception \n connect issue_slots[12].in_uop.bits.stale_pdst, issue_slots[13].out_uop.stale_pdst \n connect issue_slots[12].in_uop.bits.ppred_busy, issue_slots[13].out_uop.ppred_busy \n connect issue_slots[12].in_uop.bits.prs3_busy, issue_slots[13].out_uop.prs3_busy \n connect issue_slots[12].in_uop.bits.prs2_busy, issue_slots[13].out_uop.prs2_busy \n connect issue_slots[12].in_uop.bits.prs1_busy, issue_slots[13].out_uop.prs1_busy \n connect issue_slots[12].in_uop.bits.ppred, issue_slots[13].out_uop.ppred \n connect issue_slots[12].in_uop.bits.prs3, issue_slots[13].out_uop.prs3 \n connect issue_slots[12].in_uop.bits.prs2, issue_slots[13].out_uop.prs2 \n connect issue_slots[12].in_uop.bits.prs1, issue_slots[13].out_uop.prs1 \n connect issue_slots[12].in_uop.bits.pdst, issue_slots[13].out_uop.pdst \n connect issue_slots[12].in_uop.bits.rxq_idx, issue_slots[13].out_uop.rxq_idx \n connect issue_slots[12].in_uop.bits.stq_idx, issue_slots[13].out_uop.stq_idx \n connect issue_slots[12].in_uop.bits.ldq_idx, issue_slots[13].out_uop.ldq_idx \n connect issue_slots[12].in_uop.bits.rob_idx, issue_slots[13].out_uop.rob_idx \n connect issue_slots[12].in_uop.bits.fp_ctrl.vec, issue_slots[13].out_uop.fp_ctrl.vec \n connect issue_slots[12].in_uop.bits.fp_ctrl.wflags, issue_slots[13].out_uop.fp_ctrl.wflags \n connect issue_slots[12].in_uop.bits.fp_ctrl.sqrt, issue_slots[13].out_uop.fp_ctrl.sqrt \n connect issue_slots[12].in_uop.bits.fp_ctrl.div, issue_slots[13].out_uop.fp_ctrl.div \n connect issue_slots[12].in_uop.bits.fp_ctrl.fma, issue_slots[13].out_uop.fp_ctrl.fma \n connect issue_slots[12].in_uop.bits.fp_ctrl.fastpipe, issue_slots[13].out_uop.fp_ctrl.fastpipe \n connect issue_slots[12].in_uop.bits.fp_ctrl.toint, issue_slots[13].out_uop.fp_ctrl.toint \n connect issue_slots[12].in_uop.bits.fp_ctrl.fromint, issue_slots[13].out_uop.fp_ctrl.fromint \n connect issue_slots[12].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[13].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[12].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[13].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[12].in_uop.bits.fp_ctrl.swap23, issue_slots[13].out_uop.fp_ctrl.swap23 \n connect issue_slots[12].in_uop.bits.fp_ctrl.swap12, issue_slots[13].out_uop.fp_ctrl.swap12 \n connect issue_slots[12].in_uop.bits.fp_ctrl.ren3, issue_slots[13].out_uop.fp_ctrl.ren3 \n connect issue_slots[12].in_uop.bits.fp_ctrl.ren2, issue_slots[13].out_uop.fp_ctrl.ren2 \n connect issue_slots[12].in_uop.bits.fp_ctrl.ren1, issue_slots[13].out_uop.fp_ctrl.ren1 \n connect issue_slots[12].in_uop.bits.fp_ctrl.wen, issue_slots[13].out_uop.fp_ctrl.wen \n connect issue_slots[12].in_uop.bits.fp_ctrl.ldst, issue_slots[13].out_uop.fp_ctrl.ldst \n connect issue_slots[12].in_uop.bits.op2_sel, issue_slots[13].out_uop.op2_sel \n connect issue_slots[12].in_uop.bits.op1_sel, issue_slots[13].out_uop.op1_sel \n connect issue_slots[12].in_uop.bits.imm_packed, issue_slots[13].out_uop.imm_packed \n connect issue_slots[12].in_uop.bits.pimm, issue_slots[13].out_uop.pimm \n connect issue_slots[12].in_uop.bits.imm_sel, issue_slots[13].out_uop.imm_sel \n connect issue_slots[12].in_uop.bits.imm_rename, issue_slots[13].out_uop.imm_rename \n connect issue_slots[12].in_uop.bits.taken, issue_slots[13].out_uop.taken \n connect issue_slots[12].in_uop.bits.pc_lob, issue_slots[13].out_uop.pc_lob \n connect issue_slots[12].in_uop.bits.edge_inst, issue_slots[13].out_uop.edge_inst \n connect issue_slots[12].in_uop.bits.ftq_idx, issue_slots[13].out_uop.ftq_idx \n connect issue_slots[12].in_uop.bits.is_mov, issue_slots[13].out_uop.is_mov \n connect issue_slots[12].in_uop.bits.is_rocc, issue_slots[13].out_uop.is_rocc \n connect issue_slots[12].in_uop.bits.is_sys_pc2epc, issue_slots[13].out_uop.is_sys_pc2epc \n connect issue_slots[12].in_uop.bits.is_eret, issue_slots[13].out_uop.is_eret \n connect issue_slots[12].in_uop.bits.is_amo, issue_slots[13].out_uop.is_amo \n connect issue_slots[12].in_uop.bits.is_sfence, issue_slots[13].out_uop.is_sfence \n connect issue_slots[12].in_uop.bits.is_fencei, issue_slots[13].out_uop.is_fencei \n connect issue_slots[12].in_uop.bits.is_fence, issue_slots[13].out_uop.is_fence \n connect issue_slots[12].in_uop.bits.is_sfb, issue_slots[13].out_uop.is_sfb \n connect issue_slots[12].in_uop.bits.br_type, issue_slots[13].out_uop.br_type \n connect issue_slots[12].in_uop.bits.br_tag, issue_slots[13].out_uop.br_tag \n connect issue_slots[12].in_uop.bits.br_mask, issue_slots[13].out_uop.br_mask \n connect issue_slots[12].in_uop.bits.dis_col_sel, issue_slots[13].out_uop.dis_col_sel \n connect issue_slots[12].in_uop.bits.iw_p3_bypass_hint, issue_slots[13].out_uop.iw_p3_bypass_hint \n connect issue_slots[12].in_uop.bits.iw_p2_bypass_hint, issue_slots[13].out_uop.iw_p2_bypass_hint \n connect issue_slots[12].in_uop.bits.iw_p1_bypass_hint, issue_slots[13].out_uop.iw_p1_bypass_hint \n connect issue_slots[12].in_uop.bits.iw_p2_speculative_child, issue_slots[13].out_uop.iw_p2_speculative_child \n connect issue_slots[12].in_uop.bits.iw_p1_speculative_child, issue_slots[13].out_uop.iw_p1_speculative_child \n connect issue_slots[12].in_uop.bits.iw_issued_partial_dgen, issue_slots[13].out_uop.iw_issued_partial_dgen \n connect issue_slots[12].in_uop.bits.iw_issued_partial_agen, issue_slots[13].out_uop.iw_issued_partial_agen \n connect issue_slots[12].in_uop.bits.iw_issued, issue_slots[13].out_uop.iw_issued \n connect issue_slots[12].in_uop.bits.fu_code[0], issue_slots[13].out_uop.fu_code[0] \n connect issue_slots[12].in_uop.bits.fu_code[1], issue_slots[13].out_uop.fu_code[1] \n connect issue_slots[12].in_uop.bits.fu_code[2], issue_slots[13].out_uop.fu_code[2] \n connect issue_slots[12].in_uop.bits.fu_code[3], issue_slots[13].out_uop.fu_code[3] \n connect issue_slots[12].in_uop.bits.fu_code[4], issue_slots[13].out_uop.fu_code[4] \n connect issue_slots[12].in_uop.bits.fu_code[5], issue_slots[13].out_uop.fu_code[5] \n connect issue_slots[12].in_uop.bits.fu_code[6], issue_slots[13].out_uop.fu_code[6] \n connect issue_slots[12].in_uop.bits.fu_code[7], issue_slots[13].out_uop.fu_code[7] \n connect issue_slots[12].in_uop.bits.fu_code[8], issue_slots[13].out_uop.fu_code[8] \n connect issue_slots[12].in_uop.bits.fu_code[9], issue_slots[13].out_uop.fu_code[9] \n connect issue_slots[12].in_uop.bits.iq_type[0], issue_slots[13].out_uop.iq_type[0] \n connect issue_slots[12].in_uop.bits.iq_type[1], issue_slots[13].out_uop.iq_type[1] \n connect issue_slots[12].in_uop.bits.iq_type[2], issue_slots[13].out_uop.iq_type[2] \n connect issue_slots[12].in_uop.bits.iq_type[3], issue_slots[13].out_uop.iq_type[3] \n connect issue_slots[12].in_uop.bits.debug_pc, issue_slots[13].out_uop.debug_pc \n connect issue_slots[12].in_uop.bits.is_rvc, issue_slots[13].out_uop.is_rvc \n connect issue_slots[12].in_uop.bits.debug_inst, issue_slots[13].out_uop.debug_inst \n connect issue_slots[12].in_uop.bits.inst, issue_slots[13].out_uop.inst \n node _T_186 = eq(shamts_oh[13], UInt<1>(0h1)) \n when _T_186 : \n connect issue_slots[12].in_uop.valid, issue_slots[13].will_be_valid \n connect issue_slots[12].in_uop.bits.debug_tsrc, issue_slots[13].out_uop.debug_tsrc \n connect issue_slots[12].in_uop.bits.debug_fsrc, issue_slots[13].out_uop.debug_fsrc \n connect issue_slots[12].in_uop.bits.bp_xcpt_if, issue_slots[13].out_uop.bp_xcpt_if \n connect issue_slots[12].in_uop.bits.bp_debug_if, issue_slots[13].out_uop.bp_debug_if \n connect issue_slots[12].in_uop.bits.xcpt_ma_if, issue_slots[13].out_uop.xcpt_ma_if \n connect issue_slots[12].in_uop.bits.xcpt_ae_if, issue_slots[13].out_uop.xcpt_ae_if \n connect issue_slots[12].in_uop.bits.xcpt_pf_if, issue_slots[13].out_uop.xcpt_pf_if \n connect issue_slots[12].in_uop.bits.fp_typ, issue_slots[13].out_uop.fp_typ \n connect issue_slots[12].in_uop.bits.fp_rm, issue_slots[13].out_uop.fp_rm \n connect issue_slots[12].in_uop.bits.fp_val, issue_slots[13].out_uop.fp_val \n connect issue_slots[12].in_uop.bits.fcn_op, issue_slots[13].out_uop.fcn_op \n connect issue_slots[12].in_uop.bits.fcn_dw, issue_slots[13].out_uop.fcn_dw \n connect issue_slots[12].in_uop.bits.frs3_en, issue_slots[13].out_uop.frs3_en \n connect issue_slots[12].in_uop.bits.lrs2_rtype, issue_slots[13].out_uop.lrs2_rtype \n connect issue_slots[12].in_uop.bits.lrs1_rtype, issue_slots[13].out_uop.lrs1_rtype \n connect issue_slots[12].in_uop.bits.dst_rtype, issue_slots[13].out_uop.dst_rtype \n connect issue_slots[12].in_uop.bits.lrs3, issue_slots[13].out_uop.lrs3 \n connect issue_slots[12].in_uop.bits.lrs2, issue_slots[13].out_uop.lrs2 \n connect issue_slots[12].in_uop.bits.lrs1, issue_slots[13].out_uop.lrs1 \n connect issue_slots[12].in_uop.bits.ldst, issue_slots[13].out_uop.ldst \n connect issue_slots[12].in_uop.bits.ldst_is_rs1, issue_slots[13].out_uop.ldst_is_rs1 \n connect issue_slots[12].in_uop.bits.csr_cmd, issue_slots[13].out_uop.csr_cmd \n connect issue_slots[12].in_uop.bits.flush_on_commit, issue_slots[13].out_uop.flush_on_commit \n connect issue_slots[12].in_uop.bits.is_unique, issue_slots[13].out_uop.is_unique \n connect issue_slots[12].in_uop.bits.uses_stq, issue_slots[13].out_uop.uses_stq \n connect issue_slots[12].in_uop.bits.uses_ldq, issue_slots[13].out_uop.uses_ldq \n connect issue_slots[12].in_uop.bits.mem_signed, issue_slots[13].out_uop.mem_signed \n connect issue_slots[12].in_uop.bits.mem_size, issue_slots[13].out_uop.mem_size \n connect issue_slots[12].in_uop.bits.mem_cmd, issue_slots[13].out_uop.mem_cmd \n connect issue_slots[12].in_uop.bits.exc_cause, issue_slots[13].out_uop.exc_cause \n connect issue_slots[12].in_uop.bits.exception, issue_slots[13].out_uop.exception \n connect issue_slots[12].in_uop.bits.stale_pdst, issue_slots[13].out_uop.stale_pdst \n connect issue_slots[12].in_uop.bits.ppred_busy, issue_slots[13].out_uop.ppred_busy \n connect issue_slots[12].in_uop.bits.prs3_busy, issue_slots[13].out_uop.prs3_busy \n connect issue_slots[12].in_uop.bits.prs2_busy, issue_slots[13].out_uop.prs2_busy \n connect issue_slots[12].in_uop.bits.prs1_busy, issue_slots[13].out_uop.prs1_busy \n connect issue_slots[12].in_uop.bits.ppred, issue_slots[13].out_uop.ppred \n connect issue_slots[12].in_uop.bits.prs3, issue_slots[13].out_uop.prs3 \n connect issue_slots[12].in_uop.bits.prs2, issue_slots[13].out_uop.prs2 \n connect issue_slots[12].in_uop.bits.prs1, issue_slots[13].out_uop.prs1 \n connect issue_slots[12].in_uop.bits.pdst, issue_slots[13].out_uop.pdst \n connect issue_slots[12].in_uop.bits.rxq_idx, issue_slots[13].out_uop.rxq_idx \n connect issue_slots[12].in_uop.bits.stq_idx, issue_slots[13].out_uop.stq_idx \n connect issue_slots[12].in_uop.bits.ldq_idx, issue_slots[13].out_uop.ldq_idx \n connect issue_slots[12].in_uop.bits.rob_idx, issue_slots[13].out_uop.rob_idx \n connect issue_slots[12].in_uop.bits.fp_ctrl.vec, issue_slots[13].out_uop.fp_ctrl.vec \n connect issue_slots[12].in_uop.bits.fp_ctrl.wflags, issue_slots[13].out_uop.fp_ctrl.wflags \n connect issue_slots[12].in_uop.bits.fp_ctrl.sqrt, issue_slots[13].out_uop.fp_ctrl.sqrt \n connect issue_slots[12].in_uop.bits.fp_ctrl.div, issue_slots[13].out_uop.fp_ctrl.div \n connect issue_slots[12].in_uop.bits.fp_ctrl.fma, issue_slots[13].out_uop.fp_ctrl.fma \n connect issue_slots[12].in_uop.bits.fp_ctrl.fastpipe, issue_slots[13].out_uop.fp_ctrl.fastpipe \n connect issue_slots[12].in_uop.bits.fp_ctrl.toint, issue_slots[13].out_uop.fp_ctrl.toint \n connect issue_slots[12].in_uop.bits.fp_ctrl.fromint, issue_slots[13].out_uop.fp_ctrl.fromint \n connect issue_slots[12].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[13].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[12].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[13].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[12].in_uop.bits.fp_ctrl.swap23, issue_slots[13].out_uop.fp_ctrl.swap23 \n connect issue_slots[12].in_uop.bits.fp_ctrl.swap12, issue_slots[13].out_uop.fp_ctrl.swap12 \n connect issue_slots[12].in_uop.bits.fp_ctrl.ren3, issue_slots[13].out_uop.fp_ctrl.ren3 \n connect issue_slots[12].in_uop.bits.fp_ctrl.ren2, issue_slots[13].out_uop.fp_ctrl.ren2 \n connect issue_slots[12].in_uop.bits.fp_ctrl.ren1, issue_slots[13].out_uop.fp_ctrl.ren1 \n connect issue_slots[12].in_uop.bits.fp_ctrl.wen, issue_slots[13].out_uop.fp_ctrl.wen \n connect issue_slots[12].in_uop.bits.fp_ctrl.ldst, issue_slots[13].out_uop.fp_ctrl.ldst \n connect issue_slots[12].in_uop.bits.op2_sel, issue_slots[13].out_uop.op2_sel \n connect issue_slots[12].in_uop.bits.op1_sel, issue_slots[13].out_uop.op1_sel \n connect issue_slots[12].in_uop.bits.imm_packed, issue_slots[13].out_uop.imm_packed \n connect issue_slots[12].in_uop.bits.pimm, issue_slots[13].out_uop.pimm \n connect issue_slots[12].in_uop.bits.imm_sel, issue_slots[13].out_uop.imm_sel \n connect issue_slots[12].in_uop.bits.imm_rename, issue_slots[13].out_uop.imm_rename \n connect issue_slots[12].in_uop.bits.taken, issue_slots[13].out_uop.taken \n connect issue_slots[12].in_uop.bits.pc_lob, issue_slots[13].out_uop.pc_lob \n connect issue_slots[12].in_uop.bits.edge_inst, issue_slots[13].out_uop.edge_inst \n connect issue_slots[12].in_uop.bits.ftq_idx, issue_slots[13].out_uop.ftq_idx \n connect issue_slots[12].in_uop.bits.is_mov, issue_slots[13].out_uop.is_mov \n connect issue_slots[12].in_uop.bits.is_rocc, issue_slots[13].out_uop.is_rocc \n connect issue_slots[12].in_uop.bits.is_sys_pc2epc, issue_slots[13].out_uop.is_sys_pc2epc \n connect issue_slots[12].in_uop.bits.is_eret, issue_slots[13].out_uop.is_eret \n connect issue_slots[12].in_uop.bits.is_amo, issue_slots[13].out_uop.is_amo \n connect issue_slots[12].in_uop.bits.is_sfence, issue_slots[13].out_uop.is_sfence \n connect issue_slots[12].in_uop.bits.is_fencei, issue_slots[13].out_uop.is_fencei \n connect issue_slots[12].in_uop.bits.is_fence, issue_slots[13].out_uop.is_fence \n connect issue_slots[12].in_uop.bits.is_sfb, issue_slots[13].out_uop.is_sfb \n connect issue_slots[12].in_uop.bits.br_type, issue_slots[13].out_uop.br_type \n connect issue_slots[12].in_uop.bits.br_tag, issue_slots[13].out_uop.br_tag \n connect issue_slots[12].in_uop.bits.br_mask, issue_slots[13].out_uop.br_mask \n connect issue_slots[12].in_uop.bits.dis_col_sel, issue_slots[13].out_uop.dis_col_sel \n connect issue_slots[12].in_uop.bits.iw_p3_bypass_hint, issue_slots[13].out_uop.iw_p3_bypass_hint \n connect issue_slots[12].in_uop.bits.iw_p2_bypass_hint, issue_slots[13].out_uop.iw_p2_bypass_hint \n connect issue_slots[12].in_uop.bits.iw_p1_bypass_hint, issue_slots[13].out_uop.iw_p1_bypass_hint \n connect issue_slots[12].in_uop.bits.iw_p2_speculative_child, issue_slots[13].out_uop.iw_p2_speculative_child \n connect issue_slots[12].in_uop.bits.iw_p1_speculative_child, issue_slots[13].out_uop.iw_p1_speculative_child \n connect issue_slots[12].in_uop.bits.iw_issued_partial_dgen, issue_slots[13].out_uop.iw_issued_partial_dgen \n connect issue_slots[12].in_uop.bits.iw_issued_partial_agen, issue_slots[13].out_uop.iw_issued_partial_agen \n connect issue_slots[12].in_uop.bits.iw_issued, issue_slots[13].out_uop.iw_issued \n connect issue_slots[12].in_uop.bits.fu_code[0], issue_slots[13].out_uop.fu_code[0] \n connect issue_slots[12].in_uop.bits.fu_code[1], issue_slots[13].out_uop.fu_code[1] \n connect issue_slots[12].in_uop.bits.fu_code[2], issue_slots[13].out_uop.fu_code[2] \n connect issue_slots[12].in_uop.bits.fu_code[3], issue_slots[13].out_uop.fu_code[3] \n connect issue_slots[12].in_uop.bits.fu_code[4], issue_slots[13].out_uop.fu_code[4] \n connect issue_slots[12].in_uop.bits.fu_code[5], issue_slots[13].out_uop.fu_code[5] \n connect issue_slots[12].in_uop.bits.fu_code[6], issue_slots[13].out_uop.fu_code[6] \n connect issue_slots[12].in_uop.bits.fu_code[7], issue_slots[13].out_uop.fu_code[7] \n connect issue_slots[12].in_uop.bits.fu_code[8], issue_slots[13].out_uop.fu_code[8] \n connect issue_slots[12].in_uop.bits.fu_code[9], issue_slots[13].out_uop.fu_code[9] \n connect issue_slots[12].in_uop.bits.iq_type[0], issue_slots[13].out_uop.iq_type[0] \n connect issue_slots[12].in_uop.bits.iq_type[1], issue_slots[13].out_uop.iq_type[1] \n connect issue_slots[12].in_uop.bits.iq_type[2], issue_slots[13].out_uop.iq_type[2] \n connect issue_slots[12].in_uop.bits.iq_type[3], issue_slots[13].out_uop.iq_type[3] \n connect issue_slots[12].in_uop.bits.debug_pc, issue_slots[13].out_uop.debug_pc \n connect issue_slots[12].in_uop.bits.is_rvc, issue_slots[13].out_uop.is_rvc \n connect issue_slots[12].in_uop.bits.debug_inst, issue_slots[13].out_uop.debug_inst \n connect issue_slots[12].in_uop.bits.inst, issue_slots[13].out_uop.inst \n node _T_187 = eq(shamts_oh[14], UInt<2>(0h2)) \n when _T_187 : \n connect issue_slots[12].in_uop.valid, issue_slots[14].will_be_valid \n connect issue_slots[12].in_uop.bits.debug_tsrc, issue_slots[14].out_uop.debug_tsrc \n connect issue_slots[12].in_uop.bits.debug_fsrc, issue_slots[14].out_uop.debug_fsrc \n connect issue_slots[12].in_uop.bits.bp_xcpt_if, issue_slots[14].out_uop.bp_xcpt_if \n connect issue_slots[12].in_uop.bits.bp_debug_if, issue_slots[14].out_uop.bp_debug_if \n connect issue_slots[12].in_uop.bits.xcpt_ma_if, issue_slots[14].out_uop.xcpt_ma_if \n connect issue_slots[12].in_uop.bits.xcpt_ae_if, issue_slots[14].out_uop.xcpt_ae_if \n connect issue_slots[12].in_uop.bits.xcpt_pf_if, issue_slots[14].out_uop.xcpt_pf_if \n connect issue_slots[12].in_uop.bits.fp_typ, issue_slots[14].out_uop.fp_typ \n connect issue_slots[12].in_uop.bits.fp_rm, issue_slots[14].out_uop.fp_rm \n connect issue_slots[12].in_uop.bits.fp_val, issue_slots[14].out_uop.fp_val \n connect issue_slots[12].in_uop.bits.fcn_op, issue_slots[14].out_uop.fcn_op \n connect issue_slots[12].in_uop.bits.fcn_dw, issue_slots[14].out_uop.fcn_dw \n connect issue_slots[12].in_uop.bits.frs3_en, issue_slots[14].out_uop.frs3_en \n connect issue_slots[12].in_uop.bits.lrs2_rtype, issue_slots[14].out_uop.lrs2_rtype \n connect issue_slots[12].in_uop.bits.lrs1_rtype, issue_slots[14].out_uop.lrs1_rtype \n connect issue_slots[12].in_uop.bits.dst_rtype, issue_slots[14].out_uop.dst_rtype \n connect issue_slots[12].in_uop.bits.lrs3, issue_slots[14].out_uop.lrs3 \n connect issue_slots[12].in_uop.bits.lrs2, issue_slots[14].out_uop.lrs2 \n connect issue_slots[12].in_uop.bits.lrs1, issue_slots[14].out_uop.lrs1 \n connect issue_slots[12].in_uop.bits.ldst, issue_slots[14].out_uop.ldst \n connect issue_slots[12].in_uop.bits.ldst_is_rs1, issue_slots[14].out_uop.ldst_is_rs1 \n connect issue_slots[12].in_uop.bits.csr_cmd, issue_slots[14].out_uop.csr_cmd \n connect issue_slots[12].in_uop.bits.flush_on_commit, issue_slots[14].out_uop.flush_on_commit \n connect issue_slots[12].in_uop.bits.is_unique, issue_slots[14].out_uop.is_unique \n connect issue_slots[12].in_uop.bits.uses_stq, issue_slots[14].out_uop.uses_stq \n connect issue_slots[12].in_uop.bits.uses_ldq, issue_slots[14].out_uop.uses_ldq \n connect issue_slots[12].in_uop.bits.mem_signed, issue_slots[14].out_uop.mem_signed \n connect issue_slots[12].in_uop.bits.mem_size, issue_slots[14].out_uop.mem_size \n connect issue_slots[12].in_uop.bits.mem_cmd, issue_slots[14].out_uop.mem_cmd \n connect issue_slots[12].in_uop.bits.exc_cause, issue_slots[14].out_uop.exc_cause \n connect issue_slots[12].in_uop.bits.exception, issue_slots[14].out_uop.exception \n connect issue_slots[12].in_uop.bits.stale_pdst, issue_slots[14].out_uop.stale_pdst \n connect issue_slots[12].in_uop.bits.ppred_busy, issue_slots[14].out_uop.ppred_busy \n connect issue_slots[12].in_uop.bits.prs3_busy, issue_slots[14].out_uop.prs3_busy \n connect issue_slots[12].in_uop.bits.prs2_busy, issue_slots[14].out_uop.prs2_busy \n connect issue_slots[12].in_uop.bits.prs1_busy, issue_slots[14].out_uop.prs1_busy \n connect issue_slots[12].in_uop.bits.ppred, issue_slots[14].out_uop.ppred \n connect issue_slots[12].in_uop.bits.prs3, issue_slots[14].out_uop.prs3 \n connect issue_slots[12].in_uop.bits.prs2, issue_slots[14].out_uop.prs2 \n connect issue_slots[12].in_uop.bits.prs1, issue_slots[14].out_uop.prs1 \n connect issue_slots[12].in_uop.bits.pdst, issue_slots[14].out_uop.pdst \n connect issue_slots[12].in_uop.bits.rxq_idx, issue_slots[14].out_uop.rxq_idx \n connect issue_slots[12].in_uop.bits.stq_idx, issue_slots[14].out_uop.stq_idx \n connect issue_slots[12].in_uop.bits.ldq_idx, issue_slots[14].out_uop.ldq_idx \n connect issue_slots[12].in_uop.bits.rob_idx, issue_slots[14].out_uop.rob_idx \n connect issue_slots[12].in_uop.bits.fp_ctrl.vec, issue_slots[14].out_uop.fp_ctrl.vec \n connect issue_slots[12].in_uop.bits.fp_ctrl.wflags, issue_slots[14].out_uop.fp_ctrl.wflags \n connect issue_slots[12].in_uop.bits.fp_ctrl.sqrt, issue_slots[14].out_uop.fp_ctrl.sqrt \n connect issue_slots[12].in_uop.bits.fp_ctrl.div, issue_slots[14].out_uop.fp_ctrl.div \n connect issue_slots[12].in_uop.bits.fp_ctrl.fma, issue_slots[14].out_uop.fp_ctrl.fma \n connect issue_slots[12].in_uop.bits.fp_ctrl.fastpipe, issue_slots[14].out_uop.fp_ctrl.fastpipe \n connect issue_slots[12].in_uop.bits.fp_ctrl.toint, issue_slots[14].out_uop.fp_ctrl.toint \n connect issue_slots[12].in_uop.bits.fp_ctrl.fromint, issue_slots[14].out_uop.fp_ctrl.fromint \n connect issue_slots[12].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[14].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[12].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[14].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[12].in_uop.bits.fp_ctrl.swap23, issue_slots[14].out_uop.fp_ctrl.swap23 \n connect issue_slots[12].in_uop.bits.fp_ctrl.swap12, issue_slots[14].out_uop.fp_ctrl.swap12 \n connect issue_slots[12].in_uop.bits.fp_ctrl.ren3, issue_slots[14].out_uop.fp_ctrl.ren3 \n connect issue_slots[12].in_uop.bits.fp_ctrl.ren2, issue_slots[14].out_uop.fp_ctrl.ren2 \n connect issue_slots[12].in_uop.bits.fp_ctrl.ren1, issue_slots[14].out_uop.fp_ctrl.ren1 \n connect issue_slots[12].in_uop.bits.fp_ctrl.wen, issue_slots[14].out_uop.fp_ctrl.wen \n connect issue_slots[12].in_uop.bits.fp_ctrl.ldst, issue_slots[14].out_uop.fp_ctrl.ldst \n connect issue_slots[12].in_uop.bits.op2_sel, issue_slots[14].out_uop.op2_sel \n connect issue_slots[12].in_uop.bits.op1_sel, issue_slots[14].out_uop.op1_sel \n connect issue_slots[12].in_uop.bits.imm_packed, issue_slots[14].out_uop.imm_packed \n connect issue_slots[12].in_uop.bits.pimm, issue_slots[14].out_uop.pimm \n connect issue_slots[12].in_uop.bits.imm_sel, issue_slots[14].out_uop.imm_sel \n connect issue_slots[12].in_uop.bits.imm_rename, issue_slots[14].out_uop.imm_rename \n connect issue_slots[12].in_uop.bits.taken, issue_slots[14].out_uop.taken \n connect issue_slots[12].in_uop.bits.pc_lob, issue_slots[14].out_uop.pc_lob \n connect issue_slots[12].in_uop.bits.edge_inst, issue_slots[14].out_uop.edge_inst \n connect issue_slots[12].in_uop.bits.ftq_idx, issue_slots[14].out_uop.ftq_idx \n connect issue_slots[12].in_uop.bits.is_mov, issue_slots[14].out_uop.is_mov \n connect issue_slots[12].in_uop.bits.is_rocc, issue_slots[14].out_uop.is_rocc \n connect issue_slots[12].in_uop.bits.is_sys_pc2epc, issue_slots[14].out_uop.is_sys_pc2epc \n connect issue_slots[12].in_uop.bits.is_eret, issue_slots[14].out_uop.is_eret \n connect issue_slots[12].in_uop.bits.is_amo, issue_slots[14].out_uop.is_amo \n connect issue_slots[12].in_uop.bits.is_sfence, issue_slots[14].out_uop.is_sfence \n connect issue_slots[12].in_uop.bits.is_fencei, issue_slots[14].out_uop.is_fencei \n connect issue_slots[12].in_uop.bits.is_fence, issue_slots[14].out_uop.is_fence \n connect issue_slots[12].in_uop.bits.is_sfb, issue_slots[14].out_uop.is_sfb \n connect issue_slots[12].in_uop.bits.br_type, issue_slots[14].out_uop.br_type \n connect issue_slots[12].in_uop.bits.br_tag, issue_slots[14].out_uop.br_tag \n connect issue_slots[12].in_uop.bits.br_mask, issue_slots[14].out_uop.br_mask \n connect issue_slots[12].in_uop.bits.dis_col_sel, issue_slots[14].out_uop.dis_col_sel \n connect issue_slots[12].in_uop.bits.iw_p3_bypass_hint, issue_slots[14].out_uop.iw_p3_bypass_hint \n connect issue_slots[12].in_uop.bits.iw_p2_bypass_hint, issue_slots[14].out_uop.iw_p2_bypass_hint \n connect issue_slots[12].in_uop.bits.iw_p1_bypass_hint, issue_slots[14].out_uop.iw_p1_bypass_hint \n connect issue_slots[12].in_uop.bits.iw_p2_speculative_child, issue_slots[14].out_uop.iw_p2_speculative_child \n connect issue_slots[12].in_uop.bits.iw_p1_speculative_child, issue_slots[14].out_uop.iw_p1_speculative_child \n connect issue_slots[12].in_uop.bits.iw_issued_partial_dgen, issue_slots[14].out_uop.iw_issued_partial_dgen \n connect issue_slots[12].in_uop.bits.iw_issued_partial_agen, issue_slots[14].out_uop.iw_issued_partial_agen \n connect issue_slots[12].in_uop.bits.iw_issued, issue_slots[14].out_uop.iw_issued \n connect issue_slots[12].in_uop.bits.fu_code[0], issue_slots[14].out_uop.fu_code[0] \n connect issue_slots[12].in_uop.bits.fu_code[1], issue_slots[14].out_uop.fu_code[1] \n connect issue_slots[12].in_uop.bits.fu_code[2], issue_slots[14].out_uop.fu_code[2] \n connect issue_slots[12].in_uop.bits.fu_code[3], issue_slots[14].out_uop.fu_code[3] \n connect issue_slots[12].in_uop.bits.fu_code[4], issue_slots[14].out_uop.fu_code[4] \n connect issue_slots[12].in_uop.bits.fu_code[5], issue_slots[14].out_uop.fu_code[5] \n connect issue_slots[12].in_uop.bits.fu_code[6], issue_slots[14].out_uop.fu_code[6] \n connect issue_slots[12].in_uop.bits.fu_code[7], issue_slots[14].out_uop.fu_code[7] \n connect issue_slots[12].in_uop.bits.fu_code[8], issue_slots[14].out_uop.fu_code[8] \n connect issue_slots[12].in_uop.bits.fu_code[9], issue_slots[14].out_uop.fu_code[9] \n connect issue_slots[12].in_uop.bits.iq_type[0], issue_slots[14].out_uop.iq_type[0] \n connect issue_slots[12].in_uop.bits.iq_type[1], issue_slots[14].out_uop.iq_type[1] \n connect issue_slots[12].in_uop.bits.iq_type[2], issue_slots[14].out_uop.iq_type[2] \n connect issue_slots[12].in_uop.bits.iq_type[3], issue_slots[14].out_uop.iq_type[3] \n connect issue_slots[12].in_uop.bits.debug_pc, issue_slots[14].out_uop.debug_pc \n connect issue_slots[12].in_uop.bits.is_rvc, issue_slots[14].out_uop.is_rvc \n connect issue_slots[12].in_uop.bits.debug_inst, issue_slots[14].out_uop.debug_inst \n connect issue_slots[12].in_uop.bits.inst, issue_slots[14].out_uop.inst \n node _issue_slots_12_clear_T = neq(shamts_oh[12], UInt<1>(0h0)) \n connect issue_slots[12].clear, _issue_slots_12_clear_T \n connect issue_slots[13].in_uop.valid, UInt<1>(0h0) \n connect issue_slots[13].in_uop.bits.debug_tsrc, issue_slots[14].out_uop.debug_tsrc \n connect issue_slots[13].in_uop.bits.debug_fsrc, issue_slots[14].out_uop.debug_fsrc \n connect issue_slots[13].in_uop.bits.bp_xcpt_if, issue_slots[14].out_uop.bp_xcpt_if \n connect issue_slots[13].in_uop.bits.bp_debug_if, issue_slots[14].out_uop.bp_debug_if \n connect issue_slots[13].in_uop.bits.xcpt_ma_if, issue_slots[14].out_uop.xcpt_ma_if \n connect issue_slots[13].in_uop.bits.xcpt_ae_if, issue_slots[14].out_uop.xcpt_ae_if \n connect issue_slots[13].in_uop.bits.xcpt_pf_if, issue_slots[14].out_uop.xcpt_pf_if \n connect issue_slots[13].in_uop.bits.fp_typ, issue_slots[14].out_uop.fp_typ \n connect issue_slots[13].in_uop.bits.fp_rm, issue_slots[14].out_uop.fp_rm \n connect issue_slots[13].in_uop.bits.fp_val, issue_slots[14].out_uop.fp_val \n connect issue_slots[13].in_uop.bits.fcn_op, issue_slots[14].out_uop.fcn_op \n connect issue_slots[13].in_uop.bits.fcn_dw, issue_slots[14].out_uop.fcn_dw \n connect issue_slots[13].in_uop.bits.frs3_en, issue_slots[14].out_uop.frs3_en \n connect issue_slots[13].in_uop.bits.lrs2_rtype, issue_slots[14].out_uop.lrs2_rtype \n connect issue_slots[13].in_uop.bits.lrs1_rtype, issue_slots[14].out_uop.lrs1_rtype \n connect issue_slots[13].in_uop.bits.dst_rtype, issue_slots[14].out_uop.dst_rtype \n connect issue_slots[13].in_uop.bits.lrs3, issue_slots[14].out_uop.lrs3 \n connect issue_slots[13].in_uop.bits.lrs2, issue_slots[14].out_uop.lrs2 \n connect issue_slots[13].in_uop.bits.lrs1, issue_slots[14].out_uop.lrs1 \n connect issue_slots[13].in_uop.bits.ldst, issue_slots[14].out_uop.ldst \n connect issue_slots[13].in_uop.bits.ldst_is_rs1, issue_slots[14].out_uop.ldst_is_rs1 \n connect issue_slots[13].in_uop.bits.csr_cmd, issue_slots[14].out_uop.csr_cmd \n connect issue_slots[13].in_uop.bits.flush_on_commit, issue_slots[14].out_uop.flush_on_commit \n connect issue_slots[13].in_uop.bits.is_unique, issue_slots[14].out_uop.is_unique \n connect issue_slots[13].in_uop.bits.uses_stq, issue_slots[14].out_uop.uses_stq \n connect issue_slots[13].in_uop.bits.uses_ldq, issue_slots[14].out_uop.uses_ldq \n connect issue_slots[13].in_uop.bits.mem_signed, issue_slots[14].out_uop.mem_signed \n connect issue_slots[13].in_uop.bits.mem_size, issue_slots[14].out_uop.mem_size \n connect issue_slots[13].in_uop.bits.mem_cmd, issue_slots[14].out_uop.mem_cmd \n connect issue_slots[13].in_uop.bits.exc_cause, issue_slots[14].out_uop.exc_cause \n connect issue_slots[13].in_uop.bits.exception, issue_slots[14].out_uop.exception \n connect issue_slots[13].in_uop.bits.stale_pdst, issue_slots[14].out_uop.stale_pdst \n connect issue_slots[13].in_uop.bits.ppred_busy, issue_slots[14].out_uop.ppred_busy \n connect issue_slots[13].in_uop.bits.prs3_busy, issue_slots[14].out_uop.prs3_busy \n connect issue_slots[13].in_uop.bits.prs2_busy, issue_slots[14].out_uop.prs2_busy \n connect issue_slots[13].in_uop.bits.prs1_busy, issue_slots[14].out_uop.prs1_busy \n connect issue_slots[13].in_uop.bits.ppred, issue_slots[14].out_uop.ppred \n connect issue_slots[13].in_uop.bits.prs3, issue_slots[14].out_uop.prs3 \n connect issue_slots[13].in_uop.bits.prs2, issue_slots[14].out_uop.prs2 \n connect issue_slots[13].in_uop.bits.prs1, issue_slots[14].out_uop.prs1 \n connect issue_slots[13].in_uop.bits.pdst, issue_slots[14].out_uop.pdst \n connect issue_slots[13].in_uop.bits.rxq_idx, issue_slots[14].out_uop.rxq_idx \n connect issue_slots[13].in_uop.bits.stq_idx, issue_slots[14].out_uop.stq_idx \n connect issue_slots[13].in_uop.bits.ldq_idx, issue_slots[14].out_uop.ldq_idx \n connect issue_slots[13].in_uop.bits.rob_idx, issue_slots[14].out_uop.rob_idx \n connect issue_slots[13].in_uop.bits.fp_ctrl.vec, issue_slots[14].out_uop.fp_ctrl.vec \n connect issue_slots[13].in_uop.bits.fp_ctrl.wflags, issue_slots[14].out_uop.fp_ctrl.wflags \n connect issue_slots[13].in_uop.bits.fp_ctrl.sqrt, issue_slots[14].out_uop.fp_ctrl.sqrt \n connect issue_slots[13].in_uop.bits.fp_ctrl.div, issue_slots[14].out_uop.fp_ctrl.div \n connect issue_slots[13].in_uop.bits.fp_ctrl.fma, issue_slots[14].out_uop.fp_ctrl.fma \n connect issue_slots[13].in_uop.bits.fp_ctrl.fastpipe, issue_slots[14].out_uop.fp_ctrl.fastpipe \n connect issue_slots[13].in_uop.bits.fp_ctrl.toint, issue_slots[14].out_uop.fp_ctrl.toint \n connect issue_slots[13].in_uop.bits.fp_ctrl.fromint, issue_slots[14].out_uop.fp_ctrl.fromint \n connect issue_slots[13].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[14].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[13].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[14].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[13].in_uop.bits.fp_ctrl.swap23, issue_slots[14].out_uop.fp_ctrl.swap23 \n connect issue_slots[13].in_uop.bits.fp_ctrl.swap12, issue_slots[14].out_uop.fp_ctrl.swap12 \n connect issue_slots[13].in_uop.bits.fp_ctrl.ren3, issue_slots[14].out_uop.fp_ctrl.ren3 \n connect issue_slots[13].in_uop.bits.fp_ctrl.ren2, issue_slots[14].out_uop.fp_ctrl.ren2 \n connect issue_slots[13].in_uop.bits.fp_ctrl.ren1, issue_slots[14].out_uop.fp_ctrl.ren1 \n connect issue_slots[13].in_uop.bits.fp_ctrl.wen, issue_slots[14].out_uop.fp_ctrl.wen \n connect issue_slots[13].in_uop.bits.fp_ctrl.ldst, issue_slots[14].out_uop.fp_ctrl.ldst \n connect issue_slots[13].in_uop.bits.op2_sel, issue_slots[14].out_uop.op2_sel \n connect issue_slots[13].in_uop.bits.op1_sel, issue_slots[14].out_uop.op1_sel \n connect issue_slots[13].in_uop.bits.imm_packed, issue_slots[14].out_uop.imm_packed \n connect issue_slots[13].in_uop.bits.pimm, issue_slots[14].out_uop.pimm \n connect issue_slots[13].in_uop.bits.imm_sel, issue_slots[14].out_uop.imm_sel \n connect issue_slots[13].in_uop.bits.imm_rename, issue_slots[14].out_uop.imm_rename \n connect issue_slots[13].in_uop.bits.taken, issue_slots[14].out_uop.taken \n connect issue_slots[13].in_uop.bits.pc_lob, issue_slots[14].out_uop.pc_lob \n connect issue_slots[13].in_uop.bits.edge_inst, issue_slots[14].out_uop.edge_inst \n connect issue_slots[13].in_uop.bits.ftq_idx, issue_slots[14].out_uop.ftq_idx \n connect issue_slots[13].in_uop.bits.is_mov, issue_slots[14].out_uop.is_mov \n connect issue_slots[13].in_uop.bits.is_rocc, issue_slots[14].out_uop.is_rocc \n connect issue_slots[13].in_uop.bits.is_sys_pc2epc, issue_slots[14].out_uop.is_sys_pc2epc \n connect issue_slots[13].in_uop.bits.is_eret, issue_slots[14].out_uop.is_eret \n connect issue_slots[13].in_uop.bits.is_amo, issue_slots[14].out_uop.is_amo \n connect issue_slots[13].in_uop.bits.is_sfence, issue_slots[14].out_uop.is_sfence \n connect issue_slots[13].in_uop.bits.is_fencei, issue_slots[14].out_uop.is_fencei \n connect issue_slots[13].in_uop.bits.is_fence, issue_slots[14].out_uop.is_fence \n connect issue_slots[13].in_uop.bits.is_sfb, issue_slots[14].out_uop.is_sfb \n connect issue_slots[13].in_uop.bits.br_type, issue_slots[14].out_uop.br_type \n connect issue_slots[13].in_uop.bits.br_tag, issue_slots[14].out_uop.br_tag \n connect issue_slots[13].in_uop.bits.br_mask, issue_slots[14].out_uop.br_mask \n connect issue_slots[13].in_uop.bits.dis_col_sel, issue_slots[14].out_uop.dis_col_sel \n connect issue_slots[13].in_uop.bits.iw_p3_bypass_hint, issue_slots[14].out_uop.iw_p3_bypass_hint \n connect issue_slots[13].in_uop.bits.iw_p2_bypass_hint, issue_slots[14].out_uop.iw_p2_bypass_hint \n connect issue_slots[13].in_uop.bits.iw_p1_bypass_hint, issue_slots[14].out_uop.iw_p1_bypass_hint \n connect issue_slots[13].in_uop.bits.iw_p2_speculative_child, issue_slots[14].out_uop.iw_p2_speculative_child \n connect issue_slots[13].in_uop.bits.iw_p1_speculative_child, issue_slots[14].out_uop.iw_p1_speculative_child \n connect issue_slots[13].in_uop.bits.iw_issued_partial_dgen, issue_slots[14].out_uop.iw_issued_partial_dgen \n connect issue_slots[13].in_uop.bits.iw_issued_partial_agen, issue_slots[14].out_uop.iw_issued_partial_agen \n connect issue_slots[13].in_uop.bits.iw_issued, issue_slots[14].out_uop.iw_issued \n connect issue_slots[13].in_uop.bits.fu_code[0], issue_slots[14].out_uop.fu_code[0] \n connect issue_slots[13].in_uop.bits.fu_code[1], issue_slots[14].out_uop.fu_code[1] \n connect issue_slots[13].in_uop.bits.fu_code[2], issue_slots[14].out_uop.fu_code[2] \n connect issue_slots[13].in_uop.bits.fu_code[3], issue_slots[14].out_uop.fu_code[3] \n connect issue_slots[13].in_uop.bits.fu_code[4], issue_slots[14].out_uop.fu_code[4] \n connect issue_slots[13].in_uop.bits.fu_code[5], issue_slots[14].out_uop.fu_code[5] \n connect issue_slots[13].in_uop.bits.fu_code[6], issue_slots[14].out_uop.fu_code[6] \n connect issue_slots[13].in_uop.bits.fu_code[7], issue_slots[14].out_uop.fu_code[7] \n connect issue_slots[13].in_uop.bits.fu_code[8], issue_slots[14].out_uop.fu_code[8] \n connect issue_slots[13].in_uop.bits.fu_code[9], issue_slots[14].out_uop.fu_code[9] \n connect issue_slots[13].in_uop.bits.iq_type[0], issue_slots[14].out_uop.iq_type[0] \n connect issue_slots[13].in_uop.bits.iq_type[1], issue_slots[14].out_uop.iq_type[1] \n connect issue_slots[13].in_uop.bits.iq_type[2], issue_slots[14].out_uop.iq_type[2] \n connect issue_slots[13].in_uop.bits.iq_type[3], issue_slots[14].out_uop.iq_type[3] \n connect issue_slots[13].in_uop.bits.debug_pc, issue_slots[14].out_uop.debug_pc \n connect issue_slots[13].in_uop.bits.is_rvc, issue_slots[14].out_uop.is_rvc \n connect issue_slots[13].in_uop.bits.debug_inst, issue_slots[14].out_uop.debug_inst \n connect issue_slots[13].in_uop.bits.inst, issue_slots[14].out_uop.inst \n node _T_188 = eq(shamts_oh[14], UInt<1>(0h1)) \n when _T_188 : \n connect issue_slots[13].in_uop.valid, issue_slots[14].will_be_valid \n connect issue_slots[13].in_uop.bits.debug_tsrc, issue_slots[14].out_uop.debug_tsrc \n connect issue_slots[13].in_uop.bits.debug_fsrc, issue_slots[14].out_uop.debug_fsrc \n connect issue_slots[13].in_uop.bits.bp_xcpt_if, issue_slots[14].out_uop.bp_xcpt_if \n connect issue_slots[13].in_uop.bits.bp_debug_if, issue_slots[14].out_uop.bp_debug_if \n connect issue_slots[13].in_uop.bits.xcpt_ma_if, issue_slots[14].out_uop.xcpt_ma_if \n connect issue_slots[13].in_uop.bits.xcpt_ae_if, issue_slots[14].out_uop.xcpt_ae_if \n connect issue_slots[13].in_uop.bits.xcpt_pf_if, issue_slots[14].out_uop.xcpt_pf_if \n connect issue_slots[13].in_uop.bits.fp_typ, issue_slots[14].out_uop.fp_typ \n connect issue_slots[13].in_uop.bits.fp_rm, issue_slots[14].out_uop.fp_rm \n connect issue_slots[13].in_uop.bits.fp_val, issue_slots[14].out_uop.fp_val \n connect issue_slots[13].in_uop.bits.fcn_op, issue_slots[14].out_uop.fcn_op \n connect issue_slots[13].in_uop.bits.fcn_dw, issue_slots[14].out_uop.fcn_dw \n connect issue_slots[13].in_uop.bits.frs3_en, issue_slots[14].out_uop.frs3_en \n connect issue_slots[13].in_uop.bits.lrs2_rtype, issue_slots[14].out_uop.lrs2_rtype \n connect issue_slots[13].in_uop.bits.lrs1_rtype, issue_slots[14].out_uop.lrs1_rtype \n connect issue_slots[13].in_uop.bits.dst_rtype, issue_slots[14].out_uop.dst_rtype \n connect issue_slots[13].in_uop.bits.lrs3, issue_slots[14].out_uop.lrs3 \n connect issue_slots[13].in_uop.bits.lrs2, issue_slots[14].out_uop.lrs2 \n connect issue_slots[13].in_uop.bits.lrs1, issue_slots[14].out_uop.lrs1 \n connect issue_slots[13].in_uop.bits.ldst, issue_slots[14].out_uop.ldst \n connect issue_slots[13].in_uop.bits.ldst_is_rs1, issue_slots[14].out_uop.ldst_is_rs1 \n connect issue_slots[13].in_uop.bits.csr_cmd, issue_slots[14].out_uop.csr_cmd \n connect issue_slots[13].in_uop.bits.flush_on_commit, issue_slots[14].out_uop.flush_on_commit \n connect issue_slots[13].in_uop.bits.is_unique, issue_slots[14].out_uop.is_unique \n connect issue_slots[13].in_uop.bits.uses_stq, issue_slots[14].out_uop.uses_stq \n connect issue_slots[13].in_uop.bits.uses_ldq, issue_slots[14].out_uop.uses_ldq \n connect issue_slots[13].in_uop.bits.mem_signed, issue_slots[14].out_uop.mem_signed \n connect issue_slots[13].in_uop.bits.mem_size, issue_slots[14].out_uop.mem_size \n connect issue_slots[13].in_uop.bits.mem_cmd, issue_slots[14].out_uop.mem_cmd \n connect issue_slots[13].in_uop.bits.exc_cause, issue_slots[14].out_uop.exc_cause \n connect issue_slots[13].in_uop.bits.exception, issue_slots[14].out_uop.exception \n connect issue_slots[13].in_uop.bits.stale_pdst, issue_slots[14].out_uop.stale_pdst \n connect issue_slots[13].in_uop.bits.ppred_busy, issue_slots[14].out_uop.ppred_busy \n connect issue_slots[13].in_uop.bits.prs3_busy, issue_slots[14].out_uop.prs3_busy \n connect issue_slots[13].in_uop.bits.prs2_busy, issue_slots[14].out_uop.prs2_busy \n connect issue_slots[13].in_uop.bits.prs1_busy, issue_slots[14].out_uop.prs1_busy \n connect issue_slots[13].in_uop.bits.ppred, issue_slots[14].out_uop.ppred \n connect issue_slots[13].in_uop.bits.prs3, issue_slots[14].out_uop.prs3 \n connect issue_slots[13].in_uop.bits.prs2, issue_slots[14].out_uop.prs2 \n connect issue_slots[13].in_uop.bits.prs1, issue_slots[14].out_uop.prs1 \n connect issue_slots[13].in_uop.bits.pdst, issue_slots[14].out_uop.pdst \n connect issue_slots[13].in_uop.bits.rxq_idx, issue_slots[14].out_uop.rxq_idx \n connect issue_slots[13].in_uop.bits.stq_idx, issue_slots[14].out_uop.stq_idx \n connect issue_slots[13].in_uop.bits.ldq_idx, issue_slots[14].out_uop.ldq_idx \n connect issue_slots[13].in_uop.bits.rob_idx, issue_slots[14].out_uop.rob_idx \n connect issue_slots[13].in_uop.bits.fp_ctrl.vec, issue_slots[14].out_uop.fp_ctrl.vec \n connect issue_slots[13].in_uop.bits.fp_ctrl.wflags, issue_slots[14].out_uop.fp_ctrl.wflags \n connect issue_slots[13].in_uop.bits.fp_ctrl.sqrt, issue_slots[14].out_uop.fp_ctrl.sqrt \n connect issue_slots[13].in_uop.bits.fp_ctrl.div, issue_slots[14].out_uop.fp_ctrl.div \n connect issue_slots[13].in_uop.bits.fp_ctrl.fma, issue_slots[14].out_uop.fp_ctrl.fma \n connect issue_slots[13].in_uop.bits.fp_ctrl.fastpipe, issue_slots[14].out_uop.fp_ctrl.fastpipe \n connect issue_slots[13].in_uop.bits.fp_ctrl.toint, issue_slots[14].out_uop.fp_ctrl.toint \n connect issue_slots[13].in_uop.bits.fp_ctrl.fromint, issue_slots[14].out_uop.fp_ctrl.fromint \n connect issue_slots[13].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[14].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[13].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[14].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[13].in_uop.bits.fp_ctrl.swap23, issue_slots[14].out_uop.fp_ctrl.swap23 \n connect issue_slots[13].in_uop.bits.fp_ctrl.swap12, issue_slots[14].out_uop.fp_ctrl.swap12 \n connect issue_slots[13].in_uop.bits.fp_ctrl.ren3, issue_slots[14].out_uop.fp_ctrl.ren3 \n connect issue_slots[13].in_uop.bits.fp_ctrl.ren2, issue_slots[14].out_uop.fp_ctrl.ren2 \n connect issue_slots[13].in_uop.bits.fp_ctrl.ren1, issue_slots[14].out_uop.fp_ctrl.ren1 \n connect issue_slots[13].in_uop.bits.fp_ctrl.wen, issue_slots[14].out_uop.fp_ctrl.wen \n connect issue_slots[13].in_uop.bits.fp_ctrl.ldst, issue_slots[14].out_uop.fp_ctrl.ldst \n connect issue_slots[13].in_uop.bits.op2_sel, issue_slots[14].out_uop.op2_sel \n connect issue_slots[13].in_uop.bits.op1_sel, issue_slots[14].out_uop.op1_sel \n connect issue_slots[13].in_uop.bits.imm_packed, issue_slots[14].out_uop.imm_packed \n connect issue_slots[13].in_uop.bits.pimm, issue_slots[14].out_uop.pimm \n connect issue_slots[13].in_uop.bits.imm_sel, issue_slots[14].out_uop.imm_sel \n connect issue_slots[13].in_uop.bits.imm_rename, issue_slots[14].out_uop.imm_rename \n connect issue_slots[13].in_uop.bits.taken, issue_slots[14].out_uop.taken \n connect issue_slots[13].in_uop.bits.pc_lob, issue_slots[14].out_uop.pc_lob \n connect issue_slots[13].in_uop.bits.edge_inst, issue_slots[14].out_uop.edge_inst \n connect issue_slots[13].in_uop.bits.ftq_idx, issue_slots[14].out_uop.ftq_idx \n connect issue_slots[13].in_uop.bits.is_mov, issue_slots[14].out_uop.is_mov \n connect issue_slots[13].in_uop.bits.is_rocc, issue_slots[14].out_uop.is_rocc \n connect issue_slots[13].in_uop.bits.is_sys_pc2epc, issue_slots[14].out_uop.is_sys_pc2epc \n connect issue_slots[13].in_uop.bits.is_eret, issue_slots[14].out_uop.is_eret \n connect issue_slots[13].in_uop.bits.is_amo, issue_slots[14].out_uop.is_amo \n connect issue_slots[13].in_uop.bits.is_sfence, issue_slots[14].out_uop.is_sfence \n connect issue_slots[13].in_uop.bits.is_fencei, issue_slots[14].out_uop.is_fencei \n connect issue_slots[13].in_uop.bits.is_fence, issue_slots[14].out_uop.is_fence \n connect issue_slots[13].in_uop.bits.is_sfb, issue_slots[14].out_uop.is_sfb \n connect issue_slots[13].in_uop.bits.br_type, issue_slots[14].out_uop.br_type \n connect issue_slots[13].in_uop.bits.br_tag, issue_slots[14].out_uop.br_tag \n connect issue_slots[13].in_uop.bits.br_mask, issue_slots[14].out_uop.br_mask \n connect issue_slots[13].in_uop.bits.dis_col_sel, issue_slots[14].out_uop.dis_col_sel \n connect issue_slots[13].in_uop.bits.iw_p3_bypass_hint, issue_slots[14].out_uop.iw_p3_bypass_hint \n connect issue_slots[13].in_uop.bits.iw_p2_bypass_hint, issue_slots[14].out_uop.iw_p2_bypass_hint \n connect issue_slots[13].in_uop.bits.iw_p1_bypass_hint, issue_slots[14].out_uop.iw_p1_bypass_hint \n connect issue_slots[13].in_uop.bits.iw_p2_speculative_child, issue_slots[14].out_uop.iw_p2_speculative_child \n connect issue_slots[13].in_uop.bits.iw_p1_speculative_child, issue_slots[14].out_uop.iw_p1_speculative_child \n connect issue_slots[13].in_uop.bits.iw_issued_partial_dgen, issue_slots[14].out_uop.iw_issued_partial_dgen \n connect issue_slots[13].in_uop.bits.iw_issued_partial_agen, issue_slots[14].out_uop.iw_issued_partial_agen \n connect issue_slots[13].in_uop.bits.iw_issued, issue_slots[14].out_uop.iw_issued \n connect issue_slots[13].in_uop.bits.fu_code[0], issue_slots[14].out_uop.fu_code[0] \n connect issue_slots[13].in_uop.bits.fu_code[1], issue_slots[14].out_uop.fu_code[1] \n connect issue_slots[13].in_uop.bits.fu_code[2], issue_slots[14].out_uop.fu_code[2] \n connect issue_slots[13].in_uop.bits.fu_code[3], issue_slots[14].out_uop.fu_code[3] \n connect issue_slots[13].in_uop.bits.fu_code[4], issue_slots[14].out_uop.fu_code[4] \n connect issue_slots[13].in_uop.bits.fu_code[5], issue_slots[14].out_uop.fu_code[5] \n connect issue_slots[13].in_uop.bits.fu_code[6], issue_slots[14].out_uop.fu_code[6] \n connect issue_slots[13].in_uop.bits.fu_code[7], issue_slots[14].out_uop.fu_code[7] \n connect issue_slots[13].in_uop.bits.fu_code[8], issue_slots[14].out_uop.fu_code[8] \n connect issue_slots[13].in_uop.bits.fu_code[9], issue_slots[14].out_uop.fu_code[9] \n connect issue_slots[13].in_uop.bits.iq_type[0], issue_slots[14].out_uop.iq_type[0] \n connect issue_slots[13].in_uop.bits.iq_type[1], issue_slots[14].out_uop.iq_type[1] \n connect issue_slots[13].in_uop.bits.iq_type[2], issue_slots[14].out_uop.iq_type[2] \n connect issue_slots[13].in_uop.bits.iq_type[3], issue_slots[14].out_uop.iq_type[3] \n connect issue_slots[13].in_uop.bits.debug_pc, issue_slots[14].out_uop.debug_pc \n connect issue_slots[13].in_uop.bits.is_rvc, issue_slots[14].out_uop.is_rvc \n connect issue_slots[13].in_uop.bits.debug_inst, issue_slots[14].out_uop.debug_inst \n connect issue_slots[13].in_uop.bits.inst, issue_slots[14].out_uop.inst \n node _T_189 = eq(shamts_oh[15], UInt<2>(0h2)) \n when _T_189 : \n connect issue_slots[13].in_uop.valid, issue_slots[15].will_be_valid \n connect issue_slots[13].in_uop.bits.debug_tsrc, issue_slots[15].out_uop.debug_tsrc \n connect issue_slots[13].in_uop.bits.debug_fsrc, issue_slots[15].out_uop.debug_fsrc \n connect issue_slots[13].in_uop.bits.bp_xcpt_if, issue_slots[15].out_uop.bp_xcpt_if \n connect issue_slots[13].in_uop.bits.bp_debug_if, issue_slots[15].out_uop.bp_debug_if \n connect issue_slots[13].in_uop.bits.xcpt_ma_if, issue_slots[15].out_uop.xcpt_ma_if \n connect issue_slots[13].in_uop.bits.xcpt_ae_if, issue_slots[15].out_uop.xcpt_ae_if \n connect issue_slots[13].in_uop.bits.xcpt_pf_if, issue_slots[15].out_uop.xcpt_pf_if \n connect issue_slots[13].in_uop.bits.fp_typ, issue_slots[15].out_uop.fp_typ \n connect issue_slots[13].in_uop.bits.fp_rm, issue_slots[15].out_uop.fp_rm \n connect issue_slots[13].in_uop.bits.fp_val, issue_slots[15].out_uop.fp_val \n connect issue_slots[13].in_uop.bits.fcn_op, issue_slots[15].out_uop.fcn_op \n connect issue_slots[13].in_uop.bits.fcn_dw, issue_slots[15].out_uop.fcn_dw \n connect issue_slots[13].in_uop.bits.frs3_en, issue_slots[15].out_uop.frs3_en \n connect issue_slots[13].in_uop.bits.lrs2_rtype, issue_slots[15].out_uop.lrs2_rtype \n connect issue_slots[13].in_uop.bits.lrs1_rtype, issue_slots[15].out_uop.lrs1_rtype \n connect issue_slots[13].in_uop.bits.dst_rtype, issue_slots[15].out_uop.dst_rtype \n connect issue_slots[13].in_uop.bits.lrs3, issue_slots[15].out_uop.lrs3 \n connect issue_slots[13].in_uop.bits.lrs2, issue_slots[15].out_uop.lrs2 \n connect issue_slots[13].in_uop.bits.lrs1, issue_slots[15].out_uop.lrs1 \n connect issue_slots[13].in_uop.bits.ldst, issue_slots[15].out_uop.ldst \n connect issue_slots[13].in_uop.bits.ldst_is_rs1, issue_slots[15].out_uop.ldst_is_rs1 \n connect issue_slots[13].in_uop.bits.csr_cmd, issue_slots[15].out_uop.csr_cmd \n connect issue_slots[13].in_uop.bits.flush_on_commit, issue_slots[15].out_uop.flush_on_commit \n connect issue_slots[13].in_uop.bits.is_unique, issue_slots[15].out_uop.is_unique \n connect issue_slots[13].in_uop.bits.uses_stq, issue_slots[15].out_uop.uses_stq \n connect issue_slots[13].in_uop.bits.uses_ldq, issue_slots[15].out_uop.uses_ldq \n connect issue_slots[13].in_uop.bits.mem_signed, issue_slots[15].out_uop.mem_signed \n connect issue_slots[13].in_uop.bits.mem_size, issue_slots[15].out_uop.mem_size \n connect issue_slots[13].in_uop.bits.mem_cmd, issue_slots[15].out_uop.mem_cmd \n connect issue_slots[13].in_uop.bits.exc_cause, issue_slots[15].out_uop.exc_cause \n connect issue_slots[13].in_uop.bits.exception, issue_slots[15].out_uop.exception \n connect issue_slots[13].in_uop.bits.stale_pdst, issue_slots[15].out_uop.stale_pdst \n connect issue_slots[13].in_uop.bits.ppred_busy, issue_slots[15].out_uop.ppred_busy \n connect issue_slots[13].in_uop.bits.prs3_busy, issue_slots[15].out_uop.prs3_busy \n connect issue_slots[13].in_uop.bits.prs2_busy, issue_slots[15].out_uop.prs2_busy \n connect issue_slots[13].in_uop.bits.prs1_busy, issue_slots[15].out_uop.prs1_busy \n connect issue_slots[13].in_uop.bits.ppred, issue_slots[15].out_uop.ppred \n connect issue_slots[13].in_uop.bits.prs3, issue_slots[15].out_uop.prs3 \n connect issue_slots[13].in_uop.bits.prs2, issue_slots[15].out_uop.prs2 \n connect issue_slots[13].in_uop.bits.prs1, issue_slots[15].out_uop.prs1 \n connect issue_slots[13].in_uop.bits.pdst, issue_slots[15].out_uop.pdst \n connect issue_slots[13].in_uop.bits.rxq_idx, issue_slots[15].out_uop.rxq_idx \n connect issue_slots[13].in_uop.bits.stq_idx, issue_slots[15].out_uop.stq_idx \n connect issue_slots[13].in_uop.bits.ldq_idx, issue_slots[15].out_uop.ldq_idx \n connect issue_slots[13].in_uop.bits.rob_idx, issue_slots[15].out_uop.rob_idx \n connect issue_slots[13].in_uop.bits.fp_ctrl.vec, issue_slots[15].out_uop.fp_ctrl.vec \n connect issue_slots[13].in_uop.bits.fp_ctrl.wflags, issue_slots[15].out_uop.fp_ctrl.wflags \n connect issue_slots[13].in_uop.bits.fp_ctrl.sqrt, issue_slots[15].out_uop.fp_ctrl.sqrt \n connect issue_slots[13].in_uop.bits.fp_ctrl.div, issue_slots[15].out_uop.fp_ctrl.div \n connect issue_slots[13].in_uop.bits.fp_ctrl.fma, issue_slots[15].out_uop.fp_ctrl.fma \n connect issue_slots[13].in_uop.bits.fp_ctrl.fastpipe, issue_slots[15].out_uop.fp_ctrl.fastpipe \n connect issue_slots[13].in_uop.bits.fp_ctrl.toint, issue_slots[15].out_uop.fp_ctrl.toint \n connect issue_slots[13].in_uop.bits.fp_ctrl.fromint, issue_slots[15].out_uop.fp_ctrl.fromint \n connect issue_slots[13].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[15].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[13].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[15].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[13].in_uop.bits.fp_ctrl.swap23, issue_slots[15].out_uop.fp_ctrl.swap23 \n connect issue_slots[13].in_uop.bits.fp_ctrl.swap12, issue_slots[15].out_uop.fp_ctrl.swap12 \n connect issue_slots[13].in_uop.bits.fp_ctrl.ren3, issue_slots[15].out_uop.fp_ctrl.ren3 \n connect issue_slots[13].in_uop.bits.fp_ctrl.ren2, issue_slots[15].out_uop.fp_ctrl.ren2 \n connect issue_slots[13].in_uop.bits.fp_ctrl.ren1, issue_slots[15].out_uop.fp_ctrl.ren1 \n connect issue_slots[13].in_uop.bits.fp_ctrl.wen, issue_slots[15].out_uop.fp_ctrl.wen \n connect issue_slots[13].in_uop.bits.fp_ctrl.ldst, issue_slots[15].out_uop.fp_ctrl.ldst \n connect issue_slots[13].in_uop.bits.op2_sel, issue_slots[15].out_uop.op2_sel \n connect issue_slots[13].in_uop.bits.op1_sel, issue_slots[15].out_uop.op1_sel \n connect issue_slots[13].in_uop.bits.imm_packed, issue_slots[15].out_uop.imm_packed \n connect issue_slots[13].in_uop.bits.pimm, issue_slots[15].out_uop.pimm \n connect issue_slots[13].in_uop.bits.imm_sel, issue_slots[15].out_uop.imm_sel \n connect issue_slots[13].in_uop.bits.imm_rename, issue_slots[15].out_uop.imm_rename \n connect issue_slots[13].in_uop.bits.taken, issue_slots[15].out_uop.taken \n connect issue_slots[13].in_uop.bits.pc_lob, issue_slots[15].out_uop.pc_lob \n connect issue_slots[13].in_uop.bits.edge_inst, issue_slots[15].out_uop.edge_inst \n connect issue_slots[13].in_uop.bits.ftq_idx, issue_slots[15].out_uop.ftq_idx \n connect issue_slots[13].in_uop.bits.is_mov, issue_slots[15].out_uop.is_mov \n connect issue_slots[13].in_uop.bits.is_rocc, issue_slots[15].out_uop.is_rocc \n connect issue_slots[13].in_uop.bits.is_sys_pc2epc, issue_slots[15].out_uop.is_sys_pc2epc \n connect issue_slots[13].in_uop.bits.is_eret, issue_slots[15].out_uop.is_eret \n connect issue_slots[13].in_uop.bits.is_amo, issue_slots[15].out_uop.is_amo \n connect issue_slots[13].in_uop.bits.is_sfence, issue_slots[15].out_uop.is_sfence \n connect issue_slots[13].in_uop.bits.is_fencei, issue_slots[15].out_uop.is_fencei \n connect issue_slots[13].in_uop.bits.is_fence, issue_slots[15].out_uop.is_fence \n connect issue_slots[13].in_uop.bits.is_sfb, issue_slots[15].out_uop.is_sfb \n connect issue_slots[13].in_uop.bits.br_type, issue_slots[15].out_uop.br_type \n connect issue_slots[13].in_uop.bits.br_tag, issue_slots[15].out_uop.br_tag \n connect issue_slots[13].in_uop.bits.br_mask, issue_slots[15].out_uop.br_mask \n connect issue_slots[13].in_uop.bits.dis_col_sel, issue_slots[15].out_uop.dis_col_sel \n connect issue_slots[13].in_uop.bits.iw_p3_bypass_hint, issue_slots[15].out_uop.iw_p3_bypass_hint \n connect issue_slots[13].in_uop.bits.iw_p2_bypass_hint, issue_slots[15].out_uop.iw_p2_bypass_hint \n connect issue_slots[13].in_uop.bits.iw_p1_bypass_hint, issue_slots[15].out_uop.iw_p1_bypass_hint \n connect issue_slots[13].in_uop.bits.iw_p2_speculative_child, issue_slots[15].out_uop.iw_p2_speculative_child \n connect issue_slots[13].in_uop.bits.iw_p1_speculative_child, issue_slots[15].out_uop.iw_p1_speculative_child \n connect issue_slots[13].in_uop.bits.iw_issued_partial_dgen, issue_slots[15].out_uop.iw_issued_partial_dgen \n connect issue_slots[13].in_uop.bits.iw_issued_partial_agen, issue_slots[15].out_uop.iw_issued_partial_agen \n connect issue_slots[13].in_uop.bits.iw_issued, issue_slots[15].out_uop.iw_issued \n connect issue_slots[13].in_uop.bits.fu_code[0], issue_slots[15].out_uop.fu_code[0] \n connect issue_slots[13].in_uop.bits.fu_code[1], issue_slots[15].out_uop.fu_code[1] \n connect issue_slots[13].in_uop.bits.fu_code[2], issue_slots[15].out_uop.fu_code[2] \n connect issue_slots[13].in_uop.bits.fu_code[3], issue_slots[15].out_uop.fu_code[3] \n connect issue_slots[13].in_uop.bits.fu_code[4], issue_slots[15].out_uop.fu_code[4] \n connect issue_slots[13].in_uop.bits.fu_code[5], issue_slots[15].out_uop.fu_code[5] \n connect issue_slots[13].in_uop.bits.fu_code[6], issue_slots[15].out_uop.fu_code[6] \n connect issue_slots[13].in_uop.bits.fu_code[7], issue_slots[15].out_uop.fu_code[7] \n connect issue_slots[13].in_uop.bits.fu_code[8], issue_slots[15].out_uop.fu_code[8] \n connect issue_slots[13].in_uop.bits.fu_code[9], issue_slots[15].out_uop.fu_code[9] \n connect issue_slots[13].in_uop.bits.iq_type[0], issue_slots[15].out_uop.iq_type[0] \n connect issue_slots[13].in_uop.bits.iq_type[1], issue_slots[15].out_uop.iq_type[1] \n connect issue_slots[13].in_uop.bits.iq_type[2], issue_slots[15].out_uop.iq_type[2] \n connect issue_slots[13].in_uop.bits.iq_type[3], issue_slots[15].out_uop.iq_type[3] \n connect issue_slots[13].in_uop.bits.debug_pc, issue_slots[15].out_uop.debug_pc \n connect issue_slots[13].in_uop.bits.is_rvc, issue_slots[15].out_uop.is_rvc \n connect issue_slots[13].in_uop.bits.debug_inst, issue_slots[15].out_uop.debug_inst \n connect issue_slots[13].in_uop.bits.inst, issue_slots[15].out_uop.inst \n node _issue_slots_13_clear_T = neq(shamts_oh[13], UInt<1>(0h0)) \n connect issue_slots[13].clear, _issue_slots_13_clear_T \n connect issue_slots[14].in_uop.valid, UInt<1>(0h0) \n connect issue_slots[14].in_uop.bits.debug_tsrc, issue_slots[15].out_uop.debug_tsrc \n connect issue_slots[14].in_uop.bits.debug_fsrc, issue_slots[15].out_uop.debug_fsrc \n connect issue_slots[14].in_uop.bits.bp_xcpt_if, issue_slots[15].out_uop.bp_xcpt_if \n connect issue_slots[14].in_uop.bits.bp_debug_if, issue_slots[15].out_uop.bp_debug_if \n connect issue_slots[14].in_uop.bits.xcpt_ma_if, issue_slots[15].out_uop.xcpt_ma_if \n connect issue_slots[14].in_uop.bits.xcpt_ae_if, issue_slots[15].out_uop.xcpt_ae_if \n connect issue_slots[14].in_uop.bits.xcpt_pf_if, issue_slots[15].out_uop.xcpt_pf_if \n connect issue_slots[14].in_uop.bits.fp_typ, issue_slots[15].out_uop.fp_typ \n connect issue_slots[14].in_uop.bits.fp_rm, issue_slots[15].out_uop.fp_rm \n connect issue_slots[14].in_uop.bits.fp_val, issue_slots[15].out_uop.fp_val \n connect issue_slots[14].in_uop.bits.fcn_op, issue_slots[15].out_uop.fcn_op \n connect issue_slots[14].in_uop.bits.fcn_dw, issue_slots[15].out_uop.fcn_dw \n connect issue_slots[14].in_uop.bits.frs3_en, issue_slots[15].out_uop.frs3_en \n connect issue_slots[14].in_uop.bits.lrs2_rtype, issue_slots[15].out_uop.lrs2_rtype \n connect issue_slots[14].in_uop.bits.lrs1_rtype, issue_slots[15].out_uop.lrs1_rtype \n connect issue_slots[14].in_uop.bits.dst_rtype, issue_slots[15].out_uop.dst_rtype \n connect issue_slots[14].in_uop.bits.lrs3, issue_slots[15].out_uop.lrs3 \n connect issue_slots[14].in_uop.bits.lrs2, issue_slots[15].out_uop.lrs2 \n connect issue_slots[14].in_uop.bits.lrs1, issue_slots[15].out_uop.lrs1 \n connect issue_slots[14].in_uop.bits.ldst, issue_slots[15].out_uop.ldst \n connect issue_slots[14].in_uop.bits.ldst_is_rs1, issue_slots[15].out_uop.ldst_is_rs1 \n connect issue_slots[14].in_uop.bits.csr_cmd, issue_slots[15].out_uop.csr_cmd \n connect issue_slots[14].in_uop.bits.flush_on_commit, issue_slots[15].out_uop.flush_on_commit \n connect issue_slots[14].in_uop.bits.is_unique, issue_slots[15].out_uop.is_unique \n connect issue_slots[14].in_uop.bits.uses_stq, issue_slots[15].out_uop.uses_stq \n connect issue_slots[14].in_uop.bits.uses_ldq, issue_slots[15].out_uop.uses_ldq \n connect issue_slots[14].in_uop.bits.mem_signed, issue_slots[15].out_uop.mem_signed \n connect issue_slots[14].in_uop.bits.mem_size, issue_slots[15].out_uop.mem_size \n connect issue_slots[14].in_uop.bits.mem_cmd, issue_slots[15].out_uop.mem_cmd \n connect issue_slots[14].in_uop.bits.exc_cause, issue_slots[15].out_uop.exc_cause \n connect issue_slots[14].in_uop.bits.exception, issue_slots[15].out_uop.exception \n connect issue_slots[14].in_uop.bits.stale_pdst, issue_slots[15].out_uop.stale_pdst \n connect issue_slots[14].in_uop.bits.ppred_busy, issue_slots[15].out_uop.ppred_busy \n connect issue_slots[14].in_uop.bits.prs3_busy, issue_slots[15].out_uop.prs3_busy \n connect issue_slots[14].in_uop.bits.prs2_busy, issue_slots[15].out_uop.prs2_busy \n connect issue_slots[14].in_uop.bits.prs1_busy, issue_slots[15].out_uop.prs1_busy \n connect issue_slots[14].in_uop.bits.ppred, issue_slots[15].out_uop.ppred \n connect issue_slots[14].in_uop.bits.prs3, issue_slots[15].out_uop.prs3 \n connect issue_slots[14].in_uop.bits.prs2, issue_slots[15].out_uop.prs2 \n connect issue_slots[14].in_uop.bits.prs1, issue_slots[15].out_uop.prs1 \n connect issue_slots[14].in_uop.bits.pdst, issue_slots[15].out_uop.pdst \n connect issue_slots[14].in_uop.bits.rxq_idx, issue_slots[15].out_uop.rxq_idx \n connect issue_slots[14].in_uop.bits.stq_idx, issue_slots[15].out_uop.stq_idx \n connect issue_slots[14].in_uop.bits.ldq_idx, issue_slots[15].out_uop.ldq_idx \n connect issue_slots[14].in_uop.bits.rob_idx, issue_slots[15].out_uop.rob_idx \n connect issue_slots[14].in_uop.bits.fp_ctrl.vec, issue_slots[15].out_uop.fp_ctrl.vec \n connect issue_slots[14].in_uop.bits.fp_ctrl.wflags, issue_slots[15].out_uop.fp_ctrl.wflags \n connect issue_slots[14].in_uop.bits.fp_ctrl.sqrt, issue_slots[15].out_uop.fp_ctrl.sqrt \n connect issue_slots[14].in_uop.bits.fp_ctrl.div, issue_slots[15].out_uop.fp_ctrl.div \n connect issue_slots[14].in_uop.bits.fp_ctrl.fma, issue_slots[15].out_uop.fp_ctrl.fma \n connect issue_slots[14].in_uop.bits.fp_ctrl.fastpipe, issue_slots[15].out_uop.fp_ctrl.fastpipe \n connect issue_slots[14].in_uop.bits.fp_ctrl.toint, issue_slots[15].out_uop.fp_ctrl.toint \n connect issue_slots[14].in_uop.bits.fp_ctrl.fromint, issue_slots[15].out_uop.fp_ctrl.fromint \n connect issue_slots[14].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[15].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[14].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[15].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[14].in_uop.bits.fp_ctrl.swap23, issue_slots[15].out_uop.fp_ctrl.swap23 \n connect issue_slots[14].in_uop.bits.fp_ctrl.swap12, issue_slots[15].out_uop.fp_ctrl.swap12 \n connect issue_slots[14].in_uop.bits.fp_ctrl.ren3, issue_slots[15].out_uop.fp_ctrl.ren3 \n connect issue_slots[14].in_uop.bits.fp_ctrl.ren2, issue_slots[15].out_uop.fp_ctrl.ren2 \n connect issue_slots[14].in_uop.bits.fp_ctrl.ren1, issue_slots[15].out_uop.fp_ctrl.ren1 \n connect issue_slots[14].in_uop.bits.fp_ctrl.wen, issue_slots[15].out_uop.fp_ctrl.wen \n connect issue_slots[14].in_uop.bits.fp_ctrl.ldst, issue_slots[15].out_uop.fp_ctrl.ldst \n connect issue_slots[14].in_uop.bits.op2_sel, issue_slots[15].out_uop.op2_sel \n connect issue_slots[14].in_uop.bits.op1_sel, issue_slots[15].out_uop.op1_sel \n connect issue_slots[14].in_uop.bits.imm_packed, issue_slots[15].out_uop.imm_packed \n connect issue_slots[14].in_uop.bits.pimm, issue_slots[15].out_uop.pimm \n connect issue_slots[14].in_uop.bits.imm_sel, issue_slots[15].out_uop.imm_sel \n connect issue_slots[14].in_uop.bits.imm_rename, issue_slots[15].out_uop.imm_rename \n connect issue_slots[14].in_uop.bits.taken, issue_slots[15].out_uop.taken \n connect issue_slots[14].in_uop.bits.pc_lob, issue_slots[15].out_uop.pc_lob \n connect issue_slots[14].in_uop.bits.edge_inst, issue_slots[15].out_uop.edge_inst \n connect issue_slots[14].in_uop.bits.ftq_idx, issue_slots[15].out_uop.ftq_idx \n connect issue_slots[14].in_uop.bits.is_mov, issue_slots[15].out_uop.is_mov \n connect issue_slots[14].in_uop.bits.is_rocc, issue_slots[15].out_uop.is_rocc \n connect issue_slots[14].in_uop.bits.is_sys_pc2epc, issue_slots[15].out_uop.is_sys_pc2epc \n connect issue_slots[14].in_uop.bits.is_eret, issue_slots[15].out_uop.is_eret \n connect issue_slots[14].in_uop.bits.is_amo, issue_slots[15].out_uop.is_amo \n connect issue_slots[14].in_uop.bits.is_sfence, issue_slots[15].out_uop.is_sfence \n connect issue_slots[14].in_uop.bits.is_fencei, issue_slots[15].out_uop.is_fencei \n connect issue_slots[14].in_uop.bits.is_fence, issue_slots[15].out_uop.is_fence \n connect issue_slots[14].in_uop.bits.is_sfb, issue_slots[15].out_uop.is_sfb \n connect issue_slots[14].in_uop.bits.br_type, issue_slots[15].out_uop.br_type \n connect issue_slots[14].in_uop.bits.br_tag, issue_slots[15].out_uop.br_tag \n connect issue_slots[14].in_uop.bits.br_mask, issue_slots[15].out_uop.br_mask \n connect issue_slots[14].in_uop.bits.dis_col_sel, issue_slots[15].out_uop.dis_col_sel \n connect issue_slots[14].in_uop.bits.iw_p3_bypass_hint, issue_slots[15].out_uop.iw_p3_bypass_hint \n connect issue_slots[14].in_uop.bits.iw_p2_bypass_hint, issue_slots[15].out_uop.iw_p2_bypass_hint \n connect issue_slots[14].in_uop.bits.iw_p1_bypass_hint, issue_slots[15].out_uop.iw_p1_bypass_hint \n connect issue_slots[14].in_uop.bits.iw_p2_speculative_child, issue_slots[15].out_uop.iw_p2_speculative_child \n connect issue_slots[14].in_uop.bits.iw_p1_speculative_child, issue_slots[15].out_uop.iw_p1_speculative_child \n connect issue_slots[14].in_uop.bits.iw_issued_partial_dgen, issue_slots[15].out_uop.iw_issued_partial_dgen \n connect issue_slots[14].in_uop.bits.iw_issued_partial_agen, issue_slots[15].out_uop.iw_issued_partial_agen \n connect issue_slots[14].in_uop.bits.iw_issued, issue_slots[15].out_uop.iw_issued \n connect issue_slots[14].in_uop.bits.fu_code[0], issue_slots[15].out_uop.fu_code[0] \n connect issue_slots[14].in_uop.bits.fu_code[1], issue_slots[15].out_uop.fu_code[1] \n connect issue_slots[14].in_uop.bits.fu_code[2], issue_slots[15].out_uop.fu_code[2] \n connect issue_slots[14].in_uop.bits.fu_code[3], issue_slots[15].out_uop.fu_code[3] \n connect issue_slots[14].in_uop.bits.fu_code[4], issue_slots[15].out_uop.fu_code[4] \n connect issue_slots[14].in_uop.bits.fu_code[5], issue_slots[15].out_uop.fu_code[5] \n connect issue_slots[14].in_uop.bits.fu_code[6], issue_slots[15].out_uop.fu_code[6] \n connect issue_slots[14].in_uop.bits.fu_code[7], issue_slots[15].out_uop.fu_code[7] \n connect issue_slots[14].in_uop.bits.fu_code[8], issue_slots[15].out_uop.fu_code[8] \n connect issue_slots[14].in_uop.bits.fu_code[9], issue_slots[15].out_uop.fu_code[9] \n connect issue_slots[14].in_uop.bits.iq_type[0], issue_slots[15].out_uop.iq_type[0] \n connect issue_slots[14].in_uop.bits.iq_type[1], issue_slots[15].out_uop.iq_type[1] \n connect issue_slots[14].in_uop.bits.iq_type[2], issue_slots[15].out_uop.iq_type[2] \n connect issue_slots[14].in_uop.bits.iq_type[3], issue_slots[15].out_uop.iq_type[3] \n connect issue_slots[14].in_uop.bits.debug_pc, issue_slots[15].out_uop.debug_pc \n connect issue_slots[14].in_uop.bits.is_rvc, issue_slots[15].out_uop.is_rvc \n connect issue_slots[14].in_uop.bits.debug_inst, issue_slots[15].out_uop.debug_inst \n connect issue_slots[14].in_uop.bits.inst, issue_slots[15].out_uop.inst \n node _T_190 = eq(shamts_oh[15], UInt<1>(0h1)) \n when _T_190 : \n connect issue_slots[14].in_uop.valid, issue_slots[15].will_be_valid \n connect issue_slots[14].in_uop.bits.debug_tsrc, issue_slots[15].out_uop.debug_tsrc \n connect issue_slots[14].in_uop.bits.debug_fsrc, issue_slots[15].out_uop.debug_fsrc \n connect issue_slots[14].in_uop.bits.bp_xcpt_if, issue_slots[15].out_uop.bp_xcpt_if \n connect issue_slots[14].in_uop.bits.bp_debug_if, issue_slots[15].out_uop.bp_debug_if \n connect issue_slots[14].in_uop.bits.xcpt_ma_if, issue_slots[15].out_uop.xcpt_ma_if \n connect issue_slots[14].in_uop.bits.xcpt_ae_if, issue_slots[15].out_uop.xcpt_ae_if \n connect issue_slots[14].in_uop.bits.xcpt_pf_if, issue_slots[15].out_uop.xcpt_pf_if \n connect issue_slots[14].in_uop.bits.fp_typ, issue_slots[15].out_uop.fp_typ \n connect issue_slots[14].in_uop.bits.fp_rm, issue_slots[15].out_uop.fp_rm \n connect issue_slots[14].in_uop.bits.fp_val, issue_slots[15].out_uop.fp_val \n connect issue_slots[14].in_uop.bits.fcn_op, issue_slots[15].out_uop.fcn_op \n connect issue_slots[14].in_uop.bits.fcn_dw, issue_slots[15].out_uop.fcn_dw \n connect issue_slots[14].in_uop.bits.frs3_en, issue_slots[15].out_uop.frs3_en \n connect issue_slots[14].in_uop.bits.lrs2_rtype, issue_slots[15].out_uop.lrs2_rtype \n connect issue_slots[14].in_uop.bits.lrs1_rtype, issue_slots[15].out_uop.lrs1_rtype \n connect issue_slots[14].in_uop.bits.dst_rtype, issue_slots[15].out_uop.dst_rtype \n connect issue_slots[14].in_uop.bits.lrs3, issue_slots[15].out_uop.lrs3 \n connect issue_slots[14].in_uop.bits.lrs2, issue_slots[15].out_uop.lrs2 \n connect issue_slots[14].in_uop.bits.lrs1, issue_slots[15].out_uop.lrs1 \n connect issue_slots[14].in_uop.bits.ldst, issue_slots[15].out_uop.ldst \n connect issue_slots[14].in_uop.bits.ldst_is_rs1, issue_slots[15].out_uop.ldst_is_rs1 \n connect issue_slots[14].in_uop.bits.csr_cmd, issue_slots[15].out_uop.csr_cmd \n connect issue_slots[14].in_uop.bits.flush_on_commit, issue_slots[15].out_uop.flush_on_commit \n connect issue_slots[14].in_uop.bits.is_unique, issue_slots[15].out_uop.is_unique \n connect issue_slots[14].in_uop.bits.uses_stq, issue_slots[15].out_uop.uses_stq \n connect issue_slots[14].in_uop.bits.uses_ldq, issue_slots[15].out_uop.uses_ldq \n connect issue_slots[14].in_uop.bits.mem_signed, issue_slots[15].out_uop.mem_signed \n connect issue_slots[14].in_uop.bits.mem_size, issue_slots[15].out_uop.mem_size \n connect issue_slots[14].in_uop.bits.mem_cmd, issue_slots[15].out_uop.mem_cmd \n connect issue_slots[14].in_uop.bits.exc_cause, issue_slots[15].out_uop.exc_cause \n connect issue_slots[14].in_uop.bits.exception, issue_slots[15].out_uop.exception \n connect issue_slots[14].in_uop.bits.stale_pdst, issue_slots[15].out_uop.stale_pdst \n connect issue_slots[14].in_uop.bits.ppred_busy, issue_slots[15].out_uop.ppred_busy \n connect issue_slots[14].in_uop.bits.prs3_busy, issue_slots[15].out_uop.prs3_busy \n connect issue_slots[14].in_uop.bits.prs2_busy, issue_slots[15].out_uop.prs2_busy \n connect issue_slots[14].in_uop.bits.prs1_busy, issue_slots[15].out_uop.prs1_busy \n connect issue_slots[14].in_uop.bits.ppred, issue_slots[15].out_uop.ppred \n connect issue_slots[14].in_uop.bits.prs3, issue_slots[15].out_uop.prs3 \n connect issue_slots[14].in_uop.bits.prs2, issue_slots[15].out_uop.prs2 \n connect issue_slots[14].in_uop.bits.prs1, issue_slots[15].out_uop.prs1 \n connect issue_slots[14].in_uop.bits.pdst, issue_slots[15].out_uop.pdst \n connect issue_slots[14].in_uop.bits.rxq_idx, issue_slots[15].out_uop.rxq_idx \n connect issue_slots[14].in_uop.bits.stq_idx, issue_slots[15].out_uop.stq_idx \n connect issue_slots[14].in_uop.bits.ldq_idx, issue_slots[15].out_uop.ldq_idx \n connect issue_slots[14].in_uop.bits.rob_idx, issue_slots[15].out_uop.rob_idx \n connect issue_slots[14].in_uop.bits.fp_ctrl.vec, issue_slots[15].out_uop.fp_ctrl.vec \n connect issue_slots[14].in_uop.bits.fp_ctrl.wflags, issue_slots[15].out_uop.fp_ctrl.wflags \n connect issue_slots[14].in_uop.bits.fp_ctrl.sqrt, issue_slots[15].out_uop.fp_ctrl.sqrt \n connect issue_slots[14].in_uop.bits.fp_ctrl.div, issue_slots[15].out_uop.fp_ctrl.div \n connect issue_slots[14].in_uop.bits.fp_ctrl.fma, issue_slots[15].out_uop.fp_ctrl.fma \n connect issue_slots[14].in_uop.bits.fp_ctrl.fastpipe, issue_slots[15].out_uop.fp_ctrl.fastpipe \n connect issue_slots[14].in_uop.bits.fp_ctrl.toint, issue_slots[15].out_uop.fp_ctrl.toint \n connect issue_slots[14].in_uop.bits.fp_ctrl.fromint, issue_slots[15].out_uop.fp_ctrl.fromint \n connect issue_slots[14].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[15].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[14].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[15].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[14].in_uop.bits.fp_ctrl.swap23, issue_slots[15].out_uop.fp_ctrl.swap23 \n connect issue_slots[14].in_uop.bits.fp_ctrl.swap12, issue_slots[15].out_uop.fp_ctrl.swap12 \n connect issue_slots[14].in_uop.bits.fp_ctrl.ren3, issue_slots[15].out_uop.fp_ctrl.ren3 \n connect issue_slots[14].in_uop.bits.fp_ctrl.ren2, issue_slots[15].out_uop.fp_ctrl.ren2 \n connect issue_slots[14].in_uop.bits.fp_ctrl.ren1, issue_slots[15].out_uop.fp_ctrl.ren1 \n connect issue_slots[14].in_uop.bits.fp_ctrl.wen, issue_slots[15].out_uop.fp_ctrl.wen \n connect issue_slots[14].in_uop.bits.fp_ctrl.ldst, issue_slots[15].out_uop.fp_ctrl.ldst \n connect issue_slots[14].in_uop.bits.op2_sel, issue_slots[15].out_uop.op2_sel \n connect issue_slots[14].in_uop.bits.op1_sel, issue_slots[15].out_uop.op1_sel \n connect issue_slots[14].in_uop.bits.imm_packed, issue_slots[15].out_uop.imm_packed \n connect issue_slots[14].in_uop.bits.pimm, issue_slots[15].out_uop.pimm \n connect issue_slots[14].in_uop.bits.imm_sel, issue_slots[15].out_uop.imm_sel \n connect issue_slots[14].in_uop.bits.imm_rename, issue_slots[15].out_uop.imm_rename \n connect issue_slots[14].in_uop.bits.taken, issue_slots[15].out_uop.taken \n connect issue_slots[14].in_uop.bits.pc_lob, issue_slots[15].out_uop.pc_lob \n connect issue_slots[14].in_uop.bits.edge_inst, issue_slots[15].out_uop.edge_inst \n connect issue_slots[14].in_uop.bits.ftq_idx, issue_slots[15].out_uop.ftq_idx \n connect issue_slots[14].in_uop.bits.is_mov, issue_slots[15].out_uop.is_mov \n connect issue_slots[14].in_uop.bits.is_rocc, issue_slots[15].out_uop.is_rocc \n connect issue_slots[14].in_uop.bits.is_sys_pc2epc, issue_slots[15].out_uop.is_sys_pc2epc \n connect issue_slots[14].in_uop.bits.is_eret, issue_slots[15].out_uop.is_eret \n connect issue_slots[14].in_uop.bits.is_amo, issue_slots[15].out_uop.is_amo \n connect issue_slots[14].in_uop.bits.is_sfence, issue_slots[15].out_uop.is_sfence \n connect issue_slots[14].in_uop.bits.is_fencei, issue_slots[15].out_uop.is_fencei \n connect issue_slots[14].in_uop.bits.is_fence, issue_slots[15].out_uop.is_fence \n connect issue_slots[14].in_uop.bits.is_sfb, issue_slots[15].out_uop.is_sfb \n connect issue_slots[14].in_uop.bits.br_type, issue_slots[15].out_uop.br_type \n connect issue_slots[14].in_uop.bits.br_tag, issue_slots[15].out_uop.br_tag \n connect issue_slots[14].in_uop.bits.br_mask, issue_slots[15].out_uop.br_mask \n connect issue_slots[14].in_uop.bits.dis_col_sel, issue_slots[15].out_uop.dis_col_sel \n connect issue_slots[14].in_uop.bits.iw_p3_bypass_hint, issue_slots[15].out_uop.iw_p3_bypass_hint \n connect issue_slots[14].in_uop.bits.iw_p2_bypass_hint, issue_slots[15].out_uop.iw_p2_bypass_hint \n connect issue_slots[14].in_uop.bits.iw_p1_bypass_hint, issue_slots[15].out_uop.iw_p1_bypass_hint \n connect issue_slots[14].in_uop.bits.iw_p2_speculative_child, issue_slots[15].out_uop.iw_p2_speculative_child \n connect issue_slots[14].in_uop.bits.iw_p1_speculative_child, issue_slots[15].out_uop.iw_p1_speculative_child \n connect issue_slots[14].in_uop.bits.iw_issued_partial_dgen, issue_slots[15].out_uop.iw_issued_partial_dgen \n connect issue_slots[14].in_uop.bits.iw_issued_partial_agen, issue_slots[15].out_uop.iw_issued_partial_agen \n connect issue_slots[14].in_uop.bits.iw_issued, issue_slots[15].out_uop.iw_issued \n connect issue_slots[14].in_uop.bits.fu_code[0], issue_slots[15].out_uop.fu_code[0] \n connect issue_slots[14].in_uop.bits.fu_code[1], issue_slots[15].out_uop.fu_code[1] \n connect issue_slots[14].in_uop.bits.fu_code[2], issue_slots[15].out_uop.fu_code[2] \n connect issue_slots[14].in_uop.bits.fu_code[3], issue_slots[15].out_uop.fu_code[3] \n connect issue_slots[14].in_uop.bits.fu_code[4], issue_slots[15].out_uop.fu_code[4] \n connect issue_slots[14].in_uop.bits.fu_code[5], issue_slots[15].out_uop.fu_code[5] \n connect issue_slots[14].in_uop.bits.fu_code[6], issue_slots[15].out_uop.fu_code[6] \n connect issue_slots[14].in_uop.bits.fu_code[7], issue_slots[15].out_uop.fu_code[7] \n connect issue_slots[14].in_uop.bits.fu_code[8], issue_slots[15].out_uop.fu_code[8] \n connect issue_slots[14].in_uop.bits.fu_code[9], issue_slots[15].out_uop.fu_code[9] \n connect issue_slots[14].in_uop.bits.iq_type[0], issue_slots[15].out_uop.iq_type[0] \n connect issue_slots[14].in_uop.bits.iq_type[1], issue_slots[15].out_uop.iq_type[1] \n connect issue_slots[14].in_uop.bits.iq_type[2], issue_slots[15].out_uop.iq_type[2] \n connect issue_slots[14].in_uop.bits.iq_type[3], issue_slots[15].out_uop.iq_type[3] \n connect issue_slots[14].in_uop.bits.debug_pc, issue_slots[15].out_uop.debug_pc \n connect issue_slots[14].in_uop.bits.is_rvc, issue_slots[15].out_uop.is_rvc \n connect issue_slots[14].in_uop.bits.debug_inst, issue_slots[15].out_uop.debug_inst \n connect issue_slots[14].in_uop.bits.inst, issue_slots[15].out_uop.inst \n node _T_191 = eq(shamts_oh[16], UInt<2>(0h2)) \n when _T_191 : \n connect issue_slots[14].in_uop.valid, issue_slots[16].will_be_valid \n connect issue_slots[14].in_uop.bits.debug_tsrc, issue_slots[16].out_uop.debug_tsrc \n connect issue_slots[14].in_uop.bits.debug_fsrc, issue_slots[16].out_uop.debug_fsrc \n connect issue_slots[14].in_uop.bits.bp_xcpt_if, issue_slots[16].out_uop.bp_xcpt_if \n connect issue_slots[14].in_uop.bits.bp_debug_if, issue_slots[16].out_uop.bp_debug_if \n connect issue_slots[14].in_uop.bits.xcpt_ma_if, issue_slots[16].out_uop.xcpt_ma_if \n connect issue_slots[14].in_uop.bits.xcpt_ae_if, issue_slots[16].out_uop.xcpt_ae_if \n connect issue_slots[14].in_uop.bits.xcpt_pf_if, issue_slots[16].out_uop.xcpt_pf_if \n connect issue_slots[14].in_uop.bits.fp_typ, issue_slots[16].out_uop.fp_typ \n connect issue_slots[14].in_uop.bits.fp_rm, issue_slots[16].out_uop.fp_rm \n connect issue_slots[14].in_uop.bits.fp_val, issue_slots[16].out_uop.fp_val \n connect issue_slots[14].in_uop.bits.fcn_op, issue_slots[16].out_uop.fcn_op \n connect issue_slots[14].in_uop.bits.fcn_dw, issue_slots[16].out_uop.fcn_dw \n connect issue_slots[14].in_uop.bits.frs3_en, issue_slots[16].out_uop.frs3_en \n connect issue_slots[14].in_uop.bits.lrs2_rtype, issue_slots[16].out_uop.lrs2_rtype \n connect issue_slots[14].in_uop.bits.lrs1_rtype, issue_slots[16].out_uop.lrs1_rtype \n connect issue_slots[14].in_uop.bits.dst_rtype, issue_slots[16].out_uop.dst_rtype \n connect issue_slots[14].in_uop.bits.lrs3, issue_slots[16].out_uop.lrs3 \n connect issue_slots[14].in_uop.bits.lrs2, issue_slots[16].out_uop.lrs2 \n connect issue_slots[14].in_uop.bits.lrs1, issue_slots[16].out_uop.lrs1 \n connect issue_slots[14].in_uop.bits.ldst, issue_slots[16].out_uop.ldst \n connect issue_slots[14].in_uop.bits.ldst_is_rs1, issue_slots[16].out_uop.ldst_is_rs1 \n connect issue_slots[14].in_uop.bits.csr_cmd, issue_slots[16].out_uop.csr_cmd \n connect issue_slots[14].in_uop.bits.flush_on_commit, issue_slots[16].out_uop.flush_on_commit \n connect issue_slots[14].in_uop.bits.is_unique, issue_slots[16].out_uop.is_unique \n connect issue_slots[14].in_uop.bits.uses_stq, issue_slots[16].out_uop.uses_stq \n connect issue_slots[14].in_uop.bits.uses_ldq, issue_slots[16].out_uop.uses_ldq \n connect issue_slots[14].in_uop.bits.mem_signed, issue_slots[16].out_uop.mem_signed \n connect issue_slots[14].in_uop.bits.mem_size, issue_slots[16].out_uop.mem_size \n connect issue_slots[14].in_uop.bits.mem_cmd, issue_slots[16].out_uop.mem_cmd \n connect issue_slots[14].in_uop.bits.exc_cause, issue_slots[16].out_uop.exc_cause \n connect issue_slots[14].in_uop.bits.exception, issue_slots[16].out_uop.exception \n connect issue_slots[14].in_uop.bits.stale_pdst, issue_slots[16].out_uop.stale_pdst \n connect issue_slots[14].in_uop.bits.ppred_busy, issue_slots[16].out_uop.ppred_busy \n connect issue_slots[14].in_uop.bits.prs3_busy, issue_slots[16].out_uop.prs3_busy \n connect issue_slots[14].in_uop.bits.prs2_busy, issue_slots[16].out_uop.prs2_busy \n connect issue_slots[14].in_uop.bits.prs1_busy, issue_slots[16].out_uop.prs1_busy \n connect issue_slots[14].in_uop.bits.ppred, issue_slots[16].out_uop.ppred \n connect issue_slots[14].in_uop.bits.prs3, issue_slots[16].out_uop.prs3 \n connect issue_slots[14].in_uop.bits.prs2, issue_slots[16].out_uop.prs2 \n connect issue_slots[14].in_uop.bits.prs1, issue_slots[16].out_uop.prs1 \n connect issue_slots[14].in_uop.bits.pdst, issue_slots[16].out_uop.pdst \n connect issue_slots[14].in_uop.bits.rxq_idx, issue_slots[16].out_uop.rxq_idx \n connect issue_slots[14].in_uop.bits.stq_idx, issue_slots[16].out_uop.stq_idx \n connect issue_slots[14].in_uop.bits.ldq_idx, issue_slots[16].out_uop.ldq_idx \n connect issue_slots[14].in_uop.bits.rob_idx, issue_slots[16].out_uop.rob_idx \n connect issue_slots[14].in_uop.bits.fp_ctrl.vec, issue_slots[16].out_uop.fp_ctrl.vec \n connect issue_slots[14].in_uop.bits.fp_ctrl.wflags, issue_slots[16].out_uop.fp_ctrl.wflags \n connect issue_slots[14].in_uop.bits.fp_ctrl.sqrt, issue_slots[16].out_uop.fp_ctrl.sqrt \n connect issue_slots[14].in_uop.bits.fp_ctrl.div, issue_slots[16].out_uop.fp_ctrl.div \n connect issue_slots[14].in_uop.bits.fp_ctrl.fma, issue_slots[16].out_uop.fp_ctrl.fma \n connect issue_slots[14].in_uop.bits.fp_ctrl.fastpipe, issue_slots[16].out_uop.fp_ctrl.fastpipe \n connect issue_slots[14].in_uop.bits.fp_ctrl.toint, issue_slots[16].out_uop.fp_ctrl.toint \n connect issue_slots[14].in_uop.bits.fp_ctrl.fromint, issue_slots[16].out_uop.fp_ctrl.fromint \n connect issue_slots[14].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[16].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[14].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[16].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[14].in_uop.bits.fp_ctrl.swap23, issue_slots[16].out_uop.fp_ctrl.swap23 \n connect issue_slots[14].in_uop.bits.fp_ctrl.swap12, issue_slots[16].out_uop.fp_ctrl.swap12 \n connect issue_slots[14].in_uop.bits.fp_ctrl.ren3, issue_slots[16].out_uop.fp_ctrl.ren3 \n connect issue_slots[14].in_uop.bits.fp_ctrl.ren2, issue_slots[16].out_uop.fp_ctrl.ren2 \n connect issue_slots[14].in_uop.bits.fp_ctrl.ren1, issue_slots[16].out_uop.fp_ctrl.ren1 \n connect issue_slots[14].in_uop.bits.fp_ctrl.wen, issue_slots[16].out_uop.fp_ctrl.wen \n connect issue_slots[14].in_uop.bits.fp_ctrl.ldst, issue_slots[16].out_uop.fp_ctrl.ldst \n connect issue_slots[14].in_uop.bits.op2_sel, issue_slots[16].out_uop.op2_sel \n connect issue_slots[14].in_uop.bits.op1_sel, issue_slots[16].out_uop.op1_sel \n connect issue_slots[14].in_uop.bits.imm_packed, issue_slots[16].out_uop.imm_packed \n connect issue_slots[14].in_uop.bits.pimm, issue_slots[16].out_uop.pimm \n connect issue_slots[14].in_uop.bits.imm_sel, issue_slots[16].out_uop.imm_sel \n connect issue_slots[14].in_uop.bits.imm_rename, issue_slots[16].out_uop.imm_rename \n connect issue_slots[14].in_uop.bits.taken, issue_slots[16].out_uop.taken \n connect issue_slots[14].in_uop.bits.pc_lob, issue_slots[16].out_uop.pc_lob \n connect issue_slots[14].in_uop.bits.edge_inst, issue_slots[16].out_uop.edge_inst \n connect issue_slots[14].in_uop.bits.ftq_idx, issue_slots[16].out_uop.ftq_idx \n connect issue_slots[14].in_uop.bits.is_mov, issue_slots[16].out_uop.is_mov \n connect issue_slots[14].in_uop.bits.is_rocc, issue_slots[16].out_uop.is_rocc \n connect issue_slots[14].in_uop.bits.is_sys_pc2epc, issue_slots[16].out_uop.is_sys_pc2epc \n connect issue_slots[14].in_uop.bits.is_eret, issue_slots[16].out_uop.is_eret \n connect issue_slots[14].in_uop.bits.is_amo, issue_slots[16].out_uop.is_amo \n connect issue_slots[14].in_uop.bits.is_sfence, issue_slots[16].out_uop.is_sfence \n connect issue_slots[14].in_uop.bits.is_fencei, issue_slots[16].out_uop.is_fencei \n connect issue_slots[14].in_uop.bits.is_fence, issue_slots[16].out_uop.is_fence \n connect issue_slots[14].in_uop.bits.is_sfb, issue_slots[16].out_uop.is_sfb \n connect issue_slots[14].in_uop.bits.br_type, issue_slots[16].out_uop.br_type \n connect issue_slots[14].in_uop.bits.br_tag, issue_slots[16].out_uop.br_tag \n connect issue_slots[14].in_uop.bits.br_mask, issue_slots[16].out_uop.br_mask \n connect issue_slots[14].in_uop.bits.dis_col_sel, issue_slots[16].out_uop.dis_col_sel \n connect issue_slots[14].in_uop.bits.iw_p3_bypass_hint, issue_slots[16].out_uop.iw_p3_bypass_hint \n connect issue_slots[14].in_uop.bits.iw_p2_bypass_hint, issue_slots[16].out_uop.iw_p2_bypass_hint \n connect issue_slots[14].in_uop.bits.iw_p1_bypass_hint, issue_slots[16].out_uop.iw_p1_bypass_hint \n connect issue_slots[14].in_uop.bits.iw_p2_speculative_child, issue_slots[16].out_uop.iw_p2_speculative_child \n connect issue_slots[14].in_uop.bits.iw_p1_speculative_child, issue_slots[16].out_uop.iw_p1_speculative_child \n connect issue_slots[14].in_uop.bits.iw_issued_partial_dgen, issue_slots[16].out_uop.iw_issued_partial_dgen \n connect issue_slots[14].in_uop.bits.iw_issued_partial_agen, issue_slots[16].out_uop.iw_issued_partial_agen \n connect issue_slots[14].in_uop.bits.iw_issued, issue_slots[16].out_uop.iw_issued \n connect issue_slots[14].in_uop.bits.fu_code[0], issue_slots[16].out_uop.fu_code[0] \n connect issue_slots[14].in_uop.bits.fu_code[1], issue_slots[16].out_uop.fu_code[1] \n connect issue_slots[14].in_uop.bits.fu_code[2], issue_slots[16].out_uop.fu_code[2] \n connect issue_slots[14].in_uop.bits.fu_code[3], issue_slots[16].out_uop.fu_code[3] \n connect issue_slots[14].in_uop.bits.fu_code[4], issue_slots[16].out_uop.fu_code[4] \n connect issue_slots[14].in_uop.bits.fu_code[5], issue_slots[16].out_uop.fu_code[5] \n connect issue_slots[14].in_uop.bits.fu_code[6], issue_slots[16].out_uop.fu_code[6] \n connect issue_slots[14].in_uop.bits.fu_code[7], issue_slots[16].out_uop.fu_code[7] \n connect issue_slots[14].in_uop.bits.fu_code[8], issue_slots[16].out_uop.fu_code[8] \n connect issue_slots[14].in_uop.bits.fu_code[9], issue_slots[16].out_uop.fu_code[9] \n connect issue_slots[14].in_uop.bits.iq_type[0], issue_slots[16].out_uop.iq_type[0] \n connect issue_slots[14].in_uop.bits.iq_type[1], issue_slots[16].out_uop.iq_type[1] \n connect issue_slots[14].in_uop.bits.iq_type[2], issue_slots[16].out_uop.iq_type[2] \n connect issue_slots[14].in_uop.bits.iq_type[3], issue_slots[16].out_uop.iq_type[3] \n connect issue_slots[14].in_uop.bits.debug_pc, issue_slots[16].out_uop.debug_pc \n connect issue_slots[14].in_uop.bits.is_rvc, issue_slots[16].out_uop.is_rvc \n connect issue_slots[14].in_uop.bits.debug_inst, issue_slots[16].out_uop.debug_inst \n connect issue_slots[14].in_uop.bits.inst, issue_slots[16].out_uop.inst \n node _issue_slots_14_clear_T = neq(shamts_oh[14], UInt<1>(0h0)) \n connect issue_slots[14].clear, _issue_slots_14_clear_T \n connect issue_slots[15].in_uop.valid, UInt<1>(0h0) \n connect issue_slots[15].in_uop.bits.debug_tsrc, issue_slots[16].out_uop.debug_tsrc \n connect issue_slots[15].in_uop.bits.debug_fsrc, issue_slots[16].out_uop.debug_fsrc \n connect issue_slots[15].in_uop.bits.bp_xcpt_if, issue_slots[16].out_uop.bp_xcpt_if \n connect issue_slots[15].in_uop.bits.bp_debug_if, issue_slots[16].out_uop.bp_debug_if \n connect issue_slots[15].in_uop.bits.xcpt_ma_if, issue_slots[16].out_uop.xcpt_ma_if \n connect issue_slots[15].in_uop.bits.xcpt_ae_if, issue_slots[16].out_uop.xcpt_ae_if \n connect issue_slots[15].in_uop.bits.xcpt_pf_if, issue_slots[16].out_uop.xcpt_pf_if \n connect issue_slots[15].in_uop.bits.fp_typ, issue_slots[16].out_uop.fp_typ \n connect issue_slots[15].in_uop.bits.fp_rm, issue_slots[16].out_uop.fp_rm \n connect issue_slots[15].in_uop.bits.fp_val, issue_slots[16].out_uop.fp_val \n connect issue_slots[15].in_uop.bits.fcn_op, issue_slots[16].out_uop.fcn_op \n connect issue_slots[15].in_uop.bits.fcn_dw, issue_slots[16].out_uop.fcn_dw \n connect issue_slots[15].in_uop.bits.frs3_en, issue_slots[16].out_uop.frs3_en \n connect issue_slots[15].in_uop.bits.lrs2_rtype, issue_slots[16].out_uop.lrs2_rtype \n connect issue_slots[15].in_uop.bits.lrs1_rtype, issue_slots[16].out_uop.lrs1_rtype \n connect issue_slots[15].in_uop.bits.dst_rtype, issue_slots[16].out_uop.dst_rtype \n connect issue_slots[15].in_uop.bits.lrs3, issue_slots[16].out_uop.lrs3 \n connect issue_slots[15].in_uop.bits.lrs2, issue_slots[16].out_uop.lrs2 \n connect issue_slots[15].in_uop.bits.lrs1, issue_slots[16].out_uop.lrs1 \n connect issue_slots[15].in_uop.bits.ldst, issue_slots[16].out_uop.ldst \n connect issue_slots[15].in_uop.bits.ldst_is_rs1, issue_slots[16].out_uop.ldst_is_rs1 \n connect issue_slots[15].in_uop.bits.csr_cmd, issue_slots[16].out_uop.csr_cmd \n connect issue_slots[15].in_uop.bits.flush_on_commit, issue_slots[16].out_uop.flush_on_commit \n connect issue_slots[15].in_uop.bits.is_unique, issue_slots[16].out_uop.is_unique \n connect issue_slots[15].in_uop.bits.uses_stq, issue_slots[16].out_uop.uses_stq \n connect issue_slots[15].in_uop.bits.uses_ldq, issue_slots[16].out_uop.uses_ldq \n connect issue_slots[15].in_uop.bits.mem_signed, issue_slots[16].out_uop.mem_signed \n connect issue_slots[15].in_uop.bits.mem_size, issue_slots[16].out_uop.mem_size \n connect issue_slots[15].in_uop.bits.mem_cmd, issue_slots[16].out_uop.mem_cmd \n connect issue_slots[15].in_uop.bits.exc_cause, issue_slots[16].out_uop.exc_cause \n connect issue_slots[15].in_uop.bits.exception, issue_slots[16].out_uop.exception \n connect issue_slots[15].in_uop.bits.stale_pdst, issue_slots[16].out_uop.stale_pdst \n connect issue_slots[15].in_uop.bits.ppred_busy, issue_slots[16].out_uop.ppred_busy \n connect issue_slots[15].in_uop.bits.prs3_busy, issue_slots[16].out_uop.prs3_busy \n connect issue_slots[15].in_uop.bits.prs2_busy, issue_slots[16].out_uop.prs2_busy \n connect issue_slots[15].in_uop.bits.prs1_busy, issue_slots[16].out_uop.prs1_busy \n connect issue_slots[15].in_uop.bits.ppred, issue_slots[16].out_uop.ppred \n connect issue_slots[15].in_uop.bits.prs3, issue_slots[16].out_uop.prs3 \n connect issue_slots[15].in_uop.bits.prs2, issue_slots[16].out_uop.prs2 \n connect issue_slots[15].in_uop.bits.prs1, issue_slots[16].out_uop.prs1 \n connect issue_slots[15].in_uop.bits.pdst, issue_slots[16].out_uop.pdst \n connect issue_slots[15].in_uop.bits.rxq_idx, issue_slots[16].out_uop.rxq_idx \n connect issue_slots[15].in_uop.bits.stq_idx, issue_slots[16].out_uop.stq_idx \n connect issue_slots[15].in_uop.bits.ldq_idx, issue_slots[16].out_uop.ldq_idx \n connect issue_slots[15].in_uop.bits.rob_idx, issue_slots[16].out_uop.rob_idx \n connect issue_slots[15].in_uop.bits.fp_ctrl.vec, issue_slots[16].out_uop.fp_ctrl.vec \n connect issue_slots[15].in_uop.bits.fp_ctrl.wflags, issue_slots[16].out_uop.fp_ctrl.wflags \n connect issue_slots[15].in_uop.bits.fp_ctrl.sqrt, issue_slots[16].out_uop.fp_ctrl.sqrt \n connect issue_slots[15].in_uop.bits.fp_ctrl.div, issue_slots[16].out_uop.fp_ctrl.div \n connect issue_slots[15].in_uop.bits.fp_ctrl.fma, issue_slots[16].out_uop.fp_ctrl.fma \n connect issue_slots[15].in_uop.bits.fp_ctrl.fastpipe, issue_slots[16].out_uop.fp_ctrl.fastpipe \n connect issue_slots[15].in_uop.bits.fp_ctrl.toint, issue_slots[16].out_uop.fp_ctrl.toint \n connect issue_slots[15].in_uop.bits.fp_ctrl.fromint, issue_slots[16].out_uop.fp_ctrl.fromint \n connect issue_slots[15].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[16].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[15].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[16].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[15].in_uop.bits.fp_ctrl.swap23, issue_slots[16].out_uop.fp_ctrl.swap23 \n connect issue_slots[15].in_uop.bits.fp_ctrl.swap12, issue_slots[16].out_uop.fp_ctrl.swap12 \n connect issue_slots[15].in_uop.bits.fp_ctrl.ren3, issue_slots[16].out_uop.fp_ctrl.ren3 \n connect issue_slots[15].in_uop.bits.fp_ctrl.ren2, issue_slots[16].out_uop.fp_ctrl.ren2 \n connect issue_slots[15].in_uop.bits.fp_ctrl.ren1, issue_slots[16].out_uop.fp_ctrl.ren1 \n connect issue_slots[15].in_uop.bits.fp_ctrl.wen, issue_slots[16].out_uop.fp_ctrl.wen \n connect issue_slots[15].in_uop.bits.fp_ctrl.ldst, issue_slots[16].out_uop.fp_ctrl.ldst \n connect issue_slots[15].in_uop.bits.op2_sel, issue_slots[16].out_uop.op2_sel \n connect issue_slots[15].in_uop.bits.op1_sel, issue_slots[16].out_uop.op1_sel \n connect issue_slots[15].in_uop.bits.imm_packed, issue_slots[16].out_uop.imm_packed \n connect issue_slots[15].in_uop.bits.pimm, issue_slots[16].out_uop.pimm \n connect issue_slots[15].in_uop.bits.imm_sel, issue_slots[16].out_uop.imm_sel \n connect issue_slots[15].in_uop.bits.imm_rename, issue_slots[16].out_uop.imm_rename \n connect issue_slots[15].in_uop.bits.taken, issue_slots[16].out_uop.taken \n connect issue_slots[15].in_uop.bits.pc_lob, issue_slots[16].out_uop.pc_lob \n connect issue_slots[15].in_uop.bits.edge_inst, issue_slots[16].out_uop.edge_inst \n connect issue_slots[15].in_uop.bits.ftq_idx, issue_slots[16].out_uop.ftq_idx \n connect issue_slots[15].in_uop.bits.is_mov, issue_slots[16].out_uop.is_mov \n connect issue_slots[15].in_uop.bits.is_rocc, issue_slots[16].out_uop.is_rocc \n connect issue_slots[15].in_uop.bits.is_sys_pc2epc, issue_slots[16].out_uop.is_sys_pc2epc \n connect issue_slots[15].in_uop.bits.is_eret, issue_slots[16].out_uop.is_eret \n connect issue_slots[15].in_uop.bits.is_amo, issue_slots[16].out_uop.is_amo \n connect issue_slots[15].in_uop.bits.is_sfence, issue_slots[16].out_uop.is_sfence \n connect issue_slots[15].in_uop.bits.is_fencei, issue_slots[16].out_uop.is_fencei \n connect issue_slots[15].in_uop.bits.is_fence, issue_slots[16].out_uop.is_fence \n connect issue_slots[15].in_uop.bits.is_sfb, issue_slots[16].out_uop.is_sfb \n connect issue_slots[15].in_uop.bits.br_type, issue_slots[16].out_uop.br_type \n connect issue_slots[15].in_uop.bits.br_tag, issue_slots[16].out_uop.br_tag \n connect issue_slots[15].in_uop.bits.br_mask, issue_slots[16].out_uop.br_mask \n connect issue_slots[15].in_uop.bits.dis_col_sel, issue_slots[16].out_uop.dis_col_sel \n connect issue_slots[15].in_uop.bits.iw_p3_bypass_hint, issue_slots[16].out_uop.iw_p3_bypass_hint \n connect issue_slots[15].in_uop.bits.iw_p2_bypass_hint, issue_slots[16].out_uop.iw_p2_bypass_hint \n connect issue_slots[15].in_uop.bits.iw_p1_bypass_hint, issue_slots[16].out_uop.iw_p1_bypass_hint \n connect issue_slots[15].in_uop.bits.iw_p2_speculative_child, issue_slots[16].out_uop.iw_p2_speculative_child \n connect issue_slots[15].in_uop.bits.iw_p1_speculative_child, issue_slots[16].out_uop.iw_p1_speculative_child \n connect issue_slots[15].in_uop.bits.iw_issued_partial_dgen, issue_slots[16].out_uop.iw_issued_partial_dgen \n connect issue_slots[15].in_uop.bits.iw_issued_partial_agen, issue_slots[16].out_uop.iw_issued_partial_agen \n connect issue_slots[15].in_uop.bits.iw_issued, issue_slots[16].out_uop.iw_issued \n connect issue_slots[15].in_uop.bits.fu_code[0], issue_slots[16].out_uop.fu_code[0] \n connect issue_slots[15].in_uop.bits.fu_code[1], issue_slots[16].out_uop.fu_code[1] \n connect issue_slots[15].in_uop.bits.fu_code[2], issue_slots[16].out_uop.fu_code[2] \n connect issue_slots[15].in_uop.bits.fu_code[3], issue_slots[16].out_uop.fu_code[3] \n connect issue_slots[15].in_uop.bits.fu_code[4], issue_slots[16].out_uop.fu_code[4] \n connect issue_slots[15].in_uop.bits.fu_code[5], issue_slots[16].out_uop.fu_code[5] \n connect issue_slots[15].in_uop.bits.fu_code[6], issue_slots[16].out_uop.fu_code[6] \n connect issue_slots[15].in_uop.bits.fu_code[7], issue_slots[16].out_uop.fu_code[7] \n connect issue_slots[15].in_uop.bits.fu_code[8], issue_slots[16].out_uop.fu_code[8] \n connect issue_slots[15].in_uop.bits.fu_code[9], issue_slots[16].out_uop.fu_code[9] \n connect issue_slots[15].in_uop.bits.iq_type[0], issue_slots[16].out_uop.iq_type[0] \n connect issue_slots[15].in_uop.bits.iq_type[1], issue_slots[16].out_uop.iq_type[1] \n connect issue_slots[15].in_uop.bits.iq_type[2], issue_slots[16].out_uop.iq_type[2] \n connect issue_slots[15].in_uop.bits.iq_type[3], issue_slots[16].out_uop.iq_type[3] \n connect issue_slots[15].in_uop.bits.debug_pc, issue_slots[16].out_uop.debug_pc \n connect issue_slots[15].in_uop.bits.is_rvc, issue_slots[16].out_uop.is_rvc \n connect issue_slots[15].in_uop.bits.debug_inst, issue_slots[16].out_uop.debug_inst \n connect issue_slots[15].in_uop.bits.inst, issue_slots[16].out_uop.inst \n node _T_192 = eq(shamts_oh[16], UInt<1>(0h1)) \n when _T_192 : \n connect issue_slots[15].in_uop.valid, issue_slots[16].will_be_valid \n connect issue_slots[15].in_uop.bits.debug_tsrc, issue_slots[16].out_uop.debug_tsrc \n connect issue_slots[15].in_uop.bits.debug_fsrc, issue_slots[16].out_uop.debug_fsrc \n connect issue_slots[15].in_uop.bits.bp_xcpt_if, issue_slots[16].out_uop.bp_xcpt_if \n connect issue_slots[15].in_uop.bits.bp_debug_if, issue_slots[16].out_uop.bp_debug_if \n connect issue_slots[15].in_uop.bits.xcpt_ma_if, issue_slots[16].out_uop.xcpt_ma_if \n connect issue_slots[15].in_uop.bits.xcpt_ae_if, issue_slots[16].out_uop.xcpt_ae_if \n connect issue_slots[15].in_uop.bits.xcpt_pf_if, issue_slots[16].out_uop.xcpt_pf_if \n connect issue_slots[15].in_uop.bits.fp_typ, issue_slots[16].out_uop.fp_typ \n connect issue_slots[15].in_uop.bits.fp_rm, issue_slots[16].out_uop.fp_rm \n connect issue_slots[15].in_uop.bits.fp_val, issue_slots[16].out_uop.fp_val \n connect issue_slots[15].in_uop.bits.fcn_op, issue_slots[16].out_uop.fcn_op \n connect issue_slots[15].in_uop.bits.fcn_dw, issue_slots[16].out_uop.fcn_dw \n connect issue_slots[15].in_uop.bits.frs3_en, issue_slots[16].out_uop.frs3_en \n connect issue_slots[15].in_uop.bits.lrs2_rtype, issue_slots[16].out_uop.lrs2_rtype \n connect issue_slots[15].in_uop.bits.lrs1_rtype, issue_slots[16].out_uop.lrs1_rtype \n connect issue_slots[15].in_uop.bits.dst_rtype, issue_slots[16].out_uop.dst_rtype \n connect issue_slots[15].in_uop.bits.lrs3, issue_slots[16].out_uop.lrs3 \n connect issue_slots[15].in_uop.bits.lrs2, issue_slots[16].out_uop.lrs2 \n connect issue_slots[15].in_uop.bits.lrs1, issue_slots[16].out_uop.lrs1 \n connect issue_slots[15].in_uop.bits.ldst, issue_slots[16].out_uop.ldst \n connect issue_slots[15].in_uop.bits.ldst_is_rs1, issue_slots[16].out_uop.ldst_is_rs1 \n connect issue_slots[15].in_uop.bits.csr_cmd, issue_slots[16].out_uop.csr_cmd \n connect issue_slots[15].in_uop.bits.flush_on_commit, issue_slots[16].out_uop.flush_on_commit \n connect issue_slots[15].in_uop.bits.is_unique, issue_slots[16].out_uop.is_unique \n connect issue_slots[15].in_uop.bits.uses_stq, issue_slots[16].out_uop.uses_stq \n connect issue_slots[15].in_uop.bits.uses_ldq, issue_slots[16].out_uop.uses_ldq \n connect issue_slots[15].in_uop.bits.mem_signed, issue_slots[16].out_uop.mem_signed \n connect issue_slots[15].in_uop.bits.mem_size, issue_slots[16].out_uop.mem_size \n connect issue_slots[15].in_uop.bits.mem_cmd, issue_slots[16].out_uop.mem_cmd \n connect issue_slots[15].in_uop.bits.exc_cause, issue_slots[16].out_uop.exc_cause \n connect issue_slots[15].in_uop.bits.exception, issue_slots[16].out_uop.exception \n connect issue_slots[15].in_uop.bits.stale_pdst, issue_slots[16].out_uop.stale_pdst \n connect issue_slots[15].in_uop.bits.ppred_busy, issue_slots[16].out_uop.ppred_busy \n connect issue_slots[15].in_uop.bits.prs3_busy, issue_slots[16].out_uop.prs3_busy \n connect issue_slots[15].in_uop.bits.prs2_busy, issue_slots[16].out_uop.prs2_busy \n connect issue_slots[15].in_uop.bits.prs1_busy, issue_slots[16].out_uop.prs1_busy \n connect issue_slots[15].in_uop.bits.ppred, issue_slots[16].out_uop.ppred \n connect issue_slots[15].in_uop.bits.prs3, issue_slots[16].out_uop.prs3 \n connect issue_slots[15].in_uop.bits.prs2, issue_slots[16].out_uop.prs2 \n connect issue_slots[15].in_uop.bits.prs1, issue_slots[16].out_uop.prs1 \n connect issue_slots[15].in_uop.bits.pdst, issue_slots[16].out_uop.pdst \n connect issue_slots[15].in_uop.bits.rxq_idx, issue_slots[16].out_uop.rxq_idx \n connect issue_slots[15].in_uop.bits.stq_idx, issue_slots[16].out_uop.stq_idx \n connect issue_slots[15].in_uop.bits.ldq_idx, issue_slots[16].out_uop.ldq_idx \n connect issue_slots[15].in_uop.bits.rob_idx, issue_slots[16].out_uop.rob_idx \n connect issue_slots[15].in_uop.bits.fp_ctrl.vec, issue_slots[16].out_uop.fp_ctrl.vec \n connect issue_slots[15].in_uop.bits.fp_ctrl.wflags, issue_slots[16].out_uop.fp_ctrl.wflags \n connect issue_slots[15].in_uop.bits.fp_ctrl.sqrt, issue_slots[16].out_uop.fp_ctrl.sqrt \n connect issue_slots[15].in_uop.bits.fp_ctrl.div, issue_slots[16].out_uop.fp_ctrl.div \n connect issue_slots[15].in_uop.bits.fp_ctrl.fma, issue_slots[16].out_uop.fp_ctrl.fma \n connect issue_slots[15].in_uop.bits.fp_ctrl.fastpipe, issue_slots[16].out_uop.fp_ctrl.fastpipe \n connect issue_slots[15].in_uop.bits.fp_ctrl.toint, issue_slots[16].out_uop.fp_ctrl.toint \n connect issue_slots[15].in_uop.bits.fp_ctrl.fromint, issue_slots[16].out_uop.fp_ctrl.fromint \n connect issue_slots[15].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[16].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[15].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[16].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[15].in_uop.bits.fp_ctrl.swap23, issue_slots[16].out_uop.fp_ctrl.swap23 \n connect issue_slots[15].in_uop.bits.fp_ctrl.swap12, issue_slots[16].out_uop.fp_ctrl.swap12 \n connect issue_slots[15].in_uop.bits.fp_ctrl.ren3, issue_slots[16].out_uop.fp_ctrl.ren3 \n connect issue_slots[15].in_uop.bits.fp_ctrl.ren2, issue_slots[16].out_uop.fp_ctrl.ren2 \n connect issue_slots[15].in_uop.bits.fp_ctrl.ren1, issue_slots[16].out_uop.fp_ctrl.ren1 \n connect issue_slots[15].in_uop.bits.fp_ctrl.wen, issue_slots[16].out_uop.fp_ctrl.wen \n connect issue_slots[15].in_uop.bits.fp_ctrl.ldst, issue_slots[16].out_uop.fp_ctrl.ldst \n connect issue_slots[15].in_uop.bits.op2_sel, issue_slots[16].out_uop.op2_sel \n connect issue_slots[15].in_uop.bits.op1_sel, issue_slots[16].out_uop.op1_sel \n connect issue_slots[15].in_uop.bits.imm_packed, issue_slots[16].out_uop.imm_packed \n connect issue_slots[15].in_uop.bits.pimm, issue_slots[16].out_uop.pimm \n connect issue_slots[15].in_uop.bits.imm_sel, issue_slots[16].out_uop.imm_sel \n connect issue_slots[15].in_uop.bits.imm_rename, issue_slots[16].out_uop.imm_rename \n connect issue_slots[15].in_uop.bits.taken, issue_slots[16].out_uop.taken \n connect issue_slots[15].in_uop.bits.pc_lob, issue_slots[16].out_uop.pc_lob \n connect issue_slots[15].in_uop.bits.edge_inst, issue_slots[16].out_uop.edge_inst \n connect issue_slots[15].in_uop.bits.ftq_idx, issue_slots[16].out_uop.ftq_idx \n connect issue_slots[15].in_uop.bits.is_mov, issue_slots[16].out_uop.is_mov \n connect issue_slots[15].in_uop.bits.is_rocc, issue_slots[16].out_uop.is_rocc \n connect issue_slots[15].in_uop.bits.is_sys_pc2epc, issue_slots[16].out_uop.is_sys_pc2epc \n connect issue_slots[15].in_uop.bits.is_eret, issue_slots[16].out_uop.is_eret \n connect issue_slots[15].in_uop.bits.is_amo, issue_slots[16].out_uop.is_amo \n connect issue_slots[15].in_uop.bits.is_sfence, issue_slots[16].out_uop.is_sfence \n connect issue_slots[15].in_uop.bits.is_fencei, issue_slots[16].out_uop.is_fencei \n connect issue_slots[15].in_uop.bits.is_fence, issue_slots[16].out_uop.is_fence \n connect issue_slots[15].in_uop.bits.is_sfb, issue_slots[16].out_uop.is_sfb \n connect issue_slots[15].in_uop.bits.br_type, issue_slots[16].out_uop.br_type \n connect issue_slots[15].in_uop.bits.br_tag, issue_slots[16].out_uop.br_tag \n connect issue_slots[15].in_uop.bits.br_mask, issue_slots[16].out_uop.br_mask \n connect issue_slots[15].in_uop.bits.dis_col_sel, issue_slots[16].out_uop.dis_col_sel \n connect issue_slots[15].in_uop.bits.iw_p3_bypass_hint, issue_slots[16].out_uop.iw_p3_bypass_hint \n connect issue_slots[15].in_uop.bits.iw_p2_bypass_hint, issue_slots[16].out_uop.iw_p2_bypass_hint \n connect issue_slots[15].in_uop.bits.iw_p1_bypass_hint, issue_slots[16].out_uop.iw_p1_bypass_hint \n connect issue_slots[15].in_uop.bits.iw_p2_speculative_child, issue_slots[16].out_uop.iw_p2_speculative_child \n connect issue_slots[15].in_uop.bits.iw_p1_speculative_child, issue_slots[16].out_uop.iw_p1_speculative_child \n connect issue_slots[15].in_uop.bits.iw_issued_partial_dgen, issue_slots[16].out_uop.iw_issued_partial_dgen \n connect issue_slots[15].in_uop.bits.iw_issued_partial_agen, issue_slots[16].out_uop.iw_issued_partial_agen \n connect issue_slots[15].in_uop.bits.iw_issued, issue_slots[16].out_uop.iw_issued \n connect issue_slots[15].in_uop.bits.fu_code[0], issue_slots[16].out_uop.fu_code[0] \n connect issue_slots[15].in_uop.bits.fu_code[1], issue_slots[16].out_uop.fu_code[1] \n connect issue_slots[15].in_uop.bits.fu_code[2], issue_slots[16].out_uop.fu_code[2] \n connect issue_slots[15].in_uop.bits.fu_code[3], issue_slots[16].out_uop.fu_code[3] \n connect issue_slots[15].in_uop.bits.fu_code[4], issue_slots[16].out_uop.fu_code[4] \n connect issue_slots[15].in_uop.bits.fu_code[5], issue_slots[16].out_uop.fu_code[5] \n connect issue_slots[15].in_uop.bits.fu_code[6], issue_slots[16].out_uop.fu_code[6] \n connect issue_slots[15].in_uop.bits.fu_code[7], issue_slots[16].out_uop.fu_code[7] \n connect issue_slots[15].in_uop.bits.fu_code[8], issue_slots[16].out_uop.fu_code[8] \n connect issue_slots[15].in_uop.bits.fu_code[9], issue_slots[16].out_uop.fu_code[9] \n connect issue_slots[15].in_uop.bits.iq_type[0], issue_slots[16].out_uop.iq_type[0] \n connect issue_slots[15].in_uop.bits.iq_type[1], issue_slots[16].out_uop.iq_type[1] \n connect issue_slots[15].in_uop.bits.iq_type[2], issue_slots[16].out_uop.iq_type[2] \n connect issue_slots[15].in_uop.bits.iq_type[3], issue_slots[16].out_uop.iq_type[3] \n connect issue_slots[15].in_uop.bits.debug_pc, issue_slots[16].out_uop.debug_pc \n connect issue_slots[15].in_uop.bits.is_rvc, issue_slots[16].out_uop.is_rvc \n connect issue_slots[15].in_uop.bits.debug_inst, issue_slots[16].out_uop.debug_inst \n connect issue_slots[15].in_uop.bits.inst, issue_slots[16].out_uop.inst \n node _T_193 = eq(shamts_oh[17], UInt<2>(0h2)) \n when _T_193 : \n connect issue_slots[15].in_uop.valid, issue_slots[17].will_be_valid \n connect issue_slots[15].in_uop.bits.debug_tsrc, issue_slots[17].out_uop.debug_tsrc \n connect issue_slots[15].in_uop.bits.debug_fsrc, issue_slots[17].out_uop.debug_fsrc \n connect issue_slots[15].in_uop.bits.bp_xcpt_if, issue_slots[17].out_uop.bp_xcpt_if \n connect issue_slots[15].in_uop.bits.bp_debug_if, issue_slots[17].out_uop.bp_debug_if \n connect issue_slots[15].in_uop.bits.xcpt_ma_if, issue_slots[17].out_uop.xcpt_ma_if \n connect issue_slots[15].in_uop.bits.xcpt_ae_if, issue_slots[17].out_uop.xcpt_ae_if \n connect issue_slots[15].in_uop.bits.xcpt_pf_if, issue_slots[17].out_uop.xcpt_pf_if \n connect issue_slots[15].in_uop.bits.fp_typ, issue_slots[17].out_uop.fp_typ \n connect issue_slots[15].in_uop.bits.fp_rm, issue_slots[17].out_uop.fp_rm \n connect issue_slots[15].in_uop.bits.fp_val, issue_slots[17].out_uop.fp_val \n connect issue_slots[15].in_uop.bits.fcn_op, issue_slots[17].out_uop.fcn_op \n connect issue_slots[15].in_uop.bits.fcn_dw, issue_slots[17].out_uop.fcn_dw \n connect issue_slots[15].in_uop.bits.frs3_en, issue_slots[17].out_uop.frs3_en \n connect issue_slots[15].in_uop.bits.lrs2_rtype, issue_slots[17].out_uop.lrs2_rtype \n connect issue_slots[15].in_uop.bits.lrs1_rtype, issue_slots[17].out_uop.lrs1_rtype \n connect issue_slots[15].in_uop.bits.dst_rtype, issue_slots[17].out_uop.dst_rtype \n connect issue_slots[15].in_uop.bits.lrs3, issue_slots[17].out_uop.lrs3 \n connect issue_slots[15].in_uop.bits.lrs2, issue_slots[17].out_uop.lrs2 \n connect issue_slots[15].in_uop.bits.lrs1, issue_slots[17].out_uop.lrs1 \n connect issue_slots[15].in_uop.bits.ldst, issue_slots[17].out_uop.ldst \n connect issue_slots[15].in_uop.bits.ldst_is_rs1, issue_slots[17].out_uop.ldst_is_rs1 \n connect issue_slots[15].in_uop.bits.csr_cmd, issue_slots[17].out_uop.csr_cmd \n connect issue_slots[15].in_uop.bits.flush_on_commit, issue_slots[17].out_uop.flush_on_commit \n connect issue_slots[15].in_uop.bits.is_unique, issue_slots[17].out_uop.is_unique \n connect issue_slots[15].in_uop.bits.uses_stq, issue_slots[17].out_uop.uses_stq \n connect issue_slots[15].in_uop.bits.uses_ldq, issue_slots[17].out_uop.uses_ldq \n connect issue_slots[15].in_uop.bits.mem_signed, issue_slots[17].out_uop.mem_signed \n connect issue_slots[15].in_uop.bits.mem_size, issue_slots[17].out_uop.mem_size \n connect issue_slots[15].in_uop.bits.mem_cmd, issue_slots[17].out_uop.mem_cmd \n connect issue_slots[15].in_uop.bits.exc_cause, issue_slots[17].out_uop.exc_cause \n connect issue_slots[15].in_uop.bits.exception, issue_slots[17].out_uop.exception \n connect issue_slots[15].in_uop.bits.stale_pdst, issue_slots[17].out_uop.stale_pdst \n connect issue_slots[15].in_uop.bits.ppred_busy, issue_slots[17].out_uop.ppred_busy \n connect issue_slots[15].in_uop.bits.prs3_busy, issue_slots[17].out_uop.prs3_busy \n connect issue_slots[15].in_uop.bits.prs2_busy, issue_slots[17].out_uop.prs2_busy \n connect issue_slots[15].in_uop.bits.prs1_busy, issue_slots[17].out_uop.prs1_busy \n connect issue_slots[15].in_uop.bits.ppred, issue_slots[17].out_uop.ppred \n connect issue_slots[15].in_uop.bits.prs3, issue_slots[17].out_uop.prs3 \n connect issue_slots[15].in_uop.bits.prs2, issue_slots[17].out_uop.prs2 \n connect issue_slots[15].in_uop.bits.prs1, issue_slots[17].out_uop.prs1 \n connect issue_slots[15].in_uop.bits.pdst, issue_slots[17].out_uop.pdst \n connect issue_slots[15].in_uop.bits.rxq_idx, issue_slots[17].out_uop.rxq_idx \n connect issue_slots[15].in_uop.bits.stq_idx, issue_slots[17].out_uop.stq_idx \n connect issue_slots[15].in_uop.bits.ldq_idx, issue_slots[17].out_uop.ldq_idx \n connect issue_slots[15].in_uop.bits.rob_idx, issue_slots[17].out_uop.rob_idx \n connect issue_slots[15].in_uop.bits.fp_ctrl.vec, issue_slots[17].out_uop.fp_ctrl.vec \n connect issue_slots[15].in_uop.bits.fp_ctrl.wflags, issue_slots[17].out_uop.fp_ctrl.wflags \n connect issue_slots[15].in_uop.bits.fp_ctrl.sqrt, issue_slots[17].out_uop.fp_ctrl.sqrt \n connect issue_slots[15].in_uop.bits.fp_ctrl.div, issue_slots[17].out_uop.fp_ctrl.div \n connect issue_slots[15].in_uop.bits.fp_ctrl.fma, issue_slots[17].out_uop.fp_ctrl.fma \n connect issue_slots[15].in_uop.bits.fp_ctrl.fastpipe, issue_slots[17].out_uop.fp_ctrl.fastpipe \n connect issue_slots[15].in_uop.bits.fp_ctrl.toint, issue_slots[17].out_uop.fp_ctrl.toint \n connect issue_slots[15].in_uop.bits.fp_ctrl.fromint, issue_slots[17].out_uop.fp_ctrl.fromint \n connect issue_slots[15].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[17].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[15].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[17].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[15].in_uop.bits.fp_ctrl.swap23, issue_slots[17].out_uop.fp_ctrl.swap23 \n connect issue_slots[15].in_uop.bits.fp_ctrl.swap12, issue_slots[17].out_uop.fp_ctrl.swap12 \n connect issue_slots[15].in_uop.bits.fp_ctrl.ren3, issue_slots[17].out_uop.fp_ctrl.ren3 \n connect issue_slots[15].in_uop.bits.fp_ctrl.ren2, issue_slots[17].out_uop.fp_ctrl.ren2 \n connect issue_slots[15].in_uop.bits.fp_ctrl.ren1, issue_slots[17].out_uop.fp_ctrl.ren1 \n connect issue_slots[15].in_uop.bits.fp_ctrl.wen, issue_slots[17].out_uop.fp_ctrl.wen \n connect issue_slots[15].in_uop.bits.fp_ctrl.ldst, issue_slots[17].out_uop.fp_ctrl.ldst \n connect issue_slots[15].in_uop.bits.op2_sel, issue_slots[17].out_uop.op2_sel \n connect issue_slots[15].in_uop.bits.op1_sel, issue_slots[17].out_uop.op1_sel \n connect issue_slots[15].in_uop.bits.imm_packed, issue_slots[17].out_uop.imm_packed \n connect issue_slots[15].in_uop.bits.pimm, issue_slots[17].out_uop.pimm \n connect issue_slots[15].in_uop.bits.imm_sel, issue_slots[17].out_uop.imm_sel \n connect issue_slots[15].in_uop.bits.imm_rename, issue_slots[17].out_uop.imm_rename \n connect issue_slots[15].in_uop.bits.taken, issue_slots[17].out_uop.taken \n connect issue_slots[15].in_uop.bits.pc_lob, issue_slots[17].out_uop.pc_lob \n connect issue_slots[15].in_uop.bits.edge_inst, issue_slots[17].out_uop.edge_inst \n connect issue_slots[15].in_uop.bits.ftq_idx, issue_slots[17].out_uop.ftq_idx \n connect issue_slots[15].in_uop.bits.is_mov, issue_slots[17].out_uop.is_mov \n connect issue_slots[15].in_uop.bits.is_rocc, issue_slots[17].out_uop.is_rocc \n connect issue_slots[15].in_uop.bits.is_sys_pc2epc, issue_slots[17].out_uop.is_sys_pc2epc \n connect issue_slots[15].in_uop.bits.is_eret, issue_slots[17].out_uop.is_eret \n connect issue_slots[15].in_uop.bits.is_amo, issue_slots[17].out_uop.is_amo \n connect issue_slots[15].in_uop.bits.is_sfence, issue_slots[17].out_uop.is_sfence \n connect issue_slots[15].in_uop.bits.is_fencei, issue_slots[17].out_uop.is_fencei \n connect issue_slots[15].in_uop.bits.is_fence, issue_slots[17].out_uop.is_fence \n connect issue_slots[15].in_uop.bits.is_sfb, issue_slots[17].out_uop.is_sfb \n connect issue_slots[15].in_uop.bits.br_type, issue_slots[17].out_uop.br_type \n connect issue_slots[15].in_uop.bits.br_tag, issue_slots[17].out_uop.br_tag \n connect issue_slots[15].in_uop.bits.br_mask, issue_slots[17].out_uop.br_mask \n connect issue_slots[15].in_uop.bits.dis_col_sel, issue_slots[17].out_uop.dis_col_sel \n connect issue_slots[15].in_uop.bits.iw_p3_bypass_hint, issue_slots[17].out_uop.iw_p3_bypass_hint \n connect issue_slots[15].in_uop.bits.iw_p2_bypass_hint, issue_slots[17].out_uop.iw_p2_bypass_hint \n connect issue_slots[15].in_uop.bits.iw_p1_bypass_hint, issue_slots[17].out_uop.iw_p1_bypass_hint \n connect issue_slots[15].in_uop.bits.iw_p2_speculative_child, issue_slots[17].out_uop.iw_p2_speculative_child \n connect issue_slots[15].in_uop.bits.iw_p1_speculative_child, issue_slots[17].out_uop.iw_p1_speculative_child \n connect issue_slots[15].in_uop.bits.iw_issued_partial_dgen, issue_slots[17].out_uop.iw_issued_partial_dgen \n connect issue_slots[15].in_uop.bits.iw_issued_partial_agen, issue_slots[17].out_uop.iw_issued_partial_agen \n connect issue_slots[15].in_uop.bits.iw_issued, issue_slots[17].out_uop.iw_issued \n connect issue_slots[15].in_uop.bits.fu_code[0], issue_slots[17].out_uop.fu_code[0] \n connect issue_slots[15].in_uop.bits.fu_code[1], issue_slots[17].out_uop.fu_code[1] \n connect issue_slots[15].in_uop.bits.fu_code[2], issue_slots[17].out_uop.fu_code[2] \n connect issue_slots[15].in_uop.bits.fu_code[3], issue_slots[17].out_uop.fu_code[3] \n connect issue_slots[15].in_uop.bits.fu_code[4], issue_slots[17].out_uop.fu_code[4] \n connect issue_slots[15].in_uop.bits.fu_code[5], issue_slots[17].out_uop.fu_code[5] \n connect issue_slots[15].in_uop.bits.fu_code[6], issue_slots[17].out_uop.fu_code[6] \n connect issue_slots[15].in_uop.bits.fu_code[7], issue_slots[17].out_uop.fu_code[7] \n connect issue_slots[15].in_uop.bits.fu_code[8], issue_slots[17].out_uop.fu_code[8] \n connect issue_slots[15].in_uop.bits.fu_code[9], issue_slots[17].out_uop.fu_code[9] \n connect issue_slots[15].in_uop.bits.iq_type[0], issue_slots[17].out_uop.iq_type[0] \n connect issue_slots[15].in_uop.bits.iq_type[1], issue_slots[17].out_uop.iq_type[1] \n connect issue_slots[15].in_uop.bits.iq_type[2], issue_slots[17].out_uop.iq_type[2] \n connect issue_slots[15].in_uop.bits.iq_type[3], issue_slots[17].out_uop.iq_type[3] \n connect issue_slots[15].in_uop.bits.debug_pc, issue_slots[17].out_uop.debug_pc \n connect issue_slots[15].in_uop.bits.is_rvc, issue_slots[17].out_uop.is_rvc \n connect issue_slots[15].in_uop.bits.debug_inst, issue_slots[17].out_uop.debug_inst \n connect issue_slots[15].in_uop.bits.inst, issue_slots[17].out_uop.inst \n node _issue_slots_15_clear_T = neq(shamts_oh[15], UInt<1>(0h0)) \n connect issue_slots[15].clear, _issue_slots_15_clear_T \n connect issue_slots[16].in_uop.valid, UInt<1>(0h0) \n connect issue_slots[16].in_uop.bits.debug_tsrc, issue_slots[17].out_uop.debug_tsrc \n connect issue_slots[16].in_uop.bits.debug_fsrc, issue_slots[17].out_uop.debug_fsrc \n connect issue_slots[16].in_uop.bits.bp_xcpt_if, issue_slots[17].out_uop.bp_xcpt_if \n connect issue_slots[16].in_uop.bits.bp_debug_if, issue_slots[17].out_uop.bp_debug_if \n connect issue_slots[16].in_uop.bits.xcpt_ma_if, issue_slots[17].out_uop.xcpt_ma_if \n connect issue_slots[16].in_uop.bits.xcpt_ae_if, issue_slots[17].out_uop.xcpt_ae_if \n connect issue_slots[16].in_uop.bits.xcpt_pf_if, issue_slots[17].out_uop.xcpt_pf_if \n connect issue_slots[16].in_uop.bits.fp_typ, issue_slots[17].out_uop.fp_typ \n connect issue_slots[16].in_uop.bits.fp_rm, issue_slots[17].out_uop.fp_rm \n connect issue_slots[16].in_uop.bits.fp_val, issue_slots[17].out_uop.fp_val \n connect issue_slots[16].in_uop.bits.fcn_op, issue_slots[17].out_uop.fcn_op \n connect issue_slots[16].in_uop.bits.fcn_dw, issue_slots[17].out_uop.fcn_dw \n connect issue_slots[16].in_uop.bits.frs3_en, issue_slots[17].out_uop.frs3_en \n connect issue_slots[16].in_uop.bits.lrs2_rtype, issue_slots[17].out_uop.lrs2_rtype \n connect issue_slots[16].in_uop.bits.lrs1_rtype, issue_slots[17].out_uop.lrs1_rtype \n connect issue_slots[16].in_uop.bits.dst_rtype, issue_slots[17].out_uop.dst_rtype \n connect issue_slots[16].in_uop.bits.lrs3, issue_slots[17].out_uop.lrs3 \n connect issue_slots[16].in_uop.bits.lrs2, issue_slots[17].out_uop.lrs2 \n connect issue_slots[16].in_uop.bits.lrs1, issue_slots[17].out_uop.lrs1 \n connect issue_slots[16].in_uop.bits.ldst, issue_slots[17].out_uop.ldst \n connect issue_slots[16].in_uop.bits.ldst_is_rs1, issue_slots[17].out_uop.ldst_is_rs1 \n connect issue_slots[16].in_uop.bits.csr_cmd, issue_slots[17].out_uop.csr_cmd \n connect issue_slots[16].in_uop.bits.flush_on_commit, issue_slots[17].out_uop.flush_on_commit \n connect issue_slots[16].in_uop.bits.is_unique, issue_slots[17].out_uop.is_unique \n connect issue_slots[16].in_uop.bits.uses_stq, issue_slots[17].out_uop.uses_stq \n connect issue_slots[16].in_uop.bits.uses_ldq, issue_slots[17].out_uop.uses_ldq \n connect issue_slots[16].in_uop.bits.mem_signed, issue_slots[17].out_uop.mem_signed \n connect issue_slots[16].in_uop.bits.mem_size, issue_slots[17].out_uop.mem_size \n connect issue_slots[16].in_uop.bits.mem_cmd, issue_slots[17].out_uop.mem_cmd \n connect issue_slots[16].in_uop.bits.exc_cause, issue_slots[17].out_uop.exc_cause \n connect issue_slots[16].in_uop.bits.exception, issue_slots[17].out_uop.exception \n connect issue_slots[16].in_uop.bits.stale_pdst, issue_slots[17].out_uop.stale_pdst \n connect issue_slots[16].in_uop.bits.ppred_busy, issue_slots[17].out_uop.ppred_busy \n connect issue_slots[16].in_uop.bits.prs3_busy, issue_slots[17].out_uop.prs3_busy \n connect issue_slots[16].in_uop.bits.prs2_busy, issue_slots[17].out_uop.prs2_busy \n connect issue_slots[16].in_uop.bits.prs1_busy, issue_slots[17].out_uop.prs1_busy \n connect issue_slots[16].in_uop.bits.ppred, issue_slots[17].out_uop.ppred \n connect issue_slots[16].in_uop.bits.prs3, issue_slots[17].out_uop.prs3 \n connect issue_slots[16].in_uop.bits.prs2, issue_slots[17].out_uop.prs2 \n connect issue_slots[16].in_uop.bits.prs1, issue_slots[17].out_uop.prs1 \n connect issue_slots[16].in_uop.bits.pdst, issue_slots[17].out_uop.pdst \n connect issue_slots[16].in_uop.bits.rxq_idx, issue_slots[17].out_uop.rxq_idx \n connect issue_slots[16].in_uop.bits.stq_idx, issue_slots[17].out_uop.stq_idx \n connect issue_slots[16].in_uop.bits.ldq_idx, issue_slots[17].out_uop.ldq_idx \n connect issue_slots[16].in_uop.bits.rob_idx, issue_slots[17].out_uop.rob_idx \n connect issue_slots[16].in_uop.bits.fp_ctrl.vec, issue_slots[17].out_uop.fp_ctrl.vec \n connect issue_slots[16].in_uop.bits.fp_ctrl.wflags, issue_slots[17].out_uop.fp_ctrl.wflags \n connect issue_slots[16].in_uop.bits.fp_ctrl.sqrt, issue_slots[17].out_uop.fp_ctrl.sqrt \n connect issue_slots[16].in_uop.bits.fp_ctrl.div, issue_slots[17].out_uop.fp_ctrl.div \n connect issue_slots[16].in_uop.bits.fp_ctrl.fma, issue_slots[17].out_uop.fp_ctrl.fma \n connect issue_slots[16].in_uop.bits.fp_ctrl.fastpipe, issue_slots[17].out_uop.fp_ctrl.fastpipe \n connect issue_slots[16].in_uop.bits.fp_ctrl.toint, issue_slots[17].out_uop.fp_ctrl.toint \n connect issue_slots[16].in_uop.bits.fp_ctrl.fromint, issue_slots[17].out_uop.fp_ctrl.fromint \n connect issue_slots[16].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[17].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[16].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[17].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[16].in_uop.bits.fp_ctrl.swap23, issue_slots[17].out_uop.fp_ctrl.swap23 \n connect issue_slots[16].in_uop.bits.fp_ctrl.swap12, issue_slots[17].out_uop.fp_ctrl.swap12 \n connect issue_slots[16].in_uop.bits.fp_ctrl.ren3, issue_slots[17].out_uop.fp_ctrl.ren3 \n connect issue_slots[16].in_uop.bits.fp_ctrl.ren2, issue_slots[17].out_uop.fp_ctrl.ren2 \n connect issue_slots[16].in_uop.bits.fp_ctrl.ren1, issue_slots[17].out_uop.fp_ctrl.ren1 \n connect issue_slots[16].in_uop.bits.fp_ctrl.wen, issue_slots[17].out_uop.fp_ctrl.wen \n connect issue_slots[16].in_uop.bits.fp_ctrl.ldst, issue_slots[17].out_uop.fp_ctrl.ldst \n connect issue_slots[16].in_uop.bits.op2_sel, issue_slots[17].out_uop.op2_sel \n connect issue_slots[16].in_uop.bits.op1_sel, issue_slots[17].out_uop.op1_sel \n connect issue_slots[16].in_uop.bits.imm_packed, issue_slots[17].out_uop.imm_packed \n connect issue_slots[16].in_uop.bits.pimm, issue_slots[17].out_uop.pimm \n connect issue_slots[16].in_uop.bits.imm_sel, issue_slots[17].out_uop.imm_sel \n connect issue_slots[16].in_uop.bits.imm_rename, issue_slots[17].out_uop.imm_rename \n connect issue_slots[16].in_uop.bits.taken, issue_slots[17].out_uop.taken \n connect issue_slots[16].in_uop.bits.pc_lob, issue_slots[17].out_uop.pc_lob \n connect issue_slots[16].in_uop.bits.edge_inst, issue_slots[17].out_uop.edge_inst \n connect issue_slots[16].in_uop.bits.ftq_idx, issue_slots[17].out_uop.ftq_idx \n connect issue_slots[16].in_uop.bits.is_mov, issue_slots[17].out_uop.is_mov \n connect issue_slots[16].in_uop.bits.is_rocc, issue_slots[17].out_uop.is_rocc \n connect issue_slots[16].in_uop.bits.is_sys_pc2epc, issue_slots[17].out_uop.is_sys_pc2epc \n connect issue_slots[16].in_uop.bits.is_eret, issue_slots[17].out_uop.is_eret \n connect issue_slots[16].in_uop.bits.is_amo, issue_slots[17].out_uop.is_amo \n connect issue_slots[16].in_uop.bits.is_sfence, issue_slots[17].out_uop.is_sfence \n connect issue_slots[16].in_uop.bits.is_fencei, issue_slots[17].out_uop.is_fencei \n connect issue_slots[16].in_uop.bits.is_fence, issue_slots[17].out_uop.is_fence \n connect issue_slots[16].in_uop.bits.is_sfb, issue_slots[17].out_uop.is_sfb \n connect issue_slots[16].in_uop.bits.br_type, issue_slots[17].out_uop.br_type \n connect issue_slots[16].in_uop.bits.br_tag, issue_slots[17].out_uop.br_tag \n connect issue_slots[16].in_uop.bits.br_mask, issue_slots[17].out_uop.br_mask \n connect issue_slots[16].in_uop.bits.dis_col_sel, issue_slots[17].out_uop.dis_col_sel \n connect issue_slots[16].in_uop.bits.iw_p3_bypass_hint, issue_slots[17].out_uop.iw_p3_bypass_hint \n connect issue_slots[16].in_uop.bits.iw_p2_bypass_hint, issue_slots[17].out_uop.iw_p2_bypass_hint \n connect issue_slots[16].in_uop.bits.iw_p1_bypass_hint, issue_slots[17].out_uop.iw_p1_bypass_hint \n connect issue_slots[16].in_uop.bits.iw_p2_speculative_child, issue_slots[17].out_uop.iw_p2_speculative_child \n connect issue_slots[16].in_uop.bits.iw_p1_speculative_child, issue_slots[17].out_uop.iw_p1_speculative_child \n connect issue_slots[16].in_uop.bits.iw_issued_partial_dgen, issue_slots[17].out_uop.iw_issued_partial_dgen \n connect issue_slots[16].in_uop.bits.iw_issued_partial_agen, issue_slots[17].out_uop.iw_issued_partial_agen \n connect issue_slots[16].in_uop.bits.iw_issued, issue_slots[17].out_uop.iw_issued \n connect issue_slots[16].in_uop.bits.fu_code[0], issue_slots[17].out_uop.fu_code[0] \n connect issue_slots[16].in_uop.bits.fu_code[1], issue_slots[17].out_uop.fu_code[1] \n connect issue_slots[16].in_uop.bits.fu_code[2], issue_slots[17].out_uop.fu_code[2] \n connect issue_slots[16].in_uop.bits.fu_code[3], issue_slots[17].out_uop.fu_code[3] \n connect issue_slots[16].in_uop.bits.fu_code[4], issue_slots[17].out_uop.fu_code[4] \n connect issue_slots[16].in_uop.bits.fu_code[5], issue_slots[17].out_uop.fu_code[5] \n connect issue_slots[16].in_uop.bits.fu_code[6], issue_slots[17].out_uop.fu_code[6] \n connect issue_slots[16].in_uop.bits.fu_code[7], issue_slots[17].out_uop.fu_code[7] \n connect issue_slots[16].in_uop.bits.fu_code[8], issue_slots[17].out_uop.fu_code[8] \n connect issue_slots[16].in_uop.bits.fu_code[9], issue_slots[17].out_uop.fu_code[9] \n connect issue_slots[16].in_uop.bits.iq_type[0], issue_slots[17].out_uop.iq_type[0] \n connect issue_slots[16].in_uop.bits.iq_type[1], issue_slots[17].out_uop.iq_type[1] \n connect issue_slots[16].in_uop.bits.iq_type[2], issue_slots[17].out_uop.iq_type[2] \n connect issue_slots[16].in_uop.bits.iq_type[3], issue_slots[17].out_uop.iq_type[3] \n connect issue_slots[16].in_uop.bits.debug_pc, issue_slots[17].out_uop.debug_pc \n connect issue_slots[16].in_uop.bits.is_rvc, issue_slots[17].out_uop.is_rvc \n connect issue_slots[16].in_uop.bits.debug_inst, issue_slots[17].out_uop.debug_inst \n connect issue_slots[16].in_uop.bits.inst, issue_slots[17].out_uop.inst \n node _T_194 = eq(shamts_oh[17], UInt<1>(0h1)) \n when _T_194 : \n connect issue_slots[16].in_uop.valid, issue_slots[17].will_be_valid \n connect issue_slots[16].in_uop.bits.debug_tsrc, issue_slots[17].out_uop.debug_tsrc \n connect issue_slots[16].in_uop.bits.debug_fsrc, issue_slots[17].out_uop.debug_fsrc \n connect issue_slots[16].in_uop.bits.bp_xcpt_if, issue_slots[17].out_uop.bp_xcpt_if \n connect issue_slots[16].in_uop.bits.bp_debug_if, issue_slots[17].out_uop.bp_debug_if \n connect issue_slots[16].in_uop.bits.xcpt_ma_if, issue_slots[17].out_uop.xcpt_ma_if \n connect issue_slots[16].in_uop.bits.xcpt_ae_if, issue_slots[17].out_uop.xcpt_ae_if \n connect issue_slots[16].in_uop.bits.xcpt_pf_if, issue_slots[17].out_uop.xcpt_pf_if \n connect issue_slots[16].in_uop.bits.fp_typ, issue_slots[17].out_uop.fp_typ \n connect issue_slots[16].in_uop.bits.fp_rm, issue_slots[17].out_uop.fp_rm \n connect issue_slots[16].in_uop.bits.fp_val, issue_slots[17].out_uop.fp_val \n connect issue_slots[16].in_uop.bits.fcn_op, issue_slots[17].out_uop.fcn_op \n connect issue_slots[16].in_uop.bits.fcn_dw, issue_slots[17].out_uop.fcn_dw \n connect issue_slots[16].in_uop.bits.frs3_en, issue_slots[17].out_uop.frs3_en \n connect issue_slots[16].in_uop.bits.lrs2_rtype, issue_slots[17].out_uop.lrs2_rtype \n connect issue_slots[16].in_uop.bits.lrs1_rtype, issue_slots[17].out_uop.lrs1_rtype \n connect issue_slots[16].in_uop.bits.dst_rtype, issue_slots[17].out_uop.dst_rtype \n connect issue_slots[16].in_uop.bits.lrs3, issue_slots[17].out_uop.lrs3 \n connect issue_slots[16].in_uop.bits.lrs2, issue_slots[17].out_uop.lrs2 \n connect issue_slots[16].in_uop.bits.lrs1, issue_slots[17].out_uop.lrs1 \n connect issue_slots[16].in_uop.bits.ldst, issue_slots[17].out_uop.ldst \n connect issue_slots[16].in_uop.bits.ldst_is_rs1, issue_slots[17].out_uop.ldst_is_rs1 \n connect issue_slots[16].in_uop.bits.csr_cmd, issue_slots[17].out_uop.csr_cmd \n connect issue_slots[16].in_uop.bits.flush_on_commit, issue_slots[17].out_uop.flush_on_commit \n connect issue_slots[16].in_uop.bits.is_unique, issue_slots[17].out_uop.is_unique \n connect issue_slots[16].in_uop.bits.uses_stq, issue_slots[17].out_uop.uses_stq \n connect issue_slots[16].in_uop.bits.uses_ldq, issue_slots[17].out_uop.uses_ldq \n connect issue_slots[16].in_uop.bits.mem_signed, issue_slots[17].out_uop.mem_signed \n connect issue_slots[16].in_uop.bits.mem_size, issue_slots[17].out_uop.mem_size \n connect issue_slots[16].in_uop.bits.mem_cmd, issue_slots[17].out_uop.mem_cmd \n connect issue_slots[16].in_uop.bits.exc_cause, issue_slots[17].out_uop.exc_cause \n connect issue_slots[16].in_uop.bits.exception, issue_slots[17].out_uop.exception \n connect issue_slots[16].in_uop.bits.stale_pdst, issue_slots[17].out_uop.stale_pdst \n connect issue_slots[16].in_uop.bits.ppred_busy, issue_slots[17].out_uop.ppred_busy \n connect issue_slots[16].in_uop.bits.prs3_busy, issue_slots[17].out_uop.prs3_busy \n connect issue_slots[16].in_uop.bits.prs2_busy, issue_slots[17].out_uop.prs2_busy \n connect issue_slots[16].in_uop.bits.prs1_busy, issue_slots[17].out_uop.prs1_busy \n connect issue_slots[16].in_uop.bits.ppred, issue_slots[17].out_uop.ppred \n connect issue_slots[16].in_uop.bits.prs3, issue_slots[17].out_uop.prs3 \n connect issue_slots[16].in_uop.bits.prs2, issue_slots[17].out_uop.prs2 \n connect issue_slots[16].in_uop.bits.prs1, issue_slots[17].out_uop.prs1 \n connect issue_slots[16].in_uop.bits.pdst, issue_slots[17].out_uop.pdst \n connect issue_slots[16].in_uop.bits.rxq_idx, issue_slots[17].out_uop.rxq_idx \n connect issue_slots[16].in_uop.bits.stq_idx, issue_slots[17].out_uop.stq_idx \n connect issue_slots[16].in_uop.bits.ldq_idx, issue_slots[17].out_uop.ldq_idx \n connect issue_slots[16].in_uop.bits.rob_idx, issue_slots[17].out_uop.rob_idx \n connect issue_slots[16].in_uop.bits.fp_ctrl.vec, issue_slots[17].out_uop.fp_ctrl.vec \n connect issue_slots[16].in_uop.bits.fp_ctrl.wflags, issue_slots[17].out_uop.fp_ctrl.wflags \n connect issue_slots[16].in_uop.bits.fp_ctrl.sqrt, issue_slots[17].out_uop.fp_ctrl.sqrt \n connect issue_slots[16].in_uop.bits.fp_ctrl.div, issue_slots[17].out_uop.fp_ctrl.div \n connect issue_slots[16].in_uop.bits.fp_ctrl.fma, issue_slots[17].out_uop.fp_ctrl.fma \n connect issue_slots[16].in_uop.bits.fp_ctrl.fastpipe, issue_slots[17].out_uop.fp_ctrl.fastpipe \n connect issue_slots[16].in_uop.bits.fp_ctrl.toint, issue_slots[17].out_uop.fp_ctrl.toint \n connect issue_slots[16].in_uop.bits.fp_ctrl.fromint, issue_slots[17].out_uop.fp_ctrl.fromint \n connect issue_slots[16].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[17].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[16].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[17].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[16].in_uop.bits.fp_ctrl.swap23, issue_slots[17].out_uop.fp_ctrl.swap23 \n connect issue_slots[16].in_uop.bits.fp_ctrl.swap12, issue_slots[17].out_uop.fp_ctrl.swap12 \n connect issue_slots[16].in_uop.bits.fp_ctrl.ren3, issue_slots[17].out_uop.fp_ctrl.ren3 \n connect issue_slots[16].in_uop.bits.fp_ctrl.ren2, issue_slots[17].out_uop.fp_ctrl.ren2 \n connect issue_slots[16].in_uop.bits.fp_ctrl.ren1, issue_slots[17].out_uop.fp_ctrl.ren1 \n connect issue_slots[16].in_uop.bits.fp_ctrl.wen, issue_slots[17].out_uop.fp_ctrl.wen \n connect issue_slots[16].in_uop.bits.fp_ctrl.ldst, issue_slots[17].out_uop.fp_ctrl.ldst \n connect issue_slots[16].in_uop.bits.op2_sel, issue_slots[17].out_uop.op2_sel \n connect issue_slots[16].in_uop.bits.op1_sel, issue_slots[17].out_uop.op1_sel \n connect issue_slots[16].in_uop.bits.imm_packed, issue_slots[17].out_uop.imm_packed \n connect issue_slots[16].in_uop.bits.pimm, issue_slots[17].out_uop.pimm \n connect issue_slots[16].in_uop.bits.imm_sel, issue_slots[17].out_uop.imm_sel \n connect issue_slots[16].in_uop.bits.imm_rename, issue_slots[17].out_uop.imm_rename \n connect issue_slots[16].in_uop.bits.taken, issue_slots[17].out_uop.taken \n connect issue_slots[16].in_uop.bits.pc_lob, issue_slots[17].out_uop.pc_lob \n connect issue_slots[16].in_uop.bits.edge_inst, issue_slots[17].out_uop.edge_inst \n connect issue_slots[16].in_uop.bits.ftq_idx, issue_slots[17].out_uop.ftq_idx \n connect issue_slots[16].in_uop.bits.is_mov, issue_slots[17].out_uop.is_mov \n connect issue_slots[16].in_uop.bits.is_rocc, issue_slots[17].out_uop.is_rocc \n connect issue_slots[16].in_uop.bits.is_sys_pc2epc, issue_slots[17].out_uop.is_sys_pc2epc \n connect issue_slots[16].in_uop.bits.is_eret, issue_slots[17].out_uop.is_eret \n connect issue_slots[16].in_uop.bits.is_amo, issue_slots[17].out_uop.is_amo \n connect issue_slots[16].in_uop.bits.is_sfence, issue_slots[17].out_uop.is_sfence \n connect issue_slots[16].in_uop.bits.is_fencei, issue_slots[17].out_uop.is_fencei \n connect issue_slots[16].in_uop.bits.is_fence, issue_slots[17].out_uop.is_fence \n connect issue_slots[16].in_uop.bits.is_sfb, issue_slots[17].out_uop.is_sfb \n connect issue_slots[16].in_uop.bits.br_type, issue_slots[17].out_uop.br_type \n connect issue_slots[16].in_uop.bits.br_tag, issue_slots[17].out_uop.br_tag \n connect issue_slots[16].in_uop.bits.br_mask, issue_slots[17].out_uop.br_mask \n connect issue_slots[16].in_uop.bits.dis_col_sel, issue_slots[17].out_uop.dis_col_sel \n connect issue_slots[16].in_uop.bits.iw_p3_bypass_hint, issue_slots[17].out_uop.iw_p3_bypass_hint \n connect issue_slots[16].in_uop.bits.iw_p2_bypass_hint, issue_slots[17].out_uop.iw_p2_bypass_hint \n connect issue_slots[16].in_uop.bits.iw_p1_bypass_hint, issue_slots[17].out_uop.iw_p1_bypass_hint \n connect issue_slots[16].in_uop.bits.iw_p2_speculative_child, issue_slots[17].out_uop.iw_p2_speculative_child \n connect issue_slots[16].in_uop.bits.iw_p1_speculative_child, issue_slots[17].out_uop.iw_p1_speculative_child \n connect issue_slots[16].in_uop.bits.iw_issued_partial_dgen, issue_slots[17].out_uop.iw_issued_partial_dgen \n connect issue_slots[16].in_uop.bits.iw_issued_partial_agen, issue_slots[17].out_uop.iw_issued_partial_agen \n connect issue_slots[16].in_uop.bits.iw_issued, issue_slots[17].out_uop.iw_issued \n connect issue_slots[16].in_uop.bits.fu_code[0], issue_slots[17].out_uop.fu_code[0] \n connect issue_slots[16].in_uop.bits.fu_code[1], issue_slots[17].out_uop.fu_code[1] \n connect issue_slots[16].in_uop.bits.fu_code[2], issue_slots[17].out_uop.fu_code[2] \n connect issue_slots[16].in_uop.bits.fu_code[3], issue_slots[17].out_uop.fu_code[3] \n connect issue_slots[16].in_uop.bits.fu_code[4], issue_slots[17].out_uop.fu_code[4] \n connect issue_slots[16].in_uop.bits.fu_code[5], issue_slots[17].out_uop.fu_code[5] \n connect issue_slots[16].in_uop.bits.fu_code[6], issue_slots[17].out_uop.fu_code[6] \n connect issue_slots[16].in_uop.bits.fu_code[7], issue_slots[17].out_uop.fu_code[7] \n connect issue_slots[16].in_uop.bits.fu_code[8], issue_slots[17].out_uop.fu_code[8] \n connect issue_slots[16].in_uop.bits.fu_code[9], issue_slots[17].out_uop.fu_code[9] \n connect issue_slots[16].in_uop.bits.iq_type[0], issue_slots[17].out_uop.iq_type[0] \n connect issue_slots[16].in_uop.bits.iq_type[1], issue_slots[17].out_uop.iq_type[1] \n connect issue_slots[16].in_uop.bits.iq_type[2], issue_slots[17].out_uop.iq_type[2] \n connect issue_slots[16].in_uop.bits.iq_type[3], issue_slots[17].out_uop.iq_type[3] \n connect issue_slots[16].in_uop.bits.debug_pc, issue_slots[17].out_uop.debug_pc \n connect issue_slots[16].in_uop.bits.is_rvc, issue_slots[17].out_uop.is_rvc \n connect issue_slots[16].in_uop.bits.debug_inst, issue_slots[17].out_uop.debug_inst \n connect issue_slots[16].in_uop.bits.inst, issue_slots[17].out_uop.inst \n node _T_195 = eq(shamts_oh[18], UInt<2>(0h2)) \n when _T_195 : \n connect issue_slots[16].in_uop.valid, issue_slots[18].will_be_valid \n connect issue_slots[16].in_uop.bits.debug_tsrc, issue_slots[18].out_uop.debug_tsrc \n connect issue_slots[16].in_uop.bits.debug_fsrc, issue_slots[18].out_uop.debug_fsrc \n connect issue_slots[16].in_uop.bits.bp_xcpt_if, issue_slots[18].out_uop.bp_xcpt_if \n connect issue_slots[16].in_uop.bits.bp_debug_if, issue_slots[18].out_uop.bp_debug_if \n connect issue_slots[16].in_uop.bits.xcpt_ma_if, issue_slots[18].out_uop.xcpt_ma_if \n connect issue_slots[16].in_uop.bits.xcpt_ae_if, issue_slots[18].out_uop.xcpt_ae_if \n connect issue_slots[16].in_uop.bits.xcpt_pf_if, issue_slots[18].out_uop.xcpt_pf_if \n connect issue_slots[16].in_uop.bits.fp_typ, issue_slots[18].out_uop.fp_typ \n connect issue_slots[16].in_uop.bits.fp_rm, issue_slots[18].out_uop.fp_rm \n connect issue_slots[16].in_uop.bits.fp_val, issue_slots[18].out_uop.fp_val \n connect issue_slots[16].in_uop.bits.fcn_op, issue_slots[18].out_uop.fcn_op \n connect issue_slots[16].in_uop.bits.fcn_dw, issue_slots[18].out_uop.fcn_dw \n connect issue_slots[16].in_uop.bits.frs3_en, issue_slots[18].out_uop.frs3_en \n connect issue_slots[16].in_uop.bits.lrs2_rtype, issue_slots[18].out_uop.lrs2_rtype \n connect issue_slots[16].in_uop.bits.lrs1_rtype, issue_slots[18].out_uop.lrs1_rtype \n connect issue_slots[16].in_uop.bits.dst_rtype, issue_slots[18].out_uop.dst_rtype \n connect issue_slots[16].in_uop.bits.lrs3, issue_slots[18].out_uop.lrs3 \n connect issue_slots[16].in_uop.bits.lrs2, issue_slots[18].out_uop.lrs2 \n connect issue_slots[16].in_uop.bits.lrs1, issue_slots[18].out_uop.lrs1 \n connect issue_slots[16].in_uop.bits.ldst, issue_slots[18].out_uop.ldst \n connect issue_slots[16].in_uop.bits.ldst_is_rs1, issue_slots[18].out_uop.ldst_is_rs1 \n connect issue_slots[16].in_uop.bits.csr_cmd, issue_slots[18].out_uop.csr_cmd \n connect issue_slots[16].in_uop.bits.flush_on_commit, issue_slots[18].out_uop.flush_on_commit \n connect issue_slots[16].in_uop.bits.is_unique, issue_slots[18].out_uop.is_unique \n connect issue_slots[16].in_uop.bits.uses_stq, issue_slots[18].out_uop.uses_stq \n connect issue_slots[16].in_uop.bits.uses_ldq, issue_slots[18].out_uop.uses_ldq \n connect issue_slots[16].in_uop.bits.mem_signed, issue_slots[18].out_uop.mem_signed \n connect issue_slots[16].in_uop.bits.mem_size, issue_slots[18].out_uop.mem_size \n connect issue_slots[16].in_uop.bits.mem_cmd, issue_slots[18].out_uop.mem_cmd \n connect issue_slots[16].in_uop.bits.exc_cause, issue_slots[18].out_uop.exc_cause \n connect issue_slots[16].in_uop.bits.exception, issue_slots[18].out_uop.exception \n connect issue_slots[16].in_uop.bits.stale_pdst, issue_slots[18].out_uop.stale_pdst \n connect issue_slots[16].in_uop.bits.ppred_busy, issue_slots[18].out_uop.ppred_busy \n connect issue_slots[16].in_uop.bits.prs3_busy, issue_slots[18].out_uop.prs3_busy \n connect issue_slots[16].in_uop.bits.prs2_busy, issue_slots[18].out_uop.prs2_busy \n connect issue_slots[16].in_uop.bits.prs1_busy, issue_slots[18].out_uop.prs1_busy \n connect issue_slots[16].in_uop.bits.ppred, issue_slots[18].out_uop.ppred \n connect issue_slots[16].in_uop.bits.prs3, issue_slots[18].out_uop.prs3 \n connect issue_slots[16].in_uop.bits.prs2, issue_slots[18].out_uop.prs2 \n connect issue_slots[16].in_uop.bits.prs1, issue_slots[18].out_uop.prs1 \n connect issue_slots[16].in_uop.bits.pdst, issue_slots[18].out_uop.pdst \n connect issue_slots[16].in_uop.bits.rxq_idx, issue_slots[18].out_uop.rxq_idx \n connect issue_slots[16].in_uop.bits.stq_idx, issue_slots[18].out_uop.stq_idx \n connect issue_slots[16].in_uop.bits.ldq_idx, issue_slots[18].out_uop.ldq_idx \n connect issue_slots[16].in_uop.bits.rob_idx, issue_slots[18].out_uop.rob_idx \n connect issue_slots[16].in_uop.bits.fp_ctrl.vec, issue_slots[18].out_uop.fp_ctrl.vec \n connect issue_slots[16].in_uop.bits.fp_ctrl.wflags, issue_slots[18].out_uop.fp_ctrl.wflags \n connect issue_slots[16].in_uop.bits.fp_ctrl.sqrt, issue_slots[18].out_uop.fp_ctrl.sqrt \n connect issue_slots[16].in_uop.bits.fp_ctrl.div, issue_slots[18].out_uop.fp_ctrl.div \n connect issue_slots[16].in_uop.bits.fp_ctrl.fma, issue_slots[18].out_uop.fp_ctrl.fma \n connect issue_slots[16].in_uop.bits.fp_ctrl.fastpipe, issue_slots[18].out_uop.fp_ctrl.fastpipe \n connect issue_slots[16].in_uop.bits.fp_ctrl.toint, issue_slots[18].out_uop.fp_ctrl.toint \n connect issue_slots[16].in_uop.bits.fp_ctrl.fromint, issue_slots[18].out_uop.fp_ctrl.fromint \n connect issue_slots[16].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[18].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[16].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[18].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[16].in_uop.bits.fp_ctrl.swap23, issue_slots[18].out_uop.fp_ctrl.swap23 \n connect issue_slots[16].in_uop.bits.fp_ctrl.swap12, issue_slots[18].out_uop.fp_ctrl.swap12 \n connect issue_slots[16].in_uop.bits.fp_ctrl.ren3, issue_slots[18].out_uop.fp_ctrl.ren3 \n connect issue_slots[16].in_uop.bits.fp_ctrl.ren2, issue_slots[18].out_uop.fp_ctrl.ren2 \n connect issue_slots[16].in_uop.bits.fp_ctrl.ren1, issue_slots[18].out_uop.fp_ctrl.ren1 \n connect issue_slots[16].in_uop.bits.fp_ctrl.wen, issue_slots[18].out_uop.fp_ctrl.wen \n connect issue_slots[16].in_uop.bits.fp_ctrl.ldst, issue_slots[18].out_uop.fp_ctrl.ldst \n connect issue_slots[16].in_uop.bits.op2_sel, issue_slots[18].out_uop.op2_sel \n connect issue_slots[16].in_uop.bits.op1_sel, issue_slots[18].out_uop.op1_sel \n connect issue_slots[16].in_uop.bits.imm_packed, issue_slots[18].out_uop.imm_packed \n connect issue_slots[16].in_uop.bits.pimm, issue_slots[18].out_uop.pimm \n connect issue_slots[16].in_uop.bits.imm_sel, issue_slots[18].out_uop.imm_sel \n connect issue_slots[16].in_uop.bits.imm_rename, issue_slots[18].out_uop.imm_rename \n connect issue_slots[16].in_uop.bits.taken, issue_slots[18].out_uop.taken \n connect issue_slots[16].in_uop.bits.pc_lob, issue_slots[18].out_uop.pc_lob \n connect issue_slots[16].in_uop.bits.edge_inst, issue_slots[18].out_uop.edge_inst \n connect issue_slots[16].in_uop.bits.ftq_idx, issue_slots[18].out_uop.ftq_idx \n connect issue_slots[16].in_uop.bits.is_mov, issue_slots[18].out_uop.is_mov \n connect issue_slots[16].in_uop.bits.is_rocc, issue_slots[18].out_uop.is_rocc \n connect issue_slots[16].in_uop.bits.is_sys_pc2epc, issue_slots[18].out_uop.is_sys_pc2epc \n connect issue_slots[16].in_uop.bits.is_eret, issue_slots[18].out_uop.is_eret \n connect issue_slots[16].in_uop.bits.is_amo, issue_slots[18].out_uop.is_amo \n connect issue_slots[16].in_uop.bits.is_sfence, issue_slots[18].out_uop.is_sfence \n connect issue_slots[16].in_uop.bits.is_fencei, issue_slots[18].out_uop.is_fencei \n connect issue_slots[16].in_uop.bits.is_fence, issue_slots[18].out_uop.is_fence \n connect issue_slots[16].in_uop.bits.is_sfb, issue_slots[18].out_uop.is_sfb \n connect issue_slots[16].in_uop.bits.br_type, issue_slots[18].out_uop.br_type \n connect issue_slots[16].in_uop.bits.br_tag, issue_slots[18].out_uop.br_tag \n connect issue_slots[16].in_uop.bits.br_mask, issue_slots[18].out_uop.br_mask \n connect issue_slots[16].in_uop.bits.dis_col_sel, issue_slots[18].out_uop.dis_col_sel \n connect issue_slots[16].in_uop.bits.iw_p3_bypass_hint, issue_slots[18].out_uop.iw_p3_bypass_hint \n connect issue_slots[16].in_uop.bits.iw_p2_bypass_hint, issue_slots[18].out_uop.iw_p2_bypass_hint \n connect issue_slots[16].in_uop.bits.iw_p1_bypass_hint, issue_slots[18].out_uop.iw_p1_bypass_hint \n connect issue_slots[16].in_uop.bits.iw_p2_speculative_child, issue_slots[18].out_uop.iw_p2_speculative_child \n connect issue_slots[16].in_uop.bits.iw_p1_speculative_child, issue_slots[18].out_uop.iw_p1_speculative_child \n connect issue_slots[16].in_uop.bits.iw_issued_partial_dgen, issue_slots[18].out_uop.iw_issued_partial_dgen \n connect issue_slots[16].in_uop.bits.iw_issued_partial_agen, issue_slots[18].out_uop.iw_issued_partial_agen \n connect issue_slots[16].in_uop.bits.iw_issued, issue_slots[18].out_uop.iw_issued \n connect issue_slots[16].in_uop.bits.fu_code[0], issue_slots[18].out_uop.fu_code[0] \n connect issue_slots[16].in_uop.bits.fu_code[1], issue_slots[18].out_uop.fu_code[1] \n connect issue_slots[16].in_uop.bits.fu_code[2], issue_slots[18].out_uop.fu_code[2] \n connect issue_slots[16].in_uop.bits.fu_code[3], issue_slots[18].out_uop.fu_code[3] \n connect issue_slots[16].in_uop.bits.fu_code[4], issue_slots[18].out_uop.fu_code[4] \n connect issue_slots[16].in_uop.bits.fu_code[5], issue_slots[18].out_uop.fu_code[5] \n connect issue_slots[16].in_uop.bits.fu_code[6], issue_slots[18].out_uop.fu_code[6] \n connect issue_slots[16].in_uop.bits.fu_code[7], issue_slots[18].out_uop.fu_code[7] \n connect issue_slots[16].in_uop.bits.fu_code[8], issue_slots[18].out_uop.fu_code[8] \n connect issue_slots[16].in_uop.bits.fu_code[9], issue_slots[18].out_uop.fu_code[9] \n connect issue_slots[16].in_uop.bits.iq_type[0], issue_slots[18].out_uop.iq_type[0] \n connect issue_slots[16].in_uop.bits.iq_type[1], issue_slots[18].out_uop.iq_type[1] \n connect issue_slots[16].in_uop.bits.iq_type[2], issue_slots[18].out_uop.iq_type[2] \n connect issue_slots[16].in_uop.bits.iq_type[3], issue_slots[18].out_uop.iq_type[3] \n connect issue_slots[16].in_uop.bits.debug_pc, issue_slots[18].out_uop.debug_pc \n connect issue_slots[16].in_uop.bits.is_rvc, issue_slots[18].out_uop.is_rvc \n connect issue_slots[16].in_uop.bits.debug_inst, issue_slots[18].out_uop.debug_inst \n connect issue_slots[16].in_uop.bits.inst, issue_slots[18].out_uop.inst \n node _issue_slots_16_clear_T = neq(shamts_oh[16], UInt<1>(0h0)) \n connect issue_slots[16].clear, _issue_slots_16_clear_T \n connect issue_slots[17].in_uop.valid, UInt<1>(0h0) \n connect issue_slots[17].in_uop.bits.debug_tsrc, issue_slots[18].out_uop.debug_tsrc \n connect issue_slots[17].in_uop.bits.debug_fsrc, issue_slots[18].out_uop.debug_fsrc \n connect issue_slots[17].in_uop.bits.bp_xcpt_if, issue_slots[18].out_uop.bp_xcpt_if \n connect issue_slots[17].in_uop.bits.bp_debug_if, issue_slots[18].out_uop.bp_debug_if \n connect issue_slots[17].in_uop.bits.xcpt_ma_if, issue_slots[18].out_uop.xcpt_ma_if \n connect issue_slots[17].in_uop.bits.xcpt_ae_if, issue_slots[18].out_uop.xcpt_ae_if \n connect issue_slots[17].in_uop.bits.xcpt_pf_if, issue_slots[18].out_uop.xcpt_pf_if \n connect issue_slots[17].in_uop.bits.fp_typ, issue_slots[18].out_uop.fp_typ \n connect issue_slots[17].in_uop.bits.fp_rm, issue_slots[18].out_uop.fp_rm \n connect issue_slots[17].in_uop.bits.fp_val, issue_slots[18].out_uop.fp_val \n connect issue_slots[17].in_uop.bits.fcn_op, issue_slots[18].out_uop.fcn_op \n connect issue_slots[17].in_uop.bits.fcn_dw, issue_slots[18].out_uop.fcn_dw \n connect issue_slots[17].in_uop.bits.frs3_en, issue_slots[18].out_uop.frs3_en \n connect issue_slots[17].in_uop.bits.lrs2_rtype, issue_slots[18].out_uop.lrs2_rtype \n connect issue_slots[17].in_uop.bits.lrs1_rtype, issue_slots[18].out_uop.lrs1_rtype \n connect issue_slots[17].in_uop.bits.dst_rtype, issue_slots[18].out_uop.dst_rtype \n connect issue_slots[17].in_uop.bits.lrs3, issue_slots[18].out_uop.lrs3 \n connect issue_slots[17].in_uop.bits.lrs2, issue_slots[18].out_uop.lrs2 \n connect issue_slots[17].in_uop.bits.lrs1, issue_slots[18].out_uop.lrs1 \n connect issue_slots[17].in_uop.bits.ldst, issue_slots[18].out_uop.ldst \n connect issue_slots[17].in_uop.bits.ldst_is_rs1, issue_slots[18].out_uop.ldst_is_rs1 \n connect issue_slots[17].in_uop.bits.csr_cmd, issue_slots[18].out_uop.csr_cmd \n connect issue_slots[17].in_uop.bits.flush_on_commit, issue_slots[18].out_uop.flush_on_commit \n connect issue_slots[17].in_uop.bits.is_unique, issue_slots[18].out_uop.is_unique \n connect issue_slots[17].in_uop.bits.uses_stq, issue_slots[18].out_uop.uses_stq \n connect issue_slots[17].in_uop.bits.uses_ldq, issue_slots[18].out_uop.uses_ldq \n connect issue_slots[17].in_uop.bits.mem_signed, issue_slots[18].out_uop.mem_signed \n connect issue_slots[17].in_uop.bits.mem_size, issue_slots[18].out_uop.mem_size \n connect issue_slots[17].in_uop.bits.mem_cmd, issue_slots[18].out_uop.mem_cmd \n connect issue_slots[17].in_uop.bits.exc_cause, issue_slots[18].out_uop.exc_cause \n connect issue_slots[17].in_uop.bits.exception, issue_slots[18].out_uop.exception \n connect issue_slots[17].in_uop.bits.stale_pdst, issue_slots[18].out_uop.stale_pdst \n connect issue_slots[17].in_uop.bits.ppred_busy, issue_slots[18].out_uop.ppred_busy \n connect issue_slots[17].in_uop.bits.prs3_busy, issue_slots[18].out_uop.prs3_busy \n connect issue_slots[17].in_uop.bits.prs2_busy, issue_slots[18].out_uop.prs2_busy \n connect issue_slots[17].in_uop.bits.prs1_busy, issue_slots[18].out_uop.prs1_busy \n connect issue_slots[17].in_uop.bits.ppred, issue_slots[18].out_uop.ppred \n connect issue_slots[17].in_uop.bits.prs3, issue_slots[18].out_uop.prs3 \n connect issue_slots[17].in_uop.bits.prs2, issue_slots[18].out_uop.prs2 \n connect issue_slots[17].in_uop.bits.prs1, issue_slots[18].out_uop.prs1 \n connect issue_slots[17].in_uop.bits.pdst, issue_slots[18].out_uop.pdst \n connect issue_slots[17].in_uop.bits.rxq_idx, issue_slots[18].out_uop.rxq_idx \n connect issue_slots[17].in_uop.bits.stq_idx, issue_slots[18].out_uop.stq_idx \n connect issue_slots[17].in_uop.bits.ldq_idx, issue_slots[18].out_uop.ldq_idx \n connect issue_slots[17].in_uop.bits.rob_idx, issue_slots[18].out_uop.rob_idx \n connect issue_slots[17].in_uop.bits.fp_ctrl.vec, issue_slots[18].out_uop.fp_ctrl.vec \n connect issue_slots[17].in_uop.bits.fp_ctrl.wflags, issue_slots[18].out_uop.fp_ctrl.wflags \n connect issue_slots[17].in_uop.bits.fp_ctrl.sqrt, issue_slots[18].out_uop.fp_ctrl.sqrt \n connect issue_slots[17].in_uop.bits.fp_ctrl.div, issue_slots[18].out_uop.fp_ctrl.div \n connect issue_slots[17].in_uop.bits.fp_ctrl.fma, issue_slots[18].out_uop.fp_ctrl.fma \n connect issue_slots[17].in_uop.bits.fp_ctrl.fastpipe, issue_slots[18].out_uop.fp_ctrl.fastpipe \n connect issue_slots[17].in_uop.bits.fp_ctrl.toint, issue_slots[18].out_uop.fp_ctrl.toint \n connect issue_slots[17].in_uop.bits.fp_ctrl.fromint, issue_slots[18].out_uop.fp_ctrl.fromint \n connect issue_slots[17].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[18].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[17].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[18].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[17].in_uop.bits.fp_ctrl.swap23, issue_slots[18].out_uop.fp_ctrl.swap23 \n connect issue_slots[17].in_uop.bits.fp_ctrl.swap12, issue_slots[18].out_uop.fp_ctrl.swap12 \n connect issue_slots[17].in_uop.bits.fp_ctrl.ren3, issue_slots[18].out_uop.fp_ctrl.ren3 \n connect issue_slots[17].in_uop.bits.fp_ctrl.ren2, issue_slots[18].out_uop.fp_ctrl.ren2 \n connect issue_slots[17].in_uop.bits.fp_ctrl.ren1, issue_slots[18].out_uop.fp_ctrl.ren1 \n connect issue_slots[17].in_uop.bits.fp_ctrl.wen, issue_slots[18].out_uop.fp_ctrl.wen \n connect issue_slots[17].in_uop.bits.fp_ctrl.ldst, issue_slots[18].out_uop.fp_ctrl.ldst \n connect issue_slots[17].in_uop.bits.op2_sel, issue_slots[18].out_uop.op2_sel \n connect issue_slots[17].in_uop.bits.op1_sel, issue_slots[18].out_uop.op1_sel \n connect issue_slots[17].in_uop.bits.imm_packed, issue_slots[18].out_uop.imm_packed \n connect issue_slots[17].in_uop.bits.pimm, issue_slots[18].out_uop.pimm \n connect issue_slots[17].in_uop.bits.imm_sel, issue_slots[18].out_uop.imm_sel \n connect issue_slots[17].in_uop.bits.imm_rename, issue_slots[18].out_uop.imm_rename \n connect issue_slots[17].in_uop.bits.taken, issue_slots[18].out_uop.taken \n connect issue_slots[17].in_uop.bits.pc_lob, issue_slots[18].out_uop.pc_lob \n connect issue_slots[17].in_uop.bits.edge_inst, issue_slots[18].out_uop.edge_inst \n connect issue_slots[17].in_uop.bits.ftq_idx, issue_slots[18].out_uop.ftq_idx \n connect issue_slots[17].in_uop.bits.is_mov, issue_slots[18].out_uop.is_mov \n connect issue_slots[17].in_uop.bits.is_rocc, issue_slots[18].out_uop.is_rocc \n connect issue_slots[17].in_uop.bits.is_sys_pc2epc, issue_slots[18].out_uop.is_sys_pc2epc \n connect issue_slots[17].in_uop.bits.is_eret, issue_slots[18].out_uop.is_eret \n connect issue_slots[17].in_uop.bits.is_amo, issue_slots[18].out_uop.is_amo \n connect issue_slots[17].in_uop.bits.is_sfence, issue_slots[18].out_uop.is_sfence \n connect issue_slots[17].in_uop.bits.is_fencei, issue_slots[18].out_uop.is_fencei \n connect issue_slots[17].in_uop.bits.is_fence, issue_slots[18].out_uop.is_fence \n connect issue_slots[17].in_uop.bits.is_sfb, issue_slots[18].out_uop.is_sfb \n connect issue_slots[17].in_uop.bits.br_type, issue_slots[18].out_uop.br_type \n connect issue_slots[17].in_uop.bits.br_tag, issue_slots[18].out_uop.br_tag \n connect issue_slots[17].in_uop.bits.br_mask, issue_slots[18].out_uop.br_mask \n connect issue_slots[17].in_uop.bits.dis_col_sel, issue_slots[18].out_uop.dis_col_sel \n connect issue_slots[17].in_uop.bits.iw_p3_bypass_hint, issue_slots[18].out_uop.iw_p3_bypass_hint \n connect issue_slots[17].in_uop.bits.iw_p2_bypass_hint, issue_slots[18].out_uop.iw_p2_bypass_hint \n connect issue_slots[17].in_uop.bits.iw_p1_bypass_hint, issue_slots[18].out_uop.iw_p1_bypass_hint \n connect issue_slots[17].in_uop.bits.iw_p2_speculative_child, issue_slots[18].out_uop.iw_p2_speculative_child \n connect issue_slots[17].in_uop.bits.iw_p1_speculative_child, issue_slots[18].out_uop.iw_p1_speculative_child \n connect issue_slots[17].in_uop.bits.iw_issued_partial_dgen, issue_slots[18].out_uop.iw_issued_partial_dgen \n connect issue_slots[17].in_uop.bits.iw_issued_partial_agen, issue_slots[18].out_uop.iw_issued_partial_agen \n connect issue_slots[17].in_uop.bits.iw_issued, issue_slots[18].out_uop.iw_issued \n connect issue_slots[17].in_uop.bits.fu_code[0], issue_slots[18].out_uop.fu_code[0] \n connect issue_slots[17].in_uop.bits.fu_code[1], issue_slots[18].out_uop.fu_code[1] \n connect issue_slots[17].in_uop.bits.fu_code[2], issue_slots[18].out_uop.fu_code[2] \n connect issue_slots[17].in_uop.bits.fu_code[3], issue_slots[18].out_uop.fu_code[3] \n connect issue_slots[17].in_uop.bits.fu_code[4], issue_slots[18].out_uop.fu_code[4] \n connect issue_slots[17].in_uop.bits.fu_code[5], issue_slots[18].out_uop.fu_code[5] \n connect issue_slots[17].in_uop.bits.fu_code[6], issue_slots[18].out_uop.fu_code[6] \n connect issue_slots[17].in_uop.bits.fu_code[7], issue_slots[18].out_uop.fu_code[7] \n connect issue_slots[17].in_uop.bits.fu_code[8], issue_slots[18].out_uop.fu_code[8] \n connect issue_slots[17].in_uop.bits.fu_code[9], issue_slots[18].out_uop.fu_code[9] \n connect issue_slots[17].in_uop.bits.iq_type[0], issue_slots[18].out_uop.iq_type[0] \n connect issue_slots[17].in_uop.bits.iq_type[1], issue_slots[18].out_uop.iq_type[1] \n connect issue_slots[17].in_uop.bits.iq_type[2], issue_slots[18].out_uop.iq_type[2] \n connect issue_slots[17].in_uop.bits.iq_type[3], issue_slots[18].out_uop.iq_type[3] \n connect issue_slots[17].in_uop.bits.debug_pc, issue_slots[18].out_uop.debug_pc \n connect issue_slots[17].in_uop.bits.is_rvc, issue_slots[18].out_uop.is_rvc \n connect issue_slots[17].in_uop.bits.debug_inst, issue_slots[18].out_uop.debug_inst \n connect issue_slots[17].in_uop.bits.inst, issue_slots[18].out_uop.inst \n node _T_196 = eq(shamts_oh[18], UInt<1>(0h1)) \n when _T_196 : \n connect issue_slots[17].in_uop.valid, issue_slots[18].will_be_valid \n connect issue_slots[17].in_uop.bits.debug_tsrc, issue_slots[18].out_uop.debug_tsrc \n connect issue_slots[17].in_uop.bits.debug_fsrc, issue_slots[18].out_uop.debug_fsrc \n connect issue_slots[17].in_uop.bits.bp_xcpt_if, issue_slots[18].out_uop.bp_xcpt_if \n connect issue_slots[17].in_uop.bits.bp_debug_if, issue_slots[18].out_uop.bp_debug_if \n connect issue_slots[17].in_uop.bits.xcpt_ma_if, issue_slots[18].out_uop.xcpt_ma_if \n connect issue_slots[17].in_uop.bits.xcpt_ae_if, issue_slots[18].out_uop.xcpt_ae_if \n connect issue_slots[17].in_uop.bits.xcpt_pf_if, issue_slots[18].out_uop.xcpt_pf_if \n connect issue_slots[17].in_uop.bits.fp_typ, issue_slots[18].out_uop.fp_typ \n connect issue_slots[17].in_uop.bits.fp_rm, issue_slots[18].out_uop.fp_rm \n connect issue_slots[17].in_uop.bits.fp_val, issue_slots[18].out_uop.fp_val \n connect issue_slots[17].in_uop.bits.fcn_op, issue_slots[18].out_uop.fcn_op \n connect issue_slots[17].in_uop.bits.fcn_dw, issue_slots[18].out_uop.fcn_dw \n connect issue_slots[17].in_uop.bits.frs3_en, issue_slots[18].out_uop.frs3_en \n connect issue_slots[17].in_uop.bits.lrs2_rtype, issue_slots[18].out_uop.lrs2_rtype \n connect issue_slots[17].in_uop.bits.lrs1_rtype, issue_slots[18].out_uop.lrs1_rtype \n connect issue_slots[17].in_uop.bits.dst_rtype, issue_slots[18].out_uop.dst_rtype \n connect issue_slots[17].in_uop.bits.lrs3, issue_slots[18].out_uop.lrs3 \n connect issue_slots[17].in_uop.bits.lrs2, issue_slots[18].out_uop.lrs2 \n connect issue_slots[17].in_uop.bits.lrs1, issue_slots[18].out_uop.lrs1 \n connect issue_slots[17].in_uop.bits.ldst, issue_slots[18].out_uop.ldst \n connect issue_slots[17].in_uop.bits.ldst_is_rs1, issue_slots[18].out_uop.ldst_is_rs1 \n connect issue_slots[17].in_uop.bits.csr_cmd, issue_slots[18].out_uop.csr_cmd \n connect issue_slots[17].in_uop.bits.flush_on_commit, issue_slots[18].out_uop.flush_on_commit \n connect issue_slots[17].in_uop.bits.is_unique, issue_slots[18].out_uop.is_unique \n connect issue_slots[17].in_uop.bits.uses_stq, issue_slots[18].out_uop.uses_stq \n connect issue_slots[17].in_uop.bits.uses_ldq, issue_slots[18].out_uop.uses_ldq \n connect issue_slots[17].in_uop.bits.mem_signed, issue_slots[18].out_uop.mem_signed \n connect issue_slots[17].in_uop.bits.mem_size, issue_slots[18].out_uop.mem_size \n connect issue_slots[17].in_uop.bits.mem_cmd, issue_slots[18].out_uop.mem_cmd \n connect issue_slots[17].in_uop.bits.exc_cause, issue_slots[18].out_uop.exc_cause \n connect issue_slots[17].in_uop.bits.exception, issue_slots[18].out_uop.exception \n connect issue_slots[17].in_uop.bits.stale_pdst, issue_slots[18].out_uop.stale_pdst \n connect issue_slots[17].in_uop.bits.ppred_busy, issue_slots[18].out_uop.ppred_busy \n connect issue_slots[17].in_uop.bits.prs3_busy, issue_slots[18].out_uop.prs3_busy \n connect issue_slots[17].in_uop.bits.prs2_busy, issue_slots[18].out_uop.prs2_busy \n connect issue_slots[17].in_uop.bits.prs1_busy, issue_slots[18].out_uop.prs1_busy \n connect issue_slots[17].in_uop.bits.ppred, issue_slots[18].out_uop.ppred \n connect issue_slots[17].in_uop.bits.prs3, issue_slots[18].out_uop.prs3 \n connect issue_slots[17].in_uop.bits.prs2, issue_slots[18].out_uop.prs2 \n connect issue_slots[17].in_uop.bits.prs1, issue_slots[18].out_uop.prs1 \n connect issue_slots[17].in_uop.bits.pdst, issue_slots[18].out_uop.pdst \n connect issue_slots[17].in_uop.bits.rxq_idx, issue_slots[18].out_uop.rxq_idx \n connect issue_slots[17].in_uop.bits.stq_idx, issue_slots[18].out_uop.stq_idx \n connect issue_slots[17].in_uop.bits.ldq_idx, issue_slots[18].out_uop.ldq_idx \n connect issue_slots[17].in_uop.bits.rob_idx, issue_slots[18].out_uop.rob_idx \n connect issue_slots[17].in_uop.bits.fp_ctrl.vec, issue_slots[18].out_uop.fp_ctrl.vec \n connect issue_slots[17].in_uop.bits.fp_ctrl.wflags, issue_slots[18].out_uop.fp_ctrl.wflags \n connect issue_slots[17].in_uop.bits.fp_ctrl.sqrt, issue_slots[18].out_uop.fp_ctrl.sqrt \n connect issue_slots[17].in_uop.bits.fp_ctrl.div, issue_slots[18].out_uop.fp_ctrl.div \n connect issue_slots[17].in_uop.bits.fp_ctrl.fma, issue_slots[18].out_uop.fp_ctrl.fma \n connect issue_slots[17].in_uop.bits.fp_ctrl.fastpipe, issue_slots[18].out_uop.fp_ctrl.fastpipe \n connect issue_slots[17].in_uop.bits.fp_ctrl.toint, issue_slots[18].out_uop.fp_ctrl.toint \n connect issue_slots[17].in_uop.bits.fp_ctrl.fromint, issue_slots[18].out_uop.fp_ctrl.fromint \n connect issue_slots[17].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[18].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[17].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[18].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[17].in_uop.bits.fp_ctrl.swap23, issue_slots[18].out_uop.fp_ctrl.swap23 \n connect issue_slots[17].in_uop.bits.fp_ctrl.swap12, issue_slots[18].out_uop.fp_ctrl.swap12 \n connect issue_slots[17].in_uop.bits.fp_ctrl.ren3, issue_slots[18].out_uop.fp_ctrl.ren3 \n connect issue_slots[17].in_uop.bits.fp_ctrl.ren2, issue_slots[18].out_uop.fp_ctrl.ren2 \n connect issue_slots[17].in_uop.bits.fp_ctrl.ren1, issue_slots[18].out_uop.fp_ctrl.ren1 \n connect issue_slots[17].in_uop.bits.fp_ctrl.wen, issue_slots[18].out_uop.fp_ctrl.wen \n connect issue_slots[17].in_uop.bits.fp_ctrl.ldst, issue_slots[18].out_uop.fp_ctrl.ldst \n connect issue_slots[17].in_uop.bits.op2_sel, issue_slots[18].out_uop.op2_sel \n connect issue_slots[17].in_uop.bits.op1_sel, issue_slots[18].out_uop.op1_sel \n connect issue_slots[17].in_uop.bits.imm_packed, issue_slots[18].out_uop.imm_packed \n connect issue_slots[17].in_uop.bits.pimm, issue_slots[18].out_uop.pimm \n connect issue_slots[17].in_uop.bits.imm_sel, issue_slots[18].out_uop.imm_sel \n connect issue_slots[17].in_uop.bits.imm_rename, issue_slots[18].out_uop.imm_rename \n connect issue_slots[17].in_uop.bits.taken, issue_slots[18].out_uop.taken \n connect issue_slots[17].in_uop.bits.pc_lob, issue_slots[18].out_uop.pc_lob \n connect issue_slots[17].in_uop.bits.edge_inst, issue_slots[18].out_uop.edge_inst \n connect issue_slots[17].in_uop.bits.ftq_idx, issue_slots[18].out_uop.ftq_idx \n connect issue_slots[17].in_uop.bits.is_mov, issue_slots[18].out_uop.is_mov \n connect issue_slots[17].in_uop.bits.is_rocc, issue_slots[18].out_uop.is_rocc \n connect issue_slots[17].in_uop.bits.is_sys_pc2epc, issue_slots[18].out_uop.is_sys_pc2epc \n connect issue_slots[17].in_uop.bits.is_eret, issue_slots[18].out_uop.is_eret \n connect issue_slots[17].in_uop.bits.is_amo, issue_slots[18].out_uop.is_amo \n connect issue_slots[17].in_uop.bits.is_sfence, issue_slots[18].out_uop.is_sfence \n connect issue_slots[17].in_uop.bits.is_fencei, issue_slots[18].out_uop.is_fencei \n connect issue_slots[17].in_uop.bits.is_fence, issue_slots[18].out_uop.is_fence \n connect issue_slots[17].in_uop.bits.is_sfb, issue_slots[18].out_uop.is_sfb \n connect issue_slots[17].in_uop.bits.br_type, issue_slots[18].out_uop.br_type \n connect issue_slots[17].in_uop.bits.br_tag, issue_slots[18].out_uop.br_tag \n connect issue_slots[17].in_uop.bits.br_mask, issue_slots[18].out_uop.br_mask \n connect issue_slots[17].in_uop.bits.dis_col_sel, issue_slots[18].out_uop.dis_col_sel \n connect issue_slots[17].in_uop.bits.iw_p3_bypass_hint, issue_slots[18].out_uop.iw_p3_bypass_hint \n connect issue_slots[17].in_uop.bits.iw_p2_bypass_hint, issue_slots[18].out_uop.iw_p2_bypass_hint \n connect issue_slots[17].in_uop.bits.iw_p1_bypass_hint, issue_slots[18].out_uop.iw_p1_bypass_hint \n connect issue_slots[17].in_uop.bits.iw_p2_speculative_child, issue_slots[18].out_uop.iw_p2_speculative_child \n connect issue_slots[17].in_uop.bits.iw_p1_speculative_child, issue_slots[18].out_uop.iw_p1_speculative_child \n connect issue_slots[17].in_uop.bits.iw_issued_partial_dgen, issue_slots[18].out_uop.iw_issued_partial_dgen \n connect issue_slots[17].in_uop.bits.iw_issued_partial_agen, issue_slots[18].out_uop.iw_issued_partial_agen \n connect issue_slots[17].in_uop.bits.iw_issued, issue_slots[18].out_uop.iw_issued \n connect issue_slots[17].in_uop.bits.fu_code[0], issue_slots[18].out_uop.fu_code[0] \n connect issue_slots[17].in_uop.bits.fu_code[1], issue_slots[18].out_uop.fu_code[1] \n connect issue_slots[17].in_uop.bits.fu_code[2], issue_slots[18].out_uop.fu_code[2] \n connect issue_slots[17].in_uop.bits.fu_code[3], issue_slots[18].out_uop.fu_code[3] \n connect issue_slots[17].in_uop.bits.fu_code[4], issue_slots[18].out_uop.fu_code[4] \n connect issue_slots[17].in_uop.bits.fu_code[5], issue_slots[18].out_uop.fu_code[5] \n connect issue_slots[17].in_uop.bits.fu_code[6], issue_slots[18].out_uop.fu_code[6] \n connect issue_slots[17].in_uop.bits.fu_code[7], issue_slots[18].out_uop.fu_code[7] \n connect issue_slots[17].in_uop.bits.fu_code[8], issue_slots[18].out_uop.fu_code[8] \n connect issue_slots[17].in_uop.bits.fu_code[9], issue_slots[18].out_uop.fu_code[9] \n connect issue_slots[17].in_uop.bits.iq_type[0], issue_slots[18].out_uop.iq_type[0] \n connect issue_slots[17].in_uop.bits.iq_type[1], issue_slots[18].out_uop.iq_type[1] \n connect issue_slots[17].in_uop.bits.iq_type[2], issue_slots[18].out_uop.iq_type[2] \n connect issue_slots[17].in_uop.bits.iq_type[3], issue_slots[18].out_uop.iq_type[3] \n connect issue_slots[17].in_uop.bits.debug_pc, issue_slots[18].out_uop.debug_pc \n connect issue_slots[17].in_uop.bits.is_rvc, issue_slots[18].out_uop.is_rvc \n connect issue_slots[17].in_uop.bits.debug_inst, issue_slots[18].out_uop.debug_inst \n connect issue_slots[17].in_uop.bits.inst, issue_slots[18].out_uop.inst \n node _T_197 = eq(shamts_oh[19], UInt<2>(0h2)) \n when _T_197 : \n connect issue_slots[17].in_uop.valid, issue_slots[19].will_be_valid \n connect issue_slots[17].in_uop.bits.debug_tsrc, issue_slots[19].out_uop.debug_tsrc \n connect issue_slots[17].in_uop.bits.debug_fsrc, issue_slots[19].out_uop.debug_fsrc \n connect issue_slots[17].in_uop.bits.bp_xcpt_if, issue_slots[19].out_uop.bp_xcpt_if \n connect issue_slots[17].in_uop.bits.bp_debug_if, issue_slots[19].out_uop.bp_debug_if \n connect issue_slots[17].in_uop.bits.xcpt_ma_if, issue_slots[19].out_uop.xcpt_ma_if \n connect issue_slots[17].in_uop.bits.xcpt_ae_if, issue_slots[19].out_uop.xcpt_ae_if \n connect issue_slots[17].in_uop.bits.xcpt_pf_if, issue_slots[19].out_uop.xcpt_pf_if \n connect issue_slots[17].in_uop.bits.fp_typ, issue_slots[19].out_uop.fp_typ \n connect issue_slots[17].in_uop.bits.fp_rm, issue_slots[19].out_uop.fp_rm \n connect issue_slots[17].in_uop.bits.fp_val, issue_slots[19].out_uop.fp_val \n connect issue_slots[17].in_uop.bits.fcn_op, issue_slots[19].out_uop.fcn_op \n connect issue_slots[17].in_uop.bits.fcn_dw, issue_slots[19].out_uop.fcn_dw \n connect issue_slots[17].in_uop.bits.frs3_en, issue_slots[19].out_uop.frs3_en \n connect issue_slots[17].in_uop.bits.lrs2_rtype, issue_slots[19].out_uop.lrs2_rtype \n connect issue_slots[17].in_uop.bits.lrs1_rtype, issue_slots[19].out_uop.lrs1_rtype \n connect issue_slots[17].in_uop.bits.dst_rtype, issue_slots[19].out_uop.dst_rtype \n connect issue_slots[17].in_uop.bits.lrs3, issue_slots[19].out_uop.lrs3 \n connect issue_slots[17].in_uop.bits.lrs2, issue_slots[19].out_uop.lrs2 \n connect issue_slots[17].in_uop.bits.lrs1, issue_slots[19].out_uop.lrs1 \n connect issue_slots[17].in_uop.bits.ldst, issue_slots[19].out_uop.ldst \n connect issue_slots[17].in_uop.bits.ldst_is_rs1, issue_slots[19].out_uop.ldst_is_rs1 \n connect issue_slots[17].in_uop.bits.csr_cmd, issue_slots[19].out_uop.csr_cmd \n connect issue_slots[17].in_uop.bits.flush_on_commit, issue_slots[19].out_uop.flush_on_commit \n connect issue_slots[17].in_uop.bits.is_unique, issue_slots[19].out_uop.is_unique \n connect issue_slots[17].in_uop.bits.uses_stq, issue_slots[19].out_uop.uses_stq \n connect issue_slots[17].in_uop.bits.uses_ldq, issue_slots[19].out_uop.uses_ldq \n connect issue_slots[17].in_uop.bits.mem_signed, issue_slots[19].out_uop.mem_signed \n connect issue_slots[17].in_uop.bits.mem_size, issue_slots[19].out_uop.mem_size \n connect issue_slots[17].in_uop.bits.mem_cmd, issue_slots[19].out_uop.mem_cmd \n connect issue_slots[17].in_uop.bits.exc_cause, issue_slots[19].out_uop.exc_cause \n connect issue_slots[17].in_uop.bits.exception, issue_slots[19].out_uop.exception \n connect issue_slots[17].in_uop.bits.stale_pdst, issue_slots[19].out_uop.stale_pdst \n connect issue_slots[17].in_uop.bits.ppred_busy, issue_slots[19].out_uop.ppred_busy \n connect issue_slots[17].in_uop.bits.prs3_busy, issue_slots[19].out_uop.prs3_busy \n connect issue_slots[17].in_uop.bits.prs2_busy, issue_slots[19].out_uop.prs2_busy \n connect issue_slots[17].in_uop.bits.prs1_busy, issue_slots[19].out_uop.prs1_busy \n connect issue_slots[17].in_uop.bits.ppred, issue_slots[19].out_uop.ppred \n connect issue_slots[17].in_uop.bits.prs3, issue_slots[19].out_uop.prs3 \n connect issue_slots[17].in_uop.bits.prs2, issue_slots[19].out_uop.prs2 \n connect issue_slots[17].in_uop.bits.prs1, issue_slots[19].out_uop.prs1 \n connect issue_slots[17].in_uop.bits.pdst, issue_slots[19].out_uop.pdst \n connect issue_slots[17].in_uop.bits.rxq_idx, issue_slots[19].out_uop.rxq_idx \n connect issue_slots[17].in_uop.bits.stq_idx, issue_slots[19].out_uop.stq_idx \n connect issue_slots[17].in_uop.bits.ldq_idx, issue_slots[19].out_uop.ldq_idx \n connect issue_slots[17].in_uop.bits.rob_idx, issue_slots[19].out_uop.rob_idx \n connect issue_slots[17].in_uop.bits.fp_ctrl.vec, issue_slots[19].out_uop.fp_ctrl.vec \n connect issue_slots[17].in_uop.bits.fp_ctrl.wflags, issue_slots[19].out_uop.fp_ctrl.wflags \n connect issue_slots[17].in_uop.bits.fp_ctrl.sqrt, issue_slots[19].out_uop.fp_ctrl.sqrt \n connect issue_slots[17].in_uop.bits.fp_ctrl.div, issue_slots[19].out_uop.fp_ctrl.div \n connect issue_slots[17].in_uop.bits.fp_ctrl.fma, issue_slots[19].out_uop.fp_ctrl.fma \n connect issue_slots[17].in_uop.bits.fp_ctrl.fastpipe, issue_slots[19].out_uop.fp_ctrl.fastpipe \n connect issue_slots[17].in_uop.bits.fp_ctrl.toint, issue_slots[19].out_uop.fp_ctrl.toint \n connect issue_slots[17].in_uop.bits.fp_ctrl.fromint, issue_slots[19].out_uop.fp_ctrl.fromint \n connect issue_slots[17].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[19].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[17].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[19].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[17].in_uop.bits.fp_ctrl.swap23, issue_slots[19].out_uop.fp_ctrl.swap23 \n connect issue_slots[17].in_uop.bits.fp_ctrl.swap12, issue_slots[19].out_uop.fp_ctrl.swap12 \n connect issue_slots[17].in_uop.bits.fp_ctrl.ren3, issue_slots[19].out_uop.fp_ctrl.ren3 \n connect issue_slots[17].in_uop.bits.fp_ctrl.ren2, issue_slots[19].out_uop.fp_ctrl.ren2 \n connect issue_slots[17].in_uop.bits.fp_ctrl.ren1, issue_slots[19].out_uop.fp_ctrl.ren1 \n connect issue_slots[17].in_uop.bits.fp_ctrl.wen, issue_slots[19].out_uop.fp_ctrl.wen \n connect issue_slots[17].in_uop.bits.fp_ctrl.ldst, issue_slots[19].out_uop.fp_ctrl.ldst \n connect issue_slots[17].in_uop.bits.op2_sel, issue_slots[19].out_uop.op2_sel \n connect issue_slots[17].in_uop.bits.op1_sel, issue_slots[19].out_uop.op1_sel \n connect issue_slots[17].in_uop.bits.imm_packed, issue_slots[19].out_uop.imm_packed \n connect issue_slots[17].in_uop.bits.pimm, issue_slots[19].out_uop.pimm \n connect issue_slots[17].in_uop.bits.imm_sel, issue_slots[19].out_uop.imm_sel \n connect issue_slots[17].in_uop.bits.imm_rename, issue_slots[19].out_uop.imm_rename \n connect issue_slots[17].in_uop.bits.taken, issue_slots[19].out_uop.taken \n connect issue_slots[17].in_uop.bits.pc_lob, issue_slots[19].out_uop.pc_lob \n connect issue_slots[17].in_uop.bits.edge_inst, issue_slots[19].out_uop.edge_inst \n connect issue_slots[17].in_uop.bits.ftq_idx, issue_slots[19].out_uop.ftq_idx \n connect issue_slots[17].in_uop.bits.is_mov, issue_slots[19].out_uop.is_mov \n connect issue_slots[17].in_uop.bits.is_rocc, issue_slots[19].out_uop.is_rocc \n connect issue_slots[17].in_uop.bits.is_sys_pc2epc, issue_slots[19].out_uop.is_sys_pc2epc \n connect issue_slots[17].in_uop.bits.is_eret, issue_slots[19].out_uop.is_eret \n connect issue_slots[17].in_uop.bits.is_amo, issue_slots[19].out_uop.is_amo \n connect issue_slots[17].in_uop.bits.is_sfence, issue_slots[19].out_uop.is_sfence \n connect issue_slots[17].in_uop.bits.is_fencei, issue_slots[19].out_uop.is_fencei \n connect issue_slots[17].in_uop.bits.is_fence, issue_slots[19].out_uop.is_fence \n connect issue_slots[17].in_uop.bits.is_sfb, issue_slots[19].out_uop.is_sfb \n connect issue_slots[17].in_uop.bits.br_type, issue_slots[19].out_uop.br_type \n connect issue_slots[17].in_uop.bits.br_tag, issue_slots[19].out_uop.br_tag \n connect issue_slots[17].in_uop.bits.br_mask, issue_slots[19].out_uop.br_mask \n connect issue_slots[17].in_uop.bits.dis_col_sel, issue_slots[19].out_uop.dis_col_sel \n connect issue_slots[17].in_uop.bits.iw_p3_bypass_hint, issue_slots[19].out_uop.iw_p3_bypass_hint \n connect issue_slots[17].in_uop.bits.iw_p2_bypass_hint, issue_slots[19].out_uop.iw_p2_bypass_hint \n connect issue_slots[17].in_uop.bits.iw_p1_bypass_hint, issue_slots[19].out_uop.iw_p1_bypass_hint \n connect issue_slots[17].in_uop.bits.iw_p2_speculative_child, issue_slots[19].out_uop.iw_p2_speculative_child \n connect issue_slots[17].in_uop.bits.iw_p1_speculative_child, issue_slots[19].out_uop.iw_p1_speculative_child \n connect issue_slots[17].in_uop.bits.iw_issued_partial_dgen, issue_slots[19].out_uop.iw_issued_partial_dgen \n connect issue_slots[17].in_uop.bits.iw_issued_partial_agen, issue_slots[19].out_uop.iw_issued_partial_agen \n connect issue_slots[17].in_uop.bits.iw_issued, issue_slots[19].out_uop.iw_issued \n connect issue_slots[17].in_uop.bits.fu_code[0], issue_slots[19].out_uop.fu_code[0] \n connect issue_slots[17].in_uop.bits.fu_code[1], issue_slots[19].out_uop.fu_code[1] \n connect issue_slots[17].in_uop.bits.fu_code[2], issue_slots[19].out_uop.fu_code[2] \n connect issue_slots[17].in_uop.bits.fu_code[3], issue_slots[19].out_uop.fu_code[3] \n connect issue_slots[17].in_uop.bits.fu_code[4], issue_slots[19].out_uop.fu_code[4] \n connect issue_slots[17].in_uop.bits.fu_code[5], issue_slots[19].out_uop.fu_code[5] \n connect issue_slots[17].in_uop.bits.fu_code[6], issue_slots[19].out_uop.fu_code[6] \n connect issue_slots[17].in_uop.bits.fu_code[7], issue_slots[19].out_uop.fu_code[7] \n connect issue_slots[17].in_uop.bits.fu_code[8], issue_slots[19].out_uop.fu_code[8] \n connect issue_slots[17].in_uop.bits.fu_code[9], issue_slots[19].out_uop.fu_code[9] \n connect issue_slots[17].in_uop.bits.iq_type[0], issue_slots[19].out_uop.iq_type[0] \n connect issue_slots[17].in_uop.bits.iq_type[1], issue_slots[19].out_uop.iq_type[1] \n connect issue_slots[17].in_uop.bits.iq_type[2], issue_slots[19].out_uop.iq_type[2] \n connect issue_slots[17].in_uop.bits.iq_type[3], issue_slots[19].out_uop.iq_type[3] \n connect issue_slots[17].in_uop.bits.debug_pc, issue_slots[19].out_uop.debug_pc \n connect issue_slots[17].in_uop.bits.is_rvc, issue_slots[19].out_uop.is_rvc \n connect issue_slots[17].in_uop.bits.debug_inst, issue_slots[19].out_uop.debug_inst \n connect issue_slots[17].in_uop.bits.inst, issue_slots[19].out_uop.inst \n node _issue_slots_17_clear_T = neq(shamts_oh[17], UInt<1>(0h0)) \n connect issue_slots[17].clear, _issue_slots_17_clear_T \n connect issue_slots[18].in_uop.valid, UInt<1>(0h0) \n connect issue_slots[18].in_uop.bits.debug_tsrc, issue_slots[19].out_uop.debug_tsrc \n connect issue_slots[18].in_uop.bits.debug_fsrc, issue_slots[19].out_uop.debug_fsrc \n connect issue_slots[18].in_uop.bits.bp_xcpt_if, issue_slots[19].out_uop.bp_xcpt_if \n connect issue_slots[18].in_uop.bits.bp_debug_if, issue_slots[19].out_uop.bp_debug_if \n connect issue_slots[18].in_uop.bits.xcpt_ma_if, issue_slots[19].out_uop.xcpt_ma_if \n connect issue_slots[18].in_uop.bits.xcpt_ae_if, issue_slots[19].out_uop.xcpt_ae_if \n connect issue_slots[18].in_uop.bits.xcpt_pf_if, issue_slots[19].out_uop.xcpt_pf_if \n connect issue_slots[18].in_uop.bits.fp_typ, issue_slots[19].out_uop.fp_typ \n connect issue_slots[18].in_uop.bits.fp_rm, issue_slots[19].out_uop.fp_rm \n connect issue_slots[18].in_uop.bits.fp_val, issue_slots[19].out_uop.fp_val \n connect issue_slots[18].in_uop.bits.fcn_op, issue_slots[19].out_uop.fcn_op \n connect issue_slots[18].in_uop.bits.fcn_dw, issue_slots[19].out_uop.fcn_dw \n connect issue_slots[18].in_uop.bits.frs3_en, issue_slots[19].out_uop.frs3_en \n connect issue_slots[18].in_uop.bits.lrs2_rtype, issue_slots[19].out_uop.lrs2_rtype \n connect issue_slots[18].in_uop.bits.lrs1_rtype, issue_slots[19].out_uop.lrs1_rtype \n connect issue_slots[18].in_uop.bits.dst_rtype, issue_slots[19].out_uop.dst_rtype \n connect issue_slots[18].in_uop.bits.lrs3, issue_slots[19].out_uop.lrs3 \n connect issue_slots[18].in_uop.bits.lrs2, issue_slots[19].out_uop.lrs2 \n connect issue_slots[18].in_uop.bits.lrs1, issue_slots[19].out_uop.lrs1 \n connect issue_slots[18].in_uop.bits.ldst, issue_slots[19].out_uop.ldst \n connect issue_slots[18].in_uop.bits.ldst_is_rs1, issue_slots[19].out_uop.ldst_is_rs1 \n connect issue_slots[18].in_uop.bits.csr_cmd, issue_slots[19].out_uop.csr_cmd \n connect issue_slots[18].in_uop.bits.flush_on_commit, issue_slots[19].out_uop.flush_on_commit \n connect issue_slots[18].in_uop.bits.is_unique, issue_slots[19].out_uop.is_unique \n connect issue_slots[18].in_uop.bits.uses_stq, issue_slots[19].out_uop.uses_stq \n connect issue_slots[18].in_uop.bits.uses_ldq, issue_slots[19].out_uop.uses_ldq \n connect issue_slots[18].in_uop.bits.mem_signed, issue_slots[19].out_uop.mem_signed \n connect issue_slots[18].in_uop.bits.mem_size, issue_slots[19].out_uop.mem_size \n connect issue_slots[18].in_uop.bits.mem_cmd, issue_slots[19].out_uop.mem_cmd \n connect issue_slots[18].in_uop.bits.exc_cause, issue_slots[19].out_uop.exc_cause \n connect issue_slots[18].in_uop.bits.exception, issue_slots[19].out_uop.exception \n connect issue_slots[18].in_uop.bits.stale_pdst, issue_slots[19].out_uop.stale_pdst \n connect issue_slots[18].in_uop.bits.ppred_busy, issue_slots[19].out_uop.ppred_busy \n connect issue_slots[18].in_uop.bits.prs3_busy, issue_slots[19].out_uop.prs3_busy \n connect issue_slots[18].in_uop.bits.prs2_busy, issue_slots[19].out_uop.prs2_busy \n connect issue_slots[18].in_uop.bits.prs1_busy, issue_slots[19].out_uop.prs1_busy \n connect issue_slots[18].in_uop.bits.ppred, issue_slots[19].out_uop.ppred \n connect issue_slots[18].in_uop.bits.prs3, issue_slots[19].out_uop.prs3 \n connect issue_slots[18].in_uop.bits.prs2, issue_slots[19].out_uop.prs2 \n connect issue_slots[18].in_uop.bits.prs1, issue_slots[19].out_uop.prs1 \n connect issue_slots[18].in_uop.bits.pdst, issue_slots[19].out_uop.pdst \n connect issue_slots[18].in_uop.bits.rxq_idx, issue_slots[19].out_uop.rxq_idx \n connect issue_slots[18].in_uop.bits.stq_idx, issue_slots[19].out_uop.stq_idx \n connect issue_slots[18].in_uop.bits.ldq_idx, issue_slots[19].out_uop.ldq_idx \n connect issue_slots[18].in_uop.bits.rob_idx, issue_slots[19].out_uop.rob_idx \n connect issue_slots[18].in_uop.bits.fp_ctrl.vec, issue_slots[19].out_uop.fp_ctrl.vec \n connect issue_slots[18].in_uop.bits.fp_ctrl.wflags, issue_slots[19].out_uop.fp_ctrl.wflags \n connect issue_slots[18].in_uop.bits.fp_ctrl.sqrt, issue_slots[19].out_uop.fp_ctrl.sqrt \n connect issue_slots[18].in_uop.bits.fp_ctrl.div, issue_slots[19].out_uop.fp_ctrl.div \n connect issue_slots[18].in_uop.bits.fp_ctrl.fma, issue_slots[19].out_uop.fp_ctrl.fma \n connect issue_slots[18].in_uop.bits.fp_ctrl.fastpipe, issue_slots[19].out_uop.fp_ctrl.fastpipe \n connect issue_slots[18].in_uop.bits.fp_ctrl.toint, issue_slots[19].out_uop.fp_ctrl.toint \n connect issue_slots[18].in_uop.bits.fp_ctrl.fromint, issue_slots[19].out_uop.fp_ctrl.fromint \n connect issue_slots[18].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[19].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[18].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[19].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[18].in_uop.bits.fp_ctrl.swap23, issue_slots[19].out_uop.fp_ctrl.swap23 \n connect issue_slots[18].in_uop.bits.fp_ctrl.swap12, issue_slots[19].out_uop.fp_ctrl.swap12 \n connect issue_slots[18].in_uop.bits.fp_ctrl.ren3, issue_slots[19].out_uop.fp_ctrl.ren3 \n connect issue_slots[18].in_uop.bits.fp_ctrl.ren2, issue_slots[19].out_uop.fp_ctrl.ren2 \n connect issue_slots[18].in_uop.bits.fp_ctrl.ren1, issue_slots[19].out_uop.fp_ctrl.ren1 \n connect issue_slots[18].in_uop.bits.fp_ctrl.wen, issue_slots[19].out_uop.fp_ctrl.wen \n connect issue_slots[18].in_uop.bits.fp_ctrl.ldst, issue_slots[19].out_uop.fp_ctrl.ldst \n connect issue_slots[18].in_uop.bits.op2_sel, issue_slots[19].out_uop.op2_sel \n connect issue_slots[18].in_uop.bits.op1_sel, issue_slots[19].out_uop.op1_sel \n connect issue_slots[18].in_uop.bits.imm_packed, issue_slots[19].out_uop.imm_packed \n connect issue_slots[18].in_uop.bits.pimm, issue_slots[19].out_uop.pimm \n connect issue_slots[18].in_uop.bits.imm_sel, issue_slots[19].out_uop.imm_sel \n connect issue_slots[18].in_uop.bits.imm_rename, issue_slots[19].out_uop.imm_rename \n connect issue_slots[18].in_uop.bits.taken, issue_slots[19].out_uop.taken \n connect issue_slots[18].in_uop.bits.pc_lob, issue_slots[19].out_uop.pc_lob \n connect issue_slots[18].in_uop.bits.edge_inst, issue_slots[19].out_uop.edge_inst \n connect issue_slots[18].in_uop.bits.ftq_idx, issue_slots[19].out_uop.ftq_idx \n connect issue_slots[18].in_uop.bits.is_mov, issue_slots[19].out_uop.is_mov \n connect issue_slots[18].in_uop.bits.is_rocc, issue_slots[19].out_uop.is_rocc \n connect issue_slots[18].in_uop.bits.is_sys_pc2epc, issue_slots[19].out_uop.is_sys_pc2epc \n connect issue_slots[18].in_uop.bits.is_eret, issue_slots[19].out_uop.is_eret \n connect issue_slots[18].in_uop.bits.is_amo, issue_slots[19].out_uop.is_amo \n connect issue_slots[18].in_uop.bits.is_sfence, issue_slots[19].out_uop.is_sfence \n connect issue_slots[18].in_uop.bits.is_fencei, issue_slots[19].out_uop.is_fencei \n connect issue_slots[18].in_uop.bits.is_fence, issue_slots[19].out_uop.is_fence \n connect issue_slots[18].in_uop.bits.is_sfb, issue_slots[19].out_uop.is_sfb \n connect issue_slots[18].in_uop.bits.br_type, issue_slots[19].out_uop.br_type \n connect issue_slots[18].in_uop.bits.br_tag, issue_slots[19].out_uop.br_tag \n connect issue_slots[18].in_uop.bits.br_mask, issue_slots[19].out_uop.br_mask \n connect issue_slots[18].in_uop.bits.dis_col_sel, issue_slots[19].out_uop.dis_col_sel \n connect issue_slots[18].in_uop.bits.iw_p3_bypass_hint, issue_slots[19].out_uop.iw_p3_bypass_hint \n connect issue_slots[18].in_uop.bits.iw_p2_bypass_hint, issue_slots[19].out_uop.iw_p2_bypass_hint \n connect issue_slots[18].in_uop.bits.iw_p1_bypass_hint, issue_slots[19].out_uop.iw_p1_bypass_hint \n connect issue_slots[18].in_uop.bits.iw_p2_speculative_child, issue_slots[19].out_uop.iw_p2_speculative_child \n connect issue_slots[18].in_uop.bits.iw_p1_speculative_child, issue_slots[19].out_uop.iw_p1_speculative_child \n connect issue_slots[18].in_uop.bits.iw_issued_partial_dgen, issue_slots[19].out_uop.iw_issued_partial_dgen \n connect issue_slots[18].in_uop.bits.iw_issued_partial_agen, issue_slots[19].out_uop.iw_issued_partial_agen \n connect issue_slots[18].in_uop.bits.iw_issued, issue_slots[19].out_uop.iw_issued \n connect issue_slots[18].in_uop.bits.fu_code[0], issue_slots[19].out_uop.fu_code[0] \n connect issue_slots[18].in_uop.bits.fu_code[1], issue_slots[19].out_uop.fu_code[1] \n connect issue_slots[18].in_uop.bits.fu_code[2], issue_slots[19].out_uop.fu_code[2] \n connect issue_slots[18].in_uop.bits.fu_code[3], issue_slots[19].out_uop.fu_code[3] \n connect issue_slots[18].in_uop.bits.fu_code[4], issue_slots[19].out_uop.fu_code[4] \n connect issue_slots[18].in_uop.bits.fu_code[5], issue_slots[19].out_uop.fu_code[5] \n connect issue_slots[18].in_uop.bits.fu_code[6], issue_slots[19].out_uop.fu_code[6] \n connect issue_slots[18].in_uop.bits.fu_code[7], issue_slots[19].out_uop.fu_code[7] \n connect issue_slots[18].in_uop.bits.fu_code[8], issue_slots[19].out_uop.fu_code[8] \n connect issue_slots[18].in_uop.bits.fu_code[9], issue_slots[19].out_uop.fu_code[9] \n connect issue_slots[18].in_uop.bits.iq_type[0], issue_slots[19].out_uop.iq_type[0] \n connect issue_slots[18].in_uop.bits.iq_type[1], issue_slots[19].out_uop.iq_type[1] \n connect issue_slots[18].in_uop.bits.iq_type[2], issue_slots[19].out_uop.iq_type[2] \n connect issue_slots[18].in_uop.bits.iq_type[3], issue_slots[19].out_uop.iq_type[3] \n connect issue_slots[18].in_uop.bits.debug_pc, issue_slots[19].out_uop.debug_pc \n connect issue_slots[18].in_uop.bits.is_rvc, issue_slots[19].out_uop.is_rvc \n connect issue_slots[18].in_uop.bits.debug_inst, issue_slots[19].out_uop.debug_inst \n connect issue_slots[18].in_uop.bits.inst, issue_slots[19].out_uop.inst \n node _T_198 = eq(shamts_oh[19], UInt<1>(0h1)) \n when _T_198 : \n connect issue_slots[18].in_uop.valid, issue_slots[19].will_be_valid \n connect issue_slots[18].in_uop.bits.debug_tsrc, issue_slots[19].out_uop.debug_tsrc \n connect issue_slots[18].in_uop.bits.debug_fsrc, issue_slots[19].out_uop.debug_fsrc \n connect issue_slots[18].in_uop.bits.bp_xcpt_if, issue_slots[19].out_uop.bp_xcpt_if \n connect issue_slots[18].in_uop.bits.bp_debug_if, issue_slots[19].out_uop.bp_debug_if \n connect issue_slots[18].in_uop.bits.xcpt_ma_if, issue_slots[19].out_uop.xcpt_ma_if \n connect issue_slots[18].in_uop.bits.xcpt_ae_if, issue_slots[19].out_uop.xcpt_ae_if \n connect issue_slots[18].in_uop.bits.xcpt_pf_if, issue_slots[19].out_uop.xcpt_pf_if \n connect issue_slots[18].in_uop.bits.fp_typ, issue_slots[19].out_uop.fp_typ \n connect issue_slots[18].in_uop.bits.fp_rm, issue_slots[19].out_uop.fp_rm \n connect issue_slots[18].in_uop.bits.fp_val, issue_slots[19].out_uop.fp_val \n connect issue_slots[18].in_uop.bits.fcn_op, issue_slots[19].out_uop.fcn_op \n connect issue_slots[18].in_uop.bits.fcn_dw, issue_slots[19].out_uop.fcn_dw \n connect issue_slots[18].in_uop.bits.frs3_en, issue_slots[19].out_uop.frs3_en \n connect issue_slots[18].in_uop.bits.lrs2_rtype, issue_slots[19].out_uop.lrs2_rtype \n connect issue_slots[18].in_uop.bits.lrs1_rtype, issue_slots[19].out_uop.lrs1_rtype \n connect issue_slots[18].in_uop.bits.dst_rtype, issue_slots[19].out_uop.dst_rtype \n connect issue_slots[18].in_uop.bits.lrs3, issue_slots[19].out_uop.lrs3 \n connect issue_slots[18].in_uop.bits.lrs2, issue_slots[19].out_uop.lrs2 \n connect issue_slots[18].in_uop.bits.lrs1, issue_slots[19].out_uop.lrs1 \n connect issue_slots[18].in_uop.bits.ldst, issue_slots[19].out_uop.ldst \n connect issue_slots[18].in_uop.bits.ldst_is_rs1, issue_slots[19].out_uop.ldst_is_rs1 \n connect issue_slots[18].in_uop.bits.csr_cmd, issue_slots[19].out_uop.csr_cmd \n connect issue_slots[18].in_uop.bits.flush_on_commit, issue_slots[19].out_uop.flush_on_commit \n connect issue_slots[18].in_uop.bits.is_unique, issue_slots[19].out_uop.is_unique \n connect issue_slots[18].in_uop.bits.uses_stq, issue_slots[19].out_uop.uses_stq \n connect issue_slots[18].in_uop.bits.uses_ldq, issue_slots[19].out_uop.uses_ldq \n connect issue_slots[18].in_uop.bits.mem_signed, issue_slots[19].out_uop.mem_signed \n connect issue_slots[18].in_uop.bits.mem_size, issue_slots[19].out_uop.mem_size \n connect issue_slots[18].in_uop.bits.mem_cmd, issue_slots[19].out_uop.mem_cmd \n connect issue_slots[18].in_uop.bits.exc_cause, issue_slots[19].out_uop.exc_cause \n connect issue_slots[18].in_uop.bits.exception, issue_slots[19].out_uop.exception \n connect issue_slots[18].in_uop.bits.stale_pdst, issue_slots[19].out_uop.stale_pdst \n connect issue_slots[18].in_uop.bits.ppred_busy, issue_slots[19].out_uop.ppred_busy \n connect issue_slots[18].in_uop.bits.prs3_busy, issue_slots[19].out_uop.prs3_busy \n connect issue_slots[18].in_uop.bits.prs2_busy, issue_slots[19].out_uop.prs2_busy \n connect issue_slots[18].in_uop.bits.prs1_busy, issue_slots[19].out_uop.prs1_busy \n connect issue_slots[18].in_uop.bits.ppred, issue_slots[19].out_uop.ppred \n connect issue_slots[18].in_uop.bits.prs3, issue_slots[19].out_uop.prs3 \n connect issue_slots[18].in_uop.bits.prs2, issue_slots[19].out_uop.prs2 \n connect issue_slots[18].in_uop.bits.prs1, issue_slots[19].out_uop.prs1 \n connect issue_slots[18].in_uop.bits.pdst, issue_slots[19].out_uop.pdst \n connect issue_slots[18].in_uop.bits.rxq_idx, issue_slots[19].out_uop.rxq_idx \n connect issue_slots[18].in_uop.bits.stq_idx, issue_slots[19].out_uop.stq_idx \n connect issue_slots[18].in_uop.bits.ldq_idx, issue_slots[19].out_uop.ldq_idx \n connect issue_slots[18].in_uop.bits.rob_idx, issue_slots[19].out_uop.rob_idx \n connect issue_slots[18].in_uop.bits.fp_ctrl.vec, issue_slots[19].out_uop.fp_ctrl.vec \n connect issue_slots[18].in_uop.bits.fp_ctrl.wflags, issue_slots[19].out_uop.fp_ctrl.wflags \n connect issue_slots[18].in_uop.bits.fp_ctrl.sqrt, issue_slots[19].out_uop.fp_ctrl.sqrt \n connect issue_slots[18].in_uop.bits.fp_ctrl.div, issue_slots[19].out_uop.fp_ctrl.div \n connect issue_slots[18].in_uop.bits.fp_ctrl.fma, issue_slots[19].out_uop.fp_ctrl.fma \n connect issue_slots[18].in_uop.bits.fp_ctrl.fastpipe, issue_slots[19].out_uop.fp_ctrl.fastpipe \n connect issue_slots[18].in_uop.bits.fp_ctrl.toint, issue_slots[19].out_uop.fp_ctrl.toint \n connect issue_slots[18].in_uop.bits.fp_ctrl.fromint, issue_slots[19].out_uop.fp_ctrl.fromint \n connect issue_slots[18].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[19].out_uop.fp_ctrl.typeTagOut \n connect issue_slots[18].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[19].out_uop.fp_ctrl.typeTagIn \n connect issue_slots[18].in_uop.bits.fp_ctrl.swap23, issue_slots[19].out_uop.fp_ctrl.swap23 \n connect issue_slots[18].in_uop.bits.fp_ctrl.swap12, issue_slots[19].out_uop.fp_ctrl.swap12 \n connect issue_slots[18].in_uop.bits.fp_ctrl.ren3, issue_slots[19].out_uop.fp_ctrl.ren3 \n connect issue_slots[18].in_uop.bits.fp_ctrl.ren2, issue_slots[19].out_uop.fp_ctrl.ren2 \n connect issue_slots[18].in_uop.bits.fp_ctrl.ren1, issue_slots[19].out_uop.fp_ctrl.ren1 \n connect issue_slots[18].in_uop.bits.fp_ctrl.wen, issue_slots[19].out_uop.fp_ctrl.wen \n connect issue_slots[18].in_uop.bits.fp_ctrl.ldst, issue_slots[19].out_uop.fp_ctrl.ldst \n connect issue_slots[18].in_uop.bits.op2_sel, issue_slots[19].out_uop.op2_sel \n connect issue_slots[18].in_uop.bits.op1_sel, issue_slots[19].out_uop.op1_sel \n connect issue_slots[18].in_uop.bits.imm_packed, issue_slots[19].out_uop.imm_packed \n connect issue_slots[18].in_uop.bits.pimm, issue_slots[19].out_uop.pimm \n connect issue_slots[18].in_uop.bits.imm_sel, issue_slots[19].out_uop.imm_sel \n connect issue_slots[18].in_uop.bits.imm_rename, issue_slots[19].out_uop.imm_rename \n connect issue_slots[18].in_uop.bits.taken, issue_slots[19].out_uop.taken \n connect issue_slots[18].in_uop.bits.pc_lob, issue_slots[19].out_uop.pc_lob \n connect issue_slots[18].in_uop.bits.edge_inst, issue_slots[19].out_uop.edge_inst \n connect issue_slots[18].in_uop.bits.ftq_idx, issue_slots[19].out_uop.ftq_idx \n connect issue_slots[18].in_uop.bits.is_mov, issue_slots[19].out_uop.is_mov \n connect issue_slots[18].in_uop.bits.is_rocc, issue_slots[19].out_uop.is_rocc \n connect issue_slots[18].in_uop.bits.is_sys_pc2epc, issue_slots[19].out_uop.is_sys_pc2epc \n connect issue_slots[18].in_uop.bits.is_eret, issue_slots[19].out_uop.is_eret \n connect issue_slots[18].in_uop.bits.is_amo, issue_slots[19].out_uop.is_amo \n connect issue_slots[18].in_uop.bits.is_sfence, issue_slots[19].out_uop.is_sfence \n connect issue_slots[18].in_uop.bits.is_fencei, issue_slots[19].out_uop.is_fencei \n connect issue_slots[18].in_uop.bits.is_fence, issue_slots[19].out_uop.is_fence \n connect issue_slots[18].in_uop.bits.is_sfb, issue_slots[19].out_uop.is_sfb \n connect issue_slots[18].in_uop.bits.br_type, issue_slots[19].out_uop.br_type \n connect issue_slots[18].in_uop.bits.br_tag, issue_slots[19].out_uop.br_tag \n connect issue_slots[18].in_uop.bits.br_mask, issue_slots[19].out_uop.br_mask \n connect issue_slots[18].in_uop.bits.dis_col_sel, issue_slots[19].out_uop.dis_col_sel \n connect issue_slots[18].in_uop.bits.iw_p3_bypass_hint, issue_slots[19].out_uop.iw_p3_bypass_hint \n connect issue_slots[18].in_uop.bits.iw_p2_bypass_hint, issue_slots[19].out_uop.iw_p2_bypass_hint \n connect issue_slots[18].in_uop.bits.iw_p1_bypass_hint, issue_slots[19].out_uop.iw_p1_bypass_hint \n connect issue_slots[18].in_uop.bits.iw_p2_speculative_child, issue_slots[19].out_uop.iw_p2_speculative_child \n connect issue_slots[18].in_uop.bits.iw_p1_speculative_child, issue_slots[19].out_uop.iw_p1_speculative_child \n connect issue_slots[18].in_uop.bits.iw_issued_partial_dgen, issue_slots[19].out_uop.iw_issued_partial_dgen \n connect issue_slots[18].in_uop.bits.iw_issued_partial_agen, issue_slots[19].out_uop.iw_issued_partial_agen \n connect issue_slots[18].in_uop.bits.iw_issued, issue_slots[19].out_uop.iw_issued \n connect issue_slots[18].in_uop.bits.fu_code[0], issue_slots[19].out_uop.fu_code[0] \n connect issue_slots[18].in_uop.bits.fu_code[1], issue_slots[19].out_uop.fu_code[1] \n connect issue_slots[18].in_uop.bits.fu_code[2], issue_slots[19].out_uop.fu_code[2] \n connect issue_slots[18].in_uop.bits.fu_code[3], issue_slots[19].out_uop.fu_code[3] \n connect issue_slots[18].in_uop.bits.fu_code[4], issue_slots[19].out_uop.fu_code[4] \n connect issue_slots[18].in_uop.bits.fu_code[5], issue_slots[19].out_uop.fu_code[5] \n connect issue_slots[18].in_uop.bits.fu_code[6], issue_slots[19].out_uop.fu_code[6] \n connect issue_slots[18].in_uop.bits.fu_code[7], issue_slots[19].out_uop.fu_code[7] \n connect issue_slots[18].in_uop.bits.fu_code[8], issue_slots[19].out_uop.fu_code[8] \n connect issue_slots[18].in_uop.bits.fu_code[9], issue_slots[19].out_uop.fu_code[9] \n connect issue_slots[18].in_uop.bits.iq_type[0], issue_slots[19].out_uop.iq_type[0] \n connect issue_slots[18].in_uop.bits.iq_type[1], issue_slots[19].out_uop.iq_type[1] \n connect issue_slots[18].in_uop.bits.iq_type[2], issue_slots[19].out_uop.iq_type[2] \n connect issue_slots[18].in_uop.bits.iq_type[3], issue_slots[19].out_uop.iq_type[3] \n connect issue_slots[18].in_uop.bits.debug_pc, issue_slots[19].out_uop.debug_pc \n connect issue_slots[18].in_uop.bits.is_rvc, issue_slots[19].out_uop.is_rvc \n connect issue_slots[18].in_uop.bits.debug_inst, issue_slots[19].out_uop.debug_inst \n connect issue_slots[18].in_uop.bits.inst, issue_slots[19].out_uop.inst \n node _T_199 = eq(shamts_oh[20], UInt<2>(0h2)) \n when _T_199 : \n connect issue_slots[18].in_uop.valid, will_be_valid_20 \n connect issue_slots[18].in_uop.bits.debug_tsrc, _WIRE.debug_tsrc \n connect issue_slots[18].in_uop.bits.debug_fsrc, _WIRE.debug_fsrc \n connect issue_slots[18].in_uop.bits.bp_xcpt_if, _WIRE.bp_xcpt_if \n connect issue_slots[18].in_uop.bits.bp_debug_if, _WIRE.bp_debug_if \n connect issue_slots[18].in_uop.bits.xcpt_ma_if, _WIRE.xcpt_ma_if \n connect issue_slots[18].in_uop.bits.xcpt_ae_if, _WIRE.xcpt_ae_if \n connect issue_slots[18].in_uop.bits.xcpt_pf_if, _WIRE.xcpt_pf_if \n connect issue_slots[18].in_uop.bits.fp_typ, _WIRE.fp_typ \n connect issue_slots[18].in_uop.bits.fp_rm, _WIRE.fp_rm \n connect issue_slots[18].in_uop.bits.fp_val, _WIRE.fp_val \n connect issue_slots[18].in_uop.bits.fcn_op, _WIRE.fcn_op \n connect issue_slots[18].in_uop.bits.fcn_dw, _WIRE.fcn_dw \n connect issue_slots[18].in_uop.bits.frs3_en, _WIRE.frs3_en \n connect issue_slots[18].in_uop.bits.lrs2_rtype, _WIRE.lrs2_rtype \n connect issue_slots[18].in_uop.bits.lrs1_rtype, _WIRE.lrs1_rtype \n connect issue_slots[18].in_uop.bits.dst_rtype, _WIRE.dst_rtype \n connect issue_slots[18].in_uop.bits.lrs3, _WIRE.lrs3 \n connect issue_slots[18].in_uop.bits.lrs2, _WIRE.lrs2 \n connect issue_slots[18].in_uop.bits.lrs1, _WIRE.lrs1 \n connect issue_slots[18].in_uop.bits.ldst, _WIRE.ldst \n connect issue_slots[18].in_uop.bits.ldst_is_rs1, _WIRE.ldst_is_rs1 \n connect issue_slots[18].in_uop.bits.csr_cmd, _WIRE.csr_cmd \n connect issue_slots[18].in_uop.bits.flush_on_commit, _WIRE.flush_on_commit \n connect issue_slots[18].in_uop.bits.is_unique, _WIRE.is_unique \n connect issue_slots[18].in_uop.bits.uses_stq, _WIRE.uses_stq \n connect issue_slots[18].in_uop.bits.uses_ldq, _WIRE.uses_ldq \n connect issue_slots[18].in_uop.bits.mem_signed, _WIRE.mem_signed \n connect issue_slots[18].in_uop.bits.mem_size, _WIRE.mem_size \n connect issue_slots[18].in_uop.bits.mem_cmd, _WIRE.mem_cmd \n connect issue_slots[18].in_uop.bits.exc_cause, _WIRE.exc_cause \n connect issue_slots[18].in_uop.bits.exception, _WIRE.exception \n connect issue_slots[18].in_uop.bits.stale_pdst, _WIRE.stale_pdst \n connect issue_slots[18].in_uop.bits.ppred_busy, _WIRE.ppred_busy \n connect issue_slots[18].in_uop.bits.prs3_busy, _WIRE.prs3_busy \n connect issue_slots[18].in_uop.bits.prs2_busy, _WIRE.prs2_busy \n connect issue_slots[18].in_uop.bits.prs1_busy, _WIRE.prs1_busy \n connect issue_slots[18].in_uop.bits.ppred, _WIRE.ppred \n connect issue_slots[18].in_uop.bits.prs3, _WIRE.prs3 \n connect issue_slots[18].in_uop.bits.prs2, _WIRE.prs2 \n connect issue_slots[18].in_uop.bits.prs1, _WIRE.prs1 \n connect issue_slots[18].in_uop.bits.pdst, _WIRE.pdst \n connect issue_slots[18].in_uop.bits.rxq_idx, _WIRE.rxq_idx \n connect issue_slots[18].in_uop.bits.stq_idx, _WIRE.stq_idx \n connect issue_slots[18].in_uop.bits.ldq_idx, _WIRE.ldq_idx \n connect issue_slots[18].in_uop.bits.rob_idx, _WIRE.rob_idx \n connect issue_slots[18].in_uop.bits.fp_ctrl.vec, _WIRE.fp_ctrl.vec \n connect issue_slots[18].in_uop.bits.fp_ctrl.wflags, _WIRE.fp_ctrl.wflags \n connect issue_slots[18].in_uop.bits.fp_ctrl.sqrt, _WIRE.fp_ctrl.sqrt \n connect issue_slots[18].in_uop.bits.fp_ctrl.div, _WIRE.fp_ctrl.div \n connect issue_slots[18].in_uop.bits.fp_ctrl.fma, _WIRE.fp_ctrl.fma \n connect issue_slots[18].in_uop.bits.fp_ctrl.fastpipe, _WIRE.fp_ctrl.fastpipe \n connect issue_slots[18].in_uop.bits.fp_ctrl.toint, _WIRE.fp_ctrl.toint \n connect issue_slots[18].in_uop.bits.fp_ctrl.fromint, _WIRE.fp_ctrl.fromint \n connect issue_slots[18].in_uop.bits.fp_ctrl.typeTagOut, _WIRE.fp_ctrl.typeTagOut \n connect issue_slots[18].in_uop.bits.fp_ctrl.typeTagIn, _WIRE.fp_ctrl.typeTagIn \n connect issue_slots[18].in_uop.bits.fp_ctrl.swap23, _WIRE.fp_ctrl.swap23 \n connect issue_slots[18].in_uop.bits.fp_ctrl.swap12, _WIRE.fp_ctrl.swap12 \n connect issue_slots[18].in_uop.bits.fp_ctrl.ren3, _WIRE.fp_ctrl.ren3 \n connect issue_slots[18].in_uop.bits.fp_ctrl.ren2, _WIRE.fp_ctrl.ren2 \n connect issue_slots[18].in_uop.bits.fp_ctrl.ren1, _WIRE.fp_ctrl.ren1 \n connect issue_slots[18].in_uop.bits.fp_ctrl.wen, _WIRE.fp_ctrl.wen \n connect issue_slots[18].in_uop.bits.fp_ctrl.ldst, _WIRE.fp_ctrl.ldst \n connect issue_slots[18].in_uop.bits.op2_sel, _WIRE.op2_sel \n connect issue_slots[18].in_uop.bits.op1_sel, _WIRE.op1_sel \n connect issue_slots[18].in_uop.bits.imm_packed, _WIRE.imm_packed \n connect issue_slots[18].in_uop.bits.pimm, _WIRE.pimm \n connect issue_slots[18].in_uop.bits.imm_sel, _WIRE.imm_sel \n connect issue_slots[18].in_uop.bits.imm_rename, _WIRE.imm_rename \n connect issue_slots[18].in_uop.bits.taken, _WIRE.taken \n connect issue_slots[18].in_uop.bits.pc_lob, _WIRE.pc_lob \n connect issue_slots[18].in_uop.bits.edge_inst, _WIRE.edge_inst \n connect issue_slots[18].in_uop.bits.ftq_idx, _WIRE.ftq_idx \n connect issue_slots[18].in_uop.bits.is_mov, _WIRE.is_mov \n connect issue_slots[18].in_uop.bits.is_rocc, _WIRE.is_rocc \n connect issue_slots[18].in_uop.bits.is_sys_pc2epc, _WIRE.is_sys_pc2epc \n connect issue_slots[18].in_uop.bits.is_eret, _WIRE.is_eret \n connect issue_slots[18].in_uop.bits.is_amo, _WIRE.is_amo \n connect issue_slots[18].in_uop.bits.is_sfence, _WIRE.is_sfence \n connect issue_slots[18].in_uop.bits.is_fencei, _WIRE.is_fencei \n connect issue_slots[18].in_uop.bits.is_fence, _WIRE.is_fence \n connect issue_slots[18].in_uop.bits.is_sfb, _WIRE.is_sfb \n connect issue_slots[18].in_uop.bits.br_type, _WIRE.br_type \n connect issue_slots[18].in_uop.bits.br_tag, _WIRE.br_tag \n connect issue_slots[18].in_uop.bits.br_mask, _WIRE.br_mask \n connect issue_slots[18].in_uop.bits.dis_col_sel, _WIRE.dis_col_sel \n connect issue_slots[18].in_uop.bits.iw_p3_bypass_hint, _WIRE.iw_p3_bypass_hint \n connect issue_slots[18].in_uop.bits.iw_p2_bypass_hint, _WIRE.iw_p2_bypass_hint \n connect issue_slots[18].in_uop.bits.iw_p1_bypass_hint, _WIRE.iw_p1_bypass_hint \n connect issue_slots[18].in_uop.bits.iw_p2_speculative_child, _WIRE.iw_p2_speculative_child \n connect issue_slots[18].in_uop.bits.iw_p1_speculative_child, _WIRE.iw_p1_speculative_child \n connect issue_slots[18].in_uop.bits.iw_issued_partial_dgen, _WIRE.iw_issued_partial_dgen \n connect issue_slots[18].in_uop.bits.iw_issued_partial_agen, _WIRE.iw_issued_partial_agen \n connect issue_slots[18].in_uop.bits.iw_issued, _WIRE.iw_issued \n connect issue_slots[18].in_uop.bits.fu_code[0], _WIRE.fu_code[0] \n connect issue_slots[18].in_uop.bits.fu_code[1], _WIRE.fu_code[1] \n connect issue_slots[18].in_uop.bits.fu_code[2], _WIRE.fu_code[2] \n connect issue_slots[18].in_uop.bits.fu_code[3], _WIRE.fu_code[3] \n connect issue_slots[18].in_uop.bits.fu_code[4], _WIRE.fu_code[4] \n connect issue_slots[18].in_uop.bits.fu_code[5], _WIRE.fu_code[5] \n connect issue_slots[18].in_uop.bits.fu_code[6], _WIRE.fu_code[6] \n connect issue_slots[18].in_uop.bits.fu_code[7], _WIRE.fu_code[7] \n connect issue_slots[18].in_uop.bits.fu_code[8], _WIRE.fu_code[8] \n connect issue_slots[18].in_uop.bits.fu_code[9], _WIRE.fu_code[9] \n connect issue_slots[18].in_uop.bits.iq_type[0], _WIRE.iq_type[0] \n connect issue_slots[18].in_uop.bits.iq_type[1], _WIRE.iq_type[1] \n connect issue_slots[18].in_uop.bits.iq_type[2], _WIRE.iq_type[2] \n connect issue_slots[18].in_uop.bits.iq_type[3], _WIRE.iq_type[3] \n connect issue_slots[18].in_uop.bits.debug_pc, _WIRE.debug_pc \n connect issue_slots[18].in_uop.bits.is_rvc, _WIRE.is_rvc \n connect issue_slots[18].in_uop.bits.debug_inst, _WIRE.debug_inst \n connect issue_slots[18].in_uop.bits.inst, _WIRE.inst \n node _issue_slots_18_clear_T = neq(shamts_oh[18], UInt<1>(0h0)) \n connect issue_slots[18].clear, _issue_slots_18_clear_T \n connect issue_slots[19].in_uop.valid, UInt<1>(0h0) \n connect issue_slots[19].in_uop.bits.debug_tsrc, _WIRE.debug_tsrc \n connect issue_slots[19].in_uop.bits.debug_fsrc, _WIRE.debug_fsrc \n connect issue_slots[19].in_uop.bits.bp_xcpt_if, _WIRE.bp_xcpt_if \n connect issue_slots[19].in_uop.bits.bp_debug_if, _WIRE.bp_debug_if \n connect issue_slots[19].in_uop.bits.xcpt_ma_if, _WIRE.xcpt_ma_if \n connect issue_slots[19].in_uop.bits.xcpt_ae_if, _WIRE.xcpt_ae_if \n connect issue_slots[19].in_uop.bits.xcpt_pf_if, _WIRE.xcpt_pf_if \n connect issue_slots[19].in_uop.bits.fp_typ, _WIRE.fp_typ \n connect issue_slots[19].in_uop.bits.fp_rm, _WIRE.fp_rm \n connect issue_slots[19].in_uop.bits.fp_val, _WIRE.fp_val \n connect issue_slots[19].in_uop.bits.fcn_op, _WIRE.fcn_op \n connect issue_slots[19].in_uop.bits.fcn_dw, _WIRE.fcn_dw \n connect issue_slots[19].in_uop.bits.frs3_en, _WIRE.frs3_en \n connect issue_slots[19].in_uop.bits.lrs2_rtype, _WIRE.lrs2_rtype \n connect issue_slots[19].in_uop.bits.lrs1_rtype, _WIRE.lrs1_rtype \n connect issue_slots[19].in_uop.bits.dst_rtype, _WIRE.dst_rtype \n connect issue_slots[19].in_uop.bits.lrs3, _WIRE.lrs3 \n connect issue_slots[19].in_uop.bits.lrs2, _WIRE.lrs2 \n connect issue_slots[19].in_uop.bits.lrs1, _WIRE.lrs1 \n connect issue_slots[19].in_uop.bits.ldst, _WIRE.ldst \n connect issue_slots[19].in_uop.bits.ldst_is_rs1, _WIRE.ldst_is_rs1 \n connect issue_slots[19].in_uop.bits.csr_cmd, _WIRE.csr_cmd \n connect issue_slots[19].in_uop.bits.flush_on_commit, _WIRE.flush_on_commit \n connect issue_slots[19].in_uop.bits.is_unique, _WIRE.is_unique \n connect issue_slots[19].in_uop.bits.uses_stq, _WIRE.uses_stq \n connect issue_slots[19].in_uop.bits.uses_ldq, _WIRE.uses_ldq \n connect issue_slots[19].in_uop.bits.mem_signed, _WIRE.mem_signed \n connect issue_slots[19].in_uop.bits.mem_size, _WIRE.mem_size \n connect issue_slots[19].in_uop.bits.mem_cmd, _WIRE.mem_cmd \n connect issue_slots[19].in_uop.bits.exc_cause, _WIRE.exc_cause \n connect issue_slots[19].in_uop.bits.exception, _WIRE.exception \n connect issue_slots[19].in_uop.bits.stale_pdst, _WIRE.stale_pdst \n connect issue_slots[19].in_uop.bits.ppred_busy, _WIRE.ppred_busy \n connect issue_slots[19].in_uop.bits.prs3_busy, _WIRE.prs3_busy \n connect issue_slots[19].in_uop.bits.prs2_busy, _WIRE.prs2_busy \n connect issue_slots[19].in_uop.bits.prs1_busy, _WIRE.prs1_busy \n connect issue_slots[19].in_uop.bits.ppred, _WIRE.ppred \n connect issue_slots[19].in_uop.bits.prs3, _WIRE.prs3 \n connect issue_slots[19].in_uop.bits.prs2, _WIRE.prs2 \n connect issue_slots[19].in_uop.bits.prs1, _WIRE.prs1 \n connect issue_slots[19].in_uop.bits.pdst, _WIRE.pdst \n connect issue_slots[19].in_uop.bits.rxq_idx, _WIRE.rxq_idx \n connect issue_slots[19].in_uop.bits.stq_idx, _WIRE.stq_idx \n connect issue_slots[19].in_uop.bits.ldq_idx, _WIRE.ldq_idx \n connect issue_slots[19].in_uop.bits.rob_idx, _WIRE.rob_idx \n connect issue_slots[19].in_uop.bits.fp_ctrl.vec, _WIRE.fp_ctrl.vec \n connect issue_slots[19].in_uop.bits.fp_ctrl.wflags, _WIRE.fp_ctrl.wflags \n connect issue_slots[19].in_uop.bits.fp_ctrl.sqrt, _WIRE.fp_ctrl.sqrt \n connect issue_slots[19].in_uop.bits.fp_ctrl.div, _WIRE.fp_ctrl.div \n connect issue_slots[19].in_uop.bits.fp_ctrl.fma, _WIRE.fp_ctrl.fma \n connect issue_slots[19].in_uop.bits.fp_ctrl.fastpipe, _WIRE.fp_ctrl.fastpipe \n connect issue_slots[19].in_uop.bits.fp_ctrl.toint, _WIRE.fp_ctrl.toint \n connect issue_slots[19].in_uop.bits.fp_ctrl.fromint, _WIRE.fp_ctrl.fromint \n connect issue_slots[19].in_uop.bits.fp_ctrl.typeTagOut, _WIRE.fp_ctrl.typeTagOut \n connect issue_slots[19].in_uop.bits.fp_ctrl.typeTagIn, _WIRE.fp_ctrl.typeTagIn \n connect issue_slots[19].in_uop.bits.fp_ctrl.swap23, _WIRE.fp_ctrl.swap23 \n connect issue_slots[19].in_uop.bits.fp_ctrl.swap12, _WIRE.fp_ctrl.swap12 \n connect issue_slots[19].in_uop.bits.fp_ctrl.ren3, _WIRE.fp_ctrl.ren3 \n connect issue_slots[19].in_uop.bits.fp_ctrl.ren2, _WIRE.fp_ctrl.ren2 \n connect issue_slots[19].in_uop.bits.fp_ctrl.ren1, _WIRE.fp_ctrl.ren1 \n connect issue_slots[19].in_uop.bits.fp_ctrl.wen, _WIRE.fp_ctrl.wen \n connect issue_slots[19].in_uop.bits.fp_ctrl.ldst, _WIRE.fp_ctrl.ldst \n connect issue_slots[19].in_uop.bits.op2_sel, _WIRE.op2_sel \n connect issue_slots[19].in_uop.bits.op1_sel, _WIRE.op1_sel \n connect issue_slots[19].in_uop.bits.imm_packed, _WIRE.imm_packed \n connect issue_slots[19].in_uop.bits.pimm, _WIRE.pimm \n connect issue_slots[19].in_uop.bits.imm_sel, _WIRE.imm_sel \n connect issue_slots[19].in_uop.bits.imm_rename, _WIRE.imm_rename \n connect issue_slots[19].in_uop.bits.taken, _WIRE.taken \n connect issue_slots[19].in_uop.bits.pc_lob, _WIRE.pc_lob \n connect issue_slots[19].in_uop.bits.edge_inst, _WIRE.edge_inst \n connect issue_slots[19].in_uop.bits.ftq_idx, _WIRE.ftq_idx \n connect issue_slots[19].in_uop.bits.is_mov, _WIRE.is_mov \n connect issue_slots[19].in_uop.bits.is_rocc, _WIRE.is_rocc \n connect issue_slots[19].in_uop.bits.is_sys_pc2epc, _WIRE.is_sys_pc2epc \n connect issue_slots[19].in_uop.bits.is_eret, _WIRE.is_eret \n connect issue_slots[19].in_uop.bits.is_amo, _WIRE.is_amo \n connect issue_slots[19].in_uop.bits.is_sfence, _WIRE.is_sfence \n connect issue_slots[19].in_uop.bits.is_fencei, _WIRE.is_fencei \n connect issue_slots[19].in_uop.bits.is_fence, _WIRE.is_fence \n connect issue_slots[19].in_uop.bits.is_sfb, _WIRE.is_sfb \n connect issue_slots[19].in_uop.bits.br_type, _WIRE.br_type \n connect issue_slots[19].in_uop.bits.br_tag, _WIRE.br_tag \n connect issue_slots[19].in_uop.bits.br_mask, _WIRE.br_mask \n connect issue_slots[19].in_uop.bits.dis_col_sel, _WIRE.dis_col_sel \n connect issue_slots[19].in_uop.bits.iw_p3_bypass_hint, _WIRE.iw_p3_bypass_hint \n connect issue_slots[19].in_uop.bits.iw_p2_bypass_hint, _WIRE.iw_p2_bypass_hint \n connect issue_slots[19].in_uop.bits.iw_p1_bypass_hint, _WIRE.iw_p1_bypass_hint \n connect issue_slots[19].in_uop.bits.iw_p2_speculative_child, _WIRE.iw_p2_speculative_child \n connect issue_slots[19].in_uop.bits.iw_p1_speculative_child, _WIRE.iw_p1_speculative_child \n connect issue_slots[19].in_uop.bits.iw_issued_partial_dgen, _WIRE.iw_issued_partial_dgen \n connect issue_slots[19].in_uop.bits.iw_issued_partial_agen, _WIRE.iw_issued_partial_agen \n connect issue_slots[19].in_uop.bits.iw_issued, _WIRE.iw_issued \n connect issue_slots[19].in_uop.bits.fu_code[0], _WIRE.fu_code[0] \n connect issue_slots[19].in_uop.bits.fu_code[1], _WIRE.fu_code[1] \n connect issue_slots[19].in_uop.bits.fu_code[2], _WIRE.fu_code[2] \n connect issue_slots[19].in_uop.bits.fu_code[3], _WIRE.fu_code[3] \n connect issue_slots[19].in_uop.bits.fu_code[4], _WIRE.fu_code[4] \n connect issue_slots[19].in_uop.bits.fu_code[5], _WIRE.fu_code[5] \n connect issue_slots[19].in_uop.bits.fu_code[6], _WIRE.fu_code[6] \n connect issue_slots[19].in_uop.bits.fu_code[7], _WIRE.fu_code[7] \n connect issue_slots[19].in_uop.bits.fu_code[8], _WIRE.fu_code[8] \n connect issue_slots[19].in_uop.bits.fu_code[9], _WIRE.fu_code[9] \n connect issue_slots[19].in_uop.bits.iq_type[0], _WIRE.iq_type[0] \n connect issue_slots[19].in_uop.bits.iq_type[1], _WIRE.iq_type[1] \n connect issue_slots[19].in_uop.bits.iq_type[2], _WIRE.iq_type[2] \n connect issue_slots[19].in_uop.bits.iq_type[3], _WIRE.iq_type[3] \n connect issue_slots[19].in_uop.bits.debug_pc, _WIRE.debug_pc \n connect issue_slots[19].in_uop.bits.is_rvc, _WIRE.is_rvc \n connect issue_slots[19].in_uop.bits.debug_inst, _WIRE.debug_inst \n connect issue_slots[19].in_uop.bits.inst, _WIRE.inst \n node _T_200 = eq(shamts_oh[20], UInt<1>(0h1)) \n when _T_200 : \n connect issue_slots[19].in_uop.valid, will_be_valid_20 \n connect issue_slots[19].in_uop.bits.debug_tsrc, _WIRE.debug_tsrc \n connect issue_slots[19].in_uop.bits.debug_fsrc, _WIRE.debug_fsrc \n connect issue_slots[19].in_uop.bits.bp_xcpt_if, _WIRE.bp_xcpt_if \n connect issue_slots[19].in_uop.bits.bp_debug_if, _WIRE.bp_debug_if \n connect issue_slots[19].in_uop.bits.xcpt_ma_if, _WIRE.xcpt_ma_if \n connect issue_slots[19].in_uop.bits.xcpt_ae_if, _WIRE.xcpt_ae_if \n connect issue_slots[19].in_uop.bits.xcpt_pf_if, _WIRE.xcpt_pf_if \n connect issue_slots[19].in_uop.bits.fp_typ, _WIRE.fp_typ \n connect issue_slots[19].in_uop.bits.fp_rm, _WIRE.fp_rm \n connect issue_slots[19].in_uop.bits.fp_val, _WIRE.fp_val \n connect issue_slots[19].in_uop.bits.fcn_op, _WIRE.fcn_op \n connect issue_slots[19].in_uop.bits.fcn_dw, _WIRE.fcn_dw \n connect issue_slots[19].in_uop.bits.frs3_en, _WIRE.frs3_en \n connect issue_slots[19].in_uop.bits.lrs2_rtype, _WIRE.lrs2_rtype \n connect issue_slots[19].in_uop.bits.lrs1_rtype, _WIRE.lrs1_rtype \n connect issue_slots[19].in_uop.bits.dst_rtype, _WIRE.dst_rtype \n connect issue_slots[19].in_uop.bits.lrs3, _WIRE.lrs3 \n connect issue_slots[19].in_uop.bits.lrs2, _WIRE.lrs2 \n connect issue_slots[19].in_uop.bits.lrs1, _WIRE.lrs1 \n connect issue_slots[19].in_uop.bits.ldst, _WIRE.ldst \n connect issue_slots[19].in_uop.bits.ldst_is_rs1, _WIRE.ldst_is_rs1 \n connect issue_slots[19].in_uop.bits.csr_cmd, _WIRE.csr_cmd \n connect issue_slots[19].in_uop.bits.flush_on_commit, _WIRE.flush_on_commit \n connect issue_slots[19].in_uop.bits.is_unique, _WIRE.is_unique \n connect issue_slots[19].in_uop.bits.uses_stq, _WIRE.uses_stq \n connect issue_slots[19].in_uop.bits.uses_ldq, _WIRE.uses_ldq \n connect issue_slots[19].in_uop.bits.mem_signed, _WIRE.mem_signed \n connect issue_slots[19].in_uop.bits.mem_size, _WIRE.mem_size \n connect issue_slots[19].in_uop.bits.mem_cmd, _WIRE.mem_cmd \n connect issue_slots[19].in_uop.bits.exc_cause, _WIRE.exc_cause \n connect issue_slots[19].in_uop.bits.exception, _WIRE.exception \n connect issue_slots[19].in_uop.bits.stale_pdst, _WIRE.stale_pdst \n connect issue_slots[19].in_uop.bits.ppred_busy, _WIRE.ppred_busy \n connect issue_slots[19].in_uop.bits.prs3_busy, _WIRE.prs3_busy \n connect issue_slots[19].in_uop.bits.prs2_busy, _WIRE.prs2_busy \n connect issue_slots[19].in_uop.bits.prs1_busy, _WIRE.prs1_busy \n connect issue_slots[19].in_uop.bits.ppred, _WIRE.ppred \n connect issue_slots[19].in_uop.bits.prs3, _WIRE.prs3 \n connect issue_slots[19].in_uop.bits.prs2, _WIRE.prs2 \n connect issue_slots[19].in_uop.bits.prs1, _WIRE.prs1 \n connect issue_slots[19].in_uop.bits.pdst, _WIRE.pdst \n connect issue_slots[19].in_uop.bits.rxq_idx, _WIRE.rxq_idx \n connect issue_slots[19].in_uop.bits.stq_idx, _WIRE.stq_idx \n connect issue_slots[19].in_uop.bits.ldq_idx, _WIRE.ldq_idx \n connect issue_slots[19].in_uop.bits.rob_idx, _WIRE.rob_idx \n connect issue_slots[19].in_uop.bits.fp_ctrl.vec, _WIRE.fp_ctrl.vec \n connect issue_slots[19].in_uop.bits.fp_ctrl.wflags, _WIRE.fp_ctrl.wflags \n connect issue_slots[19].in_uop.bits.fp_ctrl.sqrt, _WIRE.fp_ctrl.sqrt \n connect issue_slots[19].in_uop.bits.fp_ctrl.div, _WIRE.fp_ctrl.div \n connect issue_slots[19].in_uop.bits.fp_ctrl.fma, _WIRE.fp_ctrl.fma \n connect issue_slots[19].in_uop.bits.fp_ctrl.fastpipe, _WIRE.fp_ctrl.fastpipe \n connect issue_slots[19].in_uop.bits.fp_ctrl.toint, _WIRE.fp_ctrl.toint \n connect issue_slots[19].in_uop.bits.fp_ctrl.fromint, _WIRE.fp_ctrl.fromint \n connect issue_slots[19].in_uop.bits.fp_ctrl.typeTagOut, _WIRE.fp_ctrl.typeTagOut \n connect issue_slots[19].in_uop.bits.fp_ctrl.typeTagIn, _WIRE.fp_ctrl.typeTagIn \n connect issue_slots[19].in_uop.bits.fp_ctrl.swap23, _WIRE.fp_ctrl.swap23 \n connect issue_slots[19].in_uop.bits.fp_ctrl.swap12, _WIRE.fp_ctrl.swap12 \n connect issue_slots[19].in_uop.bits.fp_ctrl.ren3, _WIRE.fp_ctrl.ren3 \n connect issue_slots[19].in_uop.bits.fp_ctrl.ren2, _WIRE.fp_ctrl.ren2 \n connect issue_slots[19].in_uop.bits.fp_ctrl.ren1, _WIRE.fp_ctrl.ren1 \n connect issue_slots[19].in_uop.bits.fp_ctrl.wen, _WIRE.fp_ctrl.wen \n connect issue_slots[19].in_uop.bits.fp_ctrl.ldst, _WIRE.fp_ctrl.ldst \n connect issue_slots[19].in_uop.bits.op2_sel, _WIRE.op2_sel \n connect issue_slots[19].in_uop.bits.op1_sel, _WIRE.op1_sel \n connect issue_slots[19].in_uop.bits.imm_packed, _WIRE.imm_packed \n connect issue_slots[19].in_uop.bits.pimm, _WIRE.pimm \n connect issue_slots[19].in_uop.bits.imm_sel, _WIRE.imm_sel \n connect issue_slots[19].in_uop.bits.imm_rename, _WIRE.imm_rename \n connect issue_slots[19].in_uop.bits.taken, _WIRE.taken \n connect issue_slots[19].in_uop.bits.pc_lob, _WIRE.pc_lob \n connect issue_slots[19].in_uop.bits.edge_inst, _WIRE.edge_inst \n connect issue_slots[19].in_uop.bits.ftq_idx, _WIRE.ftq_idx \n connect issue_slots[19].in_uop.bits.is_mov, _WIRE.is_mov \n connect issue_slots[19].in_uop.bits.is_rocc, _WIRE.is_rocc \n connect issue_slots[19].in_uop.bits.is_sys_pc2epc, _WIRE.is_sys_pc2epc \n connect issue_slots[19].in_uop.bits.is_eret, _WIRE.is_eret \n connect issue_slots[19].in_uop.bits.is_amo, _WIRE.is_amo \n connect issue_slots[19].in_uop.bits.is_sfence, _WIRE.is_sfence \n connect issue_slots[19].in_uop.bits.is_fencei, _WIRE.is_fencei \n connect issue_slots[19].in_uop.bits.is_fence, _WIRE.is_fence \n connect issue_slots[19].in_uop.bits.is_sfb, _WIRE.is_sfb \n connect issue_slots[19].in_uop.bits.br_type, _WIRE.br_type \n connect issue_slots[19].in_uop.bits.br_tag, _WIRE.br_tag \n connect issue_slots[19].in_uop.bits.br_mask, _WIRE.br_mask \n connect issue_slots[19].in_uop.bits.dis_col_sel, _WIRE.dis_col_sel \n connect issue_slots[19].in_uop.bits.iw_p3_bypass_hint, _WIRE.iw_p3_bypass_hint \n connect issue_slots[19].in_uop.bits.iw_p2_bypass_hint, _WIRE.iw_p2_bypass_hint \n connect issue_slots[19].in_uop.bits.iw_p1_bypass_hint, _WIRE.iw_p1_bypass_hint \n connect issue_slots[19].in_uop.bits.iw_p2_speculative_child, _WIRE.iw_p2_speculative_child \n connect issue_slots[19].in_uop.bits.iw_p1_speculative_child, _WIRE.iw_p1_speculative_child \n connect issue_slots[19].in_uop.bits.iw_issued_partial_dgen, _WIRE.iw_issued_partial_dgen \n connect issue_slots[19].in_uop.bits.iw_issued_partial_agen, _WIRE.iw_issued_partial_agen \n connect issue_slots[19].in_uop.bits.iw_issued, _WIRE.iw_issued \n connect issue_slots[19].in_uop.bits.fu_code[0], _WIRE.fu_code[0] \n connect issue_slots[19].in_uop.bits.fu_code[1], _WIRE.fu_code[1] \n connect issue_slots[19].in_uop.bits.fu_code[2], _WIRE.fu_code[2] \n connect issue_slots[19].in_uop.bits.fu_code[3], _WIRE.fu_code[3] \n connect issue_slots[19].in_uop.bits.fu_code[4], _WIRE.fu_code[4] \n connect issue_slots[19].in_uop.bits.fu_code[5], _WIRE.fu_code[5] \n connect issue_slots[19].in_uop.bits.fu_code[6], _WIRE.fu_code[6] \n connect issue_slots[19].in_uop.bits.fu_code[7], _WIRE.fu_code[7] \n connect issue_slots[19].in_uop.bits.fu_code[8], _WIRE.fu_code[8] \n connect issue_slots[19].in_uop.bits.fu_code[9], _WIRE.fu_code[9] \n connect issue_slots[19].in_uop.bits.iq_type[0], _WIRE.iq_type[0] \n connect issue_slots[19].in_uop.bits.iq_type[1], _WIRE.iq_type[1] \n connect issue_slots[19].in_uop.bits.iq_type[2], _WIRE.iq_type[2] \n connect issue_slots[19].in_uop.bits.iq_type[3], _WIRE.iq_type[3] \n connect issue_slots[19].in_uop.bits.debug_pc, _WIRE.debug_pc \n connect issue_slots[19].in_uop.bits.is_rvc, _WIRE.is_rvc \n connect issue_slots[19].in_uop.bits.debug_inst, _WIRE.debug_inst \n connect issue_slots[19].in_uop.bits.inst, _WIRE.inst \n node _T_201 = eq(shamts_oh[21], UInt<2>(0h2)) \n when _T_201 : \n connect issue_slots[19].in_uop.valid, will_be_valid_21 \n connect issue_slots[19].in_uop.bits.debug_tsrc, _WIRE_1.debug_tsrc \n connect issue_slots[19].in_uop.bits.debug_fsrc, _WIRE_1.debug_fsrc \n connect issue_slots[19].in_uop.bits.bp_xcpt_if, _WIRE_1.bp_xcpt_if \n connect issue_slots[19].in_uop.bits.bp_debug_if, _WIRE_1.bp_debug_if \n connect issue_slots[19].in_uop.bits.xcpt_ma_if, _WIRE_1.xcpt_ma_if \n connect issue_slots[19].in_uop.bits.xcpt_ae_if, _WIRE_1.xcpt_ae_if \n connect issue_slots[19].in_uop.bits.xcpt_pf_if, _WIRE_1.xcpt_pf_if \n connect issue_slots[19].in_uop.bits.fp_typ, _WIRE_1.fp_typ \n connect issue_slots[19].in_uop.bits.fp_rm, _WIRE_1.fp_rm \n connect issue_slots[19].in_uop.bits.fp_val, _WIRE_1.fp_val \n connect issue_slots[19].in_uop.bits.fcn_op, _WIRE_1.fcn_op \n connect issue_slots[19].in_uop.bits.fcn_dw, _WIRE_1.fcn_dw \n connect issue_slots[19].in_uop.bits.frs3_en, _WIRE_1.frs3_en \n connect issue_slots[19].in_uop.bits.lrs2_rtype, _WIRE_1.lrs2_rtype \n connect issue_slots[19].in_uop.bits.lrs1_rtype, _WIRE_1.lrs1_rtype \n connect issue_slots[19].in_uop.bits.dst_rtype, _WIRE_1.dst_rtype \n connect issue_slots[19].in_uop.bits.lrs3, _WIRE_1.lrs3 \n connect issue_slots[19].in_uop.bits.lrs2, _WIRE_1.lrs2 \n connect issue_slots[19].in_uop.bits.lrs1, _WIRE_1.lrs1 \n connect issue_slots[19].in_uop.bits.ldst, _WIRE_1.ldst \n connect issue_slots[19].in_uop.bits.ldst_is_rs1, _WIRE_1.ldst_is_rs1 \n connect issue_slots[19].in_uop.bits.csr_cmd, _WIRE_1.csr_cmd \n connect issue_slots[19].in_uop.bits.flush_on_commit, _WIRE_1.flush_on_commit \n connect issue_slots[19].in_uop.bits.is_unique, _WIRE_1.is_unique \n connect issue_slots[19].in_uop.bits.uses_stq, _WIRE_1.uses_stq \n connect issue_slots[19].in_uop.bits.uses_ldq, _WIRE_1.uses_ldq \n connect issue_slots[19].in_uop.bits.mem_signed, _WIRE_1.mem_signed \n connect issue_slots[19].in_uop.bits.mem_size, _WIRE_1.mem_size \n connect issue_slots[19].in_uop.bits.mem_cmd, _WIRE_1.mem_cmd \n connect issue_slots[19].in_uop.bits.exc_cause, _WIRE_1.exc_cause \n connect issue_slots[19].in_uop.bits.exception, _WIRE_1.exception \n connect issue_slots[19].in_uop.bits.stale_pdst, _WIRE_1.stale_pdst \n connect issue_slots[19].in_uop.bits.ppred_busy, _WIRE_1.ppred_busy \n connect issue_slots[19].in_uop.bits.prs3_busy, _WIRE_1.prs3_busy \n connect issue_slots[19].in_uop.bits.prs2_busy, _WIRE_1.prs2_busy \n connect issue_slots[19].in_uop.bits.prs1_busy, _WIRE_1.prs1_busy \n connect issue_slots[19].in_uop.bits.ppred, _WIRE_1.ppred \n connect issue_slots[19].in_uop.bits.prs3, _WIRE_1.prs3 \n connect issue_slots[19].in_uop.bits.prs2, _WIRE_1.prs2 \n connect issue_slots[19].in_uop.bits.prs1, _WIRE_1.prs1 \n connect issue_slots[19].in_uop.bits.pdst, _WIRE_1.pdst \n connect issue_slots[19].in_uop.bits.rxq_idx, _WIRE_1.rxq_idx \n connect issue_slots[19].in_uop.bits.stq_idx, _WIRE_1.stq_idx \n connect issue_slots[19].in_uop.bits.ldq_idx, _WIRE_1.ldq_idx \n connect issue_slots[19].in_uop.bits.rob_idx, _WIRE_1.rob_idx \n connect issue_slots[19].in_uop.bits.fp_ctrl.vec, _WIRE_1.fp_ctrl.vec \n connect issue_slots[19].in_uop.bits.fp_ctrl.wflags, _WIRE_1.fp_ctrl.wflags \n connect issue_slots[19].in_uop.bits.fp_ctrl.sqrt, _WIRE_1.fp_ctrl.sqrt \n connect issue_slots[19].in_uop.bits.fp_ctrl.div, _WIRE_1.fp_ctrl.div \n connect issue_slots[19].in_uop.bits.fp_ctrl.fma, _WIRE_1.fp_ctrl.fma \n connect issue_slots[19].in_uop.bits.fp_ctrl.fastpipe, _WIRE_1.fp_ctrl.fastpipe \n connect issue_slots[19].in_uop.bits.fp_ctrl.toint, _WIRE_1.fp_ctrl.toint \n connect issue_slots[19].in_uop.bits.fp_ctrl.fromint, _WIRE_1.fp_ctrl.fromint \n connect issue_slots[19].in_uop.bits.fp_ctrl.typeTagOut, _WIRE_1.fp_ctrl.typeTagOut \n connect issue_slots[19].in_uop.bits.fp_ctrl.typeTagIn, _WIRE_1.fp_ctrl.typeTagIn \n connect issue_slots[19].in_uop.bits.fp_ctrl.swap23, _WIRE_1.fp_ctrl.swap23 \n connect issue_slots[19].in_uop.bits.fp_ctrl.swap12, _WIRE_1.fp_ctrl.swap12 \n connect issue_slots[19].in_uop.bits.fp_ctrl.ren3, _WIRE_1.fp_ctrl.ren3 \n connect issue_slots[19].in_uop.bits.fp_ctrl.ren2, _WIRE_1.fp_ctrl.ren2 \n connect issue_slots[19].in_uop.bits.fp_ctrl.ren1, _WIRE_1.fp_ctrl.ren1 \n connect issue_slots[19].in_uop.bits.fp_ctrl.wen, _WIRE_1.fp_ctrl.wen \n connect issue_slots[19].in_uop.bits.fp_ctrl.ldst, _WIRE_1.fp_ctrl.ldst \n connect issue_slots[19].in_uop.bits.op2_sel, _WIRE_1.op2_sel \n connect issue_slots[19].in_uop.bits.op1_sel, _WIRE_1.op1_sel \n connect issue_slots[19].in_uop.bits.imm_packed, _WIRE_1.imm_packed \n connect issue_slots[19].in_uop.bits.pimm, _WIRE_1.pimm \n connect issue_slots[19].in_uop.bits.imm_sel, _WIRE_1.imm_sel \n connect issue_slots[19].in_uop.bits.imm_rename, _WIRE_1.imm_rename \n connect issue_slots[19].in_uop.bits.taken, _WIRE_1.taken \n connect issue_slots[19].in_uop.bits.pc_lob, _WIRE_1.pc_lob \n connect issue_slots[19].in_uop.bits.edge_inst, _WIRE_1.edge_inst \n connect issue_slots[19].in_uop.bits.ftq_idx, _WIRE_1.ftq_idx \n connect issue_slots[19].in_uop.bits.is_mov, _WIRE_1.is_mov \n connect issue_slots[19].in_uop.bits.is_rocc, _WIRE_1.is_rocc \n connect issue_slots[19].in_uop.bits.is_sys_pc2epc, _WIRE_1.is_sys_pc2epc \n connect issue_slots[19].in_uop.bits.is_eret, _WIRE_1.is_eret \n connect issue_slots[19].in_uop.bits.is_amo, _WIRE_1.is_amo \n connect issue_slots[19].in_uop.bits.is_sfence, _WIRE_1.is_sfence \n connect issue_slots[19].in_uop.bits.is_fencei, _WIRE_1.is_fencei \n connect issue_slots[19].in_uop.bits.is_fence, _WIRE_1.is_fence \n connect issue_slots[19].in_uop.bits.is_sfb, _WIRE_1.is_sfb \n connect issue_slots[19].in_uop.bits.br_type, _WIRE_1.br_type \n connect issue_slots[19].in_uop.bits.br_tag, _WIRE_1.br_tag \n connect issue_slots[19].in_uop.bits.br_mask, _WIRE_1.br_mask \n connect issue_slots[19].in_uop.bits.dis_col_sel, _WIRE_1.dis_col_sel \n connect issue_slots[19].in_uop.bits.iw_p3_bypass_hint, _WIRE_1.iw_p3_bypass_hint \n connect issue_slots[19].in_uop.bits.iw_p2_bypass_hint, _WIRE_1.iw_p2_bypass_hint \n connect issue_slots[19].in_uop.bits.iw_p1_bypass_hint, _WIRE_1.iw_p1_bypass_hint \n connect issue_slots[19].in_uop.bits.iw_p2_speculative_child, _WIRE_1.iw_p2_speculative_child \n connect issue_slots[19].in_uop.bits.iw_p1_speculative_child, _WIRE_1.iw_p1_speculative_child \n connect issue_slots[19].in_uop.bits.iw_issued_partial_dgen, _WIRE_1.iw_issued_partial_dgen \n connect issue_slots[19].in_uop.bits.iw_issued_partial_agen, _WIRE_1.iw_issued_partial_agen \n connect issue_slots[19].in_uop.bits.iw_issued, _WIRE_1.iw_issued \n connect issue_slots[19].in_uop.bits.fu_code[0], _WIRE_1.fu_code[0] \n connect issue_slots[19].in_uop.bits.fu_code[1], _WIRE_1.fu_code[1] \n connect issue_slots[19].in_uop.bits.fu_code[2], _WIRE_1.fu_code[2] \n connect issue_slots[19].in_uop.bits.fu_code[3], _WIRE_1.fu_code[3] \n connect issue_slots[19].in_uop.bits.fu_code[4], _WIRE_1.fu_code[4] \n connect issue_slots[19].in_uop.bits.fu_code[5], _WIRE_1.fu_code[5] \n connect issue_slots[19].in_uop.bits.fu_code[6], _WIRE_1.fu_code[6] \n connect issue_slots[19].in_uop.bits.fu_code[7], _WIRE_1.fu_code[7] \n connect issue_slots[19].in_uop.bits.fu_code[8], _WIRE_1.fu_code[8] \n connect issue_slots[19].in_uop.bits.fu_code[9], _WIRE_1.fu_code[9] \n connect issue_slots[19].in_uop.bits.iq_type[0], _WIRE_1.iq_type[0] \n connect issue_slots[19].in_uop.bits.iq_type[1], _WIRE_1.iq_type[1] \n connect issue_slots[19].in_uop.bits.iq_type[2], _WIRE_1.iq_type[2] \n connect issue_slots[19].in_uop.bits.iq_type[3], _WIRE_1.iq_type[3] \n connect issue_slots[19].in_uop.bits.debug_pc, _WIRE_1.debug_pc \n connect issue_slots[19].in_uop.bits.is_rvc, _WIRE_1.is_rvc \n connect issue_slots[19].in_uop.bits.debug_inst, _WIRE_1.debug_inst \n connect issue_slots[19].in_uop.bits.inst, _WIRE_1.inst \n node _issue_slots_19_clear_T = neq(shamts_oh[19], UInt<1>(0h0)) \n connect issue_slots[19].clear, _issue_slots_19_clear_T \n reg is_available : UInt<1>[20], clock \n node _T_202 = eq(issue_slots[0].will_be_valid, UInt<1>(0h0)) \n node _T_203 = or(_T_202, issue_slots[0].clear) \n node _T_204 = eq(issue_slots[0].in_uop.valid, UInt<1>(0h0)) \n node _T_205 = and(_T_203, _T_204) \n node _T_206 = eq(issue_slots[1].will_be_valid, UInt<1>(0h0)) \n node _T_207 = or(_T_206, issue_slots[1].clear) \n node _T_208 = eq(issue_slots[1].in_uop.valid, UInt<1>(0h0)) \n node _T_209 = and(_T_207, _T_208) \n node _T_210 = eq(issue_slots[2].will_be_valid, UInt<1>(0h0)) \n node _T_211 = or(_T_210, issue_slots[2].clear) \n node _T_212 = eq(issue_slots[2].in_uop.valid, UInt<1>(0h0)) \n node _T_213 = and(_T_211, _T_212) \n node _T_214 = eq(issue_slots[3].will_be_valid, UInt<1>(0h0)) \n node _T_215 = or(_T_214, issue_slots[3].clear) \n node _T_216 = eq(issue_slots[3].in_uop.valid, UInt<1>(0h0)) \n node _T_217 = and(_T_215, _T_216) \n node _T_218 = eq(issue_slots[4].will_be_valid, UInt<1>(0h0)) \n node _T_219 = or(_T_218, issue_slots[4].clear) \n node _T_220 = eq(issue_slots[4].in_uop.valid, UInt<1>(0h0)) \n node _T_221 = and(_T_219, _T_220) \n node _T_222 = eq(issue_slots[5].will_be_valid, UInt<1>(0h0)) \n node _T_223 = or(_T_222, issue_slots[5].clear) \n node _T_224 = eq(issue_slots[5].in_uop.valid, UInt<1>(0h0)) \n node _T_225 = and(_T_223, _T_224) \n node _T_226 = eq(issue_slots[6].will_be_valid, UInt<1>(0h0)) \n node _T_227 = or(_T_226, issue_slots[6].clear) \n node _T_228 = eq(issue_slots[6].in_uop.valid, UInt<1>(0h0)) \n node _T_229 = and(_T_227, _T_228) \n node _T_230 = eq(issue_slots[7].will_be_valid, UInt<1>(0h0)) \n node _T_231 = or(_T_230, issue_slots[7].clear) \n node _T_232 = eq(issue_slots[7].in_uop.valid, UInt<1>(0h0)) \n node _T_233 = and(_T_231, _T_232) \n node _T_234 = eq(issue_slots[8].will_be_valid, UInt<1>(0h0)) \n node _T_235 = or(_T_234, issue_slots[8].clear) \n node _T_236 = eq(issue_slots[8].in_uop.valid, UInt<1>(0h0)) \n node _T_237 = and(_T_235, _T_236) \n node _T_238 = eq(issue_slots[9].will_be_valid, UInt<1>(0h0)) \n node _T_239 = or(_T_238, issue_slots[9].clear) \n node _T_240 = eq(issue_slots[9].in_uop.valid, UInt<1>(0h0)) \n node _T_241 = and(_T_239, _T_240) \n node _T_242 = eq(issue_slots[10].will_be_valid, UInt<1>(0h0)) \n node _T_243 = or(_T_242, issue_slots[10].clear) \n node _T_244 = eq(issue_slots[10].in_uop.valid, UInt<1>(0h0)) \n node _T_245 = and(_T_243, _T_244) \n node _T_246 = eq(issue_slots[11].will_be_valid, UInt<1>(0h0)) \n node _T_247 = or(_T_246, issue_slots[11].clear) \n node _T_248 = eq(issue_slots[11].in_uop.valid, UInt<1>(0h0)) \n node _T_249 = and(_T_247, _T_248) \n node _T_250 = eq(issue_slots[12].will_be_valid, UInt<1>(0h0)) \n node _T_251 = or(_T_250, issue_slots[12].clear) \n node _T_252 = eq(issue_slots[12].in_uop.valid, UInt<1>(0h0)) \n node _T_253 = and(_T_251, _T_252) \n node _T_254 = eq(issue_slots[13].will_be_valid, UInt<1>(0h0)) \n node _T_255 = or(_T_254, issue_slots[13].clear) \n node _T_256 = eq(issue_slots[13].in_uop.valid, UInt<1>(0h0)) \n node _T_257 = and(_T_255, _T_256) \n node _T_258 = eq(issue_slots[14].will_be_valid, UInt<1>(0h0)) \n node _T_259 = or(_T_258, issue_slots[14].clear) \n node _T_260 = eq(issue_slots[14].in_uop.valid, UInt<1>(0h0)) \n node _T_261 = and(_T_259, _T_260) \n node _T_262 = eq(issue_slots[15].will_be_valid, UInt<1>(0h0)) \n node _T_263 = or(_T_262, issue_slots[15].clear) \n node _T_264 = eq(issue_slots[15].in_uop.valid, UInt<1>(0h0)) \n node _T_265 = and(_T_263, _T_264) \n node _T_266 = eq(issue_slots[16].will_be_valid, UInt<1>(0h0)) \n node _T_267 = or(_T_266, issue_slots[16].clear) \n node _T_268 = eq(issue_slots[16].in_uop.valid, UInt<1>(0h0)) \n node _T_269 = and(_T_267, _T_268) \n node _T_270 = eq(issue_slots[17].will_be_valid, UInt<1>(0h0)) \n node _T_271 = or(_T_270, issue_slots[17].clear) \n node _T_272 = eq(issue_slots[17].in_uop.valid, UInt<1>(0h0)) \n node _T_273 = and(_T_271, _T_272) \n node _T_274 = eq(issue_slots[18].will_be_valid, UInt<1>(0h0)) \n node _T_275 = or(_T_274, issue_slots[18].clear) \n node _T_276 = eq(issue_slots[18].in_uop.valid, UInt<1>(0h0)) \n node _T_277 = and(_T_275, _T_276) \n node _T_278 = eq(issue_slots[19].will_be_valid, UInt<1>(0h0)) \n node _T_279 = or(_T_278, issue_slots[19].clear) \n node _T_280 = eq(issue_slots[19].in_uop.valid, UInt<1>(0h0)) \n node _T_281 = and(_T_279, _T_280) \n wire _WIRE_12 : UInt<1>[20] \n connect _WIRE_12[0], _T_205 \n connect _WIRE_12[1], _T_209 \n connect _WIRE_12[2], _T_213 \n connect _WIRE_12[3], _T_217 \n connect _WIRE_12[4], _T_221 \n connect _WIRE_12[5], _T_225 \n connect _WIRE_12[6], _T_229 \n connect _WIRE_12[7], _T_233 \n connect _WIRE_12[8], _T_237 \n connect _WIRE_12[9], _T_241 \n connect _WIRE_12[10], _T_245 \n connect _WIRE_12[11], _T_249 \n connect _WIRE_12[12], _T_253 \n connect _WIRE_12[13], _T_257 \n connect _WIRE_12[14], _T_261 \n connect _WIRE_12[15], _T_265 \n connect _WIRE_12[16], _T_269 \n connect _WIRE_12[17], _T_273 \n connect _WIRE_12[18], _T_277 \n connect _WIRE_12[19], _T_281 \n connect is_available, _WIRE_12 \n node _io_dis_uops_0_ready_T = add(is_available[0], is_available[1]) \n node _io_dis_uops_0_ready_T_1 = bits(_io_dis_uops_0_ready_T, 1, 0) \n node _io_dis_uops_0_ready_T_2 = add(is_available[3], is_available[4]) \n node _io_dis_uops_0_ready_T_3 = bits(_io_dis_uops_0_ready_T_2, 1, 0) \n node _io_dis_uops_0_ready_T_4 = add(is_available[2], _io_dis_uops_0_ready_T_3) \n node _io_dis_uops_0_ready_T_5 = bits(_io_dis_uops_0_ready_T_4, 1, 0) \n node _io_dis_uops_0_ready_T_6 = add(_io_dis_uops_0_ready_T_1, _io_dis_uops_0_ready_T_5) \n node _io_dis_uops_0_ready_T_7 = bits(_io_dis_uops_0_ready_T_6, 2, 0) \n node _io_dis_uops_0_ready_T_8 = add(is_available[5], is_available[6]) \n node _io_dis_uops_0_ready_T_9 = bits(_io_dis_uops_0_ready_T_8, 1, 0) \n node _io_dis_uops_0_ready_T_10 = add(is_available[8], is_available[9]) \n node _io_dis_uops_0_ready_T_11 = bits(_io_dis_uops_0_ready_T_10, 1, 0) \n node _io_dis_uops_0_ready_T_12 = add(is_available[7], _io_dis_uops_0_ready_T_11) \n node _io_dis_uops_0_ready_T_13 = bits(_io_dis_uops_0_ready_T_12, 1, 0) \n node _io_dis_uops_0_ready_T_14 = add(_io_dis_uops_0_ready_T_9, _io_dis_uops_0_ready_T_13) \n node _io_dis_uops_0_ready_T_15 = bits(_io_dis_uops_0_ready_T_14, 2, 0) \n node _io_dis_uops_0_ready_T_16 = add(_io_dis_uops_0_ready_T_7, _io_dis_uops_0_ready_T_15) \n node _io_dis_uops_0_ready_T_17 = bits(_io_dis_uops_0_ready_T_16, 3, 0) \n node _io_dis_uops_0_ready_T_18 = add(is_available[10], is_available[11]) \n node _io_dis_uops_0_ready_T_19 = bits(_io_dis_uops_0_ready_T_18, 1, 0) \n node _io_dis_uops_0_ready_T_20 = add(is_available[13], is_available[14]) \n node _io_dis_uops_0_ready_T_21 = bits(_io_dis_uops_0_ready_T_20, 1, 0) \n node _io_dis_uops_0_ready_T_22 = add(is_available[12], _io_dis_uops_0_ready_T_21) \n node _io_dis_uops_0_ready_T_23 = bits(_io_dis_uops_0_ready_T_22, 1, 0) \n node _io_dis_uops_0_ready_T_24 = add(_io_dis_uops_0_ready_T_19, _io_dis_uops_0_ready_T_23) \n node _io_dis_uops_0_ready_T_25 = bits(_io_dis_uops_0_ready_T_24, 2, 0) \n node _io_dis_uops_0_ready_T_26 = add(is_available[15], is_available[16]) \n node _io_dis_uops_0_ready_T_27 = bits(_io_dis_uops_0_ready_T_26, 1, 0) \n node _io_dis_uops_0_ready_T_28 = add(is_available[18], is_available[19]) \n node _io_dis_uops_0_ready_T_29 = bits(_io_dis_uops_0_ready_T_28, 1, 0) \n node _io_dis_uops_0_ready_T_30 = add(is_available[17], _io_dis_uops_0_ready_T_29) \n node _io_dis_uops_0_ready_T_31 = bits(_io_dis_uops_0_ready_T_30, 1, 0) \n node _io_dis_uops_0_ready_T_32 = add(_io_dis_uops_0_ready_T_27, _io_dis_uops_0_ready_T_31) \n node _io_dis_uops_0_ready_T_33 = bits(_io_dis_uops_0_ready_T_32, 2, 0) \n node _io_dis_uops_0_ready_T_34 = add(_io_dis_uops_0_ready_T_25, _io_dis_uops_0_ready_T_33) \n node _io_dis_uops_0_ready_T_35 = bits(_io_dis_uops_0_ready_T_34, 3, 0) \n node _io_dis_uops_0_ready_T_36 = add(_io_dis_uops_0_ready_T_17, _io_dis_uops_0_ready_T_35) \n node _io_dis_uops_0_ready_T_37 = bits(_io_dis_uops_0_ready_T_36, 4, 0) \n node _io_dis_uops_0_ready_T_38 = and(io.dis_uops[0].ready, io.dis_uops[0].valid) \n node _io_dis_uops_0_ready_T_39 = and(io.dis_uops[1].ready, io.dis_uops[1].valid) \n node _io_dis_uops_0_ready_T_40 = add(_io_dis_uops_0_ready_T_38, _io_dis_uops_0_ready_T_39) \n node _io_dis_uops_0_ready_T_41 = bits(_io_dis_uops_0_ready_T_40, 1, 0) \n node _io_dis_uops_0_ready_T_42 = add(UInt<5>(0h0), _io_dis_uops_0_ready_T_41) \n node _io_dis_uops_0_ready_T_43 = tail(_io_dis_uops_0_ready_T_42, 1) \n node _io_dis_uops_0_ready_T_44 = gt(_io_dis_uops_0_ready_T_37, _io_dis_uops_0_ready_T_43) \n reg io_dis_uops_0_ready_REG : UInt<1>, clock \n connect io_dis_uops_0_ready_REG, _io_dis_uops_0_ready_T_44 \n connect io.dis_uops[0].ready, io_dis_uops_0_ready_REG \n node _T_282 = eq(io.dis_uops[0].ready, UInt<1>(0h0)) \n node _T_283 = shr(shamts_oh[20], 0) \n node _T_284 = neq(_T_283, UInt<1>(0h0)) \n node _T_285 = or(_T_282, _T_284) \n node _T_286 = asUInt(reset) \n node _T_287 = eq(_T_286, UInt<1>(0h0)) \n when _T_287 : \n node _T_288 = eq(_T_285, UInt<1>(0h0)) \n when _T_288 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at issue-unit-age-ordered.scala:214 assert (!io.dis_uops(w).ready || (shamts_oh(w+numIssueSlots) >> w) =/= 0.U)\\n\") : printf_1 \n assert(clock, _T_285, UInt<1>(0h1), \"\") : assert_1 \n node _io_dis_uops_1_ready_T = add(is_available[0], is_available[1]) \n node _io_dis_uops_1_ready_T_1 = bits(_io_dis_uops_1_ready_T, 1, 0) \n node _io_dis_uops_1_ready_T_2 = add(is_available[3], is_available[4]) \n node _io_dis_uops_1_ready_T_3 = bits(_io_dis_uops_1_ready_T_2, 1, 0) \n node _io_dis_uops_1_ready_T_4 = add(is_available[2], _io_dis_uops_1_ready_T_3) \n node _io_dis_uops_1_ready_T_5 = bits(_io_dis_uops_1_ready_T_4, 1, 0) \n node _io_dis_uops_1_ready_T_6 = add(_io_dis_uops_1_ready_T_1, _io_dis_uops_1_ready_T_5) \n node _io_dis_uops_1_ready_T_7 = bits(_io_dis_uops_1_ready_T_6, 2, 0) \n node _io_dis_uops_1_ready_T_8 = add(is_available[5], is_available[6]) \n node _io_dis_uops_1_ready_T_9 = bits(_io_dis_uops_1_ready_T_8, 1, 0) \n node _io_dis_uops_1_ready_T_10 = add(is_available[8], is_available[9]) \n node _io_dis_uops_1_ready_T_11 = bits(_io_dis_uops_1_ready_T_10, 1, 0) \n node _io_dis_uops_1_ready_T_12 = add(is_available[7], _io_dis_uops_1_ready_T_11) \n node _io_dis_uops_1_ready_T_13 = bits(_io_dis_uops_1_ready_T_12, 1, 0) \n node _io_dis_uops_1_ready_T_14 = add(_io_dis_uops_1_ready_T_9, _io_dis_uops_1_ready_T_13) \n node _io_dis_uops_1_ready_T_15 = bits(_io_dis_uops_1_ready_T_14, 2, 0) \n node _io_dis_uops_1_ready_T_16 = add(_io_dis_uops_1_ready_T_7, _io_dis_uops_1_ready_T_15) \n node _io_dis_uops_1_ready_T_17 = bits(_io_dis_uops_1_ready_T_16, 3, 0) \n node _io_dis_uops_1_ready_T_18 = add(is_available[10], is_available[11]) \n node _io_dis_uops_1_ready_T_19 = bits(_io_dis_uops_1_ready_T_18, 1, 0) \n node _io_dis_uops_1_ready_T_20 = add(is_available[13], is_available[14]) \n node _io_dis_uops_1_ready_T_21 = bits(_io_dis_uops_1_ready_T_20, 1, 0) \n node _io_dis_uops_1_ready_T_22 = add(is_available[12], _io_dis_uops_1_ready_T_21) \n node _io_dis_uops_1_ready_T_23 = bits(_io_dis_uops_1_ready_T_22, 1, 0) \n node _io_dis_uops_1_ready_T_24 = add(_io_dis_uops_1_ready_T_19, _io_dis_uops_1_ready_T_23) \n node _io_dis_uops_1_ready_T_25 = bits(_io_dis_uops_1_ready_T_24, 2, 0) \n node _io_dis_uops_1_ready_T_26 = add(is_available[15], is_available[16]) \n node _io_dis_uops_1_ready_T_27 = bits(_io_dis_uops_1_ready_T_26, 1, 0) \n node _io_dis_uops_1_ready_T_28 = add(is_available[18], is_available[19]) \n node _io_dis_uops_1_ready_T_29 = bits(_io_dis_uops_1_ready_T_28, 1, 0) \n node _io_dis_uops_1_ready_T_30 = add(is_available[17], _io_dis_uops_1_ready_T_29) \n node _io_dis_uops_1_ready_T_31 = bits(_io_dis_uops_1_ready_T_30, 1, 0) \n node _io_dis_uops_1_ready_T_32 = add(_io_dis_uops_1_ready_T_27, _io_dis_uops_1_ready_T_31) \n node _io_dis_uops_1_ready_T_33 = bits(_io_dis_uops_1_ready_T_32, 2, 0) \n node _io_dis_uops_1_ready_T_34 = add(_io_dis_uops_1_ready_T_25, _io_dis_uops_1_ready_T_33) \n node _io_dis_uops_1_ready_T_35 = bits(_io_dis_uops_1_ready_T_34, 3, 0) \n node _io_dis_uops_1_ready_T_36 = add(_io_dis_uops_1_ready_T_17, _io_dis_uops_1_ready_T_35) \n node _io_dis_uops_1_ready_T_37 = bits(_io_dis_uops_1_ready_T_36, 4, 0) \n node _io_dis_uops_1_ready_T_38 = and(io.dis_uops[0].ready, io.dis_uops[0].valid) \n node _io_dis_uops_1_ready_T_39 = and(io.dis_uops[1].ready, io.dis_uops[1].valid) \n node _io_dis_uops_1_ready_T_40 = add(_io_dis_uops_1_ready_T_38, _io_dis_uops_1_ready_T_39) \n node _io_dis_uops_1_ready_T_41 = bits(_io_dis_uops_1_ready_T_40, 1, 0) \n node _io_dis_uops_1_ready_T_42 = add(UInt<5>(0h1), _io_dis_uops_1_ready_T_41) \n node _io_dis_uops_1_ready_T_43 = tail(_io_dis_uops_1_ready_T_42, 1) \n node _io_dis_uops_1_ready_T_44 = gt(_io_dis_uops_1_ready_T_37, _io_dis_uops_1_ready_T_43) \n reg io_dis_uops_1_ready_REG : UInt<1>, clock \n connect io_dis_uops_1_ready_REG, _io_dis_uops_1_ready_T_44 \n connect io.dis_uops[1].ready, io_dis_uops_1_ready_REG \n node _T_289 = eq(io.dis_uops[1].ready, UInt<1>(0h0)) \n node _T_290 = shr(shamts_oh[21], 1) \n node _T_291 = neq(_T_290, UInt<1>(0h0)) \n node _T_292 = or(_T_289, _T_291) \n node _T_293 = asUInt(reset) \n node _T_294 = eq(_T_293, UInt<1>(0h0)) \n when _T_294 : \n node _T_295 = eq(_T_292, UInt<1>(0h0)) \n when _T_295 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at issue-unit-age-ordered.scala:214 assert (!io.dis_uops(w).ready || (shamts_oh(w+numIssueSlots) >> w) =/= 0.U)\\n\") : printf_2 \n assert(clock, _T_292, UInt<1>(0h1), \"\") : assert_2 \n wire iss_uops : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}[2] \n connect iss_uops[0].valid, UInt<1>(0h0) \n invalidate iss_uops[0].bits.debug_tsrc \n invalidate iss_uops[0].bits.debug_fsrc \n invalidate iss_uops[0].bits.bp_xcpt_if \n invalidate iss_uops[0].bits.bp_debug_if \n invalidate iss_uops[0].bits.xcpt_ma_if \n invalidate iss_uops[0].bits.xcpt_ae_if \n invalidate iss_uops[0].bits.xcpt_pf_if \n invalidate iss_uops[0].bits.fp_typ \n invalidate iss_uops[0].bits.fp_rm \n invalidate iss_uops[0].bits.fp_val \n invalidate iss_uops[0].bits.fcn_op \n invalidate iss_uops[0].bits.fcn_dw \n invalidate iss_uops[0].bits.frs3_en \n invalidate iss_uops[0].bits.lrs2_rtype \n invalidate iss_uops[0].bits.lrs1_rtype \n invalidate iss_uops[0].bits.dst_rtype \n invalidate iss_uops[0].bits.lrs3 \n invalidate iss_uops[0].bits.lrs2 \n invalidate iss_uops[0].bits.lrs1 \n invalidate iss_uops[0].bits.ldst \n invalidate iss_uops[0].bits.ldst_is_rs1 \n invalidate iss_uops[0].bits.csr_cmd \n invalidate iss_uops[0].bits.flush_on_commit \n invalidate iss_uops[0].bits.is_unique \n invalidate iss_uops[0].bits.uses_stq \n invalidate iss_uops[0].bits.uses_ldq \n invalidate iss_uops[0].bits.mem_signed \n invalidate iss_uops[0].bits.mem_size \n invalidate iss_uops[0].bits.mem_cmd \n invalidate iss_uops[0].bits.exc_cause \n invalidate iss_uops[0].bits.exception \n invalidate iss_uops[0].bits.stale_pdst \n invalidate iss_uops[0].bits.ppred_busy \n invalidate iss_uops[0].bits.prs3_busy \n invalidate iss_uops[0].bits.prs2_busy \n invalidate iss_uops[0].bits.prs1_busy \n invalidate iss_uops[0].bits.ppred \n invalidate iss_uops[0].bits.prs3 \n invalidate iss_uops[0].bits.prs2 \n invalidate iss_uops[0].bits.prs1 \n invalidate iss_uops[0].bits.pdst \n invalidate iss_uops[0].bits.rxq_idx \n invalidate iss_uops[0].bits.stq_idx \n invalidate iss_uops[0].bits.ldq_idx \n invalidate iss_uops[0].bits.rob_idx \n invalidate iss_uops[0].bits.fp_ctrl.vec \n invalidate iss_uops[0].bits.fp_ctrl.wflags \n invalidate iss_uops[0].bits.fp_ctrl.sqrt \n invalidate iss_uops[0].bits.fp_ctrl.div \n invalidate iss_uops[0].bits.fp_ctrl.fma \n invalidate iss_uops[0].bits.fp_ctrl.fastpipe \n invalidate iss_uops[0].bits.fp_ctrl.toint \n invalidate iss_uops[0].bits.fp_ctrl.fromint \n invalidate iss_uops[0].bits.fp_ctrl.typeTagOut \n invalidate iss_uops[0].bits.fp_ctrl.typeTagIn \n invalidate iss_uops[0].bits.fp_ctrl.swap23 \n invalidate iss_uops[0].bits.fp_ctrl.swap12 \n invalidate iss_uops[0].bits.fp_ctrl.ren3 \n invalidate iss_uops[0].bits.fp_ctrl.ren2 \n invalidate iss_uops[0].bits.fp_ctrl.ren1 \n invalidate iss_uops[0].bits.fp_ctrl.wen \n invalidate iss_uops[0].bits.fp_ctrl.ldst \n invalidate iss_uops[0].bits.op2_sel \n invalidate iss_uops[0].bits.op1_sel \n invalidate iss_uops[0].bits.imm_packed \n invalidate iss_uops[0].bits.pimm \n invalidate iss_uops[0].bits.imm_sel \n invalidate iss_uops[0].bits.imm_rename \n invalidate iss_uops[0].bits.taken \n invalidate iss_uops[0].bits.pc_lob \n invalidate iss_uops[0].bits.edge_inst \n invalidate iss_uops[0].bits.ftq_idx \n invalidate iss_uops[0].bits.is_mov \n invalidate iss_uops[0].bits.is_rocc \n invalidate iss_uops[0].bits.is_sys_pc2epc \n invalidate iss_uops[0].bits.is_eret \n invalidate iss_uops[0].bits.is_amo \n invalidate iss_uops[0].bits.is_sfence \n invalidate iss_uops[0].bits.is_fencei \n invalidate iss_uops[0].bits.is_fence \n invalidate iss_uops[0].bits.is_sfb \n invalidate iss_uops[0].bits.br_type \n invalidate iss_uops[0].bits.br_tag \n invalidate iss_uops[0].bits.br_mask \n invalidate iss_uops[0].bits.dis_col_sel \n invalidate iss_uops[0].bits.iw_p3_bypass_hint \n invalidate iss_uops[0].bits.iw_p2_bypass_hint \n invalidate iss_uops[0].bits.iw_p1_bypass_hint \n invalidate iss_uops[0].bits.iw_p2_speculative_child \n invalidate iss_uops[0].bits.iw_p1_speculative_child \n invalidate iss_uops[0].bits.iw_issued_partial_dgen \n invalidate iss_uops[0].bits.iw_issued_partial_agen \n invalidate iss_uops[0].bits.iw_issued \n invalidate iss_uops[0].bits.fu_code[0] \n invalidate iss_uops[0].bits.fu_code[1] \n invalidate iss_uops[0].bits.fu_code[2] \n invalidate iss_uops[0].bits.fu_code[3] \n invalidate iss_uops[0].bits.fu_code[4] \n invalidate iss_uops[0].bits.fu_code[5] \n invalidate iss_uops[0].bits.fu_code[6] \n invalidate iss_uops[0].bits.fu_code[7] \n invalidate iss_uops[0].bits.fu_code[8] \n invalidate iss_uops[0].bits.fu_code[9] \n invalidate iss_uops[0].bits.iq_type[0] \n invalidate iss_uops[0].bits.iq_type[1] \n invalidate iss_uops[0].bits.iq_type[2] \n invalidate iss_uops[0].bits.iq_type[3] \n invalidate iss_uops[0].bits.debug_pc \n invalidate iss_uops[0].bits.is_rvc \n invalidate iss_uops[0].bits.debug_inst \n invalidate iss_uops[0].bits.inst \n connect iss_uops[1].valid, UInt<1>(0h0) \n invalidate iss_uops[1].bits.debug_tsrc \n invalidate iss_uops[1].bits.debug_fsrc \n invalidate iss_uops[1].bits.bp_xcpt_if \n invalidate iss_uops[1].bits.bp_debug_if \n invalidate iss_uops[1].bits.xcpt_ma_if \n invalidate iss_uops[1].bits.xcpt_ae_if \n invalidate iss_uops[1].bits.xcpt_pf_if \n invalidate iss_uops[1].bits.fp_typ \n invalidate iss_uops[1].bits.fp_rm \n invalidate iss_uops[1].bits.fp_val \n invalidate iss_uops[1].bits.fcn_op \n invalidate iss_uops[1].bits.fcn_dw \n invalidate iss_uops[1].bits.frs3_en \n invalidate iss_uops[1].bits.lrs2_rtype \n invalidate iss_uops[1].bits.lrs1_rtype \n invalidate iss_uops[1].bits.dst_rtype \n invalidate iss_uops[1].bits.lrs3 \n invalidate iss_uops[1].bits.lrs2 \n invalidate iss_uops[1].bits.lrs1 \n invalidate iss_uops[1].bits.ldst \n invalidate iss_uops[1].bits.ldst_is_rs1 \n invalidate iss_uops[1].bits.csr_cmd \n invalidate iss_uops[1].bits.flush_on_commit \n invalidate iss_uops[1].bits.is_unique \n invalidate iss_uops[1].bits.uses_stq \n invalidate iss_uops[1].bits.uses_ldq \n invalidate iss_uops[1].bits.mem_signed \n invalidate iss_uops[1].bits.mem_size \n invalidate iss_uops[1].bits.mem_cmd \n invalidate iss_uops[1].bits.exc_cause \n invalidate iss_uops[1].bits.exception \n invalidate iss_uops[1].bits.stale_pdst \n invalidate iss_uops[1].bits.ppred_busy \n invalidate iss_uops[1].bits.prs3_busy \n invalidate iss_uops[1].bits.prs2_busy \n invalidate iss_uops[1].bits.prs1_busy \n invalidate iss_uops[1].bits.ppred \n invalidate iss_uops[1].bits.prs3 \n invalidate iss_uops[1].bits.prs2 \n invalidate iss_uops[1].bits.prs1 \n invalidate iss_uops[1].bits.pdst \n invalidate iss_uops[1].bits.rxq_idx \n invalidate iss_uops[1].bits.stq_idx \n invalidate iss_uops[1].bits.ldq_idx \n invalidate iss_uops[1].bits.rob_idx \n invalidate iss_uops[1].bits.fp_ctrl.vec \n invalidate iss_uops[1].bits.fp_ctrl.wflags \n invalidate iss_uops[1].bits.fp_ctrl.sqrt \n invalidate iss_uops[1].bits.fp_ctrl.div \n invalidate iss_uops[1].bits.fp_ctrl.fma \n invalidate iss_uops[1].bits.fp_ctrl.fastpipe \n invalidate iss_uops[1].bits.fp_ctrl.toint \n invalidate iss_uops[1].bits.fp_ctrl.fromint \n invalidate iss_uops[1].bits.fp_ctrl.typeTagOut \n invalidate iss_uops[1].bits.fp_ctrl.typeTagIn \n invalidate iss_uops[1].bits.fp_ctrl.swap23 \n invalidate iss_uops[1].bits.fp_ctrl.swap12 \n invalidate iss_uops[1].bits.fp_ctrl.ren3 \n invalidate iss_uops[1].bits.fp_ctrl.ren2 \n invalidate iss_uops[1].bits.fp_ctrl.ren1 \n invalidate iss_uops[1].bits.fp_ctrl.wen \n invalidate iss_uops[1].bits.fp_ctrl.ldst \n invalidate iss_uops[1].bits.op2_sel \n invalidate iss_uops[1].bits.op1_sel \n invalidate iss_uops[1].bits.imm_packed \n invalidate iss_uops[1].bits.pimm \n invalidate iss_uops[1].bits.imm_sel \n invalidate iss_uops[1].bits.imm_rename \n invalidate iss_uops[1].bits.taken \n invalidate iss_uops[1].bits.pc_lob \n invalidate iss_uops[1].bits.edge_inst \n invalidate iss_uops[1].bits.ftq_idx \n invalidate iss_uops[1].bits.is_mov \n invalidate iss_uops[1].bits.is_rocc \n invalidate iss_uops[1].bits.is_sys_pc2epc \n invalidate iss_uops[1].bits.is_eret \n invalidate iss_uops[1].bits.is_amo \n invalidate iss_uops[1].bits.is_sfence \n invalidate iss_uops[1].bits.is_fencei \n invalidate iss_uops[1].bits.is_fence \n invalidate iss_uops[1].bits.is_sfb \n invalidate iss_uops[1].bits.br_type \n invalidate iss_uops[1].bits.br_tag \n invalidate iss_uops[1].bits.br_mask \n invalidate iss_uops[1].bits.dis_col_sel \n invalidate iss_uops[1].bits.iw_p3_bypass_hint \n invalidate iss_uops[1].bits.iw_p2_bypass_hint \n invalidate iss_uops[1].bits.iw_p1_bypass_hint \n invalidate iss_uops[1].bits.iw_p2_speculative_child \n invalidate iss_uops[1].bits.iw_p1_speculative_child \n invalidate iss_uops[1].bits.iw_issued_partial_dgen \n invalidate iss_uops[1].bits.iw_issued_partial_agen \n invalidate iss_uops[1].bits.iw_issued \n invalidate iss_uops[1].bits.fu_code[0] \n invalidate iss_uops[1].bits.fu_code[1] \n invalidate iss_uops[1].bits.fu_code[2] \n invalidate iss_uops[1].bits.fu_code[3] \n invalidate iss_uops[1].bits.fu_code[4] \n invalidate iss_uops[1].bits.fu_code[5] \n invalidate iss_uops[1].bits.fu_code[6] \n invalidate iss_uops[1].bits.fu_code[7] \n invalidate iss_uops[1].bits.fu_code[8] \n invalidate iss_uops[1].bits.fu_code[9] \n invalidate iss_uops[1].bits.iq_type[0] \n invalidate iss_uops[1].bits.iq_type[1] \n invalidate iss_uops[1].bits.iq_type[2] \n invalidate iss_uops[1].bits.iq_type[3] \n invalidate iss_uops[1].bits.debug_pc \n invalidate iss_uops[1].bits.is_rvc \n invalidate iss_uops[1].bits.debug_inst \n invalidate iss_uops[1].bits.inst \n connect issue_slots[0].grant, UInt<1>(0h0) \n node _fu_code_match_T = and(issue_slots[0].iss_uop.fu_code[0], io.fu_types[0][0]) \n node _fu_code_match_T_1 = and(issue_slots[0].iss_uop.fu_code[1], io.fu_types[0][1]) \n node _fu_code_match_T_2 = and(issue_slots[0].iss_uop.fu_code[2], io.fu_types[0][2]) \n node _fu_code_match_T_3 = and(issue_slots[0].iss_uop.fu_code[3], io.fu_types[0][3]) \n node _fu_code_match_T_4 = and(issue_slots[0].iss_uop.fu_code[4], io.fu_types[0][4]) \n node _fu_code_match_T_5 = and(issue_slots[0].iss_uop.fu_code[5], io.fu_types[0][5]) \n node _fu_code_match_T_6 = and(issue_slots[0].iss_uop.fu_code[6], io.fu_types[0][6]) \n node _fu_code_match_T_7 = and(issue_slots[0].iss_uop.fu_code[7], io.fu_types[0][7]) \n node _fu_code_match_T_8 = and(issue_slots[0].iss_uop.fu_code[8], io.fu_types[0][8]) \n node _fu_code_match_T_9 = and(issue_slots[0].iss_uop.fu_code[9], io.fu_types[0][9]) \n node _fu_code_match_T_10 = or(_fu_code_match_T, _fu_code_match_T_1) \n node _fu_code_match_T_11 = or(_fu_code_match_T_10, _fu_code_match_T_2) \n node _fu_code_match_T_12 = or(_fu_code_match_T_11, _fu_code_match_T_3) \n node _fu_code_match_T_13 = or(_fu_code_match_T_12, _fu_code_match_T_4) \n node _fu_code_match_T_14 = or(_fu_code_match_T_13, _fu_code_match_T_5) \n node _fu_code_match_T_15 = or(_fu_code_match_T_14, _fu_code_match_T_6) \n node _fu_code_match_T_16 = or(_fu_code_match_T_15, _fu_code_match_T_7) \n node _fu_code_match_T_17 = or(_fu_code_match_T_16, _fu_code_match_T_8) \n node fu_code_match = or(_fu_code_match_T_17, _fu_code_match_T_9) \n node can_allocate = and(fu_code_match, UInt<1>(0h1)) \n node _T_296 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_297 = and(issue_slots[0].request, _T_296) \n node _T_298 = and(_T_297, can_allocate) \n node _T_299 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_300 = and(_T_298, _T_299) \n when _T_300 : \n connect issue_slots[0].grant, UInt<1>(0h1) \n connect iss_uops[0].valid, UInt<1>(0h1) \n connect iss_uops[0].bits, issue_slots[0].iss_uop \n node _T_301 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_302 = and(issue_slots[0].request, _T_301) \n node _T_303 = and(_T_302, can_allocate) \n node _T_304 = or(_T_303, UInt<1>(0h0)) \n node _T_305 = and(issue_slots[0].request, can_allocate) \n node _T_306 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_307 = and(_T_305, _T_306) \n node _T_308 = or(_T_307, UInt<1>(0h0)) \n node _fu_code_match_T_18 = and(issue_slots[0].iss_uop.fu_code[0], io.fu_types[1][0]) \n node _fu_code_match_T_19 = and(issue_slots[0].iss_uop.fu_code[1], io.fu_types[1][1]) \n node _fu_code_match_T_20 = and(issue_slots[0].iss_uop.fu_code[2], io.fu_types[1][2]) \n node _fu_code_match_T_21 = and(issue_slots[0].iss_uop.fu_code[3], io.fu_types[1][3]) \n node _fu_code_match_T_22 = and(issue_slots[0].iss_uop.fu_code[4], io.fu_types[1][4]) \n node _fu_code_match_T_23 = and(issue_slots[0].iss_uop.fu_code[5], io.fu_types[1][5]) \n node _fu_code_match_T_24 = and(issue_slots[0].iss_uop.fu_code[6], io.fu_types[1][6]) \n node _fu_code_match_T_25 = and(issue_slots[0].iss_uop.fu_code[7], io.fu_types[1][7]) \n node _fu_code_match_T_26 = and(issue_slots[0].iss_uop.fu_code[8], io.fu_types[1][8]) \n node _fu_code_match_T_27 = and(issue_slots[0].iss_uop.fu_code[9], io.fu_types[1][9]) \n node _fu_code_match_T_28 = or(_fu_code_match_T_18, _fu_code_match_T_19) \n node _fu_code_match_T_29 = or(_fu_code_match_T_28, _fu_code_match_T_20) \n node _fu_code_match_T_30 = or(_fu_code_match_T_29, _fu_code_match_T_21) \n node _fu_code_match_T_31 = or(_fu_code_match_T_30, _fu_code_match_T_22) \n node _fu_code_match_T_32 = or(_fu_code_match_T_31, _fu_code_match_T_23) \n node _fu_code_match_T_33 = or(_fu_code_match_T_32, _fu_code_match_T_24) \n node _fu_code_match_T_34 = or(_fu_code_match_T_33, _fu_code_match_T_25) \n node _fu_code_match_T_35 = or(_fu_code_match_T_34, _fu_code_match_T_26) \n node fu_code_match_1 = or(_fu_code_match_T_35, _fu_code_match_T_27) \n node can_allocate_1 = and(fu_code_match_1, UInt<1>(0h1)) \n node _T_309 = eq(_T_308, UInt<1>(0h0)) \n node _T_310 = and(issue_slots[0].request, _T_309) \n node _T_311 = and(_T_310, can_allocate_1) \n node _T_312 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_313 = and(_T_311, _T_312) \n when _T_313 : \n connect issue_slots[0].grant, UInt<1>(0h1) \n connect iss_uops[1].valid, UInt<1>(0h1) \n connect iss_uops[1].bits, issue_slots[0].iss_uop \n node _T_314 = eq(_T_308, UInt<1>(0h0)) \n node _T_315 = and(issue_slots[0].request, _T_314) \n node _T_316 = and(_T_315, can_allocate_1) \n node _T_317 = or(_T_316, UInt<1>(0h0)) \n node _T_318 = and(issue_slots[0].request, can_allocate_1) \n node _T_319 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_320 = and(_T_318, _T_319) \n node _T_321 = or(_T_320, _T_308) \n connect issue_slots[1].grant, UInt<1>(0h0) \n node _fu_code_match_T_36 = and(issue_slots[1].iss_uop.fu_code[0], io.fu_types[0][0]) \n node _fu_code_match_T_37 = and(issue_slots[1].iss_uop.fu_code[1], io.fu_types[0][1]) \n node _fu_code_match_T_38 = and(issue_slots[1].iss_uop.fu_code[2], io.fu_types[0][2]) \n node _fu_code_match_T_39 = and(issue_slots[1].iss_uop.fu_code[3], io.fu_types[0][3]) \n node _fu_code_match_T_40 = and(issue_slots[1].iss_uop.fu_code[4], io.fu_types[0][4]) \n node _fu_code_match_T_41 = and(issue_slots[1].iss_uop.fu_code[5], io.fu_types[0][5]) \n node _fu_code_match_T_42 = and(issue_slots[1].iss_uop.fu_code[6], io.fu_types[0][6]) \n node _fu_code_match_T_43 = and(issue_slots[1].iss_uop.fu_code[7], io.fu_types[0][7]) \n node _fu_code_match_T_44 = and(issue_slots[1].iss_uop.fu_code[8], io.fu_types[0][8]) \n node _fu_code_match_T_45 = and(issue_slots[1].iss_uop.fu_code[9], io.fu_types[0][9]) \n node _fu_code_match_T_46 = or(_fu_code_match_T_36, _fu_code_match_T_37) \n node _fu_code_match_T_47 = or(_fu_code_match_T_46, _fu_code_match_T_38) \n node _fu_code_match_T_48 = or(_fu_code_match_T_47, _fu_code_match_T_39) \n node _fu_code_match_T_49 = or(_fu_code_match_T_48, _fu_code_match_T_40) \n node _fu_code_match_T_50 = or(_fu_code_match_T_49, _fu_code_match_T_41) \n node _fu_code_match_T_51 = or(_fu_code_match_T_50, _fu_code_match_T_42) \n node _fu_code_match_T_52 = or(_fu_code_match_T_51, _fu_code_match_T_43) \n node _fu_code_match_T_53 = or(_fu_code_match_T_52, _fu_code_match_T_44) \n node fu_code_match_2 = or(_fu_code_match_T_53, _fu_code_match_T_45) \n node can_allocate_2 = and(fu_code_match_2, UInt<1>(0h1)) \n node _T_322 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_323 = and(issue_slots[1].request, _T_322) \n node _T_324 = and(_T_323, can_allocate_2) \n node _T_325 = eq(_T_304, UInt<1>(0h0)) \n node _T_326 = and(_T_324, _T_325) \n when _T_326 : \n connect issue_slots[1].grant, UInt<1>(0h1) \n connect iss_uops[0].valid, UInt<1>(0h1) \n connect iss_uops[0].bits, issue_slots[1].iss_uop \n node _T_327 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_328 = and(issue_slots[1].request, _T_327) \n node _T_329 = and(_T_328, can_allocate_2) \n node _T_330 = or(_T_329, _T_304) \n node _T_331 = and(issue_slots[1].request, can_allocate_2) \n node _T_332 = eq(_T_304, UInt<1>(0h0)) \n node _T_333 = and(_T_331, _T_332) \n node _T_334 = or(_T_333, UInt<1>(0h0)) \n node _fu_code_match_T_54 = and(issue_slots[1].iss_uop.fu_code[0], io.fu_types[1][0]) \n node _fu_code_match_T_55 = and(issue_slots[1].iss_uop.fu_code[1], io.fu_types[1][1]) \n node _fu_code_match_T_56 = and(issue_slots[1].iss_uop.fu_code[2], io.fu_types[1][2]) \n node _fu_code_match_T_57 = and(issue_slots[1].iss_uop.fu_code[3], io.fu_types[1][3]) \n node _fu_code_match_T_58 = and(issue_slots[1].iss_uop.fu_code[4], io.fu_types[1][4]) \n node _fu_code_match_T_59 = and(issue_slots[1].iss_uop.fu_code[5], io.fu_types[1][5]) \n node _fu_code_match_T_60 = and(issue_slots[1].iss_uop.fu_code[6], io.fu_types[1][6]) \n node _fu_code_match_T_61 = and(issue_slots[1].iss_uop.fu_code[7], io.fu_types[1][7]) \n node _fu_code_match_T_62 = and(issue_slots[1].iss_uop.fu_code[8], io.fu_types[1][8]) \n node _fu_code_match_T_63 = and(issue_slots[1].iss_uop.fu_code[9], io.fu_types[1][9]) \n node _fu_code_match_T_64 = or(_fu_code_match_T_54, _fu_code_match_T_55) \n node _fu_code_match_T_65 = or(_fu_code_match_T_64, _fu_code_match_T_56) \n node _fu_code_match_T_66 = or(_fu_code_match_T_65, _fu_code_match_T_57) \n node _fu_code_match_T_67 = or(_fu_code_match_T_66, _fu_code_match_T_58) \n node _fu_code_match_T_68 = or(_fu_code_match_T_67, _fu_code_match_T_59) \n node _fu_code_match_T_69 = or(_fu_code_match_T_68, _fu_code_match_T_60) \n node _fu_code_match_T_70 = or(_fu_code_match_T_69, _fu_code_match_T_61) \n node _fu_code_match_T_71 = or(_fu_code_match_T_70, _fu_code_match_T_62) \n node fu_code_match_3 = or(_fu_code_match_T_71, _fu_code_match_T_63) \n node can_allocate_3 = and(fu_code_match_3, UInt<1>(0h1)) \n node _T_335 = eq(_T_334, UInt<1>(0h0)) \n node _T_336 = and(issue_slots[1].request, _T_335) \n node _T_337 = and(_T_336, can_allocate_3) \n node _T_338 = eq(_T_317, UInt<1>(0h0)) \n node _T_339 = and(_T_337, _T_338) \n when _T_339 : \n connect issue_slots[1].grant, UInt<1>(0h1) \n connect iss_uops[1].valid, UInt<1>(0h1) \n connect iss_uops[1].bits, issue_slots[1].iss_uop \n node _T_340 = eq(_T_334, UInt<1>(0h0)) \n node _T_341 = and(issue_slots[1].request, _T_340) \n node _T_342 = and(_T_341, can_allocate_3) \n node _T_343 = or(_T_342, _T_317) \n node _T_344 = and(issue_slots[1].request, can_allocate_3) \n node _T_345 = eq(_T_317, UInt<1>(0h0)) \n node _T_346 = and(_T_344, _T_345) \n node _T_347 = or(_T_346, _T_334) \n connect issue_slots[2].grant, UInt<1>(0h0) \n node _fu_code_match_T_72 = and(issue_slots[2].iss_uop.fu_code[0], io.fu_types[0][0]) \n node _fu_code_match_T_73 = and(issue_slots[2].iss_uop.fu_code[1], io.fu_types[0][1]) \n node _fu_code_match_T_74 = and(issue_slots[2].iss_uop.fu_code[2], io.fu_types[0][2]) \n node _fu_code_match_T_75 = and(issue_slots[2].iss_uop.fu_code[3], io.fu_types[0][3]) \n node _fu_code_match_T_76 = and(issue_slots[2].iss_uop.fu_code[4], io.fu_types[0][4]) \n node _fu_code_match_T_77 = and(issue_slots[2].iss_uop.fu_code[5], io.fu_types[0][5]) \n node _fu_code_match_T_78 = and(issue_slots[2].iss_uop.fu_code[6], io.fu_types[0][6]) \n node _fu_code_match_T_79 = and(issue_slots[2].iss_uop.fu_code[7], io.fu_types[0][7]) \n node _fu_code_match_T_80 = and(issue_slots[2].iss_uop.fu_code[8], io.fu_types[0][8]) \n node _fu_code_match_T_81 = and(issue_slots[2].iss_uop.fu_code[9], io.fu_types[0][9]) \n node _fu_code_match_T_82 = or(_fu_code_match_T_72, _fu_code_match_T_73) \n node _fu_code_match_T_83 = or(_fu_code_match_T_82, _fu_code_match_T_74) \n node _fu_code_match_T_84 = or(_fu_code_match_T_83, _fu_code_match_T_75) \n node _fu_code_match_T_85 = or(_fu_code_match_T_84, _fu_code_match_T_76) \n node _fu_code_match_T_86 = or(_fu_code_match_T_85, _fu_code_match_T_77) \n node _fu_code_match_T_87 = or(_fu_code_match_T_86, _fu_code_match_T_78) \n node _fu_code_match_T_88 = or(_fu_code_match_T_87, _fu_code_match_T_79) \n node _fu_code_match_T_89 = or(_fu_code_match_T_88, _fu_code_match_T_80) \n node fu_code_match_4 = or(_fu_code_match_T_89, _fu_code_match_T_81) \n node can_allocate_4 = and(fu_code_match_4, UInt<1>(0h1)) \n node _T_348 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_349 = and(issue_slots[2].request, _T_348) \n node _T_350 = and(_T_349, can_allocate_4) \n node _T_351 = eq(_T_330, UInt<1>(0h0)) \n node _T_352 = and(_T_350, _T_351) \n when _T_352 : \n connect issue_slots[2].grant, UInt<1>(0h1) \n connect iss_uops[0].valid, UInt<1>(0h1) \n connect iss_uops[0].bits, issue_slots[2].iss_uop \n node _T_353 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_354 = and(issue_slots[2].request, _T_353) \n node _T_355 = and(_T_354, can_allocate_4) \n node _T_356 = or(_T_355, _T_330) \n node _T_357 = and(issue_slots[2].request, can_allocate_4) \n node _T_358 = eq(_T_330, UInt<1>(0h0)) \n node _T_359 = and(_T_357, _T_358) \n node _T_360 = or(_T_359, UInt<1>(0h0)) \n node _fu_code_match_T_90 = and(issue_slots[2].iss_uop.fu_code[0], io.fu_types[1][0]) \n node _fu_code_match_T_91 = and(issue_slots[2].iss_uop.fu_code[1], io.fu_types[1][1]) \n node _fu_code_match_T_92 = and(issue_slots[2].iss_uop.fu_code[2], io.fu_types[1][2]) \n node _fu_code_match_T_93 = and(issue_slots[2].iss_uop.fu_code[3], io.fu_types[1][3]) \n node _fu_code_match_T_94 = and(issue_slots[2].iss_uop.fu_code[4], io.fu_types[1][4]) \n node _fu_code_match_T_95 = and(issue_slots[2].iss_uop.fu_code[5], io.fu_types[1][5]) \n node _fu_code_match_T_96 = and(issue_slots[2].iss_uop.fu_code[6], io.fu_types[1][6]) \n node _fu_code_match_T_97 = and(issue_slots[2].iss_uop.fu_code[7], io.fu_types[1][7]) \n node _fu_code_match_T_98 = and(issue_slots[2].iss_uop.fu_code[8], io.fu_types[1][8]) \n node _fu_code_match_T_99 = and(issue_slots[2].iss_uop.fu_code[9], io.fu_types[1][9]) \n node _fu_code_match_T_100 = or(_fu_code_match_T_90, _fu_code_match_T_91) \n node _fu_code_match_T_101 = or(_fu_code_match_T_100, _fu_code_match_T_92) \n node _fu_code_match_T_102 = or(_fu_code_match_T_101, _fu_code_match_T_93) \n node _fu_code_match_T_103 = or(_fu_code_match_T_102, _fu_code_match_T_94) \n node _fu_code_match_T_104 = or(_fu_code_match_T_103, _fu_code_match_T_95) \n node _fu_code_match_T_105 = or(_fu_code_match_T_104, _fu_code_match_T_96) \n node _fu_code_match_T_106 = or(_fu_code_match_T_105, _fu_code_match_T_97) \n node _fu_code_match_T_107 = or(_fu_code_match_T_106, _fu_code_match_T_98) \n node fu_code_match_5 = or(_fu_code_match_T_107, _fu_code_match_T_99) \n node can_allocate_5 = and(fu_code_match_5, UInt<1>(0h1)) \n node _T_361 = eq(_T_360, UInt<1>(0h0)) \n node _T_362 = and(issue_slots[2].request, _T_361) \n node _T_363 = and(_T_362, can_allocate_5) \n node _T_364 = eq(_T_343, UInt<1>(0h0)) \n node _T_365 = and(_T_363, _T_364) \n when _T_365 : \n connect issue_slots[2].grant, UInt<1>(0h1) \n connect iss_uops[1].valid, UInt<1>(0h1) \n connect iss_uops[1].bits, issue_slots[2].iss_uop \n node _T_366 = eq(_T_360, UInt<1>(0h0)) \n node _T_367 = and(issue_slots[2].request, _T_366) \n node _T_368 = and(_T_367, can_allocate_5) \n node _T_369 = or(_T_368, _T_343) \n node _T_370 = and(issue_slots[2].request, can_allocate_5) \n node _T_371 = eq(_T_343, UInt<1>(0h0)) \n node _T_372 = and(_T_370, _T_371) \n node _T_373 = or(_T_372, _T_360) \n connect issue_slots[3].grant, UInt<1>(0h0) \n node _fu_code_match_T_108 = and(issue_slots[3].iss_uop.fu_code[0], io.fu_types[0][0]) \n node _fu_code_match_T_109 = and(issue_slots[3].iss_uop.fu_code[1], io.fu_types[0][1]) \n node _fu_code_match_T_110 = and(issue_slots[3].iss_uop.fu_code[2], io.fu_types[0][2]) \n node _fu_code_match_T_111 = and(issue_slots[3].iss_uop.fu_code[3], io.fu_types[0][3]) \n node _fu_code_match_T_112 = and(issue_slots[3].iss_uop.fu_code[4], io.fu_types[0][4]) \n node _fu_code_match_T_113 = and(issue_slots[3].iss_uop.fu_code[5], io.fu_types[0][5]) \n node _fu_code_match_T_114 = and(issue_slots[3].iss_uop.fu_code[6], io.fu_types[0][6]) \n node _fu_code_match_T_115 = and(issue_slots[3].iss_uop.fu_code[7], io.fu_types[0][7]) \n node _fu_code_match_T_116 = and(issue_slots[3].iss_uop.fu_code[8], io.fu_types[0][8]) \n node _fu_code_match_T_117 = and(issue_slots[3].iss_uop.fu_code[9], io.fu_types[0][9]) \n node _fu_code_match_T_118 = or(_fu_code_match_T_108, _fu_code_match_T_109) \n node _fu_code_match_T_119 = or(_fu_code_match_T_118, _fu_code_match_T_110) \n node _fu_code_match_T_120 = or(_fu_code_match_T_119, _fu_code_match_T_111) \n node _fu_code_match_T_121 = or(_fu_code_match_T_120, _fu_code_match_T_112) \n node _fu_code_match_T_122 = or(_fu_code_match_T_121, _fu_code_match_T_113) \n node _fu_code_match_T_123 = or(_fu_code_match_T_122, _fu_code_match_T_114) \n node _fu_code_match_T_124 = or(_fu_code_match_T_123, _fu_code_match_T_115) \n node _fu_code_match_T_125 = or(_fu_code_match_T_124, _fu_code_match_T_116) \n node fu_code_match_6 = or(_fu_code_match_T_125, _fu_code_match_T_117) \n node can_allocate_6 = and(fu_code_match_6, UInt<1>(0h1)) \n node _T_374 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_375 = and(issue_slots[3].request, _T_374) \n node _T_376 = and(_T_375, can_allocate_6) \n node _T_377 = eq(_T_356, UInt<1>(0h0)) \n node _T_378 = and(_T_376, _T_377) \n when _T_378 : \n connect issue_slots[3].grant, UInt<1>(0h1) \n connect iss_uops[0].valid, UInt<1>(0h1) \n connect iss_uops[0].bits, issue_slots[3].iss_uop \n node _T_379 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_380 = and(issue_slots[3].request, _T_379) \n node _T_381 = and(_T_380, can_allocate_6) \n node _T_382 = or(_T_381, _T_356) \n node _T_383 = and(issue_slots[3].request, can_allocate_6) \n node _T_384 = eq(_T_356, UInt<1>(0h0)) \n node _T_385 = and(_T_383, _T_384) \n node _T_386 = or(_T_385, UInt<1>(0h0)) \n node _fu_code_match_T_126 = and(issue_slots[3].iss_uop.fu_code[0], io.fu_types[1][0]) \n node _fu_code_match_T_127 = and(issue_slots[3].iss_uop.fu_code[1], io.fu_types[1][1]) \n node _fu_code_match_T_128 = and(issue_slots[3].iss_uop.fu_code[2], io.fu_types[1][2]) \n node _fu_code_match_T_129 = and(issue_slots[3].iss_uop.fu_code[3], io.fu_types[1][3]) \n node _fu_code_match_T_130 = and(issue_slots[3].iss_uop.fu_code[4], io.fu_types[1][4]) \n node _fu_code_match_T_131 = and(issue_slots[3].iss_uop.fu_code[5], io.fu_types[1][5]) \n node _fu_code_match_T_132 = and(issue_slots[3].iss_uop.fu_code[6], io.fu_types[1][6]) \n node _fu_code_match_T_133 = and(issue_slots[3].iss_uop.fu_code[7], io.fu_types[1][7]) \n node _fu_code_match_T_134 = and(issue_slots[3].iss_uop.fu_code[8], io.fu_types[1][8]) \n node _fu_code_match_T_135 = and(issue_slots[3].iss_uop.fu_code[9], io.fu_types[1][9]) \n node _fu_code_match_T_136 = or(_fu_code_match_T_126, _fu_code_match_T_127) \n node _fu_code_match_T_137 = or(_fu_code_match_T_136, _fu_code_match_T_128) \n node _fu_code_match_T_138 = or(_fu_code_match_T_137, _fu_code_match_T_129) \n node _fu_code_match_T_139 = or(_fu_code_match_T_138, _fu_code_match_T_130) \n node _fu_code_match_T_140 = or(_fu_code_match_T_139, _fu_code_match_T_131) \n node _fu_code_match_T_141 = or(_fu_code_match_T_140, _fu_code_match_T_132) \n node _fu_code_match_T_142 = or(_fu_code_match_T_141, _fu_code_match_T_133) \n node _fu_code_match_T_143 = or(_fu_code_match_T_142, _fu_code_match_T_134) \n node fu_code_match_7 = or(_fu_code_match_T_143, _fu_code_match_T_135) \n node can_allocate_7 = and(fu_code_match_7, UInt<1>(0h1)) \n node _T_387 = eq(_T_386, UInt<1>(0h0)) \n node _T_388 = and(issue_slots[3].request, _T_387) \n node _T_389 = and(_T_388, can_allocate_7) \n node _T_390 = eq(_T_369, UInt<1>(0h0)) \n node _T_391 = and(_T_389, _T_390) \n when _T_391 : \n connect issue_slots[3].grant, UInt<1>(0h1) \n connect iss_uops[1].valid, UInt<1>(0h1) \n connect iss_uops[1].bits, issue_slots[3].iss_uop \n node _T_392 = eq(_T_386, UInt<1>(0h0)) \n node _T_393 = and(issue_slots[3].request, _T_392) \n node _T_394 = and(_T_393, can_allocate_7) \n node _T_395 = or(_T_394, _T_369) \n node _T_396 = and(issue_slots[3].request, can_allocate_7) \n node _T_397 = eq(_T_369, UInt<1>(0h0)) \n node _T_398 = and(_T_396, _T_397) \n node _T_399 = or(_T_398, _T_386) \n connect issue_slots[4].grant, UInt<1>(0h0) \n node _fu_code_match_T_144 = and(issue_slots[4].iss_uop.fu_code[0], io.fu_types[0][0]) \n node _fu_code_match_T_145 = and(issue_slots[4].iss_uop.fu_code[1], io.fu_types[0][1]) \n node _fu_code_match_T_146 = and(issue_slots[4].iss_uop.fu_code[2], io.fu_types[0][2]) \n node _fu_code_match_T_147 = and(issue_slots[4].iss_uop.fu_code[3], io.fu_types[0][3]) \n node _fu_code_match_T_148 = and(issue_slots[4].iss_uop.fu_code[4], io.fu_types[0][4]) \n node _fu_code_match_T_149 = and(issue_slots[4].iss_uop.fu_code[5], io.fu_types[0][5]) \n node _fu_code_match_T_150 = and(issue_slots[4].iss_uop.fu_code[6], io.fu_types[0][6]) \n node _fu_code_match_T_151 = and(issue_slots[4].iss_uop.fu_code[7], io.fu_types[0][7]) \n node _fu_code_match_T_152 = and(issue_slots[4].iss_uop.fu_code[8], io.fu_types[0][8]) \n node _fu_code_match_T_153 = and(issue_slots[4].iss_uop.fu_code[9], io.fu_types[0][9]) \n node _fu_code_match_T_154 = or(_fu_code_match_T_144, _fu_code_match_T_145) \n node _fu_code_match_T_155 = or(_fu_code_match_T_154, _fu_code_match_T_146) \n node _fu_code_match_T_156 = or(_fu_code_match_T_155, _fu_code_match_T_147) \n node _fu_code_match_T_157 = or(_fu_code_match_T_156, _fu_code_match_T_148) \n node _fu_code_match_T_158 = or(_fu_code_match_T_157, _fu_code_match_T_149) \n node _fu_code_match_T_159 = or(_fu_code_match_T_158, _fu_code_match_T_150) \n node _fu_code_match_T_160 = or(_fu_code_match_T_159, _fu_code_match_T_151) \n node _fu_code_match_T_161 = or(_fu_code_match_T_160, _fu_code_match_T_152) \n node fu_code_match_8 = or(_fu_code_match_T_161, _fu_code_match_T_153) \n node can_allocate_8 = and(fu_code_match_8, UInt<1>(0h1)) \n node _T_400 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_401 = and(issue_slots[4].request, _T_400) \n node _T_402 = and(_T_401, can_allocate_8) \n node _T_403 = eq(_T_382, UInt<1>(0h0)) \n node _T_404 = and(_T_402, _T_403) \n when _T_404 : \n connect issue_slots[4].grant, UInt<1>(0h1) \n connect iss_uops[0].valid, UInt<1>(0h1) \n connect iss_uops[0].bits, issue_slots[4].iss_uop \n node _T_405 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_406 = and(issue_slots[4].request, _T_405) \n node _T_407 = and(_T_406, can_allocate_8) \n node _T_408 = or(_T_407, _T_382) \n node _T_409 = and(issue_slots[4].request, can_allocate_8) \n node _T_410 = eq(_T_382, UInt<1>(0h0)) \n node _T_411 = and(_T_409, _T_410) \n node _T_412 = or(_T_411, UInt<1>(0h0)) \n node _fu_code_match_T_162 = and(issue_slots[4].iss_uop.fu_code[0], io.fu_types[1][0]) \n node _fu_code_match_T_163 = and(issue_slots[4].iss_uop.fu_code[1], io.fu_types[1][1]) \n node _fu_code_match_T_164 = and(issue_slots[4].iss_uop.fu_code[2], io.fu_types[1][2]) \n node _fu_code_match_T_165 = and(issue_slots[4].iss_uop.fu_code[3], io.fu_types[1][3]) \n node _fu_code_match_T_166 = and(issue_slots[4].iss_uop.fu_code[4], io.fu_types[1][4]) \n node _fu_code_match_T_167 = and(issue_slots[4].iss_uop.fu_code[5], io.fu_types[1][5]) \n node _fu_code_match_T_168 = and(issue_slots[4].iss_uop.fu_code[6], io.fu_types[1][6]) \n node _fu_code_match_T_169 = and(issue_slots[4].iss_uop.fu_code[7], io.fu_types[1][7]) \n node _fu_code_match_T_170 = and(issue_slots[4].iss_uop.fu_code[8], io.fu_types[1][8]) \n node _fu_code_match_T_171 = and(issue_slots[4].iss_uop.fu_code[9], io.fu_types[1][9]) \n node _fu_code_match_T_172 = or(_fu_code_match_T_162, _fu_code_match_T_163) \n node _fu_code_match_T_173 = or(_fu_code_match_T_172, _fu_code_match_T_164) \n node _fu_code_match_T_174 = or(_fu_code_match_T_173, _fu_code_match_T_165) \n node _fu_code_match_T_175 = or(_fu_code_match_T_174, _fu_code_match_T_166) \n node _fu_code_match_T_176 = or(_fu_code_match_T_175, _fu_code_match_T_167) \n node _fu_code_match_T_177 = or(_fu_code_match_T_176, _fu_code_match_T_168) \n node _fu_code_match_T_178 = or(_fu_code_match_T_177, _fu_code_match_T_169) \n node _fu_code_match_T_179 = or(_fu_code_match_T_178, _fu_code_match_T_170) \n node fu_code_match_9 = or(_fu_code_match_T_179, _fu_code_match_T_171) \n node can_allocate_9 = and(fu_code_match_9, UInt<1>(0h1)) \n node _T_413 = eq(_T_412, UInt<1>(0h0)) \n node _T_414 = and(issue_slots[4].request, _T_413) \n node _T_415 = and(_T_414, can_allocate_9) \n node _T_416 = eq(_T_395, UInt<1>(0h0)) \n node _T_417 = and(_T_415, _T_416) \n when _T_417 : \n connect issue_slots[4].grant, UInt<1>(0h1) \n connect iss_uops[1].valid, UInt<1>(0h1) \n connect iss_uops[1].bits, issue_slots[4].iss_uop \n node _T_418 = eq(_T_412, UInt<1>(0h0)) \n node _T_419 = and(issue_slots[4].request, _T_418) \n node _T_420 = and(_T_419, can_allocate_9) \n node _T_421 = or(_T_420, _T_395) \n node _T_422 = and(issue_slots[4].request, can_allocate_9) \n node _T_423 = eq(_T_395, UInt<1>(0h0)) \n node _T_424 = and(_T_422, _T_423) \n node _T_425 = or(_T_424, _T_412) \n connect issue_slots[5].grant, UInt<1>(0h0) \n node _fu_code_match_T_180 = and(issue_slots[5].iss_uop.fu_code[0], io.fu_types[0][0]) \n node _fu_code_match_T_181 = and(issue_slots[5].iss_uop.fu_code[1], io.fu_types[0][1]) \n node _fu_code_match_T_182 = and(issue_slots[5].iss_uop.fu_code[2], io.fu_types[0][2]) \n node _fu_code_match_T_183 = and(issue_slots[5].iss_uop.fu_code[3], io.fu_types[0][3]) \n node _fu_code_match_T_184 = and(issue_slots[5].iss_uop.fu_code[4], io.fu_types[0][4]) \n node _fu_code_match_T_185 = and(issue_slots[5].iss_uop.fu_code[5], io.fu_types[0][5]) \n node _fu_code_match_T_186 = and(issue_slots[5].iss_uop.fu_code[6], io.fu_types[0][6]) \n node _fu_code_match_T_187 = and(issue_slots[5].iss_uop.fu_code[7], io.fu_types[0][7]) \n node _fu_code_match_T_188 = and(issue_slots[5].iss_uop.fu_code[8], io.fu_types[0][8]) \n node _fu_code_match_T_189 = and(issue_slots[5].iss_uop.fu_code[9], io.fu_types[0][9]) \n node _fu_code_match_T_190 = or(_fu_code_match_T_180, _fu_code_match_T_181) \n node _fu_code_match_T_191 = or(_fu_code_match_T_190, _fu_code_match_T_182) \n node _fu_code_match_T_192 = or(_fu_code_match_T_191, _fu_code_match_T_183) \n node _fu_code_match_T_193 = or(_fu_code_match_T_192, _fu_code_match_T_184) \n node _fu_code_match_T_194 = or(_fu_code_match_T_193, _fu_code_match_T_185) \n node _fu_code_match_T_195 = or(_fu_code_match_T_194, _fu_code_match_T_186) \n node _fu_code_match_T_196 = or(_fu_code_match_T_195, _fu_code_match_T_187) \n node _fu_code_match_T_197 = or(_fu_code_match_T_196, _fu_code_match_T_188) \n node fu_code_match_10 = or(_fu_code_match_T_197, _fu_code_match_T_189) \n node can_allocate_10 = and(fu_code_match_10, UInt<1>(0h1)) \n node _T_426 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_427 = and(issue_slots[5].request, _T_426) \n node _T_428 = and(_T_427, can_allocate_10) \n node _T_429 = eq(_T_408, UInt<1>(0h0)) \n node _T_430 = and(_T_428, _T_429) \n when _T_430 : \n connect issue_slots[5].grant, UInt<1>(0h1) \n connect iss_uops[0].valid, UInt<1>(0h1) \n connect iss_uops[0].bits, issue_slots[5].iss_uop \n node _T_431 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_432 = and(issue_slots[5].request, _T_431) \n node _T_433 = and(_T_432, can_allocate_10) \n node _T_434 = or(_T_433, _T_408) \n node _T_435 = and(issue_slots[5].request, can_allocate_10) \n node _T_436 = eq(_T_408, UInt<1>(0h0)) \n node _T_437 = and(_T_435, _T_436) \n node _T_438 = or(_T_437, UInt<1>(0h0)) \n node _fu_code_match_T_198 = and(issue_slots[5].iss_uop.fu_code[0], io.fu_types[1][0]) \n node _fu_code_match_T_199 = and(issue_slots[5].iss_uop.fu_code[1], io.fu_types[1][1]) \n node _fu_code_match_T_200 = and(issue_slots[5].iss_uop.fu_code[2], io.fu_types[1][2]) \n node _fu_code_match_T_201 = and(issue_slots[5].iss_uop.fu_code[3], io.fu_types[1][3]) \n node _fu_code_match_T_202 = and(issue_slots[5].iss_uop.fu_code[4], io.fu_types[1][4]) \n node _fu_code_match_T_203 = and(issue_slots[5].iss_uop.fu_code[5], io.fu_types[1][5]) \n node _fu_code_match_T_204 = and(issue_slots[5].iss_uop.fu_code[6], io.fu_types[1][6]) \n node _fu_code_match_T_205 = and(issue_slots[5].iss_uop.fu_code[7], io.fu_types[1][7]) \n node _fu_code_match_T_206 = and(issue_slots[5].iss_uop.fu_code[8], io.fu_types[1][8]) \n node _fu_code_match_T_207 = and(issue_slots[5].iss_uop.fu_code[9], io.fu_types[1][9]) \n node _fu_code_match_T_208 = or(_fu_code_match_T_198, _fu_code_match_T_199) \n node _fu_code_match_T_209 = or(_fu_code_match_T_208, _fu_code_match_T_200) \n node _fu_code_match_T_210 = or(_fu_code_match_T_209, _fu_code_match_T_201) \n node _fu_code_match_T_211 = or(_fu_code_match_T_210, _fu_code_match_T_202) \n node _fu_code_match_T_212 = or(_fu_code_match_T_211, _fu_code_match_T_203) \n node _fu_code_match_T_213 = or(_fu_code_match_T_212, _fu_code_match_T_204) \n node _fu_code_match_T_214 = or(_fu_code_match_T_213, _fu_code_match_T_205) \n node _fu_code_match_T_215 = or(_fu_code_match_T_214, _fu_code_match_T_206) \n node fu_code_match_11 = or(_fu_code_match_T_215, _fu_code_match_T_207) \n node can_allocate_11 = and(fu_code_match_11, UInt<1>(0h1)) \n node _T_439 = eq(_T_438, UInt<1>(0h0)) \n node _T_440 = and(issue_slots[5].request, _T_439) \n node _T_441 = and(_T_440, can_allocate_11) \n node _T_442 = eq(_T_421, UInt<1>(0h0)) \n node _T_443 = and(_T_441, _T_442) \n when _T_443 : \n connect issue_slots[5].grant, UInt<1>(0h1) \n connect iss_uops[1].valid, UInt<1>(0h1) \n connect iss_uops[1].bits, issue_slots[5].iss_uop \n node _T_444 = eq(_T_438, UInt<1>(0h0)) \n node _T_445 = and(issue_slots[5].request, _T_444) \n node _T_446 = and(_T_445, can_allocate_11) \n node _T_447 = or(_T_446, _T_421) \n node _T_448 = and(issue_slots[5].request, can_allocate_11) \n node _T_449 = eq(_T_421, UInt<1>(0h0)) \n node _T_450 = and(_T_448, _T_449) \n node _T_451 = or(_T_450, _T_438) \n connect issue_slots[6].grant, UInt<1>(0h0) \n node _fu_code_match_T_216 = and(issue_slots[6].iss_uop.fu_code[0], io.fu_types[0][0]) \n node _fu_code_match_T_217 = and(issue_slots[6].iss_uop.fu_code[1], io.fu_types[0][1]) \n node _fu_code_match_T_218 = and(issue_slots[6].iss_uop.fu_code[2], io.fu_types[0][2]) \n node _fu_code_match_T_219 = and(issue_slots[6].iss_uop.fu_code[3], io.fu_types[0][3]) \n node _fu_code_match_T_220 = and(issue_slots[6].iss_uop.fu_code[4], io.fu_types[0][4]) \n node _fu_code_match_T_221 = and(issue_slots[6].iss_uop.fu_code[5], io.fu_types[0][5]) \n node _fu_code_match_T_222 = and(issue_slots[6].iss_uop.fu_code[6], io.fu_types[0][6]) \n node _fu_code_match_T_223 = and(issue_slots[6].iss_uop.fu_code[7], io.fu_types[0][7]) \n node _fu_code_match_T_224 = and(issue_slots[6].iss_uop.fu_code[8], io.fu_types[0][8]) \n node _fu_code_match_T_225 = and(issue_slots[6].iss_uop.fu_code[9], io.fu_types[0][9]) \n node _fu_code_match_T_226 = or(_fu_code_match_T_216, _fu_code_match_T_217) \n node _fu_code_match_T_227 = or(_fu_code_match_T_226, _fu_code_match_T_218) \n node _fu_code_match_T_228 = or(_fu_code_match_T_227, _fu_code_match_T_219) \n node _fu_code_match_T_229 = or(_fu_code_match_T_228, _fu_code_match_T_220) \n node _fu_code_match_T_230 = or(_fu_code_match_T_229, _fu_code_match_T_221) \n node _fu_code_match_T_231 = or(_fu_code_match_T_230, _fu_code_match_T_222) \n node _fu_code_match_T_232 = or(_fu_code_match_T_231, _fu_code_match_T_223) \n node _fu_code_match_T_233 = or(_fu_code_match_T_232, _fu_code_match_T_224) \n node fu_code_match_12 = or(_fu_code_match_T_233, _fu_code_match_T_225) \n node can_allocate_12 = and(fu_code_match_12, UInt<1>(0h1)) \n node _T_452 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_453 = and(issue_slots[6].request, _T_452) \n node _T_454 = and(_T_453, can_allocate_12) \n node _T_455 = eq(_T_434, UInt<1>(0h0)) \n node _T_456 = and(_T_454, _T_455) \n when _T_456 : \n connect issue_slots[6].grant, UInt<1>(0h1) \n connect iss_uops[0].valid, UInt<1>(0h1) \n connect iss_uops[0].bits, issue_slots[6].iss_uop \n node _T_457 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_458 = and(issue_slots[6].request, _T_457) \n node _T_459 = and(_T_458, can_allocate_12) \n node _T_460 = or(_T_459, _T_434) \n node _T_461 = and(issue_slots[6].request, can_allocate_12) \n node _T_462 = eq(_T_434, UInt<1>(0h0)) \n node _T_463 = and(_T_461, _T_462) \n node _T_464 = or(_T_463, UInt<1>(0h0)) \n node _fu_code_match_T_234 = and(issue_slots[6].iss_uop.fu_code[0], io.fu_types[1][0]) \n node _fu_code_match_T_235 = and(issue_slots[6].iss_uop.fu_code[1], io.fu_types[1][1]) \n node _fu_code_match_T_236 = and(issue_slots[6].iss_uop.fu_code[2], io.fu_types[1][2]) \n node _fu_code_match_T_237 = and(issue_slots[6].iss_uop.fu_code[3], io.fu_types[1][3]) \n node _fu_code_match_T_238 = and(issue_slots[6].iss_uop.fu_code[4], io.fu_types[1][4]) \n node _fu_code_match_T_239 = and(issue_slots[6].iss_uop.fu_code[5], io.fu_types[1][5]) \n node _fu_code_match_T_240 = and(issue_slots[6].iss_uop.fu_code[6], io.fu_types[1][6]) \n node _fu_code_match_T_241 = and(issue_slots[6].iss_uop.fu_code[7], io.fu_types[1][7]) \n node _fu_code_match_T_242 = and(issue_slots[6].iss_uop.fu_code[8], io.fu_types[1][8]) \n node _fu_code_match_T_243 = and(issue_slots[6].iss_uop.fu_code[9], io.fu_types[1][9]) \n node _fu_code_match_T_244 = or(_fu_code_match_T_234, _fu_code_match_T_235) \n node _fu_code_match_T_245 = or(_fu_code_match_T_244, _fu_code_match_T_236) \n node _fu_code_match_T_246 = or(_fu_code_match_T_245, _fu_code_match_T_237) \n node _fu_code_match_T_247 = or(_fu_code_match_T_246, _fu_code_match_T_238) \n node _fu_code_match_T_248 = or(_fu_code_match_T_247, _fu_code_match_T_239) \n node _fu_code_match_T_249 = or(_fu_code_match_T_248, _fu_code_match_T_240) \n node _fu_code_match_T_250 = or(_fu_code_match_T_249, _fu_code_match_T_241) \n node _fu_code_match_T_251 = or(_fu_code_match_T_250, _fu_code_match_T_242) \n node fu_code_match_13 = or(_fu_code_match_T_251, _fu_code_match_T_243) \n node can_allocate_13 = and(fu_code_match_13, UInt<1>(0h1)) \n node _T_465 = eq(_T_464, UInt<1>(0h0)) \n node _T_466 = and(issue_slots[6].request, _T_465) \n node _T_467 = and(_T_466, can_allocate_13) \n node _T_468 = eq(_T_447, UInt<1>(0h0)) \n node _T_469 = and(_T_467, _T_468) \n when _T_469 : \n connect issue_slots[6].grant, UInt<1>(0h1) \n connect iss_uops[1].valid, UInt<1>(0h1) \n connect iss_uops[1].bits, issue_slots[6].iss_uop \n node _T_470 = eq(_T_464, UInt<1>(0h0)) \n node _T_471 = and(issue_slots[6].request, _T_470) \n node _T_472 = and(_T_471, can_allocate_13) \n node _T_473 = or(_T_472, _T_447) \n node _T_474 = and(issue_slots[6].request, can_allocate_13) \n node _T_475 = eq(_T_447, UInt<1>(0h0)) \n node _T_476 = and(_T_474, _T_475) \n node _T_477 = or(_T_476, _T_464) \n connect issue_slots[7].grant, UInt<1>(0h0) \n node _fu_code_match_T_252 = and(issue_slots[7].iss_uop.fu_code[0], io.fu_types[0][0]) \n node _fu_code_match_T_253 = and(issue_slots[7].iss_uop.fu_code[1], io.fu_types[0][1]) \n node _fu_code_match_T_254 = and(issue_slots[7].iss_uop.fu_code[2], io.fu_types[0][2]) \n node _fu_code_match_T_255 = and(issue_slots[7].iss_uop.fu_code[3], io.fu_types[0][3]) \n node _fu_code_match_T_256 = and(issue_slots[7].iss_uop.fu_code[4], io.fu_types[0][4]) \n node _fu_code_match_T_257 = and(issue_slots[7].iss_uop.fu_code[5], io.fu_types[0][5]) \n node _fu_code_match_T_258 = and(issue_slots[7].iss_uop.fu_code[6], io.fu_types[0][6]) \n node _fu_code_match_T_259 = and(issue_slots[7].iss_uop.fu_code[7], io.fu_types[0][7]) \n node _fu_code_match_T_260 = and(issue_slots[7].iss_uop.fu_code[8], io.fu_types[0][8]) \n node _fu_code_match_T_261 = and(issue_slots[7].iss_uop.fu_code[9], io.fu_types[0][9]) \n node _fu_code_match_T_262 = or(_fu_code_match_T_252, _fu_code_match_T_253) \n node _fu_code_match_T_263 = or(_fu_code_match_T_262, _fu_code_match_T_254) \n node _fu_code_match_T_264 = or(_fu_code_match_T_263, _fu_code_match_T_255) \n node _fu_code_match_T_265 = or(_fu_code_match_T_264, _fu_code_match_T_256) \n node _fu_code_match_T_266 = or(_fu_code_match_T_265, _fu_code_match_T_257) \n node _fu_code_match_T_267 = or(_fu_code_match_T_266, _fu_code_match_T_258) \n node _fu_code_match_T_268 = or(_fu_code_match_T_267, _fu_code_match_T_259) \n node _fu_code_match_T_269 = or(_fu_code_match_T_268, _fu_code_match_T_260) \n node fu_code_match_14 = or(_fu_code_match_T_269, _fu_code_match_T_261) \n node can_allocate_14 = and(fu_code_match_14, UInt<1>(0h1)) \n node _T_478 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_479 = and(issue_slots[7].request, _T_478) \n node _T_480 = and(_T_479, can_allocate_14) \n node _T_481 = eq(_T_460, UInt<1>(0h0)) \n node _T_482 = and(_T_480, _T_481) \n when _T_482 : \n connect issue_slots[7].grant, UInt<1>(0h1) \n connect iss_uops[0].valid, UInt<1>(0h1) \n connect iss_uops[0].bits, issue_slots[7].iss_uop \n node _T_483 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_484 = and(issue_slots[7].request, _T_483) \n node _T_485 = and(_T_484, can_allocate_14) \n node _T_486 = or(_T_485, _T_460) \n node _T_487 = and(issue_slots[7].request, can_allocate_14) \n node _T_488 = eq(_T_460, UInt<1>(0h0)) \n node _T_489 = and(_T_487, _T_488) \n node _T_490 = or(_T_489, UInt<1>(0h0)) \n node _fu_code_match_T_270 = and(issue_slots[7].iss_uop.fu_code[0], io.fu_types[1][0]) \n node _fu_code_match_T_271 = and(issue_slots[7].iss_uop.fu_code[1], io.fu_types[1][1]) \n node _fu_code_match_T_272 = and(issue_slots[7].iss_uop.fu_code[2], io.fu_types[1][2]) \n node _fu_code_match_T_273 = and(issue_slots[7].iss_uop.fu_code[3], io.fu_types[1][3]) \n node _fu_code_match_T_274 = and(issue_slots[7].iss_uop.fu_code[4], io.fu_types[1][4]) \n node _fu_code_match_T_275 = and(issue_slots[7].iss_uop.fu_code[5], io.fu_types[1][5]) \n node _fu_code_match_T_276 = and(issue_slots[7].iss_uop.fu_code[6], io.fu_types[1][6]) \n node _fu_code_match_T_277 = and(issue_slots[7].iss_uop.fu_code[7], io.fu_types[1][7]) \n node _fu_code_match_T_278 = and(issue_slots[7].iss_uop.fu_code[8], io.fu_types[1][8]) \n node _fu_code_match_T_279 = and(issue_slots[7].iss_uop.fu_code[9], io.fu_types[1][9]) \n node _fu_code_match_T_280 = or(_fu_code_match_T_270, _fu_code_match_T_271) \n node _fu_code_match_T_281 = or(_fu_code_match_T_280, _fu_code_match_T_272) \n node _fu_code_match_T_282 = or(_fu_code_match_T_281, _fu_code_match_T_273) \n node _fu_code_match_T_283 = or(_fu_code_match_T_282, _fu_code_match_T_274) \n node _fu_code_match_T_284 = or(_fu_code_match_T_283, _fu_code_match_T_275) \n node _fu_code_match_T_285 = or(_fu_code_match_T_284, _fu_code_match_T_276) \n node _fu_code_match_T_286 = or(_fu_code_match_T_285, _fu_code_match_T_277) \n node _fu_code_match_T_287 = or(_fu_code_match_T_286, _fu_code_match_T_278) \n node fu_code_match_15 = or(_fu_code_match_T_287, _fu_code_match_T_279) \n node can_allocate_15 = and(fu_code_match_15, UInt<1>(0h1)) \n node _T_491 = eq(_T_490, UInt<1>(0h0)) \n node _T_492 = and(issue_slots[7].request, _T_491) \n node _T_493 = and(_T_492, can_allocate_15) \n node _T_494 = eq(_T_473, UInt<1>(0h0)) \n node _T_495 = and(_T_493, _T_494) \n when _T_495 : \n connect issue_slots[7].grant, UInt<1>(0h1) \n connect iss_uops[1].valid, UInt<1>(0h1) \n connect iss_uops[1].bits, issue_slots[7].iss_uop \n node _T_496 = eq(_T_490, UInt<1>(0h0)) \n node _T_497 = and(issue_slots[7].request, _T_496) \n node _T_498 = and(_T_497, can_allocate_15) \n node _T_499 = or(_T_498, _T_473) \n node _T_500 = and(issue_slots[7].request, can_allocate_15) \n node _T_501 = eq(_T_473, UInt<1>(0h0)) \n node _T_502 = and(_T_500, _T_501) \n node _T_503 = or(_T_502, _T_490) \n connect issue_slots[8].grant, UInt<1>(0h0) \n node _fu_code_match_T_288 = and(issue_slots[8].iss_uop.fu_code[0], io.fu_types[0][0]) \n node _fu_code_match_T_289 = and(issue_slots[8].iss_uop.fu_code[1], io.fu_types[0][1]) \n node _fu_code_match_T_290 = and(issue_slots[8].iss_uop.fu_code[2], io.fu_types[0][2]) \n node _fu_code_match_T_291 = and(issue_slots[8].iss_uop.fu_code[3], io.fu_types[0][3]) \n node _fu_code_match_T_292 = and(issue_slots[8].iss_uop.fu_code[4], io.fu_types[0][4]) \n node _fu_code_match_T_293 = and(issue_slots[8].iss_uop.fu_code[5], io.fu_types[0][5]) \n node _fu_code_match_T_294 = and(issue_slots[8].iss_uop.fu_code[6], io.fu_types[0][6]) \n node _fu_code_match_T_295 = and(issue_slots[8].iss_uop.fu_code[7], io.fu_types[0][7]) \n node _fu_code_match_T_296 = and(issue_slots[8].iss_uop.fu_code[8], io.fu_types[0][8]) \n node _fu_code_match_T_297 = and(issue_slots[8].iss_uop.fu_code[9], io.fu_types[0][9]) \n node _fu_code_match_T_298 = or(_fu_code_match_T_288, _fu_code_match_T_289) \n node _fu_code_match_T_299 = or(_fu_code_match_T_298, _fu_code_match_T_290) \n node _fu_code_match_T_300 = or(_fu_code_match_T_299, _fu_code_match_T_291) \n node _fu_code_match_T_301 = or(_fu_code_match_T_300, _fu_code_match_T_292) \n node _fu_code_match_T_302 = or(_fu_code_match_T_301, _fu_code_match_T_293) \n node _fu_code_match_T_303 = or(_fu_code_match_T_302, _fu_code_match_T_294) \n node _fu_code_match_T_304 = or(_fu_code_match_T_303, _fu_code_match_T_295) \n node _fu_code_match_T_305 = or(_fu_code_match_T_304, _fu_code_match_T_296) \n node fu_code_match_16 = or(_fu_code_match_T_305, _fu_code_match_T_297) \n node can_allocate_16 = and(fu_code_match_16, UInt<1>(0h1)) \n node _T_504 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_505 = and(issue_slots[8].request, _T_504) \n node _T_506 = and(_T_505, can_allocate_16) \n node _T_507 = eq(_T_486, UInt<1>(0h0)) \n node _T_508 = and(_T_506, _T_507) \n when _T_508 : \n connect issue_slots[8].grant, UInt<1>(0h1) \n connect iss_uops[0].valid, UInt<1>(0h1) \n connect iss_uops[0].bits, issue_slots[8].iss_uop \n node _T_509 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_510 = and(issue_slots[8].request, _T_509) \n node _T_511 = and(_T_510, can_allocate_16) \n node _T_512 = or(_T_511, _T_486) \n node _T_513 = and(issue_slots[8].request, can_allocate_16) \n node _T_514 = eq(_T_486, UInt<1>(0h0)) \n node _T_515 = and(_T_513, _T_514) \n node _T_516 = or(_T_515, UInt<1>(0h0)) \n node _fu_code_match_T_306 = and(issue_slots[8].iss_uop.fu_code[0], io.fu_types[1][0]) \n node _fu_code_match_T_307 = and(issue_slots[8].iss_uop.fu_code[1], io.fu_types[1][1]) \n node _fu_code_match_T_308 = and(issue_slots[8].iss_uop.fu_code[2], io.fu_types[1][2]) \n node _fu_code_match_T_309 = and(issue_slots[8].iss_uop.fu_code[3], io.fu_types[1][3]) \n node _fu_code_match_T_310 = and(issue_slots[8].iss_uop.fu_code[4], io.fu_types[1][4]) \n node _fu_code_match_T_311 = and(issue_slots[8].iss_uop.fu_code[5], io.fu_types[1][5]) \n node _fu_code_match_T_312 = and(issue_slots[8].iss_uop.fu_code[6], io.fu_types[1][6]) \n node _fu_code_match_T_313 = and(issue_slots[8].iss_uop.fu_code[7], io.fu_types[1][7]) \n node _fu_code_match_T_314 = and(issue_slots[8].iss_uop.fu_code[8], io.fu_types[1][8]) \n node _fu_code_match_T_315 = and(issue_slots[8].iss_uop.fu_code[9], io.fu_types[1][9]) \n node _fu_code_match_T_316 = or(_fu_code_match_T_306, _fu_code_match_T_307) \n node _fu_code_match_T_317 = or(_fu_code_match_T_316, _fu_code_match_T_308) \n node _fu_code_match_T_318 = or(_fu_code_match_T_317, _fu_code_match_T_309) \n node _fu_code_match_T_319 = or(_fu_code_match_T_318, _fu_code_match_T_310) \n node _fu_code_match_T_320 = or(_fu_code_match_T_319, _fu_code_match_T_311) \n node _fu_code_match_T_321 = or(_fu_code_match_T_320, _fu_code_match_T_312) \n node _fu_code_match_T_322 = or(_fu_code_match_T_321, _fu_code_match_T_313) \n node _fu_code_match_T_323 = or(_fu_code_match_T_322, _fu_code_match_T_314) \n node fu_code_match_17 = or(_fu_code_match_T_323, _fu_code_match_T_315) \n node can_allocate_17 = and(fu_code_match_17, UInt<1>(0h1)) \n node _T_517 = eq(_T_516, UInt<1>(0h0)) \n node _T_518 = and(issue_slots[8].request, _T_517) \n node _T_519 = and(_T_518, can_allocate_17) \n node _T_520 = eq(_T_499, UInt<1>(0h0)) \n node _T_521 = and(_T_519, _T_520) \n when _T_521 : \n connect issue_slots[8].grant, UInt<1>(0h1) \n connect iss_uops[1].valid, UInt<1>(0h1) \n connect iss_uops[1].bits, issue_slots[8].iss_uop \n node _T_522 = eq(_T_516, UInt<1>(0h0)) \n node _T_523 = and(issue_slots[8].request, _T_522) \n node _T_524 = and(_T_523, can_allocate_17) \n node _T_525 = or(_T_524, _T_499) \n node _T_526 = and(issue_slots[8].request, can_allocate_17) \n node _T_527 = eq(_T_499, UInt<1>(0h0)) \n node _T_528 = and(_T_526, _T_527) \n node _T_529 = or(_T_528, _T_516) \n connect issue_slots[9].grant, UInt<1>(0h0) \n node _fu_code_match_T_324 = and(issue_slots[9].iss_uop.fu_code[0], io.fu_types[0][0]) \n node _fu_code_match_T_325 = and(issue_slots[9].iss_uop.fu_code[1], io.fu_types[0][1]) \n node _fu_code_match_T_326 = and(issue_slots[9].iss_uop.fu_code[2], io.fu_types[0][2]) \n node _fu_code_match_T_327 = and(issue_slots[9].iss_uop.fu_code[3], io.fu_types[0][3]) \n node _fu_code_match_T_328 = and(issue_slots[9].iss_uop.fu_code[4], io.fu_types[0][4]) \n node _fu_code_match_T_329 = and(issue_slots[9].iss_uop.fu_code[5], io.fu_types[0][5]) \n node _fu_code_match_T_330 = and(issue_slots[9].iss_uop.fu_code[6], io.fu_types[0][6]) \n node _fu_code_match_T_331 = and(issue_slots[9].iss_uop.fu_code[7], io.fu_types[0][7]) \n node _fu_code_match_T_332 = and(issue_slots[9].iss_uop.fu_code[8], io.fu_types[0][8]) \n node _fu_code_match_T_333 = and(issue_slots[9].iss_uop.fu_code[9], io.fu_types[0][9]) \n node _fu_code_match_T_334 = or(_fu_code_match_T_324, _fu_code_match_T_325) \n node _fu_code_match_T_335 = or(_fu_code_match_T_334, _fu_code_match_T_326) \n node _fu_code_match_T_336 = or(_fu_code_match_T_335, _fu_code_match_T_327) \n node _fu_code_match_T_337 = or(_fu_code_match_T_336, _fu_code_match_T_328) \n node _fu_code_match_T_338 = or(_fu_code_match_T_337, _fu_code_match_T_329) \n node _fu_code_match_T_339 = or(_fu_code_match_T_338, _fu_code_match_T_330) \n node _fu_code_match_T_340 = or(_fu_code_match_T_339, _fu_code_match_T_331) \n node _fu_code_match_T_341 = or(_fu_code_match_T_340, _fu_code_match_T_332) \n node fu_code_match_18 = or(_fu_code_match_T_341, _fu_code_match_T_333) \n node can_allocate_18 = and(fu_code_match_18, UInt<1>(0h1)) \n node _T_530 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_531 = and(issue_slots[9].request, _T_530) \n node _T_532 = and(_T_531, can_allocate_18) \n node _T_533 = eq(_T_512, UInt<1>(0h0)) \n node _T_534 = and(_T_532, _T_533) \n when _T_534 : \n connect issue_slots[9].grant, UInt<1>(0h1) \n connect iss_uops[0].valid, UInt<1>(0h1) \n connect iss_uops[0].bits, issue_slots[9].iss_uop \n node _T_535 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_536 = and(issue_slots[9].request, _T_535) \n node _T_537 = and(_T_536, can_allocate_18) \n node _T_538 = or(_T_537, _T_512) \n node _T_539 = and(issue_slots[9].request, can_allocate_18) \n node _T_540 = eq(_T_512, UInt<1>(0h0)) \n node _T_541 = and(_T_539, _T_540) \n node _T_542 = or(_T_541, UInt<1>(0h0)) \n node _fu_code_match_T_342 = and(issue_slots[9].iss_uop.fu_code[0], io.fu_types[1][0]) \n node _fu_code_match_T_343 = and(issue_slots[9].iss_uop.fu_code[1], io.fu_types[1][1]) \n node _fu_code_match_T_344 = and(issue_slots[9].iss_uop.fu_code[2], io.fu_types[1][2]) \n node _fu_code_match_T_345 = and(issue_slots[9].iss_uop.fu_code[3], io.fu_types[1][3]) \n node _fu_code_match_T_346 = and(issue_slots[9].iss_uop.fu_code[4], io.fu_types[1][4]) \n node _fu_code_match_T_347 = and(issue_slots[9].iss_uop.fu_code[5], io.fu_types[1][5]) \n node _fu_code_match_T_348 = and(issue_slots[9].iss_uop.fu_code[6], io.fu_types[1][6]) \n node _fu_code_match_T_349 = and(issue_slots[9].iss_uop.fu_code[7], io.fu_types[1][7]) \n node _fu_code_match_T_350 = and(issue_slots[9].iss_uop.fu_code[8], io.fu_types[1][8]) \n node _fu_code_match_T_351 = and(issue_slots[9].iss_uop.fu_code[9], io.fu_types[1][9]) \n node _fu_code_match_T_352 = or(_fu_code_match_T_342, _fu_code_match_T_343) \n node _fu_code_match_T_353 = or(_fu_code_match_T_352, _fu_code_match_T_344) \n node _fu_code_match_T_354 = or(_fu_code_match_T_353, _fu_code_match_T_345) \n node _fu_code_match_T_355 = or(_fu_code_match_T_354, _fu_code_match_T_346) \n node _fu_code_match_T_356 = or(_fu_code_match_T_355, _fu_code_match_T_347) \n node _fu_code_match_T_357 = or(_fu_code_match_T_356, _fu_code_match_T_348) \n node _fu_code_match_T_358 = or(_fu_code_match_T_357, _fu_code_match_T_349) \n node _fu_code_match_T_359 = or(_fu_code_match_T_358, _fu_code_match_T_350) \n node fu_code_match_19 = or(_fu_code_match_T_359, _fu_code_match_T_351) \n node can_allocate_19 = and(fu_code_match_19, UInt<1>(0h1)) \n node _T_543 = eq(_T_542, UInt<1>(0h0)) \n node _T_544 = and(issue_slots[9].request, _T_543) \n node _T_545 = and(_T_544, can_allocate_19) \n node _T_546 = eq(_T_525, UInt<1>(0h0)) \n node _T_547 = and(_T_545, _T_546) \n when _T_547 : \n connect issue_slots[9].grant, UInt<1>(0h1) \n connect iss_uops[1].valid, UInt<1>(0h1) \n connect iss_uops[1].bits, issue_slots[9].iss_uop \n node _T_548 = eq(_T_542, UInt<1>(0h0)) \n node _T_549 = and(issue_slots[9].request, _T_548) \n node _T_550 = and(_T_549, can_allocate_19) \n node _T_551 = or(_T_550, _T_525) \n node _T_552 = and(issue_slots[9].request, can_allocate_19) \n node _T_553 = eq(_T_525, UInt<1>(0h0)) \n node _T_554 = and(_T_552, _T_553) \n node _T_555 = or(_T_554, _T_542) \n connect issue_slots[10].grant, UInt<1>(0h0) \n node _fu_code_match_T_360 = and(issue_slots[10].iss_uop.fu_code[0], io.fu_types[0][0]) \n node _fu_code_match_T_361 = and(issue_slots[10].iss_uop.fu_code[1], io.fu_types[0][1]) \n node _fu_code_match_T_362 = and(issue_slots[10].iss_uop.fu_code[2], io.fu_types[0][2]) \n node _fu_code_match_T_363 = and(issue_slots[10].iss_uop.fu_code[3], io.fu_types[0][3]) \n node _fu_code_match_T_364 = and(issue_slots[10].iss_uop.fu_code[4], io.fu_types[0][4]) \n node _fu_code_match_T_365 = and(issue_slots[10].iss_uop.fu_code[5], io.fu_types[0][5]) \n node _fu_code_match_T_366 = and(issue_slots[10].iss_uop.fu_code[6], io.fu_types[0][6]) \n node _fu_code_match_T_367 = and(issue_slots[10].iss_uop.fu_code[7], io.fu_types[0][7]) \n node _fu_code_match_T_368 = and(issue_slots[10].iss_uop.fu_code[8], io.fu_types[0][8]) \n node _fu_code_match_T_369 = and(issue_slots[10].iss_uop.fu_code[9], io.fu_types[0][9]) \n node _fu_code_match_T_370 = or(_fu_code_match_T_360, _fu_code_match_T_361) \n node _fu_code_match_T_371 = or(_fu_code_match_T_370, _fu_code_match_T_362) \n node _fu_code_match_T_372 = or(_fu_code_match_T_371, _fu_code_match_T_363) \n node _fu_code_match_T_373 = or(_fu_code_match_T_372, _fu_code_match_T_364) \n node _fu_code_match_T_374 = or(_fu_code_match_T_373, _fu_code_match_T_365) \n node _fu_code_match_T_375 = or(_fu_code_match_T_374, _fu_code_match_T_366) \n node _fu_code_match_T_376 = or(_fu_code_match_T_375, _fu_code_match_T_367) \n node _fu_code_match_T_377 = or(_fu_code_match_T_376, _fu_code_match_T_368) \n node fu_code_match_20 = or(_fu_code_match_T_377, _fu_code_match_T_369) \n node can_allocate_20 = and(fu_code_match_20, UInt<1>(0h1)) \n node _T_556 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_557 = and(issue_slots[10].request, _T_556) \n node _T_558 = and(_T_557, can_allocate_20) \n node _T_559 = eq(_T_538, UInt<1>(0h0)) \n node _T_560 = and(_T_558, _T_559) \n when _T_560 : \n connect issue_slots[10].grant, UInt<1>(0h1) \n connect iss_uops[0].valid, UInt<1>(0h1) \n connect iss_uops[0].bits, issue_slots[10].iss_uop \n node _T_561 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_562 = and(issue_slots[10].request, _T_561) \n node _T_563 = and(_T_562, can_allocate_20) \n node _T_564 = or(_T_563, _T_538) \n node _T_565 = and(issue_slots[10].request, can_allocate_20) \n node _T_566 = eq(_T_538, UInt<1>(0h0)) \n node _T_567 = and(_T_565, _T_566) \n node _T_568 = or(_T_567, UInt<1>(0h0)) \n node _fu_code_match_T_378 = and(issue_slots[10].iss_uop.fu_code[0], io.fu_types[1][0]) \n node _fu_code_match_T_379 = and(issue_slots[10].iss_uop.fu_code[1], io.fu_types[1][1]) \n node _fu_code_match_T_380 = and(issue_slots[10].iss_uop.fu_code[2], io.fu_types[1][2]) \n node _fu_code_match_T_381 = and(issue_slots[10].iss_uop.fu_code[3], io.fu_types[1][3]) \n node _fu_code_match_T_382 = and(issue_slots[10].iss_uop.fu_code[4], io.fu_types[1][4]) \n node _fu_code_match_T_383 = and(issue_slots[10].iss_uop.fu_code[5], io.fu_types[1][5]) \n node _fu_code_match_T_384 = and(issue_slots[10].iss_uop.fu_code[6], io.fu_types[1][6]) \n node _fu_code_match_T_385 = and(issue_slots[10].iss_uop.fu_code[7], io.fu_types[1][7]) \n node _fu_code_match_T_386 = and(issue_slots[10].iss_uop.fu_code[8], io.fu_types[1][8]) \n node _fu_code_match_T_387 = and(issue_slots[10].iss_uop.fu_code[9], io.fu_types[1][9]) \n node _fu_code_match_T_388 = or(_fu_code_match_T_378, _fu_code_match_T_379) \n node _fu_code_match_T_389 = or(_fu_code_match_T_388, _fu_code_match_T_380) \n node _fu_code_match_T_390 = or(_fu_code_match_T_389, _fu_code_match_T_381) \n node _fu_code_match_T_391 = or(_fu_code_match_T_390, _fu_code_match_T_382) \n node _fu_code_match_T_392 = or(_fu_code_match_T_391, _fu_code_match_T_383) \n node _fu_code_match_T_393 = or(_fu_code_match_T_392, _fu_code_match_T_384) \n node _fu_code_match_T_394 = or(_fu_code_match_T_393, _fu_code_match_T_385) \n node _fu_code_match_T_395 = or(_fu_code_match_T_394, _fu_code_match_T_386) \n node fu_code_match_21 = or(_fu_code_match_T_395, _fu_code_match_T_387) \n node can_allocate_21 = and(fu_code_match_21, UInt<1>(0h1)) \n node _T_569 = eq(_T_568, UInt<1>(0h0)) \n node _T_570 = and(issue_slots[10].request, _T_569) \n node _T_571 = and(_T_570, can_allocate_21) \n node _T_572 = eq(_T_551, UInt<1>(0h0)) \n node _T_573 = and(_T_571, _T_572) \n when _T_573 : \n connect issue_slots[10].grant, UInt<1>(0h1) \n connect iss_uops[1].valid, UInt<1>(0h1) \n connect iss_uops[1].bits, issue_slots[10].iss_uop \n node _T_574 = eq(_T_568, UInt<1>(0h0)) \n node _T_575 = and(issue_slots[10].request, _T_574) \n node _T_576 = and(_T_575, can_allocate_21) \n node _T_577 = or(_T_576, _T_551) \n node _T_578 = and(issue_slots[10].request, can_allocate_21) \n node _T_579 = eq(_T_551, UInt<1>(0h0)) \n node _T_580 = and(_T_578, _T_579) \n node _T_581 = or(_T_580, _T_568) \n connect issue_slots[11].grant, UInt<1>(0h0) \n node _fu_code_match_T_396 = and(issue_slots[11].iss_uop.fu_code[0], io.fu_types[0][0]) \n node _fu_code_match_T_397 = and(issue_slots[11].iss_uop.fu_code[1], io.fu_types[0][1]) \n node _fu_code_match_T_398 = and(issue_slots[11].iss_uop.fu_code[2], io.fu_types[0][2]) \n node _fu_code_match_T_399 = and(issue_slots[11].iss_uop.fu_code[3], io.fu_types[0][3]) \n node _fu_code_match_T_400 = and(issue_slots[11].iss_uop.fu_code[4], io.fu_types[0][4]) \n node _fu_code_match_T_401 = and(issue_slots[11].iss_uop.fu_code[5], io.fu_types[0][5]) \n node _fu_code_match_T_402 = and(issue_slots[11].iss_uop.fu_code[6], io.fu_types[0][6]) \n node _fu_code_match_T_403 = and(issue_slots[11].iss_uop.fu_code[7], io.fu_types[0][7]) \n node _fu_code_match_T_404 = and(issue_slots[11].iss_uop.fu_code[8], io.fu_types[0][8]) \n node _fu_code_match_T_405 = and(issue_slots[11].iss_uop.fu_code[9], io.fu_types[0][9]) \n node _fu_code_match_T_406 = or(_fu_code_match_T_396, _fu_code_match_T_397) \n node _fu_code_match_T_407 = or(_fu_code_match_T_406, _fu_code_match_T_398) \n node _fu_code_match_T_408 = or(_fu_code_match_T_407, _fu_code_match_T_399) \n node _fu_code_match_T_409 = or(_fu_code_match_T_408, _fu_code_match_T_400) \n node _fu_code_match_T_410 = or(_fu_code_match_T_409, _fu_code_match_T_401) \n node _fu_code_match_T_411 = or(_fu_code_match_T_410, _fu_code_match_T_402) \n node _fu_code_match_T_412 = or(_fu_code_match_T_411, _fu_code_match_T_403) \n node _fu_code_match_T_413 = or(_fu_code_match_T_412, _fu_code_match_T_404) \n node fu_code_match_22 = or(_fu_code_match_T_413, _fu_code_match_T_405) \n node can_allocate_22 = and(fu_code_match_22, UInt<1>(0h1)) \n node _T_582 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_583 = and(issue_slots[11].request, _T_582) \n node _T_584 = and(_T_583, can_allocate_22) \n node _T_585 = eq(_T_564, UInt<1>(0h0)) \n node _T_586 = and(_T_584, _T_585) \n when _T_586 : \n connect issue_slots[11].grant, UInt<1>(0h1) \n connect iss_uops[0].valid, UInt<1>(0h1) \n connect iss_uops[0].bits, issue_slots[11].iss_uop \n node _T_587 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_588 = and(issue_slots[11].request, _T_587) \n node _T_589 = and(_T_588, can_allocate_22) \n node _T_590 = or(_T_589, _T_564) \n node _T_591 = and(issue_slots[11].request, can_allocate_22) \n node _T_592 = eq(_T_564, UInt<1>(0h0)) \n node _T_593 = and(_T_591, _T_592) \n node _T_594 = or(_T_593, UInt<1>(0h0)) \n node _fu_code_match_T_414 = and(issue_slots[11].iss_uop.fu_code[0], io.fu_types[1][0]) \n node _fu_code_match_T_415 = and(issue_slots[11].iss_uop.fu_code[1], io.fu_types[1][1]) \n node _fu_code_match_T_416 = and(issue_slots[11].iss_uop.fu_code[2], io.fu_types[1][2]) \n node _fu_code_match_T_417 = and(issue_slots[11].iss_uop.fu_code[3], io.fu_types[1][3]) \n node _fu_code_match_T_418 = and(issue_slots[11].iss_uop.fu_code[4], io.fu_types[1][4]) \n node _fu_code_match_T_419 = and(issue_slots[11].iss_uop.fu_code[5], io.fu_types[1][5]) \n node _fu_code_match_T_420 = and(issue_slots[11].iss_uop.fu_code[6], io.fu_types[1][6]) \n node _fu_code_match_T_421 = and(issue_slots[11].iss_uop.fu_code[7], io.fu_types[1][7]) \n node _fu_code_match_T_422 = and(issue_slots[11].iss_uop.fu_code[8], io.fu_types[1][8]) \n node _fu_code_match_T_423 = and(issue_slots[11].iss_uop.fu_code[9], io.fu_types[1][9]) \n node _fu_code_match_T_424 = or(_fu_code_match_T_414, _fu_code_match_T_415) \n node _fu_code_match_T_425 = or(_fu_code_match_T_424, _fu_code_match_T_416) \n node _fu_code_match_T_426 = or(_fu_code_match_T_425, _fu_code_match_T_417) \n node _fu_code_match_T_427 = or(_fu_code_match_T_426, _fu_code_match_T_418) \n node _fu_code_match_T_428 = or(_fu_code_match_T_427, _fu_code_match_T_419) \n node _fu_code_match_T_429 = or(_fu_code_match_T_428, _fu_code_match_T_420) \n node _fu_code_match_T_430 = or(_fu_code_match_T_429, _fu_code_match_T_421) \n node _fu_code_match_T_431 = or(_fu_code_match_T_430, _fu_code_match_T_422) \n node fu_code_match_23 = or(_fu_code_match_T_431, _fu_code_match_T_423) \n node can_allocate_23 = and(fu_code_match_23, UInt<1>(0h1)) \n node _T_595 = eq(_T_594, UInt<1>(0h0)) \n node _T_596 = and(issue_slots[11].request, _T_595) \n node _T_597 = and(_T_596, can_allocate_23) \n node _T_598 = eq(_T_577, UInt<1>(0h0)) \n node _T_599 = and(_T_597, _T_598) \n when _T_599 : \n connect issue_slots[11].grant, UInt<1>(0h1) \n connect iss_uops[1].valid, UInt<1>(0h1) \n connect iss_uops[1].bits, issue_slots[11].iss_uop \n node _T_600 = eq(_T_594, UInt<1>(0h0)) \n node _T_601 = and(issue_slots[11].request, _T_600) \n node _T_602 = and(_T_601, can_allocate_23) \n node _T_603 = or(_T_602, _T_577) \n node _T_604 = and(issue_slots[11].request, can_allocate_23) \n node _T_605 = eq(_T_577, UInt<1>(0h0)) \n node _T_606 = and(_T_604, _T_605) \n node _T_607 = or(_T_606, _T_594) \n connect issue_slots[12].grant, UInt<1>(0h0) \n node _fu_code_match_T_432 = and(issue_slots[12].iss_uop.fu_code[0], io.fu_types[0][0]) \n node _fu_code_match_T_433 = and(issue_slots[12].iss_uop.fu_code[1], io.fu_types[0][1]) \n node _fu_code_match_T_434 = and(issue_slots[12].iss_uop.fu_code[2], io.fu_types[0][2]) \n node _fu_code_match_T_435 = and(issue_slots[12].iss_uop.fu_code[3], io.fu_types[0][3]) \n node _fu_code_match_T_436 = and(issue_slots[12].iss_uop.fu_code[4], io.fu_types[0][4]) \n node _fu_code_match_T_437 = and(issue_slots[12].iss_uop.fu_code[5], io.fu_types[0][5]) \n node _fu_code_match_T_438 = and(issue_slots[12].iss_uop.fu_code[6], io.fu_types[0][6]) \n node _fu_code_match_T_439 = and(issue_slots[12].iss_uop.fu_code[7], io.fu_types[0][7]) \n node _fu_code_match_T_440 = and(issue_slots[12].iss_uop.fu_code[8], io.fu_types[0][8]) \n node _fu_code_match_T_441 = and(issue_slots[12].iss_uop.fu_code[9], io.fu_types[0][9]) \n node _fu_code_match_T_442 = or(_fu_code_match_T_432, _fu_code_match_T_433) \n node _fu_code_match_T_443 = or(_fu_code_match_T_442, _fu_code_match_T_434) \n node _fu_code_match_T_444 = or(_fu_code_match_T_443, _fu_code_match_T_435) \n node _fu_code_match_T_445 = or(_fu_code_match_T_444, _fu_code_match_T_436) \n node _fu_code_match_T_446 = or(_fu_code_match_T_445, _fu_code_match_T_437) \n node _fu_code_match_T_447 = or(_fu_code_match_T_446, _fu_code_match_T_438) \n node _fu_code_match_T_448 = or(_fu_code_match_T_447, _fu_code_match_T_439) \n node _fu_code_match_T_449 = or(_fu_code_match_T_448, _fu_code_match_T_440) \n node fu_code_match_24 = or(_fu_code_match_T_449, _fu_code_match_T_441) \n node can_allocate_24 = and(fu_code_match_24, UInt<1>(0h1)) \n node _T_608 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_609 = and(issue_slots[12].request, _T_608) \n node _T_610 = and(_T_609, can_allocate_24) \n node _T_611 = eq(_T_590, UInt<1>(0h0)) \n node _T_612 = and(_T_610, _T_611) \n when _T_612 : \n connect issue_slots[12].grant, UInt<1>(0h1) \n connect iss_uops[0].valid, UInt<1>(0h1) \n connect iss_uops[0].bits, issue_slots[12].iss_uop \n node _T_613 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_614 = and(issue_slots[12].request, _T_613) \n node _T_615 = and(_T_614, can_allocate_24) \n node _T_616 = or(_T_615, _T_590) \n node _T_617 = and(issue_slots[12].request, can_allocate_24) \n node _T_618 = eq(_T_590, UInt<1>(0h0)) \n node _T_619 = and(_T_617, _T_618) \n node _T_620 = or(_T_619, UInt<1>(0h0)) \n node _fu_code_match_T_450 = and(issue_slots[12].iss_uop.fu_code[0], io.fu_types[1][0]) \n node _fu_code_match_T_451 = and(issue_slots[12].iss_uop.fu_code[1], io.fu_types[1][1]) \n node _fu_code_match_T_452 = and(issue_slots[12].iss_uop.fu_code[2], io.fu_types[1][2]) \n node _fu_code_match_T_453 = and(issue_slots[12].iss_uop.fu_code[3], io.fu_types[1][3]) \n node _fu_code_match_T_454 = and(issue_slots[12].iss_uop.fu_code[4], io.fu_types[1][4]) \n node _fu_code_match_T_455 = and(issue_slots[12].iss_uop.fu_code[5], io.fu_types[1][5]) \n node _fu_code_match_T_456 = and(issue_slots[12].iss_uop.fu_code[6], io.fu_types[1][6]) \n node _fu_code_match_T_457 = and(issue_slots[12].iss_uop.fu_code[7], io.fu_types[1][7]) \n node _fu_code_match_T_458 = and(issue_slots[12].iss_uop.fu_code[8], io.fu_types[1][8]) \n node _fu_code_match_T_459 = and(issue_slots[12].iss_uop.fu_code[9], io.fu_types[1][9]) \n node _fu_code_match_T_460 = or(_fu_code_match_T_450, _fu_code_match_T_451) \n node _fu_code_match_T_461 = or(_fu_code_match_T_460, _fu_code_match_T_452) \n node _fu_code_match_T_462 = or(_fu_code_match_T_461, _fu_code_match_T_453) \n node _fu_code_match_T_463 = or(_fu_code_match_T_462, _fu_code_match_T_454) \n node _fu_code_match_T_464 = or(_fu_code_match_T_463, _fu_code_match_T_455) \n node _fu_code_match_T_465 = or(_fu_code_match_T_464, _fu_code_match_T_456) \n node _fu_code_match_T_466 = or(_fu_code_match_T_465, _fu_code_match_T_457) \n node _fu_code_match_T_467 = or(_fu_code_match_T_466, _fu_code_match_T_458) \n node fu_code_match_25 = or(_fu_code_match_T_467, _fu_code_match_T_459) \n node can_allocate_25 = and(fu_code_match_25, UInt<1>(0h1)) \n node _T_621 = eq(_T_620, UInt<1>(0h0)) \n node _T_622 = and(issue_slots[12].request, _T_621) \n node _T_623 = and(_T_622, can_allocate_25) \n node _T_624 = eq(_T_603, UInt<1>(0h0)) \n node _T_625 = and(_T_623, _T_624) \n when _T_625 : \n connect issue_slots[12].grant, UInt<1>(0h1) \n connect iss_uops[1].valid, UInt<1>(0h1) \n connect iss_uops[1].bits, issue_slots[12].iss_uop \n node _T_626 = eq(_T_620, UInt<1>(0h0)) \n node _T_627 = and(issue_slots[12].request, _T_626) \n node _T_628 = and(_T_627, can_allocate_25) \n node _T_629 = or(_T_628, _T_603) \n node _T_630 = and(issue_slots[12].request, can_allocate_25) \n node _T_631 = eq(_T_603, UInt<1>(0h0)) \n node _T_632 = and(_T_630, _T_631) \n node _T_633 = or(_T_632, _T_620) \n connect issue_slots[13].grant, UInt<1>(0h0) \n node _fu_code_match_T_468 = and(issue_slots[13].iss_uop.fu_code[0], io.fu_types[0][0]) \n node _fu_code_match_T_469 = and(issue_slots[13].iss_uop.fu_code[1], io.fu_types[0][1]) \n node _fu_code_match_T_470 = and(issue_slots[13].iss_uop.fu_code[2], io.fu_types[0][2]) \n node _fu_code_match_T_471 = and(issue_slots[13].iss_uop.fu_code[3], io.fu_types[0][3]) \n node _fu_code_match_T_472 = and(issue_slots[13].iss_uop.fu_code[4], io.fu_types[0][4]) \n node _fu_code_match_T_473 = and(issue_slots[13].iss_uop.fu_code[5], io.fu_types[0][5]) \n node _fu_code_match_T_474 = and(issue_slots[13].iss_uop.fu_code[6], io.fu_types[0][6]) \n node _fu_code_match_T_475 = and(issue_slots[13].iss_uop.fu_code[7], io.fu_types[0][7]) \n node _fu_code_match_T_476 = and(issue_slots[13].iss_uop.fu_code[8], io.fu_types[0][8]) \n node _fu_code_match_T_477 = and(issue_slots[13].iss_uop.fu_code[9], io.fu_types[0][9]) \n node _fu_code_match_T_478 = or(_fu_code_match_T_468, _fu_code_match_T_469) \n node _fu_code_match_T_479 = or(_fu_code_match_T_478, _fu_code_match_T_470) \n node _fu_code_match_T_480 = or(_fu_code_match_T_479, _fu_code_match_T_471) \n node _fu_code_match_T_481 = or(_fu_code_match_T_480, _fu_code_match_T_472) \n node _fu_code_match_T_482 = or(_fu_code_match_T_481, _fu_code_match_T_473) \n node _fu_code_match_T_483 = or(_fu_code_match_T_482, _fu_code_match_T_474) \n node _fu_code_match_T_484 = or(_fu_code_match_T_483, _fu_code_match_T_475) \n node _fu_code_match_T_485 = or(_fu_code_match_T_484, _fu_code_match_T_476) \n node fu_code_match_26 = or(_fu_code_match_T_485, _fu_code_match_T_477) \n node can_allocate_26 = and(fu_code_match_26, UInt<1>(0h1)) \n node _T_634 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_635 = and(issue_slots[13].request, _T_634) \n node _T_636 = and(_T_635, can_allocate_26) \n node _T_637 = eq(_T_616, UInt<1>(0h0)) \n node _T_638 = and(_T_636, _T_637) \n when _T_638 : \n connect issue_slots[13].grant, UInt<1>(0h1) \n connect iss_uops[0].valid, UInt<1>(0h1) \n connect iss_uops[0].bits, issue_slots[13].iss_uop \n node _T_639 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_640 = and(issue_slots[13].request, _T_639) \n node _T_641 = and(_T_640, can_allocate_26) \n node _T_642 = or(_T_641, _T_616) \n node _T_643 = and(issue_slots[13].request, can_allocate_26) \n node _T_644 = eq(_T_616, UInt<1>(0h0)) \n node _T_645 = and(_T_643, _T_644) \n node _T_646 = or(_T_645, UInt<1>(0h0)) \n node _fu_code_match_T_486 = and(issue_slots[13].iss_uop.fu_code[0], io.fu_types[1][0]) \n node _fu_code_match_T_487 = and(issue_slots[13].iss_uop.fu_code[1], io.fu_types[1][1]) \n node _fu_code_match_T_488 = and(issue_slots[13].iss_uop.fu_code[2], io.fu_types[1][2]) \n node _fu_code_match_T_489 = and(issue_slots[13].iss_uop.fu_code[3], io.fu_types[1][3]) \n node _fu_code_match_T_490 = and(issue_slots[13].iss_uop.fu_code[4], io.fu_types[1][4]) \n node _fu_code_match_T_491 = and(issue_slots[13].iss_uop.fu_code[5], io.fu_types[1][5]) \n node _fu_code_match_T_492 = and(issue_slots[13].iss_uop.fu_code[6], io.fu_types[1][6]) \n node _fu_code_match_T_493 = and(issue_slots[13].iss_uop.fu_code[7], io.fu_types[1][7]) \n node _fu_code_match_T_494 = and(issue_slots[13].iss_uop.fu_code[8], io.fu_types[1][8]) \n node _fu_code_match_T_495 = and(issue_slots[13].iss_uop.fu_code[9], io.fu_types[1][9]) \n node _fu_code_match_T_496 = or(_fu_code_match_T_486, _fu_code_match_T_487) \n node _fu_code_match_T_497 = or(_fu_code_match_T_496, _fu_code_match_T_488) \n node _fu_code_match_T_498 = or(_fu_code_match_T_497, _fu_code_match_T_489) \n node _fu_code_match_T_499 = or(_fu_code_match_T_498, _fu_code_match_T_490) \n node _fu_code_match_T_500 = or(_fu_code_match_T_499, _fu_code_match_T_491) \n node _fu_code_match_T_501 = or(_fu_code_match_T_500, _fu_code_match_T_492) \n node _fu_code_match_T_502 = or(_fu_code_match_T_501, _fu_code_match_T_493) \n node _fu_code_match_T_503 = or(_fu_code_match_T_502, _fu_code_match_T_494) \n node fu_code_match_27 = or(_fu_code_match_T_503, _fu_code_match_T_495) \n node can_allocate_27 = and(fu_code_match_27, UInt<1>(0h1)) \n node _T_647 = eq(_T_646, UInt<1>(0h0)) \n node _T_648 = and(issue_slots[13].request, _T_647) \n node _T_649 = and(_T_648, can_allocate_27) \n node _T_650 = eq(_T_629, UInt<1>(0h0)) \n node _T_651 = and(_T_649, _T_650) \n when _T_651 : \n connect issue_slots[13].grant, UInt<1>(0h1) \n connect iss_uops[1].valid, UInt<1>(0h1) \n connect iss_uops[1].bits, issue_slots[13].iss_uop \n node _T_652 = eq(_T_646, UInt<1>(0h0)) \n node _T_653 = and(issue_slots[13].request, _T_652) \n node _T_654 = and(_T_653, can_allocate_27) \n node _T_655 = or(_T_654, _T_629) \n node _T_656 = and(issue_slots[13].request, can_allocate_27) \n node _T_657 = eq(_T_629, UInt<1>(0h0)) \n node _T_658 = and(_T_656, _T_657) \n node _T_659 = or(_T_658, _T_646) \n connect issue_slots[14].grant, UInt<1>(0h0) \n node _fu_code_match_T_504 = and(issue_slots[14].iss_uop.fu_code[0], io.fu_types[0][0]) \n node _fu_code_match_T_505 = and(issue_slots[14].iss_uop.fu_code[1], io.fu_types[0][1]) \n node _fu_code_match_T_506 = and(issue_slots[14].iss_uop.fu_code[2], io.fu_types[0][2]) \n node _fu_code_match_T_507 = and(issue_slots[14].iss_uop.fu_code[3], io.fu_types[0][3]) \n node _fu_code_match_T_508 = and(issue_slots[14].iss_uop.fu_code[4], io.fu_types[0][4]) \n node _fu_code_match_T_509 = and(issue_slots[14].iss_uop.fu_code[5], io.fu_types[0][5]) \n node _fu_code_match_T_510 = and(issue_slots[14].iss_uop.fu_code[6], io.fu_types[0][6]) \n node _fu_code_match_T_511 = and(issue_slots[14].iss_uop.fu_code[7], io.fu_types[0][7]) \n node _fu_code_match_T_512 = and(issue_slots[14].iss_uop.fu_code[8], io.fu_types[0][8]) \n node _fu_code_match_T_513 = and(issue_slots[14].iss_uop.fu_code[9], io.fu_types[0][9]) \n node _fu_code_match_T_514 = or(_fu_code_match_T_504, _fu_code_match_T_505) \n node _fu_code_match_T_515 = or(_fu_code_match_T_514, _fu_code_match_T_506) \n node _fu_code_match_T_516 = or(_fu_code_match_T_515, _fu_code_match_T_507) \n node _fu_code_match_T_517 = or(_fu_code_match_T_516, _fu_code_match_T_508) \n node _fu_code_match_T_518 = or(_fu_code_match_T_517, _fu_code_match_T_509) \n node _fu_code_match_T_519 = or(_fu_code_match_T_518, _fu_code_match_T_510) \n node _fu_code_match_T_520 = or(_fu_code_match_T_519, _fu_code_match_T_511) \n node _fu_code_match_T_521 = or(_fu_code_match_T_520, _fu_code_match_T_512) \n node fu_code_match_28 = or(_fu_code_match_T_521, _fu_code_match_T_513) \n node can_allocate_28 = and(fu_code_match_28, UInt<1>(0h1)) \n node _T_660 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_661 = and(issue_slots[14].request, _T_660) \n node _T_662 = and(_T_661, can_allocate_28) \n node _T_663 = eq(_T_642, UInt<1>(0h0)) \n node _T_664 = and(_T_662, _T_663) \n when _T_664 : \n connect issue_slots[14].grant, UInt<1>(0h1) \n connect iss_uops[0].valid, UInt<1>(0h1) \n connect iss_uops[0].bits, issue_slots[14].iss_uop \n node _T_665 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_666 = and(issue_slots[14].request, _T_665) \n node _T_667 = and(_T_666, can_allocate_28) \n node _T_668 = or(_T_667, _T_642) \n node _T_669 = and(issue_slots[14].request, can_allocate_28) \n node _T_670 = eq(_T_642, UInt<1>(0h0)) \n node _T_671 = and(_T_669, _T_670) \n node _T_672 = or(_T_671, UInt<1>(0h0)) \n node _fu_code_match_T_522 = and(issue_slots[14].iss_uop.fu_code[0], io.fu_types[1][0]) \n node _fu_code_match_T_523 = and(issue_slots[14].iss_uop.fu_code[1], io.fu_types[1][1]) \n node _fu_code_match_T_524 = and(issue_slots[14].iss_uop.fu_code[2], io.fu_types[1][2]) \n node _fu_code_match_T_525 = and(issue_slots[14].iss_uop.fu_code[3], io.fu_types[1][3]) \n node _fu_code_match_T_526 = and(issue_slots[14].iss_uop.fu_code[4], io.fu_types[1][4]) \n node _fu_code_match_T_527 = and(issue_slots[14].iss_uop.fu_code[5], io.fu_types[1][5]) \n node _fu_code_match_T_528 = and(issue_slots[14].iss_uop.fu_code[6], io.fu_types[1][6]) \n node _fu_code_match_T_529 = and(issue_slots[14].iss_uop.fu_code[7], io.fu_types[1][7]) \n node _fu_code_match_T_530 = and(issue_slots[14].iss_uop.fu_code[8], io.fu_types[1][8]) \n node _fu_code_match_T_531 = and(issue_slots[14].iss_uop.fu_code[9], io.fu_types[1][9]) \n node _fu_code_match_T_532 = or(_fu_code_match_T_522, _fu_code_match_T_523) \n node _fu_code_match_T_533 = or(_fu_code_match_T_532, _fu_code_match_T_524) \n node _fu_code_match_T_534 = or(_fu_code_match_T_533, _fu_code_match_T_525) \n node _fu_code_match_T_535 = or(_fu_code_match_T_534, _fu_code_match_T_526) \n node _fu_code_match_T_536 = or(_fu_code_match_T_535, _fu_code_match_T_527) \n node _fu_code_match_T_537 = or(_fu_code_match_T_536, _fu_code_match_T_528) \n node _fu_code_match_T_538 = or(_fu_code_match_T_537, _fu_code_match_T_529) \n node _fu_code_match_T_539 = or(_fu_code_match_T_538, _fu_code_match_T_530) \n node fu_code_match_29 = or(_fu_code_match_T_539, _fu_code_match_T_531) \n node can_allocate_29 = and(fu_code_match_29, UInt<1>(0h1)) \n node _T_673 = eq(_T_672, UInt<1>(0h0)) \n node _T_674 = and(issue_slots[14].request, _T_673) \n node _T_675 = and(_T_674, can_allocate_29) \n node _T_676 = eq(_T_655, UInt<1>(0h0)) \n node _T_677 = and(_T_675, _T_676) \n when _T_677 : \n connect issue_slots[14].grant, UInt<1>(0h1) \n connect iss_uops[1].valid, UInt<1>(0h1) \n connect iss_uops[1].bits, issue_slots[14].iss_uop \n node _T_678 = eq(_T_672, UInt<1>(0h0)) \n node _T_679 = and(issue_slots[14].request, _T_678) \n node _T_680 = and(_T_679, can_allocate_29) \n node _T_681 = or(_T_680, _T_655) \n node _T_682 = and(issue_slots[14].request, can_allocate_29) \n node _T_683 = eq(_T_655, UInt<1>(0h0)) \n node _T_684 = and(_T_682, _T_683) \n node _T_685 = or(_T_684, _T_672) \n connect issue_slots[15].grant, UInt<1>(0h0) \n node _fu_code_match_T_540 = and(issue_slots[15].iss_uop.fu_code[0], io.fu_types[0][0]) \n node _fu_code_match_T_541 = and(issue_slots[15].iss_uop.fu_code[1], io.fu_types[0][1]) \n node _fu_code_match_T_542 = and(issue_slots[15].iss_uop.fu_code[2], io.fu_types[0][2]) \n node _fu_code_match_T_543 = and(issue_slots[15].iss_uop.fu_code[3], io.fu_types[0][3]) \n node _fu_code_match_T_544 = and(issue_slots[15].iss_uop.fu_code[4], io.fu_types[0][4]) \n node _fu_code_match_T_545 = and(issue_slots[15].iss_uop.fu_code[5], io.fu_types[0][5]) \n node _fu_code_match_T_546 = and(issue_slots[15].iss_uop.fu_code[6], io.fu_types[0][6]) \n node _fu_code_match_T_547 = and(issue_slots[15].iss_uop.fu_code[7], io.fu_types[0][7]) \n node _fu_code_match_T_548 = and(issue_slots[15].iss_uop.fu_code[8], io.fu_types[0][8]) \n node _fu_code_match_T_549 = and(issue_slots[15].iss_uop.fu_code[9], io.fu_types[0][9]) \n node _fu_code_match_T_550 = or(_fu_code_match_T_540, _fu_code_match_T_541) \n node _fu_code_match_T_551 = or(_fu_code_match_T_550, _fu_code_match_T_542) \n node _fu_code_match_T_552 = or(_fu_code_match_T_551, _fu_code_match_T_543) \n node _fu_code_match_T_553 = or(_fu_code_match_T_552, _fu_code_match_T_544) \n node _fu_code_match_T_554 = or(_fu_code_match_T_553, _fu_code_match_T_545) \n node _fu_code_match_T_555 = or(_fu_code_match_T_554, _fu_code_match_T_546) \n node _fu_code_match_T_556 = or(_fu_code_match_T_555, _fu_code_match_T_547) \n node _fu_code_match_T_557 = or(_fu_code_match_T_556, _fu_code_match_T_548) \n node fu_code_match_30 = or(_fu_code_match_T_557, _fu_code_match_T_549) \n node can_allocate_30 = and(fu_code_match_30, UInt<1>(0h1)) \n node _T_686 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_687 = and(issue_slots[15].request, _T_686) \n node _T_688 = and(_T_687, can_allocate_30) \n node _T_689 = eq(_T_668, UInt<1>(0h0)) \n node _T_690 = and(_T_688, _T_689) \n when _T_690 : \n connect issue_slots[15].grant, UInt<1>(0h1) \n connect iss_uops[0].valid, UInt<1>(0h1) \n connect iss_uops[0].bits, issue_slots[15].iss_uop \n node _T_691 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_692 = and(issue_slots[15].request, _T_691) \n node _T_693 = and(_T_692, can_allocate_30) \n node _T_694 = or(_T_693, _T_668) \n node _T_695 = and(issue_slots[15].request, can_allocate_30) \n node _T_696 = eq(_T_668, UInt<1>(0h0)) \n node _T_697 = and(_T_695, _T_696) \n node _T_698 = or(_T_697, UInt<1>(0h0)) \n node _fu_code_match_T_558 = and(issue_slots[15].iss_uop.fu_code[0], io.fu_types[1][0]) \n node _fu_code_match_T_559 = and(issue_slots[15].iss_uop.fu_code[1], io.fu_types[1][1]) \n node _fu_code_match_T_560 = and(issue_slots[15].iss_uop.fu_code[2], io.fu_types[1][2]) \n node _fu_code_match_T_561 = and(issue_slots[15].iss_uop.fu_code[3], io.fu_types[1][3]) \n node _fu_code_match_T_562 = and(issue_slots[15].iss_uop.fu_code[4], io.fu_types[1][4]) \n node _fu_code_match_T_563 = and(issue_slots[15].iss_uop.fu_code[5], io.fu_types[1][5]) \n node _fu_code_match_T_564 = and(issue_slots[15].iss_uop.fu_code[6], io.fu_types[1][6]) \n node _fu_code_match_T_565 = and(issue_slots[15].iss_uop.fu_code[7], io.fu_types[1][7]) \n node _fu_code_match_T_566 = and(issue_slots[15].iss_uop.fu_code[8], io.fu_types[1][8]) \n node _fu_code_match_T_567 = and(issue_slots[15].iss_uop.fu_code[9], io.fu_types[1][9]) \n node _fu_code_match_T_568 = or(_fu_code_match_T_558, _fu_code_match_T_559) \n node _fu_code_match_T_569 = or(_fu_code_match_T_568, _fu_code_match_T_560) \n node _fu_code_match_T_570 = or(_fu_code_match_T_569, _fu_code_match_T_561) \n node _fu_code_match_T_571 = or(_fu_code_match_T_570, _fu_code_match_T_562) \n node _fu_code_match_T_572 = or(_fu_code_match_T_571, _fu_code_match_T_563) \n node _fu_code_match_T_573 = or(_fu_code_match_T_572, _fu_code_match_T_564) \n node _fu_code_match_T_574 = or(_fu_code_match_T_573, _fu_code_match_T_565) \n node _fu_code_match_T_575 = or(_fu_code_match_T_574, _fu_code_match_T_566) \n node fu_code_match_31 = or(_fu_code_match_T_575, _fu_code_match_T_567) \n node can_allocate_31 = and(fu_code_match_31, UInt<1>(0h1)) \n node _T_699 = eq(_T_698, UInt<1>(0h0)) \n node _T_700 = and(issue_slots[15].request, _T_699) \n node _T_701 = and(_T_700, can_allocate_31) \n node _T_702 = eq(_T_681, UInt<1>(0h0)) \n node _T_703 = and(_T_701, _T_702) \n when _T_703 : \n connect issue_slots[15].grant, UInt<1>(0h1) \n connect iss_uops[1].valid, UInt<1>(0h1) \n connect iss_uops[1].bits, issue_slots[15].iss_uop \n node _T_704 = eq(_T_698, UInt<1>(0h0)) \n node _T_705 = and(issue_slots[15].request, _T_704) \n node _T_706 = and(_T_705, can_allocate_31) \n node _T_707 = or(_T_706, _T_681) \n node _T_708 = and(issue_slots[15].request, can_allocate_31) \n node _T_709 = eq(_T_681, UInt<1>(0h0)) \n node _T_710 = and(_T_708, _T_709) \n node _T_711 = or(_T_710, _T_698) \n connect issue_slots[16].grant, UInt<1>(0h0) \n node _fu_code_match_T_576 = and(issue_slots[16].iss_uop.fu_code[0], io.fu_types[0][0]) \n node _fu_code_match_T_577 = and(issue_slots[16].iss_uop.fu_code[1], io.fu_types[0][1]) \n node _fu_code_match_T_578 = and(issue_slots[16].iss_uop.fu_code[2], io.fu_types[0][2]) \n node _fu_code_match_T_579 = and(issue_slots[16].iss_uop.fu_code[3], io.fu_types[0][3]) \n node _fu_code_match_T_580 = and(issue_slots[16].iss_uop.fu_code[4], io.fu_types[0][4]) \n node _fu_code_match_T_581 = and(issue_slots[16].iss_uop.fu_code[5], io.fu_types[0][5]) \n node _fu_code_match_T_582 = and(issue_slots[16].iss_uop.fu_code[6], io.fu_types[0][6]) \n node _fu_code_match_T_583 = and(issue_slots[16].iss_uop.fu_code[7], io.fu_types[0][7]) \n node _fu_code_match_T_584 = and(issue_slots[16].iss_uop.fu_code[8], io.fu_types[0][8]) \n node _fu_code_match_T_585 = and(issue_slots[16].iss_uop.fu_code[9], io.fu_types[0][9]) \n node _fu_code_match_T_586 = or(_fu_code_match_T_576, _fu_code_match_T_577) \n node _fu_code_match_T_587 = or(_fu_code_match_T_586, _fu_code_match_T_578) \n node _fu_code_match_T_588 = or(_fu_code_match_T_587, _fu_code_match_T_579) \n node _fu_code_match_T_589 = or(_fu_code_match_T_588, _fu_code_match_T_580) \n node _fu_code_match_T_590 = or(_fu_code_match_T_589, _fu_code_match_T_581) \n node _fu_code_match_T_591 = or(_fu_code_match_T_590, _fu_code_match_T_582) \n node _fu_code_match_T_592 = or(_fu_code_match_T_591, _fu_code_match_T_583) \n node _fu_code_match_T_593 = or(_fu_code_match_T_592, _fu_code_match_T_584) \n node fu_code_match_32 = or(_fu_code_match_T_593, _fu_code_match_T_585) \n node can_allocate_32 = and(fu_code_match_32, UInt<1>(0h1)) \n node _T_712 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_713 = and(issue_slots[16].request, _T_712) \n node _T_714 = and(_T_713, can_allocate_32) \n node _T_715 = eq(_T_694, UInt<1>(0h0)) \n node _T_716 = and(_T_714, _T_715) \n when _T_716 : \n connect issue_slots[16].grant, UInt<1>(0h1) \n connect iss_uops[0].valid, UInt<1>(0h1) \n connect iss_uops[0].bits, issue_slots[16].iss_uop \n node _T_717 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_718 = and(issue_slots[16].request, _T_717) \n node _T_719 = and(_T_718, can_allocate_32) \n node _T_720 = or(_T_719, _T_694) \n node _T_721 = and(issue_slots[16].request, can_allocate_32) \n node _T_722 = eq(_T_694, UInt<1>(0h0)) \n node _T_723 = and(_T_721, _T_722) \n node _T_724 = or(_T_723, UInt<1>(0h0)) \n node _fu_code_match_T_594 = and(issue_slots[16].iss_uop.fu_code[0], io.fu_types[1][0]) \n node _fu_code_match_T_595 = and(issue_slots[16].iss_uop.fu_code[1], io.fu_types[1][1]) \n node _fu_code_match_T_596 = and(issue_slots[16].iss_uop.fu_code[2], io.fu_types[1][2]) \n node _fu_code_match_T_597 = and(issue_slots[16].iss_uop.fu_code[3], io.fu_types[1][3]) \n node _fu_code_match_T_598 = and(issue_slots[16].iss_uop.fu_code[4], io.fu_types[1][4]) \n node _fu_code_match_T_599 = and(issue_slots[16].iss_uop.fu_code[5], io.fu_types[1][5]) \n node _fu_code_match_T_600 = and(issue_slots[16].iss_uop.fu_code[6], io.fu_types[1][6]) \n node _fu_code_match_T_601 = and(issue_slots[16].iss_uop.fu_code[7], io.fu_types[1][7]) \n node _fu_code_match_T_602 = and(issue_slots[16].iss_uop.fu_code[8], io.fu_types[1][8]) \n node _fu_code_match_T_603 = and(issue_slots[16].iss_uop.fu_code[9], io.fu_types[1][9]) \n node _fu_code_match_T_604 = or(_fu_code_match_T_594, _fu_code_match_T_595) \n node _fu_code_match_T_605 = or(_fu_code_match_T_604, _fu_code_match_T_596) \n node _fu_code_match_T_606 = or(_fu_code_match_T_605, _fu_code_match_T_597) \n node _fu_code_match_T_607 = or(_fu_code_match_T_606, _fu_code_match_T_598) \n node _fu_code_match_T_608 = or(_fu_code_match_T_607, _fu_code_match_T_599) \n node _fu_code_match_T_609 = or(_fu_code_match_T_608, _fu_code_match_T_600) \n node _fu_code_match_T_610 = or(_fu_code_match_T_609, _fu_code_match_T_601) \n node _fu_code_match_T_611 = or(_fu_code_match_T_610, _fu_code_match_T_602) \n node fu_code_match_33 = or(_fu_code_match_T_611, _fu_code_match_T_603) \n node can_allocate_33 = and(fu_code_match_33, UInt<1>(0h1)) \n node _T_725 = eq(_T_724, UInt<1>(0h0)) \n node _T_726 = and(issue_slots[16].request, _T_725) \n node _T_727 = and(_T_726, can_allocate_33) \n node _T_728 = eq(_T_707, UInt<1>(0h0)) \n node _T_729 = and(_T_727, _T_728) \n when _T_729 : \n connect issue_slots[16].grant, UInt<1>(0h1) \n connect iss_uops[1].valid, UInt<1>(0h1) \n connect iss_uops[1].bits, issue_slots[16].iss_uop \n node _T_730 = eq(_T_724, UInt<1>(0h0)) \n node _T_731 = and(issue_slots[16].request, _T_730) \n node _T_732 = and(_T_731, can_allocate_33) \n node _T_733 = or(_T_732, _T_707) \n node _T_734 = and(issue_slots[16].request, can_allocate_33) \n node _T_735 = eq(_T_707, UInt<1>(0h0)) \n node _T_736 = and(_T_734, _T_735) \n node _T_737 = or(_T_736, _T_724) \n connect issue_slots[17].grant, UInt<1>(0h0) \n node _fu_code_match_T_612 = and(issue_slots[17].iss_uop.fu_code[0], io.fu_types[0][0]) \n node _fu_code_match_T_613 = and(issue_slots[17].iss_uop.fu_code[1], io.fu_types[0][1]) \n node _fu_code_match_T_614 = and(issue_slots[17].iss_uop.fu_code[2], io.fu_types[0][2]) \n node _fu_code_match_T_615 = and(issue_slots[17].iss_uop.fu_code[3], io.fu_types[0][3]) \n node _fu_code_match_T_616 = and(issue_slots[17].iss_uop.fu_code[4], io.fu_types[0][4]) \n node _fu_code_match_T_617 = and(issue_slots[17].iss_uop.fu_code[5], io.fu_types[0][5]) \n node _fu_code_match_T_618 = and(issue_slots[17].iss_uop.fu_code[6], io.fu_types[0][6]) \n node _fu_code_match_T_619 = and(issue_slots[17].iss_uop.fu_code[7], io.fu_types[0][7]) \n node _fu_code_match_T_620 = and(issue_slots[17].iss_uop.fu_code[8], io.fu_types[0][8]) \n node _fu_code_match_T_621 = and(issue_slots[17].iss_uop.fu_code[9], io.fu_types[0][9]) \n node _fu_code_match_T_622 = or(_fu_code_match_T_612, _fu_code_match_T_613) \n node _fu_code_match_T_623 = or(_fu_code_match_T_622, _fu_code_match_T_614) \n node _fu_code_match_T_624 = or(_fu_code_match_T_623, _fu_code_match_T_615) \n node _fu_code_match_T_625 = or(_fu_code_match_T_624, _fu_code_match_T_616) \n node _fu_code_match_T_626 = or(_fu_code_match_T_625, _fu_code_match_T_617) \n node _fu_code_match_T_627 = or(_fu_code_match_T_626, _fu_code_match_T_618) \n node _fu_code_match_T_628 = or(_fu_code_match_T_627, _fu_code_match_T_619) \n node _fu_code_match_T_629 = or(_fu_code_match_T_628, _fu_code_match_T_620) \n node fu_code_match_34 = or(_fu_code_match_T_629, _fu_code_match_T_621) \n node can_allocate_34 = and(fu_code_match_34, UInt<1>(0h1)) \n node _T_738 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_739 = and(issue_slots[17].request, _T_738) \n node _T_740 = and(_T_739, can_allocate_34) \n node _T_741 = eq(_T_720, UInt<1>(0h0)) \n node _T_742 = and(_T_740, _T_741) \n when _T_742 : \n connect issue_slots[17].grant, UInt<1>(0h1) \n connect iss_uops[0].valid, UInt<1>(0h1) \n connect iss_uops[0].bits, issue_slots[17].iss_uop \n node _T_743 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_744 = and(issue_slots[17].request, _T_743) \n node _T_745 = and(_T_744, can_allocate_34) \n node _T_746 = or(_T_745, _T_720) \n node _T_747 = and(issue_slots[17].request, can_allocate_34) \n node _T_748 = eq(_T_720, UInt<1>(0h0)) \n node _T_749 = and(_T_747, _T_748) \n node _T_750 = or(_T_749, UInt<1>(0h0)) \n node _fu_code_match_T_630 = and(issue_slots[17].iss_uop.fu_code[0], io.fu_types[1][0]) \n node _fu_code_match_T_631 = and(issue_slots[17].iss_uop.fu_code[1], io.fu_types[1][1]) \n node _fu_code_match_T_632 = and(issue_slots[17].iss_uop.fu_code[2], io.fu_types[1][2]) \n node _fu_code_match_T_633 = and(issue_slots[17].iss_uop.fu_code[3], io.fu_types[1][3]) \n node _fu_code_match_T_634 = and(issue_slots[17].iss_uop.fu_code[4], io.fu_types[1][4]) \n node _fu_code_match_T_635 = and(issue_slots[17].iss_uop.fu_code[5], io.fu_types[1][5]) \n node _fu_code_match_T_636 = and(issue_slots[17].iss_uop.fu_code[6], io.fu_types[1][6]) \n node _fu_code_match_T_637 = and(issue_slots[17].iss_uop.fu_code[7], io.fu_types[1][7]) \n node _fu_code_match_T_638 = and(issue_slots[17].iss_uop.fu_code[8], io.fu_types[1][8]) \n node _fu_code_match_T_639 = and(issue_slots[17].iss_uop.fu_code[9], io.fu_types[1][9]) \n node _fu_code_match_T_640 = or(_fu_code_match_T_630, _fu_code_match_T_631) \n node _fu_code_match_T_641 = or(_fu_code_match_T_640, _fu_code_match_T_632) \n node _fu_code_match_T_642 = or(_fu_code_match_T_641, _fu_code_match_T_633) \n node _fu_code_match_T_643 = or(_fu_code_match_T_642, _fu_code_match_T_634) \n node _fu_code_match_T_644 = or(_fu_code_match_T_643, _fu_code_match_T_635) \n node _fu_code_match_T_645 = or(_fu_code_match_T_644, _fu_code_match_T_636) \n node _fu_code_match_T_646 = or(_fu_code_match_T_645, _fu_code_match_T_637) \n node _fu_code_match_T_647 = or(_fu_code_match_T_646, _fu_code_match_T_638) \n node fu_code_match_35 = or(_fu_code_match_T_647, _fu_code_match_T_639) \n node can_allocate_35 = and(fu_code_match_35, UInt<1>(0h1)) \n node _T_751 = eq(_T_750, UInt<1>(0h0)) \n node _T_752 = and(issue_slots[17].request, _T_751) \n node _T_753 = and(_T_752, can_allocate_35) \n node _T_754 = eq(_T_733, UInt<1>(0h0)) \n node _T_755 = and(_T_753, _T_754) \n when _T_755 : \n connect issue_slots[17].grant, UInt<1>(0h1) \n connect iss_uops[1].valid, UInt<1>(0h1) \n connect iss_uops[1].bits, issue_slots[17].iss_uop \n node _T_756 = eq(_T_750, UInt<1>(0h0)) \n node _T_757 = and(issue_slots[17].request, _T_756) \n node _T_758 = and(_T_757, can_allocate_35) \n node _T_759 = or(_T_758, _T_733) \n node _T_760 = and(issue_slots[17].request, can_allocate_35) \n node _T_761 = eq(_T_733, UInt<1>(0h0)) \n node _T_762 = and(_T_760, _T_761) \n node _T_763 = or(_T_762, _T_750) \n connect issue_slots[18].grant, UInt<1>(0h0) \n node _fu_code_match_T_648 = and(issue_slots[18].iss_uop.fu_code[0], io.fu_types[0][0]) \n node _fu_code_match_T_649 = and(issue_slots[18].iss_uop.fu_code[1], io.fu_types[0][1]) \n node _fu_code_match_T_650 = and(issue_slots[18].iss_uop.fu_code[2], io.fu_types[0][2]) \n node _fu_code_match_T_651 = and(issue_slots[18].iss_uop.fu_code[3], io.fu_types[0][3]) \n node _fu_code_match_T_652 = and(issue_slots[18].iss_uop.fu_code[4], io.fu_types[0][4]) \n node _fu_code_match_T_653 = and(issue_slots[18].iss_uop.fu_code[5], io.fu_types[0][5]) \n node _fu_code_match_T_654 = and(issue_slots[18].iss_uop.fu_code[6], io.fu_types[0][6]) \n node _fu_code_match_T_655 = and(issue_slots[18].iss_uop.fu_code[7], io.fu_types[0][7]) \n node _fu_code_match_T_656 = and(issue_slots[18].iss_uop.fu_code[8], io.fu_types[0][8]) \n node _fu_code_match_T_657 = and(issue_slots[18].iss_uop.fu_code[9], io.fu_types[0][9]) \n node _fu_code_match_T_658 = or(_fu_code_match_T_648, _fu_code_match_T_649) \n node _fu_code_match_T_659 = or(_fu_code_match_T_658, _fu_code_match_T_650) \n node _fu_code_match_T_660 = or(_fu_code_match_T_659, _fu_code_match_T_651) \n node _fu_code_match_T_661 = or(_fu_code_match_T_660, _fu_code_match_T_652) \n node _fu_code_match_T_662 = or(_fu_code_match_T_661, _fu_code_match_T_653) \n node _fu_code_match_T_663 = or(_fu_code_match_T_662, _fu_code_match_T_654) \n node _fu_code_match_T_664 = or(_fu_code_match_T_663, _fu_code_match_T_655) \n node _fu_code_match_T_665 = or(_fu_code_match_T_664, _fu_code_match_T_656) \n node fu_code_match_36 = or(_fu_code_match_T_665, _fu_code_match_T_657) \n node can_allocate_36 = and(fu_code_match_36, UInt<1>(0h1)) \n node _T_764 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_765 = and(issue_slots[18].request, _T_764) \n node _T_766 = and(_T_765, can_allocate_36) \n node _T_767 = eq(_T_746, UInt<1>(0h0)) \n node _T_768 = and(_T_766, _T_767) \n when _T_768 : \n connect issue_slots[18].grant, UInt<1>(0h1) \n connect iss_uops[0].valid, UInt<1>(0h1) \n connect iss_uops[0].bits, issue_slots[18].iss_uop \n node _T_769 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_770 = and(issue_slots[18].request, _T_769) \n node _T_771 = and(_T_770, can_allocate_36) \n node _T_772 = or(_T_771, _T_746) \n node _T_773 = and(issue_slots[18].request, can_allocate_36) \n node _T_774 = eq(_T_746, UInt<1>(0h0)) \n node _T_775 = and(_T_773, _T_774) \n node _T_776 = or(_T_775, UInt<1>(0h0)) \n node _fu_code_match_T_666 = and(issue_slots[18].iss_uop.fu_code[0], io.fu_types[1][0]) \n node _fu_code_match_T_667 = and(issue_slots[18].iss_uop.fu_code[1], io.fu_types[1][1]) \n node _fu_code_match_T_668 = and(issue_slots[18].iss_uop.fu_code[2], io.fu_types[1][2]) \n node _fu_code_match_T_669 = and(issue_slots[18].iss_uop.fu_code[3], io.fu_types[1][3]) \n node _fu_code_match_T_670 = and(issue_slots[18].iss_uop.fu_code[4], io.fu_types[1][4]) \n node _fu_code_match_T_671 = and(issue_slots[18].iss_uop.fu_code[5], io.fu_types[1][5]) \n node _fu_code_match_T_672 = and(issue_slots[18].iss_uop.fu_code[6], io.fu_types[1][6]) \n node _fu_code_match_T_673 = and(issue_slots[18].iss_uop.fu_code[7], io.fu_types[1][7]) \n node _fu_code_match_T_674 = and(issue_slots[18].iss_uop.fu_code[8], io.fu_types[1][8]) \n node _fu_code_match_T_675 = and(issue_slots[18].iss_uop.fu_code[9], io.fu_types[1][9]) \n node _fu_code_match_T_676 = or(_fu_code_match_T_666, _fu_code_match_T_667) \n node _fu_code_match_T_677 = or(_fu_code_match_T_676, _fu_code_match_T_668) \n node _fu_code_match_T_678 = or(_fu_code_match_T_677, _fu_code_match_T_669) \n node _fu_code_match_T_679 = or(_fu_code_match_T_678, _fu_code_match_T_670) \n node _fu_code_match_T_680 = or(_fu_code_match_T_679, _fu_code_match_T_671) \n node _fu_code_match_T_681 = or(_fu_code_match_T_680, _fu_code_match_T_672) \n node _fu_code_match_T_682 = or(_fu_code_match_T_681, _fu_code_match_T_673) \n node _fu_code_match_T_683 = or(_fu_code_match_T_682, _fu_code_match_T_674) \n node fu_code_match_37 = or(_fu_code_match_T_683, _fu_code_match_T_675) \n node can_allocate_37 = and(fu_code_match_37, UInt<1>(0h1)) \n node _T_777 = eq(_T_776, UInt<1>(0h0)) \n node _T_778 = and(issue_slots[18].request, _T_777) \n node _T_779 = and(_T_778, can_allocate_37) \n node _T_780 = eq(_T_759, UInt<1>(0h0)) \n node _T_781 = and(_T_779, _T_780) \n when _T_781 : \n connect issue_slots[18].grant, UInt<1>(0h1) \n connect iss_uops[1].valid, UInt<1>(0h1) \n connect iss_uops[1].bits, issue_slots[18].iss_uop \n node _T_782 = eq(_T_776, UInt<1>(0h0)) \n node _T_783 = and(issue_slots[18].request, _T_782) \n node _T_784 = and(_T_783, can_allocate_37) \n node _T_785 = or(_T_784, _T_759) \n node _T_786 = and(issue_slots[18].request, can_allocate_37) \n node _T_787 = eq(_T_759, UInt<1>(0h0)) \n node _T_788 = and(_T_786, _T_787) \n node _T_789 = or(_T_788, _T_776) \n connect issue_slots[19].grant, UInt<1>(0h0) \n node _fu_code_match_T_684 = and(issue_slots[19].iss_uop.fu_code[0], io.fu_types[0][0]) \n node _fu_code_match_T_685 = and(issue_slots[19].iss_uop.fu_code[1], io.fu_types[0][1]) \n node _fu_code_match_T_686 = and(issue_slots[19].iss_uop.fu_code[2], io.fu_types[0][2]) \n node _fu_code_match_T_687 = and(issue_slots[19].iss_uop.fu_code[3], io.fu_types[0][3]) \n node _fu_code_match_T_688 = and(issue_slots[19].iss_uop.fu_code[4], io.fu_types[0][4]) \n node _fu_code_match_T_689 = and(issue_slots[19].iss_uop.fu_code[5], io.fu_types[0][5]) \n node _fu_code_match_T_690 = and(issue_slots[19].iss_uop.fu_code[6], io.fu_types[0][6]) \n node _fu_code_match_T_691 = and(issue_slots[19].iss_uop.fu_code[7], io.fu_types[0][7]) \n node _fu_code_match_T_692 = and(issue_slots[19].iss_uop.fu_code[8], io.fu_types[0][8]) \n node _fu_code_match_T_693 = and(issue_slots[19].iss_uop.fu_code[9], io.fu_types[0][9]) \n node _fu_code_match_T_694 = or(_fu_code_match_T_684, _fu_code_match_T_685) \n node _fu_code_match_T_695 = or(_fu_code_match_T_694, _fu_code_match_T_686) \n node _fu_code_match_T_696 = or(_fu_code_match_T_695, _fu_code_match_T_687) \n node _fu_code_match_T_697 = or(_fu_code_match_T_696, _fu_code_match_T_688) \n node _fu_code_match_T_698 = or(_fu_code_match_T_697, _fu_code_match_T_689) \n node _fu_code_match_T_699 = or(_fu_code_match_T_698, _fu_code_match_T_690) \n node _fu_code_match_T_700 = or(_fu_code_match_T_699, _fu_code_match_T_691) \n node _fu_code_match_T_701 = or(_fu_code_match_T_700, _fu_code_match_T_692) \n node fu_code_match_38 = or(_fu_code_match_T_701, _fu_code_match_T_693) \n node can_allocate_38 = and(fu_code_match_38, UInt<1>(0h1)) \n node _T_790 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_791 = and(issue_slots[19].request, _T_790) \n node _T_792 = and(_T_791, can_allocate_38) \n node _T_793 = eq(_T_772, UInt<1>(0h0)) \n node _T_794 = and(_T_792, _T_793) \n when _T_794 : \n connect issue_slots[19].grant, UInt<1>(0h1) \n connect iss_uops[0].valid, UInt<1>(0h1) \n connect iss_uops[0].bits, issue_slots[19].iss_uop \n node _T_795 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_796 = and(issue_slots[19].request, _T_795) \n node _T_797 = and(_T_796, can_allocate_38) \n node _T_798 = or(_T_797, _T_772) \n node _T_799 = and(issue_slots[19].request, can_allocate_38) \n node _T_800 = eq(_T_772, UInt<1>(0h0)) \n node _T_801 = and(_T_799, _T_800) \n node _T_802 = or(_T_801, UInt<1>(0h0)) \n node _fu_code_match_T_702 = and(issue_slots[19].iss_uop.fu_code[0], io.fu_types[1][0]) \n node _fu_code_match_T_703 = and(issue_slots[19].iss_uop.fu_code[1], io.fu_types[1][1]) \n node _fu_code_match_T_704 = and(issue_slots[19].iss_uop.fu_code[2], io.fu_types[1][2]) \n node _fu_code_match_T_705 = and(issue_slots[19].iss_uop.fu_code[3], io.fu_types[1][3]) \n node _fu_code_match_T_706 = and(issue_slots[19].iss_uop.fu_code[4], io.fu_types[1][4]) \n node _fu_code_match_T_707 = and(issue_slots[19].iss_uop.fu_code[5], io.fu_types[1][5]) \n node _fu_code_match_T_708 = and(issue_slots[19].iss_uop.fu_code[6], io.fu_types[1][6]) \n node _fu_code_match_T_709 = and(issue_slots[19].iss_uop.fu_code[7], io.fu_types[1][7]) \n node _fu_code_match_T_710 = and(issue_slots[19].iss_uop.fu_code[8], io.fu_types[1][8]) \n node _fu_code_match_T_711 = and(issue_slots[19].iss_uop.fu_code[9], io.fu_types[1][9]) \n node _fu_code_match_T_712 = or(_fu_code_match_T_702, _fu_code_match_T_703) \n node _fu_code_match_T_713 = or(_fu_code_match_T_712, _fu_code_match_T_704) \n node _fu_code_match_T_714 = or(_fu_code_match_T_713, _fu_code_match_T_705) \n node _fu_code_match_T_715 = or(_fu_code_match_T_714, _fu_code_match_T_706) \n node _fu_code_match_T_716 = or(_fu_code_match_T_715, _fu_code_match_T_707) \n node _fu_code_match_T_717 = or(_fu_code_match_T_716, _fu_code_match_T_708) \n node _fu_code_match_T_718 = or(_fu_code_match_T_717, _fu_code_match_T_709) \n node _fu_code_match_T_719 = or(_fu_code_match_T_718, _fu_code_match_T_710) \n node fu_code_match_39 = or(_fu_code_match_T_719, _fu_code_match_T_711) \n node can_allocate_39 = and(fu_code_match_39, UInt<1>(0h1)) \n node _T_803 = eq(_T_802, UInt<1>(0h0)) \n node _T_804 = and(issue_slots[19].request, _T_803) \n node _T_805 = and(_T_804, can_allocate_39) \n node _T_806 = eq(_T_785, UInt<1>(0h0)) \n node _T_807 = and(_T_805, _T_806) \n when _T_807 : \n connect issue_slots[19].grant, UInt<1>(0h1) \n connect iss_uops[1].valid, UInt<1>(0h1) \n connect iss_uops[1].bits, issue_slots[19].iss_uop \n node _T_808 = eq(_T_802, UInt<1>(0h0)) \n node _T_809 = and(issue_slots[19].request, _T_808) \n node _T_810 = and(_T_809, can_allocate_39) \n node _T_811 = or(_T_810, _T_785) \n node _T_812 = and(issue_slots[19].request, can_allocate_39) \n node _T_813 = eq(_T_785, UInt<1>(0h0)) \n node _T_814 = and(_T_812, _T_813) \n node _T_815 = or(_T_814, _T_802) \n connect io.iss_uops, iss_uops \n when io.squash_grant : \n connect io.iss_uops[0].valid, UInt<1>(0h0) \n connect io.iss_uops[1].valid, UInt<1>(0h0)"},"response":{"kind":"string","value":"module IssueUnitCollapsing_3(\t// @[issue-unit-age-ordered.scala:22:7]\n input clock,\t// @[issue-unit-age-ordered.scala:22:7]\n input reset,\t// @[issue-unit-age-ordered.scala:22:7]\n output io_dis_uops_0_ready,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_valid,\t// @[issue-unit.scala:44:14]\n input [31:0] io_dis_uops_0_bits_inst,\t// @[issue-unit.scala:44:14]\n input [31:0] io_dis_uops_0_bits_debug_inst,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_is_rvc,\t// @[issue-unit.scala:44:14]\n input [39:0] io_dis_uops_0_bits_debug_pc,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_iq_type_0,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_iq_type_1,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_iq_type_2,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_iq_type_3,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_fu_code_0,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_fu_code_1,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_fu_code_2,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_fu_code_3,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_fu_code_4,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_fu_code_5,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_fu_code_6,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_fu_code_7,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_fu_code_8,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_fu_code_9,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_iw_issued,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_iw_issued_partial_agen,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_iw_issued_partial_dgen,\t// @[issue-unit.scala:44:14]\n input [1:0] io_dis_uops_0_bits_iw_p1_speculative_child,\t// @[issue-unit.scala:44:14]\n input [1:0] io_dis_uops_0_bits_iw_p2_speculative_child,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_iw_p1_bypass_hint,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_iw_p2_bypass_hint,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_iw_p3_bypass_hint,\t// @[issue-unit.scala:44:14]\n input [1:0] io_dis_uops_0_bits_dis_col_sel,\t// @[issue-unit.scala:44:14]\n input [11:0] io_dis_uops_0_bits_br_mask,\t// @[issue-unit.scala:44:14]\n input [3:0] io_dis_uops_0_bits_br_tag,\t// @[issue-unit.scala:44:14]\n input [3:0] io_dis_uops_0_bits_br_type,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_is_sfb,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_is_fence,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_is_fencei,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_is_sfence,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_is_amo,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_is_eret,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_is_sys_pc2epc,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_is_rocc,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_is_mov,\t// @[issue-unit.scala:44:14]\n input [4:0] io_dis_uops_0_bits_ftq_idx,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_edge_inst,\t// @[issue-unit.scala:44:14]\n input [5:0] io_dis_uops_0_bits_pc_lob,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_taken,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_imm_rename,\t// @[issue-unit.scala:44:14]\n input [2:0] io_dis_uops_0_bits_imm_sel,\t// @[issue-unit.scala:44:14]\n input [4:0] io_dis_uops_0_bits_pimm,\t// @[issue-unit.scala:44:14]\n input [19:0] io_dis_uops_0_bits_imm_packed,\t// @[issue-unit.scala:44:14]\n input [1:0] io_dis_uops_0_bits_op1_sel,\t// @[issue-unit.scala:44:14]\n input [2:0] io_dis_uops_0_bits_op2_sel,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_fp_ctrl_ldst,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_fp_ctrl_wen,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_fp_ctrl_ren1,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_fp_ctrl_ren2,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_fp_ctrl_ren3,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_fp_ctrl_swap12,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_fp_ctrl_swap23,\t// @[issue-unit.scala:44:14]\n input [1:0] io_dis_uops_0_bits_fp_ctrl_typeTagIn,\t// @[issue-unit.scala:44:14]\n input [1:0] io_dis_uops_0_bits_fp_ctrl_typeTagOut,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_fp_ctrl_fromint,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_fp_ctrl_toint,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_fp_ctrl_fastpipe,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_fp_ctrl_fma,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_fp_ctrl_div,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_fp_ctrl_sqrt,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_fp_ctrl_wflags,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_fp_ctrl_vec,\t// @[issue-unit.scala:44:14]\n input [5:0] io_dis_uops_0_bits_rob_idx,\t// @[issue-unit.scala:44:14]\n input [3:0] io_dis_uops_0_bits_ldq_idx,\t// @[issue-unit.scala:44:14]\n input [3:0] io_dis_uops_0_bits_stq_idx,\t// @[issue-unit.scala:44:14]\n input [1:0] io_dis_uops_0_bits_rxq_idx,\t// @[issue-unit.scala:44:14]\n input [6:0] io_dis_uops_0_bits_pdst,\t// @[issue-unit.scala:44:14]\n input [6:0] io_dis_uops_0_bits_prs1,\t// @[issue-unit.scala:44:14]\n input [6:0] io_dis_uops_0_bits_prs2,\t// @[issue-unit.scala:44:14]\n input [6:0] io_dis_uops_0_bits_prs3,\t// @[issue-unit.scala:44:14]\n input [4:0] io_dis_uops_0_bits_ppred,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_prs1_busy,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_prs2_busy,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_prs3_busy,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_ppred_busy,\t// @[issue-unit.scala:44:14]\n input [6:0] io_dis_uops_0_bits_stale_pdst,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_exception,\t// @[issue-unit.scala:44:14]\n input [63:0] io_dis_uops_0_bits_exc_cause,\t// @[issue-unit.scala:44:14]\n input [4:0] io_dis_uops_0_bits_mem_cmd,\t// @[issue-unit.scala:44:14]\n input [1:0] io_dis_uops_0_bits_mem_size,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_mem_signed,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_uses_ldq,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_uses_stq,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_is_unique,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_flush_on_commit,\t// @[issue-unit.scala:44:14]\n input [2:0] io_dis_uops_0_bits_csr_cmd,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_ldst_is_rs1,\t// @[issue-unit.scala:44:14]\n input [5:0] io_dis_uops_0_bits_ldst,\t// @[issue-unit.scala:44:14]\n input [5:0] io_dis_uops_0_bits_lrs1,\t// @[issue-unit.scala:44:14]\n input [5:0] io_dis_uops_0_bits_lrs2,\t// @[issue-unit.scala:44:14]\n input [5:0] io_dis_uops_0_bits_lrs3,\t// @[issue-unit.scala:44:14]\n input [1:0] io_dis_uops_0_bits_dst_rtype,\t// @[issue-unit.scala:44:14]\n input [1:0] io_dis_uops_0_bits_lrs1_rtype,\t// @[issue-unit.scala:44:14]\n input [1:0] io_dis_uops_0_bits_lrs2_rtype,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_frs3_en,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_fcn_dw,\t// @[issue-unit.scala:44:14]\n input [4:0] io_dis_uops_0_bits_fcn_op,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_fp_val,\t// @[issue-unit.scala:44:14]\n input [2:0] io_dis_uops_0_bits_fp_rm,\t// @[issue-unit.scala:44:14]\n input [1:0] io_dis_uops_0_bits_fp_typ,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_xcpt_pf_if,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_xcpt_ae_if,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_xcpt_ma_if,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_bp_debug_if,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_0_bits_bp_xcpt_if,\t// @[issue-unit.scala:44:14]\n input [2:0] io_dis_uops_0_bits_debug_fsrc,\t// @[issue-unit.scala:44:14]\n input [2:0] io_dis_uops_0_bits_debug_tsrc,\t// @[issue-unit.scala:44:14]\n output io_dis_uops_1_ready,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_valid,\t// @[issue-unit.scala:44:14]\n input [31:0] io_dis_uops_1_bits_inst,\t// @[issue-unit.scala:44:14]\n input [31:0] io_dis_uops_1_bits_debug_inst,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_is_rvc,\t// @[issue-unit.scala:44:14]\n input [39:0] io_dis_uops_1_bits_debug_pc,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_iq_type_0,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_iq_type_1,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_iq_type_2,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_iq_type_3,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_fu_code_0,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_fu_code_1,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_fu_code_2,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_fu_code_3,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_fu_code_4,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_fu_code_5,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_fu_code_6,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_fu_code_7,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_fu_code_8,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_fu_code_9,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_iw_issued,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_iw_issued_partial_agen,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_iw_issued_partial_dgen,\t// @[issue-unit.scala:44:14]\n input [1:0] io_dis_uops_1_bits_iw_p1_speculative_child,\t// @[issue-unit.scala:44:14]\n input [1:0] io_dis_uops_1_bits_iw_p2_speculative_child,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_iw_p1_bypass_hint,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_iw_p2_bypass_hint,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_iw_p3_bypass_hint,\t// @[issue-unit.scala:44:14]\n input [1:0] io_dis_uops_1_bits_dis_col_sel,\t// @[issue-unit.scala:44:14]\n input [11:0] io_dis_uops_1_bits_br_mask,\t// @[issue-unit.scala:44:14]\n input [3:0] io_dis_uops_1_bits_br_tag,\t// @[issue-unit.scala:44:14]\n input [3:0] io_dis_uops_1_bits_br_type,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_is_sfb,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_is_fence,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_is_fencei,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_is_sfence,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_is_amo,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_is_eret,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_is_sys_pc2epc,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_is_rocc,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_is_mov,\t// @[issue-unit.scala:44:14]\n input [4:0] io_dis_uops_1_bits_ftq_idx,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_edge_inst,\t// @[issue-unit.scala:44:14]\n input [5:0] io_dis_uops_1_bits_pc_lob,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_taken,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_imm_rename,\t// @[issue-unit.scala:44:14]\n input [2:0] io_dis_uops_1_bits_imm_sel,\t// @[issue-unit.scala:44:14]\n input [4:0] io_dis_uops_1_bits_pimm,\t// @[issue-unit.scala:44:14]\n input [19:0] io_dis_uops_1_bits_imm_packed,\t// @[issue-unit.scala:44:14]\n input [1:0] io_dis_uops_1_bits_op1_sel,\t// @[issue-unit.scala:44:14]\n input [2:0] io_dis_uops_1_bits_op2_sel,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_fp_ctrl_ldst,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_fp_ctrl_wen,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_fp_ctrl_ren1,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_fp_ctrl_ren2,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_fp_ctrl_ren3,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_fp_ctrl_swap12,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_fp_ctrl_swap23,\t// @[issue-unit.scala:44:14]\n input [1:0] io_dis_uops_1_bits_fp_ctrl_typeTagIn,\t// @[issue-unit.scala:44:14]\n input [1:0] io_dis_uops_1_bits_fp_ctrl_typeTagOut,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_fp_ctrl_fromint,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_fp_ctrl_toint,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_fp_ctrl_fastpipe,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_fp_ctrl_fma,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_fp_ctrl_div,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_fp_ctrl_sqrt,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_fp_ctrl_wflags,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_fp_ctrl_vec,\t// @[issue-unit.scala:44:14]\n input [5:0] io_dis_uops_1_bits_rob_idx,\t// @[issue-unit.scala:44:14]\n input [3:0] io_dis_uops_1_bits_ldq_idx,\t// @[issue-unit.scala:44:14]\n input [3:0] io_dis_uops_1_bits_stq_idx,\t// @[issue-unit.scala:44:14]\n input [1:0] io_dis_uops_1_bits_rxq_idx,\t// @[issue-unit.scala:44:14]\n input [6:0] io_dis_uops_1_bits_pdst,\t// @[issue-unit.scala:44:14]\n input [6:0] io_dis_uops_1_bits_prs1,\t// @[issue-unit.scala:44:14]\n input [6:0] io_dis_uops_1_bits_prs2,\t// @[issue-unit.scala:44:14]\n input [6:0] io_dis_uops_1_bits_prs3,\t// @[issue-unit.scala:44:14]\n input [4:0] io_dis_uops_1_bits_ppred,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_prs1_busy,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_prs2_busy,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_prs3_busy,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_ppred_busy,\t// @[issue-unit.scala:44:14]\n input [6:0] io_dis_uops_1_bits_stale_pdst,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_exception,\t// @[issue-unit.scala:44:14]\n input [63:0] io_dis_uops_1_bits_exc_cause,\t// @[issue-unit.scala:44:14]\n input [4:0] io_dis_uops_1_bits_mem_cmd,\t// @[issue-unit.scala:44:14]\n input [1:0] io_dis_uops_1_bits_mem_size,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_mem_signed,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_uses_ldq,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_uses_stq,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_is_unique,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_flush_on_commit,\t// @[issue-unit.scala:44:14]\n input [2:0] io_dis_uops_1_bits_csr_cmd,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_ldst_is_rs1,\t// @[issue-unit.scala:44:14]\n input [5:0] io_dis_uops_1_bits_ldst,\t// @[issue-unit.scala:44:14]\n input [5:0] io_dis_uops_1_bits_lrs1,\t// @[issue-unit.scala:44:14]\n input [5:0] io_dis_uops_1_bits_lrs2,\t// @[issue-unit.scala:44:14]\n input [5:0] io_dis_uops_1_bits_lrs3,\t// @[issue-unit.scala:44:14]\n input [1:0] io_dis_uops_1_bits_dst_rtype,\t// @[issue-unit.scala:44:14]\n input [1:0] io_dis_uops_1_bits_lrs1_rtype,\t// @[issue-unit.scala:44:14]\n input [1:0] io_dis_uops_1_bits_lrs2_rtype,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_frs3_en,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_fcn_dw,\t// @[issue-unit.scala:44:14]\n input [4:0] io_dis_uops_1_bits_fcn_op,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_fp_val,\t// @[issue-unit.scala:44:14]\n input [2:0] io_dis_uops_1_bits_fp_rm,\t// @[issue-unit.scala:44:14]\n input [1:0] io_dis_uops_1_bits_fp_typ,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_xcpt_pf_if,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_xcpt_ae_if,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_xcpt_ma_if,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_bp_debug_if,\t// @[issue-unit.scala:44:14]\n input io_dis_uops_1_bits_bp_xcpt_if,\t// @[issue-unit.scala:44:14]\n input [2:0] io_dis_uops_1_bits_debug_fsrc,\t// @[issue-unit.scala:44:14]\n input [2:0] io_dis_uops_1_bits_debug_tsrc,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_valid,\t// @[issue-unit.scala:44:14]\n output [31:0] io_iss_uops_0_bits_inst,\t// @[issue-unit.scala:44:14]\n output [31:0] io_iss_uops_0_bits_debug_inst,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_is_rvc,\t// @[issue-unit.scala:44:14]\n output [39:0] io_iss_uops_0_bits_debug_pc,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_iq_type_0,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_iq_type_1,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_iq_type_2,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_iq_type_3,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_fu_code_0,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_fu_code_1,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_fu_code_2,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_fu_code_3,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_fu_code_4,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_fu_code_5,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_fu_code_6,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_fu_code_7,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_fu_code_8,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_fu_code_9,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_iw_issued,\t// @[issue-unit.scala:44:14]\n output [1:0] io_iss_uops_0_bits_iw_p1_speculative_child,\t// @[issue-unit.scala:44:14]\n output [1:0] io_iss_uops_0_bits_iw_p2_speculative_child,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_iw_p1_bypass_hint,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_iw_p2_bypass_hint,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_iw_p3_bypass_hint,\t// @[issue-unit.scala:44:14]\n output [1:0] io_iss_uops_0_bits_dis_col_sel,\t// @[issue-unit.scala:44:14]\n output [11:0] io_iss_uops_0_bits_br_mask,\t// @[issue-unit.scala:44:14]\n output [3:0] io_iss_uops_0_bits_br_tag,\t// @[issue-unit.scala:44:14]\n output [3:0] io_iss_uops_0_bits_br_type,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_is_sfb,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_is_fence,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_is_fencei,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_is_sfence,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_is_amo,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_is_eret,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_is_sys_pc2epc,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_is_rocc,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_is_mov,\t// @[issue-unit.scala:44:14]\n output [4:0] io_iss_uops_0_bits_ftq_idx,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_edge_inst,\t// @[issue-unit.scala:44:14]\n output [5:0] io_iss_uops_0_bits_pc_lob,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_taken,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_imm_rename,\t// @[issue-unit.scala:44:14]\n output [2:0] io_iss_uops_0_bits_imm_sel,\t// @[issue-unit.scala:44:14]\n output [4:0] io_iss_uops_0_bits_pimm,\t// @[issue-unit.scala:44:14]\n output [19:0] io_iss_uops_0_bits_imm_packed,\t// @[issue-unit.scala:44:14]\n output [1:0] io_iss_uops_0_bits_op1_sel,\t// @[issue-unit.scala:44:14]\n output [2:0] io_iss_uops_0_bits_op2_sel,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_fp_ctrl_ldst,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_fp_ctrl_wen,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_fp_ctrl_ren1,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_fp_ctrl_ren2,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_fp_ctrl_ren3,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_fp_ctrl_swap12,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_fp_ctrl_swap23,\t// @[issue-unit.scala:44:14]\n output [1:0] io_iss_uops_0_bits_fp_ctrl_typeTagIn,\t// @[issue-unit.scala:44:14]\n output [1:0] io_iss_uops_0_bits_fp_ctrl_typeTagOut,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_fp_ctrl_fromint,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_fp_ctrl_toint,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_fp_ctrl_fastpipe,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_fp_ctrl_fma,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_fp_ctrl_div,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_fp_ctrl_sqrt,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_fp_ctrl_wflags,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_fp_ctrl_vec,\t// @[issue-unit.scala:44:14]\n output [5:0] io_iss_uops_0_bits_rob_idx,\t// @[issue-unit.scala:44:14]\n output [3:0] io_iss_uops_0_bits_ldq_idx,\t// @[issue-unit.scala:44:14]\n output [3:0] io_iss_uops_0_bits_stq_idx,\t// @[issue-unit.scala:44:14]\n output [1:0] io_iss_uops_0_bits_rxq_idx,\t// @[issue-unit.scala:44:14]\n output [6:0] io_iss_uops_0_bits_pdst,\t// @[issue-unit.scala:44:14]\n output [6:0] io_iss_uops_0_bits_prs1,\t// @[issue-unit.scala:44:14]\n output [6:0] io_iss_uops_0_bits_prs2,\t// @[issue-unit.scala:44:14]\n output [6:0] io_iss_uops_0_bits_prs3,\t// @[issue-unit.scala:44:14]\n output [4:0] io_iss_uops_0_bits_ppred,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_prs1_busy,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_prs2_busy,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_prs3_busy,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_ppred_busy,\t// @[issue-unit.scala:44:14]\n output [6:0] io_iss_uops_0_bits_stale_pdst,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_exception,\t// @[issue-unit.scala:44:14]\n output [63:0] io_iss_uops_0_bits_exc_cause,\t// @[issue-unit.scala:44:14]\n output [4:0] io_iss_uops_0_bits_mem_cmd,\t// @[issue-unit.scala:44:14]\n output [1:0] io_iss_uops_0_bits_mem_size,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_mem_signed,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_uses_ldq,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_uses_stq,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_is_unique,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_flush_on_commit,\t// @[issue-unit.scala:44:14]\n output [2:0] io_iss_uops_0_bits_csr_cmd,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_ldst_is_rs1,\t// @[issue-unit.scala:44:14]\n output [5:0] io_iss_uops_0_bits_ldst,\t// @[issue-unit.scala:44:14]\n output [5:0] io_iss_uops_0_bits_lrs1,\t// @[issue-unit.scala:44:14]\n output [5:0] io_iss_uops_0_bits_lrs2,\t// @[issue-unit.scala:44:14]\n output [5:0] io_iss_uops_0_bits_lrs3,\t// @[issue-unit.scala:44:14]\n output [1:0] io_iss_uops_0_bits_dst_rtype,\t// @[issue-unit.scala:44:14]\n output [1:0] io_iss_uops_0_bits_lrs1_rtype,\t// @[issue-unit.scala:44:14]\n output [1:0] io_iss_uops_0_bits_lrs2_rtype,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_frs3_en,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_fcn_dw,\t// @[issue-unit.scala:44:14]\n output [4:0] io_iss_uops_0_bits_fcn_op,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_fp_val,\t// @[issue-unit.scala:44:14]\n output [2:0] io_iss_uops_0_bits_fp_rm,\t// @[issue-unit.scala:44:14]\n output [1:0] io_iss_uops_0_bits_fp_typ,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_xcpt_pf_if,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_xcpt_ae_if,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_xcpt_ma_if,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_bp_debug_if,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_0_bits_bp_xcpt_if,\t// @[issue-unit.scala:44:14]\n output [2:0] io_iss_uops_0_bits_debug_fsrc,\t// @[issue-unit.scala:44:14]\n output [2:0] io_iss_uops_0_bits_debug_tsrc,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_valid,\t// @[issue-unit.scala:44:14]\n output [31:0] io_iss_uops_1_bits_inst,\t// @[issue-unit.scala:44:14]\n output [31:0] io_iss_uops_1_bits_debug_inst,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_is_rvc,\t// @[issue-unit.scala:44:14]\n output [39:0] io_iss_uops_1_bits_debug_pc,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_iq_type_0,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_iq_type_1,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_iq_type_2,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_iq_type_3,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_fu_code_0,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_fu_code_1,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_fu_code_2,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_fu_code_3,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_fu_code_4,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_fu_code_5,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_fu_code_6,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_fu_code_7,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_fu_code_8,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_fu_code_9,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_iw_issued,\t// @[issue-unit.scala:44:14]\n output [1:0] io_iss_uops_1_bits_iw_p1_speculative_child,\t// @[issue-unit.scala:44:14]\n output [1:0] io_iss_uops_1_bits_iw_p2_speculative_child,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_iw_p1_bypass_hint,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_iw_p2_bypass_hint,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_iw_p3_bypass_hint,\t// @[issue-unit.scala:44:14]\n output [1:0] io_iss_uops_1_bits_dis_col_sel,\t// @[issue-unit.scala:44:14]\n output [11:0] io_iss_uops_1_bits_br_mask,\t// @[issue-unit.scala:44:14]\n output [3:0] io_iss_uops_1_bits_br_tag,\t// @[issue-unit.scala:44:14]\n output [3:0] io_iss_uops_1_bits_br_type,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_is_sfb,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_is_fence,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_is_fencei,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_is_sfence,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_is_amo,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_is_eret,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_is_sys_pc2epc,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_is_rocc,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_is_mov,\t// @[issue-unit.scala:44:14]\n output [4:0] io_iss_uops_1_bits_ftq_idx,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_edge_inst,\t// @[issue-unit.scala:44:14]\n output [5:0] io_iss_uops_1_bits_pc_lob,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_taken,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_imm_rename,\t// @[issue-unit.scala:44:14]\n output [2:0] io_iss_uops_1_bits_imm_sel,\t// @[issue-unit.scala:44:14]\n output [4:0] io_iss_uops_1_bits_pimm,\t// @[issue-unit.scala:44:14]\n output [19:0] io_iss_uops_1_bits_imm_packed,\t// @[issue-unit.scala:44:14]\n output [1:0] io_iss_uops_1_bits_op1_sel,\t// @[issue-unit.scala:44:14]\n output [2:0] io_iss_uops_1_bits_op2_sel,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_fp_ctrl_ldst,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_fp_ctrl_wen,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_fp_ctrl_ren1,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_fp_ctrl_ren2,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_fp_ctrl_ren3,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_fp_ctrl_swap12,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_fp_ctrl_swap23,\t// @[issue-unit.scala:44:14]\n output [1:0] io_iss_uops_1_bits_fp_ctrl_typeTagIn,\t// @[issue-unit.scala:44:14]\n output [1:0] io_iss_uops_1_bits_fp_ctrl_typeTagOut,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_fp_ctrl_fromint,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_fp_ctrl_toint,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_fp_ctrl_fastpipe,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_fp_ctrl_fma,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_fp_ctrl_div,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_fp_ctrl_sqrt,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_fp_ctrl_wflags,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_fp_ctrl_vec,\t// @[issue-unit.scala:44:14]\n output [5:0] io_iss_uops_1_bits_rob_idx,\t// @[issue-unit.scala:44:14]\n output [3:0] io_iss_uops_1_bits_ldq_idx,\t// @[issue-unit.scala:44:14]\n output [3:0] io_iss_uops_1_bits_stq_idx,\t// @[issue-unit.scala:44:14]\n output [1:0] io_iss_uops_1_bits_rxq_idx,\t// @[issue-unit.scala:44:14]\n output [6:0] io_iss_uops_1_bits_pdst,\t// @[issue-unit.scala:44:14]\n output [6:0] io_iss_uops_1_bits_prs1,\t// @[issue-unit.scala:44:14]\n output [6:0] io_iss_uops_1_bits_prs2,\t// @[issue-unit.scala:44:14]\n output [6:0] io_iss_uops_1_bits_prs3,\t// @[issue-unit.scala:44:14]\n output [4:0] io_iss_uops_1_bits_ppred,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_prs1_busy,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_prs2_busy,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_prs3_busy,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_ppred_busy,\t// @[issue-unit.scala:44:14]\n output [6:0] io_iss_uops_1_bits_stale_pdst,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_exception,\t// @[issue-unit.scala:44:14]\n output [63:0] io_iss_uops_1_bits_exc_cause,\t// @[issue-unit.scala:44:14]\n output [4:0] io_iss_uops_1_bits_mem_cmd,\t// @[issue-unit.scala:44:14]\n output [1:0] io_iss_uops_1_bits_mem_size,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_mem_signed,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_uses_ldq,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_uses_stq,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_is_unique,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_flush_on_commit,\t// @[issue-unit.scala:44:14]\n output [2:0] io_iss_uops_1_bits_csr_cmd,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_ldst_is_rs1,\t// @[issue-unit.scala:44:14]\n output [5:0] io_iss_uops_1_bits_ldst,\t// @[issue-unit.scala:44:14]\n output [5:0] io_iss_uops_1_bits_lrs1,\t// @[issue-unit.scala:44:14]\n output [5:0] io_iss_uops_1_bits_lrs2,\t// @[issue-unit.scala:44:14]\n output [5:0] io_iss_uops_1_bits_lrs3,\t// @[issue-unit.scala:44:14]\n output [1:0] io_iss_uops_1_bits_dst_rtype,\t// @[issue-unit.scala:44:14]\n output [1:0] io_iss_uops_1_bits_lrs1_rtype,\t// @[issue-unit.scala:44:14]\n output [1:0] io_iss_uops_1_bits_lrs2_rtype,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_frs3_en,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_fcn_dw,\t// @[issue-unit.scala:44:14]\n output [4:0] io_iss_uops_1_bits_fcn_op,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_fp_val,\t// @[issue-unit.scala:44:14]\n output [2:0] io_iss_uops_1_bits_fp_rm,\t// @[issue-unit.scala:44:14]\n output [1:0] io_iss_uops_1_bits_fp_typ,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_xcpt_pf_if,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_xcpt_ae_if,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_xcpt_ma_if,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_bp_debug_if,\t// @[issue-unit.scala:44:14]\n output io_iss_uops_1_bits_bp_xcpt_if,\t// @[issue-unit.scala:44:14]\n output [2:0] io_iss_uops_1_bits_debug_fsrc,\t// @[issue-unit.scala:44:14]\n output [2:0] io_iss_uops_1_bits_debug_tsrc,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_valid,\t// @[issue-unit.scala:44:14]\n input [31:0] io_wakeup_ports_0_bits_uop_inst,\t// @[issue-unit.scala:44:14]\n input [31:0] io_wakeup_ports_0_bits_uop_debug_inst,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_is_rvc,\t// @[issue-unit.scala:44:14]\n input [39:0] io_wakeup_ports_0_bits_uop_debug_pc,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_iq_type_0,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_iq_type_1,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_iq_type_2,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_iq_type_3,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_fu_code_0,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_fu_code_1,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_fu_code_2,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_fu_code_3,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_fu_code_4,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_fu_code_5,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_fu_code_6,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_fu_code_7,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_fu_code_8,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_fu_code_9,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_iw_issued,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel,\t// @[issue-unit.scala:44:14]\n input [11:0] io_wakeup_ports_0_bits_uop_br_mask,\t// @[issue-unit.scala:44:14]\n input [3:0] io_wakeup_ports_0_bits_uop_br_tag,\t// @[issue-unit.scala:44:14]\n input [3:0] io_wakeup_ports_0_bits_uop_br_type,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_is_sfb,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_is_fence,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_is_fencei,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_is_sfence,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_is_amo,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_is_eret,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_is_sys_pc2epc,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_is_rocc,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_is_mov,\t// @[issue-unit.scala:44:14]\n input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_edge_inst,\t// @[issue-unit.scala:44:14]\n input [5:0] io_wakeup_ports_0_bits_uop_pc_lob,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_taken,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_imm_rename,\t// @[issue-unit.scala:44:14]\n input [2:0] io_wakeup_ports_0_bits_uop_imm_sel,\t// @[issue-unit.scala:44:14]\n input [4:0] io_wakeup_ports_0_bits_uop_pimm,\t// @[issue-unit.scala:44:14]\n input [19:0] io_wakeup_ports_0_bits_uop_imm_packed,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_0_bits_uop_op1_sel,\t// @[issue-unit.scala:44:14]\n input [2:0] io_wakeup_ports_0_bits_uop_op2_sel,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_fp_ctrl_wen,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_fp_ctrl_toint,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_fp_ctrl_fma,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_fp_ctrl_div,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_fp_ctrl_vec,\t// @[issue-unit.scala:44:14]\n input [5:0] io_wakeup_ports_0_bits_uop_rob_idx,\t// @[issue-unit.scala:44:14]\n input [3:0] io_wakeup_ports_0_bits_uop_ldq_idx,\t// @[issue-unit.scala:44:14]\n input [3:0] io_wakeup_ports_0_bits_uop_stq_idx,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx,\t// @[issue-unit.scala:44:14]\n input [6:0] io_wakeup_ports_0_bits_uop_pdst,\t// @[issue-unit.scala:44:14]\n input [6:0] io_wakeup_ports_0_bits_uop_prs1,\t// @[issue-unit.scala:44:14]\n input [6:0] io_wakeup_ports_0_bits_uop_prs2,\t// @[issue-unit.scala:44:14]\n input [6:0] io_wakeup_ports_0_bits_uop_prs3,\t// @[issue-unit.scala:44:14]\n input [4:0] io_wakeup_ports_0_bits_uop_ppred,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_prs1_busy,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_prs2_busy,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_prs3_busy,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_ppred_busy,\t// @[issue-unit.scala:44:14]\n input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_exception,\t// @[issue-unit.scala:44:14]\n input [63:0] io_wakeup_ports_0_bits_uop_exc_cause,\t// @[issue-unit.scala:44:14]\n input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_0_bits_uop_mem_size,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_mem_signed,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_uses_ldq,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_uses_stq,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_is_unique,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_flush_on_commit,\t// @[issue-unit.scala:44:14]\n input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_ldst_is_rs1,\t// @[issue-unit.scala:44:14]\n input [5:0] io_wakeup_ports_0_bits_uop_ldst,\t// @[issue-unit.scala:44:14]\n input [5:0] io_wakeup_ports_0_bits_uop_lrs1,\t// @[issue-unit.scala:44:14]\n input [5:0] io_wakeup_ports_0_bits_uop_lrs2,\t// @[issue-unit.scala:44:14]\n input [5:0] io_wakeup_ports_0_bits_uop_lrs3,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_frs3_en,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_fcn_dw,\t// @[issue-unit.scala:44:14]\n input [4:0] io_wakeup_ports_0_bits_uop_fcn_op,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_fp_val,\t// @[issue-unit.scala:44:14]\n input [2:0] io_wakeup_ports_0_bits_uop_fp_rm,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_0_bits_uop_fp_typ,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_xcpt_pf_if,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_xcpt_ae_if,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_xcpt_ma_if,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_bp_debug_if,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_uop_bp_xcpt_if,\t// @[issue-unit.scala:44:14]\n input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc,\t// @[issue-unit.scala:44:14]\n input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_bypassable,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_0_bits_speculative_mask,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_0_bits_rebusy,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_valid,\t// @[issue-unit.scala:44:14]\n input [31:0] io_wakeup_ports_1_bits_uop_inst,\t// @[issue-unit.scala:44:14]\n input [31:0] io_wakeup_ports_1_bits_uop_debug_inst,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_is_rvc,\t// @[issue-unit.scala:44:14]\n input [39:0] io_wakeup_ports_1_bits_uop_debug_pc,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_iq_type_0,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_iq_type_1,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_iq_type_2,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_iq_type_3,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_fu_code_0,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_fu_code_1,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_fu_code_2,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_fu_code_3,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_fu_code_4,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_fu_code_5,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_fu_code_6,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_fu_code_7,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_fu_code_8,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_fu_code_9,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_iw_issued,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel,\t// @[issue-unit.scala:44:14]\n input [11:0] io_wakeup_ports_1_bits_uop_br_mask,\t// @[issue-unit.scala:44:14]\n input [3:0] io_wakeup_ports_1_bits_uop_br_tag,\t// @[issue-unit.scala:44:14]\n input [3:0] io_wakeup_ports_1_bits_uop_br_type,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_is_sfb,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_is_fence,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_is_fencei,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_is_sfence,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_is_amo,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_is_eret,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_is_sys_pc2epc,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_is_rocc,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_is_mov,\t// @[issue-unit.scala:44:14]\n input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_edge_inst,\t// @[issue-unit.scala:44:14]\n input [5:0] io_wakeup_ports_1_bits_uop_pc_lob,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_taken,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_imm_rename,\t// @[issue-unit.scala:44:14]\n input [2:0] io_wakeup_ports_1_bits_uop_imm_sel,\t// @[issue-unit.scala:44:14]\n input [4:0] io_wakeup_ports_1_bits_uop_pimm,\t// @[issue-unit.scala:44:14]\n input [19:0] io_wakeup_ports_1_bits_uop_imm_packed,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_1_bits_uop_op1_sel,\t// @[issue-unit.scala:44:14]\n input [2:0] io_wakeup_ports_1_bits_uop_op2_sel,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_fp_ctrl_wen,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_fp_ctrl_toint,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_fp_ctrl_fma,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_fp_ctrl_div,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_fp_ctrl_vec,\t// @[issue-unit.scala:44:14]\n input [5:0] io_wakeup_ports_1_bits_uop_rob_idx,\t// @[issue-unit.scala:44:14]\n input [3:0] io_wakeup_ports_1_bits_uop_ldq_idx,\t// @[issue-unit.scala:44:14]\n input [3:0] io_wakeup_ports_1_bits_uop_stq_idx,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx,\t// @[issue-unit.scala:44:14]\n input [6:0] io_wakeup_ports_1_bits_uop_pdst,\t// @[issue-unit.scala:44:14]\n input [6:0] io_wakeup_ports_1_bits_uop_prs1,\t// @[issue-unit.scala:44:14]\n input [6:0] io_wakeup_ports_1_bits_uop_prs2,\t// @[issue-unit.scala:44:14]\n input [6:0] io_wakeup_ports_1_bits_uop_prs3,\t// @[issue-unit.scala:44:14]\n input [4:0] io_wakeup_ports_1_bits_uop_ppred,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_prs1_busy,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_prs2_busy,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_prs3_busy,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_ppred_busy,\t// @[issue-unit.scala:44:14]\n input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_exception,\t// @[issue-unit.scala:44:14]\n input [63:0] io_wakeup_ports_1_bits_uop_exc_cause,\t// @[issue-unit.scala:44:14]\n input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_1_bits_uop_mem_size,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_mem_signed,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_uses_ldq,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_uses_stq,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_is_unique,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_flush_on_commit,\t// @[issue-unit.scala:44:14]\n input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_ldst_is_rs1,\t// @[issue-unit.scala:44:14]\n input [5:0] io_wakeup_ports_1_bits_uop_ldst,\t// @[issue-unit.scala:44:14]\n input [5:0] io_wakeup_ports_1_bits_uop_lrs1,\t// @[issue-unit.scala:44:14]\n input [5:0] io_wakeup_ports_1_bits_uop_lrs2,\t// @[issue-unit.scala:44:14]\n input [5:0] io_wakeup_ports_1_bits_uop_lrs3,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_frs3_en,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_fcn_dw,\t// @[issue-unit.scala:44:14]\n input [4:0] io_wakeup_ports_1_bits_uop_fcn_op,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_fp_val,\t// @[issue-unit.scala:44:14]\n input [2:0] io_wakeup_ports_1_bits_uop_fp_rm,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_1_bits_uop_fp_typ,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_xcpt_pf_if,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_xcpt_ae_if,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_xcpt_ma_if,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_bp_debug_if,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_1_bits_uop_bp_xcpt_if,\t// @[issue-unit.scala:44:14]\n input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc,\t// @[issue-unit.scala:44:14]\n input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_valid,\t// @[issue-unit.scala:44:14]\n input [31:0] io_wakeup_ports_2_bits_uop_inst,\t// @[issue-unit.scala:44:14]\n input [31:0] io_wakeup_ports_2_bits_uop_debug_inst,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_is_rvc,\t// @[issue-unit.scala:44:14]\n input [39:0] io_wakeup_ports_2_bits_uop_debug_pc,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_iq_type_0,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_iq_type_1,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_iq_type_2,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_iq_type_3,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_fu_code_0,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_fu_code_1,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_fu_code_2,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_fu_code_3,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_fu_code_4,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_fu_code_5,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_fu_code_6,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_fu_code_7,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_fu_code_8,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_fu_code_9,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_iw_issued,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel,\t// @[issue-unit.scala:44:14]\n input [11:0] io_wakeup_ports_2_bits_uop_br_mask,\t// @[issue-unit.scala:44:14]\n input [3:0] io_wakeup_ports_2_bits_uop_br_tag,\t// @[issue-unit.scala:44:14]\n input [3:0] io_wakeup_ports_2_bits_uop_br_type,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_is_sfb,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_is_fence,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_is_fencei,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_is_sfence,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_is_amo,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_is_eret,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_is_sys_pc2epc,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_is_rocc,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_is_mov,\t// @[issue-unit.scala:44:14]\n input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_edge_inst,\t// @[issue-unit.scala:44:14]\n input [5:0] io_wakeup_ports_2_bits_uop_pc_lob,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_taken,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_imm_rename,\t// @[issue-unit.scala:44:14]\n input [2:0] io_wakeup_ports_2_bits_uop_imm_sel,\t// @[issue-unit.scala:44:14]\n input [4:0] io_wakeup_ports_2_bits_uop_pimm,\t// @[issue-unit.scala:44:14]\n input [19:0] io_wakeup_ports_2_bits_uop_imm_packed,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_2_bits_uop_op1_sel,\t// @[issue-unit.scala:44:14]\n input [2:0] io_wakeup_ports_2_bits_uop_op2_sel,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_fp_ctrl_wen,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_fp_ctrl_toint,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_fp_ctrl_fma,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_fp_ctrl_div,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_fp_ctrl_vec,\t// @[issue-unit.scala:44:14]\n input [5:0] io_wakeup_ports_2_bits_uop_rob_idx,\t// @[issue-unit.scala:44:14]\n input [3:0] io_wakeup_ports_2_bits_uop_ldq_idx,\t// @[issue-unit.scala:44:14]\n input [3:0] io_wakeup_ports_2_bits_uop_stq_idx,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx,\t// @[issue-unit.scala:44:14]\n input [6:0] io_wakeup_ports_2_bits_uop_pdst,\t// @[issue-unit.scala:44:14]\n input [6:0] io_wakeup_ports_2_bits_uop_prs1,\t// @[issue-unit.scala:44:14]\n input [6:0] io_wakeup_ports_2_bits_uop_prs2,\t// @[issue-unit.scala:44:14]\n input [6:0] io_wakeup_ports_2_bits_uop_prs3,\t// @[issue-unit.scala:44:14]\n input [4:0] io_wakeup_ports_2_bits_uop_ppred,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_prs1_busy,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_prs2_busy,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_prs3_busy,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_ppred_busy,\t// @[issue-unit.scala:44:14]\n input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_exception,\t// @[issue-unit.scala:44:14]\n input [63:0] io_wakeup_ports_2_bits_uop_exc_cause,\t// @[issue-unit.scala:44:14]\n input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_2_bits_uop_mem_size,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_mem_signed,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_uses_ldq,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_uses_stq,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_is_unique,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_flush_on_commit,\t// @[issue-unit.scala:44:14]\n input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_ldst_is_rs1,\t// @[issue-unit.scala:44:14]\n input [5:0] io_wakeup_ports_2_bits_uop_ldst,\t// @[issue-unit.scala:44:14]\n input [5:0] io_wakeup_ports_2_bits_uop_lrs1,\t// @[issue-unit.scala:44:14]\n input [5:0] io_wakeup_ports_2_bits_uop_lrs2,\t// @[issue-unit.scala:44:14]\n input [5:0] io_wakeup_ports_2_bits_uop_lrs3,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_frs3_en,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_fcn_dw,\t// @[issue-unit.scala:44:14]\n input [4:0] io_wakeup_ports_2_bits_uop_fcn_op,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_fp_val,\t// @[issue-unit.scala:44:14]\n input [2:0] io_wakeup_ports_2_bits_uop_fp_rm,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_2_bits_uop_fp_typ,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_xcpt_pf_if,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_xcpt_ae_if,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_xcpt_ma_if,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_bp_debug_if,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_2_bits_uop_bp_xcpt_if,\t// @[issue-unit.scala:44:14]\n input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc,\t// @[issue-unit.scala:44:14]\n input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_valid,\t// @[issue-unit.scala:44:14]\n input [31:0] io_wakeup_ports_3_bits_uop_inst,\t// @[issue-unit.scala:44:14]\n input [31:0] io_wakeup_ports_3_bits_uop_debug_inst,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_is_rvc,\t// @[issue-unit.scala:44:14]\n input [39:0] io_wakeup_ports_3_bits_uop_debug_pc,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_iq_type_0,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_iq_type_1,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_iq_type_2,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_iq_type_3,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_fu_code_0,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_fu_code_1,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_fu_code_2,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_fu_code_3,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_fu_code_4,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_fu_code_5,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_fu_code_6,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_fu_code_7,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_fu_code_8,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_fu_code_9,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_iw_issued,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel,\t// @[issue-unit.scala:44:14]\n input [11:0] io_wakeup_ports_3_bits_uop_br_mask,\t// @[issue-unit.scala:44:14]\n input [3:0] io_wakeup_ports_3_bits_uop_br_tag,\t// @[issue-unit.scala:44:14]\n input [3:0] io_wakeup_ports_3_bits_uop_br_type,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_is_sfb,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_is_fence,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_is_fencei,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_is_sfence,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_is_amo,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_is_eret,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_is_sys_pc2epc,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_is_rocc,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_is_mov,\t// @[issue-unit.scala:44:14]\n input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_edge_inst,\t// @[issue-unit.scala:44:14]\n input [5:0] io_wakeup_ports_3_bits_uop_pc_lob,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_taken,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_imm_rename,\t// @[issue-unit.scala:44:14]\n input [2:0] io_wakeup_ports_3_bits_uop_imm_sel,\t// @[issue-unit.scala:44:14]\n input [4:0] io_wakeup_ports_3_bits_uop_pimm,\t// @[issue-unit.scala:44:14]\n input [19:0] io_wakeup_ports_3_bits_uop_imm_packed,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_3_bits_uop_op1_sel,\t// @[issue-unit.scala:44:14]\n input [2:0] io_wakeup_ports_3_bits_uop_op2_sel,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_fp_ctrl_wen,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_fp_ctrl_toint,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_fp_ctrl_fma,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_fp_ctrl_div,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_fp_ctrl_vec,\t// @[issue-unit.scala:44:14]\n input [5:0] io_wakeup_ports_3_bits_uop_rob_idx,\t// @[issue-unit.scala:44:14]\n input [3:0] io_wakeup_ports_3_bits_uop_ldq_idx,\t// @[issue-unit.scala:44:14]\n input [3:0] io_wakeup_ports_3_bits_uop_stq_idx,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx,\t// @[issue-unit.scala:44:14]\n input [6:0] io_wakeup_ports_3_bits_uop_pdst,\t// @[issue-unit.scala:44:14]\n input [6:0] io_wakeup_ports_3_bits_uop_prs1,\t// @[issue-unit.scala:44:14]\n input [6:0] io_wakeup_ports_3_bits_uop_prs2,\t// @[issue-unit.scala:44:14]\n input [6:0] io_wakeup_ports_3_bits_uop_prs3,\t// @[issue-unit.scala:44:14]\n input [4:0] io_wakeup_ports_3_bits_uop_ppred,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_prs1_busy,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_prs2_busy,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_prs3_busy,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_ppred_busy,\t// @[issue-unit.scala:44:14]\n input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_exception,\t// @[issue-unit.scala:44:14]\n input [63:0] io_wakeup_ports_3_bits_uop_exc_cause,\t// @[issue-unit.scala:44:14]\n input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_3_bits_uop_mem_size,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_mem_signed,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_uses_ldq,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_uses_stq,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_is_unique,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_flush_on_commit,\t// @[issue-unit.scala:44:14]\n input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_ldst_is_rs1,\t// @[issue-unit.scala:44:14]\n input [5:0] io_wakeup_ports_3_bits_uop_ldst,\t// @[issue-unit.scala:44:14]\n input [5:0] io_wakeup_ports_3_bits_uop_lrs1,\t// @[issue-unit.scala:44:14]\n input [5:0] io_wakeup_ports_3_bits_uop_lrs2,\t// @[issue-unit.scala:44:14]\n input [5:0] io_wakeup_ports_3_bits_uop_lrs3,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_frs3_en,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_fcn_dw,\t// @[issue-unit.scala:44:14]\n input [4:0] io_wakeup_ports_3_bits_uop_fcn_op,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_fp_val,\t// @[issue-unit.scala:44:14]\n input [2:0] io_wakeup_ports_3_bits_uop_fp_rm,\t// @[issue-unit.scala:44:14]\n input [1:0] io_wakeup_ports_3_bits_uop_fp_typ,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_xcpt_pf_if,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_xcpt_ae_if,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_xcpt_ma_if,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_bp_debug_if,\t// @[issue-unit.scala:44:14]\n input io_wakeup_ports_3_bits_uop_bp_xcpt_if,\t// @[issue-unit.scala:44:14]\n input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc,\t// @[issue-unit.scala:44:14]\n input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc,\t// @[issue-unit.scala:44:14]\n input io_pred_wakeup_port_valid,\t// @[issue-unit.scala:44:14]\n input [4:0] io_pred_wakeup_port_bits,\t// @[issue-unit.scala:44:14]\n input [1:0] io_child_rebusys,\t// @[issue-unit.scala:44:14]\n input [11:0] io_brupdate_b1_resolve_mask,\t// @[issue-unit.scala:44:14]\n input [11:0] io_brupdate_b1_mispredict_mask,\t// @[issue-unit.scala:44:14]\n input [31:0] io_brupdate_b2_uop_inst,\t// @[issue-unit.scala:44:14]\n input [31:0] io_brupdate_b2_uop_debug_inst,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_is_rvc,\t// @[issue-unit.scala:44:14]\n input [39:0] io_brupdate_b2_uop_debug_pc,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_iq_type_0,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_iq_type_1,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_iq_type_2,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_iq_type_3,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_fu_code_0,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_fu_code_1,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_fu_code_2,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_fu_code_3,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_fu_code_4,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_fu_code_5,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_fu_code_6,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_fu_code_7,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_fu_code_8,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_fu_code_9,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_iw_issued,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_iw_issued_partial_agen,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_iw_issued_partial_dgen,\t// @[issue-unit.scala:44:14]\n input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child,\t// @[issue-unit.scala:44:14]\n input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_iw_p1_bypass_hint,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_iw_p2_bypass_hint,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_iw_p3_bypass_hint,\t// @[issue-unit.scala:44:14]\n input [1:0] io_brupdate_b2_uop_dis_col_sel,\t// @[issue-unit.scala:44:14]\n input [11:0] io_brupdate_b2_uop_br_mask,\t// @[issue-unit.scala:44:14]\n input [3:0] io_brupdate_b2_uop_br_tag,\t// @[issue-unit.scala:44:14]\n input [3:0] io_brupdate_b2_uop_br_type,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_is_sfb,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_is_fence,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_is_fencei,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_is_sfence,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_is_amo,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_is_eret,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_is_sys_pc2epc,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_is_rocc,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_is_mov,\t// @[issue-unit.scala:44:14]\n input [4:0] io_brupdate_b2_uop_ftq_idx,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_edge_inst,\t// @[issue-unit.scala:44:14]\n input [5:0] io_brupdate_b2_uop_pc_lob,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_taken,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_imm_rename,\t// @[issue-unit.scala:44:14]\n input [2:0] io_brupdate_b2_uop_imm_sel,\t// @[issue-unit.scala:44:14]\n input [4:0] io_brupdate_b2_uop_pimm,\t// @[issue-unit.scala:44:14]\n input [19:0] io_brupdate_b2_uop_imm_packed,\t// @[issue-unit.scala:44:14]\n input [1:0] io_brupdate_b2_uop_op1_sel,\t// @[issue-unit.scala:44:14]\n input [2:0] io_brupdate_b2_uop_op2_sel,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_fp_ctrl_ldst,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_fp_ctrl_wen,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_fp_ctrl_ren1,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_fp_ctrl_ren2,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_fp_ctrl_ren3,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_fp_ctrl_swap12,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_fp_ctrl_swap23,\t// @[issue-unit.scala:44:14]\n input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn,\t// @[issue-unit.scala:44:14]\n input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_fp_ctrl_fromint,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_fp_ctrl_toint,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_fp_ctrl_fastpipe,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_fp_ctrl_fma,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_fp_ctrl_div,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_fp_ctrl_sqrt,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_fp_ctrl_wflags,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_fp_ctrl_vec,\t// @[issue-unit.scala:44:14]\n input [5:0] io_brupdate_b2_uop_rob_idx,\t// @[issue-unit.scala:44:14]\n input [3:0] io_brupdate_b2_uop_ldq_idx,\t// @[issue-unit.scala:44:14]\n input [3:0] io_brupdate_b2_uop_stq_idx,\t// @[issue-unit.scala:44:14]\n input [1:0] io_brupdate_b2_uop_rxq_idx,\t// @[issue-unit.scala:44:14]\n input [6:0] io_brupdate_b2_uop_pdst,\t// @[issue-unit.scala:44:14]\n input [6:0] io_brupdate_b2_uop_prs1,\t// @[issue-unit.scala:44:14]\n input [6:0] io_brupdate_b2_uop_prs2,\t// @[issue-unit.scala:44:14]\n input [6:0] io_brupdate_b2_uop_prs3,\t// @[issue-unit.scala:44:14]\n input [4:0] io_brupdate_b2_uop_ppred,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_prs1_busy,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_prs2_busy,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_prs3_busy,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_ppred_busy,\t// @[issue-unit.scala:44:14]\n input [6:0] io_brupdate_b2_uop_stale_pdst,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_exception,\t// @[issue-unit.scala:44:14]\n input [63:0] io_brupdate_b2_uop_exc_cause,\t// @[issue-unit.scala:44:14]\n input [4:0] io_brupdate_b2_uop_mem_cmd,\t// @[issue-unit.scala:44:14]\n input [1:0] io_brupdate_b2_uop_mem_size,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_mem_signed,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_uses_ldq,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_uses_stq,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_is_unique,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_flush_on_commit,\t// @[issue-unit.scala:44:14]\n input [2:0] io_brupdate_b2_uop_csr_cmd,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_ldst_is_rs1,\t// @[issue-unit.scala:44:14]\n input [5:0] io_brupdate_b2_uop_ldst,\t// @[issue-unit.scala:44:14]\n input [5:0] io_brupdate_b2_uop_lrs1,\t// @[issue-unit.scala:44:14]\n input [5:0] io_brupdate_b2_uop_lrs2,\t// @[issue-unit.scala:44:14]\n input [5:0] io_brupdate_b2_uop_lrs3,\t// @[issue-unit.scala:44:14]\n input [1:0] io_brupdate_b2_uop_dst_rtype,\t// @[issue-unit.scala:44:14]\n input [1:0] io_brupdate_b2_uop_lrs1_rtype,\t// @[issue-unit.scala:44:14]\n input [1:0] io_brupdate_b2_uop_lrs2_rtype,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_frs3_en,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_fcn_dw,\t// @[issue-unit.scala:44:14]\n input [4:0] io_brupdate_b2_uop_fcn_op,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_fp_val,\t// @[issue-unit.scala:44:14]\n input [2:0] io_brupdate_b2_uop_fp_rm,\t// @[issue-unit.scala:44:14]\n input [1:0] io_brupdate_b2_uop_fp_typ,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_xcpt_pf_if,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_xcpt_ae_if,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_xcpt_ma_if,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_bp_debug_if,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_uop_bp_xcpt_if,\t// @[issue-unit.scala:44:14]\n input [2:0] io_brupdate_b2_uop_debug_fsrc,\t// @[issue-unit.scala:44:14]\n input [2:0] io_brupdate_b2_uop_debug_tsrc,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_mispredict,\t// @[issue-unit.scala:44:14]\n input io_brupdate_b2_taken,\t// @[issue-unit.scala:44:14]\n input [2:0] io_brupdate_b2_cfi_type,\t// @[issue-unit.scala:44:14]\n input [1:0] io_brupdate_b2_pc_sel,\t// @[issue-unit.scala:44:14]\n input [39:0] io_brupdate_b2_jalr_target,\t// @[issue-unit.scala:44:14]\n input [20:0] io_brupdate_b2_target_offset,\t// @[issue-unit.scala:44:14]\n input io_flush_pipeline,\t// @[issue-unit.scala:44:14]\n input io_squash_grant,\t// @[issue-unit.scala:44:14]\n input [63:0] io_tsc_reg\t// @[issue-unit.scala:44:14]\n);\n\n wire issue_slots_19_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire io_dis_uops_0_valid_0 = io_dis_uops_0_valid;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [31:0] io_dis_uops_0_bits_inst_0 = io_dis_uops_0_bits_inst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [31:0] io_dis_uops_0_bits_debug_inst_0 = io_dis_uops_0_bits_debug_inst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_is_rvc_0 = io_dis_uops_0_bits_is_rvc;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [39:0] io_dis_uops_0_bits_debug_pc_0 = io_dis_uops_0_bits_debug_pc;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_iq_type_0_0 = io_dis_uops_0_bits_iq_type_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_iq_type_1_0 = io_dis_uops_0_bits_iq_type_1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_iq_type_2_0 = io_dis_uops_0_bits_iq_type_2;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_iq_type_3_0 = io_dis_uops_0_bits_iq_type_3;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_fu_code_0_0 = io_dis_uops_0_bits_fu_code_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_fu_code_1_0 = io_dis_uops_0_bits_fu_code_1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_fu_code_2_0 = io_dis_uops_0_bits_fu_code_2;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_fu_code_3_0 = io_dis_uops_0_bits_fu_code_3;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_fu_code_4_0 = io_dis_uops_0_bits_fu_code_4;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_fu_code_5_0 = io_dis_uops_0_bits_fu_code_5;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_fu_code_6_0 = io_dis_uops_0_bits_fu_code_6;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_fu_code_7_0 = io_dis_uops_0_bits_fu_code_7;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_fu_code_8_0 = io_dis_uops_0_bits_fu_code_8;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_fu_code_9_0 = io_dis_uops_0_bits_fu_code_9;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_iw_issued_0 = io_dis_uops_0_bits_iw_issued;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_iw_issued_partial_agen_0 = io_dis_uops_0_bits_iw_issued_partial_agen;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_iw_issued_partial_dgen_0 = io_dis_uops_0_bits_iw_issued_partial_dgen;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_dis_uops_0_bits_iw_p1_speculative_child_0 = io_dis_uops_0_bits_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_dis_uops_0_bits_iw_p2_speculative_child_0 = io_dis_uops_0_bits_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_iw_p1_bypass_hint_0 = io_dis_uops_0_bits_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_iw_p2_bypass_hint_0 = io_dis_uops_0_bits_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_iw_p3_bypass_hint_0 = io_dis_uops_0_bits_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_dis_uops_0_bits_dis_col_sel_0 = io_dis_uops_0_bits_dis_col_sel;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [11:0] io_dis_uops_0_bits_br_mask_0 = io_dis_uops_0_bits_br_mask;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [3:0] io_dis_uops_0_bits_br_tag_0 = io_dis_uops_0_bits_br_tag;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [3:0] io_dis_uops_0_bits_br_type_0 = io_dis_uops_0_bits_br_type;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_is_sfb_0 = io_dis_uops_0_bits_is_sfb;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_is_fence_0 = io_dis_uops_0_bits_is_fence;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_is_fencei_0 = io_dis_uops_0_bits_is_fencei;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_is_sfence_0 = io_dis_uops_0_bits_is_sfence;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_is_amo_0 = io_dis_uops_0_bits_is_amo;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_is_eret_0 = io_dis_uops_0_bits_is_eret;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_is_sys_pc2epc_0 = io_dis_uops_0_bits_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_is_rocc_0 = io_dis_uops_0_bits_is_rocc;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_is_mov_0 = io_dis_uops_0_bits_is_mov;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_dis_uops_0_bits_ftq_idx_0 = io_dis_uops_0_bits_ftq_idx;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_edge_inst_0 = io_dis_uops_0_bits_edge_inst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_dis_uops_0_bits_pc_lob_0 = io_dis_uops_0_bits_pc_lob;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_taken_0 = io_dis_uops_0_bits_taken;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_imm_rename_0 = io_dis_uops_0_bits_imm_rename;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_dis_uops_0_bits_imm_sel_0 = io_dis_uops_0_bits_imm_sel;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_dis_uops_0_bits_pimm_0 = io_dis_uops_0_bits_pimm;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [19:0] io_dis_uops_0_bits_imm_packed_0 = io_dis_uops_0_bits_imm_packed;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_dis_uops_0_bits_op1_sel_0 = io_dis_uops_0_bits_op1_sel;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_dis_uops_0_bits_op2_sel_0 = io_dis_uops_0_bits_op2_sel;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_fp_ctrl_ldst_0 = io_dis_uops_0_bits_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_fp_ctrl_wen_0 = io_dis_uops_0_bits_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_fp_ctrl_ren1_0 = io_dis_uops_0_bits_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_fp_ctrl_ren2_0 = io_dis_uops_0_bits_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_fp_ctrl_ren3_0 = io_dis_uops_0_bits_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_fp_ctrl_swap12_0 = io_dis_uops_0_bits_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_fp_ctrl_swap23_0 = io_dis_uops_0_bits_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_dis_uops_0_bits_fp_ctrl_typeTagIn_0 = io_dis_uops_0_bits_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_dis_uops_0_bits_fp_ctrl_typeTagOut_0 = io_dis_uops_0_bits_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_fp_ctrl_fromint_0 = io_dis_uops_0_bits_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_fp_ctrl_toint_0 = io_dis_uops_0_bits_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_fp_ctrl_fastpipe_0 = io_dis_uops_0_bits_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_fp_ctrl_fma_0 = io_dis_uops_0_bits_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_fp_ctrl_div_0 = io_dis_uops_0_bits_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_fp_ctrl_sqrt_0 = io_dis_uops_0_bits_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_fp_ctrl_wflags_0 = io_dis_uops_0_bits_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_fp_ctrl_vec_0 = io_dis_uops_0_bits_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_dis_uops_0_bits_rob_idx_0 = io_dis_uops_0_bits_rob_idx;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [3:0] io_dis_uops_0_bits_ldq_idx_0 = io_dis_uops_0_bits_ldq_idx;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [3:0] io_dis_uops_0_bits_stq_idx_0 = io_dis_uops_0_bits_stq_idx;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_dis_uops_0_bits_rxq_idx_0 = io_dis_uops_0_bits_rxq_idx;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_dis_uops_0_bits_pdst_0 = io_dis_uops_0_bits_pdst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_dis_uops_0_bits_prs1_0 = io_dis_uops_0_bits_prs1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_dis_uops_0_bits_prs2_0 = io_dis_uops_0_bits_prs2;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_dis_uops_0_bits_prs3_0 = io_dis_uops_0_bits_prs3;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_dis_uops_0_bits_ppred_0 = io_dis_uops_0_bits_ppred;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_prs1_busy_0 = io_dis_uops_0_bits_prs1_busy;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_prs2_busy_0 = io_dis_uops_0_bits_prs2_busy;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_prs3_busy_0 = io_dis_uops_0_bits_prs3_busy;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_ppred_busy_0 = io_dis_uops_0_bits_ppred_busy;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_dis_uops_0_bits_stale_pdst_0 = io_dis_uops_0_bits_stale_pdst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_exception_0 = io_dis_uops_0_bits_exception;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [63:0] io_dis_uops_0_bits_exc_cause_0 = io_dis_uops_0_bits_exc_cause;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_dis_uops_0_bits_mem_cmd_0 = io_dis_uops_0_bits_mem_cmd;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_dis_uops_0_bits_mem_size_0 = io_dis_uops_0_bits_mem_size;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_mem_signed_0 = io_dis_uops_0_bits_mem_signed;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_uses_ldq_0 = io_dis_uops_0_bits_uses_ldq;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_uses_stq_0 = io_dis_uops_0_bits_uses_stq;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_is_unique_0 = io_dis_uops_0_bits_is_unique;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_flush_on_commit_0 = io_dis_uops_0_bits_flush_on_commit;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_dis_uops_0_bits_csr_cmd_0 = io_dis_uops_0_bits_csr_cmd;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_ldst_is_rs1_0 = io_dis_uops_0_bits_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_dis_uops_0_bits_ldst_0 = io_dis_uops_0_bits_ldst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_dis_uops_0_bits_lrs1_0 = io_dis_uops_0_bits_lrs1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_dis_uops_0_bits_lrs2_0 = io_dis_uops_0_bits_lrs2;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_dis_uops_0_bits_lrs3_0 = io_dis_uops_0_bits_lrs3;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_dis_uops_0_bits_dst_rtype_0 = io_dis_uops_0_bits_dst_rtype;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_dis_uops_0_bits_lrs1_rtype_0 = io_dis_uops_0_bits_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_dis_uops_0_bits_lrs2_rtype_0 = io_dis_uops_0_bits_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_frs3_en_0 = io_dis_uops_0_bits_frs3_en;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_fcn_dw_0 = io_dis_uops_0_bits_fcn_dw;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_dis_uops_0_bits_fcn_op_0 = io_dis_uops_0_bits_fcn_op;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_fp_val_0 = io_dis_uops_0_bits_fp_val;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_dis_uops_0_bits_fp_rm_0 = io_dis_uops_0_bits_fp_rm;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_dis_uops_0_bits_fp_typ_0 = io_dis_uops_0_bits_fp_typ;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_xcpt_pf_if_0 = io_dis_uops_0_bits_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_xcpt_ae_if_0 = io_dis_uops_0_bits_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_xcpt_ma_if_0 = io_dis_uops_0_bits_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_bp_debug_if_0 = io_dis_uops_0_bits_bp_debug_if;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_0_bits_bp_xcpt_if_0 = io_dis_uops_0_bits_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_dis_uops_0_bits_debug_fsrc_0 = io_dis_uops_0_bits_debug_fsrc;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_dis_uops_0_bits_debug_tsrc_0 = io_dis_uops_0_bits_debug_tsrc;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_valid_0 = io_dis_uops_1_valid;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [31:0] io_dis_uops_1_bits_inst_0 = io_dis_uops_1_bits_inst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [31:0] io_dis_uops_1_bits_debug_inst_0 = io_dis_uops_1_bits_debug_inst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_is_rvc_0 = io_dis_uops_1_bits_is_rvc;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [39:0] io_dis_uops_1_bits_debug_pc_0 = io_dis_uops_1_bits_debug_pc;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_iq_type_0_0 = io_dis_uops_1_bits_iq_type_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_iq_type_1_0 = io_dis_uops_1_bits_iq_type_1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_iq_type_2_0 = io_dis_uops_1_bits_iq_type_2;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_iq_type_3_0 = io_dis_uops_1_bits_iq_type_3;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_fu_code_0_0 = io_dis_uops_1_bits_fu_code_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_fu_code_1_0 = io_dis_uops_1_bits_fu_code_1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_fu_code_2_0 = io_dis_uops_1_bits_fu_code_2;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_fu_code_3_0 = io_dis_uops_1_bits_fu_code_3;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_fu_code_4_0 = io_dis_uops_1_bits_fu_code_4;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_fu_code_5_0 = io_dis_uops_1_bits_fu_code_5;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_fu_code_6_0 = io_dis_uops_1_bits_fu_code_6;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_fu_code_7_0 = io_dis_uops_1_bits_fu_code_7;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_fu_code_8_0 = io_dis_uops_1_bits_fu_code_8;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_fu_code_9_0 = io_dis_uops_1_bits_fu_code_9;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_iw_issued_0 = io_dis_uops_1_bits_iw_issued;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_iw_issued_partial_agen_0 = io_dis_uops_1_bits_iw_issued_partial_agen;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_iw_issued_partial_dgen_0 = io_dis_uops_1_bits_iw_issued_partial_dgen;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_dis_uops_1_bits_iw_p1_speculative_child_0 = io_dis_uops_1_bits_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_dis_uops_1_bits_iw_p2_speculative_child_0 = io_dis_uops_1_bits_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_iw_p1_bypass_hint_0 = io_dis_uops_1_bits_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_iw_p2_bypass_hint_0 = io_dis_uops_1_bits_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_iw_p3_bypass_hint_0 = io_dis_uops_1_bits_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_dis_uops_1_bits_dis_col_sel_0 = io_dis_uops_1_bits_dis_col_sel;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [11:0] io_dis_uops_1_bits_br_mask_0 = io_dis_uops_1_bits_br_mask;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [3:0] io_dis_uops_1_bits_br_tag_0 = io_dis_uops_1_bits_br_tag;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [3:0] io_dis_uops_1_bits_br_type_0 = io_dis_uops_1_bits_br_type;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_is_sfb_0 = io_dis_uops_1_bits_is_sfb;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_is_fence_0 = io_dis_uops_1_bits_is_fence;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_is_fencei_0 = io_dis_uops_1_bits_is_fencei;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_is_sfence_0 = io_dis_uops_1_bits_is_sfence;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_is_amo_0 = io_dis_uops_1_bits_is_amo;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_is_eret_0 = io_dis_uops_1_bits_is_eret;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_is_sys_pc2epc_0 = io_dis_uops_1_bits_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_is_rocc_0 = io_dis_uops_1_bits_is_rocc;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_is_mov_0 = io_dis_uops_1_bits_is_mov;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_dis_uops_1_bits_ftq_idx_0 = io_dis_uops_1_bits_ftq_idx;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_edge_inst_0 = io_dis_uops_1_bits_edge_inst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_dis_uops_1_bits_pc_lob_0 = io_dis_uops_1_bits_pc_lob;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_taken_0 = io_dis_uops_1_bits_taken;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_imm_rename_0 = io_dis_uops_1_bits_imm_rename;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_dis_uops_1_bits_imm_sel_0 = io_dis_uops_1_bits_imm_sel;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_dis_uops_1_bits_pimm_0 = io_dis_uops_1_bits_pimm;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [19:0] io_dis_uops_1_bits_imm_packed_0 = io_dis_uops_1_bits_imm_packed;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_dis_uops_1_bits_op1_sel_0 = io_dis_uops_1_bits_op1_sel;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_dis_uops_1_bits_op2_sel_0 = io_dis_uops_1_bits_op2_sel;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_fp_ctrl_ldst_0 = io_dis_uops_1_bits_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_fp_ctrl_wen_0 = io_dis_uops_1_bits_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_fp_ctrl_ren1_0 = io_dis_uops_1_bits_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_fp_ctrl_ren2_0 = io_dis_uops_1_bits_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_fp_ctrl_ren3_0 = io_dis_uops_1_bits_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_fp_ctrl_swap12_0 = io_dis_uops_1_bits_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_fp_ctrl_swap23_0 = io_dis_uops_1_bits_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_dis_uops_1_bits_fp_ctrl_typeTagIn_0 = io_dis_uops_1_bits_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_dis_uops_1_bits_fp_ctrl_typeTagOut_0 = io_dis_uops_1_bits_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_fp_ctrl_fromint_0 = io_dis_uops_1_bits_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_fp_ctrl_toint_0 = io_dis_uops_1_bits_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_fp_ctrl_fastpipe_0 = io_dis_uops_1_bits_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_fp_ctrl_fma_0 = io_dis_uops_1_bits_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_fp_ctrl_div_0 = io_dis_uops_1_bits_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_fp_ctrl_sqrt_0 = io_dis_uops_1_bits_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_fp_ctrl_wflags_0 = io_dis_uops_1_bits_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_fp_ctrl_vec_0 = io_dis_uops_1_bits_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_dis_uops_1_bits_rob_idx_0 = io_dis_uops_1_bits_rob_idx;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [3:0] io_dis_uops_1_bits_ldq_idx_0 = io_dis_uops_1_bits_ldq_idx;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [3:0] io_dis_uops_1_bits_stq_idx_0 = io_dis_uops_1_bits_stq_idx;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_dis_uops_1_bits_rxq_idx_0 = io_dis_uops_1_bits_rxq_idx;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_dis_uops_1_bits_pdst_0 = io_dis_uops_1_bits_pdst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_dis_uops_1_bits_prs1_0 = io_dis_uops_1_bits_prs1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_dis_uops_1_bits_prs2_0 = io_dis_uops_1_bits_prs2;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_dis_uops_1_bits_prs3_0 = io_dis_uops_1_bits_prs3;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_dis_uops_1_bits_ppred_0 = io_dis_uops_1_bits_ppred;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_prs1_busy_0 = io_dis_uops_1_bits_prs1_busy;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_prs2_busy_0 = io_dis_uops_1_bits_prs2_busy;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_prs3_busy_0 = io_dis_uops_1_bits_prs3_busy;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_ppred_busy_0 = io_dis_uops_1_bits_ppred_busy;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_dis_uops_1_bits_stale_pdst_0 = io_dis_uops_1_bits_stale_pdst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_exception_0 = io_dis_uops_1_bits_exception;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [63:0] io_dis_uops_1_bits_exc_cause_0 = io_dis_uops_1_bits_exc_cause;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_dis_uops_1_bits_mem_cmd_0 = io_dis_uops_1_bits_mem_cmd;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_dis_uops_1_bits_mem_size_0 = io_dis_uops_1_bits_mem_size;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_mem_signed_0 = io_dis_uops_1_bits_mem_signed;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_uses_ldq_0 = io_dis_uops_1_bits_uses_ldq;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_uses_stq_0 = io_dis_uops_1_bits_uses_stq;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_is_unique_0 = io_dis_uops_1_bits_is_unique;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_flush_on_commit_0 = io_dis_uops_1_bits_flush_on_commit;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_dis_uops_1_bits_csr_cmd_0 = io_dis_uops_1_bits_csr_cmd;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_ldst_is_rs1_0 = io_dis_uops_1_bits_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_dis_uops_1_bits_ldst_0 = io_dis_uops_1_bits_ldst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_dis_uops_1_bits_lrs1_0 = io_dis_uops_1_bits_lrs1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_dis_uops_1_bits_lrs2_0 = io_dis_uops_1_bits_lrs2;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_dis_uops_1_bits_lrs3_0 = io_dis_uops_1_bits_lrs3;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_dis_uops_1_bits_dst_rtype_0 = io_dis_uops_1_bits_dst_rtype;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_dis_uops_1_bits_lrs1_rtype_0 = io_dis_uops_1_bits_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_dis_uops_1_bits_lrs2_rtype_0 = io_dis_uops_1_bits_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_frs3_en_0 = io_dis_uops_1_bits_frs3_en;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_fcn_dw_0 = io_dis_uops_1_bits_fcn_dw;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_dis_uops_1_bits_fcn_op_0 = io_dis_uops_1_bits_fcn_op;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_fp_val_0 = io_dis_uops_1_bits_fp_val;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_dis_uops_1_bits_fp_rm_0 = io_dis_uops_1_bits_fp_rm;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_dis_uops_1_bits_fp_typ_0 = io_dis_uops_1_bits_fp_typ;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_xcpt_pf_if_0 = io_dis_uops_1_bits_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_xcpt_ae_if_0 = io_dis_uops_1_bits_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_xcpt_ma_if_0 = io_dis_uops_1_bits_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_bp_debug_if_0 = io_dis_uops_1_bits_bp_debug_if;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_bits_bp_xcpt_if_0 = io_dis_uops_1_bits_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_dis_uops_1_bits_debug_fsrc_0 = io_dis_uops_1_bits_debug_fsrc;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_dis_uops_1_bits_debug_tsrc_0 = io_dis_uops_1_bits_debug_tsrc;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [11:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [3:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [3:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [11:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [3:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [3:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [11:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [3:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [3:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [11:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [3:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [3:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_pred_wakeup_port_valid_0 = io_pred_wakeup_port_valid;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_pred_wakeup_port_bits_0 = io_pred_wakeup_port_bits;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_child_rebusys_0 = io_child_rebusys;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [11:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [11:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [11:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [3:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [3:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_flush_pipeline_0 = io_flush_pipeline;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_squash_grant_0 = io_squash_grant;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [63:0] io_tsc_reg_0 = io_tsc_reg;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_bypassable = 1'h0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_1_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_2_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_fu_types_0_1 = 1'h0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_fu_types_0_2 = 1'h0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_fu_types_0_3 = 1'h0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_fu_types_0_4 = 1'h0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_fu_types_0_5 = 1'h0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_fu_types_0_6 = 1'h0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_fu_types_0_7 = 1'h0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_fu_types_0_8 = 1'h0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_fu_types_0_9 = 1'h0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_fu_types_1_1 = 1'h0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_fu_types_1_2 = 1'h0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_fu_types_1_3 = 1'h0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_fu_types_1_4 = 1'h0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_fu_types_1_5 = 1'h0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_fu_types_1_6 = 1'h0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_fu_types_1_7 = 1'h0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_fu_types_1_8 = 1'h0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_fu_types_1_9 = 1'h0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire prs1_rebusys_1 = 1'h0;\t// @[issue-unit-age-ordered.scala:50:95]\n wire prs1_rebusys_2 = 1'h0;\t// @[issue-unit-age-ordered.scala:50:95]\n wire prs1_rebusys_3 = 1'h0;\t// @[issue-unit-age-ordered.scala:50:95]\n wire prs2_rebusys_1 = 1'h0;\t// @[issue-unit-age-ordered.scala:51:95]\n wire prs2_rebusys_2 = 1'h0;\t// @[issue-unit-age-ordered.scala:51:95]\n wire prs2_rebusys_3 = 1'h0;\t// @[issue-unit-age-ordered.scala:51:95]\n wire prs1_rebusys_1_1 = 1'h0;\t// @[issue-unit-age-ordered.scala:50:95]\n wire prs1_rebusys_2_1 = 1'h0;\t// @[issue-unit-age-ordered.scala:50:95]\n wire prs1_rebusys_3_1 = 1'h0;\t// @[issue-unit-age-ordered.scala:50:95]\n wire prs2_rebusys_1_1 = 1'h0;\t// @[issue-unit-age-ordered.scala:51:95]\n wire prs2_rebusys_2_1 = 1'h0;\t// @[issue-unit-age-ordered.scala:51:95]\n wire prs2_rebusys_3_1 = 1'h0;\t// @[issue-unit-age-ordered.scala:51:95]\n wire issue_slots_0_iss_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_clear = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_wakeup_ports_1_bits_bypassable = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_wakeup_ports_1_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_wakeup_ports_2_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_wakeup_ports_3_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_wakeup_ports_1_bits_bypassable = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_wakeup_ports_1_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_wakeup_ports_2_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_wakeup_ports_3_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_wakeup_ports_1_bits_bypassable = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_wakeup_ports_1_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_wakeup_ports_2_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_wakeup_ports_3_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_wakeup_ports_1_bits_bypassable = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_wakeup_ports_1_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_wakeup_ports_2_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_wakeup_ports_3_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_wakeup_ports_1_bits_bypassable = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_wakeup_ports_1_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_wakeup_ports_2_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_wakeup_ports_3_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_wakeup_ports_1_bits_bypassable = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_wakeup_ports_1_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_wakeup_ports_2_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_wakeup_ports_3_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_wakeup_ports_1_bits_bypassable = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_wakeup_ports_1_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_wakeup_ports_2_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_wakeup_ports_3_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_wakeup_ports_1_bits_bypassable = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_wakeup_ports_1_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_wakeup_ports_2_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_wakeup_ports_3_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_wakeup_ports_1_bits_bypassable = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_wakeup_ports_1_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_wakeup_ports_2_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_wakeup_ports_3_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_wakeup_ports_1_bits_bypassable = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_wakeup_ports_1_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_wakeup_ports_2_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_wakeup_ports_3_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_wakeup_ports_1_bits_bypassable = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_wakeup_ports_1_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_wakeup_ports_2_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_wakeup_ports_3_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_wakeup_ports_1_bits_bypassable = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_wakeup_ports_1_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_wakeup_ports_2_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_wakeup_ports_3_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_wakeup_ports_1_bits_bypassable = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_wakeup_ports_1_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_wakeup_ports_2_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_wakeup_ports_3_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_wakeup_ports_1_bits_bypassable = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_wakeup_ports_1_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_wakeup_ports_2_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_wakeup_ports_3_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_wakeup_ports_1_bits_bypassable = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_wakeup_ports_1_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_wakeup_ports_2_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_wakeup_ports_3_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_wakeup_ports_1_bits_bypassable = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_wakeup_ports_1_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_wakeup_ports_2_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_wakeup_ports_3_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_wakeup_ports_1_bits_bypassable = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_wakeup_ports_1_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_wakeup_ports_2_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_wakeup_ports_3_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_wakeup_ports_1_bits_bypassable = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_wakeup_ports_1_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_wakeup_ports_2_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_wakeup_ports_3_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_wakeup_ports_1_bits_bypassable = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_wakeup_ports_1_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_wakeup_ports_2_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_wakeup_ports_3_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_iw_issued = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_wakeup_ports_1_bits_bypassable = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_wakeup_ports_1_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_wakeup_ports_2_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_wakeup_ports_3_bits_rebusy = 1'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire _shamts_oh_1_T_2 = 1'h0;\t// @[issue-unit-age-ordered.scala:165:28]\n wire _issue_slots_0_clear_T = 1'h0;\t// @[issue-unit-age-ordered.scala:199:49]\n wire iss_uops_0_bits_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_iw_issued_partial_agen = 1'h0;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_iw_issued_partial_dgen = 1'h0;\t// @[issue-unit-age-ordered.scala:241:22]\n wire _fu_code_match_T_1 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_2 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_3 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_4 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_5 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_6 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_7 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_8 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_9 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_19 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_20 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_21 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_22 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_23 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_24 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_25 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_26 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_27 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_37 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_38 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_39 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_40 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_41 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_42 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_43 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_44 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_45 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_55 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_56 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_57 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_58 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_59 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_60 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_61 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_62 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_63 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_73 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_74 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_75 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_76 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_77 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_78 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_79 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_80 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_81 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_91 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_92 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_93 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_94 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_95 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_96 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_97 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_98 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_99 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_109 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_110 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_111 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_112 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_113 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_114 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_115 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_116 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_117 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_127 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_128 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_129 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_130 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_131 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_132 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_133 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_134 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_135 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_145 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_146 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_147 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_148 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_149 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_150 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_151 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_152 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_153 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_163 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_164 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_165 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_166 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_167 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_168 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_169 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_170 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_171 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_181 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_182 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_183 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_184 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_185 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_186 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_187 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_188 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_189 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_199 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_200 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_201 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_202 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_203 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_204 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_205 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_206 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_207 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_217 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_218 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_219 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_220 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_221 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_222 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_223 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_224 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_225 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_235 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_236 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_237 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_238 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_239 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_240 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_241 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_242 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_243 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_253 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_254 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_255 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_256 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_257 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_258 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_259 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_260 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_261 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_271 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_272 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_273 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_274 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_275 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_276 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_277 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_278 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_279 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_289 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_290 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_291 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_292 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_293 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_294 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_295 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_296 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_297 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_307 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_308 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_309 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_310 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_311 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_312 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_313 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_314 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_315 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_325 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_326 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_327 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_328 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_329 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_330 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_331 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_332 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_333 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_343 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_344 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_345 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_346 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_347 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_348 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_349 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_350 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_351 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_361 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_362 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_363 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_364 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_365 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_366 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_367 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_368 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_369 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_379 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_380 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_381 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_382 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_383 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_384 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_385 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_386 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_387 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_397 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_398 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_399 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_400 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_401 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_402 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_403 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_404 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_405 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_415 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_416 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_417 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_418 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_419 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_420 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_421 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_422 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_423 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_433 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_434 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_435 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_436 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_437 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_438 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_439 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_440 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_441 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_451 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_452 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_453 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_454 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_455 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_456 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_457 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_458 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_459 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_469 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_470 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_471 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_472 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_473 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_474 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_475 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_476 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_477 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_487 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_488 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_489 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_490 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_491 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_492 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_493 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_494 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_495 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_505 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_506 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_507 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_508 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_509 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_510 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_511 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_512 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_513 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_523 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_524 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_525 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_526 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_527 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_528 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_529 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_530 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_531 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_541 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_542 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_543 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_544 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_545 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_546 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_547 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_548 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_549 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_559 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_560 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_561 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_562 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_563 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_564 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_565 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_566 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_567 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_577 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_578 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_579 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_580 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_581 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_582 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_583 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_584 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_585 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_595 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_596 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_597 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_598 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_599 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_600 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_601 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_602 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_603 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_613 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_614 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_615 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_616 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_617 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_618 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_619 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_620 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_621 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_631 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_632 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_633 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_634 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_635 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_636 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_637 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_638 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_639 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_649 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_650 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_651 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_652 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_653 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_654 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_655 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_656 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_657 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_667 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_668 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_669 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_670 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_671 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_672 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_673 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_674 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_675 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_685 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_686 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_687 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_688 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_689 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_690 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_691 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_692 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_693 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_703 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_704 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_705 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_706 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_707 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_708 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_709 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_710 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire _fu_code_match_T_711 = 1'h0;\t// @[issue-unit-age-ordered.scala:253:25]\n wire [1:0] io_wakeup_ports_1_bits_speculative_mask = 2'h0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] issue_slots_0_wakeup_ports_1_bits_speculative_mask = 2'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_1_wakeup_ports_1_bits_speculative_mask = 2'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_2_wakeup_ports_1_bits_speculative_mask = 2'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_3_wakeup_ports_1_bits_speculative_mask = 2'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_4_wakeup_ports_1_bits_speculative_mask = 2'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_5_wakeup_ports_1_bits_speculative_mask = 2'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_6_wakeup_ports_1_bits_speculative_mask = 2'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_7_wakeup_ports_1_bits_speculative_mask = 2'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_8_wakeup_ports_1_bits_speculative_mask = 2'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_9_wakeup_ports_1_bits_speculative_mask = 2'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_10_wakeup_ports_1_bits_speculative_mask = 2'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_11_wakeup_ports_1_bits_speculative_mask = 2'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_12_wakeup_ports_1_bits_speculative_mask = 2'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_13_wakeup_ports_1_bits_speculative_mask = 2'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_14_wakeup_ports_1_bits_speculative_mask = 2'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_15_wakeup_ports_1_bits_speculative_mask = 2'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_16_wakeup_ports_1_bits_speculative_mask = 2'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_17_wakeup_ports_1_bits_speculative_mask = 2'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_18_wakeup_ports_1_bits_speculative_mask = 2'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_19_wakeup_ports_1_bits_speculative_mask = 2'h0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] shamts_oh_0 = 2'h0;\t// @[issue-unit-age-ordered.scala:158:23]\n wire io_wakeup_ports_2_bits_bypassable = 1'h1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_wakeup_ports_3_bits_bypassable = 1'h1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_fu_types_0_0 = 1'h1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_fu_types_1_0 = 1'h1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire issue_slots_0_wakeup_ports_2_bits_bypassable = 1'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_wakeup_ports_3_bits_bypassable = 1'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_wakeup_ports_2_bits_bypassable = 1'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_wakeup_ports_3_bits_bypassable = 1'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_wakeup_ports_2_bits_bypassable = 1'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_wakeup_ports_3_bits_bypassable = 1'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_wakeup_ports_2_bits_bypassable = 1'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_wakeup_ports_3_bits_bypassable = 1'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_wakeup_ports_2_bits_bypassable = 1'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_wakeup_ports_3_bits_bypassable = 1'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_wakeup_ports_2_bits_bypassable = 1'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_wakeup_ports_3_bits_bypassable = 1'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_wakeup_ports_2_bits_bypassable = 1'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_wakeup_ports_3_bits_bypassable = 1'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_wakeup_ports_2_bits_bypassable = 1'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_wakeup_ports_3_bits_bypassable = 1'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_wakeup_ports_2_bits_bypassable = 1'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_wakeup_ports_3_bits_bypassable = 1'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_wakeup_ports_2_bits_bypassable = 1'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_wakeup_ports_3_bits_bypassable = 1'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_wakeup_ports_2_bits_bypassable = 1'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_wakeup_ports_3_bits_bypassable = 1'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_wakeup_ports_2_bits_bypassable = 1'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_wakeup_ports_3_bits_bypassable = 1'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_wakeup_ports_2_bits_bypassable = 1'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_wakeup_ports_3_bits_bypassable = 1'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_wakeup_ports_2_bits_bypassable = 1'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_wakeup_ports_3_bits_bypassable = 1'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_wakeup_ports_2_bits_bypassable = 1'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_wakeup_ports_3_bits_bypassable = 1'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_wakeup_ports_2_bits_bypassable = 1'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_wakeup_ports_3_bits_bypassable = 1'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_wakeup_ports_2_bits_bypassable = 1'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_wakeup_ports_3_bits_bypassable = 1'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_wakeup_ports_2_bits_bypassable = 1'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_wakeup_ports_3_bits_bypassable = 1'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_wakeup_ports_2_bits_bypassable = 1'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_wakeup_ports_3_bits_bypassable = 1'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_wakeup_ports_2_bits_bypassable = 1'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_wakeup_ports_3_bits_bypassable = 1'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire _shamts_oh_1_T = 1'h1;\t// @[issue-unit-age-ordered.scala:163:21]\n wire _shamts_oh_1_T_3 = 1'h1;\t// @[issue-unit-age-ordered.scala:165:19]\n wire [1:0] io_wakeup_ports_2_bits_speculative_mask = 2'h1;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] issue_slots_0_wakeup_ports_2_bits_speculative_mask = 2'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_1_wakeup_ports_2_bits_speculative_mask = 2'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_2_wakeup_ports_2_bits_speculative_mask = 2'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_3_wakeup_ports_2_bits_speculative_mask = 2'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_4_wakeup_ports_2_bits_speculative_mask = 2'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_5_wakeup_ports_2_bits_speculative_mask = 2'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_6_wakeup_ports_2_bits_speculative_mask = 2'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_7_wakeup_ports_2_bits_speculative_mask = 2'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_8_wakeup_ports_2_bits_speculative_mask = 2'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_9_wakeup_ports_2_bits_speculative_mask = 2'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_10_wakeup_ports_2_bits_speculative_mask = 2'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_11_wakeup_ports_2_bits_speculative_mask = 2'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_12_wakeup_ports_2_bits_speculative_mask = 2'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_13_wakeup_ports_2_bits_speculative_mask = 2'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_14_wakeup_ports_2_bits_speculative_mask = 2'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_15_wakeup_ports_2_bits_speculative_mask = 2'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_16_wakeup_ports_2_bits_speculative_mask = 2'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_17_wakeup_ports_2_bits_speculative_mask = 2'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_18_wakeup_ports_2_bits_speculative_mask = 2'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_19_wakeup_ports_2_bits_speculative_mask = 2'h1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] io_wakeup_ports_3_bits_speculative_mask = 2'h2;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] issue_slots_0_wakeup_ports_3_bits_speculative_mask = 2'h2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_1_wakeup_ports_3_bits_speculative_mask = 2'h2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_2_wakeup_ports_3_bits_speculative_mask = 2'h2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_3_wakeup_ports_3_bits_speculative_mask = 2'h2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_4_wakeup_ports_3_bits_speculative_mask = 2'h2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_5_wakeup_ports_3_bits_speculative_mask = 2'h2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_6_wakeup_ports_3_bits_speculative_mask = 2'h2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_7_wakeup_ports_3_bits_speculative_mask = 2'h2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_8_wakeup_ports_3_bits_speculative_mask = 2'h2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_9_wakeup_ports_3_bits_speculative_mask = 2'h2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_10_wakeup_ports_3_bits_speculative_mask = 2'h2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_11_wakeup_ports_3_bits_speculative_mask = 2'h2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_12_wakeup_ports_3_bits_speculative_mask = 2'h2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_13_wakeup_ports_3_bits_speculative_mask = 2'h2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_14_wakeup_ports_3_bits_speculative_mask = 2'h2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_15_wakeup_ports_3_bits_speculative_mask = 2'h2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_16_wakeup_ports_3_bits_speculative_mask = 2'h2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_17_wakeup_ports_3_bits_speculative_mask = 2'h2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_18_wakeup_ports_3_bits_speculative_mask = 2'h2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_19_wakeup_ports_3_bits_speculative_mask = 2'h2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] _shamts_oh_1_next_T = 3'h0;\t// @[issue-unit-age-ordered.scala:166:26]\n wire [31:0] iss_uops_0_bits_inst;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [31:0] iss_uops_0_bits_debug_inst;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_is_rvc;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [39:0] iss_uops_0_bits_debug_pc;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_iq_type_0;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_iq_type_1;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_iq_type_2;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_iq_type_3;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_fu_code_0;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_fu_code_1;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_fu_code_2;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_fu_code_3;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_fu_code_4;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_fu_code_5;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_fu_code_6;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_fu_code_7;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_fu_code_8;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_fu_code_9;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_iw_issued;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [1:0] iss_uops_0_bits_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [1:0] iss_uops_0_bits_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [1:0] iss_uops_0_bits_dis_col_sel;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [11:0] iss_uops_0_bits_br_mask;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [3:0] iss_uops_0_bits_br_tag;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [3:0] iss_uops_0_bits_br_type;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_is_sfb;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_is_fence;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_is_fencei;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_is_sfence;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_is_amo;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_is_eret;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_is_rocc;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_is_mov;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [4:0] iss_uops_0_bits_ftq_idx;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_edge_inst;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [5:0] iss_uops_0_bits_pc_lob;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_taken;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_imm_rename;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [2:0] iss_uops_0_bits_imm_sel;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [4:0] iss_uops_0_bits_pimm;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [19:0] iss_uops_0_bits_imm_packed;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [1:0] iss_uops_0_bits_op1_sel;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [2:0] iss_uops_0_bits_op2_sel;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [1:0] iss_uops_0_bits_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [1:0] iss_uops_0_bits_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [5:0] iss_uops_0_bits_rob_idx;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [3:0] iss_uops_0_bits_ldq_idx;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [3:0] iss_uops_0_bits_stq_idx;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [1:0] iss_uops_0_bits_rxq_idx;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [6:0] iss_uops_0_bits_pdst;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [6:0] iss_uops_0_bits_prs1;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [6:0] iss_uops_0_bits_prs2;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [6:0] iss_uops_0_bits_prs3;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [4:0] iss_uops_0_bits_ppred;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_prs1_busy;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_prs2_busy;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_prs3_busy;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_ppred_busy;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [6:0] iss_uops_0_bits_stale_pdst;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_exception;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [63:0] iss_uops_0_bits_exc_cause;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [4:0] iss_uops_0_bits_mem_cmd;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [1:0] iss_uops_0_bits_mem_size;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_mem_signed;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_uses_ldq;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_uses_stq;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_is_unique;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_flush_on_commit;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [2:0] iss_uops_0_bits_csr_cmd;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [5:0] iss_uops_0_bits_ldst;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [5:0] iss_uops_0_bits_lrs1;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [5:0] iss_uops_0_bits_lrs2;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [5:0] iss_uops_0_bits_lrs3;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [1:0] iss_uops_0_bits_dst_rtype;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [1:0] iss_uops_0_bits_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [1:0] iss_uops_0_bits_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_frs3_en;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_fcn_dw;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [4:0] iss_uops_0_bits_fcn_op;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_fp_val;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [2:0] iss_uops_0_bits_fp_rm;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [1:0] iss_uops_0_bits_fp_typ;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_bp_debug_if;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_0_bits_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [2:0] iss_uops_0_bits_debug_fsrc;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [2:0] iss_uops_0_bits_debug_tsrc;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [31:0] iss_uops_1_bits_inst;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [31:0] iss_uops_1_bits_debug_inst;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_is_rvc;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [39:0] iss_uops_1_bits_debug_pc;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_iq_type_0;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_iq_type_1;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_iq_type_2;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_iq_type_3;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_fu_code_0;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_fu_code_1;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_fu_code_2;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_fu_code_3;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_fu_code_4;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_fu_code_5;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_fu_code_6;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_fu_code_7;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_fu_code_8;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_fu_code_9;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_iw_issued;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [1:0] iss_uops_1_bits_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [1:0] iss_uops_1_bits_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [1:0] iss_uops_1_bits_dis_col_sel;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [11:0] iss_uops_1_bits_br_mask;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [3:0] iss_uops_1_bits_br_tag;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [3:0] iss_uops_1_bits_br_type;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_is_sfb;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_is_fence;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_is_fencei;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_is_sfence;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_is_amo;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_is_eret;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_is_rocc;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_is_mov;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [4:0] iss_uops_1_bits_ftq_idx;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_edge_inst;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [5:0] iss_uops_1_bits_pc_lob;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_taken;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_imm_rename;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [2:0] iss_uops_1_bits_imm_sel;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [4:0] iss_uops_1_bits_pimm;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [19:0] iss_uops_1_bits_imm_packed;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [1:0] iss_uops_1_bits_op1_sel;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [2:0] iss_uops_1_bits_op2_sel;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [1:0] iss_uops_1_bits_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [1:0] iss_uops_1_bits_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [5:0] iss_uops_1_bits_rob_idx;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [3:0] iss_uops_1_bits_ldq_idx;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [3:0] iss_uops_1_bits_stq_idx;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [1:0] iss_uops_1_bits_rxq_idx;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [6:0] iss_uops_1_bits_pdst;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [6:0] iss_uops_1_bits_prs1;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [6:0] iss_uops_1_bits_prs2;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [6:0] iss_uops_1_bits_prs3;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [4:0] iss_uops_1_bits_ppred;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_prs1_busy;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_prs2_busy;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_prs3_busy;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_ppred_busy;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [6:0] iss_uops_1_bits_stale_pdst;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_exception;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [63:0] iss_uops_1_bits_exc_cause;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [4:0] iss_uops_1_bits_mem_cmd;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [1:0] iss_uops_1_bits_mem_size;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_mem_signed;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_uses_ldq;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_uses_stq;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_is_unique;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_flush_on_commit;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [2:0] iss_uops_1_bits_csr_cmd;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [5:0] iss_uops_1_bits_ldst;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [5:0] iss_uops_1_bits_lrs1;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [5:0] iss_uops_1_bits_lrs2;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [5:0] iss_uops_1_bits_lrs3;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [1:0] iss_uops_1_bits_dst_rtype;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [1:0] iss_uops_1_bits_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [1:0] iss_uops_1_bits_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_frs3_en;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_fcn_dw;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [4:0] iss_uops_1_bits_fcn_op;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_fp_val;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [2:0] iss_uops_1_bits_fp_rm;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [1:0] iss_uops_1_bits_fp_typ;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_bp_debug_if;\t// @[issue-unit-age-ordered.scala:241:22]\n wire iss_uops_1_bits_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [2:0] iss_uops_1_bits_debug_fsrc;\t// @[issue-unit-age-ordered.scala:241:22]\n wire [2:0] iss_uops_1_bits_debug_tsrc;\t// @[issue-unit-age-ordered.scala:241:22]\n wire issue_slots_0_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_0_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_1_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_2_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_3_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_4_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_5_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_6_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_7_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_8_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_9_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_10_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_11_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_12_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_13_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_14_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_15_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_16_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_17_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_18_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_19_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_0_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_1_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_2_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_3_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_4_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_5_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_6_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_7_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_8_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_9_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_10_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_11_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_12_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_13_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_14_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_15_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_16_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_17_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_18_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_19_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_0_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_1_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_2_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_3_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_4_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_5_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_6_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_7_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_8_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_9_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_10_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_11_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_12_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_13_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_14_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_15_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_16_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_17_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_18_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_19_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_0_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_1_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_2_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_3_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_4_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_5_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_6_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_7_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_8_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_9_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_10_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_11_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_12_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_13_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_14_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_15_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_16_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_17_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_18_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_19_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_0_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_1_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_2_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_3_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_4_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_5_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_6_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_7_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_8_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_9_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_10_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_11_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_12_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_13_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_14_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_15_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_16_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_17_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_18_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_19_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_0_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_1_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_2_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_3_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_4_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_5_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_6_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_7_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_8_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_9_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_10_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_11_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_12_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_13_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_14_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_15_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_16_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_17_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_18_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_19_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_16_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_17_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_18_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_19_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_12_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_13_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_14_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_15_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_16_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_17_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_18_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_19_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_16_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_17_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_18_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_19_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_16_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_17_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_18_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_19_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_0_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_1_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_2_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_3_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_4_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_5_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_6_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_7_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_8_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_9_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_10_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_11_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_12_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_13_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_14_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_15_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_16_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_17_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_18_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_19_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_16_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_17_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_18_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_19_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_12_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_13_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_14_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_15_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_16_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_17_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_18_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_19_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_0_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_1_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_2_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_3_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_4_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_5_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_6_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_7_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_8_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_9_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_10_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_11_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_12_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_13_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_14_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_15_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_16_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_17_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_18_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_19_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_0_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_1_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_2_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_3_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_4_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_5_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_6_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_7_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_8_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_9_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_10_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_11_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_12_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_13_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_14_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_15_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_16_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_17_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_18_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_19_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_12_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_13_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_14_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_15_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_16_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_17_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_18_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_19_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_12_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_13_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_14_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_15_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_16_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_17_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_18_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_19_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_12_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_13_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_14_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_15_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_16_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_17_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_18_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_19_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_12_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_13_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_14_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_15_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_16_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_17_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_18_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_19_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_16_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_17_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_18_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_19_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_12_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_13_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_14_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_15_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_16_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_17_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_18_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_19_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_0_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_1_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_2_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_3_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_4_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_5_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_6_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_7_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_8_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_9_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_10_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_11_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_12_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_13_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_14_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_15_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_16_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_17_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_18_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_19_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_16_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_17_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_18_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_19_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_16_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_17_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_18_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_19_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_12_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_13_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_14_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_15_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_16_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_17_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_18_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_19_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_12_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_13_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_14_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_15_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_16_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_17_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_18_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_19_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_12_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_13_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_14_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_15_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_16_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_17_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_18_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_19_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_12_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_13_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_14_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_15_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_16_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_17_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_18_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_19_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_16_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_17_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_18_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_19_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_16_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_17_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_18_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_19_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_16_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_17_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_18_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_19_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_16_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_17_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_18_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_19_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_0_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_1_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_2_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_3_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_4_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_5_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_6_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_7_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_8_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_9_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_10_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_11_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_12_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_13_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_14_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_15_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_16_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_17_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_18_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_19_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_0_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_1_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_2_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_3_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_4_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_5_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_6_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_7_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_8_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_9_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_10_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_11_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_12_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_13_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_14_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_15_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_16_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_17_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_18_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_19_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_0_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_1_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_2_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_3_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_4_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_5_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_6_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_7_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_8_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_9_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_10_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_11_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_12_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_13_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_14_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_15_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_16_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_17_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_18_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_19_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_0_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_1_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_2_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_3_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_4_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_5_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_6_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_7_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_8_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_9_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_10_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_11_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_12_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_13_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_14_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_15_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_16_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_17_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_18_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_19_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_0_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_1_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_2_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_3_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_4_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_5_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_6_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_7_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_8_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_9_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_10_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_11_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_12_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_13_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_14_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_15_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_16_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_17_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_18_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_19_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_0_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_1_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_2_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_3_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_4_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_5_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_6_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_7_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_8_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_9_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_10_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_11_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_12_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_13_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_14_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_15_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_16_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_17_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_18_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_19_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_16_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_17_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_18_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_19_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_12_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_13_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_14_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_15_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_16_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_17_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_18_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_19_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_16_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_17_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_18_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_19_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_16_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_17_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_18_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_19_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_0_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_1_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_2_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_3_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_4_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_5_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_6_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_7_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_8_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_9_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_10_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_11_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_12_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_13_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_14_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_15_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_16_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_17_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_18_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_19_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_16_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_17_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_18_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_19_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_12_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_13_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_14_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_15_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_16_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_17_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_18_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_19_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_0_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_1_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_2_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_3_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_4_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_5_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_6_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_7_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_8_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_9_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_10_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_11_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_12_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_13_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_14_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_15_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_16_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_17_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_18_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_19_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_0_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_1_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_2_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_3_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_4_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_5_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_6_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_7_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_8_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_9_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_10_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_11_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_12_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_13_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_14_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_15_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_16_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_17_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_18_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_19_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_12_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_13_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_14_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_15_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_16_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_17_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_18_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_19_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_12_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_13_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_14_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_15_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_16_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_17_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_18_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_19_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_12_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_13_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_14_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_15_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_16_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_17_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_18_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_19_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_12_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_13_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_14_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_15_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_16_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_17_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_18_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_19_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_16_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_17_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_18_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_19_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_12_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_13_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_14_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_15_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_16_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_17_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_18_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_19_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_0_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_1_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_2_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_3_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_4_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_5_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_6_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_7_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_8_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_9_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_10_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_11_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_12_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_13_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_14_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_15_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_16_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_17_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_18_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_19_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_16_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_17_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_18_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_19_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_16_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_17_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_18_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_19_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_12_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_13_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_14_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_15_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_16_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_17_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_18_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_19_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_12_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_13_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_14_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_15_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_16_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_17_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_18_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_19_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_12_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_13_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_14_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_15_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_16_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_17_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_18_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_19_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_12_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_13_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_14_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_15_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_16_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_17_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_18_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_19_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_16_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_17_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_18_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_19_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_16_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_17_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_18_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_19_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_16_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_17_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_18_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_19_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_16_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_17_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_18_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_19_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_0_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_1_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_2_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_3_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_4_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_5_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_6_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_7_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_8_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_9_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_10_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_11_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_12_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_13_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_14_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_15_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_16_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_17_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_18_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_19_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_0_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_1_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_2_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_3_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_4_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_5_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_6_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_7_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_8_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_9_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_10_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_11_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_12_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_13_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_14_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_15_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_16_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_17_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_18_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_19_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_0_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_1_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_2_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_3_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_4_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_5_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_6_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_7_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_8_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_9_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_10_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_11_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_12_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_13_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_14_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_15_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_16_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_17_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_18_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_19_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_0_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_1_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_2_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_3_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_4_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_5_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_6_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_7_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_8_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_9_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_10_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_11_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_12_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_13_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_14_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_15_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_16_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_17_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_18_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_19_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_0_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_1_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_2_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_3_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_4_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_5_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_6_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_7_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_8_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_9_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_10_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_11_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_12_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_13_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_14_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_15_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_16_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_17_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_18_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_19_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_0_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_1_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_2_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_3_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_4_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_5_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_6_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_7_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_8_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_9_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_10_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_11_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_12_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_13_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_14_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_15_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_16_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_17_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_18_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_19_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_0_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_1_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_2_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_3_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_4_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_5_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_6_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_7_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_8_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_9_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_10_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_11_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_12_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_13_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_14_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_15_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_16_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_17_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_18_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_19_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_0_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_1_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_2_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_3_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_4_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_5_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_6_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_7_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_8_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_9_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_10_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_11_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_12_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_13_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_14_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_15_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_16_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_17_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_18_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_19_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_12_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_13_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_14_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_15_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_16_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_17_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_18_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_19_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_0_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_1_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_2_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_3_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_4_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_5_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_6_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_7_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_8_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_9_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_10_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_11_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_12_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_13_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_14_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_15_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_16_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_17_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_18_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_19_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_0_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_1_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_2_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_3_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_4_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_5_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_6_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_7_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_8_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_9_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_10_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_11_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_12_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_13_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_14_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_15_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_16_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_17_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_18_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_19_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_12_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_13_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_14_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_15_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_16_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_17_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_18_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_19_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_0_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_1_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_2_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_3_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_4_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_5_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_6_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_7_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_8_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_9_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_10_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_11_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_12_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_13_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_14_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_15_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_16_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_17_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_18_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_19_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_0_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_1_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_2_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_3_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_4_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_5_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_6_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_7_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_8_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_9_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_10_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_11_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_12_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_13_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_14_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_15_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_16_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_17_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_18_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_19_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_0_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_1_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_2_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_3_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_4_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_5_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_6_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_7_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_8_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_9_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_10_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_11_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_12_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_13_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_14_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_15_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_16_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_17_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_18_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_19_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_0_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_1_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_2_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_3_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_4_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_5_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_6_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_7_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_8_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_9_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_10_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_11_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_12_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_13_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_14_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_15_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_16_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_17_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_18_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_19_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_0_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_1_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_2_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_3_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_4_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_5_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_6_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_7_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_8_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_9_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_10_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_11_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_12_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_13_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_14_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_15_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_16_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_17_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_18_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_19_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_0_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_1_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_2_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_3_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_4_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_5_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_6_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_7_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_8_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_9_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_10_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_11_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_12_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_13_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_14_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_15_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_16_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_17_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_18_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_19_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_0_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_1_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_2_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_3_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_4_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_5_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_6_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_7_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_8_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_9_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_10_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_11_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_12_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_13_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_14_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_15_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_16_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_17_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_18_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_19_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_0_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_1_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_2_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_3_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_4_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_5_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_6_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_7_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_8_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_9_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_10_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_11_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_12_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_13_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_14_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_15_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_16_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_17_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_18_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_19_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_0_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_1_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_2_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_3_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_4_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_5_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_6_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_7_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_8_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_9_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_10_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_11_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_12_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_13_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_14_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_15_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_16_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_17_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_18_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_19_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_0_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_1_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_2_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_3_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_4_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_5_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_6_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_7_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_8_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_9_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_10_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_11_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_12_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_13_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_14_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_15_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_16_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_17_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_18_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_19_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_0_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_1_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_2_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_3_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_4_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_5_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_6_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_7_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_8_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_9_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_10_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_11_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_12_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_13_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_14_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_15_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_16_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_17_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_18_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_19_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_12_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_13_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_14_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_15_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_16_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_17_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_18_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_19_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_0_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_1_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_2_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_3_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_4_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_5_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_6_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_7_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_8_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_9_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_10_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_11_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_12_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_13_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_14_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_15_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_16_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_17_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_18_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_19_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_0_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_1_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_2_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_3_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_4_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_5_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_6_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_7_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_8_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_9_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_10_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_11_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_12_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_13_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_14_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_15_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_16_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_17_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_18_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_19_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_0_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_1_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_2_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_3_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_4_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_5_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_6_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_7_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_8_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_9_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_10_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_11_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_12_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_13_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_14_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_15_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_16_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_17_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_18_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_19_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_0_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_1_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_2_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_3_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_4_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_5_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_6_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_7_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_8_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_9_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_10_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_11_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_12_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_13_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_14_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_15_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_16_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_17_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_18_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_19_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_0_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_1_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_2_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_3_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_4_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_5_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_6_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_7_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_8_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_9_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_10_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_11_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_12_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_13_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_14_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_15_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_16_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_17_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_18_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_19_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_12_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_13_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_14_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_15_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_16_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_17_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_18_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_19_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_12_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_13_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_14_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_15_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_16_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_17_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_18_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_19_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_12_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_13_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_14_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_15_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_16_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_17_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_18_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_19_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_0_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_1_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_2_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_3_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_4_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_5_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_6_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_7_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_8_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_9_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_10_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_11_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_12_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_13_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_14_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_15_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_16_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_17_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_18_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_19_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_0_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_1_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_2_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_3_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_4_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_5_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_6_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_7_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_8_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_9_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_10_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_11_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_12_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_13_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_14_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_15_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_16_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_17_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_18_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_19_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_0_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_1_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_2_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_3_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_4_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_5_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_6_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_7_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_8_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_9_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_10_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_11_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_12_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_13_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_14_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_15_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_16_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_17_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_18_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_19_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_0_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_1_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_2_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_3_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_4_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_5_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_6_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_7_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_8_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_9_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_10_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_11_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_12_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_13_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_14_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_15_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_16_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_17_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_18_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_19_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_0_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_1_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_2_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_3_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_4_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_5_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_6_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_7_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_8_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_9_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_10_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_11_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_12_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_13_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_14_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_15_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_16_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_17_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_18_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_19_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_0_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_1_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_2_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_3_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_4_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_5_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_6_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_7_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_8_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_9_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_10_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_11_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_12_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_13_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_14_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_15_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_16_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_17_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_18_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_19_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_0_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_1_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_2_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_3_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_4_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_5_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_6_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_7_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_8_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_9_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_10_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_11_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_12_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_13_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_14_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_15_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_16_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_17_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_18_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_19_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_0_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_1_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_2_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_3_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_4_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_5_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_6_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_7_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_8_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_9_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_10_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_11_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_12_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_13_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_14_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_15_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_16_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_17_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_18_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_19_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_12_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_13_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_14_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_15_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_16_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_17_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_18_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_19_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_0_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_1_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_2_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_3_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_4_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_5_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_6_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_7_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_8_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_9_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_10_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_11_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_12_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_13_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_14_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_15_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_16_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_17_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_18_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_19_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_0_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_1_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_2_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_3_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_4_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_5_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_6_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_7_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_8_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_9_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_10_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_11_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_12_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_13_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_14_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_15_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_16_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_17_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_18_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_19_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_12_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_13_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_14_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_15_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_16_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_17_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_18_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_19_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_0_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_1_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_2_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_3_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_4_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_5_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_6_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_7_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_8_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_9_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_10_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_11_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_12_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_13_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_14_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_15_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_16_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_17_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_18_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_19_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_0_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_1_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_2_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_3_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_4_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_5_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_6_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_7_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_8_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_9_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_10_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_11_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_12_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_13_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_14_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_15_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_16_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_17_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_18_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_19_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_0_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_1_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_2_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_3_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_4_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_5_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_6_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_7_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_8_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_9_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_10_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_11_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_12_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_13_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_14_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_15_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_16_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_17_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_18_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_19_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_0_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_1_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_2_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_3_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_4_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_5_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_6_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_7_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_8_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_9_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_10_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_11_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_12_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_13_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_14_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_15_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_16_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_17_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_18_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_19_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_0_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_1_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_2_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_3_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_4_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_5_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_6_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_7_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_8_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_9_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_10_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_11_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_12_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_13_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_14_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_15_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_16_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_17_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_18_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_19_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_0_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_1_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_2_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_3_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_4_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_5_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_6_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_7_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_8_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_9_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_10_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_11_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_12_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_13_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_14_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_15_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_16_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_17_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_18_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_19_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_0_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_1_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_2_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_3_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_4_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_5_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_6_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_7_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_8_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_9_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_10_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_11_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_12_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_13_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_14_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_15_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_16_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_17_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_18_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_19_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_0_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_1_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_2_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_3_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_4_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_5_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_6_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_7_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_8_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_9_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_10_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_11_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_12_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_13_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_14_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_15_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_16_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_17_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_18_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_19_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_0_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_1_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_2_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_3_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_4_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_5_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_6_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_7_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_8_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_9_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_10_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_11_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_12_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_13_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_14_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_15_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_16_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_17_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_18_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_19_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_0_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_1_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_2_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_3_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_4_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_5_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_6_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_7_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_8_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_9_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_10_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_11_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_12_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_13_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_14_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_15_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_16_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_17_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_18_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_19_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_0_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_1_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_2_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_3_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_4_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_5_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_6_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_7_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_8_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_9_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_10_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_11_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_12_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_13_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_14_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_15_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_16_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_17_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_18_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_19_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_12_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_13_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_14_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_15_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_16_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_17_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_18_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_19_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_0_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_1_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_2_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_3_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_4_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_5_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_6_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_7_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_8_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_9_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_10_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_11_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_12_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_13_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_14_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_15_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_16_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_17_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_18_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_19_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_0_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_1_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_2_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_3_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_4_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_5_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_6_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_7_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_8_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_9_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_10_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_11_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_12_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_13_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_14_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_15_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_16_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_17_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_18_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_19_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_0_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_1_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_2_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_3_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_4_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_5_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_6_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_7_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_8_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_9_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_10_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_11_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_12_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_13_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_14_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_15_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_16_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_17_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_18_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_19_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_0_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_1_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_2_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_3_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_4_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_5_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_6_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_7_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_8_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_9_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_10_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_11_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_12_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_13_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_14_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_15_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_16_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_17_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_18_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_19_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_0_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_1_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_2_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_3_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_4_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_5_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_6_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_7_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_8_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_9_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_10_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_11_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_12_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_13_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_14_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_15_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_16_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_17_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_18_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_19_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_12_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_13_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_14_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_15_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_16_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_17_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_18_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_19_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_12_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_13_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_14_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_15_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_16_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_17_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_18_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_19_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_12_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_13_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_14_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_15_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_16_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_17_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_18_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_19_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_0_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_1_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_2_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_3_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_4_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_5_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_6_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_7_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_8_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_9_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_10_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_11_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_12_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_13_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_14_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_15_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_16_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_17_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_18_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_19_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_child_rebusys = io_child_rebusys_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_child_rebusys = io_child_rebusys_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_child_rebusys = io_child_rebusys_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_child_rebusys = io_child_rebusys_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_child_rebusys = io_child_rebusys_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_child_rebusys = io_child_rebusys_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_child_rebusys = io_child_rebusys_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_child_rebusys = io_child_rebusys_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_child_rebusys = io_child_rebusys_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_child_rebusys = io_child_rebusys_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_child_rebusys = io_child_rebusys_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_child_rebusys = io_child_rebusys_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_child_rebusys = io_child_rebusys_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_child_rebusys = io_child_rebusys_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_child_rebusys = io_child_rebusys_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_child_rebusys = io_child_rebusys_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_child_rebusys = io_child_rebusys_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_child_rebusys = io_child_rebusys_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_child_rebusys = io_child_rebusys_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_child_rebusys = io_child_rebusys_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_0_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_1_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_2_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_3_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_4_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_5_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_6_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_7_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_8_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_9_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_10_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_11_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_12_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_13_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_14_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_15_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_16_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_17_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_18_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_19_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_0_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_1_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_2_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_3_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_4_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_5_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_6_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_7_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_8_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_9_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_10_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_11_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_12_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_13_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_14_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_15_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_16_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_17_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_18_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_19_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_0_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_1_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_2_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_3_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_4_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_5_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_6_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_7_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_8_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_9_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_10_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_11_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_12_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_13_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_14_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_15_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_16_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_17_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_18_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_19_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_0_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_1_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_2_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_3_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_4_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_5_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_6_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_7_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_8_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_9_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_10_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_11_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_12_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_13_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_14_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_15_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_16_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_17_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_18_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [31:0] issue_slots_19_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_0_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_1_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_2_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_3_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_4_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_5_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_6_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_7_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_8_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_9_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_10_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_11_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_12_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_13_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_14_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_15_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_16_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_17_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_18_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_19_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_0_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_1_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_2_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_3_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_4_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_5_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_6_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_7_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_8_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_9_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_10_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_11_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_12_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_13_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_14_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_15_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_16_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_17_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_18_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [11:0] issue_slots_19_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_0_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_1_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_2_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_3_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_4_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_5_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_6_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_7_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_8_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_9_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_10_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_11_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_12_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_13_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_14_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_15_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_16_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_17_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_18_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_19_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_0_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_1_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_2_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_3_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_4_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_5_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_6_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_7_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_8_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_9_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_10_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_11_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_12_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_13_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_14_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_15_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_16_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_17_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_18_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_19_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_0_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_1_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_2_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_3_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_4_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_5_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_6_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_7_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_8_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_9_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_10_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_11_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_12_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_13_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_14_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_15_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_16_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_17_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_18_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_19_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_0_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_1_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_2_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_3_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_4_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_5_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_6_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_7_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_8_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_9_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_10_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_11_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_12_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_13_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_14_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_15_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_16_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_17_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_18_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_19_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_0_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_1_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_2_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_3_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_4_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_5_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_6_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_7_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_8_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_9_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_10_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_11_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_12_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_13_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_14_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_15_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_16_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_17_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_18_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_19_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_0_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_1_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_2_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_3_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_4_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_5_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_6_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_7_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_8_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_9_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_10_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_11_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_12_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_13_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_14_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_15_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_16_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_17_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_18_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_19_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_0_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_1_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_2_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_3_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_4_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_5_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_6_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_7_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_8_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_9_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_10_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_11_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_12_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_13_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_14_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_15_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_16_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_17_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_18_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [19:0] issue_slots_19_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_0_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_1_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_2_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_3_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_4_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_5_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_6_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_7_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_8_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_9_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_10_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_11_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_12_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_13_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_14_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_15_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_16_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_17_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_18_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_19_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_0_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_1_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_2_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_3_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_4_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_5_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_6_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_7_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_8_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_9_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_10_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_11_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_12_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_13_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_14_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_15_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_16_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_17_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_18_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_19_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_0_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_1_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_2_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_3_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_4_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_5_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_6_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_7_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_8_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_9_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_10_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_11_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_12_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_13_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_14_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_15_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_16_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_17_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_18_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_19_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_0_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_1_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_2_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_3_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_4_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_5_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_6_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_7_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_8_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_9_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_10_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_11_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_12_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_13_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_14_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_15_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_16_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_17_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_18_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [3:0] issue_slots_19_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_0_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_1_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_2_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_3_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_4_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_5_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_6_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_7_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_8_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_9_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_10_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_11_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_12_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_13_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_14_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_15_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_16_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_17_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_18_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_19_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_0_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_1_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_2_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_3_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_4_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_5_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_6_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_7_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_8_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_9_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_10_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_11_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_12_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_13_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_14_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_15_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_16_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_17_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_18_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_19_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_0_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_1_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_2_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_3_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_4_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_5_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_6_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_7_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_8_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_9_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_10_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_11_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_12_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_13_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_14_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_15_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_16_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_17_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_18_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_19_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_0_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_1_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_2_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_3_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_4_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_5_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_6_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_7_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_8_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_9_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_10_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_11_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_12_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_13_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_14_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_15_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_16_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_17_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_18_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_19_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_0_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_1_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_2_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_3_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_4_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_5_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_6_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_7_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_8_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_9_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_10_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_11_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_12_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_13_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_14_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_15_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_16_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_17_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_18_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_19_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_0_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_1_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_2_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_3_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_4_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_5_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_6_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_7_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_8_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_9_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_10_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_11_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_12_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_13_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_14_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_15_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_16_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_17_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_18_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [6:0] issue_slots_19_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_0_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_1_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_2_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_3_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_4_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_5_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_6_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_7_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_8_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_9_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_10_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_11_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_12_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_13_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_14_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_15_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_16_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_17_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_18_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [63:0] issue_slots_19_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_0_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_1_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_2_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_3_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_4_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_5_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_6_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_7_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_8_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_9_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_10_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_11_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_12_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_13_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_14_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_15_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_16_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_17_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_18_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_19_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_0_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_1_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_2_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_3_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_4_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_5_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_6_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_7_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_8_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_9_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_10_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_11_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_12_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_13_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_14_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_15_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_16_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_17_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_18_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_19_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_0_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_1_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_2_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_3_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_4_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_5_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_6_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_7_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_8_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_9_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_10_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_11_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_12_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_13_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_14_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_15_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_16_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_17_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_18_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_19_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_0_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_1_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_2_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_3_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_4_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_5_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_6_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_7_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_8_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_9_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_10_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_11_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_12_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_13_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_14_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_15_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_16_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_17_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_18_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_19_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_0_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_1_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_2_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_3_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_4_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_5_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_6_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_7_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_8_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_9_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_10_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_11_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_12_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_13_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_14_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_15_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_16_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_17_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_18_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_19_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_0_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_1_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_2_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_3_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_4_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_5_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_6_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_7_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_8_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_9_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_10_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_11_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_12_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_13_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_14_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_15_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_16_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_17_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_18_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [5:0] issue_slots_19_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_0_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_1_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_2_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_3_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_4_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_5_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_6_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_7_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_8_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_9_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_10_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_11_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_12_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_13_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_14_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_15_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_16_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_17_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_18_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [4:0] issue_slots_19_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_0_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_1_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_2_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_3_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_4_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_5_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_6_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_7_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_8_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_9_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_10_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_11_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_12_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_13_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_14_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_15_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_16_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_17_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_18_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_19_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_0_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_1_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_2_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_3_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_4_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_5_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_6_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_7_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_8_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_9_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_10_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_11_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_12_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_13_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_14_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_15_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_16_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_17_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_18_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_19_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_0_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_1_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_2_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_3_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_4_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_5_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_6_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_7_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_8_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_9_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_10_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_11_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_12_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_13_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_14_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_15_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_16_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_17_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_18_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_19_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_brupdate_b2_taken = io_brupdate_b2_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_brupdate_b2_taken = io_brupdate_b2_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_brupdate_b2_taken = io_brupdate_b2_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_brupdate_b2_taken = io_brupdate_b2_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_brupdate_b2_taken = io_brupdate_b2_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_brupdate_b2_taken = io_brupdate_b2_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_brupdate_b2_taken = io_brupdate_b2_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_brupdate_b2_taken = io_brupdate_b2_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_brupdate_b2_taken = io_brupdate_b2_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_brupdate_b2_taken = io_brupdate_b2_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_brupdate_b2_taken = io_brupdate_b2_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_brupdate_b2_taken = io_brupdate_b2_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_brupdate_b2_taken = io_brupdate_b2_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_brupdate_b2_taken = io_brupdate_b2_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_brupdate_b2_taken = io_brupdate_b2_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_brupdate_b2_taken = io_brupdate_b2_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_brupdate_b2_taken = io_brupdate_b2_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_brupdate_b2_taken = io_brupdate_b2_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_brupdate_b2_taken = io_brupdate_b2_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_brupdate_b2_taken = io_brupdate_b2_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_0_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_1_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_2_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_3_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_4_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_5_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_6_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_7_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_8_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_9_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_10_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_11_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_12_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_13_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_14_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_15_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_16_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_17_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_18_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [2:0] issue_slots_19_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_0_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_1_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_2_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_3_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_4_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_5_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_6_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_7_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_8_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_9_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_10_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_11_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_12_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_13_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_14_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_15_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_16_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_17_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_18_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [1:0] issue_slots_19_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_0_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_1_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_2_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_3_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_4_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_5_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_6_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_7_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_8_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_9_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_10_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_11_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_12_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_13_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_14_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_15_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_16_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_17_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_18_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [39:0] issue_slots_19_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [20:0] issue_slots_0_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [20:0] issue_slots_1_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [20:0] issue_slots_2_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [20:0] issue_slots_3_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [20:0] issue_slots_4_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [20:0] issue_slots_5_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [20:0] issue_slots_6_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [20:0] issue_slots_7_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [20:0] issue_slots_8_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [20:0] issue_slots_9_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [20:0] issue_slots_10_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [20:0] issue_slots_11_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [20:0] issue_slots_12_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [20:0] issue_slots_13_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [20:0] issue_slots_14_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [20:0] issue_slots_15_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [20:0] issue_slots_16_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [20:0] issue_slots_17_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [20:0] issue_slots_18_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire [20:0] issue_slots_19_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_kill = io_flush_pipeline_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_kill = io_flush_pipeline_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_kill = io_flush_pipeline_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_kill = io_flush_pipeline_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_kill = io_flush_pipeline_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_kill = io_flush_pipeline_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_kill = io_flush_pipeline_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_kill = io_flush_pipeline_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_kill = io_flush_pipeline_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_kill = io_flush_pipeline_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_kill = io_flush_pipeline_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_kill = io_flush_pipeline_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_kill = io_flush_pipeline_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_kill = io_flush_pipeline_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_kill = io_flush_pipeline_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_kill = io_flush_pipeline_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_kill = io_flush_pipeline_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_kill = io_flush_pipeline_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_kill = io_flush_pipeline_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_kill = io_flush_pipeline_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_0_squash_grant = io_squash_grant_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_1_squash_grant = io_squash_grant_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_2_squash_grant = io_squash_grant_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_3_squash_grant = io_squash_grant_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_4_squash_grant = io_squash_grant_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_5_squash_grant = io_squash_grant_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_6_squash_grant = io_squash_grant_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_7_squash_grant = io_squash_grant_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_8_squash_grant = io_squash_grant_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_9_squash_grant = io_squash_grant_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_10_squash_grant = io_squash_grant_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_11_squash_grant = io_squash_grant_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_12_squash_grant = io_squash_grant_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_13_squash_grant = io_squash_grant_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_14_squash_grant = io_squash_grant_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_15_squash_grant = io_squash_grant_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_16_squash_grant = io_squash_grant_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_17_squash_grant = io_squash_grant_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_18_squash_grant = io_squash_grant_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire issue_slots_19_squash_grant = io_squash_grant_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28]\n wire io_dis_uops_0_ready_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_dis_uops_1_ready_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_iss_uops_0_bits_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_iss_uops_0_bits_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [31:0] io_iss_uops_0_bits_inst_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [31:0] io_iss_uops_0_bits_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [39:0] io_iss_uops_0_bits_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_iss_uops_0_bits_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_iss_uops_0_bits_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_iss_uops_0_bits_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [11:0] io_iss_uops_0_bits_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [3:0] io_iss_uops_0_bits_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [3:0] io_iss_uops_0_bits_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_iss_uops_0_bits_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_iss_uops_0_bits_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_taken_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_iss_uops_0_bits_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_iss_uops_0_bits_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [19:0] io_iss_uops_0_bits_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_iss_uops_0_bits_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_iss_uops_0_bits_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_iss_uops_0_bits_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [3:0] io_iss_uops_0_bits_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [3:0] io_iss_uops_0_bits_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_iss_uops_0_bits_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_iss_uops_0_bits_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_iss_uops_0_bits_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_iss_uops_0_bits_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_iss_uops_0_bits_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_iss_uops_0_bits_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_iss_uops_0_bits_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_exception_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [63:0] io_iss_uops_0_bits_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_iss_uops_0_bits_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_iss_uops_0_bits_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_iss_uops_0_bits_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_iss_uops_0_bits_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_iss_uops_0_bits_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_iss_uops_0_bits_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_iss_uops_0_bits_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_iss_uops_0_bits_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_iss_uops_0_bits_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_iss_uops_0_bits_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_iss_uops_0_bits_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_iss_uops_0_bits_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_iss_uops_0_bits_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_bits_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_iss_uops_0_bits_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_iss_uops_0_bits_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_0_valid_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_iss_uops_1_bits_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_iss_uops_1_bits_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [31:0] io_iss_uops_1_bits_inst_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [31:0] io_iss_uops_1_bits_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [39:0] io_iss_uops_1_bits_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_iw_issued_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_iss_uops_1_bits_iw_p1_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_iss_uops_1_bits_iw_p2_speculative_child_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_iw_p1_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_iw_p2_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_iw_p3_bypass_hint_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_iss_uops_1_bits_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [11:0] io_iss_uops_1_bits_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [3:0] io_iss_uops_1_bits_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [3:0] io_iss_uops_1_bits_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_iss_uops_1_bits_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_iss_uops_1_bits_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_taken_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_iss_uops_1_bits_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_iss_uops_1_bits_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [19:0] io_iss_uops_1_bits_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_iss_uops_1_bits_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_iss_uops_1_bits_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_iss_uops_1_bits_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [3:0] io_iss_uops_1_bits_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [3:0] io_iss_uops_1_bits_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_iss_uops_1_bits_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_iss_uops_1_bits_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_iss_uops_1_bits_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_iss_uops_1_bits_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_iss_uops_1_bits_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_iss_uops_1_bits_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [6:0] io_iss_uops_1_bits_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_exception_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [63:0] io_iss_uops_1_bits_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_iss_uops_1_bits_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_iss_uops_1_bits_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_iss_uops_1_bits_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_iss_uops_1_bits_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_iss_uops_1_bits_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_iss_uops_1_bits_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [5:0] io_iss_uops_1_bits_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_iss_uops_1_bits_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_iss_uops_1_bits_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_iss_uops_1_bits_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [4:0] io_iss_uops_1_bits_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_iss_uops_1_bits_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [1:0] io_iss_uops_1_bits_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_bits_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_iss_uops_1_bits_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire [2:0] io_iss_uops_1_bits_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire io_iss_uops_1_valid_0;\t// @[issue-unit-age-ordered.scala:22:7]\n wire prs1_matches_0 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_0_bits_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :44:69]\n wire prs1_matches_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_0_bits_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :44:69]\n wire prs1_matches_2 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_0_bits_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :44:69]\n wire prs1_matches_3 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_0_bits_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :44:69]\n wire prs2_matches_0 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_0_bits_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :45:69]\n wire prs2_matches_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_0_bits_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :45:69]\n wire prs2_matches_2 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_0_bits_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :45:69]\n wire prs2_matches_3 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_0_bits_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :45:69]\n wire prs3_matches_0 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_0_bits_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :46:69]\n wire prs3_matches_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_0_bits_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :46:69]\n wire prs3_matches_2 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_0_bits_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :46:69]\n wire prs3_matches_3 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_0_bits_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :46:69]\n wire prs1_wakeups_0 = io_wakeup_ports_0_valid_0 & prs1_matches_0;\t// @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89]\n wire prs1_wakeups_1 = io_wakeup_ports_1_valid_0 & prs1_matches_1;\t// @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89]\n wire prs1_wakeups_2 = io_wakeup_ports_2_valid_0 & prs1_matches_2;\t// @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89]\n wire prs1_wakeups_3 = io_wakeup_ports_3_valid_0 & prs1_matches_3;\t// @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89]\n wire prs2_wakeups_0 = io_wakeup_ports_0_valid_0 & prs2_matches_0;\t// @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89]\n wire prs2_wakeups_1 = io_wakeup_ports_1_valid_0 & prs2_matches_1;\t// @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89]\n wire prs2_wakeups_2 = io_wakeup_ports_2_valid_0 & prs2_matches_2;\t// @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89]\n wire prs2_wakeups_3 = io_wakeup_ports_3_valid_0 & prs2_matches_3;\t// @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89]\n wire prs3_wakeups_0 = io_wakeup_ports_0_valid_0 & prs3_matches_0;\t// @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89]\n wire prs3_wakeups_1 = io_wakeup_ports_1_valid_0 & prs3_matches_1;\t// @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89]\n wire prs3_wakeups_2 = io_wakeup_ports_2_valid_0 & prs3_matches_2;\t// @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89]\n wire prs3_wakeups_3 = io_wakeup_ports_3_valid_0 & prs3_matches_3;\t// @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89]\n wire prs1_rebusys_0 = io_wakeup_ports_0_bits_rebusy_0 & prs1_matches_0;\t// @[issue-unit-age-ordered.scala:22:7, :44:69, :50:95]\n wire prs2_rebusys_0 = io_wakeup_ports_0_bits_rebusy_0 & prs2_matches_0;\t// @[issue-unit-age-ordered.scala:22:7, :45:69, :51:95]\n wire _T_2 = prs1_wakeups_0 | prs1_wakeups_1 | prs1_wakeups_2 | prs1_wakeups_3;\t// @[issue-unit-age-ordered.scala:47:89, :57:32]\n wire [1:0] _WIRE_iw_p1_speculative_child = _T_2 ? (prs1_wakeups_0 ? io_wakeup_ports_0_bits_speculative_mask_0 : 2'h0) | {prs1_wakeups_3, prs1_wakeups_2} : io_dis_uops_0_bits_iw_p1_speculative_child_0;\t// @[Mux.scala:30:73]\n wire _WIRE_iw_p1_bypass_hint = _T_2 & (prs1_wakeups_0 & io_wakeup_ports_0_bits_bypassable_0 | prs1_wakeups_2 | prs1_wakeups_3);\t// @[Mux.scala:30:73]\n wire _WIRE_prs1_busy = (|{prs1_rebusys_0, io_child_rebusys_0 & io_dis_uops_0_bits_iw_p1_speculative_child_0}) ? io_dis_uops_0_bits_lrs1_rtype_0 == 2'h0 : ~_T_2 & io_dis_uops_0_bits_prs1_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :35:17, :50:95, :57:{32,38}, :58:29, :62:{37,59,106,116}, :63:{29,63}]\n wire _T_26 = prs2_wakeups_0 | prs2_wakeups_1 | prs2_wakeups_2 | prs2_wakeups_3;\t// @[issue-unit-age-ordered.scala:48:89, :65:32]\n wire [1:0] _WIRE_iw_p2_speculative_child = _T_26 ? (prs2_wakeups_0 ? io_wakeup_ports_0_bits_speculative_mask_0 : 2'h0) | {prs2_wakeups_3, prs2_wakeups_2} : io_dis_uops_0_bits_iw_p2_speculative_child_0;\t// @[Mux.scala:30:73]\n wire _WIRE_iw_p2_bypass_hint = _T_26 & (prs2_wakeups_0 & io_wakeup_ports_0_bits_bypassable_0 | prs2_wakeups_2 | prs2_wakeups_3);\t// @[Mux.scala:30:73]\n wire _WIRE_prs2_busy = (|{prs2_rebusys_0, io_child_rebusys_0 & io_dis_uops_0_bits_iw_p2_speculative_child_0}) ? io_dis_uops_0_bits_lrs2_rtype_0 == 2'h0 : ~_T_26 & io_dis_uops_0_bits_prs2_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :35:17, :51:95, :65:{32,38}, :66:29, :71:{37,59,106,116}, :72:{29,63}]\n wire _T_50 = prs3_wakeups_0 | prs3_wakeups_1 | prs3_wakeups_2 | prs3_wakeups_3;\t// @[issue-unit-age-ordered.scala:49:89, :76:32]\n wire _WIRE_prs3_busy = ~_T_50 & io_dis_uops_0_bits_prs3_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :35:17, :76:{32,38}, :77:29]\n wire _WIRE_iw_p3_bypass_hint = _T_50 & (prs3_wakeups_0 & io_wakeup_ports_0_bits_bypassable_0 | prs3_wakeups_2 | prs3_wakeups_3);\t// @[Mux.scala:30:73]\n wire _WIRE_ppred_busy = ~(io_pred_wakeup_port_valid_0 & io_pred_wakeup_port_bits_0 == io_dis_uops_0_bits_ppred_0) & io_dis_uops_0_bits_ppred_busy_0;\t// @[issue-unit-age-ordered.scala:22:7, :35:17, :80:{37,65,96}, :81:30]\n wire prs1_matches_0_1 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_1_bits_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :44:69]\n wire prs1_matches_1_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_1_bits_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :44:69]\n wire prs1_matches_2_1 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_1_bits_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :44:69]\n wire prs1_matches_3_1 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_1_bits_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :44:69]\n wire prs2_matches_0_1 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_1_bits_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :45:69]\n wire prs2_matches_1_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_1_bits_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :45:69]\n wire prs2_matches_2_1 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_1_bits_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :45:69]\n wire prs2_matches_3_1 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_1_bits_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :45:69]\n wire prs3_matches_0_1 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_1_bits_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :46:69]\n wire prs3_matches_1_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_1_bits_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :46:69]\n wire prs3_matches_2_1 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_1_bits_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :46:69]\n wire prs3_matches_3_1 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_1_bits_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :46:69]\n wire prs1_wakeups_0_1 = io_wakeup_ports_0_valid_0 & prs1_matches_0_1;\t// @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89]\n wire prs1_wakeups_1_1 = io_wakeup_ports_1_valid_0 & prs1_matches_1_1;\t// @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89]\n wire prs1_wakeups_2_1 = io_wakeup_ports_2_valid_0 & prs1_matches_2_1;\t// @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89]\n wire prs1_wakeups_3_1 = io_wakeup_ports_3_valid_0 & prs1_matches_3_1;\t// @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89]\n wire prs2_wakeups_0_1 = io_wakeup_ports_0_valid_0 & prs2_matches_0_1;\t// @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89]\n wire prs2_wakeups_1_1 = io_wakeup_ports_1_valid_0 & prs2_matches_1_1;\t// @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89]\n wire prs2_wakeups_2_1 = io_wakeup_ports_2_valid_0 & prs2_matches_2_1;\t// @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89]\n wire prs2_wakeups_3_1 = io_wakeup_ports_3_valid_0 & prs2_matches_3_1;\t// @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89]\n wire prs3_wakeups_0_1 = io_wakeup_ports_0_valid_0 & prs3_matches_0_1;\t// @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89]\n wire prs3_wakeups_1_1 = io_wakeup_ports_1_valid_0 & prs3_matches_1_1;\t// @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89]\n wire prs3_wakeups_2_1 = io_wakeup_ports_2_valid_0 & prs3_matches_2_1;\t// @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89]\n wire prs3_wakeups_3_1 = io_wakeup_ports_3_valid_0 & prs3_matches_3_1;\t// @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89]\n wire prs1_rebusys_0_1 = io_wakeup_ports_0_bits_rebusy_0 & prs1_matches_0_1;\t// @[issue-unit-age-ordered.scala:22:7, :44:69, :50:95]\n wire prs2_rebusys_0_1 = io_wakeup_ports_0_bits_rebusy_0 & prs2_matches_0_1;\t// @[issue-unit-age-ordered.scala:22:7, :45:69, :51:95]\n wire _T_62 = prs1_wakeups_0_1 | prs1_wakeups_1_1 | prs1_wakeups_2_1 | prs1_wakeups_3_1;\t// @[issue-unit-age-ordered.scala:47:89, :57:32]\n wire _T_86 = prs2_wakeups_0_1 | prs2_wakeups_1_1 | prs2_wakeups_2_1 | prs2_wakeups_3_1;\t// @[issue-unit-age-ordered.scala:48:89, :65:32]\n wire _T_110 = prs3_wakeups_0_1 | prs3_wakeups_1_1 | prs3_wakeups_2_1 | prs3_wakeups_3_1;\t// @[issue-unit-age-ordered.scala:49:89, :76:32]\n wire _fu_code_match_T = issue_slots_0_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :253:25]\n wire _fu_code_match_T_18 = issue_slots_0_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :253:25]\n wire _fu_code_match_T_36 = issue_slots_1_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :253:25]\n wire _fu_code_match_T_54 = issue_slots_1_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :253:25]\n wire _issue_slots_1_clear_T;\t// @[issue-unit-age-ordered.scala:199:49]\n wire _fu_code_match_T_72 = issue_slots_2_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :253:25]\n wire _fu_code_match_T_90 = issue_slots_2_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :253:25]\n wire _issue_slots_2_clear_T;\t// @[issue-unit-age-ordered.scala:199:49]\n wire _fu_code_match_T_108 = issue_slots_3_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :253:25]\n wire _fu_code_match_T_126 = issue_slots_3_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :253:25]\n wire _issue_slots_3_clear_T;\t// @[issue-unit-age-ordered.scala:199:49]\n wire _fu_code_match_T_144 = issue_slots_4_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :253:25]\n wire _fu_code_match_T_162 = issue_slots_4_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :253:25]\n wire _issue_slots_4_clear_T;\t// @[issue-unit-age-ordered.scala:199:49]\n wire _fu_code_match_T_180 = issue_slots_5_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :253:25]\n wire _fu_code_match_T_198 = issue_slots_5_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :253:25]\n wire _issue_slots_5_clear_T;\t// @[issue-unit-age-ordered.scala:199:49]\n wire _fu_code_match_T_216 = issue_slots_6_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :253:25]\n wire _fu_code_match_T_234 = issue_slots_6_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :253:25]\n wire _issue_slots_6_clear_T;\t// @[issue-unit-age-ordered.scala:199:49]\n wire _fu_code_match_T_252 = issue_slots_7_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :253:25]\n wire _fu_code_match_T_270 = issue_slots_7_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :253:25]\n wire _issue_slots_7_clear_T;\t// @[issue-unit-age-ordered.scala:199:49]\n wire _fu_code_match_T_288 = issue_slots_8_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :253:25]\n wire _fu_code_match_T_306 = issue_slots_8_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :253:25]\n wire _issue_slots_8_clear_T;\t// @[issue-unit-age-ordered.scala:199:49]\n wire _fu_code_match_T_324 = issue_slots_9_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :253:25]\n wire _fu_code_match_T_342 = issue_slots_9_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :253:25]\n wire _issue_slots_9_clear_T;\t// @[issue-unit-age-ordered.scala:199:49]\n wire _fu_code_match_T_360 = issue_slots_10_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :253:25]\n wire _fu_code_match_T_378 = issue_slots_10_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :253:25]\n wire _issue_slots_10_clear_T;\t// @[issue-unit-age-ordered.scala:199:49]\n wire _fu_code_match_T_396 = issue_slots_11_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :253:25]\n wire _fu_code_match_T_414 = issue_slots_11_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :253:25]\n wire _issue_slots_11_clear_T;\t// @[issue-unit-age-ordered.scala:199:49]\n wire _fu_code_match_T_432 = issue_slots_12_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :253:25]\n wire _fu_code_match_T_450 = issue_slots_12_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :253:25]\n wire _issue_slots_12_clear_T;\t// @[issue-unit-age-ordered.scala:199:49]\n wire _fu_code_match_T_468 = issue_slots_13_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :253:25]\n wire _fu_code_match_T_486 = issue_slots_13_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :253:25]\n wire _issue_slots_13_clear_T;\t// @[issue-unit-age-ordered.scala:199:49]\n wire _fu_code_match_T_504 = issue_slots_14_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :253:25]\n wire _fu_code_match_T_522 = issue_slots_14_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :253:25]\n wire _issue_slots_14_clear_T;\t// @[issue-unit-age-ordered.scala:199:49]\n wire _fu_code_match_T_540 = issue_slots_15_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :253:25]\n wire _fu_code_match_T_558 = issue_slots_15_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :253:25]\n wire _issue_slots_15_clear_T;\t// @[issue-unit-age-ordered.scala:199:49]\n wire _fu_code_match_T_576 = issue_slots_16_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :253:25]\n wire _fu_code_match_T_594 = issue_slots_16_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :253:25]\n wire _issue_slots_16_clear_T;\t// @[issue-unit-age-ordered.scala:199:49]\n wire _fu_code_match_T_612 = issue_slots_17_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :253:25]\n wire _fu_code_match_T_630 = issue_slots_17_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :253:25]\n wire _issue_slots_17_clear_T;\t// @[issue-unit-age-ordered.scala:199:49]\n wire _fu_code_match_T_648 = issue_slots_18_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :253:25]\n wire _fu_code_match_T_666 = issue_slots_18_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :253:25]\n wire _issue_slots_18_clear_T;\t// @[issue-unit-age-ordered.scala:199:49]\n wire _fu_code_match_T_684 = issue_slots_19_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :253:25]\n wire _fu_code_match_T_702 = issue_slots_19_iss_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :253:25]\n wire _issue_slots_19_clear_T;\t// @[issue-unit-age-ordered.scala:199:49]\n wire issue_slots_0_iss_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_0_iss_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_0_iss_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_0_iss_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_0_iss_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_0_iss_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_0_iss_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_0_iss_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_0_iss_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_0_iss_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_0_iss_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_0_iss_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_0_iss_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_0_iss_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_0_iss_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_0_iss_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_0_iss_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_0_iss_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_0_iss_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_0_iss_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_0_iss_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_0_iss_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_0_iss_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_0_iss_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_0_iss_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_0_iss_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_0_iss_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_0_iss_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_0_iss_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_0_iss_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_0_iss_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_0_iss_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_0_iss_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_0_iss_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_0_iss_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_0_iss_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_0_iss_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_0_iss_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_0_iss_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_0_iss_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_0_iss_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_0_iss_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_0_iss_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_iss_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_0_iss_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_0_iss_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_0_in_uop_bits_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_0_in_uop_bits_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_0_in_uop_bits_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_0_in_uop_bits_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_0_in_uop_bits_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_0_in_uop_bits_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_0_in_uop_bits_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_0_in_uop_bits_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_0_in_uop_bits_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_0_in_uop_bits_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_0_in_uop_bits_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_0_in_uop_bits_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_0_in_uop_bits_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_0_in_uop_bits_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_0_in_uop_bits_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_0_in_uop_bits_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_0_in_uop_bits_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_0_in_uop_bits_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_0_in_uop_bits_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_0_in_uop_bits_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_0_in_uop_bits_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_0_in_uop_bits_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_0_in_uop_bits_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_0_in_uop_bits_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_0_in_uop_bits_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_0_in_uop_bits_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_0_in_uop_bits_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_0_in_uop_bits_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_0_in_uop_bits_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_0_in_uop_bits_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_0_in_uop_bits_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_0_in_uop_bits_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_0_in_uop_bits_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_0_in_uop_bits_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_0_in_uop_bits_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_0_in_uop_bits_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_0_in_uop_bits_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_0_in_uop_bits_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_0_in_uop_bits_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_0_in_uop_bits_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_0_in_uop_bits_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_0_in_uop_bits_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_bits_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_0_in_uop_bits_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_0_in_uop_bits_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_in_uop_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_0_out_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_0_out_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_0_out_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_0_out_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_0_out_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_0_out_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_0_out_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_0_out_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_0_out_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_0_out_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_0_out_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_0_out_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_0_out_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_0_out_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_0_out_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_0_out_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_0_out_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_0_out_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_0_out_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_0_out_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_0_out_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_0_out_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_0_out_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_0_out_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_0_out_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_0_out_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_0_out_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_0_out_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_0_out_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_0_out_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_0_out_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_0_out_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_0_out_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_0_out_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_0_out_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_0_out_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_0_out_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_0_out_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_0_out_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_0_out_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_0_out_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_0_out_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_out_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_0_out_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_0_out_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_will_be_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_request;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_0_grant;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_1_iss_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_1_iss_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_1_iss_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_1_iss_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_1_iss_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_1_iss_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_1_iss_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_1_iss_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_1_iss_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_1_iss_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_1_iss_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_1_iss_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_1_iss_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_1_iss_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_1_iss_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_1_iss_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_1_iss_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_1_iss_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_1_iss_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_1_iss_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_1_iss_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_1_iss_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_1_iss_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_1_iss_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_1_iss_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_1_iss_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_1_iss_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_1_iss_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_1_iss_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_1_iss_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_1_iss_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_1_iss_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_1_iss_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_1_iss_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_1_iss_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_1_iss_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_1_iss_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_1_iss_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_1_iss_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_1_iss_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_1_iss_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_1_iss_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_iss_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_1_iss_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_1_iss_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_1_in_uop_bits_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_1_in_uop_bits_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_1_in_uop_bits_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_1_in_uop_bits_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_1_in_uop_bits_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_1_in_uop_bits_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_1_in_uop_bits_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_1_in_uop_bits_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_1_in_uop_bits_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_1_in_uop_bits_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_1_in_uop_bits_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_1_in_uop_bits_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_1_in_uop_bits_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_1_in_uop_bits_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_1_in_uop_bits_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_1_in_uop_bits_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_1_in_uop_bits_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_1_in_uop_bits_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_1_in_uop_bits_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_1_in_uop_bits_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_1_in_uop_bits_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_1_in_uop_bits_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_1_in_uop_bits_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_1_in_uop_bits_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_1_in_uop_bits_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_1_in_uop_bits_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_1_in_uop_bits_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_1_in_uop_bits_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_1_in_uop_bits_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_1_in_uop_bits_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_1_in_uop_bits_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_1_in_uop_bits_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_1_in_uop_bits_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_1_in_uop_bits_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_1_in_uop_bits_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_1_in_uop_bits_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_1_in_uop_bits_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_1_in_uop_bits_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_1_in_uop_bits_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_1_in_uop_bits_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_1_in_uop_bits_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_1_in_uop_bits_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_bits_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_1_in_uop_bits_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_1_in_uop_bits_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_in_uop_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_1_out_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_1_out_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_1_out_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_1_out_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_1_out_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_1_out_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_1_out_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_1_out_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_1_out_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_1_out_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_1_out_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_1_out_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_1_out_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_1_out_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_1_out_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_1_out_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_1_out_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_1_out_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_1_out_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_1_out_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_1_out_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_1_out_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_1_out_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_1_out_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_1_out_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_1_out_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_1_out_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_1_out_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_1_out_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_1_out_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_1_out_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_1_out_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_1_out_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_1_out_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_1_out_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_1_out_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_1_out_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_1_out_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_1_out_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_1_out_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_1_out_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_1_out_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_out_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_1_out_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_1_out_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_will_be_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_request;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_grant;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_1_clear;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_2_iss_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_2_iss_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_2_iss_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_2_iss_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_2_iss_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_2_iss_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_2_iss_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_2_iss_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_2_iss_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_2_iss_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_2_iss_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_2_iss_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_2_iss_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_2_iss_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_2_iss_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_2_iss_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_2_iss_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_2_iss_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_2_iss_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_2_iss_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_2_iss_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_2_iss_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_2_iss_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_2_iss_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_2_iss_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_2_iss_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_2_iss_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_2_iss_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_2_iss_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_2_iss_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_2_iss_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_2_iss_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_2_iss_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_2_iss_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_2_iss_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_2_iss_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_2_iss_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_2_iss_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_2_iss_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_2_iss_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_2_iss_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_2_iss_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_iss_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_2_iss_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_2_iss_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_2_in_uop_bits_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_2_in_uop_bits_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_2_in_uop_bits_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_2_in_uop_bits_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_2_in_uop_bits_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_2_in_uop_bits_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_2_in_uop_bits_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_2_in_uop_bits_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_2_in_uop_bits_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_2_in_uop_bits_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_2_in_uop_bits_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_2_in_uop_bits_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_2_in_uop_bits_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_2_in_uop_bits_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_2_in_uop_bits_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_2_in_uop_bits_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_2_in_uop_bits_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_2_in_uop_bits_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_2_in_uop_bits_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_2_in_uop_bits_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_2_in_uop_bits_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_2_in_uop_bits_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_2_in_uop_bits_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_2_in_uop_bits_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_2_in_uop_bits_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_2_in_uop_bits_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_2_in_uop_bits_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_2_in_uop_bits_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_2_in_uop_bits_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_2_in_uop_bits_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_2_in_uop_bits_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_2_in_uop_bits_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_2_in_uop_bits_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_2_in_uop_bits_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_2_in_uop_bits_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_2_in_uop_bits_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_2_in_uop_bits_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_2_in_uop_bits_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_2_in_uop_bits_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_2_in_uop_bits_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_2_in_uop_bits_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_2_in_uop_bits_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_bits_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_2_in_uop_bits_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_2_in_uop_bits_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_in_uop_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_2_out_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_2_out_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_2_out_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_2_out_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_2_out_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_2_out_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_2_out_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_2_out_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_2_out_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_2_out_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_2_out_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_2_out_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_2_out_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_2_out_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_2_out_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_2_out_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_2_out_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_2_out_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_2_out_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_2_out_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_2_out_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_2_out_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_2_out_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_2_out_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_2_out_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_2_out_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_2_out_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_2_out_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_2_out_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_2_out_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_2_out_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_2_out_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_2_out_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_2_out_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_2_out_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_2_out_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_2_out_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_2_out_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_2_out_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_2_out_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_2_out_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_2_out_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_out_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_2_out_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_2_out_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_will_be_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_request;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_grant;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_2_clear;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_3_iss_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_3_iss_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_3_iss_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_3_iss_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_3_iss_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_3_iss_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_3_iss_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_3_iss_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_3_iss_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_3_iss_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_3_iss_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_3_iss_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_3_iss_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_3_iss_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_3_iss_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_3_iss_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_3_iss_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_3_iss_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_3_iss_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_3_iss_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_3_iss_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_3_iss_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_3_iss_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_3_iss_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_3_iss_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_3_iss_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_3_iss_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_3_iss_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_3_iss_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_3_iss_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_3_iss_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_3_iss_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_3_iss_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_3_iss_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_3_iss_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_3_iss_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_3_iss_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_3_iss_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_3_iss_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_3_iss_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_3_iss_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_3_iss_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_iss_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_3_iss_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_3_iss_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_3_in_uop_bits_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_3_in_uop_bits_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_3_in_uop_bits_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_3_in_uop_bits_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_3_in_uop_bits_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_3_in_uop_bits_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_3_in_uop_bits_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_3_in_uop_bits_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_3_in_uop_bits_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_3_in_uop_bits_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_3_in_uop_bits_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_3_in_uop_bits_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_3_in_uop_bits_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_3_in_uop_bits_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_3_in_uop_bits_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_3_in_uop_bits_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_3_in_uop_bits_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_3_in_uop_bits_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_3_in_uop_bits_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_3_in_uop_bits_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_3_in_uop_bits_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_3_in_uop_bits_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_3_in_uop_bits_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_3_in_uop_bits_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_3_in_uop_bits_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_3_in_uop_bits_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_3_in_uop_bits_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_3_in_uop_bits_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_3_in_uop_bits_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_3_in_uop_bits_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_3_in_uop_bits_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_3_in_uop_bits_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_3_in_uop_bits_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_3_in_uop_bits_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_3_in_uop_bits_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_3_in_uop_bits_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_3_in_uop_bits_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_3_in_uop_bits_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_3_in_uop_bits_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_3_in_uop_bits_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_3_in_uop_bits_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_3_in_uop_bits_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_bits_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_3_in_uop_bits_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_3_in_uop_bits_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_in_uop_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_3_out_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_3_out_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_3_out_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_3_out_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_3_out_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_3_out_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_3_out_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_3_out_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_3_out_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_3_out_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_3_out_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_3_out_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_3_out_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_3_out_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_3_out_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_3_out_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_3_out_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_3_out_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_3_out_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_3_out_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_3_out_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_3_out_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_3_out_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_3_out_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_3_out_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_3_out_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_3_out_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_3_out_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_3_out_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_3_out_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_3_out_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_3_out_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_3_out_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_3_out_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_3_out_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_3_out_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_3_out_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_3_out_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_3_out_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_3_out_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_3_out_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_3_out_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_out_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_3_out_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_3_out_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_will_be_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_request;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_grant;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_3_clear;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_4_iss_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_4_iss_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_4_iss_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_4_iss_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_4_iss_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_4_iss_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_4_iss_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_4_iss_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_4_iss_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_4_iss_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_4_iss_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_4_iss_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_4_iss_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_4_iss_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_4_iss_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_4_iss_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_4_iss_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_4_iss_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_4_iss_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_4_iss_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_4_iss_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_4_iss_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_4_iss_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_4_iss_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_4_iss_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_4_iss_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_4_iss_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_4_iss_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_4_iss_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_4_iss_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_4_iss_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_4_iss_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_4_iss_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_4_iss_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_4_iss_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_4_iss_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_4_iss_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_4_iss_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_4_iss_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_4_iss_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_4_iss_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_4_iss_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_iss_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_4_iss_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_4_iss_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_4_in_uop_bits_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_4_in_uop_bits_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_4_in_uop_bits_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_4_in_uop_bits_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_4_in_uop_bits_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_4_in_uop_bits_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_4_in_uop_bits_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_4_in_uop_bits_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_4_in_uop_bits_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_4_in_uop_bits_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_4_in_uop_bits_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_4_in_uop_bits_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_4_in_uop_bits_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_4_in_uop_bits_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_4_in_uop_bits_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_4_in_uop_bits_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_4_in_uop_bits_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_4_in_uop_bits_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_4_in_uop_bits_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_4_in_uop_bits_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_4_in_uop_bits_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_4_in_uop_bits_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_4_in_uop_bits_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_4_in_uop_bits_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_4_in_uop_bits_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_4_in_uop_bits_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_4_in_uop_bits_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_4_in_uop_bits_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_4_in_uop_bits_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_4_in_uop_bits_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_4_in_uop_bits_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_4_in_uop_bits_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_4_in_uop_bits_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_4_in_uop_bits_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_4_in_uop_bits_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_4_in_uop_bits_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_4_in_uop_bits_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_4_in_uop_bits_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_4_in_uop_bits_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_4_in_uop_bits_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_4_in_uop_bits_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_4_in_uop_bits_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_bits_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_4_in_uop_bits_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_4_in_uop_bits_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_in_uop_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_4_out_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_4_out_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_4_out_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_4_out_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_4_out_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_4_out_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_4_out_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_4_out_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_4_out_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_4_out_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_4_out_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_4_out_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_4_out_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_4_out_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_4_out_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_4_out_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_4_out_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_4_out_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_4_out_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_4_out_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_4_out_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_4_out_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_4_out_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_4_out_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_4_out_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_4_out_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_4_out_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_4_out_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_4_out_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_4_out_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_4_out_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_4_out_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_4_out_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_4_out_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_4_out_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_4_out_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_4_out_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_4_out_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_4_out_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_4_out_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_4_out_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_4_out_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_out_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_4_out_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_4_out_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_will_be_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_request;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_grant;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_4_clear;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_5_iss_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_5_iss_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_5_iss_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_5_iss_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_5_iss_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_5_iss_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_5_iss_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_5_iss_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_5_iss_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_5_iss_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_5_iss_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_5_iss_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_5_iss_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_5_iss_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_5_iss_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_5_iss_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_5_iss_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_5_iss_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_5_iss_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_5_iss_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_5_iss_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_5_iss_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_5_iss_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_5_iss_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_5_iss_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_5_iss_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_5_iss_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_5_iss_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_5_iss_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_5_iss_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_5_iss_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_5_iss_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_5_iss_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_5_iss_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_5_iss_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_5_iss_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_5_iss_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_5_iss_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_5_iss_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_5_iss_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_5_iss_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_5_iss_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_iss_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_5_iss_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_5_iss_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_5_in_uop_bits_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_5_in_uop_bits_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_5_in_uop_bits_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_5_in_uop_bits_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_5_in_uop_bits_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_5_in_uop_bits_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_5_in_uop_bits_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_5_in_uop_bits_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_5_in_uop_bits_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_5_in_uop_bits_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_5_in_uop_bits_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_5_in_uop_bits_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_5_in_uop_bits_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_5_in_uop_bits_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_5_in_uop_bits_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_5_in_uop_bits_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_5_in_uop_bits_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_5_in_uop_bits_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_5_in_uop_bits_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_5_in_uop_bits_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_5_in_uop_bits_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_5_in_uop_bits_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_5_in_uop_bits_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_5_in_uop_bits_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_5_in_uop_bits_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_5_in_uop_bits_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_5_in_uop_bits_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_5_in_uop_bits_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_5_in_uop_bits_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_5_in_uop_bits_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_5_in_uop_bits_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_5_in_uop_bits_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_5_in_uop_bits_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_5_in_uop_bits_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_5_in_uop_bits_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_5_in_uop_bits_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_5_in_uop_bits_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_5_in_uop_bits_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_5_in_uop_bits_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_5_in_uop_bits_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_5_in_uop_bits_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_5_in_uop_bits_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_bits_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_5_in_uop_bits_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_5_in_uop_bits_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_in_uop_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_5_out_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_5_out_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_5_out_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_5_out_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_5_out_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_5_out_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_5_out_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_5_out_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_5_out_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_5_out_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_5_out_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_5_out_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_5_out_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_5_out_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_5_out_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_5_out_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_5_out_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_5_out_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_5_out_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_5_out_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_5_out_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_5_out_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_5_out_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_5_out_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_5_out_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_5_out_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_5_out_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_5_out_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_5_out_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_5_out_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_5_out_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_5_out_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_5_out_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_5_out_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_5_out_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_5_out_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_5_out_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_5_out_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_5_out_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_5_out_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_5_out_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_5_out_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_out_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_5_out_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_5_out_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_will_be_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_request;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_grant;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_5_clear;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_6_iss_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_6_iss_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_6_iss_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_6_iss_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_6_iss_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_6_iss_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_6_iss_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_6_iss_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_6_iss_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_6_iss_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_6_iss_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_6_iss_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_6_iss_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_6_iss_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_6_iss_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_6_iss_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_6_iss_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_6_iss_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_6_iss_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_6_iss_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_6_iss_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_6_iss_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_6_iss_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_6_iss_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_6_iss_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_6_iss_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_6_iss_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_6_iss_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_6_iss_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_6_iss_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_6_iss_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_6_iss_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_6_iss_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_6_iss_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_6_iss_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_6_iss_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_6_iss_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_6_iss_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_6_iss_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_6_iss_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_6_iss_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_6_iss_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_iss_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_6_iss_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_6_iss_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_6_in_uop_bits_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_6_in_uop_bits_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_6_in_uop_bits_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_6_in_uop_bits_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_6_in_uop_bits_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_6_in_uop_bits_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_6_in_uop_bits_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_6_in_uop_bits_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_6_in_uop_bits_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_6_in_uop_bits_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_6_in_uop_bits_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_6_in_uop_bits_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_6_in_uop_bits_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_6_in_uop_bits_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_6_in_uop_bits_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_6_in_uop_bits_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_6_in_uop_bits_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_6_in_uop_bits_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_6_in_uop_bits_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_6_in_uop_bits_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_6_in_uop_bits_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_6_in_uop_bits_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_6_in_uop_bits_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_6_in_uop_bits_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_6_in_uop_bits_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_6_in_uop_bits_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_6_in_uop_bits_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_6_in_uop_bits_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_6_in_uop_bits_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_6_in_uop_bits_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_6_in_uop_bits_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_6_in_uop_bits_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_6_in_uop_bits_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_6_in_uop_bits_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_6_in_uop_bits_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_6_in_uop_bits_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_6_in_uop_bits_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_6_in_uop_bits_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_6_in_uop_bits_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_6_in_uop_bits_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_6_in_uop_bits_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_6_in_uop_bits_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_bits_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_6_in_uop_bits_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_6_in_uop_bits_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_in_uop_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_6_out_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_6_out_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_6_out_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_6_out_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_6_out_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_6_out_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_6_out_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_6_out_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_6_out_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_6_out_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_6_out_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_6_out_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_6_out_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_6_out_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_6_out_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_6_out_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_6_out_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_6_out_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_6_out_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_6_out_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_6_out_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_6_out_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_6_out_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_6_out_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_6_out_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_6_out_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_6_out_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_6_out_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_6_out_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_6_out_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_6_out_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_6_out_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_6_out_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_6_out_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_6_out_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_6_out_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_6_out_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_6_out_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_6_out_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_6_out_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_6_out_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_6_out_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_out_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_6_out_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_6_out_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_will_be_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_request;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_grant;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_6_clear;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_7_iss_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_7_iss_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_7_iss_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_7_iss_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_7_iss_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_7_iss_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_7_iss_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_7_iss_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_7_iss_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_7_iss_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_7_iss_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_7_iss_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_7_iss_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_7_iss_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_7_iss_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_7_iss_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_7_iss_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_7_iss_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_7_iss_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_7_iss_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_7_iss_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_7_iss_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_7_iss_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_7_iss_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_7_iss_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_7_iss_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_7_iss_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_7_iss_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_7_iss_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_7_iss_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_7_iss_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_7_iss_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_7_iss_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_7_iss_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_7_iss_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_7_iss_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_7_iss_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_7_iss_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_7_iss_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_7_iss_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_7_iss_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_7_iss_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_iss_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_7_iss_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_7_iss_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_7_in_uop_bits_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_7_in_uop_bits_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_7_in_uop_bits_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_7_in_uop_bits_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_7_in_uop_bits_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_7_in_uop_bits_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_7_in_uop_bits_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_7_in_uop_bits_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_7_in_uop_bits_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_7_in_uop_bits_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_7_in_uop_bits_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_7_in_uop_bits_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_7_in_uop_bits_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_7_in_uop_bits_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_7_in_uop_bits_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_7_in_uop_bits_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_7_in_uop_bits_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_7_in_uop_bits_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_7_in_uop_bits_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_7_in_uop_bits_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_7_in_uop_bits_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_7_in_uop_bits_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_7_in_uop_bits_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_7_in_uop_bits_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_7_in_uop_bits_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_7_in_uop_bits_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_7_in_uop_bits_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_7_in_uop_bits_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_7_in_uop_bits_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_7_in_uop_bits_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_7_in_uop_bits_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_7_in_uop_bits_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_7_in_uop_bits_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_7_in_uop_bits_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_7_in_uop_bits_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_7_in_uop_bits_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_7_in_uop_bits_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_7_in_uop_bits_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_7_in_uop_bits_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_7_in_uop_bits_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_7_in_uop_bits_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_7_in_uop_bits_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_bits_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_7_in_uop_bits_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_7_in_uop_bits_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_in_uop_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_7_out_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_7_out_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_7_out_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_7_out_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_7_out_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_7_out_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_7_out_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_7_out_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_7_out_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_7_out_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_7_out_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_7_out_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_7_out_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_7_out_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_7_out_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_7_out_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_7_out_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_7_out_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_7_out_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_7_out_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_7_out_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_7_out_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_7_out_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_7_out_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_7_out_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_7_out_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_7_out_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_7_out_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_7_out_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_7_out_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_7_out_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_7_out_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_7_out_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_7_out_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_7_out_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_7_out_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_7_out_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_7_out_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_7_out_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_7_out_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_7_out_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_7_out_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_out_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_7_out_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_7_out_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_will_be_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_request;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_grant;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_7_clear;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_8_iss_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_8_iss_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_8_iss_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_8_iss_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_8_iss_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_8_iss_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_8_iss_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_8_iss_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_8_iss_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_8_iss_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_8_iss_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_8_iss_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_8_iss_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_8_iss_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_8_iss_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_8_iss_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_8_iss_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_8_iss_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_8_iss_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_8_iss_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_8_iss_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_8_iss_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_8_iss_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_8_iss_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_8_iss_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_8_iss_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_8_iss_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_8_iss_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_8_iss_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_8_iss_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_8_iss_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_8_iss_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_8_iss_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_8_iss_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_8_iss_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_8_iss_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_8_iss_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_8_iss_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_8_iss_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_8_iss_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_8_iss_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_8_iss_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_iss_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_8_iss_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_8_iss_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_8_in_uop_bits_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_8_in_uop_bits_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_8_in_uop_bits_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_8_in_uop_bits_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_8_in_uop_bits_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_8_in_uop_bits_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_8_in_uop_bits_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_8_in_uop_bits_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_8_in_uop_bits_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_8_in_uop_bits_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_8_in_uop_bits_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_8_in_uop_bits_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_8_in_uop_bits_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_8_in_uop_bits_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_8_in_uop_bits_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_8_in_uop_bits_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_8_in_uop_bits_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_8_in_uop_bits_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_8_in_uop_bits_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_8_in_uop_bits_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_8_in_uop_bits_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_8_in_uop_bits_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_8_in_uop_bits_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_8_in_uop_bits_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_8_in_uop_bits_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_8_in_uop_bits_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_8_in_uop_bits_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_8_in_uop_bits_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_8_in_uop_bits_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_8_in_uop_bits_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_8_in_uop_bits_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_8_in_uop_bits_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_8_in_uop_bits_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_8_in_uop_bits_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_8_in_uop_bits_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_8_in_uop_bits_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_8_in_uop_bits_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_8_in_uop_bits_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_8_in_uop_bits_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_8_in_uop_bits_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_8_in_uop_bits_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_8_in_uop_bits_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_bits_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_8_in_uop_bits_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_8_in_uop_bits_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_in_uop_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_8_out_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_8_out_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_8_out_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_8_out_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_8_out_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_8_out_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_8_out_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_8_out_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_8_out_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_8_out_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_8_out_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_8_out_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_8_out_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_8_out_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_8_out_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_8_out_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_8_out_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_8_out_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_8_out_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_8_out_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_8_out_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_8_out_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_8_out_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_8_out_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_8_out_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_8_out_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_8_out_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_8_out_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_8_out_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_8_out_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_8_out_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_8_out_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_8_out_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_8_out_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_8_out_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_8_out_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_8_out_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_8_out_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_8_out_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_8_out_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_8_out_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_8_out_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_out_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_8_out_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_8_out_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_will_be_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_request;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_grant;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_8_clear;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_9_iss_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_9_iss_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_9_iss_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_9_iss_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_9_iss_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_9_iss_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_9_iss_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_9_iss_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_9_iss_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_9_iss_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_9_iss_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_9_iss_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_9_iss_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_9_iss_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_9_iss_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_9_iss_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_9_iss_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_9_iss_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_9_iss_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_9_iss_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_9_iss_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_9_iss_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_9_iss_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_9_iss_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_9_iss_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_9_iss_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_9_iss_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_9_iss_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_9_iss_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_9_iss_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_9_iss_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_9_iss_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_9_iss_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_9_iss_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_9_iss_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_9_iss_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_9_iss_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_9_iss_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_9_iss_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_9_iss_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_9_iss_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_9_iss_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_iss_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_9_iss_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_9_iss_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_9_in_uop_bits_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_9_in_uop_bits_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_9_in_uop_bits_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_9_in_uop_bits_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_9_in_uop_bits_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_9_in_uop_bits_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_9_in_uop_bits_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_9_in_uop_bits_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_9_in_uop_bits_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_9_in_uop_bits_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_9_in_uop_bits_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_9_in_uop_bits_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_9_in_uop_bits_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_9_in_uop_bits_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_9_in_uop_bits_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_9_in_uop_bits_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_9_in_uop_bits_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_9_in_uop_bits_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_9_in_uop_bits_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_9_in_uop_bits_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_9_in_uop_bits_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_9_in_uop_bits_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_9_in_uop_bits_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_9_in_uop_bits_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_9_in_uop_bits_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_9_in_uop_bits_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_9_in_uop_bits_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_9_in_uop_bits_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_9_in_uop_bits_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_9_in_uop_bits_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_9_in_uop_bits_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_9_in_uop_bits_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_9_in_uop_bits_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_9_in_uop_bits_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_9_in_uop_bits_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_9_in_uop_bits_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_9_in_uop_bits_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_9_in_uop_bits_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_9_in_uop_bits_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_9_in_uop_bits_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_9_in_uop_bits_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_9_in_uop_bits_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_bits_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_9_in_uop_bits_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_9_in_uop_bits_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_in_uop_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_9_out_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_9_out_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_9_out_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_9_out_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_9_out_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_9_out_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_9_out_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_9_out_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_9_out_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_9_out_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_9_out_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_9_out_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_9_out_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_9_out_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_9_out_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_9_out_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_9_out_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_9_out_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_9_out_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_9_out_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_9_out_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_9_out_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_9_out_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_9_out_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_9_out_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_9_out_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_9_out_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_9_out_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_9_out_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_9_out_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_9_out_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_9_out_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_9_out_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_9_out_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_9_out_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_9_out_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_9_out_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_9_out_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_9_out_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_9_out_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_9_out_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_9_out_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_out_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_9_out_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_9_out_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_will_be_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_request;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_grant;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_9_clear;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_10_iss_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_10_iss_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_10_iss_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_10_iss_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_10_iss_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_10_iss_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_10_iss_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_10_iss_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_10_iss_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_10_iss_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_10_iss_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_10_iss_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_10_iss_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_10_iss_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_10_iss_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_10_iss_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_10_iss_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_10_iss_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_10_iss_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_10_iss_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_10_iss_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_10_iss_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_10_iss_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_10_iss_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_10_iss_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_10_iss_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_10_iss_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_10_iss_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_10_iss_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_10_iss_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_10_iss_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_10_iss_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_10_iss_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_10_iss_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_10_iss_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_10_iss_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_10_iss_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_10_iss_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_10_iss_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_10_iss_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_10_iss_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_10_iss_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_iss_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_10_iss_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_10_iss_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_10_in_uop_bits_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_10_in_uop_bits_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_10_in_uop_bits_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_10_in_uop_bits_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_10_in_uop_bits_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_10_in_uop_bits_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_10_in_uop_bits_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_10_in_uop_bits_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_10_in_uop_bits_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_10_in_uop_bits_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_10_in_uop_bits_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_10_in_uop_bits_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_10_in_uop_bits_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_10_in_uop_bits_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_10_in_uop_bits_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_10_in_uop_bits_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_10_in_uop_bits_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_10_in_uop_bits_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_10_in_uop_bits_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_10_in_uop_bits_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_10_in_uop_bits_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_10_in_uop_bits_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_10_in_uop_bits_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_10_in_uop_bits_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_10_in_uop_bits_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_10_in_uop_bits_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_10_in_uop_bits_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_10_in_uop_bits_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_10_in_uop_bits_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_10_in_uop_bits_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_10_in_uop_bits_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_10_in_uop_bits_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_10_in_uop_bits_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_10_in_uop_bits_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_10_in_uop_bits_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_10_in_uop_bits_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_10_in_uop_bits_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_10_in_uop_bits_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_10_in_uop_bits_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_10_in_uop_bits_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_10_in_uop_bits_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_10_in_uop_bits_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_bits_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_10_in_uop_bits_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_10_in_uop_bits_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_in_uop_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_10_out_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_10_out_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_10_out_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_10_out_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_10_out_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_10_out_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_10_out_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_10_out_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_10_out_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_10_out_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_10_out_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_10_out_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_10_out_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_10_out_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_10_out_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_10_out_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_10_out_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_10_out_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_10_out_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_10_out_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_10_out_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_10_out_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_10_out_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_10_out_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_10_out_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_10_out_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_10_out_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_10_out_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_10_out_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_10_out_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_10_out_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_10_out_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_10_out_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_10_out_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_10_out_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_10_out_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_10_out_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_10_out_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_10_out_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_10_out_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_10_out_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_10_out_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_out_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_10_out_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_10_out_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_will_be_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_request;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_grant;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_10_clear;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_11_iss_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_11_iss_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_11_iss_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_11_iss_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_11_iss_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_11_iss_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_11_iss_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_11_iss_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_11_iss_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_11_iss_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_11_iss_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_11_iss_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_11_iss_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_11_iss_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_11_iss_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_11_iss_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_11_iss_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_11_iss_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_11_iss_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_11_iss_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_11_iss_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_11_iss_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_11_iss_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_11_iss_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_11_iss_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_11_iss_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_11_iss_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_11_iss_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_11_iss_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_11_iss_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_11_iss_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_11_iss_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_11_iss_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_11_iss_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_11_iss_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_11_iss_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_11_iss_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_11_iss_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_11_iss_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_11_iss_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_11_iss_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_11_iss_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_iss_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_11_iss_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_11_iss_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_11_in_uop_bits_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_11_in_uop_bits_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_11_in_uop_bits_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_11_in_uop_bits_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_11_in_uop_bits_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_11_in_uop_bits_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_11_in_uop_bits_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_11_in_uop_bits_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_11_in_uop_bits_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_11_in_uop_bits_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_11_in_uop_bits_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_11_in_uop_bits_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_11_in_uop_bits_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_11_in_uop_bits_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_11_in_uop_bits_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_11_in_uop_bits_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_11_in_uop_bits_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_11_in_uop_bits_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_11_in_uop_bits_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_11_in_uop_bits_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_11_in_uop_bits_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_11_in_uop_bits_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_11_in_uop_bits_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_11_in_uop_bits_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_11_in_uop_bits_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_11_in_uop_bits_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_11_in_uop_bits_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_11_in_uop_bits_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_11_in_uop_bits_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_11_in_uop_bits_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_11_in_uop_bits_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_11_in_uop_bits_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_11_in_uop_bits_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_11_in_uop_bits_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_11_in_uop_bits_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_11_in_uop_bits_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_11_in_uop_bits_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_11_in_uop_bits_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_11_in_uop_bits_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_11_in_uop_bits_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_11_in_uop_bits_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_11_in_uop_bits_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_bits_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_11_in_uop_bits_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_11_in_uop_bits_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_in_uop_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_11_out_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_11_out_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_11_out_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_11_out_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_11_out_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_11_out_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_11_out_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_11_out_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_11_out_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_11_out_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_11_out_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_11_out_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_11_out_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_11_out_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_11_out_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_11_out_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_11_out_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_11_out_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_11_out_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_11_out_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_11_out_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_11_out_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_11_out_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_11_out_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_11_out_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_11_out_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_11_out_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_11_out_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_11_out_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_11_out_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_11_out_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_11_out_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_11_out_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_11_out_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_11_out_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_11_out_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_11_out_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_11_out_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_11_out_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_11_out_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_11_out_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_11_out_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_out_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_11_out_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_11_out_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_will_be_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_request;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_grant;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_11_clear;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_12_iss_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_12_iss_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_12_iss_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_12_iss_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_12_iss_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_12_iss_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_12_iss_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_12_iss_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_12_iss_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_12_iss_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_12_iss_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_12_iss_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_12_iss_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_12_iss_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_12_iss_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_12_iss_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_12_iss_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_12_iss_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_12_iss_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_12_iss_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_12_iss_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_12_iss_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_12_iss_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_12_iss_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_12_iss_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_12_iss_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_12_iss_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_12_iss_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_12_iss_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_12_iss_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_12_iss_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_12_iss_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_12_iss_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_12_iss_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_12_iss_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_12_iss_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_12_iss_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_12_iss_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_12_iss_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_12_iss_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_12_iss_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_12_iss_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_iss_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_12_iss_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_12_iss_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_12_in_uop_bits_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_12_in_uop_bits_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_12_in_uop_bits_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_12_in_uop_bits_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_12_in_uop_bits_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_12_in_uop_bits_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_12_in_uop_bits_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_12_in_uop_bits_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_12_in_uop_bits_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_12_in_uop_bits_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_12_in_uop_bits_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_12_in_uop_bits_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_12_in_uop_bits_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_12_in_uop_bits_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_12_in_uop_bits_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_12_in_uop_bits_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_12_in_uop_bits_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_12_in_uop_bits_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_12_in_uop_bits_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_12_in_uop_bits_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_12_in_uop_bits_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_12_in_uop_bits_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_12_in_uop_bits_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_12_in_uop_bits_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_12_in_uop_bits_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_12_in_uop_bits_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_12_in_uop_bits_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_12_in_uop_bits_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_12_in_uop_bits_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_12_in_uop_bits_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_12_in_uop_bits_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_12_in_uop_bits_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_12_in_uop_bits_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_12_in_uop_bits_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_12_in_uop_bits_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_12_in_uop_bits_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_12_in_uop_bits_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_12_in_uop_bits_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_12_in_uop_bits_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_12_in_uop_bits_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_12_in_uop_bits_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_12_in_uop_bits_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_bits_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_12_in_uop_bits_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_12_in_uop_bits_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_in_uop_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_12_out_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_12_out_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_12_out_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_12_out_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_12_out_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_12_out_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_12_out_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_12_out_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_12_out_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_12_out_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_12_out_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_12_out_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_12_out_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_12_out_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_12_out_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_12_out_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_12_out_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_12_out_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_12_out_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_12_out_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_12_out_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_12_out_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_12_out_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_12_out_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_12_out_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_12_out_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_12_out_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_12_out_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_12_out_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_12_out_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_12_out_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_12_out_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_12_out_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_12_out_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_12_out_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_12_out_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_12_out_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_12_out_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_12_out_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_12_out_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_12_out_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_12_out_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_out_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_12_out_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_12_out_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_will_be_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_request;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_grant;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_12_clear;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_13_iss_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_13_iss_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_13_iss_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_13_iss_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_13_iss_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_13_iss_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_13_iss_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_13_iss_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_13_iss_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_13_iss_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_13_iss_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_13_iss_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_13_iss_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_13_iss_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_13_iss_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_13_iss_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_13_iss_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_13_iss_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_13_iss_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_13_iss_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_13_iss_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_13_iss_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_13_iss_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_13_iss_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_13_iss_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_13_iss_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_13_iss_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_13_iss_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_13_iss_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_13_iss_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_13_iss_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_13_iss_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_13_iss_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_13_iss_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_13_iss_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_13_iss_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_13_iss_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_13_iss_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_13_iss_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_13_iss_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_13_iss_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_13_iss_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_iss_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_13_iss_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_13_iss_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_13_in_uop_bits_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_13_in_uop_bits_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_13_in_uop_bits_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_13_in_uop_bits_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_13_in_uop_bits_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_13_in_uop_bits_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_13_in_uop_bits_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_13_in_uop_bits_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_13_in_uop_bits_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_13_in_uop_bits_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_13_in_uop_bits_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_13_in_uop_bits_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_13_in_uop_bits_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_13_in_uop_bits_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_13_in_uop_bits_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_13_in_uop_bits_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_13_in_uop_bits_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_13_in_uop_bits_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_13_in_uop_bits_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_13_in_uop_bits_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_13_in_uop_bits_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_13_in_uop_bits_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_13_in_uop_bits_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_13_in_uop_bits_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_13_in_uop_bits_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_13_in_uop_bits_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_13_in_uop_bits_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_13_in_uop_bits_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_13_in_uop_bits_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_13_in_uop_bits_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_13_in_uop_bits_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_13_in_uop_bits_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_13_in_uop_bits_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_13_in_uop_bits_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_13_in_uop_bits_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_13_in_uop_bits_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_13_in_uop_bits_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_13_in_uop_bits_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_13_in_uop_bits_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_13_in_uop_bits_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_13_in_uop_bits_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_13_in_uop_bits_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_bits_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_13_in_uop_bits_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_13_in_uop_bits_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_in_uop_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_13_out_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_13_out_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_13_out_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_13_out_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_13_out_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_13_out_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_13_out_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_13_out_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_13_out_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_13_out_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_13_out_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_13_out_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_13_out_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_13_out_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_13_out_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_13_out_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_13_out_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_13_out_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_13_out_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_13_out_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_13_out_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_13_out_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_13_out_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_13_out_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_13_out_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_13_out_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_13_out_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_13_out_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_13_out_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_13_out_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_13_out_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_13_out_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_13_out_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_13_out_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_13_out_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_13_out_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_13_out_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_13_out_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_13_out_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_13_out_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_13_out_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_13_out_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_out_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_13_out_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_13_out_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_will_be_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_request;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_grant;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_13_clear;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_14_iss_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_14_iss_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_14_iss_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_14_iss_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_14_iss_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_14_iss_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_14_iss_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_14_iss_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_14_iss_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_14_iss_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_14_iss_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_14_iss_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_14_iss_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_14_iss_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_14_iss_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_14_iss_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_14_iss_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_14_iss_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_14_iss_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_14_iss_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_14_iss_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_14_iss_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_14_iss_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_14_iss_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_14_iss_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_14_iss_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_14_iss_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_14_iss_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_14_iss_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_14_iss_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_14_iss_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_14_iss_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_14_iss_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_14_iss_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_14_iss_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_14_iss_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_14_iss_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_14_iss_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_14_iss_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_14_iss_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_14_iss_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_14_iss_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_iss_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_14_iss_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_14_iss_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_14_in_uop_bits_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_14_in_uop_bits_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_14_in_uop_bits_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_14_in_uop_bits_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_14_in_uop_bits_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_14_in_uop_bits_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_14_in_uop_bits_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_14_in_uop_bits_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_14_in_uop_bits_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_14_in_uop_bits_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_14_in_uop_bits_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_14_in_uop_bits_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_14_in_uop_bits_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_14_in_uop_bits_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_14_in_uop_bits_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_14_in_uop_bits_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_14_in_uop_bits_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_14_in_uop_bits_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_14_in_uop_bits_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_14_in_uop_bits_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_14_in_uop_bits_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_14_in_uop_bits_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_14_in_uop_bits_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_14_in_uop_bits_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_14_in_uop_bits_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_14_in_uop_bits_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_14_in_uop_bits_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_14_in_uop_bits_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_14_in_uop_bits_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_14_in_uop_bits_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_14_in_uop_bits_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_14_in_uop_bits_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_14_in_uop_bits_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_14_in_uop_bits_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_14_in_uop_bits_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_14_in_uop_bits_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_14_in_uop_bits_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_14_in_uop_bits_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_14_in_uop_bits_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_14_in_uop_bits_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_14_in_uop_bits_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_14_in_uop_bits_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_bits_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_14_in_uop_bits_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_14_in_uop_bits_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_in_uop_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_14_out_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_14_out_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_14_out_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_14_out_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_14_out_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_14_out_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_14_out_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_14_out_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_14_out_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_14_out_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_14_out_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_14_out_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_14_out_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_14_out_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_14_out_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_14_out_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_14_out_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_14_out_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_14_out_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_14_out_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_14_out_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_14_out_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_14_out_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_14_out_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_14_out_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_14_out_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_14_out_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_14_out_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_14_out_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_14_out_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_14_out_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_14_out_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_14_out_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_14_out_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_14_out_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_14_out_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_14_out_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_14_out_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_14_out_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_14_out_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_14_out_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_14_out_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_out_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_14_out_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_14_out_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_will_be_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_request;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_grant;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_14_clear;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_15_iss_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_15_iss_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_15_iss_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_15_iss_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_15_iss_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_15_iss_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_15_iss_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_15_iss_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_15_iss_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_15_iss_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_15_iss_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_15_iss_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_15_iss_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_15_iss_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_15_iss_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_15_iss_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_15_iss_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_15_iss_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_15_iss_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_15_iss_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_15_iss_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_15_iss_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_15_iss_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_15_iss_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_15_iss_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_15_iss_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_15_iss_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_15_iss_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_15_iss_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_15_iss_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_15_iss_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_15_iss_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_15_iss_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_15_iss_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_15_iss_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_15_iss_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_15_iss_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_15_iss_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_15_iss_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_15_iss_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_15_iss_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_15_iss_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_iss_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_15_iss_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_15_iss_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_15_in_uop_bits_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_15_in_uop_bits_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_15_in_uop_bits_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_15_in_uop_bits_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_15_in_uop_bits_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_15_in_uop_bits_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_15_in_uop_bits_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_15_in_uop_bits_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_15_in_uop_bits_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_15_in_uop_bits_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_15_in_uop_bits_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_15_in_uop_bits_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_15_in_uop_bits_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_15_in_uop_bits_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_15_in_uop_bits_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_15_in_uop_bits_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_15_in_uop_bits_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_15_in_uop_bits_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_15_in_uop_bits_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_15_in_uop_bits_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_15_in_uop_bits_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_15_in_uop_bits_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_15_in_uop_bits_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_15_in_uop_bits_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_15_in_uop_bits_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_15_in_uop_bits_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_15_in_uop_bits_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_15_in_uop_bits_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_15_in_uop_bits_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_15_in_uop_bits_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_15_in_uop_bits_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_15_in_uop_bits_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_15_in_uop_bits_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_15_in_uop_bits_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_15_in_uop_bits_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_15_in_uop_bits_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_15_in_uop_bits_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_15_in_uop_bits_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_15_in_uop_bits_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_15_in_uop_bits_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_15_in_uop_bits_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_15_in_uop_bits_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_bits_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_15_in_uop_bits_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_15_in_uop_bits_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_in_uop_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_15_out_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_15_out_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_15_out_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_15_out_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_15_out_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_15_out_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_15_out_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_15_out_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_15_out_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_15_out_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_15_out_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_15_out_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_15_out_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_15_out_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_15_out_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_15_out_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_15_out_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_15_out_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_15_out_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_15_out_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_15_out_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_15_out_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_15_out_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_15_out_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_15_out_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_15_out_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_15_out_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_15_out_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_15_out_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_15_out_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_15_out_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_15_out_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_15_out_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_15_out_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_15_out_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_15_out_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_15_out_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_15_out_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_15_out_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_15_out_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_15_out_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_15_out_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_out_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_15_out_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_15_out_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_will_be_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_request;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_grant;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_15_clear;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_16_iss_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_16_iss_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_16_iss_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_16_iss_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_16_iss_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_16_iss_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_16_iss_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_16_iss_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_16_iss_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_16_iss_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_16_iss_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_16_iss_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_16_iss_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_16_iss_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_16_iss_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_16_iss_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_16_iss_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_16_iss_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_16_iss_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_16_iss_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_16_iss_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_16_iss_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_16_iss_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_16_iss_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_16_iss_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_16_iss_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_16_iss_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_16_iss_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_16_iss_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_16_iss_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_16_iss_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_16_iss_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_16_iss_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_16_iss_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_16_iss_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_16_iss_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_16_iss_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_16_iss_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_16_iss_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_16_iss_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_16_iss_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_16_iss_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_iss_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_16_iss_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_16_iss_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_16_in_uop_bits_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_16_in_uop_bits_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_16_in_uop_bits_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_16_in_uop_bits_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_16_in_uop_bits_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_16_in_uop_bits_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_16_in_uop_bits_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_16_in_uop_bits_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_16_in_uop_bits_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_16_in_uop_bits_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_16_in_uop_bits_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_16_in_uop_bits_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_16_in_uop_bits_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_16_in_uop_bits_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_16_in_uop_bits_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_16_in_uop_bits_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_16_in_uop_bits_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_16_in_uop_bits_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_16_in_uop_bits_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_16_in_uop_bits_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_16_in_uop_bits_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_16_in_uop_bits_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_16_in_uop_bits_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_16_in_uop_bits_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_16_in_uop_bits_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_16_in_uop_bits_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_16_in_uop_bits_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_16_in_uop_bits_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_16_in_uop_bits_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_16_in_uop_bits_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_16_in_uop_bits_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_16_in_uop_bits_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_16_in_uop_bits_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_16_in_uop_bits_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_16_in_uop_bits_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_16_in_uop_bits_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_16_in_uop_bits_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_16_in_uop_bits_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_16_in_uop_bits_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_16_in_uop_bits_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_16_in_uop_bits_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_16_in_uop_bits_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_bits_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_16_in_uop_bits_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_16_in_uop_bits_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_in_uop_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_16_out_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_16_out_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_16_out_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_16_out_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_16_out_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_16_out_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_16_out_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_16_out_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_16_out_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_16_out_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_16_out_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_16_out_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_16_out_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_16_out_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_16_out_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_16_out_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_16_out_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_16_out_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_16_out_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_16_out_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_16_out_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_16_out_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_16_out_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_16_out_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_16_out_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_16_out_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_16_out_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_16_out_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_16_out_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_16_out_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_16_out_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_16_out_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_16_out_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_16_out_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_16_out_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_16_out_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_16_out_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_16_out_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_16_out_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_16_out_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_16_out_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_16_out_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_out_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_16_out_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_16_out_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_will_be_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_request;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_grant;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_16_clear;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_17_iss_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_17_iss_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_17_iss_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_17_iss_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_17_iss_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_17_iss_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_17_iss_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_17_iss_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_17_iss_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_17_iss_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_17_iss_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_17_iss_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_17_iss_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_17_iss_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_17_iss_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_17_iss_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_17_iss_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_17_iss_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_17_iss_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_17_iss_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_17_iss_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_17_iss_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_17_iss_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_17_iss_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_17_iss_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_17_iss_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_17_iss_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_17_iss_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_17_iss_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_17_iss_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_17_iss_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_17_iss_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_17_iss_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_17_iss_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_17_iss_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_17_iss_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_17_iss_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_17_iss_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_17_iss_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_17_iss_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_17_iss_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_17_iss_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_iss_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_17_iss_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_17_iss_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_17_in_uop_bits_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_17_in_uop_bits_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_17_in_uop_bits_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_17_in_uop_bits_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_17_in_uop_bits_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_17_in_uop_bits_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_17_in_uop_bits_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_17_in_uop_bits_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_17_in_uop_bits_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_17_in_uop_bits_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_17_in_uop_bits_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_17_in_uop_bits_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_17_in_uop_bits_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_17_in_uop_bits_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_17_in_uop_bits_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_17_in_uop_bits_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_17_in_uop_bits_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_17_in_uop_bits_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_17_in_uop_bits_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_17_in_uop_bits_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_17_in_uop_bits_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_17_in_uop_bits_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_17_in_uop_bits_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_17_in_uop_bits_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_17_in_uop_bits_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_17_in_uop_bits_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_17_in_uop_bits_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_17_in_uop_bits_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_17_in_uop_bits_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_17_in_uop_bits_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_17_in_uop_bits_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_17_in_uop_bits_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_17_in_uop_bits_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_17_in_uop_bits_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_17_in_uop_bits_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_17_in_uop_bits_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_17_in_uop_bits_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_17_in_uop_bits_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_17_in_uop_bits_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_17_in_uop_bits_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_17_in_uop_bits_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_17_in_uop_bits_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_bits_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_17_in_uop_bits_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_17_in_uop_bits_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_in_uop_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_17_out_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_17_out_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_17_out_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_17_out_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_17_out_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_17_out_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_17_out_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_17_out_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_17_out_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_17_out_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_17_out_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_17_out_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_17_out_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_17_out_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_17_out_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_17_out_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_17_out_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_17_out_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_17_out_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_17_out_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_17_out_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_17_out_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_17_out_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_17_out_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_17_out_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_17_out_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_17_out_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_17_out_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_17_out_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_17_out_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_17_out_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_17_out_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_17_out_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_17_out_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_17_out_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_17_out_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_17_out_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_17_out_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_17_out_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_17_out_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_17_out_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_17_out_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_out_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_17_out_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_17_out_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_will_be_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_request;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_grant;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_17_clear;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_18_iss_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_18_iss_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_18_iss_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_18_iss_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_18_iss_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_18_iss_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_18_iss_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_18_iss_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_18_iss_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_18_iss_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_18_iss_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_18_iss_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_18_iss_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_18_iss_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_18_iss_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_18_iss_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_18_iss_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_18_iss_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_18_iss_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_18_iss_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_18_iss_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_18_iss_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_18_iss_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_18_iss_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_18_iss_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_18_iss_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_18_iss_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_18_iss_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_18_iss_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_18_iss_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_18_iss_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_18_iss_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_18_iss_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_18_iss_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_18_iss_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_18_iss_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_18_iss_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_18_iss_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_18_iss_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_18_iss_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_18_iss_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_18_iss_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_iss_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_18_iss_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_18_iss_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_18_in_uop_bits_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_18_in_uop_bits_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_18_in_uop_bits_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_18_in_uop_bits_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_18_in_uop_bits_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_18_in_uop_bits_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_18_in_uop_bits_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_18_in_uop_bits_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_18_in_uop_bits_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_18_in_uop_bits_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_18_in_uop_bits_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_18_in_uop_bits_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_18_in_uop_bits_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_18_in_uop_bits_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_18_in_uop_bits_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_18_in_uop_bits_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_18_in_uop_bits_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_18_in_uop_bits_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_18_in_uop_bits_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_18_in_uop_bits_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_18_in_uop_bits_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_18_in_uop_bits_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_18_in_uop_bits_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_18_in_uop_bits_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_18_in_uop_bits_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_18_in_uop_bits_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_18_in_uop_bits_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_18_in_uop_bits_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_18_in_uop_bits_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_18_in_uop_bits_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_18_in_uop_bits_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_18_in_uop_bits_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_18_in_uop_bits_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_18_in_uop_bits_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_18_in_uop_bits_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_18_in_uop_bits_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_18_in_uop_bits_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_18_in_uop_bits_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_18_in_uop_bits_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_18_in_uop_bits_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_18_in_uop_bits_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_18_in_uop_bits_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_bits_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_18_in_uop_bits_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_18_in_uop_bits_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_in_uop_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_18_out_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_18_out_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_18_out_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_18_out_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_18_out_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_18_out_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_18_out_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_18_out_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_18_out_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_18_out_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_18_out_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_18_out_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_18_out_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_18_out_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_18_out_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_18_out_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_18_out_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_18_out_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_18_out_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_18_out_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_18_out_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_18_out_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_18_out_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_18_out_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_18_out_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_18_out_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_18_out_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_18_out_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_18_out_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_18_out_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_18_out_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_18_out_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_18_out_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_18_out_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_18_out_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_18_out_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_18_out_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_18_out_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_18_out_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_18_out_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_18_out_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_18_out_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_out_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_18_out_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_18_out_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_will_be_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_request;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_grant;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_18_clear;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_19_iss_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_19_iss_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_19_iss_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_19_iss_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_19_iss_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_19_iss_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_19_iss_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_19_iss_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_19_iss_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_19_iss_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_19_iss_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_19_iss_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_19_iss_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_19_iss_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_19_iss_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_19_iss_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_19_iss_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_19_iss_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_19_iss_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_19_iss_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_19_iss_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_19_iss_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_19_iss_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_19_iss_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_19_iss_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_19_iss_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_19_iss_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_19_iss_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_19_iss_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_19_iss_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_19_iss_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_19_iss_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_19_iss_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_19_iss_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_19_iss_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_19_iss_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_19_iss_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_19_iss_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_19_iss_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_19_iss_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_19_iss_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_19_iss_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_iss_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_19_iss_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_19_iss_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_19_in_uop_bits_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_19_in_uop_bits_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_19_in_uop_bits_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_19_in_uop_bits_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_19_in_uop_bits_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_19_in_uop_bits_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_19_in_uop_bits_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_19_in_uop_bits_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_19_in_uop_bits_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_19_in_uop_bits_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_19_in_uop_bits_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_19_in_uop_bits_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_19_in_uop_bits_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_19_in_uop_bits_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_19_in_uop_bits_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_19_in_uop_bits_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_19_in_uop_bits_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_19_in_uop_bits_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_19_in_uop_bits_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_19_in_uop_bits_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_19_in_uop_bits_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_19_in_uop_bits_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_19_in_uop_bits_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_19_in_uop_bits_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_19_in_uop_bits_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_19_in_uop_bits_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_19_in_uop_bits_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_19_in_uop_bits_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_19_in_uop_bits_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_19_in_uop_bits_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_19_in_uop_bits_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_19_in_uop_bits_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_19_in_uop_bits_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_19_in_uop_bits_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_19_in_uop_bits_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_19_in_uop_bits_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_19_in_uop_bits_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_19_in_uop_bits_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_19_in_uop_bits_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_19_in_uop_bits_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_19_in_uop_bits_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_19_in_uop_bits_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_bits_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_19_in_uop_bits_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_19_in_uop_bits_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_in_uop_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_19_out_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_19_out_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_19_out_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [31:0] issue_slots_19_out_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [39:0] issue_slots_19_out_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_19_out_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_19_out_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_19_out_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [11:0] issue_slots_19_out_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_19_out_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_19_out_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_19_out_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_19_out_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_19_out_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_19_out_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [19:0] issue_slots_19_out_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_19_out_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_19_out_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_19_out_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_19_out_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [3:0] issue_slots_19_out_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_19_out_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_19_out_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_19_out_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_19_out_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_19_out_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_19_out_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [6:0] issue_slots_19_out_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [63:0] issue_slots_19_out_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_19_out_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_19_out_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_19_out_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_19_out_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_19_out_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_19_out_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [5:0] issue_slots_19_out_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_19_out_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_19_out_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_19_out_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [4:0] issue_slots_19_out_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_19_out_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [1:0] issue_slots_19_out_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_out_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_19_out_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire [2:0] issue_slots_19_out_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_will_be_valid;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_request;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_grant;\t// @[issue-unit-age-ordered.scala:122:28]\n wire issue_slots_19_clear;\t// @[issue-unit-age-ordered.scala:122:28]\n wire vacants_0 = ~issue_slots_0_valid;\t// @[issue-unit-age-ordered.scala:122:28, :157:38]\n wire _shamts_oh_1_T_1 = vacants_0;\t// @[issue-unit-age-ordered.scala:157:38, :163:29]\n wire _shamts_oh_1_T_4 = vacants_0;\t// @[issue-unit-age-ordered.scala:157:38, :165:36]\n wire vacants_1 = ~issue_slots_1_valid;\t// @[issue-unit-age-ordered.scala:122:28, :157:38]\n wire vacants_2 = ~issue_slots_2_valid;\t// @[issue-unit-age-ordered.scala:122:28, :157:38]\n wire vacants_3 = ~issue_slots_3_valid;\t// @[issue-unit-age-ordered.scala:122:28, :157:38]\n wire vacants_4 = ~issue_slots_4_valid;\t// @[issue-unit-age-ordered.scala:122:28, :157:38]\n wire vacants_5 = ~issue_slots_5_valid;\t// @[issue-unit-age-ordered.scala:122:28, :157:38]\n wire vacants_6 = ~issue_slots_6_valid;\t// @[issue-unit-age-ordered.scala:122:28, :157:38]\n wire vacants_7 = ~issue_slots_7_valid;\t// @[issue-unit-age-ordered.scala:122:28, :157:38]\n wire vacants_8 = ~issue_slots_8_valid;\t// @[issue-unit-age-ordered.scala:122:28, :157:38]\n wire vacants_9 = ~issue_slots_9_valid;\t// @[issue-unit-age-ordered.scala:122:28, :157:38]\n wire vacants_10 = ~issue_slots_10_valid;\t// @[issue-unit-age-ordered.scala:122:28, :157:38]\n wire vacants_11 = ~issue_slots_11_valid;\t// @[issue-unit-age-ordered.scala:122:28, :157:38]\n wire vacants_12 = ~issue_slots_12_valid;\t// @[issue-unit-age-ordered.scala:122:28, :157:38]\n wire vacants_13 = ~issue_slots_13_valid;\t// @[issue-unit-age-ordered.scala:122:28, :157:38]\n wire vacants_14 = ~issue_slots_14_valid;\t// @[issue-unit-age-ordered.scala:122:28, :157:38]\n wire vacants_15 = ~issue_slots_15_valid;\t// @[issue-unit-age-ordered.scala:122:28, :157:38]\n wire vacants_16 = ~issue_slots_16_valid;\t// @[issue-unit-age-ordered.scala:122:28, :157:38]\n wire vacants_17 = ~issue_slots_17_valid;\t// @[issue-unit-age-ordered.scala:122:28, :157:38]\n wire vacants_18 = ~issue_slots_18_valid;\t// @[issue-unit-age-ordered.scala:122:28, :157:38]\n wire vacants_19 = ~issue_slots_19_valid;\t// @[issue-unit-age-ordered.scala:122:28, :157:38]\n wire vacants_20 = ~io_dis_uops_0_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :157:82]\n wire vacants_21 = ~io_dis_uops_1_valid_0;\t// @[issue-unit-age-ordered.scala:22:7, :157:82]\n wire [1:0] shamts_oh_1_next;\t// @[issue-unit-age-ordered.scala:161:21]\n wire [1:0] shamts_oh_2_next;\t// @[issue-unit-age-ordered.scala:161:21]\n wire [1:0] shamts_oh_3_next;\t// @[issue-unit-age-ordered.scala:161:21]\n wire [1:0] shamts_oh_4_next;\t// @[issue-unit-age-ordered.scala:161:21]\n wire [1:0] shamts_oh_5_next;\t// @[issue-unit-age-ordered.scala:161:21]\n wire [1:0] shamts_oh_6_next;\t// @[issue-unit-age-ordered.scala:161:21]\n wire [1:0] shamts_oh_7_next;\t// @[issue-unit-age-ordered.scala:161:21]\n wire [1:0] shamts_oh_8_next;\t// @[issue-unit-age-ordered.scala:161:21]\n wire [1:0] shamts_oh_9_next;\t// @[issue-unit-age-ordered.scala:161:21]\n wire [1:0] shamts_oh_10_next;\t// @[issue-unit-age-ordered.scala:161:21]\n wire [1:0] shamts_oh_11_next;\t// @[issue-unit-age-ordered.scala:161:21]\n wire [1:0] shamts_oh_12_next;\t// @[issue-unit-age-ordered.scala:161:21]\n wire [1:0] shamts_oh_13_next;\t// @[issue-unit-age-ordered.scala:161:21]\n wire [1:0] shamts_oh_14_next;\t// @[issue-unit-age-ordered.scala:161:21]\n wire [1:0] shamts_oh_15_next;\t// @[issue-unit-age-ordered.scala:161:21]\n wire [1:0] shamts_oh_16_next;\t// @[issue-unit-age-ordered.scala:161:21]\n wire [1:0] shamts_oh_17_next;\t// @[issue-unit-age-ordered.scala:161:21]\n wire [1:0] shamts_oh_18_next;\t// @[issue-unit-age-ordered.scala:161:21]\n wire [1:0] shamts_oh_19_next;\t// @[issue-unit-age-ordered.scala:161:21]\n wire [1:0] shamts_oh_20_next;\t// @[issue-unit-age-ordered.scala:161:21]\n wire [1:0] shamts_oh_21_next;\t// @[issue-unit-age-ordered.scala:161:21]\n wire [1:0] shamts_oh_1;\t// @[issue-unit-age-ordered.scala:158:23]\n wire [1:0] shamts_oh_2;\t// @[issue-unit-age-ordered.scala:158:23]\n wire [1:0] shamts_oh_3;\t// @[issue-unit-age-ordered.scala:158:23]\n wire [1:0] shamts_oh_4;\t// @[issue-unit-age-ordered.scala:158:23]\n wire [1:0] shamts_oh_5;\t// @[issue-unit-age-ordered.scala:158:23]\n wire [1:0] shamts_oh_6;\t// @[issue-unit-age-ordered.scala:158:23]\n wire [1:0] shamts_oh_7;\t// @[issue-unit-age-ordered.scala:158:23]\n wire [1:0] shamts_oh_8;\t// @[issue-unit-age-ordered.scala:158:23]\n wire [1:0] shamts_oh_9;\t// @[issue-unit-age-ordered.scala:158:23]\n wire [1:0] shamts_oh_10;\t// @[issue-unit-age-ordered.scala:158:23]\n wire [1:0] shamts_oh_11;\t// @[issue-unit-age-ordered.scala:158:23]\n wire [1:0] shamts_oh_12;\t// @[issue-unit-age-ordered.scala:158:23]\n wire [1:0] shamts_oh_13;\t// @[issue-unit-age-ordered.scala:158:23]\n wire [1:0] shamts_oh_14;\t// @[issue-unit-age-ordered.scala:158:23]\n wire [1:0] shamts_oh_15;\t// @[issue-unit-age-ordered.scala:158:23]\n wire [1:0] shamts_oh_16;\t// @[issue-unit-age-ordered.scala:158:23]\n wire [1:0] shamts_oh_17;\t// @[issue-unit-age-ordered.scala:158:23]\n wire [1:0] shamts_oh_18;\t// @[issue-unit-age-ordered.scala:158:23]\n wire [1:0] shamts_oh_19;\t// @[issue-unit-age-ordered.scala:158:23]\n wire [1:0] shamts_oh_20;\t// @[issue-unit-age-ordered.scala:158:23]\n wire [1:0] shamts_oh_21;\t// @[issue-unit-age-ordered.scala:158:23]\n assign shamts_oh_1 = shamts_oh_1_next;\t// @[issue-unit-age-ordered.scala:158:23, :161:21]\n assign shamts_oh_1_next = {1'h0, _shamts_oh_1_T_1};\t// @[issue-unit-age-ordered.scala:161:21, :163:{29,37}, :164:13, :165:44]\n assign shamts_oh_2 = shamts_oh_2_next;\t// @[issue-unit-age-ordered.scala:158:23, :161:21]\n wire _shamts_oh_2_T = ~(|shamts_oh_1);\t// @[issue-unit-age-ordered.scala:158:23, :163:21]\n wire _shamts_oh_2_T_1 = _shamts_oh_2_T & vacants_1;\t// @[issue-unit-age-ordered.scala:157:38, :163:{21,29}]\n wire _shamts_oh_2_T_2 = shamts_oh_1[1];\t// @[issue-unit-age-ordered.scala:158:23, :165:28]\n wire _shamts_oh_2_T_3 = ~_shamts_oh_2_T_2;\t// @[issue-unit-age-ordered.scala:165:{19,28}]\n wire _shamts_oh_2_T_4 = _shamts_oh_2_T_3 & vacants_1;\t// @[issue-unit-age-ordered.scala:157:38, :165:{19,36}]\n wire [2:0] _shamts_oh_2_next_T = {shamts_oh_1, 1'h0};\t// @[issue-unit-age-ordered.scala:158:23, :166:26]\n assign shamts_oh_2_next = _shamts_oh_2_T_1 ? 2'h1 : _shamts_oh_2_T_4 ? _shamts_oh_2_next_T[1:0] : shamts_oh_1;\t// @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}]\n assign shamts_oh_3 = shamts_oh_3_next;\t// @[issue-unit-age-ordered.scala:158:23, :161:21]\n wire _shamts_oh_3_T = ~(|shamts_oh_2);\t// @[issue-unit-age-ordered.scala:158:23, :163:21]\n wire _shamts_oh_3_T_1 = _shamts_oh_3_T & vacants_2;\t// @[issue-unit-age-ordered.scala:157:38, :163:{21,29}]\n wire _shamts_oh_3_T_2 = shamts_oh_2[1];\t// @[issue-unit-age-ordered.scala:158:23, :165:28]\n wire _shamts_oh_3_T_3 = ~_shamts_oh_3_T_2;\t// @[issue-unit-age-ordered.scala:165:{19,28}]\n wire _shamts_oh_3_T_4 = _shamts_oh_3_T_3 & vacants_2;\t// @[issue-unit-age-ordered.scala:157:38, :165:{19,36}]\n wire [2:0] _shamts_oh_3_next_T = {shamts_oh_2, 1'h0};\t// @[issue-unit-age-ordered.scala:158:23, :166:26]\n assign shamts_oh_3_next = _shamts_oh_3_T_1 ? 2'h1 : _shamts_oh_3_T_4 ? _shamts_oh_3_next_T[1:0] : shamts_oh_2;\t// @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}]\n assign shamts_oh_4 = shamts_oh_4_next;\t// @[issue-unit-age-ordered.scala:158:23, :161:21]\n wire _shamts_oh_4_T = ~(|shamts_oh_3);\t// @[issue-unit-age-ordered.scala:158:23, :163:21]\n wire _shamts_oh_4_T_1 = _shamts_oh_4_T & vacants_3;\t// @[issue-unit-age-ordered.scala:157:38, :163:{21,29}]\n wire _shamts_oh_4_T_2 = shamts_oh_3[1];\t// @[issue-unit-age-ordered.scala:158:23, :165:28]\n wire _shamts_oh_4_T_3 = ~_shamts_oh_4_T_2;\t// @[issue-unit-age-ordered.scala:165:{19,28}]\n wire _shamts_oh_4_T_4 = _shamts_oh_4_T_3 & vacants_3;\t// @[issue-unit-age-ordered.scala:157:38, :165:{19,36}]\n wire [2:0] _shamts_oh_4_next_T = {shamts_oh_3, 1'h0};\t// @[issue-unit-age-ordered.scala:158:23, :166:26]\n assign shamts_oh_4_next = _shamts_oh_4_T_1 ? 2'h1 : _shamts_oh_4_T_4 ? _shamts_oh_4_next_T[1:0] : shamts_oh_3;\t// @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}]\n assign shamts_oh_5 = shamts_oh_5_next;\t// @[issue-unit-age-ordered.scala:158:23, :161:21]\n wire _shamts_oh_5_T = ~(|shamts_oh_4);\t// @[issue-unit-age-ordered.scala:158:23, :163:21]\n wire _shamts_oh_5_T_1 = _shamts_oh_5_T & vacants_4;\t// @[issue-unit-age-ordered.scala:157:38, :163:{21,29}]\n wire _shamts_oh_5_T_2 = shamts_oh_4[1];\t// @[issue-unit-age-ordered.scala:158:23, :165:28]\n wire _shamts_oh_5_T_3 = ~_shamts_oh_5_T_2;\t// @[issue-unit-age-ordered.scala:165:{19,28}]\n wire _shamts_oh_5_T_4 = _shamts_oh_5_T_3 & vacants_4;\t// @[issue-unit-age-ordered.scala:157:38, :165:{19,36}]\n wire [2:0] _shamts_oh_5_next_T = {shamts_oh_4, 1'h0};\t// @[issue-unit-age-ordered.scala:158:23, :166:26]\n assign shamts_oh_5_next = _shamts_oh_5_T_1 ? 2'h1 : _shamts_oh_5_T_4 ? _shamts_oh_5_next_T[1:0] : shamts_oh_4;\t// @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}]\n assign shamts_oh_6 = shamts_oh_6_next;\t// @[issue-unit-age-ordered.scala:158:23, :161:21]\n wire _shamts_oh_6_T = ~(|shamts_oh_5);\t// @[issue-unit-age-ordered.scala:158:23, :163:21]\n wire _shamts_oh_6_T_1 = _shamts_oh_6_T & vacants_5;\t// @[issue-unit-age-ordered.scala:157:38, :163:{21,29}]\n wire _shamts_oh_6_T_2 = shamts_oh_5[1];\t// @[issue-unit-age-ordered.scala:158:23, :165:28]\n wire _shamts_oh_6_T_3 = ~_shamts_oh_6_T_2;\t// @[issue-unit-age-ordered.scala:165:{19,28}]\n wire _shamts_oh_6_T_4 = _shamts_oh_6_T_3 & vacants_5;\t// @[issue-unit-age-ordered.scala:157:38, :165:{19,36}]\n wire [2:0] _shamts_oh_6_next_T = {shamts_oh_5, 1'h0};\t// @[issue-unit-age-ordered.scala:158:23, :166:26]\n assign shamts_oh_6_next = _shamts_oh_6_T_1 ? 2'h1 : _shamts_oh_6_T_4 ? _shamts_oh_6_next_T[1:0] : shamts_oh_5;\t// @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}]\n assign shamts_oh_7 = shamts_oh_7_next;\t// @[issue-unit-age-ordered.scala:158:23, :161:21]\n wire _shamts_oh_7_T = ~(|shamts_oh_6);\t// @[issue-unit-age-ordered.scala:158:23, :163:21]\n wire _shamts_oh_7_T_1 = _shamts_oh_7_T & vacants_6;\t// @[issue-unit-age-ordered.scala:157:38, :163:{21,29}]\n wire _shamts_oh_7_T_2 = shamts_oh_6[1];\t// @[issue-unit-age-ordered.scala:158:23, :165:28]\n wire _shamts_oh_7_T_3 = ~_shamts_oh_7_T_2;\t// @[issue-unit-age-ordered.scala:165:{19,28}]\n wire _shamts_oh_7_T_4 = _shamts_oh_7_T_3 & vacants_6;\t// @[issue-unit-age-ordered.scala:157:38, :165:{19,36}]\n wire [2:0] _shamts_oh_7_next_T = {shamts_oh_6, 1'h0};\t// @[issue-unit-age-ordered.scala:158:23, :166:26]\n assign shamts_oh_7_next = _shamts_oh_7_T_1 ? 2'h1 : _shamts_oh_7_T_4 ? _shamts_oh_7_next_T[1:0] : shamts_oh_6;\t// @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}]\n assign shamts_oh_8 = shamts_oh_8_next;\t// @[issue-unit-age-ordered.scala:158:23, :161:21]\n wire _shamts_oh_8_T = ~(|shamts_oh_7);\t// @[issue-unit-age-ordered.scala:158:23, :163:21]\n wire _shamts_oh_8_T_1 = _shamts_oh_8_T & vacants_7;\t// @[issue-unit-age-ordered.scala:157:38, :163:{21,29}]\n wire _shamts_oh_8_T_2 = shamts_oh_7[1];\t// @[issue-unit-age-ordered.scala:158:23, :165:28]\n wire _shamts_oh_8_T_3 = ~_shamts_oh_8_T_2;\t// @[issue-unit-age-ordered.scala:165:{19,28}]\n wire _shamts_oh_8_T_4 = _shamts_oh_8_T_3 & vacants_7;\t// @[issue-unit-age-ordered.scala:157:38, :165:{19,36}]\n wire [2:0] _shamts_oh_8_next_T = {shamts_oh_7, 1'h0};\t// @[issue-unit-age-ordered.scala:158:23, :166:26]\n assign shamts_oh_8_next = _shamts_oh_8_T_1 ? 2'h1 : _shamts_oh_8_T_4 ? _shamts_oh_8_next_T[1:0] : shamts_oh_7;\t// @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}]\n assign shamts_oh_9 = shamts_oh_9_next;\t// @[issue-unit-age-ordered.scala:158:23, :161:21]\n wire _shamts_oh_9_T = ~(|shamts_oh_8);\t// @[issue-unit-age-ordered.scala:158:23, :163:21]\n wire _shamts_oh_9_T_1 = _shamts_oh_9_T & vacants_8;\t// @[issue-unit-age-ordered.scala:157:38, :163:{21,29}]\n wire _shamts_oh_9_T_2 = shamts_oh_8[1];\t// @[issue-unit-age-ordered.scala:158:23, :165:28]\n wire _shamts_oh_9_T_3 = ~_shamts_oh_9_T_2;\t// @[issue-unit-age-ordered.scala:165:{19,28}]\n wire _shamts_oh_9_T_4 = _shamts_oh_9_T_3 & vacants_8;\t// @[issue-unit-age-ordered.scala:157:38, :165:{19,36}]\n wire [2:0] _shamts_oh_9_next_T = {shamts_oh_8, 1'h0};\t// @[issue-unit-age-ordered.scala:158:23, :166:26]\n assign shamts_oh_9_next = _shamts_oh_9_T_1 ? 2'h1 : _shamts_oh_9_T_4 ? _shamts_oh_9_next_T[1:0] : shamts_oh_8;\t// @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}]\n assign shamts_oh_10 = shamts_oh_10_next;\t// @[issue-unit-age-ordered.scala:158:23, :161:21]\n wire _shamts_oh_10_T = ~(|shamts_oh_9);\t// @[issue-unit-age-ordered.scala:158:23, :163:21]\n wire _shamts_oh_10_T_1 = _shamts_oh_10_T & vacants_9;\t// @[issue-unit-age-ordered.scala:157:38, :163:{21,29}]\n wire _shamts_oh_10_T_2 = shamts_oh_9[1];\t// @[issue-unit-age-ordered.scala:158:23, :165:28]\n wire _shamts_oh_10_T_3 = ~_shamts_oh_10_T_2;\t// @[issue-unit-age-ordered.scala:165:{19,28}]\n wire _shamts_oh_10_T_4 = _shamts_oh_10_T_3 & vacants_9;\t// @[issue-unit-age-ordered.scala:157:38, :165:{19,36}]\n wire [2:0] _shamts_oh_10_next_T = {shamts_oh_9, 1'h0};\t// @[issue-unit-age-ordered.scala:158:23, :166:26]\n assign shamts_oh_10_next = _shamts_oh_10_T_1 ? 2'h1 : _shamts_oh_10_T_4 ? _shamts_oh_10_next_T[1:0] : shamts_oh_9;\t// @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}]\n assign shamts_oh_11 = shamts_oh_11_next;\t// @[issue-unit-age-ordered.scala:158:23, :161:21]\n wire _shamts_oh_11_T = ~(|shamts_oh_10);\t// @[issue-unit-age-ordered.scala:158:23, :163:21]\n wire _shamts_oh_11_T_1 = _shamts_oh_11_T & vacants_10;\t// @[issue-unit-age-ordered.scala:157:38, :163:{21,29}]\n wire _shamts_oh_11_T_2 = shamts_oh_10[1];\t// @[issue-unit-age-ordered.scala:158:23, :165:28]\n wire _shamts_oh_11_T_3 = ~_shamts_oh_11_T_2;\t// @[issue-unit-age-ordered.scala:165:{19,28}]\n wire _shamts_oh_11_T_4 = _shamts_oh_11_T_3 & vacants_10;\t// @[issue-unit-age-ordered.scala:157:38, :165:{19,36}]\n wire [2:0] _shamts_oh_11_next_T = {shamts_oh_10, 1'h0};\t// @[issue-unit-age-ordered.scala:158:23, :166:26]\n assign shamts_oh_11_next = _shamts_oh_11_T_1 ? 2'h1 : _shamts_oh_11_T_4 ? _shamts_oh_11_next_T[1:0] : shamts_oh_10;\t// @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}]\n assign shamts_oh_12 = shamts_oh_12_next;\t// @[issue-unit-age-ordered.scala:158:23, :161:21]\n wire _shamts_oh_12_T = ~(|shamts_oh_11);\t// @[issue-unit-age-ordered.scala:158:23, :163:21]\n wire _shamts_oh_12_T_1 = _shamts_oh_12_T & vacants_11;\t// @[issue-unit-age-ordered.scala:157:38, :163:{21,29}]\n wire _shamts_oh_12_T_2 = shamts_oh_11[1];\t// @[issue-unit-age-ordered.scala:158:23, :165:28]\n wire _shamts_oh_12_T_3 = ~_shamts_oh_12_T_2;\t// @[issue-unit-age-ordered.scala:165:{19,28}]\n wire _shamts_oh_12_T_4 = _shamts_oh_12_T_3 & vacants_11;\t// @[issue-unit-age-ordered.scala:157:38, :165:{19,36}]\n wire [2:0] _shamts_oh_12_next_T = {shamts_oh_11, 1'h0};\t// @[issue-unit-age-ordered.scala:158:23, :166:26]\n assign shamts_oh_12_next = _shamts_oh_12_T_1 ? 2'h1 : _shamts_oh_12_T_4 ? _shamts_oh_12_next_T[1:0] : shamts_oh_11;\t// @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}]\n assign shamts_oh_13 = shamts_oh_13_next;\t// @[issue-unit-age-ordered.scala:158:23, :161:21]\n wire _shamts_oh_13_T = ~(|shamts_oh_12);\t// @[issue-unit-age-ordered.scala:158:23, :163:21]\n wire _shamts_oh_13_T_1 = _shamts_oh_13_T & vacants_12;\t// @[issue-unit-age-ordered.scala:157:38, :163:{21,29}]\n wire _shamts_oh_13_T_2 = shamts_oh_12[1];\t// @[issue-unit-age-ordered.scala:158:23, :165:28]\n wire _shamts_oh_13_T_3 = ~_shamts_oh_13_T_2;\t// @[issue-unit-age-ordered.scala:165:{19,28}]\n wire _shamts_oh_13_T_4 = _shamts_oh_13_T_3 & vacants_12;\t// @[issue-unit-age-ordered.scala:157:38, :165:{19,36}]\n wire [2:0] _shamts_oh_13_next_T = {shamts_oh_12, 1'h0};\t// @[issue-unit-age-ordered.scala:158:23, :166:26]\n assign shamts_oh_13_next = _shamts_oh_13_T_1 ? 2'h1 : _shamts_oh_13_T_4 ? _shamts_oh_13_next_T[1:0] : shamts_oh_12;\t// @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}]\n assign shamts_oh_14 = shamts_oh_14_next;\t// @[issue-unit-age-ordered.scala:158:23, :161:21]\n wire _shamts_oh_14_T = ~(|shamts_oh_13);\t// @[issue-unit-age-ordered.scala:158:23, :163:21]\n wire _shamts_oh_14_T_1 = _shamts_oh_14_T & vacants_13;\t// @[issue-unit-age-ordered.scala:157:38, :163:{21,29}]\n wire _shamts_oh_14_T_2 = shamts_oh_13[1];\t// @[issue-unit-age-ordered.scala:158:23, :165:28]\n wire _shamts_oh_14_T_3 = ~_shamts_oh_14_T_2;\t// @[issue-unit-age-ordered.scala:165:{19,28}]\n wire _shamts_oh_14_T_4 = _shamts_oh_14_T_3 & vacants_13;\t// @[issue-unit-age-ordered.scala:157:38, :165:{19,36}]\n wire [2:0] _shamts_oh_14_next_T = {shamts_oh_13, 1'h0};\t// @[issue-unit-age-ordered.scala:158:23, :166:26]\n assign shamts_oh_14_next = _shamts_oh_14_T_1 ? 2'h1 : _shamts_oh_14_T_4 ? _shamts_oh_14_next_T[1:0] : shamts_oh_13;\t// @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}]\n assign shamts_oh_15 = shamts_oh_15_next;\t// @[issue-unit-age-ordered.scala:158:23, :161:21]\n wire _shamts_oh_15_T = ~(|shamts_oh_14);\t// @[issue-unit-age-ordered.scala:158:23, :163:21]\n wire _shamts_oh_15_T_1 = _shamts_oh_15_T & vacants_14;\t// @[issue-unit-age-ordered.scala:157:38, :163:{21,29}]\n wire _shamts_oh_15_T_2 = shamts_oh_14[1];\t// @[issue-unit-age-ordered.scala:158:23, :165:28]\n wire _shamts_oh_15_T_3 = ~_shamts_oh_15_T_2;\t// @[issue-unit-age-ordered.scala:165:{19,28}]\n wire _shamts_oh_15_T_4 = _shamts_oh_15_T_3 & vacants_14;\t// @[issue-unit-age-ordered.scala:157:38, :165:{19,36}]\n wire [2:0] _shamts_oh_15_next_T = {shamts_oh_14, 1'h0};\t// @[issue-unit-age-ordered.scala:158:23, :166:26]\n assign shamts_oh_15_next = _shamts_oh_15_T_1 ? 2'h1 : _shamts_oh_15_T_4 ? _shamts_oh_15_next_T[1:0] : shamts_oh_14;\t// @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}]\n assign shamts_oh_16 = shamts_oh_16_next;\t// @[issue-unit-age-ordered.scala:158:23, :161:21]\n wire _shamts_oh_16_T = ~(|shamts_oh_15);\t// @[issue-unit-age-ordered.scala:158:23, :163:21]\n wire _shamts_oh_16_T_1 = _shamts_oh_16_T & vacants_15;\t// @[issue-unit-age-ordered.scala:157:38, :163:{21,29}]\n wire _shamts_oh_16_T_2 = shamts_oh_15[1];\t// @[issue-unit-age-ordered.scala:158:23, :165:28]\n wire _shamts_oh_16_T_3 = ~_shamts_oh_16_T_2;\t// @[issue-unit-age-ordered.scala:165:{19,28}]\n wire _shamts_oh_16_T_4 = _shamts_oh_16_T_3 & vacants_15;\t// @[issue-unit-age-ordered.scala:157:38, :165:{19,36}]\n wire [2:0] _shamts_oh_16_next_T = {shamts_oh_15, 1'h0};\t// @[issue-unit-age-ordered.scala:158:23, :166:26]\n assign shamts_oh_16_next = _shamts_oh_16_T_1 ? 2'h1 : _shamts_oh_16_T_4 ? _shamts_oh_16_next_T[1:0] : shamts_oh_15;\t// @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}]\n assign shamts_oh_17 = shamts_oh_17_next;\t// @[issue-unit-age-ordered.scala:158:23, :161:21]\n wire _shamts_oh_17_T = ~(|shamts_oh_16);\t// @[issue-unit-age-ordered.scala:158:23, :163:21]\n wire _shamts_oh_17_T_1 = _shamts_oh_17_T & vacants_16;\t// @[issue-unit-age-ordered.scala:157:38, :163:{21,29}]\n wire _shamts_oh_17_T_2 = shamts_oh_16[1];\t// @[issue-unit-age-ordered.scala:158:23, :165:28]\n wire _shamts_oh_17_T_3 = ~_shamts_oh_17_T_2;\t// @[issue-unit-age-ordered.scala:165:{19,28}]\n wire _shamts_oh_17_T_4 = _shamts_oh_17_T_3 & vacants_16;\t// @[issue-unit-age-ordered.scala:157:38, :165:{19,36}]\n wire [2:0] _shamts_oh_17_next_T = {shamts_oh_16, 1'h0};\t// @[issue-unit-age-ordered.scala:158:23, :166:26]\n assign shamts_oh_17_next = _shamts_oh_17_T_1 ? 2'h1 : _shamts_oh_17_T_4 ? _shamts_oh_17_next_T[1:0] : shamts_oh_16;\t// @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}]\n assign shamts_oh_18 = shamts_oh_18_next;\t// @[issue-unit-age-ordered.scala:158:23, :161:21]\n wire _shamts_oh_18_T = ~(|shamts_oh_17);\t// @[issue-unit-age-ordered.scala:158:23, :163:21]\n wire _shamts_oh_18_T_1 = _shamts_oh_18_T & vacants_17;\t// @[issue-unit-age-ordered.scala:157:38, :163:{21,29}]\n wire _shamts_oh_18_T_2 = shamts_oh_17[1];\t// @[issue-unit-age-ordered.scala:158:23, :165:28]\n wire _shamts_oh_18_T_3 = ~_shamts_oh_18_T_2;\t// @[issue-unit-age-ordered.scala:165:{19,28}]\n wire _shamts_oh_18_T_4 = _shamts_oh_18_T_3 & vacants_17;\t// @[issue-unit-age-ordered.scala:157:38, :165:{19,36}]\n wire [2:0] _shamts_oh_18_next_T = {shamts_oh_17, 1'h0};\t// @[issue-unit-age-ordered.scala:158:23, :166:26]\n assign shamts_oh_18_next = _shamts_oh_18_T_1 ? 2'h1 : _shamts_oh_18_T_4 ? _shamts_oh_18_next_T[1:0] : shamts_oh_17;\t// @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}]\n assign shamts_oh_19 = shamts_oh_19_next;\t// @[issue-unit-age-ordered.scala:158:23, :161:21]\n wire _shamts_oh_19_T = ~(|shamts_oh_18);\t// @[issue-unit-age-ordered.scala:158:23, :163:21]\n wire _shamts_oh_19_T_1 = _shamts_oh_19_T & vacants_18;\t// @[issue-unit-age-ordered.scala:157:38, :163:{21,29}]\n wire _shamts_oh_19_T_2 = shamts_oh_18[1];\t// @[issue-unit-age-ordered.scala:158:23, :165:28]\n wire _shamts_oh_19_T_3 = ~_shamts_oh_19_T_2;\t// @[issue-unit-age-ordered.scala:165:{19,28}]\n wire _shamts_oh_19_T_4 = _shamts_oh_19_T_3 & vacants_18;\t// @[issue-unit-age-ordered.scala:157:38, :165:{19,36}]\n wire [2:0] _shamts_oh_19_next_T = {shamts_oh_18, 1'h0};\t// @[issue-unit-age-ordered.scala:158:23, :166:26]\n assign shamts_oh_19_next = _shamts_oh_19_T_1 ? 2'h1 : _shamts_oh_19_T_4 ? _shamts_oh_19_next_T[1:0] : shamts_oh_18;\t// @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}]\n assign shamts_oh_20 = shamts_oh_20_next;\t// @[issue-unit-age-ordered.scala:158:23, :161:21]\n wire _shamts_oh_20_T = ~(|shamts_oh_19);\t// @[issue-unit-age-ordered.scala:158:23, :163:21]\n wire _shamts_oh_20_T_1 = _shamts_oh_20_T & vacants_19;\t// @[issue-unit-age-ordered.scala:157:38, :163:{21,29}]\n wire _shamts_oh_20_T_2 = shamts_oh_19[1];\t// @[issue-unit-age-ordered.scala:158:23, :165:28]\n wire _shamts_oh_20_T_3 = ~_shamts_oh_20_T_2;\t// @[issue-unit-age-ordered.scala:165:{19,28}]\n wire _shamts_oh_20_T_4 = _shamts_oh_20_T_3 & vacants_19;\t// @[issue-unit-age-ordered.scala:157:38, :165:{19,36}]\n wire [2:0] _shamts_oh_20_next_T = {shamts_oh_19, 1'h0};\t// @[issue-unit-age-ordered.scala:158:23, :166:26]\n assign shamts_oh_20_next = _shamts_oh_20_T_1 ? 2'h1 : _shamts_oh_20_T_4 ? _shamts_oh_20_next_T[1:0] : shamts_oh_19;\t// @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}]\n assign shamts_oh_21 = shamts_oh_21_next;\t// @[issue-unit-age-ordered.scala:158:23, :161:21]\n wire _shamts_oh_21_T = shamts_oh_20 == 2'h0;\t// @[issue-unit-age-ordered.scala:158:23, :163:21]\n wire _shamts_oh_21_T_1 = _shamts_oh_21_T & vacants_20;\t// @[issue-unit-age-ordered.scala:157:82, :163:{21,29}]\n wire _shamts_oh_21_T_2 = shamts_oh_20[1];\t// @[issue-unit-age-ordered.scala:158:23, :165:28]\n wire _shamts_oh_21_T_3 = ~_shamts_oh_21_T_2;\t// @[issue-unit-age-ordered.scala:165:{19,28}]\n wire _shamts_oh_21_T_4 = _shamts_oh_21_T_3 & vacants_20;\t// @[issue-unit-age-ordered.scala:157:82, :165:{19,36}]\n wire [2:0] _shamts_oh_21_next_T = {shamts_oh_20, 1'h0};\t// @[issue-unit-age-ordered.scala:158:23, :166:26]\n assign shamts_oh_21_next = _shamts_oh_21_T_1 ? 2'h1 : _shamts_oh_21_T_4 ? _shamts_oh_21_next_T[1:0] : shamts_oh_20;\t// @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}]\n wire _will_be_valid_T = ~io_dis_uops_0_bits_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :185:57]\n wire _will_be_valid_T_1 = io_dis_uops_0_valid_0 & _will_be_valid_T;\t// @[issue-unit-age-ordered.scala:22:7, :184:77, :185:57]\n wire _will_be_valid_T_2 = ~io_dis_uops_0_bits_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :186:57]\n wire _will_be_valid_T_3 = _will_be_valid_T_1 & _will_be_valid_T_2;\t// @[issue-unit-age-ordered.scala:184:77, :185:80, :186:57]\n wire _will_be_valid_T_4 = ~io_dis_uops_0_bits_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :187:57]\n wire will_be_valid_20 = _will_be_valid_T_3 & _will_be_valid_T_4;\t// @[issue-unit-age-ordered.scala:185:80, :186:79, :187:57]\n wire _will_be_valid_T_5 = ~io_dis_uops_1_bits_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :185:57]\n wire _will_be_valid_T_6 = io_dis_uops_1_valid_0 & _will_be_valid_T_5;\t// @[issue-unit-age-ordered.scala:22:7, :184:77, :185:57]\n wire _will_be_valid_T_7 = ~io_dis_uops_1_bits_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :186:57]\n wire _will_be_valid_T_8 = _will_be_valid_T_6 & _will_be_valid_T_7;\t// @[issue-unit-age-ordered.scala:184:77, :185:80, :186:57]\n wire _will_be_valid_T_9 = ~io_dis_uops_1_bits_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :187:57]\n wire will_be_valid_21 = _will_be_valid_T_8 & _will_be_valid_T_9;\t// @[issue-unit-age-ordered.scala:185:80, :186:79, :187:57]\n wire _T_163 = shamts_oh_2 == 2'h2;\t// @[issue-unit-age-ordered.scala:158:23, :194:28]\n assign issue_slots_0_in_uop_valid = _T_163 ? issue_slots_2_will_be_valid : shamts_oh_1 == 2'h1 & issue_slots_1_will_be_valid;\t// @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37]\n assign issue_slots_0_in_uop_bits_debug_tsrc = _T_163 ? issue_slots_2_out_uop_debug_tsrc : issue_slots_1_out_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_debug_fsrc = _T_163 ? issue_slots_2_out_uop_debug_fsrc : issue_slots_1_out_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_bp_xcpt_if = _T_163 ? issue_slots_2_out_uop_bp_xcpt_if : issue_slots_1_out_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_bp_debug_if = _T_163 ? issue_slots_2_out_uop_bp_debug_if : issue_slots_1_out_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_xcpt_ma_if = _T_163 ? issue_slots_2_out_uop_xcpt_ma_if : issue_slots_1_out_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_xcpt_ae_if = _T_163 ? issue_slots_2_out_uop_xcpt_ae_if : issue_slots_1_out_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_xcpt_pf_if = _T_163 ? issue_slots_2_out_uop_xcpt_pf_if : issue_slots_1_out_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_fp_typ = _T_163 ? issue_slots_2_out_uop_fp_typ : issue_slots_1_out_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_fp_rm = _T_163 ? issue_slots_2_out_uop_fp_rm : issue_slots_1_out_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_fp_val = _T_163 ? issue_slots_2_out_uop_fp_val : issue_slots_1_out_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_fcn_op = _T_163 ? issue_slots_2_out_uop_fcn_op : issue_slots_1_out_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_fcn_dw = _T_163 ? issue_slots_2_out_uop_fcn_dw : issue_slots_1_out_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_frs3_en = _T_163 ? issue_slots_2_out_uop_frs3_en : issue_slots_1_out_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_lrs2_rtype = _T_163 ? issue_slots_2_out_uop_lrs2_rtype : issue_slots_1_out_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_lrs1_rtype = _T_163 ? issue_slots_2_out_uop_lrs1_rtype : issue_slots_1_out_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_dst_rtype = _T_163 ? issue_slots_2_out_uop_dst_rtype : issue_slots_1_out_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_lrs3 = _T_163 ? issue_slots_2_out_uop_lrs3 : issue_slots_1_out_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_lrs2 = _T_163 ? issue_slots_2_out_uop_lrs2 : issue_slots_1_out_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_lrs1 = _T_163 ? issue_slots_2_out_uop_lrs1 : issue_slots_1_out_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_ldst = _T_163 ? issue_slots_2_out_uop_ldst : issue_slots_1_out_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_ldst_is_rs1 = _T_163 ? issue_slots_2_out_uop_ldst_is_rs1 : issue_slots_1_out_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_csr_cmd = _T_163 ? issue_slots_2_out_uop_csr_cmd : issue_slots_1_out_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_flush_on_commit = _T_163 ? issue_slots_2_out_uop_flush_on_commit : issue_slots_1_out_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_is_unique = _T_163 ? issue_slots_2_out_uop_is_unique : issue_slots_1_out_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_uses_stq = _T_163 ? issue_slots_2_out_uop_uses_stq : issue_slots_1_out_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_uses_ldq = _T_163 ? issue_slots_2_out_uop_uses_ldq : issue_slots_1_out_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_mem_signed = _T_163 ? issue_slots_2_out_uop_mem_signed : issue_slots_1_out_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_mem_size = _T_163 ? issue_slots_2_out_uop_mem_size : issue_slots_1_out_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_mem_cmd = _T_163 ? issue_slots_2_out_uop_mem_cmd : issue_slots_1_out_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_exc_cause = _T_163 ? issue_slots_2_out_uop_exc_cause : issue_slots_1_out_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_exception = _T_163 ? issue_slots_2_out_uop_exception : issue_slots_1_out_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_stale_pdst = _T_163 ? issue_slots_2_out_uop_stale_pdst : issue_slots_1_out_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_ppred_busy = _T_163 ? issue_slots_2_out_uop_ppred_busy : issue_slots_1_out_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_prs3_busy = _T_163 ? issue_slots_2_out_uop_prs3_busy : issue_slots_1_out_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_prs2_busy = _T_163 ? issue_slots_2_out_uop_prs2_busy : issue_slots_1_out_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_prs1_busy = _T_163 ? issue_slots_2_out_uop_prs1_busy : issue_slots_1_out_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_ppred = _T_163 ? issue_slots_2_out_uop_ppred : issue_slots_1_out_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_prs3 = _T_163 ? issue_slots_2_out_uop_prs3 : issue_slots_1_out_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_prs2 = _T_163 ? issue_slots_2_out_uop_prs2 : issue_slots_1_out_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_prs1 = _T_163 ? issue_slots_2_out_uop_prs1 : issue_slots_1_out_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_pdst = _T_163 ? issue_slots_2_out_uop_pdst : issue_slots_1_out_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_rxq_idx = _T_163 ? issue_slots_2_out_uop_rxq_idx : issue_slots_1_out_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_stq_idx = _T_163 ? issue_slots_2_out_uop_stq_idx : issue_slots_1_out_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_ldq_idx = _T_163 ? issue_slots_2_out_uop_ldq_idx : issue_slots_1_out_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_rob_idx = _T_163 ? issue_slots_2_out_uop_rob_idx : issue_slots_1_out_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_fp_ctrl_vec = _T_163 ? issue_slots_2_out_uop_fp_ctrl_vec : issue_slots_1_out_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_fp_ctrl_wflags = _T_163 ? issue_slots_2_out_uop_fp_ctrl_wflags : issue_slots_1_out_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_fp_ctrl_sqrt = _T_163 ? issue_slots_2_out_uop_fp_ctrl_sqrt : issue_slots_1_out_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_fp_ctrl_div = _T_163 ? issue_slots_2_out_uop_fp_ctrl_div : issue_slots_1_out_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_fp_ctrl_fma = _T_163 ? issue_slots_2_out_uop_fp_ctrl_fma : issue_slots_1_out_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_fp_ctrl_fastpipe = _T_163 ? issue_slots_2_out_uop_fp_ctrl_fastpipe : issue_slots_1_out_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_fp_ctrl_toint = _T_163 ? issue_slots_2_out_uop_fp_ctrl_toint : issue_slots_1_out_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_fp_ctrl_fromint = _T_163 ? issue_slots_2_out_uop_fp_ctrl_fromint : issue_slots_1_out_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_fp_ctrl_typeTagOut = _T_163 ? issue_slots_2_out_uop_fp_ctrl_typeTagOut : issue_slots_1_out_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_fp_ctrl_typeTagIn = _T_163 ? issue_slots_2_out_uop_fp_ctrl_typeTagIn : issue_slots_1_out_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_fp_ctrl_swap23 = _T_163 ? issue_slots_2_out_uop_fp_ctrl_swap23 : issue_slots_1_out_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_fp_ctrl_swap12 = _T_163 ? issue_slots_2_out_uop_fp_ctrl_swap12 : issue_slots_1_out_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_fp_ctrl_ren3 = _T_163 ? issue_slots_2_out_uop_fp_ctrl_ren3 : issue_slots_1_out_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_fp_ctrl_ren2 = _T_163 ? issue_slots_2_out_uop_fp_ctrl_ren2 : issue_slots_1_out_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_fp_ctrl_ren1 = _T_163 ? issue_slots_2_out_uop_fp_ctrl_ren1 : issue_slots_1_out_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_fp_ctrl_wen = _T_163 ? issue_slots_2_out_uop_fp_ctrl_wen : issue_slots_1_out_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_fp_ctrl_ldst = _T_163 ? issue_slots_2_out_uop_fp_ctrl_ldst : issue_slots_1_out_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_op2_sel = _T_163 ? issue_slots_2_out_uop_op2_sel : issue_slots_1_out_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_op1_sel = _T_163 ? issue_slots_2_out_uop_op1_sel : issue_slots_1_out_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_imm_packed = _T_163 ? issue_slots_2_out_uop_imm_packed : issue_slots_1_out_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_pimm = _T_163 ? issue_slots_2_out_uop_pimm : issue_slots_1_out_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_imm_sel = _T_163 ? issue_slots_2_out_uop_imm_sel : issue_slots_1_out_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_imm_rename = _T_163 ? issue_slots_2_out_uop_imm_rename : issue_slots_1_out_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_taken = _T_163 ? issue_slots_2_out_uop_taken : issue_slots_1_out_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_pc_lob = _T_163 ? issue_slots_2_out_uop_pc_lob : issue_slots_1_out_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_edge_inst = _T_163 ? issue_slots_2_out_uop_edge_inst : issue_slots_1_out_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_ftq_idx = _T_163 ? issue_slots_2_out_uop_ftq_idx : issue_slots_1_out_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_is_mov = _T_163 ? issue_slots_2_out_uop_is_mov : issue_slots_1_out_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_is_rocc = _T_163 ? issue_slots_2_out_uop_is_rocc : issue_slots_1_out_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_is_sys_pc2epc = _T_163 ? issue_slots_2_out_uop_is_sys_pc2epc : issue_slots_1_out_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_is_eret = _T_163 ? issue_slots_2_out_uop_is_eret : issue_slots_1_out_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_is_amo = _T_163 ? issue_slots_2_out_uop_is_amo : issue_slots_1_out_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_is_sfence = _T_163 ? issue_slots_2_out_uop_is_sfence : issue_slots_1_out_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_is_fencei = _T_163 ? issue_slots_2_out_uop_is_fencei : issue_slots_1_out_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_is_fence = _T_163 ? issue_slots_2_out_uop_is_fence : issue_slots_1_out_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_is_sfb = _T_163 ? issue_slots_2_out_uop_is_sfb : issue_slots_1_out_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_br_type = _T_163 ? issue_slots_2_out_uop_br_type : issue_slots_1_out_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_br_tag = _T_163 ? issue_slots_2_out_uop_br_tag : issue_slots_1_out_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_br_mask = _T_163 ? issue_slots_2_out_uop_br_mask : issue_slots_1_out_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_dis_col_sel = _T_163 ? issue_slots_2_out_uop_dis_col_sel : issue_slots_1_out_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_iw_p3_bypass_hint = _T_163 ? issue_slots_2_out_uop_iw_p3_bypass_hint : issue_slots_1_out_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_iw_p2_bypass_hint = _T_163 ? issue_slots_2_out_uop_iw_p2_bypass_hint : issue_slots_1_out_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_iw_p1_bypass_hint = _T_163 ? issue_slots_2_out_uop_iw_p1_bypass_hint : issue_slots_1_out_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_iw_p2_speculative_child = _T_163 ? issue_slots_2_out_uop_iw_p2_speculative_child : issue_slots_1_out_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_iw_p1_speculative_child = _T_163 ? issue_slots_2_out_uop_iw_p1_speculative_child : issue_slots_1_out_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_iw_issued = _T_163 ? issue_slots_2_out_uop_iw_issued : issue_slots_1_out_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_fu_code_0 = _T_163 ? issue_slots_2_out_uop_fu_code_0 : issue_slots_1_out_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_fu_code_1 = _T_163 ? issue_slots_2_out_uop_fu_code_1 : issue_slots_1_out_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_fu_code_2 = _T_163 ? issue_slots_2_out_uop_fu_code_2 : issue_slots_1_out_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_fu_code_3 = _T_163 ? issue_slots_2_out_uop_fu_code_3 : issue_slots_1_out_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_fu_code_4 = _T_163 ? issue_slots_2_out_uop_fu_code_4 : issue_slots_1_out_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_fu_code_5 = _T_163 ? issue_slots_2_out_uop_fu_code_5 : issue_slots_1_out_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_fu_code_6 = _T_163 ? issue_slots_2_out_uop_fu_code_6 : issue_slots_1_out_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_fu_code_7 = _T_163 ? issue_slots_2_out_uop_fu_code_7 : issue_slots_1_out_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_fu_code_8 = _T_163 ? issue_slots_2_out_uop_fu_code_8 : issue_slots_1_out_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_fu_code_9 = _T_163 ? issue_slots_2_out_uop_fu_code_9 : issue_slots_1_out_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_iq_type_0 = _T_163 ? issue_slots_2_out_uop_iq_type_0 : issue_slots_1_out_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_iq_type_1 = _T_163 ? issue_slots_2_out_uop_iq_type_1 : issue_slots_1_out_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_iq_type_2 = _T_163 ? issue_slots_2_out_uop_iq_type_2 : issue_slots_1_out_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_iq_type_3 = _T_163 ? issue_slots_2_out_uop_iq_type_3 : issue_slots_1_out_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_debug_pc = _T_163 ? issue_slots_2_out_uop_debug_pc : issue_slots_1_out_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_is_rvc = _T_163 ? issue_slots_2_out_uop_is_rvc : issue_slots_1_out_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_debug_inst = _T_163 ? issue_slots_2_out_uop_debug_inst : issue_slots_1_out_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_0_in_uop_bits_inst = _T_163 ? issue_slots_2_out_uop_inst : issue_slots_1_out_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n wire _T_165 = shamts_oh_3 == 2'h2;\t// @[issue-unit-age-ordered.scala:158:23, :194:28]\n assign issue_slots_1_in_uop_valid = _T_165 ? issue_slots_3_will_be_valid : shamts_oh_2 == 2'h1 & issue_slots_2_will_be_valid;\t// @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37]\n assign issue_slots_1_in_uop_bits_debug_tsrc = _T_165 ? issue_slots_3_out_uop_debug_tsrc : issue_slots_2_out_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_debug_fsrc = _T_165 ? issue_slots_3_out_uop_debug_fsrc : issue_slots_2_out_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_bp_xcpt_if = _T_165 ? issue_slots_3_out_uop_bp_xcpt_if : issue_slots_2_out_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_bp_debug_if = _T_165 ? issue_slots_3_out_uop_bp_debug_if : issue_slots_2_out_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_xcpt_ma_if = _T_165 ? issue_slots_3_out_uop_xcpt_ma_if : issue_slots_2_out_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_xcpt_ae_if = _T_165 ? issue_slots_3_out_uop_xcpt_ae_if : issue_slots_2_out_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_xcpt_pf_if = _T_165 ? issue_slots_3_out_uop_xcpt_pf_if : issue_slots_2_out_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_fp_typ = _T_165 ? issue_slots_3_out_uop_fp_typ : issue_slots_2_out_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_fp_rm = _T_165 ? issue_slots_3_out_uop_fp_rm : issue_slots_2_out_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_fp_val = _T_165 ? issue_slots_3_out_uop_fp_val : issue_slots_2_out_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_fcn_op = _T_165 ? issue_slots_3_out_uop_fcn_op : issue_slots_2_out_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_fcn_dw = _T_165 ? issue_slots_3_out_uop_fcn_dw : issue_slots_2_out_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_frs3_en = _T_165 ? issue_slots_3_out_uop_frs3_en : issue_slots_2_out_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_lrs2_rtype = _T_165 ? issue_slots_3_out_uop_lrs2_rtype : issue_slots_2_out_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_lrs1_rtype = _T_165 ? issue_slots_3_out_uop_lrs1_rtype : issue_slots_2_out_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_dst_rtype = _T_165 ? issue_slots_3_out_uop_dst_rtype : issue_slots_2_out_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_lrs3 = _T_165 ? issue_slots_3_out_uop_lrs3 : issue_slots_2_out_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_lrs2 = _T_165 ? issue_slots_3_out_uop_lrs2 : issue_slots_2_out_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_lrs1 = _T_165 ? issue_slots_3_out_uop_lrs1 : issue_slots_2_out_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_ldst = _T_165 ? issue_slots_3_out_uop_ldst : issue_slots_2_out_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_ldst_is_rs1 = _T_165 ? issue_slots_3_out_uop_ldst_is_rs1 : issue_slots_2_out_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_csr_cmd = _T_165 ? issue_slots_3_out_uop_csr_cmd : issue_slots_2_out_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_flush_on_commit = _T_165 ? issue_slots_3_out_uop_flush_on_commit : issue_slots_2_out_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_is_unique = _T_165 ? issue_slots_3_out_uop_is_unique : issue_slots_2_out_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_uses_stq = _T_165 ? issue_slots_3_out_uop_uses_stq : issue_slots_2_out_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_uses_ldq = _T_165 ? issue_slots_3_out_uop_uses_ldq : issue_slots_2_out_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_mem_signed = _T_165 ? issue_slots_3_out_uop_mem_signed : issue_slots_2_out_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_mem_size = _T_165 ? issue_slots_3_out_uop_mem_size : issue_slots_2_out_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_mem_cmd = _T_165 ? issue_slots_3_out_uop_mem_cmd : issue_slots_2_out_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_exc_cause = _T_165 ? issue_slots_3_out_uop_exc_cause : issue_slots_2_out_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_exception = _T_165 ? issue_slots_3_out_uop_exception : issue_slots_2_out_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_stale_pdst = _T_165 ? issue_slots_3_out_uop_stale_pdst : issue_slots_2_out_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_ppred_busy = _T_165 ? issue_slots_3_out_uop_ppred_busy : issue_slots_2_out_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_prs3_busy = _T_165 ? issue_slots_3_out_uop_prs3_busy : issue_slots_2_out_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_prs2_busy = _T_165 ? issue_slots_3_out_uop_prs2_busy : issue_slots_2_out_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_prs1_busy = _T_165 ? issue_slots_3_out_uop_prs1_busy : issue_slots_2_out_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_ppred = _T_165 ? issue_slots_3_out_uop_ppred : issue_slots_2_out_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_prs3 = _T_165 ? issue_slots_3_out_uop_prs3 : issue_slots_2_out_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_prs2 = _T_165 ? issue_slots_3_out_uop_prs2 : issue_slots_2_out_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_prs1 = _T_165 ? issue_slots_3_out_uop_prs1 : issue_slots_2_out_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_pdst = _T_165 ? issue_slots_3_out_uop_pdst : issue_slots_2_out_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_rxq_idx = _T_165 ? issue_slots_3_out_uop_rxq_idx : issue_slots_2_out_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_stq_idx = _T_165 ? issue_slots_3_out_uop_stq_idx : issue_slots_2_out_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_ldq_idx = _T_165 ? issue_slots_3_out_uop_ldq_idx : issue_slots_2_out_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_rob_idx = _T_165 ? issue_slots_3_out_uop_rob_idx : issue_slots_2_out_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_fp_ctrl_vec = _T_165 ? issue_slots_3_out_uop_fp_ctrl_vec : issue_slots_2_out_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_fp_ctrl_wflags = _T_165 ? issue_slots_3_out_uop_fp_ctrl_wflags : issue_slots_2_out_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_fp_ctrl_sqrt = _T_165 ? issue_slots_3_out_uop_fp_ctrl_sqrt : issue_slots_2_out_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_fp_ctrl_div = _T_165 ? issue_slots_3_out_uop_fp_ctrl_div : issue_slots_2_out_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_fp_ctrl_fma = _T_165 ? issue_slots_3_out_uop_fp_ctrl_fma : issue_slots_2_out_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_fp_ctrl_fastpipe = _T_165 ? issue_slots_3_out_uop_fp_ctrl_fastpipe : issue_slots_2_out_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_fp_ctrl_toint = _T_165 ? issue_slots_3_out_uop_fp_ctrl_toint : issue_slots_2_out_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_fp_ctrl_fromint = _T_165 ? issue_slots_3_out_uop_fp_ctrl_fromint : issue_slots_2_out_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_fp_ctrl_typeTagOut = _T_165 ? issue_slots_3_out_uop_fp_ctrl_typeTagOut : issue_slots_2_out_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_fp_ctrl_typeTagIn = _T_165 ? issue_slots_3_out_uop_fp_ctrl_typeTagIn : issue_slots_2_out_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_fp_ctrl_swap23 = _T_165 ? issue_slots_3_out_uop_fp_ctrl_swap23 : issue_slots_2_out_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_fp_ctrl_swap12 = _T_165 ? issue_slots_3_out_uop_fp_ctrl_swap12 : issue_slots_2_out_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_fp_ctrl_ren3 = _T_165 ? issue_slots_3_out_uop_fp_ctrl_ren3 : issue_slots_2_out_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_fp_ctrl_ren2 = _T_165 ? issue_slots_3_out_uop_fp_ctrl_ren2 : issue_slots_2_out_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_fp_ctrl_ren1 = _T_165 ? issue_slots_3_out_uop_fp_ctrl_ren1 : issue_slots_2_out_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_fp_ctrl_wen = _T_165 ? issue_slots_3_out_uop_fp_ctrl_wen : issue_slots_2_out_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_fp_ctrl_ldst = _T_165 ? issue_slots_3_out_uop_fp_ctrl_ldst : issue_slots_2_out_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_op2_sel = _T_165 ? issue_slots_3_out_uop_op2_sel : issue_slots_2_out_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_op1_sel = _T_165 ? issue_slots_3_out_uop_op1_sel : issue_slots_2_out_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_imm_packed = _T_165 ? issue_slots_3_out_uop_imm_packed : issue_slots_2_out_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_pimm = _T_165 ? issue_slots_3_out_uop_pimm : issue_slots_2_out_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_imm_sel = _T_165 ? issue_slots_3_out_uop_imm_sel : issue_slots_2_out_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_imm_rename = _T_165 ? issue_slots_3_out_uop_imm_rename : issue_slots_2_out_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_taken = _T_165 ? issue_slots_3_out_uop_taken : issue_slots_2_out_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_pc_lob = _T_165 ? issue_slots_3_out_uop_pc_lob : issue_slots_2_out_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_edge_inst = _T_165 ? issue_slots_3_out_uop_edge_inst : issue_slots_2_out_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_ftq_idx = _T_165 ? issue_slots_3_out_uop_ftq_idx : issue_slots_2_out_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_is_mov = _T_165 ? issue_slots_3_out_uop_is_mov : issue_slots_2_out_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_is_rocc = _T_165 ? issue_slots_3_out_uop_is_rocc : issue_slots_2_out_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_is_sys_pc2epc = _T_165 ? issue_slots_3_out_uop_is_sys_pc2epc : issue_slots_2_out_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_is_eret = _T_165 ? issue_slots_3_out_uop_is_eret : issue_slots_2_out_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_is_amo = _T_165 ? issue_slots_3_out_uop_is_amo : issue_slots_2_out_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_is_sfence = _T_165 ? issue_slots_3_out_uop_is_sfence : issue_slots_2_out_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_is_fencei = _T_165 ? issue_slots_3_out_uop_is_fencei : issue_slots_2_out_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_is_fence = _T_165 ? issue_slots_3_out_uop_is_fence : issue_slots_2_out_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_is_sfb = _T_165 ? issue_slots_3_out_uop_is_sfb : issue_slots_2_out_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_br_type = _T_165 ? issue_slots_3_out_uop_br_type : issue_slots_2_out_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_br_tag = _T_165 ? issue_slots_3_out_uop_br_tag : issue_slots_2_out_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_br_mask = _T_165 ? issue_slots_3_out_uop_br_mask : issue_slots_2_out_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_dis_col_sel = _T_165 ? issue_slots_3_out_uop_dis_col_sel : issue_slots_2_out_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_iw_p3_bypass_hint = _T_165 ? issue_slots_3_out_uop_iw_p3_bypass_hint : issue_slots_2_out_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_iw_p2_bypass_hint = _T_165 ? issue_slots_3_out_uop_iw_p2_bypass_hint : issue_slots_2_out_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_iw_p1_bypass_hint = _T_165 ? issue_slots_3_out_uop_iw_p1_bypass_hint : issue_slots_2_out_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_iw_p2_speculative_child = _T_165 ? issue_slots_3_out_uop_iw_p2_speculative_child : issue_slots_2_out_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_iw_p1_speculative_child = _T_165 ? issue_slots_3_out_uop_iw_p1_speculative_child : issue_slots_2_out_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_iw_issued = _T_165 ? issue_slots_3_out_uop_iw_issued : issue_slots_2_out_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_fu_code_0 = _T_165 ? issue_slots_3_out_uop_fu_code_0 : issue_slots_2_out_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_fu_code_1 = _T_165 ? issue_slots_3_out_uop_fu_code_1 : issue_slots_2_out_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_fu_code_2 = _T_165 ? issue_slots_3_out_uop_fu_code_2 : issue_slots_2_out_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_fu_code_3 = _T_165 ? issue_slots_3_out_uop_fu_code_3 : issue_slots_2_out_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_fu_code_4 = _T_165 ? issue_slots_3_out_uop_fu_code_4 : issue_slots_2_out_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_fu_code_5 = _T_165 ? issue_slots_3_out_uop_fu_code_5 : issue_slots_2_out_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_fu_code_6 = _T_165 ? issue_slots_3_out_uop_fu_code_6 : issue_slots_2_out_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_fu_code_7 = _T_165 ? issue_slots_3_out_uop_fu_code_7 : issue_slots_2_out_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_fu_code_8 = _T_165 ? issue_slots_3_out_uop_fu_code_8 : issue_slots_2_out_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_fu_code_9 = _T_165 ? issue_slots_3_out_uop_fu_code_9 : issue_slots_2_out_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_iq_type_0 = _T_165 ? issue_slots_3_out_uop_iq_type_0 : issue_slots_2_out_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_iq_type_1 = _T_165 ? issue_slots_3_out_uop_iq_type_1 : issue_slots_2_out_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_iq_type_2 = _T_165 ? issue_slots_3_out_uop_iq_type_2 : issue_slots_2_out_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_iq_type_3 = _T_165 ? issue_slots_3_out_uop_iq_type_3 : issue_slots_2_out_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_debug_pc = _T_165 ? issue_slots_3_out_uop_debug_pc : issue_slots_2_out_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_is_rvc = _T_165 ? issue_slots_3_out_uop_is_rvc : issue_slots_2_out_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_debug_inst = _T_165 ? issue_slots_3_out_uop_debug_inst : issue_slots_2_out_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_1_in_uop_bits_inst = _T_165 ? issue_slots_3_out_uop_inst : issue_slots_2_out_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign _issue_slots_1_clear_T = |shamts_oh_1;\t// @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49]\n assign issue_slots_1_clear = _issue_slots_1_clear_T;\t// @[issue-unit-age-ordered.scala:122:28, :199:49]\n wire _T_167 = shamts_oh_4 == 2'h2;\t// @[issue-unit-age-ordered.scala:158:23, :194:28]\n assign issue_slots_2_in_uop_valid = _T_167 ? issue_slots_4_will_be_valid : shamts_oh_3 == 2'h1 & issue_slots_3_will_be_valid;\t// @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37]\n assign issue_slots_2_in_uop_bits_debug_tsrc = _T_167 ? issue_slots_4_out_uop_debug_tsrc : issue_slots_3_out_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_debug_fsrc = _T_167 ? issue_slots_4_out_uop_debug_fsrc : issue_slots_3_out_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_bp_xcpt_if = _T_167 ? issue_slots_4_out_uop_bp_xcpt_if : issue_slots_3_out_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_bp_debug_if = _T_167 ? issue_slots_4_out_uop_bp_debug_if : issue_slots_3_out_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_xcpt_ma_if = _T_167 ? issue_slots_4_out_uop_xcpt_ma_if : issue_slots_3_out_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_xcpt_ae_if = _T_167 ? issue_slots_4_out_uop_xcpt_ae_if : issue_slots_3_out_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_xcpt_pf_if = _T_167 ? issue_slots_4_out_uop_xcpt_pf_if : issue_slots_3_out_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_fp_typ = _T_167 ? issue_slots_4_out_uop_fp_typ : issue_slots_3_out_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_fp_rm = _T_167 ? issue_slots_4_out_uop_fp_rm : issue_slots_3_out_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_fp_val = _T_167 ? issue_slots_4_out_uop_fp_val : issue_slots_3_out_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_fcn_op = _T_167 ? issue_slots_4_out_uop_fcn_op : issue_slots_3_out_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_fcn_dw = _T_167 ? issue_slots_4_out_uop_fcn_dw : issue_slots_3_out_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_frs3_en = _T_167 ? issue_slots_4_out_uop_frs3_en : issue_slots_3_out_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_lrs2_rtype = _T_167 ? issue_slots_4_out_uop_lrs2_rtype : issue_slots_3_out_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_lrs1_rtype = _T_167 ? issue_slots_4_out_uop_lrs1_rtype : issue_slots_3_out_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_dst_rtype = _T_167 ? issue_slots_4_out_uop_dst_rtype : issue_slots_3_out_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_lrs3 = _T_167 ? issue_slots_4_out_uop_lrs3 : issue_slots_3_out_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_lrs2 = _T_167 ? issue_slots_4_out_uop_lrs2 : issue_slots_3_out_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_lrs1 = _T_167 ? issue_slots_4_out_uop_lrs1 : issue_slots_3_out_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_ldst = _T_167 ? issue_slots_4_out_uop_ldst : issue_slots_3_out_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_ldst_is_rs1 = _T_167 ? issue_slots_4_out_uop_ldst_is_rs1 : issue_slots_3_out_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_csr_cmd = _T_167 ? issue_slots_4_out_uop_csr_cmd : issue_slots_3_out_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_flush_on_commit = _T_167 ? issue_slots_4_out_uop_flush_on_commit : issue_slots_3_out_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_is_unique = _T_167 ? issue_slots_4_out_uop_is_unique : issue_slots_3_out_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_uses_stq = _T_167 ? issue_slots_4_out_uop_uses_stq : issue_slots_3_out_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_uses_ldq = _T_167 ? issue_slots_4_out_uop_uses_ldq : issue_slots_3_out_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_mem_signed = _T_167 ? issue_slots_4_out_uop_mem_signed : issue_slots_3_out_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_mem_size = _T_167 ? issue_slots_4_out_uop_mem_size : issue_slots_3_out_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_mem_cmd = _T_167 ? issue_slots_4_out_uop_mem_cmd : issue_slots_3_out_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_exc_cause = _T_167 ? issue_slots_4_out_uop_exc_cause : issue_slots_3_out_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_exception = _T_167 ? issue_slots_4_out_uop_exception : issue_slots_3_out_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_stale_pdst = _T_167 ? issue_slots_4_out_uop_stale_pdst : issue_slots_3_out_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_ppred_busy = _T_167 ? issue_slots_4_out_uop_ppred_busy : issue_slots_3_out_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_prs3_busy = _T_167 ? issue_slots_4_out_uop_prs3_busy : issue_slots_3_out_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_prs2_busy = _T_167 ? issue_slots_4_out_uop_prs2_busy : issue_slots_3_out_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_prs1_busy = _T_167 ? issue_slots_4_out_uop_prs1_busy : issue_slots_3_out_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_ppred = _T_167 ? issue_slots_4_out_uop_ppred : issue_slots_3_out_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_prs3 = _T_167 ? issue_slots_4_out_uop_prs3 : issue_slots_3_out_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_prs2 = _T_167 ? issue_slots_4_out_uop_prs2 : issue_slots_3_out_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_prs1 = _T_167 ? issue_slots_4_out_uop_prs1 : issue_slots_3_out_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_pdst = _T_167 ? issue_slots_4_out_uop_pdst : issue_slots_3_out_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_rxq_idx = _T_167 ? issue_slots_4_out_uop_rxq_idx : issue_slots_3_out_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_stq_idx = _T_167 ? issue_slots_4_out_uop_stq_idx : issue_slots_3_out_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_ldq_idx = _T_167 ? issue_slots_4_out_uop_ldq_idx : issue_slots_3_out_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_rob_idx = _T_167 ? issue_slots_4_out_uop_rob_idx : issue_slots_3_out_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_fp_ctrl_vec = _T_167 ? issue_slots_4_out_uop_fp_ctrl_vec : issue_slots_3_out_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_fp_ctrl_wflags = _T_167 ? issue_slots_4_out_uop_fp_ctrl_wflags : issue_slots_3_out_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_fp_ctrl_sqrt = _T_167 ? issue_slots_4_out_uop_fp_ctrl_sqrt : issue_slots_3_out_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_fp_ctrl_div = _T_167 ? issue_slots_4_out_uop_fp_ctrl_div : issue_slots_3_out_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_fp_ctrl_fma = _T_167 ? issue_slots_4_out_uop_fp_ctrl_fma : issue_slots_3_out_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_fp_ctrl_fastpipe = _T_167 ? issue_slots_4_out_uop_fp_ctrl_fastpipe : issue_slots_3_out_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_fp_ctrl_toint = _T_167 ? issue_slots_4_out_uop_fp_ctrl_toint : issue_slots_3_out_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_fp_ctrl_fromint = _T_167 ? issue_slots_4_out_uop_fp_ctrl_fromint : issue_slots_3_out_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_fp_ctrl_typeTagOut = _T_167 ? issue_slots_4_out_uop_fp_ctrl_typeTagOut : issue_slots_3_out_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_fp_ctrl_typeTagIn = _T_167 ? issue_slots_4_out_uop_fp_ctrl_typeTagIn : issue_slots_3_out_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_fp_ctrl_swap23 = _T_167 ? issue_slots_4_out_uop_fp_ctrl_swap23 : issue_slots_3_out_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_fp_ctrl_swap12 = _T_167 ? issue_slots_4_out_uop_fp_ctrl_swap12 : issue_slots_3_out_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_fp_ctrl_ren3 = _T_167 ? issue_slots_4_out_uop_fp_ctrl_ren3 : issue_slots_3_out_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_fp_ctrl_ren2 = _T_167 ? issue_slots_4_out_uop_fp_ctrl_ren2 : issue_slots_3_out_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_fp_ctrl_ren1 = _T_167 ? issue_slots_4_out_uop_fp_ctrl_ren1 : issue_slots_3_out_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_fp_ctrl_wen = _T_167 ? issue_slots_4_out_uop_fp_ctrl_wen : issue_slots_3_out_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_fp_ctrl_ldst = _T_167 ? issue_slots_4_out_uop_fp_ctrl_ldst : issue_slots_3_out_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_op2_sel = _T_167 ? issue_slots_4_out_uop_op2_sel : issue_slots_3_out_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_op1_sel = _T_167 ? issue_slots_4_out_uop_op1_sel : issue_slots_3_out_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_imm_packed = _T_167 ? issue_slots_4_out_uop_imm_packed : issue_slots_3_out_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_pimm = _T_167 ? issue_slots_4_out_uop_pimm : issue_slots_3_out_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_imm_sel = _T_167 ? issue_slots_4_out_uop_imm_sel : issue_slots_3_out_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_imm_rename = _T_167 ? issue_slots_4_out_uop_imm_rename : issue_slots_3_out_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_taken = _T_167 ? issue_slots_4_out_uop_taken : issue_slots_3_out_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_pc_lob = _T_167 ? issue_slots_4_out_uop_pc_lob : issue_slots_3_out_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_edge_inst = _T_167 ? issue_slots_4_out_uop_edge_inst : issue_slots_3_out_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_ftq_idx = _T_167 ? issue_slots_4_out_uop_ftq_idx : issue_slots_3_out_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_is_mov = _T_167 ? issue_slots_4_out_uop_is_mov : issue_slots_3_out_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_is_rocc = _T_167 ? issue_slots_4_out_uop_is_rocc : issue_slots_3_out_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_is_sys_pc2epc = _T_167 ? issue_slots_4_out_uop_is_sys_pc2epc : issue_slots_3_out_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_is_eret = _T_167 ? issue_slots_4_out_uop_is_eret : issue_slots_3_out_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_is_amo = _T_167 ? issue_slots_4_out_uop_is_amo : issue_slots_3_out_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_is_sfence = _T_167 ? issue_slots_4_out_uop_is_sfence : issue_slots_3_out_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_is_fencei = _T_167 ? issue_slots_4_out_uop_is_fencei : issue_slots_3_out_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_is_fence = _T_167 ? issue_slots_4_out_uop_is_fence : issue_slots_3_out_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_is_sfb = _T_167 ? issue_slots_4_out_uop_is_sfb : issue_slots_3_out_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_br_type = _T_167 ? issue_slots_4_out_uop_br_type : issue_slots_3_out_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_br_tag = _T_167 ? issue_slots_4_out_uop_br_tag : issue_slots_3_out_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_br_mask = _T_167 ? issue_slots_4_out_uop_br_mask : issue_slots_3_out_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_dis_col_sel = _T_167 ? issue_slots_4_out_uop_dis_col_sel : issue_slots_3_out_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_iw_p3_bypass_hint = _T_167 ? issue_slots_4_out_uop_iw_p3_bypass_hint : issue_slots_3_out_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_iw_p2_bypass_hint = _T_167 ? issue_slots_4_out_uop_iw_p2_bypass_hint : issue_slots_3_out_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_iw_p1_bypass_hint = _T_167 ? issue_slots_4_out_uop_iw_p1_bypass_hint : issue_slots_3_out_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_iw_p2_speculative_child = _T_167 ? issue_slots_4_out_uop_iw_p2_speculative_child : issue_slots_3_out_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_iw_p1_speculative_child = _T_167 ? issue_slots_4_out_uop_iw_p1_speculative_child : issue_slots_3_out_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_iw_issued = _T_167 ? issue_slots_4_out_uop_iw_issued : issue_slots_3_out_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_fu_code_0 = _T_167 ? issue_slots_4_out_uop_fu_code_0 : issue_slots_3_out_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_fu_code_1 = _T_167 ? issue_slots_4_out_uop_fu_code_1 : issue_slots_3_out_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_fu_code_2 = _T_167 ? issue_slots_4_out_uop_fu_code_2 : issue_slots_3_out_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_fu_code_3 = _T_167 ? issue_slots_4_out_uop_fu_code_3 : issue_slots_3_out_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_fu_code_4 = _T_167 ? issue_slots_4_out_uop_fu_code_4 : issue_slots_3_out_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_fu_code_5 = _T_167 ? issue_slots_4_out_uop_fu_code_5 : issue_slots_3_out_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_fu_code_6 = _T_167 ? issue_slots_4_out_uop_fu_code_6 : issue_slots_3_out_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_fu_code_7 = _T_167 ? issue_slots_4_out_uop_fu_code_7 : issue_slots_3_out_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_fu_code_8 = _T_167 ? issue_slots_4_out_uop_fu_code_8 : issue_slots_3_out_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_fu_code_9 = _T_167 ? issue_slots_4_out_uop_fu_code_9 : issue_slots_3_out_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_iq_type_0 = _T_167 ? issue_slots_4_out_uop_iq_type_0 : issue_slots_3_out_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_iq_type_1 = _T_167 ? issue_slots_4_out_uop_iq_type_1 : issue_slots_3_out_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_iq_type_2 = _T_167 ? issue_slots_4_out_uop_iq_type_2 : issue_slots_3_out_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_iq_type_3 = _T_167 ? issue_slots_4_out_uop_iq_type_3 : issue_slots_3_out_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_debug_pc = _T_167 ? issue_slots_4_out_uop_debug_pc : issue_slots_3_out_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_is_rvc = _T_167 ? issue_slots_4_out_uop_is_rvc : issue_slots_3_out_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_debug_inst = _T_167 ? issue_slots_4_out_uop_debug_inst : issue_slots_3_out_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_2_in_uop_bits_inst = _T_167 ? issue_slots_4_out_uop_inst : issue_slots_3_out_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign _issue_slots_2_clear_T = |shamts_oh_2;\t// @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49]\n assign issue_slots_2_clear = _issue_slots_2_clear_T;\t// @[issue-unit-age-ordered.scala:122:28, :199:49]\n wire _T_169 = shamts_oh_5 == 2'h2;\t// @[issue-unit-age-ordered.scala:158:23, :194:28]\n assign issue_slots_3_in_uop_valid = _T_169 ? issue_slots_5_will_be_valid : shamts_oh_4 == 2'h1 & issue_slots_4_will_be_valid;\t// @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37]\n assign issue_slots_3_in_uop_bits_debug_tsrc = _T_169 ? issue_slots_5_out_uop_debug_tsrc : issue_slots_4_out_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_debug_fsrc = _T_169 ? issue_slots_5_out_uop_debug_fsrc : issue_slots_4_out_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_bp_xcpt_if = _T_169 ? issue_slots_5_out_uop_bp_xcpt_if : issue_slots_4_out_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_bp_debug_if = _T_169 ? issue_slots_5_out_uop_bp_debug_if : issue_slots_4_out_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_xcpt_ma_if = _T_169 ? issue_slots_5_out_uop_xcpt_ma_if : issue_slots_4_out_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_xcpt_ae_if = _T_169 ? issue_slots_5_out_uop_xcpt_ae_if : issue_slots_4_out_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_xcpt_pf_if = _T_169 ? issue_slots_5_out_uop_xcpt_pf_if : issue_slots_4_out_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_fp_typ = _T_169 ? issue_slots_5_out_uop_fp_typ : issue_slots_4_out_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_fp_rm = _T_169 ? issue_slots_5_out_uop_fp_rm : issue_slots_4_out_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_fp_val = _T_169 ? issue_slots_5_out_uop_fp_val : issue_slots_4_out_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_fcn_op = _T_169 ? issue_slots_5_out_uop_fcn_op : issue_slots_4_out_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_fcn_dw = _T_169 ? issue_slots_5_out_uop_fcn_dw : issue_slots_4_out_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_frs3_en = _T_169 ? issue_slots_5_out_uop_frs3_en : issue_slots_4_out_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_lrs2_rtype = _T_169 ? issue_slots_5_out_uop_lrs2_rtype : issue_slots_4_out_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_lrs1_rtype = _T_169 ? issue_slots_5_out_uop_lrs1_rtype : issue_slots_4_out_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_dst_rtype = _T_169 ? issue_slots_5_out_uop_dst_rtype : issue_slots_4_out_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_lrs3 = _T_169 ? issue_slots_5_out_uop_lrs3 : issue_slots_4_out_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_lrs2 = _T_169 ? issue_slots_5_out_uop_lrs2 : issue_slots_4_out_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_lrs1 = _T_169 ? issue_slots_5_out_uop_lrs1 : issue_slots_4_out_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_ldst = _T_169 ? issue_slots_5_out_uop_ldst : issue_slots_4_out_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_ldst_is_rs1 = _T_169 ? issue_slots_5_out_uop_ldst_is_rs1 : issue_slots_4_out_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_csr_cmd = _T_169 ? issue_slots_5_out_uop_csr_cmd : issue_slots_4_out_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_flush_on_commit = _T_169 ? issue_slots_5_out_uop_flush_on_commit : issue_slots_4_out_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_is_unique = _T_169 ? issue_slots_5_out_uop_is_unique : issue_slots_4_out_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_uses_stq = _T_169 ? issue_slots_5_out_uop_uses_stq : issue_slots_4_out_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_uses_ldq = _T_169 ? issue_slots_5_out_uop_uses_ldq : issue_slots_4_out_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_mem_signed = _T_169 ? issue_slots_5_out_uop_mem_signed : issue_slots_4_out_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_mem_size = _T_169 ? issue_slots_5_out_uop_mem_size : issue_slots_4_out_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_mem_cmd = _T_169 ? issue_slots_5_out_uop_mem_cmd : issue_slots_4_out_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_exc_cause = _T_169 ? issue_slots_5_out_uop_exc_cause : issue_slots_4_out_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_exception = _T_169 ? issue_slots_5_out_uop_exception : issue_slots_4_out_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_stale_pdst = _T_169 ? issue_slots_5_out_uop_stale_pdst : issue_slots_4_out_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_ppred_busy = _T_169 ? issue_slots_5_out_uop_ppred_busy : issue_slots_4_out_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_prs3_busy = _T_169 ? issue_slots_5_out_uop_prs3_busy : issue_slots_4_out_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_prs2_busy = _T_169 ? issue_slots_5_out_uop_prs2_busy : issue_slots_4_out_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_prs1_busy = _T_169 ? issue_slots_5_out_uop_prs1_busy : issue_slots_4_out_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_ppred = _T_169 ? issue_slots_5_out_uop_ppred : issue_slots_4_out_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_prs3 = _T_169 ? issue_slots_5_out_uop_prs3 : issue_slots_4_out_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_prs2 = _T_169 ? issue_slots_5_out_uop_prs2 : issue_slots_4_out_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_prs1 = _T_169 ? issue_slots_5_out_uop_prs1 : issue_slots_4_out_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_pdst = _T_169 ? issue_slots_5_out_uop_pdst : issue_slots_4_out_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_rxq_idx = _T_169 ? issue_slots_5_out_uop_rxq_idx : issue_slots_4_out_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_stq_idx = _T_169 ? issue_slots_5_out_uop_stq_idx : issue_slots_4_out_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_ldq_idx = _T_169 ? issue_slots_5_out_uop_ldq_idx : issue_slots_4_out_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_rob_idx = _T_169 ? issue_slots_5_out_uop_rob_idx : issue_slots_4_out_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_fp_ctrl_vec = _T_169 ? issue_slots_5_out_uop_fp_ctrl_vec : issue_slots_4_out_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_fp_ctrl_wflags = _T_169 ? issue_slots_5_out_uop_fp_ctrl_wflags : issue_slots_4_out_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_fp_ctrl_sqrt = _T_169 ? issue_slots_5_out_uop_fp_ctrl_sqrt : issue_slots_4_out_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_fp_ctrl_div = _T_169 ? issue_slots_5_out_uop_fp_ctrl_div : issue_slots_4_out_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_fp_ctrl_fma = _T_169 ? issue_slots_5_out_uop_fp_ctrl_fma : issue_slots_4_out_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_fp_ctrl_fastpipe = _T_169 ? issue_slots_5_out_uop_fp_ctrl_fastpipe : issue_slots_4_out_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_fp_ctrl_toint = _T_169 ? issue_slots_5_out_uop_fp_ctrl_toint : issue_slots_4_out_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_fp_ctrl_fromint = _T_169 ? issue_slots_5_out_uop_fp_ctrl_fromint : issue_slots_4_out_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_fp_ctrl_typeTagOut = _T_169 ? issue_slots_5_out_uop_fp_ctrl_typeTagOut : issue_slots_4_out_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_fp_ctrl_typeTagIn = _T_169 ? issue_slots_5_out_uop_fp_ctrl_typeTagIn : issue_slots_4_out_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_fp_ctrl_swap23 = _T_169 ? issue_slots_5_out_uop_fp_ctrl_swap23 : issue_slots_4_out_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_fp_ctrl_swap12 = _T_169 ? issue_slots_5_out_uop_fp_ctrl_swap12 : issue_slots_4_out_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_fp_ctrl_ren3 = _T_169 ? issue_slots_5_out_uop_fp_ctrl_ren3 : issue_slots_4_out_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_fp_ctrl_ren2 = _T_169 ? issue_slots_5_out_uop_fp_ctrl_ren2 : issue_slots_4_out_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_fp_ctrl_ren1 = _T_169 ? issue_slots_5_out_uop_fp_ctrl_ren1 : issue_slots_4_out_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_fp_ctrl_wen = _T_169 ? issue_slots_5_out_uop_fp_ctrl_wen : issue_slots_4_out_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_fp_ctrl_ldst = _T_169 ? issue_slots_5_out_uop_fp_ctrl_ldst : issue_slots_4_out_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_op2_sel = _T_169 ? issue_slots_5_out_uop_op2_sel : issue_slots_4_out_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_op1_sel = _T_169 ? issue_slots_5_out_uop_op1_sel : issue_slots_4_out_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_imm_packed = _T_169 ? issue_slots_5_out_uop_imm_packed : issue_slots_4_out_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_pimm = _T_169 ? issue_slots_5_out_uop_pimm : issue_slots_4_out_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_imm_sel = _T_169 ? issue_slots_5_out_uop_imm_sel : issue_slots_4_out_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_imm_rename = _T_169 ? issue_slots_5_out_uop_imm_rename : issue_slots_4_out_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_taken = _T_169 ? issue_slots_5_out_uop_taken : issue_slots_4_out_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_pc_lob = _T_169 ? issue_slots_5_out_uop_pc_lob : issue_slots_4_out_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_edge_inst = _T_169 ? issue_slots_5_out_uop_edge_inst : issue_slots_4_out_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_ftq_idx = _T_169 ? issue_slots_5_out_uop_ftq_idx : issue_slots_4_out_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_is_mov = _T_169 ? issue_slots_5_out_uop_is_mov : issue_slots_4_out_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_is_rocc = _T_169 ? issue_slots_5_out_uop_is_rocc : issue_slots_4_out_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_is_sys_pc2epc = _T_169 ? issue_slots_5_out_uop_is_sys_pc2epc : issue_slots_4_out_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_is_eret = _T_169 ? issue_slots_5_out_uop_is_eret : issue_slots_4_out_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_is_amo = _T_169 ? issue_slots_5_out_uop_is_amo : issue_slots_4_out_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_is_sfence = _T_169 ? issue_slots_5_out_uop_is_sfence : issue_slots_4_out_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_is_fencei = _T_169 ? issue_slots_5_out_uop_is_fencei : issue_slots_4_out_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_is_fence = _T_169 ? issue_slots_5_out_uop_is_fence : issue_slots_4_out_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_is_sfb = _T_169 ? issue_slots_5_out_uop_is_sfb : issue_slots_4_out_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_br_type = _T_169 ? issue_slots_5_out_uop_br_type : issue_slots_4_out_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_br_tag = _T_169 ? issue_slots_5_out_uop_br_tag : issue_slots_4_out_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_br_mask = _T_169 ? issue_slots_5_out_uop_br_mask : issue_slots_4_out_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_dis_col_sel = _T_169 ? issue_slots_5_out_uop_dis_col_sel : issue_slots_4_out_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_iw_p3_bypass_hint = _T_169 ? issue_slots_5_out_uop_iw_p3_bypass_hint : issue_slots_4_out_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_iw_p2_bypass_hint = _T_169 ? issue_slots_5_out_uop_iw_p2_bypass_hint : issue_slots_4_out_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_iw_p1_bypass_hint = _T_169 ? issue_slots_5_out_uop_iw_p1_bypass_hint : issue_slots_4_out_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_iw_p2_speculative_child = _T_169 ? issue_slots_5_out_uop_iw_p2_speculative_child : issue_slots_4_out_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_iw_p1_speculative_child = _T_169 ? issue_slots_5_out_uop_iw_p1_speculative_child : issue_slots_4_out_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_iw_issued = _T_169 ? issue_slots_5_out_uop_iw_issued : issue_slots_4_out_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_fu_code_0 = _T_169 ? issue_slots_5_out_uop_fu_code_0 : issue_slots_4_out_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_fu_code_1 = _T_169 ? issue_slots_5_out_uop_fu_code_1 : issue_slots_4_out_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_fu_code_2 = _T_169 ? issue_slots_5_out_uop_fu_code_2 : issue_slots_4_out_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_fu_code_3 = _T_169 ? issue_slots_5_out_uop_fu_code_3 : issue_slots_4_out_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_fu_code_4 = _T_169 ? issue_slots_5_out_uop_fu_code_4 : issue_slots_4_out_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_fu_code_5 = _T_169 ? issue_slots_5_out_uop_fu_code_5 : issue_slots_4_out_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_fu_code_6 = _T_169 ? issue_slots_5_out_uop_fu_code_6 : issue_slots_4_out_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_fu_code_7 = _T_169 ? issue_slots_5_out_uop_fu_code_7 : issue_slots_4_out_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_fu_code_8 = _T_169 ? issue_slots_5_out_uop_fu_code_8 : issue_slots_4_out_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_fu_code_9 = _T_169 ? issue_slots_5_out_uop_fu_code_9 : issue_slots_4_out_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_iq_type_0 = _T_169 ? issue_slots_5_out_uop_iq_type_0 : issue_slots_4_out_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_iq_type_1 = _T_169 ? issue_slots_5_out_uop_iq_type_1 : issue_slots_4_out_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_iq_type_2 = _T_169 ? issue_slots_5_out_uop_iq_type_2 : issue_slots_4_out_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_iq_type_3 = _T_169 ? issue_slots_5_out_uop_iq_type_3 : issue_slots_4_out_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_debug_pc = _T_169 ? issue_slots_5_out_uop_debug_pc : issue_slots_4_out_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_is_rvc = _T_169 ? issue_slots_5_out_uop_is_rvc : issue_slots_4_out_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_debug_inst = _T_169 ? issue_slots_5_out_uop_debug_inst : issue_slots_4_out_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_3_in_uop_bits_inst = _T_169 ? issue_slots_5_out_uop_inst : issue_slots_4_out_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign _issue_slots_3_clear_T = |shamts_oh_3;\t// @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49]\n assign issue_slots_3_clear = _issue_slots_3_clear_T;\t// @[issue-unit-age-ordered.scala:122:28, :199:49]\n wire _T_171 = shamts_oh_6 == 2'h2;\t// @[issue-unit-age-ordered.scala:158:23, :194:28]\n assign issue_slots_4_in_uop_valid = _T_171 ? issue_slots_6_will_be_valid : shamts_oh_5 == 2'h1 & issue_slots_5_will_be_valid;\t// @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37]\n assign issue_slots_4_in_uop_bits_debug_tsrc = _T_171 ? issue_slots_6_out_uop_debug_tsrc : issue_slots_5_out_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_debug_fsrc = _T_171 ? issue_slots_6_out_uop_debug_fsrc : issue_slots_5_out_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_bp_xcpt_if = _T_171 ? issue_slots_6_out_uop_bp_xcpt_if : issue_slots_5_out_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_bp_debug_if = _T_171 ? issue_slots_6_out_uop_bp_debug_if : issue_slots_5_out_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_xcpt_ma_if = _T_171 ? issue_slots_6_out_uop_xcpt_ma_if : issue_slots_5_out_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_xcpt_ae_if = _T_171 ? issue_slots_6_out_uop_xcpt_ae_if : issue_slots_5_out_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_xcpt_pf_if = _T_171 ? issue_slots_6_out_uop_xcpt_pf_if : issue_slots_5_out_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_fp_typ = _T_171 ? issue_slots_6_out_uop_fp_typ : issue_slots_5_out_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_fp_rm = _T_171 ? issue_slots_6_out_uop_fp_rm : issue_slots_5_out_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_fp_val = _T_171 ? issue_slots_6_out_uop_fp_val : issue_slots_5_out_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_fcn_op = _T_171 ? issue_slots_6_out_uop_fcn_op : issue_slots_5_out_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_fcn_dw = _T_171 ? issue_slots_6_out_uop_fcn_dw : issue_slots_5_out_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_frs3_en = _T_171 ? issue_slots_6_out_uop_frs3_en : issue_slots_5_out_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_lrs2_rtype = _T_171 ? issue_slots_6_out_uop_lrs2_rtype : issue_slots_5_out_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_lrs1_rtype = _T_171 ? issue_slots_6_out_uop_lrs1_rtype : issue_slots_5_out_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_dst_rtype = _T_171 ? issue_slots_6_out_uop_dst_rtype : issue_slots_5_out_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_lrs3 = _T_171 ? issue_slots_6_out_uop_lrs3 : issue_slots_5_out_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_lrs2 = _T_171 ? issue_slots_6_out_uop_lrs2 : issue_slots_5_out_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_lrs1 = _T_171 ? issue_slots_6_out_uop_lrs1 : issue_slots_5_out_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_ldst = _T_171 ? issue_slots_6_out_uop_ldst : issue_slots_5_out_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_ldst_is_rs1 = _T_171 ? issue_slots_6_out_uop_ldst_is_rs1 : issue_slots_5_out_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_csr_cmd = _T_171 ? issue_slots_6_out_uop_csr_cmd : issue_slots_5_out_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_flush_on_commit = _T_171 ? issue_slots_6_out_uop_flush_on_commit : issue_slots_5_out_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_is_unique = _T_171 ? issue_slots_6_out_uop_is_unique : issue_slots_5_out_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_uses_stq = _T_171 ? issue_slots_6_out_uop_uses_stq : issue_slots_5_out_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_uses_ldq = _T_171 ? issue_slots_6_out_uop_uses_ldq : issue_slots_5_out_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_mem_signed = _T_171 ? issue_slots_6_out_uop_mem_signed : issue_slots_5_out_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_mem_size = _T_171 ? issue_slots_6_out_uop_mem_size : issue_slots_5_out_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_mem_cmd = _T_171 ? issue_slots_6_out_uop_mem_cmd : issue_slots_5_out_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_exc_cause = _T_171 ? issue_slots_6_out_uop_exc_cause : issue_slots_5_out_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_exception = _T_171 ? issue_slots_6_out_uop_exception : issue_slots_5_out_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_stale_pdst = _T_171 ? issue_slots_6_out_uop_stale_pdst : issue_slots_5_out_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_ppred_busy = _T_171 ? issue_slots_6_out_uop_ppred_busy : issue_slots_5_out_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_prs3_busy = _T_171 ? issue_slots_6_out_uop_prs3_busy : issue_slots_5_out_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_prs2_busy = _T_171 ? issue_slots_6_out_uop_prs2_busy : issue_slots_5_out_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_prs1_busy = _T_171 ? issue_slots_6_out_uop_prs1_busy : issue_slots_5_out_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_ppred = _T_171 ? issue_slots_6_out_uop_ppred : issue_slots_5_out_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_prs3 = _T_171 ? issue_slots_6_out_uop_prs3 : issue_slots_5_out_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_prs2 = _T_171 ? issue_slots_6_out_uop_prs2 : issue_slots_5_out_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_prs1 = _T_171 ? issue_slots_6_out_uop_prs1 : issue_slots_5_out_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_pdst = _T_171 ? issue_slots_6_out_uop_pdst : issue_slots_5_out_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_rxq_idx = _T_171 ? issue_slots_6_out_uop_rxq_idx : issue_slots_5_out_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_stq_idx = _T_171 ? issue_slots_6_out_uop_stq_idx : issue_slots_5_out_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_ldq_idx = _T_171 ? issue_slots_6_out_uop_ldq_idx : issue_slots_5_out_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_rob_idx = _T_171 ? issue_slots_6_out_uop_rob_idx : issue_slots_5_out_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_fp_ctrl_vec = _T_171 ? issue_slots_6_out_uop_fp_ctrl_vec : issue_slots_5_out_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_fp_ctrl_wflags = _T_171 ? issue_slots_6_out_uop_fp_ctrl_wflags : issue_slots_5_out_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_fp_ctrl_sqrt = _T_171 ? issue_slots_6_out_uop_fp_ctrl_sqrt : issue_slots_5_out_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_fp_ctrl_div = _T_171 ? issue_slots_6_out_uop_fp_ctrl_div : issue_slots_5_out_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_fp_ctrl_fma = _T_171 ? issue_slots_6_out_uop_fp_ctrl_fma : issue_slots_5_out_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_fp_ctrl_fastpipe = _T_171 ? issue_slots_6_out_uop_fp_ctrl_fastpipe : issue_slots_5_out_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_fp_ctrl_toint = _T_171 ? issue_slots_6_out_uop_fp_ctrl_toint : issue_slots_5_out_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_fp_ctrl_fromint = _T_171 ? issue_slots_6_out_uop_fp_ctrl_fromint : issue_slots_5_out_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_fp_ctrl_typeTagOut = _T_171 ? issue_slots_6_out_uop_fp_ctrl_typeTagOut : issue_slots_5_out_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_fp_ctrl_typeTagIn = _T_171 ? issue_slots_6_out_uop_fp_ctrl_typeTagIn : issue_slots_5_out_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_fp_ctrl_swap23 = _T_171 ? issue_slots_6_out_uop_fp_ctrl_swap23 : issue_slots_5_out_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_fp_ctrl_swap12 = _T_171 ? issue_slots_6_out_uop_fp_ctrl_swap12 : issue_slots_5_out_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_fp_ctrl_ren3 = _T_171 ? issue_slots_6_out_uop_fp_ctrl_ren3 : issue_slots_5_out_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_fp_ctrl_ren2 = _T_171 ? issue_slots_6_out_uop_fp_ctrl_ren2 : issue_slots_5_out_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_fp_ctrl_ren1 = _T_171 ? issue_slots_6_out_uop_fp_ctrl_ren1 : issue_slots_5_out_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_fp_ctrl_wen = _T_171 ? issue_slots_6_out_uop_fp_ctrl_wen : issue_slots_5_out_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_fp_ctrl_ldst = _T_171 ? issue_slots_6_out_uop_fp_ctrl_ldst : issue_slots_5_out_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_op2_sel = _T_171 ? issue_slots_6_out_uop_op2_sel : issue_slots_5_out_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_op1_sel = _T_171 ? issue_slots_6_out_uop_op1_sel : issue_slots_5_out_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_imm_packed = _T_171 ? issue_slots_6_out_uop_imm_packed : issue_slots_5_out_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_pimm = _T_171 ? issue_slots_6_out_uop_pimm : issue_slots_5_out_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_imm_sel = _T_171 ? issue_slots_6_out_uop_imm_sel : issue_slots_5_out_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_imm_rename = _T_171 ? issue_slots_6_out_uop_imm_rename : issue_slots_5_out_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_taken = _T_171 ? issue_slots_6_out_uop_taken : issue_slots_5_out_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_pc_lob = _T_171 ? issue_slots_6_out_uop_pc_lob : issue_slots_5_out_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_edge_inst = _T_171 ? issue_slots_6_out_uop_edge_inst : issue_slots_5_out_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_ftq_idx = _T_171 ? issue_slots_6_out_uop_ftq_idx : issue_slots_5_out_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_is_mov = _T_171 ? issue_slots_6_out_uop_is_mov : issue_slots_5_out_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_is_rocc = _T_171 ? issue_slots_6_out_uop_is_rocc : issue_slots_5_out_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_is_sys_pc2epc = _T_171 ? issue_slots_6_out_uop_is_sys_pc2epc : issue_slots_5_out_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_is_eret = _T_171 ? issue_slots_6_out_uop_is_eret : issue_slots_5_out_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_is_amo = _T_171 ? issue_slots_6_out_uop_is_amo : issue_slots_5_out_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_is_sfence = _T_171 ? issue_slots_6_out_uop_is_sfence : issue_slots_5_out_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_is_fencei = _T_171 ? issue_slots_6_out_uop_is_fencei : issue_slots_5_out_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_is_fence = _T_171 ? issue_slots_6_out_uop_is_fence : issue_slots_5_out_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_is_sfb = _T_171 ? issue_slots_6_out_uop_is_sfb : issue_slots_5_out_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_br_type = _T_171 ? issue_slots_6_out_uop_br_type : issue_slots_5_out_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_br_tag = _T_171 ? issue_slots_6_out_uop_br_tag : issue_slots_5_out_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_br_mask = _T_171 ? issue_slots_6_out_uop_br_mask : issue_slots_5_out_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_dis_col_sel = _T_171 ? issue_slots_6_out_uop_dis_col_sel : issue_slots_5_out_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_iw_p3_bypass_hint = _T_171 ? issue_slots_6_out_uop_iw_p3_bypass_hint : issue_slots_5_out_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_iw_p2_bypass_hint = _T_171 ? issue_slots_6_out_uop_iw_p2_bypass_hint : issue_slots_5_out_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_iw_p1_bypass_hint = _T_171 ? issue_slots_6_out_uop_iw_p1_bypass_hint : issue_slots_5_out_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_iw_p2_speculative_child = _T_171 ? issue_slots_6_out_uop_iw_p2_speculative_child : issue_slots_5_out_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_iw_p1_speculative_child = _T_171 ? issue_slots_6_out_uop_iw_p1_speculative_child : issue_slots_5_out_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_iw_issued = _T_171 ? issue_slots_6_out_uop_iw_issued : issue_slots_5_out_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_fu_code_0 = _T_171 ? issue_slots_6_out_uop_fu_code_0 : issue_slots_5_out_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_fu_code_1 = _T_171 ? issue_slots_6_out_uop_fu_code_1 : issue_slots_5_out_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_fu_code_2 = _T_171 ? issue_slots_6_out_uop_fu_code_2 : issue_slots_5_out_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_fu_code_3 = _T_171 ? issue_slots_6_out_uop_fu_code_3 : issue_slots_5_out_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_fu_code_4 = _T_171 ? issue_slots_6_out_uop_fu_code_4 : issue_slots_5_out_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_fu_code_5 = _T_171 ? issue_slots_6_out_uop_fu_code_5 : issue_slots_5_out_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_fu_code_6 = _T_171 ? issue_slots_6_out_uop_fu_code_6 : issue_slots_5_out_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_fu_code_7 = _T_171 ? issue_slots_6_out_uop_fu_code_7 : issue_slots_5_out_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_fu_code_8 = _T_171 ? issue_slots_6_out_uop_fu_code_8 : issue_slots_5_out_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_fu_code_9 = _T_171 ? issue_slots_6_out_uop_fu_code_9 : issue_slots_5_out_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_iq_type_0 = _T_171 ? issue_slots_6_out_uop_iq_type_0 : issue_slots_5_out_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_iq_type_1 = _T_171 ? issue_slots_6_out_uop_iq_type_1 : issue_slots_5_out_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_iq_type_2 = _T_171 ? issue_slots_6_out_uop_iq_type_2 : issue_slots_5_out_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_iq_type_3 = _T_171 ? issue_slots_6_out_uop_iq_type_3 : issue_slots_5_out_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_debug_pc = _T_171 ? issue_slots_6_out_uop_debug_pc : issue_slots_5_out_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_is_rvc = _T_171 ? issue_slots_6_out_uop_is_rvc : issue_slots_5_out_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_debug_inst = _T_171 ? issue_slots_6_out_uop_debug_inst : issue_slots_5_out_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_4_in_uop_bits_inst = _T_171 ? issue_slots_6_out_uop_inst : issue_slots_5_out_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign _issue_slots_4_clear_T = |shamts_oh_4;\t// @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49]\n assign issue_slots_4_clear = _issue_slots_4_clear_T;\t// @[issue-unit-age-ordered.scala:122:28, :199:49]\n wire _T_173 = shamts_oh_7 == 2'h2;\t// @[issue-unit-age-ordered.scala:158:23, :194:28]\n assign issue_slots_5_in_uop_valid = _T_173 ? issue_slots_7_will_be_valid : shamts_oh_6 == 2'h1 & issue_slots_6_will_be_valid;\t// @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37]\n assign issue_slots_5_in_uop_bits_debug_tsrc = _T_173 ? issue_slots_7_out_uop_debug_tsrc : issue_slots_6_out_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_debug_fsrc = _T_173 ? issue_slots_7_out_uop_debug_fsrc : issue_slots_6_out_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_bp_xcpt_if = _T_173 ? issue_slots_7_out_uop_bp_xcpt_if : issue_slots_6_out_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_bp_debug_if = _T_173 ? issue_slots_7_out_uop_bp_debug_if : issue_slots_6_out_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_xcpt_ma_if = _T_173 ? issue_slots_7_out_uop_xcpt_ma_if : issue_slots_6_out_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_xcpt_ae_if = _T_173 ? issue_slots_7_out_uop_xcpt_ae_if : issue_slots_6_out_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_xcpt_pf_if = _T_173 ? issue_slots_7_out_uop_xcpt_pf_if : issue_slots_6_out_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_fp_typ = _T_173 ? issue_slots_7_out_uop_fp_typ : issue_slots_6_out_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_fp_rm = _T_173 ? issue_slots_7_out_uop_fp_rm : issue_slots_6_out_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_fp_val = _T_173 ? issue_slots_7_out_uop_fp_val : issue_slots_6_out_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_fcn_op = _T_173 ? issue_slots_7_out_uop_fcn_op : issue_slots_6_out_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_fcn_dw = _T_173 ? issue_slots_7_out_uop_fcn_dw : issue_slots_6_out_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_frs3_en = _T_173 ? issue_slots_7_out_uop_frs3_en : issue_slots_6_out_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_lrs2_rtype = _T_173 ? issue_slots_7_out_uop_lrs2_rtype : issue_slots_6_out_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_lrs1_rtype = _T_173 ? issue_slots_7_out_uop_lrs1_rtype : issue_slots_6_out_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_dst_rtype = _T_173 ? issue_slots_7_out_uop_dst_rtype : issue_slots_6_out_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_lrs3 = _T_173 ? issue_slots_7_out_uop_lrs3 : issue_slots_6_out_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_lrs2 = _T_173 ? issue_slots_7_out_uop_lrs2 : issue_slots_6_out_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_lrs1 = _T_173 ? issue_slots_7_out_uop_lrs1 : issue_slots_6_out_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_ldst = _T_173 ? issue_slots_7_out_uop_ldst : issue_slots_6_out_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_ldst_is_rs1 = _T_173 ? issue_slots_7_out_uop_ldst_is_rs1 : issue_slots_6_out_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_csr_cmd = _T_173 ? issue_slots_7_out_uop_csr_cmd : issue_slots_6_out_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_flush_on_commit = _T_173 ? issue_slots_7_out_uop_flush_on_commit : issue_slots_6_out_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_is_unique = _T_173 ? issue_slots_7_out_uop_is_unique : issue_slots_6_out_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_uses_stq = _T_173 ? issue_slots_7_out_uop_uses_stq : issue_slots_6_out_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_uses_ldq = _T_173 ? issue_slots_7_out_uop_uses_ldq : issue_slots_6_out_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_mem_signed = _T_173 ? issue_slots_7_out_uop_mem_signed : issue_slots_6_out_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_mem_size = _T_173 ? issue_slots_7_out_uop_mem_size : issue_slots_6_out_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_mem_cmd = _T_173 ? issue_slots_7_out_uop_mem_cmd : issue_slots_6_out_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_exc_cause = _T_173 ? issue_slots_7_out_uop_exc_cause : issue_slots_6_out_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_exception = _T_173 ? issue_slots_7_out_uop_exception : issue_slots_6_out_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_stale_pdst = _T_173 ? issue_slots_7_out_uop_stale_pdst : issue_slots_6_out_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_ppred_busy = _T_173 ? issue_slots_7_out_uop_ppred_busy : issue_slots_6_out_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_prs3_busy = _T_173 ? issue_slots_7_out_uop_prs3_busy : issue_slots_6_out_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_prs2_busy = _T_173 ? issue_slots_7_out_uop_prs2_busy : issue_slots_6_out_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_prs1_busy = _T_173 ? issue_slots_7_out_uop_prs1_busy : issue_slots_6_out_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_ppred = _T_173 ? issue_slots_7_out_uop_ppred : issue_slots_6_out_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_prs3 = _T_173 ? issue_slots_7_out_uop_prs3 : issue_slots_6_out_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_prs2 = _T_173 ? issue_slots_7_out_uop_prs2 : issue_slots_6_out_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_prs1 = _T_173 ? issue_slots_7_out_uop_prs1 : issue_slots_6_out_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_pdst = _T_173 ? issue_slots_7_out_uop_pdst : issue_slots_6_out_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_rxq_idx = _T_173 ? issue_slots_7_out_uop_rxq_idx : issue_slots_6_out_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_stq_idx = _T_173 ? issue_slots_7_out_uop_stq_idx : issue_slots_6_out_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_ldq_idx = _T_173 ? issue_slots_7_out_uop_ldq_idx : issue_slots_6_out_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_rob_idx = _T_173 ? issue_slots_7_out_uop_rob_idx : issue_slots_6_out_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_fp_ctrl_vec = _T_173 ? issue_slots_7_out_uop_fp_ctrl_vec : issue_slots_6_out_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_fp_ctrl_wflags = _T_173 ? issue_slots_7_out_uop_fp_ctrl_wflags : issue_slots_6_out_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_fp_ctrl_sqrt = _T_173 ? issue_slots_7_out_uop_fp_ctrl_sqrt : issue_slots_6_out_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_fp_ctrl_div = _T_173 ? issue_slots_7_out_uop_fp_ctrl_div : issue_slots_6_out_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_fp_ctrl_fma = _T_173 ? issue_slots_7_out_uop_fp_ctrl_fma : issue_slots_6_out_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_fp_ctrl_fastpipe = _T_173 ? issue_slots_7_out_uop_fp_ctrl_fastpipe : issue_slots_6_out_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_fp_ctrl_toint = _T_173 ? issue_slots_7_out_uop_fp_ctrl_toint : issue_slots_6_out_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_fp_ctrl_fromint = _T_173 ? issue_slots_7_out_uop_fp_ctrl_fromint : issue_slots_6_out_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_fp_ctrl_typeTagOut = _T_173 ? issue_slots_7_out_uop_fp_ctrl_typeTagOut : issue_slots_6_out_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_fp_ctrl_typeTagIn = _T_173 ? issue_slots_7_out_uop_fp_ctrl_typeTagIn : issue_slots_6_out_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_fp_ctrl_swap23 = _T_173 ? issue_slots_7_out_uop_fp_ctrl_swap23 : issue_slots_6_out_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_fp_ctrl_swap12 = _T_173 ? issue_slots_7_out_uop_fp_ctrl_swap12 : issue_slots_6_out_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_fp_ctrl_ren3 = _T_173 ? issue_slots_7_out_uop_fp_ctrl_ren3 : issue_slots_6_out_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_fp_ctrl_ren2 = _T_173 ? issue_slots_7_out_uop_fp_ctrl_ren2 : issue_slots_6_out_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_fp_ctrl_ren1 = _T_173 ? issue_slots_7_out_uop_fp_ctrl_ren1 : issue_slots_6_out_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_fp_ctrl_wen = _T_173 ? issue_slots_7_out_uop_fp_ctrl_wen : issue_slots_6_out_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_fp_ctrl_ldst = _T_173 ? issue_slots_7_out_uop_fp_ctrl_ldst : issue_slots_6_out_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_op2_sel = _T_173 ? issue_slots_7_out_uop_op2_sel : issue_slots_6_out_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_op1_sel = _T_173 ? issue_slots_7_out_uop_op1_sel : issue_slots_6_out_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_imm_packed = _T_173 ? issue_slots_7_out_uop_imm_packed : issue_slots_6_out_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_pimm = _T_173 ? issue_slots_7_out_uop_pimm : issue_slots_6_out_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_imm_sel = _T_173 ? issue_slots_7_out_uop_imm_sel : issue_slots_6_out_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_imm_rename = _T_173 ? issue_slots_7_out_uop_imm_rename : issue_slots_6_out_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_taken = _T_173 ? issue_slots_7_out_uop_taken : issue_slots_6_out_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_pc_lob = _T_173 ? issue_slots_7_out_uop_pc_lob : issue_slots_6_out_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_edge_inst = _T_173 ? issue_slots_7_out_uop_edge_inst : issue_slots_6_out_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_ftq_idx = _T_173 ? issue_slots_7_out_uop_ftq_idx : issue_slots_6_out_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_is_mov = _T_173 ? issue_slots_7_out_uop_is_mov : issue_slots_6_out_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_is_rocc = _T_173 ? issue_slots_7_out_uop_is_rocc : issue_slots_6_out_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_is_sys_pc2epc = _T_173 ? issue_slots_7_out_uop_is_sys_pc2epc : issue_slots_6_out_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_is_eret = _T_173 ? issue_slots_7_out_uop_is_eret : issue_slots_6_out_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_is_amo = _T_173 ? issue_slots_7_out_uop_is_amo : issue_slots_6_out_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_is_sfence = _T_173 ? issue_slots_7_out_uop_is_sfence : issue_slots_6_out_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_is_fencei = _T_173 ? issue_slots_7_out_uop_is_fencei : issue_slots_6_out_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_is_fence = _T_173 ? issue_slots_7_out_uop_is_fence : issue_slots_6_out_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_is_sfb = _T_173 ? issue_slots_7_out_uop_is_sfb : issue_slots_6_out_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_br_type = _T_173 ? issue_slots_7_out_uop_br_type : issue_slots_6_out_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_br_tag = _T_173 ? issue_slots_7_out_uop_br_tag : issue_slots_6_out_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_br_mask = _T_173 ? issue_slots_7_out_uop_br_mask : issue_slots_6_out_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_dis_col_sel = _T_173 ? issue_slots_7_out_uop_dis_col_sel : issue_slots_6_out_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_iw_p3_bypass_hint = _T_173 ? issue_slots_7_out_uop_iw_p3_bypass_hint : issue_slots_6_out_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_iw_p2_bypass_hint = _T_173 ? issue_slots_7_out_uop_iw_p2_bypass_hint : issue_slots_6_out_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_iw_p1_bypass_hint = _T_173 ? issue_slots_7_out_uop_iw_p1_bypass_hint : issue_slots_6_out_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_iw_p2_speculative_child = _T_173 ? issue_slots_7_out_uop_iw_p2_speculative_child : issue_slots_6_out_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_iw_p1_speculative_child = _T_173 ? issue_slots_7_out_uop_iw_p1_speculative_child : issue_slots_6_out_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_iw_issued = _T_173 ? issue_slots_7_out_uop_iw_issued : issue_slots_6_out_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_fu_code_0 = _T_173 ? issue_slots_7_out_uop_fu_code_0 : issue_slots_6_out_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_fu_code_1 = _T_173 ? issue_slots_7_out_uop_fu_code_1 : issue_slots_6_out_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_fu_code_2 = _T_173 ? issue_slots_7_out_uop_fu_code_2 : issue_slots_6_out_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_fu_code_3 = _T_173 ? issue_slots_7_out_uop_fu_code_3 : issue_slots_6_out_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_fu_code_4 = _T_173 ? issue_slots_7_out_uop_fu_code_4 : issue_slots_6_out_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_fu_code_5 = _T_173 ? issue_slots_7_out_uop_fu_code_5 : issue_slots_6_out_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_fu_code_6 = _T_173 ? issue_slots_7_out_uop_fu_code_6 : issue_slots_6_out_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_fu_code_7 = _T_173 ? issue_slots_7_out_uop_fu_code_7 : issue_slots_6_out_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_fu_code_8 = _T_173 ? issue_slots_7_out_uop_fu_code_8 : issue_slots_6_out_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_fu_code_9 = _T_173 ? issue_slots_7_out_uop_fu_code_9 : issue_slots_6_out_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_iq_type_0 = _T_173 ? issue_slots_7_out_uop_iq_type_0 : issue_slots_6_out_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_iq_type_1 = _T_173 ? issue_slots_7_out_uop_iq_type_1 : issue_slots_6_out_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_iq_type_2 = _T_173 ? issue_slots_7_out_uop_iq_type_2 : issue_slots_6_out_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_iq_type_3 = _T_173 ? issue_slots_7_out_uop_iq_type_3 : issue_slots_6_out_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_debug_pc = _T_173 ? issue_slots_7_out_uop_debug_pc : issue_slots_6_out_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_is_rvc = _T_173 ? issue_slots_7_out_uop_is_rvc : issue_slots_6_out_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_debug_inst = _T_173 ? issue_slots_7_out_uop_debug_inst : issue_slots_6_out_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_5_in_uop_bits_inst = _T_173 ? issue_slots_7_out_uop_inst : issue_slots_6_out_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign _issue_slots_5_clear_T = |shamts_oh_5;\t// @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49]\n assign issue_slots_5_clear = _issue_slots_5_clear_T;\t// @[issue-unit-age-ordered.scala:122:28, :199:49]\n wire _T_175 = shamts_oh_8 == 2'h2;\t// @[issue-unit-age-ordered.scala:158:23, :194:28]\n assign issue_slots_6_in_uop_valid = _T_175 ? issue_slots_8_will_be_valid : shamts_oh_7 == 2'h1 & issue_slots_7_will_be_valid;\t// @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37]\n assign issue_slots_6_in_uop_bits_debug_tsrc = _T_175 ? issue_slots_8_out_uop_debug_tsrc : issue_slots_7_out_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_debug_fsrc = _T_175 ? issue_slots_8_out_uop_debug_fsrc : issue_slots_7_out_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_bp_xcpt_if = _T_175 ? issue_slots_8_out_uop_bp_xcpt_if : issue_slots_7_out_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_bp_debug_if = _T_175 ? issue_slots_8_out_uop_bp_debug_if : issue_slots_7_out_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_xcpt_ma_if = _T_175 ? issue_slots_8_out_uop_xcpt_ma_if : issue_slots_7_out_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_xcpt_ae_if = _T_175 ? issue_slots_8_out_uop_xcpt_ae_if : issue_slots_7_out_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_xcpt_pf_if = _T_175 ? issue_slots_8_out_uop_xcpt_pf_if : issue_slots_7_out_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_fp_typ = _T_175 ? issue_slots_8_out_uop_fp_typ : issue_slots_7_out_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_fp_rm = _T_175 ? issue_slots_8_out_uop_fp_rm : issue_slots_7_out_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_fp_val = _T_175 ? issue_slots_8_out_uop_fp_val : issue_slots_7_out_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_fcn_op = _T_175 ? issue_slots_8_out_uop_fcn_op : issue_slots_7_out_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_fcn_dw = _T_175 ? issue_slots_8_out_uop_fcn_dw : issue_slots_7_out_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_frs3_en = _T_175 ? issue_slots_8_out_uop_frs3_en : issue_slots_7_out_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_lrs2_rtype = _T_175 ? issue_slots_8_out_uop_lrs2_rtype : issue_slots_7_out_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_lrs1_rtype = _T_175 ? issue_slots_8_out_uop_lrs1_rtype : issue_slots_7_out_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_dst_rtype = _T_175 ? issue_slots_8_out_uop_dst_rtype : issue_slots_7_out_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_lrs3 = _T_175 ? issue_slots_8_out_uop_lrs3 : issue_slots_7_out_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_lrs2 = _T_175 ? issue_slots_8_out_uop_lrs2 : issue_slots_7_out_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_lrs1 = _T_175 ? issue_slots_8_out_uop_lrs1 : issue_slots_7_out_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_ldst = _T_175 ? issue_slots_8_out_uop_ldst : issue_slots_7_out_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_ldst_is_rs1 = _T_175 ? issue_slots_8_out_uop_ldst_is_rs1 : issue_slots_7_out_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_csr_cmd = _T_175 ? issue_slots_8_out_uop_csr_cmd : issue_slots_7_out_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_flush_on_commit = _T_175 ? issue_slots_8_out_uop_flush_on_commit : issue_slots_7_out_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_is_unique = _T_175 ? issue_slots_8_out_uop_is_unique : issue_slots_7_out_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_uses_stq = _T_175 ? issue_slots_8_out_uop_uses_stq : issue_slots_7_out_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_uses_ldq = _T_175 ? issue_slots_8_out_uop_uses_ldq : issue_slots_7_out_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_mem_signed = _T_175 ? issue_slots_8_out_uop_mem_signed : issue_slots_7_out_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_mem_size = _T_175 ? issue_slots_8_out_uop_mem_size : issue_slots_7_out_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_mem_cmd = _T_175 ? issue_slots_8_out_uop_mem_cmd : issue_slots_7_out_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_exc_cause = _T_175 ? issue_slots_8_out_uop_exc_cause : issue_slots_7_out_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_exception = _T_175 ? issue_slots_8_out_uop_exception : issue_slots_7_out_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_stale_pdst = _T_175 ? issue_slots_8_out_uop_stale_pdst : issue_slots_7_out_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_ppred_busy = _T_175 ? issue_slots_8_out_uop_ppred_busy : issue_slots_7_out_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_prs3_busy = _T_175 ? issue_slots_8_out_uop_prs3_busy : issue_slots_7_out_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_prs2_busy = _T_175 ? issue_slots_8_out_uop_prs2_busy : issue_slots_7_out_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_prs1_busy = _T_175 ? issue_slots_8_out_uop_prs1_busy : issue_slots_7_out_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_ppred = _T_175 ? issue_slots_8_out_uop_ppred : issue_slots_7_out_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_prs3 = _T_175 ? issue_slots_8_out_uop_prs3 : issue_slots_7_out_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_prs2 = _T_175 ? issue_slots_8_out_uop_prs2 : issue_slots_7_out_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_prs1 = _T_175 ? issue_slots_8_out_uop_prs1 : issue_slots_7_out_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_pdst = _T_175 ? issue_slots_8_out_uop_pdst : issue_slots_7_out_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_rxq_idx = _T_175 ? issue_slots_8_out_uop_rxq_idx : issue_slots_7_out_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_stq_idx = _T_175 ? issue_slots_8_out_uop_stq_idx : issue_slots_7_out_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_ldq_idx = _T_175 ? issue_slots_8_out_uop_ldq_idx : issue_slots_7_out_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_rob_idx = _T_175 ? issue_slots_8_out_uop_rob_idx : issue_slots_7_out_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_fp_ctrl_vec = _T_175 ? issue_slots_8_out_uop_fp_ctrl_vec : issue_slots_7_out_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_fp_ctrl_wflags = _T_175 ? issue_slots_8_out_uop_fp_ctrl_wflags : issue_slots_7_out_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_fp_ctrl_sqrt = _T_175 ? issue_slots_8_out_uop_fp_ctrl_sqrt : issue_slots_7_out_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_fp_ctrl_div = _T_175 ? issue_slots_8_out_uop_fp_ctrl_div : issue_slots_7_out_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_fp_ctrl_fma = _T_175 ? issue_slots_8_out_uop_fp_ctrl_fma : issue_slots_7_out_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_fp_ctrl_fastpipe = _T_175 ? issue_slots_8_out_uop_fp_ctrl_fastpipe : issue_slots_7_out_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_fp_ctrl_toint = _T_175 ? issue_slots_8_out_uop_fp_ctrl_toint : issue_slots_7_out_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_fp_ctrl_fromint = _T_175 ? issue_slots_8_out_uop_fp_ctrl_fromint : issue_slots_7_out_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_fp_ctrl_typeTagOut = _T_175 ? issue_slots_8_out_uop_fp_ctrl_typeTagOut : issue_slots_7_out_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_fp_ctrl_typeTagIn = _T_175 ? issue_slots_8_out_uop_fp_ctrl_typeTagIn : issue_slots_7_out_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_fp_ctrl_swap23 = _T_175 ? issue_slots_8_out_uop_fp_ctrl_swap23 : issue_slots_7_out_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_fp_ctrl_swap12 = _T_175 ? issue_slots_8_out_uop_fp_ctrl_swap12 : issue_slots_7_out_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_fp_ctrl_ren3 = _T_175 ? issue_slots_8_out_uop_fp_ctrl_ren3 : issue_slots_7_out_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_fp_ctrl_ren2 = _T_175 ? issue_slots_8_out_uop_fp_ctrl_ren2 : issue_slots_7_out_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_fp_ctrl_ren1 = _T_175 ? issue_slots_8_out_uop_fp_ctrl_ren1 : issue_slots_7_out_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_fp_ctrl_wen = _T_175 ? issue_slots_8_out_uop_fp_ctrl_wen : issue_slots_7_out_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_fp_ctrl_ldst = _T_175 ? issue_slots_8_out_uop_fp_ctrl_ldst : issue_slots_7_out_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_op2_sel = _T_175 ? issue_slots_8_out_uop_op2_sel : issue_slots_7_out_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_op1_sel = _T_175 ? issue_slots_8_out_uop_op1_sel : issue_slots_7_out_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_imm_packed = _T_175 ? issue_slots_8_out_uop_imm_packed : issue_slots_7_out_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_pimm = _T_175 ? issue_slots_8_out_uop_pimm : issue_slots_7_out_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_imm_sel = _T_175 ? issue_slots_8_out_uop_imm_sel : issue_slots_7_out_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_imm_rename = _T_175 ? issue_slots_8_out_uop_imm_rename : issue_slots_7_out_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_taken = _T_175 ? issue_slots_8_out_uop_taken : issue_slots_7_out_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_pc_lob = _T_175 ? issue_slots_8_out_uop_pc_lob : issue_slots_7_out_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_edge_inst = _T_175 ? issue_slots_8_out_uop_edge_inst : issue_slots_7_out_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_ftq_idx = _T_175 ? issue_slots_8_out_uop_ftq_idx : issue_slots_7_out_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_is_mov = _T_175 ? issue_slots_8_out_uop_is_mov : issue_slots_7_out_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_is_rocc = _T_175 ? issue_slots_8_out_uop_is_rocc : issue_slots_7_out_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_is_sys_pc2epc = _T_175 ? issue_slots_8_out_uop_is_sys_pc2epc : issue_slots_7_out_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_is_eret = _T_175 ? issue_slots_8_out_uop_is_eret : issue_slots_7_out_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_is_amo = _T_175 ? issue_slots_8_out_uop_is_amo : issue_slots_7_out_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_is_sfence = _T_175 ? issue_slots_8_out_uop_is_sfence : issue_slots_7_out_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_is_fencei = _T_175 ? issue_slots_8_out_uop_is_fencei : issue_slots_7_out_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_is_fence = _T_175 ? issue_slots_8_out_uop_is_fence : issue_slots_7_out_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_is_sfb = _T_175 ? issue_slots_8_out_uop_is_sfb : issue_slots_7_out_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_br_type = _T_175 ? issue_slots_8_out_uop_br_type : issue_slots_7_out_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_br_tag = _T_175 ? issue_slots_8_out_uop_br_tag : issue_slots_7_out_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_br_mask = _T_175 ? issue_slots_8_out_uop_br_mask : issue_slots_7_out_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_dis_col_sel = _T_175 ? issue_slots_8_out_uop_dis_col_sel : issue_slots_7_out_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_iw_p3_bypass_hint = _T_175 ? issue_slots_8_out_uop_iw_p3_bypass_hint : issue_slots_7_out_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_iw_p2_bypass_hint = _T_175 ? issue_slots_8_out_uop_iw_p2_bypass_hint : issue_slots_7_out_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_iw_p1_bypass_hint = _T_175 ? issue_slots_8_out_uop_iw_p1_bypass_hint : issue_slots_7_out_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_iw_p2_speculative_child = _T_175 ? issue_slots_8_out_uop_iw_p2_speculative_child : issue_slots_7_out_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_iw_p1_speculative_child = _T_175 ? issue_slots_8_out_uop_iw_p1_speculative_child : issue_slots_7_out_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_iw_issued = _T_175 ? issue_slots_8_out_uop_iw_issued : issue_slots_7_out_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_fu_code_0 = _T_175 ? issue_slots_8_out_uop_fu_code_0 : issue_slots_7_out_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_fu_code_1 = _T_175 ? issue_slots_8_out_uop_fu_code_1 : issue_slots_7_out_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_fu_code_2 = _T_175 ? issue_slots_8_out_uop_fu_code_2 : issue_slots_7_out_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_fu_code_3 = _T_175 ? issue_slots_8_out_uop_fu_code_3 : issue_slots_7_out_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_fu_code_4 = _T_175 ? issue_slots_8_out_uop_fu_code_4 : issue_slots_7_out_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_fu_code_5 = _T_175 ? issue_slots_8_out_uop_fu_code_5 : issue_slots_7_out_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_fu_code_6 = _T_175 ? issue_slots_8_out_uop_fu_code_6 : issue_slots_7_out_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_fu_code_7 = _T_175 ? issue_slots_8_out_uop_fu_code_7 : issue_slots_7_out_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_fu_code_8 = _T_175 ? issue_slots_8_out_uop_fu_code_8 : issue_slots_7_out_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_fu_code_9 = _T_175 ? issue_slots_8_out_uop_fu_code_9 : issue_slots_7_out_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_iq_type_0 = _T_175 ? issue_slots_8_out_uop_iq_type_0 : issue_slots_7_out_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_iq_type_1 = _T_175 ? issue_slots_8_out_uop_iq_type_1 : issue_slots_7_out_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_iq_type_2 = _T_175 ? issue_slots_8_out_uop_iq_type_2 : issue_slots_7_out_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_iq_type_3 = _T_175 ? issue_slots_8_out_uop_iq_type_3 : issue_slots_7_out_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_debug_pc = _T_175 ? issue_slots_8_out_uop_debug_pc : issue_slots_7_out_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_is_rvc = _T_175 ? issue_slots_8_out_uop_is_rvc : issue_slots_7_out_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_debug_inst = _T_175 ? issue_slots_8_out_uop_debug_inst : issue_slots_7_out_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_6_in_uop_bits_inst = _T_175 ? issue_slots_8_out_uop_inst : issue_slots_7_out_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign _issue_slots_6_clear_T = |shamts_oh_6;\t// @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49]\n assign issue_slots_6_clear = _issue_slots_6_clear_T;\t// @[issue-unit-age-ordered.scala:122:28, :199:49]\n wire _T_177 = shamts_oh_9 == 2'h2;\t// @[issue-unit-age-ordered.scala:158:23, :194:28]\n assign issue_slots_7_in_uop_valid = _T_177 ? issue_slots_9_will_be_valid : shamts_oh_8 == 2'h1 & issue_slots_8_will_be_valid;\t// @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37]\n assign issue_slots_7_in_uop_bits_debug_tsrc = _T_177 ? issue_slots_9_out_uop_debug_tsrc : issue_slots_8_out_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_debug_fsrc = _T_177 ? issue_slots_9_out_uop_debug_fsrc : issue_slots_8_out_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_bp_xcpt_if = _T_177 ? issue_slots_9_out_uop_bp_xcpt_if : issue_slots_8_out_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_bp_debug_if = _T_177 ? issue_slots_9_out_uop_bp_debug_if : issue_slots_8_out_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_xcpt_ma_if = _T_177 ? issue_slots_9_out_uop_xcpt_ma_if : issue_slots_8_out_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_xcpt_ae_if = _T_177 ? issue_slots_9_out_uop_xcpt_ae_if : issue_slots_8_out_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_xcpt_pf_if = _T_177 ? issue_slots_9_out_uop_xcpt_pf_if : issue_slots_8_out_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_fp_typ = _T_177 ? issue_slots_9_out_uop_fp_typ : issue_slots_8_out_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_fp_rm = _T_177 ? issue_slots_9_out_uop_fp_rm : issue_slots_8_out_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_fp_val = _T_177 ? issue_slots_9_out_uop_fp_val : issue_slots_8_out_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_fcn_op = _T_177 ? issue_slots_9_out_uop_fcn_op : issue_slots_8_out_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_fcn_dw = _T_177 ? issue_slots_9_out_uop_fcn_dw : issue_slots_8_out_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_frs3_en = _T_177 ? issue_slots_9_out_uop_frs3_en : issue_slots_8_out_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_lrs2_rtype = _T_177 ? issue_slots_9_out_uop_lrs2_rtype : issue_slots_8_out_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_lrs1_rtype = _T_177 ? issue_slots_9_out_uop_lrs1_rtype : issue_slots_8_out_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_dst_rtype = _T_177 ? issue_slots_9_out_uop_dst_rtype : issue_slots_8_out_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_lrs3 = _T_177 ? issue_slots_9_out_uop_lrs3 : issue_slots_8_out_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_lrs2 = _T_177 ? issue_slots_9_out_uop_lrs2 : issue_slots_8_out_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_lrs1 = _T_177 ? issue_slots_9_out_uop_lrs1 : issue_slots_8_out_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_ldst = _T_177 ? issue_slots_9_out_uop_ldst : issue_slots_8_out_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_ldst_is_rs1 = _T_177 ? issue_slots_9_out_uop_ldst_is_rs1 : issue_slots_8_out_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_csr_cmd = _T_177 ? issue_slots_9_out_uop_csr_cmd : issue_slots_8_out_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_flush_on_commit = _T_177 ? issue_slots_9_out_uop_flush_on_commit : issue_slots_8_out_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_is_unique = _T_177 ? issue_slots_9_out_uop_is_unique : issue_slots_8_out_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_uses_stq = _T_177 ? issue_slots_9_out_uop_uses_stq : issue_slots_8_out_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_uses_ldq = _T_177 ? issue_slots_9_out_uop_uses_ldq : issue_slots_8_out_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_mem_signed = _T_177 ? issue_slots_9_out_uop_mem_signed : issue_slots_8_out_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_mem_size = _T_177 ? issue_slots_9_out_uop_mem_size : issue_slots_8_out_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_mem_cmd = _T_177 ? issue_slots_9_out_uop_mem_cmd : issue_slots_8_out_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_exc_cause = _T_177 ? issue_slots_9_out_uop_exc_cause : issue_slots_8_out_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_exception = _T_177 ? issue_slots_9_out_uop_exception : issue_slots_8_out_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_stale_pdst = _T_177 ? issue_slots_9_out_uop_stale_pdst : issue_slots_8_out_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_ppred_busy = _T_177 ? issue_slots_9_out_uop_ppred_busy : issue_slots_8_out_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_prs3_busy = _T_177 ? issue_slots_9_out_uop_prs3_busy : issue_slots_8_out_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_prs2_busy = _T_177 ? issue_slots_9_out_uop_prs2_busy : issue_slots_8_out_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_prs1_busy = _T_177 ? issue_slots_9_out_uop_prs1_busy : issue_slots_8_out_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_ppred = _T_177 ? issue_slots_9_out_uop_ppred : issue_slots_8_out_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_prs3 = _T_177 ? issue_slots_9_out_uop_prs3 : issue_slots_8_out_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_prs2 = _T_177 ? issue_slots_9_out_uop_prs2 : issue_slots_8_out_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_prs1 = _T_177 ? issue_slots_9_out_uop_prs1 : issue_slots_8_out_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_pdst = _T_177 ? issue_slots_9_out_uop_pdst : issue_slots_8_out_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_rxq_idx = _T_177 ? issue_slots_9_out_uop_rxq_idx : issue_slots_8_out_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_stq_idx = _T_177 ? issue_slots_9_out_uop_stq_idx : issue_slots_8_out_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_ldq_idx = _T_177 ? issue_slots_9_out_uop_ldq_idx : issue_slots_8_out_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_rob_idx = _T_177 ? issue_slots_9_out_uop_rob_idx : issue_slots_8_out_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_fp_ctrl_vec = _T_177 ? issue_slots_9_out_uop_fp_ctrl_vec : issue_slots_8_out_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_fp_ctrl_wflags = _T_177 ? issue_slots_9_out_uop_fp_ctrl_wflags : issue_slots_8_out_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_fp_ctrl_sqrt = _T_177 ? issue_slots_9_out_uop_fp_ctrl_sqrt : issue_slots_8_out_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_fp_ctrl_div = _T_177 ? issue_slots_9_out_uop_fp_ctrl_div : issue_slots_8_out_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_fp_ctrl_fma = _T_177 ? issue_slots_9_out_uop_fp_ctrl_fma : issue_slots_8_out_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_fp_ctrl_fastpipe = _T_177 ? issue_slots_9_out_uop_fp_ctrl_fastpipe : issue_slots_8_out_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_fp_ctrl_toint = _T_177 ? issue_slots_9_out_uop_fp_ctrl_toint : issue_slots_8_out_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_fp_ctrl_fromint = _T_177 ? issue_slots_9_out_uop_fp_ctrl_fromint : issue_slots_8_out_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_fp_ctrl_typeTagOut = _T_177 ? issue_slots_9_out_uop_fp_ctrl_typeTagOut : issue_slots_8_out_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_fp_ctrl_typeTagIn = _T_177 ? issue_slots_9_out_uop_fp_ctrl_typeTagIn : issue_slots_8_out_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_fp_ctrl_swap23 = _T_177 ? issue_slots_9_out_uop_fp_ctrl_swap23 : issue_slots_8_out_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_fp_ctrl_swap12 = _T_177 ? issue_slots_9_out_uop_fp_ctrl_swap12 : issue_slots_8_out_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_fp_ctrl_ren3 = _T_177 ? issue_slots_9_out_uop_fp_ctrl_ren3 : issue_slots_8_out_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_fp_ctrl_ren2 = _T_177 ? issue_slots_9_out_uop_fp_ctrl_ren2 : issue_slots_8_out_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_fp_ctrl_ren1 = _T_177 ? issue_slots_9_out_uop_fp_ctrl_ren1 : issue_slots_8_out_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_fp_ctrl_wen = _T_177 ? issue_slots_9_out_uop_fp_ctrl_wen : issue_slots_8_out_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_fp_ctrl_ldst = _T_177 ? issue_slots_9_out_uop_fp_ctrl_ldst : issue_slots_8_out_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_op2_sel = _T_177 ? issue_slots_9_out_uop_op2_sel : issue_slots_8_out_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_op1_sel = _T_177 ? issue_slots_9_out_uop_op1_sel : issue_slots_8_out_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_imm_packed = _T_177 ? issue_slots_9_out_uop_imm_packed : issue_slots_8_out_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_pimm = _T_177 ? issue_slots_9_out_uop_pimm : issue_slots_8_out_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_imm_sel = _T_177 ? issue_slots_9_out_uop_imm_sel : issue_slots_8_out_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_imm_rename = _T_177 ? issue_slots_9_out_uop_imm_rename : issue_slots_8_out_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_taken = _T_177 ? issue_slots_9_out_uop_taken : issue_slots_8_out_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_pc_lob = _T_177 ? issue_slots_9_out_uop_pc_lob : issue_slots_8_out_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_edge_inst = _T_177 ? issue_slots_9_out_uop_edge_inst : issue_slots_8_out_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_ftq_idx = _T_177 ? issue_slots_9_out_uop_ftq_idx : issue_slots_8_out_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_is_mov = _T_177 ? issue_slots_9_out_uop_is_mov : issue_slots_8_out_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_is_rocc = _T_177 ? issue_slots_9_out_uop_is_rocc : issue_slots_8_out_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_is_sys_pc2epc = _T_177 ? issue_slots_9_out_uop_is_sys_pc2epc : issue_slots_8_out_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_is_eret = _T_177 ? issue_slots_9_out_uop_is_eret : issue_slots_8_out_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_is_amo = _T_177 ? issue_slots_9_out_uop_is_amo : issue_slots_8_out_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_is_sfence = _T_177 ? issue_slots_9_out_uop_is_sfence : issue_slots_8_out_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_is_fencei = _T_177 ? issue_slots_9_out_uop_is_fencei : issue_slots_8_out_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_is_fence = _T_177 ? issue_slots_9_out_uop_is_fence : issue_slots_8_out_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_is_sfb = _T_177 ? issue_slots_9_out_uop_is_sfb : issue_slots_8_out_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_br_type = _T_177 ? issue_slots_9_out_uop_br_type : issue_slots_8_out_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_br_tag = _T_177 ? issue_slots_9_out_uop_br_tag : issue_slots_8_out_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_br_mask = _T_177 ? issue_slots_9_out_uop_br_mask : issue_slots_8_out_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_dis_col_sel = _T_177 ? issue_slots_9_out_uop_dis_col_sel : issue_slots_8_out_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_iw_p3_bypass_hint = _T_177 ? issue_slots_9_out_uop_iw_p3_bypass_hint : issue_slots_8_out_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_iw_p2_bypass_hint = _T_177 ? issue_slots_9_out_uop_iw_p2_bypass_hint : issue_slots_8_out_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_iw_p1_bypass_hint = _T_177 ? issue_slots_9_out_uop_iw_p1_bypass_hint : issue_slots_8_out_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_iw_p2_speculative_child = _T_177 ? issue_slots_9_out_uop_iw_p2_speculative_child : issue_slots_8_out_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_iw_p1_speculative_child = _T_177 ? issue_slots_9_out_uop_iw_p1_speculative_child : issue_slots_8_out_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_iw_issued = _T_177 ? issue_slots_9_out_uop_iw_issued : issue_slots_8_out_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_fu_code_0 = _T_177 ? issue_slots_9_out_uop_fu_code_0 : issue_slots_8_out_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_fu_code_1 = _T_177 ? issue_slots_9_out_uop_fu_code_1 : issue_slots_8_out_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_fu_code_2 = _T_177 ? issue_slots_9_out_uop_fu_code_2 : issue_slots_8_out_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_fu_code_3 = _T_177 ? issue_slots_9_out_uop_fu_code_3 : issue_slots_8_out_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_fu_code_4 = _T_177 ? issue_slots_9_out_uop_fu_code_4 : issue_slots_8_out_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_fu_code_5 = _T_177 ? issue_slots_9_out_uop_fu_code_5 : issue_slots_8_out_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_fu_code_6 = _T_177 ? issue_slots_9_out_uop_fu_code_6 : issue_slots_8_out_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_fu_code_7 = _T_177 ? issue_slots_9_out_uop_fu_code_7 : issue_slots_8_out_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_fu_code_8 = _T_177 ? issue_slots_9_out_uop_fu_code_8 : issue_slots_8_out_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_fu_code_9 = _T_177 ? issue_slots_9_out_uop_fu_code_9 : issue_slots_8_out_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_iq_type_0 = _T_177 ? issue_slots_9_out_uop_iq_type_0 : issue_slots_8_out_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_iq_type_1 = _T_177 ? issue_slots_9_out_uop_iq_type_1 : issue_slots_8_out_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_iq_type_2 = _T_177 ? issue_slots_9_out_uop_iq_type_2 : issue_slots_8_out_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_iq_type_3 = _T_177 ? issue_slots_9_out_uop_iq_type_3 : issue_slots_8_out_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_debug_pc = _T_177 ? issue_slots_9_out_uop_debug_pc : issue_slots_8_out_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_is_rvc = _T_177 ? issue_slots_9_out_uop_is_rvc : issue_slots_8_out_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_debug_inst = _T_177 ? issue_slots_9_out_uop_debug_inst : issue_slots_8_out_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_7_in_uop_bits_inst = _T_177 ? issue_slots_9_out_uop_inst : issue_slots_8_out_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign _issue_slots_7_clear_T = |shamts_oh_7;\t// @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49]\n assign issue_slots_7_clear = _issue_slots_7_clear_T;\t// @[issue-unit-age-ordered.scala:122:28, :199:49]\n wire _T_179 = shamts_oh_10 == 2'h2;\t// @[issue-unit-age-ordered.scala:158:23, :194:28]\n assign issue_slots_8_in_uop_valid = _T_179 ? issue_slots_10_will_be_valid : shamts_oh_9 == 2'h1 & issue_slots_9_will_be_valid;\t// @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37]\n assign issue_slots_8_in_uop_bits_debug_tsrc = _T_179 ? issue_slots_10_out_uop_debug_tsrc : issue_slots_9_out_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_debug_fsrc = _T_179 ? issue_slots_10_out_uop_debug_fsrc : issue_slots_9_out_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_bp_xcpt_if = _T_179 ? issue_slots_10_out_uop_bp_xcpt_if : issue_slots_9_out_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_bp_debug_if = _T_179 ? issue_slots_10_out_uop_bp_debug_if : issue_slots_9_out_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_xcpt_ma_if = _T_179 ? issue_slots_10_out_uop_xcpt_ma_if : issue_slots_9_out_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_xcpt_ae_if = _T_179 ? issue_slots_10_out_uop_xcpt_ae_if : issue_slots_9_out_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_xcpt_pf_if = _T_179 ? issue_slots_10_out_uop_xcpt_pf_if : issue_slots_9_out_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_fp_typ = _T_179 ? issue_slots_10_out_uop_fp_typ : issue_slots_9_out_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_fp_rm = _T_179 ? issue_slots_10_out_uop_fp_rm : issue_slots_9_out_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_fp_val = _T_179 ? issue_slots_10_out_uop_fp_val : issue_slots_9_out_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_fcn_op = _T_179 ? issue_slots_10_out_uop_fcn_op : issue_slots_9_out_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_fcn_dw = _T_179 ? issue_slots_10_out_uop_fcn_dw : issue_slots_9_out_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_frs3_en = _T_179 ? issue_slots_10_out_uop_frs3_en : issue_slots_9_out_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_lrs2_rtype = _T_179 ? issue_slots_10_out_uop_lrs2_rtype : issue_slots_9_out_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_lrs1_rtype = _T_179 ? issue_slots_10_out_uop_lrs1_rtype : issue_slots_9_out_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_dst_rtype = _T_179 ? issue_slots_10_out_uop_dst_rtype : issue_slots_9_out_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_lrs3 = _T_179 ? issue_slots_10_out_uop_lrs3 : issue_slots_9_out_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_lrs2 = _T_179 ? issue_slots_10_out_uop_lrs2 : issue_slots_9_out_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_lrs1 = _T_179 ? issue_slots_10_out_uop_lrs1 : issue_slots_9_out_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_ldst = _T_179 ? issue_slots_10_out_uop_ldst : issue_slots_9_out_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_ldst_is_rs1 = _T_179 ? issue_slots_10_out_uop_ldst_is_rs1 : issue_slots_9_out_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_csr_cmd = _T_179 ? issue_slots_10_out_uop_csr_cmd : issue_slots_9_out_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_flush_on_commit = _T_179 ? issue_slots_10_out_uop_flush_on_commit : issue_slots_9_out_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_is_unique = _T_179 ? issue_slots_10_out_uop_is_unique : issue_slots_9_out_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_uses_stq = _T_179 ? issue_slots_10_out_uop_uses_stq : issue_slots_9_out_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_uses_ldq = _T_179 ? issue_slots_10_out_uop_uses_ldq : issue_slots_9_out_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_mem_signed = _T_179 ? issue_slots_10_out_uop_mem_signed : issue_slots_9_out_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_mem_size = _T_179 ? issue_slots_10_out_uop_mem_size : issue_slots_9_out_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_mem_cmd = _T_179 ? issue_slots_10_out_uop_mem_cmd : issue_slots_9_out_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_exc_cause = _T_179 ? issue_slots_10_out_uop_exc_cause : issue_slots_9_out_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_exception = _T_179 ? issue_slots_10_out_uop_exception : issue_slots_9_out_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_stale_pdst = _T_179 ? issue_slots_10_out_uop_stale_pdst : issue_slots_9_out_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_ppred_busy = _T_179 ? issue_slots_10_out_uop_ppred_busy : issue_slots_9_out_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_prs3_busy = _T_179 ? issue_slots_10_out_uop_prs3_busy : issue_slots_9_out_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_prs2_busy = _T_179 ? issue_slots_10_out_uop_prs2_busy : issue_slots_9_out_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_prs1_busy = _T_179 ? issue_slots_10_out_uop_prs1_busy : issue_slots_9_out_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_ppred = _T_179 ? issue_slots_10_out_uop_ppred : issue_slots_9_out_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_prs3 = _T_179 ? issue_slots_10_out_uop_prs3 : issue_slots_9_out_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_prs2 = _T_179 ? issue_slots_10_out_uop_prs2 : issue_slots_9_out_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_prs1 = _T_179 ? issue_slots_10_out_uop_prs1 : issue_slots_9_out_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_pdst = _T_179 ? issue_slots_10_out_uop_pdst : issue_slots_9_out_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_rxq_idx = _T_179 ? issue_slots_10_out_uop_rxq_idx : issue_slots_9_out_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_stq_idx = _T_179 ? issue_slots_10_out_uop_stq_idx : issue_slots_9_out_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_ldq_idx = _T_179 ? issue_slots_10_out_uop_ldq_idx : issue_slots_9_out_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_rob_idx = _T_179 ? issue_slots_10_out_uop_rob_idx : issue_slots_9_out_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_fp_ctrl_vec = _T_179 ? issue_slots_10_out_uop_fp_ctrl_vec : issue_slots_9_out_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_fp_ctrl_wflags = _T_179 ? issue_slots_10_out_uop_fp_ctrl_wflags : issue_slots_9_out_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_fp_ctrl_sqrt = _T_179 ? issue_slots_10_out_uop_fp_ctrl_sqrt : issue_slots_9_out_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_fp_ctrl_div = _T_179 ? issue_slots_10_out_uop_fp_ctrl_div : issue_slots_9_out_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_fp_ctrl_fma = _T_179 ? issue_slots_10_out_uop_fp_ctrl_fma : issue_slots_9_out_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_fp_ctrl_fastpipe = _T_179 ? issue_slots_10_out_uop_fp_ctrl_fastpipe : issue_slots_9_out_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_fp_ctrl_toint = _T_179 ? issue_slots_10_out_uop_fp_ctrl_toint : issue_slots_9_out_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_fp_ctrl_fromint = _T_179 ? issue_slots_10_out_uop_fp_ctrl_fromint : issue_slots_9_out_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_fp_ctrl_typeTagOut = _T_179 ? issue_slots_10_out_uop_fp_ctrl_typeTagOut : issue_slots_9_out_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_fp_ctrl_typeTagIn = _T_179 ? issue_slots_10_out_uop_fp_ctrl_typeTagIn : issue_slots_9_out_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_fp_ctrl_swap23 = _T_179 ? issue_slots_10_out_uop_fp_ctrl_swap23 : issue_slots_9_out_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_fp_ctrl_swap12 = _T_179 ? issue_slots_10_out_uop_fp_ctrl_swap12 : issue_slots_9_out_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_fp_ctrl_ren3 = _T_179 ? issue_slots_10_out_uop_fp_ctrl_ren3 : issue_slots_9_out_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_fp_ctrl_ren2 = _T_179 ? issue_slots_10_out_uop_fp_ctrl_ren2 : issue_slots_9_out_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_fp_ctrl_ren1 = _T_179 ? issue_slots_10_out_uop_fp_ctrl_ren1 : issue_slots_9_out_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_fp_ctrl_wen = _T_179 ? issue_slots_10_out_uop_fp_ctrl_wen : issue_slots_9_out_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_fp_ctrl_ldst = _T_179 ? issue_slots_10_out_uop_fp_ctrl_ldst : issue_slots_9_out_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_op2_sel = _T_179 ? issue_slots_10_out_uop_op2_sel : issue_slots_9_out_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_op1_sel = _T_179 ? issue_slots_10_out_uop_op1_sel : issue_slots_9_out_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_imm_packed = _T_179 ? issue_slots_10_out_uop_imm_packed : issue_slots_9_out_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_pimm = _T_179 ? issue_slots_10_out_uop_pimm : issue_slots_9_out_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_imm_sel = _T_179 ? issue_slots_10_out_uop_imm_sel : issue_slots_9_out_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_imm_rename = _T_179 ? issue_slots_10_out_uop_imm_rename : issue_slots_9_out_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_taken = _T_179 ? issue_slots_10_out_uop_taken : issue_slots_9_out_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_pc_lob = _T_179 ? issue_slots_10_out_uop_pc_lob : issue_slots_9_out_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_edge_inst = _T_179 ? issue_slots_10_out_uop_edge_inst : issue_slots_9_out_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_ftq_idx = _T_179 ? issue_slots_10_out_uop_ftq_idx : issue_slots_9_out_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_is_mov = _T_179 ? issue_slots_10_out_uop_is_mov : issue_slots_9_out_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_is_rocc = _T_179 ? issue_slots_10_out_uop_is_rocc : issue_slots_9_out_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_is_sys_pc2epc = _T_179 ? issue_slots_10_out_uop_is_sys_pc2epc : issue_slots_9_out_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_is_eret = _T_179 ? issue_slots_10_out_uop_is_eret : issue_slots_9_out_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_is_amo = _T_179 ? issue_slots_10_out_uop_is_amo : issue_slots_9_out_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_is_sfence = _T_179 ? issue_slots_10_out_uop_is_sfence : issue_slots_9_out_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_is_fencei = _T_179 ? issue_slots_10_out_uop_is_fencei : issue_slots_9_out_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_is_fence = _T_179 ? issue_slots_10_out_uop_is_fence : issue_slots_9_out_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_is_sfb = _T_179 ? issue_slots_10_out_uop_is_sfb : issue_slots_9_out_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_br_type = _T_179 ? issue_slots_10_out_uop_br_type : issue_slots_9_out_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_br_tag = _T_179 ? issue_slots_10_out_uop_br_tag : issue_slots_9_out_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_br_mask = _T_179 ? issue_slots_10_out_uop_br_mask : issue_slots_9_out_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_dis_col_sel = _T_179 ? issue_slots_10_out_uop_dis_col_sel : issue_slots_9_out_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_iw_p3_bypass_hint = _T_179 ? issue_slots_10_out_uop_iw_p3_bypass_hint : issue_slots_9_out_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_iw_p2_bypass_hint = _T_179 ? issue_slots_10_out_uop_iw_p2_bypass_hint : issue_slots_9_out_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_iw_p1_bypass_hint = _T_179 ? issue_slots_10_out_uop_iw_p1_bypass_hint : issue_slots_9_out_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_iw_p2_speculative_child = _T_179 ? issue_slots_10_out_uop_iw_p2_speculative_child : issue_slots_9_out_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_iw_p1_speculative_child = _T_179 ? issue_slots_10_out_uop_iw_p1_speculative_child : issue_slots_9_out_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_iw_issued = _T_179 ? issue_slots_10_out_uop_iw_issued : issue_slots_9_out_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_fu_code_0 = _T_179 ? issue_slots_10_out_uop_fu_code_0 : issue_slots_9_out_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_fu_code_1 = _T_179 ? issue_slots_10_out_uop_fu_code_1 : issue_slots_9_out_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_fu_code_2 = _T_179 ? issue_slots_10_out_uop_fu_code_2 : issue_slots_9_out_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_fu_code_3 = _T_179 ? issue_slots_10_out_uop_fu_code_3 : issue_slots_9_out_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_fu_code_4 = _T_179 ? issue_slots_10_out_uop_fu_code_4 : issue_slots_9_out_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_fu_code_5 = _T_179 ? issue_slots_10_out_uop_fu_code_5 : issue_slots_9_out_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_fu_code_6 = _T_179 ? issue_slots_10_out_uop_fu_code_6 : issue_slots_9_out_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_fu_code_7 = _T_179 ? issue_slots_10_out_uop_fu_code_7 : issue_slots_9_out_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_fu_code_8 = _T_179 ? issue_slots_10_out_uop_fu_code_8 : issue_slots_9_out_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_fu_code_9 = _T_179 ? issue_slots_10_out_uop_fu_code_9 : issue_slots_9_out_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_iq_type_0 = _T_179 ? issue_slots_10_out_uop_iq_type_0 : issue_slots_9_out_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_iq_type_1 = _T_179 ? issue_slots_10_out_uop_iq_type_1 : issue_slots_9_out_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_iq_type_2 = _T_179 ? issue_slots_10_out_uop_iq_type_2 : issue_slots_9_out_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_iq_type_3 = _T_179 ? issue_slots_10_out_uop_iq_type_3 : issue_slots_9_out_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_debug_pc = _T_179 ? issue_slots_10_out_uop_debug_pc : issue_slots_9_out_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_is_rvc = _T_179 ? issue_slots_10_out_uop_is_rvc : issue_slots_9_out_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_debug_inst = _T_179 ? issue_slots_10_out_uop_debug_inst : issue_slots_9_out_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_8_in_uop_bits_inst = _T_179 ? issue_slots_10_out_uop_inst : issue_slots_9_out_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign _issue_slots_8_clear_T = |shamts_oh_8;\t// @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49]\n assign issue_slots_8_clear = _issue_slots_8_clear_T;\t// @[issue-unit-age-ordered.scala:122:28, :199:49]\n wire _T_181 = shamts_oh_11 == 2'h2;\t// @[issue-unit-age-ordered.scala:158:23, :194:28]\n assign issue_slots_9_in_uop_valid = _T_181 ? issue_slots_11_will_be_valid : shamts_oh_10 == 2'h1 & issue_slots_10_will_be_valid;\t// @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37]\n assign issue_slots_9_in_uop_bits_debug_tsrc = _T_181 ? issue_slots_11_out_uop_debug_tsrc : issue_slots_10_out_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_debug_fsrc = _T_181 ? issue_slots_11_out_uop_debug_fsrc : issue_slots_10_out_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_bp_xcpt_if = _T_181 ? issue_slots_11_out_uop_bp_xcpt_if : issue_slots_10_out_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_bp_debug_if = _T_181 ? issue_slots_11_out_uop_bp_debug_if : issue_slots_10_out_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_xcpt_ma_if = _T_181 ? issue_slots_11_out_uop_xcpt_ma_if : issue_slots_10_out_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_xcpt_ae_if = _T_181 ? issue_slots_11_out_uop_xcpt_ae_if : issue_slots_10_out_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_xcpt_pf_if = _T_181 ? issue_slots_11_out_uop_xcpt_pf_if : issue_slots_10_out_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_fp_typ = _T_181 ? issue_slots_11_out_uop_fp_typ : issue_slots_10_out_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_fp_rm = _T_181 ? issue_slots_11_out_uop_fp_rm : issue_slots_10_out_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_fp_val = _T_181 ? issue_slots_11_out_uop_fp_val : issue_slots_10_out_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_fcn_op = _T_181 ? issue_slots_11_out_uop_fcn_op : issue_slots_10_out_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_fcn_dw = _T_181 ? issue_slots_11_out_uop_fcn_dw : issue_slots_10_out_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_frs3_en = _T_181 ? issue_slots_11_out_uop_frs3_en : issue_slots_10_out_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_lrs2_rtype = _T_181 ? issue_slots_11_out_uop_lrs2_rtype : issue_slots_10_out_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_lrs1_rtype = _T_181 ? issue_slots_11_out_uop_lrs1_rtype : issue_slots_10_out_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_dst_rtype = _T_181 ? issue_slots_11_out_uop_dst_rtype : issue_slots_10_out_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_lrs3 = _T_181 ? issue_slots_11_out_uop_lrs3 : issue_slots_10_out_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_lrs2 = _T_181 ? issue_slots_11_out_uop_lrs2 : issue_slots_10_out_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_lrs1 = _T_181 ? issue_slots_11_out_uop_lrs1 : issue_slots_10_out_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_ldst = _T_181 ? issue_slots_11_out_uop_ldst : issue_slots_10_out_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_ldst_is_rs1 = _T_181 ? issue_slots_11_out_uop_ldst_is_rs1 : issue_slots_10_out_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_csr_cmd = _T_181 ? issue_slots_11_out_uop_csr_cmd : issue_slots_10_out_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_flush_on_commit = _T_181 ? issue_slots_11_out_uop_flush_on_commit : issue_slots_10_out_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_is_unique = _T_181 ? issue_slots_11_out_uop_is_unique : issue_slots_10_out_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_uses_stq = _T_181 ? issue_slots_11_out_uop_uses_stq : issue_slots_10_out_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_uses_ldq = _T_181 ? issue_slots_11_out_uop_uses_ldq : issue_slots_10_out_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_mem_signed = _T_181 ? issue_slots_11_out_uop_mem_signed : issue_slots_10_out_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_mem_size = _T_181 ? issue_slots_11_out_uop_mem_size : issue_slots_10_out_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_mem_cmd = _T_181 ? issue_slots_11_out_uop_mem_cmd : issue_slots_10_out_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_exc_cause = _T_181 ? issue_slots_11_out_uop_exc_cause : issue_slots_10_out_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_exception = _T_181 ? issue_slots_11_out_uop_exception : issue_slots_10_out_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_stale_pdst = _T_181 ? issue_slots_11_out_uop_stale_pdst : issue_slots_10_out_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_ppred_busy = _T_181 ? issue_slots_11_out_uop_ppred_busy : issue_slots_10_out_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_prs3_busy = _T_181 ? issue_slots_11_out_uop_prs3_busy : issue_slots_10_out_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_prs2_busy = _T_181 ? issue_slots_11_out_uop_prs2_busy : issue_slots_10_out_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_prs1_busy = _T_181 ? issue_slots_11_out_uop_prs1_busy : issue_slots_10_out_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_ppred = _T_181 ? issue_slots_11_out_uop_ppred : issue_slots_10_out_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_prs3 = _T_181 ? issue_slots_11_out_uop_prs3 : issue_slots_10_out_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_prs2 = _T_181 ? issue_slots_11_out_uop_prs2 : issue_slots_10_out_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_prs1 = _T_181 ? issue_slots_11_out_uop_prs1 : issue_slots_10_out_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_pdst = _T_181 ? issue_slots_11_out_uop_pdst : issue_slots_10_out_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_rxq_idx = _T_181 ? issue_slots_11_out_uop_rxq_idx : issue_slots_10_out_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_stq_idx = _T_181 ? issue_slots_11_out_uop_stq_idx : issue_slots_10_out_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_ldq_idx = _T_181 ? issue_slots_11_out_uop_ldq_idx : issue_slots_10_out_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_rob_idx = _T_181 ? issue_slots_11_out_uop_rob_idx : issue_slots_10_out_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_fp_ctrl_vec = _T_181 ? issue_slots_11_out_uop_fp_ctrl_vec : issue_slots_10_out_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_fp_ctrl_wflags = _T_181 ? issue_slots_11_out_uop_fp_ctrl_wflags : issue_slots_10_out_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_fp_ctrl_sqrt = _T_181 ? issue_slots_11_out_uop_fp_ctrl_sqrt : issue_slots_10_out_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_fp_ctrl_div = _T_181 ? issue_slots_11_out_uop_fp_ctrl_div : issue_slots_10_out_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_fp_ctrl_fma = _T_181 ? issue_slots_11_out_uop_fp_ctrl_fma : issue_slots_10_out_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_fp_ctrl_fastpipe = _T_181 ? issue_slots_11_out_uop_fp_ctrl_fastpipe : issue_slots_10_out_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_fp_ctrl_toint = _T_181 ? issue_slots_11_out_uop_fp_ctrl_toint : issue_slots_10_out_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_fp_ctrl_fromint = _T_181 ? issue_slots_11_out_uop_fp_ctrl_fromint : issue_slots_10_out_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_fp_ctrl_typeTagOut = _T_181 ? issue_slots_11_out_uop_fp_ctrl_typeTagOut : issue_slots_10_out_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_fp_ctrl_typeTagIn = _T_181 ? issue_slots_11_out_uop_fp_ctrl_typeTagIn : issue_slots_10_out_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_fp_ctrl_swap23 = _T_181 ? issue_slots_11_out_uop_fp_ctrl_swap23 : issue_slots_10_out_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_fp_ctrl_swap12 = _T_181 ? issue_slots_11_out_uop_fp_ctrl_swap12 : issue_slots_10_out_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_fp_ctrl_ren3 = _T_181 ? issue_slots_11_out_uop_fp_ctrl_ren3 : issue_slots_10_out_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_fp_ctrl_ren2 = _T_181 ? issue_slots_11_out_uop_fp_ctrl_ren2 : issue_slots_10_out_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_fp_ctrl_ren1 = _T_181 ? issue_slots_11_out_uop_fp_ctrl_ren1 : issue_slots_10_out_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_fp_ctrl_wen = _T_181 ? issue_slots_11_out_uop_fp_ctrl_wen : issue_slots_10_out_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_fp_ctrl_ldst = _T_181 ? issue_slots_11_out_uop_fp_ctrl_ldst : issue_slots_10_out_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_op2_sel = _T_181 ? issue_slots_11_out_uop_op2_sel : issue_slots_10_out_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_op1_sel = _T_181 ? issue_slots_11_out_uop_op1_sel : issue_slots_10_out_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_imm_packed = _T_181 ? issue_slots_11_out_uop_imm_packed : issue_slots_10_out_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_pimm = _T_181 ? issue_slots_11_out_uop_pimm : issue_slots_10_out_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_imm_sel = _T_181 ? issue_slots_11_out_uop_imm_sel : issue_slots_10_out_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_imm_rename = _T_181 ? issue_slots_11_out_uop_imm_rename : issue_slots_10_out_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_taken = _T_181 ? issue_slots_11_out_uop_taken : issue_slots_10_out_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_pc_lob = _T_181 ? issue_slots_11_out_uop_pc_lob : issue_slots_10_out_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_edge_inst = _T_181 ? issue_slots_11_out_uop_edge_inst : issue_slots_10_out_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_ftq_idx = _T_181 ? issue_slots_11_out_uop_ftq_idx : issue_slots_10_out_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_is_mov = _T_181 ? issue_slots_11_out_uop_is_mov : issue_slots_10_out_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_is_rocc = _T_181 ? issue_slots_11_out_uop_is_rocc : issue_slots_10_out_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_is_sys_pc2epc = _T_181 ? issue_slots_11_out_uop_is_sys_pc2epc : issue_slots_10_out_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_is_eret = _T_181 ? issue_slots_11_out_uop_is_eret : issue_slots_10_out_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_is_amo = _T_181 ? issue_slots_11_out_uop_is_amo : issue_slots_10_out_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_is_sfence = _T_181 ? issue_slots_11_out_uop_is_sfence : issue_slots_10_out_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_is_fencei = _T_181 ? issue_slots_11_out_uop_is_fencei : issue_slots_10_out_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_is_fence = _T_181 ? issue_slots_11_out_uop_is_fence : issue_slots_10_out_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_is_sfb = _T_181 ? issue_slots_11_out_uop_is_sfb : issue_slots_10_out_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_br_type = _T_181 ? issue_slots_11_out_uop_br_type : issue_slots_10_out_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_br_tag = _T_181 ? issue_slots_11_out_uop_br_tag : issue_slots_10_out_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_br_mask = _T_181 ? issue_slots_11_out_uop_br_mask : issue_slots_10_out_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_dis_col_sel = _T_181 ? issue_slots_11_out_uop_dis_col_sel : issue_slots_10_out_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_iw_p3_bypass_hint = _T_181 ? issue_slots_11_out_uop_iw_p3_bypass_hint : issue_slots_10_out_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_iw_p2_bypass_hint = _T_181 ? issue_slots_11_out_uop_iw_p2_bypass_hint : issue_slots_10_out_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_iw_p1_bypass_hint = _T_181 ? issue_slots_11_out_uop_iw_p1_bypass_hint : issue_slots_10_out_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_iw_p2_speculative_child = _T_181 ? issue_slots_11_out_uop_iw_p2_speculative_child : issue_slots_10_out_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_iw_p1_speculative_child = _T_181 ? issue_slots_11_out_uop_iw_p1_speculative_child : issue_slots_10_out_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_iw_issued = _T_181 ? issue_slots_11_out_uop_iw_issued : issue_slots_10_out_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_fu_code_0 = _T_181 ? issue_slots_11_out_uop_fu_code_0 : issue_slots_10_out_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_fu_code_1 = _T_181 ? issue_slots_11_out_uop_fu_code_1 : issue_slots_10_out_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_fu_code_2 = _T_181 ? issue_slots_11_out_uop_fu_code_2 : issue_slots_10_out_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_fu_code_3 = _T_181 ? issue_slots_11_out_uop_fu_code_3 : issue_slots_10_out_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_fu_code_4 = _T_181 ? issue_slots_11_out_uop_fu_code_4 : issue_slots_10_out_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_fu_code_5 = _T_181 ? issue_slots_11_out_uop_fu_code_5 : issue_slots_10_out_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_fu_code_6 = _T_181 ? issue_slots_11_out_uop_fu_code_6 : issue_slots_10_out_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_fu_code_7 = _T_181 ? issue_slots_11_out_uop_fu_code_7 : issue_slots_10_out_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_fu_code_8 = _T_181 ? issue_slots_11_out_uop_fu_code_8 : issue_slots_10_out_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_fu_code_9 = _T_181 ? issue_slots_11_out_uop_fu_code_9 : issue_slots_10_out_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_iq_type_0 = _T_181 ? issue_slots_11_out_uop_iq_type_0 : issue_slots_10_out_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_iq_type_1 = _T_181 ? issue_slots_11_out_uop_iq_type_1 : issue_slots_10_out_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_iq_type_2 = _T_181 ? issue_slots_11_out_uop_iq_type_2 : issue_slots_10_out_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_iq_type_3 = _T_181 ? issue_slots_11_out_uop_iq_type_3 : issue_slots_10_out_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_debug_pc = _T_181 ? issue_slots_11_out_uop_debug_pc : issue_slots_10_out_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_is_rvc = _T_181 ? issue_slots_11_out_uop_is_rvc : issue_slots_10_out_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_debug_inst = _T_181 ? issue_slots_11_out_uop_debug_inst : issue_slots_10_out_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_9_in_uop_bits_inst = _T_181 ? issue_slots_11_out_uop_inst : issue_slots_10_out_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign _issue_slots_9_clear_T = |shamts_oh_9;\t// @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49]\n assign issue_slots_9_clear = _issue_slots_9_clear_T;\t// @[issue-unit-age-ordered.scala:122:28, :199:49]\n wire _T_183 = shamts_oh_12 == 2'h2;\t// @[issue-unit-age-ordered.scala:158:23, :194:28]\n assign issue_slots_10_in_uop_valid = _T_183 ? issue_slots_12_will_be_valid : shamts_oh_11 == 2'h1 & issue_slots_11_will_be_valid;\t// @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37]\n assign issue_slots_10_in_uop_bits_debug_tsrc = _T_183 ? issue_slots_12_out_uop_debug_tsrc : issue_slots_11_out_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_debug_fsrc = _T_183 ? issue_slots_12_out_uop_debug_fsrc : issue_slots_11_out_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_bp_xcpt_if = _T_183 ? issue_slots_12_out_uop_bp_xcpt_if : issue_slots_11_out_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_bp_debug_if = _T_183 ? issue_slots_12_out_uop_bp_debug_if : issue_slots_11_out_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_xcpt_ma_if = _T_183 ? issue_slots_12_out_uop_xcpt_ma_if : issue_slots_11_out_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_xcpt_ae_if = _T_183 ? issue_slots_12_out_uop_xcpt_ae_if : issue_slots_11_out_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_xcpt_pf_if = _T_183 ? issue_slots_12_out_uop_xcpt_pf_if : issue_slots_11_out_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_fp_typ = _T_183 ? issue_slots_12_out_uop_fp_typ : issue_slots_11_out_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_fp_rm = _T_183 ? issue_slots_12_out_uop_fp_rm : issue_slots_11_out_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_fp_val = _T_183 ? issue_slots_12_out_uop_fp_val : issue_slots_11_out_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_fcn_op = _T_183 ? issue_slots_12_out_uop_fcn_op : issue_slots_11_out_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_fcn_dw = _T_183 ? issue_slots_12_out_uop_fcn_dw : issue_slots_11_out_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_frs3_en = _T_183 ? issue_slots_12_out_uop_frs3_en : issue_slots_11_out_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_lrs2_rtype = _T_183 ? issue_slots_12_out_uop_lrs2_rtype : issue_slots_11_out_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_lrs1_rtype = _T_183 ? issue_slots_12_out_uop_lrs1_rtype : issue_slots_11_out_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_dst_rtype = _T_183 ? issue_slots_12_out_uop_dst_rtype : issue_slots_11_out_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_lrs3 = _T_183 ? issue_slots_12_out_uop_lrs3 : issue_slots_11_out_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_lrs2 = _T_183 ? issue_slots_12_out_uop_lrs2 : issue_slots_11_out_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_lrs1 = _T_183 ? issue_slots_12_out_uop_lrs1 : issue_slots_11_out_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_ldst = _T_183 ? issue_slots_12_out_uop_ldst : issue_slots_11_out_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_ldst_is_rs1 = _T_183 ? issue_slots_12_out_uop_ldst_is_rs1 : issue_slots_11_out_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_csr_cmd = _T_183 ? issue_slots_12_out_uop_csr_cmd : issue_slots_11_out_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_flush_on_commit = _T_183 ? issue_slots_12_out_uop_flush_on_commit : issue_slots_11_out_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_is_unique = _T_183 ? issue_slots_12_out_uop_is_unique : issue_slots_11_out_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_uses_stq = _T_183 ? issue_slots_12_out_uop_uses_stq : issue_slots_11_out_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_uses_ldq = _T_183 ? issue_slots_12_out_uop_uses_ldq : issue_slots_11_out_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_mem_signed = _T_183 ? issue_slots_12_out_uop_mem_signed : issue_slots_11_out_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_mem_size = _T_183 ? issue_slots_12_out_uop_mem_size : issue_slots_11_out_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_mem_cmd = _T_183 ? issue_slots_12_out_uop_mem_cmd : issue_slots_11_out_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_exc_cause = _T_183 ? issue_slots_12_out_uop_exc_cause : issue_slots_11_out_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_exception = _T_183 ? issue_slots_12_out_uop_exception : issue_slots_11_out_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_stale_pdst = _T_183 ? issue_slots_12_out_uop_stale_pdst : issue_slots_11_out_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_ppred_busy = _T_183 ? issue_slots_12_out_uop_ppred_busy : issue_slots_11_out_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_prs3_busy = _T_183 ? issue_slots_12_out_uop_prs3_busy : issue_slots_11_out_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_prs2_busy = _T_183 ? issue_slots_12_out_uop_prs2_busy : issue_slots_11_out_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_prs1_busy = _T_183 ? issue_slots_12_out_uop_prs1_busy : issue_slots_11_out_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_ppred = _T_183 ? issue_slots_12_out_uop_ppred : issue_slots_11_out_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_prs3 = _T_183 ? issue_slots_12_out_uop_prs3 : issue_slots_11_out_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_prs2 = _T_183 ? issue_slots_12_out_uop_prs2 : issue_slots_11_out_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_prs1 = _T_183 ? issue_slots_12_out_uop_prs1 : issue_slots_11_out_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_pdst = _T_183 ? issue_slots_12_out_uop_pdst : issue_slots_11_out_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_rxq_idx = _T_183 ? issue_slots_12_out_uop_rxq_idx : issue_slots_11_out_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_stq_idx = _T_183 ? issue_slots_12_out_uop_stq_idx : issue_slots_11_out_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_ldq_idx = _T_183 ? issue_slots_12_out_uop_ldq_idx : issue_slots_11_out_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_rob_idx = _T_183 ? issue_slots_12_out_uop_rob_idx : issue_slots_11_out_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_fp_ctrl_vec = _T_183 ? issue_slots_12_out_uop_fp_ctrl_vec : issue_slots_11_out_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_fp_ctrl_wflags = _T_183 ? issue_slots_12_out_uop_fp_ctrl_wflags : issue_slots_11_out_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_fp_ctrl_sqrt = _T_183 ? issue_slots_12_out_uop_fp_ctrl_sqrt : issue_slots_11_out_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_fp_ctrl_div = _T_183 ? issue_slots_12_out_uop_fp_ctrl_div : issue_slots_11_out_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_fp_ctrl_fma = _T_183 ? issue_slots_12_out_uop_fp_ctrl_fma : issue_slots_11_out_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_fp_ctrl_fastpipe = _T_183 ? issue_slots_12_out_uop_fp_ctrl_fastpipe : issue_slots_11_out_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_fp_ctrl_toint = _T_183 ? issue_slots_12_out_uop_fp_ctrl_toint : issue_slots_11_out_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_fp_ctrl_fromint = _T_183 ? issue_slots_12_out_uop_fp_ctrl_fromint : issue_slots_11_out_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_fp_ctrl_typeTagOut = _T_183 ? issue_slots_12_out_uop_fp_ctrl_typeTagOut : issue_slots_11_out_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_fp_ctrl_typeTagIn = _T_183 ? issue_slots_12_out_uop_fp_ctrl_typeTagIn : issue_slots_11_out_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_fp_ctrl_swap23 = _T_183 ? issue_slots_12_out_uop_fp_ctrl_swap23 : issue_slots_11_out_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_fp_ctrl_swap12 = _T_183 ? issue_slots_12_out_uop_fp_ctrl_swap12 : issue_slots_11_out_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_fp_ctrl_ren3 = _T_183 ? issue_slots_12_out_uop_fp_ctrl_ren3 : issue_slots_11_out_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_fp_ctrl_ren2 = _T_183 ? issue_slots_12_out_uop_fp_ctrl_ren2 : issue_slots_11_out_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_fp_ctrl_ren1 = _T_183 ? issue_slots_12_out_uop_fp_ctrl_ren1 : issue_slots_11_out_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_fp_ctrl_wen = _T_183 ? issue_slots_12_out_uop_fp_ctrl_wen : issue_slots_11_out_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_fp_ctrl_ldst = _T_183 ? issue_slots_12_out_uop_fp_ctrl_ldst : issue_slots_11_out_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_op2_sel = _T_183 ? issue_slots_12_out_uop_op2_sel : issue_slots_11_out_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_op1_sel = _T_183 ? issue_slots_12_out_uop_op1_sel : issue_slots_11_out_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_imm_packed = _T_183 ? issue_slots_12_out_uop_imm_packed : issue_slots_11_out_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_pimm = _T_183 ? issue_slots_12_out_uop_pimm : issue_slots_11_out_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_imm_sel = _T_183 ? issue_slots_12_out_uop_imm_sel : issue_slots_11_out_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_imm_rename = _T_183 ? issue_slots_12_out_uop_imm_rename : issue_slots_11_out_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_taken = _T_183 ? issue_slots_12_out_uop_taken : issue_slots_11_out_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_pc_lob = _T_183 ? issue_slots_12_out_uop_pc_lob : issue_slots_11_out_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_edge_inst = _T_183 ? issue_slots_12_out_uop_edge_inst : issue_slots_11_out_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_ftq_idx = _T_183 ? issue_slots_12_out_uop_ftq_idx : issue_slots_11_out_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_is_mov = _T_183 ? issue_slots_12_out_uop_is_mov : issue_slots_11_out_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_is_rocc = _T_183 ? issue_slots_12_out_uop_is_rocc : issue_slots_11_out_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_is_sys_pc2epc = _T_183 ? issue_slots_12_out_uop_is_sys_pc2epc : issue_slots_11_out_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_is_eret = _T_183 ? issue_slots_12_out_uop_is_eret : issue_slots_11_out_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_is_amo = _T_183 ? issue_slots_12_out_uop_is_amo : issue_slots_11_out_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_is_sfence = _T_183 ? issue_slots_12_out_uop_is_sfence : issue_slots_11_out_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_is_fencei = _T_183 ? issue_slots_12_out_uop_is_fencei : issue_slots_11_out_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_is_fence = _T_183 ? issue_slots_12_out_uop_is_fence : issue_slots_11_out_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_is_sfb = _T_183 ? issue_slots_12_out_uop_is_sfb : issue_slots_11_out_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_br_type = _T_183 ? issue_slots_12_out_uop_br_type : issue_slots_11_out_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_br_tag = _T_183 ? issue_slots_12_out_uop_br_tag : issue_slots_11_out_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_br_mask = _T_183 ? issue_slots_12_out_uop_br_mask : issue_slots_11_out_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_dis_col_sel = _T_183 ? issue_slots_12_out_uop_dis_col_sel : issue_slots_11_out_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_iw_p3_bypass_hint = _T_183 ? issue_slots_12_out_uop_iw_p3_bypass_hint : issue_slots_11_out_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_iw_p2_bypass_hint = _T_183 ? issue_slots_12_out_uop_iw_p2_bypass_hint : issue_slots_11_out_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_iw_p1_bypass_hint = _T_183 ? issue_slots_12_out_uop_iw_p1_bypass_hint : issue_slots_11_out_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_iw_p2_speculative_child = _T_183 ? issue_slots_12_out_uop_iw_p2_speculative_child : issue_slots_11_out_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_iw_p1_speculative_child = _T_183 ? issue_slots_12_out_uop_iw_p1_speculative_child : issue_slots_11_out_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_iw_issued = _T_183 ? issue_slots_12_out_uop_iw_issued : issue_slots_11_out_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_fu_code_0 = _T_183 ? issue_slots_12_out_uop_fu_code_0 : issue_slots_11_out_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_fu_code_1 = _T_183 ? issue_slots_12_out_uop_fu_code_1 : issue_slots_11_out_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_fu_code_2 = _T_183 ? issue_slots_12_out_uop_fu_code_2 : issue_slots_11_out_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_fu_code_3 = _T_183 ? issue_slots_12_out_uop_fu_code_3 : issue_slots_11_out_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_fu_code_4 = _T_183 ? issue_slots_12_out_uop_fu_code_4 : issue_slots_11_out_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_fu_code_5 = _T_183 ? issue_slots_12_out_uop_fu_code_5 : issue_slots_11_out_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_fu_code_6 = _T_183 ? issue_slots_12_out_uop_fu_code_6 : issue_slots_11_out_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_fu_code_7 = _T_183 ? issue_slots_12_out_uop_fu_code_7 : issue_slots_11_out_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_fu_code_8 = _T_183 ? issue_slots_12_out_uop_fu_code_8 : issue_slots_11_out_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_fu_code_9 = _T_183 ? issue_slots_12_out_uop_fu_code_9 : issue_slots_11_out_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_iq_type_0 = _T_183 ? issue_slots_12_out_uop_iq_type_0 : issue_slots_11_out_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_iq_type_1 = _T_183 ? issue_slots_12_out_uop_iq_type_1 : issue_slots_11_out_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_iq_type_2 = _T_183 ? issue_slots_12_out_uop_iq_type_2 : issue_slots_11_out_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_iq_type_3 = _T_183 ? issue_slots_12_out_uop_iq_type_3 : issue_slots_11_out_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_debug_pc = _T_183 ? issue_slots_12_out_uop_debug_pc : issue_slots_11_out_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_is_rvc = _T_183 ? issue_slots_12_out_uop_is_rvc : issue_slots_11_out_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_debug_inst = _T_183 ? issue_slots_12_out_uop_debug_inst : issue_slots_11_out_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_10_in_uop_bits_inst = _T_183 ? issue_slots_12_out_uop_inst : issue_slots_11_out_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign _issue_slots_10_clear_T = |shamts_oh_10;\t// @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49]\n assign issue_slots_10_clear = _issue_slots_10_clear_T;\t// @[issue-unit-age-ordered.scala:122:28, :199:49]\n wire _T_185 = shamts_oh_13 == 2'h2;\t// @[issue-unit-age-ordered.scala:158:23, :194:28]\n assign issue_slots_11_in_uop_valid = _T_185 ? issue_slots_13_will_be_valid : shamts_oh_12 == 2'h1 & issue_slots_12_will_be_valid;\t// @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37]\n assign issue_slots_11_in_uop_bits_debug_tsrc = _T_185 ? issue_slots_13_out_uop_debug_tsrc : issue_slots_12_out_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_debug_fsrc = _T_185 ? issue_slots_13_out_uop_debug_fsrc : issue_slots_12_out_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_bp_xcpt_if = _T_185 ? issue_slots_13_out_uop_bp_xcpt_if : issue_slots_12_out_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_bp_debug_if = _T_185 ? issue_slots_13_out_uop_bp_debug_if : issue_slots_12_out_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_xcpt_ma_if = _T_185 ? issue_slots_13_out_uop_xcpt_ma_if : issue_slots_12_out_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_xcpt_ae_if = _T_185 ? issue_slots_13_out_uop_xcpt_ae_if : issue_slots_12_out_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_xcpt_pf_if = _T_185 ? issue_slots_13_out_uop_xcpt_pf_if : issue_slots_12_out_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_fp_typ = _T_185 ? issue_slots_13_out_uop_fp_typ : issue_slots_12_out_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_fp_rm = _T_185 ? issue_slots_13_out_uop_fp_rm : issue_slots_12_out_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_fp_val = _T_185 ? issue_slots_13_out_uop_fp_val : issue_slots_12_out_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_fcn_op = _T_185 ? issue_slots_13_out_uop_fcn_op : issue_slots_12_out_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_fcn_dw = _T_185 ? issue_slots_13_out_uop_fcn_dw : issue_slots_12_out_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_frs3_en = _T_185 ? issue_slots_13_out_uop_frs3_en : issue_slots_12_out_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_lrs2_rtype = _T_185 ? issue_slots_13_out_uop_lrs2_rtype : issue_slots_12_out_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_lrs1_rtype = _T_185 ? issue_slots_13_out_uop_lrs1_rtype : issue_slots_12_out_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_dst_rtype = _T_185 ? issue_slots_13_out_uop_dst_rtype : issue_slots_12_out_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_lrs3 = _T_185 ? issue_slots_13_out_uop_lrs3 : issue_slots_12_out_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_lrs2 = _T_185 ? issue_slots_13_out_uop_lrs2 : issue_slots_12_out_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_lrs1 = _T_185 ? issue_slots_13_out_uop_lrs1 : issue_slots_12_out_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_ldst = _T_185 ? issue_slots_13_out_uop_ldst : issue_slots_12_out_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_ldst_is_rs1 = _T_185 ? issue_slots_13_out_uop_ldst_is_rs1 : issue_slots_12_out_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_csr_cmd = _T_185 ? issue_slots_13_out_uop_csr_cmd : issue_slots_12_out_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_flush_on_commit = _T_185 ? issue_slots_13_out_uop_flush_on_commit : issue_slots_12_out_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_is_unique = _T_185 ? issue_slots_13_out_uop_is_unique : issue_slots_12_out_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_uses_stq = _T_185 ? issue_slots_13_out_uop_uses_stq : issue_slots_12_out_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_uses_ldq = _T_185 ? issue_slots_13_out_uop_uses_ldq : issue_slots_12_out_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_mem_signed = _T_185 ? issue_slots_13_out_uop_mem_signed : issue_slots_12_out_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_mem_size = _T_185 ? issue_slots_13_out_uop_mem_size : issue_slots_12_out_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_mem_cmd = _T_185 ? issue_slots_13_out_uop_mem_cmd : issue_slots_12_out_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_exc_cause = _T_185 ? issue_slots_13_out_uop_exc_cause : issue_slots_12_out_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_exception = _T_185 ? issue_slots_13_out_uop_exception : issue_slots_12_out_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_stale_pdst = _T_185 ? issue_slots_13_out_uop_stale_pdst : issue_slots_12_out_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_ppred_busy = _T_185 ? issue_slots_13_out_uop_ppred_busy : issue_slots_12_out_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_prs3_busy = _T_185 ? issue_slots_13_out_uop_prs3_busy : issue_slots_12_out_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_prs2_busy = _T_185 ? issue_slots_13_out_uop_prs2_busy : issue_slots_12_out_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_prs1_busy = _T_185 ? issue_slots_13_out_uop_prs1_busy : issue_slots_12_out_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_ppred = _T_185 ? issue_slots_13_out_uop_ppred : issue_slots_12_out_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_prs3 = _T_185 ? issue_slots_13_out_uop_prs3 : issue_slots_12_out_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_prs2 = _T_185 ? issue_slots_13_out_uop_prs2 : issue_slots_12_out_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_prs1 = _T_185 ? issue_slots_13_out_uop_prs1 : issue_slots_12_out_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_pdst = _T_185 ? issue_slots_13_out_uop_pdst : issue_slots_12_out_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_rxq_idx = _T_185 ? issue_slots_13_out_uop_rxq_idx : issue_slots_12_out_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_stq_idx = _T_185 ? issue_slots_13_out_uop_stq_idx : issue_slots_12_out_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_ldq_idx = _T_185 ? issue_slots_13_out_uop_ldq_idx : issue_slots_12_out_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_rob_idx = _T_185 ? issue_slots_13_out_uop_rob_idx : issue_slots_12_out_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_fp_ctrl_vec = _T_185 ? issue_slots_13_out_uop_fp_ctrl_vec : issue_slots_12_out_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_fp_ctrl_wflags = _T_185 ? issue_slots_13_out_uop_fp_ctrl_wflags : issue_slots_12_out_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_fp_ctrl_sqrt = _T_185 ? issue_slots_13_out_uop_fp_ctrl_sqrt : issue_slots_12_out_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_fp_ctrl_div = _T_185 ? issue_slots_13_out_uop_fp_ctrl_div : issue_slots_12_out_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_fp_ctrl_fma = _T_185 ? issue_slots_13_out_uop_fp_ctrl_fma : issue_slots_12_out_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_fp_ctrl_fastpipe = _T_185 ? issue_slots_13_out_uop_fp_ctrl_fastpipe : issue_slots_12_out_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_fp_ctrl_toint = _T_185 ? issue_slots_13_out_uop_fp_ctrl_toint : issue_slots_12_out_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_fp_ctrl_fromint = _T_185 ? issue_slots_13_out_uop_fp_ctrl_fromint : issue_slots_12_out_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_fp_ctrl_typeTagOut = _T_185 ? issue_slots_13_out_uop_fp_ctrl_typeTagOut : issue_slots_12_out_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_fp_ctrl_typeTagIn = _T_185 ? issue_slots_13_out_uop_fp_ctrl_typeTagIn : issue_slots_12_out_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_fp_ctrl_swap23 = _T_185 ? issue_slots_13_out_uop_fp_ctrl_swap23 : issue_slots_12_out_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_fp_ctrl_swap12 = _T_185 ? issue_slots_13_out_uop_fp_ctrl_swap12 : issue_slots_12_out_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_fp_ctrl_ren3 = _T_185 ? issue_slots_13_out_uop_fp_ctrl_ren3 : issue_slots_12_out_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_fp_ctrl_ren2 = _T_185 ? issue_slots_13_out_uop_fp_ctrl_ren2 : issue_slots_12_out_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_fp_ctrl_ren1 = _T_185 ? issue_slots_13_out_uop_fp_ctrl_ren1 : issue_slots_12_out_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_fp_ctrl_wen = _T_185 ? issue_slots_13_out_uop_fp_ctrl_wen : issue_slots_12_out_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_fp_ctrl_ldst = _T_185 ? issue_slots_13_out_uop_fp_ctrl_ldst : issue_slots_12_out_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_op2_sel = _T_185 ? issue_slots_13_out_uop_op2_sel : issue_slots_12_out_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_op1_sel = _T_185 ? issue_slots_13_out_uop_op1_sel : issue_slots_12_out_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_imm_packed = _T_185 ? issue_slots_13_out_uop_imm_packed : issue_slots_12_out_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_pimm = _T_185 ? issue_slots_13_out_uop_pimm : issue_slots_12_out_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_imm_sel = _T_185 ? issue_slots_13_out_uop_imm_sel : issue_slots_12_out_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_imm_rename = _T_185 ? issue_slots_13_out_uop_imm_rename : issue_slots_12_out_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_taken = _T_185 ? issue_slots_13_out_uop_taken : issue_slots_12_out_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_pc_lob = _T_185 ? issue_slots_13_out_uop_pc_lob : issue_slots_12_out_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_edge_inst = _T_185 ? issue_slots_13_out_uop_edge_inst : issue_slots_12_out_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_ftq_idx = _T_185 ? issue_slots_13_out_uop_ftq_idx : issue_slots_12_out_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_is_mov = _T_185 ? issue_slots_13_out_uop_is_mov : issue_slots_12_out_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_is_rocc = _T_185 ? issue_slots_13_out_uop_is_rocc : issue_slots_12_out_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_is_sys_pc2epc = _T_185 ? issue_slots_13_out_uop_is_sys_pc2epc : issue_slots_12_out_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_is_eret = _T_185 ? issue_slots_13_out_uop_is_eret : issue_slots_12_out_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_is_amo = _T_185 ? issue_slots_13_out_uop_is_amo : issue_slots_12_out_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_is_sfence = _T_185 ? issue_slots_13_out_uop_is_sfence : issue_slots_12_out_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_is_fencei = _T_185 ? issue_slots_13_out_uop_is_fencei : issue_slots_12_out_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_is_fence = _T_185 ? issue_slots_13_out_uop_is_fence : issue_slots_12_out_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_is_sfb = _T_185 ? issue_slots_13_out_uop_is_sfb : issue_slots_12_out_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_br_type = _T_185 ? issue_slots_13_out_uop_br_type : issue_slots_12_out_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_br_tag = _T_185 ? issue_slots_13_out_uop_br_tag : issue_slots_12_out_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_br_mask = _T_185 ? issue_slots_13_out_uop_br_mask : issue_slots_12_out_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_dis_col_sel = _T_185 ? issue_slots_13_out_uop_dis_col_sel : issue_slots_12_out_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_iw_p3_bypass_hint = _T_185 ? issue_slots_13_out_uop_iw_p3_bypass_hint : issue_slots_12_out_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_iw_p2_bypass_hint = _T_185 ? issue_slots_13_out_uop_iw_p2_bypass_hint : issue_slots_12_out_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_iw_p1_bypass_hint = _T_185 ? issue_slots_13_out_uop_iw_p1_bypass_hint : issue_slots_12_out_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_iw_p2_speculative_child = _T_185 ? issue_slots_13_out_uop_iw_p2_speculative_child : issue_slots_12_out_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_iw_p1_speculative_child = _T_185 ? issue_slots_13_out_uop_iw_p1_speculative_child : issue_slots_12_out_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_iw_issued = _T_185 ? issue_slots_13_out_uop_iw_issued : issue_slots_12_out_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_fu_code_0 = _T_185 ? issue_slots_13_out_uop_fu_code_0 : issue_slots_12_out_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_fu_code_1 = _T_185 ? issue_slots_13_out_uop_fu_code_1 : issue_slots_12_out_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_fu_code_2 = _T_185 ? issue_slots_13_out_uop_fu_code_2 : issue_slots_12_out_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_fu_code_3 = _T_185 ? issue_slots_13_out_uop_fu_code_3 : issue_slots_12_out_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_fu_code_4 = _T_185 ? issue_slots_13_out_uop_fu_code_4 : issue_slots_12_out_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_fu_code_5 = _T_185 ? issue_slots_13_out_uop_fu_code_5 : issue_slots_12_out_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_fu_code_6 = _T_185 ? issue_slots_13_out_uop_fu_code_6 : issue_slots_12_out_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_fu_code_7 = _T_185 ? issue_slots_13_out_uop_fu_code_7 : issue_slots_12_out_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_fu_code_8 = _T_185 ? issue_slots_13_out_uop_fu_code_8 : issue_slots_12_out_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_fu_code_9 = _T_185 ? issue_slots_13_out_uop_fu_code_9 : issue_slots_12_out_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_iq_type_0 = _T_185 ? issue_slots_13_out_uop_iq_type_0 : issue_slots_12_out_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_iq_type_1 = _T_185 ? issue_slots_13_out_uop_iq_type_1 : issue_slots_12_out_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_iq_type_2 = _T_185 ? issue_slots_13_out_uop_iq_type_2 : issue_slots_12_out_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_iq_type_3 = _T_185 ? issue_slots_13_out_uop_iq_type_3 : issue_slots_12_out_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_debug_pc = _T_185 ? issue_slots_13_out_uop_debug_pc : issue_slots_12_out_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_is_rvc = _T_185 ? issue_slots_13_out_uop_is_rvc : issue_slots_12_out_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_debug_inst = _T_185 ? issue_slots_13_out_uop_debug_inst : issue_slots_12_out_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_11_in_uop_bits_inst = _T_185 ? issue_slots_13_out_uop_inst : issue_slots_12_out_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign _issue_slots_11_clear_T = |shamts_oh_11;\t// @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49]\n assign issue_slots_11_clear = _issue_slots_11_clear_T;\t// @[issue-unit-age-ordered.scala:122:28, :199:49]\n wire _T_187 = shamts_oh_14 == 2'h2;\t// @[issue-unit-age-ordered.scala:158:23, :194:28]\n assign issue_slots_12_in_uop_valid = _T_187 ? issue_slots_14_will_be_valid : shamts_oh_13 == 2'h1 & issue_slots_13_will_be_valid;\t// @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37]\n assign issue_slots_12_in_uop_bits_debug_tsrc = _T_187 ? issue_slots_14_out_uop_debug_tsrc : issue_slots_13_out_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_debug_fsrc = _T_187 ? issue_slots_14_out_uop_debug_fsrc : issue_slots_13_out_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_bp_xcpt_if = _T_187 ? issue_slots_14_out_uop_bp_xcpt_if : issue_slots_13_out_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_bp_debug_if = _T_187 ? issue_slots_14_out_uop_bp_debug_if : issue_slots_13_out_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_xcpt_ma_if = _T_187 ? issue_slots_14_out_uop_xcpt_ma_if : issue_slots_13_out_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_xcpt_ae_if = _T_187 ? issue_slots_14_out_uop_xcpt_ae_if : issue_slots_13_out_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_xcpt_pf_if = _T_187 ? issue_slots_14_out_uop_xcpt_pf_if : issue_slots_13_out_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_fp_typ = _T_187 ? issue_slots_14_out_uop_fp_typ : issue_slots_13_out_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_fp_rm = _T_187 ? issue_slots_14_out_uop_fp_rm : issue_slots_13_out_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_fp_val = _T_187 ? issue_slots_14_out_uop_fp_val : issue_slots_13_out_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_fcn_op = _T_187 ? issue_slots_14_out_uop_fcn_op : issue_slots_13_out_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_fcn_dw = _T_187 ? issue_slots_14_out_uop_fcn_dw : issue_slots_13_out_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_frs3_en = _T_187 ? issue_slots_14_out_uop_frs3_en : issue_slots_13_out_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_lrs2_rtype = _T_187 ? issue_slots_14_out_uop_lrs2_rtype : issue_slots_13_out_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_lrs1_rtype = _T_187 ? issue_slots_14_out_uop_lrs1_rtype : issue_slots_13_out_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_dst_rtype = _T_187 ? issue_slots_14_out_uop_dst_rtype : issue_slots_13_out_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_lrs3 = _T_187 ? issue_slots_14_out_uop_lrs3 : issue_slots_13_out_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_lrs2 = _T_187 ? issue_slots_14_out_uop_lrs2 : issue_slots_13_out_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_lrs1 = _T_187 ? issue_slots_14_out_uop_lrs1 : issue_slots_13_out_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_ldst = _T_187 ? issue_slots_14_out_uop_ldst : issue_slots_13_out_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_ldst_is_rs1 = _T_187 ? issue_slots_14_out_uop_ldst_is_rs1 : issue_slots_13_out_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_csr_cmd = _T_187 ? issue_slots_14_out_uop_csr_cmd : issue_slots_13_out_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_flush_on_commit = _T_187 ? issue_slots_14_out_uop_flush_on_commit : issue_slots_13_out_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_is_unique = _T_187 ? issue_slots_14_out_uop_is_unique : issue_slots_13_out_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_uses_stq = _T_187 ? issue_slots_14_out_uop_uses_stq : issue_slots_13_out_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_uses_ldq = _T_187 ? issue_slots_14_out_uop_uses_ldq : issue_slots_13_out_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_mem_signed = _T_187 ? issue_slots_14_out_uop_mem_signed : issue_slots_13_out_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_mem_size = _T_187 ? issue_slots_14_out_uop_mem_size : issue_slots_13_out_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_mem_cmd = _T_187 ? issue_slots_14_out_uop_mem_cmd : issue_slots_13_out_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_exc_cause = _T_187 ? issue_slots_14_out_uop_exc_cause : issue_slots_13_out_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_exception = _T_187 ? issue_slots_14_out_uop_exception : issue_slots_13_out_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_stale_pdst = _T_187 ? issue_slots_14_out_uop_stale_pdst : issue_slots_13_out_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_ppred_busy = _T_187 ? issue_slots_14_out_uop_ppred_busy : issue_slots_13_out_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_prs3_busy = _T_187 ? issue_slots_14_out_uop_prs3_busy : issue_slots_13_out_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_prs2_busy = _T_187 ? issue_slots_14_out_uop_prs2_busy : issue_slots_13_out_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_prs1_busy = _T_187 ? issue_slots_14_out_uop_prs1_busy : issue_slots_13_out_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_ppred = _T_187 ? issue_slots_14_out_uop_ppred : issue_slots_13_out_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_prs3 = _T_187 ? issue_slots_14_out_uop_prs3 : issue_slots_13_out_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_prs2 = _T_187 ? issue_slots_14_out_uop_prs2 : issue_slots_13_out_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_prs1 = _T_187 ? issue_slots_14_out_uop_prs1 : issue_slots_13_out_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_pdst = _T_187 ? issue_slots_14_out_uop_pdst : issue_slots_13_out_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_rxq_idx = _T_187 ? issue_slots_14_out_uop_rxq_idx : issue_slots_13_out_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_stq_idx = _T_187 ? issue_slots_14_out_uop_stq_idx : issue_slots_13_out_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_ldq_idx = _T_187 ? issue_slots_14_out_uop_ldq_idx : issue_slots_13_out_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_rob_idx = _T_187 ? issue_slots_14_out_uop_rob_idx : issue_slots_13_out_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_fp_ctrl_vec = _T_187 ? issue_slots_14_out_uop_fp_ctrl_vec : issue_slots_13_out_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_fp_ctrl_wflags = _T_187 ? issue_slots_14_out_uop_fp_ctrl_wflags : issue_slots_13_out_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_fp_ctrl_sqrt = _T_187 ? issue_slots_14_out_uop_fp_ctrl_sqrt : issue_slots_13_out_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_fp_ctrl_div = _T_187 ? issue_slots_14_out_uop_fp_ctrl_div : issue_slots_13_out_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_fp_ctrl_fma = _T_187 ? issue_slots_14_out_uop_fp_ctrl_fma : issue_slots_13_out_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_fp_ctrl_fastpipe = _T_187 ? issue_slots_14_out_uop_fp_ctrl_fastpipe : issue_slots_13_out_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_fp_ctrl_toint = _T_187 ? issue_slots_14_out_uop_fp_ctrl_toint : issue_slots_13_out_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_fp_ctrl_fromint = _T_187 ? issue_slots_14_out_uop_fp_ctrl_fromint : issue_slots_13_out_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_fp_ctrl_typeTagOut = _T_187 ? issue_slots_14_out_uop_fp_ctrl_typeTagOut : issue_slots_13_out_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_fp_ctrl_typeTagIn = _T_187 ? issue_slots_14_out_uop_fp_ctrl_typeTagIn : issue_slots_13_out_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_fp_ctrl_swap23 = _T_187 ? issue_slots_14_out_uop_fp_ctrl_swap23 : issue_slots_13_out_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_fp_ctrl_swap12 = _T_187 ? issue_slots_14_out_uop_fp_ctrl_swap12 : issue_slots_13_out_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_fp_ctrl_ren3 = _T_187 ? issue_slots_14_out_uop_fp_ctrl_ren3 : issue_slots_13_out_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_fp_ctrl_ren2 = _T_187 ? issue_slots_14_out_uop_fp_ctrl_ren2 : issue_slots_13_out_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_fp_ctrl_ren1 = _T_187 ? issue_slots_14_out_uop_fp_ctrl_ren1 : issue_slots_13_out_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_fp_ctrl_wen = _T_187 ? issue_slots_14_out_uop_fp_ctrl_wen : issue_slots_13_out_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_fp_ctrl_ldst = _T_187 ? issue_slots_14_out_uop_fp_ctrl_ldst : issue_slots_13_out_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_op2_sel = _T_187 ? issue_slots_14_out_uop_op2_sel : issue_slots_13_out_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_op1_sel = _T_187 ? issue_slots_14_out_uop_op1_sel : issue_slots_13_out_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_imm_packed = _T_187 ? issue_slots_14_out_uop_imm_packed : issue_slots_13_out_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_pimm = _T_187 ? issue_slots_14_out_uop_pimm : issue_slots_13_out_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_imm_sel = _T_187 ? issue_slots_14_out_uop_imm_sel : issue_slots_13_out_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_imm_rename = _T_187 ? issue_slots_14_out_uop_imm_rename : issue_slots_13_out_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_taken = _T_187 ? issue_slots_14_out_uop_taken : issue_slots_13_out_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_pc_lob = _T_187 ? issue_slots_14_out_uop_pc_lob : issue_slots_13_out_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_edge_inst = _T_187 ? issue_slots_14_out_uop_edge_inst : issue_slots_13_out_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_ftq_idx = _T_187 ? issue_slots_14_out_uop_ftq_idx : issue_slots_13_out_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_is_mov = _T_187 ? issue_slots_14_out_uop_is_mov : issue_slots_13_out_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_is_rocc = _T_187 ? issue_slots_14_out_uop_is_rocc : issue_slots_13_out_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_is_sys_pc2epc = _T_187 ? issue_slots_14_out_uop_is_sys_pc2epc : issue_slots_13_out_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_is_eret = _T_187 ? issue_slots_14_out_uop_is_eret : issue_slots_13_out_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_is_amo = _T_187 ? issue_slots_14_out_uop_is_amo : issue_slots_13_out_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_is_sfence = _T_187 ? issue_slots_14_out_uop_is_sfence : issue_slots_13_out_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_is_fencei = _T_187 ? issue_slots_14_out_uop_is_fencei : issue_slots_13_out_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_is_fence = _T_187 ? issue_slots_14_out_uop_is_fence : issue_slots_13_out_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_is_sfb = _T_187 ? issue_slots_14_out_uop_is_sfb : issue_slots_13_out_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_br_type = _T_187 ? issue_slots_14_out_uop_br_type : issue_slots_13_out_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_br_tag = _T_187 ? issue_slots_14_out_uop_br_tag : issue_slots_13_out_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_br_mask = _T_187 ? issue_slots_14_out_uop_br_mask : issue_slots_13_out_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_dis_col_sel = _T_187 ? issue_slots_14_out_uop_dis_col_sel : issue_slots_13_out_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_iw_p3_bypass_hint = _T_187 ? issue_slots_14_out_uop_iw_p3_bypass_hint : issue_slots_13_out_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_iw_p2_bypass_hint = _T_187 ? issue_slots_14_out_uop_iw_p2_bypass_hint : issue_slots_13_out_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_iw_p1_bypass_hint = _T_187 ? issue_slots_14_out_uop_iw_p1_bypass_hint : issue_slots_13_out_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_iw_p2_speculative_child = _T_187 ? issue_slots_14_out_uop_iw_p2_speculative_child : issue_slots_13_out_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_iw_p1_speculative_child = _T_187 ? issue_slots_14_out_uop_iw_p1_speculative_child : issue_slots_13_out_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_iw_issued = _T_187 ? issue_slots_14_out_uop_iw_issued : issue_slots_13_out_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_fu_code_0 = _T_187 ? issue_slots_14_out_uop_fu_code_0 : issue_slots_13_out_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_fu_code_1 = _T_187 ? issue_slots_14_out_uop_fu_code_1 : issue_slots_13_out_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_fu_code_2 = _T_187 ? issue_slots_14_out_uop_fu_code_2 : issue_slots_13_out_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_fu_code_3 = _T_187 ? issue_slots_14_out_uop_fu_code_3 : issue_slots_13_out_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_fu_code_4 = _T_187 ? issue_slots_14_out_uop_fu_code_4 : issue_slots_13_out_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_fu_code_5 = _T_187 ? issue_slots_14_out_uop_fu_code_5 : issue_slots_13_out_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_fu_code_6 = _T_187 ? issue_slots_14_out_uop_fu_code_6 : issue_slots_13_out_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_fu_code_7 = _T_187 ? issue_slots_14_out_uop_fu_code_7 : issue_slots_13_out_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_fu_code_8 = _T_187 ? issue_slots_14_out_uop_fu_code_8 : issue_slots_13_out_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_fu_code_9 = _T_187 ? issue_slots_14_out_uop_fu_code_9 : issue_slots_13_out_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_iq_type_0 = _T_187 ? issue_slots_14_out_uop_iq_type_0 : issue_slots_13_out_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_iq_type_1 = _T_187 ? issue_slots_14_out_uop_iq_type_1 : issue_slots_13_out_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_iq_type_2 = _T_187 ? issue_slots_14_out_uop_iq_type_2 : issue_slots_13_out_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_iq_type_3 = _T_187 ? issue_slots_14_out_uop_iq_type_3 : issue_slots_13_out_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_debug_pc = _T_187 ? issue_slots_14_out_uop_debug_pc : issue_slots_13_out_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_is_rvc = _T_187 ? issue_slots_14_out_uop_is_rvc : issue_slots_13_out_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_debug_inst = _T_187 ? issue_slots_14_out_uop_debug_inst : issue_slots_13_out_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_12_in_uop_bits_inst = _T_187 ? issue_slots_14_out_uop_inst : issue_slots_13_out_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign _issue_slots_12_clear_T = |shamts_oh_12;\t// @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49]\n assign issue_slots_12_clear = _issue_slots_12_clear_T;\t// @[issue-unit-age-ordered.scala:122:28, :199:49]\n wire _T_189 = shamts_oh_15 == 2'h2;\t// @[issue-unit-age-ordered.scala:158:23, :194:28]\n assign issue_slots_13_in_uop_valid = _T_189 ? issue_slots_15_will_be_valid : shamts_oh_14 == 2'h1 & issue_slots_14_will_be_valid;\t// @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37]\n assign issue_slots_13_in_uop_bits_debug_tsrc = _T_189 ? issue_slots_15_out_uop_debug_tsrc : issue_slots_14_out_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_debug_fsrc = _T_189 ? issue_slots_15_out_uop_debug_fsrc : issue_slots_14_out_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_bp_xcpt_if = _T_189 ? issue_slots_15_out_uop_bp_xcpt_if : issue_slots_14_out_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_bp_debug_if = _T_189 ? issue_slots_15_out_uop_bp_debug_if : issue_slots_14_out_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_xcpt_ma_if = _T_189 ? issue_slots_15_out_uop_xcpt_ma_if : issue_slots_14_out_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_xcpt_ae_if = _T_189 ? issue_slots_15_out_uop_xcpt_ae_if : issue_slots_14_out_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_xcpt_pf_if = _T_189 ? issue_slots_15_out_uop_xcpt_pf_if : issue_slots_14_out_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_fp_typ = _T_189 ? issue_slots_15_out_uop_fp_typ : issue_slots_14_out_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_fp_rm = _T_189 ? issue_slots_15_out_uop_fp_rm : issue_slots_14_out_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_fp_val = _T_189 ? issue_slots_15_out_uop_fp_val : issue_slots_14_out_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_fcn_op = _T_189 ? issue_slots_15_out_uop_fcn_op : issue_slots_14_out_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_fcn_dw = _T_189 ? issue_slots_15_out_uop_fcn_dw : issue_slots_14_out_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_frs3_en = _T_189 ? issue_slots_15_out_uop_frs3_en : issue_slots_14_out_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_lrs2_rtype = _T_189 ? issue_slots_15_out_uop_lrs2_rtype : issue_slots_14_out_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_lrs1_rtype = _T_189 ? issue_slots_15_out_uop_lrs1_rtype : issue_slots_14_out_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_dst_rtype = _T_189 ? issue_slots_15_out_uop_dst_rtype : issue_slots_14_out_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_lrs3 = _T_189 ? issue_slots_15_out_uop_lrs3 : issue_slots_14_out_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_lrs2 = _T_189 ? issue_slots_15_out_uop_lrs2 : issue_slots_14_out_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_lrs1 = _T_189 ? issue_slots_15_out_uop_lrs1 : issue_slots_14_out_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_ldst = _T_189 ? issue_slots_15_out_uop_ldst : issue_slots_14_out_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_ldst_is_rs1 = _T_189 ? issue_slots_15_out_uop_ldst_is_rs1 : issue_slots_14_out_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_csr_cmd = _T_189 ? issue_slots_15_out_uop_csr_cmd : issue_slots_14_out_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_flush_on_commit = _T_189 ? issue_slots_15_out_uop_flush_on_commit : issue_slots_14_out_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_is_unique = _T_189 ? issue_slots_15_out_uop_is_unique : issue_slots_14_out_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_uses_stq = _T_189 ? issue_slots_15_out_uop_uses_stq : issue_slots_14_out_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_uses_ldq = _T_189 ? issue_slots_15_out_uop_uses_ldq : issue_slots_14_out_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_mem_signed = _T_189 ? issue_slots_15_out_uop_mem_signed : issue_slots_14_out_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_mem_size = _T_189 ? issue_slots_15_out_uop_mem_size : issue_slots_14_out_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_mem_cmd = _T_189 ? issue_slots_15_out_uop_mem_cmd : issue_slots_14_out_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_exc_cause = _T_189 ? issue_slots_15_out_uop_exc_cause : issue_slots_14_out_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_exception = _T_189 ? issue_slots_15_out_uop_exception : issue_slots_14_out_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_stale_pdst = _T_189 ? issue_slots_15_out_uop_stale_pdst : issue_slots_14_out_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_ppred_busy = _T_189 ? issue_slots_15_out_uop_ppred_busy : issue_slots_14_out_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_prs3_busy = _T_189 ? issue_slots_15_out_uop_prs3_busy : issue_slots_14_out_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_prs2_busy = _T_189 ? issue_slots_15_out_uop_prs2_busy : issue_slots_14_out_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_prs1_busy = _T_189 ? issue_slots_15_out_uop_prs1_busy : issue_slots_14_out_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_ppred = _T_189 ? issue_slots_15_out_uop_ppred : issue_slots_14_out_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_prs3 = _T_189 ? issue_slots_15_out_uop_prs3 : issue_slots_14_out_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_prs2 = _T_189 ? issue_slots_15_out_uop_prs2 : issue_slots_14_out_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_prs1 = _T_189 ? issue_slots_15_out_uop_prs1 : issue_slots_14_out_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_pdst = _T_189 ? issue_slots_15_out_uop_pdst : issue_slots_14_out_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_rxq_idx = _T_189 ? issue_slots_15_out_uop_rxq_idx : issue_slots_14_out_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_stq_idx = _T_189 ? issue_slots_15_out_uop_stq_idx : issue_slots_14_out_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_ldq_idx = _T_189 ? issue_slots_15_out_uop_ldq_idx : issue_slots_14_out_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_rob_idx = _T_189 ? issue_slots_15_out_uop_rob_idx : issue_slots_14_out_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_fp_ctrl_vec = _T_189 ? issue_slots_15_out_uop_fp_ctrl_vec : issue_slots_14_out_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_fp_ctrl_wflags = _T_189 ? issue_slots_15_out_uop_fp_ctrl_wflags : issue_slots_14_out_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_fp_ctrl_sqrt = _T_189 ? issue_slots_15_out_uop_fp_ctrl_sqrt : issue_slots_14_out_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_fp_ctrl_div = _T_189 ? issue_slots_15_out_uop_fp_ctrl_div : issue_slots_14_out_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_fp_ctrl_fma = _T_189 ? issue_slots_15_out_uop_fp_ctrl_fma : issue_slots_14_out_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_fp_ctrl_fastpipe = _T_189 ? issue_slots_15_out_uop_fp_ctrl_fastpipe : issue_slots_14_out_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_fp_ctrl_toint = _T_189 ? issue_slots_15_out_uop_fp_ctrl_toint : issue_slots_14_out_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_fp_ctrl_fromint = _T_189 ? issue_slots_15_out_uop_fp_ctrl_fromint : issue_slots_14_out_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_fp_ctrl_typeTagOut = _T_189 ? issue_slots_15_out_uop_fp_ctrl_typeTagOut : issue_slots_14_out_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_fp_ctrl_typeTagIn = _T_189 ? issue_slots_15_out_uop_fp_ctrl_typeTagIn : issue_slots_14_out_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_fp_ctrl_swap23 = _T_189 ? issue_slots_15_out_uop_fp_ctrl_swap23 : issue_slots_14_out_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_fp_ctrl_swap12 = _T_189 ? issue_slots_15_out_uop_fp_ctrl_swap12 : issue_slots_14_out_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_fp_ctrl_ren3 = _T_189 ? issue_slots_15_out_uop_fp_ctrl_ren3 : issue_slots_14_out_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_fp_ctrl_ren2 = _T_189 ? issue_slots_15_out_uop_fp_ctrl_ren2 : issue_slots_14_out_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_fp_ctrl_ren1 = _T_189 ? issue_slots_15_out_uop_fp_ctrl_ren1 : issue_slots_14_out_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_fp_ctrl_wen = _T_189 ? issue_slots_15_out_uop_fp_ctrl_wen : issue_slots_14_out_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_fp_ctrl_ldst = _T_189 ? issue_slots_15_out_uop_fp_ctrl_ldst : issue_slots_14_out_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_op2_sel = _T_189 ? issue_slots_15_out_uop_op2_sel : issue_slots_14_out_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_op1_sel = _T_189 ? issue_slots_15_out_uop_op1_sel : issue_slots_14_out_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_imm_packed = _T_189 ? issue_slots_15_out_uop_imm_packed : issue_slots_14_out_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_pimm = _T_189 ? issue_slots_15_out_uop_pimm : issue_slots_14_out_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_imm_sel = _T_189 ? issue_slots_15_out_uop_imm_sel : issue_slots_14_out_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_imm_rename = _T_189 ? issue_slots_15_out_uop_imm_rename : issue_slots_14_out_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_taken = _T_189 ? issue_slots_15_out_uop_taken : issue_slots_14_out_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_pc_lob = _T_189 ? issue_slots_15_out_uop_pc_lob : issue_slots_14_out_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_edge_inst = _T_189 ? issue_slots_15_out_uop_edge_inst : issue_slots_14_out_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_ftq_idx = _T_189 ? issue_slots_15_out_uop_ftq_idx : issue_slots_14_out_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_is_mov = _T_189 ? issue_slots_15_out_uop_is_mov : issue_slots_14_out_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_is_rocc = _T_189 ? issue_slots_15_out_uop_is_rocc : issue_slots_14_out_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_is_sys_pc2epc = _T_189 ? issue_slots_15_out_uop_is_sys_pc2epc : issue_slots_14_out_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_is_eret = _T_189 ? issue_slots_15_out_uop_is_eret : issue_slots_14_out_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_is_amo = _T_189 ? issue_slots_15_out_uop_is_amo : issue_slots_14_out_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_is_sfence = _T_189 ? issue_slots_15_out_uop_is_sfence : issue_slots_14_out_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_is_fencei = _T_189 ? issue_slots_15_out_uop_is_fencei : issue_slots_14_out_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_is_fence = _T_189 ? issue_slots_15_out_uop_is_fence : issue_slots_14_out_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_is_sfb = _T_189 ? issue_slots_15_out_uop_is_sfb : issue_slots_14_out_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_br_type = _T_189 ? issue_slots_15_out_uop_br_type : issue_slots_14_out_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_br_tag = _T_189 ? issue_slots_15_out_uop_br_tag : issue_slots_14_out_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_br_mask = _T_189 ? issue_slots_15_out_uop_br_mask : issue_slots_14_out_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_dis_col_sel = _T_189 ? issue_slots_15_out_uop_dis_col_sel : issue_slots_14_out_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_iw_p3_bypass_hint = _T_189 ? issue_slots_15_out_uop_iw_p3_bypass_hint : issue_slots_14_out_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_iw_p2_bypass_hint = _T_189 ? issue_slots_15_out_uop_iw_p2_bypass_hint : issue_slots_14_out_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_iw_p1_bypass_hint = _T_189 ? issue_slots_15_out_uop_iw_p1_bypass_hint : issue_slots_14_out_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_iw_p2_speculative_child = _T_189 ? issue_slots_15_out_uop_iw_p2_speculative_child : issue_slots_14_out_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_iw_p1_speculative_child = _T_189 ? issue_slots_15_out_uop_iw_p1_speculative_child : issue_slots_14_out_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_iw_issued = _T_189 ? issue_slots_15_out_uop_iw_issued : issue_slots_14_out_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_fu_code_0 = _T_189 ? issue_slots_15_out_uop_fu_code_0 : issue_slots_14_out_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_fu_code_1 = _T_189 ? issue_slots_15_out_uop_fu_code_1 : issue_slots_14_out_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_fu_code_2 = _T_189 ? issue_slots_15_out_uop_fu_code_2 : issue_slots_14_out_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_fu_code_3 = _T_189 ? issue_slots_15_out_uop_fu_code_3 : issue_slots_14_out_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_fu_code_4 = _T_189 ? issue_slots_15_out_uop_fu_code_4 : issue_slots_14_out_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_fu_code_5 = _T_189 ? issue_slots_15_out_uop_fu_code_5 : issue_slots_14_out_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_fu_code_6 = _T_189 ? issue_slots_15_out_uop_fu_code_6 : issue_slots_14_out_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_fu_code_7 = _T_189 ? issue_slots_15_out_uop_fu_code_7 : issue_slots_14_out_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_fu_code_8 = _T_189 ? issue_slots_15_out_uop_fu_code_8 : issue_slots_14_out_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_fu_code_9 = _T_189 ? issue_slots_15_out_uop_fu_code_9 : issue_slots_14_out_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_iq_type_0 = _T_189 ? issue_slots_15_out_uop_iq_type_0 : issue_slots_14_out_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_iq_type_1 = _T_189 ? issue_slots_15_out_uop_iq_type_1 : issue_slots_14_out_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_iq_type_2 = _T_189 ? issue_slots_15_out_uop_iq_type_2 : issue_slots_14_out_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_iq_type_3 = _T_189 ? issue_slots_15_out_uop_iq_type_3 : issue_slots_14_out_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_debug_pc = _T_189 ? issue_slots_15_out_uop_debug_pc : issue_slots_14_out_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_is_rvc = _T_189 ? issue_slots_15_out_uop_is_rvc : issue_slots_14_out_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_debug_inst = _T_189 ? issue_slots_15_out_uop_debug_inst : issue_slots_14_out_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_13_in_uop_bits_inst = _T_189 ? issue_slots_15_out_uop_inst : issue_slots_14_out_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign _issue_slots_13_clear_T = |shamts_oh_13;\t// @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49]\n assign issue_slots_13_clear = _issue_slots_13_clear_T;\t// @[issue-unit-age-ordered.scala:122:28, :199:49]\n wire _T_191 = shamts_oh_16 == 2'h2;\t// @[issue-unit-age-ordered.scala:158:23, :194:28]\n assign issue_slots_14_in_uop_valid = _T_191 ? issue_slots_16_will_be_valid : shamts_oh_15 == 2'h1 & issue_slots_15_will_be_valid;\t// @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37]\n assign issue_slots_14_in_uop_bits_debug_tsrc = _T_191 ? issue_slots_16_out_uop_debug_tsrc : issue_slots_15_out_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_debug_fsrc = _T_191 ? issue_slots_16_out_uop_debug_fsrc : issue_slots_15_out_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_bp_xcpt_if = _T_191 ? issue_slots_16_out_uop_bp_xcpt_if : issue_slots_15_out_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_bp_debug_if = _T_191 ? issue_slots_16_out_uop_bp_debug_if : issue_slots_15_out_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_xcpt_ma_if = _T_191 ? issue_slots_16_out_uop_xcpt_ma_if : issue_slots_15_out_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_xcpt_ae_if = _T_191 ? issue_slots_16_out_uop_xcpt_ae_if : issue_slots_15_out_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_xcpt_pf_if = _T_191 ? issue_slots_16_out_uop_xcpt_pf_if : issue_slots_15_out_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_fp_typ = _T_191 ? issue_slots_16_out_uop_fp_typ : issue_slots_15_out_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_fp_rm = _T_191 ? issue_slots_16_out_uop_fp_rm : issue_slots_15_out_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_fp_val = _T_191 ? issue_slots_16_out_uop_fp_val : issue_slots_15_out_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_fcn_op = _T_191 ? issue_slots_16_out_uop_fcn_op : issue_slots_15_out_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_fcn_dw = _T_191 ? issue_slots_16_out_uop_fcn_dw : issue_slots_15_out_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_frs3_en = _T_191 ? issue_slots_16_out_uop_frs3_en : issue_slots_15_out_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_lrs2_rtype = _T_191 ? issue_slots_16_out_uop_lrs2_rtype : issue_slots_15_out_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_lrs1_rtype = _T_191 ? issue_slots_16_out_uop_lrs1_rtype : issue_slots_15_out_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_dst_rtype = _T_191 ? issue_slots_16_out_uop_dst_rtype : issue_slots_15_out_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_lrs3 = _T_191 ? issue_slots_16_out_uop_lrs3 : issue_slots_15_out_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_lrs2 = _T_191 ? issue_slots_16_out_uop_lrs2 : issue_slots_15_out_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_lrs1 = _T_191 ? issue_slots_16_out_uop_lrs1 : issue_slots_15_out_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_ldst = _T_191 ? issue_slots_16_out_uop_ldst : issue_slots_15_out_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_ldst_is_rs1 = _T_191 ? issue_slots_16_out_uop_ldst_is_rs1 : issue_slots_15_out_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_csr_cmd = _T_191 ? issue_slots_16_out_uop_csr_cmd : issue_slots_15_out_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_flush_on_commit = _T_191 ? issue_slots_16_out_uop_flush_on_commit : issue_slots_15_out_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_is_unique = _T_191 ? issue_slots_16_out_uop_is_unique : issue_slots_15_out_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_uses_stq = _T_191 ? issue_slots_16_out_uop_uses_stq : issue_slots_15_out_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_uses_ldq = _T_191 ? issue_slots_16_out_uop_uses_ldq : issue_slots_15_out_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_mem_signed = _T_191 ? issue_slots_16_out_uop_mem_signed : issue_slots_15_out_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_mem_size = _T_191 ? issue_slots_16_out_uop_mem_size : issue_slots_15_out_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_mem_cmd = _T_191 ? issue_slots_16_out_uop_mem_cmd : issue_slots_15_out_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_exc_cause = _T_191 ? issue_slots_16_out_uop_exc_cause : issue_slots_15_out_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_exception = _T_191 ? issue_slots_16_out_uop_exception : issue_slots_15_out_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_stale_pdst = _T_191 ? issue_slots_16_out_uop_stale_pdst : issue_slots_15_out_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_ppred_busy = _T_191 ? issue_slots_16_out_uop_ppred_busy : issue_slots_15_out_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_prs3_busy = _T_191 ? issue_slots_16_out_uop_prs3_busy : issue_slots_15_out_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_prs2_busy = _T_191 ? issue_slots_16_out_uop_prs2_busy : issue_slots_15_out_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_prs1_busy = _T_191 ? issue_slots_16_out_uop_prs1_busy : issue_slots_15_out_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_ppred = _T_191 ? issue_slots_16_out_uop_ppred : issue_slots_15_out_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_prs3 = _T_191 ? issue_slots_16_out_uop_prs3 : issue_slots_15_out_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_prs2 = _T_191 ? issue_slots_16_out_uop_prs2 : issue_slots_15_out_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_prs1 = _T_191 ? issue_slots_16_out_uop_prs1 : issue_slots_15_out_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_pdst = _T_191 ? issue_slots_16_out_uop_pdst : issue_slots_15_out_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_rxq_idx = _T_191 ? issue_slots_16_out_uop_rxq_idx : issue_slots_15_out_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_stq_idx = _T_191 ? issue_slots_16_out_uop_stq_idx : issue_slots_15_out_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_ldq_idx = _T_191 ? issue_slots_16_out_uop_ldq_idx : issue_slots_15_out_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_rob_idx = _T_191 ? issue_slots_16_out_uop_rob_idx : issue_slots_15_out_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_fp_ctrl_vec = _T_191 ? issue_slots_16_out_uop_fp_ctrl_vec : issue_slots_15_out_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_fp_ctrl_wflags = _T_191 ? issue_slots_16_out_uop_fp_ctrl_wflags : issue_slots_15_out_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_fp_ctrl_sqrt = _T_191 ? issue_slots_16_out_uop_fp_ctrl_sqrt : issue_slots_15_out_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_fp_ctrl_div = _T_191 ? issue_slots_16_out_uop_fp_ctrl_div : issue_slots_15_out_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_fp_ctrl_fma = _T_191 ? issue_slots_16_out_uop_fp_ctrl_fma : issue_slots_15_out_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_fp_ctrl_fastpipe = _T_191 ? issue_slots_16_out_uop_fp_ctrl_fastpipe : issue_slots_15_out_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_fp_ctrl_toint = _T_191 ? issue_slots_16_out_uop_fp_ctrl_toint : issue_slots_15_out_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_fp_ctrl_fromint = _T_191 ? issue_slots_16_out_uop_fp_ctrl_fromint : issue_slots_15_out_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_fp_ctrl_typeTagOut = _T_191 ? issue_slots_16_out_uop_fp_ctrl_typeTagOut : issue_slots_15_out_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_fp_ctrl_typeTagIn = _T_191 ? issue_slots_16_out_uop_fp_ctrl_typeTagIn : issue_slots_15_out_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_fp_ctrl_swap23 = _T_191 ? issue_slots_16_out_uop_fp_ctrl_swap23 : issue_slots_15_out_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_fp_ctrl_swap12 = _T_191 ? issue_slots_16_out_uop_fp_ctrl_swap12 : issue_slots_15_out_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_fp_ctrl_ren3 = _T_191 ? issue_slots_16_out_uop_fp_ctrl_ren3 : issue_slots_15_out_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_fp_ctrl_ren2 = _T_191 ? issue_slots_16_out_uop_fp_ctrl_ren2 : issue_slots_15_out_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_fp_ctrl_ren1 = _T_191 ? issue_slots_16_out_uop_fp_ctrl_ren1 : issue_slots_15_out_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_fp_ctrl_wen = _T_191 ? issue_slots_16_out_uop_fp_ctrl_wen : issue_slots_15_out_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_fp_ctrl_ldst = _T_191 ? issue_slots_16_out_uop_fp_ctrl_ldst : issue_slots_15_out_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_op2_sel = _T_191 ? issue_slots_16_out_uop_op2_sel : issue_slots_15_out_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_op1_sel = _T_191 ? issue_slots_16_out_uop_op1_sel : issue_slots_15_out_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_imm_packed = _T_191 ? issue_slots_16_out_uop_imm_packed : issue_slots_15_out_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_pimm = _T_191 ? issue_slots_16_out_uop_pimm : issue_slots_15_out_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_imm_sel = _T_191 ? issue_slots_16_out_uop_imm_sel : issue_slots_15_out_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_imm_rename = _T_191 ? issue_slots_16_out_uop_imm_rename : issue_slots_15_out_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_taken = _T_191 ? issue_slots_16_out_uop_taken : issue_slots_15_out_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_pc_lob = _T_191 ? issue_slots_16_out_uop_pc_lob : issue_slots_15_out_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_edge_inst = _T_191 ? issue_slots_16_out_uop_edge_inst : issue_slots_15_out_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_ftq_idx = _T_191 ? issue_slots_16_out_uop_ftq_idx : issue_slots_15_out_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_is_mov = _T_191 ? issue_slots_16_out_uop_is_mov : issue_slots_15_out_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_is_rocc = _T_191 ? issue_slots_16_out_uop_is_rocc : issue_slots_15_out_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_is_sys_pc2epc = _T_191 ? issue_slots_16_out_uop_is_sys_pc2epc : issue_slots_15_out_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_is_eret = _T_191 ? issue_slots_16_out_uop_is_eret : issue_slots_15_out_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_is_amo = _T_191 ? issue_slots_16_out_uop_is_amo : issue_slots_15_out_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_is_sfence = _T_191 ? issue_slots_16_out_uop_is_sfence : issue_slots_15_out_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_is_fencei = _T_191 ? issue_slots_16_out_uop_is_fencei : issue_slots_15_out_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_is_fence = _T_191 ? issue_slots_16_out_uop_is_fence : issue_slots_15_out_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_is_sfb = _T_191 ? issue_slots_16_out_uop_is_sfb : issue_slots_15_out_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_br_type = _T_191 ? issue_slots_16_out_uop_br_type : issue_slots_15_out_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_br_tag = _T_191 ? issue_slots_16_out_uop_br_tag : issue_slots_15_out_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_br_mask = _T_191 ? issue_slots_16_out_uop_br_mask : issue_slots_15_out_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_dis_col_sel = _T_191 ? issue_slots_16_out_uop_dis_col_sel : issue_slots_15_out_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_iw_p3_bypass_hint = _T_191 ? issue_slots_16_out_uop_iw_p3_bypass_hint : issue_slots_15_out_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_iw_p2_bypass_hint = _T_191 ? issue_slots_16_out_uop_iw_p2_bypass_hint : issue_slots_15_out_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_iw_p1_bypass_hint = _T_191 ? issue_slots_16_out_uop_iw_p1_bypass_hint : issue_slots_15_out_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_iw_p2_speculative_child = _T_191 ? issue_slots_16_out_uop_iw_p2_speculative_child : issue_slots_15_out_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_iw_p1_speculative_child = _T_191 ? issue_slots_16_out_uop_iw_p1_speculative_child : issue_slots_15_out_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_iw_issued = _T_191 ? issue_slots_16_out_uop_iw_issued : issue_slots_15_out_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_fu_code_0 = _T_191 ? issue_slots_16_out_uop_fu_code_0 : issue_slots_15_out_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_fu_code_1 = _T_191 ? issue_slots_16_out_uop_fu_code_1 : issue_slots_15_out_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_fu_code_2 = _T_191 ? issue_slots_16_out_uop_fu_code_2 : issue_slots_15_out_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_fu_code_3 = _T_191 ? issue_slots_16_out_uop_fu_code_3 : issue_slots_15_out_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_fu_code_4 = _T_191 ? issue_slots_16_out_uop_fu_code_4 : issue_slots_15_out_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_fu_code_5 = _T_191 ? issue_slots_16_out_uop_fu_code_5 : issue_slots_15_out_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_fu_code_6 = _T_191 ? issue_slots_16_out_uop_fu_code_6 : issue_slots_15_out_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_fu_code_7 = _T_191 ? issue_slots_16_out_uop_fu_code_7 : issue_slots_15_out_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_fu_code_8 = _T_191 ? issue_slots_16_out_uop_fu_code_8 : issue_slots_15_out_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_fu_code_9 = _T_191 ? issue_slots_16_out_uop_fu_code_9 : issue_slots_15_out_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_iq_type_0 = _T_191 ? issue_slots_16_out_uop_iq_type_0 : issue_slots_15_out_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_iq_type_1 = _T_191 ? issue_slots_16_out_uop_iq_type_1 : issue_slots_15_out_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_iq_type_2 = _T_191 ? issue_slots_16_out_uop_iq_type_2 : issue_slots_15_out_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_iq_type_3 = _T_191 ? issue_slots_16_out_uop_iq_type_3 : issue_slots_15_out_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_debug_pc = _T_191 ? issue_slots_16_out_uop_debug_pc : issue_slots_15_out_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_is_rvc = _T_191 ? issue_slots_16_out_uop_is_rvc : issue_slots_15_out_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_debug_inst = _T_191 ? issue_slots_16_out_uop_debug_inst : issue_slots_15_out_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_14_in_uop_bits_inst = _T_191 ? issue_slots_16_out_uop_inst : issue_slots_15_out_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign _issue_slots_14_clear_T = |shamts_oh_14;\t// @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49]\n assign issue_slots_14_clear = _issue_slots_14_clear_T;\t// @[issue-unit-age-ordered.scala:122:28, :199:49]\n wire _T_193 = shamts_oh_17 == 2'h2;\t// @[issue-unit-age-ordered.scala:158:23, :194:28]\n assign issue_slots_15_in_uop_valid = _T_193 ? issue_slots_17_will_be_valid : shamts_oh_16 == 2'h1 & issue_slots_16_will_be_valid;\t// @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37]\n assign issue_slots_15_in_uop_bits_debug_tsrc = _T_193 ? issue_slots_17_out_uop_debug_tsrc : issue_slots_16_out_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_debug_fsrc = _T_193 ? issue_slots_17_out_uop_debug_fsrc : issue_slots_16_out_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_bp_xcpt_if = _T_193 ? issue_slots_17_out_uop_bp_xcpt_if : issue_slots_16_out_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_bp_debug_if = _T_193 ? issue_slots_17_out_uop_bp_debug_if : issue_slots_16_out_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_xcpt_ma_if = _T_193 ? issue_slots_17_out_uop_xcpt_ma_if : issue_slots_16_out_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_xcpt_ae_if = _T_193 ? issue_slots_17_out_uop_xcpt_ae_if : issue_slots_16_out_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_xcpt_pf_if = _T_193 ? issue_slots_17_out_uop_xcpt_pf_if : issue_slots_16_out_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_fp_typ = _T_193 ? issue_slots_17_out_uop_fp_typ : issue_slots_16_out_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_fp_rm = _T_193 ? issue_slots_17_out_uop_fp_rm : issue_slots_16_out_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_fp_val = _T_193 ? issue_slots_17_out_uop_fp_val : issue_slots_16_out_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_fcn_op = _T_193 ? issue_slots_17_out_uop_fcn_op : issue_slots_16_out_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_fcn_dw = _T_193 ? issue_slots_17_out_uop_fcn_dw : issue_slots_16_out_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_frs3_en = _T_193 ? issue_slots_17_out_uop_frs3_en : issue_slots_16_out_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_lrs2_rtype = _T_193 ? issue_slots_17_out_uop_lrs2_rtype : issue_slots_16_out_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_lrs1_rtype = _T_193 ? issue_slots_17_out_uop_lrs1_rtype : issue_slots_16_out_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_dst_rtype = _T_193 ? issue_slots_17_out_uop_dst_rtype : issue_slots_16_out_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_lrs3 = _T_193 ? issue_slots_17_out_uop_lrs3 : issue_slots_16_out_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_lrs2 = _T_193 ? issue_slots_17_out_uop_lrs2 : issue_slots_16_out_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_lrs1 = _T_193 ? issue_slots_17_out_uop_lrs1 : issue_slots_16_out_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_ldst = _T_193 ? issue_slots_17_out_uop_ldst : issue_slots_16_out_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_ldst_is_rs1 = _T_193 ? issue_slots_17_out_uop_ldst_is_rs1 : issue_slots_16_out_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_csr_cmd = _T_193 ? issue_slots_17_out_uop_csr_cmd : issue_slots_16_out_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_flush_on_commit = _T_193 ? issue_slots_17_out_uop_flush_on_commit : issue_slots_16_out_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_is_unique = _T_193 ? issue_slots_17_out_uop_is_unique : issue_slots_16_out_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_uses_stq = _T_193 ? issue_slots_17_out_uop_uses_stq : issue_slots_16_out_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_uses_ldq = _T_193 ? issue_slots_17_out_uop_uses_ldq : issue_slots_16_out_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_mem_signed = _T_193 ? issue_slots_17_out_uop_mem_signed : issue_slots_16_out_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_mem_size = _T_193 ? issue_slots_17_out_uop_mem_size : issue_slots_16_out_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_mem_cmd = _T_193 ? issue_slots_17_out_uop_mem_cmd : issue_slots_16_out_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_exc_cause = _T_193 ? issue_slots_17_out_uop_exc_cause : issue_slots_16_out_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_exception = _T_193 ? issue_slots_17_out_uop_exception : issue_slots_16_out_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_stale_pdst = _T_193 ? issue_slots_17_out_uop_stale_pdst : issue_slots_16_out_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_ppred_busy = _T_193 ? issue_slots_17_out_uop_ppred_busy : issue_slots_16_out_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_prs3_busy = _T_193 ? issue_slots_17_out_uop_prs3_busy : issue_slots_16_out_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_prs2_busy = _T_193 ? issue_slots_17_out_uop_prs2_busy : issue_slots_16_out_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_prs1_busy = _T_193 ? issue_slots_17_out_uop_prs1_busy : issue_slots_16_out_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_ppred = _T_193 ? issue_slots_17_out_uop_ppred : issue_slots_16_out_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_prs3 = _T_193 ? issue_slots_17_out_uop_prs3 : issue_slots_16_out_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_prs2 = _T_193 ? issue_slots_17_out_uop_prs2 : issue_slots_16_out_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_prs1 = _T_193 ? issue_slots_17_out_uop_prs1 : issue_slots_16_out_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_pdst = _T_193 ? issue_slots_17_out_uop_pdst : issue_slots_16_out_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_rxq_idx = _T_193 ? issue_slots_17_out_uop_rxq_idx : issue_slots_16_out_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_stq_idx = _T_193 ? issue_slots_17_out_uop_stq_idx : issue_slots_16_out_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_ldq_idx = _T_193 ? issue_slots_17_out_uop_ldq_idx : issue_slots_16_out_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_rob_idx = _T_193 ? issue_slots_17_out_uop_rob_idx : issue_slots_16_out_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_fp_ctrl_vec = _T_193 ? issue_slots_17_out_uop_fp_ctrl_vec : issue_slots_16_out_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_fp_ctrl_wflags = _T_193 ? issue_slots_17_out_uop_fp_ctrl_wflags : issue_slots_16_out_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_fp_ctrl_sqrt = _T_193 ? issue_slots_17_out_uop_fp_ctrl_sqrt : issue_slots_16_out_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_fp_ctrl_div = _T_193 ? issue_slots_17_out_uop_fp_ctrl_div : issue_slots_16_out_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_fp_ctrl_fma = _T_193 ? issue_slots_17_out_uop_fp_ctrl_fma : issue_slots_16_out_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_fp_ctrl_fastpipe = _T_193 ? issue_slots_17_out_uop_fp_ctrl_fastpipe : issue_slots_16_out_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_fp_ctrl_toint = _T_193 ? issue_slots_17_out_uop_fp_ctrl_toint : issue_slots_16_out_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_fp_ctrl_fromint = _T_193 ? issue_slots_17_out_uop_fp_ctrl_fromint : issue_slots_16_out_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_fp_ctrl_typeTagOut = _T_193 ? issue_slots_17_out_uop_fp_ctrl_typeTagOut : issue_slots_16_out_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_fp_ctrl_typeTagIn = _T_193 ? issue_slots_17_out_uop_fp_ctrl_typeTagIn : issue_slots_16_out_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_fp_ctrl_swap23 = _T_193 ? issue_slots_17_out_uop_fp_ctrl_swap23 : issue_slots_16_out_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_fp_ctrl_swap12 = _T_193 ? issue_slots_17_out_uop_fp_ctrl_swap12 : issue_slots_16_out_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_fp_ctrl_ren3 = _T_193 ? issue_slots_17_out_uop_fp_ctrl_ren3 : issue_slots_16_out_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_fp_ctrl_ren2 = _T_193 ? issue_slots_17_out_uop_fp_ctrl_ren2 : issue_slots_16_out_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_fp_ctrl_ren1 = _T_193 ? issue_slots_17_out_uop_fp_ctrl_ren1 : issue_slots_16_out_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_fp_ctrl_wen = _T_193 ? issue_slots_17_out_uop_fp_ctrl_wen : issue_slots_16_out_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_fp_ctrl_ldst = _T_193 ? issue_slots_17_out_uop_fp_ctrl_ldst : issue_slots_16_out_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_op2_sel = _T_193 ? issue_slots_17_out_uop_op2_sel : issue_slots_16_out_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_op1_sel = _T_193 ? issue_slots_17_out_uop_op1_sel : issue_slots_16_out_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_imm_packed = _T_193 ? issue_slots_17_out_uop_imm_packed : issue_slots_16_out_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_pimm = _T_193 ? issue_slots_17_out_uop_pimm : issue_slots_16_out_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_imm_sel = _T_193 ? issue_slots_17_out_uop_imm_sel : issue_slots_16_out_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_imm_rename = _T_193 ? issue_slots_17_out_uop_imm_rename : issue_slots_16_out_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_taken = _T_193 ? issue_slots_17_out_uop_taken : issue_slots_16_out_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_pc_lob = _T_193 ? issue_slots_17_out_uop_pc_lob : issue_slots_16_out_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_edge_inst = _T_193 ? issue_slots_17_out_uop_edge_inst : issue_slots_16_out_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_ftq_idx = _T_193 ? issue_slots_17_out_uop_ftq_idx : issue_slots_16_out_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_is_mov = _T_193 ? issue_slots_17_out_uop_is_mov : issue_slots_16_out_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_is_rocc = _T_193 ? issue_slots_17_out_uop_is_rocc : issue_slots_16_out_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_is_sys_pc2epc = _T_193 ? issue_slots_17_out_uop_is_sys_pc2epc : issue_slots_16_out_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_is_eret = _T_193 ? issue_slots_17_out_uop_is_eret : issue_slots_16_out_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_is_amo = _T_193 ? issue_slots_17_out_uop_is_amo : issue_slots_16_out_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_is_sfence = _T_193 ? issue_slots_17_out_uop_is_sfence : issue_slots_16_out_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_is_fencei = _T_193 ? issue_slots_17_out_uop_is_fencei : issue_slots_16_out_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_is_fence = _T_193 ? issue_slots_17_out_uop_is_fence : issue_slots_16_out_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_is_sfb = _T_193 ? issue_slots_17_out_uop_is_sfb : issue_slots_16_out_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_br_type = _T_193 ? issue_slots_17_out_uop_br_type : issue_slots_16_out_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_br_tag = _T_193 ? issue_slots_17_out_uop_br_tag : issue_slots_16_out_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_br_mask = _T_193 ? issue_slots_17_out_uop_br_mask : issue_slots_16_out_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_dis_col_sel = _T_193 ? issue_slots_17_out_uop_dis_col_sel : issue_slots_16_out_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_iw_p3_bypass_hint = _T_193 ? issue_slots_17_out_uop_iw_p3_bypass_hint : issue_slots_16_out_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_iw_p2_bypass_hint = _T_193 ? issue_slots_17_out_uop_iw_p2_bypass_hint : issue_slots_16_out_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_iw_p1_bypass_hint = _T_193 ? issue_slots_17_out_uop_iw_p1_bypass_hint : issue_slots_16_out_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_iw_p2_speculative_child = _T_193 ? issue_slots_17_out_uop_iw_p2_speculative_child : issue_slots_16_out_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_iw_p1_speculative_child = _T_193 ? issue_slots_17_out_uop_iw_p1_speculative_child : issue_slots_16_out_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_iw_issued = _T_193 ? issue_slots_17_out_uop_iw_issued : issue_slots_16_out_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_fu_code_0 = _T_193 ? issue_slots_17_out_uop_fu_code_0 : issue_slots_16_out_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_fu_code_1 = _T_193 ? issue_slots_17_out_uop_fu_code_1 : issue_slots_16_out_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_fu_code_2 = _T_193 ? issue_slots_17_out_uop_fu_code_2 : issue_slots_16_out_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_fu_code_3 = _T_193 ? issue_slots_17_out_uop_fu_code_3 : issue_slots_16_out_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_fu_code_4 = _T_193 ? issue_slots_17_out_uop_fu_code_4 : issue_slots_16_out_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_fu_code_5 = _T_193 ? issue_slots_17_out_uop_fu_code_5 : issue_slots_16_out_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_fu_code_6 = _T_193 ? issue_slots_17_out_uop_fu_code_6 : issue_slots_16_out_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_fu_code_7 = _T_193 ? issue_slots_17_out_uop_fu_code_7 : issue_slots_16_out_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_fu_code_8 = _T_193 ? issue_slots_17_out_uop_fu_code_8 : issue_slots_16_out_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_fu_code_9 = _T_193 ? issue_slots_17_out_uop_fu_code_9 : issue_slots_16_out_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_iq_type_0 = _T_193 ? issue_slots_17_out_uop_iq_type_0 : issue_slots_16_out_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_iq_type_1 = _T_193 ? issue_slots_17_out_uop_iq_type_1 : issue_slots_16_out_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_iq_type_2 = _T_193 ? issue_slots_17_out_uop_iq_type_2 : issue_slots_16_out_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_iq_type_3 = _T_193 ? issue_slots_17_out_uop_iq_type_3 : issue_slots_16_out_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_debug_pc = _T_193 ? issue_slots_17_out_uop_debug_pc : issue_slots_16_out_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_is_rvc = _T_193 ? issue_slots_17_out_uop_is_rvc : issue_slots_16_out_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_debug_inst = _T_193 ? issue_slots_17_out_uop_debug_inst : issue_slots_16_out_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_15_in_uop_bits_inst = _T_193 ? issue_slots_17_out_uop_inst : issue_slots_16_out_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign _issue_slots_15_clear_T = |shamts_oh_15;\t// @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49]\n assign issue_slots_15_clear = _issue_slots_15_clear_T;\t// @[issue-unit-age-ordered.scala:122:28, :199:49]\n wire _T_195 = shamts_oh_18 == 2'h2;\t// @[issue-unit-age-ordered.scala:158:23, :194:28]\n assign issue_slots_16_in_uop_valid = _T_195 ? issue_slots_18_will_be_valid : shamts_oh_17 == 2'h1 & issue_slots_17_will_be_valid;\t// @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37]\n assign issue_slots_16_in_uop_bits_debug_tsrc = _T_195 ? issue_slots_18_out_uop_debug_tsrc : issue_slots_17_out_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_debug_fsrc = _T_195 ? issue_slots_18_out_uop_debug_fsrc : issue_slots_17_out_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_bp_xcpt_if = _T_195 ? issue_slots_18_out_uop_bp_xcpt_if : issue_slots_17_out_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_bp_debug_if = _T_195 ? issue_slots_18_out_uop_bp_debug_if : issue_slots_17_out_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_xcpt_ma_if = _T_195 ? issue_slots_18_out_uop_xcpt_ma_if : issue_slots_17_out_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_xcpt_ae_if = _T_195 ? issue_slots_18_out_uop_xcpt_ae_if : issue_slots_17_out_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_xcpt_pf_if = _T_195 ? issue_slots_18_out_uop_xcpt_pf_if : issue_slots_17_out_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_fp_typ = _T_195 ? issue_slots_18_out_uop_fp_typ : issue_slots_17_out_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_fp_rm = _T_195 ? issue_slots_18_out_uop_fp_rm : issue_slots_17_out_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_fp_val = _T_195 ? issue_slots_18_out_uop_fp_val : issue_slots_17_out_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_fcn_op = _T_195 ? issue_slots_18_out_uop_fcn_op : issue_slots_17_out_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_fcn_dw = _T_195 ? issue_slots_18_out_uop_fcn_dw : issue_slots_17_out_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_frs3_en = _T_195 ? issue_slots_18_out_uop_frs3_en : issue_slots_17_out_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_lrs2_rtype = _T_195 ? issue_slots_18_out_uop_lrs2_rtype : issue_slots_17_out_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_lrs1_rtype = _T_195 ? issue_slots_18_out_uop_lrs1_rtype : issue_slots_17_out_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_dst_rtype = _T_195 ? issue_slots_18_out_uop_dst_rtype : issue_slots_17_out_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_lrs3 = _T_195 ? issue_slots_18_out_uop_lrs3 : issue_slots_17_out_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_lrs2 = _T_195 ? issue_slots_18_out_uop_lrs2 : issue_slots_17_out_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_lrs1 = _T_195 ? issue_slots_18_out_uop_lrs1 : issue_slots_17_out_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_ldst = _T_195 ? issue_slots_18_out_uop_ldst : issue_slots_17_out_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_ldst_is_rs1 = _T_195 ? issue_slots_18_out_uop_ldst_is_rs1 : issue_slots_17_out_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_csr_cmd = _T_195 ? issue_slots_18_out_uop_csr_cmd : issue_slots_17_out_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_flush_on_commit = _T_195 ? issue_slots_18_out_uop_flush_on_commit : issue_slots_17_out_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_is_unique = _T_195 ? issue_slots_18_out_uop_is_unique : issue_slots_17_out_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_uses_stq = _T_195 ? issue_slots_18_out_uop_uses_stq : issue_slots_17_out_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_uses_ldq = _T_195 ? issue_slots_18_out_uop_uses_ldq : issue_slots_17_out_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_mem_signed = _T_195 ? issue_slots_18_out_uop_mem_signed : issue_slots_17_out_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_mem_size = _T_195 ? issue_slots_18_out_uop_mem_size : issue_slots_17_out_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_mem_cmd = _T_195 ? issue_slots_18_out_uop_mem_cmd : issue_slots_17_out_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_exc_cause = _T_195 ? issue_slots_18_out_uop_exc_cause : issue_slots_17_out_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_exception = _T_195 ? issue_slots_18_out_uop_exception : issue_slots_17_out_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_stale_pdst = _T_195 ? issue_slots_18_out_uop_stale_pdst : issue_slots_17_out_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_ppred_busy = _T_195 ? issue_slots_18_out_uop_ppred_busy : issue_slots_17_out_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_prs3_busy = _T_195 ? issue_slots_18_out_uop_prs3_busy : issue_slots_17_out_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_prs2_busy = _T_195 ? issue_slots_18_out_uop_prs2_busy : issue_slots_17_out_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_prs1_busy = _T_195 ? issue_slots_18_out_uop_prs1_busy : issue_slots_17_out_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_ppred = _T_195 ? issue_slots_18_out_uop_ppred : issue_slots_17_out_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_prs3 = _T_195 ? issue_slots_18_out_uop_prs3 : issue_slots_17_out_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_prs2 = _T_195 ? issue_slots_18_out_uop_prs2 : issue_slots_17_out_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_prs1 = _T_195 ? issue_slots_18_out_uop_prs1 : issue_slots_17_out_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_pdst = _T_195 ? issue_slots_18_out_uop_pdst : issue_slots_17_out_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_rxq_idx = _T_195 ? issue_slots_18_out_uop_rxq_idx : issue_slots_17_out_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_stq_idx = _T_195 ? issue_slots_18_out_uop_stq_idx : issue_slots_17_out_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_ldq_idx = _T_195 ? issue_slots_18_out_uop_ldq_idx : issue_slots_17_out_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_rob_idx = _T_195 ? issue_slots_18_out_uop_rob_idx : issue_slots_17_out_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_fp_ctrl_vec = _T_195 ? issue_slots_18_out_uop_fp_ctrl_vec : issue_slots_17_out_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_fp_ctrl_wflags = _T_195 ? issue_slots_18_out_uop_fp_ctrl_wflags : issue_slots_17_out_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_fp_ctrl_sqrt = _T_195 ? issue_slots_18_out_uop_fp_ctrl_sqrt : issue_slots_17_out_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_fp_ctrl_div = _T_195 ? issue_slots_18_out_uop_fp_ctrl_div : issue_slots_17_out_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_fp_ctrl_fma = _T_195 ? issue_slots_18_out_uop_fp_ctrl_fma : issue_slots_17_out_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_fp_ctrl_fastpipe = _T_195 ? issue_slots_18_out_uop_fp_ctrl_fastpipe : issue_slots_17_out_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_fp_ctrl_toint = _T_195 ? issue_slots_18_out_uop_fp_ctrl_toint : issue_slots_17_out_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_fp_ctrl_fromint = _T_195 ? issue_slots_18_out_uop_fp_ctrl_fromint : issue_slots_17_out_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_fp_ctrl_typeTagOut = _T_195 ? issue_slots_18_out_uop_fp_ctrl_typeTagOut : issue_slots_17_out_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_fp_ctrl_typeTagIn = _T_195 ? issue_slots_18_out_uop_fp_ctrl_typeTagIn : issue_slots_17_out_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_fp_ctrl_swap23 = _T_195 ? issue_slots_18_out_uop_fp_ctrl_swap23 : issue_slots_17_out_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_fp_ctrl_swap12 = _T_195 ? issue_slots_18_out_uop_fp_ctrl_swap12 : issue_slots_17_out_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_fp_ctrl_ren3 = _T_195 ? issue_slots_18_out_uop_fp_ctrl_ren3 : issue_slots_17_out_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_fp_ctrl_ren2 = _T_195 ? issue_slots_18_out_uop_fp_ctrl_ren2 : issue_slots_17_out_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_fp_ctrl_ren1 = _T_195 ? issue_slots_18_out_uop_fp_ctrl_ren1 : issue_slots_17_out_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_fp_ctrl_wen = _T_195 ? issue_slots_18_out_uop_fp_ctrl_wen : issue_slots_17_out_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_fp_ctrl_ldst = _T_195 ? issue_slots_18_out_uop_fp_ctrl_ldst : issue_slots_17_out_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_op2_sel = _T_195 ? issue_slots_18_out_uop_op2_sel : issue_slots_17_out_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_op1_sel = _T_195 ? issue_slots_18_out_uop_op1_sel : issue_slots_17_out_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_imm_packed = _T_195 ? issue_slots_18_out_uop_imm_packed : issue_slots_17_out_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_pimm = _T_195 ? issue_slots_18_out_uop_pimm : issue_slots_17_out_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_imm_sel = _T_195 ? issue_slots_18_out_uop_imm_sel : issue_slots_17_out_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_imm_rename = _T_195 ? issue_slots_18_out_uop_imm_rename : issue_slots_17_out_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_taken = _T_195 ? issue_slots_18_out_uop_taken : issue_slots_17_out_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_pc_lob = _T_195 ? issue_slots_18_out_uop_pc_lob : issue_slots_17_out_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_edge_inst = _T_195 ? issue_slots_18_out_uop_edge_inst : issue_slots_17_out_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_ftq_idx = _T_195 ? issue_slots_18_out_uop_ftq_idx : issue_slots_17_out_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_is_mov = _T_195 ? issue_slots_18_out_uop_is_mov : issue_slots_17_out_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_is_rocc = _T_195 ? issue_slots_18_out_uop_is_rocc : issue_slots_17_out_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_is_sys_pc2epc = _T_195 ? issue_slots_18_out_uop_is_sys_pc2epc : issue_slots_17_out_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_is_eret = _T_195 ? issue_slots_18_out_uop_is_eret : issue_slots_17_out_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_is_amo = _T_195 ? issue_slots_18_out_uop_is_amo : issue_slots_17_out_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_is_sfence = _T_195 ? issue_slots_18_out_uop_is_sfence : issue_slots_17_out_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_is_fencei = _T_195 ? issue_slots_18_out_uop_is_fencei : issue_slots_17_out_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_is_fence = _T_195 ? issue_slots_18_out_uop_is_fence : issue_slots_17_out_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_is_sfb = _T_195 ? issue_slots_18_out_uop_is_sfb : issue_slots_17_out_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_br_type = _T_195 ? issue_slots_18_out_uop_br_type : issue_slots_17_out_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_br_tag = _T_195 ? issue_slots_18_out_uop_br_tag : issue_slots_17_out_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_br_mask = _T_195 ? issue_slots_18_out_uop_br_mask : issue_slots_17_out_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_dis_col_sel = _T_195 ? issue_slots_18_out_uop_dis_col_sel : issue_slots_17_out_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_iw_p3_bypass_hint = _T_195 ? issue_slots_18_out_uop_iw_p3_bypass_hint : issue_slots_17_out_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_iw_p2_bypass_hint = _T_195 ? issue_slots_18_out_uop_iw_p2_bypass_hint : issue_slots_17_out_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_iw_p1_bypass_hint = _T_195 ? issue_slots_18_out_uop_iw_p1_bypass_hint : issue_slots_17_out_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_iw_p2_speculative_child = _T_195 ? issue_slots_18_out_uop_iw_p2_speculative_child : issue_slots_17_out_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_iw_p1_speculative_child = _T_195 ? issue_slots_18_out_uop_iw_p1_speculative_child : issue_slots_17_out_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_iw_issued = _T_195 ? issue_slots_18_out_uop_iw_issued : issue_slots_17_out_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_fu_code_0 = _T_195 ? issue_slots_18_out_uop_fu_code_0 : issue_slots_17_out_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_fu_code_1 = _T_195 ? issue_slots_18_out_uop_fu_code_1 : issue_slots_17_out_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_fu_code_2 = _T_195 ? issue_slots_18_out_uop_fu_code_2 : issue_slots_17_out_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_fu_code_3 = _T_195 ? issue_slots_18_out_uop_fu_code_3 : issue_slots_17_out_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_fu_code_4 = _T_195 ? issue_slots_18_out_uop_fu_code_4 : issue_slots_17_out_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_fu_code_5 = _T_195 ? issue_slots_18_out_uop_fu_code_5 : issue_slots_17_out_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_fu_code_6 = _T_195 ? issue_slots_18_out_uop_fu_code_6 : issue_slots_17_out_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_fu_code_7 = _T_195 ? issue_slots_18_out_uop_fu_code_7 : issue_slots_17_out_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_fu_code_8 = _T_195 ? issue_slots_18_out_uop_fu_code_8 : issue_slots_17_out_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_fu_code_9 = _T_195 ? issue_slots_18_out_uop_fu_code_9 : issue_slots_17_out_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_iq_type_0 = _T_195 ? issue_slots_18_out_uop_iq_type_0 : issue_slots_17_out_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_iq_type_1 = _T_195 ? issue_slots_18_out_uop_iq_type_1 : issue_slots_17_out_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_iq_type_2 = _T_195 ? issue_slots_18_out_uop_iq_type_2 : issue_slots_17_out_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_iq_type_3 = _T_195 ? issue_slots_18_out_uop_iq_type_3 : issue_slots_17_out_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_debug_pc = _T_195 ? issue_slots_18_out_uop_debug_pc : issue_slots_17_out_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_is_rvc = _T_195 ? issue_slots_18_out_uop_is_rvc : issue_slots_17_out_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_debug_inst = _T_195 ? issue_slots_18_out_uop_debug_inst : issue_slots_17_out_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_16_in_uop_bits_inst = _T_195 ? issue_slots_18_out_uop_inst : issue_slots_17_out_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign _issue_slots_16_clear_T = |shamts_oh_16;\t// @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49]\n assign issue_slots_16_clear = _issue_slots_16_clear_T;\t// @[issue-unit-age-ordered.scala:122:28, :199:49]\n wire _T_197 = shamts_oh_19 == 2'h2;\t// @[issue-unit-age-ordered.scala:158:23, :194:28]\n assign issue_slots_17_in_uop_valid = _T_197 ? issue_slots_19_will_be_valid : shamts_oh_18 == 2'h1 & issue_slots_18_will_be_valid;\t// @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37]\n assign issue_slots_17_in_uop_bits_debug_tsrc = _T_197 ? issue_slots_19_out_uop_debug_tsrc : issue_slots_18_out_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_debug_fsrc = _T_197 ? issue_slots_19_out_uop_debug_fsrc : issue_slots_18_out_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_bp_xcpt_if = _T_197 ? issue_slots_19_out_uop_bp_xcpt_if : issue_slots_18_out_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_bp_debug_if = _T_197 ? issue_slots_19_out_uop_bp_debug_if : issue_slots_18_out_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_xcpt_ma_if = _T_197 ? issue_slots_19_out_uop_xcpt_ma_if : issue_slots_18_out_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_xcpt_ae_if = _T_197 ? issue_slots_19_out_uop_xcpt_ae_if : issue_slots_18_out_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_xcpt_pf_if = _T_197 ? issue_slots_19_out_uop_xcpt_pf_if : issue_slots_18_out_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_fp_typ = _T_197 ? issue_slots_19_out_uop_fp_typ : issue_slots_18_out_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_fp_rm = _T_197 ? issue_slots_19_out_uop_fp_rm : issue_slots_18_out_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_fp_val = _T_197 ? issue_slots_19_out_uop_fp_val : issue_slots_18_out_uop_fp_val;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_fcn_op = _T_197 ? issue_slots_19_out_uop_fcn_op : issue_slots_18_out_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_fcn_dw = _T_197 ? issue_slots_19_out_uop_fcn_dw : issue_slots_18_out_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_frs3_en = _T_197 ? issue_slots_19_out_uop_frs3_en : issue_slots_18_out_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_lrs2_rtype = _T_197 ? issue_slots_19_out_uop_lrs2_rtype : issue_slots_18_out_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_lrs1_rtype = _T_197 ? issue_slots_19_out_uop_lrs1_rtype : issue_slots_18_out_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_dst_rtype = _T_197 ? issue_slots_19_out_uop_dst_rtype : issue_slots_18_out_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_lrs3 = _T_197 ? issue_slots_19_out_uop_lrs3 : issue_slots_18_out_uop_lrs3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_lrs2 = _T_197 ? issue_slots_19_out_uop_lrs2 : issue_slots_18_out_uop_lrs2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_lrs1 = _T_197 ? issue_slots_19_out_uop_lrs1 : issue_slots_18_out_uop_lrs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_ldst = _T_197 ? issue_slots_19_out_uop_ldst : issue_slots_18_out_uop_ldst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_ldst_is_rs1 = _T_197 ? issue_slots_19_out_uop_ldst_is_rs1 : issue_slots_18_out_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_csr_cmd = _T_197 ? issue_slots_19_out_uop_csr_cmd : issue_slots_18_out_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_flush_on_commit = _T_197 ? issue_slots_19_out_uop_flush_on_commit : issue_slots_18_out_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_is_unique = _T_197 ? issue_slots_19_out_uop_is_unique : issue_slots_18_out_uop_is_unique;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_uses_stq = _T_197 ? issue_slots_19_out_uop_uses_stq : issue_slots_18_out_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_uses_ldq = _T_197 ? issue_slots_19_out_uop_uses_ldq : issue_slots_18_out_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_mem_signed = _T_197 ? issue_slots_19_out_uop_mem_signed : issue_slots_18_out_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_mem_size = _T_197 ? issue_slots_19_out_uop_mem_size : issue_slots_18_out_uop_mem_size;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_mem_cmd = _T_197 ? issue_slots_19_out_uop_mem_cmd : issue_slots_18_out_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_exc_cause = _T_197 ? issue_slots_19_out_uop_exc_cause : issue_slots_18_out_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_exception = _T_197 ? issue_slots_19_out_uop_exception : issue_slots_18_out_uop_exception;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_stale_pdst = _T_197 ? issue_slots_19_out_uop_stale_pdst : issue_slots_18_out_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_ppred_busy = _T_197 ? issue_slots_19_out_uop_ppred_busy : issue_slots_18_out_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_prs3_busy = _T_197 ? issue_slots_19_out_uop_prs3_busy : issue_slots_18_out_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_prs2_busy = _T_197 ? issue_slots_19_out_uop_prs2_busy : issue_slots_18_out_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_prs1_busy = _T_197 ? issue_slots_19_out_uop_prs1_busy : issue_slots_18_out_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_ppred = _T_197 ? issue_slots_19_out_uop_ppred : issue_slots_18_out_uop_ppred;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_prs3 = _T_197 ? issue_slots_19_out_uop_prs3 : issue_slots_18_out_uop_prs3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_prs2 = _T_197 ? issue_slots_19_out_uop_prs2 : issue_slots_18_out_uop_prs2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_prs1 = _T_197 ? issue_slots_19_out_uop_prs1 : issue_slots_18_out_uop_prs1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_pdst = _T_197 ? issue_slots_19_out_uop_pdst : issue_slots_18_out_uop_pdst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_rxq_idx = _T_197 ? issue_slots_19_out_uop_rxq_idx : issue_slots_18_out_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_stq_idx = _T_197 ? issue_slots_19_out_uop_stq_idx : issue_slots_18_out_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_ldq_idx = _T_197 ? issue_slots_19_out_uop_ldq_idx : issue_slots_18_out_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_rob_idx = _T_197 ? issue_slots_19_out_uop_rob_idx : issue_slots_18_out_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_fp_ctrl_vec = _T_197 ? issue_slots_19_out_uop_fp_ctrl_vec : issue_slots_18_out_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_fp_ctrl_wflags = _T_197 ? issue_slots_19_out_uop_fp_ctrl_wflags : issue_slots_18_out_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_fp_ctrl_sqrt = _T_197 ? issue_slots_19_out_uop_fp_ctrl_sqrt : issue_slots_18_out_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_fp_ctrl_div = _T_197 ? issue_slots_19_out_uop_fp_ctrl_div : issue_slots_18_out_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_fp_ctrl_fma = _T_197 ? issue_slots_19_out_uop_fp_ctrl_fma : issue_slots_18_out_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_fp_ctrl_fastpipe = _T_197 ? issue_slots_19_out_uop_fp_ctrl_fastpipe : issue_slots_18_out_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_fp_ctrl_toint = _T_197 ? issue_slots_19_out_uop_fp_ctrl_toint : issue_slots_18_out_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_fp_ctrl_fromint = _T_197 ? issue_slots_19_out_uop_fp_ctrl_fromint : issue_slots_18_out_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_fp_ctrl_typeTagOut = _T_197 ? issue_slots_19_out_uop_fp_ctrl_typeTagOut : issue_slots_18_out_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_fp_ctrl_typeTagIn = _T_197 ? issue_slots_19_out_uop_fp_ctrl_typeTagIn : issue_slots_18_out_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_fp_ctrl_swap23 = _T_197 ? issue_slots_19_out_uop_fp_ctrl_swap23 : issue_slots_18_out_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_fp_ctrl_swap12 = _T_197 ? issue_slots_19_out_uop_fp_ctrl_swap12 : issue_slots_18_out_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_fp_ctrl_ren3 = _T_197 ? issue_slots_19_out_uop_fp_ctrl_ren3 : issue_slots_18_out_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_fp_ctrl_ren2 = _T_197 ? issue_slots_19_out_uop_fp_ctrl_ren2 : issue_slots_18_out_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_fp_ctrl_ren1 = _T_197 ? issue_slots_19_out_uop_fp_ctrl_ren1 : issue_slots_18_out_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_fp_ctrl_wen = _T_197 ? issue_slots_19_out_uop_fp_ctrl_wen : issue_slots_18_out_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_fp_ctrl_ldst = _T_197 ? issue_slots_19_out_uop_fp_ctrl_ldst : issue_slots_18_out_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_op2_sel = _T_197 ? issue_slots_19_out_uop_op2_sel : issue_slots_18_out_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_op1_sel = _T_197 ? issue_slots_19_out_uop_op1_sel : issue_slots_18_out_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_imm_packed = _T_197 ? issue_slots_19_out_uop_imm_packed : issue_slots_18_out_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_pimm = _T_197 ? issue_slots_19_out_uop_pimm : issue_slots_18_out_uop_pimm;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_imm_sel = _T_197 ? issue_slots_19_out_uop_imm_sel : issue_slots_18_out_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_imm_rename = _T_197 ? issue_slots_19_out_uop_imm_rename : issue_slots_18_out_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_taken = _T_197 ? issue_slots_19_out_uop_taken : issue_slots_18_out_uop_taken;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_pc_lob = _T_197 ? issue_slots_19_out_uop_pc_lob : issue_slots_18_out_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_edge_inst = _T_197 ? issue_slots_19_out_uop_edge_inst : issue_slots_18_out_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_ftq_idx = _T_197 ? issue_slots_19_out_uop_ftq_idx : issue_slots_18_out_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_is_mov = _T_197 ? issue_slots_19_out_uop_is_mov : issue_slots_18_out_uop_is_mov;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_is_rocc = _T_197 ? issue_slots_19_out_uop_is_rocc : issue_slots_18_out_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_is_sys_pc2epc = _T_197 ? issue_slots_19_out_uop_is_sys_pc2epc : issue_slots_18_out_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_is_eret = _T_197 ? issue_slots_19_out_uop_is_eret : issue_slots_18_out_uop_is_eret;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_is_amo = _T_197 ? issue_slots_19_out_uop_is_amo : issue_slots_18_out_uop_is_amo;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_is_sfence = _T_197 ? issue_slots_19_out_uop_is_sfence : issue_slots_18_out_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_is_fencei = _T_197 ? issue_slots_19_out_uop_is_fencei : issue_slots_18_out_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_is_fence = _T_197 ? issue_slots_19_out_uop_is_fence : issue_slots_18_out_uop_is_fence;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_is_sfb = _T_197 ? issue_slots_19_out_uop_is_sfb : issue_slots_18_out_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_br_type = _T_197 ? issue_slots_19_out_uop_br_type : issue_slots_18_out_uop_br_type;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_br_tag = _T_197 ? issue_slots_19_out_uop_br_tag : issue_slots_18_out_uop_br_tag;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_br_mask = _T_197 ? issue_slots_19_out_uop_br_mask : issue_slots_18_out_uop_br_mask;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_dis_col_sel = _T_197 ? issue_slots_19_out_uop_dis_col_sel : issue_slots_18_out_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_iw_p3_bypass_hint = _T_197 ? issue_slots_19_out_uop_iw_p3_bypass_hint : issue_slots_18_out_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_iw_p2_bypass_hint = _T_197 ? issue_slots_19_out_uop_iw_p2_bypass_hint : issue_slots_18_out_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_iw_p1_bypass_hint = _T_197 ? issue_slots_19_out_uop_iw_p1_bypass_hint : issue_slots_18_out_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_iw_p2_speculative_child = _T_197 ? issue_slots_19_out_uop_iw_p2_speculative_child : issue_slots_18_out_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_iw_p1_speculative_child = _T_197 ? issue_slots_19_out_uop_iw_p1_speculative_child : issue_slots_18_out_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_iw_issued = _T_197 ? issue_slots_19_out_uop_iw_issued : issue_slots_18_out_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_fu_code_0 = _T_197 ? issue_slots_19_out_uop_fu_code_0 : issue_slots_18_out_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_fu_code_1 = _T_197 ? issue_slots_19_out_uop_fu_code_1 : issue_slots_18_out_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_fu_code_2 = _T_197 ? issue_slots_19_out_uop_fu_code_2 : issue_slots_18_out_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_fu_code_3 = _T_197 ? issue_slots_19_out_uop_fu_code_3 : issue_slots_18_out_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_fu_code_4 = _T_197 ? issue_slots_19_out_uop_fu_code_4 : issue_slots_18_out_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_fu_code_5 = _T_197 ? issue_slots_19_out_uop_fu_code_5 : issue_slots_18_out_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_fu_code_6 = _T_197 ? issue_slots_19_out_uop_fu_code_6 : issue_slots_18_out_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_fu_code_7 = _T_197 ? issue_slots_19_out_uop_fu_code_7 : issue_slots_18_out_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_fu_code_8 = _T_197 ? issue_slots_19_out_uop_fu_code_8 : issue_slots_18_out_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_fu_code_9 = _T_197 ? issue_slots_19_out_uop_fu_code_9 : issue_slots_18_out_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_iq_type_0 = _T_197 ? issue_slots_19_out_uop_iq_type_0 : issue_slots_18_out_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_iq_type_1 = _T_197 ? issue_slots_19_out_uop_iq_type_1 : issue_slots_18_out_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_iq_type_2 = _T_197 ? issue_slots_19_out_uop_iq_type_2 : issue_slots_18_out_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_iq_type_3 = _T_197 ? issue_slots_19_out_uop_iq_type_3 : issue_slots_18_out_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_debug_pc = _T_197 ? issue_slots_19_out_uop_debug_pc : issue_slots_18_out_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_is_rvc = _T_197 ? issue_slots_19_out_uop_is_rvc : issue_slots_18_out_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_debug_inst = _T_197 ? issue_slots_19_out_uop_debug_inst : issue_slots_18_out_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_17_in_uop_bits_inst = _T_197 ? issue_slots_19_out_uop_inst : issue_slots_18_out_uop_inst;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign _issue_slots_17_clear_T = |shamts_oh_17;\t// @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49]\n assign issue_slots_17_clear = _issue_slots_17_clear_T;\t// @[issue-unit-age-ordered.scala:122:28, :199:49]\n wire _T_199 = shamts_oh_20 == 2'h2;\t// @[issue-unit-age-ordered.scala:158:23, :194:28]\n assign issue_slots_18_in_uop_valid = _T_199 ? will_be_valid_20 : shamts_oh_19 == 2'h1 & issue_slots_19_will_be_valid;\t// @[issue-unit-age-ordered.scala:122:28, :158:23, :186:79, :191:33, :194:{28,48}, :195:37]\n assign issue_slots_18_in_uop_bits_debug_tsrc = _T_199 ? io_dis_uops_0_bits_debug_tsrc_0 : issue_slots_19_out_uop_debug_tsrc;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_debug_fsrc = _T_199 ? io_dis_uops_0_bits_debug_fsrc_0 : issue_slots_19_out_uop_debug_fsrc;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_bp_xcpt_if = _T_199 ? io_dis_uops_0_bits_bp_xcpt_if_0 : issue_slots_19_out_uop_bp_xcpt_if;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_bp_debug_if = _T_199 ? io_dis_uops_0_bits_bp_debug_if_0 : issue_slots_19_out_uop_bp_debug_if;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_xcpt_ma_if = _T_199 ? io_dis_uops_0_bits_xcpt_ma_if_0 : issue_slots_19_out_uop_xcpt_ma_if;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_xcpt_ae_if = _T_199 ? io_dis_uops_0_bits_xcpt_ae_if_0 : issue_slots_19_out_uop_xcpt_ae_if;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_xcpt_pf_if = _T_199 ? io_dis_uops_0_bits_xcpt_pf_if_0 : issue_slots_19_out_uop_xcpt_pf_if;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_fp_typ = _T_199 ? io_dis_uops_0_bits_fp_typ_0 : issue_slots_19_out_uop_fp_typ;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_fp_rm = _T_199 ? io_dis_uops_0_bits_fp_rm_0 : issue_slots_19_out_uop_fp_rm;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_fp_val = _T_199 ? io_dis_uops_0_bits_fp_val_0 : issue_slots_19_out_uop_fp_val;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_fcn_op = _T_199 ? io_dis_uops_0_bits_fcn_op_0 : issue_slots_19_out_uop_fcn_op;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_fcn_dw = _T_199 ? io_dis_uops_0_bits_fcn_dw_0 : issue_slots_19_out_uop_fcn_dw;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_frs3_en = _T_199 ? io_dis_uops_0_bits_frs3_en_0 : issue_slots_19_out_uop_frs3_en;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_lrs2_rtype = _T_199 ? io_dis_uops_0_bits_lrs2_rtype_0 : issue_slots_19_out_uop_lrs2_rtype;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_lrs1_rtype = _T_199 ? io_dis_uops_0_bits_lrs1_rtype_0 : issue_slots_19_out_uop_lrs1_rtype;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_dst_rtype = _T_199 ? io_dis_uops_0_bits_dst_rtype_0 : issue_slots_19_out_uop_dst_rtype;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_lrs3 = _T_199 ? io_dis_uops_0_bits_lrs3_0 : issue_slots_19_out_uop_lrs3;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_lrs2 = _T_199 ? io_dis_uops_0_bits_lrs2_0 : issue_slots_19_out_uop_lrs2;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_lrs1 = _T_199 ? io_dis_uops_0_bits_lrs1_0 : issue_slots_19_out_uop_lrs1;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_ldst = _T_199 ? io_dis_uops_0_bits_ldst_0 : issue_slots_19_out_uop_ldst;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_ldst_is_rs1 = _T_199 ? io_dis_uops_0_bits_ldst_is_rs1_0 : issue_slots_19_out_uop_ldst_is_rs1;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_csr_cmd = _T_199 ? io_dis_uops_0_bits_csr_cmd_0 : issue_slots_19_out_uop_csr_cmd;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_flush_on_commit = _T_199 ? io_dis_uops_0_bits_flush_on_commit_0 : issue_slots_19_out_uop_flush_on_commit;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_is_unique = _T_199 ? io_dis_uops_0_bits_is_unique_0 : issue_slots_19_out_uop_is_unique;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_uses_stq = _T_199 ? io_dis_uops_0_bits_uses_stq_0 : issue_slots_19_out_uop_uses_stq;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_uses_ldq = _T_199 ? io_dis_uops_0_bits_uses_ldq_0 : issue_slots_19_out_uop_uses_ldq;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_mem_signed = _T_199 ? io_dis_uops_0_bits_mem_signed_0 : issue_slots_19_out_uop_mem_signed;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_mem_size = _T_199 ? io_dis_uops_0_bits_mem_size_0 : issue_slots_19_out_uop_mem_size;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_mem_cmd = _T_199 ? io_dis_uops_0_bits_mem_cmd_0 : issue_slots_19_out_uop_mem_cmd;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_exc_cause = _T_199 ? io_dis_uops_0_bits_exc_cause_0 : issue_slots_19_out_uop_exc_cause;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_exception = _T_199 ? io_dis_uops_0_bits_exception_0 : issue_slots_19_out_uop_exception;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_stale_pdst = _T_199 ? io_dis_uops_0_bits_stale_pdst_0 : issue_slots_19_out_uop_stale_pdst;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_ppred_busy = _T_199 ? _WIRE_ppred_busy : issue_slots_19_out_uop_ppred_busy;\t// @[issue-unit-age-ordered.scala:35:17, :80:96, :81:30, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_prs3_busy = _T_199 ? _WIRE_prs3_busy : issue_slots_19_out_uop_prs3_busy;\t// @[issue-unit-age-ordered.scala:35:17, :76:38, :77:29, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_prs2_busy = _T_199 ? _WIRE_prs2_busy : issue_slots_19_out_uop_prs2_busy;\t// @[issue-unit-age-ordered.scala:65:38, :71:116, :72:29, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_prs1_busy = _T_199 ? _WIRE_prs1_busy : issue_slots_19_out_uop_prs1_busy;\t// @[issue-unit-age-ordered.scala:57:38, :62:116, :63:29, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_ppred = _T_199 ? io_dis_uops_0_bits_ppred_0 : issue_slots_19_out_uop_ppred;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_prs3 = _T_199 ? io_dis_uops_0_bits_prs3_0 : issue_slots_19_out_uop_prs3;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_prs2 = _T_199 ? io_dis_uops_0_bits_prs2_0 : issue_slots_19_out_uop_prs2;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_prs1 = _T_199 ? io_dis_uops_0_bits_prs1_0 : issue_slots_19_out_uop_prs1;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_pdst = _T_199 ? io_dis_uops_0_bits_pdst_0 : issue_slots_19_out_uop_pdst;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_rxq_idx = _T_199 ? io_dis_uops_0_bits_rxq_idx_0 : issue_slots_19_out_uop_rxq_idx;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_stq_idx = _T_199 ? io_dis_uops_0_bits_stq_idx_0 : issue_slots_19_out_uop_stq_idx;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_ldq_idx = _T_199 ? io_dis_uops_0_bits_ldq_idx_0 : issue_slots_19_out_uop_ldq_idx;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_rob_idx = _T_199 ? io_dis_uops_0_bits_rob_idx_0 : issue_slots_19_out_uop_rob_idx;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_fp_ctrl_vec = _T_199 ? io_dis_uops_0_bits_fp_ctrl_vec_0 : issue_slots_19_out_uop_fp_ctrl_vec;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_fp_ctrl_wflags = _T_199 ? io_dis_uops_0_bits_fp_ctrl_wflags_0 : issue_slots_19_out_uop_fp_ctrl_wflags;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_fp_ctrl_sqrt = _T_199 ? io_dis_uops_0_bits_fp_ctrl_sqrt_0 : issue_slots_19_out_uop_fp_ctrl_sqrt;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_fp_ctrl_div = _T_199 ? io_dis_uops_0_bits_fp_ctrl_div_0 : issue_slots_19_out_uop_fp_ctrl_div;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_fp_ctrl_fma = _T_199 ? io_dis_uops_0_bits_fp_ctrl_fma_0 : issue_slots_19_out_uop_fp_ctrl_fma;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_fp_ctrl_fastpipe = _T_199 ? io_dis_uops_0_bits_fp_ctrl_fastpipe_0 : issue_slots_19_out_uop_fp_ctrl_fastpipe;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_fp_ctrl_toint = _T_199 ? io_dis_uops_0_bits_fp_ctrl_toint_0 : issue_slots_19_out_uop_fp_ctrl_toint;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_fp_ctrl_fromint = _T_199 ? io_dis_uops_0_bits_fp_ctrl_fromint_0 : issue_slots_19_out_uop_fp_ctrl_fromint;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_fp_ctrl_typeTagOut = _T_199 ? io_dis_uops_0_bits_fp_ctrl_typeTagOut_0 : issue_slots_19_out_uop_fp_ctrl_typeTagOut;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_fp_ctrl_typeTagIn = _T_199 ? io_dis_uops_0_bits_fp_ctrl_typeTagIn_0 : issue_slots_19_out_uop_fp_ctrl_typeTagIn;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_fp_ctrl_swap23 = _T_199 ? io_dis_uops_0_bits_fp_ctrl_swap23_0 : issue_slots_19_out_uop_fp_ctrl_swap23;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_fp_ctrl_swap12 = _T_199 ? io_dis_uops_0_bits_fp_ctrl_swap12_0 : issue_slots_19_out_uop_fp_ctrl_swap12;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_fp_ctrl_ren3 = _T_199 ? io_dis_uops_0_bits_fp_ctrl_ren3_0 : issue_slots_19_out_uop_fp_ctrl_ren3;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_fp_ctrl_ren2 = _T_199 ? io_dis_uops_0_bits_fp_ctrl_ren2_0 : issue_slots_19_out_uop_fp_ctrl_ren2;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_fp_ctrl_ren1 = _T_199 ? io_dis_uops_0_bits_fp_ctrl_ren1_0 : issue_slots_19_out_uop_fp_ctrl_ren1;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_fp_ctrl_wen = _T_199 ? io_dis_uops_0_bits_fp_ctrl_wen_0 : issue_slots_19_out_uop_fp_ctrl_wen;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_fp_ctrl_ldst = _T_199 ? io_dis_uops_0_bits_fp_ctrl_ldst_0 : issue_slots_19_out_uop_fp_ctrl_ldst;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_op2_sel = _T_199 ? io_dis_uops_0_bits_op2_sel_0 : issue_slots_19_out_uop_op2_sel;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_op1_sel = _T_199 ? io_dis_uops_0_bits_op1_sel_0 : issue_slots_19_out_uop_op1_sel;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_imm_packed = _T_199 ? io_dis_uops_0_bits_imm_packed_0 : issue_slots_19_out_uop_imm_packed;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_pimm = _T_199 ? io_dis_uops_0_bits_pimm_0 : issue_slots_19_out_uop_pimm;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_imm_sel = _T_199 ? io_dis_uops_0_bits_imm_sel_0 : issue_slots_19_out_uop_imm_sel;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_imm_rename = _T_199 ? io_dis_uops_0_bits_imm_rename_0 : issue_slots_19_out_uop_imm_rename;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_taken = _T_199 ? io_dis_uops_0_bits_taken_0 : issue_slots_19_out_uop_taken;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_pc_lob = _T_199 ? io_dis_uops_0_bits_pc_lob_0 : issue_slots_19_out_uop_pc_lob;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_edge_inst = _T_199 ? io_dis_uops_0_bits_edge_inst_0 : issue_slots_19_out_uop_edge_inst;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_ftq_idx = _T_199 ? io_dis_uops_0_bits_ftq_idx_0 : issue_slots_19_out_uop_ftq_idx;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_is_mov = _T_199 ? io_dis_uops_0_bits_is_mov_0 : issue_slots_19_out_uop_is_mov;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_is_rocc = _T_199 ? io_dis_uops_0_bits_is_rocc_0 : issue_slots_19_out_uop_is_rocc;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_is_sys_pc2epc = _T_199 ? io_dis_uops_0_bits_is_sys_pc2epc_0 : issue_slots_19_out_uop_is_sys_pc2epc;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_is_eret = _T_199 ? io_dis_uops_0_bits_is_eret_0 : issue_slots_19_out_uop_is_eret;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_is_amo = _T_199 ? io_dis_uops_0_bits_is_amo_0 : issue_slots_19_out_uop_is_amo;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_is_sfence = _T_199 ? io_dis_uops_0_bits_is_sfence_0 : issue_slots_19_out_uop_is_sfence;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_is_fencei = _T_199 ? io_dis_uops_0_bits_is_fencei_0 : issue_slots_19_out_uop_is_fencei;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_is_fence = _T_199 ? io_dis_uops_0_bits_is_fence_0 : issue_slots_19_out_uop_is_fence;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_is_sfb = _T_199 ? io_dis_uops_0_bits_is_sfb_0 : issue_slots_19_out_uop_is_sfb;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_br_type = _T_199 ? io_dis_uops_0_bits_br_type_0 : issue_slots_19_out_uop_br_type;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_br_tag = _T_199 ? io_dis_uops_0_bits_br_tag_0 : issue_slots_19_out_uop_br_tag;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_br_mask = _T_199 ? io_dis_uops_0_bits_br_mask_0 : issue_slots_19_out_uop_br_mask;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_dis_col_sel = _T_199 ? io_dis_uops_0_bits_dis_col_sel_0 : issue_slots_19_out_uop_dis_col_sel;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_iw_p3_bypass_hint = _T_199 ? _WIRE_iw_p3_bypass_hint : issue_slots_19_out_uop_iw_p3_bypass_hint;\t// @[issue-unit-age-ordered.scala:41:35, :76:38, :78:37, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_iw_p2_bypass_hint = _T_199 ? _WIRE_iw_p2_bypass_hint : issue_slots_19_out_uop_iw_p2_bypass_hint;\t// @[issue-unit-age-ordered.scala:40:35, :65:38, :68:37, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_iw_p1_bypass_hint = _T_199 ? _WIRE_iw_p1_bypass_hint : issue_slots_19_out_uop_iw_p1_bypass_hint;\t// @[issue-unit-age-ordered.scala:39:35, :57:38, :60:37, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_iw_p2_speculative_child = _T_199 ? _WIRE_iw_p2_speculative_child : issue_slots_19_out_uop_iw_p2_speculative_child;\t// @[issue-unit-age-ordered.scala:35:17, :65:38, :67:43, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_iw_p1_speculative_child = _T_199 ? _WIRE_iw_p1_speculative_child : issue_slots_19_out_uop_iw_p1_speculative_child;\t// @[issue-unit-age-ordered.scala:35:17, :57:38, :59:43, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_iw_issued = ~_T_199 & issue_slots_19_out_uop_iw_issued;\t// @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_fu_code_0 = _T_199 ? io_dis_uops_0_bits_fu_code_0_0 : issue_slots_19_out_uop_fu_code_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_fu_code_1 = _T_199 ? io_dis_uops_0_bits_fu_code_1_0 : issue_slots_19_out_uop_fu_code_1;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_fu_code_2 = _T_199 ? io_dis_uops_0_bits_fu_code_2_0 : issue_slots_19_out_uop_fu_code_2;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_fu_code_3 = _T_199 ? io_dis_uops_0_bits_fu_code_3_0 : issue_slots_19_out_uop_fu_code_3;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_fu_code_4 = _T_199 ? io_dis_uops_0_bits_fu_code_4_0 : issue_slots_19_out_uop_fu_code_4;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_fu_code_5 = _T_199 ? io_dis_uops_0_bits_fu_code_5_0 : issue_slots_19_out_uop_fu_code_5;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_fu_code_6 = _T_199 ? io_dis_uops_0_bits_fu_code_6_0 : issue_slots_19_out_uop_fu_code_6;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_fu_code_7 = _T_199 ? io_dis_uops_0_bits_fu_code_7_0 : issue_slots_19_out_uop_fu_code_7;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_fu_code_8 = _T_199 ? io_dis_uops_0_bits_fu_code_8_0 : issue_slots_19_out_uop_fu_code_8;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_fu_code_9 = _T_199 ? io_dis_uops_0_bits_fu_code_9_0 : issue_slots_19_out_uop_fu_code_9;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_iq_type_0 = _T_199 ? io_dis_uops_0_bits_iq_type_0_0 : issue_slots_19_out_uop_iq_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_iq_type_1 = _T_199 ? io_dis_uops_0_bits_iq_type_1_0 : issue_slots_19_out_uop_iq_type_1;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_iq_type_2 = _T_199 ? io_dis_uops_0_bits_iq_type_2_0 : issue_slots_19_out_uop_iq_type_2;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_iq_type_3 = _T_199 ? io_dis_uops_0_bits_iq_type_3_0 : issue_slots_19_out_uop_iq_type_3;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_debug_pc = _T_199 ? io_dis_uops_0_bits_debug_pc_0 : issue_slots_19_out_uop_debug_pc;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_is_rvc = _T_199 ? io_dis_uops_0_bits_is_rvc_0 : issue_slots_19_out_uop_is_rvc;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_debug_inst = _T_199 ? io_dis_uops_0_bits_debug_inst_0 : issue_slots_19_out_uop_debug_inst;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_18_in_uop_bits_inst = _T_199 ? io_dis_uops_0_bits_inst_0 : issue_slots_19_out_uop_inst;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign _issue_slots_18_clear_T = |shamts_oh_18;\t// @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49]\n assign issue_slots_18_clear = _issue_slots_18_clear_T;\t// @[issue-unit-age-ordered.scala:122:28, :199:49]\n wire _T_201 = shamts_oh_21 == 2'h2;\t// @[issue-unit-age-ordered.scala:158:23, :194:28]\n assign issue_slots_19_in_uop_valid = _T_201 ? will_be_valid_21 : shamts_oh_20 == 2'h1 & will_be_valid_20;\t// @[issue-unit-age-ordered.scala:122:28, :158:23, :186:79, :191:33, :194:{28,48}, :195:37]\n assign issue_slots_19_in_uop_bits_debug_tsrc = _T_201 ? io_dis_uops_1_bits_debug_tsrc_0 : io_dis_uops_0_bits_debug_tsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_debug_fsrc = _T_201 ? io_dis_uops_1_bits_debug_fsrc_0 : io_dis_uops_0_bits_debug_fsrc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_bp_xcpt_if = _T_201 ? io_dis_uops_1_bits_bp_xcpt_if_0 : io_dis_uops_0_bits_bp_xcpt_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_bp_debug_if = _T_201 ? io_dis_uops_1_bits_bp_debug_if_0 : io_dis_uops_0_bits_bp_debug_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_xcpt_ma_if = _T_201 ? io_dis_uops_1_bits_xcpt_ma_if_0 : io_dis_uops_0_bits_xcpt_ma_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_xcpt_ae_if = _T_201 ? io_dis_uops_1_bits_xcpt_ae_if_0 : io_dis_uops_0_bits_xcpt_ae_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_xcpt_pf_if = _T_201 ? io_dis_uops_1_bits_xcpt_pf_if_0 : io_dis_uops_0_bits_xcpt_pf_if_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_fp_typ = _T_201 ? io_dis_uops_1_bits_fp_typ_0 : io_dis_uops_0_bits_fp_typ_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_fp_rm = _T_201 ? io_dis_uops_1_bits_fp_rm_0 : io_dis_uops_0_bits_fp_rm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_fp_val = _T_201 ? io_dis_uops_1_bits_fp_val_0 : io_dis_uops_0_bits_fp_val_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_fcn_op = _T_201 ? io_dis_uops_1_bits_fcn_op_0 : io_dis_uops_0_bits_fcn_op_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_fcn_dw = _T_201 ? io_dis_uops_1_bits_fcn_dw_0 : io_dis_uops_0_bits_fcn_dw_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_frs3_en = _T_201 ? io_dis_uops_1_bits_frs3_en_0 : io_dis_uops_0_bits_frs3_en_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_lrs2_rtype = _T_201 ? io_dis_uops_1_bits_lrs2_rtype_0 : io_dis_uops_0_bits_lrs2_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_lrs1_rtype = _T_201 ? io_dis_uops_1_bits_lrs1_rtype_0 : io_dis_uops_0_bits_lrs1_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_dst_rtype = _T_201 ? io_dis_uops_1_bits_dst_rtype_0 : io_dis_uops_0_bits_dst_rtype_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_lrs3 = _T_201 ? io_dis_uops_1_bits_lrs3_0 : io_dis_uops_0_bits_lrs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_lrs2 = _T_201 ? io_dis_uops_1_bits_lrs2_0 : io_dis_uops_0_bits_lrs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_lrs1 = _T_201 ? io_dis_uops_1_bits_lrs1_0 : io_dis_uops_0_bits_lrs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_ldst = _T_201 ? io_dis_uops_1_bits_ldst_0 : io_dis_uops_0_bits_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_ldst_is_rs1 = _T_201 ? io_dis_uops_1_bits_ldst_is_rs1_0 : io_dis_uops_0_bits_ldst_is_rs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_csr_cmd = _T_201 ? io_dis_uops_1_bits_csr_cmd_0 : io_dis_uops_0_bits_csr_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_flush_on_commit = _T_201 ? io_dis_uops_1_bits_flush_on_commit_0 : io_dis_uops_0_bits_flush_on_commit_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_is_unique = _T_201 ? io_dis_uops_1_bits_is_unique_0 : io_dis_uops_0_bits_is_unique_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_uses_stq = _T_201 ? io_dis_uops_1_bits_uses_stq_0 : io_dis_uops_0_bits_uses_stq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_uses_ldq = _T_201 ? io_dis_uops_1_bits_uses_ldq_0 : io_dis_uops_0_bits_uses_ldq_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_mem_signed = _T_201 ? io_dis_uops_1_bits_mem_signed_0 : io_dis_uops_0_bits_mem_signed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_mem_size = _T_201 ? io_dis_uops_1_bits_mem_size_0 : io_dis_uops_0_bits_mem_size_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_mem_cmd = _T_201 ? io_dis_uops_1_bits_mem_cmd_0 : io_dis_uops_0_bits_mem_cmd_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_exc_cause = _T_201 ? io_dis_uops_1_bits_exc_cause_0 : io_dis_uops_0_bits_exc_cause_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_exception = _T_201 ? io_dis_uops_1_bits_exception_0 : io_dis_uops_0_bits_exception_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_stale_pdst = _T_201 ? io_dis_uops_1_bits_stale_pdst_0 : io_dis_uops_0_bits_stale_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_ppred_busy = _T_201 ? ~(io_pred_wakeup_port_valid_0 & io_pred_wakeup_port_bits_0 == io_dis_uops_1_bits_ppred_0) & io_dis_uops_1_bits_ppred_busy_0 : _WIRE_ppred_busy;\t// @[issue-unit-age-ordered.scala:22:7, :35:17, :80:{37,65,96}, :81:30, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_prs3_busy = _T_201 ? ~_T_110 & io_dis_uops_1_bits_prs3_busy_0 : _WIRE_prs3_busy;\t// @[issue-unit-age-ordered.scala:22:7, :35:17, :76:{32,38}, :77:29, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_prs2_busy = _T_201 ? ((|{prs2_rebusys_0_1, io_child_rebusys_0 & io_dis_uops_1_bits_iw_p2_speculative_child_0}) ? io_dis_uops_1_bits_lrs2_rtype_0 == 2'h0 : ~_T_86 & io_dis_uops_1_bits_prs2_busy_0) : _WIRE_prs2_busy;\t// @[issue-unit-age-ordered.scala:22:7, :35:17, :51:95, :65:{32,38}, :66:29, :71:{37,59,106,116}, :72:{29,63}, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_prs1_busy = _T_201 ? ((|{prs1_rebusys_0_1, io_child_rebusys_0 & io_dis_uops_1_bits_iw_p1_speculative_child_0}) ? io_dis_uops_1_bits_lrs1_rtype_0 == 2'h0 : ~_T_62 & io_dis_uops_1_bits_prs1_busy_0) : _WIRE_prs1_busy;\t// @[issue-unit-age-ordered.scala:22:7, :35:17, :50:95, :57:{32,38}, :58:29, :62:{37,59,106,116}, :63:{29,63}, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_ppred = _T_201 ? io_dis_uops_1_bits_ppred_0 : io_dis_uops_0_bits_ppred_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_prs3 = _T_201 ? io_dis_uops_1_bits_prs3_0 : io_dis_uops_0_bits_prs3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_prs2 = _T_201 ? io_dis_uops_1_bits_prs2_0 : io_dis_uops_0_bits_prs2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_prs1 = _T_201 ? io_dis_uops_1_bits_prs1_0 : io_dis_uops_0_bits_prs1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_pdst = _T_201 ? io_dis_uops_1_bits_pdst_0 : io_dis_uops_0_bits_pdst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_rxq_idx = _T_201 ? io_dis_uops_1_bits_rxq_idx_0 : io_dis_uops_0_bits_rxq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_stq_idx = _T_201 ? io_dis_uops_1_bits_stq_idx_0 : io_dis_uops_0_bits_stq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_ldq_idx = _T_201 ? io_dis_uops_1_bits_ldq_idx_0 : io_dis_uops_0_bits_ldq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_rob_idx = _T_201 ? io_dis_uops_1_bits_rob_idx_0 : io_dis_uops_0_bits_rob_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_fp_ctrl_vec = _T_201 ? io_dis_uops_1_bits_fp_ctrl_vec_0 : io_dis_uops_0_bits_fp_ctrl_vec_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_fp_ctrl_wflags = _T_201 ? io_dis_uops_1_bits_fp_ctrl_wflags_0 : io_dis_uops_0_bits_fp_ctrl_wflags_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_fp_ctrl_sqrt = _T_201 ? io_dis_uops_1_bits_fp_ctrl_sqrt_0 : io_dis_uops_0_bits_fp_ctrl_sqrt_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_fp_ctrl_div = _T_201 ? io_dis_uops_1_bits_fp_ctrl_div_0 : io_dis_uops_0_bits_fp_ctrl_div_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_fp_ctrl_fma = _T_201 ? io_dis_uops_1_bits_fp_ctrl_fma_0 : io_dis_uops_0_bits_fp_ctrl_fma_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_fp_ctrl_fastpipe = _T_201 ? io_dis_uops_1_bits_fp_ctrl_fastpipe_0 : io_dis_uops_0_bits_fp_ctrl_fastpipe_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_fp_ctrl_toint = _T_201 ? io_dis_uops_1_bits_fp_ctrl_toint_0 : io_dis_uops_0_bits_fp_ctrl_toint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_fp_ctrl_fromint = _T_201 ? io_dis_uops_1_bits_fp_ctrl_fromint_0 : io_dis_uops_0_bits_fp_ctrl_fromint_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_fp_ctrl_typeTagOut = _T_201 ? io_dis_uops_1_bits_fp_ctrl_typeTagOut_0 : io_dis_uops_0_bits_fp_ctrl_typeTagOut_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_fp_ctrl_typeTagIn = _T_201 ? io_dis_uops_1_bits_fp_ctrl_typeTagIn_0 : io_dis_uops_0_bits_fp_ctrl_typeTagIn_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_fp_ctrl_swap23 = _T_201 ? io_dis_uops_1_bits_fp_ctrl_swap23_0 : io_dis_uops_0_bits_fp_ctrl_swap23_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_fp_ctrl_swap12 = _T_201 ? io_dis_uops_1_bits_fp_ctrl_swap12_0 : io_dis_uops_0_bits_fp_ctrl_swap12_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_fp_ctrl_ren3 = _T_201 ? io_dis_uops_1_bits_fp_ctrl_ren3_0 : io_dis_uops_0_bits_fp_ctrl_ren3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_fp_ctrl_ren2 = _T_201 ? io_dis_uops_1_bits_fp_ctrl_ren2_0 : io_dis_uops_0_bits_fp_ctrl_ren2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_fp_ctrl_ren1 = _T_201 ? io_dis_uops_1_bits_fp_ctrl_ren1_0 : io_dis_uops_0_bits_fp_ctrl_ren1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_fp_ctrl_wen = _T_201 ? io_dis_uops_1_bits_fp_ctrl_wen_0 : io_dis_uops_0_bits_fp_ctrl_wen_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_fp_ctrl_ldst = _T_201 ? io_dis_uops_1_bits_fp_ctrl_ldst_0 : io_dis_uops_0_bits_fp_ctrl_ldst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_op2_sel = _T_201 ? io_dis_uops_1_bits_op2_sel_0 : io_dis_uops_0_bits_op2_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_op1_sel = _T_201 ? io_dis_uops_1_bits_op1_sel_0 : io_dis_uops_0_bits_op1_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_imm_packed = _T_201 ? io_dis_uops_1_bits_imm_packed_0 : io_dis_uops_0_bits_imm_packed_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_pimm = _T_201 ? io_dis_uops_1_bits_pimm_0 : io_dis_uops_0_bits_pimm_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_imm_sel = _T_201 ? io_dis_uops_1_bits_imm_sel_0 : io_dis_uops_0_bits_imm_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_imm_rename = _T_201 ? io_dis_uops_1_bits_imm_rename_0 : io_dis_uops_0_bits_imm_rename_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_taken = _T_201 ? io_dis_uops_1_bits_taken_0 : io_dis_uops_0_bits_taken_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_pc_lob = _T_201 ? io_dis_uops_1_bits_pc_lob_0 : io_dis_uops_0_bits_pc_lob_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_edge_inst = _T_201 ? io_dis_uops_1_bits_edge_inst_0 : io_dis_uops_0_bits_edge_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_ftq_idx = _T_201 ? io_dis_uops_1_bits_ftq_idx_0 : io_dis_uops_0_bits_ftq_idx_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_is_mov = _T_201 ? io_dis_uops_1_bits_is_mov_0 : io_dis_uops_0_bits_is_mov_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_is_rocc = _T_201 ? io_dis_uops_1_bits_is_rocc_0 : io_dis_uops_0_bits_is_rocc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_is_sys_pc2epc = _T_201 ? io_dis_uops_1_bits_is_sys_pc2epc_0 : io_dis_uops_0_bits_is_sys_pc2epc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_is_eret = _T_201 ? io_dis_uops_1_bits_is_eret_0 : io_dis_uops_0_bits_is_eret_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_is_amo = _T_201 ? io_dis_uops_1_bits_is_amo_0 : io_dis_uops_0_bits_is_amo_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_is_sfence = _T_201 ? io_dis_uops_1_bits_is_sfence_0 : io_dis_uops_0_bits_is_sfence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_is_fencei = _T_201 ? io_dis_uops_1_bits_is_fencei_0 : io_dis_uops_0_bits_is_fencei_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_is_fence = _T_201 ? io_dis_uops_1_bits_is_fence_0 : io_dis_uops_0_bits_is_fence_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_is_sfb = _T_201 ? io_dis_uops_1_bits_is_sfb_0 : io_dis_uops_0_bits_is_sfb_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_br_type = _T_201 ? io_dis_uops_1_bits_br_type_0 : io_dis_uops_0_bits_br_type_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_br_tag = _T_201 ? io_dis_uops_1_bits_br_tag_0 : io_dis_uops_0_bits_br_tag_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_br_mask = _T_201 ? io_dis_uops_1_bits_br_mask_0 : io_dis_uops_0_bits_br_mask_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_dis_col_sel = _T_201 ? io_dis_uops_1_bits_dis_col_sel_0 : io_dis_uops_0_bits_dis_col_sel_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_iw_p3_bypass_hint = _T_201 ? _T_110 & (prs3_wakeups_0_1 & io_wakeup_ports_0_bits_bypassable_0 | prs3_wakeups_2_1 | prs3_wakeups_3_1) : _WIRE_iw_p3_bypass_hint;\t// @[Mux.scala:30:73]\n assign issue_slots_19_in_uop_bits_iw_p2_bypass_hint = _T_201 ? _T_86 & (prs2_wakeups_0_1 & io_wakeup_ports_0_bits_bypassable_0 | prs2_wakeups_2_1 | prs2_wakeups_3_1) : _WIRE_iw_p2_bypass_hint;\t// @[Mux.scala:30:73]\n assign issue_slots_19_in_uop_bits_iw_p1_bypass_hint = _T_201 ? _T_62 & (prs1_wakeups_0_1 & io_wakeup_ports_0_bits_bypassable_0 | prs1_wakeups_2_1 | prs1_wakeups_3_1) : _WIRE_iw_p1_bypass_hint;\t// @[Mux.scala:30:73]\n assign issue_slots_19_in_uop_bits_iw_p2_speculative_child = _T_201 ? (_T_86 ? (prs2_wakeups_0_1 ? io_wakeup_ports_0_bits_speculative_mask_0 : 2'h0) | {prs2_wakeups_3_1, prs2_wakeups_2_1} : io_dis_uops_1_bits_iw_p2_speculative_child_0) : _WIRE_iw_p2_speculative_child;\t// @[Mux.scala:30:73]\n assign issue_slots_19_in_uop_bits_iw_p1_speculative_child = _T_201 ? (_T_62 ? (prs1_wakeups_0_1 ? io_wakeup_ports_0_bits_speculative_mask_0 : 2'h0) | {prs1_wakeups_3_1, prs1_wakeups_2_1} : io_dis_uops_1_bits_iw_p1_speculative_child_0) : _WIRE_iw_p1_speculative_child;\t// @[Mux.scala:30:73]\n assign issue_slots_19_in_uop_bits_fu_code_0 = _T_201 ? io_dis_uops_1_bits_fu_code_0_0 : io_dis_uops_0_bits_fu_code_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_fu_code_1 = _T_201 ? io_dis_uops_1_bits_fu_code_1_0 : io_dis_uops_0_bits_fu_code_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_fu_code_2 = _T_201 ? io_dis_uops_1_bits_fu_code_2_0 : io_dis_uops_0_bits_fu_code_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_fu_code_3 = _T_201 ? io_dis_uops_1_bits_fu_code_3_0 : io_dis_uops_0_bits_fu_code_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_fu_code_4 = _T_201 ? io_dis_uops_1_bits_fu_code_4_0 : io_dis_uops_0_bits_fu_code_4_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_fu_code_5 = _T_201 ? io_dis_uops_1_bits_fu_code_5_0 : io_dis_uops_0_bits_fu_code_5_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_fu_code_6 = _T_201 ? io_dis_uops_1_bits_fu_code_6_0 : io_dis_uops_0_bits_fu_code_6_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_fu_code_7 = _T_201 ? io_dis_uops_1_bits_fu_code_7_0 : io_dis_uops_0_bits_fu_code_7_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_fu_code_8 = _T_201 ? io_dis_uops_1_bits_fu_code_8_0 : io_dis_uops_0_bits_fu_code_8_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_fu_code_9 = _T_201 ? io_dis_uops_1_bits_fu_code_9_0 : io_dis_uops_0_bits_fu_code_9_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_iq_type_0 = _T_201 ? io_dis_uops_1_bits_iq_type_0_0 : io_dis_uops_0_bits_iq_type_0_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_iq_type_1 = _T_201 ? io_dis_uops_1_bits_iq_type_1_0 : io_dis_uops_0_bits_iq_type_1_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_iq_type_2 = _T_201 ? io_dis_uops_1_bits_iq_type_2_0 : io_dis_uops_0_bits_iq_type_2_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_iq_type_3 = _T_201 ? io_dis_uops_1_bits_iq_type_3_0 : io_dis_uops_0_bits_iq_type_3_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_debug_pc = _T_201 ? io_dis_uops_1_bits_debug_pc_0 : io_dis_uops_0_bits_debug_pc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_is_rvc = _T_201 ? io_dis_uops_1_bits_is_rvc_0 : io_dis_uops_0_bits_is_rvc_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_debug_inst = _T_201 ? io_dis_uops_1_bits_debug_inst_0 : io_dis_uops_0_bits_debug_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign issue_slots_19_in_uop_bits_inst = _T_201 ? io_dis_uops_1_bits_inst_0 : io_dis_uops_0_bits_inst_0;\t// @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]\n assign _issue_slots_19_clear_T = |shamts_oh_19;\t// @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49]\n assign issue_slots_19_clear = _issue_slots_19_clear_T;\t// @[issue-unit-age-ordered.scala:122:28, :199:49]\n reg is_available_0;\t// @[issue-unit-age-ordered.scala:208:25]\n reg is_available_1;\t// @[issue-unit-age-ordered.scala:208:25]\n reg is_available_2;\t// @[issue-unit-age-ordered.scala:208:25]\n reg is_available_3;\t// @[issue-unit-age-ordered.scala:208:25]\n reg is_available_4;\t// @[issue-unit-age-ordered.scala:208:25]\n reg is_available_5;\t// @[issue-unit-age-ordered.scala:208:25]\n reg is_available_6;\t// @[issue-unit-age-ordered.scala:208:25]\n reg is_available_7;\t// @[issue-unit-age-ordered.scala:208:25]\n reg is_available_8;\t// @[issue-unit-age-ordered.scala:208:25]\n reg is_available_9;\t// @[issue-unit-age-ordered.scala:208:25]\n reg is_available_10;\t// @[issue-unit-age-ordered.scala:208:25]\n reg is_available_11;\t// @[issue-unit-age-ordered.scala:208:25]\n reg is_available_12;\t// @[issue-unit-age-ordered.scala:208:25]\n reg is_available_13;\t// @[issue-unit-age-ordered.scala:208:25]\n reg is_available_14;\t// @[issue-unit-age-ordered.scala:208:25]\n reg is_available_15;\t// @[issue-unit-age-ordered.scala:208:25]\n reg is_available_16;\t// @[issue-unit-age-ordered.scala:208:25]\n reg is_available_17;\t// @[issue-unit-age-ordered.scala:208:25]\n reg is_available_18;\t// @[issue-unit-age-ordered.scala:208:25]\n reg is_available_19;\t// @[issue-unit-age-ordered.scala:208:25]\n wire [1:0] _GEN = {1'h0, is_available_0} + {1'h0, is_available_1};\t// @[issue-unit-age-ordered.scala:208:25, :212:45]\n wire [1:0] _io_dis_uops_0_ready_T;\t// @[issue-unit-age-ordered.scala:212:45]\n assign _io_dis_uops_0_ready_T = _GEN;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [1:0] _io_dis_uops_1_ready_T;\t// @[issue-unit-age-ordered.scala:212:45]\n assign _io_dis_uops_1_ready_T = _GEN;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [1:0] _io_dis_uops_0_ready_T_1 = _io_dis_uops_0_ready_T;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [1:0] _GEN_0 = {1'h0, is_available_3} + {1'h0, is_available_4};\t// @[issue-unit-age-ordered.scala:208:25, :212:45]\n wire [1:0] _io_dis_uops_0_ready_T_2;\t// @[issue-unit-age-ordered.scala:212:45]\n assign _io_dis_uops_0_ready_T_2 = _GEN_0;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [1:0] _io_dis_uops_1_ready_T_2;\t// @[issue-unit-age-ordered.scala:212:45]\n assign _io_dis_uops_1_ready_T_2 = _GEN_0;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [1:0] _io_dis_uops_0_ready_T_3 = _io_dis_uops_0_ready_T_2;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [2:0] _GEN_1 = {2'h0, is_available_2};\t// @[issue-unit-age-ordered.scala:208:25, :212:45]\n wire [2:0] _io_dis_uops_0_ready_T_4 = _GEN_1 + {1'h0, _io_dis_uops_0_ready_T_3};\t// @[issue-unit-age-ordered.scala:212:45]\n wire [1:0] _io_dis_uops_0_ready_T_5 = _io_dis_uops_0_ready_T_4[1:0];\t// @[issue-unit-age-ordered.scala:212:45]\n wire [2:0] _io_dis_uops_0_ready_T_6 = {1'h0, _io_dis_uops_0_ready_T_1} + {1'h0, _io_dis_uops_0_ready_T_5};\t// @[issue-unit-age-ordered.scala:212:45]\n wire [2:0] _io_dis_uops_0_ready_T_7 = _io_dis_uops_0_ready_T_6;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [1:0] _GEN_2 = {1'h0, is_available_5} + {1'h0, is_available_6};\t// @[issue-unit-age-ordered.scala:208:25, :212:45]\n wire [1:0] _io_dis_uops_0_ready_T_8;\t// @[issue-unit-age-ordered.scala:212:45]\n assign _io_dis_uops_0_ready_T_8 = _GEN_2;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [1:0] _io_dis_uops_1_ready_T_8;\t// @[issue-unit-age-ordered.scala:212:45]\n assign _io_dis_uops_1_ready_T_8 = _GEN_2;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [1:0] _io_dis_uops_0_ready_T_9 = _io_dis_uops_0_ready_T_8;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [1:0] _GEN_3 = {1'h0, is_available_8} + {1'h0, is_available_9};\t// @[issue-unit-age-ordered.scala:208:25, :212:45]\n wire [1:0] _io_dis_uops_0_ready_T_10;\t// @[issue-unit-age-ordered.scala:212:45]\n assign _io_dis_uops_0_ready_T_10 = _GEN_3;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [1:0] _io_dis_uops_1_ready_T_10;\t// @[issue-unit-age-ordered.scala:212:45]\n assign _io_dis_uops_1_ready_T_10 = _GEN_3;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [1:0] _io_dis_uops_0_ready_T_11 = _io_dis_uops_0_ready_T_10;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [2:0] _GEN_4 = {2'h0, is_available_7};\t// @[issue-unit-age-ordered.scala:208:25, :212:45]\n wire [2:0] _io_dis_uops_0_ready_T_12 = _GEN_4 + {1'h0, _io_dis_uops_0_ready_T_11};\t// @[issue-unit-age-ordered.scala:212:45]\n wire [1:0] _io_dis_uops_0_ready_T_13 = _io_dis_uops_0_ready_T_12[1:0];\t// @[issue-unit-age-ordered.scala:212:45]\n wire [2:0] _io_dis_uops_0_ready_T_14 = {1'h0, _io_dis_uops_0_ready_T_9} + {1'h0, _io_dis_uops_0_ready_T_13};\t// @[issue-unit-age-ordered.scala:212:45]\n wire [2:0] _io_dis_uops_0_ready_T_15 = _io_dis_uops_0_ready_T_14;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [3:0] _io_dis_uops_0_ready_T_16 = {1'h0, _io_dis_uops_0_ready_T_7} + {1'h0, _io_dis_uops_0_ready_T_15};\t// @[issue-unit-age-ordered.scala:212:45]\n wire [3:0] _io_dis_uops_0_ready_T_17 = _io_dis_uops_0_ready_T_16;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [1:0] _GEN_5 = {1'h0, is_available_10} + {1'h0, is_available_11};\t// @[issue-unit-age-ordered.scala:208:25, :212:45]\n wire [1:0] _io_dis_uops_0_ready_T_18;\t// @[issue-unit-age-ordered.scala:212:45]\n assign _io_dis_uops_0_ready_T_18 = _GEN_5;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [1:0] _io_dis_uops_1_ready_T_18;\t// @[issue-unit-age-ordered.scala:212:45]\n assign _io_dis_uops_1_ready_T_18 = _GEN_5;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [1:0] _io_dis_uops_0_ready_T_19 = _io_dis_uops_0_ready_T_18;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [1:0] _GEN_6 = {1'h0, is_available_13} + {1'h0, is_available_14};\t// @[issue-unit-age-ordered.scala:208:25, :212:45]\n wire [1:0] _io_dis_uops_0_ready_T_20;\t// @[issue-unit-age-ordered.scala:212:45]\n assign _io_dis_uops_0_ready_T_20 = _GEN_6;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [1:0] _io_dis_uops_1_ready_T_20;\t// @[issue-unit-age-ordered.scala:212:45]\n assign _io_dis_uops_1_ready_T_20 = _GEN_6;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [1:0] _io_dis_uops_0_ready_T_21 = _io_dis_uops_0_ready_T_20;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [2:0] _GEN_7 = {2'h0, is_available_12};\t// @[issue-unit-age-ordered.scala:208:25, :212:45]\n wire [2:0] _io_dis_uops_0_ready_T_22 = _GEN_7 + {1'h0, _io_dis_uops_0_ready_T_21};\t// @[issue-unit-age-ordered.scala:212:45]\n wire [1:0] _io_dis_uops_0_ready_T_23 = _io_dis_uops_0_ready_T_22[1:0];\t// @[issue-unit-age-ordered.scala:212:45]\n wire [2:0] _io_dis_uops_0_ready_T_24 = {1'h0, _io_dis_uops_0_ready_T_19} + {1'h0, _io_dis_uops_0_ready_T_23};\t// @[issue-unit-age-ordered.scala:212:45]\n wire [2:0] _io_dis_uops_0_ready_T_25 = _io_dis_uops_0_ready_T_24;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [1:0] _GEN_8 = {1'h0, is_available_15} + {1'h0, is_available_16};\t// @[issue-unit-age-ordered.scala:208:25, :212:45]\n wire [1:0] _io_dis_uops_0_ready_T_26;\t// @[issue-unit-age-ordered.scala:212:45]\n assign _io_dis_uops_0_ready_T_26 = _GEN_8;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [1:0] _io_dis_uops_1_ready_T_26;\t// @[issue-unit-age-ordered.scala:212:45]\n assign _io_dis_uops_1_ready_T_26 = _GEN_8;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [1:0] _io_dis_uops_0_ready_T_27 = _io_dis_uops_0_ready_T_26;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [1:0] _GEN_9 = {1'h0, is_available_18} + {1'h0, is_available_19};\t// @[issue-unit-age-ordered.scala:208:25, :212:45]\n wire [1:0] _io_dis_uops_0_ready_T_28;\t// @[issue-unit-age-ordered.scala:212:45]\n assign _io_dis_uops_0_ready_T_28 = _GEN_9;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [1:0] _io_dis_uops_1_ready_T_28;\t// @[issue-unit-age-ordered.scala:212:45]\n assign _io_dis_uops_1_ready_T_28 = _GEN_9;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [1:0] _io_dis_uops_0_ready_T_29 = _io_dis_uops_0_ready_T_28;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [2:0] _GEN_10 = {2'h0, is_available_17};\t// @[issue-unit-age-ordered.scala:208:25, :212:45]\n wire [2:0] _io_dis_uops_0_ready_T_30 = _GEN_10 + {1'h0, _io_dis_uops_0_ready_T_29};\t// @[issue-unit-age-ordered.scala:212:45]\n wire [1:0] _io_dis_uops_0_ready_T_31 = _io_dis_uops_0_ready_T_30[1:0];\t// @[issue-unit-age-ordered.scala:212:45]\n wire [2:0] _io_dis_uops_0_ready_T_32 = {1'h0, _io_dis_uops_0_ready_T_27} + {1'h0, _io_dis_uops_0_ready_T_31};\t// @[issue-unit-age-ordered.scala:212:45]\n wire [2:0] _io_dis_uops_0_ready_T_33 = _io_dis_uops_0_ready_T_32;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [3:0] _io_dis_uops_0_ready_T_34 = {1'h0, _io_dis_uops_0_ready_T_25} + {1'h0, _io_dis_uops_0_ready_T_33};\t// @[issue-unit-age-ordered.scala:212:45]\n wire [3:0] _io_dis_uops_0_ready_T_35 = _io_dis_uops_0_ready_T_34;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [4:0] _io_dis_uops_0_ready_T_36 = {1'h0, _io_dis_uops_0_ready_T_17} + {1'h0, _io_dis_uops_0_ready_T_35};\t// @[issue-unit-age-ordered.scala:212:45]\n wire [4:0] _io_dis_uops_0_ready_T_37 = _io_dis_uops_0_ready_T_36;\t// @[issue-unit-age-ordered.scala:212:45]\n wire _GEN_11 = io_dis_uops_0_ready_0 & io_dis_uops_0_valid_0;\t// @[Decoupled.scala:51:35]\n wire _io_dis_uops_0_ready_T_38;\t// @[Decoupled.scala:51:35]\n assign _io_dis_uops_0_ready_T_38 = _GEN_11;\t// @[Decoupled.scala:51:35]\n wire _io_dis_uops_1_ready_T_38;\t// @[Decoupled.scala:51:35]\n assign _io_dis_uops_1_ready_T_38 = _GEN_11;\t// @[Decoupled.scala:51:35]\n wire _GEN_12 = io_dis_uops_1_ready_0 & io_dis_uops_1_valid_0;\t// @[Decoupled.scala:51:35]\n wire _io_dis_uops_0_ready_T_39;\t// @[Decoupled.scala:51:35]\n assign _io_dis_uops_0_ready_T_39 = _GEN_12;\t// @[Decoupled.scala:51:35]\n wire _io_dis_uops_1_ready_T_39;\t// @[Decoupled.scala:51:35]\n assign _io_dis_uops_1_ready_T_39 = _GEN_12;\t// @[Decoupled.scala:51:35]\n wire [1:0] _io_dis_uops_0_ready_T_40 = {1'h0, _io_dis_uops_0_ready_T_38} + {1'h0, _io_dis_uops_0_ready_T_39};\t// @[Decoupled.scala:51:35]\n wire [1:0] _io_dis_uops_0_ready_T_41 = _io_dis_uops_0_ready_T_40;\t// @[issue-unit-age-ordered.scala:212:100]\n wire [5:0] _io_dis_uops_0_ready_T_42 = {4'h0, _io_dis_uops_0_ready_T_41};\t// @[issue-unit-age-ordered.scala:212:{90,100}]\n wire [4:0] _io_dis_uops_0_ready_T_43 = _io_dis_uops_0_ready_T_42[4:0];\t// @[issue-unit-age-ordered.scala:212:90]\n wire _io_dis_uops_0_ready_T_44 = _io_dis_uops_0_ready_T_37 > _io_dis_uops_0_ready_T_43;\t// @[issue-unit-age-ordered.scala:212:{45,60,90}]\n reg io_dis_uops_0_ready_REG;\t// @[issue-unit-age-ordered.scala:212:36]\n assign io_dis_uops_0_ready_0 = io_dis_uops_0_ready_REG;\t// @[issue-unit-age-ordered.scala:22:7, :212:36]\n wire [1:0] _io_dis_uops_1_ready_T_1 = _io_dis_uops_1_ready_T;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [1:0] _io_dis_uops_1_ready_T_3 = _io_dis_uops_1_ready_T_2;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [2:0] _io_dis_uops_1_ready_T_4 = _GEN_1 + {1'h0, _io_dis_uops_1_ready_T_3};\t// @[issue-unit-age-ordered.scala:212:45]\n wire [1:0] _io_dis_uops_1_ready_T_5 = _io_dis_uops_1_ready_T_4[1:0];\t// @[issue-unit-age-ordered.scala:212:45]\n wire [2:0] _io_dis_uops_1_ready_T_6 = {1'h0, _io_dis_uops_1_ready_T_1} + {1'h0, _io_dis_uops_1_ready_T_5};\t// @[issue-unit-age-ordered.scala:212:45]\n wire [2:0] _io_dis_uops_1_ready_T_7 = _io_dis_uops_1_ready_T_6;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [1:0] _io_dis_uops_1_ready_T_9 = _io_dis_uops_1_ready_T_8;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [1:0] _io_dis_uops_1_ready_T_11 = _io_dis_uops_1_ready_T_10;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [2:0] _io_dis_uops_1_ready_T_12 = _GEN_4 + {1'h0, _io_dis_uops_1_ready_T_11};\t// @[issue-unit-age-ordered.scala:212:45]\n wire [1:0] _io_dis_uops_1_ready_T_13 = _io_dis_uops_1_ready_T_12[1:0];\t// @[issue-unit-age-ordered.scala:212:45]\n wire [2:0] _io_dis_uops_1_ready_T_14 = {1'h0, _io_dis_uops_1_ready_T_9} + {1'h0, _io_dis_uops_1_ready_T_13};\t// @[issue-unit-age-ordered.scala:212:45]\n wire [2:0] _io_dis_uops_1_ready_T_15 = _io_dis_uops_1_ready_T_14;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [3:0] _io_dis_uops_1_ready_T_16 = {1'h0, _io_dis_uops_1_ready_T_7} + {1'h0, _io_dis_uops_1_ready_T_15};\t// @[issue-unit-age-ordered.scala:212:45]\n wire [3:0] _io_dis_uops_1_ready_T_17 = _io_dis_uops_1_ready_T_16;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [1:0] _io_dis_uops_1_ready_T_19 = _io_dis_uops_1_ready_T_18;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [1:0] _io_dis_uops_1_ready_T_21 = _io_dis_uops_1_ready_T_20;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [2:0] _io_dis_uops_1_ready_T_22 = _GEN_7 + {1'h0, _io_dis_uops_1_ready_T_21};\t// @[issue-unit-age-ordered.scala:212:45]\n wire [1:0] _io_dis_uops_1_ready_T_23 = _io_dis_uops_1_ready_T_22[1:0];\t// @[issue-unit-age-ordered.scala:212:45]\n wire [2:0] _io_dis_uops_1_ready_T_24 = {1'h0, _io_dis_uops_1_ready_T_19} + {1'h0, _io_dis_uops_1_ready_T_23};\t// @[issue-unit-age-ordered.scala:212:45]\n wire [2:0] _io_dis_uops_1_ready_T_25 = _io_dis_uops_1_ready_T_24;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [1:0] _io_dis_uops_1_ready_T_27 = _io_dis_uops_1_ready_T_26;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [1:0] _io_dis_uops_1_ready_T_29 = _io_dis_uops_1_ready_T_28;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [2:0] _io_dis_uops_1_ready_T_30 = _GEN_10 + {1'h0, _io_dis_uops_1_ready_T_29};\t// @[issue-unit-age-ordered.scala:212:45]\n wire [1:0] _io_dis_uops_1_ready_T_31 = _io_dis_uops_1_ready_T_30[1:0];\t// @[issue-unit-age-ordered.scala:212:45]\n wire [2:0] _io_dis_uops_1_ready_T_32 = {1'h0, _io_dis_uops_1_ready_T_27} + {1'h0, _io_dis_uops_1_ready_T_31};\t// @[issue-unit-age-ordered.scala:212:45]\n wire [2:0] _io_dis_uops_1_ready_T_33 = _io_dis_uops_1_ready_T_32;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [3:0] _io_dis_uops_1_ready_T_34 = {1'h0, _io_dis_uops_1_ready_T_25} + {1'h0, _io_dis_uops_1_ready_T_33};\t// @[issue-unit-age-ordered.scala:212:45]\n wire [3:0] _io_dis_uops_1_ready_T_35 = _io_dis_uops_1_ready_T_34;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [4:0] _io_dis_uops_1_ready_T_36 = {1'h0, _io_dis_uops_1_ready_T_17} + {1'h0, _io_dis_uops_1_ready_T_35};\t// @[issue-unit-age-ordered.scala:212:45]\n wire [4:0] _io_dis_uops_1_ready_T_37 = _io_dis_uops_1_ready_T_36;\t// @[issue-unit-age-ordered.scala:212:45]\n wire [1:0] _io_dis_uops_1_ready_T_40 = {1'h0, _io_dis_uops_1_ready_T_38} + {1'h0, _io_dis_uops_1_ready_T_39};\t// @[Decoupled.scala:51:35]\n wire [1:0] _io_dis_uops_1_ready_T_41 = _io_dis_uops_1_ready_T_40;\t// @[issue-unit-age-ordered.scala:212:100]\n wire [5:0] _io_dis_uops_1_ready_T_42 = {4'h0, _io_dis_uops_1_ready_T_41} + 6'h1;\t// @[issue-unit-age-ordered.scala:212:{90,100}]\n wire [4:0] _io_dis_uops_1_ready_T_43 = _io_dis_uops_1_ready_T_42[4:0];\t// @[issue-unit-age-ordered.scala:212:90]\n wire _io_dis_uops_1_ready_T_44 = _io_dis_uops_1_ready_T_37 > _io_dis_uops_1_ready_T_43;\t// @[issue-unit-age-ordered.scala:212:{45,60,90}]\n reg io_dis_uops_1_ready_REG;\t// @[issue-unit-age-ordered.scala:212:36]\n assign io_dis_uops_1_ready_0 = io_dis_uops_1_ready_REG;\t// @[issue-unit-age-ordered.scala:22:7, :212:36]"}}},{"rowIdx":34394,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module InputUnit_44 : \n input clock : Clock \n input reset : Reset \n output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}}}, flip vcalloc_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, flip out_credit_available : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}[1], debug : { va_stall : UInt<2>, sa_stall : UInt<2>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}} \n\n\n inst input_buffer of InputBuffer_44 \n connect input_buffer.clock, clock\n\n connect input_buffer.reset, reset\n\n connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id \n connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id \n connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node \n connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id \n connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node \n connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id \n connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload \n connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail \n connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head \n connect input_buffer.io.enq[0].valid, io.in.flit[0].valid \n connect input_buffer.io.deq[0].ready, UInt<1>(0h0) \n connect input_buffer.io.deq[1].ready, UInt<1>(0h0) \n connect input_buffer.io.deq[2].ready, UInt<1>(0h0) \n inst route_arbiter of Arbiter3_RouteComputerReq_44 \n connect route_arbiter.clock, clock\n\n connect route_arbiter.reset, reset\n\n connect io.router_req.bits, route_arbiter.io.out.bits \n connect io.router_req.valid, route_arbiter.io.out.valid \n connect route_arbiter.io.out.ready, io.router_req.ready \n reg states : { g : UInt<3>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, fifo_deps : UInt<3>}[3], clock \n node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) \n when _T : \n node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3)) \n node _T_2 = asUInt(reset) \n node _T_3 = eq(_T_2, UInt<1>(0h0)) \n when _T_3 : \n node _T_4 = eq(_T_1, UInt<1>(0h0)) \n when _T_4 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\\n\") : printf \n assert(clock, _T_1, UInt<1>(0h1), \"\") : assert \n node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) \n node _T_6 = asUInt(reset) \n node _T_7 = eq(_T_6, UInt<1>(0h0)) \n when _T_7 : \n node _T_8 = eq(_T_5, UInt<1>(0h0)) \n when _T_8 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at InputUnit.scala:208 assert(states(id).g === g_i)\\n\") : printf_1 \n assert(clock, _T_5, UInt<1>(0h1), \"\") : assert_1 \n node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0he)) \n node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) \n connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T \n connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) \n connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) \n connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0) \n connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) \n connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0) \n connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0) \n connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0) \n node _T_9 = eq(UInt<1>(0h0), io.in.flit[0].bits.flow.egress_node_id) \n when _T_9 : \n connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h1) \n connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow \n connect route_arbiter.io.in[0].valid, UInt<1>(0h0) \n invalidate route_arbiter.io.in[0].bits.flow.egress_node_id \n invalidate route_arbiter.io.in[0].bits.flow.egress_node \n invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id \n invalidate route_arbiter.io.in[0].bits.flow.ingress_node \n invalidate route_arbiter.io.in[0].bits.flow.vnet_id \n invalidate route_arbiter.io.in[0].bits.src_virt_id \n node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1)) \n connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T \n connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id \n connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node \n connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id \n connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node \n connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id \n connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1) \n node _T_10 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) \n when _T_10 : \n connect states[1].g, UInt<3>(0h2) \n node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1)) \n connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T \n connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id \n connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node \n connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id \n connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node \n connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id \n connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2) \n node _T_11 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid) \n when _T_11 : \n connect states[2].g, UInt<3>(0h2) \n node _T_12 = and(io.router_req.ready, io.router_req.valid) \n when _T_12 : \n node _T_13 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) \n node _T_14 = asUInt(reset) \n node _T_15 = eq(_T_14, UInt<1>(0h0)) \n when _T_15 : \n node _T_16 = eq(_T_13, UInt<1>(0h0)) \n when _T_16 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at InputUnit.scala:241 assert(states(id).g === g_r)\\n\") : printf_2 \n assert(clock, _T_13, UInt<1>(0h1), \"\") : assert_2 \n connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) \n node _T_17 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) \n when _T_17 : \n connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` \n connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` \n connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2` \n node _T_18 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) \n when _T_18 : \n connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` \n connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` \n connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2` \n node _T_19 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id) \n when _T_19 : \n connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0` \n connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1` \n connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2` \n regreset mask : UInt<3>, clock, reset, UInt<3>(0h0) \n wire vcalloc_reqs : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}}[3] \n wire vcalloc_vals : UInt<1>[3] \n node vcalloc_filter_hi = cat(vcalloc_vals[2], vcalloc_vals[1]) \n node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_vals[0]) \n node vcalloc_filter_hi_1 = cat(vcalloc_vals[2], vcalloc_vals[1]) \n node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_vals[0]) \n node _vcalloc_filter_T_2 = not(mask) \n node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) \n node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) \n node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) \n node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) \n node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) \n node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) \n node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4) \n node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5) \n node _vcalloc_filter_T_11 = mux(_vcalloc_filter_T_10, UInt<6>(0h20), UInt<6>(0h0)) \n node _vcalloc_filter_T_12 = mux(_vcalloc_filter_T_9, UInt<6>(0h10), _vcalloc_filter_T_11) \n node _vcalloc_filter_T_13 = mux(_vcalloc_filter_T_8, UInt<6>(0h8), _vcalloc_filter_T_12) \n node _vcalloc_filter_T_14 = mux(_vcalloc_filter_T_7, UInt<6>(0h4), _vcalloc_filter_T_13) \n node _vcalloc_filter_T_15 = mux(_vcalloc_filter_T_6, UInt<6>(0h2), _vcalloc_filter_T_14) \n node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<6>(0h1), _vcalloc_filter_T_15) \n node _vcalloc_sel_T = bits(vcalloc_filter, 2, 0) \n node _vcalloc_sel_T_1 = shr(vcalloc_filter, 3) \n node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) \n node _T_20 = and(io.router_req.ready, io.router_req.valid) \n when _T_20 : \n node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) \n node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) \n node _mask_T_2 = tail(_mask_T_1, 1) \n connect mask, _mask_T_2 \n else :\n\n node _T_21 = or(vcalloc_vals[0], vcalloc_vals[1]) \n node _T_22 = or(_T_21, vcalloc_vals[2]) \n when _T_22 : \n node _mask_T_3 = not(UInt<1>(0h0)) \n node _mask_T_4 = not(UInt<2>(0h0)) \n node _mask_T_5 = not(UInt<3>(0h0)) \n node _mask_T_6 = bits(vcalloc_sel, 0, 0) \n node _mask_T_7 = bits(vcalloc_sel, 1, 1) \n node _mask_T_8 = bits(vcalloc_sel, 2, 2) \n node _mask_T_9 = mux(_mask_T_6, _mask_T_3, UInt<1>(0h0)) \n node _mask_T_10 = mux(_mask_T_7, _mask_T_4, UInt<1>(0h0)) \n node _mask_T_11 = mux(_mask_T_8, _mask_T_5, UInt<1>(0h0)) \n node _mask_T_12 = or(_mask_T_9, _mask_T_10) \n node _mask_T_13 = or(_mask_T_12, _mask_T_11) \n wire _mask_WIRE : UInt<3> \n connect _mask_WIRE, _mask_T_13 \n connect mask, _mask_WIRE \n node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) \n node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2]) \n connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_1 \n node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) \n node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) \n node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2) \n wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}} \n wire _io_vcalloc_req_bits_WIRE_1 : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]} \n wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[3] \n node _io_vcalloc_req_bits_T_3 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_4 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_5 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_6 = or(_io_vcalloc_req_bits_T_3, _io_vcalloc_req_bits_T_4) \n node _io_vcalloc_req_bits_T_7 = or(_io_vcalloc_req_bits_T_6, _io_vcalloc_req_bits_T_5) \n wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> \n connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_7 \n connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 \n node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_11 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9) \n node _io_vcalloc_req_bits_T_12 = or(_io_vcalloc_req_bits_T_11, _io_vcalloc_req_bits_T_10) \n wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> \n connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_12 \n connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 \n node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_13, _io_vcalloc_req_bits_T_14) \n node _io_vcalloc_req_bits_T_17 = or(_io_vcalloc_req_bits_T_16, _io_vcalloc_req_bits_T_15) \n wire _io_vcalloc_req_bits_WIRE_5 : UInt<1> \n connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_17 \n connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5 \n connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 \n wire _io_vcalloc_req_bits_WIRE_6 : UInt<1>[3] \n node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_19 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_20 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_18, _io_vcalloc_req_bits_T_19) \n node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_20) \n wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> \n connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_22 \n connect _io_vcalloc_req_bits_WIRE_6[0], _io_vcalloc_req_bits_WIRE_7 \n node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_26 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24) \n node _io_vcalloc_req_bits_T_27 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_25) \n wire _io_vcalloc_req_bits_WIRE_8 : UInt<1> \n connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_27 \n connect _io_vcalloc_req_bits_WIRE_6[1], _io_vcalloc_req_bits_WIRE_8 \n node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_28, _io_vcalloc_req_bits_T_29) \n node _io_vcalloc_req_bits_T_32 = or(_io_vcalloc_req_bits_T_31, _io_vcalloc_req_bits_T_30) \n wire _io_vcalloc_req_bits_WIRE_9 : UInt<1> \n connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_32 \n connect _io_vcalloc_req_bits_WIRE_6[2], _io_vcalloc_req_bits_WIRE_9 \n connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_6 \n wire _io_vcalloc_req_bits_WIRE_10 : UInt<1>[1] \n node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_34 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_33, _io_vcalloc_req_bits_T_34) \n node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_35) \n wire _io_vcalloc_req_bits_WIRE_11 : UInt<1> \n connect _io_vcalloc_req_bits_WIRE_11, _io_vcalloc_req_bits_T_37 \n connect _io_vcalloc_req_bits_WIRE_10[0], _io_vcalloc_req_bits_WIRE_11 \n connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_10 \n connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 \n node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_41 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39) \n node _io_vcalloc_req_bits_T_42 = or(_io_vcalloc_req_bits_T_41, _io_vcalloc_req_bits_T_40) \n wire _io_vcalloc_req_bits_WIRE_12 : UInt<2> \n connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_42 \n connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_12 \n wire _io_vcalloc_req_bits_WIRE_13 : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>} \n node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_43, _io_vcalloc_req_bits_T_44) \n node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_45) \n wire _io_vcalloc_req_bits_WIRE_14 : UInt<2> \n connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_47 \n connect _io_vcalloc_req_bits_WIRE_13.egress_node_id, _io_vcalloc_req_bits_WIRE_14 \n node _io_vcalloc_req_bits_T_48 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_49 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_50 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_51 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_49) \n node _io_vcalloc_req_bits_T_52 = or(_io_vcalloc_req_bits_T_51, _io_vcalloc_req_bits_T_50) \n wire _io_vcalloc_req_bits_WIRE_15 : UInt<4> \n connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_52 \n connect _io_vcalloc_req_bits_WIRE_13.egress_node, _io_vcalloc_req_bits_WIRE_15 \n node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_56 = or(_io_vcalloc_req_bits_T_53, _io_vcalloc_req_bits_T_54) \n node _io_vcalloc_req_bits_T_57 = or(_io_vcalloc_req_bits_T_56, _io_vcalloc_req_bits_T_55) \n wire _io_vcalloc_req_bits_WIRE_16 : UInt<3> \n connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_57 \n connect _io_vcalloc_req_bits_WIRE_13.ingress_node_id, _io_vcalloc_req_bits_WIRE_16 \n node _io_vcalloc_req_bits_T_58 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_58, _io_vcalloc_req_bits_T_59) \n node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_60) \n wire _io_vcalloc_req_bits_WIRE_17 : UInt<4> \n connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_62 \n connect _io_vcalloc_req_bits_WIRE_13.ingress_node, _io_vcalloc_req_bits_WIRE_17 \n node _io_vcalloc_req_bits_T_63 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_64 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_65 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0)) \n node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_64) \n node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_65) \n wire _io_vcalloc_req_bits_WIRE_18 : UInt<2> \n connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_67 \n connect _io_vcalloc_req_bits_WIRE_13.vnet_id, _io_vcalloc_req_bits_WIRE_18 \n connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_13 \n connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE \n connect vcalloc_vals[0], UInt<1>(0h0) \n invalidate vcalloc_reqs[0].vc_sel.`0`[0] \n invalidate vcalloc_reqs[0].vc_sel.`0`[1] \n invalidate vcalloc_reqs[0].vc_sel.`0`[2] \n invalidate vcalloc_reqs[0].vc_sel.`1`[0] \n invalidate vcalloc_reqs[0].vc_sel.`1`[1] \n invalidate vcalloc_reqs[0].vc_sel.`1`[2] \n invalidate vcalloc_reqs[0].vc_sel.`2`[0] \n invalidate vcalloc_reqs[0].in_vc \n invalidate vcalloc_reqs[0].flow.egress_node_id \n invalidate vcalloc_reqs[0].flow.egress_node \n invalidate vcalloc_reqs[0].flow.ingress_node_id \n invalidate vcalloc_reqs[0].flow.ingress_node \n invalidate vcalloc_reqs[0].flow.vnet_id \n node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2)) \n node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0)) \n node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1) \n connect vcalloc_vals[1], _vcalloc_vals_1_T_2 \n connect vcalloc_reqs[1].in_vc, UInt<1>(0h1) \n connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0` \n connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1` \n connect vcalloc_reqs[1].vc_sel.`2`, states[1].vc_sel.`2` \n connect vcalloc_reqs[1].flow, states[1].flow \n node _T_23 = bits(vcalloc_sel, 1, 1) \n node _T_24 = and(vcalloc_vals[1], _T_23) \n node _T_25 = and(_T_24, io.vcalloc_req.ready) \n when _T_25 : \n connect states[1].g, UInt<3>(0h3) \n node _T_26 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) \n when _T_26 : \n connect vcalloc_vals[1], UInt<1>(0h1) \n connect vcalloc_reqs[1].vc_sel.`0`, io.router_resp.vc_sel.`0` \n connect vcalloc_reqs[1].vc_sel.`1`, io.router_resp.vc_sel.`1` \n connect vcalloc_reqs[1].vc_sel.`2`, io.router_resp.vc_sel.`2` \n node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2)) \n node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0)) \n node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1) \n connect vcalloc_vals[2], _vcalloc_vals_2_T_2 \n connect vcalloc_reqs[2].in_vc, UInt<2>(0h2) \n connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0` \n connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1` \n connect vcalloc_reqs[2].vc_sel.`2`, states[2].vc_sel.`2` \n connect vcalloc_reqs[2].flow, states[2].flow \n node _T_27 = bits(vcalloc_sel, 2, 2) \n node _T_28 = and(vcalloc_vals[2], _T_27) \n node _T_29 = and(_T_28, io.vcalloc_req.ready) \n when _T_29 : \n connect states[2].g, UInt<3>(0h3) \n node _T_30 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid) \n when _T_30 : \n connect vcalloc_vals[2], UInt<1>(0h1) \n connect vcalloc_reqs[2].vc_sel.`0`, io.router_resp.vc_sel.`0` \n connect vcalloc_reqs[2].vc_sel.`1`, io.router_resp.vc_sel.`1` \n connect vcalloc_reqs[2].vc_sel.`2`, io.router_resp.vc_sel.`2` \n node _io_debug_va_stall_T = add(vcalloc_vals[1], vcalloc_vals[2]) \n node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) \n node _io_debug_va_stall_T_2 = add(vcalloc_vals[0], _io_debug_va_stall_T_1) \n node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0) \n node _io_debug_va_stall_T_4 = sub(_io_debug_va_stall_T_3, io.vcalloc_req.ready) \n node _io_debug_va_stall_T_5 = tail(_io_debug_va_stall_T_4, 1) \n connect io.debug.va_stall, _io_debug_va_stall_T_5 \n node _T_31 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) \n when _T_31 : \n node _T_32 = bits(vcalloc_sel, 0, 0) \n when _T_32 : \n connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` \n connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` \n connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` \n connect states[0].g, UInt<3>(0h3) \n node _T_33 = bits(vcalloc_sel, 1, 1) \n when _T_33 : \n connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` \n connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` \n connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` \n connect states[1].g, UInt<3>(0h3) \n node _T_34 = bits(vcalloc_sel, 2, 2) \n when _T_34 : \n connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` \n connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` \n connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` \n connect states[2].g, UInt<3>(0h3) \n inst salloc_arb of SwitchArbiter_108 \n connect salloc_arb.clock, clock\n\n connect salloc_arb.reset, reset\n\n connect salloc_arb.io.in[0].valid, UInt<1>(0h0) \n invalidate salloc_arb.io.in[0].bits.tail \n invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0] \n invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1] \n invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[2] \n invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0] \n invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[1] \n invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[2] \n invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[0] \n node credit_available_hi = cat(states[1].vc_sel.`0`[2], states[1].vc_sel.`0`[1]) \n node _credit_available_T = cat(credit_available_hi, states[1].vc_sel.`0`[0]) \n node credit_available_hi_1 = cat(states[1].vc_sel.`1`[2], states[1].vc_sel.`1`[1]) \n node _credit_available_T_1 = cat(credit_available_hi_1, states[1].vc_sel.`1`[0]) \n node credit_available_hi_2 = cat(states[1].vc_sel.`2`[0], _credit_available_T_1) \n node _credit_available_T_2 = cat(credit_available_hi_2, _credit_available_T) \n node credit_available_hi_3 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) \n node _credit_available_T_3 = cat(credit_available_hi_3, io.out_credit_available.`0`[0]) \n node credit_available_hi_4 = cat(io.out_credit_available.`1`[2], io.out_credit_available.`1`[1]) \n node _credit_available_T_4 = cat(credit_available_hi_4, io.out_credit_available.`1`[0]) \n node credit_available_hi_5 = cat(io.out_credit_available.`2`[0], _credit_available_T_4) \n node _credit_available_T_5 = cat(credit_available_hi_5, _credit_available_T_3) \n node _credit_available_T_6 = and(_credit_available_T_2, _credit_available_T_5) \n node credit_available = neq(_credit_available_T_6, UInt<1>(0h0)) \n node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3)) \n node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available) \n node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid) \n connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2 \n connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0] \n connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1] \n connect salloc_arb.io.in[1].bits.vc_sel.`0`[2], states[1].vc_sel.`0`[2] \n connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0] \n connect salloc_arb.io.in[1].bits.vc_sel.`1`[1], states[1].vc_sel.`1`[1] \n connect salloc_arb.io.in[1].bits.vc_sel.`1`[2], states[1].vc_sel.`1`[2] \n connect salloc_arb.io.in[1].bits.vc_sel.`2`[0], states[1].vc_sel.`2`[0] \n connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail \n node _T_35 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid) \n node _T_36 = and(_T_35, input_buffer.io.deq[1].bits.tail) \n when _T_36 : \n connect states[1].g, UInt<3>(0h0) \n connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready \n node credit_available_hi_6 = cat(states[2].vc_sel.`0`[2], states[2].vc_sel.`0`[1]) \n node _credit_available_T_7 = cat(credit_available_hi_6, states[2].vc_sel.`0`[0]) \n node credit_available_hi_7 = cat(states[2].vc_sel.`1`[2], states[2].vc_sel.`1`[1]) \n node _credit_available_T_8 = cat(credit_available_hi_7, states[2].vc_sel.`1`[0]) \n node credit_available_hi_8 = cat(states[2].vc_sel.`2`[0], _credit_available_T_8) \n node _credit_available_T_9 = cat(credit_available_hi_8, _credit_available_T_7) \n node credit_available_hi_9 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) \n node _credit_available_T_10 = cat(credit_available_hi_9, io.out_credit_available.`0`[0]) \n node credit_available_hi_10 = cat(io.out_credit_available.`1`[2], io.out_credit_available.`1`[1]) \n node _credit_available_T_11 = cat(credit_available_hi_10, io.out_credit_available.`1`[0]) \n node credit_available_hi_11 = cat(io.out_credit_available.`2`[0], _credit_available_T_11) \n node _credit_available_T_12 = cat(credit_available_hi_11, _credit_available_T_10) \n node _credit_available_T_13 = and(_credit_available_T_9, _credit_available_T_12) \n node credit_available_1 = neq(_credit_available_T_13, UInt<1>(0h0)) \n node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3)) \n node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available_1) \n node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid) \n connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2 \n connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0] \n connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1] \n connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2] \n connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0] \n connect salloc_arb.io.in[2].bits.vc_sel.`1`[1], states[2].vc_sel.`1`[1] \n connect salloc_arb.io.in[2].bits.vc_sel.`1`[2], states[2].vc_sel.`1`[2] \n connect salloc_arb.io.in[2].bits.vc_sel.`2`[0], states[2].vc_sel.`2`[0] \n connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail \n node _T_37 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid) \n node _T_38 = and(_T_37, input_buffer.io.deq[2].bits.tail) \n when _T_38 : \n connect states[2].g, UInt<3>(0h0) \n connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready \n node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) \n node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) \n node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) \n node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) \n node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0)) \n node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4) \n node _io_debug_sa_stall_T_6 = add(_io_debug_sa_stall_T_3, _io_debug_sa_stall_T_5) \n node _io_debug_sa_stall_T_7 = bits(_io_debug_sa_stall_T_6, 1, 0) \n node _io_debug_sa_stall_T_8 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_7) \n node _io_debug_sa_stall_T_9 = bits(_io_debug_sa_stall_T_8, 1, 0) \n connect io.debug.sa_stall, _io_debug_sa_stall_T_9 \n connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits \n connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid \n connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready \n when io.block : \n connect salloc_arb.io.out[0].ready, UInt<1>(0h0) \n connect io.salloc_req[0].valid, UInt<1>(0h0) \n wire salloc_outs : { valid : UInt<1>, vid : UInt<2>, out_vid : UInt<2>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1] \n node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) \n node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) \n connect io.in.credit_return, _io_in_credit_return_T_1 \n node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) \n node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) \n node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) \n node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2) \n node _io_in_vc_free_T_4 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) \n node _io_in_vc_free_T_5 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) \n node _io_in_vc_free_T_6 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) \n node _io_in_vc_free_T_7 = or(_io_in_vc_free_T_4, _io_in_vc_free_T_5) \n node _io_in_vc_free_T_8 = or(_io_in_vc_free_T_7, _io_in_vc_free_T_6) \n wire _io_in_vc_free_WIRE : UInt<1> \n connect _io_in_vc_free_WIRE, _io_in_vc_free_T_8 \n node _io_in_vc_free_T_9 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) \n node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_9, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) \n connect io.in.vc_free, _io_in_vc_free_T_10 \n node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) \n connect salloc_outs[0].valid, _salloc_outs_0_valid_T \n node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 2, 2) \n node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 1, 0) \n node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi) \n node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo) \n node _salloc_outs_0_vid_T_2 = bits(_salloc_outs_0_vid_T_1, 1, 1) \n node _salloc_outs_0_vid_T_3 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_2) \n connect salloc_outs[0].vid, _salloc_outs_0_vid_T_3 \n node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) \n node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) \n node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) \n wire vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]} \n wire _vc_sel_WIRE : UInt<1>[3] \n node _vc_sel_T_3 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) \n node _vc_sel_T_4 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) \n node _vc_sel_T_5 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0)) \n node _vc_sel_T_6 = or(_vc_sel_T_3, _vc_sel_T_4) \n node _vc_sel_T_7 = or(_vc_sel_T_6, _vc_sel_T_5) \n wire _vc_sel_WIRE_1 : UInt<1> \n connect _vc_sel_WIRE_1, _vc_sel_T_7 \n connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 \n node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) \n node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) \n node _vc_sel_T_10 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0)) \n node _vc_sel_T_11 = or(_vc_sel_T_8, _vc_sel_T_9) \n node _vc_sel_T_12 = or(_vc_sel_T_11, _vc_sel_T_10) \n wire _vc_sel_WIRE_2 : UInt<1> \n connect _vc_sel_WIRE_2, _vc_sel_T_12 \n connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 \n node _vc_sel_T_13 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0)) \n node _vc_sel_T_14 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0)) \n node _vc_sel_T_15 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0)) \n node _vc_sel_T_16 = or(_vc_sel_T_13, _vc_sel_T_14) \n node _vc_sel_T_17 = or(_vc_sel_T_16, _vc_sel_T_15) \n wire _vc_sel_WIRE_3 : UInt<1> \n connect _vc_sel_WIRE_3, _vc_sel_T_17 \n connect _vc_sel_WIRE[2], _vc_sel_WIRE_3 \n connect vc_sel.`0`, _vc_sel_WIRE \n wire _vc_sel_WIRE_4 : UInt<1>[3] \n node _vc_sel_T_18 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) \n node _vc_sel_T_19 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) \n node _vc_sel_T_20 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0)) \n node _vc_sel_T_21 = or(_vc_sel_T_18, _vc_sel_T_19) \n node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_20) \n wire _vc_sel_WIRE_5 : UInt<1> \n connect _vc_sel_WIRE_5, _vc_sel_T_22 \n connect _vc_sel_WIRE_4[0], _vc_sel_WIRE_5 \n node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0)) \n node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0)) \n node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0)) \n node _vc_sel_T_26 = or(_vc_sel_T_23, _vc_sel_T_24) \n node _vc_sel_T_27 = or(_vc_sel_T_26, _vc_sel_T_25) \n wire _vc_sel_WIRE_6 : UInt<1> \n connect _vc_sel_WIRE_6, _vc_sel_T_27 \n connect _vc_sel_WIRE_4[1], _vc_sel_WIRE_6 \n node _vc_sel_T_28 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0)) \n node _vc_sel_T_29 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0)) \n node _vc_sel_T_30 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0)) \n node _vc_sel_T_31 = or(_vc_sel_T_28, _vc_sel_T_29) \n node _vc_sel_T_32 = or(_vc_sel_T_31, _vc_sel_T_30) \n wire _vc_sel_WIRE_7 : UInt<1> \n connect _vc_sel_WIRE_7, _vc_sel_T_32 \n connect _vc_sel_WIRE_4[2], _vc_sel_WIRE_7 \n connect vc_sel.`1`, _vc_sel_WIRE_4 \n wire _vc_sel_WIRE_8 : UInt<1>[1] \n node _vc_sel_T_33 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0)) \n node _vc_sel_T_34 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0)) \n node _vc_sel_T_35 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0)) \n node _vc_sel_T_36 = or(_vc_sel_T_33, _vc_sel_T_34) \n node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_35) \n wire _vc_sel_WIRE_9 : UInt<1> \n connect _vc_sel_WIRE_9, _vc_sel_T_37 \n connect _vc_sel_WIRE_8[0], _vc_sel_WIRE_9 \n connect vc_sel.`2`, _vc_sel_WIRE_8 \n node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1]) \n node channel_oh_0 = or(_channel_oh_T, vc_sel.`0`[2]) \n node _channel_oh_T_1 = or(vc_sel.`1`[0], vc_sel.`1`[1]) \n node channel_oh_1 = or(_channel_oh_T_1, vc_sel.`1`[2]) \n node virt_channel_hi = cat(vc_sel.`0`[2], vc_sel.`0`[1]) \n node _virt_channel_T = cat(virt_channel_hi, vc_sel.`0`[0]) \n node virt_channel_hi_1 = bits(_virt_channel_T, 2, 2) \n node virt_channel_lo = bits(_virt_channel_T, 1, 0) \n node _virt_channel_T_1 = orr(virt_channel_hi_1) \n node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo) \n node _virt_channel_T_3 = bits(_virt_channel_T_2, 1, 1) \n node _virt_channel_T_4 = cat(_virt_channel_T_1, _virt_channel_T_3) \n node virt_channel_hi_2 = cat(vc_sel.`1`[2], vc_sel.`1`[1]) \n node _virt_channel_T_5 = cat(virt_channel_hi_2, vc_sel.`1`[0]) \n node virt_channel_hi_3 = bits(_virt_channel_T_5, 2, 2) \n node virt_channel_lo_1 = bits(_virt_channel_T_5, 1, 0) \n node _virt_channel_T_6 = orr(virt_channel_hi_3) \n node _virt_channel_T_7 = or(virt_channel_hi_3, virt_channel_lo_1) \n node _virt_channel_T_8 = bits(_virt_channel_T_7, 1, 1) \n node _virt_channel_T_9 = cat(_virt_channel_T_6, _virt_channel_T_8) \n node _virt_channel_T_10 = mux(channel_oh_0, _virt_channel_T_4, UInt<1>(0h0)) \n node _virt_channel_T_11 = mux(channel_oh_1, _virt_channel_T_9, UInt<1>(0h0)) \n node _virt_channel_T_12 = mux(vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0)) \n node _virt_channel_T_13 = or(_virt_channel_T_10, _virt_channel_T_11) \n node _virt_channel_T_14 = or(_virt_channel_T_13, _virt_channel_T_12) \n wire virt_channel : UInt<2> \n connect virt_channel, _virt_channel_T_14 \n node _T_39 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) \n when _T_39 : \n connect salloc_outs[0].out_vid, virt_channel \n node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) \n node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) \n node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) \n node _salloc_outs_0_flit_payload_T_3 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) \n node _salloc_outs_0_flit_payload_T_4 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) \n node _salloc_outs_0_flit_payload_T_5 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0)) \n node _salloc_outs_0_flit_payload_T_6 = or(_salloc_outs_0_flit_payload_T_3, _salloc_outs_0_flit_payload_T_4) \n node _salloc_outs_0_flit_payload_T_7 = or(_salloc_outs_0_flit_payload_T_6, _salloc_outs_0_flit_payload_T_5) \n wire _salloc_outs_0_flit_payload_WIRE : UInt<145> \n connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_7 \n connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE \n node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) \n node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) \n node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) \n node _salloc_outs_0_flit_head_T_3 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) \n node _salloc_outs_0_flit_head_T_4 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) \n node _salloc_outs_0_flit_head_T_5 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0)) \n node _salloc_outs_0_flit_head_T_6 = or(_salloc_outs_0_flit_head_T_3, _salloc_outs_0_flit_head_T_4) \n node _salloc_outs_0_flit_head_T_7 = or(_salloc_outs_0_flit_head_T_6, _salloc_outs_0_flit_head_T_5) \n wire _salloc_outs_0_flit_head_WIRE : UInt<1> \n connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_7 \n connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE \n node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) \n node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) \n node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) \n node _salloc_outs_0_flit_tail_T_3 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) \n node _salloc_outs_0_flit_tail_T_4 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) \n node _salloc_outs_0_flit_tail_T_5 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) \n node _salloc_outs_0_flit_tail_T_6 = or(_salloc_outs_0_flit_tail_T_3, _salloc_outs_0_flit_tail_T_4) \n node _salloc_outs_0_flit_tail_T_7 = or(_salloc_outs_0_flit_tail_T_6, _salloc_outs_0_flit_tail_T_5) \n wire _salloc_outs_0_flit_tail_WIRE : UInt<1> \n connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_7 \n connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE \n node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) \n node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) \n node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) \n wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>} \n node _salloc_outs_0_flit_flow_T_3 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_4 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_5 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_6 = or(_salloc_outs_0_flit_flow_T_3, _salloc_outs_0_flit_flow_T_4) \n node _salloc_outs_0_flit_flow_T_7 = or(_salloc_outs_0_flit_flow_T_6, _salloc_outs_0_flit_flow_T_5) \n wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2> \n connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_7 \n connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 \n node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_11 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9) \n node _salloc_outs_0_flit_flow_T_12 = or(_salloc_outs_0_flit_flow_T_11, _salloc_outs_0_flit_flow_T_10) \n wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4> \n connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_12 \n connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 \n node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_13, _salloc_outs_0_flit_flow_T_14) \n node _salloc_outs_0_flit_flow_T_17 = or(_salloc_outs_0_flit_flow_T_16, _salloc_outs_0_flit_flow_T_15) \n wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<3> \n connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_17 \n connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 \n node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_19 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_20 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_18, _salloc_outs_0_flit_flow_T_19) \n node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_20) \n wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4> \n connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_22 \n connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 \n node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0)) \n node _salloc_outs_0_flit_flow_T_26 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24) \n node _salloc_outs_0_flit_flow_T_27 = or(_salloc_outs_0_flit_flow_T_26, _salloc_outs_0_flit_flow_T_25) \n wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<2> \n connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_27 \n connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 \n connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE \n else :\n\n invalidate salloc_outs[0].out_vid \n invalidate salloc_outs[0].flit.virt_channel_id \n invalidate salloc_outs[0].flit.flow.egress_node_id \n invalidate salloc_outs[0].flit.flow.egress_node \n invalidate salloc_outs[0].flit.flow.ingress_node_id \n invalidate salloc_outs[0].flit.flow.ingress_node \n invalidate salloc_outs[0].flit.flow.vnet_id \n invalidate salloc_outs[0].flit.payload \n invalidate salloc_outs[0].flit.tail \n invalidate salloc_outs[0].flit.head \n invalidate salloc_outs[0].flit.virt_channel_id \n connect io.out[0].valid, salloc_outs[0].valid \n connect io.out[0].bits.flit, salloc_outs[0].flit \n connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid \n invalidate states[0].fifo_deps \n invalidate states[0].flow.egress_node_id \n invalidate states[0].flow.egress_node \n invalidate states[0].flow.ingress_node_id \n invalidate states[0].flow.ingress_node \n invalidate states[0].flow.vnet_id \n invalidate states[0].vc_sel.`0`[0] \n invalidate states[0].vc_sel.`0`[1] \n invalidate states[0].vc_sel.`0`[2] \n invalidate states[0].vc_sel.`1`[0] \n invalidate states[0].vc_sel.`1`[1] \n invalidate states[0].vc_sel.`1`[2] \n invalidate states[0].vc_sel.`2`[0] \n invalidate states[0].g \n connect states[1].vc_sel.`0`[0], UInt<1>(0h0) \n connect states[1].vc_sel.`0`[2], UInt<1>(0h0) \n connect states[1].vc_sel.`1`[0], UInt<1>(0h0) \n connect states[1].vc_sel.`1`[2], UInt<1>(0h0) \n connect states[2].vc_sel.`0`[0], UInt<1>(0h0) \n connect states[2].vc_sel.`0`[1], UInt<1>(0h0) \n connect states[2].vc_sel.`1`[0], UInt<1>(0h0) \n connect states[2].vc_sel.`1`[1], UInt<1>(0h0) \n node _T_40 = asUInt(reset) \n when _T_40 : \n connect states[0].g, UInt<3>(0h0) \n connect states[1].g, UInt<3>(0h0) \n connect states[2].g, UInt<3>(0h0)"},"response":{"kind":"string","value":"module InputUnit_44(\t// @[InputUnit.scala:158:7]\n input clock,\t// @[InputUnit.scala:158:7]\n input reset,\t// @[InputUnit.scala:158:7]\n output [1:0] io_router_req_bits_src_virt_id,\t// @[InputUnit.scala:170:14]\n output [1:0] io_router_req_bits_flow_vnet_id,\t// @[InputUnit.scala:170:14]\n output [3:0] io_router_req_bits_flow_ingress_node,\t// @[InputUnit.scala:170:14]\n output [2:0] io_router_req_bits_flow_ingress_node_id,\t// @[InputUnit.scala:170:14]\n output [3:0] io_router_req_bits_flow_egress_node,\t// @[InputUnit.scala:170:14]\n output [1:0] io_router_req_bits_flow_egress_node_id,\t// @[InputUnit.scala:170:14]\n input io_router_resp_vc_sel_1_0,\t// @[InputUnit.scala:170:14]\n input io_router_resp_vc_sel_1_1,\t// @[InputUnit.scala:170:14]\n input io_router_resp_vc_sel_1_2,\t// @[InputUnit.scala:170:14]\n input io_router_resp_vc_sel_0_0,\t// @[InputUnit.scala:170:14]\n input io_router_resp_vc_sel_0_1,\t// @[InputUnit.scala:170:14]\n input io_router_resp_vc_sel_0_2,\t// @[InputUnit.scala:170:14]\n input io_vcalloc_req_ready,\t// @[InputUnit.scala:170:14]\n output io_vcalloc_req_valid,\t// @[InputUnit.scala:170:14]\n output io_vcalloc_req_bits_vc_sel_2_0,\t// @[InputUnit.scala:170:14]\n output io_vcalloc_req_bits_vc_sel_1_0,\t// @[InputUnit.scala:170:14]\n output io_vcalloc_req_bits_vc_sel_1_1,\t// @[InputUnit.scala:170:14]\n output io_vcalloc_req_bits_vc_sel_1_2,\t// @[InputUnit.scala:170:14]\n output io_vcalloc_req_bits_vc_sel_0_0,\t// @[InputUnit.scala:170:14]\n output io_vcalloc_req_bits_vc_sel_0_1,\t// @[InputUnit.scala:170:14]\n output io_vcalloc_req_bits_vc_sel_0_2,\t// @[InputUnit.scala:170:14]\n input io_vcalloc_resp_vc_sel_2_0,\t// @[InputUnit.scala:170:14]\n input io_vcalloc_resp_vc_sel_1_1,\t// @[InputUnit.scala:170:14]\n input io_vcalloc_resp_vc_sel_1_2,\t// @[InputUnit.scala:170:14]\n input io_vcalloc_resp_vc_sel_0_1,\t// @[InputUnit.scala:170:14]\n input io_vcalloc_resp_vc_sel_0_2,\t// @[InputUnit.scala:170:14]\n input io_out_credit_available_2_0,\t// @[InputUnit.scala:170:14]\n input io_out_credit_available_1_1,\t// @[InputUnit.scala:170:14]\n input io_out_credit_available_1_2,\t// @[InputUnit.scala:170:14]\n input io_out_credit_available_0_1,\t// @[InputUnit.scala:170:14]\n input io_out_credit_available_0_2,\t// @[InputUnit.scala:170:14]\n input io_salloc_req_0_ready,\t// @[InputUnit.scala:170:14]\n output io_salloc_req_0_valid,\t// @[InputUnit.scala:170:14]\n output io_salloc_req_0_bits_vc_sel_2_0,\t// @[InputUnit.scala:170:14]\n output io_salloc_req_0_bits_vc_sel_1_0,\t// @[InputUnit.scala:170:14]\n output io_salloc_req_0_bits_vc_sel_1_1,\t// @[InputUnit.scala:170:14]\n output io_salloc_req_0_bits_vc_sel_1_2,\t// @[InputUnit.scala:170:14]\n output io_salloc_req_0_bits_vc_sel_0_1,\t// @[InputUnit.scala:170:14]\n output io_salloc_req_0_bits_vc_sel_0_2,\t// @[InputUnit.scala:170:14]\n output io_salloc_req_0_bits_tail,\t// @[InputUnit.scala:170:14]\n output io_out_0_valid,\t// @[InputUnit.scala:170:14]\n output io_out_0_bits_flit_head,\t// @[InputUnit.scala:170:14]\n output io_out_0_bits_flit_tail,\t// @[InputUnit.scala:170:14]\n output [144:0] io_out_0_bits_flit_payload,\t// @[InputUnit.scala:170:14]\n output [1:0] io_out_0_bits_flit_flow_vnet_id,\t// @[InputUnit.scala:170:14]\n output [3:0] io_out_0_bits_flit_flow_ingress_node,\t// @[InputUnit.scala:170:14]\n output [2:0] io_out_0_bits_flit_flow_ingress_node_id,\t// @[InputUnit.scala:170:14]\n output [3:0] io_out_0_bits_flit_flow_egress_node,\t// @[InputUnit.scala:170:14]\n output [1:0] io_out_0_bits_flit_flow_egress_node_id,\t// @[InputUnit.scala:170:14]\n output [1:0] io_out_0_bits_out_virt_channel,\t// @[InputUnit.scala:170:14]\n output [1:0] io_debug_va_stall,\t// @[InputUnit.scala:170:14]\n output [1:0] io_debug_sa_stall,\t// @[InputUnit.scala:170:14]\n input io_in_flit_0_valid,\t// @[InputUnit.scala:170:14]\n input io_in_flit_0_bits_head,\t// @[InputUnit.scala:170:14]\n input io_in_flit_0_bits_tail,\t// @[InputUnit.scala:170:14]\n input [144:0] io_in_flit_0_bits_payload,\t// @[InputUnit.scala:170:14]\n input [1:0] io_in_flit_0_bits_flow_vnet_id,\t// @[InputUnit.scala:170:14]\n input [3:0] io_in_flit_0_bits_flow_ingress_node,\t// @[InputUnit.scala:170:14]\n input [2:0] io_in_flit_0_bits_flow_ingress_node_id,\t// @[InputUnit.scala:170:14]\n input [3:0] io_in_flit_0_bits_flow_egress_node,\t// @[InputUnit.scala:170:14]\n input [1:0] io_in_flit_0_bits_flow_egress_node_id,\t// @[InputUnit.scala:170:14]\n input [1:0] io_in_flit_0_bits_virt_channel_id,\t// @[InputUnit.scala:170:14]\n output [2:0] io_in_credit_return,\t// @[InputUnit.scala:170:14]\n output [2:0] io_in_vc_free\t// @[InputUnit.scala:170:14]\n);\n\n wire _GEN;\t// @[MixedVec.scala:116:9]\n wire vcalloc_reqs_2_vc_sel_1_2;\t// @[MixedVec.scala:116:9]\n wire vcalloc_reqs_2_vc_sel_0_2;\t// @[MixedVec.scala:116:9]\n wire vcalloc_vals_2;\t// @[InputUnit.scala:266:25, :272:46, :273:29]\n wire _GEN_0;\t// @[MixedVec.scala:116:9]\n wire vcalloc_reqs_1_vc_sel_1_1;\t// @[MixedVec.scala:116:9]\n wire vcalloc_reqs_1_vc_sel_0_1;\t// @[MixedVec.scala:116:9]\n wire vcalloc_vals_1;\t// @[InputUnit.scala:266:25, :272:46, :273:29]\n wire _salloc_arb_io_in_1_ready;\t// @[InputUnit.scala:296:26]\n wire _salloc_arb_io_in_2_ready;\t// @[InputUnit.scala:296:26]\n wire _salloc_arb_io_out_0_valid;\t// @[InputUnit.scala:296:26]\n wire [2:0] _salloc_arb_io_chosen_oh_0;\t// @[InputUnit.scala:296:26]\n wire _route_arbiter_io_in_1_ready;\t// @[InputUnit.scala:187:29]\n wire _route_arbiter_io_in_2_ready;\t// @[InputUnit.scala:187:29]\n wire _route_arbiter_io_out_valid;\t// @[InputUnit.scala:187:29]\n wire [1:0] _route_arbiter_io_out_bits_src_virt_id;\t// @[InputUnit.scala:187:29]\n wire _input_buffer_io_deq_0_bits_head;\t// @[InputUnit.scala:181:28]\n wire _input_buffer_io_deq_0_bits_tail;\t// @[InputUnit.scala:181:28]\n wire [144:0] _input_buffer_io_deq_0_bits_payload;\t// @[InputUnit.scala:181:28]\n wire _input_buffer_io_deq_1_valid;\t// @[InputUnit.scala:181:28]\n wire _input_buffer_io_deq_1_bits_head;\t// @[InputUnit.scala:181:28]\n wire _input_buffer_io_deq_1_bits_tail;\t// @[InputUnit.scala:181:28]\n wire [144:0] _input_buffer_io_deq_1_bits_payload;\t// @[InputUnit.scala:181:28]\n wire _input_buffer_io_deq_2_valid;\t// @[InputUnit.scala:181:28]\n wire _input_buffer_io_deq_2_bits_head;\t// @[InputUnit.scala:181:28]\n wire _input_buffer_io_deq_2_bits_tail;\t// @[InputUnit.scala:181:28]\n wire [144:0] _input_buffer_io_deq_2_bits_payload;\t// @[InputUnit.scala:181:28]\n reg [2:0] states_1_g;\t// @[InputUnit.scala:192:19]\n reg states_1_vc_sel_2_0;\t// @[InputUnit.scala:192:19]\n reg states_1_vc_sel_1_1;\t// @[InputUnit.scala:192:19]\n reg states_1_vc_sel_0_1;\t// @[InputUnit.scala:192:19]\n reg [1:0] states_1_flow_vnet_id;\t// @[InputUnit.scala:192:19]\n reg [3:0] states_1_flow_ingress_node;\t// @[InputUnit.scala:192:19]\n reg [2:0] states_1_flow_ingress_node_id;\t// @[InputUnit.scala:192:19]\n reg [3:0] states_1_flow_egress_node;\t// @[InputUnit.scala:192:19]\n reg [1:0] states_1_flow_egress_node_id;\t// @[InputUnit.scala:192:19]\n reg [2:0] states_2_g;\t// @[InputUnit.scala:192:19]\n reg states_2_vc_sel_2_0;\t// @[InputUnit.scala:192:19]\n reg states_2_vc_sel_1_2;\t// @[InputUnit.scala:192:19]\n reg states_2_vc_sel_0_2;\t// @[InputUnit.scala:192:19]\n reg [1:0] states_2_flow_vnet_id;\t// @[InputUnit.scala:192:19]\n reg [3:0] states_2_flow_ingress_node;\t// @[InputUnit.scala:192:19]\n reg [2:0] states_2_flow_ingress_node_id;\t// @[InputUnit.scala:192:19]\n reg [3:0] states_2_flow_egress_node;\t// @[InputUnit.scala:192:19]\n reg [1:0] states_2_flow_egress_node_id;\t// @[InputUnit.scala:192:19]\n wire _GEN_1 = io_in_flit_0_valid & io_in_flit_0_bits_head;\t// @[InputUnit.scala:205:30]\n wire route_arbiter_io_in_1_valid = states_1_g == 3'h1;\t// @[InputUnit.scala:192:19, :229:22]\n wire _GEN_2 = _route_arbiter_io_in_1_ready & route_arbiter_io_in_1_valid;\t// @[Decoupled.scala:51:35]\n wire route_arbiter_io_in_2_valid = states_2_g == 3'h1;\t// @[InputUnit.scala:192:19, :229:22]\n wire _GEN_3 = _route_arbiter_io_in_2_ready & route_arbiter_io_in_2_valid;\t// @[Decoupled.scala:51:35]"}}},{"rowIdx":34395,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_137 : \n input clock : Clock \n input reset : Reset \n output io : { flip d : UInt<1>, q : UInt<1>} \n\n\n node _output_T = asAsyncReset(reset) \n node _output_T_1 = bits(io.d, 0, 0) \n inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_233 \n connect output_chain.clock, clock\n\n connect output_chain.reset, _output_T\n\n connect output_chain.io.d, _output_T_1 \n wire output_0 : UInt<1> \n connect output_0, output_chain.io.q \n connect io.q, output_0"},"response":{"kind":"string","value":"module AsyncResetSynchronizerShiftReg_w1_d3_i0_137(\t// @[SynchronizerReg.scala:80:7]\n input clock,\t// @[SynchronizerReg.scala:80:7]\n input reset,\t// @[SynchronizerReg.scala:80:7]\n output io_q\t// @[ShiftReg.scala:36:14]\n);\n\n wire _output_T = reset;\t// @[SynchronizerReg.scala:86:21]\n wire io_d = 1'h1;\t// @[SynchronizerReg.scala:80:7, :87:41]\n wire _output_T_1 = 1'h1;\t// @[SynchronizerReg.scala:80:7, :87:41]\n wire output_0;\t// @[ShiftReg.scala:48:24]\n wire io_q_0;\t// @[SynchronizerReg.scala:80:7]\n assign io_q_0 = output_0;\t// @[SynchronizerReg.scala:80:7]\n AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_233 output_chain (\t// @[ShiftReg.scala:45:23]\n .clock (clock),\n .reset (_output_T),\t// @[SynchronizerReg.scala:86:21]\n .io_q (output_0)\n );\t// @[ShiftReg.scala:45:23]\n assign io_q = io_q_0;\t// @[SynchronizerReg.scala:80:7]\nendmodule"}}},{"rowIdx":34396,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module IntSyncSyncCrossingSink_n1x1_37 : \n output auto : { flip in : { sync : UInt<1>[1]}, out : UInt<1>[1]} \n\n\n wire childClock : Clock \n wire childReset : Reset \n node _childClock_T = asClock(UInt<1>(0h0)) \n connect childClock, _childClock_T \n invalidate childReset \n wire nodeIn : { sync : UInt<1>[1]} \n invalidate nodeIn.sync[0] \n wire nodeOut : UInt<1>[1] \n invalidate nodeOut[0] \n connect auto.out, nodeOut \n connect nodeIn, auto.in \n connect nodeOut, nodeIn.sync"},"response":{"kind":"string","value":"module IntSyncSyncCrossingSink_n1x1_37();\t// @[Crossing.scala:96:9]\n wire auto_in_sync_0 = 1'h0;\t// @[Crossing.scala:96:9]\n wire auto_out_0 = 1'h0;\t// @[Crossing.scala:96:9]\n wire childClock = 1'h0;\t// @[LazyModuleImp.scala:155:31]\n wire childReset = 1'h0;\t// @[LazyModuleImp.scala:158:31]\n wire _childClock_T = 1'h0;\t// @[LazyModuleImp.scala:160:25]\n wire nodeIn_sync_0 = 1'h0;\t// @[MixedNode.scala:551:17]\n wire nodeOut_0 = 1'h0;\t// @[MixedNode.scala:542:17]\nendmodule"}}},{"rowIdx":34397,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module ConstellationSystemBus : \n output auto : { flip coupler_from_rockettile_tl_master_clock_xing_in_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}, flip coupler_from_rockettile_tl_master_clock_xing_in_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}, flip coupler_from_rockettile_tl_master_clock_xing_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}, flip coupler_from_rockettile_tl_master_clock_xing_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}, coupler_to_bus_named_coh_widget_anon_out_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, coupler_to_bus_named_coh_widget_anon_out_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, coupler_to_bus_named_coh_widget_anon_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, coupler_to_bus_named_coh_widget_anon_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip coupler_from_bus_named_fbus_bus_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_bus_named_cbus_bus_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, fixedClockNode_anon_out_5 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_4 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_3 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_2 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_1 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_0 : { clock : Clock, reset : Reset}, flip sbus_clock_groups_in : { member : { sbus_1 : { clock : Clock, reset : Reset}, sbus_0 : { clock : Clock, reset : Reset}}}, sbus_clock_groups_out : { member : { coh_0 : { clock : Clock, reset : Reset}}}} \n output clock : Clock \n output reset : Reset \n\n\n wire childClock : Clock \n wire childReset : Reset \n node _childClock_T = asClock(UInt<1>(0h0)) \n connect childClock, _childClock_T \n invalidate childReset \n inst sbus_clock_groups of ClockGroupAggregator_sbus \n inst clockGroup of ClockGroup \n inst fixedClockNode of FixedClockBroadcast_7 \n inst broadcast of BundleBridgeNexus_NoOutput \n inst system_bus_noc of TLNoC \n connect system_bus_noc.clock, childClock\n\n connect system_bus_noc.reset, childReset\n\n inst fixer of TLFIFOFixer \n connect fixer.clock, childClock\n\n connect fixer.reset, childReset\n\n inst coupler_to_bus_named_cbus of TLInterconnectCoupler_sbus_to_bus_named_cbus \n connect coupler_to_bus_named_cbus.clock, childClock\n\n connect coupler_to_bus_named_cbus.reset, childReset\n\n inst coupler_from_bus_named_fbus of TLInterconnectCoupler_sbus_from_bus_named_fbus \n connect coupler_from_bus_named_fbus.clock, childClock\n\n connect coupler_from_bus_named_fbus.reset, childReset\n\n inst coupler_to_bus_named_coh of TLInterconnectCoupler_sbus_to_bus_named_coh \n connect coupler_to_bus_named_coh.clock, childClock\n\n connect coupler_to_bus_named_coh.reset, childReset\n\n inst coupler_from_rockettile of TLInterconnectCoupler_sbus_from_rockettile \n connect coupler_from_rockettile.clock, childClock\n\n connect coupler_from_rockettile.reset, childReset\n\n inst coupler_from_rockettile_1 of TLInterconnectCoupler_sbus_from_rockettile_1 \n connect coupler_from_rockettile_1.clock, childClock\n\n connect coupler_from_rockettile_1.reset, childReset\n\n inst coupler_from_rockettile_2 of TLInterconnectCoupler_sbus_from_rockettile_2 \n connect coupler_from_rockettile_2.clock, childClock\n\n connect coupler_from_rockettile_2.reset, childReset\n\n inst coupler_from_rockettile_3 of TLInterconnectCoupler_sbus_from_rockettile_3 \n connect coupler_from_rockettile_3.clock, childClock\n\n connect coupler_from_rockettile_3.reset, childReset\n\n wire clockSinkNodeIn : { clock : Clock, reset : Reset} \n invalidate clockSinkNodeIn.reset \n invalidate clockSinkNodeIn.clock \n connect clockGroup.auto.in, sbus_clock_groups.auto.out_0 \n connect fixedClockNode.auto.anon_in, clockGroup.auto.out \n connect clockSinkNodeIn, fixedClockNode.auto.anon_out_0 \n connect coupler_to_bus_named_cbus.auto.widget_anon_in, system_bus_noc.auto.out_0 \n connect coupler_to_bus_named_coh.auto.widget_anon_in_0, system_bus_noc.auto.out_1 \n connect coupler_to_bus_named_coh.auto.widget_anon_in_1, system_bus_noc.auto.out_2 \n connect coupler_to_bus_named_coh.auto.widget_anon_in_2, system_bus_noc.auto.out_3 \n connect coupler_to_bus_named_coh.auto.widget_anon_in_3, system_bus_noc.auto.out_4 \n connect system_bus_noc.auto.in_0, fixer.auto.anon_out_0 \n connect system_bus_noc.auto.in_1, fixer.auto.anon_out_1 \n connect system_bus_noc.auto.in_2, fixer.auto.anon_out_2 \n connect system_bus_noc.auto.in_3, fixer.auto.anon_out_3 \n connect system_bus_noc.auto.in_4, fixer.auto.anon_out_4 \n connect fixer.auto.anon_in_0, coupler_from_bus_named_fbus.auto.widget_anon_out \n connect fixer.auto.anon_in_1, coupler_from_rockettile.auto.tl_out \n connect fixer.auto.anon_in_2, coupler_from_rockettile_1.auto.tl_out \n connect fixer.auto.anon_in_3, coupler_from_rockettile_2.auto.tl_out \n connect fixer.auto.anon_in_4, coupler_from_rockettile_3.auto.tl_out \n connect auto.sbus_clock_groups_out, sbus_clock_groups.auto.out_1 \n connect sbus_clock_groups.auto.in, auto.sbus_clock_groups_in \n connect auto.fixedClockNode_anon_out_0, fixedClockNode.auto.anon_out_1 \n connect auto.fixedClockNode_anon_out_1, fixedClockNode.auto.anon_out_2 \n connect auto.fixedClockNode_anon_out_2, fixedClockNode.auto.anon_out_3 \n connect auto.fixedClockNode_anon_out_3, fixedClockNode.auto.anon_out_4 \n connect auto.fixedClockNode_anon_out_4, fixedClockNode.auto.anon_out_5 \n connect auto.fixedClockNode_anon_out_5, fixedClockNode.auto.anon_out_6 \n connect coupler_to_bus_named_cbus.auto.bus_xing_out.d, auto.coupler_to_bus_named_cbus_bus_xing_out.d \n connect auto.coupler_to_bus_named_cbus_bus_xing_out.a.bits, coupler_to_bus_named_cbus.auto.bus_xing_out.a.bits \n connect auto.coupler_to_bus_named_cbus_bus_xing_out.a.valid, coupler_to_bus_named_cbus.auto.bus_xing_out.a.valid \n connect coupler_to_bus_named_cbus.auto.bus_xing_out.a.ready, auto.coupler_to_bus_named_cbus_bus_xing_out.a.ready \n connect coupler_from_bus_named_fbus.auto.bus_xing_in, auto.coupler_from_bus_named_fbus_bus_xing_in \n connect auto.coupler_to_bus_named_coh_widget_anon_out_0.e.bits, coupler_to_bus_named_coh.auto.widget_anon_out_0.e.bits \n connect auto.coupler_to_bus_named_coh_widget_anon_out_0.e.valid, coupler_to_bus_named_coh.auto.widget_anon_out_0.e.valid \n connect coupler_to_bus_named_coh.auto.widget_anon_out_0.e.ready, auto.coupler_to_bus_named_coh_widget_anon_out_0.e.ready \n connect coupler_to_bus_named_coh.auto.widget_anon_out_0.d, auto.coupler_to_bus_named_coh_widget_anon_out_0.d \n connect auto.coupler_to_bus_named_coh_widget_anon_out_0.c.bits, coupler_to_bus_named_coh.auto.widget_anon_out_0.c.bits \n connect auto.coupler_to_bus_named_coh_widget_anon_out_0.c.valid, coupler_to_bus_named_coh.auto.widget_anon_out_0.c.valid \n connect coupler_to_bus_named_coh.auto.widget_anon_out_0.c.ready, auto.coupler_to_bus_named_coh_widget_anon_out_0.c.ready \n connect coupler_to_bus_named_coh.auto.widget_anon_out_0.b, auto.coupler_to_bus_named_coh_widget_anon_out_0.b \n connect auto.coupler_to_bus_named_coh_widget_anon_out_0.a.bits, coupler_to_bus_named_coh.auto.widget_anon_out_0.a.bits \n connect auto.coupler_to_bus_named_coh_widget_anon_out_0.a.valid, coupler_to_bus_named_coh.auto.widget_anon_out_0.a.valid \n connect coupler_to_bus_named_coh.auto.widget_anon_out_0.a.ready, auto.coupler_to_bus_named_coh_widget_anon_out_0.a.ready \n connect auto.coupler_to_bus_named_coh_widget_anon_out_1.e.bits, coupler_to_bus_named_coh.auto.widget_anon_out_1.e.bits \n connect auto.coupler_to_bus_named_coh_widget_anon_out_1.e.valid, coupler_to_bus_named_coh.auto.widget_anon_out_1.e.valid \n connect coupler_to_bus_named_coh.auto.widget_anon_out_1.e.ready, auto.coupler_to_bus_named_coh_widget_anon_out_1.e.ready \n connect coupler_to_bus_named_coh.auto.widget_anon_out_1.d, auto.coupler_to_bus_named_coh_widget_anon_out_1.d \n connect auto.coupler_to_bus_named_coh_widget_anon_out_1.c.bits, coupler_to_bus_named_coh.auto.widget_anon_out_1.c.bits \n connect auto.coupler_to_bus_named_coh_widget_anon_out_1.c.valid, coupler_to_bus_named_coh.auto.widget_anon_out_1.c.valid \n connect coupler_to_bus_named_coh.auto.widget_anon_out_1.c.ready, auto.coupler_to_bus_named_coh_widget_anon_out_1.c.ready \n connect coupler_to_bus_named_coh.auto.widget_anon_out_1.b, auto.coupler_to_bus_named_coh_widget_anon_out_1.b \n connect auto.coupler_to_bus_named_coh_widget_anon_out_1.a.bits, coupler_to_bus_named_coh.auto.widget_anon_out_1.a.bits \n connect auto.coupler_to_bus_named_coh_widget_anon_out_1.a.valid, coupler_to_bus_named_coh.auto.widget_anon_out_1.a.valid \n connect coupler_to_bus_named_coh.auto.widget_anon_out_1.a.ready, auto.coupler_to_bus_named_coh_widget_anon_out_1.a.ready \n connect auto.coupler_to_bus_named_coh_widget_anon_out_2.e.bits, coupler_to_bus_named_coh.auto.widget_anon_out_2.e.bits \n connect auto.coupler_to_bus_named_coh_widget_anon_out_2.e.valid, coupler_to_bus_named_coh.auto.widget_anon_out_2.e.valid \n connect coupler_to_bus_named_coh.auto.widget_anon_out_2.e.ready, auto.coupler_to_bus_named_coh_widget_anon_out_2.e.ready \n connect coupler_to_bus_named_coh.auto.widget_anon_out_2.d, auto.coupler_to_bus_named_coh_widget_anon_out_2.d \n connect auto.coupler_to_bus_named_coh_widget_anon_out_2.c.bits, coupler_to_bus_named_coh.auto.widget_anon_out_2.c.bits \n connect auto.coupler_to_bus_named_coh_widget_anon_out_2.c.valid, coupler_to_bus_named_coh.auto.widget_anon_out_2.c.valid \n connect coupler_to_bus_named_coh.auto.widget_anon_out_2.c.ready, auto.coupler_to_bus_named_coh_widget_anon_out_2.c.ready \n connect coupler_to_bus_named_coh.auto.widget_anon_out_2.b, auto.coupler_to_bus_named_coh_widget_anon_out_2.b \n connect auto.coupler_to_bus_named_coh_widget_anon_out_2.a.bits, coupler_to_bus_named_coh.auto.widget_anon_out_2.a.bits \n connect auto.coupler_to_bus_named_coh_widget_anon_out_2.a.valid, coupler_to_bus_named_coh.auto.widget_anon_out_2.a.valid \n connect coupler_to_bus_named_coh.auto.widget_anon_out_2.a.ready, auto.coupler_to_bus_named_coh_widget_anon_out_2.a.ready \n connect auto.coupler_to_bus_named_coh_widget_anon_out_3.e.bits, coupler_to_bus_named_coh.auto.widget_anon_out_3.e.bits \n connect auto.coupler_to_bus_named_coh_widget_anon_out_3.e.valid, coupler_to_bus_named_coh.auto.widget_anon_out_3.e.valid \n connect coupler_to_bus_named_coh.auto.widget_anon_out_3.e.ready, auto.coupler_to_bus_named_coh_widget_anon_out_3.e.ready \n connect coupler_to_bus_named_coh.auto.widget_anon_out_3.d, auto.coupler_to_bus_named_coh_widget_anon_out_3.d \n connect auto.coupler_to_bus_named_coh_widget_anon_out_3.c.bits, coupler_to_bus_named_coh.auto.widget_anon_out_3.c.bits \n connect auto.coupler_to_bus_named_coh_widget_anon_out_3.c.valid, coupler_to_bus_named_coh.auto.widget_anon_out_3.c.valid \n connect coupler_to_bus_named_coh.auto.widget_anon_out_3.c.ready, auto.coupler_to_bus_named_coh_widget_anon_out_3.c.ready \n connect coupler_to_bus_named_coh.auto.widget_anon_out_3.b, auto.coupler_to_bus_named_coh_widget_anon_out_3.b \n connect auto.coupler_to_bus_named_coh_widget_anon_out_3.a.bits, coupler_to_bus_named_coh.auto.widget_anon_out_3.a.bits \n connect auto.coupler_to_bus_named_coh_widget_anon_out_3.a.valid, coupler_to_bus_named_coh.auto.widget_anon_out_3.a.valid \n connect coupler_to_bus_named_coh.auto.widget_anon_out_3.a.ready, auto.coupler_to_bus_named_coh_widget_anon_out_3.a.ready \n connect coupler_from_rockettile.auto.tl_master_clock_xing_in, auto.coupler_from_rockettile_tl_master_clock_xing_in_0 \n connect coupler_from_rockettile_1.auto.tl_master_clock_xing_in, auto.coupler_from_rockettile_tl_master_clock_xing_in_1 \n connect coupler_from_rockettile_2.auto.tl_master_clock_xing_in, auto.coupler_from_rockettile_tl_master_clock_xing_in_2 \n connect coupler_from_rockettile_3.auto.tl_master_clock_xing_in, auto.coupler_from_rockettile_tl_master_clock_xing_in_3 \n connect childClock, clockSinkNodeIn.clock \n connect childReset, clockSinkNodeIn.reset \n connect clock, clockSinkNodeIn.clock \n connect reset, clockSinkNodeIn.reset"},"response":{"kind":"string","value":"module ConstellationSystemBus(\t// @[ClockDomain.scala:14:9]\n output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n input [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_address,\t// @[LazyModuleImp.scala:107:25]\n output [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_address,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_denied,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_valid,\t// @[LazyModuleImp.scala:107:25]\n input [4:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n input [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_address,\t// @[LazyModuleImp.scala:107:25]\n output [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_address,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_denied,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_valid,\t// @[LazyModuleImp.scala:107:25]\n input [4:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n input [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_address,\t// @[LazyModuleImp.scala:107:25]\n output [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_address,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_denied,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_valid,\t// @[LazyModuleImp.scala:107:25]\n input [4:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n input [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_address,\t// @[LazyModuleImp.scala:107:25]\n output [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_address,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_denied,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_valid,\t// @[LazyModuleImp.scala:107:25]\n input [4:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_to_bus_named_coh_widget_anon_out_3_a_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_to_bus_named_coh_widget_anon_out_3_a_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n output [7:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_to_bus_named_coh_widget_anon_out_3_b_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_to_bus_named_coh_widget_anon_out_3_b_valid,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_b_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_b_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_b_bits_address,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_to_bus_named_coh_widget_anon_out_3_c_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_to_bus_named_coh_widget_anon_out_3_c_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_address,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_to_bus_named_coh_widget_anon_out_3_d_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_to_bus_named_coh_widget_anon_out_3_d_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_denied,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_to_bus_named_coh_widget_anon_out_3_e_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_e_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_to_bus_named_coh_widget_anon_out_2_a_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_to_bus_named_coh_widget_anon_out_2_a_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n output [7:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_to_bus_named_coh_widget_anon_out_2_b_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_to_bus_named_coh_widget_anon_out_2_b_valid,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_b_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_b_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_b_bits_address,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_to_bus_named_coh_widget_anon_out_2_c_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_to_bus_named_coh_widget_anon_out_2_c_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_address,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_to_bus_named_coh_widget_anon_out_2_d_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_to_bus_named_coh_widget_anon_out_2_d_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_denied,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_to_bus_named_coh_widget_anon_out_2_e_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_e_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_to_bus_named_coh_widget_anon_out_1_a_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_to_bus_named_coh_widget_anon_out_1_a_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n output [7:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_to_bus_named_coh_widget_anon_out_1_b_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_to_bus_named_coh_widget_anon_out_1_b_valid,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_b_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_b_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_b_bits_address,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_to_bus_named_coh_widget_anon_out_1_c_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_to_bus_named_coh_widget_anon_out_1_c_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_address,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_to_bus_named_coh_widget_anon_out_1_d_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_to_bus_named_coh_widget_anon_out_1_d_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_denied,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_to_bus_named_coh_widget_anon_out_1_e_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_e_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_to_bus_named_coh_widget_anon_out_0_a_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_to_bus_named_coh_widget_anon_out_0_a_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n output [7:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_to_bus_named_coh_widget_anon_out_0_b_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_to_bus_named_coh_widget_anon_out_0_b_valid,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_b_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_b_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_b_bits_address,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_to_bus_named_coh_widget_anon_out_0_c_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_to_bus_named_coh_widget_anon_out_0_c_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_address,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_to_bus_named_coh_widget_anon_out_0_d_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_to_bus_named_coh_widget_anon_out_0_d_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_denied,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_to_bus_named_coh_widget_anon_out_0_e_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_e_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [4:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n input [7:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [5:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [28:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n output [7:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [5:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_fixedClockNode_anon_out_4_clock,\t// @[LazyModuleImp.scala:107:25]\n output auto_fixedClockNode_anon_out_4_reset,\t// @[LazyModuleImp.scala:107:25]\n output auto_fixedClockNode_anon_out_3_clock,\t// @[LazyModuleImp.scala:107:25]\n output auto_fixedClockNode_anon_out_3_reset,\t// @[LazyModuleImp.scala:107:25]\n output auto_fixedClockNode_anon_out_2_clock,\t// @[LazyModuleImp.scala:107:25]\n output auto_fixedClockNode_anon_out_2_reset,\t// @[LazyModuleImp.scala:107:25]\n output auto_fixedClockNode_anon_out_1_clock,\t// @[LazyModuleImp.scala:107:25]\n output auto_fixedClockNode_anon_out_1_reset,\t// @[LazyModuleImp.scala:107:25]\n input auto_sbus_clock_groups_in_member_sbus_1_clock,\t// @[LazyModuleImp.scala:107:25]\n input auto_sbus_clock_groups_in_member_sbus_1_reset,\t// @[LazyModuleImp.scala:107:25]\n input auto_sbus_clock_groups_in_member_sbus_0_clock,\t// @[LazyModuleImp.scala:107:25]\n input auto_sbus_clock_groups_in_member_sbus_0_reset,\t// @[LazyModuleImp.scala:107:25]\n output auto_sbus_clock_groups_out_member_coh_0_clock,\t// @[LazyModuleImp.scala:107:25]\n output auto_sbus_clock_groups_out_member_coh_0_reset\t// @[LazyModuleImp.scala:107:25]\n);\n\n wire _fixedClockNode_auto_anon_out_0_clock;\t// @[ClockGroup.scala:115:114]\n wire _fixedClockNode_auto_anon_out_0_reset;\t// @[ClockGroup.scala:115:114]\n FixedClockBroadcast_7 fixedClockNode (\t// @[ClockGroup.scala:115:114]\n .auto_anon_in_clock (auto_sbus_clock_groups_in_member_sbus_0_clock),\n .auto_anon_in_reset (auto_sbus_clock_groups_in_member_sbus_0_reset),\n .auto_anon_out_6_clock (/* unused */),\n .auto_anon_out_6_reset (/* unused */),\n .auto_anon_out_5_clock (auto_fixedClockNode_anon_out_4_clock),\n .auto_anon_out_5_reset (auto_fixedClockNode_anon_out_4_reset),\n .auto_anon_out_4_clock (auto_fixedClockNode_anon_out_3_clock),\n .auto_anon_out_4_reset (auto_fixedClockNode_anon_out_3_reset),\n .auto_anon_out_3_clock (auto_fixedClockNode_anon_out_2_clock),\n .auto_anon_out_3_reset (auto_fixedClockNode_anon_out_2_reset),\n .auto_anon_out_2_clock (auto_fixedClockNode_anon_out_1_clock),\n .auto_anon_out_2_reset (auto_fixedClockNode_anon_out_1_reset),\n .auto_anon_out_1_clock (/* unused */),\n .auto_anon_out_1_reset (/* unused */),\n .auto_anon_out_0_clock (_fixedClockNode_auto_anon_out_0_clock),\n .auto_anon_out_0_reset (_fixedClockNode_auto_anon_out_0_reset)\n );\t// @[ClockGroup.scala:115:114]\n TLNoC system_bus_noc (\t// @[Buses.scala:50:49]\n .clock (_fixedClockNode_auto_anon_out_0_clock),\t// @[ClockGroup.scala:115:114]\n .reset (_fixedClockNode_auto_anon_out_0_reset),\t// @[ClockGroup.scala:115:114]\n .auto_in_4_a_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_ready),\n .auto_in_4_a_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_valid),\n .auto_in_4_a_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_opcode),\n .auto_in_4_a_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_param),\n .auto_in_4_a_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_size),\n .auto_in_4_a_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_source),\n .auto_in_4_a_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_address),\n .auto_in_4_a_bits_mask (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_mask),\n .auto_in_4_a_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_data),\n .auto_in_4_a_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_corrupt),\n .auto_in_4_b_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_ready),\n .auto_in_4_b_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_valid),\n .auto_in_4_b_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_opcode),\n .auto_in_4_b_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_param),\n .auto_in_4_b_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_size),\n .auto_in_4_b_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_source),\n .auto_in_4_b_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_address),\n .auto_in_4_b_bits_mask (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_mask),\n .auto_in_4_b_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_data),\n .auto_in_4_b_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_corrupt),\n .auto_in_4_c_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_ready),\n .auto_in_4_c_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_valid),\n .auto_in_4_c_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_opcode),\n .auto_in_4_c_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_param),\n .auto_in_4_c_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_size),\n .auto_in_4_c_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_source),\n .auto_in_4_c_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_address),\n .auto_in_4_c_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_data),\n .auto_in_4_c_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_corrupt),\n .auto_in_4_d_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_ready),\n .auto_in_4_d_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_valid),\n .auto_in_4_d_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_opcode),\n .auto_in_4_d_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_param),\n .auto_in_4_d_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_size),\n .auto_in_4_d_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_source),\n .auto_in_4_d_bits_sink (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_sink),\n .auto_in_4_d_bits_denied (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_denied),\n .auto_in_4_d_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_data),\n .auto_in_4_d_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_corrupt),\n .auto_in_4_e_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_ready),\n .auto_in_4_e_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_valid),\n .auto_in_4_e_bits_sink (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_bits_sink),\n .auto_in_3_a_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_ready),\n .auto_in_3_a_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_valid),\n .auto_in_3_a_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_opcode),\n .auto_in_3_a_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_param),\n .auto_in_3_a_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_size),\n .auto_in_3_a_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_source),\n .auto_in_3_a_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_address),\n .auto_in_3_a_bits_mask (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_mask),\n .auto_in_3_a_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_data),\n .auto_in_3_a_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_corrupt),\n .auto_in_3_b_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_ready),\n .auto_in_3_b_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_valid),\n .auto_in_3_b_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_opcode),\n .auto_in_3_b_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_param),\n .auto_in_3_b_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_size),\n .auto_in_3_b_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_source),\n .auto_in_3_b_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_address),\n .auto_in_3_b_bits_mask (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_mask),\n .auto_in_3_b_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_data),\n .auto_in_3_b_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_corrupt),\n .auto_in_3_c_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_ready),\n .auto_in_3_c_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_valid),\n .auto_in_3_c_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_opcode),\n .auto_in_3_c_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_param),\n .auto_in_3_c_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_size),\n .auto_in_3_c_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_source),\n .auto_in_3_c_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_address),\n .auto_in_3_c_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_data),\n .auto_in_3_c_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_corrupt),\n .auto_in_3_d_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_ready),\n .auto_in_3_d_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_valid),\n .auto_in_3_d_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_opcode),\n .auto_in_3_d_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_param),\n .auto_in_3_d_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_size),\n .auto_in_3_d_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_source),\n .auto_in_3_d_bits_sink (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_sink),\n .auto_in_3_d_bits_denied (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_denied),\n .auto_in_3_d_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_data),\n .auto_in_3_d_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_corrupt),\n .auto_in_3_e_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_ready),\n .auto_in_3_e_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_valid),\n .auto_in_3_e_bits_sink (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_bits_sink),\n .auto_in_2_a_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_ready),\n .auto_in_2_a_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_valid),\n .auto_in_2_a_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_opcode),\n .auto_in_2_a_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_param),\n .auto_in_2_a_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_size),\n .auto_in_2_a_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_source),\n .auto_in_2_a_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_address),\n .auto_in_2_a_bits_mask (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_mask),\n .auto_in_2_a_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_data),\n .auto_in_2_a_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_corrupt),\n .auto_in_2_b_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_ready),\n .auto_in_2_b_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_valid),\n .auto_in_2_b_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_opcode),\n .auto_in_2_b_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_param),\n .auto_in_2_b_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_size),\n .auto_in_2_b_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_source),\n .auto_in_2_b_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_address),\n .auto_in_2_b_bits_mask (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_mask),\n .auto_in_2_b_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_data),\n .auto_in_2_b_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_corrupt),\n .auto_in_2_c_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_ready),\n .auto_in_2_c_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_valid),\n .auto_in_2_c_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_opcode),\n .auto_in_2_c_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_param),\n .auto_in_2_c_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_size),\n .auto_in_2_c_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_source),\n .auto_in_2_c_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_address),\n .auto_in_2_c_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_data),\n .auto_in_2_c_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_corrupt),\n .auto_in_2_d_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_ready),\n .auto_in_2_d_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_valid),\n .auto_in_2_d_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_opcode),\n .auto_in_2_d_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_param),\n .auto_in_2_d_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_size),\n .auto_in_2_d_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_source),\n .auto_in_2_d_bits_sink (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_sink),\n .auto_in_2_d_bits_denied (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_denied),\n .auto_in_2_d_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_data),\n .auto_in_2_d_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_corrupt),\n .auto_in_2_e_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_ready),\n .auto_in_2_e_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_valid),\n .auto_in_2_e_bits_sink (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_bits_sink),\n .auto_in_1_a_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_ready),\n .auto_in_1_a_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_valid),\n .auto_in_1_a_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_opcode),\n .auto_in_1_a_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_param),\n .auto_in_1_a_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_size),\n .auto_in_1_a_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_source),\n .auto_in_1_a_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_address),\n .auto_in_1_a_bits_mask (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_mask),\n .auto_in_1_a_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_data),\n .auto_in_1_a_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_corrupt),\n .auto_in_1_b_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_ready),\n .auto_in_1_b_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_valid),\n .auto_in_1_b_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_opcode),\n .auto_in_1_b_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_param),\n .auto_in_1_b_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_size),\n .auto_in_1_b_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_source),\n .auto_in_1_b_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_address),\n .auto_in_1_b_bits_mask (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_mask),\n .auto_in_1_b_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_data),\n .auto_in_1_b_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_corrupt),\n .auto_in_1_c_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_ready),\n .auto_in_1_c_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_valid),\n .auto_in_1_c_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_opcode),\n .auto_in_1_c_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_param),\n .auto_in_1_c_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_size),\n .auto_in_1_c_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_source),\n .auto_in_1_c_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_address),\n .auto_in_1_c_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_data),\n .auto_in_1_c_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_corrupt),\n .auto_in_1_d_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_ready),\n .auto_in_1_d_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_valid),\n .auto_in_1_d_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_opcode),\n .auto_in_1_d_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_param),\n .auto_in_1_d_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_size),\n .auto_in_1_d_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_source),\n .auto_in_1_d_bits_sink (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_sink),\n .auto_in_1_d_bits_denied (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_denied),\n .auto_in_1_d_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_data),\n .auto_in_1_d_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_corrupt),\n .auto_in_1_e_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_ready),\n .auto_in_1_e_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_valid),\n .auto_in_1_e_bits_sink (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_bits_sink),\n .auto_in_0_a_ready (auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready),\n .auto_in_0_a_valid (auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid),\n .auto_in_0_a_bits_opcode (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode),\n .auto_in_0_a_bits_param (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param),\n .auto_in_0_a_bits_size (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size),\n .auto_in_0_a_bits_source (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source),\n .auto_in_0_a_bits_address (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address),\n .auto_in_0_a_bits_mask (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask),\n .auto_in_0_a_bits_data (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data),\n .auto_in_0_a_bits_corrupt (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt),\n .auto_in_0_d_ready (auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready),\n .auto_in_0_d_valid (auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid),\n .auto_in_0_d_bits_opcode (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode),\n .auto_in_0_d_bits_param (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param),\n .auto_in_0_d_bits_size (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size),\n .auto_in_0_d_bits_source (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source),\n .auto_in_0_d_bits_sink (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink),\n .auto_in_0_d_bits_denied (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied),\n .auto_in_0_d_bits_data (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data),\n .auto_in_0_d_bits_corrupt (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt),\n .auto_out_4_a_ready (auto_coupler_to_bus_named_coh_widget_anon_out_3_a_ready),\n .auto_out_4_a_valid (auto_coupler_to_bus_named_coh_widget_anon_out_3_a_valid),\n .auto_out_4_a_bits_opcode (auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_opcode),\n .auto_out_4_a_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_param),\n .auto_out_4_a_bits_size (auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_size),\n .auto_out_4_a_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_source),\n .auto_out_4_a_bits_address (auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_address),\n .auto_out_4_a_bits_mask (auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_mask),\n .auto_out_4_a_bits_data (auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_data),\n .auto_out_4_a_bits_corrupt (auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_corrupt),\n .auto_out_4_b_ready (auto_coupler_to_bus_named_coh_widget_anon_out_3_b_ready),\n .auto_out_4_b_valid (auto_coupler_to_bus_named_coh_widget_anon_out_3_b_valid),\n .auto_out_4_b_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_3_b_bits_param),\n .auto_out_4_b_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_3_b_bits_source),\n .auto_out_4_b_bits_address (auto_coupler_to_bus_named_coh_widget_anon_out_3_b_bits_address),\n .auto_out_4_c_ready (auto_coupler_to_bus_named_coh_widget_anon_out_3_c_ready),\n .auto_out_4_c_valid (auto_coupler_to_bus_named_coh_widget_anon_out_3_c_valid),\n .auto_out_4_c_bits_opcode (auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_opcode),\n .auto_out_4_c_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_param),\n .auto_out_4_c_bits_size (auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_size),\n .auto_out_4_c_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_source),\n .auto_out_4_c_bits_address (auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_address),\n .auto_out_4_c_bits_data (auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_data),\n .auto_out_4_c_bits_corrupt (auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_corrupt),\n .auto_out_4_d_ready (auto_coupler_to_bus_named_coh_widget_anon_out_3_d_ready),\n .auto_out_4_d_valid (auto_coupler_to_bus_named_coh_widget_anon_out_3_d_valid),\n .auto_out_4_d_bits_opcode (auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_opcode),\n .auto_out_4_d_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_param),\n .auto_out_4_d_bits_size (auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_size),\n .auto_out_4_d_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_source),\n .auto_out_4_d_bits_sink (auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_sink),\n .auto_out_4_d_bits_denied (auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_denied),\n .auto_out_4_d_bits_data (auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_data),\n .auto_out_4_d_bits_corrupt (auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_corrupt),\n .auto_out_4_e_valid (auto_coupler_to_bus_named_coh_widget_anon_out_3_e_valid),\n .auto_out_4_e_bits_sink (auto_coupler_to_bus_named_coh_widget_anon_out_3_e_bits_sink),\n .auto_out_3_a_ready (auto_coupler_to_bus_named_coh_widget_anon_out_2_a_ready),\n .auto_out_3_a_valid (auto_coupler_to_bus_named_coh_widget_anon_out_2_a_valid),\n .auto_out_3_a_bits_opcode (auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_opcode),\n .auto_out_3_a_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_param),\n .auto_out_3_a_bits_size (auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_size),\n .auto_out_3_a_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_source),\n .auto_out_3_a_bits_address (auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_address),\n .auto_out_3_a_bits_mask (auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_mask),\n .auto_out_3_a_bits_data (auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_data),\n .auto_out_3_a_bits_corrupt (auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_corrupt),\n .auto_out_3_b_ready (auto_coupler_to_bus_named_coh_widget_anon_out_2_b_ready),\n .auto_out_3_b_valid (auto_coupler_to_bus_named_coh_widget_anon_out_2_b_valid),\n .auto_out_3_b_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_2_b_bits_param),\n .auto_out_3_b_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_2_b_bits_source),\n .auto_out_3_b_bits_address (auto_coupler_to_bus_named_coh_widget_anon_out_2_b_bits_address),\n .auto_out_3_c_ready (auto_coupler_to_bus_named_coh_widget_anon_out_2_c_ready),\n .auto_out_3_c_valid (auto_coupler_to_bus_named_coh_widget_anon_out_2_c_valid),\n .auto_out_3_c_bits_opcode (auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_opcode),\n .auto_out_3_c_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_param),\n .auto_out_3_c_bits_size (auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_size),\n .auto_out_3_c_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_source),\n .auto_out_3_c_bits_address (auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_address),\n .auto_out_3_c_bits_data (auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_data),\n .auto_out_3_c_bits_corrupt (auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_corrupt),\n .auto_out_3_d_ready (auto_coupler_to_bus_named_coh_widget_anon_out_2_d_ready),\n .auto_out_3_d_valid (auto_coupler_to_bus_named_coh_widget_anon_out_2_d_valid),\n .auto_out_3_d_bits_opcode (auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_opcode),\n .auto_out_3_d_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_param),\n .auto_out_3_d_bits_size (auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_size),\n .auto_out_3_d_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_source),\n .auto_out_3_d_bits_sink (auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_sink),\n .auto_out_3_d_bits_denied (auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_denied),\n .auto_out_3_d_bits_data (auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_data),\n .auto_out_3_d_bits_corrupt (auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_corrupt),\n .auto_out_3_e_valid (auto_coupler_to_bus_named_coh_widget_anon_out_2_e_valid),\n .auto_out_3_e_bits_sink (auto_coupler_to_bus_named_coh_widget_anon_out_2_e_bits_sink),\n .auto_out_2_a_ready (auto_coupler_to_bus_named_coh_widget_anon_out_1_a_ready),\n .auto_out_2_a_valid (auto_coupler_to_bus_named_coh_widget_anon_out_1_a_valid),\n .auto_out_2_a_bits_opcode (auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_opcode),\n .auto_out_2_a_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_param),\n .auto_out_2_a_bits_size (auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_size),\n .auto_out_2_a_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_source),\n .auto_out_2_a_bits_address (auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_address),\n .auto_out_2_a_bits_mask (auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_mask),\n .auto_out_2_a_bits_data (auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_data),\n .auto_out_2_a_bits_corrupt (auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_corrupt),\n .auto_out_2_b_ready (auto_coupler_to_bus_named_coh_widget_anon_out_1_b_ready),\n .auto_out_2_b_valid (auto_coupler_to_bus_named_coh_widget_anon_out_1_b_valid),\n .auto_out_2_b_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_1_b_bits_param),\n .auto_out_2_b_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_1_b_bits_source),\n .auto_out_2_b_bits_address (auto_coupler_to_bus_named_coh_widget_anon_out_1_b_bits_address),\n .auto_out_2_c_ready (auto_coupler_to_bus_named_coh_widget_anon_out_1_c_ready),\n .auto_out_2_c_valid (auto_coupler_to_bus_named_coh_widget_anon_out_1_c_valid),\n .auto_out_2_c_bits_opcode (auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_opcode),\n .auto_out_2_c_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_param),\n .auto_out_2_c_bits_size (auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_size),\n .auto_out_2_c_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_source),\n .auto_out_2_c_bits_address (auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_address),\n .auto_out_2_c_bits_data (auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_data),\n .auto_out_2_c_bits_corrupt (auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_corrupt),\n .auto_out_2_d_ready (auto_coupler_to_bus_named_coh_widget_anon_out_1_d_ready),\n .auto_out_2_d_valid (auto_coupler_to_bus_named_coh_widget_anon_out_1_d_valid),\n .auto_out_2_d_bits_opcode (auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_opcode),\n .auto_out_2_d_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_param),\n .auto_out_2_d_bits_size (auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_size),\n .auto_out_2_d_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_source),\n .auto_out_2_d_bits_sink (auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_sink),\n .auto_out_2_d_bits_denied (auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_denied),\n .auto_out_2_d_bits_data (auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_data),\n .auto_out_2_d_bits_corrupt (auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_corrupt),\n .auto_out_2_e_valid (auto_coupler_to_bus_named_coh_widget_anon_out_1_e_valid),\n .auto_out_2_e_bits_sink (auto_coupler_to_bus_named_coh_widget_anon_out_1_e_bits_sink),\n .auto_out_1_a_ready (auto_coupler_to_bus_named_coh_widget_anon_out_0_a_ready),\n .auto_out_1_a_valid (auto_coupler_to_bus_named_coh_widget_anon_out_0_a_valid),\n .auto_out_1_a_bits_opcode (auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_opcode),\n .auto_out_1_a_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_param),\n .auto_out_1_a_bits_size (auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_size),\n .auto_out_1_a_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_source),\n .auto_out_1_a_bits_address (auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_address),\n .auto_out_1_a_bits_mask (auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_mask),\n .auto_out_1_a_bits_data (auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_data),\n .auto_out_1_a_bits_corrupt (auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_corrupt),\n .auto_out_1_b_ready (auto_coupler_to_bus_named_coh_widget_anon_out_0_b_ready),\n .auto_out_1_b_valid (auto_coupler_to_bus_named_coh_widget_anon_out_0_b_valid),\n .auto_out_1_b_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_0_b_bits_param),\n .auto_out_1_b_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_0_b_bits_source),\n .auto_out_1_b_bits_address (auto_coupler_to_bus_named_coh_widget_anon_out_0_b_bits_address),\n .auto_out_1_c_ready (auto_coupler_to_bus_named_coh_widget_anon_out_0_c_ready),\n .auto_out_1_c_valid (auto_coupler_to_bus_named_coh_widget_anon_out_0_c_valid),\n .auto_out_1_c_bits_opcode (auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_opcode),\n .auto_out_1_c_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_param),\n .auto_out_1_c_bits_size (auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_size),\n .auto_out_1_c_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_source),\n .auto_out_1_c_bits_address (auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_address),\n .auto_out_1_c_bits_data (auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_data),\n .auto_out_1_c_bits_corrupt (auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_corrupt),\n .auto_out_1_d_ready (auto_coupler_to_bus_named_coh_widget_anon_out_0_d_ready),\n .auto_out_1_d_valid (auto_coupler_to_bus_named_coh_widget_anon_out_0_d_valid),\n .auto_out_1_d_bits_opcode (auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_opcode),\n .auto_out_1_d_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_param),\n .auto_out_1_d_bits_size (auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_size),\n .auto_out_1_d_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_source),\n .auto_out_1_d_bits_sink (auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_sink),\n .auto_out_1_d_bits_denied (auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_denied),\n .auto_out_1_d_bits_data (auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_data),\n .auto_out_1_d_bits_corrupt (auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_corrupt),\n .auto_out_1_e_valid (auto_coupler_to_bus_named_coh_widget_anon_out_0_e_valid),\n .auto_out_1_e_bits_sink (auto_coupler_to_bus_named_coh_widget_anon_out_0_e_bits_sink),\n .auto_out_0_a_ready (auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready),\n .auto_out_0_a_valid (auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid),\n .auto_out_0_a_bits_opcode (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode),\n .auto_out_0_a_bits_param (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param),\n .auto_out_0_a_bits_size (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size),\n .auto_out_0_a_bits_source (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source),\n .auto_out_0_a_bits_address (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address),\n .auto_out_0_a_bits_mask (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask),\n .auto_out_0_a_bits_data (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data),\n .auto_out_0_a_bits_corrupt (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt),\n .auto_out_0_d_ready (auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready),\n .auto_out_0_d_valid (auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid),\n .auto_out_0_d_bits_opcode (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode),\n .auto_out_0_d_bits_param (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param),\n .auto_out_0_d_bits_size (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size),\n .auto_out_0_d_bits_source (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source),\n .auto_out_0_d_bits_sink (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink),\n .auto_out_0_d_bits_denied (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied),\n .auto_out_0_d_bits_data (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data),\n .auto_out_0_d_bits_corrupt (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt)\n );\t// @[Buses.scala:50:49]\n assign auto_sbus_clock_groups_out_member_coh_0_clock = auto_sbus_clock_groups_in_member_sbus_1_clock;\t// @[ClockDomain.scala:14:9]\n assign auto_sbus_clock_groups_out_member_coh_0_reset = auto_sbus_clock_groups_in_member_sbus_1_reset;\t// @[ClockDomain.scala:14:9]\nendmodule"}}},{"rowIdx":34398,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_24 : \n input clock : Clock \n input reset : AsyncReset \n output io : { flip d : UInt<1>, q : UInt<1>} \n\n\n regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) \n regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) \n regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) \n node _sync_2_T = bits(io.d, 0, 0) \n connect sync_2, _sync_2_T \n connect sync_0, sync_1 \n connect sync_1, sync_2 \n connect io.q, sync_0"},"response":{"kind":"string","value":"module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_24(\t// @[SynchronizerReg.scala:68:19]\n input clock,\t// @[SynchronizerReg.scala:68:19]\n input reset,\t// @[SynchronizerReg.scala:68:19]\n input io_d,\t// @[ShiftReg.scala:36:14]\n output io_q\t// @[ShiftReg.scala:36:14]\n);\n\n wire io_d_0 = io_d;\t// @[SynchronizerReg.scala:68:19]\n wire _sync_2_T = io_d_0;\t// @[SynchronizerReg.scala:54:22, :68:19]\n wire io_q_0;\t// @[SynchronizerReg.scala:68:19]\n reg sync_0;\t// @[SynchronizerReg.scala:51:87]\n assign io_q_0 = sync_0;\t// @[SynchronizerReg.scala:51:87, :68:19]\n reg sync_1;\t// @[SynchronizerReg.scala:51:87]\n reg sync_2;\t// @[SynchronizerReg.scala:51:87]\n always @(posedge clock or posedge reset) begin\t// @[SynchronizerReg.scala:68:19]\n if (reset) begin\t// @[SynchronizerReg.scala:68:19]\n sync_0 <= 1'h0;\t// @[SynchronizerReg.scala:51:87]\n sync_1 <= 1'h0;\t// @[SynchronizerReg.scala:51:87]\n sync_2 <= 1'h0;\t// @[SynchronizerReg.scala:51:87]\n end\n else begin\t// @[SynchronizerReg.scala:68:19]\n sync_0 <= sync_1;\t// @[SynchronizerReg.scala:51:87]\n sync_1 <= sync_2;\t// @[SynchronizerReg.scala:51:87]\n sync_2 <= _sync_2_T;\t// @[SynchronizerReg.scala:51:87, :54:22]\n end\n always @(posedge, posedge)"}}},{"rowIdx":34399,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module INToRecFN_i1_e8_s24_18 : \n output io : { flip signedIn : UInt<1>, flip in : UInt<1>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} \n\n\n node _intAsRawFloat_sign_T = bits(io.in, 0, 0) \n node intAsRawFloat_sign = and(io.signedIn, _intAsRawFloat_sign_T) \n node _intAsRawFloat_absIn_T = sub(UInt<1>(0h0), io.in) \n node _intAsRawFloat_absIn_T_1 = tail(_intAsRawFloat_absIn_T, 1) \n node intAsRawFloat_absIn = mux(intAsRawFloat_sign, _intAsRawFloat_absIn_T_1, io.in) \n node _intAsRawFloat_extAbsIn_T = cat(UInt<2>(0h0), intAsRawFloat_absIn) \n node intAsRawFloat_extAbsIn = bits(_intAsRawFloat_extAbsIn_T, 1, 0) \n node _intAsRawFloat_adjustedNormDist_T = bits(intAsRawFloat_extAbsIn, 0, 0) \n node _intAsRawFloat_adjustedNormDist_T_1 = bits(intAsRawFloat_extAbsIn, 1, 1) \n node intAsRawFloat_adjustedNormDist = mux(_intAsRawFloat_adjustedNormDist_T_1, UInt<1>(0h0), UInt<1>(0h1)) \n node _intAsRawFloat_sig_T = dshl(intAsRawFloat_extAbsIn, intAsRawFloat_adjustedNormDist) \n node intAsRawFloat_sig = bits(_intAsRawFloat_sig_T, 1, 1) \n wire intAsRawFloat : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<4>, sig : UInt<2>} \n connect intAsRawFloat.isNaN, UInt<1>(0h0) \n connect intAsRawFloat.isInf, UInt<1>(0h0) \n node _intAsRawFloat_out_isZero_T = bits(intAsRawFloat_sig, 0, 0) \n node _intAsRawFloat_out_isZero_T_1 = eq(_intAsRawFloat_out_isZero_T, UInt<1>(0h0)) \n connect intAsRawFloat.isZero, _intAsRawFloat_out_isZero_T_1 \n connect intAsRawFloat.sign, intAsRawFloat_sign \n node _intAsRawFloat_out_sExp_T = bits(intAsRawFloat_adjustedNormDist, 0, 0) \n node _intAsRawFloat_out_sExp_T_1 = not(_intAsRawFloat_out_sExp_T) \n node _intAsRawFloat_out_sExp_T_2 = cat(UInt<2>(0h2), _intAsRawFloat_out_sExp_T_1) \n node _intAsRawFloat_out_sExp_T_3 = cvt(_intAsRawFloat_out_sExp_T_2) \n connect intAsRawFloat.sExp, _intAsRawFloat_out_sExp_T_3 \n connect intAsRawFloat.sig, intAsRawFloat_sig \n inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_18 \n connect roundAnyRawFNToRecFN.io.invalidExc, UInt<1>(0h0) \n connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) \n connect roundAnyRawFNToRecFN.io.in.sig, intAsRawFloat.sig \n connect roundAnyRawFNToRecFN.io.in.sExp, intAsRawFloat.sExp \n connect roundAnyRawFNToRecFN.io.in.sign, intAsRawFloat.sign \n connect roundAnyRawFNToRecFN.io.in.isZero, intAsRawFloat.isZero \n connect roundAnyRawFNToRecFN.io.in.isInf, intAsRawFloat.isInf \n connect roundAnyRawFNToRecFN.io.in.isNaN, intAsRawFloat.isNaN \n connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode \n connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess \n connect io.out, roundAnyRawFNToRecFN.io.out \n connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags"},"response":{"kind":"string","value":"module INToRecFN_i1_e8_s24_18();\t// @[INToRecFN.scala:43:7]\n wire [1:0] _intAsRawFloat_absIn_T = 2'h3;\t// @[rawFloatFromIN.scala:52:31]\n wire [2:0] _intAsRawFloat_extAbsIn_T = 3'h1;\t// @[rawFloatFromIN.scala:53:44]\n wire [2:0] _intAsRawFloat_sig_T = 3'h2;\t// @[rawFloatFromIN.scala:56:22]\n wire [2:0] _intAsRawFloat_out_sExp_T_2 = 3'h4;\t// @[rawFloatFromIN.scala:64:33]\n wire [3:0] intAsRawFloat_sExp = 4'h4;\t// @[rawFloatFromIN.scala:59:23, :64:72]\n wire [3:0] _intAsRawFloat_out_sExp_T_3 = 4'h4;\t// @[rawFloatFromIN.scala:59:23, :64:72]\n wire [1:0] intAsRawFloat_extAbsIn = 2'h1;\t// @[rawFloatFromIN.scala:53:53, :59:23, :65:20]\n wire [1:0] intAsRawFloat_sig = 2'h1;\t// @[rawFloatFromIN.scala:53:53, :59:23, :65:20]\n wire [4:0] io_exceptionFlags = 5'h0;\t// @[INToRecFN.scala:43:7, :46:16, :60:15]\n wire [32:0] io_out = 33'h80000000;\t// @[INToRecFN.scala:43:7, :46:16, :60:15]\n wire [2:0] io_roundingMode = 3'h0;\t// @[INToRecFN.scala:43:7, :46:16, :60:15]\n wire io_in = 1'h1;\t// @[Mux.scala:50:70]\n wire io_detectTininess = 1'h1;\t// @[Mux.scala:50:70]\n wire _intAsRawFloat_sign_T = 1'h1;\t// @[Mux.scala:50:70]\n wire _intAsRawFloat_absIn_T_1 = 1'h1;\t// @[Mux.scala:50:70]\n wire intAsRawFloat_absIn = 1'h1;\t// @[Mux.scala:50:70]\n wire _intAsRawFloat_adjustedNormDist_T = 1'h1;\t// @[Mux.scala:50:70]\n wire intAsRawFloat_adjustedNormDist = 1'h1;\t// @[Mux.scala:50:70]\n wire intAsRawFloat_sig_0 = 1'h1;\t// @[Mux.scala:50:70]\n wire _intAsRawFloat_out_isZero_T = 1'h1;\t// @[Mux.scala:50:70]\n wire _intAsRawFloat_out_sExp_T = 1'h1;\t// @[Mux.scala:50:70]\n wire io_signedIn = 1'h0;\t// @[INToRecFN.scala:43:7]\n wire intAsRawFloat_sign = 1'h0;\t// @[rawFloatFromIN.scala:51:29]\n wire _intAsRawFloat_adjustedNormDist_T_1 = 1'h0;\t// @[primitives.scala:91:52]\n wire intAsRawFloat_isNaN = 1'h0;\t// @[rawFloatFromIN.scala:59:23]\n wire intAsRawFloat_isInf = 1'h0;\t// @[rawFloatFromIN.scala:59:23]\n wire intAsRawFloat_isZero = 1'h0;\t// @[rawFloatFromIN.scala:59:23]\n wire intAsRawFloat_sign_0 = 1'h0;\t// @[rawFloatFromIN.scala:59:23]\n wire _intAsRawFloat_out_isZero_T_1 = 1'h0;\t// @[rawFloatFromIN.scala:62:23]\n wire _intAsRawFloat_out_sExp_T_1 = 1'h0;\t// @[rawFloatFromIN.scala:64:36]\n RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_18 roundAnyRawFNToRecFN ();\t// @[INToRecFN.scala:60:15]\nendmodule"}}}],"truncated":false,"partial":false},"paginationData":{"pageIndex":343,"numItemsPerPage":100,"numTotalItems":35529,"offset":34300,"length":100}},"jwt":"eyJhbGciOiJFZERTQSJ9.eyJyZWFkIjp0cnVlLCJwZXJtaXNzaW9ucyI6eyJyZXBvLmNvbnRlbnQucmVhZCI6dHJ1ZX0sImlhdCI6MTc1MjQyNzkxOCwic3ViIjoiL2RhdGFzZXRzL3J0bC1sbG0vY2hpc2VsLXZlcmlsb2ctcGFpcnMiLCJleHAiOjE3NTI0MzE1MTgsImlzcyI6Imh0dHBzOi8vaHVnZ2luZ2ZhY2UuY28ifQ.kpoIMJxrqJarE1zJhrZGwJkmA6d9Ja7sg58C5fbXliMPlpLu7puag9pDV7joyrnNbooT5ITNs2KB5HGxSCLPDw","displayUrls":true},"discussionsStats":{"closed":0,"open":1,"total":1},"fullWidth":true,"hasGatedAccess":true,"hasFullAccess":true,"isEmbedded":false,"savedQueries":{"community":[],"user":[]}}">
prompt
stringlengths 162
4.26M
| response
stringlengths 109
5.16M
|
|---|---|
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_31 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _source_ok_T_35 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _source_ok_T_36 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _source_ok_T_41 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _source_ok_T_42 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _source_ok_T_44 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _source_ok_T_46 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _source_ok_T_47 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _source_ok_T_48 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _source_ok_T_49 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE : UInt<1>[30]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_25
connect _source_ok_WIRE[6], _source_ok_T_26
connect _source_ok_WIRE[7], _source_ok_T_27
connect _source_ok_WIRE[8], _source_ok_T_28
connect _source_ok_WIRE[9], _source_ok_T_29
connect _source_ok_WIRE[10], _source_ok_T_30
connect _source_ok_WIRE[11], _source_ok_T_31
connect _source_ok_WIRE[12], _source_ok_T_32
connect _source_ok_WIRE[13], _source_ok_T_33
connect _source_ok_WIRE[14], _source_ok_T_34
connect _source_ok_WIRE[15], _source_ok_T_35
connect _source_ok_WIRE[16], _source_ok_T_36
connect _source_ok_WIRE[17], _source_ok_T_37
connect _source_ok_WIRE[18], _source_ok_T_38
connect _source_ok_WIRE[19], _source_ok_T_39
connect _source_ok_WIRE[20], _source_ok_T_40
connect _source_ok_WIRE[21], _source_ok_T_41
connect _source_ok_WIRE[22], _source_ok_T_42
connect _source_ok_WIRE[23], _source_ok_T_43
connect _source_ok_WIRE[24], _source_ok_T_44
connect _source_ok_WIRE[25], _source_ok_T_45
connect _source_ok_WIRE[26], _source_ok_T_46
connect _source_ok_WIRE[27], _source_ok_T_47
connect _source_ok_WIRE[28], _source_ok_T_48
connect _source_ok_WIRE[29], _source_ok_T_49
node _source_ok_T_50 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[2])
node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[3])
node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[4])
node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE[5])
node _source_ok_T_55 = or(_source_ok_T_54, _source_ok_WIRE[6])
node _source_ok_T_56 = or(_source_ok_T_55, _source_ok_WIRE[7])
node _source_ok_T_57 = or(_source_ok_T_56, _source_ok_WIRE[8])
node _source_ok_T_58 = or(_source_ok_T_57, _source_ok_WIRE[9])
node _source_ok_T_59 = or(_source_ok_T_58, _source_ok_WIRE[10])
node _source_ok_T_60 = or(_source_ok_T_59, _source_ok_WIRE[11])
node _source_ok_T_61 = or(_source_ok_T_60, _source_ok_WIRE[12])
node _source_ok_T_62 = or(_source_ok_T_61, _source_ok_WIRE[13])
node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE[14])
node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE[15])
node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE[16])
node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE[17])
node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE[18])
node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE[19])
node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE[20])
node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE[21])
node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE[22])
node _source_ok_T_72 = or(_source_ok_T_71, _source_ok_WIRE[23])
node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE[24])
node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE[25])
node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE[26])
node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE[27])
node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE[28])
node source_ok = or(_source_ok_T_77, _source_ok_WIRE[29])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_67 = cvt(_T_66)
node _T_68 = and(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = asSInt(_T_68)
node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0)))
node _T_71 = or(_T_65, _T_70)
node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_73 = eq(_T_72, UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<1>(0h0)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = or(_T_73, _T_78)
node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_81 = eq(_T_80, UInt<1>(0h0))
node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_83 = cvt(_T_82)
node _T_84 = and(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = asSInt(_T_84)
node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = or(_T_81, _T_86)
node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_89 = eq(_T_88, UInt<1>(0h0))
node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<1>(0h0)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_89, _T_94)
node _T_96 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_99 = cvt(_T_98)
node _T_100 = and(_T_99, asSInt(UInt<1>(0h0)))
node _T_101 = asSInt(_T_100)
node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0)))
node _T_103 = or(_T_97, _T_102)
node _T_104 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_105 = eq(_T_104, UInt<1>(0h0))
node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_107 = cvt(_T_106)
node _T_108 = and(_T_107, asSInt(UInt<1>(0h0)))
node _T_109 = asSInt(_T_108)
node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = or(_T_105, _T_110)
node _T_112 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_113 = eq(_T_112, UInt<1>(0h0))
node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_115 = cvt(_T_114)
node _T_116 = and(_T_115, asSInt(UInt<1>(0h0)))
node _T_117 = asSInt(_T_116)
node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0)))
node _T_119 = or(_T_113, _T_118)
node _T_120 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_123 = cvt(_T_122)
node _T_124 = and(_T_123, asSInt(UInt<1>(0h0)))
node _T_125 = asSInt(_T_124)
node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0)))
node _T_127 = or(_T_121, _T_126)
node _T_128 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_129 = eq(_T_128, UInt<1>(0h0))
node _T_130 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_131 = cvt(_T_130)
node _T_132 = and(_T_131, asSInt(UInt<1>(0h0)))
node _T_133 = asSInt(_T_132)
node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0)))
node _T_135 = or(_T_129, _T_134)
node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_137 = eq(_T_136, UInt<1>(0h0))
node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_139 = cvt(_T_138)
node _T_140 = and(_T_139, asSInt(UInt<1>(0h0)))
node _T_141 = asSInt(_T_140)
node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0)))
node _T_143 = or(_T_137, _T_142)
node _T_144 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_145 = eq(_T_144, UInt<1>(0h0))
node _T_146 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_147 = cvt(_T_146)
node _T_148 = and(_T_147, asSInt(UInt<1>(0h0)))
node _T_149 = asSInt(_T_148)
node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0)))
node _T_151 = or(_T_145, _T_150)
node _T_152 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_155 = cvt(_T_154)
node _T_156 = and(_T_155, asSInt(UInt<1>(0h0)))
node _T_157 = asSInt(_T_156)
node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0)))
node _T_159 = or(_T_153, _T_158)
node _T_160 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_161 = eq(_T_160, UInt<1>(0h0))
node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_163 = cvt(_T_162)
node _T_164 = and(_T_163, asSInt(UInt<1>(0h0)))
node _T_165 = asSInt(_T_164)
node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0)))
node _T_167 = or(_T_161, _T_166)
node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_169 = eq(_T_168, UInt<1>(0h0))
node _T_170 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_171 = cvt(_T_170)
node _T_172 = and(_T_171, asSInt(UInt<1>(0h0)))
node _T_173 = asSInt(_T_172)
node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0)))
node _T_175 = or(_T_169, _T_174)
node _T_176 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_177 = eq(_T_176, UInt<1>(0h0))
node _T_178 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_179 = cvt(_T_178)
node _T_180 = and(_T_179, asSInt(UInt<1>(0h0)))
node _T_181 = asSInt(_T_180)
node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0)))
node _T_183 = or(_T_177, _T_182)
node _T_184 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_185 = eq(_T_184, UInt<1>(0h0))
node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_187 = cvt(_T_186)
node _T_188 = and(_T_187, asSInt(UInt<1>(0h0)))
node _T_189 = asSInt(_T_188)
node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0)))
node _T_191 = or(_T_185, _T_190)
node _T_192 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_193 = eq(_T_192, UInt<1>(0h0))
node _T_194 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_195 = cvt(_T_194)
node _T_196 = and(_T_195, asSInt(UInt<1>(0h0)))
node _T_197 = asSInt(_T_196)
node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0)))
node _T_199 = or(_T_193, _T_198)
node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_201 = eq(_T_200, UInt<1>(0h0))
node _T_202 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_203 = cvt(_T_202)
node _T_204 = and(_T_203, asSInt(UInt<1>(0h0)))
node _T_205 = asSInt(_T_204)
node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0)))
node _T_207 = or(_T_201, _T_206)
node _T_208 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_209 = eq(_T_208, UInt<1>(0h0))
node _T_210 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_211 = cvt(_T_210)
node _T_212 = and(_T_211, asSInt(UInt<1>(0h0)))
node _T_213 = asSInt(_T_212)
node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0)))
node _T_215 = or(_T_209, _T_214)
node _T_216 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_217 = eq(_T_216, UInt<1>(0h0))
node _T_218 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_219 = cvt(_T_218)
node _T_220 = and(_T_219, asSInt(UInt<1>(0h0)))
node _T_221 = asSInt(_T_220)
node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0)))
node _T_223 = or(_T_217, _T_222)
node _T_224 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_225 = eq(_T_224, UInt<1>(0h0))
node _T_226 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_227 = cvt(_T_226)
node _T_228 = and(_T_227, asSInt(UInt<1>(0h0)))
node _T_229 = asSInt(_T_228)
node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0)))
node _T_231 = or(_T_225, _T_230)
node _T_232 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_233 = eq(_T_232, UInt<1>(0h0))
node _T_234 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_235 = cvt(_T_234)
node _T_236 = and(_T_235, asSInt(UInt<1>(0h0)))
node _T_237 = asSInt(_T_236)
node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0)))
node _T_239 = or(_T_233, _T_238)
node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_243 = cvt(_T_242)
node _T_244 = and(_T_243, asSInt(UInt<1>(0h0)))
node _T_245 = asSInt(_T_244)
node _T_246 = eq(_T_245, asSInt(UInt<1>(0h0)))
node _T_247 = or(_T_241, _T_246)
node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_249 = eq(_T_248, UInt<1>(0h0))
node _T_250 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_251 = cvt(_T_250)
node _T_252 = and(_T_251, asSInt(UInt<1>(0h0)))
node _T_253 = asSInt(_T_252)
node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0)))
node _T_255 = or(_T_249, _T_254)
node _T_256 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_257 = eq(_T_256, UInt<1>(0h0))
node _T_258 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_259 = cvt(_T_258)
node _T_260 = and(_T_259, asSInt(UInt<1>(0h0)))
node _T_261 = asSInt(_T_260)
node _T_262 = eq(_T_261, asSInt(UInt<1>(0h0)))
node _T_263 = or(_T_257, _T_262)
node _T_264 = and(_T_11, _T_24)
node _T_265 = and(_T_264, _T_37)
node _T_266 = and(_T_265, _T_50)
node _T_267 = and(_T_266, _T_63)
node _T_268 = and(_T_267, _T_71)
node _T_269 = and(_T_268, _T_79)
node _T_270 = and(_T_269, _T_87)
node _T_271 = and(_T_270, _T_95)
node _T_272 = and(_T_271, _T_103)
node _T_273 = and(_T_272, _T_111)
node _T_274 = and(_T_273, _T_119)
node _T_275 = and(_T_274, _T_127)
node _T_276 = and(_T_275, _T_135)
node _T_277 = and(_T_276, _T_143)
node _T_278 = and(_T_277, _T_151)
node _T_279 = and(_T_278, _T_159)
node _T_280 = and(_T_279, _T_167)
node _T_281 = and(_T_280, _T_175)
node _T_282 = and(_T_281, _T_183)
node _T_283 = and(_T_282, _T_191)
node _T_284 = and(_T_283, _T_199)
node _T_285 = and(_T_284, _T_207)
node _T_286 = and(_T_285, _T_215)
node _T_287 = and(_T_286, _T_223)
node _T_288 = and(_T_287, _T_231)
node _T_289 = and(_T_288, _T_239)
node _T_290 = and(_T_289, _T_247)
node _T_291 = and(_T_290, _T_255)
node _T_292 = and(_T_291, _T_263)
node _T_293 = asUInt(reset)
node _T_294 = eq(_T_293, UInt<1>(0h0))
when _T_294 :
node _T_295 = eq(_T_292, UInt<1>(0h0))
when _T_295 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_292, UInt<1>(0h1), "") : assert_1
node _T_296 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_296 :
node _T_297 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_298 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_299 = and(_T_297, _T_298)
node _T_300 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_301 = shr(io.in.a.bits.source, 2)
node _T_302 = eq(_T_301, UInt<1>(0h0))
node _T_303 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_304 = and(_T_302, _T_303)
node _T_305 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_306 = and(_T_304, _T_305)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_307 = shr(io.in.a.bits.source, 2)
node _T_308 = eq(_T_307, UInt<1>(0h1))
node _T_309 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_310 = and(_T_308, _T_309)
node _T_311 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_312 = and(_T_310, _T_311)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_313 = shr(io.in.a.bits.source, 2)
node _T_314 = eq(_T_313, UInt<2>(0h2))
node _T_315 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_316 = and(_T_314, _T_315)
node _T_317 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_318 = and(_T_316, _T_317)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_319 = shr(io.in.a.bits.source, 2)
node _T_320 = eq(_T_319, UInt<2>(0h3))
node _T_321 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_322 = and(_T_320, _T_321)
node _T_323 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_324 = and(_T_322, _T_323)
node _T_325 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_326 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_329 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_330 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_331 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_332 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_333 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_334 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_335 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_336 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_337 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_338 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_339 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_340 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_341 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_342 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_343 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_344 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_345 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_346 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_347 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_348 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_349 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_350 = or(_T_300, _T_306)
node _T_351 = or(_T_350, _T_312)
node _T_352 = or(_T_351, _T_318)
node _T_353 = or(_T_352, _T_324)
node _T_354 = or(_T_353, _T_325)
node _T_355 = or(_T_354, _T_326)
node _T_356 = or(_T_355, _T_327)
node _T_357 = or(_T_356, _T_328)
node _T_358 = or(_T_357, _T_329)
node _T_359 = or(_T_358, _T_330)
node _T_360 = or(_T_359, _T_331)
node _T_361 = or(_T_360, _T_332)
node _T_362 = or(_T_361, _T_333)
node _T_363 = or(_T_362, _T_334)
node _T_364 = or(_T_363, _T_335)
node _T_365 = or(_T_364, _T_336)
node _T_366 = or(_T_365, _T_337)
node _T_367 = or(_T_366, _T_338)
node _T_368 = or(_T_367, _T_339)
node _T_369 = or(_T_368, _T_340)
node _T_370 = or(_T_369, _T_341)
node _T_371 = or(_T_370, _T_342)
node _T_372 = or(_T_371, _T_343)
node _T_373 = or(_T_372, _T_344)
node _T_374 = or(_T_373, _T_345)
node _T_375 = or(_T_374, _T_346)
node _T_376 = or(_T_375, _T_347)
node _T_377 = or(_T_376, _T_348)
node _T_378 = or(_T_377, _T_349)
node _T_379 = and(_T_299, _T_378)
node _T_380 = or(UInt<1>(0h0), _T_379)
node _T_381 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_382 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_383 = cvt(_T_382)
node _T_384 = and(_T_383, asSInt(UInt<27>(0h4000000)))
node _T_385 = asSInt(_T_384)
node _T_386 = eq(_T_385, asSInt(UInt<1>(0h0)))
node _T_387 = and(_T_381, _T_386)
node _T_388 = or(UInt<1>(0h0), _T_387)
node _T_389 = and(_T_380, _T_388)
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_389, UInt<1>(0h1), "") : assert_2
node _T_393 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_394 = shr(io.in.a.bits.source, 2)
node _T_395 = eq(_T_394, UInt<1>(0h0))
node _T_396 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_397 = and(_T_395, _T_396)
node _T_398 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_399 = and(_T_397, _T_398)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_400 = shr(io.in.a.bits.source, 2)
node _T_401 = eq(_T_400, UInt<1>(0h1))
node _T_402 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_403 = and(_T_401, _T_402)
node _T_404 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_405 = and(_T_403, _T_404)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_406 = shr(io.in.a.bits.source, 2)
node _T_407 = eq(_T_406, UInt<2>(0h2))
node _T_408 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_409 = and(_T_407, _T_408)
node _T_410 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_411 = and(_T_409, _T_410)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_412 = shr(io.in.a.bits.source, 2)
node _T_413 = eq(_T_412, UInt<2>(0h3))
node _T_414 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_415 = and(_T_413, _T_414)
node _T_416 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_417 = and(_T_415, _T_416)
node _T_418 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_419 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_420 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_421 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_422 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_423 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_424 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_425 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_426 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_427 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_428 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_429 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_430 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_431 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_432 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_433 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_434 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_435 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_436 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_437 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_438 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_439 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_440 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_441 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_442 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE : UInt<1>[30]
connect _WIRE[0], _T_393
connect _WIRE[1], _T_399
connect _WIRE[2], _T_405
connect _WIRE[3], _T_411
connect _WIRE[4], _T_417
connect _WIRE[5], _T_418
connect _WIRE[6], _T_419
connect _WIRE[7], _T_420
connect _WIRE[8], _T_421
connect _WIRE[9], _T_422
connect _WIRE[10], _T_423
connect _WIRE[11], _T_424
connect _WIRE[12], _T_425
connect _WIRE[13], _T_426
connect _WIRE[14], _T_427
connect _WIRE[15], _T_428
connect _WIRE[16], _T_429
connect _WIRE[17], _T_430
connect _WIRE[18], _T_431
connect _WIRE[19], _T_432
connect _WIRE[20], _T_433
connect _WIRE[21], _T_434
connect _WIRE[22], _T_435
connect _WIRE[23], _T_436
connect _WIRE[24], _T_437
connect _WIRE[25], _T_438
connect _WIRE[26], _T_439
connect _WIRE[27], _T_440
connect _WIRE[28], _T_441
connect _WIRE[29], _T_442
node _T_443 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_444 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_445 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_446 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_447 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_448 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_449 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_450 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_451 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_452 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_453 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_454 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_455 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_456 = mux(_WIRE[5], _T_443, UInt<1>(0h0))
node _T_457 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_458 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_459 = mux(_WIRE[8], _T_444, UInt<1>(0h0))
node _T_460 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_461 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_462 = mux(_WIRE[11], _T_445, UInt<1>(0h0))
node _T_463 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0))
node _T_464 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0))
node _T_465 = mux(_WIRE[14], _T_446, UInt<1>(0h0))
node _T_466 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0))
node _T_467 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_468 = mux(_WIRE[17], _T_447, UInt<1>(0h0))
node _T_469 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0))
node _T_470 = mux(_WIRE[19], UInt<1>(0h0), UInt<1>(0h0))
node _T_471 = mux(_WIRE[20], _T_448, UInt<1>(0h0))
node _T_472 = mux(_WIRE[21], UInt<1>(0h0), UInt<1>(0h0))
node _T_473 = mux(_WIRE[22], UInt<1>(0h0), UInt<1>(0h0))
node _T_474 = mux(_WIRE[23], _T_449, UInt<1>(0h0))
node _T_475 = mux(_WIRE[24], UInt<1>(0h0), UInt<1>(0h0))
node _T_476 = mux(_WIRE[25], UInt<1>(0h0), UInt<1>(0h0))
node _T_477 = mux(_WIRE[26], _T_450, UInt<1>(0h0))
node _T_478 = mux(_WIRE[27], UInt<1>(0h0), UInt<1>(0h0))
node _T_479 = mux(_WIRE[28], UInt<1>(0h0), UInt<1>(0h0))
node _T_480 = mux(_WIRE[29], UInt<1>(0h0), UInt<1>(0h0))
node _T_481 = or(_T_451, _T_452)
node _T_482 = or(_T_481, _T_453)
node _T_483 = or(_T_482, _T_454)
node _T_484 = or(_T_483, _T_455)
node _T_485 = or(_T_484, _T_456)
node _T_486 = or(_T_485, _T_457)
node _T_487 = or(_T_486, _T_458)
node _T_488 = or(_T_487, _T_459)
node _T_489 = or(_T_488, _T_460)
node _T_490 = or(_T_489, _T_461)
node _T_491 = or(_T_490, _T_462)
node _T_492 = or(_T_491, _T_463)
node _T_493 = or(_T_492, _T_464)
node _T_494 = or(_T_493, _T_465)
node _T_495 = or(_T_494, _T_466)
node _T_496 = or(_T_495, _T_467)
node _T_497 = or(_T_496, _T_468)
node _T_498 = or(_T_497, _T_469)
node _T_499 = or(_T_498, _T_470)
node _T_500 = or(_T_499, _T_471)
node _T_501 = or(_T_500, _T_472)
node _T_502 = or(_T_501, _T_473)
node _T_503 = or(_T_502, _T_474)
node _T_504 = or(_T_503, _T_475)
node _T_505 = or(_T_504, _T_476)
node _T_506 = or(_T_505, _T_477)
node _T_507 = or(_T_506, _T_478)
node _T_508 = or(_T_507, _T_479)
node _T_509 = or(_T_508, _T_480)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_509
node _T_510 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_511 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_512 = and(_T_510, _T_511)
node _T_513 = or(UInt<1>(0h0), _T_512)
node _T_514 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_515 = cvt(_T_514)
node _T_516 = and(_T_515, asSInt(UInt<27>(0h4000000)))
node _T_517 = asSInt(_T_516)
node _T_518 = eq(_T_517, asSInt(UInt<1>(0h0)))
node _T_519 = and(_T_513, _T_518)
node _T_520 = or(UInt<1>(0h0), _T_519)
node _T_521 = and(_WIRE_1, _T_520)
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_521, UInt<1>(0h1), "") : assert_3
node _T_525 = asUInt(reset)
node _T_526 = eq(_T_525, UInt<1>(0h0))
when _T_526 :
node _T_527 = eq(source_ok, UInt<1>(0h0))
when _T_527 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_528 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_529 = asUInt(reset)
node _T_530 = eq(_T_529, UInt<1>(0h0))
when _T_530 :
node _T_531 = eq(_T_528, UInt<1>(0h0))
when _T_531 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_528, UInt<1>(0h1), "") : assert_5
node _T_532 = asUInt(reset)
node _T_533 = eq(_T_532, UInt<1>(0h0))
when _T_533 :
node _T_534 = eq(is_aligned, UInt<1>(0h0))
when _T_534 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_535 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_536 = asUInt(reset)
node _T_537 = eq(_T_536, UInt<1>(0h0))
when _T_537 :
node _T_538 = eq(_T_535, UInt<1>(0h0))
when _T_538 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_535, UInt<1>(0h1), "") : assert_7
node _T_539 = not(io.in.a.bits.mask)
node _T_540 = eq(_T_539, UInt<1>(0h0))
node _T_541 = asUInt(reset)
node _T_542 = eq(_T_541, UInt<1>(0h0))
when _T_542 :
node _T_543 = eq(_T_540, UInt<1>(0h0))
when _T_543 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_540, UInt<1>(0h1), "") : assert_8
node _T_544 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_544, UInt<1>(0h1), "") : assert_9
node _T_548 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_548 :
node _T_549 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_550 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_551 = and(_T_549, _T_550)
node _T_552 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_553 = shr(io.in.a.bits.source, 2)
node _T_554 = eq(_T_553, UInt<1>(0h0))
node _T_555 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_556 = and(_T_554, _T_555)
node _T_557 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_558 = and(_T_556, _T_557)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_559 = shr(io.in.a.bits.source, 2)
node _T_560 = eq(_T_559, UInt<1>(0h1))
node _T_561 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_562 = and(_T_560, _T_561)
node _T_563 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_564 = and(_T_562, _T_563)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_565 = shr(io.in.a.bits.source, 2)
node _T_566 = eq(_T_565, UInt<2>(0h2))
node _T_567 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_568 = and(_T_566, _T_567)
node _T_569 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_570 = and(_T_568, _T_569)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_571 = shr(io.in.a.bits.source, 2)
node _T_572 = eq(_T_571, UInt<2>(0h3))
node _T_573 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_574 = and(_T_572, _T_573)
node _T_575 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_576 = and(_T_574, _T_575)
node _T_577 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_578 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_579 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_580 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_581 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_582 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_583 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_584 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_585 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_586 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_587 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_588 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_589 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_590 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_591 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_592 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_593 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_594 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_595 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_596 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_597 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_598 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_599 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_600 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_601 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_602 = or(_T_552, _T_558)
node _T_603 = or(_T_602, _T_564)
node _T_604 = or(_T_603, _T_570)
node _T_605 = or(_T_604, _T_576)
node _T_606 = or(_T_605, _T_577)
node _T_607 = or(_T_606, _T_578)
node _T_608 = or(_T_607, _T_579)
node _T_609 = or(_T_608, _T_580)
node _T_610 = or(_T_609, _T_581)
node _T_611 = or(_T_610, _T_582)
node _T_612 = or(_T_611, _T_583)
node _T_613 = or(_T_612, _T_584)
node _T_614 = or(_T_613, _T_585)
node _T_615 = or(_T_614, _T_586)
node _T_616 = or(_T_615, _T_587)
node _T_617 = or(_T_616, _T_588)
node _T_618 = or(_T_617, _T_589)
node _T_619 = or(_T_618, _T_590)
node _T_620 = or(_T_619, _T_591)
node _T_621 = or(_T_620, _T_592)
node _T_622 = or(_T_621, _T_593)
node _T_623 = or(_T_622, _T_594)
node _T_624 = or(_T_623, _T_595)
node _T_625 = or(_T_624, _T_596)
node _T_626 = or(_T_625, _T_597)
node _T_627 = or(_T_626, _T_598)
node _T_628 = or(_T_627, _T_599)
node _T_629 = or(_T_628, _T_600)
node _T_630 = or(_T_629, _T_601)
node _T_631 = and(_T_551, _T_630)
node _T_632 = or(UInt<1>(0h0), _T_631)
node _T_633 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_634 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_635 = cvt(_T_634)
node _T_636 = and(_T_635, asSInt(UInt<27>(0h4000000)))
node _T_637 = asSInt(_T_636)
node _T_638 = eq(_T_637, asSInt(UInt<1>(0h0)))
node _T_639 = and(_T_633, _T_638)
node _T_640 = or(UInt<1>(0h0), _T_639)
node _T_641 = and(_T_632, _T_640)
node _T_642 = asUInt(reset)
node _T_643 = eq(_T_642, UInt<1>(0h0))
when _T_643 :
node _T_644 = eq(_T_641, UInt<1>(0h0))
when _T_644 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_641, UInt<1>(0h1), "") : assert_10
node _T_645 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_646 = shr(io.in.a.bits.source, 2)
node _T_647 = eq(_T_646, UInt<1>(0h0))
node _T_648 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_649 = and(_T_647, _T_648)
node _T_650 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_651 = and(_T_649, _T_650)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_652 = shr(io.in.a.bits.source, 2)
node _T_653 = eq(_T_652, UInt<1>(0h1))
node _T_654 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_655 = and(_T_653, _T_654)
node _T_656 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_657 = and(_T_655, _T_656)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_658 = shr(io.in.a.bits.source, 2)
node _T_659 = eq(_T_658, UInt<2>(0h2))
node _T_660 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_661 = and(_T_659, _T_660)
node _T_662 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_663 = and(_T_661, _T_662)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_664 = shr(io.in.a.bits.source, 2)
node _T_665 = eq(_T_664, UInt<2>(0h3))
node _T_666 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_667 = and(_T_665, _T_666)
node _T_668 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_669 = and(_T_667, _T_668)
node _T_670 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_671 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_672 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_673 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_674 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_675 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_676 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_677 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_678 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_679 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_680 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_681 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_682 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_683 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_684 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_685 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_686 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_687 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_688 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_689 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_690 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_691 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_692 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_693 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_694 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE_2 : UInt<1>[30]
connect _WIRE_2[0], _T_645
connect _WIRE_2[1], _T_651
connect _WIRE_2[2], _T_657
connect _WIRE_2[3], _T_663
connect _WIRE_2[4], _T_669
connect _WIRE_2[5], _T_670
connect _WIRE_2[6], _T_671
connect _WIRE_2[7], _T_672
connect _WIRE_2[8], _T_673
connect _WIRE_2[9], _T_674
connect _WIRE_2[10], _T_675
connect _WIRE_2[11], _T_676
connect _WIRE_2[12], _T_677
connect _WIRE_2[13], _T_678
connect _WIRE_2[14], _T_679
connect _WIRE_2[15], _T_680
connect _WIRE_2[16], _T_681
connect _WIRE_2[17], _T_682
connect _WIRE_2[18], _T_683
connect _WIRE_2[19], _T_684
connect _WIRE_2[20], _T_685
connect _WIRE_2[21], _T_686
connect _WIRE_2[22], _T_687
connect _WIRE_2[23], _T_688
connect _WIRE_2[24], _T_689
connect _WIRE_2[25], _T_690
connect _WIRE_2[26], _T_691
connect _WIRE_2[27], _T_692
connect _WIRE_2[28], _T_693
connect _WIRE_2[29], _T_694
node _T_695 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_696 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_697 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_698 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_699 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_700 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_701 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_702 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_703 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_704 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_705 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_706 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_707 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_708 = mux(_WIRE_2[5], _T_695, UInt<1>(0h0))
node _T_709 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_710 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_711 = mux(_WIRE_2[8], _T_696, UInt<1>(0h0))
node _T_712 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_713 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_714 = mux(_WIRE_2[11], _T_697, UInt<1>(0h0))
node _T_715 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0))
node _T_716 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0))
node _T_717 = mux(_WIRE_2[14], _T_698, UInt<1>(0h0))
node _T_718 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0))
node _T_719 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_720 = mux(_WIRE_2[17], _T_699, UInt<1>(0h0))
node _T_721 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0))
node _T_722 = mux(_WIRE_2[19], UInt<1>(0h0), UInt<1>(0h0))
node _T_723 = mux(_WIRE_2[20], _T_700, UInt<1>(0h0))
node _T_724 = mux(_WIRE_2[21], UInt<1>(0h0), UInt<1>(0h0))
node _T_725 = mux(_WIRE_2[22], UInt<1>(0h0), UInt<1>(0h0))
node _T_726 = mux(_WIRE_2[23], _T_701, UInt<1>(0h0))
node _T_727 = mux(_WIRE_2[24], UInt<1>(0h0), UInt<1>(0h0))
node _T_728 = mux(_WIRE_2[25], UInt<1>(0h0), UInt<1>(0h0))
node _T_729 = mux(_WIRE_2[26], _T_702, UInt<1>(0h0))
node _T_730 = mux(_WIRE_2[27], UInt<1>(0h0), UInt<1>(0h0))
node _T_731 = mux(_WIRE_2[28], UInt<1>(0h0), UInt<1>(0h0))
node _T_732 = mux(_WIRE_2[29], UInt<1>(0h0), UInt<1>(0h0))
node _T_733 = or(_T_703, _T_704)
node _T_734 = or(_T_733, _T_705)
node _T_735 = or(_T_734, _T_706)
node _T_736 = or(_T_735, _T_707)
node _T_737 = or(_T_736, _T_708)
node _T_738 = or(_T_737, _T_709)
node _T_739 = or(_T_738, _T_710)
node _T_740 = or(_T_739, _T_711)
node _T_741 = or(_T_740, _T_712)
node _T_742 = or(_T_741, _T_713)
node _T_743 = or(_T_742, _T_714)
node _T_744 = or(_T_743, _T_715)
node _T_745 = or(_T_744, _T_716)
node _T_746 = or(_T_745, _T_717)
node _T_747 = or(_T_746, _T_718)
node _T_748 = or(_T_747, _T_719)
node _T_749 = or(_T_748, _T_720)
node _T_750 = or(_T_749, _T_721)
node _T_751 = or(_T_750, _T_722)
node _T_752 = or(_T_751, _T_723)
node _T_753 = or(_T_752, _T_724)
node _T_754 = or(_T_753, _T_725)
node _T_755 = or(_T_754, _T_726)
node _T_756 = or(_T_755, _T_727)
node _T_757 = or(_T_756, _T_728)
node _T_758 = or(_T_757, _T_729)
node _T_759 = or(_T_758, _T_730)
node _T_760 = or(_T_759, _T_731)
node _T_761 = or(_T_760, _T_732)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_761
node _T_762 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_763 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_764 = and(_T_762, _T_763)
node _T_765 = or(UInt<1>(0h0), _T_764)
node _T_766 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_767 = cvt(_T_766)
node _T_768 = and(_T_767, asSInt(UInt<27>(0h4000000)))
node _T_769 = asSInt(_T_768)
node _T_770 = eq(_T_769, asSInt(UInt<1>(0h0)))
node _T_771 = and(_T_765, _T_770)
node _T_772 = or(UInt<1>(0h0), _T_771)
node _T_773 = and(_WIRE_3, _T_772)
node _T_774 = asUInt(reset)
node _T_775 = eq(_T_774, UInt<1>(0h0))
when _T_775 :
node _T_776 = eq(_T_773, UInt<1>(0h0))
when _T_776 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_773, UInt<1>(0h1), "") : assert_11
node _T_777 = asUInt(reset)
node _T_778 = eq(_T_777, UInt<1>(0h0))
when _T_778 :
node _T_779 = eq(source_ok, UInt<1>(0h0))
when _T_779 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_780 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_781 = asUInt(reset)
node _T_782 = eq(_T_781, UInt<1>(0h0))
when _T_782 :
node _T_783 = eq(_T_780, UInt<1>(0h0))
when _T_783 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_780, UInt<1>(0h1), "") : assert_13
node _T_784 = asUInt(reset)
node _T_785 = eq(_T_784, UInt<1>(0h0))
when _T_785 :
node _T_786 = eq(is_aligned, UInt<1>(0h0))
when _T_786 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_787 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_788 = asUInt(reset)
node _T_789 = eq(_T_788, UInt<1>(0h0))
when _T_789 :
node _T_790 = eq(_T_787, UInt<1>(0h0))
when _T_790 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_787, UInt<1>(0h1), "") : assert_15
node _T_791 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_792 = asUInt(reset)
node _T_793 = eq(_T_792, UInt<1>(0h0))
when _T_793 :
node _T_794 = eq(_T_791, UInt<1>(0h0))
when _T_794 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_791, UInt<1>(0h1), "") : assert_16
node _T_795 = not(io.in.a.bits.mask)
node _T_796 = eq(_T_795, UInt<1>(0h0))
node _T_797 = asUInt(reset)
node _T_798 = eq(_T_797, UInt<1>(0h0))
when _T_798 :
node _T_799 = eq(_T_796, UInt<1>(0h0))
when _T_799 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_796, UInt<1>(0h1), "") : assert_17
node _T_800 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_801 = asUInt(reset)
node _T_802 = eq(_T_801, UInt<1>(0h0))
when _T_802 :
node _T_803 = eq(_T_800, UInt<1>(0h0))
when _T_803 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_800, UInt<1>(0h1), "") : assert_18
node _T_804 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_804 :
node _T_805 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_806 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_807 = and(_T_805, _T_806)
node _T_808 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_809 = shr(io.in.a.bits.source, 2)
node _T_810 = eq(_T_809, UInt<1>(0h0))
node _T_811 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_812 = and(_T_810, _T_811)
node _T_813 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_814 = and(_T_812, _T_813)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_815 = shr(io.in.a.bits.source, 2)
node _T_816 = eq(_T_815, UInt<1>(0h1))
node _T_817 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_818 = and(_T_816, _T_817)
node _T_819 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_820 = and(_T_818, _T_819)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_821 = shr(io.in.a.bits.source, 2)
node _T_822 = eq(_T_821, UInt<2>(0h2))
node _T_823 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_824 = and(_T_822, _T_823)
node _T_825 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_826 = and(_T_824, _T_825)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_827 = shr(io.in.a.bits.source, 2)
node _T_828 = eq(_T_827, UInt<2>(0h3))
node _T_829 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_830 = and(_T_828, _T_829)
node _T_831 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_832 = and(_T_830, _T_831)
node _T_833 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_834 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_835 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_836 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_837 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_838 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_839 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_840 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_841 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_842 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_843 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_844 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_845 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_846 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_847 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_848 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_849 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_850 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_851 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_852 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_853 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_854 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_855 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_856 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_857 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_858 = or(_T_808, _T_814)
node _T_859 = or(_T_858, _T_820)
node _T_860 = or(_T_859, _T_826)
node _T_861 = or(_T_860, _T_832)
node _T_862 = or(_T_861, _T_833)
node _T_863 = or(_T_862, _T_834)
node _T_864 = or(_T_863, _T_835)
node _T_865 = or(_T_864, _T_836)
node _T_866 = or(_T_865, _T_837)
node _T_867 = or(_T_866, _T_838)
node _T_868 = or(_T_867, _T_839)
node _T_869 = or(_T_868, _T_840)
node _T_870 = or(_T_869, _T_841)
node _T_871 = or(_T_870, _T_842)
node _T_872 = or(_T_871, _T_843)
node _T_873 = or(_T_872, _T_844)
node _T_874 = or(_T_873, _T_845)
node _T_875 = or(_T_874, _T_846)
node _T_876 = or(_T_875, _T_847)
node _T_877 = or(_T_876, _T_848)
node _T_878 = or(_T_877, _T_849)
node _T_879 = or(_T_878, _T_850)
node _T_880 = or(_T_879, _T_851)
node _T_881 = or(_T_880, _T_852)
node _T_882 = or(_T_881, _T_853)
node _T_883 = or(_T_882, _T_854)
node _T_884 = or(_T_883, _T_855)
node _T_885 = or(_T_884, _T_856)
node _T_886 = or(_T_885, _T_857)
node _T_887 = and(_T_807, _T_886)
node _T_888 = or(UInt<1>(0h0), _T_887)
node _T_889 = asUInt(reset)
node _T_890 = eq(_T_889, UInt<1>(0h0))
when _T_890 :
node _T_891 = eq(_T_888, UInt<1>(0h0))
when _T_891 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_888, UInt<1>(0h1), "") : assert_19
node _T_892 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_893 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_894 = and(_T_892, _T_893)
node _T_895 = or(UInt<1>(0h0), _T_894)
node _T_896 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_897 = cvt(_T_896)
node _T_898 = and(_T_897, asSInt(UInt<27>(0h4000000)))
node _T_899 = asSInt(_T_898)
node _T_900 = eq(_T_899, asSInt(UInt<1>(0h0)))
node _T_901 = and(_T_895, _T_900)
node _T_902 = or(UInt<1>(0h0), _T_901)
node _T_903 = asUInt(reset)
node _T_904 = eq(_T_903, UInt<1>(0h0))
when _T_904 :
node _T_905 = eq(_T_902, UInt<1>(0h0))
when _T_905 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_902, UInt<1>(0h1), "") : assert_20
node _T_906 = asUInt(reset)
node _T_907 = eq(_T_906, UInt<1>(0h0))
when _T_907 :
node _T_908 = eq(source_ok, UInt<1>(0h0))
when _T_908 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_909 = asUInt(reset)
node _T_910 = eq(_T_909, UInt<1>(0h0))
when _T_910 :
node _T_911 = eq(is_aligned, UInt<1>(0h0))
when _T_911 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_912 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_913 = asUInt(reset)
node _T_914 = eq(_T_913, UInt<1>(0h0))
when _T_914 :
node _T_915 = eq(_T_912, UInt<1>(0h0))
when _T_915 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_912, UInt<1>(0h1), "") : assert_23
node _T_916 = eq(io.in.a.bits.mask, mask)
node _T_917 = asUInt(reset)
node _T_918 = eq(_T_917, UInt<1>(0h0))
when _T_918 :
node _T_919 = eq(_T_916, UInt<1>(0h0))
when _T_919 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_916, UInt<1>(0h1), "") : assert_24
node _T_920 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_921 = asUInt(reset)
node _T_922 = eq(_T_921, UInt<1>(0h0))
when _T_922 :
node _T_923 = eq(_T_920, UInt<1>(0h0))
when _T_923 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_920, UInt<1>(0h1), "") : assert_25
node _T_924 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_924 :
node _T_925 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_926 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_927 = and(_T_925, _T_926)
node _T_928 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_929 = shr(io.in.a.bits.source, 2)
node _T_930 = eq(_T_929, UInt<1>(0h0))
node _T_931 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_932 = and(_T_930, _T_931)
node _T_933 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_934 = and(_T_932, _T_933)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_935 = shr(io.in.a.bits.source, 2)
node _T_936 = eq(_T_935, UInt<1>(0h1))
node _T_937 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_938 = and(_T_936, _T_937)
node _T_939 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_940 = and(_T_938, _T_939)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_941 = shr(io.in.a.bits.source, 2)
node _T_942 = eq(_T_941, UInt<2>(0h2))
node _T_943 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_944 = and(_T_942, _T_943)
node _T_945 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_946 = and(_T_944, _T_945)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_947 = shr(io.in.a.bits.source, 2)
node _T_948 = eq(_T_947, UInt<2>(0h3))
node _T_949 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_950 = and(_T_948, _T_949)
node _T_951 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_952 = and(_T_950, _T_951)
node _T_953 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_954 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_955 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_956 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_957 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_958 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_959 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_960 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_961 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_962 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_963 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_964 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_965 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_966 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_967 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_968 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_969 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_970 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_971 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_972 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_973 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_974 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_975 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_976 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_977 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_978 = or(_T_928, _T_934)
node _T_979 = or(_T_978, _T_940)
node _T_980 = or(_T_979, _T_946)
node _T_981 = or(_T_980, _T_952)
node _T_982 = or(_T_981, _T_953)
node _T_983 = or(_T_982, _T_954)
node _T_984 = or(_T_983, _T_955)
node _T_985 = or(_T_984, _T_956)
node _T_986 = or(_T_985, _T_957)
node _T_987 = or(_T_986, _T_958)
node _T_988 = or(_T_987, _T_959)
node _T_989 = or(_T_988, _T_960)
node _T_990 = or(_T_989, _T_961)
node _T_991 = or(_T_990, _T_962)
node _T_992 = or(_T_991, _T_963)
node _T_993 = or(_T_992, _T_964)
node _T_994 = or(_T_993, _T_965)
node _T_995 = or(_T_994, _T_966)
node _T_996 = or(_T_995, _T_967)
node _T_997 = or(_T_996, _T_968)
node _T_998 = or(_T_997, _T_969)
node _T_999 = or(_T_998, _T_970)
node _T_1000 = or(_T_999, _T_971)
node _T_1001 = or(_T_1000, _T_972)
node _T_1002 = or(_T_1001, _T_973)
node _T_1003 = or(_T_1002, _T_974)
node _T_1004 = or(_T_1003, _T_975)
node _T_1005 = or(_T_1004, _T_976)
node _T_1006 = or(_T_1005, _T_977)
node _T_1007 = and(_T_927, _T_1006)
node _T_1008 = or(UInt<1>(0h0), _T_1007)
node _T_1009 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1010 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1011 = and(_T_1009, _T_1010)
node _T_1012 = or(UInt<1>(0h0), _T_1011)
node _T_1013 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1014 = cvt(_T_1013)
node _T_1015 = and(_T_1014, asSInt(UInt<27>(0h4000000)))
node _T_1016 = asSInt(_T_1015)
node _T_1017 = eq(_T_1016, asSInt(UInt<1>(0h0)))
node _T_1018 = and(_T_1012, _T_1017)
node _T_1019 = or(UInt<1>(0h0), _T_1018)
node _T_1020 = and(_T_1008, _T_1019)
node _T_1021 = asUInt(reset)
node _T_1022 = eq(_T_1021, UInt<1>(0h0))
when _T_1022 :
node _T_1023 = eq(_T_1020, UInt<1>(0h0))
when _T_1023 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_1020, UInt<1>(0h1), "") : assert_26
node _T_1024 = asUInt(reset)
node _T_1025 = eq(_T_1024, UInt<1>(0h0))
when _T_1025 :
node _T_1026 = eq(source_ok, UInt<1>(0h0))
when _T_1026 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_1027 = asUInt(reset)
node _T_1028 = eq(_T_1027, UInt<1>(0h0))
when _T_1028 :
node _T_1029 = eq(is_aligned, UInt<1>(0h0))
when _T_1029 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_1030 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_1031 = asUInt(reset)
node _T_1032 = eq(_T_1031, UInt<1>(0h0))
when _T_1032 :
node _T_1033 = eq(_T_1030, UInt<1>(0h0))
when _T_1033 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_1030, UInt<1>(0h1), "") : assert_29
node _T_1034 = eq(io.in.a.bits.mask, mask)
node _T_1035 = asUInt(reset)
node _T_1036 = eq(_T_1035, UInt<1>(0h0))
when _T_1036 :
node _T_1037 = eq(_T_1034, UInt<1>(0h0))
when _T_1037 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_1034, UInt<1>(0h1), "") : assert_30
node _T_1038 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_1038 :
node _T_1039 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1040 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1041 = and(_T_1039, _T_1040)
node _T_1042 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_1043 = shr(io.in.a.bits.source, 2)
node _T_1044 = eq(_T_1043, UInt<1>(0h0))
node _T_1045 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_1046 = and(_T_1044, _T_1045)
node _T_1047 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_1048 = and(_T_1046, _T_1047)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_1049 = shr(io.in.a.bits.source, 2)
node _T_1050 = eq(_T_1049, UInt<1>(0h1))
node _T_1051 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_1052 = and(_T_1050, _T_1051)
node _T_1053 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_1054 = and(_T_1052, _T_1053)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_1055 = shr(io.in.a.bits.source, 2)
node _T_1056 = eq(_T_1055, UInt<2>(0h2))
node _T_1057 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_1058 = and(_T_1056, _T_1057)
node _T_1059 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_1060 = and(_T_1058, _T_1059)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_1061 = shr(io.in.a.bits.source, 2)
node _T_1062 = eq(_T_1061, UInt<2>(0h3))
node _T_1063 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_1064 = and(_T_1062, _T_1063)
node _T_1065 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_1066 = and(_T_1064, _T_1065)
node _T_1067 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_1068 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_1069 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_1070 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_1071 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_1072 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_1073 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_1074 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_1075 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_1076 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_1077 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_1078 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_1079 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_1080 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_1081 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_1082 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1083 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_1084 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1085 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1086 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1087 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1088 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1089 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1090 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1091 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1092 = or(_T_1042, _T_1048)
node _T_1093 = or(_T_1092, _T_1054)
node _T_1094 = or(_T_1093, _T_1060)
node _T_1095 = or(_T_1094, _T_1066)
node _T_1096 = or(_T_1095, _T_1067)
node _T_1097 = or(_T_1096, _T_1068)
node _T_1098 = or(_T_1097, _T_1069)
node _T_1099 = or(_T_1098, _T_1070)
node _T_1100 = or(_T_1099, _T_1071)
node _T_1101 = or(_T_1100, _T_1072)
node _T_1102 = or(_T_1101, _T_1073)
node _T_1103 = or(_T_1102, _T_1074)
node _T_1104 = or(_T_1103, _T_1075)
node _T_1105 = or(_T_1104, _T_1076)
node _T_1106 = or(_T_1105, _T_1077)
node _T_1107 = or(_T_1106, _T_1078)
node _T_1108 = or(_T_1107, _T_1079)
node _T_1109 = or(_T_1108, _T_1080)
node _T_1110 = or(_T_1109, _T_1081)
node _T_1111 = or(_T_1110, _T_1082)
node _T_1112 = or(_T_1111, _T_1083)
node _T_1113 = or(_T_1112, _T_1084)
node _T_1114 = or(_T_1113, _T_1085)
node _T_1115 = or(_T_1114, _T_1086)
node _T_1116 = or(_T_1115, _T_1087)
node _T_1117 = or(_T_1116, _T_1088)
node _T_1118 = or(_T_1117, _T_1089)
node _T_1119 = or(_T_1118, _T_1090)
node _T_1120 = or(_T_1119, _T_1091)
node _T_1121 = and(_T_1041, _T_1120)
node _T_1122 = or(UInt<1>(0h0), _T_1121)
node _T_1123 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1124 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1125 = and(_T_1123, _T_1124)
node _T_1126 = or(UInt<1>(0h0), _T_1125)
node _T_1127 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1128 = cvt(_T_1127)
node _T_1129 = and(_T_1128, asSInt(UInt<27>(0h4000000)))
node _T_1130 = asSInt(_T_1129)
node _T_1131 = eq(_T_1130, asSInt(UInt<1>(0h0)))
node _T_1132 = and(_T_1126, _T_1131)
node _T_1133 = or(UInt<1>(0h0), _T_1132)
node _T_1134 = and(_T_1122, _T_1133)
node _T_1135 = asUInt(reset)
node _T_1136 = eq(_T_1135, UInt<1>(0h0))
when _T_1136 :
node _T_1137 = eq(_T_1134, UInt<1>(0h0))
when _T_1137 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_1134, UInt<1>(0h1), "") : assert_31
node _T_1138 = asUInt(reset)
node _T_1139 = eq(_T_1138, UInt<1>(0h0))
when _T_1139 :
node _T_1140 = eq(source_ok, UInt<1>(0h0))
when _T_1140 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_1141 = asUInt(reset)
node _T_1142 = eq(_T_1141, UInt<1>(0h0))
when _T_1142 :
node _T_1143 = eq(is_aligned, UInt<1>(0h0))
when _T_1143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_1144 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_1145 = asUInt(reset)
node _T_1146 = eq(_T_1145, UInt<1>(0h0))
when _T_1146 :
node _T_1147 = eq(_T_1144, UInt<1>(0h0))
when _T_1147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_1144, UInt<1>(0h1), "") : assert_34
node _T_1148 = not(mask)
node _T_1149 = and(io.in.a.bits.mask, _T_1148)
node _T_1150 = eq(_T_1149, UInt<1>(0h0))
node _T_1151 = asUInt(reset)
node _T_1152 = eq(_T_1151, UInt<1>(0h0))
when _T_1152 :
node _T_1153 = eq(_T_1150, UInt<1>(0h0))
when _T_1153 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_1150, UInt<1>(0h1), "") : assert_35
node _T_1154 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_1154 :
node _T_1155 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1156 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1157 = and(_T_1155, _T_1156)
node _T_1158 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_1159 = shr(io.in.a.bits.source, 2)
node _T_1160 = eq(_T_1159, UInt<1>(0h0))
node _T_1161 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_1162 = and(_T_1160, _T_1161)
node _T_1163 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_1164 = and(_T_1162, _T_1163)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_1165 = shr(io.in.a.bits.source, 2)
node _T_1166 = eq(_T_1165, UInt<1>(0h1))
node _T_1167 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_1168 = and(_T_1166, _T_1167)
node _T_1169 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_1170 = and(_T_1168, _T_1169)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_1171 = shr(io.in.a.bits.source, 2)
node _T_1172 = eq(_T_1171, UInt<2>(0h2))
node _T_1173 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_1174 = and(_T_1172, _T_1173)
node _T_1175 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_1176 = and(_T_1174, _T_1175)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_1177 = shr(io.in.a.bits.source, 2)
node _T_1178 = eq(_T_1177, UInt<2>(0h3))
node _T_1179 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_1180 = and(_T_1178, _T_1179)
node _T_1181 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_1182 = and(_T_1180, _T_1181)
node _T_1183 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_1184 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_1185 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_1186 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_1187 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_1188 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_1189 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_1190 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_1191 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_1192 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_1193 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_1194 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_1195 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_1196 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_1197 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_1198 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1199 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_1200 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1201 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1202 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1203 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1204 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1205 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1206 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1207 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1208 = or(_T_1158, _T_1164)
node _T_1209 = or(_T_1208, _T_1170)
node _T_1210 = or(_T_1209, _T_1176)
node _T_1211 = or(_T_1210, _T_1182)
node _T_1212 = or(_T_1211, _T_1183)
node _T_1213 = or(_T_1212, _T_1184)
node _T_1214 = or(_T_1213, _T_1185)
node _T_1215 = or(_T_1214, _T_1186)
node _T_1216 = or(_T_1215, _T_1187)
node _T_1217 = or(_T_1216, _T_1188)
node _T_1218 = or(_T_1217, _T_1189)
node _T_1219 = or(_T_1218, _T_1190)
node _T_1220 = or(_T_1219, _T_1191)
node _T_1221 = or(_T_1220, _T_1192)
node _T_1222 = or(_T_1221, _T_1193)
node _T_1223 = or(_T_1222, _T_1194)
node _T_1224 = or(_T_1223, _T_1195)
node _T_1225 = or(_T_1224, _T_1196)
node _T_1226 = or(_T_1225, _T_1197)
node _T_1227 = or(_T_1226, _T_1198)
node _T_1228 = or(_T_1227, _T_1199)
node _T_1229 = or(_T_1228, _T_1200)
node _T_1230 = or(_T_1229, _T_1201)
node _T_1231 = or(_T_1230, _T_1202)
node _T_1232 = or(_T_1231, _T_1203)
node _T_1233 = or(_T_1232, _T_1204)
node _T_1234 = or(_T_1233, _T_1205)
node _T_1235 = or(_T_1234, _T_1206)
node _T_1236 = or(_T_1235, _T_1207)
node _T_1237 = and(_T_1157, _T_1236)
node _T_1238 = or(UInt<1>(0h0), _T_1237)
node _T_1239 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1240 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1241 = cvt(_T_1240)
node _T_1242 = and(_T_1241, asSInt(UInt<27>(0h4000000)))
node _T_1243 = asSInt(_T_1242)
node _T_1244 = eq(_T_1243, asSInt(UInt<1>(0h0)))
node _T_1245 = and(_T_1239, _T_1244)
node _T_1246 = or(UInt<1>(0h0), _T_1245)
node _T_1247 = and(_T_1238, _T_1246)
node _T_1248 = asUInt(reset)
node _T_1249 = eq(_T_1248, UInt<1>(0h0))
when _T_1249 :
node _T_1250 = eq(_T_1247, UInt<1>(0h0))
when _T_1250 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_1247, UInt<1>(0h1), "") : assert_36
node _T_1251 = asUInt(reset)
node _T_1252 = eq(_T_1251, UInt<1>(0h0))
when _T_1252 :
node _T_1253 = eq(source_ok, UInt<1>(0h0))
when _T_1253 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_1254 = asUInt(reset)
node _T_1255 = eq(_T_1254, UInt<1>(0h0))
when _T_1255 :
node _T_1256 = eq(is_aligned, UInt<1>(0h0))
when _T_1256 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_1257 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_1258 = asUInt(reset)
node _T_1259 = eq(_T_1258, UInt<1>(0h0))
when _T_1259 :
node _T_1260 = eq(_T_1257, UInt<1>(0h0))
when _T_1260 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_1257, UInt<1>(0h1), "") : assert_39
node _T_1261 = eq(io.in.a.bits.mask, mask)
node _T_1262 = asUInt(reset)
node _T_1263 = eq(_T_1262, UInt<1>(0h0))
when _T_1263 :
node _T_1264 = eq(_T_1261, UInt<1>(0h0))
when _T_1264 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_1261, UInt<1>(0h1), "") : assert_40
node _T_1265 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_1265 :
node _T_1266 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1267 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1268 = and(_T_1266, _T_1267)
node _T_1269 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_1270 = shr(io.in.a.bits.source, 2)
node _T_1271 = eq(_T_1270, UInt<1>(0h0))
node _T_1272 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_1273 = and(_T_1271, _T_1272)
node _T_1274 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_1275 = and(_T_1273, _T_1274)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_1276 = shr(io.in.a.bits.source, 2)
node _T_1277 = eq(_T_1276, UInt<1>(0h1))
node _T_1278 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_1279 = and(_T_1277, _T_1278)
node _T_1280 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_1281 = and(_T_1279, _T_1280)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_1282 = shr(io.in.a.bits.source, 2)
node _T_1283 = eq(_T_1282, UInt<2>(0h2))
node _T_1284 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_1285 = and(_T_1283, _T_1284)
node _T_1286 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_1287 = and(_T_1285, _T_1286)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_1288 = shr(io.in.a.bits.source, 2)
node _T_1289 = eq(_T_1288, UInt<2>(0h3))
node _T_1290 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_1291 = and(_T_1289, _T_1290)
node _T_1292 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_1293 = and(_T_1291, _T_1292)
node _T_1294 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_1295 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_1296 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_1297 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_1298 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_1299 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_1300 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_1301 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_1302 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_1303 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_1304 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_1305 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_1306 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_1307 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_1308 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_1309 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1310 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_1311 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1312 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1313 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1314 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1315 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1316 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1317 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1318 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1319 = or(_T_1269, _T_1275)
node _T_1320 = or(_T_1319, _T_1281)
node _T_1321 = or(_T_1320, _T_1287)
node _T_1322 = or(_T_1321, _T_1293)
node _T_1323 = or(_T_1322, _T_1294)
node _T_1324 = or(_T_1323, _T_1295)
node _T_1325 = or(_T_1324, _T_1296)
node _T_1326 = or(_T_1325, _T_1297)
node _T_1327 = or(_T_1326, _T_1298)
node _T_1328 = or(_T_1327, _T_1299)
node _T_1329 = or(_T_1328, _T_1300)
node _T_1330 = or(_T_1329, _T_1301)
node _T_1331 = or(_T_1330, _T_1302)
node _T_1332 = or(_T_1331, _T_1303)
node _T_1333 = or(_T_1332, _T_1304)
node _T_1334 = or(_T_1333, _T_1305)
node _T_1335 = or(_T_1334, _T_1306)
node _T_1336 = or(_T_1335, _T_1307)
node _T_1337 = or(_T_1336, _T_1308)
node _T_1338 = or(_T_1337, _T_1309)
node _T_1339 = or(_T_1338, _T_1310)
node _T_1340 = or(_T_1339, _T_1311)
node _T_1341 = or(_T_1340, _T_1312)
node _T_1342 = or(_T_1341, _T_1313)
node _T_1343 = or(_T_1342, _T_1314)
node _T_1344 = or(_T_1343, _T_1315)
node _T_1345 = or(_T_1344, _T_1316)
node _T_1346 = or(_T_1345, _T_1317)
node _T_1347 = or(_T_1346, _T_1318)
node _T_1348 = and(_T_1268, _T_1347)
node _T_1349 = or(UInt<1>(0h0), _T_1348)
node _T_1350 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1351 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1352 = cvt(_T_1351)
node _T_1353 = and(_T_1352, asSInt(UInt<27>(0h4000000)))
node _T_1354 = asSInt(_T_1353)
node _T_1355 = eq(_T_1354, asSInt(UInt<1>(0h0)))
node _T_1356 = and(_T_1350, _T_1355)
node _T_1357 = or(UInt<1>(0h0), _T_1356)
node _T_1358 = and(_T_1349, _T_1357)
node _T_1359 = asUInt(reset)
node _T_1360 = eq(_T_1359, UInt<1>(0h0))
when _T_1360 :
node _T_1361 = eq(_T_1358, UInt<1>(0h0))
when _T_1361 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_1358, UInt<1>(0h1), "") : assert_41
node _T_1362 = asUInt(reset)
node _T_1363 = eq(_T_1362, UInt<1>(0h0))
when _T_1363 :
node _T_1364 = eq(source_ok, UInt<1>(0h0))
when _T_1364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_1365 = asUInt(reset)
node _T_1366 = eq(_T_1365, UInt<1>(0h0))
when _T_1366 :
node _T_1367 = eq(is_aligned, UInt<1>(0h0))
when _T_1367 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_1368 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_1369 = asUInt(reset)
node _T_1370 = eq(_T_1369, UInt<1>(0h0))
when _T_1370 :
node _T_1371 = eq(_T_1368, UInt<1>(0h0))
when _T_1371 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_1368, UInt<1>(0h1), "") : assert_44
node _T_1372 = eq(io.in.a.bits.mask, mask)
node _T_1373 = asUInt(reset)
node _T_1374 = eq(_T_1373, UInt<1>(0h0))
when _T_1374 :
node _T_1375 = eq(_T_1372, UInt<1>(0h0))
when _T_1375 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_1372, UInt<1>(0h1), "") : assert_45
node _T_1376 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_1376 :
node _T_1377 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1378 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1379 = and(_T_1377, _T_1378)
node _T_1380 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0)
node _T_1381 = shr(io.in.a.bits.source, 2)
node _T_1382 = eq(_T_1381, UInt<1>(0h0))
node _T_1383 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_1384 = and(_T_1382, _T_1383)
node _T_1385 = leq(uncommonBits_40, UInt<2>(0h3))
node _T_1386 = and(_T_1384, _T_1385)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0)
node _T_1387 = shr(io.in.a.bits.source, 2)
node _T_1388 = eq(_T_1387, UInt<1>(0h1))
node _T_1389 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_1390 = and(_T_1388, _T_1389)
node _T_1391 = leq(uncommonBits_41, UInt<2>(0h3))
node _T_1392 = and(_T_1390, _T_1391)
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_1393 = shr(io.in.a.bits.source, 2)
node _T_1394 = eq(_T_1393, UInt<2>(0h2))
node _T_1395 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_1396 = and(_T_1394, _T_1395)
node _T_1397 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_1398 = and(_T_1396, _T_1397)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_1399 = shr(io.in.a.bits.source, 2)
node _T_1400 = eq(_T_1399, UInt<2>(0h3))
node _T_1401 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_1402 = and(_T_1400, _T_1401)
node _T_1403 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_1404 = and(_T_1402, _T_1403)
node _T_1405 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_1406 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_1407 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_1408 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_1409 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_1410 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_1411 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_1412 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_1413 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_1414 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_1415 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_1416 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_1417 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_1418 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_1419 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_1420 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1421 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_1422 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1423 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1424 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1425 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1426 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1427 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1428 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1429 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1430 = or(_T_1380, _T_1386)
node _T_1431 = or(_T_1430, _T_1392)
node _T_1432 = or(_T_1431, _T_1398)
node _T_1433 = or(_T_1432, _T_1404)
node _T_1434 = or(_T_1433, _T_1405)
node _T_1435 = or(_T_1434, _T_1406)
node _T_1436 = or(_T_1435, _T_1407)
node _T_1437 = or(_T_1436, _T_1408)
node _T_1438 = or(_T_1437, _T_1409)
node _T_1439 = or(_T_1438, _T_1410)
node _T_1440 = or(_T_1439, _T_1411)
node _T_1441 = or(_T_1440, _T_1412)
node _T_1442 = or(_T_1441, _T_1413)
node _T_1443 = or(_T_1442, _T_1414)
node _T_1444 = or(_T_1443, _T_1415)
node _T_1445 = or(_T_1444, _T_1416)
node _T_1446 = or(_T_1445, _T_1417)
node _T_1447 = or(_T_1446, _T_1418)
node _T_1448 = or(_T_1447, _T_1419)
node _T_1449 = or(_T_1448, _T_1420)
node _T_1450 = or(_T_1449, _T_1421)
node _T_1451 = or(_T_1450, _T_1422)
node _T_1452 = or(_T_1451, _T_1423)
node _T_1453 = or(_T_1452, _T_1424)
node _T_1454 = or(_T_1453, _T_1425)
node _T_1455 = or(_T_1454, _T_1426)
node _T_1456 = or(_T_1455, _T_1427)
node _T_1457 = or(_T_1456, _T_1428)
node _T_1458 = or(_T_1457, _T_1429)
node _T_1459 = and(_T_1379, _T_1458)
node _T_1460 = or(UInt<1>(0h0), _T_1459)
node _T_1461 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1462 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1463 = cvt(_T_1462)
node _T_1464 = and(_T_1463, asSInt(UInt<27>(0h4000000)))
node _T_1465 = asSInt(_T_1464)
node _T_1466 = eq(_T_1465, asSInt(UInt<1>(0h0)))
node _T_1467 = and(_T_1461, _T_1466)
node _T_1468 = or(UInt<1>(0h0), _T_1467)
node _T_1469 = and(_T_1460, _T_1468)
node _T_1470 = asUInt(reset)
node _T_1471 = eq(_T_1470, UInt<1>(0h0))
when _T_1471 :
node _T_1472 = eq(_T_1469, UInt<1>(0h0))
when _T_1472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1469, UInt<1>(0h1), "") : assert_46
node _T_1473 = asUInt(reset)
node _T_1474 = eq(_T_1473, UInt<1>(0h0))
when _T_1474 :
node _T_1475 = eq(source_ok, UInt<1>(0h0))
when _T_1475 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1476 = asUInt(reset)
node _T_1477 = eq(_T_1476, UInt<1>(0h0))
when _T_1477 :
node _T_1478 = eq(is_aligned, UInt<1>(0h0))
when _T_1478 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1479 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1480 = asUInt(reset)
node _T_1481 = eq(_T_1480, UInt<1>(0h0))
when _T_1481 :
node _T_1482 = eq(_T_1479, UInt<1>(0h0))
when _T_1482 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1479, UInt<1>(0h1), "") : assert_49
node _T_1483 = eq(io.in.a.bits.mask, mask)
node _T_1484 = asUInt(reset)
node _T_1485 = eq(_T_1484, UInt<1>(0h0))
when _T_1485 :
node _T_1486 = eq(_T_1483, UInt<1>(0h0))
when _T_1486 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1483, UInt<1>(0h1), "") : assert_50
node _T_1487 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1488 = asUInt(reset)
node _T_1489 = eq(_T_1488, UInt<1>(0h0))
when _T_1489 :
node _T_1490 = eq(_T_1487, UInt<1>(0h0))
when _T_1490 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1487, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1491 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1492 = asUInt(reset)
node _T_1493 = eq(_T_1492, UInt<1>(0h0))
when _T_1493 :
node _T_1494 = eq(_T_1491, UInt<1>(0h0))
when _T_1494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1491, UInt<1>(0h1), "") : assert_52
node _source_ok_T_78 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_79 = shr(io.in.d.bits.source, 2)
node _source_ok_T_80 = eq(_source_ok_T_79, UInt<1>(0h0))
node _source_ok_T_81 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81)
node _source_ok_T_83 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83)
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_85 = shr(io.in.d.bits.source, 2)
node _source_ok_T_86 = eq(_source_ok_T_85, UInt<1>(0h1))
node _source_ok_T_87 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87)
node _source_ok_T_89 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_90 = and(_source_ok_T_88, _source_ok_T_89)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_91 = shr(io.in.d.bits.source, 2)
node _source_ok_T_92 = eq(_source_ok_T_91, UInt<2>(0h2))
node _source_ok_T_93 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_94 = and(_source_ok_T_92, _source_ok_T_93)
node _source_ok_T_95 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_96 = and(_source_ok_T_94, _source_ok_T_95)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_97 = shr(io.in.d.bits.source, 2)
node _source_ok_T_98 = eq(_source_ok_T_97, UInt<2>(0h3))
node _source_ok_T_99 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_100 = and(_source_ok_T_98, _source_ok_T_99)
node _source_ok_T_101 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_102 = and(_source_ok_T_100, _source_ok_T_101)
node _source_ok_T_103 = eq(io.in.d.bits.source, UInt<6>(0h3c))
node _source_ok_T_104 = eq(io.in.d.bits.source, UInt<6>(0h3d))
node _source_ok_T_105 = eq(io.in.d.bits.source, UInt<6>(0h3e))
node _source_ok_T_106 = eq(io.in.d.bits.source, UInt<6>(0h38))
node _source_ok_T_107 = eq(io.in.d.bits.source, UInt<6>(0h39))
node _source_ok_T_108 = eq(io.in.d.bits.source, UInt<6>(0h3a))
node _source_ok_T_109 = eq(io.in.d.bits.source, UInt<6>(0h34))
node _source_ok_T_110 = eq(io.in.d.bits.source, UInt<6>(0h35))
node _source_ok_T_111 = eq(io.in.d.bits.source, UInt<6>(0h36))
node _source_ok_T_112 = eq(io.in.d.bits.source, UInt<6>(0h30))
node _source_ok_T_113 = eq(io.in.d.bits.source, UInt<6>(0h31))
node _source_ok_T_114 = eq(io.in.d.bits.source, UInt<6>(0h32))
node _source_ok_T_115 = eq(io.in.d.bits.source, UInt<6>(0h2c))
node _source_ok_T_116 = eq(io.in.d.bits.source, UInt<6>(0h2d))
node _source_ok_T_117 = eq(io.in.d.bits.source, UInt<6>(0h2e))
node _source_ok_T_118 = eq(io.in.d.bits.source, UInt<6>(0h28))
node _source_ok_T_119 = eq(io.in.d.bits.source, UInt<6>(0h29))
node _source_ok_T_120 = eq(io.in.d.bits.source, UInt<6>(0h2a))
node _source_ok_T_121 = eq(io.in.d.bits.source, UInt<6>(0h24))
node _source_ok_T_122 = eq(io.in.d.bits.source, UInt<6>(0h25))
node _source_ok_T_123 = eq(io.in.d.bits.source, UInt<6>(0h26))
node _source_ok_T_124 = eq(io.in.d.bits.source, UInt<6>(0h20))
node _source_ok_T_125 = eq(io.in.d.bits.source, UInt<6>(0h21))
node _source_ok_T_126 = eq(io.in.d.bits.source, UInt<6>(0h22))
node _source_ok_T_127 = eq(io.in.d.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE_1 : UInt<1>[30]
connect _source_ok_WIRE_1[0], _source_ok_T_78
connect _source_ok_WIRE_1[1], _source_ok_T_84
connect _source_ok_WIRE_1[2], _source_ok_T_90
connect _source_ok_WIRE_1[3], _source_ok_T_96
connect _source_ok_WIRE_1[4], _source_ok_T_102
connect _source_ok_WIRE_1[5], _source_ok_T_103
connect _source_ok_WIRE_1[6], _source_ok_T_104
connect _source_ok_WIRE_1[7], _source_ok_T_105
connect _source_ok_WIRE_1[8], _source_ok_T_106
connect _source_ok_WIRE_1[9], _source_ok_T_107
connect _source_ok_WIRE_1[10], _source_ok_T_108
connect _source_ok_WIRE_1[11], _source_ok_T_109
connect _source_ok_WIRE_1[12], _source_ok_T_110
connect _source_ok_WIRE_1[13], _source_ok_T_111
connect _source_ok_WIRE_1[14], _source_ok_T_112
connect _source_ok_WIRE_1[15], _source_ok_T_113
connect _source_ok_WIRE_1[16], _source_ok_T_114
connect _source_ok_WIRE_1[17], _source_ok_T_115
connect _source_ok_WIRE_1[18], _source_ok_T_116
connect _source_ok_WIRE_1[19], _source_ok_T_117
connect _source_ok_WIRE_1[20], _source_ok_T_118
connect _source_ok_WIRE_1[21], _source_ok_T_119
connect _source_ok_WIRE_1[22], _source_ok_T_120
connect _source_ok_WIRE_1[23], _source_ok_T_121
connect _source_ok_WIRE_1[24], _source_ok_T_122
connect _source_ok_WIRE_1[25], _source_ok_T_123
connect _source_ok_WIRE_1[26], _source_ok_T_124
connect _source_ok_WIRE_1[27], _source_ok_T_125
connect _source_ok_WIRE_1[28], _source_ok_T_126
connect _source_ok_WIRE_1[29], _source_ok_T_127
node _source_ok_T_128 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_129 = or(_source_ok_T_128, _source_ok_WIRE_1[2])
node _source_ok_T_130 = or(_source_ok_T_129, _source_ok_WIRE_1[3])
node _source_ok_T_131 = or(_source_ok_T_130, _source_ok_WIRE_1[4])
node _source_ok_T_132 = or(_source_ok_T_131, _source_ok_WIRE_1[5])
node _source_ok_T_133 = or(_source_ok_T_132, _source_ok_WIRE_1[6])
node _source_ok_T_134 = or(_source_ok_T_133, _source_ok_WIRE_1[7])
node _source_ok_T_135 = or(_source_ok_T_134, _source_ok_WIRE_1[8])
node _source_ok_T_136 = or(_source_ok_T_135, _source_ok_WIRE_1[9])
node _source_ok_T_137 = or(_source_ok_T_136, _source_ok_WIRE_1[10])
node _source_ok_T_138 = or(_source_ok_T_137, _source_ok_WIRE_1[11])
node _source_ok_T_139 = or(_source_ok_T_138, _source_ok_WIRE_1[12])
node _source_ok_T_140 = or(_source_ok_T_139, _source_ok_WIRE_1[13])
node _source_ok_T_141 = or(_source_ok_T_140, _source_ok_WIRE_1[14])
node _source_ok_T_142 = or(_source_ok_T_141, _source_ok_WIRE_1[15])
node _source_ok_T_143 = or(_source_ok_T_142, _source_ok_WIRE_1[16])
node _source_ok_T_144 = or(_source_ok_T_143, _source_ok_WIRE_1[17])
node _source_ok_T_145 = or(_source_ok_T_144, _source_ok_WIRE_1[18])
node _source_ok_T_146 = or(_source_ok_T_145, _source_ok_WIRE_1[19])
node _source_ok_T_147 = or(_source_ok_T_146, _source_ok_WIRE_1[20])
node _source_ok_T_148 = or(_source_ok_T_147, _source_ok_WIRE_1[21])
node _source_ok_T_149 = or(_source_ok_T_148, _source_ok_WIRE_1[22])
node _source_ok_T_150 = or(_source_ok_T_149, _source_ok_WIRE_1[23])
node _source_ok_T_151 = or(_source_ok_T_150, _source_ok_WIRE_1[24])
node _source_ok_T_152 = or(_source_ok_T_151, _source_ok_WIRE_1[25])
node _source_ok_T_153 = or(_source_ok_T_152, _source_ok_WIRE_1[26])
node _source_ok_T_154 = or(_source_ok_T_153, _source_ok_WIRE_1[27])
node _source_ok_T_155 = or(_source_ok_T_154, _source_ok_WIRE_1[28])
node source_ok_1 = or(_source_ok_T_155, _source_ok_WIRE_1[29])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1495 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1495 :
node _T_1496 = asUInt(reset)
node _T_1497 = eq(_T_1496, UInt<1>(0h0))
when _T_1497 :
node _T_1498 = eq(source_ok_1, UInt<1>(0h0))
when _T_1498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1499 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1500 = asUInt(reset)
node _T_1501 = eq(_T_1500, UInt<1>(0h0))
when _T_1501 :
node _T_1502 = eq(_T_1499, UInt<1>(0h0))
when _T_1502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1499, UInt<1>(0h1), "") : assert_54
node _T_1503 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1504 = asUInt(reset)
node _T_1505 = eq(_T_1504, UInt<1>(0h0))
when _T_1505 :
node _T_1506 = eq(_T_1503, UInt<1>(0h0))
when _T_1506 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1503, UInt<1>(0h1), "") : assert_55
node _T_1507 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1508 = asUInt(reset)
node _T_1509 = eq(_T_1508, UInt<1>(0h0))
when _T_1509 :
node _T_1510 = eq(_T_1507, UInt<1>(0h0))
when _T_1510 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1507, UInt<1>(0h1), "") : assert_56
node _T_1511 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1512 = asUInt(reset)
node _T_1513 = eq(_T_1512, UInt<1>(0h0))
when _T_1513 :
node _T_1514 = eq(_T_1511, UInt<1>(0h0))
when _T_1514 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1511, UInt<1>(0h1), "") : assert_57
node _T_1515 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1515 :
node _T_1516 = asUInt(reset)
node _T_1517 = eq(_T_1516, UInt<1>(0h0))
when _T_1517 :
node _T_1518 = eq(source_ok_1, UInt<1>(0h0))
when _T_1518 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1519 = asUInt(reset)
node _T_1520 = eq(_T_1519, UInt<1>(0h0))
when _T_1520 :
node _T_1521 = eq(sink_ok, UInt<1>(0h0))
when _T_1521 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1522 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1523 = asUInt(reset)
node _T_1524 = eq(_T_1523, UInt<1>(0h0))
when _T_1524 :
node _T_1525 = eq(_T_1522, UInt<1>(0h0))
when _T_1525 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1522, UInt<1>(0h1), "") : assert_60
node _T_1526 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1527 = asUInt(reset)
node _T_1528 = eq(_T_1527, UInt<1>(0h0))
when _T_1528 :
node _T_1529 = eq(_T_1526, UInt<1>(0h0))
when _T_1529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1526, UInt<1>(0h1), "") : assert_61
node _T_1530 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1531 = asUInt(reset)
node _T_1532 = eq(_T_1531, UInt<1>(0h0))
when _T_1532 :
node _T_1533 = eq(_T_1530, UInt<1>(0h0))
when _T_1533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1530, UInt<1>(0h1), "") : assert_62
node _T_1534 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1535 = asUInt(reset)
node _T_1536 = eq(_T_1535, UInt<1>(0h0))
when _T_1536 :
node _T_1537 = eq(_T_1534, UInt<1>(0h0))
when _T_1537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1534, UInt<1>(0h1), "") : assert_63
node _T_1538 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1539 = or(UInt<1>(0h0), _T_1538)
node _T_1540 = asUInt(reset)
node _T_1541 = eq(_T_1540, UInt<1>(0h0))
when _T_1541 :
node _T_1542 = eq(_T_1539, UInt<1>(0h0))
when _T_1542 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1539, UInt<1>(0h1), "") : assert_64
node _T_1543 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1543 :
node _T_1544 = asUInt(reset)
node _T_1545 = eq(_T_1544, UInt<1>(0h0))
when _T_1545 :
node _T_1546 = eq(source_ok_1, UInt<1>(0h0))
when _T_1546 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1547 = asUInt(reset)
node _T_1548 = eq(_T_1547, UInt<1>(0h0))
when _T_1548 :
node _T_1549 = eq(sink_ok, UInt<1>(0h0))
when _T_1549 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1550 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1551 = asUInt(reset)
node _T_1552 = eq(_T_1551, UInt<1>(0h0))
when _T_1552 :
node _T_1553 = eq(_T_1550, UInt<1>(0h0))
when _T_1553 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1550, UInt<1>(0h1), "") : assert_67
node _T_1554 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1555 = asUInt(reset)
node _T_1556 = eq(_T_1555, UInt<1>(0h0))
when _T_1556 :
node _T_1557 = eq(_T_1554, UInt<1>(0h0))
when _T_1557 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1554, UInt<1>(0h1), "") : assert_68
node _T_1558 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1559 = asUInt(reset)
node _T_1560 = eq(_T_1559, UInt<1>(0h0))
when _T_1560 :
node _T_1561 = eq(_T_1558, UInt<1>(0h0))
when _T_1561 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1558, UInt<1>(0h1), "") : assert_69
node _T_1562 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1563 = or(_T_1562, io.in.d.bits.corrupt)
node _T_1564 = asUInt(reset)
node _T_1565 = eq(_T_1564, UInt<1>(0h0))
when _T_1565 :
node _T_1566 = eq(_T_1563, UInt<1>(0h0))
when _T_1566 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1563, UInt<1>(0h1), "") : assert_70
node _T_1567 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1568 = or(UInt<1>(0h0), _T_1567)
node _T_1569 = asUInt(reset)
node _T_1570 = eq(_T_1569, UInt<1>(0h0))
when _T_1570 :
node _T_1571 = eq(_T_1568, UInt<1>(0h0))
when _T_1571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1568, UInt<1>(0h1), "") : assert_71
node _T_1572 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1572 :
node _T_1573 = asUInt(reset)
node _T_1574 = eq(_T_1573, UInt<1>(0h0))
when _T_1574 :
node _T_1575 = eq(source_ok_1, UInt<1>(0h0))
when _T_1575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1576 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1577 = asUInt(reset)
node _T_1578 = eq(_T_1577, UInt<1>(0h0))
when _T_1578 :
node _T_1579 = eq(_T_1576, UInt<1>(0h0))
when _T_1579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1576, UInt<1>(0h1), "") : assert_73
node _T_1580 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1581 = asUInt(reset)
node _T_1582 = eq(_T_1581, UInt<1>(0h0))
when _T_1582 :
node _T_1583 = eq(_T_1580, UInt<1>(0h0))
when _T_1583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1580, UInt<1>(0h1), "") : assert_74
node _T_1584 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1585 = or(UInt<1>(0h0), _T_1584)
node _T_1586 = asUInt(reset)
node _T_1587 = eq(_T_1586, UInt<1>(0h0))
when _T_1587 :
node _T_1588 = eq(_T_1585, UInt<1>(0h0))
when _T_1588 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1585, UInt<1>(0h1), "") : assert_75
node _T_1589 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1589 :
node _T_1590 = asUInt(reset)
node _T_1591 = eq(_T_1590, UInt<1>(0h0))
when _T_1591 :
node _T_1592 = eq(source_ok_1, UInt<1>(0h0))
when _T_1592 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1593 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1594 = asUInt(reset)
node _T_1595 = eq(_T_1594, UInt<1>(0h0))
when _T_1595 :
node _T_1596 = eq(_T_1593, UInt<1>(0h0))
when _T_1596 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1593, UInt<1>(0h1), "") : assert_77
node _T_1597 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1598 = or(_T_1597, io.in.d.bits.corrupt)
node _T_1599 = asUInt(reset)
node _T_1600 = eq(_T_1599, UInt<1>(0h0))
when _T_1600 :
node _T_1601 = eq(_T_1598, UInt<1>(0h0))
when _T_1601 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1598, UInt<1>(0h1), "") : assert_78
node _T_1602 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1603 = or(UInt<1>(0h0), _T_1602)
node _T_1604 = asUInt(reset)
node _T_1605 = eq(_T_1604, UInt<1>(0h0))
when _T_1605 :
node _T_1606 = eq(_T_1603, UInt<1>(0h0))
when _T_1606 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1603, UInt<1>(0h1), "") : assert_79
node _T_1607 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1607 :
node _T_1608 = asUInt(reset)
node _T_1609 = eq(_T_1608, UInt<1>(0h0))
when _T_1609 :
node _T_1610 = eq(source_ok_1, UInt<1>(0h0))
when _T_1610 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1611 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1612 = asUInt(reset)
node _T_1613 = eq(_T_1612, UInt<1>(0h0))
when _T_1613 :
node _T_1614 = eq(_T_1611, UInt<1>(0h0))
when _T_1614 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1611, UInt<1>(0h1), "") : assert_81
node _T_1615 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1616 = asUInt(reset)
node _T_1617 = eq(_T_1616, UInt<1>(0h0))
when _T_1617 :
node _T_1618 = eq(_T_1615, UInt<1>(0h0))
when _T_1618 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1615, UInt<1>(0h1), "") : assert_82
node _T_1619 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1620 = or(UInt<1>(0h0), _T_1619)
node _T_1621 = asUInt(reset)
node _T_1622 = eq(_T_1621, UInt<1>(0h0))
when _T_1622 :
node _T_1623 = eq(_T_1620, UInt<1>(0h0))
when _T_1623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1620, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<28>(0h0)
connect _WIRE_4.bits.source, UInt<7>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1624 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1625 = asUInt(reset)
node _T_1626 = eq(_T_1625, UInt<1>(0h0))
when _T_1626 :
node _T_1627 = eq(_T_1624, UInt<1>(0h0))
when _T_1627 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1624, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<28>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1628 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1629 = asUInt(reset)
node _T_1630 = eq(_T_1629, UInt<1>(0h0))
when _T_1630 :
node _T_1631 = eq(_T_1628, UInt<1>(0h0))
when _T_1631 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1628, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1632 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1633 = asUInt(reset)
node _T_1634 = eq(_T_1633, UInt<1>(0h0))
when _T_1634 :
node _T_1635 = eq(_T_1632, UInt<1>(0h0))
when _T_1635 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1632, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1636 = eq(a_first, UInt<1>(0h0))
node _T_1637 = and(io.in.a.valid, _T_1636)
when _T_1637 :
node _T_1638 = eq(io.in.a.bits.opcode, opcode)
node _T_1639 = asUInt(reset)
node _T_1640 = eq(_T_1639, UInt<1>(0h0))
when _T_1640 :
node _T_1641 = eq(_T_1638, UInt<1>(0h0))
when _T_1641 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1638, UInt<1>(0h1), "") : assert_87
node _T_1642 = eq(io.in.a.bits.param, param)
node _T_1643 = asUInt(reset)
node _T_1644 = eq(_T_1643, UInt<1>(0h0))
when _T_1644 :
node _T_1645 = eq(_T_1642, UInt<1>(0h0))
when _T_1645 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1642, UInt<1>(0h1), "") : assert_88
node _T_1646 = eq(io.in.a.bits.size, size)
node _T_1647 = asUInt(reset)
node _T_1648 = eq(_T_1647, UInt<1>(0h0))
when _T_1648 :
node _T_1649 = eq(_T_1646, UInt<1>(0h0))
when _T_1649 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1646, UInt<1>(0h1), "") : assert_89
node _T_1650 = eq(io.in.a.bits.source, source)
node _T_1651 = asUInt(reset)
node _T_1652 = eq(_T_1651, UInt<1>(0h0))
when _T_1652 :
node _T_1653 = eq(_T_1650, UInt<1>(0h0))
when _T_1653 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1650, UInt<1>(0h1), "") : assert_90
node _T_1654 = eq(io.in.a.bits.address, address)
node _T_1655 = asUInt(reset)
node _T_1656 = eq(_T_1655, UInt<1>(0h0))
when _T_1656 :
node _T_1657 = eq(_T_1654, UInt<1>(0h0))
when _T_1657 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1654, UInt<1>(0h1), "") : assert_91
node _T_1658 = and(io.in.a.ready, io.in.a.valid)
node _T_1659 = and(_T_1658, a_first)
when _T_1659 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1660 = eq(d_first, UInt<1>(0h0))
node _T_1661 = and(io.in.d.valid, _T_1660)
when _T_1661 :
node _T_1662 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1663 = asUInt(reset)
node _T_1664 = eq(_T_1663, UInt<1>(0h0))
when _T_1664 :
node _T_1665 = eq(_T_1662, UInt<1>(0h0))
when _T_1665 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1662, UInt<1>(0h1), "") : assert_92
node _T_1666 = eq(io.in.d.bits.param, param_1)
node _T_1667 = asUInt(reset)
node _T_1668 = eq(_T_1667, UInt<1>(0h0))
when _T_1668 :
node _T_1669 = eq(_T_1666, UInt<1>(0h0))
when _T_1669 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1666, UInt<1>(0h1), "") : assert_93
node _T_1670 = eq(io.in.d.bits.size, size_1)
node _T_1671 = asUInt(reset)
node _T_1672 = eq(_T_1671, UInt<1>(0h0))
when _T_1672 :
node _T_1673 = eq(_T_1670, UInt<1>(0h0))
when _T_1673 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1670, UInt<1>(0h1), "") : assert_94
node _T_1674 = eq(io.in.d.bits.source, source_1)
node _T_1675 = asUInt(reset)
node _T_1676 = eq(_T_1675, UInt<1>(0h0))
when _T_1676 :
node _T_1677 = eq(_T_1674, UInt<1>(0h0))
when _T_1677 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1674, UInt<1>(0h1), "") : assert_95
node _T_1678 = eq(io.in.d.bits.sink, sink)
node _T_1679 = asUInt(reset)
node _T_1680 = eq(_T_1679, UInt<1>(0h0))
when _T_1680 :
node _T_1681 = eq(_T_1678, UInt<1>(0h0))
when _T_1681 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1678, UInt<1>(0h1), "") : assert_96
node _T_1682 = eq(io.in.d.bits.denied, denied)
node _T_1683 = asUInt(reset)
node _T_1684 = eq(_T_1683, UInt<1>(0h0))
when _T_1684 :
node _T_1685 = eq(_T_1682, UInt<1>(0h0))
when _T_1685 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1682, UInt<1>(0h1), "") : assert_97
node _T_1686 = and(io.in.d.ready, io.in.d.valid)
node _T_1687 = and(_T_1686, d_first)
when _T_1687 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<65>
connect a_set, UInt<65>(0h0)
wire a_set_wo_ready : UInt<65>
connect a_set_wo_ready, UInt<65>(0h0)
wire a_opcodes_set : UInt<260>
connect a_opcodes_set, UInt<260>(0h0)
wire a_sizes_set : UInt<260>
connect a_sizes_set, UInt<260>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1688 = and(io.in.a.valid, a_first_1)
node _T_1689 = and(_T_1688, UInt<1>(0h1))
when _T_1689 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1690 = and(io.in.a.ready, io.in.a.valid)
node _T_1691 = and(_T_1690, a_first_1)
node _T_1692 = and(_T_1691, UInt<1>(0h1))
when _T_1692 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1693 = dshr(inflight, io.in.a.bits.source)
node _T_1694 = bits(_T_1693, 0, 0)
node _T_1695 = eq(_T_1694, UInt<1>(0h0))
node _T_1696 = asUInt(reset)
node _T_1697 = eq(_T_1696, UInt<1>(0h0))
when _T_1697 :
node _T_1698 = eq(_T_1695, UInt<1>(0h0))
when _T_1698 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1695, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<65>
connect d_clr, UInt<65>(0h0)
wire d_clr_wo_ready : UInt<65>
connect d_clr_wo_ready, UInt<65>(0h0)
wire d_opcodes_clr : UInt<260>
connect d_opcodes_clr, UInt<260>(0h0)
wire d_sizes_clr : UInt<260>
connect d_sizes_clr, UInt<260>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1699 = and(io.in.d.valid, d_first_1)
node _T_1700 = and(_T_1699, UInt<1>(0h1))
node _T_1701 = eq(d_release_ack, UInt<1>(0h0))
node _T_1702 = and(_T_1700, _T_1701)
when _T_1702 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1703 = and(io.in.d.ready, io.in.d.valid)
node _T_1704 = and(_T_1703, d_first_1)
node _T_1705 = and(_T_1704, UInt<1>(0h1))
node _T_1706 = eq(d_release_ack, UInt<1>(0h0))
node _T_1707 = and(_T_1705, _T_1706)
when _T_1707 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1708 = and(io.in.d.valid, d_first_1)
node _T_1709 = and(_T_1708, UInt<1>(0h1))
node _T_1710 = eq(d_release_ack, UInt<1>(0h0))
node _T_1711 = and(_T_1709, _T_1710)
when _T_1711 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1712 = dshr(inflight, io.in.d.bits.source)
node _T_1713 = bits(_T_1712, 0, 0)
node _T_1714 = or(_T_1713, same_cycle_resp)
node _T_1715 = asUInt(reset)
node _T_1716 = eq(_T_1715, UInt<1>(0h0))
when _T_1716 :
node _T_1717 = eq(_T_1714, UInt<1>(0h0))
when _T_1717 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1714, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1718 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1719 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1720 = or(_T_1718, _T_1719)
node _T_1721 = asUInt(reset)
node _T_1722 = eq(_T_1721, UInt<1>(0h0))
when _T_1722 :
node _T_1723 = eq(_T_1720, UInt<1>(0h0))
when _T_1723 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1720, UInt<1>(0h1), "") : assert_100
node _T_1724 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1725 = asUInt(reset)
node _T_1726 = eq(_T_1725, UInt<1>(0h0))
when _T_1726 :
node _T_1727 = eq(_T_1724, UInt<1>(0h0))
when _T_1727 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1724, UInt<1>(0h1), "") : assert_101
else :
node _T_1728 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1729 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1730 = or(_T_1728, _T_1729)
node _T_1731 = asUInt(reset)
node _T_1732 = eq(_T_1731, UInt<1>(0h0))
when _T_1732 :
node _T_1733 = eq(_T_1730, UInt<1>(0h0))
when _T_1733 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1730, UInt<1>(0h1), "") : assert_102
node _T_1734 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1735 = asUInt(reset)
node _T_1736 = eq(_T_1735, UInt<1>(0h0))
when _T_1736 :
node _T_1737 = eq(_T_1734, UInt<1>(0h0))
when _T_1737 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1734, UInt<1>(0h1), "") : assert_103
node _T_1738 = and(io.in.d.valid, d_first_1)
node _T_1739 = and(_T_1738, a_first_1)
node _T_1740 = and(_T_1739, io.in.a.valid)
node _T_1741 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1742 = and(_T_1740, _T_1741)
node _T_1743 = eq(d_release_ack, UInt<1>(0h0))
node _T_1744 = and(_T_1742, _T_1743)
when _T_1744 :
node _T_1745 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1746 = or(_T_1745, io.in.a.ready)
node _T_1747 = asUInt(reset)
node _T_1748 = eq(_T_1747, UInt<1>(0h0))
when _T_1748 :
node _T_1749 = eq(_T_1746, UInt<1>(0h0))
when _T_1749 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1746, UInt<1>(0h1), "") : assert_104
node _T_1750 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1751 = orr(a_set_wo_ready)
node _T_1752 = eq(_T_1751, UInt<1>(0h0))
node _T_1753 = or(_T_1750, _T_1752)
node _T_1754 = asUInt(reset)
node _T_1755 = eq(_T_1754, UInt<1>(0h0))
when _T_1755 :
node _T_1756 = eq(_T_1753, UInt<1>(0h0))
when _T_1756 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1753, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_88
node _T_1757 = orr(inflight)
node _T_1758 = eq(_T_1757, UInt<1>(0h0))
node _T_1759 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1760 = or(_T_1758, _T_1759)
node _T_1761 = lt(watchdog, plusarg_reader.out)
node _T_1762 = or(_T_1760, _T_1761)
node _T_1763 = asUInt(reset)
node _T_1764 = eq(_T_1763, UInt<1>(0h0))
when _T_1764 :
node _T_1765 = eq(_T_1762, UInt<1>(0h0))
when _T_1765 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1762, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1766 = and(io.in.a.ready, io.in.a.valid)
node _T_1767 = and(io.in.d.ready, io.in.d.valid)
node _T_1768 = or(_T_1766, _T_1767)
when _T_1768 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<28>(0h0)
connect _c_first_WIRE.bits.source, UInt<7>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<65>
connect c_set, UInt<65>(0h0)
wire c_set_wo_ready : UInt<65>
connect c_set_wo_ready, UInt<65>(0h0)
wire c_opcodes_set : UInt<260>
connect c_opcodes_set, UInt<260>(0h0)
wire c_sizes_set : UInt<260>
connect c_sizes_set, UInt<260>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<28>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1769 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<28>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1770 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1771 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1772 = and(_T_1770, _T_1771)
node _T_1773 = and(_T_1769, _T_1772)
when _T_1773 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<28>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1774 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1775 = and(_T_1774, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<28>(0h0)
connect _WIRE_16.bits.source, UInt<7>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1776 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1777 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1778 = and(_T_1776, _T_1777)
node _T_1779 = and(_T_1775, _T_1778)
when _T_1779 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<28>(0h0)
connect _WIRE_18.bits.source, UInt<7>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1780 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1781 = bits(_T_1780, 0, 0)
node _T_1782 = eq(_T_1781, UInt<1>(0h0))
node _T_1783 = asUInt(reset)
node _T_1784 = eq(_T_1783, UInt<1>(0h0))
when _T_1784 :
node _T_1785 = eq(_T_1782, UInt<1>(0h0))
when _T_1785 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1782, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<65>
connect d_clr_1, UInt<65>(0h0)
wire d_clr_wo_ready_1 : UInt<65>
connect d_clr_wo_ready_1, UInt<65>(0h0)
wire d_opcodes_clr_1 : UInt<260>
connect d_opcodes_clr_1, UInt<260>(0h0)
wire d_sizes_clr_1 : UInt<260>
connect d_sizes_clr_1, UInt<260>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1786 = and(io.in.d.valid, d_first_2)
node _T_1787 = and(_T_1786, UInt<1>(0h1))
node _T_1788 = and(_T_1787, d_release_ack_1)
when _T_1788 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1789 = and(io.in.d.ready, io.in.d.valid)
node _T_1790 = and(_T_1789, d_first_2)
node _T_1791 = and(_T_1790, UInt<1>(0h1))
node _T_1792 = and(_T_1791, d_release_ack_1)
when _T_1792 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1793 = and(io.in.d.valid, d_first_2)
node _T_1794 = and(_T_1793, UInt<1>(0h1))
node _T_1795 = and(_T_1794, d_release_ack_1)
when _T_1795 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1796 = dshr(inflight_1, io.in.d.bits.source)
node _T_1797 = bits(_T_1796, 0, 0)
node _T_1798 = or(_T_1797, same_cycle_resp_1)
node _T_1799 = asUInt(reset)
node _T_1800 = eq(_T_1799, UInt<1>(0h0))
when _T_1800 :
node _T_1801 = eq(_T_1798, UInt<1>(0h0))
when _T_1801 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1798, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<28>(0h0)
connect _WIRE_20.bits.source, UInt<7>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1802 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1803 = asUInt(reset)
node _T_1804 = eq(_T_1803, UInt<1>(0h0))
when _T_1804 :
node _T_1805 = eq(_T_1802, UInt<1>(0h0))
when _T_1805 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1802, UInt<1>(0h1), "") : assert_109
else :
node _T_1806 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1807 = asUInt(reset)
node _T_1808 = eq(_T_1807, UInt<1>(0h0))
when _T_1808 :
node _T_1809 = eq(_T_1806, UInt<1>(0h0))
when _T_1809 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1806, UInt<1>(0h1), "") : assert_110
node _T_1810 = and(io.in.d.valid, d_first_2)
node _T_1811 = and(_T_1810, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<28>(0h0)
connect _WIRE_22.bits.source, UInt<7>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1812 = and(_T_1811, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<28>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1813 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1814 = and(_T_1812, _T_1813)
node _T_1815 = and(_T_1814, d_release_ack_1)
node _T_1816 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1817 = and(_T_1815, _T_1816)
when _T_1817 :
node _T_1818 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<28>(0h0)
connect _WIRE_26.bits.source, UInt<7>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1819 = or(_T_1818, _WIRE_27.ready)
node _T_1820 = asUInt(reset)
node _T_1821 = eq(_T_1820, UInt<1>(0h0))
when _T_1821 :
node _T_1822 = eq(_T_1819, UInt<1>(0h0))
when _T_1822 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1819, UInt<1>(0h1), "") : assert_111
node _T_1823 = orr(c_set_wo_ready)
when _T_1823 :
node _T_1824 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1825 = asUInt(reset)
node _T_1826 = eq(_T_1825, UInt<1>(0h0))
when _T_1826 :
node _T_1827 = eq(_T_1824, UInt<1>(0h0))
when _T_1827 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1824, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_89
node _T_1828 = orr(inflight_1)
node _T_1829 = eq(_T_1828, UInt<1>(0h0))
node _T_1830 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1831 = or(_T_1829, _T_1830)
node _T_1832 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1833 = or(_T_1831, _T_1832)
node _T_1834 = asUInt(reset)
node _T_1835 = eq(_T_1834, UInt<1>(0h0))
when _T_1835 :
node _T_1836 = eq(_T_1833, UInt<1>(0h0))
when _T_1836 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1833, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<28>(0h0)
connect _WIRE_28.bits.source, UInt<7>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1837 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1838 = and(io.in.d.ready, io.in.d.valid)
node _T_1839 = or(_T_1837, _T_1838)
when _T_1839 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_31( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [27:0] address; // @[Monitor.scala:391:22]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire [127:0] _GEN_0 = {121'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [127:0] _GEN_3 = {121'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_30 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<1>(0h0))
node mask_sizeOH = or(UInt<1>(0h1), UInt<1>(0h1))
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_15 :
node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_18 = and(_T_16, _T_17)
node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_20 = and(_T_18, _T_19)
node _T_21 = or(UInt<1>(0h0), _T_20)
node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_24 = cvt(_T_23)
node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000)))
node _T_26 = asSInt(_T_25)
node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0)))
node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_29 = cvt(_T_28)
node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000)))
node _T_31 = asSInt(_T_30)
node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0)))
node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_39 = cvt(_T_38)
node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000)))
node _T_41 = asSInt(_T_40)
node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0)))
node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_44 = cvt(_T_43)
node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000)))
node _T_46 = asSInt(_T_45)
node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_54 = cvt(_T_53)
node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000)))
node _T_56 = asSInt(_T_55)
node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0)))
node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_27, _T_32)
node _T_64 = or(_T_63, _T_37)
node _T_65 = or(_T_64, _T_42)
node _T_66 = or(_T_65, _T_47)
node _T_67 = or(_T_66, _T_52)
node _T_68 = or(_T_67, _T_57)
node _T_69 = or(_T_68, _T_62)
node _T_70 = and(_T_22, _T_69)
node _T_71 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_72 = or(UInt<1>(0h0), _T_71)
node _T_73 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_74 = cvt(_T_73)
node _T_75 = and(_T_74, asSInt(UInt<17>(0h10000)))
node _T_76 = asSInt(_T_75)
node _T_77 = eq(_T_76, asSInt(UInt<1>(0h0)))
node _T_78 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_79 = cvt(_T_78)
node _T_80 = and(_T_79, asSInt(UInt<29>(0h10000000)))
node _T_81 = asSInt(_T_80)
node _T_82 = eq(_T_81, asSInt(UInt<1>(0h0)))
node _T_83 = or(_T_77, _T_82)
node _T_84 = and(_T_72, _T_83)
node _T_85 = or(UInt<1>(0h0), _T_70)
node _T_86 = or(_T_85, _T_84)
node _T_87 = and(_T_21, _T_86)
node _T_88 = asUInt(reset)
node _T_89 = eq(_T_88, UInt<1>(0h0))
when _T_89 :
node _T_90 = eq(_T_87, UInt<1>(0h0))
when _T_90 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_87, UInt<1>(0h1), "") : assert_2
node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_93 = and(_T_91, _T_92)
node _T_94 = or(UInt<1>(0h0), _T_93)
node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<14>(0h2000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_101 = cvt(_T_100)
node _T_102 = and(_T_101, asSInt(UInt<13>(0h1000)))
node _T_103 = asSInt(_T_102)
node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0)))
node _T_105 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_106 = cvt(_T_105)
node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000)))
node _T_108 = asSInt(_T_107)
node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0)))
node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<18>(0h2f000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_116 = cvt(_T_115)
node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000)))
node _T_118 = asSInt(_T_117)
node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0)))
node _T_120 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_121 = cvt(_T_120)
node _T_122 = and(_T_121, asSInt(UInt<13>(0h1000)))
node _T_123 = asSInt(_T_122)
node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0)))
node _T_125 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_126 = cvt(_T_125)
node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000)))
node _T_128 = asSInt(_T_127)
node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0)))
node _T_130 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_131 = cvt(_T_130)
node _T_132 = and(_T_131, asSInt(UInt<27>(0h4000000)))
node _T_133 = asSInt(_T_132)
node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0)))
node _T_135 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_136 = cvt(_T_135)
node _T_137 = and(_T_136, asSInt(UInt<13>(0h1000)))
node _T_138 = asSInt(_T_137)
node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0)))
node _T_140 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_141 = cvt(_T_140)
node _T_142 = and(_T_141, asSInt(UInt<29>(0h10000000)))
node _T_143 = asSInt(_T_142)
node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0)))
node _T_145 = or(_T_99, _T_104)
node _T_146 = or(_T_145, _T_109)
node _T_147 = or(_T_146, _T_114)
node _T_148 = or(_T_147, _T_119)
node _T_149 = or(_T_148, _T_124)
node _T_150 = or(_T_149, _T_129)
node _T_151 = or(_T_150, _T_134)
node _T_152 = or(_T_151, _T_139)
node _T_153 = or(_T_152, _T_144)
node _T_154 = and(_T_94, _T_153)
node _T_155 = or(UInt<1>(0h0), _T_154)
node _T_156 = and(UInt<1>(0h0), _T_155)
node _T_157 = asUInt(reset)
node _T_158 = eq(_T_157, UInt<1>(0h0))
when _T_158 :
node _T_159 = eq(_T_156, UInt<1>(0h0))
when _T_159 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_156, UInt<1>(0h1), "") : assert_3
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_163 = geq(io.in.a.bits.size, UInt<1>(0h0))
node _T_164 = asUInt(reset)
node _T_165 = eq(_T_164, UInt<1>(0h0))
when _T_165 :
node _T_166 = eq(_T_163, UInt<1>(0h0))
when _T_166 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_163, UInt<1>(0h1), "") : assert_5
node _T_167 = asUInt(reset)
node _T_168 = eq(_T_167, UInt<1>(0h0))
when _T_168 :
node _T_169 = eq(is_aligned, UInt<1>(0h0))
when _T_169 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_170 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_171 = asUInt(reset)
node _T_172 = eq(_T_171, UInt<1>(0h0))
when _T_172 :
node _T_173 = eq(_T_170, UInt<1>(0h0))
when _T_173 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_170, UInt<1>(0h1), "") : assert_7
node _T_174 = not(io.in.a.bits.mask)
node _T_175 = eq(_T_174, UInt<1>(0h0))
node _T_176 = asUInt(reset)
node _T_177 = eq(_T_176, UInt<1>(0h0))
when _T_177 :
node _T_178 = eq(_T_175, UInt<1>(0h0))
when _T_178 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_175, UInt<1>(0h1), "") : assert_8
node _T_179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(_T_179, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_179, UInt<1>(0h1), "") : assert_9
node _T_183 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_183 :
node _T_184 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_185 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_186 = and(_T_184, _T_185)
node _T_187 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_188 = and(_T_186, _T_187)
node _T_189 = or(UInt<1>(0h0), _T_188)
node _T_190 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_191 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_192 = cvt(_T_191)
node _T_193 = and(_T_192, asSInt(UInt<14>(0h2000)))
node _T_194 = asSInt(_T_193)
node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0)))
node _T_196 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_197 = cvt(_T_196)
node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000)))
node _T_199 = asSInt(_T_198)
node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0)))
node _T_201 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_202 = cvt(_T_201)
node _T_203 = and(_T_202, asSInt(UInt<17>(0h10000)))
node _T_204 = asSInt(_T_203)
node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0)))
node _T_206 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_207 = cvt(_T_206)
node _T_208 = and(_T_207, asSInt(UInt<18>(0h2f000)))
node _T_209 = asSInt(_T_208)
node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0)))
node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_217 = cvt(_T_216)
node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000)))
node _T_219 = asSInt(_T_218)
node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0)))
node _T_221 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_222 = cvt(_T_221)
node _T_223 = and(_T_222, asSInt(UInt<27>(0h4000000)))
node _T_224 = asSInt(_T_223)
node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0)))
node _T_226 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_227 = cvt(_T_226)
node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000)))
node _T_229 = asSInt(_T_228)
node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0)))
node _T_231 = or(_T_195, _T_200)
node _T_232 = or(_T_231, _T_205)
node _T_233 = or(_T_232, _T_210)
node _T_234 = or(_T_233, _T_215)
node _T_235 = or(_T_234, _T_220)
node _T_236 = or(_T_235, _T_225)
node _T_237 = or(_T_236, _T_230)
node _T_238 = and(_T_190, _T_237)
node _T_239 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_240 = or(UInt<1>(0h0), _T_239)
node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_242 = cvt(_T_241)
node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000)))
node _T_244 = asSInt(_T_243)
node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0)))
node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_247 = cvt(_T_246)
node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000)))
node _T_249 = asSInt(_T_248)
node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0)))
node _T_251 = or(_T_245, _T_250)
node _T_252 = and(_T_240, _T_251)
node _T_253 = or(UInt<1>(0h0), _T_238)
node _T_254 = or(_T_253, _T_252)
node _T_255 = and(_T_189, _T_254)
node _T_256 = asUInt(reset)
node _T_257 = eq(_T_256, UInt<1>(0h0))
when _T_257 :
node _T_258 = eq(_T_255, UInt<1>(0h0))
when _T_258 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_255, UInt<1>(0h1), "") : assert_10
node _T_259 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_260 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_261 = and(_T_259, _T_260)
node _T_262 = or(UInt<1>(0h0), _T_261)
node _T_263 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_264 = cvt(_T_263)
node _T_265 = and(_T_264, asSInt(UInt<14>(0h2000)))
node _T_266 = asSInt(_T_265)
node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0)))
node _T_268 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_269 = cvt(_T_268)
node _T_270 = and(_T_269, asSInt(UInt<13>(0h1000)))
node _T_271 = asSInt(_T_270)
node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0)))
node _T_273 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_274 = cvt(_T_273)
node _T_275 = and(_T_274, asSInt(UInt<17>(0h10000)))
node _T_276 = asSInt(_T_275)
node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0)))
node _T_278 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_279 = cvt(_T_278)
node _T_280 = and(_T_279, asSInt(UInt<18>(0h2f000)))
node _T_281 = asSInt(_T_280)
node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0)))
node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_284 = cvt(_T_283)
node _T_285 = and(_T_284, asSInt(UInt<17>(0h10000)))
node _T_286 = asSInt(_T_285)
node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0)))
node _T_288 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_289 = cvt(_T_288)
node _T_290 = and(_T_289, asSInt(UInt<13>(0h1000)))
node _T_291 = asSInt(_T_290)
node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0)))
node _T_293 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_294 = cvt(_T_293)
node _T_295 = and(_T_294, asSInt(UInt<17>(0h10000)))
node _T_296 = asSInt(_T_295)
node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0)))
node _T_298 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_299 = cvt(_T_298)
node _T_300 = and(_T_299, asSInt(UInt<27>(0h4000000)))
node _T_301 = asSInt(_T_300)
node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0)))
node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_304 = cvt(_T_303)
node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000)))
node _T_306 = asSInt(_T_305)
node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0)))
node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_309 = cvt(_T_308)
node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000)))
node _T_311 = asSInt(_T_310)
node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0)))
node _T_313 = or(_T_267, _T_272)
node _T_314 = or(_T_313, _T_277)
node _T_315 = or(_T_314, _T_282)
node _T_316 = or(_T_315, _T_287)
node _T_317 = or(_T_316, _T_292)
node _T_318 = or(_T_317, _T_297)
node _T_319 = or(_T_318, _T_302)
node _T_320 = or(_T_319, _T_307)
node _T_321 = or(_T_320, _T_312)
node _T_322 = and(_T_262, _T_321)
node _T_323 = or(UInt<1>(0h0), _T_322)
node _T_324 = and(UInt<1>(0h0), _T_323)
node _T_325 = asUInt(reset)
node _T_326 = eq(_T_325, UInt<1>(0h0))
when _T_326 :
node _T_327 = eq(_T_324, UInt<1>(0h0))
when _T_327 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_324, UInt<1>(0h1), "") : assert_11
node _T_328 = asUInt(reset)
node _T_329 = eq(_T_328, UInt<1>(0h0))
when _T_329 :
node _T_330 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_330 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_331 = geq(io.in.a.bits.size, UInt<1>(0h0))
node _T_332 = asUInt(reset)
node _T_333 = eq(_T_332, UInt<1>(0h0))
when _T_333 :
node _T_334 = eq(_T_331, UInt<1>(0h0))
when _T_334 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_331, UInt<1>(0h1), "") : assert_13
node _T_335 = asUInt(reset)
node _T_336 = eq(_T_335, UInt<1>(0h0))
when _T_336 :
node _T_337 = eq(is_aligned, UInt<1>(0h0))
when _T_337 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_338 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_339 = asUInt(reset)
node _T_340 = eq(_T_339, UInt<1>(0h0))
when _T_340 :
node _T_341 = eq(_T_338, UInt<1>(0h0))
when _T_341 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_338, UInt<1>(0h1), "") : assert_15
node _T_342 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_343 = asUInt(reset)
node _T_344 = eq(_T_343, UInt<1>(0h0))
when _T_344 :
node _T_345 = eq(_T_342, UInt<1>(0h0))
when _T_345 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_342, UInt<1>(0h1), "") : assert_16
node _T_346 = not(io.in.a.bits.mask)
node _T_347 = eq(_T_346, UInt<1>(0h0))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_347, UInt<1>(0h1), "") : assert_17
node _T_351 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_351, UInt<1>(0h1), "") : assert_18
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _T_359 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_360 = and(_T_358, _T_359)
node _T_361 = or(UInt<1>(0h0), _T_360)
node _T_362 = asUInt(reset)
node _T_363 = eq(_T_362, UInt<1>(0h0))
when _T_363 :
node _T_364 = eq(_T_361, UInt<1>(0h0))
when _T_364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_361, UInt<1>(0h1), "") : assert_19
node _T_365 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_366 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_367 = and(_T_365, _T_366)
node _T_368 = or(UInt<1>(0h0), _T_367)
node _T_369 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_370 = cvt(_T_369)
node _T_371 = and(_T_370, asSInt(UInt<13>(0h1000)))
node _T_372 = asSInt(_T_371)
node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0)))
node _T_374 = and(_T_368, _T_373)
node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_376 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_377 = and(_T_375, _T_376)
node _T_378 = or(UInt<1>(0h0), _T_377)
node _T_379 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_380 = cvt(_T_379)
node _T_381 = and(_T_380, asSInt(UInt<14>(0h2000)))
node _T_382 = asSInt(_T_381)
node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0)))
node _T_384 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_385 = cvt(_T_384)
node _T_386 = and(_T_385, asSInt(UInt<17>(0h10000)))
node _T_387 = asSInt(_T_386)
node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0)))
node _T_389 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_390 = cvt(_T_389)
node _T_391 = and(_T_390, asSInt(UInt<18>(0h2f000)))
node _T_392 = asSInt(_T_391)
node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0)))
node _T_394 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_395 = cvt(_T_394)
node _T_396 = and(_T_395, asSInt(UInt<17>(0h10000)))
node _T_397 = asSInt(_T_396)
node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0)))
node _T_399 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_400 = cvt(_T_399)
node _T_401 = and(_T_400, asSInt(UInt<13>(0h1000)))
node _T_402 = asSInt(_T_401)
node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0)))
node _T_404 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_405 = cvt(_T_404)
node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000)))
node _T_407 = asSInt(_T_406)
node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0)))
node _T_409 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_410 = cvt(_T_409)
node _T_411 = and(_T_410, asSInt(UInt<27>(0h4000000)))
node _T_412 = asSInt(_T_411)
node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0)))
node _T_414 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_415 = cvt(_T_414)
node _T_416 = and(_T_415, asSInt(UInt<13>(0h1000)))
node _T_417 = asSInt(_T_416)
node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0)))
node _T_419 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_420 = cvt(_T_419)
node _T_421 = and(_T_420, asSInt(UInt<29>(0h10000000)))
node _T_422 = asSInt(_T_421)
node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0)))
node _T_424 = or(_T_383, _T_388)
node _T_425 = or(_T_424, _T_393)
node _T_426 = or(_T_425, _T_398)
node _T_427 = or(_T_426, _T_403)
node _T_428 = or(_T_427, _T_408)
node _T_429 = or(_T_428, _T_413)
node _T_430 = or(_T_429, _T_418)
node _T_431 = or(_T_430, _T_423)
node _T_432 = and(_T_378, _T_431)
node _T_433 = or(UInt<1>(0h0), _T_374)
node _T_434 = or(_T_433, _T_432)
node _T_435 = asUInt(reset)
node _T_436 = eq(_T_435, UInt<1>(0h0))
when _T_436 :
node _T_437 = eq(_T_434, UInt<1>(0h0))
when _T_437 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_434, UInt<1>(0h1), "") : assert_20
node _T_438 = asUInt(reset)
node _T_439 = eq(_T_438, UInt<1>(0h0))
when _T_439 :
node _T_440 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_440 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(is_aligned, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_444 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_445 = asUInt(reset)
node _T_446 = eq(_T_445, UInt<1>(0h0))
when _T_446 :
node _T_447 = eq(_T_444, UInt<1>(0h0))
when _T_447 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_444, UInt<1>(0h1), "") : assert_23
node _T_448 = eq(io.in.a.bits.mask, UInt<1>(0h1))
node _T_449 = asUInt(reset)
node _T_450 = eq(_T_449, UInt<1>(0h0))
when _T_450 :
node _T_451 = eq(_T_448, UInt<1>(0h0))
when _T_451 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_448, UInt<1>(0h1), "") : assert_24
node _T_452 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(_T_452, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_452, UInt<1>(0h1), "") : assert_25
node _T_456 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_456 :
node _T_457 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_458 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_459 = and(_T_457, _T_458)
node _T_460 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_461 = and(_T_459, _T_460)
node _T_462 = or(UInt<1>(0h0), _T_461)
node _T_463 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_464 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_465 = and(_T_463, _T_464)
node _T_466 = or(UInt<1>(0h0), _T_465)
node _T_467 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_468 = cvt(_T_467)
node _T_469 = and(_T_468, asSInt(UInt<13>(0h1000)))
node _T_470 = asSInt(_T_469)
node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0)))
node _T_472 = and(_T_466, _T_471)
node _T_473 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_474 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_475 = and(_T_473, _T_474)
node _T_476 = or(UInt<1>(0h0), _T_475)
node _T_477 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_478 = cvt(_T_477)
node _T_479 = and(_T_478, asSInt(UInt<14>(0h2000)))
node _T_480 = asSInt(_T_479)
node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0)))
node _T_482 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_483 = cvt(_T_482)
node _T_484 = and(_T_483, asSInt(UInt<18>(0h2f000)))
node _T_485 = asSInt(_T_484)
node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0)))
node _T_487 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_488 = cvt(_T_487)
node _T_489 = and(_T_488, asSInt(UInt<17>(0h10000)))
node _T_490 = asSInt(_T_489)
node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0)))
node _T_492 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_493 = cvt(_T_492)
node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000)))
node _T_495 = asSInt(_T_494)
node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0)))
node _T_497 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_498 = cvt(_T_497)
node _T_499 = and(_T_498, asSInt(UInt<17>(0h10000)))
node _T_500 = asSInt(_T_499)
node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0)))
node _T_502 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_503 = cvt(_T_502)
node _T_504 = and(_T_503, asSInt(UInt<27>(0h4000000)))
node _T_505 = asSInt(_T_504)
node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0)))
node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_508 = cvt(_T_507)
node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000)))
node _T_510 = asSInt(_T_509)
node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0)))
node _T_512 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_513 = cvt(_T_512)
node _T_514 = and(_T_513, asSInt(UInt<29>(0h10000000)))
node _T_515 = asSInt(_T_514)
node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0)))
node _T_517 = or(_T_481, _T_486)
node _T_518 = or(_T_517, _T_491)
node _T_519 = or(_T_518, _T_496)
node _T_520 = or(_T_519, _T_501)
node _T_521 = or(_T_520, _T_506)
node _T_522 = or(_T_521, _T_511)
node _T_523 = or(_T_522, _T_516)
node _T_524 = and(_T_476, _T_523)
node _T_525 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_526 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_527 = cvt(_T_526)
node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000)))
node _T_529 = asSInt(_T_528)
node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0)))
node _T_531 = and(_T_525, _T_530)
node _T_532 = or(UInt<1>(0h0), _T_472)
node _T_533 = or(_T_532, _T_524)
node _T_534 = or(_T_533, _T_531)
node _T_535 = and(_T_462, _T_534)
node _T_536 = asUInt(reset)
node _T_537 = eq(_T_536, UInt<1>(0h0))
when _T_537 :
node _T_538 = eq(_T_535, UInt<1>(0h0))
when _T_538 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_535, UInt<1>(0h1), "") : assert_26
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_542 = asUInt(reset)
node _T_543 = eq(_T_542, UInt<1>(0h0))
when _T_543 :
node _T_544 = eq(is_aligned, UInt<1>(0h0))
when _T_544 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_545 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_546 = asUInt(reset)
node _T_547 = eq(_T_546, UInt<1>(0h0))
when _T_547 :
node _T_548 = eq(_T_545, UInt<1>(0h0))
when _T_548 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_545, UInt<1>(0h1), "") : assert_29
node _T_549 = eq(io.in.a.bits.mask, UInt<1>(0h1))
node _T_550 = asUInt(reset)
node _T_551 = eq(_T_550, UInt<1>(0h0))
when _T_551 :
node _T_552 = eq(_T_549, UInt<1>(0h0))
when _T_552 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_549, UInt<1>(0h1), "") : assert_30
node _T_553 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_553 :
node _T_554 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_555 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_556 = and(_T_554, _T_555)
node _T_557 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_558 = and(_T_556, _T_557)
node _T_559 = or(UInt<1>(0h0), _T_558)
node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_562 = and(_T_560, _T_561)
node _T_563 = or(UInt<1>(0h0), _T_562)
node _T_564 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_565 = cvt(_T_564)
node _T_566 = and(_T_565, asSInt(UInt<13>(0h1000)))
node _T_567 = asSInt(_T_566)
node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0)))
node _T_569 = and(_T_563, _T_568)
node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_572 = and(_T_570, _T_571)
node _T_573 = or(UInt<1>(0h0), _T_572)
node _T_574 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_575 = cvt(_T_574)
node _T_576 = and(_T_575, asSInt(UInt<14>(0h2000)))
node _T_577 = asSInt(_T_576)
node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0)))
node _T_579 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_580 = cvt(_T_579)
node _T_581 = and(_T_580, asSInt(UInt<18>(0h2f000)))
node _T_582 = asSInt(_T_581)
node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0)))
node _T_584 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_585 = cvt(_T_584)
node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000)))
node _T_587 = asSInt(_T_586)
node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0)))
node _T_589 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_590 = cvt(_T_589)
node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000)))
node _T_592 = asSInt(_T_591)
node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0)))
node _T_594 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_595 = cvt(_T_594)
node _T_596 = and(_T_595, asSInt(UInt<17>(0h10000)))
node _T_597 = asSInt(_T_596)
node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0)))
node _T_599 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_600 = cvt(_T_599)
node _T_601 = and(_T_600, asSInt(UInt<27>(0h4000000)))
node _T_602 = asSInt(_T_601)
node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0)))
node _T_604 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_605 = cvt(_T_604)
node _T_606 = and(_T_605, asSInt(UInt<13>(0h1000)))
node _T_607 = asSInt(_T_606)
node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0)))
node _T_609 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_610 = cvt(_T_609)
node _T_611 = and(_T_610, asSInt(UInt<29>(0h10000000)))
node _T_612 = asSInt(_T_611)
node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0)))
node _T_614 = or(_T_578, _T_583)
node _T_615 = or(_T_614, _T_588)
node _T_616 = or(_T_615, _T_593)
node _T_617 = or(_T_616, _T_598)
node _T_618 = or(_T_617, _T_603)
node _T_619 = or(_T_618, _T_608)
node _T_620 = or(_T_619, _T_613)
node _T_621 = and(_T_573, _T_620)
node _T_622 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_623 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_624 = cvt(_T_623)
node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000)))
node _T_626 = asSInt(_T_625)
node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0)))
node _T_628 = and(_T_622, _T_627)
node _T_629 = or(UInt<1>(0h0), _T_569)
node _T_630 = or(_T_629, _T_621)
node _T_631 = or(_T_630, _T_628)
node _T_632 = and(_T_559, _T_631)
node _T_633 = asUInt(reset)
node _T_634 = eq(_T_633, UInt<1>(0h0))
when _T_634 :
node _T_635 = eq(_T_632, UInt<1>(0h0))
when _T_635 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_632, UInt<1>(0h1), "") : assert_31
node _T_636 = asUInt(reset)
node _T_637 = eq(_T_636, UInt<1>(0h0))
when _T_637 :
node _T_638 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_638 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_639 = asUInt(reset)
node _T_640 = eq(_T_639, UInt<1>(0h0))
when _T_640 :
node _T_641 = eq(is_aligned, UInt<1>(0h0))
when _T_641 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_642 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_643 = asUInt(reset)
node _T_644 = eq(_T_643, UInt<1>(0h0))
when _T_644 :
node _T_645 = eq(_T_642, UInt<1>(0h0))
when _T_645 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_642, UInt<1>(0h1), "") : assert_34
node _T_646 = not(UInt<1>(0h1))
node _T_647 = and(io.in.a.bits.mask, _T_646)
node _T_648 = eq(_T_647, UInt<1>(0h0))
node _T_649 = asUInt(reset)
node _T_650 = eq(_T_649, UInt<1>(0h0))
when _T_650 :
node _T_651 = eq(_T_648, UInt<1>(0h0))
when _T_651 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_648, UInt<1>(0h1), "") : assert_35
node _T_652 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_652 :
node _T_653 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_654 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_655 = and(_T_653, _T_654)
node _T_656 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_657 = and(_T_655, _T_656)
node _T_658 = or(UInt<1>(0h0), _T_657)
node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_660 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_661 = and(_T_659, _T_660)
node _T_662 = or(UInt<1>(0h0), _T_661)
node _T_663 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_664 = cvt(_T_663)
node _T_665 = and(_T_664, asSInt(UInt<14>(0h2000)))
node _T_666 = asSInt(_T_665)
node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0)))
node _T_668 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_669 = cvt(_T_668)
node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000)))
node _T_671 = asSInt(_T_670)
node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0)))
node _T_673 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_674 = cvt(_T_673)
node _T_675 = and(_T_674, asSInt(UInt<18>(0h2f000)))
node _T_676 = asSInt(_T_675)
node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0)))
node _T_678 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_679 = cvt(_T_678)
node _T_680 = and(_T_679, asSInt(UInt<17>(0h10000)))
node _T_681 = asSInt(_T_680)
node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0)))
node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_684 = cvt(_T_683)
node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000)))
node _T_686 = asSInt(_T_685)
node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0)))
node _T_688 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_689 = cvt(_T_688)
node _T_690 = and(_T_689, asSInt(UInt<17>(0h10000)))
node _T_691 = asSInt(_T_690)
node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0)))
node _T_693 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_694 = cvt(_T_693)
node _T_695 = and(_T_694, asSInt(UInt<27>(0h4000000)))
node _T_696 = asSInt(_T_695)
node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0)))
node _T_698 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_699 = cvt(_T_698)
node _T_700 = and(_T_699, asSInt(UInt<13>(0h1000)))
node _T_701 = asSInt(_T_700)
node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0)))
node _T_703 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_704 = cvt(_T_703)
node _T_705 = and(_T_704, asSInt(UInt<29>(0h10000000)))
node _T_706 = asSInt(_T_705)
node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0)))
node _T_708 = or(_T_667, _T_672)
node _T_709 = or(_T_708, _T_677)
node _T_710 = or(_T_709, _T_682)
node _T_711 = or(_T_710, _T_687)
node _T_712 = or(_T_711, _T_692)
node _T_713 = or(_T_712, _T_697)
node _T_714 = or(_T_713, _T_702)
node _T_715 = or(_T_714, _T_707)
node _T_716 = and(_T_662, _T_715)
node _T_717 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_718 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_719 = cvt(_T_718)
node _T_720 = and(_T_719, asSInt(UInt<17>(0h10000)))
node _T_721 = asSInt(_T_720)
node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0)))
node _T_723 = and(_T_717, _T_722)
node _T_724 = or(UInt<1>(0h0), _T_716)
node _T_725 = or(_T_724, _T_723)
node _T_726 = and(_T_658, _T_725)
node _T_727 = asUInt(reset)
node _T_728 = eq(_T_727, UInt<1>(0h0))
when _T_728 :
node _T_729 = eq(_T_726, UInt<1>(0h0))
when _T_729 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_726, UInt<1>(0h1), "") : assert_36
node _T_730 = asUInt(reset)
node _T_731 = eq(_T_730, UInt<1>(0h0))
when _T_731 :
node _T_732 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_732 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_733 = asUInt(reset)
node _T_734 = eq(_T_733, UInt<1>(0h0))
when _T_734 :
node _T_735 = eq(is_aligned, UInt<1>(0h0))
when _T_735 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_736 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_737 = asUInt(reset)
node _T_738 = eq(_T_737, UInt<1>(0h0))
when _T_738 :
node _T_739 = eq(_T_736, UInt<1>(0h0))
when _T_739 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_736, UInt<1>(0h1), "") : assert_39
node _T_740 = eq(io.in.a.bits.mask, UInt<1>(0h1))
node _T_741 = asUInt(reset)
node _T_742 = eq(_T_741, UInt<1>(0h0))
when _T_742 :
node _T_743 = eq(_T_740, UInt<1>(0h0))
when _T_743 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_740, UInt<1>(0h1), "") : assert_40
node _T_744 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_744 :
node _T_745 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_746 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_747 = and(_T_745, _T_746)
node _T_748 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_749 = and(_T_747, _T_748)
node _T_750 = or(UInt<1>(0h0), _T_749)
node _T_751 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_752 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_753 = and(_T_751, _T_752)
node _T_754 = or(UInt<1>(0h0), _T_753)
node _T_755 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_756 = cvt(_T_755)
node _T_757 = and(_T_756, asSInt(UInt<14>(0h2000)))
node _T_758 = asSInt(_T_757)
node _T_759 = eq(_T_758, asSInt(UInt<1>(0h0)))
node _T_760 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_761 = cvt(_T_760)
node _T_762 = and(_T_761, asSInt(UInt<13>(0h1000)))
node _T_763 = asSInt(_T_762)
node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0)))
node _T_765 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_766 = cvt(_T_765)
node _T_767 = and(_T_766, asSInt(UInt<18>(0h2f000)))
node _T_768 = asSInt(_T_767)
node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0)))
node _T_770 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_771 = cvt(_T_770)
node _T_772 = and(_T_771, asSInt(UInt<17>(0h10000)))
node _T_773 = asSInt(_T_772)
node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0)))
node _T_775 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_776 = cvt(_T_775)
node _T_777 = and(_T_776, asSInt(UInt<13>(0h1000)))
node _T_778 = asSInt(_T_777)
node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0)))
node _T_780 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_781 = cvt(_T_780)
node _T_782 = and(_T_781, asSInt(UInt<17>(0h10000)))
node _T_783 = asSInt(_T_782)
node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0)))
node _T_785 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_786 = cvt(_T_785)
node _T_787 = and(_T_786, asSInt(UInt<27>(0h4000000)))
node _T_788 = asSInt(_T_787)
node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0)))
node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_791 = cvt(_T_790)
node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000)))
node _T_793 = asSInt(_T_792)
node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0)))
node _T_795 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_796 = cvt(_T_795)
node _T_797 = and(_T_796, asSInt(UInt<29>(0h10000000)))
node _T_798 = asSInt(_T_797)
node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0)))
node _T_800 = or(_T_759, _T_764)
node _T_801 = or(_T_800, _T_769)
node _T_802 = or(_T_801, _T_774)
node _T_803 = or(_T_802, _T_779)
node _T_804 = or(_T_803, _T_784)
node _T_805 = or(_T_804, _T_789)
node _T_806 = or(_T_805, _T_794)
node _T_807 = or(_T_806, _T_799)
node _T_808 = and(_T_754, _T_807)
node _T_809 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_810 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_811 = cvt(_T_810)
node _T_812 = and(_T_811, asSInt(UInt<17>(0h10000)))
node _T_813 = asSInt(_T_812)
node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0)))
node _T_815 = and(_T_809, _T_814)
node _T_816 = or(UInt<1>(0h0), _T_808)
node _T_817 = or(_T_816, _T_815)
node _T_818 = and(_T_750, _T_817)
node _T_819 = asUInt(reset)
node _T_820 = eq(_T_819, UInt<1>(0h0))
when _T_820 :
node _T_821 = eq(_T_818, UInt<1>(0h0))
when _T_821 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_818, UInt<1>(0h1), "") : assert_41
node _T_822 = asUInt(reset)
node _T_823 = eq(_T_822, UInt<1>(0h0))
when _T_823 :
node _T_824 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_824 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_825 = asUInt(reset)
node _T_826 = eq(_T_825, UInt<1>(0h0))
when _T_826 :
node _T_827 = eq(is_aligned, UInt<1>(0h0))
when _T_827 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_828 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_829 = asUInt(reset)
node _T_830 = eq(_T_829, UInt<1>(0h0))
when _T_830 :
node _T_831 = eq(_T_828, UInt<1>(0h0))
when _T_831 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_828, UInt<1>(0h1), "") : assert_44
node _T_832 = eq(io.in.a.bits.mask, UInt<1>(0h1))
node _T_833 = asUInt(reset)
node _T_834 = eq(_T_833, UInt<1>(0h0))
when _T_834 :
node _T_835 = eq(_T_832, UInt<1>(0h0))
when _T_835 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_832, UInt<1>(0h1), "") : assert_45
node _T_836 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_836 :
node _T_837 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_838 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_839 = and(_T_837, _T_838)
node _T_840 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_841 = and(_T_839, _T_840)
node _T_842 = or(UInt<1>(0h0), _T_841)
node _T_843 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_844 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_845 = and(_T_843, _T_844)
node _T_846 = or(UInt<1>(0h0), _T_845)
node _T_847 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_848 = cvt(_T_847)
node _T_849 = and(_T_848, asSInt(UInt<13>(0h1000)))
node _T_850 = asSInt(_T_849)
node _T_851 = eq(_T_850, asSInt(UInt<1>(0h0)))
node _T_852 = and(_T_846, _T_851)
node _T_853 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_854 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_855 = cvt(_T_854)
node _T_856 = and(_T_855, asSInt(UInt<14>(0h2000)))
node _T_857 = asSInt(_T_856)
node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0)))
node _T_859 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_860 = cvt(_T_859)
node _T_861 = and(_T_860, asSInt(UInt<17>(0h10000)))
node _T_862 = asSInt(_T_861)
node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0)))
node _T_864 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_865 = cvt(_T_864)
node _T_866 = and(_T_865, asSInt(UInt<18>(0h2f000)))
node _T_867 = asSInt(_T_866)
node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0)))
node _T_869 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_870 = cvt(_T_869)
node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000)))
node _T_872 = asSInt(_T_871)
node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0)))
node _T_874 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_875 = cvt(_T_874)
node _T_876 = and(_T_875, asSInt(UInt<13>(0h1000)))
node _T_877 = asSInt(_T_876)
node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0)))
node _T_879 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_880 = cvt(_T_879)
node _T_881 = and(_T_880, asSInt(UInt<27>(0h4000000)))
node _T_882 = asSInt(_T_881)
node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0)))
node _T_884 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_885 = cvt(_T_884)
node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000)))
node _T_887 = asSInt(_T_886)
node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0)))
node _T_889 = or(_T_858, _T_863)
node _T_890 = or(_T_889, _T_868)
node _T_891 = or(_T_890, _T_873)
node _T_892 = or(_T_891, _T_878)
node _T_893 = or(_T_892, _T_883)
node _T_894 = or(_T_893, _T_888)
node _T_895 = and(_T_853, _T_894)
node _T_896 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_897 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_898 = and(_T_896, _T_897)
node _T_899 = or(UInt<1>(0h0), _T_898)
node _T_900 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_901 = cvt(_T_900)
node _T_902 = and(_T_901, asSInt(UInt<17>(0h10000)))
node _T_903 = asSInt(_T_902)
node _T_904 = eq(_T_903, asSInt(UInt<1>(0h0)))
node _T_905 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_906 = cvt(_T_905)
node _T_907 = and(_T_906, asSInt(UInt<29>(0h10000000)))
node _T_908 = asSInt(_T_907)
node _T_909 = eq(_T_908, asSInt(UInt<1>(0h0)))
node _T_910 = or(_T_904, _T_909)
node _T_911 = and(_T_899, _T_910)
node _T_912 = or(UInt<1>(0h0), _T_852)
node _T_913 = or(_T_912, _T_895)
node _T_914 = or(_T_913, _T_911)
node _T_915 = and(_T_842, _T_914)
node _T_916 = asUInt(reset)
node _T_917 = eq(_T_916, UInt<1>(0h0))
when _T_917 :
node _T_918 = eq(_T_915, UInt<1>(0h0))
when _T_918 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_915, UInt<1>(0h1), "") : assert_46
node _T_919 = asUInt(reset)
node _T_920 = eq(_T_919, UInt<1>(0h0))
when _T_920 :
node _T_921 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_921 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_922 = asUInt(reset)
node _T_923 = eq(_T_922, UInt<1>(0h0))
when _T_923 :
node _T_924 = eq(is_aligned, UInt<1>(0h0))
when _T_924 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_925 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_926 = asUInt(reset)
node _T_927 = eq(_T_926, UInt<1>(0h0))
when _T_927 :
node _T_928 = eq(_T_925, UInt<1>(0h0))
when _T_928 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_925, UInt<1>(0h1), "") : assert_49
node _T_929 = eq(io.in.a.bits.mask, UInt<1>(0h1))
node _T_930 = asUInt(reset)
node _T_931 = eq(_T_930, UInt<1>(0h0))
when _T_931 :
node _T_932 = eq(_T_929, UInt<1>(0h0))
when _T_932 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_929, UInt<1>(0h1), "") : assert_50
node _T_933 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_934 = asUInt(reset)
node _T_935 = eq(_T_934, UInt<1>(0h0))
when _T_935 :
node _T_936 = eq(_T_933, UInt<1>(0h0))
when _T_936 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_933, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_937 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_938 = asUInt(reset)
node _T_939 = eq(_T_938, UInt<1>(0h0))
when _T_939 :
node _T_940 = eq(_T_937, UInt<1>(0h0))
when _T_940 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_937, UInt<1>(0h1), "") : assert_52
node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_1
node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8))
node _T_941 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_941 :
node _T_942 = asUInt(reset)
node _T_943 = eq(_T_942, UInt<1>(0h0))
when _T_943 :
node _T_944 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_944 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_945 = geq(io.in.d.bits.size, UInt<1>(0h0))
node _T_946 = asUInt(reset)
node _T_947 = eq(_T_946, UInt<1>(0h0))
when _T_947 :
node _T_948 = eq(_T_945, UInt<1>(0h0))
when _T_948 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_945, UInt<1>(0h1), "") : assert_54
node _T_949 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_950 = asUInt(reset)
node _T_951 = eq(_T_950, UInt<1>(0h0))
when _T_951 :
node _T_952 = eq(_T_949, UInt<1>(0h0))
when _T_952 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_949, UInt<1>(0h1), "") : assert_55
node _T_953 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_954 = asUInt(reset)
node _T_955 = eq(_T_954, UInt<1>(0h0))
when _T_955 :
node _T_956 = eq(_T_953, UInt<1>(0h0))
when _T_956 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_953, UInt<1>(0h1), "") : assert_56
node _T_957 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_958 = asUInt(reset)
node _T_959 = eq(_T_958, UInt<1>(0h0))
when _T_959 :
node _T_960 = eq(_T_957, UInt<1>(0h0))
when _T_960 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_957, UInt<1>(0h1), "") : assert_57
node _T_961 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_961 :
node _T_962 = asUInt(reset)
node _T_963 = eq(_T_962, UInt<1>(0h0))
when _T_963 :
node _T_964 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_964 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_965 = asUInt(reset)
node _T_966 = eq(_T_965, UInt<1>(0h0))
when _T_966 :
node _T_967 = eq(sink_ok, UInt<1>(0h0))
when _T_967 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_968 = geq(io.in.d.bits.size, UInt<1>(0h0))
node _T_969 = asUInt(reset)
node _T_970 = eq(_T_969, UInt<1>(0h0))
when _T_970 :
node _T_971 = eq(_T_968, UInt<1>(0h0))
when _T_971 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_968, UInt<1>(0h1), "") : assert_60
node _T_972 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_973 = asUInt(reset)
node _T_974 = eq(_T_973, UInt<1>(0h0))
when _T_974 :
node _T_975 = eq(_T_972, UInt<1>(0h0))
when _T_975 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_972, UInt<1>(0h1), "") : assert_61
node _T_976 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_977 = asUInt(reset)
node _T_978 = eq(_T_977, UInt<1>(0h0))
when _T_978 :
node _T_979 = eq(_T_976, UInt<1>(0h0))
when _T_979 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_976, UInt<1>(0h1), "") : assert_62
node _T_980 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_981 = asUInt(reset)
node _T_982 = eq(_T_981, UInt<1>(0h0))
when _T_982 :
node _T_983 = eq(_T_980, UInt<1>(0h0))
when _T_983 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_980, UInt<1>(0h1), "") : assert_63
node _T_984 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_985 = or(UInt<1>(0h1), _T_984)
node _T_986 = asUInt(reset)
node _T_987 = eq(_T_986, UInt<1>(0h0))
when _T_987 :
node _T_988 = eq(_T_985, UInt<1>(0h0))
when _T_988 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_985, UInt<1>(0h1), "") : assert_64
node _T_989 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_989 :
node _T_990 = asUInt(reset)
node _T_991 = eq(_T_990, UInt<1>(0h0))
when _T_991 :
node _T_992 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_992 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_993 = asUInt(reset)
node _T_994 = eq(_T_993, UInt<1>(0h0))
when _T_994 :
node _T_995 = eq(sink_ok, UInt<1>(0h0))
when _T_995 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_996 = geq(io.in.d.bits.size, UInt<1>(0h0))
node _T_997 = asUInt(reset)
node _T_998 = eq(_T_997, UInt<1>(0h0))
when _T_998 :
node _T_999 = eq(_T_996, UInt<1>(0h0))
when _T_999 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_996, UInt<1>(0h1), "") : assert_67
node _T_1000 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1001 = asUInt(reset)
node _T_1002 = eq(_T_1001, UInt<1>(0h0))
when _T_1002 :
node _T_1003 = eq(_T_1000, UInt<1>(0h0))
when _T_1003 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1000, UInt<1>(0h1), "") : assert_68
node _T_1004 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1005 = asUInt(reset)
node _T_1006 = eq(_T_1005, UInt<1>(0h0))
when _T_1006 :
node _T_1007 = eq(_T_1004, UInt<1>(0h0))
when _T_1007 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1004, UInt<1>(0h1), "") : assert_69
node _T_1008 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1009 = or(_T_1008, io.in.d.bits.corrupt)
node _T_1010 = asUInt(reset)
node _T_1011 = eq(_T_1010, UInt<1>(0h0))
when _T_1011 :
node _T_1012 = eq(_T_1009, UInt<1>(0h0))
when _T_1012 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1009, UInt<1>(0h1), "") : assert_70
node _T_1013 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1014 = or(UInt<1>(0h1), _T_1013)
node _T_1015 = asUInt(reset)
node _T_1016 = eq(_T_1015, UInt<1>(0h0))
when _T_1016 :
node _T_1017 = eq(_T_1014, UInt<1>(0h0))
when _T_1017 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1014, UInt<1>(0h1), "") : assert_71
node _T_1018 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1018 :
node _T_1019 = asUInt(reset)
node _T_1020 = eq(_T_1019, UInt<1>(0h0))
when _T_1020 :
node _T_1021 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1021 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_1022 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1023 = asUInt(reset)
node _T_1024 = eq(_T_1023, UInt<1>(0h0))
when _T_1024 :
node _T_1025 = eq(_T_1022, UInt<1>(0h0))
when _T_1025 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1022, UInt<1>(0h1), "") : assert_73
node _T_1026 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1027 = asUInt(reset)
node _T_1028 = eq(_T_1027, UInt<1>(0h0))
when _T_1028 :
node _T_1029 = eq(_T_1026, UInt<1>(0h0))
when _T_1029 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1026, UInt<1>(0h1), "") : assert_74
node _T_1030 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1031 = or(UInt<1>(0h1), _T_1030)
node _T_1032 = asUInt(reset)
node _T_1033 = eq(_T_1032, UInt<1>(0h0))
when _T_1033 :
node _T_1034 = eq(_T_1031, UInt<1>(0h0))
when _T_1034 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1031, UInt<1>(0h1), "") : assert_75
node _T_1035 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1035 :
node _T_1036 = asUInt(reset)
node _T_1037 = eq(_T_1036, UInt<1>(0h0))
when _T_1037 :
node _T_1038 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1038 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_1039 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1040 = asUInt(reset)
node _T_1041 = eq(_T_1040, UInt<1>(0h0))
when _T_1041 :
node _T_1042 = eq(_T_1039, UInt<1>(0h0))
when _T_1042 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1039, UInt<1>(0h1), "") : assert_77
node _T_1043 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1044 = or(_T_1043, io.in.d.bits.corrupt)
node _T_1045 = asUInt(reset)
node _T_1046 = eq(_T_1045, UInt<1>(0h0))
when _T_1046 :
node _T_1047 = eq(_T_1044, UInt<1>(0h0))
when _T_1047 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1044, UInt<1>(0h1), "") : assert_78
node _T_1048 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1049 = or(UInt<1>(0h1), _T_1048)
node _T_1050 = asUInt(reset)
node _T_1051 = eq(_T_1050, UInt<1>(0h0))
when _T_1051 :
node _T_1052 = eq(_T_1049, UInt<1>(0h0))
when _T_1052 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1049, UInt<1>(0h1), "") : assert_79
node _T_1053 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1053 :
node _T_1054 = asUInt(reset)
node _T_1055 = eq(_T_1054, UInt<1>(0h0))
when _T_1055 :
node _T_1056 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1056 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_1057 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1058 = asUInt(reset)
node _T_1059 = eq(_T_1058, UInt<1>(0h0))
when _T_1059 :
node _T_1060 = eq(_T_1057, UInt<1>(0h0))
when _T_1060 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1057, UInt<1>(0h1), "") : assert_81
node _T_1061 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1062 = asUInt(reset)
node _T_1063 = eq(_T_1062, UInt<1>(0h0))
when _T_1063 :
node _T_1064 = eq(_T_1061, UInt<1>(0h0))
when _T_1064 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1061, UInt<1>(0h1), "") : assert_82
node _T_1065 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1066 = or(UInt<1>(0h1), _T_1065)
node _T_1067 = asUInt(reset)
node _T_1068 = eq(_T_1067, UInt<1>(0h0))
when _T_1068 :
node _T_1069 = eq(_T_1066, UInt<1>(0h0))
when _T_1069 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1066, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<8>(0h0)
connect _WIRE.bits.mask, UInt<1>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1070 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_1071 = asUInt(reset)
node _T_1072 = eq(_T_1071, UInt<1>(0h0))
when _T_1072 :
node _T_1073 = eq(_T_1070, UInt<1>(0h0))
when _T_1073 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1070, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<8>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_1074 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_1075 = asUInt(reset)
node _T_1076 = eq(_T_1075, UInt<1>(0h0))
when _T_1076 :
node _T_1077 = eq(_T_1074, UInt<1>(0h0))
when _T_1077 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1074, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_4.bits.sink, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1078 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1079 = asUInt(reset)
node _T_1080 = eq(_T_1079, UInt<1>(0h0))
when _T_1080 :
node _T_1081 = eq(_T_1078, UInt<1>(0h0))
when _T_1081 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1078, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 0)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<12>, clock, reset, UInt<12>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1082 = eq(a_first, UInt<1>(0h0))
node _T_1083 = and(io.in.a.valid, _T_1082)
when _T_1083 :
node _T_1084 = eq(io.in.a.bits.opcode, opcode)
node _T_1085 = asUInt(reset)
node _T_1086 = eq(_T_1085, UInt<1>(0h0))
when _T_1086 :
node _T_1087 = eq(_T_1084, UInt<1>(0h0))
when _T_1087 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1084, UInt<1>(0h1), "") : assert_87
node _T_1088 = eq(io.in.a.bits.param, param)
node _T_1089 = asUInt(reset)
node _T_1090 = eq(_T_1089, UInt<1>(0h0))
when _T_1090 :
node _T_1091 = eq(_T_1088, UInt<1>(0h0))
when _T_1091 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1088, UInt<1>(0h1), "") : assert_88
node _T_1092 = eq(io.in.a.bits.size, size)
node _T_1093 = asUInt(reset)
node _T_1094 = eq(_T_1093, UInt<1>(0h0))
when _T_1094 :
node _T_1095 = eq(_T_1092, UInt<1>(0h0))
when _T_1095 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1092, UInt<1>(0h1), "") : assert_89
node _T_1096 = eq(io.in.a.bits.source, source)
node _T_1097 = asUInt(reset)
node _T_1098 = eq(_T_1097, UInt<1>(0h0))
when _T_1098 :
node _T_1099 = eq(_T_1096, UInt<1>(0h0))
when _T_1099 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1096, UInt<1>(0h1), "") : assert_90
node _T_1100 = eq(io.in.a.bits.address, address)
node _T_1101 = asUInt(reset)
node _T_1102 = eq(_T_1101, UInt<1>(0h0))
when _T_1102 :
node _T_1103 = eq(_T_1100, UInt<1>(0h0))
when _T_1103 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1100, UInt<1>(0h1), "") : assert_91
node _T_1104 = and(io.in.a.ready, io.in.a.valid)
node _T_1105 = and(_T_1104, a_first)
when _T_1105 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 0)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<12>, clock, reset, UInt<12>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1106 = eq(d_first, UInt<1>(0h0))
node _T_1107 = and(io.in.d.valid, _T_1106)
when _T_1107 :
node _T_1108 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1109 = asUInt(reset)
node _T_1110 = eq(_T_1109, UInt<1>(0h0))
when _T_1110 :
node _T_1111 = eq(_T_1108, UInt<1>(0h0))
when _T_1111 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1108, UInt<1>(0h1), "") : assert_92
node _T_1112 = eq(io.in.d.bits.param, param_1)
node _T_1113 = asUInt(reset)
node _T_1114 = eq(_T_1113, UInt<1>(0h0))
when _T_1114 :
node _T_1115 = eq(_T_1112, UInt<1>(0h0))
when _T_1115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1112, UInt<1>(0h1), "") : assert_93
node _T_1116 = eq(io.in.d.bits.size, size_1)
node _T_1117 = asUInt(reset)
node _T_1118 = eq(_T_1117, UInt<1>(0h0))
when _T_1118 :
node _T_1119 = eq(_T_1116, UInt<1>(0h0))
when _T_1119 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1116, UInt<1>(0h1), "") : assert_94
node _T_1120 = eq(io.in.d.bits.source, source_1)
node _T_1121 = asUInt(reset)
node _T_1122 = eq(_T_1121, UInt<1>(0h0))
when _T_1122 :
node _T_1123 = eq(_T_1120, UInt<1>(0h0))
when _T_1123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1120, UInt<1>(0h1), "") : assert_95
node _T_1124 = eq(io.in.d.bits.sink, sink)
node _T_1125 = asUInt(reset)
node _T_1126 = eq(_T_1125, UInt<1>(0h0))
when _T_1126 :
node _T_1127 = eq(_T_1124, UInt<1>(0h0))
when _T_1127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1124, UInt<1>(0h1), "") : assert_96
node _T_1128 = eq(io.in.d.bits.denied, denied)
node _T_1129 = asUInt(reset)
node _T_1130 = eq(_T_1129, UInt<1>(0h0))
when _T_1130 :
node _T_1131 = eq(_T_1128, UInt<1>(0h0))
when _T_1131 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1128, UInt<1>(0h1), "") : assert_97
node _T_1132 = and(io.in.d.ready, io.in.d.valid)
node _T_1133 = and(_T_1132, d_first)
when _T_1133 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 0)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<12>, clock, reset, UInt<12>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 0)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<12>, clock, reset, UInt<12>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1>
connect a_set, UInt<1>(0h0)
wire a_set_wo_ready : UInt<1>
connect a_set_wo_ready, UInt<1>(0h0)
wire a_opcodes_set : UInt<4>
connect a_opcodes_set, UInt<4>(0h0)
wire a_sizes_set : UInt<8>
connect a_sizes_set, UInt<8>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1134 = and(io.in.a.valid, a_first_1)
node _T_1135 = and(_T_1134, UInt<1>(0h1))
when _T_1135 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1136 = and(io.in.a.ready, io.in.a.valid)
node _T_1137 = and(_T_1136, a_first_1)
node _T_1138 = and(_T_1137, UInt<1>(0h1))
when _T_1138 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1139 = dshr(inflight, io.in.a.bits.source)
node _T_1140 = bits(_T_1139, 0, 0)
node _T_1141 = eq(_T_1140, UInt<1>(0h0))
node _T_1142 = asUInt(reset)
node _T_1143 = eq(_T_1142, UInt<1>(0h0))
when _T_1143 :
node _T_1144 = eq(_T_1141, UInt<1>(0h0))
when _T_1144 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1141, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1>
connect d_clr, UInt<1>(0h0)
wire d_clr_wo_ready : UInt<1>
connect d_clr_wo_ready, UInt<1>(0h0)
wire d_opcodes_clr : UInt<4>
connect d_opcodes_clr, UInt<4>(0h0)
wire d_sizes_clr : UInt<8>
connect d_sizes_clr, UInt<8>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1145 = and(io.in.d.valid, d_first_1)
node _T_1146 = and(_T_1145, UInt<1>(0h1))
node _T_1147 = eq(d_release_ack, UInt<1>(0h0))
node _T_1148 = and(_T_1146, _T_1147)
when _T_1148 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1149 = and(io.in.d.ready, io.in.d.valid)
node _T_1150 = and(_T_1149, d_first_1)
node _T_1151 = and(_T_1150, UInt<1>(0h1))
node _T_1152 = eq(d_release_ack, UInt<1>(0h0))
node _T_1153 = and(_T_1151, _T_1152)
when _T_1153 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1154 = and(io.in.d.valid, d_first_1)
node _T_1155 = and(_T_1154, UInt<1>(0h1))
node _T_1156 = eq(d_release_ack, UInt<1>(0h0))
node _T_1157 = and(_T_1155, _T_1156)
when _T_1157 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1158 = dshr(inflight, io.in.d.bits.source)
node _T_1159 = bits(_T_1158, 0, 0)
node _T_1160 = or(_T_1159, same_cycle_resp)
node _T_1161 = asUInt(reset)
node _T_1162 = eq(_T_1161, UInt<1>(0h0))
when _T_1162 :
node _T_1163 = eq(_T_1160, UInt<1>(0h0))
when _T_1163 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1160, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1164 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1165 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1166 = or(_T_1164, _T_1165)
node _T_1167 = asUInt(reset)
node _T_1168 = eq(_T_1167, UInt<1>(0h0))
when _T_1168 :
node _T_1169 = eq(_T_1166, UInt<1>(0h0))
when _T_1169 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1166, UInt<1>(0h1), "") : assert_100
node _T_1170 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1171 = asUInt(reset)
node _T_1172 = eq(_T_1171, UInt<1>(0h0))
when _T_1172 :
node _T_1173 = eq(_T_1170, UInt<1>(0h0))
when _T_1173 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1170, UInt<1>(0h1), "") : assert_101
else :
node _T_1174 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1175 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1176 = or(_T_1174, _T_1175)
node _T_1177 = asUInt(reset)
node _T_1178 = eq(_T_1177, UInt<1>(0h0))
when _T_1178 :
node _T_1179 = eq(_T_1176, UInt<1>(0h0))
when _T_1179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1176, UInt<1>(0h1), "") : assert_102
node _T_1180 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1181 = asUInt(reset)
node _T_1182 = eq(_T_1181, UInt<1>(0h0))
when _T_1182 :
node _T_1183 = eq(_T_1180, UInt<1>(0h0))
when _T_1183 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1180, UInt<1>(0h1), "") : assert_103
node _T_1184 = and(io.in.d.valid, d_first_1)
node _T_1185 = and(_T_1184, a_first_1)
node _T_1186 = and(_T_1185, io.in.a.valid)
node _T_1187 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1188 = and(_T_1186, _T_1187)
node _T_1189 = eq(d_release_ack, UInt<1>(0h0))
node _T_1190 = and(_T_1188, _T_1189)
when _T_1190 :
node _T_1191 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1192 = or(_T_1191, io.in.a.ready)
node _T_1193 = asUInt(reset)
node _T_1194 = eq(_T_1193, UInt<1>(0h0))
when _T_1194 :
node _T_1195 = eq(_T_1192, UInt<1>(0h0))
when _T_1195 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1192, UInt<1>(0h1), "") : assert_104
node _T_1196 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1197 = orr(a_set_wo_ready)
node _T_1198 = eq(_T_1197, UInt<1>(0h0))
node _T_1199 = or(_T_1196, _T_1198)
node _T_1200 = asUInt(reset)
node _T_1201 = eq(_T_1200, UInt<1>(0h0))
when _T_1201 :
node _T_1202 = eq(_T_1199, UInt<1>(0h0))
when _T_1202 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1199, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_60
node _T_1203 = orr(inflight)
node _T_1204 = eq(_T_1203, UInt<1>(0h0))
node _T_1205 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1206 = or(_T_1204, _T_1205)
node _T_1207 = lt(watchdog, plusarg_reader.out)
node _T_1208 = or(_T_1206, _T_1207)
node _T_1209 = asUInt(reset)
node _T_1210 = eq(_T_1209, UInt<1>(0h0))
when _T_1210 :
node _T_1211 = eq(_T_1208, UInt<1>(0h0))
when _T_1211 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1208, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1212 = and(io.in.a.ready, io.in.a.valid)
node _T_1213 = and(io.in.d.ready, io.in.d.valid)
node _T_1214 = or(_T_1212, _T_1213)
when _T_1214 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<8>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<1>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<8>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 0)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<12>, clock, reset, UInt<12>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 0)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<12>, clock, reset, UInt<12>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1>
connect c_set, UInt<1>(0h0)
wire c_set_wo_ready : UInt<1>
connect c_set_wo_ready, UInt<1>(0h0)
wire c_opcodes_set : UInt<4>
connect c_opcodes_set, UInt<4>(0h0)
wire c_sizes_set : UInt<8>
connect c_sizes_set, UInt<8>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1215 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<8>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1216 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1217 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1218 = and(_T_1216, _T_1217)
node _T_1219 = and(_T_1215, _T_1218)
when _T_1219 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<8>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<8>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<1>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1220 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1221 = and(_T_1220, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<8>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<1>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1222 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1223 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1224 = and(_T_1222, _T_1223)
node _T_1225 = and(_T_1221, _T_1224)
when _T_1225 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<8>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<8>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<8>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<8>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<8>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<8>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<1>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1226 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1227 = bits(_T_1226, 0, 0)
node _T_1228 = eq(_T_1227, UInt<1>(0h0))
node _T_1229 = asUInt(reset)
node _T_1230 = eq(_T_1229, UInt<1>(0h0))
when _T_1230 :
node _T_1231 = eq(_T_1228, UInt<1>(0h0))
when _T_1231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1228, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<8>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<8>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1>
connect d_clr_1, UInt<1>(0h0)
wire d_clr_wo_ready_1 : UInt<1>
connect d_clr_wo_ready_1, UInt<1>(0h0)
wire d_opcodes_clr_1 : UInt<4>
connect d_opcodes_clr_1, UInt<4>(0h0)
wire d_sizes_clr_1 : UInt<8>
connect d_sizes_clr_1, UInt<8>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1232 = and(io.in.d.valid, d_first_2)
node _T_1233 = and(_T_1232, UInt<1>(0h1))
node _T_1234 = and(_T_1233, d_release_ack_1)
when _T_1234 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1235 = and(io.in.d.ready, io.in.d.valid)
node _T_1236 = and(_T_1235, d_first_2)
node _T_1237 = and(_T_1236, UInt<1>(0h1))
node _T_1238 = and(_T_1237, d_release_ack_1)
when _T_1238 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1239 = and(io.in.d.valid, d_first_2)
node _T_1240 = and(_T_1239, UInt<1>(0h1))
node _T_1241 = and(_T_1240, d_release_ack_1)
when _T_1241 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<8>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<8>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<8>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1242 = dshr(inflight_1, io.in.d.bits.source)
node _T_1243 = bits(_T_1242, 0, 0)
node _T_1244 = or(_T_1243, same_cycle_resp_1)
node _T_1245 = asUInt(reset)
node _T_1246 = eq(_T_1245, UInt<1>(0h0))
when _T_1246 :
node _T_1247 = eq(_T_1244, UInt<1>(0h0))
when _T_1247 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1244, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<8>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<1>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1248 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1249 = asUInt(reset)
node _T_1250 = eq(_T_1249, UInt<1>(0h0))
when _T_1250 :
node _T_1251 = eq(_T_1248, UInt<1>(0h0))
when _T_1251 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1248, UInt<1>(0h1), "") : assert_109
else :
node _T_1252 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1253 = asUInt(reset)
node _T_1254 = eq(_T_1253, UInt<1>(0h0))
when _T_1254 :
node _T_1255 = eq(_T_1252, UInt<1>(0h0))
when _T_1255 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1252, UInt<1>(0h1), "") : assert_110
node _T_1256 = and(io.in.d.valid, d_first_2)
node _T_1257 = and(_T_1256, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<8>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<1>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1258 = and(_T_1257, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<8>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<1>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1259 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1260 = and(_T_1258, _T_1259)
node _T_1261 = and(_T_1260, d_release_ack_1)
node _T_1262 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1263 = and(_T_1261, _T_1262)
when _T_1263 :
node _T_1264 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<8>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<1>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1265 = or(_T_1264, _WIRE_23.ready)
node _T_1266 = asUInt(reset)
node _T_1267 = eq(_T_1266, UInt<1>(0h0))
when _T_1267 :
node _T_1268 = eq(_T_1265, UInt<1>(0h0))
when _T_1268 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1265, UInt<1>(0h1), "") : assert_111
node _T_1269 = orr(c_set_wo_ready)
when _T_1269 :
node _T_1270 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1271 = asUInt(reset)
node _T_1272 = eq(_T_1271, UInt<1>(0h0))
when _T_1272 :
node _T_1273 = eq(_T_1270, UInt<1>(0h0))
when _T_1273 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1270, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_61
node _T_1274 = orr(inflight_1)
node _T_1275 = eq(_T_1274, UInt<1>(0h0))
node _T_1276 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1277 = or(_T_1275, _T_1276)
node _T_1278 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1279 = or(_T_1277, _T_1278)
node _T_1280 = asUInt(reset)
node _T_1281 = eq(_T_1280, UInt<1>(0h0))
when _T_1281 :
node _T_1282 = eq(_T_1279, UInt<1>(0h0))
when _T_1282 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1279, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<8>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<1>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1283 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1284 = and(io.in.d.ready, io.in.d.valid)
node _T_1285 = or(_T_1283, _T_1284)
when _T_1285 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_30( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [7:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [7:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire c_set = 1'h0; // @[Monitor.scala:738:34]
wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire io_in_a_bits_mask = 1'h1; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31]
wire mask_sizeOH = 1'h1; // @[Misc.scala:202:81]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113]
wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69]
wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65]
wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79]
wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77]
wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101]
wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34]
wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69]
wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101]
wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74]
wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74]
wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76]
wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76]
wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] c_first_beats1_decode = 12'h0; // @[Edges.scala:220:59]
wire [11:0] c_first_beats1 = 12'h0; // @[Edges.scala:221:14]
wire [11:0] _c_first_count_T = 12'h0; // @[Edges.scala:234:27]
wire [11:0] c_first_count = 12'h0; // @[Edges.scala:234:25]
wire [11:0] _c_first_counter_T = 12'h0; // @[Edges.scala:236:21]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [11:0] c_first_counter1 = 12'hFFF; // @[Edges.scala:230:28]
wire [12:0] _c_first_counter1_T = 13'h1FFF; // @[Edges.scala:230:28]
wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_2_bits_data = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_3_bits_data = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34]
wire [7:0] _c_set_wo_ready_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_wo_ready_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_interm_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_interm_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_interm_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_2_bits_data = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_3_bits_data = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_2_bits_data = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_3_bits_data = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_4_bits_data = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_5_bits_data = 8'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52]
wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire _T_1212 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1212; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1212; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [11:0] a_first_beats1_decode = _a_first_beats1_decode_T_2; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [11:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 12'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [11:0] a_first_counter; // @[Edges.scala:229:27]
wire [12:0] _a_first_counter1_T = {1'h0, a_first_counter} - 13'h1; // @[Edges.scala:229:27, :230:28]
wire [11:0] a_first_counter1 = _a_first_counter1_T[11:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 12'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 12'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 12'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [11:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [11:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1285 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1285; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1285; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1285; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [11:0] d_first_beats1_decode = _d_first_beats1_decode_T_2; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [11:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 12'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [11:0] d_first_counter; // @[Edges.scala:229:27]
wire [12:0] _d_first_counter1_T = {1'h0, d_first_counter} - 13'h1; // @[Edges.scala:229:27, :230:28]
wire [11:0] d_first_counter1 = _d_first_counter1_T[11:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 12'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 12'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 12'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [11:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [11:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [11:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44]
reg [7:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [11:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [11:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 12'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [11:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [12:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 13'h1; // @[Edges.scala:229:27, :230:28]
wire [11:0] a_first_counter1_1 = _a_first_counter1_T_1[11:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 12'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 12'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 12'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [11:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [11:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [11:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5; // @[package.scala:243:46]
wire [11:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 12'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [11:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [12:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 13'h1; // @[Edges.scala:229:27, :230:28]
wire [11:0] d_first_counter1_1 = _d_first_counter1_T_1[11:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 12'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 12'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 12'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [11:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [11:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [11:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire a_set; // @[Monitor.scala:626:34]
wire a_set_wo_ready; // @[Monitor.scala:627:34]
wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [7:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}]
wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _T_1135 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26]
assign a_set_wo_ready = _T_1135; // @[Monitor.scala:627:34, :651:26]
wire _same_cycle_resp_T; // @[Monitor.scala:684:44]
assign _same_cycle_resp_T = _T_1135; // @[Monitor.scala:651:26, :684:44]
assign a_set = _T_1212 & a_first_1; // @[Decoupled.scala:51:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = a_set ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:{28,59}]
wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54]
assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}]
wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :660:52]
assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}]
wire d_clr; // @[Monitor.scala:664:34]
wire d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_1 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_1; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_1; // @[Monitor.scala:673:46, :783:46]
wire _T_1184 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
assign d_clr_wo_ready = _T_1184 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}]
assign d_clr = _T_1285 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21]
assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}]
wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27]
wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}]
wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44]
wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42]
wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [11:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8; // @[package.scala:243:46]
wire [11:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 12'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [11:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [12:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 13'h1; // @[Edges.scala:229:27, :230:28]
wire [11:0] d_first_counter1_2 = _d_first_counter1_T_2[11:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 12'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 12'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 12'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [11:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [11:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [11:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}]
wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire d_clr_1; // @[Monitor.scala:774:34]
wire d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1256 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1256 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}]
assign d_clr_1 = _T_1285 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21]
assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21]
wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}]
wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module BoomTile_1 :
input clock : Clock
input reset : Reset
output auto : { buffer_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}, wfi_out : UInt<1>[1], cease_out : UInt<1>[1], halt_out : UInt<1>[1], flip int_local_in_3 : UInt<1>[1], flip int_local_in_2 : UInt<1>[1], flip int_local_in_1 : UInt<1>[2], flip int_local_in_0 : UInt<1>[1], trace_core_source_out : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>}, trace_source_out : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[3], time : UInt<64>, custom : { rob_empty : UInt<1>}}, flip reset_vector_in : UInt<32>, flip hartid_in : UInt<2>}
inst tlMasterXbar of TLXbar_MasterXbar_BoomTile_i2_o1_a32d128s4k4z4c_1
connect tlMasterXbar.clock, clock
connect tlMasterXbar.reset, reset
inst tlSlaveXbar of TLXbar_SlaveXbar_BoomTile_i0_o0_a1d8s1k1z1u_1
connect tlSlaveXbar.clock, clock
connect tlSlaveXbar.reset, reset
inst intXbar of IntXbar_i4_o1_3
inst broadcast of BundleBridgeNexus_UInt2_3
inst broadcast_1 of BundleBridgeNexus_UInt32_3
inst nexus of BundleBridgeNexus_NoOutput_12
inst nexus_1 of BundleBridgeNexus_TraceAux_3
inst broadcast_2 of BundleBridgeNexus_NoOutput_13
inst widget of TLWidthWidget16_8
connect widget.clock, clock
connect widget.reset, reset
inst dcache of BoomNonBlockingDCache_1
connect dcache.clock, clock
connect dcache.reset, reset
inst frontend of BoomFrontend_1
connect frontend.clock, clock
connect frontend.reset, reset
inst widget_1 of TLWidthWidget16_9
connect widget_1.clock, clock
connect widget_1.reset, reset
inst buffer of TLBuffer_a32d128s4k4z4c_2
connect buffer.clock, clock
connect buffer.reset, reset
inst buffer_1 of TLBuffer_7
connect buffer_1.clock, clock
connect buffer_1.reset, reset
wire tlOtherMastersNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}
invalidate tlOtherMastersNodeOut.e.bits.sink
invalidate tlOtherMastersNodeOut.e.valid
invalidate tlOtherMastersNodeOut.e.ready
invalidate tlOtherMastersNodeOut.d.bits.corrupt
invalidate tlOtherMastersNodeOut.d.bits.data
invalidate tlOtherMastersNodeOut.d.bits.denied
invalidate tlOtherMastersNodeOut.d.bits.sink
invalidate tlOtherMastersNodeOut.d.bits.source
invalidate tlOtherMastersNodeOut.d.bits.size
invalidate tlOtherMastersNodeOut.d.bits.param
invalidate tlOtherMastersNodeOut.d.bits.opcode
invalidate tlOtherMastersNodeOut.d.valid
invalidate tlOtherMastersNodeOut.d.ready
invalidate tlOtherMastersNodeOut.c.bits.corrupt
invalidate tlOtherMastersNodeOut.c.bits.data
invalidate tlOtherMastersNodeOut.c.bits.address
invalidate tlOtherMastersNodeOut.c.bits.source
invalidate tlOtherMastersNodeOut.c.bits.size
invalidate tlOtherMastersNodeOut.c.bits.param
invalidate tlOtherMastersNodeOut.c.bits.opcode
invalidate tlOtherMastersNodeOut.c.valid
invalidate tlOtherMastersNodeOut.c.ready
invalidate tlOtherMastersNodeOut.b.bits.corrupt
invalidate tlOtherMastersNodeOut.b.bits.data
invalidate tlOtherMastersNodeOut.b.bits.mask
invalidate tlOtherMastersNodeOut.b.bits.address
invalidate tlOtherMastersNodeOut.b.bits.source
invalidate tlOtherMastersNodeOut.b.bits.size
invalidate tlOtherMastersNodeOut.b.bits.param
invalidate tlOtherMastersNodeOut.b.bits.opcode
invalidate tlOtherMastersNodeOut.b.valid
invalidate tlOtherMastersNodeOut.b.ready
invalidate tlOtherMastersNodeOut.a.bits.corrupt
invalidate tlOtherMastersNodeOut.a.bits.data
invalidate tlOtherMastersNodeOut.a.bits.mask
invalidate tlOtherMastersNodeOut.a.bits.address
invalidate tlOtherMastersNodeOut.a.bits.source
invalidate tlOtherMastersNodeOut.a.bits.size
invalidate tlOtherMastersNodeOut.a.bits.param
invalidate tlOtherMastersNodeOut.a.bits.opcode
invalidate tlOtherMastersNodeOut.a.valid
invalidate tlOtherMastersNodeOut.a.ready
wire tlOtherMastersNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}
invalidate tlOtherMastersNodeIn.e.bits.sink
invalidate tlOtherMastersNodeIn.e.valid
invalidate tlOtherMastersNodeIn.e.ready
invalidate tlOtherMastersNodeIn.d.bits.corrupt
invalidate tlOtherMastersNodeIn.d.bits.data
invalidate tlOtherMastersNodeIn.d.bits.denied
invalidate tlOtherMastersNodeIn.d.bits.sink
invalidate tlOtherMastersNodeIn.d.bits.source
invalidate tlOtherMastersNodeIn.d.bits.size
invalidate tlOtherMastersNodeIn.d.bits.param
invalidate tlOtherMastersNodeIn.d.bits.opcode
invalidate tlOtherMastersNodeIn.d.valid
invalidate tlOtherMastersNodeIn.d.ready
invalidate tlOtherMastersNodeIn.c.bits.corrupt
invalidate tlOtherMastersNodeIn.c.bits.data
invalidate tlOtherMastersNodeIn.c.bits.address
invalidate tlOtherMastersNodeIn.c.bits.source
invalidate tlOtherMastersNodeIn.c.bits.size
invalidate tlOtherMastersNodeIn.c.bits.param
invalidate tlOtherMastersNodeIn.c.bits.opcode
invalidate tlOtherMastersNodeIn.c.valid
invalidate tlOtherMastersNodeIn.c.ready
invalidate tlOtherMastersNodeIn.b.bits.corrupt
invalidate tlOtherMastersNodeIn.b.bits.data
invalidate tlOtherMastersNodeIn.b.bits.mask
invalidate tlOtherMastersNodeIn.b.bits.address
invalidate tlOtherMastersNodeIn.b.bits.source
invalidate tlOtherMastersNodeIn.b.bits.size
invalidate tlOtherMastersNodeIn.b.bits.param
invalidate tlOtherMastersNodeIn.b.bits.opcode
invalidate tlOtherMastersNodeIn.b.valid
invalidate tlOtherMastersNodeIn.b.ready
invalidate tlOtherMastersNodeIn.a.bits.corrupt
invalidate tlOtherMastersNodeIn.a.bits.data
invalidate tlOtherMastersNodeIn.a.bits.mask
invalidate tlOtherMastersNodeIn.a.bits.address
invalidate tlOtherMastersNodeIn.a.bits.source
invalidate tlOtherMastersNodeIn.a.bits.size
invalidate tlOtherMastersNodeIn.a.bits.param
invalidate tlOtherMastersNodeIn.a.bits.opcode
invalidate tlOtherMastersNodeIn.a.valid
invalidate tlOtherMastersNodeIn.a.ready
connect tlOtherMastersNodeOut, tlOtherMastersNodeIn
wire hartIdSinkNodeIn : UInt<2>
invalidate hartIdSinkNodeIn
wire hartidOut : UInt<2>
invalidate hartidOut
wire hartidIn : UInt<2>
invalidate hartidIn
connect hartidOut, hartidIn
wire resetVectorSinkNodeIn : UInt<32>
invalidate resetVectorSinkNodeIn
wire reset_vectorOut : UInt<32>
invalidate reset_vectorOut
wire reset_vectorIn : UInt<32>
invalidate reset_vectorIn
connect reset_vectorOut, reset_vectorIn
wire traceSourceNodeOut : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[3], time : UInt<64>, custom : { rob_empty : UInt<1>}}
invalidate traceSourceNodeOut.custom.rob_empty
invalidate traceSourceNodeOut.time
invalidate traceSourceNodeOut.insns[0].tval
invalidate traceSourceNodeOut.insns[0].cause
invalidate traceSourceNodeOut.insns[0].interrupt
invalidate traceSourceNodeOut.insns[0].exception
invalidate traceSourceNodeOut.insns[0].priv
invalidate traceSourceNodeOut.insns[0].insn
invalidate traceSourceNodeOut.insns[0].iaddr
invalidate traceSourceNodeOut.insns[0].valid
invalidate traceSourceNodeOut.insns[1].tval
invalidate traceSourceNodeOut.insns[1].cause
invalidate traceSourceNodeOut.insns[1].interrupt
invalidate traceSourceNodeOut.insns[1].exception
invalidate traceSourceNodeOut.insns[1].priv
invalidate traceSourceNodeOut.insns[1].insn
invalidate traceSourceNodeOut.insns[1].iaddr
invalidate traceSourceNodeOut.insns[1].valid
invalidate traceSourceNodeOut.insns[2].tval
invalidate traceSourceNodeOut.insns[2].cause
invalidate traceSourceNodeOut.insns[2].interrupt
invalidate traceSourceNodeOut.insns[2].exception
invalidate traceSourceNodeOut.insns[2].priv
invalidate traceSourceNodeOut.insns[2].insn
invalidate traceSourceNodeOut.insns[2].iaddr
invalidate traceSourceNodeOut.insns[2].valid
wire traceCoreSourceNodeOut : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>}
invalidate traceCoreSourceNodeOut.cause
invalidate traceCoreSourceNodeOut.tval
invalidate traceCoreSourceNodeOut.priv
invalidate traceCoreSourceNodeOut.group[0].ilastsize
invalidate traceCoreSourceNodeOut.group[0].itype
invalidate traceCoreSourceNodeOut.group[0].iaddr
invalidate traceCoreSourceNodeOut.group[0].iretire
wire bundleIn_x_sourceOpt : { enable : UInt<1>, stall : UInt<1>}
connect bundleIn_x_sourceOpt.stall, UInt<1>(0h0)
connect bundleIn_x_sourceOpt.enable, UInt<1>(0h0)
wire traceAuxSinkNodeIn : { enable : UInt<1>, stall : UInt<1>}
invalidate traceAuxSinkNodeIn.stall
invalidate traceAuxSinkNodeIn.enable
wire bpwatchSourceNodeOut : { valid : UInt<1>[3], rvalid : UInt<1>[3], wvalid : UInt<1>[3], ivalid : UInt<1>[3], action : UInt<3>}[0]
wire int_localOut : UInt<1>[1]
invalidate int_localOut[0]
wire x1_int_localOut : UInt<1>[2]
invalidate x1_int_localOut[0]
invalidate x1_int_localOut[1]
wire x1_int_localOut_1 : UInt<1>[1]
invalidate x1_int_localOut_1[0]
wire x1_int_localOut_2 : UInt<1>[1]
invalidate x1_int_localOut_2[0]
wire int_localIn : UInt<1>[1]
invalidate int_localIn[0]
wire x1_int_localIn : UInt<1>[2]
invalidate x1_int_localIn[0]
invalidate x1_int_localIn[1]
wire x1_int_localIn_1 : UInt<1>[1]
invalidate x1_int_localIn_1[0]
wire x1_int_localIn_2 : UInt<1>[1]
invalidate x1_int_localIn_2[0]
connect int_localOut, int_localIn
connect x1_int_localOut, x1_int_localIn
connect x1_int_localOut_1, x1_int_localIn_1
connect x1_int_localOut_2, x1_int_localIn_2
wire intSinkNodeIn : UInt<1>[5]
invalidate intSinkNodeIn[0]
invalidate intSinkNodeIn[1]
invalidate intSinkNodeIn[2]
invalidate intSinkNodeIn[3]
invalidate intSinkNodeIn[4]
wire haltNodeOut : UInt<1>[1]
invalidate haltNodeOut[0]
wire ceaseNodeOut : UInt<1>[1]
invalidate ceaseNodeOut[0]
wire wfiNodeOut : UInt<1>[1]
invalidate wfiNodeOut[0]
wire masterNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}
invalidate masterNodeOut.e.bits.sink
invalidate masterNodeOut.e.valid
invalidate masterNodeOut.e.ready
invalidate masterNodeOut.d.bits.corrupt
invalidate masterNodeOut.d.bits.data
invalidate masterNodeOut.d.bits.denied
invalidate masterNodeOut.d.bits.sink
invalidate masterNodeOut.d.bits.source
invalidate masterNodeOut.d.bits.size
invalidate masterNodeOut.d.bits.param
invalidate masterNodeOut.d.bits.opcode
invalidate masterNodeOut.d.valid
invalidate masterNodeOut.d.ready
invalidate masterNodeOut.c.bits.corrupt
invalidate masterNodeOut.c.bits.data
invalidate masterNodeOut.c.bits.address
invalidate masterNodeOut.c.bits.source
invalidate masterNodeOut.c.bits.size
invalidate masterNodeOut.c.bits.param
invalidate masterNodeOut.c.bits.opcode
invalidate masterNodeOut.c.valid
invalidate masterNodeOut.c.ready
invalidate masterNodeOut.b.bits.corrupt
invalidate masterNodeOut.b.bits.data
invalidate masterNodeOut.b.bits.mask
invalidate masterNodeOut.b.bits.address
invalidate masterNodeOut.b.bits.source
invalidate masterNodeOut.b.bits.size
invalidate masterNodeOut.b.bits.param
invalidate masterNodeOut.b.bits.opcode
invalidate masterNodeOut.b.valid
invalidate masterNodeOut.b.ready
invalidate masterNodeOut.a.bits.corrupt
invalidate masterNodeOut.a.bits.data
invalidate masterNodeOut.a.bits.mask
invalidate masterNodeOut.a.bits.address
invalidate masterNodeOut.a.bits.source
invalidate masterNodeOut.a.bits.size
invalidate masterNodeOut.a.bits.param
invalidate masterNodeOut.a.bits.opcode
invalidate masterNodeOut.a.valid
invalidate masterNodeOut.a.ready
wire masterNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}
invalidate masterNodeIn.e.bits.sink
invalidate masterNodeIn.e.valid
invalidate masterNodeIn.e.ready
invalidate masterNodeIn.d.bits.corrupt
invalidate masterNodeIn.d.bits.data
invalidate masterNodeIn.d.bits.denied
invalidate masterNodeIn.d.bits.sink
invalidate masterNodeIn.d.bits.source
invalidate masterNodeIn.d.bits.size
invalidate masterNodeIn.d.bits.param
invalidate masterNodeIn.d.bits.opcode
invalidate masterNodeIn.d.valid
invalidate masterNodeIn.d.ready
invalidate masterNodeIn.c.bits.corrupt
invalidate masterNodeIn.c.bits.data
invalidate masterNodeIn.c.bits.address
invalidate masterNodeIn.c.bits.source
invalidate masterNodeIn.c.bits.size
invalidate masterNodeIn.c.bits.param
invalidate masterNodeIn.c.bits.opcode
invalidate masterNodeIn.c.valid
invalidate masterNodeIn.c.ready
invalidate masterNodeIn.b.bits.corrupt
invalidate masterNodeIn.b.bits.data
invalidate masterNodeIn.b.bits.mask
invalidate masterNodeIn.b.bits.address
invalidate masterNodeIn.b.bits.source
invalidate masterNodeIn.b.bits.size
invalidate masterNodeIn.b.bits.param
invalidate masterNodeIn.b.bits.opcode
invalidate masterNodeIn.b.valid
invalidate masterNodeIn.b.ready
invalidate masterNodeIn.a.bits.corrupt
invalidate masterNodeIn.a.bits.data
invalidate masterNodeIn.a.bits.mask
invalidate masterNodeIn.a.bits.address
invalidate masterNodeIn.a.bits.source
invalidate masterNodeIn.a.bits.size
invalidate masterNodeIn.a.bits.param
invalidate masterNodeIn.a.bits.opcode
invalidate masterNodeIn.a.valid
invalidate masterNodeIn.a.ready
connect masterNodeOut, masterNodeIn
wire dCacheTapOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}
invalidate dCacheTapOut.e.bits.sink
invalidate dCacheTapOut.e.valid
invalidate dCacheTapOut.e.ready
invalidate dCacheTapOut.d.bits.corrupt
invalidate dCacheTapOut.d.bits.data
invalidate dCacheTapOut.d.bits.denied
invalidate dCacheTapOut.d.bits.sink
invalidate dCacheTapOut.d.bits.source
invalidate dCacheTapOut.d.bits.size
invalidate dCacheTapOut.d.bits.param
invalidate dCacheTapOut.d.bits.opcode
invalidate dCacheTapOut.d.valid
invalidate dCacheTapOut.d.ready
invalidate dCacheTapOut.c.bits.corrupt
invalidate dCacheTapOut.c.bits.data
invalidate dCacheTapOut.c.bits.address
invalidate dCacheTapOut.c.bits.source
invalidate dCacheTapOut.c.bits.size
invalidate dCacheTapOut.c.bits.param
invalidate dCacheTapOut.c.bits.opcode
invalidate dCacheTapOut.c.valid
invalidate dCacheTapOut.c.ready
invalidate dCacheTapOut.b.bits.corrupt
invalidate dCacheTapOut.b.bits.data
invalidate dCacheTapOut.b.bits.mask
invalidate dCacheTapOut.b.bits.address
invalidate dCacheTapOut.b.bits.source
invalidate dCacheTapOut.b.bits.size
invalidate dCacheTapOut.b.bits.param
invalidate dCacheTapOut.b.bits.opcode
invalidate dCacheTapOut.b.valid
invalidate dCacheTapOut.b.ready
invalidate dCacheTapOut.a.bits.corrupt
invalidate dCacheTapOut.a.bits.data
invalidate dCacheTapOut.a.bits.mask
invalidate dCacheTapOut.a.bits.address
invalidate dCacheTapOut.a.bits.source
invalidate dCacheTapOut.a.bits.size
invalidate dCacheTapOut.a.bits.param
invalidate dCacheTapOut.a.bits.opcode
invalidate dCacheTapOut.a.valid
invalidate dCacheTapOut.a.ready
wire dCacheTapIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}
invalidate dCacheTapIn.e.bits.sink
invalidate dCacheTapIn.e.valid
invalidate dCacheTapIn.e.ready
invalidate dCacheTapIn.d.bits.corrupt
invalidate dCacheTapIn.d.bits.data
invalidate dCacheTapIn.d.bits.denied
invalidate dCacheTapIn.d.bits.sink
invalidate dCacheTapIn.d.bits.source
invalidate dCacheTapIn.d.bits.size
invalidate dCacheTapIn.d.bits.param
invalidate dCacheTapIn.d.bits.opcode
invalidate dCacheTapIn.d.valid
invalidate dCacheTapIn.d.ready
invalidate dCacheTapIn.c.bits.corrupt
invalidate dCacheTapIn.c.bits.data
invalidate dCacheTapIn.c.bits.address
invalidate dCacheTapIn.c.bits.source
invalidate dCacheTapIn.c.bits.size
invalidate dCacheTapIn.c.bits.param
invalidate dCacheTapIn.c.bits.opcode
invalidate dCacheTapIn.c.valid
invalidate dCacheTapIn.c.ready
invalidate dCacheTapIn.b.bits.corrupt
invalidate dCacheTapIn.b.bits.data
invalidate dCacheTapIn.b.bits.mask
invalidate dCacheTapIn.b.bits.address
invalidate dCacheTapIn.b.bits.source
invalidate dCacheTapIn.b.bits.size
invalidate dCacheTapIn.b.bits.param
invalidate dCacheTapIn.b.bits.opcode
invalidate dCacheTapIn.b.valid
invalidate dCacheTapIn.b.ready
invalidate dCacheTapIn.a.bits.corrupt
invalidate dCacheTapIn.a.bits.data
invalidate dCacheTapIn.a.bits.mask
invalidate dCacheTapIn.a.bits.address
invalidate dCacheTapIn.a.bits.source
invalidate dCacheTapIn.a.bits.size
invalidate dCacheTapIn.a.bits.param
invalidate dCacheTapIn.a.bits.opcode
invalidate dCacheTapIn.a.valid
invalidate dCacheTapIn.a.ready
connect dCacheTapOut, dCacheTapIn
connect masterNodeIn, tlOtherMastersNodeOut
connect tlOtherMastersNodeIn.e.bits, tlMasterXbar.auto.anon_out.e.bits
connect tlOtherMastersNodeIn.e.valid, tlMasterXbar.auto.anon_out.e.valid
connect tlMasterXbar.auto.anon_out.e.ready, tlOtherMastersNodeIn.e.ready
connect tlMasterXbar.auto.anon_out.d, tlOtherMastersNodeIn.d
connect tlOtherMastersNodeIn.c.bits, tlMasterXbar.auto.anon_out.c.bits
connect tlOtherMastersNodeIn.c.valid, tlMasterXbar.auto.anon_out.c.valid
connect tlMasterXbar.auto.anon_out.c.ready, tlOtherMastersNodeIn.c.ready
connect tlMasterXbar.auto.anon_out.b, tlOtherMastersNodeIn.b
connect tlOtherMastersNodeIn.a.bits, tlMasterXbar.auto.anon_out.a.bits
connect tlOtherMastersNodeIn.a.valid, tlMasterXbar.auto.anon_out.a.valid
connect tlMasterXbar.auto.anon_out.a.ready, tlOtherMastersNodeIn.a.ready
connect intSinkNodeIn, intXbar.auto.anon_out
connect hartIdSinkNodeIn, broadcast.auto.out
connect broadcast.auto.in, hartidOut
connect resetVectorSinkNodeIn, broadcast_1.auto.out_0
connect frontend.auto.reset_vector_sink_in, broadcast_1.auto.out_1
connect broadcast_1.auto.in, reset_vectorOut
connect traceAuxSinkNodeIn, nexus_1.auto.out
connect intXbar.auto.anon_in_0[0], int_localOut[0]
connect intXbar.auto.anon_in_1[0], x1_int_localOut[0]
connect intXbar.auto.anon_in_1[1], x1_int_localOut[1]
connect intXbar.auto.anon_in_2[0], x1_int_localOut_1[0]
connect intXbar.auto.anon_in_3[0], x1_int_localOut_2[0]
connect buffer.auto.in, masterNodeOut
connect tlMasterXbar.auto.anon_in_0, dCacheTapOut
connect dCacheTapIn.e.bits, widget.auto.anon_out.e.bits
connect dCacheTapIn.e.valid, widget.auto.anon_out.e.valid
connect widget.auto.anon_out.e.ready, dCacheTapIn.e.ready
connect widget.auto.anon_out.d, dCacheTapIn.d
connect dCacheTapIn.c.bits, widget.auto.anon_out.c.bits
connect dCacheTapIn.c.valid, widget.auto.anon_out.c.valid
connect widget.auto.anon_out.c.ready, dCacheTapIn.c.ready
connect widget.auto.anon_out.b, dCacheTapIn.b
connect dCacheTapIn.a.bits, widget.auto.anon_out.a.bits
connect dCacheTapIn.a.valid, widget.auto.anon_out.a.valid
connect widget.auto.anon_out.a.ready, dCacheTapIn.a.ready
connect widget.auto.anon_in, dcache.auto.out
connect widget_1.auto.anon_in, frontend.auto.icache_master_out
connect tlMasterXbar.auto.anon_in_1, widget_1.auto.anon_out
connect hartidIn, auto.hartid_in
connect reset_vectorIn, auto.reset_vector_in
connect auto.trace_source_out, traceSourceNodeOut
connect auto.trace_core_source_out, traceCoreSourceNodeOut
connect int_localIn, auto.int_local_in_0
connect x1_int_localIn, auto.int_local_in_1
connect x1_int_localIn_1, auto.int_local_in_2
connect x1_int_localIn_2, auto.int_local_in_3
connect auto.halt_out, haltNodeOut
connect auto.cease_out, ceaseNodeOut
connect auto.wfi_out, wfiNodeOut
connect auto.buffer_out.e.bits, buffer.auto.out.e.bits
connect auto.buffer_out.e.valid, buffer.auto.out.e.valid
connect buffer.auto.out.e.ready, auto.buffer_out.e.ready
connect buffer.auto.out.d, auto.buffer_out.d
connect auto.buffer_out.c.bits, buffer.auto.out.c.bits
connect auto.buffer_out.c.valid, buffer.auto.out.c.valid
connect buffer.auto.out.c.ready, auto.buffer_out.c.ready
connect buffer.auto.out.b, auto.buffer_out.b
connect auto.buffer_out.a.bits, buffer.auto.out.a.bits
connect auto.buffer_out.a.valid, buffer.auto.out.a.valid
connect buffer.auto.out.a.ready, auto.buffer_out.a.ready
inst core of BoomCore_1
connect core.clock, clock
connect core.reset, reset
inst lsu of LSU_1
connect lsu.clock, clock
connect lsu.reset, reset
connect wfiNodeOut[0], UInt<1>(0h0)
connect core.io.interrupts.debug, intSinkNodeIn[0]
connect core.io.interrupts.msip, intSinkNodeIn[1]
connect core.io.interrupts.mtip, intSinkNodeIn[2]
connect core.io.interrupts.meip, intSinkNodeIn[3]
connect core.io.interrupts.seip, intSinkNodeIn[4]
connect traceSourceNodeOut, core.io.trace
connect core.io.hartid, hartIdSinkNodeIn
connect frontend.io.cpu, core.io.ifu
connect core.io.lsu, lsu.io.core
invalidate core.io.rocc.exception
invalidate core.io.rocc.interrupt
invalidate core.io.rocc.busy
invalidate core.io.rocc.mem.clock_enabled
invalidate core.io.rocc.mem.keep_clock_enabled
invalidate core.io.rocc.mem.perf.storeBufferEmptyAfterStore
invalidate core.io.rocc.mem.perf.storeBufferEmptyAfterLoad
invalidate core.io.rocc.mem.perf.canAcceptLoadThenLoad
invalidate core.io.rocc.mem.perf.canAcceptStoreThenRMW
invalidate core.io.rocc.mem.perf.canAcceptStoreThenLoad
invalidate core.io.rocc.mem.perf.blocked
invalidate core.io.rocc.mem.perf.tlbMiss
invalidate core.io.rocc.mem.perf.grant
invalidate core.io.rocc.mem.perf.release
invalidate core.io.rocc.mem.perf.acquire
invalidate core.io.rocc.mem.store_pending
invalidate core.io.rocc.mem.ordered
invalidate core.io.rocc.mem.s2_gpa_is_pte
invalidate core.io.rocc.mem.s2_gpa
invalidate core.io.rocc.mem.s2_xcpt.ae.st
invalidate core.io.rocc.mem.s2_xcpt.ae.ld
invalidate core.io.rocc.mem.s2_xcpt.gf.st
invalidate core.io.rocc.mem.s2_xcpt.gf.ld
invalidate core.io.rocc.mem.s2_xcpt.pf.st
invalidate core.io.rocc.mem.s2_xcpt.pf.ld
invalidate core.io.rocc.mem.s2_xcpt.ma.st
invalidate core.io.rocc.mem.s2_xcpt.ma.ld
invalidate core.io.rocc.mem.replay_next
invalidate core.io.rocc.mem.resp.bits.store_data
invalidate core.io.rocc.mem.resp.bits.data_raw
invalidate core.io.rocc.mem.resp.bits.data_word_bypass
invalidate core.io.rocc.mem.resp.bits.has_data
invalidate core.io.rocc.mem.resp.bits.replay
invalidate core.io.rocc.mem.resp.bits.mask
invalidate core.io.rocc.mem.resp.bits.data
invalidate core.io.rocc.mem.resp.bits.dv
invalidate core.io.rocc.mem.resp.bits.dprv
invalidate core.io.rocc.mem.resp.bits.signed
invalidate core.io.rocc.mem.resp.bits.size
invalidate core.io.rocc.mem.resp.bits.cmd
invalidate core.io.rocc.mem.resp.bits.tag
invalidate core.io.rocc.mem.resp.bits.addr
invalidate core.io.rocc.mem.resp.valid
invalidate core.io.rocc.mem.s2_paddr
invalidate core.io.rocc.mem.s2_uncached
invalidate core.io.rocc.mem.s2_kill
invalidate core.io.rocc.mem.s2_nack_cause_raw
invalidate core.io.rocc.mem.s2_nack
invalidate core.io.rocc.mem.s1_data.mask
invalidate core.io.rocc.mem.s1_data.data
invalidate core.io.rocc.mem.s1_kill
invalidate core.io.rocc.mem.req.bits.mask
invalidate core.io.rocc.mem.req.bits.data
invalidate core.io.rocc.mem.req.bits.no_xcpt
invalidate core.io.rocc.mem.req.bits.no_alloc
invalidate core.io.rocc.mem.req.bits.no_resp
invalidate core.io.rocc.mem.req.bits.phys
invalidate core.io.rocc.mem.req.bits.dv
invalidate core.io.rocc.mem.req.bits.dprv
invalidate core.io.rocc.mem.req.bits.signed
invalidate core.io.rocc.mem.req.bits.size
invalidate core.io.rocc.mem.req.bits.cmd
invalidate core.io.rocc.mem.req.bits.tag
invalidate core.io.rocc.mem.req.bits.addr
invalidate core.io.rocc.mem.req.valid
invalidate core.io.rocc.mem.req.ready
invalidate core.io.rocc.resp.bits.data
invalidate core.io.rocc.resp.bits.rd
invalidate core.io.rocc.resp.valid
invalidate core.io.rocc.resp.ready
invalidate core.io.rocc.cmd.bits.status.uie
invalidate core.io.rocc.cmd.bits.status.sie
invalidate core.io.rocc.cmd.bits.status.hie
invalidate core.io.rocc.cmd.bits.status.mie
invalidate core.io.rocc.cmd.bits.status.upie
invalidate core.io.rocc.cmd.bits.status.spie
invalidate core.io.rocc.cmd.bits.status.ube
invalidate core.io.rocc.cmd.bits.status.mpie
invalidate core.io.rocc.cmd.bits.status.spp
invalidate core.io.rocc.cmd.bits.status.vs
invalidate core.io.rocc.cmd.bits.status.mpp
invalidate core.io.rocc.cmd.bits.status.fs
invalidate core.io.rocc.cmd.bits.status.xs
invalidate core.io.rocc.cmd.bits.status.mprv
invalidate core.io.rocc.cmd.bits.status.sum
invalidate core.io.rocc.cmd.bits.status.mxr
invalidate core.io.rocc.cmd.bits.status.tvm
invalidate core.io.rocc.cmd.bits.status.tw
invalidate core.io.rocc.cmd.bits.status.tsr
invalidate core.io.rocc.cmd.bits.status.zero1
invalidate core.io.rocc.cmd.bits.status.sd_rv32
invalidate core.io.rocc.cmd.bits.status.uxl
invalidate core.io.rocc.cmd.bits.status.sxl
invalidate core.io.rocc.cmd.bits.status.sbe
invalidate core.io.rocc.cmd.bits.status.mbe
invalidate core.io.rocc.cmd.bits.status.gva
invalidate core.io.rocc.cmd.bits.status.mpv
invalidate core.io.rocc.cmd.bits.status.zero2
invalidate core.io.rocc.cmd.bits.status.sd
invalidate core.io.rocc.cmd.bits.status.v
invalidate core.io.rocc.cmd.bits.status.prv
invalidate core.io.rocc.cmd.bits.status.dv
invalidate core.io.rocc.cmd.bits.status.dprv
invalidate core.io.rocc.cmd.bits.status.isa
invalidate core.io.rocc.cmd.bits.status.wfi
invalidate core.io.rocc.cmd.bits.status.cease
invalidate core.io.rocc.cmd.bits.status.debug
invalidate core.io.rocc.cmd.bits.rs2
invalidate core.io.rocc.cmd.bits.rs1
invalidate core.io.rocc.cmd.bits.inst.opcode
invalidate core.io.rocc.cmd.bits.inst.rd
invalidate core.io.rocc.cmd.bits.inst.xs2
invalidate core.io.rocc.cmd.bits.inst.xs1
invalidate core.io.rocc.cmd.bits.inst.xd
invalidate core.io.rocc.cmd.bits.inst.rs1
invalidate core.io.rocc.cmd.bits.inst.rs2
invalidate core.io.rocc.cmd.bits.inst.funct
invalidate core.io.rocc.cmd.valid
invalidate core.io.rocc.cmd.ready
inst ptw of PTW_3
connect ptw.clock, clock
connect ptw.reset, reset
connect core.io.ptw, ptw.io.dpath
connect ptw.io.requestor[0], lsu.io.ptw
connect ptw.io.requestor[1], frontend.io.ptw
connect ptw.io.requestor[2], core.io.ptw_tlb
inst hellaCacheArb of HellaCacheArbiter_3
connect hellaCacheArb.clock, clock
connect hellaCacheArb.reset, reset
connect hellaCacheArb.io.requestor[0], ptw.io.mem
connect lsu.io.hellacache, hellaCacheArb.io.mem
connect dcache.io.lsu, lsu.io.dmem | module BoomTile_1( // @[tile.scala:155:7]
input clock, // @[tile.scala:155:7]
input reset, // @[tile.scala:155:7]
input auto_buffer_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_buffer_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_buffer_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_buffer_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_buffer_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_buffer_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_buffer_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [15:0] auto_buffer_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_buffer_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_buffer_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_buffer_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_buffer_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_buffer_out_b_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_buffer_out_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_buffer_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input [15:0] auto_buffer_out_b_bits_mask, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_buffer_out_b_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_buffer_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_buffer_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_buffer_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_buffer_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_buffer_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_buffer_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_buffer_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_buffer_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_buffer_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_buffer_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_buffer_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_buffer_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_buffer_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_buffer_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_e_ready, // @[LazyModuleImp.scala:107:25]
output auto_buffer_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_buffer_out_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_int_local_in_3_0, // @[LazyModuleImp.scala:107:25]
input auto_int_local_in_2_0, // @[LazyModuleImp.scala:107:25]
input auto_int_local_in_1_0, // @[LazyModuleImp.scala:107:25]
input auto_int_local_in_1_1, // @[LazyModuleImp.scala:107:25]
input auto_int_local_in_0_0, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_trace_source_out_time, // @[LazyModuleImp.scala:107:25]
output auto_trace_source_out_custom_rob_empty, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_hartid_in // @[LazyModuleImp.scala:107:25]
);
wire dCacheTapOut_e_ready; // @[MixedNode.scala:542:17]
wire dCacheTapOut_d_valid; // @[MixedNode.scala:542:17]
wire dCacheTapOut_d_bits_corrupt; // @[MixedNode.scala:542:17]
wire [127:0] dCacheTapOut_d_bits_data; // @[MixedNode.scala:542:17]
wire dCacheTapOut_d_bits_denied; // @[MixedNode.scala:542:17]
wire [3:0] dCacheTapOut_d_bits_sink; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapOut_d_bits_source; // @[MixedNode.scala:542:17]
wire [3:0] dCacheTapOut_d_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] dCacheTapOut_d_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapOut_d_bits_opcode; // @[MixedNode.scala:542:17]
wire dCacheTapOut_c_ready; // @[MixedNode.scala:542:17]
wire dCacheTapOut_b_valid; // @[MixedNode.scala:542:17]
wire dCacheTapOut_b_bits_corrupt; // @[MixedNode.scala:542:17]
wire [127:0] dCacheTapOut_b_bits_data; // @[MixedNode.scala:542:17]
wire [15:0] dCacheTapOut_b_bits_mask; // @[MixedNode.scala:542:17]
wire [31:0] dCacheTapOut_b_bits_address; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapOut_b_bits_source; // @[MixedNode.scala:542:17]
wire [3:0] dCacheTapOut_b_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] dCacheTapOut_b_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapOut_b_bits_opcode; // @[MixedNode.scala:542:17]
wire dCacheTapOut_a_ready; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_e_valid; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_e_ready; // @[MixedNode.scala:542:17]
wire [3:0] tlOtherMastersNodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_d_valid; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_d_ready; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17]
wire [127:0] tlOtherMastersNodeOut_d_bits_data; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_d_bits_denied; // @[MixedNode.scala:542:17]
wire [3:0] tlOtherMastersNodeOut_d_bits_sink; // @[MixedNode.scala:542:17]
wire [3:0] tlOtherMastersNodeOut_d_bits_source; // @[MixedNode.scala:542:17]
wire [3:0] tlOtherMastersNodeOut_d_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] tlOtherMastersNodeOut_d_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] tlOtherMastersNodeOut_d_bits_opcode; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_c_valid; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_c_ready; // @[MixedNode.scala:542:17]
wire [127:0] tlOtherMastersNodeOut_c_bits_data; // @[MixedNode.scala:542:17]
wire [31:0] tlOtherMastersNodeOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [3:0] tlOtherMastersNodeOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [3:0] tlOtherMastersNodeOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] tlOtherMastersNodeOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] tlOtherMastersNodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_b_valid; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_b_ready; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_b_bits_corrupt; // @[MixedNode.scala:542:17]
wire [127:0] tlOtherMastersNodeOut_b_bits_data; // @[MixedNode.scala:542:17]
wire [15:0] tlOtherMastersNodeOut_b_bits_mask; // @[MixedNode.scala:542:17]
wire [31:0] tlOtherMastersNodeOut_b_bits_address; // @[MixedNode.scala:542:17]
wire [3:0] tlOtherMastersNodeOut_b_bits_source; // @[MixedNode.scala:542:17]
wire [3:0] tlOtherMastersNodeOut_b_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] tlOtherMastersNodeOut_b_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] tlOtherMastersNodeOut_b_bits_opcode; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_a_valid; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_a_ready; // @[MixedNode.scala:542:17]
wire [127:0] tlOtherMastersNodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire [15:0] tlOtherMastersNodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [31:0] tlOtherMastersNodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [3:0] tlOtherMastersNodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [3:0] tlOtherMastersNodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] tlOtherMastersNodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] tlOtherMastersNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire buffer_auto_in_e_valid; // @[Buffer.scala:40:9]
wire buffer_auto_in_e_ready; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_e_bits_sink; // @[Buffer.scala:40:9]
wire buffer_auto_in_d_valid; // @[Buffer.scala:40:9]
wire buffer_auto_in_d_ready; // @[Buffer.scala:40:9]
wire buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9]
wire [127:0] buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9]
wire buffer_auto_in_d_bits_denied; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_d_bits_sink; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_in_d_bits_param; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9]
wire buffer_auto_in_c_valid; // @[Buffer.scala:40:9]
wire buffer_auto_in_c_ready; // @[Buffer.scala:40:9]
wire [127:0] buffer_auto_in_c_bits_data; // @[Buffer.scala:40:9]
wire [31:0] buffer_auto_in_c_bits_address; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_c_bits_source; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_c_bits_size; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_c_bits_param; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_c_bits_opcode; // @[Buffer.scala:40:9]
wire buffer_auto_in_b_valid; // @[Buffer.scala:40:9]
wire buffer_auto_in_b_ready; // @[Buffer.scala:40:9]
wire buffer_auto_in_b_bits_corrupt; // @[Buffer.scala:40:9]
wire [127:0] buffer_auto_in_b_bits_data; // @[Buffer.scala:40:9]
wire [15:0] buffer_auto_in_b_bits_mask; // @[Buffer.scala:40:9]
wire [31:0] buffer_auto_in_b_bits_address; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_b_bits_source; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_b_bits_size; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_in_b_bits_param; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_b_bits_opcode; // @[Buffer.scala:40:9]
wire buffer_auto_in_a_valid; // @[Buffer.scala:40:9]
wire buffer_auto_in_a_ready; // @[Buffer.scala:40:9]
wire [127:0] buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire [15:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [31:0] buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire widget_1_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [127:0] widget_1_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [1:0] widget_1_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [31:0] widget_1_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_e_valid; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_e_ready; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_out_e_bits_sink; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [127:0] widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [1:0] widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_c_valid; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_c_ready; // @[WidthWidget.scala:27:9]
wire [127:0] widget_auto_anon_out_c_bits_data; // @[WidthWidget.scala:27:9]
wire [31:0] widget_auto_anon_out_c_bits_address; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_c_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_out_c_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_c_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_c_bits_opcode; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_b_valid; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_b_ready; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_b_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [127:0] widget_auto_anon_out_b_bits_data; // @[WidthWidget.scala:27:9]
wire [15:0] widget_auto_anon_out_b_bits_mask; // @[WidthWidget.scala:27:9]
wire [31:0] widget_auto_anon_out_b_bits_address; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_b_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_out_b_bits_size; // @[WidthWidget.scala:27:9]
wire [1:0] widget_auto_anon_out_b_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_b_bits_opcode; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire [127:0] widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9]
wire [15:0] widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [31:0] widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_e_valid; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_in_e_bits_sink; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_c_valid; // @[WidthWidget.scala:27:9]
wire [127:0] widget_auto_anon_in_c_bits_data; // @[WidthWidget.scala:27:9]
wire [31:0] widget_auto_anon_in_c_bits_address; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_c_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_in_c_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_c_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_c_bits_opcode; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_b_ready; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [127:0] widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire [15:0] widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [31:0] widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] broadcast_auto_in; // @[BundleBridgeNexus.scala:20:9]
wire _hellaCacheArb_io_requestor_0_req_ready; // @[tile.scala:243:29]
wire _hellaCacheArb_io_requestor_0_s2_nack; // @[tile.scala:243:29]
wire _hellaCacheArb_io_requestor_0_resp_valid; // @[tile.scala:243:29]
wire [39:0] _hellaCacheArb_io_requestor_0_resp_bits_addr; // @[tile.scala:243:29]
wire [63:0] _hellaCacheArb_io_requestor_0_resp_bits_data; // @[tile.scala:243:29]
wire _hellaCacheArb_io_requestor_0_s2_xcpt_ma_ld; // @[tile.scala:243:29]
wire _hellaCacheArb_io_requestor_0_s2_xcpt_ma_st; // @[tile.scala:243:29]
wire _hellaCacheArb_io_requestor_0_s2_xcpt_pf_ld; // @[tile.scala:243:29]
wire _hellaCacheArb_io_requestor_0_s2_xcpt_pf_st; // @[tile.scala:243:29]
wire _hellaCacheArb_io_requestor_0_s2_xcpt_gf_ld; // @[tile.scala:243:29]
wire _hellaCacheArb_io_requestor_0_s2_xcpt_gf_st; // @[tile.scala:243:29]
wire _hellaCacheArb_io_requestor_0_s2_xcpt_ae_ld; // @[tile.scala:243:29]
wire _hellaCacheArb_io_requestor_0_s2_xcpt_ae_st; // @[tile.scala:243:29]
wire _hellaCacheArb_io_requestor_0_store_pending; // @[tile.scala:243:29]
wire _hellaCacheArb_io_mem_req_valid; // @[tile.scala:243:29]
wire [39:0] _hellaCacheArb_io_mem_req_bits_addr; // @[tile.scala:243:29]
wire _hellaCacheArb_io_mem_req_bits_dv; // @[tile.scala:243:29]
wire _hellaCacheArb_io_mem_s1_kill; // @[tile.scala:243:29]
wire _ptw_io_requestor_0_req_ready; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_valid; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_ae_ptw; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_ae_final; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_pf; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_gf; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_hr; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_hw; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_hx; // @[tile.scala:237:20]
wire [9:0] _ptw_io_requestor_0_resp_bits_pte_reserved_for_future; // @[tile.scala:237:20]
wire [43:0] _ptw_io_requestor_0_resp_bits_pte_ppn; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_0_resp_bits_pte_reserved_for_software; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_pte_d; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_pte_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_pte_g; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_pte_u; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_pte_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_pte_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_pte_r; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_pte_v; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_0_resp_bits_level; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_homogeneous; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_gpa_valid; // @[tile.scala:237:20]
wire [38:0] _ptw_io_requestor_0_resp_bits_gpa_bits; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_gpa_is_pte; // @[tile.scala:237:20]
wire [3:0] _ptw_io_requestor_0_ptbr_mode; // @[tile.scala:237:20]
wire [43:0] _ptw_io_requestor_0_ptbr_ppn; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_debug; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_cease; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_wfi; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_0_status_dprv; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_dv; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_0_status_prv; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_v; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_sd; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_mpv; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_gva; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_tsr; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_tw; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_tvm; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_mxr; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_sum; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_mprv; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_0_status_fs; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_0_status_mpp; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_spp; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_mpie; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_spie; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_mie; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_sie; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_0_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_0_pmp_0_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_0_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_0_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_0_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_0_pmp_0_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_0_pmp_0_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_1_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_0_pmp_1_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_1_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_1_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_1_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_0_pmp_1_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_0_pmp_1_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_2_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_0_pmp_2_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_2_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_2_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_2_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_0_pmp_2_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_0_pmp_2_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_3_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_0_pmp_3_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_3_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_3_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_3_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_0_pmp_3_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_0_pmp_3_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_4_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_0_pmp_4_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_4_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_4_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_4_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_0_pmp_4_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_0_pmp_4_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_5_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_0_pmp_5_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_5_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_5_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_5_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_0_pmp_5_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_0_pmp_5_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_6_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_0_pmp_6_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_6_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_6_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_6_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_0_pmp_6_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_0_pmp_6_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_7_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_0_pmp_7_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_7_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_7_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_7_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_0_pmp_7_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_0_pmp_7_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_req_ready; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_valid; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_ae_ptw; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_ae_final; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_pf; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_gf; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_hr; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_hw; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_hx; // @[tile.scala:237:20]
wire [9:0] _ptw_io_requestor_1_resp_bits_pte_reserved_for_future; // @[tile.scala:237:20]
wire [43:0] _ptw_io_requestor_1_resp_bits_pte_ppn; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_1_resp_bits_pte_reserved_for_software; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_pte_d; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_pte_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_pte_g; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_pte_u; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_pte_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_pte_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_pte_r; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_pte_v; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_1_resp_bits_level; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_homogeneous; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_gpa_valid; // @[tile.scala:237:20]
wire [38:0] _ptw_io_requestor_1_resp_bits_gpa_bits; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_gpa_is_pte; // @[tile.scala:237:20]
wire [3:0] _ptw_io_requestor_1_ptbr_mode; // @[tile.scala:237:20]
wire [43:0] _ptw_io_requestor_1_ptbr_ppn; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_debug; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_cease; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_wfi; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_1_status_dprv; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_dv; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_1_status_prv; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_v; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_sd; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_mpv; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_gva; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_tsr; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_tw; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_tvm; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_mxr; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_sum; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_mprv; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_1_status_fs; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_1_status_mpp; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_spp; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_mpie; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_spie; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_mie; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_sie; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_0_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_1_pmp_0_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_0_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_0_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_0_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_1_pmp_0_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_1_pmp_0_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_1_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_1_pmp_1_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_1_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_1_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_1_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_1_pmp_1_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_1_pmp_1_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_2_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_1_pmp_2_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_2_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_2_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_2_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_1_pmp_2_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_1_pmp_2_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_3_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_1_pmp_3_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_3_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_3_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_3_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_1_pmp_3_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_1_pmp_3_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_4_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_1_pmp_4_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_4_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_4_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_4_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_1_pmp_4_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_1_pmp_4_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_5_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_1_pmp_5_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_5_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_5_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_5_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_1_pmp_5_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_1_pmp_5_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_6_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_1_pmp_6_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_6_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_6_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_6_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_1_pmp_6_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_1_pmp_6_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_7_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_1_pmp_7_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_7_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_7_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_7_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_1_pmp_7_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_1_pmp_7_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_req_ready; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_valid; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_ae_ptw; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_ae_final; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_pf; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_gf; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_hr; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_hw; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_hx; // @[tile.scala:237:20]
wire [9:0] _ptw_io_requestor_2_resp_bits_pte_reserved_for_future; // @[tile.scala:237:20]
wire [43:0] _ptw_io_requestor_2_resp_bits_pte_ppn; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_2_resp_bits_pte_reserved_for_software; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_pte_d; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_pte_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_pte_g; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_pte_u; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_pte_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_pte_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_pte_r; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_pte_v; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_2_resp_bits_level; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_homogeneous; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_gpa_valid; // @[tile.scala:237:20]
wire [38:0] _ptw_io_requestor_2_resp_bits_gpa_bits; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_gpa_is_pte; // @[tile.scala:237:20]
wire [3:0] _ptw_io_requestor_2_ptbr_mode; // @[tile.scala:237:20]
wire [43:0] _ptw_io_requestor_2_ptbr_ppn; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_debug; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_cease; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_wfi; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_2_status_dprv; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_dv; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_2_status_prv; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_v; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_sd; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_mpv; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_gva; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_tsr; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_tw; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_tvm; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_mxr; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_sum; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_mprv; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_2_status_fs; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_2_status_mpp; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_spp; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_mpie; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_spie; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_mie; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_sie; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_0_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_2_pmp_0_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_0_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_0_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_0_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_2_pmp_0_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_2_pmp_0_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_1_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_2_pmp_1_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_1_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_1_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_1_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_2_pmp_1_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_2_pmp_1_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_2_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_2_pmp_2_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_2_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_2_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_2_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_2_pmp_2_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_2_pmp_2_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_3_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_2_pmp_3_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_3_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_3_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_3_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_2_pmp_3_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_2_pmp_3_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_4_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_2_pmp_4_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_4_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_4_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_4_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_2_pmp_4_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_2_pmp_4_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_5_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_2_pmp_5_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_5_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_5_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_5_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_2_pmp_5_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_2_pmp_5_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_6_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_2_pmp_6_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_6_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_6_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_6_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_2_pmp_6_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_2_pmp_6_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_7_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_2_pmp_7_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_7_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_7_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_7_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_2_pmp_7_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_2_pmp_7_mask; // @[tile.scala:237:20]
wire _ptw_io_mem_req_valid; // @[tile.scala:237:20]
wire [39:0] _ptw_io_mem_req_bits_addr; // @[tile.scala:237:20]
wire _ptw_io_mem_req_bits_dv; // @[tile.scala:237:20]
wire _ptw_io_mem_s1_kill; // @[tile.scala:237:20]
wire _ptw_io_dpath_perf_l2miss; // @[tile.scala:237:20]
wire _ptw_io_dpath_perf_l2hit; // @[tile.scala:237:20]
wire _ptw_io_dpath_perf_pte_miss; // @[tile.scala:237:20]
wire _ptw_io_dpath_perf_pte_hit; // @[tile.scala:237:20]
wire _ptw_io_dpath_clock_enabled; // @[tile.scala:237:20]
wire _lsu_io_ptw_req_valid; // @[tile.scala:160:20]
wire _lsu_io_ptw_req_bits_valid; // @[tile.scala:160:20]
wire [26:0] _lsu_io_ptw_req_bits_bits_addr; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_valid; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_exe_0_iresp_bits_uop_uopc; // @[tile.scala:160:20]
wire [31:0] _lsu_io_core_exe_0_iresp_bits_uop_inst; // @[tile.scala:160:20]
wire [31:0] _lsu_io_core_exe_0_iresp_bits_uop_debug_inst; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_is_rvc; // @[tile.scala:160:20]
wire [39:0] _lsu_io_core_exe_0_iresp_bits_uop_debug_pc; // @[tile.scala:160:20]
wire [2:0] _lsu_io_core_exe_0_iresp_bits_uop_iq_type; // @[tile.scala:160:20]
wire [9:0] _lsu_io_core_exe_0_iresp_bits_uop_fu_code; // @[tile.scala:160:20]
wire [3:0] _lsu_io_core_exe_0_iresp_bits_uop_ctrl_br_type; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_ctrl_op1_sel; // @[tile.scala:160:20]
wire [2:0] _lsu_io_core_exe_0_iresp_bits_uop_ctrl_op2_sel; // @[tile.scala:160:20]
wire [2:0] _lsu_io_core_exe_0_iresp_bits_uop_ctrl_imm_sel; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_exe_0_iresp_bits_uop_ctrl_op_fcn; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_ctrl_fcn_dw; // @[tile.scala:160:20]
wire [2:0] _lsu_io_core_exe_0_iresp_bits_uop_ctrl_csr_cmd; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_ctrl_is_load; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_ctrl_is_sta; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_ctrl_is_std; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_iw_state; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_iw_p1_poisoned; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_iw_p2_poisoned; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_is_br; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_is_jalr; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_is_jal; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_is_sfb; // @[tile.scala:160:20]
wire [15:0] _lsu_io_core_exe_0_iresp_bits_uop_br_mask; // @[tile.scala:160:20]
wire [3:0] _lsu_io_core_exe_0_iresp_bits_uop_br_tag; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_exe_0_iresp_bits_uop_ftq_idx; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_edge_inst; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_exe_0_iresp_bits_uop_pc_lob; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_taken; // @[tile.scala:160:20]
wire [19:0] _lsu_io_core_exe_0_iresp_bits_uop_imm_packed; // @[tile.scala:160:20]
wire [11:0] _lsu_io_core_exe_0_iresp_bits_uop_csr_addr; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_exe_0_iresp_bits_uop_rob_idx; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_exe_0_iresp_bits_uop_ldq_idx; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_exe_0_iresp_bits_uop_stq_idx; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_rxq_idx; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_exe_0_iresp_bits_uop_pdst; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_exe_0_iresp_bits_uop_prs1; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_exe_0_iresp_bits_uop_prs2; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_exe_0_iresp_bits_uop_prs3; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_exe_0_iresp_bits_uop_ppred; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_prs1_busy; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_prs2_busy; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_prs3_busy; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_ppred_busy; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_exe_0_iresp_bits_uop_stale_pdst; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_exception; // @[tile.scala:160:20]
wire [63:0] _lsu_io_core_exe_0_iresp_bits_uop_exc_cause; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_bypassable; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_exe_0_iresp_bits_uop_mem_cmd; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_mem_size; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_mem_signed; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_is_fence; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_is_fencei; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_is_amo; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_uses_ldq; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_uses_stq; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_is_sys_pc2epc; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_is_unique; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_flush_on_commit; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_ldst_is_rs1; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_exe_0_iresp_bits_uop_ldst; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_exe_0_iresp_bits_uop_lrs1; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_exe_0_iresp_bits_uop_lrs2; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_exe_0_iresp_bits_uop_lrs3; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_ldst_val; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_dst_rtype; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_lrs1_rtype; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_lrs2_rtype; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_frs3_en; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_fp_val; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_fp_single; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_xcpt_pf_if; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_xcpt_ae_if; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_xcpt_ma_if; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_bp_debug_if; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_bp_xcpt_if; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_debug_fsrc; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_debug_tsrc; // @[tile.scala:160:20]
wire [63:0] _lsu_io_core_exe_0_iresp_bits_data; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_valid; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_exe_0_fresp_bits_uop_uopc; // @[tile.scala:160:20]
wire [31:0] _lsu_io_core_exe_0_fresp_bits_uop_inst; // @[tile.scala:160:20]
wire [31:0] _lsu_io_core_exe_0_fresp_bits_uop_debug_inst; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_is_rvc; // @[tile.scala:160:20]
wire [39:0] _lsu_io_core_exe_0_fresp_bits_uop_debug_pc; // @[tile.scala:160:20]
wire [2:0] _lsu_io_core_exe_0_fresp_bits_uop_iq_type; // @[tile.scala:160:20]
wire [9:0] _lsu_io_core_exe_0_fresp_bits_uop_fu_code; // @[tile.scala:160:20]
wire [3:0] _lsu_io_core_exe_0_fresp_bits_uop_ctrl_br_type; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_ctrl_op1_sel; // @[tile.scala:160:20]
wire [2:0] _lsu_io_core_exe_0_fresp_bits_uop_ctrl_op2_sel; // @[tile.scala:160:20]
wire [2:0] _lsu_io_core_exe_0_fresp_bits_uop_ctrl_imm_sel; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_exe_0_fresp_bits_uop_ctrl_op_fcn; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_ctrl_fcn_dw; // @[tile.scala:160:20]
wire [2:0] _lsu_io_core_exe_0_fresp_bits_uop_ctrl_csr_cmd; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_ctrl_is_load; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_ctrl_is_sta; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_ctrl_is_std; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_iw_state; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_iw_p1_poisoned; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_iw_p2_poisoned; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_is_br; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_is_jalr; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_is_jal; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_is_sfb; // @[tile.scala:160:20]
wire [15:0] _lsu_io_core_exe_0_fresp_bits_uop_br_mask; // @[tile.scala:160:20]
wire [3:0] _lsu_io_core_exe_0_fresp_bits_uop_br_tag; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_exe_0_fresp_bits_uop_ftq_idx; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_edge_inst; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_exe_0_fresp_bits_uop_pc_lob; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_taken; // @[tile.scala:160:20]
wire [19:0] _lsu_io_core_exe_0_fresp_bits_uop_imm_packed; // @[tile.scala:160:20]
wire [11:0] _lsu_io_core_exe_0_fresp_bits_uop_csr_addr; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_exe_0_fresp_bits_uop_rob_idx; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_exe_0_fresp_bits_uop_ldq_idx; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_exe_0_fresp_bits_uop_stq_idx; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_rxq_idx; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_exe_0_fresp_bits_uop_pdst; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_exe_0_fresp_bits_uop_prs1; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_exe_0_fresp_bits_uop_prs2; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_exe_0_fresp_bits_uop_prs3; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_exe_0_fresp_bits_uop_ppred; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_prs1_busy; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_prs2_busy; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_prs3_busy; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_ppred_busy; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_exe_0_fresp_bits_uop_stale_pdst; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_exception; // @[tile.scala:160:20]
wire [63:0] _lsu_io_core_exe_0_fresp_bits_uop_exc_cause; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_bypassable; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_exe_0_fresp_bits_uop_mem_cmd; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_mem_size; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_mem_signed; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_is_fence; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_is_fencei; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_is_amo; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_uses_ldq; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_uses_stq; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_is_sys_pc2epc; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_is_unique; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_flush_on_commit; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_ldst_is_rs1; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_exe_0_fresp_bits_uop_ldst; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_exe_0_fresp_bits_uop_lrs1; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_exe_0_fresp_bits_uop_lrs2; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_exe_0_fresp_bits_uop_lrs3; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_ldst_val; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_dst_rtype; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_lrs1_rtype; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_lrs2_rtype; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_frs3_en; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_fp_val; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_fp_single; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_xcpt_pf_if; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_xcpt_ae_if; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_xcpt_ma_if; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_bp_debug_if; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_bp_xcpt_if; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_debug_fsrc; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_debug_tsrc; // @[tile.scala:160:20]
wire [64:0] _lsu_io_core_exe_0_fresp_bits_data; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_dis_ldq_idx_0; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_dis_ldq_idx_1; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_dis_ldq_idx_2; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_dis_stq_idx_0; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_dis_stq_idx_1; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_dis_stq_idx_2; // @[tile.scala:160:20]
wire _lsu_io_core_ldq_full_0; // @[tile.scala:160:20]
wire _lsu_io_core_ldq_full_1; // @[tile.scala:160:20]
wire _lsu_io_core_ldq_full_2; // @[tile.scala:160:20]
wire _lsu_io_core_stq_full_0; // @[tile.scala:160:20]
wire _lsu_io_core_stq_full_1; // @[tile.scala:160:20]
wire _lsu_io_core_stq_full_2; // @[tile.scala:160:20]
wire _lsu_io_core_fp_stdata_ready; // @[tile.scala:160:20]
wire _lsu_io_core_clr_bsy_0_valid; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_clr_bsy_0_bits; // @[tile.scala:160:20]
wire _lsu_io_core_clr_bsy_1_valid; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_clr_bsy_1_bits; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_clr_unsafe_0_bits; // @[tile.scala:160:20]
wire _lsu_io_core_spec_ld_wakeup_0_valid; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_spec_ld_wakeup_0_bits; // @[tile.scala:160:20]
wire _lsu_io_core_ld_miss; // @[tile.scala:160:20]
wire _lsu_io_core_fencei_rdy; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_valid; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_lxcpt_bits_uop_uopc; // @[tile.scala:160:20]
wire [31:0] _lsu_io_core_lxcpt_bits_uop_inst; // @[tile.scala:160:20]
wire [31:0] _lsu_io_core_lxcpt_bits_uop_debug_inst; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_is_rvc; // @[tile.scala:160:20]
wire [39:0] _lsu_io_core_lxcpt_bits_uop_debug_pc; // @[tile.scala:160:20]
wire [2:0] _lsu_io_core_lxcpt_bits_uop_iq_type; // @[tile.scala:160:20]
wire [9:0] _lsu_io_core_lxcpt_bits_uop_fu_code; // @[tile.scala:160:20]
wire [3:0] _lsu_io_core_lxcpt_bits_uop_ctrl_br_type; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_lxcpt_bits_uop_ctrl_op1_sel; // @[tile.scala:160:20]
wire [2:0] _lsu_io_core_lxcpt_bits_uop_ctrl_op2_sel; // @[tile.scala:160:20]
wire [2:0] _lsu_io_core_lxcpt_bits_uop_ctrl_imm_sel; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_lxcpt_bits_uop_ctrl_op_fcn; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_ctrl_fcn_dw; // @[tile.scala:160:20]
wire [2:0] _lsu_io_core_lxcpt_bits_uop_ctrl_csr_cmd; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_ctrl_is_load; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_ctrl_is_sta; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_ctrl_is_std; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_lxcpt_bits_uop_iw_state; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_iw_p1_poisoned; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_iw_p2_poisoned; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_is_br; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_is_jalr; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_is_jal; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_is_sfb; // @[tile.scala:160:20]
wire [15:0] _lsu_io_core_lxcpt_bits_uop_br_mask; // @[tile.scala:160:20]
wire [3:0] _lsu_io_core_lxcpt_bits_uop_br_tag; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_lxcpt_bits_uop_ftq_idx; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_edge_inst; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_lxcpt_bits_uop_pc_lob; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_taken; // @[tile.scala:160:20]
wire [19:0] _lsu_io_core_lxcpt_bits_uop_imm_packed; // @[tile.scala:160:20]
wire [11:0] _lsu_io_core_lxcpt_bits_uop_csr_addr; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_lxcpt_bits_uop_rob_idx; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_lxcpt_bits_uop_ldq_idx; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_lxcpt_bits_uop_stq_idx; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_lxcpt_bits_uop_rxq_idx; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_lxcpt_bits_uop_pdst; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_lxcpt_bits_uop_prs1; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_lxcpt_bits_uop_prs2; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_lxcpt_bits_uop_prs3; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_lxcpt_bits_uop_ppred; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_prs1_busy; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_prs2_busy; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_prs3_busy; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_ppred_busy; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_lxcpt_bits_uop_stale_pdst; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_exception; // @[tile.scala:160:20]
wire [63:0] _lsu_io_core_lxcpt_bits_uop_exc_cause; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_bypassable; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_lxcpt_bits_uop_mem_cmd; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_lxcpt_bits_uop_mem_size; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_mem_signed; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_is_fence; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_is_fencei; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_is_amo; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_uses_ldq; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_uses_stq; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_is_sys_pc2epc; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_is_unique; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_flush_on_commit; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_ldst_is_rs1; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_lxcpt_bits_uop_ldst; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_lxcpt_bits_uop_lrs1; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_lxcpt_bits_uop_lrs2; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_lxcpt_bits_uop_lrs3; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_ldst_val; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_lxcpt_bits_uop_dst_rtype; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_lxcpt_bits_uop_lrs1_rtype; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_lxcpt_bits_uop_lrs2_rtype; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_frs3_en; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_fp_val; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_fp_single; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_xcpt_pf_if; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_xcpt_ae_if; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_xcpt_ma_if; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_bp_debug_if; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_bp_xcpt_if; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_lxcpt_bits_uop_debug_fsrc; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_lxcpt_bits_uop_debug_tsrc; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_lxcpt_bits_cause; // @[tile.scala:160:20]
wire [39:0] _lsu_io_core_lxcpt_bits_badvaddr; // @[tile.scala:160:20]
wire _lsu_io_core_perf_acquire; // @[tile.scala:160:20]
wire _lsu_io_core_perf_release; // @[tile.scala:160:20]
wire _lsu_io_core_perf_tlbMiss; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_valid; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_valid; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_uopc; // @[tile.scala:160:20]
wire [31:0] _lsu_io_dmem_req_bits_0_bits_uop_inst; // @[tile.scala:160:20]
wire [31:0] _lsu_io_dmem_req_bits_0_bits_uop_debug_inst; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_is_rvc; // @[tile.scala:160:20]
wire [39:0] _lsu_io_dmem_req_bits_0_bits_uop_debug_pc; // @[tile.scala:160:20]
wire [2:0] _lsu_io_dmem_req_bits_0_bits_uop_iq_type; // @[tile.scala:160:20]
wire [9:0] _lsu_io_dmem_req_bits_0_bits_uop_fu_code; // @[tile.scala:160:20]
wire [3:0] _lsu_io_dmem_req_bits_0_bits_uop_ctrl_br_type; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_ctrl_op1_sel; // @[tile.scala:160:20]
wire [2:0] _lsu_io_dmem_req_bits_0_bits_uop_ctrl_op2_sel; // @[tile.scala:160:20]
wire [2:0] _lsu_io_dmem_req_bits_0_bits_uop_ctrl_imm_sel; // @[tile.scala:160:20]
wire [4:0] _lsu_io_dmem_req_bits_0_bits_uop_ctrl_op_fcn; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_ctrl_fcn_dw; // @[tile.scala:160:20]
wire [2:0] _lsu_io_dmem_req_bits_0_bits_uop_ctrl_csr_cmd; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_ctrl_is_load; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_ctrl_is_sta; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_ctrl_is_std; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_iw_state; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_iw_p1_poisoned; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_iw_p2_poisoned; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_is_br; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_is_jalr; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_is_jal; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_is_sfb; // @[tile.scala:160:20]
wire [15:0] _lsu_io_dmem_req_bits_0_bits_uop_br_mask; // @[tile.scala:160:20]
wire [3:0] _lsu_io_dmem_req_bits_0_bits_uop_br_tag; // @[tile.scala:160:20]
wire [4:0] _lsu_io_dmem_req_bits_0_bits_uop_ftq_idx; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_edge_inst; // @[tile.scala:160:20]
wire [5:0] _lsu_io_dmem_req_bits_0_bits_uop_pc_lob; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_taken; // @[tile.scala:160:20]
wire [19:0] _lsu_io_dmem_req_bits_0_bits_uop_imm_packed; // @[tile.scala:160:20]
wire [11:0] _lsu_io_dmem_req_bits_0_bits_uop_csr_addr; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_rob_idx; // @[tile.scala:160:20]
wire [4:0] _lsu_io_dmem_req_bits_0_bits_uop_ldq_idx; // @[tile.scala:160:20]
wire [4:0] _lsu_io_dmem_req_bits_0_bits_uop_stq_idx; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_rxq_idx; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_pdst; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_prs1; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_prs2; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_prs3; // @[tile.scala:160:20]
wire [4:0] _lsu_io_dmem_req_bits_0_bits_uop_ppred; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_prs1_busy; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_prs2_busy; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_prs3_busy; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_ppred_busy; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_stale_pdst; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_exception; // @[tile.scala:160:20]
wire [63:0] _lsu_io_dmem_req_bits_0_bits_uop_exc_cause; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_bypassable; // @[tile.scala:160:20]
wire [4:0] _lsu_io_dmem_req_bits_0_bits_uop_mem_cmd; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_mem_size; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_mem_signed; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_is_fence; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_is_fencei; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_is_amo; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_uses_ldq; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_uses_stq; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_is_sys_pc2epc; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_is_unique; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_flush_on_commit; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_ldst_is_rs1; // @[tile.scala:160:20]
wire [5:0] _lsu_io_dmem_req_bits_0_bits_uop_ldst; // @[tile.scala:160:20]
wire [5:0] _lsu_io_dmem_req_bits_0_bits_uop_lrs1; // @[tile.scala:160:20]
wire [5:0] _lsu_io_dmem_req_bits_0_bits_uop_lrs2; // @[tile.scala:160:20]
wire [5:0] _lsu_io_dmem_req_bits_0_bits_uop_lrs3; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_ldst_val; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_dst_rtype; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_lrs1_rtype; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_lrs2_rtype; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_frs3_en; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_fp_val; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_fp_single; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_xcpt_pf_if; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_xcpt_ae_if; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_xcpt_ma_if; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_bp_debug_if; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_bp_xcpt_if; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_debug_fsrc; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_debug_tsrc; // @[tile.scala:160:20]
wire [39:0] _lsu_io_dmem_req_bits_0_bits_addr; // @[tile.scala:160:20]
wire [63:0] _lsu_io_dmem_req_bits_0_bits_data; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_is_hella; // @[tile.scala:160:20]
wire _lsu_io_dmem_s1_kill_0; // @[tile.scala:160:20]
wire [15:0] _lsu_io_dmem_brupdate_b1_resolve_mask; // @[tile.scala:160:20]
wire [15:0] _lsu_io_dmem_brupdate_b1_mispredict_mask; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_brupdate_b2_uop_uopc; // @[tile.scala:160:20]
wire [31:0] _lsu_io_dmem_brupdate_b2_uop_inst; // @[tile.scala:160:20]
wire [31:0] _lsu_io_dmem_brupdate_b2_uop_debug_inst; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_is_rvc; // @[tile.scala:160:20]
wire [39:0] _lsu_io_dmem_brupdate_b2_uop_debug_pc; // @[tile.scala:160:20]
wire [2:0] _lsu_io_dmem_brupdate_b2_uop_iq_type; // @[tile.scala:160:20]
wire [9:0] _lsu_io_dmem_brupdate_b2_uop_fu_code; // @[tile.scala:160:20]
wire [3:0] _lsu_io_dmem_brupdate_b2_uop_ctrl_br_type; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_brupdate_b2_uop_ctrl_op1_sel; // @[tile.scala:160:20]
wire [2:0] _lsu_io_dmem_brupdate_b2_uop_ctrl_op2_sel; // @[tile.scala:160:20]
wire [2:0] _lsu_io_dmem_brupdate_b2_uop_ctrl_imm_sel; // @[tile.scala:160:20]
wire [4:0] _lsu_io_dmem_brupdate_b2_uop_ctrl_op_fcn; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_ctrl_fcn_dw; // @[tile.scala:160:20]
wire [2:0] _lsu_io_dmem_brupdate_b2_uop_ctrl_csr_cmd; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_ctrl_is_load; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_ctrl_is_sta; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_ctrl_is_std; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_brupdate_b2_uop_iw_state; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_iw_p1_poisoned; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_iw_p2_poisoned; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_is_br; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_is_jalr; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_is_jal; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_is_sfb; // @[tile.scala:160:20]
wire [15:0] _lsu_io_dmem_brupdate_b2_uop_br_mask; // @[tile.scala:160:20]
wire [3:0] _lsu_io_dmem_brupdate_b2_uop_br_tag; // @[tile.scala:160:20]
wire [4:0] _lsu_io_dmem_brupdate_b2_uop_ftq_idx; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_edge_inst; // @[tile.scala:160:20]
wire [5:0] _lsu_io_dmem_brupdate_b2_uop_pc_lob; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_taken; // @[tile.scala:160:20]
wire [19:0] _lsu_io_dmem_brupdate_b2_uop_imm_packed; // @[tile.scala:160:20]
wire [11:0] _lsu_io_dmem_brupdate_b2_uop_csr_addr; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_brupdate_b2_uop_rob_idx; // @[tile.scala:160:20]
wire [4:0] _lsu_io_dmem_brupdate_b2_uop_ldq_idx; // @[tile.scala:160:20]
wire [4:0] _lsu_io_dmem_brupdate_b2_uop_stq_idx; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_brupdate_b2_uop_rxq_idx; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_brupdate_b2_uop_pdst; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_brupdate_b2_uop_prs1; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_brupdate_b2_uop_prs2; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_brupdate_b2_uop_prs3; // @[tile.scala:160:20]
wire [4:0] _lsu_io_dmem_brupdate_b2_uop_ppred; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_prs1_busy; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_prs2_busy; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_prs3_busy; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_ppred_busy; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_brupdate_b2_uop_stale_pdst; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_exception; // @[tile.scala:160:20]
wire [63:0] _lsu_io_dmem_brupdate_b2_uop_exc_cause; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_bypassable; // @[tile.scala:160:20]
wire [4:0] _lsu_io_dmem_brupdate_b2_uop_mem_cmd; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_brupdate_b2_uop_mem_size; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_mem_signed; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_is_fence; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_is_fencei; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_is_amo; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_uses_ldq; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_uses_stq; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_is_sys_pc2epc; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_is_unique; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_flush_on_commit; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_ldst_is_rs1; // @[tile.scala:160:20]
wire [5:0] _lsu_io_dmem_brupdate_b2_uop_ldst; // @[tile.scala:160:20]
wire [5:0] _lsu_io_dmem_brupdate_b2_uop_lrs1; // @[tile.scala:160:20]
wire [5:0] _lsu_io_dmem_brupdate_b2_uop_lrs2; // @[tile.scala:160:20]
wire [5:0] _lsu_io_dmem_brupdate_b2_uop_lrs3; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_ldst_val; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_brupdate_b2_uop_dst_rtype; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_brupdate_b2_uop_lrs1_rtype; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_brupdate_b2_uop_lrs2_rtype; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_frs3_en; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_fp_val; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_fp_single; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_xcpt_pf_if; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_xcpt_ae_if; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_xcpt_ma_if; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_bp_debug_if; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_bp_xcpt_if; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_brupdate_b2_uop_debug_fsrc; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_brupdate_b2_uop_debug_tsrc; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_valid; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_mispredict; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_taken; // @[tile.scala:160:20]
wire [2:0] _lsu_io_dmem_brupdate_b2_cfi_type; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_brupdate_b2_pc_sel; // @[tile.scala:160:20]
wire [39:0] _lsu_io_dmem_brupdate_b2_jalr_target; // @[tile.scala:160:20]
wire [20:0] _lsu_io_dmem_brupdate_b2_target_offset; // @[tile.scala:160:20]
wire _lsu_io_dmem_exception; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_rob_pnr_idx; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_rob_head_idx; // @[tile.scala:160:20]
wire _lsu_io_dmem_release_ready; // @[tile.scala:160:20]
wire _lsu_io_dmem_force_order; // @[tile.scala:160:20]
wire _lsu_io_hellacache_req_ready; // @[tile.scala:160:20]
wire _lsu_io_hellacache_s2_nack; // @[tile.scala:160:20]
wire _lsu_io_hellacache_resp_valid; // @[tile.scala:160:20]
wire [39:0] _lsu_io_hellacache_resp_bits_addr; // @[tile.scala:160:20]
wire [63:0] _lsu_io_hellacache_resp_bits_data; // @[tile.scala:160:20]
wire _lsu_io_hellacache_s2_xcpt_ma_ld; // @[tile.scala:160:20]
wire _lsu_io_hellacache_s2_xcpt_ma_st; // @[tile.scala:160:20]
wire _lsu_io_hellacache_s2_xcpt_pf_ld; // @[tile.scala:160:20]
wire _lsu_io_hellacache_s2_xcpt_pf_st; // @[tile.scala:160:20]
wire _lsu_io_hellacache_s2_xcpt_gf_ld; // @[tile.scala:160:20]
wire _lsu_io_hellacache_s2_xcpt_gf_st; // @[tile.scala:160:20]
wire _lsu_io_hellacache_s2_xcpt_ae_ld; // @[tile.scala:160:20]
wire _lsu_io_hellacache_s2_xcpt_ae_st; // @[tile.scala:160:20]
wire _lsu_io_hellacache_store_pending; // @[tile.scala:160:20]
wire _core_io_ifu_fetchpacket_ready; // @[tile.scala:159:20]
wire [4:0] _core_io_ifu_get_pc_0_ftq_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_ifu_get_pc_1_ftq_idx; // @[tile.scala:159:20]
wire _core_io_ifu_status_debug; // @[tile.scala:159:20]
wire _core_io_ifu_status_cease; // @[tile.scala:159:20]
wire _core_io_ifu_status_wfi; // @[tile.scala:159:20]
wire [1:0] _core_io_ifu_status_dprv; // @[tile.scala:159:20]
wire _core_io_ifu_status_dv; // @[tile.scala:159:20]
wire [1:0] _core_io_ifu_status_prv; // @[tile.scala:159:20]
wire _core_io_ifu_status_v; // @[tile.scala:159:20]
wire _core_io_ifu_status_sd; // @[tile.scala:159:20]
wire _core_io_ifu_status_mpv; // @[tile.scala:159:20]
wire _core_io_ifu_status_gva; // @[tile.scala:159:20]
wire _core_io_ifu_status_tsr; // @[tile.scala:159:20]
wire _core_io_ifu_status_tw; // @[tile.scala:159:20]
wire _core_io_ifu_status_tvm; // @[tile.scala:159:20]
wire _core_io_ifu_status_mxr; // @[tile.scala:159:20]
wire _core_io_ifu_status_sum; // @[tile.scala:159:20]
wire _core_io_ifu_status_mprv; // @[tile.scala:159:20]
wire [1:0] _core_io_ifu_status_fs; // @[tile.scala:159:20]
wire [1:0] _core_io_ifu_status_mpp; // @[tile.scala:159:20]
wire _core_io_ifu_status_spp; // @[tile.scala:159:20]
wire _core_io_ifu_status_mpie; // @[tile.scala:159:20]
wire _core_io_ifu_status_spie; // @[tile.scala:159:20]
wire _core_io_ifu_status_mie; // @[tile.scala:159:20]
wire _core_io_ifu_status_sie; // @[tile.scala:159:20]
wire _core_io_ifu_sfence_valid; // @[tile.scala:159:20]
wire _core_io_ifu_sfence_bits_rs1; // @[tile.scala:159:20]
wire _core_io_ifu_sfence_bits_rs2; // @[tile.scala:159:20]
wire [38:0] _core_io_ifu_sfence_bits_addr; // @[tile.scala:159:20]
wire _core_io_ifu_sfence_bits_asid; // @[tile.scala:159:20]
wire [15:0] _core_io_ifu_brupdate_b1_resolve_mask; // @[tile.scala:159:20]
wire [15:0] _core_io_ifu_brupdate_b1_mispredict_mask; // @[tile.scala:159:20]
wire [6:0] _core_io_ifu_brupdate_b2_uop_uopc; // @[tile.scala:159:20]
wire [31:0] _core_io_ifu_brupdate_b2_uop_inst; // @[tile.scala:159:20]
wire [31:0] _core_io_ifu_brupdate_b2_uop_debug_inst; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_is_rvc; // @[tile.scala:159:20]
wire [39:0] _core_io_ifu_brupdate_b2_uop_debug_pc; // @[tile.scala:159:20]
wire [2:0] _core_io_ifu_brupdate_b2_uop_iq_type; // @[tile.scala:159:20]
wire [9:0] _core_io_ifu_brupdate_b2_uop_fu_code; // @[tile.scala:159:20]
wire [3:0] _core_io_ifu_brupdate_b2_uop_ctrl_br_type; // @[tile.scala:159:20]
wire [1:0] _core_io_ifu_brupdate_b2_uop_ctrl_op1_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_ifu_brupdate_b2_uop_ctrl_op2_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_ifu_brupdate_b2_uop_ctrl_imm_sel; // @[tile.scala:159:20]
wire [4:0] _core_io_ifu_brupdate_b2_uop_ctrl_op_fcn; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_ctrl_fcn_dw; // @[tile.scala:159:20]
wire [2:0] _core_io_ifu_brupdate_b2_uop_ctrl_csr_cmd; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_ctrl_is_load; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_ctrl_is_sta; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_ctrl_is_std; // @[tile.scala:159:20]
wire [1:0] _core_io_ifu_brupdate_b2_uop_iw_state; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_iw_p1_poisoned; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_iw_p2_poisoned; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_is_br; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_is_jalr; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_is_jal; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_is_sfb; // @[tile.scala:159:20]
wire [15:0] _core_io_ifu_brupdate_b2_uop_br_mask; // @[tile.scala:159:20]
wire [3:0] _core_io_ifu_brupdate_b2_uop_br_tag; // @[tile.scala:159:20]
wire [4:0] _core_io_ifu_brupdate_b2_uop_ftq_idx; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_edge_inst; // @[tile.scala:159:20]
wire [5:0] _core_io_ifu_brupdate_b2_uop_pc_lob; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_taken; // @[tile.scala:159:20]
wire [19:0] _core_io_ifu_brupdate_b2_uop_imm_packed; // @[tile.scala:159:20]
wire [11:0] _core_io_ifu_brupdate_b2_uop_csr_addr; // @[tile.scala:159:20]
wire [6:0] _core_io_ifu_brupdate_b2_uop_rob_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_ifu_brupdate_b2_uop_ldq_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_ifu_brupdate_b2_uop_stq_idx; // @[tile.scala:159:20]
wire [1:0] _core_io_ifu_brupdate_b2_uop_rxq_idx; // @[tile.scala:159:20]
wire [6:0] _core_io_ifu_brupdate_b2_uop_pdst; // @[tile.scala:159:20]
wire [6:0] _core_io_ifu_brupdate_b2_uop_prs1; // @[tile.scala:159:20]
wire [6:0] _core_io_ifu_brupdate_b2_uop_prs2; // @[tile.scala:159:20]
wire [6:0] _core_io_ifu_brupdate_b2_uop_prs3; // @[tile.scala:159:20]
wire [4:0] _core_io_ifu_brupdate_b2_uop_ppred; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_prs1_busy; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_prs2_busy; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_prs3_busy; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_ppred_busy; // @[tile.scala:159:20]
wire [6:0] _core_io_ifu_brupdate_b2_uop_stale_pdst; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_exception; // @[tile.scala:159:20]
wire [63:0] _core_io_ifu_brupdate_b2_uop_exc_cause; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_bypassable; // @[tile.scala:159:20]
wire [4:0] _core_io_ifu_brupdate_b2_uop_mem_cmd; // @[tile.scala:159:20]
wire [1:0] _core_io_ifu_brupdate_b2_uop_mem_size; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_mem_signed; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_is_fence; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_is_fencei; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_is_amo; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_uses_ldq; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_uses_stq; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_is_sys_pc2epc; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_is_unique; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_flush_on_commit; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_ldst_is_rs1; // @[tile.scala:159:20]
wire [5:0] _core_io_ifu_brupdate_b2_uop_ldst; // @[tile.scala:159:20]
wire [5:0] _core_io_ifu_brupdate_b2_uop_lrs1; // @[tile.scala:159:20]
wire [5:0] _core_io_ifu_brupdate_b2_uop_lrs2; // @[tile.scala:159:20]
wire [5:0] _core_io_ifu_brupdate_b2_uop_lrs3; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_ldst_val; // @[tile.scala:159:20]
wire [1:0] _core_io_ifu_brupdate_b2_uop_dst_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_ifu_brupdate_b2_uop_lrs1_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_ifu_brupdate_b2_uop_lrs2_rtype; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_frs3_en; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_fp_val; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_fp_single; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_xcpt_pf_if; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_xcpt_ae_if; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_xcpt_ma_if; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_bp_debug_if; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_bp_xcpt_if; // @[tile.scala:159:20]
wire [1:0] _core_io_ifu_brupdate_b2_uop_debug_fsrc; // @[tile.scala:159:20]
wire [1:0] _core_io_ifu_brupdate_b2_uop_debug_tsrc; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_valid; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_mispredict; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_taken; // @[tile.scala:159:20]
wire [2:0] _core_io_ifu_brupdate_b2_cfi_type; // @[tile.scala:159:20]
wire [1:0] _core_io_ifu_brupdate_b2_pc_sel; // @[tile.scala:159:20]
wire [39:0] _core_io_ifu_brupdate_b2_jalr_target; // @[tile.scala:159:20]
wire [20:0] _core_io_ifu_brupdate_b2_target_offset; // @[tile.scala:159:20]
wire _core_io_ifu_redirect_flush; // @[tile.scala:159:20]
wire _core_io_ifu_redirect_val; // @[tile.scala:159:20]
wire [39:0] _core_io_ifu_redirect_pc; // @[tile.scala:159:20]
wire [4:0] _core_io_ifu_redirect_ftq_idx; // @[tile.scala:159:20]
wire [63:0] _core_io_ifu_redirect_ghist_old_history; // @[tile.scala:159:20]
wire _core_io_ifu_redirect_ghist_current_saw_branch_not_taken; // @[tile.scala:159:20]
wire _core_io_ifu_redirect_ghist_new_saw_branch_not_taken; // @[tile.scala:159:20]
wire _core_io_ifu_redirect_ghist_new_saw_branch_taken; // @[tile.scala:159:20]
wire [4:0] _core_io_ifu_redirect_ghist_ras_idx; // @[tile.scala:159:20]
wire _core_io_ifu_commit_valid; // @[tile.scala:159:20]
wire [31:0] _core_io_ifu_commit_bits; // @[tile.scala:159:20]
wire _core_io_ifu_flush_icache; // @[tile.scala:159:20]
wire [3:0] _core_io_ptw_ptbr_mode; // @[tile.scala:159:20]
wire [43:0] _core_io_ptw_ptbr_ppn; // @[tile.scala:159:20]
wire _core_io_ptw_sfence_valid; // @[tile.scala:159:20]
wire _core_io_ptw_sfence_bits_rs1; // @[tile.scala:159:20]
wire _core_io_ptw_sfence_bits_rs2; // @[tile.scala:159:20]
wire [38:0] _core_io_ptw_sfence_bits_addr; // @[tile.scala:159:20]
wire _core_io_ptw_sfence_bits_asid; // @[tile.scala:159:20]
wire _core_io_ptw_status_debug; // @[tile.scala:159:20]
wire _core_io_ptw_status_cease; // @[tile.scala:159:20]
wire _core_io_ptw_status_wfi; // @[tile.scala:159:20]
wire [1:0] _core_io_ptw_status_dprv; // @[tile.scala:159:20]
wire _core_io_ptw_status_dv; // @[tile.scala:159:20]
wire [1:0] _core_io_ptw_status_prv; // @[tile.scala:159:20]
wire _core_io_ptw_status_v; // @[tile.scala:159:20]
wire _core_io_ptw_status_sd; // @[tile.scala:159:20]
wire _core_io_ptw_status_mpv; // @[tile.scala:159:20]
wire _core_io_ptw_status_gva; // @[tile.scala:159:20]
wire _core_io_ptw_status_tsr; // @[tile.scala:159:20]
wire _core_io_ptw_status_tw; // @[tile.scala:159:20]
wire _core_io_ptw_status_tvm; // @[tile.scala:159:20]
wire _core_io_ptw_status_mxr; // @[tile.scala:159:20]
wire _core_io_ptw_status_sum; // @[tile.scala:159:20]
wire _core_io_ptw_status_mprv; // @[tile.scala:159:20]
wire [1:0] _core_io_ptw_status_fs; // @[tile.scala:159:20]
wire [1:0] _core_io_ptw_status_mpp; // @[tile.scala:159:20]
wire _core_io_ptw_status_spp; // @[tile.scala:159:20]
wire _core_io_ptw_status_mpie; // @[tile.scala:159:20]
wire _core_io_ptw_status_spie; // @[tile.scala:159:20]
wire _core_io_ptw_status_mie; // @[tile.scala:159:20]
wire _core_io_ptw_status_sie; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_0_cfg_l; // @[tile.scala:159:20]
wire [1:0] _core_io_ptw_pmp_0_cfg_a; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_0_cfg_x; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_0_cfg_w; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_0_cfg_r; // @[tile.scala:159:20]
wire [29:0] _core_io_ptw_pmp_0_addr; // @[tile.scala:159:20]
wire [31:0] _core_io_ptw_pmp_0_mask; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_1_cfg_l; // @[tile.scala:159:20]
wire [1:0] _core_io_ptw_pmp_1_cfg_a; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_1_cfg_x; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_1_cfg_w; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_1_cfg_r; // @[tile.scala:159:20]
wire [29:0] _core_io_ptw_pmp_1_addr; // @[tile.scala:159:20]
wire [31:0] _core_io_ptw_pmp_1_mask; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_2_cfg_l; // @[tile.scala:159:20]
wire [1:0] _core_io_ptw_pmp_2_cfg_a; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_2_cfg_x; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_2_cfg_w; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_2_cfg_r; // @[tile.scala:159:20]
wire [29:0] _core_io_ptw_pmp_2_addr; // @[tile.scala:159:20]
wire [31:0] _core_io_ptw_pmp_2_mask; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_3_cfg_l; // @[tile.scala:159:20]
wire [1:0] _core_io_ptw_pmp_3_cfg_a; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_3_cfg_x; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_3_cfg_w; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_3_cfg_r; // @[tile.scala:159:20]
wire [29:0] _core_io_ptw_pmp_3_addr; // @[tile.scala:159:20]
wire [31:0] _core_io_ptw_pmp_3_mask; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_4_cfg_l; // @[tile.scala:159:20]
wire [1:0] _core_io_ptw_pmp_4_cfg_a; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_4_cfg_x; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_4_cfg_w; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_4_cfg_r; // @[tile.scala:159:20]
wire [29:0] _core_io_ptw_pmp_4_addr; // @[tile.scala:159:20]
wire [31:0] _core_io_ptw_pmp_4_mask; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_5_cfg_l; // @[tile.scala:159:20]
wire [1:0] _core_io_ptw_pmp_5_cfg_a; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_5_cfg_x; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_5_cfg_w; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_5_cfg_r; // @[tile.scala:159:20]
wire [29:0] _core_io_ptw_pmp_5_addr; // @[tile.scala:159:20]
wire [31:0] _core_io_ptw_pmp_5_mask; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_6_cfg_l; // @[tile.scala:159:20]
wire [1:0] _core_io_ptw_pmp_6_cfg_a; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_6_cfg_x; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_6_cfg_w; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_6_cfg_r; // @[tile.scala:159:20]
wire [29:0] _core_io_ptw_pmp_6_addr; // @[tile.scala:159:20]
wire [31:0] _core_io_ptw_pmp_6_mask; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_7_cfg_l; // @[tile.scala:159:20]
wire [1:0] _core_io_ptw_pmp_7_cfg_a; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_7_cfg_x; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_7_cfg_w; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_7_cfg_r; // @[tile.scala:159:20]
wire [29:0] _core_io_ptw_pmp_7_addr; // @[tile.scala:159:20]
wire [31:0] _core_io_ptw_pmp_7_mask; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_valid; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_exe_0_req_bits_uop_uopc; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_exe_0_req_bits_uop_inst; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_exe_0_req_bits_uop_debug_inst; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_is_rvc; // @[tile.scala:159:20]
wire [39:0] _core_io_lsu_exe_0_req_bits_uop_debug_pc; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_exe_0_req_bits_uop_iq_type; // @[tile.scala:159:20]
wire [9:0] _core_io_lsu_exe_0_req_bits_uop_fu_code; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_exe_0_req_bits_uop_ctrl_br_type; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_exe_0_req_bits_uop_ctrl_op1_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_exe_0_req_bits_uop_ctrl_op2_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_exe_0_req_bits_uop_ctrl_imm_sel; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_exe_0_req_bits_uop_ctrl_op_fcn; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_ctrl_fcn_dw; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_exe_0_req_bits_uop_ctrl_csr_cmd; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_ctrl_is_load; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_ctrl_is_sta; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_ctrl_is_std; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_exe_0_req_bits_uop_iw_state; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_iw_p1_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_iw_p2_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_is_br; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_is_jalr; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_is_jal; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_is_sfb; // @[tile.scala:159:20]
wire [15:0] _core_io_lsu_exe_0_req_bits_uop_br_mask; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_exe_0_req_bits_uop_br_tag; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_exe_0_req_bits_uop_ftq_idx; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_edge_inst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_exe_0_req_bits_uop_pc_lob; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_taken; // @[tile.scala:159:20]
wire [19:0] _core_io_lsu_exe_0_req_bits_uop_imm_packed; // @[tile.scala:159:20]
wire [11:0] _core_io_lsu_exe_0_req_bits_uop_csr_addr; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_exe_0_req_bits_uop_rob_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_exe_0_req_bits_uop_ldq_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_exe_0_req_bits_uop_stq_idx; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_exe_0_req_bits_uop_rxq_idx; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_exe_0_req_bits_uop_pdst; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_exe_0_req_bits_uop_prs1; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_exe_0_req_bits_uop_prs2; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_exe_0_req_bits_uop_prs3; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_exe_0_req_bits_uop_ppred; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_prs1_busy; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_prs2_busy; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_prs3_busy; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_ppred_busy; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_exe_0_req_bits_uop_stale_pdst; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_exception; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_exe_0_req_bits_uop_exc_cause; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_bypassable; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_exe_0_req_bits_uop_mem_cmd; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_exe_0_req_bits_uop_mem_size; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_mem_signed; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_is_fence; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_is_fencei; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_is_amo; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_uses_ldq; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_uses_stq; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_is_sys_pc2epc; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_is_unique; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_flush_on_commit; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_ldst_is_rs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_exe_0_req_bits_uop_ldst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_exe_0_req_bits_uop_lrs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_exe_0_req_bits_uop_lrs2; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_exe_0_req_bits_uop_lrs3; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_ldst_val; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_exe_0_req_bits_uop_dst_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_exe_0_req_bits_uop_lrs1_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_exe_0_req_bits_uop_lrs2_rtype; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_frs3_en; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_fp_val; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_fp_single; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_xcpt_pf_if; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_xcpt_ae_if; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_xcpt_ma_if; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_bp_debug_if; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_bp_xcpt_if; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_exe_0_req_bits_uop_debug_fsrc; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_exe_0_req_bits_uop_debug_tsrc; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_exe_0_req_bits_data; // @[tile.scala:159:20]
wire [39:0] _core_io_lsu_exe_0_req_bits_addr; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_mxcpt_valid; // @[tile.scala:159:20]
wire [24:0] _core_io_lsu_exe_0_req_bits_mxcpt_bits; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_sfence_valid; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_sfence_bits_rs1; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_sfence_bits_rs2; // @[tile.scala:159:20]
wire [38:0] _core_io_lsu_exe_0_req_bits_sfence_bits_addr; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_sfence_bits_asid; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_valid; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_0_bits_uopc; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_dis_uops_0_bits_inst; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_dis_uops_0_bits_debug_inst; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_is_rvc; // @[tile.scala:159:20]
wire [39:0] _core_io_lsu_dis_uops_0_bits_debug_pc; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_dis_uops_0_bits_iq_type; // @[tile.scala:159:20]
wire [9:0] _core_io_lsu_dis_uops_0_bits_fu_code; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_dis_uops_0_bits_ctrl_br_type; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_0_bits_ctrl_op1_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_dis_uops_0_bits_ctrl_op2_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_dis_uops_0_bits_ctrl_imm_sel; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_0_bits_ctrl_op_fcn; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_ctrl_fcn_dw; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_dis_uops_0_bits_ctrl_csr_cmd; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_ctrl_is_load; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_ctrl_is_sta; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_ctrl_is_std; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_0_bits_iw_state; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_iw_p1_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_iw_p2_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_is_br; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_is_jalr; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_is_jal; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_is_sfb; // @[tile.scala:159:20]
wire [15:0] _core_io_lsu_dis_uops_0_bits_br_mask; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_dis_uops_0_bits_br_tag; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_0_bits_ftq_idx; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_edge_inst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_0_bits_pc_lob; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_taken; // @[tile.scala:159:20]
wire [19:0] _core_io_lsu_dis_uops_0_bits_imm_packed; // @[tile.scala:159:20]
wire [11:0] _core_io_lsu_dis_uops_0_bits_csr_addr; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_0_bits_rob_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_0_bits_ldq_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_0_bits_stq_idx; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_0_bits_rxq_idx; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_0_bits_pdst; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_0_bits_prs1; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_0_bits_prs2; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_0_bits_prs3; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_prs1_busy; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_prs2_busy; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_prs3_busy; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_0_bits_stale_pdst; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_exception; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_dis_uops_0_bits_exc_cause; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_bypassable; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_0_bits_mem_cmd; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_0_bits_mem_size; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_mem_signed; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_is_fence; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_is_fencei; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_is_amo; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_uses_ldq; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_uses_stq; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_is_sys_pc2epc; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_is_unique; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_flush_on_commit; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_ldst_is_rs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_0_bits_ldst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_0_bits_lrs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_0_bits_lrs2; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_0_bits_lrs3; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_ldst_val; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_0_bits_dst_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_0_bits_lrs1_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_0_bits_lrs2_rtype; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_frs3_en; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_fp_val; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_fp_single; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_xcpt_pf_if; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_xcpt_ae_if; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_xcpt_ma_if; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_bp_debug_if; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_bp_xcpt_if; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_0_bits_debug_fsrc; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_0_bits_debug_tsrc; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_valid; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_1_bits_uopc; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_dis_uops_1_bits_inst; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_dis_uops_1_bits_debug_inst; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_is_rvc; // @[tile.scala:159:20]
wire [39:0] _core_io_lsu_dis_uops_1_bits_debug_pc; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_dis_uops_1_bits_iq_type; // @[tile.scala:159:20]
wire [9:0] _core_io_lsu_dis_uops_1_bits_fu_code; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_dis_uops_1_bits_ctrl_br_type; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_1_bits_ctrl_op1_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_dis_uops_1_bits_ctrl_op2_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_dis_uops_1_bits_ctrl_imm_sel; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_1_bits_ctrl_op_fcn; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_ctrl_fcn_dw; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_dis_uops_1_bits_ctrl_csr_cmd; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_ctrl_is_load; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_ctrl_is_sta; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_ctrl_is_std; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_1_bits_iw_state; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_iw_p1_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_iw_p2_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_is_br; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_is_jalr; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_is_jal; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_is_sfb; // @[tile.scala:159:20]
wire [15:0] _core_io_lsu_dis_uops_1_bits_br_mask; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_dis_uops_1_bits_br_tag; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_1_bits_ftq_idx; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_edge_inst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_1_bits_pc_lob; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_taken; // @[tile.scala:159:20]
wire [19:0] _core_io_lsu_dis_uops_1_bits_imm_packed; // @[tile.scala:159:20]
wire [11:0] _core_io_lsu_dis_uops_1_bits_csr_addr; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_1_bits_rob_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_1_bits_ldq_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_1_bits_stq_idx; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_1_bits_rxq_idx; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_1_bits_pdst; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_1_bits_prs1; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_1_bits_prs2; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_1_bits_prs3; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_prs1_busy; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_prs2_busy; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_prs3_busy; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_1_bits_stale_pdst; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_exception; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_dis_uops_1_bits_exc_cause; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_bypassable; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_1_bits_mem_cmd; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_1_bits_mem_size; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_mem_signed; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_is_fence; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_is_fencei; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_is_amo; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_uses_ldq; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_uses_stq; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_is_sys_pc2epc; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_is_unique; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_flush_on_commit; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_ldst_is_rs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_1_bits_ldst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_1_bits_lrs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_1_bits_lrs2; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_1_bits_lrs3; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_ldst_val; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_1_bits_dst_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_1_bits_lrs1_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_1_bits_lrs2_rtype; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_frs3_en; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_fp_val; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_fp_single; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_xcpt_pf_if; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_xcpt_ae_if; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_xcpt_ma_if; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_bp_debug_if; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_bp_xcpt_if; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_1_bits_debug_fsrc; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_1_bits_debug_tsrc; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_valid; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_2_bits_uopc; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_dis_uops_2_bits_inst; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_dis_uops_2_bits_debug_inst; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_is_rvc; // @[tile.scala:159:20]
wire [39:0] _core_io_lsu_dis_uops_2_bits_debug_pc; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_dis_uops_2_bits_iq_type; // @[tile.scala:159:20]
wire [9:0] _core_io_lsu_dis_uops_2_bits_fu_code; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_dis_uops_2_bits_ctrl_br_type; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_2_bits_ctrl_op1_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_dis_uops_2_bits_ctrl_op2_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_dis_uops_2_bits_ctrl_imm_sel; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_2_bits_ctrl_op_fcn; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_ctrl_fcn_dw; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_dis_uops_2_bits_ctrl_csr_cmd; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_ctrl_is_load; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_ctrl_is_sta; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_ctrl_is_std; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_2_bits_iw_state; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_iw_p1_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_iw_p2_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_is_br; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_is_jalr; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_is_jal; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_is_sfb; // @[tile.scala:159:20]
wire [15:0] _core_io_lsu_dis_uops_2_bits_br_mask; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_dis_uops_2_bits_br_tag; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_2_bits_ftq_idx; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_edge_inst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_2_bits_pc_lob; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_taken; // @[tile.scala:159:20]
wire [19:0] _core_io_lsu_dis_uops_2_bits_imm_packed; // @[tile.scala:159:20]
wire [11:0] _core_io_lsu_dis_uops_2_bits_csr_addr; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_2_bits_rob_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_2_bits_ldq_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_2_bits_stq_idx; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_2_bits_rxq_idx; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_2_bits_pdst; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_2_bits_prs1; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_2_bits_prs2; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_2_bits_prs3; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_prs1_busy; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_prs2_busy; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_prs3_busy; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_2_bits_stale_pdst; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_exception; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_dis_uops_2_bits_exc_cause; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_bypassable; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_2_bits_mem_cmd; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_2_bits_mem_size; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_mem_signed; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_is_fence; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_is_fencei; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_is_amo; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_uses_ldq; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_uses_stq; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_is_sys_pc2epc; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_is_unique; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_flush_on_commit; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_ldst_is_rs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_2_bits_ldst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_2_bits_lrs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_2_bits_lrs2; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_2_bits_lrs3; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_ldst_val; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_2_bits_dst_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_2_bits_lrs1_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_2_bits_lrs2_rtype; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_frs3_en; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_fp_val; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_fp_single; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_xcpt_pf_if; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_xcpt_ae_if; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_xcpt_ma_if; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_bp_debug_if; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_bp_xcpt_if; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_2_bits_debug_fsrc; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_2_bits_debug_tsrc; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_valid; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_fp_stdata_bits_uop_uopc; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_fp_stdata_bits_uop_inst; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_fp_stdata_bits_uop_debug_inst; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_is_rvc; // @[tile.scala:159:20]
wire [39:0] _core_io_lsu_fp_stdata_bits_uop_debug_pc; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_fp_stdata_bits_uop_iq_type; // @[tile.scala:159:20]
wire [9:0] _core_io_lsu_fp_stdata_bits_uop_fu_code; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_fp_stdata_bits_uop_ctrl_br_type; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_uop_ctrl_op1_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_fp_stdata_bits_uop_ctrl_op2_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_fp_stdata_bits_uop_ctrl_imm_sel; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_fp_stdata_bits_uop_ctrl_op_fcn; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_ctrl_fcn_dw; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_fp_stdata_bits_uop_ctrl_csr_cmd; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_ctrl_is_load; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_ctrl_is_sta; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_ctrl_is_std; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_uop_iw_state; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_iw_p1_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_iw_p2_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_is_br; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_is_jalr; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_is_jal; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_is_sfb; // @[tile.scala:159:20]
wire [15:0] _core_io_lsu_fp_stdata_bits_uop_br_mask; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_fp_stdata_bits_uop_br_tag; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_fp_stdata_bits_uop_ftq_idx; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_edge_inst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_fp_stdata_bits_uop_pc_lob; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_taken; // @[tile.scala:159:20]
wire [19:0] _core_io_lsu_fp_stdata_bits_uop_imm_packed; // @[tile.scala:159:20]
wire [11:0] _core_io_lsu_fp_stdata_bits_uop_csr_addr; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_fp_stdata_bits_uop_rob_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_fp_stdata_bits_uop_ldq_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_fp_stdata_bits_uop_stq_idx; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_uop_rxq_idx; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_fp_stdata_bits_uop_pdst; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_fp_stdata_bits_uop_prs1; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_fp_stdata_bits_uop_prs2; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_fp_stdata_bits_uop_prs3; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_fp_stdata_bits_uop_ppred; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_prs1_busy; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_prs2_busy; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_prs3_busy; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_ppred_busy; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_fp_stdata_bits_uop_stale_pdst; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_exception; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_fp_stdata_bits_uop_exc_cause; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_bypassable; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_fp_stdata_bits_uop_mem_cmd; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_uop_mem_size; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_mem_signed; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_is_fence; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_is_fencei; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_is_amo; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_uses_ldq; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_uses_stq; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_is_sys_pc2epc; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_is_unique; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_flush_on_commit; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_ldst_is_rs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_fp_stdata_bits_uop_ldst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_fp_stdata_bits_uop_lrs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_fp_stdata_bits_uop_lrs2; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_fp_stdata_bits_uop_lrs3; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_ldst_val; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_uop_dst_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_uop_lrs1_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_uop_lrs2_rtype; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_frs3_en; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_fp_val; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_fp_single; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_xcpt_pf_if; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_xcpt_ae_if; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_xcpt_ma_if; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_bp_debug_if; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_bp_xcpt_if; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_uop_debug_fsrc; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_uop_debug_tsrc; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_fp_stdata_bits_data; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_predicated; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_valid; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_uopc; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_inst; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_debug_inst; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_rvc; // @[tile.scala:159:20]
wire [39:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_debug_pc; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_iq_type; // @[tile.scala:159:20]
wire [9:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_fu_code; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_br_type; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op1_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op2_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_imm_sel; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op_fcn; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_fcn_dw; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_csr_cmd; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_load; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_sta; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_std; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_iw_state; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p1_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p2_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_br; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_jalr; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_jal; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_sfb; // @[tile.scala:159:20]
wire [15:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_br_mask; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_br_tag; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ftq_idx; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_edge_inst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_pc_lob; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_taken; // @[tile.scala:159:20]
wire [19:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_imm_packed; // @[tile.scala:159:20]
wire [11:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_csr_addr; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_rob_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ldq_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_stq_idx; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_rxq_idx; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_pdst; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs1; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs2; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs3; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ppred; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs1_busy; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs2_busy; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs3_busy; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ppred_busy; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_stale_pdst; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_exception; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_exc_cause; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_bypassable; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_mem_cmd; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_mem_size; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_mem_signed; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_fence; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_fencei; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_amo; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_uses_ldq; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_uses_stq; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_sys_pc2epc; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_unique; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_flush_on_commit; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_is_rs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ldst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs3; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_val; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_dst_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2_rtype; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_frs3_en; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_fp_val; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_fp_single; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_pf_if; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ae_if; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ma_if; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_bp_debug_if; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_bp_xcpt_if; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_debug_fsrc; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_debug_tsrc; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_fp_stdata_bits_fflags_bits_flags; // @[tile.scala:159:20]
wire _core_io_lsu_commit_valids_0; // @[tile.scala:159:20]
wire _core_io_lsu_commit_valids_1; // @[tile.scala:159:20]
wire _core_io_lsu_commit_valids_2; // @[tile.scala:159:20]
wire _core_io_lsu_commit_arch_valids_0; // @[tile.scala:159:20]
wire _core_io_lsu_commit_arch_valids_1; // @[tile.scala:159:20]
wire _core_io_lsu_commit_arch_valids_2; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_0_uopc; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_commit_uops_0_inst; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_commit_uops_0_debug_inst; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_is_rvc; // @[tile.scala:159:20]
wire [39:0] _core_io_lsu_commit_uops_0_debug_pc; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_commit_uops_0_iq_type; // @[tile.scala:159:20]
wire [9:0] _core_io_lsu_commit_uops_0_fu_code; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_commit_uops_0_ctrl_br_type; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_0_ctrl_op1_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_commit_uops_0_ctrl_op2_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_commit_uops_0_ctrl_imm_sel; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_0_ctrl_op_fcn; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_ctrl_fcn_dw; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_commit_uops_0_ctrl_csr_cmd; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_ctrl_is_load; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_ctrl_is_sta; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_ctrl_is_std; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_0_iw_state; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_iw_p1_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_iw_p2_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_is_br; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_is_jalr; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_is_jal; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_is_sfb; // @[tile.scala:159:20]
wire [15:0] _core_io_lsu_commit_uops_0_br_mask; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_commit_uops_0_br_tag; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_0_ftq_idx; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_edge_inst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_0_pc_lob; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_taken; // @[tile.scala:159:20]
wire [19:0] _core_io_lsu_commit_uops_0_imm_packed; // @[tile.scala:159:20]
wire [11:0] _core_io_lsu_commit_uops_0_csr_addr; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_0_rob_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_0_ldq_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_0_stq_idx; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_0_rxq_idx; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_0_pdst; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_0_prs1; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_0_prs2; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_0_prs3; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_0_ppred; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_prs1_busy; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_prs2_busy; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_prs3_busy; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_ppred_busy; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_0_stale_pdst; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_exception; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_commit_uops_0_exc_cause; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_bypassable; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_0_mem_cmd; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_0_mem_size; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_mem_signed; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_is_fence; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_is_fencei; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_is_amo; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_uses_ldq; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_uses_stq; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_is_sys_pc2epc; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_is_unique; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_flush_on_commit; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_ldst_is_rs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_0_ldst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_0_lrs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_0_lrs2; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_0_lrs3; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_ldst_val; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_0_dst_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_0_lrs1_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_0_lrs2_rtype; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_frs3_en; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_fp_val; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_fp_single; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_xcpt_pf_if; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_xcpt_ae_if; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_xcpt_ma_if; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_bp_debug_if; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_bp_xcpt_if; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_0_debug_fsrc; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_0_debug_tsrc; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_1_uopc; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_commit_uops_1_inst; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_commit_uops_1_debug_inst; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_is_rvc; // @[tile.scala:159:20]
wire [39:0] _core_io_lsu_commit_uops_1_debug_pc; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_commit_uops_1_iq_type; // @[tile.scala:159:20]
wire [9:0] _core_io_lsu_commit_uops_1_fu_code; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_commit_uops_1_ctrl_br_type; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_1_ctrl_op1_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_commit_uops_1_ctrl_op2_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_commit_uops_1_ctrl_imm_sel; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_1_ctrl_op_fcn; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_ctrl_fcn_dw; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_commit_uops_1_ctrl_csr_cmd; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_ctrl_is_load; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_ctrl_is_sta; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_ctrl_is_std; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_1_iw_state; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_iw_p1_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_iw_p2_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_is_br; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_is_jalr; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_is_jal; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_is_sfb; // @[tile.scala:159:20]
wire [15:0] _core_io_lsu_commit_uops_1_br_mask; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_commit_uops_1_br_tag; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_1_ftq_idx; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_edge_inst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_1_pc_lob; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_taken; // @[tile.scala:159:20]
wire [19:0] _core_io_lsu_commit_uops_1_imm_packed; // @[tile.scala:159:20]
wire [11:0] _core_io_lsu_commit_uops_1_csr_addr; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_1_rob_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_1_ldq_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_1_stq_idx; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_1_rxq_idx; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_1_pdst; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_1_prs1; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_1_prs2; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_1_prs3; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_1_ppred; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_prs1_busy; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_prs2_busy; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_prs3_busy; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_ppred_busy; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_1_stale_pdst; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_exception; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_commit_uops_1_exc_cause; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_bypassable; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_1_mem_cmd; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_1_mem_size; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_mem_signed; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_is_fence; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_is_fencei; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_is_amo; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_uses_ldq; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_uses_stq; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_is_sys_pc2epc; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_is_unique; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_flush_on_commit; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_ldst_is_rs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_1_ldst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_1_lrs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_1_lrs2; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_1_lrs3; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_ldst_val; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_1_dst_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_1_lrs1_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_1_lrs2_rtype; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_frs3_en; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_fp_val; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_fp_single; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_xcpt_pf_if; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_xcpt_ae_if; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_xcpt_ma_if; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_bp_debug_if; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_bp_xcpt_if; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_1_debug_fsrc; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_1_debug_tsrc; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_2_uopc; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_commit_uops_2_inst; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_commit_uops_2_debug_inst; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_is_rvc; // @[tile.scala:159:20]
wire [39:0] _core_io_lsu_commit_uops_2_debug_pc; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_commit_uops_2_iq_type; // @[tile.scala:159:20]
wire [9:0] _core_io_lsu_commit_uops_2_fu_code; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_commit_uops_2_ctrl_br_type; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_2_ctrl_op1_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_commit_uops_2_ctrl_op2_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_commit_uops_2_ctrl_imm_sel; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_2_ctrl_op_fcn; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_ctrl_fcn_dw; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_commit_uops_2_ctrl_csr_cmd; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_ctrl_is_load; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_ctrl_is_sta; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_ctrl_is_std; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_2_iw_state; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_iw_p1_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_iw_p2_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_is_br; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_is_jalr; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_is_jal; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_is_sfb; // @[tile.scala:159:20]
wire [15:0] _core_io_lsu_commit_uops_2_br_mask; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_commit_uops_2_br_tag; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_2_ftq_idx; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_edge_inst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_2_pc_lob; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_taken; // @[tile.scala:159:20]
wire [19:0] _core_io_lsu_commit_uops_2_imm_packed; // @[tile.scala:159:20]
wire [11:0] _core_io_lsu_commit_uops_2_csr_addr; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_2_rob_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_2_ldq_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_2_stq_idx; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_2_rxq_idx; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_2_pdst; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_2_prs1; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_2_prs2; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_2_prs3; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_2_ppred; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_prs1_busy; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_prs2_busy; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_prs3_busy; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_ppred_busy; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_2_stale_pdst; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_exception; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_commit_uops_2_exc_cause; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_bypassable; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_2_mem_cmd; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_2_mem_size; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_mem_signed; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_is_fence; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_is_fencei; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_is_amo; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_uses_ldq; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_uses_stq; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_is_sys_pc2epc; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_is_unique; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_flush_on_commit; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_ldst_is_rs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_2_ldst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_2_lrs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_2_lrs2; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_2_lrs3; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_ldst_val; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_2_dst_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_2_lrs1_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_2_lrs2_rtype; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_frs3_en; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_fp_val; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_fp_single; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_xcpt_pf_if; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_xcpt_ae_if; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_xcpt_ma_if; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_bp_debug_if; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_bp_xcpt_if; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_2_debug_fsrc; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_2_debug_tsrc; // @[tile.scala:159:20]
wire _core_io_lsu_commit_fflags_valid; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_fflags_bits; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_commit_debug_insts_0; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_commit_debug_insts_1; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_commit_debug_insts_2; // @[tile.scala:159:20]
wire _core_io_lsu_commit_rbk_valids_0; // @[tile.scala:159:20]
wire _core_io_lsu_commit_rbk_valids_1; // @[tile.scala:159:20]
wire _core_io_lsu_commit_rbk_valids_2; // @[tile.scala:159:20]
wire _core_io_lsu_commit_rollback; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_commit_debug_wdata_0; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_commit_debug_wdata_1; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_commit_debug_wdata_2; // @[tile.scala:159:20]
wire _core_io_lsu_commit_load_at_rob_head; // @[tile.scala:159:20]
wire _core_io_lsu_fence_dmem; // @[tile.scala:159:20]
wire [15:0] _core_io_lsu_brupdate_b1_resolve_mask; // @[tile.scala:159:20]
wire [15:0] _core_io_lsu_brupdate_b1_mispredict_mask; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_brupdate_b2_uop_uopc; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_brupdate_b2_uop_inst; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_brupdate_b2_uop_debug_inst; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_is_rvc; // @[tile.scala:159:20]
wire [39:0] _core_io_lsu_brupdate_b2_uop_debug_pc; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_brupdate_b2_uop_iq_type; // @[tile.scala:159:20]
wire [9:0] _core_io_lsu_brupdate_b2_uop_fu_code; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_brupdate_b2_uop_ctrl_br_type; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_brupdate_b2_uop_ctrl_op1_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_brupdate_b2_uop_ctrl_op2_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_brupdate_b2_uop_ctrl_imm_sel; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_brupdate_b2_uop_ctrl_op_fcn; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_ctrl_fcn_dw; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_brupdate_b2_uop_ctrl_csr_cmd; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_ctrl_is_load; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_ctrl_is_sta; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_ctrl_is_std; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_brupdate_b2_uop_iw_state; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_iw_p1_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_iw_p2_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_is_br; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_is_jalr; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_is_jal; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_is_sfb; // @[tile.scala:159:20]
wire [15:0] _core_io_lsu_brupdate_b2_uop_br_mask; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_brupdate_b2_uop_br_tag; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_brupdate_b2_uop_ftq_idx; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_edge_inst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_brupdate_b2_uop_pc_lob; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_taken; // @[tile.scala:159:20]
wire [19:0] _core_io_lsu_brupdate_b2_uop_imm_packed; // @[tile.scala:159:20]
wire [11:0] _core_io_lsu_brupdate_b2_uop_csr_addr; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_brupdate_b2_uop_rob_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_brupdate_b2_uop_ldq_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_brupdate_b2_uop_stq_idx; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_brupdate_b2_uop_rxq_idx; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_brupdate_b2_uop_pdst; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_brupdate_b2_uop_prs1; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_brupdate_b2_uop_prs2; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_brupdate_b2_uop_prs3; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_brupdate_b2_uop_ppred; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_prs1_busy; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_prs2_busy; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_prs3_busy; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_ppred_busy; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_brupdate_b2_uop_stale_pdst; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_exception; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_brupdate_b2_uop_exc_cause; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_bypassable; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_brupdate_b2_uop_mem_cmd; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_brupdate_b2_uop_mem_size; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_mem_signed; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_is_fence; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_is_fencei; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_is_amo; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_uses_ldq; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_uses_stq; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_is_sys_pc2epc; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_is_unique; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_flush_on_commit; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_ldst_is_rs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_brupdate_b2_uop_ldst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_brupdate_b2_uop_lrs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_brupdate_b2_uop_lrs2; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_brupdate_b2_uop_lrs3; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_ldst_val; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_brupdate_b2_uop_dst_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_brupdate_b2_uop_lrs1_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_brupdate_b2_uop_lrs2_rtype; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_frs3_en; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_fp_val; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_fp_single; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_xcpt_pf_if; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_xcpt_ae_if; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_xcpt_ma_if; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_bp_debug_if; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_bp_xcpt_if; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_brupdate_b2_uop_debug_fsrc; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_brupdate_b2_uop_debug_tsrc; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_valid; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_mispredict; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_taken; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_brupdate_b2_cfi_type; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_brupdate_b2_pc_sel; // @[tile.scala:159:20]
wire [39:0] _core_io_lsu_brupdate_b2_jalr_target; // @[tile.scala:159:20]
wire [20:0] _core_io_lsu_brupdate_b2_target_offset; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_rob_pnr_idx; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_rob_head_idx; // @[tile.scala:159:20]
wire _core_io_lsu_exception; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_tsc_reg; // @[tile.scala:159:20]
wire _frontend_io_cpu_fetchpacket_valid; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_0_valid; // @[tile.scala:138:28]
wire [31:0] _frontend_io_cpu_fetchpacket_bits_uops_0_bits_inst; // @[tile.scala:138:28]
wire [31:0] _frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_inst; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_0_bits_is_rvc; // @[tile.scala:138:28]
wire [39:0] _frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_pc; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_0_bits_is_sfb; // @[tile.scala:138:28]
wire [4:0] _frontend_io_cpu_fetchpacket_bits_uops_0_bits_ftq_idx; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_0_bits_edge_inst; // @[tile.scala:138:28]
wire [5:0] _frontend_io_cpu_fetchpacket_bits_uops_0_bits_pc_lob; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_0_bits_taken; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_0_bits_xcpt_pf_if; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_0_bits_xcpt_ae_if; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_0_bits_bp_debug_if; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_0_bits_bp_xcpt_if; // @[tile.scala:138:28]
wire [1:0] _frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_fsrc; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_1_valid; // @[tile.scala:138:28]
wire [31:0] _frontend_io_cpu_fetchpacket_bits_uops_1_bits_inst; // @[tile.scala:138:28]
wire [31:0] _frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_inst; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_1_bits_is_rvc; // @[tile.scala:138:28]
wire [39:0] _frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_pc; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_1_bits_is_sfb; // @[tile.scala:138:28]
wire [4:0] _frontend_io_cpu_fetchpacket_bits_uops_1_bits_ftq_idx; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_1_bits_edge_inst; // @[tile.scala:138:28]
wire [5:0] _frontend_io_cpu_fetchpacket_bits_uops_1_bits_pc_lob; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_1_bits_taken; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_1_bits_xcpt_pf_if; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_1_bits_xcpt_ae_if; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_1_bits_bp_debug_if; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_1_bits_bp_xcpt_if; // @[tile.scala:138:28]
wire [1:0] _frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_fsrc; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_2_valid; // @[tile.scala:138:28]
wire [31:0] _frontend_io_cpu_fetchpacket_bits_uops_2_bits_inst; // @[tile.scala:138:28]
wire [31:0] _frontend_io_cpu_fetchpacket_bits_uops_2_bits_debug_inst; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_2_bits_is_rvc; // @[tile.scala:138:28]
wire [39:0] _frontend_io_cpu_fetchpacket_bits_uops_2_bits_debug_pc; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_2_bits_is_sfb; // @[tile.scala:138:28]
wire [4:0] _frontend_io_cpu_fetchpacket_bits_uops_2_bits_ftq_idx; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_2_bits_edge_inst; // @[tile.scala:138:28]
wire [5:0] _frontend_io_cpu_fetchpacket_bits_uops_2_bits_pc_lob; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_2_bits_taken; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_2_bits_xcpt_pf_if; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_2_bits_xcpt_ae_if; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_2_bits_bp_debug_if; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_2_bits_bp_xcpt_if; // @[tile.scala:138:28]
wire [1:0] _frontend_io_cpu_fetchpacket_bits_uops_2_bits_debug_fsrc; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_0_entry_cfi_idx_valid; // @[tile.scala:138:28]
wire [2:0] _frontend_io_cpu_get_pc_0_entry_cfi_idx_bits; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_0_entry_cfi_taken; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_0_entry_cfi_mispredicted; // @[tile.scala:138:28]
wire [2:0] _frontend_io_cpu_get_pc_0_entry_cfi_type; // @[tile.scala:138:28]
wire [7:0] _frontend_io_cpu_get_pc_0_entry_br_mask; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_0_entry_cfi_is_call; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_0_entry_cfi_is_ret; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_0_entry_cfi_npc_plus4; // @[tile.scala:138:28]
wire [39:0] _frontend_io_cpu_get_pc_0_entry_ras_top; // @[tile.scala:138:28]
wire [4:0] _frontend_io_cpu_get_pc_0_entry_ras_idx; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_0_entry_start_bank; // @[tile.scala:138:28]
wire [39:0] _frontend_io_cpu_get_pc_0_pc; // @[tile.scala:138:28]
wire [39:0] _frontend_io_cpu_get_pc_0_com_pc; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_0_next_val; // @[tile.scala:138:28]
wire [39:0] _frontend_io_cpu_get_pc_0_next_pc; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_1_entry_cfi_idx_valid; // @[tile.scala:138:28]
wire [2:0] _frontend_io_cpu_get_pc_1_entry_cfi_idx_bits; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_1_entry_cfi_taken; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_1_entry_cfi_mispredicted; // @[tile.scala:138:28]
wire [2:0] _frontend_io_cpu_get_pc_1_entry_cfi_type; // @[tile.scala:138:28]
wire [7:0] _frontend_io_cpu_get_pc_1_entry_br_mask; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_1_entry_cfi_is_call; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_1_entry_cfi_is_ret; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_1_entry_cfi_npc_plus4; // @[tile.scala:138:28]
wire [39:0] _frontend_io_cpu_get_pc_1_entry_ras_top; // @[tile.scala:138:28]
wire [4:0] _frontend_io_cpu_get_pc_1_entry_ras_idx; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_1_entry_start_bank; // @[tile.scala:138:28]
wire [63:0] _frontend_io_cpu_get_pc_1_ghist_old_history; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_1_ghist_current_saw_branch_not_taken; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_1_ghist_new_saw_branch_not_taken; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_1_ghist_new_saw_branch_taken; // @[tile.scala:138:28]
wire [4:0] _frontend_io_cpu_get_pc_1_ghist_ras_idx; // @[tile.scala:138:28]
wire [39:0] _frontend_io_cpu_get_pc_1_pc; // @[tile.scala:138:28]
wire [39:0] _frontend_io_cpu_get_pc_1_com_pc; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_1_next_val; // @[tile.scala:138:28]
wire [39:0] _frontend_io_cpu_get_pc_1_next_pc; // @[tile.scala:138:28]
wire [39:0] _frontend_io_cpu_debug_fetch_pc_0; // @[tile.scala:138:28]
wire [39:0] _frontend_io_cpu_debug_fetch_pc_1; // @[tile.scala:138:28]
wire [39:0] _frontend_io_cpu_debug_fetch_pc_2; // @[tile.scala:138:28]
wire _frontend_io_cpu_perf_acquire; // @[tile.scala:138:28]
wire _frontend_io_cpu_perf_tlbMiss; // @[tile.scala:138:28]
wire _frontend_io_ptw_req_valid; // @[tile.scala:138:28]
wire [26:0] _frontend_io_ptw_req_bits_bits_addr; // @[tile.scala:138:28]
wire _frontend_io_ptw_req_bits_bits_need_gpa; // @[tile.scala:138:28]
wire _dcache_io_lsu_req_ready; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_valid; // @[tile.scala:132:54]
wire [6:0] _dcache_io_lsu_resp_0_bits_uop_uopc; // @[tile.scala:132:54]
wire [31:0] _dcache_io_lsu_resp_0_bits_uop_inst; // @[tile.scala:132:54]
wire [31:0] _dcache_io_lsu_resp_0_bits_uop_debug_inst; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_is_rvc; // @[tile.scala:132:54]
wire [39:0] _dcache_io_lsu_resp_0_bits_uop_debug_pc; // @[tile.scala:132:54]
wire [2:0] _dcache_io_lsu_resp_0_bits_uop_iq_type; // @[tile.scala:132:54]
wire [9:0] _dcache_io_lsu_resp_0_bits_uop_fu_code; // @[tile.scala:132:54]
wire [3:0] _dcache_io_lsu_resp_0_bits_uop_ctrl_br_type; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_resp_0_bits_uop_ctrl_op1_sel; // @[tile.scala:132:54]
wire [2:0] _dcache_io_lsu_resp_0_bits_uop_ctrl_op2_sel; // @[tile.scala:132:54]
wire [2:0] _dcache_io_lsu_resp_0_bits_uop_ctrl_imm_sel; // @[tile.scala:132:54]
wire [4:0] _dcache_io_lsu_resp_0_bits_uop_ctrl_op_fcn; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_ctrl_fcn_dw; // @[tile.scala:132:54]
wire [2:0] _dcache_io_lsu_resp_0_bits_uop_ctrl_csr_cmd; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_ctrl_is_load; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_ctrl_is_sta; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_ctrl_is_std; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_resp_0_bits_uop_iw_state; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_iw_p1_poisoned; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_iw_p2_poisoned; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_is_br; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_is_jalr; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_is_jal; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_is_sfb; // @[tile.scala:132:54]
wire [15:0] _dcache_io_lsu_resp_0_bits_uop_br_mask; // @[tile.scala:132:54]
wire [3:0] _dcache_io_lsu_resp_0_bits_uop_br_tag; // @[tile.scala:132:54]
wire [4:0] _dcache_io_lsu_resp_0_bits_uop_ftq_idx; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_edge_inst; // @[tile.scala:132:54]
wire [5:0] _dcache_io_lsu_resp_0_bits_uop_pc_lob; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_taken; // @[tile.scala:132:54]
wire [19:0] _dcache_io_lsu_resp_0_bits_uop_imm_packed; // @[tile.scala:132:54]
wire [11:0] _dcache_io_lsu_resp_0_bits_uop_csr_addr; // @[tile.scala:132:54]
wire [6:0] _dcache_io_lsu_resp_0_bits_uop_rob_idx; // @[tile.scala:132:54]
wire [4:0] _dcache_io_lsu_resp_0_bits_uop_ldq_idx; // @[tile.scala:132:54]
wire [4:0] _dcache_io_lsu_resp_0_bits_uop_stq_idx; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_resp_0_bits_uop_rxq_idx; // @[tile.scala:132:54]
wire [6:0] _dcache_io_lsu_resp_0_bits_uop_pdst; // @[tile.scala:132:54]
wire [6:0] _dcache_io_lsu_resp_0_bits_uop_prs1; // @[tile.scala:132:54]
wire [6:0] _dcache_io_lsu_resp_0_bits_uop_prs2; // @[tile.scala:132:54]
wire [6:0] _dcache_io_lsu_resp_0_bits_uop_prs3; // @[tile.scala:132:54]
wire [4:0] _dcache_io_lsu_resp_0_bits_uop_ppred; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_prs1_busy; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_prs2_busy; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_prs3_busy; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_ppred_busy; // @[tile.scala:132:54]
wire [6:0] _dcache_io_lsu_resp_0_bits_uop_stale_pdst; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_exception; // @[tile.scala:132:54]
wire [63:0] _dcache_io_lsu_resp_0_bits_uop_exc_cause; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_bypassable; // @[tile.scala:132:54]
wire [4:0] _dcache_io_lsu_resp_0_bits_uop_mem_cmd; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_resp_0_bits_uop_mem_size; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_mem_signed; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_is_fence; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_is_fencei; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_is_amo; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_uses_ldq; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_uses_stq; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_is_sys_pc2epc; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_is_unique; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_flush_on_commit; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_ldst_is_rs1; // @[tile.scala:132:54]
wire [5:0] _dcache_io_lsu_resp_0_bits_uop_ldst; // @[tile.scala:132:54]
wire [5:0] _dcache_io_lsu_resp_0_bits_uop_lrs1; // @[tile.scala:132:54]
wire [5:0] _dcache_io_lsu_resp_0_bits_uop_lrs2; // @[tile.scala:132:54]
wire [5:0] _dcache_io_lsu_resp_0_bits_uop_lrs3; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_ldst_val; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_resp_0_bits_uop_dst_rtype; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_resp_0_bits_uop_lrs1_rtype; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_resp_0_bits_uop_lrs2_rtype; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_frs3_en; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_fp_val; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_fp_single; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_xcpt_pf_if; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_xcpt_ae_if; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_xcpt_ma_if; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_bp_debug_if; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_bp_xcpt_if; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_resp_0_bits_uop_debug_fsrc; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_resp_0_bits_uop_debug_tsrc; // @[tile.scala:132:54]
wire [63:0] _dcache_io_lsu_resp_0_bits_data; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_is_hella; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_valid; // @[tile.scala:132:54]
wire [6:0] _dcache_io_lsu_nack_0_bits_uop_uopc; // @[tile.scala:132:54]
wire [31:0] _dcache_io_lsu_nack_0_bits_uop_inst; // @[tile.scala:132:54]
wire [31:0] _dcache_io_lsu_nack_0_bits_uop_debug_inst; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_is_rvc; // @[tile.scala:132:54]
wire [39:0] _dcache_io_lsu_nack_0_bits_uop_debug_pc; // @[tile.scala:132:54]
wire [2:0] _dcache_io_lsu_nack_0_bits_uop_iq_type; // @[tile.scala:132:54]
wire [9:0] _dcache_io_lsu_nack_0_bits_uop_fu_code; // @[tile.scala:132:54]
wire [3:0] _dcache_io_lsu_nack_0_bits_uop_ctrl_br_type; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_nack_0_bits_uop_ctrl_op1_sel; // @[tile.scala:132:54]
wire [2:0] _dcache_io_lsu_nack_0_bits_uop_ctrl_op2_sel; // @[tile.scala:132:54]
wire [2:0] _dcache_io_lsu_nack_0_bits_uop_ctrl_imm_sel; // @[tile.scala:132:54]
wire [4:0] _dcache_io_lsu_nack_0_bits_uop_ctrl_op_fcn; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_ctrl_fcn_dw; // @[tile.scala:132:54]
wire [2:0] _dcache_io_lsu_nack_0_bits_uop_ctrl_csr_cmd; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_ctrl_is_load; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_ctrl_is_sta; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_ctrl_is_std; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_nack_0_bits_uop_iw_state; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_iw_p1_poisoned; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_iw_p2_poisoned; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_is_br; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_is_jalr; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_is_jal; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_is_sfb; // @[tile.scala:132:54]
wire [15:0] _dcache_io_lsu_nack_0_bits_uop_br_mask; // @[tile.scala:132:54]
wire [3:0] _dcache_io_lsu_nack_0_bits_uop_br_tag; // @[tile.scala:132:54]
wire [4:0] _dcache_io_lsu_nack_0_bits_uop_ftq_idx; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_edge_inst; // @[tile.scala:132:54]
wire [5:0] _dcache_io_lsu_nack_0_bits_uop_pc_lob; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_taken; // @[tile.scala:132:54]
wire [19:0] _dcache_io_lsu_nack_0_bits_uop_imm_packed; // @[tile.scala:132:54]
wire [11:0] _dcache_io_lsu_nack_0_bits_uop_csr_addr; // @[tile.scala:132:54]
wire [6:0] _dcache_io_lsu_nack_0_bits_uop_rob_idx; // @[tile.scala:132:54]
wire [4:0] _dcache_io_lsu_nack_0_bits_uop_ldq_idx; // @[tile.scala:132:54]
wire [4:0] _dcache_io_lsu_nack_0_bits_uop_stq_idx; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_nack_0_bits_uop_rxq_idx; // @[tile.scala:132:54]
wire [6:0] _dcache_io_lsu_nack_0_bits_uop_pdst; // @[tile.scala:132:54]
wire [6:0] _dcache_io_lsu_nack_0_bits_uop_prs1; // @[tile.scala:132:54]
wire [6:0] _dcache_io_lsu_nack_0_bits_uop_prs2; // @[tile.scala:132:54]
wire [6:0] _dcache_io_lsu_nack_0_bits_uop_prs3; // @[tile.scala:132:54]
wire [4:0] _dcache_io_lsu_nack_0_bits_uop_ppred; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_prs1_busy; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_prs2_busy; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_prs3_busy; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_ppred_busy; // @[tile.scala:132:54]
wire [6:0] _dcache_io_lsu_nack_0_bits_uop_stale_pdst; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_exception; // @[tile.scala:132:54]
wire [63:0] _dcache_io_lsu_nack_0_bits_uop_exc_cause; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_bypassable; // @[tile.scala:132:54]
wire [4:0] _dcache_io_lsu_nack_0_bits_uop_mem_cmd; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_nack_0_bits_uop_mem_size; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_mem_signed; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_is_fence; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_is_fencei; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_is_amo; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_uses_ldq; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_uses_stq; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_is_sys_pc2epc; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_is_unique; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_flush_on_commit; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_ldst_is_rs1; // @[tile.scala:132:54]
wire [5:0] _dcache_io_lsu_nack_0_bits_uop_ldst; // @[tile.scala:132:54]
wire [5:0] _dcache_io_lsu_nack_0_bits_uop_lrs1; // @[tile.scala:132:54]
wire [5:0] _dcache_io_lsu_nack_0_bits_uop_lrs2; // @[tile.scala:132:54]
wire [5:0] _dcache_io_lsu_nack_0_bits_uop_lrs3; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_ldst_val; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_nack_0_bits_uop_dst_rtype; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_nack_0_bits_uop_lrs1_rtype; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_nack_0_bits_uop_lrs2_rtype; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_frs3_en; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_fp_val; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_fp_single; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_xcpt_pf_if; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_xcpt_ae_if; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_xcpt_ma_if; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_bp_debug_if; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_bp_xcpt_if; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_nack_0_bits_uop_debug_fsrc; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_nack_0_bits_uop_debug_tsrc; // @[tile.scala:132:54]
wire [39:0] _dcache_io_lsu_nack_0_bits_addr; // @[tile.scala:132:54]
wire [63:0] _dcache_io_lsu_nack_0_bits_data; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_is_hella; // @[tile.scala:132:54]
wire _dcache_io_lsu_release_valid; // @[tile.scala:132:54]
wire [2:0] _dcache_io_lsu_release_bits_opcode; // @[tile.scala:132:54]
wire [2:0] _dcache_io_lsu_release_bits_param; // @[tile.scala:132:54]
wire [3:0] _dcache_io_lsu_release_bits_size; // @[tile.scala:132:54]
wire [2:0] _dcache_io_lsu_release_bits_source; // @[tile.scala:132:54]
wire [31:0] _dcache_io_lsu_release_bits_address; // @[tile.scala:132:54]
wire [127:0] _dcache_io_lsu_release_bits_data; // @[tile.scala:132:54]
wire _dcache_io_lsu_ordered; // @[tile.scala:132:54]
wire _dcache_io_lsu_perf_acquire; // @[tile.scala:132:54]
wire _dcache_io_lsu_perf_release; // @[tile.scala:132:54]
wire auto_buffer_out_a_ready_0 = auto_buffer_out_a_ready; // @[tile.scala:155:7]
wire auto_buffer_out_b_valid_0 = auto_buffer_out_b_valid; // @[tile.scala:155:7]
wire [2:0] auto_buffer_out_b_bits_opcode_0 = auto_buffer_out_b_bits_opcode; // @[tile.scala:155:7]
wire [1:0] auto_buffer_out_b_bits_param_0 = auto_buffer_out_b_bits_param; // @[tile.scala:155:7]
wire [3:0] auto_buffer_out_b_bits_size_0 = auto_buffer_out_b_bits_size; // @[tile.scala:155:7]
wire [3:0] auto_buffer_out_b_bits_source_0 = auto_buffer_out_b_bits_source; // @[tile.scala:155:7]
wire [31:0] auto_buffer_out_b_bits_address_0 = auto_buffer_out_b_bits_address; // @[tile.scala:155:7]
wire [15:0] auto_buffer_out_b_bits_mask_0 = auto_buffer_out_b_bits_mask; // @[tile.scala:155:7]
wire [127:0] auto_buffer_out_b_bits_data_0 = auto_buffer_out_b_bits_data; // @[tile.scala:155:7]
wire auto_buffer_out_b_bits_corrupt_0 = auto_buffer_out_b_bits_corrupt; // @[tile.scala:155:7]
wire auto_buffer_out_c_ready_0 = auto_buffer_out_c_ready; // @[tile.scala:155:7]
wire auto_buffer_out_d_valid_0 = auto_buffer_out_d_valid; // @[tile.scala:155:7]
wire [2:0] auto_buffer_out_d_bits_opcode_0 = auto_buffer_out_d_bits_opcode; // @[tile.scala:155:7]
wire [1:0] auto_buffer_out_d_bits_param_0 = auto_buffer_out_d_bits_param; // @[tile.scala:155:7]
wire [3:0] auto_buffer_out_d_bits_size_0 = auto_buffer_out_d_bits_size; // @[tile.scala:155:7]
wire [3:0] auto_buffer_out_d_bits_source_0 = auto_buffer_out_d_bits_source; // @[tile.scala:155:7]
wire [3:0] auto_buffer_out_d_bits_sink_0 = auto_buffer_out_d_bits_sink; // @[tile.scala:155:7]
wire auto_buffer_out_d_bits_denied_0 = auto_buffer_out_d_bits_denied; // @[tile.scala:155:7]
wire [127:0] auto_buffer_out_d_bits_data_0 = auto_buffer_out_d_bits_data; // @[tile.scala:155:7]
wire auto_buffer_out_d_bits_corrupt_0 = auto_buffer_out_d_bits_corrupt; // @[tile.scala:155:7]
wire auto_buffer_out_e_ready_0 = auto_buffer_out_e_ready; // @[tile.scala:155:7]
wire auto_int_local_in_3_0_0 = auto_int_local_in_3_0; // @[tile.scala:155:7]
wire auto_int_local_in_2_0_0 = auto_int_local_in_2_0; // @[tile.scala:155:7]
wire auto_int_local_in_1_0_0 = auto_int_local_in_1_0; // @[tile.scala:155:7]
wire auto_int_local_in_1_1_0 = auto_int_local_in_1_1; // @[tile.scala:155:7]
wire auto_int_local_in_0_0_0 = auto_int_local_in_0_0; // @[tile.scala:155:7]
wire [1:0] auto_hartid_in_0 = auto_hartid_in; // @[tile.scala:155:7]
wire auto_buffer_out_a_bits_corrupt = 1'h0; // @[tile.scala:155:7]
wire auto_buffer_out_c_bits_corrupt = 1'h0; // @[tile.scala:155:7]
wire auto_wfi_out_0 = 1'h0; // @[tile.scala:155:7]
wire auto_cease_out_0 = 1'h0; // @[tile.scala:155:7]
wire auto_halt_out_0 = 1'h0; // @[tile.scala:155:7]
wire auto_trace_core_source_out_group_0_iretire = 1'h0; // @[tile.scala:155:7]
wire auto_trace_core_source_out_group_0_ilastsize = 1'h0; // @[tile.scala:155:7]
wire auto_trace_source_out_insns_0_valid = 1'h0; // @[tile.scala:155:7]
wire auto_trace_source_out_insns_0_exception = 1'h0; // @[tile.scala:155:7]
wire auto_trace_source_out_insns_0_interrupt = 1'h0; // @[tile.scala:155:7]
wire auto_trace_source_out_insns_1_valid = 1'h0; // @[tile.scala:155:7]
wire auto_trace_source_out_insns_1_exception = 1'h0; // @[tile.scala:155:7]
wire auto_trace_source_out_insns_1_interrupt = 1'h0; // @[tile.scala:155:7]
wire auto_trace_source_out_insns_2_valid = 1'h0; // @[tile.scala:155:7]
wire auto_trace_source_out_insns_2_exception = 1'h0; // @[tile.scala:155:7]
wire auto_trace_source_out_insns_2_interrupt = 1'h0; // @[tile.scala:155:7]
wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire broadcast_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire broadcast_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire broadcast_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire nexus_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire nexus_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire nexus__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire nexus_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire nexus_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire nexus_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire nexus_1_x1_bundleOut_x_sourceOpt_enable = 1'h0; // @[BaseTile.scala:305:19]
wire nexus_1_x1_bundleOut_x_sourceOpt_stall = 1'h0; // @[BaseTile.scala:305:19]
wire nexus_1_nodeOut_enable = 1'h0; // @[MixedNode.scala:542:17]
wire nexus_1_nodeOut_stall = 1'h0; // @[MixedNode.scala:542:17]
wire nexus_1_defaultWireOpt_enable = 1'h0; // @[BaseTile.scala:305:19]
wire nexus_1_defaultWireOpt_stall = 1'h0; // @[BaseTile.scala:305:19]
wire broadcast_2_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire broadcast_2_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire broadcast_2__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire widget_auto_anon_in_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_c_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_c_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire widget_anonOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire widget_anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire widget_anonIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire widget_1_auto_anon_in_a_bits_source = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_d_bits_source = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_a_bits_source = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_d_bits_source = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_1_anonOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire widget_1_anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire widget_1_anonOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire widget_1_anonIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire widget_1_anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire widget_1_anonIn_d_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire buffer_auto_in_a_bits_corrupt = 1'h0; // @[Buffer.scala:40:9]
wire buffer_auto_in_c_bits_corrupt = 1'h0; // @[Buffer.scala:40:9]
wire buffer_auto_out_a_bits_corrupt = 1'h0; // @[Buffer.scala:40:9]
wire buffer_auto_out_c_bits_corrupt = 1'h0; // @[Buffer.scala:40:9]
wire buffer_nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire buffer_nodeOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire buffer_nodeIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire tlOtherMastersNodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire tlOtherMastersNodeIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire traceSourceNodeOut_insns_0_valid = 1'h0; // @[MixedNode.scala:542:17]
wire traceSourceNodeOut_insns_0_exception = 1'h0; // @[MixedNode.scala:542:17]
wire traceSourceNodeOut_insns_0_interrupt = 1'h0; // @[MixedNode.scala:542:17]
wire traceSourceNodeOut_insns_1_valid = 1'h0; // @[MixedNode.scala:542:17]
wire traceSourceNodeOut_insns_1_exception = 1'h0; // @[MixedNode.scala:542:17]
wire traceSourceNodeOut_insns_1_interrupt = 1'h0; // @[MixedNode.scala:542:17]
wire traceSourceNodeOut_insns_2_valid = 1'h0; // @[MixedNode.scala:542:17]
wire traceSourceNodeOut_insns_2_exception = 1'h0; // @[MixedNode.scala:542:17]
wire traceSourceNodeOut_insns_2_interrupt = 1'h0; // @[MixedNode.scala:542:17]
wire traceCoreSourceNodeOut_group_0_iretire = 1'h0; // @[MixedNode.scala:542:17]
wire traceCoreSourceNodeOut_group_0_ilastsize = 1'h0; // @[MixedNode.scala:542:17]
wire bundleIn_x_sourceOpt_enable = 1'h0; // @[BaseTile.scala:305:19]
wire bundleIn_x_sourceOpt_stall = 1'h0; // @[BaseTile.scala:305:19]
wire traceAuxSinkNodeIn_enable = 1'h0; // @[MixedNode.scala:551:17]
wire traceAuxSinkNodeIn_stall = 1'h0; // @[MixedNode.scala:551:17]
wire haltNodeOut_0 = 1'h0; // @[MixedNode.scala:542:17]
wire ceaseNodeOut_0 = 1'h0; // @[MixedNode.scala:542:17]
wire wfiNodeOut_0 = 1'h0; // @[MixedNode.scala:542:17]
wire masterNodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire masterNodeOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire masterNodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire masterNodeIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire dCacheTapOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire dCacheTapOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire dCacheTapIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire dCacheTapIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire [2:0] widget_1_auto_anon_in_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_auto_anon_out_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_anonOut_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_anonIn_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_auto_anon_in_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_auto_anon_out_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_anonOut_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_anonIn_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9]
wire [15:0] widget_1_auto_anon_in_a_bits_mask = 16'hFFFF; // @[WidthWidget.scala:27:9]
wire [15:0] widget_1_auto_anon_out_a_bits_mask = 16'hFFFF; // @[WidthWidget.scala:27:9]
wire [15:0] widget_1_anonOut_a_bits_mask = 16'hFFFF; // @[WidthWidget.scala:27:9]
wire [15:0] widget_1_anonIn_a_bits_mask = 16'hFFFF; // @[WidthWidget.scala:27:9]
wire [127:0] widget_1_auto_anon_in_a_bits_data = 128'h0; // @[WidthWidget.scala:27:9]
wire [127:0] widget_1_auto_anon_out_a_bits_data = 128'h0; // @[WidthWidget.scala:27:9]
wire [127:0] widget_1_anonOut_a_bits_data = 128'h0; // @[WidthWidget.scala:27:9]
wire [127:0] widget_1_anonIn_a_bits_data = 128'h0; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_d_ready = 1'h1; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_d_ready = 1'h1; // @[WidthWidget.scala:27:9]
wire widget_1_anonOut_d_ready = 1'h1; // @[WidthWidget.scala:27:9]
wire widget_1_anonIn_d_ready = 1'h1; // @[WidthWidget.scala:27:9]
wire [31:0] auto_reset_vector_in = 32'h10000; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] broadcast_1_auto_in = 32'h10000; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] broadcast_1_auto_out_1 = 32'h10000; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] broadcast_1_auto_out_0 = 32'h10000; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] broadcast_1_nodeIn = 32'h10000; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] broadcast_1_nodeOut = 32'h10000; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] broadcast_1_x1_nodeOut = 32'h10000; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] resetVectorSinkNodeIn = 32'h10000; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] reset_vectorOut = 32'h10000; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] reset_vectorIn = 32'h10000; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] auto_trace_source_out_insns_0_cause = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] auto_trace_source_out_insns_1_cause = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] auto_trace_source_out_insns_2_cause = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] traceSourceNodeOut_insns_0_cause = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] traceSourceNodeOut_insns_1_cause = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] traceSourceNodeOut_insns_2_cause = 64'h0; // @[MixedNode.scala:542:17]
wire [2:0] auto_trace_source_out_insns_0_priv = 3'h0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_trace_source_out_insns_1_priv = 3'h0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_trace_source_out_insns_2_priv = 3'h0; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_auto_anon_in_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_auto_anon_out_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_anonOut_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_anonIn_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9]
wire [2:0] traceSourceNodeOut_insns_0_priv = 3'h0; // @[WidthWidget.scala:27:9]
wire [2:0] traceSourceNodeOut_insns_1_priv = 3'h0; // @[WidthWidget.scala:27:9]
wire [2:0] traceSourceNodeOut_insns_2_priv = 3'h0; // @[WidthWidget.scala:27:9]
wire [39:0] auto_trace_source_out_insns_0_iaddr = 40'h0; // @[MixedNode.scala:542:17]
wire [39:0] auto_trace_source_out_insns_0_tval = 40'h0; // @[MixedNode.scala:542:17]
wire [39:0] auto_trace_source_out_insns_1_iaddr = 40'h0; // @[MixedNode.scala:542:17]
wire [39:0] auto_trace_source_out_insns_1_tval = 40'h0; // @[MixedNode.scala:542:17]
wire [39:0] auto_trace_source_out_insns_2_iaddr = 40'h0; // @[MixedNode.scala:542:17]
wire [39:0] auto_trace_source_out_insns_2_tval = 40'h0; // @[MixedNode.scala:542:17]
wire [39:0] traceSourceNodeOut_insns_0_iaddr = 40'h0; // @[MixedNode.scala:542:17]
wire [39:0] traceSourceNodeOut_insns_0_tval = 40'h0; // @[MixedNode.scala:542:17]
wire [39:0] traceSourceNodeOut_insns_1_iaddr = 40'h0; // @[MixedNode.scala:542:17]
wire [39:0] traceSourceNodeOut_insns_1_tval = 40'h0; // @[MixedNode.scala:542:17]
wire [39:0] traceSourceNodeOut_insns_2_iaddr = 40'h0; // @[MixedNode.scala:542:17]
wire [39:0] traceSourceNodeOut_insns_2_tval = 40'h0; // @[MixedNode.scala:542:17]
wire [3:0] auto_trace_core_source_out_group_0_itype = 4'h0; // @[tile.scala:155:7]
wire [3:0] auto_trace_core_source_out_priv = 4'h0; // @[tile.scala:155:7]
wire [3:0] traceCoreSourceNodeOut_group_0_itype = 4'h0; // @[MixedNode.scala:542:17]
wire [3:0] traceCoreSourceNodeOut_priv = 4'h0; // @[MixedNode.scala:542:17]
wire [31:0] auto_trace_core_source_out_group_0_iaddr = 32'h0; // @[tile.scala:155:7]
wire [31:0] auto_trace_core_source_out_tval = 32'h0; // @[tile.scala:155:7]
wire [31:0] auto_trace_core_source_out_cause = 32'h0; // @[tile.scala:155:7]
wire [31:0] auto_trace_source_out_insns_0_insn = 32'h0; // @[tile.scala:155:7]
wire [31:0] auto_trace_source_out_insns_1_insn = 32'h0; // @[tile.scala:155:7]
wire [31:0] auto_trace_source_out_insns_2_insn = 32'h0; // @[tile.scala:155:7]
wire [31:0] traceSourceNodeOut_insns_0_insn = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] traceSourceNodeOut_insns_1_insn = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] traceSourceNodeOut_insns_2_insn = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] traceCoreSourceNodeOut_group_0_iaddr = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] traceCoreSourceNodeOut_tval = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] traceCoreSourceNodeOut_cause = 32'h0; // @[MixedNode.scala:542:17]
wire buffer_auto_out_a_ready = auto_buffer_out_a_ready_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_a_valid; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9]
wire [15:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9]
wire [127:0] buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9]
wire buffer_auto_out_b_ready; // @[Buffer.scala:40:9]
wire buffer_auto_out_b_valid = auto_buffer_out_b_valid_0; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_b_bits_opcode = auto_buffer_out_b_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_out_b_bits_param = auto_buffer_out_b_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_b_bits_size = auto_buffer_out_b_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_b_bits_source = auto_buffer_out_b_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] buffer_auto_out_b_bits_address = auto_buffer_out_b_bits_address_0; // @[Buffer.scala:40:9]
wire [15:0] buffer_auto_out_b_bits_mask = auto_buffer_out_b_bits_mask_0; // @[Buffer.scala:40:9]
wire [127:0] buffer_auto_out_b_bits_data = auto_buffer_out_b_bits_data_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_b_bits_corrupt = auto_buffer_out_b_bits_corrupt_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_c_ready = auto_buffer_out_c_ready_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_c_valid; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_c_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_c_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_c_bits_size; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_c_bits_source; // @[Buffer.scala:40:9]
wire [31:0] buffer_auto_out_c_bits_address; // @[Buffer.scala:40:9]
wire [127:0] buffer_auto_out_c_bits_data; // @[Buffer.scala:40:9]
wire buffer_auto_out_d_ready; // @[Buffer.scala:40:9]
wire buffer_auto_out_d_valid = auto_buffer_out_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_d_bits_opcode = auto_buffer_out_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_out_d_bits_param = auto_buffer_out_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_d_bits_size = auto_buffer_out_d_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_d_bits_source = auto_buffer_out_d_bits_source_0; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_d_bits_sink = auto_buffer_out_d_bits_sink_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_d_bits_denied = auto_buffer_out_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [127:0] buffer_auto_out_d_bits_data = auto_buffer_out_d_bits_data_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_d_bits_corrupt = auto_buffer_out_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_e_ready = auto_buffer_out_e_ready_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_e_valid; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_e_bits_sink; // @[Buffer.scala:40:9]
wire x1_int_localIn_2_0 = auto_int_local_in_3_0_0; // @[MixedNode.scala:551:17]
wire x1_int_localIn_1_0 = auto_int_local_in_2_0_0; // @[MixedNode.scala:551:17]
wire x1_int_localIn_0 = auto_int_local_in_1_0_0; // @[MixedNode.scala:551:17]
wire x1_int_localIn_1 = auto_int_local_in_1_1_0; // @[MixedNode.scala:551:17]
wire int_localIn_0 = auto_int_local_in_0_0_0; // @[MixedNode.scala:551:17]
wire [63:0] traceSourceNodeOut_time; // @[MixedNode.scala:542:17]
wire traceSourceNodeOut_custom_rob_empty; // @[MixedNode.scala:542:17]
wire [1:0] hartidIn = auto_hartid_in_0; // @[MixedNode.scala:551:17]
wire [2:0] auto_buffer_out_a_bits_opcode_0; // @[tile.scala:155:7]
wire [2:0] auto_buffer_out_a_bits_param_0; // @[tile.scala:155:7]
wire [3:0] auto_buffer_out_a_bits_size_0; // @[tile.scala:155:7]
wire [3:0] auto_buffer_out_a_bits_source_0; // @[tile.scala:155:7]
wire [31:0] auto_buffer_out_a_bits_address_0; // @[tile.scala:155:7]
wire [15:0] auto_buffer_out_a_bits_mask_0; // @[tile.scala:155:7]
wire [127:0] auto_buffer_out_a_bits_data_0; // @[tile.scala:155:7]
wire auto_buffer_out_a_valid_0; // @[tile.scala:155:7]
wire auto_buffer_out_b_ready_0; // @[tile.scala:155:7]
wire [2:0] auto_buffer_out_c_bits_opcode_0; // @[tile.scala:155:7]
wire [2:0] auto_buffer_out_c_bits_param_0; // @[tile.scala:155:7]
wire [3:0] auto_buffer_out_c_bits_size_0; // @[tile.scala:155:7]
wire [3:0] auto_buffer_out_c_bits_source_0; // @[tile.scala:155:7]
wire [31:0] auto_buffer_out_c_bits_address_0; // @[tile.scala:155:7]
wire [127:0] auto_buffer_out_c_bits_data_0; // @[tile.scala:155:7]
wire auto_buffer_out_c_valid_0; // @[tile.scala:155:7]
wire auto_buffer_out_d_ready_0; // @[tile.scala:155:7]
wire [3:0] auto_buffer_out_e_bits_sink_0; // @[tile.scala:155:7]
wire auto_buffer_out_e_valid_0; // @[tile.scala:155:7]
wire auto_trace_source_out_custom_rob_empty_0; // @[tile.scala:155:7]
wire [63:0] auto_trace_source_out_time_0; // @[tile.scala:155:7]
wire [1:0] hartidOut; // @[MixedNode.scala:542:17]
wire [1:0] broadcast_nodeIn = broadcast_auto_in; // @[MixedNode.scala:551:17]
wire [1:0] broadcast_nodeOut; // @[MixedNode.scala:542:17]
wire [1:0] broadcast_auto_out; // @[BundleBridgeNexus.scala:20:9]
wire [1:0] hartIdSinkNodeIn = broadcast_auto_out; // @[MixedNode.scala:551:17]
assign broadcast_nodeOut = broadcast_nodeIn; // @[MixedNode.scala:542:17, :551:17]
assign broadcast_auto_out = broadcast_nodeOut; // @[MixedNode.scala:542:17]
wire widget_anonIn_a_ready; // @[MixedNode.scala:551:17]
wire widget_anonIn_a_valid = widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_a_bits_opcode = widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_a_bits_param = widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_anonIn_a_bits_size = widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_a_bits_source = widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] widget_anonIn_a_bits_address = widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [15:0] widget_anonIn_a_bits_mask = widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [127:0] widget_anonIn_a_bits_data = widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire widget_anonIn_b_ready = widget_auto_anon_in_b_ready; // @[WidthWidget.scala:27:9]
wire widget_anonIn_b_valid; // @[MixedNode.scala:551:17]
wire [2:0] widget_anonIn_b_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] widget_anonIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] widget_anonIn_b_bits_size; // @[MixedNode.scala:551:17]
wire [2:0] widget_anonIn_b_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] widget_anonIn_b_bits_address; // @[MixedNode.scala:551:17]
wire [15:0] widget_anonIn_b_bits_mask; // @[MixedNode.scala:551:17]
wire [127:0] widget_anonIn_b_bits_data; // @[MixedNode.scala:551:17]
wire widget_anonIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
wire widget_anonIn_c_ready; // @[MixedNode.scala:551:17]
wire widget_anonIn_c_valid = widget_auto_anon_in_c_valid; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_c_bits_opcode = widget_auto_anon_in_c_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_c_bits_param = widget_auto_anon_in_c_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_anonIn_c_bits_size = widget_auto_anon_in_c_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_c_bits_source = widget_auto_anon_in_c_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] widget_anonIn_c_bits_address = widget_auto_anon_in_c_bits_address; // @[WidthWidget.scala:27:9]
wire [127:0] widget_anonIn_c_bits_data = widget_auto_anon_in_c_bits_data; // @[WidthWidget.scala:27:9]
wire widget_anonIn_d_ready = widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire widget_anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [2:0] widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [127:0] widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire widget_anonIn_e_ready; // @[MixedNode.scala:551:17]
wire widget_anonIn_e_valid = widget_auto_anon_in_e_valid; // @[WidthWidget.scala:27:9]
wire [3:0] widget_anonIn_e_bits_sink = widget_auto_anon_in_e_bits_sink; // @[WidthWidget.scala:27:9]
wire dCacheTapIn_a_ready; // @[MixedNode.scala:551:17]
wire widget_anonOut_a_ready = widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire widget_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire dCacheTapIn_a_valid = widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapIn_a_bits_opcode = widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [3:0] widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapIn_a_bits_param = widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [3:0] dCacheTapIn_a_bits_size = widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
wire [31:0] widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapIn_a_bits_source = widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
wire [15:0] widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [31:0] dCacheTapIn_a_bits_address = widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire [127:0] widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire [15:0] dCacheTapIn_a_bits_mask = widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [127:0] dCacheTapIn_a_bits_data = widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9]
wire widget_anonOut_b_ready; // @[MixedNode.scala:542:17]
wire dCacheTapIn_b_ready = widget_auto_anon_out_b_ready; // @[WidthWidget.scala:27:9]
wire dCacheTapIn_b_valid; // @[MixedNode.scala:551:17]
wire widget_anonOut_b_valid = widget_auto_anon_out_b_valid; // @[WidthWidget.scala:27:9]
wire [2:0] dCacheTapIn_b_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] widget_anonOut_b_bits_opcode = widget_auto_anon_out_b_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] dCacheTapIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [1:0] widget_anonOut_b_bits_param = widget_auto_anon_out_b_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] dCacheTapIn_b_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] widget_anonOut_b_bits_size = widget_auto_anon_out_b_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] dCacheTapIn_b_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] widget_anonOut_b_bits_source = widget_auto_anon_out_b_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] dCacheTapIn_b_bits_address; // @[MixedNode.scala:551:17]
wire [31:0] widget_anonOut_b_bits_address = widget_auto_anon_out_b_bits_address; // @[WidthWidget.scala:27:9]
wire [15:0] dCacheTapIn_b_bits_mask; // @[MixedNode.scala:551:17]
wire [15:0] widget_anonOut_b_bits_mask = widget_auto_anon_out_b_bits_mask; // @[WidthWidget.scala:27:9]
wire [127:0] dCacheTapIn_b_bits_data; // @[MixedNode.scala:551:17]
wire [127:0] widget_anonOut_b_bits_data = widget_auto_anon_out_b_bits_data; // @[WidthWidget.scala:27:9]
wire dCacheTapIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
wire widget_anonOut_b_bits_corrupt = widget_auto_anon_out_b_bits_corrupt; // @[WidthWidget.scala:27:9]
wire dCacheTapIn_c_ready; // @[MixedNode.scala:551:17]
wire widget_anonOut_c_ready = widget_auto_anon_out_c_ready; // @[WidthWidget.scala:27:9]
wire widget_anonOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] widget_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire dCacheTapIn_c_valid = widget_auto_anon_out_c_valid; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapIn_c_bits_opcode = widget_auto_anon_out_c_bits_opcode; // @[WidthWidget.scala:27:9]
wire [3:0] widget_anonOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapIn_c_bits_param = widget_auto_anon_out_c_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [3:0] dCacheTapIn_c_bits_size = widget_auto_anon_out_c_bits_size; // @[WidthWidget.scala:27:9]
wire [31:0] widget_anonOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapIn_c_bits_source = widget_auto_anon_out_c_bits_source; // @[WidthWidget.scala:27:9]
wire [127:0] widget_anonOut_c_bits_data; // @[MixedNode.scala:542:17]
wire [31:0] dCacheTapIn_c_bits_address = widget_auto_anon_out_c_bits_address; // @[WidthWidget.scala:27:9]
wire [127:0] dCacheTapIn_c_bits_data = widget_auto_anon_out_c_bits_data; // @[WidthWidget.scala:27:9]
wire widget_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire dCacheTapIn_d_ready = widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9]
wire dCacheTapIn_d_valid; // @[MixedNode.scala:551:17]
wire widget_anonOut_d_valid = widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] dCacheTapIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] widget_anonOut_d_bits_opcode = widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] dCacheTapIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [1:0] widget_anonOut_d_bits_param = widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] dCacheTapIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] widget_anonOut_d_bits_size = widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] dCacheTapIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] widget_anonOut_d_bits_source = widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] dCacheTapIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire [3:0] widget_anonOut_d_bits_sink = widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire dCacheTapIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire widget_anonOut_d_bits_denied = widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [127:0] dCacheTapIn_d_bits_data; // @[MixedNode.scala:551:17]
wire [127:0] widget_anonOut_d_bits_data = widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire dCacheTapIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire widget_anonOut_d_bits_corrupt = widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire dCacheTapIn_e_ready; // @[MixedNode.scala:551:17]
wire widget_anonOut_e_ready = widget_auto_anon_out_e_ready; // @[WidthWidget.scala:27:9]
wire widget_anonOut_e_valid; // @[MixedNode.scala:542:17]
wire [3:0] widget_anonOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire dCacheTapIn_e_valid = widget_auto_anon_out_e_valid; // @[WidthWidget.scala:27:9]
wire [3:0] dCacheTapIn_e_bits_sink = widget_auto_anon_out_e_bits_sink; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_b_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] widget_auto_anon_in_b_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_in_b_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_b_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] widget_auto_anon_in_b_bits_address; // @[WidthWidget.scala:27:9]
wire [15:0] widget_auto_anon_in_b_bits_mask; // @[WidthWidget.scala:27:9]
wire [127:0] widget_auto_anon_in_b_bits_data; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_b_bits_corrupt; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_b_valid; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_c_ready; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [127:0] widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_e_ready; // @[WidthWidget.scala:27:9]
assign widget_anonIn_a_ready = widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_out_a_valid = widget_anonOut_a_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_opcode = widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_param = widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_size = widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_source = widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_address = widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_mask = widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_data = widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_b_ready = widget_anonOut_b_ready; // @[WidthWidget.scala:27:9]
assign widget_anonIn_b_valid = widget_anonOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_opcode = widget_anonOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_param = widget_anonOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_size = widget_anonOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_source = widget_anonOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_address = widget_anonOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_mask = widget_anonOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_data = widget_anonOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_corrupt = widget_anonOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_c_ready = widget_anonOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_out_c_valid = widget_anonOut_c_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_c_bits_opcode = widget_anonOut_c_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_c_bits_param = widget_anonOut_c_bits_param; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_c_bits_size = widget_anonOut_c_bits_size; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_c_bits_source = widget_anonOut_c_bits_source; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_c_bits_address = widget_anonOut_c_bits_address; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_c_bits_data = widget_anonOut_c_bits_data; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_d_ready = widget_anonOut_d_ready; // @[WidthWidget.scala:27:9]
assign widget_anonIn_d_valid = widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_opcode = widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_param = widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_size = widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_source = widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_sink = widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_denied = widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_data = widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_corrupt = widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_e_ready = widget_anonOut_e_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_out_e_valid = widget_anonOut_e_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_e_bits_sink = widget_anonOut_e_bits_sink; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_a_ready = widget_anonIn_a_ready; // @[WidthWidget.scala:27:9]
assign widget_anonOut_a_valid = widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_opcode = widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_param = widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_size = widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_source = widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_address = widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_mask = widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_data = widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_b_ready = widget_anonIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_in_b_valid = widget_anonIn_b_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_opcode = widget_anonIn_b_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_param = widget_anonIn_b_bits_param; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_size = widget_anonIn_b_bits_size; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_source = widget_anonIn_b_bits_source; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_address = widget_anonIn_b_bits_address; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_mask = widget_anonIn_b_bits_mask; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_data = widget_anonIn_b_bits_data; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_corrupt = widget_anonIn_b_bits_corrupt; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_c_ready = widget_anonIn_c_ready; // @[WidthWidget.scala:27:9]
assign widget_anonOut_c_valid = widget_anonIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_c_bits_opcode = widget_anonIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_c_bits_param = widget_anonIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_c_bits_size = widget_anonIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_c_bits_source = widget_anonIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_c_bits_address = widget_anonIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_c_bits_data = widget_anonIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_d_ready = widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_in_d_valid = widget_anonIn_d_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_opcode = widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_param = widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_size = widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_source = widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_sink = widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_denied = widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_data = widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_corrupt = widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_e_ready = widget_anonIn_e_ready; // @[WidthWidget.scala:27:9]
assign widget_anonOut_e_valid = widget_anonIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_e_bits_sink = widget_anonIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire widget_1_anonIn_a_ready; // @[MixedNode.scala:551:17]
wire widget_1_anonIn_a_valid = widget_1_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [31:0] widget_1_anonIn_a_bits_address = widget_1_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire widget_1_anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] widget_1_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] widget_1_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] widget_1_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] widget_1_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire widget_1_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [127:0] widget_1_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire widget_1_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire widget_1_anonOut_a_ready = widget_1_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire widget_1_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [31:0] widget_1_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire widget_1_anonOut_d_valid = widget_1_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_anonOut_d_bits_opcode = widget_1_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] widget_1_anonOut_d_bits_param = widget_1_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_anonOut_d_bits_size = widget_1_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_anonOut_d_bits_sink = widget_1_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire widget_1_anonOut_d_bits_denied = widget_1_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [127:0] widget_1_anonOut_d_bits_data = widget_1_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire widget_1_anonOut_d_bits_corrupt = widget_1_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] widget_1_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [127:0] widget_1_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire [31:0] widget_1_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
assign widget_1_anonIn_a_ready = widget_1_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_auto_anon_out_a_valid = widget_1_anonOut_a_valid; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_out_a_bits_address = widget_1_anonOut_a_bits_address; // @[WidthWidget.scala:27:9]
assign widget_1_anonIn_d_valid = widget_1_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_opcode = widget_1_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_param = widget_1_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_size = widget_1_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_sink = widget_1_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_denied = widget_1_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_data = widget_1_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_corrupt = widget_1_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_auto_anon_in_a_ready = widget_1_anonIn_a_ready; // @[WidthWidget.scala:27:9]
assign widget_1_anonOut_a_valid = widget_1_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonOut_a_bits_address = widget_1_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_auto_anon_in_d_valid = widget_1_anonIn_d_valid; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_opcode = widget_1_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_param = widget_1_anonIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_size = widget_1_anonIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_sink = widget_1_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_denied = widget_1_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_data = widget_1_anonIn_d_bits_data; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_corrupt = widget_1_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire buffer_nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire masterNodeOut_a_ready = buffer_auto_in_a_ready; // @[Buffer.scala:40:9]
wire masterNodeOut_a_valid; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_a_valid = buffer_auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] masterNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] buffer_nodeIn_a_bits_opcode = buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] masterNodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] buffer_nodeIn_a_bits_param = buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] masterNodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] buffer_nodeIn_a_bits_size = buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [3:0] masterNodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [3:0] buffer_nodeIn_a_bits_source = buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] masterNodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [31:0] buffer_nodeIn_a_bits_address = buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [15:0] masterNodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [15:0] buffer_nodeIn_a_bits_mask = buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [127:0] masterNodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire [127:0] buffer_nodeIn_a_bits_data = buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire masterNodeOut_b_ready; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_b_ready = buffer_auto_in_b_ready; // @[Buffer.scala:40:9]
wire buffer_nodeIn_b_valid; // @[MixedNode.scala:551:17]
wire [2:0] buffer_nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17]
wire masterNodeOut_b_valid = buffer_auto_in_b_valid; // @[Buffer.scala:40:9]
wire [1:0] buffer_nodeIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] masterNodeOut_b_bits_opcode = buffer_auto_in_b_bits_opcode; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeIn_b_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] masterNodeOut_b_bits_param = buffer_auto_in_b_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeIn_b_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] masterNodeOut_b_bits_size = buffer_auto_in_b_bits_size; // @[Buffer.scala:40:9]
wire [31:0] buffer_nodeIn_b_bits_address; // @[MixedNode.scala:551:17]
wire [3:0] masterNodeOut_b_bits_source = buffer_auto_in_b_bits_source; // @[Buffer.scala:40:9]
wire [15:0] buffer_nodeIn_b_bits_mask; // @[MixedNode.scala:551:17]
wire [31:0] masterNodeOut_b_bits_address = buffer_auto_in_b_bits_address; // @[Buffer.scala:40:9]
wire [127:0] buffer_nodeIn_b_bits_data; // @[MixedNode.scala:551:17]
wire [15:0] masterNodeOut_b_bits_mask = buffer_auto_in_b_bits_mask; // @[Buffer.scala:40:9]
wire buffer_nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
wire [127:0] masterNodeOut_b_bits_data = buffer_auto_in_b_bits_data; // @[Buffer.scala:40:9]
wire buffer_nodeIn_c_ready; // @[MixedNode.scala:551:17]
wire masterNodeOut_b_bits_corrupt = buffer_auto_in_b_bits_corrupt; // @[Buffer.scala:40:9]
wire masterNodeOut_c_ready = buffer_auto_in_c_ready; // @[Buffer.scala:40:9]
wire masterNodeOut_c_valid; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_c_valid = buffer_auto_in_c_valid; // @[Buffer.scala:40:9]
wire [2:0] masterNodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] buffer_nodeIn_c_bits_opcode = buffer_auto_in_c_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] masterNodeOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] buffer_nodeIn_c_bits_param = buffer_auto_in_c_bits_param; // @[Buffer.scala:40:9]
wire [3:0] masterNodeOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] buffer_nodeIn_c_bits_size = buffer_auto_in_c_bits_size; // @[Buffer.scala:40:9]
wire [3:0] masterNodeOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [3:0] buffer_nodeIn_c_bits_source = buffer_auto_in_c_bits_source; // @[Buffer.scala:40:9]
wire [31:0] masterNodeOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [31:0] buffer_nodeIn_c_bits_address = buffer_auto_in_c_bits_address; // @[Buffer.scala:40:9]
wire [127:0] masterNodeOut_c_bits_data; // @[MixedNode.scala:542:17]
wire [127:0] buffer_nodeIn_c_bits_data = buffer_auto_in_c_bits_data; // @[Buffer.scala:40:9]
wire masterNodeOut_d_ready; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_d_ready = buffer_auto_in_d_ready; // @[Buffer.scala:40:9]
wire buffer_nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] buffer_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire masterNodeOut_d_valid = buffer_auto_in_d_valid; // @[Buffer.scala:40:9]
wire [1:0] buffer_nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] masterNodeOut_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] masterNodeOut_d_bits_param = buffer_auto_in_d_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] masterNodeOut_d_bits_size = buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire [3:0] masterNodeOut_d_bits_source = buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9]
wire buffer_nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [3:0] masterNodeOut_d_bits_sink = buffer_auto_in_d_bits_sink; // @[Buffer.scala:40:9]
wire [127:0] buffer_nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire masterNodeOut_d_bits_denied = buffer_auto_in_d_bits_denied; // @[Buffer.scala:40:9]
wire buffer_nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire [127:0] masterNodeOut_d_bits_data = buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9]
wire buffer_nodeIn_e_ready; // @[MixedNode.scala:551:17]
wire masterNodeOut_d_bits_corrupt = buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9]
wire masterNodeOut_e_ready = buffer_auto_in_e_ready; // @[Buffer.scala:40:9]
wire masterNodeOut_e_valid; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_e_valid = buffer_auto_in_e_valid; // @[Buffer.scala:40:9]
wire [3:0] masterNodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire [3:0] buffer_nodeIn_e_bits_sink = buffer_auto_in_e_bits_sink; // @[Buffer.scala:40:9]
wire buffer_nodeOut_a_ready = buffer_auto_out_a_ready; // @[Buffer.scala:40:9]
wire buffer_nodeOut_a_valid; // @[MixedNode.scala:542:17]
assign auto_buffer_out_a_valid_0 = buffer_auto_out_a_valid; // @[Buffer.scala:40:9]
wire [2:0] buffer_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign auto_buffer_out_a_bits_opcode_0 = buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] buffer_nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
assign auto_buffer_out_a_bits_param_0 = buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
assign auto_buffer_out_a_bits_size_0 = buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
assign auto_buffer_out_a_bits_source_0 = buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] buffer_nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
assign auto_buffer_out_a_bits_address_0 = buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9]
wire [15:0] buffer_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign auto_buffer_out_a_bits_mask_0 = buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9]
wire [127:0] buffer_nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
assign auto_buffer_out_a_bits_data_0 = buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9]
wire buffer_nodeOut_b_ready; // @[MixedNode.scala:542:17]
assign auto_buffer_out_b_ready_0 = buffer_auto_out_b_ready; // @[Buffer.scala:40:9]
wire buffer_nodeOut_b_valid = buffer_auto_out_b_valid; // @[Buffer.scala:40:9]
wire [2:0] buffer_nodeOut_b_bits_opcode = buffer_auto_out_b_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] buffer_nodeOut_b_bits_param = buffer_auto_out_b_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeOut_b_bits_size = buffer_auto_out_b_bits_size; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeOut_b_bits_source = buffer_auto_out_b_bits_source; // @[Buffer.scala:40:9]
wire [31:0] buffer_nodeOut_b_bits_address = buffer_auto_out_b_bits_address; // @[Buffer.scala:40:9]
wire [15:0] buffer_nodeOut_b_bits_mask = buffer_auto_out_b_bits_mask; // @[Buffer.scala:40:9]
wire [127:0] buffer_nodeOut_b_bits_data = buffer_auto_out_b_bits_data; // @[Buffer.scala:40:9]
wire buffer_nodeOut_b_bits_corrupt = buffer_auto_out_b_bits_corrupt; // @[Buffer.scala:40:9]
wire buffer_nodeOut_c_ready = buffer_auto_out_c_ready; // @[Buffer.scala:40:9]
wire buffer_nodeOut_c_valid; // @[MixedNode.scala:542:17]
assign auto_buffer_out_c_valid_0 = buffer_auto_out_c_valid; // @[Buffer.scala:40:9]
wire [2:0] buffer_nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
assign auto_buffer_out_c_bits_opcode_0 = buffer_auto_out_c_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] buffer_nodeOut_c_bits_param; // @[MixedNode.scala:542:17]
assign auto_buffer_out_c_bits_param_0 = buffer_auto_out_c_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeOut_c_bits_size; // @[MixedNode.scala:542:17]
assign auto_buffer_out_c_bits_size_0 = buffer_auto_out_c_bits_size; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeOut_c_bits_source; // @[MixedNode.scala:542:17]
assign auto_buffer_out_c_bits_source_0 = buffer_auto_out_c_bits_source; // @[Buffer.scala:40:9]
wire [31:0] buffer_nodeOut_c_bits_address; // @[MixedNode.scala:542:17]
assign auto_buffer_out_c_bits_address_0 = buffer_auto_out_c_bits_address; // @[Buffer.scala:40:9]
wire [127:0] buffer_nodeOut_c_bits_data; // @[MixedNode.scala:542:17]
assign auto_buffer_out_c_bits_data_0 = buffer_auto_out_c_bits_data; // @[Buffer.scala:40:9]
wire buffer_nodeOut_d_ready; // @[MixedNode.scala:542:17]
assign auto_buffer_out_d_ready_0 = buffer_auto_out_d_ready; // @[Buffer.scala:40:9]
wire buffer_nodeOut_d_valid = buffer_auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] buffer_nodeOut_d_bits_opcode = buffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] buffer_nodeOut_d_bits_param = buffer_auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeOut_d_bits_size = buffer_auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeOut_d_bits_source = buffer_auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeOut_d_bits_sink = buffer_auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire buffer_nodeOut_d_bits_denied = buffer_auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire [127:0] buffer_nodeOut_d_bits_data = buffer_auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire buffer_nodeOut_d_bits_corrupt = buffer_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire buffer_nodeOut_e_ready = buffer_auto_out_e_ready; // @[Buffer.scala:40:9]
wire buffer_nodeOut_e_valid; // @[MixedNode.scala:542:17]
assign auto_buffer_out_e_valid_0 = buffer_auto_out_e_valid; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
assign auto_buffer_out_e_bits_sink_0 = buffer_auto_out_e_bits_sink; // @[Buffer.scala:40:9]
assign buffer_nodeIn_a_ready = buffer_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_out_a_valid = buffer_nodeOut_a_valid; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_opcode = buffer_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_param = buffer_nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_size = buffer_nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_source = buffer_nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_address = buffer_nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_mask = buffer_nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_data = buffer_nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign buffer_auto_out_b_ready = buffer_nodeOut_b_ready; // @[Buffer.scala:40:9]
assign buffer_nodeIn_b_valid = buffer_nodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_b_bits_opcode = buffer_nodeOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_b_bits_param = buffer_nodeOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_b_bits_size = buffer_nodeOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_b_bits_source = buffer_nodeOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_b_bits_address = buffer_nodeOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_b_bits_mask = buffer_nodeOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_b_bits_data = buffer_nodeOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_b_bits_corrupt = buffer_nodeOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_c_ready = buffer_nodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_out_c_valid = buffer_nodeOut_c_valid; // @[Buffer.scala:40:9]
assign buffer_auto_out_c_bits_opcode = buffer_nodeOut_c_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_out_c_bits_param = buffer_nodeOut_c_bits_param; // @[Buffer.scala:40:9]
assign buffer_auto_out_c_bits_size = buffer_nodeOut_c_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_out_c_bits_source = buffer_nodeOut_c_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_out_c_bits_address = buffer_nodeOut_c_bits_address; // @[Buffer.scala:40:9]
assign buffer_auto_out_c_bits_data = buffer_nodeOut_c_bits_data; // @[Buffer.scala:40:9]
assign buffer_auto_out_d_ready = buffer_nodeOut_d_ready; // @[Buffer.scala:40:9]
assign buffer_nodeIn_d_valid = buffer_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_opcode = buffer_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_param = buffer_nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_size = buffer_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_source = buffer_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_sink = buffer_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_denied = buffer_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_data = buffer_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_corrupt = buffer_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_e_ready = buffer_nodeOut_e_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_out_e_valid = buffer_nodeOut_e_valid; // @[Buffer.scala:40:9]
assign buffer_auto_out_e_bits_sink = buffer_nodeOut_e_bits_sink; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_ready = buffer_nodeIn_a_ready; // @[Buffer.scala:40:9]
assign buffer_nodeOut_a_valid = buffer_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_opcode = buffer_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_param = buffer_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_size = buffer_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_source = buffer_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_address = buffer_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_mask = buffer_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_data = buffer_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_b_ready = buffer_nodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_in_b_valid = buffer_nodeIn_b_valid; // @[Buffer.scala:40:9]
assign buffer_auto_in_b_bits_opcode = buffer_nodeIn_b_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_in_b_bits_param = buffer_nodeIn_b_bits_param; // @[Buffer.scala:40:9]
assign buffer_auto_in_b_bits_size = buffer_nodeIn_b_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_in_b_bits_source = buffer_nodeIn_b_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_in_b_bits_address = buffer_nodeIn_b_bits_address; // @[Buffer.scala:40:9]
assign buffer_auto_in_b_bits_mask = buffer_nodeIn_b_bits_mask; // @[Buffer.scala:40:9]
assign buffer_auto_in_b_bits_data = buffer_nodeIn_b_bits_data; // @[Buffer.scala:40:9]
assign buffer_auto_in_b_bits_corrupt = buffer_nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9]
assign buffer_auto_in_c_ready = buffer_nodeIn_c_ready; // @[Buffer.scala:40:9]
assign buffer_nodeOut_c_valid = buffer_nodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_c_bits_opcode = buffer_nodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_c_bits_param = buffer_nodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_c_bits_size = buffer_nodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_c_bits_source = buffer_nodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_c_bits_address = buffer_nodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_c_bits_data = buffer_nodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_d_ready = buffer_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_in_d_valid = buffer_nodeIn_d_valid; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_opcode = buffer_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_param = buffer_nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_size = buffer_nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_source = buffer_nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_sink = buffer_nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_denied = buffer_nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_data = buffer_nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_corrupt = buffer_nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign buffer_auto_in_e_ready = buffer_nodeIn_e_ready; // @[Buffer.scala:40:9]
assign buffer_nodeOut_e_valid = buffer_nodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_e_bits_sink = buffer_nodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire masterNodeIn_a_ready; // @[MixedNode.scala:551:17]
wire tlOtherMastersNodeIn_a_ready = tlOtherMastersNodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire tlOtherMastersNodeIn_a_valid; // @[MixedNode.scala:551:17]
wire [2:0] tlOtherMastersNodeIn_a_bits_opcode; // @[MixedNode.scala:551:17]
wire masterNodeIn_a_valid = tlOtherMastersNodeOut_a_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] tlOtherMastersNodeIn_a_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] masterNodeIn_a_bits_opcode = tlOtherMastersNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] tlOtherMastersNodeIn_a_bits_size; // @[MixedNode.scala:551:17]
wire [2:0] masterNodeIn_a_bits_param = tlOtherMastersNodeOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] tlOtherMastersNodeIn_a_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] masterNodeIn_a_bits_size = tlOtherMastersNodeOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] tlOtherMastersNodeIn_a_bits_address; // @[MixedNode.scala:551:17]
wire [3:0] masterNodeIn_a_bits_source = tlOtherMastersNodeOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [15:0] tlOtherMastersNodeIn_a_bits_mask; // @[MixedNode.scala:551:17]
wire [31:0] masterNodeIn_a_bits_address = tlOtherMastersNodeOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [127:0] tlOtherMastersNodeIn_a_bits_data; // @[MixedNode.scala:551:17]
wire [15:0] masterNodeIn_a_bits_mask = tlOtherMastersNodeOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [127:0] masterNodeIn_a_bits_data = tlOtherMastersNodeOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire tlOtherMastersNodeIn_b_ready; // @[MixedNode.scala:551:17]
wire masterNodeIn_b_ready = tlOtherMastersNodeOut_b_ready; // @[MixedNode.scala:542:17, :551:17]
wire masterNodeIn_b_valid; // @[MixedNode.scala:551:17]
wire tlOtherMastersNodeIn_b_valid = tlOtherMastersNodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] masterNodeIn_b_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] tlOtherMastersNodeIn_b_bits_opcode = tlOtherMastersNodeOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] masterNodeIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [1:0] tlOtherMastersNodeIn_b_bits_param = tlOtherMastersNodeOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] masterNodeIn_b_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] tlOtherMastersNodeIn_b_bits_size = tlOtherMastersNodeOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] masterNodeIn_b_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] tlOtherMastersNodeIn_b_bits_source = tlOtherMastersNodeOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] masterNodeIn_b_bits_address; // @[MixedNode.scala:551:17]
wire [31:0] tlOtherMastersNodeIn_b_bits_address = tlOtherMastersNodeOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [15:0] masterNodeIn_b_bits_mask; // @[MixedNode.scala:551:17]
wire [15:0] tlOtherMastersNodeIn_b_bits_mask = tlOtherMastersNodeOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [127:0] masterNodeIn_b_bits_data; // @[MixedNode.scala:551:17]
wire [127:0] tlOtherMastersNodeIn_b_bits_data = tlOtherMastersNodeOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire masterNodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
wire tlOtherMastersNodeIn_b_bits_corrupt = tlOtherMastersNodeOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire masterNodeIn_c_ready; // @[MixedNode.scala:551:17]
wire tlOtherMastersNodeIn_c_ready = tlOtherMastersNodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
wire tlOtherMastersNodeIn_c_valid; // @[MixedNode.scala:551:17]
wire [2:0] tlOtherMastersNodeIn_c_bits_opcode; // @[MixedNode.scala:551:17]
wire masterNodeIn_c_valid = tlOtherMastersNodeOut_c_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] tlOtherMastersNodeIn_c_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] masterNodeIn_c_bits_opcode = tlOtherMastersNodeOut_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] tlOtherMastersNodeIn_c_bits_size; // @[MixedNode.scala:551:17]
wire [2:0] masterNodeIn_c_bits_param = tlOtherMastersNodeOut_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] tlOtherMastersNodeIn_c_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] masterNodeIn_c_bits_size = tlOtherMastersNodeOut_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] tlOtherMastersNodeIn_c_bits_address; // @[MixedNode.scala:551:17]
wire [3:0] masterNodeIn_c_bits_source = tlOtherMastersNodeOut_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [127:0] tlOtherMastersNodeIn_c_bits_data; // @[MixedNode.scala:551:17]
wire [31:0] masterNodeIn_c_bits_address = tlOtherMastersNodeOut_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [127:0] masterNodeIn_c_bits_data = tlOtherMastersNodeOut_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire tlOtherMastersNodeIn_d_ready; // @[MixedNode.scala:551:17]
wire masterNodeIn_d_ready = tlOtherMastersNodeOut_d_ready; // @[MixedNode.scala:542:17, :551:17]
wire masterNodeIn_d_valid; // @[MixedNode.scala:551:17]
wire tlOtherMastersNodeIn_d_valid = tlOtherMastersNodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] masterNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] tlOtherMastersNodeIn_d_bits_opcode = tlOtherMastersNodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] masterNodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [1:0] tlOtherMastersNodeIn_d_bits_param = tlOtherMastersNodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] masterNodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] tlOtherMastersNodeIn_d_bits_size = tlOtherMastersNodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] masterNodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] tlOtherMastersNodeIn_d_bits_source = tlOtherMastersNodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] masterNodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire [3:0] tlOtherMastersNodeIn_d_bits_sink = tlOtherMastersNodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire masterNodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire tlOtherMastersNodeIn_d_bits_denied = tlOtherMastersNodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [127:0] masterNodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire [127:0] tlOtherMastersNodeIn_d_bits_data = tlOtherMastersNodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire masterNodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire tlOtherMastersNodeIn_d_bits_corrupt = tlOtherMastersNodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire masterNodeIn_e_ready; // @[MixedNode.scala:551:17]
wire tlOtherMastersNodeIn_e_ready = tlOtherMastersNodeOut_e_ready; // @[MixedNode.scala:542:17, :551:17]
wire tlOtherMastersNodeIn_e_valid; // @[MixedNode.scala:551:17]
wire [3:0] tlOtherMastersNodeIn_e_bits_sink; // @[MixedNode.scala:551:17]
wire masterNodeIn_e_valid = tlOtherMastersNodeOut_e_valid; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] masterNodeIn_e_bits_sink = tlOtherMastersNodeOut_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_a_valid = tlOtherMastersNodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_a_bits_opcode = tlOtherMastersNodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_a_bits_param = tlOtherMastersNodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_a_bits_size = tlOtherMastersNodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_a_bits_source = tlOtherMastersNodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_a_bits_address = tlOtherMastersNodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_a_bits_mask = tlOtherMastersNodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_a_bits_data = tlOtherMastersNodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_b_ready = tlOtherMastersNodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_c_valid = tlOtherMastersNodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_c_bits_opcode = tlOtherMastersNodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_c_bits_param = tlOtherMastersNodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_c_bits_size = tlOtherMastersNodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_c_bits_source = tlOtherMastersNodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_c_bits_address = tlOtherMastersNodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_c_bits_data = tlOtherMastersNodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_d_ready = tlOtherMastersNodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_e_valid = tlOtherMastersNodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_e_bits_sink = tlOtherMastersNodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign broadcast_auto_in = hartidOut; // @[MixedNode.scala:542:17]
assign hartidOut = hartidIn; // @[MixedNode.scala:542:17, :551:17]
assign auto_trace_source_out_time_0 = traceSourceNodeOut_time; // @[MixedNode.scala:542:17]
assign auto_trace_source_out_custom_rob_empty_0 = traceSourceNodeOut_custom_rob_empty; // @[MixedNode.scala:542:17]
wire int_localOut_0; // @[MixedNode.scala:542:17]
wire x1_int_localOut_0; // @[MixedNode.scala:542:17]
wire x1_int_localOut_1; // @[MixedNode.scala:542:17]
wire x1_int_localOut_1_0; // @[MixedNode.scala:542:17]
wire x1_int_localOut_2_0; // @[MixedNode.scala:542:17]
assign int_localOut_0 = int_localIn_0; // @[MixedNode.scala:542:17, :551:17]
assign x1_int_localOut_0 = x1_int_localIn_0; // @[MixedNode.scala:542:17, :551:17]
assign x1_int_localOut_1 = x1_int_localIn_1; // @[MixedNode.scala:542:17, :551:17]
assign x1_int_localOut_1_0 = x1_int_localIn_1_0; // @[MixedNode.scala:542:17, :551:17]
assign x1_int_localOut_2_0 = x1_int_localIn_2_0; // @[MixedNode.scala:542:17, :551:17]
wire intSinkNodeIn_0; // @[MixedNode.scala:551:17]
wire intSinkNodeIn_1; // @[MixedNode.scala:551:17]
wire intSinkNodeIn_2; // @[MixedNode.scala:551:17]
wire intSinkNodeIn_3; // @[MixedNode.scala:551:17]
wire intSinkNodeIn_4; // @[MixedNode.scala:551:17]
assign masterNodeIn_a_ready = masterNodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_in_a_valid = masterNodeOut_a_valid; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_opcode = masterNodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_param = masterNodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_size = masterNodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_source = masterNodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_address = masterNodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_mask = masterNodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_data = masterNodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign buffer_auto_in_b_ready = masterNodeOut_b_ready; // @[Buffer.scala:40:9]
assign masterNodeIn_b_valid = masterNodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_b_bits_opcode = masterNodeOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_b_bits_param = masterNodeOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_b_bits_size = masterNodeOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_b_bits_source = masterNodeOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_b_bits_address = masterNodeOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_b_bits_mask = masterNodeOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_b_bits_data = masterNodeOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_b_bits_corrupt = masterNodeOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_c_ready = masterNodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_in_c_valid = masterNodeOut_c_valid; // @[Buffer.scala:40:9]
assign buffer_auto_in_c_bits_opcode = masterNodeOut_c_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_in_c_bits_param = masterNodeOut_c_bits_param; // @[Buffer.scala:40:9]
assign buffer_auto_in_c_bits_size = masterNodeOut_c_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_in_c_bits_source = masterNodeOut_c_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_in_c_bits_address = masterNodeOut_c_bits_address; // @[Buffer.scala:40:9]
assign buffer_auto_in_c_bits_data = masterNodeOut_c_bits_data; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_ready = masterNodeOut_d_ready; // @[Buffer.scala:40:9]
assign masterNodeIn_d_valid = masterNodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_d_bits_opcode = masterNodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_d_bits_param = masterNodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_d_bits_size = masterNodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_d_bits_source = masterNodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_d_bits_sink = masterNodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_d_bits_denied = masterNodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_d_bits_data = masterNodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_d_bits_corrupt = masterNodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_e_ready = masterNodeOut_e_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_in_e_valid = masterNodeOut_e_valid; // @[Buffer.scala:40:9]
assign buffer_auto_in_e_bits_sink = masterNodeOut_e_bits_sink; // @[Buffer.scala:40:9]
assign tlOtherMastersNodeOut_a_ready = masterNodeIn_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_a_valid = masterNodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_a_bits_opcode = masterNodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_a_bits_param = masterNodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_a_bits_size = masterNodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_a_bits_source = masterNodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_a_bits_address = masterNodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_a_bits_mask = masterNodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_a_bits_data = masterNodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_b_ready = masterNodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_b_valid = masterNodeIn_b_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_b_bits_opcode = masterNodeIn_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_b_bits_param = masterNodeIn_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_b_bits_size = masterNodeIn_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_b_bits_source = masterNodeIn_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_b_bits_address = masterNodeIn_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_b_bits_mask = masterNodeIn_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_b_bits_data = masterNodeIn_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_b_bits_corrupt = masterNodeIn_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_c_ready = masterNodeIn_c_ready; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_c_valid = masterNodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_c_bits_opcode = masterNodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_c_bits_param = masterNodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_c_bits_size = masterNodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_c_bits_source = masterNodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_c_bits_address = masterNodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_c_bits_data = masterNodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_d_ready = masterNodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_d_valid = masterNodeIn_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_d_bits_opcode = masterNodeIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_d_bits_param = masterNodeIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_d_bits_size = masterNodeIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_d_bits_source = masterNodeIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_d_bits_sink = masterNodeIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_d_bits_denied = masterNodeIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_d_bits_data = masterNodeIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_d_bits_corrupt = masterNodeIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_e_ready = masterNodeIn_e_ready; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_e_valid = masterNodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_e_bits_sink = masterNodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_a_ready = dCacheTapOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_b_valid = dCacheTapOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_b_bits_opcode = dCacheTapOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_b_bits_param = dCacheTapOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_b_bits_size = dCacheTapOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_b_bits_source = dCacheTapOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_b_bits_address = dCacheTapOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_b_bits_mask = dCacheTapOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_b_bits_data = dCacheTapOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_b_bits_corrupt = dCacheTapOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_c_ready = dCacheTapOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_d_valid = dCacheTapOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_d_bits_opcode = dCacheTapOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_d_bits_param = dCacheTapOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_d_bits_size = dCacheTapOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_d_bits_source = dCacheTapOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_d_bits_sink = dCacheTapOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_d_bits_denied = dCacheTapOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_d_bits_data = dCacheTapOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_d_bits_corrupt = dCacheTapOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_e_ready = dCacheTapOut_e_ready; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] dCacheTapOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] dCacheTapOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] dCacheTapOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [15:0] dCacheTapOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [127:0] dCacheTapOut_a_bits_data; // @[MixedNode.scala:542:17]
wire dCacheTapOut_a_valid; // @[MixedNode.scala:542:17]
wire dCacheTapOut_b_ready; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] dCacheTapOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] dCacheTapOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [127:0] dCacheTapOut_c_bits_data; // @[MixedNode.scala:542:17]
wire dCacheTapOut_c_valid; // @[MixedNode.scala:542:17]
wire dCacheTapOut_d_ready; // @[MixedNode.scala:542:17]
wire [3:0] dCacheTapOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire dCacheTapOut_e_valid; // @[MixedNode.scala:542:17]
assign widget_auto_anon_out_a_ready = dCacheTapIn_a_ready; // @[WidthWidget.scala:27:9]
assign dCacheTapOut_a_valid = dCacheTapIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_a_bits_opcode = dCacheTapIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_a_bits_param = dCacheTapIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_a_bits_size = dCacheTapIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_a_bits_source = dCacheTapIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_a_bits_address = dCacheTapIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_a_bits_mask = dCacheTapIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_a_bits_data = dCacheTapIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_b_ready = dCacheTapIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_out_b_valid = dCacheTapIn_b_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_b_bits_opcode = dCacheTapIn_b_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_b_bits_param = dCacheTapIn_b_bits_param; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_b_bits_size = dCacheTapIn_b_bits_size; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_b_bits_source = dCacheTapIn_b_bits_source; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_b_bits_address = dCacheTapIn_b_bits_address; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_b_bits_mask = dCacheTapIn_b_bits_mask; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_b_bits_data = dCacheTapIn_b_bits_data; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_b_bits_corrupt = dCacheTapIn_b_bits_corrupt; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_c_ready = dCacheTapIn_c_ready; // @[WidthWidget.scala:27:9]
assign dCacheTapOut_c_valid = dCacheTapIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_c_bits_opcode = dCacheTapIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_c_bits_param = dCacheTapIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_c_bits_size = dCacheTapIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_c_bits_source = dCacheTapIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_c_bits_address = dCacheTapIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_c_bits_data = dCacheTapIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_d_ready = dCacheTapIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_out_d_valid = dCacheTapIn_d_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_d_bits_opcode = dCacheTapIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_d_bits_param = dCacheTapIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_d_bits_size = dCacheTapIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_d_bits_source = dCacheTapIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_d_bits_sink = dCacheTapIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_d_bits_denied = dCacheTapIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_d_bits_data = dCacheTapIn_d_bits_data; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_d_bits_corrupt = dCacheTapIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_e_ready = dCacheTapIn_e_ready; // @[WidthWidget.scala:27:9]
assign dCacheTapOut_e_valid = dCacheTapIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_e_bits_sink = dCacheTapIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
TLXbar_MasterXbar_BoomTile_i2_o1_a32d128s4k4z4c_1 tlMasterXbar ( // @[HierarchicalElement.scala:55:42]
.clock (clock),
.reset (reset),
.auto_anon_in_1_a_ready (widget_1_auto_anon_out_a_ready),
.auto_anon_in_1_a_valid (widget_1_auto_anon_out_a_valid), // @[WidthWidget.scala:27:9]
.auto_anon_in_1_a_bits_address (widget_1_auto_anon_out_a_bits_address), // @[WidthWidget.scala:27:9]
.auto_anon_in_1_d_valid (widget_1_auto_anon_out_d_valid),
.auto_anon_in_1_d_bits_opcode (widget_1_auto_anon_out_d_bits_opcode),
.auto_anon_in_1_d_bits_param (widget_1_auto_anon_out_d_bits_param),
.auto_anon_in_1_d_bits_size (widget_1_auto_anon_out_d_bits_size),
.auto_anon_in_1_d_bits_sink (widget_1_auto_anon_out_d_bits_sink),
.auto_anon_in_1_d_bits_denied (widget_1_auto_anon_out_d_bits_denied),
.auto_anon_in_1_d_bits_data (widget_1_auto_anon_out_d_bits_data),
.auto_anon_in_1_d_bits_corrupt (widget_1_auto_anon_out_d_bits_corrupt),
.auto_anon_in_0_a_ready (dCacheTapOut_a_ready),
.auto_anon_in_0_a_valid (dCacheTapOut_a_valid), // @[MixedNode.scala:542:17]
.auto_anon_in_0_a_bits_opcode (dCacheTapOut_a_bits_opcode), // @[MixedNode.scala:542:17]
.auto_anon_in_0_a_bits_param (dCacheTapOut_a_bits_param), // @[MixedNode.scala:542:17]
.auto_anon_in_0_a_bits_size (dCacheTapOut_a_bits_size), // @[MixedNode.scala:542:17]
.auto_anon_in_0_a_bits_source (dCacheTapOut_a_bits_source), // @[MixedNode.scala:542:17]
.auto_anon_in_0_a_bits_address (dCacheTapOut_a_bits_address), // @[MixedNode.scala:542:17]
.auto_anon_in_0_a_bits_mask (dCacheTapOut_a_bits_mask), // @[MixedNode.scala:542:17]
.auto_anon_in_0_a_bits_data (dCacheTapOut_a_bits_data), // @[MixedNode.scala:542:17]
.auto_anon_in_0_b_ready (dCacheTapOut_b_ready), // @[MixedNode.scala:542:17]
.auto_anon_in_0_b_valid (dCacheTapOut_b_valid),
.auto_anon_in_0_b_bits_opcode (dCacheTapOut_b_bits_opcode),
.auto_anon_in_0_b_bits_param (dCacheTapOut_b_bits_param),
.auto_anon_in_0_b_bits_size (dCacheTapOut_b_bits_size),
.auto_anon_in_0_b_bits_source (dCacheTapOut_b_bits_source),
.auto_anon_in_0_b_bits_address (dCacheTapOut_b_bits_address),
.auto_anon_in_0_b_bits_mask (dCacheTapOut_b_bits_mask),
.auto_anon_in_0_b_bits_data (dCacheTapOut_b_bits_data),
.auto_anon_in_0_b_bits_corrupt (dCacheTapOut_b_bits_corrupt),
.auto_anon_in_0_c_ready (dCacheTapOut_c_ready),
.auto_anon_in_0_c_valid (dCacheTapOut_c_valid), // @[MixedNode.scala:542:17]
.auto_anon_in_0_c_bits_opcode (dCacheTapOut_c_bits_opcode), // @[MixedNode.scala:542:17]
.auto_anon_in_0_c_bits_param (dCacheTapOut_c_bits_param), // @[MixedNode.scala:542:17]
.auto_anon_in_0_c_bits_size (dCacheTapOut_c_bits_size), // @[MixedNode.scala:542:17]
.auto_anon_in_0_c_bits_source (dCacheTapOut_c_bits_source), // @[MixedNode.scala:542:17]
.auto_anon_in_0_c_bits_address (dCacheTapOut_c_bits_address), // @[MixedNode.scala:542:17]
.auto_anon_in_0_c_bits_data (dCacheTapOut_c_bits_data), // @[MixedNode.scala:542:17]
.auto_anon_in_0_d_ready (dCacheTapOut_d_ready), // @[MixedNode.scala:542:17]
.auto_anon_in_0_d_valid (dCacheTapOut_d_valid),
.auto_anon_in_0_d_bits_opcode (dCacheTapOut_d_bits_opcode),
.auto_anon_in_0_d_bits_param (dCacheTapOut_d_bits_param),
.auto_anon_in_0_d_bits_size (dCacheTapOut_d_bits_size),
.auto_anon_in_0_d_bits_source (dCacheTapOut_d_bits_source),
.auto_anon_in_0_d_bits_sink (dCacheTapOut_d_bits_sink),
.auto_anon_in_0_d_bits_denied (dCacheTapOut_d_bits_denied),
.auto_anon_in_0_d_bits_data (dCacheTapOut_d_bits_data),
.auto_anon_in_0_d_bits_corrupt (dCacheTapOut_d_bits_corrupt),
.auto_anon_in_0_e_ready (dCacheTapOut_e_ready),
.auto_anon_in_0_e_valid (dCacheTapOut_e_valid), // @[MixedNode.scala:542:17]
.auto_anon_in_0_e_bits_sink (dCacheTapOut_e_bits_sink), // @[MixedNode.scala:542:17]
.auto_anon_out_a_ready (tlOtherMastersNodeIn_a_ready), // @[MixedNode.scala:551:17]
.auto_anon_out_a_valid (tlOtherMastersNodeIn_a_valid),
.auto_anon_out_a_bits_opcode (tlOtherMastersNodeIn_a_bits_opcode),
.auto_anon_out_a_bits_param (tlOtherMastersNodeIn_a_bits_param),
.auto_anon_out_a_bits_size (tlOtherMastersNodeIn_a_bits_size),
.auto_anon_out_a_bits_source (tlOtherMastersNodeIn_a_bits_source),
.auto_anon_out_a_bits_address (tlOtherMastersNodeIn_a_bits_address),
.auto_anon_out_a_bits_mask (tlOtherMastersNodeIn_a_bits_mask),
.auto_anon_out_a_bits_data (tlOtherMastersNodeIn_a_bits_data),
.auto_anon_out_b_ready (tlOtherMastersNodeIn_b_ready),
.auto_anon_out_b_valid (tlOtherMastersNodeIn_b_valid), // @[MixedNode.scala:551:17]
.auto_anon_out_b_bits_opcode (tlOtherMastersNodeIn_b_bits_opcode), // @[MixedNode.scala:551:17]
.auto_anon_out_b_bits_param (tlOtherMastersNodeIn_b_bits_param), // @[MixedNode.scala:551:17]
.auto_anon_out_b_bits_size (tlOtherMastersNodeIn_b_bits_size), // @[MixedNode.scala:551:17]
.auto_anon_out_b_bits_source (tlOtherMastersNodeIn_b_bits_source), // @[MixedNode.scala:551:17]
.auto_anon_out_b_bits_address (tlOtherMastersNodeIn_b_bits_address), // @[MixedNode.scala:551:17]
.auto_anon_out_b_bits_mask (tlOtherMastersNodeIn_b_bits_mask), // @[MixedNode.scala:551:17]
.auto_anon_out_b_bits_data (tlOtherMastersNodeIn_b_bits_data), // @[MixedNode.scala:551:17]
.auto_anon_out_b_bits_corrupt (tlOtherMastersNodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17]
.auto_anon_out_c_ready (tlOtherMastersNodeIn_c_ready), // @[MixedNode.scala:551:17]
.auto_anon_out_c_valid (tlOtherMastersNodeIn_c_valid),
.auto_anon_out_c_bits_opcode (tlOtherMastersNodeIn_c_bits_opcode),
.auto_anon_out_c_bits_param (tlOtherMastersNodeIn_c_bits_param),
.auto_anon_out_c_bits_size (tlOtherMastersNodeIn_c_bits_size),
.auto_anon_out_c_bits_source (tlOtherMastersNodeIn_c_bits_source),
.auto_anon_out_c_bits_address (tlOtherMastersNodeIn_c_bits_address),
.auto_anon_out_c_bits_data (tlOtherMastersNodeIn_c_bits_data),
.auto_anon_out_d_ready (tlOtherMastersNodeIn_d_ready),
.auto_anon_out_d_valid (tlOtherMastersNodeIn_d_valid), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_opcode (tlOtherMastersNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_param (tlOtherMastersNodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_size (tlOtherMastersNodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_source (tlOtherMastersNodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_sink (tlOtherMastersNodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_denied (tlOtherMastersNodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_data (tlOtherMastersNodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_corrupt (tlOtherMastersNodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17]
.auto_anon_out_e_ready (tlOtherMastersNodeIn_e_ready), // @[MixedNode.scala:551:17]
.auto_anon_out_e_valid (tlOtherMastersNodeIn_e_valid),
.auto_anon_out_e_bits_sink (tlOtherMastersNodeIn_e_bits_sink)
); // @[HierarchicalElement.scala:55:42]
TLXbar_SlaveXbar_BoomTile_i0_o0_a1d8s1k1z1u_1 tlSlaveXbar ( // @[HierarchicalElement.scala:56:41]
.clock (clock),
.reset (reset)
); // @[HierarchicalElement.scala:56:41]
IntXbar_i4_o1_3 intXbar ( // @[HierarchicalElement.scala:57:37]
.auto_anon_in_3_0 (x1_int_localOut_2_0), // @[MixedNode.scala:542:17]
.auto_anon_in_2_0 (x1_int_localOut_1_0), // @[MixedNode.scala:542:17]
.auto_anon_in_1_0 (x1_int_localOut_0), // @[MixedNode.scala:542:17]
.auto_anon_in_1_1 (x1_int_localOut_1), // @[MixedNode.scala:542:17]
.auto_anon_in_0_0 (int_localOut_0), // @[MixedNode.scala:542:17]
.auto_anon_out_0 (intSinkNodeIn_0),
.auto_anon_out_1 (intSinkNodeIn_1),
.auto_anon_out_2 (intSinkNodeIn_2),
.auto_anon_out_3 (intSinkNodeIn_3),
.auto_anon_out_4 (intSinkNodeIn_4)
); // @[HierarchicalElement.scala:57:37]
BoomNonBlockingDCache_1 dcache ( // @[tile.scala:132:54]
.clock (clock),
.reset (reset),
.auto_out_a_ready (widget_auto_anon_in_a_ready), // @[WidthWidget.scala:27:9]
.auto_out_a_valid (widget_auto_anon_in_a_valid),
.auto_out_a_bits_opcode (widget_auto_anon_in_a_bits_opcode),
.auto_out_a_bits_param (widget_auto_anon_in_a_bits_param),
.auto_out_a_bits_size (widget_auto_anon_in_a_bits_size),
.auto_out_a_bits_source (widget_auto_anon_in_a_bits_source),
.auto_out_a_bits_address (widget_auto_anon_in_a_bits_address),
.auto_out_a_bits_mask (widget_auto_anon_in_a_bits_mask),
.auto_out_a_bits_data (widget_auto_anon_in_a_bits_data),
.auto_out_b_ready (widget_auto_anon_in_b_ready),
.auto_out_b_valid (widget_auto_anon_in_b_valid), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_opcode (widget_auto_anon_in_b_bits_opcode), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_param (widget_auto_anon_in_b_bits_param), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_size (widget_auto_anon_in_b_bits_size), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_source (widget_auto_anon_in_b_bits_source), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_address (widget_auto_anon_in_b_bits_address), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_mask (widget_auto_anon_in_b_bits_mask), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_data (widget_auto_anon_in_b_bits_data), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_corrupt (widget_auto_anon_in_b_bits_corrupt), // @[WidthWidget.scala:27:9]
.auto_out_c_ready (widget_auto_anon_in_c_ready), // @[WidthWidget.scala:27:9]
.auto_out_c_valid (widget_auto_anon_in_c_valid),
.auto_out_c_bits_opcode (widget_auto_anon_in_c_bits_opcode),
.auto_out_c_bits_param (widget_auto_anon_in_c_bits_param),
.auto_out_c_bits_size (widget_auto_anon_in_c_bits_size),
.auto_out_c_bits_source (widget_auto_anon_in_c_bits_source),
.auto_out_c_bits_address (widget_auto_anon_in_c_bits_address),
.auto_out_c_bits_data (widget_auto_anon_in_c_bits_data),
.auto_out_d_ready (widget_auto_anon_in_d_ready),
.auto_out_d_valid (widget_auto_anon_in_d_valid), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_opcode (widget_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_param (widget_auto_anon_in_d_bits_param), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_size (widget_auto_anon_in_d_bits_size), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_source (widget_auto_anon_in_d_bits_source), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_sink (widget_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_denied (widget_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_data (widget_auto_anon_in_d_bits_data), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_corrupt (widget_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:27:9]
.auto_out_e_ready (widget_auto_anon_in_e_ready), // @[WidthWidget.scala:27:9]
.auto_out_e_valid (widget_auto_anon_in_e_valid),
.auto_out_e_bits_sink (widget_auto_anon_in_e_bits_sink),
.io_lsu_req_ready (_dcache_io_lsu_req_ready),
.io_lsu_req_valid (_lsu_io_dmem_req_valid), // @[tile.scala:160:20]
.io_lsu_req_bits_0_valid (_lsu_io_dmem_req_bits_0_valid), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_uopc (_lsu_io_dmem_req_bits_0_bits_uop_uopc), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_inst (_lsu_io_dmem_req_bits_0_bits_uop_inst), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_debug_inst (_lsu_io_dmem_req_bits_0_bits_uop_debug_inst), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_is_rvc (_lsu_io_dmem_req_bits_0_bits_uop_is_rvc), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_debug_pc (_lsu_io_dmem_req_bits_0_bits_uop_debug_pc), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_iq_type (_lsu_io_dmem_req_bits_0_bits_uop_iq_type), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_fu_code (_lsu_io_dmem_req_bits_0_bits_uop_fu_code), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ctrl_br_type (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_br_type), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ctrl_op1_sel (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_op1_sel), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ctrl_op2_sel (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_op2_sel), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ctrl_imm_sel (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_imm_sel), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ctrl_op_fcn (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_op_fcn), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ctrl_fcn_dw (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_fcn_dw), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ctrl_csr_cmd (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_csr_cmd), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ctrl_is_load (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_is_load), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ctrl_is_sta (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_is_sta), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ctrl_is_std (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_is_std), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_iw_state (_lsu_io_dmem_req_bits_0_bits_uop_iw_state), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_iw_p1_poisoned (_lsu_io_dmem_req_bits_0_bits_uop_iw_p1_poisoned), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_iw_p2_poisoned (_lsu_io_dmem_req_bits_0_bits_uop_iw_p2_poisoned), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_is_br (_lsu_io_dmem_req_bits_0_bits_uop_is_br), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_is_jalr (_lsu_io_dmem_req_bits_0_bits_uop_is_jalr), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_is_jal (_lsu_io_dmem_req_bits_0_bits_uop_is_jal), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_is_sfb (_lsu_io_dmem_req_bits_0_bits_uop_is_sfb), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_br_mask (_lsu_io_dmem_req_bits_0_bits_uop_br_mask), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_br_tag (_lsu_io_dmem_req_bits_0_bits_uop_br_tag), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ftq_idx (_lsu_io_dmem_req_bits_0_bits_uop_ftq_idx), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_edge_inst (_lsu_io_dmem_req_bits_0_bits_uop_edge_inst), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_pc_lob (_lsu_io_dmem_req_bits_0_bits_uop_pc_lob), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_taken (_lsu_io_dmem_req_bits_0_bits_uop_taken), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_imm_packed (_lsu_io_dmem_req_bits_0_bits_uop_imm_packed), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_csr_addr (_lsu_io_dmem_req_bits_0_bits_uop_csr_addr), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_rob_idx (_lsu_io_dmem_req_bits_0_bits_uop_rob_idx), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ldq_idx (_lsu_io_dmem_req_bits_0_bits_uop_ldq_idx), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_stq_idx (_lsu_io_dmem_req_bits_0_bits_uop_stq_idx), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_rxq_idx (_lsu_io_dmem_req_bits_0_bits_uop_rxq_idx), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_pdst (_lsu_io_dmem_req_bits_0_bits_uop_pdst), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_prs1 (_lsu_io_dmem_req_bits_0_bits_uop_prs1), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_prs2 (_lsu_io_dmem_req_bits_0_bits_uop_prs2), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_prs3 (_lsu_io_dmem_req_bits_0_bits_uop_prs3), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ppred (_lsu_io_dmem_req_bits_0_bits_uop_ppred), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_prs1_busy (_lsu_io_dmem_req_bits_0_bits_uop_prs1_busy), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_prs2_busy (_lsu_io_dmem_req_bits_0_bits_uop_prs2_busy), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_prs3_busy (_lsu_io_dmem_req_bits_0_bits_uop_prs3_busy), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ppred_busy (_lsu_io_dmem_req_bits_0_bits_uop_ppred_busy), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_stale_pdst (_lsu_io_dmem_req_bits_0_bits_uop_stale_pdst), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_exception (_lsu_io_dmem_req_bits_0_bits_uop_exception), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_exc_cause (_lsu_io_dmem_req_bits_0_bits_uop_exc_cause), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_bypassable (_lsu_io_dmem_req_bits_0_bits_uop_bypassable), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_mem_cmd (_lsu_io_dmem_req_bits_0_bits_uop_mem_cmd), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_mem_size (_lsu_io_dmem_req_bits_0_bits_uop_mem_size), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_mem_signed (_lsu_io_dmem_req_bits_0_bits_uop_mem_signed), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_is_fence (_lsu_io_dmem_req_bits_0_bits_uop_is_fence), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_is_fencei (_lsu_io_dmem_req_bits_0_bits_uop_is_fencei), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_is_amo (_lsu_io_dmem_req_bits_0_bits_uop_is_amo), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_uses_ldq (_lsu_io_dmem_req_bits_0_bits_uop_uses_ldq), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_uses_stq (_lsu_io_dmem_req_bits_0_bits_uop_uses_stq), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_is_sys_pc2epc (_lsu_io_dmem_req_bits_0_bits_uop_is_sys_pc2epc), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_is_unique (_lsu_io_dmem_req_bits_0_bits_uop_is_unique), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_flush_on_commit (_lsu_io_dmem_req_bits_0_bits_uop_flush_on_commit), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ldst_is_rs1 (_lsu_io_dmem_req_bits_0_bits_uop_ldst_is_rs1), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ldst (_lsu_io_dmem_req_bits_0_bits_uop_ldst), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_lrs1 (_lsu_io_dmem_req_bits_0_bits_uop_lrs1), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_lrs2 (_lsu_io_dmem_req_bits_0_bits_uop_lrs2), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_lrs3 (_lsu_io_dmem_req_bits_0_bits_uop_lrs3), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ldst_val (_lsu_io_dmem_req_bits_0_bits_uop_ldst_val), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_dst_rtype (_lsu_io_dmem_req_bits_0_bits_uop_dst_rtype), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_lrs1_rtype (_lsu_io_dmem_req_bits_0_bits_uop_lrs1_rtype), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_lrs2_rtype (_lsu_io_dmem_req_bits_0_bits_uop_lrs2_rtype), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_frs3_en (_lsu_io_dmem_req_bits_0_bits_uop_frs3_en), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_fp_val (_lsu_io_dmem_req_bits_0_bits_uop_fp_val), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_fp_single (_lsu_io_dmem_req_bits_0_bits_uop_fp_single), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_xcpt_pf_if (_lsu_io_dmem_req_bits_0_bits_uop_xcpt_pf_if), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_xcpt_ae_if (_lsu_io_dmem_req_bits_0_bits_uop_xcpt_ae_if), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_xcpt_ma_if (_lsu_io_dmem_req_bits_0_bits_uop_xcpt_ma_if), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_bp_debug_if (_lsu_io_dmem_req_bits_0_bits_uop_bp_debug_if), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_bp_xcpt_if (_lsu_io_dmem_req_bits_0_bits_uop_bp_xcpt_if), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_debug_fsrc (_lsu_io_dmem_req_bits_0_bits_uop_debug_fsrc), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_debug_tsrc (_lsu_io_dmem_req_bits_0_bits_uop_debug_tsrc), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_addr (_lsu_io_dmem_req_bits_0_bits_addr), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_data (_lsu_io_dmem_req_bits_0_bits_data), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_is_hella (_lsu_io_dmem_req_bits_0_bits_is_hella), // @[tile.scala:160:20]
.io_lsu_s1_kill_0 (_lsu_io_dmem_s1_kill_0), // @[tile.scala:160:20]
.io_lsu_resp_0_valid (_dcache_io_lsu_resp_0_valid),
.io_lsu_resp_0_bits_uop_uopc (_dcache_io_lsu_resp_0_bits_uop_uopc),
.io_lsu_resp_0_bits_uop_inst (_dcache_io_lsu_resp_0_bits_uop_inst),
.io_lsu_resp_0_bits_uop_debug_inst (_dcache_io_lsu_resp_0_bits_uop_debug_inst),
.io_lsu_resp_0_bits_uop_is_rvc (_dcache_io_lsu_resp_0_bits_uop_is_rvc),
.io_lsu_resp_0_bits_uop_debug_pc (_dcache_io_lsu_resp_0_bits_uop_debug_pc),
.io_lsu_resp_0_bits_uop_iq_type (_dcache_io_lsu_resp_0_bits_uop_iq_type),
.io_lsu_resp_0_bits_uop_fu_code (_dcache_io_lsu_resp_0_bits_uop_fu_code),
.io_lsu_resp_0_bits_uop_ctrl_br_type (_dcache_io_lsu_resp_0_bits_uop_ctrl_br_type),
.io_lsu_resp_0_bits_uop_ctrl_op1_sel (_dcache_io_lsu_resp_0_bits_uop_ctrl_op1_sel),
.io_lsu_resp_0_bits_uop_ctrl_op2_sel (_dcache_io_lsu_resp_0_bits_uop_ctrl_op2_sel),
.io_lsu_resp_0_bits_uop_ctrl_imm_sel (_dcache_io_lsu_resp_0_bits_uop_ctrl_imm_sel),
.io_lsu_resp_0_bits_uop_ctrl_op_fcn (_dcache_io_lsu_resp_0_bits_uop_ctrl_op_fcn),
.io_lsu_resp_0_bits_uop_ctrl_fcn_dw (_dcache_io_lsu_resp_0_bits_uop_ctrl_fcn_dw),
.io_lsu_resp_0_bits_uop_ctrl_csr_cmd (_dcache_io_lsu_resp_0_bits_uop_ctrl_csr_cmd),
.io_lsu_resp_0_bits_uop_ctrl_is_load (_dcache_io_lsu_resp_0_bits_uop_ctrl_is_load),
.io_lsu_resp_0_bits_uop_ctrl_is_sta (_dcache_io_lsu_resp_0_bits_uop_ctrl_is_sta),
.io_lsu_resp_0_bits_uop_ctrl_is_std (_dcache_io_lsu_resp_0_bits_uop_ctrl_is_std),
.io_lsu_resp_0_bits_uop_iw_state (_dcache_io_lsu_resp_0_bits_uop_iw_state),
.io_lsu_resp_0_bits_uop_iw_p1_poisoned (_dcache_io_lsu_resp_0_bits_uop_iw_p1_poisoned),
.io_lsu_resp_0_bits_uop_iw_p2_poisoned (_dcache_io_lsu_resp_0_bits_uop_iw_p2_poisoned),
.io_lsu_resp_0_bits_uop_is_br (_dcache_io_lsu_resp_0_bits_uop_is_br),
.io_lsu_resp_0_bits_uop_is_jalr (_dcache_io_lsu_resp_0_bits_uop_is_jalr),
.io_lsu_resp_0_bits_uop_is_jal (_dcache_io_lsu_resp_0_bits_uop_is_jal),
.io_lsu_resp_0_bits_uop_is_sfb (_dcache_io_lsu_resp_0_bits_uop_is_sfb),
.io_lsu_resp_0_bits_uop_br_mask (_dcache_io_lsu_resp_0_bits_uop_br_mask),
.io_lsu_resp_0_bits_uop_br_tag (_dcache_io_lsu_resp_0_bits_uop_br_tag),
.io_lsu_resp_0_bits_uop_ftq_idx (_dcache_io_lsu_resp_0_bits_uop_ftq_idx),
.io_lsu_resp_0_bits_uop_edge_inst (_dcache_io_lsu_resp_0_bits_uop_edge_inst),
.io_lsu_resp_0_bits_uop_pc_lob (_dcache_io_lsu_resp_0_bits_uop_pc_lob),
.io_lsu_resp_0_bits_uop_taken (_dcache_io_lsu_resp_0_bits_uop_taken),
.io_lsu_resp_0_bits_uop_imm_packed (_dcache_io_lsu_resp_0_bits_uop_imm_packed),
.io_lsu_resp_0_bits_uop_csr_addr (_dcache_io_lsu_resp_0_bits_uop_csr_addr),
.io_lsu_resp_0_bits_uop_rob_idx (_dcache_io_lsu_resp_0_bits_uop_rob_idx),
.io_lsu_resp_0_bits_uop_ldq_idx (_dcache_io_lsu_resp_0_bits_uop_ldq_idx),
.io_lsu_resp_0_bits_uop_stq_idx (_dcache_io_lsu_resp_0_bits_uop_stq_idx),
.io_lsu_resp_0_bits_uop_rxq_idx (_dcache_io_lsu_resp_0_bits_uop_rxq_idx),
.io_lsu_resp_0_bits_uop_pdst (_dcache_io_lsu_resp_0_bits_uop_pdst),
.io_lsu_resp_0_bits_uop_prs1 (_dcache_io_lsu_resp_0_bits_uop_prs1),
.io_lsu_resp_0_bits_uop_prs2 (_dcache_io_lsu_resp_0_bits_uop_prs2),
.io_lsu_resp_0_bits_uop_prs3 (_dcache_io_lsu_resp_0_bits_uop_prs3),
.io_lsu_resp_0_bits_uop_ppred (_dcache_io_lsu_resp_0_bits_uop_ppred),
.io_lsu_resp_0_bits_uop_prs1_busy (_dcache_io_lsu_resp_0_bits_uop_prs1_busy),
.io_lsu_resp_0_bits_uop_prs2_busy (_dcache_io_lsu_resp_0_bits_uop_prs2_busy),
.io_lsu_resp_0_bits_uop_prs3_busy (_dcache_io_lsu_resp_0_bits_uop_prs3_busy),
.io_lsu_resp_0_bits_uop_ppred_busy (_dcache_io_lsu_resp_0_bits_uop_ppred_busy),
.io_lsu_resp_0_bits_uop_stale_pdst (_dcache_io_lsu_resp_0_bits_uop_stale_pdst),
.io_lsu_resp_0_bits_uop_exception (_dcache_io_lsu_resp_0_bits_uop_exception),
.io_lsu_resp_0_bits_uop_exc_cause (_dcache_io_lsu_resp_0_bits_uop_exc_cause),
.io_lsu_resp_0_bits_uop_bypassable (_dcache_io_lsu_resp_0_bits_uop_bypassable),
.io_lsu_resp_0_bits_uop_mem_cmd (_dcache_io_lsu_resp_0_bits_uop_mem_cmd),
.io_lsu_resp_0_bits_uop_mem_size (_dcache_io_lsu_resp_0_bits_uop_mem_size),
.io_lsu_resp_0_bits_uop_mem_signed (_dcache_io_lsu_resp_0_bits_uop_mem_signed),
.io_lsu_resp_0_bits_uop_is_fence (_dcache_io_lsu_resp_0_bits_uop_is_fence),
.io_lsu_resp_0_bits_uop_is_fencei (_dcache_io_lsu_resp_0_bits_uop_is_fencei),
.io_lsu_resp_0_bits_uop_is_amo (_dcache_io_lsu_resp_0_bits_uop_is_amo),
.io_lsu_resp_0_bits_uop_uses_ldq (_dcache_io_lsu_resp_0_bits_uop_uses_ldq),
.io_lsu_resp_0_bits_uop_uses_stq (_dcache_io_lsu_resp_0_bits_uop_uses_stq),
.io_lsu_resp_0_bits_uop_is_sys_pc2epc (_dcache_io_lsu_resp_0_bits_uop_is_sys_pc2epc),
.io_lsu_resp_0_bits_uop_is_unique (_dcache_io_lsu_resp_0_bits_uop_is_unique),
.io_lsu_resp_0_bits_uop_flush_on_commit (_dcache_io_lsu_resp_0_bits_uop_flush_on_commit),
.io_lsu_resp_0_bits_uop_ldst_is_rs1 (_dcache_io_lsu_resp_0_bits_uop_ldst_is_rs1),
.io_lsu_resp_0_bits_uop_ldst (_dcache_io_lsu_resp_0_bits_uop_ldst),
.io_lsu_resp_0_bits_uop_lrs1 (_dcache_io_lsu_resp_0_bits_uop_lrs1),
.io_lsu_resp_0_bits_uop_lrs2 (_dcache_io_lsu_resp_0_bits_uop_lrs2),
.io_lsu_resp_0_bits_uop_lrs3 (_dcache_io_lsu_resp_0_bits_uop_lrs3),
.io_lsu_resp_0_bits_uop_ldst_val (_dcache_io_lsu_resp_0_bits_uop_ldst_val),
.io_lsu_resp_0_bits_uop_dst_rtype (_dcache_io_lsu_resp_0_bits_uop_dst_rtype),
.io_lsu_resp_0_bits_uop_lrs1_rtype (_dcache_io_lsu_resp_0_bits_uop_lrs1_rtype),
.io_lsu_resp_0_bits_uop_lrs2_rtype (_dcache_io_lsu_resp_0_bits_uop_lrs2_rtype),
.io_lsu_resp_0_bits_uop_frs3_en (_dcache_io_lsu_resp_0_bits_uop_frs3_en),
.io_lsu_resp_0_bits_uop_fp_val (_dcache_io_lsu_resp_0_bits_uop_fp_val),
.io_lsu_resp_0_bits_uop_fp_single (_dcache_io_lsu_resp_0_bits_uop_fp_single),
.io_lsu_resp_0_bits_uop_xcpt_pf_if (_dcache_io_lsu_resp_0_bits_uop_xcpt_pf_if),
.io_lsu_resp_0_bits_uop_xcpt_ae_if (_dcache_io_lsu_resp_0_bits_uop_xcpt_ae_if),
.io_lsu_resp_0_bits_uop_xcpt_ma_if (_dcache_io_lsu_resp_0_bits_uop_xcpt_ma_if),
.io_lsu_resp_0_bits_uop_bp_debug_if (_dcache_io_lsu_resp_0_bits_uop_bp_debug_if),
.io_lsu_resp_0_bits_uop_bp_xcpt_if (_dcache_io_lsu_resp_0_bits_uop_bp_xcpt_if),
.io_lsu_resp_0_bits_uop_debug_fsrc (_dcache_io_lsu_resp_0_bits_uop_debug_fsrc),
.io_lsu_resp_0_bits_uop_debug_tsrc (_dcache_io_lsu_resp_0_bits_uop_debug_tsrc),
.io_lsu_resp_0_bits_data (_dcache_io_lsu_resp_0_bits_data),
.io_lsu_resp_0_bits_is_hella (_dcache_io_lsu_resp_0_bits_is_hella),
.io_lsu_nack_0_valid (_dcache_io_lsu_nack_0_valid),
.io_lsu_nack_0_bits_uop_uopc (_dcache_io_lsu_nack_0_bits_uop_uopc),
.io_lsu_nack_0_bits_uop_inst (_dcache_io_lsu_nack_0_bits_uop_inst),
.io_lsu_nack_0_bits_uop_debug_inst (_dcache_io_lsu_nack_0_bits_uop_debug_inst),
.io_lsu_nack_0_bits_uop_is_rvc (_dcache_io_lsu_nack_0_bits_uop_is_rvc),
.io_lsu_nack_0_bits_uop_debug_pc (_dcache_io_lsu_nack_0_bits_uop_debug_pc),
.io_lsu_nack_0_bits_uop_iq_type (_dcache_io_lsu_nack_0_bits_uop_iq_type),
.io_lsu_nack_0_bits_uop_fu_code (_dcache_io_lsu_nack_0_bits_uop_fu_code),
.io_lsu_nack_0_bits_uop_ctrl_br_type (_dcache_io_lsu_nack_0_bits_uop_ctrl_br_type),
.io_lsu_nack_0_bits_uop_ctrl_op1_sel (_dcache_io_lsu_nack_0_bits_uop_ctrl_op1_sel),
.io_lsu_nack_0_bits_uop_ctrl_op2_sel (_dcache_io_lsu_nack_0_bits_uop_ctrl_op2_sel),
.io_lsu_nack_0_bits_uop_ctrl_imm_sel (_dcache_io_lsu_nack_0_bits_uop_ctrl_imm_sel),
.io_lsu_nack_0_bits_uop_ctrl_op_fcn (_dcache_io_lsu_nack_0_bits_uop_ctrl_op_fcn),
.io_lsu_nack_0_bits_uop_ctrl_fcn_dw (_dcache_io_lsu_nack_0_bits_uop_ctrl_fcn_dw),
.io_lsu_nack_0_bits_uop_ctrl_csr_cmd (_dcache_io_lsu_nack_0_bits_uop_ctrl_csr_cmd),
.io_lsu_nack_0_bits_uop_ctrl_is_load (_dcache_io_lsu_nack_0_bits_uop_ctrl_is_load),
.io_lsu_nack_0_bits_uop_ctrl_is_sta (_dcache_io_lsu_nack_0_bits_uop_ctrl_is_sta),
.io_lsu_nack_0_bits_uop_ctrl_is_std (_dcache_io_lsu_nack_0_bits_uop_ctrl_is_std),
.io_lsu_nack_0_bits_uop_iw_state (_dcache_io_lsu_nack_0_bits_uop_iw_state),
.io_lsu_nack_0_bits_uop_iw_p1_poisoned (_dcache_io_lsu_nack_0_bits_uop_iw_p1_poisoned),
.io_lsu_nack_0_bits_uop_iw_p2_poisoned (_dcache_io_lsu_nack_0_bits_uop_iw_p2_poisoned),
.io_lsu_nack_0_bits_uop_is_br (_dcache_io_lsu_nack_0_bits_uop_is_br),
.io_lsu_nack_0_bits_uop_is_jalr (_dcache_io_lsu_nack_0_bits_uop_is_jalr),
.io_lsu_nack_0_bits_uop_is_jal (_dcache_io_lsu_nack_0_bits_uop_is_jal),
.io_lsu_nack_0_bits_uop_is_sfb (_dcache_io_lsu_nack_0_bits_uop_is_sfb),
.io_lsu_nack_0_bits_uop_br_mask (_dcache_io_lsu_nack_0_bits_uop_br_mask),
.io_lsu_nack_0_bits_uop_br_tag (_dcache_io_lsu_nack_0_bits_uop_br_tag),
.io_lsu_nack_0_bits_uop_ftq_idx (_dcache_io_lsu_nack_0_bits_uop_ftq_idx),
.io_lsu_nack_0_bits_uop_edge_inst (_dcache_io_lsu_nack_0_bits_uop_edge_inst),
.io_lsu_nack_0_bits_uop_pc_lob (_dcache_io_lsu_nack_0_bits_uop_pc_lob),
.io_lsu_nack_0_bits_uop_taken (_dcache_io_lsu_nack_0_bits_uop_taken),
.io_lsu_nack_0_bits_uop_imm_packed (_dcache_io_lsu_nack_0_bits_uop_imm_packed),
.io_lsu_nack_0_bits_uop_csr_addr (_dcache_io_lsu_nack_0_bits_uop_csr_addr),
.io_lsu_nack_0_bits_uop_rob_idx (_dcache_io_lsu_nack_0_bits_uop_rob_idx),
.io_lsu_nack_0_bits_uop_ldq_idx (_dcache_io_lsu_nack_0_bits_uop_ldq_idx),
.io_lsu_nack_0_bits_uop_stq_idx (_dcache_io_lsu_nack_0_bits_uop_stq_idx),
.io_lsu_nack_0_bits_uop_rxq_idx (_dcache_io_lsu_nack_0_bits_uop_rxq_idx),
.io_lsu_nack_0_bits_uop_pdst (_dcache_io_lsu_nack_0_bits_uop_pdst),
.io_lsu_nack_0_bits_uop_prs1 (_dcache_io_lsu_nack_0_bits_uop_prs1),
.io_lsu_nack_0_bits_uop_prs2 (_dcache_io_lsu_nack_0_bits_uop_prs2),
.io_lsu_nack_0_bits_uop_prs3 (_dcache_io_lsu_nack_0_bits_uop_prs3),
.io_lsu_nack_0_bits_uop_ppred (_dcache_io_lsu_nack_0_bits_uop_ppred),
.io_lsu_nack_0_bits_uop_prs1_busy (_dcache_io_lsu_nack_0_bits_uop_prs1_busy),
.io_lsu_nack_0_bits_uop_prs2_busy (_dcache_io_lsu_nack_0_bits_uop_prs2_busy),
.io_lsu_nack_0_bits_uop_prs3_busy (_dcache_io_lsu_nack_0_bits_uop_prs3_busy),
.io_lsu_nack_0_bits_uop_ppred_busy (_dcache_io_lsu_nack_0_bits_uop_ppred_busy),
.io_lsu_nack_0_bits_uop_stale_pdst (_dcache_io_lsu_nack_0_bits_uop_stale_pdst),
.io_lsu_nack_0_bits_uop_exception (_dcache_io_lsu_nack_0_bits_uop_exception),
.io_lsu_nack_0_bits_uop_exc_cause (_dcache_io_lsu_nack_0_bits_uop_exc_cause),
.io_lsu_nack_0_bits_uop_bypassable (_dcache_io_lsu_nack_0_bits_uop_bypassable),
.io_lsu_nack_0_bits_uop_mem_cmd (_dcache_io_lsu_nack_0_bits_uop_mem_cmd),
.io_lsu_nack_0_bits_uop_mem_size (_dcache_io_lsu_nack_0_bits_uop_mem_size),
.io_lsu_nack_0_bits_uop_mem_signed (_dcache_io_lsu_nack_0_bits_uop_mem_signed),
.io_lsu_nack_0_bits_uop_is_fence (_dcache_io_lsu_nack_0_bits_uop_is_fence),
.io_lsu_nack_0_bits_uop_is_fencei (_dcache_io_lsu_nack_0_bits_uop_is_fencei),
.io_lsu_nack_0_bits_uop_is_amo (_dcache_io_lsu_nack_0_bits_uop_is_amo),
.io_lsu_nack_0_bits_uop_uses_ldq (_dcache_io_lsu_nack_0_bits_uop_uses_ldq),
.io_lsu_nack_0_bits_uop_uses_stq (_dcache_io_lsu_nack_0_bits_uop_uses_stq),
.io_lsu_nack_0_bits_uop_is_sys_pc2epc (_dcache_io_lsu_nack_0_bits_uop_is_sys_pc2epc),
.io_lsu_nack_0_bits_uop_is_unique (_dcache_io_lsu_nack_0_bits_uop_is_unique),
.io_lsu_nack_0_bits_uop_flush_on_commit (_dcache_io_lsu_nack_0_bits_uop_flush_on_commit),
.io_lsu_nack_0_bits_uop_ldst_is_rs1 (_dcache_io_lsu_nack_0_bits_uop_ldst_is_rs1),
.io_lsu_nack_0_bits_uop_ldst (_dcache_io_lsu_nack_0_bits_uop_ldst),
.io_lsu_nack_0_bits_uop_lrs1 (_dcache_io_lsu_nack_0_bits_uop_lrs1),
.io_lsu_nack_0_bits_uop_lrs2 (_dcache_io_lsu_nack_0_bits_uop_lrs2),
.io_lsu_nack_0_bits_uop_lrs3 (_dcache_io_lsu_nack_0_bits_uop_lrs3),
.io_lsu_nack_0_bits_uop_ldst_val (_dcache_io_lsu_nack_0_bits_uop_ldst_val),
.io_lsu_nack_0_bits_uop_dst_rtype (_dcache_io_lsu_nack_0_bits_uop_dst_rtype),
.io_lsu_nack_0_bits_uop_lrs1_rtype (_dcache_io_lsu_nack_0_bits_uop_lrs1_rtype),
.io_lsu_nack_0_bits_uop_lrs2_rtype (_dcache_io_lsu_nack_0_bits_uop_lrs2_rtype),
.io_lsu_nack_0_bits_uop_frs3_en (_dcache_io_lsu_nack_0_bits_uop_frs3_en),
.io_lsu_nack_0_bits_uop_fp_val (_dcache_io_lsu_nack_0_bits_uop_fp_val),
.io_lsu_nack_0_bits_uop_fp_single (_dcache_io_lsu_nack_0_bits_uop_fp_single),
.io_lsu_nack_0_bits_uop_xcpt_pf_if (_dcache_io_lsu_nack_0_bits_uop_xcpt_pf_if),
.io_lsu_nack_0_bits_uop_xcpt_ae_if (_dcache_io_lsu_nack_0_bits_uop_xcpt_ae_if),
.io_lsu_nack_0_bits_uop_xcpt_ma_if (_dcache_io_lsu_nack_0_bits_uop_xcpt_ma_if),
.io_lsu_nack_0_bits_uop_bp_debug_if (_dcache_io_lsu_nack_0_bits_uop_bp_debug_if),
.io_lsu_nack_0_bits_uop_bp_xcpt_if (_dcache_io_lsu_nack_0_bits_uop_bp_xcpt_if),
.io_lsu_nack_0_bits_uop_debug_fsrc (_dcache_io_lsu_nack_0_bits_uop_debug_fsrc),
.io_lsu_nack_0_bits_uop_debug_tsrc (_dcache_io_lsu_nack_0_bits_uop_debug_tsrc),
.io_lsu_nack_0_bits_addr (_dcache_io_lsu_nack_0_bits_addr),
.io_lsu_nack_0_bits_data (_dcache_io_lsu_nack_0_bits_data),
.io_lsu_nack_0_bits_is_hella (_dcache_io_lsu_nack_0_bits_is_hella),
.io_lsu_brupdate_b1_resolve_mask (_lsu_io_dmem_brupdate_b1_resolve_mask), // @[tile.scala:160:20]
.io_lsu_brupdate_b1_mispredict_mask (_lsu_io_dmem_brupdate_b1_mispredict_mask), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_uopc (_lsu_io_dmem_brupdate_b2_uop_uopc), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_inst (_lsu_io_dmem_brupdate_b2_uop_inst), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_debug_inst (_lsu_io_dmem_brupdate_b2_uop_debug_inst), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_is_rvc (_lsu_io_dmem_brupdate_b2_uop_is_rvc), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_debug_pc (_lsu_io_dmem_brupdate_b2_uop_debug_pc), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_iq_type (_lsu_io_dmem_brupdate_b2_uop_iq_type), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_fu_code (_lsu_io_dmem_brupdate_b2_uop_fu_code), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ctrl_br_type (_lsu_io_dmem_brupdate_b2_uop_ctrl_br_type), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ctrl_op1_sel (_lsu_io_dmem_brupdate_b2_uop_ctrl_op1_sel), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ctrl_op2_sel (_lsu_io_dmem_brupdate_b2_uop_ctrl_op2_sel), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ctrl_imm_sel (_lsu_io_dmem_brupdate_b2_uop_ctrl_imm_sel), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ctrl_op_fcn (_lsu_io_dmem_brupdate_b2_uop_ctrl_op_fcn), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ctrl_fcn_dw (_lsu_io_dmem_brupdate_b2_uop_ctrl_fcn_dw), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ctrl_csr_cmd (_lsu_io_dmem_brupdate_b2_uop_ctrl_csr_cmd), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ctrl_is_load (_lsu_io_dmem_brupdate_b2_uop_ctrl_is_load), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ctrl_is_sta (_lsu_io_dmem_brupdate_b2_uop_ctrl_is_sta), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ctrl_is_std (_lsu_io_dmem_brupdate_b2_uop_ctrl_is_std), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_iw_state (_lsu_io_dmem_brupdate_b2_uop_iw_state), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_iw_p1_poisoned (_lsu_io_dmem_brupdate_b2_uop_iw_p1_poisoned), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_iw_p2_poisoned (_lsu_io_dmem_brupdate_b2_uop_iw_p2_poisoned), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_is_br (_lsu_io_dmem_brupdate_b2_uop_is_br), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_is_jalr (_lsu_io_dmem_brupdate_b2_uop_is_jalr), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_is_jal (_lsu_io_dmem_brupdate_b2_uop_is_jal), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_is_sfb (_lsu_io_dmem_brupdate_b2_uop_is_sfb), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_br_mask (_lsu_io_dmem_brupdate_b2_uop_br_mask), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_br_tag (_lsu_io_dmem_brupdate_b2_uop_br_tag), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ftq_idx (_lsu_io_dmem_brupdate_b2_uop_ftq_idx), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_edge_inst (_lsu_io_dmem_brupdate_b2_uop_edge_inst), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_pc_lob (_lsu_io_dmem_brupdate_b2_uop_pc_lob), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_taken (_lsu_io_dmem_brupdate_b2_uop_taken), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_imm_packed (_lsu_io_dmem_brupdate_b2_uop_imm_packed), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_csr_addr (_lsu_io_dmem_brupdate_b2_uop_csr_addr), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_rob_idx (_lsu_io_dmem_brupdate_b2_uop_rob_idx), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ldq_idx (_lsu_io_dmem_brupdate_b2_uop_ldq_idx), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_stq_idx (_lsu_io_dmem_brupdate_b2_uop_stq_idx), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_rxq_idx (_lsu_io_dmem_brupdate_b2_uop_rxq_idx), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_pdst (_lsu_io_dmem_brupdate_b2_uop_pdst), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_prs1 (_lsu_io_dmem_brupdate_b2_uop_prs1), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_prs2 (_lsu_io_dmem_brupdate_b2_uop_prs2), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_prs3 (_lsu_io_dmem_brupdate_b2_uop_prs3), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ppred (_lsu_io_dmem_brupdate_b2_uop_ppred), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_prs1_busy (_lsu_io_dmem_brupdate_b2_uop_prs1_busy), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_prs2_busy (_lsu_io_dmem_brupdate_b2_uop_prs2_busy), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_prs3_busy (_lsu_io_dmem_brupdate_b2_uop_prs3_busy), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ppred_busy (_lsu_io_dmem_brupdate_b2_uop_ppred_busy), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_stale_pdst (_lsu_io_dmem_brupdate_b2_uop_stale_pdst), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_exception (_lsu_io_dmem_brupdate_b2_uop_exception), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_exc_cause (_lsu_io_dmem_brupdate_b2_uop_exc_cause), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_bypassable (_lsu_io_dmem_brupdate_b2_uop_bypassable), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_mem_cmd (_lsu_io_dmem_brupdate_b2_uop_mem_cmd), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_mem_size (_lsu_io_dmem_brupdate_b2_uop_mem_size), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_mem_signed (_lsu_io_dmem_brupdate_b2_uop_mem_signed), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_is_fence (_lsu_io_dmem_brupdate_b2_uop_is_fence), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_is_fencei (_lsu_io_dmem_brupdate_b2_uop_is_fencei), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_is_amo (_lsu_io_dmem_brupdate_b2_uop_is_amo), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_uses_ldq (_lsu_io_dmem_brupdate_b2_uop_uses_ldq), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_uses_stq (_lsu_io_dmem_brupdate_b2_uop_uses_stq), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_is_sys_pc2epc (_lsu_io_dmem_brupdate_b2_uop_is_sys_pc2epc), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_is_unique (_lsu_io_dmem_brupdate_b2_uop_is_unique), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_flush_on_commit (_lsu_io_dmem_brupdate_b2_uop_flush_on_commit), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ldst_is_rs1 (_lsu_io_dmem_brupdate_b2_uop_ldst_is_rs1), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ldst (_lsu_io_dmem_brupdate_b2_uop_ldst), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_lrs1 (_lsu_io_dmem_brupdate_b2_uop_lrs1), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_lrs2 (_lsu_io_dmem_brupdate_b2_uop_lrs2), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_lrs3 (_lsu_io_dmem_brupdate_b2_uop_lrs3), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ldst_val (_lsu_io_dmem_brupdate_b2_uop_ldst_val), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_dst_rtype (_lsu_io_dmem_brupdate_b2_uop_dst_rtype), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_lrs1_rtype (_lsu_io_dmem_brupdate_b2_uop_lrs1_rtype), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_lrs2_rtype (_lsu_io_dmem_brupdate_b2_uop_lrs2_rtype), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_frs3_en (_lsu_io_dmem_brupdate_b2_uop_frs3_en), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_fp_val (_lsu_io_dmem_brupdate_b2_uop_fp_val), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_fp_single (_lsu_io_dmem_brupdate_b2_uop_fp_single), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_xcpt_pf_if (_lsu_io_dmem_brupdate_b2_uop_xcpt_pf_if), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_xcpt_ae_if (_lsu_io_dmem_brupdate_b2_uop_xcpt_ae_if), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_xcpt_ma_if (_lsu_io_dmem_brupdate_b2_uop_xcpt_ma_if), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_bp_debug_if (_lsu_io_dmem_brupdate_b2_uop_bp_debug_if), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_bp_xcpt_if (_lsu_io_dmem_brupdate_b2_uop_bp_xcpt_if), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_debug_fsrc (_lsu_io_dmem_brupdate_b2_uop_debug_fsrc), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_debug_tsrc (_lsu_io_dmem_brupdate_b2_uop_debug_tsrc), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_valid (_lsu_io_dmem_brupdate_b2_valid), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_mispredict (_lsu_io_dmem_brupdate_b2_mispredict), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_taken (_lsu_io_dmem_brupdate_b2_taken), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_cfi_type (_lsu_io_dmem_brupdate_b2_cfi_type), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_pc_sel (_lsu_io_dmem_brupdate_b2_pc_sel), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_jalr_target (_lsu_io_dmem_brupdate_b2_jalr_target), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_target_offset (_lsu_io_dmem_brupdate_b2_target_offset), // @[tile.scala:160:20]
.io_lsu_exception (_lsu_io_dmem_exception), // @[tile.scala:160:20]
.io_lsu_rob_pnr_idx (_lsu_io_dmem_rob_pnr_idx), // @[tile.scala:160:20]
.io_lsu_rob_head_idx (_lsu_io_dmem_rob_head_idx), // @[tile.scala:160:20]
.io_lsu_release_ready (_lsu_io_dmem_release_ready), // @[tile.scala:160:20]
.io_lsu_release_valid (_dcache_io_lsu_release_valid),
.io_lsu_release_bits_opcode (_dcache_io_lsu_release_bits_opcode),
.io_lsu_release_bits_param (_dcache_io_lsu_release_bits_param),
.io_lsu_release_bits_size (_dcache_io_lsu_release_bits_size),
.io_lsu_release_bits_source (_dcache_io_lsu_release_bits_source),
.io_lsu_release_bits_address (_dcache_io_lsu_release_bits_address),
.io_lsu_release_bits_data (_dcache_io_lsu_release_bits_data),
.io_lsu_force_order (_lsu_io_dmem_force_order), // @[tile.scala:160:20]
.io_lsu_ordered (_dcache_io_lsu_ordered),
.io_lsu_perf_acquire (_dcache_io_lsu_perf_acquire),
.io_lsu_perf_release (_dcache_io_lsu_perf_release)
); // @[tile.scala:132:54]
BoomFrontend_1 frontend ( // @[tile.scala:138:28]
.clock (clock),
.reset (reset),
.auto_icache_master_out_a_ready (widget_1_auto_anon_in_a_ready), // @[WidthWidget.scala:27:9]
.auto_icache_master_out_a_valid (widget_1_auto_anon_in_a_valid),
.auto_icache_master_out_a_bits_address (widget_1_auto_anon_in_a_bits_address),
.auto_icache_master_out_d_valid (widget_1_auto_anon_in_d_valid), // @[WidthWidget.scala:27:9]
.auto_icache_master_out_d_bits_opcode (widget_1_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:27:9]
.auto_icache_master_out_d_bits_param (widget_1_auto_anon_in_d_bits_param), // @[WidthWidget.scala:27:9]
.auto_icache_master_out_d_bits_size (widget_1_auto_anon_in_d_bits_size), // @[WidthWidget.scala:27:9]
.auto_icache_master_out_d_bits_sink (widget_1_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:27:9]
.auto_icache_master_out_d_bits_denied (widget_1_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:27:9]
.auto_icache_master_out_d_bits_data (widget_1_auto_anon_in_d_bits_data), // @[WidthWidget.scala:27:9]
.auto_icache_master_out_d_bits_corrupt (widget_1_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:27:9]
.io_cpu_fetchpacket_ready (_core_io_ifu_fetchpacket_ready), // @[tile.scala:159:20]
.io_cpu_fetchpacket_valid (_frontend_io_cpu_fetchpacket_valid),
.io_cpu_fetchpacket_bits_uops_0_valid (_frontend_io_cpu_fetchpacket_bits_uops_0_valid),
.io_cpu_fetchpacket_bits_uops_0_bits_inst (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_inst),
.io_cpu_fetchpacket_bits_uops_0_bits_debug_inst (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_inst),
.io_cpu_fetchpacket_bits_uops_0_bits_is_rvc (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_is_rvc),
.io_cpu_fetchpacket_bits_uops_0_bits_debug_pc (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_pc),
.io_cpu_fetchpacket_bits_uops_0_bits_is_sfb (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_is_sfb),
.io_cpu_fetchpacket_bits_uops_0_bits_ftq_idx (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_ftq_idx),
.io_cpu_fetchpacket_bits_uops_0_bits_edge_inst (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_edge_inst),
.io_cpu_fetchpacket_bits_uops_0_bits_pc_lob (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_pc_lob),
.io_cpu_fetchpacket_bits_uops_0_bits_taken (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_taken),
.io_cpu_fetchpacket_bits_uops_0_bits_xcpt_pf_if (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_xcpt_pf_if),
.io_cpu_fetchpacket_bits_uops_0_bits_xcpt_ae_if (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_xcpt_ae_if),
.io_cpu_fetchpacket_bits_uops_0_bits_bp_debug_if (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_bp_debug_if),
.io_cpu_fetchpacket_bits_uops_0_bits_bp_xcpt_if (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_bp_xcpt_if),
.io_cpu_fetchpacket_bits_uops_0_bits_debug_fsrc (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_fsrc),
.io_cpu_fetchpacket_bits_uops_1_valid (_frontend_io_cpu_fetchpacket_bits_uops_1_valid),
.io_cpu_fetchpacket_bits_uops_1_bits_inst (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_inst),
.io_cpu_fetchpacket_bits_uops_1_bits_debug_inst (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_inst),
.io_cpu_fetchpacket_bits_uops_1_bits_is_rvc (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_is_rvc),
.io_cpu_fetchpacket_bits_uops_1_bits_debug_pc (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_pc),
.io_cpu_fetchpacket_bits_uops_1_bits_is_sfb (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_is_sfb),
.io_cpu_fetchpacket_bits_uops_1_bits_ftq_idx (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_ftq_idx),
.io_cpu_fetchpacket_bits_uops_1_bits_edge_inst (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_edge_inst),
.io_cpu_fetchpacket_bits_uops_1_bits_pc_lob (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_pc_lob),
.io_cpu_fetchpacket_bits_uops_1_bits_taken (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_taken),
.io_cpu_fetchpacket_bits_uops_1_bits_xcpt_pf_if (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_xcpt_pf_if),
.io_cpu_fetchpacket_bits_uops_1_bits_xcpt_ae_if (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_xcpt_ae_if),
.io_cpu_fetchpacket_bits_uops_1_bits_bp_debug_if (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_bp_debug_if),
.io_cpu_fetchpacket_bits_uops_1_bits_bp_xcpt_if (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_bp_xcpt_if),
.io_cpu_fetchpacket_bits_uops_1_bits_debug_fsrc (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_fsrc),
.io_cpu_fetchpacket_bits_uops_2_valid (_frontend_io_cpu_fetchpacket_bits_uops_2_valid),
.io_cpu_fetchpacket_bits_uops_2_bits_inst (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_inst),
.io_cpu_fetchpacket_bits_uops_2_bits_debug_inst (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_debug_inst),
.io_cpu_fetchpacket_bits_uops_2_bits_is_rvc (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_is_rvc),
.io_cpu_fetchpacket_bits_uops_2_bits_debug_pc (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_debug_pc),
.io_cpu_fetchpacket_bits_uops_2_bits_is_sfb (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_is_sfb),
.io_cpu_fetchpacket_bits_uops_2_bits_ftq_idx (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_ftq_idx),
.io_cpu_fetchpacket_bits_uops_2_bits_edge_inst (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_edge_inst),
.io_cpu_fetchpacket_bits_uops_2_bits_pc_lob (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_pc_lob),
.io_cpu_fetchpacket_bits_uops_2_bits_taken (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_taken),
.io_cpu_fetchpacket_bits_uops_2_bits_xcpt_pf_if (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_xcpt_pf_if),
.io_cpu_fetchpacket_bits_uops_2_bits_xcpt_ae_if (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_xcpt_ae_if),
.io_cpu_fetchpacket_bits_uops_2_bits_bp_debug_if (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_bp_debug_if),
.io_cpu_fetchpacket_bits_uops_2_bits_bp_xcpt_if (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_bp_xcpt_if),
.io_cpu_fetchpacket_bits_uops_2_bits_debug_fsrc (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_debug_fsrc),
.io_cpu_get_pc_0_ftq_idx (_core_io_ifu_get_pc_0_ftq_idx), // @[tile.scala:159:20]
.io_cpu_get_pc_0_entry_cfi_idx_valid (_frontend_io_cpu_get_pc_0_entry_cfi_idx_valid),
.io_cpu_get_pc_0_entry_cfi_idx_bits (_frontend_io_cpu_get_pc_0_entry_cfi_idx_bits),
.io_cpu_get_pc_0_entry_cfi_taken (_frontend_io_cpu_get_pc_0_entry_cfi_taken),
.io_cpu_get_pc_0_entry_cfi_mispredicted (_frontend_io_cpu_get_pc_0_entry_cfi_mispredicted),
.io_cpu_get_pc_0_entry_cfi_type (_frontend_io_cpu_get_pc_0_entry_cfi_type),
.io_cpu_get_pc_0_entry_br_mask (_frontend_io_cpu_get_pc_0_entry_br_mask),
.io_cpu_get_pc_0_entry_cfi_is_call (_frontend_io_cpu_get_pc_0_entry_cfi_is_call),
.io_cpu_get_pc_0_entry_cfi_is_ret (_frontend_io_cpu_get_pc_0_entry_cfi_is_ret),
.io_cpu_get_pc_0_entry_cfi_npc_plus4 (_frontend_io_cpu_get_pc_0_entry_cfi_npc_plus4),
.io_cpu_get_pc_0_entry_ras_top (_frontend_io_cpu_get_pc_0_entry_ras_top),
.io_cpu_get_pc_0_entry_ras_idx (_frontend_io_cpu_get_pc_0_entry_ras_idx),
.io_cpu_get_pc_0_entry_start_bank (_frontend_io_cpu_get_pc_0_entry_start_bank),
.io_cpu_get_pc_0_pc (_frontend_io_cpu_get_pc_0_pc),
.io_cpu_get_pc_0_com_pc (_frontend_io_cpu_get_pc_0_com_pc),
.io_cpu_get_pc_0_next_val (_frontend_io_cpu_get_pc_0_next_val),
.io_cpu_get_pc_0_next_pc (_frontend_io_cpu_get_pc_0_next_pc),
.io_cpu_get_pc_1_ftq_idx (_core_io_ifu_get_pc_1_ftq_idx), // @[tile.scala:159:20]
.io_cpu_get_pc_1_entry_cfi_idx_valid (_frontend_io_cpu_get_pc_1_entry_cfi_idx_valid),
.io_cpu_get_pc_1_entry_cfi_idx_bits (_frontend_io_cpu_get_pc_1_entry_cfi_idx_bits),
.io_cpu_get_pc_1_entry_cfi_taken (_frontend_io_cpu_get_pc_1_entry_cfi_taken),
.io_cpu_get_pc_1_entry_cfi_mispredicted (_frontend_io_cpu_get_pc_1_entry_cfi_mispredicted),
.io_cpu_get_pc_1_entry_cfi_type (_frontend_io_cpu_get_pc_1_entry_cfi_type),
.io_cpu_get_pc_1_entry_br_mask (_frontend_io_cpu_get_pc_1_entry_br_mask),
.io_cpu_get_pc_1_entry_cfi_is_call (_frontend_io_cpu_get_pc_1_entry_cfi_is_call),
.io_cpu_get_pc_1_entry_cfi_is_ret (_frontend_io_cpu_get_pc_1_entry_cfi_is_ret),
.io_cpu_get_pc_1_entry_cfi_npc_plus4 (_frontend_io_cpu_get_pc_1_entry_cfi_npc_plus4),
.io_cpu_get_pc_1_entry_ras_top (_frontend_io_cpu_get_pc_1_entry_ras_top),
.io_cpu_get_pc_1_entry_ras_idx (_frontend_io_cpu_get_pc_1_entry_ras_idx),
.io_cpu_get_pc_1_entry_start_bank (_frontend_io_cpu_get_pc_1_entry_start_bank),
.io_cpu_get_pc_1_ghist_old_history (_frontend_io_cpu_get_pc_1_ghist_old_history),
.io_cpu_get_pc_1_ghist_current_saw_branch_not_taken (_frontend_io_cpu_get_pc_1_ghist_current_saw_branch_not_taken),
.io_cpu_get_pc_1_ghist_new_saw_branch_not_taken (_frontend_io_cpu_get_pc_1_ghist_new_saw_branch_not_taken),
.io_cpu_get_pc_1_ghist_new_saw_branch_taken (_frontend_io_cpu_get_pc_1_ghist_new_saw_branch_taken),
.io_cpu_get_pc_1_ghist_ras_idx (_frontend_io_cpu_get_pc_1_ghist_ras_idx),
.io_cpu_get_pc_1_pc (_frontend_io_cpu_get_pc_1_pc),
.io_cpu_get_pc_1_com_pc (_frontend_io_cpu_get_pc_1_com_pc),
.io_cpu_get_pc_1_next_val (_frontend_io_cpu_get_pc_1_next_val),
.io_cpu_get_pc_1_next_pc (_frontend_io_cpu_get_pc_1_next_pc),
.io_cpu_debug_fetch_pc_0 (_frontend_io_cpu_debug_fetch_pc_0),
.io_cpu_debug_fetch_pc_1 (_frontend_io_cpu_debug_fetch_pc_1),
.io_cpu_debug_fetch_pc_2 (_frontend_io_cpu_debug_fetch_pc_2),
.io_cpu_status_debug (_core_io_ifu_status_debug), // @[tile.scala:159:20]
.io_cpu_status_cease (_core_io_ifu_status_cease), // @[tile.scala:159:20]
.io_cpu_status_wfi (_core_io_ifu_status_wfi), // @[tile.scala:159:20]
.io_cpu_status_dprv (_core_io_ifu_status_dprv), // @[tile.scala:159:20]
.io_cpu_status_dv (_core_io_ifu_status_dv), // @[tile.scala:159:20]
.io_cpu_status_prv (_core_io_ifu_status_prv), // @[tile.scala:159:20]
.io_cpu_status_v (_core_io_ifu_status_v), // @[tile.scala:159:20]
.io_cpu_status_sd (_core_io_ifu_status_sd), // @[tile.scala:159:20]
.io_cpu_status_mpv (_core_io_ifu_status_mpv), // @[tile.scala:159:20]
.io_cpu_status_gva (_core_io_ifu_status_gva), // @[tile.scala:159:20]
.io_cpu_status_tsr (_core_io_ifu_status_tsr), // @[tile.scala:159:20]
.io_cpu_status_tw (_core_io_ifu_status_tw), // @[tile.scala:159:20]
.io_cpu_status_tvm (_core_io_ifu_status_tvm), // @[tile.scala:159:20]
.io_cpu_status_mxr (_core_io_ifu_status_mxr), // @[tile.scala:159:20]
.io_cpu_status_sum (_core_io_ifu_status_sum), // @[tile.scala:159:20]
.io_cpu_status_mprv (_core_io_ifu_status_mprv), // @[tile.scala:159:20]
.io_cpu_status_fs (_core_io_ifu_status_fs), // @[tile.scala:159:20]
.io_cpu_status_mpp (_core_io_ifu_status_mpp), // @[tile.scala:159:20]
.io_cpu_status_spp (_core_io_ifu_status_spp), // @[tile.scala:159:20]
.io_cpu_status_mpie (_core_io_ifu_status_mpie), // @[tile.scala:159:20]
.io_cpu_status_spie (_core_io_ifu_status_spie), // @[tile.scala:159:20]
.io_cpu_status_mie (_core_io_ifu_status_mie), // @[tile.scala:159:20]
.io_cpu_status_sie (_core_io_ifu_status_sie), // @[tile.scala:159:20]
.io_cpu_sfence_valid (_core_io_ifu_sfence_valid), // @[tile.scala:159:20]
.io_cpu_sfence_bits_rs1 (_core_io_ifu_sfence_bits_rs1), // @[tile.scala:159:20]
.io_cpu_sfence_bits_rs2 (_core_io_ifu_sfence_bits_rs2), // @[tile.scala:159:20]
.io_cpu_sfence_bits_addr (_core_io_ifu_sfence_bits_addr), // @[tile.scala:159:20]
.io_cpu_sfence_bits_asid (_core_io_ifu_sfence_bits_asid), // @[tile.scala:159:20]
.io_cpu_brupdate_b1_resolve_mask (_core_io_ifu_brupdate_b1_resolve_mask), // @[tile.scala:159:20]
.io_cpu_brupdate_b1_mispredict_mask (_core_io_ifu_brupdate_b1_mispredict_mask), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_uopc (_core_io_ifu_brupdate_b2_uop_uopc), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_inst (_core_io_ifu_brupdate_b2_uop_inst), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_debug_inst (_core_io_ifu_brupdate_b2_uop_debug_inst), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_is_rvc (_core_io_ifu_brupdate_b2_uop_is_rvc), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_debug_pc (_core_io_ifu_brupdate_b2_uop_debug_pc), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_iq_type (_core_io_ifu_brupdate_b2_uop_iq_type), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_fu_code (_core_io_ifu_brupdate_b2_uop_fu_code), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ctrl_br_type (_core_io_ifu_brupdate_b2_uop_ctrl_br_type), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ctrl_op1_sel (_core_io_ifu_brupdate_b2_uop_ctrl_op1_sel), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ctrl_op2_sel (_core_io_ifu_brupdate_b2_uop_ctrl_op2_sel), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ctrl_imm_sel (_core_io_ifu_brupdate_b2_uop_ctrl_imm_sel), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ctrl_op_fcn (_core_io_ifu_brupdate_b2_uop_ctrl_op_fcn), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ctrl_fcn_dw (_core_io_ifu_brupdate_b2_uop_ctrl_fcn_dw), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ctrl_csr_cmd (_core_io_ifu_brupdate_b2_uop_ctrl_csr_cmd), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ctrl_is_load (_core_io_ifu_brupdate_b2_uop_ctrl_is_load), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ctrl_is_sta (_core_io_ifu_brupdate_b2_uop_ctrl_is_sta), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ctrl_is_std (_core_io_ifu_brupdate_b2_uop_ctrl_is_std), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_iw_state (_core_io_ifu_brupdate_b2_uop_iw_state), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_iw_p1_poisoned (_core_io_ifu_brupdate_b2_uop_iw_p1_poisoned), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_iw_p2_poisoned (_core_io_ifu_brupdate_b2_uop_iw_p2_poisoned), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_is_br (_core_io_ifu_brupdate_b2_uop_is_br), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_is_jalr (_core_io_ifu_brupdate_b2_uop_is_jalr), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_is_jal (_core_io_ifu_brupdate_b2_uop_is_jal), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_is_sfb (_core_io_ifu_brupdate_b2_uop_is_sfb), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_br_mask (_core_io_ifu_brupdate_b2_uop_br_mask), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_br_tag (_core_io_ifu_brupdate_b2_uop_br_tag), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ftq_idx (_core_io_ifu_brupdate_b2_uop_ftq_idx), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_edge_inst (_core_io_ifu_brupdate_b2_uop_edge_inst), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_pc_lob (_core_io_ifu_brupdate_b2_uop_pc_lob), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_taken (_core_io_ifu_brupdate_b2_uop_taken), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_imm_packed (_core_io_ifu_brupdate_b2_uop_imm_packed), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_csr_addr (_core_io_ifu_brupdate_b2_uop_csr_addr), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_rob_idx (_core_io_ifu_brupdate_b2_uop_rob_idx), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ldq_idx (_core_io_ifu_brupdate_b2_uop_ldq_idx), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_stq_idx (_core_io_ifu_brupdate_b2_uop_stq_idx), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_rxq_idx (_core_io_ifu_brupdate_b2_uop_rxq_idx), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_pdst (_core_io_ifu_brupdate_b2_uop_pdst), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_prs1 (_core_io_ifu_brupdate_b2_uop_prs1), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_prs2 (_core_io_ifu_brupdate_b2_uop_prs2), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_prs3 (_core_io_ifu_brupdate_b2_uop_prs3), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ppred (_core_io_ifu_brupdate_b2_uop_ppred), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_prs1_busy (_core_io_ifu_brupdate_b2_uop_prs1_busy), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_prs2_busy (_core_io_ifu_brupdate_b2_uop_prs2_busy), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_prs3_busy (_core_io_ifu_brupdate_b2_uop_prs3_busy), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ppred_busy (_core_io_ifu_brupdate_b2_uop_ppred_busy), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_stale_pdst (_core_io_ifu_brupdate_b2_uop_stale_pdst), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_exception (_core_io_ifu_brupdate_b2_uop_exception), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_exc_cause (_core_io_ifu_brupdate_b2_uop_exc_cause), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_bypassable (_core_io_ifu_brupdate_b2_uop_bypassable), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_mem_cmd (_core_io_ifu_brupdate_b2_uop_mem_cmd), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_mem_size (_core_io_ifu_brupdate_b2_uop_mem_size), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_mem_signed (_core_io_ifu_brupdate_b2_uop_mem_signed), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_is_fence (_core_io_ifu_brupdate_b2_uop_is_fence), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_is_fencei (_core_io_ifu_brupdate_b2_uop_is_fencei), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_is_amo (_core_io_ifu_brupdate_b2_uop_is_amo), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_uses_ldq (_core_io_ifu_brupdate_b2_uop_uses_ldq), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_uses_stq (_core_io_ifu_brupdate_b2_uop_uses_stq), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_is_sys_pc2epc (_core_io_ifu_brupdate_b2_uop_is_sys_pc2epc), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_is_unique (_core_io_ifu_brupdate_b2_uop_is_unique), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_flush_on_commit (_core_io_ifu_brupdate_b2_uop_flush_on_commit), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ldst_is_rs1 (_core_io_ifu_brupdate_b2_uop_ldst_is_rs1), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ldst (_core_io_ifu_brupdate_b2_uop_ldst), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_lrs1 (_core_io_ifu_brupdate_b2_uop_lrs1), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_lrs2 (_core_io_ifu_brupdate_b2_uop_lrs2), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_lrs3 (_core_io_ifu_brupdate_b2_uop_lrs3), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ldst_val (_core_io_ifu_brupdate_b2_uop_ldst_val), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_dst_rtype (_core_io_ifu_brupdate_b2_uop_dst_rtype), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_lrs1_rtype (_core_io_ifu_brupdate_b2_uop_lrs1_rtype), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_lrs2_rtype (_core_io_ifu_brupdate_b2_uop_lrs2_rtype), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_frs3_en (_core_io_ifu_brupdate_b2_uop_frs3_en), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_fp_val (_core_io_ifu_brupdate_b2_uop_fp_val), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_fp_single (_core_io_ifu_brupdate_b2_uop_fp_single), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_xcpt_pf_if (_core_io_ifu_brupdate_b2_uop_xcpt_pf_if), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_xcpt_ae_if (_core_io_ifu_brupdate_b2_uop_xcpt_ae_if), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_xcpt_ma_if (_core_io_ifu_brupdate_b2_uop_xcpt_ma_if), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_bp_debug_if (_core_io_ifu_brupdate_b2_uop_bp_debug_if), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_bp_xcpt_if (_core_io_ifu_brupdate_b2_uop_bp_xcpt_if), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_debug_fsrc (_core_io_ifu_brupdate_b2_uop_debug_fsrc), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_debug_tsrc (_core_io_ifu_brupdate_b2_uop_debug_tsrc), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_valid (_core_io_ifu_brupdate_b2_valid), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_mispredict (_core_io_ifu_brupdate_b2_mispredict), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_taken (_core_io_ifu_brupdate_b2_taken), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_cfi_type (_core_io_ifu_brupdate_b2_cfi_type), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_pc_sel (_core_io_ifu_brupdate_b2_pc_sel), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_jalr_target (_core_io_ifu_brupdate_b2_jalr_target), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_target_offset (_core_io_ifu_brupdate_b2_target_offset), // @[tile.scala:159:20]
.io_cpu_redirect_flush (_core_io_ifu_redirect_flush), // @[tile.scala:159:20]
.io_cpu_redirect_val (_core_io_ifu_redirect_val), // @[tile.scala:159:20]
.io_cpu_redirect_pc (_core_io_ifu_redirect_pc), // @[tile.scala:159:20]
.io_cpu_redirect_ftq_idx (_core_io_ifu_redirect_ftq_idx), // @[tile.scala:159:20]
.io_cpu_redirect_ghist_old_history (_core_io_ifu_redirect_ghist_old_history), // @[tile.scala:159:20]
.io_cpu_redirect_ghist_current_saw_branch_not_taken (_core_io_ifu_redirect_ghist_current_saw_branch_not_taken), // @[tile.scala:159:20]
.io_cpu_redirect_ghist_new_saw_branch_not_taken (_core_io_ifu_redirect_ghist_new_saw_branch_not_taken), // @[tile.scala:159:20]
.io_cpu_redirect_ghist_new_saw_branch_taken (_core_io_ifu_redirect_ghist_new_saw_branch_taken), // @[tile.scala:159:20]
.io_cpu_redirect_ghist_ras_idx (_core_io_ifu_redirect_ghist_ras_idx), // @[tile.scala:159:20]
.io_cpu_commit_valid (_core_io_ifu_commit_valid), // @[tile.scala:159:20]
.io_cpu_commit_bits (_core_io_ifu_commit_bits), // @[tile.scala:159:20]
.io_cpu_flush_icache (_core_io_ifu_flush_icache), // @[tile.scala:159:20]
.io_cpu_perf_acquire (_frontend_io_cpu_perf_acquire),
.io_cpu_perf_tlbMiss (_frontend_io_cpu_perf_tlbMiss),
.io_ptw_req_ready (_ptw_io_requestor_1_req_ready), // @[tile.scala:237:20]
.io_ptw_req_valid (_frontend_io_ptw_req_valid),
.io_ptw_req_bits_bits_addr (_frontend_io_ptw_req_bits_bits_addr),
.io_ptw_req_bits_bits_need_gpa (_frontend_io_ptw_req_bits_bits_need_gpa),
.io_ptw_resp_valid (_ptw_io_requestor_1_resp_valid), // @[tile.scala:237:20]
.io_ptw_resp_bits_ae_ptw (_ptw_io_requestor_1_resp_bits_ae_ptw), // @[tile.scala:237:20]
.io_ptw_resp_bits_ae_final (_ptw_io_requestor_1_resp_bits_ae_final), // @[tile.scala:237:20]
.io_ptw_resp_bits_pf (_ptw_io_requestor_1_resp_bits_pf), // @[tile.scala:237:20]
.io_ptw_resp_bits_gf (_ptw_io_requestor_1_resp_bits_gf), // @[tile.scala:237:20]
.io_ptw_resp_bits_hr (_ptw_io_requestor_1_resp_bits_hr), // @[tile.scala:237:20]
.io_ptw_resp_bits_hw (_ptw_io_requestor_1_resp_bits_hw), // @[tile.scala:237:20]
.io_ptw_resp_bits_hx (_ptw_io_requestor_1_resp_bits_hx), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_reserved_for_future (_ptw_io_requestor_1_resp_bits_pte_reserved_for_future), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_ppn (_ptw_io_requestor_1_resp_bits_pte_ppn), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_reserved_for_software (_ptw_io_requestor_1_resp_bits_pte_reserved_for_software), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_d (_ptw_io_requestor_1_resp_bits_pte_d), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_a (_ptw_io_requestor_1_resp_bits_pte_a), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_g (_ptw_io_requestor_1_resp_bits_pte_g), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_u (_ptw_io_requestor_1_resp_bits_pte_u), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_x (_ptw_io_requestor_1_resp_bits_pte_x), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_w (_ptw_io_requestor_1_resp_bits_pte_w), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_r (_ptw_io_requestor_1_resp_bits_pte_r), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_v (_ptw_io_requestor_1_resp_bits_pte_v), // @[tile.scala:237:20]
.io_ptw_resp_bits_level (_ptw_io_requestor_1_resp_bits_level), // @[tile.scala:237:20]
.io_ptw_resp_bits_homogeneous (_ptw_io_requestor_1_resp_bits_homogeneous), // @[tile.scala:237:20]
.io_ptw_resp_bits_gpa_valid (_ptw_io_requestor_1_resp_bits_gpa_valid), // @[tile.scala:237:20]
.io_ptw_resp_bits_gpa_bits (_ptw_io_requestor_1_resp_bits_gpa_bits), // @[tile.scala:237:20]
.io_ptw_resp_bits_gpa_is_pte (_ptw_io_requestor_1_resp_bits_gpa_is_pte), // @[tile.scala:237:20]
.io_ptw_ptbr_mode (_ptw_io_requestor_1_ptbr_mode), // @[tile.scala:237:20]
.io_ptw_ptbr_ppn (_ptw_io_requestor_1_ptbr_ppn), // @[tile.scala:237:20]
.io_ptw_status_debug (_ptw_io_requestor_1_status_debug), // @[tile.scala:237:20]
.io_ptw_status_cease (_ptw_io_requestor_1_status_cease), // @[tile.scala:237:20]
.io_ptw_status_wfi (_ptw_io_requestor_1_status_wfi), // @[tile.scala:237:20]
.io_ptw_status_dprv (_ptw_io_requestor_1_status_dprv), // @[tile.scala:237:20]
.io_ptw_status_dv (_ptw_io_requestor_1_status_dv), // @[tile.scala:237:20]
.io_ptw_status_prv (_ptw_io_requestor_1_status_prv), // @[tile.scala:237:20]
.io_ptw_status_v (_ptw_io_requestor_1_status_v), // @[tile.scala:237:20]
.io_ptw_status_sd (_ptw_io_requestor_1_status_sd), // @[tile.scala:237:20]
.io_ptw_status_mpv (_ptw_io_requestor_1_status_mpv), // @[tile.scala:237:20]
.io_ptw_status_gva (_ptw_io_requestor_1_status_gva), // @[tile.scala:237:20]
.io_ptw_status_tsr (_ptw_io_requestor_1_status_tsr), // @[tile.scala:237:20]
.io_ptw_status_tw (_ptw_io_requestor_1_status_tw), // @[tile.scala:237:20]
.io_ptw_status_tvm (_ptw_io_requestor_1_status_tvm), // @[tile.scala:237:20]
.io_ptw_status_mxr (_ptw_io_requestor_1_status_mxr), // @[tile.scala:237:20]
.io_ptw_status_sum (_ptw_io_requestor_1_status_sum), // @[tile.scala:237:20]
.io_ptw_status_mprv (_ptw_io_requestor_1_status_mprv), // @[tile.scala:237:20]
.io_ptw_status_fs (_ptw_io_requestor_1_status_fs), // @[tile.scala:237:20]
.io_ptw_status_mpp (_ptw_io_requestor_1_status_mpp), // @[tile.scala:237:20]
.io_ptw_status_spp (_ptw_io_requestor_1_status_spp), // @[tile.scala:237:20]
.io_ptw_status_mpie (_ptw_io_requestor_1_status_mpie), // @[tile.scala:237:20]
.io_ptw_status_spie (_ptw_io_requestor_1_status_spie), // @[tile.scala:237:20]
.io_ptw_status_mie (_ptw_io_requestor_1_status_mie), // @[tile.scala:237:20]
.io_ptw_status_sie (_ptw_io_requestor_1_status_sie), // @[tile.scala:237:20]
.io_ptw_pmp_0_cfg_l (_ptw_io_requestor_1_pmp_0_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_0_cfg_a (_ptw_io_requestor_1_pmp_0_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_0_cfg_x (_ptw_io_requestor_1_pmp_0_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_0_cfg_w (_ptw_io_requestor_1_pmp_0_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_0_cfg_r (_ptw_io_requestor_1_pmp_0_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_0_addr (_ptw_io_requestor_1_pmp_0_addr), // @[tile.scala:237:20]
.io_ptw_pmp_0_mask (_ptw_io_requestor_1_pmp_0_mask), // @[tile.scala:237:20]
.io_ptw_pmp_1_cfg_l (_ptw_io_requestor_1_pmp_1_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_1_cfg_a (_ptw_io_requestor_1_pmp_1_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_1_cfg_x (_ptw_io_requestor_1_pmp_1_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_1_cfg_w (_ptw_io_requestor_1_pmp_1_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_1_cfg_r (_ptw_io_requestor_1_pmp_1_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_1_addr (_ptw_io_requestor_1_pmp_1_addr), // @[tile.scala:237:20]
.io_ptw_pmp_1_mask (_ptw_io_requestor_1_pmp_1_mask), // @[tile.scala:237:20]
.io_ptw_pmp_2_cfg_l (_ptw_io_requestor_1_pmp_2_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_2_cfg_a (_ptw_io_requestor_1_pmp_2_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_2_cfg_x (_ptw_io_requestor_1_pmp_2_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_2_cfg_w (_ptw_io_requestor_1_pmp_2_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_2_cfg_r (_ptw_io_requestor_1_pmp_2_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_2_addr (_ptw_io_requestor_1_pmp_2_addr), // @[tile.scala:237:20]
.io_ptw_pmp_2_mask (_ptw_io_requestor_1_pmp_2_mask), // @[tile.scala:237:20]
.io_ptw_pmp_3_cfg_l (_ptw_io_requestor_1_pmp_3_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_3_cfg_a (_ptw_io_requestor_1_pmp_3_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_3_cfg_x (_ptw_io_requestor_1_pmp_3_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_3_cfg_w (_ptw_io_requestor_1_pmp_3_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_3_cfg_r (_ptw_io_requestor_1_pmp_3_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_3_addr (_ptw_io_requestor_1_pmp_3_addr), // @[tile.scala:237:20]
.io_ptw_pmp_3_mask (_ptw_io_requestor_1_pmp_3_mask), // @[tile.scala:237:20]
.io_ptw_pmp_4_cfg_l (_ptw_io_requestor_1_pmp_4_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_4_cfg_a (_ptw_io_requestor_1_pmp_4_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_4_cfg_x (_ptw_io_requestor_1_pmp_4_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_4_cfg_w (_ptw_io_requestor_1_pmp_4_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_4_cfg_r (_ptw_io_requestor_1_pmp_4_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_4_addr (_ptw_io_requestor_1_pmp_4_addr), // @[tile.scala:237:20]
.io_ptw_pmp_4_mask (_ptw_io_requestor_1_pmp_4_mask), // @[tile.scala:237:20]
.io_ptw_pmp_5_cfg_l (_ptw_io_requestor_1_pmp_5_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_5_cfg_a (_ptw_io_requestor_1_pmp_5_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_5_cfg_x (_ptw_io_requestor_1_pmp_5_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_5_cfg_w (_ptw_io_requestor_1_pmp_5_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_5_cfg_r (_ptw_io_requestor_1_pmp_5_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_5_addr (_ptw_io_requestor_1_pmp_5_addr), // @[tile.scala:237:20]
.io_ptw_pmp_5_mask (_ptw_io_requestor_1_pmp_5_mask), // @[tile.scala:237:20]
.io_ptw_pmp_6_cfg_l (_ptw_io_requestor_1_pmp_6_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_6_cfg_a (_ptw_io_requestor_1_pmp_6_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_6_cfg_x (_ptw_io_requestor_1_pmp_6_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_6_cfg_w (_ptw_io_requestor_1_pmp_6_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_6_cfg_r (_ptw_io_requestor_1_pmp_6_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_6_addr (_ptw_io_requestor_1_pmp_6_addr), // @[tile.scala:237:20]
.io_ptw_pmp_6_mask (_ptw_io_requestor_1_pmp_6_mask), // @[tile.scala:237:20]
.io_ptw_pmp_7_cfg_l (_ptw_io_requestor_1_pmp_7_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_7_cfg_a (_ptw_io_requestor_1_pmp_7_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_7_cfg_x (_ptw_io_requestor_1_pmp_7_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_7_cfg_w (_ptw_io_requestor_1_pmp_7_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_7_cfg_r (_ptw_io_requestor_1_pmp_7_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_7_addr (_ptw_io_requestor_1_pmp_7_addr), // @[tile.scala:237:20]
.io_ptw_pmp_7_mask (_ptw_io_requestor_1_pmp_7_mask) // @[tile.scala:237:20]
); // @[tile.scala:138:28]
BoomCore_1 core ( // @[tile.scala:159:20]
.clock (clock),
.reset (reset),
.io_hartid (hartIdSinkNodeIn), // @[MixedNode.scala:551:17]
.io_interrupts_debug (intSinkNodeIn_0), // @[MixedNode.scala:551:17]
.io_interrupts_mtip (intSinkNodeIn_2), // @[MixedNode.scala:551:17]
.io_interrupts_msip (intSinkNodeIn_1), // @[MixedNode.scala:551:17]
.io_interrupts_meip (intSinkNodeIn_3), // @[MixedNode.scala:551:17]
.io_interrupts_seip (intSinkNodeIn_4), // @[MixedNode.scala:551:17]
.io_ifu_fetchpacket_ready (_core_io_ifu_fetchpacket_ready),
.io_ifu_fetchpacket_valid (_frontend_io_cpu_fetchpacket_valid), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_valid (_frontend_io_cpu_fetchpacket_bits_uops_0_valid), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_bits_inst (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_inst), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_bits_debug_inst (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_inst), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_bits_is_rvc (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_is_rvc), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_bits_debug_pc (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_pc), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_bits_is_sfb (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_is_sfb), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_bits_ftq_idx (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_ftq_idx), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_bits_edge_inst (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_edge_inst), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_bits_pc_lob (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_pc_lob), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_bits_taken (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_taken), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_bits_xcpt_pf_if (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_xcpt_pf_if), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_bits_xcpt_ae_if (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_xcpt_ae_if), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_bits_bp_debug_if (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_bp_debug_if), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_bits_bp_xcpt_if (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_bp_xcpt_if), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_bits_debug_fsrc (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_fsrc), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_valid (_frontend_io_cpu_fetchpacket_bits_uops_1_valid), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_bits_inst (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_inst), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_bits_debug_inst (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_inst), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_bits_is_rvc (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_is_rvc), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_bits_debug_pc (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_pc), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_bits_is_sfb (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_is_sfb), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_bits_ftq_idx (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_ftq_idx), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_bits_edge_inst (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_edge_inst), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_bits_pc_lob (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_pc_lob), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_bits_taken (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_taken), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_bits_xcpt_pf_if (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_xcpt_pf_if), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_bits_xcpt_ae_if (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_xcpt_ae_if), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_bits_bp_debug_if (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_bp_debug_if), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_bits_bp_xcpt_if (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_bp_xcpt_if), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_bits_debug_fsrc (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_fsrc), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_valid (_frontend_io_cpu_fetchpacket_bits_uops_2_valid), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_bits_inst (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_inst), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_bits_debug_inst (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_debug_inst), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_bits_is_rvc (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_is_rvc), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_bits_debug_pc (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_debug_pc), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_bits_is_sfb (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_is_sfb), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_bits_ftq_idx (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_ftq_idx), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_bits_edge_inst (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_edge_inst), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_bits_pc_lob (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_pc_lob), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_bits_taken (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_taken), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_bits_xcpt_pf_if (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_xcpt_pf_if), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_bits_xcpt_ae_if (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_xcpt_ae_if), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_bits_bp_debug_if (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_bp_debug_if), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_bits_bp_xcpt_if (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_bp_xcpt_if), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_bits_debug_fsrc (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_debug_fsrc), // @[tile.scala:138:28]
.io_ifu_get_pc_0_ftq_idx (_core_io_ifu_get_pc_0_ftq_idx),
.io_ifu_get_pc_0_entry_cfi_idx_valid (_frontend_io_cpu_get_pc_0_entry_cfi_idx_valid), // @[tile.scala:138:28]
.io_ifu_get_pc_0_entry_cfi_idx_bits (_frontend_io_cpu_get_pc_0_entry_cfi_idx_bits), // @[tile.scala:138:28]
.io_ifu_get_pc_0_entry_cfi_taken (_frontend_io_cpu_get_pc_0_entry_cfi_taken), // @[tile.scala:138:28]
.io_ifu_get_pc_0_entry_cfi_mispredicted (_frontend_io_cpu_get_pc_0_entry_cfi_mispredicted), // @[tile.scala:138:28]
.io_ifu_get_pc_0_entry_cfi_type (_frontend_io_cpu_get_pc_0_entry_cfi_type), // @[tile.scala:138:28]
.io_ifu_get_pc_0_entry_br_mask (_frontend_io_cpu_get_pc_0_entry_br_mask), // @[tile.scala:138:28]
.io_ifu_get_pc_0_entry_cfi_is_call (_frontend_io_cpu_get_pc_0_entry_cfi_is_call), // @[tile.scala:138:28]
.io_ifu_get_pc_0_entry_cfi_is_ret (_frontend_io_cpu_get_pc_0_entry_cfi_is_ret), // @[tile.scala:138:28]
.io_ifu_get_pc_0_entry_cfi_npc_plus4 (_frontend_io_cpu_get_pc_0_entry_cfi_npc_plus4), // @[tile.scala:138:28]
.io_ifu_get_pc_0_entry_ras_top (_frontend_io_cpu_get_pc_0_entry_ras_top), // @[tile.scala:138:28]
.io_ifu_get_pc_0_entry_ras_idx (_frontend_io_cpu_get_pc_0_entry_ras_idx), // @[tile.scala:138:28]
.io_ifu_get_pc_0_entry_start_bank (_frontend_io_cpu_get_pc_0_entry_start_bank), // @[tile.scala:138:28]
.io_ifu_get_pc_0_pc (_frontend_io_cpu_get_pc_0_pc), // @[tile.scala:138:28]
.io_ifu_get_pc_0_com_pc (_frontend_io_cpu_get_pc_0_com_pc), // @[tile.scala:138:28]
.io_ifu_get_pc_0_next_val (_frontend_io_cpu_get_pc_0_next_val), // @[tile.scala:138:28]
.io_ifu_get_pc_0_next_pc (_frontend_io_cpu_get_pc_0_next_pc), // @[tile.scala:138:28]
.io_ifu_get_pc_1_ftq_idx (_core_io_ifu_get_pc_1_ftq_idx),
.io_ifu_get_pc_1_entry_cfi_idx_valid (_frontend_io_cpu_get_pc_1_entry_cfi_idx_valid), // @[tile.scala:138:28]
.io_ifu_get_pc_1_entry_cfi_idx_bits (_frontend_io_cpu_get_pc_1_entry_cfi_idx_bits), // @[tile.scala:138:28]
.io_ifu_get_pc_1_entry_cfi_taken (_frontend_io_cpu_get_pc_1_entry_cfi_taken), // @[tile.scala:138:28]
.io_ifu_get_pc_1_entry_cfi_mispredicted (_frontend_io_cpu_get_pc_1_entry_cfi_mispredicted), // @[tile.scala:138:28]
.io_ifu_get_pc_1_entry_cfi_type (_frontend_io_cpu_get_pc_1_entry_cfi_type), // @[tile.scala:138:28]
.io_ifu_get_pc_1_entry_br_mask (_frontend_io_cpu_get_pc_1_entry_br_mask), // @[tile.scala:138:28]
.io_ifu_get_pc_1_entry_cfi_is_call (_frontend_io_cpu_get_pc_1_entry_cfi_is_call), // @[tile.scala:138:28]
.io_ifu_get_pc_1_entry_cfi_is_ret (_frontend_io_cpu_get_pc_1_entry_cfi_is_ret), // @[tile.scala:138:28]
.io_ifu_get_pc_1_entry_cfi_npc_plus4 (_frontend_io_cpu_get_pc_1_entry_cfi_npc_plus4), // @[tile.scala:138:28]
.io_ifu_get_pc_1_entry_ras_top (_frontend_io_cpu_get_pc_1_entry_ras_top), // @[tile.scala:138:28]
.io_ifu_get_pc_1_entry_ras_idx (_frontend_io_cpu_get_pc_1_entry_ras_idx), // @[tile.scala:138:28]
.io_ifu_get_pc_1_entry_start_bank (_frontend_io_cpu_get_pc_1_entry_start_bank), // @[tile.scala:138:28]
.io_ifu_get_pc_1_ghist_old_history (_frontend_io_cpu_get_pc_1_ghist_old_history), // @[tile.scala:138:28]
.io_ifu_get_pc_1_ghist_current_saw_branch_not_taken (_frontend_io_cpu_get_pc_1_ghist_current_saw_branch_not_taken), // @[tile.scala:138:28]
.io_ifu_get_pc_1_ghist_new_saw_branch_not_taken (_frontend_io_cpu_get_pc_1_ghist_new_saw_branch_not_taken), // @[tile.scala:138:28]
.io_ifu_get_pc_1_ghist_new_saw_branch_taken (_frontend_io_cpu_get_pc_1_ghist_new_saw_branch_taken), // @[tile.scala:138:28]
.io_ifu_get_pc_1_ghist_ras_idx (_frontend_io_cpu_get_pc_1_ghist_ras_idx), // @[tile.scala:138:28]
.io_ifu_get_pc_1_pc (_frontend_io_cpu_get_pc_1_pc), // @[tile.scala:138:28]
.io_ifu_get_pc_1_com_pc (_frontend_io_cpu_get_pc_1_com_pc), // @[tile.scala:138:28]
.io_ifu_get_pc_1_next_val (_frontend_io_cpu_get_pc_1_next_val), // @[tile.scala:138:28]
.io_ifu_get_pc_1_next_pc (_frontend_io_cpu_get_pc_1_next_pc), // @[tile.scala:138:28]
.io_ifu_debug_fetch_pc_0 (_frontend_io_cpu_debug_fetch_pc_0), // @[tile.scala:138:28]
.io_ifu_debug_fetch_pc_1 (_frontend_io_cpu_debug_fetch_pc_1), // @[tile.scala:138:28]
.io_ifu_debug_fetch_pc_2 (_frontend_io_cpu_debug_fetch_pc_2), // @[tile.scala:138:28]
.io_ifu_status_debug (_core_io_ifu_status_debug),
.io_ifu_status_cease (_core_io_ifu_status_cease),
.io_ifu_status_wfi (_core_io_ifu_status_wfi),
.io_ifu_status_dprv (_core_io_ifu_status_dprv),
.io_ifu_status_dv (_core_io_ifu_status_dv),
.io_ifu_status_prv (_core_io_ifu_status_prv),
.io_ifu_status_v (_core_io_ifu_status_v),
.io_ifu_status_sd (_core_io_ifu_status_sd),
.io_ifu_status_mpv (_core_io_ifu_status_mpv),
.io_ifu_status_gva (_core_io_ifu_status_gva),
.io_ifu_status_tsr (_core_io_ifu_status_tsr),
.io_ifu_status_tw (_core_io_ifu_status_tw),
.io_ifu_status_tvm (_core_io_ifu_status_tvm),
.io_ifu_status_mxr (_core_io_ifu_status_mxr),
.io_ifu_status_sum (_core_io_ifu_status_sum),
.io_ifu_status_mprv (_core_io_ifu_status_mprv),
.io_ifu_status_fs (_core_io_ifu_status_fs),
.io_ifu_status_mpp (_core_io_ifu_status_mpp),
.io_ifu_status_spp (_core_io_ifu_status_spp),
.io_ifu_status_mpie (_core_io_ifu_status_mpie),
.io_ifu_status_spie (_core_io_ifu_status_spie),
.io_ifu_status_mie (_core_io_ifu_status_mie),
.io_ifu_status_sie (_core_io_ifu_status_sie),
.io_ifu_sfence_valid (_core_io_ifu_sfence_valid),
.io_ifu_sfence_bits_rs1 (_core_io_ifu_sfence_bits_rs1),
.io_ifu_sfence_bits_rs2 (_core_io_ifu_sfence_bits_rs2),
.io_ifu_sfence_bits_addr (_core_io_ifu_sfence_bits_addr),
.io_ifu_sfence_bits_asid (_core_io_ifu_sfence_bits_asid),
.io_ifu_brupdate_b1_resolve_mask (_core_io_ifu_brupdate_b1_resolve_mask),
.io_ifu_brupdate_b1_mispredict_mask (_core_io_ifu_brupdate_b1_mispredict_mask),
.io_ifu_brupdate_b2_uop_uopc (_core_io_ifu_brupdate_b2_uop_uopc),
.io_ifu_brupdate_b2_uop_inst (_core_io_ifu_brupdate_b2_uop_inst),
.io_ifu_brupdate_b2_uop_debug_inst (_core_io_ifu_brupdate_b2_uop_debug_inst),
.io_ifu_brupdate_b2_uop_is_rvc (_core_io_ifu_brupdate_b2_uop_is_rvc),
.io_ifu_brupdate_b2_uop_debug_pc (_core_io_ifu_brupdate_b2_uop_debug_pc),
.io_ifu_brupdate_b2_uop_iq_type (_core_io_ifu_brupdate_b2_uop_iq_type),
.io_ifu_brupdate_b2_uop_fu_code (_core_io_ifu_brupdate_b2_uop_fu_code),
.io_ifu_brupdate_b2_uop_ctrl_br_type (_core_io_ifu_brupdate_b2_uop_ctrl_br_type),
.io_ifu_brupdate_b2_uop_ctrl_op1_sel (_core_io_ifu_brupdate_b2_uop_ctrl_op1_sel),
.io_ifu_brupdate_b2_uop_ctrl_op2_sel (_core_io_ifu_brupdate_b2_uop_ctrl_op2_sel),
.io_ifu_brupdate_b2_uop_ctrl_imm_sel (_core_io_ifu_brupdate_b2_uop_ctrl_imm_sel),
.io_ifu_brupdate_b2_uop_ctrl_op_fcn (_core_io_ifu_brupdate_b2_uop_ctrl_op_fcn),
.io_ifu_brupdate_b2_uop_ctrl_fcn_dw (_core_io_ifu_brupdate_b2_uop_ctrl_fcn_dw),
.io_ifu_brupdate_b2_uop_ctrl_csr_cmd (_core_io_ifu_brupdate_b2_uop_ctrl_csr_cmd),
.io_ifu_brupdate_b2_uop_ctrl_is_load (_core_io_ifu_brupdate_b2_uop_ctrl_is_load),
.io_ifu_brupdate_b2_uop_ctrl_is_sta (_core_io_ifu_brupdate_b2_uop_ctrl_is_sta),
.io_ifu_brupdate_b2_uop_ctrl_is_std (_core_io_ifu_brupdate_b2_uop_ctrl_is_std),
.io_ifu_brupdate_b2_uop_iw_state (_core_io_ifu_brupdate_b2_uop_iw_state),
.io_ifu_brupdate_b2_uop_iw_p1_poisoned (_core_io_ifu_brupdate_b2_uop_iw_p1_poisoned),
.io_ifu_brupdate_b2_uop_iw_p2_poisoned (_core_io_ifu_brupdate_b2_uop_iw_p2_poisoned),
.io_ifu_brupdate_b2_uop_is_br (_core_io_ifu_brupdate_b2_uop_is_br),
.io_ifu_brupdate_b2_uop_is_jalr (_core_io_ifu_brupdate_b2_uop_is_jalr),
.io_ifu_brupdate_b2_uop_is_jal (_core_io_ifu_brupdate_b2_uop_is_jal),
.io_ifu_brupdate_b2_uop_is_sfb (_core_io_ifu_brupdate_b2_uop_is_sfb),
.io_ifu_brupdate_b2_uop_br_mask (_core_io_ifu_brupdate_b2_uop_br_mask),
.io_ifu_brupdate_b2_uop_br_tag (_core_io_ifu_brupdate_b2_uop_br_tag),
.io_ifu_brupdate_b2_uop_ftq_idx (_core_io_ifu_brupdate_b2_uop_ftq_idx),
.io_ifu_brupdate_b2_uop_edge_inst (_core_io_ifu_brupdate_b2_uop_edge_inst),
.io_ifu_brupdate_b2_uop_pc_lob (_core_io_ifu_brupdate_b2_uop_pc_lob),
.io_ifu_brupdate_b2_uop_taken (_core_io_ifu_brupdate_b2_uop_taken),
.io_ifu_brupdate_b2_uop_imm_packed (_core_io_ifu_brupdate_b2_uop_imm_packed),
.io_ifu_brupdate_b2_uop_csr_addr (_core_io_ifu_brupdate_b2_uop_csr_addr),
.io_ifu_brupdate_b2_uop_rob_idx (_core_io_ifu_brupdate_b2_uop_rob_idx),
.io_ifu_brupdate_b2_uop_ldq_idx (_core_io_ifu_brupdate_b2_uop_ldq_idx),
.io_ifu_brupdate_b2_uop_stq_idx (_core_io_ifu_brupdate_b2_uop_stq_idx),
.io_ifu_brupdate_b2_uop_rxq_idx (_core_io_ifu_brupdate_b2_uop_rxq_idx),
.io_ifu_brupdate_b2_uop_pdst (_core_io_ifu_brupdate_b2_uop_pdst),
.io_ifu_brupdate_b2_uop_prs1 (_core_io_ifu_brupdate_b2_uop_prs1),
.io_ifu_brupdate_b2_uop_prs2 (_core_io_ifu_brupdate_b2_uop_prs2),
.io_ifu_brupdate_b2_uop_prs3 (_core_io_ifu_brupdate_b2_uop_prs3),
.io_ifu_brupdate_b2_uop_ppred (_core_io_ifu_brupdate_b2_uop_ppred),
.io_ifu_brupdate_b2_uop_prs1_busy (_core_io_ifu_brupdate_b2_uop_prs1_busy),
.io_ifu_brupdate_b2_uop_prs2_busy (_core_io_ifu_brupdate_b2_uop_prs2_busy),
.io_ifu_brupdate_b2_uop_prs3_busy (_core_io_ifu_brupdate_b2_uop_prs3_busy),
.io_ifu_brupdate_b2_uop_ppred_busy (_core_io_ifu_brupdate_b2_uop_ppred_busy),
.io_ifu_brupdate_b2_uop_stale_pdst (_core_io_ifu_brupdate_b2_uop_stale_pdst),
.io_ifu_brupdate_b2_uop_exception (_core_io_ifu_brupdate_b2_uop_exception),
.io_ifu_brupdate_b2_uop_exc_cause (_core_io_ifu_brupdate_b2_uop_exc_cause),
.io_ifu_brupdate_b2_uop_bypassable (_core_io_ifu_brupdate_b2_uop_bypassable),
.io_ifu_brupdate_b2_uop_mem_cmd (_core_io_ifu_brupdate_b2_uop_mem_cmd),
.io_ifu_brupdate_b2_uop_mem_size (_core_io_ifu_brupdate_b2_uop_mem_size),
.io_ifu_brupdate_b2_uop_mem_signed (_core_io_ifu_brupdate_b2_uop_mem_signed),
.io_ifu_brupdate_b2_uop_is_fence (_core_io_ifu_brupdate_b2_uop_is_fence),
.io_ifu_brupdate_b2_uop_is_fencei (_core_io_ifu_brupdate_b2_uop_is_fencei),
.io_ifu_brupdate_b2_uop_is_amo (_core_io_ifu_brupdate_b2_uop_is_amo),
.io_ifu_brupdate_b2_uop_uses_ldq (_core_io_ifu_brupdate_b2_uop_uses_ldq),
.io_ifu_brupdate_b2_uop_uses_stq (_core_io_ifu_brupdate_b2_uop_uses_stq),
.io_ifu_brupdate_b2_uop_is_sys_pc2epc (_core_io_ifu_brupdate_b2_uop_is_sys_pc2epc),
.io_ifu_brupdate_b2_uop_is_unique (_core_io_ifu_brupdate_b2_uop_is_unique),
.io_ifu_brupdate_b2_uop_flush_on_commit (_core_io_ifu_brupdate_b2_uop_flush_on_commit),
.io_ifu_brupdate_b2_uop_ldst_is_rs1 (_core_io_ifu_brupdate_b2_uop_ldst_is_rs1),
.io_ifu_brupdate_b2_uop_ldst (_core_io_ifu_brupdate_b2_uop_ldst),
.io_ifu_brupdate_b2_uop_lrs1 (_core_io_ifu_brupdate_b2_uop_lrs1),
.io_ifu_brupdate_b2_uop_lrs2 (_core_io_ifu_brupdate_b2_uop_lrs2),
.io_ifu_brupdate_b2_uop_lrs3 (_core_io_ifu_brupdate_b2_uop_lrs3),
.io_ifu_brupdate_b2_uop_ldst_val (_core_io_ifu_brupdate_b2_uop_ldst_val),
.io_ifu_brupdate_b2_uop_dst_rtype (_core_io_ifu_brupdate_b2_uop_dst_rtype),
.io_ifu_brupdate_b2_uop_lrs1_rtype (_core_io_ifu_brupdate_b2_uop_lrs1_rtype),
.io_ifu_brupdate_b2_uop_lrs2_rtype (_core_io_ifu_brupdate_b2_uop_lrs2_rtype),
.io_ifu_brupdate_b2_uop_frs3_en (_core_io_ifu_brupdate_b2_uop_frs3_en),
.io_ifu_brupdate_b2_uop_fp_val (_core_io_ifu_brupdate_b2_uop_fp_val),
.io_ifu_brupdate_b2_uop_fp_single (_core_io_ifu_brupdate_b2_uop_fp_single),
.io_ifu_brupdate_b2_uop_xcpt_pf_if (_core_io_ifu_brupdate_b2_uop_xcpt_pf_if),
.io_ifu_brupdate_b2_uop_xcpt_ae_if (_core_io_ifu_brupdate_b2_uop_xcpt_ae_if),
.io_ifu_brupdate_b2_uop_xcpt_ma_if (_core_io_ifu_brupdate_b2_uop_xcpt_ma_if),
.io_ifu_brupdate_b2_uop_bp_debug_if (_core_io_ifu_brupdate_b2_uop_bp_debug_if),
.io_ifu_brupdate_b2_uop_bp_xcpt_if (_core_io_ifu_brupdate_b2_uop_bp_xcpt_if),
.io_ifu_brupdate_b2_uop_debug_fsrc (_core_io_ifu_brupdate_b2_uop_debug_fsrc),
.io_ifu_brupdate_b2_uop_debug_tsrc (_core_io_ifu_brupdate_b2_uop_debug_tsrc),
.io_ifu_brupdate_b2_valid (_core_io_ifu_brupdate_b2_valid),
.io_ifu_brupdate_b2_mispredict (_core_io_ifu_brupdate_b2_mispredict),
.io_ifu_brupdate_b2_taken (_core_io_ifu_brupdate_b2_taken),
.io_ifu_brupdate_b2_cfi_type (_core_io_ifu_brupdate_b2_cfi_type),
.io_ifu_brupdate_b2_pc_sel (_core_io_ifu_brupdate_b2_pc_sel),
.io_ifu_brupdate_b2_jalr_target (_core_io_ifu_brupdate_b2_jalr_target),
.io_ifu_brupdate_b2_target_offset (_core_io_ifu_brupdate_b2_target_offset),
.io_ifu_redirect_flush (_core_io_ifu_redirect_flush),
.io_ifu_redirect_val (_core_io_ifu_redirect_val),
.io_ifu_redirect_pc (_core_io_ifu_redirect_pc),
.io_ifu_redirect_ftq_idx (_core_io_ifu_redirect_ftq_idx),
.io_ifu_redirect_ghist_old_history (_core_io_ifu_redirect_ghist_old_history),
.io_ifu_redirect_ghist_current_saw_branch_not_taken (_core_io_ifu_redirect_ghist_current_saw_branch_not_taken),
.io_ifu_redirect_ghist_new_saw_branch_not_taken (_core_io_ifu_redirect_ghist_new_saw_branch_not_taken),
.io_ifu_redirect_ghist_new_saw_branch_taken (_core_io_ifu_redirect_ghist_new_saw_branch_taken),
.io_ifu_redirect_ghist_ras_idx (_core_io_ifu_redirect_ghist_ras_idx),
.io_ifu_commit_valid (_core_io_ifu_commit_valid),
.io_ifu_commit_bits (_core_io_ifu_commit_bits),
.io_ifu_flush_icache (_core_io_ifu_flush_icache),
.io_ifu_perf_acquire (_frontend_io_cpu_perf_acquire), // @[tile.scala:138:28]
.io_ifu_perf_tlbMiss (_frontend_io_cpu_perf_tlbMiss), // @[tile.scala:138:28]
.io_ptw_ptbr_mode (_core_io_ptw_ptbr_mode),
.io_ptw_ptbr_ppn (_core_io_ptw_ptbr_ppn),
.io_ptw_sfence_valid (_core_io_ptw_sfence_valid),
.io_ptw_sfence_bits_rs1 (_core_io_ptw_sfence_bits_rs1),
.io_ptw_sfence_bits_rs2 (_core_io_ptw_sfence_bits_rs2),
.io_ptw_sfence_bits_addr (_core_io_ptw_sfence_bits_addr),
.io_ptw_sfence_bits_asid (_core_io_ptw_sfence_bits_asid),
.io_ptw_status_debug (_core_io_ptw_status_debug),
.io_ptw_status_cease (_core_io_ptw_status_cease),
.io_ptw_status_wfi (_core_io_ptw_status_wfi),
.io_ptw_status_dprv (_core_io_ptw_status_dprv),
.io_ptw_status_dv (_core_io_ptw_status_dv),
.io_ptw_status_prv (_core_io_ptw_status_prv),
.io_ptw_status_v (_core_io_ptw_status_v),
.io_ptw_status_sd (_core_io_ptw_status_sd),
.io_ptw_status_mpv (_core_io_ptw_status_mpv),
.io_ptw_status_gva (_core_io_ptw_status_gva),
.io_ptw_status_tsr (_core_io_ptw_status_tsr),
.io_ptw_status_tw (_core_io_ptw_status_tw),
.io_ptw_status_tvm (_core_io_ptw_status_tvm),
.io_ptw_status_mxr (_core_io_ptw_status_mxr),
.io_ptw_status_sum (_core_io_ptw_status_sum),
.io_ptw_status_mprv (_core_io_ptw_status_mprv),
.io_ptw_status_fs (_core_io_ptw_status_fs),
.io_ptw_status_mpp (_core_io_ptw_status_mpp),
.io_ptw_status_spp (_core_io_ptw_status_spp),
.io_ptw_status_mpie (_core_io_ptw_status_mpie),
.io_ptw_status_spie (_core_io_ptw_status_spie),
.io_ptw_status_mie (_core_io_ptw_status_mie),
.io_ptw_status_sie (_core_io_ptw_status_sie),
.io_ptw_pmp_0_cfg_l (_core_io_ptw_pmp_0_cfg_l),
.io_ptw_pmp_0_cfg_a (_core_io_ptw_pmp_0_cfg_a),
.io_ptw_pmp_0_cfg_x (_core_io_ptw_pmp_0_cfg_x),
.io_ptw_pmp_0_cfg_w (_core_io_ptw_pmp_0_cfg_w),
.io_ptw_pmp_0_cfg_r (_core_io_ptw_pmp_0_cfg_r),
.io_ptw_pmp_0_addr (_core_io_ptw_pmp_0_addr),
.io_ptw_pmp_0_mask (_core_io_ptw_pmp_0_mask),
.io_ptw_pmp_1_cfg_l (_core_io_ptw_pmp_1_cfg_l),
.io_ptw_pmp_1_cfg_a (_core_io_ptw_pmp_1_cfg_a),
.io_ptw_pmp_1_cfg_x (_core_io_ptw_pmp_1_cfg_x),
.io_ptw_pmp_1_cfg_w (_core_io_ptw_pmp_1_cfg_w),
.io_ptw_pmp_1_cfg_r (_core_io_ptw_pmp_1_cfg_r),
.io_ptw_pmp_1_addr (_core_io_ptw_pmp_1_addr),
.io_ptw_pmp_1_mask (_core_io_ptw_pmp_1_mask),
.io_ptw_pmp_2_cfg_l (_core_io_ptw_pmp_2_cfg_l),
.io_ptw_pmp_2_cfg_a (_core_io_ptw_pmp_2_cfg_a),
.io_ptw_pmp_2_cfg_x (_core_io_ptw_pmp_2_cfg_x),
.io_ptw_pmp_2_cfg_w (_core_io_ptw_pmp_2_cfg_w),
.io_ptw_pmp_2_cfg_r (_core_io_ptw_pmp_2_cfg_r),
.io_ptw_pmp_2_addr (_core_io_ptw_pmp_2_addr),
.io_ptw_pmp_2_mask (_core_io_ptw_pmp_2_mask),
.io_ptw_pmp_3_cfg_l (_core_io_ptw_pmp_3_cfg_l),
.io_ptw_pmp_3_cfg_a (_core_io_ptw_pmp_3_cfg_a),
.io_ptw_pmp_3_cfg_x (_core_io_ptw_pmp_3_cfg_x),
.io_ptw_pmp_3_cfg_w (_core_io_ptw_pmp_3_cfg_w),
.io_ptw_pmp_3_cfg_r (_core_io_ptw_pmp_3_cfg_r),
.io_ptw_pmp_3_addr (_core_io_ptw_pmp_3_addr),
.io_ptw_pmp_3_mask (_core_io_ptw_pmp_3_mask),
.io_ptw_pmp_4_cfg_l (_core_io_ptw_pmp_4_cfg_l),
.io_ptw_pmp_4_cfg_a (_core_io_ptw_pmp_4_cfg_a),
.io_ptw_pmp_4_cfg_x (_core_io_ptw_pmp_4_cfg_x),
.io_ptw_pmp_4_cfg_w (_core_io_ptw_pmp_4_cfg_w),
.io_ptw_pmp_4_cfg_r (_core_io_ptw_pmp_4_cfg_r),
.io_ptw_pmp_4_addr (_core_io_ptw_pmp_4_addr),
.io_ptw_pmp_4_mask (_core_io_ptw_pmp_4_mask),
.io_ptw_pmp_5_cfg_l (_core_io_ptw_pmp_5_cfg_l),
.io_ptw_pmp_5_cfg_a (_core_io_ptw_pmp_5_cfg_a),
.io_ptw_pmp_5_cfg_x (_core_io_ptw_pmp_5_cfg_x),
.io_ptw_pmp_5_cfg_w (_core_io_ptw_pmp_5_cfg_w),
.io_ptw_pmp_5_cfg_r (_core_io_ptw_pmp_5_cfg_r),
.io_ptw_pmp_5_addr (_core_io_ptw_pmp_5_addr),
.io_ptw_pmp_5_mask (_core_io_ptw_pmp_5_mask),
.io_ptw_pmp_6_cfg_l (_core_io_ptw_pmp_6_cfg_l),
.io_ptw_pmp_6_cfg_a (_core_io_ptw_pmp_6_cfg_a),
.io_ptw_pmp_6_cfg_x (_core_io_ptw_pmp_6_cfg_x),
.io_ptw_pmp_6_cfg_w (_core_io_ptw_pmp_6_cfg_w),
.io_ptw_pmp_6_cfg_r (_core_io_ptw_pmp_6_cfg_r),
.io_ptw_pmp_6_addr (_core_io_ptw_pmp_6_addr),
.io_ptw_pmp_6_mask (_core_io_ptw_pmp_6_mask),
.io_ptw_pmp_7_cfg_l (_core_io_ptw_pmp_7_cfg_l),
.io_ptw_pmp_7_cfg_a (_core_io_ptw_pmp_7_cfg_a),
.io_ptw_pmp_7_cfg_x (_core_io_ptw_pmp_7_cfg_x),
.io_ptw_pmp_7_cfg_w (_core_io_ptw_pmp_7_cfg_w),
.io_ptw_pmp_7_cfg_r (_core_io_ptw_pmp_7_cfg_r),
.io_ptw_pmp_7_addr (_core_io_ptw_pmp_7_addr),
.io_ptw_pmp_7_mask (_core_io_ptw_pmp_7_mask),
.io_ptw_perf_l2miss (_ptw_io_dpath_perf_l2miss), // @[tile.scala:237:20]
.io_ptw_perf_l2hit (_ptw_io_dpath_perf_l2hit), // @[tile.scala:237:20]
.io_ptw_perf_pte_miss (_ptw_io_dpath_perf_pte_miss), // @[tile.scala:237:20]
.io_ptw_perf_pte_hit (_ptw_io_dpath_perf_pte_hit), // @[tile.scala:237:20]
.io_ptw_clock_enabled (_ptw_io_dpath_clock_enabled), // @[tile.scala:237:20]
.io_lsu_exe_0_req_valid (_core_io_lsu_exe_0_req_valid),
.io_lsu_exe_0_req_bits_uop_uopc (_core_io_lsu_exe_0_req_bits_uop_uopc),
.io_lsu_exe_0_req_bits_uop_inst (_core_io_lsu_exe_0_req_bits_uop_inst),
.io_lsu_exe_0_req_bits_uop_debug_inst (_core_io_lsu_exe_0_req_bits_uop_debug_inst),
.io_lsu_exe_0_req_bits_uop_is_rvc (_core_io_lsu_exe_0_req_bits_uop_is_rvc),
.io_lsu_exe_0_req_bits_uop_debug_pc (_core_io_lsu_exe_0_req_bits_uop_debug_pc),
.io_lsu_exe_0_req_bits_uop_iq_type (_core_io_lsu_exe_0_req_bits_uop_iq_type),
.io_lsu_exe_0_req_bits_uop_fu_code (_core_io_lsu_exe_0_req_bits_uop_fu_code),
.io_lsu_exe_0_req_bits_uop_ctrl_br_type (_core_io_lsu_exe_0_req_bits_uop_ctrl_br_type),
.io_lsu_exe_0_req_bits_uop_ctrl_op1_sel (_core_io_lsu_exe_0_req_bits_uop_ctrl_op1_sel),
.io_lsu_exe_0_req_bits_uop_ctrl_op2_sel (_core_io_lsu_exe_0_req_bits_uop_ctrl_op2_sel),
.io_lsu_exe_0_req_bits_uop_ctrl_imm_sel (_core_io_lsu_exe_0_req_bits_uop_ctrl_imm_sel),
.io_lsu_exe_0_req_bits_uop_ctrl_op_fcn (_core_io_lsu_exe_0_req_bits_uop_ctrl_op_fcn),
.io_lsu_exe_0_req_bits_uop_ctrl_fcn_dw (_core_io_lsu_exe_0_req_bits_uop_ctrl_fcn_dw),
.io_lsu_exe_0_req_bits_uop_ctrl_csr_cmd (_core_io_lsu_exe_0_req_bits_uop_ctrl_csr_cmd),
.io_lsu_exe_0_req_bits_uop_ctrl_is_load (_core_io_lsu_exe_0_req_bits_uop_ctrl_is_load),
.io_lsu_exe_0_req_bits_uop_ctrl_is_sta (_core_io_lsu_exe_0_req_bits_uop_ctrl_is_sta),
.io_lsu_exe_0_req_bits_uop_ctrl_is_std (_core_io_lsu_exe_0_req_bits_uop_ctrl_is_std),
.io_lsu_exe_0_req_bits_uop_iw_state (_core_io_lsu_exe_0_req_bits_uop_iw_state),
.io_lsu_exe_0_req_bits_uop_iw_p1_poisoned (_core_io_lsu_exe_0_req_bits_uop_iw_p1_poisoned),
.io_lsu_exe_0_req_bits_uop_iw_p2_poisoned (_core_io_lsu_exe_0_req_bits_uop_iw_p2_poisoned),
.io_lsu_exe_0_req_bits_uop_is_br (_core_io_lsu_exe_0_req_bits_uop_is_br),
.io_lsu_exe_0_req_bits_uop_is_jalr (_core_io_lsu_exe_0_req_bits_uop_is_jalr),
.io_lsu_exe_0_req_bits_uop_is_jal (_core_io_lsu_exe_0_req_bits_uop_is_jal),
.io_lsu_exe_0_req_bits_uop_is_sfb (_core_io_lsu_exe_0_req_bits_uop_is_sfb),
.io_lsu_exe_0_req_bits_uop_br_mask (_core_io_lsu_exe_0_req_bits_uop_br_mask),
.io_lsu_exe_0_req_bits_uop_br_tag (_core_io_lsu_exe_0_req_bits_uop_br_tag),
.io_lsu_exe_0_req_bits_uop_ftq_idx (_core_io_lsu_exe_0_req_bits_uop_ftq_idx),
.io_lsu_exe_0_req_bits_uop_edge_inst (_core_io_lsu_exe_0_req_bits_uop_edge_inst),
.io_lsu_exe_0_req_bits_uop_pc_lob (_core_io_lsu_exe_0_req_bits_uop_pc_lob),
.io_lsu_exe_0_req_bits_uop_taken (_core_io_lsu_exe_0_req_bits_uop_taken),
.io_lsu_exe_0_req_bits_uop_imm_packed (_core_io_lsu_exe_0_req_bits_uop_imm_packed),
.io_lsu_exe_0_req_bits_uop_csr_addr (_core_io_lsu_exe_0_req_bits_uop_csr_addr),
.io_lsu_exe_0_req_bits_uop_rob_idx (_core_io_lsu_exe_0_req_bits_uop_rob_idx),
.io_lsu_exe_0_req_bits_uop_ldq_idx (_core_io_lsu_exe_0_req_bits_uop_ldq_idx),
.io_lsu_exe_0_req_bits_uop_stq_idx (_core_io_lsu_exe_0_req_bits_uop_stq_idx),
.io_lsu_exe_0_req_bits_uop_rxq_idx (_core_io_lsu_exe_0_req_bits_uop_rxq_idx),
.io_lsu_exe_0_req_bits_uop_pdst (_core_io_lsu_exe_0_req_bits_uop_pdst),
.io_lsu_exe_0_req_bits_uop_prs1 (_core_io_lsu_exe_0_req_bits_uop_prs1),
.io_lsu_exe_0_req_bits_uop_prs2 (_core_io_lsu_exe_0_req_bits_uop_prs2),
.io_lsu_exe_0_req_bits_uop_prs3 (_core_io_lsu_exe_0_req_bits_uop_prs3),
.io_lsu_exe_0_req_bits_uop_ppred (_core_io_lsu_exe_0_req_bits_uop_ppred),
.io_lsu_exe_0_req_bits_uop_prs1_busy (_core_io_lsu_exe_0_req_bits_uop_prs1_busy),
.io_lsu_exe_0_req_bits_uop_prs2_busy (_core_io_lsu_exe_0_req_bits_uop_prs2_busy),
.io_lsu_exe_0_req_bits_uop_prs3_busy (_core_io_lsu_exe_0_req_bits_uop_prs3_busy),
.io_lsu_exe_0_req_bits_uop_ppred_busy (_core_io_lsu_exe_0_req_bits_uop_ppred_busy),
.io_lsu_exe_0_req_bits_uop_stale_pdst (_core_io_lsu_exe_0_req_bits_uop_stale_pdst),
.io_lsu_exe_0_req_bits_uop_exception (_core_io_lsu_exe_0_req_bits_uop_exception),
.io_lsu_exe_0_req_bits_uop_exc_cause (_core_io_lsu_exe_0_req_bits_uop_exc_cause),
.io_lsu_exe_0_req_bits_uop_bypassable (_core_io_lsu_exe_0_req_bits_uop_bypassable),
.io_lsu_exe_0_req_bits_uop_mem_cmd (_core_io_lsu_exe_0_req_bits_uop_mem_cmd),
.io_lsu_exe_0_req_bits_uop_mem_size (_core_io_lsu_exe_0_req_bits_uop_mem_size),
.io_lsu_exe_0_req_bits_uop_mem_signed (_core_io_lsu_exe_0_req_bits_uop_mem_signed),
.io_lsu_exe_0_req_bits_uop_is_fence (_core_io_lsu_exe_0_req_bits_uop_is_fence),
.io_lsu_exe_0_req_bits_uop_is_fencei (_core_io_lsu_exe_0_req_bits_uop_is_fencei),
.io_lsu_exe_0_req_bits_uop_is_amo (_core_io_lsu_exe_0_req_bits_uop_is_amo),
.io_lsu_exe_0_req_bits_uop_uses_ldq (_core_io_lsu_exe_0_req_bits_uop_uses_ldq),
.io_lsu_exe_0_req_bits_uop_uses_stq (_core_io_lsu_exe_0_req_bits_uop_uses_stq),
.io_lsu_exe_0_req_bits_uop_is_sys_pc2epc (_core_io_lsu_exe_0_req_bits_uop_is_sys_pc2epc),
.io_lsu_exe_0_req_bits_uop_is_unique (_core_io_lsu_exe_0_req_bits_uop_is_unique),
.io_lsu_exe_0_req_bits_uop_flush_on_commit (_core_io_lsu_exe_0_req_bits_uop_flush_on_commit),
.io_lsu_exe_0_req_bits_uop_ldst_is_rs1 (_core_io_lsu_exe_0_req_bits_uop_ldst_is_rs1),
.io_lsu_exe_0_req_bits_uop_ldst (_core_io_lsu_exe_0_req_bits_uop_ldst),
.io_lsu_exe_0_req_bits_uop_lrs1 (_core_io_lsu_exe_0_req_bits_uop_lrs1),
.io_lsu_exe_0_req_bits_uop_lrs2 (_core_io_lsu_exe_0_req_bits_uop_lrs2),
.io_lsu_exe_0_req_bits_uop_lrs3 (_core_io_lsu_exe_0_req_bits_uop_lrs3),
.io_lsu_exe_0_req_bits_uop_ldst_val (_core_io_lsu_exe_0_req_bits_uop_ldst_val),
.io_lsu_exe_0_req_bits_uop_dst_rtype (_core_io_lsu_exe_0_req_bits_uop_dst_rtype),
.io_lsu_exe_0_req_bits_uop_lrs1_rtype (_core_io_lsu_exe_0_req_bits_uop_lrs1_rtype),
.io_lsu_exe_0_req_bits_uop_lrs2_rtype (_core_io_lsu_exe_0_req_bits_uop_lrs2_rtype),
.io_lsu_exe_0_req_bits_uop_frs3_en (_core_io_lsu_exe_0_req_bits_uop_frs3_en),
.io_lsu_exe_0_req_bits_uop_fp_val (_core_io_lsu_exe_0_req_bits_uop_fp_val),
.io_lsu_exe_0_req_bits_uop_fp_single (_core_io_lsu_exe_0_req_bits_uop_fp_single),
.io_lsu_exe_0_req_bits_uop_xcpt_pf_if (_core_io_lsu_exe_0_req_bits_uop_xcpt_pf_if),
.io_lsu_exe_0_req_bits_uop_xcpt_ae_if (_core_io_lsu_exe_0_req_bits_uop_xcpt_ae_if),
.io_lsu_exe_0_req_bits_uop_xcpt_ma_if (_core_io_lsu_exe_0_req_bits_uop_xcpt_ma_if),
.io_lsu_exe_0_req_bits_uop_bp_debug_if (_core_io_lsu_exe_0_req_bits_uop_bp_debug_if),
.io_lsu_exe_0_req_bits_uop_bp_xcpt_if (_core_io_lsu_exe_0_req_bits_uop_bp_xcpt_if),
.io_lsu_exe_0_req_bits_uop_debug_fsrc (_core_io_lsu_exe_0_req_bits_uop_debug_fsrc),
.io_lsu_exe_0_req_bits_uop_debug_tsrc (_core_io_lsu_exe_0_req_bits_uop_debug_tsrc),
.io_lsu_exe_0_req_bits_data (_core_io_lsu_exe_0_req_bits_data),
.io_lsu_exe_0_req_bits_addr (_core_io_lsu_exe_0_req_bits_addr),
.io_lsu_exe_0_req_bits_mxcpt_valid (_core_io_lsu_exe_0_req_bits_mxcpt_valid),
.io_lsu_exe_0_req_bits_mxcpt_bits (_core_io_lsu_exe_0_req_bits_mxcpt_bits),
.io_lsu_exe_0_req_bits_sfence_valid (_core_io_lsu_exe_0_req_bits_sfence_valid),
.io_lsu_exe_0_req_bits_sfence_bits_rs1 (_core_io_lsu_exe_0_req_bits_sfence_bits_rs1),
.io_lsu_exe_0_req_bits_sfence_bits_rs2 (_core_io_lsu_exe_0_req_bits_sfence_bits_rs2),
.io_lsu_exe_0_req_bits_sfence_bits_addr (_core_io_lsu_exe_0_req_bits_sfence_bits_addr),
.io_lsu_exe_0_req_bits_sfence_bits_asid (_core_io_lsu_exe_0_req_bits_sfence_bits_asid),
.io_lsu_exe_0_iresp_valid (_lsu_io_core_exe_0_iresp_valid), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_uopc (_lsu_io_core_exe_0_iresp_bits_uop_uopc), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_inst (_lsu_io_core_exe_0_iresp_bits_uop_inst), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_debug_inst (_lsu_io_core_exe_0_iresp_bits_uop_debug_inst), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_is_rvc (_lsu_io_core_exe_0_iresp_bits_uop_is_rvc), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_debug_pc (_lsu_io_core_exe_0_iresp_bits_uop_debug_pc), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_iq_type (_lsu_io_core_exe_0_iresp_bits_uop_iq_type), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_fu_code (_lsu_io_core_exe_0_iresp_bits_uop_fu_code), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ctrl_br_type (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_br_type), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ctrl_op1_sel (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_op1_sel), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ctrl_op2_sel (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_op2_sel), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ctrl_imm_sel (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_imm_sel), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ctrl_op_fcn (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_op_fcn), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ctrl_fcn_dw (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_fcn_dw), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ctrl_csr_cmd (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_csr_cmd), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ctrl_is_load (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_is_load), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ctrl_is_sta (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_is_sta), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ctrl_is_std (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_is_std), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_iw_state (_lsu_io_core_exe_0_iresp_bits_uop_iw_state), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_iw_p1_poisoned (_lsu_io_core_exe_0_iresp_bits_uop_iw_p1_poisoned), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_iw_p2_poisoned (_lsu_io_core_exe_0_iresp_bits_uop_iw_p2_poisoned), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_is_br (_lsu_io_core_exe_0_iresp_bits_uop_is_br), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_is_jalr (_lsu_io_core_exe_0_iresp_bits_uop_is_jalr), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_is_jal (_lsu_io_core_exe_0_iresp_bits_uop_is_jal), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_is_sfb (_lsu_io_core_exe_0_iresp_bits_uop_is_sfb), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_br_mask (_lsu_io_core_exe_0_iresp_bits_uop_br_mask), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_br_tag (_lsu_io_core_exe_0_iresp_bits_uop_br_tag), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ftq_idx (_lsu_io_core_exe_0_iresp_bits_uop_ftq_idx), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_edge_inst (_lsu_io_core_exe_0_iresp_bits_uop_edge_inst), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_pc_lob (_lsu_io_core_exe_0_iresp_bits_uop_pc_lob), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_taken (_lsu_io_core_exe_0_iresp_bits_uop_taken), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_imm_packed (_lsu_io_core_exe_0_iresp_bits_uop_imm_packed), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_csr_addr (_lsu_io_core_exe_0_iresp_bits_uop_csr_addr), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_rob_idx (_lsu_io_core_exe_0_iresp_bits_uop_rob_idx), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ldq_idx (_lsu_io_core_exe_0_iresp_bits_uop_ldq_idx), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_stq_idx (_lsu_io_core_exe_0_iresp_bits_uop_stq_idx), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_rxq_idx (_lsu_io_core_exe_0_iresp_bits_uop_rxq_idx), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_pdst (_lsu_io_core_exe_0_iresp_bits_uop_pdst), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_prs1 (_lsu_io_core_exe_0_iresp_bits_uop_prs1), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_prs2 (_lsu_io_core_exe_0_iresp_bits_uop_prs2), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_prs3 (_lsu_io_core_exe_0_iresp_bits_uop_prs3), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ppred (_lsu_io_core_exe_0_iresp_bits_uop_ppred), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_prs1_busy (_lsu_io_core_exe_0_iresp_bits_uop_prs1_busy), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_prs2_busy (_lsu_io_core_exe_0_iresp_bits_uop_prs2_busy), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_prs3_busy (_lsu_io_core_exe_0_iresp_bits_uop_prs3_busy), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ppred_busy (_lsu_io_core_exe_0_iresp_bits_uop_ppred_busy), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_stale_pdst (_lsu_io_core_exe_0_iresp_bits_uop_stale_pdst), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_exception (_lsu_io_core_exe_0_iresp_bits_uop_exception), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_exc_cause (_lsu_io_core_exe_0_iresp_bits_uop_exc_cause), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_bypassable (_lsu_io_core_exe_0_iresp_bits_uop_bypassable), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_mem_cmd (_lsu_io_core_exe_0_iresp_bits_uop_mem_cmd), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_mem_size (_lsu_io_core_exe_0_iresp_bits_uop_mem_size), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_mem_signed (_lsu_io_core_exe_0_iresp_bits_uop_mem_signed), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_is_fence (_lsu_io_core_exe_0_iresp_bits_uop_is_fence), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_is_fencei (_lsu_io_core_exe_0_iresp_bits_uop_is_fencei), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_is_amo (_lsu_io_core_exe_0_iresp_bits_uop_is_amo), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_uses_ldq (_lsu_io_core_exe_0_iresp_bits_uop_uses_ldq), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_uses_stq (_lsu_io_core_exe_0_iresp_bits_uop_uses_stq), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_is_sys_pc2epc (_lsu_io_core_exe_0_iresp_bits_uop_is_sys_pc2epc), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_is_unique (_lsu_io_core_exe_0_iresp_bits_uop_is_unique), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_flush_on_commit (_lsu_io_core_exe_0_iresp_bits_uop_flush_on_commit), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ldst_is_rs1 (_lsu_io_core_exe_0_iresp_bits_uop_ldst_is_rs1), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ldst (_lsu_io_core_exe_0_iresp_bits_uop_ldst), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_lrs1 (_lsu_io_core_exe_0_iresp_bits_uop_lrs1), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_lrs2 (_lsu_io_core_exe_0_iresp_bits_uop_lrs2), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_lrs3 (_lsu_io_core_exe_0_iresp_bits_uop_lrs3), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ldst_val (_lsu_io_core_exe_0_iresp_bits_uop_ldst_val), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_dst_rtype (_lsu_io_core_exe_0_iresp_bits_uop_dst_rtype), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_lrs1_rtype (_lsu_io_core_exe_0_iresp_bits_uop_lrs1_rtype), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_lrs2_rtype (_lsu_io_core_exe_0_iresp_bits_uop_lrs2_rtype), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_frs3_en (_lsu_io_core_exe_0_iresp_bits_uop_frs3_en), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_fp_val (_lsu_io_core_exe_0_iresp_bits_uop_fp_val), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_fp_single (_lsu_io_core_exe_0_iresp_bits_uop_fp_single), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_xcpt_pf_if (_lsu_io_core_exe_0_iresp_bits_uop_xcpt_pf_if), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_xcpt_ae_if (_lsu_io_core_exe_0_iresp_bits_uop_xcpt_ae_if), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_xcpt_ma_if (_lsu_io_core_exe_0_iresp_bits_uop_xcpt_ma_if), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_bp_debug_if (_lsu_io_core_exe_0_iresp_bits_uop_bp_debug_if), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_bp_xcpt_if (_lsu_io_core_exe_0_iresp_bits_uop_bp_xcpt_if), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_debug_fsrc (_lsu_io_core_exe_0_iresp_bits_uop_debug_fsrc), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_debug_tsrc (_lsu_io_core_exe_0_iresp_bits_uop_debug_tsrc), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_data (_lsu_io_core_exe_0_iresp_bits_data), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_valid (_lsu_io_core_exe_0_fresp_valid), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_uopc (_lsu_io_core_exe_0_fresp_bits_uop_uopc), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_inst (_lsu_io_core_exe_0_fresp_bits_uop_inst), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_debug_inst (_lsu_io_core_exe_0_fresp_bits_uop_debug_inst), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_is_rvc (_lsu_io_core_exe_0_fresp_bits_uop_is_rvc), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_debug_pc (_lsu_io_core_exe_0_fresp_bits_uop_debug_pc), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_iq_type (_lsu_io_core_exe_0_fresp_bits_uop_iq_type), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_fu_code (_lsu_io_core_exe_0_fresp_bits_uop_fu_code), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ctrl_br_type (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_br_type), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ctrl_op1_sel (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_op1_sel), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ctrl_op2_sel (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_op2_sel), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ctrl_imm_sel (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_imm_sel), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ctrl_op_fcn (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_op_fcn), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ctrl_fcn_dw (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_fcn_dw), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ctrl_csr_cmd (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_csr_cmd), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ctrl_is_load (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_is_load), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ctrl_is_sta (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_is_sta), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ctrl_is_std (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_is_std), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_iw_state (_lsu_io_core_exe_0_fresp_bits_uop_iw_state), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_iw_p1_poisoned (_lsu_io_core_exe_0_fresp_bits_uop_iw_p1_poisoned), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_iw_p2_poisoned (_lsu_io_core_exe_0_fresp_bits_uop_iw_p2_poisoned), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_is_br (_lsu_io_core_exe_0_fresp_bits_uop_is_br), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_is_jalr (_lsu_io_core_exe_0_fresp_bits_uop_is_jalr), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_is_jal (_lsu_io_core_exe_0_fresp_bits_uop_is_jal), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_is_sfb (_lsu_io_core_exe_0_fresp_bits_uop_is_sfb), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_br_mask (_lsu_io_core_exe_0_fresp_bits_uop_br_mask), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_br_tag (_lsu_io_core_exe_0_fresp_bits_uop_br_tag), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ftq_idx (_lsu_io_core_exe_0_fresp_bits_uop_ftq_idx), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_edge_inst (_lsu_io_core_exe_0_fresp_bits_uop_edge_inst), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_pc_lob (_lsu_io_core_exe_0_fresp_bits_uop_pc_lob), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_taken (_lsu_io_core_exe_0_fresp_bits_uop_taken), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_imm_packed (_lsu_io_core_exe_0_fresp_bits_uop_imm_packed), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_csr_addr (_lsu_io_core_exe_0_fresp_bits_uop_csr_addr), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_rob_idx (_lsu_io_core_exe_0_fresp_bits_uop_rob_idx), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ldq_idx (_lsu_io_core_exe_0_fresp_bits_uop_ldq_idx), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_stq_idx (_lsu_io_core_exe_0_fresp_bits_uop_stq_idx), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_rxq_idx (_lsu_io_core_exe_0_fresp_bits_uop_rxq_idx), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_pdst (_lsu_io_core_exe_0_fresp_bits_uop_pdst), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_prs1 (_lsu_io_core_exe_0_fresp_bits_uop_prs1), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_prs2 (_lsu_io_core_exe_0_fresp_bits_uop_prs2), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_prs3 (_lsu_io_core_exe_0_fresp_bits_uop_prs3), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ppred (_lsu_io_core_exe_0_fresp_bits_uop_ppred), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_prs1_busy (_lsu_io_core_exe_0_fresp_bits_uop_prs1_busy), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_prs2_busy (_lsu_io_core_exe_0_fresp_bits_uop_prs2_busy), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_prs3_busy (_lsu_io_core_exe_0_fresp_bits_uop_prs3_busy), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ppred_busy (_lsu_io_core_exe_0_fresp_bits_uop_ppred_busy), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_stale_pdst (_lsu_io_core_exe_0_fresp_bits_uop_stale_pdst), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_exception (_lsu_io_core_exe_0_fresp_bits_uop_exception), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_exc_cause (_lsu_io_core_exe_0_fresp_bits_uop_exc_cause), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_bypassable (_lsu_io_core_exe_0_fresp_bits_uop_bypassable), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_mem_cmd (_lsu_io_core_exe_0_fresp_bits_uop_mem_cmd), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_mem_size (_lsu_io_core_exe_0_fresp_bits_uop_mem_size), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_mem_signed (_lsu_io_core_exe_0_fresp_bits_uop_mem_signed), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_is_fence (_lsu_io_core_exe_0_fresp_bits_uop_is_fence), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_is_fencei (_lsu_io_core_exe_0_fresp_bits_uop_is_fencei), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_is_amo (_lsu_io_core_exe_0_fresp_bits_uop_is_amo), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_uses_ldq (_lsu_io_core_exe_0_fresp_bits_uop_uses_ldq), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_uses_stq (_lsu_io_core_exe_0_fresp_bits_uop_uses_stq), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_is_sys_pc2epc (_lsu_io_core_exe_0_fresp_bits_uop_is_sys_pc2epc), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_is_unique (_lsu_io_core_exe_0_fresp_bits_uop_is_unique), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_flush_on_commit (_lsu_io_core_exe_0_fresp_bits_uop_flush_on_commit), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ldst_is_rs1 (_lsu_io_core_exe_0_fresp_bits_uop_ldst_is_rs1), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ldst (_lsu_io_core_exe_0_fresp_bits_uop_ldst), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_lrs1 (_lsu_io_core_exe_0_fresp_bits_uop_lrs1), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_lrs2 (_lsu_io_core_exe_0_fresp_bits_uop_lrs2), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_lrs3 (_lsu_io_core_exe_0_fresp_bits_uop_lrs3), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ldst_val (_lsu_io_core_exe_0_fresp_bits_uop_ldst_val), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_dst_rtype (_lsu_io_core_exe_0_fresp_bits_uop_dst_rtype), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_lrs1_rtype (_lsu_io_core_exe_0_fresp_bits_uop_lrs1_rtype), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_lrs2_rtype (_lsu_io_core_exe_0_fresp_bits_uop_lrs2_rtype), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_frs3_en (_lsu_io_core_exe_0_fresp_bits_uop_frs3_en), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_fp_val (_lsu_io_core_exe_0_fresp_bits_uop_fp_val), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_fp_single (_lsu_io_core_exe_0_fresp_bits_uop_fp_single), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_xcpt_pf_if (_lsu_io_core_exe_0_fresp_bits_uop_xcpt_pf_if), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_xcpt_ae_if (_lsu_io_core_exe_0_fresp_bits_uop_xcpt_ae_if), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_xcpt_ma_if (_lsu_io_core_exe_0_fresp_bits_uop_xcpt_ma_if), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_bp_debug_if (_lsu_io_core_exe_0_fresp_bits_uop_bp_debug_if), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_bp_xcpt_if (_lsu_io_core_exe_0_fresp_bits_uop_bp_xcpt_if), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_debug_fsrc (_lsu_io_core_exe_0_fresp_bits_uop_debug_fsrc), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_debug_tsrc (_lsu_io_core_exe_0_fresp_bits_uop_debug_tsrc), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_data (_lsu_io_core_exe_0_fresp_bits_data), // @[tile.scala:160:20]
.io_lsu_dis_uops_0_valid (_core_io_lsu_dis_uops_0_valid),
.io_lsu_dis_uops_0_bits_uopc (_core_io_lsu_dis_uops_0_bits_uopc),
.io_lsu_dis_uops_0_bits_inst (_core_io_lsu_dis_uops_0_bits_inst),
.io_lsu_dis_uops_0_bits_debug_inst (_core_io_lsu_dis_uops_0_bits_debug_inst),
.io_lsu_dis_uops_0_bits_is_rvc (_core_io_lsu_dis_uops_0_bits_is_rvc),
.io_lsu_dis_uops_0_bits_debug_pc (_core_io_lsu_dis_uops_0_bits_debug_pc),
.io_lsu_dis_uops_0_bits_iq_type (_core_io_lsu_dis_uops_0_bits_iq_type),
.io_lsu_dis_uops_0_bits_fu_code (_core_io_lsu_dis_uops_0_bits_fu_code),
.io_lsu_dis_uops_0_bits_ctrl_br_type (_core_io_lsu_dis_uops_0_bits_ctrl_br_type),
.io_lsu_dis_uops_0_bits_ctrl_op1_sel (_core_io_lsu_dis_uops_0_bits_ctrl_op1_sel),
.io_lsu_dis_uops_0_bits_ctrl_op2_sel (_core_io_lsu_dis_uops_0_bits_ctrl_op2_sel),
.io_lsu_dis_uops_0_bits_ctrl_imm_sel (_core_io_lsu_dis_uops_0_bits_ctrl_imm_sel),
.io_lsu_dis_uops_0_bits_ctrl_op_fcn (_core_io_lsu_dis_uops_0_bits_ctrl_op_fcn),
.io_lsu_dis_uops_0_bits_ctrl_fcn_dw (_core_io_lsu_dis_uops_0_bits_ctrl_fcn_dw),
.io_lsu_dis_uops_0_bits_ctrl_csr_cmd (_core_io_lsu_dis_uops_0_bits_ctrl_csr_cmd),
.io_lsu_dis_uops_0_bits_ctrl_is_load (_core_io_lsu_dis_uops_0_bits_ctrl_is_load),
.io_lsu_dis_uops_0_bits_ctrl_is_sta (_core_io_lsu_dis_uops_0_bits_ctrl_is_sta),
.io_lsu_dis_uops_0_bits_ctrl_is_std (_core_io_lsu_dis_uops_0_bits_ctrl_is_std),
.io_lsu_dis_uops_0_bits_iw_state (_core_io_lsu_dis_uops_0_bits_iw_state),
.io_lsu_dis_uops_0_bits_iw_p1_poisoned (_core_io_lsu_dis_uops_0_bits_iw_p1_poisoned),
.io_lsu_dis_uops_0_bits_iw_p2_poisoned (_core_io_lsu_dis_uops_0_bits_iw_p2_poisoned),
.io_lsu_dis_uops_0_bits_is_br (_core_io_lsu_dis_uops_0_bits_is_br),
.io_lsu_dis_uops_0_bits_is_jalr (_core_io_lsu_dis_uops_0_bits_is_jalr),
.io_lsu_dis_uops_0_bits_is_jal (_core_io_lsu_dis_uops_0_bits_is_jal),
.io_lsu_dis_uops_0_bits_is_sfb (_core_io_lsu_dis_uops_0_bits_is_sfb),
.io_lsu_dis_uops_0_bits_br_mask (_core_io_lsu_dis_uops_0_bits_br_mask),
.io_lsu_dis_uops_0_bits_br_tag (_core_io_lsu_dis_uops_0_bits_br_tag),
.io_lsu_dis_uops_0_bits_ftq_idx (_core_io_lsu_dis_uops_0_bits_ftq_idx),
.io_lsu_dis_uops_0_bits_edge_inst (_core_io_lsu_dis_uops_0_bits_edge_inst),
.io_lsu_dis_uops_0_bits_pc_lob (_core_io_lsu_dis_uops_0_bits_pc_lob),
.io_lsu_dis_uops_0_bits_taken (_core_io_lsu_dis_uops_0_bits_taken),
.io_lsu_dis_uops_0_bits_imm_packed (_core_io_lsu_dis_uops_0_bits_imm_packed),
.io_lsu_dis_uops_0_bits_csr_addr (_core_io_lsu_dis_uops_0_bits_csr_addr),
.io_lsu_dis_uops_0_bits_rob_idx (_core_io_lsu_dis_uops_0_bits_rob_idx),
.io_lsu_dis_uops_0_bits_ldq_idx (_core_io_lsu_dis_uops_0_bits_ldq_idx),
.io_lsu_dis_uops_0_bits_stq_idx (_core_io_lsu_dis_uops_0_bits_stq_idx),
.io_lsu_dis_uops_0_bits_rxq_idx (_core_io_lsu_dis_uops_0_bits_rxq_idx),
.io_lsu_dis_uops_0_bits_pdst (_core_io_lsu_dis_uops_0_bits_pdst),
.io_lsu_dis_uops_0_bits_prs1 (_core_io_lsu_dis_uops_0_bits_prs1),
.io_lsu_dis_uops_0_bits_prs2 (_core_io_lsu_dis_uops_0_bits_prs2),
.io_lsu_dis_uops_0_bits_prs3 (_core_io_lsu_dis_uops_0_bits_prs3),
.io_lsu_dis_uops_0_bits_prs1_busy (_core_io_lsu_dis_uops_0_bits_prs1_busy),
.io_lsu_dis_uops_0_bits_prs2_busy (_core_io_lsu_dis_uops_0_bits_prs2_busy),
.io_lsu_dis_uops_0_bits_prs3_busy (_core_io_lsu_dis_uops_0_bits_prs3_busy),
.io_lsu_dis_uops_0_bits_stale_pdst (_core_io_lsu_dis_uops_0_bits_stale_pdst),
.io_lsu_dis_uops_0_bits_exception (_core_io_lsu_dis_uops_0_bits_exception),
.io_lsu_dis_uops_0_bits_exc_cause (_core_io_lsu_dis_uops_0_bits_exc_cause),
.io_lsu_dis_uops_0_bits_bypassable (_core_io_lsu_dis_uops_0_bits_bypassable),
.io_lsu_dis_uops_0_bits_mem_cmd (_core_io_lsu_dis_uops_0_bits_mem_cmd),
.io_lsu_dis_uops_0_bits_mem_size (_core_io_lsu_dis_uops_0_bits_mem_size),
.io_lsu_dis_uops_0_bits_mem_signed (_core_io_lsu_dis_uops_0_bits_mem_signed),
.io_lsu_dis_uops_0_bits_is_fence (_core_io_lsu_dis_uops_0_bits_is_fence),
.io_lsu_dis_uops_0_bits_is_fencei (_core_io_lsu_dis_uops_0_bits_is_fencei),
.io_lsu_dis_uops_0_bits_is_amo (_core_io_lsu_dis_uops_0_bits_is_amo),
.io_lsu_dis_uops_0_bits_uses_ldq (_core_io_lsu_dis_uops_0_bits_uses_ldq),
.io_lsu_dis_uops_0_bits_uses_stq (_core_io_lsu_dis_uops_0_bits_uses_stq),
.io_lsu_dis_uops_0_bits_is_sys_pc2epc (_core_io_lsu_dis_uops_0_bits_is_sys_pc2epc),
.io_lsu_dis_uops_0_bits_is_unique (_core_io_lsu_dis_uops_0_bits_is_unique),
.io_lsu_dis_uops_0_bits_flush_on_commit (_core_io_lsu_dis_uops_0_bits_flush_on_commit),
.io_lsu_dis_uops_0_bits_ldst_is_rs1 (_core_io_lsu_dis_uops_0_bits_ldst_is_rs1),
.io_lsu_dis_uops_0_bits_ldst (_core_io_lsu_dis_uops_0_bits_ldst),
.io_lsu_dis_uops_0_bits_lrs1 (_core_io_lsu_dis_uops_0_bits_lrs1),
.io_lsu_dis_uops_0_bits_lrs2 (_core_io_lsu_dis_uops_0_bits_lrs2),
.io_lsu_dis_uops_0_bits_lrs3 (_core_io_lsu_dis_uops_0_bits_lrs3),
.io_lsu_dis_uops_0_bits_ldst_val (_core_io_lsu_dis_uops_0_bits_ldst_val),
.io_lsu_dis_uops_0_bits_dst_rtype (_core_io_lsu_dis_uops_0_bits_dst_rtype),
.io_lsu_dis_uops_0_bits_lrs1_rtype (_core_io_lsu_dis_uops_0_bits_lrs1_rtype),
.io_lsu_dis_uops_0_bits_lrs2_rtype (_core_io_lsu_dis_uops_0_bits_lrs2_rtype),
.io_lsu_dis_uops_0_bits_frs3_en (_core_io_lsu_dis_uops_0_bits_frs3_en),
.io_lsu_dis_uops_0_bits_fp_val (_core_io_lsu_dis_uops_0_bits_fp_val),
.io_lsu_dis_uops_0_bits_fp_single (_core_io_lsu_dis_uops_0_bits_fp_single),
.io_lsu_dis_uops_0_bits_xcpt_pf_if (_core_io_lsu_dis_uops_0_bits_xcpt_pf_if),
.io_lsu_dis_uops_0_bits_xcpt_ae_if (_core_io_lsu_dis_uops_0_bits_xcpt_ae_if),
.io_lsu_dis_uops_0_bits_xcpt_ma_if (_core_io_lsu_dis_uops_0_bits_xcpt_ma_if),
.io_lsu_dis_uops_0_bits_bp_debug_if (_core_io_lsu_dis_uops_0_bits_bp_debug_if),
.io_lsu_dis_uops_0_bits_bp_xcpt_if (_core_io_lsu_dis_uops_0_bits_bp_xcpt_if),
.io_lsu_dis_uops_0_bits_debug_fsrc (_core_io_lsu_dis_uops_0_bits_debug_fsrc),
.io_lsu_dis_uops_0_bits_debug_tsrc (_core_io_lsu_dis_uops_0_bits_debug_tsrc),
.io_lsu_dis_uops_1_valid (_core_io_lsu_dis_uops_1_valid),
.io_lsu_dis_uops_1_bits_uopc (_core_io_lsu_dis_uops_1_bits_uopc),
.io_lsu_dis_uops_1_bits_inst (_core_io_lsu_dis_uops_1_bits_inst),
.io_lsu_dis_uops_1_bits_debug_inst (_core_io_lsu_dis_uops_1_bits_debug_inst),
.io_lsu_dis_uops_1_bits_is_rvc (_core_io_lsu_dis_uops_1_bits_is_rvc),
.io_lsu_dis_uops_1_bits_debug_pc (_core_io_lsu_dis_uops_1_bits_debug_pc),
.io_lsu_dis_uops_1_bits_iq_type (_core_io_lsu_dis_uops_1_bits_iq_type),
.io_lsu_dis_uops_1_bits_fu_code (_core_io_lsu_dis_uops_1_bits_fu_code),
.io_lsu_dis_uops_1_bits_ctrl_br_type (_core_io_lsu_dis_uops_1_bits_ctrl_br_type),
.io_lsu_dis_uops_1_bits_ctrl_op1_sel (_core_io_lsu_dis_uops_1_bits_ctrl_op1_sel),
.io_lsu_dis_uops_1_bits_ctrl_op2_sel (_core_io_lsu_dis_uops_1_bits_ctrl_op2_sel),
.io_lsu_dis_uops_1_bits_ctrl_imm_sel (_core_io_lsu_dis_uops_1_bits_ctrl_imm_sel),
.io_lsu_dis_uops_1_bits_ctrl_op_fcn (_core_io_lsu_dis_uops_1_bits_ctrl_op_fcn),
.io_lsu_dis_uops_1_bits_ctrl_fcn_dw (_core_io_lsu_dis_uops_1_bits_ctrl_fcn_dw),
.io_lsu_dis_uops_1_bits_ctrl_csr_cmd (_core_io_lsu_dis_uops_1_bits_ctrl_csr_cmd),
.io_lsu_dis_uops_1_bits_ctrl_is_load (_core_io_lsu_dis_uops_1_bits_ctrl_is_load),
.io_lsu_dis_uops_1_bits_ctrl_is_sta (_core_io_lsu_dis_uops_1_bits_ctrl_is_sta),
.io_lsu_dis_uops_1_bits_ctrl_is_std (_core_io_lsu_dis_uops_1_bits_ctrl_is_std),
.io_lsu_dis_uops_1_bits_iw_state (_core_io_lsu_dis_uops_1_bits_iw_state),
.io_lsu_dis_uops_1_bits_iw_p1_poisoned (_core_io_lsu_dis_uops_1_bits_iw_p1_poisoned),
.io_lsu_dis_uops_1_bits_iw_p2_poisoned (_core_io_lsu_dis_uops_1_bits_iw_p2_poisoned),
.io_lsu_dis_uops_1_bits_is_br (_core_io_lsu_dis_uops_1_bits_is_br),
.io_lsu_dis_uops_1_bits_is_jalr (_core_io_lsu_dis_uops_1_bits_is_jalr),
.io_lsu_dis_uops_1_bits_is_jal (_core_io_lsu_dis_uops_1_bits_is_jal),
.io_lsu_dis_uops_1_bits_is_sfb (_core_io_lsu_dis_uops_1_bits_is_sfb),
.io_lsu_dis_uops_1_bits_br_mask (_core_io_lsu_dis_uops_1_bits_br_mask),
.io_lsu_dis_uops_1_bits_br_tag (_core_io_lsu_dis_uops_1_bits_br_tag),
.io_lsu_dis_uops_1_bits_ftq_idx (_core_io_lsu_dis_uops_1_bits_ftq_idx),
.io_lsu_dis_uops_1_bits_edge_inst (_core_io_lsu_dis_uops_1_bits_edge_inst),
.io_lsu_dis_uops_1_bits_pc_lob (_core_io_lsu_dis_uops_1_bits_pc_lob),
.io_lsu_dis_uops_1_bits_taken (_core_io_lsu_dis_uops_1_bits_taken),
.io_lsu_dis_uops_1_bits_imm_packed (_core_io_lsu_dis_uops_1_bits_imm_packed),
.io_lsu_dis_uops_1_bits_csr_addr (_core_io_lsu_dis_uops_1_bits_csr_addr),
.io_lsu_dis_uops_1_bits_rob_idx (_core_io_lsu_dis_uops_1_bits_rob_idx),
.io_lsu_dis_uops_1_bits_ldq_idx (_core_io_lsu_dis_uops_1_bits_ldq_idx),
.io_lsu_dis_uops_1_bits_stq_idx (_core_io_lsu_dis_uops_1_bits_stq_idx),
.io_lsu_dis_uops_1_bits_rxq_idx (_core_io_lsu_dis_uops_1_bits_rxq_idx),
.io_lsu_dis_uops_1_bits_pdst (_core_io_lsu_dis_uops_1_bits_pdst),
.io_lsu_dis_uops_1_bits_prs1 (_core_io_lsu_dis_uops_1_bits_prs1),
.io_lsu_dis_uops_1_bits_prs2 (_core_io_lsu_dis_uops_1_bits_prs2),
.io_lsu_dis_uops_1_bits_prs3 (_core_io_lsu_dis_uops_1_bits_prs3),
.io_lsu_dis_uops_1_bits_prs1_busy (_core_io_lsu_dis_uops_1_bits_prs1_busy),
.io_lsu_dis_uops_1_bits_prs2_busy (_core_io_lsu_dis_uops_1_bits_prs2_busy),
.io_lsu_dis_uops_1_bits_prs3_busy (_core_io_lsu_dis_uops_1_bits_prs3_busy),
.io_lsu_dis_uops_1_bits_stale_pdst (_core_io_lsu_dis_uops_1_bits_stale_pdst),
.io_lsu_dis_uops_1_bits_exception (_core_io_lsu_dis_uops_1_bits_exception),
.io_lsu_dis_uops_1_bits_exc_cause (_core_io_lsu_dis_uops_1_bits_exc_cause),
.io_lsu_dis_uops_1_bits_bypassable (_core_io_lsu_dis_uops_1_bits_bypassable),
.io_lsu_dis_uops_1_bits_mem_cmd (_core_io_lsu_dis_uops_1_bits_mem_cmd),
.io_lsu_dis_uops_1_bits_mem_size (_core_io_lsu_dis_uops_1_bits_mem_size),
.io_lsu_dis_uops_1_bits_mem_signed (_core_io_lsu_dis_uops_1_bits_mem_signed),
.io_lsu_dis_uops_1_bits_is_fence (_core_io_lsu_dis_uops_1_bits_is_fence),
.io_lsu_dis_uops_1_bits_is_fencei (_core_io_lsu_dis_uops_1_bits_is_fencei),
.io_lsu_dis_uops_1_bits_is_amo (_core_io_lsu_dis_uops_1_bits_is_amo),
.io_lsu_dis_uops_1_bits_uses_ldq (_core_io_lsu_dis_uops_1_bits_uses_ldq),
.io_lsu_dis_uops_1_bits_uses_stq (_core_io_lsu_dis_uops_1_bits_uses_stq),
.io_lsu_dis_uops_1_bits_is_sys_pc2epc (_core_io_lsu_dis_uops_1_bits_is_sys_pc2epc),
.io_lsu_dis_uops_1_bits_is_unique (_core_io_lsu_dis_uops_1_bits_is_unique),
.io_lsu_dis_uops_1_bits_flush_on_commit (_core_io_lsu_dis_uops_1_bits_flush_on_commit),
.io_lsu_dis_uops_1_bits_ldst_is_rs1 (_core_io_lsu_dis_uops_1_bits_ldst_is_rs1),
.io_lsu_dis_uops_1_bits_ldst (_core_io_lsu_dis_uops_1_bits_ldst),
.io_lsu_dis_uops_1_bits_lrs1 (_core_io_lsu_dis_uops_1_bits_lrs1),
.io_lsu_dis_uops_1_bits_lrs2 (_core_io_lsu_dis_uops_1_bits_lrs2),
.io_lsu_dis_uops_1_bits_lrs3 (_core_io_lsu_dis_uops_1_bits_lrs3),
.io_lsu_dis_uops_1_bits_ldst_val (_core_io_lsu_dis_uops_1_bits_ldst_val),
.io_lsu_dis_uops_1_bits_dst_rtype (_core_io_lsu_dis_uops_1_bits_dst_rtype),
.io_lsu_dis_uops_1_bits_lrs1_rtype (_core_io_lsu_dis_uops_1_bits_lrs1_rtype),
.io_lsu_dis_uops_1_bits_lrs2_rtype (_core_io_lsu_dis_uops_1_bits_lrs2_rtype),
.io_lsu_dis_uops_1_bits_frs3_en (_core_io_lsu_dis_uops_1_bits_frs3_en),
.io_lsu_dis_uops_1_bits_fp_val (_core_io_lsu_dis_uops_1_bits_fp_val),
.io_lsu_dis_uops_1_bits_fp_single (_core_io_lsu_dis_uops_1_bits_fp_single),
.io_lsu_dis_uops_1_bits_xcpt_pf_if (_core_io_lsu_dis_uops_1_bits_xcpt_pf_if),
.io_lsu_dis_uops_1_bits_xcpt_ae_if (_core_io_lsu_dis_uops_1_bits_xcpt_ae_if),
.io_lsu_dis_uops_1_bits_xcpt_ma_if (_core_io_lsu_dis_uops_1_bits_xcpt_ma_if),
.io_lsu_dis_uops_1_bits_bp_debug_if (_core_io_lsu_dis_uops_1_bits_bp_debug_if),
.io_lsu_dis_uops_1_bits_bp_xcpt_if (_core_io_lsu_dis_uops_1_bits_bp_xcpt_if),
.io_lsu_dis_uops_1_bits_debug_fsrc (_core_io_lsu_dis_uops_1_bits_debug_fsrc),
.io_lsu_dis_uops_1_bits_debug_tsrc (_core_io_lsu_dis_uops_1_bits_debug_tsrc),
.io_lsu_dis_uops_2_valid (_core_io_lsu_dis_uops_2_valid),
.io_lsu_dis_uops_2_bits_uopc (_core_io_lsu_dis_uops_2_bits_uopc),
.io_lsu_dis_uops_2_bits_inst (_core_io_lsu_dis_uops_2_bits_inst),
.io_lsu_dis_uops_2_bits_debug_inst (_core_io_lsu_dis_uops_2_bits_debug_inst),
.io_lsu_dis_uops_2_bits_is_rvc (_core_io_lsu_dis_uops_2_bits_is_rvc),
.io_lsu_dis_uops_2_bits_debug_pc (_core_io_lsu_dis_uops_2_bits_debug_pc),
.io_lsu_dis_uops_2_bits_iq_type (_core_io_lsu_dis_uops_2_bits_iq_type),
.io_lsu_dis_uops_2_bits_fu_code (_core_io_lsu_dis_uops_2_bits_fu_code),
.io_lsu_dis_uops_2_bits_ctrl_br_type (_core_io_lsu_dis_uops_2_bits_ctrl_br_type),
.io_lsu_dis_uops_2_bits_ctrl_op1_sel (_core_io_lsu_dis_uops_2_bits_ctrl_op1_sel),
.io_lsu_dis_uops_2_bits_ctrl_op2_sel (_core_io_lsu_dis_uops_2_bits_ctrl_op2_sel),
.io_lsu_dis_uops_2_bits_ctrl_imm_sel (_core_io_lsu_dis_uops_2_bits_ctrl_imm_sel),
.io_lsu_dis_uops_2_bits_ctrl_op_fcn (_core_io_lsu_dis_uops_2_bits_ctrl_op_fcn),
.io_lsu_dis_uops_2_bits_ctrl_fcn_dw (_core_io_lsu_dis_uops_2_bits_ctrl_fcn_dw),
.io_lsu_dis_uops_2_bits_ctrl_csr_cmd (_core_io_lsu_dis_uops_2_bits_ctrl_csr_cmd),
.io_lsu_dis_uops_2_bits_ctrl_is_load (_core_io_lsu_dis_uops_2_bits_ctrl_is_load),
.io_lsu_dis_uops_2_bits_ctrl_is_sta (_core_io_lsu_dis_uops_2_bits_ctrl_is_sta),
.io_lsu_dis_uops_2_bits_ctrl_is_std (_core_io_lsu_dis_uops_2_bits_ctrl_is_std),
.io_lsu_dis_uops_2_bits_iw_state (_core_io_lsu_dis_uops_2_bits_iw_state),
.io_lsu_dis_uops_2_bits_iw_p1_poisoned (_core_io_lsu_dis_uops_2_bits_iw_p1_poisoned),
.io_lsu_dis_uops_2_bits_iw_p2_poisoned (_core_io_lsu_dis_uops_2_bits_iw_p2_poisoned),
.io_lsu_dis_uops_2_bits_is_br (_core_io_lsu_dis_uops_2_bits_is_br),
.io_lsu_dis_uops_2_bits_is_jalr (_core_io_lsu_dis_uops_2_bits_is_jalr),
.io_lsu_dis_uops_2_bits_is_jal (_core_io_lsu_dis_uops_2_bits_is_jal),
.io_lsu_dis_uops_2_bits_is_sfb (_core_io_lsu_dis_uops_2_bits_is_sfb),
.io_lsu_dis_uops_2_bits_br_mask (_core_io_lsu_dis_uops_2_bits_br_mask),
.io_lsu_dis_uops_2_bits_br_tag (_core_io_lsu_dis_uops_2_bits_br_tag),
.io_lsu_dis_uops_2_bits_ftq_idx (_core_io_lsu_dis_uops_2_bits_ftq_idx),
.io_lsu_dis_uops_2_bits_edge_inst (_core_io_lsu_dis_uops_2_bits_edge_inst),
.io_lsu_dis_uops_2_bits_pc_lob (_core_io_lsu_dis_uops_2_bits_pc_lob),
.io_lsu_dis_uops_2_bits_taken (_core_io_lsu_dis_uops_2_bits_taken),
.io_lsu_dis_uops_2_bits_imm_packed (_core_io_lsu_dis_uops_2_bits_imm_packed),
.io_lsu_dis_uops_2_bits_csr_addr (_core_io_lsu_dis_uops_2_bits_csr_addr),
.io_lsu_dis_uops_2_bits_rob_idx (_core_io_lsu_dis_uops_2_bits_rob_idx),
.io_lsu_dis_uops_2_bits_ldq_idx (_core_io_lsu_dis_uops_2_bits_ldq_idx),
.io_lsu_dis_uops_2_bits_stq_idx (_core_io_lsu_dis_uops_2_bits_stq_idx),
.io_lsu_dis_uops_2_bits_rxq_idx (_core_io_lsu_dis_uops_2_bits_rxq_idx),
.io_lsu_dis_uops_2_bits_pdst (_core_io_lsu_dis_uops_2_bits_pdst),
.io_lsu_dis_uops_2_bits_prs1 (_core_io_lsu_dis_uops_2_bits_prs1),
.io_lsu_dis_uops_2_bits_prs2 (_core_io_lsu_dis_uops_2_bits_prs2),
.io_lsu_dis_uops_2_bits_prs3 (_core_io_lsu_dis_uops_2_bits_prs3),
.io_lsu_dis_uops_2_bits_prs1_busy (_core_io_lsu_dis_uops_2_bits_prs1_busy),
.io_lsu_dis_uops_2_bits_prs2_busy (_core_io_lsu_dis_uops_2_bits_prs2_busy),
.io_lsu_dis_uops_2_bits_prs3_busy (_core_io_lsu_dis_uops_2_bits_prs3_busy),
.io_lsu_dis_uops_2_bits_stale_pdst (_core_io_lsu_dis_uops_2_bits_stale_pdst),
.io_lsu_dis_uops_2_bits_exception (_core_io_lsu_dis_uops_2_bits_exception),
.io_lsu_dis_uops_2_bits_exc_cause (_core_io_lsu_dis_uops_2_bits_exc_cause),
.io_lsu_dis_uops_2_bits_bypassable (_core_io_lsu_dis_uops_2_bits_bypassable),
.io_lsu_dis_uops_2_bits_mem_cmd (_core_io_lsu_dis_uops_2_bits_mem_cmd),
.io_lsu_dis_uops_2_bits_mem_size (_core_io_lsu_dis_uops_2_bits_mem_size),
.io_lsu_dis_uops_2_bits_mem_signed (_core_io_lsu_dis_uops_2_bits_mem_signed),
.io_lsu_dis_uops_2_bits_is_fence (_core_io_lsu_dis_uops_2_bits_is_fence),
.io_lsu_dis_uops_2_bits_is_fencei (_core_io_lsu_dis_uops_2_bits_is_fencei),
.io_lsu_dis_uops_2_bits_is_amo (_core_io_lsu_dis_uops_2_bits_is_amo),
.io_lsu_dis_uops_2_bits_uses_ldq (_core_io_lsu_dis_uops_2_bits_uses_ldq),
.io_lsu_dis_uops_2_bits_uses_stq (_core_io_lsu_dis_uops_2_bits_uses_stq),
.io_lsu_dis_uops_2_bits_is_sys_pc2epc (_core_io_lsu_dis_uops_2_bits_is_sys_pc2epc),
.io_lsu_dis_uops_2_bits_is_unique (_core_io_lsu_dis_uops_2_bits_is_unique),
.io_lsu_dis_uops_2_bits_flush_on_commit (_core_io_lsu_dis_uops_2_bits_flush_on_commit),
.io_lsu_dis_uops_2_bits_ldst_is_rs1 (_core_io_lsu_dis_uops_2_bits_ldst_is_rs1),
.io_lsu_dis_uops_2_bits_ldst (_core_io_lsu_dis_uops_2_bits_ldst),
.io_lsu_dis_uops_2_bits_lrs1 (_core_io_lsu_dis_uops_2_bits_lrs1),
.io_lsu_dis_uops_2_bits_lrs2 (_core_io_lsu_dis_uops_2_bits_lrs2),
.io_lsu_dis_uops_2_bits_lrs3 (_core_io_lsu_dis_uops_2_bits_lrs3),
.io_lsu_dis_uops_2_bits_ldst_val (_core_io_lsu_dis_uops_2_bits_ldst_val),
.io_lsu_dis_uops_2_bits_dst_rtype (_core_io_lsu_dis_uops_2_bits_dst_rtype),
.io_lsu_dis_uops_2_bits_lrs1_rtype (_core_io_lsu_dis_uops_2_bits_lrs1_rtype),
.io_lsu_dis_uops_2_bits_lrs2_rtype (_core_io_lsu_dis_uops_2_bits_lrs2_rtype),
.io_lsu_dis_uops_2_bits_frs3_en (_core_io_lsu_dis_uops_2_bits_frs3_en),
.io_lsu_dis_uops_2_bits_fp_val (_core_io_lsu_dis_uops_2_bits_fp_val),
.io_lsu_dis_uops_2_bits_fp_single (_core_io_lsu_dis_uops_2_bits_fp_single),
.io_lsu_dis_uops_2_bits_xcpt_pf_if (_core_io_lsu_dis_uops_2_bits_xcpt_pf_if),
.io_lsu_dis_uops_2_bits_xcpt_ae_if (_core_io_lsu_dis_uops_2_bits_xcpt_ae_if),
.io_lsu_dis_uops_2_bits_xcpt_ma_if (_core_io_lsu_dis_uops_2_bits_xcpt_ma_if),
.io_lsu_dis_uops_2_bits_bp_debug_if (_core_io_lsu_dis_uops_2_bits_bp_debug_if),
.io_lsu_dis_uops_2_bits_bp_xcpt_if (_core_io_lsu_dis_uops_2_bits_bp_xcpt_if),
.io_lsu_dis_uops_2_bits_debug_fsrc (_core_io_lsu_dis_uops_2_bits_debug_fsrc),
.io_lsu_dis_uops_2_bits_debug_tsrc (_core_io_lsu_dis_uops_2_bits_debug_tsrc),
.io_lsu_dis_ldq_idx_0 (_lsu_io_core_dis_ldq_idx_0), // @[tile.scala:160:20]
.io_lsu_dis_ldq_idx_1 (_lsu_io_core_dis_ldq_idx_1), // @[tile.scala:160:20]
.io_lsu_dis_ldq_idx_2 (_lsu_io_core_dis_ldq_idx_2), // @[tile.scala:160:20]
.io_lsu_dis_stq_idx_0 (_lsu_io_core_dis_stq_idx_0), // @[tile.scala:160:20]
.io_lsu_dis_stq_idx_1 (_lsu_io_core_dis_stq_idx_1), // @[tile.scala:160:20]
.io_lsu_dis_stq_idx_2 (_lsu_io_core_dis_stq_idx_2), // @[tile.scala:160:20]
.io_lsu_ldq_full_0 (_lsu_io_core_ldq_full_0), // @[tile.scala:160:20]
.io_lsu_ldq_full_1 (_lsu_io_core_ldq_full_1), // @[tile.scala:160:20]
.io_lsu_ldq_full_2 (_lsu_io_core_ldq_full_2), // @[tile.scala:160:20]
.io_lsu_stq_full_0 (_lsu_io_core_stq_full_0), // @[tile.scala:160:20]
.io_lsu_stq_full_1 (_lsu_io_core_stq_full_1), // @[tile.scala:160:20]
.io_lsu_stq_full_2 (_lsu_io_core_stq_full_2), // @[tile.scala:160:20]
.io_lsu_fp_stdata_ready (_lsu_io_core_fp_stdata_ready), // @[tile.scala:160:20]
.io_lsu_fp_stdata_valid (_core_io_lsu_fp_stdata_valid),
.io_lsu_fp_stdata_bits_uop_uopc (_core_io_lsu_fp_stdata_bits_uop_uopc),
.io_lsu_fp_stdata_bits_uop_inst (_core_io_lsu_fp_stdata_bits_uop_inst),
.io_lsu_fp_stdata_bits_uop_debug_inst (_core_io_lsu_fp_stdata_bits_uop_debug_inst),
.io_lsu_fp_stdata_bits_uop_is_rvc (_core_io_lsu_fp_stdata_bits_uop_is_rvc),
.io_lsu_fp_stdata_bits_uop_debug_pc (_core_io_lsu_fp_stdata_bits_uop_debug_pc),
.io_lsu_fp_stdata_bits_uop_iq_type (_core_io_lsu_fp_stdata_bits_uop_iq_type),
.io_lsu_fp_stdata_bits_uop_fu_code (_core_io_lsu_fp_stdata_bits_uop_fu_code),
.io_lsu_fp_stdata_bits_uop_ctrl_br_type (_core_io_lsu_fp_stdata_bits_uop_ctrl_br_type),
.io_lsu_fp_stdata_bits_uop_ctrl_op1_sel (_core_io_lsu_fp_stdata_bits_uop_ctrl_op1_sel),
.io_lsu_fp_stdata_bits_uop_ctrl_op2_sel (_core_io_lsu_fp_stdata_bits_uop_ctrl_op2_sel),
.io_lsu_fp_stdata_bits_uop_ctrl_imm_sel (_core_io_lsu_fp_stdata_bits_uop_ctrl_imm_sel),
.io_lsu_fp_stdata_bits_uop_ctrl_op_fcn (_core_io_lsu_fp_stdata_bits_uop_ctrl_op_fcn),
.io_lsu_fp_stdata_bits_uop_ctrl_fcn_dw (_core_io_lsu_fp_stdata_bits_uop_ctrl_fcn_dw),
.io_lsu_fp_stdata_bits_uop_ctrl_csr_cmd (_core_io_lsu_fp_stdata_bits_uop_ctrl_csr_cmd),
.io_lsu_fp_stdata_bits_uop_ctrl_is_load (_core_io_lsu_fp_stdata_bits_uop_ctrl_is_load),
.io_lsu_fp_stdata_bits_uop_ctrl_is_sta (_core_io_lsu_fp_stdata_bits_uop_ctrl_is_sta),
.io_lsu_fp_stdata_bits_uop_ctrl_is_std (_core_io_lsu_fp_stdata_bits_uop_ctrl_is_std),
.io_lsu_fp_stdata_bits_uop_iw_state (_core_io_lsu_fp_stdata_bits_uop_iw_state),
.io_lsu_fp_stdata_bits_uop_iw_p1_poisoned (_core_io_lsu_fp_stdata_bits_uop_iw_p1_poisoned),
.io_lsu_fp_stdata_bits_uop_iw_p2_poisoned (_core_io_lsu_fp_stdata_bits_uop_iw_p2_poisoned),
.io_lsu_fp_stdata_bits_uop_is_br (_core_io_lsu_fp_stdata_bits_uop_is_br),
.io_lsu_fp_stdata_bits_uop_is_jalr (_core_io_lsu_fp_stdata_bits_uop_is_jalr),
.io_lsu_fp_stdata_bits_uop_is_jal (_core_io_lsu_fp_stdata_bits_uop_is_jal),
.io_lsu_fp_stdata_bits_uop_is_sfb (_core_io_lsu_fp_stdata_bits_uop_is_sfb),
.io_lsu_fp_stdata_bits_uop_br_mask (_core_io_lsu_fp_stdata_bits_uop_br_mask),
.io_lsu_fp_stdata_bits_uop_br_tag (_core_io_lsu_fp_stdata_bits_uop_br_tag),
.io_lsu_fp_stdata_bits_uop_ftq_idx (_core_io_lsu_fp_stdata_bits_uop_ftq_idx),
.io_lsu_fp_stdata_bits_uop_edge_inst (_core_io_lsu_fp_stdata_bits_uop_edge_inst),
.io_lsu_fp_stdata_bits_uop_pc_lob (_core_io_lsu_fp_stdata_bits_uop_pc_lob),
.io_lsu_fp_stdata_bits_uop_taken (_core_io_lsu_fp_stdata_bits_uop_taken),
.io_lsu_fp_stdata_bits_uop_imm_packed (_core_io_lsu_fp_stdata_bits_uop_imm_packed),
.io_lsu_fp_stdata_bits_uop_csr_addr (_core_io_lsu_fp_stdata_bits_uop_csr_addr),
.io_lsu_fp_stdata_bits_uop_rob_idx (_core_io_lsu_fp_stdata_bits_uop_rob_idx),
.io_lsu_fp_stdata_bits_uop_ldq_idx (_core_io_lsu_fp_stdata_bits_uop_ldq_idx),
.io_lsu_fp_stdata_bits_uop_stq_idx (_core_io_lsu_fp_stdata_bits_uop_stq_idx),
.io_lsu_fp_stdata_bits_uop_rxq_idx (_core_io_lsu_fp_stdata_bits_uop_rxq_idx),
.io_lsu_fp_stdata_bits_uop_pdst (_core_io_lsu_fp_stdata_bits_uop_pdst),
.io_lsu_fp_stdata_bits_uop_prs1 (_core_io_lsu_fp_stdata_bits_uop_prs1),
.io_lsu_fp_stdata_bits_uop_prs2 (_core_io_lsu_fp_stdata_bits_uop_prs2),
.io_lsu_fp_stdata_bits_uop_prs3 (_core_io_lsu_fp_stdata_bits_uop_prs3),
.io_lsu_fp_stdata_bits_uop_ppred (_core_io_lsu_fp_stdata_bits_uop_ppred),
.io_lsu_fp_stdata_bits_uop_prs1_busy (_core_io_lsu_fp_stdata_bits_uop_prs1_busy),
.io_lsu_fp_stdata_bits_uop_prs2_busy (_core_io_lsu_fp_stdata_bits_uop_prs2_busy),
.io_lsu_fp_stdata_bits_uop_prs3_busy (_core_io_lsu_fp_stdata_bits_uop_prs3_busy),
.io_lsu_fp_stdata_bits_uop_ppred_busy (_core_io_lsu_fp_stdata_bits_uop_ppred_busy),
.io_lsu_fp_stdata_bits_uop_stale_pdst (_core_io_lsu_fp_stdata_bits_uop_stale_pdst),
.io_lsu_fp_stdata_bits_uop_exception (_core_io_lsu_fp_stdata_bits_uop_exception),
.io_lsu_fp_stdata_bits_uop_exc_cause (_core_io_lsu_fp_stdata_bits_uop_exc_cause),
.io_lsu_fp_stdata_bits_uop_bypassable (_core_io_lsu_fp_stdata_bits_uop_bypassable),
.io_lsu_fp_stdata_bits_uop_mem_cmd (_core_io_lsu_fp_stdata_bits_uop_mem_cmd),
.io_lsu_fp_stdata_bits_uop_mem_size (_core_io_lsu_fp_stdata_bits_uop_mem_size),
.io_lsu_fp_stdata_bits_uop_mem_signed (_core_io_lsu_fp_stdata_bits_uop_mem_signed),
.io_lsu_fp_stdata_bits_uop_is_fence (_core_io_lsu_fp_stdata_bits_uop_is_fence),
.io_lsu_fp_stdata_bits_uop_is_fencei (_core_io_lsu_fp_stdata_bits_uop_is_fencei),
.io_lsu_fp_stdata_bits_uop_is_amo (_core_io_lsu_fp_stdata_bits_uop_is_amo),
.io_lsu_fp_stdata_bits_uop_uses_ldq (_core_io_lsu_fp_stdata_bits_uop_uses_ldq),
.io_lsu_fp_stdata_bits_uop_uses_stq (_core_io_lsu_fp_stdata_bits_uop_uses_stq),
.io_lsu_fp_stdata_bits_uop_is_sys_pc2epc (_core_io_lsu_fp_stdata_bits_uop_is_sys_pc2epc),
.io_lsu_fp_stdata_bits_uop_is_unique (_core_io_lsu_fp_stdata_bits_uop_is_unique),
.io_lsu_fp_stdata_bits_uop_flush_on_commit (_core_io_lsu_fp_stdata_bits_uop_flush_on_commit),
.io_lsu_fp_stdata_bits_uop_ldst_is_rs1 (_core_io_lsu_fp_stdata_bits_uop_ldst_is_rs1),
.io_lsu_fp_stdata_bits_uop_ldst (_core_io_lsu_fp_stdata_bits_uop_ldst),
.io_lsu_fp_stdata_bits_uop_lrs1 (_core_io_lsu_fp_stdata_bits_uop_lrs1),
.io_lsu_fp_stdata_bits_uop_lrs2 (_core_io_lsu_fp_stdata_bits_uop_lrs2),
.io_lsu_fp_stdata_bits_uop_lrs3 (_core_io_lsu_fp_stdata_bits_uop_lrs3),
.io_lsu_fp_stdata_bits_uop_ldst_val (_core_io_lsu_fp_stdata_bits_uop_ldst_val),
.io_lsu_fp_stdata_bits_uop_dst_rtype (_core_io_lsu_fp_stdata_bits_uop_dst_rtype),
.io_lsu_fp_stdata_bits_uop_lrs1_rtype (_core_io_lsu_fp_stdata_bits_uop_lrs1_rtype),
.io_lsu_fp_stdata_bits_uop_lrs2_rtype (_core_io_lsu_fp_stdata_bits_uop_lrs2_rtype),
.io_lsu_fp_stdata_bits_uop_frs3_en (_core_io_lsu_fp_stdata_bits_uop_frs3_en),
.io_lsu_fp_stdata_bits_uop_fp_val (_core_io_lsu_fp_stdata_bits_uop_fp_val),
.io_lsu_fp_stdata_bits_uop_fp_single (_core_io_lsu_fp_stdata_bits_uop_fp_single),
.io_lsu_fp_stdata_bits_uop_xcpt_pf_if (_core_io_lsu_fp_stdata_bits_uop_xcpt_pf_if),
.io_lsu_fp_stdata_bits_uop_xcpt_ae_if (_core_io_lsu_fp_stdata_bits_uop_xcpt_ae_if),
.io_lsu_fp_stdata_bits_uop_xcpt_ma_if (_core_io_lsu_fp_stdata_bits_uop_xcpt_ma_if),
.io_lsu_fp_stdata_bits_uop_bp_debug_if (_core_io_lsu_fp_stdata_bits_uop_bp_debug_if),
.io_lsu_fp_stdata_bits_uop_bp_xcpt_if (_core_io_lsu_fp_stdata_bits_uop_bp_xcpt_if),
.io_lsu_fp_stdata_bits_uop_debug_fsrc (_core_io_lsu_fp_stdata_bits_uop_debug_fsrc),
.io_lsu_fp_stdata_bits_uop_debug_tsrc (_core_io_lsu_fp_stdata_bits_uop_debug_tsrc),
.io_lsu_fp_stdata_bits_data (_core_io_lsu_fp_stdata_bits_data),
.io_lsu_fp_stdata_bits_predicated (_core_io_lsu_fp_stdata_bits_predicated),
.io_lsu_fp_stdata_bits_fflags_valid (_core_io_lsu_fp_stdata_bits_fflags_valid),
.io_lsu_fp_stdata_bits_fflags_bits_uop_uopc (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_uopc),
.io_lsu_fp_stdata_bits_fflags_bits_uop_inst (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_inst),
.io_lsu_fp_stdata_bits_fflags_bits_uop_debug_inst (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_debug_inst),
.io_lsu_fp_stdata_bits_fflags_bits_uop_is_rvc (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_rvc),
.io_lsu_fp_stdata_bits_fflags_bits_uop_debug_pc (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_debug_pc),
.io_lsu_fp_stdata_bits_fflags_bits_uop_iq_type (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_iq_type),
.io_lsu_fp_stdata_bits_fflags_bits_uop_fu_code (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_fu_code),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_br_type (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_br_type),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op1_sel (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op1_sel),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op2_sel (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op2_sel),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_imm_sel (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_imm_sel),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op_fcn (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op_fcn),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_fcn_dw (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_fcn_dw),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_csr_cmd (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_csr_cmd),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_load (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_load),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_sta (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_sta),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_std (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_std),
.io_lsu_fp_stdata_bits_fflags_bits_uop_iw_state (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_iw_state),
.io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p1_poisoned (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p1_poisoned),
.io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p2_poisoned (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p2_poisoned),
.io_lsu_fp_stdata_bits_fflags_bits_uop_is_br (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_br),
.io_lsu_fp_stdata_bits_fflags_bits_uop_is_jalr (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_jalr),
.io_lsu_fp_stdata_bits_fflags_bits_uop_is_jal (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_jal),
.io_lsu_fp_stdata_bits_fflags_bits_uop_is_sfb (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_sfb),
.io_lsu_fp_stdata_bits_fflags_bits_uop_br_mask (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_br_mask),
.io_lsu_fp_stdata_bits_fflags_bits_uop_br_tag (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_br_tag),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ftq_idx (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ftq_idx),
.io_lsu_fp_stdata_bits_fflags_bits_uop_edge_inst (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_edge_inst),
.io_lsu_fp_stdata_bits_fflags_bits_uop_pc_lob (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_pc_lob),
.io_lsu_fp_stdata_bits_fflags_bits_uop_taken (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_taken),
.io_lsu_fp_stdata_bits_fflags_bits_uop_imm_packed (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_imm_packed),
.io_lsu_fp_stdata_bits_fflags_bits_uop_csr_addr (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_csr_addr),
.io_lsu_fp_stdata_bits_fflags_bits_uop_rob_idx (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_rob_idx),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ldq_idx (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ldq_idx),
.io_lsu_fp_stdata_bits_fflags_bits_uop_stq_idx (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_stq_idx),
.io_lsu_fp_stdata_bits_fflags_bits_uop_rxq_idx (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_rxq_idx),
.io_lsu_fp_stdata_bits_fflags_bits_uop_pdst (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_pdst),
.io_lsu_fp_stdata_bits_fflags_bits_uop_prs1 (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs1),
.io_lsu_fp_stdata_bits_fflags_bits_uop_prs2 (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs2),
.io_lsu_fp_stdata_bits_fflags_bits_uop_prs3 (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs3),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ppred (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ppred),
.io_lsu_fp_stdata_bits_fflags_bits_uop_prs1_busy (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs1_busy),
.io_lsu_fp_stdata_bits_fflags_bits_uop_prs2_busy (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs2_busy),
.io_lsu_fp_stdata_bits_fflags_bits_uop_prs3_busy (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs3_busy),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ppred_busy (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ppred_busy),
.io_lsu_fp_stdata_bits_fflags_bits_uop_stale_pdst (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_stale_pdst),
.io_lsu_fp_stdata_bits_fflags_bits_uop_exception (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_exception),
.io_lsu_fp_stdata_bits_fflags_bits_uop_exc_cause (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_exc_cause),
.io_lsu_fp_stdata_bits_fflags_bits_uop_bypassable (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_bypassable),
.io_lsu_fp_stdata_bits_fflags_bits_uop_mem_cmd (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_mem_cmd),
.io_lsu_fp_stdata_bits_fflags_bits_uop_mem_size (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_mem_size),
.io_lsu_fp_stdata_bits_fflags_bits_uop_mem_signed (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_mem_signed),
.io_lsu_fp_stdata_bits_fflags_bits_uop_is_fence (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_fence),
.io_lsu_fp_stdata_bits_fflags_bits_uop_is_fencei (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_fencei),
.io_lsu_fp_stdata_bits_fflags_bits_uop_is_amo (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_amo),
.io_lsu_fp_stdata_bits_fflags_bits_uop_uses_ldq (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_uses_ldq),
.io_lsu_fp_stdata_bits_fflags_bits_uop_uses_stq (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_uses_stq),
.io_lsu_fp_stdata_bits_fflags_bits_uop_is_sys_pc2epc (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_sys_pc2epc),
.io_lsu_fp_stdata_bits_fflags_bits_uop_is_unique (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_unique),
.io_lsu_fp_stdata_bits_fflags_bits_uop_flush_on_commit (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_flush_on_commit),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_is_rs1 (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_is_rs1),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ldst (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ldst),
.io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1 (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1),
.io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2 (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2),
.io_lsu_fp_stdata_bits_fflags_bits_uop_lrs3 (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs3),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_val (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_val),
.io_lsu_fp_stdata_bits_fflags_bits_uop_dst_rtype (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_dst_rtype),
.io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1_rtype (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1_rtype),
.io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2_rtype (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2_rtype),
.io_lsu_fp_stdata_bits_fflags_bits_uop_frs3_en (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_frs3_en),
.io_lsu_fp_stdata_bits_fflags_bits_uop_fp_val (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_fp_val),
.io_lsu_fp_stdata_bits_fflags_bits_uop_fp_single (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_fp_single),
.io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_pf_if (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_pf_if),
.io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ae_if (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ae_if),
.io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ma_if (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ma_if),
.io_lsu_fp_stdata_bits_fflags_bits_uop_bp_debug_if (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_bp_debug_if),
.io_lsu_fp_stdata_bits_fflags_bits_uop_bp_xcpt_if (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_bp_xcpt_if),
.io_lsu_fp_stdata_bits_fflags_bits_uop_debug_fsrc (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_debug_fsrc),
.io_lsu_fp_stdata_bits_fflags_bits_uop_debug_tsrc (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_debug_tsrc),
.io_lsu_fp_stdata_bits_fflags_bits_flags (_core_io_lsu_fp_stdata_bits_fflags_bits_flags),
.io_lsu_commit_valids_0 (_core_io_lsu_commit_valids_0),
.io_lsu_commit_valids_1 (_core_io_lsu_commit_valids_1),
.io_lsu_commit_valids_2 (_core_io_lsu_commit_valids_2),
.io_lsu_commit_arch_valids_0 (_core_io_lsu_commit_arch_valids_0),
.io_lsu_commit_arch_valids_1 (_core_io_lsu_commit_arch_valids_1),
.io_lsu_commit_arch_valids_2 (_core_io_lsu_commit_arch_valids_2),
.io_lsu_commit_uops_0_uopc (_core_io_lsu_commit_uops_0_uopc),
.io_lsu_commit_uops_0_inst (_core_io_lsu_commit_uops_0_inst),
.io_lsu_commit_uops_0_debug_inst (_core_io_lsu_commit_uops_0_debug_inst),
.io_lsu_commit_uops_0_is_rvc (_core_io_lsu_commit_uops_0_is_rvc),
.io_lsu_commit_uops_0_debug_pc (_core_io_lsu_commit_uops_0_debug_pc),
.io_lsu_commit_uops_0_iq_type (_core_io_lsu_commit_uops_0_iq_type),
.io_lsu_commit_uops_0_fu_code (_core_io_lsu_commit_uops_0_fu_code),
.io_lsu_commit_uops_0_ctrl_br_type (_core_io_lsu_commit_uops_0_ctrl_br_type),
.io_lsu_commit_uops_0_ctrl_op1_sel (_core_io_lsu_commit_uops_0_ctrl_op1_sel),
.io_lsu_commit_uops_0_ctrl_op2_sel (_core_io_lsu_commit_uops_0_ctrl_op2_sel),
.io_lsu_commit_uops_0_ctrl_imm_sel (_core_io_lsu_commit_uops_0_ctrl_imm_sel),
.io_lsu_commit_uops_0_ctrl_op_fcn (_core_io_lsu_commit_uops_0_ctrl_op_fcn),
.io_lsu_commit_uops_0_ctrl_fcn_dw (_core_io_lsu_commit_uops_0_ctrl_fcn_dw),
.io_lsu_commit_uops_0_ctrl_csr_cmd (_core_io_lsu_commit_uops_0_ctrl_csr_cmd),
.io_lsu_commit_uops_0_ctrl_is_load (_core_io_lsu_commit_uops_0_ctrl_is_load),
.io_lsu_commit_uops_0_ctrl_is_sta (_core_io_lsu_commit_uops_0_ctrl_is_sta),
.io_lsu_commit_uops_0_ctrl_is_std (_core_io_lsu_commit_uops_0_ctrl_is_std),
.io_lsu_commit_uops_0_iw_state (_core_io_lsu_commit_uops_0_iw_state),
.io_lsu_commit_uops_0_iw_p1_poisoned (_core_io_lsu_commit_uops_0_iw_p1_poisoned),
.io_lsu_commit_uops_0_iw_p2_poisoned (_core_io_lsu_commit_uops_0_iw_p2_poisoned),
.io_lsu_commit_uops_0_is_br (_core_io_lsu_commit_uops_0_is_br),
.io_lsu_commit_uops_0_is_jalr (_core_io_lsu_commit_uops_0_is_jalr),
.io_lsu_commit_uops_0_is_jal (_core_io_lsu_commit_uops_0_is_jal),
.io_lsu_commit_uops_0_is_sfb (_core_io_lsu_commit_uops_0_is_sfb),
.io_lsu_commit_uops_0_br_mask (_core_io_lsu_commit_uops_0_br_mask),
.io_lsu_commit_uops_0_br_tag (_core_io_lsu_commit_uops_0_br_tag),
.io_lsu_commit_uops_0_ftq_idx (_core_io_lsu_commit_uops_0_ftq_idx),
.io_lsu_commit_uops_0_edge_inst (_core_io_lsu_commit_uops_0_edge_inst),
.io_lsu_commit_uops_0_pc_lob (_core_io_lsu_commit_uops_0_pc_lob),
.io_lsu_commit_uops_0_taken (_core_io_lsu_commit_uops_0_taken),
.io_lsu_commit_uops_0_imm_packed (_core_io_lsu_commit_uops_0_imm_packed),
.io_lsu_commit_uops_0_csr_addr (_core_io_lsu_commit_uops_0_csr_addr),
.io_lsu_commit_uops_0_rob_idx (_core_io_lsu_commit_uops_0_rob_idx),
.io_lsu_commit_uops_0_ldq_idx (_core_io_lsu_commit_uops_0_ldq_idx),
.io_lsu_commit_uops_0_stq_idx (_core_io_lsu_commit_uops_0_stq_idx),
.io_lsu_commit_uops_0_rxq_idx (_core_io_lsu_commit_uops_0_rxq_idx),
.io_lsu_commit_uops_0_pdst (_core_io_lsu_commit_uops_0_pdst),
.io_lsu_commit_uops_0_prs1 (_core_io_lsu_commit_uops_0_prs1),
.io_lsu_commit_uops_0_prs2 (_core_io_lsu_commit_uops_0_prs2),
.io_lsu_commit_uops_0_prs3 (_core_io_lsu_commit_uops_0_prs3),
.io_lsu_commit_uops_0_ppred (_core_io_lsu_commit_uops_0_ppred),
.io_lsu_commit_uops_0_prs1_busy (_core_io_lsu_commit_uops_0_prs1_busy),
.io_lsu_commit_uops_0_prs2_busy (_core_io_lsu_commit_uops_0_prs2_busy),
.io_lsu_commit_uops_0_prs3_busy (_core_io_lsu_commit_uops_0_prs3_busy),
.io_lsu_commit_uops_0_ppred_busy (_core_io_lsu_commit_uops_0_ppred_busy),
.io_lsu_commit_uops_0_stale_pdst (_core_io_lsu_commit_uops_0_stale_pdst),
.io_lsu_commit_uops_0_exception (_core_io_lsu_commit_uops_0_exception),
.io_lsu_commit_uops_0_exc_cause (_core_io_lsu_commit_uops_0_exc_cause),
.io_lsu_commit_uops_0_bypassable (_core_io_lsu_commit_uops_0_bypassable),
.io_lsu_commit_uops_0_mem_cmd (_core_io_lsu_commit_uops_0_mem_cmd),
.io_lsu_commit_uops_0_mem_size (_core_io_lsu_commit_uops_0_mem_size),
.io_lsu_commit_uops_0_mem_signed (_core_io_lsu_commit_uops_0_mem_signed),
.io_lsu_commit_uops_0_is_fence (_core_io_lsu_commit_uops_0_is_fence),
.io_lsu_commit_uops_0_is_fencei (_core_io_lsu_commit_uops_0_is_fencei),
.io_lsu_commit_uops_0_is_amo (_core_io_lsu_commit_uops_0_is_amo),
.io_lsu_commit_uops_0_uses_ldq (_core_io_lsu_commit_uops_0_uses_ldq),
.io_lsu_commit_uops_0_uses_stq (_core_io_lsu_commit_uops_0_uses_stq),
.io_lsu_commit_uops_0_is_sys_pc2epc (_core_io_lsu_commit_uops_0_is_sys_pc2epc),
.io_lsu_commit_uops_0_is_unique (_core_io_lsu_commit_uops_0_is_unique),
.io_lsu_commit_uops_0_flush_on_commit (_core_io_lsu_commit_uops_0_flush_on_commit),
.io_lsu_commit_uops_0_ldst_is_rs1 (_core_io_lsu_commit_uops_0_ldst_is_rs1),
.io_lsu_commit_uops_0_ldst (_core_io_lsu_commit_uops_0_ldst),
.io_lsu_commit_uops_0_lrs1 (_core_io_lsu_commit_uops_0_lrs1),
.io_lsu_commit_uops_0_lrs2 (_core_io_lsu_commit_uops_0_lrs2),
.io_lsu_commit_uops_0_lrs3 (_core_io_lsu_commit_uops_0_lrs3),
.io_lsu_commit_uops_0_ldst_val (_core_io_lsu_commit_uops_0_ldst_val),
.io_lsu_commit_uops_0_dst_rtype (_core_io_lsu_commit_uops_0_dst_rtype),
.io_lsu_commit_uops_0_lrs1_rtype (_core_io_lsu_commit_uops_0_lrs1_rtype),
.io_lsu_commit_uops_0_lrs2_rtype (_core_io_lsu_commit_uops_0_lrs2_rtype),
.io_lsu_commit_uops_0_frs3_en (_core_io_lsu_commit_uops_0_frs3_en),
.io_lsu_commit_uops_0_fp_val (_core_io_lsu_commit_uops_0_fp_val),
.io_lsu_commit_uops_0_fp_single (_core_io_lsu_commit_uops_0_fp_single),
.io_lsu_commit_uops_0_xcpt_pf_if (_core_io_lsu_commit_uops_0_xcpt_pf_if),
.io_lsu_commit_uops_0_xcpt_ae_if (_core_io_lsu_commit_uops_0_xcpt_ae_if),
.io_lsu_commit_uops_0_xcpt_ma_if (_core_io_lsu_commit_uops_0_xcpt_ma_if),
.io_lsu_commit_uops_0_bp_debug_if (_core_io_lsu_commit_uops_0_bp_debug_if),
.io_lsu_commit_uops_0_bp_xcpt_if (_core_io_lsu_commit_uops_0_bp_xcpt_if),
.io_lsu_commit_uops_0_debug_fsrc (_core_io_lsu_commit_uops_0_debug_fsrc),
.io_lsu_commit_uops_0_debug_tsrc (_core_io_lsu_commit_uops_0_debug_tsrc),
.io_lsu_commit_uops_1_uopc (_core_io_lsu_commit_uops_1_uopc),
.io_lsu_commit_uops_1_inst (_core_io_lsu_commit_uops_1_inst),
.io_lsu_commit_uops_1_debug_inst (_core_io_lsu_commit_uops_1_debug_inst),
.io_lsu_commit_uops_1_is_rvc (_core_io_lsu_commit_uops_1_is_rvc),
.io_lsu_commit_uops_1_debug_pc (_core_io_lsu_commit_uops_1_debug_pc),
.io_lsu_commit_uops_1_iq_type (_core_io_lsu_commit_uops_1_iq_type),
.io_lsu_commit_uops_1_fu_code (_core_io_lsu_commit_uops_1_fu_code),
.io_lsu_commit_uops_1_ctrl_br_type (_core_io_lsu_commit_uops_1_ctrl_br_type),
.io_lsu_commit_uops_1_ctrl_op1_sel (_core_io_lsu_commit_uops_1_ctrl_op1_sel),
.io_lsu_commit_uops_1_ctrl_op2_sel (_core_io_lsu_commit_uops_1_ctrl_op2_sel),
.io_lsu_commit_uops_1_ctrl_imm_sel (_core_io_lsu_commit_uops_1_ctrl_imm_sel),
.io_lsu_commit_uops_1_ctrl_op_fcn (_core_io_lsu_commit_uops_1_ctrl_op_fcn),
.io_lsu_commit_uops_1_ctrl_fcn_dw (_core_io_lsu_commit_uops_1_ctrl_fcn_dw),
.io_lsu_commit_uops_1_ctrl_csr_cmd (_core_io_lsu_commit_uops_1_ctrl_csr_cmd),
.io_lsu_commit_uops_1_ctrl_is_load (_core_io_lsu_commit_uops_1_ctrl_is_load),
.io_lsu_commit_uops_1_ctrl_is_sta (_core_io_lsu_commit_uops_1_ctrl_is_sta),
.io_lsu_commit_uops_1_ctrl_is_std (_core_io_lsu_commit_uops_1_ctrl_is_std),
.io_lsu_commit_uops_1_iw_state (_core_io_lsu_commit_uops_1_iw_state),
.io_lsu_commit_uops_1_iw_p1_poisoned (_core_io_lsu_commit_uops_1_iw_p1_poisoned),
.io_lsu_commit_uops_1_iw_p2_poisoned (_core_io_lsu_commit_uops_1_iw_p2_poisoned),
.io_lsu_commit_uops_1_is_br (_core_io_lsu_commit_uops_1_is_br),
.io_lsu_commit_uops_1_is_jalr (_core_io_lsu_commit_uops_1_is_jalr),
.io_lsu_commit_uops_1_is_jal (_core_io_lsu_commit_uops_1_is_jal),
.io_lsu_commit_uops_1_is_sfb (_core_io_lsu_commit_uops_1_is_sfb),
.io_lsu_commit_uops_1_br_mask (_core_io_lsu_commit_uops_1_br_mask),
.io_lsu_commit_uops_1_br_tag (_core_io_lsu_commit_uops_1_br_tag),
.io_lsu_commit_uops_1_ftq_idx (_core_io_lsu_commit_uops_1_ftq_idx),
.io_lsu_commit_uops_1_edge_inst (_core_io_lsu_commit_uops_1_edge_inst),
.io_lsu_commit_uops_1_pc_lob (_core_io_lsu_commit_uops_1_pc_lob),
.io_lsu_commit_uops_1_taken (_core_io_lsu_commit_uops_1_taken),
.io_lsu_commit_uops_1_imm_packed (_core_io_lsu_commit_uops_1_imm_packed),
.io_lsu_commit_uops_1_csr_addr (_core_io_lsu_commit_uops_1_csr_addr),
.io_lsu_commit_uops_1_rob_idx (_core_io_lsu_commit_uops_1_rob_idx),
.io_lsu_commit_uops_1_ldq_idx (_core_io_lsu_commit_uops_1_ldq_idx),
.io_lsu_commit_uops_1_stq_idx (_core_io_lsu_commit_uops_1_stq_idx),
.io_lsu_commit_uops_1_rxq_idx (_core_io_lsu_commit_uops_1_rxq_idx),
.io_lsu_commit_uops_1_pdst (_core_io_lsu_commit_uops_1_pdst),
.io_lsu_commit_uops_1_prs1 (_core_io_lsu_commit_uops_1_prs1),
.io_lsu_commit_uops_1_prs2 (_core_io_lsu_commit_uops_1_prs2),
.io_lsu_commit_uops_1_prs3 (_core_io_lsu_commit_uops_1_prs3),
.io_lsu_commit_uops_1_ppred (_core_io_lsu_commit_uops_1_ppred),
.io_lsu_commit_uops_1_prs1_busy (_core_io_lsu_commit_uops_1_prs1_busy),
.io_lsu_commit_uops_1_prs2_busy (_core_io_lsu_commit_uops_1_prs2_busy),
.io_lsu_commit_uops_1_prs3_busy (_core_io_lsu_commit_uops_1_prs3_busy),
.io_lsu_commit_uops_1_ppred_busy (_core_io_lsu_commit_uops_1_ppred_busy),
.io_lsu_commit_uops_1_stale_pdst (_core_io_lsu_commit_uops_1_stale_pdst),
.io_lsu_commit_uops_1_exception (_core_io_lsu_commit_uops_1_exception),
.io_lsu_commit_uops_1_exc_cause (_core_io_lsu_commit_uops_1_exc_cause),
.io_lsu_commit_uops_1_bypassable (_core_io_lsu_commit_uops_1_bypassable),
.io_lsu_commit_uops_1_mem_cmd (_core_io_lsu_commit_uops_1_mem_cmd),
.io_lsu_commit_uops_1_mem_size (_core_io_lsu_commit_uops_1_mem_size),
.io_lsu_commit_uops_1_mem_signed (_core_io_lsu_commit_uops_1_mem_signed),
.io_lsu_commit_uops_1_is_fence (_core_io_lsu_commit_uops_1_is_fence),
.io_lsu_commit_uops_1_is_fencei (_core_io_lsu_commit_uops_1_is_fencei),
.io_lsu_commit_uops_1_is_amo (_core_io_lsu_commit_uops_1_is_amo),
.io_lsu_commit_uops_1_uses_ldq (_core_io_lsu_commit_uops_1_uses_ldq),
.io_lsu_commit_uops_1_uses_stq (_core_io_lsu_commit_uops_1_uses_stq),
.io_lsu_commit_uops_1_is_sys_pc2epc (_core_io_lsu_commit_uops_1_is_sys_pc2epc),
.io_lsu_commit_uops_1_is_unique (_core_io_lsu_commit_uops_1_is_unique),
.io_lsu_commit_uops_1_flush_on_commit (_core_io_lsu_commit_uops_1_flush_on_commit),
.io_lsu_commit_uops_1_ldst_is_rs1 (_core_io_lsu_commit_uops_1_ldst_is_rs1),
.io_lsu_commit_uops_1_ldst (_core_io_lsu_commit_uops_1_ldst),
.io_lsu_commit_uops_1_lrs1 (_core_io_lsu_commit_uops_1_lrs1),
.io_lsu_commit_uops_1_lrs2 (_core_io_lsu_commit_uops_1_lrs2),
.io_lsu_commit_uops_1_lrs3 (_core_io_lsu_commit_uops_1_lrs3),
.io_lsu_commit_uops_1_ldst_val (_core_io_lsu_commit_uops_1_ldst_val),
.io_lsu_commit_uops_1_dst_rtype (_core_io_lsu_commit_uops_1_dst_rtype),
.io_lsu_commit_uops_1_lrs1_rtype (_core_io_lsu_commit_uops_1_lrs1_rtype),
.io_lsu_commit_uops_1_lrs2_rtype (_core_io_lsu_commit_uops_1_lrs2_rtype),
.io_lsu_commit_uops_1_frs3_en (_core_io_lsu_commit_uops_1_frs3_en),
.io_lsu_commit_uops_1_fp_val (_core_io_lsu_commit_uops_1_fp_val),
.io_lsu_commit_uops_1_fp_single (_core_io_lsu_commit_uops_1_fp_single),
.io_lsu_commit_uops_1_xcpt_pf_if (_core_io_lsu_commit_uops_1_xcpt_pf_if),
.io_lsu_commit_uops_1_xcpt_ae_if (_core_io_lsu_commit_uops_1_xcpt_ae_if),
.io_lsu_commit_uops_1_xcpt_ma_if (_core_io_lsu_commit_uops_1_xcpt_ma_if),
.io_lsu_commit_uops_1_bp_debug_if (_core_io_lsu_commit_uops_1_bp_debug_if),
.io_lsu_commit_uops_1_bp_xcpt_if (_core_io_lsu_commit_uops_1_bp_xcpt_if),
.io_lsu_commit_uops_1_debug_fsrc (_core_io_lsu_commit_uops_1_debug_fsrc),
.io_lsu_commit_uops_1_debug_tsrc (_core_io_lsu_commit_uops_1_debug_tsrc),
.io_lsu_commit_uops_2_uopc (_core_io_lsu_commit_uops_2_uopc),
.io_lsu_commit_uops_2_inst (_core_io_lsu_commit_uops_2_inst),
.io_lsu_commit_uops_2_debug_inst (_core_io_lsu_commit_uops_2_debug_inst),
.io_lsu_commit_uops_2_is_rvc (_core_io_lsu_commit_uops_2_is_rvc),
.io_lsu_commit_uops_2_debug_pc (_core_io_lsu_commit_uops_2_debug_pc),
.io_lsu_commit_uops_2_iq_type (_core_io_lsu_commit_uops_2_iq_type),
.io_lsu_commit_uops_2_fu_code (_core_io_lsu_commit_uops_2_fu_code),
.io_lsu_commit_uops_2_ctrl_br_type (_core_io_lsu_commit_uops_2_ctrl_br_type),
.io_lsu_commit_uops_2_ctrl_op1_sel (_core_io_lsu_commit_uops_2_ctrl_op1_sel),
.io_lsu_commit_uops_2_ctrl_op2_sel (_core_io_lsu_commit_uops_2_ctrl_op2_sel),
.io_lsu_commit_uops_2_ctrl_imm_sel (_core_io_lsu_commit_uops_2_ctrl_imm_sel),
.io_lsu_commit_uops_2_ctrl_op_fcn (_core_io_lsu_commit_uops_2_ctrl_op_fcn),
.io_lsu_commit_uops_2_ctrl_fcn_dw (_core_io_lsu_commit_uops_2_ctrl_fcn_dw),
.io_lsu_commit_uops_2_ctrl_csr_cmd (_core_io_lsu_commit_uops_2_ctrl_csr_cmd),
.io_lsu_commit_uops_2_ctrl_is_load (_core_io_lsu_commit_uops_2_ctrl_is_load),
.io_lsu_commit_uops_2_ctrl_is_sta (_core_io_lsu_commit_uops_2_ctrl_is_sta),
.io_lsu_commit_uops_2_ctrl_is_std (_core_io_lsu_commit_uops_2_ctrl_is_std),
.io_lsu_commit_uops_2_iw_state (_core_io_lsu_commit_uops_2_iw_state),
.io_lsu_commit_uops_2_iw_p1_poisoned (_core_io_lsu_commit_uops_2_iw_p1_poisoned),
.io_lsu_commit_uops_2_iw_p2_poisoned (_core_io_lsu_commit_uops_2_iw_p2_poisoned),
.io_lsu_commit_uops_2_is_br (_core_io_lsu_commit_uops_2_is_br),
.io_lsu_commit_uops_2_is_jalr (_core_io_lsu_commit_uops_2_is_jalr),
.io_lsu_commit_uops_2_is_jal (_core_io_lsu_commit_uops_2_is_jal),
.io_lsu_commit_uops_2_is_sfb (_core_io_lsu_commit_uops_2_is_sfb),
.io_lsu_commit_uops_2_br_mask (_core_io_lsu_commit_uops_2_br_mask),
.io_lsu_commit_uops_2_br_tag (_core_io_lsu_commit_uops_2_br_tag),
.io_lsu_commit_uops_2_ftq_idx (_core_io_lsu_commit_uops_2_ftq_idx),
.io_lsu_commit_uops_2_edge_inst (_core_io_lsu_commit_uops_2_edge_inst),
.io_lsu_commit_uops_2_pc_lob (_core_io_lsu_commit_uops_2_pc_lob),
.io_lsu_commit_uops_2_taken (_core_io_lsu_commit_uops_2_taken),
.io_lsu_commit_uops_2_imm_packed (_core_io_lsu_commit_uops_2_imm_packed),
.io_lsu_commit_uops_2_csr_addr (_core_io_lsu_commit_uops_2_csr_addr),
.io_lsu_commit_uops_2_rob_idx (_core_io_lsu_commit_uops_2_rob_idx),
.io_lsu_commit_uops_2_ldq_idx (_core_io_lsu_commit_uops_2_ldq_idx),
.io_lsu_commit_uops_2_stq_idx (_core_io_lsu_commit_uops_2_stq_idx),
.io_lsu_commit_uops_2_rxq_idx (_core_io_lsu_commit_uops_2_rxq_idx),
.io_lsu_commit_uops_2_pdst (_core_io_lsu_commit_uops_2_pdst),
.io_lsu_commit_uops_2_prs1 (_core_io_lsu_commit_uops_2_prs1),
.io_lsu_commit_uops_2_prs2 (_core_io_lsu_commit_uops_2_prs2),
.io_lsu_commit_uops_2_prs3 (_core_io_lsu_commit_uops_2_prs3),
.io_lsu_commit_uops_2_ppred (_core_io_lsu_commit_uops_2_ppred),
.io_lsu_commit_uops_2_prs1_busy (_core_io_lsu_commit_uops_2_prs1_busy),
.io_lsu_commit_uops_2_prs2_busy (_core_io_lsu_commit_uops_2_prs2_busy),
.io_lsu_commit_uops_2_prs3_busy (_core_io_lsu_commit_uops_2_prs3_busy),
.io_lsu_commit_uops_2_ppred_busy (_core_io_lsu_commit_uops_2_ppred_busy),
.io_lsu_commit_uops_2_stale_pdst (_core_io_lsu_commit_uops_2_stale_pdst),
.io_lsu_commit_uops_2_exception (_core_io_lsu_commit_uops_2_exception),
.io_lsu_commit_uops_2_exc_cause (_core_io_lsu_commit_uops_2_exc_cause),
.io_lsu_commit_uops_2_bypassable (_core_io_lsu_commit_uops_2_bypassable),
.io_lsu_commit_uops_2_mem_cmd (_core_io_lsu_commit_uops_2_mem_cmd),
.io_lsu_commit_uops_2_mem_size (_core_io_lsu_commit_uops_2_mem_size),
.io_lsu_commit_uops_2_mem_signed (_core_io_lsu_commit_uops_2_mem_signed),
.io_lsu_commit_uops_2_is_fence (_core_io_lsu_commit_uops_2_is_fence),
.io_lsu_commit_uops_2_is_fencei (_core_io_lsu_commit_uops_2_is_fencei),
.io_lsu_commit_uops_2_is_amo (_core_io_lsu_commit_uops_2_is_amo),
.io_lsu_commit_uops_2_uses_ldq (_core_io_lsu_commit_uops_2_uses_ldq),
.io_lsu_commit_uops_2_uses_stq (_core_io_lsu_commit_uops_2_uses_stq),
.io_lsu_commit_uops_2_is_sys_pc2epc (_core_io_lsu_commit_uops_2_is_sys_pc2epc),
.io_lsu_commit_uops_2_is_unique (_core_io_lsu_commit_uops_2_is_unique),
.io_lsu_commit_uops_2_flush_on_commit (_core_io_lsu_commit_uops_2_flush_on_commit),
.io_lsu_commit_uops_2_ldst_is_rs1 (_core_io_lsu_commit_uops_2_ldst_is_rs1),
.io_lsu_commit_uops_2_ldst (_core_io_lsu_commit_uops_2_ldst),
.io_lsu_commit_uops_2_lrs1 (_core_io_lsu_commit_uops_2_lrs1),
.io_lsu_commit_uops_2_lrs2 (_core_io_lsu_commit_uops_2_lrs2),
.io_lsu_commit_uops_2_lrs3 (_core_io_lsu_commit_uops_2_lrs3),
.io_lsu_commit_uops_2_ldst_val (_core_io_lsu_commit_uops_2_ldst_val),
.io_lsu_commit_uops_2_dst_rtype (_core_io_lsu_commit_uops_2_dst_rtype),
.io_lsu_commit_uops_2_lrs1_rtype (_core_io_lsu_commit_uops_2_lrs1_rtype),
.io_lsu_commit_uops_2_lrs2_rtype (_core_io_lsu_commit_uops_2_lrs2_rtype),
.io_lsu_commit_uops_2_frs3_en (_core_io_lsu_commit_uops_2_frs3_en),
.io_lsu_commit_uops_2_fp_val (_core_io_lsu_commit_uops_2_fp_val),
.io_lsu_commit_uops_2_fp_single (_core_io_lsu_commit_uops_2_fp_single),
.io_lsu_commit_uops_2_xcpt_pf_if (_core_io_lsu_commit_uops_2_xcpt_pf_if),
.io_lsu_commit_uops_2_xcpt_ae_if (_core_io_lsu_commit_uops_2_xcpt_ae_if),
.io_lsu_commit_uops_2_xcpt_ma_if (_core_io_lsu_commit_uops_2_xcpt_ma_if),
.io_lsu_commit_uops_2_bp_debug_if (_core_io_lsu_commit_uops_2_bp_debug_if),
.io_lsu_commit_uops_2_bp_xcpt_if (_core_io_lsu_commit_uops_2_bp_xcpt_if),
.io_lsu_commit_uops_2_debug_fsrc (_core_io_lsu_commit_uops_2_debug_fsrc),
.io_lsu_commit_uops_2_debug_tsrc (_core_io_lsu_commit_uops_2_debug_tsrc),
.io_lsu_commit_fflags_valid (_core_io_lsu_commit_fflags_valid),
.io_lsu_commit_fflags_bits (_core_io_lsu_commit_fflags_bits),
.io_lsu_commit_debug_insts_0 (_core_io_lsu_commit_debug_insts_0),
.io_lsu_commit_debug_insts_1 (_core_io_lsu_commit_debug_insts_1),
.io_lsu_commit_debug_insts_2 (_core_io_lsu_commit_debug_insts_2),
.io_lsu_commit_rbk_valids_0 (_core_io_lsu_commit_rbk_valids_0),
.io_lsu_commit_rbk_valids_1 (_core_io_lsu_commit_rbk_valids_1),
.io_lsu_commit_rbk_valids_2 (_core_io_lsu_commit_rbk_valids_2),
.io_lsu_commit_rollback (_core_io_lsu_commit_rollback),
.io_lsu_commit_debug_wdata_0 (_core_io_lsu_commit_debug_wdata_0),
.io_lsu_commit_debug_wdata_1 (_core_io_lsu_commit_debug_wdata_1),
.io_lsu_commit_debug_wdata_2 (_core_io_lsu_commit_debug_wdata_2),
.io_lsu_commit_load_at_rob_head (_core_io_lsu_commit_load_at_rob_head),
.io_lsu_clr_bsy_0_valid (_lsu_io_core_clr_bsy_0_valid), // @[tile.scala:160:20]
.io_lsu_clr_bsy_0_bits (_lsu_io_core_clr_bsy_0_bits), // @[tile.scala:160:20]
.io_lsu_clr_bsy_1_valid (_lsu_io_core_clr_bsy_1_valid), // @[tile.scala:160:20]
.io_lsu_clr_bsy_1_bits (_lsu_io_core_clr_bsy_1_bits), // @[tile.scala:160:20]
.io_lsu_clr_unsafe_0_bits (_lsu_io_core_clr_unsafe_0_bits), // @[tile.scala:160:20]
.io_lsu_fence_dmem (_core_io_lsu_fence_dmem),
.io_lsu_spec_ld_wakeup_0_valid (_lsu_io_core_spec_ld_wakeup_0_valid), // @[tile.scala:160:20]
.io_lsu_spec_ld_wakeup_0_bits (_lsu_io_core_spec_ld_wakeup_0_bits), // @[tile.scala:160:20]
.io_lsu_ld_miss (_lsu_io_core_ld_miss), // @[tile.scala:160:20]
.io_lsu_brupdate_b1_resolve_mask (_core_io_lsu_brupdate_b1_resolve_mask),
.io_lsu_brupdate_b1_mispredict_mask (_core_io_lsu_brupdate_b1_mispredict_mask),
.io_lsu_brupdate_b2_uop_uopc (_core_io_lsu_brupdate_b2_uop_uopc),
.io_lsu_brupdate_b2_uop_inst (_core_io_lsu_brupdate_b2_uop_inst),
.io_lsu_brupdate_b2_uop_debug_inst (_core_io_lsu_brupdate_b2_uop_debug_inst),
.io_lsu_brupdate_b2_uop_is_rvc (_core_io_lsu_brupdate_b2_uop_is_rvc),
.io_lsu_brupdate_b2_uop_debug_pc (_core_io_lsu_brupdate_b2_uop_debug_pc),
.io_lsu_brupdate_b2_uop_iq_type (_core_io_lsu_brupdate_b2_uop_iq_type),
.io_lsu_brupdate_b2_uop_fu_code (_core_io_lsu_brupdate_b2_uop_fu_code),
.io_lsu_brupdate_b2_uop_ctrl_br_type (_core_io_lsu_brupdate_b2_uop_ctrl_br_type),
.io_lsu_brupdate_b2_uop_ctrl_op1_sel (_core_io_lsu_brupdate_b2_uop_ctrl_op1_sel),
.io_lsu_brupdate_b2_uop_ctrl_op2_sel (_core_io_lsu_brupdate_b2_uop_ctrl_op2_sel),
.io_lsu_brupdate_b2_uop_ctrl_imm_sel (_core_io_lsu_brupdate_b2_uop_ctrl_imm_sel),
.io_lsu_brupdate_b2_uop_ctrl_op_fcn (_core_io_lsu_brupdate_b2_uop_ctrl_op_fcn),
.io_lsu_brupdate_b2_uop_ctrl_fcn_dw (_core_io_lsu_brupdate_b2_uop_ctrl_fcn_dw),
.io_lsu_brupdate_b2_uop_ctrl_csr_cmd (_core_io_lsu_brupdate_b2_uop_ctrl_csr_cmd),
.io_lsu_brupdate_b2_uop_ctrl_is_load (_core_io_lsu_brupdate_b2_uop_ctrl_is_load),
.io_lsu_brupdate_b2_uop_ctrl_is_sta (_core_io_lsu_brupdate_b2_uop_ctrl_is_sta),
.io_lsu_brupdate_b2_uop_ctrl_is_std (_core_io_lsu_brupdate_b2_uop_ctrl_is_std),
.io_lsu_brupdate_b2_uop_iw_state (_core_io_lsu_brupdate_b2_uop_iw_state),
.io_lsu_brupdate_b2_uop_iw_p1_poisoned (_core_io_lsu_brupdate_b2_uop_iw_p1_poisoned),
.io_lsu_brupdate_b2_uop_iw_p2_poisoned (_core_io_lsu_brupdate_b2_uop_iw_p2_poisoned),
.io_lsu_brupdate_b2_uop_is_br (_core_io_lsu_brupdate_b2_uop_is_br),
.io_lsu_brupdate_b2_uop_is_jalr (_core_io_lsu_brupdate_b2_uop_is_jalr),
.io_lsu_brupdate_b2_uop_is_jal (_core_io_lsu_brupdate_b2_uop_is_jal),
.io_lsu_brupdate_b2_uop_is_sfb (_core_io_lsu_brupdate_b2_uop_is_sfb),
.io_lsu_brupdate_b2_uop_br_mask (_core_io_lsu_brupdate_b2_uop_br_mask),
.io_lsu_brupdate_b2_uop_br_tag (_core_io_lsu_brupdate_b2_uop_br_tag),
.io_lsu_brupdate_b2_uop_ftq_idx (_core_io_lsu_brupdate_b2_uop_ftq_idx),
.io_lsu_brupdate_b2_uop_edge_inst (_core_io_lsu_brupdate_b2_uop_edge_inst),
.io_lsu_brupdate_b2_uop_pc_lob (_core_io_lsu_brupdate_b2_uop_pc_lob),
.io_lsu_brupdate_b2_uop_taken (_core_io_lsu_brupdate_b2_uop_taken),
.io_lsu_brupdate_b2_uop_imm_packed (_core_io_lsu_brupdate_b2_uop_imm_packed),
.io_lsu_brupdate_b2_uop_csr_addr (_core_io_lsu_brupdate_b2_uop_csr_addr),
.io_lsu_brupdate_b2_uop_rob_idx (_core_io_lsu_brupdate_b2_uop_rob_idx),
.io_lsu_brupdate_b2_uop_ldq_idx (_core_io_lsu_brupdate_b2_uop_ldq_idx),
.io_lsu_brupdate_b2_uop_stq_idx (_core_io_lsu_brupdate_b2_uop_stq_idx),
.io_lsu_brupdate_b2_uop_rxq_idx (_core_io_lsu_brupdate_b2_uop_rxq_idx),
.io_lsu_brupdate_b2_uop_pdst (_core_io_lsu_brupdate_b2_uop_pdst),
.io_lsu_brupdate_b2_uop_prs1 (_core_io_lsu_brupdate_b2_uop_prs1),
.io_lsu_brupdate_b2_uop_prs2 (_core_io_lsu_brupdate_b2_uop_prs2),
.io_lsu_brupdate_b2_uop_prs3 (_core_io_lsu_brupdate_b2_uop_prs3),
.io_lsu_brupdate_b2_uop_ppred (_core_io_lsu_brupdate_b2_uop_ppred),
.io_lsu_brupdate_b2_uop_prs1_busy (_core_io_lsu_brupdate_b2_uop_prs1_busy),
.io_lsu_brupdate_b2_uop_prs2_busy (_core_io_lsu_brupdate_b2_uop_prs2_busy),
.io_lsu_brupdate_b2_uop_prs3_busy (_core_io_lsu_brupdate_b2_uop_prs3_busy),
.io_lsu_brupdate_b2_uop_ppred_busy (_core_io_lsu_brupdate_b2_uop_ppred_busy),
.io_lsu_brupdate_b2_uop_stale_pdst (_core_io_lsu_brupdate_b2_uop_stale_pdst),
.io_lsu_brupdate_b2_uop_exception (_core_io_lsu_brupdate_b2_uop_exception),
.io_lsu_brupdate_b2_uop_exc_cause (_core_io_lsu_brupdate_b2_uop_exc_cause),
.io_lsu_brupdate_b2_uop_bypassable (_core_io_lsu_brupdate_b2_uop_bypassable),
.io_lsu_brupdate_b2_uop_mem_cmd (_core_io_lsu_brupdate_b2_uop_mem_cmd),
.io_lsu_brupdate_b2_uop_mem_size (_core_io_lsu_brupdate_b2_uop_mem_size),
.io_lsu_brupdate_b2_uop_mem_signed (_core_io_lsu_brupdate_b2_uop_mem_signed),
.io_lsu_brupdate_b2_uop_is_fence (_core_io_lsu_brupdate_b2_uop_is_fence),
.io_lsu_brupdate_b2_uop_is_fencei (_core_io_lsu_brupdate_b2_uop_is_fencei),
.io_lsu_brupdate_b2_uop_is_amo (_core_io_lsu_brupdate_b2_uop_is_amo),
.io_lsu_brupdate_b2_uop_uses_ldq (_core_io_lsu_brupdate_b2_uop_uses_ldq),
.io_lsu_brupdate_b2_uop_uses_stq (_core_io_lsu_brupdate_b2_uop_uses_stq),
.io_lsu_brupdate_b2_uop_is_sys_pc2epc (_core_io_lsu_brupdate_b2_uop_is_sys_pc2epc),
.io_lsu_brupdate_b2_uop_is_unique (_core_io_lsu_brupdate_b2_uop_is_unique),
.io_lsu_brupdate_b2_uop_flush_on_commit (_core_io_lsu_brupdate_b2_uop_flush_on_commit),
.io_lsu_brupdate_b2_uop_ldst_is_rs1 (_core_io_lsu_brupdate_b2_uop_ldst_is_rs1),
.io_lsu_brupdate_b2_uop_ldst (_core_io_lsu_brupdate_b2_uop_ldst),
.io_lsu_brupdate_b2_uop_lrs1 (_core_io_lsu_brupdate_b2_uop_lrs1),
.io_lsu_brupdate_b2_uop_lrs2 (_core_io_lsu_brupdate_b2_uop_lrs2),
.io_lsu_brupdate_b2_uop_lrs3 (_core_io_lsu_brupdate_b2_uop_lrs3),
.io_lsu_brupdate_b2_uop_ldst_val (_core_io_lsu_brupdate_b2_uop_ldst_val),
.io_lsu_brupdate_b2_uop_dst_rtype (_core_io_lsu_brupdate_b2_uop_dst_rtype),
.io_lsu_brupdate_b2_uop_lrs1_rtype (_core_io_lsu_brupdate_b2_uop_lrs1_rtype),
.io_lsu_brupdate_b2_uop_lrs2_rtype (_core_io_lsu_brupdate_b2_uop_lrs2_rtype),
.io_lsu_brupdate_b2_uop_frs3_en (_core_io_lsu_brupdate_b2_uop_frs3_en),
.io_lsu_brupdate_b2_uop_fp_val (_core_io_lsu_brupdate_b2_uop_fp_val),
.io_lsu_brupdate_b2_uop_fp_single (_core_io_lsu_brupdate_b2_uop_fp_single),
.io_lsu_brupdate_b2_uop_xcpt_pf_if (_core_io_lsu_brupdate_b2_uop_xcpt_pf_if),
.io_lsu_brupdate_b2_uop_xcpt_ae_if (_core_io_lsu_brupdate_b2_uop_xcpt_ae_if),
.io_lsu_brupdate_b2_uop_xcpt_ma_if (_core_io_lsu_brupdate_b2_uop_xcpt_ma_if),
.io_lsu_brupdate_b2_uop_bp_debug_if (_core_io_lsu_brupdate_b2_uop_bp_debug_if),
.io_lsu_brupdate_b2_uop_bp_xcpt_if (_core_io_lsu_brupdate_b2_uop_bp_xcpt_if),
.io_lsu_brupdate_b2_uop_debug_fsrc (_core_io_lsu_brupdate_b2_uop_debug_fsrc),
.io_lsu_brupdate_b2_uop_debug_tsrc (_core_io_lsu_brupdate_b2_uop_debug_tsrc),
.io_lsu_brupdate_b2_valid (_core_io_lsu_brupdate_b2_valid),
.io_lsu_brupdate_b2_mispredict (_core_io_lsu_brupdate_b2_mispredict),
.io_lsu_brupdate_b2_taken (_core_io_lsu_brupdate_b2_taken),
.io_lsu_brupdate_b2_cfi_type (_core_io_lsu_brupdate_b2_cfi_type),
.io_lsu_brupdate_b2_pc_sel (_core_io_lsu_brupdate_b2_pc_sel),
.io_lsu_brupdate_b2_jalr_target (_core_io_lsu_brupdate_b2_jalr_target),
.io_lsu_brupdate_b2_target_offset (_core_io_lsu_brupdate_b2_target_offset),
.io_lsu_rob_pnr_idx (_core_io_lsu_rob_pnr_idx),
.io_lsu_rob_head_idx (_core_io_lsu_rob_head_idx),
.io_lsu_exception (_core_io_lsu_exception),
.io_lsu_fencei_rdy (_lsu_io_core_fencei_rdy), // @[tile.scala:160:20]
.io_lsu_lxcpt_valid (_lsu_io_core_lxcpt_valid), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_uopc (_lsu_io_core_lxcpt_bits_uop_uopc), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_inst (_lsu_io_core_lxcpt_bits_uop_inst), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_debug_inst (_lsu_io_core_lxcpt_bits_uop_debug_inst), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_is_rvc (_lsu_io_core_lxcpt_bits_uop_is_rvc), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_debug_pc (_lsu_io_core_lxcpt_bits_uop_debug_pc), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_iq_type (_lsu_io_core_lxcpt_bits_uop_iq_type), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_fu_code (_lsu_io_core_lxcpt_bits_uop_fu_code), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ctrl_br_type (_lsu_io_core_lxcpt_bits_uop_ctrl_br_type), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ctrl_op1_sel (_lsu_io_core_lxcpt_bits_uop_ctrl_op1_sel), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ctrl_op2_sel (_lsu_io_core_lxcpt_bits_uop_ctrl_op2_sel), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ctrl_imm_sel (_lsu_io_core_lxcpt_bits_uop_ctrl_imm_sel), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ctrl_op_fcn (_lsu_io_core_lxcpt_bits_uop_ctrl_op_fcn), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ctrl_fcn_dw (_lsu_io_core_lxcpt_bits_uop_ctrl_fcn_dw), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ctrl_csr_cmd (_lsu_io_core_lxcpt_bits_uop_ctrl_csr_cmd), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ctrl_is_load (_lsu_io_core_lxcpt_bits_uop_ctrl_is_load), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ctrl_is_sta (_lsu_io_core_lxcpt_bits_uop_ctrl_is_sta), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ctrl_is_std (_lsu_io_core_lxcpt_bits_uop_ctrl_is_std), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_iw_state (_lsu_io_core_lxcpt_bits_uop_iw_state), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_iw_p1_poisoned (_lsu_io_core_lxcpt_bits_uop_iw_p1_poisoned), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_iw_p2_poisoned (_lsu_io_core_lxcpt_bits_uop_iw_p2_poisoned), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_is_br (_lsu_io_core_lxcpt_bits_uop_is_br), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_is_jalr (_lsu_io_core_lxcpt_bits_uop_is_jalr), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_is_jal (_lsu_io_core_lxcpt_bits_uop_is_jal), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_is_sfb (_lsu_io_core_lxcpt_bits_uop_is_sfb), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_br_mask (_lsu_io_core_lxcpt_bits_uop_br_mask), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_br_tag (_lsu_io_core_lxcpt_bits_uop_br_tag), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ftq_idx (_lsu_io_core_lxcpt_bits_uop_ftq_idx), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_edge_inst (_lsu_io_core_lxcpt_bits_uop_edge_inst), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_pc_lob (_lsu_io_core_lxcpt_bits_uop_pc_lob), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_taken (_lsu_io_core_lxcpt_bits_uop_taken), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_imm_packed (_lsu_io_core_lxcpt_bits_uop_imm_packed), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_csr_addr (_lsu_io_core_lxcpt_bits_uop_csr_addr), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_rob_idx (_lsu_io_core_lxcpt_bits_uop_rob_idx), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ldq_idx (_lsu_io_core_lxcpt_bits_uop_ldq_idx), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_stq_idx (_lsu_io_core_lxcpt_bits_uop_stq_idx), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_rxq_idx (_lsu_io_core_lxcpt_bits_uop_rxq_idx), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_pdst (_lsu_io_core_lxcpt_bits_uop_pdst), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_prs1 (_lsu_io_core_lxcpt_bits_uop_prs1), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_prs2 (_lsu_io_core_lxcpt_bits_uop_prs2), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_prs3 (_lsu_io_core_lxcpt_bits_uop_prs3), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ppred (_lsu_io_core_lxcpt_bits_uop_ppred), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_prs1_busy (_lsu_io_core_lxcpt_bits_uop_prs1_busy), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_prs2_busy (_lsu_io_core_lxcpt_bits_uop_prs2_busy), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_prs3_busy (_lsu_io_core_lxcpt_bits_uop_prs3_busy), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ppred_busy (_lsu_io_core_lxcpt_bits_uop_ppred_busy), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_stale_pdst (_lsu_io_core_lxcpt_bits_uop_stale_pdst), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_exception (_lsu_io_core_lxcpt_bits_uop_exception), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_exc_cause (_lsu_io_core_lxcpt_bits_uop_exc_cause), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_bypassable (_lsu_io_core_lxcpt_bits_uop_bypassable), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_mem_cmd (_lsu_io_core_lxcpt_bits_uop_mem_cmd), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_mem_size (_lsu_io_core_lxcpt_bits_uop_mem_size), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_mem_signed (_lsu_io_core_lxcpt_bits_uop_mem_signed), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_is_fence (_lsu_io_core_lxcpt_bits_uop_is_fence), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_is_fencei (_lsu_io_core_lxcpt_bits_uop_is_fencei), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_is_amo (_lsu_io_core_lxcpt_bits_uop_is_amo), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_uses_ldq (_lsu_io_core_lxcpt_bits_uop_uses_ldq), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_uses_stq (_lsu_io_core_lxcpt_bits_uop_uses_stq), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_is_sys_pc2epc (_lsu_io_core_lxcpt_bits_uop_is_sys_pc2epc), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_is_unique (_lsu_io_core_lxcpt_bits_uop_is_unique), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_flush_on_commit (_lsu_io_core_lxcpt_bits_uop_flush_on_commit), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ldst_is_rs1 (_lsu_io_core_lxcpt_bits_uop_ldst_is_rs1), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ldst (_lsu_io_core_lxcpt_bits_uop_ldst), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_lrs1 (_lsu_io_core_lxcpt_bits_uop_lrs1), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_lrs2 (_lsu_io_core_lxcpt_bits_uop_lrs2), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_lrs3 (_lsu_io_core_lxcpt_bits_uop_lrs3), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ldst_val (_lsu_io_core_lxcpt_bits_uop_ldst_val), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_dst_rtype (_lsu_io_core_lxcpt_bits_uop_dst_rtype), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_lrs1_rtype (_lsu_io_core_lxcpt_bits_uop_lrs1_rtype), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_lrs2_rtype (_lsu_io_core_lxcpt_bits_uop_lrs2_rtype), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_frs3_en (_lsu_io_core_lxcpt_bits_uop_frs3_en), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_fp_val (_lsu_io_core_lxcpt_bits_uop_fp_val), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_fp_single (_lsu_io_core_lxcpt_bits_uop_fp_single), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_xcpt_pf_if (_lsu_io_core_lxcpt_bits_uop_xcpt_pf_if), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_xcpt_ae_if (_lsu_io_core_lxcpt_bits_uop_xcpt_ae_if), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_xcpt_ma_if (_lsu_io_core_lxcpt_bits_uop_xcpt_ma_if), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_bp_debug_if (_lsu_io_core_lxcpt_bits_uop_bp_debug_if), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_bp_xcpt_if (_lsu_io_core_lxcpt_bits_uop_bp_xcpt_if), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_debug_fsrc (_lsu_io_core_lxcpt_bits_uop_debug_fsrc), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_debug_tsrc (_lsu_io_core_lxcpt_bits_uop_debug_tsrc), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_cause (_lsu_io_core_lxcpt_bits_cause), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_badvaddr (_lsu_io_core_lxcpt_bits_badvaddr), // @[tile.scala:160:20]
.io_lsu_tsc_reg (_core_io_lsu_tsc_reg),
.io_lsu_perf_acquire (_lsu_io_core_perf_acquire), // @[tile.scala:160:20]
.io_lsu_perf_release (_lsu_io_core_perf_release), // @[tile.scala:160:20]
.io_lsu_perf_tlbMiss (_lsu_io_core_perf_tlbMiss), // @[tile.scala:160:20]
.io_ptw_tlb_req_ready (_ptw_io_requestor_2_req_ready), // @[tile.scala:237:20]
.io_ptw_tlb_resp_valid (_ptw_io_requestor_2_resp_valid), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_ae_ptw (_ptw_io_requestor_2_resp_bits_ae_ptw), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_ae_final (_ptw_io_requestor_2_resp_bits_ae_final), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_pf (_ptw_io_requestor_2_resp_bits_pf), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_gf (_ptw_io_requestor_2_resp_bits_gf), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_hr (_ptw_io_requestor_2_resp_bits_hr), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_hw (_ptw_io_requestor_2_resp_bits_hw), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_hx (_ptw_io_requestor_2_resp_bits_hx), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_pte_reserved_for_future (_ptw_io_requestor_2_resp_bits_pte_reserved_for_future), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_pte_ppn (_ptw_io_requestor_2_resp_bits_pte_ppn), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_pte_reserved_for_software (_ptw_io_requestor_2_resp_bits_pte_reserved_for_software), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_pte_d (_ptw_io_requestor_2_resp_bits_pte_d), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_pte_a (_ptw_io_requestor_2_resp_bits_pte_a), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_pte_g (_ptw_io_requestor_2_resp_bits_pte_g), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_pte_u (_ptw_io_requestor_2_resp_bits_pte_u), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_pte_x (_ptw_io_requestor_2_resp_bits_pte_x), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_pte_w (_ptw_io_requestor_2_resp_bits_pte_w), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_pte_r (_ptw_io_requestor_2_resp_bits_pte_r), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_pte_v (_ptw_io_requestor_2_resp_bits_pte_v), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_level (_ptw_io_requestor_2_resp_bits_level), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_homogeneous (_ptw_io_requestor_2_resp_bits_homogeneous), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_gpa_valid (_ptw_io_requestor_2_resp_bits_gpa_valid), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_gpa_bits (_ptw_io_requestor_2_resp_bits_gpa_bits), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_gpa_is_pte (_ptw_io_requestor_2_resp_bits_gpa_is_pte), // @[tile.scala:237:20]
.io_ptw_tlb_ptbr_mode (_ptw_io_requestor_2_ptbr_mode), // @[tile.scala:237:20]
.io_ptw_tlb_ptbr_ppn (_ptw_io_requestor_2_ptbr_ppn), // @[tile.scala:237:20]
.io_ptw_tlb_status_debug (_ptw_io_requestor_2_status_debug), // @[tile.scala:237:20]
.io_ptw_tlb_status_cease (_ptw_io_requestor_2_status_cease), // @[tile.scala:237:20]
.io_ptw_tlb_status_wfi (_ptw_io_requestor_2_status_wfi), // @[tile.scala:237:20]
.io_ptw_tlb_status_dprv (_ptw_io_requestor_2_status_dprv), // @[tile.scala:237:20]
.io_ptw_tlb_status_dv (_ptw_io_requestor_2_status_dv), // @[tile.scala:237:20]
.io_ptw_tlb_status_prv (_ptw_io_requestor_2_status_prv), // @[tile.scala:237:20]
.io_ptw_tlb_status_v (_ptw_io_requestor_2_status_v), // @[tile.scala:237:20]
.io_ptw_tlb_status_sd (_ptw_io_requestor_2_status_sd), // @[tile.scala:237:20]
.io_ptw_tlb_status_mpv (_ptw_io_requestor_2_status_mpv), // @[tile.scala:237:20]
.io_ptw_tlb_status_gva (_ptw_io_requestor_2_status_gva), // @[tile.scala:237:20]
.io_ptw_tlb_status_tsr (_ptw_io_requestor_2_status_tsr), // @[tile.scala:237:20]
.io_ptw_tlb_status_tw (_ptw_io_requestor_2_status_tw), // @[tile.scala:237:20]
.io_ptw_tlb_status_tvm (_ptw_io_requestor_2_status_tvm), // @[tile.scala:237:20]
.io_ptw_tlb_status_mxr (_ptw_io_requestor_2_status_mxr), // @[tile.scala:237:20]
.io_ptw_tlb_status_sum (_ptw_io_requestor_2_status_sum), // @[tile.scala:237:20]
.io_ptw_tlb_status_mprv (_ptw_io_requestor_2_status_mprv), // @[tile.scala:237:20]
.io_ptw_tlb_status_fs (_ptw_io_requestor_2_status_fs), // @[tile.scala:237:20]
.io_ptw_tlb_status_mpp (_ptw_io_requestor_2_status_mpp), // @[tile.scala:237:20]
.io_ptw_tlb_status_spp (_ptw_io_requestor_2_status_spp), // @[tile.scala:237:20]
.io_ptw_tlb_status_mpie (_ptw_io_requestor_2_status_mpie), // @[tile.scala:237:20]
.io_ptw_tlb_status_spie (_ptw_io_requestor_2_status_spie), // @[tile.scala:237:20]
.io_ptw_tlb_status_mie (_ptw_io_requestor_2_status_mie), // @[tile.scala:237:20]
.io_ptw_tlb_status_sie (_ptw_io_requestor_2_status_sie), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_0_cfg_l (_ptw_io_requestor_2_pmp_0_cfg_l), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_0_cfg_a (_ptw_io_requestor_2_pmp_0_cfg_a), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_0_cfg_x (_ptw_io_requestor_2_pmp_0_cfg_x), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_0_cfg_w (_ptw_io_requestor_2_pmp_0_cfg_w), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_0_cfg_r (_ptw_io_requestor_2_pmp_0_cfg_r), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_0_addr (_ptw_io_requestor_2_pmp_0_addr), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_0_mask (_ptw_io_requestor_2_pmp_0_mask), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_1_cfg_l (_ptw_io_requestor_2_pmp_1_cfg_l), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_1_cfg_a (_ptw_io_requestor_2_pmp_1_cfg_a), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_1_cfg_x (_ptw_io_requestor_2_pmp_1_cfg_x), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_1_cfg_w (_ptw_io_requestor_2_pmp_1_cfg_w), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_1_cfg_r (_ptw_io_requestor_2_pmp_1_cfg_r), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_1_addr (_ptw_io_requestor_2_pmp_1_addr), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_1_mask (_ptw_io_requestor_2_pmp_1_mask), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_2_cfg_l (_ptw_io_requestor_2_pmp_2_cfg_l), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_2_cfg_a (_ptw_io_requestor_2_pmp_2_cfg_a), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_2_cfg_x (_ptw_io_requestor_2_pmp_2_cfg_x), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_2_cfg_w (_ptw_io_requestor_2_pmp_2_cfg_w), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_2_cfg_r (_ptw_io_requestor_2_pmp_2_cfg_r), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_2_addr (_ptw_io_requestor_2_pmp_2_addr), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_2_mask (_ptw_io_requestor_2_pmp_2_mask), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_3_cfg_l (_ptw_io_requestor_2_pmp_3_cfg_l), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_3_cfg_a (_ptw_io_requestor_2_pmp_3_cfg_a), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_3_cfg_x (_ptw_io_requestor_2_pmp_3_cfg_x), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_3_cfg_w (_ptw_io_requestor_2_pmp_3_cfg_w), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_3_cfg_r (_ptw_io_requestor_2_pmp_3_cfg_r), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_3_addr (_ptw_io_requestor_2_pmp_3_addr), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_3_mask (_ptw_io_requestor_2_pmp_3_mask), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_4_cfg_l (_ptw_io_requestor_2_pmp_4_cfg_l), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_4_cfg_a (_ptw_io_requestor_2_pmp_4_cfg_a), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_4_cfg_x (_ptw_io_requestor_2_pmp_4_cfg_x), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_4_cfg_w (_ptw_io_requestor_2_pmp_4_cfg_w), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_4_cfg_r (_ptw_io_requestor_2_pmp_4_cfg_r), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_4_addr (_ptw_io_requestor_2_pmp_4_addr), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_4_mask (_ptw_io_requestor_2_pmp_4_mask), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_5_cfg_l (_ptw_io_requestor_2_pmp_5_cfg_l), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_5_cfg_a (_ptw_io_requestor_2_pmp_5_cfg_a), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_5_cfg_x (_ptw_io_requestor_2_pmp_5_cfg_x), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_5_cfg_w (_ptw_io_requestor_2_pmp_5_cfg_w), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_5_cfg_r (_ptw_io_requestor_2_pmp_5_cfg_r), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_5_addr (_ptw_io_requestor_2_pmp_5_addr), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_5_mask (_ptw_io_requestor_2_pmp_5_mask), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_6_cfg_l (_ptw_io_requestor_2_pmp_6_cfg_l), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_6_cfg_a (_ptw_io_requestor_2_pmp_6_cfg_a), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_6_cfg_x (_ptw_io_requestor_2_pmp_6_cfg_x), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_6_cfg_w (_ptw_io_requestor_2_pmp_6_cfg_w), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_6_cfg_r (_ptw_io_requestor_2_pmp_6_cfg_r), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_6_addr (_ptw_io_requestor_2_pmp_6_addr), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_6_mask (_ptw_io_requestor_2_pmp_6_mask), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_7_cfg_l (_ptw_io_requestor_2_pmp_7_cfg_l), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_7_cfg_a (_ptw_io_requestor_2_pmp_7_cfg_a), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_7_cfg_x (_ptw_io_requestor_2_pmp_7_cfg_x), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_7_cfg_w (_ptw_io_requestor_2_pmp_7_cfg_w), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_7_cfg_r (_ptw_io_requestor_2_pmp_7_cfg_r), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_7_addr (_ptw_io_requestor_2_pmp_7_addr), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_7_mask (_ptw_io_requestor_2_pmp_7_mask), // @[tile.scala:237:20]
.io_trace_time (traceSourceNodeOut_time),
.io_trace_custom_rob_empty (traceSourceNodeOut_custom_rob_empty)
); // @[tile.scala:159:20]
LSU_1 lsu ( // @[tile.scala:160:20]
.clock (clock),
.reset (reset),
.io_ptw_req_ready (_ptw_io_requestor_0_req_ready), // @[tile.scala:237:20]
.io_ptw_req_valid (_lsu_io_ptw_req_valid),
.io_ptw_req_bits_valid (_lsu_io_ptw_req_bits_valid),
.io_ptw_req_bits_bits_addr (_lsu_io_ptw_req_bits_bits_addr),
.io_ptw_resp_valid (_ptw_io_requestor_0_resp_valid), // @[tile.scala:237:20]
.io_ptw_resp_bits_ae_ptw (_ptw_io_requestor_0_resp_bits_ae_ptw), // @[tile.scala:237:20]
.io_ptw_resp_bits_ae_final (_ptw_io_requestor_0_resp_bits_ae_final), // @[tile.scala:237:20]
.io_ptw_resp_bits_pf (_ptw_io_requestor_0_resp_bits_pf), // @[tile.scala:237:20]
.io_ptw_resp_bits_gf (_ptw_io_requestor_0_resp_bits_gf), // @[tile.scala:237:20]
.io_ptw_resp_bits_hr (_ptw_io_requestor_0_resp_bits_hr), // @[tile.scala:237:20]
.io_ptw_resp_bits_hw (_ptw_io_requestor_0_resp_bits_hw), // @[tile.scala:237:20]
.io_ptw_resp_bits_hx (_ptw_io_requestor_0_resp_bits_hx), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_reserved_for_future (_ptw_io_requestor_0_resp_bits_pte_reserved_for_future), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_ppn (_ptw_io_requestor_0_resp_bits_pte_ppn), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_reserved_for_software (_ptw_io_requestor_0_resp_bits_pte_reserved_for_software), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_d (_ptw_io_requestor_0_resp_bits_pte_d), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_a (_ptw_io_requestor_0_resp_bits_pte_a), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_g (_ptw_io_requestor_0_resp_bits_pte_g), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_u (_ptw_io_requestor_0_resp_bits_pte_u), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_x (_ptw_io_requestor_0_resp_bits_pte_x), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_w (_ptw_io_requestor_0_resp_bits_pte_w), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_r (_ptw_io_requestor_0_resp_bits_pte_r), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_v (_ptw_io_requestor_0_resp_bits_pte_v), // @[tile.scala:237:20]
.io_ptw_resp_bits_level (_ptw_io_requestor_0_resp_bits_level), // @[tile.scala:237:20]
.io_ptw_resp_bits_homogeneous (_ptw_io_requestor_0_resp_bits_homogeneous), // @[tile.scala:237:20]
.io_ptw_resp_bits_gpa_valid (_ptw_io_requestor_0_resp_bits_gpa_valid), // @[tile.scala:237:20]
.io_ptw_resp_bits_gpa_bits (_ptw_io_requestor_0_resp_bits_gpa_bits), // @[tile.scala:237:20]
.io_ptw_resp_bits_gpa_is_pte (_ptw_io_requestor_0_resp_bits_gpa_is_pte), // @[tile.scala:237:20]
.io_ptw_ptbr_mode (_ptw_io_requestor_0_ptbr_mode), // @[tile.scala:237:20]
.io_ptw_ptbr_ppn (_ptw_io_requestor_0_ptbr_ppn), // @[tile.scala:237:20]
.io_ptw_status_debug (_ptw_io_requestor_0_status_debug), // @[tile.scala:237:20]
.io_ptw_status_cease (_ptw_io_requestor_0_status_cease), // @[tile.scala:237:20]
.io_ptw_status_wfi (_ptw_io_requestor_0_status_wfi), // @[tile.scala:237:20]
.io_ptw_status_dprv (_ptw_io_requestor_0_status_dprv), // @[tile.scala:237:20]
.io_ptw_status_dv (_ptw_io_requestor_0_status_dv), // @[tile.scala:237:20]
.io_ptw_status_prv (_ptw_io_requestor_0_status_prv), // @[tile.scala:237:20]
.io_ptw_status_v (_ptw_io_requestor_0_status_v), // @[tile.scala:237:20]
.io_ptw_status_sd (_ptw_io_requestor_0_status_sd), // @[tile.scala:237:20]
.io_ptw_status_mpv (_ptw_io_requestor_0_status_mpv), // @[tile.scala:237:20]
.io_ptw_status_gva (_ptw_io_requestor_0_status_gva), // @[tile.scala:237:20]
.io_ptw_status_tsr (_ptw_io_requestor_0_status_tsr), // @[tile.scala:237:20]
.io_ptw_status_tw (_ptw_io_requestor_0_status_tw), // @[tile.scala:237:20]
.io_ptw_status_tvm (_ptw_io_requestor_0_status_tvm), // @[tile.scala:237:20]
.io_ptw_status_mxr (_ptw_io_requestor_0_status_mxr), // @[tile.scala:237:20]
.io_ptw_status_sum (_ptw_io_requestor_0_status_sum), // @[tile.scala:237:20]
.io_ptw_status_mprv (_ptw_io_requestor_0_status_mprv), // @[tile.scala:237:20]
.io_ptw_status_fs (_ptw_io_requestor_0_status_fs), // @[tile.scala:237:20]
.io_ptw_status_mpp (_ptw_io_requestor_0_status_mpp), // @[tile.scala:237:20]
.io_ptw_status_spp (_ptw_io_requestor_0_status_spp), // @[tile.scala:237:20]
.io_ptw_status_mpie (_ptw_io_requestor_0_status_mpie), // @[tile.scala:237:20]
.io_ptw_status_spie (_ptw_io_requestor_0_status_spie), // @[tile.scala:237:20]
.io_ptw_status_mie (_ptw_io_requestor_0_status_mie), // @[tile.scala:237:20]
.io_ptw_status_sie (_ptw_io_requestor_0_status_sie), // @[tile.scala:237:20]
.io_ptw_pmp_0_cfg_l (_ptw_io_requestor_0_pmp_0_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_0_cfg_a (_ptw_io_requestor_0_pmp_0_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_0_cfg_x (_ptw_io_requestor_0_pmp_0_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_0_cfg_w (_ptw_io_requestor_0_pmp_0_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_0_cfg_r (_ptw_io_requestor_0_pmp_0_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_0_addr (_ptw_io_requestor_0_pmp_0_addr), // @[tile.scala:237:20]
.io_ptw_pmp_0_mask (_ptw_io_requestor_0_pmp_0_mask), // @[tile.scala:237:20]
.io_ptw_pmp_1_cfg_l (_ptw_io_requestor_0_pmp_1_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_1_cfg_a (_ptw_io_requestor_0_pmp_1_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_1_cfg_x (_ptw_io_requestor_0_pmp_1_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_1_cfg_w (_ptw_io_requestor_0_pmp_1_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_1_cfg_r (_ptw_io_requestor_0_pmp_1_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_1_addr (_ptw_io_requestor_0_pmp_1_addr), // @[tile.scala:237:20]
.io_ptw_pmp_1_mask (_ptw_io_requestor_0_pmp_1_mask), // @[tile.scala:237:20]
.io_ptw_pmp_2_cfg_l (_ptw_io_requestor_0_pmp_2_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_2_cfg_a (_ptw_io_requestor_0_pmp_2_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_2_cfg_x (_ptw_io_requestor_0_pmp_2_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_2_cfg_w (_ptw_io_requestor_0_pmp_2_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_2_cfg_r (_ptw_io_requestor_0_pmp_2_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_2_addr (_ptw_io_requestor_0_pmp_2_addr), // @[tile.scala:237:20]
.io_ptw_pmp_2_mask (_ptw_io_requestor_0_pmp_2_mask), // @[tile.scala:237:20]
.io_ptw_pmp_3_cfg_l (_ptw_io_requestor_0_pmp_3_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_3_cfg_a (_ptw_io_requestor_0_pmp_3_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_3_cfg_x (_ptw_io_requestor_0_pmp_3_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_3_cfg_w (_ptw_io_requestor_0_pmp_3_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_3_cfg_r (_ptw_io_requestor_0_pmp_3_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_3_addr (_ptw_io_requestor_0_pmp_3_addr), // @[tile.scala:237:20]
.io_ptw_pmp_3_mask (_ptw_io_requestor_0_pmp_3_mask), // @[tile.scala:237:20]
.io_ptw_pmp_4_cfg_l (_ptw_io_requestor_0_pmp_4_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_4_cfg_a (_ptw_io_requestor_0_pmp_4_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_4_cfg_x (_ptw_io_requestor_0_pmp_4_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_4_cfg_w (_ptw_io_requestor_0_pmp_4_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_4_cfg_r (_ptw_io_requestor_0_pmp_4_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_4_addr (_ptw_io_requestor_0_pmp_4_addr), // @[tile.scala:237:20]
.io_ptw_pmp_4_mask (_ptw_io_requestor_0_pmp_4_mask), // @[tile.scala:237:20]
.io_ptw_pmp_5_cfg_l (_ptw_io_requestor_0_pmp_5_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_5_cfg_a (_ptw_io_requestor_0_pmp_5_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_5_cfg_x (_ptw_io_requestor_0_pmp_5_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_5_cfg_w (_ptw_io_requestor_0_pmp_5_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_5_cfg_r (_ptw_io_requestor_0_pmp_5_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_5_addr (_ptw_io_requestor_0_pmp_5_addr), // @[tile.scala:237:20]
.io_ptw_pmp_5_mask (_ptw_io_requestor_0_pmp_5_mask), // @[tile.scala:237:20]
.io_ptw_pmp_6_cfg_l (_ptw_io_requestor_0_pmp_6_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_6_cfg_a (_ptw_io_requestor_0_pmp_6_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_6_cfg_x (_ptw_io_requestor_0_pmp_6_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_6_cfg_w (_ptw_io_requestor_0_pmp_6_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_6_cfg_r (_ptw_io_requestor_0_pmp_6_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_6_addr (_ptw_io_requestor_0_pmp_6_addr), // @[tile.scala:237:20]
.io_ptw_pmp_6_mask (_ptw_io_requestor_0_pmp_6_mask), // @[tile.scala:237:20]
.io_ptw_pmp_7_cfg_l (_ptw_io_requestor_0_pmp_7_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_7_cfg_a (_ptw_io_requestor_0_pmp_7_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_7_cfg_x (_ptw_io_requestor_0_pmp_7_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_7_cfg_w (_ptw_io_requestor_0_pmp_7_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_7_cfg_r (_ptw_io_requestor_0_pmp_7_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_7_addr (_ptw_io_requestor_0_pmp_7_addr), // @[tile.scala:237:20]
.io_ptw_pmp_7_mask (_ptw_io_requestor_0_pmp_7_mask), // @[tile.scala:237:20]
.io_core_exe_0_req_valid (_core_io_lsu_exe_0_req_valid), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_uopc (_core_io_lsu_exe_0_req_bits_uop_uopc), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_inst (_core_io_lsu_exe_0_req_bits_uop_inst), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_debug_inst (_core_io_lsu_exe_0_req_bits_uop_debug_inst), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_is_rvc (_core_io_lsu_exe_0_req_bits_uop_is_rvc), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_debug_pc (_core_io_lsu_exe_0_req_bits_uop_debug_pc), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_iq_type (_core_io_lsu_exe_0_req_bits_uop_iq_type), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_fu_code (_core_io_lsu_exe_0_req_bits_uop_fu_code), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ctrl_br_type (_core_io_lsu_exe_0_req_bits_uop_ctrl_br_type), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ctrl_op1_sel (_core_io_lsu_exe_0_req_bits_uop_ctrl_op1_sel), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ctrl_op2_sel (_core_io_lsu_exe_0_req_bits_uop_ctrl_op2_sel), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ctrl_imm_sel (_core_io_lsu_exe_0_req_bits_uop_ctrl_imm_sel), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ctrl_op_fcn (_core_io_lsu_exe_0_req_bits_uop_ctrl_op_fcn), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ctrl_fcn_dw (_core_io_lsu_exe_0_req_bits_uop_ctrl_fcn_dw), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ctrl_csr_cmd (_core_io_lsu_exe_0_req_bits_uop_ctrl_csr_cmd), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ctrl_is_load (_core_io_lsu_exe_0_req_bits_uop_ctrl_is_load), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ctrl_is_sta (_core_io_lsu_exe_0_req_bits_uop_ctrl_is_sta), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ctrl_is_std (_core_io_lsu_exe_0_req_bits_uop_ctrl_is_std), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_iw_state (_core_io_lsu_exe_0_req_bits_uop_iw_state), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_iw_p1_poisoned (_core_io_lsu_exe_0_req_bits_uop_iw_p1_poisoned), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_iw_p2_poisoned (_core_io_lsu_exe_0_req_bits_uop_iw_p2_poisoned), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_is_br (_core_io_lsu_exe_0_req_bits_uop_is_br), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_is_jalr (_core_io_lsu_exe_0_req_bits_uop_is_jalr), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_is_jal (_core_io_lsu_exe_0_req_bits_uop_is_jal), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_is_sfb (_core_io_lsu_exe_0_req_bits_uop_is_sfb), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_br_mask (_core_io_lsu_exe_0_req_bits_uop_br_mask), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_br_tag (_core_io_lsu_exe_0_req_bits_uop_br_tag), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ftq_idx (_core_io_lsu_exe_0_req_bits_uop_ftq_idx), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_edge_inst (_core_io_lsu_exe_0_req_bits_uop_edge_inst), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_pc_lob (_core_io_lsu_exe_0_req_bits_uop_pc_lob), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_taken (_core_io_lsu_exe_0_req_bits_uop_taken), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_imm_packed (_core_io_lsu_exe_0_req_bits_uop_imm_packed), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_csr_addr (_core_io_lsu_exe_0_req_bits_uop_csr_addr), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_rob_idx (_core_io_lsu_exe_0_req_bits_uop_rob_idx), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ldq_idx (_core_io_lsu_exe_0_req_bits_uop_ldq_idx), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_stq_idx (_core_io_lsu_exe_0_req_bits_uop_stq_idx), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_rxq_idx (_core_io_lsu_exe_0_req_bits_uop_rxq_idx), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_pdst (_core_io_lsu_exe_0_req_bits_uop_pdst), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_prs1 (_core_io_lsu_exe_0_req_bits_uop_prs1), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_prs2 (_core_io_lsu_exe_0_req_bits_uop_prs2), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_prs3 (_core_io_lsu_exe_0_req_bits_uop_prs3), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ppred (_core_io_lsu_exe_0_req_bits_uop_ppred), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_prs1_busy (_core_io_lsu_exe_0_req_bits_uop_prs1_busy), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_prs2_busy (_core_io_lsu_exe_0_req_bits_uop_prs2_busy), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_prs3_busy (_core_io_lsu_exe_0_req_bits_uop_prs3_busy), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ppred_busy (_core_io_lsu_exe_0_req_bits_uop_ppred_busy), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_stale_pdst (_core_io_lsu_exe_0_req_bits_uop_stale_pdst), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_exception (_core_io_lsu_exe_0_req_bits_uop_exception), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_exc_cause (_core_io_lsu_exe_0_req_bits_uop_exc_cause), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_bypassable (_core_io_lsu_exe_0_req_bits_uop_bypassable), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_mem_cmd (_core_io_lsu_exe_0_req_bits_uop_mem_cmd), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_mem_size (_core_io_lsu_exe_0_req_bits_uop_mem_size), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_mem_signed (_core_io_lsu_exe_0_req_bits_uop_mem_signed), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_is_fence (_core_io_lsu_exe_0_req_bits_uop_is_fence), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_is_fencei (_core_io_lsu_exe_0_req_bits_uop_is_fencei), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_is_amo (_core_io_lsu_exe_0_req_bits_uop_is_amo), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_uses_ldq (_core_io_lsu_exe_0_req_bits_uop_uses_ldq), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_uses_stq (_core_io_lsu_exe_0_req_bits_uop_uses_stq), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_is_sys_pc2epc (_core_io_lsu_exe_0_req_bits_uop_is_sys_pc2epc), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_is_unique (_core_io_lsu_exe_0_req_bits_uop_is_unique), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_flush_on_commit (_core_io_lsu_exe_0_req_bits_uop_flush_on_commit), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ldst_is_rs1 (_core_io_lsu_exe_0_req_bits_uop_ldst_is_rs1), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ldst (_core_io_lsu_exe_0_req_bits_uop_ldst), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_lrs1 (_core_io_lsu_exe_0_req_bits_uop_lrs1), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_lrs2 (_core_io_lsu_exe_0_req_bits_uop_lrs2), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_lrs3 (_core_io_lsu_exe_0_req_bits_uop_lrs3), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ldst_val (_core_io_lsu_exe_0_req_bits_uop_ldst_val), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_dst_rtype (_core_io_lsu_exe_0_req_bits_uop_dst_rtype), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_lrs1_rtype (_core_io_lsu_exe_0_req_bits_uop_lrs1_rtype), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_lrs2_rtype (_core_io_lsu_exe_0_req_bits_uop_lrs2_rtype), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_frs3_en (_core_io_lsu_exe_0_req_bits_uop_frs3_en), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_fp_val (_core_io_lsu_exe_0_req_bits_uop_fp_val), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_fp_single (_core_io_lsu_exe_0_req_bits_uop_fp_single), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_xcpt_pf_if (_core_io_lsu_exe_0_req_bits_uop_xcpt_pf_if), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_xcpt_ae_if (_core_io_lsu_exe_0_req_bits_uop_xcpt_ae_if), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_xcpt_ma_if (_core_io_lsu_exe_0_req_bits_uop_xcpt_ma_if), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_bp_debug_if (_core_io_lsu_exe_0_req_bits_uop_bp_debug_if), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_bp_xcpt_if (_core_io_lsu_exe_0_req_bits_uop_bp_xcpt_if), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_debug_fsrc (_core_io_lsu_exe_0_req_bits_uop_debug_fsrc), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_debug_tsrc (_core_io_lsu_exe_0_req_bits_uop_debug_tsrc), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_data (_core_io_lsu_exe_0_req_bits_data), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_addr (_core_io_lsu_exe_0_req_bits_addr), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_mxcpt_valid (_core_io_lsu_exe_0_req_bits_mxcpt_valid), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_mxcpt_bits (_core_io_lsu_exe_0_req_bits_mxcpt_bits), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_sfence_valid (_core_io_lsu_exe_0_req_bits_sfence_valid), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_sfence_bits_rs1 (_core_io_lsu_exe_0_req_bits_sfence_bits_rs1), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_sfence_bits_rs2 (_core_io_lsu_exe_0_req_bits_sfence_bits_rs2), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_sfence_bits_addr (_core_io_lsu_exe_0_req_bits_sfence_bits_addr), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_sfence_bits_asid (_core_io_lsu_exe_0_req_bits_sfence_bits_asid), // @[tile.scala:159:20]
.io_core_exe_0_iresp_valid (_lsu_io_core_exe_0_iresp_valid),
.io_core_exe_0_iresp_bits_uop_uopc (_lsu_io_core_exe_0_iresp_bits_uop_uopc),
.io_core_exe_0_iresp_bits_uop_inst (_lsu_io_core_exe_0_iresp_bits_uop_inst),
.io_core_exe_0_iresp_bits_uop_debug_inst (_lsu_io_core_exe_0_iresp_bits_uop_debug_inst),
.io_core_exe_0_iresp_bits_uop_is_rvc (_lsu_io_core_exe_0_iresp_bits_uop_is_rvc),
.io_core_exe_0_iresp_bits_uop_debug_pc (_lsu_io_core_exe_0_iresp_bits_uop_debug_pc),
.io_core_exe_0_iresp_bits_uop_iq_type (_lsu_io_core_exe_0_iresp_bits_uop_iq_type),
.io_core_exe_0_iresp_bits_uop_fu_code (_lsu_io_core_exe_0_iresp_bits_uop_fu_code),
.io_core_exe_0_iresp_bits_uop_ctrl_br_type (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_br_type),
.io_core_exe_0_iresp_bits_uop_ctrl_op1_sel (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_op1_sel),
.io_core_exe_0_iresp_bits_uop_ctrl_op2_sel (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_op2_sel),
.io_core_exe_0_iresp_bits_uop_ctrl_imm_sel (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_imm_sel),
.io_core_exe_0_iresp_bits_uop_ctrl_op_fcn (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_op_fcn),
.io_core_exe_0_iresp_bits_uop_ctrl_fcn_dw (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_fcn_dw),
.io_core_exe_0_iresp_bits_uop_ctrl_csr_cmd (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_csr_cmd),
.io_core_exe_0_iresp_bits_uop_ctrl_is_load (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_is_load),
.io_core_exe_0_iresp_bits_uop_ctrl_is_sta (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_is_sta),
.io_core_exe_0_iresp_bits_uop_ctrl_is_std (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_is_std),
.io_core_exe_0_iresp_bits_uop_iw_state (_lsu_io_core_exe_0_iresp_bits_uop_iw_state),
.io_core_exe_0_iresp_bits_uop_iw_p1_poisoned (_lsu_io_core_exe_0_iresp_bits_uop_iw_p1_poisoned),
.io_core_exe_0_iresp_bits_uop_iw_p2_poisoned (_lsu_io_core_exe_0_iresp_bits_uop_iw_p2_poisoned),
.io_core_exe_0_iresp_bits_uop_is_br (_lsu_io_core_exe_0_iresp_bits_uop_is_br),
.io_core_exe_0_iresp_bits_uop_is_jalr (_lsu_io_core_exe_0_iresp_bits_uop_is_jalr),
.io_core_exe_0_iresp_bits_uop_is_jal (_lsu_io_core_exe_0_iresp_bits_uop_is_jal),
.io_core_exe_0_iresp_bits_uop_is_sfb (_lsu_io_core_exe_0_iresp_bits_uop_is_sfb),
.io_core_exe_0_iresp_bits_uop_br_mask (_lsu_io_core_exe_0_iresp_bits_uop_br_mask),
.io_core_exe_0_iresp_bits_uop_br_tag (_lsu_io_core_exe_0_iresp_bits_uop_br_tag),
.io_core_exe_0_iresp_bits_uop_ftq_idx (_lsu_io_core_exe_0_iresp_bits_uop_ftq_idx),
.io_core_exe_0_iresp_bits_uop_edge_inst (_lsu_io_core_exe_0_iresp_bits_uop_edge_inst),
.io_core_exe_0_iresp_bits_uop_pc_lob (_lsu_io_core_exe_0_iresp_bits_uop_pc_lob),
.io_core_exe_0_iresp_bits_uop_taken (_lsu_io_core_exe_0_iresp_bits_uop_taken),
.io_core_exe_0_iresp_bits_uop_imm_packed (_lsu_io_core_exe_0_iresp_bits_uop_imm_packed),
.io_core_exe_0_iresp_bits_uop_csr_addr (_lsu_io_core_exe_0_iresp_bits_uop_csr_addr),
.io_core_exe_0_iresp_bits_uop_rob_idx (_lsu_io_core_exe_0_iresp_bits_uop_rob_idx),
.io_core_exe_0_iresp_bits_uop_ldq_idx (_lsu_io_core_exe_0_iresp_bits_uop_ldq_idx),
.io_core_exe_0_iresp_bits_uop_stq_idx (_lsu_io_core_exe_0_iresp_bits_uop_stq_idx),
.io_core_exe_0_iresp_bits_uop_rxq_idx (_lsu_io_core_exe_0_iresp_bits_uop_rxq_idx),
.io_core_exe_0_iresp_bits_uop_pdst (_lsu_io_core_exe_0_iresp_bits_uop_pdst),
.io_core_exe_0_iresp_bits_uop_prs1 (_lsu_io_core_exe_0_iresp_bits_uop_prs1),
.io_core_exe_0_iresp_bits_uop_prs2 (_lsu_io_core_exe_0_iresp_bits_uop_prs2),
.io_core_exe_0_iresp_bits_uop_prs3 (_lsu_io_core_exe_0_iresp_bits_uop_prs3),
.io_core_exe_0_iresp_bits_uop_ppred (_lsu_io_core_exe_0_iresp_bits_uop_ppred),
.io_core_exe_0_iresp_bits_uop_prs1_busy (_lsu_io_core_exe_0_iresp_bits_uop_prs1_busy),
.io_core_exe_0_iresp_bits_uop_prs2_busy (_lsu_io_core_exe_0_iresp_bits_uop_prs2_busy),
.io_core_exe_0_iresp_bits_uop_prs3_busy (_lsu_io_core_exe_0_iresp_bits_uop_prs3_busy),
.io_core_exe_0_iresp_bits_uop_ppred_busy (_lsu_io_core_exe_0_iresp_bits_uop_ppred_busy),
.io_core_exe_0_iresp_bits_uop_stale_pdst (_lsu_io_core_exe_0_iresp_bits_uop_stale_pdst),
.io_core_exe_0_iresp_bits_uop_exception (_lsu_io_core_exe_0_iresp_bits_uop_exception),
.io_core_exe_0_iresp_bits_uop_exc_cause (_lsu_io_core_exe_0_iresp_bits_uop_exc_cause),
.io_core_exe_0_iresp_bits_uop_bypassable (_lsu_io_core_exe_0_iresp_bits_uop_bypassable),
.io_core_exe_0_iresp_bits_uop_mem_cmd (_lsu_io_core_exe_0_iresp_bits_uop_mem_cmd),
.io_core_exe_0_iresp_bits_uop_mem_size (_lsu_io_core_exe_0_iresp_bits_uop_mem_size),
.io_core_exe_0_iresp_bits_uop_mem_signed (_lsu_io_core_exe_0_iresp_bits_uop_mem_signed),
.io_core_exe_0_iresp_bits_uop_is_fence (_lsu_io_core_exe_0_iresp_bits_uop_is_fence),
.io_core_exe_0_iresp_bits_uop_is_fencei (_lsu_io_core_exe_0_iresp_bits_uop_is_fencei),
.io_core_exe_0_iresp_bits_uop_is_amo (_lsu_io_core_exe_0_iresp_bits_uop_is_amo),
.io_core_exe_0_iresp_bits_uop_uses_ldq (_lsu_io_core_exe_0_iresp_bits_uop_uses_ldq),
.io_core_exe_0_iresp_bits_uop_uses_stq (_lsu_io_core_exe_0_iresp_bits_uop_uses_stq),
.io_core_exe_0_iresp_bits_uop_is_sys_pc2epc (_lsu_io_core_exe_0_iresp_bits_uop_is_sys_pc2epc),
.io_core_exe_0_iresp_bits_uop_is_unique (_lsu_io_core_exe_0_iresp_bits_uop_is_unique),
.io_core_exe_0_iresp_bits_uop_flush_on_commit (_lsu_io_core_exe_0_iresp_bits_uop_flush_on_commit),
.io_core_exe_0_iresp_bits_uop_ldst_is_rs1 (_lsu_io_core_exe_0_iresp_bits_uop_ldst_is_rs1),
.io_core_exe_0_iresp_bits_uop_ldst (_lsu_io_core_exe_0_iresp_bits_uop_ldst),
.io_core_exe_0_iresp_bits_uop_lrs1 (_lsu_io_core_exe_0_iresp_bits_uop_lrs1),
.io_core_exe_0_iresp_bits_uop_lrs2 (_lsu_io_core_exe_0_iresp_bits_uop_lrs2),
.io_core_exe_0_iresp_bits_uop_lrs3 (_lsu_io_core_exe_0_iresp_bits_uop_lrs3),
.io_core_exe_0_iresp_bits_uop_ldst_val (_lsu_io_core_exe_0_iresp_bits_uop_ldst_val),
.io_core_exe_0_iresp_bits_uop_dst_rtype (_lsu_io_core_exe_0_iresp_bits_uop_dst_rtype),
.io_core_exe_0_iresp_bits_uop_lrs1_rtype (_lsu_io_core_exe_0_iresp_bits_uop_lrs1_rtype),
.io_core_exe_0_iresp_bits_uop_lrs2_rtype (_lsu_io_core_exe_0_iresp_bits_uop_lrs2_rtype),
.io_core_exe_0_iresp_bits_uop_frs3_en (_lsu_io_core_exe_0_iresp_bits_uop_frs3_en),
.io_core_exe_0_iresp_bits_uop_fp_val (_lsu_io_core_exe_0_iresp_bits_uop_fp_val),
.io_core_exe_0_iresp_bits_uop_fp_single (_lsu_io_core_exe_0_iresp_bits_uop_fp_single),
.io_core_exe_0_iresp_bits_uop_xcpt_pf_if (_lsu_io_core_exe_0_iresp_bits_uop_xcpt_pf_if),
.io_core_exe_0_iresp_bits_uop_xcpt_ae_if (_lsu_io_core_exe_0_iresp_bits_uop_xcpt_ae_if),
.io_core_exe_0_iresp_bits_uop_xcpt_ma_if (_lsu_io_core_exe_0_iresp_bits_uop_xcpt_ma_if),
.io_core_exe_0_iresp_bits_uop_bp_debug_if (_lsu_io_core_exe_0_iresp_bits_uop_bp_debug_if),
.io_core_exe_0_iresp_bits_uop_bp_xcpt_if (_lsu_io_core_exe_0_iresp_bits_uop_bp_xcpt_if),
.io_core_exe_0_iresp_bits_uop_debug_fsrc (_lsu_io_core_exe_0_iresp_bits_uop_debug_fsrc),
.io_core_exe_0_iresp_bits_uop_debug_tsrc (_lsu_io_core_exe_0_iresp_bits_uop_debug_tsrc),
.io_core_exe_0_iresp_bits_data (_lsu_io_core_exe_0_iresp_bits_data),
.io_core_exe_0_fresp_valid (_lsu_io_core_exe_0_fresp_valid),
.io_core_exe_0_fresp_bits_uop_uopc (_lsu_io_core_exe_0_fresp_bits_uop_uopc),
.io_core_exe_0_fresp_bits_uop_inst (_lsu_io_core_exe_0_fresp_bits_uop_inst),
.io_core_exe_0_fresp_bits_uop_debug_inst (_lsu_io_core_exe_0_fresp_bits_uop_debug_inst),
.io_core_exe_0_fresp_bits_uop_is_rvc (_lsu_io_core_exe_0_fresp_bits_uop_is_rvc),
.io_core_exe_0_fresp_bits_uop_debug_pc (_lsu_io_core_exe_0_fresp_bits_uop_debug_pc),
.io_core_exe_0_fresp_bits_uop_iq_type (_lsu_io_core_exe_0_fresp_bits_uop_iq_type),
.io_core_exe_0_fresp_bits_uop_fu_code (_lsu_io_core_exe_0_fresp_bits_uop_fu_code),
.io_core_exe_0_fresp_bits_uop_ctrl_br_type (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_br_type),
.io_core_exe_0_fresp_bits_uop_ctrl_op1_sel (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_op1_sel),
.io_core_exe_0_fresp_bits_uop_ctrl_op2_sel (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_op2_sel),
.io_core_exe_0_fresp_bits_uop_ctrl_imm_sel (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_imm_sel),
.io_core_exe_0_fresp_bits_uop_ctrl_op_fcn (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_op_fcn),
.io_core_exe_0_fresp_bits_uop_ctrl_fcn_dw (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_fcn_dw),
.io_core_exe_0_fresp_bits_uop_ctrl_csr_cmd (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_csr_cmd),
.io_core_exe_0_fresp_bits_uop_ctrl_is_load (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_is_load),
.io_core_exe_0_fresp_bits_uop_ctrl_is_sta (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_is_sta),
.io_core_exe_0_fresp_bits_uop_ctrl_is_std (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_is_std),
.io_core_exe_0_fresp_bits_uop_iw_state (_lsu_io_core_exe_0_fresp_bits_uop_iw_state),
.io_core_exe_0_fresp_bits_uop_iw_p1_poisoned (_lsu_io_core_exe_0_fresp_bits_uop_iw_p1_poisoned),
.io_core_exe_0_fresp_bits_uop_iw_p2_poisoned (_lsu_io_core_exe_0_fresp_bits_uop_iw_p2_poisoned),
.io_core_exe_0_fresp_bits_uop_is_br (_lsu_io_core_exe_0_fresp_bits_uop_is_br),
.io_core_exe_0_fresp_bits_uop_is_jalr (_lsu_io_core_exe_0_fresp_bits_uop_is_jalr),
.io_core_exe_0_fresp_bits_uop_is_jal (_lsu_io_core_exe_0_fresp_bits_uop_is_jal),
.io_core_exe_0_fresp_bits_uop_is_sfb (_lsu_io_core_exe_0_fresp_bits_uop_is_sfb),
.io_core_exe_0_fresp_bits_uop_br_mask (_lsu_io_core_exe_0_fresp_bits_uop_br_mask),
.io_core_exe_0_fresp_bits_uop_br_tag (_lsu_io_core_exe_0_fresp_bits_uop_br_tag),
.io_core_exe_0_fresp_bits_uop_ftq_idx (_lsu_io_core_exe_0_fresp_bits_uop_ftq_idx),
.io_core_exe_0_fresp_bits_uop_edge_inst (_lsu_io_core_exe_0_fresp_bits_uop_edge_inst),
.io_core_exe_0_fresp_bits_uop_pc_lob (_lsu_io_core_exe_0_fresp_bits_uop_pc_lob),
.io_core_exe_0_fresp_bits_uop_taken (_lsu_io_core_exe_0_fresp_bits_uop_taken),
.io_core_exe_0_fresp_bits_uop_imm_packed (_lsu_io_core_exe_0_fresp_bits_uop_imm_packed),
.io_core_exe_0_fresp_bits_uop_csr_addr (_lsu_io_core_exe_0_fresp_bits_uop_csr_addr),
.io_core_exe_0_fresp_bits_uop_rob_idx (_lsu_io_core_exe_0_fresp_bits_uop_rob_idx),
.io_core_exe_0_fresp_bits_uop_ldq_idx (_lsu_io_core_exe_0_fresp_bits_uop_ldq_idx),
.io_core_exe_0_fresp_bits_uop_stq_idx (_lsu_io_core_exe_0_fresp_bits_uop_stq_idx),
.io_core_exe_0_fresp_bits_uop_rxq_idx (_lsu_io_core_exe_0_fresp_bits_uop_rxq_idx),
.io_core_exe_0_fresp_bits_uop_pdst (_lsu_io_core_exe_0_fresp_bits_uop_pdst),
.io_core_exe_0_fresp_bits_uop_prs1 (_lsu_io_core_exe_0_fresp_bits_uop_prs1),
.io_core_exe_0_fresp_bits_uop_prs2 (_lsu_io_core_exe_0_fresp_bits_uop_prs2),
.io_core_exe_0_fresp_bits_uop_prs3 (_lsu_io_core_exe_0_fresp_bits_uop_prs3),
.io_core_exe_0_fresp_bits_uop_ppred (_lsu_io_core_exe_0_fresp_bits_uop_ppred),
.io_core_exe_0_fresp_bits_uop_prs1_busy (_lsu_io_core_exe_0_fresp_bits_uop_prs1_busy),
.io_core_exe_0_fresp_bits_uop_prs2_busy (_lsu_io_core_exe_0_fresp_bits_uop_prs2_busy),
.io_core_exe_0_fresp_bits_uop_prs3_busy (_lsu_io_core_exe_0_fresp_bits_uop_prs3_busy),
.io_core_exe_0_fresp_bits_uop_ppred_busy (_lsu_io_core_exe_0_fresp_bits_uop_ppred_busy),
.io_core_exe_0_fresp_bits_uop_stale_pdst (_lsu_io_core_exe_0_fresp_bits_uop_stale_pdst),
.io_core_exe_0_fresp_bits_uop_exception (_lsu_io_core_exe_0_fresp_bits_uop_exception),
.io_core_exe_0_fresp_bits_uop_exc_cause (_lsu_io_core_exe_0_fresp_bits_uop_exc_cause),
.io_core_exe_0_fresp_bits_uop_bypassable (_lsu_io_core_exe_0_fresp_bits_uop_bypassable),
.io_core_exe_0_fresp_bits_uop_mem_cmd (_lsu_io_core_exe_0_fresp_bits_uop_mem_cmd),
.io_core_exe_0_fresp_bits_uop_mem_size (_lsu_io_core_exe_0_fresp_bits_uop_mem_size),
.io_core_exe_0_fresp_bits_uop_mem_signed (_lsu_io_core_exe_0_fresp_bits_uop_mem_signed),
.io_core_exe_0_fresp_bits_uop_is_fence (_lsu_io_core_exe_0_fresp_bits_uop_is_fence),
.io_core_exe_0_fresp_bits_uop_is_fencei (_lsu_io_core_exe_0_fresp_bits_uop_is_fencei),
.io_core_exe_0_fresp_bits_uop_is_amo (_lsu_io_core_exe_0_fresp_bits_uop_is_amo),
.io_core_exe_0_fresp_bits_uop_uses_ldq (_lsu_io_core_exe_0_fresp_bits_uop_uses_ldq),
.io_core_exe_0_fresp_bits_uop_uses_stq (_lsu_io_core_exe_0_fresp_bits_uop_uses_stq),
.io_core_exe_0_fresp_bits_uop_is_sys_pc2epc (_lsu_io_core_exe_0_fresp_bits_uop_is_sys_pc2epc),
.io_core_exe_0_fresp_bits_uop_is_unique (_lsu_io_core_exe_0_fresp_bits_uop_is_unique),
.io_core_exe_0_fresp_bits_uop_flush_on_commit (_lsu_io_core_exe_0_fresp_bits_uop_flush_on_commit),
.io_core_exe_0_fresp_bits_uop_ldst_is_rs1 (_lsu_io_core_exe_0_fresp_bits_uop_ldst_is_rs1),
.io_core_exe_0_fresp_bits_uop_ldst (_lsu_io_core_exe_0_fresp_bits_uop_ldst),
.io_core_exe_0_fresp_bits_uop_lrs1 (_lsu_io_core_exe_0_fresp_bits_uop_lrs1),
.io_core_exe_0_fresp_bits_uop_lrs2 (_lsu_io_core_exe_0_fresp_bits_uop_lrs2),
.io_core_exe_0_fresp_bits_uop_lrs3 (_lsu_io_core_exe_0_fresp_bits_uop_lrs3),
.io_core_exe_0_fresp_bits_uop_ldst_val (_lsu_io_core_exe_0_fresp_bits_uop_ldst_val),
.io_core_exe_0_fresp_bits_uop_dst_rtype (_lsu_io_core_exe_0_fresp_bits_uop_dst_rtype),
.io_core_exe_0_fresp_bits_uop_lrs1_rtype (_lsu_io_core_exe_0_fresp_bits_uop_lrs1_rtype),
.io_core_exe_0_fresp_bits_uop_lrs2_rtype (_lsu_io_core_exe_0_fresp_bits_uop_lrs2_rtype),
.io_core_exe_0_fresp_bits_uop_frs3_en (_lsu_io_core_exe_0_fresp_bits_uop_frs3_en),
.io_core_exe_0_fresp_bits_uop_fp_val (_lsu_io_core_exe_0_fresp_bits_uop_fp_val),
.io_core_exe_0_fresp_bits_uop_fp_single (_lsu_io_core_exe_0_fresp_bits_uop_fp_single),
.io_core_exe_0_fresp_bits_uop_xcpt_pf_if (_lsu_io_core_exe_0_fresp_bits_uop_xcpt_pf_if),
.io_core_exe_0_fresp_bits_uop_xcpt_ae_if (_lsu_io_core_exe_0_fresp_bits_uop_xcpt_ae_if),
.io_core_exe_0_fresp_bits_uop_xcpt_ma_if (_lsu_io_core_exe_0_fresp_bits_uop_xcpt_ma_if),
.io_core_exe_0_fresp_bits_uop_bp_debug_if (_lsu_io_core_exe_0_fresp_bits_uop_bp_debug_if),
.io_core_exe_0_fresp_bits_uop_bp_xcpt_if (_lsu_io_core_exe_0_fresp_bits_uop_bp_xcpt_if),
.io_core_exe_0_fresp_bits_uop_debug_fsrc (_lsu_io_core_exe_0_fresp_bits_uop_debug_fsrc),
.io_core_exe_0_fresp_bits_uop_debug_tsrc (_lsu_io_core_exe_0_fresp_bits_uop_debug_tsrc),
.io_core_exe_0_fresp_bits_data (_lsu_io_core_exe_0_fresp_bits_data),
.io_core_dis_uops_0_valid (_core_io_lsu_dis_uops_0_valid), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_uopc (_core_io_lsu_dis_uops_0_bits_uopc), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_inst (_core_io_lsu_dis_uops_0_bits_inst), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_debug_inst (_core_io_lsu_dis_uops_0_bits_debug_inst), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_is_rvc (_core_io_lsu_dis_uops_0_bits_is_rvc), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_debug_pc (_core_io_lsu_dis_uops_0_bits_debug_pc), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_iq_type (_core_io_lsu_dis_uops_0_bits_iq_type), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_fu_code (_core_io_lsu_dis_uops_0_bits_fu_code), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ctrl_br_type (_core_io_lsu_dis_uops_0_bits_ctrl_br_type), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ctrl_op1_sel (_core_io_lsu_dis_uops_0_bits_ctrl_op1_sel), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ctrl_op2_sel (_core_io_lsu_dis_uops_0_bits_ctrl_op2_sel), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ctrl_imm_sel (_core_io_lsu_dis_uops_0_bits_ctrl_imm_sel), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ctrl_op_fcn (_core_io_lsu_dis_uops_0_bits_ctrl_op_fcn), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ctrl_fcn_dw (_core_io_lsu_dis_uops_0_bits_ctrl_fcn_dw), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ctrl_csr_cmd (_core_io_lsu_dis_uops_0_bits_ctrl_csr_cmd), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ctrl_is_load (_core_io_lsu_dis_uops_0_bits_ctrl_is_load), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ctrl_is_sta (_core_io_lsu_dis_uops_0_bits_ctrl_is_sta), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ctrl_is_std (_core_io_lsu_dis_uops_0_bits_ctrl_is_std), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_iw_state (_core_io_lsu_dis_uops_0_bits_iw_state), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_iw_p1_poisoned (_core_io_lsu_dis_uops_0_bits_iw_p1_poisoned), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_iw_p2_poisoned (_core_io_lsu_dis_uops_0_bits_iw_p2_poisoned), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_is_br (_core_io_lsu_dis_uops_0_bits_is_br), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_is_jalr (_core_io_lsu_dis_uops_0_bits_is_jalr), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_is_jal (_core_io_lsu_dis_uops_0_bits_is_jal), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_is_sfb (_core_io_lsu_dis_uops_0_bits_is_sfb), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_br_mask (_core_io_lsu_dis_uops_0_bits_br_mask), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_br_tag (_core_io_lsu_dis_uops_0_bits_br_tag), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ftq_idx (_core_io_lsu_dis_uops_0_bits_ftq_idx), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_edge_inst (_core_io_lsu_dis_uops_0_bits_edge_inst), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_pc_lob (_core_io_lsu_dis_uops_0_bits_pc_lob), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_taken (_core_io_lsu_dis_uops_0_bits_taken), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_imm_packed (_core_io_lsu_dis_uops_0_bits_imm_packed), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_csr_addr (_core_io_lsu_dis_uops_0_bits_csr_addr), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_rob_idx (_core_io_lsu_dis_uops_0_bits_rob_idx), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ldq_idx (_core_io_lsu_dis_uops_0_bits_ldq_idx), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_stq_idx (_core_io_lsu_dis_uops_0_bits_stq_idx), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_rxq_idx (_core_io_lsu_dis_uops_0_bits_rxq_idx), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_pdst (_core_io_lsu_dis_uops_0_bits_pdst), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_prs1 (_core_io_lsu_dis_uops_0_bits_prs1), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_prs2 (_core_io_lsu_dis_uops_0_bits_prs2), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_prs3 (_core_io_lsu_dis_uops_0_bits_prs3), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_prs1_busy (_core_io_lsu_dis_uops_0_bits_prs1_busy), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_prs2_busy (_core_io_lsu_dis_uops_0_bits_prs2_busy), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_prs3_busy (_core_io_lsu_dis_uops_0_bits_prs3_busy), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_stale_pdst (_core_io_lsu_dis_uops_0_bits_stale_pdst), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_exception (_core_io_lsu_dis_uops_0_bits_exception), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_exc_cause (_core_io_lsu_dis_uops_0_bits_exc_cause), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_bypassable (_core_io_lsu_dis_uops_0_bits_bypassable), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_mem_cmd (_core_io_lsu_dis_uops_0_bits_mem_cmd), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_mem_size (_core_io_lsu_dis_uops_0_bits_mem_size), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_mem_signed (_core_io_lsu_dis_uops_0_bits_mem_signed), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_is_fence (_core_io_lsu_dis_uops_0_bits_is_fence), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_is_fencei (_core_io_lsu_dis_uops_0_bits_is_fencei), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_is_amo (_core_io_lsu_dis_uops_0_bits_is_amo), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_uses_ldq (_core_io_lsu_dis_uops_0_bits_uses_ldq), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_uses_stq (_core_io_lsu_dis_uops_0_bits_uses_stq), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_is_sys_pc2epc (_core_io_lsu_dis_uops_0_bits_is_sys_pc2epc), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_is_unique (_core_io_lsu_dis_uops_0_bits_is_unique), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_flush_on_commit (_core_io_lsu_dis_uops_0_bits_flush_on_commit), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ldst_is_rs1 (_core_io_lsu_dis_uops_0_bits_ldst_is_rs1), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ldst (_core_io_lsu_dis_uops_0_bits_ldst), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_lrs1 (_core_io_lsu_dis_uops_0_bits_lrs1), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_lrs2 (_core_io_lsu_dis_uops_0_bits_lrs2), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_lrs3 (_core_io_lsu_dis_uops_0_bits_lrs3), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ldst_val (_core_io_lsu_dis_uops_0_bits_ldst_val), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_dst_rtype (_core_io_lsu_dis_uops_0_bits_dst_rtype), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_lrs1_rtype (_core_io_lsu_dis_uops_0_bits_lrs1_rtype), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_lrs2_rtype (_core_io_lsu_dis_uops_0_bits_lrs2_rtype), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_frs3_en (_core_io_lsu_dis_uops_0_bits_frs3_en), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_fp_val (_core_io_lsu_dis_uops_0_bits_fp_val), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_fp_single (_core_io_lsu_dis_uops_0_bits_fp_single), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_xcpt_pf_if (_core_io_lsu_dis_uops_0_bits_xcpt_pf_if), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_xcpt_ae_if (_core_io_lsu_dis_uops_0_bits_xcpt_ae_if), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_xcpt_ma_if (_core_io_lsu_dis_uops_0_bits_xcpt_ma_if), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_bp_debug_if (_core_io_lsu_dis_uops_0_bits_bp_debug_if), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_bp_xcpt_if (_core_io_lsu_dis_uops_0_bits_bp_xcpt_if), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_debug_fsrc (_core_io_lsu_dis_uops_0_bits_debug_fsrc), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_debug_tsrc (_core_io_lsu_dis_uops_0_bits_debug_tsrc), // @[tile.scala:159:20]
.io_core_dis_uops_1_valid (_core_io_lsu_dis_uops_1_valid), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_uopc (_core_io_lsu_dis_uops_1_bits_uopc), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_inst (_core_io_lsu_dis_uops_1_bits_inst), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_debug_inst (_core_io_lsu_dis_uops_1_bits_debug_inst), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_is_rvc (_core_io_lsu_dis_uops_1_bits_is_rvc), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_debug_pc (_core_io_lsu_dis_uops_1_bits_debug_pc), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_iq_type (_core_io_lsu_dis_uops_1_bits_iq_type), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_fu_code (_core_io_lsu_dis_uops_1_bits_fu_code), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ctrl_br_type (_core_io_lsu_dis_uops_1_bits_ctrl_br_type), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ctrl_op1_sel (_core_io_lsu_dis_uops_1_bits_ctrl_op1_sel), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ctrl_op2_sel (_core_io_lsu_dis_uops_1_bits_ctrl_op2_sel), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ctrl_imm_sel (_core_io_lsu_dis_uops_1_bits_ctrl_imm_sel), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ctrl_op_fcn (_core_io_lsu_dis_uops_1_bits_ctrl_op_fcn), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ctrl_fcn_dw (_core_io_lsu_dis_uops_1_bits_ctrl_fcn_dw), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ctrl_csr_cmd (_core_io_lsu_dis_uops_1_bits_ctrl_csr_cmd), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ctrl_is_load (_core_io_lsu_dis_uops_1_bits_ctrl_is_load), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ctrl_is_sta (_core_io_lsu_dis_uops_1_bits_ctrl_is_sta), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ctrl_is_std (_core_io_lsu_dis_uops_1_bits_ctrl_is_std), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_iw_state (_core_io_lsu_dis_uops_1_bits_iw_state), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_iw_p1_poisoned (_core_io_lsu_dis_uops_1_bits_iw_p1_poisoned), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_iw_p2_poisoned (_core_io_lsu_dis_uops_1_bits_iw_p2_poisoned), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_is_br (_core_io_lsu_dis_uops_1_bits_is_br), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_is_jalr (_core_io_lsu_dis_uops_1_bits_is_jalr), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_is_jal (_core_io_lsu_dis_uops_1_bits_is_jal), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_is_sfb (_core_io_lsu_dis_uops_1_bits_is_sfb), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_br_mask (_core_io_lsu_dis_uops_1_bits_br_mask), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_br_tag (_core_io_lsu_dis_uops_1_bits_br_tag), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ftq_idx (_core_io_lsu_dis_uops_1_bits_ftq_idx), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_edge_inst (_core_io_lsu_dis_uops_1_bits_edge_inst), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_pc_lob (_core_io_lsu_dis_uops_1_bits_pc_lob), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_taken (_core_io_lsu_dis_uops_1_bits_taken), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_imm_packed (_core_io_lsu_dis_uops_1_bits_imm_packed), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_csr_addr (_core_io_lsu_dis_uops_1_bits_csr_addr), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_rob_idx (_core_io_lsu_dis_uops_1_bits_rob_idx), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ldq_idx (_core_io_lsu_dis_uops_1_bits_ldq_idx), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_stq_idx (_core_io_lsu_dis_uops_1_bits_stq_idx), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_rxq_idx (_core_io_lsu_dis_uops_1_bits_rxq_idx), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_pdst (_core_io_lsu_dis_uops_1_bits_pdst), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_prs1 (_core_io_lsu_dis_uops_1_bits_prs1), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_prs2 (_core_io_lsu_dis_uops_1_bits_prs2), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_prs3 (_core_io_lsu_dis_uops_1_bits_prs3), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_prs1_busy (_core_io_lsu_dis_uops_1_bits_prs1_busy), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_prs2_busy (_core_io_lsu_dis_uops_1_bits_prs2_busy), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_prs3_busy (_core_io_lsu_dis_uops_1_bits_prs3_busy), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_stale_pdst (_core_io_lsu_dis_uops_1_bits_stale_pdst), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_exception (_core_io_lsu_dis_uops_1_bits_exception), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_exc_cause (_core_io_lsu_dis_uops_1_bits_exc_cause), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_bypassable (_core_io_lsu_dis_uops_1_bits_bypassable), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_mem_cmd (_core_io_lsu_dis_uops_1_bits_mem_cmd), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_mem_size (_core_io_lsu_dis_uops_1_bits_mem_size), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_mem_signed (_core_io_lsu_dis_uops_1_bits_mem_signed), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_is_fence (_core_io_lsu_dis_uops_1_bits_is_fence), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_is_fencei (_core_io_lsu_dis_uops_1_bits_is_fencei), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_is_amo (_core_io_lsu_dis_uops_1_bits_is_amo), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_uses_ldq (_core_io_lsu_dis_uops_1_bits_uses_ldq), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_uses_stq (_core_io_lsu_dis_uops_1_bits_uses_stq), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_is_sys_pc2epc (_core_io_lsu_dis_uops_1_bits_is_sys_pc2epc), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_is_unique (_core_io_lsu_dis_uops_1_bits_is_unique), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_flush_on_commit (_core_io_lsu_dis_uops_1_bits_flush_on_commit), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ldst_is_rs1 (_core_io_lsu_dis_uops_1_bits_ldst_is_rs1), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ldst (_core_io_lsu_dis_uops_1_bits_ldst), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_lrs1 (_core_io_lsu_dis_uops_1_bits_lrs1), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_lrs2 (_core_io_lsu_dis_uops_1_bits_lrs2), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_lrs3 (_core_io_lsu_dis_uops_1_bits_lrs3), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ldst_val (_core_io_lsu_dis_uops_1_bits_ldst_val), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_dst_rtype (_core_io_lsu_dis_uops_1_bits_dst_rtype), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_lrs1_rtype (_core_io_lsu_dis_uops_1_bits_lrs1_rtype), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_lrs2_rtype (_core_io_lsu_dis_uops_1_bits_lrs2_rtype), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_frs3_en (_core_io_lsu_dis_uops_1_bits_frs3_en), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_fp_val (_core_io_lsu_dis_uops_1_bits_fp_val), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_fp_single (_core_io_lsu_dis_uops_1_bits_fp_single), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_xcpt_pf_if (_core_io_lsu_dis_uops_1_bits_xcpt_pf_if), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_xcpt_ae_if (_core_io_lsu_dis_uops_1_bits_xcpt_ae_if), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_xcpt_ma_if (_core_io_lsu_dis_uops_1_bits_xcpt_ma_if), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_bp_debug_if (_core_io_lsu_dis_uops_1_bits_bp_debug_if), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_bp_xcpt_if (_core_io_lsu_dis_uops_1_bits_bp_xcpt_if), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_debug_fsrc (_core_io_lsu_dis_uops_1_bits_debug_fsrc), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_debug_tsrc (_core_io_lsu_dis_uops_1_bits_debug_tsrc), // @[tile.scala:159:20]
.io_core_dis_uops_2_valid (_core_io_lsu_dis_uops_2_valid), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_uopc (_core_io_lsu_dis_uops_2_bits_uopc), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_inst (_core_io_lsu_dis_uops_2_bits_inst), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_debug_inst (_core_io_lsu_dis_uops_2_bits_debug_inst), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_is_rvc (_core_io_lsu_dis_uops_2_bits_is_rvc), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_debug_pc (_core_io_lsu_dis_uops_2_bits_debug_pc), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_iq_type (_core_io_lsu_dis_uops_2_bits_iq_type), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_fu_code (_core_io_lsu_dis_uops_2_bits_fu_code), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ctrl_br_type (_core_io_lsu_dis_uops_2_bits_ctrl_br_type), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ctrl_op1_sel (_core_io_lsu_dis_uops_2_bits_ctrl_op1_sel), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ctrl_op2_sel (_core_io_lsu_dis_uops_2_bits_ctrl_op2_sel), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ctrl_imm_sel (_core_io_lsu_dis_uops_2_bits_ctrl_imm_sel), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ctrl_op_fcn (_core_io_lsu_dis_uops_2_bits_ctrl_op_fcn), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ctrl_fcn_dw (_core_io_lsu_dis_uops_2_bits_ctrl_fcn_dw), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ctrl_csr_cmd (_core_io_lsu_dis_uops_2_bits_ctrl_csr_cmd), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ctrl_is_load (_core_io_lsu_dis_uops_2_bits_ctrl_is_load), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ctrl_is_sta (_core_io_lsu_dis_uops_2_bits_ctrl_is_sta), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ctrl_is_std (_core_io_lsu_dis_uops_2_bits_ctrl_is_std), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_iw_state (_core_io_lsu_dis_uops_2_bits_iw_state), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_iw_p1_poisoned (_core_io_lsu_dis_uops_2_bits_iw_p1_poisoned), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_iw_p2_poisoned (_core_io_lsu_dis_uops_2_bits_iw_p2_poisoned), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_is_br (_core_io_lsu_dis_uops_2_bits_is_br), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_is_jalr (_core_io_lsu_dis_uops_2_bits_is_jalr), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_is_jal (_core_io_lsu_dis_uops_2_bits_is_jal), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_is_sfb (_core_io_lsu_dis_uops_2_bits_is_sfb), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_br_mask (_core_io_lsu_dis_uops_2_bits_br_mask), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_br_tag (_core_io_lsu_dis_uops_2_bits_br_tag), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ftq_idx (_core_io_lsu_dis_uops_2_bits_ftq_idx), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_edge_inst (_core_io_lsu_dis_uops_2_bits_edge_inst), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_pc_lob (_core_io_lsu_dis_uops_2_bits_pc_lob), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_taken (_core_io_lsu_dis_uops_2_bits_taken), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_imm_packed (_core_io_lsu_dis_uops_2_bits_imm_packed), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_csr_addr (_core_io_lsu_dis_uops_2_bits_csr_addr), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_rob_idx (_core_io_lsu_dis_uops_2_bits_rob_idx), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ldq_idx (_core_io_lsu_dis_uops_2_bits_ldq_idx), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_stq_idx (_core_io_lsu_dis_uops_2_bits_stq_idx), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_rxq_idx (_core_io_lsu_dis_uops_2_bits_rxq_idx), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_pdst (_core_io_lsu_dis_uops_2_bits_pdst), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_prs1 (_core_io_lsu_dis_uops_2_bits_prs1), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_prs2 (_core_io_lsu_dis_uops_2_bits_prs2), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_prs3 (_core_io_lsu_dis_uops_2_bits_prs3), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_prs1_busy (_core_io_lsu_dis_uops_2_bits_prs1_busy), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_prs2_busy (_core_io_lsu_dis_uops_2_bits_prs2_busy), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_prs3_busy (_core_io_lsu_dis_uops_2_bits_prs3_busy), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_stale_pdst (_core_io_lsu_dis_uops_2_bits_stale_pdst), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_exception (_core_io_lsu_dis_uops_2_bits_exception), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_exc_cause (_core_io_lsu_dis_uops_2_bits_exc_cause), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_bypassable (_core_io_lsu_dis_uops_2_bits_bypassable), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_mem_cmd (_core_io_lsu_dis_uops_2_bits_mem_cmd), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_mem_size (_core_io_lsu_dis_uops_2_bits_mem_size), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_mem_signed (_core_io_lsu_dis_uops_2_bits_mem_signed), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_is_fence (_core_io_lsu_dis_uops_2_bits_is_fence), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_is_fencei (_core_io_lsu_dis_uops_2_bits_is_fencei), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_is_amo (_core_io_lsu_dis_uops_2_bits_is_amo), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_uses_ldq (_core_io_lsu_dis_uops_2_bits_uses_ldq), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_uses_stq (_core_io_lsu_dis_uops_2_bits_uses_stq), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_is_sys_pc2epc (_core_io_lsu_dis_uops_2_bits_is_sys_pc2epc), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_is_unique (_core_io_lsu_dis_uops_2_bits_is_unique), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_flush_on_commit (_core_io_lsu_dis_uops_2_bits_flush_on_commit), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ldst_is_rs1 (_core_io_lsu_dis_uops_2_bits_ldst_is_rs1), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ldst (_core_io_lsu_dis_uops_2_bits_ldst), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_lrs1 (_core_io_lsu_dis_uops_2_bits_lrs1), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_lrs2 (_core_io_lsu_dis_uops_2_bits_lrs2), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_lrs3 (_core_io_lsu_dis_uops_2_bits_lrs3), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ldst_val (_core_io_lsu_dis_uops_2_bits_ldst_val), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_dst_rtype (_core_io_lsu_dis_uops_2_bits_dst_rtype), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_lrs1_rtype (_core_io_lsu_dis_uops_2_bits_lrs1_rtype), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_lrs2_rtype (_core_io_lsu_dis_uops_2_bits_lrs2_rtype), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_frs3_en (_core_io_lsu_dis_uops_2_bits_frs3_en), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_fp_val (_core_io_lsu_dis_uops_2_bits_fp_val), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_fp_single (_core_io_lsu_dis_uops_2_bits_fp_single), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_xcpt_pf_if (_core_io_lsu_dis_uops_2_bits_xcpt_pf_if), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_xcpt_ae_if (_core_io_lsu_dis_uops_2_bits_xcpt_ae_if), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_xcpt_ma_if (_core_io_lsu_dis_uops_2_bits_xcpt_ma_if), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_bp_debug_if (_core_io_lsu_dis_uops_2_bits_bp_debug_if), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_bp_xcpt_if (_core_io_lsu_dis_uops_2_bits_bp_xcpt_if), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_debug_fsrc (_core_io_lsu_dis_uops_2_bits_debug_fsrc), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_debug_tsrc (_core_io_lsu_dis_uops_2_bits_debug_tsrc), // @[tile.scala:159:20]
.io_core_dis_ldq_idx_0 (_lsu_io_core_dis_ldq_idx_0),
.io_core_dis_ldq_idx_1 (_lsu_io_core_dis_ldq_idx_1),
.io_core_dis_ldq_idx_2 (_lsu_io_core_dis_ldq_idx_2),
.io_core_dis_stq_idx_0 (_lsu_io_core_dis_stq_idx_0),
.io_core_dis_stq_idx_1 (_lsu_io_core_dis_stq_idx_1),
.io_core_dis_stq_idx_2 (_lsu_io_core_dis_stq_idx_2),
.io_core_ldq_full_0 (_lsu_io_core_ldq_full_0),
.io_core_ldq_full_1 (_lsu_io_core_ldq_full_1),
.io_core_ldq_full_2 (_lsu_io_core_ldq_full_2),
.io_core_stq_full_0 (_lsu_io_core_stq_full_0),
.io_core_stq_full_1 (_lsu_io_core_stq_full_1),
.io_core_stq_full_2 (_lsu_io_core_stq_full_2),
.io_core_fp_stdata_ready (_lsu_io_core_fp_stdata_ready),
.io_core_fp_stdata_valid (_core_io_lsu_fp_stdata_valid), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_uopc (_core_io_lsu_fp_stdata_bits_uop_uopc), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_inst (_core_io_lsu_fp_stdata_bits_uop_inst), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_debug_inst (_core_io_lsu_fp_stdata_bits_uop_debug_inst), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_is_rvc (_core_io_lsu_fp_stdata_bits_uop_is_rvc), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_debug_pc (_core_io_lsu_fp_stdata_bits_uop_debug_pc), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_iq_type (_core_io_lsu_fp_stdata_bits_uop_iq_type), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_fu_code (_core_io_lsu_fp_stdata_bits_uop_fu_code), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ctrl_br_type (_core_io_lsu_fp_stdata_bits_uop_ctrl_br_type), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ctrl_op1_sel (_core_io_lsu_fp_stdata_bits_uop_ctrl_op1_sel), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ctrl_op2_sel (_core_io_lsu_fp_stdata_bits_uop_ctrl_op2_sel), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ctrl_imm_sel (_core_io_lsu_fp_stdata_bits_uop_ctrl_imm_sel), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ctrl_op_fcn (_core_io_lsu_fp_stdata_bits_uop_ctrl_op_fcn), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ctrl_fcn_dw (_core_io_lsu_fp_stdata_bits_uop_ctrl_fcn_dw), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ctrl_csr_cmd (_core_io_lsu_fp_stdata_bits_uop_ctrl_csr_cmd), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ctrl_is_load (_core_io_lsu_fp_stdata_bits_uop_ctrl_is_load), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ctrl_is_sta (_core_io_lsu_fp_stdata_bits_uop_ctrl_is_sta), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ctrl_is_std (_core_io_lsu_fp_stdata_bits_uop_ctrl_is_std), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_iw_state (_core_io_lsu_fp_stdata_bits_uop_iw_state), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_iw_p1_poisoned (_core_io_lsu_fp_stdata_bits_uop_iw_p1_poisoned), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_iw_p2_poisoned (_core_io_lsu_fp_stdata_bits_uop_iw_p2_poisoned), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_is_br (_core_io_lsu_fp_stdata_bits_uop_is_br), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_is_jalr (_core_io_lsu_fp_stdata_bits_uop_is_jalr), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_is_jal (_core_io_lsu_fp_stdata_bits_uop_is_jal), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_is_sfb (_core_io_lsu_fp_stdata_bits_uop_is_sfb), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_br_mask (_core_io_lsu_fp_stdata_bits_uop_br_mask), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_br_tag (_core_io_lsu_fp_stdata_bits_uop_br_tag), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ftq_idx (_core_io_lsu_fp_stdata_bits_uop_ftq_idx), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_edge_inst (_core_io_lsu_fp_stdata_bits_uop_edge_inst), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_pc_lob (_core_io_lsu_fp_stdata_bits_uop_pc_lob), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_taken (_core_io_lsu_fp_stdata_bits_uop_taken), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_imm_packed (_core_io_lsu_fp_stdata_bits_uop_imm_packed), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_csr_addr (_core_io_lsu_fp_stdata_bits_uop_csr_addr), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_rob_idx (_core_io_lsu_fp_stdata_bits_uop_rob_idx), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ldq_idx (_core_io_lsu_fp_stdata_bits_uop_ldq_idx), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_stq_idx (_core_io_lsu_fp_stdata_bits_uop_stq_idx), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_rxq_idx (_core_io_lsu_fp_stdata_bits_uop_rxq_idx), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_pdst (_core_io_lsu_fp_stdata_bits_uop_pdst), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_prs1 (_core_io_lsu_fp_stdata_bits_uop_prs1), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_prs2 (_core_io_lsu_fp_stdata_bits_uop_prs2), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_prs3 (_core_io_lsu_fp_stdata_bits_uop_prs3), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ppred (_core_io_lsu_fp_stdata_bits_uop_ppred), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_prs1_busy (_core_io_lsu_fp_stdata_bits_uop_prs1_busy), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_prs2_busy (_core_io_lsu_fp_stdata_bits_uop_prs2_busy), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_prs3_busy (_core_io_lsu_fp_stdata_bits_uop_prs3_busy), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ppred_busy (_core_io_lsu_fp_stdata_bits_uop_ppred_busy), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_stale_pdst (_core_io_lsu_fp_stdata_bits_uop_stale_pdst), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_exception (_core_io_lsu_fp_stdata_bits_uop_exception), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_exc_cause (_core_io_lsu_fp_stdata_bits_uop_exc_cause), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_bypassable (_core_io_lsu_fp_stdata_bits_uop_bypassable), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_mem_cmd (_core_io_lsu_fp_stdata_bits_uop_mem_cmd), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_mem_size (_core_io_lsu_fp_stdata_bits_uop_mem_size), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_mem_signed (_core_io_lsu_fp_stdata_bits_uop_mem_signed), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_is_fence (_core_io_lsu_fp_stdata_bits_uop_is_fence), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_is_fencei (_core_io_lsu_fp_stdata_bits_uop_is_fencei), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_is_amo (_core_io_lsu_fp_stdata_bits_uop_is_amo), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_uses_ldq (_core_io_lsu_fp_stdata_bits_uop_uses_ldq), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_uses_stq (_core_io_lsu_fp_stdata_bits_uop_uses_stq), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_is_sys_pc2epc (_core_io_lsu_fp_stdata_bits_uop_is_sys_pc2epc), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_is_unique (_core_io_lsu_fp_stdata_bits_uop_is_unique), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_flush_on_commit (_core_io_lsu_fp_stdata_bits_uop_flush_on_commit), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ldst_is_rs1 (_core_io_lsu_fp_stdata_bits_uop_ldst_is_rs1), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ldst (_core_io_lsu_fp_stdata_bits_uop_ldst), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_lrs1 (_core_io_lsu_fp_stdata_bits_uop_lrs1), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_lrs2 (_core_io_lsu_fp_stdata_bits_uop_lrs2), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_lrs3 (_core_io_lsu_fp_stdata_bits_uop_lrs3), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ldst_val (_core_io_lsu_fp_stdata_bits_uop_ldst_val), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_dst_rtype (_core_io_lsu_fp_stdata_bits_uop_dst_rtype), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_lrs1_rtype (_core_io_lsu_fp_stdata_bits_uop_lrs1_rtype), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_lrs2_rtype (_core_io_lsu_fp_stdata_bits_uop_lrs2_rtype), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_frs3_en (_core_io_lsu_fp_stdata_bits_uop_frs3_en), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_fp_val (_core_io_lsu_fp_stdata_bits_uop_fp_val), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_fp_single (_core_io_lsu_fp_stdata_bits_uop_fp_single), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_xcpt_pf_if (_core_io_lsu_fp_stdata_bits_uop_xcpt_pf_if), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_xcpt_ae_if (_core_io_lsu_fp_stdata_bits_uop_xcpt_ae_if), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_xcpt_ma_if (_core_io_lsu_fp_stdata_bits_uop_xcpt_ma_if), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_bp_debug_if (_core_io_lsu_fp_stdata_bits_uop_bp_debug_if), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_bp_xcpt_if (_core_io_lsu_fp_stdata_bits_uop_bp_xcpt_if), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_debug_fsrc (_core_io_lsu_fp_stdata_bits_uop_debug_fsrc), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_debug_tsrc (_core_io_lsu_fp_stdata_bits_uop_debug_tsrc), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_data (_core_io_lsu_fp_stdata_bits_data), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_predicated (_core_io_lsu_fp_stdata_bits_predicated), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_valid (_core_io_lsu_fp_stdata_bits_fflags_valid), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_uopc (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_uopc), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_inst (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_inst), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_debug_inst (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_debug_inst), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_is_rvc (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_rvc), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_debug_pc (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_debug_pc), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_iq_type (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_iq_type), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_fu_code (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_fu_code), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ctrl_br_type (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_br_type), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op1_sel (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op1_sel), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op2_sel (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op2_sel), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ctrl_imm_sel (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_imm_sel), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op_fcn (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op_fcn), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ctrl_fcn_dw (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_fcn_dw), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ctrl_csr_cmd (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_csr_cmd), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_load (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_load), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_sta (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_sta), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_std (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_std), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_iw_state (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_iw_state), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_iw_p1_poisoned (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p1_poisoned), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_iw_p2_poisoned (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p2_poisoned), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_is_br (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_br), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_is_jalr (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_jalr), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_is_jal (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_jal), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_is_sfb (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_sfb), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_br_mask (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_br_mask), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_br_tag (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_br_tag), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ftq_idx (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ftq_idx), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_edge_inst (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_edge_inst), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_pc_lob (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_pc_lob), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_taken (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_taken), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_imm_packed (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_imm_packed), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_csr_addr (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_csr_addr), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_rob_idx (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_rob_idx), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ldq_idx (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ldq_idx), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_stq_idx (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_stq_idx), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_rxq_idx (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_rxq_idx), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_pdst (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_pdst), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_prs1 (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs1), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_prs2 (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs2), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_prs3 (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs3), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ppred (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ppred), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_prs1_busy (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs1_busy), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_prs2_busy (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs2_busy), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_prs3_busy (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs3_busy), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ppred_busy (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ppred_busy), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_stale_pdst (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_stale_pdst), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_exception (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_exception), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_exc_cause (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_exc_cause), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_bypassable (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_bypassable), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_mem_cmd (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_mem_cmd), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_mem_size (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_mem_size), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_mem_signed (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_mem_signed), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_is_fence (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_fence), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_is_fencei (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_fencei), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_is_amo (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_amo), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_uses_ldq (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_uses_ldq), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_uses_stq (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_uses_stq), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_is_sys_pc2epc (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_sys_pc2epc), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_is_unique (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_unique), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_flush_on_commit (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_flush_on_commit), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ldst_is_rs1 (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_is_rs1), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ldst (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ldst), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_lrs1 (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_lrs2 (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_lrs3 (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs3), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ldst_val (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_val), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_dst_rtype (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_dst_rtype), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_lrs1_rtype (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1_rtype), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_lrs2_rtype (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2_rtype), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_frs3_en (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_frs3_en), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_fp_val (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_fp_val), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_fp_single (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_fp_single), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_xcpt_pf_if (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_pf_if), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_xcpt_ae_if (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ae_if), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_xcpt_ma_if (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ma_if), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_bp_debug_if (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_bp_debug_if), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_bp_xcpt_if (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_bp_xcpt_if), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_debug_fsrc (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_debug_fsrc), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_debug_tsrc (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_debug_tsrc), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_flags (_core_io_lsu_fp_stdata_bits_fflags_bits_flags), // @[tile.scala:159:20]
.io_core_commit_valids_0 (_core_io_lsu_commit_valids_0), // @[tile.scala:159:20]
.io_core_commit_valids_1 (_core_io_lsu_commit_valids_1), // @[tile.scala:159:20]
.io_core_commit_valids_2 (_core_io_lsu_commit_valids_2), // @[tile.scala:159:20]
.io_core_commit_arch_valids_0 (_core_io_lsu_commit_arch_valids_0), // @[tile.scala:159:20]
.io_core_commit_arch_valids_1 (_core_io_lsu_commit_arch_valids_1), // @[tile.scala:159:20]
.io_core_commit_arch_valids_2 (_core_io_lsu_commit_arch_valids_2), // @[tile.scala:159:20]
.io_core_commit_uops_0_uopc (_core_io_lsu_commit_uops_0_uopc), // @[tile.scala:159:20]
.io_core_commit_uops_0_inst (_core_io_lsu_commit_uops_0_inst), // @[tile.scala:159:20]
.io_core_commit_uops_0_debug_inst (_core_io_lsu_commit_uops_0_debug_inst), // @[tile.scala:159:20]
.io_core_commit_uops_0_is_rvc (_core_io_lsu_commit_uops_0_is_rvc), // @[tile.scala:159:20]
.io_core_commit_uops_0_debug_pc (_core_io_lsu_commit_uops_0_debug_pc), // @[tile.scala:159:20]
.io_core_commit_uops_0_iq_type (_core_io_lsu_commit_uops_0_iq_type), // @[tile.scala:159:20]
.io_core_commit_uops_0_fu_code (_core_io_lsu_commit_uops_0_fu_code), // @[tile.scala:159:20]
.io_core_commit_uops_0_ctrl_br_type (_core_io_lsu_commit_uops_0_ctrl_br_type), // @[tile.scala:159:20]
.io_core_commit_uops_0_ctrl_op1_sel (_core_io_lsu_commit_uops_0_ctrl_op1_sel), // @[tile.scala:159:20]
.io_core_commit_uops_0_ctrl_op2_sel (_core_io_lsu_commit_uops_0_ctrl_op2_sel), // @[tile.scala:159:20]
.io_core_commit_uops_0_ctrl_imm_sel (_core_io_lsu_commit_uops_0_ctrl_imm_sel), // @[tile.scala:159:20]
.io_core_commit_uops_0_ctrl_op_fcn (_core_io_lsu_commit_uops_0_ctrl_op_fcn), // @[tile.scala:159:20]
.io_core_commit_uops_0_ctrl_fcn_dw (_core_io_lsu_commit_uops_0_ctrl_fcn_dw), // @[tile.scala:159:20]
.io_core_commit_uops_0_ctrl_csr_cmd (_core_io_lsu_commit_uops_0_ctrl_csr_cmd), // @[tile.scala:159:20]
.io_core_commit_uops_0_ctrl_is_load (_core_io_lsu_commit_uops_0_ctrl_is_load), // @[tile.scala:159:20]
.io_core_commit_uops_0_ctrl_is_sta (_core_io_lsu_commit_uops_0_ctrl_is_sta), // @[tile.scala:159:20]
.io_core_commit_uops_0_ctrl_is_std (_core_io_lsu_commit_uops_0_ctrl_is_std), // @[tile.scala:159:20]
.io_core_commit_uops_0_iw_state (_core_io_lsu_commit_uops_0_iw_state), // @[tile.scala:159:20]
.io_core_commit_uops_0_iw_p1_poisoned (_core_io_lsu_commit_uops_0_iw_p1_poisoned), // @[tile.scala:159:20]
.io_core_commit_uops_0_iw_p2_poisoned (_core_io_lsu_commit_uops_0_iw_p2_poisoned), // @[tile.scala:159:20]
.io_core_commit_uops_0_is_br (_core_io_lsu_commit_uops_0_is_br), // @[tile.scala:159:20]
.io_core_commit_uops_0_is_jalr (_core_io_lsu_commit_uops_0_is_jalr), // @[tile.scala:159:20]
.io_core_commit_uops_0_is_jal (_core_io_lsu_commit_uops_0_is_jal), // @[tile.scala:159:20]
.io_core_commit_uops_0_is_sfb (_core_io_lsu_commit_uops_0_is_sfb), // @[tile.scala:159:20]
.io_core_commit_uops_0_br_mask (_core_io_lsu_commit_uops_0_br_mask), // @[tile.scala:159:20]
.io_core_commit_uops_0_br_tag (_core_io_lsu_commit_uops_0_br_tag), // @[tile.scala:159:20]
.io_core_commit_uops_0_ftq_idx (_core_io_lsu_commit_uops_0_ftq_idx), // @[tile.scala:159:20]
.io_core_commit_uops_0_edge_inst (_core_io_lsu_commit_uops_0_edge_inst), // @[tile.scala:159:20]
.io_core_commit_uops_0_pc_lob (_core_io_lsu_commit_uops_0_pc_lob), // @[tile.scala:159:20]
.io_core_commit_uops_0_taken (_core_io_lsu_commit_uops_0_taken), // @[tile.scala:159:20]
.io_core_commit_uops_0_imm_packed (_core_io_lsu_commit_uops_0_imm_packed), // @[tile.scala:159:20]
.io_core_commit_uops_0_csr_addr (_core_io_lsu_commit_uops_0_csr_addr), // @[tile.scala:159:20]
.io_core_commit_uops_0_rob_idx (_core_io_lsu_commit_uops_0_rob_idx), // @[tile.scala:159:20]
.io_core_commit_uops_0_ldq_idx (_core_io_lsu_commit_uops_0_ldq_idx), // @[tile.scala:159:20]
.io_core_commit_uops_0_stq_idx (_core_io_lsu_commit_uops_0_stq_idx), // @[tile.scala:159:20]
.io_core_commit_uops_0_rxq_idx (_core_io_lsu_commit_uops_0_rxq_idx), // @[tile.scala:159:20]
.io_core_commit_uops_0_pdst (_core_io_lsu_commit_uops_0_pdst), // @[tile.scala:159:20]
.io_core_commit_uops_0_prs1 (_core_io_lsu_commit_uops_0_prs1), // @[tile.scala:159:20]
.io_core_commit_uops_0_prs2 (_core_io_lsu_commit_uops_0_prs2), // @[tile.scala:159:20]
.io_core_commit_uops_0_prs3 (_core_io_lsu_commit_uops_0_prs3), // @[tile.scala:159:20]
.io_core_commit_uops_0_ppred (_core_io_lsu_commit_uops_0_ppred), // @[tile.scala:159:20]
.io_core_commit_uops_0_prs1_busy (_core_io_lsu_commit_uops_0_prs1_busy), // @[tile.scala:159:20]
.io_core_commit_uops_0_prs2_busy (_core_io_lsu_commit_uops_0_prs2_busy), // @[tile.scala:159:20]
.io_core_commit_uops_0_prs3_busy (_core_io_lsu_commit_uops_0_prs3_busy), // @[tile.scala:159:20]
.io_core_commit_uops_0_ppred_busy (_core_io_lsu_commit_uops_0_ppred_busy), // @[tile.scala:159:20]
.io_core_commit_uops_0_stale_pdst (_core_io_lsu_commit_uops_0_stale_pdst), // @[tile.scala:159:20]
.io_core_commit_uops_0_exception (_core_io_lsu_commit_uops_0_exception), // @[tile.scala:159:20]
.io_core_commit_uops_0_exc_cause (_core_io_lsu_commit_uops_0_exc_cause), // @[tile.scala:159:20]
.io_core_commit_uops_0_bypassable (_core_io_lsu_commit_uops_0_bypassable), // @[tile.scala:159:20]
.io_core_commit_uops_0_mem_cmd (_core_io_lsu_commit_uops_0_mem_cmd), // @[tile.scala:159:20]
.io_core_commit_uops_0_mem_size (_core_io_lsu_commit_uops_0_mem_size), // @[tile.scala:159:20]
.io_core_commit_uops_0_mem_signed (_core_io_lsu_commit_uops_0_mem_signed), // @[tile.scala:159:20]
.io_core_commit_uops_0_is_fence (_core_io_lsu_commit_uops_0_is_fence), // @[tile.scala:159:20]
.io_core_commit_uops_0_is_fencei (_core_io_lsu_commit_uops_0_is_fencei), // @[tile.scala:159:20]
.io_core_commit_uops_0_is_amo (_core_io_lsu_commit_uops_0_is_amo), // @[tile.scala:159:20]
.io_core_commit_uops_0_uses_ldq (_core_io_lsu_commit_uops_0_uses_ldq), // @[tile.scala:159:20]
.io_core_commit_uops_0_uses_stq (_core_io_lsu_commit_uops_0_uses_stq), // @[tile.scala:159:20]
.io_core_commit_uops_0_is_sys_pc2epc (_core_io_lsu_commit_uops_0_is_sys_pc2epc), // @[tile.scala:159:20]
.io_core_commit_uops_0_is_unique (_core_io_lsu_commit_uops_0_is_unique), // @[tile.scala:159:20]
.io_core_commit_uops_0_flush_on_commit (_core_io_lsu_commit_uops_0_flush_on_commit), // @[tile.scala:159:20]
.io_core_commit_uops_0_ldst_is_rs1 (_core_io_lsu_commit_uops_0_ldst_is_rs1), // @[tile.scala:159:20]
.io_core_commit_uops_0_ldst (_core_io_lsu_commit_uops_0_ldst), // @[tile.scala:159:20]
.io_core_commit_uops_0_lrs1 (_core_io_lsu_commit_uops_0_lrs1), // @[tile.scala:159:20]
.io_core_commit_uops_0_lrs2 (_core_io_lsu_commit_uops_0_lrs2), // @[tile.scala:159:20]
.io_core_commit_uops_0_lrs3 (_core_io_lsu_commit_uops_0_lrs3), // @[tile.scala:159:20]
.io_core_commit_uops_0_ldst_val (_core_io_lsu_commit_uops_0_ldst_val), // @[tile.scala:159:20]
.io_core_commit_uops_0_dst_rtype (_core_io_lsu_commit_uops_0_dst_rtype), // @[tile.scala:159:20]
.io_core_commit_uops_0_lrs1_rtype (_core_io_lsu_commit_uops_0_lrs1_rtype), // @[tile.scala:159:20]
.io_core_commit_uops_0_lrs2_rtype (_core_io_lsu_commit_uops_0_lrs2_rtype), // @[tile.scala:159:20]
.io_core_commit_uops_0_frs3_en (_core_io_lsu_commit_uops_0_frs3_en), // @[tile.scala:159:20]
.io_core_commit_uops_0_fp_val (_core_io_lsu_commit_uops_0_fp_val), // @[tile.scala:159:20]
.io_core_commit_uops_0_fp_single (_core_io_lsu_commit_uops_0_fp_single), // @[tile.scala:159:20]
.io_core_commit_uops_0_xcpt_pf_if (_core_io_lsu_commit_uops_0_xcpt_pf_if), // @[tile.scala:159:20]
.io_core_commit_uops_0_xcpt_ae_if (_core_io_lsu_commit_uops_0_xcpt_ae_if), // @[tile.scala:159:20]
.io_core_commit_uops_0_xcpt_ma_if (_core_io_lsu_commit_uops_0_xcpt_ma_if), // @[tile.scala:159:20]
.io_core_commit_uops_0_bp_debug_if (_core_io_lsu_commit_uops_0_bp_debug_if), // @[tile.scala:159:20]
.io_core_commit_uops_0_bp_xcpt_if (_core_io_lsu_commit_uops_0_bp_xcpt_if), // @[tile.scala:159:20]
.io_core_commit_uops_0_debug_fsrc (_core_io_lsu_commit_uops_0_debug_fsrc), // @[tile.scala:159:20]
.io_core_commit_uops_0_debug_tsrc (_core_io_lsu_commit_uops_0_debug_tsrc), // @[tile.scala:159:20]
.io_core_commit_uops_1_uopc (_core_io_lsu_commit_uops_1_uopc), // @[tile.scala:159:20]
.io_core_commit_uops_1_inst (_core_io_lsu_commit_uops_1_inst), // @[tile.scala:159:20]
.io_core_commit_uops_1_debug_inst (_core_io_lsu_commit_uops_1_debug_inst), // @[tile.scala:159:20]
.io_core_commit_uops_1_is_rvc (_core_io_lsu_commit_uops_1_is_rvc), // @[tile.scala:159:20]
.io_core_commit_uops_1_debug_pc (_core_io_lsu_commit_uops_1_debug_pc), // @[tile.scala:159:20]
.io_core_commit_uops_1_iq_type (_core_io_lsu_commit_uops_1_iq_type), // @[tile.scala:159:20]
.io_core_commit_uops_1_fu_code (_core_io_lsu_commit_uops_1_fu_code), // @[tile.scala:159:20]
.io_core_commit_uops_1_ctrl_br_type (_core_io_lsu_commit_uops_1_ctrl_br_type), // @[tile.scala:159:20]
.io_core_commit_uops_1_ctrl_op1_sel (_core_io_lsu_commit_uops_1_ctrl_op1_sel), // @[tile.scala:159:20]
.io_core_commit_uops_1_ctrl_op2_sel (_core_io_lsu_commit_uops_1_ctrl_op2_sel), // @[tile.scala:159:20]
.io_core_commit_uops_1_ctrl_imm_sel (_core_io_lsu_commit_uops_1_ctrl_imm_sel), // @[tile.scala:159:20]
.io_core_commit_uops_1_ctrl_op_fcn (_core_io_lsu_commit_uops_1_ctrl_op_fcn), // @[tile.scala:159:20]
.io_core_commit_uops_1_ctrl_fcn_dw (_core_io_lsu_commit_uops_1_ctrl_fcn_dw), // @[tile.scala:159:20]
.io_core_commit_uops_1_ctrl_csr_cmd (_core_io_lsu_commit_uops_1_ctrl_csr_cmd), // @[tile.scala:159:20]
.io_core_commit_uops_1_ctrl_is_load (_core_io_lsu_commit_uops_1_ctrl_is_load), // @[tile.scala:159:20]
.io_core_commit_uops_1_ctrl_is_sta (_core_io_lsu_commit_uops_1_ctrl_is_sta), // @[tile.scala:159:20]
.io_core_commit_uops_1_ctrl_is_std (_core_io_lsu_commit_uops_1_ctrl_is_std), // @[tile.scala:159:20]
.io_core_commit_uops_1_iw_state (_core_io_lsu_commit_uops_1_iw_state), // @[tile.scala:159:20]
.io_core_commit_uops_1_iw_p1_poisoned (_core_io_lsu_commit_uops_1_iw_p1_poisoned), // @[tile.scala:159:20]
.io_core_commit_uops_1_iw_p2_poisoned (_core_io_lsu_commit_uops_1_iw_p2_poisoned), // @[tile.scala:159:20]
.io_core_commit_uops_1_is_br (_core_io_lsu_commit_uops_1_is_br), // @[tile.scala:159:20]
.io_core_commit_uops_1_is_jalr (_core_io_lsu_commit_uops_1_is_jalr), // @[tile.scala:159:20]
.io_core_commit_uops_1_is_jal (_core_io_lsu_commit_uops_1_is_jal), // @[tile.scala:159:20]
.io_core_commit_uops_1_is_sfb (_core_io_lsu_commit_uops_1_is_sfb), // @[tile.scala:159:20]
.io_core_commit_uops_1_br_mask (_core_io_lsu_commit_uops_1_br_mask), // @[tile.scala:159:20]
.io_core_commit_uops_1_br_tag (_core_io_lsu_commit_uops_1_br_tag), // @[tile.scala:159:20]
.io_core_commit_uops_1_ftq_idx (_core_io_lsu_commit_uops_1_ftq_idx), // @[tile.scala:159:20]
.io_core_commit_uops_1_edge_inst (_core_io_lsu_commit_uops_1_edge_inst), // @[tile.scala:159:20]
.io_core_commit_uops_1_pc_lob (_core_io_lsu_commit_uops_1_pc_lob), // @[tile.scala:159:20]
.io_core_commit_uops_1_taken (_core_io_lsu_commit_uops_1_taken), // @[tile.scala:159:20]
.io_core_commit_uops_1_imm_packed (_core_io_lsu_commit_uops_1_imm_packed), // @[tile.scala:159:20]
.io_core_commit_uops_1_csr_addr (_core_io_lsu_commit_uops_1_csr_addr), // @[tile.scala:159:20]
.io_core_commit_uops_1_rob_idx (_core_io_lsu_commit_uops_1_rob_idx), // @[tile.scala:159:20]
.io_core_commit_uops_1_ldq_idx (_core_io_lsu_commit_uops_1_ldq_idx), // @[tile.scala:159:20]
.io_core_commit_uops_1_stq_idx (_core_io_lsu_commit_uops_1_stq_idx), // @[tile.scala:159:20]
.io_core_commit_uops_1_rxq_idx (_core_io_lsu_commit_uops_1_rxq_idx), // @[tile.scala:159:20]
.io_core_commit_uops_1_pdst (_core_io_lsu_commit_uops_1_pdst), // @[tile.scala:159:20]
.io_core_commit_uops_1_prs1 (_core_io_lsu_commit_uops_1_prs1), // @[tile.scala:159:20]
.io_core_commit_uops_1_prs2 (_core_io_lsu_commit_uops_1_prs2), // @[tile.scala:159:20]
.io_core_commit_uops_1_prs3 (_core_io_lsu_commit_uops_1_prs3), // @[tile.scala:159:20]
.io_core_commit_uops_1_ppred (_core_io_lsu_commit_uops_1_ppred), // @[tile.scala:159:20]
.io_core_commit_uops_1_prs1_busy (_core_io_lsu_commit_uops_1_prs1_busy), // @[tile.scala:159:20]
.io_core_commit_uops_1_prs2_busy (_core_io_lsu_commit_uops_1_prs2_busy), // @[tile.scala:159:20]
.io_core_commit_uops_1_prs3_busy (_core_io_lsu_commit_uops_1_prs3_busy), // @[tile.scala:159:20]
.io_core_commit_uops_1_ppred_busy (_core_io_lsu_commit_uops_1_ppred_busy), // @[tile.scala:159:20]
.io_core_commit_uops_1_stale_pdst (_core_io_lsu_commit_uops_1_stale_pdst), // @[tile.scala:159:20]
.io_core_commit_uops_1_exception (_core_io_lsu_commit_uops_1_exception), // @[tile.scala:159:20]
.io_core_commit_uops_1_exc_cause (_core_io_lsu_commit_uops_1_exc_cause), // @[tile.scala:159:20]
.io_core_commit_uops_1_bypassable (_core_io_lsu_commit_uops_1_bypassable), // @[tile.scala:159:20]
.io_core_commit_uops_1_mem_cmd (_core_io_lsu_commit_uops_1_mem_cmd), // @[tile.scala:159:20]
.io_core_commit_uops_1_mem_size (_core_io_lsu_commit_uops_1_mem_size), // @[tile.scala:159:20]
.io_core_commit_uops_1_mem_signed (_core_io_lsu_commit_uops_1_mem_signed), // @[tile.scala:159:20]
.io_core_commit_uops_1_is_fence (_core_io_lsu_commit_uops_1_is_fence), // @[tile.scala:159:20]
.io_core_commit_uops_1_is_fencei (_core_io_lsu_commit_uops_1_is_fencei), // @[tile.scala:159:20]
.io_core_commit_uops_1_is_amo (_core_io_lsu_commit_uops_1_is_amo), // @[tile.scala:159:20]
.io_core_commit_uops_1_uses_ldq (_core_io_lsu_commit_uops_1_uses_ldq), // @[tile.scala:159:20]
.io_core_commit_uops_1_uses_stq (_core_io_lsu_commit_uops_1_uses_stq), // @[tile.scala:159:20]
.io_core_commit_uops_1_is_sys_pc2epc (_core_io_lsu_commit_uops_1_is_sys_pc2epc), // @[tile.scala:159:20]
.io_core_commit_uops_1_is_unique (_core_io_lsu_commit_uops_1_is_unique), // @[tile.scala:159:20]
.io_core_commit_uops_1_flush_on_commit (_core_io_lsu_commit_uops_1_flush_on_commit), // @[tile.scala:159:20]
.io_core_commit_uops_1_ldst_is_rs1 (_core_io_lsu_commit_uops_1_ldst_is_rs1), // @[tile.scala:159:20]
.io_core_commit_uops_1_ldst (_core_io_lsu_commit_uops_1_ldst), // @[tile.scala:159:20]
.io_core_commit_uops_1_lrs1 (_core_io_lsu_commit_uops_1_lrs1), // @[tile.scala:159:20]
.io_core_commit_uops_1_lrs2 (_core_io_lsu_commit_uops_1_lrs2), // @[tile.scala:159:20]
.io_core_commit_uops_1_lrs3 (_core_io_lsu_commit_uops_1_lrs3), // @[tile.scala:159:20]
.io_core_commit_uops_1_ldst_val (_core_io_lsu_commit_uops_1_ldst_val), // @[tile.scala:159:20]
.io_core_commit_uops_1_dst_rtype (_core_io_lsu_commit_uops_1_dst_rtype), // @[tile.scala:159:20]
.io_core_commit_uops_1_lrs1_rtype (_core_io_lsu_commit_uops_1_lrs1_rtype), // @[tile.scala:159:20]
.io_core_commit_uops_1_lrs2_rtype (_core_io_lsu_commit_uops_1_lrs2_rtype), // @[tile.scala:159:20]
.io_core_commit_uops_1_frs3_en (_core_io_lsu_commit_uops_1_frs3_en), // @[tile.scala:159:20]
.io_core_commit_uops_1_fp_val (_core_io_lsu_commit_uops_1_fp_val), // @[tile.scala:159:20]
.io_core_commit_uops_1_fp_single (_core_io_lsu_commit_uops_1_fp_single), // @[tile.scala:159:20]
.io_core_commit_uops_1_xcpt_pf_if (_core_io_lsu_commit_uops_1_xcpt_pf_if), // @[tile.scala:159:20]
.io_core_commit_uops_1_xcpt_ae_if (_core_io_lsu_commit_uops_1_xcpt_ae_if), // @[tile.scala:159:20]
.io_core_commit_uops_1_xcpt_ma_if (_core_io_lsu_commit_uops_1_xcpt_ma_if), // @[tile.scala:159:20]
.io_core_commit_uops_1_bp_debug_if (_core_io_lsu_commit_uops_1_bp_debug_if), // @[tile.scala:159:20]
.io_core_commit_uops_1_bp_xcpt_if (_core_io_lsu_commit_uops_1_bp_xcpt_if), // @[tile.scala:159:20]
.io_core_commit_uops_1_debug_fsrc (_core_io_lsu_commit_uops_1_debug_fsrc), // @[tile.scala:159:20]
.io_core_commit_uops_1_debug_tsrc (_core_io_lsu_commit_uops_1_debug_tsrc), // @[tile.scala:159:20]
.io_core_commit_uops_2_uopc (_core_io_lsu_commit_uops_2_uopc), // @[tile.scala:159:20]
.io_core_commit_uops_2_inst (_core_io_lsu_commit_uops_2_inst), // @[tile.scala:159:20]
.io_core_commit_uops_2_debug_inst (_core_io_lsu_commit_uops_2_debug_inst), // @[tile.scala:159:20]
.io_core_commit_uops_2_is_rvc (_core_io_lsu_commit_uops_2_is_rvc), // @[tile.scala:159:20]
.io_core_commit_uops_2_debug_pc (_core_io_lsu_commit_uops_2_debug_pc), // @[tile.scala:159:20]
.io_core_commit_uops_2_iq_type (_core_io_lsu_commit_uops_2_iq_type), // @[tile.scala:159:20]
.io_core_commit_uops_2_fu_code (_core_io_lsu_commit_uops_2_fu_code), // @[tile.scala:159:20]
.io_core_commit_uops_2_ctrl_br_type (_core_io_lsu_commit_uops_2_ctrl_br_type), // @[tile.scala:159:20]
.io_core_commit_uops_2_ctrl_op1_sel (_core_io_lsu_commit_uops_2_ctrl_op1_sel), // @[tile.scala:159:20]
.io_core_commit_uops_2_ctrl_op2_sel (_core_io_lsu_commit_uops_2_ctrl_op2_sel), // @[tile.scala:159:20]
.io_core_commit_uops_2_ctrl_imm_sel (_core_io_lsu_commit_uops_2_ctrl_imm_sel), // @[tile.scala:159:20]
.io_core_commit_uops_2_ctrl_op_fcn (_core_io_lsu_commit_uops_2_ctrl_op_fcn), // @[tile.scala:159:20]
.io_core_commit_uops_2_ctrl_fcn_dw (_core_io_lsu_commit_uops_2_ctrl_fcn_dw), // @[tile.scala:159:20]
.io_core_commit_uops_2_ctrl_csr_cmd (_core_io_lsu_commit_uops_2_ctrl_csr_cmd), // @[tile.scala:159:20]
.io_core_commit_uops_2_ctrl_is_load (_core_io_lsu_commit_uops_2_ctrl_is_load), // @[tile.scala:159:20]
.io_core_commit_uops_2_ctrl_is_sta (_core_io_lsu_commit_uops_2_ctrl_is_sta), // @[tile.scala:159:20]
.io_core_commit_uops_2_ctrl_is_std (_core_io_lsu_commit_uops_2_ctrl_is_std), // @[tile.scala:159:20]
.io_core_commit_uops_2_iw_state (_core_io_lsu_commit_uops_2_iw_state), // @[tile.scala:159:20]
.io_core_commit_uops_2_iw_p1_poisoned (_core_io_lsu_commit_uops_2_iw_p1_poisoned), // @[tile.scala:159:20]
.io_core_commit_uops_2_iw_p2_poisoned (_core_io_lsu_commit_uops_2_iw_p2_poisoned), // @[tile.scala:159:20]
.io_core_commit_uops_2_is_br (_core_io_lsu_commit_uops_2_is_br), // @[tile.scala:159:20]
.io_core_commit_uops_2_is_jalr (_core_io_lsu_commit_uops_2_is_jalr), // @[tile.scala:159:20]
.io_core_commit_uops_2_is_jal (_core_io_lsu_commit_uops_2_is_jal), // @[tile.scala:159:20]
.io_core_commit_uops_2_is_sfb (_core_io_lsu_commit_uops_2_is_sfb), // @[tile.scala:159:20]
.io_core_commit_uops_2_br_mask (_core_io_lsu_commit_uops_2_br_mask), // @[tile.scala:159:20]
.io_core_commit_uops_2_br_tag (_core_io_lsu_commit_uops_2_br_tag), // @[tile.scala:159:20]
.io_core_commit_uops_2_ftq_idx (_core_io_lsu_commit_uops_2_ftq_idx), // @[tile.scala:159:20]
.io_core_commit_uops_2_edge_inst (_core_io_lsu_commit_uops_2_edge_inst), // @[tile.scala:159:20]
.io_core_commit_uops_2_pc_lob (_core_io_lsu_commit_uops_2_pc_lob), // @[tile.scala:159:20]
.io_core_commit_uops_2_taken (_core_io_lsu_commit_uops_2_taken), // @[tile.scala:159:20]
.io_core_commit_uops_2_imm_packed (_core_io_lsu_commit_uops_2_imm_packed), // @[tile.scala:159:20]
.io_core_commit_uops_2_csr_addr (_core_io_lsu_commit_uops_2_csr_addr), // @[tile.scala:159:20]
.io_core_commit_uops_2_rob_idx (_core_io_lsu_commit_uops_2_rob_idx), // @[tile.scala:159:20]
.io_core_commit_uops_2_ldq_idx (_core_io_lsu_commit_uops_2_ldq_idx), // @[tile.scala:159:20]
.io_core_commit_uops_2_stq_idx (_core_io_lsu_commit_uops_2_stq_idx), // @[tile.scala:159:20]
.io_core_commit_uops_2_rxq_idx (_core_io_lsu_commit_uops_2_rxq_idx), // @[tile.scala:159:20]
.io_core_commit_uops_2_pdst (_core_io_lsu_commit_uops_2_pdst), // @[tile.scala:159:20]
.io_core_commit_uops_2_prs1 (_core_io_lsu_commit_uops_2_prs1), // @[tile.scala:159:20]
.io_core_commit_uops_2_prs2 (_core_io_lsu_commit_uops_2_prs2), // @[tile.scala:159:20]
.io_core_commit_uops_2_prs3 (_core_io_lsu_commit_uops_2_prs3), // @[tile.scala:159:20]
.io_core_commit_uops_2_ppred (_core_io_lsu_commit_uops_2_ppred), // @[tile.scala:159:20]
.io_core_commit_uops_2_prs1_busy (_core_io_lsu_commit_uops_2_prs1_busy), // @[tile.scala:159:20]
.io_core_commit_uops_2_prs2_busy (_core_io_lsu_commit_uops_2_prs2_busy), // @[tile.scala:159:20]
.io_core_commit_uops_2_prs3_busy (_core_io_lsu_commit_uops_2_prs3_busy), // @[tile.scala:159:20]
.io_core_commit_uops_2_ppred_busy (_core_io_lsu_commit_uops_2_ppred_busy), // @[tile.scala:159:20]
.io_core_commit_uops_2_stale_pdst (_core_io_lsu_commit_uops_2_stale_pdst), // @[tile.scala:159:20]
.io_core_commit_uops_2_exception (_core_io_lsu_commit_uops_2_exception), // @[tile.scala:159:20]
.io_core_commit_uops_2_exc_cause (_core_io_lsu_commit_uops_2_exc_cause), // @[tile.scala:159:20]
.io_core_commit_uops_2_bypassable (_core_io_lsu_commit_uops_2_bypassable), // @[tile.scala:159:20]
.io_core_commit_uops_2_mem_cmd (_core_io_lsu_commit_uops_2_mem_cmd), // @[tile.scala:159:20]
.io_core_commit_uops_2_mem_size (_core_io_lsu_commit_uops_2_mem_size), // @[tile.scala:159:20]
.io_core_commit_uops_2_mem_signed (_core_io_lsu_commit_uops_2_mem_signed), // @[tile.scala:159:20]
.io_core_commit_uops_2_is_fence (_core_io_lsu_commit_uops_2_is_fence), // @[tile.scala:159:20]
.io_core_commit_uops_2_is_fencei (_core_io_lsu_commit_uops_2_is_fencei), // @[tile.scala:159:20]
.io_core_commit_uops_2_is_amo (_core_io_lsu_commit_uops_2_is_amo), // @[tile.scala:159:20]
.io_core_commit_uops_2_uses_ldq (_core_io_lsu_commit_uops_2_uses_ldq), // @[tile.scala:159:20]
.io_core_commit_uops_2_uses_stq (_core_io_lsu_commit_uops_2_uses_stq), // @[tile.scala:159:20]
.io_core_commit_uops_2_is_sys_pc2epc (_core_io_lsu_commit_uops_2_is_sys_pc2epc), // @[tile.scala:159:20]
.io_core_commit_uops_2_is_unique (_core_io_lsu_commit_uops_2_is_unique), // @[tile.scala:159:20]
.io_core_commit_uops_2_flush_on_commit (_core_io_lsu_commit_uops_2_flush_on_commit), // @[tile.scala:159:20]
.io_core_commit_uops_2_ldst_is_rs1 (_core_io_lsu_commit_uops_2_ldst_is_rs1), // @[tile.scala:159:20]
.io_core_commit_uops_2_ldst (_core_io_lsu_commit_uops_2_ldst), // @[tile.scala:159:20]
.io_core_commit_uops_2_lrs1 (_core_io_lsu_commit_uops_2_lrs1), // @[tile.scala:159:20]
.io_core_commit_uops_2_lrs2 (_core_io_lsu_commit_uops_2_lrs2), // @[tile.scala:159:20]
.io_core_commit_uops_2_lrs3 (_core_io_lsu_commit_uops_2_lrs3), // @[tile.scala:159:20]
.io_core_commit_uops_2_ldst_val (_core_io_lsu_commit_uops_2_ldst_val), // @[tile.scala:159:20]
.io_core_commit_uops_2_dst_rtype (_core_io_lsu_commit_uops_2_dst_rtype), // @[tile.scala:159:20]
.io_core_commit_uops_2_lrs1_rtype (_core_io_lsu_commit_uops_2_lrs1_rtype), // @[tile.scala:159:20]
.io_core_commit_uops_2_lrs2_rtype (_core_io_lsu_commit_uops_2_lrs2_rtype), // @[tile.scala:159:20]
.io_core_commit_uops_2_frs3_en (_core_io_lsu_commit_uops_2_frs3_en), // @[tile.scala:159:20]
.io_core_commit_uops_2_fp_val (_core_io_lsu_commit_uops_2_fp_val), // @[tile.scala:159:20]
.io_core_commit_uops_2_fp_single (_core_io_lsu_commit_uops_2_fp_single), // @[tile.scala:159:20]
.io_core_commit_uops_2_xcpt_pf_if (_core_io_lsu_commit_uops_2_xcpt_pf_if), // @[tile.scala:159:20]
.io_core_commit_uops_2_xcpt_ae_if (_core_io_lsu_commit_uops_2_xcpt_ae_if), // @[tile.scala:159:20]
.io_core_commit_uops_2_xcpt_ma_if (_core_io_lsu_commit_uops_2_xcpt_ma_if), // @[tile.scala:159:20]
.io_core_commit_uops_2_bp_debug_if (_core_io_lsu_commit_uops_2_bp_debug_if), // @[tile.scala:159:20]
.io_core_commit_uops_2_bp_xcpt_if (_core_io_lsu_commit_uops_2_bp_xcpt_if), // @[tile.scala:159:20]
.io_core_commit_uops_2_debug_fsrc (_core_io_lsu_commit_uops_2_debug_fsrc), // @[tile.scala:159:20]
.io_core_commit_uops_2_debug_tsrc (_core_io_lsu_commit_uops_2_debug_tsrc), // @[tile.scala:159:20]
.io_core_commit_fflags_valid (_core_io_lsu_commit_fflags_valid), // @[tile.scala:159:20]
.io_core_commit_fflags_bits (_core_io_lsu_commit_fflags_bits), // @[tile.scala:159:20]
.io_core_commit_debug_insts_0 (_core_io_lsu_commit_debug_insts_0), // @[tile.scala:159:20]
.io_core_commit_debug_insts_1 (_core_io_lsu_commit_debug_insts_1), // @[tile.scala:159:20]
.io_core_commit_debug_insts_2 (_core_io_lsu_commit_debug_insts_2), // @[tile.scala:159:20]
.io_core_commit_rbk_valids_0 (_core_io_lsu_commit_rbk_valids_0), // @[tile.scala:159:20]
.io_core_commit_rbk_valids_1 (_core_io_lsu_commit_rbk_valids_1), // @[tile.scala:159:20]
.io_core_commit_rbk_valids_2 (_core_io_lsu_commit_rbk_valids_2), // @[tile.scala:159:20]
.io_core_commit_rollback (_core_io_lsu_commit_rollback), // @[tile.scala:159:20]
.io_core_commit_debug_wdata_0 (_core_io_lsu_commit_debug_wdata_0), // @[tile.scala:159:20]
.io_core_commit_debug_wdata_1 (_core_io_lsu_commit_debug_wdata_1), // @[tile.scala:159:20]
.io_core_commit_debug_wdata_2 (_core_io_lsu_commit_debug_wdata_2), // @[tile.scala:159:20]
.io_core_commit_load_at_rob_head (_core_io_lsu_commit_load_at_rob_head), // @[tile.scala:159:20]
.io_core_clr_bsy_0_valid (_lsu_io_core_clr_bsy_0_valid),
.io_core_clr_bsy_0_bits (_lsu_io_core_clr_bsy_0_bits),
.io_core_clr_bsy_1_valid (_lsu_io_core_clr_bsy_1_valid),
.io_core_clr_bsy_1_bits (_lsu_io_core_clr_bsy_1_bits),
.io_core_clr_unsafe_0_bits (_lsu_io_core_clr_unsafe_0_bits),
.io_core_fence_dmem (_core_io_lsu_fence_dmem), // @[tile.scala:159:20]
.io_core_spec_ld_wakeup_0_valid (_lsu_io_core_spec_ld_wakeup_0_valid),
.io_core_spec_ld_wakeup_0_bits (_lsu_io_core_spec_ld_wakeup_0_bits),
.io_core_ld_miss (_lsu_io_core_ld_miss),
.io_core_brupdate_b1_resolve_mask (_core_io_lsu_brupdate_b1_resolve_mask), // @[tile.scala:159:20]
.io_core_brupdate_b1_mispredict_mask (_core_io_lsu_brupdate_b1_mispredict_mask), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_uopc (_core_io_lsu_brupdate_b2_uop_uopc), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_inst (_core_io_lsu_brupdate_b2_uop_inst), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_debug_inst (_core_io_lsu_brupdate_b2_uop_debug_inst), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_is_rvc (_core_io_lsu_brupdate_b2_uop_is_rvc), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_debug_pc (_core_io_lsu_brupdate_b2_uop_debug_pc), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_iq_type (_core_io_lsu_brupdate_b2_uop_iq_type), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_fu_code (_core_io_lsu_brupdate_b2_uop_fu_code), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ctrl_br_type (_core_io_lsu_brupdate_b2_uop_ctrl_br_type), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ctrl_op1_sel (_core_io_lsu_brupdate_b2_uop_ctrl_op1_sel), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ctrl_op2_sel (_core_io_lsu_brupdate_b2_uop_ctrl_op2_sel), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ctrl_imm_sel (_core_io_lsu_brupdate_b2_uop_ctrl_imm_sel), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ctrl_op_fcn (_core_io_lsu_brupdate_b2_uop_ctrl_op_fcn), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ctrl_fcn_dw (_core_io_lsu_brupdate_b2_uop_ctrl_fcn_dw), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ctrl_csr_cmd (_core_io_lsu_brupdate_b2_uop_ctrl_csr_cmd), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ctrl_is_load (_core_io_lsu_brupdate_b2_uop_ctrl_is_load), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ctrl_is_sta (_core_io_lsu_brupdate_b2_uop_ctrl_is_sta), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ctrl_is_std (_core_io_lsu_brupdate_b2_uop_ctrl_is_std), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_iw_state (_core_io_lsu_brupdate_b2_uop_iw_state), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_iw_p1_poisoned (_core_io_lsu_brupdate_b2_uop_iw_p1_poisoned), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_iw_p2_poisoned (_core_io_lsu_brupdate_b2_uop_iw_p2_poisoned), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_is_br (_core_io_lsu_brupdate_b2_uop_is_br), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_is_jalr (_core_io_lsu_brupdate_b2_uop_is_jalr), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_is_jal (_core_io_lsu_brupdate_b2_uop_is_jal), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_is_sfb (_core_io_lsu_brupdate_b2_uop_is_sfb), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_br_mask (_core_io_lsu_brupdate_b2_uop_br_mask), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_br_tag (_core_io_lsu_brupdate_b2_uop_br_tag), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ftq_idx (_core_io_lsu_brupdate_b2_uop_ftq_idx), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_edge_inst (_core_io_lsu_brupdate_b2_uop_edge_inst), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_pc_lob (_core_io_lsu_brupdate_b2_uop_pc_lob), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_taken (_core_io_lsu_brupdate_b2_uop_taken), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_imm_packed (_core_io_lsu_brupdate_b2_uop_imm_packed), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_csr_addr (_core_io_lsu_brupdate_b2_uop_csr_addr), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_rob_idx (_core_io_lsu_brupdate_b2_uop_rob_idx), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ldq_idx (_core_io_lsu_brupdate_b2_uop_ldq_idx), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_stq_idx (_core_io_lsu_brupdate_b2_uop_stq_idx), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_rxq_idx (_core_io_lsu_brupdate_b2_uop_rxq_idx), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_pdst (_core_io_lsu_brupdate_b2_uop_pdst), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_prs1 (_core_io_lsu_brupdate_b2_uop_prs1), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_prs2 (_core_io_lsu_brupdate_b2_uop_prs2), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_prs3 (_core_io_lsu_brupdate_b2_uop_prs3), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ppred (_core_io_lsu_brupdate_b2_uop_ppred), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_prs1_busy (_core_io_lsu_brupdate_b2_uop_prs1_busy), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_prs2_busy (_core_io_lsu_brupdate_b2_uop_prs2_busy), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_prs3_busy (_core_io_lsu_brupdate_b2_uop_prs3_busy), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ppred_busy (_core_io_lsu_brupdate_b2_uop_ppred_busy), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_stale_pdst (_core_io_lsu_brupdate_b2_uop_stale_pdst), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_exception (_core_io_lsu_brupdate_b2_uop_exception), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_exc_cause (_core_io_lsu_brupdate_b2_uop_exc_cause), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_bypassable (_core_io_lsu_brupdate_b2_uop_bypassable), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_mem_cmd (_core_io_lsu_brupdate_b2_uop_mem_cmd), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_mem_size (_core_io_lsu_brupdate_b2_uop_mem_size), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_mem_signed (_core_io_lsu_brupdate_b2_uop_mem_signed), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_is_fence (_core_io_lsu_brupdate_b2_uop_is_fence), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_is_fencei (_core_io_lsu_brupdate_b2_uop_is_fencei), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_is_amo (_core_io_lsu_brupdate_b2_uop_is_amo), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_uses_ldq (_core_io_lsu_brupdate_b2_uop_uses_ldq), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_uses_stq (_core_io_lsu_brupdate_b2_uop_uses_stq), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_is_sys_pc2epc (_core_io_lsu_brupdate_b2_uop_is_sys_pc2epc), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_is_unique (_core_io_lsu_brupdate_b2_uop_is_unique), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_flush_on_commit (_core_io_lsu_brupdate_b2_uop_flush_on_commit), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ldst_is_rs1 (_core_io_lsu_brupdate_b2_uop_ldst_is_rs1), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ldst (_core_io_lsu_brupdate_b2_uop_ldst), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_lrs1 (_core_io_lsu_brupdate_b2_uop_lrs1), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_lrs2 (_core_io_lsu_brupdate_b2_uop_lrs2), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_lrs3 (_core_io_lsu_brupdate_b2_uop_lrs3), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ldst_val (_core_io_lsu_brupdate_b2_uop_ldst_val), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_dst_rtype (_core_io_lsu_brupdate_b2_uop_dst_rtype), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_lrs1_rtype (_core_io_lsu_brupdate_b2_uop_lrs1_rtype), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_lrs2_rtype (_core_io_lsu_brupdate_b2_uop_lrs2_rtype), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_frs3_en (_core_io_lsu_brupdate_b2_uop_frs3_en), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_fp_val (_core_io_lsu_brupdate_b2_uop_fp_val), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_fp_single (_core_io_lsu_brupdate_b2_uop_fp_single), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_xcpt_pf_if (_core_io_lsu_brupdate_b2_uop_xcpt_pf_if), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_xcpt_ae_if (_core_io_lsu_brupdate_b2_uop_xcpt_ae_if), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_xcpt_ma_if (_core_io_lsu_brupdate_b2_uop_xcpt_ma_if), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_bp_debug_if (_core_io_lsu_brupdate_b2_uop_bp_debug_if), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_bp_xcpt_if (_core_io_lsu_brupdate_b2_uop_bp_xcpt_if), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_debug_fsrc (_core_io_lsu_brupdate_b2_uop_debug_fsrc), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_debug_tsrc (_core_io_lsu_brupdate_b2_uop_debug_tsrc), // @[tile.scala:159:20]
.io_core_brupdate_b2_valid (_core_io_lsu_brupdate_b2_valid), // @[tile.scala:159:20]
.io_core_brupdate_b2_mispredict (_core_io_lsu_brupdate_b2_mispredict), // @[tile.scala:159:20]
.io_core_brupdate_b2_taken (_core_io_lsu_brupdate_b2_taken), // @[tile.scala:159:20]
.io_core_brupdate_b2_cfi_type (_core_io_lsu_brupdate_b2_cfi_type), // @[tile.scala:159:20]
.io_core_brupdate_b2_pc_sel (_core_io_lsu_brupdate_b2_pc_sel), // @[tile.scala:159:20]
.io_core_brupdate_b2_jalr_target (_core_io_lsu_brupdate_b2_jalr_target), // @[tile.scala:159:20]
.io_core_brupdate_b2_target_offset (_core_io_lsu_brupdate_b2_target_offset), // @[tile.scala:159:20]
.io_core_rob_pnr_idx (_core_io_lsu_rob_pnr_idx), // @[tile.scala:159:20]
.io_core_rob_head_idx (_core_io_lsu_rob_head_idx), // @[tile.scala:159:20]
.io_core_exception (_core_io_lsu_exception), // @[tile.scala:159:20]
.io_core_fencei_rdy (_lsu_io_core_fencei_rdy),
.io_core_lxcpt_valid (_lsu_io_core_lxcpt_valid),
.io_core_lxcpt_bits_uop_uopc (_lsu_io_core_lxcpt_bits_uop_uopc),
.io_core_lxcpt_bits_uop_inst (_lsu_io_core_lxcpt_bits_uop_inst),
.io_core_lxcpt_bits_uop_debug_inst (_lsu_io_core_lxcpt_bits_uop_debug_inst),
.io_core_lxcpt_bits_uop_is_rvc (_lsu_io_core_lxcpt_bits_uop_is_rvc),
.io_core_lxcpt_bits_uop_debug_pc (_lsu_io_core_lxcpt_bits_uop_debug_pc),
.io_core_lxcpt_bits_uop_iq_type (_lsu_io_core_lxcpt_bits_uop_iq_type),
.io_core_lxcpt_bits_uop_fu_code (_lsu_io_core_lxcpt_bits_uop_fu_code),
.io_core_lxcpt_bits_uop_ctrl_br_type (_lsu_io_core_lxcpt_bits_uop_ctrl_br_type),
.io_core_lxcpt_bits_uop_ctrl_op1_sel (_lsu_io_core_lxcpt_bits_uop_ctrl_op1_sel),
.io_core_lxcpt_bits_uop_ctrl_op2_sel (_lsu_io_core_lxcpt_bits_uop_ctrl_op2_sel),
.io_core_lxcpt_bits_uop_ctrl_imm_sel (_lsu_io_core_lxcpt_bits_uop_ctrl_imm_sel),
.io_core_lxcpt_bits_uop_ctrl_op_fcn (_lsu_io_core_lxcpt_bits_uop_ctrl_op_fcn),
.io_core_lxcpt_bits_uop_ctrl_fcn_dw (_lsu_io_core_lxcpt_bits_uop_ctrl_fcn_dw),
.io_core_lxcpt_bits_uop_ctrl_csr_cmd (_lsu_io_core_lxcpt_bits_uop_ctrl_csr_cmd),
.io_core_lxcpt_bits_uop_ctrl_is_load (_lsu_io_core_lxcpt_bits_uop_ctrl_is_load),
.io_core_lxcpt_bits_uop_ctrl_is_sta (_lsu_io_core_lxcpt_bits_uop_ctrl_is_sta),
.io_core_lxcpt_bits_uop_ctrl_is_std (_lsu_io_core_lxcpt_bits_uop_ctrl_is_std),
.io_core_lxcpt_bits_uop_iw_state (_lsu_io_core_lxcpt_bits_uop_iw_state),
.io_core_lxcpt_bits_uop_iw_p1_poisoned (_lsu_io_core_lxcpt_bits_uop_iw_p1_poisoned),
.io_core_lxcpt_bits_uop_iw_p2_poisoned (_lsu_io_core_lxcpt_bits_uop_iw_p2_poisoned),
.io_core_lxcpt_bits_uop_is_br (_lsu_io_core_lxcpt_bits_uop_is_br),
.io_core_lxcpt_bits_uop_is_jalr (_lsu_io_core_lxcpt_bits_uop_is_jalr),
.io_core_lxcpt_bits_uop_is_jal (_lsu_io_core_lxcpt_bits_uop_is_jal),
.io_core_lxcpt_bits_uop_is_sfb (_lsu_io_core_lxcpt_bits_uop_is_sfb),
.io_core_lxcpt_bits_uop_br_mask (_lsu_io_core_lxcpt_bits_uop_br_mask),
.io_core_lxcpt_bits_uop_br_tag (_lsu_io_core_lxcpt_bits_uop_br_tag),
.io_core_lxcpt_bits_uop_ftq_idx (_lsu_io_core_lxcpt_bits_uop_ftq_idx),
.io_core_lxcpt_bits_uop_edge_inst (_lsu_io_core_lxcpt_bits_uop_edge_inst),
.io_core_lxcpt_bits_uop_pc_lob (_lsu_io_core_lxcpt_bits_uop_pc_lob),
.io_core_lxcpt_bits_uop_taken (_lsu_io_core_lxcpt_bits_uop_taken),
.io_core_lxcpt_bits_uop_imm_packed (_lsu_io_core_lxcpt_bits_uop_imm_packed),
.io_core_lxcpt_bits_uop_csr_addr (_lsu_io_core_lxcpt_bits_uop_csr_addr),
.io_core_lxcpt_bits_uop_rob_idx (_lsu_io_core_lxcpt_bits_uop_rob_idx),
.io_core_lxcpt_bits_uop_ldq_idx (_lsu_io_core_lxcpt_bits_uop_ldq_idx),
.io_core_lxcpt_bits_uop_stq_idx (_lsu_io_core_lxcpt_bits_uop_stq_idx),
.io_core_lxcpt_bits_uop_rxq_idx (_lsu_io_core_lxcpt_bits_uop_rxq_idx),
.io_core_lxcpt_bits_uop_pdst (_lsu_io_core_lxcpt_bits_uop_pdst),
.io_core_lxcpt_bits_uop_prs1 (_lsu_io_core_lxcpt_bits_uop_prs1),
.io_core_lxcpt_bits_uop_prs2 (_lsu_io_core_lxcpt_bits_uop_prs2),
.io_core_lxcpt_bits_uop_prs3 (_lsu_io_core_lxcpt_bits_uop_prs3),
.io_core_lxcpt_bits_uop_ppred (_lsu_io_core_lxcpt_bits_uop_ppred),
.io_core_lxcpt_bits_uop_prs1_busy (_lsu_io_core_lxcpt_bits_uop_prs1_busy),
.io_core_lxcpt_bits_uop_prs2_busy (_lsu_io_core_lxcpt_bits_uop_prs2_busy),
.io_core_lxcpt_bits_uop_prs3_busy (_lsu_io_core_lxcpt_bits_uop_prs3_busy),
.io_core_lxcpt_bits_uop_ppred_busy (_lsu_io_core_lxcpt_bits_uop_ppred_busy),
.io_core_lxcpt_bits_uop_stale_pdst (_lsu_io_core_lxcpt_bits_uop_stale_pdst),
.io_core_lxcpt_bits_uop_exception (_lsu_io_core_lxcpt_bits_uop_exception),
.io_core_lxcpt_bits_uop_exc_cause (_lsu_io_core_lxcpt_bits_uop_exc_cause),
.io_core_lxcpt_bits_uop_bypassable (_lsu_io_core_lxcpt_bits_uop_bypassable),
.io_core_lxcpt_bits_uop_mem_cmd (_lsu_io_core_lxcpt_bits_uop_mem_cmd),
.io_core_lxcpt_bits_uop_mem_size (_lsu_io_core_lxcpt_bits_uop_mem_size),
.io_core_lxcpt_bits_uop_mem_signed (_lsu_io_core_lxcpt_bits_uop_mem_signed),
.io_core_lxcpt_bits_uop_is_fence (_lsu_io_core_lxcpt_bits_uop_is_fence),
.io_core_lxcpt_bits_uop_is_fencei (_lsu_io_core_lxcpt_bits_uop_is_fencei),
.io_core_lxcpt_bits_uop_is_amo (_lsu_io_core_lxcpt_bits_uop_is_amo),
.io_core_lxcpt_bits_uop_uses_ldq (_lsu_io_core_lxcpt_bits_uop_uses_ldq),
.io_core_lxcpt_bits_uop_uses_stq (_lsu_io_core_lxcpt_bits_uop_uses_stq),
.io_core_lxcpt_bits_uop_is_sys_pc2epc (_lsu_io_core_lxcpt_bits_uop_is_sys_pc2epc),
.io_core_lxcpt_bits_uop_is_unique (_lsu_io_core_lxcpt_bits_uop_is_unique),
.io_core_lxcpt_bits_uop_flush_on_commit (_lsu_io_core_lxcpt_bits_uop_flush_on_commit),
.io_core_lxcpt_bits_uop_ldst_is_rs1 (_lsu_io_core_lxcpt_bits_uop_ldst_is_rs1),
.io_core_lxcpt_bits_uop_ldst (_lsu_io_core_lxcpt_bits_uop_ldst),
.io_core_lxcpt_bits_uop_lrs1 (_lsu_io_core_lxcpt_bits_uop_lrs1),
.io_core_lxcpt_bits_uop_lrs2 (_lsu_io_core_lxcpt_bits_uop_lrs2),
.io_core_lxcpt_bits_uop_lrs3 (_lsu_io_core_lxcpt_bits_uop_lrs3),
.io_core_lxcpt_bits_uop_ldst_val (_lsu_io_core_lxcpt_bits_uop_ldst_val),
.io_core_lxcpt_bits_uop_dst_rtype (_lsu_io_core_lxcpt_bits_uop_dst_rtype),
.io_core_lxcpt_bits_uop_lrs1_rtype (_lsu_io_core_lxcpt_bits_uop_lrs1_rtype),
.io_core_lxcpt_bits_uop_lrs2_rtype (_lsu_io_core_lxcpt_bits_uop_lrs2_rtype),
.io_core_lxcpt_bits_uop_frs3_en (_lsu_io_core_lxcpt_bits_uop_frs3_en),
.io_core_lxcpt_bits_uop_fp_val (_lsu_io_core_lxcpt_bits_uop_fp_val),
.io_core_lxcpt_bits_uop_fp_single (_lsu_io_core_lxcpt_bits_uop_fp_single),
.io_core_lxcpt_bits_uop_xcpt_pf_if (_lsu_io_core_lxcpt_bits_uop_xcpt_pf_if),
.io_core_lxcpt_bits_uop_xcpt_ae_if (_lsu_io_core_lxcpt_bits_uop_xcpt_ae_if),
.io_core_lxcpt_bits_uop_xcpt_ma_if (_lsu_io_core_lxcpt_bits_uop_xcpt_ma_if),
.io_core_lxcpt_bits_uop_bp_debug_if (_lsu_io_core_lxcpt_bits_uop_bp_debug_if),
.io_core_lxcpt_bits_uop_bp_xcpt_if (_lsu_io_core_lxcpt_bits_uop_bp_xcpt_if),
.io_core_lxcpt_bits_uop_debug_fsrc (_lsu_io_core_lxcpt_bits_uop_debug_fsrc),
.io_core_lxcpt_bits_uop_debug_tsrc (_lsu_io_core_lxcpt_bits_uop_debug_tsrc),
.io_core_lxcpt_bits_cause (_lsu_io_core_lxcpt_bits_cause),
.io_core_lxcpt_bits_badvaddr (_lsu_io_core_lxcpt_bits_badvaddr),
.io_core_tsc_reg (_core_io_lsu_tsc_reg), // @[tile.scala:159:20]
.io_core_perf_acquire (_lsu_io_core_perf_acquire),
.io_core_perf_release (_lsu_io_core_perf_release),
.io_core_perf_tlbMiss (_lsu_io_core_perf_tlbMiss),
.io_dmem_req_ready (_dcache_io_lsu_req_ready), // @[tile.scala:132:54]
.io_dmem_req_valid (_lsu_io_dmem_req_valid),
.io_dmem_req_bits_0_valid (_lsu_io_dmem_req_bits_0_valid),
.io_dmem_req_bits_0_bits_uop_uopc (_lsu_io_dmem_req_bits_0_bits_uop_uopc),
.io_dmem_req_bits_0_bits_uop_inst (_lsu_io_dmem_req_bits_0_bits_uop_inst),
.io_dmem_req_bits_0_bits_uop_debug_inst (_lsu_io_dmem_req_bits_0_bits_uop_debug_inst),
.io_dmem_req_bits_0_bits_uop_is_rvc (_lsu_io_dmem_req_bits_0_bits_uop_is_rvc),
.io_dmem_req_bits_0_bits_uop_debug_pc (_lsu_io_dmem_req_bits_0_bits_uop_debug_pc),
.io_dmem_req_bits_0_bits_uop_iq_type (_lsu_io_dmem_req_bits_0_bits_uop_iq_type),
.io_dmem_req_bits_0_bits_uop_fu_code (_lsu_io_dmem_req_bits_0_bits_uop_fu_code),
.io_dmem_req_bits_0_bits_uop_ctrl_br_type (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_br_type),
.io_dmem_req_bits_0_bits_uop_ctrl_op1_sel (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_op1_sel),
.io_dmem_req_bits_0_bits_uop_ctrl_op2_sel (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_op2_sel),
.io_dmem_req_bits_0_bits_uop_ctrl_imm_sel (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_imm_sel),
.io_dmem_req_bits_0_bits_uop_ctrl_op_fcn (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_op_fcn),
.io_dmem_req_bits_0_bits_uop_ctrl_fcn_dw (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_fcn_dw),
.io_dmem_req_bits_0_bits_uop_ctrl_csr_cmd (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_csr_cmd),
.io_dmem_req_bits_0_bits_uop_ctrl_is_load (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_is_load),
.io_dmem_req_bits_0_bits_uop_ctrl_is_sta (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_is_sta),
.io_dmem_req_bits_0_bits_uop_ctrl_is_std (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_is_std),
.io_dmem_req_bits_0_bits_uop_iw_state (_lsu_io_dmem_req_bits_0_bits_uop_iw_state),
.io_dmem_req_bits_0_bits_uop_iw_p1_poisoned (_lsu_io_dmem_req_bits_0_bits_uop_iw_p1_poisoned),
.io_dmem_req_bits_0_bits_uop_iw_p2_poisoned (_lsu_io_dmem_req_bits_0_bits_uop_iw_p2_poisoned),
.io_dmem_req_bits_0_bits_uop_is_br (_lsu_io_dmem_req_bits_0_bits_uop_is_br),
.io_dmem_req_bits_0_bits_uop_is_jalr (_lsu_io_dmem_req_bits_0_bits_uop_is_jalr),
.io_dmem_req_bits_0_bits_uop_is_jal (_lsu_io_dmem_req_bits_0_bits_uop_is_jal),
.io_dmem_req_bits_0_bits_uop_is_sfb (_lsu_io_dmem_req_bits_0_bits_uop_is_sfb),
.io_dmem_req_bits_0_bits_uop_br_mask (_lsu_io_dmem_req_bits_0_bits_uop_br_mask),
.io_dmem_req_bits_0_bits_uop_br_tag (_lsu_io_dmem_req_bits_0_bits_uop_br_tag),
.io_dmem_req_bits_0_bits_uop_ftq_idx (_lsu_io_dmem_req_bits_0_bits_uop_ftq_idx),
.io_dmem_req_bits_0_bits_uop_edge_inst (_lsu_io_dmem_req_bits_0_bits_uop_edge_inst),
.io_dmem_req_bits_0_bits_uop_pc_lob (_lsu_io_dmem_req_bits_0_bits_uop_pc_lob),
.io_dmem_req_bits_0_bits_uop_taken (_lsu_io_dmem_req_bits_0_bits_uop_taken),
.io_dmem_req_bits_0_bits_uop_imm_packed (_lsu_io_dmem_req_bits_0_bits_uop_imm_packed),
.io_dmem_req_bits_0_bits_uop_csr_addr (_lsu_io_dmem_req_bits_0_bits_uop_csr_addr),
.io_dmem_req_bits_0_bits_uop_rob_idx (_lsu_io_dmem_req_bits_0_bits_uop_rob_idx),
.io_dmem_req_bits_0_bits_uop_ldq_idx (_lsu_io_dmem_req_bits_0_bits_uop_ldq_idx),
.io_dmem_req_bits_0_bits_uop_stq_idx (_lsu_io_dmem_req_bits_0_bits_uop_stq_idx),
.io_dmem_req_bits_0_bits_uop_rxq_idx (_lsu_io_dmem_req_bits_0_bits_uop_rxq_idx),
.io_dmem_req_bits_0_bits_uop_pdst (_lsu_io_dmem_req_bits_0_bits_uop_pdst),
.io_dmem_req_bits_0_bits_uop_prs1 (_lsu_io_dmem_req_bits_0_bits_uop_prs1),
.io_dmem_req_bits_0_bits_uop_prs2 (_lsu_io_dmem_req_bits_0_bits_uop_prs2),
.io_dmem_req_bits_0_bits_uop_prs3 (_lsu_io_dmem_req_bits_0_bits_uop_prs3),
.io_dmem_req_bits_0_bits_uop_ppred (_lsu_io_dmem_req_bits_0_bits_uop_ppred),
.io_dmem_req_bits_0_bits_uop_prs1_busy (_lsu_io_dmem_req_bits_0_bits_uop_prs1_busy),
.io_dmem_req_bits_0_bits_uop_prs2_busy (_lsu_io_dmem_req_bits_0_bits_uop_prs2_busy),
.io_dmem_req_bits_0_bits_uop_prs3_busy (_lsu_io_dmem_req_bits_0_bits_uop_prs3_busy),
.io_dmem_req_bits_0_bits_uop_ppred_busy (_lsu_io_dmem_req_bits_0_bits_uop_ppred_busy),
.io_dmem_req_bits_0_bits_uop_stale_pdst (_lsu_io_dmem_req_bits_0_bits_uop_stale_pdst),
.io_dmem_req_bits_0_bits_uop_exception (_lsu_io_dmem_req_bits_0_bits_uop_exception),
.io_dmem_req_bits_0_bits_uop_exc_cause (_lsu_io_dmem_req_bits_0_bits_uop_exc_cause),
.io_dmem_req_bits_0_bits_uop_bypassable (_lsu_io_dmem_req_bits_0_bits_uop_bypassable),
.io_dmem_req_bits_0_bits_uop_mem_cmd (_lsu_io_dmem_req_bits_0_bits_uop_mem_cmd),
.io_dmem_req_bits_0_bits_uop_mem_size (_lsu_io_dmem_req_bits_0_bits_uop_mem_size),
.io_dmem_req_bits_0_bits_uop_mem_signed (_lsu_io_dmem_req_bits_0_bits_uop_mem_signed),
.io_dmem_req_bits_0_bits_uop_is_fence (_lsu_io_dmem_req_bits_0_bits_uop_is_fence),
.io_dmem_req_bits_0_bits_uop_is_fencei (_lsu_io_dmem_req_bits_0_bits_uop_is_fencei),
.io_dmem_req_bits_0_bits_uop_is_amo (_lsu_io_dmem_req_bits_0_bits_uop_is_amo),
.io_dmem_req_bits_0_bits_uop_uses_ldq (_lsu_io_dmem_req_bits_0_bits_uop_uses_ldq),
.io_dmem_req_bits_0_bits_uop_uses_stq (_lsu_io_dmem_req_bits_0_bits_uop_uses_stq),
.io_dmem_req_bits_0_bits_uop_is_sys_pc2epc (_lsu_io_dmem_req_bits_0_bits_uop_is_sys_pc2epc),
.io_dmem_req_bits_0_bits_uop_is_unique (_lsu_io_dmem_req_bits_0_bits_uop_is_unique),
.io_dmem_req_bits_0_bits_uop_flush_on_commit (_lsu_io_dmem_req_bits_0_bits_uop_flush_on_commit),
.io_dmem_req_bits_0_bits_uop_ldst_is_rs1 (_lsu_io_dmem_req_bits_0_bits_uop_ldst_is_rs1),
.io_dmem_req_bits_0_bits_uop_ldst (_lsu_io_dmem_req_bits_0_bits_uop_ldst),
.io_dmem_req_bits_0_bits_uop_lrs1 (_lsu_io_dmem_req_bits_0_bits_uop_lrs1),
.io_dmem_req_bits_0_bits_uop_lrs2 (_lsu_io_dmem_req_bits_0_bits_uop_lrs2),
.io_dmem_req_bits_0_bits_uop_lrs3 (_lsu_io_dmem_req_bits_0_bits_uop_lrs3),
.io_dmem_req_bits_0_bits_uop_ldst_val (_lsu_io_dmem_req_bits_0_bits_uop_ldst_val),
.io_dmem_req_bits_0_bits_uop_dst_rtype (_lsu_io_dmem_req_bits_0_bits_uop_dst_rtype),
.io_dmem_req_bits_0_bits_uop_lrs1_rtype (_lsu_io_dmem_req_bits_0_bits_uop_lrs1_rtype),
.io_dmem_req_bits_0_bits_uop_lrs2_rtype (_lsu_io_dmem_req_bits_0_bits_uop_lrs2_rtype),
.io_dmem_req_bits_0_bits_uop_frs3_en (_lsu_io_dmem_req_bits_0_bits_uop_frs3_en),
.io_dmem_req_bits_0_bits_uop_fp_val (_lsu_io_dmem_req_bits_0_bits_uop_fp_val),
.io_dmem_req_bits_0_bits_uop_fp_single (_lsu_io_dmem_req_bits_0_bits_uop_fp_single),
.io_dmem_req_bits_0_bits_uop_xcpt_pf_if (_lsu_io_dmem_req_bits_0_bits_uop_xcpt_pf_if),
.io_dmem_req_bits_0_bits_uop_xcpt_ae_if (_lsu_io_dmem_req_bits_0_bits_uop_xcpt_ae_if),
.io_dmem_req_bits_0_bits_uop_xcpt_ma_if (_lsu_io_dmem_req_bits_0_bits_uop_xcpt_ma_if),
.io_dmem_req_bits_0_bits_uop_bp_debug_if (_lsu_io_dmem_req_bits_0_bits_uop_bp_debug_if),
.io_dmem_req_bits_0_bits_uop_bp_xcpt_if (_lsu_io_dmem_req_bits_0_bits_uop_bp_xcpt_if),
.io_dmem_req_bits_0_bits_uop_debug_fsrc (_lsu_io_dmem_req_bits_0_bits_uop_debug_fsrc),
.io_dmem_req_bits_0_bits_uop_debug_tsrc (_lsu_io_dmem_req_bits_0_bits_uop_debug_tsrc),
.io_dmem_req_bits_0_bits_addr (_lsu_io_dmem_req_bits_0_bits_addr),
.io_dmem_req_bits_0_bits_data (_lsu_io_dmem_req_bits_0_bits_data),
.io_dmem_req_bits_0_bits_is_hella (_lsu_io_dmem_req_bits_0_bits_is_hella),
.io_dmem_s1_kill_0 (_lsu_io_dmem_s1_kill_0),
.io_dmem_resp_0_valid (_dcache_io_lsu_resp_0_valid), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_uopc (_dcache_io_lsu_resp_0_bits_uop_uopc), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_inst (_dcache_io_lsu_resp_0_bits_uop_inst), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_debug_inst (_dcache_io_lsu_resp_0_bits_uop_debug_inst), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_is_rvc (_dcache_io_lsu_resp_0_bits_uop_is_rvc), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_debug_pc (_dcache_io_lsu_resp_0_bits_uop_debug_pc), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_iq_type (_dcache_io_lsu_resp_0_bits_uop_iq_type), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_fu_code (_dcache_io_lsu_resp_0_bits_uop_fu_code), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ctrl_br_type (_dcache_io_lsu_resp_0_bits_uop_ctrl_br_type), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ctrl_op1_sel (_dcache_io_lsu_resp_0_bits_uop_ctrl_op1_sel), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ctrl_op2_sel (_dcache_io_lsu_resp_0_bits_uop_ctrl_op2_sel), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ctrl_imm_sel (_dcache_io_lsu_resp_0_bits_uop_ctrl_imm_sel), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ctrl_op_fcn (_dcache_io_lsu_resp_0_bits_uop_ctrl_op_fcn), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ctrl_fcn_dw (_dcache_io_lsu_resp_0_bits_uop_ctrl_fcn_dw), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ctrl_csr_cmd (_dcache_io_lsu_resp_0_bits_uop_ctrl_csr_cmd), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ctrl_is_load (_dcache_io_lsu_resp_0_bits_uop_ctrl_is_load), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ctrl_is_sta (_dcache_io_lsu_resp_0_bits_uop_ctrl_is_sta), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ctrl_is_std (_dcache_io_lsu_resp_0_bits_uop_ctrl_is_std), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_iw_state (_dcache_io_lsu_resp_0_bits_uop_iw_state), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_iw_p1_poisoned (_dcache_io_lsu_resp_0_bits_uop_iw_p1_poisoned), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_iw_p2_poisoned (_dcache_io_lsu_resp_0_bits_uop_iw_p2_poisoned), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_is_br (_dcache_io_lsu_resp_0_bits_uop_is_br), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_is_jalr (_dcache_io_lsu_resp_0_bits_uop_is_jalr), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_is_jal (_dcache_io_lsu_resp_0_bits_uop_is_jal), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_is_sfb (_dcache_io_lsu_resp_0_bits_uop_is_sfb), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_br_mask (_dcache_io_lsu_resp_0_bits_uop_br_mask), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_br_tag (_dcache_io_lsu_resp_0_bits_uop_br_tag), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ftq_idx (_dcache_io_lsu_resp_0_bits_uop_ftq_idx), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_edge_inst (_dcache_io_lsu_resp_0_bits_uop_edge_inst), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_pc_lob (_dcache_io_lsu_resp_0_bits_uop_pc_lob), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_taken (_dcache_io_lsu_resp_0_bits_uop_taken), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_imm_packed (_dcache_io_lsu_resp_0_bits_uop_imm_packed), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_csr_addr (_dcache_io_lsu_resp_0_bits_uop_csr_addr), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_rob_idx (_dcache_io_lsu_resp_0_bits_uop_rob_idx), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ldq_idx (_dcache_io_lsu_resp_0_bits_uop_ldq_idx), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_stq_idx (_dcache_io_lsu_resp_0_bits_uop_stq_idx), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_rxq_idx (_dcache_io_lsu_resp_0_bits_uop_rxq_idx), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_pdst (_dcache_io_lsu_resp_0_bits_uop_pdst), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_prs1 (_dcache_io_lsu_resp_0_bits_uop_prs1), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_prs2 (_dcache_io_lsu_resp_0_bits_uop_prs2), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_prs3 (_dcache_io_lsu_resp_0_bits_uop_prs3), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ppred (_dcache_io_lsu_resp_0_bits_uop_ppred), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_prs1_busy (_dcache_io_lsu_resp_0_bits_uop_prs1_busy), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_prs2_busy (_dcache_io_lsu_resp_0_bits_uop_prs2_busy), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_prs3_busy (_dcache_io_lsu_resp_0_bits_uop_prs3_busy), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ppred_busy (_dcache_io_lsu_resp_0_bits_uop_ppred_busy), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_stale_pdst (_dcache_io_lsu_resp_0_bits_uop_stale_pdst), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_exception (_dcache_io_lsu_resp_0_bits_uop_exception), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_exc_cause (_dcache_io_lsu_resp_0_bits_uop_exc_cause), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_bypassable (_dcache_io_lsu_resp_0_bits_uop_bypassable), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_mem_cmd (_dcache_io_lsu_resp_0_bits_uop_mem_cmd), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_mem_size (_dcache_io_lsu_resp_0_bits_uop_mem_size), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_mem_signed (_dcache_io_lsu_resp_0_bits_uop_mem_signed), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_is_fence (_dcache_io_lsu_resp_0_bits_uop_is_fence), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_is_fencei (_dcache_io_lsu_resp_0_bits_uop_is_fencei), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_is_amo (_dcache_io_lsu_resp_0_bits_uop_is_amo), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_uses_ldq (_dcache_io_lsu_resp_0_bits_uop_uses_ldq), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_uses_stq (_dcache_io_lsu_resp_0_bits_uop_uses_stq), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_is_sys_pc2epc (_dcache_io_lsu_resp_0_bits_uop_is_sys_pc2epc), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_is_unique (_dcache_io_lsu_resp_0_bits_uop_is_unique), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_flush_on_commit (_dcache_io_lsu_resp_0_bits_uop_flush_on_commit), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ldst_is_rs1 (_dcache_io_lsu_resp_0_bits_uop_ldst_is_rs1), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ldst (_dcache_io_lsu_resp_0_bits_uop_ldst), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_lrs1 (_dcache_io_lsu_resp_0_bits_uop_lrs1), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_lrs2 (_dcache_io_lsu_resp_0_bits_uop_lrs2), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_lrs3 (_dcache_io_lsu_resp_0_bits_uop_lrs3), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ldst_val (_dcache_io_lsu_resp_0_bits_uop_ldst_val), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_dst_rtype (_dcache_io_lsu_resp_0_bits_uop_dst_rtype), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_lrs1_rtype (_dcache_io_lsu_resp_0_bits_uop_lrs1_rtype), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_lrs2_rtype (_dcache_io_lsu_resp_0_bits_uop_lrs2_rtype), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_frs3_en (_dcache_io_lsu_resp_0_bits_uop_frs3_en), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_fp_val (_dcache_io_lsu_resp_0_bits_uop_fp_val), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_fp_single (_dcache_io_lsu_resp_0_bits_uop_fp_single), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_xcpt_pf_if (_dcache_io_lsu_resp_0_bits_uop_xcpt_pf_if), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_xcpt_ae_if (_dcache_io_lsu_resp_0_bits_uop_xcpt_ae_if), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_xcpt_ma_if (_dcache_io_lsu_resp_0_bits_uop_xcpt_ma_if), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_bp_debug_if (_dcache_io_lsu_resp_0_bits_uop_bp_debug_if), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_bp_xcpt_if (_dcache_io_lsu_resp_0_bits_uop_bp_xcpt_if), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_debug_fsrc (_dcache_io_lsu_resp_0_bits_uop_debug_fsrc), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_debug_tsrc (_dcache_io_lsu_resp_0_bits_uop_debug_tsrc), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_data (_dcache_io_lsu_resp_0_bits_data), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_is_hella (_dcache_io_lsu_resp_0_bits_is_hella), // @[tile.scala:132:54]
.io_dmem_nack_0_valid (_dcache_io_lsu_nack_0_valid), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_uopc (_dcache_io_lsu_nack_0_bits_uop_uopc), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_inst (_dcache_io_lsu_nack_0_bits_uop_inst), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_debug_inst (_dcache_io_lsu_nack_0_bits_uop_debug_inst), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_is_rvc (_dcache_io_lsu_nack_0_bits_uop_is_rvc), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_debug_pc (_dcache_io_lsu_nack_0_bits_uop_debug_pc), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_iq_type (_dcache_io_lsu_nack_0_bits_uop_iq_type), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_fu_code (_dcache_io_lsu_nack_0_bits_uop_fu_code), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ctrl_br_type (_dcache_io_lsu_nack_0_bits_uop_ctrl_br_type), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ctrl_op1_sel (_dcache_io_lsu_nack_0_bits_uop_ctrl_op1_sel), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ctrl_op2_sel (_dcache_io_lsu_nack_0_bits_uop_ctrl_op2_sel), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ctrl_imm_sel (_dcache_io_lsu_nack_0_bits_uop_ctrl_imm_sel), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ctrl_op_fcn (_dcache_io_lsu_nack_0_bits_uop_ctrl_op_fcn), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ctrl_fcn_dw (_dcache_io_lsu_nack_0_bits_uop_ctrl_fcn_dw), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ctrl_csr_cmd (_dcache_io_lsu_nack_0_bits_uop_ctrl_csr_cmd), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ctrl_is_load (_dcache_io_lsu_nack_0_bits_uop_ctrl_is_load), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ctrl_is_sta (_dcache_io_lsu_nack_0_bits_uop_ctrl_is_sta), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ctrl_is_std (_dcache_io_lsu_nack_0_bits_uop_ctrl_is_std), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_iw_state (_dcache_io_lsu_nack_0_bits_uop_iw_state), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_iw_p1_poisoned (_dcache_io_lsu_nack_0_bits_uop_iw_p1_poisoned), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_iw_p2_poisoned (_dcache_io_lsu_nack_0_bits_uop_iw_p2_poisoned), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_is_br (_dcache_io_lsu_nack_0_bits_uop_is_br), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_is_jalr (_dcache_io_lsu_nack_0_bits_uop_is_jalr), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_is_jal (_dcache_io_lsu_nack_0_bits_uop_is_jal), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_is_sfb (_dcache_io_lsu_nack_0_bits_uop_is_sfb), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_br_mask (_dcache_io_lsu_nack_0_bits_uop_br_mask), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_br_tag (_dcache_io_lsu_nack_0_bits_uop_br_tag), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ftq_idx (_dcache_io_lsu_nack_0_bits_uop_ftq_idx), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_edge_inst (_dcache_io_lsu_nack_0_bits_uop_edge_inst), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_pc_lob (_dcache_io_lsu_nack_0_bits_uop_pc_lob), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_taken (_dcache_io_lsu_nack_0_bits_uop_taken), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_imm_packed (_dcache_io_lsu_nack_0_bits_uop_imm_packed), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_csr_addr (_dcache_io_lsu_nack_0_bits_uop_csr_addr), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_rob_idx (_dcache_io_lsu_nack_0_bits_uop_rob_idx), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ldq_idx (_dcache_io_lsu_nack_0_bits_uop_ldq_idx), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_stq_idx (_dcache_io_lsu_nack_0_bits_uop_stq_idx), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_rxq_idx (_dcache_io_lsu_nack_0_bits_uop_rxq_idx), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_pdst (_dcache_io_lsu_nack_0_bits_uop_pdst), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_prs1 (_dcache_io_lsu_nack_0_bits_uop_prs1), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_prs2 (_dcache_io_lsu_nack_0_bits_uop_prs2), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_prs3 (_dcache_io_lsu_nack_0_bits_uop_prs3), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ppred (_dcache_io_lsu_nack_0_bits_uop_ppred), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_prs1_busy (_dcache_io_lsu_nack_0_bits_uop_prs1_busy), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_prs2_busy (_dcache_io_lsu_nack_0_bits_uop_prs2_busy), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_prs3_busy (_dcache_io_lsu_nack_0_bits_uop_prs3_busy), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ppred_busy (_dcache_io_lsu_nack_0_bits_uop_ppred_busy), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_stale_pdst (_dcache_io_lsu_nack_0_bits_uop_stale_pdst), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_exception (_dcache_io_lsu_nack_0_bits_uop_exception), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_exc_cause (_dcache_io_lsu_nack_0_bits_uop_exc_cause), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_bypassable (_dcache_io_lsu_nack_0_bits_uop_bypassable), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_mem_cmd (_dcache_io_lsu_nack_0_bits_uop_mem_cmd), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_mem_size (_dcache_io_lsu_nack_0_bits_uop_mem_size), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_mem_signed (_dcache_io_lsu_nack_0_bits_uop_mem_signed), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_is_fence (_dcache_io_lsu_nack_0_bits_uop_is_fence), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_is_fencei (_dcache_io_lsu_nack_0_bits_uop_is_fencei), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_is_amo (_dcache_io_lsu_nack_0_bits_uop_is_amo), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_uses_ldq (_dcache_io_lsu_nack_0_bits_uop_uses_ldq), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_uses_stq (_dcache_io_lsu_nack_0_bits_uop_uses_stq), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_is_sys_pc2epc (_dcache_io_lsu_nack_0_bits_uop_is_sys_pc2epc), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_is_unique (_dcache_io_lsu_nack_0_bits_uop_is_unique), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_flush_on_commit (_dcache_io_lsu_nack_0_bits_uop_flush_on_commit), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ldst_is_rs1 (_dcache_io_lsu_nack_0_bits_uop_ldst_is_rs1), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ldst (_dcache_io_lsu_nack_0_bits_uop_ldst), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_lrs1 (_dcache_io_lsu_nack_0_bits_uop_lrs1), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_lrs2 (_dcache_io_lsu_nack_0_bits_uop_lrs2), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_lrs3 (_dcache_io_lsu_nack_0_bits_uop_lrs3), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ldst_val (_dcache_io_lsu_nack_0_bits_uop_ldst_val), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_dst_rtype (_dcache_io_lsu_nack_0_bits_uop_dst_rtype), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_lrs1_rtype (_dcache_io_lsu_nack_0_bits_uop_lrs1_rtype), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_lrs2_rtype (_dcache_io_lsu_nack_0_bits_uop_lrs2_rtype), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_frs3_en (_dcache_io_lsu_nack_0_bits_uop_frs3_en), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_fp_val (_dcache_io_lsu_nack_0_bits_uop_fp_val), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_fp_single (_dcache_io_lsu_nack_0_bits_uop_fp_single), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_xcpt_pf_if (_dcache_io_lsu_nack_0_bits_uop_xcpt_pf_if), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_xcpt_ae_if (_dcache_io_lsu_nack_0_bits_uop_xcpt_ae_if), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_xcpt_ma_if (_dcache_io_lsu_nack_0_bits_uop_xcpt_ma_if), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_bp_debug_if (_dcache_io_lsu_nack_0_bits_uop_bp_debug_if), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_bp_xcpt_if (_dcache_io_lsu_nack_0_bits_uop_bp_xcpt_if), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_debug_fsrc (_dcache_io_lsu_nack_0_bits_uop_debug_fsrc), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_debug_tsrc (_dcache_io_lsu_nack_0_bits_uop_debug_tsrc), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_addr (_dcache_io_lsu_nack_0_bits_addr), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_data (_dcache_io_lsu_nack_0_bits_data), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_is_hella (_dcache_io_lsu_nack_0_bits_is_hella), // @[tile.scala:132:54]
.io_dmem_brupdate_b1_resolve_mask (_lsu_io_dmem_brupdate_b1_resolve_mask),
.io_dmem_brupdate_b1_mispredict_mask (_lsu_io_dmem_brupdate_b1_mispredict_mask),
.io_dmem_brupdate_b2_uop_uopc (_lsu_io_dmem_brupdate_b2_uop_uopc),
.io_dmem_brupdate_b2_uop_inst (_lsu_io_dmem_brupdate_b2_uop_inst),
.io_dmem_brupdate_b2_uop_debug_inst (_lsu_io_dmem_brupdate_b2_uop_debug_inst),
.io_dmem_brupdate_b2_uop_is_rvc (_lsu_io_dmem_brupdate_b2_uop_is_rvc),
.io_dmem_brupdate_b2_uop_debug_pc (_lsu_io_dmem_brupdate_b2_uop_debug_pc),
.io_dmem_brupdate_b2_uop_iq_type (_lsu_io_dmem_brupdate_b2_uop_iq_type),
.io_dmem_brupdate_b2_uop_fu_code (_lsu_io_dmem_brupdate_b2_uop_fu_code),
.io_dmem_brupdate_b2_uop_ctrl_br_type (_lsu_io_dmem_brupdate_b2_uop_ctrl_br_type),
.io_dmem_brupdate_b2_uop_ctrl_op1_sel (_lsu_io_dmem_brupdate_b2_uop_ctrl_op1_sel),
.io_dmem_brupdate_b2_uop_ctrl_op2_sel (_lsu_io_dmem_brupdate_b2_uop_ctrl_op2_sel),
.io_dmem_brupdate_b2_uop_ctrl_imm_sel (_lsu_io_dmem_brupdate_b2_uop_ctrl_imm_sel),
.io_dmem_brupdate_b2_uop_ctrl_op_fcn (_lsu_io_dmem_brupdate_b2_uop_ctrl_op_fcn),
.io_dmem_brupdate_b2_uop_ctrl_fcn_dw (_lsu_io_dmem_brupdate_b2_uop_ctrl_fcn_dw),
.io_dmem_brupdate_b2_uop_ctrl_csr_cmd (_lsu_io_dmem_brupdate_b2_uop_ctrl_csr_cmd),
.io_dmem_brupdate_b2_uop_ctrl_is_load (_lsu_io_dmem_brupdate_b2_uop_ctrl_is_load),
.io_dmem_brupdate_b2_uop_ctrl_is_sta (_lsu_io_dmem_brupdate_b2_uop_ctrl_is_sta),
.io_dmem_brupdate_b2_uop_ctrl_is_std (_lsu_io_dmem_brupdate_b2_uop_ctrl_is_std),
.io_dmem_brupdate_b2_uop_iw_state (_lsu_io_dmem_brupdate_b2_uop_iw_state),
.io_dmem_brupdate_b2_uop_iw_p1_poisoned (_lsu_io_dmem_brupdate_b2_uop_iw_p1_poisoned),
.io_dmem_brupdate_b2_uop_iw_p2_poisoned (_lsu_io_dmem_brupdate_b2_uop_iw_p2_poisoned),
.io_dmem_brupdate_b2_uop_is_br (_lsu_io_dmem_brupdate_b2_uop_is_br),
.io_dmem_brupdate_b2_uop_is_jalr (_lsu_io_dmem_brupdate_b2_uop_is_jalr),
.io_dmem_brupdate_b2_uop_is_jal (_lsu_io_dmem_brupdate_b2_uop_is_jal),
.io_dmem_brupdate_b2_uop_is_sfb (_lsu_io_dmem_brupdate_b2_uop_is_sfb),
.io_dmem_brupdate_b2_uop_br_mask (_lsu_io_dmem_brupdate_b2_uop_br_mask),
.io_dmem_brupdate_b2_uop_br_tag (_lsu_io_dmem_brupdate_b2_uop_br_tag),
.io_dmem_brupdate_b2_uop_ftq_idx (_lsu_io_dmem_brupdate_b2_uop_ftq_idx),
.io_dmem_brupdate_b2_uop_edge_inst (_lsu_io_dmem_brupdate_b2_uop_edge_inst),
.io_dmem_brupdate_b2_uop_pc_lob (_lsu_io_dmem_brupdate_b2_uop_pc_lob),
.io_dmem_brupdate_b2_uop_taken (_lsu_io_dmem_brupdate_b2_uop_taken),
.io_dmem_brupdate_b2_uop_imm_packed (_lsu_io_dmem_brupdate_b2_uop_imm_packed),
.io_dmem_brupdate_b2_uop_csr_addr (_lsu_io_dmem_brupdate_b2_uop_csr_addr),
.io_dmem_brupdate_b2_uop_rob_idx (_lsu_io_dmem_brupdate_b2_uop_rob_idx),
.io_dmem_brupdate_b2_uop_ldq_idx (_lsu_io_dmem_brupdate_b2_uop_ldq_idx),
.io_dmem_brupdate_b2_uop_stq_idx (_lsu_io_dmem_brupdate_b2_uop_stq_idx),
.io_dmem_brupdate_b2_uop_rxq_idx (_lsu_io_dmem_brupdate_b2_uop_rxq_idx),
.io_dmem_brupdate_b2_uop_pdst (_lsu_io_dmem_brupdate_b2_uop_pdst),
.io_dmem_brupdate_b2_uop_prs1 (_lsu_io_dmem_brupdate_b2_uop_prs1),
.io_dmem_brupdate_b2_uop_prs2 (_lsu_io_dmem_brupdate_b2_uop_prs2),
.io_dmem_brupdate_b2_uop_prs3 (_lsu_io_dmem_brupdate_b2_uop_prs3),
.io_dmem_brupdate_b2_uop_ppred (_lsu_io_dmem_brupdate_b2_uop_ppred),
.io_dmem_brupdate_b2_uop_prs1_busy (_lsu_io_dmem_brupdate_b2_uop_prs1_busy),
.io_dmem_brupdate_b2_uop_prs2_busy (_lsu_io_dmem_brupdate_b2_uop_prs2_busy),
.io_dmem_brupdate_b2_uop_prs3_busy (_lsu_io_dmem_brupdate_b2_uop_prs3_busy),
.io_dmem_brupdate_b2_uop_ppred_busy (_lsu_io_dmem_brupdate_b2_uop_ppred_busy),
.io_dmem_brupdate_b2_uop_stale_pdst (_lsu_io_dmem_brupdate_b2_uop_stale_pdst),
.io_dmem_brupdate_b2_uop_exception (_lsu_io_dmem_brupdate_b2_uop_exception),
.io_dmem_brupdate_b2_uop_exc_cause (_lsu_io_dmem_brupdate_b2_uop_exc_cause),
.io_dmem_brupdate_b2_uop_bypassable (_lsu_io_dmem_brupdate_b2_uop_bypassable),
.io_dmem_brupdate_b2_uop_mem_cmd (_lsu_io_dmem_brupdate_b2_uop_mem_cmd),
.io_dmem_brupdate_b2_uop_mem_size (_lsu_io_dmem_brupdate_b2_uop_mem_size),
.io_dmem_brupdate_b2_uop_mem_signed (_lsu_io_dmem_brupdate_b2_uop_mem_signed),
.io_dmem_brupdate_b2_uop_is_fence (_lsu_io_dmem_brupdate_b2_uop_is_fence),
.io_dmem_brupdate_b2_uop_is_fencei (_lsu_io_dmem_brupdate_b2_uop_is_fencei),
.io_dmem_brupdate_b2_uop_is_amo (_lsu_io_dmem_brupdate_b2_uop_is_amo),
.io_dmem_brupdate_b2_uop_uses_ldq (_lsu_io_dmem_brupdate_b2_uop_uses_ldq),
.io_dmem_brupdate_b2_uop_uses_stq (_lsu_io_dmem_brupdate_b2_uop_uses_stq),
.io_dmem_brupdate_b2_uop_is_sys_pc2epc (_lsu_io_dmem_brupdate_b2_uop_is_sys_pc2epc),
.io_dmem_brupdate_b2_uop_is_unique (_lsu_io_dmem_brupdate_b2_uop_is_unique),
.io_dmem_brupdate_b2_uop_flush_on_commit (_lsu_io_dmem_brupdate_b2_uop_flush_on_commit),
.io_dmem_brupdate_b2_uop_ldst_is_rs1 (_lsu_io_dmem_brupdate_b2_uop_ldst_is_rs1),
.io_dmem_brupdate_b2_uop_ldst (_lsu_io_dmem_brupdate_b2_uop_ldst),
.io_dmem_brupdate_b2_uop_lrs1 (_lsu_io_dmem_brupdate_b2_uop_lrs1),
.io_dmem_brupdate_b2_uop_lrs2 (_lsu_io_dmem_brupdate_b2_uop_lrs2),
.io_dmem_brupdate_b2_uop_lrs3 (_lsu_io_dmem_brupdate_b2_uop_lrs3),
.io_dmem_brupdate_b2_uop_ldst_val (_lsu_io_dmem_brupdate_b2_uop_ldst_val),
.io_dmem_brupdate_b2_uop_dst_rtype (_lsu_io_dmem_brupdate_b2_uop_dst_rtype),
.io_dmem_brupdate_b2_uop_lrs1_rtype (_lsu_io_dmem_brupdate_b2_uop_lrs1_rtype),
.io_dmem_brupdate_b2_uop_lrs2_rtype (_lsu_io_dmem_brupdate_b2_uop_lrs2_rtype),
.io_dmem_brupdate_b2_uop_frs3_en (_lsu_io_dmem_brupdate_b2_uop_frs3_en),
.io_dmem_brupdate_b2_uop_fp_val (_lsu_io_dmem_brupdate_b2_uop_fp_val),
.io_dmem_brupdate_b2_uop_fp_single (_lsu_io_dmem_brupdate_b2_uop_fp_single),
.io_dmem_brupdate_b2_uop_xcpt_pf_if (_lsu_io_dmem_brupdate_b2_uop_xcpt_pf_if),
.io_dmem_brupdate_b2_uop_xcpt_ae_if (_lsu_io_dmem_brupdate_b2_uop_xcpt_ae_if),
.io_dmem_brupdate_b2_uop_xcpt_ma_if (_lsu_io_dmem_brupdate_b2_uop_xcpt_ma_if),
.io_dmem_brupdate_b2_uop_bp_debug_if (_lsu_io_dmem_brupdate_b2_uop_bp_debug_if),
.io_dmem_brupdate_b2_uop_bp_xcpt_if (_lsu_io_dmem_brupdate_b2_uop_bp_xcpt_if),
.io_dmem_brupdate_b2_uop_debug_fsrc (_lsu_io_dmem_brupdate_b2_uop_debug_fsrc),
.io_dmem_brupdate_b2_uop_debug_tsrc (_lsu_io_dmem_brupdate_b2_uop_debug_tsrc),
.io_dmem_brupdate_b2_valid (_lsu_io_dmem_brupdate_b2_valid),
.io_dmem_brupdate_b2_mispredict (_lsu_io_dmem_brupdate_b2_mispredict),
.io_dmem_brupdate_b2_taken (_lsu_io_dmem_brupdate_b2_taken),
.io_dmem_brupdate_b2_cfi_type (_lsu_io_dmem_brupdate_b2_cfi_type),
.io_dmem_brupdate_b2_pc_sel (_lsu_io_dmem_brupdate_b2_pc_sel),
.io_dmem_brupdate_b2_jalr_target (_lsu_io_dmem_brupdate_b2_jalr_target),
.io_dmem_brupdate_b2_target_offset (_lsu_io_dmem_brupdate_b2_target_offset),
.io_dmem_exception (_lsu_io_dmem_exception),
.io_dmem_rob_pnr_idx (_lsu_io_dmem_rob_pnr_idx),
.io_dmem_rob_head_idx (_lsu_io_dmem_rob_head_idx),
.io_dmem_release_ready (_lsu_io_dmem_release_ready),
.io_dmem_release_valid (_dcache_io_lsu_release_valid), // @[tile.scala:132:54]
.io_dmem_release_bits_opcode (_dcache_io_lsu_release_bits_opcode), // @[tile.scala:132:54]
.io_dmem_release_bits_param (_dcache_io_lsu_release_bits_param), // @[tile.scala:132:54]
.io_dmem_release_bits_size (_dcache_io_lsu_release_bits_size), // @[tile.scala:132:54]
.io_dmem_release_bits_source (_dcache_io_lsu_release_bits_source), // @[tile.scala:132:54]
.io_dmem_release_bits_address (_dcache_io_lsu_release_bits_address), // @[tile.scala:132:54]
.io_dmem_release_bits_data (_dcache_io_lsu_release_bits_data), // @[tile.scala:132:54]
.io_dmem_force_order (_lsu_io_dmem_force_order),
.io_dmem_ordered (_dcache_io_lsu_ordered), // @[tile.scala:132:54]
.io_dmem_perf_acquire (_dcache_io_lsu_perf_acquire), // @[tile.scala:132:54]
.io_dmem_perf_release (_dcache_io_lsu_perf_release), // @[tile.scala:132:54]
.io_hellacache_req_ready (_lsu_io_hellacache_req_ready),
.io_hellacache_req_valid (_hellaCacheArb_io_mem_req_valid), // @[tile.scala:243:29]
.io_hellacache_req_bits_addr (_hellaCacheArb_io_mem_req_bits_addr), // @[tile.scala:243:29]
.io_hellacache_req_bits_dv (_hellaCacheArb_io_mem_req_bits_dv), // @[tile.scala:243:29]
.io_hellacache_s1_kill (_hellaCacheArb_io_mem_s1_kill), // @[tile.scala:243:29]
.io_hellacache_s2_nack (_lsu_io_hellacache_s2_nack),
.io_hellacache_resp_valid (_lsu_io_hellacache_resp_valid),
.io_hellacache_resp_bits_addr (_lsu_io_hellacache_resp_bits_addr),
.io_hellacache_resp_bits_data (_lsu_io_hellacache_resp_bits_data),
.io_hellacache_s2_xcpt_ma_ld (_lsu_io_hellacache_s2_xcpt_ma_ld),
.io_hellacache_s2_xcpt_ma_st (_lsu_io_hellacache_s2_xcpt_ma_st),
.io_hellacache_s2_xcpt_pf_ld (_lsu_io_hellacache_s2_xcpt_pf_ld),
.io_hellacache_s2_xcpt_pf_st (_lsu_io_hellacache_s2_xcpt_pf_st),
.io_hellacache_s2_xcpt_gf_ld (_lsu_io_hellacache_s2_xcpt_gf_ld),
.io_hellacache_s2_xcpt_gf_st (_lsu_io_hellacache_s2_xcpt_gf_st),
.io_hellacache_s2_xcpt_ae_ld (_lsu_io_hellacache_s2_xcpt_ae_ld),
.io_hellacache_s2_xcpt_ae_st (_lsu_io_hellacache_s2_xcpt_ae_st),
.io_hellacache_store_pending (_lsu_io_hellacache_store_pending)
); // @[tile.scala:160:20]
PTW_3 ptw ( // @[tile.scala:237:20]
.clock (clock),
.reset (reset),
.io_requestor_0_req_ready (_ptw_io_requestor_0_req_ready),
.io_requestor_0_req_valid (_lsu_io_ptw_req_valid), // @[tile.scala:160:20]
.io_requestor_0_req_bits_valid (_lsu_io_ptw_req_bits_valid), // @[tile.scala:160:20]
.io_requestor_0_req_bits_bits_addr (_lsu_io_ptw_req_bits_bits_addr), // @[tile.scala:160:20]
.io_requestor_0_resp_valid (_ptw_io_requestor_0_resp_valid),
.io_requestor_0_resp_bits_ae_ptw (_ptw_io_requestor_0_resp_bits_ae_ptw),
.io_requestor_0_resp_bits_ae_final (_ptw_io_requestor_0_resp_bits_ae_final),
.io_requestor_0_resp_bits_pf (_ptw_io_requestor_0_resp_bits_pf),
.io_requestor_0_resp_bits_gf (_ptw_io_requestor_0_resp_bits_gf),
.io_requestor_0_resp_bits_hr (_ptw_io_requestor_0_resp_bits_hr),
.io_requestor_0_resp_bits_hw (_ptw_io_requestor_0_resp_bits_hw),
.io_requestor_0_resp_bits_hx (_ptw_io_requestor_0_resp_bits_hx),
.io_requestor_0_resp_bits_pte_reserved_for_future (_ptw_io_requestor_0_resp_bits_pte_reserved_for_future),
.io_requestor_0_resp_bits_pte_ppn (_ptw_io_requestor_0_resp_bits_pte_ppn),
.io_requestor_0_resp_bits_pte_reserved_for_software (_ptw_io_requestor_0_resp_bits_pte_reserved_for_software),
.io_requestor_0_resp_bits_pte_d (_ptw_io_requestor_0_resp_bits_pte_d),
.io_requestor_0_resp_bits_pte_a (_ptw_io_requestor_0_resp_bits_pte_a),
.io_requestor_0_resp_bits_pte_g (_ptw_io_requestor_0_resp_bits_pte_g),
.io_requestor_0_resp_bits_pte_u (_ptw_io_requestor_0_resp_bits_pte_u),
.io_requestor_0_resp_bits_pte_x (_ptw_io_requestor_0_resp_bits_pte_x),
.io_requestor_0_resp_bits_pte_w (_ptw_io_requestor_0_resp_bits_pte_w),
.io_requestor_0_resp_bits_pte_r (_ptw_io_requestor_0_resp_bits_pte_r),
.io_requestor_0_resp_bits_pte_v (_ptw_io_requestor_0_resp_bits_pte_v),
.io_requestor_0_resp_bits_level (_ptw_io_requestor_0_resp_bits_level),
.io_requestor_0_resp_bits_homogeneous (_ptw_io_requestor_0_resp_bits_homogeneous),
.io_requestor_0_resp_bits_gpa_valid (_ptw_io_requestor_0_resp_bits_gpa_valid),
.io_requestor_0_resp_bits_gpa_bits (_ptw_io_requestor_0_resp_bits_gpa_bits),
.io_requestor_0_resp_bits_gpa_is_pte (_ptw_io_requestor_0_resp_bits_gpa_is_pte),
.io_requestor_0_ptbr_mode (_ptw_io_requestor_0_ptbr_mode),
.io_requestor_0_ptbr_ppn (_ptw_io_requestor_0_ptbr_ppn),
.io_requestor_0_status_debug (_ptw_io_requestor_0_status_debug),
.io_requestor_0_status_cease (_ptw_io_requestor_0_status_cease),
.io_requestor_0_status_wfi (_ptw_io_requestor_0_status_wfi),
.io_requestor_0_status_dprv (_ptw_io_requestor_0_status_dprv),
.io_requestor_0_status_dv (_ptw_io_requestor_0_status_dv),
.io_requestor_0_status_prv (_ptw_io_requestor_0_status_prv),
.io_requestor_0_status_v (_ptw_io_requestor_0_status_v),
.io_requestor_0_status_sd (_ptw_io_requestor_0_status_sd),
.io_requestor_0_status_mpv (_ptw_io_requestor_0_status_mpv),
.io_requestor_0_status_gva (_ptw_io_requestor_0_status_gva),
.io_requestor_0_status_tsr (_ptw_io_requestor_0_status_tsr),
.io_requestor_0_status_tw (_ptw_io_requestor_0_status_tw),
.io_requestor_0_status_tvm (_ptw_io_requestor_0_status_tvm),
.io_requestor_0_status_mxr (_ptw_io_requestor_0_status_mxr),
.io_requestor_0_status_sum (_ptw_io_requestor_0_status_sum),
.io_requestor_0_status_mprv (_ptw_io_requestor_0_status_mprv),
.io_requestor_0_status_fs (_ptw_io_requestor_0_status_fs),
.io_requestor_0_status_mpp (_ptw_io_requestor_0_status_mpp),
.io_requestor_0_status_spp (_ptw_io_requestor_0_status_spp),
.io_requestor_0_status_mpie (_ptw_io_requestor_0_status_mpie),
.io_requestor_0_status_spie (_ptw_io_requestor_0_status_spie),
.io_requestor_0_status_mie (_ptw_io_requestor_0_status_mie),
.io_requestor_0_status_sie (_ptw_io_requestor_0_status_sie),
.io_requestor_0_pmp_0_cfg_l (_ptw_io_requestor_0_pmp_0_cfg_l),
.io_requestor_0_pmp_0_cfg_a (_ptw_io_requestor_0_pmp_0_cfg_a),
.io_requestor_0_pmp_0_cfg_x (_ptw_io_requestor_0_pmp_0_cfg_x),
.io_requestor_0_pmp_0_cfg_w (_ptw_io_requestor_0_pmp_0_cfg_w),
.io_requestor_0_pmp_0_cfg_r (_ptw_io_requestor_0_pmp_0_cfg_r),
.io_requestor_0_pmp_0_addr (_ptw_io_requestor_0_pmp_0_addr),
.io_requestor_0_pmp_0_mask (_ptw_io_requestor_0_pmp_0_mask),
.io_requestor_0_pmp_1_cfg_l (_ptw_io_requestor_0_pmp_1_cfg_l),
.io_requestor_0_pmp_1_cfg_a (_ptw_io_requestor_0_pmp_1_cfg_a),
.io_requestor_0_pmp_1_cfg_x (_ptw_io_requestor_0_pmp_1_cfg_x),
.io_requestor_0_pmp_1_cfg_w (_ptw_io_requestor_0_pmp_1_cfg_w),
.io_requestor_0_pmp_1_cfg_r (_ptw_io_requestor_0_pmp_1_cfg_r),
.io_requestor_0_pmp_1_addr (_ptw_io_requestor_0_pmp_1_addr),
.io_requestor_0_pmp_1_mask (_ptw_io_requestor_0_pmp_1_mask),
.io_requestor_0_pmp_2_cfg_l (_ptw_io_requestor_0_pmp_2_cfg_l),
.io_requestor_0_pmp_2_cfg_a (_ptw_io_requestor_0_pmp_2_cfg_a),
.io_requestor_0_pmp_2_cfg_x (_ptw_io_requestor_0_pmp_2_cfg_x),
.io_requestor_0_pmp_2_cfg_w (_ptw_io_requestor_0_pmp_2_cfg_w),
.io_requestor_0_pmp_2_cfg_r (_ptw_io_requestor_0_pmp_2_cfg_r),
.io_requestor_0_pmp_2_addr (_ptw_io_requestor_0_pmp_2_addr),
.io_requestor_0_pmp_2_mask (_ptw_io_requestor_0_pmp_2_mask),
.io_requestor_0_pmp_3_cfg_l (_ptw_io_requestor_0_pmp_3_cfg_l),
.io_requestor_0_pmp_3_cfg_a (_ptw_io_requestor_0_pmp_3_cfg_a),
.io_requestor_0_pmp_3_cfg_x (_ptw_io_requestor_0_pmp_3_cfg_x),
.io_requestor_0_pmp_3_cfg_w (_ptw_io_requestor_0_pmp_3_cfg_w),
.io_requestor_0_pmp_3_cfg_r (_ptw_io_requestor_0_pmp_3_cfg_r),
.io_requestor_0_pmp_3_addr (_ptw_io_requestor_0_pmp_3_addr),
.io_requestor_0_pmp_3_mask (_ptw_io_requestor_0_pmp_3_mask),
.io_requestor_0_pmp_4_cfg_l (_ptw_io_requestor_0_pmp_4_cfg_l),
.io_requestor_0_pmp_4_cfg_a (_ptw_io_requestor_0_pmp_4_cfg_a),
.io_requestor_0_pmp_4_cfg_x (_ptw_io_requestor_0_pmp_4_cfg_x),
.io_requestor_0_pmp_4_cfg_w (_ptw_io_requestor_0_pmp_4_cfg_w),
.io_requestor_0_pmp_4_cfg_r (_ptw_io_requestor_0_pmp_4_cfg_r),
.io_requestor_0_pmp_4_addr (_ptw_io_requestor_0_pmp_4_addr),
.io_requestor_0_pmp_4_mask (_ptw_io_requestor_0_pmp_4_mask),
.io_requestor_0_pmp_5_cfg_l (_ptw_io_requestor_0_pmp_5_cfg_l),
.io_requestor_0_pmp_5_cfg_a (_ptw_io_requestor_0_pmp_5_cfg_a),
.io_requestor_0_pmp_5_cfg_x (_ptw_io_requestor_0_pmp_5_cfg_x),
.io_requestor_0_pmp_5_cfg_w (_ptw_io_requestor_0_pmp_5_cfg_w),
.io_requestor_0_pmp_5_cfg_r (_ptw_io_requestor_0_pmp_5_cfg_r),
.io_requestor_0_pmp_5_addr (_ptw_io_requestor_0_pmp_5_addr),
.io_requestor_0_pmp_5_mask (_ptw_io_requestor_0_pmp_5_mask),
.io_requestor_0_pmp_6_cfg_l (_ptw_io_requestor_0_pmp_6_cfg_l),
.io_requestor_0_pmp_6_cfg_a (_ptw_io_requestor_0_pmp_6_cfg_a),
.io_requestor_0_pmp_6_cfg_x (_ptw_io_requestor_0_pmp_6_cfg_x),
.io_requestor_0_pmp_6_cfg_w (_ptw_io_requestor_0_pmp_6_cfg_w),
.io_requestor_0_pmp_6_cfg_r (_ptw_io_requestor_0_pmp_6_cfg_r),
.io_requestor_0_pmp_6_addr (_ptw_io_requestor_0_pmp_6_addr),
.io_requestor_0_pmp_6_mask (_ptw_io_requestor_0_pmp_6_mask),
.io_requestor_0_pmp_7_cfg_l (_ptw_io_requestor_0_pmp_7_cfg_l),
.io_requestor_0_pmp_7_cfg_a (_ptw_io_requestor_0_pmp_7_cfg_a),
.io_requestor_0_pmp_7_cfg_x (_ptw_io_requestor_0_pmp_7_cfg_x),
.io_requestor_0_pmp_7_cfg_w (_ptw_io_requestor_0_pmp_7_cfg_w),
.io_requestor_0_pmp_7_cfg_r (_ptw_io_requestor_0_pmp_7_cfg_r),
.io_requestor_0_pmp_7_addr (_ptw_io_requestor_0_pmp_7_addr),
.io_requestor_0_pmp_7_mask (_ptw_io_requestor_0_pmp_7_mask),
.io_requestor_1_req_ready (_ptw_io_requestor_1_req_ready),
.io_requestor_1_req_valid (_frontend_io_ptw_req_valid), // @[tile.scala:138:28]
.io_requestor_1_req_bits_bits_addr (_frontend_io_ptw_req_bits_bits_addr), // @[tile.scala:138:28]
.io_requestor_1_req_bits_bits_need_gpa (_frontend_io_ptw_req_bits_bits_need_gpa), // @[tile.scala:138:28]
.io_requestor_1_resp_valid (_ptw_io_requestor_1_resp_valid),
.io_requestor_1_resp_bits_ae_ptw (_ptw_io_requestor_1_resp_bits_ae_ptw),
.io_requestor_1_resp_bits_ae_final (_ptw_io_requestor_1_resp_bits_ae_final),
.io_requestor_1_resp_bits_pf (_ptw_io_requestor_1_resp_bits_pf),
.io_requestor_1_resp_bits_gf (_ptw_io_requestor_1_resp_bits_gf),
.io_requestor_1_resp_bits_hr (_ptw_io_requestor_1_resp_bits_hr),
.io_requestor_1_resp_bits_hw (_ptw_io_requestor_1_resp_bits_hw),
.io_requestor_1_resp_bits_hx (_ptw_io_requestor_1_resp_bits_hx),
.io_requestor_1_resp_bits_pte_reserved_for_future (_ptw_io_requestor_1_resp_bits_pte_reserved_for_future),
.io_requestor_1_resp_bits_pte_ppn (_ptw_io_requestor_1_resp_bits_pte_ppn),
.io_requestor_1_resp_bits_pte_reserved_for_software (_ptw_io_requestor_1_resp_bits_pte_reserved_for_software),
.io_requestor_1_resp_bits_pte_d (_ptw_io_requestor_1_resp_bits_pte_d),
.io_requestor_1_resp_bits_pte_a (_ptw_io_requestor_1_resp_bits_pte_a),
.io_requestor_1_resp_bits_pte_g (_ptw_io_requestor_1_resp_bits_pte_g),
.io_requestor_1_resp_bits_pte_u (_ptw_io_requestor_1_resp_bits_pte_u),
.io_requestor_1_resp_bits_pte_x (_ptw_io_requestor_1_resp_bits_pte_x),
.io_requestor_1_resp_bits_pte_w (_ptw_io_requestor_1_resp_bits_pte_w),
.io_requestor_1_resp_bits_pte_r (_ptw_io_requestor_1_resp_bits_pte_r),
.io_requestor_1_resp_bits_pte_v (_ptw_io_requestor_1_resp_bits_pte_v),
.io_requestor_1_resp_bits_level (_ptw_io_requestor_1_resp_bits_level),
.io_requestor_1_resp_bits_homogeneous (_ptw_io_requestor_1_resp_bits_homogeneous),
.io_requestor_1_resp_bits_gpa_valid (_ptw_io_requestor_1_resp_bits_gpa_valid),
.io_requestor_1_resp_bits_gpa_bits (_ptw_io_requestor_1_resp_bits_gpa_bits),
.io_requestor_1_resp_bits_gpa_is_pte (_ptw_io_requestor_1_resp_bits_gpa_is_pte),
.io_requestor_1_ptbr_mode (_ptw_io_requestor_1_ptbr_mode),
.io_requestor_1_ptbr_ppn (_ptw_io_requestor_1_ptbr_ppn),
.io_requestor_1_status_debug (_ptw_io_requestor_1_status_debug),
.io_requestor_1_status_cease (_ptw_io_requestor_1_status_cease),
.io_requestor_1_status_wfi (_ptw_io_requestor_1_status_wfi),
.io_requestor_1_status_dprv (_ptw_io_requestor_1_status_dprv),
.io_requestor_1_status_dv (_ptw_io_requestor_1_status_dv),
.io_requestor_1_status_prv (_ptw_io_requestor_1_status_prv),
.io_requestor_1_status_v (_ptw_io_requestor_1_status_v),
.io_requestor_1_status_sd (_ptw_io_requestor_1_status_sd),
.io_requestor_1_status_mpv (_ptw_io_requestor_1_status_mpv),
.io_requestor_1_status_gva (_ptw_io_requestor_1_status_gva),
.io_requestor_1_status_tsr (_ptw_io_requestor_1_status_tsr),
.io_requestor_1_status_tw (_ptw_io_requestor_1_status_tw),
.io_requestor_1_status_tvm (_ptw_io_requestor_1_status_tvm),
.io_requestor_1_status_mxr (_ptw_io_requestor_1_status_mxr),
.io_requestor_1_status_sum (_ptw_io_requestor_1_status_sum),
.io_requestor_1_status_mprv (_ptw_io_requestor_1_status_mprv),
.io_requestor_1_status_fs (_ptw_io_requestor_1_status_fs),
.io_requestor_1_status_mpp (_ptw_io_requestor_1_status_mpp),
.io_requestor_1_status_spp (_ptw_io_requestor_1_status_spp),
.io_requestor_1_status_mpie (_ptw_io_requestor_1_status_mpie),
.io_requestor_1_status_spie (_ptw_io_requestor_1_status_spie),
.io_requestor_1_status_mie (_ptw_io_requestor_1_status_mie),
.io_requestor_1_status_sie (_ptw_io_requestor_1_status_sie),
.io_requestor_1_pmp_0_cfg_l (_ptw_io_requestor_1_pmp_0_cfg_l),
.io_requestor_1_pmp_0_cfg_a (_ptw_io_requestor_1_pmp_0_cfg_a),
.io_requestor_1_pmp_0_cfg_x (_ptw_io_requestor_1_pmp_0_cfg_x),
.io_requestor_1_pmp_0_cfg_w (_ptw_io_requestor_1_pmp_0_cfg_w),
.io_requestor_1_pmp_0_cfg_r (_ptw_io_requestor_1_pmp_0_cfg_r),
.io_requestor_1_pmp_0_addr (_ptw_io_requestor_1_pmp_0_addr),
.io_requestor_1_pmp_0_mask (_ptw_io_requestor_1_pmp_0_mask),
.io_requestor_1_pmp_1_cfg_l (_ptw_io_requestor_1_pmp_1_cfg_l),
.io_requestor_1_pmp_1_cfg_a (_ptw_io_requestor_1_pmp_1_cfg_a),
.io_requestor_1_pmp_1_cfg_x (_ptw_io_requestor_1_pmp_1_cfg_x),
.io_requestor_1_pmp_1_cfg_w (_ptw_io_requestor_1_pmp_1_cfg_w),
.io_requestor_1_pmp_1_cfg_r (_ptw_io_requestor_1_pmp_1_cfg_r),
.io_requestor_1_pmp_1_addr (_ptw_io_requestor_1_pmp_1_addr),
.io_requestor_1_pmp_1_mask (_ptw_io_requestor_1_pmp_1_mask),
.io_requestor_1_pmp_2_cfg_l (_ptw_io_requestor_1_pmp_2_cfg_l),
.io_requestor_1_pmp_2_cfg_a (_ptw_io_requestor_1_pmp_2_cfg_a),
.io_requestor_1_pmp_2_cfg_x (_ptw_io_requestor_1_pmp_2_cfg_x),
.io_requestor_1_pmp_2_cfg_w (_ptw_io_requestor_1_pmp_2_cfg_w),
.io_requestor_1_pmp_2_cfg_r (_ptw_io_requestor_1_pmp_2_cfg_r),
.io_requestor_1_pmp_2_addr (_ptw_io_requestor_1_pmp_2_addr),
.io_requestor_1_pmp_2_mask (_ptw_io_requestor_1_pmp_2_mask),
.io_requestor_1_pmp_3_cfg_l (_ptw_io_requestor_1_pmp_3_cfg_l),
.io_requestor_1_pmp_3_cfg_a (_ptw_io_requestor_1_pmp_3_cfg_a),
.io_requestor_1_pmp_3_cfg_x (_ptw_io_requestor_1_pmp_3_cfg_x),
.io_requestor_1_pmp_3_cfg_w (_ptw_io_requestor_1_pmp_3_cfg_w),
.io_requestor_1_pmp_3_cfg_r (_ptw_io_requestor_1_pmp_3_cfg_r),
.io_requestor_1_pmp_3_addr (_ptw_io_requestor_1_pmp_3_addr),
.io_requestor_1_pmp_3_mask (_ptw_io_requestor_1_pmp_3_mask),
.io_requestor_1_pmp_4_cfg_l (_ptw_io_requestor_1_pmp_4_cfg_l),
.io_requestor_1_pmp_4_cfg_a (_ptw_io_requestor_1_pmp_4_cfg_a),
.io_requestor_1_pmp_4_cfg_x (_ptw_io_requestor_1_pmp_4_cfg_x),
.io_requestor_1_pmp_4_cfg_w (_ptw_io_requestor_1_pmp_4_cfg_w),
.io_requestor_1_pmp_4_cfg_r (_ptw_io_requestor_1_pmp_4_cfg_r),
.io_requestor_1_pmp_4_addr (_ptw_io_requestor_1_pmp_4_addr),
.io_requestor_1_pmp_4_mask (_ptw_io_requestor_1_pmp_4_mask),
.io_requestor_1_pmp_5_cfg_l (_ptw_io_requestor_1_pmp_5_cfg_l),
.io_requestor_1_pmp_5_cfg_a (_ptw_io_requestor_1_pmp_5_cfg_a),
.io_requestor_1_pmp_5_cfg_x (_ptw_io_requestor_1_pmp_5_cfg_x),
.io_requestor_1_pmp_5_cfg_w (_ptw_io_requestor_1_pmp_5_cfg_w),
.io_requestor_1_pmp_5_cfg_r (_ptw_io_requestor_1_pmp_5_cfg_r),
.io_requestor_1_pmp_5_addr (_ptw_io_requestor_1_pmp_5_addr),
.io_requestor_1_pmp_5_mask (_ptw_io_requestor_1_pmp_5_mask),
.io_requestor_1_pmp_6_cfg_l (_ptw_io_requestor_1_pmp_6_cfg_l),
.io_requestor_1_pmp_6_cfg_a (_ptw_io_requestor_1_pmp_6_cfg_a),
.io_requestor_1_pmp_6_cfg_x (_ptw_io_requestor_1_pmp_6_cfg_x),
.io_requestor_1_pmp_6_cfg_w (_ptw_io_requestor_1_pmp_6_cfg_w),
.io_requestor_1_pmp_6_cfg_r (_ptw_io_requestor_1_pmp_6_cfg_r),
.io_requestor_1_pmp_6_addr (_ptw_io_requestor_1_pmp_6_addr),
.io_requestor_1_pmp_6_mask (_ptw_io_requestor_1_pmp_6_mask),
.io_requestor_1_pmp_7_cfg_l (_ptw_io_requestor_1_pmp_7_cfg_l),
.io_requestor_1_pmp_7_cfg_a (_ptw_io_requestor_1_pmp_7_cfg_a),
.io_requestor_1_pmp_7_cfg_x (_ptw_io_requestor_1_pmp_7_cfg_x),
.io_requestor_1_pmp_7_cfg_w (_ptw_io_requestor_1_pmp_7_cfg_w),
.io_requestor_1_pmp_7_cfg_r (_ptw_io_requestor_1_pmp_7_cfg_r),
.io_requestor_1_pmp_7_addr (_ptw_io_requestor_1_pmp_7_addr),
.io_requestor_1_pmp_7_mask (_ptw_io_requestor_1_pmp_7_mask),
.io_requestor_2_req_ready (_ptw_io_requestor_2_req_ready),
.io_requestor_2_resp_valid (_ptw_io_requestor_2_resp_valid),
.io_requestor_2_resp_bits_ae_ptw (_ptw_io_requestor_2_resp_bits_ae_ptw),
.io_requestor_2_resp_bits_ae_final (_ptw_io_requestor_2_resp_bits_ae_final),
.io_requestor_2_resp_bits_pf (_ptw_io_requestor_2_resp_bits_pf),
.io_requestor_2_resp_bits_gf (_ptw_io_requestor_2_resp_bits_gf),
.io_requestor_2_resp_bits_hr (_ptw_io_requestor_2_resp_bits_hr),
.io_requestor_2_resp_bits_hw (_ptw_io_requestor_2_resp_bits_hw),
.io_requestor_2_resp_bits_hx (_ptw_io_requestor_2_resp_bits_hx),
.io_requestor_2_resp_bits_pte_reserved_for_future (_ptw_io_requestor_2_resp_bits_pte_reserved_for_future),
.io_requestor_2_resp_bits_pte_ppn (_ptw_io_requestor_2_resp_bits_pte_ppn),
.io_requestor_2_resp_bits_pte_reserved_for_software (_ptw_io_requestor_2_resp_bits_pte_reserved_for_software),
.io_requestor_2_resp_bits_pte_d (_ptw_io_requestor_2_resp_bits_pte_d),
.io_requestor_2_resp_bits_pte_a (_ptw_io_requestor_2_resp_bits_pte_a),
.io_requestor_2_resp_bits_pte_g (_ptw_io_requestor_2_resp_bits_pte_g),
.io_requestor_2_resp_bits_pte_u (_ptw_io_requestor_2_resp_bits_pte_u),
.io_requestor_2_resp_bits_pte_x (_ptw_io_requestor_2_resp_bits_pte_x),
.io_requestor_2_resp_bits_pte_w (_ptw_io_requestor_2_resp_bits_pte_w),
.io_requestor_2_resp_bits_pte_r (_ptw_io_requestor_2_resp_bits_pte_r),
.io_requestor_2_resp_bits_pte_v (_ptw_io_requestor_2_resp_bits_pte_v),
.io_requestor_2_resp_bits_level (_ptw_io_requestor_2_resp_bits_level),
.io_requestor_2_resp_bits_homogeneous (_ptw_io_requestor_2_resp_bits_homogeneous),
.io_requestor_2_resp_bits_gpa_valid (_ptw_io_requestor_2_resp_bits_gpa_valid),
.io_requestor_2_resp_bits_gpa_bits (_ptw_io_requestor_2_resp_bits_gpa_bits),
.io_requestor_2_resp_bits_gpa_is_pte (_ptw_io_requestor_2_resp_bits_gpa_is_pte),
.io_requestor_2_ptbr_mode (_ptw_io_requestor_2_ptbr_mode),
.io_requestor_2_ptbr_ppn (_ptw_io_requestor_2_ptbr_ppn),
.io_requestor_2_status_debug (_ptw_io_requestor_2_status_debug),
.io_requestor_2_status_cease (_ptw_io_requestor_2_status_cease),
.io_requestor_2_status_wfi (_ptw_io_requestor_2_status_wfi),
.io_requestor_2_status_dprv (_ptw_io_requestor_2_status_dprv),
.io_requestor_2_status_dv (_ptw_io_requestor_2_status_dv),
.io_requestor_2_status_prv (_ptw_io_requestor_2_status_prv),
.io_requestor_2_status_v (_ptw_io_requestor_2_status_v),
.io_requestor_2_status_sd (_ptw_io_requestor_2_status_sd),
.io_requestor_2_status_mpv (_ptw_io_requestor_2_status_mpv),
.io_requestor_2_status_gva (_ptw_io_requestor_2_status_gva),
.io_requestor_2_status_tsr (_ptw_io_requestor_2_status_tsr),
.io_requestor_2_status_tw (_ptw_io_requestor_2_status_tw),
.io_requestor_2_status_tvm (_ptw_io_requestor_2_status_tvm),
.io_requestor_2_status_mxr (_ptw_io_requestor_2_status_mxr),
.io_requestor_2_status_sum (_ptw_io_requestor_2_status_sum),
.io_requestor_2_status_mprv (_ptw_io_requestor_2_status_mprv),
.io_requestor_2_status_fs (_ptw_io_requestor_2_status_fs),
.io_requestor_2_status_mpp (_ptw_io_requestor_2_status_mpp),
.io_requestor_2_status_spp (_ptw_io_requestor_2_status_spp),
.io_requestor_2_status_mpie (_ptw_io_requestor_2_status_mpie),
.io_requestor_2_status_spie (_ptw_io_requestor_2_status_spie),
.io_requestor_2_status_mie (_ptw_io_requestor_2_status_mie),
.io_requestor_2_status_sie (_ptw_io_requestor_2_status_sie),
.io_requestor_2_pmp_0_cfg_l (_ptw_io_requestor_2_pmp_0_cfg_l),
.io_requestor_2_pmp_0_cfg_a (_ptw_io_requestor_2_pmp_0_cfg_a),
.io_requestor_2_pmp_0_cfg_x (_ptw_io_requestor_2_pmp_0_cfg_x),
.io_requestor_2_pmp_0_cfg_w (_ptw_io_requestor_2_pmp_0_cfg_w),
.io_requestor_2_pmp_0_cfg_r (_ptw_io_requestor_2_pmp_0_cfg_r),
.io_requestor_2_pmp_0_addr (_ptw_io_requestor_2_pmp_0_addr),
.io_requestor_2_pmp_0_mask (_ptw_io_requestor_2_pmp_0_mask),
.io_requestor_2_pmp_1_cfg_l (_ptw_io_requestor_2_pmp_1_cfg_l),
.io_requestor_2_pmp_1_cfg_a (_ptw_io_requestor_2_pmp_1_cfg_a),
.io_requestor_2_pmp_1_cfg_x (_ptw_io_requestor_2_pmp_1_cfg_x),
.io_requestor_2_pmp_1_cfg_w (_ptw_io_requestor_2_pmp_1_cfg_w),
.io_requestor_2_pmp_1_cfg_r (_ptw_io_requestor_2_pmp_1_cfg_r),
.io_requestor_2_pmp_1_addr (_ptw_io_requestor_2_pmp_1_addr),
.io_requestor_2_pmp_1_mask (_ptw_io_requestor_2_pmp_1_mask),
.io_requestor_2_pmp_2_cfg_l (_ptw_io_requestor_2_pmp_2_cfg_l),
.io_requestor_2_pmp_2_cfg_a (_ptw_io_requestor_2_pmp_2_cfg_a),
.io_requestor_2_pmp_2_cfg_x (_ptw_io_requestor_2_pmp_2_cfg_x),
.io_requestor_2_pmp_2_cfg_w (_ptw_io_requestor_2_pmp_2_cfg_w),
.io_requestor_2_pmp_2_cfg_r (_ptw_io_requestor_2_pmp_2_cfg_r),
.io_requestor_2_pmp_2_addr (_ptw_io_requestor_2_pmp_2_addr),
.io_requestor_2_pmp_2_mask (_ptw_io_requestor_2_pmp_2_mask),
.io_requestor_2_pmp_3_cfg_l (_ptw_io_requestor_2_pmp_3_cfg_l),
.io_requestor_2_pmp_3_cfg_a (_ptw_io_requestor_2_pmp_3_cfg_a),
.io_requestor_2_pmp_3_cfg_x (_ptw_io_requestor_2_pmp_3_cfg_x),
.io_requestor_2_pmp_3_cfg_w (_ptw_io_requestor_2_pmp_3_cfg_w),
.io_requestor_2_pmp_3_cfg_r (_ptw_io_requestor_2_pmp_3_cfg_r),
.io_requestor_2_pmp_3_addr (_ptw_io_requestor_2_pmp_3_addr),
.io_requestor_2_pmp_3_mask (_ptw_io_requestor_2_pmp_3_mask),
.io_requestor_2_pmp_4_cfg_l (_ptw_io_requestor_2_pmp_4_cfg_l),
.io_requestor_2_pmp_4_cfg_a (_ptw_io_requestor_2_pmp_4_cfg_a),
.io_requestor_2_pmp_4_cfg_x (_ptw_io_requestor_2_pmp_4_cfg_x),
.io_requestor_2_pmp_4_cfg_w (_ptw_io_requestor_2_pmp_4_cfg_w),
.io_requestor_2_pmp_4_cfg_r (_ptw_io_requestor_2_pmp_4_cfg_r),
.io_requestor_2_pmp_4_addr (_ptw_io_requestor_2_pmp_4_addr),
.io_requestor_2_pmp_4_mask (_ptw_io_requestor_2_pmp_4_mask),
.io_requestor_2_pmp_5_cfg_l (_ptw_io_requestor_2_pmp_5_cfg_l),
.io_requestor_2_pmp_5_cfg_a (_ptw_io_requestor_2_pmp_5_cfg_a),
.io_requestor_2_pmp_5_cfg_x (_ptw_io_requestor_2_pmp_5_cfg_x),
.io_requestor_2_pmp_5_cfg_w (_ptw_io_requestor_2_pmp_5_cfg_w),
.io_requestor_2_pmp_5_cfg_r (_ptw_io_requestor_2_pmp_5_cfg_r),
.io_requestor_2_pmp_5_addr (_ptw_io_requestor_2_pmp_5_addr),
.io_requestor_2_pmp_5_mask (_ptw_io_requestor_2_pmp_5_mask),
.io_requestor_2_pmp_6_cfg_l (_ptw_io_requestor_2_pmp_6_cfg_l),
.io_requestor_2_pmp_6_cfg_a (_ptw_io_requestor_2_pmp_6_cfg_a),
.io_requestor_2_pmp_6_cfg_x (_ptw_io_requestor_2_pmp_6_cfg_x),
.io_requestor_2_pmp_6_cfg_w (_ptw_io_requestor_2_pmp_6_cfg_w),
.io_requestor_2_pmp_6_cfg_r (_ptw_io_requestor_2_pmp_6_cfg_r),
.io_requestor_2_pmp_6_addr (_ptw_io_requestor_2_pmp_6_addr),
.io_requestor_2_pmp_6_mask (_ptw_io_requestor_2_pmp_6_mask),
.io_requestor_2_pmp_7_cfg_l (_ptw_io_requestor_2_pmp_7_cfg_l),
.io_requestor_2_pmp_7_cfg_a (_ptw_io_requestor_2_pmp_7_cfg_a),
.io_requestor_2_pmp_7_cfg_x (_ptw_io_requestor_2_pmp_7_cfg_x),
.io_requestor_2_pmp_7_cfg_w (_ptw_io_requestor_2_pmp_7_cfg_w),
.io_requestor_2_pmp_7_cfg_r (_ptw_io_requestor_2_pmp_7_cfg_r),
.io_requestor_2_pmp_7_addr (_ptw_io_requestor_2_pmp_7_addr),
.io_requestor_2_pmp_7_mask (_ptw_io_requestor_2_pmp_7_mask),
.io_mem_req_ready (_hellaCacheArb_io_requestor_0_req_ready), // @[tile.scala:243:29]
.io_mem_req_valid (_ptw_io_mem_req_valid),
.io_mem_req_bits_addr (_ptw_io_mem_req_bits_addr),
.io_mem_req_bits_dv (_ptw_io_mem_req_bits_dv),
.io_mem_s1_kill (_ptw_io_mem_s1_kill),
.io_mem_s2_nack (_hellaCacheArb_io_requestor_0_s2_nack), // @[tile.scala:243:29]
.io_mem_resp_valid (_hellaCacheArb_io_requestor_0_resp_valid), // @[tile.scala:243:29]
.io_mem_resp_bits_addr (_hellaCacheArb_io_requestor_0_resp_bits_addr), // @[tile.scala:243:29]
.io_mem_resp_bits_data (_hellaCacheArb_io_requestor_0_resp_bits_data), // @[tile.scala:243:29]
.io_mem_s2_xcpt_ma_ld (_hellaCacheArb_io_requestor_0_s2_xcpt_ma_ld), // @[tile.scala:243:29]
.io_mem_s2_xcpt_ma_st (_hellaCacheArb_io_requestor_0_s2_xcpt_ma_st), // @[tile.scala:243:29]
.io_mem_s2_xcpt_pf_ld (_hellaCacheArb_io_requestor_0_s2_xcpt_pf_ld), // @[tile.scala:243:29]
.io_mem_s2_xcpt_pf_st (_hellaCacheArb_io_requestor_0_s2_xcpt_pf_st), // @[tile.scala:243:29]
.io_mem_s2_xcpt_gf_ld (_hellaCacheArb_io_requestor_0_s2_xcpt_gf_ld), // @[tile.scala:243:29]
.io_mem_s2_xcpt_gf_st (_hellaCacheArb_io_requestor_0_s2_xcpt_gf_st), // @[tile.scala:243:29]
.io_mem_s2_xcpt_ae_ld (_hellaCacheArb_io_requestor_0_s2_xcpt_ae_ld), // @[tile.scala:243:29]
.io_mem_s2_xcpt_ae_st (_hellaCacheArb_io_requestor_0_s2_xcpt_ae_st), // @[tile.scala:243:29]
.io_mem_store_pending (_hellaCacheArb_io_requestor_0_store_pending), // @[tile.scala:243:29]
.io_dpath_ptbr_mode (_core_io_ptw_ptbr_mode), // @[tile.scala:159:20]
.io_dpath_ptbr_ppn (_core_io_ptw_ptbr_ppn), // @[tile.scala:159:20]
.io_dpath_sfence_valid (_core_io_ptw_sfence_valid), // @[tile.scala:159:20]
.io_dpath_sfence_bits_rs1 (_core_io_ptw_sfence_bits_rs1), // @[tile.scala:159:20]
.io_dpath_sfence_bits_rs2 (_core_io_ptw_sfence_bits_rs2), // @[tile.scala:159:20]
.io_dpath_sfence_bits_addr (_core_io_ptw_sfence_bits_addr), // @[tile.scala:159:20]
.io_dpath_sfence_bits_asid (_core_io_ptw_sfence_bits_asid), // @[tile.scala:159:20]
.io_dpath_status_debug (_core_io_ptw_status_debug), // @[tile.scala:159:20]
.io_dpath_status_cease (_core_io_ptw_status_cease), // @[tile.scala:159:20]
.io_dpath_status_wfi (_core_io_ptw_status_wfi), // @[tile.scala:159:20]
.io_dpath_status_dprv (_core_io_ptw_status_dprv), // @[tile.scala:159:20]
.io_dpath_status_dv (_core_io_ptw_status_dv), // @[tile.scala:159:20]
.io_dpath_status_prv (_core_io_ptw_status_prv), // @[tile.scala:159:20]
.io_dpath_status_v (_core_io_ptw_status_v), // @[tile.scala:159:20]
.io_dpath_status_sd (_core_io_ptw_status_sd), // @[tile.scala:159:20]
.io_dpath_status_mpv (_core_io_ptw_status_mpv), // @[tile.scala:159:20]
.io_dpath_status_gva (_core_io_ptw_status_gva), // @[tile.scala:159:20]
.io_dpath_status_tsr (_core_io_ptw_status_tsr), // @[tile.scala:159:20]
.io_dpath_status_tw (_core_io_ptw_status_tw), // @[tile.scala:159:20]
.io_dpath_status_tvm (_core_io_ptw_status_tvm), // @[tile.scala:159:20]
.io_dpath_status_mxr (_core_io_ptw_status_mxr), // @[tile.scala:159:20]
.io_dpath_status_sum (_core_io_ptw_status_sum), // @[tile.scala:159:20]
.io_dpath_status_mprv (_core_io_ptw_status_mprv), // @[tile.scala:159:20]
.io_dpath_status_fs (_core_io_ptw_status_fs), // @[tile.scala:159:20]
.io_dpath_status_mpp (_core_io_ptw_status_mpp), // @[tile.scala:159:20]
.io_dpath_status_spp (_core_io_ptw_status_spp), // @[tile.scala:159:20]
.io_dpath_status_mpie (_core_io_ptw_status_mpie), // @[tile.scala:159:20]
.io_dpath_status_spie (_core_io_ptw_status_spie), // @[tile.scala:159:20]
.io_dpath_status_mie (_core_io_ptw_status_mie), // @[tile.scala:159:20]
.io_dpath_status_sie (_core_io_ptw_status_sie), // @[tile.scala:159:20]
.io_dpath_pmp_0_cfg_l (_core_io_ptw_pmp_0_cfg_l), // @[tile.scala:159:20]
.io_dpath_pmp_0_cfg_a (_core_io_ptw_pmp_0_cfg_a), // @[tile.scala:159:20]
.io_dpath_pmp_0_cfg_x (_core_io_ptw_pmp_0_cfg_x), // @[tile.scala:159:20]
.io_dpath_pmp_0_cfg_w (_core_io_ptw_pmp_0_cfg_w), // @[tile.scala:159:20]
.io_dpath_pmp_0_cfg_r (_core_io_ptw_pmp_0_cfg_r), // @[tile.scala:159:20]
.io_dpath_pmp_0_addr (_core_io_ptw_pmp_0_addr), // @[tile.scala:159:20]
.io_dpath_pmp_0_mask (_core_io_ptw_pmp_0_mask), // @[tile.scala:159:20]
.io_dpath_pmp_1_cfg_l (_core_io_ptw_pmp_1_cfg_l), // @[tile.scala:159:20]
.io_dpath_pmp_1_cfg_a (_core_io_ptw_pmp_1_cfg_a), // @[tile.scala:159:20]
.io_dpath_pmp_1_cfg_x (_core_io_ptw_pmp_1_cfg_x), // @[tile.scala:159:20]
.io_dpath_pmp_1_cfg_w (_core_io_ptw_pmp_1_cfg_w), // @[tile.scala:159:20]
.io_dpath_pmp_1_cfg_r (_core_io_ptw_pmp_1_cfg_r), // @[tile.scala:159:20]
.io_dpath_pmp_1_addr (_core_io_ptw_pmp_1_addr), // @[tile.scala:159:20]
.io_dpath_pmp_1_mask (_core_io_ptw_pmp_1_mask), // @[tile.scala:159:20]
.io_dpath_pmp_2_cfg_l (_core_io_ptw_pmp_2_cfg_l), // @[tile.scala:159:20]
.io_dpath_pmp_2_cfg_a (_core_io_ptw_pmp_2_cfg_a), // @[tile.scala:159:20]
.io_dpath_pmp_2_cfg_x (_core_io_ptw_pmp_2_cfg_x), // @[tile.scala:159:20]
.io_dpath_pmp_2_cfg_w (_core_io_ptw_pmp_2_cfg_w), // @[tile.scala:159:20]
.io_dpath_pmp_2_cfg_r (_core_io_ptw_pmp_2_cfg_r), // @[tile.scala:159:20]
.io_dpath_pmp_2_addr (_core_io_ptw_pmp_2_addr), // @[tile.scala:159:20]
.io_dpath_pmp_2_mask (_core_io_ptw_pmp_2_mask), // @[tile.scala:159:20]
.io_dpath_pmp_3_cfg_l (_core_io_ptw_pmp_3_cfg_l), // @[tile.scala:159:20]
.io_dpath_pmp_3_cfg_a (_core_io_ptw_pmp_3_cfg_a), // @[tile.scala:159:20]
.io_dpath_pmp_3_cfg_x (_core_io_ptw_pmp_3_cfg_x), // @[tile.scala:159:20]
.io_dpath_pmp_3_cfg_w (_core_io_ptw_pmp_3_cfg_w), // @[tile.scala:159:20]
.io_dpath_pmp_3_cfg_r (_core_io_ptw_pmp_3_cfg_r), // @[tile.scala:159:20]
.io_dpath_pmp_3_addr (_core_io_ptw_pmp_3_addr), // @[tile.scala:159:20]
.io_dpath_pmp_3_mask (_core_io_ptw_pmp_3_mask), // @[tile.scala:159:20]
.io_dpath_pmp_4_cfg_l (_core_io_ptw_pmp_4_cfg_l), // @[tile.scala:159:20]
.io_dpath_pmp_4_cfg_a (_core_io_ptw_pmp_4_cfg_a), // @[tile.scala:159:20]
.io_dpath_pmp_4_cfg_x (_core_io_ptw_pmp_4_cfg_x), // @[tile.scala:159:20]
.io_dpath_pmp_4_cfg_w (_core_io_ptw_pmp_4_cfg_w), // @[tile.scala:159:20]
.io_dpath_pmp_4_cfg_r (_core_io_ptw_pmp_4_cfg_r), // @[tile.scala:159:20]
.io_dpath_pmp_4_addr (_core_io_ptw_pmp_4_addr), // @[tile.scala:159:20]
.io_dpath_pmp_4_mask (_core_io_ptw_pmp_4_mask), // @[tile.scala:159:20]
.io_dpath_pmp_5_cfg_l (_core_io_ptw_pmp_5_cfg_l), // @[tile.scala:159:20]
.io_dpath_pmp_5_cfg_a (_core_io_ptw_pmp_5_cfg_a), // @[tile.scala:159:20]
.io_dpath_pmp_5_cfg_x (_core_io_ptw_pmp_5_cfg_x), // @[tile.scala:159:20]
.io_dpath_pmp_5_cfg_w (_core_io_ptw_pmp_5_cfg_w), // @[tile.scala:159:20]
.io_dpath_pmp_5_cfg_r (_core_io_ptw_pmp_5_cfg_r), // @[tile.scala:159:20]
.io_dpath_pmp_5_addr (_core_io_ptw_pmp_5_addr), // @[tile.scala:159:20]
.io_dpath_pmp_5_mask (_core_io_ptw_pmp_5_mask), // @[tile.scala:159:20]
.io_dpath_pmp_6_cfg_l (_core_io_ptw_pmp_6_cfg_l), // @[tile.scala:159:20]
.io_dpath_pmp_6_cfg_a (_core_io_ptw_pmp_6_cfg_a), // @[tile.scala:159:20]
.io_dpath_pmp_6_cfg_x (_core_io_ptw_pmp_6_cfg_x), // @[tile.scala:159:20]
.io_dpath_pmp_6_cfg_w (_core_io_ptw_pmp_6_cfg_w), // @[tile.scala:159:20]
.io_dpath_pmp_6_cfg_r (_core_io_ptw_pmp_6_cfg_r), // @[tile.scala:159:20]
.io_dpath_pmp_6_addr (_core_io_ptw_pmp_6_addr), // @[tile.scala:159:20]
.io_dpath_pmp_6_mask (_core_io_ptw_pmp_6_mask), // @[tile.scala:159:20]
.io_dpath_pmp_7_cfg_l (_core_io_ptw_pmp_7_cfg_l), // @[tile.scala:159:20]
.io_dpath_pmp_7_cfg_a (_core_io_ptw_pmp_7_cfg_a), // @[tile.scala:159:20]
.io_dpath_pmp_7_cfg_x (_core_io_ptw_pmp_7_cfg_x), // @[tile.scala:159:20]
.io_dpath_pmp_7_cfg_w (_core_io_ptw_pmp_7_cfg_w), // @[tile.scala:159:20]
.io_dpath_pmp_7_cfg_r (_core_io_ptw_pmp_7_cfg_r), // @[tile.scala:159:20]
.io_dpath_pmp_7_addr (_core_io_ptw_pmp_7_addr), // @[tile.scala:159:20]
.io_dpath_pmp_7_mask (_core_io_ptw_pmp_7_mask), // @[tile.scala:159:20]
.io_dpath_perf_l2miss (_ptw_io_dpath_perf_l2miss),
.io_dpath_perf_l2hit (_ptw_io_dpath_perf_l2hit),
.io_dpath_perf_pte_miss (_ptw_io_dpath_perf_pte_miss),
.io_dpath_perf_pte_hit (_ptw_io_dpath_perf_pte_hit),
.io_dpath_clock_enabled (_ptw_io_dpath_clock_enabled)
); // @[tile.scala:237:20]
HellaCacheArbiter_3 hellaCacheArb ( // @[tile.scala:243:29]
.clock (clock),
.reset (reset),
.io_requestor_0_req_ready (_hellaCacheArb_io_requestor_0_req_ready),
.io_requestor_0_req_valid (_ptw_io_mem_req_valid), // @[tile.scala:237:20]
.io_requestor_0_req_bits_addr (_ptw_io_mem_req_bits_addr), // @[tile.scala:237:20]
.io_requestor_0_req_bits_dv (_ptw_io_mem_req_bits_dv), // @[tile.scala:237:20]
.io_requestor_0_s1_kill (_ptw_io_mem_s1_kill), // @[tile.scala:237:20]
.io_requestor_0_s2_nack (_hellaCacheArb_io_requestor_0_s2_nack),
.io_requestor_0_resp_valid (_hellaCacheArb_io_requestor_0_resp_valid),
.io_requestor_0_resp_bits_addr (_hellaCacheArb_io_requestor_0_resp_bits_addr),
.io_requestor_0_resp_bits_data (_hellaCacheArb_io_requestor_0_resp_bits_data),
.io_requestor_0_s2_xcpt_ma_ld (_hellaCacheArb_io_requestor_0_s2_xcpt_ma_ld),
.io_requestor_0_s2_xcpt_ma_st (_hellaCacheArb_io_requestor_0_s2_xcpt_ma_st),
.io_requestor_0_s2_xcpt_pf_ld (_hellaCacheArb_io_requestor_0_s2_xcpt_pf_ld),
.io_requestor_0_s2_xcpt_pf_st (_hellaCacheArb_io_requestor_0_s2_xcpt_pf_st),
.io_requestor_0_s2_xcpt_gf_ld (_hellaCacheArb_io_requestor_0_s2_xcpt_gf_ld),
.io_requestor_0_s2_xcpt_gf_st (_hellaCacheArb_io_requestor_0_s2_xcpt_gf_st),
.io_requestor_0_s2_xcpt_ae_ld (_hellaCacheArb_io_requestor_0_s2_xcpt_ae_ld),
.io_requestor_0_s2_xcpt_ae_st (_hellaCacheArb_io_requestor_0_s2_xcpt_ae_st),
.io_requestor_0_store_pending (_hellaCacheArb_io_requestor_0_store_pending),
.io_mem_req_ready (_lsu_io_hellacache_req_ready), // @[tile.scala:160:20]
.io_mem_req_valid (_hellaCacheArb_io_mem_req_valid),
.io_mem_req_bits_addr (_hellaCacheArb_io_mem_req_bits_addr),
.io_mem_req_bits_dv (_hellaCacheArb_io_mem_req_bits_dv),
.io_mem_s1_kill (_hellaCacheArb_io_mem_s1_kill),
.io_mem_s2_nack (_lsu_io_hellacache_s2_nack), // @[tile.scala:160:20]
.io_mem_resp_valid (_lsu_io_hellacache_resp_valid), // @[tile.scala:160:20]
.io_mem_resp_bits_addr (_lsu_io_hellacache_resp_bits_addr), // @[tile.scala:160:20]
.io_mem_resp_bits_data (_lsu_io_hellacache_resp_bits_data), // @[tile.scala:160:20]
.io_mem_s2_xcpt_ma_ld (_lsu_io_hellacache_s2_xcpt_ma_ld), // @[tile.scala:160:20]
.io_mem_s2_xcpt_ma_st (_lsu_io_hellacache_s2_xcpt_ma_st), // @[tile.scala:160:20]
.io_mem_s2_xcpt_pf_ld (_lsu_io_hellacache_s2_xcpt_pf_ld), // @[tile.scala:160:20]
.io_mem_s2_xcpt_pf_st (_lsu_io_hellacache_s2_xcpt_pf_st), // @[tile.scala:160:20]
.io_mem_s2_xcpt_gf_ld (_lsu_io_hellacache_s2_xcpt_gf_ld), // @[tile.scala:160:20]
.io_mem_s2_xcpt_gf_st (_lsu_io_hellacache_s2_xcpt_gf_st), // @[tile.scala:160:20]
.io_mem_s2_xcpt_ae_ld (_lsu_io_hellacache_s2_xcpt_ae_ld), // @[tile.scala:160:20]
.io_mem_s2_xcpt_ae_st (_lsu_io_hellacache_s2_xcpt_ae_st), // @[tile.scala:160:20]
.io_mem_store_pending (_lsu_io_hellacache_store_pending) // @[tile.scala:160:20]
); // @[tile.scala:243:29]
assign auto_buffer_out_a_valid = auto_buffer_out_a_valid_0; // @[tile.scala:155:7]
assign auto_buffer_out_a_bits_opcode = auto_buffer_out_a_bits_opcode_0; // @[tile.scala:155:7]
assign auto_buffer_out_a_bits_param = auto_buffer_out_a_bits_param_0; // @[tile.scala:155:7]
assign auto_buffer_out_a_bits_size = auto_buffer_out_a_bits_size_0; // @[tile.scala:155:7]
assign auto_buffer_out_a_bits_source = auto_buffer_out_a_bits_source_0; // @[tile.scala:155:7]
assign auto_buffer_out_a_bits_address = auto_buffer_out_a_bits_address_0; // @[tile.scala:155:7]
assign auto_buffer_out_a_bits_mask = auto_buffer_out_a_bits_mask_0; // @[tile.scala:155:7]
assign auto_buffer_out_a_bits_data = auto_buffer_out_a_bits_data_0; // @[tile.scala:155:7]
assign auto_buffer_out_b_ready = auto_buffer_out_b_ready_0; // @[tile.scala:155:7]
assign auto_buffer_out_c_valid = auto_buffer_out_c_valid_0; // @[tile.scala:155:7]
assign auto_buffer_out_c_bits_opcode = auto_buffer_out_c_bits_opcode_0; // @[tile.scala:155:7]
assign auto_buffer_out_c_bits_param = auto_buffer_out_c_bits_param_0; // @[tile.scala:155:7]
assign auto_buffer_out_c_bits_size = auto_buffer_out_c_bits_size_0; // @[tile.scala:155:7]
assign auto_buffer_out_c_bits_source = auto_buffer_out_c_bits_source_0; // @[tile.scala:155:7]
assign auto_buffer_out_c_bits_address = auto_buffer_out_c_bits_address_0; // @[tile.scala:155:7]
assign auto_buffer_out_c_bits_data = auto_buffer_out_c_bits_data_0; // @[tile.scala:155:7]
assign auto_buffer_out_d_ready = auto_buffer_out_d_ready_0; // @[tile.scala:155:7]
assign auto_buffer_out_e_valid = auto_buffer_out_e_valid_0; // @[tile.scala:155:7]
assign auto_buffer_out_e_bits_sink = auto_buffer_out_e_bits_sink_0; // @[tile.scala:155:7]
assign auto_trace_source_out_time = auto_trace_source_out_time_0; // @[tile.scala:155:7]
assign auto_trace_source_out_custom_rob_empty = auto_trace_source_out_custom_rob_empty_0; // @[tile.scala:155:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_15 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_15
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_15( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_15 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module ALUExeUnit_5 :
input clock : Clock
input reset : Reset
output io : { fu_types : UInt<10>, flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, rs1_data : UInt<65>, rs2_data : UInt<65>, rs3_data : UInt<65>, pred_data : UInt<1>, kill : UInt<1>}}, iresp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}, bypass : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}[1], flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, brinfo : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}, flip get_ftq_pc : { flip ftq_idx : UInt<5>, entry : { cfi_idx : { valid : UInt<1>, bits : UInt<3>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_type : UInt<3>, br_mask : UInt<8>, cfi_is_call : UInt<1>, cfi_is_ret : UInt<1>, cfi_npc_plus4 : UInt<1>, ras_top : UInt<40>, ras_idx : UInt<5>, start_bank : UInt<1>}, ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>}, pc : UInt<40>, com_pc : UInt<40>, next_val : UInt<1>, next_pc : UInt<40>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}
connect io.req.ready, UInt<1>(0h0)
connect io.iresp.valid, UInt<1>(0h0)
invalidate io.iresp.bits.fflags.bits.flags
invalidate io.iresp.bits.fflags.bits.uop.debug_tsrc
invalidate io.iresp.bits.fflags.bits.uop.debug_fsrc
invalidate io.iresp.bits.fflags.bits.uop.bp_xcpt_if
invalidate io.iresp.bits.fflags.bits.uop.bp_debug_if
invalidate io.iresp.bits.fflags.bits.uop.xcpt_ma_if
invalidate io.iresp.bits.fflags.bits.uop.xcpt_ae_if
invalidate io.iresp.bits.fflags.bits.uop.xcpt_pf_if
invalidate io.iresp.bits.fflags.bits.uop.fp_single
invalidate io.iresp.bits.fflags.bits.uop.fp_val
invalidate io.iresp.bits.fflags.bits.uop.frs3_en
invalidate io.iresp.bits.fflags.bits.uop.lrs2_rtype
invalidate io.iresp.bits.fflags.bits.uop.lrs1_rtype
invalidate io.iresp.bits.fflags.bits.uop.dst_rtype
invalidate io.iresp.bits.fflags.bits.uop.ldst_val
invalidate io.iresp.bits.fflags.bits.uop.lrs3
invalidate io.iresp.bits.fflags.bits.uop.lrs2
invalidate io.iresp.bits.fflags.bits.uop.lrs1
invalidate io.iresp.bits.fflags.bits.uop.ldst
invalidate io.iresp.bits.fflags.bits.uop.ldst_is_rs1
invalidate io.iresp.bits.fflags.bits.uop.flush_on_commit
invalidate io.iresp.bits.fflags.bits.uop.is_unique
invalidate io.iresp.bits.fflags.bits.uop.is_sys_pc2epc
invalidate io.iresp.bits.fflags.bits.uop.uses_stq
invalidate io.iresp.bits.fflags.bits.uop.uses_ldq
invalidate io.iresp.bits.fflags.bits.uop.is_amo
invalidate io.iresp.bits.fflags.bits.uop.is_fencei
invalidate io.iresp.bits.fflags.bits.uop.is_fence
invalidate io.iresp.bits.fflags.bits.uop.mem_signed
invalidate io.iresp.bits.fflags.bits.uop.mem_size
invalidate io.iresp.bits.fflags.bits.uop.mem_cmd
invalidate io.iresp.bits.fflags.bits.uop.bypassable
invalidate io.iresp.bits.fflags.bits.uop.exc_cause
invalidate io.iresp.bits.fflags.bits.uop.exception
invalidate io.iresp.bits.fflags.bits.uop.stale_pdst
invalidate io.iresp.bits.fflags.bits.uop.ppred_busy
invalidate io.iresp.bits.fflags.bits.uop.prs3_busy
invalidate io.iresp.bits.fflags.bits.uop.prs2_busy
invalidate io.iresp.bits.fflags.bits.uop.prs1_busy
invalidate io.iresp.bits.fflags.bits.uop.ppred
invalidate io.iresp.bits.fflags.bits.uop.prs3
invalidate io.iresp.bits.fflags.bits.uop.prs2
invalidate io.iresp.bits.fflags.bits.uop.prs1
invalidate io.iresp.bits.fflags.bits.uop.pdst
invalidate io.iresp.bits.fflags.bits.uop.rxq_idx
invalidate io.iresp.bits.fflags.bits.uop.stq_idx
invalidate io.iresp.bits.fflags.bits.uop.ldq_idx
invalidate io.iresp.bits.fflags.bits.uop.rob_idx
invalidate io.iresp.bits.fflags.bits.uop.csr_addr
invalidate io.iresp.bits.fflags.bits.uop.imm_packed
invalidate io.iresp.bits.fflags.bits.uop.taken
invalidate io.iresp.bits.fflags.bits.uop.pc_lob
invalidate io.iresp.bits.fflags.bits.uop.edge_inst
invalidate io.iresp.bits.fflags.bits.uop.ftq_idx
invalidate io.iresp.bits.fflags.bits.uop.br_tag
invalidate io.iresp.bits.fflags.bits.uop.br_mask
invalidate io.iresp.bits.fflags.bits.uop.is_sfb
invalidate io.iresp.bits.fflags.bits.uop.is_jal
invalidate io.iresp.bits.fflags.bits.uop.is_jalr
invalidate io.iresp.bits.fflags.bits.uop.is_br
invalidate io.iresp.bits.fflags.bits.uop.iw_p2_poisoned
invalidate io.iresp.bits.fflags.bits.uop.iw_p1_poisoned
invalidate io.iresp.bits.fflags.bits.uop.iw_state
invalidate io.iresp.bits.fflags.bits.uop.ctrl.is_std
invalidate io.iresp.bits.fflags.bits.uop.ctrl.is_sta
invalidate io.iresp.bits.fflags.bits.uop.ctrl.is_load
invalidate io.iresp.bits.fflags.bits.uop.ctrl.csr_cmd
invalidate io.iresp.bits.fflags.bits.uop.ctrl.fcn_dw
invalidate io.iresp.bits.fflags.bits.uop.ctrl.op_fcn
invalidate io.iresp.bits.fflags.bits.uop.ctrl.imm_sel
invalidate io.iresp.bits.fflags.bits.uop.ctrl.op2_sel
invalidate io.iresp.bits.fflags.bits.uop.ctrl.op1_sel
invalidate io.iresp.bits.fflags.bits.uop.ctrl.br_type
invalidate io.iresp.bits.fflags.bits.uop.fu_code
invalidate io.iresp.bits.fflags.bits.uop.iq_type
invalidate io.iresp.bits.fflags.bits.uop.debug_pc
invalidate io.iresp.bits.fflags.bits.uop.is_rvc
invalidate io.iresp.bits.fflags.bits.uop.debug_inst
invalidate io.iresp.bits.fflags.bits.uop.inst
invalidate io.iresp.bits.fflags.bits.uop.uopc
invalidate io.iresp.bits.fflags.valid
invalidate io.iresp.bits.predicated
invalidate io.iresp.bits.data
invalidate io.iresp.bits.uop.debug_tsrc
invalidate io.iresp.bits.uop.debug_fsrc
invalidate io.iresp.bits.uop.bp_xcpt_if
invalidate io.iresp.bits.uop.bp_debug_if
invalidate io.iresp.bits.uop.xcpt_ma_if
invalidate io.iresp.bits.uop.xcpt_ae_if
invalidate io.iresp.bits.uop.xcpt_pf_if
invalidate io.iresp.bits.uop.fp_single
invalidate io.iresp.bits.uop.fp_val
invalidate io.iresp.bits.uop.frs3_en
invalidate io.iresp.bits.uop.lrs2_rtype
invalidate io.iresp.bits.uop.lrs1_rtype
invalidate io.iresp.bits.uop.dst_rtype
invalidate io.iresp.bits.uop.ldst_val
invalidate io.iresp.bits.uop.lrs3
invalidate io.iresp.bits.uop.lrs2
invalidate io.iresp.bits.uop.lrs1
invalidate io.iresp.bits.uop.ldst
invalidate io.iresp.bits.uop.ldst_is_rs1
invalidate io.iresp.bits.uop.flush_on_commit
invalidate io.iresp.bits.uop.is_unique
invalidate io.iresp.bits.uop.is_sys_pc2epc
invalidate io.iresp.bits.uop.uses_stq
invalidate io.iresp.bits.uop.uses_ldq
invalidate io.iresp.bits.uop.is_amo
invalidate io.iresp.bits.uop.is_fencei
invalidate io.iresp.bits.uop.is_fence
invalidate io.iresp.bits.uop.mem_signed
invalidate io.iresp.bits.uop.mem_size
invalidate io.iresp.bits.uop.mem_cmd
invalidate io.iresp.bits.uop.bypassable
invalidate io.iresp.bits.uop.exc_cause
invalidate io.iresp.bits.uop.exception
invalidate io.iresp.bits.uop.stale_pdst
invalidate io.iresp.bits.uop.ppred_busy
invalidate io.iresp.bits.uop.prs3_busy
invalidate io.iresp.bits.uop.prs2_busy
invalidate io.iresp.bits.uop.prs1_busy
invalidate io.iresp.bits.uop.ppred
invalidate io.iresp.bits.uop.prs3
invalidate io.iresp.bits.uop.prs2
invalidate io.iresp.bits.uop.prs1
invalidate io.iresp.bits.uop.pdst
invalidate io.iresp.bits.uop.rxq_idx
invalidate io.iresp.bits.uop.stq_idx
invalidate io.iresp.bits.uop.ldq_idx
invalidate io.iresp.bits.uop.rob_idx
invalidate io.iresp.bits.uop.csr_addr
invalidate io.iresp.bits.uop.imm_packed
invalidate io.iresp.bits.uop.taken
invalidate io.iresp.bits.uop.pc_lob
invalidate io.iresp.bits.uop.edge_inst
invalidate io.iresp.bits.uop.ftq_idx
invalidate io.iresp.bits.uop.br_tag
invalidate io.iresp.bits.uop.br_mask
invalidate io.iresp.bits.uop.is_sfb
invalidate io.iresp.bits.uop.is_jal
invalidate io.iresp.bits.uop.is_jalr
invalidate io.iresp.bits.uop.is_br
invalidate io.iresp.bits.uop.iw_p2_poisoned
invalidate io.iresp.bits.uop.iw_p1_poisoned
invalidate io.iresp.bits.uop.iw_state
invalidate io.iresp.bits.uop.ctrl.is_std
invalidate io.iresp.bits.uop.ctrl.is_sta
invalidate io.iresp.bits.uop.ctrl.is_load
invalidate io.iresp.bits.uop.ctrl.csr_cmd
invalidate io.iresp.bits.uop.ctrl.fcn_dw
invalidate io.iresp.bits.uop.ctrl.op_fcn
invalidate io.iresp.bits.uop.ctrl.imm_sel
invalidate io.iresp.bits.uop.ctrl.op2_sel
invalidate io.iresp.bits.uop.ctrl.op1_sel
invalidate io.iresp.bits.uop.ctrl.br_type
invalidate io.iresp.bits.uop.fu_code
invalidate io.iresp.bits.uop.iq_type
invalidate io.iresp.bits.uop.debug_pc
invalidate io.iresp.bits.uop.is_rvc
invalidate io.iresp.bits.uop.debug_inst
invalidate io.iresp.bits.uop.inst
invalidate io.iresp.bits.uop.uopc
connect io.iresp.bits.fflags.valid, UInt<1>(0h0)
connect io.iresp.bits.predicated, UInt<1>(0h0)
node _T = asUInt(reset)
node _T_1 = eq(_T, UInt<1>(0h0))
when _T_1 :
node _T_2 = eq(io.iresp.ready, UInt<1>(0h0))
when _T_2 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at execution-unit.scala:147 assert(io.iresp.ready)\n") : printf
assert(clock, io.iresp.ready, UInt<1>(0h1), "") : assert
wire div_busy : UInt<1>
connect div_busy, UInt<1>(0h0)
wire ifpu_busy : UInt<1>
connect ifpu_busy, UInt<1>(0h0)
node _io_fu_types_T = mux(UInt<1>(0h1), UInt<10>(0h1), UInt<1>(0h0))
node _io_fu_types_T_1 = mux(UInt<1>(0h0), UInt<10>(0h8), UInt<1>(0h0))
node _io_fu_types_T_2 = or(_io_fu_types_T, _io_fu_types_T_1)
node _io_fu_types_T_3 = eq(div_busy, UInt<1>(0h0))
node _io_fu_types_T_4 = and(_io_fu_types_T_3, UInt<1>(0h1))
node _io_fu_types_T_5 = mux(_io_fu_types_T_4, UInt<10>(0h10), UInt<1>(0h0))
node _io_fu_types_T_6 = or(_io_fu_types_T_2, _io_fu_types_T_5)
node _io_fu_types_T_7 = mux(UInt<1>(0h0), UInt<10>(0h20), UInt<1>(0h0))
node _io_fu_types_T_8 = or(_io_fu_types_T_6, _io_fu_types_T_7)
node _io_fu_types_T_9 = mux(UInt<1>(0h1), UInt<10>(0h2), UInt<1>(0h0))
node _io_fu_types_T_10 = or(_io_fu_types_T_8, _io_fu_types_T_9)
node _io_fu_types_T_11 = eq(ifpu_busy, UInt<1>(0h0))
node _io_fu_types_T_12 = and(_io_fu_types_T_11, UInt<1>(0h0))
node _io_fu_types_T_13 = mux(_io_fu_types_T_12, UInt<10>(0h100), UInt<1>(0h0))
node _io_fu_types_T_14 = or(_io_fu_types_T_10, _io_fu_types_T_13)
node _io_fu_types_T_15 = mux(UInt<1>(0h0), UInt<10>(0h4), UInt<1>(0h0))
node _io_fu_types_T_16 = or(_io_fu_types_T_14, _io_fu_types_T_15)
connect io.fu_types, _io_fu_types_T_16
inst ALUUnit of ALUUnit_3
connect ALUUnit.clock, clock
connect ALUUnit.reset, reset
node _T_3 = eq(io.req.bits.uop.fu_code, UInt<10>(0h1))
node _T_4 = eq(io.req.bits.uop.fu_code, UInt<10>(0h2))
node _T_5 = or(_T_3, _T_4)
node _T_6 = eq(io.req.bits.uop.fu_code, UInt<10>(0h20))
node _T_7 = neq(io.req.bits.uop.uopc, UInt<7>(0h6c))
node _T_8 = and(_T_6, _T_7)
node _T_9 = or(_T_5, _T_8)
node _T_10 = and(io.req.valid, _T_9)
connect ALUUnit.io.req.valid, _T_10
connect ALUUnit.io.req.bits.uop.debug_tsrc, io.req.bits.uop.debug_tsrc
connect ALUUnit.io.req.bits.uop.debug_fsrc, io.req.bits.uop.debug_fsrc
connect ALUUnit.io.req.bits.uop.bp_xcpt_if, io.req.bits.uop.bp_xcpt_if
connect ALUUnit.io.req.bits.uop.bp_debug_if, io.req.bits.uop.bp_debug_if
connect ALUUnit.io.req.bits.uop.xcpt_ma_if, io.req.bits.uop.xcpt_ma_if
connect ALUUnit.io.req.bits.uop.xcpt_ae_if, io.req.bits.uop.xcpt_ae_if
connect ALUUnit.io.req.bits.uop.xcpt_pf_if, io.req.bits.uop.xcpt_pf_if
connect ALUUnit.io.req.bits.uop.fp_single, io.req.bits.uop.fp_single
connect ALUUnit.io.req.bits.uop.fp_val, io.req.bits.uop.fp_val
connect ALUUnit.io.req.bits.uop.frs3_en, io.req.bits.uop.frs3_en
connect ALUUnit.io.req.bits.uop.lrs2_rtype, io.req.bits.uop.lrs2_rtype
connect ALUUnit.io.req.bits.uop.lrs1_rtype, io.req.bits.uop.lrs1_rtype
connect ALUUnit.io.req.bits.uop.dst_rtype, io.req.bits.uop.dst_rtype
connect ALUUnit.io.req.bits.uop.ldst_val, io.req.bits.uop.ldst_val
connect ALUUnit.io.req.bits.uop.lrs3, io.req.bits.uop.lrs3
connect ALUUnit.io.req.bits.uop.lrs2, io.req.bits.uop.lrs2
connect ALUUnit.io.req.bits.uop.lrs1, io.req.bits.uop.lrs1
connect ALUUnit.io.req.bits.uop.ldst, io.req.bits.uop.ldst
connect ALUUnit.io.req.bits.uop.ldst_is_rs1, io.req.bits.uop.ldst_is_rs1
connect ALUUnit.io.req.bits.uop.flush_on_commit, io.req.bits.uop.flush_on_commit
connect ALUUnit.io.req.bits.uop.is_unique, io.req.bits.uop.is_unique
connect ALUUnit.io.req.bits.uop.is_sys_pc2epc, io.req.bits.uop.is_sys_pc2epc
connect ALUUnit.io.req.bits.uop.uses_stq, io.req.bits.uop.uses_stq
connect ALUUnit.io.req.bits.uop.uses_ldq, io.req.bits.uop.uses_ldq
connect ALUUnit.io.req.bits.uop.is_amo, io.req.bits.uop.is_amo
connect ALUUnit.io.req.bits.uop.is_fencei, io.req.bits.uop.is_fencei
connect ALUUnit.io.req.bits.uop.is_fence, io.req.bits.uop.is_fence
connect ALUUnit.io.req.bits.uop.mem_signed, io.req.bits.uop.mem_signed
connect ALUUnit.io.req.bits.uop.mem_size, io.req.bits.uop.mem_size
connect ALUUnit.io.req.bits.uop.mem_cmd, io.req.bits.uop.mem_cmd
connect ALUUnit.io.req.bits.uop.bypassable, io.req.bits.uop.bypassable
connect ALUUnit.io.req.bits.uop.exc_cause, io.req.bits.uop.exc_cause
connect ALUUnit.io.req.bits.uop.exception, io.req.bits.uop.exception
connect ALUUnit.io.req.bits.uop.stale_pdst, io.req.bits.uop.stale_pdst
connect ALUUnit.io.req.bits.uop.ppred_busy, io.req.bits.uop.ppred_busy
connect ALUUnit.io.req.bits.uop.prs3_busy, io.req.bits.uop.prs3_busy
connect ALUUnit.io.req.bits.uop.prs2_busy, io.req.bits.uop.prs2_busy
connect ALUUnit.io.req.bits.uop.prs1_busy, io.req.bits.uop.prs1_busy
connect ALUUnit.io.req.bits.uop.ppred, io.req.bits.uop.ppred
connect ALUUnit.io.req.bits.uop.prs3, io.req.bits.uop.prs3
connect ALUUnit.io.req.bits.uop.prs2, io.req.bits.uop.prs2
connect ALUUnit.io.req.bits.uop.prs1, io.req.bits.uop.prs1
connect ALUUnit.io.req.bits.uop.pdst, io.req.bits.uop.pdst
connect ALUUnit.io.req.bits.uop.rxq_idx, io.req.bits.uop.rxq_idx
connect ALUUnit.io.req.bits.uop.stq_idx, io.req.bits.uop.stq_idx
connect ALUUnit.io.req.bits.uop.ldq_idx, io.req.bits.uop.ldq_idx
connect ALUUnit.io.req.bits.uop.rob_idx, io.req.bits.uop.rob_idx
connect ALUUnit.io.req.bits.uop.csr_addr, io.req.bits.uop.csr_addr
connect ALUUnit.io.req.bits.uop.imm_packed, io.req.bits.uop.imm_packed
connect ALUUnit.io.req.bits.uop.taken, io.req.bits.uop.taken
connect ALUUnit.io.req.bits.uop.pc_lob, io.req.bits.uop.pc_lob
connect ALUUnit.io.req.bits.uop.edge_inst, io.req.bits.uop.edge_inst
connect ALUUnit.io.req.bits.uop.ftq_idx, io.req.bits.uop.ftq_idx
connect ALUUnit.io.req.bits.uop.br_tag, io.req.bits.uop.br_tag
connect ALUUnit.io.req.bits.uop.br_mask, io.req.bits.uop.br_mask
connect ALUUnit.io.req.bits.uop.is_sfb, io.req.bits.uop.is_sfb
connect ALUUnit.io.req.bits.uop.is_jal, io.req.bits.uop.is_jal
connect ALUUnit.io.req.bits.uop.is_jalr, io.req.bits.uop.is_jalr
connect ALUUnit.io.req.bits.uop.is_br, io.req.bits.uop.is_br
connect ALUUnit.io.req.bits.uop.iw_p2_poisoned, io.req.bits.uop.iw_p2_poisoned
connect ALUUnit.io.req.bits.uop.iw_p1_poisoned, io.req.bits.uop.iw_p1_poisoned
connect ALUUnit.io.req.bits.uop.iw_state, io.req.bits.uop.iw_state
connect ALUUnit.io.req.bits.uop.ctrl.is_std, io.req.bits.uop.ctrl.is_std
connect ALUUnit.io.req.bits.uop.ctrl.is_sta, io.req.bits.uop.ctrl.is_sta
connect ALUUnit.io.req.bits.uop.ctrl.is_load, io.req.bits.uop.ctrl.is_load
connect ALUUnit.io.req.bits.uop.ctrl.csr_cmd, io.req.bits.uop.ctrl.csr_cmd
connect ALUUnit.io.req.bits.uop.ctrl.fcn_dw, io.req.bits.uop.ctrl.fcn_dw
connect ALUUnit.io.req.bits.uop.ctrl.op_fcn, io.req.bits.uop.ctrl.op_fcn
connect ALUUnit.io.req.bits.uop.ctrl.imm_sel, io.req.bits.uop.ctrl.imm_sel
connect ALUUnit.io.req.bits.uop.ctrl.op2_sel, io.req.bits.uop.ctrl.op2_sel
connect ALUUnit.io.req.bits.uop.ctrl.op1_sel, io.req.bits.uop.ctrl.op1_sel
connect ALUUnit.io.req.bits.uop.ctrl.br_type, io.req.bits.uop.ctrl.br_type
connect ALUUnit.io.req.bits.uop.fu_code, io.req.bits.uop.fu_code
connect ALUUnit.io.req.bits.uop.iq_type, io.req.bits.uop.iq_type
connect ALUUnit.io.req.bits.uop.debug_pc, io.req.bits.uop.debug_pc
connect ALUUnit.io.req.bits.uop.is_rvc, io.req.bits.uop.is_rvc
connect ALUUnit.io.req.bits.uop.debug_inst, io.req.bits.uop.debug_inst
connect ALUUnit.io.req.bits.uop.inst, io.req.bits.uop.inst
connect ALUUnit.io.req.bits.uop.uopc, io.req.bits.uop.uopc
connect ALUUnit.io.req.bits.kill, io.req.bits.kill
connect ALUUnit.io.req.bits.rs1_data, io.req.bits.rs1_data
connect ALUUnit.io.req.bits.rs2_data, io.req.bits.rs2_data
invalidate ALUUnit.io.req.bits.rs3_data
connect ALUUnit.io.req.bits.pred_data, io.req.bits.pred_data
invalidate ALUUnit.io.resp.ready
connect ALUUnit.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect ALUUnit.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect ALUUnit.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect ALUUnit.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect ALUUnit.io.brupdate.b2.taken, io.brupdate.b2.taken
connect ALUUnit.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect ALUUnit.io.brupdate.b2.valid, io.brupdate.b2.valid
connect ALUUnit.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect ALUUnit.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect ALUUnit.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect ALUUnit.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect ALUUnit.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect ALUUnit.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect ALUUnit.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect ALUUnit.io.brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect ALUUnit.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect ALUUnit.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect ALUUnit.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect ALUUnit.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect ALUUnit.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect ALUUnit.io.brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect ALUUnit.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect ALUUnit.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect ALUUnit.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect ALUUnit.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect ALUUnit.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect ALUUnit.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect ALUUnit.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect ALUUnit.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect ALUUnit.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect ALUUnit.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect ALUUnit.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect ALUUnit.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect ALUUnit.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect ALUUnit.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect ALUUnit.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect ALUUnit.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect ALUUnit.io.brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect ALUUnit.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect ALUUnit.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect ALUUnit.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect ALUUnit.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect ALUUnit.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect ALUUnit.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect ALUUnit.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect ALUUnit.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect ALUUnit.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect ALUUnit.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect ALUUnit.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect ALUUnit.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect ALUUnit.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect ALUUnit.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect ALUUnit.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect ALUUnit.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect ALUUnit.io.brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect ALUUnit.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect ALUUnit.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect ALUUnit.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect ALUUnit.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect ALUUnit.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect ALUUnit.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect ALUUnit.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect ALUUnit.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect ALUUnit.io.brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect ALUUnit.io.brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect ALUUnit.io.brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect ALUUnit.io.brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect ALUUnit.io.brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect ALUUnit.io.brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect ALUUnit.io.brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect ALUUnit.io.brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect ALUUnit.io.brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect ALUUnit.io.brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect ALUUnit.io.brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect ALUUnit.io.brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect ALUUnit.io.brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect ALUUnit.io.brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect ALUUnit.io.brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect ALUUnit.io.brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect ALUUnit.io.brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect ALUUnit.io.brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect ALUUnit.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect ALUUnit.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect ALUUnit.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect ALUUnit.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect ALUUnit.io.brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect ALUUnit.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect ALUUnit.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect io.bypass, ALUUnit.io.bypass
connect io.brinfo, ALUUnit.io.brinfo
connect ALUUnit.io.get_ftq_pc, io.get_ftq_pc
wire div_resp_val : UInt<1>
connect div_resp_val, UInt<1>(0h0)
inst DivUnit of DivUnit_1
connect DivUnit.clock, clock
connect DivUnit.reset, reset
invalidate DivUnit.io.brupdate.b2.target_offset
invalidate DivUnit.io.brupdate.b2.jalr_target
invalidate DivUnit.io.brupdate.b2.pc_sel
invalidate DivUnit.io.brupdate.b2.cfi_type
invalidate DivUnit.io.brupdate.b2.taken
invalidate DivUnit.io.brupdate.b2.mispredict
invalidate DivUnit.io.brupdate.b2.valid
invalidate DivUnit.io.brupdate.b2.uop.debug_tsrc
invalidate DivUnit.io.brupdate.b2.uop.debug_fsrc
invalidate DivUnit.io.brupdate.b2.uop.bp_xcpt_if
invalidate DivUnit.io.brupdate.b2.uop.bp_debug_if
invalidate DivUnit.io.brupdate.b2.uop.xcpt_ma_if
invalidate DivUnit.io.brupdate.b2.uop.xcpt_ae_if
invalidate DivUnit.io.brupdate.b2.uop.xcpt_pf_if
invalidate DivUnit.io.brupdate.b2.uop.fp_single
invalidate DivUnit.io.brupdate.b2.uop.fp_val
invalidate DivUnit.io.brupdate.b2.uop.frs3_en
invalidate DivUnit.io.brupdate.b2.uop.lrs2_rtype
invalidate DivUnit.io.brupdate.b2.uop.lrs1_rtype
invalidate DivUnit.io.brupdate.b2.uop.dst_rtype
invalidate DivUnit.io.brupdate.b2.uop.ldst_val
invalidate DivUnit.io.brupdate.b2.uop.lrs3
invalidate DivUnit.io.brupdate.b2.uop.lrs2
invalidate DivUnit.io.brupdate.b2.uop.lrs1
invalidate DivUnit.io.brupdate.b2.uop.ldst
invalidate DivUnit.io.brupdate.b2.uop.ldst_is_rs1
invalidate DivUnit.io.brupdate.b2.uop.flush_on_commit
invalidate DivUnit.io.brupdate.b2.uop.is_unique
invalidate DivUnit.io.brupdate.b2.uop.is_sys_pc2epc
invalidate DivUnit.io.brupdate.b2.uop.uses_stq
invalidate DivUnit.io.brupdate.b2.uop.uses_ldq
invalidate DivUnit.io.brupdate.b2.uop.is_amo
invalidate DivUnit.io.brupdate.b2.uop.is_fencei
invalidate DivUnit.io.brupdate.b2.uop.is_fence
invalidate DivUnit.io.brupdate.b2.uop.mem_signed
invalidate DivUnit.io.brupdate.b2.uop.mem_size
invalidate DivUnit.io.brupdate.b2.uop.mem_cmd
invalidate DivUnit.io.brupdate.b2.uop.bypassable
invalidate DivUnit.io.brupdate.b2.uop.exc_cause
invalidate DivUnit.io.brupdate.b2.uop.exception
invalidate DivUnit.io.brupdate.b2.uop.stale_pdst
invalidate DivUnit.io.brupdate.b2.uop.ppred_busy
invalidate DivUnit.io.brupdate.b2.uop.prs3_busy
invalidate DivUnit.io.brupdate.b2.uop.prs2_busy
invalidate DivUnit.io.brupdate.b2.uop.prs1_busy
invalidate DivUnit.io.brupdate.b2.uop.ppred
invalidate DivUnit.io.brupdate.b2.uop.prs3
invalidate DivUnit.io.brupdate.b2.uop.prs2
invalidate DivUnit.io.brupdate.b2.uop.prs1
invalidate DivUnit.io.brupdate.b2.uop.pdst
invalidate DivUnit.io.brupdate.b2.uop.rxq_idx
invalidate DivUnit.io.brupdate.b2.uop.stq_idx
invalidate DivUnit.io.brupdate.b2.uop.ldq_idx
invalidate DivUnit.io.brupdate.b2.uop.rob_idx
invalidate DivUnit.io.brupdate.b2.uop.csr_addr
invalidate DivUnit.io.brupdate.b2.uop.imm_packed
invalidate DivUnit.io.brupdate.b2.uop.taken
invalidate DivUnit.io.brupdate.b2.uop.pc_lob
invalidate DivUnit.io.brupdate.b2.uop.edge_inst
invalidate DivUnit.io.brupdate.b2.uop.ftq_idx
invalidate DivUnit.io.brupdate.b2.uop.br_tag
invalidate DivUnit.io.brupdate.b2.uop.br_mask
invalidate DivUnit.io.brupdate.b2.uop.is_sfb
invalidate DivUnit.io.brupdate.b2.uop.is_jal
invalidate DivUnit.io.brupdate.b2.uop.is_jalr
invalidate DivUnit.io.brupdate.b2.uop.is_br
invalidate DivUnit.io.brupdate.b2.uop.iw_p2_poisoned
invalidate DivUnit.io.brupdate.b2.uop.iw_p1_poisoned
invalidate DivUnit.io.brupdate.b2.uop.iw_state
invalidate DivUnit.io.brupdate.b2.uop.ctrl.is_std
invalidate DivUnit.io.brupdate.b2.uop.ctrl.is_sta
invalidate DivUnit.io.brupdate.b2.uop.ctrl.is_load
invalidate DivUnit.io.brupdate.b2.uop.ctrl.csr_cmd
invalidate DivUnit.io.brupdate.b2.uop.ctrl.fcn_dw
invalidate DivUnit.io.brupdate.b2.uop.ctrl.op_fcn
invalidate DivUnit.io.brupdate.b2.uop.ctrl.imm_sel
invalidate DivUnit.io.brupdate.b2.uop.ctrl.op2_sel
invalidate DivUnit.io.brupdate.b2.uop.ctrl.op1_sel
invalidate DivUnit.io.brupdate.b2.uop.ctrl.br_type
invalidate DivUnit.io.brupdate.b2.uop.fu_code
invalidate DivUnit.io.brupdate.b2.uop.iq_type
invalidate DivUnit.io.brupdate.b2.uop.debug_pc
invalidate DivUnit.io.brupdate.b2.uop.is_rvc
invalidate DivUnit.io.brupdate.b2.uop.debug_inst
invalidate DivUnit.io.brupdate.b2.uop.inst
invalidate DivUnit.io.brupdate.b2.uop.uopc
invalidate DivUnit.io.brupdate.b1.mispredict_mask
invalidate DivUnit.io.brupdate.b1.resolve_mask
invalidate DivUnit.io.resp.bits.sfence.bits.hg
invalidate DivUnit.io.resp.bits.sfence.bits.hv
invalidate DivUnit.io.resp.bits.sfence.bits.asid
invalidate DivUnit.io.resp.bits.sfence.bits.addr
invalidate DivUnit.io.resp.bits.sfence.bits.rs2
invalidate DivUnit.io.resp.bits.sfence.bits.rs1
invalidate DivUnit.io.resp.bits.sfence.valid
invalidate DivUnit.io.resp.bits.mxcpt.bits
invalidate DivUnit.io.resp.bits.mxcpt.valid
invalidate DivUnit.io.resp.bits.addr
invalidate DivUnit.io.resp.bits.fflags.bits.flags
invalidate DivUnit.io.resp.bits.fflags.bits.uop.debug_tsrc
invalidate DivUnit.io.resp.bits.fflags.bits.uop.debug_fsrc
invalidate DivUnit.io.resp.bits.fflags.bits.uop.bp_xcpt_if
invalidate DivUnit.io.resp.bits.fflags.bits.uop.bp_debug_if
invalidate DivUnit.io.resp.bits.fflags.bits.uop.xcpt_ma_if
invalidate DivUnit.io.resp.bits.fflags.bits.uop.xcpt_ae_if
invalidate DivUnit.io.resp.bits.fflags.bits.uop.xcpt_pf_if
invalidate DivUnit.io.resp.bits.fflags.bits.uop.fp_single
invalidate DivUnit.io.resp.bits.fflags.bits.uop.fp_val
invalidate DivUnit.io.resp.bits.fflags.bits.uop.frs3_en
invalidate DivUnit.io.resp.bits.fflags.bits.uop.lrs2_rtype
invalidate DivUnit.io.resp.bits.fflags.bits.uop.lrs1_rtype
invalidate DivUnit.io.resp.bits.fflags.bits.uop.dst_rtype
invalidate DivUnit.io.resp.bits.fflags.bits.uop.ldst_val
invalidate DivUnit.io.resp.bits.fflags.bits.uop.lrs3
invalidate DivUnit.io.resp.bits.fflags.bits.uop.lrs2
invalidate DivUnit.io.resp.bits.fflags.bits.uop.lrs1
invalidate DivUnit.io.resp.bits.fflags.bits.uop.ldst
invalidate DivUnit.io.resp.bits.fflags.bits.uop.ldst_is_rs1
invalidate DivUnit.io.resp.bits.fflags.bits.uop.flush_on_commit
invalidate DivUnit.io.resp.bits.fflags.bits.uop.is_unique
invalidate DivUnit.io.resp.bits.fflags.bits.uop.is_sys_pc2epc
invalidate DivUnit.io.resp.bits.fflags.bits.uop.uses_stq
invalidate DivUnit.io.resp.bits.fflags.bits.uop.uses_ldq
invalidate DivUnit.io.resp.bits.fflags.bits.uop.is_amo
invalidate DivUnit.io.resp.bits.fflags.bits.uop.is_fencei
invalidate DivUnit.io.resp.bits.fflags.bits.uop.is_fence
invalidate DivUnit.io.resp.bits.fflags.bits.uop.mem_signed
invalidate DivUnit.io.resp.bits.fflags.bits.uop.mem_size
invalidate DivUnit.io.resp.bits.fflags.bits.uop.mem_cmd
invalidate DivUnit.io.resp.bits.fflags.bits.uop.bypassable
invalidate DivUnit.io.resp.bits.fflags.bits.uop.exc_cause
invalidate DivUnit.io.resp.bits.fflags.bits.uop.exception
invalidate DivUnit.io.resp.bits.fflags.bits.uop.stale_pdst
invalidate DivUnit.io.resp.bits.fflags.bits.uop.ppred_busy
invalidate DivUnit.io.resp.bits.fflags.bits.uop.prs3_busy
invalidate DivUnit.io.resp.bits.fflags.bits.uop.prs2_busy
invalidate DivUnit.io.resp.bits.fflags.bits.uop.prs1_busy
invalidate DivUnit.io.resp.bits.fflags.bits.uop.ppred
invalidate DivUnit.io.resp.bits.fflags.bits.uop.prs3
invalidate DivUnit.io.resp.bits.fflags.bits.uop.prs2
invalidate DivUnit.io.resp.bits.fflags.bits.uop.prs1
invalidate DivUnit.io.resp.bits.fflags.bits.uop.pdst
invalidate DivUnit.io.resp.bits.fflags.bits.uop.rxq_idx
invalidate DivUnit.io.resp.bits.fflags.bits.uop.stq_idx
invalidate DivUnit.io.resp.bits.fflags.bits.uop.ldq_idx
invalidate DivUnit.io.resp.bits.fflags.bits.uop.rob_idx
invalidate DivUnit.io.resp.bits.fflags.bits.uop.csr_addr
invalidate DivUnit.io.resp.bits.fflags.bits.uop.imm_packed
invalidate DivUnit.io.resp.bits.fflags.bits.uop.taken
invalidate DivUnit.io.resp.bits.fflags.bits.uop.pc_lob
invalidate DivUnit.io.resp.bits.fflags.bits.uop.edge_inst
invalidate DivUnit.io.resp.bits.fflags.bits.uop.ftq_idx
invalidate DivUnit.io.resp.bits.fflags.bits.uop.br_tag
invalidate DivUnit.io.resp.bits.fflags.bits.uop.br_mask
invalidate DivUnit.io.resp.bits.fflags.bits.uop.is_sfb
invalidate DivUnit.io.resp.bits.fflags.bits.uop.is_jal
invalidate DivUnit.io.resp.bits.fflags.bits.uop.is_jalr
invalidate DivUnit.io.resp.bits.fflags.bits.uop.is_br
invalidate DivUnit.io.resp.bits.fflags.bits.uop.iw_p2_poisoned
invalidate DivUnit.io.resp.bits.fflags.bits.uop.iw_p1_poisoned
invalidate DivUnit.io.resp.bits.fflags.bits.uop.iw_state
invalidate DivUnit.io.resp.bits.fflags.bits.uop.ctrl.is_std
invalidate DivUnit.io.resp.bits.fflags.bits.uop.ctrl.is_sta
invalidate DivUnit.io.resp.bits.fflags.bits.uop.ctrl.is_load
invalidate DivUnit.io.resp.bits.fflags.bits.uop.ctrl.csr_cmd
invalidate DivUnit.io.resp.bits.fflags.bits.uop.ctrl.fcn_dw
invalidate DivUnit.io.resp.bits.fflags.bits.uop.ctrl.op_fcn
invalidate DivUnit.io.resp.bits.fflags.bits.uop.ctrl.imm_sel
invalidate DivUnit.io.resp.bits.fflags.bits.uop.ctrl.op2_sel
invalidate DivUnit.io.resp.bits.fflags.bits.uop.ctrl.op1_sel
invalidate DivUnit.io.resp.bits.fflags.bits.uop.ctrl.br_type
invalidate DivUnit.io.resp.bits.fflags.bits.uop.fu_code
invalidate DivUnit.io.resp.bits.fflags.bits.uop.iq_type
invalidate DivUnit.io.resp.bits.fflags.bits.uop.debug_pc
invalidate DivUnit.io.resp.bits.fflags.bits.uop.is_rvc
invalidate DivUnit.io.resp.bits.fflags.bits.uop.debug_inst
invalidate DivUnit.io.resp.bits.fflags.bits.uop.inst
invalidate DivUnit.io.resp.bits.fflags.bits.uop.uopc
invalidate DivUnit.io.resp.bits.fflags.valid
invalidate DivUnit.io.resp.bits.data
invalidate DivUnit.io.resp.bits.predicated
invalidate DivUnit.io.resp.bits.uop.debug_tsrc
invalidate DivUnit.io.resp.bits.uop.debug_fsrc
invalidate DivUnit.io.resp.bits.uop.bp_xcpt_if
invalidate DivUnit.io.resp.bits.uop.bp_debug_if
invalidate DivUnit.io.resp.bits.uop.xcpt_ma_if
invalidate DivUnit.io.resp.bits.uop.xcpt_ae_if
invalidate DivUnit.io.resp.bits.uop.xcpt_pf_if
invalidate DivUnit.io.resp.bits.uop.fp_single
invalidate DivUnit.io.resp.bits.uop.fp_val
invalidate DivUnit.io.resp.bits.uop.frs3_en
invalidate DivUnit.io.resp.bits.uop.lrs2_rtype
invalidate DivUnit.io.resp.bits.uop.lrs1_rtype
invalidate DivUnit.io.resp.bits.uop.dst_rtype
invalidate DivUnit.io.resp.bits.uop.ldst_val
invalidate DivUnit.io.resp.bits.uop.lrs3
invalidate DivUnit.io.resp.bits.uop.lrs2
invalidate DivUnit.io.resp.bits.uop.lrs1
invalidate DivUnit.io.resp.bits.uop.ldst
invalidate DivUnit.io.resp.bits.uop.ldst_is_rs1
invalidate DivUnit.io.resp.bits.uop.flush_on_commit
invalidate DivUnit.io.resp.bits.uop.is_unique
invalidate DivUnit.io.resp.bits.uop.is_sys_pc2epc
invalidate DivUnit.io.resp.bits.uop.uses_stq
invalidate DivUnit.io.resp.bits.uop.uses_ldq
invalidate DivUnit.io.resp.bits.uop.is_amo
invalidate DivUnit.io.resp.bits.uop.is_fencei
invalidate DivUnit.io.resp.bits.uop.is_fence
invalidate DivUnit.io.resp.bits.uop.mem_signed
invalidate DivUnit.io.resp.bits.uop.mem_size
invalidate DivUnit.io.resp.bits.uop.mem_cmd
invalidate DivUnit.io.resp.bits.uop.bypassable
invalidate DivUnit.io.resp.bits.uop.exc_cause
invalidate DivUnit.io.resp.bits.uop.exception
invalidate DivUnit.io.resp.bits.uop.stale_pdst
invalidate DivUnit.io.resp.bits.uop.ppred_busy
invalidate DivUnit.io.resp.bits.uop.prs3_busy
invalidate DivUnit.io.resp.bits.uop.prs2_busy
invalidate DivUnit.io.resp.bits.uop.prs1_busy
invalidate DivUnit.io.resp.bits.uop.ppred
invalidate DivUnit.io.resp.bits.uop.prs3
invalidate DivUnit.io.resp.bits.uop.prs2
invalidate DivUnit.io.resp.bits.uop.prs1
invalidate DivUnit.io.resp.bits.uop.pdst
invalidate DivUnit.io.resp.bits.uop.rxq_idx
invalidate DivUnit.io.resp.bits.uop.stq_idx
invalidate DivUnit.io.resp.bits.uop.ldq_idx
invalidate DivUnit.io.resp.bits.uop.rob_idx
invalidate DivUnit.io.resp.bits.uop.csr_addr
invalidate DivUnit.io.resp.bits.uop.imm_packed
invalidate DivUnit.io.resp.bits.uop.taken
invalidate DivUnit.io.resp.bits.uop.pc_lob
invalidate DivUnit.io.resp.bits.uop.edge_inst
invalidate DivUnit.io.resp.bits.uop.ftq_idx
invalidate DivUnit.io.resp.bits.uop.br_tag
invalidate DivUnit.io.resp.bits.uop.br_mask
invalidate DivUnit.io.resp.bits.uop.is_sfb
invalidate DivUnit.io.resp.bits.uop.is_jal
invalidate DivUnit.io.resp.bits.uop.is_jalr
invalidate DivUnit.io.resp.bits.uop.is_br
invalidate DivUnit.io.resp.bits.uop.iw_p2_poisoned
invalidate DivUnit.io.resp.bits.uop.iw_p1_poisoned
invalidate DivUnit.io.resp.bits.uop.iw_state
invalidate DivUnit.io.resp.bits.uop.ctrl.is_std
invalidate DivUnit.io.resp.bits.uop.ctrl.is_sta
invalidate DivUnit.io.resp.bits.uop.ctrl.is_load
invalidate DivUnit.io.resp.bits.uop.ctrl.csr_cmd
invalidate DivUnit.io.resp.bits.uop.ctrl.fcn_dw
invalidate DivUnit.io.resp.bits.uop.ctrl.op_fcn
invalidate DivUnit.io.resp.bits.uop.ctrl.imm_sel
invalidate DivUnit.io.resp.bits.uop.ctrl.op2_sel
invalidate DivUnit.io.resp.bits.uop.ctrl.op1_sel
invalidate DivUnit.io.resp.bits.uop.ctrl.br_type
invalidate DivUnit.io.resp.bits.uop.fu_code
invalidate DivUnit.io.resp.bits.uop.iq_type
invalidate DivUnit.io.resp.bits.uop.debug_pc
invalidate DivUnit.io.resp.bits.uop.is_rvc
invalidate DivUnit.io.resp.bits.uop.debug_inst
invalidate DivUnit.io.resp.bits.uop.inst
invalidate DivUnit.io.resp.bits.uop.uopc
invalidate DivUnit.io.resp.valid
invalidate DivUnit.io.resp.ready
invalidate DivUnit.io.req.bits.kill
invalidate DivUnit.io.req.bits.pred_data
invalidate DivUnit.io.req.bits.rs3_data
invalidate DivUnit.io.req.bits.rs2_data
invalidate DivUnit.io.req.bits.rs1_data
invalidate DivUnit.io.req.bits.uop.debug_tsrc
invalidate DivUnit.io.req.bits.uop.debug_fsrc
invalidate DivUnit.io.req.bits.uop.bp_xcpt_if
invalidate DivUnit.io.req.bits.uop.bp_debug_if
invalidate DivUnit.io.req.bits.uop.xcpt_ma_if
invalidate DivUnit.io.req.bits.uop.xcpt_ae_if
invalidate DivUnit.io.req.bits.uop.xcpt_pf_if
invalidate DivUnit.io.req.bits.uop.fp_single
invalidate DivUnit.io.req.bits.uop.fp_val
invalidate DivUnit.io.req.bits.uop.frs3_en
invalidate DivUnit.io.req.bits.uop.lrs2_rtype
invalidate DivUnit.io.req.bits.uop.lrs1_rtype
invalidate DivUnit.io.req.bits.uop.dst_rtype
invalidate DivUnit.io.req.bits.uop.ldst_val
invalidate DivUnit.io.req.bits.uop.lrs3
invalidate DivUnit.io.req.bits.uop.lrs2
invalidate DivUnit.io.req.bits.uop.lrs1
invalidate DivUnit.io.req.bits.uop.ldst
invalidate DivUnit.io.req.bits.uop.ldst_is_rs1
invalidate DivUnit.io.req.bits.uop.flush_on_commit
invalidate DivUnit.io.req.bits.uop.is_unique
invalidate DivUnit.io.req.bits.uop.is_sys_pc2epc
invalidate DivUnit.io.req.bits.uop.uses_stq
invalidate DivUnit.io.req.bits.uop.uses_ldq
invalidate DivUnit.io.req.bits.uop.is_amo
invalidate DivUnit.io.req.bits.uop.is_fencei
invalidate DivUnit.io.req.bits.uop.is_fence
invalidate DivUnit.io.req.bits.uop.mem_signed
invalidate DivUnit.io.req.bits.uop.mem_size
invalidate DivUnit.io.req.bits.uop.mem_cmd
invalidate DivUnit.io.req.bits.uop.bypassable
invalidate DivUnit.io.req.bits.uop.exc_cause
invalidate DivUnit.io.req.bits.uop.exception
invalidate DivUnit.io.req.bits.uop.stale_pdst
invalidate DivUnit.io.req.bits.uop.ppred_busy
invalidate DivUnit.io.req.bits.uop.prs3_busy
invalidate DivUnit.io.req.bits.uop.prs2_busy
invalidate DivUnit.io.req.bits.uop.prs1_busy
invalidate DivUnit.io.req.bits.uop.ppred
invalidate DivUnit.io.req.bits.uop.prs3
invalidate DivUnit.io.req.bits.uop.prs2
invalidate DivUnit.io.req.bits.uop.prs1
invalidate DivUnit.io.req.bits.uop.pdst
invalidate DivUnit.io.req.bits.uop.rxq_idx
invalidate DivUnit.io.req.bits.uop.stq_idx
invalidate DivUnit.io.req.bits.uop.ldq_idx
invalidate DivUnit.io.req.bits.uop.rob_idx
invalidate DivUnit.io.req.bits.uop.csr_addr
invalidate DivUnit.io.req.bits.uop.imm_packed
invalidate DivUnit.io.req.bits.uop.taken
invalidate DivUnit.io.req.bits.uop.pc_lob
invalidate DivUnit.io.req.bits.uop.edge_inst
invalidate DivUnit.io.req.bits.uop.ftq_idx
invalidate DivUnit.io.req.bits.uop.br_tag
invalidate DivUnit.io.req.bits.uop.br_mask
invalidate DivUnit.io.req.bits.uop.is_sfb
invalidate DivUnit.io.req.bits.uop.is_jal
invalidate DivUnit.io.req.bits.uop.is_jalr
invalidate DivUnit.io.req.bits.uop.is_br
invalidate DivUnit.io.req.bits.uop.iw_p2_poisoned
invalidate DivUnit.io.req.bits.uop.iw_p1_poisoned
invalidate DivUnit.io.req.bits.uop.iw_state
invalidate DivUnit.io.req.bits.uop.ctrl.is_std
invalidate DivUnit.io.req.bits.uop.ctrl.is_sta
invalidate DivUnit.io.req.bits.uop.ctrl.is_load
invalidate DivUnit.io.req.bits.uop.ctrl.csr_cmd
invalidate DivUnit.io.req.bits.uop.ctrl.fcn_dw
invalidate DivUnit.io.req.bits.uop.ctrl.op_fcn
invalidate DivUnit.io.req.bits.uop.ctrl.imm_sel
invalidate DivUnit.io.req.bits.uop.ctrl.op2_sel
invalidate DivUnit.io.req.bits.uop.ctrl.op1_sel
invalidate DivUnit.io.req.bits.uop.ctrl.br_type
invalidate DivUnit.io.req.bits.uop.fu_code
invalidate DivUnit.io.req.bits.uop.iq_type
invalidate DivUnit.io.req.bits.uop.debug_pc
invalidate DivUnit.io.req.bits.uop.is_rvc
invalidate DivUnit.io.req.bits.uop.debug_inst
invalidate DivUnit.io.req.bits.uop.inst
invalidate DivUnit.io.req.bits.uop.uopc
invalidate DivUnit.io.req.valid
invalidate DivUnit.io.req.ready
node _T_11 = and(io.req.bits.uop.fu_code, UInt<10>(0h10))
node _T_12 = neq(_T_11, UInt<1>(0h0))
node _T_13 = and(io.req.valid, _T_12)
node _T_14 = and(_T_13, UInt<1>(0h1))
connect DivUnit.io.req.valid, _T_14
connect DivUnit.io.req.bits.uop.debug_tsrc, io.req.bits.uop.debug_tsrc
connect DivUnit.io.req.bits.uop.debug_fsrc, io.req.bits.uop.debug_fsrc
connect DivUnit.io.req.bits.uop.bp_xcpt_if, io.req.bits.uop.bp_xcpt_if
connect DivUnit.io.req.bits.uop.bp_debug_if, io.req.bits.uop.bp_debug_if
connect DivUnit.io.req.bits.uop.xcpt_ma_if, io.req.bits.uop.xcpt_ma_if
connect DivUnit.io.req.bits.uop.xcpt_ae_if, io.req.bits.uop.xcpt_ae_if
connect DivUnit.io.req.bits.uop.xcpt_pf_if, io.req.bits.uop.xcpt_pf_if
connect DivUnit.io.req.bits.uop.fp_single, io.req.bits.uop.fp_single
connect DivUnit.io.req.bits.uop.fp_val, io.req.bits.uop.fp_val
connect DivUnit.io.req.bits.uop.frs3_en, io.req.bits.uop.frs3_en
connect DivUnit.io.req.bits.uop.lrs2_rtype, io.req.bits.uop.lrs2_rtype
connect DivUnit.io.req.bits.uop.lrs1_rtype, io.req.bits.uop.lrs1_rtype
connect DivUnit.io.req.bits.uop.dst_rtype, io.req.bits.uop.dst_rtype
connect DivUnit.io.req.bits.uop.ldst_val, io.req.bits.uop.ldst_val
connect DivUnit.io.req.bits.uop.lrs3, io.req.bits.uop.lrs3
connect DivUnit.io.req.bits.uop.lrs2, io.req.bits.uop.lrs2
connect DivUnit.io.req.bits.uop.lrs1, io.req.bits.uop.lrs1
connect DivUnit.io.req.bits.uop.ldst, io.req.bits.uop.ldst
connect DivUnit.io.req.bits.uop.ldst_is_rs1, io.req.bits.uop.ldst_is_rs1
connect DivUnit.io.req.bits.uop.flush_on_commit, io.req.bits.uop.flush_on_commit
connect DivUnit.io.req.bits.uop.is_unique, io.req.bits.uop.is_unique
connect DivUnit.io.req.bits.uop.is_sys_pc2epc, io.req.bits.uop.is_sys_pc2epc
connect DivUnit.io.req.bits.uop.uses_stq, io.req.bits.uop.uses_stq
connect DivUnit.io.req.bits.uop.uses_ldq, io.req.bits.uop.uses_ldq
connect DivUnit.io.req.bits.uop.is_amo, io.req.bits.uop.is_amo
connect DivUnit.io.req.bits.uop.is_fencei, io.req.bits.uop.is_fencei
connect DivUnit.io.req.bits.uop.is_fence, io.req.bits.uop.is_fence
connect DivUnit.io.req.bits.uop.mem_signed, io.req.bits.uop.mem_signed
connect DivUnit.io.req.bits.uop.mem_size, io.req.bits.uop.mem_size
connect DivUnit.io.req.bits.uop.mem_cmd, io.req.bits.uop.mem_cmd
connect DivUnit.io.req.bits.uop.bypassable, io.req.bits.uop.bypassable
connect DivUnit.io.req.bits.uop.exc_cause, io.req.bits.uop.exc_cause
connect DivUnit.io.req.bits.uop.exception, io.req.bits.uop.exception
connect DivUnit.io.req.bits.uop.stale_pdst, io.req.bits.uop.stale_pdst
connect DivUnit.io.req.bits.uop.ppred_busy, io.req.bits.uop.ppred_busy
connect DivUnit.io.req.bits.uop.prs3_busy, io.req.bits.uop.prs3_busy
connect DivUnit.io.req.bits.uop.prs2_busy, io.req.bits.uop.prs2_busy
connect DivUnit.io.req.bits.uop.prs1_busy, io.req.bits.uop.prs1_busy
connect DivUnit.io.req.bits.uop.ppred, io.req.bits.uop.ppred
connect DivUnit.io.req.bits.uop.prs3, io.req.bits.uop.prs3
connect DivUnit.io.req.bits.uop.prs2, io.req.bits.uop.prs2
connect DivUnit.io.req.bits.uop.prs1, io.req.bits.uop.prs1
connect DivUnit.io.req.bits.uop.pdst, io.req.bits.uop.pdst
connect DivUnit.io.req.bits.uop.rxq_idx, io.req.bits.uop.rxq_idx
connect DivUnit.io.req.bits.uop.stq_idx, io.req.bits.uop.stq_idx
connect DivUnit.io.req.bits.uop.ldq_idx, io.req.bits.uop.ldq_idx
connect DivUnit.io.req.bits.uop.rob_idx, io.req.bits.uop.rob_idx
connect DivUnit.io.req.bits.uop.csr_addr, io.req.bits.uop.csr_addr
connect DivUnit.io.req.bits.uop.imm_packed, io.req.bits.uop.imm_packed
connect DivUnit.io.req.bits.uop.taken, io.req.bits.uop.taken
connect DivUnit.io.req.bits.uop.pc_lob, io.req.bits.uop.pc_lob
connect DivUnit.io.req.bits.uop.edge_inst, io.req.bits.uop.edge_inst
connect DivUnit.io.req.bits.uop.ftq_idx, io.req.bits.uop.ftq_idx
connect DivUnit.io.req.bits.uop.br_tag, io.req.bits.uop.br_tag
connect DivUnit.io.req.bits.uop.br_mask, io.req.bits.uop.br_mask
connect DivUnit.io.req.bits.uop.is_sfb, io.req.bits.uop.is_sfb
connect DivUnit.io.req.bits.uop.is_jal, io.req.bits.uop.is_jal
connect DivUnit.io.req.bits.uop.is_jalr, io.req.bits.uop.is_jalr
connect DivUnit.io.req.bits.uop.is_br, io.req.bits.uop.is_br
connect DivUnit.io.req.bits.uop.iw_p2_poisoned, io.req.bits.uop.iw_p2_poisoned
connect DivUnit.io.req.bits.uop.iw_p1_poisoned, io.req.bits.uop.iw_p1_poisoned
connect DivUnit.io.req.bits.uop.iw_state, io.req.bits.uop.iw_state
connect DivUnit.io.req.bits.uop.ctrl.is_std, io.req.bits.uop.ctrl.is_std
connect DivUnit.io.req.bits.uop.ctrl.is_sta, io.req.bits.uop.ctrl.is_sta
connect DivUnit.io.req.bits.uop.ctrl.is_load, io.req.bits.uop.ctrl.is_load
connect DivUnit.io.req.bits.uop.ctrl.csr_cmd, io.req.bits.uop.ctrl.csr_cmd
connect DivUnit.io.req.bits.uop.ctrl.fcn_dw, io.req.bits.uop.ctrl.fcn_dw
connect DivUnit.io.req.bits.uop.ctrl.op_fcn, io.req.bits.uop.ctrl.op_fcn
connect DivUnit.io.req.bits.uop.ctrl.imm_sel, io.req.bits.uop.ctrl.imm_sel
connect DivUnit.io.req.bits.uop.ctrl.op2_sel, io.req.bits.uop.ctrl.op2_sel
connect DivUnit.io.req.bits.uop.ctrl.op1_sel, io.req.bits.uop.ctrl.op1_sel
connect DivUnit.io.req.bits.uop.ctrl.br_type, io.req.bits.uop.ctrl.br_type
connect DivUnit.io.req.bits.uop.fu_code, io.req.bits.uop.fu_code
connect DivUnit.io.req.bits.uop.iq_type, io.req.bits.uop.iq_type
connect DivUnit.io.req.bits.uop.debug_pc, io.req.bits.uop.debug_pc
connect DivUnit.io.req.bits.uop.is_rvc, io.req.bits.uop.is_rvc
connect DivUnit.io.req.bits.uop.debug_inst, io.req.bits.uop.debug_inst
connect DivUnit.io.req.bits.uop.inst, io.req.bits.uop.inst
connect DivUnit.io.req.bits.uop.uopc, io.req.bits.uop.uopc
connect DivUnit.io.req.bits.rs1_data, io.req.bits.rs1_data
connect DivUnit.io.req.bits.rs2_data, io.req.bits.rs2_data
connect DivUnit.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect DivUnit.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect DivUnit.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect DivUnit.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect DivUnit.io.brupdate.b2.taken, io.brupdate.b2.taken
connect DivUnit.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect DivUnit.io.brupdate.b2.valid, io.brupdate.b2.valid
connect DivUnit.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect DivUnit.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect DivUnit.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect DivUnit.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect DivUnit.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect DivUnit.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect DivUnit.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect DivUnit.io.brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect DivUnit.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect DivUnit.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect DivUnit.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect DivUnit.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect DivUnit.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect DivUnit.io.brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect DivUnit.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect DivUnit.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect DivUnit.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect DivUnit.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect DivUnit.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect DivUnit.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect DivUnit.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect DivUnit.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect DivUnit.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect DivUnit.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect DivUnit.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect DivUnit.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect DivUnit.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect DivUnit.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect DivUnit.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect DivUnit.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect DivUnit.io.brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect DivUnit.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect DivUnit.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect DivUnit.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect DivUnit.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect DivUnit.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect DivUnit.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect DivUnit.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect DivUnit.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect DivUnit.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect DivUnit.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect DivUnit.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect DivUnit.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect DivUnit.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect DivUnit.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect DivUnit.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect DivUnit.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect DivUnit.io.brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect DivUnit.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect DivUnit.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect DivUnit.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect DivUnit.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect DivUnit.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect DivUnit.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect DivUnit.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect DivUnit.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect DivUnit.io.brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect DivUnit.io.brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect DivUnit.io.brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect DivUnit.io.brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect DivUnit.io.brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect DivUnit.io.brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect DivUnit.io.brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect DivUnit.io.brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect DivUnit.io.brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect DivUnit.io.brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect DivUnit.io.brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect DivUnit.io.brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect DivUnit.io.brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect DivUnit.io.brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect DivUnit.io.brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect DivUnit.io.brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect DivUnit.io.brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect DivUnit.io.brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect DivUnit.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect DivUnit.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect DivUnit.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect DivUnit.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect DivUnit.io.brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect DivUnit.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect DivUnit.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect DivUnit.io.req.bits.kill, io.req.bits.kill
node _T_15 = eq(ALUUnit.io.resp.valid, UInt<1>(0h0))
connect DivUnit.io.resp.ready, _T_15
connect div_resp_val, DivUnit.io.resp.valid
node _div_busy_T = eq(DivUnit.io.req.ready, UInt<1>(0h0))
node _div_busy_T_1 = and(io.req.bits.uop.fu_code, UInt<10>(0h10))
node _div_busy_T_2 = neq(_div_busy_T_1, UInt<1>(0h0))
node _div_busy_T_3 = and(io.req.valid, _div_busy_T_2)
node _div_busy_T_4 = or(_div_busy_T, _div_busy_T_3)
connect div_busy, _div_busy_T_4
node _io_iresp_valid_T = or(ALUUnit.io.resp.valid, DivUnit.io.resp.valid)
connect io.iresp.valid, _io_iresp_valid_T
node _io_iresp_bits_uop_T = mux(ALUUnit.io.resp.valid, ALUUnit.io.resp.bits.uop, DivUnit.io.resp.bits.uop)
connect io.iresp.bits.uop, _io_iresp_bits_uop_T
node _io_iresp_bits_data_T = mux(ALUUnit.io.resp.valid, ALUUnit.io.resp.bits.data, DivUnit.io.resp.bits.data)
connect io.iresp.bits.data, _io_iresp_bits_data_T
node _io_iresp_bits_predicated_T = mux(ALUUnit.io.resp.valid, ALUUnit.io.resp.bits.predicated, DivUnit.io.resp.bits.predicated)
connect io.iresp.bits.predicated, _io_iresp_bits_predicated_T
node _io_iresp_bits_uop_csr_addr_sign_T = bits(ALUUnit.io.resp.bits.uop.imm_packed, 19, 19)
node io_iresp_bits_uop_csr_addr_sign = asSInt(_io_iresp_bits_uop_csr_addr_sign_T)
node _io_iresp_bits_uop_csr_addr_i30_20_T = eq(UInt<3>(0h0), UInt<3>(0h3))
node _io_iresp_bits_uop_csr_addr_i30_20_T_1 = bits(ALUUnit.io.resp.bits.uop.imm_packed, 18, 8)
node _io_iresp_bits_uop_csr_addr_i30_20_T_2 = asSInt(_io_iresp_bits_uop_csr_addr_i30_20_T_1)
node io_iresp_bits_uop_csr_addr_i30_20 = mux(_io_iresp_bits_uop_csr_addr_i30_20_T, _io_iresp_bits_uop_csr_addr_i30_20_T_2, io_iresp_bits_uop_csr_addr_sign)
node _io_iresp_bits_uop_csr_addr_i19_12_T = eq(UInt<3>(0h0), UInt<3>(0h3))
node _io_iresp_bits_uop_csr_addr_i19_12_T_1 = eq(UInt<3>(0h0), UInt<3>(0h4))
node _io_iresp_bits_uop_csr_addr_i19_12_T_2 = or(_io_iresp_bits_uop_csr_addr_i19_12_T, _io_iresp_bits_uop_csr_addr_i19_12_T_1)
node _io_iresp_bits_uop_csr_addr_i19_12_T_3 = bits(ALUUnit.io.resp.bits.uop.imm_packed, 7, 0)
node _io_iresp_bits_uop_csr_addr_i19_12_T_4 = asSInt(_io_iresp_bits_uop_csr_addr_i19_12_T_3)
node io_iresp_bits_uop_csr_addr_i19_12 = mux(_io_iresp_bits_uop_csr_addr_i19_12_T_2, _io_iresp_bits_uop_csr_addr_i19_12_T_4, io_iresp_bits_uop_csr_addr_sign)
node _io_iresp_bits_uop_csr_addr_i11_T = eq(UInt<3>(0h0), UInt<3>(0h3))
node _io_iresp_bits_uop_csr_addr_i11_T_1 = eq(UInt<3>(0h0), UInt<3>(0h4))
node _io_iresp_bits_uop_csr_addr_i11_T_2 = eq(UInt<3>(0h0), UInt<3>(0h2))
node _io_iresp_bits_uop_csr_addr_i11_T_3 = or(_io_iresp_bits_uop_csr_addr_i11_T_1, _io_iresp_bits_uop_csr_addr_i11_T_2)
node _io_iresp_bits_uop_csr_addr_i11_T_4 = bits(ALUUnit.io.resp.bits.uop.imm_packed, 8, 8)
node _io_iresp_bits_uop_csr_addr_i11_T_5 = asSInt(_io_iresp_bits_uop_csr_addr_i11_T_4)
node _io_iresp_bits_uop_csr_addr_i11_T_6 = mux(_io_iresp_bits_uop_csr_addr_i11_T_3, _io_iresp_bits_uop_csr_addr_i11_T_5, io_iresp_bits_uop_csr_addr_sign)
node io_iresp_bits_uop_csr_addr_i11 = mux(_io_iresp_bits_uop_csr_addr_i11_T, asSInt(UInt<1>(0h0)), _io_iresp_bits_uop_csr_addr_i11_T_6)
node _io_iresp_bits_uop_csr_addr_i10_5_T = eq(UInt<3>(0h0), UInt<3>(0h3))
node _io_iresp_bits_uop_csr_addr_i10_5_T_1 = bits(ALUUnit.io.resp.bits.uop.imm_packed, 18, 14)
node _io_iresp_bits_uop_csr_addr_i10_5_T_2 = asSInt(_io_iresp_bits_uop_csr_addr_i10_5_T_1)
node io_iresp_bits_uop_csr_addr_i10_5 = mux(_io_iresp_bits_uop_csr_addr_i10_5_T, asSInt(UInt<1>(0h0)), _io_iresp_bits_uop_csr_addr_i10_5_T_2)
node _io_iresp_bits_uop_csr_addr_i4_1_T = eq(UInt<3>(0h0), UInt<3>(0h3))
node _io_iresp_bits_uop_csr_addr_i4_1_T_1 = bits(ALUUnit.io.resp.bits.uop.imm_packed, 13, 9)
node _io_iresp_bits_uop_csr_addr_i4_1_T_2 = asSInt(_io_iresp_bits_uop_csr_addr_i4_1_T_1)
node io_iresp_bits_uop_csr_addr_i4_1 = mux(_io_iresp_bits_uop_csr_addr_i4_1_T, asSInt(UInt<1>(0h0)), _io_iresp_bits_uop_csr_addr_i4_1_T_2)
node _io_iresp_bits_uop_csr_addr_i0_T = eq(UInt<3>(0h0), UInt<3>(0h1))
node _io_iresp_bits_uop_csr_addr_i0_T_1 = eq(UInt<3>(0h0), UInt<3>(0h0))
node _io_iresp_bits_uop_csr_addr_i0_T_2 = or(_io_iresp_bits_uop_csr_addr_i0_T, _io_iresp_bits_uop_csr_addr_i0_T_1)
node _io_iresp_bits_uop_csr_addr_i0_T_3 = bits(ALUUnit.io.resp.bits.uop.imm_packed, 8, 8)
node _io_iresp_bits_uop_csr_addr_i0_T_4 = asSInt(_io_iresp_bits_uop_csr_addr_i0_T_3)
node io_iresp_bits_uop_csr_addr_i0 = mux(_io_iresp_bits_uop_csr_addr_i0_T_2, _io_iresp_bits_uop_csr_addr_i0_T_4, asSInt(UInt<1>(0h0)))
node io_iresp_bits_uop_csr_addr_lo_lo = asUInt(io_iresp_bits_uop_csr_addr_i0)
node io_iresp_bits_uop_csr_addr_lo_hi_lo = asUInt(io_iresp_bits_uop_csr_addr_i4_1)
node io_iresp_bits_uop_csr_addr_lo_hi_hi = asUInt(io_iresp_bits_uop_csr_addr_i10_5)
node io_iresp_bits_uop_csr_addr_lo_hi = cat(io_iresp_bits_uop_csr_addr_lo_hi_hi, io_iresp_bits_uop_csr_addr_lo_hi_lo)
node io_iresp_bits_uop_csr_addr_lo = cat(io_iresp_bits_uop_csr_addr_lo_hi, io_iresp_bits_uop_csr_addr_lo_lo)
node io_iresp_bits_uop_csr_addr_hi_lo_lo = asUInt(io_iresp_bits_uop_csr_addr_i11)
node io_iresp_bits_uop_csr_addr_hi_lo_hi = asUInt(io_iresp_bits_uop_csr_addr_i19_12)
node io_iresp_bits_uop_csr_addr_hi_lo = cat(io_iresp_bits_uop_csr_addr_hi_lo_hi, io_iresp_bits_uop_csr_addr_hi_lo_lo)
node io_iresp_bits_uop_csr_addr_hi_hi_lo = asUInt(io_iresp_bits_uop_csr_addr_i30_20)
node io_iresp_bits_uop_csr_addr_hi_hi_hi = asUInt(io_iresp_bits_uop_csr_addr_sign)
node io_iresp_bits_uop_csr_addr_hi_hi = cat(io_iresp_bits_uop_csr_addr_hi_hi_hi, io_iresp_bits_uop_csr_addr_hi_hi_lo)
node io_iresp_bits_uop_csr_addr_hi = cat(io_iresp_bits_uop_csr_addr_hi_hi, io_iresp_bits_uop_csr_addr_hi_lo)
node _io_iresp_bits_uop_csr_addr_T = cat(io_iresp_bits_uop_csr_addr_hi, io_iresp_bits_uop_csr_addr_lo)
node _io_iresp_bits_uop_csr_addr_T_1 = asSInt(_io_iresp_bits_uop_csr_addr_T)
node _io_iresp_bits_uop_csr_addr_T_2 = asUInt(_io_iresp_bits_uop_csr_addr_T_1)
connect io.iresp.bits.uop.csr_addr, _io_iresp_bits_uop_csr_addr_T_2
connect io.iresp.bits.uop.ctrl.csr_cmd, ALUUnit.io.resp.bits.uop.ctrl.csr_cmd
node _T_16 = add(ALUUnit.io.resp.valid, DivUnit.io.resp.valid)
node _T_17 = bits(_T_16, 1, 0)
node _T_18 = leq(_T_17, UInt<1>(0h1))
node _T_19 = eq(div_resp_val, UInt<1>(0h0))
node _T_20 = and(_T_18, _T_19)
node _T_21 = add(ALUUnit.io.resp.valid, DivUnit.io.resp.valid)
node _T_22 = bits(_T_21, 1, 0)
node _T_23 = leq(_T_22, UInt<2>(0h2))
node _T_24 = and(_T_23, div_resp_val)
node _T_25 = or(_T_20, _T_24)
node _T_26 = asUInt(reset)
node _T_27 = eq(_T_26, UInt<1>(0h0))
when _T_27 :
node _T_28 = eq(_T_25, UInt<1>(0h0))
when _T_28 :
printf(clock, UInt<1>(0h1), "Assertion failed: Multiple functional units are fighting over the write port.\n at execution-unit.scala:425 assert ((PopCount(iresp_fu_units.map(_.io.resp.valid)) <= 1.U && !div_resp_val) ||\n") : printf_1
assert(clock, _T_25, UInt<1>(0h1), "") : assert_1 | module ALUExeUnit_5( // @[execution-unit.scala:204:7]
input clock, // @[execution-unit.scala:204:7]
input reset, // @[execution-unit.scala:204:7]
output [9:0] io_fu_types, // @[execution-unit.scala:104:14]
input io_req_valid, // @[execution-unit.scala:104:14]
input [6:0] io_req_bits_uop_uopc, // @[execution-unit.scala:104:14]
input [31:0] io_req_bits_uop_inst, // @[execution-unit.scala:104:14]
input [31:0] io_req_bits_uop_debug_inst, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_rvc, // @[execution-unit.scala:104:14]
input [39:0] io_req_bits_uop_debug_pc, // @[execution-unit.scala:104:14]
input [2:0] io_req_bits_uop_iq_type, // @[execution-unit.scala:104:14]
input [9:0] io_req_bits_uop_fu_code, // @[execution-unit.scala:104:14]
input [3:0] io_req_bits_uop_ctrl_br_type, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14]
input [2:0] io_req_bits_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14]
input [2:0] io_req_bits_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14]
input [4:0] io_req_bits_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14]
input io_req_bits_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14]
input [2:0] io_req_bits_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14]
input io_req_bits_uop_ctrl_is_load, // @[execution-unit.scala:104:14]
input io_req_bits_uop_ctrl_is_sta, // @[execution-unit.scala:104:14]
input io_req_bits_uop_ctrl_is_std, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_iw_state, // @[execution-unit.scala:104:14]
input io_req_bits_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14]
input io_req_bits_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_br, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_jalr, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_jal, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_sfb, // @[execution-unit.scala:104:14]
input [15:0] io_req_bits_uop_br_mask, // @[execution-unit.scala:104:14]
input [3:0] io_req_bits_uop_br_tag, // @[execution-unit.scala:104:14]
input [4:0] io_req_bits_uop_ftq_idx, // @[execution-unit.scala:104:14]
input io_req_bits_uop_edge_inst, // @[execution-unit.scala:104:14]
input [5:0] io_req_bits_uop_pc_lob, // @[execution-unit.scala:104:14]
input io_req_bits_uop_taken, // @[execution-unit.scala:104:14]
input [19:0] io_req_bits_uop_imm_packed, // @[execution-unit.scala:104:14]
input [11:0] io_req_bits_uop_csr_addr, // @[execution-unit.scala:104:14]
input [6:0] io_req_bits_uop_rob_idx, // @[execution-unit.scala:104:14]
input [4:0] io_req_bits_uop_ldq_idx, // @[execution-unit.scala:104:14]
input [4:0] io_req_bits_uop_stq_idx, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_rxq_idx, // @[execution-unit.scala:104:14]
input [6:0] io_req_bits_uop_pdst, // @[execution-unit.scala:104:14]
input [6:0] io_req_bits_uop_prs1, // @[execution-unit.scala:104:14]
input [6:0] io_req_bits_uop_prs2, // @[execution-unit.scala:104:14]
input [6:0] io_req_bits_uop_prs3, // @[execution-unit.scala:104:14]
input [4:0] io_req_bits_uop_ppred, // @[execution-unit.scala:104:14]
input io_req_bits_uop_prs1_busy, // @[execution-unit.scala:104:14]
input io_req_bits_uop_prs2_busy, // @[execution-unit.scala:104:14]
input io_req_bits_uop_prs3_busy, // @[execution-unit.scala:104:14]
input io_req_bits_uop_ppred_busy, // @[execution-unit.scala:104:14]
input [6:0] io_req_bits_uop_stale_pdst, // @[execution-unit.scala:104:14]
input io_req_bits_uop_exception, // @[execution-unit.scala:104:14]
input [63:0] io_req_bits_uop_exc_cause, // @[execution-unit.scala:104:14]
input io_req_bits_uop_bypassable, // @[execution-unit.scala:104:14]
input [4:0] io_req_bits_uop_mem_cmd, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_mem_size, // @[execution-unit.scala:104:14]
input io_req_bits_uop_mem_signed, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_fence, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_fencei, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_amo, // @[execution-unit.scala:104:14]
input io_req_bits_uop_uses_ldq, // @[execution-unit.scala:104:14]
input io_req_bits_uop_uses_stq, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_unique, // @[execution-unit.scala:104:14]
input io_req_bits_uop_flush_on_commit, // @[execution-unit.scala:104:14]
input io_req_bits_uop_ldst_is_rs1, // @[execution-unit.scala:104:14]
input [5:0] io_req_bits_uop_ldst, // @[execution-unit.scala:104:14]
input [5:0] io_req_bits_uop_lrs1, // @[execution-unit.scala:104:14]
input [5:0] io_req_bits_uop_lrs2, // @[execution-unit.scala:104:14]
input [5:0] io_req_bits_uop_lrs3, // @[execution-unit.scala:104:14]
input io_req_bits_uop_ldst_val, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_dst_rtype, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_lrs1_rtype, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_lrs2_rtype, // @[execution-unit.scala:104:14]
input io_req_bits_uop_frs3_en, // @[execution-unit.scala:104:14]
input io_req_bits_uop_fp_val, // @[execution-unit.scala:104:14]
input io_req_bits_uop_fp_single, // @[execution-unit.scala:104:14]
input io_req_bits_uop_xcpt_pf_if, // @[execution-unit.scala:104:14]
input io_req_bits_uop_xcpt_ae_if, // @[execution-unit.scala:104:14]
input io_req_bits_uop_xcpt_ma_if, // @[execution-unit.scala:104:14]
input io_req_bits_uop_bp_debug_if, // @[execution-unit.scala:104:14]
input io_req_bits_uop_bp_xcpt_if, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_debug_fsrc, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_debug_tsrc, // @[execution-unit.scala:104:14]
input [64:0] io_req_bits_rs1_data, // @[execution-unit.scala:104:14]
input [64:0] io_req_bits_rs2_data, // @[execution-unit.scala:104:14]
input io_req_bits_kill, // @[execution-unit.scala:104:14]
output io_iresp_valid, // @[execution-unit.scala:104:14]
output [6:0] io_iresp_bits_uop_uopc, // @[execution-unit.scala:104:14]
output [31:0] io_iresp_bits_uop_inst, // @[execution-unit.scala:104:14]
output [31:0] io_iresp_bits_uop_debug_inst, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_is_rvc, // @[execution-unit.scala:104:14]
output [39:0] io_iresp_bits_uop_debug_pc, // @[execution-unit.scala:104:14]
output [2:0] io_iresp_bits_uop_iq_type, // @[execution-unit.scala:104:14]
output [9:0] io_iresp_bits_uop_fu_code, // @[execution-unit.scala:104:14]
output [3:0] io_iresp_bits_uop_ctrl_br_type, // @[execution-unit.scala:104:14]
output [1:0] io_iresp_bits_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14]
output [2:0] io_iresp_bits_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14]
output [2:0] io_iresp_bits_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14]
output [4:0] io_iresp_bits_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14]
output [2:0] io_iresp_bits_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_ctrl_is_load, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_ctrl_is_sta, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_ctrl_is_std, // @[execution-unit.scala:104:14]
output [1:0] io_iresp_bits_uop_iw_state, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_is_br, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_is_jalr, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_is_jal, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_is_sfb, // @[execution-unit.scala:104:14]
output [15:0] io_iresp_bits_uop_br_mask, // @[execution-unit.scala:104:14]
output [3:0] io_iresp_bits_uop_br_tag, // @[execution-unit.scala:104:14]
output [4:0] io_iresp_bits_uop_ftq_idx, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_edge_inst, // @[execution-unit.scala:104:14]
output [5:0] io_iresp_bits_uop_pc_lob, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_taken, // @[execution-unit.scala:104:14]
output [19:0] io_iresp_bits_uop_imm_packed, // @[execution-unit.scala:104:14]
output [11:0] io_iresp_bits_uop_csr_addr, // @[execution-unit.scala:104:14]
output [6:0] io_iresp_bits_uop_rob_idx, // @[execution-unit.scala:104:14]
output [4:0] io_iresp_bits_uop_ldq_idx, // @[execution-unit.scala:104:14]
output [4:0] io_iresp_bits_uop_stq_idx, // @[execution-unit.scala:104:14]
output [1:0] io_iresp_bits_uop_rxq_idx, // @[execution-unit.scala:104:14]
output [6:0] io_iresp_bits_uop_pdst, // @[execution-unit.scala:104:14]
output [6:0] io_iresp_bits_uop_prs1, // @[execution-unit.scala:104:14]
output [6:0] io_iresp_bits_uop_prs2, // @[execution-unit.scala:104:14]
output [6:0] io_iresp_bits_uop_prs3, // @[execution-unit.scala:104:14]
output [4:0] io_iresp_bits_uop_ppred, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_prs1_busy, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_prs2_busy, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_prs3_busy, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_ppred_busy, // @[execution-unit.scala:104:14]
output [6:0] io_iresp_bits_uop_stale_pdst, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_exception, // @[execution-unit.scala:104:14]
output [63:0] io_iresp_bits_uop_exc_cause, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_bypassable, // @[execution-unit.scala:104:14]
output [4:0] io_iresp_bits_uop_mem_cmd, // @[execution-unit.scala:104:14]
output [1:0] io_iresp_bits_uop_mem_size, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_mem_signed, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_is_fence, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_is_fencei, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_is_amo, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_uses_ldq, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_uses_stq, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_is_unique, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_flush_on_commit, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_ldst_is_rs1, // @[execution-unit.scala:104:14]
output [5:0] io_iresp_bits_uop_ldst, // @[execution-unit.scala:104:14]
output [5:0] io_iresp_bits_uop_lrs1, // @[execution-unit.scala:104:14]
output [5:0] io_iresp_bits_uop_lrs2, // @[execution-unit.scala:104:14]
output [5:0] io_iresp_bits_uop_lrs3, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_ldst_val, // @[execution-unit.scala:104:14]
output [1:0] io_iresp_bits_uop_dst_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_iresp_bits_uop_lrs1_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_iresp_bits_uop_lrs2_rtype, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_frs3_en, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_fp_val, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_fp_single, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_xcpt_pf_if, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_xcpt_ae_if, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_xcpt_ma_if, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_bp_debug_if, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_bp_xcpt_if, // @[execution-unit.scala:104:14]
output [1:0] io_iresp_bits_uop_debug_fsrc, // @[execution-unit.scala:104:14]
output [1:0] io_iresp_bits_uop_debug_tsrc, // @[execution-unit.scala:104:14]
output [64:0] io_iresp_bits_data, // @[execution-unit.scala:104:14]
output io_bypass_0_valid, // @[execution-unit.scala:104:14]
output [6:0] io_bypass_0_bits_uop_uopc, // @[execution-unit.scala:104:14]
output [31:0] io_bypass_0_bits_uop_inst, // @[execution-unit.scala:104:14]
output [31:0] io_bypass_0_bits_uop_debug_inst, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_is_rvc, // @[execution-unit.scala:104:14]
output [39:0] io_bypass_0_bits_uop_debug_pc, // @[execution-unit.scala:104:14]
output [2:0] io_bypass_0_bits_uop_iq_type, // @[execution-unit.scala:104:14]
output [9:0] io_bypass_0_bits_uop_fu_code, // @[execution-unit.scala:104:14]
output [3:0] io_bypass_0_bits_uop_ctrl_br_type, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_0_bits_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14]
output [2:0] io_bypass_0_bits_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14]
output [2:0] io_bypass_0_bits_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14]
output [4:0] io_bypass_0_bits_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14]
output [2:0] io_bypass_0_bits_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_ctrl_is_load, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_ctrl_is_sta, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_ctrl_is_std, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_0_bits_uop_iw_state, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_is_br, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_is_jalr, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_is_jal, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_is_sfb, // @[execution-unit.scala:104:14]
output [15:0] io_bypass_0_bits_uop_br_mask, // @[execution-unit.scala:104:14]
output [3:0] io_bypass_0_bits_uop_br_tag, // @[execution-unit.scala:104:14]
output [4:0] io_bypass_0_bits_uop_ftq_idx, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_edge_inst, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_0_bits_uop_pc_lob, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_taken, // @[execution-unit.scala:104:14]
output [19:0] io_bypass_0_bits_uop_imm_packed, // @[execution-unit.scala:104:14]
output [11:0] io_bypass_0_bits_uop_csr_addr, // @[execution-unit.scala:104:14]
output [6:0] io_bypass_0_bits_uop_rob_idx, // @[execution-unit.scala:104:14]
output [4:0] io_bypass_0_bits_uop_ldq_idx, // @[execution-unit.scala:104:14]
output [4:0] io_bypass_0_bits_uop_stq_idx, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_0_bits_uop_rxq_idx, // @[execution-unit.scala:104:14]
output [6:0] io_bypass_0_bits_uop_pdst, // @[execution-unit.scala:104:14]
output [6:0] io_bypass_0_bits_uop_prs1, // @[execution-unit.scala:104:14]
output [6:0] io_bypass_0_bits_uop_prs2, // @[execution-unit.scala:104:14]
output [6:0] io_bypass_0_bits_uop_prs3, // @[execution-unit.scala:104:14]
output [4:0] io_bypass_0_bits_uop_ppred, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_prs1_busy, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_prs2_busy, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_prs3_busy, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_ppred_busy, // @[execution-unit.scala:104:14]
output [6:0] io_bypass_0_bits_uop_stale_pdst, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_exception, // @[execution-unit.scala:104:14]
output [63:0] io_bypass_0_bits_uop_exc_cause, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_bypassable, // @[execution-unit.scala:104:14]
output [4:0] io_bypass_0_bits_uop_mem_cmd, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_0_bits_uop_mem_size, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_mem_signed, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_is_fence, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_is_fencei, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_is_amo, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_uses_ldq, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_uses_stq, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_is_unique, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_flush_on_commit, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_ldst_is_rs1, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_0_bits_uop_ldst, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_0_bits_uop_lrs1, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_0_bits_uop_lrs2, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_0_bits_uop_lrs3, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_ldst_val, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_0_bits_uop_dst_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_0_bits_uop_lrs1_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_0_bits_uop_lrs2_rtype, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_frs3_en, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_fp_val, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_fp_single, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_xcpt_pf_if, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_xcpt_ae_if, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_xcpt_ma_if, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_bp_debug_if, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_bp_xcpt_if, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_0_bits_uop_debug_fsrc, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_0_bits_uop_debug_tsrc, // @[execution-unit.scala:104:14]
output [64:0] io_bypass_0_bits_data, // @[execution-unit.scala:104:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[execution-unit.scala:104:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[execution-unit.scala:104:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[execution-unit.scala:104:14]
input [31:0] io_brupdate_b2_uop_inst, // @[execution-unit.scala:104:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_rvc, // @[execution-unit.scala:104:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[execution-unit.scala:104:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[execution-unit.scala:104:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[execution-unit.scala:104:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_br, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_jalr, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_jal, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_sfb, // @[execution-unit.scala:104:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[execution-unit.scala:104:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[execution-unit.scala:104:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_edge_inst, // @[execution-unit.scala:104:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_taken, // @[execution-unit.scala:104:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[execution-unit.scala:104:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[execution-unit.scala:104:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[execution-unit.scala:104:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[execution-unit.scala:104:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[execution-unit.scala:104:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[execution-unit.scala:104:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[execution-unit.scala:104:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[execution-unit.scala:104:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[execution-unit.scala:104:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_prs1_busy, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_prs2_busy, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_prs3_busy, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_ppred_busy, // @[execution-unit.scala:104:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_exception, // @[execution-unit.scala:104:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_bypassable, // @[execution-unit.scala:104:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_mem_signed, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_fence, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_fencei, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_amo, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_uses_ldq, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_uses_stq, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_unique, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_flush_on_commit, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[execution-unit.scala:104:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[execution-unit.scala:104:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[execution-unit.scala:104:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[execution-unit.scala:104:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_ldst_val, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_frs3_en, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_fp_val, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_fp_single, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_bp_debug_if, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[execution-unit.scala:104:14]
input io_brupdate_b2_valid, // @[execution-unit.scala:104:14]
input io_brupdate_b2_mispredict, // @[execution-unit.scala:104:14]
input io_brupdate_b2_taken, // @[execution-unit.scala:104:14]
input [2:0] io_brupdate_b2_cfi_type, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_pc_sel, // @[execution-unit.scala:104:14]
input [39:0] io_brupdate_b2_jalr_target, // @[execution-unit.scala:104:14]
input [20:0] io_brupdate_b2_target_offset, // @[execution-unit.scala:104:14]
output [6:0] io_brinfo_uop_uopc, // @[execution-unit.scala:104:14]
output [31:0] io_brinfo_uop_inst, // @[execution-unit.scala:104:14]
output [31:0] io_brinfo_uop_debug_inst, // @[execution-unit.scala:104:14]
output io_brinfo_uop_is_rvc, // @[execution-unit.scala:104:14]
output [39:0] io_brinfo_uop_debug_pc, // @[execution-unit.scala:104:14]
output [2:0] io_brinfo_uop_iq_type, // @[execution-unit.scala:104:14]
output [9:0] io_brinfo_uop_fu_code, // @[execution-unit.scala:104:14]
output [3:0] io_brinfo_uop_ctrl_br_type, // @[execution-unit.scala:104:14]
output [1:0] io_brinfo_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14]
output [2:0] io_brinfo_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14]
output [2:0] io_brinfo_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14]
output [4:0] io_brinfo_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14]
output io_brinfo_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14]
output [2:0] io_brinfo_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14]
output io_brinfo_uop_ctrl_is_load, // @[execution-unit.scala:104:14]
output io_brinfo_uop_ctrl_is_sta, // @[execution-unit.scala:104:14]
output io_brinfo_uop_ctrl_is_std, // @[execution-unit.scala:104:14]
output [1:0] io_brinfo_uop_iw_state, // @[execution-unit.scala:104:14]
output io_brinfo_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14]
output io_brinfo_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14]
output io_brinfo_uop_is_br, // @[execution-unit.scala:104:14]
output io_brinfo_uop_is_jalr, // @[execution-unit.scala:104:14]
output io_brinfo_uop_is_jal, // @[execution-unit.scala:104:14]
output io_brinfo_uop_is_sfb, // @[execution-unit.scala:104:14]
output [15:0] io_brinfo_uop_br_mask, // @[execution-unit.scala:104:14]
output [3:0] io_brinfo_uop_br_tag, // @[execution-unit.scala:104:14]
output [4:0] io_brinfo_uop_ftq_idx, // @[execution-unit.scala:104:14]
output io_brinfo_uop_edge_inst, // @[execution-unit.scala:104:14]
output [5:0] io_brinfo_uop_pc_lob, // @[execution-unit.scala:104:14]
output io_brinfo_uop_taken, // @[execution-unit.scala:104:14]
output [19:0] io_brinfo_uop_imm_packed, // @[execution-unit.scala:104:14]
output [11:0] io_brinfo_uop_csr_addr, // @[execution-unit.scala:104:14]
output [6:0] io_brinfo_uop_rob_idx, // @[execution-unit.scala:104:14]
output [4:0] io_brinfo_uop_ldq_idx, // @[execution-unit.scala:104:14]
output [4:0] io_brinfo_uop_stq_idx, // @[execution-unit.scala:104:14]
output [1:0] io_brinfo_uop_rxq_idx, // @[execution-unit.scala:104:14]
output [6:0] io_brinfo_uop_pdst, // @[execution-unit.scala:104:14]
output [6:0] io_brinfo_uop_prs1, // @[execution-unit.scala:104:14]
output [6:0] io_brinfo_uop_prs2, // @[execution-unit.scala:104:14]
output [6:0] io_brinfo_uop_prs3, // @[execution-unit.scala:104:14]
output [4:0] io_brinfo_uop_ppred, // @[execution-unit.scala:104:14]
output io_brinfo_uop_prs1_busy, // @[execution-unit.scala:104:14]
output io_brinfo_uop_prs2_busy, // @[execution-unit.scala:104:14]
output io_brinfo_uop_prs3_busy, // @[execution-unit.scala:104:14]
output io_brinfo_uop_ppred_busy, // @[execution-unit.scala:104:14]
output [6:0] io_brinfo_uop_stale_pdst, // @[execution-unit.scala:104:14]
output io_brinfo_uop_exception, // @[execution-unit.scala:104:14]
output [63:0] io_brinfo_uop_exc_cause, // @[execution-unit.scala:104:14]
output io_brinfo_uop_bypassable, // @[execution-unit.scala:104:14]
output [4:0] io_brinfo_uop_mem_cmd, // @[execution-unit.scala:104:14]
output [1:0] io_brinfo_uop_mem_size, // @[execution-unit.scala:104:14]
output io_brinfo_uop_mem_signed, // @[execution-unit.scala:104:14]
output io_brinfo_uop_is_fence, // @[execution-unit.scala:104:14]
output io_brinfo_uop_is_fencei, // @[execution-unit.scala:104:14]
output io_brinfo_uop_is_amo, // @[execution-unit.scala:104:14]
output io_brinfo_uop_uses_ldq, // @[execution-unit.scala:104:14]
output io_brinfo_uop_uses_stq, // @[execution-unit.scala:104:14]
output io_brinfo_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14]
output io_brinfo_uop_is_unique, // @[execution-unit.scala:104:14]
output io_brinfo_uop_flush_on_commit, // @[execution-unit.scala:104:14]
output io_brinfo_uop_ldst_is_rs1, // @[execution-unit.scala:104:14]
output [5:0] io_brinfo_uop_ldst, // @[execution-unit.scala:104:14]
output [5:0] io_brinfo_uop_lrs1, // @[execution-unit.scala:104:14]
output [5:0] io_brinfo_uop_lrs2, // @[execution-unit.scala:104:14]
output [5:0] io_brinfo_uop_lrs3, // @[execution-unit.scala:104:14]
output io_brinfo_uop_ldst_val, // @[execution-unit.scala:104:14]
output [1:0] io_brinfo_uop_dst_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_brinfo_uop_lrs1_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_brinfo_uop_lrs2_rtype, // @[execution-unit.scala:104:14]
output io_brinfo_uop_frs3_en, // @[execution-unit.scala:104:14]
output io_brinfo_uop_fp_val, // @[execution-unit.scala:104:14]
output io_brinfo_uop_fp_single, // @[execution-unit.scala:104:14]
output io_brinfo_uop_xcpt_pf_if, // @[execution-unit.scala:104:14]
output io_brinfo_uop_xcpt_ae_if, // @[execution-unit.scala:104:14]
output io_brinfo_uop_xcpt_ma_if, // @[execution-unit.scala:104:14]
output io_brinfo_uop_bp_debug_if, // @[execution-unit.scala:104:14]
output io_brinfo_uop_bp_xcpt_if, // @[execution-unit.scala:104:14]
output [1:0] io_brinfo_uop_debug_fsrc, // @[execution-unit.scala:104:14]
output [1:0] io_brinfo_uop_debug_tsrc, // @[execution-unit.scala:104:14]
output io_brinfo_valid, // @[execution-unit.scala:104:14]
output io_brinfo_mispredict, // @[execution-unit.scala:104:14]
output io_brinfo_taken, // @[execution-unit.scala:104:14]
output [2:0] io_brinfo_cfi_type, // @[execution-unit.scala:104:14]
output [1:0] io_brinfo_pc_sel, // @[execution-unit.scala:104:14]
output [39:0] io_brinfo_jalr_target, // @[execution-unit.scala:104:14]
output [20:0] io_brinfo_target_offset, // @[execution-unit.scala:104:14]
input io_get_ftq_pc_entry_cfi_idx_valid, // @[execution-unit.scala:104:14]
input [2:0] io_get_ftq_pc_entry_cfi_idx_bits, // @[execution-unit.scala:104:14]
input io_get_ftq_pc_entry_cfi_taken, // @[execution-unit.scala:104:14]
input io_get_ftq_pc_entry_cfi_mispredicted, // @[execution-unit.scala:104:14]
input [2:0] io_get_ftq_pc_entry_cfi_type, // @[execution-unit.scala:104:14]
input [7:0] io_get_ftq_pc_entry_br_mask, // @[execution-unit.scala:104:14]
input io_get_ftq_pc_entry_cfi_is_call, // @[execution-unit.scala:104:14]
input io_get_ftq_pc_entry_cfi_is_ret, // @[execution-unit.scala:104:14]
input io_get_ftq_pc_entry_cfi_npc_plus4, // @[execution-unit.scala:104:14]
input [39:0] io_get_ftq_pc_entry_ras_top, // @[execution-unit.scala:104:14]
input [4:0] io_get_ftq_pc_entry_ras_idx, // @[execution-unit.scala:104:14]
input io_get_ftq_pc_entry_start_bank, // @[execution-unit.scala:104:14]
input [39:0] io_get_ftq_pc_pc, // @[execution-unit.scala:104:14]
input io_get_ftq_pc_next_val, // @[execution-unit.scala:104:14]
input [39:0] io_get_ftq_pc_next_pc, // @[execution-unit.scala:104:14]
input io_status_debug, // @[execution-unit.scala:104:14]
input io_status_cease, // @[execution-unit.scala:104:14]
input io_status_wfi, // @[execution-unit.scala:104:14]
input [1:0] io_status_dprv, // @[execution-unit.scala:104:14]
input io_status_dv, // @[execution-unit.scala:104:14]
input [1:0] io_status_prv, // @[execution-unit.scala:104:14]
input io_status_v, // @[execution-unit.scala:104:14]
input io_status_sd, // @[execution-unit.scala:104:14]
input io_status_mpv, // @[execution-unit.scala:104:14]
input io_status_gva, // @[execution-unit.scala:104:14]
input io_status_tsr, // @[execution-unit.scala:104:14]
input io_status_tw, // @[execution-unit.scala:104:14]
input io_status_tvm, // @[execution-unit.scala:104:14]
input io_status_mxr, // @[execution-unit.scala:104:14]
input io_status_sum, // @[execution-unit.scala:104:14]
input io_status_mprv, // @[execution-unit.scala:104:14]
input [1:0] io_status_fs, // @[execution-unit.scala:104:14]
input [1:0] io_status_mpp, // @[execution-unit.scala:104:14]
input io_status_spp, // @[execution-unit.scala:104:14]
input io_status_mpie, // @[execution-unit.scala:104:14]
input io_status_spie, // @[execution-unit.scala:104:14]
input io_status_mie, // @[execution-unit.scala:104:14]
input io_status_sie // @[execution-unit.scala:104:14]
);
wire _DivUnit_io_req_ready; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_valid; // @[execution-unit.scala:366:17]
wire [6:0] _DivUnit_io_resp_bits_uop_uopc; // @[execution-unit.scala:366:17]
wire [31:0] _DivUnit_io_resp_bits_uop_inst; // @[execution-unit.scala:366:17]
wire [31:0] _DivUnit_io_resp_bits_uop_debug_inst; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_is_rvc; // @[execution-unit.scala:366:17]
wire [39:0] _DivUnit_io_resp_bits_uop_debug_pc; // @[execution-unit.scala:366:17]
wire [2:0] _DivUnit_io_resp_bits_uop_iq_type; // @[execution-unit.scala:366:17]
wire [9:0] _DivUnit_io_resp_bits_uop_fu_code; // @[execution-unit.scala:366:17]
wire [3:0] _DivUnit_io_resp_bits_uop_ctrl_br_type; // @[execution-unit.scala:366:17]
wire [1:0] _DivUnit_io_resp_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:366:17]
wire [2:0] _DivUnit_io_resp_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:366:17]
wire [2:0] _DivUnit_io_resp_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:366:17]
wire [4:0] _DivUnit_io_resp_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:366:17]
wire [2:0] _DivUnit_io_resp_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_ctrl_is_load; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_ctrl_is_sta; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_ctrl_is_std; // @[execution-unit.scala:366:17]
wire [1:0] _DivUnit_io_resp_bits_uop_iw_state; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_is_br; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_is_jalr; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_is_jal; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_is_sfb; // @[execution-unit.scala:366:17]
wire [15:0] _DivUnit_io_resp_bits_uop_br_mask; // @[execution-unit.scala:366:17]
wire [3:0] _DivUnit_io_resp_bits_uop_br_tag; // @[execution-unit.scala:366:17]
wire [4:0] _DivUnit_io_resp_bits_uop_ftq_idx; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_edge_inst; // @[execution-unit.scala:366:17]
wire [5:0] _DivUnit_io_resp_bits_uop_pc_lob; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_taken; // @[execution-unit.scala:366:17]
wire [19:0] _DivUnit_io_resp_bits_uop_imm_packed; // @[execution-unit.scala:366:17]
wire [11:0] _DivUnit_io_resp_bits_uop_csr_addr; // @[execution-unit.scala:366:17]
wire [6:0] _DivUnit_io_resp_bits_uop_rob_idx; // @[execution-unit.scala:366:17]
wire [4:0] _DivUnit_io_resp_bits_uop_ldq_idx; // @[execution-unit.scala:366:17]
wire [4:0] _DivUnit_io_resp_bits_uop_stq_idx; // @[execution-unit.scala:366:17]
wire [1:0] _DivUnit_io_resp_bits_uop_rxq_idx; // @[execution-unit.scala:366:17]
wire [6:0] _DivUnit_io_resp_bits_uop_pdst; // @[execution-unit.scala:366:17]
wire [6:0] _DivUnit_io_resp_bits_uop_prs1; // @[execution-unit.scala:366:17]
wire [6:0] _DivUnit_io_resp_bits_uop_prs2; // @[execution-unit.scala:366:17]
wire [6:0] _DivUnit_io_resp_bits_uop_prs3; // @[execution-unit.scala:366:17]
wire [4:0] _DivUnit_io_resp_bits_uop_ppred; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_prs1_busy; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_prs2_busy; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_prs3_busy; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_ppred_busy; // @[execution-unit.scala:366:17]
wire [6:0] _DivUnit_io_resp_bits_uop_stale_pdst; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_exception; // @[execution-unit.scala:366:17]
wire [63:0] _DivUnit_io_resp_bits_uop_exc_cause; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_bypassable; // @[execution-unit.scala:366:17]
wire [4:0] _DivUnit_io_resp_bits_uop_mem_cmd; // @[execution-unit.scala:366:17]
wire [1:0] _DivUnit_io_resp_bits_uop_mem_size; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_mem_signed; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_is_fence; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_is_fencei; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_is_amo; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_uses_ldq; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_uses_stq; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_is_unique; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_flush_on_commit; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_ldst_is_rs1; // @[execution-unit.scala:366:17]
wire [5:0] _DivUnit_io_resp_bits_uop_ldst; // @[execution-unit.scala:366:17]
wire [5:0] _DivUnit_io_resp_bits_uop_lrs1; // @[execution-unit.scala:366:17]
wire [5:0] _DivUnit_io_resp_bits_uop_lrs2; // @[execution-unit.scala:366:17]
wire [5:0] _DivUnit_io_resp_bits_uop_lrs3; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_ldst_val; // @[execution-unit.scala:366:17]
wire [1:0] _DivUnit_io_resp_bits_uop_dst_rtype; // @[execution-unit.scala:366:17]
wire [1:0] _DivUnit_io_resp_bits_uop_lrs1_rtype; // @[execution-unit.scala:366:17]
wire [1:0] _DivUnit_io_resp_bits_uop_lrs2_rtype; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_frs3_en; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_fp_val; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_fp_single; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_xcpt_pf_if; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_xcpt_ae_if; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_xcpt_ma_if; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_bp_debug_if; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_bp_xcpt_if; // @[execution-unit.scala:366:17]
wire [1:0] _DivUnit_io_resp_bits_uop_debug_fsrc; // @[execution-unit.scala:366:17]
wire [1:0] _DivUnit_io_resp_bits_uop_debug_tsrc; // @[execution-unit.scala:366:17]
wire [63:0] _DivUnit_io_resp_bits_data; // @[execution-unit.scala:366:17]
wire _ALUUnit_io_resp_valid; // @[execution-unit.scala:271:17]
wire [6:0] _ALUUnit_io_resp_bits_uop_uopc; // @[execution-unit.scala:271:17]
wire [31:0] _ALUUnit_io_resp_bits_uop_inst; // @[execution-unit.scala:271:17]
wire [31:0] _ALUUnit_io_resp_bits_uop_debug_inst; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_is_rvc; // @[execution-unit.scala:271:17]
wire [39:0] _ALUUnit_io_resp_bits_uop_debug_pc; // @[execution-unit.scala:271:17]
wire [2:0] _ALUUnit_io_resp_bits_uop_iq_type; // @[execution-unit.scala:271:17]
wire [9:0] _ALUUnit_io_resp_bits_uop_fu_code; // @[execution-unit.scala:271:17]
wire [3:0] _ALUUnit_io_resp_bits_uop_ctrl_br_type; // @[execution-unit.scala:271:17]
wire [1:0] _ALUUnit_io_resp_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:271:17]
wire [2:0] _ALUUnit_io_resp_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:271:17]
wire [2:0] _ALUUnit_io_resp_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:271:17]
wire [4:0] _ALUUnit_io_resp_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:271:17]
wire [2:0] _ALUUnit_io_resp_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_ctrl_is_load; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_ctrl_is_sta; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_ctrl_is_std; // @[execution-unit.scala:271:17]
wire [1:0] _ALUUnit_io_resp_bits_uop_iw_state; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_is_br; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_is_jalr; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_is_jal; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_is_sfb; // @[execution-unit.scala:271:17]
wire [15:0] _ALUUnit_io_resp_bits_uop_br_mask; // @[execution-unit.scala:271:17]
wire [3:0] _ALUUnit_io_resp_bits_uop_br_tag; // @[execution-unit.scala:271:17]
wire [4:0] _ALUUnit_io_resp_bits_uop_ftq_idx; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_edge_inst; // @[execution-unit.scala:271:17]
wire [5:0] _ALUUnit_io_resp_bits_uop_pc_lob; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_taken; // @[execution-unit.scala:271:17]
wire [19:0] _ALUUnit_io_resp_bits_uop_imm_packed; // @[execution-unit.scala:271:17]
wire [11:0] _ALUUnit_io_resp_bits_uop_csr_addr; // @[execution-unit.scala:271:17]
wire [6:0] _ALUUnit_io_resp_bits_uop_rob_idx; // @[execution-unit.scala:271:17]
wire [4:0] _ALUUnit_io_resp_bits_uop_ldq_idx; // @[execution-unit.scala:271:17]
wire [4:0] _ALUUnit_io_resp_bits_uop_stq_idx; // @[execution-unit.scala:271:17]
wire [1:0] _ALUUnit_io_resp_bits_uop_rxq_idx; // @[execution-unit.scala:271:17]
wire [6:0] _ALUUnit_io_resp_bits_uop_pdst; // @[execution-unit.scala:271:17]
wire [6:0] _ALUUnit_io_resp_bits_uop_prs1; // @[execution-unit.scala:271:17]
wire [6:0] _ALUUnit_io_resp_bits_uop_prs2; // @[execution-unit.scala:271:17]
wire [6:0] _ALUUnit_io_resp_bits_uop_prs3; // @[execution-unit.scala:271:17]
wire [4:0] _ALUUnit_io_resp_bits_uop_ppred; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_prs1_busy; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_prs2_busy; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_prs3_busy; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_ppred_busy; // @[execution-unit.scala:271:17]
wire [6:0] _ALUUnit_io_resp_bits_uop_stale_pdst; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_exception; // @[execution-unit.scala:271:17]
wire [63:0] _ALUUnit_io_resp_bits_uop_exc_cause; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_bypassable; // @[execution-unit.scala:271:17]
wire [4:0] _ALUUnit_io_resp_bits_uop_mem_cmd; // @[execution-unit.scala:271:17]
wire [1:0] _ALUUnit_io_resp_bits_uop_mem_size; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_mem_signed; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_is_fence; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_is_fencei; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_is_amo; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_uses_ldq; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_uses_stq; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_is_unique; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_flush_on_commit; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_ldst_is_rs1; // @[execution-unit.scala:271:17]
wire [5:0] _ALUUnit_io_resp_bits_uop_ldst; // @[execution-unit.scala:271:17]
wire [5:0] _ALUUnit_io_resp_bits_uop_lrs1; // @[execution-unit.scala:271:17]
wire [5:0] _ALUUnit_io_resp_bits_uop_lrs2; // @[execution-unit.scala:271:17]
wire [5:0] _ALUUnit_io_resp_bits_uop_lrs3; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_ldst_val; // @[execution-unit.scala:271:17]
wire [1:0] _ALUUnit_io_resp_bits_uop_dst_rtype; // @[execution-unit.scala:271:17]
wire [1:0] _ALUUnit_io_resp_bits_uop_lrs1_rtype; // @[execution-unit.scala:271:17]
wire [1:0] _ALUUnit_io_resp_bits_uop_lrs2_rtype; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_frs3_en; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_fp_val; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_fp_single; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_xcpt_pf_if; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_xcpt_ae_if; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_xcpt_ma_if; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_bp_debug_if; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_bp_xcpt_if; // @[execution-unit.scala:271:17]
wire [1:0] _ALUUnit_io_resp_bits_uop_debug_fsrc; // @[execution-unit.scala:271:17]
wire [1:0] _ALUUnit_io_resp_bits_uop_debug_tsrc; // @[execution-unit.scala:271:17]
wire [63:0] _ALUUnit_io_resp_bits_data; // @[execution-unit.scala:271:17]
wire [63:0] _ALUUnit_io_bypass_0_bits_data; // @[execution-unit.scala:271:17]
wire io_req_valid_0 = io_req_valid; // @[execution-unit.scala:204:7]
wire [6:0] io_req_bits_uop_uopc_0 = io_req_bits_uop_uopc; // @[execution-unit.scala:204:7]
wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[execution-unit.scala:204:7]
wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[execution-unit.scala:204:7]
wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[execution-unit.scala:204:7]
wire [2:0] io_req_bits_uop_iq_type_0 = io_req_bits_uop_iq_type; // @[execution-unit.scala:204:7]
wire [9:0] io_req_bits_uop_fu_code_0 = io_req_bits_uop_fu_code; // @[execution-unit.scala:204:7]
wire [3:0] io_req_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type; // @[execution-unit.scala:204:7]
wire [1:0] io_req_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:204:7]
wire [2:0] io_req_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:204:7]
wire [2:0] io_req_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:204:7]
wire [4:0] io_req_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:204:7]
wire [2:0] io_req_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std; // @[execution-unit.scala:204:7]
wire [1:0] io_req_bits_uop_iw_state_0 = io_req_bits_uop_iw_state; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_is_br_0 = io_req_bits_uop_is_br; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_is_jal_0 = io_req_bits_uop_is_jal; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[execution-unit.scala:204:7]
wire [15:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[execution-unit.scala:204:7]
wire [3:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[execution-unit.scala:204:7]
wire [4:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[execution-unit.scala:204:7]
wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[execution-unit.scala:204:7]
wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[execution-unit.scala:204:7]
wire [11:0] io_req_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr; // @[execution-unit.scala:204:7]
wire [6:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[execution-unit.scala:204:7]
wire [4:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[execution-unit.scala:204:7]
wire [4:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[execution-unit.scala:204:7]
wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[execution-unit.scala:204:7]
wire [6:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[execution-unit.scala:204:7]
wire [6:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[execution-unit.scala:204:7]
wire [6:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[execution-unit.scala:204:7]
wire [6:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[execution-unit.scala:204:7]
wire [4:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[execution-unit.scala:204:7]
wire [6:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[execution-unit.scala:204:7]
wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_bypassable_0 = io_req_bits_uop_bypassable; // @[execution-unit.scala:204:7]
wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[execution-unit.scala:204:7]
wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[execution-unit.scala:204:7]
wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[execution-unit.scala:204:7]
wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[execution-unit.scala:204:7]
wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[execution-unit.scala:204:7]
wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val; // @[execution-unit.scala:204:7]
wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[execution-unit.scala:204:7]
wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[execution-unit.scala:204:7]
wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_fp_single_0 = io_req_bits_uop_fp_single; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[execution-unit.scala:204:7]
wire [1:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[execution-unit.scala:204:7]
wire [1:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[execution-unit.scala:204:7]
wire [64:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data; // @[execution-unit.scala:204:7]
wire [64:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data; // @[execution-unit.scala:204:7]
wire io_req_bits_kill_0 = io_req_bits_kill; // @[execution-unit.scala:204:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[execution-unit.scala:204:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[execution-unit.scala:204:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[execution-unit.scala:204:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[execution-unit.scala:204:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[execution-unit.scala:204:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[execution-unit.scala:204:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[execution-unit.scala:204:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[execution-unit.scala:204:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[execution-unit.scala:204:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[execution-unit.scala:204:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[execution-unit.scala:204:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[execution-unit.scala:204:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[execution-unit.scala:204:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[execution-unit.scala:204:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[execution-unit.scala:204:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[execution-unit.scala:204:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[execution-unit.scala:204:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[execution-unit.scala:204:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[execution-unit.scala:204:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[execution-unit.scala:204:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[execution-unit.scala:204:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[execution-unit.scala:204:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[execution-unit.scala:204:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[execution-unit.scala:204:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[execution-unit.scala:204:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[execution-unit.scala:204:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[execution-unit.scala:204:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[execution-unit.scala:204:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[execution-unit.scala:204:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[execution-unit.scala:204:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[execution-unit.scala:204:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[execution-unit.scala:204:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[execution-unit.scala:204:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[execution-unit.scala:204:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[execution-unit.scala:204:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[execution-unit.scala:204:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[execution-unit.scala:204:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[execution-unit.scala:204:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[execution-unit.scala:204:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[execution-unit.scala:204:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[execution-unit.scala:204:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[execution-unit.scala:204:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[execution-unit.scala:204:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[execution-unit.scala:204:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[execution-unit.scala:204:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[execution-unit.scala:204:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[execution-unit.scala:204:7]
wire io_get_ftq_pc_entry_cfi_idx_valid_0 = io_get_ftq_pc_entry_cfi_idx_valid; // @[execution-unit.scala:204:7]
wire [2:0] io_get_ftq_pc_entry_cfi_idx_bits_0 = io_get_ftq_pc_entry_cfi_idx_bits; // @[execution-unit.scala:204:7]
wire io_get_ftq_pc_entry_cfi_taken_0 = io_get_ftq_pc_entry_cfi_taken; // @[execution-unit.scala:204:7]
wire io_get_ftq_pc_entry_cfi_mispredicted_0 = io_get_ftq_pc_entry_cfi_mispredicted; // @[execution-unit.scala:204:7]
wire [2:0] io_get_ftq_pc_entry_cfi_type_0 = io_get_ftq_pc_entry_cfi_type; // @[execution-unit.scala:204:7]
wire [7:0] io_get_ftq_pc_entry_br_mask_0 = io_get_ftq_pc_entry_br_mask; // @[execution-unit.scala:204:7]
wire io_get_ftq_pc_entry_cfi_is_call_0 = io_get_ftq_pc_entry_cfi_is_call; // @[execution-unit.scala:204:7]
wire io_get_ftq_pc_entry_cfi_is_ret_0 = io_get_ftq_pc_entry_cfi_is_ret; // @[execution-unit.scala:204:7]
wire io_get_ftq_pc_entry_cfi_npc_plus4_0 = io_get_ftq_pc_entry_cfi_npc_plus4; // @[execution-unit.scala:204:7]
wire [39:0] io_get_ftq_pc_entry_ras_top_0 = io_get_ftq_pc_entry_ras_top; // @[execution-unit.scala:204:7]
wire [4:0] io_get_ftq_pc_entry_ras_idx_0 = io_get_ftq_pc_entry_ras_idx; // @[execution-unit.scala:204:7]
wire io_get_ftq_pc_entry_start_bank_0 = io_get_ftq_pc_entry_start_bank; // @[execution-unit.scala:204:7]
wire [39:0] io_get_ftq_pc_pc_0 = io_get_ftq_pc_pc; // @[execution-unit.scala:204:7]
wire io_get_ftq_pc_next_val_0 = io_get_ftq_pc_next_val; // @[execution-unit.scala:204:7]
wire [39:0] io_get_ftq_pc_next_pc_0 = io_get_ftq_pc_next_pc; // @[execution-unit.scala:204:7]
wire io_status_debug_0 = io_status_debug; // @[execution-unit.scala:204:7]
wire io_status_cease_0 = io_status_cease; // @[execution-unit.scala:204:7]
wire io_status_wfi_0 = io_status_wfi; // @[execution-unit.scala:204:7]
wire [1:0] io_status_dprv_0 = io_status_dprv; // @[execution-unit.scala:204:7]
wire io_status_dv_0 = io_status_dv; // @[execution-unit.scala:204:7]
wire [1:0] io_status_prv_0 = io_status_prv; // @[execution-unit.scala:204:7]
wire io_status_v_0 = io_status_v; // @[execution-unit.scala:204:7]
wire io_status_sd_0 = io_status_sd; // @[execution-unit.scala:204:7]
wire io_status_mpv_0 = io_status_mpv; // @[execution-unit.scala:204:7]
wire io_status_gva_0 = io_status_gva; // @[execution-unit.scala:204:7]
wire io_status_tsr_0 = io_status_tsr; // @[execution-unit.scala:204:7]
wire io_status_tw_0 = io_status_tw; // @[execution-unit.scala:204:7]
wire io_status_tvm_0 = io_status_tvm; // @[execution-unit.scala:204:7]
wire io_status_mxr_0 = io_status_mxr; // @[execution-unit.scala:204:7]
wire io_status_sum_0 = io_status_sum; // @[execution-unit.scala:204:7]
wire io_status_mprv_0 = io_status_mprv; // @[execution-unit.scala:204:7]
wire [1:0] io_status_fs_0 = io_status_fs; // @[execution-unit.scala:204:7]
wire [1:0] io_status_mpp_0 = io_status_mpp; // @[execution-unit.scala:204:7]
wire io_status_spp_0 = io_status_spp; // @[execution-unit.scala:204:7]
wire io_status_mpie_0 = io_status_mpie; // @[execution-unit.scala:204:7]
wire io_status_spie_0 = io_status_spie; // @[execution-unit.scala:204:7]
wire io_status_mie_0 = io_status_mie; // @[execution-unit.scala:204:7]
wire io_status_sie_0 = io_status_sie; // @[execution-unit.scala:204:7]
wire io_req_ready = 1'h0; // @[execution-unit.scala:204:7]
wire io_req_bits_pred_data = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_predicated = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_valid = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_is_rvc = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_is_br = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_is_jalr = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_is_jal = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_is_sfb = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_edge_inst = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_taken = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_exception = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_bypassable = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_mem_signed = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_is_fence = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_is_fencei = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_is_amo = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_uses_stq = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_is_unique = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_ldst_val = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_frs3_en = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_fp_val = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_fp_single = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_predicated = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_valid = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_is_rvc = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_is_br = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_is_jalr = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_is_jal = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_is_sfb = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_edge_inst = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_taken = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_exception = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_bypassable = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_mem_signed = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_is_fence = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_is_fencei = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_is_amo = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_uses_stq = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_is_unique = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_ldst_val = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_frs3_en = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_fp_val = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_fp_single = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_get_ftq_pc_ghist_current_saw_branch_not_taken = 1'h0; // @[execution-unit.scala:204:7]
wire io_get_ftq_pc_ghist_new_saw_branch_not_taken = 1'h0; // @[execution-unit.scala:204:7]
wire io_get_ftq_pc_ghist_new_saw_branch_taken = 1'h0; // @[execution-unit.scala:204:7]
wire io_status_mbe = 1'h0; // @[execution-unit.scala:204:7]
wire io_status_sbe = 1'h0; // @[execution-unit.scala:204:7]
wire io_status_sd_rv32 = 1'h0; // @[execution-unit.scala:204:7]
wire io_status_ube = 1'h0; // @[execution-unit.scala:204:7]
wire io_status_upie = 1'h0; // @[execution-unit.scala:204:7]
wire io_status_hie = 1'h0; // @[execution-unit.scala:204:7]
wire io_status_uie = 1'h0; // @[execution-unit.scala:204:7]
wire ifpu_busy = 1'h0; // @[execution-unit.scala:254:27]
wire _io_fu_types_T_12 = 1'h0; // @[execution-unit.scala:265:33]
wire _io_iresp_bits_predicated_T = 1'h0; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_csr_addr_i30_20_T = 1'h0; // @[util.scala:274:27]
wire _io_iresp_bits_uop_csr_addr_i19_12_T = 1'h0; // @[util.scala:275:27]
wire _io_iresp_bits_uop_csr_addr_i19_12_T_1 = 1'h0; // @[util.scala:275:44]
wire _io_iresp_bits_uop_csr_addr_i19_12_T_2 = 1'h0; // @[util.scala:275:36]
wire _io_iresp_bits_uop_csr_addr_i11_T = 1'h0; // @[util.scala:276:27]
wire _io_iresp_bits_uop_csr_addr_i11_T_1 = 1'h0; // @[util.scala:277:27]
wire _io_iresp_bits_uop_csr_addr_i11_T_2 = 1'h0; // @[util.scala:277:44]
wire _io_iresp_bits_uop_csr_addr_i11_T_3 = 1'h0; // @[util.scala:277:36]
wire _io_iresp_bits_uop_csr_addr_i10_5_T = 1'h0; // @[util.scala:278:27]
wire _io_iresp_bits_uop_csr_addr_i4_1_T = 1'h0; // @[util.scala:279:27]
wire _io_iresp_bits_uop_csr_addr_i0_T = 1'h0; // @[util.scala:280:27]
wire [31:0] io_status_isa = 32'h14112D; // @[execution-unit.scala:204:7]
wire [22:0] io_status_zero2 = 23'h0; // @[execution-unit.scala:204:7]
wire [7:0] io_status_zero1 = 8'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_fflags_bits_uop_iw_state = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_fflags_bits_uop_mem_size = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_iw_state = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_mem_size = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_status_xs = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_status_vs = 2'h0; // @[execution-unit.scala:204:7]
wire [64:0] io_req_bits_rs3_data = 65'h0; // @[execution-unit.scala:204:7]
wire io_iresp_ready = 1'h1; // @[execution-unit.scala:204:7]
wire _io_fu_types_T_11 = 1'h1; // @[execution-unit.scala:265:22]
wire _io_iresp_bits_uop_csr_addr_i0_T_1 = 1'h1; // @[util.scala:280:44]
wire _io_iresp_bits_uop_csr_addr_i0_T_2 = 1'h1; // @[util.scala:280:36]
wire [6:0] io_iresp_bits_fflags_bits_uop_uopc = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_iresp_bits_fflags_bits_uop_rob_idx = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_iresp_bits_fflags_bits_uop_pdst = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_iresp_bits_fflags_bits_uop_prs1 = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_iresp_bits_fflags_bits_uop_prs2 = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_iresp_bits_fflags_bits_uop_prs3 = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_iresp_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_0_bits_fflags_bits_uop_uopc = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_0_bits_fflags_bits_uop_rob_idx = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_0_bits_fflags_bits_uop_pdst = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_0_bits_fflags_bits_uop_prs1 = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_0_bits_fflags_bits_uop_prs2 = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_0_bits_fflags_bits_uop_prs3 = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_0_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[execution-unit.scala:204:7]
wire [31:0] io_iresp_bits_fflags_bits_uop_inst = 32'h0; // @[execution-unit.scala:204:7]
wire [31:0] io_iresp_bits_fflags_bits_uop_debug_inst = 32'h0; // @[execution-unit.scala:204:7]
wire [31:0] io_bypass_0_bits_fflags_bits_uop_inst = 32'h0; // @[execution-unit.scala:204:7]
wire [31:0] io_bypass_0_bits_fflags_bits_uop_debug_inst = 32'h0; // @[execution-unit.scala:204:7]
wire [39:0] io_iresp_bits_fflags_bits_uop_debug_pc = 40'h0; // @[execution-unit.scala:204:7]
wire [39:0] io_bypass_0_bits_fflags_bits_uop_debug_pc = 40'h0; // @[execution-unit.scala:204:7]
wire [39:0] io_get_ftq_pc_com_pc = 40'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_iresp_bits_fflags_bits_uop_iq_type = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_iresp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_iresp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_iresp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_0_bits_fflags_bits_uop_iq_type = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_0_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_0_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_0_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[execution-unit.scala:204:7]
wire [9:0] io_iresp_bits_fflags_bits_uop_fu_code = 10'h0; // @[execution-unit.scala:204:7]
wire [9:0] io_bypass_0_bits_fflags_bits_uop_fu_code = 10'h0; // @[execution-unit.scala:204:7]
wire [9:0] _io_fu_types_T_1 = 10'h0; // @[execution-unit.scala:261:21]
wire [9:0] _io_fu_types_T_7 = 10'h0; // @[execution-unit.scala:263:21]
wire [9:0] _io_fu_types_T_13 = 10'h0; // @[execution-unit.scala:265:21]
wire [9:0] _io_fu_types_T_15 = 10'h0; // @[execution-unit.scala:266:21]
wire [3:0] io_iresp_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[execution-unit.scala:204:7]
wire [3:0] io_iresp_bits_fflags_bits_uop_br_tag = 4'h0; // @[execution-unit.scala:204:7]
wire [3:0] io_bypass_0_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[execution-unit.scala:204:7]
wire [3:0] io_bypass_0_bits_fflags_bits_uop_br_tag = 4'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_iresp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_iresp_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_iresp_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_iresp_bits_fflags_bits_uop_stq_idx = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_iresp_bits_fflags_bits_uop_ppred = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_iresp_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_iresp_bits_fflags_bits_flags = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_0_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_0_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_0_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_0_bits_fflags_bits_uop_stq_idx = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_0_bits_fflags_bits_uop_ppred = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_0_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_0_bits_fflags_bits_flags = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_get_ftq_pc_ftq_idx = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_get_ftq_pc_ghist_ras_idx = 5'h0; // @[execution-unit.scala:204:7]
wire [15:0] io_iresp_bits_fflags_bits_uop_br_mask = 16'h0; // @[execution-unit.scala:204:7]
wire [15:0] io_bypass_0_bits_fflags_bits_uop_br_mask = 16'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_iresp_bits_fflags_bits_uop_pc_lob = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_iresp_bits_fflags_bits_uop_ldst = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_iresp_bits_fflags_bits_uop_lrs1 = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_iresp_bits_fflags_bits_uop_lrs2 = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_iresp_bits_fflags_bits_uop_lrs3 = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_0_bits_fflags_bits_uop_pc_lob = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_0_bits_fflags_bits_uop_ldst = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_0_bits_fflags_bits_uop_lrs1 = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_0_bits_fflags_bits_uop_lrs2 = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_0_bits_fflags_bits_uop_lrs3 = 6'h0; // @[execution-unit.scala:204:7]
wire [19:0] io_iresp_bits_fflags_bits_uop_imm_packed = 20'h0; // @[execution-unit.scala:204:7]
wire [19:0] io_bypass_0_bits_fflags_bits_uop_imm_packed = 20'h0; // @[execution-unit.scala:204:7]
wire [11:0] io_iresp_bits_fflags_bits_uop_csr_addr = 12'h0; // @[execution-unit.scala:204:7]
wire [11:0] io_bypass_0_bits_fflags_bits_uop_csr_addr = 12'h0; // @[execution-unit.scala:204:7]
wire [63:0] io_iresp_bits_fflags_bits_uop_exc_cause = 64'h0; // @[execution-unit.scala:204:7]
wire [63:0] io_bypass_0_bits_fflags_bits_uop_exc_cause = 64'h0; // @[execution-unit.scala:204:7]
wire [63:0] io_get_ftq_pc_ghist_old_history = 64'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_status_sxl = 2'h2; // @[execution-unit.scala:204:7]
wire [1:0] io_status_uxl = 2'h2; // @[execution-unit.scala:204:7]
wire [9:0] _io_fu_types_T_9 = 10'h2; // @[execution-unit.scala:264:21]
wire [9:0] _io_fu_types_T = 10'h1; // @[execution-unit.scala:260:21]
wire [9:0] _io_fu_types_T_2 = 10'h1; // @[execution-unit.scala:260:45]
wire [9:0] _io_fu_types_T_16; // @[execution-unit.scala:265:60]
wire _io_iresp_valid_T; // @[execution-unit.scala:409:71]
wire [6:0] _io_iresp_bits_uop_T_uopc; // @[Mux.scala:50:70]
wire [31:0] _io_iresp_bits_uop_T_inst; // @[Mux.scala:50:70]
wire [31:0] _io_iresp_bits_uop_T_debug_inst; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_is_rvc; // @[Mux.scala:50:70]
wire [39:0] _io_iresp_bits_uop_T_debug_pc; // @[Mux.scala:50:70]
wire [2:0] _io_iresp_bits_uop_T_iq_type; // @[Mux.scala:50:70]
wire [9:0] _io_iresp_bits_uop_T_fu_code; // @[Mux.scala:50:70]
wire [3:0] _io_iresp_bits_uop_T_ctrl_br_type; // @[Mux.scala:50:70]
wire [1:0] _io_iresp_bits_uop_T_ctrl_op1_sel; // @[Mux.scala:50:70]
wire [2:0] _io_iresp_bits_uop_T_ctrl_op2_sel; // @[Mux.scala:50:70]
wire [2:0] _io_iresp_bits_uop_T_ctrl_imm_sel; // @[Mux.scala:50:70]
wire [4:0] _io_iresp_bits_uop_T_ctrl_op_fcn; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_ctrl_fcn_dw; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_ctrl_is_load; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_ctrl_is_sta; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_ctrl_is_std; // @[Mux.scala:50:70]
wire [1:0] _io_iresp_bits_uop_T_iw_state; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_iw_p1_poisoned; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_iw_p2_poisoned; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_is_br; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_is_jalr; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_is_jal; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_is_sfb; // @[Mux.scala:50:70]
wire [15:0] _io_iresp_bits_uop_T_br_mask; // @[Mux.scala:50:70]
wire [3:0] _io_iresp_bits_uop_T_br_tag; // @[Mux.scala:50:70]
wire [4:0] _io_iresp_bits_uop_T_ftq_idx; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_edge_inst; // @[Mux.scala:50:70]
wire [5:0] _io_iresp_bits_uop_T_pc_lob; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_taken; // @[Mux.scala:50:70]
wire [19:0] _io_iresp_bits_uop_T_imm_packed; // @[Mux.scala:50:70]
wire [6:0] _io_iresp_bits_uop_T_rob_idx; // @[Mux.scala:50:70]
wire [4:0] _io_iresp_bits_uop_T_ldq_idx; // @[Mux.scala:50:70]
wire [4:0] _io_iresp_bits_uop_T_stq_idx; // @[Mux.scala:50:70]
wire [1:0] _io_iresp_bits_uop_T_rxq_idx; // @[Mux.scala:50:70]
wire [6:0] _io_iresp_bits_uop_T_pdst; // @[Mux.scala:50:70]
wire [6:0] _io_iresp_bits_uop_T_prs1; // @[Mux.scala:50:70]
wire [6:0] _io_iresp_bits_uop_T_prs2; // @[Mux.scala:50:70]
wire [6:0] _io_iresp_bits_uop_T_prs3; // @[Mux.scala:50:70]
wire [4:0] _io_iresp_bits_uop_T_ppred; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_prs1_busy; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_prs2_busy; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_prs3_busy; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_ppred_busy; // @[Mux.scala:50:70]
wire [6:0] _io_iresp_bits_uop_T_stale_pdst; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_exception; // @[Mux.scala:50:70]
wire [63:0] _io_iresp_bits_uop_T_exc_cause; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_bypassable; // @[Mux.scala:50:70]
wire [4:0] _io_iresp_bits_uop_T_mem_cmd; // @[Mux.scala:50:70]
wire [1:0] _io_iresp_bits_uop_T_mem_size; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_mem_signed; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_is_fence; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_is_fencei; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_is_amo; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_uses_ldq; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_uses_stq; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_is_sys_pc2epc; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_is_unique; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_flush_on_commit; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_ldst_is_rs1; // @[Mux.scala:50:70]
wire [5:0] _io_iresp_bits_uop_T_ldst; // @[Mux.scala:50:70]
wire [5:0] _io_iresp_bits_uop_T_lrs1; // @[Mux.scala:50:70]
wire [5:0] _io_iresp_bits_uop_T_lrs2; // @[Mux.scala:50:70]
wire [5:0] _io_iresp_bits_uop_T_lrs3; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_ldst_val; // @[Mux.scala:50:70]
wire [1:0] _io_iresp_bits_uop_T_dst_rtype; // @[Mux.scala:50:70]
wire [1:0] _io_iresp_bits_uop_T_lrs1_rtype; // @[Mux.scala:50:70]
wire [1:0] _io_iresp_bits_uop_T_lrs2_rtype; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_frs3_en; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_fp_val; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_fp_single; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_xcpt_pf_if; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_xcpt_ae_if; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_xcpt_ma_if; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_bp_debug_if; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_bp_xcpt_if; // @[Mux.scala:50:70]
wire [1:0] _io_iresp_bits_uop_T_debug_fsrc; // @[Mux.scala:50:70]
wire [1:0] _io_iresp_bits_uop_T_debug_tsrc; // @[Mux.scala:50:70]
wire [3:0] io_iresp_bits_uop_ctrl_br_type_0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_uop_ctrl_op1_sel_0; // @[execution-unit.scala:204:7]
wire [2:0] io_iresp_bits_uop_ctrl_op2_sel_0; // @[execution-unit.scala:204:7]
wire [2:0] io_iresp_bits_uop_ctrl_imm_sel_0; // @[execution-unit.scala:204:7]
wire [4:0] io_iresp_bits_uop_ctrl_op_fcn_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_ctrl_fcn_dw_0; // @[execution-unit.scala:204:7]
wire [2:0] io_iresp_bits_uop_ctrl_csr_cmd_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_ctrl_is_load_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_ctrl_is_sta_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_ctrl_is_std_0; // @[execution-unit.scala:204:7]
wire [6:0] io_iresp_bits_uop_uopc_0; // @[execution-unit.scala:204:7]
wire [31:0] io_iresp_bits_uop_inst_0; // @[execution-unit.scala:204:7]
wire [31:0] io_iresp_bits_uop_debug_inst_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_is_rvc_0; // @[execution-unit.scala:204:7]
wire [39:0] io_iresp_bits_uop_debug_pc_0; // @[execution-unit.scala:204:7]
wire [2:0] io_iresp_bits_uop_iq_type_0; // @[execution-unit.scala:204:7]
wire [9:0] io_iresp_bits_uop_fu_code_0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_uop_iw_state_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_iw_p1_poisoned_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_iw_p2_poisoned_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_is_br_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_is_jalr_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_is_jal_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_is_sfb_0; // @[execution-unit.scala:204:7]
wire [15:0] io_iresp_bits_uop_br_mask_0; // @[execution-unit.scala:204:7]
wire [3:0] io_iresp_bits_uop_br_tag_0; // @[execution-unit.scala:204:7]
wire [4:0] io_iresp_bits_uop_ftq_idx_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_edge_inst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_iresp_bits_uop_pc_lob_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_taken_0; // @[execution-unit.scala:204:7]
wire [19:0] io_iresp_bits_uop_imm_packed_0; // @[execution-unit.scala:204:7]
wire [11:0] io_iresp_bits_uop_csr_addr_0; // @[execution-unit.scala:204:7]
wire [6:0] io_iresp_bits_uop_rob_idx_0; // @[execution-unit.scala:204:7]
wire [4:0] io_iresp_bits_uop_ldq_idx_0; // @[execution-unit.scala:204:7]
wire [4:0] io_iresp_bits_uop_stq_idx_0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_uop_rxq_idx_0; // @[execution-unit.scala:204:7]
wire [6:0] io_iresp_bits_uop_pdst_0; // @[execution-unit.scala:204:7]
wire [6:0] io_iresp_bits_uop_prs1_0; // @[execution-unit.scala:204:7]
wire [6:0] io_iresp_bits_uop_prs2_0; // @[execution-unit.scala:204:7]
wire [6:0] io_iresp_bits_uop_prs3_0; // @[execution-unit.scala:204:7]
wire [4:0] io_iresp_bits_uop_ppred_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_prs1_busy_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_prs2_busy_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_prs3_busy_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_ppred_busy_0; // @[execution-unit.scala:204:7]
wire [6:0] io_iresp_bits_uop_stale_pdst_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_exception_0; // @[execution-unit.scala:204:7]
wire [63:0] io_iresp_bits_uop_exc_cause_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_bypassable_0; // @[execution-unit.scala:204:7]
wire [4:0] io_iresp_bits_uop_mem_cmd_0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_uop_mem_size_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_mem_signed_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_is_fence_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_is_fencei_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_is_amo_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_uses_ldq_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_uses_stq_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_is_sys_pc2epc_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_is_unique_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_flush_on_commit_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_ldst_is_rs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_iresp_bits_uop_ldst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_iresp_bits_uop_lrs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_iresp_bits_uop_lrs2_0; // @[execution-unit.scala:204:7]
wire [5:0] io_iresp_bits_uop_lrs3_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_ldst_val_0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_uop_dst_rtype_0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_uop_lrs1_rtype_0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_uop_lrs2_rtype_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_frs3_en_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_fp_val_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_fp_single_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_xcpt_pf_if_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_xcpt_ae_if_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_xcpt_ma_if_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_bp_debug_if_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_bp_xcpt_if_0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_uop_debug_fsrc_0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_uop_debug_tsrc_0; // @[execution-unit.scala:204:7]
wire [64:0] io_iresp_bits_data_0; // @[execution-unit.scala:204:7]
wire io_iresp_valid_0; // @[execution-unit.scala:204:7]
wire [3:0] io_bypass_0_bits_uop_ctrl_br_type_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_uop_ctrl_op1_sel_0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_0_bits_uop_ctrl_op2_sel_0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_0_bits_uop_ctrl_imm_sel_0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_0_bits_uop_ctrl_op_fcn_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_ctrl_fcn_dw_0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_0_bits_uop_ctrl_csr_cmd_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_ctrl_is_load_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_ctrl_is_sta_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_ctrl_is_std_0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_0_bits_uop_uopc_0; // @[execution-unit.scala:204:7]
wire [31:0] io_bypass_0_bits_uop_inst_0; // @[execution-unit.scala:204:7]
wire [31:0] io_bypass_0_bits_uop_debug_inst_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_is_rvc_0; // @[execution-unit.scala:204:7]
wire [39:0] io_bypass_0_bits_uop_debug_pc_0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_0_bits_uop_iq_type_0; // @[execution-unit.scala:204:7]
wire [9:0] io_bypass_0_bits_uop_fu_code_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_uop_iw_state_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_iw_p1_poisoned_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_iw_p2_poisoned_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_is_br_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_is_jalr_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_is_jal_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_is_sfb_0; // @[execution-unit.scala:204:7]
wire [15:0] io_bypass_0_bits_uop_br_mask_0; // @[execution-unit.scala:204:7]
wire [3:0] io_bypass_0_bits_uop_br_tag_0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_0_bits_uop_ftq_idx_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_edge_inst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_0_bits_uop_pc_lob_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_taken_0; // @[execution-unit.scala:204:7]
wire [19:0] io_bypass_0_bits_uop_imm_packed_0; // @[execution-unit.scala:204:7]
wire [11:0] io_bypass_0_bits_uop_csr_addr_0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_0_bits_uop_rob_idx_0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_0_bits_uop_ldq_idx_0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_0_bits_uop_stq_idx_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_uop_rxq_idx_0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_0_bits_uop_pdst_0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_0_bits_uop_prs1_0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_0_bits_uop_prs2_0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_0_bits_uop_prs3_0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_0_bits_uop_ppred_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_prs1_busy_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_prs2_busy_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_prs3_busy_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_ppred_busy_0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_0_bits_uop_stale_pdst_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_exception_0; // @[execution-unit.scala:204:7]
wire [63:0] io_bypass_0_bits_uop_exc_cause_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_bypassable_0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_0_bits_uop_mem_cmd_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_uop_mem_size_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_mem_signed_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_is_fence_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_is_fencei_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_is_amo_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_uses_ldq_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_uses_stq_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_is_sys_pc2epc_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_is_unique_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_flush_on_commit_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_ldst_is_rs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_0_bits_uop_ldst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_0_bits_uop_lrs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_0_bits_uop_lrs2_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_0_bits_uop_lrs3_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_ldst_val_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_uop_dst_rtype_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_uop_lrs1_rtype_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_uop_lrs2_rtype_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_frs3_en_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_fp_val_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_fp_single_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_xcpt_pf_if_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_xcpt_ae_if_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_xcpt_ma_if_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_bp_debug_if_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_bp_xcpt_if_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_uop_debug_fsrc_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_uop_debug_tsrc_0; // @[execution-unit.scala:204:7]
wire [64:0] io_bypass_0_bits_data_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_valid_0; // @[execution-unit.scala:204:7]
wire [3:0] io_brinfo_uop_ctrl_br_type_0; // @[execution-unit.scala:204:7]
wire [1:0] io_brinfo_uop_ctrl_op1_sel_0; // @[execution-unit.scala:204:7]
wire [2:0] io_brinfo_uop_ctrl_op2_sel_0; // @[execution-unit.scala:204:7]
wire [2:0] io_brinfo_uop_ctrl_imm_sel_0; // @[execution-unit.scala:204:7]
wire [4:0] io_brinfo_uop_ctrl_op_fcn_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_ctrl_fcn_dw_0; // @[execution-unit.scala:204:7]
wire [2:0] io_brinfo_uop_ctrl_csr_cmd_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_ctrl_is_load_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_ctrl_is_sta_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_ctrl_is_std_0; // @[execution-unit.scala:204:7]
wire [6:0] io_brinfo_uop_uopc_0; // @[execution-unit.scala:204:7]
wire [31:0] io_brinfo_uop_inst_0; // @[execution-unit.scala:204:7]
wire [31:0] io_brinfo_uop_debug_inst_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_is_rvc_0; // @[execution-unit.scala:204:7]
wire [39:0] io_brinfo_uop_debug_pc_0; // @[execution-unit.scala:204:7]
wire [2:0] io_brinfo_uop_iq_type_0; // @[execution-unit.scala:204:7]
wire [9:0] io_brinfo_uop_fu_code_0; // @[execution-unit.scala:204:7]
wire [1:0] io_brinfo_uop_iw_state_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_iw_p1_poisoned_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_iw_p2_poisoned_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_is_br_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_is_jalr_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_is_jal_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_is_sfb_0; // @[execution-unit.scala:204:7]
wire [15:0] io_brinfo_uop_br_mask_0; // @[execution-unit.scala:204:7]
wire [3:0] io_brinfo_uop_br_tag_0; // @[execution-unit.scala:204:7]
wire [4:0] io_brinfo_uop_ftq_idx_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_edge_inst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_brinfo_uop_pc_lob_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_taken_0; // @[execution-unit.scala:204:7]
wire [19:0] io_brinfo_uop_imm_packed_0; // @[execution-unit.scala:204:7]
wire [11:0] io_brinfo_uop_csr_addr_0; // @[execution-unit.scala:204:7]
wire [6:0] io_brinfo_uop_rob_idx_0; // @[execution-unit.scala:204:7]
wire [4:0] io_brinfo_uop_ldq_idx_0; // @[execution-unit.scala:204:7]
wire [4:0] io_brinfo_uop_stq_idx_0; // @[execution-unit.scala:204:7]
wire [1:0] io_brinfo_uop_rxq_idx_0; // @[execution-unit.scala:204:7]
wire [6:0] io_brinfo_uop_pdst_0; // @[execution-unit.scala:204:7]
wire [6:0] io_brinfo_uop_prs1_0; // @[execution-unit.scala:204:7]
wire [6:0] io_brinfo_uop_prs2_0; // @[execution-unit.scala:204:7]
wire [6:0] io_brinfo_uop_prs3_0; // @[execution-unit.scala:204:7]
wire [4:0] io_brinfo_uop_ppred_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_prs1_busy_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_prs2_busy_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_prs3_busy_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_ppred_busy_0; // @[execution-unit.scala:204:7]
wire [6:0] io_brinfo_uop_stale_pdst_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_exception_0; // @[execution-unit.scala:204:7]
wire [63:0] io_brinfo_uop_exc_cause_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_bypassable_0; // @[execution-unit.scala:204:7]
wire [4:0] io_brinfo_uop_mem_cmd_0; // @[execution-unit.scala:204:7]
wire [1:0] io_brinfo_uop_mem_size_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_mem_signed_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_is_fence_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_is_fencei_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_is_amo_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_uses_ldq_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_uses_stq_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_is_sys_pc2epc_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_is_unique_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_flush_on_commit_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_ldst_is_rs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_brinfo_uop_ldst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_brinfo_uop_lrs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_brinfo_uop_lrs2_0; // @[execution-unit.scala:204:7]
wire [5:0] io_brinfo_uop_lrs3_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_ldst_val_0; // @[execution-unit.scala:204:7]
wire [1:0] io_brinfo_uop_dst_rtype_0; // @[execution-unit.scala:204:7]
wire [1:0] io_brinfo_uop_lrs1_rtype_0; // @[execution-unit.scala:204:7]
wire [1:0] io_brinfo_uop_lrs2_rtype_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_frs3_en_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_fp_val_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_fp_single_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_xcpt_pf_if_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_xcpt_ae_if_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_xcpt_ma_if_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_bp_debug_if_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_bp_xcpt_if_0; // @[execution-unit.scala:204:7]
wire [1:0] io_brinfo_uop_debug_fsrc_0; // @[execution-unit.scala:204:7]
wire [1:0] io_brinfo_uop_debug_tsrc_0; // @[execution-unit.scala:204:7]
wire io_brinfo_valid_0; // @[execution-unit.scala:204:7]
wire io_brinfo_mispredict_0; // @[execution-unit.scala:204:7]
wire io_brinfo_taken_0; // @[execution-unit.scala:204:7]
wire [2:0] io_brinfo_cfi_type_0; // @[execution-unit.scala:204:7]
wire [1:0] io_brinfo_pc_sel_0; // @[execution-unit.scala:204:7]
wire [39:0] io_brinfo_jalr_target_0; // @[execution-unit.scala:204:7]
wire [20:0] io_brinfo_target_offset_0; // @[execution-unit.scala:204:7]
wire [9:0] io_fu_types_0; // @[execution-unit.scala:204:7]
wire _div_busy_T_4; // @[execution-unit.scala:379:39]
wire div_busy; // @[execution-unit.scala:253:27]
wire _io_fu_types_T_3 = ~div_busy; // @[execution-unit.scala:253:27, :262:22]
wire _io_fu_types_T_4 = _io_fu_types_T_3; // @[execution-unit.scala:262:{22,32}]
wire [9:0] _io_fu_types_T_5 = {5'h0, _io_fu_types_T_4, 4'h0}; // @[execution-unit.scala:262:{21,32}]
wire [9:0] _io_fu_types_T_6 = _io_fu_types_T_5 | 10'h1; // @[execution-unit.scala:261:45, :262:21]
wire [9:0] _io_fu_types_T_8 = _io_fu_types_T_6; // @[execution-unit.scala:261:45, :262:58]
wire [9:0] _io_fu_types_T_10 = _io_fu_types_T_8 | 10'h2; // @[execution-unit.scala:262:58, :263:45]
wire [9:0] _io_fu_types_T_14 = _io_fu_types_T_10; // @[execution-unit.scala:263:45, :264:49]
assign _io_fu_types_T_16 = _io_fu_types_T_14; // @[execution-unit.scala:264:49, :265:60]
assign io_fu_types_0 = _io_fu_types_T_16; // @[execution-unit.scala:204:7, :265:60]
assign io_bypass_0_bits_data_0 = {1'h0, _ALUUnit_io_bypass_0_bits_data}; // @[execution-unit.scala:204:7, :271:17, :293:15]
wire div_resp_val; // @[execution-unit.scala:364:30]
wire [9:0] _div_busy_T_1 = io_req_bits_uop_fu_code_0 & 10'h10; // @[execution-unit.scala:204:7]
wire _div_busy_T = ~_DivUnit_io_req_ready; // @[execution-unit.scala:366:17, :379:21]
wire _div_busy_T_2 = |_div_busy_T_1; // @[micro-op.scala:154:{40,47}]
wire _div_busy_T_3 = io_req_valid_0 & _div_busy_T_2; // @[execution-unit.scala:204:7, :380:35]
assign _div_busy_T_4 = _div_busy_T | _div_busy_T_3; // @[execution-unit.scala:379:{21,39}, :380:35]
assign div_busy = _div_busy_T_4; // @[execution-unit.scala:253:27, :379:39]
assign _io_iresp_valid_T = _ALUUnit_io_resp_valid | _DivUnit_io_resp_valid; // @[execution-unit.scala:271:17, :366:17, :409:71]
assign io_iresp_valid_0 = _io_iresp_valid_T; // @[execution-unit.scala:204:7, :409:71]
assign _io_iresp_bits_uop_T_uopc = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_uopc : _DivUnit_io_resp_bits_uop_uopc; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_inst = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_inst : _DivUnit_io_resp_bits_uop_inst; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_debug_inst = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_debug_inst : _DivUnit_io_resp_bits_uop_debug_inst; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_is_rvc = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_rvc : _DivUnit_io_resp_bits_uop_is_rvc; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_debug_pc = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_debug_pc : _DivUnit_io_resp_bits_uop_debug_pc; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_iq_type = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_iq_type : _DivUnit_io_resp_bits_uop_iq_type; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_fu_code = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_fu_code : _DivUnit_io_resp_bits_uop_fu_code; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_ctrl_br_type = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_br_type : _DivUnit_io_resp_bits_uop_ctrl_br_type; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_ctrl_op1_sel = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_op1_sel : _DivUnit_io_resp_bits_uop_ctrl_op1_sel; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_ctrl_op2_sel = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_op2_sel : _DivUnit_io_resp_bits_uop_ctrl_op2_sel; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_ctrl_imm_sel = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_imm_sel : _DivUnit_io_resp_bits_uop_ctrl_imm_sel; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_ctrl_op_fcn = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_op_fcn : _DivUnit_io_resp_bits_uop_ctrl_op_fcn; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_ctrl_fcn_dw = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_fcn_dw : _DivUnit_io_resp_bits_uop_ctrl_fcn_dw; // @[Mux.scala:50:70]
wire [2:0] _io_iresp_bits_uop_T_ctrl_csr_cmd = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_csr_cmd : _DivUnit_io_resp_bits_uop_ctrl_csr_cmd; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_ctrl_is_load = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_is_load : _DivUnit_io_resp_bits_uop_ctrl_is_load; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_ctrl_is_sta = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_is_sta : _DivUnit_io_resp_bits_uop_ctrl_is_sta; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_ctrl_is_std = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_is_std : _DivUnit_io_resp_bits_uop_ctrl_is_std; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_iw_state = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_iw_state : _DivUnit_io_resp_bits_uop_iw_state; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_iw_p1_poisoned = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_iw_p1_poisoned : _DivUnit_io_resp_bits_uop_iw_p1_poisoned; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_iw_p2_poisoned = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_iw_p2_poisoned : _DivUnit_io_resp_bits_uop_iw_p2_poisoned; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_is_br = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_br : _DivUnit_io_resp_bits_uop_is_br; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_is_jalr = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_jalr : _DivUnit_io_resp_bits_uop_is_jalr; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_is_jal = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_jal : _DivUnit_io_resp_bits_uop_is_jal; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_is_sfb = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_sfb : _DivUnit_io_resp_bits_uop_is_sfb; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_br_mask = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_br_mask : _DivUnit_io_resp_bits_uop_br_mask; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_br_tag = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_br_tag : _DivUnit_io_resp_bits_uop_br_tag; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_ftq_idx = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ftq_idx : _DivUnit_io_resp_bits_uop_ftq_idx; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_edge_inst = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_edge_inst : _DivUnit_io_resp_bits_uop_edge_inst; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_pc_lob = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_pc_lob : _DivUnit_io_resp_bits_uop_pc_lob; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_taken = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_taken : _DivUnit_io_resp_bits_uop_taken; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_imm_packed = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_imm_packed : _DivUnit_io_resp_bits_uop_imm_packed; // @[Mux.scala:50:70]
wire [11:0] _io_iresp_bits_uop_T_csr_addr = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_csr_addr : _DivUnit_io_resp_bits_uop_csr_addr; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_rob_idx = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_rob_idx : _DivUnit_io_resp_bits_uop_rob_idx; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_ldq_idx = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ldq_idx : _DivUnit_io_resp_bits_uop_ldq_idx; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_stq_idx = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_stq_idx : _DivUnit_io_resp_bits_uop_stq_idx; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_rxq_idx = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_rxq_idx : _DivUnit_io_resp_bits_uop_rxq_idx; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_pdst = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_pdst : _DivUnit_io_resp_bits_uop_pdst; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_prs1 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_prs1 : _DivUnit_io_resp_bits_uop_prs1; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_prs2 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_prs2 : _DivUnit_io_resp_bits_uop_prs2; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_prs3 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_prs3 : _DivUnit_io_resp_bits_uop_prs3; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_ppred = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ppred : _DivUnit_io_resp_bits_uop_ppred; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_prs1_busy = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_prs1_busy : _DivUnit_io_resp_bits_uop_prs1_busy; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_prs2_busy = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_prs2_busy : _DivUnit_io_resp_bits_uop_prs2_busy; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_prs3_busy = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_prs3_busy : _DivUnit_io_resp_bits_uop_prs3_busy; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_ppred_busy = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ppred_busy : _DivUnit_io_resp_bits_uop_ppred_busy; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_stale_pdst = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_stale_pdst : _DivUnit_io_resp_bits_uop_stale_pdst; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_exception = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_exception : _DivUnit_io_resp_bits_uop_exception; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_exc_cause = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_exc_cause : _DivUnit_io_resp_bits_uop_exc_cause; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_bypassable = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_bypassable : _DivUnit_io_resp_bits_uop_bypassable; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_mem_cmd = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_mem_cmd : _DivUnit_io_resp_bits_uop_mem_cmd; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_mem_size = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_mem_size : _DivUnit_io_resp_bits_uop_mem_size; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_mem_signed = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_mem_signed : _DivUnit_io_resp_bits_uop_mem_signed; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_is_fence = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_fence : _DivUnit_io_resp_bits_uop_is_fence; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_is_fencei = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_fencei : _DivUnit_io_resp_bits_uop_is_fencei; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_is_amo = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_amo : _DivUnit_io_resp_bits_uop_is_amo; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_uses_ldq = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_uses_ldq : _DivUnit_io_resp_bits_uop_uses_ldq; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_uses_stq = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_uses_stq : _DivUnit_io_resp_bits_uop_uses_stq; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_is_sys_pc2epc = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_sys_pc2epc : _DivUnit_io_resp_bits_uop_is_sys_pc2epc; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_is_unique = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_unique : _DivUnit_io_resp_bits_uop_is_unique; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_flush_on_commit = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_flush_on_commit : _DivUnit_io_resp_bits_uop_flush_on_commit; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_ldst_is_rs1 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ldst_is_rs1 : _DivUnit_io_resp_bits_uop_ldst_is_rs1; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_ldst = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ldst : _DivUnit_io_resp_bits_uop_ldst; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_lrs1 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_lrs1 : _DivUnit_io_resp_bits_uop_lrs1; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_lrs2 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_lrs2 : _DivUnit_io_resp_bits_uop_lrs2; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_lrs3 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_lrs3 : _DivUnit_io_resp_bits_uop_lrs3; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_ldst_val = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ldst_val : _DivUnit_io_resp_bits_uop_ldst_val; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_dst_rtype = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_dst_rtype : _DivUnit_io_resp_bits_uop_dst_rtype; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_lrs1_rtype = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_lrs1_rtype : _DivUnit_io_resp_bits_uop_lrs1_rtype; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_lrs2_rtype = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_lrs2_rtype : _DivUnit_io_resp_bits_uop_lrs2_rtype; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_frs3_en = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_frs3_en : _DivUnit_io_resp_bits_uop_frs3_en; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_fp_val = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_fp_val : _DivUnit_io_resp_bits_uop_fp_val; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_fp_single = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_fp_single : _DivUnit_io_resp_bits_uop_fp_single; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_xcpt_pf_if = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_xcpt_pf_if : _DivUnit_io_resp_bits_uop_xcpt_pf_if; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_xcpt_ae_if = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_xcpt_ae_if : _DivUnit_io_resp_bits_uop_xcpt_ae_if; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_xcpt_ma_if = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_xcpt_ma_if : _DivUnit_io_resp_bits_uop_xcpt_ma_if; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_bp_debug_if = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_bp_debug_if : _DivUnit_io_resp_bits_uop_bp_debug_if; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_bp_xcpt_if = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_bp_xcpt_if : _DivUnit_io_resp_bits_uop_bp_xcpt_if; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_debug_fsrc = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_debug_fsrc : _DivUnit_io_resp_bits_uop_debug_fsrc; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_debug_tsrc = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_debug_tsrc : _DivUnit_io_resp_bits_uop_debug_tsrc; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_uopc_0 = _io_iresp_bits_uop_T_uopc; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_inst_0 = _io_iresp_bits_uop_T_inst; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_debug_inst_0 = _io_iresp_bits_uop_T_debug_inst; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_is_rvc_0 = _io_iresp_bits_uop_T_is_rvc; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_debug_pc_0 = _io_iresp_bits_uop_T_debug_pc; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_iq_type_0 = _io_iresp_bits_uop_T_iq_type; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_fu_code_0 = _io_iresp_bits_uop_T_fu_code; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ctrl_br_type_0 = _io_iresp_bits_uop_T_ctrl_br_type; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ctrl_op1_sel_0 = _io_iresp_bits_uop_T_ctrl_op1_sel; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ctrl_op2_sel_0 = _io_iresp_bits_uop_T_ctrl_op2_sel; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ctrl_imm_sel_0 = _io_iresp_bits_uop_T_ctrl_imm_sel; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ctrl_op_fcn_0 = _io_iresp_bits_uop_T_ctrl_op_fcn; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ctrl_fcn_dw_0 = _io_iresp_bits_uop_T_ctrl_fcn_dw; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ctrl_is_load_0 = _io_iresp_bits_uop_T_ctrl_is_load; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ctrl_is_sta_0 = _io_iresp_bits_uop_T_ctrl_is_sta; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ctrl_is_std_0 = _io_iresp_bits_uop_T_ctrl_is_std; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_iw_state_0 = _io_iresp_bits_uop_T_iw_state; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_iw_p1_poisoned_0 = _io_iresp_bits_uop_T_iw_p1_poisoned; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_iw_p2_poisoned_0 = _io_iresp_bits_uop_T_iw_p2_poisoned; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_is_br_0 = _io_iresp_bits_uop_T_is_br; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_is_jalr_0 = _io_iresp_bits_uop_T_is_jalr; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_is_jal_0 = _io_iresp_bits_uop_T_is_jal; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_is_sfb_0 = _io_iresp_bits_uop_T_is_sfb; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_br_mask_0 = _io_iresp_bits_uop_T_br_mask; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_br_tag_0 = _io_iresp_bits_uop_T_br_tag; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ftq_idx_0 = _io_iresp_bits_uop_T_ftq_idx; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_edge_inst_0 = _io_iresp_bits_uop_T_edge_inst; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_pc_lob_0 = _io_iresp_bits_uop_T_pc_lob; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_taken_0 = _io_iresp_bits_uop_T_taken; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_imm_packed_0 = _io_iresp_bits_uop_T_imm_packed; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_rob_idx_0 = _io_iresp_bits_uop_T_rob_idx; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ldq_idx_0 = _io_iresp_bits_uop_T_ldq_idx; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_stq_idx_0 = _io_iresp_bits_uop_T_stq_idx; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_rxq_idx_0 = _io_iresp_bits_uop_T_rxq_idx; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_pdst_0 = _io_iresp_bits_uop_T_pdst; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_prs1_0 = _io_iresp_bits_uop_T_prs1; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_prs2_0 = _io_iresp_bits_uop_T_prs2; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_prs3_0 = _io_iresp_bits_uop_T_prs3; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ppred_0 = _io_iresp_bits_uop_T_ppred; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_prs1_busy_0 = _io_iresp_bits_uop_T_prs1_busy; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_prs2_busy_0 = _io_iresp_bits_uop_T_prs2_busy; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_prs3_busy_0 = _io_iresp_bits_uop_T_prs3_busy; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ppred_busy_0 = _io_iresp_bits_uop_T_ppred_busy; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_stale_pdst_0 = _io_iresp_bits_uop_T_stale_pdst; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_exception_0 = _io_iresp_bits_uop_T_exception; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_exc_cause_0 = _io_iresp_bits_uop_T_exc_cause; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_bypassable_0 = _io_iresp_bits_uop_T_bypassable; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_mem_cmd_0 = _io_iresp_bits_uop_T_mem_cmd; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_mem_size_0 = _io_iresp_bits_uop_T_mem_size; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_mem_signed_0 = _io_iresp_bits_uop_T_mem_signed; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_is_fence_0 = _io_iresp_bits_uop_T_is_fence; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_is_fencei_0 = _io_iresp_bits_uop_T_is_fencei; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_is_amo_0 = _io_iresp_bits_uop_T_is_amo; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_uses_ldq_0 = _io_iresp_bits_uop_T_uses_ldq; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_uses_stq_0 = _io_iresp_bits_uop_T_uses_stq; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_is_sys_pc2epc_0 = _io_iresp_bits_uop_T_is_sys_pc2epc; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_is_unique_0 = _io_iresp_bits_uop_T_is_unique; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_flush_on_commit_0 = _io_iresp_bits_uop_T_flush_on_commit; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ldst_is_rs1_0 = _io_iresp_bits_uop_T_ldst_is_rs1; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ldst_0 = _io_iresp_bits_uop_T_ldst; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_lrs1_0 = _io_iresp_bits_uop_T_lrs1; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_lrs2_0 = _io_iresp_bits_uop_T_lrs2; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_lrs3_0 = _io_iresp_bits_uop_T_lrs3; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ldst_val_0 = _io_iresp_bits_uop_T_ldst_val; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_dst_rtype_0 = _io_iresp_bits_uop_T_dst_rtype; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_lrs1_rtype_0 = _io_iresp_bits_uop_T_lrs1_rtype; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_lrs2_rtype_0 = _io_iresp_bits_uop_T_lrs2_rtype; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_frs3_en_0 = _io_iresp_bits_uop_T_frs3_en; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_fp_val_0 = _io_iresp_bits_uop_T_fp_val; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_fp_single_0 = _io_iresp_bits_uop_T_fp_single; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_xcpt_pf_if_0 = _io_iresp_bits_uop_T_xcpt_pf_if; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_xcpt_ae_if_0 = _io_iresp_bits_uop_T_xcpt_ae_if; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_xcpt_ma_if_0 = _io_iresp_bits_uop_T_xcpt_ma_if; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_bp_debug_if_0 = _io_iresp_bits_uop_T_bp_debug_if; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_bp_xcpt_if_0 = _io_iresp_bits_uop_T_bp_xcpt_if; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_debug_fsrc_0 = _io_iresp_bits_uop_T_debug_fsrc; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_debug_tsrc_0 = _io_iresp_bits_uop_T_debug_tsrc; // @[Mux.scala:50:70]
wire [63:0] _io_iresp_bits_data_T = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_data : _DivUnit_io_resp_bits_data; // @[Mux.scala:50:70]
assign io_iresp_bits_data_0 = {1'h0, _io_iresp_bits_data_T}; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_csr_addr_sign_T = _ALUUnit_io_resp_bits_uop_imm_packed[19]; // @[util.scala:273:18]
wire io_iresp_bits_uop_csr_addr_sign = _io_iresp_bits_uop_csr_addr_sign_T; // @[util.scala:273:{18,37}]
wire _io_iresp_bits_uop_csr_addr_i11_T_6 = io_iresp_bits_uop_csr_addr_sign; // @[util.scala:273:37, :277:21]
wire io_iresp_bits_uop_csr_addr_hi_hi_hi = io_iresp_bits_uop_csr_addr_sign; // @[util.scala:273:37, :282:15]
wire [10:0] _io_iresp_bits_uop_csr_addr_i30_20_T_1 = _ALUUnit_io_resp_bits_uop_imm_packed[18:8]; // @[util.scala:274:39]
wire [10:0] _io_iresp_bits_uop_csr_addr_i30_20_T_2 = _io_iresp_bits_uop_csr_addr_i30_20_T_1; // @[util.scala:274:{39,46}]
wire [10:0] io_iresp_bits_uop_csr_addr_i30_20 = {11{io_iresp_bits_uop_csr_addr_sign}}; // @[util.scala:273:37, :274:21]
wire [10:0] io_iresp_bits_uop_csr_addr_hi_hi_lo = io_iresp_bits_uop_csr_addr_i30_20; // @[util.scala:274:21, :282:15]
wire [7:0] _io_iresp_bits_uop_csr_addr_i19_12_T_3 = _ALUUnit_io_resp_bits_uop_imm_packed[7:0]; // @[util.scala:275:56]
wire [7:0] _io_iresp_bits_uop_csr_addr_i19_12_T_4 = _io_iresp_bits_uop_csr_addr_i19_12_T_3; // @[util.scala:275:{56,62}]
wire [7:0] io_iresp_bits_uop_csr_addr_i19_12 = {8{io_iresp_bits_uop_csr_addr_sign}}; // @[util.scala:273:37, :275:21]
wire [7:0] io_iresp_bits_uop_csr_addr_hi_lo_hi = io_iresp_bits_uop_csr_addr_i19_12; // @[util.scala:275:21, :282:15]
wire _io_iresp_bits_uop_csr_addr_i11_T_4 = _ALUUnit_io_resp_bits_uop_imm_packed[8]; // @[util.scala:277:56]
wire _io_iresp_bits_uop_csr_addr_i0_T_3 = _ALUUnit_io_resp_bits_uop_imm_packed[8]; // @[util.scala:277:56, :280:56]
wire _io_iresp_bits_uop_csr_addr_i11_T_5 = _io_iresp_bits_uop_csr_addr_i11_T_4; // @[util.scala:277:{56,60}]
wire io_iresp_bits_uop_csr_addr_i11 = _io_iresp_bits_uop_csr_addr_i11_T_6; // @[util.scala:276:21, :277:21]
wire io_iresp_bits_uop_csr_addr_hi_lo_lo = io_iresp_bits_uop_csr_addr_i11; // @[util.scala:276:21, :282:15]
wire [4:0] _io_iresp_bits_uop_csr_addr_i10_5_T_1 = _ALUUnit_io_resp_bits_uop_imm_packed[18:14]; // @[util.scala:278:44]
wire [4:0] _io_iresp_bits_uop_csr_addr_i10_5_T_2 = _io_iresp_bits_uop_csr_addr_i10_5_T_1; // @[util.scala:278:{44,52}]
wire [4:0] io_iresp_bits_uop_csr_addr_i10_5 = _io_iresp_bits_uop_csr_addr_i10_5_T_2; // @[util.scala:278:{21,52}]
wire [4:0] io_iresp_bits_uop_csr_addr_lo_hi_hi = io_iresp_bits_uop_csr_addr_i10_5; // @[util.scala:278:21, :282:15]
wire [4:0] _io_iresp_bits_uop_csr_addr_i4_1_T_1 = _ALUUnit_io_resp_bits_uop_imm_packed[13:9]; // @[util.scala:279:44]
wire [4:0] _io_iresp_bits_uop_csr_addr_i4_1_T_2 = _io_iresp_bits_uop_csr_addr_i4_1_T_1; // @[util.scala:279:{44,51}]
wire [4:0] io_iresp_bits_uop_csr_addr_i4_1 = _io_iresp_bits_uop_csr_addr_i4_1_T_2; // @[util.scala:279:{21,51}]
wire [4:0] io_iresp_bits_uop_csr_addr_lo_hi_lo = io_iresp_bits_uop_csr_addr_i4_1; // @[util.scala:279:21, :282:15]
wire _io_iresp_bits_uop_csr_addr_i0_T_4 = _io_iresp_bits_uop_csr_addr_i0_T_3; // @[util.scala:280:{56,60}]
wire io_iresp_bits_uop_csr_addr_i0 = _io_iresp_bits_uop_csr_addr_i0_T_4; // @[util.scala:280:{21,60}]
wire io_iresp_bits_uop_csr_addr_lo_lo = io_iresp_bits_uop_csr_addr_i0; // @[util.scala:280:21, :282:15]
wire [9:0] io_iresp_bits_uop_csr_addr_lo_hi = {io_iresp_bits_uop_csr_addr_lo_hi_hi, io_iresp_bits_uop_csr_addr_lo_hi_lo}; // @[util.scala:282:15]
wire [10:0] io_iresp_bits_uop_csr_addr_lo = {io_iresp_bits_uop_csr_addr_lo_hi, io_iresp_bits_uop_csr_addr_lo_lo}; // @[util.scala:282:15]
wire [8:0] io_iresp_bits_uop_csr_addr_hi_lo = {io_iresp_bits_uop_csr_addr_hi_lo_hi, io_iresp_bits_uop_csr_addr_hi_lo_lo}; // @[util.scala:282:15]
wire [11:0] io_iresp_bits_uop_csr_addr_hi_hi = {io_iresp_bits_uop_csr_addr_hi_hi_hi, io_iresp_bits_uop_csr_addr_hi_hi_lo}; // @[util.scala:282:15]
wire [20:0] io_iresp_bits_uop_csr_addr_hi = {io_iresp_bits_uop_csr_addr_hi_hi, io_iresp_bits_uop_csr_addr_hi_lo}; // @[util.scala:282:15]
wire [31:0] _io_iresp_bits_uop_csr_addr_T = {io_iresp_bits_uop_csr_addr_hi, io_iresp_bits_uop_csr_addr_lo}; // @[util.scala:282:15]
wire [31:0] _io_iresp_bits_uop_csr_addr_T_1 = _io_iresp_bits_uop_csr_addr_T; // @[util.scala:282:{15,60}]
wire [31:0] _io_iresp_bits_uop_csr_addr_T_2 = _io_iresp_bits_uop_csr_addr_T_1; // @[util.scala:282:60]
assign io_iresp_bits_uop_csr_addr_0 = _io_iresp_bits_uop_csr_addr_T_2[11:0]; // @[execution-unit.scala:204:7, :420:{34,83}] |
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_22 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, flip out_credit_available : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}[1], debug : { va_stall : UInt<2>, sa_stall : UInt<2>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}}
inst input_buffer of InputBuffer_22
connect input_buffer.clock, clock
connect input_buffer.reset, reset
connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id
connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id
connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node
connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id
connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node
connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id
connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload
connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail
connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head
connect input_buffer.io.enq[0].valid, io.in.flit[0].valid
connect input_buffer.io.deq[0].ready, UInt<1>(0h0)
connect input_buffer.io.deq[1].ready, UInt<1>(0h0)
connect input_buffer.io.deq[2].ready, UInt<1>(0h0)
inst route_arbiter of Arbiter3_RouteComputerReq_22
connect route_arbiter.clock, clock
connect route_arbiter.reset, reset
connect io.router_req.bits, route_arbiter.io.out.bits
connect io.router_req.valid, route_arbiter.io.out.valid
connect route_arbiter.io.out.ready, io.router_req.ready
reg states : { g : UInt<3>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, fifo_deps : UInt<3>}[3], clock
node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T :
node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3))
node _T_2 = asUInt(reset)
node _T_3 = eq(_T_2, UInt<1>(0h0))
when _T_3 :
node _T_4 = eq(_T_1, UInt<1>(0h0))
when _T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf
assert(clock, _T_1, UInt<1>(0h1), "") : assert
node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0))
node _T_6 = asUInt(reset)
node _T_7 = eq(_T_6, UInt<1>(0h0))
when _T_7 :
node _T_8 = eq(_T_5, UInt<1>(0h0))
when _T_8 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1
assert(clock, _T_5, UInt<1>(0h1), "") : assert_1
node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7))
node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1))
connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0)
node _T_9 = eq(UInt<1>(0h0), io.in.flit[0].bits.flow.egress_node_id)
when _T_9 :
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h1)
connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow
node _route_arbiter_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h1))
connect route_arbiter.io.in[0].valid, _route_arbiter_io_in_0_valid_T
connect route_arbiter.io.in[0].bits.flow.egress_node_id, states[0].flow.egress_node_id
connect route_arbiter.io.in[0].bits.flow.egress_node, states[0].flow.egress_node
connect route_arbiter.io.in[0].bits.flow.ingress_node_id, states[0].flow.ingress_node_id
connect route_arbiter.io.in[0].bits.flow.ingress_node, states[0].flow.ingress_node
connect route_arbiter.io.in[0].bits.flow.vnet_id, states[0].flow.vnet_id
connect route_arbiter.io.in[0].bits.src_virt_id, UInt<1>(0h0)
node _T_10 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid)
when _T_10 :
connect states[0].g, UInt<3>(0h2)
connect route_arbiter.io.in[1].valid, UInt<1>(0h0)
invalidate route_arbiter.io.in[1].bits.flow.egress_node_id
invalidate route_arbiter.io.in[1].bits.flow.egress_node
invalidate route_arbiter.io.in[1].bits.flow.ingress_node_id
invalidate route_arbiter.io.in[1].bits.flow.ingress_node
invalidate route_arbiter.io.in[1].bits.flow.vnet_id
invalidate route_arbiter.io.in[1].bits.src_virt_id
connect route_arbiter.io.in[2].valid, UInt<1>(0h0)
invalidate route_arbiter.io.in[2].bits.flow.egress_node_id
invalidate route_arbiter.io.in[2].bits.flow.egress_node
invalidate route_arbiter.io.in[2].bits.flow.ingress_node_id
invalidate route_arbiter.io.in[2].bits.flow.ingress_node
invalidate route_arbiter.io.in[2].bits.flow.vnet_id
invalidate route_arbiter.io.in[2].bits.src_virt_id
node _T_11 = and(io.router_req.ready, io.router_req.valid)
when _T_11 :
node _T_12 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1))
node _T_13 = asUInt(reset)
node _T_14 = eq(_T_13, UInt<1>(0h0))
when _T_14 :
node _T_15 = eq(_T_12, UInt<1>(0h0))
when _T_15 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2
assert(clock, _T_12, UInt<1>(0h1), "") : assert_2
connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2)
node _T_16 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id)
when _T_16 :
connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_17 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id)
when _T_17 :
connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_18 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id)
when _T_18 :
connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[2].vc_sel.`3`, io.router_resp.vc_sel.`3`
regreset mask : UInt<3>, clock, reset, UInt<3>(0h0)
wire vcalloc_reqs : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}[3]
wire vcalloc_vals : UInt<1>[3]
node vcalloc_filter_hi = cat(vcalloc_vals[2], vcalloc_vals[1])
node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_vals[0])
node vcalloc_filter_hi_1 = cat(vcalloc_vals[2], vcalloc_vals[1])
node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_vals[0])
node _vcalloc_filter_T_2 = not(mask)
node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2)
node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3)
node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0)
node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1)
node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2)
node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3)
node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4)
node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5)
node _vcalloc_filter_T_11 = mux(_vcalloc_filter_T_10, UInt<6>(0h20), UInt<6>(0h0))
node _vcalloc_filter_T_12 = mux(_vcalloc_filter_T_9, UInt<6>(0h10), _vcalloc_filter_T_11)
node _vcalloc_filter_T_13 = mux(_vcalloc_filter_T_8, UInt<6>(0h8), _vcalloc_filter_T_12)
node _vcalloc_filter_T_14 = mux(_vcalloc_filter_T_7, UInt<6>(0h4), _vcalloc_filter_T_13)
node _vcalloc_filter_T_15 = mux(_vcalloc_filter_T_6, UInt<6>(0h2), _vcalloc_filter_T_14)
node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<6>(0h1), _vcalloc_filter_T_15)
node _vcalloc_sel_T = bits(vcalloc_filter, 2, 0)
node _vcalloc_sel_T_1 = shr(vcalloc_filter, 3)
node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1)
node _T_19 = and(io.router_req.ready, io.router_req.valid)
when _T_19 :
node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id)
node _mask_T_1 = sub(_mask_T, UInt<1>(0h1))
node _mask_T_2 = tail(_mask_T_1, 1)
connect mask, _mask_T_2
else :
node _T_20 = or(vcalloc_vals[0], vcalloc_vals[1])
node _T_21 = or(_T_20, vcalloc_vals[2])
when _T_21 :
node _mask_T_3 = not(UInt<1>(0h0))
node _mask_T_4 = not(UInt<2>(0h0))
node _mask_T_5 = not(UInt<3>(0h0))
node _mask_T_6 = bits(vcalloc_sel, 0, 0)
node _mask_T_7 = bits(vcalloc_sel, 1, 1)
node _mask_T_8 = bits(vcalloc_sel, 2, 2)
node _mask_T_9 = mux(_mask_T_6, _mask_T_3, UInt<1>(0h0))
node _mask_T_10 = mux(_mask_T_7, _mask_T_4, UInt<1>(0h0))
node _mask_T_11 = mux(_mask_T_8, _mask_T_5, UInt<1>(0h0))
node _mask_T_12 = or(_mask_T_9, _mask_T_10)
node _mask_T_13 = or(_mask_T_12, _mask_T_11)
wire _mask_WIRE : UInt<3>
connect _mask_WIRE, _mask_T_13
connect mask, _mask_WIRE
node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1])
node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2])
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_1
node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0)
node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1)
node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2)
wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}
wire _io_vcalloc_req_bits_WIRE_1 : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}
wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[3]
node _io_vcalloc_req_bits_T_3 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_4 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_5 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_6 = or(_io_vcalloc_req_bits_T_3, _io_vcalloc_req_bits_T_4)
node _io_vcalloc_req_bits_T_7 = or(_io_vcalloc_req_bits_T_6, _io_vcalloc_req_bits_T_5)
wire _io_vcalloc_req_bits_WIRE_3 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_7
connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3
node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_11 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9)
node _io_vcalloc_req_bits_T_12 = or(_io_vcalloc_req_bits_T_11, _io_vcalloc_req_bits_T_10)
wire _io_vcalloc_req_bits_WIRE_4 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_12
connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4
node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_13, _io_vcalloc_req_bits_T_14)
node _io_vcalloc_req_bits_T_17 = or(_io_vcalloc_req_bits_T_16, _io_vcalloc_req_bits_T_15)
wire _io_vcalloc_req_bits_WIRE_5 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_17
connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5
connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2
wire _io_vcalloc_req_bits_WIRE_6 : UInt<1>[3]
node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_19 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_20 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_18, _io_vcalloc_req_bits_T_19)
node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_20)
wire _io_vcalloc_req_bits_WIRE_7 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_22
connect _io_vcalloc_req_bits_WIRE_6[0], _io_vcalloc_req_bits_WIRE_7
node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_26 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24)
node _io_vcalloc_req_bits_T_27 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_25)
wire _io_vcalloc_req_bits_WIRE_8 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_27
connect _io_vcalloc_req_bits_WIRE_6[1], _io_vcalloc_req_bits_WIRE_8
node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_28, _io_vcalloc_req_bits_T_29)
node _io_vcalloc_req_bits_T_32 = or(_io_vcalloc_req_bits_T_31, _io_vcalloc_req_bits_T_30)
wire _io_vcalloc_req_bits_WIRE_9 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_32
connect _io_vcalloc_req_bits_WIRE_6[2], _io_vcalloc_req_bits_WIRE_9
connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_6
wire _io_vcalloc_req_bits_WIRE_10 : UInt<1>[3]
node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_34 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_33, _io_vcalloc_req_bits_T_34)
node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_35)
wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_11, _io_vcalloc_req_bits_T_37
connect _io_vcalloc_req_bits_WIRE_10[0], _io_vcalloc_req_bits_WIRE_11
node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_41 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39)
node _io_vcalloc_req_bits_T_42 = or(_io_vcalloc_req_bits_T_41, _io_vcalloc_req_bits_T_40)
wire _io_vcalloc_req_bits_WIRE_12 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_42
connect _io_vcalloc_req_bits_WIRE_10[1], _io_vcalloc_req_bits_WIRE_12
node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_43, _io_vcalloc_req_bits_T_44)
node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_45)
wire _io_vcalloc_req_bits_WIRE_13 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_47
connect _io_vcalloc_req_bits_WIRE_10[2], _io_vcalloc_req_bits_WIRE_13
connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_10
wire _io_vcalloc_req_bits_WIRE_14 : UInt<1>[1]
node _io_vcalloc_req_bits_T_48 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_49 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_50 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_51 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_49)
node _io_vcalloc_req_bits_T_52 = or(_io_vcalloc_req_bits_T_51, _io_vcalloc_req_bits_T_50)
wire _io_vcalloc_req_bits_WIRE_15 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_52
connect _io_vcalloc_req_bits_WIRE_14[0], _io_vcalloc_req_bits_WIRE_15
connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_14
connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1
node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_56 = or(_io_vcalloc_req_bits_T_53, _io_vcalloc_req_bits_T_54)
node _io_vcalloc_req_bits_T_57 = or(_io_vcalloc_req_bits_T_56, _io_vcalloc_req_bits_T_55)
wire _io_vcalloc_req_bits_WIRE_16 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_57
connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_16
wire _io_vcalloc_req_bits_WIRE_17 : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}
node _io_vcalloc_req_bits_T_58 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_58, _io_vcalloc_req_bits_T_59)
node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_60)
wire _io_vcalloc_req_bits_WIRE_18 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_62
connect _io_vcalloc_req_bits_WIRE_17.egress_node_id, _io_vcalloc_req_bits_WIRE_18
node _io_vcalloc_req_bits_T_63 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_64 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_65 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_64)
node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_65)
wire _io_vcalloc_req_bits_WIRE_19 : UInt<4>
connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_67
connect _io_vcalloc_req_bits_WIRE_17.egress_node, _io_vcalloc_req_bits_WIRE_19
node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_71 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69)
node _io_vcalloc_req_bits_T_72 = or(_io_vcalloc_req_bits_T_71, _io_vcalloc_req_bits_T_70)
wire _io_vcalloc_req_bits_WIRE_20 : UInt<3>
connect _io_vcalloc_req_bits_WIRE_20, _io_vcalloc_req_bits_T_72
connect _io_vcalloc_req_bits_WIRE_17.ingress_node_id, _io_vcalloc_req_bits_WIRE_20
node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_73, _io_vcalloc_req_bits_T_74)
node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_76, _io_vcalloc_req_bits_T_75)
wire _io_vcalloc_req_bits_WIRE_21 : UInt<4>
connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_77
connect _io_vcalloc_req_bits_WIRE_17.ingress_node, _io_vcalloc_req_bits_WIRE_21
node _io_vcalloc_req_bits_T_78 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_79 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_80 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_79)
node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_80)
wire _io_vcalloc_req_bits_WIRE_22 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_82
connect _io_vcalloc_req_bits_WIRE_17.vnet_id, _io_vcalloc_req_bits_WIRE_22
connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_17
connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE
node _vcalloc_vals_0_T = eq(states[0].g, UInt<3>(0h2))
node _vcalloc_vals_0_T_1 = eq(states[0].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_0_T_2 = and(_vcalloc_vals_0_T, _vcalloc_vals_0_T_1)
connect vcalloc_vals[0], _vcalloc_vals_0_T_2
connect vcalloc_reqs[0].in_vc, UInt<1>(0h0)
connect vcalloc_reqs[0].vc_sel.`0`, states[0].vc_sel.`0`
connect vcalloc_reqs[0].vc_sel.`1`, states[0].vc_sel.`1`
connect vcalloc_reqs[0].vc_sel.`2`, states[0].vc_sel.`2`
connect vcalloc_reqs[0].vc_sel.`3`, states[0].vc_sel.`3`
connect vcalloc_reqs[0].flow, states[0].flow
node _T_22 = bits(vcalloc_sel, 0, 0)
node _T_23 = and(vcalloc_vals[0], _T_22)
node _T_24 = and(_T_23, io.vcalloc_req.ready)
when _T_24 :
connect states[0].g, UInt<3>(0h3)
node _T_25 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid)
when _T_25 :
connect vcalloc_vals[0], UInt<1>(0h1)
connect vcalloc_reqs[0].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect vcalloc_reqs[0].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect vcalloc_reqs[0].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect vcalloc_reqs[0].vc_sel.`3`, io.router_resp.vc_sel.`3`
connect vcalloc_vals[1], UInt<1>(0h0)
invalidate vcalloc_reqs[1].vc_sel.`0`[0]
invalidate vcalloc_reqs[1].vc_sel.`0`[1]
invalidate vcalloc_reqs[1].vc_sel.`0`[2]
invalidate vcalloc_reqs[1].vc_sel.`1`[0]
invalidate vcalloc_reqs[1].vc_sel.`1`[1]
invalidate vcalloc_reqs[1].vc_sel.`1`[2]
invalidate vcalloc_reqs[1].vc_sel.`2`[0]
invalidate vcalloc_reqs[1].vc_sel.`2`[1]
invalidate vcalloc_reqs[1].vc_sel.`2`[2]
invalidate vcalloc_reqs[1].vc_sel.`3`[0]
invalidate vcalloc_reqs[1].in_vc
invalidate vcalloc_reqs[1].flow.egress_node_id
invalidate vcalloc_reqs[1].flow.egress_node
invalidate vcalloc_reqs[1].flow.ingress_node_id
invalidate vcalloc_reqs[1].flow.ingress_node
invalidate vcalloc_reqs[1].flow.vnet_id
connect vcalloc_vals[2], UInt<1>(0h0)
invalidate vcalloc_reqs[2].vc_sel.`0`[0]
invalidate vcalloc_reqs[2].vc_sel.`0`[1]
invalidate vcalloc_reqs[2].vc_sel.`0`[2]
invalidate vcalloc_reqs[2].vc_sel.`1`[0]
invalidate vcalloc_reqs[2].vc_sel.`1`[1]
invalidate vcalloc_reqs[2].vc_sel.`1`[2]
invalidate vcalloc_reqs[2].vc_sel.`2`[0]
invalidate vcalloc_reqs[2].vc_sel.`2`[1]
invalidate vcalloc_reqs[2].vc_sel.`2`[2]
invalidate vcalloc_reqs[2].vc_sel.`3`[0]
invalidate vcalloc_reqs[2].in_vc
invalidate vcalloc_reqs[2].flow.egress_node_id
invalidate vcalloc_reqs[2].flow.egress_node
invalidate vcalloc_reqs[2].flow.ingress_node_id
invalidate vcalloc_reqs[2].flow.ingress_node
invalidate vcalloc_reqs[2].flow.vnet_id
node _io_debug_va_stall_T = add(vcalloc_vals[1], vcalloc_vals[2])
node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0)
node _io_debug_va_stall_T_2 = add(vcalloc_vals[0], _io_debug_va_stall_T_1)
node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0)
node _io_debug_va_stall_T_4 = sub(_io_debug_va_stall_T_3, io.vcalloc_req.ready)
node _io_debug_va_stall_T_5 = tail(_io_debug_va_stall_T_4, 1)
connect io.debug.va_stall, _io_debug_va_stall_T_5
node _T_26 = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
when _T_26 :
node _T_27 = bits(vcalloc_sel, 0, 0)
when _T_27 :
connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[0].g, UInt<3>(0h3)
node _T_28 = bits(vcalloc_sel, 1, 1)
when _T_28 :
connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[1].g, UInt<3>(0h3)
node _T_29 = bits(vcalloc_sel, 2, 2)
when _T_29 :
connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[2].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[2].g, UInt<3>(0h3)
inst salloc_arb of SwitchArbiter_55
connect salloc_arb.clock, clock
connect salloc_arb.reset, reset
node credit_available_hi = cat(states[0].vc_sel.`0`[2], states[0].vc_sel.`0`[1])
node _credit_available_T = cat(credit_available_hi, states[0].vc_sel.`0`[0])
node credit_available_hi_1 = cat(states[0].vc_sel.`1`[2], states[0].vc_sel.`1`[1])
node _credit_available_T_1 = cat(credit_available_hi_1, states[0].vc_sel.`1`[0])
node credit_available_hi_2 = cat(states[0].vc_sel.`2`[2], states[0].vc_sel.`2`[1])
node _credit_available_T_2 = cat(credit_available_hi_2, states[0].vc_sel.`2`[0])
node credit_available_lo = cat(_credit_available_T_1, _credit_available_T)
node credit_available_hi_3 = cat(states[0].vc_sel.`3`[0], _credit_available_T_2)
node _credit_available_T_3 = cat(credit_available_hi_3, credit_available_lo)
node credit_available_hi_4 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1])
node _credit_available_T_4 = cat(credit_available_hi_4, io.out_credit_available.`0`[0])
node credit_available_hi_5 = cat(io.out_credit_available.`1`[2], io.out_credit_available.`1`[1])
node _credit_available_T_5 = cat(credit_available_hi_5, io.out_credit_available.`1`[0])
node credit_available_hi_6 = cat(io.out_credit_available.`2`[2], io.out_credit_available.`2`[1])
node _credit_available_T_6 = cat(credit_available_hi_6, io.out_credit_available.`2`[0])
node credit_available_lo_1 = cat(_credit_available_T_5, _credit_available_T_4)
node credit_available_hi_7 = cat(io.out_credit_available.`3`[0], _credit_available_T_6)
node _credit_available_T_7 = cat(credit_available_hi_7, credit_available_lo_1)
node _credit_available_T_8 = and(_credit_available_T_3, _credit_available_T_7)
node credit_available = neq(_credit_available_T_8, UInt<1>(0h0))
node _salloc_arb_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h3))
node _salloc_arb_io_in_0_valid_T_1 = and(_salloc_arb_io_in_0_valid_T, credit_available)
node _salloc_arb_io_in_0_valid_T_2 = and(_salloc_arb_io_in_0_valid_T_1, input_buffer.io.deq[0].valid)
connect salloc_arb.io.in[0].valid, _salloc_arb_io_in_0_valid_T_2
connect salloc_arb.io.in[0].bits.vc_sel.`0`[0], states[0].vc_sel.`0`[0]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[1], states[0].vc_sel.`0`[1]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[2], states[0].vc_sel.`0`[2]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[0], states[0].vc_sel.`1`[0]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[1], states[0].vc_sel.`1`[1]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[2], states[0].vc_sel.`1`[2]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[0], states[0].vc_sel.`2`[0]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[1], states[0].vc_sel.`2`[1]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[2], states[0].vc_sel.`2`[2]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[0], states[0].vc_sel.`3`[0]
connect salloc_arb.io.in[0].bits.tail, input_buffer.io.deq[0].bits.tail
node _T_30 = and(salloc_arb.io.in[0].ready, salloc_arb.io.in[0].valid)
node _T_31 = and(_T_30, input_buffer.io.deq[0].bits.tail)
when _T_31 :
connect states[0].g, UInt<3>(0h0)
connect input_buffer.io.deq[0].ready, salloc_arb.io.in[0].ready
connect salloc_arb.io.in[1].valid, UInt<1>(0h0)
invalidate salloc_arb.io.in[1].bits.tail
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[0]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[1]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[2]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[0]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[1]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[2]
invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[0]
invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[1]
invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[2]
invalidate salloc_arb.io.in[1].bits.vc_sel.`3`[0]
connect salloc_arb.io.in[2].valid, UInt<1>(0h0)
invalidate salloc_arb.io.in[2].bits.tail
invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[0]
invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[1]
invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[2]
invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[0]
invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[1]
invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[2]
invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[0]
invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[1]
invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[2]
invalidate salloc_arb.io.in[2].bits.vc_sel.`3`[0]
node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T)
node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2)
node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4)
node _io_debug_sa_stall_T_6 = add(_io_debug_sa_stall_T_3, _io_debug_sa_stall_T_5)
node _io_debug_sa_stall_T_7 = bits(_io_debug_sa_stall_T_6, 1, 0)
node _io_debug_sa_stall_T_8 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_7)
node _io_debug_sa_stall_T_9 = bits(_io_debug_sa_stall_T_8, 1, 0)
connect io.debug.sa_stall, _io_debug_sa_stall_T_9
connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits
connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid
connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready
when io.block :
connect salloc_arb.io.out[0].ready, UInt<1>(0h0)
connect io.salloc_req[0].valid, UInt<1>(0h0)
wire salloc_outs : { valid : UInt<1>, vid : UInt<2>, out_vid : UInt<2>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1]
node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.credit_return, _io_in_credit_return_T_1
node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _io_in_vc_free_T_4 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_5 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_6 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_7 = or(_io_in_vc_free_T_4, _io_in_vc_free_T_5)
node _io_in_vc_free_T_8 = or(_io_in_vc_free_T_7, _io_in_vc_free_T_6)
wire _io_in_vc_free_WIRE : UInt<1>
connect _io_in_vc_free_WIRE, _io_in_vc_free_T_8
node _io_in_vc_free_T_9 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE)
node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_9, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.vc_free, _io_in_vc_free_T_10
node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
connect salloc_outs[0].valid, _salloc_outs_0_valid_T
node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 1, 0)
node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi)
node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo)
node _salloc_outs_0_vid_T_2 = bits(_salloc_outs_0_vid_T_1, 1, 1)
node _salloc_outs_0_vid_T_3 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_2)
connect salloc_outs[0].vid, _salloc_outs_0_vid_T_3
node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
wire vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}
wire _vc_sel_WIRE : UInt<1>[3]
node _vc_sel_T_3 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_4 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_5 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_6 = or(_vc_sel_T_3, _vc_sel_T_4)
node _vc_sel_T_7 = or(_vc_sel_T_6, _vc_sel_T_5)
wire _vc_sel_WIRE_1 : UInt<1>
connect _vc_sel_WIRE_1, _vc_sel_T_7
connect _vc_sel_WIRE[0], _vc_sel_WIRE_1
node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_10 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_11 = or(_vc_sel_T_8, _vc_sel_T_9)
node _vc_sel_T_12 = or(_vc_sel_T_11, _vc_sel_T_10)
wire _vc_sel_WIRE_2 : UInt<1>
connect _vc_sel_WIRE_2, _vc_sel_T_12
connect _vc_sel_WIRE[1], _vc_sel_WIRE_2
node _vc_sel_T_13 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_14 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_15 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_16 = or(_vc_sel_T_13, _vc_sel_T_14)
node _vc_sel_T_17 = or(_vc_sel_T_16, _vc_sel_T_15)
wire _vc_sel_WIRE_3 : UInt<1>
connect _vc_sel_WIRE_3, _vc_sel_T_17
connect _vc_sel_WIRE[2], _vc_sel_WIRE_3
connect vc_sel.`0`, _vc_sel_WIRE
wire _vc_sel_WIRE_4 : UInt<1>[3]
node _vc_sel_T_18 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_19 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_20 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_21 = or(_vc_sel_T_18, _vc_sel_T_19)
node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_20)
wire _vc_sel_WIRE_5 : UInt<1>
connect _vc_sel_WIRE_5, _vc_sel_T_22
connect _vc_sel_WIRE_4[0], _vc_sel_WIRE_5
node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_26 = or(_vc_sel_T_23, _vc_sel_T_24)
node _vc_sel_T_27 = or(_vc_sel_T_26, _vc_sel_T_25)
wire _vc_sel_WIRE_6 : UInt<1>
connect _vc_sel_WIRE_6, _vc_sel_T_27
connect _vc_sel_WIRE_4[1], _vc_sel_WIRE_6
node _vc_sel_T_28 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_29 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_30 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_31 = or(_vc_sel_T_28, _vc_sel_T_29)
node _vc_sel_T_32 = or(_vc_sel_T_31, _vc_sel_T_30)
wire _vc_sel_WIRE_7 : UInt<1>
connect _vc_sel_WIRE_7, _vc_sel_T_32
connect _vc_sel_WIRE_4[2], _vc_sel_WIRE_7
connect vc_sel.`1`, _vc_sel_WIRE_4
wire _vc_sel_WIRE_8 : UInt<1>[3]
node _vc_sel_T_33 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_34 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_35 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_36 = or(_vc_sel_T_33, _vc_sel_T_34)
node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_35)
wire _vc_sel_WIRE_9 : UInt<1>
connect _vc_sel_WIRE_9, _vc_sel_T_37
connect _vc_sel_WIRE_8[0], _vc_sel_WIRE_9
node _vc_sel_T_38 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_39 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_40 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_41 = or(_vc_sel_T_38, _vc_sel_T_39)
node _vc_sel_T_42 = or(_vc_sel_T_41, _vc_sel_T_40)
wire _vc_sel_WIRE_10 : UInt<1>
connect _vc_sel_WIRE_10, _vc_sel_T_42
connect _vc_sel_WIRE_8[1], _vc_sel_WIRE_10
node _vc_sel_T_43 = mux(_vc_sel_T, states[0].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_44 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_45 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_46 = or(_vc_sel_T_43, _vc_sel_T_44)
node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_45)
wire _vc_sel_WIRE_11 : UInt<1>
connect _vc_sel_WIRE_11, _vc_sel_T_47
connect _vc_sel_WIRE_8[2], _vc_sel_WIRE_11
connect vc_sel.`2`, _vc_sel_WIRE_8
wire _vc_sel_WIRE_12 : UInt<1>[1]
node _vc_sel_T_48 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_49 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_50 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_51 = or(_vc_sel_T_48, _vc_sel_T_49)
node _vc_sel_T_52 = or(_vc_sel_T_51, _vc_sel_T_50)
wire _vc_sel_WIRE_13 : UInt<1>
connect _vc_sel_WIRE_13, _vc_sel_T_52
connect _vc_sel_WIRE_12[0], _vc_sel_WIRE_13
connect vc_sel.`3`, _vc_sel_WIRE_12
node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1])
node channel_oh_0 = or(_channel_oh_T, vc_sel.`0`[2])
node _channel_oh_T_1 = or(vc_sel.`1`[0], vc_sel.`1`[1])
node channel_oh_1 = or(_channel_oh_T_1, vc_sel.`1`[2])
node _channel_oh_T_2 = or(vc_sel.`2`[0], vc_sel.`2`[1])
node channel_oh_2 = or(_channel_oh_T_2, vc_sel.`2`[2])
node virt_channel_hi = cat(vc_sel.`0`[2], vc_sel.`0`[1])
node _virt_channel_T = cat(virt_channel_hi, vc_sel.`0`[0])
node virt_channel_hi_1 = bits(_virt_channel_T, 2, 2)
node virt_channel_lo = bits(_virt_channel_T, 1, 0)
node _virt_channel_T_1 = orr(virt_channel_hi_1)
node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo)
node _virt_channel_T_3 = bits(_virt_channel_T_2, 1, 1)
node _virt_channel_T_4 = cat(_virt_channel_T_1, _virt_channel_T_3)
node virt_channel_hi_2 = cat(vc_sel.`1`[2], vc_sel.`1`[1])
node _virt_channel_T_5 = cat(virt_channel_hi_2, vc_sel.`1`[0])
node virt_channel_hi_3 = bits(_virt_channel_T_5, 2, 2)
node virt_channel_lo_1 = bits(_virt_channel_T_5, 1, 0)
node _virt_channel_T_6 = orr(virt_channel_hi_3)
node _virt_channel_T_7 = or(virt_channel_hi_3, virt_channel_lo_1)
node _virt_channel_T_8 = bits(_virt_channel_T_7, 1, 1)
node _virt_channel_T_9 = cat(_virt_channel_T_6, _virt_channel_T_8)
node virt_channel_hi_4 = cat(vc_sel.`2`[2], vc_sel.`2`[1])
node _virt_channel_T_10 = cat(virt_channel_hi_4, vc_sel.`2`[0])
node virt_channel_hi_5 = bits(_virt_channel_T_10, 2, 2)
node virt_channel_lo_2 = bits(_virt_channel_T_10, 1, 0)
node _virt_channel_T_11 = orr(virt_channel_hi_5)
node _virt_channel_T_12 = or(virt_channel_hi_5, virt_channel_lo_2)
node _virt_channel_T_13 = bits(_virt_channel_T_12, 1, 1)
node _virt_channel_T_14 = cat(_virt_channel_T_11, _virt_channel_T_13)
node _virt_channel_T_15 = mux(channel_oh_0, _virt_channel_T_4, UInt<1>(0h0))
node _virt_channel_T_16 = mux(channel_oh_1, _virt_channel_T_9, UInt<1>(0h0))
node _virt_channel_T_17 = mux(channel_oh_2, _virt_channel_T_14, UInt<1>(0h0))
node _virt_channel_T_18 = mux(vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0))
node _virt_channel_T_19 = or(_virt_channel_T_15, _virt_channel_T_16)
node _virt_channel_T_20 = or(_virt_channel_T_19, _virt_channel_T_17)
node _virt_channel_T_21 = or(_virt_channel_T_20, _virt_channel_T_18)
wire virt_channel : UInt<2>
connect virt_channel, _virt_channel_T_21
node _T_32 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
when _T_32 :
connect salloc_outs[0].out_vid, virt_channel
node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_payload_T_3 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_4 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_5 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_6 = or(_salloc_outs_0_flit_payload_T_3, _salloc_outs_0_flit_payload_T_4)
node _salloc_outs_0_flit_payload_T_7 = or(_salloc_outs_0_flit_payload_T_6, _salloc_outs_0_flit_payload_T_5)
wire _salloc_outs_0_flit_payload_WIRE : UInt<145>
connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_7
connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE
node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_head_T_3 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_4 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_5 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_6 = or(_salloc_outs_0_flit_head_T_3, _salloc_outs_0_flit_head_T_4)
node _salloc_outs_0_flit_head_T_7 = or(_salloc_outs_0_flit_head_T_6, _salloc_outs_0_flit_head_T_5)
wire _salloc_outs_0_flit_head_WIRE : UInt<1>
connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_7
connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE
node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_tail_T_3 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_4 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_5 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_6 = or(_salloc_outs_0_flit_tail_T_3, _salloc_outs_0_flit_tail_T_4)
node _salloc_outs_0_flit_tail_T_7 = or(_salloc_outs_0_flit_tail_T_6, _salloc_outs_0_flit_tail_T_5)
wire _salloc_outs_0_flit_tail_WIRE : UInt<1>
connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_7
connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE
node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}
node _salloc_outs_0_flit_flow_T_3 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_4 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_5 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_6 = or(_salloc_outs_0_flit_flow_T_3, _salloc_outs_0_flit_flow_T_4)
node _salloc_outs_0_flit_flow_T_7 = or(_salloc_outs_0_flit_flow_T_6, _salloc_outs_0_flit_flow_T_5)
wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_7
connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1
node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_11 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9)
node _salloc_outs_0_flit_flow_T_12 = or(_salloc_outs_0_flit_flow_T_11, _salloc_outs_0_flit_flow_T_10)
wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4>
connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_12
connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2
node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_13, _salloc_outs_0_flit_flow_T_14)
node _salloc_outs_0_flit_flow_T_17 = or(_salloc_outs_0_flit_flow_T_16, _salloc_outs_0_flit_flow_T_15)
wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<3>
connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_17
connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3
node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_19 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_20 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_18, _salloc_outs_0_flit_flow_T_19)
node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_20)
wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4>
connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_22
connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4
node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_26 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24)
node _salloc_outs_0_flit_flow_T_27 = or(_salloc_outs_0_flit_flow_T_26, _salloc_outs_0_flit_flow_T_25)
wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_27
connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5
connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE
else :
invalidate salloc_outs[0].out_vid
invalidate salloc_outs[0].flit.virt_channel_id
invalidate salloc_outs[0].flit.flow.egress_node_id
invalidate salloc_outs[0].flit.flow.egress_node
invalidate salloc_outs[0].flit.flow.ingress_node_id
invalidate salloc_outs[0].flit.flow.ingress_node
invalidate salloc_outs[0].flit.flow.vnet_id
invalidate salloc_outs[0].flit.payload
invalidate salloc_outs[0].flit.tail
invalidate salloc_outs[0].flit.head
invalidate salloc_outs[0].flit.virt_channel_id
connect io.out[0].valid, salloc_outs[0].valid
connect io.out[0].bits.flit, salloc_outs[0].flit
connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid
connect states[0].vc_sel.`0`[1], UInt<1>(0h0)
connect states[0].vc_sel.`0`[2], UInt<1>(0h0)
connect states[0].vc_sel.`1`[0], UInt<1>(0h0)
connect states[0].vc_sel.`1`[1], UInt<1>(0h0)
connect states[0].vc_sel.`1`[2], UInt<1>(0h0)
connect states[0].vc_sel.`2`[1], UInt<1>(0h0)
connect states[0].vc_sel.`2`[2], UInt<1>(0h0)
invalidate states[1].fifo_deps
invalidate states[1].flow.egress_node_id
invalidate states[1].flow.egress_node
invalidate states[1].flow.ingress_node_id
invalidate states[1].flow.ingress_node
invalidate states[1].flow.vnet_id
invalidate states[1].vc_sel.`0`[0]
invalidate states[1].vc_sel.`0`[1]
invalidate states[1].vc_sel.`0`[2]
invalidate states[1].vc_sel.`1`[0]
invalidate states[1].vc_sel.`1`[1]
invalidate states[1].vc_sel.`1`[2]
invalidate states[1].vc_sel.`2`[0]
invalidate states[1].vc_sel.`2`[1]
invalidate states[1].vc_sel.`2`[2]
invalidate states[1].vc_sel.`3`[0]
invalidate states[1].g
invalidate states[2].fifo_deps
invalidate states[2].flow.egress_node_id
invalidate states[2].flow.egress_node
invalidate states[2].flow.ingress_node_id
invalidate states[2].flow.ingress_node
invalidate states[2].flow.vnet_id
invalidate states[2].vc_sel.`0`[0]
invalidate states[2].vc_sel.`0`[1]
invalidate states[2].vc_sel.`0`[2]
invalidate states[2].vc_sel.`1`[0]
invalidate states[2].vc_sel.`1`[1]
invalidate states[2].vc_sel.`1`[2]
invalidate states[2].vc_sel.`2`[0]
invalidate states[2].vc_sel.`2`[1]
invalidate states[2].vc_sel.`2`[2]
invalidate states[2].vc_sel.`3`[0]
invalidate states[2].g
node _T_33 = asUInt(reset)
when _T_33 :
connect states[0].g, UInt<3>(0h0)
connect states[1].g, UInt<3>(0h0)
connect states[2].g, UInt<3>(0h0) | module InputUnit_22( // @[InputUnit.scala:158:7]
input clock, // @[InputUnit.scala:158:7]
input reset, // @[InputUnit.scala:158:7]
output [1:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
output [2:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_2, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_2, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14]
input io_vcalloc_req_ready, // @[InputUnit.scala:170:14]
output io_vcalloc_req_valid, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_2, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_2, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_0, // @[InputUnit.scala:170:14]
input io_salloc_req_0_ready, // @[InputUnit.scala:170:14]
output io_salloc_req_0_valid, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14]
output io_out_0_valid, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14]
output [144:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14]
output [1:0] io_debug_va_stall, // @[InputUnit.scala:170:14]
output [1:0] io_debug_sa_stall, // @[InputUnit.scala:170:14]
input io_in_flit_0_valid, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14]
input [144:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14]
output [2:0] io_in_credit_return, // @[InputUnit.scala:170:14]
output [2:0] io_in_vc_free // @[InputUnit.scala:170:14]
);
wire _GEN; // @[MixedVec.scala:116:9]
wire vcalloc_reqs_0_vc_sel_2_0; // @[MixedVec.scala:116:9]
wire vcalloc_reqs_0_vc_sel_0_0; // @[MixedVec.scala:116:9]
wire vcalloc_vals_0; // @[InputUnit.scala:266:25, :272:46, :273:29]
wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26]
wire [2:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26]
wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29]
wire [1:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29]
wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28]
wire [144:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28]
wire [144:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28]
wire [144:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28]
reg [2:0] states_0_g; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_3_0; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_0_0; // @[InputUnit.scala:192:19]
reg [1:0] states_0_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [2:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19]
wire _GEN_0 = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30]
wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_183 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_193
connect io_out_source_valid.clock, clock
connect io_out_source_valid.reset, reset
connect io_out_source_valid.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_valid.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_183( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_193 io_out_source_valid ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetRegVec_w1_i0_6 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>}
node _reg_T = asAsyncReset(reset)
regreset reg : UInt<1>, clock, _reg_T, UInt<1>(0h0)
when io.en :
connect reg, io.d
connect io.q, reg | module AsyncResetRegVec_w1_i0_6( // @[AsyncResetReg.scala:56:7]
input clock, // @[AsyncResetReg.scala:56:7]
input reset // @[AsyncResetReg.scala:56:7]
);
wire _reg_T = reset; // @[AsyncResetReg.scala:61:29]
wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14]
wire io_d = 1'h0; // @[AsyncResetReg.scala:56:7]
wire io_q = 1'h0; // @[AsyncResetReg.scala:56:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d64s2k3z4c_3 :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate nodeIn.e.bits.sink
invalidate nodeIn.e.valid
invalidate nodeIn.e.ready
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.c.bits.corrupt
invalidate nodeIn.c.bits.data
invalidate nodeIn.c.bits.address
invalidate nodeIn.c.bits.source
invalidate nodeIn.c.bits.size
invalidate nodeIn.c.bits.param
invalidate nodeIn.c.bits.opcode
invalidate nodeIn.c.valid
invalidate nodeIn.c.ready
invalidate nodeIn.b.bits.corrupt
invalidate nodeIn.b.bits.data
invalidate nodeIn.b.bits.mask
invalidate nodeIn.b.bits.address
invalidate nodeIn.b.bits.source
invalidate nodeIn.b.bits.size
invalidate nodeIn.b.bits.param
invalidate nodeIn.b.bits.opcode
invalidate nodeIn.b.valid
invalidate nodeIn.b.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_48
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.e.bits.sink, nodeIn.e.bits.sink
connect monitor.io.in.e.valid, nodeIn.e.valid
connect monitor.io.in.e.ready, nodeIn.e.ready
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.c.bits.corrupt, nodeIn.c.bits.corrupt
connect monitor.io.in.c.bits.data, nodeIn.c.bits.data
connect monitor.io.in.c.bits.address, nodeIn.c.bits.address
connect monitor.io.in.c.bits.source, nodeIn.c.bits.source
connect monitor.io.in.c.bits.size, nodeIn.c.bits.size
connect monitor.io.in.c.bits.param, nodeIn.c.bits.param
connect monitor.io.in.c.bits.opcode, nodeIn.c.bits.opcode
connect monitor.io.in.c.valid, nodeIn.c.valid
connect monitor.io.in.c.ready, nodeIn.c.ready
connect monitor.io.in.b.bits.corrupt, nodeIn.b.bits.corrupt
connect monitor.io.in.b.bits.data, nodeIn.b.bits.data
connect monitor.io.in.b.bits.mask, nodeIn.b.bits.mask
connect monitor.io.in.b.bits.address, nodeIn.b.bits.address
connect monitor.io.in.b.bits.source, nodeIn.b.bits.source
connect monitor.io.in.b.bits.size, nodeIn.b.bits.size
connect monitor.io.in.b.bits.param, nodeIn.b.bits.param
connect monitor.io.in.b.bits.opcode, nodeIn.b.bits.opcode
connect monitor.io.in.b.valid, nodeIn.b.valid
connect monitor.io.in.b.ready, nodeIn.b.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate nodeOut.e.bits.sink
invalidate nodeOut.e.valid
invalidate nodeOut.e.ready
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.c.bits.corrupt
invalidate nodeOut.c.bits.data
invalidate nodeOut.c.bits.address
invalidate nodeOut.c.bits.source
invalidate nodeOut.c.bits.size
invalidate nodeOut.c.bits.param
invalidate nodeOut.c.bits.opcode
invalidate nodeOut.c.valid
invalidate nodeOut.c.ready
invalidate nodeOut.b.bits.corrupt
invalidate nodeOut.b.bits.data
invalidate nodeOut.b.bits.mask
invalidate nodeOut.b.bits.address
invalidate nodeOut.b.bits.source
invalidate nodeOut.b.bits.size
invalidate nodeOut.b.bits.param
invalidate nodeOut.b.bits.opcode
invalidate nodeOut.b.valid
invalidate nodeOut.b.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
inst nodeOut_a_q of Queue2_TLBundleA_a32d64s2k3z4c_1
connect nodeOut_a_q.clock, clock
connect nodeOut_a_q.reset, reset
connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid
connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt
connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data
connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask
connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address
connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source
connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size
connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param
connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode
connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready
connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits
connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid
connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready
inst nodeIn_d_q of Queue2_TLBundleD_a32d64s2k3z4c_1
connect nodeIn_d_q.clock, clock
connect nodeIn_d_q.reset, reset
connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid
connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt
connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data
connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied
connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink
connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source
connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size
connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param
connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode
connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready
connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits
connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid
connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready
inst nodeIn_b_q of Queue2_TLBundleB_a32d64s2k3z4c_1
connect nodeIn_b_q.clock, clock
connect nodeIn_b_q.reset, reset
connect nodeIn_b_q.io.enq.valid, nodeOut.b.valid
connect nodeIn_b_q.io.enq.bits.corrupt, nodeOut.b.bits.corrupt
connect nodeIn_b_q.io.enq.bits.data, nodeOut.b.bits.data
connect nodeIn_b_q.io.enq.bits.mask, nodeOut.b.bits.mask
connect nodeIn_b_q.io.enq.bits.address, nodeOut.b.bits.address
connect nodeIn_b_q.io.enq.bits.source, nodeOut.b.bits.source
connect nodeIn_b_q.io.enq.bits.size, nodeOut.b.bits.size
connect nodeIn_b_q.io.enq.bits.param, nodeOut.b.bits.param
connect nodeIn_b_q.io.enq.bits.opcode, nodeOut.b.bits.opcode
connect nodeOut.b.ready, nodeIn_b_q.io.enq.ready
connect nodeIn.b.bits, nodeIn_b_q.io.deq.bits
connect nodeIn.b.valid, nodeIn_b_q.io.deq.valid
connect nodeIn_b_q.io.deq.ready, nodeIn.b.ready
inst nodeOut_c_q of Queue2_TLBundleC_a32d64s2k3z4c_1
connect nodeOut_c_q.clock, clock
connect nodeOut_c_q.reset, reset
connect nodeOut_c_q.io.enq.valid, nodeIn.c.valid
connect nodeOut_c_q.io.enq.bits.corrupt, nodeIn.c.bits.corrupt
connect nodeOut_c_q.io.enq.bits.data, nodeIn.c.bits.data
connect nodeOut_c_q.io.enq.bits.address, nodeIn.c.bits.address
connect nodeOut_c_q.io.enq.bits.source, nodeIn.c.bits.source
connect nodeOut_c_q.io.enq.bits.size, nodeIn.c.bits.size
connect nodeOut_c_q.io.enq.bits.param, nodeIn.c.bits.param
connect nodeOut_c_q.io.enq.bits.opcode, nodeIn.c.bits.opcode
connect nodeIn.c.ready, nodeOut_c_q.io.enq.ready
connect nodeOut.c.bits, nodeOut_c_q.io.deq.bits
connect nodeOut.c.valid, nodeOut_c_q.io.deq.valid
connect nodeOut_c_q.io.deq.ready, nodeOut.c.ready
inst nodeOut_e_q of Queue2_TLBundleE_a32d64s2k3z4c_1
connect nodeOut_e_q.clock, clock
connect nodeOut_e_q.reset, reset
connect nodeOut_e_q.io.enq.valid, nodeIn.e.valid
connect nodeOut_e_q.io.enq.bits.sink, nodeIn.e.bits.sink
connect nodeIn.e.ready, nodeOut_e_q.io.enq.ready
connect nodeOut.e.bits, nodeOut_e_q.io.deq.bits
connect nodeOut.e.valid, nodeOut_e_q.io.deq.valid
connect nodeOut_e_q.io.deq.ready, nodeOut.e.ready | module TLBuffer_a32d64s2k3z4c_3( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_b_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_in_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_b_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_b_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_out_b_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_b_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_e_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [1:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire auto_in_b_ready_0 = auto_in_b_ready; // @[Buffer.scala:40:9]
wire auto_in_c_valid_0 = auto_in_c_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[Buffer.scala:40:9]
wire [1:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[Buffer.scala:40:9]
wire [63:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[Buffer.scala:40:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9]
wire auto_in_e_valid_0 = auto_in_e_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9]
wire auto_out_b_valid_0 = auto_out_b_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_b_bits_opcode_0 = auto_out_b_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_out_b_bits_size_0 = auto_out_b_bits_size; // @[Buffer.scala:40:9]
wire [1:0] auto_out_b_bits_source_0 = auto_out_b_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[Buffer.scala:40:9]
wire [7:0] auto_out_b_bits_mask_0 = auto_out_b_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] auto_out_b_bits_data_0 = auto_out_b_bits_data; // @[Buffer.scala:40:9]
wire auto_out_b_bits_corrupt_0 = auto_out_b_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_out_c_ready_0 = auto_out_c_ready; // @[Buffer.scala:40:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [1:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_out_e_ready_0 = auto_out_e_ready; // @[Buffer.scala:40:9]
wire auto_in_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire auto_in_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire nodeIn_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_b_ready = auto_in_b_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_b_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_b_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17]
wire [7:0] nodeIn_b_bits_mask; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_b_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_c_ready; // @[MixedNode.scala:551:17]
wire nodeIn_c_valid = auto_in_c_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_e_ready; // @[MixedNode.scala:551:17]
wire nodeIn_e_valid = auto_in_e_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_b_ready; // @[MixedNode.scala:542:17]
wire nodeOut_b_valid = auto_out_b_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_b_bits_opcode = auto_out_b_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_b_bits_size = auto_out_b_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_b_bits_source = auto_out_b_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] nodeOut_b_bits_mask = auto_out_b_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] nodeOut_b_bits_data = auto_out_b_bits_data_0; // @[Buffer.scala:40:9]
wire nodeOut_b_bits_corrupt = auto_out_b_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeOut_c_ready = auto_out_c_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeOut_e_ready = auto_out_e_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire auto_in_a_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_b_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_b_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_b_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_in_b_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_in_b_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_b_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_b_valid_0; // @[Buffer.scala:40:9]
wire auto_in_c_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_d_valid_0; // @[Buffer.scala:40:9]
wire auto_in_e_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_a_valid_0; // @[Buffer.scala:40:9]
wire auto_out_b_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_c_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_c_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] auto_out_c_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_out_c_bits_address_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_c_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_c_valid_0; // @[Buffer.scala:40:9]
wire auto_out_d_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_e_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_out_e_valid_0; // @[Buffer.scala:40:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9]
assign auto_in_b_valid_0 = nodeIn_b_valid; // @[Buffer.scala:40:9]
assign auto_in_b_bits_opcode_0 = nodeIn_b_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[Buffer.scala:40:9]
assign auto_in_b_bits_size_0 = nodeIn_b_bits_size; // @[Buffer.scala:40:9]
assign auto_in_b_bits_source_0 = nodeIn_b_bits_source; // @[Buffer.scala:40:9]
assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[Buffer.scala:40:9]
assign auto_in_b_bits_mask_0 = nodeIn_b_bits_mask; // @[Buffer.scala:40:9]
assign auto_in_b_bits_data_0 = nodeIn_b_bits_data; // @[Buffer.scala:40:9]
assign auto_in_b_bits_corrupt_0 = nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_in_c_ready_0 = nodeIn_c_ready; // @[Buffer.scala:40:9]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_in_e_ready_0 = nodeIn_e_ready; // @[Buffer.scala:40:9]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_b_ready_0 = nodeOut_b_ready; // @[Buffer.scala:40:9]
assign auto_out_c_valid_0 = nodeOut_c_valid; // @[Buffer.scala:40:9]
assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[Buffer.scala:40:9]
assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[Buffer.scala:40:9]
assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[Buffer.scala:40:9]
assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[Buffer.scala:40:9]
assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[Buffer.scala:40:9]
assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9]
assign auto_out_e_valid_0 = nodeOut_e_valid; // @[Buffer.scala:40:9]
assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[Buffer.scala:40:9]
TLMonitor_48 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17]
.io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17]
.io_in_b_bits_opcode (nodeIn_b_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17]
.io_in_b_bits_size (nodeIn_b_bits_size), // @[MixedNode.scala:551:17]
.io_in_b_bits_source (nodeIn_b_bits_source), // @[MixedNode.scala:551:17]
.io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17]
.io_in_b_bits_mask (nodeIn_b_bits_mask), // @[MixedNode.scala:551:17]
.io_in_b_bits_data (nodeIn_b_bits_data), // @[MixedNode.scala:551:17]
.io_in_b_bits_corrupt (nodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17]
.io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17]
.io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17]
.io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17]
.io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17]
.io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17]
.io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_e_ready (nodeIn_e_ready), // @[MixedNode.scala:551:17]
.io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17]
.io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a32d64s2k3z4c_1 nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_a_valid),
.io_deq_bits_opcode (nodeOut_a_bits_opcode),
.io_deq_bits_param (nodeOut_a_bits_param),
.io_deq_bits_size (nodeOut_a_bits_size),
.io_deq_bits_source (nodeOut_a_bits_source),
.io_deq_bits_address (nodeOut_a_bits_address),
.io_deq_bits_mask (nodeOut_a_bits_mask),
.io_deq_bits_data (nodeOut_a_bits_data),
.io_deq_bits_corrupt (nodeOut_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a32d64s2k3z4c_1 nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_d_ready),
.io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17]
.io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_d_valid),
.io_deq_bits_opcode (nodeIn_d_bits_opcode),
.io_deq_bits_param (nodeIn_d_bits_param),
.io_deq_bits_size (nodeIn_d_bits_size),
.io_deq_bits_source (nodeIn_d_bits_source),
.io_deq_bits_sink (nodeIn_d_bits_sink),
.io_deq_bits_denied (nodeIn_d_bits_denied),
.io_deq_bits_data (nodeIn_d_bits_data),
.io_deq_bits_corrupt (nodeIn_d_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleB_a32d64s2k3z4c_1 nodeIn_b_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_b_ready),
.io_enq_valid (nodeOut_b_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_b_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_b_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_b_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_b_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_address (nodeOut_b_bits_address), // @[MixedNode.scala:542:17]
.io_enq_bits_mask (nodeOut_b_bits_mask), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_b_bits_data), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (nodeOut_b_bits_corrupt), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_b_valid),
.io_deq_bits_opcode (nodeIn_b_bits_opcode),
.io_deq_bits_param (nodeIn_b_bits_param),
.io_deq_bits_size (nodeIn_b_bits_size),
.io_deq_bits_source (nodeIn_b_bits_source),
.io_deq_bits_address (nodeIn_b_bits_address),
.io_deq_bits_mask (nodeIn_b_bits_mask),
.io_deq_bits_data (nodeIn_b_bits_data),
.io_deq_bits_corrupt (nodeIn_b_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleC_a32d64s2k3z4c_1 nodeOut_c_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_c_ready),
.io_enq_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_c_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_c_valid),
.io_deq_bits_opcode (nodeOut_c_bits_opcode),
.io_deq_bits_param (nodeOut_c_bits_param),
.io_deq_bits_size (nodeOut_c_bits_size),
.io_deq_bits_source (nodeOut_c_bits_source),
.io_deq_bits_address (nodeOut_c_bits_address),
.io_deq_bits_data (nodeOut_c_bits_data),
.io_deq_bits_corrupt (nodeOut_c_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleE_a32d64s2k3z4c_1 nodeOut_e_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_e_ready),
.io_enq_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_sink (nodeIn_e_bits_sink), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_e_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_e_valid),
.io_deq_bits_sink (nodeOut_e_bits_sink)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9]
assign auto_in_b_valid = auto_in_b_valid_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_opcode = auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_size = auto_in_b_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_source = auto_in_b_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_mask = auto_in_b_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_data = auto_in_b_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_corrupt = auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_in_c_ready = auto_in_c_ready_0; // @[Buffer.scala:40:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_in_e_ready = auto_in_e_ready_0; // @[Buffer.scala:40:9]
assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_b_ready = auto_out_b_ready_0; // @[Buffer.scala:40:9]
assign auto_out_c_valid = auto_out_c_valid_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9]
assign auto_out_e_valid = auto_out_e_valid_0; // @[Buffer.scala:40:9]
assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[Buffer.scala:40:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module L1MetadataArrayBank_2 :
input clock : Clock
input reset : Reset
output io : { flip read : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<4>, tag : UInt<20>}}, flip write : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<4>, tag : UInt<20>, data : { coh : { state : UInt<2>}, tag : UInt<20>}}}, resp : { coh : { state : UInt<2>}, tag : UInt<20>}[4]}
wire rstVal_meta : { state : UInt<2>}
connect rstVal_meta.state, UInt<2>(0h0)
wire rstVal : { coh : { state : UInt<2>}, tag : UInt<20>}
connect rstVal.tag, UInt<1>(0h0)
connect rstVal.coh, rstVal_meta
regreset rst_cnt : UInt<5>, clock, reset, UInt<5>(0h0)
node rst = lt(rst_cnt, UInt<5>(0h10))
node waddr = mux(rst, rst_cnt, io.write.bits.idx)
node _wdata_T = mux(rst, rstVal, io.write.bits.data)
node wdata = cat(_wdata_T.coh.state, _wdata_T.tag)
node _wmask_T = or(rst, UInt<1>(0h0))
node _wmask_T_1 = not(UInt<4>(0h0))
node _wmask_T_2 = mux(_wmask_T, _wmask_T_1, io.write.bits.way_en)
node wmask_0 = bits(_wmask_T_2, 0, 0)
node wmask_1 = bits(_wmask_T_2, 1, 1)
node wmask_2 = bits(_wmask_T_2, 2, 2)
node wmask_3 = bits(_wmask_T_2, 3, 3)
node _rmask_T = or(rst, UInt<1>(0h0))
node _rmask_T_1 = not(UInt<4>(0h0))
node _rmask_T_2 = mux(_rmask_T, _rmask_T_1, io.read.bits.way_en)
node rmask_0 = bits(_rmask_T_2, 0, 0)
node rmask_1 = bits(_rmask_T_2, 1, 1)
node rmask_2 = bits(_rmask_T_2, 2, 2)
node rmask_3 = bits(_rmask_T_2, 3, 3)
when rst :
node _rst_cnt_T = add(rst_cnt, UInt<1>(0h1))
node _rst_cnt_T_1 = tail(_rst_cnt_T, 1)
connect rst_cnt, _rst_cnt_T_1
smem tag_array : UInt<22>[4] [16]
wire wen : UInt<1>
wire ren : UInt<1>
regreset stall_ctr : UInt<2>, clock, reset, UInt<2>(0h0)
node _stall_read_T = not(UInt<2>(0h0))
node stall_read = eq(stall_ctr, _stall_read_T)
wire force_stall : UInt<1>
connect force_stall, UInt<1>(0h0)
regreset rbuf_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg rbuf_idx : UInt<4>, clock
reg rbuf : { coh : { state : UInt<2>}, tag : UInt<20>}[4], clock
wire forward_from_rbuf : UInt<1>
connect forward_from_rbuf, UInt<1>(0h0)
node _T = and(io.read.valid, force_stall)
when _T :
node _stall_ctr_T = add(stall_ctr, UInt<1>(0h1))
node _stall_ctr_T_1 = tail(_stall_ctr_T, 1)
connect stall_ctr, _stall_ctr_T_1
else :
connect stall_ctr, UInt<1>(0h0)
when rst :
connect wen, UInt<1>(0h1)
connect ren, UInt<1>(0h0)
connect io.read.ready, UInt<1>(0h0)
connect io.write.ready, UInt<1>(0h0)
else :
node _T_1 = eq(stall_read, UInt<1>(0h0))
node _T_2 = and(io.read.valid, _T_1)
when _T_2 :
node _T_3 = eq(io.read.bits.idx, rbuf_idx)
node _T_4 = and(_T_3, rbuf_valid)
when _T_4 :
connect forward_from_rbuf, UInt<1>(0h1)
connect ren, UInt<1>(0h0)
connect wen, io.write.valid
connect io.read.ready, UInt<1>(0h1)
connect io.write.ready, UInt<1>(0h1)
else :
connect ren, UInt<1>(0h1)
connect wen, UInt<1>(0h0)
connect io.read.ready, UInt<1>(0h1)
connect io.write.ready, UInt<1>(0h0)
connect force_stall, io.write.valid
else :
connect ren, UInt<1>(0h0)
connect wen, io.write.valid
connect io.read.ready, UInt<1>(0h0)
connect io.write.ready, UInt<1>(0h1)
reg s1_read_idx : UInt<6>, clock
when io.read.valid :
connect s1_read_idx, io.read.bits.idx
node _T_5 = and(io.read.ready, io.read.valid)
node _T_6 = eq(forward_from_rbuf, UInt<1>(0h0))
node _T_7 = and(_T_5, _T_6)
reg REG : UInt<1>, clock
connect REG, _T_7
node _T_8 = eq(io.write.bits.idx, s1_read_idx)
node _T_9 = and(io.write.valid, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = and(REG, _T_10)
when _T_11 :
connect rbuf_valid, UInt<1>(0h1)
connect rbuf_idx, s1_read_idx
connect rbuf[0].tag, io.resp[0].tag
connect rbuf[0].coh.state, io.resp[0].coh.state
connect rbuf[1].tag, io.resp[1].tag
connect rbuf[1].coh.state, io.resp[1].coh.state
connect rbuf[2].tag, io.resp[2].tag
connect rbuf[2].coh.state, io.resp[2].coh.state
connect rbuf[3].tag, io.resp[3].tag
connect rbuf[3].coh.state, io.resp[3].coh.state
node _T_12 = eq(io.write.bits.idx, rbuf_idx)
node _T_13 = and(io.write.valid, _T_12)
when _T_13 :
connect rbuf_valid, UInt<1>(0h0)
when wen :
wire _WIRE : UInt<22>[4]
connect _WIRE[0], wdata
connect _WIRE[1], wdata
connect _WIRE[2], wdata
connect _WIRE[3], wdata
node _T_14 = bits(waddr, 3, 0)
write mport MPORT = tag_array[_T_14], clock
when wmask_0 :
connect MPORT[0], _WIRE[0]
when wmask_1 :
connect MPORT[1], _WIRE[1]
when wmask_2 :
connect MPORT[2], _WIRE[2]
when wmask_3 :
connect MPORT[3], _WIRE[3]
node _T_15 = eq(wen, UInt<1>(0h0))
node _T_16 = and(ren, _T_15)
wire _WIRE_1 : UInt<6>
invalidate _WIRE_1
when _T_16 :
connect _WIRE_1, io.read.bits.idx
node _T_17 = bits(_WIRE_1, 3, 0)
read mport MPORT_1 = tag_array[_T_17], clock
wire _WIRE_2 : { coh : { state : UInt<2>}, tag : UInt<20>}
wire _WIRE_3 : UInt<22>
connect _WIRE_3, MPORT_1[0]
node _T_18 = bits(_WIRE_3, 19, 0)
connect _WIRE_2.tag, _T_18
node _T_19 = bits(_WIRE_3, 21, 20)
connect _WIRE_2.coh.state, _T_19
wire _WIRE_4 : { coh : { state : UInt<2>}, tag : UInt<20>}
wire _WIRE_5 : UInt<22>
connect _WIRE_5, MPORT_1[1]
node _T_20 = bits(_WIRE_5, 19, 0)
connect _WIRE_4.tag, _T_20
node _T_21 = bits(_WIRE_5, 21, 20)
connect _WIRE_4.coh.state, _T_21
wire _WIRE_6 : { coh : { state : UInt<2>}, tag : UInt<20>}
wire _WIRE_7 : UInt<22>
connect _WIRE_7, MPORT_1[2]
node _T_22 = bits(_WIRE_7, 19, 0)
connect _WIRE_6.tag, _T_22
node _T_23 = bits(_WIRE_7, 21, 20)
connect _WIRE_6.coh.state, _T_23
wire _WIRE_8 : { coh : { state : UInt<2>}, tag : UInt<20>}
wire _WIRE_9 : UInt<22>
connect _WIRE_9, MPORT_1[3]
node _T_24 = bits(_WIRE_9, 19, 0)
connect _WIRE_8.tag, _T_24
node _T_25 = bits(_WIRE_9, 21, 20)
connect _WIRE_8.coh.state, _T_25
connect io.resp[0], _WIRE_2
connect io.resp[1], _WIRE_4
connect io.resp[2], _WIRE_6
connect io.resp[3], _WIRE_8
reg REG_1 : UInt<1>, clock
connect REG_1, forward_from_rbuf
when REG_1 :
reg r : { coh : { state : UInt<2>}, tag : UInt<20>}[4], clock
when forward_from_rbuf :
connect r, rbuf
connect io.resp, r | module L1MetadataArrayBank_2( // @[TagArray.scala:12:7]
input clock, // @[TagArray.scala:12:7]
input reset, // @[TagArray.scala:12:7]
output io_read_ready, // @[TagArray.scala:14:14]
input io_read_valid, // @[TagArray.scala:14:14]
input [5:0] io_read_bits_idx, // @[TagArray.scala:14:14]
input [3:0] io_read_bits_way_en, // @[TagArray.scala:14:14]
input [19:0] io_read_bits_tag, // @[TagArray.scala:14:14]
output io_write_ready, // @[TagArray.scala:14:14]
input io_write_valid, // @[TagArray.scala:14:14]
input [5:0] io_write_bits_idx, // @[TagArray.scala:14:14]
input [3:0] io_write_bits_way_en, // @[TagArray.scala:14:14]
input [19:0] io_write_bits_tag, // @[TagArray.scala:14:14]
input [1:0] io_write_bits_data_coh_state, // @[TagArray.scala:14:14]
input [19:0] io_write_bits_data_tag, // @[TagArray.scala:14:14]
output [1:0] io_resp_0_coh_state, // @[TagArray.scala:14:14]
output [19:0] io_resp_0_tag, // @[TagArray.scala:14:14]
output [1:0] io_resp_1_coh_state, // @[TagArray.scala:14:14]
output [19:0] io_resp_1_tag, // @[TagArray.scala:14:14]
output [1:0] io_resp_2_coh_state, // @[TagArray.scala:14:14]
output [19:0] io_resp_2_tag, // @[TagArray.scala:14:14]
output [1:0] io_resp_3_coh_state, // @[TagArray.scala:14:14]
output [19:0] io_resp_3_tag // @[TagArray.scala:14:14]
);
wire [3:0] tag_array_MPORT_1_addr; // @[TagArray.scala:87:28]
wire tag_array_MPORT_1_en; // @[TagArray.scala:87:51]
wire [3:0] tag_array_MPORT_addr; // @[TagArray.scala:85:20]
wire [87:0] _tag_array_RW0_rdata; // @[TagArray.scala:28:30]
wire io_read_valid_0 = io_read_valid; // @[TagArray.scala:12:7]
wire [5:0] io_read_bits_idx_0 = io_read_bits_idx; // @[TagArray.scala:12:7]
wire [3:0] io_read_bits_way_en_0 = io_read_bits_way_en; // @[TagArray.scala:12:7]
wire [19:0] io_read_bits_tag_0 = io_read_bits_tag; // @[TagArray.scala:12:7]
wire io_write_valid_0 = io_write_valid; // @[TagArray.scala:12:7]
wire [5:0] io_write_bits_idx_0 = io_write_bits_idx; // @[TagArray.scala:12:7]
wire [3:0] io_write_bits_way_en_0 = io_write_bits_way_en; // @[TagArray.scala:12:7]
wire [19:0] io_write_bits_tag_0 = io_write_bits_tag; // @[TagArray.scala:12:7]
wire [1:0] io_write_bits_data_coh_state_0 = io_write_bits_data_coh_state; // @[TagArray.scala:12:7]
wire [19:0] io_write_bits_data_tag_0 = io_write_bits_data_tag; // @[TagArray.scala:12:7]
wire [1:0] rstVal_meta_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] rstVal_coh_state = 2'h0; // @[HellaCache.scala:305:20]
wire [19:0] rstVal_tag = 20'h0; // @[HellaCache.scala:305:20]
wire [3:0] _wmask_T_1 = 4'hF; // @[TagArray.scala:23:42]
wire [3:0] _rmask_T_1 = 4'hF; // @[TagArray.scala:24:42]
wire [1:0] _stall_read_T = 2'h3; // @[TagArray.scala:33:34]
wire io_read_ready_0; // @[TagArray.scala:12:7]
wire io_write_ready_0; // @[TagArray.scala:12:7]
wire [1:0] io_resp_0_coh_state_0; // @[TagArray.scala:12:7]
wire [19:0] io_resp_0_tag_0; // @[TagArray.scala:12:7]
wire [1:0] io_resp_1_coh_state_0; // @[TagArray.scala:12:7]
wire [19:0] io_resp_1_tag_0; // @[TagArray.scala:12:7]
wire [1:0] io_resp_2_coh_state_0; // @[TagArray.scala:12:7]
wire [19:0] io_resp_2_tag_0; // @[TagArray.scala:12:7]
wire [1:0] io_resp_3_coh_state_0; // @[TagArray.scala:12:7]
wire [19:0] io_resp_3_tag_0; // @[TagArray.scala:12:7]
reg [4:0] rst_cnt; // @[TagArray.scala:19:24]
wire rst = ~(rst_cnt[4]); // @[TagArray.scala:19:24, :20:21]
wire _wmask_T = rst; // @[TagArray.scala:20:21, :23:23]
wire _rmask_T = rst; // @[TagArray.scala:20:21, :24:23]
wire [5:0] _GEN = {1'h0, rst_cnt}; // @[TagArray.scala:19:24, :21:18]
wire [5:0] waddr = rst ? _GEN : io_write_bits_idx_0; // @[TagArray.scala:12:7, :20:21, :21:18]
wire [1:0] _wdata_T_coh_state = rst ? 2'h0 : io_write_bits_data_coh_state_0; // @[TagArray.scala:12:7, :20:21, :22:18]
wire [19:0] _wdata_T_tag = rst ? 20'h0 : io_write_bits_data_tag_0; // @[TagArray.scala:12:7, :20:21, :22:18]
wire [21:0] wdata = {_wdata_T_coh_state, _wdata_T_tag}; // @[TagArray.scala:22:{18,52}]
wire [3:0] _wmask_T_2 = _wmask_T ? 4'hF : io_write_bits_way_en_0; // @[TagArray.scala:12:7, :23:{18,23}]
wire wmask_0 = _wmask_T_2[0]; // @[TagArray.scala:23:{18,81}]
wire wmask_1 = _wmask_T_2[1]; // @[TagArray.scala:23:{18,81}]
wire wmask_2 = _wmask_T_2[2]; // @[TagArray.scala:23:{18,81}]
wire wmask_3 = _wmask_T_2[3]; // @[TagArray.scala:23:{18,81}]
wire [3:0] _rmask_T_2 = _rmask_T ? 4'hF : io_read_bits_way_en_0; // @[TagArray.scala:12:7, :24:{18,23}]
wire rmask_0 = _rmask_T_2[0]; // @[TagArray.scala:24:{18,80}]
wire rmask_1 = _rmask_T_2[1]; // @[TagArray.scala:24:{18,80}]
wire rmask_2 = _rmask_T_2[2]; // @[TagArray.scala:24:{18,80}]
wire rmask_3 = _rmask_T_2[3]; // @[TagArray.scala:24:{18,80}]
wire [5:0] _rst_cnt_T = _GEN + 6'h1; // @[TagArray.scala:21:18, :25:35]
wire [4:0] _rst_cnt_T_1 = _rst_cnt_T[4:0]; // @[TagArray.scala:25:35]
wire wen; // @[TagArray.scala:30:17]
wire ren; // @[TagArray.scala:31:17]
reg [1:0] stall_ctr; // @[TagArray.scala:32:26]
wire stall_read = &stall_ctr; // @[TagArray.scala:32:26, :33:30]
wire force_stall; // @[TagArray.scala:34:29]
reg rbuf_valid; // @[TagArray.scala:36:27]
reg [3:0] rbuf_idx; // @[TagArray.scala:37:21]
reg [1:0] rbuf_0_coh_state; // @[TagArray.scala:38:17]
reg [19:0] rbuf_0_tag; // @[TagArray.scala:38:17]
reg [1:0] rbuf_1_coh_state; // @[TagArray.scala:38:17]
reg [19:0] rbuf_1_tag; // @[TagArray.scala:38:17]
reg [1:0] rbuf_2_coh_state; // @[TagArray.scala:38:17]
reg [19:0] rbuf_2_tag; // @[TagArray.scala:38:17]
reg [1:0] rbuf_3_coh_state; // @[TagArray.scala:38:17]
reg [19:0] rbuf_3_tag; // @[TagArray.scala:38:17]
wire forward_from_rbuf; // @[TagArray.scala:39:35]
wire [2:0] _stall_ctr_T = {1'h0, stall_ctr} + 3'h1; // @[TagArray.scala:32:26, :42:28]
wire [1:0] _stall_ctr_T_1 = _stall_ctr_T[1:0]; // @[TagArray.scala:42:28]
wire _T_2 = io_read_valid_0 & ~stall_read; // @[TagArray.scala:12:7, :33:30, :53:{25,28}]
wire [5:0] _GEN_0 = {2'h0, rbuf_idx}; // @[TagArray.scala:37:21, :54:30]
wire _T_4 = io_read_bits_idx_0 == _GEN_0 & rbuf_valid; // @[TagArray.scala:12:7, :36:27, :54:{30,43}]
assign forward_from_rbuf = ~rst & _T_2 & _T_4; // @[TagArray.scala:20:21, :39:35, :47:14, :53:{25,41}, :54:{43,58}]
assign force_stall = ~rst & _T_2 & ~_T_4 & io_write_valid_0; // @[TagArray.scala:12:7, :20:21, :34:29, :39:35, :47:14, :53:{25,41}, :54:{43,58}, :65:21]
assign ren = ~rst & _T_2 & ~_T_4; // @[TagArray.scala:20:21, :31:17, :39:35, :47:14, :49:9, :53:{25,41}, :54:{43,58}, :56:13, :61:13, :68:11]
wire _GEN_1 = ~_T_2 | _T_4; // @[TagArray.scala:53:{25,41}, :54:{43,58}, :69:11]
assign wen = rst | _GEN_1 & io_write_valid_0; // @[TagArray.scala:12:7, :20:21, :30:17, :47:14, :48:9, :53:41, :54:58, :69:11]
assign io_read_ready_0 = ~rst & _T_2; // @[TagArray.scala:12:7, :20:21, :39:35, :47:14, :50:19, :53:{25,41}]
assign io_write_ready_0 = ~rst & _GEN_1; // @[TagArray.scala:12:7, :20:21, :39:35, :47:14, :51:20, :53:41, :54:58, :69:11]
reg [5:0] s1_read_idx; // @[TagArray.scala:74:30]
reg REG; // @[TagArray.scala:75:16]
assign tag_array_MPORT_addr = waddr[3:0]; // @[TagArray.scala:21:18, :85:20]
assign tag_array_MPORT_1_en = ren & ~wen; // @[TagArray.scala:30:17, :31:17, :87:{51,54}]
assign tag_array_MPORT_1_addr = io_read_bits_idx_0[3:0]; // @[TagArray.scala:12:7, :87:28]
reg REG_1; // @[TagArray.scala:88:16]
reg [1:0] r_0_coh_state; // @[TagArray.scala:89:25]
reg [19:0] r_0_tag; // @[TagArray.scala:89:25]
reg [1:0] r_1_coh_state; // @[TagArray.scala:89:25]
reg [19:0] r_1_tag; // @[TagArray.scala:89:25]
reg [1:0] r_2_coh_state; // @[TagArray.scala:89:25]
reg [19:0] r_2_tag; // @[TagArray.scala:89:25]
reg [1:0] r_3_coh_state; // @[TagArray.scala:89:25]
reg [19:0] r_3_tag; // @[TagArray.scala:89:25]
assign io_resp_0_coh_state_0 = REG_1 ? r_0_coh_state : _tag_array_RW0_rdata[21:20]; // @[TagArray.scala:12:7, :28:30, :87:{11,74}, :88:{16,37}, :89:{13,25}]
assign io_resp_0_tag_0 = REG_1 ? r_0_tag : _tag_array_RW0_rdata[19:0]; // @[TagArray.scala:12:7, :28:30, :87:{11,74}, :88:{16,37}, :89:{13,25}]
assign io_resp_1_coh_state_0 = REG_1 ? r_1_coh_state : _tag_array_RW0_rdata[43:42]; // @[TagArray.scala:12:7, :28:30, :87:{11,74}, :88:{16,37}, :89:{13,25}]
assign io_resp_1_tag_0 = REG_1 ? r_1_tag : _tag_array_RW0_rdata[41:22]; // @[TagArray.scala:12:7, :28:30, :87:{11,74}, :88:{16,37}, :89:{13,25}]
assign io_resp_2_coh_state_0 = REG_1 ? r_2_coh_state : _tag_array_RW0_rdata[65:64]; // @[TagArray.scala:12:7, :28:30, :87:{11,74}, :88:{16,37}, :89:{13,25}]
assign io_resp_2_tag_0 = REG_1 ? r_2_tag : _tag_array_RW0_rdata[63:44]; // @[TagArray.scala:12:7, :28:30, :87:{11,74}, :88:{16,37}, :89:{13,25}]
assign io_resp_3_coh_state_0 = REG_1 ? r_3_coh_state : _tag_array_RW0_rdata[87:86]; // @[TagArray.scala:12:7, :28:30, :87:{11,74}, :88:{16,37}, :89:{13,25}]
assign io_resp_3_tag_0 = REG_1 ? r_3_tag : _tag_array_RW0_rdata[85:66]; // @[TagArray.scala:12:7, :28:30, :87:{11,74}, :88:{16,37}, :89:{13,25}]
wire _T_11 = REG & ~(io_write_valid_0 & io_write_bits_idx_0 == s1_read_idx); // @[TagArray.scala:12:7, :74:30, :75:{16,53,56,73,94}]
always @(posedge clock) begin // @[TagArray.scala:12:7]
if (reset) begin // @[TagArray.scala:12:7]
rst_cnt <= 5'h0; // @[TagArray.scala:19:24]
stall_ctr <= 2'h0; // @[TagArray.scala:32:26]
rbuf_valid <= 1'h0; // @[TagArray.scala:36:27]
end
else begin // @[TagArray.scala:12:7]
if (rst) // @[TagArray.scala:20:21]
rst_cnt <= _rst_cnt_T_1; // @[TagArray.scala:19:24, :25:35]
stall_ctr <= io_read_valid_0 & force_stall ? _stall_ctr_T_1 : 2'h0; // @[TagArray.scala:12:7, :32:26, :34:29, :41:{23,39}, :42:{15,28}, :44:15]
rbuf_valid <= ~(io_write_valid_0 & io_write_bits_idx_0 == _GEN_0) & (_T_11 | rbuf_valid); // @[TagArray.scala:12:7, :36:27, :54:30, :75:{53,112}, :76:16, :80:{24,45,59}, :81:16]
end
if (_T_11) begin // @[TagArray.scala:75:53]
rbuf_idx <= s1_read_idx[3:0]; // @[TagArray.scala:37:21, :74:30, :77:14]
rbuf_0_coh_state <= io_resp_0_coh_state_0; // @[TagArray.scala:12:7, :38:17]
rbuf_0_tag <= io_resp_0_tag_0; // @[TagArray.scala:12:7, :38:17]
rbuf_1_coh_state <= io_resp_1_coh_state_0; // @[TagArray.scala:12:7, :38:17]
rbuf_1_tag <= io_resp_1_tag_0; // @[TagArray.scala:12:7, :38:17]
rbuf_2_coh_state <= io_resp_2_coh_state_0; // @[TagArray.scala:12:7, :38:17]
rbuf_2_tag <= io_resp_2_tag_0; // @[TagArray.scala:12:7, :38:17]
rbuf_3_coh_state <= io_resp_3_coh_state_0; // @[TagArray.scala:12:7, :38:17]
rbuf_3_tag <= io_resp_3_tag_0; // @[TagArray.scala:12:7, :38:17]
end
if (io_read_valid_0) // @[TagArray.scala:12:7]
s1_read_idx <= io_read_bits_idx_0; // @[TagArray.scala:12:7, :74:30]
REG <= io_read_ready_0 & io_read_valid_0 & ~forward_from_rbuf; // @[Decoupled.scala:51:35]
REG_1 <= forward_from_rbuf; // @[TagArray.scala:39:35, :88:16]
if (forward_from_rbuf) begin // @[TagArray.scala:39:35]
r_0_coh_state <= rbuf_0_coh_state; // @[TagArray.scala:38:17, :89:25]
r_0_tag <= rbuf_0_tag; // @[TagArray.scala:38:17, :89:25]
r_1_coh_state <= rbuf_1_coh_state; // @[TagArray.scala:38:17, :89:25]
r_1_tag <= rbuf_1_tag; // @[TagArray.scala:38:17, :89:25]
r_2_coh_state <= rbuf_2_coh_state; // @[TagArray.scala:38:17, :89:25]
r_2_tag <= rbuf_2_tag; // @[TagArray.scala:38:17, :89:25]
r_3_coh_state <= rbuf_3_coh_state; // @[TagArray.scala:38:17, :89:25]
r_3_tag <= rbuf_3_tag; // @[TagArray.scala:38:17, :89:25]
end
always @(posedge)
tag_array_2 tag_array ( // @[TagArray.scala:28:30]
.RW0_addr (wen ? tag_array_MPORT_addr : tag_array_MPORT_1_addr), // @[TagArray.scala:28:30, :30:17, :85:20, :87:28]
.RW0_en (tag_array_MPORT_1_en | wen), // @[TagArray.scala:28:30, :30:17, :87:51]
.RW0_clk (clock),
.RW0_wmode (wen), // @[TagArray.scala:30:17]
.RW0_wdata ({4{wdata}}), // @[TagArray.scala:22:52, :28:30]
.RW0_rdata (_tag_array_RW0_rdata),
.RW0_wmask ({wmask_3, wmask_2, wmask_1, wmask_0}) // @[TagArray.scala:23:81, :28:30]
); // @[TagArray.scala:28:30]
assign io_read_ready = io_read_ready_0; // @[TagArray.scala:12:7]
assign io_write_ready = io_write_ready_0; // @[TagArray.scala:12:7]
assign io_resp_0_coh_state = io_resp_0_coh_state_0; // @[TagArray.scala:12:7]
assign io_resp_0_tag = io_resp_0_tag_0; // @[TagArray.scala:12:7]
assign io_resp_1_coh_state = io_resp_1_coh_state_0; // @[TagArray.scala:12:7]
assign io_resp_1_tag = io_resp_1_tag_0; // @[TagArray.scala:12:7]
assign io_resp_2_coh_state = io_resp_2_coh_state_0; // @[TagArray.scala:12:7]
assign io_resp_2_tag = io_resp_2_tag_0; // @[TagArray.scala:12:7]
assign io_resp_3_coh_state = io_resp_3_coh_state_0; // @[TagArray.scala:12:7]
assign io_resp_3_tag = io_resp_3_tag_0; // @[TagArray.scala:12:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_63 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T
node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2))
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_lo = cat(mask_acc_1, mask_acc)
node mask_hi = cat(mask_acc_3, mask_acc_2)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_15 :
node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_17 = and(UInt<1>(0h0), _T_16)
node _T_18 = or(UInt<1>(0h0), _T_17)
node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_20 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_21 = cvt(_T_20)
node _T_22 = and(_T_21, asSInt(UInt<7>(0h40)))
node _T_23 = asSInt(_T_22)
node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0)))
node _T_25 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_26 = cvt(_T_25)
node _T_27 = and(_T_26, asSInt(UInt<5>(0h14)))
node _T_28 = asSInt(_T_27)
node _T_29 = eq(_T_28, asSInt(UInt<1>(0h0)))
node _T_30 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_31 = cvt(_T_30)
node _T_32 = and(_T_31, asSInt(UInt<4>(0h8)))
node _T_33 = asSInt(_T_32)
node _T_34 = eq(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_36 = cvt(_T_35)
node _T_37 = and(_T_36, asSInt(UInt<6>(0h20)))
node _T_38 = asSInt(_T_37)
node _T_39 = eq(_T_38, asSInt(UInt<1>(0h0)))
node _T_40 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_41 = cvt(_T_40)
node _T_42 = and(_T_41, asSInt(UInt<8>(0h80)))
node _T_43 = asSInt(_T_42)
node _T_44 = eq(_T_43, asSInt(UInt<1>(0h0)))
node _T_45 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<9>(0h100)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_24, _T_29)
node _T_51 = or(_T_50, _T_34)
node _T_52 = or(_T_51, _T_39)
node _T_53 = or(_T_52, _T_44)
node _T_54 = or(_T_53, _T_49)
node _T_55 = and(_T_19, _T_54)
node _T_56 = or(UInt<1>(0h0), _T_55)
node _T_57 = and(_T_18, _T_56)
node _T_58 = asUInt(reset)
node _T_59 = eq(_T_58, UInt<1>(0h0))
when _T_59 :
node _T_60 = eq(_T_57, UInt<1>(0h0))
when _T_60 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_57, UInt<1>(0h1), "") : assert_2
node _T_61 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_62 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_63 = and(_T_61, _T_62)
node _T_64 = or(UInt<1>(0h0), _T_63)
node _T_65 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_66 = cvt(_T_65)
node _T_67 = and(_T_66, asSInt(UInt<7>(0h40)))
node _T_68 = asSInt(_T_67)
node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0)))
node _T_70 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_71 = cvt(_T_70)
node _T_72 = and(_T_71, asSInt(UInt<5>(0h14)))
node _T_73 = asSInt(_T_72)
node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0)))
node _T_75 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_76 = cvt(_T_75)
node _T_77 = and(_T_76, asSInt(UInt<4>(0h8)))
node _T_78 = asSInt(_T_77)
node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0)))
node _T_80 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_81 = cvt(_T_80)
node _T_82 = and(_T_81, asSInt(UInt<6>(0h20)))
node _T_83 = asSInt(_T_82)
node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_86 = cvt(_T_85)
node _T_87 = and(_T_86, asSInt(UInt<8>(0h80)))
node _T_88 = asSInt(_T_87)
node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0)))
node _T_90 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<9>(0h100)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_69, _T_74)
node _T_96 = or(_T_95, _T_79)
node _T_97 = or(_T_96, _T_84)
node _T_98 = or(_T_97, _T_89)
node _T_99 = or(_T_98, _T_94)
node _T_100 = and(_T_64, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(UInt<1>(0h0), _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_102, UInt<1>(0h1), "") : assert_3
node _T_106 = asUInt(reset)
node _T_107 = eq(_T_106, UInt<1>(0h0))
when _T_107 :
node _T_108 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_108 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_109 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_110 = asUInt(reset)
node _T_111 = eq(_T_110, UInt<1>(0h0))
when _T_111 :
node _T_112 = eq(_T_109, UInt<1>(0h0))
when _T_112 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_109, UInt<1>(0h1), "") : assert_5
node _T_113 = asUInt(reset)
node _T_114 = eq(_T_113, UInt<1>(0h0))
when _T_114 :
node _T_115 = eq(is_aligned, UInt<1>(0h0))
when _T_115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_116 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_117 = asUInt(reset)
node _T_118 = eq(_T_117, UInt<1>(0h0))
when _T_118 :
node _T_119 = eq(_T_116, UInt<1>(0h0))
when _T_119 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_116, UInt<1>(0h1), "") : assert_7
node _T_120 = not(io.in.a.bits.mask)
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = asUInt(reset)
node _T_123 = eq(_T_122, UInt<1>(0h0))
when _T_123 :
node _T_124 = eq(_T_121, UInt<1>(0h0))
when _T_124 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_121, UInt<1>(0h1), "") : assert_8
node _T_125 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_126 = asUInt(reset)
node _T_127 = eq(_T_126, UInt<1>(0h0))
when _T_127 :
node _T_128 = eq(_T_125, UInt<1>(0h0))
when _T_128 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_125, UInt<1>(0h1), "") : assert_9
node _T_129 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_129 :
node _T_130 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_131 = and(UInt<1>(0h0), _T_130)
node _T_132 = or(UInt<1>(0h0), _T_131)
node _T_133 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_134 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_135 = cvt(_T_134)
node _T_136 = and(_T_135, asSInt(UInt<7>(0h40)))
node _T_137 = asSInt(_T_136)
node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0)))
node _T_139 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_140 = cvt(_T_139)
node _T_141 = and(_T_140, asSInt(UInt<5>(0h14)))
node _T_142 = asSInt(_T_141)
node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0)))
node _T_144 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_145 = cvt(_T_144)
node _T_146 = and(_T_145, asSInt(UInt<4>(0h8)))
node _T_147 = asSInt(_T_146)
node _T_148 = eq(_T_147, asSInt(UInt<1>(0h0)))
node _T_149 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_150 = cvt(_T_149)
node _T_151 = and(_T_150, asSInt(UInt<6>(0h20)))
node _T_152 = asSInt(_T_151)
node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0)))
node _T_154 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_155 = cvt(_T_154)
node _T_156 = and(_T_155, asSInt(UInt<8>(0h80)))
node _T_157 = asSInt(_T_156)
node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0)))
node _T_159 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_160 = cvt(_T_159)
node _T_161 = and(_T_160, asSInt(UInt<9>(0h100)))
node _T_162 = asSInt(_T_161)
node _T_163 = eq(_T_162, asSInt(UInt<1>(0h0)))
node _T_164 = or(_T_138, _T_143)
node _T_165 = or(_T_164, _T_148)
node _T_166 = or(_T_165, _T_153)
node _T_167 = or(_T_166, _T_158)
node _T_168 = or(_T_167, _T_163)
node _T_169 = and(_T_133, _T_168)
node _T_170 = or(UInt<1>(0h0), _T_169)
node _T_171 = and(_T_132, _T_170)
node _T_172 = asUInt(reset)
node _T_173 = eq(_T_172, UInt<1>(0h0))
when _T_173 :
node _T_174 = eq(_T_171, UInt<1>(0h0))
when _T_174 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_171, UInt<1>(0h1), "") : assert_10
node _T_175 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_176 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_177 = and(_T_175, _T_176)
node _T_178 = or(UInt<1>(0h0), _T_177)
node _T_179 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_180 = cvt(_T_179)
node _T_181 = and(_T_180, asSInt(UInt<7>(0h40)))
node _T_182 = asSInt(_T_181)
node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0)))
node _T_184 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_185 = cvt(_T_184)
node _T_186 = and(_T_185, asSInt(UInt<5>(0h14)))
node _T_187 = asSInt(_T_186)
node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0)))
node _T_189 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_190 = cvt(_T_189)
node _T_191 = and(_T_190, asSInt(UInt<4>(0h8)))
node _T_192 = asSInt(_T_191)
node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0)))
node _T_194 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_195 = cvt(_T_194)
node _T_196 = and(_T_195, asSInt(UInt<6>(0h20)))
node _T_197 = asSInt(_T_196)
node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0)))
node _T_199 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_200 = cvt(_T_199)
node _T_201 = and(_T_200, asSInt(UInt<8>(0h80)))
node _T_202 = asSInt(_T_201)
node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0)))
node _T_204 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_205 = cvt(_T_204)
node _T_206 = and(_T_205, asSInt(UInt<9>(0h100)))
node _T_207 = asSInt(_T_206)
node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0)))
node _T_209 = or(_T_183, _T_188)
node _T_210 = or(_T_209, _T_193)
node _T_211 = or(_T_210, _T_198)
node _T_212 = or(_T_211, _T_203)
node _T_213 = or(_T_212, _T_208)
node _T_214 = and(_T_178, _T_213)
node _T_215 = or(UInt<1>(0h0), _T_214)
node _T_216 = and(UInt<1>(0h0), _T_215)
node _T_217 = asUInt(reset)
node _T_218 = eq(_T_217, UInt<1>(0h0))
when _T_218 :
node _T_219 = eq(_T_216, UInt<1>(0h0))
when _T_219 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_216, UInt<1>(0h1), "") : assert_11
node _T_220 = asUInt(reset)
node _T_221 = eq(_T_220, UInt<1>(0h0))
when _T_221 :
node _T_222 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_222 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_223 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_224 = asUInt(reset)
node _T_225 = eq(_T_224, UInt<1>(0h0))
when _T_225 :
node _T_226 = eq(_T_223, UInt<1>(0h0))
when _T_226 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_223, UInt<1>(0h1), "") : assert_13
node _T_227 = asUInt(reset)
node _T_228 = eq(_T_227, UInt<1>(0h0))
when _T_228 :
node _T_229 = eq(is_aligned, UInt<1>(0h0))
when _T_229 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_230 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_231 = asUInt(reset)
node _T_232 = eq(_T_231, UInt<1>(0h0))
when _T_232 :
node _T_233 = eq(_T_230, UInt<1>(0h0))
when _T_233 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_230, UInt<1>(0h1), "") : assert_15
node _T_234 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_235 = asUInt(reset)
node _T_236 = eq(_T_235, UInt<1>(0h0))
when _T_236 :
node _T_237 = eq(_T_234, UInt<1>(0h0))
when _T_237 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_234, UInt<1>(0h1), "") : assert_16
node _T_238 = not(io.in.a.bits.mask)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(_T_239, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_239, UInt<1>(0h1), "") : assert_17
node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_244 = asUInt(reset)
node _T_245 = eq(_T_244, UInt<1>(0h0))
when _T_245 :
node _T_246 = eq(_T_243, UInt<1>(0h0))
when _T_246 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_243, UInt<1>(0h1), "") : assert_18
node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_247 :
node _T_248 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_249 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = asUInt(reset)
node _T_253 = eq(_T_252, UInt<1>(0h0))
when _T_253 :
node _T_254 = eq(_T_251, UInt<1>(0h0))
when _T_254 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_251, UInt<1>(0h1), "") : assert_19
node _T_255 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_256 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_257 = and(_T_255, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_260 = cvt(_T_259)
node _T_261 = and(_T_260, asSInt(UInt<7>(0h40)))
node _T_262 = asSInt(_T_261)
node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0)))
node _T_264 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_265 = cvt(_T_264)
node _T_266 = and(_T_265, asSInt(UInt<5>(0h14)))
node _T_267 = asSInt(_T_266)
node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0)))
node _T_269 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_270 = cvt(_T_269)
node _T_271 = and(_T_270, asSInt(UInt<4>(0h8)))
node _T_272 = asSInt(_T_271)
node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0)))
node _T_274 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_275 = cvt(_T_274)
node _T_276 = and(_T_275, asSInt(UInt<6>(0h20)))
node _T_277 = asSInt(_T_276)
node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0)))
node _T_279 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_280 = cvt(_T_279)
node _T_281 = and(_T_280, asSInt(UInt<8>(0h80)))
node _T_282 = asSInt(_T_281)
node _T_283 = eq(_T_282, asSInt(UInt<1>(0h0)))
node _T_284 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_285 = cvt(_T_284)
node _T_286 = and(_T_285, asSInt(UInt<9>(0h100)))
node _T_287 = asSInt(_T_286)
node _T_288 = eq(_T_287, asSInt(UInt<1>(0h0)))
node _T_289 = or(_T_263, _T_268)
node _T_290 = or(_T_289, _T_273)
node _T_291 = or(_T_290, _T_278)
node _T_292 = or(_T_291, _T_283)
node _T_293 = or(_T_292, _T_288)
node _T_294 = and(_T_258, _T_293)
node _T_295 = or(UInt<1>(0h0), _T_294)
node _T_296 = asUInt(reset)
node _T_297 = eq(_T_296, UInt<1>(0h0))
when _T_297 :
node _T_298 = eq(_T_295, UInt<1>(0h0))
when _T_298 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_295, UInt<1>(0h1), "") : assert_20
node _T_299 = asUInt(reset)
node _T_300 = eq(_T_299, UInt<1>(0h0))
when _T_300 :
node _T_301 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_301 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(is_aligned, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_305 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(_T_305, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_305, UInt<1>(0h1), "") : assert_23
node _T_309 = eq(io.in.a.bits.mask, mask)
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_309, UInt<1>(0h1), "") : assert_24
node _T_313 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_313, UInt<1>(0h1), "") : assert_25
node _T_317 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_317 :
node _T_318 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_319 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_320 = and(_T_318, _T_319)
node _T_321 = or(UInt<1>(0h0), _T_320)
node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_323 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_324 = and(_T_322, _T_323)
node _T_325 = or(UInt<1>(0h0), _T_324)
node _T_326 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_327 = cvt(_T_326)
node _T_328 = and(_T_327, asSInt(UInt<7>(0h40)))
node _T_329 = asSInt(_T_328)
node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0)))
node _T_331 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_332 = cvt(_T_331)
node _T_333 = and(_T_332, asSInt(UInt<5>(0h14)))
node _T_334 = asSInt(_T_333)
node _T_335 = eq(_T_334, asSInt(UInt<1>(0h0)))
node _T_336 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_337 = cvt(_T_336)
node _T_338 = and(_T_337, asSInt(UInt<4>(0h8)))
node _T_339 = asSInt(_T_338)
node _T_340 = eq(_T_339, asSInt(UInt<1>(0h0)))
node _T_341 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_342 = cvt(_T_341)
node _T_343 = and(_T_342, asSInt(UInt<6>(0h20)))
node _T_344 = asSInt(_T_343)
node _T_345 = eq(_T_344, asSInt(UInt<1>(0h0)))
node _T_346 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_347 = cvt(_T_346)
node _T_348 = and(_T_347, asSInt(UInt<8>(0h80)))
node _T_349 = asSInt(_T_348)
node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0)))
node _T_351 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_352 = cvt(_T_351)
node _T_353 = and(_T_352, asSInt(UInt<9>(0h100)))
node _T_354 = asSInt(_T_353)
node _T_355 = eq(_T_354, asSInt(UInt<1>(0h0)))
node _T_356 = or(_T_330, _T_335)
node _T_357 = or(_T_356, _T_340)
node _T_358 = or(_T_357, _T_345)
node _T_359 = or(_T_358, _T_350)
node _T_360 = or(_T_359, _T_355)
node _T_361 = and(_T_325, _T_360)
node _T_362 = or(UInt<1>(0h0), _T_361)
node _T_363 = and(_T_321, _T_362)
node _T_364 = asUInt(reset)
node _T_365 = eq(_T_364, UInt<1>(0h0))
when _T_365 :
node _T_366 = eq(_T_363, UInt<1>(0h0))
when _T_366 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_363, UInt<1>(0h1), "") : assert_26
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_370 = asUInt(reset)
node _T_371 = eq(_T_370, UInt<1>(0h0))
when _T_371 :
node _T_372 = eq(is_aligned, UInt<1>(0h0))
when _T_372 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_373 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_374 = asUInt(reset)
node _T_375 = eq(_T_374, UInt<1>(0h0))
when _T_375 :
node _T_376 = eq(_T_373, UInt<1>(0h0))
when _T_376 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_373, UInt<1>(0h1), "") : assert_29
node _T_377 = eq(io.in.a.bits.mask, mask)
node _T_378 = asUInt(reset)
node _T_379 = eq(_T_378, UInt<1>(0h0))
when _T_379 :
node _T_380 = eq(_T_377, UInt<1>(0h0))
when _T_380 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_377, UInt<1>(0h1), "") : assert_30
node _T_381 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_381 :
node _T_382 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_383 = and(UInt<1>(0h0), _T_382)
node _T_384 = or(UInt<1>(0h0), _T_383)
node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_386 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_387 = and(_T_385, _T_386)
node _T_388 = or(UInt<1>(0h0), _T_387)
node _T_389 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_390 = cvt(_T_389)
node _T_391 = and(_T_390, asSInt(UInt<7>(0h40)))
node _T_392 = asSInt(_T_391)
node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0)))
node _T_394 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_395 = cvt(_T_394)
node _T_396 = and(_T_395, asSInt(UInt<5>(0h14)))
node _T_397 = asSInt(_T_396)
node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0)))
node _T_399 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_400 = cvt(_T_399)
node _T_401 = and(_T_400, asSInt(UInt<4>(0h8)))
node _T_402 = asSInt(_T_401)
node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0)))
node _T_404 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_405 = cvt(_T_404)
node _T_406 = and(_T_405, asSInt(UInt<6>(0h20)))
node _T_407 = asSInt(_T_406)
node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0)))
node _T_409 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_410 = cvt(_T_409)
node _T_411 = and(_T_410, asSInt(UInt<8>(0h80)))
node _T_412 = asSInt(_T_411)
node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0)))
node _T_414 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_415 = cvt(_T_414)
node _T_416 = and(_T_415, asSInt(UInt<9>(0h100)))
node _T_417 = asSInt(_T_416)
node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0)))
node _T_419 = or(_T_393, _T_398)
node _T_420 = or(_T_419, _T_403)
node _T_421 = or(_T_420, _T_408)
node _T_422 = or(_T_421, _T_413)
node _T_423 = or(_T_422, _T_418)
node _T_424 = and(_T_388, _T_423)
node _T_425 = or(UInt<1>(0h0), _T_424)
node _T_426 = and(_T_384, _T_425)
node _T_427 = asUInt(reset)
node _T_428 = eq(_T_427, UInt<1>(0h0))
when _T_428 :
node _T_429 = eq(_T_426, UInt<1>(0h0))
when _T_429 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_426, UInt<1>(0h1), "") : assert_31
node _T_430 = asUInt(reset)
node _T_431 = eq(_T_430, UInt<1>(0h0))
when _T_431 :
node _T_432 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_432 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(is_aligned, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_436 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_436, UInt<1>(0h1), "") : assert_34
node _T_440 = not(mask)
node _T_441 = and(io.in.a.bits.mask, _T_440)
node _T_442 = eq(_T_441, UInt<1>(0h0))
node _T_443 = asUInt(reset)
node _T_444 = eq(_T_443, UInt<1>(0h0))
when _T_444 :
node _T_445 = eq(_T_442, UInt<1>(0h0))
when _T_445 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_442, UInt<1>(0h1), "") : assert_35
node _T_446 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_446 :
node _T_447 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_448 = and(UInt<1>(0h0), _T_447)
node _T_449 = or(UInt<1>(0h0), _T_448)
node _T_450 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_451 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_452 = cvt(_T_451)
node _T_453 = and(_T_452, asSInt(UInt<7>(0h40)))
node _T_454 = asSInt(_T_453)
node _T_455 = eq(_T_454, asSInt(UInt<1>(0h0)))
node _T_456 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_457 = cvt(_T_456)
node _T_458 = and(_T_457, asSInt(UInt<5>(0h14)))
node _T_459 = asSInt(_T_458)
node _T_460 = eq(_T_459, asSInt(UInt<1>(0h0)))
node _T_461 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_462 = cvt(_T_461)
node _T_463 = and(_T_462, asSInt(UInt<4>(0h8)))
node _T_464 = asSInt(_T_463)
node _T_465 = eq(_T_464, asSInt(UInt<1>(0h0)))
node _T_466 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_467 = cvt(_T_466)
node _T_468 = and(_T_467, asSInt(UInt<6>(0h20)))
node _T_469 = asSInt(_T_468)
node _T_470 = eq(_T_469, asSInt(UInt<1>(0h0)))
node _T_471 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_472 = cvt(_T_471)
node _T_473 = and(_T_472, asSInt(UInt<8>(0h80)))
node _T_474 = asSInt(_T_473)
node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0)))
node _T_476 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_477 = cvt(_T_476)
node _T_478 = and(_T_477, asSInt(UInt<9>(0h100)))
node _T_479 = asSInt(_T_478)
node _T_480 = eq(_T_479, asSInt(UInt<1>(0h0)))
node _T_481 = or(_T_455, _T_460)
node _T_482 = or(_T_481, _T_465)
node _T_483 = or(_T_482, _T_470)
node _T_484 = or(_T_483, _T_475)
node _T_485 = or(_T_484, _T_480)
node _T_486 = and(_T_450, _T_485)
node _T_487 = or(UInt<1>(0h0), _T_486)
node _T_488 = and(_T_449, _T_487)
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_488, UInt<1>(0h1), "") : assert_36
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_495 = asUInt(reset)
node _T_496 = eq(_T_495, UInt<1>(0h0))
when _T_496 :
node _T_497 = eq(is_aligned, UInt<1>(0h0))
when _T_497 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_498 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_499 = asUInt(reset)
node _T_500 = eq(_T_499, UInt<1>(0h0))
when _T_500 :
node _T_501 = eq(_T_498, UInt<1>(0h0))
when _T_501 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_498, UInt<1>(0h1), "") : assert_39
node _T_502 = eq(io.in.a.bits.mask, mask)
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_502, UInt<1>(0h1), "") : assert_40
node _T_506 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_506 :
node _T_507 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_508 = and(UInt<1>(0h0), _T_507)
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_511 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_512 = cvt(_T_511)
node _T_513 = and(_T_512, asSInt(UInt<7>(0h40)))
node _T_514 = asSInt(_T_513)
node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0)))
node _T_516 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_517 = cvt(_T_516)
node _T_518 = and(_T_517, asSInt(UInt<5>(0h14)))
node _T_519 = asSInt(_T_518)
node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0)))
node _T_521 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_522 = cvt(_T_521)
node _T_523 = and(_T_522, asSInt(UInt<4>(0h8)))
node _T_524 = asSInt(_T_523)
node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0)))
node _T_526 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_527 = cvt(_T_526)
node _T_528 = and(_T_527, asSInt(UInt<6>(0h20)))
node _T_529 = asSInt(_T_528)
node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0)))
node _T_531 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_532 = cvt(_T_531)
node _T_533 = and(_T_532, asSInt(UInt<8>(0h80)))
node _T_534 = asSInt(_T_533)
node _T_535 = eq(_T_534, asSInt(UInt<1>(0h0)))
node _T_536 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_537 = cvt(_T_536)
node _T_538 = and(_T_537, asSInt(UInt<9>(0h100)))
node _T_539 = asSInt(_T_538)
node _T_540 = eq(_T_539, asSInt(UInt<1>(0h0)))
node _T_541 = or(_T_515, _T_520)
node _T_542 = or(_T_541, _T_525)
node _T_543 = or(_T_542, _T_530)
node _T_544 = or(_T_543, _T_535)
node _T_545 = or(_T_544, _T_540)
node _T_546 = and(_T_510, _T_545)
node _T_547 = or(UInt<1>(0h0), _T_546)
node _T_548 = and(_T_509, _T_547)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_548, UInt<1>(0h1), "") : assert_41
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_555 = asUInt(reset)
node _T_556 = eq(_T_555, UInt<1>(0h0))
when _T_556 :
node _T_557 = eq(is_aligned, UInt<1>(0h0))
when _T_557 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_558 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_559 = asUInt(reset)
node _T_560 = eq(_T_559, UInt<1>(0h0))
when _T_560 :
node _T_561 = eq(_T_558, UInt<1>(0h0))
when _T_561 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_558, UInt<1>(0h1), "") : assert_44
node _T_562 = eq(io.in.a.bits.mask, mask)
node _T_563 = asUInt(reset)
node _T_564 = eq(_T_563, UInt<1>(0h0))
when _T_564 :
node _T_565 = eq(_T_562, UInt<1>(0h0))
when _T_565 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_562, UInt<1>(0h1), "") : assert_45
node _T_566 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_566 :
node _T_567 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_568 = and(UInt<1>(0h0), _T_567)
node _T_569 = or(UInt<1>(0h0), _T_568)
node _T_570 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_571 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_572 = cvt(_T_571)
node _T_573 = and(_T_572, asSInt(UInt<7>(0h40)))
node _T_574 = asSInt(_T_573)
node _T_575 = eq(_T_574, asSInt(UInt<1>(0h0)))
node _T_576 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_577 = cvt(_T_576)
node _T_578 = and(_T_577, asSInt(UInt<5>(0h14)))
node _T_579 = asSInt(_T_578)
node _T_580 = eq(_T_579, asSInt(UInt<1>(0h0)))
node _T_581 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_582 = cvt(_T_581)
node _T_583 = and(_T_582, asSInt(UInt<4>(0h8)))
node _T_584 = asSInt(_T_583)
node _T_585 = eq(_T_584, asSInt(UInt<1>(0h0)))
node _T_586 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_587 = cvt(_T_586)
node _T_588 = and(_T_587, asSInt(UInt<6>(0h20)))
node _T_589 = asSInt(_T_588)
node _T_590 = eq(_T_589, asSInt(UInt<1>(0h0)))
node _T_591 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_592 = cvt(_T_591)
node _T_593 = and(_T_592, asSInt(UInt<8>(0h80)))
node _T_594 = asSInt(_T_593)
node _T_595 = eq(_T_594, asSInt(UInt<1>(0h0)))
node _T_596 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_597 = cvt(_T_596)
node _T_598 = and(_T_597, asSInt(UInt<9>(0h100)))
node _T_599 = asSInt(_T_598)
node _T_600 = eq(_T_599, asSInt(UInt<1>(0h0)))
node _T_601 = or(_T_575, _T_580)
node _T_602 = or(_T_601, _T_585)
node _T_603 = or(_T_602, _T_590)
node _T_604 = or(_T_603, _T_595)
node _T_605 = or(_T_604, _T_600)
node _T_606 = and(_T_570, _T_605)
node _T_607 = or(UInt<1>(0h0), _T_606)
node _T_608 = and(_T_569, _T_607)
node _T_609 = asUInt(reset)
node _T_610 = eq(_T_609, UInt<1>(0h0))
when _T_610 :
node _T_611 = eq(_T_608, UInt<1>(0h0))
when _T_611 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_608, UInt<1>(0h1), "") : assert_46
node _T_612 = asUInt(reset)
node _T_613 = eq(_T_612, UInt<1>(0h0))
when _T_613 :
node _T_614 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_614 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_615 = asUInt(reset)
node _T_616 = eq(_T_615, UInt<1>(0h0))
when _T_616 :
node _T_617 = eq(is_aligned, UInt<1>(0h0))
when _T_617 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_618 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_619 = asUInt(reset)
node _T_620 = eq(_T_619, UInt<1>(0h0))
when _T_620 :
node _T_621 = eq(_T_618, UInt<1>(0h0))
when _T_621 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_618, UInt<1>(0h1), "") : assert_49
node _T_622 = eq(io.in.a.bits.mask, mask)
node _T_623 = asUInt(reset)
node _T_624 = eq(_T_623, UInt<1>(0h0))
when _T_624 :
node _T_625 = eq(_T_622, UInt<1>(0h0))
when _T_625 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_622, UInt<1>(0h1), "") : assert_50
node _T_626 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_626, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_630 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_630, UInt<1>(0h1), "") : assert_52
node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_1
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_634 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_634 :
node _T_635 = asUInt(reset)
node _T_636 = eq(_T_635, UInt<1>(0h0))
when _T_636 :
node _T_637 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_637 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_638 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_639 = asUInt(reset)
node _T_640 = eq(_T_639, UInt<1>(0h0))
when _T_640 :
node _T_641 = eq(_T_638, UInt<1>(0h0))
when _T_641 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_638, UInt<1>(0h1), "") : assert_54
node _T_642 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_643 = asUInt(reset)
node _T_644 = eq(_T_643, UInt<1>(0h0))
when _T_644 :
node _T_645 = eq(_T_642, UInt<1>(0h0))
when _T_645 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_642, UInt<1>(0h1), "") : assert_55
node _T_646 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_647 = asUInt(reset)
node _T_648 = eq(_T_647, UInt<1>(0h0))
when _T_648 :
node _T_649 = eq(_T_646, UInt<1>(0h0))
when _T_649 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_646, UInt<1>(0h1), "") : assert_56
node _T_650 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_651 = asUInt(reset)
node _T_652 = eq(_T_651, UInt<1>(0h0))
when _T_652 :
node _T_653 = eq(_T_650, UInt<1>(0h0))
when _T_653 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_650, UInt<1>(0h1), "") : assert_57
node _T_654 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_654 :
node _T_655 = asUInt(reset)
node _T_656 = eq(_T_655, UInt<1>(0h0))
when _T_656 :
node _T_657 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_657 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_658 = asUInt(reset)
node _T_659 = eq(_T_658, UInt<1>(0h0))
when _T_659 :
node _T_660 = eq(sink_ok, UInt<1>(0h0))
when _T_660 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_661 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_662 = asUInt(reset)
node _T_663 = eq(_T_662, UInt<1>(0h0))
when _T_663 :
node _T_664 = eq(_T_661, UInt<1>(0h0))
when _T_664 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_661, UInt<1>(0h1), "") : assert_60
node _T_665 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_666 = asUInt(reset)
node _T_667 = eq(_T_666, UInt<1>(0h0))
when _T_667 :
node _T_668 = eq(_T_665, UInt<1>(0h0))
when _T_668 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_665, UInt<1>(0h1), "") : assert_61
node _T_669 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_670 = asUInt(reset)
node _T_671 = eq(_T_670, UInt<1>(0h0))
when _T_671 :
node _T_672 = eq(_T_669, UInt<1>(0h0))
when _T_672 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_669, UInt<1>(0h1), "") : assert_62
node _T_673 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_674 = asUInt(reset)
node _T_675 = eq(_T_674, UInt<1>(0h0))
when _T_675 :
node _T_676 = eq(_T_673, UInt<1>(0h0))
when _T_676 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_673, UInt<1>(0h1), "") : assert_63
node _T_677 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_678 = or(UInt<1>(0h0), _T_677)
node _T_679 = asUInt(reset)
node _T_680 = eq(_T_679, UInt<1>(0h0))
when _T_680 :
node _T_681 = eq(_T_678, UInt<1>(0h0))
when _T_681 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_678, UInt<1>(0h1), "") : assert_64
node _T_682 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_682 :
node _T_683 = asUInt(reset)
node _T_684 = eq(_T_683, UInt<1>(0h0))
when _T_684 :
node _T_685 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_685 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_686 = asUInt(reset)
node _T_687 = eq(_T_686, UInt<1>(0h0))
when _T_687 :
node _T_688 = eq(sink_ok, UInt<1>(0h0))
when _T_688 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_689 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_690 = asUInt(reset)
node _T_691 = eq(_T_690, UInt<1>(0h0))
when _T_691 :
node _T_692 = eq(_T_689, UInt<1>(0h0))
when _T_692 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_689, UInt<1>(0h1), "") : assert_67
node _T_693 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_694 = asUInt(reset)
node _T_695 = eq(_T_694, UInt<1>(0h0))
when _T_695 :
node _T_696 = eq(_T_693, UInt<1>(0h0))
when _T_696 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_693, UInt<1>(0h1), "") : assert_68
node _T_697 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_698 = asUInt(reset)
node _T_699 = eq(_T_698, UInt<1>(0h0))
when _T_699 :
node _T_700 = eq(_T_697, UInt<1>(0h0))
when _T_700 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_697, UInt<1>(0h1), "") : assert_69
node _T_701 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_702 = or(_T_701, io.in.d.bits.corrupt)
node _T_703 = asUInt(reset)
node _T_704 = eq(_T_703, UInt<1>(0h0))
when _T_704 :
node _T_705 = eq(_T_702, UInt<1>(0h0))
when _T_705 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_702, UInt<1>(0h1), "") : assert_70
node _T_706 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_707 = or(UInt<1>(0h0), _T_706)
node _T_708 = asUInt(reset)
node _T_709 = eq(_T_708, UInt<1>(0h0))
when _T_709 :
node _T_710 = eq(_T_707, UInt<1>(0h0))
when _T_710 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_707, UInt<1>(0h1), "") : assert_71
node _T_711 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_711 :
node _T_712 = asUInt(reset)
node _T_713 = eq(_T_712, UInt<1>(0h0))
when _T_713 :
node _T_714 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_714 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_715 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_716 = asUInt(reset)
node _T_717 = eq(_T_716, UInt<1>(0h0))
when _T_717 :
node _T_718 = eq(_T_715, UInt<1>(0h0))
when _T_718 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_715, UInt<1>(0h1), "") : assert_73
node _T_719 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_720 = asUInt(reset)
node _T_721 = eq(_T_720, UInt<1>(0h0))
when _T_721 :
node _T_722 = eq(_T_719, UInt<1>(0h0))
when _T_722 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_719, UInt<1>(0h1), "") : assert_74
node _T_723 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_724 = or(UInt<1>(0h0), _T_723)
node _T_725 = asUInt(reset)
node _T_726 = eq(_T_725, UInt<1>(0h0))
when _T_726 :
node _T_727 = eq(_T_724, UInt<1>(0h0))
when _T_727 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_724, UInt<1>(0h1), "") : assert_75
node _T_728 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_728 :
node _T_729 = asUInt(reset)
node _T_730 = eq(_T_729, UInt<1>(0h0))
when _T_730 :
node _T_731 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_731 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_732 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_733 = asUInt(reset)
node _T_734 = eq(_T_733, UInt<1>(0h0))
when _T_734 :
node _T_735 = eq(_T_732, UInt<1>(0h0))
when _T_735 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_732, UInt<1>(0h1), "") : assert_77
node _T_736 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_737 = or(_T_736, io.in.d.bits.corrupt)
node _T_738 = asUInt(reset)
node _T_739 = eq(_T_738, UInt<1>(0h0))
when _T_739 :
node _T_740 = eq(_T_737, UInt<1>(0h0))
when _T_740 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_737, UInt<1>(0h1), "") : assert_78
node _T_741 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_742 = or(UInt<1>(0h0), _T_741)
node _T_743 = asUInt(reset)
node _T_744 = eq(_T_743, UInt<1>(0h0))
when _T_744 :
node _T_745 = eq(_T_742, UInt<1>(0h0))
when _T_745 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_742, UInt<1>(0h1), "") : assert_79
node _T_746 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_746 :
node _T_747 = asUInt(reset)
node _T_748 = eq(_T_747, UInt<1>(0h0))
when _T_748 :
node _T_749 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_749 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_750 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_751 = asUInt(reset)
node _T_752 = eq(_T_751, UInt<1>(0h0))
when _T_752 :
node _T_753 = eq(_T_750, UInt<1>(0h0))
when _T_753 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_750, UInt<1>(0h1), "") : assert_81
node _T_754 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_755 = asUInt(reset)
node _T_756 = eq(_T_755, UInt<1>(0h0))
when _T_756 :
node _T_757 = eq(_T_754, UInt<1>(0h0))
when _T_757 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_754, UInt<1>(0h1), "") : assert_82
node _T_758 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_759 = or(UInt<1>(0h0), _T_758)
node _T_760 = asUInt(reset)
node _T_761 = eq(_T_760, UInt<1>(0h0))
when _T_761 :
node _T_762 = eq(_T_759, UInt<1>(0h0))
when _T_762 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_759, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<32>(0h0)
connect _WIRE.bits.mask, UInt<4>(0h0)
connect _WIRE.bits.address, UInt<9>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_763 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_764 = asUInt(reset)
node _T_765 = eq(_T_764, UInt<1>(0h0))
when _T_765 :
node _T_766 = eq(_T_763, UInt<1>(0h0))
when _T_766 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_763, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<32>(0h0)
connect _WIRE_2.bits.address, UInt<9>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_767 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_768 = asUInt(reset)
node _T_769 = eq(_T_768, UInt<1>(0h0))
when _T_769 :
node _T_770 = eq(_T_767, UInt<1>(0h0))
when _T_770 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_767, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_771 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_772 = asUInt(reset)
node _T_773 = eq(_T_772, UInt<1>(0h0))
when _T_773 :
node _T_774 = eq(_T_771, UInt<1>(0h0))
when _T_774 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_771, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_775 = eq(a_first, UInt<1>(0h0))
node _T_776 = and(io.in.a.valid, _T_775)
when _T_776 :
node _T_777 = eq(io.in.a.bits.opcode, opcode)
node _T_778 = asUInt(reset)
node _T_779 = eq(_T_778, UInt<1>(0h0))
when _T_779 :
node _T_780 = eq(_T_777, UInt<1>(0h0))
when _T_780 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_777, UInt<1>(0h1), "") : assert_87
node _T_781 = eq(io.in.a.bits.param, param)
node _T_782 = asUInt(reset)
node _T_783 = eq(_T_782, UInt<1>(0h0))
when _T_783 :
node _T_784 = eq(_T_781, UInt<1>(0h0))
when _T_784 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_781, UInt<1>(0h1), "") : assert_88
node _T_785 = eq(io.in.a.bits.size, size)
node _T_786 = asUInt(reset)
node _T_787 = eq(_T_786, UInt<1>(0h0))
when _T_787 :
node _T_788 = eq(_T_785, UInt<1>(0h0))
when _T_788 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_785, UInt<1>(0h1), "") : assert_89
node _T_789 = eq(io.in.a.bits.source, source)
node _T_790 = asUInt(reset)
node _T_791 = eq(_T_790, UInt<1>(0h0))
when _T_791 :
node _T_792 = eq(_T_789, UInt<1>(0h0))
when _T_792 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_789, UInt<1>(0h1), "") : assert_90
node _T_793 = eq(io.in.a.bits.address, address)
node _T_794 = asUInt(reset)
node _T_795 = eq(_T_794, UInt<1>(0h0))
when _T_795 :
node _T_796 = eq(_T_793, UInt<1>(0h0))
when _T_796 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_793, UInt<1>(0h1), "") : assert_91
node _T_797 = and(io.in.a.ready, io.in.a.valid)
node _T_798 = and(_T_797, a_first)
when _T_798 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_799 = eq(d_first, UInt<1>(0h0))
node _T_800 = and(io.in.d.valid, _T_799)
when _T_800 :
node _T_801 = eq(io.in.d.bits.opcode, opcode_1)
node _T_802 = asUInt(reset)
node _T_803 = eq(_T_802, UInt<1>(0h0))
when _T_803 :
node _T_804 = eq(_T_801, UInt<1>(0h0))
when _T_804 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_801, UInt<1>(0h1), "") : assert_92
node _T_805 = eq(io.in.d.bits.param, param_1)
node _T_806 = asUInt(reset)
node _T_807 = eq(_T_806, UInt<1>(0h0))
when _T_807 :
node _T_808 = eq(_T_805, UInt<1>(0h0))
when _T_808 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_805, UInt<1>(0h1), "") : assert_93
node _T_809 = eq(io.in.d.bits.size, size_1)
node _T_810 = asUInt(reset)
node _T_811 = eq(_T_810, UInt<1>(0h0))
when _T_811 :
node _T_812 = eq(_T_809, UInt<1>(0h0))
when _T_812 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_809, UInt<1>(0h1), "") : assert_94
node _T_813 = eq(io.in.d.bits.source, source_1)
node _T_814 = asUInt(reset)
node _T_815 = eq(_T_814, UInt<1>(0h0))
when _T_815 :
node _T_816 = eq(_T_813, UInt<1>(0h0))
when _T_816 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_813, UInt<1>(0h1), "") : assert_95
node _T_817 = eq(io.in.d.bits.sink, sink)
node _T_818 = asUInt(reset)
node _T_819 = eq(_T_818, UInt<1>(0h0))
when _T_819 :
node _T_820 = eq(_T_817, UInt<1>(0h0))
when _T_820 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_817, UInt<1>(0h1), "") : assert_96
node _T_821 = eq(io.in.d.bits.denied, denied)
node _T_822 = asUInt(reset)
node _T_823 = eq(_T_822, UInt<1>(0h0))
when _T_823 :
node _T_824 = eq(_T_821, UInt<1>(0h0))
when _T_824 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_821, UInt<1>(0h1), "") : assert_97
node _T_825 = and(io.in.d.ready, io.in.d.valid)
node _T_826 = and(_T_825, d_first)
when _T_826 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1>
connect a_set, UInt<1>(0h0)
wire a_set_wo_ready : UInt<1>
connect a_set_wo_ready, UInt<1>(0h0)
wire a_opcodes_set : UInt<4>
connect a_opcodes_set, UInt<4>(0h0)
wire a_sizes_set : UInt<4>
connect a_sizes_set, UInt<4>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_827 = and(io.in.a.valid, a_first_1)
node _T_828 = and(_T_827, UInt<1>(0h1))
when _T_828 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_829 = and(io.in.a.ready, io.in.a.valid)
node _T_830 = and(_T_829, a_first_1)
node _T_831 = and(_T_830, UInt<1>(0h1))
when _T_831 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_832 = dshr(inflight, io.in.a.bits.source)
node _T_833 = bits(_T_832, 0, 0)
node _T_834 = eq(_T_833, UInt<1>(0h0))
node _T_835 = asUInt(reset)
node _T_836 = eq(_T_835, UInt<1>(0h0))
when _T_836 :
node _T_837 = eq(_T_834, UInt<1>(0h0))
when _T_837 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_834, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1>
connect d_clr, UInt<1>(0h0)
wire d_clr_wo_ready : UInt<1>
connect d_clr_wo_ready, UInt<1>(0h0)
wire d_opcodes_clr : UInt<4>
connect d_opcodes_clr, UInt<4>(0h0)
wire d_sizes_clr : UInt<4>
connect d_sizes_clr, UInt<4>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_838 = and(io.in.d.valid, d_first_1)
node _T_839 = and(_T_838, UInt<1>(0h1))
node _T_840 = eq(d_release_ack, UInt<1>(0h0))
node _T_841 = and(_T_839, _T_840)
when _T_841 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_842 = and(io.in.d.ready, io.in.d.valid)
node _T_843 = and(_T_842, d_first_1)
node _T_844 = and(_T_843, UInt<1>(0h1))
node _T_845 = eq(d_release_ack, UInt<1>(0h0))
node _T_846 = and(_T_844, _T_845)
when _T_846 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_847 = and(io.in.d.valid, d_first_1)
node _T_848 = and(_T_847, UInt<1>(0h1))
node _T_849 = eq(d_release_ack, UInt<1>(0h0))
node _T_850 = and(_T_848, _T_849)
when _T_850 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_851 = dshr(inflight, io.in.d.bits.source)
node _T_852 = bits(_T_851, 0, 0)
node _T_853 = or(_T_852, same_cycle_resp)
node _T_854 = asUInt(reset)
node _T_855 = eq(_T_854, UInt<1>(0h0))
when _T_855 :
node _T_856 = eq(_T_853, UInt<1>(0h0))
when _T_856 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_853, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_857 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_858 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_859 = or(_T_857, _T_858)
node _T_860 = asUInt(reset)
node _T_861 = eq(_T_860, UInt<1>(0h0))
when _T_861 :
node _T_862 = eq(_T_859, UInt<1>(0h0))
when _T_862 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_859, UInt<1>(0h1), "") : assert_100
node _T_863 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_864 = asUInt(reset)
node _T_865 = eq(_T_864, UInt<1>(0h0))
when _T_865 :
node _T_866 = eq(_T_863, UInt<1>(0h0))
when _T_866 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_863, UInt<1>(0h1), "") : assert_101
else :
node _T_867 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_868 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_869 = or(_T_867, _T_868)
node _T_870 = asUInt(reset)
node _T_871 = eq(_T_870, UInt<1>(0h0))
when _T_871 :
node _T_872 = eq(_T_869, UInt<1>(0h0))
when _T_872 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_869, UInt<1>(0h1), "") : assert_102
node _T_873 = eq(io.in.d.bits.size, a_size_lookup)
node _T_874 = asUInt(reset)
node _T_875 = eq(_T_874, UInt<1>(0h0))
when _T_875 :
node _T_876 = eq(_T_873, UInt<1>(0h0))
when _T_876 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_873, UInt<1>(0h1), "") : assert_103
node _T_877 = and(io.in.d.valid, d_first_1)
node _T_878 = and(_T_877, a_first_1)
node _T_879 = and(_T_878, io.in.a.valid)
node _T_880 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_881 = and(_T_879, _T_880)
node _T_882 = eq(d_release_ack, UInt<1>(0h0))
node _T_883 = and(_T_881, _T_882)
when _T_883 :
node _T_884 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_885 = or(_T_884, io.in.a.ready)
node _T_886 = asUInt(reset)
node _T_887 = eq(_T_886, UInt<1>(0h0))
when _T_887 :
node _T_888 = eq(_T_885, UInt<1>(0h0))
when _T_888 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_885, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_127
node _T_889 = orr(inflight)
node _T_890 = eq(_T_889, UInt<1>(0h0))
node _T_891 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_892 = or(_T_890, _T_891)
node _T_893 = lt(watchdog, plusarg_reader.out)
node _T_894 = or(_T_892, _T_893)
node _T_895 = asUInt(reset)
node _T_896 = eq(_T_895, UInt<1>(0h0))
when _T_896 :
node _T_897 = eq(_T_894, UInt<1>(0h0))
when _T_897 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_894, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_898 = and(io.in.a.ready, io.in.a.valid)
node _T_899 = and(io.in.d.ready, io.in.d.valid)
node _T_900 = or(_T_898, _T_899)
when _T_900 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<32>(0h0)
connect _c_first_WIRE.bits.address, UInt<9>(0h0)
connect _c_first_WIRE.bits.source, UInt<1>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<9>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1>
connect c_set, UInt<1>(0h0)
wire c_set_wo_ready : UInt<1>
connect c_set_wo_ready, UInt<1>(0h0)
wire c_opcodes_set : UInt<4>
connect c_opcodes_set, UInt<4>(0h0)
wire c_sizes_set : UInt<4>
connect c_sizes_set, UInt<4>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<32>(0h0)
connect _WIRE_6.bits.address, UInt<9>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_901 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<32>(0h0)
connect _WIRE_8.bits.address, UInt<9>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_902 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_903 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_904 = and(_T_902, _T_903)
node _T_905 = and(_T_901, _T_904)
when _T_905 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<9>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<32>(0h0)
connect _WIRE_10.bits.address, UInt<9>(0h0)
connect _WIRE_10.bits.source, UInt<1>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_906 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_907 = and(_T_906, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<32>(0h0)
connect _WIRE_12.bits.address, UInt<9>(0h0)
connect _WIRE_12.bits.source, UInt<1>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_908 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_909 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_910 = and(_T_908, _T_909)
node _T_911 = and(_T_907, _T_910)
when _T_911 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<9>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<9>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<32>(0h0)
connect _WIRE_14.bits.address, UInt<9>(0h0)
connect _WIRE_14.bits.source, UInt<1>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_912 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_913 = bits(_T_912, 0, 0)
node _T_914 = eq(_T_913, UInt<1>(0h0))
node _T_915 = asUInt(reset)
node _T_916 = eq(_T_915, UInt<1>(0h0))
when _T_916 :
node _T_917 = eq(_T_914, UInt<1>(0h0))
when _T_917 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_914, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<9>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<9>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1>
connect d_clr_1, UInt<1>(0h0)
wire d_clr_wo_ready_1 : UInt<1>
connect d_clr_wo_ready_1, UInt<1>(0h0)
wire d_opcodes_clr_1 : UInt<4>
connect d_opcodes_clr_1, UInt<4>(0h0)
wire d_sizes_clr_1 : UInt<4>
connect d_sizes_clr_1, UInt<4>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_918 = and(io.in.d.valid, d_first_2)
node _T_919 = and(_T_918, UInt<1>(0h1))
node _T_920 = and(_T_919, d_release_ack_1)
when _T_920 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_921 = and(io.in.d.ready, io.in.d.valid)
node _T_922 = and(_T_921, d_first_2)
node _T_923 = and(_T_922, UInt<1>(0h1))
node _T_924 = and(_T_923, d_release_ack_1)
when _T_924 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_925 = and(io.in.d.valid, d_first_2)
node _T_926 = and(_T_925, UInt<1>(0h1))
node _T_927 = and(_T_926, d_release_ack_1)
when _T_927 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_928 = dshr(inflight_1, io.in.d.bits.source)
node _T_929 = bits(_T_928, 0, 0)
node _T_930 = or(_T_929, same_cycle_resp_1)
node _T_931 = asUInt(reset)
node _T_932 = eq(_T_931, UInt<1>(0h0))
when _T_932 :
node _T_933 = eq(_T_930, UInt<1>(0h0))
when _T_933 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_930, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<32>(0h0)
connect _WIRE_16.bits.address, UInt<9>(0h0)
connect _WIRE_16.bits.source, UInt<1>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_934 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_935 = asUInt(reset)
node _T_936 = eq(_T_935, UInt<1>(0h0))
when _T_936 :
node _T_937 = eq(_T_934, UInt<1>(0h0))
when _T_937 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_934, UInt<1>(0h1), "") : assert_108
else :
node _T_938 = eq(io.in.d.bits.size, c_size_lookup)
node _T_939 = asUInt(reset)
node _T_940 = eq(_T_939, UInt<1>(0h0))
when _T_940 :
node _T_941 = eq(_T_938, UInt<1>(0h0))
when _T_941 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_938, UInt<1>(0h1), "") : assert_109
node _T_942 = and(io.in.d.valid, d_first_2)
node _T_943 = and(_T_942, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<32>(0h0)
connect _WIRE_18.bits.address, UInt<9>(0h0)
connect _WIRE_18.bits.source, UInt<1>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_944 = and(_T_943, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<32>(0h0)
connect _WIRE_20.bits.address, UInt<9>(0h0)
connect _WIRE_20.bits.source, UInt<1>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_945 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_946 = and(_T_944, _T_945)
node _T_947 = and(_T_946, d_release_ack_1)
node _T_948 = eq(c_probe_ack, UInt<1>(0h0))
node _T_949 = and(_T_947, _T_948)
when _T_949 :
node _T_950 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<32>(0h0)
connect _WIRE_22.bits.address, UInt<9>(0h0)
connect _WIRE_22.bits.source, UInt<1>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_951 = or(_T_950, _WIRE_23.ready)
node _T_952 = asUInt(reset)
node _T_953 = eq(_T_952, UInt<1>(0h0))
when _T_953 :
node _T_954 = eq(_T_951, UInt<1>(0h0))
when _T_954 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_951, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_128
node _T_955 = orr(inflight_1)
node _T_956 = eq(_T_955, UInt<1>(0h0))
node _T_957 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_958 = or(_T_956, _T_957)
node _T_959 = lt(watchdog_1, plusarg_reader_1.out)
node _T_960 = or(_T_958, _T_959)
node _T_961 = asUInt(reset)
node _T_962 = eq(_T_961, UInt<1>(0h0))
when _T_962 :
node _T_963 = eq(_T_960, UInt<1>(0h0))
when _T_963 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_960, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<32>(0h0)
connect _WIRE_24.bits.address, UInt<9>(0h0)
connect _WIRE_24.bits.source, UInt<1>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_964 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_965 = and(io.in.d.ready, io.in.d.valid)
node _T_966 = or(_T_964, _T_965)
when _T_966 :
connect watchdog_1, UInt<1>(0h0)
extmodule plusarg_reader_129 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_130 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLMonitor_63( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input io_in_a_bits_source, // @[Monitor.scala:20:14]
input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [8:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire c_set = 1'h0; // @[Monitor.scala:738:34]
wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_first_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_first_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_set_wo_ready_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_wo_ready_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_4_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_5_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52]
wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34]
wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79]
wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77]
wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [1:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [4:0] _GEN = 5'h3 << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [4:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [4:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [4:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [1:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [8:0] _is_aligned_T = {7'h0, io_in_a_bits_address_0[1:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 9'h0; // @[Edges.scala:21:{16,24}]
wire mask_sizeOH_shiftAmount = _mask_sizeOH_T[0]; // @[OneHot.scala:64:49]
wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [1:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}]
wire [1:0] mask_sizeOH = {_mask_sizeOH_T_2[1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_0_1 = io_in_a_bits_size_0[1]; // @[Misc.scala:206:21]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31]
wire _T_898 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_898; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_898; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire [1:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg source; // @[Monitor.scala:390:22]
reg [8:0] address; // @[Monitor.scala:391:22]
wire _T_966 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_966; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_966; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_966; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [4:0] _GEN_0 = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg source_1; // @[Monitor.scala:541:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [3:0] inflight_sizes; // @[Monitor.scala:618:33]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire [1:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire a_set; // @[Monitor.scala:626:34]
wire a_set_wo_ready; // @[Monitor.scala:627:34]
wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [3:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [3:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [3:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}]
wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [1:0] _GEN_2 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35]
wire [1:0] _GEN_3 = 2'h1 << _GEN_2; // @[OneHot.scala:58:35]
wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [1:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T & _a_set_wo_ready_T[0]; // @[OneHot.scala:58:35]
wire _T_831 = _T_898 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_831 & _a_set_T[0]; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_831 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_831 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [3:0] _GEN_4 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [3:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_4; // @[Monitor.scala:659:79]
wire [3:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_4; // @[Monitor.scala:659:79, :660:77]
wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_831 ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_831 ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire d_clr; // @[Monitor.scala:664:34]
wire d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46]
wire _T_877 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [1:0] _GEN_6 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [1:0] _GEN_7 = 2'h1 << _GEN_6; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_877 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35]
wire _T_846 = _T_966 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_846 & _d_clr_T[0]; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_846 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [30:0] _d_sizes_clr_T_5 = 31'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_846 ? _d_sizes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27]
wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}]
wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}]
wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire d_clr_1; // @[Monitor.scala:774:34]
wire d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_942 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_942 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35]
wire _T_924 = _T_966 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_924 & _d_clr_T_1[0]; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_924 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [30:0] _d_sizes_clr_T_11 = 31'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_924 ? _d_sizes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113]
wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}]
wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module BranchKillableQueue :
input clock : Clock
input reset : Reset
output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>}}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip flush : UInt<1>, empty : UInt<1>, count : UInt<4>}
cmem ram : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>} [15]
wire _valids_WIRE : UInt<1>[15]
connect _valids_WIRE[0], UInt<1>(0h0)
connect _valids_WIRE[1], UInt<1>(0h0)
connect _valids_WIRE[2], UInt<1>(0h0)
connect _valids_WIRE[3], UInt<1>(0h0)
connect _valids_WIRE[4], UInt<1>(0h0)
connect _valids_WIRE[5], UInt<1>(0h0)
connect _valids_WIRE[6], UInt<1>(0h0)
connect _valids_WIRE[7], UInt<1>(0h0)
connect _valids_WIRE[8], UInt<1>(0h0)
connect _valids_WIRE[9], UInt<1>(0h0)
connect _valids_WIRE[10], UInt<1>(0h0)
connect _valids_WIRE[11], UInt<1>(0h0)
connect _valids_WIRE[12], UInt<1>(0h0)
connect _valids_WIRE[13], UInt<1>(0h0)
connect _valids_WIRE[14], UInt<1>(0h0)
regreset valids : UInt<1>[15], clock, reset, _valids_WIRE
reg uops : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[15], clock
regreset enq_ptr_value : UInt<4>, clock, reset, UInt<4>(0h0)
regreset deq_ptr_value : UInt<4>, clock, reset, UInt<4>(0h0)
regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0)
node ptr_match = eq(enq_ptr_value, deq_ptr_value)
node _io_empty_T = eq(maybe_full, UInt<1>(0h0))
node _io_empty_T_1 = and(ptr_match, _io_empty_T)
connect io.empty, _io_empty_T_1
node full = and(ptr_match, maybe_full)
node _do_enq_T = and(io.enq.ready, io.enq.valid)
node _do_enq_T_1 = and(io.brupdate.b1.mispredict_mask, io.enq.bits.uop.br_mask)
node _do_enq_T_2 = neq(_do_enq_T_1, UInt<1>(0h0))
node _do_enq_T_3 = or(_do_enq_T_2, UInt<1>(0h0))
node _do_enq_T_4 = eq(_do_enq_T_3, UInt<1>(0h0))
node _do_enq_T_5 = and(_do_enq_T, _do_enq_T_4)
node _do_enq_T_6 = and(io.flush, io.enq.bits.uop.uses_ldq)
node _do_enq_T_7 = eq(_do_enq_T_6, UInt<1>(0h0))
node _do_enq_T_8 = and(_do_enq_T_5, _do_enq_T_7)
wire do_enq : UInt<1>
connect do_enq, _do_enq_T_8
node _do_deq_T = eq(valids[deq_ptr_value], UInt<1>(0h0))
node _do_deq_T_1 = or(io.deq.ready, _do_deq_T)
node _do_deq_T_2 = eq(io.empty, UInt<1>(0h0))
node _do_deq_T_3 = and(_do_deq_T_1, _do_deq_T_2)
wire do_deq : UInt<1>
connect do_deq, _do_deq_T_3
node _valids_0_T = and(io.brupdate.b1.mispredict_mask, uops[0].br_mask)
node _valids_0_T_1 = neq(_valids_0_T, UInt<1>(0h0))
node _valids_0_T_2 = or(_valids_0_T_1, UInt<1>(0h0))
node _valids_0_T_3 = eq(_valids_0_T_2, UInt<1>(0h0))
node _valids_0_T_4 = and(valids[0], _valids_0_T_3)
node _valids_0_T_5 = and(io.flush, uops[0].uses_ldq)
node _valids_0_T_6 = eq(_valids_0_T_5, UInt<1>(0h0))
node _valids_0_T_7 = and(_valids_0_T_4, _valids_0_T_6)
connect valids[0], _valids_0_T_7
when valids[0] :
node _uops_0_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_0_br_mask_T_1 = and(uops[0].br_mask, _uops_0_br_mask_T)
connect uops[0].br_mask, _uops_0_br_mask_T_1
node _valids_1_T = and(io.brupdate.b1.mispredict_mask, uops[1].br_mask)
node _valids_1_T_1 = neq(_valids_1_T, UInt<1>(0h0))
node _valids_1_T_2 = or(_valids_1_T_1, UInt<1>(0h0))
node _valids_1_T_3 = eq(_valids_1_T_2, UInt<1>(0h0))
node _valids_1_T_4 = and(valids[1], _valids_1_T_3)
node _valids_1_T_5 = and(io.flush, uops[1].uses_ldq)
node _valids_1_T_6 = eq(_valids_1_T_5, UInt<1>(0h0))
node _valids_1_T_7 = and(_valids_1_T_4, _valids_1_T_6)
connect valids[1], _valids_1_T_7
when valids[1] :
node _uops_1_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_1_br_mask_T_1 = and(uops[1].br_mask, _uops_1_br_mask_T)
connect uops[1].br_mask, _uops_1_br_mask_T_1
node _valids_2_T = and(io.brupdate.b1.mispredict_mask, uops[2].br_mask)
node _valids_2_T_1 = neq(_valids_2_T, UInt<1>(0h0))
node _valids_2_T_2 = or(_valids_2_T_1, UInt<1>(0h0))
node _valids_2_T_3 = eq(_valids_2_T_2, UInt<1>(0h0))
node _valids_2_T_4 = and(valids[2], _valids_2_T_3)
node _valids_2_T_5 = and(io.flush, uops[2].uses_ldq)
node _valids_2_T_6 = eq(_valids_2_T_5, UInt<1>(0h0))
node _valids_2_T_7 = and(_valids_2_T_4, _valids_2_T_6)
connect valids[2], _valids_2_T_7
when valids[2] :
node _uops_2_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_2_br_mask_T_1 = and(uops[2].br_mask, _uops_2_br_mask_T)
connect uops[2].br_mask, _uops_2_br_mask_T_1
node _valids_3_T = and(io.brupdate.b1.mispredict_mask, uops[3].br_mask)
node _valids_3_T_1 = neq(_valids_3_T, UInt<1>(0h0))
node _valids_3_T_2 = or(_valids_3_T_1, UInt<1>(0h0))
node _valids_3_T_3 = eq(_valids_3_T_2, UInt<1>(0h0))
node _valids_3_T_4 = and(valids[3], _valids_3_T_3)
node _valids_3_T_5 = and(io.flush, uops[3].uses_ldq)
node _valids_3_T_6 = eq(_valids_3_T_5, UInt<1>(0h0))
node _valids_3_T_7 = and(_valids_3_T_4, _valids_3_T_6)
connect valids[3], _valids_3_T_7
when valids[3] :
node _uops_3_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_3_br_mask_T_1 = and(uops[3].br_mask, _uops_3_br_mask_T)
connect uops[3].br_mask, _uops_3_br_mask_T_1
node _valids_4_T = and(io.brupdate.b1.mispredict_mask, uops[4].br_mask)
node _valids_4_T_1 = neq(_valids_4_T, UInt<1>(0h0))
node _valids_4_T_2 = or(_valids_4_T_1, UInt<1>(0h0))
node _valids_4_T_3 = eq(_valids_4_T_2, UInt<1>(0h0))
node _valids_4_T_4 = and(valids[4], _valids_4_T_3)
node _valids_4_T_5 = and(io.flush, uops[4].uses_ldq)
node _valids_4_T_6 = eq(_valids_4_T_5, UInt<1>(0h0))
node _valids_4_T_7 = and(_valids_4_T_4, _valids_4_T_6)
connect valids[4], _valids_4_T_7
when valids[4] :
node _uops_4_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_4_br_mask_T_1 = and(uops[4].br_mask, _uops_4_br_mask_T)
connect uops[4].br_mask, _uops_4_br_mask_T_1
node _valids_5_T = and(io.brupdate.b1.mispredict_mask, uops[5].br_mask)
node _valids_5_T_1 = neq(_valids_5_T, UInt<1>(0h0))
node _valids_5_T_2 = or(_valids_5_T_1, UInt<1>(0h0))
node _valids_5_T_3 = eq(_valids_5_T_2, UInt<1>(0h0))
node _valids_5_T_4 = and(valids[5], _valids_5_T_3)
node _valids_5_T_5 = and(io.flush, uops[5].uses_ldq)
node _valids_5_T_6 = eq(_valids_5_T_5, UInt<1>(0h0))
node _valids_5_T_7 = and(_valids_5_T_4, _valids_5_T_6)
connect valids[5], _valids_5_T_7
when valids[5] :
node _uops_5_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_5_br_mask_T_1 = and(uops[5].br_mask, _uops_5_br_mask_T)
connect uops[5].br_mask, _uops_5_br_mask_T_1
node _valids_6_T = and(io.brupdate.b1.mispredict_mask, uops[6].br_mask)
node _valids_6_T_1 = neq(_valids_6_T, UInt<1>(0h0))
node _valids_6_T_2 = or(_valids_6_T_1, UInt<1>(0h0))
node _valids_6_T_3 = eq(_valids_6_T_2, UInt<1>(0h0))
node _valids_6_T_4 = and(valids[6], _valids_6_T_3)
node _valids_6_T_5 = and(io.flush, uops[6].uses_ldq)
node _valids_6_T_6 = eq(_valids_6_T_5, UInt<1>(0h0))
node _valids_6_T_7 = and(_valids_6_T_4, _valids_6_T_6)
connect valids[6], _valids_6_T_7
when valids[6] :
node _uops_6_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_6_br_mask_T_1 = and(uops[6].br_mask, _uops_6_br_mask_T)
connect uops[6].br_mask, _uops_6_br_mask_T_1
node _valids_7_T = and(io.brupdate.b1.mispredict_mask, uops[7].br_mask)
node _valids_7_T_1 = neq(_valids_7_T, UInt<1>(0h0))
node _valids_7_T_2 = or(_valids_7_T_1, UInt<1>(0h0))
node _valids_7_T_3 = eq(_valids_7_T_2, UInt<1>(0h0))
node _valids_7_T_4 = and(valids[7], _valids_7_T_3)
node _valids_7_T_5 = and(io.flush, uops[7].uses_ldq)
node _valids_7_T_6 = eq(_valids_7_T_5, UInt<1>(0h0))
node _valids_7_T_7 = and(_valids_7_T_4, _valids_7_T_6)
connect valids[7], _valids_7_T_7
when valids[7] :
node _uops_7_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_7_br_mask_T_1 = and(uops[7].br_mask, _uops_7_br_mask_T)
connect uops[7].br_mask, _uops_7_br_mask_T_1
node _valids_8_T = and(io.brupdate.b1.mispredict_mask, uops[8].br_mask)
node _valids_8_T_1 = neq(_valids_8_T, UInt<1>(0h0))
node _valids_8_T_2 = or(_valids_8_T_1, UInt<1>(0h0))
node _valids_8_T_3 = eq(_valids_8_T_2, UInt<1>(0h0))
node _valids_8_T_4 = and(valids[8], _valids_8_T_3)
node _valids_8_T_5 = and(io.flush, uops[8].uses_ldq)
node _valids_8_T_6 = eq(_valids_8_T_5, UInt<1>(0h0))
node _valids_8_T_7 = and(_valids_8_T_4, _valids_8_T_6)
connect valids[8], _valids_8_T_7
when valids[8] :
node _uops_8_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_8_br_mask_T_1 = and(uops[8].br_mask, _uops_8_br_mask_T)
connect uops[8].br_mask, _uops_8_br_mask_T_1
node _valids_9_T = and(io.brupdate.b1.mispredict_mask, uops[9].br_mask)
node _valids_9_T_1 = neq(_valids_9_T, UInt<1>(0h0))
node _valids_9_T_2 = or(_valids_9_T_1, UInt<1>(0h0))
node _valids_9_T_3 = eq(_valids_9_T_2, UInt<1>(0h0))
node _valids_9_T_4 = and(valids[9], _valids_9_T_3)
node _valids_9_T_5 = and(io.flush, uops[9].uses_ldq)
node _valids_9_T_6 = eq(_valids_9_T_5, UInt<1>(0h0))
node _valids_9_T_7 = and(_valids_9_T_4, _valids_9_T_6)
connect valids[9], _valids_9_T_7
when valids[9] :
node _uops_9_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_9_br_mask_T_1 = and(uops[9].br_mask, _uops_9_br_mask_T)
connect uops[9].br_mask, _uops_9_br_mask_T_1
node _valids_10_T = and(io.brupdate.b1.mispredict_mask, uops[10].br_mask)
node _valids_10_T_1 = neq(_valids_10_T, UInt<1>(0h0))
node _valids_10_T_2 = or(_valids_10_T_1, UInt<1>(0h0))
node _valids_10_T_3 = eq(_valids_10_T_2, UInt<1>(0h0))
node _valids_10_T_4 = and(valids[10], _valids_10_T_3)
node _valids_10_T_5 = and(io.flush, uops[10].uses_ldq)
node _valids_10_T_6 = eq(_valids_10_T_5, UInt<1>(0h0))
node _valids_10_T_7 = and(_valids_10_T_4, _valids_10_T_6)
connect valids[10], _valids_10_T_7
when valids[10] :
node _uops_10_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_10_br_mask_T_1 = and(uops[10].br_mask, _uops_10_br_mask_T)
connect uops[10].br_mask, _uops_10_br_mask_T_1
node _valids_11_T = and(io.brupdate.b1.mispredict_mask, uops[11].br_mask)
node _valids_11_T_1 = neq(_valids_11_T, UInt<1>(0h0))
node _valids_11_T_2 = or(_valids_11_T_1, UInt<1>(0h0))
node _valids_11_T_3 = eq(_valids_11_T_2, UInt<1>(0h0))
node _valids_11_T_4 = and(valids[11], _valids_11_T_3)
node _valids_11_T_5 = and(io.flush, uops[11].uses_ldq)
node _valids_11_T_6 = eq(_valids_11_T_5, UInt<1>(0h0))
node _valids_11_T_7 = and(_valids_11_T_4, _valids_11_T_6)
connect valids[11], _valids_11_T_7
when valids[11] :
node _uops_11_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_11_br_mask_T_1 = and(uops[11].br_mask, _uops_11_br_mask_T)
connect uops[11].br_mask, _uops_11_br_mask_T_1
node _valids_12_T = and(io.brupdate.b1.mispredict_mask, uops[12].br_mask)
node _valids_12_T_1 = neq(_valids_12_T, UInt<1>(0h0))
node _valids_12_T_2 = or(_valids_12_T_1, UInt<1>(0h0))
node _valids_12_T_3 = eq(_valids_12_T_2, UInt<1>(0h0))
node _valids_12_T_4 = and(valids[12], _valids_12_T_3)
node _valids_12_T_5 = and(io.flush, uops[12].uses_ldq)
node _valids_12_T_6 = eq(_valids_12_T_5, UInt<1>(0h0))
node _valids_12_T_7 = and(_valids_12_T_4, _valids_12_T_6)
connect valids[12], _valids_12_T_7
when valids[12] :
node _uops_12_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_12_br_mask_T_1 = and(uops[12].br_mask, _uops_12_br_mask_T)
connect uops[12].br_mask, _uops_12_br_mask_T_1
node _valids_13_T = and(io.brupdate.b1.mispredict_mask, uops[13].br_mask)
node _valids_13_T_1 = neq(_valids_13_T, UInt<1>(0h0))
node _valids_13_T_2 = or(_valids_13_T_1, UInt<1>(0h0))
node _valids_13_T_3 = eq(_valids_13_T_2, UInt<1>(0h0))
node _valids_13_T_4 = and(valids[13], _valids_13_T_3)
node _valids_13_T_5 = and(io.flush, uops[13].uses_ldq)
node _valids_13_T_6 = eq(_valids_13_T_5, UInt<1>(0h0))
node _valids_13_T_7 = and(_valids_13_T_4, _valids_13_T_6)
connect valids[13], _valids_13_T_7
when valids[13] :
node _uops_13_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_13_br_mask_T_1 = and(uops[13].br_mask, _uops_13_br_mask_T)
connect uops[13].br_mask, _uops_13_br_mask_T_1
node _valids_14_T = and(io.brupdate.b1.mispredict_mask, uops[14].br_mask)
node _valids_14_T_1 = neq(_valids_14_T, UInt<1>(0h0))
node _valids_14_T_2 = or(_valids_14_T_1, UInt<1>(0h0))
node _valids_14_T_3 = eq(_valids_14_T_2, UInt<1>(0h0))
node _valids_14_T_4 = and(valids[14], _valids_14_T_3)
node _valids_14_T_5 = and(io.flush, uops[14].uses_ldq)
node _valids_14_T_6 = eq(_valids_14_T_5, UInt<1>(0h0))
node _valids_14_T_7 = and(_valids_14_T_4, _valids_14_T_6)
connect valids[14], _valids_14_T_7
when valids[14] :
node _uops_14_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_14_br_mask_T_1 = and(uops[14].br_mask, _uops_14_br_mask_T)
connect uops[14].br_mask, _uops_14_br_mask_T_1
when do_enq :
infer mport MPORT = ram[enq_ptr_value], clock
connect MPORT, io.enq.bits
connect valids[enq_ptr_value], UInt<1>(0h1)
connect uops[enq_ptr_value], io.enq.bits.uop
node _uops_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_br_mask_T_1 = and(io.enq.bits.uop.br_mask, _uops_br_mask_T)
connect uops[enq_ptr_value].br_mask, _uops_br_mask_T_1
node wrap = eq(enq_ptr_value, UInt<4>(0he))
node _value_T = add(enq_ptr_value, UInt<1>(0h1))
node _value_T_1 = tail(_value_T, 1)
connect enq_ptr_value, _value_T_1
when wrap :
connect enq_ptr_value, UInt<1>(0h0)
when do_deq :
connect valids[deq_ptr_value], UInt<1>(0h0)
node wrap_1 = eq(deq_ptr_value, UInt<4>(0he))
node _value_T_2 = add(deq_ptr_value, UInt<1>(0h1))
node _value_T_3 = tail(_value_T_2, 1)
connect deq_ptr_value, _value_T_3
when wrap_1 :
connect deq_ptr_value, UInt<1>(0h0)
node _T = neq(do_enq, do_deq)
when _T :
connect maybe_full, do_enq
node _io_enq_ready_T = eq(full, UInt<1>(0h0))
connect io.enq.ready, _io_enq_ready_T
wire out : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>}
infer mport out_MPORT = ram[deq_ptr_value], clock
connect out, out_MPORT
connect out.uop, uops[deq_ptr_value]
node _io_deq_valid_T = eq(io.empty, UInt<1>(0h0))
node _io_deq_valid_T_1 = and(_io_deq_valid_T, valids[deq_ptr_value])
connect io.deq.valid, _io_deq_valid_T_1
connect io.deq.bits, out
node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value)
node ptr_diff = tail(_ptr_diff_T, 1)
node _io_count_T = mux(maybe_full, UInt<4>(0hf), UInt<1>(0h0))
node _io_count_T_1 = gt(deq_ptr_value, enq_ptr_value)
node _io_count_T_2 = add(UInt<4>(0hf), ptr_diff)
node _io_count_T_3 = tail(_io_count_T_2, 1)
node _io_count_T_4 = mux(_io_count_T_1, _io_count_T_3, ptr_diff)
node _io_count_T_5 = mux(ptr_match, _io_count_T, _io_count_T_4)
connect io.count, _io_count_T_5 | module BranchKillableQueue( // @[util.scala:458:7]
input clock, // @[util.scala:458:7]
input reset, // @[util.scala:458:7]
output io_enq_ready, // @[util.scala:463:14]
input io_enq_valid, // @[util.scala:463:14]
input [31:0] io_enq_bits_uop_inst, // @[util.scala:463:14]
input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:463:14]
input io_enq_bits_uop_is_rvc, // @[util.scala:463:14]
input [39:0] io_enq_bits_uop_debug_pc, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_0, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_1, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_2, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_3, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_0, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_1, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_2, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_3, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_4, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_5, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_6, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_7, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_8, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_9, // @[util.scala:463:14]
input io_enq_bits_uop_iw_issued, // @[util.scala:463:14]
input io_enq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14]
input io_enq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_dis_col_sel, // @[util.scala:463:14]
input [15:0] io_enq_bits_uop_br_mask, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_br_tag, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_br_type, // @[util.scala:463:14]
input io_enq_bits_uop_is_sfb, // @[util.scala:463:14]
input io_enq_bits_uop_is_fence, // @[util.scala:463:14]
input io_enq_bits_uop_is_fencei, // @[util.scala:463:14]
input io_enq_bits_uop_is_sfence, // @[util.scala:463:14]
input io_enq_bits_uop_is_amo, // @[util.scala:463:14]
input io_enq_bits_uop_is_eret, // @[util.scala:463:14]
input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14]
input io_enq_bits_uop_is_rocc, // @[util.scala:463:14]
input io_enq_bits_uop_is_mov, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_ftq_idx, // @[util.scala:463:14]
input io_enq_bits_uop_edge_inst, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:463:14]
input io_enq_bits_uop_taken, // @[util.scala:463:14]
input io_enq_bits_uop_imm_rename, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_imm_sel, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_pimm, // @[util.scala:463:14]
input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_op1_sel, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_op2_sel, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_div, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_rob_idx, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_ldq_idx, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_stq_idx, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_pdst, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_prs1, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_prs2, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_prs3, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_ppred, // @[util.scala:463:14]
input io_enq_bits_uop_prs1_busy, // @[util.scala:463:14]
input io_enq_bits_uop_prs2_busy, // @[util.scala:463:14]
input io_enq_bits_uop_prs3_busy, // @[util.scala:463:14]
input io_enq_bits_uop_ppred_busy, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_stale_pdst, // @[util.scala:463:14]
input io_enq_bits_uop_exception, // @[util.scala:463:14]
input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:463:14]
input io_enq_bits_uop_mem_signed, // @[util.scala:463:14]
input io_enq_bits_uop_uses_ldq, // @[util.scala:463:14]
input io_enq_bits_uop_uses_stq, // @[util.scala:463:14]
input io_enq_bits_uop_is_unique, // @[util.scala:463:14]
input io_enq_bits_uop_flush_on_commit, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_csr_cmd, // @[util.scala:463:14]
input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_ldst, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:463:14]
input io_enq_bits_uop_frs3_en, // @[util.scala:463:14]
input io_enq_bits_uop_fcn_dw, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_fcn_op, // @[util.scala:463:14]
input io_enq_bits_uop_fp_val, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_fp_rm, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_fp_typ, // @[util.scala:463:14]
input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:463:14]
input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:463:14]
input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:463:14]
input io_enq_bits_uop_bp_debug_if, // @[util.scala:463:14]
input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:463:14]
input [39:0] io_enq_bits_addr, // @[util.scala:463:14]
input [63:0] io_enq_bits_data, // @[util.scala:463:14]
input io_enq_bits_is_hella, // @[util.scala:463:14]
input io_enq_bits_tag_match, // @[util.scala:463:14]
input [1:0] io_enq_bits_old_meta_coh_state, // @[util.scala:463:14]
input [19:0] io_enq_bits_old_meta_tag, // @[util.scala:463:14]
input [7:0] io_enq_bits_way_en, // @[util.scala:463:14]
input [4:0] io_enq_bits_sdq_id, // @[util.scala:463:14]
input io_deq_ready, // @[util.scala:463:14]
output io_deq_valid, // @[util.scala:463:14]
output [31:0] io_deq_bits_uop_inst, // @[util.scala:463:14]
output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:463:14]
output io_deq_bits_uop_is_rvc, // @[util.scala:463:14]
output [39:0] io_deq_bits_uop_debug_pc, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_0, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_1, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_2, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_3, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_0, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_1, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_2, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_3, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_4, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_5, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_6, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_7, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_8, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_9, // @[util.scala:463:14]
output io_deq_bits_uop_iw_issued, // @[util.scala:463:14]
output io_deq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14]
output io_deq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_dis_col_sel, // @[util.scala:463:14]
output [15:0] io_deq_bits_uop_br_mask, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_br_tag, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_br_type, // @[util.scala:463:14]
output io_deq_bits_uop_is_sfb, // @[util.scala:463:14]
output io_deq_bits_uop_is_fence, // @[util.scala:463:14]
output io_deq_bits_uop_is_fencei, // @[util.scala:463:14]
output io_deq_bits_uop_is_sfence, // @[util.scala:463:14]
output io_deq_bits_uop_is_amo, // @[util.scala:463:14]
output io_deq_bits_uop_is_eret, // @[util.scala:463:14]
output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14]
output io_deq_bits_uop_is_rocc, // @[util.scala:463:14]
output io_deq_bits_uop_is_mov, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_ftq_idx, // @[util.scala:463:14]
output io_deq_bits_uop_edge_inst, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:463:14]
output io_deq_bits_uop_taken, // @[util.scala:463:14]
output io_deq_bits_uop_imm_rename, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_imm_sel, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_pimm, // @[util.scala:463:14]
output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_op1_sel, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_op2_sel, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_div, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_rob_idx, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_ldq_idx, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_stq_idx, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_pdst, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_prs1, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_prs2, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_prs3, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_ppred, // @[util.scala:463:14]
output io_deq_bits_uop_prs1_busy, // @[util.scala:463:14]
output io_deq_bits_uop_prs2_busy, // @[util.scala:463:14]
output io_deq_bits_uop_prs3_busy, // @[util.scala:463:14]
output io_deq_bits_uop_ppred_busy, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_stale_pdst, // @[util.scala:463:14]
output io_deq_bits_uop_exception, // @[util.scala:463:14]
output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:463:14]
output io_deq_bits_uop_mem_signed, // @[util.scala:463:14]
output io_deq_bits_uop_uses_ldq, // @[util.scala:463:14]
output io_deq_bits_uop_uses_stq, // @[util.scala:463:14]
output io_deq_bits_uop_is_unique, // @[util.scala:463:14]
output io_deq_bits_uop_flush_on_commit, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_csr_cmd, // @[util.scala:463:14]
output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_ldst, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:463:14]
output io_deq_bits_uop_frs3_en, // @[util.scala:463:14]
output io_deq_bits_uop_fcn_dw, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_fcn_op, // @[util.scala:463:14]
output io_deq_bits_uop_fp_val, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_fp_rm, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_fp_typ, // @[util.scala:463:14]
output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:463:14]
output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:463:14]
output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:463:14]
output io_deq_bits_uop_bp_debug_if, // @[util.scala:463:14]
output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:463:14]
output [39:0] io_deq_bits_addr, // @[util.scala:463:14]
output [63:0] io_deq_bits_data, // @[util.scala:463:14]
output io_deq_bits_is_hella, // @[util.scala:463:14]
output io_deq_bits_tag_match, // @[util.scala:463:14]
output [1:0] io_deq_bits_old_meta_coh_state, // @[util.scala:463:14]
output [19:0] io_deq_bits_old_meta_tag, // @[util.scala:463:14]
output [7:0] io_deq_bits_way_en, // @[util.scala:463:14]
output [4:0] io_deq_bits_sdq_id, // @[util.scala:463:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[util.scala:463:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[util.scala:463:14]
input [31:0] io_brupdate_b2_uop_inst, // @[util.scala:463:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_rvc, // @[util.scala:463:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[util.scala:463:14]
input io_brupdate_b2_uop_iq_type_0, // @[util.scala:463:14]
input io_brupdate_b2_uop_iq_type_1, // @[util.scala:463:14]
input io_brupdate_b2_uop_iq_type_2, // @[util.scala:463:14]
input io_brupdate_b2_uop_iq_type_3, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_0, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_1, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_2, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_3, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_4, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_5, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_6, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_7, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_8, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_9, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_issued, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_issued_partial_agen, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[util.scala:463:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[util.scala:463:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[util.scala:463:14]
input [3:0] io_brupdate_b2_uop_br_type, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_sfb, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_fence, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_fencei, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_sfence, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_amo, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_eret, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_rocc, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_mov, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[util.scala:463:14]
input io_brupdate_b2_uop_edge_inst, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[util.scala:463:14]
input io_brupdate_b2_uop_taken, // @[util.scala:463:14]
input io_brupdate_b2_uop_imm_rename, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_imm_sel, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_pimm, // @[util.scala:463:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_op1_sel, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_op2_sel, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_ldst, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_wen, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_ren1, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_ren2, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_ren3, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_swap12, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_swap23, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_fromint, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_toint, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_fma, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_div, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_wflags, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_vec, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[util.scala:463:14]
input io_brupdate_b2_uop_prs1_busy, // @[util.scala:463:14]
input io_brupdate_b2_uop_prs2_busy, // @[util.scala:463:14]
input io_brupdate_b2_uop_prs3_busy, // @[util.scala:463:14]
input io_brupdate_b2_uop_ppred_busy, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[util.scala:463:14]
input io_brupdate_b2_uop_exception, // @[util.scala:463:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[util.scala:463:14]
input io_brupdate_b2_uop_mem_signed, // @[util.scala:463:14]
input io_brupdate_b2_uop_uses_ldq, // @[util.scala:463:14]
input io_brupdate_b2_uop_uses_stq, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_unique, // @[util.scala:463:14]
input io_brupdate_b2_uop_flush_on_commit, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_csr_cmd, // @[util.scala:463:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[util.scala:463:14]
input io_brupdate_b2_uop_frs3_en, // @[util.scala:463:14]
input io_brupdate_b2_uop_fcn_dw, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_fcn_op, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_val, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_fp_rm, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_fp_typ, // @[util.scala:463:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[util.scala:463:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[util.scala:463:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[util.scala:463:14]
input io_brupdate_b2_uop_bp_debug_if, // @[util.scala:463:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[util.scala:463:14]
input io_brupdate_b2_mispredict, // @[util.scala:463:14]
input io_brupdate_b2_taken, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_cfi_type, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_pc_sel, // @[util.scala:463:14]
input [39:0] io_brupdate_b2_jalr_target, // @[util.scala:463:14]
input [20:0] io_brupdate_b2_target_offset, // @[util.scala:463:14]
input io_flush, // @[util.scala:463:14]
output io_empty, // @[util.scala:463:14]
output [3:0] io_count // @[util.scala:463:14]
);
wire [140:0] _ram_ext_R0_data; // @[util.scala:503:22]
wire io_enq_valid_0 = io_enq_valid; // @[util.scala:458:7]
wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:458:7]
wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:458:7]
wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:458:7]
wire [39:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_0_0 = io_enq_bits_uop_iq_type_0; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_1_0 = io_enq_bits_uop_iq_type_1; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_2_0 = io_enq_bits_uop_iq_type_2; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_3_0 = io_enq_bits_uop_iq_type_3; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_0_0 = io_enq_bits_uop_fu_code_0; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_1_0 = io_enq_bits_uop_fu_code_1; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_2_0 = io_enq_bits_uop_fu_code_2; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_3_0 = io_enq_bits_uop_fu_code_3; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_4_0 = io_enq_bits_uop_fu_code_4; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_5_0 = io_enq_bits_uop_fu_code_5; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_6_0 = io_enq_bits_uop_fu_code_6; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_7_0 = io_enq_bits_uop_fu_code_7; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_8_0 = io_enq_bits_uop_fu_code_8; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_9_0 = io_enq_bits_uop_fu_code_9; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_issued_0 = io_enq_bits_uop_iw_issued; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_issued_partial_agen_0 = io_enq_bits_uop_iw_issued_partial_agen; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_issued_partial_dgen_0 = io_enq_bits_uop_iw_issued_partial_dgen; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_iw_p1_speculative_child_0 = io_enq_bits_uop_iw_p1_speculative_child; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_iw_p2_speculative_child_0 = io_enq_bits_uop_iw_p2_speculative_child; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p1_bypass_hint_0 = io_enq_bits_uop_iw_p1_bypass_hint; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p2_bypass_hint_0 = io_enq_bits_uop_iw_p2_bypass_hint; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p3_bypass_hint_0 = io_enq_bits_uop_iw_p3_bypass_hint; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_dis_col_sel_0 = io_enq_bits_uop_dis_col_sel; // @[util.scala:458:7]
wire [15:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_br_type_0 = io_enq_bits_uop_br_type; // @[util.scala:458:7]
wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:458:7]
wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:458:7]
wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:458:7]
wire io_enq_bits_uop_is_sfence_0 = io_enq_bits_uop_is_sfence; // @[util.scala:458:7]
wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:458:7]
wire io_enq_bits_uop_is_eret_0 = io_enq_bits_uop_is_eret; // @[util.scala:458:7]
wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:458:7]
wire io_enq_bits_uop_is_rocc_0 = io_enq_bits_uop_is_rocc; // @[util.scala:458:7]
wire io_enq_bits_uop_is_mov_0 = io_enq_bits_uop_is_mov; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:458:7]
wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:458:7]
wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:458:7]
wire io_enq_bits_uop_imm_rename_0 = io_enq_bits_uop_imm_rename; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_imm_sel_0 = io_enq_bits_uop_imm_sel; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_pimm_0 = io_enq_bits_uop_pimm; // @[util.scala:458:7]
wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_op1_sel_0 = io_enq_bits_uop_op1_sel; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_op2_sel_0 = io_enq_bits_uop_op2_sel; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ldst_0 = io_enq_bits_uop_fp_ctrl_ldst; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_wen_0 = io_enq_bits_uop_fp_ctrl_wen; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ren1_0 = io_enq_bits_uop_fp_ctrl_ren1; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ren2_0 = io_enq_bits_uop_fp_ctrl_ren2; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ren3_0 = io_enq_bits_uop_fp_ctrl_ren3; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_swap12_0 = io_enq_bits_uop_fp_ctrl_swap12; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_swap23_0 = io_enq_bits_uop_fp_ctrl_swap23; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn_0 = io_enq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut_0 = io_enq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_fromint_0 = io_enq_bits_uop_fp_ctrl_fromint; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_toint_0 = io_enq_bits_uop_fp_ctrl_toint; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_fastpipe_0 = io_enq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_fma_0 = io_enq_bits_uop_fp_ctrl_fma; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_div_0 = io_enq_bits_uop_fp_ctrl_div; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_sqrt_0 = io_enq_bits_uop_fp_ctrl_sqrt; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_wflags_0 = io_enq_bits_uop_fp_ctrl_wflags; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_vec_0 = io_enq_bits_uop_fp_ctrl_vec; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:458:7]
wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:458:7]
wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:458:7]
wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:458:7]
wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:458:7]
wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:458:7]
wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:458:7]
wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:458:7]
wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:458:7]
wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:458:7]
wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:458:7]
wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_csr_cmd_0 = io_enq_bits_uop_csr_cmd; // @[util.scala:458:7]
wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:458:7]
wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:458:7]
wire io_enq_bits_uop_fcn_dw_0 = io_enq_bits_uop_fcn_dw; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_fcn_op_0 = io_enq_bits_uop_fcn_op; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_fp_rm_0 = io_enq_bits_uop_fp_rm; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_fp_typ_0 = io_enq_bits_uop_fp_typ; // @[util.scala:458:7]
wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:458:7]
wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:458:7]
wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:458:7]
wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:458:7]
wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:458:7]
wire [39:0] io_enq_bits_addr_0 = io_enq_bits_addr; // @[util.scala:458:7]
wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:458:7]
wire io_enq_bits_is_hella_0 = io_enq_bits_is_hella; // @[util.scala:458:7]
wire io_enq_bits_tag_match_0 = io_enq_bits_tag_match; // @[util.scala:458:7]
wire [1:0] io_enq_bits_old_meta_coh_state_0 = io_enq_bits_old_meta_coh_state; // @[util.scala:458:7]
wire [19:0] io_enq_bits_old_meta_tag_0 = io_enq_bits_old_meta_tag; // @[util.scala:458:7]
wire [7:0] io_enq_bits_way_en_0 = io_enq_bits_way_en; // @[util.scala:458:7]
wire [4:0] io_enq_bits_sdq_id_0 = io_enq_bits_sdq_id; // @[util.scala:458:7]
wire io_deq_ready_0 = io_deq_ready; // @[util.scala:458:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[util.scala:458:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[util.scala:458:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[util.scala:458:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[util.scala:458:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[util.scala:458:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[util.scala:458:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[util.scala:458:7]
wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[util.scala:458:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[util.scala:458:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[util.scala:458:7]
wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[util.scala:458:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[util.scala:458:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[util.scala:458:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[util.scala:458:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[util.scala:458:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[util.scala:458:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[util.scala:458:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[util.scala:458:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[util.scala:458:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[util.scala:458:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[util.scala:458:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[util.scala:458:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[util.scala:458:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[util.scala:458:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[util.scala:458:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[util.scala:458:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[util.scala:458:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[util.scala:458:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[util.scala:458:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[util.scala:458:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[util.scala:458:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[util.scala:458:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[util.scala:458:7]
wire io_flush_0 = io_flush; // @[util.scala:458:7]
wire _valids_WIRE_0 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_1 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_2 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_3 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_4 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_5 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_6 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_7 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_8 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_9 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_10 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_11 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_12 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_13 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_14 = 1'h0; // @[util.scala:504:34]
wire _io_enq_ready_T; // @[util.scala:543:21]
wire _io_deq_valid_T_1; // @[util.scala:548:42]
wire [31:0] out_uop_inst; // @[util.scala:545:19]
wire [31:0] out_uop_debug_inst; // @[util.scala:545:19]
wire out_uop_is_rvc; // @[util.scala:545:19]
wire [39:0] out_uop_debug_pc; // @[util.scala:545:19]
wire out_uop_iq_type_0; // @[util.scala:545:19]
wire out_uop_iq_type_1; // @[util.scala:545:19]
wire out_uop_iq_type_2; // @[util.scala:545:19]
wire out_uop_iq_type_3; // @[util.scala:545:19]
wire out_uop_fu_code_0; // @[util.scala:545:19]
wire out_uop_fu_code_1; // @[util.scala:545:19]
wire out_uop_fu_code_2; // @[util.scala:545:19]
wire out_uop_fu_code_3; // @[util.scala:545:19]
wire out_uop_fu_code_4; // @[util.scala:545:19]
wire out_uop_fu_code_5; // @[util.scala:545:19]
wire out_uop_fu_code_6; // @[util.scala:545:19]
wire out_uop_fu_code_7; // @[util.scala:545:19]
wire out_uop_fu_code_8; // @[util.scala:545:19]
wire out_uop_fu_code_9; // @[util.scala:545:19]
wire out_uop_iw_issued; // @[util.scala:545:19]
wire out_uop_iw_issued_partial_agen; // @[util.scala:545:19]
wire out_uop_iw_issued_partial_dgen; // @[util.scala:545:19]
wire [2:0] out_uop_iw_p1_speculative_child; // @[util.scala:545:19]
wire [2:0] out_uop_iw_p2_speculative_child; // @[util.scala:545:19]
wire out_uop_iw_p1_bypass_hint; // @[util.scala:545:19]
wire out_uop_iw_p2_bypass_hint; // @[util.scala:545:19]
wire out_uop_iw_p3_bypass_hint; // @[util.scala:545:19]
wire [2:0] out_uop_dis_col_sel; // @[util.scala:545:19]
wire [15:0] out_uop_br_mask; // @[util.scala:545:19]
wire [3:0] out_uop_br_tag; // @[util.scala:545:19]
wire [3:0] out_uop_br_type; // @[util.scala:545:19]
wire out_uop_is_sfb; // @[util.scala:545:19]
wire out_uop_is_fence; // @[util.scala:545:19]
wire out_uop_is_fencei; // @[util.scala:545:19]
wire out_uop_is_sfence; // @[util.scala:545:19]
wire out_uop_is_amo; // @[util.scala:545:19]
wire out_uop_is_eret; // @[util.scala:545:19]
wire out_uop_is_sys_pc2epc; // @[util.scala:545:19]
wire out_uop_is_rocc; // @[util.scala:545:19]
wire out_uop_is_mov; // @[util.scala:545:19]
wire [4:0] out_uop_ftq_idx; // @[util.scala:545:19]
wire out_uop_edge_inst; // @[util.scala:545:19]
wire [5:0] out_uop_pc_lob; // @[util.scala:545:19]
wire out_uop_taken; // @[util.scala:545:19]
wire out_uop_imm_rename; // @[util.scala:545:19]
wire [2:0] out_uop_imm_sel; // @[util.scala:545:19]
wire [4:0] out_uop_pimm; // @[util.scala:545:19]
wire [19:0] out_uop_imm_packed; // @[util.scala:545:19]
wire [1:0] out_uop_op1_sel; // @[util.scala:545:19]
wire [2:0] out_uop_op2_sel; // @[util.scala:545:19]
wire out_uop_fp_ctrl_ldst; // @[util.scala:545:19]
wire out_uop_fp_ctrl_wen; // @[util.scala:545:19]
wire out_uop_fp_ctrl_ren1; // @[util.scala:545:19]
wire out_uop_fp_ctrl_ren2; // @[util.scala:545:19]
wire out_uop_fp_ctrl_ren3; // @[util.scala:545:19]
wire out_uop_fp_ctrl_swap12; // @[util.scala:545:19]
wire out_uop_fp_ctrl_swap23; // @[util.scala:545:19]
wire [1:0] out_uop_fp_ctrl_typeTagIn; // @[util.scala:545:19]
wire [1:0] out_uop_fp_ctrl_typeTagOut; // @[util.scala:545:19]
wire out_uop_fp_ctrl_fromint; // @[util.scala:545:19]
wire out_uop_fp_ctrl_toint; // @[util.scala:545:19]
wire out_uop_fp_ctrl_fastpipe; // @[util.scala:545:19]
wire out_uop_fp_ctrl_fma; // @[util.scala:545:19]
wire out_uop_fp_ctrl_div; // @[util.scala:545:19]
wire out_uop_fp_ctrl_sqrt; // @[util.scala:545:19]
wire out_uop_fp_ctrl_wflags; // @[util.scala:545:19]
wire out_uop_fp_ctrl_vec; // @[util.scala:545:19]
wire [6:0] out_uop_rob_idx; // @[util.scala:545:19]
wire [4:0] out_uop_ldq_idx; // @[util.scala:545:19]
wire [4:0] out_uop_stq_idx; // @[util.scala:545:19]
wire [1:0] out_uop_rxq_idx; // @[util.scala:545:19]
wire [6:0] out_uop_pdst; // @[util.scala:545:19]
wire [6:0] out_uop_prs1; // @[util.scala:545:19]
wire [6:0] out_uop_prs2; // @[util.scala:545:19]
wire [6:0] out_uop_prs3; // @[util.scala:545:19]
wire [4:0] out_uop_ppred; // @[util.scala:545:19]
wire out_uop_prs1_busy; // @[util.scala:545:19]
wire out_uop_prs2_busy; // @[util.scala:545:19]
wire out_uop_prs3_busy; // @[util.scala:545:19]
wire out_uop_ppred_busy; // @[util.scala:545:19]
wire [6:0] out_uop_stale_pdst; // @[util.scala:545:19]
wire out_uop_exception; // @[util.scala:545:19]
wire [63:0] out_uop_exc_cause; // @[util.scala:545:19]
wire [4:0] out_uop_mem_cmd; // @[util.scala:545:19]
wire [1:0] out_uop_mem_size; // @[util.scala:545:19]
wire out_uop_mem_signed; // @[util.scala:545:19]
wire out_uop_uses_ldq; // @[util.scala:545:19]
wire out_uop_uses_stq; // @[util.scala:545:19]
wire out_uop_is_unique; // @[util.scala:545:19]
wire out_uop_flush_on_commit; // @[util.scala:545:19]
wire [2:0] out_uop_csr_cmd; // @[util.scala:545:19]
wire out_uop_ldst_is_rs1; // @[util.scala:545:19]
wire [5:0] out_uop_ldst; // @[util.scala:545:19]
wire [5:0] out_uop_lrs1; // @[util.scala:545:19]
wire [5:0] out_uop_lrs2; // @[util.scala:545:19]
wire [5:0] out_uop_lrs3; // @[util.scala:545:19]
wire [1:0] out_uop_dst_rtype; // @[util.scala:545:19]
wire [1:0] out_uop_lrs1_rtype; // @[util.scala:545:19]
wire [1:0] out_uop_lrs2_rtype; // @[util.scala:545:19]
wire out_uop_frs3_en; // @[util.scala:545:19]
wire out_uop_fcn_dw; // @[util.scala:545:19]
wire [4:0] out_uop_fcn_op; // @[util.scala:545:19]
wire out_uop_fp_val; // @[util.scala:545:19]
wire [2:0] out_uop_fp_rm; // @[util.scala:545:19]
wire [1:0] out_uop_fp_typ; // @[util.scala:545:19]
wire out_uop_xcpt_pf_if; // @[util.scala:545:19]
wire out_uop_xcpt_ae_if; // @[util.scala:545:19]
wire out_uop_xcpt_ma_if; // @[util.scala:545:19]
wire out_uop_bp_debug_if; // @[util.scala:545:19]
wire out_uop_bp_xcpt_if; // @[util.scala:545:19]
wire [2:0] out_uop_debug_fsrc; // @[util.scala:545:19]
wire [2:0] out_uop_debug_tsrc; // @[util.scala:545:19]
wire [39:0] out_addr; // @[util.scala:545:19]
wire [63:0] out_data; // @[util.scala:545:19]
wire out_is_hella; // @[util.scala:545:19]
wire out_tag_match; // @[util.scala:545:19]
wire [1:0] out_old_meta_coh_state; // @[util.scala:545:19]
wire [19:0] out_old_meta_tag; // @[util.scala:545:19]
wire [7:0] out_way_en; // @[util.scala:545:19]
wire [4:0] out_sdq_id; // @[util.scala:545:19]
wire _io_empty_T_1; // @[util.scala:512:27]
wire [3:0] _io_count_T_5; // @[util.scala:556:22]
wire io_enq_ready_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7]
wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:458:7]
wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7]
wire [39:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7]
wire [15:0] io_deq_bits_uop_br_mask_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_br_tag_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_br_type_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_fence_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_amo_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_eret_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_mov_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7]
wire io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7]
wire io_deq_bits_uop_taken_0; // @[util.scala:458:7]
wire io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_pimm_0; // @[util.scala:458:7]
wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_pdst_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_prs1_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_prs2_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_prs3_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_ppred_0; // @[util.scala:458:7]
wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7]
wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7]
wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7]
wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7]
wire io_deq_bits_uop_exception_0; // @[util.scala:458:7]
wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:458:7]
wire io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7]
wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7]
wire io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_unique_0; // @[util.scala:458:7]
wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7]
wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7]
wire io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_val_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7]
wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7]
wire [19:0] io_deq_bits_old_meta_tag_0; // @[util.scala:458:7]
wire [39:0] io_deq_bits_addr_0; // @[util.scala:458:7]
wire [63:0] io_deq_bits_data_0; // @[util.scala:458:7]
wire io_deq_bits_is_hella_0; // @[util.scala:458:7]
wire io_deq_bits_tag_match_0; // @[util.scala:458:7]
wire [7:0] io_deq_bits_way_en_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_sdq_id_0; // @[util.scala:458:7]
wire io_deq_valid_0; // @[util.scala:458:7]
wire io_empty_0; // @[util.scala:458:7]
wire [3:0] io_count_0; // @[util.scala:458:7]
assign out_addr = _ram_ext_R0_data[39:0]; // @[util.scala:503:22, :545:19]
assign out_data = _ram_ext_R0_data[103:40]; // @[util.scala:503:22, :545:19]
assign out_is_hella = _ram_ext_R0_data[104]; // @[util.scala:503:22, :545:19]
assign out_tag_match = _ram_ext_R0_data[105]; // @[util.scala:503:22, :545:19]
assign out_old_meta_coh_state = _ram_ext_R0_data[107:106]; // @[util.scala:503:22, :545:19]
assign out_old_meta_tag = _ram_ext_R0_data[127:108]; // @[util.scala:503:22, :545:19]
assign out_way_en = _ram_ext_R0_data[135:128]; // @[util.scala:503:22, :545:19]
assign out_sdq_id = _ram_ext_R0_data[140:136]; // @[util.scala:503:22, :545:19]
reg valids_0; // @[util.scala:504:26]
reg valids_1; // @[util.scala:504:26]
reg valids_2; // @[util.scala:504:26]
reg valids_3; // @[util.scala:504:26]
reg valids_4; // @[util.scala:504:26]
reg valids_5; // @[util.scala:504:26]
reg valids_6; // @[util.scala:504:26]
reg valids_7; // @[util.scala:504:26]
reg valids_8; // @[util.scala:504:26]
reg valids_9; // @[util.scala:504:26]
reg valids_10; // @[util.scala:504:26]
reg valids_11; // @[util.scala:504:26]
reg valids_12; // @[util.scala:504:26]
reg valids_13; // @[util.scala:504:26]
reg valids_14; // @[util.scala:504:26]
reg [31:0] uops_0_inst; // @[util.scala:505:22]
reg [31:0] uops_0_debug_inst; // @[util.scala:505:22]
reg uops_0_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_0_debug_pc; // @[util.scala:505:22]
reg uops_0_iq_type_0; // @[util.scala:505:22]
reg uops_0_iq_type_1; // @[util.scala:505:22]
reg uops_0_iq_type_2; // @[util.scala:505:22]
reg uops_0_iq_type_3; // @[util.scala:505:22]
reg uops_0_fu_code_0; // @[util.scala:505:22]
reg uops_0_fu_code_1; // @[util.scala:505:22]
reg uops_0_fu_code_2; // @[util.scala:505:22]
reg uops_0_fu_code_3; // @[util.scala:505:22]
reg uops_0_fu_code_4; // @[util.scala:505:22]
reg uops_0_fu_code_5; // @[util.scala:505:22]
reg uops_0_fu_code_6; // @[util.scala:505:22]
reg uops_0_fu_code_7; // @[util.scala:505:22]
reg uops_0_fu_code_8; // @[util.scala:505:22]
reg uops_0_fu_code_9; // @[util.scala:505:22]
reg uops_0_iw_issued; // @[util.scala:505:22]
reg uops_0_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_0_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [2:0] uops_0_iw_p1_speculative_child; // @[util.scala:505:22]
reg [2:0] uops_0_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_0_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_0_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_0_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [2:0] uops_0_dis_col_sel; // @[util.scala:505:22]
reg [15:0] uops_0_br_mask; // @[util.scala:505:22]
reg [3:0] uops_0_br_tag; // @[util.scala:505:22]
reg [3:0] uops_0_br_type; // @[util.scala:505:22]
reg uops_0_is_sfb; // @[util.scala:505:22]
reg uops_0_is_fence; // @[util.scala:505:22]
reg uops_0_is_fencei; // @[util.scala:505:22]
reg uops_0_is_sfence; // @[util.scala:505:22]
reg uops_0_is_amo; // @[util.scala:505:22]
reg uops_0_is_eret; // @[util.scala:505:22]
reg uops_0_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_0_is_rocc; // @[util.scala:505:22]
reg uops_0_is_mov; // @[util.scala:505:22]
reg [4:0] uops_0_ftq_idx; // @[util.scala:505:22]
reg uops_0_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_0_pc_lob; // @[util.scala:505:22]
reg uops_0_taken; // @[util.scala:505:22]
reg uops_0_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_0_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_0_pimm; // @[util.scala:505:22]
reg [19:0] uops_0_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_0_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_0_op2_sel; // @[util.scala:505:22]
reg uops_0_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_0_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_0_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_0_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_0_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_0_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_0_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_0_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_0_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_0_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_0_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_0_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_0_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_0_fp_ctrl_div; // @[util.scala:505:22]
reg uops_0_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_0_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_0_fp_ctrl_vec; // @[util.scala:505:22]
reg [6:0] uops_0_rob_idx; // @[util.scala:505:22]
reg [4:0] uops_0_ldq_idx; // @[util.scala:505:22]
reg [4:0] uops_0_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_0_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_0_pdst; // @[util.scala:505:22]
reg [6:0] uops_0_prs1; // @[util.scala:505:22]
reg [6:0] uops_0_prs2; // @[util.scala:505:22]
reg [6:0] uops_0_prs3; // @[util.scala:505:22]
reg [4:0] uops_0_ppred; // @[util.scala:505:22]
reg uops_0_prs1_busy; // @[util.scala:505:22]
reg uops_0_prs2_busy; // @[util.scala:505:22]
reg uops_0_prs3_busy; // @[util.scala:505:22]
reg uops_0_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_0_stale_pdst; // @[util.scala:505:22]
reg uops_0_exception; // @[util.scala:505:22]
reg [63:0] uops_0_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_0_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_0_mem_size; // @[util.scala:505:22]
reg uops_0_mem_signed; // @[util.scala:505:22]
reg uops_0_uses_ldq; // @[util.scala:505:22]
reg uops_0_uses_stq; // @[util.scala:505:22]
reg uops_0_is_unique; // @[util.scala:505:22]
reg uops_0_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_0_csr_cmd; // @[util.scala:505:22]
reg uops_0_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_0_ldst; // @[util.scala:505:22]
reg [5:0] uops_0_lrs1; // @[util.scala:505:22]
reg [5:0] uops_0_lrs2; // @[util.scala:505:22]
reg [5:0] uops_0_lrs3; // @[util.scala:505:22]
reg [1:0] uops_0_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_0_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_0_lrs2_rtype; // @[util.scala:505:22]
reg uops_0_frs3_en; // @[util.scala:505:22]
reg uops_0_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_0_fcn_op; // @[util.scala:505:22]
reg uops_0_fp_val; // @[util.scala:505:22]
reg [2:0] uops_0_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_0_fp_typ; // @[util.scala:505:22]
reg uops_0_xcpt_pf_if; // @[util.scala:505:22]
reg uops_0_xcpt_ae_if; // @[util.scala:505:22]
reg uops_0_xcpt_ma_if; // @[util.scala:505:22]
reg uops_0_bp_debug_if; // @[util.scala:505:22]
reg uops_0_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_0_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_0_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_1_inst; // @[util.scala:505:22]
reg [31:0] uops_1_debug_inst; // @[util.scala:505:22]
reg uops_1_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_1_debug_pc; // @[util.scala:505:22]
reg uops_1_iq_type_0; // @[util.scala:505:22]
reg uops_1_iq_type_1; // @[util.scala:505:22]
reg uops_1_iq_type_2; // @[util.scala:505:22]
reg uops_1_iq_type_3; // @[util.scala:505:22]
reg uops_1_fu_code_0; // @[util.scala:505:22]
reg uops_1_fu_code_1; // @[util.scala:505:22]
reg uops_1_fu_code_2; // @[util.scala:505:22]
reg uops_1_fu_code_3; // @[util.scala:505:22]
reg uops_1_fu_code_4; // @[util.scala:505:22]
reg uops_1_fu_code_5; // @[util.scala:505:22]
reg uops_1_fu_code_6; // @[util.scala:505:22]
reg uops_1_fu_code_7; // @[util.scala:505:22]
reg uops_1_fu_code_8; // @[util.scala:505:22]
reg uops_1_fu_code_9; // @[util.scala:505:22]
reg uops_1_iw_issued; // @[util.scala:505:22]
reg uops_1_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_1_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [2:0] uops_1_iw_p1_speculative_child; // @[util.scala:505:22]
reg [2:0] uops_1_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_1_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_1_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_1_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [2:0] uops_1_dis_col_sel; // @[util.scala:505:22]
reg [15:0] uops_1_br_mask; // @[util.scala:505:22]
reg [3:0] uops_1_br_tag; // @[util.scala:505:22]
reg [3:0] uops_1_br_type; // @[util.scala:505:22]
reg uops_1_is_sfb; // @[util.scala:505:22]
reg uops_1_is_fence; // @[util.scala:505:22]
reg uops_1_is_fencei; // @[util.scala:505:22]
reg uops_1_is_sfence; // @[util.scala:505:22]
reg uops_1_is_amo; // @[util.scala:505:22]
reg uops_1_is_eret; // @[util.scala:505:22]
reg uops_1_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_1_is_rocc; // @[util.scala:505:22]
reg uops_1_is_mov; // @[util.scala:505:22]
reg [4:0] uops_1_ftq_idx; // @[util.scala:505:22]
reg uops_1_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_1_pc_lob; // @[util.scala:505:22]
reg uops_1_taken; // @[util.scala:505:22]
reg uops_1_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_1_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_1_pimm; // @[util.scala:505:22]
reg [19:0] uops_1_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_1_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_1_op2_sel; // @[util.scala:505:22]
reg uops_1_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_1_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_1_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_1_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_1_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_1_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_1_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_1_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_1_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_1_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_1_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_1_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_1_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_1_fp_ctrl_div; // @[util.scala:505:22]
reg uops_1_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_1_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_1_fp_ctrl_vec; // @[util.scala:505:22]
reg [6:0] uops_1_rob_idx; // @[util.scala:505:22]
reg [4:0] uops_1_ldq_idx; // @[util.scala:505:22]
reg [4:0] uops_1_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_1_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_1_pdst; // @[util.scala:505:22]
reg [6:0] uops_1_prs1; // @[util.scala:505:22]
reg [6:0] uops_1_prs2; // @[util.scala:505:22]
reg [6:0] uops_1_prs3; // @[util.scala:505:22]
reg [4:0] uops_1_ppred; // @[util.scala:505:22]
reg uops_1_prs1_busy; // @[util.scala:505:22]
reg uops_1_prs2_busy; // @[util.scala:505:22]
reg uops_1_prs3_busy; // @[util.scala:505:22]
reg uops_1_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_1_stale_pdst; // @[util.scala:505:22]
reg uops_1_exception; // @[util.scala:505:22]
reg [63:0] uops_1_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_1_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_1_mem_size; // @[util.scala:505:22]
reg uops_1_mem_signed; // @[util.scala:505:22]
reg uops_1_uses_ldq; // @[util.scala:505:22]
reg uops_1_uses_stq; // @[util.scala:505:22]
reg uops_1_is_unique; // @[util.scala:505:22]
reg uops_1_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_1_csr_cmd; // @[util.scala:505:22]
reg uops_1_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_1_ldst; // @[util.scala:505:22]
reg [5:0] uops_1_lrs1; // @[util.scala:505:22]
reg [5:0] uops_1_lrs2; // @[util.scala:505:22]
reg [5:0] uops_1_lrs3; // @[util.scala:505:22]
reg [1:0] uops_1_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_1_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_1_lrs2_rtype; // @[util.scala:505:22]
reg uops_1_frs3_en; // @[util.scala:505:22]
reg uops_1_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_1_fcn_op; // @[util.scala:505:22]
reg uops_1_fp_val; // @[util.scala:505:22]
reg [2:0] uops_1_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_1_fp_typ; // @[util.scala:505:22]
reg uops_1_xcpt_pf_if; // @[util.scala:505:22]
reg uops_1_xcpt_ae_if; // @[util.scala:505:22]
reg uops_1_xcpt_ma_if; // @[util.scala:505:22]
reg uops_1_bp_debug_if; // @[util.scala:505:22]
reg uops_1_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_1_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_1_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_2_inst; // @[util.scala:505:22]
reg [31:0] uops_2_debug_inst; // @[util.scala:505:22]
reg uops_2_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_2_debug_pc; // @[util.scala:505:22]
reg uops_2_iq_type_0; // @[util.scala:505:22]
reg uops_2_iq_type_1; // @[util.scala:505:22]
reg uops_2_iq_type_2; // @[util.scala:505:22]
reg uops_2_iq_type_3; // @[util.scala:505:22]
reg uops_2_fu_code_0; // @[util.scala:505:22]
reg uops_2_fu_code_1; // @[util.scala:505:22]
reg uops_2_fu_code_2; // @[util.scala:505:22]
reg uops_2_fu_code_3; // @[util.scala:505:22]
reg uops_2_fu_code_4; // @[util.scala:505:22]
reg uops_2_fu_code_5; // @[util.scala:505:22]
reg uops_2_fu_code_6; // @[util.scala:505:22]
reg uops_2_fu_code_7; // @[util.scala:505:22]
reg uops_2_fu_code_8; // @[util.scala:505:22]
reg uops_2_fu_code_9; // @[util.scala:505:22]
reg uops_2_iw_issued; // @[util.scala:505:22]
reg uops_2_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_2_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [2:0] uops_2_iw_p1_speculative_child; // @[util.scala:505:22]
reg [2:0] uops_2_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_2_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_2_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_2_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [2:0] uops_2_dis_col_sel; // @[util.scala:505:22]
reg [15:0] uops_2_br_mask; // @[util.scala:505:22]
reg [3:0] uops_2_br_tag; // @[util.scala:505:22]
reg [3:0] uops_2_br_type; // @[util.scala:505:22]
reg uops_2_is_sfb; // @[util.scala:505:22]
reg uops_2_is_fence; // @[util.scala:505:22]
reg uops_2_is_fencei; // @[util.scala:505:22]
reg uops_2_is_sfence; // @[util.scala:505:22]
reg uops_2_is_amo; // @[util.scala:505:22]
reg uops_2_is_eret; // @[util.scala:505:22]
reg uops_2_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_2_is_rocc; // @[util.scala:505:22]
reg uops_2_is_mov; // @[util.scala:505:22]
reg [4:0] uops_2_ftq_idx; // @[util.scala:505:22]
reg uops_2_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_2_pc_lob; // @[util.scala:505:22]
reg uops_2_taken; // @[util.scala:505:22]
reg uops_2_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_2_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_2_pimm; // @[util.scala:505:22]
reg [19:0] uops_2_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_2_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_2_op2_sel; // @[util.scala:505:22]
reg uops_2_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_2_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_2_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_2_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_2_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_2_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_2_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_2_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_2_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_2_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_2_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_2_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_2_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_2_fp_ctrl_div; // @[util.scala:505:22]
reg uops_2_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_2_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_2_fp_ctrl_vec; // @[util.scala:505:22]
reg [6:0] uops_2_rob_idx; // @[util.scala:505:22]
reg [4:0] uops_2_ldq_idx; // @[util.scala:505:22]
reg [4:0] uops_2_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_2_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_2_pdst; // @[util.scala:505:22]
reg [6:0] uops_2_prs1; // @[util.scala:505:22]
reg [6:0] uops_2_prs2; // @[util.scala:505:22]
reg [6:0] uops_2_prs3; // @[util.scala:505:22]
reg [4:0] uops_2_ppred; // @[util.scala:505:22]
reg uops_2_prs1_busy; // @[util.scala:505:22]
reg uops_2_prs2_busy; // @[util.scala:505:22]
reg uops_2_prs3_busy; // @[util.scala:505:22]
reg uops_2_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_2_stale_pdst; // @[util.scala:505:22]
reg uops_2_exception; // @[util.scala:505:22]
reg [63:0] uops_2_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_2_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_2_mem_size; // @[util.scala:505:22]
reg uops_2_mem_signed; // @[util.scala:505:22]
reg uops_2_uses_ldq; // @[util.scala:505:22]
reg uops_2_uses_stq; // @[util.scala:505:22]
reg uops_2_is_unique; // @[util.scala:505:22]
reg uops_2_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_2_csr_cmd; // @[util.scala:505:22]
reg uops_2_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_2_ldst; // @[util.scala:505:22]
reg [5:0] uops_2_lrs1; // @[util.scala:505:22]
reg [5:0] uops_2_lrs2; // @[util.scala:505:22]
reg [5:0] uops_2_lrs3; // @[util.scala:505:22]
reg [1:0] uops_2_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_2_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_2_lrs2_rtype; // @[util.scala:505:22]
reg uops_2_frs3_en; // @[util.scala:505:22]
reg uops_2_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_2_fcn_op; // @[util.scala:505:22]
reg uops_2_fp_val; // @[util.scala:505:22]
reg [2:0] uops_2_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_2_fp_typ; // @[util.scala:505:22]
reg uops_2_xcpt_pf_if; // @[util.scala:505:22]
reg uops_2_xcpt_ae_if; // @[util.scala:505:22]
reg uops_2_xcpt_ma_if; // @[util.scala:505:22]
reg uops_2_bp_debug_if; // @[util.scala:505:22]
reg uops_2_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_2_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_2_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_3_inst; // @[util.scala:505:22]
reg [31:0] uops_3_debug_inst; // @[util.scala:505:22]
reg uops_3_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_3_debug_pc; // @[util.scala:505:22]
reg uops_3_iq_type_0; // @[util.scala:505:22]
reg uops_3_iq_type_1; // @[util.scala:505:22]
reg uops_3_iq_type_2; // @[util.scala:505:22]
reg uops_3_iq_type_3; // @[util.scala:505:22]
reg uops_3_fu_code_0; // @[util.scala:505:22]
reg uops_3_fu_code_1; // @[util.scala:505:22]
reg uops_3_fu_code_2; // @[util.scala:505:22]
reg uops_3_fu_code_3; // @[util.scala:505:22]
reg uops_3_fu_code_4; // @[util.scala:505:22]
reg uops_3_fu_code_5; // @[util.scala:505:22]
reg uops_3_fu_code_6; // @[util.scala:505:22]
reg uops_3_fu_code_7; // @[util.scala:505:22]
reg uops_3_fu_code_8; // @[util.scala:505:22]
reg uops_3_fu_code_9; // @[util.scala:505:22]
reg uops_3_iw_issued; // @[util.scala:505:22]
reg uops_3_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_3_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [2:0] uops_3_iw_p1_speculative_child; // @[util.scala:505:22]
reg [2:0] uops_3_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_3_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_3_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_3_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [2:0] uops_3_dis_col_sel; // @[util.scala:505:22]
reg [15:0] uops_3_br_mask; // @[util.scala:505:22]
reg [3:0] uops_3_br_tag; // @[util.scala:505:22]
reg [3:0] uops_3_br_type; // @[util.scala:505:22]
reg uops_3_is_sfb; // @[util.scala:505:22]
reg uops_3_is_fence; // @[util.scala:505:22]
reg uops_3_is_fencei; // @[util.scala:505:22]
reg uops_3_is_sfence; // @[util.scala:505:22]
reg uops_3_is_amo; // @[util.scala:505:22]
reg uops_3_is_eret; // @[util.scala:505:22]
reg uops_3_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_3_is_rocc; // @[util.scala:505:22]
reg uops_3_is_mov; // @[util.scala:505:22]
reg [4:0] uops_3_ftq_idx; // @[util.scala:505:22]
reg uops_3_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_3_pc_lob; // @[util.scala:505:22]
reg uops_3_taken; // @[util.scala:505:22]
reg uops_3_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_3_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_3_pimm; // @[util.scala:505:22]
reg [19:0] uops_3_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_3_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_3_op2_sel; // @[util.scala:505:22]
reg uops_3_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_3_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_3_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_3_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_3_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_3_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_3_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_3_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_3_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_3_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_3_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_3_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_3_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_3_fp_ctrl_div; // @[util.scala:505:22]
reg uops_3_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_3_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_3_fp_ctrl_vec; // @[util.scala:505:22]
reg [6:0] uops_3_rob_idx; // @[util.scala:505:22]
reg [4:0] uops_3_ldq_idx; // @[util.scala:505:22]
reg [4:0] uops_3_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_3_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_3_pdst; // @[util.scala:505:22]
reg [6:0] uops_3_prs1; // @[util.scala:505:22]
reg [6:0] uops_3_prs2; // @[util.scala:505:22]
reg [6:0] uops_3_prs3; // @[util.scala:505:22]
reg [4:0] uops_3_ppred; // @[util.scala:505:22]
reg uops_3_prs1_busy; // @[util.scala:505:22]
reg uops_3_prs2_busy; // @[util.scala:505:22]
reg uops_3_prs3_busy; // @[util.scala:505:22]
reg uops_3_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_3_stale_pdst; // @[util.scala:505:22]
reg uops_3_exception; // @[util.scala:505:22]
reg [63:0] uops_3_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_3_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_3_mem_size; // @[util.scala:505:22]
reg uops_3_mem_signed; // @[util.scala:505:22]
reg uops_3_uses_ldq; // @[util.scala:505:22]
reg uops_3_uses_stq; // @[util.scala:505:22]
reg uops_3_is_unique; // @[util.scala:505:22]
reg uops_3_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_3_csr_cmd; // @[util.scala:505:22]
reg uops_3_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_3_ldst; // @[util.scala:505:22]
reg [5:0] uops_3_lrs1; // @[util.scala:505:22]
reg [5:0] uops_3_lrs2; // @[util.scala:505:22]
reg [5:0] uops_3_lrs3; // @[util.scala:505:22]
reg [1:0] uops_3_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_3_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_3_lrs2_rtype; // @[util.scala:505:22]
reg uops_3_frs3_en; // @[util.scala:505:22]
reg uops_3_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_3_fcn_op; // @[util.scala:505:22]
reg uops_3_fp_val; // @[util.scala:505:22]
reg [2:0] uops_3_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_3_fp_typ; // @[util.scala:505:22]
reg uops_3_xcpt_pf_if; // @[util.scala:505:22]
reg uops_3_xcpt_ae_if; // @[util.scala:505:22]
reg uops_3_xcpt_ma_if; // @[util.scala:505:22]
reg uops_3_bp_debug_if; // @[util.scala:505:22]
reg uops_3_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_3_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_3_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_4_inst; // @[util.scala:505:22]
reg [31:0] uops_4_debug_inst; // @[util.scala:505:22]
reg uops_4_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_4_debug_pc; // @[util.scala:505:22]
reg uops_4_iq_type_0; // @[util.scala:505:22]
reg uops_4_iq_type_1; // @[util.scala:505:22]
reg uops_4_iq_type_2; // @[util.scala:505:22]
reg uops_4_iq_type_3; // @[util.scala:505:22]
reg uops_4_fu_code_0; // @[util.scala:505:22]
reg uops_4_fu_code_1; // @[util.scala:505:22]
reg uops_4_fu_code_2; // @[util.scala:505:22]
reg uops_4_fu_code_3; // @[util.scala:505:22]
reg uops_4_fu_code_4; // @[util.scala:505:22]
reg uops_4_fu_code_5; // @[util.scala:505:22]
reg uops_4_fu_code_6; // @[util.scala:505:22]
reg uops_4_fu_code_7; // @[util.scala:505:22]
reg uops_4_fu_code_8; // @[util.scala:505:22]
reg uops_4_fu_code_9; // @[util.scala:505:22]
reg uops_4_iw_issued; // @[util.scala:505:22]
reg uops_4_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_4_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [2:0] uops_4_iw_p1_speculative_child; // @[util.scala:505:22]
reg [2:0] uops_4_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_4_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_4_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_4_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [2:0] uops_4_dis_col_sel; // @[util.scala:505:22]
reg [15:0] uops_4_br_mask; // @[util.scala:505:22]
reg [3:0] uops_4_br_tag; // @[util.scala:505:22]
reg [3:0] uops_4_br_type; // @[util.scala:505:22]
reg uops_4_is_sfb; // @[util.scala:505:22]
reg uops_4_is_fence; // @[util.scala:505:22]
reg uops_4_is_fencei; // @[util.scala:505:22]
reg uops_4_is_sfence; // @[util.scala:505:22]
reg uops_4_is_amo; // @[util.scala:505:22]
reg uops_4_is_eret; // @[util.scala:505:22]
reg uops_4_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_4_is_rocc; // @[util.scala:505:22]
reg uops_4_is_mov; // @[util.scala:505:22]
reg [4:0] uops_4_ftq_idx; // @[util.scala:505:22]
reg uops_4_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_4_pc_lob; // @[util.scala:505:22]
reg uops_4_taken; // @[util.scala:505:22]
reg uops_4_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_4_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_4_pimm; // @[util.scala:505:22]
reg [19:0] uops_4_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_4_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_4_op2_sel; // @[util.scala:505:22]
reg uops_4_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_4_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_4_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_4_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_4_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_4_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_4_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_4_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_4_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_4_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_4_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_4_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_4_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_4_fp_ctrl_div; // @[util.scala:505:22]
reg uops_4_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_4_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_4_fp_ctrl_vec; // @[util.scala:505:22]
reg [6:0] uops_4_rob_idx; // @[util.scala:505:22]
reg [4:0] uops_4_ldq_idx; // @[util.scala:505:22]
reg [4:0] uops_4_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_4_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_4_pdst; // @[util.scala:505:22]
reg [6:0] uops_4_prs1; // @[util.scala:505:22]
reg [6:0] uops_4_prs2; // @[util.scala:505:22]
reg [6:0] uops_4_prs3; // @[util.scala:505:22]
reg [4:0] uops_4_ppred; // @[util.scala:505:22]
reg uops_4_prs1_busy; // @[util.scala:505:22]
reg uops_4_prs2_busy; // @[util.scala:505:22]
reg uops_4_prs3_busy; // @[util.scala:505:22]
reg uops_4_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_4_stale_pdst; // @[util.scala:505:22]
reg uops_4_exception; // @[util.scala:505:22]
reg [63:0] uops_4_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_4_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_4_mem_size; // @[util.scala:505:22]
reg uops_4_mem_signed; // @[util.scala:505:22]
reg uops_4_uses_ldq; // @[util.scala:505:22]
reg uops_4_uses_stq; // @[util.scala:505:22]
reg uops_4_is_unique; // @[util.scala:505:22]
reg uops_4_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_4_csr_cmd; // @[util.scala:505:22]
reg uops_4_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_4_ldst; // @[util.scala:505:22]
reg [5:0] uops_4_lrs1; // @[util.scala:505:22]
reg [5:0] uops_4_lrs2; // @[util.scala:505:22]
reg [5:0] uops_4_lrs3; // @[util.scala:505:22]
reg [1:0] uops_4_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_4_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_4_lrs2_rtype; // @[util.scala:505:22]
reg uops_4_frs3_en; // @[util.scala:505:22]
reg uops_4_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_4_fcn_op; // @[util.scala:505:22]
reg uops_4_fp_val; // @[util.scala:505:22]
reg [2:0] uops_4_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_4_fp_typ; // @[util.scala:505:22]
reg uops_4_xcpt_pf_if; // @[util.scala:505:22]
reg uops_4_xcpt_ae_if; // @[util.scala:505:22]
reg uops_4_xcpt_ma_if; // @[util.scala:505:22]
reg uops_4_bp_debug_if; // @[util.scala:505:22]
reg uops_4_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_4_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_4_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_5_inst; // @[util.scala:505:22]
reg [31:0] uops_5_debug_inst; // @[util.scala:505:22]
reg uops_5_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_5_debug_pc; // @[util.scala:505:22]
reg uops_5_iq_type_0; // @[util.scala:505:22]
reg uops_5_iq_type_1; // @[util.scala:505:22]
reg uops_5_iq_type_2; // @[util.scala:505:22]
reg uops_5_iq_type_3; // @[util.scala:505:22]
reg uops_5_fu_code_0; // @[util.scala:505:22]
reg uops_5_fu_code_1; // @[util.scala:505:22]
reg uops_5_fu_code_2; // @[util.scala:505:22]
reg uops_5_fu_code_3; // @[util.scala:505:22]
reg uops_5_fu_code_4; // @[util.scala:505:22]
reg uops_5_fu_code_5; // @[util.scala:505:22]
reg uops_5_fu_code_6; // @[util.scala:505:22]
reg uops_5_fu_code_7; // @[util.scala:505:22]
reg uops_5_fu_code_8; // @[util.scala:505:22]
reg uops_5_fu_code_9; // @[util.scala:505:22]
reg uops_5_iw_issued; // @[util.scala:505:22]
reg uops_5_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_5_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [2:0] uops_5_iw_p1_speculative_child; // @[util.scala:505:22]
reg [2:0] uops_5_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_5_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_5_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_5_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [2:0] uops_5_dis_col_sel; // @[util.scala:505:22]
reg [15:0] uops_5_br_mask; // @[util.scala:505:22]
reg [3:0] uops_5_br_tag; // @[util.scala:505:22]
reg [3:0] uops_5_br_type; // @[util.scala:505:22]
reg uops_5_is_sfb; // @[util.scala:505:22]
reg uops_5_is_fence; // @[util.scala:505:22]
reg uops_5_is_fencei; // @[util.scala:505:22]
reg uops_5_is_sfence; // @[util.scala:505:22]
reg uops_5_is_amo; // @[util.scala:505:22]
reg uops_5_is_eret; // @[util.scala:505:22]
reg uops_5_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_5_is_rocc; // @[util.scala:505:22]
reg uops_5_is_mov; // @[util.scala:505:22]
reg [4:0] uops_5_ftq_idx; // @[util.scala:505:22]
reg uops_5_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_5_pc_lob; // @[util.scala:505:22]
reg uops_5_taken; // @[util.scala:505:22]
reg uops_5_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_5_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_5_pimm; // @[util.scala:505:22]
reg [19:0] uops_5_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_5_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_5_op2_sel; // @[util.scala:505:22]
reg uops_5_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_5_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_5_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_5_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_5_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_5_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_5_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_5_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_5_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_5_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_5_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_5_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_5_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_5_fp_ctrl_div; // @[util.scala:505:22]
reg uops_5_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_5_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_5_fp_ctrl_vec; // @[util.scala:505:22]
reg [6:0] uops_5_rob_idx; // @[util.scala:505:22]
reg [4:0] uops_5_ldq_idx; // @[util.scala:505:22]
reg [4:0] uops_5_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_5_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_5_pdst; // @[util.scala:505:22]
reg [6:0] uops_5_prs1; // @[util.scala:505:22]
reg [6:0] uops_5_prs2; // @[util.scala:505:22]
reg [6:0] uops_5_prs3; // @[util.scala:505:22]
reg [4:0] uops_5_ppred; // @[util.scala:505:22]
reg uops_5_prs1_busy; // @[util.scala:505:22]
reg uops_5_prs2_busy; // @[util.scala:505:22]
reg uops_5_prs3_busy; // @[util.scala:505:22]
reg uops_5_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_5_stale_pdst; // @[util.scala:505:22]
reg uops_5_exception; // @[util.scala:505:22]
reg [63:0] uops_5_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_5_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_5_mem_size; // @[util.scala:505:22]
reg uops_5_mem_signed; // @[util.scala:505:22]
reg uops_5_uses_ldq; // @[util.scala:505:22]
reg uops_5_uses_stq; // @[util.scala:505:22]
reg uops_5_is_unique; // @[util.scala:505:22]
reg uops_5_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_5_csr_cmd; // @[util.scala:505:22]
reg uops_5_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_5_ldst; // @[util.scala:505:22]
reg [5:0] uops_5_lrs1; // @[util.scala:505:22]
reg [5:0] uops_5_lrs2; // @[util.scala:505:22]
reg [5:0] uops_5_lrs3; // @[util.scala:505:22]
reg [1:0] uops_5_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_5_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_5_lrs2_rtype; // @[util.scala:505:22]
reg uops_5_frs3_en; // @[util.scala:505:22]
reg uops_5_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_5_fcn_op; // @[util.scala:505:22]
reg uops_5_fp_val; // @[util.scala:505:22]
reg [2:0] uops_5_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_5_fp_typ; // @[util.scala:505:22]
reg uops_5_xcpt_pf_if; // @[util.scala:505:22]
reg uops_5_xcpt_ae_if; // @[util.scala:505:22]
reg uops_5_xcpt_ma_if; // @[util.scala:505:22]
reg uops_5_bp_debug_if; // @[util.scala:505:22]
reg uops_5_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_5_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_5_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_6_inst; // @[util.scala:505:22]
reg [31:0] uops_6_debug_inst; // @[util.scala:505:22]
reg uops_6_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_6_debug_pc; // @[util.scala:505:22]
reg uops_6_iq_type_0; // @[util.scala:505:22]
reg uops_6_iq_type_1; // @[util.scala:505:22]
reg uops_6_iq_type_2; // @[util.scala:505:22]
reg uops_6_iq_type_3; // @[util.scala:505:22]
reg uops_6_fu_code_0; // @[util.scala:505:22]
reg uops_6_fu_code_1; // @[util.scala:505:22]
reg uops_6_fu_code_2; // @[util.scala:505:22]
reg uops_6_fu_code_3; // @[util.scala:505:22]
reg uops_6_fu_code_4; // @[util.scala:505:22]
reg uops_6_fu_code_5; // @[util.scala:505:22]
reg uops_6_fu_code_6; // @[util.scala:505:22]
reg uops_6_fu_code_7; // @[util.scala:505:22]
reg uops_6_fu_code_8; // @[util.scala:505:22]
reg uops_6_fu_code_9; // @[util.scala:505:22]
reg uops_6_iw_issued; // @[util.scala:505:22]
reg uops_6_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_6_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [2:0] uops_6_iw_p1_speculative_child; // @[util.scala:505:22]
reg [2:0] uops_6_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_6_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_6_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_6_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [2:0] uops_6_dis_col_sel; // @[util.scala:505:22]
reg [15:0] uops_6_br_mask; // @[util.scala:505:22]
reg [3:0] uops_6_br_tag; // @[util.scala:505:22]
reg [3:0] uops_6_br_type; // @[util.scala:505:22]
reg uops_6_is_sfb; // @[util.scala:505:22]
reg uops_6_is_fence; // @[util.scala:505:22]
reg uops_6_is_fencei; // @[util.scala:505:22]
reg uops_6_is_sfence; // @[util.scala:505:22]
reg uops_6_is_amo; // @[util.scala:505:22]
reg uops_6_is_eret; // @[util.scala:505:22]
reg uops_6_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_6_is_rocc; // @[util.scala:505:22]
reg uops_6_is_mov; // @[util.scala:505:22]
reg [4:0] uops_6_ftq_idx; // @[util.scala:505:22]
reg uops_6_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_6_pc_lob; // @[util.scala:505:22]
reg uops_6_taken; // @[util.scala:505:22]
reg uops_6_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_6_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_6_pimm; // @[util.scala:505:22]
reg [19:0] uops_6_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_6_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_6_op2_sel; // @[util.scala:505:22]
reg uops_6_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_6_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_6_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_6_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_6_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_6_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_6_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_6_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_6_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_6_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_6_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_6_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_6_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_6_fp_ctrl_div; // @[util.scala:505:22]
reg uops_6_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_6_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_6_fp_ctrl_vec; // @[util.scala:505:22]
reg [6:0] uops_6_rob_idx; // @[util.scala:505:22]
reg [4:0] uops_6_ldq_idx; // @[util.scala:505:22]
reg [4:0] uops_6_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_6_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_6_pdst; // @[util.scala:505:22]
reg [6:0] uops_6_prs1; // @[util.scala:505:22]
reg [6:0] uops_6_prs2; // @[util.scala:505:22]
reg [6:0] uops_6_prs3; // @[util.scala:505:22]
reg [4:0] uops_6_ppred; // @[util.scala:505:22]
reg uops_6_prs1_busy; // @[util.scala:505:22]
reg uops_6_prs2_busy; // @[util.scala:505:22]
reg uops_6_prs3_busy; // @[util.scala:505:22]
reg uops_6_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_6_stale_pdst; // @[util.scala:505:22]
reg uops_6_exception; // @[util.scala:505:22]
reg [63:0] uops_6_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_6_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_6_mem_size; // @[util.scala:505:22]
reg uops_6_mem_signed; // @[util.scala:505:22]
reg uops_6_uses_ldq; // @[util.scala:505:22]
reg uops_6_uses_stq; // @[util.scala:505:22]
reg uops_6_is_unique; // @[util.scala:505:22]
reg uops_6_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_6_csr_cmd; // @[util.scala:505:22]
reg uops_6_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_6_ldst; // @[util.scala:505:22]
reg [5:0] uops_6_lrs1; // @[util.scala:505:22]
reg [5:0] uops_6_lrs2; // @[util.scala:505:22]
reg [5:0] uops_6_lrs3; // @[util.scala:505:22]
reg [1:0] uops_6_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_6_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_6_lrs2_rtype; // @[util.scala:505:22]
reg uops_6_frs3_en; // @[util.scala:505:22]
reg uops_6_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_6_fcn_op; // @[util.scala:505:22]
reg uops_6_fp_val; // @[util.scala:505:22]
reg [2:0] uops_6_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_6_fp_typ; // @[util.scala:505:22]
reg uops_6_xcpt_pf_if; // @[util.scala:505:22]
reg uops_6_xcpt_ae_if; // @[util.scala:505:22]
reg uops_6_xcpt_ma_if; // @[util.scala:505:22]
reg uops_6_bp_debug_if; // @[util.scala:505:22]
reg uops_6_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_6_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_6_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_7_inst; // @[util.scala:505:22]
reg [31:0] uops_7_debug_inst; // @[util.scala:505:22]
reg uops_7_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_7_debug_pc; // @[util.scala:505:22]
reg uops_7_iq_type_0; // @[util.scala:505:22]
reg uops_7_iq_type_1; // @[util.scala:505:22]
reg uops_7_iq_type_2; // @[util.scala:505:22]
reg uops_7_iq_type_3; // @[util.scala:505:22]
reg uops_7_fu_code_0; // @[util.scala:505:22]
reg uops_7_fu_code_1; // @[util.scala:505:22]
reg uops_7_fu_code_2; // @[util.scala:505:22]
reg uops_7_fu_code_3; // @[util.scala:505:22]
reg uops_7_fu_code_4; // @[util.scala:505:22]
reg uops_7_fu_code_5; // @[util.scala:505:22]
reg uops_7_fu_code_6; // @[util.scala:505:22]
reg uops_7_fu_code_7; // @[util.scala:505:22]
reg uops_7_fu_code_8; // @[util.scala:505:22]
reg uops_7_fu_code_9; // @[util.scala:505:22]
reg uops_7_iw_issued; // @[util.scala:505:22]
reg uops_7_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_7_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [2:0] uops_7_iw_p1_speculative_child; // @[util.scala:505:22]
reg [2:0] uops_7_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_7_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_7_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_7_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [2:0] uops_7_dis_col_sel; // @[util.scala:505:22]
reg [15:0] uops_7_br_mask; // @[util.scala:505:22]
reg [3:0] uops_7_br_tag; // @[util.scala:505:22]
reg [3:0] uops_7_br_type; // @[util.scala:505:22]
reg uops_7_is_sfb; // @[util.scala:505:22]
reg uops_7_is_fence; // @[util.scala:505:22]
reg uops_7_is_fencei; // @[util.scala:505:22]
reg uops_7_is_sfence; // @[util.scala:505:22]
reg uops_7_is_amo; // @[util.scala:505:22]
reg uops_7_is_eret; // @[util.scala:505:22]
reg uops_7_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_7_is_rocc; // @[util.scala:505:22]
reg uops_7_is_mov; // @[util.scala:505:22]
reg [4:0] uops_7_ftq_idx; // @[util.scala:505:22]
reg uops_7_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_7_pc_lob; // @[util.scala:505:22]
reg uops_7_taken; // @[util.scala:505:22]
reg uops_7_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_7_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_7_pimm; // @[util.scala:505:22]
reg [19:0] uops_7_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_7_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_7_op2_sel; // @[util.scala:505:22]
reg uops_7_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_7_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_7_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_7_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_7_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_7_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_7_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_7_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_7_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_7_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_7_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_7_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_7_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_7_fp_ctrl_div; // @[util.scala:505:22]
reg uops_7_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_7_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_7_fp_ctrl_vec; // @[util.scala:505:22]
reg [6:0] uops_7_rob_idx; // @[util.scala:505:22]
reg [4:0] uops_7_ldq_idx; // @[util.scala:505:22]
reg [4:0] uops_7_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_7_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_7_pdst; // @[util.scala:505:22]
reg [6:0] uops_7_prs1; // @[util.scala:505:22]
reg [6:0] uops_7_prs2; // @[util.scala:505:22]
reg [6:0] uops_7_prs3; // @[util.scala:505:22]
reg [4:0] uops_7_ppred; // @[util.scala:505:22]
reg uops_7_prs1_busy; // @[util.scala:505:22]
reg uops_7_prs2_busy; // @[util.scala:505:22]
reg uops_7_prs3_busy; // @[util.scala:505:22]
reg uops_7_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_7_stale_pdst; // @[util.scala:505:22]
reg uops_7_exception; // @[util.scala:505:22]
reg [63:0] uops_7_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_7_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_7_mem_size; // @[util.scala:505:22]
reg uops_7_mem_signed; // @[util.scala:505:22]
reg uops_7_uses_ldq; // @[util.scala:505:22]
reg uops_7_uses_stq; // @[util.scala:505:22]
reg uops_7_is_unique; // @[util.scala:505:22]
reg uops_7_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_7_csr_cmd; // @[util.scala:505:22]
reg uops_7_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_7_ldst; // @[util.scala:505:22]
reg [5:0] uops_7_lrs1; // @[util.scala:505:22]
reg [5:0] uops_7_lrs2; // @[util.scala:505:22]
reg [5:0] uops_7_lrs3; // @[util.scala:505:22]
reg [1:0] uops_7_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_7_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_7_lrs2_rtype; // @[util.scala:505:22]
reg uops_7_frs3_en; // @[util.scala:505:22]
reg uops_7_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_7_fcn_op; // @[util.scala:505:22]
reg uops_7_fp_val; // @[util.scala:505:22]
reg [2:0] uops_7_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_7_fp_typ; // @[util.scala:505:22]
reg uops_7_xcpt_pf_if; // @[util.scala:505:22]
reg uops_7_xcpt_ae_if; // @[util.scala:505:22]
reg uops_7_xcpt_ma_if; // @[util.scala:505:22]
reg uops_7_bp_debug_if; // @[util.scala:505:22]
reg uops_7_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_7_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_7_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_8_inst; // @[util.scala:505:22]
reg [31:0] uops_8_debug_inst; // @[util.scala:505:22]
reg uops_8_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_8_debug_pc; // @[util.scala:505:22]
reg uops_8_iq_type_0; // @[util.scala:505:22]
reg uops_8_iq_type_1; // @[util.scala:505:22]
reg uops_8_iq_type_2; // @[util.scala:505:22]
reg uops_8_iq_type_3; // @[util.scala:505:22]
reg uops_8_fu_code_0; // @[util.scala:505:22]
reg uops_8_fu_code_1; // @[util.scala:505:22]
reg uops_8_fu_code_2; // @[util.scala:505:22]
reg uops_8_fu_code_3; // @[util.scala:505:22]
reg uops_8_fu_code_4; // @[util.scala:505:22]
reg uops_8_fu_code_5; // @[util.scala:505:22]
reg uops_8_fu_code_6; // @[util.scala:505:22]
reg uops_8_fu_code_7; // @[util.scala:505:22]
reg uops_8_fu_code_8; // @[util.scala:505:22]
reg uops_8_fu_code_9; // @[util.scala:505:22]
reg uops_8_iw_issued; // @[util.scala:505:22]
reg uops_8_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_8_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [2:0] uops_8_iw_p1_speculative_child; // @[util.scala:505:22]
reg [2:0] uops_8_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_8_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_8_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_8_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [2:0] uops_8_dis_col_sel; // @[util.scala:505:22]
reg [15:0] uops_8_br_mask; // @[util.scala:505:22]
reg [3:0] uops_8_br_tag; // @[util.scala:505:22]
reg [3:0] uops_8_br_type; // @[util.scala:505:22]
reg uops_8_is_sfb; // @[util.scala:505:22]
reg uops_8_is_fence; // @[util.scala:505:22]
reg uops_8_is_fencei; // @[util.scala:505:22]
reg uops_8_is_sfence; // @[util.scala:505:22]
reg uops_8_is_amo; // @[util.scala:505:22]
reg uops_8_is_eret; // @[util.scala:505:22]
reg uops_8_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_8_is_rocc; // @[util.scala:505:22]
reg uops_8_is_mov; // @[util.scala:505:22]
reg [4:0] uops_8_ftq_idx; // @[util.scala:505:22]
reg uops_8_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_8_pc_lob; // @[util.scala:505:22]
reg uops_8_taken; // @[util.scala:505:22]
reg uops_8_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_8_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_8_pimm; // @[util.scala:505:22]
reg [19:0] uops_8_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_8_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_8_op2_sel; // @[util.scala:505:22]
reg uops_8_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_8_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_8_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_8_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_8_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_8_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_8_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_8_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_8_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_8_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_8_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_8_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_8_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_8_fp_ctrl_div; // @[util.scala:505:22]
reg uops_8_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_8_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_8_fp_ctrl_vec; // @[util.scala:505:22]
reg [6:0] uops_8_rob_idx; // @[util.scala:505:22]
reg [4:0] uops_8_ldq_idx; // @[util.scala:505:22]
reg [4:0] uops_8_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_8_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_8_pdst; // @[util.scala:505:22]
reg [6:0] uops_8_prs1; // @[util.scala:505:22]
reg [6:0] uops_8_prs2; // @[util.scala:505:22]
reg [6:0] uops_8_prs3; // @[util.scala:505:22]
reg [4:0] uops_8_ppred; // @[util.scala:505:22]
reg uops_8_prs1_busy; // @[util.scala:505:22]
reg uops_8_prs2_busy; // @[util.scala:505:22]
reg uops_8_prs3_busy; // @[util.scala:505:22]
reg uops_8_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_8_stale_pdst; // @[util.scala:505:22]
reg uops_8_exception; // @[util.scala:505:22]
reg [63:0] uops_8_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_8_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_8_mem_size; // @[util.scala:505:22]
reg uops_8_mem_signed; // @[util.scala:505:22]
reg uops_8_uses_ldq; // @[util.scala:505:22]
reg uops_8_uses_stq; // @[util.scala:505:22]
reg uops_8_is_unique; // @[util.scala:505:22]
reg uops_8_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_8_csr_cmd; // @[util.scala:505:22]
reg uops_8_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_8_ldst; // @[util.scala:505:22]
reg [5:0] uops_8_lrs1; // @[util.scala:505:22]
reg [5:0] uops_8_lrs2; // @[util.scala:505:22]
reg [5:0] uops_8_lrs3; // @[util.scala:505:22]
reg [1:0] uops_8_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_8_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_8_lrs2_rtype; // @[util.scala:505:22]
reg uops_8_frs3_en; // @[util.scala:505:22]
reg uops_8_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_8_fcn_op; // @[util.scala:505:22]
reg uops_8_fp_val; // @[util.scala:505:22]
reg [2:0] uops_8_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_8_fp_typ; // @[util.scala:505:22]
reg uops_8_xcpt_pf_if; // @[util.scala:505:22]
reg uops_8_xcpt_ae_if; // @[util.scala:505:22]
reg uops_8_xcpt_ma_if; // @[util.scala:505:22]
reg uops_8_bp_debug_if; // @[util.scala:505:22]
reg uops_8_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_8_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_8_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_9_inst; // @[util.scala:505:22]
reg [31:0] uops_9_debug_inst; // @[util.scala:505:22]
reg uops_9_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_9_debug_pc; // @[util.scala:505:22]
reg uops_9_iq_type_0; // @[util.scala:505:22]
reg uops_9_iq_type_1; // @[util.scala:505:22]
reg uops_9_iq_type_2; // @[util.scala:505:22]
reg uops_9_iq_type_3; // @[util.scala:505:22]
reg uops_9_fu_code_0; // @[util.scala:505:22]
reg uops_9_fu_code_1; // @[util.scala:505:22]
reg uops_9_fu_code_2; // @[util.scala:505:22]
reg uops_9_fu_code_3; // @[util.scala:505:22]
reg uops_9_fu_code_4; // @[util.scala:505:22]
reg uops_9_fu_code_5; // @[util.scala:505:22]
reg uops_9_fu_code_6; // @[util.scala:505:22]
reg uops_9_fu_code_7; // @[util.scala:505:22]
reg uops_9_fu_code_8; // @[util.scala:505:22]
reg uops_9_fu_code_9; // @[util.scala:505:22]
reg uops_9_iw_issued; // @[util.scala:505:22]
reg uops_9_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_9_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [2:0] uops_9_iw_p1_speculative_child; // @[util.scala:505:22]
reg [2:0] uops_9_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_9_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_9_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_9_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [2:0] uops_9_dis_col_sel; // @[util.scala:505:22]
reg [15:0] uops_9_br_mask; // @[util.scala:505:22]
reg [3:0] uops_9_br_tag; // @[util.scala:505:22]
reg [3:0] uops_9_br_type; // @[util.scala:505:22]
reg uops_9_is_sfb; // @[util.scala:505:22]
reg uops_9_is_fence; // @[util.scala:505:22]
reg uops_9_is_fencei; // @[util.scala:505:22]
reg uops_9_is_sfence; // @[util.scala:505:22]
reg uops_9_is_amo; // @[util.scala:505:22]
reg uops_9_is_eret; // @[util.scala:505:22]
reg uops_9_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_9_is_rocc; // @[util.scala:505:22]
reg uops_9_is_mov; // @[util.scala:505:22]
reg [4:0] uops_9_ftq_idx; // @[util.scala:505:22]
reg uops_9_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_9_pc_lob; // @[util.scala:505:22]
reg uops_9_taken; // @[util.scala:505:22]
reg uops_9_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_9_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_9_pimm; // @[util.scala:505:22]
reg [19:0] uops_9_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_9_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_9_op2_sel; // @[util.scala:505:22]
reg uops_9_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_9_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_9_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_9_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_9_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_9_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_9_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_9_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_9_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_9_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_9_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_9_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_9_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_9_fp_ctrl_div; // @[util.scala:505:22]
reg uops_9_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_9_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_9_fp_ctrl_vec; // @[util.scala:505:22]
reg [6:0] uops_9_rob_idx; // @[util.scala:505:22]
reg [4:0] uops_9_ldq_idx; // @[util.scala:505:22]
reg [4:0] uops_9_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_9_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_9_pdst; // @[util.scala:505:22]
reg [6:0] uops_9_prs1; // @[util.scala:505:22]
reg [6:0] uops_9_prs2; // @[util.scala:505:22]
reg [6:0] uops_9_prs3; // @[util.scala:505:22]
reg [4:0] uops_9_ppred; // @[util.scala:505:22]
reg uops_9_prs1_busy; // @[util.scala:505:22]
reg uops_9_prs2_busy; // @[util.scala:505:22]
reg uops_9_prs3_busy; // @[util.scala:505:22]
reg uops_9_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_9_stale_pdst; // @[util.scala:505:22]
reg uops_9_exception; // @[util.scala:505:22]
reg [63:0] uops_9_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_9_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_9_mem_size; // @[util.scala:505:22]
reg uops_9_mem_signed; // @[util.scala:505:22]
reg uops_9_uses_ldq; // @[util.scala:505:22]
reg uops_9_uses_stq; // @[util.scala:505:22]
reg uops_9_is_unique; // @[util.scala:505:22]
reg uops_9_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_9_csr_cmd; // @[util.scala:505:22]
reg uops_9_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_9_ldst; // @[util.scala:505:22]
reg [5:0] uops_9_lrs1; // @[util.scala:505:22]
reg [5:0] uops_9_lrs2; // @[util.scala:505:22]
reg [5:0] uops_9_lrs3; // @[util.scala:505:22]
reg [1:0] uops_9_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_9_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_9_lrs2_rtype; // @[util.scala:505:22]
reg uops_9_frs3_en; // @[util.scala:505:22]
reg uops_9_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_9_fcn_op; // @[util.scala:505:22]
reg uops_9_fp_val; // @[util.scala:505:22]
reg [2:0] uops_9_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_9_fp_typ; // @[util.scala:505:22]
reg uops_9_xcpt_pf_if; // @[util.scala:505:22]
reg uops_9_xcpt_ae_if; // @[util.scala:505:22]
reg uops_9_xcpt_ma_if; // @[util.scala:505:22]
reg uops_9_bp_debug_if; // @[util.scala:505:22]
reg uops_9_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_9_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_9_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_10_inst; // @[util.scala:505:22]
reg [31:0] uops_10_debug_inst; // @[util.scala:505:22]
reg uops_10_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_10_debug_pc; // @[util.scala:505:22]
reg uops_10_iq_type_0; // @[util.scala:505:22]
reg uops_10_iq_type_1; // @[util.scala:505:22]
reg uops_10_iq_type_2; // @[util.scala:505:22]
reg uops_10_iq_type_3; // @[util.scala:505:22]
reg uops_10_fu_code_0; // @[util.scala:505:22]
reg uops_10_fu_code_1; // @[util.scala:505:22]
reg uops_10_fu_code_2; // @[util.scala:505:22]
reg uops_10_fu_code_3; // @[util.scala:505:22]
reg uops_10_fu_code_4; // @[util.scala:505:22]
reg uops_10_fu_code_5; // @[util.scala:505:22]
reg uops_10_fu_code_6; // @[util.scala:505:22]
reg uops_10_fu_code_7; // @[util.scala:505:22]
reg uops_10_fu_code_8; // @[util.scala:505:22]
reg uops_10_fu_code_9; // @[util.scala:505:22]
reg uops_10_iw_issued; // @[util.scala:505:22]
reg uops_10_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_10_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [2:0] uops_10_iw_p1_speculative_child; // @[util.scala:505:22]
reg [2:0] uops_10_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_10_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_10_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_10_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [2:0] uops_10_dis_col_sel; // @[util.scala:505:22]
reg [15:0] uops_10_br_mask; // @[util.scala:505:22]
reg [3:0] uops_10_br_tag; // @[util.scala:505:22]
reg [3:0] uops_10_br_type; // @[util.scala:505:22]
reg uops_10_is_sfb; // @[util.scala:505:22]
reg uops_10_is_fence; // @[util.scala:505:22]
reg uops_10_is_fencei; // @[util.scala:505:22]
reg uops_10_is_sfence; // @[util.scala:505:22]
reg uops_10_is_amo; // @[util.scala:505:22]
reg uops_10_is_eret; // @[util.scala:505:22]
reg uops_10_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_10_is_rocc; // @[util.scala:505:22]
reg uops_10_is_mov; // @[util.scala:505:22]
reg [4:0] uops_10_ftq_idx; // @[util.scala:505:22]
reg uops_10_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_10_pc_lob; // @[util.scala:505:22]
reg uops_10_taken; // @[util.scala:505:22]
reg uops_10_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_10_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_10_pimm; // @[util.scala:505:22]
reg [19:0] uops_10_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_10_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_10_op2_sel; // @[util.scala:505:22]
reg uops_10_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_10_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_10_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_10_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_10_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_10_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_10_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_10_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_10_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_10_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_10_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_10_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_10_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_10_fp_ctrl_div; // @[util.scala:505:22]
reg uops_10_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_10_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_10_fp_ctrl_vec; // @[util.scala:505:22]
reg [6:0] uops_10_rob_idx; // @[util.scala:505:22]
reg [4:0] uops_10_ldq_idx; // @[util.scala:505:22]
reg [4:0] uops_10_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_10_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_10_pdst; // @[util.scala:505:22]
reg [6:0] uops_10_prs1; // @[util.scala:505:22]
reg [6:0] uops_10_prs2; // @[util.scala:505:22]
reg [6:0] uops_10_prs3; // @[util.scala:505:22]
reg [4:0] uops_10_ppred; // @[util.scala:505:22]
reg uops_10_prs1_busy; // @[util.scala:505:22]
reg uops_10_prs2_busy; // @[util.scala:505:22]
reg uops_10_prs3_busy; // @[util.scala:505:22]
reg uops_10_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_10_stale_pdst; // @[util.scala:505:22]
reg uops_10_exception; // @[util.scala:505:22]
reg [63:0] uops_10_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_10_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_10_mem_size; // @[util.scala:505:22]
reg uops_10_mem_signed; // @[util.scala:505:22]
reg uops_10_uses_ldq; // @[util.scala:505:22]
reg uops_10_uses_stq; // @[util.scala:505:22]
reg uops_10_is_unique; // @[util.scala:505:22]
reg uops_10_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_10_csr_cmd; // @[util.scala:505:22]
reg uops_10_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_10_ldst; // @[util.scala:505:22]
reg [5:0] uops_10_lrs1; // @[util.scala:505:22]
reg [5:0] uops_10_lrs2; // @[util.scala:505:22]
reg [5:0] uops_10_lrs3; // @[util.scala:505:22]
reg [1:0] uops_10_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_10_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_10_lrs2_rtype; // @[util.scala:505:22]
reg uops_10_frs3_en; // @[util.scala:505:22]
reg uops_10_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_10_fcn_op; // @[util.scala:505:22]
reg uops_10_fp_val; // @[util.scala:505:22]
reg [2:0] uops_10_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_10_fp_typ; // @[util.scala:505:22]
reg uops_10_xcpt_pf_if; // @[util.scala:505:22]
reg uops_10_xcpt_ae_if; // @[util.scala:505:22]
reg uops_10_xcpt_ma_if; // @[util.scala:505:22]
reg uops_10_bp_debug_if; // @[util.scala:505:22]
reg uops_10_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_10_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_10_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_11_inst; // @[util.scala:505:22]
reg [31:0] uops_11_debug_inst; // @[util.scala:505:22]
reg uops_11_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_11_debug_pc; // @[util.scala:505:22]
reg uops_11_iq_type_0; // @[util.scala:505:22]
reg uops_11_iq_type_1; // @[util.scala:505:22]
reg uops_11_iq_type_2; // @[util.scala:505:22]
reg uops_11_iq_type_3; // @[util.scala:505:22]
reg uops_11_fu_code_0; // @[util.scala:505:22]
reg uops_11_fu_code_1; // @[util.scala:505:22]
reg uops_11_fu_code_2; // @[util.scala:505:22]
reg uops_11_fu_code_3; // @[util.scala:505:22]
reg uops_11_fu_code_4; // @[util.scala:505:22]
reg uops_11_fu_code_5; // @[util.scala:505:22]
reg uops_11_fu_code_6; // @[util.scala:505:22]
reg uops_11_fu_code_7; // @[util.scala:505:22]
reg uops_11_fu_code_8; // @[util.scala:505:22]
reg uops_11_fu_code_9; // @[util.scala:505:22]
reg uops_11_iw_issued; // @[util.scala:505:22]
reg uops_11_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_11_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [2:0] uops_11_iw_p1_speculative_child; // @[util.scala:505:22]
reg [2:0] uops_11_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_11_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_11_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_11_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [2:0] uops_11_dis_col_sel; // @[util.scala:505:22]
reg [15:0] uops_11_br_mask; // @[util.scala:505:22]
reg [3:0] uops_11_br_tag; // @[util.scala:505:22]
reg [3:0] uops_11_br_type; // @[util.scala:505:22]
reg uops_11_is_sfb; // @[util.scala:505:22]
reg uops_11_is_fence; // @[util.scala:505:22]
reg uops_11_is_fencei; // @[util.scala:505:22]
reg uops_11_is_sfence; // @[util.scala:505:22]
reg uops_11_is_amo; // @[util.scala:505:22]
reg uops_11_is_eret; // @[util.scala:505:22]
reg uops_11_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_11_is_rocc; // @[util.scala:505:22]
reg uops_11_is_mov; // @[util.scala:505:22]
reg [4:0] uops_11_ftq_idx; // @[util.scala:505:22]
reg uops_11_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_11_pc_lob; // @[util.scala:505:22]
reg uops_11_taken; // @[util.scala:505:22]
reg uops_11_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_11_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_11_pimm; // @[util.scala:505:22]
reg [19:0] uops_11_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_11_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_11_op2_sel; // @[util.scala:505:22]
reg uops_11_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_11_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_11_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_11_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_11_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_11_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_11_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_11_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_11_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_11_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_11_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_11_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_11_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_11_fp_ctrl_div; // @[util.scala:505:22]
reg uops_11_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_11_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_11_fp_ctrl_vec; // @[util.scala:505:22]
reg [6:0] uops_11_rob_idx; // @[util.scala:505:22]
reg [4:0] uops_11_ldq_idx; // @[util.scala:505:22]
reg [4:0] uops_11_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_11_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_11_pdst; // @[util.scala:505:22]
reg [6:0] uops_11_prs1; // @[util.scala:505:22]
reg [6:0] uops_11_prs2; // @[util.scala:505:22]
reg [6:0] uops_11_prs3; // @[util.scala:505:22]
reg [4:0] uops_11_ppred; // @[util.scala:505:22]
reg uops_11_prs1_busy; // @[util.scala:505:22]
reg uops_11_prs2_busy; // @[util.scala:505:22]
reg uops_11_prs3_busy; // @[util.scala:505:22]
reg uops_11_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_11_stale_pdst; // @[util.scala:505:22]
reg uops_11_exception; // @[util.scala:505:22]
reg [63:0] uops_11_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_11_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_11_mem_size; // @[util.scala:505:22]
reg uops_11_mem_signed; // @[util.scala:505:22]
reg uops_11_uses_ldq; // @[util.scala:505:22]
reg uops_11_uses_stq; // @[util.scala:505:22]
reg uops_11_is_unique; // @[util.scala:505:22]
reg uops_11_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_11_csr_cmd; // @[util.scala:505:22]
reg uops_11_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_11_ldst; // @[util.scala:505:22]
reg [5:0] uops_11_lrs1; // @[util.scala:505:22]
reg [5:0] uops_11_lrs2; // @[util.scala:505:22]
reg [5:0] uops_11_lrs3; // @[util.scala:505:22]
reg [1:0] uops_11_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_11_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_11_lrs2_rtype; // @[util.scala:505:22]
reg uops_11_frs3_en; // @[util.scala:505:22]
reg uops_11_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_11_fcn_op; // @[util.scala:505:22]
reg uops_11_fp_val; // @[util.scala:505:22]
reg [2:0] uops_11_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_11_fp_typ; // @[util.scala:505:22]
reg uops_11_xcpt_pf_if; // @[util.scala:505:22]
reg uops_11_xcpt_ae_if; // @[util.scala:505:22]
reg uops_11_xcpt_ma_if; // @[util.scala:505:22]
reg uops_11_bp_debug_if; // @[util.scala:505:22]
reg uops_11_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_11_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_11_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_12_inst; // @[util.scala:505:22]
reg [31:0] uops_12_debug_inst; // @[util.scala:505:22]
reg uops_12_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_12_debug_pc; // @[util.scala:505:22]
reg uops_12_iq_type_0; // @[util.scala:505:22]
reg uops_12_iq_type_1; // @[util.scala:505:22]
reg uops_12_iq_type_2; // @[util.scala:505:22]
reg uops_12_iq_type_3; // @[util.scala:505:22]
reg uops_12_fu_code_0; // @[util.scala:505:22]
reg uops_12_fu_code_1; // @[util.scala:505:22]
reg uops_12_fu_code_2; // @[util.scala:505:22]
reg uops_12_fu_code_3; // @[util.scala:505:22]
reg uops_12_fu_code_4; // @[util.scala:505:22]
reg uops_12_fu_code_5; // @[util.scala:505:22]
reg uops_12_fu_code_6; // @[util.scala:505:22]
reg uops_12_fu_code_7; // @[util.scala:505:22]
reg uops_12_fu_code_8; // @[util.scala:505:22]
reg uops_12_fu_code_9; // @[util.scala:505:22]
reg uops_12_iw_issued; // @[util.scala:505:22]
reg uops_12_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_12_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [2:0] uops_12_iw_p1_speculative_child; // @[util.scala:505:22]
reg [2:0] uops_12_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_12_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_12_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_12_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [2:0] uops_12_dis_col_sel; // @[util.scala:505:22]
reg [15:0] uops_12_br_mask; // @[util.scala:505:22]
reg [3:0] uops_12_br_tag; // @[util.scala:505:22]
reg [3:0] uops_12_br_type; // @[util.scala:505:22]
reg uops_12_is_sfb; // @[util.scala:505:22]
reg uops_12_is_fence; // @[util.scala:505:22]
reg uops_12_is_fencei; // @[util.scala:505:22]
reg uops_12_is_sfence; // @[util.scala:505:22]
reg uops_12_is_amo; // @[util.scala:505:22]
reg uops_12_is_eret; // @[util.scala:505:22]
reg uops_12_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_12_is_rocc; // @[util.scala:505:22]
reg uops_12_is_mov; // @[util.scala:505:22]
reg [4:0] uops_12_ftq_idx; // @[util.scala:505:22]
reg uops_12_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_12_pc_lob; // @[util.scala:505:22]
reg uops_12_taken; // @[util.scala:505:22]
reg uops_12_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_12_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_12_pimm; // @[util.scala:505:22]
reg [19:0] uops_12_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_12_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_12_op2_sel; // @[util.scala:505:22]
reg uops_12_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_12_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_12_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_12_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_12_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_12_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_12_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_12_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_12_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_12_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_12_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_12_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_12_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_12_fp_ctrl_div; // @[util.scala:505:22]
reg uops_12_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_12_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_12_fp_ctrl_vec; // @[util.scala:505:22]
reg [6:0] uops_12_rob_idx; // @[util.scala:505:22]
reg [4:0] uops_12_ldq_idx; // @[util.scala:505:22]
reg [4:0] uops_12_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_12_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_12_pdst; // @[util.scala:505:22]
reg [6:0] uops_12_prs1; // @[util.scala:505:22]
reg [6:0] uops_12_prs2; // @[util.scala:505:22]
reg [6:0] uops_12_prs3; // @[util.scala:505:22]
reg [4:0] uops_12_ppred; // @[util.scala:505:22]
reg uops_12_prs1_busy; // @[util.scala:505:22]
reg uops_12_prs2_busy; // @[util.scala:505:22]
reg uops_12_prs3_busy; // @[util.scala:505:22]
reg uops_12_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_12_stale_pdst; // @[util.scala:505:22]
reg uops_12_exception; // @[util.scala:505:22]
reg [63:0] uops_12_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_12_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_12_mem_size; // @[util.scala:505:22]
reg uops_12_mem_signed; // @[util.scala:505:22]
reg uops_12_uses_ldq; // @[util.scala:505:22]
reg uops_12_uses_stq; // @[util.scala:505:22]
reg uops_12_is_unique; // @[util.scala:505:22]
reg uops_12_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_12_csr_cmd; // @[util.scala:505:22]
reg uops_12_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_12_ldst; // @[util.scala:505:22]
reg [5:0] uops_12_lrs1; // @[util.scala:505:22]
reg [5:0] uops_12_lrs2; // @[util.scala:505:22]
reg [5:0] uops_12_lrs3; // @[util.scala:505:22]
reg [1:0] uops_12_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_12_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_12_lrs2_rtype; // @[util.scala:505:22]
reg uops_12_frs3_en; // @[util.scala:505:22]
reg uops_12_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_12_fcn_op; // @[util.scala:505:22]
reg uops_12_fp_val; // @[util.scala:505:22]
reg [2:0] uops_12_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_12_fp_typ; // @[util.scala:505:22]
reg uops_12_xcpt_pf_if; // @[util.scala:505:22]
reg uops_12_xcpt_ae_if; // @[util.scala:505:22]
reg uops_12_xcpt_ma_if; // @[util.scala:505:22]
reg uops_12_bp_debug_if; // @[util.scala:505:22]
reg uops_12_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_12_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_12_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_13_inst; // @[util.scala:505:22]
reg [31:0] uops_13_debug_inst; // @[util.scala:505:22]
reg uops_13_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_13_debug_pc; // @[util.scala:505:22]
reg uops_13_iq_type_0; // @[util.scala:505:22]
reg uops_13_iq_type_1; // @[util.scala:505:22]
reg uops_13_iq_type_2; // @[util.scala:505:22]
reg uops_13_iq_type_3; // @[util.scala:505:22]
reg uops_13_fu_code_0; // @[util.scala:505:22]
reg uops_13_fu_code_1; // @[util.scala:505:22]
reg uops_13_fu_code_2; // @[util.scala:505:22]
reg uops_13_fu_code_3; // @[util.scala:505:22]
reg uops_13_fu_code_4; // @[util.scala:505:22]
reg uops_13_fu_code_5; // @[util.scala:505:22]
reg uops_13_fu_code_6; // @[util.scala:505:22]
reg uops_13_fu_code_7; // @[util.scala:505:22]
reg uops_13_fu_code_8; // @[util.scala:505:22]
reg uops_13_fu_code_9; // @[util.scala:505:22]
reg uops_13_iw_issued; // @[util.scala:505:22]
reg uops_13_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_13_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [2:0] uops_13_iw_p1_speculative_child; // @[util.scala:505:22]
reg [2:0] uops_13_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_13_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_13_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_13_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [2:0] uops_13_dis_col_sel; // @[util.scala:505:22]
reg [15:0] uops_13_br_mask; // @[util.scala:505:22]
reg [3:0] uops_13_br_tag; // @[util.scala:505:22]
reg [3:0] uops_13_br_type; // @[util.scala:505:22]
reg uops_13_is_sfb; // @[util.scala:505:22]
reg uops_13_is_fence; // @[util.scala:505:22]
reg uops_13_is_fencei; // @[util.scala:505:22]
reg uops_13_is_sfence; // @[util.scala:505:22]
reg uops_13_is_amo; // @[util.scala:505:22]
reg uops_13_is_eret; // @[util.scala:505:22]
reg uops_13_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_13_is_rocc; // @[util.scala:505:22]
reg uops_13_is_mov; // @[util.scala:505:22]
reg [4:0] uops_13_ftq_idx; // @[util.scala:505:22]
reg uops_13_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_13_pc_lob; // @[util.scala:505:22]
reg uops_13_taken; // @[util.scala:505:22]
reg uops_13_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_13_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_13_pimm; // @[util.scala:505:22]
reg [19:0] uops_13_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_13_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_13_op2_sel; // @[util.scala:505:22]
reg uops_13_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_13_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_13_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_13_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_13_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_13_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_13_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_13_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_13_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_13_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_13_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_13_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_13_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_13_fp_ctrl_div; // @[util.scala:505:22]
reg uops_13_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_13_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_13_fp_ctrl_vec; // @[util.scala:505:22]
reg [6:0] uops_13_rob_idx; // @[util.scala:505:22]
reg [4:0] uops_13_ldq_idx; // @[util.scala:505:22]
reg [4:0] uops_13_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_13_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_13_pdst; // @[util.scala:505:22]
reg [6:0] uops_13_prs1; // @[util.scala:505:22]
reg [6:0] uops_13_prs2; // @[util.scala:505:22]
reg [6:0] uops_13_prs3; // @[util.scala:505:22]
reg [4:0] uops_13_ppred; // @[util.scala:505:22]
reg uops_13_prs1_busy; // @[util.scala:505:22]
reg uops_13_prs2_busy; // @[util.scala:505:22]
reg uops_13_prs3_busy; // @[util.scala:505:22]
reg uops_13_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_13_stale_pdst; // @[util.scala:505:22]
reg uops_13_exception; // @[util.scala:505:22]
reg [63:0] uops_13_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_13_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_13_mem_size; // @[util.scala:505:22]
reg uops_13_mem_signed; // @[util.scala:505:22]
reg uops_13_uses_ldq; // @[util.scala:505:22]
reg uops_13_uses_stq; // @[util.scala:505:22]
reg uops_13_is_unique; // @[util.scala:505:22]
reg uops_13_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_13_csr_cmd; // @[util.scala:505:22]
reg uops_13_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_13_ldst; // @[util.scala:505:22]
reg [5:0] uops_13_lrs1; // @[util.scala:505:22]
reg [5:0] uops_13_lrs2; // @[util.scala:505:22]
reg [5:0] uops_13_lrs3; // @[util.scala:505:22]
reg [1:0] uops_13_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_13_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_13_lrs2_rtype; // @[util.scala:505:22]
reg uops_13_frs3_en; // @[util.scala:505:22]
reg uops_13_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_13_fcn_op; // @[util.scala:505:22]
reg uops_13_fp_val; // @[util.scala:505:22]
reg [2:0] uops_13_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_13_fp_typ; // @[util.scala:505:22]
reg uops_13_xcpt_pf_if; // @[util.scala:505:22]
reg uops_13_xcpt_ae_if; // @[util.scala:505:22]
reg uops_13_xcpt_ma_if; // @[util.scala:505:22]
reg uops_13_bp_debug_if; // @[util.scala:505:22]
reg uops_13_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_13_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_13_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_14_inst; // @[util.scala:505:22]
reg [31:0] uops_14_debug_inst; // @[util.scala:505:22]
reg uops_14_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_14_debug_pc; // @[util.scala:505:22]
reg uops_14_iq_type_0; // @[util.scala:505:22]
reg uops_14_iq_type_1; // @[util.scala:505:22]
reg uops_14_iq_type_2; // @[util.scala:505:22]
reg uops_14_iq_type_3; // @[util.scala:505:22]
reg uops_14_fu_code_0; // @[util.scala:505:22]
reg uops_14_fu_code_1; // @[util.scala:505:22]
reg uops_14_fu_code_2; // @[util.scala:505:22]
reg uops_14_fu_code_3; // @[util.scala:505:22]
reg uops_14_fu_code_4; // @[util.scala:505:22]
reg uops_14_fu_code_5; // @[util.scala:505:22]
reg uops_14_fu_code_6; // @[util.scala:505:22]
reg uops_14_fu_code_7; // @[util.scala:505:22]
reg uops_14_fu_code_8; // @[util.scala:505:22]
reg uops_14_fu_code_9; // @[util.scala:505:22]
reg uops_14_iw_issued; // @[util.scala:505:22]
reg uops_14_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_14_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [2:0] uops_14_iw_p1_speculative_child; // @[util.scala:505:22]
reg [2:0] uops_14_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_14_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_14_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_14_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [2:0] uops_14_dis_col_sel; // @[util.scala:505:22]
reg [15:0] uops_14_br_mask; // @[util.scala:505:22]
reg [3:0] uops_14_br_tag; // @[util.scala:505:22]
reg [3:0] uops_14_br_type; // @[util.scala:505:22]
reg uops_14_is_sfb; // @[util.scala:505:22]
reg uops_14_is_fence; // @[util.scala:505:22]
reg uops_14_is_fencei; // @[util.scala:505:22]
reg uops_14_is_sfence; // @[util.scala:505:22]
reg uops_14_is_amo; // @[util.scala:505:22]
reg uops_14_is_eret; // @[util.scala:505:22]
reg uops_14_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_14_is_rocc; // @[util.scala:505:22]
reg uops_14_is_mov; // @[util.scala:505:22]
reg [4:0] uops_14_ftq_idx; // @[util.scala:505:22]
reg uops_14_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_14_pc_lob; // @[util.scala:505:22]
reg uops_14_taken; // @[util.scala:505:22]
reg uops_14_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_14_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_14_pimm; // @[util.scala:505:22]
reg [19:0] uops_14_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_14_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_14_op2_sel; // @[util.scala:505:22]
reg uops_14_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_14_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_14_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_14_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_14_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_14_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_14_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_14_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_14_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_14_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_14_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_14_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_14_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_14_fp_ctrl_div; // @[util.scala:505:22]
reg uops_14_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_14_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_14_fp_ctrl_vec; // @[util.scala:505:22]
reg [6:0] uops_14_rob_idx; // @[util.scala:505:22]
reg [4:0] uops_14_ldq_idx; // @[util.scala:505:22]
reg [4:0] uops_14_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_14_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_14_pdst; // @[util.scala:505:22]
reg [6:0] uops_14_prs1; // @[util.scala:505:22]
reg [6:0] uops_14_prs2; // @[util.scala:505:22]
reg [6:0] uops_14_prs3; // @[util.scala:505:22]
reg [4:0] uops_14_ppred; // @[util.scala:505:22]
reg uops_14_prs1_busy; // @[util.scala:505:22]
reg uops_14_prs2_busy; // @[util.scala:505:22]
reg uops_14_prs3_busy; // @[util.scala:505:22]
reg uops_14_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_14_stale_pdst; // @[util.scala:505:22]
reg uops_14_exception; // @[util.scala:505:22]
reg [63:0] uops_14_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_14_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_14_mem_size; // @[util.scala:505:22]
reg uops_14_mem_signed; // @[util.scala:505:22]
reg uops_14_uses_ldq; // @[util.scala:505:22]
reg uops_14_uses_stq; // @[util.scala:505:22]
reg uops_14_is_unique; // @[util.scala:505:22]
reg uops_14_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_14_csr_cmd; // @[util.scala:505:22]
reg uops_14_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_14_ldst; // @[util.scala:505:22]
reg [5:0] uops_14_lrs1; // @[util.scala:505:22]
reg [5:0] uops_14_lrs2; // @[util.scala:505:22]
reg [5:0] uops_14_lrs3; // @[util.scala:505:22]
reg [1:0] uops_14_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_14_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_14_lrs2_rtype; // @[util.scala:505:22]
reg uops_14_frs3_en; // @[util.scala:505:22]
reg uops_14_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_14_fcn_op; // @[util.scala:505:22]
reg uops_14_fp_val; // @[util.scala:505:22]
reg [2:0] uops_14_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_14_fp_typ; // @[util.scala:505:22]
reg uops_14_xcpt_pf_if; // @[util.scala:505:22]
reg uops_14_xcpt_ae_if; // @[util.scala:505:22]
reg uops_14_xcpt_ma_if; // @[util.scala:505:22]
reg uops_14_bp_debug_if; // @[util.scala:505:22]
reg uops_14_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_14_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_14_debug_tsrc; // @[util.scala:505:22]
reg [3:0] enq_ptr_value; // @[Counter.scala:61:40]
reg [3:0] deq_ptr_value; // @[Counter.scala:61:40]
reg maybe_full; // @[util.scala:509:29]
wire ptr_match = enq_ptr_value == deq_ptr_value; // @[Counter.scala:61:40]
wire _io_empty_T = ~maybe_full; // @[util.scala:509:29, :512:30]
assign _io_empty_T_1 = ptr_match & _io_empty_T; // @[util.scala:511:35, :512:{27,30}]
assign io_empty_0 = _io_empty_T_1; // @[util.scala:458:7, :512:27]
wire full = ptr_match & maybe_full; // @[util.scala:509:29, :511:35, :513:26]
wire _do_enq_T = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35]
wire [15:0] _do_enq_T_1 = io_brupdate_b1_mispredict_mask_0 & io_enq_bits_uop_br_mask_0; // @[util.scala:126:51, :458:7]
wire _do_enq_T_2 = |_do_enq_T_1; // @[util.scala:126:{51,59}]
wire _do_enq_T_3 = _do_enq_T_2; // @[util.scala:61:61, :126:59]
wire _do_enq_T_4 = ~_do_enq_T_3; // @[util.scala:61:61, :514:42]
wire _do_enq_T_5 = _do_enq_T & _do_enq_T_4; // @[Decoupled.scala:51:35]
wire _do_enq_T_6 = io_flush_0 & io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :514:113]
wire _do_enq_T_7 = ~_do_enq_T_6; // @[util.scala:514:{102,113}]
wire _do_enq_T_8 = _do_enq_T_5 & _do_enq_T_7; // @[util.scala:514:{39,99,102}]
wire do_enq = _do_enq_T_8; // @[util.scala:514:{26,99}]
wire [15:0] _GEN = {{valids_0}, {valids_14}, {valids_13}, {valids_12}, {valids_11}, {valids_10}, {valids_9}, {valids_8}, {valids_7}, {valids_6}, {valids_5}, {valids_4}, {valids_3}, {valids_2}, {valids_1}, {valids_0}}; // @[util.scala:504:26, :515:44]
wire _GEN_0 = _GEN[deq_ptr_value]; // @[Counter.scala:61:40]
wire _do_deq_T = ~_GEN_0; // @[util.scala:515:44]
wire _do_deq_T_1 = io_deq_ready_0 | _do_deq_T; // @[util.scala:458:7, :515:{41,44}]
wire _do_deq_T_2 = ~io_empty_0; // @[util.scala:458:7, :515:71]
wire _do_deq_T_3 = _do_deq_T_1 & _do_deq_T_2; // @[util.scala:515:{41,68,71}]
wire do_deq = _do_deq_T_3; // @[util.scala:515:{26,68}]
wire [15:0] _valids_0_T = io_brupdate_b1_mispredict_mask_0 & uops_0_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_0_T_1 = |_valids_0_T; // @[util.scala:126:{51,59}]
wire _valids_0_T_2 = _valids_0_T_1; // @[util.scala:61:61, :126:59]
wire _valids_0_T_3 = ~_valids_0_T_2; // @[util.scala:61:61, :520:34]
wire _valids_0_T_4 = valids_0 & _valids_0_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_0_T_5 = io_flush_0 & uops_0_uses_ldq; // @[util.scala:458:7, :505:22, :520:94]
wire _valids_0_T_6 = ~_valids_0_T_5; // @[util.scala:520:{83,94}]
wire _valids_0_T_7 = _valids_0_T_4 & _valids_0_T_6; // @[util.scala:520:{31,80,83}]
wire [15:0] _uops_0_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [15:0] _uops_0_br_mask_T_1 = uops_0_br_mask & _uops_0_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [15:0] _valids_1_T = io_brupdate_b1_mispredict_mask_0 & uops_1_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_1_T_1 = |_valids_1_T; // @[util.scala:126:{51,59}]
wire _valids_1_T_2 = _valids_1_T_1; // @[util.scala:61:61, :126:59]
wire _valids_1_T_3 = ~_valids_1_T_2; // @[util.scala:61:61, :520:34]
wire _valids_1_T_4 = valids_1 & _valids_1_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_1_T_5 = io_flush_0 & uops_1_uses_ldq; // @[util.scala:458:7, :505:22, :520:94]
wire _valids_1_T_6 = ~_valids_1_T_5; // @[util.scala:520:{83,94}]
wire _valids_1_T_7 = _valids_1_T_4 & _valids_1_T_6; // @[util.scala:520:{31,80,83}]
wire [15:0] _uops_1_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [15:0] _uops_1_br_mask_T_1 = uops_1_br_mask & _uops_1_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [15:0] _valids_2_T = io_brupdate_b1_mispredict_mask_0 & uops_2_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_2_T_1 = |_valids_2_T; // @[util.scala:126:{51,59}]
wire _valids_2_T_2 = _valids_2_T_1; // @[util.scala:61:61, :126:59]
wire _valids_2_T_3 = ~_valids_2_T_2; // @[util.scala:61:61, :520:34]
wire _valids_2_T_4 = valids_2 & _valids_2_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_2_T_5 = io_flush_0 & uops_2_uses_ldq; // @[util.scala:458:7, :505:22, :520:94]
wire _valids_2_T_6 = ~_valids_2_T_5; // @[util.scala:520:{83,94}]
wire _valids_2_T_7 = _valids_2_T_4 & _valids_2_T_6; // @[util.scala:520:{31,80,83}]
wire [15:0] _uops_2_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [15:0] _uops_2_br_mask_T_1 = uops_2_br_mask & _uops_2_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [15:0] _valids_3_T = io_brupdate_b1_mispredict_mask_0 & uops_3_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_3_T_1 = |_valids_3_T; // @[util.scala:126:{51,59}]
wire _valids_3_T_2 = _valids_3_T_1; // @[util.scala:61:61, :126:59]
wire _valids_3_T_3 = ~_valids_3_T_2; // @[util.scala:61:61, :520:34]
wire _valids_3_T_4 = valids_3 & _valids_3_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_3_T_5 = io_flush_0 & uops_3_uses_ldq; // @[util.scala:458:7, :505:22, :520:94]
wire _valids_3_T_6 = ~_valids_3_T_5; // @[util.scala:520:{83,94}]
wire _valids_3_T_7 = _valids_3_T_4 & _valids_3_T_6; // @[util.scala:520:{31,80,83}]
wire [15:0] _uops_3_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [15:0] _uops_3_br_mask_T_1 = uops_3_br_mask & _uops_3_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [15:0] _valids_4_T = io_brupdate_b1_mispredict_mask_0 & uops_4_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_4_T_1 = |_valids_4_T; // @[util.scala:126:{51,59}]
wire _valids_4_T_2 = _valids_4_T_1; // @[util.scala:61:61, :126:59]
wire _valids_4_T_3 = ~_valids_4_T_2; // @[util.scala:61:61, :520:34]
wire _valids_4_T_4 = valids_4 & _valids_4_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_4_T_5 = io_flush_0 & uops_4_uses_ldq; // @[util.scala:458:7, :505:22, :520:94]
wire _valids_4_T_6 = ~_valids_4_T_5; // @[util.scala:520:{83,94}]
wire _valids_4_T_7 = _valids_4_T_4 & _valids_4_T_6; // @[util.scala:520:{31,80,83}]
wire [15:0] _uops_4_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [15:0] _uops_4_br_mask_T_1 = uops_4_br_mask & _uops_4_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [15:0] _valids_5_T = io_brupdate_b1_mispredict_mask_0 & uops_5_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_5_T_1 = |_valids_5_T; // @[util.scala:126:{51,59}]
wire _valids_5_T_2 = _valids_5_T_1; // @[util.scala:61:61, :126:59]
wire _valids_5_T_3 = ~_valids_5_T_2; // @[util.scala:61:61, :520:34]
wire _valids_5_T_4 = valids_5 & _valids_5_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_5_T_5 = io_flush_0 & uops_5_uses_ldq; // @[util.scala:458:7, :505:22, :520:94]
wire _valids_5_T_6 = ~_valids_5_T_5; // @[util.scala:520:{83,94}]
wire _valids_5_T_7 = _valids_5_T_4 & _valids_5_T_6; // @[util.scala:520:{31,80,83}]
wire [15:0] _uops_5_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [15:0] _uops_5_br_mask_T_1 = uops_5_br_mask & _uops_5_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [15:0] _valids_6_T = io_brupdate_b1_mispredict_mask_0 & uops_6_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_6_T_1 = |_valids_6_T; // @[util.scala:126:{51,59}]
wire _valids_6_T_2 = _valids_6_T_1; // @[util.scala:61:61, :126:59]
wire _valids_6_T_3 = ~_valids_6_T_2; // @[util.scala:61:61, :520:34]
wire _valids_6_T_4 = valids_6 & _valids_6_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_6_T_5 = io_flush_0 & uops_6_uses_ldq; // @[util.scala:458:7, :505:22, :520:94]
wire _valids_6_T_6 = ~_valids_6_T_5; // @[util.scala:520:{83,94}]
wire _valids_6_T_7 = _valids_6_T_4 & _valids_6_T_6; // @[util.scala:520:{31,80,83}]
wire [15:0] _uops_6_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [15:0] _uops_6_br_mask_T_1 = uops_6_br_mask & _uops_6_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [15:0] _valids_7_T = io_brupdate_b1_mispredict_mask_0 & uops_7_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_7_T_1 = |_valids_7_T; // @[util.scala:126:{51,59}]
wire _valids_7_T_2 = _valids_7_T_1; // @[util.scala:61:61, :126:59]
wire _valids_7_T_3 = ~_valids_7_T_2; // @[util.scala:61:61, :520:34]
wire _valids_7_T_4 = valids_7 & _valids_7_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_7_T_5 = io_flush_0 & uops_7_uses_ldq; // @[util.scala:458:7, :505:22, :520:94]
wire _valids_7_T_6 = ~_valids_7_T_5; // @[util.scala:520:{83,94}]
wire _valids_7_T_7 = _valids_7_T_4 & _valids_7_T_6; // @[util.scala:520:{31,80,83}]
wire [15:0] _uops_7_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [15:0] _uops_7_br_mask_T_1 = uops_7_br_mask & _uops_7_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [15:0] _valids_8_T = io_brupdate_b1_mispredict_mask_0 & uops_8_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_8_T_1 = |_valids_8_T; // @[util.scala:126:{51,59}]
wire _valids_8_T_2 = _valids_8_T_1; // @[util.scala:61:61, :126:59]
wire _valids_8_T_3 = ~_valids_8_T_2; // @[util.scala:61:61, :520:34]
wire _valids_8_T_4 = valids_8 & _valids_8_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_8_T_5 = io_flush_0 & uops_8_uses_ldq; // @[util.scala:458:7, :505:22, :520:94]
wire _valids_8_T_6 = ~_valids_8_T_5; // @[util.scala:520:{83,94}]
wire _valids_8_T_7 = _valids_8_T_4 & _valids_8_T_6; // @[util.scala:520:{31,80,83}]
wire [15:0] _uops_8_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [15:0] _uops_8_br_mask_T_1 = uops_8_br_mask & _uops_8_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [15:0] _valids_9_T = io_brupdate_b1_mispredict_mask_0 & uops_9_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_9_T_1 = |_valids_9_T; // @[util.scala:126:{51,59}]
wire _valids_9_T_2 = _valids_9_T_1; // @[util.scala:61:61, :126:59]
wire _valids_9_T_3 = ~_valids_9_T_2; // @[util.scala:61:61, :520:34]
wire _valids_9_T_4 = valids_9 & _valids_9_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_9_T_5 = io_flush_0 & uops_9_uses_ldq; // @[util.scala:458:7, :505:22, :520:94]
wire _valids_9_T_6 = ~_valids_9_T_5; // @[util.scala:520:{83,94}]
wire _valids_9_T_7 = _valids_9_T_4 & _valids_9_T_6; // @[util.scala:520:{31,80,83}]
wire [15:0] _uops_9_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [15:0] _uops_9_br_mask_T_1 = uops_9_br_mask & _uops_9_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [15:0] _valids_10_T = io_brupdate_b1_mispredict_mask_0 & uops_10_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_10_T_1 = |_valids_10_T; // @[util.scala:126:{51,59}]
wire _valids_10_T_2 = _valids_10_T_1; // @[util.scala:61:61, :126:59]
wire _valids_10_T_3 = ~_valids_10_T_2; // @[util.scala:61:61, :520:34]
wire _valids_10_T_4 = valids_10 & _valids_10_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_10_T_5 = io_flush_0 & uops_10_uses_ldq; // @[util.scala:458:7, :505:22, :520:94]
wire _valids_10_T_6 = ~_valids_10_T_5; // @[util.scala:520:{83,94}]
wire _valids_10_T_7 = _valids_10_T_4 & _valids_10_T_6; // @[util.scala:520:{31,80,83}]
wire [15:0] _uops_10_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [15:0] _uops_10_br_mask_T_1 = uops_10_br_mask & _uops_10_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [15:0] _valids_11_T = io_brupdate_b1_mispredict_mask_0 & uops_11_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_11_T_1 = |_valids_11_T; // @[util.scala:126:{51,59}]
wire _valids_11_T_2 = _valids_11_T_1; // @[util.scala:61:61, :126:59]
wire _valids_11_T_3 = ~_valids_11_T_2; // @[util.scala:61:61, :520:34]
wire _valids_11_T_4 = valids_11 & _valids_11_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_11_T_5 = io_flush_0 & uops_11_uses_ldq; // @[util.scala:458:7, :505:22, :520:94]
wire _valids_11_T_6 = ~_valids_11_T_5; // @[util.scala:520:{83,94}]
wire _valids_11_T_7 = _valids_11_T_4 & _valids_11_T_6; // @[util.scala:520:{31,80,83}]
wire [15:0] _uops_11_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [15:0] _uops_11_br_mask_T_1 = uops_11_br_mask & _uops_11_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [15:0] _valids_12_T = io_brupdate_b1_mispredict_mask_0 & uops_12_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_12_T_1 = |_valids_12_T; // @[util.scala:126:{51,59}]
wire _valids_12_T_2 = _valids_12_T_1; // @[util.scala:61:61, :126:59]
wire _valids_12_T_3 = ~_valids_12_T_2; // @[util.scala:61:61, :520:34]
wire _valids_12_T_4 = valids_12 & _valids_12_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_12_T_5 = io_flush_0 & uops_12_uses_ldq; // @[util.scala:458:7, :505:22, :520:94]
wire _valids_12_T_6 = ~_valids_12_T_5; // @[util.scala:520:{83,94}]
wire _valids_12_T_7 = _valids_12_T_4 & _valids_12_T_6; // @[util.scala:520:{31,80,83}]
wire [15:0] _uops_12_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [15:0] _uops_12_br_mask_T_1 = uops_12_br_mask & _uops_12_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [15:0] _valids_13_T = io_brupdate_b1_mispredict_mask_0 & uops_13_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_13_T_1 = |_valids_13_T; // @[util.scala:126:{51,59}]
wire _valids_13_T_2 = _valids_13_T_1; // @[util.scala:61:61, :126:59]
wire _valids_13_T_3 = ~_valids_13_T_2; // @[util.scala:61:61, :520:34]
wire _valids_13_T_4 = valids_13 & _valids_13_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_13_T_5 = io_flush_0 & uops_13_uses_ldq; // @[util.scala:458:7, :505:22, :520:94]
wire _valids_13_T_6 = ~_valids_13_T_5; // @[util.scala:520:{83,94}]
wire _valids_13_T_7 = _valids_13_T_4 & _valids_13_T_6; // @[util.scala:520:{31,80,83}]
wire [15:0] _uops_13_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [15:0] _uops_13_br_mask_T_1 = uops_13_br_mask & _uops_13_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [15:0] _valids_14_T = io_brupdate_b1_mispredict_mask_0 & uops_14_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_14_T_1 = |_valids_14_T; // @[util.scala:126:{51,59}]
wire _valids_14_T_2 = _valids_14_T_1; // @[util.scala:61:61, :126:59]
wire _valids_14_T_3 = ~_valids_14_T_2; // @[util.scala:61:61, :520:34]
wire _valids_14_T_4 = valids_14 & _valids_14_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_14_T_5 = io_flush_0 & uops_14_uses_ldq; // @[util.scala:458:7, :505:22, :520:94]
wire _valids_14_T_6 = ~_valids_14_T_5; // @[util.scala:520:{83,94}]
wire _valids_14_T_7 = _valids_14_T_4 & _valids_14_T_6; // @[util.scala:520:{31,80,83}]
wire [15:0] _uops_14_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [15:0] _uops_14_br_mask_T_1 = uops_14_br_mask & _uops_14_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire wrap = enq_ptr_value == 4'hE; // @[Counter.scala:61:40, :73:24]
wire [15:0] _uops_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23, :458:7]
wire [15:0] _uops_br_mask_T_1 = io_enq_bits_uop_br_mask_0 & _uops_br_mask_T; // @[util.scala:93:{25,27}, :458:7]
wire [4:0] _GEN_1 = {1'h0, enq_ptr_value}; // @[Counter.scala:61:40, :77:24]
wire [4:0] _value_T = _GEN_1 + 5'h1; // @[Counter.scala:77:24]
wire [3:0] _value_T_1 = _value_T[3:0]; // @[Counter.scala:77:24]
wire wrap_1 = deq_ptr_value == 4'hE; // @[Counter.scala:61:40, :73:24]
wire [4:0] _GEN_2 = {1'h0, deq_ptr_value}; // @[Counter.scala:61:40, :77:24]
wire [4:0] _value_T_2 = _GEN_2 + 5'h1; // @[Counter.scala:77:24]
wire [3:0] _value_T_3 = _value_T_2[3:0]; // @[Counter.scala:77:24]
assign _io_enq_ready_T = ~full; // @[util.scala:513:26, :543:21]
assign io_enq_ready_0 = _io_enq_ready_T; // @[util.scala:458:7, :543:21]
assign io_deq_bits_uop_inst_0 = out_uop_inst; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_debug_inst_0 = out_uop_debug_inst; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_rvc_0 = out_uop_is_rvc; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_debug_pc_0 = out_uop_debug_pc; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iq_type_0_0 = out_uop_iq_type_0; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iq_type_1_0 = out_uop_iq_type_1; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iq_type_2_0 = out_uop_iq_type_2; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iq_type_3_0 = out_uop_iq_type_3; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_0_0 = out_uop_fu_code_0; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_1_0 = out_uop_fu_code_1; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_2_0 = out_uop_fu_code_2; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_3_0 = out_uop_fu_code_3; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_4_0 = out_uop_fu_code_4; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_5_0 = out_uop_fu_code_5; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_6_0 = out_uop_fu_code_6; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_7_0 = out_uop_fu_code_7; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_8_0 = out_uop_fu_code_8; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_9_0 = out_uop_fu_code_9; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_issued_0 = out_uop_iw_issued; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_issued_partial_agen_0 = out_uop_iw_issued_partial_agen; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_issued_partial_dgen_0 = out_uop_iw_issued_partial_dgen; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_p1_speculative_child_0 = out_uop_iw_p1_speculative_child; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_p2_speculative_child_0 = out_uop_iw_p2_speculative_child; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_p1_bypass_hint_0 = out_uop_iw_p1_bypass_hint; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_p2_bypass_hint_0 = out_uop_iw_p2_bypass_hint; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_p3_bypass_hint_0 = out_uop_iw_p3_bypass_hint; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_dis_col_sel_0 = out_uop_dis_col_sel; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_br_mask_0 = out_uop_br_mask; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_br_tag_0 = out_uop_br_tag; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_br_type_0 = out_uop_br_type; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_sfb_0 = out_uop_is_sfb; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_fence_0 = out_uop_is_fence; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_fencei_0 = out_uop_is_fencei; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_sfence_0 = out_uop_is_sfence; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_amo_0 = out_uop_is_amo; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_eret_0 = out_uop_is_eret; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_sys_pc2epc_0 = out_uop_is_sys_pc2epc; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_rocc_0 = out_uop_is_rocc; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_mov_0 = out_uop_is_mov; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_ftq_idx_0 = out_uop_ftq_idx; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_edge_inst_0 = out_uop_edge_inst; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_pc_lob_0 = out_uop_pc_lob; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_taken_0 = out_uop_taken; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_imm_rename_0 = out_uop_imm_rename; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_imm_sel_0 = out_uop_imm_sel; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_pimm_0 = out_uop_pimm; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_imm_packed_0 = out_uop_imm_packed; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_op1_sel_0 = out_uop_op1_sel; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_op2_sel_0 = out_uop_op2_sel; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_ldst_0 = out_uop_fp_ctrl_ldst; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_wen_0 = out_uop_fp_ctrl_wen; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_ren1_0 = out_uop_fp_ctrl_ren1; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_ren2_0 = out_uop_fp_ctrl_ren2; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_ren3_0 = out_uop_fp_ctrl_ren3; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_swap12_0 = out_uop_fp_ctrl_swap12; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_swap23_0 = out_uop_fp_ctrl_swap23; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_typeTagIn_0 = out_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_typeTagOut_0 = out_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_fromint_0 = out_uop_fp_ctrl_fromint; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_toint_0 = out_uop_fp_ctrl_toint; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_fastpipe_0 = out_uop_fp_ctrl_fastpipe; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_fma_0 = out_uop_fp_ctrl_fma; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_div_0 = out_uop_fp_ctrl_div; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_sqrt_0 = out_uop_fp_ctrl_sqrt; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_wflags_0 = out_uop_fp_ctrl_wflags; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_vec_0 = out_uop_fp_ctrl_vec; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_rob_idx_0 = out_uop_rob_idx; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_ldq_idx_0 = out_uop_ldq_idx; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_stq_idx_0 = out_uop_stq_idx; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_rxq_idx_0 = out_uop_rxq_idx; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_pdst_0 = out_uop_pdst; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_prs1_0 = out_uop_prs1; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_prs2_0 = out_uop_prs2; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_prs3_0 = out_uop_prs3; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_ppred_0 = out_uop_ppred; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_prs1_busy_0 = out_uop_prs1_busy; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_prs2_busy_0 = out_uop_prs2_busy; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_prs3_busy_0 = out_uop_prs3_busy; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_ppred_busy_0 = out_uop_ppred_busy; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_stale_pdst_0 = out_uop_stale_pdst; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_exception_0 = out_uop_exception; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_exc_cause_0 = out_uop_exc_cause; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_mem_cmd_0 = out_uop_mem_cmd; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_mem_size_0 = out_uop_mem_size; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_mem_signed_0 = out_uop_mem_signed; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_uses_ldq_0 = out_uop_uses_ldq; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_uses_stq_0 = out_uop_uses_stq; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_unique_0 = out_uop_is_unique; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_flush_on_commit_0 = out_uop_flush_on_commit; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_csr_cmd_0 = out_uop_csr_cmd; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_ldst_is_rs1_0 = out_uop_ldst_is_rs1; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_ldst_0 = out_uop_ldst; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_lrs1_0 = out_uop_lrs1; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_lrs2_0 = out_uop_lrs2; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_lrs3_0 = out_uop_lrs3; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_dst_rtype_0 = out_uop_dst_rtype; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_lrs1_rtype_0 = out_uop_lrs1_rtype; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_lrs2_rtype_0 = out_uop_lrs2_rtype; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_frs3_en_0 = out_uop_frs3_en; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fcn_dw_0 = out_uop_fcn_dw; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fcn_op_0 = out_uop_fcn_op; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_val_0 = out_uop_fp_val; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_rm_0 = out_uop_fp_rm; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_typ_0 = out_uop_fp_typ; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_xcpt_pf_if_0 = out_uop_xcpt_pf_if; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_xcpt_ae_if_0 = out_uop_xcpt_ae_if; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_xcpt_ma_if_0 = out_uop_xcpt_ma_if; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_bp_debug_if_0 = out_uop_bp_debug_if; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_bp_xcpt_if_0 = out_uop_bp_xcpt_if; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_debug_fsrc_0 = out_uop_debug_fsrc; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_debug_tsrc_0 = out_uop_debug_tsrc; // @[util.scala:458:7, :545:19]
assign io_deq_bits_addr_0 = out_addr; // @[util.scala:458:7, :545:19]
assign io_deq_bits_data_0 = out_data; // @[util.scala:458:7, :545:19]
assign io_deq_bits_is_hella_0 = out_is_hella; // @[util.scala:458:7, :545:19]
assign io_deq_bits_tag_match_0 = out_tag_match; // @[util.scala:458:7, :545:19]
assign io_deq_bits_old_meta_coh_state_0 = out_old_meta_coh_state; // @[util.scala:458:7, :545:19]
assign io_deq_bits_old_meta_tag_0 = out_old_meta_tag; // @[util.scala:458:7, :545:19]
assign io_deq_bits_way_en_0 = out_way_en; // @[util.scala:458:7, :545:19]
assign io_deq_bits_sdq_id_0 = out_sdq_id; // @[util.scala:458:7, :545:19]
wire [15:0][31:0] _GEN_3 = {{uops_0_inst}, {uops_14_inst}, {uops_13_inst}, {uops_12_inst}, {uops_11_inst}, {uops_10_inst}, {uops_9_inst}, {uops_8_inst}, {uops_7_inst}, {uops_6_inst}, {uops_5_inst}, {uops_4_inst}, {uops_3_inst}, {uops_2_inst}, {uops_1_inst}, {uops_0_inst}}; // @[util.scala:505:22, :547:21]
assign out_uop_inst = _GEN_3[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][31:0] _GEN_4 = {{uops_0_debug_inst}, {uops_14_debug_inst}, {uops_13_debug_inst}, {uops_12_debug_inst}, {uops_11_debug_inst}, {uops_10_debug_inst}, {uops_9_debug_inst}, {uops_8_debug_inst}, {uops_7_debug_inst}, {uops_6_debug_inst}, {uops_5_debug_inst}, {uops_4_debug_inst}, {uops_3_debug_inst}, {uops_2_debug_inst}, {uops_1_debug_inst}, {uops_0_debug_inst}}; // @[util.scala:505:22, :547:21]
assign out_uop_debug_inst = _GEN_4[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_5 = {{uops_0_is_rvc}, {uops_14_is_rvc}, {uops_13_is_rvc}, {uops_12_is_rvc}, {uops_11_is_rvc}, {uops_10_is_rvc}, {uops_9_is_rvc}, {uops_8_is_rvc}, {uops_7_is_rvc}, {uops_6_is_rvc}, {uops_5_is_rvc}, {uops_4_is_rvc}, {uops_3_is_rvc}, {uops_2_is_rvc}, {uops_1_is_rvc}, {uops_0_is_rvc}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_rvc = _GEN_5[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][39:0] _GEN_6 = {{uops_0_debug_pc}, {uops_14_debug_pc}, {uops_13_debug_pc}, {uops_12_debug_pc}, {uops_11_debug_pc}, {uops_10_debug_pc}, {uops_9_debug_pc}, {uops_8_debug_pc}, {uops_7_debug_pc}, {uops_6_debug_pc}, {uops_5_debug_pc}, {uops_4_debug_pc}, {uops_3_debug_pc}, {uops_2_debug_pc}, {uops_1_debug_pc}, {uops_0_debug_pc}}; // @[util.scala:505:22, :547:21]
assign out_uop_debug_pc = _GEN_6[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_7 = {{uops_0_iq_type_0}, {uops_14_iq_type_0}, {uops_13_iq_type_0}, {uops_12_iq_type_0}, {uops_11_iq_type_0}, {uops_10_iq_type_0}, {uops_9_iq_type_0}, {uops_8_iq_type_0}, {uops_7_iq_type_0}, {uops_6_iq_type_0}, {uops_5_iq_type_0}, {uops_4_iq_type_0}, {uops_3_iq_type_0}, {uops_2_iq_type_0}, {uops_1_iq_type_0}, {uops_0_iq_type_0}}; // @[util.scala:505:22, :547:21]
assign out_uop_iq_type_0 = _GEN_7[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_8 = {{uops_0_iq_type_1}, {uops_14_iq_type_1}, {uops_13_iq_type_1}, {uops_12_iq_type_1}, {uops_11_iq_type_1}, {uops_10_iq_type_1}, {uops_9_iq_type_1}, {uops_8_iq_type_1}, {uops_7_iq_type_1}, {uops_6_iq_type_1}, {uops_5_iq_type_1}, {uops_4_iq_type_1}, {uops_3_iq_type_1}, {uops_2_iq_type_1}, {uops_1_iq_type_1}, {uops_0_iq_type_1}}; // @[util.scala:505:22, :547:21]
assign out_uop_iq_type_1 = _GEN_8[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_9 = {{uops_0_iq_type_2}, {uops_14_iq_type_2}, {uops_13_iq_type_2}, {uops_12_iq_type_2}, {uops_11_iq_type_2}, {uops_10_iq_type_2}, {uops_9_iq_type_2}, {uops_8_iq_type_2}, {uops_7_iq_type_2}, {uops_6_iq_type_2}, {uops_5_iq_type_2}, {uops_4_iq_type_2}, {uops_3_iq_type_2}, {uops_2_iq_type_2}, {uops_1_iq_type_2}, {uops_0_iq_type_2}}; // @[util.scala:505:22, :547:21]
assign out_uop_iq_type_2 = _GEN_9[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_10 = {{uops_0_iq_type_3}, {uops_14_iq_type_3}, {uops_13_iq_type_3}, {uops_12_iq_type_3}, {uops_11_iq_type_3}, {uops_10_iq_type_3}, {uops_9_iq_type_3}, {uops_8_iq_type_3}, {uops_7_iq_type_3}, {uops_6_iq_type_3}, {uops_5_iq_type_3}, {uops_4_iq_type_3}, {uops_3_iq_type_3}, {uops_2_iq_type_3}, {uops_1_iq_type_3}, {uops_0_iq_type_3}}; // @[util.scala:505:22, :547:21]
assign out_uop_iq_type_3 = _GEN_10[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_11 = {{uops_0_fu_code_0}, {uops_14_fu_code_0}, {uops_13_fu_code_0}, {uops_12_fu_code_0}, {uops_11_fu_code_0}, {uops_10_fu_code_0}, {uops_9_fu_code_0}, {uops_8_fu_code_0}, {uops_7_fu_code_0}, {uops_6_fu_code_0}, {uops_5_fu_code_0}, {uops_4_fu_code_0}, {uops_3_fu_code_0}, {uops_2_fu_code_0}, {uops_1_fu_code_0}, {uops_0_fu_code_0}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_0 = _GEN_11[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_12 = {{uops_0_fu_code_1}, {uops_14_fu_code_1}, {uops_13_fu_code_1}, {uops_12_fu_code_1}, {uops_11_fu_code_1}, {uops_10_fu_code_1}, {uops_9_fu_code_1}, {uops_8_fu_code_1}, {uops_7_fu_code_1}, {uops_6_fu_code_1}, {uops_5_fu_code_1}, {uops_4_fu_code_1}, {uops_3_fu_code_1}, {uops_2_fu_code_1}, {uops_1_fu_code_1}, {uops_0_fu_code_1}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_1 = _GEN_12[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_13 = {{uops_0_fu_code_2}, {uops_14_fu_code_2}, {uops_13_fu_code_2}, {uops_12_fu_code_2}, {uops_11_fu_code_2}, {uops_10_fu_code_2}, {uops_9_fu_code_2}, {uops_8_fu_code_2}, {uops_7_fu_code_2}, {uops_6_fu_code_2}, {uops_5_fu_code_2}, {uops_4_fu_code_2}, {uops_3_fu_code_2}, {uops_2_fu_code_2}, {uops_1_fu_code_2}, {uops_0_fu_code_2}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_2 = _GEN_13[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_14 = {{uops_0_fu_code_3}, {uops_14_fu_code_3}, {uops_13_fu_code_3}, {uops_12_fu_code_3}, {uops_11_fu_code_3}, {uops_10_fu_code_3}, {uops_9_fu_code_3}, {uops_8_fu_code_3}, {uops_7_fu_code_3}, {uops_6_fu_code_3}, {uops_5_fu_code_3}, {uops_4_fu_code_3}, {uops_3_fu_code_3}, {uops_2_fu_code_3}, {uops_1_fu_code_3}, {uops_0_fu_code_3}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_3 = _GEN_14[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_15 = {{uops_0_fu_code_4}, {uops_14_fu_code_4}, {uops_13_fu_code_4}, {uops_12_fu_code_4}, {uops_11_fu_code_4}, {uops_10_fu_code_4}, {uops_9_fu_code_4}, {uops_8_fu_code_4}, {uops_7_fu_code_4}, {uops_6_fu_code_4}, {uops_5_fu_code_4}, {uops_4_fu_code_4}, {uops_3_fu_code_4}, {uops_2_fu_code_4}, {uops_1_fu_code_4}, {uops_0_fu_code_4}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_4 = _GEN_15[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_16 = {{uops_0_fu_code_5}, {uops_14_fu_code_5}, {uops_13_fu_code_5}, {uops_12_fu_code_5}, {uops_11_fu_code_5}, {uops_10_fu_code_5}, {uops_9_fu_code_5}, {uops_8_fu_code_5}, {uops_7_fu_code_5}, {uops_6_fu_code_5}, {uops_5_fu_code_5}, {uops_4_fu_code_5}, {uops_3_fu_code_5}, {uops_2_fu_code_5}, {uops_1_fu_code_5}, {uops_0_fu_code_5}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_5 = _GEN_16[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_17 = {{uops_0_fu_code_6}, {uops_14_fu_code_6}, {uops_13_fu_code_6}, {uops_12_fu_code_6}, {uops_11_fu_code_6}, {uops_10_fu_code_6}, {uops_9_fu_code_6}, {uops_8_fu_code_6}, {uops_7_fu_code_6}, {uops_6_fu_code_6}, {uops_5_fu_code_6}, {uops_4_fu_code_6}, {uops_3_fu_code_6}, {uops_2_fu_code_6}, {uops_1_fu_code_6}, {uops_0_fu_code_6}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_6 = _GEN_17[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_18 = {{uops_0_fu_code_7}, {uops_14_fu_code_7}, {uops_13_fu_code_7}, {uops_12_fu_code_7}, {uops_11_fu_code_7}, {uops_10_fu_code_7}, {uops_9_fu_code_7}, {uops_8_fu_code_7}, {uops_7_fu_code_7}, {uops_6_fu_code_7}, {uops_5_fu_code_7}, {uops_4_fu_code_7}, {uops_3_fu_code_7}, {uops_2_fu_code_7}, {uops_1_fu_code_7}, {uops_0_fu_code_7}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_7 = _GEN_18[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_19 = {{uops_0_fu_code_8}, {uops_14_fu_code_8}, {uops_13_fu_code_8}, {uops_12_fu_code_8}, {uops_11_fu_code_8}, {uops_10_fu_code_8}, {uops_9_fu_code_8}, {uops_8_fu_code_8}, {uops_7_fu_code_8}, {uops_6_fu_code_8}, {uops_5_fu_code_8}, {uops_4_fu_code_8}, {uops_3_fu_code_8}, {uops_2_fu_code_8}, {uops_1_fu_code_8}, {uops_0_fu_code_8}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_8 = _GEN_19[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_20 = {{uops_0_fu_code_9}, {uops_14_fu_code_9}, {uops_13_fu_code_9}, {uops_12_fu_code_9}, {uops_11_fu_code_9}, {uops_10_fu_code_9}, {uops_9_fu_code_9}, {uops_8_fu_code_9}, {uops_7_fu_code_9}, {uops_6_fu_code_9}, {uops_5_fu_code_9}, {uops_4_fu_code_9}, {uops_3_fu_code_9}, {uops_2_fu_code_9}, {uops_1_fu_code_9}, {uops_0_fu_code_9}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_9 = _GEN_20[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_21 = {{uops_0_iw_issued}, {uops_14_iw_issued}, {uops_13_iw_issued}, {uops_12_iw_issued}, {uops_11_iw_issued}, {uops_10_iw_issued}, {uops_9_iw_issued}, {uops_8_iw_issued}, {uops_7_iw_issued}, {uops_6_iw_issued}, {uops_5_iw_issued}, {uops_4_iw_issued}, {uops_3_iw_issued}, {uops_2_iw_issued}, {uops_1_iw_issued}, {uops_0_iw_issued}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_issued = _GEN_21[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_22 = {{uops_0_iw_issued_partial_agen}, {uops_14_iw_issued_partial_agen}, {uops_13_iw_issued_partial_agen}, {uops_12_iw_issued_partial_agen}, {uops_11_iw_issued_partial_agen}, {uops_10_iw_issued_partial_agen}, {uops_9_iw_issued_partial_agen}, {uops_8_iw_issued_partial_agen}, {uops_7_iw_issued_partial_agen}, {uops_6_iw_issued_partial_agen}, {uops_5_iw_issued_partial_agen}, {uops_4_iw_issued_partial_agen}, {uops_3_iw_issued_partial_agen}, {uops_2_iw_issued_partial_agen}, {uops_1_iw_issued_partial_agen}, {uops_0_iw_issued_partial_agen}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_issued_partial_agen = _GEN_22[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_23 = {{uops_0_iw_issued_partial_dgen}, {uops_14_iw_issued_partial_dgen}, {uops_13_iw_issued_partial_dgen}, {uops_12_iw_issued_partial_dgen}, {uops_11_iw_issued_partial_dgen}, {uops_10_iw_issued_partial_dgen}, {uops_9_iw_issued_partial_dgen}, {uops_8_iw_issued_partial_dgen}, {uops_7_iw_issued_partial_dgen}, {uops_6_iw_issued_partial_dgen}, {uops_5_iw_issued_partial_dgen}, {uops_4_iw_issued_partial_dgen}, {uops_3_iw_issued_partial_dgen}, {uops_2_iw_issued_partial_dgen}, {uops_1_iw_issued_partial_dgen}, {uops_0_iw_issued_partial_dgen}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_issued_partial_dgen = _GEN_23[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][2:0] _GEN_24 = {{uops_0_iw_p1_speculative_child}, {uops_14_iw_p1_speculative_child}, {uops_13_iw_p1_speculative_child}, {uops_12_iw_p1_speculative_child}, {uops_11_iw_p1_speculative_child}, {uops_10_iw_p1_speculative_child}, {uops_9_iw_p1_speculative_child}, {uops_8_iw_p1_speculative_child}, {uops_7_iw_p1_speculative_child}, {uops_6_iw_p1_speculative_child}, {uops_5_iw_p1_speculative_child}, {uops_4_iw_p1_speculative_child}, {uops_3_iw_p1_speculative_child}, {uops_2_iw_p1_speculative_child}, {uops_1_iw_p1_speculative_child}, {uops_0_iw_p1_speculative_child}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_p1_speculative_child = _GEN_24[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][2:0] _GEN_25 = {{uops_0_iw_p2_speculative_child}, {uops_14_iw_p2_speculative_child}, {uops_13_iw_p2_speculative_child}, {uops_12_iw_p2_speculative_child}, {uops_11_iw_p2_speculative_child}, {uops_10_iw_p2_speculative_child}, {uops_9_iw_p2_speculative_child}, {uops_8_iw_p2_speculative_child}, {uops_7_iw_p2_speculative_child}, {uops_6_iw_p2_speculative_child}, {uops_5_iw_p2_speculative_child}, {uops_4_iw_p2_speculative_child}, {uops_3_iw_p2_speculative_child}, {uops_2_iw_p2_speculative_child}, {uops_1_iw_p2_speculative_child}, {uops_0_iw_p2_speculative_child}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_p2_speculative_child = _GEN_25[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_26 = {{uops_0_iw_p1_bypass_hint}, {uops_14_iw_p1_bypass_hint}, {uops_13_iw_p1_bypass_hint}, {uops_12_iw_p1_bypass_hint}, {uops_11_iw_p1_bypass_hint}, {uops_10_iw_p1_bypass_hint}, {uops_9_iw_p1_bypass_hint}, {uops_8_iw_p1_bypass_hint}, {uops_7_iw_p1_bypass_hint}, {uops_6_iw_p1_bypass_hint}, {uops_5_iw_p1_bypass_hint}, {uops_4_iw_p1_bypass_hint}, {uops_3_iw_p1_bypass_hint}, {uops_2_iw_p1_bypass_hint}, {uops_1_iw_p1_bypass_hint}, {uops_0_iw_p1_bypass_hint}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_p1_bypass_hint = _GEN_26[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_27 = {{uops_0_iw_p2_bypass_hint}, {uops_14_iw_p2_bypass_hint}, {uops_13_iw_p2_bypass_hint}, {uops_12_iw_p2_bypass_hint}, {uops_11_iw_p2_bypass_hint}, {uops_10_iw_p2_bypass_hint}, {uops_9_iw_p2_bypass_hint}, {uops_8_iw_p2_bypass_hint}, {uops_7_iw_p2_bypass_hint}, {uops_6_iw_p2_bypass_hint}, {uops_5_iw_p2_bypass_hint}, {uops_4_iw_p2_bypass_hint}, {uops_3_iw_p2_bypass_hint}, {uops_2_iw_p2_bypass_hint}, {uops_1_iw_p2_bypass_hint}, {uops_0_iw_p2_bypass_hint}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_p2_bypass_hint = _GEN_27[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_28 = {{uops_0_iw_p3_bypass_hint}, {uops_14_iw_p3_bypass_hint}, {uops_13_iw_p3_bypass_hint}, {uops_12_iw_p3_bypass_hint}, {uops_11_iw_p3_bypass_hint}, {uops_10_iw_p3_bypass_hint}, {uops_9_iw_p3_bypass_hint}, {uops_8_iw_p3_bypass_hint}, {uops_7_iw_p3_bypass_hint}, {uops_6_iw_p3_bypass_hint}, {uops_5_iw_p3_bypass_hint}, {uops_4_iw_p3_bypass_hint}, {uops_3_iw_p3_bypass_hint}, {uops_2_iw_p3_bypass_hint}, {uops_1_iw_p3_bypass_hint}, {uops_0_iw_p3_bypass_hint}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_p3_bypass_hint = _GEN_28[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][2:0] _GEN_29 = {{uops_0_dis_col_sel}, {uops_14_dis_col_sel}, {uops_13_dis_col_sel}, {uops_12_dis_col_sel}, {uops_11_dis_col_sel}, {uops_10_dis_col_sel}, {uops_9_dis_col_sel}, {uops_8_dis_col_sel}, {uops_7_dis_col_sel}, {uops_6_dis_col_sel}, {uops_5_dis_col_sel}, {uops_4_dis_col_sel}, {uops_3_dis_col_sel}, {uops_2_dis_col_sel}, {uops_1_dis_col_sel}, {uops_0_dis_col_sel}}; // @[util.scala:505:22, :547:21]
assign out_uop_dis_col_sel = _GEN_29[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][15:0] _GEN_30 = {{uops_0_br_mask}, {uops_14_br_mask}, {uops_13_br_mask}, {uops_12_br_mask}, {uops_11_br_mask}, {uops_10_br_mask}, {uops_9_br_mask}, {uops_8_br_mask}, {uops_7_br_mask}, {uops_6_br_mask}, {uops_5_br_mask}, {uops_4_br_mask}, {uops_3_br_mask}, {uops_2_br_mask}, {uops_1_br_mask}, {uops_0_br_mask}}; // @[util.scala:505:22, :547:21]
assign out_uop_br_mask = _GEN_30[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][3:0] _GEN_31 = {{uops_0_br_tag}, {uops_14_br_tag}, {uops_13_br_tag}, {uops_12_br_tag}, {uops_11_br_tag}, {uops_10_br_tag}, {uops_9_br_tag}, {uops_8_br_tag}, {uops_7_br_tag}, {uops_6_br_tag}, {uops_5_br_tag}, {uops_4_br_tag}, {uops_3_br_tag}, {uops_2_br_tag}, {uops_1_br_tag}, {uops_0_br_tag}}; // @[util.scala:505:22, :547:21]
assign out_uop_br_tag = _GEN_31[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][3:0] _GEN_32 = {{uops_0_br_type}, {uops_14_br_type}, {uops_13_br_type}, {uops_12_br_type}, {uops_11_br_type}, {uops_10_br_type}, {uops_9_br_type}, {uops_8_br_type}, {uops_7_br_type}, {uops_6_br_type}, {uops_5_br_type}, {uops_4_br_type}, {uops_3_br_type}, {uops_2_br_type}, {uops_1_br_type}, {uops_0_br_type}}; // @[util.scala:505:22, :547:21]
assign out_uop_br_type = _GEN_32[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_33 = {{uops_0_is_sfb}, {uops_14_is_sfb}, {uops_13_is_sfb}, {uops_12_is_sfb}, {uops_11_is_sfb}, {uops_10_is_sfb}, {uops_9_is_sfb}, {uops_8_is_sfb}, {uops_7_is_sfb}, {uops_6_is_sfb}, {uops_5_is_sfb}, {uops_4_is_sfb}, {uops_3_is_sfb}, {uops_2_is_sfb}, {uops_1_is_sfb}, {uops_0_is_sfb}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_sfb = _GEN_33[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_34 = {{uops_0_is_fence}, {uops_14_is_fence}, {uops_13_is_fence}, {uops_12_is_fence}, {uops_11_is_fence}, {uops_10_is_fence}, {uops_9_is_fence}, {uops_8_is_fence}, {uops_7_is_fence}, {uops_6_is_fence}, {uops_5_is_fence}, {uops_4_is_fence}, {uops_3_is_fence}, {uops_2_is_fence}, {uops_1_is_fence}, {uops_0_is_fence}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_fence = _GEN_34[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_35 = {{uops_0_is_fencei}, {uops_14_is_fencei}, {uops_13_is_fencei}, {uops_12_is_fencei}, {uops_11_is_fencei}, {uops_10_is_fencei}, {uops_9_is_fencei}, {uops_8_is_fencei}, {uops_7_is_fencei}, {uops_6_is_fencei}, {uops_5_is_fencei}, {uops_4_is_fencei}, {uops_3_is_fencei}, {uops_2_is_fencei}, {uops_1_is_fencei}, {uops_0_is_fencei}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_fencei = _GEN_35[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_36 = {{uops_0_is_sfence}, {uops_14_is_sfence}, {uops_13_is_sfence}, {uops_12_is_sfence}, {uops_11_is_sfence}, {uops_10_is_sfence}, {uops_9_is_sfence}, {uops_8_is_sfence}, {uops_7_is_sfence}, {uops_6_is_sfence}, {uops_5_is_sfence}, {uops_4_is_sfence}, {uops_3_is_sfence}, {uops_2_is_sfence}, {uops_1_is_sfence}, {uops_0_is_sfence}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_sfence = _GEN_36[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_37 = {{uops_0_is_amo}, {uops_14_is_amo}, {uops_13_is_amo}, {uops_12_is_amo}, {uops_11_is_amo}, {uops_10_is_amo}, {uops_9_is_amo}, {uops_8_is_amo}, {uops_7_is_amo}, {uops_6_is_amo}, {uops_5_is_amo}, {uops_4_is_amo}, {uops_3_is_amo}, {uops_2_is_amo}, {uops_1_is_amo}, {uops_0_is_amo}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_amo = _GEN_37[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_38 = {{uops_0_is_eret}, {uops_14_is_eret}, {uops_13_is_eret}, {uops_12_is_eret}, {uops_11_is_eret}, {uops_10_is_eret}, {uops_9_is_eret}, {uops_8_is_eret}, {uops_7_is_eret}, {uops_6_is_eret}, {uops_5_is_eret}, {uops_4_is_eret}, {uops_3_is_eret}, {uops_2_is_eret}, {uops_1_is_eret}, {uops_0_is_eret}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_eret = _GEN_38[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_39 = {{uops_0_is_sys_pc2epc}, {uops_14_is_sys_pc2epc}, {uops_13_is_sys_pc2epc}, {uops_12_is_sys_pc2epc}, {uops_11_is_sys_pc2epc}, {uops_10_is_sys_pc2epc}, {uops_9_is_sys_pc2epc}, {uops_8_is_sys_pc2epc}, {uops_7_is_sys_pc2epc}, {uops_6_is_sys_pc2epc}, {uops_5_is_sys_pc2epc}, {uops_4_is_sys_pc2epc}, {uops_3_is_sys_pc2epc}, {uops_2_is_sys_pc2epc}, {uops_1_is_sys_pc2epc}, {uops_0_is_sys_pc2epc}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_sys_pc2epc = _GEN_39[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_40 = {{uops_0_is_rocc}, {uops_14_is_rocc}, {uops_13_is_rocc}, {uops_12_is_rocc}, {uops_11_is_rocc}, {uops_10_is_rocc}, {uops_9_is_rocc}, {uops_8_is_rocc}, {uops_7_is_rocc}, {uops_6_is_rocc}, {uops_5_is_rocc}, {uops_4_is_rocc}, {uops_3_is_rocc}, {uops_2_is_rocc}, {uops_1_is_rocc}, {uops_0_is_rocc}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_rocc = _GEN_40[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_41 = {{uops_0_is_mov}, {uops_14_is_mov}, {uops_13_is_mov}, {uops_12_is_mov}, {uops_11_is_mov}, {uops_10_is_mov}, {uops_9_is_mov}, {uops_8_is_mov}, {uops_7_is_mov}, {uops_6_is_mov}, {uops_5_is_mov}, {uops_4_is_mov}, {uops_3_is_mov}, {uops_2_is_mov}, {uops_1_is_mov}, {uops_0_is_mov}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_mov = _GEN_41[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][4:0] _GEN_42 = {{uops_0_ftq_idx}, {uops_14_ftq_idx}, {uops_13_ftq_idx}, {uops_12_ftq_idx}, {uops_11_ftq_idx}, {uops_10_ftq_idx}, {uops_9_ftq_idx}, {uops_8_ftq_idx}, {uops_7_ftq_idx}, {uops_6_ftq_idx}, {uops_5_ftq_idx}, {uops_4_ftq_idx}, {uops_3_ftq_idx}, {uops_2_ftq_idx}, {uops_1_ftq_idx}, {uops_0_ftq_idx}}; // @[util.scala:505:22, :547:21]
assign out_uop_ftq_idx = _GEN_42[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_43 = {{uops_0_edge_inst}, {uops_14_edge_inst}, {uops_13_edge_inst}, {uops_12_edge_inst}, {uops_11_edge_inst}, {uops_10_edge_inst}, {uops_9_edge_inst}, {uops_8_edge_inst}, {uops_7_edge_inst}, {uops_6_edge_inst}, {uops_5_edge_inst}, {uops_4_edge_inst}, {uops_3_edge_inst}, {uops_2_edge_inst}, {uops_1_edge_inst}, {uops_0_edge_inst}}; // @[util.scala:505:22, :547:21]
assign out_uop_edge_inst = _GEN_43[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][5:0] _GEN_44 = {{uops_0_pc_lob}, {uops_14_pc_lob}, {uops_13_pc_lob}, {uops_12_pc_lob}, {uops_11_pc_lob}, {uops_10_pc_lob}, {uops_9_pc_lob}, {uops_8_pc_lob}, {uops_7_pc_lob}, {uops_6_pc_lob}, {uops_5_pc_lob}, {uops_4_pc_lob}, {uops_3_pc_lob}, {uops_2_pc_lob}, {uops_1_pc_lob}, {uops_0_pc_lob}}; // @[util.scala:505:22, :547:21]
assign out_uop_pc_lob = _GEN_44[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_45 = {{uops_0_taken}, {uops_14_taken}, {uops_13_taken}, {uops_12_taken}, {uops_11_taken}, {uops_10_taken}, {uops_9_taken}, {uops_8_taken}, {uops_7_taken}, {uops_6_taken}, {uops_5_taken}, {uops_4_taken}, {uops_3_taken}, {uops_2_taken}, {uops_1_taken}, {uops_0_taken}}; // @[util.scala:505:22, :547:21]
assign out_uop_taken = _GEN_45[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_46 = {{uops_0_imm_rename}, {uops_14_imm_rename}, {uops_13_imm_rename}, {uops_12_imm_rename}, {uops_11_imm_rename}, {uops_10_imm_rename}, {uops_9_imm_rename}, {uops_8_imm_rename}, {uops_7_imm_rename}, {uops_6_imm_rename}, {uops_5_imm_rename}, {uops_4_imm_rename}, {uops_3_imm_rename}, {uops_2_imm_rename}, {uops_1_imm_rename}, {uops_0_imm_rename}}; // @[util.scala:505:22, :547:21]
assign out_uop_imm_rename = _GEN_46[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][2:0] _GEN_47 = {{uops_0_imm_sel}, {uops_14_imm_sel}, {uops_13_imm_sel}, {uops_12_imm_sel}, {uops_11_imm_sel}, {uops_10_imm_sel}, {uops_9_imm_sel}, {uops_8_imm_sel}, {uops_7_imm_sel}, {uops_6_imm_sel}, {uops_5_imm_sel}, {uops_4_imm_sel}, {uops_3_imm_sel}, {uops_2_imm_sel}, {uops_1_imm_sel}, {uops_0_imm_sel}}; // @[util.scala:505:22, :547:21]
assign out_uop_imm_sel = _GEN_47[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][4:0] _GEN_48 = {{uops_0_pimm}, {uops_14_pimm}, {uops_13_pimm}, {uops_12_pimm}, {uops_11_pimm}, {uops_10_pimm}, {uops_9_pimm}, {uops_8_pimm}, {uops_7_pimm}, {uops_6_pimm}, {uops_5_pimm}, {uops_4_pimm}, {uops_3_pimm}, {uops_2_pimm}, {uops_1_pimm}, {uops_0_pimm}}; // @[util.scala:505:22, :547:21]
assign out_uop_pimm = _GEN_48[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][19:0] _GEN_49 = {{uops_0_imm_packed}, {uops_14_imm_packed}, {uops_13_imm_packed}, {uops_12_imm_packed}, {uops_11_imm_packed}, {uops_10_imm_packed}, {uops_9_imm_packed}, {uops_8_imm_packed}, {uops_7_imm_packed}, {uops_6_imm_packed}, {uops_5_imm_packed}, {uops_4_imm_packed}, {uops_3_imm_packed}, {uops_2_imm_packed}, {uops_1_imm_packed}, {uops_0_imm_packed}}; // @[util.scala:505:22, :547:21]
assign out_uop_imm_packed = _GEN_49[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_50 = {{uops_0_op1_sel}, {uops_14_op1_sel}, {uops_13_op1_sel}, {uops_12_op1_sel}, {uops_11_op1_sel}, {uops_10_op1_sel}, {uops_9_op1_sel}, {uops_8_op1_sel}, {uops_7_op1_sel}, {uops_6_op1_sel}, {uops_5_op1_sel}, {uops_4_op1_sel}, {uops_3_op1_sel}, {uops_2_op1_sel}, {uops_1_op1_sel}, {uops_0_op1_sel}}; // @[util.scala:505:22, :547:21]
assign out_uop_op1_sel = _GEN_50[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][2:0] _GEN_51 = {{uops_0_op2_sel}, {uops_14_op2_sel}, {uops_13_op2_sel}, {uops_12_op2_sel}, {uops_11_op2_sel}, {uops_10_op2_sel}, {uops_9_op2_sel}, {uops_8_op2_sel}, {uops_7_op2_sel}, {uops_6_op2_sel}, {uops_5_op2_sel}, {uops_4_op2_sel}, {uops_3_op2_sel}, {uops_2_op2_sel}, {uops_1_op2_sel}, {uops_0_op2_sel}}; // @[util.scala:505:22, :547:21]
assign out_uop_op2_sel = _GEN_51[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_52 = {{uops_0_fp_ctrl_ldst}, {uops_14_fp_ctrl_ldst}, {uops_13_fp_ctrl_ldst}, {uops_12_fp_ctrl_ldst}, {uops_11_fp_ctrl_ldst}, {uops_10_fp_ctrl_ldst}, {uops_9_fp_ctrl_ldst}, {uops_8_fp_ctrl_ldst}, {uops_7_fp_ctrl_ldst}, {uops_6_fp_ctrl_ldst}, {uops_5_fp_ctrl_ldst}, {uops_4_fp_ctrl_ldst}, {uops_3_fp_ctrl_ldst}, {uops_2_fp_ctrl_ldst}, {uops_1_fp_ctrl_ldst}, {uops_0_fp_ctrl_ldst}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_ldst = _GEN_52[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_53 = {{uops_0_fp_ctrl_wen}, {uops_14_fp_ctrl_wen}, {uops_13_fp_ctrl_wen}, {uops_12_fp_ctrl_wen}, {uops_11_fp_ctrl_wen}, {uops_10_fp_ctrl_wen}, {uops_9_fp_ctrl_wen}, {uops_8_fp_ctrl_wen}, {uops_7_fp_ctrl_wen}, {uops_6_fp_ctrl_wen}, {uops_5_fp_ctrl_wen}, {uops_4_fp_ctrl_wen}, {uops_3_fp_ctrl_wen}, {uops_2_fp_ctrl_wen}, {uops_1_fp_ctrl_wen}, {uops_0_fp_ctrl_wen}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_wen = _GEN_53[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_54 = {{uops_0_fp_ctrl_ren1}, {uops_14_fp_ctrl_ren1}, {uops_13_fp_ctrl_ren1}, {uops_12_fp_ctrl_ren1}, {uops_11_fp_ctrl_ren1}, {uops_10_fp_ctrl_ren1}, {uops_9_fp_ctrl_ren1}, {uops_8_fp_ctrl_ren1}, {uops_7_fp_ctrl_ren1}, {uops_6_fp_ctrl_ren1}, {uops_5_fp_ctrl_ren1}, {uops_4_fp_ctrl_ren1}, {uops_3_fp_ctrl_ren1}, {uops_2_fp_ctrl_ren1}, {uops_1_fp_ctrl_ren1}, {uops_0_fp_ctrl_ren1}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_ren1 = _GEN_54[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_55 = {{uops_0_fp_ctrl_ren2}, {uops_14_fp_ctrl_ren2}, {uops_13_fp_ctrl_ren2}, {uops_12_fp_ctrl_ren2}, {uops_11_fp_ctrl_ren2}, {uops_10_fp_ctrl_ren2}, {uops_9_fp_ctrl_ren2}, {uops_8_fp_ctrl_ren2}, {uops_7_fp_ctrl_ren2}, {uops_6_fp_ctrl_ren2}, {uops_5_fp_ctrl_ren2}, {uops_4_fp_ctrl_ren2}, {uops_3_fp_ctrl_ren2}, {uops_2_fp_ctrl_ren2}, {uops_1_fp_ctrl_ren2}, {uops_0_fp_ctrl_ren2}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_ren2 = _GEN_55[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_56 = {{uops_0_fp_ctrl_ren3}, {uops_14_fp_ctrl_ren3}, {uops_13_fp_ctrl_ren3}, {uops_12_fp_ctrl_ren3}, {uops_11_fp_ctrl_ren3}, {uops_10_fp_ctrl_ren3}, {uops_9_fp_ctrl_ren3}, {uops_8_fp_ctrl_ren3}, {uops_7_fp_ctrl_ren3}, {uops_6_fp_ctrl_ren3}, {uops_5_fp_ctrl_ren3}, {uops_4_fp_ctrl_ren3}, {uops_3_fp_ctrl_ren3}, {uops_2_fp_ctrl_ren3}, {uops_1_fp_ctrl_ren3}, {uops_0_fp_ctrl_ren3}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_ren3 = _GEN_56[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_57 = {{uops_0_fp_ctrl_swap12}, {uops_14_fp_ctrl_swap12}, {uops_13_fp_ctrl_swap12}, {uops_12_fp_ctrl_swap12}, {uops_11_fp_ctrl_swap12}, {uops_10_fp_ctrl_swap12}, {uops_9_fp_ctrl_swap12}, {uops_8_fp_ctrl_swap12}, {uops_7_fp_ctrl_swap12}, {uops_6_fp_ctrl_swap12}, {uops_5_fp_ctrl_swap12}, {uops_4_fp_ctrl_swap12}, {uops_3_fp_ctrl_swap12}, {uops_2_fp_ctrl_swap12}, {uops_1_fp_ctrl_swap12}, {uops_0_fp_ctrl_swap12}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_swap12 = _GEN_57[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_58 = {{uops_0_fp_ctrl_swap23}, {uops_14_fp_ctrl_swap23}, {uops_13_fp_ctrl_swap23}, {uops_12_fp_ctrl_swap23}, {uops_11_fp_ctrl_swap23}, {uops_10_fp_ctrl_swap23}, {uops_9_fp_ctrl_swap23}, {uops_8_fp_ctrl_swap23}, {uops_7_fp_ctrl_swap23}, {uops_6_fp_ctrl_swap23}, {uops_5_fp_ctrl_swap23}, {uops_4_fp_ctrl_swap23}, {uops_3_fp_ctrl_swap23}, {uops_2_fp_ctrl_swap23}, {uops_1_fp_ctrl_swap23}, {uops_0_fp_ctrl_swap23}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_swap23 = _GEN_58[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_59 = {{uops_0_fp_ctrl_typeTagIn}, {uops_14_fp_ctrl_typeTagIn}, {uops_13_fp_ctrl_typeTagIn}, {uops_12_fp_ctrl_typeTagIn}, {uops_11_fp_ctrl_typeTagIn}, {uops_10_fp_ctrl_typeTagIn}, {uops_9_fp_ctrl_typeTagIn}, {uops_8_fp_ctrl_typeTagIn}, {uops_7_fp_ctrl_typeTagIn}, {uops_6_fp_ctrl_typeTagIn}, {uops_5_fp_ctrl_typeTagIn}, {uops_4_fp_ctrl_typeTagIn}, {uops_3_fp_ctrl_typeTagIn}, {uops_2_fp_ctrl_typeTagIn}, {uops_1_fp_ctrl_typeTagIn}, {uops_0_fp_ctrl_typeTagIn}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_typeTagIn = _GEN_59[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_60 = {{uops_0_fp_ctrl_typeTagOut}, {uops_14_fp_ctrl_typeTagOut}, {uops_13_fp_ctrl_typeTagOut}, {uops_12_fp_ctrl_typeTagOut}, {uops_11_fp_ctrl_typeTagOut}, {uops_10_fp_ctrl_typeTagOut}, {uops_9_fp_ctrl_typeTagOut}, {uops_8_fp_ctrl_typeTagOut}, {uops_7_fp_ctrl_typeTagOut}, {uops_6_fp_ctrl_typeTagOut}, {uops_5_fp_ctrl_typeTagOut}, {uops_4_fp_ctrl_typeTagOut}, {uops_3_fp_ctrl_typeTagOut}, {uops_2_fp_ctrl_typeTagOut}, {uops_1_fp_ctrl_typeTagOut}, {uops_0_fp_ctrl_typeTagOut}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_typeTagOut = _GEN_60[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_61 = {{uops_0_fp_ctrl_fromint}, {uops_14_fp_ctrl_fromint}, {uops_13_fp_ctrl_fromint}, {uops_12_fp_ctrl_fromint}, {uops_11_fp_ctrl_fromint}, {uops_10_fp_ctrl_fromint}, {uops_9_fp_ctrl_fromint}, {uops_8_fp_ctrl_fromint}, {uops_7_fp_ctrl_fromint}, {uops_6_fp_ctrl_fromint}, {uops_5_fp_ctrl_fromint}, {uops_4_fp_ctrl_fromint}, {uops_3_fp_ctrl_fromint}, {uops_2_fp_ctrl_fromint}, {uops_1_fp_ctrl_fromint}, {uops_0_fp_ctrl_fromint}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_fromint = _GEN_61[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_62 = {{uops_0_fp_ctrl_toint}, {uops_14_fp_ctrl_toint}, {uops_13_fp_ctrl_toint}, {uops_12_fp_ctrl_toint}, {uops_11_fp_ctrl_toint}, {uops_10_fp_ctrl_toint}, {uops_9_fp_ctrl_toint}, {uops_8_fp_ctrl_toint}, {uops_7_fp_ctrl_toint}, {uops_6_fp_ctrl_toint}, {uops_5_fp_ctrl_toint}, {uops_4_fp_ctrl_toint}, {uops_3_fp_ctrl_toint}, {uops_2_fp_ctrl_toint}, {uops_1_fp_ctrl_toint}, {uops_0_fp_ctrl_toint}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_toint = _GEN_62[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_63 = {{uops_0_fp_ctrl_fastpipe}, {uops_14_fp_ctrl_fastpipe}, {uops_13_fp_ctrl_fastpipe}, {uops_12_fp_ctrl_fastpipe}, {uops_11_fp_ctrl_fastpipe}, {uops_10_fp_ctrl_fastpipe}, {uops_9_fp_ctrl_fastpipe}, {uops_8_fp_ctrl_fastpipe}, {uops_7_fp_ctrl_fastpipe}, {uops_6_fp_ctrl_fastpipe}, {uops_5_fp_ctrl_fastpipe}, {uops_4_fp_ctrl_fastpipe}, {uops_3_fp_ctrl_fastpipe}, {uops_2_fp_ctrl_fastpipe}, {uops_1_fp_ctrl_fastpipe}, {uops_0_fp_ctrl_fastpipe}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_fastpipe = _GEN_63[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_64 = {{uops_0_fp_ctrl_fma}, {uops_14_fp_ctrl_fma}, {uops_13_fp_ctrl_fma}, {uops_12_fp_ctrl_fma}, {uops_11_fp_ctrl_fma}, {uops_10_fp_ctrl_fma}, {uops_9_fp_ctrl_fma}, {uops_8_fp_ctrl_fma}, {uops_7_fp_ctrl_fma}, {uops_6_fp_ctrl_fma}, {uops_5_fp_ctrl_fma}, {uops_4_fp_ctrl_fma}, {uops_3_fp_ctrl_fma}, {uops_2_fp_ctrl_fma}, {uops_1_fp_ctrl_fma}, {uops_0_fp_ctrl_fma}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_fma = _GEN_64[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_65 = {{uops_0_fp_ctrl_div}, {uops_14_fp_ctrl_div}, {uops_13_fp_ctrl_div}, {uops_12_fp_ctrl_div}, {uops_11_fp_ctrl_div}, {uops_10_fp_ctrl_div}, {uops_9_fp_ctrl_div}, {uops_8_fp_ctrl_div}, {uops_7_fp_ctrl_div}, {uops_6_fp_ctrl_div}, {uops_5_fp_ctrl_div}, {uops_4_fp_ctrl_div}, {uops_3_fp_ctrl_div}, {uops_2_fp_ctrl_div}, {uops_1_fp_ctrl_div}, {uops_0_fp_ctrl_div}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_div = _GEN_65[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_66 = {{uops_0_fp_ctrl_sqrt}, {uops_14_fp_ctrl_sqrt}, {uops_13_fp_ctrl_sqrt}, {uops_12_fp_ctrl_sqrt}, {uops_11_fp_ctrl_sqrt}, {uops_10_fp_ctrl_sqrt}, {uops_9_fp_ctrl_sqrt}, {uops_8_fp_ctrl_sqrt}, {uops_7_fp_ctrl_sqrt}, {uops_6_fp_ctrl_sqrt}, {uops_5_fp_ctrl_sqrt}, {uops_4_fp_ctrl_sqrt}, {uops_3_fp_ctrl_sqrt}, {uops_2_fp_ctrl_sqrt}, {uops_1_fp_ctrl_sqrt}, {uops_0_fp_ctrl_sqrt}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_sqrt = _GEN_66[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_67 = {{uops_0_fp_ctrl_wflags}, {uops_14_fp_ctrl_wflags}, {uops_13_fp_ctrl_wflags}, {uops_12_fp_ctrl_wflags}, {uops_11_fp_ctrl_wflags}, {uops_10_fp_ctrl_wflags}, {uops_9_fp_ctrl_wflags}, {uops_8_fp_ctrl_wflags}, {uops_7_fp_ctrl_wflags}, {uops_6_fp_ctrl_wflags}, {uops_5_fp_ctrl_wflags}, {uops_4_fp_ctrl_wflags}, {uops_3_fp_ctrl_wflags}, {uops_2_fp_ctrl_wflags}, {uops_1_fp_ctrl_wflags}, {uops_0_fp_ctrl_wflags}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_wflags = _GEN_67[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_68 = {{uops_0_fp_ctrl_vec}, {uops_14_fp_ctrl_vec}, {uops_13_fp_ctrl_vec}, {uops_12_fp_ctrl_vec}, {uops_11_fp_ctrl_vec}, {uops_10_fp_ctrl_vec}, {uops_9_fp_ctrl_vec}, {uops_8_fp_ctrl_vec}, {uops_7_fp_ctrl_vec}, {uops_6_fp_ctrl_vec}, {uops_5_fp_ctrl_vec}, {uops_4_fp_ctrl_vec}, {uops_3_fp_ctrl_vec}, {uops_2_fp_ctrl_vec}, {uops_1_fp_ctrl_vec}, {uops_0_fp_ctrl_vec}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_vec = _GEN_68[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][6:0] _GEN_69 = {{uops_0_rob_idx}, {uops_14_rob_idx}, {uops_13_rob_idx}, {uops_12_rob_idx}, {uops_11_rob_idx}, {uops_10_rob_idx}, {uops_9_rob_idx}, {uops_8_rob_idx}, {uops_7_rob_idx}, {uops_6_rob_idx}, {uops_5_rob_idx}, {uops_4_rob_idx}, {uops_3_rob_idx}, {uops_2_rob_idx}, {uops_1_rob_idx}, {uops_0_rob_idx}}; // @[util.scala:505:22, :547:21]
assign out_uop_rob_idx = _GEN_69[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][4:0] _GEN_70 = {{uops_0_ldq_idx}, {uops_14_ldq_idx}, {uops_13_ldq_idx}, {uops_12_ldq_idx}, {uops_11_ldq_idx}, {uops_10_ldq_idx}, {uops_9_ldq_idx}, {uops_8_ldq_idx}, {uops_7_ldq_idx}, {uops_6_ldq_idx}, {uops_5_ldq_idx}, {uops_4_ldq_idx}, {uops_3_ldq_idx}, {uops_2_ldq_idx}, {uops_1_ldq_idx}, {uops_0_ldq_idx}}; // @[util.scala:505:22, :547:21]
assign out_uop_ldq_idx = _GEN_70[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][4:0] _GEN_71 = {{uops_0_stq_idx}, {uops_14_stq_idx}, {uops_13_stq_idx}, {uops_12_stq_idx}, {uops_11_stq_idx}, {uops_10_stq_idx}, {uops_9_stq_idx}, {uops_8_stq_idx}, {uops_7_stq_idx}, {uops_6_stq_idx}, {uops_5_stq_idx}, {uops_4_stq_idx}, {uops_3_stq_idx}, {uops_2_stq_idx}, {uops_1_stq_idx}, {uops_0_stq_idx}}; // @[util.scala:505:22, :547:21]
assign out_uop_stq_idx = _GEN_71[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_72 = {{uops_0_rxq_idx}, {uops_14_rxq_idx}, {uops_13_rxq_idx}, {uops_12_rxq_idx}, {uops_11_rxq_idx}, {uops_10_rxq_idx}, {uops_9_rxq_idx}, {uops_8_rxq_idx}, {uops_7_rxq_idx}, {uops_6_rxq_idx}, {uops_5_rxq_idx}, {uops_4_rxq_idx}, {uops_3_rxq_idx}, {uops_2_rxq_idx}, {uops_1_rxq_idx}, {uops_0_rxq_idx}}; // @[util.scala:505:22, :547:21]
assign out_uop_rxq_idx = _GEN_72[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][6:0] _GEN_73 = {{uops_0_pdst}, {uops_14_pdst}, {uops_13_pdst}, {uops_12_pdst}, {uops_11_pdst}, {uops_10_pdst}, {uops_9_pdst}, {uops_8_pdst}, {uops_7_pdst}, {uops_6_pdst}, {uops_5_pdst}, {uops_4_pdst}, {uops_3_pdst}, {uops_2_pdst}, {uops_1_pdst}, {uops_0_pdst}}; // @[util.scala:505:22, :547:21]
assign out_uop_pdst = _GEN_73[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][6:0] _GEN_74 = {{uops_0_prs1}, {uops_14_prs1}, {uops_13_prs1}, {uops_12_prs1}, {uops_11_prs1}, {uops_10_prs1}, {uops_9_prs1}, {uops_8_prs1}, {uops_7_prs1}, {uops_6_prs1}, {uops_5_prs1}, {uops_4_prs1}, {uops_3_prs1}, {uops_2_prs1}, {uops_1_prs1}, {uops_0_prs1}}; // @[util.scala:505:22, :547:21]
assign out_uop_prs1 = _GEN_74[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][6:0] _GEN_75 = {{uops_0_prs2}, {uops_14_prs2}, {uops_13_prs2}, {uops_12_prs2}, {uops_11_prs2}, {uops_10_prs2}, {uops_9_prs2}, {uops_8_prs2}, {uops_7_prs2}, {uops_6_prs2}, {uops_5_prs2}, {uops_4_prs2}, {uops_3_prs2}, {uops_2_prs2}, {uops_1_prs2}, {uops_0_prs2}}; // @[util.scala:505:22, :547:21]
assign out_uop_prs2 = _GEN_75[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][6:0] _GEN_76 = {{uops_0_prs3}, {uops_14_prs3}, {uops_13_prs3}, {uops_12_prs3}, {uops_11_prs3}, {uops_10_prs3}, {uops_9_prs3}, {uops_8_prs3}, {uops_7_prs3}, {uops_6_prs3}, {uops_5_prs3}, {uops_4_prs3}, {uops_3_prs3}, {uops_2_prs3}, {uops_1_prs3}, {uops_0_prs3}}; // @[util.scala:505:22, :547:21]
assign out_uop_prs3 = _GEN_76[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][4:0] _GEN_77 = {{uops_0_ppred}, {uops_14_ppred}, {uops_13_ppred}, {uops_12_ppred}, {uops_11_ppred}, {uops_10_ppred}, {uops_9_ppred}, {uops_8_ppred}, {uops_7_ppred}, {uops_6_ppred}, {uops_5_ppred}, {uops_4_ppred}, {uops_3_ppred}, {uops_2_ppred}, {uops_1_ppred}, {uops_0_ppred}}; // @[util.scala:505:22, :547:21]
assign out_uop_ppred = _GEN_77[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_78 = {{uops_0_prs1_busy}, {uops_14_prs1_busy}, {uops_13_prs1_busy}, {uops_12_prs1_busy}, {uops_11_prs1_busy}, {uops_10_prs1_busy}, {uops_9_prs1_busy}, {uops_8_prs1_busy}, {uops_7_prs1_busy}, {uops_6_prs1_busy}, {uops_5_prs1_busy}, {uops_4_prs1_busy}, {uops_3_prs1_busy}, {uops_2_prs1_busy}, {uops_1_prs1_busy}, {uops_0_prs1_busy}}; // @[util.scala:505:22, :547:21]
assign out_uop_prs1_busy = _GEN_78[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_79 = {{uops_0_prs2_busy}, {uops_14_prs2_busy}, {uops_13_prs2_busy}, {uops_12_prs2_busy}, {uops_11_prs2_busy}, {uops_10_prs2_busy}, {uops_9_prs2_busy}, {uops_8_prs2_busy}, {uops_7_prs2_busy}, {uops_6_prs2_busy}, {uops_5_prs2_busy}, {uops_4_prs2_busy}, {uops_3_prs2_busy}, {uops_2_prs2_busy}, {uops_1_prs2_busy}, {uops_0_prs2_busy}}; // @[util.scala:505:22, :547:21]
assign out_uop_prs2_busy = _GEN_79[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_80 = {{uops_0_prs3_busy}, {uops_14_prs3_busy}, {uops_13_prs3_busy}, {uops_12_prs3_busy}, {uops_11_prs3_busy}, {uops_10_prs3_busy}, {uops_9_prs3_busy}, {uops_8_prs3_busy}, {uops_7_prs3_busy}, {uops_6_prs3_busy}, {uops_5_prs3_busy}, {uops_4_prs3_busy}, {uops_3_prs3_busy}, {uops_2_prs3_busy}, {uops_1_prs3_busy}, {uops_0_prs3_busy}}; // @[util.scala:505:22, :547:21]
assign out_uop_prs3_busy = _GEN_80[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_81 = {{uops_0_ppred_busy}, {uops_14_ppred_busy}, {uops_13_ppred_busy}, {uops_12_ppred_busy}, {uops_11_ppred_busy}, {uops_10_ppred_busy}, {uops_9_ppred_busy}, {uops_8_ppred_busy}, {uops_7_ppred_busy}, {uops_6_ppred_busy}, {uops_5_ppred_busy}, {uops_4_ppred_busy}, {uops_3_ppred_busy}, {uops_2_ppred_busy}, {uops_1_ppred_busy}, {uops_0_ppred_busy}}; // @[util.scala:505:22, :547:21]
assign out_uop_ppred_busy = _GEN_81[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][6:0] _GEN_82 = {{uops_0_stale_pdst}, {uops_14_stale_pdst}, {uops_13_stale_pdst}, {uops_12_stale_pdst}, {uops_11_stale_pdst}, {uops_10_stale_pdst}, {uops_9_stale_pdst}, {uops_8_stale_pdst}, {uops_7_stale_pdst}, {uops_6_stale_pdst}, {uops_5_stale_pdst}, {uops_4_stale_pdst}, {uops_3_stale_pdst}, {uops_2_stale_pdst}, {uops_1_stale_pdst}, {uops_0_stale_pdst}}; // @[util.scala:505:22, :547:21]
assign out_uop_stale_pdst = _GEN_82[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_83 = {{uops_0_exception}, {uops_14_exception}, {uops_13_exception}, {uops_12_exception}, {uops_11_exception}, {uops_10_exception}, {uops_9_exception}, {uops_8_exception}, {uops_7_exception}, {uops_6_exception}, {uops_5_exception}, {uops_4_exception}, {uops_3_exception}, {uops_2_exception}, {uops_1_exception}, {uops_0_exception}}; // @[util.scala:505:22, :547:21]
assign out_uop_exception = _GEN_83[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][63:0] _GEN_84 = {{uops_0_exc_cause}, {uops_14_exc_cause}, {uops_13_exc_cause}, {uops_12_exc_cause}, {uops_11_exc_cause}, {uops_10_exc_cause}, {uops_9_exc_cause}, {uops_8_exc_cause}, {uops_7_exc_cause}, {uops_6_exc_cause}, {uops_5_exc_cause}, {uops_4_exc_cause}, {uops_3_exc_cause}, {uops_2_exc_cause}, {uops_1_exc_cause}, {uops_0_exc_cause}}; // @[util.scala:505:22, :547:21]
assign out_uop_exc_cause = _GEN_84[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][4:0] _GEN_85 = {{uops_0_mem_cmd}, {uops_14_mem_cmd}, {uops_13_mem_cmd}, {uops_12_mem_cmd}, {uops_11_mem_cmd}, {uops_10_mem_cmd}, {uops_9_mem_cmd}, {uops_8_mem_cmd}, {uops_7_mem_cmd}, {uops_6_mem_cmd}, {uops_5_mem_cmd}, {uops_4_mem_cmd}, {uops_3_mem_cmd}, {uops_2_mem_cmd}, {uops_1_mem_cmd}, {uops_0_mem_cmd}}; // @[util.scala:505:22, :547:21]
assign out_uop_mem_cmd = _GEN_85[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_86 = {{uops_0_mem_size}, {uops_14_mem_size}, {uops_13_mem_size}, {uops_12_mem_size}, {uops_11_mem_size}, {uops_10_mem_size}, {uops_9_mem_size}, {uops_8_mem_size}, {uops_7_mem_size}, {uops_6_mem_size}, {uops_5_mem_size}, {uops_4_mem_size}, {uops_3_mem_size}, {uops_2_mem_size}, {uops_1_mem_size}, {uops_0_mem_size}}; // @[util.scala:505:22, :547:21]
assign out_uop_mem_size = _GEN_86[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_87 = {{uops_0_mem_signed}, {uops_14_mem_signed}, {uops_13_mem_signed}, {uops_12_mem_signed}, {uops_11_mem_signed}, {uops_10_mem_signed}, {uops_9_mem_signed}, {uops_8_mem_signed}, {uops_7_mem_signed}, {uops_6_mem_signed}, {uops_5_mem_signed}, {uops_4_mem_signed}, {uops_3_mem_signed}, {uops_2_mem_signed}, {uops_1_mem_signed}, {uops_0_mem_signed}}; // @[util.scala:505:22, :547:21]
assign out_uop_mem_signed = _GEN_87[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_88 = {{uops_0_uses_ldq}, {uops_14_uses_ldq}, {uops_13_uses_ldq}, {uops_12_uses_ldq}, {uops_11_uses_ldq}, {uops_10_uses_ldq}, {uops_9_uses_ldq}, {uops_8_uses_ldq}, {uops_7_uses_ldq}, {uops_6_uses_ldq}, {uops_5_uses_ldq}, {uops_4_uses_ldq}, {uops_3_uses_ldq}, {uops_2_uses_ldq}, {uops_1_uses_ldq}, {uops_0_uses_ldq}}; // @[util.scala:505:22, :547:21]
assign out_uop_uses_ldq = _GEN_88[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_89 = {{uops_0_uses_stq}, {uops_14_uses_stq}, {uops_13_uses_stq}, {uops_12_uses_stq}, {uops_11_uses_stq}, {uops_10_uses_stq}, {uops_9_uses_stq}, {uops_8_uses_stq}, {uops_7_uses_stq}, {uops_6_uses_stq}, {uops_5_uses_stq}, {uops_4_uses_stq}, {uops_3_uses_stq}, {uops_2_uses_stq}, {uops_1_uses_stq}, {uops_0_uses_stq}}; // @[util.scala:505:22, :547:21]
assign out_uop_uses_stq = _GEN_89[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_90 = {{uops_0_is_unique}, {uops_14_is_unique}, {uops_13_is_unique}, {uops_12_is_unique}, {uops_11_is_unique}, {uops_10_is_unique}, {uops_9_is_unique}, {uops_8_is_unique}, {uops_7_is_unique}, {uops_6_is_unique}, {uops_5_is_unique}, {uops_4_is_unique}, {uops_3_is_unique}, {uops_2_is_unique}, {uops_1_is_unique}, {uops_0_is_unique}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_unique = _GEN_90[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_91 = {{uops_0_flush_on_commit}, {uops_14_flush_on_commit}, {uops_13_flush_on_commit}, {uops_12_flush_on_commit}, {uops_11_flush_on_commit}, {uops_10_flush_on_commit}, {uops_9_flush_on_commit}, {uops_8_flush_on_commit}, {uops_7_flush_on_commit}, {uops_6_flush_on_commit}, {uops_5_flush_on_commit}, {uops_4_flush_on_commit}, {uops_3_flush_on_commit}, {uops_2_flush_on_commit}, {uops_1_flush_on_commit}, {uops_0_flush_on_commit}}; // @[util.scala:505:22, :547:21]
assign out_uop_flush_on_commit = _GEN_91[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][2:0] _GEN_92 = {{uops_0_csr_cmd}, {uops_14_csr_cmd}, {uops_13_csr_cmd}, {uops_12_csr_cmd}, {uops_11_csr_cmd}, {uops_10_csr_cmd}, {uops_9_csr_cmd}, {uops_8_csr_cmd}, {uops_7_csr_cmd}, {uops_6_csr_cmd}, {uops_5_csr_cmd}, {uops_4_csr_cmd}, {uops_3_csr_cmd}, {uops_2_csr_cmd}, {uops_1_csr_cmd}, {uops_0_csr_cmd}}; // @[util.scala:505:22, :547:21]
assign out_uop_csr_cmd = _GEN_92[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_93 = {{uops_0_ldst_is_rs1}, {uops_14_ldst_is_rs1}, {uops_13_ldst_is_rs1}, {uops_12_ldst_is_rs1}, {uops_11_ldst_is_rs1}, {uops_10_ldst_is_rs1}, {uops_9_ldst_is_rs1}, {uops_8_ldst_is_rs1}, {uops_7_ldst_is_rs1}, {uops_6_ldst_is_rs1}, {uops_5_ldst_is_rs1}, {uops_4_ldst_is_rs1}, {uops_3_ldst_is_rs1}, {uops_2_ldst_is_rs1}, {uops_1_ldst_is_rs1}, {uops_0_ldst_is_rs1}}; // @[util.scala:505:22, :547:21]
assign out_uop_ldst_is_rs1 = _GEN_93[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][5:0] _GEN_94 = {{uops_0_ldst}, {uops_14_ldst}, {uops_13_ldst}, {uops_12_ldst}, {uops_11_ldst}, {uops_10_ldst}, {uops_9_ldst}, {uops_8_ldst}, {uops_7_ldst}, {uops_6_ldst}, {uops_5_ldst}, {uops_4_ldst}, {uops_3_ldst}, {uops_2_ldst}, {uops_1_ldst}, {uops_0_ldst}}; // @[util.scala:505:22, :547:21]
assign out_uop_ldst = _GEN_94[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][5:0] _GEN_95 = {{uops_0_lrs1}, {uops_14_lrs1}, {uops_13_lrs1}, {uops_12_lrs1}, {uops_11_lrs1}, {uops_10_lrs1}, {uops_9_lrs1}, {uops_8_lrs1}, {uops_7_lrs1}, {uops_6_lrs1}, {uops_5_lrs1}, {uops_4_lrs1}, {uops_3_lrs1}, {uops_2_lrs1}, {uops_1_lrs1}, {uops_0_lrs1}}; // @[util.scala:505:22, :547:21]
assign out_uop_lrs1 = _GEN_95[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][5:0] _GEN_96 = {{uops_0_lrs2}, {uops_14_lrs2}, {uops_13_lrs2}, {uops_12_lrs2}, {uops_11_lrs2}, {uops_10_lrs2}, {uops_9_lrs2}, {uops_8_lrs2}, {uops_7_lrs2}, {uops_6_lrs2}, {uops_5_lrs2}, {uops_4_lrs2}, {uops_3_lrs2}, {uops_2_lrs2}, {uops_1_lrs2}, {uops_0_lrs2}}; // @[util.scala:505:22, :547:21]
assign out_uop_lrs2 = _GEN_96[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][5:0] _GEN_97 = {{uops_0_lrs3}, {uops_14_lrs3}, {uops_13_lrs3}, {uops_12_lrs3}, {uops_11_lrs3}, {uops_10_lrs3}, {uops_9_lrs3}, {uops_8_lrs3}, {uops_7_lrs3}, {uops_6_lrs3}, {uops_5_lrs3}, {uops_4_lrs3}, {uops_3_lrs3}, {uops_2_lrs3}, {uops_1_lrs3}, {uops_0_lrs3}}; // @[util.scala:505:22, :547:21]
assign out_uop_lrs3 = _GEN_97[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_98 = {{uops_0_dst_rtype}, {uops_14_dst_rtype}, {uops_13_dst_rtype}, {uops_12_dst_rtype}, {uops_11_dst_rtype}, {uops_10_dst_rtype}, {uops_9_dst_rtype}, {uops_8_dst_rtype}, {uops_7_dst_rtype}, {uops_6_dst_rtype}, {uops_5_dst_rtype}, {uops_4_dst_rtype}, {uops_3_dst_rtype}, {uops_2_dst_rtype}, {uops_1_dst_rtype}, {uops_0_dst_rtype}}; // @[util.scala:505:22, :547:21]
assign out_uop_dst_rtype = _GEN_98[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_99 = {{uops_0_lrs1_rtype}, {uops_14_lrs1_rtype}, {uops_13_lrs1_rtype}, {uops_12_lrs1_rtype}, {uops_11_lrs1_rtype}, {uops_10_lrs1_rtype}, {uops_9_lrs1_rtype}, {uops_8_lrs1_rtype}, {uops_7_lrs1_rtype}, {uops_6_lrs1_rtype}, {uops_5_lrs1_rtype}, {uops_4_lrs1_rtype}, {uops_3_lrs1_rtype}, {uops_2_lrs1_rtype}, {uops_1_lrs1_rtype}, {uops_0_lrs1_rtype}}; // @[util.scala:505:22, :547:21]
assign out_uop_lrs1_rtype = _GEN_99[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_100 = {{uops_0_lrs2_rtype}, {uops_14_lrs2_rtype}, {uops_13_lrs2_rtype}, {uops_12_lrs2_rtype}, {uops_11_lrs2_rtype}, {uops_10_lrs2_rtype}, {uops_9_lrs2_rtype}, {uops_8_lrs2_rtype}, {uops_7_lrs2_rtype}, {uops_6_lrs2_rtype}, {uops_5_lrs2_rtype}, {uops_4_lrs2_rtype}, {uops_3_lrs2_rtype}, {uops_2_lrs2_rtype}, {uops_1_lrs2_rtype}, {uops_0_lrs2_rtype}}; // @[util.scala:505:22, :547:21]
assign out_uop_lrs2_rtype = _GEN_100[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_101 = {{uops_0_frs3_en}, {uops_14_frs3_en}, {uops_13_frs3_en}, {uops_12_frs3_en}, {uops_11_frs3_en}, {uops_10_frs3_en}, {uops_9_frs3_en}, {uops_8_frs3_en}, {uops_7_frs3_en}, {uops_6_frs3_en}, {uops_5_frs3_en}, {uops_4_frs3_en}, {uops_3_frs3_en}, {uops_2_frs3_en}, {uops_1_frs3_en}, {uops_0_frs3_en}}; // @[util.scala:505:22, :547:21]
assign out_uop_frs3_en = _GEN_101[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_102 = {{uops_0_fcn_dw}, {uops_14_fcn_dw}, {uops_13_fcn_dw}, {uops_12_fcn_dw}, {uops_11_fcn_dw}, {uops_10_fcn_dw}, {uops_9_fcn_dw}, {uops_8_fcn_dw}, {uops_7_fcn_dw}, {uops_6_fcn_dw}, {uops_5_fcn_dw}, {uops_4_fcn_dw}, {uops_3_fcn_dw}, {uops_2_fcn_dw}, {uops_1_fcn_dw}, {uops_0_fcn_dw}}; // @[util.scala:505:22, :547:21]
assign out_uop_fcn_dw = _GEN_102[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][4:0] _GEN_103 = {{uops_0_fcn_op}, {uops_14_fcn_op}, {uops_13_fcn_op}, {uops_12_fcn_op}, {uops_11_fcn_op}, {uops_10_fcn_op}, {uops_9_fcn_op}, {uops_8_fcn_op}, {uops_7_fcn_op}, {uops_6_fcn_op}, {uops_5_fcn_op}, {uops_4_fcn_op}, {uops_3_fcn_op}, {uops_2_fcn_op}, {uops_1_fcn_op}, {uops_0_fcn_op}}; // @[util.scala:505:22, :547:21]
assign out_uop_fcn_op = _GEN_103[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_104 = {{uops_0_fp_val}, {uops_14_fp_val}, {uops_13_fp_val}, {uops_12_fp_val}, {uops_11_fp_val}, {uops_10_fp_val}, {uops_9_fp_val}, {uops_8_fp_val}, {uops_7_fp_val}, {uops_6_fp_val}, {uops_5_fp_val}, {uops_4_fp_val}, {uops_3_fp_val}, {uops_2_fp_val}, {uops_1_fp_val}, {uops_0_fp_val}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_val = _GEN_104[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][2:0] _GEN_105 = {{uops_0_fp_rm}, {uops_14_fp_rm}, {uops_13_fp_rm}, {uops_12_fp_rm}, {uops_11_fp_rm}, {uops_10_fp_rm}, {uops_9_fp_rm}, {uops_8_fp_rm}, {uops_7_fp_rm}, {uops_6_fp_rm}, {uops_5_fp_rm}, {uops_4_fp_rm}, {uops_3_fp_rm}, {uops_2_fp_rm}, {uops_1_fp_rm}, {uops_0_fp_rm}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_rm = _GEN_105[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_106 = {{uops_0_fp_typ}, {uops_14_fp_typ}, {uops_13_fp_typ}, {uops_12_fp_typ}, {uops_11_fp_typ}, {uops_10_fp_typ}, {uops_9_fp_typ}, {uops_8_fp_typ}, {uops_7_fp_typ}, {uops_6_fp_typ}, {uops_5_fp_typ}, {uops_4_fp_typ}, {uops_3_fp_typ}, {uops_2_fp_typ}, {uops_1_fp_typ}, {uops_0_fp_typ}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_typ = _GEN_106[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_107 = {{uops_0_xcpt_pf_if}, {uops_14_xcpt_pf_if}, {uops_13_xcpt_pf_if}, {uops_12_xcpt_pf_if}, {uops_11_xcpt_pf_if}, {uops_10_xcpt_pf_if}, {uops_9_xcpt_pf_if}, {uops_8_xcpt_pf_if}, {uops_7_xcpt_pf_if}, {uops_6_xcpt_pf_if}, {uops_5_xcpt_pf_if}, {uops_4_xcpt_pf_if}, {uops_3_xcpt_pf_if}, {uops_2_xcpt_pf_if}, {uops_1_xcpt_pf_if}, {uops_0_xcpt_pf_if}}; // @[util.scala:505:22, :547:21]
assign out_uop_xcpt_pf_if = _GEN_107[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_108 = {{uops_0_xcpt_ae_if}, {uops_14_xcpt_ae_if}, {uops_13_xcpt_ae_if}, {uops_12_xcpt_ae_if}, {uops_11_xcpt_ae_if}, {uops_10_xcpt_ae_if}, {uops_9_xcpt_ae_if}, {uops_8_xcpt_ae_if}, {uops_7_xcpt_ae_if}, {uops_6_xcpt_ae_if}, {uops_5_xcpt_ae_if}, {uops_4_xcpt_ae_if}, {uops_3_xcpt_ae_if}, {uops_2_xcpt_ae_if}, {uops_1_xcpt_ae_if}, {uops_0_xcpt_ae_if}}; // @[util.scala:505:22, :547:21]
assign out_uop_xcpt_ae_if = _GEN_108[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_109 = {{uops_0_xcpt_ma_if}, {uops_14_xcpt_ma_if}, {uops_13_xcpt_ma_if}, {uops_12_xcpt_ma_if}, {uops_11_xcpt_ma_if}, {uops_10_xcpt_ma_if}, {uops_9_xcpt_ma_if}, {uops_8_xcpt_ma_if}, {uops_7_xcpt_ma_if}, {uops_6_xcpt_ma_if}, {uops_5_xcpt_ma_if}, {uops_4_xcpt_ma_if}, {uops_3_xcpt_ma_if}, {uops_2_xcpt_ma_if}, {uops_1_xcpt_ma_if}, {uops_0_xcpt_ma_if}}; // @[util.scala:505:22, :547:21]
assign out_uop_xcpt_ma_if = _GEN_109[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_110 = {{uops_0_bp_debug_if}, {uops_14_bp_debug_if}, {uops_13_bp_debug_if}, {uops_12_bp_debug_if}, {uops_11_bp_debug_if}, {uops_10_bp_debug_if}, {uops_9_bp_debug_if}, {uops_8_bp_debug_if}, {uops_7_bp_debug_if}, {uops_6_bp_debug_if}, {uops_5_bp_debug_if}, {uops_4_bp_debug_if}, {uops_3_bp_debug_if}, {uops_2_bp_debug_if}, {uops_1_bp_debug_if}, {uops_0_bp_debug_if}}; // @[util.scala:505:22, :547:21]
assign out_uop_bp_debug_if = _GEN_110[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_111 = {{uops_0_bp_xcpt_if}, {uops_14_bp_xcpt_if}, {uops_13_bp_xcpt_if}, {uops_12_bp_xcpt_if}, {uops_11_bp_xcpt_if}, {uops_10_bp_xcpt_if}, {uops_9_bp_xcpt_if}, {uops_8_bp_xcpt_if}, {uops_7_bp_xcpt_if}, {uops_6_bp_xcpt_if}, {uops_5_bp_xcpt_if}, {uops_4_bp_xcpt_if}, {uops_3_bp_xcpt_if}, {uops_2_bp_xcpt_if}, {uops_1_bp_xcpt_if}, {uops_0_bp_xcpt_if}}; // @[util.scala:505:22, :547:21]
assign out_uop_bp_xcpt_if = _GEN_111[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][2:0] _GEN_112 = {{uops_0_debug_fsrc}, {uops_14_debug_fsrc}, {uops_13_debug_fsrc}, {uops_12_debug_fsrc}, {uops_11_debug_fsrc}, {uops_10_debug_fsrc}, {uops_9_debug_fsrc}, {uops_8_debug_fsrc}, {uops_7_debug_fsrc}, {uops_6_debug_fsrc}, {uops_5_debug_fsrc}, {uops_4_debug_fsrc}, {uops_3_debug_fsrc}, {uops_2_debug_fsrc}, {uops_1_debug_fsrc}, {uops_0_debug_fsrc}}; // @[util.scala:505:22, :547:21]
assign out_uop_debug_fsrc = _GEN_112[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][2:0] _GEN_113 = {{uops_0_debug_tsrc}, {uops_14_debug_tsrc}, {uops_13_debug_tsrc}, {uops_12_debug_tsrc}, {uops_11_debug_tsrc}, {uops_10_debug_tsrc}, {uops_9_debug_tsrc}, {uops_8_debug_tsrc}, {uops_7_debug_tsrc}, {uops_6_debug_tsrc}, {uops_5_debug_tsrc}, {uops_4_debug_tsrc}, {uops_3_debug_tsrc}, {uops_2_debug_tsrc}, {uops_1_debug_tsrc}, {uops_0_debug_tsrc}}; // @[util.scala:505:22, :547:21]
assign out_uop_debug_tsrc = _GEN_113[deq_ptr_value]; // @[Counter.scala:61:40]
wire _io_deq_valid_T = ~io_empty_0; // @[util.scala:458:7, :515:71, :548:32]
assign _io_deq_valid_T_1 = _io_deq_valid_T & _GEN_0; // @[util.scala:515:44, :548:{32,42}]
assign io_deq_valid_0 = _io_deq_valid_T_1; // @[util.scala:458:7, :548:42]
wire [4:0] _ptr_diff_T = _GEN_1 - _GEN_2; // @[Counter.scala:77:24]
wire [3:0] ptr_diff = _ptr_diff_T[3:0]; // @[util.scala:551:34]
wire [3:0] _io_count_T = {4{maybe_full}}; // @[util.scala:509:29, :557:12]
wire _io_count_T_1 = deq_ptr_value > enq_ptr_value; // @[Counter.scala:61:40]
wire [4:0] _io_count_T_2 = {1'h0, ptr_diff} + 5'hF; // @[util.scala:551:34, :560:26]
wire [3:0] _io_count_T_3 = _io_count_T_2[3:0]; // @[util.scala:560:26]
wire [3:0] _io_count_T_4 = _io_count_T_1 ? _io_count_T_3 : ptr_diff; // @[util.scala:551:34, :559:{12,27}, :560:26]
assign _io_count_T_5 = ptr_match ? _io_count_T : _io_count_T_4; // @[util.scala:511:35, :556:22, :557:12, :559:12]
assign io_count_0 = _io_count_T_5; // @[util.scala:458:7, :556:22]
wire _GEN_114 = enq_ptr_value == 4'h0; // @[Counter.scala:61:40]
wire _GEN_115 = do_enq & _GEN_114; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_116 = enq_ptr_value == 4'h1; // @[Counter.scala:61:40]
wire _GEN_117 = do_enq & _GEN_116; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_118 = enq_ptr_value == 4'h2; // @[Counter.scala:61:40]
wire _GEN_119 = do_enq & _GEN_118; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_120 = enq_ptr_value == 4'h3; // @[Counter.scala:61:40]
wire _GEN_121 = do_enq & _GEN_120; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_122 = enq_ptr_value == 4'h4; // @[Counter.scala:61:40]
wire _GEN_123 = do_enq & _GEN_122; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_124 = enq_ptr_value == 4'h5; // @[Counter.scala:61:40]
wire _GEN_125 = do_enq & _GEN_124; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_126 = enq_ptr_value == 4'h6; // @[Counter.scala:61:40]
wire _GEN_127 = do_enq & _GEN_126; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_128 = enq_ptr_value == 4'h7; // @[Counter.scala:61:40]
wire _GEN_129 = do_enq & _GEN_128; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_130 = enq_ptr_value == 4'h8; // @[Counter.scala:61:40]
wire _GEN_131 = do_enq & _GEN_130; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_132 = enq_ptr_value == 4'h9; // @[Counter.scala:61:40]
wire _GEN_133 = do_enq & _GEN_132; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_134 = enq_ptr_value == 4'hA; // @[Counter.scala:61:40]
wire _GEN_135 = do_enq & _GEN_134; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_136 = enq_ptr_value == 4'hB; // @[Counter.scala:61:40]
wire _GEN_137 = do_enq & _GEN_136; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_138 = enq_ptr_value == 4'hC; // @[Counter.scala:61:40]
wire _GEN_139 = do_enq & _GEN_138; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_140 = enq_ptr_value == 4'hD; // @[Counter.scala:61:40]
wire _GEN_141 = do_enq & _GEN_140; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_142 = do_enq & wrap; // @[Counter.scala:73:24]
always @(posedge clock) begin // @[util.scala:458:7]
if (reset) begin // @[util.scala:458:7]
valids_0 <= 1'h0; // @[util.scala:504:26]
valids_1 <= 1'h0; // @[util.scala:504:26]
valids_2 <= 1'h0; // @[util.scala:504:26]
valids_3 <= 1'h0; // @[util.scala:504:26]
valids_4 <= 1'h0; // @[util.scala:504:26]
valids_5 <= 1'h0; // @[util.scala:504:26]
valids_6 <= 1'h0; // @[util.scala:504:26]
valids_7 <= 1'h0; // @[util.scala:504:26]
valids_8 <= 1'h0; // @[util.scala:504:26]
valids_9 <= 1'h0; // @[util.scala:504:26]
valids_10 <= 1'h0; // @[util.scala:504:26]
valids_11 <= 1'h0; // @[util.scala:504:26]
valids_12 <= 1'h0; // @[util.scala:504:26]
valids_13 <= 1'h0; // @[util.scala:504:26]
valids_14 <= 1'h0; // @[util.scala:504:26]
enq_ptr_value <= 4'h0; // @[Counter.scala:61:40]
deq_ptr_value <= 4'h0; // @[Counter.scala:61:40]
maybe_full <= 1'h0; // @[util.scala:509:29]
end
else begin // @[util.scala:458:7]
valids_0 <= ~(do_deq & deq_ptr_value == 4'h0) & (_GEN_115 | _valids_0_T_7); // @[Counter.scala:61:40]
valids_1 <= ~(do_deq & deq_ptr_value == 4'h1) & (_GEN_117 | _valids_1_T_7); // @[Counter.scala:61:40]
valids_2 <= ~(do_deq & deq_ptr_value == 4'h2) & (_GEN_119 | _valids_2_T_7); // @[Counter.scala:61:40]
valids_3 <= ~(do_deq & deq_ptr_value == 4'h3) & (_GEN_121 | _valids_3_T_7); // @[Counter.scala:61:40]
valids_4 <= ~(do_deq & deq_ptr_value == 4'h4) & (_GEN_123 | _valids_4_T_7); // @[Counter.scala:61:40]
valids_5 <= ~(do_deq & deq_ptr_value == 4'h5) & (_GEN_125 | _valids_5_T_7); // @[Counter.scala:61:40]
valids_6 <= ~(do_deq & deq_ptr_value == 4'h6) & (_GEN_127 | _valids_6_T_7); // @[Counter.scala:61:40]
valids_7 <= ~(do_deq & deq_ptr_value == 4'h7) & (_GEN_129 | _valids_7_T_7); // @[Counter.scala:61:40]
valids_8 <= ~(do_deq & deq_ptr_value == 4'h8) & (_GEN_131 | _valids_8_T_7); // @[Counter.scala:61:40]
valids_9 <= ~(do_deq & deq_ptr_value == 4'h9) & (_GEN_133 | _valids_9_T_7); // @[Counter.scala:61:40]
valids_10 <= ~(do_deq & deq_ptr_value == 4'hA) & (_GEN_135 | _valids_10_T_7); // @[Counter.scala:61:40]
valids_11 <= ~(do_deq & deq_ptr_value == 4'hB) & (_GEN_137 | _valids_11_T_7); // @[Counter.scala:61:40]
valids_12 <= ~(do_deq & deq_ptr_value == 4'hC) & (_GEN_139 | _valids_12_T_7); // @[Counter.scala:61:40]
valids_13 <= ~(do_deq & deq_ptr_value == 4'hD) & (_GEN_141 | _valids_13_T_7); // @[Counter.scala:61:40]
valids_14 <= ~(do_deq & wrap_1) & (_GEN_142 | _valids_14_T_7); // @[Counter.scala:73:24]
if (do_enq) // @[util.scala:514:26]
enq_ptr_value <= wrap ? 4'h0 : _value_T_1; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}]
if (do_deq) // @[util.scala:515:26]
deq_ptr_value <= wrap_1 ? 4'h0 : _value_T_3; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}]
if (~(do_enq == do_deq)) // @[util.scala:509:29, :514:26, :515:26, :539:{18,30}, :540:18]
maybe_full <= do_enq; // @[util.scala:509:29, :514:26]
end
if (_GEN_115) begin // @[util.scala:520:18, :526:19, :528:35]
uops_0_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_0_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_0_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_0_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_0_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_0_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_0_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_0_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_0_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_0_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_0_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_0_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_0_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_0_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_0_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_0_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_0_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_0_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_0_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_0_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_0_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_0_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_0_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_0_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_0_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_0_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_0_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_0_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_0_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_0_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_0_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_0_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_0_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_0_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_0_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_0_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_0_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_0_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_0_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_0_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_0_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_0_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_0_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_0_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_0_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_0_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_0_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_0_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_0_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_0_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_0_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_0_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_0_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_0_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_0_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_0_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_0_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_0_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_0_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_0_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_0_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_0_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_0_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_0_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_0_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_0_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_0_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_0_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_0_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_0_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_0_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_0_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_0_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_0_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_0_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_0_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_0_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_0_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_0_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_0_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_0_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_0_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_0_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_114) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_0_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_0) // @[util.scala:504:26]
uops_0_br_mask <= _uops_0_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_117) begin // @[util.scala:520:18, :526:19, :528:35]
uops_1_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_1_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_1_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_1_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_1_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_1_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_1_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_1_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_1_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_1_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_1_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_1_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_1_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_1_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_1_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_1_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_1_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_1_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_1_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_1_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_1_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_1_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_1_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_1_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_1_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_1_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_1_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_1_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_1_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_1_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_1_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_1_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_1_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_1_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_1_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_1_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_1_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_1_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_1_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_1_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_1_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_1_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_1_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_1_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_1_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_1_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_1_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_1_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_1_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_1_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_1_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_1_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_1_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_1_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_1_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_1_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_1_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_1_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_1_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_1_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_1_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_1_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_1_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_1_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_1_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_1_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_1_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_1_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_1_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_1_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_1_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_1_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_1_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_1_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_1_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_1_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_1_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_1_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_1_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_1_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_1_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_1_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_1_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_116) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_1_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_1) // @[util.scala:504:26]
uops_1_br_mask <= _uops_1_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_119) begin // @[util.scala:520:18, :526:19, :528:35]
uops_2_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_2_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_2_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_2_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_2_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_2_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_2_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_2_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_2_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_2_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_2_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_2_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_2_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_2_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_2_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_2_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_2_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_2_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_2_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_2_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_2_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_2_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_2_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_2_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_2_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_2_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_2_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_2_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_2_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_2_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_2_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_2_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_2_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_2_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_2_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_2_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_2_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_2_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_2_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_2_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_2_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_2_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_2_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_2_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_2_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_2_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_2_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_2_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_2_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_2_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_2_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_2_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_2_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_2_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_2_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_2_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_2_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_2_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_2_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_2_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_2_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_2_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_2_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_2_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_2_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_2_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_2_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_2_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_2_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_2_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_2_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_2_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_2_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_2_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_2_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_2_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_2_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_2_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_2_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_2_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_2_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_2_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_2_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_118) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_2_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_2) // @[util.scala:504:26]
uops_2_br_mask <= _uops_2_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_121) begin // @[util.scala:520:18, :526:19, :528:35]
uops_3_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_3_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_3_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_3_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_3_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_3_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_3_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_3_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_3_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_3_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_3_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_3_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_3_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_3_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_3_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_3_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_3_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_3_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_3_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_3_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_3_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_3_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_3_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_3_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_3_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_3_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_3_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_3_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_3_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_3_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_3_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_3_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_3_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_3_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_3_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_3_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_3_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_3_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_3_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_3_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_3_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_3_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_3_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_3_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_3_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_3_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_3_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_3_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_3_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_3_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_3_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_3_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_3_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_3_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_3_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_3_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_3_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_3_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_3_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_3_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_3_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_3_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_3_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_3_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_3_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_3_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_3_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_3_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_3_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_3_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_3_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_3_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_3_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_3_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_3_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_3_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_3_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_3_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_3_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_3_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_3_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_3_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_3_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_120) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_3_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_3) // @[util.scala:504:26]
uops_3_br_mask <= _uops_3_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_123) begin // @[util.scala:520:18, :526:19, :528:35]
uops_4_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_4_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_4_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_4_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_4_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_4_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_4_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_4_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_4_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_4_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_4_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_4_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_4_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_4_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_4_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_4_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_4_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_4_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_4_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_4_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_4_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_4_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_4_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_4_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_4_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_4_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_4_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_4_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_4_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_4_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_4_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_4_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_4_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_4_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_4_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_4_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_4_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_4_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_4_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_4_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_4_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_4_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_4_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_4_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_4_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_4_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_4_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_4_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_4_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_4_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_4_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_4_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_4_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_4_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_4_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_4_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_4_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_4_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_4_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_4_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_4_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_4_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_4_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_4_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_4_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_4_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_4_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_4_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_4_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_4_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_4_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_4_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_4_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_4_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_4_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_4_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_4_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_4_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_4_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_4_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_4_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_4_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_4_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_122) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_4_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_4) // @[util.scala:504:26]
uops_4_br_mask <= _uops_4_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_125) begin // @[util.scala:520:18, :526:19, :528:35]
uops_5_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_5_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_5_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_5_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_5_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_5_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_5_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_5_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_5_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_5_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_5_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_5_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_5_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_5_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_5_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_5_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_5_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_5_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_5_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_5_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_5_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_5_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_5_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_5_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_5_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_5_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_5_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_5_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_5_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_5_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_5_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_5_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_5_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_5_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_5_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_5_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_5_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_5_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_5_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_5_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_5_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_5_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_5_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_5_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_5_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_5_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_5_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_5_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_5_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_5_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_5_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_5_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_5_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_5_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_5_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_5_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_5_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_5_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_5_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_5_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_5_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_5_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_5_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_5_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_5_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_5_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_5_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_5_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_5_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_5_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_5_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_5_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_5_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_5_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_5_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_5_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_5_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_5_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_5_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_5_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_5_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_5_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_5_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_124) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_5_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_5) // @[util.scala:504:26]
uops_5_br_mask <= _uops_5_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_127) begin // @[util.scala:520:18, :526:19, :528:35]
uops_6_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_6_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_6_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_6_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_6_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_6_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_6_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_6_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_6_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_6_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_6_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_6_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_6_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_6_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_6_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_6_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_6_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_6_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_6_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_6_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_6_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_6_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_6_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_6_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_6_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_6_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_6_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_6_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_6_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_6_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_6_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_6_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_6_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_6_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_6_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_6_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_6_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_6_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_6_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_6_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_6_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_6_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_6_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_6_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_6_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_6_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_6_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_6_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_6_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_6_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_6_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_6_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_6_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_6_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_6_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_6_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_6_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_6_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_6_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_6_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_6_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_6_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_6_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_6_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_6_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_6_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_6_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_6_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_6_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_6_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_6_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_6_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_6_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_6_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_6_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_6_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_6_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_6_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_6_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_6_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_6_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_6_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_6_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_126) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_6_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_6) // @[util.scala:504:26]
uops_6_br_mask <= _uops_6_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_129) begin // @[util.scala:520:18, :526:19, :528:35]
uops_7_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_7_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_7_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_7_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_7_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_7_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_7_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_7_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_7_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_7_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_7_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_7_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_7_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_7_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_7_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_7_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_7_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_7_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_7_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_7_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_7_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_7_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_7_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_7_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_7_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_7_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_7_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_7_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_7_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_7_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_7_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_7_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_7_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_7_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_7_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_7_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_7_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_7_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_7_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_7_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_7_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_7_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_7_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_7_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_7_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_7_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_7_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_7_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_7_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_7_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_7_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_7_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_7_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_7_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_7_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_7_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_7_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_7_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_7_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_7_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_7_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_7_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_7_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_7_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_7_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_7_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_7_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_7_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_7_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_7_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_7_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_7_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_7_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_7_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_7_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_7_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_7_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_7_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_7_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_7_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_7_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_7_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_7_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_128) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_7_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_7) // @[util.scala:504:26]
uops_7_br_mask <= _uops_7_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_131) begin // @[util.scala:520:18, :526:19, :528:35]
uops_8_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_8_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_8_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_8_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_8_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_8_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_8_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_8_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_8_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_8_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_8_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_8_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_8_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_8_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_8_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_8_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_8_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_8_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_8_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_8_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_8_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_8_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_8_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_8_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_8_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_8_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_8_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_8_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_8_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_8_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_8_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_8_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_8_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_8_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_8_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_8_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_8_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_8_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_8_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_8_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_8_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_8_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_8_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_8_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_8_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_8_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_8_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_8_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_8_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_8_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_8_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_8_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_8_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_8_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_8_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_8_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_8_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_8_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_8_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_8_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_8_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_8_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_8_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_8_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_8_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_8_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_8_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_8_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_8_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_8_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_8_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_8_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_8_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_8_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_8_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_8_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_8_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_8_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_8_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_8_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_8_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_8_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_8_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_8_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_8_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_8_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_8_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_8_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_8_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_8_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_8_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_8_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_8_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_130) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_8_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_8) // @[util.scala:504:26]
uops_8_br_mask <= _uops_8_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_133) begin // @[util.scala:520:18, :526:19, :528:35]
uops_9_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_9_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_9_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_9_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_9_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_9_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_9_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_9_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_9_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_9_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_9_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_9_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_9_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_9_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_9_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_9_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_9_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_9_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_9_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_9_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_9_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_9_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_9_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_9_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_9_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_9_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_9_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_9_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_9_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_9_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_9_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_9_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_9_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_9_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_9_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_9_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_9_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_9_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_9_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_9_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_9_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_9_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_9_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_9_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_9_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_9_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_9_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_9_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_9_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_9_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_9_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_9_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_9_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_9_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_9_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_9_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_9_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_9_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_9_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_9_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_9_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_9_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_9_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_9_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_9_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_9_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_9_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_9_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_9_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_9_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_9_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_9_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_9_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_9_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_9_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_9_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_9_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_9_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_9_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_9_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_9_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_9_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_9_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_9_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_9_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_9_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_9_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_9_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_9_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_9_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_9_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_9_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_9_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_132) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_9_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_9) // @[util.scala:504:26]
uops_9_br_mask <= _uops_9_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_135) begin // @[util.scala:520:18, :526:19, :528:35]
uops_10_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_10_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_10_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_10_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_10_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_10_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_10_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_10_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_10_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_10_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_10_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_10_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_10_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_10_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_10_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_10_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_10_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_10_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_10_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_10_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_10_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_10_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_10_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_10_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_10_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_10_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_10_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_10_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_10_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_10_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_10_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_10_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_10_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_10_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_10_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_10_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_10_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_10_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_10_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_10_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_10_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_10_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_10_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_10_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_10_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_10_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_10_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_10_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_10_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_10_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_10_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_10_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_10_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_10_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_10_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_10_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_10_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_10_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_10_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_10_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_10_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_10_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_10_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_10_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_10_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_10_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_10_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_10_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_10_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_10_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_10_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_10_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_10_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_10_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_10_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_10_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_10_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_10_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_10_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_10_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_10_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_10_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_10_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_10_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_10_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_10_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_10_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_10_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_10_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_10_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_10_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_10_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_10_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_10_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_10_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_10_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_10_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_10_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_10_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_10_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_10_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_10_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_10_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_10_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_10_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_10_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_10_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_10_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_10_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_10_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_134) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_10_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_10) // @[util.scala:504:26]
uops_10_br_mask <= _uops_10_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_137) begin // @[util.scala:520:18, :526:19, :528:35]
uops_11_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_11_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_11_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_11_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_11_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_11_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_11_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_11_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_11_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_11_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_11_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_11_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_11_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_11_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_11_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_11_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_11_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_11_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_11_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_11_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_11_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_11_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_11_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_11_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_11_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_11_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_11_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_11_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_11_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_11_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_11_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_11_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_11_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_11_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_11_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_11_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_11_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_11_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_11_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_11_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_11_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_11_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_11_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_11_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_11_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_11_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_11_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_11_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_11_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_11_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_11_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_11_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_11_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_11_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_11_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_11_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_11_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_11_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_11_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_11_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_11_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_11_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_11_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_11_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_11_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_11_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_11_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_11_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_11_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_11_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_11_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_11_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_11_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_11_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_11_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_11_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_11_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_11_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_11_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_11_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_11_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_11_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_11_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_11_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_11_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_11_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_11_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_11_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_11_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_11_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_11_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_11_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_11_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_11_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_11_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_11_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_11_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_11_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_11_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_11_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_11_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_11_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_11_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_11_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_11_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_11_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_11_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_11_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_11_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_11_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_136) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_11_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_11) // @[util.scala:504:26]
uops_11_br_mask <= _uops_11_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_139) begin // @[util.scala:520:18, :526:19, :528:35]
uops_12_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_12_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_12_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_12_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_12_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_12_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_12_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_12_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_12_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_12_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_12_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_12_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_12_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_12_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_12_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_12_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_12_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_12_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_12_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_12_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_12_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_12_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_12_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_12_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_12_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_12_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_12_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_12_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_12_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_12_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_12_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_12_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_12_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_12_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_12_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_12_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_12_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_12_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_12_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_12_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_12_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_12_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_12_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_12_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_12_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_12_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_12_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_12_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_12_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_12_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_12_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_12_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_12_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_12_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_12_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_12_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_12_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_12_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_12_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_12_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_12_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_12_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_12_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_12_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_12_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_12_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_12_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_12_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_12_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_12_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_12_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_12_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_12_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_12_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_12_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_12_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_12_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_12_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_12_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_12_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_12_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_12_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_12_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_12_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_12_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_12_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_12_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_12_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_12_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_12_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_12_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_12_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_12_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_12_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_12_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_12_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_12_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_12_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_12_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_12_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_12_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_12_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_12_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_12_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_12_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_12_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_12_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_12_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_12_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_12_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_138) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_12_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_12) // @[util.scala:504:26]
uops_12_br_mask <= _uops_12_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_141) begin // @[util.scala:520:18, :526:19, :528:35]
uops_13_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_13_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_13_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_13_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_13_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_13_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_13_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_13_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_13_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_13_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_13_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_13_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_13_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_13_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_13_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_13_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_13_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_13_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_13_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_13_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_13_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_13_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_13_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_13_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_13_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_13_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_13_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_13_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_13_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_13_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_13_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_13_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_13_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_13_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_13_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_13_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_13_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_13_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_13_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_13_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_13_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_13_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_13_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_13_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_13_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_13_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_13_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_13_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_13_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_13_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_13_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_13_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_13_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_13_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_13_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_13_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_13_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_13_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_13_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_13_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_13_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_13_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_13_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_13_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_13_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_13_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_13_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_13_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_13_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_13_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_13_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_13_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_13_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_13_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_13_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_13_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_13_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_13_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_13_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_13_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_13_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_13_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_13_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_13_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_13_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_13_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_13_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_13_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_13_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_13_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_13_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_13_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_13_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_13_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_13_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_13_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_13_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_13_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_13_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_13_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_13_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_13_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_13_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_13_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_13_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_13_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_13_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_13_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_13_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_13_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_140) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_13_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_13) // @[util.scala:504:26]
uops_13_br_mask <= _uops_13_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_142) begin // @[util.scala:520:18, :526:19, :528:35]
uops_14_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_14_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_14_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_14_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_14_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_14_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_14_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_14_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_14_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_14_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_14_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_14_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_14_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_14_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_14_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_14_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_14_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_14_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_14_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_14_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_14_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_14_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_14_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_14_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_14_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_14_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_14_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_14_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_14_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_14_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_14_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_14_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_14_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_14_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_14_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_14_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_14_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_14_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_14_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_14_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_14_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_14_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_14_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_14_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_14_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_14_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_14_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_14_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_14_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_14_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_14_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_14_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_14_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_14_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_14_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_14_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_14_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_14_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_14_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_14_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_14_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_14_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_14_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_14_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_14_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_14_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_14_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_14_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_14_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_14_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_14_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_14_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_14_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_14_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_14_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_14_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_14_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_14_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_14_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_14_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_14_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_14_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_14_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_14_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_14_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_14_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_14_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_14_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_14_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_14_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_14_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_14_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_14_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_14_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_14_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_14_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_14_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_14_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_14_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_14_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_14_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_14_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_14_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_14_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_14_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_14_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_14_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_14_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_14_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_14_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & wrap) // @[Counter.scala:73:24]
uops_14_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_14) // @[util.scala:504:26]
uops_14_br_mask <= _uops_14_br_mask_T_1; // @[util.scala:97:21, :505:22]
always @(posedge)
ram_15x141 ram_ext ( // @[util.scala:503:22]
.R0_addr (deq_ptr_value), // @[Counter.scala:61:40]
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (_ram_ext_R0_data),
.W0_addr (enq_ptr_value), // @[Counter.scala:61:40]
.W0_en (do_enq), // @[util.scala:514:26]
.W0_clk (clock),
.W0_data ({io_enq_bits_sdq_id_0, io_enq_bits_way_en_0, io_enq_bits_old_meta_tag_0, io_enq_bits_old_meta_coh_state_0, io_enq_bits_tag_match_0, io_enq_bits_is_hella_0, io_enq_bits_data_0, io_enq_bits_addr_0}) // @[util.scala:458:7, :503:22]
); // @[util.scala:503:22]
assign io_enq_ready = io_enq_ready_0; // @[util.scala:458:7]
assign io_deq_valid = io_deq_valid_0; // @[util.scala:458:7]
assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_0 = io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_1 = io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_2 = io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_3 = io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_0 = io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_1 = io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_2 = io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_3 = io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_4 = io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_5 = io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_6 = io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_7 = io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_8 = io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_9 = io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_issued = io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_issued_partial_agen = io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_issued_partial_dgen = io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p1_speculative_child = io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p2_speculative_child = io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p1_bypass_hint = io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p2_bypass_hint = io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p3_bypass_hint = io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_dis_col_sel = io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:458:7]
assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:458:7]
assign io_deq_bits_uop_br_type = io_deq_bits_uop_br_type_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_sfence = io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_eret = io_deq_bits_uop_is_eret_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_rocc = io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_mov = io_deq_bits_uop_is_mov_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7]
assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:458:7]
assign io_deq_bits_uop_imm_rename = io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7]
assign io_deq_bits_uop_imm_sel = io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_pimm = io_deq_bits_uop_pimm_0; // @[util.scala:458:7]
assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7]
assign io_deq_bits_uop_op1_sel = io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_op2_sel = io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ldst = io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_wen = io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ren1 = io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ren2 = io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ren3 = io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_swap12 = io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_swap23 = io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_typeTagIn = io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_typeTagOut = io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_fromint = io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_toint = io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_fastpipe = io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_fma = io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_div = io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_sqrt = io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_wflags = io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_vec = io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7]
assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:458:7]
assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7]
assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7]
assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:458:7]
assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7]
assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7]
assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:458:7]
assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7]
assign io_deq_bits_uop_csr_cmd = io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7]
assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fcn_dw = io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fcn_op = io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_rm = io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_typ = io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7]
assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7]
assign io_deq_bits_addr = io_deq_bits_addr_0; // @[util.scala:458:7]
assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:458:7]
assign io_deq_bits_is_hella = io_deq_bits_is_hella_0; // @[util.scala:458:7]
assign io_deq_bits_tag_match = io_deq_bits_tag_match_0; // @[util.scala:458:7]
assign io_deq_bits_old_meta_coh_state = io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7]
assign io_deq_bits_old_meta_tag = io_deq_bits_old_meta_tag_0; // @[util.scala:458:7]
assign io_deq_bits_way_en = io_deq_bits_way_en_0; // @[util.scala:458:7]
assign io_deq_bits_sdq_id = io_deq_bits_sdq_id_0; // @[util.scala:458:7]
assign io_empty = io_empty_0; // @[util.scala:458:7]
assign io_count = io_count_0; // @[util.scala:458:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLFragmenter_TileResetSetter :
input clock : Clock
input reset : Reset
output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn.d.bits.corrupt
invalidate anonIn.d.bits.data
invalidate anonIn.d.bits.denied
invalidate anonIn.d.bits.sink
invalidate anonIn.d.bits.source
invalidate anonIn.d.bits.size
invalidate anonIn.d.bits.param
invalidate anonIn.d.bits.opcode
invalidate anonIn.d.valid
invalidate anonIn.d.ready
invalidate anonIn.a.bits.corrupt
invalidate anonIn.a.bits.data
invalidate anonIn.a.bits.mask
invalidate anonIn.a.bits.address
invalidate anonIn.a.bits.source
invalidate anonIn.a.bits.size
invalidate anonIn.a.bits.param
invalidate anonIn.a.bits.opcode
invalidate anonIn.a.valid
invalidate anonIn.a.ready
inst monitor of TLMonitor_120
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, anonIn.d.bits.data
connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied
connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink
connect monitor.io.in.d.bits.source, anonIn.d.bits.source
connect monitor.io.in.d.bits.size, anonIn.d.bits.size
connect monitor.io.in.d.bits.param, anonIn.d.bits.param
connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode
connect monitor.io.in.d.valid, anonIn.d.valid
connect monitor.io.in.d.ready, anonIn.d.ready
connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, anonIn.a.bits.data
connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask
connect monitor.io.in.a.bits.address, anonIn.a.bits.address
connect monitor.io.in.a.bits.source, anonIn.a.bits.source
connect monitor.io.in.a.bits.size, anonIn.a.bits.size
connect monitor.io.in.a.bits.param, anonIn.a.bits.param
connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode
connect monitor.io.in.a.valid, anonIn.a.valid
connect monitor.io.in.a.ready, anonIn.a.ready
wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonOut.d.bits.corrupt
invalidate anonOut.d.bits.data
invalidate anonOut.d.bits.denied
invalidate anonOut.d.bits.sink
invalidate anonOut.d.bits.source
invalidate anonOut.d.bits.size
invalidate anonOut.d.bits.param
invalidate anonOut.d.bits.opcode
invalidate anonOut.d.valid
invalidate anonOut.d.ready
invalidate anonOut.a.bits.corrupt
invalidate anonOut.a.bits.data
invalidate anonOut.a.bits.mask
invalidate anonOut.a.bits.address
invalidate anonOut.a.bits.source
invalidate anonOut.a.bits.size
invalidate anonOut.a.bits.param
invalidate anonOut.a.bits.opcode
invalidate anonOut.a.valid
invalidate anonOut.a.ready
connect auto.anon_out, anonOut
connect anonIn, auto.anon_in
regreset acknum : UInt<3>, clock, reset, UInt<3>(0h0)
reg dOrig : UInt, clock
regreset dToggle : UInt<1>, clock, reset, UInt<1>(0h0)
node dFragnum = bits(anonOut.d.bits.source, 2, 0)
node dFirst = eq(acknum, UInt<1>(0h0))
node dLast = eq(dFragnum, UInt<1>(0h0))
node dsizeOH_shiftAmount = bits(anonOut.d.bits.size, 1, 0)
node _dsizeOH_T = dshl(UInt<1>(0h1), dsizeOH_shiftAmount)
node dsizeOH = bits(_dsizeOH_T, 3, 0)
node _dsizeOH1_T = dshl(UInt<3>(0h7), anonOut.d.bits.size)
node _dsizeOH1_T_1 = bits(_dsizeOH1_T, 2, 0)
node dsizeOH1 = not(_dsizeOH1_T_1)
node dHasData = bits(anonOut.d.bits.opcode, 0, 0)
node acknum_fragment = shl(dFragnum, 0)
node acknum_size = shr(dsizeOH1, 3)
node _T = eq(anonOut.d.valid, UInt<1>(0h0))
node _T_1 = and(acknum_fragment, acknum_size)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = or(_T, _T_2)
node _T_4 = asUInt(reset)
node _T_5 = eq(_T_4, UInt<1>(0h0))
when _T_5 :
node _T_6 = eq(_T_3, UInt<1>(0h0))
when _T_6 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:214 assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U)\n") : printf
assert(clock, _T_3, UInt<1>(0h1), "") : assert
node _dFirst_acknum_T = mux(dHasData, acknum_size, UInt<1>(0h0))
node dFirst_acknum = or(acknum_fragment, _dFirst_acknum_T)
node _ack_decrement_T = shr(dsizeOH, 3)
node ack_decrement = mux(dHasData, UInt<1>(0h1), _ack_decrement_T)
node _dFirst_size_T = shl(dFragnum, 3)
node _dFirst_size_T_1 = or(_dFirst_size_T, dsizeOH1)
node _dFirst_size_T_2 = shl(_dFirst_size_T_1, 1)
node _dFirst_size_T_3 = or(_dFirst_size_T_2, UInt<1>(0h1))
node _dFirst_size_T_4 = cat(UInt<1>(0h0), _dFirst_size_T_1)
node _dFirst_size_T_5 = not(_dFirst_size_T_4)
node _dFirst_size_T_6 = and(_dFirst_size_T_3, _dFirst_size_T_5)
node dFirst_size_hi = bits(_dFirst_size_T_6, 6, 4)
node dFirst_size_lo = bits(_dFirst_size_T_6, 3, 0)
node _dFirst_size_T_7 = orr(dFirst_size_hi)
node _dFirst_size_T_8 = or(dFirst_size_hi, dFirst_size_lo)
node dFirst_size_hi_1 = bits(_dFirst_size_T_8, 3, 2)
node dFirst_size_lo_1 = bits(_dFirst_size_T_8, 1, 0)
node _dFirst_size_T_9 = orr(dFirst_size_hi_1)
node _dFirst_size_T_10 = or(dFirst_size_hi_1, dFirst_size_lo_1)
node _dFirst_size_T_11 = bits(_dFirst_size_T_10, 1, 1)
node _dFirst_size_T_12 = cat(_dFirst_size_T_9, _dFirst_size_T_11)
node dFirst_size = cat(_dFirst_size_T_7, _dFirst_size_T_12)
node _T_7 = and(anonOut.d.ready, anonOut.d.valid)
when _T_7 :
node _acknum_T = sub(acknum, ack_decrement)
node _acknum_T_1 = tail(_acknum_T, 1)
node _acknum_T_2 = mux(dFirst, dFirst_acknum, _acknum_T_1)
connect acknum, _acknum_T_2
when dFirst :
connect dOrig, dFirst_size
node _dToggle_T = bits(anonOut.d.bits.source, 3, 3)
connect dToggle, _dToggle_T
node _drop_T = eq(dHasData, UInt<1>(0h0))
node _drop_T_1 = mux(UInt<1>(0h0), dFirst, dLast)
node _drop_T_2 = eq(_drop_T_1, UInt<1>(0h0))
node drop = and(_drop_T, _drop_T_2)
node _anonOut_d_ready_T = or(anonIn.d.ready, drop)
connect anonOut.d.ready, _anonOut_d_ready_T
node _anonIn_d_valid_T = eq(drop, UInt<1>(0h0))
node _anonIn_d_valid_T_1 = and(anonOut.d.valid, _anonIn_d_valid_T)
connect anonIn.d.valid, _anonIn_d_valid_T_1
connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt
connect anonIn.d.bits.data, anonOut.d.bits.data
connect anonIn.d.bits.denied, anonOut.d.bits.denied
connect anonIn.d.bits.sink, anonOut.d.bits.sink
connect anonIn.d.bits.source, anonOut.d.bits.source
connect anonIn.d.bits.size, anonOut.d.bits.size
connect anonIn.d.bits.param, anonOut.d.bits.param
connect anonIn.d.bits.opcode, anonOut.d.bits.opcode
node _anonIn_d_bits_source_T = shr(anonOut.d.bits.source, 4)
connect anonIn.d.bits.source, _anonIn_d_bits_source_T
node _anonIn_d_bits_size_T = mux(dFirst, dFirst_size, dOrig)
connect anonIn.d.bits.size, _anonIn_d_bits_size_T
inst repeater of Repeater_TLBundleA_a21d64s8k1z3u_1
connect repeater.clock, clock
connect repeater.reset, reset
connect repeater.io.enq, anonIn.a
node _find_T = xor(repeater.io.deq.bits.address, UInt<1>(0h0))
node _find_T_1 = cvt(_find_T)
node _find_T_2 = and(_find_T_1, asSInt(UInt<1>(0h0)))
node _find_T_3 = asSInt(_find_T_2)
node _find_T_4 = eq(_find_T_3, asSInt(UInt<1>(0h0)))
wire find : UInt<1>[1]
connect find[0], _find_T_4
node _limit_T = eq(UInt<1>(0h0), repeater.io.deq.bits.opcode)
node _limit_T_1 = mux(_limit_T, UInt<2>(0h3), UInt<2>(0h3))
node _limit_T_2 = eq(UInt<1>(0h1), repeater.io.deq.bits.opcode)
node _limit_T_3 = mux(_limit_T_2, UInt<2>(0h3), _limit_T_1)
node _limit_T_4 = eq(UInt<2>(0h2), repeater.io.deq.bits.opcode)
node _limit_T_5 = mux(_limit_T_4, UInt<2>(0h3), _limit_T_3)
node _limit_T_6 = eq(UInt<2>(0h3), repeater.io.deq.bits.opcode)
node _limit_T_7 = mux(_limit_T_6, UInt<2>(0h3), _limit_T_5)
node _limit_T_8 = eq(UInt<3>(0h4), repeater.io.deq.bits.opcode)
node _limit_T_9 = mux(_limit_T_8, UInt<2>(0h3), _limit_T_7)
node _limit_T_10 = eq(UInt<3>(0h5), repeater.io.deq.bits.opcode)
node limit = mux(_limit_T_10, UInt<2>(0h3), _limit_T_9)
node _aFrag_T = gt(repeater.io.deq.bits.size, limit)
node aFrag = mux(_aFrag_T, limit, repeater.io.deq.bits.size)
node _aOrigOH1_T = dshl(UInt<6>(0h3f), repeater.io.deq.bits.size)
node _aOrigOH1_T_1 = bits(_aOrigOH1_T, 5, 0)
node aOrigOH1 = not(_aOrigOH1_T_1)
node _aFragOH1_T = dshl(UInt<3>(0h7), aFrag)
node _aFragOH1_T_1 = bits(_aFragOH1_T, 2, 0)
node aFragOH1 = not(_aFragOH1_T_1)
node _aHasData_opdata_T = bits(repeater.io.deq.bits.opcode, 2, 2)
node aHasData = eq(_aHasData_opdata_T, UInt<1>(0h0))
node aMask = mux(aHasData, UInt<1>(0h0), aFragOH1)
regreset gennum : UInt<3>, clock, reset, UInt<3>(0h0)
node aFirst = eq(gennum, UInt<1>(0h0))
node _old_gennum1_T = shr(aOrigOH1, 3)
node _old_gennum1_T_1 = sub(gennum, UInt<1>(0h1))
node _old_gennum1_T_2 = tail(_old_gennum1_T_1, 1)
node old_gennum1 = mux(aFirst, _old_gennum1_T, _old_gennum1_T_2)
node _new_gennum_T = not(old_gennum1)
node _new_gennum_T_1 = shr(aMask, 3)
node _new_gennum_T_2 = or(_new_gennum_T, _new_gennum_T_1)
node new_gennum = not(_new_gennum_T_2)
node _aFragnum_T = shr(old_gennum1, 0)
node _aFragnum_T_1 = not(_aFragnum_T)
node _aFragnum_T_2 = shr(aFragOH1, 3)
node _aFragnum_T_3 = or(_aFragnum_T_1, _aFragnum_T_2)
node aFragnum = not(_aFragnum_T_3)
node aLast = eq(aFragnum, UInt<1>(0h0))
reg aToggle_r : UInt<1>, clock
when aFirst :
connect aToggle_r, dToggle
node _aToggle_T = mux(aFirst, dToggle, aToggle_r)
node aToggle = eq(_aToggle_T, UInt<1>(0h0))
node _T_8 = and(anonOut.a.ready, anonOut.a.valid)
when _T_8 :
connect gennum, new_gennum
node _repeater_io_repeat_T = eq(aHasData, UInt<1>(0h0))
node _repeater_io_repeat_T_1 = neq(aFragnum, UInt<1>(0h0))
node _repeater_io_repeat_T_2 = and(_repeater_io_repeat_T, _repeater_io_repeat_T_1)
connect repeater.io.repeat, _repeater_io_repeat_T_2
connect anonOut.a.bits, repeater.io.deq.bits
connect anonOut.a.valid, repeater.io.deq.valid
connect repeater.io.deq.ready, anonOut.a.ready
node _anonOut_a_bits_address_T = shl(old_gennum1, 3)
node _anonOut_a_bits_address_T_1 = not(aOrigOH1)
node _anonOut_a_bits_address_T_2 = or(_anonOut_a_bits_address_T, _anonOut_a_bits_address_T_1)
node _anonOut_a_bits_address_T_3 = or(_anonOut_a_bits_address_T_2, aFragOH1)
node _anonOut_a_bits_address_T_4 = or(_anonOut_a_bits_address_T_3, UInt<3>(0h7))
node _anonOut_a_bits_address_T_5 = not(_anonOut_a_bits_address_T_4)
node _anonOut_a_bits_address_T_6 = or(repeater.io.deq.bits.address, _anonOut_a_bits_address_T_5)
connect anonOut.a.bits.address, _anonOut_a_bits_address_T_6
node anonOut_a_bits_source_hi = cat(repeater.io.deq.bits.source, aToggle)
node _anonOut_a_bits_source_T = cat(anonOut_a_bits_source_hi, aFragnum)
connect anonOut.a.bits.source, _anonOut_a_bits_source_T
connect anonOut.a.bits.size, aFrag
node _T_9 = eq(repeater.io.full, UInt<1>(0h0))
node _T_10 = eq(aHasData, UInt<1>(0h0))
node _T_11 = or(_T_9, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:321 assert (!repeater.io.full || !aHasData)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
connect anonOut.a.bits.data, anonIn.a.bits.data
node _T_15 = eq(repeater.io.full, UInt<1>(0h0))
node _T_16 = eq(repeater.io.deq.bits.mask, UInt<8>(0hff))
node _T_17 = or(_T_15, _T_16)
node _T_18 = asUInt(reset)
node _T_19 = eq(_T_18, UInt<1>(0h0))
when _T_19 :
node _T_20 = eq(_T_17, UInt<1>(0h0))
when _T_20 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:324 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n") : printf_2
assert(clock, _T_17, UInt<1>(0h1), "") : assert_2
node _anonOut_a_bits_mask_T = mux(repeater.io.full, UInt<8>(0hff), anonIn.a.bits.mask)
connect anonOut.a.bits.mask, _anonOut_a_bits_mask_T
wire anonOut_a_bits_user_out : { }
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<21>(0h0)
connect _WIRE.bits.source, UInt<8>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<21>(0h0)
connect _WIRE_2.bits.source, UInt<8>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<21>(0h0)
connect _WIRE_6.bits.source, UInt<12>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<21>(0h0)
connect _WIRE_8.bits.source, UInt<12>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
connect _WIRE_9.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_10.bits.sink, UInt<1>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.valid, UInt<1>(0h0) | module TLFragmenter_TileResetSetter( // @[Fragmenter.scala:92:9]
input clock, // @[Fragmenter.scala:92:9]
input reset, // @[Fragmenter.scala:92:9]
output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [20:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [11:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [20:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [11:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_d_bits_data // @[LazyModuleImp.scala:107:25]
);
wire _repeater_io_full; // @[Fragmenter.scala:274:30]
wire _repeater_io_enq_ready; // @[Fragmenter.scala:274:30]
wire _repeater_io_deq_valid; // @[Fragmenter.scala:274:30]
wire [2:0] _repeater_io_deq_bits_opcode; // @[Fragmenter.scala:274:30]
wire [2:0] _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30]
wire [7:0] _repeater_io_deq_bits_source; // @[Fragmenter.scala:274:30]
wire [20:0] _repeater_io_deq_bits_address; // @[Fragmenter.scala:274:30]
wire [7:0] _repeater_io_deq_bits_mask; // @[Fragmenter.scala:274:30]
reg [2:0] acknum; // @[Fragmenter.scala:201:29]
reg [2:0] dOrig; // @[Fragmenter.scala:202:24]
reg dToggle; // @[Fragmenter.scala:203:30]
wire dFirst = acknum == 3'h0; // @[Fragmenter.scala:201:29, :205:29]
wire [5:0] _dsizeOH1_T = 6'h7 << auto_anon_out_d_bits_size; // @[package.scala:243:71]
wire [2:0] _GEN = ~(auto_anon_out_d_bits_source[2:0]); // @[package.scala:241:49]
wire [2:0] dFirst_size_hi = auto_anon_out_d_bits_source[2:0] & {1'h1, _GEN[2:1]}; // @[OneHot.scala:30:18]
wire [2:0] _dFirst_size_T_8 = {1'h0, dFirst_size_hi[2:1]} | ~(_dsizeOH1_T[2:0]) & {_GEN[0], _dsizeOH1_T[2:1]}; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [2:0] dFirst_size = {|dFirst_size_hi, |(_dFirst_size_T_8[2:1]), _dFirst_size_T_8[2] | _dFirst_size_T_8[0]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}]
wire drop = ~(auto_anon_out_d_bits_opcode[0]) & (|(auto_anon_out_d_bits_source[2:0])); // @[Fragmenter.scala:204:41, :206:30, :234:{20,30}]
wire anonOut_d_ready = auto_anon_in_d_ready | drop; // @[Fragmenter.scala:234:30, :235:35]
wire anonIn_d_valid = auto_anon_out_d_valid & ~drop; // @[Fragmenter.scala:234:30, :236:{36,39}]
wire [2:0] anonIn_d_bits_size = dFirst ? dFirst_size : dOrig; // @[OneHot.scala:32:10]
wire [12:0] _aOrigOH1_T = 13'h3F << _repeater_io_deq_bits_size; // @[package.scala:243:71]
reg [2:0] gennum; // @[Fragmenter.scala:303:29]
wire aFirst = gennum == 3'h0; // @[Fragmenter.scala:303:29, :304:29]
wire [2:0] aFragnum = aFirst ? ~(_aOrigOH1_T[5:3]) : gennum - 3'h1; // @[package.scala:243:{46,71,76}]
reg aToggle_r; // @[Fragmenter.scala:309:54] |
Generate the Verilog code corresponding to this FIRRTL code module Router :
input clock : Clock
input reset : Reset
output auto : { debug_out : { va_stall : UInt[4], sa_stall : UInt[4]}, egress_nodes_out_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, egress_nodes_out_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, flip ingress_nodes_in_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip ingress_nodes_in_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip ingress_nodes_in_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, source_nodes_out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}, flip dest_nodes_in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}}
wire destNodesIn : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}
invalidate destNodesIn.vc_free
invalidate destNodesIn.credit_return
invalidate destNodesIn.flit[0].bits.virt_channel_id
invalidate destNodesIn.flit[0].bits.flow.egress_node_id
invalidate destNodesIn.flit[0].bits.flow.egress_node
invalidate destNodesIn.flit[0].bits.flow.ingress_node_id
invalidate destNodesIn.flit[0].bits.flow.ingress_node
invalidate destNodesIn.flit[0].bits.flow.vnet_id
invalidate destNodesIn.flit[0].bits.payload
invalidate destNodesIn.flit[0].bits.tail
invalidate destNodesIn.flit[0].bits.head
invalidate destNodesIn.flit[0].valid
inst monitor of NoCMonitor
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.vc_free, destNodesIn.vc_free
connect monitor.io.in.credit_return, destNodesIn.credit_return
connect monitor.io.in.flit[0].bits.virt_channel_id, destNodesIn.flit[0].bits.virt_channel_id
connect monitor.io.in.flit[0].bits.flow.egress_node_id, destNodesIn.flit[0].bits.flow.egress_node_id
connect monitor.io.in.flit[0].bits.flow.egress_node, destNodesIn.flit[0].bits.flow.egress_node
connect monitor.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn.flit[0].bits.flow.ingress_node_id
connect monitor.io.in.flit[0].bits.flow.ingress_node, destNodesIn.flit[0].bits.flow.ingress_node
connect monitor.io.in.flit[0].bits.flow.vnet_id, destNodesIn.flit[0].bits.flow.vnet_id
connect monitor.io.in.flit[0].bits.payload, destNodesIn.flit[0].bits.payload
connect monitor.io.in.flit[0].bits.tail, destNodesIn.flit[0].bits.tail
connect monitor.io.in.flit[0].bits.head, destNodesIn.flit[0].bits.head
connect monitor.io.in.flit[0].valid, destNodesIn.flit[0].valid
wire sourceNodesOut : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}
invalidate sourceNodesOut.vc_free
invalidate sourceNodesOut.credit_return
invalidate sourceNodesOut.flit[0].bits.virt_channel_id
invalidate sourceNodesOut.flit[0].bits.flow.egress_node_id
invalidate sourceNodesOut.flit[0].bits.flow.egress_node
invalidate sourceNodesOut.flit[0].bits.flow.ingress_node_id
invalidate sourceNodesOut.flit[0].bits.flow.ingress_node
invalidate sourceNodesOut.flit[0].bits.flow.vnet_id
invalidate sourceNodesOut.flit[0].bits.payload
invalidate sourceNodesOut.flit[0].bits.tail
invalidate sourceNodesOut.flit[0].bits.head
invalidate sourceNodesOut.flit[0].valid
wire ingressNodesIn : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesIn.flit.bits.egress_id
invalidate ingressNodesIn.flit.bits.payload
invalidate ingressNodesIn.flit.bits.tail
invalidate ingressNodesIn.flit.bits.head
invalidate ingressNodesIn.flit.valid
invalidate ingressNodesIn.flit.ready
wire ingressNodesIn_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesIn_1.flit.bits.egress_id
invalidate ingressNodesIn_1.flit.bits.payload
invalidate ingressNodesIn_1.flit.bits.tail
invalidate ingressNodesIn_1.flit.bits.head
invalidate ingressNodesIn_1.flit.valid
invalidate ingressNodesIn_1.flit.ready
wire ingressNodesIn_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesIn_2.flit.bits.egress_id
invalidate ingressNodesIn_2.flit.bits.payload
invalidate ingressNodesIn_2.flit.bits.tail
invalidate ingressNodesIn_2.flit.bits.head
invalidate ingressNodesIn_2.flit.valid
invalidate ingressNodesIn_2.flit.ready
wire egressNodesOut : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesOut.flit.bits.ingress_id
invalidate egressNodesOut.flit.bits.payload
invalidate egressNodesOut.flit.bits.tail
invalidate egressNodesOut.flit.bits.head
invalidate egressNodesOut.flit.valid
invalidate egressNodesOut.flit.ready
wire egressNodesOut_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesOut_1.flit.bits.ingress_id
invalidate egressNodesOut_1.flit.bits.payload
invalidate egressNodesOut_1.flit.bits.tail
invalidate egressNodesOut_1.flit.bits.head
invalidate egressNodesOut_1.flit.valid
invalidate egressNodesOut_1.flit.ready
wire debugNodeOut : { va_stall : UInt[4], sa_stall : UInt[4]}
invalidate debugNodeOut.sa_stall[0]
invalidate debugNodeOut.sa_stall[1]
invalidate debugNodeOut.sa_stall[2]
invalidate debugNodeOut.sa_stall[3]
invalidate debugNodeOut.va_stall[0]
invalidate debugNodeOut.va_stall[1]
invalidate debugNodeOut.va_stall[2]
invalidate debugNodeOut.va_stall[3]
connect destNodesIn, auto.dest_nodes_in
connect auto.source_nodes_out, sourceNodesOut
connect ingressNodesIn, auto.ingress_nodes_in_0
connect ingressNodesIn_1, auto.ingress_nodes_in_1
connect ingressNodesIn_2, auto.ingress_nodes_in_2
connect auto.egress_nodes_out_0, egressNodesOut
connect auto.egress_nodes_out_1, egressNodesOut_1
connect auto.debug_out, debugNodeOut
inst input_unit_0_from_8 of InputUnit
connect input_unit_0_from_8.clock, clock
connect input_unit_0_from_8.reset, reset
inst ingress_unit_1_from_3 of IngressUnit
connect ingress_unit_1_from_3.clock, clock
connect ingress_unit_1_from_3.reset, reset
inst ingress_unit_2_from_4 of IngressUnit_1
connect ingress_unit_2_from_4.clock, clock
connect ingress_unit_2_from_4.reset, reset
inst ingress_unit_3_from_5 of IngressUnit_2
connect ingress_unit_3_from_5.clock, clock
connect ingress_unit_3_from_5.reset, reset
inst output_unit_0_to_1 of OutputUnit
connect output_unit_0_to_1.clock, clock
connect output_unit_0_to_1.reset, reset
inst egress_unit_1_to_2 of EgressUnit
connect egress_unit_1_to_2.clock, clock
connect egress_unit_1_to_2.reset, reset
inst egress_unit_2_to_3 of EgressUnit_1
connect egress_unit_2_to_3.clock, clock
connect egress_unit_2_to_3.reset, reset
inst switch of Switch
connect switch.clock, clock
connect switch.reset, reset
inst switch_allocator of SwitchAllocator
connect switch_allocator.clock, clock
connect switch_allocator.reset, reset
inst vc_allocator of RotatingSingleVCAllocator
connect vc_allocator.clock, clock
connect vc_allocator.reset, reset
inst route_computer of RouteComputer
connect route_computer.clock, clock
connect route_computer.reset, reset
node _fires_count_T = and(vc_allocator.io.req.`0`.ready, vc_allocator.io.req.`0`.valid)
node _fires_count_T_1 = and(vc_allocator.io.req.`1`.ready, vc_allocator.io.req.`1`.valid)
node _fires_count_T_2 = and(vc_allocator.io.req.`2`.ready, vc_allocator.io.req.`2`.valid)
node _fires_count_T_3 = and(vc_allocator.io.req.`3`.ready, vc_allocator.io.req.`3`.valid)
node _fires_count_T_4 = add(_fires_count_T, _fires_count_T_1)
node _fires_count_T_5 = bits(_fires_count_T_4, 1, 0)
node _fires_count_T_6 = add(_fires_count_T_2, _fires_count_T_3)
node _fires_count_T_7 = bits(_fires_count_T_6, 1, 0)
node _fires_count_T_8 = add(_fires_count_T_5, _fires_count_T_7)
node _fires_count_T_9 = bits(_fires_count_T_8, 2, 0)
wire fires_count : UInt
connect fires_count, _fires_count_T_9
connect input_unit_0_from_8.io.in, destNodesIn
connect ingress_unit_1_from_3.io.in, ingressNodesIn.flit
connect ingress_unit_2_from_4.io.in, ingressNodesIn_1.flit
connect ingress_unit_3_from_5.io.in, ingressNodesIn_2.flit
connect output_unit_0_to_1.io.out.vc_free, sourceNodesOut.vc_free
connect output_unit_0_to_1.io.out.credit_return, sourceNodesOut.credit_return
connect sourceNodesOut.flit, output_unit_0_to_1.io.out.flit
connect egressNodesOut.flit.bits, egress_unit_1_to_2.io.out.bits
connect egressNodesOut.flit.valid, egress_unit_1_to_2.io.out.valid
connect egress_unit_1_to_2.io.out.ready, egressNodesOut.flit.ready
connect egressNodesOut_1.flit.bits, egress_unit_2_to_3.io.out.bits
connect egressNodesOut_1.flit.valid, egress_unit_2_to_3.io.out.valid
connect egress_unit_2_to_3.io.out.ready, egressNodesOut_1.flit.ready
connect route_computer.io.req.`0`, input_unit_0_from_8.io.router_req
connect route_computer.io.req.`1`, ingress_unit_1_from_3.io.router_req
connect route_computer.io.req.`2`, ingress_unit_2_from_4.io.router_req
connect route_computer.io.req.`3`, ingress_unit_3_from_5.io.router_req
connect input_unit_0_from_8.io.router_resp, route_computer.io.resp.`0`
connect ingress_unit_1_from_3.io.router_resp, route_computer.io.resp.`1`
connect ingress_unit_2_from_4.io.router_resp, route_computer.io.resp.`2`
connect ingress_unit_3_from_5.io.router_resp, route_computer.io.resp.`3`
connect vc_allocator.io.req.`0`, input_unit_0_from_8.io.vcalloc_req
connect vc_allocator.io.req.`1`, ingress_unit_1_from_3.io.vcalloc_req
connect vc_allocator.io.req.`2`, ingress_unit_2_from_4.io.vcalloc_req
connect vc_allocator.io.req.`3`, ingress_unit_3_from_5.io.vcalloc_req
connect input_unit_0_from_8.io.vcalloc_resp, vc_allocator.io.resp.`0`
connect ingress_unit_1_from_3.io.vcalloc_resp, vc_allocator.io.resp.`1`
connect ingress_unit_2_from_4.io.vcalloc_resp, vc_allocator.io.resp.`2`
connect ingress_unit_3_from_5.io.vcalloc_resp, vc_allocator.io.resp.`3`
connect output_unit_0_to_1.io.allocs, vc_allocator.io.out_allocs.`0`
connect egress_unit_1_to_2.io.allocs, vc_allocator.io.out_allocs.`1`
connect egress_unit_2_to_3.io.allocs, vc_allocator.io.out_allocs.`2`
connect vc_allocator.io.channel_status.`0`[0].flow.egress_node_id, output_unit_0_to_1.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[0].flow.egress_node, output_unit_0_to_1.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node_id, output_unit_0_to_1.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node, output_unit_0_to_1.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[0].flow.vnet_id, output_unit_0_to_1.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[0].occupied, output_unit_0_to_1.io.channel_status[0].occupied
connect vc_allocator.io.channel_status.`0`[1].flow.egress_node_id, output_unit_0_to_1.io.channel_status[1].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[1].flow.egress_node, output_unit_0_to_1.io.channel_status[1].flow.egress_node
connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node_id, output_unit_0_to_1.io.channel_status[1].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node, output_unit_0_to_1.io.channel_status[1].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[1].flow.vnet_id, output_unit_0_to_1.io.channel_status[1].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[1].occupied, output_unit_0_to_1.io.channel_status[1].occupied
connect vc_allocator.io.channel_status.`0`[2].flow.egress_node_id, output_unit_0_to_1.io.channel_status[2].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[2].flow.egress_node, output_unit_0_to_1.io.channel_status[2].flow.egress_node
connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node_id, output_unit_0_to_1.io.channel_status[2].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node, output_unit_0_to_1.io.channel_status[2].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[2].flow.vnet_id, output_unit_0_to_1.io.channel_status[2].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[2].occupied, output_unit_0_to_1.io.channel_status[2].occupied
connect vc_allocator.io.channel_status.`0`[3].flow.egress_node_id, output_unit_0_to_1.io.channel_status[3].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[3].flow.egress_node, output_unit_0_to_1.io.channel_status[3].flow.egress_node
connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node_id, output_unit_0_to_1.io.channel_status[3].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node, output_unit_0_to_1.io.channel_status[3].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[3].flow.vnet_id, output_unit_0_to_1.io.channel_status[3].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[3].occupied, output_unit_0_to_1.io.channel_status[3].occupied
connect vc_allocator.io.channel_status.`0`[4].flow.egress_node_id, output_unit_0_to_1.io.channel_status[4].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[4].flow.egress_node, output_unit_0_to_1.io.channel_status[4].flow.egress_node
connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node_id, output_unit_0_to_1.io.channel_status[4].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node, output_unit_0_to_1.io.channel_status[4].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[4].flow.vnet_id, output_unit_0_to_1.io.channel_status[4].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[4].occupied, output_unit_0_to_1.io.channel_status[4].occupied
connect vc_allocator.io.channel_status.`0`[5].flow.egress_node_id, output_unit_0_to_1.io.channel_status[5].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[5].flow.egress_node, output_unit_0_to_1.io.channel_status[5].flow.egress_node
connect vc_allocator.io.channel_status.`0`[5].flow.ingress_node_id, output_unit_0_to_1.io.channel_status[5].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[5].flow.ingress_node, output_unit_0_to_1.io.channel_status[5].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[5].flow.vnet_id, output_unit_0_to_1.io.channel_status[5].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[5].occupied, output_unit_0_to_1.io.channel_status[5].occupied
connect vc_allocator.io.channel_status.`0`[6].flow.egress_node_id, output_unit_0_to_1.io.channel_status[6].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[6].flow.egress_node, output_unit_0_to_1.io.channel_status[6].flow.egress_node
connect vc_allocator.io.channel_status.`0`[6].flow.ingress_node_id, output_unit_0_to_1.io.channel_status[6].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[6].flow.ingress_node, output_unit_0_to_1.io.channel_status[6].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[6].flow.vnet_id, output_unit_0_to_1.io.channel_status[6].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[6].occupied, output_unit_0_to_1.io.channel_status[6].occupied
connect vc_allocator.io.channel_status.`0`[7].flow.egress_node_id, output_unit_0_to_1.io.channel_status[7].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[7].flow.egress_node, output_unit_0_to_1.io.channel_status[7].flow.egress_node
connect vc_allocator.io.channel_status.`0`[7].flow.ingress_node_id, output_unit_0_to_1.io.channel_status[7].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[7].flow.ingress_node, output_unit_0_to_1.io.channel_status[7].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[7].flow.vnet_id, output_unit_0_to_1.io.channel_status[7].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[7].occupied, output_unit_0_to_1.io.channel_status[7].occupied
connect vc_allocator.io.channel_status.`0`[8].flow.egress_node_id, output_unit_0_to_1.io.channel_status[8].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[8].flow.egress_node, output_unit_0_to_1.io.channel_status[8].flow.egress_node
connect vc_allocator.io.channel_status.`0`[8].flow.ingress_node_id, output_unit_0_to_1.io.channel_status[8].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[8].flow.ingress_node, output_unit_0_to_1.io.channel_status[8].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[8].flow.vnet_id, output_unit_0_to_1.io.channel_status[8].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[8].occupied, output_unit_0_to_1.io.channel_status[8].occupied
connect vc_allocator.io.channel_status.`0`[9].flow.egress_node_id, output_unit_0_to_1.io.channel_status[9].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[9].flow.egress_node, output_unit_0_to_1.io.channel_status[9].flow.egress_node
connect vc_allocator.io.channel_status.`0`[9].flow.ingress_node_id, output_unit_0_to_1.io.channel_status[9].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[9].flow.ingress_node, output_unit_0_to_1.io.channel_status[9].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[9].flow.vnet_id, output_unit_0_to_1.io.channel_status[9].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[9].occupied, output_unit_0_to_1.io.channel_status[9].occupied
connect vc_allocator.io.channel_status.`1`[0].flow.egress_node_id, egress_unit_1_to_2.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`1`[0].flow.egress_node, egress_unit_1_to_2.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node_id, egress_unit_1_to_2.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node, egress_unit_1_to_2.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`1`[0].flow.vnet_id, egress_unit_1_to_2.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`1`[0].occupied, egress_unit_1_to_2.io.channel_status[0].occupied
connect vc_allocator.io.channel_status.`2`[0].flow.egress_node_id, egress_unit_2_to_3.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`2`[0].flow.egress_node, egress_unit_2_to_3.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node_id, egress_unit_2_to_3.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node, egress_unit_2_to_3.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`2`[0].flow.vnet_id, egress_unit_2_to_3.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`2`[0].occupied, egress_unit_2_to_3.io.channel_status[0].occupied
connect input_unit_0_from_8.io.out_credit_available.`0`[0], output_unit_0_to_1.io.credit_available[0]
connect input_unit_0_from_8.io.out_credit_available.`0`[1], output_unit_0_to_1.io.credit_available[1]
connect input_unit_0_from_8.io.out_credit_available.`0`[2], output_unit_0_to_1.io.credit_available[2]
connect input_unit_0_from_8.io.out_credit_available.`0`[3], output_unit_0_to_1.io.credit_available[3]
connect input_unit_0_from_8.io.out_credit_available.`0`[4], output_unit_0_to_1.io.credit_available[4]
connect input_unit_0_from_8.io.out_credit_available.`0`[5], output_unit_0_to_1.io.credit_available[5]
connect input_unit_0_from_8.io.out_credit_available.`0`[6], output_unit_0_to_1.io.credit_available[6]
connect input_unit_0_from_8.io.out_credit_available.`0`[7], output_unit_0_to_1.io.credit_available[7]
connect input_unit_0_from_8.io.out_credit_available.`0`[8], output_unit_0_to_1.io.credit_available[8]
connect input_unit_0_from_8.io.out_credit_available.`0`[9], output_unit_0_to_1.io.credit_available[9]
connect input_unit_0_from_8.io.out_credit_available.`1`[0], egress_unit_1_to_2.io.credit_available[0]
connect input_unit_0_from_8.io.out_credit_available.`2`[0], egress_unit_2_to_3.io.credit_available[0]
connect ingress_unit_1_from_3.io.out_credit_available.`0`[0], output_unit_0_to_1.io.credit_available[0]
connect ingress_unit_1_from_3.io.out_credit_available.`0`[1], output_unit_0_to_1.io.credit_available[1]
connect ingress_unit_1_from_3.io.out_credit_available.`0`[2], output_unit_0_to_1.io.credit_available[2]
connect ingress_unit_1_from_3.io.out_credit_available.`0`[3], output_unit_0_to_1.io.credit_available[3]
connect ingress_unit_1_from_3.io.out_credit_available.`0`[4], output_unit_0_to_1.io.credit_available[4]
connect ingress_unit_1_from_3.io.out_credit_available.`0`[5], output_unit_0_to_1.io.credit_available[5]
connect ingress_unit_1_from_3.io.out_credit_available.`0`[6], output_unit_0_to_1.io.credit_available[6]
connect ingress_unit_1_from_3.io.out_credit_available.`0`[7], output_unit_0_to_1.io.credit_available[7]
connect ingress_unit_1_from_3.io.out_credit_available.`0`[8], output_unit_0_to_1.io.credit_available[8]
connect ingress_unit_1_from_3.io.out_credit_available.`0`[9], output_unit_0_to_1.io.credit_available[9]
connect ingress_unit_1_from_3.io.out_credit_available.`1`[0], egress_unit_1_to_2.io.credit_available[0]
connect ingress_unit_1_from_3.io.out_credit_available.`2`[0], egress_unit_2_to_3.io.credit_available[0]
connect ingress_unit_2_from_4.io.out_credit_available.`0`[0], output_unit_0_to_1.io.credit_available[0]
connect ingress_unit_2_from_4.io.out_credit_available.`0`[1], output_unit_0_to_1.io.credit_available[1]
connect ingress_unit_2_from_4.io.out_credit_available.`0`[2], output_unit_0_to_1.io.credit_available[2]
connect ingress_unit_2_from_4.io.out_credit_available.`0`[3], output_unit_0_to_1.io.credit_available[3]
connect ingress_unit_2_from_4.io.out_credit_available.`0`[4], output_unit_0_to_1.io.credit_available[4]
connect ingress_unit_2_from_4.io.out_credit_available.`0`[5], output_unit_0_to_1.io.credit_available[5]
connect ingress_unit_2_from_4.io.out_credit_available.`0`[6], output_unit_0_to_1.io.credit_available[6]
connect ingress_unit_2_from_4.io.out_credit_available.`0`[7], output_unit_0_to_1.io.credit_available[7]
connect ingress_unit_2_from_4.io.out_credit_available.`0`[8], output_unit_0_to_1.io.credit_available[8]
connect ingress_unit_2_from_4.io.out_credit_available.`0`[9], output_unit_0_to_1.io.credit_available[9]
connect ingress_unit_2_from_4.io.out_credit_available.`1`[0], egress_unit_1_to_2.io.credit_available[0]
connect ingress_unit_2_from_4.io.out_credit_available.`2`[0], egress_unit_2_to_3.io.credit_available[0]
connect ingress_unit_3_from_5.io.out_credit_available.`0`[0], output_unit_0_to_1.io.credit_available[0]
connect ingress_unit_3_from_5.io.out_credit_available.`0`[1], output_unit_0_to_1.io.credit_available[1]
connect ingress_unit_3_from_5.io.out_credit_available.`0`[2], output_unit_0_to_1.io.credit_available[2]
connect ingress_unit_3_from_5.io.out_credit_available.`0`[3], output_unit_0_to_1.io.credit_available[3]
connect ingress_unit_3_from_5.io.out_credit_available.`0`[4], output_unit_0_to_1.io.credit_available[4]
connect ingress_unit_3_from_5.io.out_credit_available.`0`[5], output_unit_0_to_1.io.credit_available[5]
connect ingress_unit_3_from_5.io.out_credit_available.`0`[6], output_unit_0_to_1.io.credit_available[6]
connect ingress_unit_3_from_5.io.out_credit_available.`0`[7], output_unit_0_to_1.io.credit_available[7]
connect ingress_unit_3_from_5.io.out_credit_available.`0`[8], output_unit_0_to_1.io.credit_available[8]
connect ingress_unit_3_from_5.io.out_credit_available.`0`[9], output_unit_0_to_1.io.credit_available[9]
connect ingress_unit_3_from_5.io.out_credit_available.`1`[0], egress_unit_1_to_2.io.credit_available[0]
connect ingress_unit_3_from_5.io.out_credit_available.`2`[0], egress_unit_2_to_3.io.credit_available[0]
connect switch_allocator.io.req.`0`[0], input_unit_0_from_8.io.salloc_req[0]
connect switch_allocator.io.req.`1`[0], ingress_unit_1_from_3.io.salloc_req[0]
connect switch_allocator.io.req.`2`[0], ingress_unit_2_from_4.io.salloc_req[0]
connect switch_allocator.io.req.`3`[0], ingress_unit_3_from_5.io.salloc_req[0]
connect output_unit_0_to_1.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`0`[0].tail
connect output_unit_0_to_1.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`0`[0].alloc
connect output_unit_0_to_1.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`0`[1].tail
connect output_unit_0_to_1.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`0`[1].alloc
connect output_unit_0_to_1.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`0`[2].tail
connect output_unit_0_to_1.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`0`[2].alloc
connect output_unit_0_to_1.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`0`[3].tail
connect output_unit_0_to_1.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`0`[3].alloc
connect output_unit_0_to_1.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`0`[4].tail
connect output_unit_0_to_1.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`0`[4].alloc
connect output_unit_0_to_1.io.credit_alloc[5].tail, switch_allocator.io.credit_alloc.`0`[5].tail
connect output_unit_0_to_1.io.credit_alloc[5].alloc, switch_allocator.io.credit_alloc.`0`[5].alloc
connect output_unit_0_to_1.io.credit_alloc[6].tail, switch_allocator.io.credit_alloc.`0`[6].tail
connect output_unit_0_to_1.io.credit_alloc[6].alloc, switch_allocator.io.credit_alloc.`0`[6].alloc
connect output_unit_0_to_1.io.credit_alloc[7].tail, switch_allocator.io.credit_alloc.`0`[7].tail
connect output_unit_0_to_1.io.credit_alloc[7].alloc, switch_allocator.io.credit_alloc.`0`[7].alloc
connect output_unit_0_to_1.io.credit_alloc[8].tail, switch_allocator.io.credit_alloc.`0`[8].tail
connect output_unit_0_to_1.io.credit_alloc[8].alloc, switch_allocator.io.credit_alloc.`0`[8].alloc
connect output_unit_0_to_1.io.credit_alloc[9].tail, switch_allocator.io.credit_alloc.`0`[9].tail
connect output_unit_0_to_1.io.credit_alloc[9].alloc, switch_allocator.io.credit_alloc.`0`[9].alloc
connect egress_unit_1_to_2.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`1`[0].tail
connect egress_unit_1_to_2.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`1`[0].alloc
connect egress_unit_2_to_3.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`2`[0].tail
connect egress_unit_2_to_3.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`2`[0].alloc
connect switch.io.in.`0`[0], input_unit_0_from_8.io.out[0]
connect switch.io.in.`1`[0], ingress_unit_1_from_3.io.out[0]
connect switch.io.in.`2`[0], ingress_unit_2_from_4.io.out[0]
connect switch.io.in.`3`[0], ingress_unit_3_from_5.io.out[0]
connect output_unit_0_to_1.io.in, switch.io.out.`0`
connect egress_unit_1_to_2.io.in, switch.io.out.`1`
connect egress_unit_2_to_3.io.in, switch.io.out.`2`
reg REG : { `2` : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `1` : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}, clock
connect REG, switch_allocator.io.switch_sel
connect switch.io.sel.`0`[0].`0`[0], REG.`0`[0].`0`[0]
connect switch.io.sel.`0`[0].`1`[0], REG.`0`[0].`1`[0]
connect switch.io.sel.`0`[0].`2`[0], REG.`0`[0].`2`[0]
connect switch.io.sel.`0`[0].`3`[0], REG.`0`[0].`3`[0]
connect switch.io.sel.`1`[0].`0`[0], REG.`1`[0].`0`[0]
connect switch.io.sel.`1`[0].`1`[0], REG.`1`[0].`1`[0]
connect switch.io.sel.`1`[0].`2`[0], REG.`1`[0].`2`[0]
connect switch.io.sel.`1`[0].`3`[0], REG.`1`[0].`3`[0]
connect switch.io.sel.`2`[0].`0`[0], REG.`2`[0].`0`[0]
connect switch.io.sel.`2`[0].`1`[0], REG.`2`[0].`1`[0]
connect switch.io.sel.`2`[0].`2`[0], REG.`2`[0].`2`[0]
connect switch.io.sel.`2`[0].`3`[0], REG.`2`[0].`3`[0]
connect input_unit_0_from_8.io.block, UInt<1>(0h0)
connect ingress_unit_1_from_3.io.block, UInt<1>(0h0)
connect ingress_unit_2_from_4.io.block, UInt<1>(0h0)
connect ingress_unit_3_from_5.io.block, UInt<1>(0h0)
connect debugNodeOut.va_stall[0], input_unit_0_from_8.io.debug.va_stall
connect debugNodeOut.va_stall[1], ingress_unit_1_from_3.io.debug.va_stall
connect debugNodeOut.va_stall[2], ingress_unit_2_from_4.io.debug.va_stall
connect debugNodeOut.va_stall[3], ingress_unit_3_from_5.io.debug.va_stall
connect debugNodeOut.sa_stall[0], input_unit_0_from_8.io.debug.sa_stall
connect debugNodeOut.sa_stall[1], ingress_unit_1_from_3.io.debug.sa_stall
connect debugNodeOut.sa_stall[2], ingress_unit_2_from_4.io.debug.sa_stall
connect debugNodeOut.sa_stall[3], ingress_unit_3_from_5.io.debug.sa_stall
regreset debug_tsc : UInt<64>, clock, reset, UInt<64>(0h0)
node _debug_tsc_T = add(debug_tsc, UInt<1>(0h1))
node _debug_tsc_T_1 = tail(_debug_tsc_T, 1)
connect debug_tsc, _debug_tsc_T_1
regreset debug_sample : UInt<64>, clock, reset, UInt<64>(0h0)
node _debug_sample_T = add(debug_sample, UInt<1>(0h1))
node _debug_sample_T_1 = tail(_debug_sample_T, 1)
connect debug_sample, _debug_sample_T_1
inst plusarg_reader of plusarg_reader_10
node _T = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_1 = tail(_T, 1)
node _T_2 = eq(debug_sample, _T_1)
when _T_2 :
connect debug_sample, UInt<1>(0h0)
regreset util_ctr : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T = add(util_ctr, destNodesIn.flit[0].valid)
node _util_ctr_T_1 = tail(_util_ctr_T, 1)
connect util_ctr, _util_ctr_T_1
node _fired_T = or(fired, destNodesIn.flit[0].valid)
connect fired, _fired_T
node _T_3 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_4 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_5 = tail(_T_4, 1)
node _T_6 = eq(debug_sample, _T_5)
node _T_7 = and(_T_3, _T_6)
node _T_8 = and(_T_7, fired)
when _T_8 :
node _T_9 = asUInt(reset)
node _T_10 = eq(_T_9, UInt<1>(0h0))
when _T_10 :
printf(clock, UInt<1>(0h1), "nocsample %d 8 0 %d\n", debug_tsc, util_ctr) : printf
connect fired, destNodesIn.flit[0].valid
node _T_11 = and(ingressNodesIn.flit.ready, ingressNodesIn.flit.valid)
regreset util_ctr_1 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_2 = add(util_ctr_1, _T_11)
node _util_ctr_T_3 = tail(_util_ctr_T_2, 1)
connect util_ctr_1, _util_ctr_T_3
node _fired_T_1 = or(fired_1, _T_11)
connect fired_1, _fired_T_1
node _T_12 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_13 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_14 = tail(_T_13, 1)
node _T_15 = eq(debug_sample, _T_14)
node _T_16 = and(_T_12, _T_15)
node _T_17 = and(_T_16, fired_1)
when _T_17 :
node _T_18 = asUInt(reset)
node _T_19 = eq(_T_18, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "nocsample %d i3 0 %d\n", debug_tsc, util_ctr_1) : printf_1
connect fired_1, _T_11
node _T_20 = and(ingressNodesIn_1.flit.ready, ingressNodesIn_1.flit.valid)
regreset util_ctr_2 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_4 = add(util_ctr_2, _T_20)
node _util_ctr_T_5 = tail(_util_ctr_T_4, 1)
connect util_ctr_2, _util_ctr_T_5
node _fired_T_2 = or(fired_2, _T_20)
connect fired_2, _fired_T_2
node _T_21 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_22 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_23 = tail(_T_22, 1)
node _T_24 = eq(debug_sample, _T_23)
node _T_25 = and(_T_21, _T_24)
node _T_26 = and(_T_25, fired_2)
when _T_26 :
node _T_27 = asUInt(reset)
node _T_28 = eq(_T_27, UInt<1>(0h0))
when _T_28 :
printf(clock, UInt<1>(0h1), "nocsample %d i4 0 %d\n", debug_tsc, util_ctr_2) : printf_2
connect fired_2, _T_20
node _T_29 = and(ingressNodesIn_2.flit.ready, ingressNodesIn_2.flit.valid)
regreset util_ctr_3 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_3 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_6 = add(util_ctr_3, _T_29)
node _util_ctr_T_7 = tail(_util_ctr_T_6, 1)
connect util_ctr_3, _util_ctr_T_7
node _fired_T_3 = or(fired_3, _T_29)
connect fired_3, _fired_T_3
node _T_30 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_31 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_32 = tail(_T_31, 1)
node _T_33 = eq(debug_sample, _T_32)
node _T_34 = and(_T_30, _T_33)
node _T_35 = and(_T_34, fired_3)
when _T_35 :
node _T_36 = asUInt(reset)
node _T_37 = eq(_T_36, UInt<1>(0h0))
when _T_37 :
printf(clock, UInt<1>(0h1), "nocsample %d i5 0 %d\n", debug_tsc, util_ctr_3) : printf_3
connect fired_3, _T_29
node _T_38 = and(egressNodesOut.flit.ready, egressNodesOut.flit.valid)
regreset util_ctr_4 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_4 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_8 = add(util_ctr_4, _T_38)
node _util_ctr_T_9 = tail(_util_ctr_T_8, 1)
connect util_ctr_4, _util_ctr_T_9
node _fired_T_4 = or(fired_4, _T_38)
connect fired_4, _fired_T_4
node _T_39 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_40 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_41 = tail(_T_40, 1)
node _T_42 = eq(debug_sample, _T_41)
node _T_43 = and(_T_39, _T_42)
node _T_44 = and(_T_43, fired_4)
when _T_44 :
node _T_45 = asUInt(reset)
node _T_46 = eq(_T_45, UInt<1>(0h0))
when _T_46 :
printf(clock, UInt<1>(0h1), "nocsample %d 0 e2 %d\n", debug_tsc, util_ctr_4) : printf_4
connect fired_4, _T_38
node _T_47 = and(egressNodesOut_1.flit.ready, egressNodesOut_1.flit.valid)
regreset util_ctr_5 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_5 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_10 = add(util_ctr_5, _T_47)
node _util_ctr_T_11 = tail(_util_ctr_T_10, 1)
connect util_ctr_5, _util_ctr_T_11
node _fired_T_5 = or(fired_5, _T_47)
connect fired_5, _fired_T_5
node _T_48 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_49 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_50 = tail(_T_49, 1)
node _T_51 = eq(debug_sample, _T_50)
node _T_52 = and(_T_48, _T_51)
node _T_53 = and(_T_52, fired_5)
when _T_53 :
node _T_54 = asUInt(reset)
node _T_55 = eq(_T_54, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "nocsample %d 0 e3 %d\n", debug_tsc, util_ctr_5) : printf_5
connect fired_5, _T_47 | module Router( // @[Router.scala:89:25]
input clock, // @[Router.scala:89:25]
input reset, // @[Router.scala:89:25]
output [3:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_debug_out_va_stall_3, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_debug_out_sa_stall_3, // @[LazyModuleImp.scala:107:25]
input auto_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_egress_nodes_out_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_ingress_nodes_in_2_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_2_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_2_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_ingress_nodes_in_2_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_ingress_nodes_in_2_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_dest_nodes_in_vc_free // @[LazyModuleImp.scala:107:25]
);
wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire _route_computer_io_resp_0_vc_sel_0_2; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_3; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_6; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_7; // @[Router.scala:136:32]
wire _vc_allocator_io_req_3_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_3_vc_sel_2_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_3_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_3_vc_sel_0_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_3_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_3_vc_sel_0_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_3_vc_sel_0_3; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_3_vc_sel_0_4; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_3_vc_sel_0_5; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_3_vc_sel_0_6; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_3_vc_sel_0_7; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_3_vc_sel_0_8; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_3_vc_sel_0_9; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_2_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_3; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_4; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_5; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_6; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_7; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_8; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_9; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_2_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_3; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_4; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_5; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_6; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_7; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_8; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_9; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_2_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_0_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_0_3; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_0_6; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_0_7; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_2_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_2_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_3_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_5_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_6_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_7_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_9_alloc; // @[Router.scala:133:30]
wire _switch_allocator_io_req_3_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_2_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_2_0_tail; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_0_tail; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_2_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_3_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_5_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_6_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_7_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_9_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_3_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_3_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_3_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34]
wire _switch_io_out_2_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_1_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_0_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _egress_unit_2_to_3_io_credit_available_0; // @[Router.scala:125:13]
wire _egress_unit_2_to_3_io_channel_status_0_occupied; // @[Router.scala:125:13]
wire _egress_unit_2_to_3_io_out_valid; // @[Router.scala:125:13]
wire _egress_unit_1_to_2_io_credit_available_0; // @[Router.scala:125:13]
wire _egress_unit_1_to_2_io_channel_status_0_occupied; // @[Router.scala:125:13]
wire _egress_unit_1_to_2_io_out_valid; // @[Router.scala:125:13]
wire _output_unit_0_to_1_io_credit_available_1; // @[Router.scala:122:13]
wire _output_unit_0_to_1_io_credit_available_2; // @[Router.scala:122:13]
wire _output_unit_0_to_1_io_credit_available_3; // @[Router.scala:122:13]
wire _output_unit_0_to_1_io_credit_available_5; // @[Router.scala:122:13]
wire _output_unit_0_to_1_io_credit_available_6; // @[Router.scala:122:13]
wire _output_unit_0_to_1_io_credit_available_7; // @[Router.scala:122:13]
wire _output_unit_0_to_1_io_credit_available_9; // @[Router.scala:122:13]
wire _output_unit_0_to_1_io_channel_status_1_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_1_io_channel_status_2_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_1_io_channel_status_3_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_1_io_channel_status_5_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_1_io_channel_status_6_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_1_io_channel_status_7_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_1_io_channel_status_9_occupied; // @[Router.scala:122:13]
wire _ingress_unit_3_from_5_io_vcalloc_req_valid; // @[Router.scala:116:13]
wire _ingress_unit_3_from_5_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_3_from_5_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_3_from_5_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_3_from_5_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_3_from_5_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_3_from_5_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_3_from_5_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_3_from_5_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:116:13]
wire _ingress_unit_3_from_5_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:116:13]
wire _ingress_unit_3_from_5_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:116:13]
wire _ingress_unit_3_from_5_io_vcalloc_req_bits_vc_sel_0_8; // @[Router.scala:116:13]
wire _ingress_unit_3_from_5_io_vcalloc_req_bits_vc_sel_0_9; // @[Router.scala:116:13]
wire _ingress_unit_3_from_5_io_salloc_req_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_3_from_5_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_3_from_5_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_3_from_5_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_3_from_5_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_3_from_5_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_3_from_5_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_3_from_5_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_3_from_5_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:116:13]
wire _ingress_unit_3_from_5_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:116:13]
wire _ingress_unit_3_from_5_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:116:13]
wire _ingress_unit_3_from_5_io_salloc_req_0_bits_vc_sel_0_8; // @[Router.scala:116:13]
wire _ingress_unit_3_from_5_io_salloc_req_0_bits_vc_sel_0_9; // @[Router.scala:116:13]
wire _ingress_unit_3_from_5_io_salloc_req_0_bits_tail; // @[Router.scala:116:13]
wire _ingress_unit_3_from_5_io_out_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_3_from_5_io_out_0_bits_flit_head; // @[Router.scala:116:13]
wire _ingress_unit_3_from_5_io_out_0_bits_flit_tail; // @[Router.scala:116:13]
wire [72:0] _ingress_unit_3_from_5_io_out_0_bits_flit_payload; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_3_from_5_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_3_from_5_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_3_from_5_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_3_from_5_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_3_from_5_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_3_from_5_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13]
wire _ingress_unit_3_from_5_io_in_ready; // @[Router.scala:116:13]
wire _ingress_unit_2_from_4_io_vcalloc_req_valid; // @[Router.scala:116:13]
wire _ingress_unit_2_from_4_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_4_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_4_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_4_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_2_from_4_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_2_from_4_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_2_from_4_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_2_from_4_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:116:13]
wire _ingress_unit_2_from_4_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:116:13]
wire _ingress_unit_2_from_4_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:116:13]
wire _ingress_unit_2_from_4_io_vcalloc_req_bits_vc_sel_0_8; // @[Router.scala:116:13]
wire _ingress_unit_2_from_4_io_vcalloc_req_bits_vc_sel_0_9; // @[Router.scala:116:13]
wire _ingress_unit_2_from_4_io_salloc_req_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_2_from_4_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_4_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_4_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_4_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_2_from_4_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_2_from_4_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_2_from_4_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_2_from_4_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:116:13]
wire _ingress_unit_2_from_4_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:116:13]
wire _ingress_unit_2_from_4_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:116:13]
wire _ingress_unit_2_from_4_io_salloc_req_0_bits_vc_sel_0_8; // @[Router.scala:116:13]
wire _ingress_unit_2_from_4_io_salloc_req_0_bits_vc_sel_0_9; // @[Router.scala:116:13]
wire _ingress_unit_2_from_4_io_salloc_req_0_bits_tail; // @[Router.scala:116:13]
wire _ingress_unit_2_from_4_io_out_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_2_from_4_io_out_0_bits_flit_head; // @[Router.scala:116:13]
wire _ingress_unit_2_from_4_io_out_0_bits_flit_tail; // @[Router.scala:116:13]
wire [72:0] _ingress_unit_2_from_4_io_out_0_bits_flit_payload; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_2_from_4_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_2_from_4_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_2_from_4_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_2_from_4_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_2_from_4_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_2_from_4_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13]
wire _ingress_unit_2_from_4_io_in_ready; // @[Router.scala:116:13]
wire _ingress_unit_1_from_3_io_vcalloc_req_valid; // @[Router.scala:116:13]
wire _ingress_unit_1_from_3_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_3_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_3_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_3_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_1_from_3_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_1_from_3_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_1_from_3_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_1_from_3_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:116:13]
wire _ingress_unit_1_from_3_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:116:13]
wire _ingress_unit_1_from_3_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:116:13]
wire _ingress_unit_1_from_3_io_vcalloc_req_bits_vc_sel_0_8; // @[Router.scala:116:13]
wire _ingress_unit_1_from_3_io_vcalloc_req_bits_vc_sel_0_9; // @[Router.scala:116:13]
wire _ingress_unit_1_from_3_io_salloc_req_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_1_from_3_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_3_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_3_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_3_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_1_from_3_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_1_from_3_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_1_from_3_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_1_from_3_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:116:13]
wire _ingress_unit_1_from_3_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:116:13]
wire _ingress_unit_1_from_3_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:116:13]
wire _ingress_unit_1_from_3_io_salloc_req_0_bits_vc_sel_0_8; // @[Router.scala:116:13]
wire _ingress_unit_1_from_3_io_salloc_req_0_bits_vc_sel_0_9; // @[Router.scala:116:13]
wire _ingress_unit_1_from_3_io_salloc_req_0_bits_tail; // @[Router.scala:116:13]
wire _ingress_unit_1_from_3_io_out_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_1_from_3_io_out_0_bits_flit_head; // @[Router.scala:116:13]
wire _ingress_unit_1_from_3_io_out_0_bits_flit_tail; // @[Router.scala:116:13]
wire [72:0] _ingress_unit_1_from_3_io_out_0_bits_flit_payload; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_1_from_3_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_1_from_3_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_1_from_3_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_1_from_3_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_1_from_3_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_1_from_3_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13]
wire _ingress_unit_1_from_3_io_in_ready; // @[Router.scala:116:13]
wire [3:0] _input_unit_0_from_8_io_router_req_bits_src_virt_id; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_8_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_8_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_8_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_8_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_8_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_vcalloc_req_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_salloc_req_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_salloc_req_0_bits_vc_sel_0_8; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_salloc_req_0_bits_vc_sel_0_9; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_salloc_req_0_bits_tail; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_out_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_out_0_bits_flit_head; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_out_0_bits_flit_tail; // @[Router.scala:112:13]
wire [72:0] _input_unit_0_from_8_io_out_0_bits_flit_payload; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_8_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_8_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_8_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_8_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_8_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_8_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13]
wire [2:0] fires_count = {1'h0, {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_8_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _ingress_unit_1_from_3_io_vcalloc_req_valid}} + {1'h0, {1'h0, _vc_allocator_io_req_2_ready & _ingress_unit_2_from_4_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_3_ready & _ingress_unit_3_from_5_io_vcalloc_req_valid}}; // @[Decoupled.scala:51:35]
reg REG_2_0_3_0; // @[Router.scala:178:14]
reg REG_2_0_2_0; // @[Router.scala:178:14]
reg REG_2_0_1_0; // @[Router.scala:178:14]
reg REG_2_0_0_0; // @[Router.scala:178:14]
reg REG_1_0_3_0; // @[Router.scala:178:14]
reg REG_1_0_2_0; // @[Router.scala:178:14]
reg REG_1_0_1_0; // @[Router.scala:178:14]
reg REG_1_0_0_0; // @[Router.scala:178:14]
reg REG_0_0_3_0; // @[Router.scala:178:14]
reg REG_0_0_2_0; // @[Router.scala:178:14]
reg REG_0_0_1_0; // @[Router.scala:178:14]
reg REG_0_0_0_0; // @[Router.scala:178:14]
reg [63:0] debug_tsc; // @[Router.scala:195:28]
reg [63:0] debug_sample; // @[Router.scala:197:31]
wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11]
reg [63:0] util_ctr; // @[Router.scala:203:29]
reg fired; // @[Router.scala:204:26]
wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11]
wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_1; // @[Router.scala:203:29]
reg fired_1; // @[Router.scala:204:26]
wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_2; // @[Router.scala:203:29]
reg fired_2; // @[Router.scala:204:26]
wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_3; // @[Router.scala:203:29]
reg fired_3; // @[Router.scala:204:26]
wire _GEN_4 = _GEN_0 & fired_3; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_4; // @[Router.scala:203:29]
reg fired_4; // @[Router.scala:204:26]
wire _GEN_5 = _GEN_0 & fired_4; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_5; // @[Router.scala:203:29]
reg fired_5; // @[Router.scala:204:26]
wire _GEN_6 = _GEN_0 & fired_5; // @[Router.scala:204:26, :207:{33,71}] |
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_65 :
input clock : Clock
input reset : Reset
output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}}
regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff)
reg value_reg : { symbol : UInt<10>}, clock
connect io.output_prev.key, key_reg
connect io.output_prev.value, value_reg
connect io.output_nxt.key, key_reg
connect io.output_nxt.value, value_reg
connect io.cur_output_keyval.key, key_reg
connect io.cur_output_keyval.value, value_reg
when io.cmd.valid :
node _T = eq(UInt<1>(0h0), io.cmd.bits)
when _T :
connect key_reg, io.input_nxt.key
connect value_reg, io.input_nxt.value
else :
node _T_1 = eq(UInt<1>(0h1), io.cmd.bits)
when _T_1 :
when io.insert_here :
connect key_reg, io.cur_input_keyval.key
connect value_reg, io.cur_input_keyval.value
else :
node _T_2 = geq(key_reg, io.cur_input_keyval.key)
when _T_2 :
connect key_reg, io.input_prev.key
connect value_reg, io.input_prev.value
else :
skip | module PriorityQueueStage_65( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_140 :
input clock : Clock
input reset : Reset
output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}}
regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff)
reg value_reg : { symbol : UInt<10>}, clock
connect io.output_prev.key, key_reg
connect io.output_prev.value, value_reg
connect io.output_nxt.key, key_reg
connect io.output_nxt.value, value_reg
connect io.cur_output_keyval.key, key_reg
connect io.cur_output_keyval.value, value_reg
when io.cmd.valid :
node _T = eq(UInt<1>(0h0), io.cmd.bits)
when _T :
connect key_reg, io.input_nxt.key
connect value_reg, io.input_nxt.value
else :
node _T_1 = eq(UInt<1>(0h1), io.cmd.bits)
when _T_1 :
when io.insert_here :
connect key_reg, io.cur_input_keyval.key
connect value_reg, io.cur_input_keyval.value
else :
node _T_2 = geq(key_reg, io.cur_input_keyval.key)
when _T_2 :
connect key_reg, io.input_prev.key
connect value_reg, io.input_prev.value
else :
skip | module PriorityQueueStage_140( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_23 :
input clock : Clock
input reset : Reset
output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}}
regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff)
reg value_reg : { symbol : UInt<10>}, clock
connect io.output_prev.key, key_reg
connect io.output_prev.value, value_reg
connect io.output_nxt.key, key_reg
connect io.output_nxt.value, value_reg
connect io.cur_output_keyval.key, key_reg
connect io.cur_output_keyval.value, value_reg
when io.cmd.valid :
node _T = eq(UInt<1>(0h0), io.cmd.bits)
when _T :
connect key_reg, io.input_nxt.key
connect value_reg, io.input_nxt.value
else :
node _T_1 = eq(UInt<1>(0h1), io.cmd.bits)
when _T_1 :
when io.insert_here :
connect key_reg, io.cur_input_keyval.key
connect value_reg, io.cur_input_keyval.value
else :
node _T_2 = geq(key_reg, io.cur_input_keyval.key)
when _T_2 :
connect key_reg, io.input_prev.key
connect value_reg, io.input_prev.value
else :
skip | module PriorityQueueStage_23( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_2 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h20))
wire _source_ok_WIRE : UInt<1>[7]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_25
connect _source_ok_WIRE[6], _source_ok_T_26
node _source_ok_T_27 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_28 = or(_source_ok_T_27, _source_ok_WIRE[2])
node _source_ok_T_29 = or(_source_ok_T_28, _source_ok_WIRE[3])
node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[4])
node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[5])
node source_ok = or(_source_ok_T_31, _source_ok_WIRE[6])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2))
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_lo = cat(mask_acc_1, mask_acc)
node mask_hi = cat(mask_acc_3, mask_acc_2)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_67 = cvt(_T_66)
node _T_68 = and(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = asSInt(_T_68)
node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0)))
node _T_71 = or(_T_65, _T_70)
node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_73 = eq(_T_72, UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<1>(0h0)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = or(_T_73, _T_78)
node _T_80 = and(_T_11, _T_24)
node _T_81 = and(_T_80, _T_37)
node _T_82 = and(_T_81, _T_50)
node _T_83 = and(_T_82, _T_63)
node _T_84 = and(_T_83, _T_71)
node _T_85 = and(_T_84, _T_79)
node _T_86 = asUInt(reset)
node _T_87 = eq(_T_86, UInt<1>(0h0))
when _T_87 :
node _T_88 = eq(_T_85, UInt<1>(0h0))
when _T_88 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_85, UInt<1>(0h1), "") : assert_1
node _T_89 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_89 :
node _T_90 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_91 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_92 = and(_T_90, _T_91)
node _T_93 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_94 = shr(io.in.a.bits.source, 2)
node _T_95 = eq(_T_94, UInt<1>(0h0))
node _T_96 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_97 = and(_T_95, _T_96)
node _T_98 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_99 = and(_T_97, _T_98)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_100 = shr(io.in.a.bits.source, 2)
node _T_101 = eq(_T_100, UInt<1>(0h1))
node _T_102 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_103 = and(_T_101, _T_102)
node _T_104 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_105 = and(_T_103, _T_104)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_106 = shr(io.in.a.bits.source, 2)
node _T_107 = eq(_T_106, UInt<2>(0h2))
node _T_108 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_109 = and(_T_107, _T_108)
node _T_110 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_111 = and(_T_109, _T_110)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_112 = shr(io.in.a.bits.source, 2)
node _T_113 = eq(_T_112, UInt<2>(0h3))
node _T_114 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_115 = and(_T_113, _T_114)
node _T_116 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_117 = and(_T_115, _T_116)
node _T_118 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_119 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_120 = or(_T_93, _T_99)
node _T_121 = or(_T_120, _T_105)
node _T_122 = or(_T_121, _T_111)
node _T_123 = or(_T_122, _T_117)
node _T_124 = or(_T_123, _T_118)
node _T_125 = or(_T_124, _T_119)
node _T_126 = and(_T_92, _T_125)
node _T_127 = or(UInt<1>(0h0), _T_126)
node _T_128 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_129 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_130 = cvt(_T_129)
node _T_131 = and(_T_130, asSInt(UInt<14>(0h2000)))
node _T_132 = asSInt(_T_131)
node _T_133 = eq(_T_132, asSInt(UInt<1>(0h0)))
node _T_134 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_135 = cvt(_T_134)
node _T_136 = and(_T_135, asSInt(UInt<13>(0h1000)))
node _T_137 = asSInt(_T_136)
node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0)))
node _T_139 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_140 = cvt(_T_139)
node _T_141 = and(_T_140, asSInt(UInt<17>(0h10000)))
node _T_142 = asSInt(_T_141)
node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0)))
node _T_144 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_145 = cvt(_T_144)
node _T_146 = and(_T_145, asSInt(UInt<18>(0h2f000)))
node _T_147 = asSInt(_T_146)
node _T_148 = eq(_T_147, asSInt(UInt<1>(0h0)))
node _T_149 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_150 = cvt(_T_149)
node _T_151 = and(_T_150, asSInt(UInt<17>(0h10000)))
node _T_152 = asSInt(_T_151)
node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0)))
node _T_154 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_155 = cvt(_T_154)
node _T_156 = and(_T_155, asSInt(UInt<13>(0h1000)))
node _T_157 = asSInt(_T_156)
node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0)))
node _T_159 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_160 = cvt(_T_159)
node _T_161 = and(_T_160, asSInt(UInt<27>(0h4000000)))
node _T_162 = asSInt(_T_161)
node _T_163 = eq(_T_162, asSInt(UInt<1>(0h0)))
node _T_164 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_165 = cvt(_T_164)
node _T_166 = and(_T_165, asSInt(UInt<13>(0h1000)))
node _T_167 = asSInt(_T_166)
node _T_168 = eq(_T_167, asSInt(UInt<1>(0h0)))
node _T_169 = or(_T_133, _T_138)
node _T_170 = or(_T_169, _T_143)
node _T_171 = or(_T_170, _T_148)
node _T_172 = or(_T_171, _T_153)
node _T_173 = or(_T_172, _T_158)
node _T_174 = or(_T_173, _T_163)
node _T_175 = or(_T_174, _T_168)
node _T_176 = and(_T_128, _T_175)
node _T_177 = or(UInt<1>(0h0), _T_176)
node _T_178 = and(_T_127, _T_177)
node _T_179 = asUInt(reset)
node _T_180 = eq(_T_179, UInt<1>(0h0))
when _T_180 :
node _T_181 = eq(_T_178, UInt<1>(0h0))
when _T_181 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_178, UInt<1>(0h1), "") : assert_2
node _T_182 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_183 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_184 = and(_T_182, _T_183)
node _T_185 = or(UInt<1>(0h0), _T_184)
node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_187 = cvt(_T_186)
node _T_188 = and(_T_187, asSInt(UInt<14>(0h2000)))
node _T_189 = asSInt(_T_188)
node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0)))
node _T_191 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_192 = cvt(_T_191)
node _T_193 = and(_T_192, asSInt(UInt<13>(0h1000)))
node _T_194 = asSInt(_T_193)
node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0)))
node _T_196 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_197 = cvt(_T_196)
node _T_198 = and(_T_197, asSInt(UInt<17>(0h10000)))
node _T_199 = asSInt(_T_198)
node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0)))
node _T_201 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_202 = cvt(_T_201)
node _T_203 = and(_T_202, asSInt(UInt<18>(0h2f000)))
node _T_204 = asSInt(_T_203)
node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0)))
node _T_206 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_207 = cvt(_T_206)
node _T_208 = and(_T_207, asSInt(UInt<17>(0h10000)))
node _T_209 = asSInt(_T_208)
node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0)))
node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_217 = cvt(_T_216)
node _T_218 = and(_T_217, asSInt(UInt<27>(0h4000000)))
node _T_219 = asSInt(_T_218)
node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0)))
node _T_221 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_222 = cvt(_T_221)
node _T_223 = and(_T_222, asSInt(UInt<13>(0h1000)))
node _T_224 = asSInt(_T_223)
node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0)))
node _T_226 = or(_T_190, _T_195)
node _T_227 = or(_T_226, _T_200)
node _T_228 = or(_T_227, _T_205)
node _T_229 = or(_T_228, _T_210)
node _T_230 = or(_T_229, _T_215)
node _T_231 = or(_T_230, _T_220)
node _T_232 = or(_T_231, _T_225)
node _T_233 = and(_T_185, _T_232)
node _T_234 = or(UInt<1>(0h0), _T_233)
node _T_235 = and(UInt<1>(0h0), _T_234)
node _T_236 = asUInt(reset)
node _T_237 = eq(_T_236, UInt<1>(0h0))
when _T_237 :
node _T_238 = eq(_T_235, UInt<1>(0h0))
when _T_238 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_235, UInt<1>(0h1), "") : assert_3
node _T_239 = asUInt(reset)
node _T_240 = eq(_T_239, UInt<1>(0h0))
when _T_240 :
node _T_241 = eq(source_ok, UInt<1>(0h0))
when _T_241 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_242 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_243 = asUInt(reset)
node _T_244 = eq(_T_243, UInt<1>(0h0))
when _T_244 :
node _T_245 = eq(_T_242, UInt<1>(0h0))
when _T_245 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_242, UInt<1>(0h1), "") : assert_5
node _T_246 = asUInt(reset)
node _T_247 = eq(_T_246, UInt<1>(0h0))
when _T_247 :
node _T_248 = eq(is_aligned, UInt<1>(0h0))
when _T_248 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_249 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_250 = asUInt(reset)
node _T_251 = eq(_T_250, UInt<1>(0h0))
when _T_251 :
node _T_252 = eq(_T_249, UInt<1>(0h0))
when _T_252 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_249, UInt<1>(0h1), "") : assert_7
node _T_253 = not(io.in.a.bits.mask)
node _T_254 = eq(_T_253, UInt<1>(0h0))
node _T_255 = asUInt(reset)
node _T_256 = eq(_T_255, UInt<1>(0h0))
when _T_256 :
node _T_257 = eq(_T_254, UInt<1>(0h0))
when _T_257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_254, UInt<1>(0h1), "") : assert_8
node _T_258 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_259 = asUInt(reset)
node _T_260 = eq(_T_259, UInt<1>(0h0))
when _T_260 :
node _T_261 = eq(_T_258, UInt<1>(0h0))
when _T_261 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_258, UInt<1>(0h1), "") : assert_9
node _T_262 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_262 :
node _T_263 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_264 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_265 = and(_T_263, _T_264)
node _T_266 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_267 = shr(io.in.a.bits.source, 2)
node _T_268 = eq(_T_267, UInt<1>(0h0))
node _T_269 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_270 = and(_T_268, _T_269)
node _T_271 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_272 = and(_T_270, _T_271)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_273 = shr(io.in.a.bits.source, 2)
node _T_274 = eq(_T_273, UInt<1>(0h1))
node _T_275 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_276 = and(_T_274, _T_275)
node _T_277 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_278 = and(_T_276, _T_277)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_279 = shr(io.in.a.bits.source, 2)
node _T_280 = eq(_T_279, UInt<2>(0h2))
node _T_281 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_282 = and(_T_280, _T_281)
node _T_283 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_284 = and(_T_282, _T_283)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_285 = shr(io.in.a.bits.source, 2)
node _T_286 = eq(_T_285, UInt<2>(0h3))
node _T_287 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_288 = and(_T_286, _T_287)
node _T_289 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_290 = and(_T_288, _T_289)
node _T_291 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_292 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_293 = or(_T_266, _T_272)
node _T_294 = or(_T_293, _T_278)
node _T_295 = or(_T_294, _T_284)
node _T_296 = or(_T_295, _T_290)
node _T_297 = or(_T_296, _T_291)
node _T_298 = or(_T_297, _T_292)
node _T_299 = and(_T_265, _T_298)
node _T_300 = or(UInt<1>(0h0), _T_299)
node _T_301 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_302 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_303 = cvt(_T_302)
node _T_304 = and(_T_303, asSInt(UInt<14>(0h2000)))
node _T_305 = asSInt(_T_304)
node _T_306 = eq(_T_305, asSInt(UInt<1>(0h0)))
node _T_307 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_308 = cvt(_T_307)
node _T_309 = and(_T_308, asSInt(UInt<13>(0h1000)))
node _T_310 = asSInt(_T_309)
node _T_311 = eq(_T_310, asSInt(UInt<1>(0h0)))
node _T_312 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_313 = cvt(_T_312)
node _T_314 = and(_T_313, asSInt(UInt<17>(0h10000)))
node _T_315 = asSInt(_T_314)
node _T_316 = eq(_T_315, asSInt(UInt<1>(0h0)))
node _T_317 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_318 = cvt(_T_317)
node _T_319 = and(_T_318, asSInt(UInt<18>(0h2f000)))
node _T_320 = asSInt(_T_319)
node _T_321 = eq(_T_320, asSInt(UInt<1>(0h0)))
node _T_322 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_323 = cvt(_T_322)
node _T_324 = and(_T_323, asSInt(UInt<17>(0h10000)))
node _T_325 = asSInt(_T_324)
node _T_326 = eq(_T_325, asSInt(UInt<1>(0h0)))
node _T_327 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_328 = cvt(_T_327)
node _T_329 = and(_T_328, asSInt(UInt<13>(0h1000)))
node _T_330 = asSInt(_T_329)
node _T_331 = eq(_T_330, asSInt(UInt<1>(0h0)))
node _T_332 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_333 = cvt(_T_332)
node _T_334 = and(_T_333, asSInt(UInt<27>(0h4000000)))
node _T_335 = asSInt(_T_334)
node _T_336 = eq(_T_335, asSInt(UInt<1>(0h0)))
node _T_337 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_338 = cvt(_T_337)
node _T_339 = and(_T_338, asSInt(UInt<13>(0h1000)))
node _T_340 = asSInt(_T_339)
node _T_341 = eq(_T_340, asSInt(UInt<1>(0h0)))
node _T_342 = or(_T_306, _T_311)
node _T_343 = or(_T_342, _T_316)
node _T_344 = or(_T_343, _T_321)
node _T_345 = or(_T_344, _T_326)
node _T_346 = or(_T_345, _T_331)
node _T_347 = or(_T_346, _T_336)
node _T_348 = or(_T_347, _T_341)
node _T_349 = and(_T_301, _T_348)
node _T_350 = or(UInt<1>(0h0), _T_349)
node _T_351 = and(_T_300, _T_350)
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_351, UInt<1>(0h1), "") : assert_10
node _T_355 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_356 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_357 = and(_T_355, _T_356)
node _T_358 = or(UInt<1>(0h0), _T_357)
node _T_359 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_360 = cvt(_T_359)
node _T_361 = and(_T_360, asSInt(UInt<14>(0h2000)))
node _T_362 = asSInt(_T_361)
node _T_363 = eq(_T_362, asSInt(UInt<1>(0h0)))
node _T_364 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_365 = cvt(_T_364)
node _T_366 = and(_T_365, asSInt(UInt<13>(0h1000)))
node _T_367 = asSInt(_T_366)
node _T_368 = eq(_T_367, asSInt(UInt<1>(0h0)))
node _T_369 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_370 = cvt(_T_369)
node _T_371 = and(_T_370, asSInt(UInt<17>(0h10000)))
node _T_372 = asSInt(_T_371)
node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0)))
node _T_374 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_375 = cvt(_T_374)
node _T_376 = and(_T_375, asSInt(UInt<18>(0h2f000)))
node _T_377 = asSInt(_T_376)
node _T_378 = eq(_T_377, asSInt(UInt<1>(0h0)))
node _T_379 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_380 = cvt(_T_379)
node _T_381 = and(_T_380, asSInt(UInt<17>(0h10000)))
node _T_382 = asSInt(_T_381)
node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0)))
node _T_384 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_385 = cvt(_T_384)
node _T_386 = and(_T_385, asSInt(UInt<13>(0h1000)))
node _T_387 = asSInt(_T_386)
node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0)))
node _T_389 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_390 = cvt(_T_389)
node _T_391 = and(_T_390, asSInt(UInt<27>(0h4000000)))
node _T_392 = asSInt(_T_391)
node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0)))
node _T_394 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_395 = cvt(_T_394)
node _T_396 = and(_T_395, asSInt(UInt<13>(0h1000)))
node _T_397 = asSInt(_T_396)
node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0)))
node _T_399 = or(_T_363, _T_368)
node _T_400 = or(_T_399, _T_373)
node _T_401 = or(_T_400, _T_378)
node _T_402 = or(_T_401, _T_383)
node _T_403 = or(_T_402, _T_388)
node _T_404 = or(_T_403, _T_393)
node _T_405 = or(_T_404, _T_398)
node _T_406 = and(_T_358, _T_405)
node _T_407 = or(UInt<1>(0h0), _T_406)
node _T_408 = and(UInt<1>(0h0), _T_407)
node _T_409 = asUInt(reset)
node _T_410 = eq(_T_409, UInt<1>(0h0))
when _T_410 :
node _T_411 = eq(_T_408, UInt<1>(0h0))
when _T_411 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_408, UInt<1>(0h1), "") : assert_11
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(source_ok, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_415 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_416 = asUInt(reset)
node _T_417 = eq(_T_416, UInt<1>(0h0))
when _T_417 :
node _T_418 = eq(_T_415, UInt<1>(0h0))
when _T_418 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_415, UInt<1>(0h1), "") : assert_13
node _T_419 = asUInt(reset)
node _T_420 = eq(_T_419, UInt<1>(0h0))
when _T_420 :
node _T_421 = eq(is_aligned, UInt<1>(0h0))
when _T_421 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_422 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_423 = asUInt(reset)
node _T_424 = eq(_T_423, UInt<1>(0h0))
when _T_424 :
node _T_425 = eq(_T_422, UInt<1>(0h0))
when _T_425 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_422, UInt<1>(0h1), "") : assert_15
node _T_426 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_427 = asUInt(reset)
node _T_428 = eq(_T_427, UInt<1>(0h0))
when _T_428 :
node _T_429 = eq(_T_426, UInt<1>(0h0))
when _T_429 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_426, UInt<1>(0h1), "") : assert_16
node _T_430 = not(io.in.a.bits.mask)
node _T_431 = eq(_T_430, UInt<1>(0h0))
node _T_432 = asUInt(reset)
node _T_433 = eq(_T_432, UInt<1>(0h0))
when _T_433 :
node _T_434 = eq(_T_431, UInt<1>(0h0))
when _T_434 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_431, UInt<1>(0h1), "") : assert_17
node _T_435 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_436 = asUInt(reset)
node _T_437 = eq(_T_436, UInt<1>(0h0))
when _T_437 :
node _T_438 = eq(_T_435, UInt<1>(0h0))
when _T_438 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_435, UInt<1>(0h1), "") : assert_18
node _T_439 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_439 :
node _T_440 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_441 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_442 = and(_T_440, _T_441)
node _T_443 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_444 = shr(io.in.a.bits.source, 2)
node _T_445 = eq(_T_444, UInt<1>(0h0))
node _T_446 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_447 = and(_T_445, _T_446)
node _T_448 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_449 = and(_T_447, _T_448)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_450 = shr(io.in.a.bits.source, 2)
node _T_451 = eq(_T_450, UInt<1>(0h1))
node _T_452 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_453 = and(_T_451, _T_452)
node _T_454 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_455 = and(_T_453, _T_454)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_456 = shr(io.in.a.bits.source, 2)
node _T_457 = eq(_T_456, UInt<2>(0h2))
node _T_458 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_459 = and(_T_457, _T_458)
node _T_460 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_461 = and(_T_459, _T_460)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_462 = shr(io.in.a.bits.source, 2)
node _T_463 = eq(_T_462, UInt<2>(0h3))
node _T_464 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_465 = and(_T_463, _T_464)
node _T_466 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_467 = and(_T_465, _T_466)
node _T_468 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_469 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_470 = or(_T_443, _T_449)
node _T_471 = or(_T_470, _T_455)
node _T_472 = or(_T_471, _T_461)
node _T_473 = or(_T_472, _T_467)
node _T_474 = or(_T_473, _T_468)
node _T_475 = or(_T_474, _T_469)
node _T_476 = and(_T_442, _T_475)
node _T_477 = or(UInt<1>(0h0), _T_476)
node _T_478 = asUInt(reset)
node _T_479 = eq(_T_478, UInt<1>(0h0))
when _T_479 :
node _T_480 = eq(_T_477, UInt<1>(0h0))
when _T_480 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_477, UInt<1>(0h1), "") : assert_19
node _T_481 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_482 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_483 = and(_T_481, _T_482)
node _T_484 = or(UInt<1>(0h0), _T_483)
node _T_485 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_486 = cvt(_T_485)
node _T_487 = and(_T_486, asSInt(UInt<13>(0h1000)))
node _T_488 = asSInt(_T_487)
node _T_489 = eq(_T_488, asSInt(UInt<1>(0h0)))
node _T_490 = and(_T_484, _T_489)
node _T_491 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_492 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_493 = and(_T_491, _T_492)
node _T_494 = or(UInt<1>(0h0), _T_493)
node _T_495 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_496 = cvt(_T_495)
node _T_497 = and(_T_496, asSInt(UInt<14>(0h2000)))
node _T_498 = asSInt(_T_497)
node _T_499 = eq(_T_498, asSInt(UInt<1>(0h0)))
node _T_500 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_501 = cvt(_T_500)
node _T_502 = and(_T_501, asSInt(UInt<17>(0h10000)))
node _T_503 = asSInt(_T_502)
node _T_504 = eq(_T_503, asSInt(UInt<1>(0h0)))
node _T_505 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_506 = cvt(_T_505)
node _T_507 = and(_T_506, asSInt(UInt<18>(0h2f000)))
node _T_508 = asSInt(_T_507)
node _T_509 = eq(_T_508, asSInt(UInt<1>(0h0)))
node _T_510 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_511 = cvt(_T_510)
node _T_512 = and(_T_511, asSInt(UInt<17>(0h10000)))
node _T_513 = asSInt(_T_512)
node _T_514 = eq(_T_513, asSInt(UInt<1>(0h0)))
node _T_515 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_516 = cvt(_T_515)
node _T_517 = and(_T_516, asSInt(UInt<13>(0h1000)))
node _T_518 = asSInt(_T_517)
node _T_519 = eq(_T_518, asSInt(UInt<1>(0h0)))
node _T_520 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_521 = cvt(_T_520)
node _T_522 = and(_T_521, asSInt(UInt<27>(0h4000000)))
node _T_523 = asSInt(_T_522)
node _T_524 = eq(_T_523, asSInt(UInt<1>(0h0)))
node _T_525 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_526 = cvt(_T_525)
node _T_527 = and(_T_526, asSInt(UInt<13>(0h1000)))
node _T_528 = asSInt(_T_527)
node _T_529 = eq(_T_528, asSInt(UInt<1>(0h0)))
node _T_530 = or(_T_499, _T_504)
node _T_531 = or(_T_530, _T_509)
node _T_532 = or(_T_531, _T_514)
node _T_533 = or(_T_532, _T_519)
node _T_534 = or(_T_533, _T_524)
node _T_535 = or(_T_534, _T_529)
node _T_536 = and(_T_494, _T_535)
node _T_537 = or(UInt<1>(0h0), _T_490)
node _T_538 = or(_T_537, _T_536)
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_538, UInt<1>(0h1), "") : assert_20
node _T_542 = asUInt(reset)
node _T_543 = eq(_T_542, UInt<1>(0h0))
when _T_543 :
node _T_544 = eq(source_ok, UInt<1>(0h0))
when _T_544 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(is_aligned, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_548 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_548, UInt<1>(0h1), "") : assert_23
node _T_552 = eq(io.in.a.bits.mask, mask)
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(_T_552, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_552, UInt<1>(0h1), "") : assert_24
node _T_556 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_556, UInt<1>(0h1), "") : assert_25
node _T_560 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_560 :
node _T_561 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_562 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_563 = and(_T_561, _T_562)
node _T_564 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_565 = shr(io.in.a.bits.source, 2)
node _T_566 = eq(_T_565, UInt<1>(0h0))
node _T_567 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_568 = and(_T_566, _T_567)
node _T_569 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_570 = and(_T_568, _T_569)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_571 = shr(io.in.a.bits.source, 2)
node _T_572 = eq(_T_571, UInt<1>(0h1))
node _T_573 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_574 = and(_T_572, _T_573)
node _T_575 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_576 = and(_T_574, _T_575)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_577 = shr(io.in.a.bits.source, 2)
node _T_578 = eq(_T_577, UInt<2>(0h2))
node _T_579 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_580 = and(_T_578, _T_579)
node _T_581 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_582 = and(_T_580, _T_581)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_583 = shr(io.in.a.bits.source, 2)
node _T_584 = eq(_T_583, UInt<2>(0h3))
node _T_585 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_586 = and(_T_584, _T_585)
node _T_587 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_588 = and(_T_586, _T_587)
node _T_589 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_590 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_591 = or(_T_564, _T_570)
node _T_592 = or(_T_591, _T_576)
node _T_593 = or(_T_592, _T_582)
node _T_594 = or(_T_593, _T_588)
node _T_595 = or(_T_594, _T_589)
node _T_596 = or(_T_595, _T_590)
node _T_597 = and(_T_563, _T_596)
node _T_598 = or(UInt<1>(0h0), _T_597)
node _T_599 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_600 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_601 = and(_T_599, _T_600)
node _T_602 = or(UInt<1>(0h0), _T_601)
node _T_603 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_604 = cvt(_T_603)
node _T_605 = and(_T_604, asSInt(UInt<13>(0h1000)))
node _T_606 = asSInt(_T_605)
node _T_607 = eq(_T_606, asSInt(UInt<1>(0h0)))
node _T_608 = and(_T_602, _T_607)
node _T_609 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_610 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_611 = and(_T_609, _T_610)
node _T_612 = or(UInt<1>(0h0), _T_611)
node _T_613 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_614 = cvt(_T_613)
node _T_615 = and(_T_614, asSInt(UInt<14>(0h2000)))
node _T_616 = asSInt(_T_615)
node _T_617 = eq(_T_616, asSInt(UInt<1>(0h0)))
node _T_618 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_619 = cvt(_T_618)
node _T_620 = and(_T_619, asSInt(UInt<18>(0h2f000)))
node _T_621 = asSInt(_T_620)
node _T_622 = eq(_T_621, asSInt(UInt<1>(0h0)))
node _T_623 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_624 = cvt(_T_623)
node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000)))
node _T_626 = asSInt(_T_625)
node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0)))
node _T_628 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_629 = cvt(_T_628)
node _T_630 = and(_T_629, asSInt(UInt<13>(0h1000)))
node _T_631 = asSInt(_T_630)
node _T_632 = eq(_T_631, asSInt(UInt<1>(0h0)))
node _T_633 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_634 = cvt(_T_633)
node _T_635 = and(_T_634, asSInt(UInt<27>(0h4000000)))
node _T_636 = asSInt(_T_635)
node _T_637 = eq(_T_636, asSInt(UInt<1>(0h0)))
node _T_638 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_639 = cvt(_T_638)
node _T_640 = and(_T_639, asSInt(UInt<13>(0h1000)))
node _T_641 = asSInt(_T_640)
node _T_642 = eq(_T_641, asSInt(UInt<1>(0h0)))
node _T_643 = or(_T_617, _T_622)
node _T_644 = or(_T_643, _T_627)
node _T_645 = or(_T_644, _T_632)
node _T_646 = or(_T_645, _T_637)
node _T_647 = or(_T_646, _T_642)
node _T_648 = and(_T_612, _T_647)
node _T_649 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_650 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_651 = cvt(_T_650)
node _T_652 = and(_T_651, asSInt(UInt<17>(0h10000)))
node _T_653 = asSInt(_T_652)
node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0)))
node _T_655 = and(_T_649, _T_654)
node _T_656 = or(UInt<1>(0h0), _T_608)
node _T_657 = or(_T_656, _T_648)
node _T_658 = or(_T_657, _T_655)
node _T_659 = and(_T_598, _T_658)
node _T_660 = asUInt(reset)
node _T_661 = eq(_T_660, UInt<1>(0h0))
when _T_661 :
node _T_662 = eq(_T_659, UInt<1>(0h0))
when _T_662 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_659, UInt<1>(0h1), "") : assert_26
node _T_663 = asUInt(reset)
node _T_664 = eq(_T_663, UInt<1>(0h0))
when _T_664 :
node _T_665 = eq(source_ok, UInt<1>(0h0))
when _T_665 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_666 = asUInt(reset)
node _T_667 = eq(_T_666, UInt<1>(0h0))
when _T_667 :
node _T_668 = eq(is_aligned, UInt<1>(0h0))
when _T_668 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_669 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_670 = asUInt(reset)
node _T_671 = eq(_T_670, UInt<1>(0h0))
when _T_671 :
node _T_672 = eq(_T_669, UInt<1>(0h0))
when _T_672 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_669, UInt<1>(0h1), "") : assert_29
node _T_673 = eq(io.in.a.bits.mask, mask)
node _T_674 = asUInt(reset)
node _T_675 = eq(_T_674, UInt<1>(0h0))
when _T_675 :
node _T_676 = eq(_T_673, UInt<1>(0h0))
when _T_676 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_673, UInt<1>(0h1), "") : assert_30
node _T_677 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_677 :
node _T_678 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_679 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_680 = and(_T_678, _T_679)
node _T_681 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_682 = shr(io.in.a.bits.source, 2)
node _T_683 = eq(_T_682, UInt<1>(0h0))
node _T_684 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_685 = and(_T_683, _T_684)
node _T_686 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_687 = and(_T_685, _T_686)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_688 = shr(io.in.a.bits.source, 2)
node _T_689 = eq(_T_688, UInt<1>(0h1))
node _T_690 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_691 = and(_T_689, _T_690)
node _T_692 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_693 = and(_T_691, _T_692)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_694 = shr(io.in.a.bits.source, 2)
node _T_695 = eq(_T_694, UInt<2>(0h2))
node _T_696 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_697 = and(_T_695, _T_696)
node _T_698 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_699 = and(_T_697, _T_698)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_700 = shr(io.in.a.bits.source, 2)
node _T_701 = eq(_T_700, UInt<2>(0h3))
node _T_702 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_703 = and(_T_701, _T_702)
node _T_704 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_705 = and(_T_703, _T_704)
node _T_706 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_707 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_708 = or(_T_681, _T_687)
node _T_709 = or(_T_708, _T_693)
node _T_710 = or(_T_709, _T_699)
node _T_711 = or(_T_710, _T_705)
node _T_712 = or(_T_711, _T_706)
node _T_713 = or(_T_712, _T_707)
node _T_714 = and(_T_680, _T_713)
node _T_715 = or(UInt<1>(0h0), _T_714)
node _T_716 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_717 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_718 = and(_T_716, _T_717)
node _T_719 = or(UInt<1>(0h0), _T_718)
node _T_720 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_721 = cvt(_T_720)
node _T_722 = and(_T_721, asSInt(UInt<13>(0h1000)))
node _T_723 = asSInt(_T_722)
node _T_724 = eq(_T_723, asSInt(UInt<1>(0h0)))
node _T_725 = and(_T_719, _T_724)
node _T_726 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_727 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_728 = and(_T_726, _T_727)
node _T_729 = or(UInt<1>(0h0), _T_728)
node _T_730 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_731 = cvt(_T_730)
node _T_732 = and(_T_731, asSInt(UInt<14>(0h2000)))
node _T_733 = asSInt(_T_732)
node _T_734 = eq(_T_733, asSInt(UInt<1>(0h0)))
node _T_735 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_736 = cvt(_T_735)
node _T_737 = and(_T_736, asSInt(UInt<18>(0h2f000)))
node _T_738 = asSInt(_T_737)
node _T_739 = eq(_T_738, asSInt(UInt<1>(0h0)))
node _T_740 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_741 = cvt(_T_740)
node _T_742 = and(_T_741, asSInt(UInt<17>(0h10000)))
node _T_743 = asSInt(_T_742)
node _T_744 = eq(_T_743, asSInt(UInt<1>(0h0)))
node _T_745 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_746 = cvt(_T_745)
node _T_747 = and(_T_746, asSInt(UInt<13>(0h1000)))
node _T_748 = asSInt(_T_747)
node _T_749 = eq(_T_748, asSInt(UInt<1>(0h0)))
node _T_750 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_751 = cvt(_T_750)
node _T_752 = and(_T_751, asSInt(UInt<27>(0h4000000)))
node _T_753 = asSInt(_T_752)
node _T_754 = eq(_T_753, asSInt(UInt<1>(0h0)))
node _T_755 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_756 = cvt(_T_755)
node _T_757 = and(_T_756, asSInt(UInt<13>(0h1000)))
node _T_758 = asSInt(_T_757)
node _T_759 = eq(_T_758, asSInt(UInt<1>(0h0)))
node _T_760 = or(_T_734, _T_739)
node _T_761 = or(_T_760, _T_744)
node _T_762 = or(_T_761, _T_749)
node _T_763 = or(_T_762, _T_754)
node _T_764 = or(_T_763, _T_759)
node _T_765 = and(_T_729, _T_764)
node _T_766 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_767 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_768 = cvt(_T_767)
node _T_769 = and(_T_768, asSInt(UInt<17>(0h10000)))
node _T_770 = asSInt(_T_769)
node _T_771 = eq(_T_770, asSInt(UInt<1>(0h0)))
node _T_772 = and(_T_766, _T_771)
node _T_773 = or(UInt<1>(0h0), _T_725)
node _T_774 = or(_T_773, _T_765)
node _T_775 = or(_T_774, _T_772)
node _T_776 = and(_T_715, _T_775)
node _T_777 = asUInt(reset)
node _T_778 = eq(_T_777, UInt<1>(0h0))
when _T_778 :
node _T_779 = eq(_T_776, UInt<1>(0h0))
when _T_779 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_776, UInt<1>(0h1), "") : assert_31
node _T_780 = asUInt(reset)
node _T_781 = eq(_T_780, UInt<1>(0h0))
when _T_781 :
node _T_782 = eq(source_ok, UInt<1>(0h0))
when _T_782 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_783 = asUInt(reset)
node _T_784 = eq(_T_783, UInt<1>(0h0))
when _T_784 :
node _T_785 = eq(is_aligned, UInt<1>(0h0))
when _T_785 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_786 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_787 = asUInt(reset)
node _T_788 = eq(_T_787, UInt<1>(0h0))
when _T_788 :
node _T_789 = eq(_T_786, UInt<1>(0h0))
when _T_789 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_786, UInt<1>(0h1), "") : assert_34
node _T_790 = not(mask)
node _T_791 = and(io.in.a.bits.mask, _T_790)
node _T_792 = eq(_T_791, UInt<1>(0h0))
node _T_793 = asUInt(reset)
node _T_794 = eq(_T_793, UInt<1>(0h0))
when _T_794 :
node _T_795 = eq(_T_792, UInt<1>(0h0))
when _T_795 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_792, UInt<1>(0h1), "") : assert_35
node _T_796 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_796 :
node _T_797 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_798 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_799 = and(_T_797, _T_798)
node _T_800 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_801 = shr(io.in.a.bits.source, 2)
node _T_802 = eq(_T_801, UInt<1>(0h0))
node _T_803 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_804 = and(_T_802, _T_803)
node _T_805 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_806 = and(_T_804, _T_805)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_807 = shr(io.in.a.bits.source, 2)
node _T_808 = eq(_T_807, UInt<1>(0h1))
node _T_809 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_810 = and(_T_808, _T_809)
node _T_811 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_812 = and(_T_810, _T_811)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_813 = shr(io.in.a.bits.source, 2)
node _T_814 = eq(_T_813, UInt<2>(0h2))
node _T_815 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_816 = and(_T_814, _T_815)
node _T_817 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_818 = and(_T_816, _T_817)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_819 = shr(io.in.a.bits.source, 2)
node _T_820 = eq(_T_819, UInt<2>(0h3))
node _T_821 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_822 = and(_T_820, _T_821)
node _T_823 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_824 = and(_T_822, _T_823)
node _T_825 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_826 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_827 = or(_T_800, _T_806)
node _T_828 = or(_T_827, _T_812)
node _T_829 = or(_T_828, _T_818)
node _T_830 = or(_T_829, _T_824)
node _T_831 = or(_T_830, _T_825)
node _T_832 = or(_T_831, _T_826)
node _T_833 = and(_T_799, _T_832)
node _T_834 = or(UInt<1>(0h0), _T_833)
node _T_835 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_836 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_837 = and(_T_835, _T_836)
node _T_838 = or(UInt<1>(0h0), _T_837)
node _T_839 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_840 = cvt(_T_839)
node _T_841 = and(_T_840, asSInt(UInt<14>(0h2000)))
node _T_842 = asSInt(_T_841)
node _T_843 = eq(_T_842, asSInt(UInt<1>(0h0)))
node _T_844 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_845 = cvt(_T_844)
node _T_846 = and(_T_845, asSInt(UInt<13>(0h1000)))
node _T_847 = asSInt(_T_846)
node _T_848 = eq(_T_847, asSInt(UInt<1>(0h0)))
node _T_849 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_850 = cvt(_T_849)
node _T_851 = and(_T_850, asSInt(UInt<18>(0h2f000)))
node _T_852 = asSInt(_T_851)
node _T_853 = eq(_T_852, asSInt(UInt<1>(0h0)))
node _T_854 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_855 = cvt(_T_854)
node _T_856 = and(_T_855, asSInt(UInt<17>(0h10000)))
node _T_857 = asSInt(_T_856)
node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0)))
node _T_859 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_860 = cvt(_T_859)
node _T_861 = and(_T_860, asSInt(UInt<13>(0h1000)))
node _T_862 = asSInt(_T_861)
node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0)))
node _T_864 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_865 = cvt(_T_864)
node _T_866 = and(_T_865, asSInt(UInt<27>(0h4000000)))
node _T_867 = asSInt(_T_866)
node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0)))
node _T_869 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_870 = cvt(_T_869)
node _T_871 = and(_T_870, asSInt(UInt<13>(0h1000)))
node _T_872 = asSInt(_T_871)
node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0)))
node _T_874 = or(_T_843, _T_848)
node _T_875 = or(_T_874, _T_853)
node _T_876 = or(_T_875, _T_858)
node _T_877 = or(_T_876, _T_863)
node _T_878 = or(_T_877, _T_868)
node _T_879 = or(_T_878, _T_873)
node _T_880 = and(_T_838, _T_879)
node _T_881 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_882 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_883 = cvt(_T_882)
node _T_884 = and(_T_883, asSInt(UInt<17>(0h10000)))
node _T_885 = asSInt(_T_884)
node _T_886 = eq(_T_885, asSInt(UInt<1>(0h0)))
node _T_887 = and(_T_881, _T_886)
node _T_888 = or(UInt<1>(0h0), _T_880)
node _T_889 = or(_T_888, _T_887)
node _T_890 = and(_T_834, _T_889)
node _T_891 = asUInt(reset)
node _T_892 = eq(_T_891, UInt<1>(0h0))
when _T_892 :
node _T_893 = eq(_T_890, UInt<1>(0h0))
when _T_893 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_890, UInt<1>(0h1), "") : assert_36
node _T_894 = asUInt(reset)
node _T_895 = eq(_T_894, UInt<1>(0h0))
when _T_895 :
node _T_896 = eq(source_ok, UInt<1>(0h0))
when _T_896 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_897 = asUInt(reset)
node _T_898 = eq(_T_897, UInt<1>(0h0))
when _T_898 :
node _T_899 = eq(is_aligned, UInt<1>(0h0))
when _T_899 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_900 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_901 = asUInt(reset)
node _T_902 = eq(_T_901, UInt<1>(0h0))
when _T_902 :
node _T_903 = eq(_T_900, UInt<1>(0h0))
when _T_903 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_900, UInt<1>(0h1), "") : assert_39
node _T_904 = eq(io.in.a.bits.mask, mask)
node _T_905 = asUInt(reset)
node _T_906 = eq(_T_905, UInt<1>(0h0))
when _T_906 :
node _T_907 = eq(_T_904, UInt<1>(0h0))
when _T_907 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_904, UInt<1>(0h1), "") : assert_40
node _T_908 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_908 :
node _T_909 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_910 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_911 = and(_T_909, _T_910)
node _T_912 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_913 = shr(io.in.a.bits.source, 2)
node _T_914 = eq(_T_913, UInt<1>(0h0))
node _T_915 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_916 = and(_T_914, _T_915)
node _T_917 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_918 = and(_T_916, _T_917)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_919 = shr(io.in.a.bits.source, 2)
node _T_920 = eq(_T_919, UInt<1>(0h1))
node _T_921 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_922 = and(_T_920, _T_921)
node _T_923 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_924 = and(_T_922, _T_923)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_925 = shr(io.in.a.bits.source, 2)
node _T_926 = eq(_T_925, UInt<2>(0h2))
node _T_927 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_928 = and(_T_926, _T_927)
node _T_929 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_930 = and(_T_928, _T_929)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_931 = shr(io.in.a.bits.source, 2)
node _T_932 = eq(_T_931, UInt<2>(0h3))
node _T_933 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_934 = and(_T_932, _T_933)
node _T_935 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_936 = and(_T_934, _T_935)
node _T_937 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_938 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_939 = or(_T_912, _T_918)
node _T_940 = or(_T_939, _T_924)
node _T_941 = or(_T_940, _T_930)
node _T_942 = or(_T_941, _T_936)
node _T_943 = or(_T_942, _T_937)
node _T_944 = or(_T_943, _T_938)
node _T_945 = and(_T_911, _T_944)
node _T_946 = or(UInt<1>(0h0), _T_945)
node _T_947 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_948 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_949 = and(_T_947, _T_948)
node _T_950 = or(UInt<1>(0h0), _T_949)
node _T_951 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_952 = cvt(_T_951)
node _T_953 = and(_T_952, asSInt(UInt<14>(0h2000)))
node _T_954 = asSInt(_T_953)
node _T_955 = eq(_T_954, asSInt(UInt<1>(0h0)))
node _T_956 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_957 = cvt(_T_956)
node _T_958 = and(_T_957, asSInt(UInt<13>(0h1000)))
node _T_959 = asSInt(_T_958)
node _T_960 = eq(_T_959, asSInt(UInt<1>(0h0)))
node _T_961 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_962 = cvt(_T_961)
node _T_963 = and(_T_962, asSInt(UInt<18>(0h2f000)))
node _T_964 = asSInt(_T_963)
node _T_965 = eq(_T_964, asSInt(UInt<1>(0h0)))
node _T_966 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_967 = cvt(_T_966)
node _T_968 = and(_T_967, asSInt(UInt<17>(0h10000)))
node _T_969 = asSInt(_T_968)
node _T_970 = eq(_T_969, asSInt(UInt<1>(0h0)))
node _T_971 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_972 = cvt(_T_971)
node _T_973 = and(_T_972, asSInt(UInt<13>(0h1000)))
node _T_974 = asSInt(_T_973)
node _T_975 = eq(_T_974, asSInt(UInt<1>(0h0)))
node _T_976 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_977 = cvt(_T_976)
node _T_978 = and(_T_977, asSInt(UInt<27>(0h4000000)))
node _T_979 = asSInt(_T_978)
node _T_980 = eq(_T_979, asSInt(UInt<1>(0h0)))
node _T_981 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_982 = cvt(_T_981)
node _T_983 = and(_T_982, asSInt(UInt<13>(0h1000)))
node _T_984 = asSInt(_T_983)
node _T_985 = eq(_T_984, asSInt(UInt<1>(0h0)))
node _T_986 = or(_T_955, _T_960)
node _T_987 = or(_T_986, _T_965)
node _T_988 = or(_T_987, _T_970)
node _T_989 = or(_T_988, _T_975)
node _T_990 = or(_T_989, _T_980)
node _T_991 = or(_T_990, _T_985)
node _T_992 = and(_T_950, _T_991)
node _T_993 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_994 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_995 = cvt(_T_994)
node _T_996 = and(_T_995, asSInt(UInt<17>(0h10000)))
node _T_997 = asSInt(_T_996)
node _T_998 = eq(_T_997, asSInt(UInt<1>(0h0)))
node _T_999 = and(_T_993, _T_998)
node _T_1000 = or(UInt<1>(0h0), _T_992)
node _T_1001 = or(_T_1000, _T_999)
node _T_1002 = and(_T_946, _T_1001)
node _T_1003 = asUInt(reset)
node _T_1004 = eq(_T_1003, UInt<1>(0h0))
when _T_1004 :
node _T_1005 = eq(_T_1002, UInt<1>(0h0))
when _T_1005 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_1002, UInt<1>(0h1), "") : assert_41
node _T_1006 = asUInt(reset)
node _T_1007 = eq(_T_1006, UInt<1>(0h0))
when _T_1007 :
node _T_1008 = eq(source_ok, UInt<1>(0h0))
when _T_1008 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_1009 = asUInt(reset)
node _T_1010 = eq(_T_1009, UInt<1>(0h0))
when _T_1010 :
node _T_1011 = eq(is_aligned, UInt<1>(0h0))
when _T_1011 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_1012 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_1013 = asUInt(reset)
node _T_1014 = eq(_T_1013, UInt<1>(0h0))
when _T_1014 :
node _T_1015 = eq(_T_1012, UInt<1>(0h0))
when _T_1015 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_1012, UInt<1>(0h1), "") : assert_44
node _T_1016 = eq(io.in.a.bits.mask, mask)
node _T_1017 = asUInt(reset)
node _T_1018 = eq(_T_1017, UInt<1>(0h0))
when _T_1018 :
node _T_1019 = eq(_T_1016, UInt<1>(0h0))
when _T_1019 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_1016, UInt<1>(0h1), "") : assert_45
node _T_1020 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_1020 :
node _T_1021 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1022 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1023 = and(_T_1021, _T_1022)
node _T_1024 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_1025 = shr(io.in.a.bits.source, 2)
node _T_1026 = eq(_T_1025, UInt<1>(0h0))
node _T_1027 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_1028 = and(_T_1026, _T_1027)
node _T_1029 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_1030 = and(_T_1028, _T_1029)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_1031 = shr(io.in.a.bits.source, 2)
node _T_1032 = eq(_T_1031, UInt<1>(0h1))
node _T_1033 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_1034 = and(_T_1032, _T_1033)
node _T_1035 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_1036 = and(_T_1034, _T_1035)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_1037 = shr(io.in.a.bits.source, 2)
node _T_1038 = eq(_T_1037, UInt<2>(0h2))
node _T_1039 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_1040 = and(_T_1038, _T_1039)
node _T_1041 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_1042 = and(_T_1040, _T_1041)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_1043 = shr(io.in.a.bits.source, 2)
node _T_1044 = eq(_T_1043, UInt<2>(0h3))
node _T_1045 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_1046 = and(_T_1044, _T_1045)
node _T_1047 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_1048 = and(_T_1046, _T_1047)
node _T_1049 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1050 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1051 = or(_T_1024, _T_1030)
node _T_1052 = or(_T_1051, _T_1036)
node _T_1053 = or(_T_1052, _T_1042)
node _T_1054 = or(_T_1053, _T_1048)
node _T_1055 = or(_T_1054, _T_1049)
node _T_1056 = or(_T_1055, _T_1050)
node _T_1057 = and(_T_1023, _T_1056)
node _T_1058 = or(UInt<1>(0h0), _T_1057)
node _T_1059 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1060 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1061 = and(_T_1059, _T_1060)
node _T_1062 = or(UInt<1>(0h0), _T_1061)
node _T_1063 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1064 = cvt(_T_1063)
node _T_1065 = and(_T_1064, asSInt(UInt<13>(0h1000)))
node _T_1066 = asSInt(_T_1065)
node _T_1067 = eq(_T_1066, asSInt(UInt<1>(0h0)))
node _T_1068 = and(_T_1062, _T_1067)
node _T_1069 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1070 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1071 = cvt(_T_1070)
node _T_1072 = and(_T_1071, asSInt(UInt<14>(0h2000)))
node _T_1073 = asSInt(_T_1072)
node _T_1074 = eq(_T_1073, asSInt(UInt<1>(0h0)))
node _T_1075 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1076 = cvt(_T_1075)
node _T_1077 = and(_T_1076, asSInt(UInt<17>(0h10000)))
node _T_1078 = asSInt(_T_1077)
node _T_1079 = eq(_T_1078, asSInt(UInt<1>(0h0)))
node _T_1080 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1081 = cvt(_T_1080)
node _T_1082 = and(_T_1081, asSInt(UInt<18>(0h2f000)))
node _T_1083 = asSInt(_T_1082)
node _T_1084 = eq(_T_1083, asSInt(UInt<1>(0h0)))
node _T_1085 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1086 = cvt(_T_1085)
node _T_1087 = and(_T_1086, asSInt(UInt<17>(0h10000)))
node _T_1088 = asSInt(_T_1087)
node _T_1089 = eq(_T_1088, asSInt(UInt<1>(0h0)))
node _T_1090 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1091 = cvt(_T_1090)
node _T_1092 = and(_T_1091, asSInt(UInt<13>(0h1000)))
node _T_1093 = asSInt(_T_1092)
node _T_1094 = eq(_T_1093, asSInt(UInt<1>(0h0)))
node _T_1095 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1096 = cvt(_T_1095)
node _T_1097 = and(_T_1096, asSInt(UInt<27>(0h4000000)))
node _T_1098 = asSInt(_T_1097)
node _T_1099 = eq(_T_1098, asSInt(UInt<1>(0h0)))
node _T_1100 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1101 = cvt(_T_1100)
node _T_1102 = and(_T_1101, asSInt(UInt<13>(0h1000)))
node _T_1103 = asSInt(_T_1102)
node _T_1104 = eq(_T_1103, asSInt(UInt<1>(0h0)))
node _T_1105 = or(_T_1074, _T_1079)
node _T_1106 = or(_T_1105, _T_1084)
node _T_1107 = or(_T_1106, _T_1089)
node _T_1108 = or(_T_1107, _T_1094)
node _T_1109 = or(_T_1108, _T_1099)
node _T_1110 = or(_T_1109, _T_1104)
node _T_1111 = and(_T_1069, _T_1110)
node _T_1112 = or(UInt<1>(0h0), _T_1068)
node _T_1113 = or(_T_1112, _T_1111)
node _T_1114 = and(_T_1058, _T_1113)
node _T_1115 = asUInt(reset)
node _T_1116 = eq(_T_1115, UInt<1>(0h0))
when _T_1116 :
node _T_1117 = eq(_T_1114, UInt<1>(0h0))
when _T_1117 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1114, UInt<1>(0h1), "") : assert_46
node _T_1118 = asUInt(reset)
node _T_1119 = eq(_T_1118, UInt<1>(0h0))
when _T_1119 :
node _T_1120 = eq(source_ok, UInt<1>(0h0))
when _T_1120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1121 = asUInt(reset)
node _T_1122 = eq(_T_1121, UInt<1>(0h0))
when _T_1122 :
node _T_1123 = eq(is_aligned, UInt<1>(0h0))
when _T_1123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1124 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1125 = asUInt(reset)
node _T_1126 = eq(_T_1125, UInt<1>(0h0))
when _T_1126 :
node _T_1127 = eq(_T_1124, UInt<1>(0h0))
when _T_1127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1124, UInt<1>(0h1), "") : assert_49
node _T_1128 = eq(io.in.a.bits.mask, mask)
node _T_1129 = asUInt(reset)
node _T_1130 = eq(_T_1129, UInt<1>(0h0))
when _T_1130 :
node _T_1131 = eq(_T_1128, UInt<1>(0h0))
when _T_1131 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1128, UInt<1>(0h1), "") : assert_50
node _T_1132 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1133 = asUInt(reset)
node _T_1134 = eq(_T_1133, UInt<1>(0h0))
when _T_1134 :
node _T_1135 = eq(_T_1132, UInt<1>(0h0))
when _T_1135 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1132, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1136 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1137 = asUInt(reset)
node _T_1138 = eq(_T_1137, UInt<1>(0h0))
when _T_1138 :
node _T_1139 = eq(_T_1136, UInt<1>(0h0))
when _T_1139 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1136, UInt<1>(0h1), "") : assert_52
node _source_ok_T_32 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_33 = shr(io.in.d.bits.source, 2)
node _source_ok_T_34 = eq(_source_ok_T_33, UInt<1>(0h0))
node _source_ok_T_35 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35)
node _source_ok_T_37 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37)
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_39 = shr(io.in.d.bits.source, 2)
node _source_ok_T_40 = eq(_source_ok_T_39, UInt<1>(0h1))
node _source_ok_T_41 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41)
node _source_ok_T_43 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_45 = shr(io.in.d.bits.source, 2)
node _source_ok_T_46 = eq(_source_ok_T_45, UInt<2>(0h2))
node _source_ok_T_47 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47)
node _source_ok_T_49 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_51 = shr(io.in.d.bits.source, 2)
node _source_ok_T_52 = eq(_source_ok_T_51, UInt<2>(0h3))
node _source_ok_T_53 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53)
node _source_ok_T_55 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55)
node _source_ok_T_57 = eq(io.in.d.bits.source, UInt<6>(0h21))
node _source_ok_T_58 = eq(io.in.d.bits.source, UInt<6>(0h20))
wire _source_ok_WIRE_1 : UInt<1>[7]
connect _source_ok_WIRE_1[0], _source_ok_T_32
connect _source_ok_WIRE_1[1], _source_ok_T_38
connect _source_ok_WIRE_1[2], _source_ok_T_44
connect _source_ok_WIRE_1[3], _source_ok_T_50
connect _source_ok_WIRE_1[4], _source_ok_T_56
connect _source_ok_WIRE_1[5], _source_ok_T_57
connect _source_ok_WIRE_1[6], _source_ok_T_58
node _source_ok_T_59 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_60 = or(_source_ok_T_59, _source_ok_WIRE_1[2])
node _source_ok_T_61 = or(_source_ok_T_60, _source_ok_WIRE_1[3])
node _source_ok_T_62 = or(_source_ok_T_61, _source_ok_WIRE_1[4])
node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE_1[5])
node source_ok_1 = or(_source_ok_T_63, _source_ok_WIRE_1[6])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1140 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1140 :
node _T_1141 = asUInt(reset)
node _T_1142 = eq(_T_1141, UInt<1>(0h0))
when _T_1142 :
node _T_1143 = eq(source_ok_1, UInt<1>(0h0))
when _T_1143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1144 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_1145 = asUInt(reset)
node _T_1146 = eq(_T_1145, UInt<1>(0h0))
when _T_1146 :
node _T_1147 = eq(_T_1144, UInt<1>(0h0))
when _T_1147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1144, UInt<1>(0h1), "") : assert_54
node _T_1148 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1149 = asUInt(reset)
node _T_1150 = eq(_T_1149, UInt<1>(0h0))
when _T_1150 :
node _T_1151 = eq(_T_1148, UInt<1>(0h0))
when _T_1151 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1148, UInt<1>(0h1), "") : assert_55
node _T_1152 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1153 = asUInt(reset)
node _T_1154 = eq(_T_1153, UInt<1>(0h0))
when _T_1154 :
node _T_1155 = eq(_T_1152, UInt<1>(0h0))
when _T_1155 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1152, UInt<1>(0h1), "") : assert_56
node _T_1156 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1157 = asUInt(reset)
node _T_1158 = eq(_T_1157, UInt<1>(0h0))
when _T_1158 :
node _T_1159 = eq(_T_1156, UInt<1>(0h0))
when _T_1159 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1156, UInt<1>(0h1), "") : assert_57
node _T_1160 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1160 :
node _T_1161 = asUInt(reset)
node _T_1162 = eq(_T_1161, UInt<1>(0h0))
when _T_1162 :
node _T_1163 = eq(source_ok_1, UInt<1>(0h0))
when _T_1163 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1164 = asUInt(reset)
node _T_1165 = eq(_T_1164, UInt<1>(0h0))
when _T_1165 :
node _T_1166 = eq(sink_ok, UInt<1>(0h0))
when _T_1166 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1167 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_1168 = asUInt(reset)
node _T_1169 = eq(_T_1168, UInt<1>(0h0))
when _T_1169 :
node _T_1170 = eq(_T_1167, UInt<1>(0h0))
when _T_1170 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1167, UInt<1>(0h1), "") : assert_60
node _T_1171 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1172 = asUInt(reset)
node _T_1173 = eq(_T_1172, UInt<1>(0h0))
when _T_1173 :
node _T_1174 = eq(_T_1171, UInt<1>(0h0))
when _T_1174 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1171, UInt<1>(0h1), "") : assert_61
node _T_1175 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1176 = asUInt(reset)
node _T_1177 = eq(_T_1176, UInt<1>(0h0))
when _T_1177 :
node _T_1178 = eq(_T_1175, UInt<1>(0h0))
when _T_1178 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1175, UInt<1>(0h1), "") : assert_62
node _T_1179 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1180 = asUInt(reset)
node _T_1181 = eq(_T_1180, UInt<1>(0h0))
when _T_1181 :
node _T_1182 = eq(_T_1179, UInt<1>(0h0))
when _T_1182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1179, UInt<1>(0h1), "") : assert_63
node _T_1183 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1184 = or(UInt<1>(0h1), _T_1183)
node _T_1185 = asUInt(reset)
node _T_1186 = eq(_T_1185, UInt<1>(0h0))
when _T_1186 :
node _T_1187 = eq(_T_1184, UInt<1>(0h0))
when _T_1187 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1184, UInt<1>(0h1), "") : assert_64
node _T_1188 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1188 :
node _T_1189 = asUInt(reset)
node _T_1190 = eq(_T_1189, UInt<1>(0h0))
when _T_1190 :
node _T_1191 = eq(source_ok_1, UInt<1>(0h0))
when _T_1191 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1192 = asUInt(reset)
node _T_1193 = eq(_T_1192, UInt<1>(0h0))
when _T_1193 :
node _T_1194 = eq(sink_ok, UInt<1>(0h0))
when _T_1194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1195 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_1196 = asUInt(reset)
node _T_1197 = eq(_T_1196, UInt<1>(0h0))
when _T_1197 :
node _T_1198 = eq(_T_1195, UInt<1>(0h0))
when _T_1198 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1195, UInt<1>(0h1), "") : assert_67
node _T_1199 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1200 = asUInt(reset)
node _T_1201 = eq(_T_1200, UInt<1>(0h0))
when _T_1201 :
node _T_1202 = eq(_T_1199, UInt<1>(0h0))
when _T_1202 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1199, UInt<1>(0h1), "") : assert_68
node _T_1203 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1204 = asUInt(reset)
node _T_1205 = eq(_T_1204, UInt<1>(0h0))
when _T_1205 :
node _T_1206 = eq(_T_1203, UInt<1>(0h0))
when _T_1206 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1203, UInt<1>(0h1), "") : assert_69
node _T_1207 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1208 = or(_T_1207, io.in.d.bits.corrupt)
node _T_1209 = asUInt(reset)
node _T_1210 = eq(_T_1209, UInt<1>(0h0))
when _T_1210 :
node _T_1211 = eq(_T_1208, UInt<1>(0h0))
when _T_1211 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1208, UInt<1>(0h1), "") : assert_70
node _T_1212 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1213 = or(UInt<1>(0h1), _T_1212)
node _T_1214 = asUInt(reset)
node _T_1215 = eq(_T_1214, UInt<1>(0h0))
when _T_1215 :
node _T_1216 = eq(_T_1213, UInt<1>(0h0))
when _T_1216 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1213, UInt<1>(0h1), "") : assert_71
node _T_1217 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1217 :
node _T_1218 = asUInt(reset)
node _T_1219 = eq(_T_1218, UInt<1>(0h0))
when _T_1219 :
node _T_1220 = eq(source_ok_1, UInt<1>(0h0))
when _T_1220 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1221 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1222 = asUInt(reset)
node _T_1223 = eq(_T_1222, UInt<1>(0h0))
when _T_1223 :
node _T_1224 = eq(_T_1221, UInt<1>(0h0))
when _T_1224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1221, UInt<1>(0h1), "") : assert_73
node _T_1225 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1226 = asUInt(reset)
node _T_1227 = eq(_T_1226, UInt<1>(0h0))
when _T_1227 :
node _T_1228 = eq(_T_1225, UInt<1>(0h0))
when _T_1228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1225, UInt<1>(0h1), "") : assert_74
node _T_1229 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1230 = or(UInt<1>(0h1), _T_1229)
node _T_1231 = asUInt(reset)
node _T_1232 = eq(_T_1231, UInt<1>(0h0))
when _T_1232 :
node _T_1233 = eq(_T_1230, UInt<1>(0h0))
when _T_1233 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1230, UInt<1>(0h1), "") : assert_75
node _T_1234 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1234 :
node _T_1235 = asUInt(reset)
node _T_1236 = eq(_T_1235, UInt<1>(0h0))
when _T_1236 :
node _T_1237 = eq(source_ok_1, UInt<1>(0h0))
when _T_1237 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1238 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1239 = asUInt(reset)
node _T_1240 = eq(_T_1239, UInt<1>(0h0))
when _T_1240 :
node _T_1241 = eq(_T_1238, UInt<1>(0h0))
when _T_1241 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1238, UInt<1>(0h1), "") : assert_77
node _T_1242 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1243 = or(_T_1242, io.in.d.bits.corrupt)
node _T_1244 = asUInt(reset)
node _T_1245 = eq(_T_1244, UInt<1>(0h0))
when _T_1245 :
node _T_1246 = eq(_T_1243, UInt<1>(0h0))
when _T_1246 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1243, UInt<1>(0h1), "") : assert_78
node _T_1247 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1248 = or(UInt<1>(0h1), _T_1247)
node _T_1249 = asUInt(reset)
node _T_1250 = eq(_T_1249, UInt<1>(0h0))
when _T_1250 :
node _T_1251 = eq(_T_1248, UInt<1>(0h0))
when _T_1251 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1248, UInt<1>(0h1), "") : assert_79
node _T_1252 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1252 :
node _T_1253 = asUInt(reset)
node _T_1254 = eq(_T_1253, UInt<1>(0h0))
when _T_1254 :
node _T_1255 = eq(source_ok_1, UInt<1>(0h0))
when _T_1255 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1256 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1257 = asUInt(reset)
node _T_1258 = eq(_T_1257, UInt<1>(0h0))
when _T_1258 :
node _T_1259 = eq(_T_1256, UInt<1>(0h0))
when _T_1259 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1256, UInt<1>(0h1), "") : assert_81
node _T_1260 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1261 = asUInt(reset)
node _T_1262 = eq(_T_1261, UInt<1>(0h0))
when _T_1262 :
node _T_1263 = eq(_T_1260, UInt<1>(0h0))
when _T_1263 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1260, UInt<1>(0h1), "") : assert_82
node _T_1264 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1265 = or(UInt<1>(0h1), _T_1264)
node _T_1266 = asUInt(reset)
node _T_1267 = eq(_T_1266, UInt<1>(0h0))
when _T_1267 :
node _T_1268 = eq(_T_1265, UInt<1>(0h0))
when _T_1268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1265, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<32>(0h0)
connect _WIRE.bits.mask, UInt<4>(0h0)
connect _WIRE.bits.address, UInt<29>(0h0)
connect _WIRE.bits.source, UInt<6>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1269 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_1270 = asUInt(reset)
node _T_1271 = eq(_T_1270, UInt<1>(0h0))
when _T_1271 :
node _T_1272 = eq(_T_1269, UInt<1>(0h0))
when _T_1272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1269, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<32>(0h0)
connect _WIRE_2.bits.address, UInt<29>(0h0)
connect _WIRE_2.bits.source, UInt<6>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_1273 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_1274 = asUInt(reset)
node _T_1275 = eq(_T_1274, UInt<1>(0h0))
when _T_1275 :
node _T_1276 = eq(_T_1273, UInt<1>(0h0))
when _T_1276 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1273, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1277 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1278 = asUInt(reset)
node _T_1279 = eq(_T_1278, UInt<1>(0h0))
when _T_1279 :
node _T_1280 = eq(_T_1277, UInt<1>(0h0))
when _T_1280 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1277, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<10>, clock, reset, UInt<10>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1281 = eq(a_first, UInt<1>(0h0))
node _T_1282 = and(io.in.a.valid, _T_1281)
when _T_1282 :
node _T_1283 = eq(io.in.a.bits.opcode, opcode)
node _T_1284 = asUInt(reset)
node _T_1285 = eq(_T_1284, UInt<1>(0h0))
when _T_1285 :
node _T_1286 = eq(_T_1283, UInt<1>(0h0))
when _T_1286 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1283, UInt<1>(0h1), "") : assert_87
node _T_1287 = eq(io.in.a.bits.param, param)
node _T_1288 = asUInt(reset)
node _T_1289 = eq(_T_1288, UInt<1>(0h0))
when _T_1289 :
node _T_1290 = eq(_T_1287, UInt<1>(0h0))
when _T_1290 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1287, UInt<1>(0h1), "") : assert_88
node _T_1291 = eq(io.in.a.bits.size, size)
node _T_1292 = asUInt(reset)
node _T_1293 = eq(_T_1292, UInt<1>(0h0))
when _T_1293 :
node _T_1294 = eq(_T_1291, UInt<1>(0h0))
when _T_1294 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1291, UInt<1>(0h1), "") : assert_89
node _T_1295 = eq(io.in.a.bits.source, source)
node _T_1296 = asUInt(reset)
node _T_1297 = eq(_T_1296, UInt<1>(0h0))
when _T_1297 :
node _T_1298 = eq(_T_1295, UInt<1>(0h0))
when _T_1298 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1295, UInt<1>(0h1), "") : assert_90
node _T_1299 = eq(io.in.a.bits.address, address)
node _T_1300 = asUInt(reset)
node _T_1301 = eq(_T_1300, UInt<1>(0h0))
when _T_1301 :
node _T_1302 = eq(_T_1299, UInt<1>(0h0))
when _T_1302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1299, UInt<1>(0h1), "") : assert_91
node _T_1303 = and(io.in.a.ready, io.in.a.valid)
node _T_1304 = and(_T_1303, a_first)
when _T_1304 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<10>, clock, reset, UInt<10>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1305 = eq(d_first, UInt<1>(0h0))
node _T_1306 = and(io.in.d.valid, _T_1305)
when _T_1306 :
node _T_1307 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1308 = asUInt(reset)
node _T_1309 = eq(_T_1308, UInt<1>(0h0))
when _T_1309 :
node _T_1310 = eq(_T_1307, UInt<1>(0h0))
when _T_1310 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1307, UInt<1>(0h1), "") : assert_92
node _T_1311 = eq(io.in.d.bits.param, param_1)
node _T_1312 = asUInt(reset)
node _T_1313 = eq(_T_1312, UInt<1>(0h0))
when _T_1313 :
node _T_1314 = eq(_T_1311, UInt<1>(0h0))
when _T_1314 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1311, UInt<1>(0h1), "") : assert_93
node _T_1315 = eq(io.in.d.bits.size, size_1)
node _T_1316 = asUInt(reset)
node _T_1317 = eq(_T_1316, UInt<1>(0h0))
when _T_1317 :
node _T_1318 = eq(_T_1315, UInt<1>(0h0))
when _T_1318 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1315, UInt<1>(0h1), "") : assert_94
node _T_1319 = eq(io.in.d.bits.source, source_1)
node _T_1320 = asUInt(reset)
node _T_1321 = eq(_T_1320, UInt<1>(0h0))
when _T_1321 :
node _T_1322 = eq(_T_1319, UInt<1>(0h0))
when _T_1322 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1319, UInt<1>(0h1), "") : assert_95
node _T_1323 = eq(io.in.d.bits.sink, sink)
node _T_1324 = asUInt(reset)
node _T_1325 = eq(_T_1324, UInt<1>(0h0))
when _T_1325 :
node _T_1326 = eq(_T_1323, UInt<1>(0h0))
when _T_1326 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1323, UInt<1>(0h1), "") : assert_96
node _T_1327 = eq(io.in.d.bits.denied, denied)
node _T_1328 = asUInt(reset)
node _T_1329 = eq(_T_1328, UInt<1>(0h0))
when _T_1329 :
node _T_1330 = eq(_T_1327, UInt<1>(0h0))
when _T_1330 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1327, UInt<1>(0h1), "") : assert_97
node _T_1331 = and(io.in.d.ready, io.in.d.valid)
node _T_1332 = and(_T_1331, d_first)
when _T_1332 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<34>, clock, reset, UInt<34>(0h0)
regreset inflight_opcodes : UInt<136>, clock, reset, UInt<136>(0h0)
regreset inflight_sizes : UInt<272>, clock, reset, UInt<272>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<10>, clock, reset, UInt<10>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<10>, clock, reset, UInt<10>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<34>
connect a_set, UInt<34>(0h0)
wire a_set_wo_ready : UInt<34>
connect a_set_wo_ready, UInt<34>(0h0)
wire a_opcodes_set : UInt<136>
connect a_opcodes_set, UInt<136>(0h0)
wire a_sizes_set : UInt<272>
connect a_sizes_set, UInt<272>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1333 = and(io.in.a.valid, a_first_1)
node _T_1334 = and(_T_1333, UInt<1>(0h1))
when _T_1334 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1335 = and(io.in.a.ready, io.in.a.valid)
node _T_1336 = and(_T_1335, a_first_1)
node _T_1337 = and(_T_1336, UInt<1>(0h1))
when _T_1337 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1338 = dshr(inflight, io.in.a.bits.source)
node _T_1339 = bits(_T_1338, 0, 0)
node _T_1340 = eq(_T_1339, UInt<1>(0h0))
node _T_1341 = asUInt(reset)
node _T_1342 = eq(_T_1341, UInt<1>(0h0))
when _T_1342 :
node _T_1343 = eq(_T_1340, UInt<1>(0h0))
when _T_1343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1340, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<34>
connect d_clr, UInt<34>(0h0)
wire d_clr_wo_ready : UInt<34>
connect d_clr_wo_ready, UInt<34>(0h0)
wire d_opcodes_clr : UInt<136>
connect d_opcodes_clr, UInt<136>(0h0)
wire d_sizes_clr : UInt<272>
connect d_sizes_clr, UInt<272>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1344 = and(io.in.d.valid, d_first_1)
node _T_1345 = and(_T_1344, UInt<1>(0h1))
node _T_1346 = eq(d_release_ack, UInt<1>(0h0))
node _T_1347 = and(_T_1345, _T_1346)
when _T_1347 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1348 = and(io.in.d.ready, io.in.d.valid)
node _T_1349 = and(_T_1348, d_first_1)
node _T_1350 = and(_T_1349, UInt<1>(0h1))
node _T_1351 = eq(d_release_ack, UInt<1>(0h0))
node _T_1352 = and(_T_1350, _T_1351)
when _T_1352 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1353 = and(io.in.d.valid, d_first_1)
node _T_1354 = and(_T_1353, UInt<1>(0h1))
node _T_1355 = eq(d_release_ack, UInt<1>(0h0))
node _T_1356 = and(_T_1354, _T_1355)
when _T_1356 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1357 = dshr(inflight, io.in.d.bits.source)
node _T_1358 = bits(_T_1357, 0, 0)
node _T_1359 = or(_T_1358, same_cycle_resp)
node _T_1360 = asUInt(reset)
node _T_1361 = eq(_T_1360, UInt<1>(0h0))
when _T_1361 :
node _T_1362 = eq(_T_1359, UInt<1>(0h0))
when _T_1362 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1359, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1363 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1364 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1365 = or(_T_1363, _T_1364)
node _T_1366 = asUInt(reset)
node _T_1367 = eq(_T_1366, UInt<1>(0h0))
when _T_1367 :
node _T_1368 = eq(_T_1365, UInt<1>(0h0))
when _T_1368 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1365, UInt<1>(0h1), "") : assert_100
node _T_1369 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1370 = asUInt(reset)
node _T_1371 = eq(_T_1370, UInt<1>(0h0))
when _T_1371 :
node _T_1372 = eq(_T_1369, UInt<1>(0h0))
when _T_1372 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1369, UInt<1>(0h1), "") : assert_101
else :
node _T_1373 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1374 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1375 = or(_T_1373, _T_1374)
node _T_1376 = asUInt(reset)
node _T_1377 = eq(_T_1376, UInt<1>(0h0))
when _T_1377 :
node _T_1378 = eq(_T_1375, UInt<1>(0h0))
when _T_1378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1375, UInt<1>(0h1), "") : assert_102
node _T_1379 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1380 = asUInt(reset)
node _T_1381 = eq(_T_1380, UInt<1>(0h0))
when _T_1381 :
node _T_1382 = eq(_T_1379, UInt<1>(0h0))
when _T_1382 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1379, UInt<1>(0h1), "") : assert_103
node _T_1383 = and(io.in.d.valid, d_first_1)
node _T_1384 = and(_T_1383, a_first_1)
node _T_1385 = and(_T_1384, io.in.a.valid)
node _T_1386 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1387 = and(_T_1385, _T_1386)
node _T_1388 = eq(d_release_ack, UInt<1>(0h0))
node _T_1389 = and(_T_1387, _T_1388)
when _T_1389 :
node _T_1390 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1391 = or(_T_1390, io.in.a.ready)
node _T_1392 = asUInt(reset)
node _T_1393 = eq(_T_1392, UInt<1>(0h0))
when _T_1393 :
node _T_1394 = eq(_T_1391, UInt<1>(0h0))
when _T_1394 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1391, UInt<1>(0h1), "") : assert_104
node _T_1395 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1396 = orr(a_set_wo_ready)
node _T_1397 = eq(_T_1396, UInt<1>(0h0))
node _T_1398 = or(_T_1395, _T_1397)
node _T_1399 = asUInt(reset)
node _T_1400 = eq(_T_1399, UInt<1>(0h0))
when _T_1400 :
node _T_1401 = eq(_T_1398, UInt<1>(0h0))
when _T_1401 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1398, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_4
node _T_1402 = orr(inflight)
node _T_1403 = eq(_T_1402, UInt<1>(0h0))
node _T_1404 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1405 = or(_T_1403, _T_1404)
node _T_1406 = lt(watchdog, plusarg_reader.out)
node _T_1407 = or(_T_1405, _T_1406)
node _T_1408 = asUInt(reset)
node _T_1409 = eq(_T_1408, UInt<1>(0h0))
when _T_1409 :
node _T_1410 = eq(_T_1407, UInt<1>(0h0))
when _T_1410 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1407, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1411 = and(io.in.a.ready, io.in.a.valid)
node _T_1412 = and(io.in.d.ready, io.in.d.valid)
node _T_1413 = or(_T_1411, _T_1412)
when _T_1413 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<34>, clock, reset, UInt<34>(0h0)
regreset inflight_opcodes_1 : UInt<136>, clock, reset, UInt<136>(0h0)
regreset inflight_sizes_1 : UInt<272>, clock, reset, UInt<272>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<32>(0h0)
connect _c_first_WIRE.bits.address, UInt<29>(0h0)
connect _c_first_WIRE.bits.source, UInt<6>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<6>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<10>, clock, reset, UInt<10>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<10>, clock, reset, UInt<10>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<34>
connect c_set, UInt<34>(0h0)
wire c_set_wo_ready : UInt<34>
connect c_set_wo_ready, UInt<34>(0h0)
wire c_opcodes_set : UInt<136>
connect c_opcodes_set, UInt<136>(0h0)
wire c_sizes_set : UInt<272>
connect c_sizes_set, UInt<272>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<32>(0h0)
connect _WIRE_6.bits.address, UInt<29>(0h0)
connect _WIRE_6.bits.source, UInt<6>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1414 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<32>(0h0)
connect _WIRE_8.bits.address, UInt<29>(0h0)
connect _WIRE_8.bits.source, UInt<6>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1415 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1416 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1417 = and(_T_1415, _T_1416)
node _T_1418 = and(_T_1414, _T_1417)
when _T_1418 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<6>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<32>(0h0)
connect _WIRE_10.bits.address, UInt<29>(0h0)
connect _WIRE_10.bits.source, UInt<6>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1419 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1420 = and(_T_1419, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<32>(0h0)
connect _WIRE_12.bits.address, UInt<29>(0h0)
connect _WIRE_12.bits.source, UInt<6>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1421 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1422 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1423 = and(_T_1421, _T_1422)
node _T_1424 = and(_T_1420, _T_1423)
when _T_1424 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_WIRE.bits.source, UInt<6>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<6>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<6>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<6>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<6>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<32>(0h0)
connect _WIRE_14.bits.address, UInt<29>(0h0)
connect _WIRE_14.bits.source, UInt<6>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1425 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1426 = bits(_T_1425, 0, 0)
node _T_1427 = eq(_T_1426, UInt<1>(0h0))
node _T_1428 = asUInt(reset)
node _T_1429 = eq(_T_1428, UInt<1>(0h0))
when _T_1429 :
node _T_1430 = eq(_T_1427, UInt<1>(0h0))
when _T_1430 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1427, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<6>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<6>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<34>
connect d_clr_1, UInt<34>(0h0)
wire d_clr_wo_ready_1 : UInt<34>
connect d_clr_wo_ready_1, UInt<34>(0h0)
wire d_opcodes_clr_1 : UInt<136>
connect d_opcodes_clr_1, UInt<136>(0h0)
wire d_sizes_clr_1 : UInt<272>
connect d_sizes_clr_1, UInt<272>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1431 = and(io.in.d.valid, d_first_2)
node _T_1432 = and(_T_1431, UInt<1>(0h1))
node _T_1433 = and(_T_1432, d_release_ack_1)
when _T_1433 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1434 = and(io.in.d.ready, io.in.d.valid)
node _T_1435 = and(_T_1434, d_first_2)
node _T_1436 = and(_T_1435, UInt<1>(0h1))
node _T_1437 = and(_T_1436, d_release_ack_1)
when _T_1437 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1438 = and(io.in.d.valid, d_first_2)
node _T_1439 = and(_T_1438, UInt<1>(0h1))
node _T_1440 = and(_T_1439, d_release_ack_1)
when _T_1440 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<6>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<6>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<6>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1441 = dshr(inflight_1, io.in.d.bits.source)
node _T_1442 = bits(_T_1441, 0, 0)
node _T_1443 = or(_T_1442, same_cycle_resp_1)
node _T_1444 = asUInt(reset)
node _T_1445 = eq(_T_1444, UInt<1>(0h0))
when _T_1445 :
node _T_1446 = eq(_T_1443, UInt<1>(0h0))
when _T_1446 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1443, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<32>(0h0)
connect _WIRE_16.bits.address, UInt<29>(0h0)
connect _WIRE_16.bits.source, UInt<6>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1447 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1448 = asUInt(reset)
node _T_1449 = eq(_T_1448, UInt<1>(0h0))
when _T_1449 :
node _T_1450 = eq(_T_1447, UInt<1>(0h0))
when _T_1450 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1447, UInt<1>(0h1), "") : assert_109
else :
node _T_1451 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1452 = asUInt(reset)
node _T_1453 = eq(_T_1452, UInt<1>(0h0))
when _T_1453 :
node _T_1454 = eq(_T_1451, UInt<1>(0h0))
when _T_1454 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1451, UInt<1>(0h1), "") : assert_110
node _T_1455 = and(io.in.d.valid, d_first_2)
node _T_1456 = and(_T_1455, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<32>(0h0)
connect _WIRE_18.bits.address, UInt<29>(0h0)
connect _WIRE_18.bits.source, UInt<6>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1457 = and(_T_1456, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<32>(0h0)
connect _WIRE_20.bits.address, UInt<29>(0h0)
connect _WIRE_20.bits.source, UInt<6>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1458 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1459 = and(_T_1457, _T_1458)
node _T_1460 = and(_T_1459, d_release_ack_1)
node _T_1461 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1462 = and(_T_1460, _T_1461)
when _T_1462 :
node _T_1463 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<32>(0h0)
connect _WIRE_22.bits.address, UInt<29>(0h0)
connect _WIRE_22.bits.source, UInt<6>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1464 = or(_T_1463, _WIRE_23.ready)
node _T_1465 = asUInt(reset)
node _T_1466 = eq(_T_1465, UInt<1>(0h0))
when _T_1466 :
node _T_1467 = eq(_T_1464, UInt<1>(0h0))
when _T_1467 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1464, UInt<1>(0h1), "") : assert_111
node _T_1468 = orr(c_set_wo_ready)
when _T_1468 :
node _T_1469 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1470 = asUInt(reset)
node _T_1471 = eq(_T_1470, UInt<1>(0h0))
when _T_1471 :
node _T_1472 = eq(_T_1469, UInt<1>(0h0))
when _T_1472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1469, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_5
node _T_1473 = orr(inflight_1)
node _T_1474 = eq(_T_1473, UInt<1>(0h0))
node _T_1475 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1476 = or(_T_1474, _T_1475)
node _T_1477 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1478 = or(_T_1476, _T_1477)
node _T_1479 = asUInt(reset)
node _T_1480 = eq(_T_1479, UInt<1>(0h0))
when _T_1480 :
node _T_1481 = eq(_T_1478, UInt<1>(0h0))
when _T_1481 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1478, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<32>(0h0)
connect _WIRE_24.bits.address, UInt<29>(0h0)
connect _WIRE_24.bits.source, UInt<6>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1482 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1483 = and(io.in.d.ready, io.in.d.valid)
node _T_1484 = or(_T_1482, _T_1483)
when _T_1484 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_2( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [31:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [5:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [9:0] c_first_beats1_decode = 10'h0; // @[Edges.scala:220:59]
wire [9:0] c_first_beats1 = 10'h0; // @[Edges.scala:221:14]
wire [9:0] _c_first_count_T = 10'h0; // @[Edges.scala:234:27]
wire [9:0] c_first_count = 10'h0; // @[Edges.scala:234:25]
wire [9:0] _c_first_counter_T = 10'h0; // @[Edges.scala:236:21]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [9:0] c_first_counter1 = 10'h3FF; // @[Edges.scala:230:28]
wire [10:0] _c_first_counter1_T = 11'h7FF; // @[Edges.scala:230:28]
wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_first_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_first_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_first_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_first_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_set_wo_ready_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_set_wo_ready_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_opcodes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_opcodes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_sizes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_sizes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_opcodes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_opcodes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_sizes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_sizes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_probe_ack_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_probe_ack_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_probe_ack_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_probe_ack_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _same_cycle_resp_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _same_cycle_resp_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _same_cycle_resp_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _same_cycle_resp_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _same_cycle_resp_WIRE_4_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _same_cycle_resp_WIRE_5_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [515:0] _c_sizes_set_T_1 = 516'h0; // @[Monitor.scala:768:52]
wire [8:0] _c_opcodes_set_T = 9'h0; // @[Monitor.scala:767:79]
wire [8:0] _c_sizes_set_T = 9'h0; // @[Monitor.scala:768:77]
wire [514:0] _c_opcodes_set_T_1 = 515'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [63:0] _c_set_wo_ready_T = 64'h1; // @[OneHot.scala:58:35]
wire [63:0] _c_set_T = 64'h1; // @[OneHot.scala:58:35]
wire [271:0] c_sizes_set = 272'h0; // @[Monitor.scala:741:34]
wire [135:0] c_opcodes_set = 136'h0; // @[Monitor.scala:740:34]
wire [33:0] c_set = 34'h0; // @[Monitor.scala:738:34]
wire [33:0] c_set_wo_ready = 34'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [5:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 6'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_1 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_7 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_13 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_19 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 4'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 4'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_a_bits_source_0 == 6'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire _source_ok_T_26 = io_in_a_bits_source_0 == 6'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31]
wire _source_ok_T_27 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_28 = _source_ok_T_27 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_29 = _source_ok_T_28 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_31 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}]
wire mask_sizeOH_shiftAmount = _mask_sizeOH_T[0]; // @[OneHot.scala:64:49]
wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [1:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}]
wire [1:0] mask_sizeOH = {_mask_sizeOH_T_2[1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_0_1 = |(io_in_a_bits_size_0[3:1]); // @[Misc.scala:206:21]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_32 = io_in_d_bits_source_0 == 6'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_32; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_33 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_39 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_45 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_51 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_34 = _source_ok_T_33 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_40 = _source_ok_T_39 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_44; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_46 = _source_ok_T_45 == 4'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_50; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_52 = _source_ok_T_51 == 4'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_56; // @[Parameters.scala:1138:31]
wire _source_ok_T_57 = io_in_d_bits_source_0 == 6'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_5 = _source_ok_T_57; // @[Parameters.scala:1138:31]
wire _source_ok_T_58 = io_in_d_bits_source_0 == 6'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_58; // @[Parameters.scala:1138:31]
wire _source_ok_T_59 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_60 = _source_ok_T_59 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_61 = _source_ok_T_60 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_62 = _source_ok_T_61 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_63 = _source_ok_T_62 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_63 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1411 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1411; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1411; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [9:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:2]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [9:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 10'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [9:0] a_first_counter; // @[Edges.scala:229:27]
wire [10:0] _a_first_counter1_T = {1'h0, a_first_counter} - 11'h1; // @[Edges.scala:229:27, :230:28]
wire [9:0] a_first_counter1 = _a_first_counter1_T[9:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 10'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 10'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 10'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [9:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [9:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [9:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [5:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
wire _T_1484 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1484; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1484; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1484; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [9:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:2]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [9:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 10'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [9:0] d_first_counter; // @[Edges.scala:229:27]
wire [10:0] _d_first_counter1_T = {1'h0, d_first_counter} - 11'h1; // @[Edges.scala:229:27, :230:28]
wire [9:0] d_first_counter1 = _d_first_counter1_T[9:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 10'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 10'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 10'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [9:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [9:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [9:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [5:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [33:0] inflight; // @[Monitor.scala:614:27]
reg [135:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [271:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [9:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:2]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [9:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 10'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [9:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [10:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 11'h1; // @[Edges.scala:229:27, :230:28]
wire [9:0] a_first_counter1_1 = _a_first_counter1_T_1[9:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 10'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 10'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 10'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [9:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [9:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [9:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [9:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:2]; // @[package.scala:243:46]
wire [9:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 10'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [9:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [10:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 11'h1; // @[Edges.scala:229:27, :230:28]
wire [9:0] d_first_counter1_1 = _d_first_counter1_T_1[9:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 10'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 10'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 10'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [9:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [9:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [9:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [33:0] a_set; // @[Monitor.scala:626:34]
wire [33:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [135:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [271:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [8:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [8:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [8:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [8:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [8:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [135:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [135:0] _a_opcode_lookup_T_6 = {132'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [135:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[135:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [8:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [8:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [8:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [8:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [8:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [271:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [271:0] _a_size_lookup_T_6 = {264'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [271:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[271:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [63:0] _GEN_3 = 64'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [63:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [63:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[33:0] : 34'h0; // @[OneHot.scala:58:35]
wire _T_1337 = _T_1411 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1337 ? _a_set_T[33:0] : 34'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1337 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1337 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [8:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [514:0] _a_opcodes_set_T_1 = {511'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1337 ? _a_opcodes_set_T_1[135:0] : 136'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [8:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [515:0] _a_sizes_set_T_1 = {511'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1337 ? _a_sizes_set_T_1[271:0] : 272'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [33:0] d_clr; // @[Monitor.scala:664:34]
wire [33:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [135:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [271:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1383 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [63:0] _GEN_5 = 64'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1383 & ~d_release_ack ? _d_clr_wo_ready_T[33:0] : 34'h0; // @[OneHot.scala:58:35]
wire _T_1352 = _T_1484 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1352 ? _d_clr_T[33:0] : 34'h0; // @[OneHot.scala:58:35]
wire [526:0] _d_opcodes_clr_T_5 = 527'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1352 ? _d_opcodes_clr_T_5[135:0] : 136'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [526:0] _d_sizes_clr_T_5 = 527'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1352 ? _d_sizes_clr_T_5[271:0] : 272'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [33:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [33:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [33:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [135:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [135:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [135:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [271:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [271:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [271:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [33:0] inflight_1; // @[Monitor.scala:726:35]
wire [33:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [135:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [135:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [271:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [271:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [9:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:2]; // @[package.scala:243:46]
wire [9:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 10'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [9:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [10:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 11'h1; // @[Edges.scala:229:27, :230:28]
wire [9:0] d_first_counter1_2 = _d_first_counter1_T_2[9:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 10'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 10'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 10'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [9:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [9:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [9:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [135:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [135:0] _c_opcode_lookup_T_6 = {132'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [135:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[135:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [271:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [271:0] _c_size_lookup_T_6 = {264'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [271:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[271:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [33:0] d_clr_1; // @[Monitor.scala:774:34]
wire [33:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [135:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [271:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1455 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1455 & d_release_ack_1 ? _d_clr_wo_ready_T_1[33:0] : 34'h0; // @[OneHot.scala:58:35]
wire _T_1437 = _T_1484 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1437 ? _d_clr_T_1[33:0] : 34'h0; // @[OneHot.scala:58:35]
wire [526:0] _d_opcodes_clr_T_11 = 527'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1437 ? _d_opcodes_clr_T_11[135:0] : 136'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [526:0] _d_sizes_clr_T_11 = 527'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1437 ? _d_sizes_clr_T_11[271:0] : 272'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 6'h0; // @[Monitor.scala:36:7, :795:113]
wire [33:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [33:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [135:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [135:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [271:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [271:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module CSRFile :
input clock : Clock
input reset : Reset
output io : { flip ungated_clock : Clock, flip interrupts : { debug : UInt<1>, mtip : UInt<1>, msip : UInt<1>, meip : UInt<1>, seip : UInt<1>, lip : UInt<1>[0]}, flip hartid : UInt<1>, rw : { flip addr : UInt<12>, flip cmd : UInt<3>, rdata : UInt<64>, flip wdata : UInt<64>}, decode : { flip inst : UInt<32>, fp_illegal : UInt<1>, vector_illegal : UInt<1>, fp_csr : UInt<1>, vector_csr : UInt<1>, rocc_illegal : UInt<1>, read_illegal : UInt<1>, write_illegal : UInt<1>, write_flush : UInt<1>, system_illegal : UInt<1>, virtual_access_illegal : UInt<1>, virtual_system_illegal : UInt<1>}[3], csr_stall : UInt<1>, rw_stall : UInt<1>, eret : UInt<1>, singleStep : UInt<1>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, evec : UInt<40>, flip exception : UInt<1>, flip retire : UInt<2>, flip cause : UInt<64>, flip pc : UInt<40>, flip tval : UInt<40>, flip htval : UInt<40>, flip mhtinst_read_pseudo : UInt<1>, flip gva : UInt<1>, time : UInt<64>, fcsr_rm : UInt<3>, flip fcsr_flags : { valid : UInt<1>, bits : UInt<5>}, flip set_fs_dirty : UInt<1>, flip rocc_interrupt : UInt<1>, interrupt : UInt<1>, interrupt_cause : UInt<64>, bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}[0], pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], counters : { eventSel : UInt<64>, flip inc : UInt<2>}[2], csrw_counter : UInt<32>, inhibit_cycle : UInt<1>, flip inst : UInt<32>[3], trace : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[3], mcontext : UInt<0>, scontext : UInt<0>, fiom : UInt<1>, customCSRs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4], roccCSRs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[0]}
connect io.rw_stall, UInt<1>(0h0)
wire _reset_mstatus_WIRE : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}
connect _reset_mstatus_WIRE.uie, UInt<1>(0h0)
connect _reset_mstatus_WIRE.sie, UInt<1>(0h0)
connect _reset_mstatus_WIRE.hie, UInt<1>(0h0)
connect _reset_mstatus_WIRE.mie, UInt<1>(0h0)
connect _reset_mstatus_WIRE.upie, UInt<1>(0h0)
connect _reset_mstatus_WIRE.spie, UInt<1>(0h0)
connect _reset_mstatus_WIRE.ube, UInt<1>(0h0)
connect _reset_mstatus_WIRE.mpie, UInt<1>(0h0)
connect _reset_mstatus_WIRE.spp, UInt<1>(0h0)
connect _reset_mstatus_WIRE.vs, UInt<2>(0h0)
connect _reset_mstatus_WIRE.mpp, UInt<2>(0h0)
connect _reset_mstatus_WIRE.fs, UInt<2>(0h0)
connect _reset_mstatus_WIRE.xs, UInt<2>(0h0)
connect _reset_mstatus_WIRE.mprv, UInt<1>(0h0)
connect _reset_mstatus_WIRE.sum, UInt<1>(0h0)
connect _reset_mstatus_WIRE.mxr, UInt<1>(0h0)
connect _reset_mstatus_WIRE.tvm, UInt<1>(0h0)
connect _reset_mstatus_WIRE.tw, UInt<1>(0h0)
connect _reset_mstatus_WIRE.tsr, UInt<1>(0h0)
connect _reset_mstatus_WIRE.zero1, UInt<8>(0h0)
connect _reset_mstatus_WIRE.sd_rv32, UInt<1>(0h0)
connect _reset_mstatus_WIRE.uxl, UInt<2>(0h0)
connect _reset_mstatus_WIRE.sxl, UInt<2>(0h0)
connect _reset_mstatus_WIRE.sbe, UInt<1>(0h0)
connect _reset_mstatus_WIRE.mbe, UInt<1>(0h0)
connect _reset_mstatus_WIRE.gva, UInt<1>(0h0)
connect _reset_mstatus_WIRE.mpv, UInt<1>(0h0)
connect _reset_mstatus_WIRE.zero2, UInt<23>(0h0)
connect _reset_mstatus_WIRE.sd, UInt<1>(0h0)
connect _reset_mstatus_WIRE.v, UInt<1>(0h0)
connect _reset_mstatus_WIRE.prv, UInt<2>(0h0)
connect _reset_mstatus_WIRE.dv, UInt<1>(0h0)
connect _reset_mstatus_WIRE.dprv, UInt<2>(0h0)
connect _reset_mstatus_WIRE.isa, UInt<32>(0h0)
connect _reset_mstatus_WIRE.wfi, UInt<1>(0h0)
connect _reset_mstatus_WIRE.cease, UInt<1>(0h0)
connect _reset_mstatus_WIRE.debug, UInt<1>(0h0)
wire reset_mstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}
connect reset_mstatus, _reset_mstatus_WIRE
connect reset_mstatus.mpp, UInt<2>(0h3)
connect reset_mstatus.prv, UInt<2>(0h3)
connect reset_mstatus.xs, UInt<1>(0h0)
regreset reg_mstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, clock, reset, reset_mstatus
wire new_prv : UInt
connect new_prv, reg_mstatus.prv
node _reg_mstatus_prv_T = eq(new_prv, UInt<2>(0h2))
node _reg_mstatus_prv_T_1 = mux(_reg_mstatus_prv_T, UInt<1>(0h0), new_prv)
connect reg_mstatus.prv, _reg_mstatus_prv_T_1
wire _reset_dcsr_WIRE : { xdebugver : UInt<2>, zero4 : UInt<2>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, v : UInt<1>, zero1 : UInt<2>, step : UInt<1>, prv : UInt<2>}
connect _reset_dcsr_WIRE.prv, UInt<2>(0h0)
connect _reset_dcsr_WIRE.step, UInt<1>(0h0)
connect _reset_dcsr_WIRE.zero1, UInt<2>(0h0)
connect _reset_dcsr_WIRE.v, UInt<1>(0h0)
connect _reset_dcsr_WIRE.cause, UInt<3>(0h0)
connect _reset_dcsr_WIRE.stoptime, UInt<1>(0h0)
connect _reset_dcsr_WIRE.stopcycle, UInt<1>(0h0)
connect _reset_dcsr_WIRE.zero2, UInt<1>(0h0)
connect _reset_dcsr_WIRE.ebreaku, UInt<1>(0h0)
connect _reset_dcsr_WIRE.ebreaks, UInt<1>(0h0)
connect _reset_dcsr_WIRE.ebreakh, UInt<1>(0h0)
connect _reset_dcsr_WIRE.ebreakm, UInt<1>(0h0)
connect _reset_dcsr_WIRE.zero3, UInt<12>(0h0)
connect _reset_dcsr_WIRE.zero4, UInt<2>(0h0)
connect _reset_dcsr_WIRE.xdebugver, UInt<2>(0h0)
wire reset_dcsr : { xdebugver : UInt<2>, zero4 : UInt<2>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, v : UInt<1>, zero1 : UInt<2>, step : UInt<1>, prv : UInt<2>}
connect reset_dcsr, _reset_dcsr_WIRE
connect reset_dcsr.xdebugver, UInt<1>(0h1)
connect reset_dcsr.prv, UInt<2>(0h3)
regreset reg_dcsr : { xdebugver : UInt<2>, zero4 : UInt<2>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, v : UInt<1>, zero1 : UInt<2>, step : UInt<1>, prv : UInt<2>}, clock, reset, reset_dcsr
wire sup : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
connect sup.usip, UInt<1>(0h0)
connect sup.ssip, UInt<1>(0h1)
connect sup.vssip, UInt<1>(0h0)
connect sup.msip, UInt<1>(0h1)
connect sup.utip, UInt<1>(0h0)
connect sup.stip, UInt<1>(0h1)
connect sup.vstip, UInt<1>(0h0)
connect sup.mtip, UInt<1>(0h1)
connect sup.ueip, UInt<1>(0h0)
connect sup.seip, UInt<1>(0h1)
connect sup.vseip, UInt<1>(0h0)
connect sup.meip, UInt<1>(0h1)
connect sup.sgeip, UInt<1>(0h0)
connect sup.rocc, UInt<1>(0h0)
connect sup.debug, UInt<1>(0h0)
connect sup.zero1, UInt<1>(0h0)
wire del : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
connect del, sup
connect del.msip, UInt<1>(0h0)
connect del.mtip, UInt<1>(0h0)
connect del.meip, UInt<1>(0h0)
node lo_lo_lo = cat(sup.ssip, sup.usip)
node lo_lo_hi = cat(sup.msip, sup.vssip)
node lo_lo = cat(lo_lo_hi, lo_lo_lo)
node lo_hi_lo = cat(sup.stip, sup.utip)
node lo_hi_hi = cat(sup.mtip, sup.vstip)
node lo_hi = cat(lo_hi_hi, lo_hi_lo)
node lo = cat(lo_hi, lo_lo)
node hi_lo_lo = cat(sup.seip, sup.ueip)
node hi_lo_hi = cat(sup.meip, sup.vseip)
node hi_lo = cat(hi_lo_hi, hi_lo_lo)
node hi_hi_lo = cat(sup.rocc, sup.sgeip)
node hi_hi_hi_hi = cat(UInt<0>(0h0), sup.zero1)
node hi_hi_hi = cat(hi_hi_hi_hi, sup.debug)
node hi_hi = cat(hi_hi_hi, hi_hi_lo)
node hi = cat(hi_hi, hi_lo)
node _T = cat(hi, lo)
node supported_interrupts = or(_T, UInt<1>(0h0))
node lo_lo_lo_1 = cat(del.ssip, del.usip)
node lo_lo_hi_1 = cat(del.msip, del.vssip)
node lo_lo_1 = cat(lo_lo_hi_1, lo_lo_lo_1)
node lo_hi_lo_1 = cat(del.stip, del.utip)
node lo_hi_hi_1 = cat(del.mtip, del.vstip)
node lo_hi_1 = cat(lo_hi_hi_1, lo_hi_lo_1)
node lo_1 = cat(lo_hi_1, lo_lo_1)
node hi_lo_lo_1 = cat(del.seip, del.ueip)
node hi_lo_hi_1 = cat(del.meip, del.vseip)
node hi_lo_1 = cat(hi_lo_hi_1, hi_lo_lo_1)
node hi_hi_lo_1 = cat(del.rocc, del.sgeip)
node hi_hi_hi_hi_1 = cat(UInt<0>(0h0), del.zero1)
node hi_hi_hi_1 = cat(hi_hi_hi_hi_1, del.debug)
node hi_hi_1 = cat(hi_hi_hi_1, hi_hi_lo_1)
node hi_1 = cat(hi_hi_1, hi_lo_1)
node delegable_interrupts = cat(hi_1, lo_1)
wire _always_WIRE : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
connect _always_WIRE.usip, UInt<1>(0h0)
connect _always_WIRE.ssip, UInt<1>(0h0)
connect _always_WIRE.vssip, UInt<1>(0h0)
connect _always_WIRE.msip, UInt<1>(0h0)
connect _always_WIRE.utip, UInt<1>(0h0)
connect _always_WIRE.stip, UInt<1>(0h0)
connect _always_WIRE.vstip, UInt<1>(0h0)
connect _always_WIRE.mtip, UInt<1>(0h0)
connect _always_WIRE.ueip, UInt<1>(0h0)
connect _always_WIRE.seip, UInt<1>(0h0)
connect _always_WIRE.vseip, UInt<1>(0h0)
connect _always_WIRE.meip, UInt<1>(0h0)
connect _always_WIRE.sgeip, UInt<1>(0h0)
connect _always_WIRE.rocc, UInt<1>(0h0)
connect _always_WIRE.debug, UInt<1>(0h0)
connect _always_WIRE.zero1, UInt<1>(0h0)
wire always : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
connect always, _always_WIRE
connect always.vssip, UInt<1>(0h0)
connect always.vstip, UInt<1>(0h0)
connect always.vseip, UInt<1>(0h0)
wire deleg : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
connect deleg, always
node lo_lo_lo_2 = cat(deleg.ssip, deleg.usip)
node lo_lo_hi_2 = cat(deleg.msip, deleg.vssip)
node lo_lo_2 = cat(lo_lo_hi_2, lo_lo_lo_2)
node lo_hi_lo_2 = cat(deleg.stip, deleg.utip)
node lo_hi_hi_2 = cat(deleg.mtip, deleg.vstip)
node lo_hi_2 = cat(lo_hi_hi_2, lo_hi_lo_2)
node lo_2 = cat(lo_hi_2, lo_lo_2)
node hi_lo_lo_2 = cat(deleg.seip, deleg.ueip)
node hi_lo_hi_2 = cat(deleg.meip, deleg.vseip)
node hi_lo_2 = cat(hi_lo_hi_2, hi_lo_lo_2)
node hi_hi_lo_2 = cat(deleg.rocc, deleg.sgeip)
node hi_hi_hi_hi_2 = cat(UInt<0>(0h0), deleg.zero1)
node hi_hi_hi_2 = cat(hi_hi_hi_hi_2, deleg.debug)
node hi_hi_2 = cat(hi_hi_hi_2, hi_hi_lo_2)
node hi_2 = cat(hi_hi_2, hi_lo_2)
node hs_delegable_interrupts = cat(hi_2, lo_2)
node lo_lo_lo_3 = cat(always.ssip, always.usip)
node lo_lo_hi_3 = cat(always.msip, always.vssip)
node lo_lo_3 = cat(lo_lo_hi_3, lo_lo_lo_3)
node lo_hi_lo_3 = cat(always.stip, always.utip)
node lo_hi_hi_3 = cat(always.mtip, always.vstip)
node lo_hi_3 = cat(lo_hi_hi_3, lo_hi_lo_3)
node lo_3 = cat(lo_hi_3, lo_lo_3)
node hi_lo_lo_3 = cat(always.seip, always.ueip)
node hi_lo_hi_3 = cat(always.meip, always.vseip)
node hi_lo_3 = cat(hi_lo_hi_3, hi_lo_lo_3)
node hi_hi_lo_3 = cat(always.rocc, always.sgeip)
node hi_hi_hi_hi_3 = cat(UInt<0>(0h0), always.zero1)
node hi_hi_hi_3 = cat(hi_hi_hi_hi_3, always.debug)
node hi_hi_3 = cat(hi_hi_hi_3, hi_hi_lo_3)
node hi_3 = cat(hi_hi_3, hi_lo_3)
node mideleg_always_hs = cat(hi_3, lo_3)
regreset reg_debug : UInt<1>, clock, reset, UInt<1>(0h0)
reg reg_dpc : UInt<40>, clock
reg reg_dscratch0 : UInt<64>, clock
reg reg_singleStepped : UInt<1>, clock
reg reg_tselect : UInt<1>, clock
reg reg_bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}[2], clock
reg reg_pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>}[8], clock
reg reg_mie : UInt<64>, clock
reg reg_mideleg : UInt<64>, clock
node _T_1 = and(reg_mideleg, delegable_interrupts)
node _T_2 = or(_T_1, mideleg_always_hs)
node read_mideleg = mux(UInt<1>(0h1), _T_2, UInt<1>(0h0))
reg reg_medeleg : UInt<64>, clock
node _T_3 = and(reg_medeleg, UInt<16>(0hb15d))
node read_medeleg = mux(UInt<1>(0h1), _T_3, UInt<1>(0h0))
reg reg_mip : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}, clock
reg reg_mepc : UInt<40>, clock
regreset reg_mcause : UInt<64>, clock, reset, UInt<64>(0h0)
reg reg_mtval : UInt<40>, clock
reg reg_mtval2 : UInt<40>, clock
reg reg_mscratch : UInt<64>, clock
regreset reg_mtvec : UInt<32>, clock, reset, UInt<32>(0h0)
wire _reset_mnstatus_WIRE : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>}
connect _reset_mnstatus_WIRE.zero1, UInt<3>(0h0)
connect _reset_mnstatus_WIRE.mie, UInt<1>(0h0)
connect _reset_mnstatus_WIRE.zero2, UInt<3>(0h0)
connect _reset_mnstatus_WIRE.mpv, UInt<1>(0h0)
connect _reset_mnstatus_WIRE.zero3, UInt<3>(0h0)
connect _reset_mnstatus_WIRE.mpp, UInt<2>(0h0)
wire reset_mnstatus : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>}
connect reset_mnstatus, _reset_mnstatus_WIRE
connect reset_mnstatus.mpp, UInt<2>(0h3)
reg reg_mnscratch : UInt<64>, clock
reg reg_mnepc : UInt<40>, clock
regreset reg_mncause : UInt<64>, clock, reset, UInt<64>(0h0)
regreset reg_mnstatus : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>}, clock, reset, reset_mnstatus
regreset reg_rnmie : UInt<1>, clock, reset, UInt<1>(0h1)
wire _reg_menvcfg_WIRE : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>}
connect _reg_menvcfg_WIRE.fiom, UInt<1>(0h0)
connect _reg_menvcfg_WIRE.zero3, UInt<3>(0h0)
connect _reg_menvcfg_WIRE.cbie, UInt<2>(0h0)
connect _reg_menvcfg_WIRE.cbcfe, UInt<1>(0h0)
connect _reg_menvcfg_WIRE.cbze, UInt<1>(0h0)
connect _reg_menvcfg_WIRE.zero54, UInt<54>(0h0)
connect _reg_menvcfg_WIRE.pbmte, UInt<1>(0h0)
connect _reg_menvcfg_WIRE.stce, UInt<1>(0h0)
regreset reg_menvcfg : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>}, clock, reset, _reg_menvcfg_WIRE
wire _reg_senvcfg_WIRE : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>}
connect _reg_senvcfg_WIRE.fiom, UInt<1>(0h0)
connect _reg_senvcfg_WIRE.zero3, UInt<3>(0h0)
connect _reg_senvcfg_WIRE.cbie, UInt<2>(0h0)
connect _reg_senvcfg_WIRE.cbcfe, UInt<1>(0h0)
connect _reg_senvcfg_WIRE.cbze, UInt<1>(0h0)
connect _reg_senvcfg_WIRE.zero54, UInt<54>(0h0)
connect _reg_senvcfg_WIRE.pbmte, UInt<1>(0h0)
connect _reg_senvcfg_WIRE.stce, UInt<1>(0h0)
regreset reg_senvcfg : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>}, clock, reset, _reg_senvcfg_WIRE
wire _reg_henvcfg_WIRE : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>}
connect _reg_henvcfg_WIRE.fiom, UInt<1>(0h0)
connect _reg_henvcfg_WIRE.zero3, UInt<3>(0h0)
connect _reg_henvcfg_WIRE.cbie, UInt<2>(0h0)
connect _reg_henvcfg_WIRE.cbcfe, UInt<1>(0h0)
connect _reg_henvcfg_WIRE.cbze, UInt<1>(0h0)
connect _reg_henvcfg_WIRE.zero54, UInt<54>(0h0)
connect _reg_henvcfg_WIRE.pbmte, UInt<1>(0h0)
connect _reg_henvcfg_WIRE.stce, UInt<1>(0h0)
regreset reg_henvcfg : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>}, clock, reset, _reg_henvcfg_WIRE
reg reg_mcounteren : UInt<32>, clock
node _T_4 = and(reg_mcounteren, UInt<5>(0h1f))
node read_mcounteren = mux(UInt<1>(0h1), _T_4, UInt<1>(0h0))
reg reg_scounteren : UInt<32>, clock
node _T_5 = and(reg_scounteren, UInt<5>(0h1f))
node read_scounteren = mux(UInt<1>(0h1), _T_5, UInt<1>(0h0))
reg reg_hideleg : UInt<64>, clock
node _T_6 = and(reg_hideleg, hs_delegable_interrupts)
node read_hideleg = mux(UInt<1>(0h0), _T_6, UInt<1>(0h0))
reg reg_hedeleg : UInt<64>, clock
node _T_7 = and(reg_hedeleg, UInt<16>(0hb1ff))
node read_hedeleg = mux(UInt<1>(0h0), _T_7, UInt<1>(0h0))
reg reg_hcounteren : UInt<32>, clock
node _T_8 = and(reg_hcounteren, UInt<5>(0h1f))
node read_hcounteren = mux(UInt<1>(0h0), _T_8, UInt<1>(0h0))
wire _reg_hstatus_WIRE : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}
connect _reg_hstatus_WIRE.zero1, UInt<5>(0h0)
connect _reg_hstatus_WIRE.vsbe, UInt<1>(0h0)
connect _reg_hstatus_WIRE.gva, UInt<1>(0h0)
connect _reg_hstatus_WIRE.spv, UInt<1>(0h0)
connect _reg_hstatus_WIRE.spvp, UInt<1>(0h0)
connect _reg_hstatus_WIRE.hu, UInt<1>(0h0)
connect _reg_hstatus_WIRE.zero2, UInt<2>(0h0)
connect _reg_hstatus_WIRE.vgein, UInt<6>(0h0)
connect _reg_hstatus_WIRE.zero3, UInt<2>(0h0)
connect _reg_hstatus_WIRE.vtvm, UInt<1>(0h0)
connect _reg_hstatus_WIRE.vtw, UInt<1>(0h0)
connect _reg_hstatus_WIRE.vtsr, UInt<1>(0h0)
connect _reg_hstatus_WIRE.zero5, UInt<9>(0h0)
connect _reg_hstatus_WIRE.vsxl, UInt<2>(0h0)
connect _reg_hstatus_WIRE.zero6, UInt<30>(0h0)
regreset reg_hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, clock, reset, _reg_hstatus_WIRE
reg reg_hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, clock
reg reg_htval : UInt<40>, clock
node read_hvip_lo_lo_lo = cat(reg_mip.ssip, reg_mip.usip)
node read_hvip_lo_lo_hi = cat(reg_mip.msip, reg_mip.vssip)
node read_hvip_lo_lo = cat(read_hvip_lo_lo_hi, read_hvip_lo_lo_lo)
node read_hvip_lo_hi_lo = cat(reg_mip.stip, reg_mip.utip)
node read_hvip_lo_hi_hi = cat(reg_mip.mtip, reg_mip.vstip)
node read_hvip_lo_hi = cat(read_hvip_lo_hi_hi, read_hvip_lo_hi_lo)
node read_hvip_lo = cat(read_hvip_lo_hi, read_hvip_lo_lo)
node read_hvip_hi_lo_lo = cat(reg_mip.seip, reg_mip.ueip)
node read_hvip_hi_lo_hi = cat(reg_mip.meip, reg_mip.vseip)
node read_hvip_hi_lo = cat(read_hvip_hi_lo_hi, read_hvip_hi_lo_lo)
node read_hvip_hi_hi_lo = cat(reg_mip.rocc, reg_mip.sgeip)
node read_hvip_hi_hi_hi_hi = cat(UInt<0>(0h0), reg_mip.zero1)
node read_hvip_hi_hi_hi = cat(read_hvip_hi_hi_hi_hi, reg_mip.debug)
node read_hvip_hi_hi = cat(read_hvip_hi_hi_hi, read_hvip_hi_hi_lo)
node read_hvip_hi = cat(read_hvip_hi_hi, read_hvip_hi_lo)
node _read_hvip_T = cat(read_hvip_hi, read_hvip_lo)
node read_hvip = and(_read_hvip_T, hs_delegable_interrupts)
node read_hie = and(reg_mie, hs_delegable_interrupts)
reg reg_vstvec : UInt<40>, clock
node _T_9 = bits(reg_vstvec, 0, 0)
node _T_10 = mux(_T_9, UInt<8>(0hfe), UInt<2>(0h2))
node _T_11 = and(reg_vstvec, UInt<1>(0h0))
node _T_12 = or(_T_10, _T_11)
node _T_13 = not(_T_12)
node _T_14 = and(reg_vstvec, _T_13)
node _T_15 = bits(_T_14, 39, 39)
node _T_16 = mux(_T_15, UInt<24>(0hffffff), UInt<24>(0h0))
node read_vstvec = cat(_T_16, _T_14)
reg reg_vsstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, clock
reg reg_vsscratch : UInt<64>, clock
reg reg_vsepc : UInt<40>, clock
reg reg_vscause : UInt<64>, clock
reg reg_vstval : UInt<40>, clock
reg reg_vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, clock
reg reg_sepc : UInt<40>, clock
reg reg_scause : UInt<64>, clock
reg reg_stval : UInt<40>, clock
reg reg_sscratch : UInt<64>, clock
reg reg_stvec : UInt<39>, clock
reg reg_satp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, clock
regreset reg_wfi : UInt<1>, io.ungated_clock, reset, UInt<1>(0h0)
reg reg_fflags : UInt<5>, clock
reg reg_frm : UInt<3>, clock
reg reg_mtinst_read_pseudo : UInt<1>, clock
reg reg_htinst_read_pseudo : UInt<1>, clock
node hi_4 = cat(reg_mtinst_read_pseudo, reg_mtinst_read_pseudo)
node read_mtinst = cat(hi_4, UInt<12>(0h0))
node hi_5 = cat(reg_htinst_read_pseudo, reg_htinst_read_pseudo)
node read_htinst = cat(hi_5, UInt<12>(0h0))
regreset reg_mcountinhibit : UInt<5>, clock, reset, UInt<5>(0h0)
node _io_inhibit_cycle_T = bits(reg_mcountinhibit, 0, 0)
connect io.inhibit_cycle, _io_inhibit_cycle_T
node x3 = bits(reg_mcountinhibit, 2, 2)
regreset small : UInt<6>, clock, reset, UInt<6>(0h0)
node nextSmall = add(small, io.retire)
node _T_17 = eq(x3, UInt<1>(0h0))
when _T_17 :
connect small, nextSmall
regreset large : UInt<58>, clock, reset, UInt<58>(0h0)
node _large_T = bits(nextSmall, 6, 6)
node _large_T_1 = eq(x3, UInt<1>(0h0))
node _large_T_2 = and(_large_T, _large_T_1)
when _large_T_2 :
node _large_r_T = add(large, UInt<1>(0h1))
node _large_r_T_1 = tail(_large_r_T, 1)
connect large, _large_r_T_1
node value = cat(large, small)
node x10 = eq(io.csr_stall, UInt<1>(0h0))
node x11 = bits(reg_mcountinhibit, 0, 0)
regreset small_1 : UInt<6>, io.ungated_clock, reset, UInt<6>(0h0)
node nextSmall_1 = add(small_1, x10)
node _T_18 = eq(x11, UInt<1>(0h0))
when _T_18 :
connect small_1, nextSmall_1
regreset large_1 : UInt<58>, io.ungated_clock, reset, UInt<58>(0h0)
node _large_T_3 = bits(nextSmall_1, 6, 6)
node _large_T_4 = eq(x11, UInt<1>(0h0))
node _large_T_5 = and(_large_T_3, _large_T_4)
when _large_T_5 :
node _large_r_T_2 = add(large_1, UInt<1>(0h1))
node _large_r_T_3 = tail(_large_r_T_2, 1)
connect large_1, _large_r_T_3
node value_1 = cat(large_1, small_1)
regreset reg_hpmevent_0 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset reg_hpmevent_1 : UInt<64>, clock, reset, UInt<64>(0h0)
connect io.counters[0].eventSel, reg_hpmevent_0
connect io.counters[1].eventSel, reg_hpmevent_1
node _T_19 = bits(reg_mcountinhibit, 3, 3)
reg small_2 : UInt<6>, clock
node nextSmall_2 = add(small_2, io.counters[0].inc)
node _T_20 = eq(_T_19, UInt<1>(0h0))
when _T_20 :
connect small_2, nextSmall_2
reg large_2 : UInt<34>, clock
node _large_T_6 = bits(nextSmall_2, 6, 6)
node _large_T_7 = eq(_T_19, UInt<1>(0h0))
node _large_T_8 = and(_large_T_6, _large_T_7)
when _large_T_8 :
node _large_r_T_4 = add(large_2, UInt<1>(0h1))
node _large_r_T_5 = tail(_large_r_T_4, 1)
connect large_2, _large_r_T_5
node value_2 = cat(large_2, small_2)
node _T_21 = bits(reg_mcountinhibit, 4, 4)
reg small_3 : UInt<6>, clock
node nextSmall_3 = add(small_3, io.counters[1].inc)
node _T_22 = eq(_T_21, UInt<1>(0h0))
when _T_22 :
connect small_3, nextSmall_3
reg large_3 : UInt<34>, clock
node _large_T_9 = bits(nextSmall_3, 6, 6)
node _large_T_10 = eq(_T_21, UInt<1>(0h0))
node _large_T_11 = and(_large_T_9, _large_T_10)
when _large_T_11 :
node _large_r_T_6 = add(large_3, UInt<1>(0h1))
node _large_r_T_7 = tail(_large_r_T_6, 1)
connect large_3, _large_r_T_7
node value_3 = cat(large_3, small_3)
wire mip : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
connect mip, reg_mip
connect mip.mtip, io.interrupts.mtip
connect mip.msip, io.interrupts.msip
connect mip.meip, io.interrupts.meip
node _mip_seip_T = or(reg_mip.seip, io.interrupts.seip)
connect mip.seip, _mip_seip_T
connect mip.rocc, io.rocc_interrupt
node read_mip_lo_lo_lo = cat(mip.ssip, mip.usip)
node read_mip_lo_lo_hi = cat(mip.msip, mip.vssip)
node read_mip_lo_lo = cat(read_mip_lo_lo_hi, read_mip_lo_lo_lo)
node read_mip_lo_hi_lo = cat(mip.stip, mip.utip)
node read_mip_lo_hi_hi = cat(mip.mtip, mip.vstip)
node read_mip_lo_hi = cat(read_mip_lo_hi_hi, read_mip_lo_hi_lo)
node read_mip_lo = cat(read_mip_lo_hi, read_mip_lo_lo)
node read_mip_hi_lo_lo = cat(mip.seip, mip.ueip)
node read_mip_hi_lo_hi = cat(mip.meip, mip.vseip)
node read_mip_hi_lo = cat(read_mip_hi_lo_hi, read_mip_hi_lo_lo)
node read_mip_hi_hi_lo = cat(mip.rocc, mip.sgeip)
node read_mip_hi_hi_hi_hi = cat(UInt<0>(0h0), mip.zero1)
node read_mip_hi_hi_hi = cat(read_mip_hi_hi_hi_hi, mip.debug)
node read_mip_hi_hi = cat(read_mip_hi_hi_hi, read_mip_hi_hi_lo)
node read_mip_hi = cat(read_mip_hi_hi, read_mip_hi_lo)
node _read_mip_T = cat(read_mip_hi, read_mip_lo)
node read_mip = and(_read_mip_T, supported_interrupts)
node read_hip = and(read_mip, hs_delegable_interrupts)
node _pending_interrupts_T = and(read_mip, reg_mie)
node pending_interrupts = or(UInt<1>(0h0), _pending_interrupts_T)
node d_interrupts = shl(io.interrupts.debug, 14)
node _m_interrupts_T = leq(reg_mstatus.prv, UInt<1>(0h1))
node _m_interrupts_T_1 = or(_m_interrupts_T, reg_mstatus.mie)
node _m_interrupts_T_2 = and(reg_rnmie, _m_interrupts_T_1)
node _m_interrupts_T_3 = not(pending_interrupts)
node _m_interrupts_T_4 = or(_m_interrupts_T_3, read_mideleg)
node _m_interrupts_T_5 = not(_m_interrupts_T_4)
node m_interrupts = mux(_m_interrupts_T_2, _m_interrupts_T_5, UInt<1>(0h0))
node _s_interrupts_T = lt(reg_mstatus.prv, UInt<1>(0h1))
node _s_interrupts_T_1 = or(reg_mstatus.v, _s_interrupts_T)
node _s_interrupts_T_2 = eq(reg_mstatus.prv, UInt<1>(0h1))
node _s_interrupts_T_3 = and(_s_interrupts_T_2, reg_mstatus.sie)
node _s_interrupts_T_4 = or(_s_interrupts_T_1, _s_interrupts_T_3)
node _s_interrupts_T_5 = and(reg_rnmie, _s_interrupts_T_4)
node _s_interrupts_T_6 = and(pending_interrupts, read_mideleg)
node _s_interrupts_T_7 = not(read_hideleg)
node _s_interrupts_T_8 = and(_s_interrupts_T_6, _s_interrupts_T_7)
node s_interrupts = mux(_s_interrupts_T_5, _s_interrupts_T_8, UInt<1>(0h0))
node _vs_interrupts_T = lt(reg_mstatus.prv, UInt<1>(0h1))
node _vs_interrupts_T_1 = eq(reg_mstatus.prv, UInt<1>(0h1))
node _vs_interrupts_T_2 = and(_vs_interrupts_T_1, reg_vsstatus.sie)
node _vs_interrupts_T_3 = or(_vs_interrupts_T, _vs_interrupts_T_2)
node _vs_interrupts_T_4 = and(reg_mstatus.v, _vs_interrupts_T_3)
node _vs_interrupts_T_5 = and(reg_rnmie, _vs_interrupts_T_4)
node _vs_interrupts_T_6 = and(pending_interrupts, read_hideleg)
node vs_interrupts = mux(_vs_interrupts_T_5, _vs_interrupts_T_6, UInt<1>(0h0))
node _any_T = bits(d_interrupts, 14, 14)
node _any_T_1 = bits(d_interrupts, 13, 13)
node _any_T_2 = bits(d_interrupts, 12, 12)
node _any_T_3 = bits(d_interrupts, 11, 11)
node _any_T_4 = bits(d_interrupts, 3, 3)
node _any_T_5 = bits(d_interrupts, 7, 7)
node _any_T_6 = bits(d_interrupts, 9, 9)
node _any_T_7 = bits(d_interrupts, 1, 1)
node _any_T_8 = bits(d_interrupts, 5, 5)
node _any_T_9 = bits(d_interrupts, 10, 10)
node _any_T_10 = bits(d_interrupts, 2, 2)
node _any_T_11 = bits(d_interrupts, 6, 6)
node _any_T_12 = bits(d_interrupts, 8, 8)
node _any_T_13 = bits(d_interrupts, 0, 0)
node _any_T_14 = bits(d_interrupts, 4, 4)
node _any_T_15 = bits(m_interrupts, 15, 15)
node _any_T_16 = bits(m_interrupts, 14, 14)
node _any_T_17 = bits(m_interrupts, 13, 13)
node _any_T_18 = bits(m_interrupts, 12, 12)
node _any_T_19 = bits(m_interrupts, 11, 11)
node _any_T_20 = bits(m_interrupts, 3, 3)
node _any_T_21 = bits(m_interrupts, 7, 7)
node _any_T_22 = bits(m_interrupts, 9, 9)
node _any_T_23 = bits(m_interrupts, 1, 1)
node _any_T_24 = bits(m_interrupts, 5, 5)
node _any_T_25 = bits(m_interrupts, 10, 10)
node _any_T_26 = bits(m_interrupts, 2, 2)
node _any_T_27 = bits(m_interrupts, 6, 6)
node _any_T_28 = bits(m_interrupts, 8, 8)
node _any_T_29 = bits(m_interrupts, 0, 0)
node _any_T_30 = bits(m_interrupts, 4, 4)
node _any_T_31 = bits(s_interrupts, 15, 15)
node _any_T_32 = bits(s_interrupts, 14, 14)
node _any_T_33 = bits(s_interrupts, 13, 13)
node _any_T_34 = bits(s_interrupts, 12, 12)
node _any_T_35 = bits(s_interrupts, 11, 11)
node _any_T_36 = bits(s_interrupts, 3, 3)
node _any_T_37 = bits(s_interrupts, 7, 7)
node _any_T_38 = bits(s_interrupts, 9, 9)
node _any_T_39 = bits(s_interrupts, 1, 1)
node _any_T_40 = bits(s_interrupts, 5, 5)
node _any_T_41 = bits(s_interrupts, 10, 10)
node _any_T_42 = bits(s_interrupts, 2, 2)
node _any_T_43 = bits(s_interrupts, 6, 6)
node _any_T_44 = bits(s_interrupts, 8, 8)
node _any_T_45 = bits(s_interrupts, 0, 0)
node _any_T_46 = bits(s_interrupts, 4, 4)
node _any_T_47 = bits(vs_interrupts, 15, 15)
node _any_T_48 = bits(vs_interrupts, 14, 14)
node _any_T_49 = bits(vs_interrupts, 13, 13)
node _any_T_50 = bits(vs_interrupts, 12, 12)
node _any_T_51 = bits(vs_interrupts, 11, 11)
node _any_T_52 = bits(vs_interrupts, 3, 3)
node _any_T_53 = bits(vs_interrupts, 7, 7)
node _any_T_54 = bits(vs_interrupts, 9, 9)
node _any_T_55 = bits(vs_interrupts, 1, 1)
node _any_T_56 = bits(vs_interrupts, 5, 5)
node _any_T_57 = bits(vs_interrupts, 10, 10)
node _any_T_58 = bits(vs_interrupts, 2, 2)
node _any_T_59 = bits(vs_interrupts, 6, 6)
node _any_T_60 = bits(vs_interrupts, 8, 8)
node _any_T_61 = bits(vs_interrupts, 0, 0)
node _any_T_62 = bits(vs_interrupts, 4, 4)
node _any_T_63 = or(_any_T, _any_T_1)
node _any_T_64 = or(_any_T_63, _any_T_2)
node _any_T_65 = or(_any_T_64, _any_T_3)
node _any_T_66 = or(_any_T_65, _any_T_4)
node _any_T_67 = or(_any_T_66, _any_T_5)
node _any_T_68 = or(_any_T_67, _any_T_6)
node _any_T_69 = or(_any_T_68, _any_T_7)
node _any_T_70 = or(_any_T_69, _any_T_8)
node _any_T_71 = or(_any_T_70, _any_T_9)
node _any_T_72 = or(_any_T_71, _any_T_10)
node _any_T_73 = or(_any_T_72, _any_T_11)
node _any_T_74 = or(_any_T_73, _any_T_12)
node _any_T_75 = or(_any_T_74, _any_T_13)
node _any_T_76 = or(_any_T_75, _any_T_14)
node _any_T_77 = or(_any_T_76, UInt<1>(0h0))
node _any_T_78 = or(_any_T_77, _any_T_15)
node _any_T_79 = or(_any_T_78, _any_T_16)
node _any_T_80 = or(_any_T_79, _any_T_17)
node _any_T_81 = or(_any_T_80, _any_T_18)
node _any_T_82 = or(_any_T_81, _any_T_19)
node _any_T_83 = or(_any_T_82, _any_T_20)
node _any_T_84 = or(_any_T_83, _any_T_21)
node _any_T_85 = or(_any_T_84, _any_T_22)
node _any_T_86 = or(_any_T_85, _any_T_23)
node _any_T_87 = or(_any_T_86, _any_T_24)
node _any_T_88 = or(_any_T_87, _any_T_25)
node _any_T_89 = or(_any_T_88, _any_T_26)
node _any_T_90 = or(_any_T_89, _any_T_27)
node _any_T_91 = or(_any_T_90, _any_T_28)
node _any_T_92 = or(_any_T_91, _any_T_29)
node _any_T_93 = or(_any_T_92, _any_T_30)
node _any_T_94 = or(_any_T_93, _any_T_31)
node _any_T_95 = or(_any_T_94, _any_T_32)
node _any_T_96 = or(_any_T_95, _any_T_33)
node _any_T_97 = or(_any_T_96, _any_T_34)
node _any_T_98 = or(_any_T_97, _any_T_35)
node _any_T_99 = or(_any_T_98, _any_T_36)
node _any_T_100 = or(_any_T_99, _any_T_37)
node _any_T_101 = or(_any_T_100, _any_T_38)
node _any_T_102 = or(_any_T_101, _any_T_39)
node _any_T_103 = or(_any_T_102, _any_T_40)
node _any_T_104 = or(_any_T_103, _any_T_41)
node _any_T_105 = or(_any_T_104, _any_T_42)
node _any_T_106 = or(_any_T_105, _any_T_43)
node _any_T_107 = or(_any_T_106, _any_T_44)
node _any_T_108 = or(_any_T_107, _any_T_45)
node _any_T_109 = or(_any_T_108, _any_T_46)
node _any_T_110 = or(_any_T_109, _any_T_47)
node _any_T_111 = or(_any_T_110, _any_T_48)
node _any_T_112 = or(_any_T_111, _any_T_49)
node _any_T_113 = or(_any_T_112, _any_T_50)
node _any_T_114 = or(_any_T_113, _any_T_51)
node _any_T_115 = or(_any_T_114, _any_T_52)
node _any_T_116 = or(_any_T_115, _any_T_53)
node _any_T_117 = or(_any_T_116, _any_T_54)
node _any_T_118 = or(_any_T_117, _any_T_55)
node _any_T_119 = or(_any_T_118, _any_T_56)
node _any_T_120 = or(_any_T_119, _any_T_57)
node _any_T_121 = or(_any_T_120, _any_T_58)
node _any_T_122 = or(_any_T_121, _any_T_59)
node _any_T_123 = or(_any_T_122, _any_T_60)
node _any_T_124 = or(_any_T_123, _any_T_61)
node anyInterrupt = or(_any_T_124, _any_T_62)
node _which_T = bits(d_interrupts, 14, 14)
node _which_T_1 = bits(d_interrupts, 13, 13)
node _which_T_2 = bits(d_interrupts, 12, 12)
node _which_T_3 = bits(d_interrupts, 11, 11)
node _which_T_4 = bits(d_interrupts, 3, 3)
node _which_T_5 = bits(d_interrupts, 7, 7)
node _which_T_6 = bits(d_interrupts, 9, 9)
node _which_T_7 = bits(d_interrupts, 1, 1)
node _which_T_8 = bits(d_interrupts, 5, 5)
node _which_T_9 = bits(d_interrupts, 10, 10)
node _which_T_10 = bits(d_interrupts, 2, 2)
node _which_T_11 = bits(d_interrupts, 6, 6)
node _which_T_12 = bits(d_interrupts, 8, 8)
node _which_T_13 = bits(d_interrupts, 0, 0)
node _which_T_14 = bits(d_interrupts, 4, 4)
node _which_T_15 = bits(m_interrupts, 15, 15)
node _which_T_16 = bits(m_interrupts, 14, 14)
node _which_T_17 = bits(m_interrupts, 13, 13)
node _which_T_18 = bits(m_interrupts, 12, 12)
node _which_T_19 = bits(m_interrupts, 11, 11)
node _which_T_20 = bits(m_interrupts, 3, 3)
node _which_T_21 = bits(m_interrupts, 7, 7)
node _which_T_22 = bits(m_interrupts, 9, 9)
node _which_T_23 = bits(m_interrupts, 1, 1)
node _which_T_24 = bits(m_interrupts, 5, 5)
node _which_T_25 = bits(m_interrupts, 10, 10)
node _which_T_26 = bits(m_interrupts, 2, 2)
node _which_T_27 = bits(m_interrupts, 6, 6)
node _which_T_28 = bits(m_interrupts, 8, 8)
node _which_T_29 = bits(m_interrupts, 0, 0)
node _which_T_30 = bits(m_interrupts, 4, 4)
node _which_T_31 = bits(s_interrupts, 15, 15)
node _which_T_32 = bits(s_interrupts, 14, 14)
node _which_T_33 = bits(s_interrupts, 13, 13)
node _which_T_34 = bits(s_interrupts, 12, 12)
node _which_T_35 = bits(s_interrupts, 11, 11)
node _which_T_36 = bits(s_interrupts, 3, 3)
node _which_T_37 = bits(s_interrupts, 7, 7)
node _which_T_38 = bits(s_interrupts, 9, 9)
node _which_T_39 = bits(s_interrupts, 1, 1)
node _which_T_40 = bits(s_interrupts, 5, 5)
node _which_T_41 = bits(s_interrupts, 10, 10)
node _which_T_42 = bits(s_interrupts, 2, 2)
node _which_T_43 = bits(s_interrupts, 6, 6)
node _which_T_44 = bits(s_interrupts, 8, 8)
node _which_T_45 = bits(s_interrupts, 0, 0)
node _which_T_46 = bits(s_interrupts, 4, 4)
node _which_T_47 = bits(vs_interrupts, 15, 15)
node _which_T_48 = bits(vs_interrupts, 14, 14)
node _which_T_49 = bits(vs_interrupts, 13, 13)
node _which_T_50 = bits(vs_interrupts, 12, 12)
node _which_T_51 = bits(vs_interrupts, 11, 11)
node _which_T_52 = bits(vs_interrupts, 3, 3)
node _which_T_53 = bits(vs_interrupts, 7, 7)
node _which_T_54 = bits(vs_interrupts, 9, 9)
node _which_T_55 = bits(vs_interrupts, 1, 1)
node _which_T_56 = bits(vs_interrupts, 5, 5)
node _which_T_57 = bits(vs_interrupts, 10, 10)
node _which_T_58 = bits(vs_interrupts, 2, 2)
node _which_T_59 = bits(vs_interrupts, 6, 6)
node _which_T_60 = bits(vs_interrupts, 8, 8)
node _which_T_61 = bits(vs_interrupts, 0, 0)
node _which_T_62 = bits(vs_interrupts, 4, 4)
node _which_T_63 = mux(_which_T_61, UInt<1>(0h0), UInt<3>(0h4))
node _which_T_64 = mux(_which_T_60, UInt<4>(0h8), _which_T_63)
node _which_T_65 = mux(_which_T_59, UInt<3>(0h6), _which_T_64)
node _which_T_66 = mux(_which_T_58, UInt<2>(0h2), _which_T_65)
node _which_T_67 = mux(_which_T_57, UInt<4>(0ha), _which_T_66)
node _which_T_68 = mux(_which_T_56, UInt<3>(0h5), _which_T_67)
node _which_T_69 = mux(_which_T_55, UInt<1>(0h1), _which_T_68)
node _which_T_70 = mux(_which_T_54, UInt<4>(0h9), _which_T_69)
node _which_T_71 = mux(_which_T_53, UInt<3>(0h7), _which_T_70)
node _which_T_72 = mux(_which_T_52, UInt<2>(0h3), _which_T_71)
node _which_T_73 = mux(_which_T_51, UInt<4>(0hb), _which_T_72)
node _which_T_74 = mux(_which_T_50, UInt<4>(0hc), _which_T_73)
node _which_T_75 = mux(_which_T_49, UInt<4>(0hd), _which_T_74)
node _which_T_76 = mux(_which_T_48, UInt<4>(0he), _which_T_75)
node _which_T_77 = mux(_which_T_47, UInt<4>(0hf), _which_T_76)
node _which_T_78 = mux(_which_T_46, UInt<3>(0h4), _which_T_77)
node _which_T_79 = mux(_which_T_45, UInt<1>(0h0), _which_T_78)
node _which_T_80 = mux(_which_T_44, UInt<4>(0h8), _which_T_79)
node _which_T_81 = mux(_which_T_43, UInt<3>(0h6), _which_T_80)
node _which_T_82 = mux(_which_T_42, UInt<2>(0h2), _which_T_81)
node _which_T_83 = mux(_which_T_41, UInt<4>(0ha), _which_T_82)
node _which_T_84 = mux(_which_T_40, UInt<3>(0h5), _which_T_83)
node _which_T_85 = mux(_which_T_39, UInt<1>(0h1), _which_T_84)
node _which_T_86 = mux(_which_T_38, UInt<4>(0h9), _which_T_85)
node _which_T_87 = mux(_which_T_37, UInt<3>(0h7), _which_T_86)
node _which_T_88 = mux(_which_T_36, UInt<2>(0h3), _which_T_87)
node _which_T_89 = mux(_which_T_35, UInt<4>(0hb), _which_T_88)
node _which_T_90 = mux(_which_T_34, UInt<4>(0hc), _which_T_89)
node _which_T_91 = mux(_which_T_33, UInt<4>(0hd), _which_T_90)
node _which_T_92 = mux(_which_T_32, UInt<4>(0he), _which_T_91)
node _which_T_93 = mux(_which_T_31, UInt<4>(0hf), _which_T_92)
node _which_T_94 = mux(_which_T_30, UInt<3>(0h4), _which_T_93)
node _which_T_95 = mux(_which_T_29, UInt<1>(0h0), _which_T_94)
node _which_T_96 = mux(_which_T_28, UInt<4>(0h8), _which_T_95)
node _which_T_97 = mux(_which_T_27, UInt<3>(0h6), _which_T_96)
node _which_T_98 = mux(_which_T_26, UInt<2>(0h2), _which_T_97)
node _which_T_99 = mux(_which_T_25, UInt<4>(0ha), _which_T_98)
node _which_T_100 = mux(_which_T_24, UInt<3>(0h5), _which_T_99)
node _which_T_101 = mux(_which_T_23, UInt<1>(0h1), _which_T_100)
node _which_T_102 = mux(_which_T_22, UInt<4>(0h9), _which_T_101)
node _which_T_103 = mux(_which_T_21, UInt<3>(0h7), _which_T_102)
node _which_T_104 = mux(_which_T_20, UInt<2>(0h3), _which_T_103)
node _which_T_105 = mux(_which_T_19, UInt<4>(0hb), _which_T_104)
node _which_T_106 = mux(_which_T_18, UInt<4>(0hc), _which_T_105)
node _which_T_107 = mux(_which_T_17, UInt<4>(0hd), _which_T_106)
node _which_T_108 = mux(_which_T_16, UInt<4>(0he), _which_T_107)
node _which_T_109 = mux(_which_T_15, UInt<4>(0hf), _which_T_108)
node _which_T_110 = mux(UInt<1>(0h0), UInt<1>(0h0), _which_T_109)
node _which_T_111 = mux(_which_T_14, UInt<3>(0h4), _which_T_110)
node _which_T_112 = mux(_which_T_13, UInt<1>(0h0), _which_T_111)
node _which_T_113 = mux(_which_T_12, UInt<4>(0h8), _which_T_112)
node _which_T_114 = mux(_which_T_11, UInt<3>(0h6), _which_T_113)
node _which_T_115 = mux(_which_T_10, UInt<2>(0h2), _which_T_114)
node _which_T_116 = mux(_which_T_9, UInt<4>(0ha), _which_T_115)
node _which_T_117 = mux(_which_T_8, UInt<3>(0h5), _which_T_116)
node _which_T_118 = mux(_which_T_7, UInt<1>(0h1), _which_T_117)
node _which_T_119 = mux(_which_T_6, UInt<4>(0h9), _which_T_118)
node _which_T_120 = mux(_which_T_5, UInt<3>(0h7), _which_T_119)
node _which_T_121 = mux(_which_T_4, UInt<2>(0h3), _which_T_120)
node _which_T_122 = mux(_which_T_3, UInt<4>(0hb), _which_T_121)
node _which_T_123 = mux(_which_T_2, UInt<4>(0hc), _which_T_122)
node _which_T_124 = mux(_which_T_1, UInt<4>(0hd), _which_T_123)
node whichInterrupt = mux(_which_T, UInt<4>(0he), _which_T_124)
node _interruptCause_T = shl(UInt<1>(0h0), 62)
node _interruptCause_T_1 = add(UInt<64>(0h8000000000000000), _interruptCause_T)
node _interruptCause_T_2 = tail(_interruptCause_T_1, 1)
node _interruptCause_T_3 = add(_interruptCause_T_2, whichInterrupt)
node interruptCause = tail(_interruptCause_T_3, 1)
node _io_interrupt_T = eq(io.singleStep, UInt<1>(0h0))
node _io_interrupt_T_1 = and(anyInterrupt, _io_interrupt_T)
node _io_interrupt_T_2 = or(_io_interrupt_T_1, reg_singleStepped)
node _io_interrupt_T_3 = or(reg_debug, io.status.cease)
node _io_interrupt_T_4 = eq(_io_interrupt_T_3, UInt<1>(0h0))
node _io_interrupt_T_5 = and(_io_interrupt_T_2, _io_interrupt_T_4)
connect io.interrupt, _io_interrupt_T_5
connect io.interrupt_cause, interruptCause
connect io.mcontext, UInt<1>(0h0)
connect io.scontext, UInt<1>(0h0)
node _io_fiom_T = lt(reg_mstatus.prv, UInt<2>(0h3))
node _io_fiom_T_1 = and(_io_fiom_T, reg_menvcfg.fiom)
node _io_fiom_T_2 = lt(reg_mstatus.prv, UInt<1>(0h1))
node _io_fiom_T_3 = and(_io_fiom_T_2, reg_senvcfg.fiom)
node _io_fiom_T_4 = or(_io_fiom_T_1, _io_fiom_T_3)
node _io_fiom_T_5 = and(reg_mstatus.v, reg_henvcfg.fiom)
node _io_fiom_T_6 = or(_io_fiom_T_4, _io_fiom_T_5)
connect io.fiom, _io_fiom_T_6
wire pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect pmp.cfg, reg_pmp[0].cfg
connect pmp.addr, reg_pmp[0].addr
node _pmp_mask_base_T = bits(pmp.cfg.a, 0, 0)
node _pmp_mask_base_T_1 = cat(pmp.addr, _pmp_mask_base_T)
node _pmp_mask_base_T_2 = shr(UInt<2>(0h3), 2)
node pmp_mask_base = or(_pmp_mask_base_T_1, _pmp_mask_base_T_2)
node _pmp_mask_T = add(pmp_mask_base, UInt<1>(0h1))
node _pmp_mask_T_1 = tail(_pmp_mask_T, 1)
node _pmp_mask_T_2 = not(_pmp_mask_T_1)
node _pmp_mask_T_3 = and(pmp_mask_base, _pmp_mask_T_2)
node _pmp_mask_T_4 = cat(_pmp_mask_T_3, UInt<2>(0h3))
connect pmp.mask, _pmp_mask_T_4
wire pmp_1 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect pmp_1.cfg, reg_pmp[1].cfg
connect pmp_1.addr, reg_pmp[1].addr
node _pmp_mask_base_T_3 = bits(pmp_1.cfg.a, 0, 0)
node _pmp_mask_base_T_4 = cat(pmp_1.addr, _pmp_mask_base_T_3)
node _pmp_mask_base_T_5 = shr(UInt<2>(0h3), 2)
node pmp_mask_base_1 = or(_pmp_mask_base_T_4, _pmp_mask_base_T_5)
node _pmp_mask_T_5 = add(pmp_mask_base_1, UInt<1>(0h1))
node _pmp_mask_T_6 = tail(_pmp_mask_T_5, 1)
node _pmp_mask_T_7 = not(_pmp_mask_T_6)
node _pmp_mask_T_8 = and(pmp_mask_base_1, _pmp_mask_T_7)
node _pmp_mask_T_9 = cat(_pmp_mask_T_8, UInt<2>(0h3))
connect pmp_1.mask, _pmp_mask_T_9
wire pmp_2 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect pmp_2.cfg, reg_pmp[2].cfg
connect pmp_2.addr, reg_pmp[2].addr
node _pmp_mask_base_T_6 = bits(pmp_2.cfg.a, 0, 0)
node _pmp_mask_base_T_7 = cat(pmp_2.addr, _pmp_mask_base_T_6)
node _pmp_mask_base_T_8 = shr(UInt<2>(0h3), 2)
node pmp_mask_base_2 = or(_pmp_mask_base_T_7, _pmp_mask_base_T_8)
node _pmp_mask_T_10 = add(pmp_mask_base_2, UInt<1>(0h1))
node _pmp_mask_T_11 = tail(_pmp_mask_T_10, 1)
node _pmp_mask_T_12 = not(_pmp_mask_T_11)
node _pmp_mask_T_13 = and(pmp_mask_base_2, _pmp_mask_T_12)
node _pmp_mask_T_14 = cat(_pmp_mask_T_13, UInt<2>(0h3))
connect pmp_2.mask, _pmp_mask_T_14
wire pmp_3 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect pmp_3.cfg, reg_pmp[3].cfg
connect pmp_3.addr, reg_pmp[3].addr
node _pmp_mask_base_T_9 = bits(pmp_3.cfg.a, 0, 0)
node _pmp_mask_base_T_10 = cat(pmp_3.addr, _pmp_mask_base_T_9)
node _pmp_mask_base_T_11 = shr(UInt<2>(0h3), 2)
node pmp_mask_base_3 = or(_pmp_mask_base_T_10, _pmp_mask_base_T_11)
node _pmp_mask_T_15 = add(pmp_mask_base_3, UInt<1>(0h1))
node _pmp_mask_T_16 = tail(_pmp_mask_T_15, 1)
node _pmp_mask_T_17 = not(_pmp_mask_T_16)
node _pmp_mask_T_18 = and(pmp_mask_base_3, _pmp_mask_T_17)
node _pmp_mask_T_19 = cat(_pmp_mask_T_18, UInt<2>(0h3))
connect pmp_3.mask, _pmp_mask_T_19
wire pmp_4 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect pmp_4.cfg, reg_pmp[4].cfg
connect pmp_4.addr, reg_pmp[4].addr
node _pmp_mask_base_T_12 = bits(pmp_4.cfg.a, 0, 0)
node _pmp_mask_base_T_13 = cat(pmp_4.addr, _pmp_mask_base_T_12)
node _pmp_mask_base_T_14 = shr(UInt<2>(0h3), 2)
node pmp_mask_base_4 = or(_pmp_mask_base_T_13, _pmp_mask_base_T_14)
node _pmp_mask_T_20 = add(pmp_mask_base_4, UInt<1>(0h1))
node _pmp_mask_T_21 = tail(_pmp_mask_T_20, 1)
node _pmp_mask_T_22 = not(_pmp_mask_T_21)
node _pmp_mask_T_23 = and(pmp_mask_base_4, _pmp_mask_T_22)
node _pmp_mask_T_24 = cat(_pmp_mask_T_23, UInt<2>(0h3))
connect pmp_4.mask, _pmp_mask_T_24
wire pmp_5 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect pmp_5.cfg, reg_pmp[5].cfg
connect pmp_5.addr, reg_pmp[5].addr
node _pmp_mask_base_T_15 = bits(pmp_5.cfg.a, 0, 0)
node _pmp_mask_base_T_16 = cat(pmp_5.addr, _pmp_mask_base_T_15)
node _pmp_mask_base_T_17 = shr(UInt<2>(0h3), 2)
node pmp_mask_base_5 = or(_pmp_mask_base_T_16, _pmp_mask_base_T_17)
node _pmp_mask_T_25 = add(pmp_mask_base_5, UInt<1>(0h1))
node _pmp_mask_T_26 = tail(_pmp_mask_T_25, 1)
node _pmp_mask_T_27 = not(_pmp_mask_T_26)
node _pmp_mask_T_28 = and(pmp_mask_base_5, _pmp_mask_T_27)
node _pmp_mask_T_29 = cat(_pmp_mask_T_28, UInt<2>(0h3))
connect pmp_5.mask, _pmp_mask_T_29
wire pmp_6 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect pmp_6.cfg, reg_pmp[6].cfg
connect pmp_6.addr, reg_pmp[6].addr
node _pmp_mask_base_T_18 = bits(pmp_6.cfg.a, 0, 0)
node _pmp_mask_base_T_19 = cat(pmp_6.addr, _pmp_mask_base_T_18)
node _pmp_mask_base_T_20 = shr(UInt<2>(0h3), 2)
node pmp_mask_base_6 = or(_pmp_mask_base_T_19, _pmp_mask_base_T_20)
node _pmp_mask_T_30 = add(pmp_mask_base_6, UInt<1>(0h1))
node _pmp_mask_T_31 = tail(_pmp_mask_T_30, 1)
node _pmp_mask_T_32 = not(_pmp_mask_T_31)
node _pmp_mask_T_33 = and(pmp_mask_base_6, _pmp_mask_T_32)
node _pmp_mask_T_34 = cat(_pmp_mask_T_33, UInt<2>(0h3))
connect pmp_6.mask, _pmp_mask_T_34
wire pmp_7 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect pmp_7.cfg, reg_pmp[7].cfg
connect pmp_7.addr, reg_pmp[7].addr
node _pmp_mask_base_T_21 = bits(pmp_7.cfg.a, 0, 0)
node _pmp_mask_base_T_22 = cat(pmp_7.addr, _pmp_mask_base_T_21)
node _pmp_mask_base_T_23 = shr(UInt<2>(0h3), 2)
node pmp_mask_base_7 = or(_pmp_mask_base_T_22, _pmp_mask_base_T_23)
node _pmp_mask_T_35 = add(pmp_mask_base_7, UInt<1>(0h1))
node _pmp_mask_T_36 = tail(_pmp_mask_T_35, 1)
node _pmp_mask_T_37 = not(_pmp_mask_T_36)
node _pmp_mask_T_38 = and(pmp_mask_base_7, _pmp_mask_T_37)
node _pmp_mask_T_39 = cat(_pmp_mask_T_38, UInt<2>(0h3))
connect pmp_7.mask, _pmp_mask_T_39
connect io.pmp[0], pmp
connect io.pmp[1], pmp_1
connect io.pmp[2], pmp_2
connect io.pmp[3], pmp_3
connect io.pmp[4], pmp_4
connect io.pmp[5], pmp_5
connect io.pmp[6], pmp_6
connect io.pmp[7], pmp_7
regreset reg_misa : UInt, clock, reset, UInt<64>(0h800000000014112d)
node read_mstatus_lo_lo_lo_lo = cat(io.status.sie, io.status.uie)
node read_mstatus_lo_lo_lo_hi = cat(io.status.mie, io.status.hie)
node read_mstatus_lo_lo_lo = cat(read_mstatus_lo_lo_lo_hi, read_mstatus_lo_lo_lo_lo)
node read_mstatus_lo_lo_hi_lo = cat(io.status.spie, io.status.upie)
node read_mstatus_lo_lo_hi_hi_hi = cat(io.status.spp, io.status.mpie)
node read_mstatus_lo_lo_hi_hi = cat(read_mstatus_lo_lo_hi_hi_hi, io.status.ube)
node read_mstatus_lo_lo_hi = cat(read_mstatus_lo_lo_hi_hi, read_mstatus_lo_lo_hi_lo)
node read_mstatus_lo_lo = cat(read_mstatus_lo_lo_hi, read_mstatus_lo_lo_lo)
node read_mstatus_lo_hi_lo_lo = cat(io.status.mpp, io.status.vs)
node read_mstatus_lo_hi_lo_hi = cat(io.status.xs, io.status.fs)
node read_mstatus_lo_hi_lo = cat(read_mstatus_lo_hi_lo_hi, read_mstatus_lo_hi_lo_lo)
node read_mstatus_lo_hi_hi_lo = cat(io.status.sum, io.status.mprv)
node read_mstatus_lo_hi_hi_hi_hi = cat(io.status.tw, io.status.tvm)
node read_mstatus_lo_hi_hi_hi = cat(read_mstatus_lo_hi_hi_hi_hi, io.status.mxr)
node read_mstatus_lo_hi_hi = cat(read_mstatus_lo_hi_hi_hi, read_mstatus_lo_hi_hi_lo)
node read_mstatus_lo_hi = cat(read_mstatus_lo_hi_hi, read_mstatus_lo_hi_lo)
node read_mstatus_lo = cat(read_mstatus_lo_hi, read_mstatus_lo_lo)
node read_mstatus_hi_lo_lo_lo = cat(io.status.zero1, io.status.tsr)
node read_mstatus_hi_lo_lo_hi = cat(io.status.uxl, io.status.sd_rv32)
node read_mstatus_hi_lo_lo = cat(read_mstatus_hi_lo_lo_hi, read_mstatus_hi_lo_lo_lo)
node read_mstatus_hi_lo_hi_lo = cat(io.status.sbe, io.status.sxl)
node read_mstatus_hi_lo_hi_hi_hi = cat(io.status.mpv, io.status.gva)
node read_mstatus_hi_lo_hi_hi = cat(read_mstatus_hi_lo_hi_hi_hi, io.status.mbe)
node read_mstatus_hi_lo_hi = cat(read_mstatus_hi_lo_hi_hi, read_mstatus_hi_lo_hi_lo)
node read_mstatus_hi_lo = cat(read_mstatus_hi_lo_hi, read_mstatus_hi_lo_lo)
node read_mstatus_hi_hi_lo_lo = cat(io.status.sd, io.status.zero2)
node read_mstatus_hi_hi_lo_hi_hi = cat(io.status.dv, io.status.prv)
node read_mstatus_hi_hi_lo_hi = cat(read_mstatus_hi_hi_lo_hi_hi, io.status.v)
node read_mstatus_hi_hi_lo = cat(read_mstatus_hi_hi_lo_hi, read_mstatus_hi_hi_lo_lo)
node read_mstatus_hi_hi_hi_lo = cat(io.status.isa, io.status.dprv)
node read_mstatus_hi_hi_hi_hi_hi = cat(io.status.debug, io.status.cease)
node read_mstatus_hi_hi_hi_hi = cat(read_mstatus_hi_hi_hi_hi_hi, io.status.wfi)
node read_mstatus_hi_hi_hi = cat(read_mstatus_hi_hi_hi_hi, read_mstatus_hi_hi_hi_lo)
node read_mstatus_hi_hi = cat(read_mstatus_hi_hi_hi, read_mstatus_hi_hi_lo)
node read_mstatus_hi = cat(read_mstatus_hi_hi, read_mstatus_hi_lo)
node _read_mstatus_T = cat(read_mstatus_hi, read_mstatus_lo)
node read_mstatus = bits(_read_mstatus_T, 63, 0)
node _read_mtvec_T = bits(reg_mtvec, 0, 0)
node _read_mtvec_T_1 = mux(_read_mtvec_T, UInt<8>(0hfe), UInt<2>(0h2))
node _read_mtvec_T_2 = and(reg_mtvec, UInt<1>(0h0))
node _read_mtvec_T_3 = or(_read_mtvec_T_1, _read_mtvec_T_2)
node _read_mtvec_T_4 = not(_read_mtvec_T_3)
node _read_mtvec_T_5 = and(reg_mtvec, _read_mtvec_T_4)
node read_mtvec = cat(UInt<32>(0h0), _read_mtvec_T_5)
node _read_stvec_T = bits(reg_stvec, 0, 0)
node _read_stvec_T_1 = mux(_read_stvec_T, UInt<8>(0hfe), UInt<2>(0h2))
node _read_stvec_T_2 = and(reg_stvec, UInt<1>(0h0))
node _read_stvec_T_3 = or(_read_stvec_T_1, _read_stvec_T_2)
node _read_stvec_T_4 = not(_read_stvec_T_3)
node _read_stvec_T_5 = and(reg_stvec, _read_stvec_T_4)
node _read_stvec_T_6 = bits(_read_stvec_T_5, 38, 38)
node _read_stvec_T_7 = mux(_read_stvec_T_6, UInt<25>(0h1ffffff), UInt<25>(0h0))
node read_stvec = cat(_read_stvec_T_7, _read_stvec_T_5)
node read_mapping_lo_lo_hi = cat(reg_bp[reg_tselect].control.x, reg_bp[reg_tselect].control.w)
node read_mapping_lo_lo = cat(read_mapping_lo_lo_hi, reg_bp[reg_tselect].control.r)
node read_mapping_lo_hi_lo = cat(reg_bp[reg_tselect].control.s, reg_bp[reg_tselect].control.u)
node read_mapping_lo_hi_hi = cat(reg_bp[reg_tselect].control.m, reg_bp[reg_tselect].control.h)
node read_mapping_lo_hi = cat(read_mapping_lo_hi_hi, read_mapping_lo_hi_lo)
node read_mapping_lo = cat(read_mapping_lo_hi, read_mapping_lo_lo)
node read_mapping_hi_lo_lo = cat(reg_bp[reg_tselect].control.zero, reg_bp[reg_tselect].control.tmatch)
node read_mapping_hi_lo_hi = cat(reg_bp[reg_tselect].control.action, reg_bp[reg_tselect].control.chain)
node read_mapping_hi_lo = cat(read_mapping_hi_lo_hi, read_mapping_hi_lo_lo)
node read_mapping_hi_hi_lo = cat(reg_bp[reg_tselect].control.maskmax, reg_bp[reg_tselect].control.reserved)
node read_mapping_hi_hi_hi = cat(reg_bp[reg_tselect].control.ttype, reg_bp[reg_tselect].control.dmode)
node read_mapping_hi_hi = cat(read_mapping_hi_hi_hi, read_mapping_hi_hi_lo)
node read_mapping_hi = cat(read_mapping_hi_hi, read_mapping_hi_lo)
node read_mapping_1_2 = cat(read_mapping_hi, read_mapping_lo)
node _read_mapping_T = bits(reg_bp[reg_tselect].address, 38, 38)
node _read_mapping_T_1 = mux(_read_mapping_T, UInt<25>(0h1ffffff), UInt<25>(0h0))
node read_mapping_2_2 = cat(_read_mapping_T_1, reg_bp[reg_tselect].address)
node read_mapping_lo_hi_1 = cat(reg_bp[reg_tselect].textra.svalue, reg_bp[reg_tselect].textra.pad1)
node read_mapping_lo_1 = cat(read_mapping_lo_hi_1, reg_bp[reg_tselect].textra.sselect)
node read_mapping_hi_hi_1 = cat(reg_bp[reg_tselect].textra.mvalue, reg_bp[reg_tselect].textra.mselect)
node read_mapping_hi_1 = cat(read_mapping_hi_hi_1, reg_bp[reg_tselect].textra.pad2)
node read_mapping_3_2 = cat(read_mapping_hi_1, read_mapping_lo_1)
node _read_mapping_T_2 = not(reg_mepc)
node _read_mapping_T_3 = bits(reg_misa, 2, 2)
node _read_mapping_T_4 = mux(_read_mapping_T_3, UInt<1>(0h1), UInt<2>(0h3))
node _read_mapping_T_5 = or(_read_mapping_T_2, _read_mapping_T_4)
node _read_mapping_T_6 = not(_read_mapping_T_5)
node _read_mapping_T_7 = bits(_read_mapping_T_6, 39, 39)
node _read_mapping_T_8 = mux(_read_mapping_T_7, UInt<24>(0hffffff), UInt<24>(0h0))
node read_mapping_10_2 = cat(_read_mapping_T_8, _read_mapping_T_6)
node _read_mapping_T_9 = bits(reg_mtval, 39, 39)
node _read_mapping_T_10 = mux(_read_mapping_T_9, UInt<24>(0hffffff), UInt<24>(0h0))
node read_mapping_11_2 = cat(_read_mapping_T_10, reg_mtval)
node debug_csrs_lo_lo_hi = cat(reg_dcsr.zero1, reg_dcsr.step)
node debug_csrs_lo_lo = cat(debug_csrs_lo_lo_hi, reg_dcsr.prv)
node debug_csrs_lo_hi_lo = cat(reg_dcsr.cause, reg_dcsr.v)
node debug_csrs_lo_hi_hi = cat(reg_dcsr.stopcycle, reg_dcsr.stoptime)
node debug_csrs_lo_hi = cat(debug_csrs_lo_hi_hi, debug_csrs_lo_hi_lo)
node debug_csrs_lo = cat(debug_csrs_lo_hi, debug_csrs_lo_lo)
node debug_csrs_hi_lo_lo = cat(reg_dcsr.ebreaku, reg_dcsr.zero2)
node debug_csrs_hi_lo_hi = cat(reg_dcsr.ebreakh, reg_dcsr.ebreaks)
node debug_csrs_hi_lo = cat(debug_csrs_hi_lo_hi, debug_csrs_hi_lo_lo)
node debug_csrs_hi_hi_lo = cat(reg_dcsr.zero3, reg_dcsr.ebreakm)
node debug_csrs_hi_hi_hi = cat(reg_dcsr.xdebugver, reg_dcsr.zero4)
node debug_csrs_hi_hi = cat(debug_csrs_hi_hi_hi, debug_csrs_hi_hi_lo)
node debug_csrs_hi = cat(debug_csrs_hi_hi, debug_csrs_hi_lo)
node debug_csrs_0_2 = cat(debug_csrs_hi, debug_csrs_lo)
node _debug_csrs_T = not(reg_dpc)
node _debug_csrs_T_1 = bits(reg_misa, 2, 2)
node _debug_csrs_T_2 = mux(_debug_csrs_T_1, UInt<1>(0h1), UInt<2>(0h3))
node _debug_csrs_T_3 = or(_debug_csrs_T, _debug_csrs_T_2)
node _debug_csrs_T_4 = not(_debug_csrs_T_3)
node _debug_csrs_T_5 = bits(_debug_csrs_T_4, 39, 39)
node _debug_csrs_T_6 = mux(_debug_csrs_T_5, UInt<24>(0hffffff), UInt<24>(0h0))
node debug_csrs_1_2 = cat(_debug_csrs_T_6, _debug_csrs_T_4)
wire _read_mnstatus_WIRE : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>}
connect _read_mnstatus_WIRE.zero1, UInt<3>(0h0)
connect _read_mnstatus_WIRE.mie, UInt<1>(0h0)
connect _read_mnstatus_WIRE.zero2, UInt<3>(0h0)
connect _read_mnstatus_WIRE.mpv, UInt<1>(0h0)
connect _read_mnstatus_WIRE.zero3, UInt<3>(0h0)
connect _read_mnstatus_WIRE.mpp, UInt<2>(0h0)
wire read_mnstatus : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>}
connect read_mnstatus, _read_mnstatus_WIRE
connect read_mnstatus.mpp, reg_mnstatus.mpp
connect read_mnstatus.mpv, reg_mnstatus.mpv
connect read_mnstatus.mie, reg_rnmie
node read_fcsr = cat(reg_frm, reg_fflags)
node read_vcsr = cat(UInt<1>(0h0), UInt<1>(0h0))
node lo_lo_4 = cat(reg_menvcfg.zero3, reg_menvcfg.fiom)
node lo_hi_4 = cat(reg_menvcfg.cbcfe, reg_menvcfg.cbie)
node lo_4 = cat(lo_hi_4, lo_lo_4)
node hi_lo_4 = cat(reg_menvcfg.zero54, reg_menvcfg.cbze)
node hi_hi_4 = cat(reg_menvcfg.stce, reg_menvcfg.pbmte)
node hi_6 = cat(hi_hi_4, hi_lo_4)
node _T_23 = cat(hi_6, lo_4)
wire _sie_mask_sgeip_mask_WIRE : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
connect _sie_mask_sgeip_mask_WIRE.usip, UInt<1>(0h0)
connect _sie_mask_sgeip_mask_WIRE.ssip, UInt<1>(0h0)
connect _sie_mask_sgeip_mask_WIRE.vssip, UInt<1>(0h0)
connect _sie_mask_sgeip_mask_WIRE.msip, UInt<1>(0h0)
connect _sie_mask_sgeip_mask_WIRE.utip, UInt<1>(0h0)
connect _sie_mask_sgeip_mask_WIRE.stip, UInt<1>(0h0)
connect _sie_mask_sgeip_mask_WIRE.vstip, UInt<1>(0h0)
connect _sie_mask_sgeip_mask_WIRE.mtip, UInt<1>(0h0)
connect _sie_mask_sgeip_mask_WIRE.ueip, UInt<1>(0h0)
connect _sie_mask_sgeip_mask_WIRE.seip, UInt<1>(0h0)
connect _sie_mask_sgeip_mask_WIRE.vseip, UInt<1>(0h0)
connect _sie_mask_sgeip_mask_WIRE.meip, UInt<1>(0h0)
connect _sie_mask_sgeip_mask_WIRE.sgeip, UInt<1>(0h0)
connect _sie_mask_sgeip_mask_WIRE.rocc, UInt<1>(0h0)
connect _sie_mask_sgeip_mask_WIRE.debug, UInt<1>(0h0)
connect _sie_mask_sgeip_mask_WIRE.zero1, UInt<1>(0h0)
wire sie_mask_sgeip_mask : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
connect sie_mask_sgeip_mask, _sie_mask_sgeip_mask_WIRE
connect sie_mask_sgeip_mask.sgeip, UInt<1>(0h1)
node sie_mask_lo_lo_lo = cat(sie_mask_sgeip_mask.ssip, sie_mask_sgeip_mask.usip)
node sie_mask_lo_lo_hi = cat(sie_mask_sgeip_mask.msip, sie_mask_sgeip_mask.vssip)
node sie_mask_lo_lo = cat(sie_mask_lo_lo_hi, sie_mask_lo_lo_lo)
node sie_mask_lo_hi_lo = cat(sie_mask_sgeip_mask.stip, sie_mask_sgeip_mask.utip)
node sie_mask_lo_hi_hi = cat(sie_mask_sgeip_mask.mtip, sie_mask_sgeip_mask.vstip)
node sie_mask_lo_hi = cat(sie_mask_lo_hi_hi, sie_mask_lo_hi_lo)
node sie_mask_lo = cat(sie_mask_lo_hi, sie_mask_lo_lo)
node sie_mask_hi_lo_lo = cat(sie_mask_sgeip_mask.seip, sie_mask_sgeip_mask.ueip)
node sie_mask_hi_lo_hi = cat(sie_mask_sgeip_mask.meip, sie_mask_sgeip_mask.vseip)
node sie_mask_hi_lo = cat(sie_mask_hi_lo_hi, sie_mask_hi_lo_lo)
node sie_mask_hi_hi_lo = cat(sie_mask_sgeip_mask.rocc, sie_mask_sgeip_mask.sgeip)
node sie_mask_hi_hi_hi_hi = cat(UInt<0>(0h0), sie_mask_sgeip_mask.zero1)
node sie_mask_hi_hi_hi = cat(sie_mask_hi_hi_hi_hi, sie_mask_sgeip_mask.debug)
node sie_mask_hi_hi = cat(sie_mask_hi_hi_hi, sie_mask_hi_hi_lo)
node sie_mask_hi = cat(sie_mask_hi_hi, sie_mask_hi_lo)
node _sie_mask_T = cat(sie_mask_hi, sie_mask_lo)
node _sie_mask_T_1 = or(hs_delegable_interrupts, _sie_mask_T)
node _sie_mask_T_2 = not(_sie_mask_T_1)
node sie_mask = and(read_mideleg, _sie_mask_T_2)
node read_sie = and(reg_mie, sie_mask)
node read_sip = and(read_mip, sie_mask)
wire _read_sstatus_WIRE : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}
connect _read_sstatus_WIRE.uie, UInt<1>(0h0)
connect _read_sstatus_WIRE.sie, UInt<1>(0h0)
connect _read_sstatus_WIRE.hie, UInt<1>(0h0)
connect _read_sstatus_WIRE.mie, UInt<1>(0h0)
connect _read_sstatus_WIRE.upie, UInt<1>(0h0)
connect _read_sstatus_WIRE.spie, UInt<1>(0h0)
connect _read_sstatus_WIRE.ube, UInt<1>(0h0)
connect _read_sstatus_WIRE.mpie, UInt<1>(0h0)
connect _read_sstatus_WIRE.spp, UInt<1>(0h0)
connect _read_sstatus_WIRE.vs, UInt<2>(0h0)
connect _read_sstatus_WIRE.mpp, UInt<2>(0h0)
connect _read_sstatus_WIRE.fs, UInt<2>(0h0)
connect _read_sstatus_WIRE.xs, UInt<2>(0h0)
connect _read_sstatus_WIRE.mprv, UInt<1>(0h0)
connect _read_sstatus_WIRE.sum, UInt<1>(0h0)
connect _read_sstatus_WIRE.mxr, UInt<1>(0h0)
connect _read_sstatus_WIRE.tvm, UInt<1>(0h0)
connect _read_sstatus_WIRE.tw, UInt<1>(0h0)
connect _read_sstatus_WIRE.tsr, UInt<1>(0h0)
connect _read_sstatus_WIRE.zero1, UInt<8>(0h0)
connect _read_sstatus_WIRE.sd_rv32, UInt<1>(0h0)
connect _read_sstatus_WIRE.uxl, UInt<2>(0h0)
connect _read_sstatus_WIRE.sxl, UInt<2>(0h0)
connect _read_sstatus_WIRE.sbe, UInt<1>(0h0)
connect _read_sstatus_WIRE.mbe, UInt<1>(0h0)
connect _read_sstatus_WIRE.gva, UInt<1>(0h0)
connect _read_sstatus_WIRE.mpv, UInt<1>(0h0)
connect _read_sstatus_WIRE.zero2, UInt<23>(0h0)
connect _read_sstatus_WIRE.sd, UInt<1>(0h0)
connect _read_sstatus_WIRE.v, UInt<1>(0h0)
connect _read_sstatus_WIRE.prv, UInt<2>(0h0)
connect _read_sstatus_WIRE.dv, UInt<1>(0h0)
connect _read_sstatus_WIRE.dprv, UInt<2>(0h0)
connect _read_sstatus_WIRE.isa, UInt<32>(0h0)
connect _read_sstatus_WIRE.wfi, UInt<1>(0h0)
connect _read_sstatus_WIRE.cease, UInt<1>(0h0)
connect _read_sstatus_WIRE.debug, UInt<1>(0h0)
wire read_sstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}
connect read_sstatus, _read_sstatus_WIRE
connect read_sstatus.sd, io.status.sd
connect read_sstatus.uxl, io.status.uxl
connect read_sstatus.sd_rv32, io.status.sd_rv32
connect read_sstatus.mxr, io.status.mxr
connect read_sstatus.sum, io.status.sum
connect read_sstatus.xs, io.status.xs
connect read_sstatus.fs, io.status.fs
connect read_sstatus.vs, io.status.vs
connect read_sstatus.spp, io.status.spp
connect read_sstatus.spie, io.status.spie
connect read_sstatus.sie, io.status.sie
node lo_lo_lo_lo = cat(read_sstatus.sie, read_sstatus.uie)
node lo_lo_lo_hi = cat(read_sstatus.mie, read_sstatus.hie)
node lo_lo_lo_4 = cat(lo_lo_lo_hi, lo_lo_lo_lo)
node lo_lo_hi_lo = cat(read_sstatus.spie, read_sstatus.upie)
node lo_lo_hi_hi_hi = cat(read_sstatus.spp, read_sstatus.mpie)
node lo_lo_hi_hi = cat(lo_lo_hi_hi_hi, read_sstatus.ube)
node lo_lo_hi_4 = cat(lo_lo_hi_hi, lo_lo_hi_lo)
node lo_lo_5 = cat(lo_lo_hi_4, lo_lo_lo_4)
node lo_hi_lo_lo = cat(read_sstatus.mpp, read_sstatus.vs)
node lo_hi_lo_hi = cat(read_sstatus.xs, read_sstatus.fs)
node lo_hi_lo_4 = cat(lo_hi_lo_hi, lo_hi_lo_lo)
node lo_hi_hi_lo = cat(read_sstatus.sum, read_sstatus.mprv)
node lo_hi_hi_hi_hi = cat(read_sstatus.tw, read_sstatus.tvm)
node lo_hi_hi_hi = cat(lo_hi_hi_hi_hi, read_sstatus.mxr)
node lo_hi_hi_4 = cat(lo_hi_hi_hi, lo_hi_hi_lo)
node lo_hi_5 = cat(lo_hi_hi_4, lo_hi_lo_4)
node lo_5 = cat(lo_hi_5, lo_lo_5)
node hi_lo_lo_lo = cat(read_sstatus.zero1, read_sstatus.tsr)
node hi_lo_lo_hi = cat(read_sstatus.uxl, read_sstatus.sd_rv32)
node hi_lo_lo_4 = cat(hi_lo_lo_hi, hi_lo_lo_lo)
node hi_lo_hi_lo = cat(read_sstatus.sbe, read_sstatus.sxl)
node hi_lo_hi_hi_hi = cat(read_sstatus.mpv, read_sstatus.gva)
node hi_lo_hi_hi = cat(hi_lo_hi_hi_hi, read_sstatus.mbe)
node hi_lo_hi_4 = cat(hi_lo_hi_hi, hi_lo_hi_lo)
node hi_lo_5 = cat(hi_lo_hi_4, hi_lo_lo_4)
node hi_hi_lo_lo = cat(read_sstatus.sd, read_sstatus.zero2)
node hi_hi_lo_hi_hi = cat(read_sstatus.dv, read_sstatus.prv)
node hi_hi_lo_hi = cat(hi_hi_lo_hi_hi, read_sstatus.v)
node hi_hi_lo_4 = cat(hi_hi_lo_hi, hi_hi_lo_lo)
node hi_hi_hi_lo = cat(read_sstatus.isa, read_sstatus.dprv)
node hi_hi_hi_hi_hi = cat(read_sstatus.debug, read_sstatus.cease)
node hi_hi_hi_hi_4 = cat(hi_hi_hi_hi_hi, read_sstatus.wfi)
node hi_hi_hi_4 = cat(hi_hi_hi_hi_4, hi_hi_hi_lo)
node hi_hi_5 = cat(hi_hi_hi_4, hi_hi_lo_4)
node hi_7 = cat(hi_hi_5, hi_lo_5)
node _T_24 = cat(hi_7, lo_5)
node _T_25 = bits(_T_24, 63, 0)
node _T_26 = bits(reg_stval, 39, 39)
node _T_27 = mux(_T_26, UInt<24>(0hffffff), UInt<24>(0h0))
node _T_28 = cat(_T_27, reg_stval)
node hi_8 = cat(reg_satp.mode, reg_satp.asid)
node _T_29 = cat(hi_8, reg_satp.ppn)
node _T_30 = not(reg_sepc)
node _T_31 = bits(reg_misa, 2, 2)
node _T_32 = mux(_T_31, UInt<1>(0h1), UInt<2>(0h3))
node _T_33 = or(_T_30, _T_32)
node _T_34 = not(_T_33)
node _T_35 = bits(_T_34, 39, 39)
node _T_36 = mux(_T_35, UInt<24>(0hffffff), UInt<24>(0h0))
node _T_37 = cat(_T_36, _T_34)
node lo_lo_6 = cat(reg_senvcfg.zero3, reg_senvcfg.fiom)
node lo_hi_6 = cat(reg_senvcfg.cbcfe, reg_senvcfg.cbie)
node lo_6 = cat(lo_hi_6, lo_lo_6)
node hi_lo_6 = cat(reg_senvcfg.zero54, reg_senvcfg.cbze)
node hi_hi_6 = cat(reg_senvcfg.stce, reg_senvcfg.pbmte)
node hi_9 = cat(hi_hi_6, hi_lo_6)
node _T_38 = cat(hi_9, lo_6)
wire read_pmp_15 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect read_pmp_15.mask, UInt<32>(0h0)
connect read_pmp_15.addr, UInt<30>(0h0)
connect read_pmp_15.cfg.r, UInt<1>(0h0)
connect read_pmp_15.cfg.w, UInt<1>(0h0)
connect read_pmp_15.cfg.x, UInt<1>(0h0)
connect read_pmp_15.cfg.a, UInt<2>(0h0)
connect read_pmp_15.cfg.res, UInt<2>(0h0)
connect read_pmp_15.cfg.l, UInt<1>(0h0)
node lo_hi_7 = cat(reg_pmp[0].cfg.x, reg_pmp[0].cfg.w)
node lo_7 = cat(lo_hi_7, reg_pmp[0].cfg.r)
node hi_hi_7 = cat(reg_pmp[0].cfg.l, reg_pmp[0].cfg.res)
node hi_10 = cat(hi_hi_7, reg_pmp[0].cfg.a)
node _T_39 = cat(hi_10, lo_7)
node lo_hi_8 = cat(reg_pmp[1].cfg.x, reg_pmp[1].cfg.w)
node lo_8 = cat(lo_hi_8, reg_pmp[1].cfg.r)
node hi_hi_8 = cat(reg_pmp[1].cfg.l, reg_pmp[1].cfg.res)
node hi_11 = cat(hi_hi_8, reg_pmp[1].cfg.a)
node _T_40 = cat(hi_11, lo_8)
node lo_hi_9 = cat(reg_pmp[2].cfg.x, reg_pmp[2].cfg.w)
node lo_9 = cat(lo_hi_9, reg_pmp[2].cfg.r)
node hi_hi_9 = cat(reg_pmp[2].cfg.l, reg_pmp[2].cfg.res)
node hi_12 = cat(hi_hi_9, reg_pmp[2].cfg.a)
node _T_41 = cat(hi_12, lo_9)
node lo_hi_10 = cat(reg_pmp[3].cfg.x, reg_pmp[3].cfg.w)
node lo_10 = cat(lo_hi_10, reg_pmp[3].cfg.r)
node hi_hi_10 = cat(reg_pmp[3].cfg.l, reg_pmp[3].cfg.res)
node hi_13 = cat(hi_hi_10, reg_pmp[3].cfg.a)
node _T_42 = cat(hi_13, lo_10)
node lo_hi_11 = cat(reg_pmp[4].cfg.x, reg_pmp[4].cfg.w)
node lo_11 = cat(lo_hi_11, reg_pmp[4].cfg.r)
node hi_hi_11 = cat(reg_pmp[4].cfg.l, reg_pmp[4].cfg.res)
node hi_14 = cat(hi_hi_11, reg_pmp[4].cfg.a)
node _T_43 = cat(hi_14, lo_11)
node lo_hi_12 = cat(reg_pmp[5].cfg.x, reg_pmp[5].cfg.w)
node lo_12 = cat(lo_hi_12, reg_pmp[5].cfg.r)
node hi_hi_12 = cat(reg_pmp[5].cfg.l, reg_pmp[5].cfg.res)
node hi_15 = cat(hi_hi_12, reg_pmp[5].cfg.a)
node _T_44 = cat(hi_15, lo_12)
node lo_hi_13 = cat(reg_pmp[6].cfg.x, reg_pmp[6].cfg.w)
node lo_13 = cat(lo_hi_13, reg_pmp[6].cfg.r)
node hi_hi_13 = cat(reg_pmp[6].cfg.l, reg_pmp[6].cfg.res)
node hi_16 = cat(hi_hi_13, reg_pmp[6].cfg.a)
node _T_45 = cat(hi_16, lo_13)
node lo_hi_14 = cat(reg_pmp[7].cfg.x, reg_pmp[7].cfg.w)
node lo_14 = cat(lo_hi_14, reg_pmp[7].cfg.r)
node hi_hi_14 = cat(reg_pmp[7].cfg.l, reg_pmp[7].cfg.res)
node hi_17 = cat(hi_hi_14, reg_pmp[7].cfg.a)
node _T_46 = cat(hi_17, lo_14)
node lo_lo_7 = cat(_T_40, _T_39)
node lo_hi_15 = cat(_T_42, _T_41)
node lo_15 = cat(lo_hi_15, lo_lo_7)
node hi_lo_7 = cat(_T_44, _T_43)
node hi_hi_15 = cat(_T_46, _T_45)
node hi_18 = cat(hi_hi_15, hi_lo_7)
node _T_47 = cat(hi_18, lo_15)
node lo_hi_16 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w)
node lo_16 = cat(lo_hi_16, read_pmp_15.cfg.r)
node hi_hi_16 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res)
node hi_19 = cat(hi_hi_16, read_pmp_15.cfg.a)
node _T_48 = cat(hi_19, lo_16)
node lo_hi_17 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w)
node lo_17 = cat(lo_hi_17, read_pmp_15.cfg.r)
node hi_hi_17 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res)
node hi_20 = cat(hi_hi_17, read_pmp_15.cfg.a)
node _T_49 = cat(hi_20, lo_17)
node lo_hi_18 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w)
node lo_18 = cat(lo_hi_18, read_pmp_15.cfg.r)
node hi_hi_18 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res)
node hi_21 = cat(hi_hi_18, read_pmp_15.cfg.a)
node _T_50 = cat(hi_21, lo_18)
node lo_hi_19 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w)
node lo_19 = cat(lo_hi_19, read_pmp_15.cfg.r)
node hi_hi_19 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res)
node hi_22 = cat(hi_hi_19, read_pmp_15.cfg.a)
node _T_51 = cat(hi_22, lo_19)
node lo_hi_20 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w)
node lo_20 = cat(lo_hi_20, read_pmp_15.cfg.r)
node hi_hi_20 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res)
node hi_23 = cat(hi_hi_20, read_pmp_15.cfg.a)
node _T_52 = cat(hi_23, lo_20)
node lo_hi_21 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w)
node lo_21 = cat(lo_hi_21, read_pmp_15.cfg.r)
node hi_hi_21 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res)
node hi_24 = cat(hi_hi_21, read_pmp_15.cfg.a)
node _T_53 = cat(hi_24, lo_21)
node lo_hi_22 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w)
node lo_22 = cat(lo_hi_22, read_pmp_15.cfg.r)
node hi_hi_22 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res)
node hi_25 = cat(hi_hi_22, read_pmp_15.cfg.a)
node _T_54 = cat(hi_25, lo_22)
node lo_hi_23 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w)
node lo_23 = cat(lo_hi_23, read_pmp_15.cfg.r)
node hi_hi_23 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res)
node hi_26 = cat(hi_hi_23, read_pmp_15.cfg.a)
node _T_55 = cat(hi_26, lo_23)
node lo_lo_8 = cat(_T_49, _T_48)
node lo_hi_24 = cat(_T_51, _T_50)
node lo_24 = cat(lo_hi_24, lo_lo_8)
node hi_lo_8 = cat(_T_53, _T_52)
node hi_hi_24 = cat(_T_55, _T_54)
node hi_27 = cat(hi_hi_24, hi_lo_8)
node _T_56 = cat(hi_27, lo_24)
regreset reg_custom_0 : UInt<64>, clock, reset, UInt<64>(0h1)
node _reg_custom_read_T = neq(io.rw.cmd, UInt<3>(0h0))
node _reg_custom_read_T_1 = eq(io.rw.addr, UInt<12>(0h800))
node reg_custom_read = and(_reg_custom_read_T, _reg_custom_read_T_1)
connect io.customCSRs[0].ren, reg_custom_read
node _reg_custom_T = and(reg_custom_read, io.customCSRs[0].stall)
when _reg_custom_T :
connect io.rw_stall, UInt<1>(0h1)
regreset reg_custom_1 : UInt<64>, clock, reset, UInt<64>(0h1)
node _reg_custom_read_T_2 = neq(io.rw.cmd, UInt<3>(0h0))
node _reg_custom_read_T_3 = eq(io.rw.addr, UInt<12>(0h808))
node reg_custom_read_1 = and(_reg_custom_read_T_2, _reg_custom_read_T_3)
connect io.customCSRs[1].ren, reg_custom_read_1
node _reg_custom_T_1 = and(reg_custom_read_1, io.customCSRs[1].stall)
when _reg_custom_T_1 :
connect io.rw_stall, UInt<1>(0h1)
regreset reg_custom_2 : UInt<64>, clock, reset, UInt<64>(0h0)
node _reg_custom_read_T_4 = neq(io.rw.cmd, UInt<3>(0h0))
node _reg_custom_read_T_5 = eq(io.rw.addr, UInt<11>(0h7c1))
node reg_custom_read_2 = and(_reg_custom_read_T_4, _reg_custom_read_T_5)
connect io.customCSRs[2].ren, reg_custom_read_2
node _reg_custom_T_2 = and(reg_custom_read_2, io.customCSRs[2].stall)
when _reg_custom_T_2 :
connect io.rw_stall, UInt<1>(0h1)
regreset reg_custom_3 : UInt<64>, clock, reset, UInt<64>(0h2)
node _reg_custom_read_T_6 = neq(io.rw.cmd, UInt<3>(0h0))
node _reg_custom_read_T_7 = eq(io.rw.addr, UInt<12>(0hf12))
node reg_custom_read_3 = and(_reg_custom_read_T_6, _reg_custom_read_T_7)
connect io.customCSRs[3].ren, reg_custom_read_3
node _reg_custom_T_3 = and(reg_custom_read_3, io.customCSRs[3].stall)
when _reg_custom_T_3 :
connect io.rw_stall, UInt<1>(0h1)
node decoded_addr_addr = cat(io.status.v, io.rw.addr)
wire decoded_addr_decoded_decoded_plaInput : UInt<12>
node decoded_addr_decoded_decoded_invInputs = not(decoded_addr_decoded_decoded_plaInput)
wire decoded_addr_decoded_decoded : UInt<152>
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi, decoded_addr_decoded_decoded_andMatrixOutputs_lo)
node decoded_addr_decoded_decoded_andMatrixOutputs_140_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_1)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_1)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_1)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_1)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_1)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_1)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_1)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_1)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_1)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_lo_1)
node decoded_addr_decoded_decoded_andMatrixOutputs_136_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_2)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_1)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_2)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_2)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_2)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_2)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_2)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_2)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_2)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_2)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_lo_2)
node decoded_addr_decoded_decoded_andMatrixOutputs_41_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_3)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_3)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_3)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_3)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_3)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_3)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_3)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_3)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_lo_3)
node decoded_addr_decoded_decoded_andMatrixOutputs_1_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_3)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_2)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_4)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_4)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_4)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_4)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_4)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_4)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_4)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_4)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_lo_4)
node decoded_addr_decoded_decoded_andMatrixOutputs_89_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_4)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_3)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_5)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_5)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_5)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_5)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_5)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_5)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_5)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_5)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_lo_5)
node decoded_addr_decoded_decoded_andMatrixOutputs_125_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_5)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_6)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_6)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_6)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_6)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_6)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_6)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_6)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_6)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_lo_6)
node decoded_addr_decoded_decoded_andMatrixOutputs_27_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_7)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_7)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_7)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_7)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_7)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_7)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_7)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_lo_7)
node decoded_addr_decoded_decoded_andMatrixOutputs_0_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_6 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_6)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_4)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_8)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_8)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_8)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_8)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_8)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_8)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_8)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_8)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_lo_8)
node decoded_addr_decoded_decoded_andMatrixOutputs_92_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_7 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_7)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_5)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_9)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_9)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_9)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_9)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_9)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_9)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_9)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_9)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_lo_9)
node decoded_addr_decoded_decoded_andMatrixOutputs_59_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_10 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_9 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_8 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_6 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_8)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_6)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_10)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_10)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_10)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_10)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_10)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_10)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_10)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_10)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_lo_10)
node decoded_addr_decoded_decoded_andMatrixOutputs_24_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_11 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_10 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_9 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_7 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_9)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_7)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_11)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_11)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_11)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_11)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_11)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_11)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_lo_11)
node decoded_addr_decoded_decoded_andMatrixOutputs_118_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_11)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_12 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_12 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_12 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_11 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_12)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_12)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_12)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_12)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_12)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_12)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_12)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_lo_12)
node decoded_addr_decoded_decoded_andMatrixOutputs_123_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_12)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_13)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_13)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_13)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_lo_13)
node decoded_addr_decoded_decoded_andMatrixOutputs_74_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_13)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_13 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_13 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_13 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_12 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_10 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_8 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_10)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_8)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_13)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_13)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_13)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_14)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_13)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_14)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_14)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_13)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_lo_14)
node decoded_addr_decoded_decoded_andMatrixOutputs_116_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_14)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_14 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_14 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_14 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_13 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_11 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_9 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_9)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_14)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_14)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_14)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_15)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_14)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_15)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_15)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_14)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_lo_15)
node decoded_addr_decoded_decoded_andMatrixOutputs_106_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_15)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_16 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_16 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_16 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_16 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_16 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_15 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_15 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_15 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_14 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_12 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_10 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_12)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_10)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_15)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_15)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_15)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_16)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_15)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_16)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_16)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_15)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_lo_16)
node decoded_addr_decoded_decoded_andMatrixOutputs_82_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_16)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_17 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_17 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_17 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_17 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_17 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_16 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_16 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_16 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_16 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_15 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_13 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_11 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_13)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_16)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_16)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_16)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_17)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_16)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_17)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_17)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_16)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_lo_17)
node decoded_addr_decoded_decoded_andMatrixOutputs_28_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_17)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_18 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_18 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_18 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_18 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_18 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_17 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_17 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_17 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_17 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_16 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_14 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_12 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_14)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_12)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_17)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_17)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_17)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_18)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_17)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_18)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_18)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_17)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_lo_18)
node decoded_addr_decoded_decoded_andMatrixOutputs_91_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_18)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_19 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_19 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_19 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_19 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_19 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_18 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_18 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_18 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_18 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_17 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_15 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_13 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_15)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_13)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_18)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_18)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_18)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_19)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_18)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_19)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_19)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_18)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_lo_19)
node decoded_addr_decoded_decoded_andMatrixOutputs_68_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_19)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_20 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_20 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_20 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_20 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_20 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_19 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_19 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_19 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_19 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_18 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_16 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_16)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_19)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_19)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_19)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_20)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_19)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_20)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_20)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_19)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_lo_20)
node decoded_addr_decoded_decoded_andMatrixOutputs_84_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_20)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_21 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_21 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_21 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_21 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_21 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_20 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_20 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_20 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_20 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_20)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_20)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_20)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_21)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_21)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_21)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_20)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_lo_21)
node decoded_addr_decoded_decoded_andMatrixOutputs_40_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_21)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_22 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_22 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_22 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_22 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_22 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_21 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_21 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_21 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_21 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_19 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_17 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_17)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_21)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_21)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_21)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_22)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_21)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_22)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_22)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_21)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_lo_22)
node decoded_addr_decoded_decoded_andMatrixOutputs_34_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_22)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_23 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_23 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_23 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_23 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_23 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_22 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_22 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_22 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_22 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_20 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_18 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_18)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_22)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_22)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_22)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_23)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_22)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_23)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_23)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_22)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_lo_23)
node decoded_addr_decoded_decoded_andMatrixOutputs_138_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_23)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_24 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_24 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_24 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_24 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_24 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_23 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_23 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_23 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_23 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_21 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_19 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_14 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_19)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_14)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_23)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_23)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_23)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_24)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_23)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_24)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_24)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_23)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_lo_24)
node decoded_addr_decoded_decoded_andMatrixOutputs_55_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_24)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_25 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_25 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_25 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_25 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_25 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_24 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_24 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_24 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_24 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_22 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_20 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_15 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_20)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_15)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_24)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_24)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_24)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_25)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_24)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_25)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_25)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_24)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_lo_25)
node decoded_addr_decoded_decoded_andMatrixOutputs_107_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_25)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_26 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_26 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_26 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_26 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_26 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_25 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_25 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_25 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_25 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_23 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_21 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_16 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_21)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_16)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_25)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_25)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_25)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_26)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_25)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_26)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_26)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_25)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_lo_26)
node decoded_addr_decoded_decoded_andMatrixOutputs_111_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_26)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_27 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_27 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_27 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_27 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_27 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_26 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_26 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_26 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_26 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_24 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_22 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_17 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_22)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_17)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_26)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_26)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_26)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_27)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_26)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_27)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_27)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_26)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_lo_27)
node decoded_addr_decoded_decoded_andMatrixOutputs_7_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_27)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_28 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_28 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_28 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_28 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_28 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_27 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_27 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_27 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_27 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_25 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_23 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_18 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_23)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_18)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_27)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_27)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_27)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_28)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_27)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_28)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_28)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_27)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_lo_28)
node decoded_addr_decoded_decoded_andMatrixOutputs_47_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_28)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_29 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_29 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_29 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_29 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_29 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_28 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_28 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_28 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_28 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_26 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_24 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_19 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_24)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_19)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_28)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_28)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_28)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_29)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_28)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_29)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_29)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_28)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_lo_29)
node decoded_addr_decoded_decoded_andMatrixOutputs_143_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_29)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_30 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_30 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_30 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_30 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_30 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_29 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_29 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_29 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_29 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_27 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_25 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_20 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_25)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_20)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_29)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_29)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_29)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_30)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_29)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_30)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_30)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_29)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_lo_30)
node decoded_addr_decoded_decoded_andMatrixOutputs_11_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_30)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_31 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_31 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_31 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_31 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_31 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_30 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_30 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_30 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_30 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_28 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_26 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_21 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_26)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_21)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_30)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_30)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_30)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_31)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_30)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_31)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_31)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_30)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_lo_31)
node decoded_addr_decoded_decoded_andMatrixOutputs_120_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_31)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_32 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_32 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_32 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_32 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_32 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_31 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_31 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_31 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_31 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_29 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_27 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_22 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_27)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_22)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_31)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_31)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_31)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_32)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_31)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_32)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_32)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_31)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_lo_32)
node decoded_addr_decoded_decoded_andMatrixOutputs_122_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_32)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_33 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_33 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_33 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_33 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_33 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_32 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_32 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_32 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_32 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_30 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_28 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_23 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_28)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_23)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_32)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_32)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_32)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_33)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_32)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_33)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_33)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_32)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_lo_33)
node decoded_addr_decoded_decoded_andMatrixOutputs_141_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_33)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_34 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_34 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_34 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_34 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_34 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_33 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_33 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_33 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_33 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_31 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_29 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_24 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_29)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_24)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_33)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_33)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_33)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_34)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_33)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_34)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_34)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_33)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_lo_34)
node decoded_addr_decoded_decoded_andMatrixOutputs_86_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_34)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_35 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_35 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_35 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_35 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_35 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_34 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_34 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_34 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_34 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_32 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_30 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_25 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_30)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_25)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_34)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_34)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_34)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_35)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_34)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_35)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_35)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_34)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_lo_35)
node decoded_addr_decoded_decoded_andMatrixOutputs_8_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_35)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_36 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_36 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_36 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_36 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_36 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_35 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_35 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_35 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_35 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_33 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_31 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_26 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_31)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_26)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_35)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_35)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_35)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_36)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_35)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_36)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_36)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_35)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_lo_36)
node decoded_addr_decoded_decoded_andMatrixOutputs_61_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_36)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_37 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_37 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_37 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_37 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_37 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_36 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_36 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_36 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_36 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_34 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_32 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_27 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_32)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_27)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_36)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_36)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_36)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_37)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_36)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_37)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_37)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_36)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_lo_37)
node decoded_addr_decoded_decoded_andMatrixOutputs_83_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_37)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_38 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_38 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_38 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_38 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_38 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_37 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_37 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_37 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_37 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_35 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_33 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_28 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_33)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_28)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_37)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_37)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_37)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_38)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_37)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_38)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_38)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_37)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_lo_38)
node decoded_addr_decoded_decoded_andMatrixOutputs_131_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_38)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_39 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_39 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_39 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_39 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_39 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_38 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_38 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_38 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_38 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_36 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_34 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_29 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_34)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_29)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_38)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_38)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_38)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_39)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_38)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_39)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_39)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_38)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_lo_39)
node decoded_addr_decoded_decoded_andMatrixOutputs_17_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_39)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_40 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_40 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_40 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_40 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_40 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_39 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_39 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_39 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_39 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_37 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_35 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_30 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_35)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_30)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_39)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_39)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_39)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_40)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_39)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_40)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_40)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_39)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_lo_40)
node decoded_addr_decoded_decoded_andMatrixOutputs_87_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_40)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_41 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_41 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_41 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_41 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_41 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_40 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_40 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_40 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_40 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_38 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_36 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_31 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_36)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_31)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_40)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_40)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_40)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_41)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_40)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_41)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_41)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_40)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_lo_41)
node decoded_addr_decoded_decoded_andMatrixOutputs_135_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_41)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_42 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_42 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_42 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_42 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_42 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_41 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_41 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_41 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_41 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_39 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_37 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_32 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_37)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_32)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_41)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_41)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_41)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_42)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_41)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_42)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_42)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_41)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_lo_42)
node decoded_addr_decoded_decoded_andMatrixOutputs_144_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_42)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_43 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_43 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_43 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_43 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_43 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_42 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_42 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_42 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_42 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_40 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_38 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_33 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_38)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_33)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_42)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_42)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_42)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_43)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_42)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_43)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_43)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_42)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_lo_43)
node decoded_addr_decoded_decoded_andMatrixOutputs_22_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_43)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_44 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_44 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_44 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_44 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_44 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_43 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_43 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_43 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_43 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_41 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_39 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_34 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_39)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_34)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_43)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_43)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_43)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_44)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_43)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_44)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_44)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_43)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_lo_44)
node decoded_addr_decoded_decoded_andMatrixOutputs_94_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_44)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_45 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_45 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_45 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_45 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_45 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_44 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_44 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_44 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_44 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_42 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_40 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_35 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_40)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_35)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_44)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_44)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_44)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_45)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_44)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_45)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_45)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_44)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_lo_45)
node decoded_addr_decoded_decoded_andMatrixOutputs_65_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_45)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_46 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_46 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_46 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_46 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_46 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_45 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_45 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_45 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_45 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_43 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_41 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_36 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_41)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_36)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_45)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_45)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_45)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_46)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_45)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_46)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_46)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_45)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_lo_46)
node decoded_addr_decoded_decoded_andMatrixOutputs_36_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_46)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_47 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_47 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_47 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_47 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_47 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_46 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_46 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_46 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_46 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_44 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_42 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_37 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_42)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_37)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_46)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_46)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_46)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_47)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_46)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_47)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_47)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_46)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_lo_47)
node decoded_addr_decoded_decoded_andMatrixOutputs_33_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_47)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_48 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_48 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_48 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_48 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_48 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_47 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_47 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_47 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_47 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_45 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_43 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_38 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_43)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_38)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_47)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_47)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_47)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_48)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_47)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_48)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_48)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_47)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_lo_48)
node decoded_addr_decoded_decoded_andMatrixOutputs_63_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_48)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_49 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_49 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_49 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_49 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_49 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_48 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_48 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_48 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_48 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_46 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_44 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_39 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_44)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_39)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_48)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_48)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_48)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_49)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_48)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_49)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_49)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_48)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_lo_49)
node decoded_addr_decoded_decoded_andMatrixOutputs_39_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_49)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_50 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_50 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_50 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_50 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_50 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_49 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_49 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_49 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_49 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_47 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_45 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_40 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_45)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_40)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_49)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_49)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_49)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_50)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_49)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_50)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_50)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_49)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_lo_50)
node decoded_addr_decoded_decoded_andMatrixOutputs_32_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_50)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_51 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_51 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_51 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_51 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_51 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_50 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_50 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_50 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_50 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_48 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_46 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_41 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_46)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_41)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_50)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_50)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_50)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_51)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_50)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_51)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_51)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_50)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_lo_51)
node decoded_addr_decoded_decoded_andMatrixOutputs_146_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_51)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_52 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_52 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_52 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_52 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_52 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_51 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_51 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_51 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_51 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_49 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_47 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_42 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_47)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_42)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_51)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_51)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_51)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_52)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_51)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_52)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_52)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_51)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_lo_52)
node decoded_addr_decoded_decoded_andMatrixOutputs_66_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_52)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_53 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_53 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_53 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_53 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_53 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_52 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_52 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_52 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_52 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_50 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_48 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_43 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_48)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_43)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_52)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_52)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_52)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_53)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_52)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_53)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_53)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_52)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_lo_53)
node decoded_addr_decoded_decoded_andMatrixOutputs_108_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_53)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_54 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_54 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_54 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_54 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_54 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_53 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_53 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_53 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_53 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_51 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_49 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_44 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_49)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_44)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_53)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_53)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_53)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_54)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_53)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_54)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_54)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_53)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_lo_54)
node decoded_addr_decoded_decoded_andMatrixOutputs_80_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_54)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_55 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_55 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_55 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_55 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_55 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_54 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_54 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_54 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_54 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_52 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_50 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_45 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_50)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_45)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_54)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_54)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_54)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_55)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_54)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_55)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_55)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_54)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_lo_55)
node decoded_addr_decoded_decoded_andMatrixOutputs_124_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_55)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_56 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_56 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_56 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_56 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_56 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_55 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_55 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_55 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_55 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_53 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_53)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_55)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_55)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_55)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_56)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_56)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_56)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_55)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_lo_56)
node decoded_addr_decoded_decoded_andMatrixOutputs_121_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_56)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_57 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_57 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_57 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_57 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_57 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_56 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_56 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_56 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_56 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_54 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_51 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_51)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_56)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_56)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_56)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_57)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_56)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_57)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_57)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_56)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_lo_57)
node decoded_addr_decoded_decoded_andMatrixOutputs_67_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_57)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_58 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_58 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_58 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_58 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_58 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_57 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_57 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_57 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_57 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_55 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_52 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_52)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_57)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_57)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_57)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_58)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_57)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_58)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_58)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_57)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_lo_58)
node decoded_addr_decoded_decoded_andMatrixOutputs_48_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_58)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_59 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_59 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_59 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_59 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_59 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_58 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_58 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_58 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_58 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_56 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_53 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_46 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_53)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_46)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_58)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_58)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_58)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_59)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_58)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_59)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_59)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_58)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_lo_59)
node decoded_addr_decoded_decoded_andMatrixOutputs_10_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_59)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_60 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_60 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_60 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_60 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_60 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_59 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_59 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_59 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_59 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_57 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_54 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_47 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_54)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_47)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_59)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_59)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_59)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_60)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_59)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_60)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_60)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_59)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_lo_60)
node decoded_addr_decoded_decoded_andMatrixOutputs_45_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_60)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_61 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_61 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_61 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_61 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_61 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_60 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_60 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_60 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_60 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_58 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_55 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_48 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_55)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_48)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_60)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_60)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_60)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_61)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_60)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_61)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_61)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_60)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_lo_61)
node decoded_addr_decoded_decoded_andMatrixOutputs_18_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_61)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_62 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_62 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_62 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_62 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_62 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_61 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_61 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_61 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_61 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_59 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_56 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_49 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_56)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_49)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_61)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_61)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_61)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_62)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_61)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_62)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_62)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_61)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_lo_62)
node decoded_addr_decoded_decoded_andMatrixOutputs_88_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_62)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_63 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_63 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_63 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_63 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_63 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_62 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_62 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_62 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_62 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_60 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_57 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_50 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_57)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_50)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_62)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_62)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_62)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_63)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_62)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_63)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_63)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_62)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_lo_63)
node decoded_addr_decoded_decoded_andMatrixOutputs_57_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_63)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_64 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_64 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_64 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_64 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_64 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_63 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_63 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_63 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_63 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_61 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_58 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_51 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_58)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_51)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_63)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_63)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_63)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_64)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_63)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_64)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_64)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_63)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_lo_64)
node decoded_addr_decoded_decoded_andMatrixOutputs_85_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_64)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_65 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_65 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_65 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_65 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_65 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_64 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_64 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_64 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_64 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_62 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_59 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_52 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_59)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_52)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_64)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_64)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_64)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_65)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_64)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_65)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_65)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_64)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_lo_65)
node decoded_addr_decoded_decoded_andMatrixOutputs_101_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_65)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_66 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_66 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_66 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_66 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_66 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_65 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_65 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_65 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_65 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_63 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_60 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_53 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_60)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_53)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_65)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_65)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_65)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_66)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_65)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_66)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_66)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_65)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_lo_66)
node decoded_addr_decoded_decoded_andMatrixOutputs_113_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_66)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_67 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_67 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_67 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_67 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_67 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_66 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_66 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_66 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_66 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_64 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_61 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_54 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_61)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_54)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_66)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_66)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_66)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_67)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_66)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_67)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_67)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_66)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_lo_67)
node decoded_addr_decoded_decoded_andMatrixOutputs_93_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_67)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_68 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_68 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_68 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_68 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_68 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_67 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_67 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_67 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_67 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_65 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_62 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_55 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_62)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_55)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_67)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_67)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_67)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_68)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_67)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_68)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_68)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_67)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_lo_68)
node decoded_addr_decoded_decoded_andMatrixOutputs_139_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_68)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_69 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_69 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_69 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_69 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_69 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_68 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_68 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_68 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_68 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_66 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_63 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_56 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_63)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_56)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_68)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_68)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_68)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_69)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_68)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_69)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_69)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_68)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_lo_69)
node decoded_addr_decoded_decoded_andMatrixOutputs_72_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_69)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_70 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_70 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_70 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_70 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_70 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_69 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_69 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_69 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_69 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_67 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_64 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_57 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_64)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_57)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_69)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_69)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_69)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_70)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_69)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_70)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_70)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_69)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_lo_70)
node decoded_addr_decoded_decoded_andMatrixOutputs_42_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_70)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_71 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_71 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_71 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_71 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_71 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_70 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_70 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_70 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_70 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_68 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_65 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_58 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_65)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_58)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_70)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_70)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_70)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_71)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_70)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_71)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_71)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_70)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_lo_71)
node decoded_addr_decoded_decoded_andMatrixOutputs_147_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_71)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_72 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_72 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_72 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_72 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_72 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_71 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_71 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_71 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_71 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_69 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_66 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_59 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_66)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_59)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_71)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_71)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_71)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_72)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_71)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_72)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_72)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_71)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_lo_72)
node decoded_addr_decoded_decoded_andMatrixOutputs_99_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_72)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_73 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_73 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_73 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_73 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_73 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_72 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_72 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_72 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_72 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_70 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_67 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_60 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_67)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_60)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_72)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_72)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_72)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_73)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_72)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_73)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_73)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_72)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_lo_73)
node decoded_addr_decoded_decoded_andMatrixOutputs_115_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_73)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_74 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_74 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_74 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_74 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_74 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_73 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_73 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_73 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_73 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_71 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_68 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_61 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_68)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_61)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_73)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_73)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_73)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_74)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_73)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_74)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_74)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_73)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_lo_74)
node decoded_addr_decoded_decoded_andMatrixOutputs_151_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_74)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_75 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_75 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_75 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_75 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_75 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_74 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_74 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_74 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_74 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_72 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_69 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_62 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_69)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_62)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_74)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_74)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_74)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_75)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_74)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_75)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_75)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_74)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_lo_75)
node decoded_addr_decoded_decoded_andMatrixOutputs_2_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_75)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_76 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_76 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_76 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_76 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_76 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_75 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_75 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_75 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_75 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_73 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_70 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_63 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_70)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_63)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_75)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_75)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_75)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_76)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_75)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_76)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_76)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_75)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_lo_76)
node decoded_addr_decoded_decoded_andMatrixOutputs_148_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_76)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_77 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_77 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_77 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_77 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_77 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_76 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_76 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_76 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_76 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_74 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_71 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_64 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_71)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_64)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_76)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_76)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_76)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_77)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_76)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_77)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_77)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_76)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_lo_77)
node decoded_addr_decoded_decoded_andMatrixOutputs_130_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_77)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_78 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_78 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_78 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_78 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_78 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_77 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_77 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_77 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_77 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_75 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_72 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_65 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_72)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_65)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_77)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_77)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_77)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_78)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_77)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_78)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_78)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_77)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_lo_78)
node decoded_addr_decoded_decoded_andMatrixOutputs_56_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_78)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_79 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_79 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_79 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_79 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_79 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_78 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_78 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_78 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_78 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_76 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_73 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_66 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_73)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_66)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_78)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_78)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_78)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_79)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_78)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_79)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_79)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_78)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_lo_79)
node decoded_addr_decoded_decoded_andMatrixOutputs_3_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_79)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_80 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_80 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_80 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_80 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_80 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_79 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_79 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_79 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_79 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_77 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_74 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_67 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_74)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_67)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_79)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_79)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_79)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_80)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_79)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_80)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_80)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_79)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_lo_80)
node decoded_addr_decoded_decoded_andMatrixOutputs_50_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_80)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_81 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_81 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_81 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_81 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_81 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_80 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_80 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_80 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_80 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_78 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_75 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_75)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_80)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_80)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_80)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_81)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_80)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_81)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_81)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_80)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_lo_81)
node decoded_addr_decoded_decoded_andMatrixOutputs_23_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_81)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_82 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_82 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_82 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_82 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_82 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_81 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_82)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_81)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_82)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_82)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_lo_82)
node decoded_addr_decoded_decoded_andMatrixOutputs_12_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_82)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_83 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_83 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_83 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_83 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_83 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_82 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_81 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_81 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_81 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_81)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_81)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_81)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_83)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_83)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_83)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_81)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_lo_83)
node decoded_addr_decoded_decoded_andMatrixOutputs_102_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_83)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_84 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_84 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_84 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_84 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_84 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_83 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_82 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_82 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_82 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_82)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_82)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_82)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_84)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_84)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_84)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_82)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_lo_84)
node decoded_addr_decoded_decoded_andMatrixOutputs_97_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_84)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_85 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_85 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_85 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_85 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_85 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_84 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_83 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_83 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_83 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_79 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_76 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_76)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_83)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_83)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_83)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_85)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_84)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_85)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_85)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_83)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_lo_85)
node decoded_addr_decoded_decoded_andMatrixOutputs_76_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_85)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_86 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_86 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_86 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_86 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_86 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_85 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_84 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_84 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_84 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_80 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_77 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_68 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_77)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_68)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_84)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_84)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_84)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_86)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_85)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_86)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_86)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_84)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_lo_86)
node decoded_addr_decoded_decoded_andMatrixOutputs_79_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_86)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_87 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_87 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_87 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_87 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_87 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_86 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_85 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_85 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_85 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_81 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_78 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_69 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_78)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_69)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_85)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_85)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_85)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_87)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_86)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_87)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_87)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_85)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_lo_87)
node decoded_addr_decoded_decoded_andMatrixOutputs_95_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_87)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_88 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_88 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_88 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_88 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_88 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_87 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_86 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_86 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_86 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_82 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_79 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_70 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_79)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_70)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_86)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_86)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_86)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_88)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_87)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_88)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_88)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_86)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_lo_88)
node decoded_addr_decoded_decoded_andMatrixOutputs_26_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_88)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_89 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_89 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_89 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_89 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_89 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_88 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_87 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_87 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_87 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_83 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_80 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_71 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_80)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_71)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_87)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_87)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_87)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_89)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_88)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_89)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_89)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_87)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_lo_89)
node decoded_addr_decoded_decoded_andMatrixOutputs_126_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_89)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_90 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_90 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_90 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_90 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_90 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_89 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_88 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_88 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_88 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_84 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_81 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_72 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_81)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_72)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_88)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_88)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_88)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_90)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_89)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_90)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_90)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_88)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_lo_90)
node decoded_addr_decoded_decoded_andMatrixOutputs_149_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_90)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_91 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_91 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_91 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_91 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_91 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_90 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_89 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_89 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_89 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_85 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_82 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_73 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_82)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_73)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_89)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_89)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_89)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_91)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_90)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_91)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_91)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_89)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_lo_91)
node decoded_addr_decoded_decoded_andMatrixOutputs_77_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_91)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_92 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_92 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_92 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_92 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_92 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_91 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_90 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_90 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_90 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_86 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_83 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_74 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_83)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_74)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_90)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_90)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_90)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_92)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_91)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_92)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_92)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_90)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_lo_92)
node decoded_addr_decoded_decoded_andMatrixOutputs_142_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_92)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_93 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_93 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_93 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_93 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_93 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_92 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_91 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_91 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_91 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_87 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_84 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_75 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_84)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_75)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_91)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_91)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_91)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_93)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_92)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_93)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_93)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_91)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_lo_93)
node decoded_addr_decoded_decoded_andMatrixOutputs_44_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_93)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_94 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_94 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_94 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_94 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_94 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_93 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_92 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_92 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_92 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_88 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_85 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_76 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_85)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_76)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_92)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_92)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_92)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_94)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_93)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_94)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_94)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_92)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_lo_94)
node decoded_addr_decoded_decoded_andMatrixOutputs_31_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_94)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_95 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_95 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_95 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_95 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_95 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_94 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_93 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_93 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_93 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_89 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_86 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_77 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_86)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_77)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_93)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_93)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_93)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_95)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_94)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_95)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_95)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_93)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_lo_95)
node decoded_addr_decoded_decoded_andMatrixOutputs_62_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_95)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_96 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_96 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_96 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_96 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_96 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_95 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_94 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_94 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_94 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_90 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_87 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_78 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_87)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_78)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_94)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_94)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_94)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_96)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_95)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_96)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_96)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_94)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_lo_96)
node decoded_addr_decoded_decoded_andMatrixOutputs_58_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_96)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_97 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_97 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_97 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_97 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_97 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_96 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_95 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_95 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_95 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_91 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_88 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_79 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_88)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_79)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_95)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_95)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_95)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_97)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_96)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_97)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_97)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_95)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_lo_97)
node decoded_addr_decoded_decoded_andMatrixOutputs_134_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_97)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_98 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_98 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_98 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_98 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_98 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_97 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_96 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_96 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_96 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_92 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_89 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_80 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_89)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_80)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_96)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_96)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_96)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_98)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_97)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_98)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_98)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_96)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_lo_98)
node decoded_addr_decoded_decoded_andMatrixOutputs_9_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_98)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_99 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_99 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_99 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_99 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_99 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_98 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_97 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_97 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_97 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_93 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_90 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_81 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_90)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_81)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_97)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_97)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_97)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_99)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_98)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_99)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_99)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_97)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_lo_99)
node decoded_addr_decoded_decoded_andMatrixOutputs_117_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_99)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_100 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_100 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_100 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_100 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_100 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_99 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_98 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_98 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_98 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_94 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_91 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_82 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_91)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_82)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_98)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_98)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_98)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_100)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_99)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_100)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_100)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_98)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_lo_100)
node decoded_addr_decoded_decoded_andMatrixOutputs_5_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_100)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_101 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_101 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_101 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_101 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_101 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_100 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_99 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_99 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_99 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_95 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_92 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_83 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_92)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_83)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_99)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_99)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_99)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_101)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_100)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_101)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_101)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_99)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_lo_101)
node decoded_addr_decoded_decoded_andMatrixOutputs_71_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_101)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_102 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_102 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_102 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_102 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_102 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_101 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_100 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_100 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_100 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_96 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_93 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_84 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_93)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_84)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_100)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_100)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_100)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_102)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_101)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_102)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_102)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_100)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_lo_102)
node decoded_addr_decoded_decoded_andMatrixOutputs_132_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_102)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_103 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_103 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_103 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_103 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_103 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_102 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_101 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_101 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_101 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_97 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_94 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_85 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_94)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_85)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_101)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_101)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_101)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_103)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_102)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_103)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_103)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_101)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_lo_103)
node decoded_addr_decoded_decoded_andMatrixOutputs_104_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_103)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_104 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_104 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_104 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_104 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_104 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_103 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_102 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_102 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_102 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_98 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_95 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_86 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_95)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_86)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_102)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_102)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_102)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_104)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_103)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_104)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_104)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_102)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_lo_104)
node decoded_addr_decoded_decoded_andMatrixOutputs_4_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_104)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_105 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_105 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_105 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_105 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_105 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_104 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_103 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_103 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_103 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_99 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_96 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_87 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_96)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_87)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_103)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_103)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_103)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_105)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_104)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_105)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_105)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_103)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_lo_105)
node decoded_addr_decoded_decoded_andMatrixOutputs_29_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_105)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_106 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_106 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_106 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_106 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_106 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_105 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_104 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_104 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_104 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_100 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_97 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_88 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_97)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_88)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_104)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_104)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_104)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_106)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_105)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_106)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_106)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_104)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_lo_106)
node decoded_addr_decoded_decoded_andMatrixOutputs_16_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_106)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_107 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_107 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_107 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_107 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_107 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_106 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_105 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_105 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_105 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_101 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_98 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_89 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_98)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_89)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_105)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_105)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_105)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_107)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_106)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_107)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_107)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_105)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_lo_107)
node decoded_addr_decoded_decoded_andMatrixOutputs_145_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_107)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_108 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_108 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_108 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_108 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_108 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_107 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_106 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_106 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_106 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_102 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_99 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_90 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_99)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_90)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_106)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_106)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_106)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_108)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_107)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_108)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_108)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_106)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_lo_108)
node decoded_addr_decoded_decoded_andMatrixOutputs_133_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_108)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_109 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_109 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_109 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_109 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_109 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_108 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_107 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_107 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_107 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_103 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_100 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_91 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_100)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_91)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_107)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_107)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_107)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_109)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_108)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_109)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_109)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_107)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_lo_109)
node decoded_addr_decoded_decoded_andMatrixOutputs_14_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_109)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_110 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_110 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_110 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_110 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_110 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_109 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_108 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_108 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_108 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_104 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_101 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_92 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_101)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_92)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_108)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_108)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_108)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_110)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_109)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_110)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_110)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_108)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_lo_110)
node decoded_addr_decoded_decoded_andMatrixOutputs_90_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_110)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_111 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_111 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_111 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_111 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_111 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_110 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_109 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_109 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_109 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_105 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_102 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_93 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_102)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_93)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_109)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_109)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_109)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_111)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_110)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_111)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_111)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_109)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_lo_111)
node decoded_addr_decoded_decoded_andMatrixOutputs_98_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_111)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_112 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_112 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_112 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_112 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_112 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_111 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_110 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_110 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_110 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_106 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_103 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_94 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_103)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_94)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_110)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_110)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_110)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_112)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_111)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_112)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_112)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_110)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_lo_112)
node decoded_addr_decoded_decoded_andMatrixOutputs_60_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_112)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_113 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_113 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_113 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_113 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_113 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_112 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_111 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_111 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_111 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_107 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_104 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_95 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_104)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_95)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_111)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_111)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_111)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_113)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_112)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_113)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_113)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_111)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_lo_113)
node decoded_addr_decoded_decoded_andMatrixOutputs_96_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_113)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_114 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_114 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_114 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_114 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_114 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_113 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_112 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_112 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_112 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_108 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_105 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_96 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_105)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_96)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_112)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_112)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_112)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_114)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_113)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_114)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_114)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_112)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_lo_114)
node decoded_addr_decoded_decoded_andMatrixOutputs_54_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_114)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_115 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_115 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_115 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_115 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_115 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_114 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_113 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_113 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_113 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_109 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_106 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_97 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_106)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_97)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_113)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_113)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_113)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_115)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_114)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_115)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_115)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_113)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_lo_115)
node decoded_addr_decoded_decoded_andMatrixOutputs_128_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_115)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_116 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_116 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_116 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_116 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_116 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_115 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_114 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_114 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_114 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_110 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_107 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_107)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_114)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_114)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_114)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_116)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_115)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_116)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_116)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_114)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_lo_116)
node decoded_addr_decoded_decoded_andMatrixOutputs_49_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_116)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_117 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_117 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_117 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_117 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_117 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_116 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_115 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_115 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_115 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_111 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_108 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_98 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_108)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_98)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_115)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_115)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_115)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_117)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_116)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_117)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_117)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_115)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_lo_117)
node decoded_addr_decoded_decoded_andMatrixOutputs_52_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_117)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_118 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_118 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_118 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_118 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_118 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_117 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_116 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_116 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_116 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_112 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_109 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_99 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_109)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_99)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_116)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_116)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_116)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_118)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_117)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_118)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_118)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_116)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_lo_118)
node decoded_addr_decoded_decoded_andMatrixOutputs_20_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_118)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_119 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_119 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_119 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_119 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_119 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_118 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_117 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_117 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_117 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_113 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_110 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_100 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_110)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_100)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_117)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_117)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_117)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_119)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_118)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_119)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_119)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_117)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_lo_119)
node decoded_addr_decoded_decoded_andMatrixOutputs_109_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_119)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_120 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_120 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_120 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_120 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_120 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_119 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_118 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_118 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_118 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_114 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_111 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_101 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_111)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_101)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_118)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_118)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_118)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_120)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_119)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_120)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_120)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_118)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_lo_120)
node decoded_addr_decoded_decoded_andMatrixOutputs_6_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_120)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_121 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_121 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_121 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_121 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_121 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_120 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_119 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_119 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_119 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_115 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_112 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_102 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_112)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_102)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_119)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_119)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_119)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_121)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_120)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_121)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_121)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_119)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_lo_121)
node decoded_addr_decoded_decoded_andMatrixOutputs_21_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_121)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_122 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_122 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_122 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_122 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_122 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_121 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_120 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_120 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_120 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_116 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_113 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_103 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_113)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_103)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_120)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_120)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_120)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_122)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_121)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_122)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_122)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_120)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_lo_122)
node decoded_addr_decoded_decoded_andMatrixOutputs_30_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_122)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_123 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_123 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_123 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_123 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_123 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_122 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_121 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_121 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_121 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_117 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_114 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_104 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_114)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_104)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_121)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_121)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_121)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_123)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_122)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_123)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_123)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_121)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_lo_123)
node decoded_addr_decoded_decoded_andMatrixOutputs_129_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_123)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_124 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_124 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_124 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_124 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_124 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_123 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_122 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_122 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_122 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_118 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_115 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_105 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_115)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_105)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_122)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_122)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_122)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_124)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_123)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_124)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_124)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_122)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_lo_124)
node decoded_addr_decoded_decoded_andMatrixOutputs_35_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_124)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_125 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_125 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_125 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_125 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_125 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_124 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_123 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_123 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_123 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_119 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_116 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_106 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_116)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_106)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_123)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_123)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_123)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_125)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_124)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_125)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_125)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_123)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_lo_125)
node decoded_addr_decoded_decoded_andMatrixOutputs_73_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_125)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_126 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_126 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_126 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_126 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_126 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_125 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_124 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_124 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_124 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_120 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_117 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_107 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_117)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_107)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_124)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_124)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_124)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_126)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_125)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_126)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_126)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_124)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_lo_126)
node decoded_addr_decoded_decoded_andMatrixOutputs_53_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_126)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_127 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_127 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_127 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_127 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_127 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_126 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_125 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_125 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_125 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_121 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_118 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_108 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_118)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_108)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_125)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_125)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_125)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_127)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_126)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_127)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_127)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_125)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_lo_127)
node decoded_addr_decoded_decoded_andMatrixOutputs_137_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_127)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_128 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_128 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_128 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_128 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_128 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_127 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_126 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_126 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_126 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_122 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_119 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_109 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_119)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_109)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_126)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_126)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_126)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_128)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_127)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_128)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_128)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_126)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_lo_128)
node decoded_addr_decoded_decoded_andMatrixOutputs_37_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_128)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_129 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_129 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_129 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_129 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_129 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_128 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_127 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_127 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_127 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_123 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_120 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_110 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_120)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_110)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_127)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_127)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_127)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_129)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_128)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_129)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_129)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_127)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_lo_129)
node decoded_addr_decoded_decoded_andMatrixOutputs_25_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_129)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_130 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_130 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_130 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_130 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_130 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_129 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_128 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_128 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_128 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_124 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_121 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_111 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_121)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_111)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_128)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_128)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_128)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_130)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_129)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_130)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_130)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_128)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_lo_130)
node decoded_addr_decoded_decoded_andMatrixOutputs_64_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_130)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_131 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_131 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_131 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_131 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_131 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_130 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_129 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_129 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_129 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_125 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_122 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_112 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_122)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_112)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_129)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_129)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_129)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_131)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_130)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_131)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_131)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_129)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_lo_131)
node decoded_addr_decoded_decoded_andMatrixOutputs_19_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_131)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_132 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_132 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_132 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_132 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_132 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_131 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_130 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_130 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_130 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_126 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_123 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_113 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_123)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_113)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_130)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_130)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_130)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_132)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_131)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_132)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_132)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_130)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_lo_132)
node decoded_addr_decoded_decoded_andMatrixOutputs_114_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_132)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_133 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_133 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_133 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_133 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_133 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_132 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_131 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_131 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_131 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_127 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_124 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_114 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_124)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_114)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_131)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_131)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_131)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_133)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_132)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_133)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_133)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_131)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_lo_133)
node decoded_addr_decoded_decoded_andMatrixOutputs_110_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_133)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_134 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_134 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_134 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_134 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_134 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_133 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_132 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_132 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_132 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_128 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_125 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_115 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_125)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_115)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_132)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_132)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_132)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_134)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_133)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_134)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_134)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_132)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_lo_134)
node decoded_addr_decoded_decoded_andMatrixOutputs_150_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_134)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_135 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_135 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_135 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_135 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_135 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_134 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_133 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_133 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_133 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_129 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_126 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_116 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_126)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_116)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_133)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_133)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_133)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_135)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_134)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_135)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_135)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_133)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_lo_135)
node decoded_addr_decoded_decoded_andMatrixOutputs_69_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_135)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_136 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_136 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_136 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_136 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_136 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_135 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_134 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_134 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_134 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_130 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_127 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_117 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_127)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_117)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_134)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_134)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_134)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_136)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_135)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_136)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_136)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_134)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_lo_136)
node decoded_addr_decoded_decoded_andMatrixOutputs_105_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_136)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_137 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_137 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_137 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_137 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_137 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_136 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_135 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_135 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_135 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_131 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_128 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_118 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_128)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_118)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_135)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_135)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_135)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_137)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_136)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_137)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_137)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_135)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_lo_137)
node decoded_addr_decoded_decoded_andMatrixOutputs_100_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_137)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_138 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_138 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_138 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_138 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_138 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_137 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_136 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_136 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_136 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_132 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_129 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_119 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_129)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_119)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_136)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_136)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_136)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_138)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_137)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_138)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_138)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_136)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_lo_138)
node decoded_addr_decoded_decoded_andMatrixOutputs_127_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_138)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_139 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_139 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_139 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_139 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_139 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_138 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_137 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_137 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_137 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_133 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_130 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_120 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_130)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_120)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_137)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_137)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_137)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_139)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_138)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_139)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_139)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_137)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_lo_139)
node decoded_addr_decoded_decoded_andMatrixOutputs_119_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_139)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_140 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_140 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_140 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_140 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_140 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_139 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_138 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_138 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_138 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_134 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_131 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_121 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_131)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_121)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_138)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_138)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_138)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_140)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_139)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_140)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_140)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_138)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_lo_140)
node decoded_addr_decoded_decoded_andMatrixOutputs_46_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_140)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_141 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_141 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_141 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_141 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_141 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_140 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_139 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_139 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_139 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_135 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_132 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_122 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_132)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_122)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_139)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_139)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_139)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_141)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_140)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_141)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_141)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_139)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_lo_141)
node decoded_addr_decoded_decoded_andMatrixOutputs_15_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_141)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_142 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_142 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_142 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_142 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_142 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_141 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_140 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_140 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_140 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_136 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_133 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_123 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_133)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_123)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_140)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_140)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_140)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_142)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_141)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_142)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_142)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_140)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_lo_142)
node decoded_addr_decoded_decoded_andMatrixOutputs_51_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_142)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_143 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_143 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_143 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_143 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_143 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_142 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_141 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_141 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_141 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_137 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_134 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_124 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_134)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_124)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_141)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_141)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_141)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_143)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_142)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_143)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_143)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_141)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_lo_143)
node decoded_addr_decoded_decoded_andMatrixOutputs_43_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_143)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_144 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_144 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_144 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_144 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_144 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_143 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_142 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_142 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_142 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_138 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_135 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_125 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_135)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_125)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_142)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_142)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_142)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_144)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_143)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_144)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_144)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_142)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_lo_144)
node decoded_addr_decoded_decoded_andMatrixOutputs_70_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_144)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_145 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_145 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_145 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_145 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_145 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_144 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_143 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_143 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_143 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_139 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_136 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_126 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_136)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_126)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_143)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_143)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_143)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_145)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_144)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_145)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_145)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_143)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_lo_145)
node decoded_addr_decoded_decoded_andMatrixOutputs_78_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_145)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_146 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_146 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_146 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_146 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_146 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_145 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_144 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_144 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_144 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_140 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_137 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_127 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_137)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_127)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_144)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_144)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_144)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_146)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_145)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_146)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_146)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_144)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_lo_146)
node decoded_addr_decoded_decoded_andMatrixOutputs_112_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_146)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_147 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_147 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_147 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_147 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_147 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_146 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_145 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_145 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_145 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_141 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_138 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_138)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_145)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_145)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_145)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_147)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_146)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_147)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_147)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_145)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_lo_147)
node decoded_addr_decoded_decoded_andMatrixOutputs_103_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_147)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_148 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_148 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_148 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_148 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_148 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_147 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_146 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_146 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_146 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_142 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_139 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_128 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_139)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_128)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_146)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_146)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_146)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_148)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_147)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_148)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_148)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_146)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_lo_148)
node decoded_addr_decoded_decoded_andMatrixOutputs_38_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_148)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_149 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_149 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_149 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_149 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_149 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_148 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_147 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_147 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_147 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_143 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_140 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_129 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_140)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_129)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_147)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_147)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_147)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_149)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_148)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_149)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_149)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_147)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_lo_149)
node decoded_addr_decoded_decoded_andMatrixOutputs_13_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_149)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_150 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_150 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_150 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_150 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_150 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_149 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_148 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_148 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_148 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_144 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_141 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_130 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_141)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_130)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_148)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_148)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_150 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_148)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_150, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_150)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_149)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_150, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_150)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_150 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_150)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_150 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_150, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_148)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_150 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_150, decoded_addr_decoded_decoded_andMatrixOutputs_lo_150)
node decoded_addr_decoded_decoded_andMatrixOutputs_81_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_150)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_151 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_151 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_151 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_151 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_151 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_150 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_149 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_149 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_149 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_145 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_142 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_131 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_142)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_131)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_149)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_150 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_149)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_151 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_150, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_149)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_151, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_151)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_150)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_151, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_151)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_151 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_151)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_151 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_151, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_149)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_151 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_151, decoded_addr_decoded_decoded_andMatrixOutputs_lo_151)
node decoded_addr_decoded_decoded_andMatrixOutputs_75_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_151)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T = orr(decoded_addr_decoded_decoded_andMatrixOutputs_75_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_1 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_103_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_2 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_13_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_3 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_38_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_4 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_12_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_5 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_97_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_6 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_102_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_7 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_151_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_8 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_115_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_9 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_99_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_10 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_147_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_11 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_42_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_12 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_72_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_13 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_139_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_14 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_93_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_15 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_113_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_16 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_101_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_17 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_85_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_18 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_57_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_19 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_88_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_20 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_18_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_21 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_45_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_22 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_10_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_23 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_48_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_24 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_67_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_25 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_0_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_26 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_82_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_27 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_28_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_28 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_27_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_29 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_125_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_30 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_59_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_31 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_74_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_32 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_118_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_33 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_24_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_34 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_92_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_35 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_89_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_36 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_123_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_37 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_1_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_38 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_40_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_39 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_52_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_40 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_49_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_41 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_84_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_42 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_112_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_43 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_128_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_44 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_146_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_45 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_78_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_46 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_54_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_47 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_32_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_48 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_70_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_49 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_96_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_50 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_39_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_51 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_43_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_52 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_60_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_53 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_63_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_54 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_51_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_55 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_98_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_56 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_33_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_57 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_15_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_58 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_90_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_59 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_36_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_60 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_46_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_61 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_14_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_62 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_65_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_63 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_119_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_64 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_133_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_65 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_94_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_66 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_127_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_67 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_145_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_68 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_22_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_69 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_100_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_70 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_16_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_71 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_144_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_72 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_105_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_73 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_29_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_74 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_135_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_75 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_69_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_76 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_4_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_77 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_87_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_78 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_150_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_79 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_104_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_80 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_17_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_81 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_110_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_82 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_132_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_83 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_131_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_84 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_114_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_85 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_71_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_86 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_83_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_87 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_19_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_88 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_5_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_89 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_61_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_90 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_64_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_91 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_117_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_92 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_8_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_93 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_25_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_94 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_9_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_95 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_86_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_96 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_37_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_97 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_134_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_98 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_141_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_99 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_137_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_100 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_58_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_101 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_122_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_102 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_53_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_103 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_62_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_104 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_120_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_105 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_73_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_106 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_31_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_107 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_11_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_108 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_35_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_109 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_44_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_110 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_143_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_111 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_129_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_112 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_142_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_113 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_47_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_114 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_30_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_115 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_77_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_116 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_7_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_117 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_21_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_118 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_149_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_119 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_111_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_120 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_6_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_121 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_126_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_122 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_107_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_123 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_109_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_124 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_26_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_125 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_55_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_126 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_20_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_127 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_95_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_128 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_138_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_129 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_79_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_130 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_76_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_131 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_34_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_132 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_41_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_133 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_136_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_134 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_140_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_135 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_23_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_136 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_50_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_137 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_3_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_138 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_81_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_139 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_80_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_140 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_124_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_141 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_108_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_142 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_66_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_143 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_91_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_144 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_121_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_145 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_68_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_146 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_116_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_147 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_106_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_148 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_56_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_149 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_130_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_150 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_148_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_151 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_2_2)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_1, _decoded_addr_decoded_decoded_orMatrixOutputs_T)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_3, _decoded_addr_decoded_decoded_orMatrixOutputs_T_2)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_5, _decoded_addr_decoded_decoded_orMatrixOutputs_T_4)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_8, _decoded_addr_decoded_decoded_orMatrixOutputs_T_7)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_6)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_10, _decoded_addr_decoded_decoded_orMatrixOutputs_T_9)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_13, _decoded_addr_decoded_decoded_orMatrixOutputs_T_12)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_11)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_15, _decoded_addr_decoded_decoded_orMatrixOutputs_T_14)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_18, _decoded_addr_decoded_decoded_orMatrixOutputs_T_17)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_16)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_20, _decoded_addr_decoded_decoded_orMatrixOutputs_T_19)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_22, _decoded_addr_decoded_decoded_orMatrixOutputs_T_21)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_24, _decoded_addr_decoded_decoded_orMatrixOutputs_T_23)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_27, _decoded_addr_decoded_decoded_orMatrixOutputs_T_26)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_25)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_29, _decoded_addr_decoded_decoded_orMatrixOutputs_T_28)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_32, _decoded_addr_decoded_decoded_orMatrixOutputs_T_31)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_30)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_34, _decoded_addr_decoded_decoded_orMatrixOutputs_T_33)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_37, _decoded_addr_decoded_decoded_orMatrixOutputs_T_36)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_35)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_39, _decoded_addr_decoded_decoded_orMatrixOutputs_T_38)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_41, _decoded_addr_decoded_decoded_orMatrixOutputs_T_40)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_43, _decoded_addr_decoded_decoded_orMatrixOutputs_T_42)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_46, _decoded_addr_decoded_decoded_orMatrixOutputs_T_45)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_44)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_48, _decoded_addr_decoded_decoded_orMatrixOutputs_T_47)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_51, _decoded_addr_decoded_decoded_orMatrixOutputs_T_50)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_49)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_53, _decoded_addr_decoded_decoded_orMatrixOutputs_T_52)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_56, _decoded_addr_decoded_decoded_orMatrixOutputs_T_55)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_54)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_58, _decoded_addr_decoded_decoded_orMatrixOutputs_T_57)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_60, _decoded_addr_decoded_decoded_orMatrixOutputs_T_59)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_62, _decoded_addr_decoded_decoded_orMatrixOutputs_T_61)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_65, _decoded_addr_decoded_decoded_orMatrixOutputs_T_64)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_63)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_67, _decoded_addr_decoded_decoded_orMatrixOutputs_T_66)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_70, _decoded_addr_decoded_decoded_orMatrixOutputs_T_69)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_68)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_72, _decoded_addr_decoded_decoded_orMatrixOutputs_T_71)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_75, _decoded_addr_decoded_decoded_orMatrixOutputs_T_74)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_73)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_77, _decoded_addr_decoded_decoded_orMatrixOutputs_T_76)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_79, _decoded_addr_decoded_decoded_orMatrixOutputs_T_78)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_81, _decoded_addr_decoded_decoded_orMatrixOutputs_T_80)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_84, _decoded_addr_decoded_decoded_orMatrixOutputs_T_83)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_82)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_86, _decoded_addr_decoded_decoded_orMatrixOutputs_T_85)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_89, _decoded_addr_decoded_decoded_orMatrixOutputs_T_88)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_87)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_91, _decoded_addr_decoded_decoded_orMatrixOutputs_T_90)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_94, _decoded_addr_decoded_decoded_orMatrixOutputs_T_93)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_92)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_96, _decoded_addr_decoded_decoded_orMatrixOutputs_T_95)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_98, _decoded_addr_decoded_decoded_orMatrixOutputs_T_97)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_100, _decoded_addr_decoded_decoded_orMatrixOutputs_T_99)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_103, _decoded_addr_decoded_decoded_orMatrixOutputs_T_102)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_101)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_105, _decoded_addr_decoded_decoded_orMatrixOutputs_T_104)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_108, _decoded_addr_decoded_decoded_orMatrixOutputs_T_107)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_106)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_110, _decoded_addr_decoded_decoded_orMatrixOutputs_T_109)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_113, _decoded_addr_decoded_decoded_orMatrixOutputs_T_112)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_111)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_115, _decoded_addr_decoded_decoded_orMatrixOutputs_T_114)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_117, _decoded_addr_decoded_decoded_orMatrixOutputs_T_116)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_119, _decoded_addr_decoded_decoded_orMatrixOutputs_T_118)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_122, _decoded_addr_decoded_decoded_orMatrixOutputs_T_121)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_120)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_124, _decoded_addr_decoded_decoded_orMatrixOutputs_T_123)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_127, _decoded_addr_decoded_decoded_orMatrixOutputs_T_126)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_125)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_129, _decoded_addr_decoded_decoded_orMatrixOutputs_T_128)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_132, _decoded_addr_decoded_decoded_orMatrixOutputs_T_131)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_130)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_134, _decoded_addr_decoded_decoded_orMatrixOutputs_T_133)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_136, _decoded_addr_decoded_decoded_orMatrixOutputs_T_135)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_138, _decoded_addr_decoded_decoded_orMatrixOutputs_T_137)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_141, _decoded_addr_decoded_decoded_orMatrixOutputs_T_140)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_139)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_143, _decoded_addr_decoded_decoded_orMatrixOutputs_T_142)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_146, _decoded_addr_decoded_decoded_orMatrixOutputs_T_145)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_144)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_148, _decoded_addr_decoded_decoded_orMatrixOutputs_T_147)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_151, _decoded_addr_decoded_decoded_orMatrixOutputs_T_150)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_149)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 0, 0)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_1 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 1, 1)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_2 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 2, 2)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_3 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 3, 3)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_4 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 4, 4)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_5 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 5, 5)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_6 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 6, 6)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_7 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 7, 7)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_8 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 8, 8)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_9 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 9, 9)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_10 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 10, 10)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_11 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 11, 11)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_12 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 12, 12)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_13 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 13, 13)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_14 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 14, 14)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_15 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 15, 15)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_16 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 16, 16)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_17 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 17, 17)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_18 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 18, 18)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_19 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 19, 19)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_20 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 20, 20)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_21 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 21, 21)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_22 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 22, 22)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_23 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 23, 23)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_24 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 24, 24)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_25 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 25, 25)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_26 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 26, 26)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_27 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 27, 27)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_28 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 28, 28)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_29 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 29, 29)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_30 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 30, 30)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_31 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 31, 31)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_32 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 32, 32)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_33 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 33, 33)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_34 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 34, 34)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_35 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 35, 35)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_36 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 36, 36)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_37 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 37, 37)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_38 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 38, 38)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_39 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 39, 39)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_40 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 40, 40)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_41 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 41, 41)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_42 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 42, 42)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_43 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 43, 43)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_44 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 44, 44)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_45 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 45, 45)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_46 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 46, 46)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_47 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 47, 47)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_48 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 48, 48)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_49 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 49, 49)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_50 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 50, 50)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_51 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 51, 51)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_52 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 52, 52)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_53 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 53, 53)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_54 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 54, 54)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_55 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 55, 55)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_56 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 56, 56)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_57 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 57, 57)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_58 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 58, 58)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_59 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 59, 59)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_60 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 60, 60)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_61 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 61, 61)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_62 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 62, 62)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_63 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 63, 63)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_64 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 64, 64)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_65 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 65, 65)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_66 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 66, 66)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_67 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 67, 67)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_68 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 68, 68)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_69 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 69, 69)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_70 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 70, 70)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_71 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 71, 71)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_72 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 72, 72)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_73 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 73, 73)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_74 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 74, 74)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_75 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 75, 75)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_76 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 76, 76)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_77 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 77, 77)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_78 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 78, 78)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_79 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 79, 79)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_80 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 80, 80)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_81 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 81, 81)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_82 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 82, 82)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_83 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 83, 83)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_84 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 84, 84)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_85 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 85, 85)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_86 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 86, 86)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_87 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 87, 87)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_88 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 88, 88)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_89 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 89, 89)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_90 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 90, 90)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_91 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 91, 91)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_92 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 92, 92)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_93 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 93, 93)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_94 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 94, 94)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_95 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 95, 95)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_96 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 96, 96)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_97 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 97, 97)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_98 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 98, 98)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_99 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 99, 99)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_100 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 100, 100)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_101 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 101, 101)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_102 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 102, 102)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_103 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 103, 103)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_104 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 104, 104)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_105 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 105, 105)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_106 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 106, 106)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_107 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 107, 107)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_108 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 108, 108)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_109 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 109, 109)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_110 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 110, 110)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_111 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 111, 111)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_112 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 112, 112)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_113 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 113, 113)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_114 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 114, 114)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_115 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 115, 115)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_116 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 116, 116)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_117 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 117, 117)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_118 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 118, 118)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_119 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 119, 119)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_120 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 120, 120)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_121 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 121, 121)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_122 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 122, 122)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_123 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 123, 123)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_124 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 124, 124)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_125 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 125, 125)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_126 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 126, 126)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_127 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 127, 127)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_128 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 128, 128)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_129 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 129, 129)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_130 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 130, 130)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_131 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 131, 131)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_132 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 132, 132)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_133 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 133, 133)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_134 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 134, 134)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_135 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 135, 135)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_136 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 136, 136)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_137 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 137, 137)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_138 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 138, 138)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_139 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 139, 139)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_140 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 140, 140)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_141 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 141, 141)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_142 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 142, 142)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_143 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 143, 143)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_144 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 144, 144)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_145 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 145, 145)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_146 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 146, 146)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_147 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 147, 147)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_148 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 148, 148)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_149 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 149, 149)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_150 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 150, 150)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_151 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 151, 151)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_1, _decoded_addr_decoded_decoded_invMatrixOutputs_T)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_3, _decoded_addr_decoded_decoded_invMatrixOutputs_T_2)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_5, _decoded_addr_decoded_decoded_invMatrixOutputs_T_4)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_8, _decoded_addr_decoded_decoded_invMatrixOutputs_T_7)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_6)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_10, _decoded_addr_decoded_decoded_invMatrixOutputs_T_9)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_13, _decoded_addr_decoded_decoded_invMatrixOutputs_T_12)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_11)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_15, _decoded_addr_decoded_decoded_invMatrixOutputs_T_14)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_18, _decoded_addr_decoded_decoded_invMatrixOutputs_T_17)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_16)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_20, _decoded_addr_decoded_decoded_invMatrixOutputs_T_19)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_22, _decoded_addr_decoded_decoded_invMatrixOutputs_T_21)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_24, _decoded_addr_decoded_decoded_invMatrixOutputs_T_23)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_27, _decoded_addr_decoded_decoded_invMatrixOutputs_T_26)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_25)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_29, _decoded_addr_decoded_decoded_invMatrixOutputs_T_28)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_32, _decoded_addr_decoded_decoded_invMatrixOutputs_T_31)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_30)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_34, _decoded_addr_decoded_decoded_invMatrixOutputs_T_33)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_37, _decoded_addr_decoded_decoded_invMatrixOutputs_T_36)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_35)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_39, _decoded_addr_decoded_decoded_invMatrixOutputs_T_38)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_41, _decoded_addr_decoded_decoded_invMatrixOutputs_T_40)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_43, _decoded_addr_decoded_decoded_invMatrixOutputs_T_42)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_46, _decoded_addr_decoded_decoded_invMatrixOutputs_T_45)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_44)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_48, _decoded_addr_decoded_decoded_invMatrixOutputs_T_47)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_51, _decoded_addr_decoded_decoded_invMatrixOutputs_T_50)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_49)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_53, _decoded_addr_decoded_decoded_invMatrixOutputs_T_52)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_56, _decoded_addr_decoded_decoded_invMatrixOutputs_T_55)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_54)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_58, _decoded_addr_decoded_decoded_invMatrixOutputs_T_57)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_60, _decoded_addr_decoded_decoded_invMatrixOutputs_T_59)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_62, _decoded_addr_decoded_decoded_invMatrixOutputs_T_61)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_65, _decoded_addr_decoded_decoded_invMatrixOutputs_T_64)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_63)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_67, _decoded_addr_decoded_decoded_invMatrixOutputs_T_66)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_70, _decoded_addr_decoded_decoded_invMatrixOutputs_T_69)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_68)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_72, _decoded_addr_decoded_decoded_invMatrixOutputs_T_71)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_75, _decoded_addr_decoded_decoded_invMatrixOutputs_T_74)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_73)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_77, _decoded_addr_decoded_decoded_invMatrixOutputs_T_76)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_79, _decoded_addr_decoded_decoded_invMatrixOutputs_T_78)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_81, _decoded_addr_decoded_decoded_invMatrixOutputs_T_80)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_84, _decoded_addr_decoded_decoded_invMatrixOutputs_T_83)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_82)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_86, _decoded_addr_decoded_decoded_invMatrixOutputs_T_85)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_89, _decoded_addr_decoded_decoded_invMatrixOutputs_T_88)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_87)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_91, _decoded_addr_decoded_decoded_invMatrixOutputs_T_90)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_94, _decoded_addr_decoded_decoded_invMatrixOutputs_T_93)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_92)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_96, _decoded_addr_decoded_decoded_invMatrixOutputs_T_95)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_98, _decoded_addr_decoded_decoded_invMatrixOutputs_T_97)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_100, _decoded_addr_decoded_decoded_invMatrixOutputs_T_99)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_103, _decoded_addr_decoded_decoded_invMatrixOutputs_T_102)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_101)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_105, _decoded_addr_decoded_decoded_invMatrixOutputs_T_104)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_108, _decoded_addr_decoded_decoded_invMatrixOutputs_T_107)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_106)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_110, _decoded_addr_decoded_decoded_invMatrixOutputs_T_109)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_113, _decoded_addr_decoded_decoded_invMatrixOutputs_T_112)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_111)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_115, _decoded_addr_decoded_decoded_invMatrixOutputs_T_114)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_117, _decoded_addr_decoded_decoded_invMatrixOutputs_T_116)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_119, _decoded_addr_decoded_decoded_invMatrixOutputs_T_118)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_122, _decoded_addr_decoded_decoded_invMatrixOutputs_T_121)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_120)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_124, _decoded_addr_decoded_decoded_invMatrixOutputs_T_123)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_127, _decoded_addr_decoded_decoded_invMatrixOutputs_T_126)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_125)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_129, _decoded_addr_decoded_decoded_invMatrixOutputs_T_128)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_132, _decoded_addr_decoded_decoded_invMatrixOutputs_T_131)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_130)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_134, _decoded_addr_decoded_decoded_invMatrixOutputs_T_133)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_136, _decoded_addr_decoded_decoded_invMatrixOutputs_T_135)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_138, _decoded_addr_decoded_decoded_invMatrixOutputs_T_137)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_141, _decoded_addr_decoded_decoded_invMatrixOutputs_T_140)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_139)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_143, _decoded_addr_decoded_decoded_invMatrixOutputs_T_142)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_146, _decoded_addr_decoded_decoded_invMatrixOutputs_T_145)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_144)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_148, _decoded_addr_decoded_decoded_invMatrixOutputs_T_147)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_151, _decoded_addr_decoded_decoded_invMatrixOutputs_T_150)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_149)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo)
connect decoded_addr_decoded_decoded, decoded_addr_decoded_decoded_invMatrixOutputs
connect decoded_addr_decoded_decoded_plaInput, decoded_addr_addr
node decoded_addr_decoded_0 = bits(decoded_addr_decoded_decoded, 151, 151)
node decoded_addr_decoded_1 = bits(decoded_addr_decoded_decoded, 150, 150)
node decoded_addr_decoded_2 = bits(decoded_addr_decoded_decoded, 149, 149)
node decoded_addr_decoded_3 = bits(decoded_addr_decoded_decoded, 148, 148)
node decoded_addr_decoded_4 = bits(decoded_addr_decoded_decoded, 147, 147)
node decoded_addr_decoded_5 = bits(decoded_addr_decoded_decoded, 146, 146)
node decoded_addr_decoded_6 = bits(decoded_addr_decoded_decoded, 145, 145)
node decoded_addr_decoded_7 = bits(decoded_addr_decoded_decoded, 144, 144)
node decoded_addr_decoded_8 = bits(decoded_addr_decoded_decoded, 143, 143)
node decoded_addr_decoded_9 = bits(decoded_addr_decoded_decoded, 142, 142)
node decoded_addr_decoded_10 = bits(decoded_addr_decoded_decoded, 141, 141)
node decoded_addr_decoded_11 = bits(decoded_addr_decoded_decoded, 140, 140)
node decoded_addr_decoded_12 = bits(decoded_addr_decoded_decoded, 139, 139)
node decoded_addr_decoded_13 = bits(decoded_addr_decoded_decoded, 138, 138)
node decoded_addr_decoded_14 = bits(decoded_addr_decoded_decoded, 137, 137)
node decoded_addr_decoded_15 = bits(decoded_addr_decoded_decoded, 136, 136)
node decoded_addr_decoded_16 = bits(decoded_addr_decoded_decoded, 135, 135)
node decoded_addr_decoded_17 = bits(decoded_addr_decoded_decoded, 134, 134)
node decoded_addr_decoded_18 = bits(decoded_addr_decoded_decoded, 133, 133)
node decoded_addr_decoded_19 = bits(decoded_addr_decoded_decoded, 132, 132)
node decoded_addr_decoded_20 = bits(decoded_addr_decoded_decoded, 131, 131)
node decoded_addr_decoded_21 = bits(decoded_addr_decoded_decoded, 130, 130)
node decoded_addr_decoded_22 = bits(decoded_addr_decoded_decoded, 129, 129)
node decoded_addr_decoded_23 = bits(decoded_addr_decoded_decoded, 128, 128)
node decoded_addr_decoded_24 = bits(decoded_addr_decoded_decoded, 127, 127)
node decoded_addr_decoded_25 = bits(decoded_addr_decoded_decoded, 126, 126)
node decoded_addr_decoded_26 = bits(decoded_addr_decoded_decoded, 125, 125)
node decoded_addr_decoded_27 = bits(decoded_addr_decoded_decoded, 124, 124)
node decoded_addr_decoded_28 = bits(decoded_addr_decoded_decoded, 123, 123)
node decoded_addr_decoded_29 = bits(decoded_addr_decoded_decoded, 122, 122)
node decoded_addr_decoded_30 = bits(decoded_addr_decoded_decoded, 121, 121)
node decoded_addr_decoded_31 = bits(decoded_addr_decoded_decoded, 120, 120)
node decoded_addr_decoded_32 = bits(decoded_addr_decoded_decoded, 119, 119)
node decoded_addr_decoded_33 = bits(decoded_addr_decoded_decoded, 118, 118)
node decoded_addr_decoded_34 = bits(decoded_addr_decoded_decoded, 117, 117)
node decoded_addr_decoded_35 = bits(decoded_addr_decoded_decoded, 116, 116)
node decoded_addr_decoded_36 = bits(decoded_addr_decoded_decoded, 115, 115)
node decoded_addr_decoded_37 = bits(decoded_addr_decoded_decoded, 114, 114)
node decoded_addr_decoded_38 = bits(decoded_addr_decoded_decoded, 113, 113)
node decoded_addr_decoded_39 = bits(decoded_addr_decoded_decoded, 112, 112)
node decoded_addr_decoded_40 = bits(decoded_addr_decoded_decoded, 111, 111)
node decoded_addr_decoded_41 = bits(decoded_addr_decoded_decoded, 110, 110)
node decoded_addr_decoded_42 = bits(decoded_addr_decoded_decoded, 109, 109)
node decoded_addr_decoded_43 = bits(decoded_addr_decoded_decoded, 108, 108)
node decoded_addr_decoded_44 = bits(decoded_addr_decoded_decoded, 107, 107)
node decoded_addr_decoded_45 = bits(decoded_addr_decoded_decoded, 106, 106)
node decoded_addr_decoded_46 = bits(decoded_addr_decoded_decoded, 105, 105)
node decoded_addr_decoded_47 = bits(decoded_addr_decoded_decoded, 104, 104)
node decoded_addr_decoded_48 = bits(decoded_addr_decoded_decoded, 103, 103)
node decoded_addr_decoded_49 = bits(decoded_addr_decoded_decoded, 102, 102)
node decoded_addr_decoded_50 = bits(decoded_addr_decoded_decoded, 101, 101)
node decoded_addr_decoded_51 = bits(decoded_addr_decoded_decoded, 100, 100)
node decoded_addr_decoded_52 = bits(decoded_addr_decoded_decoded, 99, 99)
node decoded_addr_decoded_53 = bits(decoded_addr_decoded_decoded, 98, 98)
node decoded_addr_decoded_54 = bits(decoded_addr_decoded_decoded, 97, 97)
node decoded_addr_decoded_55 = bits(decoded_addr_decoded_decoded, 96, 96)
node decoded_addr_decoded_56 = bits(decoded_addr_decoded_decoded, 95, 95)
node decoded_addr_decoded_57 = bits(decoded_addr_decoded_decoded, 94, 94)
node decoded_addr_decoded_58 = bits(decoded_addr_decoded_decoded, 93, 93)
node decoded_addr_decoded_59 = bits(decoded_addr_decoded_decoded, 92, 92)
node decoded_addr_decoded_60 = bits(decoded_addr_decoded_decoded, 91, 91)
node decoded_addr_decoded_61 = bits(decoded_addr_decoded_decoded, 90, 90)
node decoded_addr_decoded_62 = bits(decoded_addr_decoded_decoded, 89, 89)
node decoded_addr_decoded_63 = bits(decoded_addr_decoded_decoded, 88, 88)
node decoded_addr_decoded_64 = bits(decoded_addr_decoded_decoded, 87, 87)
node decoded_addr_decoded_65 = bits(decoded_addr_decoded_decoded, 86, 86)
node decoded_addr_decoded_66 = bits(decoded_addr_decoded_decoded, 85, 85)
node decoded_addr_decoded_67 = bits(decoded_addr_decoded_decoded, 84, 84)
node decoded_addr_decoded_68 = bits(decoded_addr_decoded_decoded, 83, 83)
node decoded_addr_decoded_69 = bits(decoded_addr_decoded_decoded, 82, 82)
node decoded_addr_decoded_70 = bits(decoded_addr_decoded_decoded, 81, 81)
node decoded_addr_decoded_71 = bits(decoded_addr_decoded_decoded, 80, 80)
node decoded_addr_decoded_72 = bits(decoded_addr_decoded_decoded, 79, 79)
node decoded_addr_decoded_73 = bits(decoded_addr_decoded_decoded, 78, 78)
node decoded_addr_decoded_74 = bits(decoded_addr_decoded_decoded, 77, 77)
node decoded_addr_decoded_75 = bits(decoded_addr_decoded_decoded, 76, 76)
node decoded_addr_decoded_76 = bits(decoded_addr_decoded_decoded, 75, 75)
node decoded_addr_decoded_77 = bits(decoded_addr_decoded_decoded, 74, 74)
node decoded_addr_decoded_78 = bits(decoded_addr_decoded_decoded, 73, 73)
node decoded_addr_decoded_79 = bits(decoded_addr_decoded_decoded, 72, 72)
node decoded_addr_decoded_80 = bits(decoded_addr_decoded_decoded, 71, 71)
node decoded_addr_decoded_81 = bits(decoded_addr_decoded_decoded, 70, 70)
node decoded_addr_decoded_82 = bits(decoded_addr_decoded_decoded, 69, 69)
node decoded_addr_decoded_83 = bits(decoded_addr_decoded_decoded, 68, 68)
node decoded_addr_decoded_84 = bits(decoded_addr_decoded_decoded, 67, 67)
node decoded_addr_decoded_85 = bits(decoded_addr_decoded_decoded, 66, 66)
node decoded_addr_decoded_86 = bits(decoded_addr_decoded_decoded, 65, 65)
node decoded_addr_decoded_87 = bits(decoded_addr_decoded_decoded, 64, 64)
node decoded_addr_decoded_88 = bits(decoded_addr_decoded_decoded, 63, 63)
node decoded_addr_decoded_89 = bits(decoded_addr_decoded_decoded, 62, 62)
node decoded_addr_decoded_90 = bits(decoded_addr_decoded_decoded, 61, 61)
node decoded_addr_decoded_91 = bits(decoded_addr_decoded_decoded, 60, 60)
node decoded_addr_decoded_92 = bits(decoded_addr_decoded_decoded, 59, 59)
node decoded_addr_decoded_93 = bits(decoded_addr_decoded_decoded, 58, 58)
node decoded_addr_decoded_94 = bits(decoded_addr_decoded_decoded, 57, 57)
node decoded_addr_decoded_95 = bits(decoded_addr_decoded_decoded, 56, 56)
node decoded_addr_decoded_96 = bits(decoded_addr_decoded_decoded, 55, 55)
node decoded_addr_decoded_97 = bits(decoded_addr_decoded_decoded, 54, 54)
node decoded_addr_decoded_98 = bits(decoded_addr_decoded_decoded, 53, 53)
node decoded_addr_decoded_99 = bits(decoded_addr_decoded_decoded, 52, 52)
node decoded_addr_decoded_100 = bits(decoded_addr_decoded_decoded, 51, 51)
node decoded_addr_decoded_101 = bits(decoded_addr_decoded_decoded, 50, 50)
node decoded_addr_decoded_102 = bits(decoded_addr_decoded_decoded, 49, 49)
node decoded_addr_decoded_103 = bits(decoded_addr_decoded_decoded, 48, 48)
node decoded_addr_decoded_104 = bits(decoded_addr_decoded_decoded, 47, 47)
node decoded_addr_decoded_105 = bits(decoded_addr_decoded_decoded, 46, 46)
node decoded_addr_decoded_106 = bits(decoded_addr_decoded_decoded, 45, 45)
node decoded_addr_decoded_107 = bits(decoded_addr_decoded_decoded, 44, 44)
node decoded_addr_decoded_108 = bits(decoded_addr_decoded_decoded, 43, 43)
node decoded_addr_decoded_109 = bits(decoded_addr_decoded_decoded, 42, 42)
node decoded_addr_decoded_110 = bits(decoded_addr_decoded_decoded, 41, 41)
node decoded_addr_decoded_111 = bits(decoded_addr_decoded_decoded, 40, 40)
node decoded_addr_decoded_112 = bits(decoded_addr_decoded_decoded, 39, 39)
node decoded_addr_decoded_113 = bits(decoded_addr_decoded_decoded, 38, 38)
node decoded_addr_decoded_114 = bits(decoded_addr_decoded_decoded, 37, 37)
node decoded_addr_decoded_115 = bits(decoded_addr_decoded_decoded, 36, 36)
node decoded_addr_decoded_116 = bits(decoded_addr_decoded_decoded, 35, 35)
node decoded_addr_decoded_117 = bits(decoded_addr_decoded_decoded, 34, 34)
node decoded_addr_decoded_118 = bits(decoded_addr_decoded_decoded, 33, 33)
node decoded_addr_decoded_119 = bits(decoded_addr_decoded_decoded, 32, 32)
node decoded_addr_decoded_120 = bits(decoded_addr_decoded_decoded, 31, 31)
node decoded_addr_decoded_121 = bits(decoded_addr_decoded_decoded, 30, 30)
node decoded_addr_decoded_122 = bits(decoded_addr_decoded_decoded, 29, 29)
node decoded_addr_decoded_123 = bits(decoded_addr_decoded_decoded, 28, 28)
node decoded_addr_decoded_124 = bits(decoded_addr_decoded_decoded, 27, 27)
node decoded_addr_decoded_125 = bits(decoded_addr_decoded_decoded, 26, 26)
node decoded_addr_decoded_126 = bits(decoded_addr_decoded_decoded, 25, 25)
node decoded_addr_decoded_127 = bits(decoded_addr_decoded_decoded, 24, 24)
node decoded_addr_decoded_128 = bits(decoded_addr_decoded_decoded, 23, 23)
node decoded_addr_decoded_129 = bits(decoded_addr_decoded_decoded, 22, 22)
node decoded_addr_decoded_130 = bits(decoded_addr_decoded_decoded, 21, 21)
node decoded_addr_decoded_131 = bits(decoded_addr_decoded_decoded, 20, 20)
node decoded_addr_decoded_132 = bits(decoded_addr_decoded_decoded, 19, 19)
node decoded_addr_decoded_133 = bits(decoded_addr_decoded_decoded, 18, 18)
node decoded_addr_decoded_134 = bits(decoded_addr_decoded_decoded, 17, 17)
node decoded_addr_decoded_135 = bits(decoded_addr_decoded_decoded, 16, 16)
node decoded_addr_decoded_136 = bits(decoded_addr_decoded_decoded, 15, 15)
node decoded_addr_decoded_137 = bits(decoded_addr_decoded_decoded, 14, 14)
node decoded_addr_decoded_138 = bits(decoded_addr_decoded_decoded, 13, 13)
node decoded_addr_decoded_139 = bits(decoded_addr_decoded_decoded, 12, 12)
node decoded_addr_decoded_140 = bits(decoded_addr_decoded_decoded, 11, 11)
node decoded_addr_decoded_141 = bits(decoded_addr_decoded_decoded, 10, 10)
node decoded_addr_decoded_142 = bits(decoded_addr_decoded_decoded, 9, 9)
node decoded_addr_decoded_143 = bits(decoded_addr_decoded_decoded, 8, 8)
node decoded_addr_decoded_144 = bits(decoded_addr_decoded_decoded, 7, 7)
node decoded_addr_decoded_145 = bits(decoded_addr_decoded_decoded, 6, 6)
node decoded_addr_decoded_146 = bits(decoded_addr_decoded_decoded, 5, 5)
node decoded_addr_decoded_147 = bits(decoded_addr_decoded_decoded, 4, 4)
node decoded_addr_decoded_148 = bits(decoded_addr_decoded_decoded, 3, 3)
node decoded_addr_decoded_149 = bits(decoded_addr_decoded_decoded, 2, 2)
node decoded_addr_decoded_150 = bits(decoded_addr_decoded_decoded, 1, 1)
node decoded_addr_decoded_151 = bits(decoded_addr_decoded_decoded, 0, 0)
node decoded_addr_98_2 = bits(decoded_addr_decoded_0, 0, 0)
node decoded_addr_55_2 = bits(decoded_addr_decoded_1, 0, 0)
node decoded_addr_10_2 = bits(decoded_addr_decoded_2, 0, 0)
node decoded_addr_120_2 = bits(decoded_addr_decoded_3, 0, 0)
node decoded_addr_95_2 = bits(decoded_addr_decoded_4, 0, 0)
node decoded_addr_101_2 = bits(decoded_addr_decoded_5, 0, 0)
node decoded_addr_72_2 = bits(decoded_addr_decoded_6, 0, 0)
node decoded_addr_109_2 = bits(decoded_addr_decoded_7, 0, 0)
node decoded_addr_77_2 = bits(decoded_addr_decoded_8, 0, 0)
node decoded_addr_131_2 = bits(decoded_addr_decoded_9, 0, 0)
node decoded_addr_134_2 = bits(decoded_addr_decoded_10, 0, 0)
node decoded_addr_138_2 = bits(decoded_addr_decoded_11, 0, 0)
node decoded_addr_29_2 = bits(decoded_addr_decoded_12, 0, 0)
node decoded_addr_133_2 = bits(decoded_addr_decoded_13, 0, 0)
node decoded_addr_49_2 = bits(decoded_addr_decoded_14, 0, 0)
node decoded_addr_90_2 = bits(decoded_addr_decoded_15, 0, 0)
node decoded_addr_57_2 = bits(decoded_addr_decoded_16, 0, 0)
node decoded_addr_36_2 = bits(decoded_addr_decoded_17, 0, 0)
node decoded_addr_68_2 = bits(decoded_addr_decoded_18, 0, 0)
node decoded_addr_100_2 = bits(decoded_addr_decoded_19, 0, 0)
node decoded_addr_132_2 = bits(decoded_addr_decoded_20, 0, 0)
node decoded_addr_104_2 = bits(decoded_addr_decoded_21, 0, 0)
node decoded_addr_123_2 = bits(decoded_addr_decoded_22, 0, 0)
node decoded_addr_148_2 = bits(decoded_addr_decoded_23, 0, 0)
node decoded_addr_17_2 = bits(decoded_addr_decoded_24, 0, 0)
node decoded_addr_27_2 = bits(decoded_addr_decoded_25, 0, 0)
node decoded_addr_84_2 = bits(decoded_addr_decoded_26, 0, 0)
node decoded_addr_52_2 = bits(decoded_addr_decoded_27, 0, 0)
node decoded_addr_146_2 = bits(decoded_addr_decoded_28, 0, 0)
node decoded_addr_70_2 = bits(decoded_addr_decoded_29, 0, 0)
node decoded_addr_112_2 = bits(decoded_addr_decoded_30, 0, 0)
node decoded_addr_83_2 = bits(decoded_addr_decoded_31, 0, 0)
node decoded_addr_31_2 = bits(decoded_addr_decoded_32, 0, 0)
node decoded_addr_0_2 = bits(decoded_addr_decoded_33, 0, 0)
node decoded_addr_59_2 = bits(decoded_addr_decoded_34, 0, 0)
node decoded_addr_140_2 = bits(decoded_addr_decoded_35, 0, 0)
node decoded_addr_128_2 = bits(decoded_addr_decoded_36, 0, 0)
node decoded_addr_74_2 = bits(decoded_addr_decoded_37, 0, 0)
node decoded_addr_117_2 = bits(decoded_addr_decoded_38, 0, 0)
node decoded_addr_91_2 = bits(decoded_addr_decoded_39, 0, 0)
node decoded_addr_114_2 = bits(decoded_addr_decoded_40, 0, 0)
node decoded_addr_1_2 = bits(decoded_addr_decoded_41, 0, 0)
node decoded_addr_16_2 = bits(decoded_addr_decoded_42, 0, 0)
node decoded_addr_79_2 = bits(decoded_addr_decoded_43, 0, 0)
node decoded_addr_39_2 = bits(decoded_addr_decoded_44, 0, 0)
node decoded_addr_51_2 = bits(decoded_addr_decoded_45, 0, 0)
node decoded_addr_110_2 = bits(decoded_addr_decoded_46, 0, 0)
node decoded_addr_92_2 = bits(decoded_addr_decoded_47, 0, 0)
node decoded_addr_82_2 = bits(decoded_addr_decoded_48, 0, 0)
node decoded_addr_67_2 = bits(decoded_addr_decoded_49, 0, 0)
node decoded_addr_106_2 = bits(decoded_addr_decoded_50, 0, 0)
node decoded_addr_124_2 = bits(decoded_addr_decoded_51, 0, 0)
node decoded_addr_24_2 = bits(decoded_addr_decoded_52, 0, 0)
node decoded_addr_126_2 = bits(decoded_addr_decoded_53, 0, 0)
node decoded_addr_26_2 = bits(decoded_addr_decoded_54, 0, 0)
node decoded_addr_130_2 = bits(decoded_addr_decoded_55, 0, 0)
node decoded_addr_7_2 = bits(decoded_addr_decoded_56, 0, 0)
node decoded_addr_62_2 = bits(decoded_addr_decoded_57, 0, 0)
node decoded_addr_78_2 = bits(decoded_addr_decoded_58, 0, 0)
node decoded_addr_46_2 = bits(decoded_addr_decoded_59, 0, 0)
node decoded_addr_113_2 = bits(decoded_addr_decoded_60, 0, 0)
node decoded_addr_60_2 = bits(decoded_addr_decoded_61, 0, 0)
node decoded_addr_93_2 = bits(decoded_addr_decoded_62, 0, 0)
node decoded_addr_150_2 = bits(decoded_addr_decoded_63, 0, 0)
node decoded_addr_14_2 = bits(decoded_addr_decoded_64, 0, 0)
node decoded_addr_21_2 = bits(decoded_addr_decoded_65, 0, 0)
node decoded_addr_33_2 = bits(decoded_addr_decoded_66, 0, 0)
node decoded_addr_19_2 = bits(decoded_addr_decoded_67, 0, 0)
node decoded_addr_135_2 = bits(decoded_addr_decoded_68, 0, 0)
node decoded_addr_151_2 = bits(decoded_addr_decoded_69, 0, 0)
node decoded_addr_50_2 = bits(decoded_addr_decoded_70, 0, 0)
node decoded_addr_75_2 = bits(decoded_addr_decoded_71, 0, 0)
node decoded_addr_103_2 = bits(decoded_addr_decoded_72, 0, 0)
node decoded_addr_85_2 = bits(decoded_addr_decoded_73, 0, 0)
node decoded_addr_45_2 = bits(decoded_addr_decoded_74, 0, 0)
node decoded_addr_64_2 = bits(decoded_addr_decoded_75, 0, 0)
node decoded_addr_122_2 = bits(decoded_addr_decoded_76, 0, 0)
node decoded_addr_30_2 = bits(decoded_addr_decoded_77, 0, 0)
node decoded_addr_5_2 = bits(decoded_addr_decoded_78, 0, 0)
node decoded_addr_32_2 = bits(decoded_addr_decoded_79, 0, 0)
node decoded_addr_145_2 = bits(decoded_addr_decoded_80, 0, 0)
node decoded_addr_119_2 = bits(decoded_addr_decoded_81, 0, 0)
node decoded_addr_63_2 = bits(decoded_addr_decoded_82, 0, 0)
node decoded_addr_108_2 = bits(decoded_addr_decoded_83, 0, 0)
node decoded_addr_89_2 = bits(decoded_addr_decoded_84, 0, 0)
node decoded_addr_115_2 = bits(decoded_addr_decoded_85, 0, 0)
node decoded_addr_73_2 = bits(decoded_addr_decoded_86, 0, 0)
node decoded_addr_53_2 = bits(decoded_addr_decoded_87, 0, 0)
node decoded_addr_149_2 = bits(decoded_addr_decoded_88, 0, 0)
node decoded_addr_41_2 = bits(decoded_addr_decoded_89, 0, 0)
node decoded_addr_56_2 = bits(decoded_addr_decoded_90, 0, 0)
node decoded_addr_37_2 = bits(decoded_addr_decoded_91, 0, 0)
node decoded_addr_80_2 = bits(decoded_addr_decoded_92, 0, 0)
node decoded_addr_97_2 = bits(decoded_addr_decoded_93, 0, 0)
node decoded_addr_4_2 = bits(decoded_addr_decoded_94, 0, 0)
node decoded_addr_102_2 = bits(decoded_addr_decoded_95, 0, 0)
node decoded_addr_121_2 = bits(decoded_addr_decoded_96, 0, 0)
node decoded_addr_22_2 = bits(decoded_addr_decoded_97, 0, 0)
node decoded_addr_141_2 = bits(decoded_addr_decoded_98, 0, 0)
node decoded_addr_11_2 = bits(decoded_addr_decoded_99, 0, 0)
node decoded_addr_136_2 = bits(decoded_addr_decoded_100, 0, 0)
node decoded_addr_12_2 = bits(decoded_addr_decoded_101, 0, 0)
node decoded_addr_65_2 = bits(decoded_addr_decoded_102, 0, 0)
node decoded_addr_87_2 = bits(decoded_addr_decoded_103, 0, 0)
node decoded_addr_47_2 = bits(decoded_addr_decoded_104, 0, 0)
node decoded_addr_107_2 = bits(decoded_addr_decoded_105, 0, 0)
node decoded_addr_58_2 = bits(decoded_addr_decoded_106, 0, 0)
node decoded_addr_88_2 = bits(decoded_addr_decoded_107, 0, 0)
node decoded_addr_144_2 = bits(decoded_addr_decoded_108, 0, 0)
node decoded_addr_13_2 = bits(decoded_addr_decoded_109, 0, 0)
node decoded_addr_35_2 = bits(decoded_addr_decoded_110, 0, 0)
node decoded_addr_2_2 = bits(decoded_addr_decoded_111, 0, 0)
node decoded_addr_66_2 = bits(decoded_addr_decoded_112, 0, 0)
node decoded_addr_42_2 = bits(decoded_addr_decoded_113, 0, 0)
node decoded_addr_61_2 = bits(decoded_addr_decoded_114, 0, 0)
node decoded_addr_48_2 = bits(decoded_addr_decoded_115, 0, 0)
node decoded_addr_44_2 = bits(decoded_addr_decoded_116, 0, 0)
node decoded_addr_15_2 = bits(decoded_addr_decoded_117, 0, 0)
node decoded_addr_147_2 = bits(decoded_addr_decoded_118, 0, 0)
node decoded_addr_94_2 = bits(decoded_addr_decoded_119, 0, 0)
node decoded_addr_6_2 = bits(decoded_addr_decoded_120, 0, 0)
node decoded_addr_28_2 = bits(decoded_addr_decoded_121, 0, 0)
node decoded_addr_25_2 = bits(decoded_addr_decoded_122, 0, 0)
node decoded_addr_139_2 = bits(decoded_addr_decoded_123, 0, 0)
node decoded_addr_125_2 = bits(decoded_addr_decoded_124, 0, 0)
node decoded_addr_23_2 = bits(decoded_addr_decoded_125, 0, 0)
node decoded_addr_69_2 = bits(decoded_addr_decoded_126, 0, 0)
node decoded_addr_143_2 = bits(decoded_addr_decoded_127, 0, 0)
node decoded_addr_9_2 = bits(decoded_addr_decoded_128, 0, 0)
node decoded_addr_105_2 = bits(decoded_addr_decoded_129, 0, 0)
node decoded_addr_8_2 = bits(decoded_addr_decoded_130, 0, 0)
node decoded_addr_127_2 = bits(decoded_addr_decoded_131, 0, 0)
node decoded_addr_86_2 = bits(decoded_addr_decoded_132, 0, 0)
node decoded_addr_54_2 = bits(decoded_addr_decoded_133, 0, 0)
node decoded_addr_20_2 = bits(decoded_addr_decoded_134, 0, 0)
node decoded_addr_137_2 = bits(decoded_addr_decoded_135, 0, 0)
node decoded_addr_116_2 = bits(decoded_addr_decoded_136, 0, 0)
node decoded_addr_43_2 = bits(decoded_addr_decoded_137, 0, 0)
node decoded_addr_71_2 = bits(decoded_addr_decoded_138, 0, 0)
node decoded_addr_111_2 = bits(decoded_addr_decoded_139, 0, 0)
node decoded_addr_142_2 = bits(decoded_addr_decoded_140, 0, 0)
node decoded_addr_34_2 = bits(decoded_addr_decoded_141, 0, 0)
node decoded_addr_40_2 = bits(decoded_addr_decoded_142, 0, 0)
node decoded_addr_81_2 = bits(decoded_addr_decoded_143, 0, 0)
node decoded_addr_99_2 = bits(decoded_addr_decoded_144, 0, 0)
node decoded_addr_76_2 = bits(decoded_addr_decoded_145, 0, 0)
node decoded_addr_118_2 = bits(decoded_addr_decoded_146, 0, 0)
node decoded_addr_18_2 = bits(decoded_addr_decoded_147, 0, 0)
node decoded_addr_3_2 = bits(decoded_addr_decoded_148, 0, 0)
node decoded_addr_129_2 = bits(decoded_addr_decoded_149, 0, 0)
node decoded_addr_38_2 = bits(decoded_addr_decoded_150, 0, 0)
node decoded_addr_96_2 = bits(decoded_addr_decoded_151, 0, 0)
node _wdata_T = bits(io.rw.cmd, 1, 1)
node _wdata_T_1 = mux(_wdata_T, io.rw.rdata, UInt<1>(0h0))
node _wdata_T_2 = or(_wdata_T_1, io.rw.wdata)
node _wdata_T_3 = bits(io.rw.cmd, 1, 0)
node _wdata_T_4 = andr(_wdata_T_3)
node _wdata_T_5 = mux(_wdata_T_4, io.rw.wdata, UInt<1>(0h0))
node _wdata_T_6 = not(_wdata_T_5)
node wdata = and(_wdata_T_2, _wdata_T_6)
node system_insn = eq(io.rw.cmd, UInt<3>(0h4))
node _insn_T = shl(io.rw.addr, 20)
node insn = or(UInt<7>(0h73), _insn_T)
wire decoded_plaInput : UInt<32>
node decoded_invInputs = not(decoded_plaInput)
wire decoded : UInt<9>
node decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_invInputs, 20, 20)
node decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_invInputs, 21, 21)
node decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoded_invInputs, 22, 22)
node decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoded_invInputs, 23, 23)
node decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoded_invInputs, 24, 24)
node decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoded_invInputs, 25, 25)
node decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoded_invInputs, 26, 26)
node decoded_andMatrixOutputs_andMatrixInput_7 = bits(decoded_invInputs, 27, 27)
node decoded_andMatrixOutputs_andMatrixInput_8 = bits(decoded_invInputs, 28, 28)
node decoded_andMatrixOutputs_andMatrixInput_9 = bits(decoded_invInputs, 29, 29)
node decoded_andMatrixOutputs_andMatrixInput_10 = bits(decoded_invInputs, 30, 30)
node decoded_andMatrixOutputs_andMatrixInput_11 = bits(decoded_invInputs, 31, 31)
node decoded_andMatrixOutputs_lo_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_9, decoded_andMatrixOutputs_andMatrixInput_10)
node decoded_andMatrixOutputs_lo_lo = cat(decoded_andMatrixOutputs_lo_lo_hi, decoded_andMatrixOutputs_andMatrixInput_11)
node decoded_andMatrixOutputs_lo_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_6, decoded_andMatrixOutputs_andMatrixInput_7)
node decoded_andMatrixOutputs_lo_hi = cat(decoded_andMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_andMatrixInput_8)
node decoded_andMatrixOutputs_lo = cat(decoded_andMatrixOutputs_lo_hi, decoded_andMatrixOutputs_lo_lo)
node decoded_andMatrixOutputs_hi_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_3, decoded_andMatrixOutputs_andMatrixInput_4)
node decoded_andMatrixOutputs_hi_lo = cat(decoded_andMatrixOutputs_hi_lo_hi, decoded_andMatrixOutputs_andMatrixInput_5)
node decoded_andMatrixOutputs_hi_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1)
node decoded_andMatrixOutputs_hi_hi = cat(decoded_andMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2)
node decoded_andMatrixOutputs_hi = cat(decoded_andMatrixOutputs_hi_hi, decoded_andMatrixOutputs_hi_lo)
node _decoded_andMatrixOutputs_T = cat(decoded_andMatrixOutputs_hi, decoded_andMatrixOutputs_lo)
node decoded_andMatrixOutputs_6_2 = andr(_decoded_andMatrixOutputs_T)
node decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_plaInput, 20, 20)
node decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_invInputs, 21, 21)
node decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoded_invInputs, 22, 22)
node decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoded_invInputs, 23, 23)
node decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoded_invInputs, 24, 24)
node decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoded_invInputs, 25, 25)
node decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoded_invInputs, 26, 26)
node decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(decoded_invInputs, 27, 27)
node decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(decoded_invInputs, 28, 28)
node decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(decoded_invInputs, 29, 29)
node decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(decoded_invInputs, 30, 30)
node decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(decoded_invInputs, 31, 31)
node decoded_andMatrixOutputs_lo_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_andMatrixOutputs_andMatrixInput_10_1)
node decoded_andMatrixOutputs_lo_lo_1 = cat(decoded_andMatrixOutputs_lo_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_11_1)
node decoded_andMatrixOutputs_lo_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_andMatrixOutputs_andMatrixInput_7_1)
node decoded_andMatrixOutputs_lo_hi_1 = cat(decoded_andMatrixOutputs_lo_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_8_1)
node decoded_andMatrixOutputs_lo_1 = cat(decoded_andMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_lo_lo_1)
node decoded_andMatrixOutputs_hi_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_andMatrixOutputs_andMatrixInput_4_1)
node decoded_andMatrixOutputs_hi_lo_1 = cat(decoded_andMatrixOutputs_hi_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_5_1)
node decoded_andMatrixOutputs_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1)
node decoded_andMatrixOutputs_hi_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_1)
node decoded_andMatrixOutputs_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_hi_lo_1)
node _decoded_andMatrixOutputs_T_1 = cat(decoded_andMatrixOutputs_hi_1, decoded_andMatrixOutputs_lo_1)
node decoded_andMatrixOutputs_4_2 = andr(_decoded_andMatrixOutputs_T_1)
node decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_plaInput, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_invInputs, 22, 22)
node decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoded_invInputs, 23, 23)
node decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoded_invInputs, 24, 24)
node decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoded_invInputs, 25, 25)
node decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoded_invInputs, 26, 26)
node decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoded_invInputs, 27, 27)
node decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(decoded_plaInput, 28, 28)
node decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(decoded_invInputs, 30, 30)
node decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(decoded_invInputs, 31, 31)
node decoded_andMatrixOutputs_lo_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_8_2, decoded_andMatrixOutputs_andMatrixInput_9_2)
node decoded_andMatrixOutputs_lo_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_5_2, decoded_andMatrixOutputs_andMatrixInput_6_2)
node decoded_andMatrixOutputs_lo_hi_2 = cat(decoded_andMatrixOutputs_lo_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_7_2)
node decoded_andMatrixOutputs_lo_2 = cat(decoded_andMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_lo_lo_2)
node decoded_andMatrixOutputs_hi_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_andMatrixOutputs_andMatrixInput_4_2)
node decoded_andMatrixOutputs_hi_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2)
node decoded_andMatrixOutputs_hi_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_2_2)
node decoded_andMatrixOutputs_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_hi_lo_2)
node _decoded_andMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_hi_2, decoded_andMatrixOutputs_lo_2)
node decoded_andMatrixOutputs_3_2 = andr(_decoded_andMatrixOutputs_T_2)
node decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_plaInput, 22, 22)
node decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoded_invInputs, 23, 23)
node decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoded_invInputs, 24, 24)
node decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoded_invInputs, 25, 25)
node decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoded_invInputs, 26, 26)
node decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoded_invInputs, 27, 27)
node decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(decoded_plaInput, 28, 28)
node decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(decoded_invInputs, 29, 29)
node decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(decoded_invInputs, 30, 30)
node decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(decoded_invInputs, 31, 31)
node decoded_andMatrixOutputs_lo_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_andMatrixOutputs_andMatrixInput_9_3)
node decoded_andMatrixOutputs_lo_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_andMatrixOutputs_andMatrixInput_6_3)
node decoded_andMatrixOutputs_lo_hi_3 = cat(decoded_andMatrixOutputs_lo_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_7_3)
node decoded_andMatrixOutputs_lo_3 = cat(decoded_andMatrixOutputs_lo_hi_3, decoded_andMatrixOutputs_lo_lo_3)
node decoded_andMatrixOutputs_hi_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_andMatrixOutputs_andMatrixInput_4_3)
node decoded_andMatrixOutputs_hi_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_3)
node decoded_andMatrixOutputs_hi_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_2_3)
node decoded_andMatrixOutputs_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_hi_lo_3)
node _decoded_andMatrixOutputs_T_3 = cat(decoded_andMatrixOutputs_hi_3, decoded_andMatrixOutputs_lo_3)
node decoded_andMatrixOutputs_1_2 = andr(_decoded_andMatrixOutputs_T_3)
node decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_plaInput, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoded_plaInput, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoded_invInputs, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoded_invInputs, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(decoded_plaInput, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(decoded_plaInput, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(decoded_plaInput, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(decoded_invInputs, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(decoded_plaInput, 25, 25)
node decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(decoded_invInputs, 26, 26)
node decoded_andMatrixOutputs_andMatrixInput_12 = bits(decoded_invInputs, 27, 27)
node decoded_andMatrixOutputs_andMatrixInput_13 = bits(decoded_plaInput, 28, 28)
node decoded_andMatrixOutputs_andMatrixInput_14 = bits(decoded_invInputs, 29, 29)
node decoded_andMatrixOutputs_andMatrixInput_15 = bits(decoded_invInputs, 30, 30)
node decoded_andMatrixOutputs_andMatrixInput_16 = bits(decoded_invInputs, 31, 31)
node decoded_andMatrixOutputs_lo_lo_lo = cat(decoded_andMatrixOutputs_andMatrixInput_15, decoded_andMatrixOutputs_andMatrixInput_16)
node decoded_andMatrixOutputs_lo_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_13, decoded_andMatrixOutputs_andMatrixInput_14)
node decoded_andMatrixOutputs_lo_lo_4 = cat(decoded_andMatrixOutputs_lo_lo_hi_2, decoded_andMatrixOutputs_lo_lo_lo)
node decoded_andMatrixOutputs_lo_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_11_2, decoded_andMatrixOutputs_andMatrixInput_12)
node decoded_andMatrixOutputs_lo_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_andMatrixOutputs_andMatrixInput_10_2)
node decoded_andMatrixOutputs_lo_hi_4 = cat(decoded_andMatrixOutputs_lo_hi_hi_4, decoded_andMatrixOutputs_lo_hi_lo)
node decoded_andMatrixOutputs_lo_4 = cat(decoded_andMatrixOutputs_lo_hi_4, decoded_andMatrixOutputs_lo_lo_4)
node decoded_andMatrixOutputs_hi_lo_lo = cat(decoded_andMatrixOutputs_andMatrixInput_7_4, decoded_andMatrixOutputs_andMatrixInput_8_4)
node decoded_andMatrixOutputs_hi_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_5_4, decoded_andMatrixOutputs_andMatrixInput_6_4)
node decoded_andMatrixOutputs_hi_lo_4 = cat(decoded_andMatrixOutputs_hi_lo_hi_2, decoded_andMatrixOutputs_hi_lo_lo)
node decoded_andMatrixOutputs_hi_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_andMatrixOutputs_andMatrixInput_4_4)
node decoded_andMatrixOutputs_hi_hi_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_andMatrixOutputs_andMatrixInput_1_4)
node decoded_andMatrixOutputs_hi_hi_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2_4)
node decoded_andMatrixOutputs_hi_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_hi_4, decoded_andMatrixOutputs_hi_hi_lo)
node decoded_andMatrixOutputs_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_4, decoded_andMatrixOutputs_hi_lo_4)
node _decoded_andMatrixOutputs_T_4 = cat(decoded_andMatrixOutputs_hi_4, decoded_andMatrixOutputs_lo_4)
node decoded_andMatrixOutputs_0_2 = andr(_decoded_andMatrixOutputs_T_4)
node decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoded_plaInput, 22, 22)
node decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoded_invInputs, 23, 23)
node decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoded_invInputs, 24, 24)
node decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoded_invInputs, 25, 25)
node decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(decoded_invInputs, 26, 26)
node decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(decoded_invInputs, 27, 27)
node decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(decoded_plaInput, 28, 28)
node decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(decoded_plaInput, 29, 29)
node decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(decoded_invInputs, 30, 30)
node decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(decoded_invInputs, 31, 31)
node decoded_andMatrixOutputs_lo_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_8_5, decoded_andMatrixOutputs_andMatrixInput_9_5)
node decoded_andMatrixOutputs_lo_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_5_5, decoded_andMatrixOutputs_andMatrixInput_6_5)
node decoded_andMatrixOutputs_lo_hi_5 = cat(decoded_andMatrixOutputs_lo_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_7_5)
node decoded_andMatrixOutputs_lo_5 = cat(decoded_andMatrixOutputs_lo_hi_5, decoded_andMatrixOutputs_lo_lo_5)
node decoded_andMatrixOutputs_hi_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_andMatrixOutputs_andMatrixInput_4_5)
node decoded_andMatrixOutputs_hi_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_5)
node decoded_andMatrixOutputs_hi_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_2_5)
node decoded_andMatrixOutputs_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_5, decoded_andMatrixOutputs_hi_lo_5)
node _decoded_andMatrixOutputs_T_5 = cat(decoded_andMatrixOutputs_hi_5, decoded_andMatrixOutputs_lo_5)
node decoded_andMatrixOutputs_5_2 = andr(_decoded_andMatrixOutputs_T_5)
node decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoded_plaInput, 30, 30)
node decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoded_invInputs, 31, 31)
node _decoded_andMatrixOutputs_T_6 = cat(decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_andMatrixOutputs_andMatrixInput_1_6)
node decoded_andMatrixOutputs_2_2 = andr(_decoded_andMatrixOutputs_T_6)
node _decoded_orMatrixOutputs_T = orr(decoded_andMatrixOutputs_0_2)
node _decoded_orMatrixOutputs_T_1 = orr(decoded_andMatrixOutputs_1_2)
node _decoded_orMatrixOutputs_T_2 = orr(decoded_andMatrixOutputs_5_2)
node _decoded_orMatrixOutputs_T_3 = cat(decoded_andMatrixOutputs_3_2, decoded_andMatrixOutputs_2_2)
node _decoded_orMatrixOutputs_T_4 = orr(_decoded_orMatrixOutputs_T_3)
node _decoded_orMatrixOutputs_T_5 = orr(decoded_andMatrixOutputs_4_2)
node _decoded_orMatrixOutputs_T_6 = orr(decoded_andMatrixOutputs_6_2)
node decoded_orMatrixOutputs_lo_lo = cat(UInt<1>(0h0), UInt<1>(0h0))
node decoded_orMatrixOutputs_lo_hi = cat(_decoded_orMatrixOutputs_T, UInt<1>(0h0))
node decoded_orMatrixOutputs_lo = cat(decoded_orMatrixOutputs_lo_hi, decoded_orMatrixOutputs_lo_lo)
node decoded_orMatrixOutputs_hi_lo = cat(_decoded_orMatrixOutputs_T_2, _decoded_orMatrixOutputs_T_1)
node decoded_orMatrixOutputs_hi_hi_hi = cat(_decoded_orMatrixOutputs_T_6, _decoded_orMatrixOutputs_T_5)
node decoded_orMatrixOutputs_hi_hi = cat(decoded_orMatrixOutputs_hi_hi_hi, _decoded_orMatrixOutputs_T_4)
node decoded_orMatrixOutputs_hi = cat(decoded_orMatrixOutputs_hi_hi, decoded_orMatrixOutputs_hi_lo)
node decoded_orMatrixOutputs = cat(decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo)
node _decoded_invMatrixOutputs_T = bits(decoded_orMatrixOutputs, 0, 0)
node _decoded_invMatrixOutputs_T_1 = bits(decoded_orMatrixOutputs, 1, 1)
node _decoded_invMatrixOutputs_T_2 = bits(decoded_orMatrixOutputs, 2, 2)
node _decoded_invMatrixOutputs_T_3 = bits(decoded_orMatrixOutputs, 3, 3)
node _decoded_invMatrixOutputs_T_4 = bits(decoded_orMatrixOutputs, 4, 4)
node _decoded_invMatrixOutputs_T_5 = bits(decoded_orMatrixOutputs, 5, 5)
node _decoded_invMatrixOutputs_T_6 = bits(decoded_orMatrixOutputs, 6, 6)
node _decoded_invMatrixOutputs_T_7 = bits(decoded_orMatrixOutputs, 7, 7)
node _decoded_invMatrixOutputs_T_8 = bits(decoded_orMatrixOutputs, 8, 8)
node decoded_invMatrixOutputs_lo_lo = cat(_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T)
node decoded_invMatrixOutputs_lo_hi = cat(_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2)
node decoded_invMatrixOutputs_lo = cat(decoded_invMatrixOutputs_lo_hi, decoded_invMatrixOutputs_lo_lo)
node decoded_invMatrixOutputs_hi_lo = cat(_decoded_invMatrixOutputs_T_5, _decoded_invMatrixOutputs_T_4)
node decoded_invMatrixOutputs_hi_hi_hi = cat(_decoded_invMatrixOutputs_T_8, _decoded_invMatrixOutputs_T_7)
node decoded_invMatrixOutputs_hi_hi = cat(decoded_invMatrixOutputs_hi_hi_hi, _decoded_invMatrixOutputs_T_6)
node decoded_invMatrixOutputs_hi = cat(decoded_invMatrixOutputs_hi_hi, decoded_invMatrixOutputs_hi_lo)
node decoded_invMatrixOutputs = cat(decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo)
connect decoded, decoded_invMatrixOutputs
connect decoded_plaInput, insn
node _T_57 = bits(decoded, 8, 8)
node _T_58 = bits(decoded, 7, 7)
node _T_59 = bits(decoded, 6, 6)
node _T_60 = bits(decoded, 5, 5)
node _T_61 = bits(decoded, 4, 4)
node _T_62 = bits(decoded, 3, 3)
node _T_63 = bits(decoded, 2, 2)
node _T_64 = bits(decoded, 1, 1)
node _T_65 = bits(decoded, 0, 0)
node _T_66 = bits(_T_57, 0, 0)
node insn_call = and(system_insn, _T_66)
node _T_67 = bits(_T_58, 0, 0)
node insn_break = and(system_insn, _T_67)
node _T_68 = bits(_T_59, 0, 0)
node insn_ret = and(system_insn, _T_68)
node _T_69 = bits(_T_60, 0, 0)
node insn_cease = and(system_insn, _T_69)
node _T_70 = bits(_T_61, 0, 0)
node insn_wfi = and(system_insn, _T_70)
node _T_71 = bits(_T_62, 0, 0)
node _T_72 = and(system_insn, _T_71)
node _T_73 = bits(_T_63, 0, 0)
node _T_74 = and(system_insn, _T_73)
node _T_75 = bits(_T_64, 0, 0)
node _T_76 = and(system_insn, _T_75)
node _T_77 = bits(_T_65, 0, 0)
node _T_78 = and(system_insn, _T_77)
node addr = bits(io.decode[0].inst, 31, 20)
wire decoded_plaInput_1 : UInt<32>
node decoded_invInputs_1 = not(decoded_plaInput_1)
wire decoded_1 : UInt<9>
node decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(decoded_invInputs_1, 20, 20)
node decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(decoded_invInputs_1, 21, 21)
node decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoded_invInputs_1, 22, 22)
node decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoded_invInputs_1, 23, 23)
node decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(decoded_invInputs_1, 24, 24)
node decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(decoded_invInputs_1, 25, 25)
node decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(decoded_invInputs_1, 26, 26)
node decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(decoded_invInputs_1, 27, 27)
node decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(decoded_invInputs_1, 28, 28)
node decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(decoded_invInputs_1, 29, 29)
node decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(decoded_invInputs_1, 30, 30)
node decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(decoded_invInputs_1, 31, 31)
node decoded_andMatrixOutputs_lo_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_andMatrixOutputs_andMatrixInput_10_3)
node decoded_andMatrixOutputs_lo_lo_6 = cat(decoded_andMatrixOutputs_lo_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_11_3)
node decoded_andMatrixOutputs_lo_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_andMatrixOutputs_andMatrixInput_7_6)
node decoded_andMatrixOutputs_lo_hi_6 = cat(decoded_andMatrixOutputs_lo_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_8_6)
node decoded_andMatrixOutputs_lo_6 = cat(decoded_andMatrixOutputs_lo_hi_6, decoded_andMatrixOutputs_lo_lo_6)
node decoded_andMatrixOutputs_hi_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_andMatrixOutputs_andMatrixInput_4_6)
node decoded_andMatrixOutputs_hi_lo_6 = cat(decoded_andMatrixOutputs_hi_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_5_6)
node decoded_andMatrixOutputs_hi_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_andMatrixOutputs_andMatrixInput_1_7)
node decoded_andMatrixOutputs_hi_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_2_6)
node decoded_andMatrixOutputs_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_6, decoded_andMatrixOutputs_hi_lo_6)
node _decoded_andMatrixOutputs_T_7 = cat(decoded_andMatrixOutputs_hi_6, decoded_andMatrixOutputs_lo_6)
node decoded_andMatrixOutputs_6_2_1 = andr(_decoded_andMatrixOutputs_T_7)
node decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(decoded_plaInput_1, 20, 20)
node decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(decoded_invInputs_1, 21, 21)
node decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(decoded_invInputs_1, 22, 22)
node decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(decoded_invInputs_1, 23, 23)
node decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(decoded_invInputs_1, 24, 24)
node decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(decoded_invInputs_1, 25, 25)
node decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(decoded_invInputs_1, 26, 26)
node decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(decoded_invInputs_1, 27, 27)
node decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(decoded_invInputs_1, 28, 28)
node decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(decoded_invInputs_1, 29, 29)
node decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(decoded_invInputs_1, 30, 30)
node decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(decoded_invInputs_1, 31, 31)
node decoded_andMatrixOutputs_lo_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_andMatrixOutputs_andMatrixInput_10_4)
node decoded_andMatrixOutputs_lo_lo_7 = cat(decoded_andMatrixOutputs_lo_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_11_4)
node decoded_andMatrixOutputs_lo_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_6_7, decoded_andMatrixOutputs_andMatrixInput_7_7)
node decoded_andMatrixOutputs_lo_hi_7 = cat(decoded_andMatrixOutputs_lo_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_8_7)
node decoded_andMatrixOutputs_lo_7 = cat(decoded_andMatrixOutputs_lo_hi_7, decoded_andMatrixOutputs_lo_lo_7)
node decoded_andMatrixOutputs_hi_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_andMatrixOutputs_andMatrixInput_4_7)
node decoded_andMatrixOutputs_hi_lo_7 = cat(decoded_andMatrixOutputs_hi_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_5_7)
node decoded_andMatrixOutputs_hi_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_andMatrixOutputs_andMatrixInput_1_8)
node decoded_andMatrixOutputs_hi_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_2_7)
node decoded_andMatrixOutputs_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_7, decoded_andMatrixOutputs_hi_lo_7)
node _decoded_andMatrixOutputs_T_8 = cat(decoded_andMatrixOutputs_hi_7, decoded_andMatrixOutputs_lo_7)
node decoded_andMatrixOutputs_4_2_1 = andr(_decoded_andMatrixOutputs_T_8)
node decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(decoded_plaInput_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(decoded_invInputs_1, 22, 22)
node decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(decoded_invInputs_1, 23, 23)
node decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(decoded_invInputs_1, 24, 24)
node decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(decoded_invInputs_1, 25, 25)
node decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(decoded_invInputs_1, 26, 26)
node decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(decoded_invInputs_1, 27, 27)
node decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(decoded_plaInput_1, 28, 28)
node decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(decoded_invInputs_1, 30, 30)
node decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(decoded_invInputs_1, 31, 31)
node decoded_andMatrixOutputs_lo_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_8_8, decoded_andMatrixOutputs_andMatrixInput_9_8)
node decoded_andMatrixOutputs_lo_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_5_8, decoded_andMatrixOutputs_andMatrixInput_6_8)
node decoded_andMatrixOutputs_lo_hi_8 = cat(decoded_andMatrixOutputs_lo_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_7_8)
node decoded_andMatrixOutputs_lo_8 = cat(decoded_andMatrixOutputs_lo_hi_8, decoded_andMatrixOutputs_lo_lo_8)
node decoded_andMatrixOutputs_hi_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_andMatrixOutputs_andMatrixInput_4_8)
node decoded_andMatrixOutputs_hi_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_andMatrixOutputs_andMatrixInput_1_9)
node decoded_andMatrixOutputs_hi_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_2_8)
node decoded_andMatrixOutputs_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_8, decoded_andMatrixOutputs_hi_lo_8)
node _decoded_andMatrixOutputs_T_9 = cat(decoded_andMatrixOutputs_hi_8, decoded_andMatrixOutputs_lo_8)
node decoded_andMatrixOutputs_3_2_1 = andr(_decoded_andMatrixOutputs_T_9)
node decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(decoded_plaInput_1, 22, 22)
node decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(decoded_invInputs_1, 23, 23)
node decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(decoded_invInputs_1, 24, 24)
node decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(decoded_invInputs_1, 25, 25)
node decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(decoded_invInputs_1, 26, 26)
node decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(decoded_invInputs_1, 27, 27)
node decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(decoded_plaInput_1, 28, 28)
node decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(decoded_invInputs_1, 29, 29)
node decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(decoded_invInputs_1, 30, 30)
node decoded_andMatrixOutputs_andMatrixInput_9_9 = bits(decoded_invInputs_1, 31, 31)
node decoded_andMatrixOutputs_lo_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_8_9, decoded_andMatrixOutputs_andMatrixInput_9_9)
node decoded_andMatrixOutputs_lo_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_5_9, decoded_andMatrixOutputs_andMatrixInput_6_9)
node decoded_andMatrixOutputs_lo_hi_9 = cat(decoded_andMatrixOutputs_lo_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_7_9)
node decoded_andMatrixOutputs_lo_9 = cat(decoded_andMatrixOutputs_lo_hi_9, decoded_andMatrixOutputs_lo_lo_9)
node decoded_andMatrixOutputs_hi_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_andMatrixOutputs_andMatrixInput_4_9)
node decoded_andMatrixOutputs_hi_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_andMatrixOutputs_andMatrixInput_1_10)
node decoded_andMatrixOutputs_hi_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_2_9)
node decoded_andMatrixOutputs_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_9, decoded_andMatrixOutputs_hi_lo_9)
node _decoded_andMatrixOutputs_T_10 = cat(decoded_andMatrixOutputs_hi_9, decoded_andMatrixOutputs_lo_9)
node decoded_andMatrixOutputs_1_2_1 = andr(_decoded_andMatrixOutputs_T_10)
node decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(decoded_plaInput_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(decoded_plaInput_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(decoded_invInputs_1, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(decoded_invInputs_1, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(decoded_plaInput_1, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(decoded_plaInput_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(decoded_plaInput_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(decoded_invInputs_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_8_10 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_9_10 = bits(decoded_invInputs_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(decoded_plaInput_1, 25, 25)
node decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(decoded_invInputs_1, 26, 26)
node decoded_andMatrixOutputs_andMatrixInput_12_1 = bits(decoded_invInputs_1, 27, 27)
node decoded_andMatrixOutputs_andMatrixInput_13_1 = bits(decoded_plaInput_1, 28, 28)
node decoded_andMatrixOutputs_andMatrixInput_14_1 = bits(decoded_invInputs_1, 29, 29)
node decoded_andMatrixOutputs_andMatrixInput_15_1 = bits(decoded_invInputs_1, 30, 30)
node decoded_andMatrixOutputs_andMatrixInput_16_1 = bits(decoded_invInputs_1, 31, 31)
node decoded_andMatrixOutputs_lo_lo_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_15_1, decoded_andMatrixOutputs_andMatrixInput_16_1)
node decoded_andMatrixOutputs_lo_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_13_1, decoded_andMatrixOutputs_andMatrixInput_14_1)
node decoded_andMatrixOutputs_lo_lo_10 = cat(decoded_andMatrixOutputs_lo_lo_hi_5, decoded_andMatrixOutputs_lo_lo_lo_1)
node decoded_andMatrixOutputs_lo_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_11_5, decoded_andMatrixOutputs_andMatrixInput_12_1)
node decoded_andMatrixOutputs_lo_hi_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_andMatrixOutputs_andMatrixInput_10_5)
node decoded_andMatrixOutputs_lo_hi_10 = cat(decoded_andMatrixOutputs_lo_hi_hi_10, decoded_andMatrixOutputs_lo_hi_lo_1)
node decoded_andMatrixOutputs_lo_10 = cat(decoded_andMatrixOutputs_lo_hi_10, decoded_andMatrixOutputs_lo_lo_10)
node decoded_andMatrixOutputs_hi_lo_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_7_10, decoded_andMatrixOutputs_andMatrixInput_8_10)
node decoded_andMatrixOutputs_hi_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_5_10, decoded_andMatrixOutputs_andMatrixInput_6_10)
node decoded_andMatrixOutputs_hi_lo_10 = cat(decoded_andMatrixOutputs_hi_lo_hi_5, decoded_andMatrixOutputs_hi_lo_lo_1)
node decoded_andMatrixOutputs_hi_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_andMatrixOutputs_andMatrixInput_4_10)
node decoded_andMatrixOutputs_hi_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_andMatrixOutputs_andMatrixInput_1_11)
node decoded_andMatrixOutputs_hi_hi_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_10)
node decoded_andMatrixOutputs_hi_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_hi_10, decoded_andMatrixOutputs_hi_hi_lo_1)
node decoded_andMatrixOutputs_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_10, decoded_andMatrixOutputs_hi_lo_10)
node _decoded_andMatrixOutputs_T_11 = cat(decoded_andMatrixOutputs_hi_10, decoded_andMatrixOutputs_lo_10)
node decoded_andMatrixOutputs_0_2_1 = andr(_decoded_andMatrixOutputs_T_11)
node decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(decoded_plaInput_1, 22, 22)
node decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(decoded_invInputs_1, 23, 23)
node decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(decoded_invInputs_1, 24, 24)
node decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(decoded_invInputs_1, 25, 25)
node decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(decoded_invInputs_1, 26, 26)
node decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(decoded_invInputs_1, 27, 27)
node decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(decoded_plaInput_1, 28, 28)
node decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(decoded_plaInput_1, 29, 29)
node decoded_andMatrixOutputs_andMatrixInput_8_11 = bits(decoded_invInputs_1, 30, 30)
node decoded_andMatrixOutputs_andMatrixInput_9_11 = bits(decoded_invInputs_1, 31, 31)
node decoded_andMatrixOutputs_lo_lo_11 = cat(decoded_andMatrixOutputs_andMatrixInput_8_11, decoded_andMatrixOutputs_andMatrixInput_9_11)
node decoded_andMatrixOutputs_lo_hi_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_5_11, decoded_andMatrixOutputs_andMatrixInput_6_11)
node decoded_andMatrixOutputs_lo_hi_11 = cat(decoded_andMatrixOutputs_lo_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_7_11)
node decoded_andMatrixOutputs_lo_11 = cat(decoded_andMatrixOutputs_lo_hi_11, decoded_andMatrixOutputs_lo_lo_11)
node decoded_andMatrixOutputs_hi_lo_11 = cat(decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_andMatrixOutputs_andMatrixInput_4_11)
node decoded_andMatrixOutputs_hi_hi_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_andMatrixOutputs_andMatrixInput_1_12)
node decoded_andMatrixOutputs_hi_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_2_11)
node decoded_andMatrixOutputs_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_11, decoded_andMatrixOutputs_hi_lo_11)
node _decoded_andMatrixOutputs_T_12 = cat(decoded_andMatrixOutputs_hi_11, decoded_andMatrixOutputs_lo_11)
node decoded_andMatrixOutputs_5_2_1 = andr(_decoded_andMatrixOutputs_T_12)
node decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(decoded_plaInput_1, 30, 30)
node decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(decoded_invInputs_1, 31, 31)
node _decoded_andMatrixOutputs_T_13 = cat(decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_andMatrixOutputs_andMatrixInput_1_13)
node decoded_andMatrixOutputs_2_2_1 = andr(_decoded_andMatrixOutputs_T_13)
node _decoded_orMatrixOutputs_T_7 = orr(decoded_andMatrixOutputs_0_2_1)
node _decoded_orMatrixOutputs_T_8 = orr(decoded_andMatrixOutputs_1_2_1)
node _decoded_orMatrixOutputs_T_9 = orr(decoded_andMatrixOutputs_5_2_1)
node _decoded_orMatrixOutputs_T_10 = cat(decoded_andMatrixOutputs_3_2_1, decoded_andMatrixOutputs_2_2_1)
node _decoded_orMatrixOutputs_T_11 = orr(_decoded_orMatrixOutputs_T_10)
node _decoded_orMatrixOutputs_T_12 = orr(decoded_andMatrixOutputs_4_2_1)
node _decoded_orMatrixOutputs_T_13 = orr(decoded_andMatrixOutputs_6_2_1)
node decoded_orMatrixOutputs_lo_lo_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node decoded_orMatrixOutputs_lo_hi_1 = cat(_decoded_orMatrixOutputs_T_7, UInt<1>(0h0))
node decoded_orMatrixOutputs_lo_1 = cat(decoded_orMatrixOutputs_lo_hi_1, decoded_orMatrixOutputs_lo_lo_1)
node decoded_orMatrixOutputs_hi_lo_1 = cat(_decoded_orMatrixOutputs_T_9, _decoded_orMatrixOutputs_T_8)
node decoded_orMatrixOutputs_hi_hi_hi_1 = cat(_decoded_orMatrixOutputs_T_13, _decoded_orMatrixOutputs_T_12)
node decoded_orMatrixOutputs_hi_hi_1 = cat(decoded_orMatrixOutputs_hi_hi_hi_1, _decoded_orMatrixOutputs_T_11)
node decoded_orMatrixOutputs_hi_1 = cat(decoded_orMatrixOutputs_hi_hi_1, decoded_orMatrixOutputs_hi_lo_1)
node decoded_orMatrixOutputs_1 = cat(decoded_orMatrixOutputs_hi_1, decoded_orMatrixOutputs_lo_1)
node _decoded_invMatrixOutputs_T_9 = bits(decoded_orMatrixOutputs_1, 0, 0)
node _decoded_invMatrixOutputs_T_10 = bits(decoded_orMatrixOutputs_1, 1, 1)
node _decoded_invMatrixOutputs_T_11 = bits(decoded_orMatrixOutputs_1, 2, 2)
node _decoded_invMatrixOutputs_T_12 = bits(decoded_orMatrixOutputs_1, 3, 3)
node _decoded_invMatrixOutputs_T_13 = bits(decoded_orMatrixOutputs_1, 4, 4)
node _decoded_invMatrixOutputs_T_14 = bits(decoded_orMatrixOutputs_1, 5, 5)
node _decoded_invMatrixOutputs_T_15 = bits(decoded_orMatrixOutputs_1, 6, 6)
node _decoded_invMatrixOutputs_T_16 = bits(decoded_orMatrixOutputs_1, 7, 7)
node _decoded_invMatrixOutputs_T_17 = bits(decoded_orMatrixOutputs_1, 8, 8)
node decoded_invMatrixOutputs_lo_lo_1 = cat(_decoded_invMatrixOutputs_T_10, _decoded_invMatrixOutputs_T_9)
node decoded_invMatrixOutputs_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_12, _decoded_invMatrixOutputs_T_11)
node decoded_invMatrixOutputs_lo_1 = cat(decoded_invMatrixOutputs_lo_hi_1, decoded_invMatrixOutputs_lo_lo_1)
node decoded_invMatrixOutputs_hi_lo_1 = cat(_decoded_invMatrixOutputs_T_14, _decoded_invMatrixOutputs_T_13)
node decoded_invMatrixOutputs_hi_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_17, _decoded_invMatrixOutputs_T_16)
node decoded_invMatrixOutputs_hi_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_hi_1, _decoded_invMatrixOutputs_T_15)
node decoded_invMatrixOutputs_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_1, decoded_invMatrixOutputs_hi_lo_1)
node decoded_invMatrixOutputs_1 = cat(decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1)
connect decoded_1, decoded_invMatrixOutputs_1
connect decoded_plaInput_1, io.decode[0].inst
node _T_79 = bits(decoded_1, 8, 8)
node _T_80 = bits(decoded_1, 7, 7)
node _T_81 = bits(decoded_1, 6, 6)
node _T_82 = bits(decoded_1, 5, 5)
node _T_83 = bits(decoded_1, 4, 4)
node _T_84 = bits(decoded_1, 3, 3)
node _T_85 = bits(decoded_1, 2, 2)
node _T_86 = bits(decoded_1, 1, 1)
node _T_87 = bits(decoded_1, 0, 0)
node _T_88 = bits(_T_79, 0, 0)
node is_break = bits(_T_80, 0, 0)
node is_ret = bits(_T_81, 0, 0)
node _T_89 = bits(_T_82, 0, 0)
node is_wfi = bits(_T_83, 0, 0)
node is_sfence = bits(_T_84, 0, 0)
node is_hfence_vvma = bits(_T_85, 0, 0)
node is_hfence_gvma = bits(_T_86, 0, 0)
node is_hlsv = bits(_T_87, 0, 0)
node _is_counter_T = geq(addr, UInt<12>(0hc00))
node _is_counter_T_1 = lt(addr, UInt<12>(0hc20))
node _is_counter_T_2 = and(_is_counter_T, _is_counter_T_1)
node _is_counter_T_3 = geq(addr, UInt<12>(0hc80))
node _is_counter_T_4 = lt(addr, UInt<12>(0hca0))
node _is_counter_T_5 = and(_is_counter_T_3, _is_counter_T_4)
node is_counter = or(_is_counter_T_2, _is_counter_T_5)
node _allow_wfi_T = gt(reg_mstatus.prv, UInt<1>(0h1))
node _allow_wfi_T_1 = or(UInt<1>(0h0), _allow_wfi_T)
node _allow_wfi_T_2 = eq(reg_mstatus.tw, UInt<1>(0h0))
node _allow_wfi_T_3 = eq(reg_mstatus.v, UInt<1>(0h0))
node _allow_wfi_T_4 = eq(reg_hstatus.vtw, UInt<1>(0h0))
node _allow_wfi_T_5 = or(_allow_wfi_T_3, _allow_wfi_T_4)
node _allow_wfi_T_6 = and(_allow_wfi_T_2, _allow_wfi_T_5)
node allow_wfi = or(_allow_wfi_T_1, _allow_wfi_T_6)
node _allow_sfence_vma_T = gt(reg_mstatus.prv, UInt<1>(0h1))
node _allow_sfence_vma_T_1 = or(UInt<1>(0h0), _allow_sfence_vma_T)
node _allow_sfence_vma_T_2 = mux(reg_mstatus.v, reg_hstatus.vtvm, reg_mstatus.tvm)
node _allow_sfence_vma_T_3 = eq(_allow_sfence_vma_T_2, UInt<1>(0h0))
node allow_sfence_vma = or(_allow_sfence_vma_T_1, _allow_sfence_vma_T_3)
node _allow_hfence_vvma_T = eq(reg_mstatus.v, UInt<1>(0h0))
node _allow_hfence_vvma_T_1 = geq(reg_mstatus.prv, UInt<1>(0h1))
node _allow_hfence_vvma_T_2 = and(_allow_hfence_vvma_T, _allow_hfence_vvma_T_1)
node allow_hfence_vvma = or(UInt<1>(0h1), _allow_hfence_vvma_T_2)
node _allow_hlsv_T = eq(reg_mstatus.v, UInt<1>(0h0))
node _allow_hlsv_T_1 = geq(reg_mstatus.prv, UInt<1>(0h1))
node _allow_hlsv_T_2 = or(_allow_hlsv_T_1, reg_hstatus.hu)
node _allow_hlsv_T_3 = and(_allow_hlsv_T, _allow_hlsv_T_2)
node allow_hlsv = or(UInt<1>(0h1), _allow_hlsv_T_3)
node _allow_sret_T = gt(reg_mstatus.prv, UInt<1>(0h1))
node _allow_sret_T_1 = or(UInt<1>(0h0), _allow_sret_T)
node _allow_sret_T_2 = mux(reg_mstatus.v, reg_hstatus.vtsr, reg_mstatus.tsr)
node _allow_sret_T_3 = eq(_allow_sret_T_2, UInt<1>(0h0))
node allow_sret = or(_allow_sret_T_1, _allow_sret_T_3)
node counter_addr = bits(addr, 4, 0)
node _allow_counter_T = gt(reg_mstatus.prv, UInt<1>(0h1))
node _allow_counter_T_1 = dshr(read_mcounteren, counter_addr)
node _allow_counter_T_2 = bits(_allow_counter_T_1, 0, 0)
node _allow_counter_T_3 = or(_allow_counter_T, _allow_counter_T_2)
node _allow_counter_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _allow_counter_T_5 = geq(reg_mstatus.prv, UInt<1>(0h1))
node _allow_counter_T_6 = or(_allow_counter_T_4, _allow_counter_T_5)
node _allow_counter_T_7 = dshr(read_scounteren, counter_addr)
node _allow_counter_T_8 = bits(_allow_counter_T_7, 0, 0)
node _allow_counter_T_9 = or(_allow_counter_T_6, _allow_counter_T_8)
node _allow_counter_T_10 = and(_allow_counter_T_3, _allow_counter_T_9)
node _allow_counter_T_11 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _allow_counter_T_12 = eq(reg_mstatus.v, UInt<1>(0h0))
node _allow_counter_T_13 = or(_allow_counter_T_11, _allow_counter_T_12)
node _allow_counter_T_14 = dshr(read_hcounteren, counter_addr)
node _allow_counter_T_15 = bits(_allow_counter_T_14, 0, 0)
node _allow_counter_T_16 = or(_allow_counter_T_13, _allow_counter_T_15)
node allow_counter = and(_allow_counter_T_10, _allow_counter_T_16)
node _io_decode_0_fp_illegal_T = eq(io.status.fs, UInt<1>(0h0))
node _io_decode_0_fp_illegal_T_1 = eq(reg_vsstatus.fs, UInt<1>(0h0))
node _io_decode_0_fp_illegal_T_2 = and(reg_mstatus.v, _io_decode_0_fp_illegal_T_1)
node _io_decode_0_fp_illegal_T_3 = or(_io_decode_0_fp_illegal_T, _io_decode_0_fp_illegal_T_2)
node _io_decode_0_fp_illegal_T_4 = bits(reg_misa, 5, 5)
node _io_decode_0_fp_illegal_T_5 = eq(_io_decode_0_fp_illegal_T_4, UInt<1>(0h0))
node _io_decode_0_fp_illegal_T_6 = or(_io_decode_0_fp_illegal_T_3, _io_decode_0_fp_illegal_T_5)
connect io.decode[0].fp_illegal, _io_decode_0_fp_illegal_T_6
node _io_decode_0_vector_illegal_T = eq(io.status.vs, UInt<1>(0h0))
node _io_decode_0_vector_illegal_T_1 = eq(reg_vsstatus.vs, UInt<1>(0h0))
node _io_decode_0_vector_illegal_T_2 = and(reg_mstatus.v, _io_decode_0_vector_illegal_T_1)
node _io_decode_0_vector_illegal_T_3 = or(_io_decode_0_vector_illegal_T, _io_decode_0_vector_illegal_T_2)
node _io_decode_0_vector_illegal_T_4 = bits(reg_misa, 21, 21)
node _io_decode_0_vector_illegal_T_5 = eq(_io_decode_0_vector_illegal_T_4, UInt<1>(0h0))
node _io_decode_0_vector_illegal_T_6 = or(_io_decode_0_vector_illegal_T_3, _io_decode_0_vector_illegal_T_5)
connect io.decode[0].vector_illegal, _io_decode_0_vector_illegal_T_6
wire io_decode_0_fp_csr_plaInput : UInt<12>
node io_decode_0_fp_csr_invInputs = not(io_decode_0_fp_csr_plaInput)
wire io_decode_0_fp_csr_plaOutput : UInt<1>
node io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_0 = bits(io_decode_0_fp_csr_invInputs, 8, 8)
node io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_1 = bits(io_decode_0_fp_csr_invInputs, 9, 9)
node io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_2 = bits(io_decode_0_fp_csr_invInputs, 10, 10)
node io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_3 = bits(io_decode_0_fp_csr_invInputs, 11, 11)
node io_decode_0_fp_csr_andMatrixOutputs_lo = cat(io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_2, io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_3)
node io_decode_0_fp_csr_andMatrixOutputs_hi = cat(io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_0, io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_1)
node _io_decode_0_fp_csr_andMatrixOutputs_T = cat(io_decode_0_fp_csr_andMatrixOutputs_hi, io_decode_0_fp_csr_andMatrixOutputs_lo)
node io_decode_0_fp_csr_andMatrixOutputs_0_2 = andr(_io_decode_0_fp_csr_andMatrixOutputs_T)
node io_decode_0_fp_csr_orMatrixOutputs = orr(io_decode_0_fp_csr_andMatrixOutputs_0_2)
node io_decode_0_fp_csr_invMatrixOutputs = bits(io_decode_0_fp_csr_orMatrixOutputs, 0, 0)
connect io_decode_0_fp_csr_plaOutput, io_decode_0_fp_csr_invMatrixOutputs
connect io_decode_0_fp_csr_plaInput, addr
node _io_decode_0_fp_csr_T = bits(io_decode_0_fp_csr_plaOutput, 0, 0)
connect io.decode[0].fp_csr, _io_decode_0_fp_csr_T
wire io_decode_0_vector_csr_plaInput : UInt<12>
node io_decode_0_vector_csr_invInputs = not(io_decode_0_vector_csr_plaInput)
wire io_decode_0_vector_csr_plaOutput : UInt<1>
connect io_decode_0_vector_csr_plaOutput, UInt<1>(0h0)
connect io_decode_0_vector_csr_plaInput, addr
node _io_decode_0_vector_csr_T = bits(io_decode_0_vector_csr_plaOutput, 0, 0)
connect io.decode[0].vector_csr, _io_decode_0_vector_csr_T
node _io_decode_0_rocc_illegal_T = eq(io.status.xs, UInt<1>(0h0))
node _io_decode_0_rocc_illegal_T_1 = eq(reg_vsstatus.xs, UInt<1>(0h0))
node _io_decode_0_rocc_illegal_T_2 = and(reg_mstatus.v, _io_decode_0_rocc_illegal_T_1)
node _io_decode_0_rocc_illegal_T_3 = or(_io_decode_0_rocc_illegal_T, _io_decode_0_rocc_illegal_T_2)
node _io_decode_0_rocc_illegal_T_4 = bits(reg_misa, 23, 23)
node _io_decode_0_rocc_illegal_T_5 = eq(_io_decode_0_rocc_illegal_T_4, UInt<1>(0h0))
node _io_decode_0_rocc_illegal_T_6 = or(_io_decode_0_rocc_illegal_T_3, _io_decode_0_rocc_illegal_T_5)
connect io.decode[0].rocc_illegal, _io_decode_0_rocc_illegal_T_6
node _csr_addr_legal_T = bits(addr, 9, 8)
node _csr_addr_legal_T_1 = geq(reg_mstatus.prv, _csr_addr_legal_T)
node _csr_addr_legal_T_2 = eq(reg_mstatus.v, UInt<1>(0h0))
node _csr_addr_legal_T_3 = and(UInt<1>(0h0), _csr_addr_legal_T_2)
node _csr_addr_legal_T_4 = eq(reg_mstatus.prv, UInt<1>(0h1))
node _csr_addr_legal_T_5 = and(_csr_addr_legal_T_3, _csr_addr_legal_T_4)
node _csr_addr_legal_T_6 = bits(addr, 9, 8)
node _csr_addr_legal_T_7 = eq(_csr_addr_legal_T_6, UInt<2>(0h2))
node _csr_addr_legal_T_8 = and(_csr_addr_legal_T_5, _csr_addr_legal_T_7)
node csr_addr_legal = or(_csr_addr_legal_T_1, _csr_addr_legal_T_8)
node _csr_exists_T = eq(addr, UInt<11>(0h7a0))
node _csr_exists_T_1 = eq(addr, UInt<11>(0h7a1))
node _csr_exists_T_2 = eq(addr, UInt<11>(0h7a2))
node _csr_exists_T_3 = eq(addr, UInt<11>(0h7a3))
node _csr_exists_T_4 = eq(addr, UInt<10>(0h301))
node _csr_exists_T_5 = eq(addr, UInt<10>(0h300))
node _csr_exists_T_6 = eq(addr, UInt<10>(0h305))
node _csr_exists_T_7 = eq(addr, UInt<10>(0h344))
node _csr_exists_T_8 = eq(addr, UInt<10>(0h304))
node _csr_exists_T_9 = eq(addr, UInt<10>(0h340))
node _csr_exists_T_10 = eq(addr, UInt<10>(0h341))
node _csr_exists_T_11 = eq(addr, UInt<10>(0h343))
node _csr_exists_T_12 = eq(addr, UInt<10>(0h342))
node _csr_exists_T_13 = eq(addr, UInt<12>(0hf14))
node _csr_exists_T_14 = eq(addr, UInt<11>(0h7b0))
node _csr_exists_T_15 = eq(addr, UInt<11>(0h7b1))
node _csr_exists_T_16 = eq(addr, UInt<11>(0h7b2))
node _csr_exists_T_17 = eq(addr, UInt<1>(0h1))
node _csr_exists_T_18 = eq(addr, UInt<2>(0h2))
node _csr_exists_T_19 = eq(addr, UInt<2>(0h3))
node _csr_exists_T_20 = eq(addr, UInt<10>(0h320))
node _csr_exists_T_21 = eq(addr, UInt<12>(0hb00))
node _csr_exists_T_22 = eq(addr, UInt<12>(0hb02))
node _csr_exists_T_23 = eq(addr, UInt<10>(0h323))
node _csr_exists_T_24 = eq(addr, UInt<12>(0hb03))
node _csr_exists_T_25 = eq(addr, UInt<12>(0hc03))
node _csr_exists_T_26 = eq(addr, UInt<10>(0h324))
node _csr_exists_T_27 = eq(addr, UInt<12>(0hb04))
node _csr_exists_T_28 = eq(addr, UInt<12>(0hc04))
node _csr_exists_T_29 = eq(addr, UInt<10>(0h325))
node _csr_exists_T_30 = eq(addr, UInt<12>(0hb05))
node _csr_exists_T_31 = eq(addr, UInt<12>(0hc05))
node _csr_exists_T_32 = eq(addr, UInt<10>(0h326))
node _csr_exists_T_33 = eq(addr, UInt<12>(0hb06))
node _csr_exists_T_34 = eq(addr, UInt<12>(0hc06))
node _csr_exists_T_35 = eq(addr, UInt<10>(0h327))
node _csr_exists_T_36 = eq(addr, UInt<12>(0hb07))
node _csr_exists_T_37 = eq(addr, UInt<12>(0hc07))
node _csr_exists_T_38 = eq(addr, UInt<10>(0h328))
node _csr_exists_T_39 = eq(addr, UInt<12>(0hb08))
node _csr_exists_T_40 = eq(addr, UInt<12>(0hc08))
node _csr_exists_T_41 = eq(addr, UInt<10>(0h329))
node _csr_exists_T_42 = eq(addr, UInt<12>(0hb09))
node _csr_exists_T_43 = eq(addr, UInt<12>(0hc09))
node _csr_exists_T_44 = eq(addr, UInt<10>(0h32a))
node _csr_exists_T_45 = eq(addr, UInt<12>(0hb0a))
node _csr_exists_T_46 = eq(addr, UInt<12>(0hc0a))
node _csr_exists_T_47 = eq(addr, UInt<10>(0h32b))
node _csr_exists_T_48 = eq(addr, UInt<12>(0hb0b))
node _csr_exists_T_49 = eq(addr, UInt<12>(0hc0b))
node _csr_exists_T_50 = eq(addr, UInt<10>(0h32c))
node _csr_exists_T_51 = eq(addr, UInt<12>(0hb0c))
node _csr_exists_T_52 = eq(addr, UInt<12>(0hc0c))
node _csr_exists_T_53 = eq(addr, UInt<10>(0h32d))
node _csr_exists_T_54 = eq(addr, UInt<12>(0hb0d))
node _csr_exists_T_55 = eq(addr, UInt<12>(0hc0d))
node _csr_exists_T_56 = eq(addr, UInt<10>(0h32e))
node _csr_exists_T_57 = eq(addr, UInt<12>(0hb0e))
node _csr_exists_T_58 = eq(addr, UInt<12>(0hc0e))
node _csr_exists_T_59 = eq(addr, UInt<10>(0h32f))
node _csr_exists_T_60 = eq(addr, UInt<12>(0hb0f))
node _csr_exists_T_61 = eq(addr, UInt<12>(0hc0f))
node _csr_exists_T_62 = eq(addr, UInt<10>(0h330))
node _csr_exists_T_63 = eq(addr, UInt<12>(0hb10))
node _csr_exists_T_64 = eq(addr, UInt<12>(0hc10))
node _csr_exists_T_65 = eq(addr, UInt<10>(0h331))
node _csr_exists_T_66 = eq(addr, UInt<12>(0hb11))
node _csr_exists_T_67 = eq(addr, UInt<12>(0hc11))
node _csr_exists_T_68 = eq(addr, UInt<10>(0h332))
node _csr_exists_T_69 = eq(addr, UInt<12>(0hb12))
node _csr_exists_T_70 = eq(addr, UInt<12>(0hc12))
node _csr_exists_T_71 = eq(addr, UInt<10>(0h333))
node _csr_exists_T_72 = eq(addr, UInt<12>(0hb13))
node _csr_exists_T_73 = eq(addr, UInt<12>(0hc13))
node _csr_exists_T_74 = eq(addr, UInt<10>(0h334))
node _csr_exists_T_75 = eq(addr, UInt<12>(0hb14))
node _csr_exists_T_76 = eq(addr, UInt<12>(0hc14))
node _csr_exists_T_77 = eq(addr, UInt<10>(0h335))
node _csr_exists_T_78 = eq(addr, UInt<12>(0hb15))
node _csr_exists_T_79 = eq(addr, UInt<12>(0hc15))
node _csr_exists_T_80 = eq(addr, UInt<10>(0h336))
node _csr_exists_T_81 = eq(addr, UInt<12>(0hb16))
node _csr_exists_T_82 = eq(addr, UInt<12>(0hc16))
node _csr_exists_T_83 = eq(addr, UInt<10>(0h337))
node _csr_exists_T_84 = eq(addr, UInt<12>(0hb17))
node _csr_exists_T_85 = eq(addr, UInt<12>(0hc17))
node _csr_exists_T_86 = eq(addr, UInt<10>(0h338))
node _csr_exists_T_87 = eq(addr, UInt<12>(0hb18))
node _csr_exists_T_88 = eq(addr, UInt<12>(0hc18))
node _csr_exists_T_89 = eq(addr, UInt<10>(0h339))
node _csr_exists_T_90 = eq(addr, UInt<12>(0hb19))
node _csr_exists_T_91 = eq(addr, UInt<12>(0hc19))
node _csr_exists_T_92 = eq(addr, UInt<10>(0h33a))
node _csr_exists_T_93 = eq(addr, UInt<12>(0hb1a))
node _csr_exists_T_94 = eq(addr, UInt<12>(0hc1a))
node _csr_exists_T_95 = eq(addr, UInt<10>(0h33b))
node _csr_exists_T_96 = eq(addr, UInt<12>(0hb1b))
node _csr_exists_T_97 = eq(addr, UInt<12>(0hc1b))
node _csr_exists_T_98 = eq(addr, UInt<10>(0h33c))
node _csr_exists_T_99 = eq(addr, UInt<12>(0hb1c))
node _csr_exists_T_100 = eq(addr, UInt<12>(0hc1c))
node _csr_exists_T_101 = eq(addr, UInt<10>(0h33d))
node _csr_exists_T_102 = eq(addr, UInt<12>(0hb1d))
node _csr_exists_T_103 = eq(addr, UInt<12>(0hc1d))
node _csr_exists_T_104 = eq(addr, UInt<10>(0h33e))
node _csr_exists_T_105 = eq(addr, UInt<12>(0hb1e))
node _csr_exists_T_106 = eq(addr, UInt<12>(0hc1e))
node _csr_exists_T_107 = eq(addr, UInt<10>(0h33f))
node _csr_exists_T_108 = eq(addr, UInt<12>(0hb1f))
node _csr_exists_T_109 = eq(addr, UInt<12>(0hc1f))
node _csr_exists_T_110 = eq(addr, UInt<10>(0h306))
node _csr_exists_T_111 = eq(addr, UInt<12>(0hc00))
node _csr_exists_T_112 = eq(addr, UInt<12>(0hc02))
node _csr_exists_T_113 = eq(addr, UInt<10>(0h30a))
node _csr_exists_T_114 = eq(addr, UInt<9>(0h100))
node _csr_exists_T_115 = eq(addr, UInt<9>(0h144))
node _csr_exists_T_116 = eq(addr, UInt<9>(0h104))
node _csr_exists_T_117 = eq(addr, UInt<9>(0h140))
node _csr_exists_T_118 = eq(addr, UInt<9>(0h142))
node _csr_exists_T_119 = eq(addr, UInt<9>(0h143))
node _csr_exists_T_120 = eq(addr, UInt<9>(0h180))
node _csr_exists_T_121 = eq(addr, UInt<9>(0h141))
node _csr_exists_T_122 = eq(addr, UInt<9>(0h105))
node _csr_exists_T_123 = eq(addr, UInt<9>(0h106))
node _csr_exists_T_124 = eq(addr, UInt<10>(0h303))
node _csr_exists_T_125 = eq(addr, UInt<10>(0h302))
node _csr_exists_T_126 = eq(addr, UInt<9>(0h10a))
node _csr_exists_T_127 = eq(addr, UInt<10>(0h3a0))
node _csr_exists_T_128 = eq(addr, UInt<10>(0h3a2))
node _csr_exists_T_129 = eq(addr, UInt<10>(0h3b0))
node _csr_exists_T_130 = eq(addr, UInt<10>(0h3b1))
node _csr_exists_T_131 = eq(addr, UInt<10>(0h3b2))
node _csr_exists_T_132 = eq(addr, UInt<10>(0h3b3))
node _csr_exists_T_133 = eq(addr, UInt<10>(0h3b4))
node _csr_exists_T_134 = eq(addr, UInt<10>(0h3b5))
node _csr_exists_T_135 = eq(addr, UInt<10>(0h3b6))
node _csr_exists_T_136 = eq(addr, UInt<10>(0h3b7))
node _csr_exists_T_137 = eq(addr, UInt<10>(0h3b8))
node _csr_exists_T_138 = eq(addr, UInt<10>(0h3b9))
node _csr_exists_T_139 = eq(addr, UInt<10>(0h3ba))
node _csr_exists_T_140 = eq(addr, UInt<10>(0h3bb))
node _csr_exists_T_141 = eq(addr, UInt<10>(0h3bc))
node _csr_exists_T_142 = eq(addr, UInt<10>(0h3bd))
node _csr_exists_T_143 = eq(addr, UInt<10>(0h3be))
node _csr_exists_T_144 = eq(addr, UInt<10>(0h3bf))
node _csr_exists_T_145 = eq(addr, UInt<12>(0h800))
node _csr_exists_T_146 = eq(addr, UInt<12>(0h808))
node _csr_exists_T_147 = eq(addr, UInt<11>(0h7c1))
node _csr_exists_T_148 = eq(addr, UInt<12>(0hf12))
node _csr_exists_T_149 = eq(addr, UInt<12>(0hf13))
node _csr_exists_T_150 = eq(addr, UInt<12>(0hf11))
node _csr_exists_T_151 = eq(addr, UInt<12>(0hf15))
node _csr_exists_T_152 = or(_csr_exists_T, _csr_exists_T_1)
node _csr_exists_T_153 = or(_csr_exists_T_152, _csr_exists_T_2)
node _csr_exists_T_154 = or(_csr_exists_T_153, _csr_exists_T_3)
node _csr_exists_T_155 = or(_csr_exists_T_154, _csr_exists_T_4)
node _csr_exists_T_156 = or(_csr_exists_T_155, _csr_exists_T_5)
node _csr_exists_T_157 = or(_csr_exists_T_156, _csr_exists_T_6)
node _csr_exists_T_158 = or(_csr_exists_T_157, _csr_exists_T_7)
node _csr_exists_T_159 = or(_csr_exists_T_158, _csr_exists_T_8)
node _csr_exists_T_160 = or(_csr_exists_T_159, _csr_exists_T_9)
node _csr_exists_T_161 = or(_csr_exists_T_160, _csr_exists_T_10)
node _csr_exists_T_162 = or(_csr_exists_T_161, _csr_exists_T_11)
node _csr_exists_T_163 = or(_csr_exists_T_162, _csr_exists_T_12)
node _csr_exists_T_164 = or(_csr_exists_T_163, _csr_exists_T_13)
node _csr_exists_T_165 = or(_csr_exists_T_164, _csr_exists_T_14)
node _csr_exists_T_166 = or(_csr_exists_T_165, _csr_exists_T_15)
node _csr_exists_T_167 = or(_csr_exists_T_166, _csr_exists_T_16)
node _csr_exists_T_168 = or(_csr_exists_T_167, _csr_exists_T_17)
node _csr_exists_T_169 = or(_csr_exists_T_168, _csr_exists_T_18)
node _csr_exists_T_170 = or(_csr_exists_T_169, _csr_exists_T_19)
node _csr_exists_T_171 = or(_csr_exists_T_170, _csr_exists_T_20)
node _csr_exists_T_172 = or(_csr_exists_T_171, _csr_exists_T_21)
node _csr_exists_T_173 = or(_csr_exists_T_172, _csr_exists_T_22)
node _csr_exists_T_174 = or(_csr_exists_T_173, _csr_exists_T_23)
node _csr_exists_T_175 = or(_csr_exists_T_174, _csr_exists_T_24)
node _csr_exists_T_176 = or(_csr_exists_T_175, _csr_exists_T_25)
node _csr_exists_T_177 = or(_csr_exists_T_176, _csr_exists_T_26)
node _csr_exists_T_178 = or(_csr_exists_T_177, _csr_exists_T_27)
node _csr_exists_T_179 = or(_csr_exists_T_178, _csr_exists_T_28)
node _csr_exists_T_180 = or(_csr_exists_T_179, _csr_exists_T_29)
node _csr_exists_T_181 = or(_csr_exists_T_180, _csr_exists_T_30)
node _csr_exists_T_182 = or(_csr_exists_T_181, _csr_exists_T_31)
node _csr_exists_T_183 = or(_csr_exists_T_182, _csr_exists_T_32)
node _csr_exists_T_184 = or(_csr_exists_T_183, _csr_exists_T_33)
node _csr_exists_T_185 = or(_csr_exists_T_184, _csr_exists_T_34)
node _csr_exists_T_186 = or(_csr_exists_T_185, _csr_exists_T_35)
node _csr_exists_T_187 = or(_csr_exists_T_186, _csr_exists_T_36)
node _csr_exists_T_188 = or(_csr_exists_T_187, _csr_exists_T_37)
node _csr_exists_T_189 = or(_csr_exists_T_188, _csr_exists_T_38)
node _csr_exists_T_190 = or(_csr_exists_T_189, _csr_exists_T_39)
node _csr_exists_T_191 = or(_csr_exists_T_190, _csr_exists_T_40)
node _csr_exists_T_192 = or(_csr_exists_T_191, _csr_exists_T_41)
node _csr_exists_T_193 = or(_csr_exists_T_192, _csr_exists_T_42)
node _csr_exists_T_194 = or(_csr_exists_T_193, _csr_exists_T_43)
node _csr_exists_T_195 = or(_csr_exists_T_194, _csr_exists_T_44)
node _csr_exists_T_196 = or(_csr_exists_T_195, _csr_exists_T_45)
node _csr_exists_T_197 = or(_csr_exists_T_196, _csr_exists_T_46)
node _csr_exists_T_198 = or(_csr_exists_T_197, _csr_exists_T_47)
node _csr_exists_T_199 = or(_csr_exists_T_198, _csr_exists_T_48)
node _csr_exists_T_200 = or(_csr_exists_T_199, _csr_exists_T_49)
node _csr_exists_T_201 = or(_csr_exists_T_200, _csr_exists_T_50)
node _csr_exists_T_202 = or(_csr_exists_T_201, _csr_exists_T_51)
node _csr_exists_T_203 = or(_csr_exists_T_202, _csr_exists_T_52)
node _csr_exists_T_204 = or(_csr_exists_T_203, _csr_exists_T_53)
node _csr_exists_T_205 = or(_csr_exists_T_204, _csr_exists_T_54)
node _csr_exists_T_206 = or(_csr_exists_T_205, _csr_exists_T_55)
node _csr_exists_T_207 = or(_csr_exists_T_206, _csr_exists_T_56)
node _csr_exists_T_208 = or(_csr_exists_T_207, _csr_exists_T_57)
node _csr_exists_T_209 = or(_csr_exists_T_208, _csr_exists_T_58)
node _csr_exists_T_210 = or(_csr_exists_T_209, _csr_exists_T_59)
node _csr_exists_T_211 = or(_csr_exists_T_210, _csr_exists_T_60)
node _csr_exists_T_212 = or(_csr_exists_T_211, _csr_exists_T_61)
node _csr_exists_T_213 = or(_csr_exists_T_212, _csr_exists_T_62)
node _csr_exists_T_214 = or(_csr_exists_T_213, _csr_exists_T_63)
node _csr_exists_T_215 = or(_csr_exists_T_214, _csr_exists_T_64)
node _csr_exists_T_216 = or(_csr_exists_T_215, _csr_exists_T_65)
node _csr_exists_T_217 = or(_csr_exists_T_216, _csr_exists_T_66)
node _csr_exists_T_218 = or(_csr_exists_T_217, _csr_exists_T_67)
node _csr_exists_T_219 = or(_csr_exists_T_218, _csr_exists_T_68)
node _csr_exists_T_220 = or(_csr_exists_T_219, _csr_exists_T_69)
node _csr_exists_T_221 = or(_csr_exists_T_220, _csr_exists_T_70)
node _csr_exists_T_222 = or(_csr_exists_T_221, _csr_exists_T_71)
node _csr_exists_T_223 = or(_csr_exists_T_222, _csr_exists_T_72)
node _csr_exists_T_224 = or(_csr_exists_T_223, _csr_exists_T_73)
node _csr_exists_T_225 = or(_csr_exists_T_224, _csr_exists_T_74)
node _csr_exists_T_226 = or(_csr_exists_T_225, _csr_exists_T_75)
node _csr_exists_T_227 = or(_csr_exists_T_226, _csr_exists_T_76)
node _csr_exists_T_228 = or(_csr_exists_T_227, _csr_exists_T_77)
node _csr_exists_T_229 = or(_csr_exists_T_228, _csr_exists_T_78)
node _csr_exists_T_230 = or(_csr_exists_T_229, _csr_exists_T_79)
node _csr_exists_T_231 = or(_csr_exists_T_230, _csr_exists_T_80)
node _csr_exists_T_232 = or(_csr_exists_T_231, _csr_exists_T_81)
node _csr_exists_T_233 = or(_csr_exists_T_232, _csr_exists_T_82)
node _csr_exists_T_234 = or(_csr_exists_T_233, _csr_exists_T_83)
node _csr_exists_T_235 = or(_csr_exists_T_234, _csr_exists_T_84)
node _csr_exists_T_236 = or(_csr_exists_T_235, _csr_exists_T_85)
node _csr_exists_T_237 = or(_csr_exists_T_236, _csr_exists_T_86)
node _csr_exists_T_238 = or(_csr_exists_T_237, _csr_exists_T_87)
node _csr_exists_T_239 = or(_csr_exists_T_238, _csr_exists_T_88)
node _csr_exists_T_240 = or(_csr_exists_T_239, _csr_exists_T_89)
node _csr_exists_T_241 = or(_csr_exists_T_240, _csr_exists_T_90)
node _csr_exists_T_242 = or(_csr_exists_T_241, _csr_exists_T_91)
node _csr_exists_T_243 = or(_csr_exists_T_242, _csr_exists_T_92)
node _csr_exists_T_244 = or(_csr_exists_T_243, _csr_exists_T_93)
node _csr_exists_T_245 = or(_csr_exists_T_244, _csr_exists_T_94)
node _csr_exists_T_246 = or(_csr_exists_T_245, _csr_exists_T_95)
node _csr_exists_T_247 = or(_csr_exists_T_246, _csr_exists_T_96)
node _csr_exists_T_248 = or(_csr_exists_T_247, _csr_exists_T_97)
node _csr_exists_T_249 = or(_csr_exists_T_248, _csr_exists_T_98)
node _csr_exists_T_250 = or(_csr_exists_T_249, _csr_exists_T_99)
node _csr_exists_T_251 = or(_csr_exists_T_250, _csr_exists_T_100)
node _csr_exists_T_252 = or(_csr_exists_T_251, _csr_exists_T_101)
node _csr_exists_T_253 = or(_csr_exists_T_252, _csr_exists_T_102)
node _csr_exists_T_254 = or(_csr_exists_T_253, _csr_exists_T_103)
node _csr_exists_T_255 = or(_csr_exists_T_254, _csr_exists_T_104)
node _csr_exists_T_256 = or(_csr_exists_T_255, _csr_exists_T_105)
node _csr_exists_T_257 = or(_csr_exists_T_256, _csr_exists_T_106)
node _csr_exists_T_258 = or(_csr_exists_T_257, _csr_exists_T_107)
node _csr_exists_T_259 = or(_csr_exists_T_258, _csr_exists_T_108)
node _csr_exists_T_260 = or(_csr_exists_T_259, _csr_exists_T_109)
node _csr_exists_T_261 = or(_csr_exists_T_260, _csr_exists_T_110)
node _csr_exists_T_262 = or(_csr_exists_T_261, _csr_exists_T_111)
node _csr_exists_T_263 = or(_csr_exists_T_262, _csr_exists_T_112)
node _csr_exists_T_264 = or(_csr_exists_T_263, _csr_exists_T_113)
node _csr_exists_T_265 = or(_csr_exists_T_264, _csr_exists_T_114)
node _csr_exists_T_266 = or(_csr_exists_T_265, _csr_exists_T_115)
node _csr_exists_T_267 = or(_csr_exists_T_266, _csr_exists_T_116)
node _csr_exists_T_268 = or(_csr_exists_T_267, _csr_exists_T_117)
node _csr_exists_T_269 = or(_csr_exists_T_268, _csr_exists_T_118)
node _csr_exists_T_270 = or(_csr_exists_T_269, _csr_exists_T_119)
node _csr_exists_T_271 = or(_csr_exists_T_270, _csr_exists_T_120)
node _csr_exists_T_272 = or(_csr_exists_T_271, _csr_exists_T_121)
node _csr_exists_T_273 = or(_csr_exists_T_272, _csr_exists_T_122)
node _csr_exists_T_274 = or(_csr_exists_T_273, _csr_exists_T_123)
node _csr_exists_T_275 = or(_csr_exists_T_274, _csr_exists_T_124)
node _csr_exists_T_276 = or(_csr_exists_T_275, _csr_exists_T_125)
node _csr_exists_T_277 = or(_csr_exists_T_276, _csr_exists_T_126)
node _csr_exists_T_278 = or(_csr_exists_T_277, _csr_exists_T_127)
node _csr_exists_T_279 = or(_csr_exists_T_278, _csr_exists_T_128)
node _csr_exists_T_280 = or(_csr_exists_T_279, _csr_exists_T_129)
node _csr_exists_T_281 = or(_csr_exists_T_280, _csr_exists_T_130)
node _csr_exists_T_282 = or(_csr_exists_T_281, _csr_exists_T_131)
node _csr_exists_T_283 = or(_csr_exists_T_282, _csr_exists_T_132)
node _csr_exists_T_284 = or(_csr_exists_T_283, _csr_exists_T_133)
node _csr_exists_T_285 = or(_csr_exists_T_284, _csr_exists_T_134)
node _csr_exists_T_286 = or(_csr_exists_T_285, _csr_exists_T_135)
node _csr_exists_T_287 = or(_csr_exists_T_286, _csr_exists_T_136)
node _csr_exists_T_288 = or(_csr_exists_T_287, _csr_exists_T_137)
node _csr_exists_T_289 = or(_csr_exists_T_288, _csr_exists_T_138)
node _csr_exists_T_290 = or(_csr_exists_T_289, _csr_exists_T_139)
node _csr_exists_T_291 = or(_csr_exists_T_290, _csr_exists_T_140)
node _csr_exists_T_292 = or(_csr_exists_T_291, _csr_exists_T_141)
node _csr_exists_T_293 = or(_csr_exists_T_292, _csr_exists_T_142)
node _csr_exists_T_294 = or(_csr_exists_T_293, _csr_exists_T_143)
node _csr_exists_T_295 = or(_csr_exists_T_294, _csr_exists_T_144)
node _csr_exists_T_296 = or(_csr_exists_T_295, _csr_exists_T_145)
node _csr_exists_T_297 = or(_csr_exists_T_296, _csr_exists_T_146)
node _csr_exists_T_298 = or(_csr_exists_T_297, _csr_exists_T_147)
node _csr_exists_T_299 = or(_csr_exists_T_298, _csr_exists_T_148)
node _csr_exists_T_300 = or(_csr_exists_T_299, _csr_exists_T_149)
node _csr_exists_T_301 = or(_csr_exists_T_300, _csr_exists_T_150)
node csr_exists = or(_csr_exists_T_301, _csr_exists_T_151)
node _io_decode_0_read_illegal_T = eq(csr_addr_legal, UInt<1>(0h0))
node _io_decode_0_read_illegal_T_1 = eq(csr_exists, UInt<1>(0h0))
node _io_decode_0_read_illegal_T_2 = or(_io_decode_0_read_illegal_T, _io_decode_0_read_illegal_T_1)
node _io_decode_0_read_illegal_T_3 = eq(addr, UInt<9>(0h180))
node _io_decode_0_read_illegal_T_4 = eq(addr, UInt<11>(0h680))
node _io_decode_0_read_illegal_T_5 = or(_io_decode_0_read_illegal_T_3, _io_decode_0_read_illegal_T_4)
node _io_decode_0_read_illegal_T_6 = eq(allow_sfence_vma, UInt<1>(0h0))
node _io_decode_0_read_illegal_T_7 = and(_io_decode_0_read_illegal_T_5, _io_decode_0_read_illegal_T_6)
node _io_decode_0_read_illegal_T_8 = or(_io_decode_0_read_illegal_T_2, _io_decode_0_read_illegal_T_7)
node _io_decode_0_read_illegal_T_9 = eq(allow_counter, UInt<1>(0h0))
node _io_decode_0_read_illegal_T_10 = and(is_counter, _io_decode_0_read_illegal_T_9)
node _io_decode_0_read_illegal_T_11 = or(_io_decode_0_read_illegal_T_8, _io_decode_0_read_illegal_T_10)
wire io_decode_0_read_illegal_plaInput : UInt<12>
node io_decode_0_read_illegal_invInputs = not(io_decode_0_read_illegal_plaInput)
wire io_decode_0_read_illegal_plaOutput : UInt<1>
node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0 = bits(io_decode_0_read_illegal_plaInput, 4, 4)
node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1 = bits(io_decode_0_read_illegal_plaInput, 5, 5)
node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2 = bits(io_decode_0_read_illegal_invInputs, 6, 6)
node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3 = bits(io_decode_0_read_illegal_plaInput, 7, 7)
node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4 = bits(io_decode_0_read_illegal_plaInput, 8, 8)
node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5 = bits(io_decode_0_read_illegal_plaInput, 9, 9)
node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6 = bits(io_decode_0_read_illegal_plaInput, 10, 10)
node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7 = bits(io_decode_0_read_illegal_invInputs, 11, 11)
node io_decode_0_read_illegal_andMatrixOutputs_lo_lo = cat(io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7)
node io_decode_0_read_illegal_andMatrixOutputs_lo_hi = cat(io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5)
node io_decode_0_read_illegal_andMatrixOutputs_lo = cat(io_decode_0_read_illegal_andMatrixOutputs_lo_hi, io_decode_0_read_illegal_andMatrixOutputs_lo_lo)
node io_decode_0_read_illegal_andMatrixOutputs_hi_lo = cat(io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3)
node io_decode_0_read_illegal_andMatrixOutputs_hi_hi = cat(io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1)
node io_decode_0_read_illegal_andMatrixOutputs_hi = cat(io_decode_0_read_illegal_andMatrixOutputs_hi_hi, io_decode_0_read_illegal_andMatrixOutputs_hi_lo)
node _io_decode_0_read_illegal_andMatrixOutputs_T = cat(io_decode_0_read_illegal_andMatrixOutputs_hi, io_decode_0_read_illegal_andMatrixOutputs_lo)
node io_decode_0_read_illegal_andMatrixOutputs_0_2 = andr(_io_decode_0_read_illegal_andMatrixOutputs_T)
node io_decode_0_read_illegal_orMatrixOutputs = orr(io_decode_0_read_illegal_andMatrixOutputs_0_2)
node io_decode_0_read_illegal_invMatrixOutputs = bits(io_decode_0_read_illegal_orMatrixOutputs, 0, 0)
connect io_decode_0_read_illegal_plaOutput, io_decode_0_read_illegal_invMatrixOutputs
connect io_decode_0_read_illegal_plaInput, addr
node _io_decode_0_read_illegal_T_12 = bits(io_decode_0_read_illegal_plaOutput, 0, 0)
node _io_decode_0_read_illegal_T_13 = eq(reg_debug, UInt<1>(0h0))
node _io_decode_0_read_illegal_T_14 = and(_io_decode_0_read_illegal_T_12, _io_decode_0_read_illegal_T_13)
node _io_decode_0_read_illegal_T_15 = or(_io_decode_0_read_illegal_T_11, _io_decode_0_read_illegal_T_14)
wire io_decode_0_read_illegal_plaInput_1 : UInt<12>
node io_decode_0_read_illegal_invInputs_1 = not(io_decode_0_read_illegal_plaInput_1)
wire io_decode_0_read_illegal_plaOutput_1 : UInt<1>
connect io_decode_0_read_illegal_plaOutput_1, UInt<1>(0h0)
connect io_decode_0_read_illegal_plaInput_1, addr
node _io_decode_0_read_illegal_T_16 = bits(io_decode_0_read_illegal_plaOutput_1, 0, 0)
node _io_decode_0_read_illegal_T_17 = and(_io_decode_0_read_illegal_T_16, io.decode[0].vector_illegal)
node _io_decode_0_read_illegal_T_18 = or(_io_decode_0_read_illegal_T_15, _io_decode_0_read_illegal_T_17)
node _io_decode_0_read_illegal_T_19 = and(io.decode[0].fp_csr, io.decode[0].fp_illegal)
node _io_decode_0_read_illegal_T_20 = or(_io_decode_0_read_illegal_T_18, _io_decode_0_read_illegal_T_19)
connect io.decode[0].read_illegal, _io_decode_0_read_illegal_T_20
node _io_decode_0_write_illegal_T = bits(addr, 11, 10)
node _io_decode_0_write_illegal_T_1 = andr(_io_decode_0_write_illegal_T)
connect io.decode[0].write_illegal, _io_decode_0_write_illegal_T_1
node _io_decode_0_write_flush_addr_m_T = shl(UInt<2>(0h3), 8)
node io_decode_0_write_flush_addr_m = or(addr, _io_decode_0_write_flush_addr_m_T)
node _io_decode_0_write_flush_T = geq(io_decode_0_write_flush_addr_m, UInt<10>(0h340))
node _io_decode_0_write_flush_T_1 = leq(io_decode_0_write_flush_addr_m, UInt<10>(0h343))
node _io_decode_0_write_flush_T_2 = and(_io_decode_0_write_flush_T, _io_decode_0_write_flush_T_1)
node _io_decode_0_write_flush_T_3 = eq(_io_decode_0_write_flush_T_2, UInt<1>(0h0))
connect io.decode[0].write_flush, _io_decode_0_write_flush_T_3
node _io_decode_0_system_illegal_T = eq(csr_addr_legal, UInt<1>(0h0))
node _io_decode_0_system_illegal_T_1 = eq(is_hlsv, UInt<1>(0h0))
node _io_decode_0_system_illegal_T_2 = and(_io_decode_0_system_illegal_T, _io_decode_0_system_illegal_T_1)
node _io_decode_0_system_illegal_T_3 = eq(allow_wfi, UInt<1>(0h0))
node _io_decode_0_system_illegal_T_4 = and(is_wfi, _io_decode_0_system_illegal_T_3)
node _io_decode_0_system_illegal_T_5 = or(_io_decode_0_system_illegal_T_2, _io_decode_0_system_illegal_T_4)
node _io_decode_0_system_illegal_T_6 = eq(allow_sret, UInt<1>(0h0))
node _io_decode_0_system_illegal_T_7 = and(is_ret, _io_decode_0_system_illegal_T_6)
node _io_decode_0_system_illegal_T_8 = or(_io_decode_0_system_illegal_T_5, _io_decode_0_system_illegal_T_7)
node _io_decode_0_system_illegal_T_9 = bits(addr, 10, 10)
node _io_decode_0_system_illegal_T_10 = and(is_ret, _io_decode_0_system_illegal_T_9)
node _io_decode_0_system_illegal_T_11 = bits(addr, 7, 7)
node _io_decode_0_system_illegal_T_12 = and(_io_decode_0_system_illegal_T_10, _io_decode_0_system_illegal_T_11)
node _io_decode_0_system_illegal_T_13 = eq(reg_debug, UInt<1>(0h0))
node _io_decode_0_system_illegal_T_14 = and(_io_decode_0_system_illegal_T_12, _io_decode_0_system_illegal_T_13)
node _io_decode_0_system_illegal_T_15 = or(_io_decode_0_system_illegal_T_8, _io_decode_0_system_illegal_T_14)
node _io_decode_0_system_illegal_T_16 = or(is_sfence, is_hfence_gvma)
node _io_decode_0_system_illegal_T_17 = eq(allow_sfence_vma, UInt<1>(0h0))
node _io_decode_0_system_illegal_T_18 = and(_io_decode_0_system_illegal_T_16, _io_decode_0_system_illegal_T_17)
node _io_decode_0_system_illegal_T_19 = or(_io_decode_0_system_illegal_T_15, _io_decode_0_system_illegal_T_18)
node _io_decode_0_system_illegal_T_20 = eq(allow_hfence_vvma, UInt<1>(0h0))
node _io_decode_0_system_illegal_T_21 = and(is_hfence_vvma, _io_decode_0_system_illegal_T_20)
node _io_decode_0_system_illegal_T_22 = or(_io_decode_0_system_illegal_T_19, _io_decode_0_system_illegal_T_21)
node _io_decode_0_system_illegal_T_23 = eq(allow_hlsv, UInt<1>(0h0))
node _io_decode_0_system_illegal_T_24 = and(is_hlsv, _io_decode_0_system_illegal_T_23)
node _io_decode_0_system_illegal_T_25 = or(_io_decode_0_system_illegal_T_22, _io_decode_0_system_illegal_T_24)
connect io.decode[0].system_illegal, _io_decode_0_system_illegal_T_25
node _io_decode_0_virtual_access_illegal_T = and(reg_mstatus.v, csr_exists)
node _io_decode_0_virtual_access_illegal_T_1 = bits(addr, 9, 8)
node _io_decode_0_virtual_access_illegal_T_2 = eq(_io_decode_0_virtual_access_illegal_T_1, UInt<2>(0h2))
node _io_decode_0_virtual_access_illegal_T_3 = dshr(read_mcounteren, counter_addr)
node _io_decode_0_virtual_access_illegal_T_4 = bits(_io_decode_0_virtual_access_illegal_T_3, 0, 0)
node _io_decode_0_virtual_access_illegal_T_5 = and(is_counter, _io_decode_0_virtual_access_illegal_T_4)
node _io_decode_0_virtual_access_illegal_T_6 = dshr(read_hcounteren, counter_addr)
node _io_decode_0_virtual_access_illegal_T_7 = bits(_io_decode_0_virtual_access_illegal_T_6, 0, 0)
node _io_decode_0_virtual_access_illegal_T_8 = eq(_io_decode_0_virtual_access_illegal_T_7, UInt<1>(0h0))
node _io_decode_0_virtual_access_illegal_T_9 = bits(reg_mstatus.prv, 0, 0)
node _io_decode_0_virtual_access_illegal_T_10 = eq(_io_decode_0_virtual_access_illegal_T_9, UInt<1>(0h0))
node _io_decode_0_virtual_access_illegal_T_11 = dshr(read_scounteren, counter_addr)
node _io_decode_0_virtual_access_illegal_T_12 = bits(_io_decode_0_virtual_access_illegal_T_11, 0, 0)
node _io_decode_0_virtual_access_illegal_T_13 = eq(_io_decode_0_virtual_access_illegal_T_12, UInt<1>(0h0))
node _io_decode_0_virtual_access_illegal_T_14 = and(_io_decode_0_virtual_access_illegal_T_10, _io_decode_0_virtual_access_illegal_T_13)
node _io_decode_0_virtual_access_illegal_T_15 = or(_io_decode_0_virtual_access_illegal_T_8, _io_decode_0_virtual_access_illegal_T_14)
node _io_decode_0_virtual_access_illegal_T_16 = and(_io_decode_0_virtual_access_illegal_T_5, _io_decode_0_virtual_access_illegal_T_15)
node _io_decode_0_virtual_access_illegal_T_17 = or(_io_decode_0_virtual_access_illegal_T_2, _io_decode_0_virtual_access_illegal_T_16)
node _io_decode_0_virtual_access_illegal_T_18 = bits(addr, 9, 8)
node _io_decode_0_virtual_access_illegal_T_19 = eq(_io_decode_0_virtual_access_illegal_T_18, UInt<1>(0h1))
node _io_decode_0_virtual_access_illegal_T_20 = bits(reg_mstatus.prv, 0, 0)
node _io_decode_0_virtual_access_illegal_T_21 = eq(_io_decode_0_virtual_access_illegal_T_20, UInt<1>(0h0))
node _io_decode_0_virtual_access_illegal_T_22 = and(_io_decode_0_virtual_access_illegal_T_19, _io_decode_0_virtual_access_illegal_T_21)
node _io_decode_0_virtual_access_illegal_T_23 = or(_io_decode_0_virtual_access_illegal_T_17, _io_decode_0_virtual_access_illegal_T_22)
node _io_decode_0_virtual_access_illegal_T_24 = eq(addr, UInt<9>(0h180))
node _io_decode_0_virtual_access_illegal_T_25 = bits(reg_mstatus.prv, 0, 0)
node _io_decode_0_virtual_access_illegal_T_26 = and(_io_decode_0_virtual_access_illegal_T_24, _io_decode_0_virtual_access_illegal_T_25)
node _io_decode_0_virtual_access_illegal_T_27 = and(_io_decode_0_virtual_access_illegal_T_26, reg_hstatus.vtvm)
node _io_decode_0_virtual_access_illegal_T_28 = or(_io_decode_0_virtual_access_illegal_T_23, _io_decode_0_virtual_access_illegal_T_27)
node _io_decode_0_virtual_access_illegal_T_29 = and(_io_decode_0_virtual_access_illegal_T, _io_decode_0_virtual_access_illegal_T_28)
connect io.decode[0].virtual_access_illegal, _io_decode_0_virtual_access_illegal_T_29
node _io_decode_0_virtual_system_illegal_T = or(is_hfence_vvma, is_hfence_gvma)
node _io_decode_0_virtual_system_illegal_T_1 = or(_io_decode_0_virtual_system_illegal_T, is_hlsv)
node _io_decode_0_virtual_system_illegal_T_2 = bits(reg_mstatus.prv, 0, 0)
node _io_decode_0_virtual_system_illegal_T_3 = eq(_io_decode_0_virtual_system_illegal_T_2, UInt<1>(0h0))
node _io_decode_0_virtual_system_illegal_T_4 = eq(reg_mstatus.tw, UInt<1>(0h0))
node _io_decode_0_virtual_system_illegal_T_5 = and(_io_decode_0_virtual_system_illegal_T_4, reg_hstatus.vtw)
node _io_decode_0_virtual_system_illegal_T_6 = or(_io_decode_0_virtual_system_illegal_T_3, _io_decode_0_virtual_system_illegal_T_5)
node _io_decode_0_virtual_system_illegal_T_7 = and(is_wfi, _io_decode_0_virtual_system_illegal_T_6)
node _io_decode_0_virtual_system_illegal_T_8 = or(_io_decode_0_virtual_system_illegal_T_1, _io_decode_0_virtual_system_illegal_T_7)
node _io_decode_0_virtual_system_illegal_T_9 = bits(addr, 9, 8)
node _io_decode_0_virtual_system_illegal_T_10 = eq(_io_decode_0_virtual_system_illegal_T_9, UInt<1>(0h1))
node _io_decode_0_virtual_system_illegal_T_11 = and(is_ret, _io_decode_0_virtual_system_illegal_T_10)
node _io_decode_0_virtual_system_illegal_T_12 = bits(reg_mstatus.prv, 0, 0)
node _io_decode_0_virtual_system_illegal_T_13 = eq(_io_decode_0_virtual_system_illegal_T_12, UInt<1>(0h0))
node _io_decode_0_virtual_system_illegal_T_14 = or(_io_decode_0_virtual_system_illegal_T_13, reg_hstatus.vtsr)
node _io_decode_0_virtual_system_illegal_T_15 = and(_io_decode_0_virtual_system_illegal_T_11, _io_decode_0_virtual_system_illegal_T_14)
node _io_decode_0_virtual_system_illegal_T_16 = or(_io_decode_0_virtual_system_illegal_T_8, _io_decode_0_virtual_system_illegal_T_15)
node _io_decode_0_virtual_system_illegal_T_17 = bits(reg_mstatus.prv, 0, 0)
node _io_decode_0_virtual_system_illegal_T_18 = eq(_io_decode_0_virtual_system_illegal_T_17, UInt<1>(0h0))
node _io_decode_0_virtual_system_illegal_T_19 = or(_io_decode_0_virtual_system_illegal_T_18, reg_hstatus.vtvm)
node _io_decode_0_virtual_system_illegal_T_20 = and(is_sfence, _io_decode_0_virtual_system_illegal_T_19)
node _io_decode_0_virtual_system_illegal_T_21 = or(_io_decode_0_virtual_system_illegal_T_16, _io_decode_0_virtual_system_illegal_T_20)
node _io_decode_0_virtual_system_illegal_T_22 = and(reg_mstatus.v, _io_decode_0_virtual_system_illegal_T_21)
connect io.decode[0].virtual_system_illegal, _io_decode_0_virtual_system_illegal_T_22
node addr_1 = bits(io.decode[1].inst, 31, 20)
wire decoded_plaInput_2 : UInt<32>
node decoded_invInputs_2 = not(decoded_plaInput_2)
wire decoded_2 : UInt<9>
node decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(decoded_invInputs_2, 20, 20)
node decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(decoded_invInputs_2, 21, 21)
node decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(decoded_invInputs_2, 22, 22)
node decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(decoded_invInputs_2, 23, 23)
node decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(decoded_invInputs_2, 24, 24)
node decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(decoded_invInputs_2, 25, 25)
node decoded_andMatrixOutputs_andMatrixInput_6_12 = bits(decoded_invInputs_2, 26, 26)
node decoded_andMatrixOutputs_andMatrixInput_7_12 = bits(decoded_invInputs_2, 27, 27)
node decoded_andMatrixOutputs_andMatrixInput_8_12 = bits(decoded_invInputs_2, 28, 28)
node decoded_andMatrixOutputs_andMatrixInput_9_12 = bits(decoded_invInputs_2, 29, 29)
node decoded_andMatrixOutputs_andMatrixInput_10_6 = bits(decoded_invInputs_2, 30, 30)
node decoded_andMatrixOutputs_andMatrixInput_11_6 = bits(decoded_invInputs_2, 31, 31)
node decoded_andMatrixOutputs_lo_lo_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_9_12, decoded_andMatrixOutputs_andMatrixInput_10_6)
node decoded_andMatrixOutputs_lo_lo_12 = cat(decoded_andMatrixOutputs_lo_lo_hi_6, decoded_andMatrixOutputs_andMatrixInput_11_6)
node decoded_andMatrixOutputs_lo_hi_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_6_12, decoded_andMatrixOutputs_andMatrixInput_7_12)
node decoded_andMatrixOutputs_lo_hi_12 = cat(decoded_andMatrixOutputs_lo_hi_hi_12, decoded_andMatrixOutputs_andMatrixInput_8_12)
node decoded_andMatrixOutputs_lo_12 = cat(decoded_andMatrixOutputs_lo_hi_12, decoded_andMatrixOutputs_lo_lo_12)
node decoded_andMatrixOutputs_hi_lo_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_3_12, decoded_andMatrixOutputs_andMatrixInput_4_12)
node decoded_andMatrixOutputs_hi_lo_12 = cat(decoded_andMatrixOutputs_hi_lo_hi_6, decoded_andMatrixOutputs_andMatrixInput_5_12)
node decoded_andMatrixOutputs_hi_hi_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_0_14, decoded_andMatrixOutputs_andMatrixInput_1_14)
node decoded_andMatrixOutputs_hi_hi_12 = cat(decoded_andMatrixOutputs_hi_hi_hi_12, decoded_andMatrixOutputs_andMatrixInput_2_12)
node decoded_andMatrixOutputs_hi_12 = cat(decoded_andMatrixOutputs_hi_hi_12, decoded_andMatrixOutputs_hi_lo_12)
node _decoded_andMatrixOutputs_T_14 = cat(decoded_andMatrixOutputs_hi_12, decoded_andMatrixOutputs_lo_12)
node decoded_andMatrixOutputs_6_2_2 = andr(_decoded_andMatrixOutputs_T_14)
node decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(decoded_plaInput_2, 20, 20)
node decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(decoded_invInputs_2, 21, 21)
node decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(decoded_invInputs_2, 22, 22)
node decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(decoded_invInputs_2, 23, 23)
node decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(decoded_invInputs_2, 24, 24)
node decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(decoded_invInputs_2, 25, 25)
node decoded_andMatrixOutputs_andMatrixInput_6_13 = bits(decoded_invInputs_2, 26, 26)
node decoded_andMatrixOutputs_andMatrixInput_7_13 = bits(decoded_invInputs_2, 27, 27)
node decoded_andMatrixOutputs_andMatrixInput_8_13 = bits(decoded_invInputs_2, 28, 28)
node decoded_andMatrixOutputs_andMatrixInput_9_13 = bits(decoded_invInputs_2, 29, 29)
node decoded_andMatrixOutputs_andMatrixInput_10_7 = bits(decoded_invInputs_2, 30, 30)
node decoded_andMatrixOutputs_andMatrixInput_11_7 = bits(decoded_invInputs_2, 31, 31)
node decoded_andMatrixOutputs_lo_lo_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_9_13, decoded_andMatrixOutputs_andMatrixInput_10_7)
node decoded_andMatrixOutputs_lo_lo_13 = cat(decoded_andMatrixOutputs_lo_lo_hi_7, decoded_andMatrixOutputs_andMatrixInput_11_7)
node decoded_andMatrixOutputs_lo_hi_hi_13 = cat(decoded_andMatrixOutputs_andMatrixInput_6_13, decoded_andMatrixOutputs_andMatrixInput_7_13)
node decoded_andMatrixOutputs_lo_hi_13 = cat(decoded_andMatrixOutputs_lo_hi_hi_13, decoded_andMatrixOutputs_andMatrixInput_8_13)
node decoded_andMatrixOutputs_lo_13 = cat(decoded_andMatrixOutputs_lo_hi_13, decoded_andMatrixOutputs_lo_lo_13)
node decoded_andMatrixOutputs_hi_lo_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_3_13, decoded_andMatrixOutputs_andMatrixInput_4_13)
node decoded_andMatrixOutputs_hi_lo_13 = cat(decoded_andMatrixOutputs_hi_lo_hi_7, decoded_andMatrixOutputs_andMatrixInput_5_13)
node decoded_andMatrixOutputs_hi_hi_hi_13 = cat(decoded_andMatrixOutputs_andMatrixInput_0_15, decoded_andMatrixOutputs_andMatrixInput_1_15)
node decoded_andMatrixOutputs_hi_hi_13 = cat(decoded_andMatrixOutputs_hi_hi_hi_13, decoded_andMatrixOutputs_andMatrixInput_2_13)
node decoded_andMatrixOutputs_hi_13 = cat(decoded_andMatrixOutputs_hi_hi_13, decoded_andMatrixOutputs_hi_lo_13)
node _decoded_andMatrixOutputs_T_15 = cat(decoded_andMatrixOutputs_hi_13, decoded_andMatrixOutputs_lo_13)
node decoded_andMatrixOutputs_4_2_2 = andr(_decoded_andMatrixOutputs_T_15)
node decoded_andMatrixOutputs_andMatrixInput_0_16 = bits(decoded_plaInput_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_16 = bits(decoded_invInputs_2, 22, 22)
node decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(decoded_invInputs_2, 23, 23)
node decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(decoded_invInputs_2, 24, 24)
node decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(decoded_invInputs_2, 25, 25)
node decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(decoded_invInputs_2, 26, 26)
node decoded_andMatrixOutputs_andMatrixInput_6_14 = bits(decoded_invInputs_2, 27, 27)
node decoded_andMatrixOutputs_andMatrixInput_7_14 = bits(decoded_plaInput_2, 28, 28)
node decoded_andMatrixOutputs_andMatrixInput_8_14 = bits(decoded_invInputs_2, 30, 30)
node decoded_andMatrixOutputs_andMatrixInput_9_14 = bits(decoded_invInputs_2, 31, 31)
node decoded_andMatrixOutputs_lo_lo_14 = cat(decoded_andMatrixOutputs_andMatrixInput_8_14, decoded_andMatrixOutputs_andMatrixInput_9_14)
node decoded_andMatrixOutputs_lo_hi_hi_14 = cat(decoded_andMatrixOutputs_andMatrixInput_5_14, decoded_andMatrixOutputs_andMatrixInput_6_14)
node decoded_andMatrixOutputs_lo_hi_14 = cat(decoded_andMatrixOutputs_lo_hi_hi_14, decoded_andMatrixOutputs_andMatrixInput_7_14)
node decoded_andMatrixOutputs_lo_14 = cat(decoded_andMatrixOutputs_lo_hi_14, decoded_andMatrixOutputs_lo_lo_14)
node decoded_andMatrixOutputs_hi_lo_14 = cat(decoded_andMatrixOutputs_andMatrixInput_3_14, decoded_andMatrixOutputs_andMatrixInput_4_14)
node decoded_andMatrixOutputs_hi_hi_hi_14 = cat(decoded_andMatrixOutputs_andMatrixInput_0_16, decoded_andMatrixOutputs_andMatrixInput_1_16)
node decoded_andMatrixOutputs_hi_hi_14 = cat(decoded_andMatrixOutputs_hi_hi_hi_14, decoded_andMatrixOutputs_andMatrixInput_2_14)
node decoded_andMatrixOutputs_hi_14 = cat(decoded_andMatrixOutputs_hi_hi_14, decoded_andMatrixOutputs_hi_lo_14)
node _decoded_andMatrixOutputs_T_16 = cat(decoded_andMatrixOutputs_hi_14, decoded_andMatrixOutputs_lo_14)
node decoded_andMatrixOutputs_3_2_2 = andr(_decoded_andMatrixOutputs_T_16)
node decoded_andMatrixOutputs_andMatrixInput_0_17 = bits(decoded_plaInput_2, 22, 22)
node decoded_andMatrixOutputs_andMatrixInput_1_17 = bits(decoded_invInputs_2, 23, 23)
node decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(decoded_invInputs_2, 24, 24)
node decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(decoded_invInputs_2, 25, 25)
node decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(decoded_invInputs_2, 26, 26)
node decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(decoded_invInputs_2, 27, 27)
node decoded_andMatrixOutputs_andMatrixInput_6_15 = bits(decoded_plaInput_2, 28, 28)
node decoded_andMatrixOutputs_andMatrixInput_7_15 = bits(decoded_invInputs_2, 29, 29)
node decoded_andMatrixOutputs_andMatrixInput_8_15 = bits(decoded_invInputs_2, 30, 30)
node decoded_andMatrixOutputs_andMatrixInput_9_15 = bits(decoded_invInputs_2, 31, 31)
node decoded_andMatrixOutputs_lo_lo_15 = cat(decoded_andMatrixOutputs_andMatrixInput_8_15, decoded_andMatrixOutputs_andMatrixInput_9_15)
node decoded_andMatrixOutputs_lo_hi_hi_15 = cat(decoded_andMatrixOutputs_andMatrixInput_5_15, decoded_andMatrixOutputs_andMatrixInput_6_15)
node decoded_andMatrixOutputs_lo_hi_15 = cat(decoded_andMatrixOutputs_lo_hi_hi_15, decoded_andMatrixOutputs_andMatrixInput_7_15)
node decoded_andMatrixOutputs_lo_15 = cat(decoded_andMatrixOutputs_lo_hi_15, decoded_andMatrixOutputs_lo_lo_15)
node decoded_andMatrixOutputs_hi_lo_15 = cat(decoded_andMatrixOutputs_andMatrixInput_3_15, decoded_andMatrixOutputs_andMatrixInput_4_15)
node decoded_andMatrixOutputs_hi_hi_hi_15 = cat(decoded_andMatrixOutputs_andMatrixInput_0_17, decoded_andMatrixOutputs_andMatrixInput_1_17)
node decoded_andMatrixOutputs_hi_hi_15 = cat(decoded_andMatrixOutputs_hi_hi_hi_15, decoded_andMatrixOutputs_andMatrixInput_2_15)
node decoded_andMatrixOutputs_hi_15 = cat(decoded_andMatrixOutputs_hi_hi_15, decoded_andMatrixOutputs_hi_lo_15)
node _decoded_andMatrixOutputs_T_17 = cat(decoded_andMatrixOutputs_hi_15, decoded_andMatrixOutputs_lo_15)
node decoded_andMatrixOutputs_1_2_2 = andr(_decoded_andMatrixOutputs_T_17)
node decoded_andMatrixOutputs_andMatrixInput_0_18 = bits(decoded_plaInput_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_18 = bits(decoded_plaInput_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_16 = bits(decoded_invInputs_2, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_3_16 = bits(decoded_invInputs_2, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_4_16 = bits(decoded_plaInput_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_5_16 = bits(decoded_plaInput_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_6_16 = bits(decoded_plaInput_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_7_16 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_8_16 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_9_16 = bits(decoded_invInputs_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_10_8 = bits(decoded_plaInput_2, 25, 25)
node decoded_andMatrixOutputs_andMatrixInput_11_8 = bits(decoded_invInputs_2, 26, 26)
node decoded_andMatrixOutputs_andMatrixInput_12_2 = bits(decoded_invInputs_2, 27, 27)
node decoded_andMatrixOutputs_andMatrixInput_13_2 = bits(decoded_plaInput_2, 28, 28)
node decoded_andMatrixOutputs_andMatrixInput_14_2 = bits(decoded_invInputs_2, 29, 29)
node decoded_andMatrixOutputs_andMatrixInput_15_2 = bits(decoded_invInputs_2, 30, 30)
node decoded_andMatrixOutputs_andMatrixInput_16_2 = bits(decoded_invInputs_2, 31, 31)
node decoded_andMatrixOutputs_lo_lo_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_15_2, decoded_andMatrixOutputs_andMatrixInput_16_2)
node decoded_andMatrixOutputs_lo_lo_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_13_2, decoded_andMatrixOutputs_andMatrixInput_14_2)
node decoded_andMatrixOutputs_lo_lo_16 = cat(decoded_andMatrixOutputs_lo_lo_hi_8, decoded_andMatrixOutputs_lo_lo_lo_2)
node decoded_andMatrixOutputs_lo_hi_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_11_8, decoded_andMatrixOutputs_andMatrixInput_12_2)
node decoded_andMatrixOutputs_lo_hi_hi_16 = cat(decoded_andMatrixOutputs_andMatrixInput_9_16, decoded_andMatrixOutputs_andMatrixInput_10_8)
node decoded_andMatrixOutputs_lo_hi_16 = cat(decoded_andMatrixOutputs_lo_hi_hi_16, decoded_andMatrixOutputs_lo_hi_lo_2)
node decoded_andMatrixOutputs_lo_16 = cat(decoded_andMatrixOutputs_lo_hi_16, decoded_andMatrixOutputs_lo_lo_16)
node decoded_andMatrixOutputs_hi_lo_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_7_16, decoded_andMatrixOutputs_andMatrixInput_8_16)
node decoded_andMatrixOutputs_hi_lo_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_5_16, decoded_andMatrixOutputs_andMatrixInput_6_16)
node decoded_andMatrixOutputs_hi_lo_16 = cat(decoded_andMatrixOutputs_hi_lo_hi_8, decoded_andMatrixOutputs_hi_lo_lo_2)
node decoded_andMatrixOutputs_hi_hi_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_3_16, decoded_andMatrixOutputs_andMatrixInput_4_16)
node decoded_andMatrixOutputs_hi_hi_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_18, decoded_andMatrixOutputs_andMatrixInput_1_18)
node decoded_andMatrixOutputs_hi_hi_hi_16 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_2_16)
node decoded_andMatrixOutputs_hi_hi_16 = cat(decoded_andMatrixOutputs_hi_hi_hi_16, decoded_andMatrixOutputs_hi_hi_lo_2)
node decoded_andMatrixOutputs_hi_16 = cat(decoded_andMatrixOutputs_hi_hi_16, decoded_andMatrixOutputs_hi_lo_16)
node _decoded_andMatrixOutputs_T_18 = cat(decoded_andMatrixOutputs_hi_16, decoded_andMatrixOutputs_lo_16)
node decoded_andMatrixOutputs_0_2_2 = andr(_decoded_andMatrixOutputs_T_18)
node decoded_andMatrixOutputs_andMatrixInput_0_19 = bits(decoded_plaInput_2, 22, 22)
node decoded_andMatrixOutputs_andMatrixInput_1_19 = bits(decoded_invInputs_2, 23, 23)
node decoded_andMatrixOutputs_andMatrixInput_2_17 = bits(decoded_invInputs_2, 24, 24)
node decoded_andMatrixOutputs_andMatrixInput_3_17 = bits(decoded_invInputs_2, 25, 25)
node decoded_andMatrixOutputs_andMatrixInput_4_17 = bits(decoded_invInputs_2, 26, 26)
node decoded_andMatrixOutputs_andMatrixInput_5_17 = bits(decoded_invInputs_2, 27, 27)
node decoded_andMatrixOutputs_andMatrixInput_6_17 = bits(decoded_plaInput_2, 28, 28)
node decoded_andMatrixOutputs_andMatrixInput_7_17 = bits(decoded_plaInput_2, 29, 29)
node decoded_andMatrixOutputs_andMatrixInput_8_17 = bits(decoded_invInputs_2, 30, 30)
node decoded_andMatrixOutputs_andMatrixInput_9_17 = bits(decoded_invInputs_2, 31, 31)
node decoded_andMatrixOutputs_lo_lo_17 = cat(decoded_andMatrixOutputs_andMatrixInput_8_17, decoded_andMatrixOutputs_andMatrixInput_9_17)
node decoded_andMatrixOutputs_lo_hi_hi_17 = cat(decoded_andMatrixOutputs_andMatrixInput_5_17, decoded_andMatrixOutputs_andMatrixInput_6_17)
node decoded_andMatrixOutputs_lo_hi_17 = cat(decoded_andMatrixOutputs_lo_hi_hi_17, decoded_andMatrixOutputs_andMatrixInput_7_17)
node decoded_andMatrixOutputs_lo_17 = cat(decoded_andMatrixOutputs_lo_hi_17, decoded_andMatrixOutputs_lo_lo_17)
node decoded_andMatrixOutputs_hi_lo_17 = cat(decoded_andMatrixOutputs_andMatrixInput_3_17, decoded_andMatrixOutputs_andMatrixInput_4_17)
node decoded_andMatrixOutputs_hi_hi_hi_17 = cat(decoded_andMatrixOutputs_andMatrixInput_0_19, decoded_andMatrixOutputs_andMatrixInput_1_19)
node decoded_andMatrixOutputs_hi_hi_17 = cat(decoded_andMatrixOutputs_hi_hi_hi_17, decoded_andMatrixOutputs_andMatrixInput_2_17)
node decoded_andMatrixOutputs_hi_17 = cat(decoded_andMatrixOutputs_hi_hi_17, decoded_andMatrixOutputs_hi_lo_17)
node _decoded_andMatrixOutputs_T_19 = cat(decoded_andMatrixOutputs_hi_17, decoded_andMatrixOutputs_lo_17)
node decoded_andMatrixOutputs_5_2_2 = andr(_decoded_andMatrixOutputs_T_19)
node decoded_andMatrixOutputs_andMatrixInput_0_20 = bits(decoded_plaInput_2, 30, 30)
node decoded_andMatrixOutputs_andMatrixInput_1_20 = bits(decoded_invInputs_2, 31, 31)
node _decoded_andMatrixOutputs_T_20 = cat(decoded_andMatrixOutputs_andMatrixInput_0_20, decoded_andMatrixOutputs_andMatrixInput_1_20)
node decoded_andMatrixOutputs_2_2_2 = andr(_decoded_andMatrixOutputs_T_20)
node _decoded_orMatrixOutputs_T_14 = orr(decoded_andMatrixOutputs_0_2_2)
node _decoded_orMatrixOutputs_T_15 = orr(decoded_andMatrixOutputs_1_2_2)
node _decoded_orMatrixOutputs_T_16 = orr(decoded_andMatrixOutputs_5_2_2)
node _decoded_orMatrixOutputs_T_17 = cat(decoded_andMatrixOutputs_3_2_2, decoded_andMatrixOutputs_2_2_2)
node _decoded_orMatrixOutputs_T_18 = orr(_decoded_orMatrixOutputs_T_17)
node _decoded_orMatrixOutputs_T_19 = orr(decoded_andMatrixOutputs_4_2_2)
node _decoded_orMatrixOutputs_T_20 = orr(decoded_andMatrixOutputs_6_2_2)
node decoded_orMatrixOutputs_lo_lo_2 = cat(UInt<1>(0h0), UInt<1>(0h0))
node decoded_orMatrixOutputs_lo_hi_2 = cat(_decoded_orMatrixOutputs_T_14, UInt<1>(0h0))
node decoded_orMatrixOutputs_lo_2 = cat(decoded_orMatrixOutputs_lo_hi_2, decoded_orMatrixOutputs_lo_lo_2)
node decoded_orMatrixOutputs_hi_lo_2 = cat(_decoded_orMatrixOutputs_T_16, _decoded_orMatrixOutputs_T_15)
node decoded_orMatrixOutputs_hi_hi_hi_2 = cat(_decoded_orMatrixOutputs_T_20, _decoded_orMatrixOutputs_T_19)
node decoded_orMatrixOutputs_hi_hi_2 = cat(decoded_orMatrixOutputs_hi_hi_hi_2, _decoded_orMatrixOutputs_T_18)
node decoded_orMatrixOutputs_hi_2 = cat(decoded_orMatrixOutputs_hi_hi_2, decoded_orMatrixOutputs_hi_lo_2)
node decoded_orMatrixOutputs_2 = cat(decoded_orMatrixOutputs_hi_2, decoded_orMatrixOutputs_lo_2)
node _decoded_invMatrixOutputs_T_18 = bits(decoded_orMatrixOutputs_2, 0, 0)
node _decoded_invMatrixOutputs_T_19 = bits(decoded_orMatrixOutputs_2, 1, 1)
node _decoded_invMatrixOutputs_T_20 = bits(decoded_orMatrixOutputs_2, 2, 2)
node _decoded_invMatrixOutputs_T_21 = bits(decoded_orMatrixOutputs_2, 3, 3)
node _decoded_invMatrixOutputs_T_22 = bits(decoded_orMatrixOutputs_2, 4, 4)
node _decoded_invMatrixOutputs_T_23 = bits(decoded_orMatrixOutputs_2, 5, 5)
node _decoded_invMatrixOutputs_T_24 = bits(decoded_orMatrixOutputs_2, 6, 6)
node _decoded_invMatrixOutputs_T_25 = bits(decoded_orMatrixOutputs_2, 7, 7)
node _decoded_invMatrixOutputs_T_26 = bits(decoded_orMatrixOutputs_2, 8, 8)
node decoded_invMatrixOutputs_lo_lo_2 = cat(_decoded_invMatrixOutputs_T_19, _decoded_invMatrixOutputs_T_18)
node decoded_invMatrixOutputs_lo_hi_2 = cat(_decoded_invMatrixOutputs_T_21, _decoded_invMatrixOutputs_T_20)
node decoded_invMatrixOutputs_lo_2 = cat(decoded_invMatrixOutputs_lo_hi_2, decoded_invMatrixOutputs_lo_lo_2)
node decoded_invMatrixOutputs_hi_lo_2 = cat(_decoded_invMatrixOutputs_T_23, _decoded_invMatrixOutputs_T_22)
node decoded_invMatrixOutputs_hi_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_26, _decoded_invMatrixOutputs_T_25)
node decoded_invMatrixOutputs_hi_hi_2 = cat(decoded_invMatrixOutputs_hi_hi_hi_2, _decoded_invMatrixOutputs_T_24)
node decoded_invMatrixOutputs_hi_2 = cat(decoded_invMatrixOutputs_hi_hi_2, decoded_invMatrixOutputs_hi_lo_2)
node decoded_invMatrixOutputs_2 = cat(decoded_invMatrixOutputs_hi_2, decoded_invMatrixOutputs_lo_2)
connect decoded_2, decoded_invMatrixOutputs_2
connect decoded_plaInput_2, io.decode[1].inst
node _T_90 = bits(decoded_2, 8, 8)
node _T_91 = bits(decoded_2, 7, 7)
node _T_92 = bits(decoded_2, 6, 6)
node _T_93 = bits(decoded_2, 5, 5)
node _T_94 = bits(decoded_2, 4, 4)
node _T_95 = bits(decoded_2, 3, 3)
node _T_96 = bits(decoded_2, 2, 2)
node _T_97 = bits(decoded_2, 1, 1)
node _T_98 = bits(decoded_2, 0, 0)
node _T_99 = bits(_T_90, 0, 0)
node is_break_1 = bits(_T_91, 0, 0)
node is_ret_1 = bits(_T_92, 0, 0)
node _T_100 = bits(_T_93, 0, 0)
node is_wfi_1 = bits(_T_94, 0, 0)
node is_sfence_1 = bits(_T_95, 0, 0)
node is_hfence_vvma_1 = bits(_T_96, 0, 0)
node is_hfence_gvma_1 = bits(_T_97, 0, 0)
node is_hlsv_1 = bits(_T_98, 0, 0)
node _is_counter_T_6 = geq(addr_1, UInt<12>(0hc00))
node _is_counter_T_7 = lt(addr_1, UInt<12>(0hc20))
node _is_counter_T_8 = and(_is_counter_T_6, _is_counter_T_7)
node _is_counter_T_9 = geq(addr_1, UInt<12>(0hc80))
node _is_counter_T_10 = lt(addr_1, UInt<12>(0hca0))
node _is_counter_T_11 = and(_is_counter_T_9, _is_counter_T_10)
node is_counter_1 = or(_is_counter_T_8, _is_counter_T_11)
node _allow_wfi_T_7 = gt(reg_mstatus.prv, UInt<1>(0h1))
node _allow_wfi_T_8 = or(UInt<1>(0h0), _allow_wfi_T_7)
node _allow_wfi_T_9 = eq(reg_mstatus.tw, UInt<1>(0h0))
node _allow_wfi_T_10 = eq(reg_mstatus.v, UInt<1>(0h0))
node _allow_wfi_T_11 = eq(reg_hstatus.vtw, UInt<1>(0h0))
node _allow_wfi_T_12 = or(_allow_wfi_T_10, _allow_wfi_T_11)
node _allow_wfi_T_13 = and(_allow_wfi_T_9, _allow_wfi_T_12)
node allow_wfi_1 = or(_allow_wfi_T_8, _allow_wfi_T_13)
node _allow_sfence_vma_T_4 = gt(reg_mstatus.prv, UInt<1>(0h1))
node _allow_sfence_vma_T_5 = or(UInt<1>(0h0), _allow_sfence_vma_T_4)
node _allow_sfence_vma_T_6 = mux(reg_mstatus.v, reg_hstatus.vtvm, reg_mstatus.tvm)
node _allow_sfence_vma_T_7 = eq(_allow_sfence_vma_T_6, UInt<1>(0h0))
node allow_sfence_vma_1 = or(_allow_sfence_vma_T_5, _allow_sfence_vma_T_7)
node _allow_hfence_vvma_T_3 = eq(reg_mstatus.v, UInt<1>(0h0))
node _allow_hfence_vvma_T_4 = geq(reg_mstatus.prv, UInt<1>(0h1))
node _allow_hfence_vvma_T_5 = and(_allow_hfence_vvma_T_3, _allow_hfence_vvma_T_4)
node allow_hfence_vvma_1 = or(UInt<1>(0h1), _allow_hfence_vvma_T_5)
node _allow_hlsv_T_4 = eq(reg_mstatus.v, UInt<1>(0h0))
node _allow_hlsv_T_5 = geq(reg_mstatus.prv, UInt<1>(0h1))
node _allow_hlsv_T_6 = or(_allow_hlsv_T_5, reg_hstatus.hu)
node _allow_hlsv_T_7 = and(_allow_hlsv_T_4, _allow_hlsv_T_6)
node allow_hlsv_1 = or(UInt<1>(0h1), _allow_hlsv_T_7)
node _allow_sret_T_4 = gt(reg_mstatus.prv, UInt<1>(0h1))
node _allow_sret_T_5 = or(UInt<1>(0h0), _allow_sret_T_4)
node _allow_sret_T_6 = mux(reg_mstatus.v, reg_hstatus.vtsr, reg_mstatus.tsr)
node _allow_sret_T_7 = eq(_allow_sret_T_6, UInt<1>(0h0))
node allow_sret_1 = or(_allow_sret_T_5, _allow_sret_T_7)
node counter_addr_1 = bits(addr_1, 4, 0)
node _allow_counter_T_17 = gt(reg_mstatus.prv, UInt<1>(0h1))
node _allow_counter_T_18 = dshr(read_mcounteren, counter_addr_1)
node _allow_counter_T_19 = bits(_allow_counter_T_18, 0, 0)
node _allow_counter_T_20 = or(_allow_counter_T_17, _allow_counter_T_19)
node _allow_counter_T_21 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _allow_counter_T_22 = geq(reg_mstatus.prv, UInt<1>(0h1))
node _allow_counter_T_23 = or(_allow_counter_T_21, _allow_counter_T_22)
node _allow_counter_T_24 = dshr(read_scounteren, counter_addr_1)
node _allow_counter_T_25 = bits(_allow_counter_T_24, 0, 0)
node _allow_counter_T_26 = or(_allow_counter_T_23, _allow_counter_T_25)
node _allow_counter_T_27 = and(_allow_counter_T_20, _allow_counter_T_26)
node _allow_counter_T_28 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _allow_counter_T_29 = eq(reg_mstatus.v, UInt<1>(0h0))
node _allow_counter_T_30 = or(_allow_counter_T_28, _allow_counter_T_29)
node _allow_counter_T_31 = dshr(read_hcounteren, counter_addr_1)
node _allow_counter_T_32 = bits(_allow_counter_T_31, 0, 0)
node _allow_counter_T_33 = or(_allow_counter_T_30, _allow_counter_T_32)
node allow_counter_1 = and(_allow_counter_T_27, _allow_counter_T_33)
node _io_decode_1_fp_illegal_T = eq(io.status.fs, UInt<1>(0h0))
node _io_decode_1_fp_illegal_T_1 = eq(reg_vsstatus.fs, UInt<1>(0h0))
node _io_decode_1_fp_illegal_T_2 = and(reg_mstatus.v, _io_decode_1_fp_illegal_T_1)
node _io_decode_1_fp_illegal_T_3 = or(_io_decode_1_fp_illegal_T, _io_decode_1_fp_illegal_T_2)
node _io_decode_1_fp_illegal_T_4 = bits(reg_misa, 5, 5)
node _io_decode_1_fp_illegal_T_5 = eq(_io_decode_1_fp_illegal_T_4, UInt<1>(0h0))
node _io_decode_1_fp_illegal_T_6 = or(_io_decode_1_fp_illegal_T_3, _io_decode_1_fp_illegal_T_5)
connect io.decode[1].fp_illegal, _io_decode_1_fp_illegal_T_6
node _io_decode_1_vector_illegal_T = eq(io.status.vs, UInt<1>(0h0))
node _io_decode_1_vector_illegal_T_1 = eq(reg_vsstatus.vs, UInt<1>(0h0))
node _io_decode_1_vector_illegal_T_2 = and(reg_mstatus.v, _io_decode_1_vector_illegal_T_1)
node _io_decode_1_vector_illegal_T_3 = or(_io_decode_1_vector_illegal_T, _io_decode_1_vector_illegal_T_2)
node _io_decode_1_vector_illegal_T_4 = bits(reg_misa, 21, 21)
node _io_decode_1_vector_illegal_T_5 = eq(_io_decode_1_vector_illegal_T_4, UInt<1>(0h0))
node _io_decode_1_vector_illegal_T_6 = or(_io_decode_1_vector_illegal_T_3, _io_decode_1_vector_illegal_T_5)
connect io.decode[1].vector_illegal, _io_decode_1_vector_illegal_T_6
wire io_decode_1_fp_csr_plaInput : UInt<12>
node io_decode_1_fp_csr_invInputs = not(io_decode_1_fp_csr_plaInput)
wire io_decode_1_fp_csr_plaOutput : UInt<1>
node io_decode_1_fp_csr_andMatrixOutputs_andMatrixInput_0 = bits(io_decode_1_fp_csr_invInputs, 8, 8)
node io_decode_1_fp_csr_andMatrixOutputs_andMatrixInput_1 = bits(io_decode_1_fp_csr_invInputs, 9, 9)
node io_decode_1_fp_csr_andMatrixOutputs_andMatrixInput_2 = bits(io_decode_1_fp_csr_invInputs, 10, 10)
node io_decode_1_fp_csr_andMatrixOutputs_andMatrixInput_3 = bits(io_decode_1_fp_csr_invInputs, 11, 11)
node io_decode_1_fp_csr_andMatrixOutputs_lo = cat(io_decode_1_fp_csr_andMatrixOutputs_andMatrixInput_2, io_decode_1_fp_csr_andMatrixOutputs_andMatrixInput_3)
node io_decode_1_fp_csr_andMatrixOutputs_hi = cat(io_decode_1_fp_csr_andMatrixOutputs_andMatrixInput_0, io_decode_1_fp_csr_andMatrixOutputs_andMatrixInput_1)
node _io_decode_1_fp_csr_andMatrixOutputs_T = cat(io_decode_1_fp_csr_andMatrixOutputs_hi, io_decode_1_fp_csr_andMatrixOutputs_lo)
node io_decode_1_fp_csr_andMatrixOutputs_0_2 = andr(_io_decode_1_fp_csr_andMatrixOutputs_T)
node io_decode_1_fp_csr_orMatrixOutputs = orr(io_decode_1_fp_csr_andMatrixOutputs_0_2)
node io_decode_1_fp_csr_invMatrixOutputs = bits(io_decode_1_fp_csr_orMatrixOutputs, 0, 0)
connect io_decode_1_fp_csr_plaOutput, io_decode_1_fp_csr_invMatrixOutputs
connect io_decode_1_fp_csr_plaInput, addr_1
node _io_decode_1_fp_csr_T = bits(io_decode_1_fp_csr_plaOutput, 0, 0)
connect io.decode[1].fp_csr, _io_decode_1_fp_csr_T
wire io_decode_1_vector_csr_plaInput : UInt<12>
node io_decode_1_vector_csr_invInputs = not(io_decode_1_vector_csr_plaInput)
wire io_decode_1_vector_csr_plaOutput : UInt<1>
connect io_decode_1_vector_csr_plaOutput, UInt<1>(0h0)
connect io_decode_1_vector_csr_plaInput, addr_1
node _io_decode_1_vector_csr_T = bits(io_decode_1_vector_csr_plaOutput, 0, 0)
connect io.decode[1].vector_csr, _io_decode_1_vector_csr_T
node _io_decode_1_rocc_illegal_T = eq(io.status.xs, UInt<1>(0h0))
node _io_decode_1_rocc_illegal_T_1 = eq(reg_vsstatus.xs, UInt<1>(0h0))
node _io_decode_1_rocc_illegal_T_2 = and(reg_mstatus.v, _io_decode_1_rocc_illegal_T_1)
node _io_decode_1_rocc_illegal_T_3 = or(_io_decode_1_rocc_illegal_T, _io_decode_1_rocc_illegal_T_2)
node _io_decode_1_rocc_illegal_T_4 = bits(reg_misa, 23, 23)
node _io_decode_1_rocc_illegal_T_5 = eq(_io_decode_1_rocc_illegal_T_4, UInt<1>(0h0))
node _io_decode_1_rocc_illegal_T_6 = or(_io_decode_1_rocc_illegal_T_3, _io_decode_1_rocc_illegal_T_5)
connect io.decode[1].rocc_illegal, _io_decode_1_rocc_illegal_T_6
node _csr_addr_legal_T_9 = bits(addr_1, 9, 8)
node _csr_addr_legal_T_10 = geq(reg_mstatus.prv, _csr_addr_legal_T_9)
node _csr_addr_legal_T_11 = eq(reg_mstatus.v, UInt<1>(0h0))
node _csr_addr_legal_T_12 = and(UInt<1>(0h0), _csr_addr_legal_T_11)
node _csr_addr_legal_T_13 = eq(reg_mstatus.prv, UInt<1>(0h1))
node _csr_addr_legal_T_14 = and(_csr_addr_legal_T_12, _csr_addr_legal_T_13)
node _csr_addr_legal_T_15 = bits(addr_1, 9, 8)
node _csr_addr_legal_T_16 = eq(_csr_addr_legal_T_15, UInt<2>(0h2))
node _csr_addr_legal_T_17 = and(_csr_addr_legal_T_14, _csr_addr_legal_T_16)
node csr_addr_legal_1 = or(_csr_addr_legal_T_10, _csr_addr_legal_T_17)
node _csr_exists_T_302 = eq(addr_1, UInt<11>(0h7a0))
node _csr_exists_T_303 = eq(addr_1, UInt<11>(0h7a1))
node _csr_exists_T_304 = eq(addr_1, UInt<11>(0h7a2))
node _csr_exists_T_305 = eq(addr_1, UInt<11>(0h7a3))
node _csr_exists_T_306 = eq(addr_1, UInt<10>(0h301))
node _csr_exists_T_307 = eq(addr_1, UInt<10>(0h300))
node _csr_exists_T_308 = eq(addr_1, UInt<10>(0h305))
node _csr_exists_T_309 = eq(addr_1, UInt<10>(0h344))
node _csr_exists_T_310 = eq(addr_1, UInt<10>(0h304))
node _csr_exists_T_311 = eq(addr_1, UInt<10>(0h340))
node _csr_exists_T_312 = eq(addr_1, UInt<10>(0h341))
node _csr_exists_T_313 = eq(addr_1, UInt<10>(0h343))
node _csr_exists_T_314 = eq(addr_1, UInt<10>(0h342))
node _csr_exists_T_315 = eq(addr_1, UInt<12>(0hf14))
node _csr_exists_T_316 = eq(addr_1, UInt<11>(0h7b0))
node _csr_exists_T_317 = eq(addr_1, UInt<11>(0h7b1))
node _csr_exists_T_318 = eq(addr_1, UInt<11>(0h7b2))
node _csr_exists_T_319 = eq(addr_1, UInt<1>(0h1))
node _csr_exists_T_320 = eq(addr_1, UInt<2>(0h2))
node _csr_exists_T_321 = eq(addr_1, UInt<2>(0h3))
node _csr_exists_T_322 = eq(addr_1, UInt<10>(0h320))
node _csr_exists_T_323 = eq(addr_1, UInt<12>(0hb00))
node _csr_exists_T_324 = eq(addr_1, UInt<12>(0hb02))
node _csr_exists_T_325 = eq(addr_1, UInt<10>(0h323))
node _csr_exists_T_326 = eq(addr_1, UInt<12>(0hb03))
node _csr_exists_T_327 = eq(addr_1, UInt<12>(0hc03))
node _csr_exists_T_328 = eq(addr_1, UInt<10>(0h324))
node _csr_exists_T_329 = eq(addr_1, UInt<12>(0hb04))
node _csr_exists_T_330 = eq(addr_1, UInt<12>(0hc04))
node _csr_exists_T_331 = eq(addr_1, UInt<10>(0h325))
node _csr_exists_T_332 = eq(addr_1, UInt<12>(0hb05))
node _csr_exists_T_333 = eq(addr_1, UInt<12>(0hc05))
node _csr_exists_T_334 = eq(addr_1, UInt<10>(0h326))
node _csr_exists_T_335 = eq(addr_1, UInt<12>(0hb06))
node _csr_exists_T_336 = eq(addr_1, UInt<12>(0hc06))
node _csr_exists_T_337 = eq(addr_1, UInt<10>(0h327))
node _csr_exists_T_338 = eq(addr_1, UInt<12>(0hb07))
node _csr_exists_T_339 = eq(addr_1, UInt<12>(0hc07))
node _csr_exists_T_340 = eq(addr_1, UInt<10>(0h328))
node _csr_exists_T_341 = eq(addr_1, UInt<12>(0hb08))
node _csr_exists_T_342 = eq(addr_1, UInt<12>(0hc08))
node _csr_exists_T_343 = eq(addr_1, UInt<10>(0h329))
node _csr_exists_T_344 = eq(addr_1, UInt<12>(0hb09))
node _csr_exists_T_345 = eq(addr_1, UInt<12>(0hc09))
node _csr_exists_T_346 = eq(addr_1, UInt<10>(0h32a))
node _csr_exists_T_347 = eq(addr_1, UInt<12>(0hb0a))
node _csr_exists_T_348 = eq(addr_1, UInt<12>(0hc0a))
node _csr_exists_T_349 = eq(addr_1, UInt<10>(0h32b))
node _csr_exists_T_350 = eq(addr_1, UInt<12>(0hb0b))
node _csr_exists_T_351 = eq(addr_1, UInt<12>(0hc0b))
node _csr_exists_T_352 = eq(addr_1, UInt<10>(0h32c))
node _csr_exists_T_353 = eq(addr_1, UInt<12>(0hb0c))
node _csr_exists_T_354 = eq(addr_1, UInt<12>(0hc0c))
node _csr_exists_T_355 = eq(addr_1, UInt<10>(0h32d))
node _csr_exists_T_356 = eq(addr_1, UInt<12>(0hb0d))
node _csr_exists_T_357 = eq(addr_1, UInt<12>(0hc0d))
node _csr_exists_T_358 = eq(addr_1, UInt<10>(0h32e))
node _csr_exists_T_359 = eq(addr_1, UInt<12>(0hb0e))
node _csr_exists_T_360 = eq(addr_1, UInt<12>(0hc0e))
node _csr_exists_T_361 = eq(addr_1, UInt<10>(0h32f))
node _csr_exists_T_362 = eq(addr_1, UInt<12>(0hb0f))
node _csr_exists_T_363 = eq(addr_1, UInt<12>(0hc0f))
node _csr_exists_T_364 = eq(addr_1, UInt<10>(0h330))
node _csr_exists_T_365 = eq(addr_1, UInt<12>(0hb10))
node _csr_exists_T_366 = eq(addr_1, UInt<12>(0hc10))
node _csr_exists_T_367 = eq(addr_1, UInt<10>(0h331))
node _csr_exists_T_368 = eq(addr_1, UInt<12>(0hb11))
node _csr_exists_T_369 = eq(addr_1, UInt<12>(0hc11))
node _csr_exists_T_370 = eq(addr_1, UInt<10>(0h332))
node _csr_exists_T_371 = eq(addr_1, UInt<12>(0hb12))
node _csr_exists_T_372 = eq(addr_1, UInt<12>(0hc12))
node _csr_exists_T_373 = eq(addr_1, UInt<10>(0h333))
node _csr_exists_T_374 = eq(addr_1, UInt<12>(0hb13))
node _csr_exists_T_375 = eq(addr_1, UInt<12>(0hc13))
node _csr_exists_T_376 = eq(addr_1, UInt<10>(0h334))
node _csr_exists_T_377 = eq(addr_1, UInt<12>(0hb14))
node _csr_exists_T_378 = eq(addr_1, UInt<12>(0hc14))
node _csr_exists_T_379 = eq(addr_1, UInt<10>(0h335))
node _csr_exists_T_380 = eq(addr_1, UInt<12>(0hb15))
node _csr_exists_T_381 = eq(addr_1, UInt<12>(0hc15))
node _csr_exists_T_382 = eq(addr_1, UInt<10>(0h336))
node _csr_exists_T_383 = eq(addr_1, UInt<12>(0hb16))
node _csr_exists_T_384 = eq(addr_1, UInt<12>(0hc16))
node _csr_exists_T_385 = eq(addr_1, UInt<10>(0h337))
node _csr_exists_T_386 = eq(addr_1, UInt<12>(0hb17))
node _csr_exists_T_387 = eq(addr_1, UInt<12>(0hc17))
node _csr_exists_T_388 = eq(addr_1, UInt<10>(0h338))
node _csr_exists_T_389 = eq(addr_1, UInt<12>(0hb18))
node _csr_exists_T_390 = eq(addr_1, UInt<12>(0hc18))
node _csr_exists_T_391 = eq(addr_1, UInt<10>(0h339))
node _csr_exists_T_392 = eq(addr_1, UInt<12>(0hb19))
node _csr_exists_T_393 = eq(addr_1, UInt<12>(0hc19))
node _csr_exists_T_394 = eq(addr_1, UInt<10>(0h33a))
node _csr_exists_T_395 = eq(addr_1, UInt<12>(0hb1a))
node _csr_exists_T_396 = eq(addr_1, UInt<12>(0hc1a))
node _csr_exists_T_397 = eq(addr_1, UInt<10>(0h33b))
node _csr_exists_T_398 = eq(addr_1, UInt<12>(0hb1b))
node _csr_exists_T_399 = eq(addr_1, UInt<12>(0hc1b))
node _csr_exists_T_400 = eq(addr_1, UInt<10>(0h33c))
node _csr_exists_T_401 = eq(addr_1, UInt<12>(0hb1c))
node _csr_exists_T_402 = eq(addr_1, UInt<12>(0hc1c))
node _csr_exists_T_403 = eq(addr_1, UInt<10>(0h33d))
node _csr_exists_T_404 = eq(addr_1, UInt<12>(0hb1d))
node _csr_exists_T_405 = eq(addr_1, UInt<12>(0hc1d))
node _csr_exists_T_406 = eq(addr_1, UInt<10>(0h33e))
node _csr_exists_T_407 = eq(addr_1, UInt<12>(0hb1e))
node _csr_exists_T_408 = eq(addr_1, UInt<12>(0hc1e))
node _csr_exists_T_409 = eq(addr_1, UInt<10>(0h33f))
node _csr_exists_T_410 = eq(addr_1, UInt<12>(0hb1f))
node _csr_exists_T_411 = eq(addr_1, UInt<12>(0hc1f))
node _csr_exists_T_412 = eq(addr_1, UInt<10>(0h306))
node _csr_exists_T_413 = eq(addr_1, UInt<12>(0hc00))
node _csr_exists_T_414 = eq(addr_1, UInt<12>(0hc02))
node _csr_exists_T_415 = eq(addr_1, UInt<10>(0h30a))
node _csr_exists_T_416 = eq(addr_1, UInt<9>(0h100))
node _csr_exists_T_417 = eq(addr_1, UInt<9>(0h144))
node _csr_exists_T_418 = eq(addr_1, UInt<9>(0h104))
node _csr_exists_T_419 = eq(addr_1, UInt<9>(0h140))
node _csr_exists_T_420 = eq(addr_1, UInt<9>(0h142))
node _csr_exists_T_421 = eq(addr_1, UInt<9>(0h143))
node _csr_exists_T_422 = eq(addr_1, UInt<9>(0h180))
node _csr_exists_T_423 = eq(addr_1, UInt<9>(0h141))
node _csr_exists_T_424 = eq(addr_1, UInt<9>(0h105))
node _csr_exists_T_425 = eq(addr_1, UInt<9>(0h106))
node _csr_exists_T_426 = eq(addr_1, UInt<10>(0h303))
node _csr_exists_T_427 = eq(addr_1, UInt<10>(0h302))
node _csr_exists_T_428 = eq(addr_1, UInt<9>(0h10a))
node _csr_exists_T_429 = eq(addr_1, UInt<10>(0h3a0))
node _csr_exists_T_430 = eq(addr_1, UInt<10>(0h3a2))
node _csr_exists_T_431 = eq(addr_1, UInt<10>(0h3b0))
node _csr_exists_T_432 = eq(addr_1, UInt<10>(0h3b1))
node _csr_exists_T_433 = eq(addr_1, UInt<10>(0h3b2))
node _csr_exists_T_434 = eq(addr_1, UInt<10>(0h3b3))
node _csr_exists_T_435 = eq(addr_1, UInt<10>(0h3b4))
node _csr_exists_T_436 = eq(addr_1, UInt<10>(0h3b5))
node _csr_exists_T_437 = eq(addr_1, UInt<10>(0h3b6))
node _csr_exists_T_438 = eq(addr_1, UInt<10>(0h3b7))
node _csr_exists_T_439 = eq(addr_1, UInt<10>(0h3b8))
node _csr_exists_T_440 = eq(addr_1, UInt<10>(0h3b9))
node _csr_exists_T_441 = eq(addr_1, UInt<10>(0h3ba))
node _csr_exists_T_442 = eq(addr_1, UInt<10>(0h3bb))
node _csr_exists_T_443 = eq(addr_1, UInt<10>(0h3bc))
node _csr_exists_T_444 = eq(addr_1, UInt<10>(0h3bd))
node _csr_exists_T_445 = eq(addr_1, UInt<10>(0h3be))
node _csr_exists_T_446 = eq(addr_1, UInt<10>(0h3bf))
node _csr_exists_T_447 = eq(addr_1, UInt<12>(0h800))
node _csr_exists_T_448 = eq(addr_1, UInt<12>(0h808))
node _csr_exists_T_449 = eq(addr_1, UInt<11>(0h7c1))
node _csr_exists_T_450 = eq(addr_1, UInt<12>(0hf12))
node _csr_exists_T_451 = eq(addr_1, UInt<12>(0hf13))
node _csr_exists_T_452 = eq(addr_1, UInt<12>(0hf11))
node _csr_exists_T_453 = eq(addr_1, UInt<12>(0hf15))
node _csr_exists_T_454 = or(_csr_exists_T_302, _csr_exists_T_303)
node _csr_exists_T_455 = or(_csr_exists_T_454, _csr_exists_T_304)
node _csr_exists_T_456 = or(_csr_exists_T_455, _csr_exists_T_305)
node _csr_exists_T_457 = or(_csr_exists_T_456, _csr_exists_T_306)
node _csr_exists_T_458 = or(_csr_exists_T_457, _csr_exists_T_307)
node _csr_exists_T_459 = or(_csr_exists_T_458, _csr_exists_T_308)
node _csr_exists_T_460 = or(_csr_exists_T_459, _csr_exists_T_309)
node _csr_exists_T_461 = or(_csr_exists_T_460, _csr_exists_T_310)
node _csr_exists_T_462 = or(_csr_exists_T_461, _csr_exists_T_311)
node _csr_exists_T_463 = or(_csr_exists_T_462, _csr_exists_T_312)
node _csr_exists_T_464 = or(_csr_exists_T_463, _csr_exists_T_313)
node _csr_exists_T_465 = or(_csr_exists_T_464, _csr_exists_T_314)
node _csr_exists_T_466 = or(_csr_exists_T_465, _csr_exists_T_315)
node _csr_exists_T_467 = or(_csr_exists_T_466, _csr_exists_T_316)
node _csr_exists_T_468 = or(_csr_exists_T_467, _csr_exists_T_317)
node _csr_exists_T_469 = or(_csr_exists_T_468, _csr_exists_T_318)
node _csr_exists_T_470 = or(_csr_exists_T_469, _csr_exists_T_319)
node _csr_exists_T_471 = or(_csr_exists_T_470, _csr_exists_T_320)
node _csr_exists_T_472 = or(_csr_exists_T_471, _csr_exists_T_321)
node _csr_exists_T_473 = or(_csr_exists_T_472, _csr_exists_T_322)
node _csr_exists_T_474 = or(_csr_exists_T_473, _csr_exists_T_323)
node _csr_exists_T_475 = or(_csr_exists_T_474, _csr_exists_T_324)
node _csr_exists_T_476 = or(_csr_exists_T_475, _csr_exists_T_325)
node _csr_exists_T_477 = or(_csr_exists_T_476, _csr_exists_T_326)
node _csr_exists_T_478 = or(_csr_exists_T_477, _csr_exists_T_327)
node _csr_exists_T_479 = or(_csr_exists_T_478, _csr_exists_T_328)
node _csr_exists_T_480 = or(_csr_exists_T_479, _csr_exists_T_329)
node _csr_exists_T_481 = or(_csr_exists_T_480, _csr_exists_T_330)
node _csr_exists_T_482 = or(_csr_exists_T_481, _csr_exists_T_331)
node _csr_exists_T_483 = or(_csr_exists_T_482, _csr_exists_T_332)
node _csr_exists_T_484 = or(_csr_exists_T_483, _csr_exists_T_333)
node _csr_exists_T_485 = or(_csr_exists_T_484, _csr_exists_T_334)
node _csr_exists_T_486 = or(_csr_exists_T_485, _csr_exists_T_335)
node _csr_exists_T_487 = or(_csr_exists_T_486, _csr_exists_T_336)
node _csr_exists_T_488 = or(_csr_exists_T_487, _csr_exists_T_337)
node _csr_exists_T_489 = or(_csr_exists_T_488, _csr_exists_T_338)
node _csr_exists_T_490 = or(_csr_exists_T_489, _csr_exists_T_339)
node _csr_exists_T_491 = or(_csr_exists_T_490, _csr_exists_T_340)
node _csr_exists_T_492 = or(_csr_exists_T_491, _csr_exists_T_341)
node _csr_exists_T_493 = or(_csr_exists_T_492, _csr_exists_T_342)
node _csr_exists_T_494 = or(_csr_exists_T_493, _csr_exists_T_343)
node _csr_exists_T_495 = or(_csr_exists_T_494, _csr_exists_T_344)
node _csr_exists_T_496 = or(_csr_exists_T_495, _csr_exists_T_345)
node _csr_exists_T_497 = or(_csr_exists_T_496, _csr_exists_T_346)
node _csr_exists_T_498 = or(_csr_exists_T_497, _csr_exists_T_347)
node _csr_exists_T_499 = or(_csr_exists_T_498, _csr_exists_T_348)
node _csr_exists_T_500 = or(_csr_exists_T_499, _csr_exists_T_349)
node _csr_exists_T_501 = or(_csr_exists_T_500, _csr_exists_T_350)
node _csr_exists_T_502 = or(_csr_exists_T_501, _csr_exists_T_351)
node _csr_exists_T_503 = or(_csr_exists_T_502, _csr_exists_T_352)
node _csr_exists_T_504 = or(_csr_exists_T_503, _csr_exists_T_353)
node _csr_exists_T_505 = or(_csr_exists_T_504, _csr_exists_T_354)
node _csr_exists_T_506 = or(_csr_exists_T_505, _csr_exists_T_355)
node _csr_exists_T_507 = or(_csr_exists_T_506, _csr_exists_T_356)
node _csr_exists_T_508 = or(_csr_exists_T_507, _csr_exists_T_357)
node _csr_exists_T_509 = or(_csr_exists_T_508, _csr_exists_T_358)
node _csr_exists_T_510 = or(_csr_exists_T_509, _csr_exists_T_359)
node _csr_exists_T_511 = or(_csr_exists_T_510, _csr_exists_T_360)
node _csr_exists_T_512 = or(_csr_exists_T_511, _csr_exists_T_361)
node _csr_exists_T_513 = or(_csr_exists_T_512, _csr_exists_T_362)
node _csr_exists_T_514 = or(_csr_exists_T_513, _csr_exists_T_363)
node _csr_exists_T_515 = or(_csr_exists_T_514, _csr_exists_T_364)
node _csr_exists_T_516 = or(_csr_exists_T_515, _csr_exists_T_365)
node _csr_exists_T_517 = or(_csr_exists_T_516, _csr_exists_T_366)
node _csr_exists_T_518 = or(_csr_exists_T_517, _csr_exists_T_367)
node _csr_exists_T_519 = or(_csr_exists_T_518, _csr_exists_T_368)
node _csr_exists_T_520 = or(_csr_exists_T_519, _csr_exists_T_369)
node _csr_exists_T_521 = or(_csr_exists_T_520, _csr_exists_T_370)
node _csr_exists_T_522 = or(_csr_exists_T_521, _csr_exists_T_371)
node _csr_exists_T_523 = or(_csr_exists_T_522, _csr_exists_T_372)
node _csr_exists_T_524 = or(_csr_exists_T_523, _csr_exists_T_373)
node _csr_exists_T_525 = or(_csr_exists_T_524, _csr_exists_T_374)
node _csr_exists_T_526 = or(_csr_exists_T_525, _csr_exists_T_375)
node _csr_exists_T_527 = or(_csr_exists_T_526, _csr_exists_T_376)
node _csr_exists_T_528 = or(_csr_exists_T_527, _csr_exists_T_377)
node _csr_exists_T_529 = or(_csr_exists_T_528, _csr_exists_T_378)
node _csr_exists_T_530 = or(_csr_exists_T_529, _csr_exists_T_379)
node _csr_exists_T_531 = or(_csr_exists_T_530, _csr_exists_T_380)
node _csr_exists_T_532 = or(_csr_exists_T_531, _csr_exists_T_381)
node _csr_exists_T_533 = or(_csr_exists_T_532, _csr_exists_T_382)
node _csr_exists_T_534 = or(_csr_exists_T_533, _csr_exists_T_383)
node _csr_exists_T_535 = or(_csr_exists_T_534, _csr_exists_T_384)
node _csr_exists_T_536 = or(_csr_exists_T_535, _csr_exists_T_385)
node _csr_exists_T_537 = or(_csr_exists_T_536, _csr_exists_T_386)
node _csr_exists_T_538 = or(_csr_exists_T_537, _csr_exists_T_387)
node _csr_exists_T_539 = or(_csr_exists_T_538, _csr_exists_T_388)
node _csr_exists_T_540 = or(_csr_exists_T_539, _csr_exists_T_389)
node _csr_exists_T_541 = or(_csr_exists_T_540, _csr_exists_T_390)
node _csr_exists_T_542 = or(_csr_exists_T_541, _csr_exists_T_391)
node _csr_exists_T_543 = or(_csr_exists_T_542, _csr_exists_T_392)
node _csr_exists_T_544 = or(_csr_exists_T_543, _csr_exists_T_393)
node _csr_exists_T_545 = or(_csr_exists_T_544, _csr_exists_T_394)
node _csr_exists_T_546 = or(_csr_exists_T_545, _csr_exists_T_395)
node _csr_exists_T_547 = or(_csr_exists_T_546, _csr_exists_T_396)
node _csr_exists_T_548 = or(_csr_exists_T_547, _csr_exists_T_397)
node _csr_exists_T_549 = or(_csr_exists_T_548, _csr_exists_T_398)
node _csr_exists_T_550 = or(_csr_exists_T_549, _csr_exists_T_399)
node _csr_exists_T_551 = or(_csr_exists_T_550, _csr_exists_T_400)
node _csr_exists_T_552 = or(_csr_exists_T_551, _csr_exists_T_401)
node _csr_exists_T_553 = or(_csr_exists_T_552, _csr_exists_T_402)
node _csr_exists_T_554 = or(_csr_exists_T_553, _csr_exists_T_403)
node _csr_exists_T_555 = or(_csr_exists_T_554, _csr_exists_T_404)
node _csr_exists_T_556 = or(_csr_exists_T_555, _csr_exists_T_405)
node _csr_exists_T_557 = or(_csr_exists_T_556, _csr_exists_T_406)
node _csr_exists_T_558 = or(_csr_exists_T_557, _csr_exists_T_407)
node _csr_exists_T_559 = or(_csr_exists_T_558, _csr_exists_T_408)
node _csr_exists_T_560 = or(_csr_exists_T_559, _csr_exists_T_409)
node _csr_exists_T_561 = or(_csr_exists_T_560, _csr_exists_T_410)
node _csr_exists_T_562 = or(_csr_exists_T_561, _csr_exists_T_411)
node _csr_exists_T_563 = or(_csr_exists_T_562, _csr_exists_T_412)
node _csr_exists_T_564 = or(_csr_exists_T_563, _csr_exists_T_413)
node _csr_exists_T_565 = or(_csr_exists_T_564, _csr_exists_T_414)
node _csr_exists_T_566 = or(_csr_exists_T_565, _csr_exists_T_415)
node _csr_exists_T_567 = or(_csr_exists_T_566, _csr_exists_T_416)
node _csr_exists_T_568 = or(_csr_exists_T_567, _csr_exists_T_417)
node _csr_exists_T_569 = or(_csr_exists_T_568, _csr_exists_T_418)
node _csr_exists_T_570 = or(_csr_exists_T_569, _csr_exists_T_419)
node _csr_exists_T_571 = or(_csr_exists_T_570, _csr_exists_T_420)
node _csr_exists_T_572 = or(_csr_exists_T_571, _csr_exists_T_421)
node _csr_exists_T_573 = or(_csr_exists_T_572, _csr_exists_T_422)
node _csr_exists_T_574 = or(_csr_exists_T_573, _csr_exists_T_423)
node _csr_exists_T_575 = or(_csr_exists_T_574, _csr_exists_T_424)
node _csr_exists_T_576 = or(_csr_exists_T_575, _csr_exists_T_425)
node _csr_exists_T_577 = or(_csr_exists_T_576, _csr_exists_T_426)
node _csr_exists_T_578 = or(_csr_exists_T_577, _csr_exists_T_427)
node _csr_exists_T_579 = or(_csr_exists_T_578, _csr_exists_T_428)
node _csr_exists_T_580 = or(_csr_exists_T_579, _csr_exists_T_429)
node _csr_exists_T_581 = or(_csr_exists_T_580, _csr_exists_T_430)
node _csr_exists_T_582 = or(_csr_exists_T_581, _csr_exists_T_431)
node _csr_exists_T_583 = or(_csr_exists_T_582, _csr_exists_T_432)
node _csr_exists_T_584 = or(_csr_exists_T_583, _csr_exists_T_433)
node _csr_exists_T_585 = or(_csr_exists_T_584, _csr_exists_T_434)
node _csr_exists_T_586 = or(_csr_exists_T_585, _csr_exists_T_435)
node _csr_exists_T_587 = or(_csr_exists_T_586, _csr_exists_T_436)
node _csr_exists_T_588 = or(_csr_exists_T_587, _csr_exists_T_437)
node _csr_exists_T_589 = or(_csr_exists_T_588, _csr_exists_T_438)
node _csr_exists_T_590 = or(_csr_exists_T_589, _csr_exists_T_439)
node _csr_exists_T_591 = or(_csr_exists_T_590, _csr_exists_T_440)
node _csr_exists_T_592 = or(_csr_exists_T_591, _csr_exists_T_441)
node _csr_exists_T_593 = or(_csr_exists_T_592, _csr_exists_T_442)
node _csr_exists_T_594 = or(_csr_exists_T_593, _csr_exists_T_443)
node _csr_exists_T_595 = or(_csr_exists_T_594, _csr_exists_T_444)
node _csr_exists_T_596 = or(_csr_exists_T_595, _csr_exists_T_445)
node _csr_exists_T_597 = or(_csr_exists_T_596, _csr_exists_T_446)
node _csr_exists_T_598 = or(_csr_exists_T_597, _csr_exists_T_447)
node _csr_exists_T_599 = or(_csr_exists_T_598, _csr_exists_T_448)
node _csr_exists_T_600 = or(_csr_exists_T_599, _csr_exists_T_449)
node _csr_exists_T_601 = or(_csr_exists_T_600, _csr_exists_T_450)
node _csr_exists_T_602 = or(_csr_exists_T_601, _csr_exists_T_451)
node _csr_exists_T_603 = or(_csr_exists_T_602, _csr_exists_T_452)
node csr_exists_1 = or(_csr_exists_T_603, _csr_exists_T_453)
node _io_decode_1_read_illegal_T = eq(csr_addr_legal_1, UInt<1>(0h0))
node _io_decode_1_read_illegal_T_1 = eq(csr_exists_1, UInt<1>(0h0))
node _io_decode_1_read_illegal_T_2 = or(_io_decode_1_read_illegal_T, _io_decode_1_read_illegal_T_1)
node _io_decode_1_read_illegal_T_3 = eq(addr_1, UInt<9>(0h180))
node _io_decode_1_read_illegal_T_4 = eq(addr_1, UInt<11>(0h680))
node _io_decode_1_read_illegal_T_5 = or(_io_decode_1_read_illegal_T_3, _io_decode_1_read_illegal_T_4)
node _io_decode_1_read_illegal_T_6 = eq(allow_sfence_vma_1, UInt<1>(0h0))
node _io_decode_1_read_illegal_T_7 = and(_io_decode_1_read_illegal_T_5, _io_decode_1_read_illegal_T_6)
node _io_decode_1_read_illegal_T_8 = or(_io_decode_1_read_illegal_T_2, _io_decode_1_read_illegal_T_7)
node _io_decode_1_read_illegal_T_9 = eq(allow_counter_1, UInt<1>(0h0))
node _io_decode_1_read_illegal_T_10 = and(is_counter_1, _io_decode_1_read_illegal_T_9)
node _io_decode_1_read_illegal_T_11 = or(_io_decode_1_read_illegal_T_8, _io_decode_1_read_illegal_T_10)
wire io_decode_1_read_illegal_plaInput : UInt<12>
node io_decode_1_read_illegal_invInputs = not(io_decode_1_read_illegal_plaInput)
wire io_decode_1_read_illegal_plaOutput : UInt<1>
node io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_0 = bits(io_decode_1_read_illegal_plaInput, 4, 4)
node io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_1 = bits(io_decode_1_read_illegal_plaInput, 5, 5)
node io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_2 = bits(io_decode_1_read_illegal_invInputs, 6, 6)
node io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_3 = bits(io_decode_1_read_illegal_plaInput, 7, 7)
node io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_4 = bits(io_decode_1_read_illegal_plaInput, 8, 8)
node io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_5 = bits(io_decode_1_read_illegal_plaInput, 9, 9)
node io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_6 = bits(io_decode_1_read_illegal_plaInput, 10, 10)
node io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_7 = bits(io_decode_1_read_illegal_invInputs, 11, 11)
node io_decode_1_read_illegal_andMatrixOutputs_lo_lo = cat(io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_6, io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_7)
node io_decode_1_read_illegal_andMatrixOutputs_lo_hi = cat(io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_4, io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_5)
node io_decode_1_read_illegal_andMatrixOutputs_lo = cat(io_decode_1_read_illegal_andMatrixOutputs_lo_hi, io_decode_1_read_illegal_andMatrixOutputs_lo_lo)
node io_decode_1_read_illegal_andMatrixOutputs_hi_lo = cat(io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_2, io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_3)
node io_decode_1_read_illegal_andMatrixOutputs_hi_hi = cat(io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_0, io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_1)
node io_decode_1_read_illegal_andMatrixOutputs_hi = cat(io_decode_1_read_illegal_andMatrixOutputs_hi_hi, io_decode_1_read_illegal_andMatrixOutputs_hi_lo)
node _io_decode_1_read_illegal_andMatrixOutputs_T = cat(io_decode_1_read_illegal_andMatrixOutputs_hi, io_decode_1_read_illegal_andMatrixOutputs_lo)
node io_decode_1_read_illegal_andMatrixOutputs_0_2 = andr(_io_decode_1_read_illegal_andMatrixOutputs_T)
node io_decode_1_read_illegal_orMatrixOutputs = orr(io_decode_1_read_illegal_andMatrixOutputs_0_2)
node io_decode_1_read_illegal_invMatrixOutputs = bits(io_decode_1_read_illegal_orMatrixOutputs, 0, 0)
connect io_decode_1_read_illegal_plaOutput, io_decode_1_read_illegal_invMatrixOutputs
connect io_decode_1_read_illegal_plaInput, addr_1
node _io_decode_1_read_illegal_T_12 = bits(io_decode_1_read_illegal_plaOutput, 0, 0)
node _io_decode_1_read_illegal_T_13 = eq(reg_debug, UInt<1>(0h0))
node _io_decode_1_read_illegal_T_14 = and(_io_decode_1_read_illegal_T_12, _io_decode_1_read_illegal_T_13)
node _io_decode_1_read_illegal_T_15 = or(_io_decode_1_read_illegal_T_11, _io_decode_1_read_illegal_T_14)
wire io_decode_1_read_illegal_plaInput_1 : UInt<12>
node io_decode_1_read_illegal_invInputs_1 = not(io_decode_1_read_illegal_plaInput_1)
wire io_decode_1_read_illegal_plaOutput_1 : UInt<1>
connect io_decode_1_read_illegal_plaOutput_1, UInt<1>(0h0)
connect io_decode_1_read_illegal_plaInput_1, addr_1
node _io_decode_1_read_illegal_T_16 = bits(io_decode_1_read_illegal_plaOutput_1, 0, 0)
node _io_decode_1_read_illegal_T_17 = and(_io_decode_1_read_illegal_T_16, io.decode[1].vector_illegal)
node _io_decode_1_read_illegal_T_18 = or(_io_decode_1_read_illegal_T_15, _io_decode_1_read_illegal_T_17)
node _io_decode_1_read_illegal_T_19 = and(io.decode[1].fp_csr, io.decode[1].fp_illegal)
node _io_decode_1_read_illegal_T_20 = or(_io_decode_1_read_illegal_T_18, _io_decode_1_read_illegal_T_19)
connect io.decode[1].read_illegal, _io_decode_1_read_illegal_T_20
node _io_decode_1_write_illegal_T = bits(addr_1, 11, 10)
node _io_decode_1_write_illegal_T_1 = andr(_io_decode_1_write_illegal_T)
connect io.decode[1].write_illegal, _io_decode_1_write_illegal_T_1
node _io_decode_1_write_flush_addr_m_T = shl(UInt<2>(0h3), 8)
node io_decode_1_write_flush_addr_m = or(addr_1, _io_decode_1_write_flush_addr_m_T)
node _io_decode_1_write_flush_T = geq(io_decode_1_write_flush_addr_m, UInt<10>(0h340))
node _io_decode_1_write_flush_T_1 = leq(io_decode_1_write_flush_addr_m, UInt<10>(0h343))
node _io_decode_1_write_flush_T_2 = and(_io_decode_1_write_flush_T, _io_decode_1_write_flush_T_1)
node _io_decode_1_write_flush_T_3 = eq(_io_decode_1_write_flush_T_2, UInt<1>(0h0))
connect io.decode[1].write_flush, _io_decode_1_write_flush_T_3
node _io_decode_1_system_illegal_T = eq(csr_addr_legal_1, UInt<1>(0h0))
node _io_decode_1_system_illegal_T_1 = eq(is_hlsv_1, UInt<1>(0h0))
node _io_decode_1_system_illegal_T_2 = and(_io_decode_1_system_illegal_T, _io_decode_1_system_illegal_T_1)
node _io_decode_1_system_illegal_T_3 = eq(allow_wfi_1, UInt<1>(0h0))
node _io_decode_1_system_illegal_T_4 = and(is_wfi_1, _io_decode_1_system_illegal_T_3)
node _io_decode_1_system_illegal_T_5 = or(_io_decode_1_system_illegal_T_2, _io_decode_1_system_illegal_T_4)
node _io_decode_1_system_illegal_T_6 = eq(allow_sret_1, UInt<1>(0h0))
node _io_decode_1_system_illegal_T_7 = and(is_ret_1, _io_decode_1_system_illegal_T_6)
node _io_decode_1_system_illegal_T_8 = or(_io_decode_1_system_illegal_T_5, _io_decode_1_system_illegal_T_7)
node _io_decode_1_system_illegal_T_9 = bits(addr_1, 10, 10)
node _io_decode_1_system_illegal_T_10 = and(is_ret_1, _io_decode_1_system_illegal_T_9)
node _io_decode_1_system_illegal_T_11 = bits(addr_1, 7, 7)
node _io_decode_1_system_illegal_T_12 = and(_io_decode_1_system_illegal_T_10, _io_decode_1_system_illegal_T_11)
node _io_decode_1_system_illegal_T_13 = eq(reg_debug, UInt<1>(0h0))
node _io_decode_1_system_illegal_T_14 = and(_io_decode_1_system_illegal_T_12, _io_decode_1_system_illegal_T_13)
node _io_decode_1_system_illegal_T_15 = or(_io_decode_1_system_illegal_T_8, _io_decode_1_system_illegal_T_14)
node _io_decode_1_system_illegal_T_16 = or(is_sfence_1, is_hfence_gvma_1)
node _io_decode_1_system_illegal_T_17 = eq(allow_sfence_vma_1, UInt<1>(0h0))
node _io_decode_1_system_illegal_T_18 = and(_io_decode_1_system_illegal_T_16, _io_decode_1_system_illegal_T_17)
node _io_decode_1_system_illegal_T_19 = or(_io_decode_1_system_illegal_T_15, _io_decode_1_system_illegal_T_18)
node _io_decode_1_system_illegal_T_20 = eq(allow_hfence_vvma_1, UInt<1>(0h0))
node _io_decode_1_system_illegal_T_21 = and(is_hfence_vvma_1, _io_decode_1_system_illegal_T_20)
node _io_decode_1_system_illegal_T_22 = or(_io_decode_1_system_illegal_T_19, _io_decode_1_system_illegal_T_21)
node _io_decode_1_system_illegal_T_23 = eq(allow_hlsv_1, UInt<1>(0h0))
node _io_decode_1_system_illegal_T_24 = and(is_hlsv_1, _io_decode_1_system_illegal_T_23)
node _io_decode_1_system_illegal_T_25 = or(_io_decode_1_system_illegal_T_22, _io_decode_1_system_illegal_T_24)
connect io.decode[1].system_illegal, _io_decode_1_system_illegal_T_25
node _io_decode_1_virtual_access_illegal_T = and(reg_mstatus.v, csr_exists_1)
node _io_decode_1_virtual_access_illegal_T_1 = bits(addr_1, 9, 8)
node _io_decode_1_virtual_access_illegal_T_2 = eq(_io_decode_1_virtual_access_illegal_T_1, UInt<2>(0h2))
node _io_decode_1_virtual_access_illegal_T_3 = dshr(read_mcounteren, counter_addr_1)
node _io_decode_1_virtual_access_illegal_T_4 = bits(_io_decode_1_virtual_access_illegal_T_3, 0, 0)
node _io_decode_1_virtual_access_illegal_T_5 = and(is_counter_1, _io_decode_1_virtual_access_illegal_T_4)
node _io_decode_1_virtual_access_illegal_T_6 = dshr(read_hcounteren, counter_addr_1)
node _io_decode_1_virtual_access_illegal_T_7 = bits(_io_decode_1_virtual_access_illegal_T_6, 0, 0)
node _io_decode_1_virtual_access_illegal_T_8 = eq(_io_decode_1_virtual_access_illegal_T_7, UInt<1>(0h0))
node _io_decode_1_virtual_access_illegal_T_9 = bits(reg_mstatus.prv, 0, 0)
node _io_decode_1_virtual_access_illegal_T_10 = eq(_io_decode_1_virtual_access_illegal_T_9, UInt<1>(0h0))
node _io_decode_1_virtual_access_illegal_T_11 = dshr(read_scounteren, counter_addr_1)
node _io_decode_1_virtual_access_illegal_T_12 = bits(_io_decode_1_virtual_access_illegal_T_11, 0, 0)
node _io_decode_1_virtual_access_illegal_T_13 = eq(_io_decode_1_virtual_access_illegal_T_12, UInt<1>(0h0))
node _io_decode_1_virtual_access_illegal_T_14 = and(_io_decode_1_virtual_access_illegal_T_10, _io_decode_1_virtual_access_illegal_T_13)
node _io_decode_1_virtual_access_illegal_T_15 = or(_io_decode_1_virtual_access_illegal_T_8, _io_decode_1_virtual_access_illegal_T_14)
node _io_decode_1_virtual_access_illegal_T_16 = and(_io_decode_1_virtual_access_illegal_T_5, _io_decode_1_virtual_access_illegal_T_15)
node _io_decode_1_virtual_access_illegal_T_17 = or(_io_decode_1_virtual_access_illegal_T_2, _io_decode_1_virtual_access_illegal_T_16)
node _io_decode_1_virtual_access_illegal_T_18 = bits(addr_1, 9, 8)
node _io_decode_1_virtual_access_illegal_T_19 = eq(_io_decode_1_virtual_access_illegal_T_18, UInt<1>(0h1))
node _io_decode_1_virtual_access_illegal_T_20 = bits(reg_mstatus.prv, 0, 0)
node _io_decode_1_virtual_access_illegal_T_21 = eq(_io_decode_1_virtual_access_illegal_T_20, UInt<1>(0h0))
node _io_decode_1_virtual_access_illegal_T_22 = and(_io_decode_1_virtual_access_illegal_T_19, _io_decode_1_virtual_access_illegal_T_21)
node _io_decode_1_virtual_access_illegal_T_23 = or(_io_decode_1_virtual_access_illegal_T_17, _io_decode_1_virtual_access_illegal_T_22)
node _io_decode_1_virtual_access_illegal_T_24 = eq(addr_1, UInt<9>(0h180))
node _io_decode_1_virtual_access_illegal_T_25 = bits(reg_mstatus.prv, 0, 0)
node _io_decode_1_virtual_access_illegal_T_26 = and(_io_decode_1_virtual_access_illegal_T_24, _io_decode_1_virtual_access_illegal_T_25)
node _io_decode_1_virtual_access_illegal_T_27 = and(_io_decode_1_virtual_access_illegal_T_26, reg_hstatus.vtvm)
node _io_decode_1_virtual_access_illegal_T_28 = or(_io_decode_1_virtual_access_illegal_T_23, _io_decode_1_virtual_access_illegal_T_27)
node _io_decode_1_virtual_access_illegal_T_29 = and(_io_decode_1_virtual_access_illegal_T, _io_decode_1_virtual_access_illegal_T_28)
connect io.decode[1].virtual_access_illegal, _io_decode_1_virtual_access_illegal_T_29
node _io_decode_1_virtual_system_illegal_T = or(is_hfence_vvma_1, is_hfence_gvma_1)
node _io_decode_1_virtual_system_illegal_T_1 = or(_io_decode_1_virtual_system_illegal_T, is_hlsv_1)
node _io_decode_1_virtual_system_illegal_T_2 = bits(reg_mstatus.prv, 0, 0)
node _io_decode_1_virtual_system_illegal_T_3 = eq(_io_decode_1_virtual_system_illegal_T_2, UInt<1>(0h0))
node _io_decode_1_virtual_system_illegal_T_4 = eq(reg_mstatus.tw, UInt<1>(0h0))
node _io_decode_1_virtual_system_illegal_T_5 = and(_io_decode_1_virtual_system_illegal_T_4, reg_hstatus.vtw)
node _io_decode_1_virtual_system_illegal_T_6 = or(_io_decode_1_virtual_system_illegal_T_3, _io_decode_1_virtual_system_illegal_T_5)
node _io_decode_1_virtual_system_illegal_T_7 = and(is_wfi_1, _io_decode_1_virtual_system_illegal_T_6)
node _io_decode_1_virtual_system_illegal_T_8 = or(_io_decode_1_virtual_system_illegal_T_1, _io_decode_1_virtual_system_illegal_T_7)
node _io_decode_1_virtual_system_illegal_T_9 = bits(addr_1, 9, 8)
node _io_decode_1_virtual_system_illegal_T_10 = eq(_io_decode_1_virtual_system_illegal_T_9, UInt<1>(0h1))
node _io_decode_1_virtual_system_illegal_T_11 = and(is_ret_1, _io_decode_1_virtual_system_illegal_T_10)
node _io_decode_1_virtual_system_illegal_T_12 = bits(reg_mstatus.prv, 0, 0)
node _io_decode_1_virtual_system_illegal_T_13 = eq(_io_decode_1_virtual_system_illegal_T_12, UInt<1>(0h0))
node _io_decode_1_virtual_system_illegal_T_14 = or(_io_decode_1_virtual_system_illegal_T_13, reg_hstatus.vtsr)
node _io_decode_1_virtual_system_illegal_T_15 = and(_io_decode_1_virtual_system_illegal_T_11, _io_decode_1_virtual_system_illegal_T_14)
node _io_decode_1_virtual_system_illegal_T_16 = or(_io_decode_1_virtual_system_illegal_T_8, _io_decode_1_virtual_system_illegal_T_15)
node _io_decode_1_virtual_system_illegal_T_17 = bits(reg_mstatus.prv, 0, 0)
node _io_decode_1_virtual_system_illegal_T_18 = eq(_io_decode_1_virtual_system_illegal_T_17, UInt<1>(0h0))
node _io_decode_1_virtual_system_illegal_T_19 = or(_io_decode_1_virtual_system_illegal_T_18, reg_hstatus.vtvm)
node _io_decode_1_virtual_system_illegal_T_20 = and(is_sfence_1, _io_decode_1_virtual_system_illegal_T_19)
node _io_decode_1_virtual_system_illegal_T_21 = or(_io_decode_1_virtual_system_illegal_T_16, _io_decode_1_virtual_system_illegal_T_20)
node _io_decode_1_virtual_system_illegal_T_22 = and(reg_mstatus.v, _io_decode_1_virtual_system_illegal_T_21)
connect io.decode[1].virtual_system_illegal, _io_decode_1_virtual_system_illegal_T_22
node addr_2 = bits(io.decode[2].inst, 31, 20)
wire decoded_plaInput_3 : UInt<32>
node decoded_invInputs_3 = not(decoded_plaInput_3)
wire decoded_3 : UInt<9>
node decoded_andMatrixOutputs_andMatrixInput_0_21 = bits(decoded_invInputs_3, 20, 20)
node decoded_andMatrixOutputs_andMatrixInput_1_21 = bits(decoded_invInputs_3, 21, 21)
node decoded_andMatrixOutputs_andMatrixInput_2_18 = bits(decoded_invInputs_3, 22, 22)
node decoded_andMatrixOutputs_andMatrixInput_3_18 = bits(decoded_invInputs_3, 23, 23)
node decoded_andMatrixOutputs_andMatrixInput_4_18 = bits(decoded_invInputs_3, 24, 24)
node decoded_andMatrixOutputs_andMatrixInput_5_18 = bits(decoded_invInputs_3, 25, 25)
node decoded_andMatrixOutputs_andMatrixInput_6_18 = bits(decoded_invInputs_3, 26, 26)
node decoded_andMatrixOutputs_andMatrixInput_7_18 = bits(decoded_invInputs_3, 27, 27)
node decoded_andMatrixOutputs_andMatrixInput_8_18 = bits(decoded_invInputs_3, 28, 28)
node decoded_andMatrixOutputs_andMatrixInput_9_18 = bits(decoded_invInputs_3, 29, 29)
node decoded_andMatrixOutputs_andMatrixInput_10_9 = bits(decoded_invInputs_3, 30, 30)
node decoded_andMatrixOutputs_andMatrixInput_11_9 = bits(decoded_invInputs_3, 31, 31)
node decoded_andMatrixOutputs_lo_lo_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_9_18, decoded_andMatrixOutputs_andMatrixInput_10_9)
node decoded_andMatrixOutputs_lo_lo_18 = cat(decoded_andMatrixOutputs_lo_lo_hi_9, decoded_andMatrixOutputs_andMatrixInput_11_9)
node decoded_andMatrixOutputs_lo_hi_hi_18 = cat(decoded_andMatrixOutputs_andMatrixInput_6_18, decoded_andMatrixOutputs_andMatrixInput_7_18)
node decoded_andMatrixOutputs_lo_hi_18 = cat(decoded_andMatrixOutputs_lo_hi_hi_18, decoded_andMatrixOutputs_andMatrixInput_8_18)
node decoded_andMatrixOutputs_lo_18 = cat(decoded_andMatrixOutputs_lo_hi_18, decoded_andMatrixOutputs_lo_lo_18)
node decoded_andMatrixOutputs_hi_lo_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_3_18, decoded_andMatrixOutputs_andMatrixInput_4_18)
node decoded_andMatrixOutputs_hi_lo_18 = cat(decoded_andMatrixOutputs_hi_lo_hi_9, decoded_andMatrixOutputs_andMatrixInput_5_18)
node decoded_andMatrixOutputs_hi_hi_hi_18 = cat(decoded_andMatrixOutputs_andMatrixInput_0_21, decoded_andMatrixOutputs_andMatrixInput_1_21)
node decoded_andMatrixOutputs_hi_hi_18 = cat(decoded_andMatrixOutputs_hi_hi_hi_18, decoded_andMatrixOutputs_andMatrixInput_2_18)
node decoded_andMatrixOutputs_hi_18 = cat(decoded_andMatrixOutputs_hi_hi_18, decoded_andMatrixOutputs_hi_lo_18)
node _decoded_andMatrixOutputs_T_21 = cat(decoded_andMatrixOutputs_hi_18, decoded_andMatrixOutputs_lo_18)
node decoded_andMatrixOutputs_6_2_3 = andr(_decoded_andMatrixOutputs_T_21)
node decoded_andMatrixOutputs_andMatrixInput_0_22 = bits(decoded_plaInput_3, 20, 20)
node decoded_andMatrixOutputs_andMatrixInput_1_22 = bits(decoded_invInputs_3, 21, 21)
node decoded_andMatrixOutputs_andMatrixInput_2_19 = bits(decoded_invInputs_3, 22, 22)
node decoded_andMatrixOutputs_andMatrixInput_3_19 = bits(decoded_invInputs_3, 23, 23)
node decoded_andMatrixOutputs_andMatrixInput_4_19 = bits(decoded_invInputs_3, 24, 24)
node decoded_andMatrixOutputs_andMatrixInput_5_19 = bits(decoded_invInputs_3, 25, 25)
node decoded_andMatrixOutputs_andMatrixInput_6_19 = bits(decoded_invInputs_3, 26, 26)
node decoded_andMatrixOutputs_andMatrixInput_7_19 = bits(decoded_invInputs_3, 27, 27)
node decoded_andMatrixOutputs_andMatrixInput_8_19 = bits(decoded_invInputs_3, 28, 28)
node decoded_andMatrixOutputs_andMatrixInput_9_19 = bits(decoded_invInputs_3, 29, 29)
node decoded_andMatrixOutputs_andMatrixInput_10_10 = bits(decoded_invInputs_3, 30, 30)
node decoded_andMatrixOutputs_andMatrixInput_11_10 = bits(decoded_invInputs_3, 31, 31)
node decoded_andMatrixOutputs_lo_lo_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_9_19, decoded_andMatrixOutputs_andMatrixInput_10_10)
node decoded_andMatrixOutputs_lo_lo_19 = cat(decoded_andMatrixOutputs_lo_lo_hi_10, decoded_andMatrixOutputs_andMatrixInput_11_10)
node decoded_andMatrixOutputs_lo_hi_hi_19 = cat(decoded_andMatrixOutputs_andMatrixInput_6_19, decoded_andMatrixOutputs_andMatrixInput_7_19)
node decoded_andMatrixOutputs_lo_hi_19 = cat(decoded_andMatrixOutputs_lo_hi_hi_19, decoded_andMatrixOutputs_andMatrixInput_8_19)
node decoded_andMatrixOutputs_lo_19 = cat(decoded_andMatrixOutputs_lo_hi_19, decoded_andMatrixOutputs_lo_lo_19)
node decoded_andMatrixOutputs_hi_lo_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_3_19, decoded_andMatrixOutputs_andMatrixInput_4_19)
node decoded_andMatrixOutputs_hi_lo_19 = cat(decoded_andMatrixOutputs_hi_lo_hi_10, decoded_andMatrixOutputs_andMatrixInput_5_19)
node decoded_andMatrixOutputs_hi_hi_hi_19 = cat(decoded_andMatrixOutputs_andMatrixInput_0_22, decoded_andMatrixOutputs_andMatrixInput_1_22)
node decoded_andMatrixOutputs_hi_hi_19 = cat(decoded_andMatrixOutputs_hi_hi_hi_19, decoded_andMatrixOutputs_andMatrixInput_2_19)
node decoded_andMatrixOutputs_hi_19 = cat(decoded_andMatrixOutputs_hi_hi_19, decoded_andMatrixOutputs_hi_lo_19)
node _decoded_andMatrixOutputs_T_22 = cat(decoded_andMatrixOutputs_hi_19, decoded_andMatrixOutputs_lo_19)
node decoded_andMatrixOutputs_4_2_3 = andr(_decoded_andMatrixOutputs_T_22)
node decoded_andMatrixOutputs_andMatrixInput_0_23 = bits(decoded_plaInput_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_23 = bits(decoded_invInputs_3, 22, 22)
node decoded_andMatrixOutputs_andMatrixInput_2_20 = bits(decoded_invInputs_3, 23, 23)
node decoded_andMatrixOutputs_andMatrixInput_3_20 = bits(decoded_invInputs_3, 24, 24)
node decoded_andMatrixOutputs_andMatrixInput_4_20 = bits(decoded_invInputs_3, 25, 25)
node decoded_andMatrixOutputs_andMatrixInput_5_20 = bits(decoded_invInputs_3, 26, 26)
node decoded_andMatrixOutputs_andMatrixInput_6_20 = bits(decoded_invInputs_3, 27, 27)
node decoded_andMatrixOutputs_andMatrixInput_7_20 = bits(decoded_plaInput_3, 28, 28)
node decoded_andMatrixOutputs_andMatrixInput_8_20 = bits(decoded_invInputs_3, 30, 30)
node decoded_andMatrixOutputs_andMatrixInput_9_20 = bits(decoded_invInputs_3, 31, 31)
node decoded_andMatrixOutputs_lo_lo_20 = cat(decoded_andMatrixOutputs_andMatrixInput_8_20, decoded_andMatrixOutputs_andMatrixInput_9_20)
node decoded_andMatrixOutputs_lo_hi_hi_20 = cat(decoded_andMatrixOutputs_andMatrixInput_5_20, decoded_andMatrixOutputs_andMatrixInput_6_20)
node decoded_andMatrixOutputs_lo_hi_20 = cat(decoded_andMatrixOutputs_lo_hi_hi_20, decoded_andMatrixOutputs_andMatrixInput_7_20)
node decoded_andMatrixOutputs_lo_20 = cat(decoded_andMatrixOutputs_lo_hi_20, decoded_andMatrixOutputs_lo_lo_20)
node decoded_andMatrixOutputs_hi_lo_20 = cat(decoded_andMatrixOutputs_andMatrixInput_3_20, decoded_andMatrixOutputs_andMatrixInput_4_20)
node decoded_andMatrixOutputs_hi_hi_hi_20 = cat(decoded_andMatrixOutputs_andMatrixInput_0_23, decoded_andMatrixOutputs_andMatrixInput_1_23)
node decoded_andMatrixOutputs_hi_hi_20 = cat(decoded_andMatrixOutputs_hi_hi_hi_20, decoded_andMatrixOutputs_andMatrixInput_2_20)
node decoded_andMatrixOutputs_hi_20 = cat(decoded_andMatrixOutputs_hi_hi_20, decoded_andMatrixOutputs_hi_lo_20)
node _decoded_andMatrixOutputs_T_23 = cat(decoded_andMatrixOutputs_hi_20, decoded_andMatrixOutputs_lo_20)
node decoded_andMatrixOutputs_3_2_3 = andr(_decoded_andMatrixOutputs_T_23)
node decoded_andMatrixOutputs_andMatrixInput_0_24 = bits(decoded_plaInput_3, 22, 22)
node decoded_andMatrixOutputs_andMatrixInput_1_24 = bits(decoded_invInputs_3, 23, 23)
node decoded_andMatrixOutputs_andMatrixInput_2_21 = bits(decoded_invInputs_3, 24, 24)
node decoded_andMatrixOutputs_andMatrixInput_3_21 = bits(decoded_invInputs_3, 25, 25)
node decoded_andMatrixOutputs_andMatrixInput_4_21 = bits(decoded_invInputs_3, 26, 26)
node decoded_andMatrixOutputs_andMatrixInput_5_21 = bits(decoded_invInputs_3, 27, 27)
node decoded_andMatrixOutputs_andMatrixInput_6_21 = bits(decoded_plaInput_3, 28, 28)
node decoded_andMatrixOutputs_andMatrixInput_7_21 = bits(decoded_invInputs_3, 29, 29)
node decoded_andMatrixOutputs_andMatrixInput_8_21 = bits(decoded_invInputs_3, 30, 30)
node decoded_andMatrixOutputs_andMatrixInput_9_21 = bits(decoded_invInputs_3, 31, 31)
node decoded_andMatrixOutputs_lo_lo_21 = cat(decoded_andMatrixOutputs_andMatrixInput_8_21, decoded_andMatrixOutputs_andMatrixInput_9_21)
node decoded_andMatrixOutputs_lo_hi_hi_21 = cat(decoded_andMatrixOutputs_andMatrixInput_5_21, decoded_andMatrixOutputs_andMatrixInput_6_21)
node decoded_andMatrixOutputs_lo_hi_21 = cat(decoded_andMatrixOutputs_lo_hi_hi_21, decoded_andMatrixOutputs_andMatrixInput_7_21)
node decoded_andMatrixOutputs_lo_21 = cat(decoded_andMatrixOutputs_lo_hi_21, decoded_andMatrixOutputs_lo_lo_21)
node decoded_andMatrixOutputs_hi_lo_21 = cat(decoded_andMatrixOutputs_andMatrixInput_3_21, decoded_andMatrixOutputs_andMatrixInput_4_21)
node decoded_andMatrixOutputs_hi_hi_hi_21 = cat(decoded_andMatrixOutputs_andMatrixInput_0_24, decoded_andMatrixOutputs_andMatrixInput_1_24)
node decoded_andMatrixOutputs_hi_hi_21 = cat(decoded_andMatrixOutputs_hi_hi_hi_21, decoded_andMatrixOutputs_andMatrixInput_2_21)
node decoded_andMatrixOutputs_hi_21 = cat(decoded_andMatrixOutputs_hi_hi_21, decoded_andMatrixOutputs_hi_lo_21)
node _decoded_andMatrixOutputs_T_24 = cat(decoded_andMatrixOutputs_hi_21, decoded_andMatrixOutputs_lo_21)
node decoded_andMatrixOutputs_1_2_3 = andr(_decoded_andMatrixOutputs_T_24)
node decoded_andMatrixOutputs_andMatrixInput_0_25 = bits(decoded_plaInput_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_25 = bits(decoded_plaInput_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_22 = bits(decoded_invInputs_3, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_3_22 = bits(decoded_invInputs_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_4_22 = bits(decoded_plaInput_3, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_5_22 = bits(decoded_plaInput_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_6_22 = bits(decoded_plaInput_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_7_22 = bits(decoded_invInputs_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_8_22 = bits(decoded_invInputs_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_9_22 = bits(decoded_invInputs_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_10_11 = bits(decoded_plaInput_3, 25, 25)
node decoded_andMatrixOutputs_andMatrixInput_11_11 = bits(decoded_invInputs_3, 26, 26)
node decoded_andMatrixOutputs_andMatrixInput_12_3 = bits(decoded_invInputs_3, 27, 27)
node decoded_andMatrixOutputs_andMatrixInput_13_3 = bits(decoded_plaInput_3, 28, 28)
node decoded_andMatrixOutputs_andMatrixInput_14_3 = bits(decoded_invInputs_3, 29, 29)
node decoded_andMatrixOutputs_andMatrixInput_15_3 = bits(decoded_invInputs_3, 30, 30)
node decoded_andMatrixOutputs_andMatrixInput_16_3 = bits(decoded_invInputs_3, 31, 31)
node decoded_andMatrixOutputs_lo_lo_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_15_3, decoded_andMatrixOutputs_andMatrixInput_16_3)
node decoded_andMatrixOutputs_lo_lo_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_13_3, decoded_andMatrixOutputs_andMatrixInput_14_3)
node decoded_andMatrixOutputs_lo_lo_22 = cat(decoded_andMatrixOutputs_lo_lo_hi_11, decoded_andMatrixOutputs_lo_lo_lo_3)
node decoded_andMatrixOutputs_lo_hi_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_11_11, decoded_andMatrixOutputs_andMatrixInput_12_3)
node decoded_andMatrixOutputs_lo_hi_hi_22 = cat(decoded_andMatrixOutputs_andMatrixInput_9_22, decoded_andMatrixOutputs_andMatrixInput_10_11)
node decoded_andMatrixOutputs_lo_hi_22 = cat(decoded_andMatrixOutputs_lo_hi_hi_22, decoded_andMatrixOutputs_lo_hi_lo_3)
node decoded_andMatrixOutputs_lo_22 = cat(decoded_andMatrixOutputs_lo_hi_22, decoded_andMatrixOutputs_lo_lo_22)
node decoded_andMatrixOutputs_hi_lo_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_7_22, decoded_andMatrixOutputs_andMatrixInput_8_22)
node decoded_andMatrixOutputs_hi_lo_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_5_22, decoded_andMatrixOutputs_andMatrixInput_6_22)
node decoded_andMatrixOutputs_hi_lo_22 = cat(decoded_andMatrixOutputs_hi_lo_hi_11, decoded_andMatrixOutputs_hi_lo_lo_3)
node decoded_andMatrixOutputs_hi_hi_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_3_22, decoded_andMatrixOutputs_andMatrixInput_4_22)
node decoded_andMatrixOutputs_hi_hi_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_0_25, decoded_andMatrixOutputs_andMatrixInput_1_25)
node decoded_andMatrixOutputs_hi_hi_hi_22 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_2_22)
node decoded_andMatrixOutputs_hi_hi_22 = cat(decoded_andMatrixOutputs_hi_hi_hi_22, decoded_andMatrixOutputs_hi_hi_lo_3)
node decoded_andMatrixOutputs_hi_22 = cat(decoded_andMatrixOutputs_hi_hi_22, decoded_andMatrixOutputs_hi_lo_22)
node _decoded_andMatrixOutputs_T_25 = cat(decoded_andMatrixOutputs_hi_22, decoded_andMatrixOutputs_lo_22)
node decoded_andMatrixOutputs_0_2_3 = andr(_decoded_andMatrixOutputs_T_25)
node decoded_andMatrixOutputs_andMatrixInput_0_26 = bits(decoded_plaInput_3, 22, 22)
node decoded_andMatrixOutputs_andMatrixInput_1_26 = bits(decoded_invInputs_3, 23, 23)
node decoded_andMatrixOutputs_andMatrixInput_2_23 = bits(decoded_invInputs_3, 24, 24)
node decoded_andMatrixOutputs_andMatrixInput_3_23 = bits(decoded_invInputs_3, 25, 25)
node decoded_andMatrixOutputs_andMatrixInput_4_23 = bits(decoded_invInputs_3, 26, 26)
node decoded_andMatrixOutputs_andMatrixInput_5_23 = bits(decoded_invInputs_3, 27, 27)
node decoded_andMatrixOutputs_andMatrixInput_6_23 = bits(decoded_plaInput_3, 28, 28)
node decoded_andMatrixOutputs_andMatrixInput_7_23 = bits(decoded_plaInput_3, 29, 29)
node decoded_andMatrixOutputs_andMatrixInput_8_23 = bits(decoded_invInputs_3, 30, 30)
node decoded_andMatrixOutputs_andMatrixInput_9_23 = bits(decoded_invInputs_3, 31, 31)
node decoded_andMatrixOutputs_lo_lo_23 = cat(decoded_andMatrixOutputs_andMatrixInput_8_23, decoded_andMatrixOutputs_andMatrixInput_9_23)
node decoded_andMatrixOutputs_lo_hi_hi_23 = cat(decoded_andMatrixOutputs_andMatrixInput_5_23, decoded_andMatrixOutputs_andMatrixInput_6_23)
node decoded_andMatrixOutputs_lo_hi_23 = cat(decoded_andMatrixOutputs_lo_hi_hi_23, decoded_andMatrixOutputs_andMatrixInput_7_23)
node decoded_andMatrixOutputs_lo_23 = cat(decoded_andMatrixOutputs_lo_hi_23, decoded_andMatrixOutputs_lo_lo_23)
node decoded_andMatrixOutputs_hi_lo_23 = cat(decoded_andMatrixOutputs_andMatrixInput_3_23, decoded_andMatrixOutputs_andMatrixInput_4_23)
node decoded_andMatrixOutputs_hi_hi_hi_23 = cat(decoded_andMatrixOutputs_andMatrixInput_0_26, decoded_andMatrixOutputs_andMatrixInput_1_26)
node decoded_andMatrixOutputs_hi_hi_23 = cat(decoded_andMatrixOutputs_hi_hi_hi_23, decoded_andMatrixOutputs_andMatrixInput_2_23)
node decoded_andMatrixOutputs_hi_23 = cat(decoded_andMatrixOutputs_hi_hi_23, decoded_andMatrixOutputs_hi_lo_23)
node _decoded_andMatrixOutputs_T_26 = cat(decoded_andMatrixOutputs_hi_23, decoded_andMatrixOutputs_lo_23)
node decoded_andMatrixOutputs_5_2_3 = andr(_decoded_andMatrixOutputs_T_26)
node decoded_andMatrixOutputs_andMatrixInput_0_27 = bits(decoded_plaInput_3, 30, 30)
node decoded_andMatrixOutputs_andMatrixInput_1_27 = bits(decoded_invInputs_3, 31, 31)
node _decoded_andMatrixOutputs_T_27 = cat(decoded_andMatrixOutputs_andMatrixInput_0_27, decoded_andMatrixOutputs_andMatrixInput_1_27)
node decoded_andMatrixOutputs_2_2_3 = andr(_decoded_andMatrixOutputs_T_27)
node _decoded_orMatrixOutputs_T_21 = orr(decoded_andMatrixOutputs_0_2_3)
node _decoded_orMatrixOutputs_T_22 = orr(decoded_andMatrixOutputs_1_2_3)
node _decoded_orMatrixOutputs_T_23 = orr(decoded_andMatrixOutputs_5_2_3)
node _decoded_orMatrixOutputs_T_24 = cat(decoded_andMatrixOutputs_3_2_3, decoded_andMatrixOutputs_2_2_3)
node _decoded_orMatrixOutputs_T_25 = orr(_decoded_orMatrixOutputs_T_24)
node _decoded_orMatrixOutputs_T_26 = orr(decoded_andMatrixOutputs_4_2_3)
node _decoded_orMatrixOutputs_T_27 = orr(decoded_andMatrixOutputs_6_2_3)
node decoded_orMatrixOutputs_lo_lo_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node decoded_orMatrixOutputs_lo_hi_3 = cat(_decoded_orMatrixOutputs_T_21, UInt<1>(0h0))
node decoded_orMatrixOutputs_lo_3 = cat(decoded_orMatrixOutputs_lo_hi_3, decoded_orMatrixOutputs_lo_lo_3)
node decoded_orMatrixOutputs_hi_lo_3 = cat(_decoded_orMatrixOutputs_T_23, _decoded_orMatrixOutputs_T_22)
node decoded_orMatrixOutputs_hi_hi_hi_3 = cat(_decoded_orMatrixOutputs_T_27, _decoded_orMatrixOutputs_T_26)
node decoded_orMatrixOutputs_hi_hi_3 = cat(decoded_orMatrixOutputs_hi_hi_hi_3, _decoded_orMatrixOutputs_T_25)
node decoded_orMatrixOutputs_hi_3 = cat(decoded_orMatrixOutputs_hi_hi_3, decoded_orMatrixOutputs_hi_lo_3)
node decoded_orMatrixOutputs_3 = cat(decoded_orMatrixOutputs_hi_3, decoded_orMatrixOutputs_lo_3)
node _decoded_invMatrixOutputs_T_27 = bits(decoded_orMatrixOutputs_3, 0, 0)
node _decoded_invMatrixOutputs_T_28 = bits(decoded_orMatrixOutputs_3, 1, 1)
node _decoded_invMatrixOutputs_T_29 = bits(decoded_orMatrixOutputs_3, 2, 2)
node _decoded_invMatrixOutputs_T_30 = bits(decoded_orMatrixOutputs_3, 3, 3)
node _decoded_invMatrixOutputs_T_31 = bits(decoded_orMatrixOutputs_3, 4, 4)
node _decoded_invMatrixOutputs_T_32 = bits(decoded_orMatrixOutputs_3, 5, 5)
node _decoded_invMatrixOutputs_T_33 = bits(decoded_orMatrixOutputs_3, 6, 6)
node _decoded_invMatrixOutputs_T_34 = bits(decoded_orMatrixOutputs_3, 7, 7)
node _decoded_invMatrixOutputs_T_35 = bits(decoded_orMatrixOutputs_3, 8, 8)
node decoded_invMatrixOutputs_lo_lo_3 = cat(_decoded_invMatrixOutputs_T_28, _decoded_invMatrixOutputs_T_27)
node decoded_invMatrixOutputs_lo_hi_3 = cat(_decoded_invMatrixOutputs_T_30, _decoded_invMatrixOutputs_T_29)
node decoded_invMatrixOutputs_lo_3 = cat(decoded_invMatrixOutputs_lo_hi_3, decoded_invMatrixOutputs_lo_lo_3)
node decoded_invMatrixOutputs_hi_lo_3 = cat(_decoded_invMatrixOutputs_T_32, _decoded_invMatrixOutputs_T_31)
node decoded_invMatrixOutputs_hi_hi_hi_3 = cat(_decoded_invMatrixOutputs_T_35, _decoded_invMatrixOutputs_T_34)
node decoded_invMatrixOutputs_hi_hi_3 = cat(decoded_invMatrixOutputs_hi_hi_hi_3, _decoded_invMatrixOutputs_T_33)
node decoded_invMatrixOutputs_hi_3 = cat(decoded_invMatrixOutputs_hi_hi_3, decoded_invMatrixOutputs_hi_lo_3)
node decoded_invMatrixOutputs_3 = cat(decoded_invMatrixOutputs_hi_3, decoded_invMatrixOutputs_lo_3)
connect decoded_3, decoded_invMatrixOutputs_3
connect decoded_plaInput_3, io.decode[2].inst
node _T_101 = bits(decoded_3, 8, 8)
node _T_102 = bits(decoded_3, 7, 7)
node _T_103 = bits(decoded_3, 6, 6)
node _T_104 = bits(decoded_3, 5, 5)
node _T_105 = bits(decoded_3, 4, 4)
node _T_106 = bits(decoded_3, 3, 3)
node _T_107 = bits(decoded_3, 2, 2)
node _T_108 = bits(decoded_3, 1, 1)
node _T_109 = bits(decoded_3, 0, 0)
node _T_110 = bits(_T_101, 0, 0)
node is_break_2 = bits(_T_102, 0, 0)
node is_ret_2 = bits(_T_103, 0, 0)
node _T_111 = bits(_T_104, 0, 0)
node is_wfi_2 = bits(_T_105, 0, 0)
node is_sfence_2 = bits(_T_106, 0, 0)
node is_hfence_vvma_2 = bits(_T_107, 0, 0)
node is_hfence_gvma_2 = bits(_T_108, 0, 0)
node is_hlsv_2 = bits(_T_109, 0, 0)
node _is_counter_T_12 = geq(addr_2, UInt<12>(0hc00))
node _is_counter_T_13 = lt(addr_2, UInt<12>(0hc20))
node _is_counter_T_14 = and(_is_counter_T_12, _is_counter_T_13)
node _is_counter_T_15 = geq(addr_2, UInt<12>(0hc80))
node _is_counter_T_16 = lt(addr_2, UInt<12>(0hca0))
node _is_counter_T_17 = and(_is_counter_T_15, _is_counter_T_16)
node is_counter_2 = or(_is_counter_T_14, _is_counter_T_17)
node _allow_wfi_T_14 = gt(reg_mstatus.prv, UInt<1>(0h1))
node _allow_wfi_T_15 = or(UInt<1>(0h0), _allow_wfi_T_14)
node _allow_wfi_T_16 = eq(reg_mstatus.tw, UInt<1>(0h0))
node _allow_wfi_T_17 = eq(reg_mstatus.v, UInt<1>(0h0))
node _allow_wfi_T_18 = eq(reg_hstatus.vtw, UInt<1>(0h0))
node _allow_wfi_T_19 = or(_allow_wfi_T_17, _allow_wfi_T_18)
node _allow_wfi_T_20 = and(_allow_wfi_T_16, _allow_wfi_T_19)
node allow_wfi_2 = or(_allow_wfi_T_15, _allow_wfi_T_20)
node _allow_sfence_vma_T_8 = gt(reg_mstatus.prv, UInt<1>(0h1))
node _allow_sfence_vma_T_9 = or(UInt<1>(0h0), _allow_sfence_vma_T_8)
node _allow_sfence_vma_T_10 = mux(reg_mstatus.v, reg_hstatus.vtvm, reg_mstatus.tvm)
node _allow_sfence_vma_T_11 = eq(_allow_sfence_vma_T_10, UInt<1>(0h0))
node allow_sfence_vma_2 = or(_allow_sfence_vma_T_9, _allow_sfence_vma_T_11)
node _allow_hfence_vvma_T_6 = eq(reg_mstatus.v, UInt<1>(0h0))
node _allow_hfence_vvma_T_7 = geq(reg_mstatus.prv, UInt<1>(0h1))
node _allow_hfence_vvma_T_8 = and(_allow_hfence_vvma_T_6, _allow_hfence_vvma_T_7)
node allow_hfence_vvma_2 = or(UInt<1>(0h1), _allow_hfence_vvma_T_8)
node _allow_hlsv_T_8 = eq(reg_mstatus.v, UInt<1>(0h0))
node _allow_hlsv_T_9 = geq(reg_mstatus.prv, UInt<1>(0h1))
node _allow_hlsv_T_10 = or(_allow_hlsv_T_9, reg_hstatus.hu)
node _allow_hlsv_T_11 = and(_allow_hlsv_T_8, _allow_hlsv_T_10)
node allow_hlsv_2 = or(UInt<1>(0h1), _allow_hlsv_T_11)
node _allow_sret_T_8 = gt(reg_mstatus.prv, UInt<1>(0h1))
node _allow_sret_T_9 = or(UInt<1>(0h0), _allow_sret_T_8)
node _allow_sret_T_10 = mux(reg_mstatus.v, reg_hstatus.vtsr, reg_mstatus.tsr)
node _allow_sret_T_11 = eq(_allow_sret_T_10, UInt<1>(0h0))
node allow_sret_2 = or(_allow_sret_T_9, _allow_sret_T_11)
node counter_addr_2 = bits(addr_2, 4, 0)
node _allow_counter_T_34 = gt(reg_mstatus.prv, UInt<1>(0h1))
node _allow_counter_T_35 = dshr(read_mcounteren, counter_addr_2)
node _allow_counter_T_36 = bits(_allow_counter_T_35, 0, 0)
node _allow_counter_T_37 = or(_allow_counter_T_34, _allow_counter_T_36)
node _allow_counter_T_38 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _allow_counter_T_39 = geq(reg_mstatus.prv, UInt<1>(0h1))
node _allow_counter_T_40 = or(_allow_counter_T_38, _allow_counter_T_39)
node _allow_counter_T_41 = dshr(read_scounteren, counter_addr_2)
node _allow_counter_T_42 = bits(_allow_counter_T_41, 0, 0)
node _allow_counter_T_43 = or(_allow_counter_T_40, _allow_counter_T_42)
node _allow_counter_T_44 = and(_allow_counter_T_37, _allow_counter_T_43)
node _allow_counter_T_45 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _allow_counter_T_46 = eq(reg_mstatus.v, UInt<1>(0h0))
node _allow_counter_T_47 = or(_allow_counter_T_45, _allow_counter_T_46)
node _allow_counter_T_48 = dshr(read_hcounteren, counter_addr_2)
node _allow_counter_T_49 = bits(_allow_counter_T_48, 0, 0)
node _allow_counter_T_50 = or(_allow_counter_T_47, _allow_counter_T_49)
node allow_counter_2 = and(_allow_counter_T_44, _allow_counter_T_50)
node _io_decode_2_fp_illegal_T = eq(io.status.fs, UInt<1>(0h0))
node _io_decode_2_fp_illegal_T_1 = eq(reg_vsstatus.fs, UInt<1>(0h0))
node _io_decode_2_fp_illegal_T_2 = and(reg_mstatus.v, _io_decode_2_fp_illegal_T_1)
node _io_decode_2_fp_illegal_T_3 = or(_io_decode_2_fp_illegal_T, _io_decode_2_fp_illegal_T_2)
node _io_decode_2_fp_illegal_T_4 = bits(reg_misa, 5, 5)
node _io_decode_2_fp_illegal_T_5 = eq(_io_decode_2_fp_illegal_T_4, UInt<1>(0h0))
node _io_decode_2_fp_illegal_T_6 = or(_io_decode_2_fp_illegal_T_3, _io_decode_2_fp_illegal_T_5)
connect io.decode[2].fp_illegal, _io_decode_2_fp_illegal_T_6
node _io_decode_2_vector_illegal_T = eq(io.status.vs, UInt<1>(0h0))
node _io_decode_2_vector_illegal_T_1 = eq(reg_vsstatus.vs, UInt<1>(0h0))
node _io_decode_2_vector_illegal_T_2 = and(reg_mstatus.v, _io_decode_2_vector_illegal_T_1)
node _io_decode_2_vector_illegal_T_3 = or(_io_decode_2_vector_illegal_T, _io_decode_2_vector_illegal_T_2)
node _io_decode_2_vector_illegal_T_4 = bits(reg_misa, 21, 21)
node _io_decode_2_vector_illegal_T_5 = eq(_io_decode_2_vector_illegal_T_4, UInt<1>(0h0))
node _io_decode_2_vector_illegal_T_6 = or(_io_decode_2_vector_illegal_T_3, _io_decode_2_vector_illegal_T_5)
connect io.decode[2].vector_illegal, _io_decode_2_vector_illegal_T_6
wire io_decode_2_fp_csr_plaInput : UInt<12>
node io_decode_2_fp_csr_invInputs = not(io_decode_2_fp_csr_plaInput)
wire io_decode_2_fp_csr_plaOutput : UInt<1>
node io_decode_2_fp_csr_andMatrixOutputs_andMatrixInput_0 = bits(io_decode_2_fp_csr_invInputs, 8, 8)
node io_decode_2_fp_csr_andMatrixOutputs_andMatrixInput_1 = bits(io_decode_2_fp_csr_invInputs, 9, 9)
node io_decode_2_fp_csr_andMatrixOutputs_andMatrixInput_2 = bits(io_decode_2_fp_csr_invInputs, 10, 10)
node io_decode_2_fp_csr_andMatrixOutputs_andMatrixInput_3 = bits(io_decode_2_fp_csr_invInputs, 11, 11)
node io_decode_2_fp_csr_andMatrixOutputs_lo = cat(io_decode_2_fp_csr_andMatrixOutputs_andMatrixInput_2, io_decode_2_fp_csr_andMatrixOutputs_andMatrixInput_3)
node io_decode_2_fp_csr_andMatrixOutputs_hi = cat(io_decode_2_fp_csr_andMatrixOutputs_andMatrixInput_0, io_decode_2_fp_csr_andMatrixOutputs_andMatrixInput_1)
node _io_decode_2_fp_csr_andMatrixOutputs_T = cat(io_decode_2_fp_csr_andMatrixOutputs_hi, io_decode_2_fp_csr_andMatrixOutputs_lo)
node io_decode_2_fp_csr_andMatrixOutputs_0_2 = andr(_io_decode_2_fp_csr_andMatrixOutputs_T)
node io_decode_2_fp_csr_orMatrixOutputs = orr(io_decode_2_fp_csr_andMatrixOutputs_0_2)
node io_decode_2_fp_csr_invMatrixOutputs = bits(io_decode_2_fp_csr_orMatrixOutputs, 0, 0)
connect io_decode_2_fp_csr_plaOutput, io_decode_2_fp_csr_invMatrixOutputs
connect io_decode_2_fp_csr_plaInput, addr_2
node _io_decode_2_fp_csr_T = bits(io_decode_2_fp_csr_plaOutput, 0, 0)
connect io.decode[2].fp_csr, _io_decode_2_fp_csr_T
wire io_decode_2_vector_csr_plaInput : UInt<12>
node io_decode_2_vector_csr_invInputs = not(io_decode_2_vector_csr_plaInput)
wire io_decode_2_vector_csr_plaOutput : UInt<1>
connect io_decode_2_vector_csr_plaOutput, UInt<1>(0h0)
connect io_decode_2_vector_csr_plaInput, addr_2
node _io_decode_2_vector_csr_T = bits(io_decode_2_vector_csr_plaOutput, 0, 0)
connect io.decode[2].vector_csr, _io_decode_2_vector_csr_T
node _io_decode_2_rocc_illegal_T = eq(io.status.xs, UInt<1>(0h0))
node _io_decode_2_rocc_illegal_T_1 = eq(reg_vsstatus.xs, UInt<1>(0h0))
node _io_decode_2_rocc_illegal_T_2 = and(reg_mstatus.v, _io_decode_2_rocc_illegal_T_1)
node _io_decode_2_rocc_illegal_T_3 = or(_io_decode_2_rocc_illegal_T, _io_decode_2_rocc_illegal_T_2)
node _io_decode_2_rocc_illegal_T_4 = bits(reg_misa, 23, 23)
node _io_decode_2_rocc_illegal_T_5 = eq(_io_decode_2_rocc_illegal_T_4, UInt<1>(0h0))
node _io_decode_2_rocc_illegal_T_6 = or(_io_decode_2_rocc_illegal_T_3, _io_decode_2_rocc_illegal_T_5)
connect io.decode[2].rocc_illegal, _io_decode_2_rocc_illegal_T_6
node _csr_addr_legal_T_18 = bits(addr_2, 9, 8)
node _csr_addr_legal_T_19 = geq(reg_mstatus.prv, _csr_addr_legal_T_18)
node _csr_addr_legal_T_20 = eq(reg_mstatus.v, UInt<1>(0h0))
node _csr_addr_legal_T_21 = and(UInt<1>(0h0), _csr_addr_legal_T_20)
node _csr_addr_legal_T_22 = eq(reg_mstatus.prv, UInt<1>(0h1))
node _csr_addr_legal_T_23 = and(_csr_addr_legal_T_21, _csr_addr_legal_T_22)
node _csr_addr_legal_T_24 = bits(addr_2, 9, 8)
node _csr_addr_legal_T_25 = eq(_csr_addr_legal_T_24, UInt<2>(0h2))
node _csr_addr_legal_T_26 = and(_csr_addr_legal_T_23, _csr_addr_legal_T_25)
node csr_addr_legal_2 = or(_csr_addr_legal_T_19, _csr_addr_legal_T_26)
node _csr_exists_T_604 = eq(addr_2, UInt<11>(0h7a0))
node _csr_exists_T_605 = eq(addr_2, UInt<11>(0h7a1))
node _csr_exists_T_606 = eq(addr_2, UInt<11>(0h7a2))
node _csr_exists_T_607 = eq(addr_2, UInt<11>(0h7a3))
node _csr_exists_T_608 = eq(addr_2, UInt<10>(0h301))
node _csr_exists_T_609 = eq(addr_2, UInt<10>(0h300))
node _csr_exists_T_610 = eq(addr_2, UInt<10>(0h305))
node _csr_exists_T_611 = eq(addr_2, UInt<10>(0h344))
node _csr_exists_T_612 = eq(addr_2, UInt<10>(0h304))
node _csr_exists_T_613 = eq(addr_2, UInt<10>(0h340))
node _csr_exists_T_614 = eq(addr_2, UInt<10>(0h341))
node _csr_exists_T_615 = eq(addr_2, UInt<10>(0h343))
node _csr_exists_T_616 = eq(addr_2, UInt<10>(0h342))
node _csr_exists_T_617 = eq(addr_2, UInt<12>(0hf14))
node _csr_exists_T_618 = eq(addr_2, UInt<11>(0h7b0))
node _csr_exists_T_619 = eq(addr_2, UInt<11>(0h7b1))
node _csr_exists_T_620 = eq(addr_2, UInt<11>(0h7b2))
node _csr_exists_T_621 = eq(addr_2, UInt<1>(0h1))
node _csr_exists_T_622 = eq(addr_2, UInt<2>(0h2))
node _csr_exists_T_623 = eq(addr_2, UInt<2>(0h3))
node _csr_exists_T_624 = eq(addr_2, UInt<10>(0h320))
node _csr_exists_T_625 = eq(addr_2, UInt<12>(0hb00))
node _csr_exists_T_626 = eq(addr_2, UInt<12>(0hb02))
node _csr_exists_T_627 = eq(addr_2, UInt<10>(0h323))
node _csr_exists_T_628 = eq(addr_2, UInt<12>(0hb03))
node _csr_exists_T_629 = eq(addr_2, UInt<12>(0hc03))
node _csr_exists_T_630 = eq(addr_2, UInt<10>(0h324))
node _csr_exists_T_631 = eq(addr_2, UInt<12>(0hb04))
node _csr_exists_T_632 = eq(addr_2, UInt<12>(0hc04))
node _csr_exists_T_633 = eq(addr_2, UInt<10>(0h325))
node _csr_exists_T_634 = eq(addr_2, UInt<12>(0hb05))
node _csr_exists_T_635 = eq(addr_2, UInt<12>(0hc05))
node _csr_exists_T_636 = eq(addr_2, UInt<10>(0h326))
node _csr_exists_T_637 = eq(addr_2, UInt<12>(0hb06))
node _csr_exists_T_638 = eq(addr_2, UInt<12>(0hc06))
node _csr_exists_T_639 = eq(addr_2, UInt<10>(0h327))
node _csr_exists_T_640 = eq(addr_2, UInt<12>(0hb07))
node _csr_exists_T_641 = eq(addr_2, UInt<12>(0hc07))
node _csr_exists_T_642 = eq(addr_2, UInt<10>(0h328))
node _csr_exists_T_643 = eq(addr_2, UInt<12>(0hb08))
node _csr_exists_T_644 = eq(addr_2, UInt<12>(0hc08))
node _csr_exists_T_645 = eq(addr_2, UInt<10>(0h329))
node _csr_exists_T_646 = eq(addr_2, UInt<12>(0hb09))
node _csr_exists_T_647 = eq(addr_2, UInt<12>(0hc09))
node _csr_exists_T_648 = eq(addr_2, UInt<10>(0h32a))
node _csr_exists_T_649 = eq(addr_2, UInt<12>(0hb0a))
node _csr_exists_T_650 = eq(addr_2, UInt<12>(0hc0a))
node _csr_exists_T_651 = eq(addr_2, UInt<10>(0h32b))
node _csr_exists_T_652 = eq(addr_2, UInt<12>(0hb0b))
node _csr_exists_T_653 = eq(addr_2, UInt<12>(0hc0b))
node _csr_exists_T_654 = eq(addr_2, UInt<10>(0h32c))
node _csr_exists_T_655 = eq(addr_2, UInt<12>(0hb0c))
node _csr_exists_T_656 = eq(addr_2, UInt<12>(0hc0c))
node _csr_exists_T_657 = eq(addr_2, UInt<10>(0h32d))
node _csr_exists_T_658 = eq(addr_2, UInt<12>(0hb0d))
node _csr_exists_T_659 = eq(addr_2, UInt<12>(0hc0d))
node _csr_exists_T_660 = eq(addr_2, UInt<10>(0h32e))
node _csr_exists_T_661 = eq(addr_2, UInt<12>(0hb0e))
node _csr_exists_T_662 = eq(addr_2, UInt<12>(0hc0e))
node _csr_exists_T_663 = eq(addr_2, UInt<10>(0h32f))
node _csr_exists_T_664 = eq(addr_2, UInt<12>(0hb0f))
node _csr_exists_T_665 = eq(addr_2, UInt<12>(0hc0f))
node _csr_exists_T_666 = eq(addr_2, UInt<10>(0h330))
node _csr_exists_T_667 = eq(addr_2, UInt<12>(0hb10))
node _csr_exists_T_668 = eq(addr_2, UInt<12>(0hc10))
node _csr_exists_T_669 = eq(addr_2, UInt<10>(0h331))
node _csr_exists_T_670 = eq(addr_2, UInt<12>(0hb11))
node _csr_exists_T_671 = eq(addr_2, UInt<12>(0hc11))
node _csr_exists_T_672 = eq(addr_2, UInt<10>(0h332))
node _csr_exists_T_673 = eq(addr_2, UInt<12>(0hb12))
node _csr_exists_T_674 = eq(addr_2, UInt<12>(0hc12))
node _csr_exists_T_675 = eq(addr_2, UInt<10>(0h333))
node _csr_exists_T_676 = eq(addr_2, UInt<12>(0hb13))
node _csr_exists_T_677 = eq(addr_2, UInt<12>(0hc13))
node _csr_exists_T_678 = eq(addr_2, UInt<10>(0h334))
node _csr_exists_T_679 = eq(addr_2, UInt<12>(0hb14))
node _csr_exists_T_680 = eq(addr_2, UInt<12>(0hc14))
node _csr_exists_T_681 = eq(addr_2, UInt<10>(0h335))
node _csr_exists_T_682 = eq(addr_2, UInt<12>(0hb15))
node _csr_exists_T_683 = eq(addr_2, UInt<12>(0hc15))
node _csr_exists_T_684 = eq(addr_2, UInt<10>(0h336))
node _csr_exists_T_685 = eq(addr_2, UInt<12>(0hb16))
node _csr_exists_T_686 = eq(addr_2, UInt<12>(0hc16))
node _csr_exists_T_687 = eq(addr_2, UInt<10>(0h337))
node _csr_exists_T_688 = eq(addr_2, UInt<12>(0hb17))
node _csr_exists_T_689 = eq(addr_2, UInt<12>(0hc17))
node _csr_exists_T_690 = eq(addr_2, UInt<10>(0h338))
node _csr_exists_T_691 = eq(addr_2, UInt<12>(0hb18))
node _csr_exists_T_692 = eq(addr_2, UInt<12>(0hc18))
node _csr_exists_T_693 = eq(addr_2, UInt<10>(0h339))
node _csr_exists_T_694 = eq(addr_2, UInt<12>(0hb19))
node _csr_exists_T_695 = eq(addr_2, UInt<12>(0hc19))
node _csr_exists_T_696 = eq(addr_2, UInt<10>(0h33a))
node _csr_exists_T_697 = eq(addr_2, UInt<12>(0hb1a))
node _csr_exists_T_698 = eq(addr_2, UInt<12>(0hc1a))
node _csr_exists_T_699 = eq(addr_2, UInt<10>(0h33b))
node _csr_exists_T_700 = eq(addr_2, UInt<12>(0hb1b))
node _csr_exists_T_701 = eq(addr_2, UInt<12>(0hc1b))
node _csr_exists_T_702 = eq(addr_2, UInt<10>(0h33c))
node _csr_exists_T_703 = eq(addr_2, UInt<12>(0hb1c))
node _csr_exists_T_704 = eq(addr_2, UInt<12>(0hc1c))
node _csr_exists_T_705 = eq(addr_2, UInt<10>(0h33d))
node _csr_exists_T_706 = eq(addr_2, UInt<12>(0hb1d))
node _csr_exists_T_707 = eq(addr_2, UInt<12>(0hc1d))
node _csr_exists_T_708 = eq(addr_2, UInt<10>(0h33e))
node _csr_exists_T_709 = eq(addr_2, UInt<12>(0hb1e))
node _csr_exists_T_710 = eq(addr_2, UInt<12>(0hc1e))
node _csr_exists_T_711 = eq(addr_2, UInt<10>(0h33f))
node _csr_exists_T_712 = eq(addr_2, UInt<12>(0hb1f))
node _csr_exists_T_713 = eq(addr_2, UInt<12>(0hc1f))
node _csr_exists_T_714 = eq(addr_2, UInt<10>(0h306))
node _csr_exists_T_715 = eq(addr_2, UInt<12>(0hc00))
node _csr_exists_T_716 = eq(addr_2, UInt<12>(0hc02))
node _csr_exists_T_717 = eq(addr_2, UInt<10>(0h30a))
node _csr_exists_T_718 = eq(addr_2, UInt<9>(0h100))
node _csr_exists_T_719 = eq(addr_2, UInt<9>(0h144))
node _csr_exists_T_720 = eq(addr_2, UInt<9>(0h104))
node _csr_exists_T_721 = eq(addr_2, UInt<9>(0h140))
node _csr_exists_T_722 = eq(addr_2, UInt<9>(0h142))
node _csr_exists_T_723 = eq(addr_2, UInt<9>(0h143))
node _csr_exists_T_724 = eq(addr_2, UInt<9>(0h180))
node _csr_exists_T_725 = eq(addr_2, UInt<9>(0h141))
node _csr_exists_T_726 = eq(addr_2, UInt<9>(0h105))
node _csr_exists_T_727 = eq(addr_2, UInt<9>(0h106))
node _csr_exists_T_728 = eq(addr_2, UInt<10>(0h303))
node _csr_exists_T_729 = eq(addr_2, UInt<10>(0h302))
node _csr_exists_T_730 = eq(addr_2, UInt<9>(0h10a))
node _csr_exists_T_731 = eq(addr_2, UInt<10>(0h3a0))
node _csr_exists_T_732 = eq(addr_2, UInt<10>(0h3a2))
node _csr_exists_T_733 = eq(addr_2, UInt<10>(0h3b0))
node _csr_exists_T_734 = eq(addr_2, UInt<10>(0h3b1))
node _csr_exists_T_735 = eq(addr_2, UInt<10>(0h3b2))
node _csr_exists_T_736 = eq(addr_2, UInt<10>(0h3b3))
node _csr_exists_T_737 = eq(addr_2, UInt<10>(0h3b4))
node _csr_exists_T_738 = eq(addr_2, UInt<10>(0h3b5))
node _csr_exists_T_739 = eq(addr_2, UInt<10>(0h3b6))
node _csr_exists_T_740 = eq(addr_2, UInt<10>(0h3b7))
node _csr_exists_T_741 = eq(addr_2, UInt<10>(0h3b8))
node _csr_exists_T_742 = eq(addr_2, UInt<10>(0h3b9))
node _csr_exists_T_743 = eq(addr_2, UInt<10>(0h3ba))
node _csr_exists_T_744 = eq(addr_2, UInt<10>(0h3bb))
node _csr_exists_T_745 = eq(addr_2, UInt<10>(0h3bc))
node _csr_exists_T_746 = eq(addr_2, UInt<10>(0h3bd))
node _csr_exists_T_747 = eq(addr_2, UInt<10>(0h3be))
node _csr_exists_T_748 = eq(addr_2, UInt<10>(0h3bf))
node _csr_exists_T_749 = eq(addr_2, UInt<12>(0h800))
node _csr_exists_T_750 = eq(addr_2, UInt<12>(0h808))
node _csr_exists_T_751 = eq(addr_2, UInt<11>(0h7c1))
node _csr_exists_T_752 = eq(addr_2, UInt<12>(0hf12))
node _csr_exists_T_753 = eq(addr_2, UInt<12>(0hf13))
node _csr_exists_T_754 = eq(addr_2, UInt<12>(0hf11))
node _csr_exists_T_755 = eq(addr_2, UInt<12>(0hf15))
node _csr_exists_T_756 = or(_csr_exists_T_604, _csr_exists_T_605)
node _csr_exists_T_757 = or(_csr_exists_T_756, _csr_exists_T_606)
node _csr_exists_T_758 = or(_csr_exists_T_757, _csr_exists_T_607)
node _csr_exists_T_759 = or(_csr_exists_T_758, _csr_exists_T_608)
node _csr_exists_T_760 = or(_csr_exists_T_759, _csr_exists_T_609)
node _csr_exists_T_761 = or(_csr_exists_T_760, _csr_exists_T_610)
node _csr_exists_T_762 = or(_csr_exists_T_761, _csr_exists_T_611)
node _csr_exists_T_763 = or(_csr_exists_T_762, _csr_exists_T_612)
node _csr_exists_T_764 = or(_csr_exists_T_763, _csr_exists_T_613)
node _csr_exists_T_765 = or(_csr_exists_T_764, _csr_exists_T_614)
node _csr_exists_T_766 = or(_csr_exists_T_765, _csr_exists_T_615)
node _csr_exists_T_767 = or(_csr_exists_T_766, _csr_exists_T_616)
node _csr_exists_T_768 = or(_csr_exists_T_767, _csr_exists_T_617)
node _csr_exists_T_769 = or(_csr_exists_T_768, _csr_exists_T_618)
node _csr_exists_T_770 = or(_csr_exists_T_769, _csr_exists_T_619)
node _csr_exists_T_771 = or(_csr_exists_T_770, _csr_exists_T_620)
node _csr_exists_T_772 = or(_csr_exists_T_771, _csr_exists_T_621)
node _csr_exists_T_773 = or(_csr_exists_T_772, _csr_exists_T_622)
node _csr_exists_T_774 = or(_csr_exists_T_773, _csr_exists_T_623)
node _csr_exists_T_775 = or(_csr_exists_T_774, _csr_exists_T_624)
node _csr_exists_T_776 = or(_csr_exists_T_775, _csr_exists_T_625)
node _csr_exists_T_777 = or(_csr_exists_T_776, _csr_exists_T_626)
node _csr_exists_T_778 = or(_csr_exists_T_777, _csr_exists_T_627)
node _csr_exists_T_779 = or(_csr_exists_T_778, _csr_exists_T_628)
node _csr_exists_T_780 = or(_csr_exists_T_779, _csr_exists_T_629)
node _csr_exists_T_781 = or(_csr_exists_T_780, _csr_exists_T_630)
node _csr_exists_T_782 = or(_csr_exists_T_781, _csr_exists_T_631)
node _csr_exists_T_783 = or(_csr_exists_T_782, _csr_exists_T_632)
node _csr_exists_T_784 = or(_csr_exists_T_783, _csr_exists_T_633)
node _csr_exists_T_785 = or(_csr_exists_T_784, _csr_exists_T_634)
node _csr_exists_T_786 = or(_csr_exists_T_785, _csr_exists_T_635)
node _csr_exists_T_787 = or(_csr_exists_T_786, _csr_exists_T_636)
node _csr_exists_T_788 = or(_csr_exists_T_787, _csr_exists_T_637)
node _csr_exists_T_789 = or(_csr_exists_T_788, _csr_exists_T_638)
node _csr_exists_T_790 = or(_csr_exists_T_789, _csr_exists_T_639)
node _csr_exists_T_791 = or(_csr_exists_T_790, _csr_exists_T_640)
node _csr_exists_T_792 = or(_csr_exists_T_791, _csr_exists_T_641)
node _csr_exists_T_793 = or(_csr_exists_T_792, _csr_exists_T_642)
node _csr_exists_T_794 = or(_csr_exists_T_793, _csr_exists_T_643)
node _csr_exists_T_795 = or(_csr_exists_T_794, _csr_exists_T_644)
node _csr_exists_T_796 = or(_csr_exists_T_795, _csr_exists_T_645)
node _csr_exists_T_797 = or(_csr_exists_T_796, _csr_exists_T_646)
node _csr_exists_T_798 = or(_csr_exists_T_797, _csr_exists_T_647)
node _csr_exists_T_799 = or(_csr_exists_T_798, _csr_exists_T_648)
node _csr_exists_T_800 = or(_csr_exists_T_799, _csr_exists_T_649)
node _csr_exists_T_801 = or(_csr_exists_T_800, _csr_exists_T_650)
node _csr_exists_T_802 = or(_csr_exists_T_801, _csr_exists_T_651)
node _csr_exists_T_803 = or(_csr_exists_T_802, _csr_exists_T_652)
node _csr_exists_T_804 = or(_csr_exists_T_803, _csr_exists_T_653)
node _csr_exists_T_805 = or(_csr_exists_T_804, _csr_exists_T_654)
node _csr_exists_T_806 = or(_csr_exists_T_805, _csr_exists_T_655)
node _csr_exists_T_807 = or(_csr_exists_T_806, _csr_exists_T_656)
node _csr_exists_T_808 = or(_csr_exists_T_807, _csr_exists_T_657)
node _csr_exists_T_809 = or(_csr_exists_T_808, _csr_exists_T_658)
node _csr_exists_T_810 = or(_csr_exists_T_809, _csr_exists_T_659)
node _csr_exists_T_811 = or(_csr_exists_T_810, _csr_exists_T_660)
node _csr_exists_T_812 = or(_csr_exists_T_811, _csr_exists_T_661)
node _csr_exists_T_813 = or(_csr_exists_T_812, _csr_exists_T_662)
node _csr_exists_T_814 = or(_csr_exists_T_813, _csr_exists_T_663)
node _csr_exists_T_815 = or(_csr_exists_T_814, _csr_exists_T_664)
node _csr_exists_T_816 = or(_csr_exists_T_815, _csr_exists_T_665)
node _csr_exists_T_817 = or(_csr_exists_T_816, _csr_exists_T_666)
node _csr_exists_T_818 = or(_csr_exists_T_817, _csr_exists_T_667)
node _csr_exists_T_819 = or(_csr_exists_T_818, _csr_exists_T_668)
node _csr_exists_T_820 = or(_csr_exists_T_819, _csr_exists_T_669)
node _csr_exists_T_821 = or(_csr_exists_T_820, _csr_exists_T_670)
node _csr_exists_T_822 = or(_csr_exists_T_821, _csr_exists_T_671)
node _csr_exists_T_823 = or(_csr_exists_T_822, _csr_exists_T_672)
node _csr_exists_T_824 = or(_csr_exists_T_823, _csr_exists_T_673)
node _csr_exists_T_825 = or(_csr_exists_T_824, _csr_exists_T_674)
node _csr_exists_T_826 = or(_csr_exists_T_825, _csr_exists_T_675)
node _csr_exists_T_827 = or(_csr_exists_T_826, _csr_exists_T_676)
node _csr_exists_T_828 = or(_csr_exists_T_827, _csr_exists_T_677)
node _csr_exists_T_829 = or(_csr_exists_T_828, _csr_exists_T_678)
node _csr_exists_T_830 = or(_csr_exists_T_829, _csr_exists_T_679)
node _csr_exists_T_831 = or(_csr_exists_T_830, _csr_exists_T_680)
node _csr_exists_T_832 = or(_csr_exists_T_831, _csr_exists_T_681)
node _csr_exists_T_833 = or(_csr_exists_T_832, _csr_exists_T_682)
node _csr_exists_T_834 = or(_csr_exists_T_833, _csr_exists_T_683)
node _csr_exists_T_835 = or(_csr_exists_T_834, _csr_exists_T_684)
node _csr_exists_T_836 = or(_csr_exists_T_835, _csr_exists_T_685)
node _csr_exists_T_837 = or(_csr_exists_T_836, _csr_exists_T_686)
node _csr_exists_T_838 = or(_csr_exists_T_837, _csr_exists_T_687)
node _csr_exists_T_839 = or(_csr_exists_T_838, _csr_exists_T_688)
node _csr_exists_T_840 = or(_csr_exists_T_839, _csr_exists_T_689)
node _csr_exists_T_841 = or(_csr_exists_T_840, _csr_exists_T_690)
node _csr_exists_T_842 = or(_csr_exists_T_841, _csr_exists_T_691)
node _csr_exists_T_843 = or(_csr_exists_T_842, _csr_exists_T_692)
node _csr_exists_T_844 = or(_csr_exists_T_843, _csr_exists_T_693)
node _csr_exists_T_845 = or(_csr_exists_T_844, _csr_exists_T_694)
node _csr_exists_T_846 = or(_csr_exists_T_845, _csr_exists_T_695)
node _csr_exists_T_847 = or(_csr_exists_T_846, _csr_exists_T_696)
node _csr_exists_T_848 = or(_csr_exists_T_847, _csr_exists_T_697)
node _csr_exists_T_849 = or(_csr_exists_T_848, _csr_exists_T_698)
node _csr_exists_T_850 = or(_csr_exists_T_849, _csr_exists_T_699)
node _csr_exists_T_851 = or(_csr_exists_T_850, _csr_exists_T_700)
node _csr_exists_T_852 = or(_csr_exists_T_851, _csr_exists_T_701)
node _csr_exists_T_853 = or(_csr_exists_T_852, _csr_exists_T_702)
node _csr_exists_T_854 = or(_csr_exists_T_853, _csr_exists_T_703)
node _csr_exists_T_855 = or(_csr_exists_T_854, _csr_exists_T_704)
node _csr_exists_T_856 = or(_csr_exists_T_855, _csr_exists_T_705)
node _csr_exists_T_857 = or(_csr_exists_T_856, _csr_exists_T_706)
node _csr_exists_T_858 = or(_csr_exists_T_857, _csr_exists_T_707)
node _csr_exists_T_859 = or(_csr_exists_T_858, _csr_exists_T_708)
node _csr_exists_T_860 = or(_csr_exists_T_859, _csr_exists_T_709)
node _csr_exists_T_861 = or(_csr_exists_T_860, _csr_exists_T_710)
node _csr_exists_T_862 = or(_csr_exists_T_861, _csr_exists_T_711)
node _csr_exists_T_863 = or(_csr_exists_T_862, _csr_exists_T_712)
node _csr_exists_T_864 = or(_csr_exists_T_863, _csr_exists_T_713)
node _csr_exists_T_865 = or(_csr_exists_T_864, _csr_exists_T_714)
node _csr_exists_T_866 = or(_csr_exists_T_865, _csr_exists_T_715)
node _csr_exists_T_867 = or(_csr_exists_T_866, _csr_exists_T_716)
node _csr_exists_T_868 = or(_csr_exists_T_867, _csr_exists_T_717)
node _csr_exists_T_869 = or(_csr_exists_T_868, _csr_exists_T_718)
node _csr_exists_T_870 = or(_csr_exists_T_869, _csr_exists_T_719)
node _csr_exists_T_871 = or(_csr_exists_T_870, _csr_exists_T_720)
node _csr_exists_T_872 = or(_csr_exists_T_871, _csr_exists_T_721)
node _csr_exists_T_873 = or(_csr_exists_T_872, _csr_exists_T_722)
node _csr_exists_T_874 = or(_csr_exists_T_873, _csr_exists_T_723)
node _csr_exists_T_875 = or(_csr_exists_T_874, _csr_exists_T_724)
node _csr_exists_T_876 = or(_csr_exists_T_875, _csr_exists_T_725)
node _csr_exists_T_877 = or(_csr_exists_T_876, _csr_exists_T_726)
node _csr_exists_T_878 = or(_csr_exists_T_877, _csr_exists_T_727)
node _csr_exists_T_879 = or(_csr_exists_T_878, _csr_exists_T_728)
node _csr_exists_T_880 = or(_csr_exists_T_879, _csr_exists_T_729)
node _csr_exists_T_881 = or(_csr_exists_T_880, _csr_exists_T_730)
node _csr_exists_T_882 = or(_csr_exists_T_881, _csr_exists_T_731)
node _csr_exists_T_883 = or(_csr_exists_T_882, _csr_exists_T_732)
node _csr_exists_T_884 = or(_csr_exists_T_883, _csr_exists_T_733)
node _csr_exists_T_885 = or(_csr_exists_T_884, _csr_exists_T_734)
node _csr_exists_T_886 = or(_csr_exists_T_885, _csr_exists_T_735)
node _csr_exists_T_887 = or(_csr_exists_T_886, _csr_exists_T_736)
node _csr_exists_T_888 = or(_csr_exists_T_887, _csr_exists_T_737)
node _csr_exists_T_889 = or(_csr_exists_T_888, _csr_exists_T_738)
node _csr_exists_T_890 = or(_csr_exists_T_889, _csr_exists_T_739)
node _csr_exists_T_891 = or(_csr_exists_T_890, _csr_exists_T_740)
node _csr_exists_T_892 = or(_csr_exists_T_891, _csr_exists_T_741)
node _csr_exists_T_893 = or(_csr_exists_T_892, _csr_exists_T_742)
node _csr_exists_T_894 = or(_csr_exists_T_893, _csr_exists_T_743)
node _csr_exists_T_895 = or(_csr_exists_T_894, _csr_exists_T_744)
node _csr_exists_T_896 = or(_csr_exists_T_895, _csr_exists_T_745)
node _csr_exists_T_897 = or(_csr_exists_T_896, _csr_exists_T_746)
node _csr_exists_T_898 = or(_csr_exists_T_897, _csr_exists_T_747)
node _csr_exists_T_899 = or(_csr_exists_T_898, _csr_exists_T_748)
node _csr_exists_T_900 = or(_csr_exists_T_899, _csr_exists_T_749)
node _csr_exists_T_901 = or(_csr_exists_T_900, _csr_exists_T_750)
node _csr_exists_T_902 = or(_csr_exists_T_901, _csr_exists_T_751)
node _csr_exists_T_903 = or(_csr_exists_T_902, _csr_exists_T_752)
node _csr_exists_T_904 = or(_csr_exists_T_903, _csr_exists_T_753)
node _csr_exists_T_905 = or(_csr_exists_T_904, _csr_exists_T_754)
node csr_exists_2 = or(_csr_exists_T_905, _csr_exists_T_755)
node _io_decode_2_read_illegal_T = eq(csr_addr_legal_2, UInt<1>(0h0))
node _io_decode_2_read_illegal_T_1 = eq(csr_exists_2, UInt<1>(0h0))
node _io_decode_2_read_illegal_T_2 = or(_io_decode_2_read_illegal_T, _io_decode_2_read_illegal_T_1)
node _io_decode_2_read_illegal_T_3 = eq(addr_2, UInt<9>(0h180))
node _io_decode_2_read_illegal_T_4 = eq(addr_2, UInt<11>(0h680))
node _io_decode_2_read_illegal_T_5 = or(_io_decode_2_read_illegal_T_3, _io_decode_2_read_illegal_T_4)
node _io_decode_2_read_illegal_T_6 = eq(allow_sfence_vma_2, UInt<1>(0h0))
node _io_decode_2_read_illegal_T_7 = and(_io_decode_2_read_illegal_T_5, _io_decode_2_read_illegal_T_6)
node _io_decode_2_read_illegal_T_8 = or(_io_decode_2_read_illegal_T_2, _io_decode_2_read_illegal_T_7)
node _io_decode_2_read_illegal_T_9 = eq(allow_counter_2, UInt<1>(0h0))
node _io_decode_2_read_illegal_T_10 = and(is_counter_2, _io_decode_2_read_illegal_T_9)
node _io_decode_2_read_illegal_T_11 = or(_io_decode_2_read_illegal_T_8, _io_decode_2_read_illegal_T_10)
wire io_decode_2_read_illegal_plaInput : UInt<12>
node io_decode_2_read_illegal_invInputs = not(io_decode_2_read_illegal_plaInput)
wire io_decode_2_read_illegal_plaOutput : UInt<1>
node io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_0 = bits(io_decode_2_read_illegal_plaInput, 4, 4)
node io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_1 = bits(io_decode_2_read_illegal_plaInput, 5, 5)
node io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_2 = bits(io_decode_2_read_illegal_invInputs, 6, 6)
node io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_3 = bits(io_decode_2_read_illegal_plaInput, 7, 7)
node io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_4 = bits(io_decode_2_read_illegal_plaInput, 8, 8)
node io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_5 = bits(io_decode_2_read_illegal_plaInput, 9, 9)
node io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_6 = bits(io_decode_2_read_illegal_plaInput, 10, 10)
node io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_7 = bits(io_decode_2_read_illegal_invInputs, 11, 11)
node io_decode_2_read_illegal_andMatrixOutputs_lo_lo = cat(io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_6, io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_7)
node io_decode_2_read_illegal_andMatrixOutputs_lo_hi = cat(io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_4, io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_5)
node io_decode_2_read_illegal_andMatrixOutputs_lo = cat(io_decode_2_read_illegal_andMatrixOutputs_lo_hi, io_decode_2_read_illegal_andMatrixOutputs_lo_lo)
node io_decode_2_read_illegal_andMatrixOutputs_hi_lo = cat(io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_2, io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_3)
node io_decode_2_read_illegal_andMatrixOutputs_hi_hi = cat(io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_0, io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_1)
node io_decode_2_read_illegal_andMatrixOutputs_hi = cat(io_decode_2_read_illegal_andMatrixOutputs_hi_hi, io_decode_2_read_illegal_andMatrixOutputs_hi_lo)
node _io_decode_2_read_illegal_andMatrixOutputs_T = cat(io_decode_2_read_illegal_andMatrixOutputs_hi, io_decode_2_read_illegal_andMatrixOutputs_lo)
node io_decode_2_read_illegal_andMatrixOutputs_0_2 = andr(_io_decode_2_read_illegal_andMatrixOutputs_T)
node io_decode_2_read_illegal_orMatrixOutputs = orr(io_decode_2_read_illegal_andMatrixOutputs_0_2)
node io_decode_2_read_illegal_invMatrixOutputs = bits(io_decode_2_read_illegal_orMatrixOutputs, 0, 0)
connect io_decode_2_read_illegal_plaOutput, io_decode_2_read_illegal_invMatrixOutputs
connect io_decode_2_read_illegal_plaInput, addr_2
node _io_decode_2_read_illegal_T_12 = bits(io_decode_2_read_illegal_plaOutput, 0, 0)
node _io_decode_2_read_illegal_T_13 = eq(reg_debug, UInt<1>(0h0))
node _io_decode_2_read_illegal_T_14 = and(_io_decode_2_read_illegal_T_12, _io_decode_2_read_illegal_T_13)
node _io_decode_2_read_illegal_T_15 = or(_io_decode_2_read_illegal_T_11, _io_decode_2_read_illegal_T_14)
wire io_decode_2_read_illegal_plaInput_1 : UInt<12>
node io_decode_2_read_illegal_invInputs_1 = not(io_decode_2_read_illegal_plaInput_1)
wire io_decode_2_read_illegal_plaOutput_1 : UInt<1>
connect io_decode_2_read_illegal_plaOutput_1, UInt<1>(0h0)
connect io_decode_2_read_illegal_plaInput_1, addr_2
node _io_decode_2_read_illegal_T_16 = bits(io_decode_2_read_illegal_plaOutput_1, 0, 0)
node _io_decode_2_read_illegal_T_17 = and(_io_decode_2_read_illegal_T_16, io.decode[2].vector_illegal)
node _io_decode_2_read_illegal_T_18 = or(_io_decode_2_read_illegal_T_15, _io_decode_2_read_illegal_T_17)
node _io_decode_2_read_illegal_T_19 = and(io.decode[2].fp_csr, io.decode[2].fp_illegal)
node _io_decode_2_read_illegal_T_20 = or(_io_decode_2_read_illegal_T_18, _io_decode_2_read_illegal_T_19)
connect io.decode[2].read_illegal, _io_decode_2_read_illegal_T_20
node _io_decode_2_write_illegal_T = bits(addr_2, 11, 10)
node _io_decode_2_write_illegal_T_1 = andr(_io_decode_2_write_illegal_T)
connect io.decode[2].write_illegal, _io_decode_2_write_illegal_T_1
node _io_decode_2_write_flush_addr_m_T = shl(UInt<2>(0h3), 8)
node io_decode_2_write_flush_addr_m = or(addr_2, _io_decode_2_write_flush_addr_m_T)
node _io_decode_2_write_flush_T = geq(io_decode_2_write_flush_addr_m, UInt<10>(0h340))
node _io_decode_2_write_flush_T_1 = leq(io_decode_2_write_flush_addr_m, UInt<10>(0h343))
node _io_decode_2_write_flush_T_2 = and(_io_decode_2_write_flush_T, _io_decode_2_write_flush_T_1)
node _io_decode_2_write_flush_T_3 = eq(_io_decode_2_write_flush_T_2, UInt<1>(0h0))
connect io.decode[2].write_flush, _io_decode_2_write_flush_T_3
node _io_decode_2_system_illegal_T = eq(csr_addr_legal_2, UInt<1>(0h0))
node _io_decode_2_system_illegal_T_1 = eq(is_hlsv_2, UInt<1>(0h0))
node _io_decode_2_system_illegal_T_2 = and(_io_decode_2_system_illegal_T, _io_decode_2_system_illegal_T_1)
node _io_decode_2_system_illegal_T_3 = eq(allow_wfi_2, UInt<1>(0h0))
node _io_decode_2_system_illegal_T_4 = and(is_wfi_2, _io_decode_2_system_illegal_T_3)
node _io_decode_2_system_illegal_T_5 = or(_io_decode_2_system_illegal_T_2, _io_decode_2_system_illegal_T_4)
node _io_decode_2_system_illegal_T_6 = eq(allow_sret_2, UInt<1>(0h0))
node _io_decode_2_system_illegal_T_7 = and(is_ret_2, _io_decode_2_system_illegal_T_6)
node _io_decode_2_system_illegal_T_8 = or(_io_decode_2_system_illegal_T_5, _io_decode_2_system_illegal_T_7)
node _io_decode_2_system_illegal_T_9 = bits(addr_2, 10, 10)
node _io_decode_2_system_illegal_T_10 = and(is_ret_2, _io_decode_2_system_illegal_T_9)
node _io_decode_2_system_illegal_T_11 = bits(addr_2, 7, 7)
node _io_decode_2_system_illegal_T_12 = and(_io_decode_2_system_illegal_T_10, _io_decode_2_system_illegal_T_11)
node _io_decode_2_system_illegal_T_13 = eq(reg_debug, UInt<1>(0h0))
node _io_decode_2_system_illegal_T_14 = and(_io_decode_2_system_illegal_T_12, _io_decode_2_system_illegal_T_13)
node _io_decode_2_system_illegal_T_15 = or(_io_decode_2_system_illegal_T_8, _io_decode_2_system_illegal_T_14)
node _io_decode_2_system_illegal_T_16 = or(is_sfence_2, is_hfence_gvma_2)
node _io_decode_2_system_illegal_T_17 = eq(allow_sfence_vma_2, UInt<1>(0h0))
node _io_decode_2_system_illegal_T_18 = and(_io_decode_2_system_illegal_T_16, _io_decode_2_system_illegal_T_17)
node _io_decode_2_system_illegal_T_19 = or(_io_decode_2_system_illegal_T_15, _io_decode_2_system_illegal_T_18)
node _io_decode_2_system_illegal_T_20 = eq(allow_hfence_vvma_2, UInt<1>(0h0))
node _io_decode_2_system_illegal_T_21 = and(is_hfence_vvma_2, _io_decode_2_system_illegal_T_20)
node _io_decode_2_system_illegal_T_22 = or(_io_decode_2_system_illegal_T_19, _io_decode_2_system_illegal_T_21)
node _io_decode_2_system_illegal_T_23 = eq(allow_hlsv_2, UInt<1>(0h0))
node _io_decode_2_system_illegal_T_24 = and(is_hlsv_2, _io_decode_2_system_illegal_T_23)
node _io_decode_2_system_illegal_T_25 = or(_io_decode_2_system_illegal_T_22, _io_decode_2_system_illegal_T_24)
connect io.decode[2].system_illegal, _io_decode_2_system_illegal_T_25
node _io_decode_2_virtual_access_illegal_T = and(reg_mstatus.v, csr_exists_2)
node _io_decode_2_virtual_access_illegal_T_1 = bits(addr_2, 9, 8)
node _io_decode_2_virtual_access_illegal_T_2 = eq(_io_decode_2_virtual_access_illegal_T_1, UInt<2>(0h2))
node _io_decode_2_virtual_access_illegal_T_3 = dshr(read_mcounteren, counter_addr_2)
node _io_decode_2_virtual_access_illegal_T_4 = bits(_io_decode_2_virtual_access_illegal_T_3, 0, 0)
node _io_decode_2_virtual_access_illegal_T_5 = and(is_counter_2, _io_decode_2_virtual_access_illegal_T_4)
node _io_decode_2_virtual_access_illegal_T_6 = dshr(read_hcounteren, counter_addr_2)
node _io_decode_2_virtual_access_illegal_T_7 = bits(_io_decode_2_virtual_access_illegal_T_6, 0, 0)
node _io_decode_2_virtual_access_illegal_T_8 = eq(_io_decode_2_virtual_access_illegal_T_7, UInt<1>(0h0))
node _io_decode_2_virtual_access_illegal_T_9 = bits(reg_mstatus.prv, 0, 0)
node _io_decode_2_virtual_access_illegal_T_10 = eq(_io_decode_2_virtual_access_illegal_T_9, UInt<1>(0h0))
node _io_decode_2_virtual_access_illegal_T_11 = dshr(read_scounteren, counter_addr_2)
node _io_decode_2_virtual_access_illegal_T_12 = bits(_io_decode_2_virtual_access_illegal_T_11, 0, 0)
node _io_decode_2_virtual_access_illegal_T_13 = eq(_io_decode_2_virtual_access_illegal_T_12, UInt<1>(0h0))
node _io_decode_2_virtual_access_illegal_T_14 = and(_io_decode_2_virtual_access_illegal_T_10, _io_decode_2_virtual_access_illegal_T_13)
node _io_decode_2_virtual_access_illegal_T_15 = or(_io_decode_2_virtual_access_illegal_T_8, _io_decode_2_virtual_access_illegal_T_14)
node _io_decode_2_virtual_access_illegal_T_16 = and(_io_decode_2_virtual_access_illegal_T_5, _io_decode_2_virtual_access_illegal_T_15)
node _io_decode_2_virtual_access_illegal_T_17 = or(_io_decode_2_virtual_access_illegal_T_2, _io_decode_2_virtual_access_illegal_T_16)
node _io_decode_2_virtual_access_illegal_T_18 = bits(addr_2, 9, 8)
node _io_decode_2_virtual_access_illegal_T_19 = eq(_io_decode_2_virtual_access_illegal_T_18, UInt<1>(0h1))
node _io_decode_2_virtual_access_illegal_T_20 = bits(reg_mstatus.prv, 0, 0)
node _io_decode_2_virtual_access_illegal_T_21 = eq(_io_decode_2_virtual_access_illegal_T_20, UInt<1>(0h0))
node _io_decode_2_virtual_access_illegal_T_22 = and(_io_decode_2_virtual_access_illegal_T_19, _io_decode_2_virtual_access_illegal_T_21)
node _io_decode_2_virtual_access_illegal_T_23 = or(_io_decode_2_virtual_access_illegal_T_17, _io_decode_2_virtual_access_illegal_T_22)
node _io_decode_2_virtual_access_illegal_T_24 = eq(addr_2, UInt<9>(0h180))
node _io_decode_2_virtual_access_illegal_T_25 = bits(reg_mstatus.prv, 0, 0)
node _io_decode_2_virtual_access_illegal_T_26 = and(_io_decode_2_virtual_access_illegal_T_24, _io_decode_2_virtual_access_illegal_T_25)
node _io_decode_2_virtual_access_illegal_T_27 = and(_io_decode_2_virtual_access_illegal_T_26, reg_hstatus.vtvm)
node _io_decode_2_virtual_access_illegal_T_28 = or(_io_decode_2_virtual_access_illegal_T_23, _io_decode_2_virtual_access_illegal_T_27)
node _io_decode_2_virtual_access_illegal_T_29 = and(_io_decode_2_virtual_access_illegal_T, _io_decode_2_virtual_access_illegal_T_28)
connect io.decode[2].virtual_access_illegal, _io_decode_2_virtual_access_illegal_T_29
node _io_decode_2_virtual_system_illegal_T = or(is_hfence_vvma_2, is_hfence_gvma_2)
node _io_decode_2_virtual_system_illegal_T_1 = or(_io_decode_2_virtual_system_illegal_T, is_hlsv_2)
node _io_decode_2_virtual_system_illegal_T_2 = bits(reg_mstatus.prv, 0, 0)
node _io_decode_2_virtual_system_illegal_T_3 = eq(_io_decode_2_virtual_system_illegal_T_2, UInt<1>(0h0))
node _io_decode_2_virtual_system_illegal_T_4 = eq(reg_mstatus.tw, UInt<1>(0h0))
node _io_decode_2_virtual_system_illegal_T_5 = and(_io_decode_2_virtual_system_illegal_T_4, reg_hstatus.vtw)
node _io_decode_2_virtual_system_illegal_T_6 = or(_io_decode_2_virtual_system_illegal_T_3, _io_decode_2_virtual_system_illegal_T_5)
node _io_decode_2_virtual_system_illegal_T_7 = and(is_wfi_2, _io_decode_2_virtual_system_illegal_T_6)
node _io_decode_2_virtual_system_illegal_T_8 = or(_io_decode_2_virtual_system_illegal_T_1, _io_decode_2_virtual_system_illegal_T_7)
node _io_decode_2_virtual_system_illegal_T_9 = bits(addr_2, 9, 8)
node _io_decode_2_virtual_system_illegal_T_10 = eq(_io_decode_2_virtual_system_illegal_T_9, UInt<1>(0h1))
node _io_decode_2_virtual_system_illegal_T_11 = and(is_ret_2, _io_decode_2_virtual_system_illegal_T_10)
node _io_decode_2_virtual_system_illegal_T_12 = bits(reg_mstatus.prv, 0, 0)
node _io_decode_2_virtual_system_illegal_T_13 = eq(_io_decode_2_virtual_system_illegal_T_12, UInt<1>(0h0))
node _io_decode_2_virtual_system_illegal_T_14 = or(_io_decode_2_virtual_system_illegal_T_13, reg_hstatus.vtsr)
node _io_decode_2_virtual_system_illegal_T_15 = and(_io_decode_2_virtual_system_illegal_T_11, _io_decode_2_virtual_system_illegal_T_14)
node _io_decode_2_virtual_system_illegal_T_16 = or(_io_decode_2_virtual_system_illegal_T_8, _io_decode_2_virtual_system_illegal_T_15)
node _io_decode_2_virtual_system_illegal_T_17 = bits(reg_mstatus.prv, 0, 0)
node _io_decode_2_virtual_system_illegal_T_18 = eq(_io_decode_2_virtual_system_illegal_T_17, UInt<1>(0h0))
node _io_decode_2_virtual_system_illegal_T_19 = or(_io_decode_2_virtual_system_illegal_T_18, reg_hstatus.vtvm)
node _io_decode_2_virtual_system_illegal_T_20 = and(is_sfence_2, _io_decode_2_virtual_system_illegal_T_19)
node _io_decode_2_virtual_system_illegal_T_21 = or(_io_decode_2_virtual_system_illegal_T_16, _io_decode_2_virtual_system_illegal_T_20)
node _io_decode_2_virtual_system_illegal_T_22 = and(reg_mstatus.v, _io_decode_2_virtual_system_illegal_T_21)
connect io.decode[2].virtual_system_illegal, _io_decode_2_virtual_system_illegal_T_22
node _cause_T = bits(reg_mstatus.prv, 0, 0)
node _cause_T_1 = and(_cause_T, reg_mstatus.v)
node _cause_T_2 = mux(_cause_T_1, UInt<2>(0h2), reg_mstatus.prv)
node _cause_T_3 = add(UInt<4>(0h8), _cause_T_2)
node _cause_T_4 = tail(_cause_T_3, 1)
node _cause_T_5 = mux(insn_break, UInt<2>(0h3), io.cause)
node cause = mux(insn_call, _cause_T_4, _cause_T_5)
node cause_lsbs = bits(cause, 7, 0)
node cause_deleg_lsbs = bits(cause, 5, 0)
node _causeIsDebugInt_T = bits(cause, 63, 63)
node _causeIsDebugInt_T_1 = eq(cause_lsbs, UInt<4>(0he))
node causeIsDebugInt = and(_causeIsDebugInt_T, _causeIsDebugInt_T_1)
node _causeIsDebugTrigger_T = bits(cause, 63, 63)
node _causeIsDebugTrigger_T_1 = eq(_causeIsDebugTrigger_T, UInt<1>(0h0))
node _causeIsDebugTrigger_T_2 = eq(cause_lsbs, UInt<4>(0he))
node causeIsDebugTrigger = and(_causeIsDebugTrigger_T_1, _causeIsDebugTrigger_T_2)
node _causeIsDebugBreak_T = bits(cause, 63, 63)
node _causeIsDebugBreak_T_1 = eq(_causeIsDebugBreak_T, UInt<1>(0h0))
node _causeIsDebugBreak_T_2 = and(_causeIsDebugBreak_T_1, insn_break)
node causeIsDebugBreak_lo = cat(reg_dcsr.ebreaks, reg_dcsr.ebreaku)
node causeIsDebugBreak_hi = cat(reg_dcsr.ebreakm, reg_dcsr.ebreakh)
node _causeIsDebugBreak_T_3 = cat(causeIsDebugBreak_hi, causeIsDebugBreak_lo)
node _causeIsDebugBreak_T_4 = dshr(_causeIsDebugBreak_T_3, reg_mstatus.prv)
node _causeIsDebugBreak_T_5 = bits(_causeIsDebugBreak_T_4, 0, 0)
node causeIsDebugBreak = and(_causeIsDebugBreak_T_2, _causeIsDebugBreak_T_5)
node _trapToDebug_T = or(reg_singleStepped, causeIsDebugInt)
node _trapToDebug_T_1 = or(_trapToDebug_T, causeIsDebugTrigger)
node _trapToDebug_T_2 = or(_trapToDebug_T_1, causeIsDebugBreak)
node _trapToDebug_T_3 = or(_trapToDebug_T_2, reg_debug)
node trapToDebug = and(UInt<1>(0h1), _trapToDebug_T_3)
node _debugTVec_T = mux(insn_break, UInt<12>(0h800), UInt<12>(0h808))
node debugTVec = mux(reg_debug, _debugTVec_T, UInt<12>(0h800))
node _delegate_T = leq(reg_mstatus.prv, UInt<1>(0h1))
node _delegate_T_1 = and(UInt<1>(0h1), _delegate_T)
node _delegate_T_2 = bits(cause, 63, 63)
node _delegate_T_3 = dshr(read_mideleg, cause_deleg_lsbs)
node _delegate_T_4 = bits(_delegate_T_3, 0, 0)
node _delegate_T_5 = dshr(read_medeleg, cause_deleg_lsbs)
node _delegate_T_6 = bits(_delegate_T_5, 0, 0)
node _delegate_T_7 = mux(_delegate_T_2, _delegate_T_4, _delegate_T_6)
node delegate = and(_delegate_T_1, _delegate_T_7)
node _delegateVS_T = and(reg_mstatus.v, delegate)
node _delegateVS_T_1 = bits(cause, 63, 63)
node _delegateVS_T_2 = dshr(read_hideleg, cause_deleg_lsbs)
node _delegateVS_T_3 = bits(_delegateVS_T_2, 0, 0)
node _delegateVS_T_4 = dshr(read_hedeleg, cause_deleg_lsbs)
node _delegateVS_T_5 = bits(_delegateVS_T_4, 0, 0)
node _delegateVS_T_6 = mux(_delegateVS_T_1, _delegateVS_T_3, _delegateVS_T_5)
node delegateVS = and(_delegateVS_T, _delegateVS_T_6)
node _notDebugTVec_base_T = mux(delegateVS, read_vstvec, read_stvec)
node notDebugTVec_base = mux(delegate, _notDebugTVec_base_T, read_mtvec)
node _notDebugTVec_interruptOffset_T = bits(cause, 5, 0)
node notDebugTVec_interruptOffset = shl(_notDebugTVec_interruptOffset_T, 2)
node _notDebugTVec_interruptVec_T = shr(notDebugTVec_base, 8)
node notDebugTVec_interruptVec = cat(_notDebugTVec_interruptVec_T, notDebugTVec_interruptOffset)
node _notDebugTVec_doVector_T = bits(notDebugTVec_base, 0, 0)
node _notDebugTVec_doVector_T_1 = bits(cause, 63, 63)
node _notDebugTVec_doVector_T_2 = and(_notDebugTVec_doVector_T, _notDebugTVec_doVector_T_1)
node _notDebugTVec_doVector_T_3 = shr(cause_lsbs, 6)
node _notDebugTVec_doVector_T_4 = eq(_notDebugTVec_doVector_T_3, UInt<1>(0h0))
node notDebugTVec_doVector = and(_notDebugTVec_doVector_T_2, _notDebugTVec_doVector_T_4)
node _notDebugTVec_T = shr(notDebugTVec_base, 2)
node _notDebugTVec_T_1 = shl(_notDebugTVec_T, 2)
node notDebugTVec = mux(notDebugTVec_doVector, notDebugTVec_interruptVec, _notDebugTVec_T_1)
node _causeIsRnmiInt_T = bits(cause, 63, 63)
node _causeIsRnmiInt_T_1 = bits(cause, 62, 62)
node _causeIsRnmiInt_T_2 = and(_causeIsRnmiInt_T, _causeIsRnmiInt_T_1)
node _causeIsRnmiInt_T_3 = eq(cause_lsbs, UInt<4>(0hd))
node _causeIsRnmiInt_T_4 = eq(cause_lsbs, UInt<4>(0hc))
node _causeIsRnmiInt_T_5 = or(_causeIsRnmiInt_T_3, _causeIsRnmiInt_T_4)
node causeIsRnmiInt = and(_causeIsRnmiInt_T_2, _causeIsRnmiInt_T_5)
node _causeIsRnmiBEU_T = bits(cause, 63, 63)
node _causeIsRnmiBEU_T_1 = bits(cause, 62, 62)
node _causeIsRnmiBEU_T_2 = and(_causeIsRnmiBEU_T, _causeIsRnmiBEU_T_1)
node _causeIsRnmiBEU_T_3 = eq(cause_lsbs, UInt<4>(0hc))
node causeIsRnmiBEU = and(_causeIsRnmiBEU_T_2, _causeIsRnmiBEU_T_3)
node trapToNmiInt = and(UInt<1>(0h0), causeIsRnmiInt)
node _trapToNmiXcpt_T = eq(reg_rnmie, UInt<1>(0h0))
node trapToNmiXcpt = and(UInt<1>(0h0), _trapToNmiXcpt_T)
node trapToNmi = or(trapToNmiInt, trapToNmiXcpt)
node _nmiTVec_T = mux(causeIsRnmiInt, UInt<1>(0h0), UInt<1>(0h0))
node _nmiTVec_T_1 = shr(_nmiTVec_T, 1)
node nmiTVec = shl(_nmiTVec_T_1, 1)
node _tvec_T = mux(trapToNmi, nmiTVec, notDebugTVec)
node tvec = mux(trapToDebug, debugTVec, _tvec_T)
connect io.evec, tvec
connect io.ptbr, reg_satp
connect io.hgatp, reg_hgatp
connect io.vsatp, reg_vsatp
node _io_eret_T = or(insn_call, insn_break)
node _io_eret_T_1 = or(_io_eret_T, insn_ret)
connect io.eret, _io_eret_T_1
node _io_singleStep_T = eq(reg_debug, UInt<1>(0h0))
node _io_singleStep_T_1 = and(reg_dcsr.step, _io_singleStep_T)
connect io.singleStep, _io_singleStep_T_1
connect io.status, reg_mstatus
node _io_status_sd_T = andr(io.status.fs)
node _io_status_sd_T_1 = andr(io.status.xs)
node _io_status_sd_T_2 = or(_io_status_sd_T, _io_status_sd_T_1)
node _io_status_sd_T_3 = andr(io.status.vs)
node _io_status_sd_T_4 = or(_io_status_sd_T_2, _io_status_sd_T_3)
connect io.status.sd, _io_status_sd_T_4
connect io.status.debug, reg_debug
connect io.status.isa, reg_misa
connect io.status.uxl, UInt<2>(0h2)
connect io.status.sxl, UInt<2>(0h2)
node _io_status_dprv_T = eq(reg_debug, UInt<1>(0h0))
node _io_status_dprv_T_1 = and(reg_mstatus.mprv, _io_status_dprv_T)
node _io_status_dprv_T_2 = mux(_io_status_dprv_T_1, reg_mstatus.mpp, reg_mstatus.prv)
connect io.status.dprv, _io_status_dprv_T_2
node _io_status_dv_T = eq(reg_debug, UInt<1>(0h0))
node _io_status_dv_T_1 = and(reg_mstatus.mprv, _io_status_dv_T)
node _io_status_dv_T_2 = mux(_io_status_dv_T_1, reg_mstatus.mpv, UInt<1>(0h0))
node _io_status_dv_T_3 = or(reg_mstatus.v, _io_status_dv_T_2)
connect io.status.dv, _io_status_dv_T_3
node _io_status_sd_rv32_T = and(UInt<1>(0h0), io.status.sd)
connect io.status.sd_rv32, _io_status_sd_rv32_T
connect io.status.mpv, reg_mstatus.mpv
connect io.status.gva, reg_mstatus.gva
connect io.hstatus, reg_hstatus
connect io.hstatus.vsxl, UInt<2>(0h2)
connect io.gstatus, reg_vsstatus
node _io_gstatus_sd_T = andr(io.gstatus.fs)
node _io_gstatus_sd_T_1 = andr(io.gstatus.xs)
node _io_gstatus_sd_T_2 = or(_io_gstatus_sd_T, _io_gstatus_sd_T_1)
node _io_gstatus_sd_T_3 = andr(io.gstatus.vs)
node _io_gstatus_sd_T_4 = or(_io_gstatus_sd_T_2, _io_gstatus_sd_T_3)
connect io.gstatus.sd, _io_gstatus_sd_T_4
connect io.gstatus.uxl, UInt<2>(0h2)
node _io_gstatus_sd_rv32_T = and(UInt<1>(0h0), io.gstatus.sd)
connect io.gstatus.sd_rv32, _io_gstatus_sd_rv32_T
node _exception_T = or(insn_call, insn_break)
node exception = or(_exception_T, io.exception)
node _T_112 = add(insn_ret, insn_call)
node _T_113 = bits(_T_112, 1, 0)
node _T_114 = add(insn_break, io.exception)
node _T_115 = bits(_T_114, 1, 0)
node _T_116 = add(_T_113, _T_115)
node _T_117 = bits(_T_116, 2, 0)
node _T_118 = leq(_T_117, UInt<1>(0h1))
node _T_119 = asUInt(reset)
node _T_120 = eq(_T_119, UInt<1>(0h0))
when _T_120 :
node _T_121 = eq(_T_118, UInt<1>(0h0))
when _T_121 :
printf(clock, UInt<1>(0h1), "Assertion failed: these conditions must be mutually exclusive\n at CSR.scala:1021 assert(PopCount(insn_ret :: insn_call :: insn_break :: io.exception :: Nil) <= 1.U, \"these conditions must be mutually exclusive\")\n") : printf
assert(clock, _T_118, UInt<1>(0h1), "") : assert
node _T_122 = eq(io.singleStep, UInt<1>(0h0))
node _T_123 = and(insn_wfi, _T_122)
node _T_124 = eq(reg_debug, UInt<1>(0h0))
node _T_125 = and(_T_123, _T_124)
when _T_125 :
connect reg_wfi, UInt<1>(0h1)
node _T_126 = orr(pending_interrupts)
node _T_127 = or(_T_126, io.interrupts.debug)
node _T_128 = or(_T_127, exception)
when _T_128 :
connect reg_wfi, UInt<1>(0h0)
node _T_129 = bits(io.retire, 0, 0)
node _T_130 = or(_T_129, exception)
when _T_130 :
connect reg_singleStepped, UInt<1>(0h1)
node _T_131 = eq(io.singleStep, UInt<1>(0h0))
when _T_131 :
connect reg_singleStepped, UInt<1>(0h0)
node _T_132 = eq(io.singleStep, UInt<1>(0h0))
node _T_133 = leq(io.retire, UInt<1>(0h1))
node _T_134 = or(_T_132, _T_133)
node _T_135 = asUInt(reset)
node _T_136 = eq(_T_135, UInt<1>(0h0))
when _T_136 :
node _T_137 = eq(_T_134, UInt<1>(0h0))
when _T_137 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at CSR.scala:1029 assert(!io.singleStep || io.retire <= 1.U)\n") : printf_1
assert(clock, _T_134, UInt<1>(0h1), "") : assert_1
node _T_138 = eq(reg_singleStepped, UInt<1>(0h0))
node _T_139 = eq(io.retire, UInt<1>(0h0))
node _T_140 = or(_T_138, _T_139)
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at CSR.scala:1030 assert(!reg_singleStepped || io.retire === 0.U)\n") : printf_2
assert(clock, _T_140, UInt<1>(0h1), "") : assert_2
node _epc_T = not(io.pc)
node _epc_T_1 = or(_epc_T, UInt<1>(0h1))
node epc = not(_epc_T_1)
node tval = mux(insn_break, epc, io.tval)
when exception :
when trapToDebug :
node _T_144 = eq(reg_debug, UInt<1>(0h0))
when _T_144 :
connect reg_mstatus.v, UInt<1>(0h0)
connect reg_debug, UInt<1>(0h1)
connect reg_dpc, epc
node _reg_dcsr_cause_T = mux(causeIsDebugTrigger, UInt<2>(0h2), UInt<1>(0h1))
node _reg_dcsr_cause_T_1 = mux(causeIsDebugInt, UInt<2>(0h3), _reg_dcsr_cause_T)
node _reg_dcsr_cause_T_2 = mux(reg_singleStepped, UInt<3>(0h4), _reg_dcsr_cause_T_1)
connect reg_dcsr.cause, _reg_dcsr_cause_T_2
connect reg_dcsr.prv, reg_mstatus.prv
connect reg_dcsr.v, reg_mstatus.v
connect new_prv, UInt<2>(0h3)
else :
when trapToNmiInt :
when reg_rnmie :
connect reg_mstatus.v, UInt<1>(0h0)
connect reg_mnstatus.mpv, reg_mstatus.v
connect reg_rnmie, UInt<1>(0h0)
connect reg_mnepc, epc
node _reg_mncause_T = mux(causeIsRnmiBEU, UInt<2>(0h3), UInt<2>(0h2))
node _reg_mncause_T_1 = or(UInt<64>(0h8000000000000000), _reg_mncause_T)
connect reg_mncause, _reg_mncause_T_1
connect reg_mnstatus.mpp, reg_mstatus.prv
connect new_prv, UInt<2>(0h3)
else :
node _T_145 = and(delegateVS, reg_rnmie)
when _T_145 :
connect reg_mstatus.v, UInt<1>(0h1)
connect reg_vsstatus.spp, reg_mstatus.prv
connect reg_vsepc, epc
node _reg_vscause_T = bits(cause, 63, 63)
node _reg_vscause_T_1 = bits(cause, 63, 2)
node _reg_vscause_T_2 = cat(_reg_vscause_T_1, UInt<2>(0h1))
node _reg_vscause_T_3 = mux(_reg_vscause_T, _reg_vscause_T_2, cause)
connect reg_vscause, _reg_vscause_T_3
connect reg_vstval, tval
connect reg_vsstatus.spie, reg_vsstatus.sie
connect reg_vsstatus.sie, UInt<1>(0h0)
connect new_prv, UInt<1>(0h1)
else :
node _T_146 = and(delegate, reg_rnmie)
when _T_146 :
connect reg_mstatus.v, UInt<1>(0h0)
node _reg_hstatus_spvp_T = bits(reg_mstatus.prv, 0, 0)
node _reg_hstatus_spvp_T_1 = mux(reg_mstatus.v, _reg_hstatus_spvp_T, reg_hstatus.spvp)
connect reg_hstatus.spvp, _reg_hstatus_spvp_T_1
connect reg_hstatus.gva, io.gva
connect reg_hstatus.spv, reg_mstatus.v
connect reg_sepc, epc
connect reg_scause, cause
connect reg_stval, tval
connect reg_htval, io.htval
connect reg_htinst_read_pseudo, io.mhtinst_read_pseudo
connect reg_mstatus.spie, reg_mstatus.sie
connect reg_mstatus.spp, reg_mstatus.prv
connect reg_mstatus.sie, UInt<1>(0h0)
connect new_prv, UInt<1>(0h1)
else :
connect reg_mstatus.v, UInt<1>(0h0)
connect reg_mstatus.mpv, reg_mstatus.v
connect reg_mstatus.gva, io.gva
connect reg_mepc, epc
connect reg_mcause, cause
connect reg_mtval, tval
connect reg_mtval2, io.htval
connect reg_mtinst_read_pseudo, io.mhtinst_read_pseudo
connect reg_mstatus.mpie, reg_mstatus.mie
connect reg_mstatus.mpp, reg_mstatus.prv
connect reg_mstatus.mie, UInt<1>(0h0)
connect new_prv, UInt<2>(0h3)
node _en_T = and(supported_interrupts, UInt<1>(0h1))
node _en_T_1 = neq(_en_T, UInt<1>(0h0))
node _en_T_2 = and(exception, _en_T_1)
node _en_T_3 = add(UInt<64>(0h8000000000000000), UInt<1>(0h0))
node _en_T_4 = tail(_en_T_3, 1)
node _en_T_5 = eq(cause, _en_T_4)
node en = and(_en_T_2, _en_T_5)
node _delegable_T = and(delegable_interrupts, UInt<1>(0h1))
node delegable = neq(_delegable_T, UInt<1>(0h0))
node _T_147 = eq(delegate, UInt<1>(0h0))
node _T_148 = and(en, _T_147)
node _T_149 = and(en, delegable)
node _T_150 = and(_T_149, delegate)
node _en_T_6 = and(supported_interrupts, UInt<2>(0h2))
node _en_T_7 = neq(_en_T_6, UInt<1>(0h0))
node _en_T_8 = and(exception, _en_T_7)
node _en_T_9 = add(UInt<64>(0h8000000000000000), UInt<1>(0h1))
node _en_T_10 = tail(_en_T_9, 1)
node _en_T_11 = eq(cause, _en_T_10)
node en_1 = and(_en_T_8, _en_T_11)
node _delegable_T_1 = and(delegable_interrupts, UInt<2>(0h2))
node delegable_1 = neq(_delegable_T_1, UInt<1>(0h0))
node _T_151 = eq(delegate, UInt<1>(0h0))
node _T_152 = and(en_1, _T_151)
node _T_153 = and(en_1, delegable_1)
node _T_154 = and(_T_153, delegate)
node _en_T_12 = and(supported_interrupts, UInt<3>(0h4))
node _en_T_13 = neq(_en_T_12, UInt<1>(0h0))
node _en_T_14 = and(exception, _en_T_13)
node _en_T_15 = add(UInt<64>(0h8000000000000000), UInt<2>(0h2))
node _en_T_16 = tail(_en_T_15, 1)
node _en_T_17 = eq(cause, _en_T_16)
node en_2 = and(_en_T_14, _en_T_17)
node _delegable_T_2 = and(delegable_interrupts, UInt<3>(0h4))
node delegable_2 = neq(_delegable_T_2, UInt<1>(0h0))
node _T_155 = eq(delegate, UInt<1>(0h0))
node _T_156 = and(en_2, _T_155)
node _T_157 = and(en_2, delegable_2)
node _T_158 = and(_T_157, delegate)
node _en_T_18 = and(supported_interrupts, UInt<4>(0h8))
node _en_T_19 = neq(_en_T_18, UInt<1>(0h0))
node _en_T_20 = and(exception, _en_T_19)
node _en_T_21 = add(UInt<64>(0h8000000000000000), UInt<2>(0h3))
node _en_T_22 = tail(_en_T_21, 1)
node _en_T_23 = eq(cause, _en_T_22)
node en_3 = and(_en_T_20, _en_T_23)
node _delegable_T_3 = and(delegable_interrupts, UInt<4>(0h8))
node delegable_3 = neq(_delegable_T_3, UInt<1>(0h0))
node _T_159 = eq(delegate, UInt<1>(0h0))
node _T_160 = and(en_3, _T_159)
node _T_161 = and(en_3, delegable_3)
node _T_162 = and(_T_161, delegate)
node _en_T_24 = and(supported_interrupts, UInt<5>(0h10))
node _en_T_25 = neq(_en_T_24, UInt<1>(0h0))
node _en_T_26 = and(exception, _en_T_25)
node _en_T_27 = add(UInt<64>(0h8000000000000000), UInt<3>(0h4))
node _en_T_28 = tail(_en_T_27, 1)
node _en_T_29 = eq(cause, _en_T_28)
node en_4 = and(_en_T_26, _en_T_29)
node _delegable_T_4 = and(delegable_interrupts, UInt<5>(0h10))
node delegable_4 = neq(_delegable_T_4, UInt<1>(0h0))
node _T_163 = eq(delegate, UInt<1>(0h0))
node _T_164 = and(en_4, _T_163)
node _T_165 = and(en_4, delegable_4)
node _T_166 = and(_T_165, delegate)
node _en_T_30 = and(supported_interrupts, UInt<6>(0h20))
node _en_T_31 = neq(_en_T_30, UInt<1>(0h0))
node _en_T_32 = and(exception, _en_T_31)
node _en_T_33 = add(UInt<64>(0h8000000000000000), UInt<3>(0h5))
node _en_T_34 = tail(_en_T_33, 1)
node _en_T_35 = eq(cause, _en_T_34)
node en_5 = and(_en_T_32, _en_T_35)
node _delegable_T_5 = and(delegable_interrupts, UInt<6>(0h20))
node delegable_5 = neq(_delegable_T_5, UInt<1>(0h0))
node _T_167 = eq(delegate, UInt<1>(0h0))
node _T_168 = and(en_5, _T_167)
node _T_169 = and(en_5, delegable_5)
node _T_170 = and(_T_169, delegate)
node _en_T_36 = and(supported_interrupts, UInt<7>(0h40))
node _en_T_37 = neq(_en_T_36, UInt<1>(0h0))
node _en_T_38 = and(exception, _en_T_37)
node _en_T_39 = add(UInt<64>(0h8000000000000000), UInt<3>(0h6))
node _en_T_40 = tail(_en_T_39, 1)
node _en_T_41 = eq(cause, _en_T_40)
node en_6 = and(_en_T_38, _en_T_41)
node _delegable_T_6 = and(delegable_interrupts, UInt<7>(0h40))
node delegable_6 = neq(_delegable_T_6, UInt<1>(0h0))
node _T_171 = eq(delegate, UInt<1>(0h0))
node _T_172 = and(en_6, _T_171)
node _T_173 = and(en_6, delegable_6)
node _T_174 = and(_T_173, delegate)
node _en_T_42 = and(supported_interrupts, UInt<8>(0h80))
node _en_T_43 = neq(_en_T_42, UInt<1>(0h0))
node _en_T_44 = and(exception, _en_T_43)
node _en_T_45 = add(UInt<64>(0h8000000000000000), UInt<3>(0h7))
node _en_T_46 = tail(_en_T_45, 1)
node _en_T_47 = eq(cause, _en_T_46)
node en_7 = and(_en_T_44, _en_T_47)
node _delegable_T_7 = and(delegable_interrupts, UInt<8>(0h80))
node delegable_7 = neq(_delegable_T_7, UInt<1>(0h0))
node _T_175 = eq(delegate, UInt<1>(0h0))
node _T_176 = and(en_7, _T_175)
node _T_177 = and(en_7, delegable_7)
node _T_178 = and(_T_177, delegate)
node _en_T_48 = and(supported_interrupts, UInt<9>(0h100))
node _en_T_49 = neq(_en_T_48, UInt<1>(0h0))
node _en_T_50 = and(exception, _en_T_49)
node _en_T_51 = add(UInt<64>(0h8000000000000000), UInt<4>(0h8))
node _en_T_52 = tail(_en_T_51, 1)
node _en_T_53 = eq(cause, _en_T_52)
node en_8 = and(_en_T_50, _en_T_53)
node _delegable_T_8 = and(delegable_interrupts, UInt<9>(0h100))
node delegable_8 = neq(_delegable_T_8, UInt<1>(0h0))
node _T_179 = eq(delegate, UInt<1>(0h0))
node _T_180 = and(en_8, _T_179)
node _T_181 = and(en_8, delegable_8)
node _T_182 = and(_T_181, delegate)
node _en_T_54 = and(supported_interrupts, UInt<10>(0h200))
node _en_T_55 = neq(_en_T_54, UInt<1>(0h0))
node _en_T_56 = and(exception, _en_T_55)
node _en_T_57 = add(UInt<64>(0h8000000000000000), UInt<4>(0h9))
node _en_T_58 = tail(_en_T_57, 1)
node _en_T_59 = eq(cause, _en_T_58)
node en_9 = and(_en_T_56, _en_T_59)
node _delegable_T_9 = and(delegable_interrupts, UInt<10>(0h200))
node delegable_9 = neq(_delegable_T_9, UInt<1>(0h0))
node _T_183 = eq(delegate, UInt<1>(0h0))
node _T_184 = and(en_9, _T_183)
node _T_185 = and(en_9, delegable_9)
node _T_186 = and(_T_185, delegate)
node _en_T_60 = and(supported_interrupts, UInt<11>(0h400))
node _en_T_61 = neq(_en_T_60, UInt<1>(0h0))
node _en_T_62 = and(exception, _en_T_61)
node _en_T_63 = add(UInt<64>(0h8000000000000000), UInt<4>(0ha))
node _en_T_64 = tail(_en_T_63, 1)
node _en_T_65 = eq(cause, _en_T_64)
node en_10 = and(_en_T_62, _en_T_65)
node _delegable_T_10 = and(delegable_interrupts, UInt<11>(0h400))
node delegable_10 = neq(_delegable_T_10, UInt<1>(0h0))
node _T_187 = eq(delegate, UInt<1>(0h0))
node _T_188 = and(en_10, _T_187)
node _T_189 = and(en_10, delegable_10)
node _T_190 = and(_T_189, delegate)
node _en_T_66 = and(supported_interrupts, UInt<12>(0h800))
node _en_T_67 = neq(_en_T_66, UInt<1>(0h0))
node _en_T_68 = and(exception, _en_T_67)
node _en_T_69 = add(UInt<64>(0h8000000000000000), UInt<4>(0hb))
node _en_T_70 = tail(_en_T_69, 1)
node _en_T_71 = eq(cause, _en_T_70)
node en_11 = and(_en_T_68, _en_T_71)
node _delegable_T_11 = and(delegable_interrupts, UInt<12>(0h800))
node delegable_11 = neq(_delegable_T_11, UInt<1>(0h0))
node _T_191 = eq(delegate, UInt<1>(0h0))
node _T_192 = and(en_11, _T_191)
node _T_193 = and(en_11, delegable_11)
node _T_194 = and(_T_193, delegate)
node _en_T_72 = and(supported_interrupts, UInt<13>(0h1000))
node _en_T_73 = neq(_en_T_72, UInt<1>(0h0))
node _en_T_74 = and(exception, _en_T_73)
node _en_T_75 = add(UInt<64>(0h8000000000000000), UInt<4>(0hc))
node _en_T_76 = tail(_en_T_75, 1)
node _en_T_77 = eq(cause, _en_T_76)
node en_12 = and(_en_T_74, _en_T_77)
node _delegable_T_12 = and(delegable_interrupts, UInt<13>(0h1000))
node delegable_12 = neq(_delegable_T_12, UInt<1>(0h0))
node _T_195 = eq(delegate, UInt<1>(0h0))
node _T_196 = and(en_12, _T_195)
node _T_197 = and(en_12, delegable_12)
node _T_198 = and(_T_197, delegate)
node _en_T_78 = and(supported_interrupts, UInt<14>(0h2000))
node _en_T_79 = neq(_en_T_78, UInt<1>(0h0))
node _en_T_80 = and(exception, _en_T_79)
node _en_T_81 = add(UInt<64>(0h8000000000000000), UInt<4>(0hd))
node _en_T_82 = tail(_en_T_81, 1)
node _en_T_83 = eq(cause, _en_T_82)
node en_13 = and(_en_T_80, _en_T_83)
node _delegable_T_13 = and(delegable_interrupts, UInt<14>(0h2000))
node delegable_13 = neq(_delegable_T_13, UInt<1>(0h0))
node _T_199 = eq(delegate, UInt<1>(0h0))
node _T_200 = and(en_13, _T_199)
node _T_201 = and(en_13, delegable_13)
node _T_202 = and(_T_201, delegate)
node _en_T_84 = and(supported_interrupts, UInt<15>(0h4000))
node _en_T_85 = neq(_en_T_84, UInt<1>(0h0))
node _en_T_86 = and(exception, _en_T_85)
node _en_T_87 = add(UInt<64>(0h8000000000000000), UInt<4>(0he))
node _en_T_88 = tail(_en_T_87, 1)
node _en_T_89 = eq(cause, _en_T_88)
node en_14 = and(_en_T_86, _en_T_89)
node _delegable_T_14 = and(delegable_interrupts, UInt<15>(0h4000))
node delegable_14 = neq(_delegable_T_14, UInt<1>(0h0))
node _T_203 = eq(delegate, UInt<1>(0h0))
node _T_204 = and(en_14, _T_203)
node _T_205 = and(en_14, delegable_14)
node _T_206 = and(_T_205, delegate)
node _en_T_90 = and(supported_interrupts, UInt<16>(0h8000))
node _en_T_91 = neq(_en_T_90, UInt<1>(0h0))
node _en_T_92 = and(exception, _en_T_91)
node _en_T_93 = add(UInt<64>(0h8000000000000000), UInt<4>(0hf))
node _en_T_94 = tail(_en_T_93, 1)
node _en_T_95 = eq(cause, _en_T_94)
node en_15 = and(_en_T_92, _en_T_95)
node _delegable_T_15 = and(delegable_interrupts, UInt<16>(0h8000))
node delegable_15 = neq(_delegable_T_15, UInt<1>(0h0))
node _T_207 = eq(delegate, UInt<1>(0h0))
node _T_208 = and(en_15, _T_207)
node _T_209 = and(en_15, delegable_15)
node _T_210 = and(_T_209, delegate)
node _en_T_96 = eq(cause, UInt<1>(0h1))
node en_16 = and(exception, _en_T_96)
node _delegable_T_16 = and(UInt<16>(0hb15d), UInt<2>(0h2))
node delegable_16 = neq(_delegable_T_16, UInt<1>(0h0))
node _T_211 = eq(delegate, UInt<1>(0h0))
node _T_212 = and(en_16, _T_211)
node _T_213 = and(en_16, delegable_16)
node _T_214 = and(_T_213, delegate)
node _en_T_97 = eq(cause, UInt<2>(0h2))
node en_17 = and(exception, _en_T_97)
node _delegable_T_17 = and(UInt<16>(0hb15d), UInt<3>(0h4))
node delegable_17 = neq(_delegable_T_17, UInt<1>(0h0))
node _T_215 = eq(delegate, UInt<1>(0h0))
node _T_216 = and(en_17, _T_215)
node _T_217 = and(en_17, delegable_17)
node _T_218 = and(_T_217, delegate)
node _en_T_98 = eq(cause, UInt<2>(0h3))
node en_18 = and(exception, _en_T_98)
node _delegable_T_18 = and(UInt<16>(0hb15d), UInt<4>(0h8))
node delegable_18 = neq(_delegable_T_18, UInt<1>(0h0))
node _T_219 = eq(delegate, UInt<1>(0h0))
node _T_220 = and(en_18, _T_219)
node _T_221 = and(en_18, delegable_18)
node _T_222 = and(_T_221, delegate)
node _en_T_99 = eq(cause, UInt<3>(0h4))
node en_19 = and(exception, _en_T_99)
node _delegable_T_19 = and(UInt<16>(0hb15d), UInt<5>(0h10))
node delegable_19 = neq(_delegable_T_19, UInt<1>(0h0))
node _T_223 = eq(delegate, UInt<1>(0h0))
node _T_224 = and(en_19, _T_223)
node _T_225 = and(en_19, delegable_19)
node _T_226 = and(_T_225, delegate)
node _en_T_100 = eq(cause, UInt<3>(0h5))
node en_20 = and(exception, _en_T_100)
node _delegable_T_20 = and(UInt<16>(0hb15d), UInt<6>(0h20))
node delegable_20 = neq(_delegable_T_20, UInt<1>(0h0))
node _T_227 = eq(delegate, UInt<1>(0h0))
node _T_228 = and(en_20, _T_227)
node _T_229 = and(en_20, delegable_20)
node _T_230 = and(_T_229, delegate)
node _en_T_101 = eq(cause, UInt<3>(0h6))
node en_21 = and(exception, _en_T_101)
node _delegable_T_21 = and(UInt<16>(0hb15d), UInt<7>(0h40))
node delegable_21 = neq(_delegable_T_21, UInt<1>(0h0))
node _T_231 = eq(delegate, UInt<1>(0h0))
node _T_232 = and(en_21, _T_231)
node _T_233 = and(en_21, delegable_21)
node _T_234 = and(_T_233, delegate)
node _en_T_102 = eq(cause, UInt<3>(0h7))
node en_22 = and(exception, _en_T_102)
node _delegable_T_22 = and(UInt<16>(0hb15d), UInt<8>(0h80))
node delegable_22 = neq(_delegable_T_22, UInt<1>(0h0))
node _T_235 = eq(delegate, UInt<1>(0h0))
node _T_236 = and(en_22, _T_235)
node _T_237 = and(en_22, delegable_22)
node _T_238 = and(_T_237, delegate)
node _en_T_103 = eq(cause, UInt<4>(0h8))
node en_23 = and(exception, _en_T_103)
node _delegable_T_23 = and(UInt<16>(0hb15d), UInt<9>(0h100))
node delegable_23 = neq(_delegable_T_23, UInt<1>(0h0))
node _T_239 = eq(delegate, UInt<1>(0h0))
node _T_240 = and(en_23, _T_239)
node _T_241 = and(en_23, delegable_23)
node _T_242 = and(_T_241, delegate)
node _en_T_104 = eq(cause, UInt<4>(0h9))
node en_24 = and(exception, _en_T_104)
node _delegable_T_24 = and(UInt<16>(0hb15d), UInt<10>(0h200))
node delegable_24 = neq(_delegable_T_24, UInt<1>(0h0))
node _T_243 = eq(delegate, UInt<1>(0h0))
node _T_244 = and(en_24, _T_243)
node _T_245 = and(en_24, delegable_24)
node _T_246 = and(_T_245, delegate)
node _en_T_105 = eq(cause, UInt<4>(0hb))
node en_25 = and(exception, _en_T_105)
node _delegable_T_25 = and(UInt<16>(0hb15d), UInt<12>(0h800))
node delegable_25 = neq(_delegable_T_25, UInt<1>(0h0))
node _T_247 = eq(delegate, UInt<1>(0h0))
node _T_248 = and(en_25, _T_247)
node _T_249 = and(en_25, delegable_25)
node _T_250 = and(_T_249, delegate)
node _en_T_106 = eq(cause, UInt<4>(0hc))
node en_26 = and(exception, _en_T_106)
node _delegable_T_26 = and(UInt<16>(0hb15d), UInt<13>(0h1000))
node delegable_26 = neq(_delegable_T_26, UInt<1>(0h0))
node _T_251 = eq(delegate, UInt<1>(0h0))
node _T_252 = and(en_26, _T_251)
node _T_253 = and(en_26, delegable_26)
node _T_254 = and(_T_253, delegate)
node _en_T_107 = eq(cause, UInt<4>(0hd))
node en_27 = and(exception, _en_T_107)
node _delegable_T_27 = and(UInt<16>(0hb15d), UInt<14>(0h2000))
node delegable_27 = neq(_delegable_T_27, UInt<1>(0h0))
node _T_255 = eq(delegate, UInt<1>(0h0))
node _T_256 = and(en_27, _T_255)
node _T_257 = and(en_27, delegable_27)
node _T_258 = and(_T_257, delegate)
node _en_T_108 = eq(cause, UInt<4>(0hf))
node en_28 = and(exception, _en_T_108)
node _delegable_T_28 = and(UInt<16>(0hb15d), UInt<16>(0h8000))
node delegable_28 = neq(_delegable_T_28, UInt<1>(0h0))
node _T_259 = eq(delegate, UInt<1>(0h0))
node _T_260 = and(en_28, _T_259)
node _T_261 = and(en_28, delegable_28)
node _T_262 = and(_T_261, delegate)
when insn_ret :
wire ret_prv : UInt
invalidate ret_prv
node _T_263 = bits(io.rw.addr, 9, 9)
node _T_264 = eq(_T_263, UInt<1>(0h0))
node _T_265 = and(UInt<1>(0h1), _T_264)
when _T_265 :
node _T_266 = eq(reg_mstatus.v, UInt<1>(0h0))
when _T_266 :
connect reg_mstatus.sie, reg_mstatus.spie
connect reg_mstatus.spie, UInt<1>(0h1)
connect reg_mstatus.spp, UInt<1>(0h0)
connect ret_prv, reg_mstatus.spp
node _reg_mstatus_v_T = and(UInt<1>(0h0), reg_hstatus.spv)
connect reg_mstatus.v, _reg_mstatus_v_T
node _io_evec_T = not(reg_sepc)
node _io_evec_T_1 = bits(reg_misa, 2, 2)
node _io_evec_T_2 = mux(_io_evec_T_1, UInt<1>(0h1), UInt<2>(0h3))
node _io_evec_T_3 = or(_io_evec_T, _io_evec_T_2)
node _io_evec_T_4 = not(_io_evec_T_3)
connect io.evec, _io_evec_T_4
connect reg_hstatus.spv, UInt<1>(0h0)
else :
connect reg_vsstatus.sie, reg_vsstatus.spie
connect reg_vsstatus.spie, UInt<1>(0h1)
connect reg_vsstatus.spp, UInt<1>(0h0)
connect ret_prv, reg_vsstatus.spp
connect reg_mstatus.v, UInt<1>(0h0)
node _io_evec_T_5 = not(reg_vsepc)
node _io_evec_T_6 = bits(reg_misa, 2, 2)
node _io_evec_T_7 = mux(_io_evec_T_6, UInt<1>(0h1), UInt<2>(0h3))
node _io_evec_T_8 = or(_io_evec_T_5, _io_evec_T_7)
node _io_evec_T_9 = not(_io_evec_T_8)
connect io.evec, _io_evec_T_9
else :
node _T_267 = bits(io.rw.addr, 10, 10)
node _T_268 = and(UInt<1>(0h1), _T_267)
node _T_269 = bits(io.rw.addr, 7, 7)
node _T_270 = and(_T_268, _T_269)
when _T_270 :
connect ret_prv, reg_dcsr.prv
node _reg_mstatus_v_T_1 = and(UInt<1>(0h0), reg_dcsr.v)
node _reg_mstatus_v_T_2 = leq(reg_dcsr.prv, UInt<1>(0h1))
node _reg_mstatus_v_T_3 = and(_reg_mstatus_v_T_1, _reg_mstatus_v_T_2)
connect reg_mstatus.v, _reg_mstatus_v_T_3
connect reg_debug, UInt<1>(0h0)
node _io_evec_T_10 = not(reg_dpc)
node _io_evec_T_11 = bits(reg_misa, 2, 2)
node _io_evec_T_12 = mux(_io_evec_T_11, UInt<1>(0h1), UInt<2>(0h3))
node _io_evec_T_13 = or(_io_evec_T_10, _io_evec_T_12)
node _io_evec_T_14 = not(_io_evec_T_13)
connect io.evec, _io_evec_T_14
else :
node _T_271 = bits(io.rw.addr, 10, 10)
node _T_272 = and(UInt<1>(0h0), _T_271)
node _T_273 = bits(io.rw.addr, 7, 7)
node _T_274 = eq(_T_273, UInt<1>(0h0))
node _T_275 = and(_T_272, _T_274)
when _T_275 :
connect ret_prv, reg_mnstatus.mpp
node _reg_mstatus_v_T_4 = and(UInt<1>(0h0), reg_mnstatus.mpv)
node _reg_mstatus_v_T_5 = leq(reg_mnstatus.mpp, UInt<1>(0h1))
node _reg_mstatus_v_T_6 = and(_reg_mstatus_v_T_4, _reg_mstatus_v_T_5)
connect reg_mstatus.v, _reg_mstatus_v_T_6
connect reg_rnmie, UInt<1>(0h1)
node _io_evec_T_15 = not(reg_mnepc)
node _io_evec_T_16 = bits(reg_misa, 2, 2)
node _io_evec_T_17 = mux(_io_evec_T_16, UInt<1>(0h1), UInt<2>(0h3))
node _io_evec_T_18 = or(_io_evec_T_15, _io_evec_T_17)
node _io_evec_T_19 = not(_io_evec_T_18)
connect io.evec, _io_evec_T_19
else :
connect reg_mstatus.mie, reg_mstatus.mpie
connect reg_mstatus.mpie, UInt<1>(0h1)
node _reg_mstatus_mpp_T = eq(UInt<1>(0h0), UInt<2>(0h2))
node _reg_mstatus_mpp_T_1 = mux(_reg_mstatus_mpp_T, UInt<1>(0h0), UInt<1>(0h0))
connect reg_mstatus.mpp, _reg_mstatus_mpp_T_1
connect reg_mstatus.mpv, UInt<1>(0h0)
connect ret_prv, reg_mstatus.mpp
node _reg_mstatus_v_T_7 = and(UInt<1>(0h0), reg_mstatus.mpv)
node _reg_mstatus_v_T_8 = leq(reg_mstatus.mpp, UInt<1>(0h1))
node _reg_mstatus_v_T_9 = and(_reg_mstatus_v_T_7, _reg_mstatus_v_T_8)
connect reg_mstatus.v, _reg_mstatus_v_T_9
node _io_evec_T_20 = not(reg_mepc)
node _io_evec_T_21 = bits(reg_misa, 2, 2)
node _io_evec_T_22 = mux(_io_evec_T_21, UInt<1>(0h1), UInt<2>(0h3))
node _io_evec_T_23 = or(_io_evec_T_20, _io_evec_T_22)
node _io_evec_T_24 = not(_io_evec_T_23)
connect io.evec, _io_evec_T_24
connect new_prv, ret_prv
node _T_276 = leq(ret_prv, UInt<1>(0h1))
node _T_277 = and(UInt<1>(0h1), _T_276)
when _T_277 :
connect reg_mstatus.mprv, UInt<1>(0h0)
connect io.time, value_1
node _io_csr_stall_T = or(reg_wfi, io.status.cease)
connect io.csr_stall, _io_csr_stall_T
regreset io_status_cease_r : UInt<1>, clock, reset, UInt<1>(0h0)
when insn_cease :
connect io_status_cease_r, UInt<1>(0h1)
connect io.status.cease, io_status_cease_r
connect io.status.wfi, reg_wfi
connect io.customCSRs[0].wen, UInt<1>(0h0)
connect io.customCSRs[0].wdata, wdata
connect io.customCSRs[0].value, reg_custom_0
connect io.customCSRs[1].wen, UInt<1>(0h0)
connect io.customCSRs[1].wdata, wdata
connect io.customCSRs[1].value, reg_custom_1
connect io.customCSRs[2].wen, UInt<1>(0h0)
connect io.customCSRs[2].wdata, wdata
connect io.customCSRs[2].value, reg_custom_2
connect io.customCSRs[3].wen, UInt<1>(0h0)
connect io.customCSRs[3].wdata, wdata
connect io.customCSRs[3].value, reg_custom_3
node _io_rw_rdata_T = mux(decoded_addr_98_2, reg_tselect, UInt<1>(0h0))
node _io_rw_rdata_T_1 = mux(decoded_addr_55_2, read_mapping_1_2, UInt<1>(0h0))
node _io_rw_rdata_T_2 = mux(decoded_addr_10_2, read_mapping_2_2, UInt<1>(0h0))
node _io_rw_rdata_T_3 = mux(decoded_addr_120_2, read_mapping_3_2, UInt<1>(0h0))
node _io_rw_rdata_T_4 = mux(decoded_addr_95_2, reg_misa, UInt<1>(0h0))
node _io_rw_rdata_T_5 = mux(decoded_addr_101_2, read_mstatus, UInt<1>(0h0))
node _io_rw_rdata_T_6 = mux(decoded_addr_72_2, read_mtvec, UInt<1>(0h0))
node _io_rw_rdata_T_7 = mux(decoded_addr_109_2, read_mip, UInt<1>(0h0))
node _io_rw_rdata_T_8 = mux(decoded_addr_77_2, reg_mie, UInt<1>(0h0))
node _io_rw_rdata_T_9 = mux(decoded_addr_131_2, reg_mscratch, UInt<1>(0h0))
node _io_rw_rdata_T_10 = mux(decoded_addr_134_2, read_mapping_10_2, UInt<1>(0h0))
node _io_rw_rdata_T_11 = mux(decoded_addr_138_2, read_mapping_11_2, UInt<1>(0h0))
node _io_rw_rdata_T_12 = mux(decoded_addr_29_2, reg_mcause, UInt<1>(0h0))
node _io_rw_rdata_T_13 = mux(decoded_addr_133_2, io.hartid, UInt<1>(0h0))
node _io_rw_rdata_T_14 = mux(decoded_addr_49_2, debug_csrs_0_2, UInt<1>(0h0))
node _io_rw_rdata_T_15 = mux(decoded_addr_90_2, debug_csrs_1_2, UInt<1>(0h0))
node _io_rw_rdata_T_16 = mux(decoded_addr_57_2, reg_dscratch0, UInt<1>(0h0))
node _io_rw_rdata_T_17 = mux(decoded_addr_36_2, reg_fflags, UInt<1>(0h0))
node _io_rw_rdata_T_18 = mux(decoded_addr_68_2, reg_frm, UInt<1>(0h0))
node _io_rw_rdata_T_19 = mux(decoded_addr_100_2, read_fcsr, UInt<1>(0h0))
node _io_rw_rdata_T_20 = mux(decoded_addr_132_2, reg_mcountinhibit, UInt<1>(0h0))
node _io_rw_rdata_T_21 = mux(decoded_addr_104_2, value_1, UInt<1>(0h0))
node _io_rw_rdata_T_22 = mux(decoded_addr_123_2, value, UInt<1>(0h0))
node _io_rw_rdata_T_23 = mux(decoded_addr_148_2, reg_hpmevent_0, UInt<1>(0h0))
node _io_rw_rdata_T_24 = mux(decoded_addr_17_2, value_2, UInt<1>(0h0))
node _io_rw_rdata_T_25 = mux(decoded_addr_27_2, value_2, UInt<1>(0h0))
node _io_rw_rdata_T_26 = mux(decoded_addr_84_2, reg_hpmevent_1, UInt<1>(0h0))
node _io_rw_rdata_T_27 = mux(decoded_addr_52_2, value_3, UInt<1>(0h0))
node _io_rw_rdata_T_28 = mux(decoded_addr_146_2, value_3, UInt<1>(0h0))
node _io_rw_rdata_T_29 = mux(decoded_addr_70_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_30 = mux(decoded_addr_112_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_31 = mux(decoded_addr_83_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_32 = mux(decoded_addr_31_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_33 = mux(decoded_addr_0_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_34 = mux(decoded_addr_59_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_35 = mux(decoded_addr_140_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_36 = mux(decoded_addr_128_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_37 = mux(decoded_addr_74_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_38 = mux(decoded_addr_117_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_39 = mux(decoded_addr_91_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_40 = mux(decoded_addr_114_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_41 = mux(decoded_addr_1_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_42 = mux(decoded_addr_16_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_43 = mux(decoded_addr_79_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_44 = mux(decoded_addr_39_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_45 = mux(decoded_addr_51_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_46 = mux(decoded_addr_110_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_47 = mux(decoded_addr_92_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_48 = mux(decoded_addr_82_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_49 = mux(decoded_addr_67_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_50 = mux(decoded_addr_106_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_51 = mux(decoded_addr_124_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_52 = mux(decoded_addr_24_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_53 = mux(decoded_addr_126_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_54 = mux(decoded_addr_26_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_55 = mux(decoded_addr_130_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_56 = mux(decoded_addr_7_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_57 = mux(decoded_addr_62_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_58 = mux(decoded_addr_78_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_59 = mux(decoded_addr_46_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_60 = mux(decoded_addr_113_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_61 = mux(decoded_addr_60_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_62 = mux(decoded_addr_93_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_63 = mux(decoded_addr_150_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_64 = mux(decoded_addr_14_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_65 = mux(decoded_addr_21_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_66 = mux(decoded_addr_33_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_67 = mux(decoded_addr_19_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_68 = mux(decoded_addr_135_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_69 = mux(decoded_addr_151_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_70 = mux(decoded_addr_50_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_71 = mux(decoded_addr_75_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_72 = mux(decoded_addr_103_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_73 = mux(decoded_addr_85_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_74 = mux(decoded_addr_45_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_75 = mux(decoded_addr_64_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_76 = mux(decoded_addr_122_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_77 = mux(decoded_addr_30_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_78 = mux(decoded_addr_5_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_79 = mux(decoded_addr_32_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_80 = mux(decoded_addr_145_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_81 = mux(decoded_addr_119_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_82 = mux(decoded_addr_63_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_83 = mux(decoded_addr_108_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_84 = mux(decoded_addr_89_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_85 = mux(decoded_addr_115_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_86 = mux(decoded_addr_73_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_87 = mux(decoded_addr_53_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_88 = mux(decoded_addr_149_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_89 = mux(decoded_addr_41_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_90 = mux(decoded_addr_56_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_91 = mux(decoded_addr_37_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_92 = mux(decoded_addr_80_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_93 = mux(decoded_addr_97_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_94 = mux(decoded_addr_4_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_95 = mux(decoded_addr_102_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_96 = mux(decoded_addr_121_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_97 = mux(decoded_addr_22_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_98 = mux(decoded_addr_141_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_99 = mux(decoded_addr_11_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_100 = mux(decoded_addr_136_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_101 = mux(decoded_addr_12_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_102 = mux(decoded_addr_65_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_103 = mux(decoded_addr_87_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_104 = mux(decoded_addr_47_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_105 = mux(decoded_addr_107_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_106 = mux(decoded_addr_58_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_107 = mux(decoded_addr_88_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_108 = mux(decoded_addr_144_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_109 = mux(decoded_addr_13_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_110 = mux(decoded_addr_35_2, read_mcounteren, UInt<1>(0h0))
node _io_rw_rdata_T_111 = mux(decoded_addr_2_2, value_1, UInt<1>(0h0))
node _io_rw_rdata_T_112 = mux(decoded_addr_66_2, value, UInt<1>(0h0))
node _io_rw_rdata_T_113 = mux(decoded_addr_42_2, _T_23, UInt<1>(0h0))
node _io_rw_rdata_T_114 = mux(decoded_addr_61_2, _T_25, UInt<1>(0h0))
node _io_rw_rdata_T_115 = mux(decoded_addr_48_2, read_sip, UInt<1>(0h0))
node _io_rw_rdata_T_116 = mux(decoded_addr_44_2, read_sie, UInt<1>(0h0))
node _io_rw_rdata_T_117 = mux(decoded_addr_15_2, reg_sscratch, UInt<1>(0h0))
node _io_rw_rdata_T_118 = mux(decoded_addr_147_2, reg_scause, UInt<1>(0h0))
node _io_rw_rdata_T_119 = mux(decoded_addr_94_2, _T_28, UInt<1>(0h0))
node _io_rw_rdata_T_120 = mux(decoded_addr_6_2, _T_29, UInt<1>(0h0))
node _io_rw_rdata_T_121 = mux(decoded_addr_28_2, _T_37, UInt<1>(0h0))
node _io_rw_rdata_T_122 = mux(decoded_addr_25_2, read_stvec, UInt<1>(0h0))
node _io_rw_rdata_T_123 = mux(decoded_addr_139_2, read_scounteren, UInt<1>(0h0))
node _io_rw_rdata_T_124 = mux(decoded_addr_125_2, read_mideleg, UInt<1>(0h0))
node _io_rw_rdata_T_125 = mux(decoded_addr_23_2, read_medeleg, UInt<1>(0h0))
node _io_rw_rdata_T_126 = mux(decoded_addr_69_2, _T_38, UInt<1>(0h0))
node _io_rw_rdata_T_127 = mux(decoded_addr_143_2, _T_47, UInt<1>(0h0))
node _io_rw_rdata_T_128 = mux(decoded_addr_9_2, _T_56, UInt<1>(0h0))
node _io_rw_rdata_T_129 = mux(decoded_addr_105_2, reg_pmp[0].addr, UInt<1>(0h0))
node _io_rw_rdata_T_130 = mux(decoded_addr_8_2, reg_pmp[1].addr, UInt<1>(0h0))
node _io_rw_rdata_T_131 = mux(decoded_addr_127_2, reg_pmp[2].addr, UInt<1>(0h0))
node _io_rw_rdata_T_132 = mux(decoded_addr_86_2, reg_pmp[3].addr, UInt<1>(0h0))
node _io_rw_rdata_T_133 = mux(decoded_addr_54_2, reg_pmp[4].addr, UInt<1>(0h0))
node _io_rw_rdata_T_134 = mux(decoded_addr_20_2, reg_pmp[5].addr, UInt<1>(0h0))
node _io_rw_rdata_T_135 = mux(decoded_addr_137_2, reg_pmp[6].addr, UInt<1>(0h0))
node _io_rw_rdata_T_136 = mux(decoded_addr_116_2, reg_pmp[7].addr, UInt<1>(0h0))
node _io_rw_rdata_T_137 = mux(decoded_addr_43_2, read_pmp_15.addr, UInt<1>(0h0))
node _io_rw_rdata_T_138 = mux(decoded_addr_71_2, read_pmp_15.addr, UInt<1>(0h0))
node _io_rw_rdata_T_139 = mux(decoded_addr_111_2, read_pmp_15.addr, UInt<1>(0h0))
node _io_rw_rdata_T_140 = mux(decoded_addr_142_2, read_pmp_15.addr, UInt<1>(0h0))
node _io_rw_rdata_T_141 = mux(decoded_addr_34_2, read_pmp_15.addr, UInt<1>(0h0))
node _io_rw_rdata_T_142 = mux(decoded_addr_40_2, read_pmp_15.addr, UInt<1>(0h0))
node _io_rw_rdata_T_143 = mux(decoded_addr_81_2, read_pmp_15.addr, UInt<1>(0h0))
node _io_rw_rdata_T_144 = mux(decoded_addr_99_2, read_pmp_15.addr, UInt<1>(0h0))
node _io_rw_rdata_T_145 = mux(decoded_addr_76_2, reg_custom_0, UInt<1>(0h0))
node _io_rw_rdata_T_146 = mux(decoded_addr_118_2, reg_custom_1, UInt<1>(0h0))
node _io_rw_rdata_T_147 = mux(decoded_addr_18_2, reg_custom_2, UInt<1>(0h0))
node _io_rw_rdata_T_148 = mux(decoded_addr_3_2, reg_custom_3, UInt<1>(0h0))
node _io_rw_rdata_T_149 = mux(decoded_addr_129_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_150 = mux(decoded_addr_38_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_151 = mux(decoded_addr_96_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_152 = or(_io_rw_rdata_T, _io_rw_rdata_T_1)
node _io_rw_rdata_T_153 = or(_io_rw_rdata_T_152, _io_rw_rdata_T_2)
node _io_rw_rdata_T_154 = or(_io_rw_rdata_T_153, _io_rw_rdata_T_3)
node _io_rw_rdata_T_155 = or(_io_rw_rdata_T_154, _io_rw_rdata_T_4)
node _io_rw_rdata_T_156 = or(_io_rw_rdata_T_155, _io_rw_rdata_T_5)
node _io_rw_rdata_T_157 = or(_io_rw_rdata_T_156, _io_rw_rdata_T_6)
node _io_rw_rdata_T_158 = or(_io_rw_rdata_T_157, _io_rw_rdata_T_7)
node _io_rw_rdata_T_159 = or(_io_rw_rdata_T_158, _io_rw_rdata_T_8)
node _io_rw_rdata_T_160 = or(_io_rw_rdata_T_159, _io_rw_rdata_T_9)
node _io_rw_rdata_T_161 = or(_io_rw_rdata_T_160, _io_rw_rdata_T_10)
node _io_rw_rdata_T_162 = or(_io_rw_rdata_T_161, _io_rw_rdata_T_11)
node _io_rw_rdata_T_163 = or(_io_rw_rdata_T_162, _io_rw_rdata_T_12)
node _io_rw_rdata_T_164 = or(_io_rw_rdata_T_163, _io_rw_rdata_T_13)
node _io_rw_rdata_T_165 = or(_io_rw_rdata_T_164, _io_rw_rdata_T_14)
node _io_rw_rdata_T_166 = or(_io_rw_rdata_T_165, _io_rw_rdata_T_15)
node _io_rw_rdata_T_167 = or(_io_rw_rdata_T_166, _io_rw_rdata_T_16)
node _io_rw_rdata_T_168 = or(_io_rw_rdata_T_167, _io_rw_rdata_T_17)
node _io_rw_rdata_T_169 = or(_io_rw_rdata_T_168, _io_rw_rdata_T_18)
node _io_rw_rdata_T_170 = or(_io_rw_rdata_T_169, _io_rw_rdata_T_19)
node _io_rw_rdata_T_171 = or(_io_rw_rdata_T_170, _io_rw_rdata_T_20)
node _io_rw_rdata_T_172 = or(_io_rw_rdata_T_171, _io_rw_rdata_T_21)
node _io_rw_rdata_T_173 = or(_io_rw_rdata_T_172, _io_rw_rdata_T_22)
node _io_rw_rdata_T_174 = or(_io_rw_rdata_T_173, _io_rw_rdata_T_23)
node _io_rw_rdata_T_175 = or(_io_rw_rdata_T_174, _io_rw_rdata_T_24)
node _io_rw_rdata_T_176 = or(_io_rw_rdata_T_175, _io_rw_rdata_T_25)
node _io_rw_rdata_T_177 = or(_io_rw_rdata_T_176, _io_rw_rdata_T_26)
node _io_rw_rdata_T_178 = or(_io_rw_rdata_T_177, _io_rw_rdata_T_27)
node _io_rw_rdata_T_179 = or(_io_rw_rdata_T_178, _io_rw_rdata_T_28)
node _io_rw_rdata_T_180 = or(_io_rw_rdata_T_179, _io_rw_rdata_T_29)
node _io_rw_rdata_T_181 = or(_io_rw_rdata_T_180, _io_rw_rdata_T_30)
node _io_rw_rdata_T_182 = or(_io_rw_rdata_T_181, _io_rw_rdata_T_31)
node _io_rw_rdata_T_183 = or(_io_rw_rdata_T_182, _io_rw_rdata_T_32)
node _io_rw_rdata_T_184 = or(_io_rw_rdata_T_183, _io_rw_rdata_T_33)
node _io_rw_rdata_T_185 = or(_io_rw_rdata_T_184, _io_rw_rdata_T_34)
node _io_rw_rdata_T_186 = or(_io_rw_rdata_T_185, _io_rw_rdata_T_35)
node _io_rw_rdata_T_187 = or(_io_rw_rdata_T_186, _io_rw_rdata_T_36)
node _io_rw_rdata_T_188 = or(_io_rw_rdata_T_187, _io_rw_rdata_T_37)
node _io_rw_rdata_T_189 = or(_io_rw_rdata_T_188, _io_rw_rdata_T_38)
node _io_rw_rdata_T_190 = or(_io_rw_rdata_T_189, _io_rw_rdata_T_39)
node _io_rw_rdata_T_191 = or(_io_rw_rdata_T_190, _io_rw_rdata_T_40)
node _io_rw_rdata_T_192 = or(_io_rw_rdata_T_191, _io_rw_rdata_T_41)
node _io_rw_rdata_T_193 = or(_io_rw_rdata_T_192, _io_rw_rdata_T_42)
node _io_rw_rdata_T_194 = or(_io_rw_rdata_T_193, _io_rw_rdata_T_43)
node _io_rw_rdata_T_195 = or(_io_rw_rdata_T_194, _io_rw_rdata_T_44)
node _io_rw_rdata_T_196 = or(_io_rw_rdata_T_195, _io_rw_rdata_T_45)
node _io_rw_rdata_T_197 = or(_io_rw_rdata_T_196, _io_rw_rdata_T_46)
node _io_rw_rdata_T_198 = or(_io_rw_rdata_T_197, _io_rw_rdata_T_47)
node _io_rw_rdata_T_199 = or(_io_rw_rdata_T_198, _io_rw_rdata_T_48)
node _io_rw_rdata_T_200 = or(_io_rw_rdata_T_199, _io_rw_rdata_T_49)
node _io_rw_rdata_T_201 = or(_io_rw_rdata_T_200, _io_rw_rdata_T_50)
node _io_rw_rdata_T_202 = or(_io_rw_rdata_T_201, _io_rw_rdata_T_51)
node _io_rw_rdata_T_203 = or(_io_rw_rdata_T_202, _io_rw_rdata_T_52)
node _io_rw_rdata_T_204 = or(_io_rw_rdata_T_203, _io_rw_rdata_T_53)
node _io_rw_rdata_T_205 = or(_io_rw_rdata_T_204, _io_rw_rdata_T_54)
node _io_rw_rdata_T_206 = or(_io_rw_rdata_T_205, _io_rw_rdata_T_55)
node _io_rw_rdata_T_207 = or(_io_rw_rdata_T_206, _io_rw_rdata_T_56)
node _io_rw_rdata_T_208 = or(_io_rw_rdata_T_207, _io_rw_rdata_T_57)
node _io_rw_rdata_T_209 = or(_io_rw_rdata_T_208, _io_rw_rdata_T_58)
node _io_rw_rdata_T_210 = or(_io_rw_rdata_T_209, _io_rw_rdata_T_59)
node _io_rw_rdata_T_211 = or(_io_rw_rdata_T_210, _io_rw_rdata_T_60)
node _io_rw_rdata_T_212 = or(_io_rw_rdata_T_211, _io_rw_rdata_T_61)
node _io_rw_rdata_T_213 = or(_io_rw_rdata_T_212, _io_rw_rdata_T_62)
node _io_rw_rdata_T_214 = or(_io_rw_rdata_T_213, _io_rw_rdata_T_63)
node _io_rw_rdata_T_215 = or(_io_rw_rdata_T_214, _io_rw_rdata_T_64)
node _io_rw_rdata_T_216 = or(_io_rw_rdata_T_215, _io_rw_rdata_T_65)
node _io_rw_rdata_T_217 = or(_io_rw_rdata_T_216, _io_rw_rdata_T_66)
node _io_rw_rdata_T_218 = or(_io_rw_rdata_T_217, _io_rw_rdata_T_67)
node _io_rw_rdata_T_219 = or(_io_rw_rdata_T_218, _io_rw_rdata_T_68)
node _io_rw_rdata_T_220 = or(_io_rw_rdata_T_219, _io_rw_rdata_T_69)
node _io_rw_rdata_T_221 = or(_io_rw_rdata_T_220, _io_rw_rdata_T_70)
node _io_rw_rdata_T_222 = or(_io_rw_rdata_T_221, _io_rw_rdata_T_71)
node _io_rw_rdata_T_223 = or(_io_rw_rdata_T_222, _io_rw_rdata_T_72)
node _io_rw_rdata_T_224 = or(_io_rw_rdata_T_223, _io_rw_rdata_T_73)
node _io_rw_rdata_T_225 = or(_io_rw_rdata_T_224, _io_rw_rdata_T_74)
node _io_rw_rdata_T_226 = or(_io_rw_rdata_T_225, _io_rw_rdata_T_75)
node _io_rw_rdata_T_227 = or(_io_rw_rdata_T_226, _io_rw_rdata_T_76)
node _io_rw_rdata_T_228 = or(_io_rw_rdata_T_227, _io_rw_rdata_T_77)
node _io_rw_rdata_T_229 = or(_io_rw_rdata_T_228, _io_rw_rdata_T_78)
node _io_rw_rdata_T_230 = or(_io_rw_rdata_T_229, _io_rw_rdata_T_79)
node _io_rw_rdata_T_231 = or(_io_rw_rdata_T_230, _io_rw_rdata_T_80)
node _io_rw_rdata_T_232 = or(_io_rw_rdata_T_231, _io_rw_rdata_T_81)
node _io_rw_rdata_T_233 = or(_io_rw_rdata_T_232, _io_rw_rdata_T_82)
node _io_rw_rdata_T_234 = or(_io_rw_rdata_T_233, _io_rw_rdata_T_83)
node _io_rw_rdata_T_235 = or(_io_rw_rdata_T_234, _io_rw_rdata_T_84)
node _io_rw_rdata_T_236 = or(_io_rw_rdata_T_235, _io_rw_rdata_T_85)
node _io_rw_rdata_T_237 = or(_io_rw_rdata_T_236, _io_rw_rdata_T_86)
node _io_rw_rdata_T_238 = or(_io_rw_rdata_T_237, _io_rw_rdata_T_87)
node _io_rw_rdata_T_239 = or(_io_rw_rdata_T_238, _io_rw_rdata_T_88)
node _io_rw_rdata_T_240 = or(_io_rw_rdata_T_239, _io_rw_rdata_T_89)
node _io_rw_rdata_T_241 = or(_io_rw_rdata_T_240, _io_rw_rdata_T_90)
node _io_rw_rdata_T_242 = or(_io_rw_rdata_T_241, _io_rw_rdata_T_91)
node _io_rw_rdata_T_243 = or(_io_rw_rdata_T_242, _io_rw_rdata_T_92)
node _io_rw_rdata_T_244 = or(_io_rw_rdata_T_243, _io_rw_rdata_T_93)
node _io_rw_rdata_T_245 = or(_io_rw_rdata_T_244, _io_rw_rdata_T_94)
node _io_rw_rdata_T_246 = or(_io_rw_rdata_T_245, _io_rw_rdata_T_95)
node _io_rw_rdata_T_247 = or(_io_rw_rdata_T_246, _io_rw_rdata_T_96)
node _io_rw_rdata_T_248 = or(_io_rw_rdata_T_247, _io_rw_rdata_T_97)
node _io_rw_rdata_T_249 = or(_io_rw_rdata_T_248, _io_rw_rdata_T_98)
node _io_rw_rdata_T_250 = or(_io_rw_rdata_T_249, _io_rw_rdata_T_99)
node _io_rw_rdata_T_251 = or(_io_rw_rdata_T_250, _io_rw_rdata_T_100)
node _io_rw_rdata_T_252 = or(_io_rw_rdata_T_251, _io_rw_rdata_T_101)
node _io_rw_rdata_T_253 = or(_io_rw_rdata_T_252, _io_rw_rdata_T_102)
node _io_rw_rdata_T_254 = or(_io_rw_rdata_T_253, _io_rw_rdata_T_103)
node _io_rw_rdata_T_255 = or(_io_rw_rdata_T_254, _io_rw_rdata_T_104)
node _io_rw_rdata_T_256 = or(_io_rw_rdata_T_255, _io_rw_rdata_T_105)
node _io_rw_rdata_T_257 = or(_io_rw_rdata_T_256, _io_rw_rdata_T_106)
node _io_rw_rdata_T_258 = or(_io_rw_rdata_T_257, _io_rw_rdata_T_107)
node _io_rw_rdata_T_259 = or(_io_rw_rdata_T_258, _io_rw_rdata_T_108)
node _io_rw_rdata_T_260 = or(_io_rw_rdata_T_259, _io_rw_rdata_T_109)
node _io_rw_rdata_T_261 = or(_io_rw_rdata_T_260, _io_rw_rdata_T_110)
node _io_rw_rdata_T_262 = or(_io_rw_rdata_T_261, _io_rw_rdata_T_111)
node _io_rw_rdata_T_263 = or(_io_rw_rdata_T_262, _io_rw_rdata_T_112)
node _io_rw_rdata_T_264 = or(_io_rw_rdata_T_263, _io_rw_rdata_T_113)
node _io_rw_rdata_T_265 = or(_io_rw_rdata_T_264, _io_rw_rdata_T_114)
node _io_rw_rdata_T_266 = or(_io_rw_rdata_T_265, _io_rw_rdata_T_115)
node _io_rw_rdata_T_267 = or(_io_rw_rdata_T_266, _io_rw_rdata_T_116)
node _io_rw_rdata_T_268 = or(_io_rw_rdata_T_267, _io_rw_rdata_T_117)
node _io_rw_rdata_T_269 = or(_io_rw_rdata_T_268, _io_rw_rdata_T_118)
node _io_rw_rdata_T_270 = or(_io_rw_rdata_T_269, _io_rw_rdata_T_119)
node _io_rw_rdata_T_271 = or(_io_rw_rdata_T_270, _io_rw_rdata_T_120)
node _io_rw_rdata_T_272 = or(_io_rw_rdata_T_271, _io_rw_rdata_T_121)
node _io_rw_rdata_T_273 = or(_io_rw_rdata_T_272, _io_rw_rdata_T_122)
node _io_rw_rdata_T_274 = or(_io_rw_rdata_T_273, _io_rw_rdata_T_123)
node _io_rw_rdata_T_275 = or(_io_rw_rdata_T_274, _io_rw_rdata_T_124)
node _io_rw_rdata_T_276 = or(_io_rw_rdata_T_275, _io_rw_rdata_T_125)
node _io_rw_rdata_T_277 = or(_io_rw_rdata_T_276, _io_rw_rdata_T_126)
node _io_rw_rdata_T_278 = or(_io_rw_rdata_T_277, _io_rw_rdata_T_127)
node _io_rw_rdata_T_279 = or(_io_rw_rdata_T_278, _io_rw_rdata_T_128)
node _io_rw_rdata_T_280 = or(_io_rw_rdata_T_279, _io_rw_rdata_T_129)
node _io_rw_rdata_T_281 = or(_io_rw_rdata_T_280, _io_rw_rdata_T_130)
node _io_rw_rdata_T_282 = or(_io_rw_rdata_T_281, _io_rw_rdata_T_131)
node _io_rw_rdata_T_283 = or(_io_rw_rdata_T_282, _io_rw_rdata_T_132)
node _io_rw_rdata_T_284 = or(_io_rw_rdata_T_283, _io_rw_rdata_T_133)
node _io_rw_rdata_T_285 = or(_io_rw_rdata_T_284, _io_rw_rdata_T_134)
node _io_rw_rdata_T_286 = or(_io_rw_rdata_T_285, _io_rw_rdata_T_135)
node _io_rw_rdata_T_287 = or(_io_rw_rdata_T_286, _io_rw_rdata_T_136)
node _io_rw_rdata_T_288 = or(_io_rw_rdata_T_287, _io_rw_rdata_T_137)
node _io_rw_rdata_T_289 = or(_io_rw_rdata_T_288, _io_rw_rdata_T_138)
node _io_rw_rdata_T_290 = or(_io_rw_rdata_T_289, _io_rw_rdata_T_139)
node _io_rw_rdata_T_291 = or(_io_rw_rdata_T_290, _io_rw_rdata_T_140)
node _io_rw_rdata_T_292 = or(_io_rw_rdata_T_291, _io_rw_rdata_T_141)
node _io_rw_rdata_T_293 = or(_io_rw_rdata_T_292, _io_rw_rdata_T_142)
node _io_rw_rdata_T_294 = or(_io_rw_rdata_T_293, _io_rw_rdata_T_143)
node _io_rw_rdata_T_295 = or(_io_rw_rdata_T_294, _io_rw_rdata_T_144)
node _io_rw_rdata_T_296 = or(_io_rw_rdata_T_295, _io_rw_rdata_T_145)
node _io_rw_rdata_T_297 = or(_io_rw_rdata_T_296, _io_rw_rdata_T_146)
node _io_rw_rdata_T_298 = or(_io_rw_rdata_T_297, _io_rw_rdata_T_147)
node _io_rw_rdata_T_299 = or(_io_rw_rdata_T_298, _io_rw_rdata_T_148)
node _io_rw_rdata_T_300 = or(_io_rw_rdata_T_299, _io_rw_rdata_T_149)
node _io_rw_rdata_T_301 = or(_io_rw_rdata_T_300, _io_rw_rdata_T_150)
node _io_rw_rdata_T_302 = or(_io_rw_rdata_T_301, _io_rw_rdata_T_151)
wire _io_rw_rdata_WIRE : UInt
connect _io_rw_rdata_WIRE, _io_rw_rdata_T_302
connect io.rw.rdata, _io_rw_rdata_WIRE
node _T_278 = andr(UInt<2>(0h1))
node _T_279 = eq(_T_278, UInt<1>(0h0))
when _T_279 :
node _T_280 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_281 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_282 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_283 = or(_T_280, _T_281)
node _T_284 = or(_T_283, _T_282)
node _T_285 = eq(io.rw.addr, UInt<11>(0h7a0))
node _T_286 = and(_T_284, _T_285)
else :
node _T_287 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_288 = eq(io.rw.addr, UInt<11>(0h7a0))
node _T_289 = and(_T_287, _T_288)
node _T_290 = andr(UInt<2>(0h1))
node _T_291 = eq(_T_290, UInt<1>(0h0))
when _T_291 :
node _T_292 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_293 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_294 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_295 = or(_T_292, _T_293)
node _T_296 = or(_T_295, _T_294)
node _T_297 = eq(io.rw.addr, UInt<11>(0h7a1))
node _T_298 = and(_T_296, _T_297)
else :
node _T_299 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_300 = eq(io.rw.addr, UInt<11>(0h7a1))
node _T_301 = and(_T_299, _T_300)
node _T_302 = andr(UInt<2>(0h1))
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_305 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_306 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_307 = or(_T_304, _T_305)
node _T_308 = or(_T_307, _T_306)
node _T_309 = eq(io.rw.addr, UInt<11>(0h7a2))
node _T_310 = and(_T_308, _T_309)
else :
node _T_311 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_312 = eq(io.rw.addr, UInt<11>(0h7a2))
node _T_313 = and(_T_311, _T_312)
node _T_314 = andr(UInt<2>(0h1))
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_317 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_318 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_319 = or(_T_316, _T_317)
node _T_320 = or(_T_319, _T_318)
node _T_321 = eq(io.rw.addr, UInt<11>(0h7a3))
node _T_322 = and(_T_320, _T_321)
else :
node _T_323 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_324 = eq(io.rw.addr, UInt<11>(0h7a3))
node _T_325 = and(_T_323, _T_324)
node _T_326 = andr(UInt<2>(0h0))
node _T_327 = eq(_T_326, UInt<1>(0h0))
when _T_327 :
node _T_328 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_329 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_330 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_331 = or(_T_328, _T_329)
node _T_332 = or(_T_331, _T_330)
node _T_333 = eq(io.rw.addr, UInt<10>(0h301))
node _T_334 = and(_T_332, _T_333)
else :
node _T_335 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_336 = eq(io.rw.addr, UInt<10>(0h301))
node _T_337 = and(_T_335, _T_336)
node _T_338 = andr(UInt<2>(0h0))
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_341 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_342 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_343 = or(_T_340, _T_341)
node _T_344 = or(_T_343, _T_342)
node _T_345 = eq(io.rw.addr, UInt<10>(0h300))
node _T_346 = and(_T_344, _T_345)
else :
node _T_347 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_348 = eq(io.rw.addr, UInt<10>(0h300))
node _T_349 = and(_T_347, _T_348)
node _T_350 = andr(UInt<2>(0h0))
node _T_351 = eq(_T_350, UInt<1>(0h0))
when _T_351 :
node _T_352 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_353 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_354 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_355 = or(_T_352, _T_353)
node _T_356 = or(_T_355, _T_354)
node _T_357 = eq(io.rw.addr, UInt<10>(0h305))
node _T_358 = and(_T_356, _T_357)
else :
node _T_359 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_360 = eq(io.rw.addr, UInt<10>(0h305))
node _T_361 = and(_T_359, _T_360)
node _T_362 = andr(UInt<2>(0h0))
node _T_363 = eq(_T_362, UInt<1>(0h0))
when _T_363 :
node _T_364 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_365 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_366 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_367 = or(_T_364, _T_365)
node _T_368 = or(_T_367, _T_366)
node _T_369 = eq(io.rw.addr, UInt<10>(0h344))
node _T_370 = and(_T_368, _T_369)
else :
node _T_371 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_372 = eq(io.rw.addr, UInt<10>(0h344))
node _T_373 = and(_T_371, _T_372)
node _T_374 = andr(UInt<2>(0h0))
node _T_375 = eq(_T_374, UInt<1>(0h0))
when _T_375 :
node _T_376 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_377 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_378 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_379 = or(_T_376, _T_377)
node _T_380 = or(_T_379, _T_378)
node _T_381 = eq(io.rw.addr, UInt<10>(0h304))
node _T_382 = and(_T_380, _T_381)
else :
node _T_383 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_384 = eq(io.rw.addr, UInt<10>(0h304))
node _T_385 = and(_T_383, _T_384)
node _T_386 = andr(UInt<2>(0h0))
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_389 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_390 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_391 = or(_T_388, _T_389)
node _T_392 = or(_T_391, _T_390)
node _T_393 = eq(io.rw.addr, UInt<10>(0h340))
node _T_394 = and(_T_392, _T_393)
else :
node _T_395 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_396 = eq(io.rw.addr, UInt<10>(0h340))
node _T_397 = and(_T_395, _T_396)
node _T_398 = andr(UInt<2>(0h0))
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_401 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_402 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_403 = or(_T_400, _T_401)
node _T_404 = or(_T_403, _T_402)
node _T_405 = eq(io.rw.addr, UInt<10>(0h341))
node _T_406 = and(_T_404, _T_405)
else :
node _T_407 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_408 = eq(io.rw.addr, UInt<10>(0h341))
node _T_409 = and(_T_407, _T_408)
node _T_410 = andr(UInt<2>(0h0))
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_413 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_414 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_415 = or(_T_412, _T_413)
node _T_416 = or(_T_415, _T_414)
node _T_417 = eq(io.rw.addr, UInt<10>(0h343))
node _T_418 = and(_T_416, _T_417)
else :
node _T_419 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_420 = eq(io.rw.addr, UInt<10>(0h343))
node _T_421 = and(_T_419, _T_420)
node _T_422 = andr(UInt<2>(0h0))
node _T_423 = eq(_T_422, UInt<1>(0h0))
when _T_423 :
node _T_424 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_425 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_426 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_427 = or(_T_424, _T_425)
node _T_428 = or(_T_427, _T_426)
node _T_429 = eq(io.rw.addr, UInt<10>(0h342))
node _T_430 = and(_T_428, _T_429)
else :
node _T_431 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_432 = eq(io.rw.addr, UInt<10>(0h342))
node _T_433 = and(_T_431, _T_432)
node _T_434 = andr(UInt<2>(0h3))
node _T_435 = eq(_T_434, UInt<1>(0h0))
when _T_435 :
node _T_436 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_437 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_438 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_439 = or(_T_436, _T_437)
node _T_440 = or(_T_439, _T_438)
node _T_441 = eq(io.rw.addr, UInt<12>(0hf14))
node _T_442 = and(_T_440, _T_441)
else :
node _T_443 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_444 = eq(io.rw.addr, UInt<12>(0hf14))
node _T_445 = and(_T_443, _T_444)
node _T_446 = andr(UInt<2>(0h1))
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_449 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_450 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_451 = or(_T_448, _T_449)
node _T_452 = or(_T_451, _T_450)
node _T_453 = eq(io.rw.addr, UInt<11>(0h7b0))
node _T_454 = and(_T_452, _T_453)
else :
node _T_455 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_456 = eq(io.rw.addr, UInt<11>(0h7b0))
node _T_457 = and(_T_455, _T_456)
node _T_458 = andr(UInt<2>(0h1))
node _T_459 = eq(_T_458, UInt<1>(0h0))
when _T_459 :
node _T_460 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_461 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_462 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_463 = or(_T_460, _T_461)
node _T_464 = or(_T_463, _T_462)
node _T_465 = eq(io.rw.addr, UInt<11>(0h7b1))
node _T_466 = and(_T_464, _T_465)
else :
node _T_467 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_468 = eq(io.rw.addr, UInt<11>(0h7b1))
node _T_469 = and(_T_467, _T_468)
node _T_470 = andr(UInt<2>(0h1))
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_473 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_474 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_475 = or(_T_472, _T_473)
node _T_476 = or(_T_475, _T_474)
node _T_477 = eq(io.rw.addr, UInt<11>(0h7b2))
node _T_478 = and(_T_476, _T_477)
else :
node _T_479 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_480 = eq(io.rw.addr, UInt<11>(0h7b2))
node _T_481 = and(_T_479, _T_480)
node _T_482 = andr(UInt<2>(0h0))
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_485 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_486 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_487 = or(_T_484, _T_485)
node _T_488 = or(_T_487, _T_486)
node _T_489 = eq(io.rw.addr, UInt<1>(0h1))
node _T_490 = and(_T_488, _T_489)
else :
node _T_491 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_492 = eq(io.rw.addr, UInt<1>(0h1))
node _T_493 = and(_T_491, _T_492)
node _T_494 = andr(UInt<2>(0h0))
node _T_495 = eq(_T_494, UInt<1>(0h0))
when _T_495 :
node _T_496 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_497 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_498 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_499 = or(_T_496, _T_497)
node _T_500 = or(_T_499, _T_498)
node _T_501 = eq(io.rw.addr, UInt<2>(0h2))
node _T_502 = and(_T_500, _T_501)
else :
node _T_503 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_504 = eq(io.rw.addr, UInt<2>(0h2))
node _T_505 = and(_T_503, _T_504)
node _T_506 = andr(UInt<2>(0h0))
node _T_507 = eq(_T_506, UInt<1>(0h0))
when _T_507 :
node _T_508 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_509 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_510 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_511 = or(_T_508, _T_509)
node _T_512 = or(_T_511, _T_510)
node _T_513 = eq(io.rw.addr, UInt<2>(0h3))
node _T_514 = and(_T_512, _T_513)
else :
node _T_515 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_516 = eq(io.rw.addr, UInt<2>(0h3))
node _T_517 = and(_T_515, _T_516)
node _T_518 = andr(UInt<2>(0h0))
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_521 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_522 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_523 = or(_T_520, _T_521)
node _T_524 = or(_T_523, _T_522)
node _T_525 = eq(io.rw.addr, UInt<10>(0h320))
node _T_526 = and(_T_524, _T_525)
else :
node _T_527 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_528 = eq(io.rw.addr, UInt<10>(0h320))
node _T_529 = and(_T_527, _T_528)
node _T_530 = andr(UInt<2>(0h2))
node _T_531 = eq(_T_530, UInt<1>(0h0))
when _T_531 :
node _T_532 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_533 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_534 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_535 = or(_T_532, _T_533)
node _T_536 = or(_T_535, _T_534)
node _T_537 = eq(io.rw.addr, UInt<12>(0hb00))
node _T_538 = and(_T_536, _T_537)
else :
node _T_539 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_540 = eq(io.rw.addr, UInt<12>(0hb00))
node _T_541 = and(_T_539, _T_540)
node _T_542 = andr(UInt<2>(0h2))
node _T_543 = eq(_T_542, UInt<1>(0h0))
when _T_543 :
node _T_544 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_545 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_546 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_547 = or(_T_544, _T_545)
node _T_548 = or(_T_547, _T_546)
node _T_549 = eq(io.rw.addr, UInt<12>(0hb02))
node _T_550 = and(_T_548, _T_549)
else :
node _T_551 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_552 = eq(io.rw.addr, UInt<12>(0hb02))
node _T_553 = and(_T_551, _T_552)
node _T_554 = andr(UInt<2>(0h0))
node _T_555 = eq(_T_554, UInt<1>(0h0))
when _T_555 :
node _T_556 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_557 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_558 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_559 = or(_T_556, _T_557)
node _T_560 = or(_T_559, _T_558)
node _T_561 = eq(io.rw.addr, UInt<10>(0h323))
node _T_562 = and(_T_560, _T_561)
else :
node _T_563 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_564 = eq(io.rw.addr, UInt<10>(0h323))
node _T_565 = and(_T_563, _T_564)
node _T_566 = andr(UInt<2>(0h2))
node _T_567 = eq(_T_566, UInt<1>(0h0))
when _T_567 :
node _T_568 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_569 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_570 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_571 = or(_T_568, _T_569)
node _T_572 = or(_T_571, _T_570)
node _T_573 = eq(io.rw.addr, UInt<12>(0hb03))
node _T_574 = and(_T_572, _T_573)
else :
node _T_575 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_576 = eq(io.rw.addr, UInt<12>(0hb03))
node _T_577 = and(_T_575, _T_576)
node _T_578 = andr(UInt<2>(0h3))
node _T_579 = eq(_T_578, UInt<1>(0h0))
when _T_579 :
node _T_580 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_581 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_582 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_583 = or(_T_580, _T_581)
node _T_584 = or(_T_583, _T_582)
node _T_585 = eq(io.rw.addr, UInt<12>(0hc03))
node _T_586 = and(_T_584, _T_585)
else :
node _T_587 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_588 = eq(io.rw.addr, UInt<12>(0hc03))
node _T_589 = and(_T_587, _T_588)
node _T_590 = andr(UInt<2>(0h0))
node _T_591 = eq(_T_590, UInt<1>(0h0))
when _T_591 :
node _T_592 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_593 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_594 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_595 = or(_T_592, _T_593)
node _T_596 = or(_T_595, _T_594)
node _T_597 = eq(io.rw.addr, UInt<10>(0h324))
node _T_598 = and(_T_596, _T_597)
else :
node _T_599 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_600 = eq(io.rw.addr, UInt<10>(0h324))
node _T_601 = and(_T_599, _T_600)
node _T_602 = andr(UInt<2>(0h2))
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_605 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_606 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_607 = or(_T_604, _T_605)
node _T_608 = or(_T_607, _T_606)
node _T_609 = eq(io.rw.addr, UInt<12>(0hb04))
node _T_610 = and(_T_608, _T_609)
else :
node _T_611 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_612 = eq(io.rw.addr, UInt<12>(0hb04))
node _T_613 = and(_T_611, _T_612)
node _T_614 = andr(UInt<2>(0h3))
node _T_615 = eq(_T_614, UInt<1>(0h0))
when _T_615 :
node _T_616 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_617 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_618 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_619 = or(_T_616, _T_617)
node _T_620 = or(_T_619, _T_618)
node _T_621 = eq(io.rw.addr, UInt<12>(0hc04))
node _T_622 = and(_T_620, _T_621)
else :
node _T_623 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_624 = eq(io.rw.addr, UInt<12>(0hc04))
node _T_625 = and(_T_623, _T_624)
node _T_626 = andr(UInt<2>(0h0))
node _T_627 = eq(_T_626, UInt<1>(0h0))
when _T_627 :
node _T_628 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_629 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_630 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_631 = or(_T_628, _T_629)
node _T_632 = or(_T_631, _T_630)
node _T_633 = eq(io.rw.addr, UInt<10>(0h325))
node _T_634 = and(_T_632, _T_633)
else :
node _T_635 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_636 = eq(io.rw.addr, UInt<10>(0h325))
node _T_637 = and(_T_635, _T_636)
node _T_638 = andr(UInt<2>(0h2))
node _T_639 = eq(_T_638, UInt<1>(0h0))
when _T_639 :
node _T_640 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_641 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_642 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_643 = or(_T_640, _T_641)
node _T_644 = or(_T_643, _T_642)
node _T_645 = eq(io.rw.addr, UInt<12>(0hb05))
node _T_646 = and(_T_644, _T_645)
else :
node _T_647 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_648 = eq(io.rw.addr, UInt<12>(0hb05))
node _T_649 = and(_T_647, _T_648)
node _T_650 = andr(UInt<2>(0h0))
node _T_651 = eq(_T_650, UInt<1>(0h0))
when _T_651 :
node _T_652 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_653 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_654 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_655 = or(_T_652, _T_653)
node _T_656 = or(_T_655, _T_654)
node _T_657 = eq(io.rw.addr, UInt<10>(0h326))
node _T_658 = and(_T_656, _T_657)
else :
node _T_659 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_660 = eq(io.rw.addr, UInt<10>(0h326))
node _T_661 = and(_T_659, _T_660)
node _T_662 = andr(UInt<2>(0h2))
node _T_663 = eq(_T_662, UInt<1>(0h0))
when _T_663 :
node _T_664 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_665 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_666 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_667 = or(_T_664, _T_665)
node _T_668 = or(_T_667, _T_666)
node _T_669 = eq(io.rw.addr, UInt<12>(0hb06))
node _T_670 = and(_T_668, _T_669)
else :
node _T_671 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_672 = eq(io.rw.addr, UInt<12>(0hb06))
node _T_673 = and(_T_671, _T_672)
node _T_674 = andr(UInt<2>(0h0))
node _T_675 = eq(_T_674, UInt<1>(0h0))
when _T_675 :
node _T_676 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_677 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_678 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_679 = or(_T_676, _T_677)
node _T_680 = or(_T_679, _T_678)
node _T_681 = eq(io.rw.addr, UInt<10>(0h327))
node _T_682 = and(_T_680, _T_681)
else :
node _T_683 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_684 = eq(io.rw.addr, UInt<10>(0h327))
node _T_685 = and(_T_683, _T_684)
node _T_686 = andr(UInt<2>(0h2))
node _T_687 = eq(_T_686, UInt<1>(0h0))
when _T_687 :
node _T_688 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_689 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_690 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_691 = or(_T_688, _T_689)
node _T_692 = or(_T_691, _T_690)
node _T_693 = eq(io.rw.addr, UInt<12>(0hb07))
node _T_694 = and(_T_692, _T_693)
else :
node _T_695 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_696 = eq(io.rw.addr, UInt<12>(0hb07))
node _T_697 = and(_T_695, _T_696)
node _T_698 = andr(UInt<2>(0h0))
node _T_699 = eq(_T_698, UInt<1>(0h0))
when _T_699 :
node _T_700 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_701 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_702 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_703 = or(_T_700, _T_701)
node _T_704 = or(_T_703, _T_702)
node _T_705 = eq(io.rw.addr, UInt<10>(0h328))
node _T_706 = and(_T_704, _T_705)
else :
node _T_707 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_708 = eq(io.rw.addr, UInt<10>(0h328))
node _T_709 = and(_T_707, _T_708)
node _T_710 = andr(UInt<2>(0h2))
node _T_711 = eq(_T_710, UInt<1>(0h0))
when _T_711 :
node _T_712 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_713 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_714 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_715 = or(_T_712, _T_713)
node _T_716 = or(_T_715, _T_714)
node _T_717 = eq(io.rw.addr, UInt<12>(0hb08))
node _T_718 = and(_T_716, _T_717)
else :
node _T_719 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_720 = eq(io.rw.addr, UInt<12>(0hb08))
node _T_721 = and(_T_719, _T_720)
node _T_722 = andr(UInt<2>(0h0))
node _T_723 = eq(_T_722, UInt<1>(0h0))
when _T_723 :
node _T_724 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_725 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_726 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_727 = or(_T_724, _T_725)
node _T_728 = or(_T_727, _T_726)
node _T_729 = eq(io.rw.addr, UInt<10>(0h329))
node _T_730 = and(_T_728, _T_729)
else :
node _T_731 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_732 = eq(io.rw.addr, UInt<10>(0h329))
node _T_733 = and(_T_731, _T_732)
node _T_734 = andr(UInt<2>(0h2))
node _T_735 = eq(_T_734, UInt<1>(0h0))
when _T_735 :
node _T_736 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_737 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_738 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_739 = or(_T_736, _T_737)
node _T_740 = or(_T_739, _T_738)
node _T_741 = eq(io.rw.addr, UInt<12>(0hb09))
node _T_742 = and(_T_740, _T_741)
else :
node _T_743 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_744 = eq(io.rw.addr, UInt<12>(0hb09))
node _T_745 = and(_T_743, _T_744)
node _T_746 = andr(UInt<2>(0h0))
node _T_747 = eq(_T_746, UInt<1>(0h0))
when _T_747 :
node _T_748 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_749 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_750 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_751 = or(_T_748, _T_749)
node _T_752 = or(_T_751, _T_750)
node _T_753 = eq(io.rw.addr, UInt<10>(0h32a))
node _T_754 = and(_T_752, _T_753)
else :
node _T_755 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_756 = eq(io.rw.addr, UInt<10>(0h32a))
node _T_757 = and(_T_755, _T_756)
node _T_758 = andr(UInt<2>(0h2))
node _T_759 = eq(_T_758, UInt<1>(0h0))
when _T_759 :
node _T_760 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_761 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_762 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_763 = or(_T_760, _T_761)
node _T_764 = or(_T_763, _T_762)
node _T_765 = eq(io.rw.addr, UInt<12>(0hb0a))
node _T_766 = and(_T_764, _T_765)
else :
node _T_767 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_768 = eq(io.rw.addr, UInt<12>(0hb0a))
node _T_769 = and(_T_767, _T_768)
node _T_770 = andr(UInt<2>(0h0))
node _T_771 = eq(_T_770, UInt<1>(0h0))
when _T_771 :
node _T_772 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_773 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_774 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_775 = or(_T_772, _T_773)
node _T_776 = or(_T_775, _T_774)
node _T_777 = eq(io.rw.addr, UInt<10>(0h32b))
node _T_778 = and(_T_776, _T_777)
else :
node _T_779 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_780 = eq(io.rw.addr, UInt<10>(0h32b))
node _T_781 = and(_T_779, _T_780)
node _T_782 = andr(UInt<2>(0h2))
node _T_783 = eq(_T_782, UInt<1>(0h0))
when _T_783 :
node _T_784 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_785 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_786 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_787 = or(_T_784, _T_785)
node _T_788 = or(_T_787, _T_786)
node _T_789 = eq(io.rw.addr, UInt<12>(0hb0b))
node _T_790 = and(_T_788, _T_789)
else :
node _T_791 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_792 = eq(io.rw.addr, UInt<12>(0hb0b))
node _T_793 = and(_T_791, _T_792)
node _T_794 = andr(UInt<2>(0h0))
node _T_795 = eq(_T_794, UInt<1>(0h0))
when _T_795 :
node _T_796 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_797 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_798 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_799 = or(_T_796, _T_797)
node _T_800 = or(_T_799, _T_798)
node _T_801 = eq(io.rw.addr, UInt<10>(0h32c))
node _T_802 = and(_T_800, _T_801)
else :
node _T_803 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_804 = eq(io.rw.addr, UInt<10>(0h32c))
node _T_805 = and(_T_803, _T_804)
node _T_806 = andr(UInt<2>(0h2))
node _T_807 = eq(_T_806, UInt<1>(0h0))
when _T_807 :
node _T_808 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_809 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_810 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_811 = or(_T_808, _T_809)
node _T_812 = or(_T_811, _T_810)
node _T_813 = eq(io.rw.addr, UInt<12>(0hb0c))
node _T_814 = and(_T_812, _T_813)
else :
node _T_815 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_816 = eq(io.rw.addr, UInt<12>(0hb0c))
node _T_817 = and(_T_815, _T_816)
node _T_818 = andr(UInt<2>(0h0))
node _T_819 = eq(_T_818, UInt<1>(0h0))
when _T_819 :
node _T_820 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_821 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_822 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_823 = or(_T_820, _T_821)
node _T_824 = or(_T_823, _T_822)
node _T_825 = eq(io.rw.addr, UInt<10>(0h32d))
node _T_826 = and(_T_824, _T_825)
else :
node _T_827 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_828 = eq(io.rw.addr, UInt<10>(0h32d))
node _T_829 = and(_T_827, _T_828)
node _T_830 = andr(UInt<2>(0h2))
node _T_831 = eq(_T_830, UInt<1>(0h0))
when _T_831 :
node _T_832 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_833 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_834 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_835 = or(_T_832, _T_833)
node _T_836 = or(_T_835, _T_834)
node _T_837 = eq(io.rw.addr, UInt<12>(0hb0d))
node _T_838 = and(_T_836, _T_837)
else :
node _T_839 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_840 = eq(io.rw.addr, UInt<12>(0hb0d))
node _T_841 = and(_T_839, _T_840)
node _T_842 = andr(UInt<2>(0h0))
node _T_843 = eq(_T_842, UInt<1>(0h0))
when _T_843 :
node _T_844 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_845 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_846 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_847 = or(_T_844, _T_845)
node _T_848 = or(_T_847, _T_846)
node _T_849 = eq(io.rw.addr, UInt<10>(0h32e))
node _T_850 = and(_T_848, _T_849)
else :
node _T_851 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_852 = eq(io.rw.addr, UInt<10>(0h32e))
node _T_853 = and(_T_851, _T_852)
node _T_854 = andr(UInt<2>(0h2))
node _T_855 = eq(_T_854, UInt<1>(0h0))
when _T_855 :
node _T_856 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_857 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_858 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_859 = or(_T_856, _T_857)
node _T_860 = or(_T_859, _T_858)
node _T_861 = eq(io.rw.addr, UInt<12>(0hb0e))
node _T_862 = and(_T_860, _T_861)
else :
node _T_863 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_864 = eq(io.rw.addr, UInt<12>(0hb0e))
node _T_865 = and(_T_863, _T_864)
node _T_866 = andr(UInt<2>(0h0))
node _T_867 = eq(_T_866, UInt<1>(0h0))
when _T_867 :
node _T_868 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_869 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_870 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_871 = or(_T_868, _T_869)
node _T_872 = or(_T_871, _T_870)
node _T_873 = eq(io.rw.addr, UInt<10>(0h32f))
node _T_874 = and(_T_872, _T_873)
else :
node _T_875 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_876 = eq(io.rw.addr, UInt<10>(0h32f))
node _T_877 = and(_T_875, _T_876)
node _T_878 = andr(UInt<2>(0h2))
node _T_879 = eq(_T_878, UInt<1>(0h0))
when _T_879 :
node _T_880 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_881 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_882 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_883 = or(_T_880, _T_881)
node _T_884 = or(_T_883, _T_882)
node _T_885 = eq(io.rw.addr, UInt<12>(0hb0f))
node _T_886 = and(_T_884, _T_885)
else :
node _T_887 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_888 = eq(io.rw.addr, UInt<12>(0hb0f))
node _T_889 = and(_T_887, _T_888)
node _T_890 = andr(UInt<2>(0h0))
node _T_891 = eq(_T_890, UInt<1>(0h0))
when _T_891 :
node _T_892 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_893 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_894 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_895 = or(_T_892, _T_893)
node _T_896 = or(_T_895, _T_894)
node _T_897 = eq(io.rw.addr, UInt<10>(0h330))
node _T_898 = and(_T_896, _T_897)
else :
node _T_899 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_900 = eq(io.rw.addr, UInt<10>(0h330))
node _T_901 = and(_T_899, _T_900)
node _T_902 = andr(UInt<2>(0h2))
node _T_903 = eq(_T_902, UInt<1>(0h0))
when _T_903 :
node _T_904 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_905 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_906 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_907 = or(_T_904, _T_905)
node _T_908 = or(_T_907, _T_906)
node _T_909 = eq(io.rw.addr, UInt<12>(0hb10))
node _T_910 = and(_T_908, _T_909)
else :
node _T_911 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_912 = eq(io.rw.addr, UInt<12>(0hb10))
node _T_913 = and(_T_911, _T_912)
node _T_914 = andr(UInt<2>(0h0))
node _T_915 = eq(_T_914, UInt<1>(0h0))
when _T_915 :
node _T_916 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_917 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_918 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_919 = or(_T_916, _T_917)
node _T_920 = or(_T_919, _T_918)
node _T_921 = eq(io.rw.addr, UInt<10>(0h331))
node _T_922 = and(_T_920, _T_921)
else :
node _T_923 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_924 = eq(io.rw.addr, UInt<10>(0h331))
node _T_925 = and(_T_923, _T_924)
node _T_926 = andr(UInt<2>(0h2))
node _T_927 = eq(_T_926, UInt<1>(0h0))
when _T_927 :
node _T_928 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_929 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_930 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_931 = or(_T_928, _T_929)
node _T_932 = or(_T_931, _T_930)
node _T_933 = eq(io.rw.addr, UInt<12>(0hb11))
node _T_934 = and(_T_932, _T_933)
else :
node _T_935 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_936 = eq(io.rw.addr, UInt<12>(0hb11))
node _T_937 = and(_T_935, _T_936)
node _T_938 = andr(UInt<2>(0h0))
node _T_939 = eq(_T_938, UInt<1>(0h0))
when _T_939 :
node _T_940 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_941 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_942 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_943 = or(_T_940, _T_941)
node _T_944 = or(_T_943, _T_942)
node _T_945 = eq(io.rw.addr, UInt<10>(0h332))
node _T_946 = and(_T_944, _T_945)
else :
node _T_947 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_948 = eq(io.rw.addr, UInt<10>(0h332))
node _T_949 = and(_T_947, _T_948)
node _T_950 = andr(UInt<2>(0h2))
node _T_951 = eq(_T_950, UInt<1>(0h0))
when _T_951 :
node _T_952 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_953 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_954 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_955 = or(_T_952, _T_953)
node _T_956 = or(_T_955, _T_954)
node _T_957 = eq(io.rw.addr, UInt<12>(0hb12))
node _T_958 = and(_T_956, _T_957)
else :
node _T_959 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_960 = eq(io.rw.addr, UInt<12>(0hb12))
node _T_961 = and(_T_959, _T_960)
node _T_962 = andr(UInt<2>(0h0))
node _T_963 = eq(_T_962, UInt<1>(0h0))
when _T_963 :
node _T_964 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_965 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_966 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_967 = or(_T_964, _T_965)
node _T_968 = or(_T_967, _T_966)
node _T_969 = eq(io.rw.addr, UInt<10>(0h333))
node _T_970 = and(_T_968, _T_969)
else :
node _T_971 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_972 = eq(io.rw.addr, UInt<10>(0h333))
node _T_973 = and(_T_971, _T_972)
node _T_974 = andr(UInt<2>(0h2))
node _T_975 = eq(_T_974, UInt<1>(0h0))
when _T_975 :
node _T_976 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_977 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_978 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_979 = or(_T_976, _T_977)
node _T_980 = or(_T_979, _T_978)
node _T_981 = eq(io.rw.addr, UInt<12>(0hb13))
node _T_982 = and(_T_980, _T_981)
else :
node _T_983 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_984 = eq(io.rw.addr, UInt<12>(0hb13))
node _T_985 = and(_T_983, _T_984)
node _T_986 = andr(UInt<2>(0h0))
node _T_987 = eq(_T_986, UInt<1>(0h0))
when _T_987 :
node _T_988 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_989 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_990 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_991 = or(_T_988, _T_989)
node _T_992 = or(_T_991, _T_990)
node _T_993 = eq(io.rw.addr, UInt<10>(0h334))
node _T_994 = and(_T_992, _T_993)
else :
node _T_995 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_996 = eq(io.rw.addr, UInt<10>(0h334))
node _T_997 = and(_T_995, _T_996)
node _T_998 = andr(UInt<2>(0h2))
node _T_999 = eq(_T_998, UInt<1>(0h0))
when _T_999 :
node _T_1000 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1001 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1002 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1003 = or(_T_1000, _T_1001)
node _T_1004 = or(_T_1003, _T_1002)
node _T_1005 = eq(io.rw.addr, UInt<12>(0hb14))
node _T_1006 = and(_T_1004, _T_1005)
else :
node _T_1007 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1008 = eq(io.rw.addr, UInt<12>(0hb14))
node _T_1009 = and(_T_1007, _T_1008)
node _T_1010 = andr(UInt<2>(0h0))
node _T_1011 = eq(_T_1010, UInt<1>(0h0))
when _T_1011 :
node _T_1012 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1013 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1014 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1015 = or(_T_1012, _T_1013)
node _T_1016 = or(_T_1015, _T_1014)
node _T_1017 = eq(io.rw.addr, UInt<10>(0h335))
node _T_1018 = and(_T_1016, _T_1017)
else :
node _T_1019 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1020 = eq(io.rw.addr, UInt<10>(0h335))
node _T_1021 = and(_T_1019, _T_1020)
node _T_1022 = andr(UInt<2>(0h2))
node _T_1023 = eq(_T_1022, UInt<1>(0h0))
when _T_1023 :
node _T_1024 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1025 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1026 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1027 = or(_T_1024, _T_1025)
node _T_1028 = or(_T_1027, _T_1026)
node _T_1029 = eq(io.rw.addr, UInt<12>(0hb15))
node _T_1030 = and(_T_1028, _T_1029)
else :
node _T_1031 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1032 = eq(io.rw.addr, UInt<12>(0hb15))
node _T_1033 = and(_T_1031, _T_1032)
node _T_1034 = andr(UInt<2>(0h0))
node _T_1035 = eq(_T_1034, UInt<1>(0h0))
when _T_1035 :
node _T_1036 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1037 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1038 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1039 = or(_T_1036, _T_1037)
node _T_1040 = or(_T_1039, _T_1038)
node _T_1041 = eq(io.rw.addr, UInt<10>(0h336))
node _T_1042 = and(_T_1040, _T_1041)
else :
node _T_1043 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1044 = eq(io.rw.addr, UInt<10>(0h336))
node _T_1045 = and(_T_1043, _T_1044)
node _T_1046 = andr(UInt<2>(0h2))
node _T_1047 = eq(_T_1046, UInt<1>(0h0))
when _T_1047 :
node _T_1048 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1049 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1050 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1051 = or(_T_1048, _T_1049)
node _T_1052 = or(_T_1051, _T_1050)
node _T_1053 = eq(io.rw.addr, UInt<12>(0hb16))
node _T_1054 = and(_T_1052, _T_1053)
else :
node _T_1055 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1056 = eq(io.rw.addr, UInt<12>(0hb16))
node _T_1057 = and(_T_1055, _T_1056)
node _T_1058 = andr(UInt<2>(0h0))
node _T_1059 = eq(_T_1058, UInt<1>(0h0))
when _T_1059 :
node _T_1060 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1061 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1062 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1063 = or(_T_1060, _T_1061)
node _T_1064 = or(_T_1063, _T_1062)
node _T_1065 = eq(io.rw.addr, UInt<10>(0h337))
node _T_1066 = and(_T_1064, _T_1065)
else :
node _T_1067 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1068 = eq(io.rw.addr, UInt<10>(0h337))
node _T_1069 = and(_T_1067, _T_1068)
node _T_1070 = andr(UInt<2>(0h2))
node _T_1071 = eq(_T_1070, UInt<1>(0h0))
when _T_1071 :
node _T_1072 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1073 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1074 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1075 = or(_T_1072, _T_1073)
node _T_1076 = or(_T_1075, _T_1074)
node _T_1077 = eq(io.rw.addr, UInt<12>(0hb17))
node _T_1078 = and(_T_1076, _T_1077)
else :
node _T_1079 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1080 = eq(io.rw.addr, UInt<12>(0hb17))
node _T_1081 = and(_T_1079, _T_1080)
node _T_1082 = andr(UInt<2>(0h0))
node _T_1083 = eq(_T_1082, UInt<1>(0h0))
when _T_1083 :
node _T_1084 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1085 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1086 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1087 = or(_T_1084, _T_1085)
node _T_1088 = or(_T_1087, _T_1086)
node _T_1089 = eq(io.rw.addr, UInt<10>(0h338))
node _T_1090 = and(_T_1088, _T_1089)
else :
node _T_1091 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1092 = eq(io.rw.addr, UInt<10>(0h338))
node _T_1093 = and(_T_1091, _T_1092)
node _T_1094 = andr(UInt<2>(0h2))
node _T_1095 = eq(_T_1094, UInt<1>(0h0))
when _T_1095 :
node _T_1096 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1097 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1098 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1099 = or(_T_1096, _T_1097)
node _T_1100 = or(_T_1099, _T_1098)
node _T_1101 = eq(io.rw.addr, UInt<12>(0hb18))
node _T_1102 = and(_T_1100, _T_1101)
else :
node _T_1103 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1104 = eq(io.rw.addr, UInt<12>(0hb18))
node _T_1105 = and(_T_1103, _T_1104)
node _T_1106 = andr(UInt<2>(0h0))
node _T_1107 = eq(_T_1106, UInt<1>(0h0))
when _T_1107 :
node _T_1108 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1109 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1110 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1111 = or(_T_1108, _T_1109)
node _T_1112 = or(_T_1111, _T_1110)
node _T_1113 = eq(io.rw.addr, UInt<10>(0h339))
node _T_1114 = and(_T_1112, _T_1113)
else :
node _T_1115 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1116 = eq(io.rw.addr, UInt<10>(0h339))
node _T_1117 = and(_T_1115, _T_1116)
node _T_1118 = andr(UInt<2>(0h2))
node _T_1119 = eq(_T_1118, UInt<1>(0h0))
when _T_1119 :
node _T_1120 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1121 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1122 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1123 = or(_T_1120, _T_1121)
node _T_1124 = or(_T_1123, _T_1122)
node _T_1125 = eq(io.rw.addr, UInt<12>(0hb19))
node _T_1126 = and(_T_1124, _T_1125)
else :
node _T_1127 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1128 = eq(io.rw.addr, UInt<12>(0hb19))
node _T_1129 = and(_T_1127, _T_1128)
node _T_1130 = andr(UInt<2>(0h0))
node _T_1131 = eq(_T_1130, UInt<1>(0h0))
when _T_1131 :
node _T_1132 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1133 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1134 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1135 = or(_T_1132, _T_1133)
node _T_1136 = or(_T_1135, _T_1134)
node _T_1137 = eq(io.rw.addr, UInt<10>(0h33a))
node _T_1138 = and(_T_1136, _T_1137)
else :
node _T_1139 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1140 = eq(io.rw.addr, UInt<10>(0h33a))
node _T_1141 = and(_T_1139, _T_1140)
node _T_1142 = andr(UInt<2>(0h2))
node _T_1143 = eq(_T_1142, UInt<1>(0h0))
when _T_1143 :
node _T_1144 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1145 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1146 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1147 = or(_T_1144, _T_1145)
node _T_1148 = or(_T_1147, _T_1146)
node _T_1149 = eq(io.rw.addr, UInt<12>(0hb1a))
node _T_1150 = and(_T_1148, _T_1149)
else :
node _T_1151 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1152 = eq(io.rw.addr, UInt<12>(0hb1a))
node _T_1153 = and(_T_1151, _T_1152)
node _T_1154 = andr(UInt<2>(0h0))
node _T_1155 = eq(_T_1154, UInt<1>(0h0))
when _T_1155 :
node _T_1156 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1157 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1158 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1159 = or(_T_1156, _T_1157)
node _T_1160 = or(_T_1159, _T_1158)
node _T_1161 = eq(io.rw.addr, UInt<10>(0h33b))
node _T_1162 = and(_T_1160, _T_1161)
else :
node _T_1163 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1164 = eq(io.rw.addr, UInt<10>(0h33b))
node _T_1165 = and(_T_1163, _T_1164)
node _T_1166 = andr(UInt<2>(0h2))
node _T_1167 = eq(_T_1166, UInt<1>(0h0))
when _T_1167 :
node _T_1168 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1169 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1170 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1171 = or(_T_1168, _T_1169)
node _T_1172 = or(_T_1171, _T_1170)
node _T_1173 = eq(io.rw.addr, UInt<12>(0hb1b))
node _T_1174 = and(_T_1172, _T_1173)
else :
node _T_1175 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1176 = eq(io.rw.addr, UInt<12>(0hb1b))
node _T_1177 = and(_T_1175, _T_1176)
node _T_1178 = andr(UInt<2>(0h0))
node _T_1179 = eq(_T_1178, UInt<1>(0h0))
when _T_1179 :
node _T_1180 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1181 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1182 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1183 = or(_T_1180, _T_1181)
node _T_1184 = or(_T_1183, _T_1182)
node _T_1185 = eq(io.rw.addr, UInt<10>(0h33c))
node _T_1186 = and(_T_1184, _T_1185)
else :
node _T_1187 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1188 = eq(io.rw.addr, UInt<10>(0h33c))
node _T_1189 = and(_T_1187, _T_1188)
node _T_1190 = andr(UInt<2>(0h2))
node _T_1191 = eq(_T_1190, UInt<1>(0h0))
when _T_1191 :
node _T_1192 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1193 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1194 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1195 = or(_T_1192, _T_1193)
node _T_1196 = or(_T_1195, _T_1194)
node _T_1197 = eq(io.rw.addr, UInt<12>(0hb1c))
node _T_1198 = and(_T_1196, _T_1197)
else :
node _T_1199 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1200 = eq(io.rw.addr, UInt<12>(0hb1c))
node _T_1201 = and(_T_1199, _T_1200)
node _T_1202 = andr(UInt<2>(0h0))
node _T_1203 = eq(_T_1202, UInt<1>(0h0))
when _T_1203 :
node _T_1204 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1205 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1206 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1207 = or(_T_1204, _T_1205)
node _T_1208 = or(_T_1207, _T_1206)
node _T_1209 = eq(io.rw.addr, UInt<10>(0h33d))
node _T_1210 = and(_T_1208, _T_1209)
else :
node _T_1211 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1212 = eq(io.rw.addr, UInt<10>(0h33d))
node _T_1213 = and(_T_1211, _T_1212)
node _T_1214 = andr(UInt<2>(0h2))
node _T_1215 = eq(_T_1214, UInt<1>(0h0))
when _T_1215 :
node _T_1216 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1217 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1218 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1219 = or(_T_1216, _T_1217)
node _T_1220 = or(_T_1219, _T_1218)
node _T_1221 = eq(io.rw.addr, UInt<12>(0hb1d))
node _T_1222 = and(_T_1220, _T_1221)
else :
node _T_1223 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1224 = eq(io.rw.addr, UInt<12>(0hb1d))
node _T_1225 = and(_T_1223, _T_1224)
node _T_1226 = andr(UInt<2>(0h0))
node _T_1227 = eq(_T_1226, UInt<1>(0h0))
when _T_1227 :
node _T_1228 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1229 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1230 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1231 = or(_T_1228, _T_1229)
node _T_1232 = or(_T_1231, _T_1230)
node _T_1233 = eq(io.rw.addr, UInt<10>(0h33e))
node _T_1234 = and(_T_1232, _T_1233)
else :
node _T_1235 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1236 = eq(io.rw.addr, UInt<10>(0h33e))
node _T_1237 = and(_T_1235, _T_1236)
node _T_1238 = andr(UInt<2>(0h2))
node _T_1239 = eq(_T_1238, UInt<1>(0h0))
when _T_1239 :
node _T_1240 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1241 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1242 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1243 = or(_T_1240, _T_1241)
node _T_1244 = or(_T_1243, _T_1242)
node _T_1245 = eq(io.rw.addr, UInt<12>(0hb1e))
node _T_1246 = and(_T_1244, _T_1245)
else :
node _T_1247 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1248 = eq(io.rw.addr, UInt<12>(0hb1e))
node _T_1249 = and(_T_1247, _T_1248)
node _T_1250 = andr(UInt<2>(0h0))
node _T_1251 = eq(_T_1250, UInt<1>(0h0))
when _T_1251 :
node _T_1252 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1253 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1254 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1255 = or(_T_1252, _T_1253)
node _T_1256 = or(_T_1255, _T_1254)
node _T_1257 = eq(io.rw.addr, UInt<10>(0h33f))
node _T_1258 = and(_T_1256, _T_1257)
else :
node _T_1259 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1260 = eq(io.rw.addr, UInt<10>(0h33f))
node _T_1261 = and(_T_1259, _T_1260)
node _T_1262 = andr(UInt<2>(0h2))
node _T_1263 = eq(_T_1262, UInt<1>(0h0))
when _T_1263 :
node _T_1264 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1265 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1266 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1267 = or(_T_1264, _T_1265)
node _T_1268 = or(_T_1267, _T_1266)
node _T_1269 = eq(io.rw.addr, UInt<12>(0hb1f))
node _T_1270 = and(_T_1268, _T_1269)
else :
node _T_1271 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1272 = eq(io.rw.addr, UInt<12>(0hb1f))
node _T_1273 = and(_T_1271, _T_1272)
node _T_1274 = andr(UInt<2>(0h0))
node _T_1275 = eq(_T_1274, UInt<1>(0h0))
when _T_1275 :
node _T_1276 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1277 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1278 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1279 = or(_T_1276, _T_1277)
node _T_1280 = or(_T_1279, _T_1278)
node _T_1281 = eq(io.rw.addr, UInt<10>(0h306))
node _T_1282 = and(_T_1280, _T_1281)
else :
node _T_1283 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1284 = eq(io.rw.addr, UInt<10>(0h306))
node _T_1285 = and(_T_1283, _T_1284)
node _T_1286 = andr(UInt<2>(0h3))
node _T_1287 = eq(_T_1286, UInt<1>(0h0))
when _T_1287 :
node _T_1288 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1289 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1290 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1291 = or(_T_1288, _T_1289)
node _T_1292 = or(_T_1291, _T_1290)
node _T_1293 = eq(io.rw.addr, UInt<12>(0hc00))
node _T_1294 = and(_T_1292, _T_1293)
else :
node _T_1295 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1296 = eq(io.rw.addr, UInt<12>(0hc00))
node _T_1297 = and(_T_1295, _T_1296)
node _T_1298 = andr(UInt<2>(0h3))
node _T_1299 = eq(_T_1298, UInt<1>(0h0))
when _T_1299 :
node _T_1300 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1301 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1302 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1303 = or(_T_1300, _T_1301)
node _T_1304 = or(_T_1303, _T_1302)
node _T_1305 = eq(io.rw.addr, UInt<12>(0hc02))
node _T_1306 = and(_T_1304, _T_1305)
else :
node _T_1307 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1308 = eq(io.rw.addr, UInt<12>(0hc02))
node _T_1309 = and(_T_1307, _T_1308)
node _T_1310 = andr(UInt<2>(0h0))
node _T_1311 = eq(_T_1310, UInt<1>(0h0))
when _T_1311 :
node _T_1312 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1313 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1314 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1315 = or(_T_1312, _T_1313)
node _T_1316 = or(_T_1315, _T_1314)
node _T_1317 = eq(io.rw.addr, UInt<10>(0h30a))
node _T_1318 = and(_T_1316, _T_1317)
else :
node _T_1319 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1320 = eq(io.rw.addr, UInt<10>(0h30a))
node _T_1321 = and(_T_1319, _T_1320)
node _T_1322 = andr(UInt<2>(0h0))
node _T_1323 = eq(_T_1322, UInt<1>(0h0))
when _T_1323 :
node _T_1324 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1325 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1326 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1327 = or(_T_1324, _T_1325)
node _T_1328 = or(_T_1327, _T_1326)
node _T_1329 = eq(io.rw.addr, UInt<9>(0h100))
node _T_1330 = and(_T_1328, _T_1329)
else :
node _T_1331 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1332 = eq(io.rw.addr, UInt<9>(0h100))
node _T_1333 = and(_T_1331, _T_1332)
node _T_1334 = andr(UInt<2>(0h0))
node _T_1335 = eq(_T_1334, UInt<1>(0h0))
when _T_1335 :
node _T_1336 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1337 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1338 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1339 = or(_T_1336, _T_1337)
node _T_1340 = or(_T_1339, _T_1338)
node _T_1341 = eq(io.rw.addr, UInt<9>(0h144))
node _T_1342 = and(_T_1340, _T_1341)
else :
node _T_1343 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1344 = eq(io.rw.addr, UInt<9>(0h144))
node _T_1345 = and(_T_1343, _T_1344)
node _T_1346 = andr(UInt<2>(0h0))
node _T_1347 = eq(_T_1346, UInt<1>(0h0))
when _T_1347 :
node _T_1348 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1349 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1350 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1351 = or(_T_1348, _T_1349)
node _T_1352 = or(_T_1351, _T_1350)
node _T_1353 = eq(io.rw.addr, UInt<9>(0h104))
node _T_1354 = and(_T_1352, _T_1353)
else :
node _T_1355 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1356 = eq(io.rw.addr, UInt<9>(0h104))
node _T_1357 = and(_T_1355, _T_1356)
node _T_1358 = andr(UInt<2>(0h0))
node _T_1359 = eq(_T_1358, UInt<1>(0h0))
when _T_1359 :
node _T_1360 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1361 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1362 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1363 = or(_T_1360, _T_1361)
node _T_1364 = or(_T_1363, _T_1362)
node _T_1365 = eq(io.rw.addr, UInt<9>(0h140))
node _T_1366 = and(_T_1364, _T_1365)
else :
node _T_1367 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1368 = eq(io.rw.addr, UInt<9>(0h140))
node _T_1369 = and(_T_1367, _T_1368)
node _T_1370 = andr(UInt<2>(0h0))
node _T_1371 = eq(_T_1370, UInt<1>(0h0))
when _T_1371 :
node _T_1372 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1373 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1374 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1375 = or(_T_1372, _T_1373)
node _T_1376 = or(_T_1375, _T_1374)
node _T_1377 = eq(io.rw.addr, UInt<9>(0h142))
node _T_1378 = and(_T_1376, _T_1377)
else :
node _T_1379 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1380 = eq(io.rw.addr, UInt<9>(0h142))
node _T_1381 = and(_T_1379, _T_1380)
node _T_1382 = andr(UInt<2>(0h0))
node _T_1383 = eq(_T_1382, UInt<1>(0h0))
when _T_1383 :
node _T_1384 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1385 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1386 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1387 = or(_T_1384, _T_1385)
node _T_1388 = or(_T_1387, _T_1386)
node _T_1389 = eq(io.rw.addr, UInt<9>(0h143))
node _T_1390 = and(_T_1388, _T_1389)
else :
node _T_1391 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1392 = eq(io.rw.addr, UInt<9>(0h143))
node _T_1393 = and(_T_1391, _T_1392)
node _T_1394 = andr(UInt<2>(0h0))
node _T_1395 = eq(_T_1394, UInt<1>(0h0))
when _T_1395 :
node _T_1396 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1397 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1398 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1399 = or(_T_1396, _T_1397)
node _T_1400 = or(_T_1399, _T_1398)
node _T_1401 = eq(io.rw.addr, UInt<9>(0h180))
node _T_1402 = and(_T_1400, _T_1401)
else :
node _T_1403 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1404 = eq(io.rw.addr, UInt<9>(0h180))
node _T_1405 = and(_T_1403, _T_1404)
node _T_1406 = andr(UInt<2>(0h0))
node _T_1407 = eq(_T_1406, UInt<1>(0h0))
when _T_1407 :
node _T_1408 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1409 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1410 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1411 = or(_T_1408, _T_1409)
node _T_1412 = or(_T_1411, _T_1410)
node _T_1413 = eq(io.rw.addr, UInt<9>(0h141))
node _T_1414 = and(_T_1412, _T_1413)
else :
node _T_1415 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1416 = eq(io.rw.addr, UInt<9>(0h141))
node _T_1417 = and(_T_1415, _T_1416)
node _T_1418 = andr(UInt<2>(0h0))
node _T_1419 = eq(_T_1418, UInt<1>(0h0))
when _T_1419 :
node _T_1420 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1421 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1422 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1423 = or(_T_1420, _T_1421)
node _T_1424 = or(_T_1423, _T_1422)
node _T_1425 = eq(io.rw.addr, UInt<9>(0h105))
node _T_1426 = and(_T_1424, _T_1425)
else :
node _T_1427 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1428 = eq(io.rw.addr, UInt<9>(0h105))
node _T_1429 = and(_T_1427, _T_1428)
node _T_1430 = andr(UInt<2>(0h0))
node _T_1431 = eq(_T_1430, UInt<1>(0h0))
when _T_1431 :
node _T_1432 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1433 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1434 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1435 = or(_T_1432, _T_1433)
node _T_1436 = or(_T_1435, _T_1434)
node _T_1437 = eq(io.rw.addr, UInt<9>(0h106))
node _T_1438 = and(_T_1436, _T_1437)
else :
node _T_1439 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1440 = eq(io.rw.addr, UInt<9>(0h106))
node _T_1441 = and(_T_1439, _T_1440)
node _T_1442 = andr(UInt<2>(0h0))
node _T_1443 = eq(_T_1442, UInt<1>(0h0))
when _T_1443 :
node _T_1444 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1445 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1446 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1447 = or(_T_1444, _T_1445)
node _T_1448 = or(_T_1447, _T_1446)
node _T_1449 = eq(io.rw.addr, UInt<10>(0h303))
node _T_1450 = and(_T_1448, _T_1449)
else :
node _T_1451 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1452 = eq(io.rw.addr, UInt<10>(0h303))
node _T_1453 = and(_T_1451, _T_1452)
node _T_1454 = andr(UInt<2>(0h0))
node _T_1455 = eq(_T_1454, UInt<1>(0h0))
when _T_1455 :
node _T_1456 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1457 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1458 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1459 = or(_T_1456, _T_1457)
node _T_1460 = or(_T_1459, _T_1458)
node _T_1461 = eq(io.rw.addr, UInt<10>(0h302))
node _T_1462 = and(_T_1460, _T_1461)
else :
node _T_1463 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1464 = eq(io.rw.addr, UInt<10>(0h302))
node _T_1465 = and(_T_1463, _T_1464)
node _T_1466 = andr(UInt<2>(0h0))
node _T_1467 = eq(_T_1466, UInt<1>(0h0))
when _T_1467 :
node _T_1468 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1469 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1470 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1471 = or(_T_1468, _T_1469)
node _T_1472 = or(_T_1471, _T_1470)
node _T_1473 = eq(io.rw.addr, UInt<9>(0h10a))
node _T_1474 = and(_T_1472, _T_1473)
else :
node _T_1475 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1476 = eq(io.rw.addr, UInt<9>(0h10a))
node _T_1477 = and(_T_1475, _T_1476)
node _T_1478 = andr(UInt<2>(0h0))
node _T_1479 = eq(_T_1478, UInt<1>(0h0))
when _T_1479 :
node _T_1480 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1481 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1482 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1483 = or(_T_1480, _T_1481)
node _T_1484 = or(_T_1483, _T_1482)
node _T_1485 = eq(io.rw.addr, UInt<10>(0h3a0))
node _T_1486 = and(_T_1484, _T_1485)
else :
node _T_1487 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1488 = eq(io.rw.addr, UInt<10>(0h3a0))
node _T_1489 = and(_T_1487, _T_1488)
node _T_1490 = andr(UInt<2>(0h0))
node _T_1491 = eq(_T_1490, UInt<1>(0h0))
when _T_1491 :
node _T_1492 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1493 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1494 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1495 = or(_T_1492, _T_1493)
node _T_1496 = or(_T_1495, _T_1494)
node _T_1497 = eq(io.rw.addr, UInt<10>(0h3a2))
node _T_1498 = and(_T_1496, _T_1497)
else :
node _T_1499 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1500 = eq(io.rw.addr, UInt<10>(0h3a2))
node _T_1501 = and(_T_1499, _T_1500)
node _T_1502 = andr(UInt<2>(0h0))
node _T_1503 = eq(_T_1502, UInt<1>(0h0))
when _T_1503 :
node _T_1504 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1505 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1506 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1507 = or(_T_1504, _T_1505)
node _T_1508 = or(_T_1507, _T_1506)
node _T_1509 = eq(io.rw.addr, UInt<10>(0h3b0))
node _T_1510 = and(_T_1508, _T_1509)
else :
node _T_1511 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1512 = eq(io.rw.addr, UInt<10>(0h3b0))
node _T_1513 = and(_T_1511, _T_1512)
node _T_1514 = andr(UInt<2>(0h0))
node _T_1515 = eq(_T_1514, UInt<1>(0h0))
when _T_1515 :
node _T_1516 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1517 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1518 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1519 = or(_T_1516, _T_1517)
node _T_1520 = or(_T_1519, _T_1518)
node _T_1521 = eq(io.rw.addr, UInt<10>(0h3b1))
node _T_1522 = and(_T_1520, _T_1521)
else :
node _T_1523 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1524 = eq(io.rw.addr, UInt<10>(0h3b1))
node _T_1525 = and(_T_1523, _T_1524)
node _T_1526 = andr(UInt<2>(0h0))
node _T_1527 = eq(_T_1526, UInt<1>(0h0))
when _T_1527 :
node _T_1528 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1529 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1530 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1531 = or(_T_1528, _T_1529)
node _T_1532 = or(_T_1531, _T_1530)
node _T_1533 = eq(io.rw.addr, UInt<10>(0h3b2))
node _T_1534 = and(_T_1532, _T_1533)
else :
node _T_1535 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1536 = eq(io.rw.addr, UInt<10>(0h3b2))
node _T_1537 = and(_T_1535, _T_1536)
node _T_1538 = andr(UInt<2>(0h0))
node _T_1539 = eq(_T_1538, UInt<1>(0h0))
when _T_1539 :
node _T_1540 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1541 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1542 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1543 = or(_T_1540, _T_1541)
node _T_1544 = or(_T_1543, _T_1542)
node _T_1545 = eq(io.rw.addr, UInt<10>(0h3b3))
node _T_1546 = and(_T_1544, _T_1545)
else :
node _T_1547 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1548 = eq(io.rw.addr, UInt<10>(0h3b3))
node _T_1549 = and(_T_1547, _T_1548)
node _T_1550 = andr(UInt<2>(0h0))
node _T_1551 = eq(_T_1550, UInt<1>(0h0))
when _T_1551 :
node _T_1552 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1553 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1554 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1555 = or(_T_1552, _T_1553)
node _T_1556 = or(_T_1555, _T_1554)
node _T_1557 = eq(io.rw.addr, UInt<10>(0h3b4))
node _T_1558 = and(_T_1556, _T_1557)
else :
node _T_1559 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1560 = eq(io.rw.addr, UInt<10>(0h3b4))
node _T_1561 = and(_T_1559, _T_1560)
node _T_1562 = andr(UInt<2>(0h0))
node _T_1563 = eq(_T_1562, UInt<1>(0h0))
when _T_1563 :
node _T_1564 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1565 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1566 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1567 = or(_T_1564, _T_1565)
node _T_1568 = or(_T_1567, _T_1566)
node _T_1569 = eq(io.rw.addr, UInt<10>(0h3b5))
node _T_1570 = and(_T_1568, _T_1569)
else :
node _T_1571 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1572 = eq(io.rw.addr, UInt<10>(0h3b5))
node _T_1573 = and(_T_1571, _T_1572)
node _T_1574 = andr(UInt<2>(0h0))
node _T_1575 = eq(_T_1574, UInt<1>(0h0))
when _T_1575 :
node _T_1576 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1577 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1578 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1579 = or(_T_1576, _T_1577)
node _T_1580 = or(_T_1579, _T_1578)
node _T_1581 = eq(io.rw.addr, UInt<10>(0h3b6))
node _T_1582 = and(_T_1580, _T_1581)
else :
node _T_1583 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1584 = eq(io.rw.addr, UInt<10>(0h3b6))
node _T_1585 = and(_T_1583, _T_1584)
node _T_1586 = andr(UInt<2>(0h0))
node _T_1587 = eq(_T_1586, UInt<1>(0h0))
when _T_1587 :
node _T_1588 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1589 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1590 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1591 = or(_T_1588, _T_1589)
node _T_1592 = or(_T_1591, _T_1590)
node _T_1593 = eq(io.rw.addr, UInt<10>(0h3b7))
node _T_1594 = and(_T_1592, _T_1593)
else :
node _T_1595 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1596 = eq(io.rw.addr, UInt<10>(0h3b7))
node _T_1597 = and(_T_1595, _T_1596)
node _T_1598 = andr(UInt<2>(0h0))
node _T_1599 = eq(_T_1598, UInt<1>(0h0))
when _T_1599 :
node _T_1600 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1601 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1602 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1603 = or(_T_1600, _T_1601)
node _T_1604 = or(_T_1603, _T_1602)
node _T_1605 = eq(io.rw.addr, UInt<10>(0h3b8))
node _T_1606 = and(_T_1604, _T_1605)
else :
node _T_1607 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1608 = eq(io.rw.addr, UInt<10>(0h3b8))
node _T_1609 = and(_T_1607, _T_1608)
node _T_1610 = andr(UInt<2>(0h0))
node _T_1611 = eq(_T_1610, UInt<1>(0h0))
when _T_1611 :
node _T_1612 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1613 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1614 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1615 = or(_T_1612, _T_1613)
node _T_1616 = or(_T_1615, _T_1614)
node _T_1617 = eq(io.rw.addr, UInt<10>(0h3b9))
node _T_1618 = and(_T_1616, _T_1617)
else :
node _T_1619 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1620 = eq(io.rw.addr, UInt<10>(0h3b9))
node _T_1621 = and(_T_1619, _T_1620)
node _T_1622 = andr(UInt<2>(0h0))
node _T_1623 = eq(_T_1622, UInt<1>(0h0))
when _T_1623 :
node _T_1624 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1625 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1626 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1627 = or(_T_1624, _T_1625)
node _T_1628 = or(_T_1627, _T_1626)
node _T_1629 = eq(io.rw.addr, UInt<10>(0h3ba))
node _T_1630 = and(_T_1628, _T_1629)
else :
node _T_1631 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1632 = eq(io.rw.addr, UInt<10>(0h3ba))
node _T_1633 = and(_T_1631, _T_1632)
node _T_1634 = andr(UInt<2>(0h0))
node _T_1635 = eq(_T_1634, UInt<1>(0h0))
when _T_1635 :
node _T_1636 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1637 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1638 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1639 = or(_T_1636, _T_1637)
node _T_1640 = or(_T_1639, _T_1638)
node _T_1641 = eq(io.rw.addr, UInt<10>(0h3bb))
node _T_1642 = and(_T_1640, _T_1641)
else :
node _T_1643 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1644 = eq(io.rw.addr, UInt<10>(0h3bb))
node _T_1645 = and(_T_1643, _T_1644)
node _T_1646 = andr(UInt<2>(0h0))
node _T_1647 = eq(_T_1646, UInt<1>(0h0))
when _T_1647 :
node _T_1648 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1649 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1650 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1651 = or(_T_1648, _T_1649)
node _T_1652 = or(_T_1651, _T_1650)
node _T_1653 = eq(io.rw.addr, UInt<10>(0h3bc))
node _T_1654 = and(_T_1652, _T_1653)
else :
node _T_1655 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1656 = eq(io.rw.addr, UInt<10>(0h3bc))
node _T_1657 = and(_T_1655, _T_1656)
node _T_1658 = andr(UInt<2>(0h0))
node _T_1659 = eq(_T_1658, UInt<1>(0h0))
when _T_1659 :
node _T_1660 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1661 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1662 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1663 = or(_T_1660, _T_1661)
node _T_1664 = or(_T_1663, _T_1662)
node _T_1665 = eq(io.rw.addr, UInt<10>(0h3bd))
node _T_1666 = and(_T_1664, _T_1665)
else :
node _T_1667 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1668 = eq(io.rw.addr, UInt<10>(0h3bd))
node _T_1669 = and(_T_1667, _T_1668)
node _T_1670 = andr(UInt<2>(0h0))
node _T_1671 = eq(_T_1670, UInt<1>(0h0))
when _T_1671 :
node _T_1672 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1673 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1674 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1675 = or(_T_1672, _T_1673)
node _T_1676 = or(_T_1675, _T_1674)
node _T_1677 = eq(io.rw.addr, UInt<10>(0h3be))
node _T_1678 = and(_T_1676, _T_1677)
else :
node _T_1679 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1680 = eq(io.rw.addr, UInt<10>(0h3be))
node _T_1681 = and(_T_1679, _T_1680)
node _T_1682 = andr(UInt<2>(0h0))
node _T_1683 = eq(_T_1682, UInt<1>(0h0))
when _T_1683 :
node _T_1684 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1685 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1686 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1687 = or(_T_1684, _T_1685)
node _T_1688 = or(_T_1687, _T_1686)
node _T_1689 = eq(io.rw.addr, UInt<10>(0h3bf))
node _T_1690 = and(_T_1688, _T_1689)
else :
node _T_1691 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1692 = eq(io.rw.addr, UInt<10>(0h3bf))
node _T_1693 = and(_T_1691, _T_1692)
node _T_1694 = andr(UInt<2>(0h2))
node _T_1695 = eq(_T_1694, UInt<1>(0h0))
when _T_1695 :
node _T_1696 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1697 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1698 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1699 = or(_T_1696, _T_1697)
node _T_1700 = or(_T_1699, _T_1698)
node _T_1701 = eq(io.rw.addr, UInt<12>(0h800))
node _T_1702 = and(_T_1700, _T_1701)
else :
node _T_1703 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1704 = eq(io.rw.addr, UInt<12>(0h800))
node _T_1705 = and(_T_1703, _T_1704)
node _T_1706 = andr(UInt<2>(0h2))
node _T_1707 = eq(_T_1706, UInt<1>(0h0))
when _T_1707 :
node _T_1708 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1709 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1710 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1711 = or(_T_1708, _T_1709)
node _T_1712 = or(_T_1711, _T_1710)
node _T_1713 = eq(io.rw.addr, UInt<12>(0h808))
node _T_1714 = and(_T_1712, _T_1713)
else :
node _T_1715 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1716 = eq(io.rw.addr, UInt<12>(0h808))
node _T_1717 = and(_T_1715, _T_1716)
node _T_1718 = andr(UInt<2>(0h1))
node _T_1719 = eq(_T_1718, UInt<1>(0h0))
when _T_1719 :
node _T_1720 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1721 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1722 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1723 = or(_T_1720, _T_1721)
node _T_1724 = or(_T_1723, _T_1722)
node _T_1725 = eq(io.rw.addr, UInt<11>(0h7c1))
node _T_1726 = and(_T_1724, _T_1725)
else :
node _T_1727 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1728 = eq(io.rw.addr, UInt<11>(0h7c1))
node _T_1729 = and(_T_1727, _T_1728)
node _T_1730 = andr(UInt<2>(0h3))
node _T_1731 = eq(_T_1730, UInt<1>(0h0))
when _T_1731 :
node _T_1732 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1733 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1734 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1735 = or(_T_1732, _T_1733)
node _T_1736 = or(_T_1735, _T_1734)
node _T_1737 = eq(io.rw.addr, UInt<12>(0hf12))
node _T_1738 = and(_T_1736, _T_1737)
else :
node _T_1739 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1740 = eq(io.rw.addr, UInt<12>(0hf12))
node _T_1741 = and(_T_1739, _T_1740)
node _T_1742 = andr(UInt<2>(0h3))
node _T_1743 = eq(_T_1742, UInt<1>(0h0))
when _T_1743 :
node _T_1744 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1745 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1746 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1747 = or(_T_1744, _T_1745)
node _T_1748 = or(_T_1747, _T_1746)
node _T_1749 = eq(io.rw.addr, UInt<12>(0hf13))
node _T_1750 = and(_T_1748, _T_1749)
else :
node _T_1751 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1752 = eq(io.rw.addr, UInt<12>(0hf13))
node _T_1753 = and(_T_1751, _T_1752)
node _T_1754 = andr(UInt<2>(0h3))
node _T_1755 = eq(_T_1754, UInt<1>(0h0))
when _T_1755 :
node _T_1756 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1757 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1758 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1759 = or(_T_1756, _T_1757)
node _T_1760 = or(_T_1759, _T_1758)
node _T_1761 = eq(io.rw.addr, UInt<12>(0hf11))
node _T_1762 = and(_T_1760, _T_1761)
else :
node _T_1763 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1764 = eq(io.rw.addr, UInt<12>(0hf11))
node _T_1765 = and(_T_1763, _T_1764)
node _T_1766 = andr(UInt<2>(0h3))
node _T_1767 = eq(_T_1766, UInt<1>(0h0))
when _T_1767 :
node _T_1768 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1769 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1770 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1771 = or(_T_1768, _T_1769)
node _T_1772 = or(_T_1771, _T_1770)
node _T_1773 = eq(io.rw.addr, UInt<12>(0hf15))
node _T_1774 = and(_T_1772, _T_1773)
else :
node _T_1775 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1776 = eq(io.rw.addr, UInt<12>(0hf15))
node _T_1777 = and(_T_1775, _T_1776)
wire set_vs_dirty : UInt<1>
connect set_vs_dirty, UInt<1>(0h0)
wire set_fs_dirty : UInt<1>
connect set_fs_dirty, io.set_fs_dirty
when set_fs_dirty :
node _T_1778 = gt(reg_mstatus.fs, UInt<1>(0h0))
node _T_1779 = asUInt(reset)
node _T_1780 = eq(_T_1779, UInt<1>(0h0))
when _T_1780 :
node _T_1781 = eq(_T_1778, UInt<1>(0h0))
when _T_1781 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at CSR.scala:1203 assert(reg_mstatus.fs > 0.U)\n") : printf_3
assert(clock, _T_1778, UInt<1>(0h1), "") : assert_3
when reg_mstatus.v :
connect reg_vsstatus.fs, UInt<2>(0h3)
connect reg_mstatus.fs, UInt<2>(0h3)
connect io.fcsr_rm, reg_frm
when io.fcsr_flags.valid :
node _reg_fflags_T = or(reg_fflags, io.fcsr_flags.bits)
connect reg_fflags, _reg_fflags_T
connect set_fs_dirty, UInt<1>(0h1)
node _csr_wen_T = eq(io.rw.cmd, UInt<3>(0h6))
node _csr_wen_T_1 = eq(io.rw.cmd, UInt<3>(0h7))
node _csr_wen_T_2 = eq(io.rw.cmd, UInt<3>(0h5))
node _csr_wen_T_3 = or(_csr_wen_T, _csr_wen_T_1)
node _csr_wen_T_4 = or(_csr_wen_T_3, _csr_wen_T_2)
node _csr_wen_T_5 = eq(io.rw_stall, UInt<1>(0h0))
node csr_wen = and(_csr_wen_T_4, _csr_wen_T_5)
node _io_csrw_counter_T = and(UInt<1>(0h1), csr_wen)
node _io_csrw_counter_T_1 = geq(io.rw.addr, UInt<12>(0hb00))
node _io_csrw_counter_T_2 = lt(io.rw.addr, UInt<12>(0hb20))
node _io_csrw_counter_T_3 = and(_io_csrw_counter_T_1, _io_csrw_counter_T_2)
node _io_csrw_counter_T_4 = geq(io.rw.addr, UInt<12>(0hb80))
node _io_csrw_counter_T_5 = lt(io.rw.addr, UInt<12>(0hba0))
node _io_csrw_counter_T_6 = and(_io_csrw_counter_T_4, _io_csrw_counter_T_5)
node _io_csrw_counter_T_7 = or(_io_csrw_counter_T_3, _io_csrw_counter_T_6)
node _io_csrw_counter_T_8 = and(_io_csrw_counter_T, _io_csrw_counter_T_7)
node _io_csrw_counter_T_9 = bits(io.rw.addr, 5, 0)
node _io_csrw_counter_T_10 = dshl(UInt<1>(0h1), _io_csrw_counter_T_9)
node _io_csrw_counter_T_11 = mux(_io_csrw_counter_T_8, _io_csrw_counter_T_10, UInt<1>(0h0))
connect io.csrw_counter, _io_csrw_counter_T_11
when csr_wen :
when decoded_addr_101_2 :
wire new_mstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}
wire _new_mstatus_WIRE : UInt<105>
connect _new_mstatus_WIRE, wdata
node _new_mstatus_T = bits(_new_mstatus_WIRE, 0, 0)
connect new_mstatus.uie, _new_mstatus_T
node _new_mstatus_T_1 = bits(_new_mstatus_WIRE, 1, 1)
connect new_mstatus.sie, _new_mstatus_T_1
node _new_mstatus_T_2 = bits(_new_mstatus_WIRE, 2, 2)
connect new_mstatus.hie, _new_mstatus_T_2
node _new_mstatus_T_3 = bits(_new_mstatus_WIRE, 3, 3)
connect new_mstatus.mie, _new_mstatus_T_3
node _new_mstatus_T_4 = bits(_new_mstatus_WIRE, 4, 4)
connect new_mstatus.upie, _new_mstatus_T_4
node _new_mstatus_T_5 = bits(_new_mstatus_WIRE, 5, 5)
connect new_mstatus.spie, _new_mstatus_T_5
node _new_mstatus_T_6 = bits(_new_mstatus_WIRE, 6, 6)
connect new_mstatus.ube, _new_mstatus_T_6
node _new_mstatus_T_7 = bits(_new_mstatus_WIRE, 7, 7)
connect new_mstatus.mpie, _new_mstatus_T_7
node _new_mstatus_T_8 = bits(_new_mstatus_WIRE, 8, 8)
connect new_mstatus.spp, _new_mstatus_T_8
node _new_mstatus_T_9 = bits(_new_mstatus_WIRE, 10, 9)
connect new_mstatus.vs, _new_mstatus_T_9
node _new_mstatus_T_10 = bits(_new_mstatus_WIRE, 12, 11)
connect new_mstatus.mpp, _new_mstatus_T_10
node _new_mstatus_T_11 = bits(_new_mstatus_WIRE, 14, 13)
connect new_mstatus.fs, _new_mstatus_T_11
node _new_mstatus_T_12 = bits(_new_mstatus_WIRE, 16, 15)
connect new_mstatus.xs, _new_mstatus_T_12
node _new_mstatus_T_13 = bits(_new_mstatus_WIRE, 17, 17)
connect new_mstatus.mprv, _new_mstatus_T_13
node _new_mstatus_T_14 = bits(_new_mstatus_WIRE, 18, 18)
connect new_mstatus.sum, _new_mstatus_T_14
node _new_mstatus_T_15 = bits(_new_mstatus_WIRE, 19, 19)
connect new_mstatus.mxr, _new_mstatus_T_15
node _new_mstatus_T_16 = bits(_new_mstatus_WIRE, 20, 20)
connect new_mstatus.tvm, _new_mstatus_T_16
node _new_mstatus_T_17 = bits(_new_mstatus_WIRE, 21, 21)
connect new_mstatus.tw, _new_mstatus_T_17
node _new_mstatus_T_18 = bits(_new_mstatus_WIRE, 22, 22)
connect new_mstatus.tsr, _new_mstatus_T_18
node _new_mstatus_T_19 = bits(_new_mstatus_WIRE, 30, 23)
connect new_mstatus.zero1, _new_mstatus_T_19
node _new_mstatus_T_20 = bits(_new_mstatus_WIRE, 31, 31)
connect new_mstatus.sd_rv32, _new_mstatus_T_20
node _new_mstatus_T_21 = bits(_new_mstatus_WIRE, 33, 32)
connect new_mstatus.uxl, _new_mstatus_T_21
node _new_mstatus_T_22 = bits(_new_mstatus_WIRE, 35, 34)
connect new_mstatus.sxl, _new_mstatus_T_22
node _new_mstatus_T_23 = bits(_new_mstatus_WIRE, 36, 36)
connect new_mstatus.sbe, _new_mstatus_T_23
node _new_mstatus_T_24 = bits(_new_mstatus_WIRE, 37, 37)
connect new_mstatus.mbe, _new_mstatus_T_24
node _new_mstatus_T_25 = bits(_new_mstatus_WIRE, 38, 38)
connect new_mstatus.gva, _new_mstatus_T_25
node _new_mstatus_T_26 = bits(_new_mstatus_WIRE, 39, 39)
connect new_mstatus.mpv, _new_mstatus_T_26
node _new_mstatus_T_27 = bits(_new_mstatus_WIRE, 62, 40)
connect new_mstatus.zero2, _new_mstatus_T_27
node _new_mstatus_T_28 = bits(_new_mstatus_WIRE, 63, 63)
connect new_mstatus.sd, _new_mstatus_T_28
node _new_mstatus_T_29 = bits(_new_mstatus_WIRE, 64, 64)
connect new_mstatus.v, _new_mstatus_T_29
node _new_mstatus_T_30 = bits(_new_mstatus_WIRE, 66, 65)
connect new_mstatus.prv, _new_mstatus_T_30
node _new_mstatus_T_31 = bits(_new_mstatus_WIRE, 67, 67)
connect new_mstatus.dv, _new_mstatus_T_31
node _new_mstatus_T_32 = bits(_new_mstatus_WIRE, 69, 68)
connect new_mstatus.dprv, _new_mstatus_T_32
node _new_mstatus_T_33 = bits(_new_mstatus_WIRE, 101, 70)
connect new_mstatus.isa, _new_mstatus_T_33
node _new_mstatus_T_34 = bits(_new_mstatus_WIRE, 102, 102)
connect new_mstatus.wfi, _new_mstatus_T_34
node _new_mstatus_T_35 = bits(_new_mstatus_WIRE, 103, 103)
connect new_mstatus.cease, _new_mstatus_T_35
node _new_mstatus_T_36 = bits(_new_mstatus_WIRE, 104, 104)
connect new_mstatus.debug, _new_mstatus_T_36
connect reg_mstatus.mie, new_mstatus.mie
connect reg_mstatus.mpie, new_mstatus.mpie
connect reg_mstatus.mprv, new_mstatus.mprv
node _reg_mstatus_mpp_T_2 = eq(new_mstatus.mpp, UInt<2>(0h2))
node _reg_mstatus_mpp_T_3 = mux(_reg_mstatus_mpp_T_2, UInt<1>(0h0), new_mstatus.mpp)
connect reg_mstatus.mpp, _reg_mstatus_mpp_T_3
connect reg_mstatus.spp, new_mstatus.spp
connect reg_mstatus.spie, new_mstatus.spie
connect reg_mstatus.sie, new_mstatus.sie
connect reg_mstatus.tw, new_mstatus.tw
connect reg_mstatus.tsr, new_mstatus.tsr
connect reg_mstatus.mxr, new_mstatus.mxr
connect reg_mstatus.sum, new_mstatus.sum
connect reg_mstatus.tvm, new_mstatus.tvm
connect reg_mstatus.fs, new_mstatus.fs
connect reg_mstatus.vs, UInt<1>(0h0)
when decoded_addr_95_2 :
node f = bits(wdata, 5, 5)
node _T_1782 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _T_1783 = bits(io.pc, 1, 1)
node _T_1784 = eq(_T_1783, UInt<1>(0h0))
node _T_1785 = or(_T_1782, _T_1784)
node _T_1786 = bits(wdata, 2, 2)
node _T_1787 = or(_T_1785, _T_1786)
when _T_1787 :
skip
when decoded_addr_109_2 :
node new_mip_lo_lo_lo = cat(reg_mip.ssip, reg_mip.usip)
node new_mip_lo_lo_hi = cat(reg_mip.msip, reg_mip.vssip)
node new_mip_lo_lo = cat(new_mip_lo_lo_hi, new_mip_lo_lo_lo)
node new_mip_lo_hi_lo = cat(reg_mip.stip, reg_mip.utip)
node new_mip_lo_hi_hi = cat(reg_mip.mtip, reg_mip.vstip)
node new_mip_lo_hi = cat(new_mip_lo_hi_hi, new_mip_lo_hi_lo)
node new_mip_lo = cat(new_mip_lo_hi, new_mip_lo_lo)
node new_mip_hi_lo_lo = cat(reg_mip.seip, reg_mip.ueip)
node new_mip_hi_lo_hi = cat(reg_mip.meip, reg_mip.vseip)
node new_mip_hi_lo = cat(new_mip_hi_lo_hi, new_mip_hi_lo_lo)
node new_mip_hi_hi_lo = cat(reg_mip.rocc, reg_mip.sgeip)
node new_mip_hi_hi_hi_hi = cat(UInt<0>(0h0), reg_mip.zero1)
node new_mip_hi_hi_hi = cat(new_mip_hi_hi_hi_hi, reg_mip.debug)
node new_mip_hi_hi = cat(new_mip_hi_hi_hi, new_mip_hi_hi_lo)
node new_mip_hi = cat(new_mip_hi_hi, new_mip_hi_lo)
node _new_mip_T = cat(new_mip_hi, new_mip_lo)
node _new_mip_T_1 = bits(io.rw.cmd, 1, 1)
node _new_mip_T_2 = mux(_new_mip_T_1, _new_mip_T, UInt<1>(0h0))
node _new_mip_T_3 = or(_new_mip_T_2, io.rw.wdata)
node _new_mip_T_4 = bits(io.rw.cmd, 1, 0)
node _new_mip_T_5 = andr(_new_mip_T_4)
node _new_mip_T_6 = mux(_new_mip_T_5, io.rw.wdata, UInt<1>(0h0))
node _new_mip_T_7 = not(_new_mip_T_6)
node _new_mip_T_8 = and(_new_mip_T_3, _new_mip_T_7)
wire new_mip : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
wire _new_mip_WIRE : UInt<16>
connect _new_mip_WIRE, _new_mip_T_8
node _new_mip_T_9 = bits(_new_mip_WIRE, 0, 0)
connect new_mip.usip, _new_mip_T_9
node _new_mip_T_10 = bits(_new_mip_WIRE, 1, 1)
connect new_mip.ssip, _new_mip_T_10
node _new_mip_T_11 = bits(_new_mip_WIRE, 2, 2)
connect new_mip.vssip, _new_mip_T_11
node _new_mip_T_12 = bits(_new_mip_WIRE, 3, 3)
connect new_mip.msip, _new_mip_T_12
node _new_mip_T_13 = bits(_new_mip_WIRE, 4, 4)
connect new_mip.utip, _new_mip_T_13
node _new_mip_T_14 = bits(_new_mip_WIRE, 5, 5)
connect new_mip.stip, _new_mip_T_14
node _new_mip_T_15 = bits(_new_mip_WIRE, 6, 6)
connect new_mip.vstip, _new_mip_T_15
node _new_mip_T_16 = bits(_new_mip_WIRE, 7, 7)
connect new_mip.mtip, _new_mip_T_16
node _new_mip_T_17 = bits(_new_mip_WIRE, 8, 8)
connect new_mip.ueip, _new_mip_T_17
node _new_mip_T_18 = bits(_new_mip_WIRE, 9, 9)
connect new_mip.seip, _new_mip_T_18
node _new_mip_T_19 = bits(_new_mip_WIRE, 10, 10)
connect new_mip.vseip, _new_mip_T_19
node _new_mip_T_20 = bits(_new_mip_WIRE, 11, 11)
connect new_mip.meip, _new_mip_T_20
node _new_mip_T_21 = bits(_new_mip_WIRE, 12, 12)
connect new_mip.sgeip, _new_mip_T_21
node _new_mip_T_22 = bits(_new_mip_WIRE, 13, 13)
connect new_mip.rocc, _new_mip_T_22
node _new_mip_T_23 = bits(_new_mip_WIRE, 14, 14)
connect new_mip.debug, _new_mip_T_23
node _new_mip_T_24 = bits(_new_mip_WIRE, 15, 15)
connect new_mip.zero1, _new_mip_T_24
connect reg_mip.ssip, new_mip.ssip
connect reg_mip.stip, new_mip.stip
connect reg_mip.seip, new_mip.seip
when decoded_addr_77_2 :
node _reg_mie_T = and(wdata, supported_interrupts)
connect reg_mie, _reg_mie_T
when decoded_addr_134_2 :
node _reg_mepc_T = not(wdata)
node _reg_mepc_T_1 = or(_reg_mepc_T, UInt<1>(0h1))
node _reg_mepc_T_2 = not(_reg_mepc_T_1)
connect reg_mepc, _reg_mepc_T_2
when decoded_addr_131_2 :
connect reg_mscratch, wdata
when decoded_addr_72_2 :
connect reg_mtvec, wdata
when decoded_addr_29_2 :
node _reg_mcause_T = and(wdata, UInt<64>(0h800000000000000f))
connect reg_mcause, _reg_mcause_T
when decoded_addr_138_2 :
connect reg_mtval, wdata
when decoded_addr_17_2 :
node _T_1788 = bits(wdata, 39, 0)
connect small_2, _T_1788
node _large_T_12 = shr(_T_1788, 6)
connect large_2, _large_T_12
when decoded_addr_148_2 :
node _reg_hpmevent_0_T = and(wdata, UInt<14>(0h3f03))
connect reg_hpmevent_0, _reg_hpmevent_0_T
when decoded_addr_52_2 :
node _T_1789 = bits(wdata, 39, 0)
connect small_3, _T_1789
node _large_T_13 = shr(_T_1789, 6)
connect large_3, _large_T_13
when decoded_addr_84_2 :
node _reg_hpmevent_1_T = and(wdata, UInt<14>(0h3f03))
connect reg_hpmevent_1, _reg_hpmevent_1_T
when decoded_addr_132_2 :
node _reg_mcountinhibit_T = not(UInt<64>(0h2))
node _reg_mcountinhibit_T_1 = and(wdata, _reg_mcountinhibit_T)
connect reg_mcountinhibit, _reg_mcountinhibit_T_1
when decoded_addr_104_2 :
node _T_1790 = bits(wdata, 63, 0)
connect small_1, _T_1790
node _large_T_14 = shr(_T_1790, 6)
connect large_1, _large_T_14
when decoded_addr_123_2 :
node _T_1791 = bits(wdata, 63, 0)
connect small, _T_1791
node _large_T_15 = shr(_T_1791, 6)
connect large, _large_T_15
when decoded_addr_36_2 :
connect set_fs_dirty, UInt<1>(0h1)
connect reg_fflags, wdata
when decoded_addr_68_2 :
connect set_fs_dirty, UInt<1>(0h1)
connect reg_frm, wdata
when decoded_addr_100_2 :
connect set_fs_dirty, UInt<1>(0h1)
connect reg_fflags, wdata
node _reg_frm_T = shr(wdata, 5)
connect reg_frm, _reg_frm_T
when decoded_addr_49_2 :
wire new_dcsr : { xdebugver : UInt<2>, zero4 : UInt<2>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, v : UInt<1>, zero1 : UInt<2>, step : UInt<1>, prv : UInt<2>}
wire _new_dcsr_WIRE : UInt<32>
connect _new_dcsr_WIRE, wdata
node _new_dcsr_T = bits(_new_dcsr_WIRE, 1, 0)
connect new_dcsr.prv, _new_dcsr_T
node _new_dcsr_T_1 = bits(_new_dcsr_WIRE, 2, 2)
connect new_dcsr.step, _new_dcsr_T_1
node _new_dcsr_T_2 = bits(_new_dcsr_WIRE, 4, 3)
connect new_dcsr.zero1, _new_dcsr_T_2
node _new_dcsr_T_3 = bits(_new_dcsr_WIRE, 5, 5)
connect new_dcsr.v, _new_dcsr_T_3
node _new_dcsr_T_4 = bits(_new_dcsr_WIRE, 8, 6)
connect new_dcsr.cause, _new_dcsr_T_4
node _new_dcsr_T_5 = bits(_new_dcsr_WIRE, 9, 9)
connect new_dcsr.stoptime, _new_dcsr_T_5
node _new_dcsr_T_6 = bits(_new_dcsr_WIRE, 10, 10)
connect new_dcsr.stopcycle, _new_dcsr_T_6
node _new_dcsr_T_7 = bits(_new_dcsr_WIRE, 11, 11)
connect new_dcsr.zero2, _new_dcsr_T_7
node _new_dcsr_T_8 = bits(_new_dcsr_WIRE, 12, 12)
connect new_dcsr.ebreaku, _new_dcsr_T_8
node _new_dcsr_T_9 = bits(_new_dcsr_WIRE, 13, 13)
connect new_dcsr.ebreaks, _new_dcsr_T_9
node _new_dcsr_T_10 = bits(_new_dcsr_WIRE, 14, 14)
connect new_dcsr.ebreakh, _new_dcsr_T_10
node _new_dcsr_T_11 = bits(_new_dcsr_WIRE, 15, 15)
connect new_dcsr.ebreakm, _new_dcsr_T_11
node _new_dcsr_T_12 = bits(_new_dcsr_WIRE, 27, 16)
connect new_dcsr.zero3, _new_dcsr_T_12
node _new_dcsr_T_13 = bits(_new_dcsr_WIRE, 29, 28)
connect new_dcsr.zero4, _new_dcsr_T_13
node _new_dcsr_T_14 = bits(_new_dcsr_WIRE, 31, 30)
connect new_dcsr.xdebugver, _new_dcsr_T_14
connect reg_dcsr.step, new_dcsr.step
connect reg_dcsr.ebreakm, new_dcsr.ebreakm
connect reg_dcsr.ebreaks, new_dcsr.ebreaks
connect reg_dcsr.ebreaku, new_dcsr.ebreaku
node _reg_dcsr_prv_T = eq(new_dcsr.prv, UInt<2>(0h2))
node _reg_dcsr_prv_T_1 = mux(_reg_dcsr_prv_T, UInt<1>(0h0), new_dcsr.prv)
connect reg_dcsr.prv, _reg_dcsr_prv_T_1
when decoded_addr_90_2 :
node _reg_dpc_T = not(wdata)
node _reg_dpc_T_1 = or(_reg_dpc_T, UInt<1>(0h1))
node _reg_dpc_T_2 = not(_reg_dpc_T_1)
connect reg_dpc, _reg_dpc_T_2
when decoded_addr_57_2 :
connect reg_dscratch0, wdata
when decoded_addr_61_2 :
wire new_sstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}
wire _new_sstatus_WIRE : UInt<105>
connect _new_sstatus_WIRE, wdata
node _new_sstatus_T = bits(_new_sstatus_WIRE, 0, 0)
connect new_sstatus.uie, _new_sstatus_T
node _new_sstatus_T_1 = bits(_new_sstatus_WIRE, 1, 1)
connect new_sstatus.sie, _new_sstatus_T_1
node _new_sstatus_T_2 = bits(_new_sstatus_WIRE, 2, 2)
connect new_sstatus.hie, _new_sstatus_T_2
node _new_sstatus_T_3 = bits(_new_sstatus_WIRE, 3, 3)
connect new_sstatus.mie, _new_sstatus_T_3
node _new_sstatus_T_4 = bits(_new_sstatus_WIRE, 4, 4)
connect new_sstatus.upie, _new_sstatus_T_4
node _new_sstatus_T_5 = bits(_new_sstatus_WIRE, 5, 5)
connect new_sstatus.spie, _new_sstatus_T_5
node _new_sstatus_T_6 = bits(_new_sstatus_WIRE, 6, 6)
connect new_sstatus.ube, _new_sstatus_T_6
node _new_sstatus_T_7 = bits(_new_sstatus_WIRE, 7, 7)
connect new_sstatus.mpie, _new_sstatus_T_7
node _new_sstatus_T_8 = bits(_new_sstatus_WIRE, 8, 8)
connect new_sstatus.spp, _new_sstatus_T_8
node _new_sstatus_T_9 = bits(_new_sstatus_WIRE, 10, 9)
connect new_sstatus.vs, _new_sstatus_T_9
node _new_sstatus_T_10 = bits(_new_sstatus_WIRE, 12, 11)
connect new_sstatus.mpp, _new_sstatus_T_10
node _new_sstatus_T_11 = bits(_new_sstatus_WIRE, 14, 13)
connect new_sstatus.fs, _new_sstatus_T_11
node _new_sstatus_T_12 = bits(_new_sstatus_WIRE, 16, 15)
connect new_sstatus.xs, _new_sstatus_T_12
node _new_sstatus_T_13 = bits(_new_sstatus_WIRE, 17, 17)
connect new_sstatus.mprv, _new_sstatus_T_13
node _new_sstatus_T_14 = bits(_new_sstatus_WIRE, 18, 18)
connect new_sstatus.sum, _new_sstatus_T_14
node _new_sstatus_T_15 = bits(_new_sstatus_WIRE, 19, 19)
connect new_sstatus.mxr, _new_sstatus_T_15
node _new_sstatus_T_16 = bits(_new_sstatus_WIRE, 20, 20)
connect new_sstatus.tvm, _new_sstatus_T_16
node _new_sstatus_T_17 = bits(_new_sstatus_WIRE, 21, 21)
connect new_sstatus.tw, _new_sstatus_T_17
node _new_sstatus_T_18 = bits(_new_sstatus_WIRE, 22, 22)
connect new_sstatus.tsr, _new_sstatus_T_18
node _new_sstatus_T_19 = bits(_new_sstatus_WIRE, 30, 23)
connect new_sstatus.zero1, _new_sstatus_T_19
node _new_sstatus_T_20 = bits(_new_sstatus_WIRE, 31, 31)
connect new_sstatus.sd_rv32, _new_sstatus_T_20
node _new_sstatus_T_21 = bits(_new_sstatus_WIRE, 33, 32)
connect new_sstatus.uxl, _new_sstatus_T_21
node _new_sstatus_T_22 = bits(_new_sstatus_WIRE, 35, 34)
connect new_sstatus.sxl, _new_sstatus_T_22
node _new_sstatus_T_23 = bits(_new_sstatus_WIRE, 36, 36)
connect new_sstatus.sbe, _new_sstatus_T_23
node _new_sstatus_T_24 = bits(_new_sstatus_WIRE, 37, 37)
connect new_sstatus.mbe, _new_sstatus_T_24
node _new_sstatus_T_25 = bits(_new_sstatus_WIRE, 38, 38)
connect new_sstatus.gva, _new_sstatus_T_25
node _new_sstatus_T_26 = bits(_new_sstatus_WIRE, 39, 39)
connect new_sstatus.mpv, _new_sstatus_T_26
node _new_sstatus_T_27 = bits(_new_sstatus_WIRE, 62, 40)
connect new_sstatus.zero2, _new_sstatus_T_27
node _new_sstatus_T_28 = bits(_new_sstatus_WIRE, 63, 63)
connect new_sstatus.sd, _new_sstatus_T_28
node _new_sstatus_T_29 = bits(_new_sstatus_WIRE, 64, 64)
connect new_sstatus.v, _new_sstatus_T_29
node _new_sstatus_T_30 = bits(_new_sstatus_WIRE, 66, 65)
connect new_sstatus.prv, _new_sstatus_T_30
node _new_sstatus_T_31 = bits(_new_sstatus_WIRE, 67, 67)
connect new_sstatus.dv, _new_sstatus_T_31
node _new_sstatus_T_32 = bits(_new_sstatus_WIRE, 69, 68)
connect new_sstatus.dprv, _new_sstatus_T_32
node _new_sstatus_T_33 = bits(_new_sstatus_WIRE, 101, 70)
connect new_sstatus.isa, _new_sstatus_T_33
node _new_sstatus_T_34 = bits(_new_sstatus_WIRE, 102, 102)
connect new_sstatus.wfi, _new_sstatus_T_34
node _new_sstatus_T_35 = bits(_new_sstatus_WIRE, 103, 103)
connect new_sstatus.cease, _new_sstatus_T_35
node _new_sstatus_T_36 = bits(_new_sstatus_WIRE, 104, 104)
connect new_sstatus.debug, _new_sstatus_T_36
connect reg_mstatus.sie, new_sstatus.sie
connect reg_mstatus.spie, new_sstatus.spie
connect reg_mstatus.spp, new_sstatus.spp
connect reg_mstatus.fs, new_sstatus.fs
connect reg_mstatus.vs, UInt<1>(0h0)
connect reg_mstatus.mxr, new_sstatus.mxr
connect reg_mstatus.sum, new_sstatus.sum
when decoded_addr_48_2 :
node _new_sip_T = not(read_mideleg)
node _new_sip_T_1 = and(read_mip, _new_sip_T)
node _new_sip_T_2 = and(wdata, read_mideleg)
node _new_sip_T_3 = or(_new_sip_T_1, _new_sip_T_2)
wire new_sip : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
wire _new_sip_WIRE : UInt<16>
connect _new_sip_WIRE, _new_sip_T_3
node _new_sip_T_4 = bits(_new_sip_WIRE, 0, 0)
connect new_sip.usip, _new_sip_T_4
node _new_sip_T_5 = bits(_new_sip_WIRE, 1, 1)
connect new_sip.ssip, _new_sip_T_5
node _new_sip_T_6 = bits(_new_sip_WIRE, 2, 2)
connect new_sip.vssip, _new_sip_T_6
node _new_sip_T_7 = bits(_new_sip_WIRE, 3, 3)
connect new_sip.msip, _new_sip_T_7
node _new_sip_T_8 = bits(_new_sip_WIRE, 4, 4)
connect new_sip.utip, _new_sip_T_8
node _new_sip_T_9 = bits(_new_sip_WIRE, 5, 5)
connect new_sip.stip, _new_sip_T_9
node _new_sip_T_10 = bits(_new_sip_WIRE, 6, 6)
connect new_sip.vstip, _new_sip_T_10
node _new_sip_T_11 = bits(_new_sip_WIRE, 7, 7)
connect new_sip.mtip, _new_sip_T_11
node _new_sip_T_12 = bits(_new_sip_WIRE, 8, 8)
connect new_sip.ueip, _new_sip_T_12
node _new_sip_T_13 = bits(_new_sip_WIRE, 9, 9)
connect new_sip.seip, _new_sip_T_13
node _new_sip_T_14 = bits(_new_sip_WIRE, 10, 10)
connect new_sip.vseip, _new_sip_T_14
node _new_sip_T_15 = bits(_new_sip_WIRE, 11, 11)
connect new_sip.meip, _new_sip_T_15
node _new_sip_T_16 = bits(_new_sip_WIRE, 12, 12)
connect new_sip.sgeip, _new_sip_T_16
node _new_sip_T_17 = bits(_new_sip_WIRE, 13, 13)
connect new_sip.rocc, _new_sip_T_17
node _new_sip_T_18 = bits(_new_sip_WIRE, 14, 14)
connect new_sip.debug, _new_sip_T_18
node _new_sip_T_19 = bits(_new_sip_WIRE, 15, 15)
connect new_sip.zero1, _new_sip_T_19
connect reg_mip.ssip, new_sip.ssip
when decoded_addr_6_2 :
wire new_satp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}
wire _new_satp_WIRE : UInt<64>
connect _new_satp_WIRE, wdata
node _new_satp_T = bits(_new_satp_WIRE, 43, 0)
connect new_satp.ppn, _new_satp_T
node _new_satp_T_1 = bits(_new_satp_WIRE, 59, 44)
connect new_satp.asid, _new_satp_T_1
node _new_satp_T_2 = bits(_new_satp_WIRE, 63, 60)
connect new_satp.mode, _new_satp_T_2
node _T_1792 = eq(new_satp.mode, UInt<1>(0h0))
node _T_1793 = eq(new_satp.mode, UInt<4>(0h8))
node _T_1794 = or(_T_1792, _T_1793)
when _T_1794 :
node _reg_satp_mode_T = and(new_satp.mode, UInt<4>(0h8))
connect reg_satp.mode, _reg_satp_mode_T
node _reg_satp_ppn_T = bits(new_satp.ppn, 19, 0)
connect reg_satp.ppn, _reg_satp_ppn_T
when decoded_addr_44_2 :
node _reg_mie_T_1 = not(sie_mask)
node _reg_mie_T_2 = and(reg_mie, _reg_mie_T_1)
node _reg_mie_T_3 = and(wdata, sie_mask)
node _reg_mie_T_4 = or(_reg_mie_T_2, _reg_mie_T_3)
connect reg_mie, _reg_mie_T_4
when decoded_addr_15_2 :
connect reg_sscratch, wdata
when decoded_addr_28_2 :
node _reg_sepc_T = not(wdata)
node _reg_sepc_T_1 = or(_reg_sepc_T, UInt<1>(0h1))
node _reg_sepc_T_2 = not(_reg_sepc_T_1)
connect reg_sepc, _reg_sepc_T_2
when decoded_addr_25_2 :
connect reg_stvec, wdata
when decoded_addr_147_2 :
node _reg_scause_T = and(wdata, UInt<64>(0h800000000000001f))
connect reg_scause, _reg_scause_T
when decoded_addr_94_2 :
connect reg_stval, wdata
when decoded_addr_125_2 :
connect reg_mideleg, wdata
when decoded_addr_23_2 :
connect reg_medeleg, wdata
when decoded_addr_139_2 :
connect reg_scounteren, wdata
when decoded_addr_69_2 :
wire new_envcfg : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>}
wire _new_envcfg_WIRE : UInt<64>
connect _new_envcfg_WIRE, wdata
node _new_envcfg_T = bits(_new_envcfg_WIRE, 0, 0)
connect new_envcfg.fiom, _new_envcfg_T
node _new_envcfg_T_1 = bits(_new_envcfg_WIRE, 3, 1)
connect new_envcfg.zero3, _new_envcfg_T_1
node _new_envcfg_T_2 = bits(_new_envcfg_WIRE, 5, 4)
connect new_envcfg.cbie, _new_envcfg_T_2
node _new_envcfg_T_3 = bits(_new_envcfg_WIRE, 6, 6)
connect new_envcfg.cbcfe, _new_envcfg_T_3
node _new_envcfg_T_4 = bits(_new_envcfg_WIRE, 7, 7)
connect new_envcfg.cbze, _new_envcfg_T_4
node _new_envcfg_T_5 = bits(_new_envcfg_WIRE, 61, 8)
connect new_envcfg.zero54, _new_envcfg_T_5
node _new_envcfg_T_6 = bits(_new_envcfg_WIRE, 62, 62)
connect new_envcfg.pbmte, _new_envcfg_T_6
node _new_envcfg_T_7 = bits(_new_envcfg_WIRE, 63, 63)
connect new_envcfg.stce, _new_envcfg_T_7
connect reg_senvcfg.fiom, new_envcfg.fiom
when decoded_addr_35_2 :
connect reg_mcounteren, wdata
when decoded_addr_42_2 :
wire new_envcfg_1 : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>}
wire _new_envcfg_WIRE_1 : UInt<64>
connect _new_envcfg_WIRE_1, wdata
node _new_envcfg_T_8 = bits(_new_envcfg_WIRE_1, 0, 0)
connect new_envcfg_1.fiom, _new_envcfg_T_8
node _new_envcfg_T_9 = bits(_new_envcfg_WIRE_1, 3, 1)
connect new_envcfg_1.zero3, _new_envcfg_T_9
node _new_envcfg_T_10 = bits(_new_envcfg_WIRE_1, 5, 4)
connect new_envcfg_1.cbie, _new_envcfg_T_10
node _new_envcfg_T_11 = bits(_new_envcfg_WIRE_1, 6, 6)
connect new_envcfg_1.cbcfe, _new_envcfg_T_11
node _new_envcfg_T_12 = bits(_new_envcfg_WIRE_1, 7, 7)
connect new_envcfg_1.cbze, _new_envcfg_T_12
node _new_envcfg_T_13 = bits(_new_envcfg_WIRE_1, 61, 8)
connect new_envcfg_1.zero54, _new_envcfg_T_13
node _new_envcfg_T_14 = bits(_new_envcfg_WIRE_1, 62, 62)
connect new_envcfg_1.pbmte, _new_envcfg_T_14
node _new_envcfg_T_15 = bits(_new_envcfg_WIRE_1, 63, 63)
connect new_envcfg_1.stce, _new_envcfg_T_15
connect reg_menvcfg.fiom, new_envcfg_1.fiom
node _T_1795 = eq(reg_pmp[0].cfg.l, UInt<1>(0h0))
node _T_1796 = and(decoded_addr_143_2, _T_1795)
when _T_1796 :
node _newCfg_T = shr(wdata, 0)
wire newCfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}
wire _newCfg_WIRE : UInt<8>
connect _newCfg_WIRE, _newCfg_T
node _newCfg_T_1 = bits(_newCfg_WIRE, 0, 0)
connect newCfg.r, _newCfg_T_1
node _newCfg_T_2 = bits(_newCfg_WIRE, 1, 1)
connect newCfg.w, _newCfg_T_2
node _newCfg_T_3 = bits(_newCfg_WIRE, 2, 2)
connect newCfg.x, _newCfg_T_3
node _newCfg_T_4 = bits(_newCfg_WIRE, 4, 3)
connect newCfg.a, _newCfg_T_4
node _newCfg_T_5 = bits(_newCfg_WIRE, 6, 5)
connect newCfg.res, _newCfg_T_5
node _newCfg_T_6 = bits(_newCfg_WIRE, 7, 7)
connect newCfg.l, _newCfg_T_6
connect reg_pmp[0].cfg, newCfg
node _reg_pmp_0_cfg_w_T = and(newCfg.w, newCfg.r)
connect reg_pmp[0].cfg.w, _reg_pmp_0_cfg_w_T
node _T_1797 = bits(reg_pmp[1].cfg.a, 1, 1)
node _T_1798 = eq(_T_1797, UInt<1>(0h0))
node _T_1799 = bits(reg_pmp[1].cfg.a, 0, 0)
node _T_1800 = and(_T_1798, _T_1799)
node _T_1801 = and(reg_pmp[1].cfg.l, _T_1800)
node _T_1802 = or(reg_pmp[0].cfg.l, _T_1801)
node _T_1803 = eq(_T_1802, UInt<1>(0h0))
node _T_1804 = and(decoded_addr_105_2, _T_1803)
when _T_1804 :
connect reg_pmp[0].addr, wdata
node _T_1805 = eq(reg_pmp[1].cfg.l, UInt<1>(0h0))
node _T_1806 = and(decoded_addr_143_2, _T_1805)
when _T_1806 :
node _newCfg_T_7 = shr(wdata, 8)
wire newCfg_1 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}
wire _newCfg_WIRE_1 : UInt<8>
connect _newCfg_WIRE_1, _newCfg_T_7
node _newCfg_T_8 = bits(_newCfg_WIRE_1, 0, 0)
connect newCfg_1.r, _newCfg_T_8
node _newCfg_T_9 = bits(_newCfg_WIRE_1, 1, 1)
connect newCfg_1.w, _newCfg_T_9
node _newCfg_T_10 = bits(_newCfg_WIRE_1, 2, 2)
connect newCfg_1.x, _newCfg_T_10
node _newCfg_T_11 = bits(_newCfg_WIRE_1, 4, 3)
connect newCfg_1.a, _newCfg_T_11
node _newCfg_T_12 = bits(_newCfg_WIRE_1, 6, 5)
connect newCfg_1.res, _newCfg_T_12
node _newCfg_T_13 = bits(_newCfg_WIRE_1, 7, 7)
connect newCfg_1.l, _newCfg_T_13
connect reg_pmp[1].cfg, newCfg_1
node _reg_pmp_1_cfg_w_T = and(newCfg_1.w, newCfg_1.r)
connect reg_pmp[1].cfg.w, _reg_pmp_1_cfg_w_T
node _T_1807 = bits(reg_pmp[2].cfg.a, 1, 1)
node _T_1808 = eq(_T_1807, UInt<1>(0h0))
node _T_1809 = bits(reg_pmp[2].cfg.a, 0, 0)
node _T_1810 = and(_T_1808, _T_1809)
node _T_1811 = and(reg_pmp[2].cfg.l, _T_1810)
node _T_1812 = or(reg_pmp[1].cfg.l, _T_1811)
node _T_1813 = eq(_T_1812, UInt<1>(0h0))
node _T_1814 = and(decoded_addr_8_2, _T_1813)
when _T_1814 :
connect reg_pmp[1].addr, wdata
node _T_1815 = eq(reg_pmp[2].cfg.l, UInt<1>(0h0))
node _T_1816 = and(decoded_addr_143_2, _T_1815)
when _T_1816 :
node _newCfg_T_14 = shr(wdata, 16)
wire newCfg_2 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}
wire _newCfg_WIRE_2 : UInt<8>
connect _newCfg_WIRE_2, _newCfg_T_14
node _newCfg_T_15 = bits(_newCfg_WIRE_2, 0, 0)
connect newCfg_2.r, _newCfg_T_15
node _newCfg_T_16 = bits(_newCfg_WIRE_2, 1, 1)
connect newCfg_2.w, _newCfg_T_16
node _newCfg_T_17 = bits(_newCfg_WIRE_2, 2, 2)
connect newCfg_2.x, _newCfg_T_17
node _newCfg_T_18 = bits(_newCfg_WIRE_2, 4, 3)
connect newCfg_2.a, _newCfg_T_18
node _newCfg_T_19 = bits(_newCfg_WIRE_2, 6, 5)
connect newCfg_2.res, _newCfg_T_19
node _newCfg_T_20 = bits(_newCfg_WIRE_2, 7, 7)
connect newCfg_2.l, _newCfg_T_20
connect reg_pmp[2].cfg, newCfg_2
node _reg_pmp_2_cfg_w_T = and(newCfg_2.w, newCfg_2.r)
connect reg_pmp[2].cfg.w, _reg_pmp_2_cfg_w_T
node _T_1817 = bits(reg_pmp[3].cfg.a, 1, 1)
node _T_1818 = eq(_T_1817, UInt<1>(0h0))
node _T_1819 = bits(reg_pmp[3].cfg.a, 0, 0)
node _T_1820 = and(_T_1818, _T_1819)
node _T_1821 = and(reg_pmp[3].cfg.l, _T_1820)
node _T_1822 = or(reg_pmp[2].cfg.l, _T_1821)
node _T_1823 = eq(_T_1822, UInt<1>(0h0))
node _T_1824 = and(decoded_addr_127_2, _T_1823)
when _T_1824 :
connect reg_pmp[2].addr, wdata
node _T_1825 = eq(reg_pmp[3].cfg.l, UInt<1>(0h0))
node _T_1826 = and(decoded_addr_143_2, _T_1825)
when _T_1826 :
node _newCfg_T_21 = shr(wdata, 24)
wire newCfg_3 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}
wire _newCfg_WIRE_3 : UInt<8>
connect _newCfg_WIRE_3, _newCfg_T_21
node _newCfg_T_22 = bits(_newCfg_WIRE_3, 0, 0)
connect newCfg_3.r, _newCfg_T_22
node _newCfg_T_23 = bits(_newCfg_WIRE_3, 1, 1)
connect newCfg_3.w, _newCfg_T_23
node _newCfg_T_24 = bits(_newCfg_WIRE_3, 2, 2)
connect newCfg_3.x, _newCfg_T_24
node _newCfg_T_25 = bits(_newCfg_WIRE_3, 4, 3)
connect newCfg_3.a, _newCfg_T_25
node _newCfg_T_26 = bits(_newCfg_WIRE_3, 6, 5)
connect newCfg_3.res, _newCfg_T_26
node _newCfg_T_27 = bits(_newCfg_WIRE_3, 7, 7)
connect newCfg_3.l, _newCfg_T_27
connect reg_pmp[3].cfg, newCfg_3
node _reg_pmp_3_cfg_w_T = and(newCfg_3.w, newCfg_3.r)
connect reg_pmp[3].cfg.w, _reg_pmp_3_cfg_w_T
node _T_1827 = bits(reg_pmp[4].cfg.a, 1, 1)
node _T_1828 = eq(_T_1827, UInt<1>(0h0))
node _T_1829 = bits(reg_pmp[4].cfg.a, 0, 0)
node _T_1830 = and(_T_1828, _T_1829)
node _T_1831 = and(reg_pmp[4].cfg.l, _T_1830)
node _T_1832 = or(reg_pmp[3].cfg.l, _T_1831)
node _T_1833 = eq(_T_1832, UInt<1>(0h0))
node _T_1834 = and(decoded_addr_86_2, _T_1833)
when _T_1834 :
connect reg_pmp[3].addr, wdata
node _T_1835 = eq(reg_pmp[4].cfg.l, UInt<1>(0h0))
node _T_1836 = and(decoded_addr_143_2, _T_1835)
when _T_1836 :
node _newCfg_T_28 = shr(wdata, 32)
wire newCfg_4 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}
wire _newCfg_WIRE_4 : UInt<8>
connect _newCfg_WIRE_4, _newCfg_T_28
node _newCfg_T_29 = bits(_newCfg_WIRE_4, 0, 0)
connect newCfg_4.r, _newCfg_T_29
node _newCfg_T_30 = bits(_newCfg_WIRE_4, 1, 1)
connect newCfg_4.w, _newCfg_T_30
node _newCfg_T_31 = bits(_newCfg_WIRE_4, 2, 2)
connect newCfg_4.x, _newCfg_T_31
node _newCfg_T_32 = bits(_newCfg_WIRE_4, 4, 3)
connect newCfg_4.a, _newCfg_T_32
node _newCfg_T_33 = bits(_newCfg_WIRE_4, 6, 5)
connect newCfg_4.res, _newCfg_T_33
node _newCfg_T_34 = bits(_newCfg_WIRE_4, 7, 7)
connect newCfg_4.l, _newCfg_T_34
connect reg_pmp[4].cfg, newCfg_4
node _reg_pmp_4_cfg_w_T = and(newCfg_4.w, newCfg_4.r)
connect reg_pmp[4].cfg.w, _reg_pmp_4_cfg_w_T
node _T_1837 = bits(reg_pmp[5].cfg.a, 1, 1)
node _T_1838 = eq(_T_1837, UInt<1>(0h0))
node _T_1839 = bits(reg_pmp[5].cfg.a, 0, 0)
node _T_1840 = and(_T_1838, _T_1839)
node _T_1841 = and(reg_pmp[5].cfg.l, _T_1840)
node _T_1842 = or(reg_pmp[4].cfg.l, _T_1841)
node _T_1843 = eq(_T_1842, UInt<1>(0h0))
node _T_1844 = and(decoded_addr_54_2, _T_1843)
when _T_1844 :
connect reg_pmp[4].addr, wdata
node _T_1845 = eq(reg_pmp[5].cfg.l, UInt<1>(0h0))
node _T_1846 = and(decoded_addr_143_2, _T_1845)
when _T_1846 :
node _newCfg_T_35 = shr(wdata, 40)
wire newCfg_5 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}
wire _newCfg_WIRE_5 : UInt<8>
connect _newCfg_WIRE_5, _newCfg_T_35
node _newCfg_T_36 = bits(_newCfg_WIRE_5, 0, 0)
connect newCfg_5.r, _newCfg_T_36
node _newCfg_T_37 = bits(_newCfg_WIRE_5, 1, 1)
connect newCfg_5.w, _newCfg_T_37
node _newCfg_T_38 = bits(_newCfg_WIRE_5, 2, 2)
connect newCfg_5.x, _newCfg_T_38
node _newCfg_T_39 = bits(_newCfg_WIRE_5, 4, 3)
connect newCfg_5.a, _newCfg_T_39
node _newCfg_T_40 = bits(_newCfg_WIRE_5, 6, 5)
connect newCfg_5.res, _newCfg_T_40
node _newCfg_T_41 = bits(_newCfg_WIRE_5, 7, 7)
connect newCfg_5.l, _newCfg_T_41
connect reg_pmp[5].cfg, newCfg_5
node _reg_pmp_5_cfg_w_T = and(newCfg_5.w, newCfg_5.r)
connect reg_pmp[5].cfg.w, _reg_pmp_5_cfg_w_T
node _T_1847 = bits(reg_pmp[6].cfg.a, 1, 1)
node _T_1848 = eq(_T_1847, UInt<1>(0h0))
node _T_1849 = bits(reg_pmp[6].cfg.a, 0, 0)
node _T_1850 = and(_T_1848, _T_1849)
node _T_1851 = and(reg_pmp[6].cfg.l, _T_1850)
node _T_1852 = or(reg_pmp[5].cfg.l, _T_1851)
node _T_1853 = eq(_T_1852, UInt<1>(0h0))
node _T_1854 = and(decoded_addr_20_2, _T_1853)
when _T_1854 :
connect reg_pmp[5].addr, wdata
node _T_1855 = eq(reg_pmp[6].cfg.l, UInt<1>(0h0))
node _T_1856 = and(decoded_addr_143_2, _T_1855)
when _T_1856 :
node _newCfg_T_42 = shr(wdata, 48)
wire newCfg_6 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}
wire _newCfg_WIRE_6 : UInt<8>
connect _newCfg_WIRE_6, _newCfg_T_42
node _newCfg_T_43 = bits(_newCfg_WIRE_6, 0, 0)
connect newCfg_6.r, _newCfg_T_43
node _newCfg_T_44 = bits(_newCfg_WIRE_6, 1, 1)
connect newCfg_6.w, _newCfg_T_44
node _newCfg_T_45 = bits(_newCfg_WIRE_6, 2, 2)
connect newCfg_6.x, _newCfg_T_45
node _newCfg_T_46 = bits(_newCfg_WIRE_6, 4, 3)
connect newCfg_6.a, _newCfg_T_46
node _newCfg_T_47 = bits(_newCfg_WIRE_6, 6, 5)
connect newCfg_6.res, _newCfg_T_47
node _newCfg_T_48 = bits(_newCfg_WIRE_6, 7, 7)
connect newCfg_6.l, _newCfg_T_48
connect reg_pmp[6].cfg, newCfg_6
node _reg_pmp_6_cfg_w_T = and(newCfg_6.w, newCfg_6.r)
connect reg_pmp[6].cfg.w, _reg_pmp_6_cfg_w_T
node _T_1857 = bits(reg_pmp[7].cfg.a, 1, 1)
node _T_1858 = eq(_T_1857, UInt<1>(0h0))
node _T_1859 = bits(reg_pmp[7].cfg.a, 0, 0)
node _T_1860 = and(_T_1858, _T_1859)
node _T_1861 = and(reg_pmp[7].cfg.l, _T_1860)
node _T_1862 = or(reg_pmp[6].cfg.l, _T_1861)
node _T_1863 = eq(_T_1862, UInt<1>(0h0))
node _T_1864 = and(decoded_addr_137_2, _T_1863)
when _T_1864 :
connect reg_pmp[6].addr, wdata
node _T_1865 = eq(reg_pmp[7].cfg.l, UInt<1>(0h0))
node _T_1866 = and(decoded_addr_143_2, _T_1865)
when _T_1866 :
node _newCfg_T_49 = shr(wdata, 56)
wire newCfg_7 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}
wire _newCfg_WIRE_7 : UInt<8>
connect _newCfg_WIRE_7, _newCfg_T_49
node _newCfg_T_50 = bits(_newCfg_WIRE_7, 0, 0)
connect newCfg_7.r, _newCfg_T_50
node _newCfg_T_51 = bits(_newCfg_WIRE_7, 1, 1)
connect newCfg_7.w, _newCfg_T_51
node _newCfg_T_52 = bits(_newCfg_WIRE_7, 2, 2)
connect newCfg_7.x, _newCfg_T_52
node _newCfg_T_53 = bits(_newCfg_WIRE_7, 4, 3)
connect newCfg_7.a, _newCfg_T_53
node _newCfg_T_54 = bits(_newCfg_WIRE_7, 6, 5)
connect newCfg_7.res, _newCfg_T_54
node _newCfg_T_55 = bits(_newCfg_WIRE_7, 7, 7)
connect newCfg_7.l, _newCfg_T_55
connect reg_pmp[7].cfg, newCfg_7
node _reg_pmp_7_cfg_w_T = and(newCfg_7.w, newCfg_7.r)
connect reg_pmp[7].cfg.w, _reg_pmp_7_cfg_w_T
node _T_1867 = bits(reg_pmp[7].cfg.a, 1, 1)
node _T_1868 = eq(_T_1867, UInt<1>(0h0))
node _T_1869 = bits(reg_pmp[7].cfg.a, 0, 0)
node _T_1870 = and(_T_1868, _T_1869)
node _T_1871 = and(reg_pmp[7].cfg.l, _T_1870)
node _T_1872 = or(reg_pmp[7].cfg.l, _T_1871)
node _T_1873 = eq(_T_1872, UInt<1>(0h0))
node _T_1874 = and(decoded_addr_116_2, _T_1873)
when _T_1874 :
connect reg_pmp[7].addr, wdata
when decoded_addr_76_2 :
node _reg_custom_0_T = and(wdata, UInt<64>(0h1))
node _reg_custom_0_T_1 = not(UInt<64>(0h1))
node _reg_custom_0_T_2 = and(reg_custom_0, _reg_custom_0_T_1)
node _reg_custom_0_T_3 = or(_reg_custom_0_T, _reg_custom_0_T_2)
connect reg_custom_0, _reg_custom_0_T_3
connect io.customCSRs[0].wen, UInt<1>(0h1)
when decoded_addr_118_2 :
node _reg_custom_1_T = and(wdata, UInt<64>(0h1))
node _reg_custom_1_T_1 = not(UInt<64>(0h1))
node _reg_custom_1_T_2 = and(reg_custom_1, _reg_custom_1_T_1)
node _reg_custom_1_T_3 = or(_reg_custom_1_T, _reg_custom_1_T_2)
connect reg_custom_1, _reg_custom_1_T_3
connect io.customCSRs[1].wen, UInt<1>(0h1)
when decoded_addr_18_2 :
node _reg_custom_2_T = and(wdata, UInt<64>(0h8))
node _reg_custom_2_T_1 = not(UInt<64>(0h8))
node _reg_custom_2_T_2 = and(reg_custom_2, _reg_custom_2_T_1)
node _reg_custom_2_T_3 = or(_reg_custom_2_T, _reg_custom_2_T_2)
connect reg_custom_2, _reg_custom_2_T_3
connect io.customCSRs[2].wen, UInt<1>(0h1)
when decoded_addr_3_2 :
node _reg_custom_3_T = and(wdata, UInt<64>(0h0))
node _reg_custom_3_T_1 = not(UInt<64>(0h0))
node _reg_custom_3_T_2 = and(reg_custom_3, _reg_custom_3_T_1)
node _reg_custom_3_T_3 = or(_reg_custom_3_T, _reg_custom_3_T_2)
connect reg_custom_3, _reg_custom_3_T_3
connect io.customCSRs[3].wen, UInt<1>(0h1)
when io.customCSRs[0].set :
node _reg_custom_0_T_4 = and(io.customCSRs[0].sdata, UInt<64>(0h1))
node _reg_custom_0_T_5 = not(UInt<64>(0h1))
node _reg_custom_0_T_6 = and(reg_custom_0, _reg_custom_0_T_5)
node _reg_custom_0_T_7 = or(_reg_custom_0_T_4, _reg_custom_0_T_6)
connect reg_custom_0, _reg_custom_0_T_7
when io.customCSRs[1].set :
node _reg_custom_1_T_4 = and(io.customCSRs[1].sdata, UInt<64>(0h1))
node _reg_custom_1_T_5 = not(UInt<64>(0h1))
node _reg_custom_1_T_6 = and(reg_custom_1, _reg_custom_1_T_5)
node _reg_custom_1_T_7 = or(_reg_custom_1_T_4, _reg_custom_1_T_6)
connect reg_custom_1, _reg_custom_1_T_7
when io.customCSRs[2].set :
node _reg_custom_2_T_4 = and(io.customCSRs[2].sdata, UInt<64>(0h8))
node _reg_custom_2_T_5 = not(UInt<64>(0h8))
node _reg_custom_2_T_6 = and(reg_custom_2, _reg_custom_2_T_5)
node _reg_custom_2_T_7 = or(_reg_custom_2_T_4, _reg_custom_2_T_6)
connect reg_custom_2, _reg_custom_2_T_7
when io.customCSRs[3].set :
node _reg_custom_3_T_4 = and(io.customCSRs[3].sdata, UInt<64>(0h0))
node _reg_custom_3_T_5 = not(UInt<64>(0h0))
node _reg_custom_3_T_6 = and(reg_custom_3, _reg_custom_3_T_5)
node _reg_custom_3_T_7 = or(_reg_custom_3_T_4, _reg_custom_3_T_6)
connect reg_custom_3, _reg_custom_3_T_7
node _T_1875 = asUInt(reset)
when _T_1875 :
connect reg_satp.mode, UInt<1>(0h0)
connect reg_vsatp.mode, UInt<1>(0h0)
connect reg_hgatp.mode, UInt<1>(0h0)
connect reg_vsatp.mode, UInt<1>(0h0)
connect reg_vsatp.ppn, UInt<1>(0h0)
connect reg_vsatp.asid, UInt<1>(0h0)
connect reg_hgatp.mode, UInt<1>(0h0)
connect reg_hgatp.ppn, UInt<1>(0h0)
connect reg_hgatp.asid, UInt<1>(0h0)
connect reg_satp.asid, UInt<1>(0h0)
connect reg_vsatp.asid, UInt<1>(0h0)
connect reg_hgatp.asid, UInt<1>(0h0)
connect reg_vsstatus.xs, UInt<1>(0h0)
connect reg_tselect, UInt<1>(0h0)
connect reg_bp[0].control.ttype, UInt<2>(0h2)
connect reg_bp[0].control.maskmax, UInt<3>(0h4)
connect reg_bp[0].control.reserved, UInt<1>(0h0)
connect reg_bp[0].control.zero, UInt<1>(0h0)
connect reg_bp[0].control.h, UInt<1>(0h0)
node _T_1876 = asUInt(reset)
when _T_1876 :
connect reg_bp[0].control.action, UInt<1>(0h0)
connect reg_bp[0].control.dmode, UInt<1>(0h0)
connect reg_bp[0].control.chain, UInt<1>(0h0)
connect reg_bp[0].control.r, UInt<1>(0h0)
connect reg_bp[0].control.w, UInt<1>(0h0)
connect reg_bp[0].control.x, UInt<1>(0h0)
connect reg_bp[1].control.ttype, UInt<2>(0h2)
connect reg_bp[1].control.maskmax, UInt<3>(0h4)
connect reg_bp[1].control.reserved, UInt<1>(0h0)
connect reg_bp[1].control.zero, UInt<1>(0h0)
connect reg_bp[1].control.h, UInt<1>(0h0)
node _T_1877 = asUInt(reset)
when _T_1877 :
connect reg_bp[1].control.action, UInt<1>(0h0)
connect reg_bp[1].control.dmode, UInt<1>(0h0)
connect reg_bp[1].control.chain, UInt<1>(0h0)
connect reg_bp[1].control.r, UInt<1>(0h0)
connect reg_bp[1].control.w, UInt<1>(0h0)
connect reg_bp[1].control.x, UInt<1>(0h0)
connect reg_bp[0].textra.mselect, UInt<1>(0h0)
connect reg_bp[0].textra.sselect, UInt<1>(0h0)
connect reg_bp[1].textra.mselect, UInt<1>(0h0)
connect reg_bp[1].textra.sselect, UInt<1>(0h0)
wire _reg_bp_0_WIRE : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}
connect _reg_bp_0_WIRE.textra.sselect, UInt<1>(0h0)
connect _reg_bp_0_WIRE.textra.pad1, UInt<1>(0h0)
invalidate _reg_bp_0_WIRE.textra.svalue
connect _reg_bp_0_WIRE.textra.pad2, UInt<48>(0h0)
connect _reg_bp_0_WIRE.textra.mselect, UInt<1>(0h0)
invalidate _reg_bp_0_WIRE.textra.mvalue
connect _reg_bp_0_WIRE.address, UInt<39>(0h0)
connect _reg_bp_0_WIRE.control.r, UInt<1>(0h0)
connect _reg_bp_0_WIRE.control.w, UInt<1>(0h0)
connect _reg_bp_0_WIRE.control.x, UInt<1>(0h0)
connect _reg_bp_0_WIRE.control.u, UInt<1>(0h0)
connect _reg_bp_0_WIRE.control.s, UInt<1>(0h0)
connect _reg_bp_0_WIRE.control.h, UInt<1>(0h0)
connect _reg_bp_0_WIRE.control.m, UInt<1>(0h0)
connect _reg_bp_0_WIRE.control.tmatch, UInt<2>(0h0)
connect _reg_bp_0_WIRE.control.zero, UInt<2>(0h0)
connect _reg_bp_0_WIRE.control.chain, UInt<1>(0h0)
connect _reg_bp_0_WIRE.control.action, UInt<1>(0h0)
connect _reg_bp_0_WIRE.control.reserved, UInt<40>(0h0)
connect _reg_bp_0_WIRE.control.maskmax, UInt<6>(0h0)
connect _reg_bp_0_WIRE.control.dmode, UInt<1>(0h0)
connect _reg_bp_0_WIRE.control.ttype, UInt<4>(0h0)
connect reg_bp[0], _reg_bp_0_WIRE
wire _reg_bp_1_WIRE : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}
connect _reg_bp_1_WIRE.textra.sselect, UInt<1>(0h0)
connect _reg_bp_1_WIRE.textra.pad1, UInt<1>(0h0)
invalidate _reg_bp_1_WIRE.textra.svalue
connect _reg_bp_1_WIRE.textra.pad2, UInt<48>(0h0)
connect _reg_bp_1_WIRE.textra.mselect, UInt<1>(0h0)
invalidate _reg_bp_1_WIRE.textra.mvalue
connect _reg_bp_1_WIRE.address, UInt<39>(0h0)
connect _reg_bp_1_WIRE.control.r, UInt<1>(0h0)
connect _reg_bp_1_WIRE.control.w, UInt<1>(0h0)
connect _reg_bp_1_WIRE.control.x, UInt<1>(0h0)
connect _reg_bp_1_WIRE.control.u, UInt<1>(0h0)
connect _reg_bp_1_WIRE.control.s, UInt<1>(0h0)
connect _reg_bp_1_WIRE.control.h, UInt<1>(0h0)
connect _reg_bp_1_WIRE.control.m, UInt<1>(0h0)
connect _reg_bp_1_WIRE.control.tmatch, UInt<2>(0h0)
connect _reg_bp_1_WIRE.control.zero, UInt<2>(0h0)
connect _reg_bp_1_WIRE.control.chain, UInt<1>(0h0)
connect _reg_bp_1_WIRE.control.action, UInt<1>(0h0)
connect _reg_bp_1_WIRE.control.reserved, UInt<40>(0h0)
connect _reg_bp_1_WIRE.control.maskmax, UInt<6>(0h0)
connect _reg_bp_1_WIRE.control.dmode, UInt<1>(0h0)
connect _reg_bp_1_WIRE.control.ttype, UInt<4>(0h0)
connect reg_bp[1], _reg_bp_1_WIRE
connect reg_pmp[0].cfg.res, UInt<1>(0h0)
node _T_1878 = asUInt(reset)
when _T_1878 :
connect reg_pmp[0].cfg.a, UInt<1>(0h0)
connect reg_pmp[0].cfg.l, UInt<1>(0h0)
connect reg_pmp[1].cfg.res, UInt<1>(0h0)
node _T_1879 = asUInt(reset)
when _T_1879 :
connect reg_pmp[1].cfg.a, UInt<1>(0h0)
connect reg_pmp[1].cfg.l, UInt<1>(0h0)
connect reg_pmp[2].cfg.res, UInt<1>(0h0)
node _T_1880 = asUInt(reset)
when _T_1880 :
connect reg_pmp[2].cfg.a, UInt<1>(0h0)
connect reg_pmp[2].cfg.l, UInt<1>(0h0)
connect reg_pmp[3].cfg.res, UInt<1>(0h0)
node _T_1881 = asUInt(reset)
when _T_1881 :
connect reg_pmp[3].cfg.a, UInt<1>(0h0)
connect reg_pmp[3].cfg.l, UInt<1>(0h0)
connect reg_pmp[4].cfg.res, UInt<1>(0h0)
node _T_1882 = asUInt(reset)
when _T_1882 :
connect reg_pmp[4].cfg.a, UInt<1>(0h0)
connect reg_pmp[4].cfg.l, UInt<1>(0h0)
connect reg_pmp[5].cfg.res, UInt<1>(0h0)
node _T_1883 = asUInt(reset)
when _T_1883 :
connect reg_pmp[5].cfg.a, UInt<1>(0h0)
connect reg_pmp[5].cfg.l, UInt<1>(0h0)
connect reg_pmp[6].cfg.res, UInt<1>(0h0)
node _T_1884 = asUInt(reset)
when _T_1884 :
connect reg_pmp[6].cfg.a, UInt<1>(0h0)
connect reg_pmp[6].cfg.l, UInt<1>(0h0)
connect reg_pmp[7].cfg.res, UInt<1>(0h0)
node _T_1885 = asUInt(reset)
when _T_1885 :
connect reg_pmp[7].cfg.a, UInt<1>(0h0)
connect reg_pmp[7].cfg.l, UInt<1>(0h0)
node _io_trace_0_exception_T = geq(io.retire, UInt<1>(0h0))
node _io_trace_0_exception_T_1 = and(_io_trace_0_exception_T, exception)
connect io.trace[0].exception, _io_trace_0_exception_T_1
node _io_trace_0_valid_T = gt(io.retire, UInt<1>(0h0))
node _io_trace_0_valid_T_1 = or(_io_trace_0_valid_T, io.trace[0].exception)
connect io.trace[0].valid, _io_trace_0_valid_T_1
connect io.trace[0].insn, io.inst[0]
connect io.trace[0].iaddr, io.pc
node _io_trace_0_priv_T = cat(reg_debug, reg_mstatus.prv)
connect io.trace[0].priv, _io_trace_0_priv_T
connect io.trace[0].cause, cause
node _io_trace_0_interrupt_T = bits(cause, 63, 63)
connect io.trace[0].interrupt, _io_trace_0_interrupt_T
connect io.trace[0].tval, io.tval
node _io_trace_1_exception_T = geq(io.retire, UInt<1>(0h1))
node _io_trace_1_exception_T_1 = and(_io_trace_1_exception_T, exception)
connect io.trace[1].exception, _io_trace_1_exception_T_1
node _io_trace_1_valid_T = gt(io.retire, UInt<1>(0h1))
node _io_trace_1_valid_T_1 = or(_io_trace_1_valid_T, io.trace[1].exception)
connect io.trace[1].valid, _io_trace_1_valid_T_1
connect io.trace[1].insn, io.inst[1]
connect io.trace[1].iaddr, io.pc
node _io_trace_1_priv_T = cat(reg_debug, reg_mstatus.prv)
connect io.trace[1].priv, _io_trace_1_priv_T
connect io.trace[1].cause, cause
node _io_trace_1_interrupt_T = bits(cause, 63, 63)
connect io.trace[1].interrupt, _io_trace_1_interrupt_T
connect io.trace[1].tval, io.tval
node _io_trace_2_exception_T = geq(io.retire, UInt<2>(0h2))
node _io_trace_2_exception_T_1 = and(_io_trace_2_exception_T, exception)
connect io.trace[2].exception, _io_trace_2_exception_T_1
node _io_trace_2_valid_T = gt(io.retire, UInt<2>(0h2))
node _io_trace_2_valid_T_1 = or(_io_trace_2_valid_T, io.trace[2].exception)
connect io.trace[2].valid, _io_trace_2_valid_T_1
connect io.trace[2].insn, io.inst[2]
connect io.trace[2].iaddr, io.pc
node _io_trace_2_priv_T = cat(reg_debug, reg_mstatus.prv)
connect io.trace[2].priv, _io_trace_2_priv_T
connect io.trace[2].cause, cause
node _io_trace_2_interrupt_T = bits(cause, 63, 63)
connect io.trace[2].interrupt, _io_trace_2_interrupt_T
connect io.trace[2].tval, io.tval | module CSRFile( // @[CSR.scala:377:7]
input clock, // @[CSR.scala:377:7]
input reset, // @[CSR.scala:377:7]
input io_ungated_clock, // @[CSR.scala:384:14]
input io_interrupts_debug, // @[CSR.scala:384:14]
input io_interrupts_mtip, // @[CSR.scala:384:14]
input io_interrupts_msip, // @[CSR.scala:384:14]
input io_interrupts_meip, // @[CSR.scala:384:14]
input io_interrupts_seip, // @[CSR.scala:384:14]
input io_hartid, // @[CSR.scala:384:14]
input [11:0] io_rw_addr, // @[CSR.scala:384:14]
input [2:0] io_rw_cmd, // @[CSR.scala:384:14]
output [63:0] io_rw_rdata, // @[CSR.scala:384:14]
input [63:0] io_rw_wdata, // @[CSR.scala:384:14]
input [31:0] io_decode_0_inst, // @[CSR.scala:384:14]
output io_decode_0_fp_illegal, // @[CSR.scala:384:14]
output io_decode_0_fp_csr, // @[CSR.scala:384:14]
output io_decode_0_read_illegal, // @[CSR.scala:384:14]
output io_decode_0_write_illegal, // @[CSR.scala:384:14]
output io_decode_0_write_flush, // @[CSR.scala:384:14]
output io_decode_0_system_illegal, // @[CSR.scala:384:14]
output io_decode_0_virtual_access_illegal, // @[CSR.scala:384:14]
output io_decode_0_virtual_system_illegal, // @[CSR.scala:384:14]
input [31:0] io_decode_1_inst, // @[CSR.scala:384:14]
output io_decode_1_fp_illegal, // @[CSR.scala:384:14]
output io_decode_1_fp_csr, // @[CSR.scala:384:14]
output io_decode_1_read_illegal, // @[CSR.scala:384:14]
output io_decode_1_write_illegal, // @[CSR.scala:384:14]
output io_decode_1_write_flush, // @[CSR.scala:384:14]
output io_decode_1_system_illegal, // @[CSR.scala:384:14]
output io_decode_1_virtual_access_illegal, // @[CSR.scala:384:14]
output io_decode_1_virtual_system_illegal, // @[CSR.scala:384:14]
input [31:0] io_decode_2_inst, // @[CSR.scala:384:14]
output io_decode_2_fp_illegal, // @[CSR.scala:384:14]
output io_decode_2_fp_csr, // @[CSR.scala:384:14]
output io_decode_2_read_illegal, // @[CSR.scala:384:14]
output io_decode_2_write_illegal, // @[CSR.scala:384:14]
output io_decode_2_write_flush, // @[CSR.scala:384:14]
output io_decode_2_system_illegal, // @[CSR.scala:384:14]
output io_decode_2_virtual_access_illegal, // @[CSR.scala:384:14]
output io_decode_2_virtual_system_illegal, // @[CSR.scala:384:14]
output io_csr_stall, // @[CSR.scala:384:14]
output io_singleStep, // @[CSR.scala:384:14]
output io_status_debug, // @[CSR.scala:384:14]
output io_status_cease, // @[CSR.scala:384:14]
output io_status_wfi, // @[CSR.scala:384:14]
output [1:0] io_status_dprv, // @[CSR.scala:384:14]
output io_status_dv, // @[CSR.scala:384:14]
output [1:0] io_status_prv, // @[CSR.scala:384:14]
output io_status_v, // @[CSR.scala:384:14]
output io_status_sd, // @[CSR.scala:384:14]
output io_status_mpv, // @[CSR.scala:384:14]
output io_status_gva, // @[CSR.scala:384:14]
output io_status_tsr, // @[CSR.scala:384:14]
output io_status_tw, // @[CSR.scala:384:14]
output io_status_tvm, // @[CSR.scala:384:14]
output io_status_mxr, // @[CSR.scala:384:14]
output io_status_sum, // @[CSR.scala:384:14]
output io_status_mprv, // @[CSR.scala:384:14]
output [1:0] io_status_fs, // @[CSR.scala:384:14]
output [1:0] io_status_mpp, // @[CSR.scala:384:14]
output io_status_spp, // @[CSR.scala:384:14]
output io_status_mpie, // @[CSR.scala:384:14]
output io_status_spie, // @[CSR.scala:384:14]
output io_status_mie, // @[CSR.scala:384:14]
output io_status_sie, // @[CSR.scala:384:14]
output [3:0] io_ptbr_mode, // @[CSR.scala:384:14]
output [43:0] io_ptbr_ppn, // @[CSR.scala:384:14]
output [39:0] io_evec, // @[CSR.scala:384:14]
input io_exception, // @[CSR.scala:384:14]
input [1:0] io_retire, // @[CSR.scala:384:14]
input [63:0] io_cause, // @[CSR.scala:384:14]
input [39:0] io_pc, // @[CSR.scala:384:14]
input [39:0] io_tval, // @[CSR.scala:384:14]
output [63:0] io_time, // @[CSR.scala:384:14]
output [2:0] io_fcsr_rm, // @[CSR.scala:384:14]
input io_fcsr_flags_valid, // @[CSR.scala:384:14]
input [4:0] io_fcsr_flags_bits, // @[CSR.scala:384:14]
input io_set_fs_dirty, // @[CSR.scala:384:14]
output io_interrupt, // @[CSR.scala:384:14]
output [63:0] io_interrupt_cause, // @[CSR.scala:384:14]
output io_pmp_0_cfg_l, // @[CSR.scala:384:14]
output [1:0] io_pmp_0_cfg_a, // @[CSR.scala:384:14]
output io_pmp_0_cfg_x, // @[CSR.scala:384:14]
output io_pmp_0_cfg_w, // @[CSR.scala:384:14]
output io_pmp_0_cfg_r, // @[CSR.scala:384:14]
output [29:0] io_pmp_0_addr, // @[CSR.scala:384:14]
output [31:0] io_pmp_0_mask, // @[CSR.scala:384:14]
output io_pmp_1_cfg_l, // @[CSR.scala:384:14]
output [1:0] io_pmp_1_cfg_a, // @[CSR.scala:384:14]
output io_pmp_1_cfg_x, // @[CSR.scala:384:14]
output io_pmp_1_cfg_w, // @[CSR.scala:384:14]
output io_pmp_1_cfg_r, // @[CSR.scala:384:14]
output [29:0] io_pmp_1_addr, // @[CSR.scala:384:14]
output [31:0] io_pmp_1_mask, // @[CSR.scala:384:14]
output io_pmp_2_cfg_l, // @[CSR.scala:384:14]
output [1:0] io_pmp_2_cfg_a, // @[CSR.scala:384:14]
output io_pmp_2_cfg_x, // @[CSR.scala:384:14]
output io_pmp_2_cfg_w, // @[CSR.scala:384:14]
output io_pmp_2_cfg_r, // @[CSR.scala:384:14]
output [29:0] io_pmp_2_addr, // @[CSR.scala:384:14]
output [31:0] io_pmp_2_mask, // @[CSR.scala:384:14]
output io_pmp_3_cfg_l, // @[CSR.scala:384:14]
output [1:0] io_pmp_3_cfg_a, // @[CSR.scala:384:14]
output io_pmp_3_cfg_x, // @[CSR.scala:384:14]
output io_pmp_3_cfg_w, // @[CSR.scala:384:14]
output io_pmp_3_cfg_r, // @[CSR.scala:384:14]
output [29:0] io_pmp_3_addr, // @[CSR.scala:384:14]
output [31:0] io_pmp_3_mask, // @[CSR.scala:384:14]
output io_pmp_4_cfg_l, // @[CSR.scala:384:14]
output [1:0] io_pmp_4_cfg_a, // @[CSR.scala:384:14]
output io_pmp_4_cfg_x, // @[CSR.scala:384:14]
output io_pmp_4_cfg_w, // @[CSR.scala:384:14]
output io_pmp_4_cfg_r, // @[CSR.scala:384:14]
output [29:0] io_pmp_4_addr, // @[CSR.scala:384:14]
output [31:0] io_pmp_4_mask, // @[CSR.scala:384:14]
output io_pmp_5_cfg_l, // @[CSR.scala:384:14]
output [1:0] io_pmp_5_cfg_a, // @[CSR.scala:384:14]
output io_pmp_5_cfg_x, // @[CSR.scala:384:14]
output io_pmp_5_cfg_w, // @[CSR.scala:384:14]
output io_pmp_5_cfg_r, // @[CSR.scala:384:14]
output [29:0] io_pmp_5_addr, // @[CSR.scala:384:14]
output [31:0] io_pmp_5_mask, // @[CSR.scala:384:14]
output io_pmp_6_cfg_l, // @[CSR.scala:384:14]
output [1:0] io_pmp_6_cfg_a, // @[CSR.scala:384:14]
output io_pmp_6_cfg_x, // @[CSR.scala:384:14]
output io_pmp_6_cfg_w, // @[CSR.scala:384:14]
output io_pmp_6_cfg_r, // @[CSR.scala:384:14]
output [29:0] io_pmp_6_addr, // @[CSR.scala:384:14]
output [31:0] io_pmp_6_mask, // @[CSR.scala:384:14]
output io_pmp_7_cfg_l, // @[CSR.scala:384:14]
output [1:0] io_pmp_7_cfg_a, // @[CSR.scala:384:14]
output io_pmp_7_cfg_x, // @[CSR.scala:384:14]
output io_pmp_7_cfg_w, // @[CSR.scala:384:14]
output io_pmp_7_cfg_r, // @[CSR.scala:384:14]
output [29:0] io_pmp_7_addr, // @[CSR.scala:384:14]
output [31:0] io_pmp_7_mask, // @[CSR.scala:384:14]
output [63:0] io_counters_0_eventSel, // @[CSR.scala:384:14]
input [1:0] io_counters_0_inc, // @[CSR.scala:384:14]
output [63:0] io_counters_1_eventSel, // @[CSR.scala:384:14]
input [1:0] io_counters_1_inc, // @[CSR.scala:384:14]
output io_customCSRs_0_ren, // @[CSR.scala:384:14]
output io_customCSRs_0_wen, // @[CSR.scala:384:14]
output [63:0] io_customCSRs_0_wdata, // @[CSR.scala:384:14]
output [63:0] io_customCSRs_0_value, // @[CSR.scala:384:14]
output io_customCSRs_1_ren, // @[CSR.scala:384:14]
output io_customCSRs_1_wen, // @[CSR.scala:384:14]
output [63:0] io_customCSRs_1_wdata, // @[CSR.scala:384:14]
output [63:0] io_customCSRs_1_value, // @[CSR.scala:384:14]
output io_customCSRs_2_ren, // @[CSR.scala:384:14]
output io_customCSRs_2_wen, // @[CSR.scala:384:14]
output [63:0] io_customCSRs_2_wdata, // @[CSR.scala:384:14]
output [63:0] io_customCSRs_2_value, // @[CSR.scala:384:14]
output io_customCSRs_3_ren, // @[CSR.scala:384:14]
output io_customCSRs_3_wen, // @[CSR.scala:384:14]
output [63:0] io_customCSRs_3_wdata, // @[CSR.scala:384:14]
output [63:0] io_customCSRs_3_value // @[CSR.scala:384:14]
);
wire io_status_sie_0; // @[CSR.scala:377:7]
wire io_status_spie_0; // @[CSR.scala:377:7]
wire io_status_spp_0; // @[CSR.scala:377:7]
wire [1:0] io_status_fs_0; // @[CSR.scala:377:7]
wire io_status_sum_0; // @[CSR.scala:377:7]
wire io_status_mxr_0; // @[CSR.scala:377:7]
wire io_status_sd_0; // @[CSR.scala:377:7]
wire io_ungated_clock_0 = io_ungated_clock; // @[CSR.scala:377:7]
wire io_interrupts_debug_0 = io_interrupts_debug; // @[CSR.scala:377:7]
wire io_interrupts_mtip_0 = io_interrupts_mtip; // @[CSR.scala:377:7]
wire io_interrupts_msip_0 = io_interrupts_msip; // @[CSR.scala:377:7]
wire io_interrupts_meip_0 = io_interrupts_meip; // @[CSR.scala:377:7]
wire io_interrupts_seip_0 = io_interrupts_seip; // @[CSR.scala:377:7]
wire io_hartid_0 = io_hartid; // @[CSR.scala:377:7]
wire [11:0] io_rw_addr_0 = io_rw_addr; // @[CSR.scala:377:7]
wire [2:0] io_rw_cmd_0 = io_rw_cmd; // @[CSR.scala:377:7]
wire [63:0] io_rw_wdata_0 = io_rw_wdata; // @[CSR.scala:377:7]
wire [31:0] io_decode_0_inst_0 = io_decode_0_inst; // @[CSR.scala:377:7]
wire [31:0] io_decode_1_inst_0 = io_decode_1_inst; // @[CSR.scala:377:7]
wire [31:0] io_decode_2_inst_0 = io_decode_2_inst; // @[CSR.scala:377:7]
wire io_exception_0 = io_exception; // @[CSR.scala:377:7]
wire [1:0] io_retire_0 = io_retire; // @[CSR.scala:377:7]
wire [63:0] io_cause_0 = io_cause; // @[CSR.scala:377:7]
wire [39:0] io_pc_0 = io_pc; // @[CSR.scala:377:7]
wire [39:0] io_tval_0 = io_tval; // @[CSR.scala:377:7]
wire io_fcsr_flags_valid_0 = io_fcsr_flags_valid; // @[CSR.scala:377:7]
wire [4:0] io_fcsr_flags_bits_0 = io_fcsr_flags_bits; // @[CSR.scala:377:7]
wire io_set_fs_dirty_0 = io_set_fs_dirty; // @[CSR.scala:377:7]
wire [1:0] io_counters_0_inc_0 = io_counters_0_inc; // @[CSR.scala:377:7]
wire [1:0] io_counters_1_inc_0 = io_counters_1_inc; // @[CSR.scala:377:7]
wire io_decode_0_vector_illegal = 1'h1; // @[CSR.scala:377:7]
wire io_decode_0_rocc_illegal = 1'h1; // @[CSR.scala:377:7]
wire io_decode_1_vector_illegal = 1'h1; // @[CSR.scala:377:7]
wire io_decode_1_rocc_illegal = 1'h1; // @[CSR.scala:377:7]
wire io_decode_2_vector_illegal = 1'h1; // @[CSR.scala:377:7]
wire io_decode_2_rocc_illegal = 1'h1; // @[CSR.scala:377:7]
wire io_gstatus_sd = 1'h1; // @[CSR.scala:377:7]
wire sup_meip = 1'h1; // @[CSR.scala:406:19]
wire sup_seip = 1'h1; // @[CSR.scala:406:19]
wire sup_mtip = 1'h1; // @[CSR.scala:406:19]
wire sup_stip = 1'h1; // @[CSR.scala:406:19]
wire sup_msip = 1'h1; // @[CSR.scala:406:19]
wire sup_ssip = 1'h1; // @[CSR.scala:406:19]
wire del_seip = 1'h1; // @[CSR.scala:426:26]
wire del_stip = 1'h1; // @[CSR.scala:426:26]
wire del_ssip = 1'h1; // @[CSR.scala:426:26]
wire _read_mapping_T_3 = 1'h1; // @[CSR.scala:1665:45]
wire _debug_csrs_T_1 = 1'h1; // @[CSR.scala:1665:45]
wire read_mnstatus_mie = 1'h1; // @[CSR.scala:675:31]
wire sie_mask_sgeip_mask_sgeip = 1'h1; // @[CSR.scala:748:30]
wire _allow_wfi_T_4 = 1'h1; // @[CSR.scala:906:112]
wire _allow_wfi_T_5 = 1'h1; // @[CSR.scala:906:109]
wire allow_hfence_vvma = 1'h1; // @[CSR.scala:908:50]
wire allow_hlsv = 1'h1; // @[CSR.scala:909:43]
wire _allow_counter_T_11 = 1'h1; // @[CSR.scala:914:8]
wire _allow_counter_T_13 = 1'h1; // @[CSR.scala:914:27]
wire _allow_counter_T_16 = 1'h1; // @[CSR.scala:914:45]
wire _io_decode_0_fp_illegal_T_4 = 1'h1; // @[CSR.scala:915:103]
wire _io_decode_0_vector_illegal_T = 1'h1; // @[CSR.scala:916:43]
wire _io_decode_0_vector_illegal_T_1 = 1'h1; // @[CSR.scala:916:87]
wire _io_decode_0_vector_illegal_T_3 = 1'h1; // @[CSR.scala:916:51]
wire _io_decode_0_vector_illegal_T_5 = 1'h1; // @[CSR.scala:916:98]
wire _io_decode_0_vector_illegal_T_6 = 1'h1; // @[CSR.scala:916:95]
wire _io_decode_0_rocc_illegal_T = 1'h1; // @[CSR.scala:919:41]
wire _io_decode_0_rocc_illegal_T_1 = 1'h1; // @[CSR.scala:919:85]
wire _io_decode_0_rocc_illegal_T_3 = 1'h1; // @[CSR.scala:919:49]
wire _io_decode_0_rocc_illegal_T_5 = 1'h1; // @[CSR.scala:919:96]
wire _io_decode_0_rocc_illegal_T_6 = 1'h1; // @[CSR.scala:919:93]
wire _allow_wfi_T_11 = 1'h1; // @[CSR.scala:906:112]
wire _allow_wfi_T_12 = 1'h1; // @[CSR.scala:906:109]
wire allow_hfence_vvma_1 = 1'h1; // @[CSR.scala:908:50]
wire allow_hlsv_1 = 1'h1; // @[CSR.scala:909:43]
wire _allow_counter_T_28 = 1'h1; // @[CSR.scala:914:8]
wire _allow_counter_T_30 = 1'h1; // @[CSR.scala:914:27]
wire _allow_counter_T_33 = 1'h1; // @[CSR.scala:914:45]
wire _io_decode_1_fp_illegal_T_4 = 1'h1; // @[CSR.scala:915:103]
wire _io_decode_1_vector_illegal_T = 1'h1; // @[CSR.scala:916:43]
wire _io_decode_1_vector_illegal_T_1 = 1'h1; // @[CSR.scala:916:87]
wire _io_decode_1_vector_illegal_T_3 = 1'h1; // @[CSR.scala:916:51]
wire _io_decode_1_vector_illegal_T_5 = 1'h1; // @[CSR.scala:916:98]
wire _io_decode_1_vector_illegal_T_6 = 1'h1; // @[CSR.scala:916:95]
wire _io_decode_1_rocc_illegal_T = 1'h1; // @[CSR.scala:919:41]
wire _io_decode_1_rocc_illegal_T_1 = 1'h1; // @[CSR.scala:919:85]
wire _io_decode_1_rocc_illegal_T_3 = 1'h1; // @[CSR.scala:919:49]
wire _io_decode_1_rocc_illegal_T_5 = 1'h1; // @[CSR.scala:919:96]
wire _io_decode_1_rocc_illegal_T_6 = 1'h1; // @[CSR.scala:919:93]
wire _allow_wfi_T_18 = 1'h1; // @[CSR.scala:906:112]
wire _allow_wfi_T_19 = 1'h1; // @[CSR.scala:906:109]
wire allow_hfence_vvma_2 = 1'h1; // @[CSR.scala:908:50]
wire allow_hlsv_2 = 1'h1; // @[CSR.scala:909:43]
wire _allow_counter_T_45 = 1'h1; // @[CSR.scala:914:8]
wire _allow_counter_T_47 = 1'h1; // @[CSR.scala:914:27]
wire _allow_counter_T_50 = 1'h1; // @[CSR.scala:914:45]
wire _io_decode_2_fp_illegal_T_4 = 1'h1; // @[CSR.scala:915:103]
wire _io_decode_2_vector_illegal_T = 1'h1; // @[CSR.scala:916:43]
wire _io_decode_2_vector_illegal_T_1 = 1'h1; // @[CSR.scala:916:87]
wire _io_decode_2_vector_illegal_T_3 = 1'h1; // @[CSR.scala:916:51]
wire _io_decode_2_vector_illegal_T_5 = 1'h1; // @[CSR.scala:916:98]
wire _io_decode_2_vector_illegal_T_6 = 1'h1; // @[CSR.scala:916:95]
wire _io_decode_2_rocc_illegal_T = 1'h1; // @[CSR.scala:919:41]
wire _io_decode_2_rocc_illegal_T_1 = 1'h1; // @[CSR.scala:919:85]
wire _io_decode_2_rocc_illegal_T_3 = 1'h1; // @[CSR.scala:919:49]
wire _io_decode_2_rocc_illegal_T_5 = 1'h1; // @[CSR.scala:919:96]
wire _io_decode_2_rocc_illegal_T_6 = 1'h1; // @[CSR.scala:919:93]
wire _io_gstatus_sd_T = 1'h1; // @[CSR.scala:1016:34]
wire _io_gstatus_sd_T_2 = 1'h1; // @[CSR.scala:1016:39]
wire _io_gstatus_sd_T_4 = 1'h1; // @[CSR.scala:1016:61]
wire _en_T_7 = 1'h1; // @[CSR.scala:1096:71]
wire delegable_1 = 1'h1; // @[CSR.scala:1097:65]
wire _en_T_19 = 1'h1; // @[CSR.scala:1096:71]
wire _en_T_31 = 1'h1; // @[CSR.scala:1096:71]
wire delegable_5 = 1'h1; // @[CSR.scala:1097:65]
wire _en_T_43 = 1'h1; // @[CSR.scala:1096:71]
wire _en_T_55 = 1'h1; // @[CSR.scala:1096:71]
wire delegable_9 = 1'h1; // @[CSR.scala:1097:65]
wire _en_T_67 = 1'h1; // @[CSR.scala:1096:71]
wire delegable_17 = 1'h1; // @[CSR.scala:1109:67]
wire delegable_18 = 1'h1; // @[CSR.scala:1109:67]
wire delegable_19 = 1'h1; // @[CSR.scala:1109:67]
wire delegable_21 = 1'h1; // @[CSR.scala:1109:67]
wire delegable_23 = 1'h1; // @[CSR.scala:1109:67]
wire delegable_26 = 1'h1; // @[CSR.scala:1109:67]
wire delegable_27 = 1'h1; // @[CSR.scala:1109:67]
wire delegable_28 = 1'h1; // @[CSR.scala:1109:67]
wire _io_evec_T_1 = 1'h1; // @[CSR.scala:1665:45]
wire _io_evec_T_6 = 1'h1; // @[CSR.scala:1665:45]
wire _io_evec_T_11 = 1'h1; // @[CSR.scala:1665:45]
wire _io_evec_T_16 = 1'h1; // @[CSR.scala:1665:45]
wire _io_evec_T_21 = 1'h1; // @[CSR.scala:1665:45]
wire _csr_wen_T_5 = 1'h1; // @[CSR.scala:1222:59]
wire _io_trace_0_exception_T = 1'h1; // @[CSR.scala:1620:30]
wire [31:0] io_status_isa = 32'h14112D; // @[CSR.scala:377:7]
wire [22:0] io_status_zero2 = 23'h0; // @[CSR.scala:377:7]
wire [22:0] io_gstatus_zero2 = 23'h0; // @[CSR.scala:377:7]
wire [22:0] _reset_mstatus_WIRE_zero2 = 23'h0; // @[CSR.scala:391:47]
wire [22:0] reset_mstatus_zero2 = 23'h0; // @[CSR.scala:391:34]
wire [22:0] _read_sstatus_WIRE_zero2 = 23'h0; // @[CSR.scala:755:48]
wire [22:0] read_sstatus_zero2 = 23'h0; // @[CSR.scala:755:35]
wire io_decode_0_vector_csr = 1'h0; // @[CSR.scala:377:7]
wire io_decode_1_vector_csr = 1'h0; // @[CSR.scala:377:7]
wire io_decode_2_vector_csr = 1'h0; // @[CSR.scala:377:7]
wire io_rw_stall = 1'h0; // @[CSR.scala:377:7]
wire io_status_mbe = 1'h0; // @[CSR.scala:377:7]
wire io_status_sbe = 1'h0; // @[CSR.scala:377:7]
wire io_status_sd_rv32 = 1'h0; // @[CSR.scala:377:7]
wire io_status_ube = 1'h0; // @[CSR.scala:377:7]
wire io_status_upie = 1'h0; // @[CSR.scala:377:7]
wire io_status_hie = 1'h0; // @[CSR.scala:377:7]
wire io_status_uie = 1'h0; // @[CSR.scala:377:7]
wire io_hstatus_vtsr = 1'h0; // @[CSR.scala:377:7]
wire io_hstatus_vtw = 1'h0; // @[CSR.scala:377:7]
wire io_hstatus_vtvm = 1'h0; // @[CSR.scala:377:7]
wire io_hstatus_hu = 1'h0; // @[CSR.scala:377:7]
wire io_hstatus_vsbe = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_debug = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_cease = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_wfi = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_dv = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_v = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_mpv = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_gva = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_mbe = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_sbe = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_sd_rv32 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_tsr = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_tw = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_tvm = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_mxr = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_sum = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_mprv = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_mpie = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_ube = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_upie = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_mie = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_hie = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_uie = 1'h0; // @[CSR.scala:377:7]
wire io_mhtinst_read_pseudo = 1'h0; // @[CSR.scala:377:7]
wire io_gva = 1'h0; // @[CSR.scala:377:7]
wire io_rocc_interrupt = 1'h0; // @[CSR.scala:377:7]
wire io_customCSRs_0_stall = 1'h0; // @[CSR.scala:377:7]
wire io_customCSRs_0_set = 1'h0; // @[CSR.scala:377:7]
wire io_customCSRs_1_stall = 1'h0; // @[CSR.scala:377:7]
wire io_customCSRs_1_set = 1'h0; // @[CSR.scala:377:7]
wire io_customCSRs_2_stall = 1'h0; // @[CSR.scala:377:7]
wire io_customCSRs_2_set = 1'h0; // @[CSR.scala:377:7]
wire io_customCSRs_3_stall = 1'h0; // @[CSR.scala:377:7]
wire io_customCSRs_3_set = 1'h0; // @[CSR.scala:377:7]
wire _reset_mstatus_WIRE_debug = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_cease = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_wfi = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_dv = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_v = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_sd = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_mpv = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_gva = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_mbe = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_sbe = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_sd_rv32 = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_tsr = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_tw = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_tvm = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_mxr = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_sum = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_mprv = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_spp = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_mpie = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_ube = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_spie = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_upie = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_mie = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_hie = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_sie = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_uie = 1'h0; // @[CSR.scala:391:47]
wire reset_mstatus_debug = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_cease = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_wfi = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_dv = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_v = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_sd = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_mpv = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_gva = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_mbe = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_sbe = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_sd_rv32 = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_tsr = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_tw = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_tvm = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_mxr = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_sum = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_mprv = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_spp = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_mpie = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_ube = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_spie = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_upie = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_mie = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_hie = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_sie = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_uie = 1'h0; // @[CSR.scala:391:34]
wire _reset_dcsr_WIRE_ebreakm = 1'h0; // @[CSR.scala:400:44]
wire _reset_dcsr_WIRE_ebreakh = 1'h0; // @[CSR.scala:400:44]
wire _reset_dcsr_WIRE_ebreaks = 1'h0; // @[CSR.scala:400:44]
wire _reset_dcsr_WIRE_ebreaku = 1'h0; // @[CSR.scala:400:44]
wire _reset_dcsr_WIRE_zero2 = 1'h0; // @[CSR.scala:400:44]
wire _reset_dcsr_WIRE_stopcycle = 1'h0; // @[CSR.scala:400:44]
wire _reset_dcsr_WIRE_stoptime = 1'h0; // @[CSR.scala:400:44]
wire _reset_dcsr_WIRE_v = 1'h0; // @[CSR.scala:400:44]
wire _reset_dcsr_WIRE_step = 1'h0; // @[CSR.scala:400:44]
wire reset_dcsr_ebreakm = 1'h0; // @[CSR.scala:400:31]
wire reset_dcsr_ebreakh = 1'h0; // @[CSR.scala:400:31]
wire reset_dcsr_ebreaks = 1'h0; // @[CSR.scala:400:31]
wire reset_dcsr_ebreaku = 1'h0; // @[CSR.scala:400:31]
wire reset_dcsr_zero2 = 1'h0; // @[CSR.scala:400:31]
wire reset_dcsr_stopcycle = 1'h0; // @[CSR.scala:400:31]
wire reset_dcsr_stoptime = 1'h0; // @[CSR.scala:400:31]
wire reset_dcsr_v = 1'h0; // @[CSR.scala:400:31]
wire reset_dcsr_step = 1'h0; // @[CSR.scala:400:31]
wire sup_zero1 = 1'h0; // @[CSR.scala:406:19]
wire sup_debug = 1'h0; // @[CSR.scala:406:19]
wire sup_rocc = 1'h0; // @[CSR.scala:406:19]
wire sup_sgeip = 1'h0; // @[CSR.scala:406:19]
wire sup_vseip = 1'h0; // @[CSR.scala:406:19]
wire sup_ueip = 1'h0; // @[CSR.scala:406:19]
wire sup_vstip = 1'h0; // @[CSR.scala:406:19]
wire sup_utip = 1'h0; // @[CSR.scala:406:19]
wire sup_vssip = 1'h0; // @[CSR.scala:406:19]
wire sup_usip = 1'h0; // @[CSR.scala:406:19]
wire del_zero1 = 1'h0; // @[CSR.scala:426:26]
wire del_debug = 1'h0; // @[CSR.scala:426:26]
wire del_rocc = 1'h0; // @[CSR.scala:426:26]
wire del_sgeip = 1'h0; // @[CSR.scala:426:26]
wire del_meip = 1'h0; // @[CSR.scala:426:26]
wire del_vseip = 1'h0; // @[CSR.scala:426:26]
wire del_ueip = 1'h0; // @[CSR.scala:426:26]
wire del_mtip = 1'h0; // @[CSR.scala:426:26]
wire del_vstip = 1'h0; // @[CSR.scala:426:26]
wire del_utip = 1'h0; // @[CSR.scala:426:26]
wire del_msip = 1'h0; // @[CSR.scala:426:26]
wire del_vssip = 1'h0; // @[CSR.scala:426:26]
wire del_usip = 1'h0; // @[CSR.scala:426:26]
wire hi_hi_hi_hi = 1'h0; // @[CSR.scala:431:10]
wire hi_hi_hi_hi_1 = 1'h0; // @[CSR.scala:431:50]
wire _always_WIRE_zero1 = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_debug = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_rocc = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_sgeip = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_meip = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_vseip = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_seip = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_ueip = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_mtip = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_vstip = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_stip = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_utip = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_msip = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_vssip = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_ssip = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_usip = 1'h0; // @[CSR.scala:471:42]
wire always_zero1 = 1'h0; // @[CSR.scala:471:29]
wire always_debug = 1'h0; // @[CSR.scala:471:29]
wire always_rocc = 1'h0; // @[CSR.scala:471:29]
wire always_sgeip = 1'h0; // @[CSR.scala:471:29]
wire always_meip = 1'h0; // @[CSR.scala:471:29]
wire always_vseip = 1'h0; // @[CSR.scala:471:29]
wire always_seip = 1'h0; // @[CSR.scala:471:29]
wire always_ueip = 1'h0; // @[CSR.scala:471:29]
wire always_mtip = 1'h0; // @[CSR.scala:471:29]
wire always_vstip = 1'h0; // @[CSR.scala:471:29]
wire always_stip = 1'h0; // @[CSR.scala:471:29]
wire always_utip = 1'h0; // @[CSR.scala:471:29]
wire always_msip = 1'h0; // @[CSR.scala:471:29]
wire always_vssip = 1'h0; // @[CSR.scala:471:29]
wire always_ssip = 1'h0; // @[CSR.scala:471:29]
wire always_usip = 1'h0; // @[CSR.scala:471:29]
wire deleg_zero1 = 1'h0; // @[CSR.scala:476:28]
wire deleg_debug = 1'h0; // @[CSR.scala:476:28]
wire deleg_rocc = 1'h0; // @[CSR.scala:476:28]
wire deleg_sgeip = 1'h0; // @[CSR.scala:476:28]
wire deleg_meip = 1'h0; // @[CSR.scala:476:28]
wire deleg_vseip = 1'h0; // @[CSR.scala:476:28]
wire deleg_seip = 1'h0; // @[CSR.scala:476:28]
wire deleg_ueip = 1'h0; // @[CSR.scala:476:28]
wire deleg_mtip = 1'h0; // @[CSR.scala:476:28]
wire deleg_vstip = 1'h0; // @[CSR.scala:476:28]
wire deleg_stip = 1'h0; // @[CSR.scala:476:28]
wire deleg_utip = 1'h0; // @[CSR.scala:476:28]
wire deleg_msip = 1'h0; // @[CSR.scala:476:28]
wire deleg_vssip = 1'h0; // @[CSR.scala:476:28]
wire deleg_ssip = 1'h0; // @[CSR.scala:476:28]
wire deleg_usip = 1'h0; // @[CSR.scala:476:28]
wire hi_hi_hi_hi_2 = 1'h0; // @[CSR.scala:479:12]
wire hi_hi_hi_hi_3 = 1'h0; // @[CSR.scala:479:27]
wire _reset_mnstatus_WIRE_mpv = 1'h0; // @[CSR.scala:516:48]
wire _reset_mnstatus_WIRE_mie = 1'h0; // @[CSR.scala:516:48]
wire reset_mnstatus_mpv = 1'h0; // @[CSR.scala:516:35]
wire reset_mnstatus_mie = 1'h0; // @[CSR.scala:516:35]
wire _reg_menvcfg_WIRE_stce = 1'h0; // @[CSR.scala:525:41]
wire _reg_menvcfg_WIRE_pbmte = 1'h0; // @[CSR.scala:525:41]
wire _reg_menvcfg_WIRE_cbze = 1'h0; // @[CSR.scala:525:41]
wire _reg_menvcfg_WIRE_cbcfe = 1'h0; // @[CSR.scala:525:41]
wire _reg_menvcfg_WIRE_fiom = 1'h0; // @[CSR.scala:525:41]
wire _reg_senvcfg_WIRE_stce = 1'h0; // @[CSR.scala:526:41]
wire _reg_senvcfg_WIRE_pbmte = 1'h0; // @[CSR.scala:526:41]
wire _reg_senvcfg_WIRE_cbze = 1'h0; // @[CSR.scala:526:41]
wire _reg_senvcfg_WIRE_cbcfe = 1'h0; // @[CSR.scala:526:41]
wire _reg_senvcfg_WIRE_fiom = 1'h0; // @[CSR.scala:526:41]
wire _reg_henvcfg_WIRE_stce = 1'h0; // @[CSR.scala:527:41]
wire _reg_henvcfg_WIRE_pbmte = 1'h0; // @[CSR.scala:527:41]
wire _reg_henvcfg_WIRE_cbze = 1'h0; // @[CSR.scala:527:41]
wire _reg_henvcfg_WIRE_cbcfe = 1'h0; // @[CSR.scala:527:41]
wire _reg_henvcfg_WIRE_fiom = 1'h0; // @[CSR.scala:527:41]
wire _reg_hstatus_WIRE_vtsr = 1'h0; // @[CSR.scala:552:41]
wire _reg_hstatus_WIRE_vtw = 1'h0; // @[CSR.scala:552:41]
wire _reg_hstatus_WIRE_vtvm = 1'h0; // @[CSR.scala:552:41]
wire _reg_hstatus_WIRE_hu = 1'h0; // @[CSR.scala:552:41]
wire _reg_hstatus_WIRE_spvp = 1'h0; // @[CSR.scala:552:41]
wire _reg_hstatus_WIRE_spv = 1'h0; // @[CSR.scala:552:41]
wire _reg_hstatus_WIRE_gva = 1'h0; // @[CSR.scala:552:41]
wire _reg_hstatus_WIRE_vsbe = 1'h0; // @[CSR.scala:552:41]
wire read_hvip_hi_hi_hi_hi = 1'h0; // @[CSR.scala:555:27]
wire mip_zero1 = 1'h0; // @[CSR.scala:600:24]
wire mip_debug = 1'h0; // @[CSR.scala:600:24]
wire mip_rocc = 1'h0; // @[CSR.scala:600:24]
wire mip_sgeip = 1'h0; // @[CSR.scala:600:24]
wire mip_vseip = 1'h0; // @[CSR.scala:600:24]
wire mip_ueip = 1'h0; // @[CSR.scala:600:24]
wire mip_vstip = 1'h0; // @[CSR.scala:600:24]
wire mip_utip = 1'h0; // @[CSR.scala:600:24]
wire mip_vssip = 1'h0; // @[CSR.scala:600:24]
wire mip_usip = 1'h0; // @[CSR.scala:600:24]
wire _any_T_47 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_48 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_49 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_50 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_51 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_52 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_53 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_54 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_55 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_56 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_57 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_58 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_59 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_60 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_61 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_62 = 1'h0; // @[CSR.scala:1637:76]
wire _which_T_47 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_48 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_49 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_50 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_51 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_52 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_53 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_54 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_55 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_56 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_57 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_58 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_59 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_60 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_61 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_62 = 1'h0; // @[CSR.scala:1638:91]
wire _io_fiom_T_5 = 1'h0; // @[CSR.scala:631:131]
wire _pmp_mask_base_T_2 = 1'h0; // @[PMP.scala:57:62]
wire _pmp_mask_base_T_5 = 1'h0; // @[PMP.scala:57:62]
wire _pmp_mask_base_T_8 = 1'h0; // @[PMP.scala:57:62]
wire _pmp_mask_base_T_11 = 1'h0; // @[PMP.scala:57:62]
wire _pmp_mask_base_T_14 = 1'h0; // @[PMP.scala:57:62]
wire _pmp_mask_base_T_17 = 1'h0; // @[PMP.scala:57:62]
wire _pmp_mask_base_T_20 = 1'h0; // @[PMP.scala:57:62]
wire _pmp_mask_base_T_23 = 1'h0; // @[PMP.scala:57:62]
wire _read_mapping_T = 1'h0; // @[package.scala:132:38]
wire read_mapping_lo_hi_1 = 1'h0; // @[CSR.scala:657:47]
wire read_mapping_hi_hi_1 = 1'h0; // @[CSR.scala:657:47]
wire _read_mnstatus_WIRE_mpv = 1'h0; // @[CSR.scala:675:44]
wire _read_mnstatus_WIRE_mie = 1'h0; // @[CSR.scala:675:44]
wire read_mnstatus_mpv = 1'h0; // @[CSR.scala:675:31]
wire _sie_mask_sgeip_mask_WIRE_zero1 = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_debug = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_rocc = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_sgeip = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_meip = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_vseip = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_seip = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_ueip = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_mtip = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_vstip = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_stip = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_utip = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_msip = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_vssip = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_ssip = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_usip = 1'h0; // @[CSR.scala:748:43]
wire sie_mask_sgeip_mask_zero1 = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_sgeip_mask_debug = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_sgeip_mask_rocc = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_sgeip_mask_meip = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_sgeip_mask_vseip = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_sgeip_mask_seip = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_sgeip_mask_ueip = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_sgeip_mask_mtip = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_sgeip_mask_vstip = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_sgeip_mask_stip = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_sgeip_mask_utip = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_sgeip_mask_msip = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_sgeip_mask_vssip = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_sgeip_mask_ssip = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_sgeip_mask_usip = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_hi_hi_hi_hi = 1'h0; // @[CSR.scala:750:59]
wire _read_sstatus_WIRE_debug = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_cease = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_wfi = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_dv = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_v = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_sd = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_mpv = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_gva = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_mbe = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_sbe = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_sd_rv32 = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_tsr = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_tw = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_tvm = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_mxr = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_sum = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_mprv = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_spp = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_mpie = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_ube = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_spie = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_upie = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_mie = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_hie = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_sie = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_uie = 1'h0; // @[CSR.scala:755:48]
wire read_sstatus_debug = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_cease = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_wfi = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_dv = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_v = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_mpv = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_gva = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_mbe = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_sbe = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_sd_rv32 = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_tsr = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_tw = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_tvm = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_mprv = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_mpie = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_ube = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_upie = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_mie = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_hie = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_uie = 1'h0; // @[CSR.scala:755:35]
wire read_pmp_15_cfg_l = 1'h0; // @[CSR.scala:787:59]
wire read_pmp_15_cfg_x = 1'h0; // @[CSR.scala:787:59]
wire read_pmp_15_cfg_w = 1'h0; // @[CSR.scala:787:59]
wire read_pmp_15_cfg_r = 1'h0; // @[CSR.scala:787:59]
wire _reg_custom_T = 1'h0; // @[CSR.scala:801:16]
wire _reg_custom_T_1 = 1'h0; // @[CSR.scala:801:16]
wire _reg_custom_T_2 = 1'h0; // @[CSR.scala:801:16]
wire _reg_custom_T_3 = 1'h0; // @[CSR.scala:801:16]
wire _allow_counter_T_4 = 1'h0; // @[CSR.scala:913:8]
wire _io_decode_0_fp_illegal_T_1 = 1'h0; // @[CSR.scala:915:83]
wire _io_decode_0_fp_illegal_T_2 = 1'h0; // @[CSR.scala:915:64]
wire _io_decode_0_fp_illegal_T_5 = 1'h0; // @[CSR.scala:915:94]
wire _io_decode_0_vector_illegal_T_4 = 1'h0; // @[CSR.scala:916:107]
wire io_decode_0_vector_csr_plaOutput = 1'h0; // @[pla.scala:81:23]
wire _io_decode_0_vector_csr_T = 1'h0; // @[Decode.scala:55:116]
wire _io_decode_0_rocc_illegal_T_4 = 1'h0; // @[CSR.scala:919:105]
wire _csr_addr_legal_T_3 = 1'h0; // @[CSR.scala:921:25]
wire _csr_addr_legal_T_5 = 1'h0; // @[CSR.scala:921:43]
wire _csr_addr_legal_T_8 = 1'h0; // @[CSR.scala:921:74]
wire io_decode_0_read_illegal_plaOutput_1 = 1'h0; // @[pla.scala:81:23]
wire _io_decode_0_read_illegal_T_16 = 1'h0; // @[Decode.scala:55:116]
wire _io_decode_0_read_illegal_T_17 = 1'h0; // @[CSR.scala:928:43]
wire _io_decode_0_system_illegal_T_20 = 1'h0; // @[CSR.scala:940:25]
wire _io_decode_0_system_illegal_T_21 = 1'h0; // @[CSR.scala:940:22]
wire _io_decode_0_system_illegal_T_23 = 1'h0; // @[CSR.scala:941:18]
wire _io_decode_0_system_illegal_T_24 = 1'h0; // @[CSR.scala:941:15]
wire _io_decode_0_virtual_access_illegal_T_27 = 1'h0; // @[CSR.scala:947:50]
wire _io_decode_0_virtual_system_illegal_T_5 = 1'h0; // @[CSR.scala:953:57]
wire _allow_counter_T_21 = 1'h0; // @[CSR.scala:913:8]
wire _io_decode_1_fp_illegal_T_1 = 1'h0; // @[CSR.scala:915:83]
wire _io_decode_1_fp_illegal_T_2 = 1'h0; // @[CSR.scala:915:64]
wire _io_decode_1_fp_illegal_T_5 = 1'h0; // @[CSR.scala:915:94]
wire _io_decode_1_vector_illegal_T_4 = 1'h0; // @[CSR.scala:916:107]
wire io_decode_1_vector_csr_plaOutput = 1'h0; // @[pla.scala:81:23]
wire _io_decode_1_vector_csr_T = 1'h0; // @[Decode.scala:55:116]
wire _io_decode_1_rocc_illegal_T_4 = 1'h0; // @[CSR.scala:919:105]
wire _csr_addr_legal_T_12 = 1'h0; // @[CSR.scala:921:25]
wire _csr_addr_legal_T_14 = 1'h0; // @[CSR.scala:921:43]
wire _csr_addr_legal_T_17 = 1'h0; // @[CSR.scala:921:74]
wire io_decode_1_read_illegal_plaOutput_1 = 1'h0; // @[pla.scala:81:23]
wire _io_decode_1_read_illegal_T_16 = 1'h0; // @[Decode.scala:55:116]
wire _io_decode_1_read_illegal_T_17 = 1'h0; // @[CSR.scala:928:43]
wire _io_decode_1_system_illegal_T_20 = 1'h0; // @[CSR.scala:940:25]
wire _io_decode_1_system_illegal_T_21 = 1'h0; // @[CSR.scala:940:22]
wire _io_decode_1_system_illegal_T_23 = 1'h0; // @[CSR.scala:941:18]
wire _io_decode_1_system_illegal_T_24 = 1'h0; // @[CSR.scala:941:15]
wire _io_decode_1_virtual_access_illegal_T_27 = 1'h0; // @[CSR.scala:947:50]
wire _io_decode_1_virtual_system_illegal_T_5 = 1'h0; // @[CSR.scala:953:57]
wire _allow_counter_T_38 = 1'h0; // @[CSR.scala:913:8]
wire _io_decode_2_fp_illegal_T_1 = 1'h0; // @[CSR.scala:915:83]
wire _io_decode_2_fp_illegal_T_2 = 1'h0; // @[CSR.scala:915:64]
wire _io_decode_2_fp_illegal_T_5 = 1'h0; // @[CSR.scala:915:94]
wire _io_decode_2_vector_illegal_T_4 = 1'h0; // @[CSR.scala:916:107]
wire io_decode_2_vector_csr_plaOutput = 1'h0; // @[pla.scala:81:23]
wire _io_decode_2_vector_csr_T = 1'h0; // @[Decode.scala:55:116]
wire _io_decode_2_rocc_illegal_T_4 = 1'h0; // @[CSR.scala:919:105]
wire _csr_addr_legal_T_21 = 1'h0; // @[CSR.scala:921:25]
wire _csr_addr_legal_T_23 = 1'h0; // @[CSR.scala:921:43]
wire _csr_addr_legal_T_26 = 1'h0; // @[CSR.scala:921:74]
wire io_decode_2_read_illegal_plaOutput_1 = 1'h0; // @[pla.scala:81:23]
wire _io_decode_2_read_illegal_T_16 = 1'h0; // @[Decode.scala:55:116]
wire _io_decode_2_read_illegal_T_17 = 1'h0; // @[CSR.scala:928:43]
wire _io_decode_2_system_illegal_T_20 = 1'h0; // @[CSR.scala:940:25]
wire _io_decode_2_system_illegal_T_21 = 1'h0; // @[CSR.scala:940:22]
wire _io_decode_2_system_illegal_T_23 = 1'h0; // @[CSR.scala:941:18]
wire _io_decode_2_system_illegal_T_24 = 1'h0; // @[CSR.scala:941:15]
wire _io_decode_2_virtual_access_illegal_T_27 = 1'h0; // @[CSR.scala:947:50]
wire _io_decode_2_virtual_system_illegal_T_5 = 1'h0; // @[CSR.scala:953:57]
wire trapToNmiInt = 1'h0; // @[CSR.scala:990:33]
wire _trapToNmiXcpt_T = 1'h0; // @[CSR.scala:991:37]
wire trapToNmiXcpt = 1'h0; // @[CSR.scala:991:34]
wire trapToNmi = 1'h0; // @[CSR.scala:992:32]
wire _nmiTVec_T = 1'h0; // @[CSR.scala:993:21]
wire _nmiTVec_T_1 = 1'h0; // @[CSR.scala:993:58]
wire _io_status_sd_T_1 = 1'h0; // @[CSR.scala:1003:53]
wire _io_status_sd_T_3 = 1'h0; // @[CSR.scala:1003:74]
wire _io_status_sd_rv32_T = 1'h0; // @[CSR.scala:1010:39]
wire _io_gstatus_sd_T_1 = 1'h0; // @[CSR.scala:1016:56]
wire _io_gstatus_sd_rv32_T = 1'h0; // @[CSR.scala:1018:40]
wire _en_T_1 = 1'h0; // @[CSR.scala:1096:71]
wire _en_T_2 = 1'h0; // @[CSR.scala:1096:24]
wire en = 1'h0; // @[CSR.scala:1096:79]
wire delegable = 1'h0; // @[CSR.scala:1097:65]
wire _en_T_13 = 1'h0; // @[CSR.scala:1096:71]
wire _en_T_14 = 1'h0; // @[CSR.scala:1096:24]
wire en_2 = 1'h0; // @[CSR.scala:1096:79]
wire delegable_2 = 1'h0; // @[CSR.scala:1097:65]
wire delegable_3 = 1'h0; // @[CSR.scala:1097:65]
wire _en_T_25 = 1'h0; // @[CSR.scala:1096:71]
wire _en_T_26 = 1'h0; // @[CSR.scala:1096:24]
wire en_4 = 1'h0; // @[CSR.scala:1096:79]
wire delegable_4 = 1'h0; // @[CSR.scala:1097:65]
wire _en_T_37 = 1'h0; // @[CSR.scala:1096:71]
wire _en_T_38 = 1'h0; // @[CSR.scala:1096:24]
wire en_6 = 1'h0; // @[CSR.scala:1096:79]
wire delegable_6 = 1'h0; // @[CSR.scala:1097:65]
wire delegable_7 = 1'h0; // @[CSR.scala:1097:65]
wire _en_T_49 = 1'h0; // @[CSR.scala:1096:71]
wire _en_T_50 = 1'h0; // @[CSR.scala:1096:24]
wire en_8 = 1'h0; // @[CSR.scala:1096:79]
wire delegable_8 = 1'h0; // @[CSR.scala:1097:65]
wire _en_T_61 = 1'h0; // @[CSR.scala:1096:71]
wire _en_T_62 = 1'h0; // @[CSR.scala:1096:24]
wire en_10 = 1'h0; // @[CSR.scala:1096:79]
wire delegable_10 = 1'h0; // @[CSR.scala:1097:65]
wire delegable_11 = 1'h0; // @[CSR.scala:1097:65]
wire _en_T_73 = 1'h0; // @[CSR.scala:1096:71]
wire _en_T_74 = 1'h0; // @[CSR.scala:1096:24]
wire en_12 = 1'h0; // @[CSR.scala:1096:79]
wire delegable_12 = 1'h0; // @[CSR.scala:1097:65]
wire _en_T_79 = 1'h0; // @[CSR.scala:1096:71]
wire _en_T_80 = 1'h0; // @[CSR.scala:1096:24]
wire en_13 = 1'h0; // @[CSR.scala:1096:79]
wire delegable_13 = 1'h0; // @[CSR.scala:1097:65]
wire _en_T_85 = 1'h0; // @[CSR.scala:1096:71]
wire _en_T_86 = 1'h0; // @[CSR.scala:1096:24]
wire en_14 = 1'h0; // @[CSR.scala:1096:79]
wire delegable_14 = 1'h0; // @[CSR.scala:1097:65]
wire _en_T_91 = 1'h0; // @[CSR.scala:1096:71]
wire _en_T_92 = 1'h0; // @[CSR.scala:1096:24]
wire en_15 = 1'h0; // @[CSR.scala:1096:79]
wire delegable_15 = 1'h0; // @[CSR.scala:1097:65]
wire delegable_16 = 1'h0; // @[CSR.scala:1109:67]
wire delegable_20 = 1'h0; // @[CSR.scala:1109:67]
wire delegable_22 = 1'h0; // @[CSR.scala:1109:67]
wire delegable_24 = 1'h0; // @[CSR.scala:1109:67]
wire delegable_25 = 1'h0; // @[CSR.scala:1109:67]
wire _reg_mstatus_v_T = 1'h0; // @[CSR.scala:1123:44]
wire _reg_mstatus_v_T_1 = 1'h0; // @[CSR.scala:1136:42]
wire _reg_mstatus_v_T_3 = 1'h0; // @[CSR.scala:1136:56]
wire _reg_mstatus_v_T_4 = 1'h0; // @[CSR.scala:1141:42]
wire _reg_mstatus_v_T_5 = 1'h0; // @[CSR.scala:1141:82]
wire _reg_mstatus_v_T_6 = 1'h0; // @[CSR.scala:1141:62]
wire _reg_mstatus_mpp_T = 1'h0; // @[CSR.scala:1647:35]
wire _reg_mstatus_mpp_T_1 = 1'h0; // @[CSR.scala:1647:29]
wire _reg_mstatus_v_T_7 = 1'h0; // @[CSR.scala:1150:42]
wire _reg_mstatus_v_T_9 = 1'h0; // @[CSR.scala:1150:61]
wire _io_rw_rdata_T = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_29 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_30 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_31 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_32 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_33 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_34 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_35 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_36 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_37 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_38 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_39 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_40 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_41 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_42 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_43 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_44 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_45 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_46 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_47 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_48 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_49 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_50 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_51 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_52 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_53 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_54 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_55 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_56 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_57 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_58 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_59 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_60 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_61 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_62 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_63 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_64 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_65 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_66 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_67 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_68 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_69 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_70 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_71 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_72 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_73 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_74 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_75 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_76 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_77 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_78 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_79 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_80 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_81 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_82 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_83 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_84 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_85 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_86 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_87 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_88 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_89 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_90 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_91 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_92 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_93 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_94 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_95 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_96 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_97 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_98 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_99 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_100 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_101 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_102 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_103 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_104 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_105 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_106 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_107 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_108 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_109 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_149 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_150 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_151 = 1'h0; // @[Mux.scala:30:73]
wire set_vs_dirty = 1'h0; // @[CSR.scala:1191:33]
wire new_mip_hi_hi_hi_hi = 1'h0; // @[CSR.scala:1271:59]
wire _reg_bp_0_WIRE_control_dmode = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_0_WIRE_control_action = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_0_WIRE_control_chain = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_0_WIRE_control_m = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_0_WIRE_control_h = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_0_WIRE_control_s = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_0_WIRE_control_u = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_0_WIRE_control_x = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_0_WIRE_control_w = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_0_WIRE_control_r = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_0_WIRE_textra_mselect = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_0_WIRE_textra_pad1 = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_0_WIRE_textra_sselect = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_1_WIRE_control_dmode = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_1_WIRE_control_action = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_1_WIRE_control_chain = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_1_WIRE_control_m = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_1_WIRE_control_h = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_1_WIRE_control_s = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_1_WIRE_control_u = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_1_WIRE_control_x = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_1_WIRE_control_w = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_1_WIRE_control_r = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_1_WIRE_textra_mselect = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_1_WIRE_textra_pad1 = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_1_WIRE_textra_sselect = 1'h0; // @[CSR.scala:1613:23]
wire [7:0] io_status_zero1 = 8'h0; // @[CSR.scala:377:7]
wire [7:0] io_gstatus_zero1 = 8'h0; // @[CSR.scala:377:7]
wire [7:0] _reset_mstatus_WIRE_zero1 = 8'h0; // @[CSR.scala:391:47]
wire [7:0] reset_mstatus_zero1 = 8'h0; // @[CSR.scala:391:34]
wire [7:0] lo_2 = 8'h0; // @[CSR.scala:479:12]
wire [7:0] hi_2 = 8'h0; // @[CSR.scala:479:12]
wire [7:0] lo_3 = 8'h0; // @[CSR.scala:479:27]
wire [7:0] hi_3 = 8'h0; // @[CSR.scala:479:27]
wire [7:0] sie_mask_lo = 8'h0; // @[CSR.scala:750:59]
wire [7:0] _read_sstatus_WIRE_zero1 = 8'h0; // @[CSR.scala:755:48]
wire [7:0] read_sstatus_zero1 = 8'h0; // @[CSR.scala:755:35]
wire [1:0] io_status_xs = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_status_vs = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_hstatus_zero3 = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_hstatus_zero2 = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_gstatus_dprv = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_gstatus_prv = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_gstatus_sxl = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_gstatus_xs = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_gstatus_mpp = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_gstatus_vs = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_0_cfg_res = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_1_cfg_res = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_2_cfg_res = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_3_cfg_res = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_4_cfg_res = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_5_cfg_res = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_6_cfg_res = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_7_cfg_res = 2'h0; // @[CSR.scala:377:7]
wire [1:0] _reset_mstatus_WIRE_dprv = 2'h0; // @[CSR.scala:391:47]
wire [1:0] _reset_mstatus_WIRE_prv = 2'h0; // @[CSR.scala:391:47]
wire [1:0] _reset_mstatus_WIRE_sxl = 2'h0; // @[CSR.scala:391:47]
wire [1:0] _reset_mstatus_WIRE_uxl = 2'h0; // @[CSR.scala:391:47]
wire [1:0] _reset_mstatus_WIRE_xs = 2'h0; // @[CSR.scala:391:47]
wire [1:0] _reset_mstatus_WIRE_fs = 2'h0; // @[CSR.scala:391:47]
wire [1:0] _reset_mstatus_WIRE_mpp = 2'h0; // @[CSR.scala:391:47]
wire [1:0] _reset_mstatus_WIRE_vs = 2'h0; // @[CSR.scala:391:47]
wire [1:0] reset_mstatus_dprv = 2'h0; // @[CSR.scala:391:34]
wire [1:0] reset_mstatus_sxl = 2'h0; // @[CSR.scala:391:34]
wire [1:0] reset_mstatus_uxl = 2'h0; // @[CSR.scala:391:34]
wire [1:0] reset_mstatus_xs = 2'h0; // @[CSR.scala:391:34]
wire [1:0] reset_mstatus_fs = 2'h0; // @[CSR.scala:391:34]
wire [1:0] reset_mstatus_vs = 2'h0; // @[CSR.scala:391:34]
wire [1:0] _reset_dcsr_WIRE_xdebugver = 2'h0; // @[CSR.scala:400:44]
wire [1:0] _reset_dcsr_WIRE_zero4 = 2'h0; // @[CSR.scala:400:44]
wire [1:0] _reset_dcsr_WIRE_zero1 = 2'h0; // @[CSR.scala:400:44]
wire [1:0] _reset_dcsr_WIRE_prv = 2'h0; // @[CSR.scala:400:44]
wire [1:0] reset_dcsr_zero4 = 2'h0; // @[CSR.scala:400:31]
wire [1:0] reset_dcsr_zero1 = 2'h0; // @[CSR.scala:400:31]
wire [1:0] hi_hi_lo = 2'h0; // @[CSR.scala:431:10]
wire [1:0] hi_hi_hi = 2'h0; // @[CSR.scala:431:10]
wire [1:0] lo_lo_hi_1 = 2'h0; // @[CSR.scala:431:50]
wire [1:0] lo_hi_hi_1 = 2'h0; // @[CSR.scala:431:50]
wire [1:0] hi_lo_hi_1 = 2'h0; // @[CSR.scala:431:50]
wire [1:0] hi_hi_lo_1 = 2'h0; // @[CSR.scala:431:50]
wire [1:0] hi_hi_hi_1 = 2'h0; // @[CSR.scala:431:50]
wire [1:0] lo_lo_lo_2 = 2'h0; // @[CSR.scala:479:12]
wire [1:0] lo_lo_hi_2 = 2'h0; // @[CSR.scala:479:12]
wire [1:0] lo_hi_lo_2 = 2'h0; // @[CSR.scala:479:12]
wire [1:0] lo_hi_hi_2 = 2'h0; // @[CSR.scala:479:12]
wire [1:0] hi_lo_lo_2 = 2'h0; // @[CSR.scala:479:12]
wire [1:0] hi_lo_hi_2 = 2'h0; // @[CSR.scala:479:12]
wire [1:0] hi_hi_lo_2 = 2'h0; // @[CSR.scala:479:12]
wire [1:0] hi_hi_hi_2 = 2'h0; // @[CSR.scala:479:12]
wire [1:0] lo_lo_lo_3 = 2'h0; // @[CSR.scala:479:27]
wire [1:0] lo_lo_hi_3 = 2'h0; // @[CSR.scala:479:27]
wire [1:0] lo_hi_lo_3 = 2'h0; // @[CSR.scala:479:27]
wire [1:0] lo_hi_hi_3 = 2'h0; // @[CSR.scala:479:27]
wire [1:0] hi_lo_lo_3 = 2'h0; // @[CSR.scala:479:27]
wire [1:0] hi_lo_hi_3 = 2'h0; // @[CSR.scala:479:27]
wire [1:0] hi_hi_lo_3 = 2'h0; // @[CSR.scala:479:27]
wire [1:0] hi_hi_hi_3 = 2'h0; // @[CSR.scala:479:27]
wire [1:0] _reset_mnstatus_WIRE_mpp = 2'h0; // @[CSR.scala:516:48]
wire [1:0] _reg_menvcfg_WIRE_cbie = 2'h0; // @[CSR.scala:525:41]
wire [1:0] _reg_senvcfg_WIRE_cbie = 2'h0; // @[CSR.scala:526:41]
wire [1:0] _reg_henvcfg_WIRE_cbie = 2'h0; // @[CSR.scala:527:41]
wire [1:0] _reg_hstatus_WIRE_vsxl = 2'h0; // @[CSR.scala:552:41]
wire [1:0] _reg_hstatus_WIRE_zero3 = 2'h0; // @[CSR.scala:552:41]
wire [1:0] _reg_hstatus_WIRE_zero2 = 2'h0; // @[CSR.scala:552:41]
wire [1:0] read_hvip_lo_lo_hi = 2'h0; // @[CSR.scala:555:27]
wire [1:0] read_hvip_lo_hi_hi = 2'h0; // @[CSR.scala:555:27]
wire [1:0] read_hvip_hi_lo_hi = 2'h0; // @[CSR.scala:555:27]
wire [1:0] read_hvip_hi_hi_lo = 2'h0; // @[CSR.scala:555:27]
wire [1:0] pmp_cfg_res = 2'h0; // @[PMP.scala:24:19]
wire [1:0] pmp_1_cfg_res = 2'h0; // @[PMP.scala:24:19]
wire [1:0] pmp_2_cfg_res = 2'h0; // @[PMP.scala:24:19]
wire [1:0] pmp_3_cfg_res = 2'h0; // @[PMP.scala:24:19]
wire [1:0] pmp_4_cfg_res = 2'h0; // @[PMP.scala:24:19]
wire [1:0] pmp_5_cfg_res = 2'h0; // @[PMP.scala:24:19]
wire [1:0] pmp_6_cfg_res = 2'h0; // @[PMP.scala:24:19]
wire [1:0] pmp_7_cfg_res = 2'h0; // @[PMP.scala:24:19]
wire [1:0] read_mapping_lo_lo_hi = 2'h0; // @[CSR.scala:655:48]
wire [1:0] read_mapping_lo_hi_lo = 2'h0; // @[CSR.scala:655:48]
wire [1:0] read_mapping_lo_hi_hi = 2'h0; // @[CSR.scala:655:48]
wire [1:0] read_mapping_hi_lo_hi = 2'h0; // @[CSR.scala:655:48]
wire [1:0] read_mapping_lo_1 = 2'h0; // @[CSR.scala:657:47]
wire [1:0] debug_csrs_lo_hi_hi = 2'h0; // @[CSR.scala:670:27]
wire [1:0] _read_mnstatus_WIRE_mpp = 2'h0; // @[CSR.scala:675:44]
wire [1:0] read_vcsr = 2'h0; // @[CSR.scala:695:22]
wire [1:0] hi_hi_4 = 2'h0; // @[CSR.scala:742:49]
wire [1:0] sie_mask_lo_lo_lo = 2'h0; // @[CSR.scala:750:59]
wire [1:0] sie_mask_lo_lo_hi = 2'h0; // @[CSR.scala:750:59]
wire [1:0] sie_mask_lo_hi_lo = 2'h0; // @[CSR.scala:750:59]
wire [1:0] sie_mask_lo_hi_hi = 2'h0; // @[CSR.scala:750:59]
wire [1:0] sie_mask_hi_lo_lo = 2'h0; // @[CSR.scala:750:59]
wire [1:0] sie_mask_hi_lo_hi = 2'h0; // @[CSR.scala:750:59]
wire [1:0] sie_mask_hi_hi_hi = 2'h0; // @[CSR.scala:750:59]
wire [1:0] _read_sstatus_WIRE_dprv = 2'h0; // @[CSR.scala:755:48]
wire [1:0] _read_sstatus_WIRE_prv = 2'h0; // @[CSR.scala:755:48]
wire [1:0] _read_sstatus_WIRE_sxl = 2'h0; // @[CSR.scala:755:48]
wire [1:0] _read_sstatus_WIRE_uxl = 2'h0; // @[CSR.scala:755:48]
wire [1:0] _read_sstatus_WIRE_xs = 2'h0; // @[CSR.scala:755:48]
wire [1:0] _read_sstatus_WIRE_fs = 2'h0; // @[CSR.scala:755:48]
wire [1:0] _read_sstatus_WIRE_mpp = 2'h0; // @[CSR.scala:755:48]
wire [1:0] _read_sstatus_WIRE_vs = 2'h0; // @[CSR.scala:755:48]
wire [1:0] read_sstatus_dprv = 2'h0; // @[CSR.scala:755:35]
wire [1:0] read_sstatus_prv = 2'h0; // @[CSR.scala:755:35]
wire [1:0] read_sstatus_sxl = 2'h0; // @[CSR.scala:755:35]
wire [1:0] read_sstatus_xs = 2'h0; // @[CSR.scala:755:35]
wire [1:0] read_sstatus_mpp = 2'h0; // @[CSR.scala:755:35]
wire [1:0] read_sstatus_vs = 2'h0; // @[CSR.scala:755:35]
wire [1:0] lo_lo_lo_hi = 2'h0; // @[CSR.scala:768:51]
wire [1:0] lo_hi_hi_hi_hi = 2'h0; // @[CSR.scala:768:51]
wire [1:0] hi_lo_hi_hi_hi = 2'h0; // @[CSR.scala:768:51]
wire [1:0] hi_hi_hi_hi_hi = 2'h0; // @[CSR.scala:768:51]
wire [1:0] hi_hi_6 = 2'h0; // @[CSR.scala:780:49]
wire [1:0] read_pmp_15_cfg_res = 2'h0; // @[CSR.scala:787:59]
wire [1:0] read_pmp_15_cfg_a = 2'h0; // @[CSR.scala:787:59]
wire [1:0] lo_hi_16 = 2'h0; // @[package.scala:45:36]
wire [1:0] lo_hi_17 = 2'h0; // @[package.scala:45:36]
wire [1:0] lo_hi_18 = 2'h0; // @[package.scala:45:36]
wire [1:0] lo_hi_19 = 2'h0; // @[package.scala:45:36]
wire [1:0] lo_hi_20 = 2'h0; // @[package.scala:45:36]
wire [1:0] lo_hi_21 = 2'h0; // @[package.scala:45:36]
wire [1:0] lo_hi_22 = 2'h0; // @[package.scala:45:36]
wire [1:0] lo_hi_23 = 2'h0; // @[package.scala:45:36]
wire [1:0] decoded_orMatrixOutputs_lo_lo = 2'h0; // @[pla.scala:102:36]
wire [1:0] decoded_orMatrixOutputs_lo_lo_1 = 2'h0; // @[pla.scala:102:36]
wire [1:0] decoded_orMatrixOutputs_lo_lo_2 = 2'h0; // @[pla.scala:102:36]
wire [1:0] decoded_orMatrixOutputs_lo_lo_3 = 2'h0; // @[pla.scala:102:36]
wire [1:0] nmiTVec = 2'h0; // @[CSR.scala:993:62]
wire [1:0] new_mip_lo_lo_hi = 2'h0; // @[CSR.scala:1271:59]
wire [1:0] new_mip_lo_hi_hi = 2'h0; // @[CSR.scala:1271:59]
wire [1:0] new_mip_hi_lo_hi = 2'h0; // @[CSR.scala:1271:59]
wire [1:0] new_mip_hi_hi_lo = 2'h0; // @[CSR.scala:1271:59]
wire [1:0] _reg_bp_0_WIRE_control_zero = 2'h0; // @[CSR.scala:1613:23]
wire [1:0] _reg_bp_0_WIRE_control_tmatch = 2'h0; // @[CSR.scala:1613:23]
wire [1:0] _reg_bp_1_WIRE_control_zero = 2'h0; // @[CSR.scala:1613:23]
wire [1:0] _reg_bp_1_WIRE_control_tmatch = 2'h0; // @[CSR.scala:1613:23]
wire [15:0] io_ptbr_asid = 16'h0; // @[CSR.scala:377:7]
wire [15:0] io_hgatp_asid = 16'h0; // @[CSR.scala:377:7]
wire [15:0] io_vsatp_asid = 16'h0; // @[CSR.scala:377:7]
wire [15:0] hs_delegable_interrupts = 16'h0; // @[CSR.scala:479:12]
wire [15:0] mideleg_always_hs = 16'h0; // @[CSR.scala:479:27]
wire [15:0] read_hvip = 16'h0; // @[CSR.scala:555:34]
wire [15:0] read_hip = 16'h0; // @[CSR.scala:611:27]
wire [15:0] lo_lo_8 = 16'h0; // @[package.scala:45:27]
wire [15:0] lo_hi_24 = 16'h0; // @[package.scala:45:27]
wire [15:0] hi_lo_8 = 16'h0; // @[package.scala:45:27]
wire [15:0] hi_hi_24 = 16'h0; // @[package.scala:45:27]
wire [15:0] _en_T = 16'h0; // @[CSR.scala:1096:49]
wire [15:0] _delegable_T = 16'h0; // @[CSR.scala:1097:43]
wire [15:0] _en_T_12 = 16'h0; // @[CSR.scala:1096:49]
wire [15:0] _delegable_T_2 = 16'h0; // @[CSR.scala:1097:43]
wire [15:0] _delegable_T_3 = 16'h0; // @[CSR.scala:1097:43]
wire [15:0] _en_T_24 = 16'h0; // @[CSR.scala:1096:49]
wire [15:0] _delegable_T_4 = 16'h0; // @[CSR.scala:1097:43]
wire [15:0] _en_T_36 = 16'h0; // @[CSR.scala:1096:49]
wire [15:0] _delegable_T_6 = 16'h0; // @[CSR.scala:1097:43]
wire [15:0] _delegable_T_7 = 16'h0; // @[CSR.scala:1097:43]
wire [15:0] _en_T_48 = 16'h0; // @[CSR.scala:1096:49]
wire [15:0] _delegable_T_8 = 16'h0; // @[CSR.scala:1097:43]
wire [15:0] _en_T_60 = 16'h0; // @[CSR.scala:1096:49]
wire [15:0] _delegable_T_10 = 16'h0; // @[CSR.scala:1097:43]
wire [15:0] _delegable_T_11 = 16'h0; // @[CSR.scala:1097:43]
wire [15:0] _en_T_72 = 16'h0; // @[CSR.scala:1096:49]
wire [15:0] _delegable_T_12 = 16'h0; // @[CSR.scala:1097:43]
wire [15:0] _en_T_78 = 16'h0; // @[CSR.scala:1096:49]
wire [15:0] _delegable_T_13 = 16'h0; // @[CSR.scala:1097:43]
wire [15:0] _en_T_84 = 16'h0; // @[CSR.scala:1096:49]
wire [15:0] _delegable_T_14 = 16'h0; // @[CSR.scala:1097:43]
wire [15:0] _en_T_90 = 16'h0; // @[CSR.scala:1096:49]
wire [15:0] _delegable_T_15 = 16'h0; // @[CSR.scala:1097:43]
wire [15:0] _delegable_T_16 = 16'h0; // @[CSR.scala:1109:45]
wire [15:0] _delegable_T_20 = 16'h0; // @[CSR.scala:1109:45]
wire [15:0] _delegable_T_22 = 16'h0; // @[CSR.scala:1109:45]
wire [15:0] _delegable_T_24 = 16'h0; // @[CSR.scala:1109:45]
wire [15:0] _delegable_T_25 = 16'h0; // @[CSR.scala:1109:45]
wire [5:0] io_hstatus_vgein = 6'h0; // @[CSR.scala:377:7]
wire [5:0] _reg_hstatus_WIRE_vgein = 6'h0; // @[CSR.scala:552:41]
wire [5:0] read_mapping_hi_lo = 6'h0; // @[CSR.scala:655:48]
wire [5:0] hi_lo_hi_4 = 6'h0; // @[CSR.scala:768:51]
wire [5:0] _reg_bp_0_WIRE_control_maskmax = 6'h0; // @[CSR.scala:1613:23]
wire [5:0] _reg_bp_1_WIRE_control_maskmax = 6'h0; // @[CSR.scala:1613:23]
wire [3:0] io_hgatp_mode = 4'h0; // @[CSR.scala:377:7]
wire [3:0] io_vsatp_mode = 4'h0; // @[CSR.scala:377:7]
wire [3:0] hi_hi = 4'h0; // @[CSR.scala:431:10]
wire [3:0] hi_hi_1 = 4'h0; // @[CSR.scala:431:50]
wire [3:0] lo_lo_2 = 4'h0; // @[CSR.scala:479:12]
wire [3:0] lo_hi_2 = 4'h0; // @[CSR.scala:479:12]
wire [3:0] hi_lo_2 = 4'h0; // @[CSR.scala:479:12]
wire [3:0] hi_hi_2 = 4'h0; // @[CSR.scala:479:12]
wire [3:0] lo_lo_3 = 4'h0; // @[CSR.scala:479:27]
wire [3:0] lo_hi_3 = 4'h0; // @[CSR.scala:479:27]
wire [3:0] hi_lo_3 = 4'h0; // @[CSR.scala:479:27]
wire [3:0] hi_hi_3 = 4'h0; // @[CSR.scala:479:27]
wire [3:0] read_mapping_lo_hi = 4'h0; // @[CSR.scala:655:48]
wire [3:0] read_mapping_hi_lo_lo = 4'h0; // @[CSR.scala:655:48]
wire [3:0] sie_mask_lo_lo = 4'h0; // @[CSR.scala:750:59]
wire [3:0] sie_mask_lo_hi = 4'h0; // @[CSR.scala:750:59]
wire [3:0] sie_mask_hi_lo = 4'h0; // @[CSR.scala:750:59]
wire [3:0] lo_hi_lo_lo = 4'h0; // @[CSR.scala:768:51]
wire [3:0] hi_hi_lo_hi = 4'h0; // @[CSR.scala:768:51]
wire [3:0] _reg_bp_0_WIRE_control_ttype = 4'h0; // @[CSR.scala:1613:23]
wire [3:0] _reg_bp_1_WIRE_control_ttype = 4'h0; // @[CSR.scala:1613:23]
wire [63:0] io_customCSRs_0_sdata = 64'h0; // @[CSR.scala:377:7]
wire [63:0] io_customCSRs_1_sdata = 64'h0; // @[CSR.scala:377:7]
wire [63:0] io_customCSRs_2_sdata = 64'h0; // @[CSR.scala:377:7]
wire [63:0] io_customCSRs_3_sdata = 64'h0; // @[CSR.scala:377:7]
wire [63:0] read_hideleg = 64'h0; // @[CSR.scala:541:14]
wire [63:0] read_hedeleg = 64'h0; // @[CSR.scala:545:14]
wire [63:0] read_hie = 64'h0; // @[CSR.scala:556:26]
wire [63:0] read_vstvec = 64'h0; // @[package.scala:132:15]
wire [63:0] _vs_interrupts_T_6 = 64'h0; // @[CSR.scala:622:153]
wire [63:0] vs_interrupts = 64'h0; // @[CSR.scala:622:26]
wire [63:0] read_mapping_1_2 = 64'h0; // @[CSR.scala:655:48]
wire [63:0] read_mapping_2_2 = 64'h0; // @[package.scala:132:15]
wire [63:0] _io_rw_rdata_T_1 = 64'h0; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_2 = 64'h0; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_128 = 64'h0; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_152 = 64'h0; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_153 = 64'h0; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_154 = 64'h0; // @[Mux.scala:30:73]
wire [63:0] _reg_custom_3_T = 64'h0; // @[CSR.scala:1506:23]
wire [63:0] _reg_custom_0_T_4 = 64'h0; // @[CSR.scala:1531:24]
wire [63:0] _reg_custom_1_T_4 = 64'h0; // @[CSR.scala:1531:24]
wire [63:0] _reg_custom_2_T_4 = 64'h0; // @[CSR.scala:1531:24]
wire [63:0] _reg_custom_3_T_4 = 64'h0; // @[CSR.scala:1531:24]
wire [29:0] io_hstatus_zero6 = 30'h0; // @[CSR.scala:377:7]
wire [29:0] _reg_hstatus_WIRE_zero6 = 30'h0; // @[CSR.scala:552:41]
wire [29:0] read_pmp_15_addr = 30'h0; // @[CSR.scala:787:59]
wire [29:0] _io_rw_rdata_T_137 = 30'h0; // @[Mux.scala:30:73]
wire [29:0] _io_rw_rdata_T_138 = 30'h0; // @[Mux.scala:30:73]
wire [29:0] _io_rw_rdata_T_139 = 30'h0; // @[Mux.scala:30:73]
wire [29:0] _io_rw_rdata_T_140 = 30'h0; // @[Mux.scala:30:73]
wire [29:0] _io_rw_rdata_T_141 = 30'h0; // @[Mux.scala:30:73]
wire [29:0] _io_rw_rdata_T_142 = 30'h0; // @[Mux.scala:30:73]
wire [29:0] _io_rw_rdata_T_143 = 30'h0; // @[Mux.scala:30:73]
wire [29:0] _io_rw_rdata_T_144 = 30'h0; // @[Mux.scala:30:73]
wire [50:0] read_mapping_hi_hi = 51'h0; // @[CSR.scala:655:48]
wire [50:0] read_mapping_3_2 = 51'h0; // @[CSR.scala:657:47]
wire [50:0] _io_rw_rdata_T_3 = 51'h0; // @[Mux.scala:30:73]
wire [1:0] reset_dcsr_xdebugver = 2'h1; // @[CSR.scala:400:31]
wire [1:0] _read_mapping_T_4 = 2'h1; // @[CSR.scala:1665:36]
wire [1:0] _debug_csrs_T_2 = 2'h1; // @[CSR.scala:1665:36]
wire [1:0] sie_mask_hi_hi_lo = 2'h1; // @[CSR.scala:750:59]
wire [1:0] _io_evec_T_2 = 2'h1; // @[CSR.scala:1665:36]
wire [1:0] _io_evec_T_7 = 2'h1; // @[CSR.scala:1665:36]
wire [1:0] _io_evec_T_12 = 2'h1; // @[CSR.scala:1665:36]
wire [1:0] _io_evec_T_17 = 2'h1; // @[CSR.scala:1665:36]
wire [1:0] _io_evec_T_22 = 2'h1; // @[CSR.scala:1665:36]
wire [4:0] io_hstatus_zero1 = 5'h0; // @[CSR.scala:377:7]
wire [4:0] _reg_hstatus_WIRE_zero1 = 5'h0; // @[CSR.scala:552:41]
wire [4:0] read_mapping_hi_hi_hi = 5'h0; // @[CSR.scala:655:48]
wire [4:0] hi_19 = 5'h0; // @[package.scala:45:36]
wire [4:0] hi_20 = 5'h0; // @[package.scala:45:36]
wire [4:0] hi_21 = 5'h0; // @[package.scala:45:36]
wire [4:0] hi_22 = 5'h0; // @[package.scala:45:36]
wire [4:0] hi_23 = 5'h0; // @[package.scala:45:36]
wire [4:0] hi_24 = 5'h0; // @[package.scala:45:36]
wire [4:0] hi_25 = 5'h0; // @[package.scala:45:36]
wire [4:0] hi_26 = 5'h0; // @[package.scala:45:36]
wire [2:0] _reset_dcsr_WIRE_cause = 3'h0; // @[CSR.scala:400:44]
wire [2:0] reset_dcsr_cause = 3'h0; // @[CSR.scala:400:31]
wire [2:0] _reset_mnstatus_WIRE_zero3 = 3'h0; // @[CSR.scala:516:48]
wire [2:0] _reset_mnstatus_WIRE_zero2 = 3'h0; // @[CSR.scala:516:48]
wire [2:0] _reset_mnstatus_WIRE_zero1 = 3'h0; // @[CSR.scala:516:48]
wire [2:0] reset_mnstatus_zero3 = 3'h0; // @[CSR.scala:516:35]
wire [2:0] reset_mnstatus_zero2 = 3'h0; // @[CSR.scala:516:35]
wire [2:0] reset_mnstatus_zero1 = 3'h0; // @[CSR.scala:516:35]
wire [2:0] _reg_menvcfg_WIRE_zero3 = 3'h0; // @[CSR.scala:525:41]
wire [2:0] _reg_senvcfg_WIRE_zero3 = 3'h0; // @[CSR.scala:526:41]
wire [2:0] _reg_henvcfg_WIRE_zero3 = 3'h0; // @[CSR.scala:527:41]
wire [2:0] read_mapping_lo_lo = 3'h0; // @[CSR.scala:655:48]
wire [2:0] _read_mnstatus_WIRE_zero3 = 3'h0; // @[CSR.scala:675:44]
wire [2:0] _read_mnstatus_WIRE_zero2 = 3'h0; // @[CSR.scala:675:44]
wire [2:0] _read_mnstatus_WIRE_zero1 = 3'h0; // @[CSR.scala:675:44]
wire [2:0] read_mnstatus_zero3 = 3'h0; // @[CSR.scala:675:31]
wire [2:0] read_mnstatus_zero2 = 3'h0; // @[CSR.scala:675:31]
wire [2:0] read_mnstatus_zero1 = 3'h0; // @[CSR.scala:675:31]
wire [2:0] lo_hi_4 = 3'h0; // @[CSR.scala:742:49]
wire [2:0] hi_lo_hi_lo = 3'h0; // @[CSR.scala:768:51]
wire [2:0] hi_lo_hi_hi = 3'h0; // @[CSR.scala:768:51]
wire [2:0] hi_hi_lo_hi_hi = 3'h0; // @[CSR.scala:768:51]
wire [2:0] hi_hi_hi_hi_4 = 3'h0; // @[CSR.scala:768:51]
wire [2:0] lo_hi_6 = 3'h0; // @[CSR.scala:780:49]
wire [2:0] lo_16 = 3'h0; // @[package.scala:45:36]
wire [2:0] hi_hi_16 = 3'h0; // @[package.scala:45:36]
wire [2:0] lo_17 = 3'h0; // @[package.scala:45:36]
wire [2:0] hi_hi_17 = 3'h0; // @[package.scala:45:36]
wire [2:0] lo_18 = 3'h0; // @[package.scala:45:36]
wire [2:0] hi_hi_18 = 3'h0; // @[package.scala:45:36]
wire [2:0] lo_19 = 3'h0; // @[package.scala:45:36]
wire [2:0] hi_hi_19 = 3'h0; // @[package.scala:45:36]
wire [2:0] lo_20 = 3'h0; // @[package.scala:45:36]
wire [2:0] hi_hi_20 = 3'h0; // @[package.scala:45:36]
wire [2:0] lo_21 = 3'h0; // @[package.scala:45:36]
wire [2:0] hi_hi_21 = 3'h0; // @[package.scala:45:36]
wire [2:0] lo_22 = 3'h0; // @[package.scala:45:36]
wire [2:0] hi_hi_22 = 3'h0; // @[package.scala:45:36]
wire [2:0] lo_23 = 3'h0; // @[package.scala:45:36]
wire [2:0] hi_hi_23 = 3'h0; // @[package.scala:45:36]
wire [56:0] read_mapping_hi = 57'h0; // @[CSR.scala:655:48]
wire [56:0] hi_6 = 57'h0; // @[CSR.scala:742:49]
wire [56:0] hi_9 = 57'h0; // @[CSR.scala:780:49]
wire [54:0] hi_lo_4 = 55'h0; // @[CSR.scala:742:49]
wire [54:0] hi_lo_6 = 55'h0; // @[CSR.scala:780:49]
wire [8:0] io_hstatus_zero5 = 9'h0; // @[CSR.scala:377:7]
wire [8:0] _reg_hstatus_WIRE_zero5 = 9'h0; // @[CSR.scala:552:41]
wire [8:0] hi_lo_lo_lo = 9'h0; // @[CSR.scala:768:51]
wire [1:0] io_gstatus_fs = 2'h3; // @[CSR.scala:377:7]
wire [1:0] reset_mstatus_prv = 2'h3; // @[CSR.scala:391:34]
wire [1:0] reset_mstatus_mpp = 2'h3; // @[CSR.scala:391:34]
wire [1:0] reset_dcsr_prv = 2'h3; // @[CSR.scala:400:31]
wire [1:0] reset_mnstatus_mpp = 2'h3; // @[CSR.scala:516:35]
wire [1:0] read_mnstatus_mpp = 2'h3; // @[CSR.scala:675:31]
wire [3:0] _which_T_64 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] _which_T_65 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] _which_T_66 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] _which_T_67 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] _which_T_68 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] _which_T_69 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] _which_T_70 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] _which_T_71 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] _which_T_72 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] _which_T_73 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] _which_T_74 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] _which_T_75 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] _which_T_76 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] _which_T_77 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] _which_T_78 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] debug_csrs_hi_hi_hi = 4'h4; // @[CSR.scala:670:27]
wire [48:0] read_mapping_hi_1 = 49'h0; // @[CSR.scala:657:47]
wire [24:0] _read_mapping_T_1 = 25'h0; // @[package.scala:132:20]
wire [45:0] read_mapping_hi_hi_lo = 46'h0; // @[CSR.scala:655:48]
wire [6:0] read_mapping_lo = 7'h0; // @[CSR.scala:655:48]
wire [2:0] read_mstatus_hi_lo_hi_lo = 3'h2; // @[CSR.scala:649:32]
wire [43:0] io_hgatp_ppn = 44'h0; // @[CSR.scala:377:7]
wire [43:0] io_vsatp_ppn = 44'h0; // @[CSR.scala:377:7]
wire [47:0] _reg_bp_0_WIRE_textra_pad2 = 48'h0; // @[CSR.scala:1613:23]
wire [47:0] _reg_bp_1_WIRE_textra_pad2 = 48'h0; // @[CSR.scala:1613:23]
wire [38:0] _read_stvec_T_2 = 39'h0; // @[package.scala:174:46]
wire [38:0] _reg_bp_0_WIRE_address = 39'h0; // @[CSR.scala:1613:23]
wire [38:0] _reg_bp_1_WIRE_address = 39'h0; // @[CSR.scala:1613:23]
wire [39:0] io_htval = 40'h0; // @[CSR.scala:377:7]
wire [39:0] _reg_bp_0_WIRE_control_reserved = 40'h0; // @[CSR.scala:1613:23]
wire [39:0] _reg_bp_1_WIRE_control_reserved = 40'h0; // @[CSR.scala:1613:23]
wire [1:0] io_status_sxl = 2'h2; // @[CSR.scala:377:7]
wire [1:0] io_status_uxl = 2'h2; // @[CSR.scala:377:7]
wire [1:0] io_hstatus_vsxl = 2'h2; // @[CSR.scala:377:7]
wire [1:0] io_gstatus_uxl = 2'h2; // @[CSR.scala:377:7]
wire [1:0] lo_lo_lo = 2'h2; // @[CSR.scala:431:10]
wire [1:0] lo_lo_hi = 2'h2; // @[CSR.scala:431:10]
wire [1:0] lo_hi_lo = 2'h2; // @[CSR.scala:431:10]
wire [1:0] lo_hi_hi = 2'h2; // @[CSR.scala:431:10]
wire [1:0] hi_lo_lo = 2'h2; // @[CSR.scala:431:10]
wire [1:0] hi_lo_hi = 2'h2; // @[CSR.scala:431:10]
wire [1:0] lo_lo_lo_1 = 2'h2; // @[CSR.scala:431:50]
wire [1:0] lo_hi_lo_1 = 2'h2; // @[CSR.scala:431:50]
wire [1:0] hi_lo_lo_1 = 2'h2; // @[CSR.scala:431:50]
wire [1:0] read_sstatus_uxl = 2'h2; // @[CSR.scala:755:35]
wire [31:0] io_gstatus_isa = 32'h0; // @[CSR.scala:377:7]
wire [31:0] io_inst_0 = 32'h0; // @[CSR.scala:377:7]
wire [31:0] io_inst_1 = 32'h0; // @[CSR.scala:377:7]
wire [31:0] io_inst_2 = 32'h0; // @[CSR.scala:377:7]
wire [31:0] io_trace_0_insn = 32'h0; // @[CSR.scala:377:7]
wire [31:0] io_trace_1_insn = 32'h0; // @[CSR.scala:377:7]
wire [31:0] io_trace_2_insn = 32'h0; // @[CSR.scala:377:7]
wire [31:0] _reset_mstatus_WIRE_isa = 32'h0; // @[CSR.scala:391:47]
wire [31:0] reset_mstatus_isa = 32'h0; // @[CSR.scala:391:34]
wire [31:0] read_hcounteren = 32'h0; // @[CSR.scala:550:14]
wire [31:0] _read_mtvec_T_2 = 32'h0; // @[package.scala:174:46]
wire [31:0] _read_sstatus_WIRE_isa = 32'h0; // @[CSR.scala:755:48]
wire [31:0] read_sstatus_isa = 32'h0; // @[CSR.scala:755:35]
wire [31:0] read_pmp_15_mask = 32'h0; // @[CSR.scala:787:59]
wire [31:0] lo_24 = 32'h0; // @[package.scala:45:27]
wire [31:0] hi_27 = 32'h0; // @[package.scala:45:27]
wire [63:0] _s_interrupts_T_7 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:621:168]
wire [63:0] _reg_custom_3_T_1 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1506:40]
wire [63:0] _reg_custom_3_T_5 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1531:41]
wire [63:0] _reg_custom_2_T_1 = 64'hFFFFFFFFFFFFFFF7; // @[CSR.scala:1506:40]
wire [63:0] _reg_custom_2_T_5 = 64'hFFFFFFFFFFFFFFF7; // @[CSR.scala:1531:41]
wire [63:0] _reg_custom_0_T_1 = 64'hFFFFFFFFFFFFFFFE; // @[CSR.scala:1506:40]
wire [63:0] _reg_custom_1_T_1 = 64'hFFFFFFFFFFFFFFFE; // @[CSR.scala:1506:40]
wire [63:0] _reg_custom_0_T_5 = 64'hFFFFFFFFFFFFFFFE; // @[CSR.scala:1531:41]
wire [63:0] _reg_custom_1_T_5 = 64'hFFFFFFFFFFFFFFFE; // @[CSR.scala:1531:41]
wire [63:0] _reg_mcountinhibit_T = 64'hFFFFFFFFFFFFFFFD; // @[CSR.scala:1306:78]
wire [15:0] _sie_mask_T = 16'h1000; // @[CSR.scala:750:59]
wire [15:0] _sie_mask_T_1 = 16'h1000; // @[CSR.scala:750:46]
wire [15:0] _delegable_T_26 = 16'h1000; // @[CSR.scala:1109:45]
wire [15:0] _en_T_18 = 16'h8; // @[CSR.scala:1096:49]
wire [15:0] _delegable_T_18 = 16'h8; // @[CSR.scala:1109:45]
wire [63:0] _en_T_94 = 64'h800000000000000F; // @[CSR.scala:1096:120]
wire [63:0] _en_T_88 = 64'h800000000000000E; // @[CSR.scala:1096:120]
wire [63:0] _en_T_82 = 64'h800000000000000D; // @[CSR.scala:1096:120]
wire [63:0] _en_T_76 = 64'h800000000000000C; // @[CSR.scala:1096:120]
wire [63:0] _en_T_70 = 64'h800000000000000B; // @[CSR.scala:1096:120]
wire [15:0] _en_T_66 = 16'h800; // @[CSR.scala:1096:49]
wire [63:0] _en_T_64 = 64'h800000000000000A; // @[CSR.scala:1096:120]
wire [15:0] _en_T_54 = 16'h200; // @[CSR.scala:1096:49]
wire [15:0] _delegable_T_9 = 16'h200; // @[CSR.scala:1097:43]
wire [63:0] _en_T_58 = 64'h8000000000000009; // @[CSR.scala:1096:120]
wire [63:0] _en_T_52 = 64'h8000000000000008; // @[CSR.scala:1096:120]
wire [63:0] _en_T_46 = 64'h8000000000000007; // @[CSR.scala:1096:120]
wire [15:0] _en_T_42 = 16'h80; // @[CSR.scala:1096:49]
wire [63:0] _en_T_40 = 64'h8000000000000006; // @[CSR.scala:1096:120]
wire [15:0] _en_T_30 = 16'h20; // @[CSR.scala:1096:49]
wire [15:0] _delegable_T_5 = 16'h20; // @[CSR.scala:1097:43]
wire [63:0] _en_T_34 = 64'h8000000000000005; // @[CSR.scala:1096:120]
wire [63:0] _en_T_28 = 64'h8000000000000004; // @[CSR.scala:1096:120]
wire [63:0] _en_T_22 = 64'h8000000000000003; // @[CSR.scala:1096:120]
wire [63:0] _en_T_16 = 64'h8000000000000002; // @[CSR.scala:1096:120]
wire [15:0] _en_T_6 = 16'h2; // @[CSR.scala:1096:49]
wire [15:0] _delegable_T_1 = 16'h2; // @[CSR.scala:1097:43]
wire [63:0] _en_T_10 = 64'h8000000000000001; // @[CSR.scala:1096:120]
wire [63:0] _interruptCause_T_2 = 64'h8000000000000000; // @[CSR.scala:625:39]
wire [63:0] _en_T_4 = 64'h8000000000000000; // @[CSR.scala:1096:120]
wire [64:0] _interruptCause_T_1 = 65'h8000000000000000; // @[CSR.scala:625:39]
wire [64:0] _en_T_3 = 65'h8000000000000000; // @[CSR.scala:1096:120]
wire [9:0] _io_decode_0_write_flush_addr_m_T = 10'h300; // @[CSR.scala:932:36]
wire [9:0] _io_decode_1_write_flush_addr_m_T = 10'h300; // @[CSR.scala:932:36]
wire [9:0] _io_decode_2_write_flush_addr_m_T = 10'h300; // @[CSR.scala:932:36]
wire [36:0] hi_hi_hi_4 = 37'h0; // @[CSR.scala:768:51]
wire [33:0] hi_hi_hi_lo = 34'h0; // @[CSR.scala:768:51]
wire [17:0] hi_lo_5 = 18'h800; // @[CSR.scala:768:51]
wire [11:0] hi_lo_lo_4 = 12'h800; // @[CSR.scala:768:51]
wire [2:0] _which_T_63 = 3'h4; // @[Mux.scala:50:70]
wire [2:0] read_mstatus_hi_lo_lo_hi = 3'h4; // @[CSR.scala:649:32]
wire [2:0] hi_lo_lo_hi = 3'h4; // @[CSR.scala:768:51]
wire [15:0] _sie_mask_T_2 = 16'hEFFF; // @[CSR.scala:750:20]
wire [7:0] sie_mask_hi = 8'h10; // @[CSR.scala:750:59]
wire [3:0] sie_mask_hi_hi = 4'h1; // @[CSR.scala:750:59]
wire [53:0] _reg_menvcfg_WIRE_zero54 = 54'h0; // @[CSR.scala:525:41]
wire [53:0] _reg_senvcfg_WIRE_zero54 = 54'h0; // @[CSR.scala:526:41]
wire [53:0] _reg_henvcfg_WIRE_zero54 = 54'h0; // @[CSR.scala:527:41]
wire [15:0] delegable_interrupts = 16'h222; // @[CSR.scala:431:50]
wire [7:0] hi_1 = 8'h2; // @[CSR.scala:431:50]
wire [3:0] lo_lo_1 = 4'h2; // @[CSR.scala:431:50]
wire [3:0] lo_hi_1 = 4'h2; // @[CSR.scala:431:50]
wire [3:0] hi_lo_1 = 4'h2; // @[CSR.scala:431:50]
wire [7:0] lo_1 = 8'h22; // @[CSR.scala:431:50]
wire [15:0] supported_interrupts = 16'hAAA; // @[CSR.scala:431:17]
wire [7:0] hi = 8'hA; // @[CSR.scala:431:10]
wire [3:0] lo_lo = 4'hA; // @[CSR.scala:431:10]
wire [3:0] lo_hi = 4'hA; // @[CSR.scala:431:10]
wire [3:0] hi_lo = 4'hA; // @[CSR.scala:431:10]
wire [7:0] lo = 8'hAA; // @[CSR.scala:431:10]
wire [11:0] _reset_dcsr_WIRE_zero3 = 12'h0; // @[CSR.scala:400:44]
wire [11:0] reset_dcsr_zero3 = 12'h0; // @[CSR.scala:400:31]
wire [15:0] _delegable_T_27 = 16'h2000; // @[CSR.scala:1109:45]
wire [15:0] _delegable_T_23 = 16'h100; // @[CSR.scala:1109:45]
wire [15:0] _delegable_T_21 = 16'h40; // @[CSR.scala:1109:45]
wire [15:0] _delegable_T_19 = 16'h10; // @[CSR.scala:1109:45]
wire [15:0] _delegable_T_17 = 16'h4; // @[CSR.scala:1109:45]
wire [64:0] _en_T_93 = 65'h800000000000000F; // @[CSR.scala:1096:120]
wire [64:0] _en_T_87 = 65'h800000000000000E; // @[CSR.scala:1096:120]
wire [64:0] _en_T_81 = 65'h800000000000000D; // @[CSR.scala:1096:120]
wire [64:0] _en_T_75 = 65'h800000000000000C; // @[CSR.scala:1096:120]
wire [64:0] _en_T_69 = 65'h800000000000000B; // @[CSR.scala:1096:120]
wire [64:0] _en_T_63 = 65'h800000000000000A; // @[CSR.scala:1096:120]
wire [64:0] _en_T_57 = 65'h8000000000000009; // @[CSR.scala:1096:120]
wire [64:0] _en_T_51 = 65'h8000000000000008; // @[CSR.scala:1096:120]
wire [64:0] _en_T_45 = 65'h8000000000000007; // @[CSR.scala:1096:120]
wire [64:0] _en_T_39 = 65'h8000000000000006; // @[CSR.scala:1096:120]
wire [64:0] _en_T_33 = 65'h8000000000000005; // @[CSR.scala:1096:120]
wire [64:0] _en_T_27 = 65'h8000000000000004; // @[CSR.scala:1096:120]
wire [64:0] _en_T_21 = 65'h8000000000000003; // @[CSR.scala:1096:120]
wire [64:0] _en_T_15 = 65'h8000000000000002; // @[CSR.scala:1096:120]
wire [64:0] _en_T_9 = 65'h8000000000000001; // @[CSR.scala:1096:120]
wire [62:0] _interruptCause_T = 63'h0; // @[CSR.scala:625:50]
wire [15:0] _delegable_T_28 = 16'h8000; // @[CSR.scala:1109:45]
wire [39:0] _io_evec_T_15 = 40'hFFFFFFFFFF; // @[CSR.scala:1665:28]
wire mip_mtip = io_interrupts_mtip_0; // @[CSR.scala:377:7, :600:24]
wire mip_msip = io_interrupts_msip_0; // @[CSR.scala:377:7, :600:24]
wire mip_meip = io_interrupts_meip_0; // @[CSR.scala:377:7, :600:24]
wire [63:0] _io_rw_rdata_WIRE; // @[Mux.scala:30:73]
wire [31:0] decoded_plaInput_1 = io_decode_0_inst_0; // @[pla.scala:77:22]
wire _io_decode_0_fp_illegal_T_6; // @[CSR.scala:915:91]
wire _io_decode_0_fp_csr_T; // @[Decode.scala:55:116]
wire _io_decode_0_read_illegal_T_20; // @[CSR.scala:928:68]
wire _io_decode_0_write_illegal_T_1; // @[CSR.scala:930:41]
wire _io_decode_0_write_flush_T_3; // @[CSR.scala:933:7]
wire _io_decode_0_system_illegal_T_25; // @[CSR.scala:940:44]
wire _io_decode_0_virtual_access_illegal_T_29; // @[CSR.scala:943:66]
wire _io_decode_0_virtual_system_illegal_T_22; // @[CSR.scala:949:52]
wire [31:0] decoded_plaInput_2 = io_decode_1_inst_0; // @[pla.scala:77:22]
wire _io_decode_1_fp_illegal_T_6; // @[CSR.scala:915:91]
wire _io_decode_1_fp_csr_T; // @[Decode.scala:55:116]
wire _io_decode_1_read_illegal_T_20; // @[CSR.scala:928:68]
wire _io_decode_1_write_illegal_T_1; // @[CSR.scala:930:41]
wire _io_decode_1_write_flush_T_3; // @[CSR.scala:933:7]
wire _io_decode_1_system_illegal_T_25; // @[CSR.scala:940:44]
wire _io_decode_1_virtual_access_illegal_T_29; // @[CSR.scala:943:66]
wire _io_decode_1_virtual_system_illegal_T_22; // @[CSR.scala:949:52]
wire [31:0] decoded_plaInput_3 = io_decode_2_inst_0; // @[pla.scala:77:22]
wire _io_decode_2_fp_illegal_T_6; // @[CSR.scala:915:91]
wire _io_decode_2_fp_csr_T; // @[Decode.scala:55:116]
wire _io_decode_2_read_illegal_T_20; // @[CSR.scala:928:68]
wire _io_decode_2_write_illegal_T_1; // @[CSR.scala:930:41]
wire _io_decode_2_write_flush_T_3; // @[CSR.scala:933:7]
wire _io_decode_2_system_illegal_T_25; // @[CSR.scala:940:44]
wire _io_decode_2_virtual_access_illegal_T_29; // @[CSR.scala:943:66]
wire _io_decode_2_virtual_system_illegal_T_22; // @[CSR.scala:949:52]
wire _io_csr_stall_T; // @[CSR.scala:1161:27]
wire _io_eret_T_1; // @[CSR.scala:1000:38]
wire _io_singleStep_T_1; // @[CSR.scala:1001:34]
wire [1:0] _io_status_dprv_T_2; // @[CSR.scala:1008:24]
wire _io_status_dv_T_3; // @[CSR.scala:1009:33]
wire _io_status_sd_T_4; // @[CSR.scala:1003:58]
wire read_sstatus_sd = io_status_sd_0; // @[CSR.scala:377:7, :755:35]
wire read_sstatus_mxr = io_status_mxr_0; // @[CSR.scala:377:7, :755:35]
wire read_sstatus_sum = io_status_sum_0; // @[CSR.scala:377:7, :755:35]
wire [1:0] read_sstatus_fs = io_status_fs_0; // @[CSR.scala:377:7, :755:35]
wire read_sstatus_spp = io_status_spp_0; // @[CSR.scala:377:7, :755:35]
wire read_sstatus_spie = io_status_spie_0; // @[CSR.scala:377:7, :755:35]
wire read_sstatus_sie = io_status_sie_0; // @[CSR.scala:377:7, :755:35]
wire [39:0] io_trace_0_iaddr = io_pc_0; // @[CSR.scala:377:7]
wire [39:0] io_trace_1_iaddr = io_pc_0; // @[CSR.scala:377:7]
wire [39:0] io_trace_2_iaddr = io_pc_0; // @[CSR.scala:377:7]
wire [39:0] io_trace_0_tval = io_tval_0; // @[CSR.scala:377:7]
wire [39:0] io_trace_1_tval = io_tval_0; // @[CSR.scala:377:7]
wire [39:0] io_trace_2_tval = io_tval_0; // @[CSR.scala:377:7]
wire [63:0] value_1; // @[Counters.scala:55:30]
wire _io_interrupt_T_5; // @[CSR.scala:626:73]
wire [63:0] interruptCause; // @[CSR.scala:625:63]
wire pmp_cfg_l; // @[PMP.scala:24:19]
wire [1:0] pmp_cfg_a; // @[PMP.scala:24:19]
wire pmp_cfg_x; // @[PMP.scala:24:19]
wire pmp_cfg_w; // @[PMP.scala:24:19]
wire pmp_cfg_r; // @[PMP.scala:24:19]
wire [29:0] pmp_addr; // @[PMP.scala:24:19]
wire [31:0] pmp_mask; // @[PMP.scala:24:19]
wire pmp_1_cfg_l; // @[PMP.scala:24:19]
wire [1:0] pmp_1_cfg_a; // @[PMP.scala:24:19]
wire pmp_1_cfg_x; // @[PMP.scala:24:19]
wire pmp_1_cfg_w; // @[PMP.scala:24:19]
wire pmp_1_cfg_r; // @[PMP.scala:24:19]
wire [29:0] pmp_1_addr; // @[PMP.scala:24:19]
wire [31:0] pmp_1_mask; // @[PMP.scala:24:19]
wire pmp_2_cfg_l; // @[PMP.scala:24:19]
wire [1:0] pmp_2_cfg_a; // @[PMP.scala:24:19]
wire pmp_2_cfg_x; // @[PMP.scala:24:19]
wire pmp_2_cfg_w; // @[PMP.scala:24:19]
wire pmp_2_cfg_r; // @[PMP.scala:24:19]
wire [29:0] pmp_2_addr; // @[PMP.scala:24:19]
wire [31:0] pmp_2_mask; // @[PMP.scala:24:19]
wire pmp_3_cfg_l; // @[PMP.scala:24:19]
wire [1:0] pmp_3_cfg_a; // @[PMP.scala:24:19]
wire pmp_3_cfg_x; // @[PMP.scala:24:19]
wire pmp_3_cfg_w; // @[PMP.scala:24:19]
wire pmp_3_cfg_r; // @[PMP.scala:24:19]
wire [29:0] pmp_3_addr; // @[PMP.scala:24:19]
wire [31:0] pmp_3_mask; // @[PMP.scala:24:19]
wire pmp_4_cfg_l; // @[PMP.scala:24:19]
wire [1:0] pmp_4_cfg_a; // @[PMP.scala:24:19]
wire pmp_4_cfg_x; // @[PMP.scala:24:19]
wire pmp_4_cfg_w; // @[PMP.scala:24:19]
wire pmp_4_cfg_r; // @[PMP.scala:24:19]
wire [29:0] pmp_4_addr; // @[PMP.scala:24:19]
wire [31:0] pmp_4_mask; // @[PMP.scala:24:19]
wire pmp_5_cfg_l; // @[PMP.scala:24:19]
wire [1:0] pmp_5_cfg_a; // @[PMP.scala:24:19]
wire pmp_5_cfg_x; // @[PMP.scala:24:19]
wire pmp_5_cfg_w; // @[PMP.scala:24:19]
wire pmp_5_cfg_r; // @[PMP.scala:24:19]
wire [29:0] pmp_5_addr; // @[PMP.scala:24:19]
wire [31:0] pmp_5_mask; // @[PMP.scala:24:19]
wire pmp_6_cfg_l; // @[PMP.scala:24:19]
wire [1:0] pmp_6_cfg_a; // @[PMP.scala:24:19]
wire pmp_6_cfg_x; // @[PMP.scala:24:19]
wire pmp_6_cfg_w; // @[PMP.scala:24:19]
wire pmp_6_cfg_r; // @[PMP.scala:24:19]
wire [29:0] pmp_6_addr; // @[PMP.scala:24:19]
wire [31:0] pmp_6_mask; // @[PMP.scala:24:19]
wire pmp_7_cfg_l; // @[PMP.scala:24:19]
wire [1:0] pmp_7_cfg_a; // @[PMP.scala:24:19]
wire pmp_7_cfg_x; // @[PMP.scala:24:19]
wire pmp_7_cfg_w; // @[PMP.scala:24:19]
wire pmp_7_cfg_r; // @[PMP.scala:24:19]
wire [29:0] pmp_7_addr; // @[PMP.scala:24:19]
wire [31:0] pmp_7_mask; // @[PMP.scala:24:19]
wire _io_inhibit_cycle_T; // @[CSR.scala:591:40]
wire _io_trace_0_valid_T_1; // @[CSR.scala:1621:32]
wire [2:0] _io_trace_0_priv_T; // @[CSR.scala:1624:18]
wire _io_trace_0_exception_T_1; // @[CSR.scala:1620:37]
wire _io_trace_0_interrupt_T; // @[CSR.scala:1626:25]
wire [63:0] cause; // @[CSR.scala:959:8]
wire _io_trace_1_valid_T_1; // @[CSR.scala:1621:32]
wire [2:0] _io_trace_1_priv_T; // @[CSR.scala:1624:18]
wire _io_trace_1_exception_T_1; // @[CSR.scala:1620:37]
wire _io_trace_1_interrupt_T; // @[CSR.scala:1626:25]
wire _io_trace_2_valid_T_1; // @[CSR.scala:1621:32]
wire [2:0] _io_trace_2_priv_T; // @[CSR.scala:1624:18]
wire _io_trace_2_exception_T_1; // @[CSR.scala:1620:37]
wire _io_trace_2_interrupt_T; // @[CSR.scala:1626:25]
wire _io_fiom_T_6; // @[CSR.scala:631:113]
wire reg_custom_read; // @[CSR.scala:799:36]
wire [63:0] wdata; // @[CSR.scala:1643:39]
wire reg_custom_read_1; // @[CSR.scala:799:36]
wire reg_custom_read_2; // @[CSR.scala:799:36]
wire reg_custom_read_3; // @[CSR.scala:799:36]
wire [63:0] io_rw_rdata_0; // @[CSR.scala:377:7]
wire io_decode_0_fp_illegal_0; // @[CSR.scala:377:7]
wire io_decode_0_fp_csr_0; // @[CSR.scala:377:7]
wire io_decode_0_read_illegal_0; // @[CSR.scala:377:7]
wire io_decode_0_write_illegal_0; // @[CSR.scala:377:7]
wire io_decode_0_write_flush_0; // @[CSR.scala:377:7]
wire io_decode_0_system_illegal_0; // @[CSR.scala:377:7]
wire io_decode_0_virtual_access_illegal_0; // @[CSR.scala:377:7]
wire io_decode_0_virtual_system_illegal_0; // @[CSR.scala:377:7]
wire io_decode_1_fp_illegal_0; // @[CSR.scala:377:7]
wire io_decode_1_fp_csr_0; // @[CSR.scala:377:7]
wire io_decode_1_read_illegal_0; // @[CSR.scala:377:7]
wire io_decode_1_write_illegal_0; // @[CSR.scala:377:7]
wire io_decode_1_write_flush_0; // @[CSR.scala:377:7]
wire io_decode_1_system_illegal_0; // @[CSR.scala:377:7]
wire io_decode_1_virtual_access_illegal_0; // @[CSR.scala:377:7]
wire io_decode_1_virtual_system_illegal_0; // @[CSR.scala:377:7]
wire io_decode_2_fp_illegal_0; // @[CSR.scala:377:7]
wire io_decode_2_fp_csr_0; // @[CSR.scala:377:7]
wire io_decode_2_read_illegal_0; // @[CSR.scala:377:7]
wire io_decode_2_write_illegal_0; // @[CSR.scala:377:7]
wire io_decode_2_write_flush_0; // @[CSR.scala:377:7]
wire io_decode_2_system_illegal_0; // @[CSR.scala:377:7]
wire io_decode_2_virtual_access_illegal_0; // @[CSR.scala:377:7]
wire io_decode_2_virtual_system_illegal_0; // @[CSR.scala:377:7]
wire io_status_debug_0; // @[CSR.scala:377:7]
wire io_status_cease_0; // @[CSR.scala:377:7]
wire io_status_wfi_0; // @[CSR.scala:377:7]
wire [1:0] io_status_dprv_0; // @[CSR.scala:377:7]
wire io_status_dv_0; // @[CSR.scala:377:7]
wire [1:0] io_status_prv_0; // @[CSR.scala:377:7]
wire io_status_v_0; // @[CSR.scala:377:7]
wire io_status_mpv_0; // @[CSR.scala:377:7]
wire io_status_gva_0; // @[CSR.scala:377:7]
wire io_status_tsr_0; // @[CSR.scala:377:7]
wire io_status_tw_0; // @[CSR.scala:377:7]
wire io_status_tvm_0; // @[CSR.scala:377:7]
wire io_status_mprv_0; // @[CSR.scala:377:7]
wire [1:0] io_status_mpp_0; // @[CSR.scala:377:7]
wire io_status_mpie_0; // @[CSR.scala:377:7]
wire io_status_mie_0; // @[CSR.scala:377:7]
wire io_hstatus_spvp; // @[CSR.scala:377:7]
wire io_hstatus_spv; // @[CSR.scala:377:7]
wire io_hstatus_gva; // @[CSR.scala:377:7]
wire io_gstatus_spp; // @[CSR.scala:377:7]
wire io_gstatus_spie; // @[CSR.scala:377:7]
wire io_gstatus_sie; // @[CSR.scala:377:7]
wire [3:0] io_ptbr_mode_0; // @[CSR.scala:377:7]
wire [43:0] io_ptbr_ppn_0; // @[CSR.scala:377:7]
wire io_pmp_0_cfg_l_0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_0_cfg_a_0; // @[CSR.scala:377:7]
wire io_pmp_0_cfg_x_0; // @[CSR.scala:377:7]
wire io_pmp_0_cfg_w_0; // @[CSR.scala:377:7]
wire io_pmp_0_cfg_r_0; // @[CSR.scala:377:7]
wire [29:0] io_pmp_0_addr_0; // @[CSR.scala:377:7]
wire [31:0] io_pmp_0_mask_0; // @[CSR.scala:377:7]
wire io_pmp_1_cfg_l_0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_1_cfg_a_0; // @[CSR.scala:377:7]
wire io_pmp_1_cfg_x_0; // @[CSR.scala:377:7]
wire io_pmp_1_cfg_w_0; // @[CSR.scala:377:7]
wire io_pmp_1_cfg_r_0; // @[CSR.scala:377:7]
wire [29:0] io_pmp_1_addr_0; // @[CSR.scala:377:7]
wire [31:0] io_pmp_1_mask_0; // @[CSR.scala:377:7]
wire io_pmp_2_cfg_l_0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_2_cfg_a_0; // @[CSR.scala:377:7]
wire io_pmp_2_cfg_x_0; // @[CSR.scala:377:7]
wire io_pmp_2_cfg_w_0; // @[CSR.scala:377:7]
wire io_pmp_2_cfg_r_0; // @[CSR.scala:377:7]
wire [29:0] io_pmp_2_addr_0; // @[CSR.scala:377:7]
wire [31:0] io_pmp_2_mask_0; // @[CSR.scala:377:7]
wire io_pmp_3_cfg_l_0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_3_cfg_a_0; // @[CSR.scala:377:7]
wire io_pmp_3_cfg_x_0; // @[CSR.scala:377:7]
wire io_pmp_3_cfg_w_0; // @[CSR.scala:377:7]
wire io_pmp_3_cfg_r_0; // @[CSR.scala:377:7]
wire [29:0] io_pmp_3_addr_0; // @[CSR.scala:377:7]
wire [31:0] io_pmp_3_mask_0; // @[CSR.scala:377:7]
wire io_pmp_4_cfg_l_0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_4_cfg_a_0; // @[CSR.scala:377:7]
wire io_pmp_4_cfg_x_0; // @[CSR.scala:377:7]
wire io_pmp_4_cfg_w_0; // @[CSR.scala:377:7]
wire io_pmp_4_cfg_r_0; // @[CSR.scala:377:7]
wire [29:0] io_pmp_4_addr_0; // @[CSR.scala:377:7]
wire [31:0] io_pmp_4_mask_0; // @[CSR.scala:377:7]
wire io_pmp_5_cfg_l_0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_5_cfg_a_0; // @[CSR.scala:377:7]
wire io_pmp_5_cfg_x_0; // @[CSR.scala:377:7]
wire io_pmp_5_cfg_w_0; // @[CSR.scala:377:7]
wire io_pmp_5_cfg_r_0; // @[CSR.scala:377:7]
wire [29:0] io_pmp_5_addr_0; // @[CSR.scala:377:7]
wire [31:0] io_pmp_5_mask_0; // @[CSR.scala:377:7]
wire io_pmp_6_cfg_l_0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_6_cfg_a_0; // @[CSR.scala:377:7]
wire io_pmp_6_cfg_x_0; // @[CSR.scala:377:7]
wire io_pmp_6_cfg_w_0; // @[CSR.scala:377:7]
wire io_pmp_6_cfg_r_0; // @[CSR.scala:377:7]
wire [29:0] io_pmp_6_addr_0; // @[CSR.scala:377:7]
wire [31:0] io_pmp_6_mask_0; // @[CSR.scala:377:7]
wire io_pmp_7_cfg_l_0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_7_cfg_a_0; // @[CSR.scala:377:7]
wire io_pmp_7_cfg_x_0; // @[CSR.scala:377:7]
wire io_pmp_7_cfg_w_0; // @[CSR.scala:377:7]
wire io_pmp_7_cfg_r_0; // @[CSR.scala:377:7]
wire [29:0] io_pmp_7_addr_0; // @[CSR.scala:377:7]
wire [31:0] io_pmp_7_mask_0; // @[CSR.scala:377:7]
wire [63:0] io_counters_0_eventSel_0; // @[CSR.scala:377:7]
wire [63:0] io_counters_1_eventSel_0; // @[CSR.scala:377:7]
wire io_trace_0_valid; // @[CSR.scala:377:7]
wire [2:0] io_trace_0_priv; // @[CSR.scala:377:7]
wire io_trace_0_exception; // @[CSR.scala:377:7]
wire io_trace_0_interrupt; // @[CSR.scala:377:7]
wire [63:0] io_trace_0_cause; // @[CSR.scala:377:7]
wire io_trace_1_valid; // @[CSR.scala:377:7]
wire [2:0] io_trace_1_priv; // @[CSR.scala:377:7]
wire io_trace_1_exception; // @[CSR.scala:377:7]
wire io_trace_1_interrupt; // @[CSR.scala:377:7]
wire [63:0] io_trace_1_cause; // @[CSR.scala:377:7]
wire io_trace_2_valid; // @[CSR.scala:377:7]
wire [2:0] io_trace_2_priv; // @[CSR.scala:377:7]
wire io_trace_2_exception; // @[CSR.scala:377:7]
wire io_trace_2_interrupt; // @[CSR.scala:377:7]
wire [63:0] io_trace_2_cause; // @[CSR.scala:377:7]
wire io_customCSRs_0_ren_0; // @[CSR.scala:377:7]
wire io_customCSRs_0_wen_0; // @[CSR.scala:377:7]
wire [63:0] io_customCSRs_0_wdata_0; // @[CSR.scala:377:7]
wire [63:0] io_customCSRs_0_value_0; // @[CSR.scala:377:7]
wire io_customCSRs_1_ren_0; // @[CSR.scala:377:7]
wire io_customCSRs_1_wen_0; // @[CSR.scala:377:7]
wire [63:0] io_customCSRs_1_wdata_0; // @[CSR.scala:377:7]
wire [63:0] io_customCSRs_1_value_0; // @[CSR.scala:377:7]
wire io_customCSRs_2_ren_0; // @[CSR.scala:377:7]
wire io_customCSRs_2_wen_0; // @[CSR.scala:377:7]
wire [63:0] io_customCSRs_2_wdata_0; // @[CSR.scala:377:7]
wire [63:0] io_customCSRs_2_value_0; // @[CSR.scala:377:7]
wire io_customCSRs_3_ren_0; // @[CSR.scala:377:7]
wire io_customCSRs_3_wen_0; // @[CSR.scala:377:7]
wire [63:0] io_customCSRs_3_wdata_0; // @[CSR.scala:377:7]
wire [63:0] io_customCSRs_3_value_0; // @[CSR.scala:377:7]
wire io_csr_stall_0; // @[CSR.scala:377:7]
wire io_eret; // @[CSR.scala:377:7]
wire io_singleStep_0; // @[CSR.scala:377:7]
wire [39:0] io_evec_0; // @[CSR.scala:377:7]
wire [63:0] io_time_0; // @[CSR.scala:377:7]
wire [2:0] io_fcsr_rm_0; // @[CSR.scala:377:7]
wire io_interrupt_0; // @[CSR.scala:377:7]
wire [63:0] io_interrupt_cause_0; // @[CSR.scala:377:7]
wire [31:0] io_csrw_counter; // @[CSR.scala:377:7]
wire io_inhibit_cycle; // @[CSR.scala:377:7]
wire io_fiom; // @[CSR.scala:377:7]
reg [1:0] reg_mstatus_prv; // @[CSR.scala:395:28]
assign io_status_prv_0 = reg_mstatus_prv; // @[CSR.scala:377:7, :395:28]
reg reg_mstatus_v; // @[CSR.scala:395:28]
assign io_status_v_0 = reg_mstatus_v; // @[CSR.scala:377:7, :395:28]
wire _io_decode_0_rocc_illegal_T_2 = reg_mstatus_v; // @[CSR.scala:395:28, :919:66]
wire _io_decode_1_rocc_illegal_T_2 = reg_mstatus_v; // @[CSR.scala:395:28, :919:66]
wire _io_decode_2_rocc_illegal_T_2 = reg_mstatus_v; // @[CSR.scala:395:28, :919:66]
reg reg_mstatus_mpv; // @[CSR.scala:395:28]
assign io_status_mpv_0 = reg_mstatus_mpv; // @[CSR.scala:377:7, :395:28]
reg reg_mstatus_gva; // @[CSR.scala:395:28]
assign io_status_gva_0 = reg_mstatus_gva; // @[CSR.scala:377:7, :395:28]
reg reg_mstatus_tsr; // @[CSR.scala:395:28]
assign io_status_tsr_0 = reg_mstatus_tsr; // @[CSR.scala:377:7, :395:28]
reg reg_mstatus_tw; // @[CSR.scala:395:28]
assign io_status_tw_0 = reg_mstatus_tw; // @[CSR.scala:377:7, :395:28]
reg reg_mstatus_tvm; // @[CSR.scala:395:28]
assign io_status_tvm_0 = reg_mstatus_tvm; // @[CSR.scala:377:7, :395:28]
reg reg_mstatus_mxr; // @[CSR.scala:395:28]
assign io_status_mxr_0 = reg_mstatus_mxr; // @[CSR.scala:377:7, :395:28]
reg reg_mstatus_sum; // @[CSR.scala:395:28]
assign io_status_sum_0 = reg_mstatus_sum; // @[CSR.scala:377:7, :395:28]
reg reg_mstatus_mprv; // @[CSR.scala:395:28]
assign io_status_mprv_0 = reg_mstatus_mprv; // @[CSR.scala:377:7, :395:28]
reg [1:0] reg_mstatus_fs; // @[CSR.scala:395:28]
assign io_status_fs_0 = reg_mstatus_fs; // @[CSR.scala:377:7, :395:28]
reg [1:0] reg_mstatus_mpp; // @[CSR.scala:395:28]
assign io_status_mpp_0 = reg_mstatus_mpp; // @[CSR.scala:377:7, :395:28]
reg reg_mstatus_spp; // @[CSR.scala:395:28]
assign io_status_spp_0 = reg_mstatus_spp; // @[CSR.scala:377:7, :395:28]
reg reg_mstatus_mpie; // @[CSR.scala:395:28]
assign io_status_mpie_0 = reg_mstatus_mpie; // @[CSR.scala:377:7, :395:28]
reg reg_mstatus_spie; // @[CSR.scala:395:28]
assign io_status_spie_0 = reg_mstatus_spie; // @[CSR.scala:377:7, :395:28]
reg reg_mstatus_mie; // @[CSR.scala:395:28]
assign io_status_mie_0 = reg_mstatus_mie; // @[CSR.scala:377:7, :395:28]
reg reg_mstatus_sie; // @[CSR.scala:395:28]
assign io_status_sie_0 = reg_mstatus_sie; // @[CSR.scala:377:7, :395:28]
wire [1:0] new_prv; // @[CSR.scala:397:28]
wire _reg_mstatus_prv_T = new_prv == 2'h2; // @[CSR.scala:397:28, :1647:35]
wire [1:0] _reg_mstatus_prv_T_1 = _reg_mstatus_prv_T ? 2'h0 : new_prv; // @[CSR.scala:397:28, :1647:{29,35}]
reg reg_dcsr_ebreakm; // @[CSR.scala:403:25]
reg reg_dcsr_ebreaks; // @[CSR.scala:403:25]
reg reg_dcsr_ebreaku; // @[CSR.scala:403:25]
reg [2:0] reg_dcsr_cause; // @[CSR.scala:403:25]
reg reg_dcsr_v; // @[CSR.scala:403:25]
reg reg_dcsr_step; // @[CSR.scala:403:25]
reg [1:0] reg_dcsr_prv; // @[CSR.scala:403:25]
reg reg_debug; // @[CSR.scala:482:26]
assign io_status_debug_0 = reg_debug; // @[CSR.scala:377:7, :482:26]
reg [39:0] reg_dpc; // @[CSR.scala:483:20]
reg [63:0] reg_dscratch0; // @[CSR.scala:484:26]
reg reg_singleStepped; // @[CSR.scala:486:30]
reg reg_pmp_0_cfg_l; // @[CSR.scala:493:20]
assign pmp_cfg_l = reg_pmp_0_cfg_l; // @[PMP.scala:24:19]
reg [1:0] reg_pmp_0_cfg_a; // @[CSR.scala:493:20]
assign pmp_cfg_a = reg_pmp_0_cfg_a; // @[PMP.scala:24:19]
reg reg_pmp_0_cfg_x; // @[CSR.scala:493:20]
assign pmp_cfg_x = reg_pmp_0_cfg_x; // @[PMP.scala:24:19]
reg reg_pmp_0_cfg_w; // @[CSR.scala:493:20]
assign pmp_cfg_w = reg_pmp_0_cfg_w; // @[PMP.scala:24:19]
reg reg_pmp_0_cfg_r; // @[CSR.scala:493:20]
assign pmp_cfg_r = reg_pmp_0_cfg_r; // @[PMP.scala:24:19]
reg [29:0] reg_pmp_0_addr; // @[CSR.scala:493:20]
assign pmp_addr = reg_pmp_0_addr; // @[PMP.scala:24:19]
reg reg_pmp_1_cfg_l; // @[CSR.scala:493:20]
assign pmp_1_cfg_l = reg_pmp_1_cfg_l; // @[PMP.scala:24:19]
reg [1:0] reg_pmp_1_cfg_a; // @[CSR.scala:493:20]
assign pmp_1_cfg_a = reg_pmp_1_cfg_a; // @[PMP.scala:24:19]
reg reg_pmp_1_cfg_x; // @[CSR.scala:493:20]
assign pmp_1_cfg_x = reg_pmp_1_cfg_x; // @[PMP.scala:24:19]
reg reg_pmp_1_cfg_w; // @[CSR.scala:493:20]
assign pmp_1_cfg_w = reg_pmp_1_cfg_w; // @[PMP.scala:24:19]
reg reg_pmp_1_cfg_r; // @[CSR.scala:493:20]
assign pmp_1_cfg_r = reg_pmp_1_cfg_r; // @[PMP.scala:24:19]
reg [29:0] reg_pmp_1_addr; // @[CSR.scala:493:20]
assign pmp_1_addr = reg_pmp_1_addr; // @[PMP.scala:24:19]
reg reg_pmp_2_cfg_l; // @[CSR.scala:493:20]
assign pmp_2_cfg_l = reg_pmp_2_cfg_l; // @[PMP.scala:24:19]
reg [1:0] reg_pmp_2_cfg_a; // @[CSR.scala:493:20]
assign pmp_2_cfg_a = reg_pmp_2_cfg_a; // @[PMP.scala:24:19]
reg reg_pmp_2_cfg_x; // @[CSR.scala:493:20]
assign pmp_2_cfg_x = reg_pmp_2_cfg_x; // @[PMP.scala:24:19]
reg reg_pmp_2_cfg_w; // @[CSR.scala:493:20]
assign pmp_2_cfg_w = reg_pmp_2_cfg_w; // @[PMP.scala:24:19]
reg reg_pmp_2_cfg_r; // @[CSR.scala:493:20]
assign pmp_2_cfg_r = reg_pmp_2_cfg_r; // @[PMP.scala:24:19]
reg [29:0] reg_pmp_2_addr; // @[CSR.scala:493:20]
assign pmp_2_addr = reg_pmp_2_addr; // @[PMP.scala:24:19]
reg reg_pmp_3_cfg_l; // @[CSR.scala:493:20]
assign pmp_3_cfg_l = reg_pmp_3_cfg_l; // @[PMP.scala:24:19]
reg [1:0] reg_pmp_3_cfg_a; // @[CSR.scala:493:20]
assign pmp_3_cfg_a = reg_pmp_3_cfg_a; // @[PMP.scala:24:19]
reg reg_pmp_3_cfg_x; // @[CSR.scala:493:20]
assign pmp_3_cfg_x = reg_pmp_3_cfg_x; // @[PMP.scala:24:19]
reg reg_pmp_3_cfg_w; // @[CSR.scala:493:20]
assign pmp_3_cfg_w = reg_pmp_3_cfg_w; // @[PMP.scala:24:19]
reg reg_pmp_3_cfg_r; // @[CSR.scala:493:20]
assign pmp_3_cfg_r = reg_pmp_3_cfg_r; // @[PMP.scala:24:19]
reg [29:0] reg_pmp_3_addr; // @[CSR.scala:493:20]
assign pmp_3_addr = reg_pmp_3_addr; // @[PMP.scala:24:19]
reg reg_pmp_4_cfg_l; // @[CSR.scala:493:20]
assign pmp_4_cfg_l = reg_pmp_4_cfg_l; // @[PMP.scala:24:19]
reg [1:0] reg_pmp_4_cfg_a; // @[CSR.scala:493:20]
assign pmp_4_cfg_a = reg_pmp_4_cfg_a; // @[PMP.scala:24:19]
reg reg_pmp_4_cfg_x; // @[CSR.scala:493:20]
assign pmp_4_cfg_x = reg_pmp_4_cfg_x; // @[PMP.scala:24:19]
reg reg_pmp_4_cfg_w; // @[CSR.scala:493:20]
assign pmp_4_cfg_w = reg_pmp_4_cfg_w; // @[PMP.scala:24:19]
reg reg_pmp_4_cfg_r; // @[CSR.scala:493:20]
assign pmp_4_cfg_r = reg_pmp_4_cfg_r; // @[PMP.scala:24:19]
reg [29:0] reg_pmp_4_addr; // @[CSR.scala:493:20]
assign pmp_4_addr = reg_pmp_4_addr; // @[PMP.scala:24:19]
reg reg_pmp_5_cfg_l; // @[CSR.scala:493:20]
assign pmp_5_cfg_l = reg_pmp_5_cfg_l; // @[PMP.scala:24:19]
reg [1:0] reg_pmp_5_cfg_a; // @[CSR.scala:493:20]
assign pmp_5_cfg_a = reg_pmp_5_cfg_a; // @[PMP.scala:24:19]
reg reg_pmp_5_cfg_x; // @[CSR.scala:493:20]
assign pmp_5_cfg_x = reg_pmp_5_cfg_x; // @[PMP.scala:24:19]
reg reg_pmp_5_cfg_w; // @[CSR.scala:493:20]
assign pmp_5_cfg_w = reg_pmp_5_cfg_w; // @[PMP.scala:24:19]
reg reg_pmp_5_cfg_r; // @[CSR.scala:493:20]
assign pmp_5_cfg_r = reg_pmp_5_cfg_r; // @[PMP.scala:24:19]
reg [29:0] reg_pmp_5_addr; // @[CSR.scala:493:20]
assign pmp_5_addr = reg_pmp_5_addr; // @[PMP.scala:24:19]
reg reg_pmp_6_cfg_l; // @[CSR.scala:493:20]
assign pmp_6_cfg_l = reg_pmp_6_cfg_l; // @[PMP.scala:24:19]
reg [1:0] reg_pmp_6_cfg_a; // @[CSR.scala:493:20]
assign pmp_6_cfg_a = reg_pmp_6_cfg_a; // @[PMP.scala:24:19]
reg reg_pmp_6_cfg_x; // @[CSR.scala:493:20]
assign pmp_6_cfg_x = reg_pmp_6_cfg_x; // @[PMP.scala:24:19]
reg reg_pmp_6_cfg_w; // @[CSR.scala:493:20]
assign pmp_6_cfg_w = reg_pmp_6_cfg_w; // @[PMP.scala:24:19]
reg reg_pmp_6_cfg_r; // @[CSR.scala:493:20]
assign pmp_6_cfg_r = reg_pmp_6_cfg_r; // @[PMP.scala:24:19]
reg [29:0] reg_pmp_6_addr; // @[CSR.scala:493:20]
assign pmp_6_addr = reg_pmp_6_addr; // @[PMP.scala:24:19]
reg reg_pmp_7_cfg_l; // @[CSR.scala:493:20]
assign pmp_7_cfg_l = reg_pmp_7_cfg_l; // @[PMP.scala:24:19]
reg [1:0] reg_pmp_7_cfg_a; // @[CSR.scala:493:20]
assign pmp_7_cfg_a = reg_pmp_7_cfg_a; // @[PMP.scala:24:19]
reg reg_pmp_7_cfg_x; // @[CSR.scala:493:20]
assign pmp_7_cfg_x = reg_pmp_7_cfg_x; // @[PMP.scala:24:19]
reg reg_pmp_7_cfg_w; // @[CSR.scala:493:20]
assign pmp_7_cfg_w = reg_pmp_7_cfg_w; // @[PMP.scala:24:19]
reg reg_pmp_7_cfg_r; // @[CSR.scala:493:20]
assign pmp_7_cfg_r = reg_pmp_7_cfg_r; // @[PMP.scala:24:19]
reg [29:0] reg_pmp_7_addr; // @[CSR.scala:493:20]
assign pmp_7_addr = reg_pmp_7_addr; // @[PMP.scala:24:19]
reg [63:0] reg_mie; // @[CSR.scala:495:20]
reg [63:0] reg_mideleg; // @[CSR.scala:497:18]
wire [63:0] read_mideleg = {54'h0, reg_mideleg[9:1] & 9'h111, 1'h0}; // @[CSR.scala:497:18, :498:{14,38,61}]
reg [63:0] reg_medeleg; // @[CSR.scala:501:18]
wire [63:0] read_medeleg = {48'h0, reg_medeleg[15:0] & 16'hB15D}; // @[CSR.scala:501:18, :502:{14,38}]
reg reg_mip_seip; // @[CSR.scala:504:20]
reg reg_mip_stip; // @[CSR.scala:504:20]
wire mip_stip = reg_mip_stip; // @[CSR.scala:504:20, :600:24]
reg reg_mip_ssip; // @[CSR.scala:504:20]
wire mip_ssip = reg_mip_ssip; // @[CSR.scala:504:20, :600:24]
reg [39:0] reg_mepc; // @[CSR.scala:505:21]
reg [63:0] reg_mcause; // @[CSR.scala:506:27]
reg [39:0] reg_mtval; // @[CSR.scala:507:22]
reg [39:0] reg_mtval2; // @[CSR.scala:508:23]
reg [63:0] reg_mscratch; // @[CSR.scala:509:25]
reg [31:0] reg_mtvec; // @[CSR.scala:512:31]
reg reg_menvcfg_fiom; // @[CSR.scala:525:28]
reg reg_senvcfg_fiom; // @[CSR.scala:526:28]
reg [31:0] reg_mcounteren; // @[CSR.scala:531:18]
wire [31:0] read_mcounteren = {27'h0, reg_mcounteren[4:0]}; // @[CSR.scala:531:18, :532:{14,32}]
reg [31:0] reg_scounteren; // @[CSR.scala:535:18]
wire [31:0] read_scounteren = {27'h0, reg_scounteren[4:0]}; // @[CSR.scala:535:18, :536:{14,38}]
reg reg_hstatus_spvp; // @[CSR.scala:552:28]
assign io_hstatus_spvp = reg_hstatus_spvp; // @[CSR.scala:377:7, :552:28]
reg reg_hstatus_spv; // @[CSR.scala:552:28]
assign io_hstatus_spv = reg_hstatus_spv; // @[CSR.scala:377:7, :552:28]
reg reg_hstatus_gva; // @[CSR.scala:552:28]
assign io_hstatus_gva = reg_hstatus_gva; // @[CSR.scala:377:7, :552:28]
reg [39:0] reg_htval; // @[CSR.scala:554:22]
wire [1:0] _GEN = {reg_mip_ssip, 1'h0}; // @[CSR.scala:504:20, :555:27]
wire [1:0] read_hvip_lo_lo_lo; // @[CSR.scala:555:27]
assign read_hvip_lo_lo_lo = _GEN; // @[CSR.scala:555:27]
wire [1:0] new_mip_lo_lo_lo; // @[CSR.scala:1271:59]
assign new_mip_lo_lo_lo = _GEN; // @[CSR.scala:555:27, :1271:59]
wire [3:0] read_hvip_lo_lo = {read_hvip_lo_lo_hi, read_hvip_lo_lo_lo}; // @[CSR.scala:555:27]
wire [1:0] _GEN_0 = {reg_mip_stip, 1'h0}; // @[CSR.scala:504:20, :555:27]
wire [1:0] read_hvip_lo_hi_lo; // @[CSR.scala:555:27]
assign read_hvip_lo_hi_lo = _GEN_0; // @[CSR.scala:555:27]
wire [1:0] new_mip_lo_hi_lo; // @[CSR.scala:1271:59]
assign new_mip_lo_hi_lo = _GEN_0; // @[CSR.scala:555:27, :1271:59]
wire [3:0] read_hvip_lo_hi = {read_hvip_lo_hi_hi, read_hvip_lo_hi_lo}; // @[CSR.scala:555:27]
wire [7:0] read_hvip_lo = {read_hvip_lo_hi, read_hvip_lo_lo}; // @[CSR.scala:555:27]
wire [1:0] _GEN_1 = {reg_mip_seip, 1'h0}; // @[CSR.scala:504:20, :555:27]
wire [1:0] read_hvip_hi_lo_lo; // @[CSR.scala:555:27]
assign read_hvip_hi_lo_lo = _GEN_1; // @[CSR.scala:555:27]
wire [1:0] new_mip_hi_lo_lo; // @[CSR.scala:1271:59]
assign new_mip_hi_lo_lo = _GEN_1; // @[CSR.scala:555:27, :1271:59]
wire [3:0] read_hvip_hi_lo = {read_hvip_hi_lo_hi, read_hvip_hi_lo_lo}; // @[CSR.scala:555:27]
wire [1:0] read_hvip_hi_hi_hi = {read_hvip_hi_hi_hi_hi, 1'h0}; // @[CSR.scala:555:27]
wire [3:0] read_hvip_hi_hi = {read_hvip_hi_hi_hi, read_hvip_hi_hi_lo}; // @[CSR.scala:555:27]
wire [7:0] read_hvip_hi = {read_hvip_hi_hi, read_hvip_hi_lo}; // @[CSR.scala:555:27]
wire [15:0] _read_hvip_T = {read_hvip_hi, read_hvip_lo}; // @[CSR.scala:555:27]
reg reg_vsstatus_spp; // @[CSR.scala:562:25]
assign io_gstatus_spp = reg_vsstatus_spp; // @[CSR.scala:377:7, :562:25]
reg reg_vsstatus_spie; // @[CSR.scala:562:25]
assign io_gstatus_spie = reg_vsstatus_spie; // @[CSR.scala:377:7, :562:25]
reg reg_vsstatus_sie; // @[CSR.scala:562:25]
assign io_gstatus_sie = reg_vsstatus_sie; // @[CSR.scala:377:7, :562:25]
reg [39:0] reg_vsepc; // @[CSR.scala:564:22]
reg [63:0] reg_vscause; // @[CSR.scala:565:24]
reg [39:0] reg_vstval; // @[CSR.scala:566:23]
reg [39:0] reg_sepc; // @[CSR.scala:569:21]
reg [63:0] reg_scause; // @[CSR.scala:570:23]
reg [39:0] reg_stval; // @[CSR.scala:571:22]
reg [63:0] reg_sscratch; // @[CSR.scala:572:25]
reg [38:0] reg_stvec; // @[CSR.scala:573:22]
reg [3:0] reg_satp_mode; // @[CSR.scala:574:21]
assign io_ptbr_mode_0 = reg_satp_mode; // @[CSR.scala:377:7, :574:21]
reg [43:0] reg_satp_ppn; // @[CSR.scala:574:21]
assign io_ptbr_ppn_0 = reg_satp_ppn; // @[CSR.scala:377:7, :574:21]
reg reg_wfi; // @[CSR.scala:575:54]
assign io_status_wfi_0 = reg_wfi; // @[CSR.scala:377:7, :575:54]
reg [4:0] reg_fflags; // @[CSR.scala:577:23]
reg [2:0] reg_frm; // @[CSR.scala:578:20]
assign io_fcsr_rm_0 = reg_frm; // @[CSR.scala:377:7, :578:20]
reg reg_mtinst_read_pseudo; // @[CSR.scala:584:35]
reg reg_htinst_read_pseudo; // @[CSR.scala:585:35]
wire [1:0] hi_4 = {2{reg_mtinst_read_pseudo}}; // @[CSR.scala:584:35, :588:103]
wire [13:0] read_mtinst = {hi_4, 12'h0}; // @[CSR.scala:588:103]
wire [1:0] hi_5 = {2{reg_htinst_read_pseudo}}; // @[CSR.scala:585:35, :588:103]
wire [13:0] read_htinst = {hi_5, 12'h0}; // @[CSR.scala:588:103]
reg [4:0] reg_mcountinhibit; // @[CSR.scala:590:34]
assign _io_inhibit_cycle_T = reg_mcountinhibit[0]; // @[CSR.scala:590:34, :591:40]
wire x11 = reg_mcountinhibit[0]; // @[CSR.scala:590:34, :591:40, :594:98]
assign io_inhibit_cycle = _io_inhibit_cycle_T; // @[CSR.scala:377:7, :591:40]
wire x3 = reg_mcountinhibit[2]; // @[CSR.scala:590:34, :592:75]
reg [5:0] small_0; // @[Counters.scala:45:41]
wire [6:0] nextSmall = {1'h0, small_0} + {5'h0, io_retire_0}; // @[Counters.scala:45:41, :46:33]
wire _large_T_1 = ~x3; // @[Counters.scala:47:9, :51:36]
reg [57:0] large_0; // @[Counters.scala:50:31]
wire _large_T = nextSmall[6]; // @[Counters.scala:46:33, :51:20]
wire _large_T_2 = _large_T & _large_T_1; // @[Counters.scala:51:{20,33,36}]
wire [58:0] _large_r_T = {1'h0, large_0} + 59'h1; // @[Counters.scala:50:31, :51:55]
wire [57:0] _large_r_T_1 = _large_r_T[57:0]; // @[Counters.scala:51:55]
wire [63:0] value = {large_0, small_0}; // @[Counters.scala:45:41, :50:31, :55:30]
wire x10 = ~io_csr_stall_0; // @[CSR.scala:377:7, :594:56]
reg [5:0] small_1; // @[Counters.scala:45:41]
wire [6:0] nextSmall_1 = {1'h0, small_1} + {6'h0, x10}; // @[Counters.scala:45:41, :46:33]
wire _large_T_4 = ~x11; // @[Counters.scala:47:9, :51:36]
reg [57:0] large_1; // @[Counters.scala:50:31]
wire _large_T_3 = nextSmall_1[6]; // @[Counters.scala:46:33, :51:20]
wire _large_T_5 = _large_T_3 & _large_T_4; // @[Counters.scala:51:{20,33,36}]
wire [58:0] _large_r_T_2 = {1'h0, large_1} + 59'h1; // @[Counters.scala:50:31, :51:55]
wire [57:0] _large_r_T_3 = _large_r_T_2[57:0]; // @[Counters.scala:51:55]
assign value_1 = {large_1, small_1}; // @[Counters.scala:45:41, :50:31, :55:30]
assign io_time_0 = value_1; // @[Counters.scala:55:30]
reg [63:0] reg_hpmevent_0; // @[CSR.scala:595:50]
assign io_counters_0_eventSel_0 = reg_hpmevent_0; // @[CSR.scala:377:7, :595:50]
reg [63:0] reg_hpmevent_1; // @[CSR.scala:595:50]
assign io_counters_1_eventSel_0 = reg_hpmevent_1; // @[CSR.scala:377:7, :595:50]
reg [5:0] small_2; // @[Counters.scala:45:69]
wire [6:0] nextSmall_2 = {1'h0, small_2} + {5'h0, io_counters_0_inc_0}; // @[Counters.scala:45:69, :46:33]
wire _large_T_7 = ~(reg_mcountinhibit[3]); // @[Counters.scala:47:9, :51:36]
reg [33:0] large_2; // @[Counters.scala:50:69]
wire _large_T_6 = nextSmall_2[6]; // @[Counters.scala:46:33, :51:20]
wire _large_T_8 = _large_T_6 & _large_T_7; // @[Counters.scala:51:{20,33,36}]
wire [34:0] _large_r_T_4 = {1'h0, large_2} + 35'h1; // @[Counters.scala:50:69, :51:55]
wire [33:0] _large_r_T_5 = _large_r_T_4[33:0]; // @[Counters.scala:51:55]
wire [39:0] value_2 = {large_2, small_2}; // @[Counters.scala:45:69, :50:69, :55:30]
reg [5:0] small_3; // @[Counters.scala:45:69]
wire [6:0] nextSmall_3 = {1'h0, small_3} + {5'h0, io_counters_1_inc_0}; // @[Counters.scala:45:69, :46:33]
wire _large_T_10 = ~(reg_mcountinhibit[4]); // @[Counters.scala:47:9, :51:36]
reg [33:0] large_3; // @[Counters.scala:50:69]
wire _large_T_9 = nextSmall_3[6]; // @[Counters.scala:46:33, :51:20]
wire _large_T_11 = _large_T_9 & _large_T_10; // @[Counters.scala:51:{20,33,36}]
wire [34:0] _large_r_T_6 = {1'h0, large_3} + 35'h1; // @[Counters.scala:50:69, :51:55]
wire [33:0] _large_r_T_7 = _large_r_T_6[33:0]; // @[Counters.scala:51:55]
wire [39:0] value_3 = {large_3, small_3}; // @[Counters.scala:45:69, :50:69, :55:30]
wire read_mip_hi_hi_hi_hi = mip_zero1; // @[CSR.scala:600:24, :610:22]
wire _mip_seip_T; // @[CSR.scala:606:57]
wire mip_seip; // @[CSR.scala:600:24]
assign _mip_seip_T = reg_mip_seip | io_interrupts_seip_0; // @[CSR.scala:377:7, :504:20, :606:57]
assign mip_seip = _mip_seip_T; // @[CSR.scala:600:24, :606:57]
wire [1:0] read_mip_lo_lo_lo = {mip_ssip, mip_usip}; // @[CSR.scala:600:24, :610:22]
wire [1:0] read_mip_lo_lo_hi = {mip_msip, mip_vssip}; // @[CSR.scala:600:24, :610:22]
wire [3:0] read_mip_lo_lo = {read_mip_lo_lo_hi, read_mip_lo_lo_lo}; // @[CSR.scala:610:22]
wire [1:0] read_mip_lo_hi_lo = {mip_stip, mip_utip}; // @[CSR.scala:600:24, :610:22]
wire [1:0] read_mip_lo_hi_hi = {mip_mtip, mip_vstip}; // @[CSR.scala:600:24, :610:22]
wire [3:0] read_mip_lo_hi = {read_mip_lo_hi_hi, read_mip_lo_hi_lo}; // @[CSR.scala:610:22]
wire [7:0] read_mip_lo = {read_mip_lo_hi, read_mip_lo_lo}; // @[CSR.scala:610:22]
wire [1:0] read_mip_hi_lo_lo = {mip_seip, mip_ueip}; // @[CSR.scala:600:24, :610:22]
wire [1:0] read_mip_hi_lo_hi = {mip_meip, mip_vseip}; // @[CSR.scala:600:24, :610:22]
wire [3:0] read_mip_hi_lo = {read_mip_hi_lo_hi, read_mip_hi_lo_lo}; // @[CSR.scala:610:22]
wire [1:0] read_mip_hi_hi_lo = {1'h0, mip_sgeip}; // @[CSR.scala:600:24, :610:22]
wire [1:0] read_mip_hi_hi_hi = {read_mip_hi_hi_hi_hi, mip_debug}; // @[CSR.scala:600:24, :610:22]
wire [3:0] read_mip_hi_hi = {read_mip_hi_hi_hi, read_mip_hi_hi_lo}; // @[CSR.scala:610:22]
wire [7:0] read_mip_hi = {read_mip_hi_hi, read_mip_hi_lo}; // @[CSR.scala:610:22]
wire [15:0] _read_mip_T = {read_mip_hi, read_mip_lo}; // @[CSR.scala:610:22]
wire [15:0] read_mip = _read_mip_T & 16'hAAA; // @[CSR.scala:610:{22,29}]
wire [63:0] _pending_interrupts_T = {48'h0, reg_mie[15:0] & read_mip}; // @[CSR.scala:495:20, :610:29, :614:56]
wire [63:0] pending_interrupts = _pending_interrupts_T; // @[CSR.scala:614:{44,56}]
wire [14:0] d_interrupts = {io_interrupts_debug_0, 14'h0}; // @[CSR.scala:377:7, :615:42]
wire _allow_wfi_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :906:61]
wire _allow_sfence_vma_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :907:60]
wire _allow_sret_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :910:62]
wire _allow_counter_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :912:42]
wire _allow_wfi_T_7 = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :906:61]
wire _allow_sfence_vma_T_4 = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :907:60]
wire _allow_sret_T_4 = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :910:62]
wire _allow_counter_T_17 = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :912:42]
wire _allow_wfi_T_14 = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :906:61]
wire _allow_sfence_vma_T_8 = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :907:60]
wire _allow_sret_T_8 = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :910:62]
wire _allow_counter_T_34 = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :912:42]
wire _m_interrupts_T = ~(reg_mstatus_prv[1]); // @[CSR.scala:395:28, :620:51]
wire _m_interrupts_T_1 = _m_interrupts_T | reg_mstatus_mie; // @[CSR.scala:395:28, :620:{51,62}]
wire _m_interrupts_T_2 = _m_interrupts_T_1; // @[CSR.scala:620:{31,62}]
wire [63:0] _m_interrupts_T_3 = ~pending_interrupts; // @[CSR.scala:614:44, :620:85]
wire [63:0] _m_interrupts_T_4 = _m_interrupts_T_3 | read_mideleg; // @[CSR.scala:498:14, :620:{85,105}]
wire [63:0] _m_interrupts_T_5 = ~_m_interrupts_T_4; // @[CSR.scala:620:{83,105}]
wire [63:0] m_interrupts = _m_interrupts_T_2 ? _m_interrupts_T_5 : 64'h0; // @[CSR.scala:620:{25,31,83}]
wire _GEN_2 = reg_mstatus_prv == 2'h0; // @[CSR.scala:395:28, :621:68]
wire _s_interrupts_T; // @[CSR.scala:621:68]
assign _s_interrupts_T = _GEN_2; // @[CSR.scala:621:68]
wire _vs_interrupts_T; // @[CSR.scala:622:70]
assign _vs_interrupts_T = _GEN_2; // @[CSR.scala:621:68, :622:70]
wire _io_fiom_T_2; // @[CSR.scala:631:82]
assign _io_fiom_T_2 = _GEN_2; // @[CSR.scala:621:68, :631:82]
wire _s_interrupts_T_1 = reg_mstatus_v | _s_interrupts_T; // @[CSR.scala:395:28, :621:{49,68}]
wire _GEN_3 = reg_mstatus_prv == 2'h1; // @[CSR.scala:395:28, :621:98]
wire _s_interrupts_T_2; // @[CSR.scala:621:98]
assign _s_interrupts_T_2 = _GEN_3; // @[CSR.scala:621:98]
wire _vs_interrupts_T_1; // @[CSR.scala:622:99]
assign _vs_interrupts_T_1 = _GEN_3; // @[CSR.scala:621:98, :622:99]
wire _csr_addr_legal_T_4; // @[CSR.scala:921:62]
assign _csr_addr_legal_T_4 = _GEN_3; // @[CSR.scala:621:98, :921:62]
wire _csr_addr_legal_T_13; // @[CSR.scala:921:62]
assign _csr_addr_legal_T_13 = _GEN_3; // @[CSR.scala:621:98, :921:62]
wire _csr_addr_legal_T_22; // @[CSR.scala:921:62]
assign _csr_addr_legal_T_22 = _GEN_3; // @[CSR.scala:621:98, :921:62]
wire _s_interrupts_T_3 = _s_interrupts_T_2 & reg_mstatus_sie; // @[CSR.scala:395:28, :621:{98,110}]
wire _s_interrupts_T_4 = _s_interrupts_T_1 | _s_interrupts_T_3; // @[CSR.scala:621:{49,78,110}]
wire _s_interrupts_T_5 = _s_interrupts_T_4; // @[CSR.scala:621:{31,78}]
wire [63:0] _s_interrupts_T_6 = pending_interrupts & read_mideleg; // @[CSR.scala:498:14, :614:44, :621:151]
wire [63:0] _s_interrupts_T_8 = _s_interrupts_T_6; // @[CSR.scala:621:{151,166}]
wire [63:0] s_interrupts = _s_interrupts_T_5 ? _s_interrupts_T_8 : 64'h0; // @[CSR.scala:621:{25,31,166}]
wire _vs_interrupts_T_2 = _vs_interrupts_T_1 & reg_vsstatus_sie; // @[CSR.scala:562:25, :622:{99,111}]
wire _vs_interrupts_T_3 = _vs_interrupts_T | _vs_interrupts_T_2; // @[CSR.scala:622:{70,80,111}]
wire _vs_interrupts_T_4 = reg_mstatus_v & _vs_interrupts_T_3; // @[CSR.scala:395:28, :622:{50,80}]
wire _vs_interrupts_T_5 = _vs_interrupts_T_4; // @[CSR.scala:622:{32,50}]
wire _any_T = d_interrupts[14]; // @[CSR.scala:615:42, :1637:76]
wire _which_T = d_interrupts[14]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_1 = d_interrupts[13]; // @[CSR.scala:615:42, :1637:76]
wire _which_T_1 = d_interrupts[13]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_2 = d_interrupts[12]; // @[CSR.scala:615:42, :1637:76]
wire _which_T_2 = d_interrupts[12]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_3 = d_interrupts[11]; // @[CSR.scala:615:42, :1637:76]
wire _which_T_3 = d_interrupts[11]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_4 = d_interrupts[3]; // @[CSR.scala:615:42, :1637:76]
wire _which_T_4 = d_interrupts[3]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_5 = d_interrupts[7]; // @[CSR.scala:615:42, :1637:76]
wire _which_T_5 = d_interrupts[7]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_6 = d_interrupts[9]; // @[CSR.scala:615:42, :1637:76]
wire _which_T_6 = d_interrupts[9]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_7 = d_interrupts[1]; // @[CSR.scala:615:42, :1637:76]
wire _which_T_7 = d_interrupts[1]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_8 = d_interrupts[5]; // @[CSR.scala:615:42, :1637:76]
wire _which_T_8 = d_interrupts[5]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_9 = d_interrupts[10]; // @[CSR.scala:615:42, :1637:76]
wire _which_T_9 = d_interrupts[10]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_10 = d_interrupts[2]; // @[CSR.scala:615:42, :1637:76]
wire _which_T_10 = d_interrupts[2]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_11 = d_interrupts[6]; // @[CSR.scala:615:42, :1637:76]
wire _which_T_11 = d_interrupts[6]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_12 = d_interrupts[8]; // @[CSR.scala:615:42, :1637:76]
wire _which_T_12 = d_interrupts[8]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_13 = d_interrupts[0]; // @[CSR.scala:615:42, :1637:76]
wire _which_T_13 = d_interrupts[0]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_14 = d_interrupts[4]; // @[CSR.scala:615:42, :1637:76]
wire _which_T_14 = d_interrupts[4]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_15 = m_interrupts[15]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_15 = m_interrupts[15]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_16 = m_interrupts[14]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_16 = m_interrupts[14]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_17 = m_interrupts[13]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_17 = m_interrupts[13]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_18 = m_interrupts[12]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_18 = m_interrupts[12]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_19 = m_interrupts[11]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_19 = m_interrupts[11]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_20 = m_interrupts[3]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_20 = m_interrupts[3]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_21 = m_interrupts[7]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_21 = m_interrupts[7]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_22 = m_interrupts[9]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_22 = m_interrupts[9]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_23 = m_interrupts[1]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_23 = m_interrupts[1]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_24 = m_interrupts[5]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_24 = m_interrupts[5]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_25 = m_interrupts[10]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_25 = m_interrupts[10]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_26 = m_interrupts[2]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_26 = m_interrupts[2]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_27 = m_interrupts[6]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_27 = m_interrupts[6]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_28 = m_interrupts[8]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_28 = m_interrupts[8]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_29 = m_interrupts[0]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_29 = m_interrupts[0]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_30 = m_interrupts[4]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_30 = m_interrupts[4]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_31 = s_interrupts[15]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_31 = s_interrupts[15]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_32 = s_interrupts[14]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_32 = s_interrupts[14]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_33 = s_interrupts[13]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_33 = s_interrupts[13]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_34 = s_interrupts[12]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_34 = s_interrupts[12]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_35 = s_interrupts[11]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_35 = s_interrupts[11]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_36 = s_interrupts[3]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_36 = s_interrupts[3]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_37 = s_interrupts[7]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_37 = s_interrupts[7]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_38 = s_interrupts[9]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_38 = s_interrupts[9]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_39 = s_interrupts[1]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_39 = s_interrupts[1]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_40 = s_interrupts[5]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_40 = s_interrupts[5]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_41 = s_interrupts[10]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_41 = s_interrupts[10]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_42 = s_interrupts[2]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_42 = s_interrupts[2]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_43 = s_interrupts[6]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_43 = s_interrupts[6]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_44 = s_interrupts[8]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_44 = s_interrupts[8]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_45 = s_interrupts[0]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_45 = s_interrupts[0]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_46 = s_interrupts[4]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_46 = s_interrupts[4]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_63 = _any_T | _any_T_1; // @[CSR.scala:1637:{76,90}]
wire _any_T_64 = _any_T_63 | _any_T_2; // @[CSR.scala:1637:{76,90}]
wire _any_T_65 = _any_T_64 | _any_T_3; // @[CSR.scala:1637:{76,90}]
wire _any_T_66 = _any_T_65 | _any_T_4; // @[CSR.scala:1637:{76,90}]
wire _any_T_67 = _any_T_66 | _any_T_5; // @[CSR.scala:1637:{76,90}]
wire _any_T_68 = _any_T_67 | _any_T_6; // @[CSR.scala:1637:{76,90}]
wire _any_T_69 = _any_T_68 | _any_T_7; // @[CSR.scala:1637:{76,90}]
wire _any_T_70 = _any_T_69 | _any_T_8; // @[CSR.scala:1637:{76,90}]
wire _any_T_71 = _any_T_70 | _any_T_9; // @[CSR.scala:1637:{76,90}]
wire _any_T_72 = _any_T_71 | _any_T_10; // @[CSR.scala:1637:{76,90}]
wire _any_T_73 = _any_T_72 | _any_T_11; // @[CSR.scala:1637:{76,90}]
wire _any_T_74 = _any_T_73 | _any_T_12; // @[CSR.scala:1637:{76,90}]
wire _any_T_75 = _any_T_74 | _any_T_13; // @[CSR.scala:1637:{76,90}]
wire _any_T_76 = _any_T_75 | _any_T_14; // @[CSR.scala:1637:{76,90}]
wire _any_T_77 = _any_T_76; // @[CSR.scala:1637:90]
wire _any_T_78 = _any_T_77 | _any_T_15; // @[CSR.scala:1637:{76,90}]
wire _any_T_79 = _any_T_78 | _any_T_16; // @[CSR.scala:1637:{76,90}]
wire _any_T_80 = _any_T_79 | _any_T_17; // @[CSR.scala:1637:{76,90}]
wire _any_T_81 = _any_T_80 | _any_T_18; // @[CSR.scala:1637:{76,90}]
wire _any_T_82 = _any_T_81 | _any_T_19; // @[CSR.scala:1637:{76,90}]
wire _any_T_83 = _any_T_82 | _any_T_20; // @[CSR.scala:1637:{76,90}]
wire _any_T_84 = _any_T_83 | _any_T_21; // @[CSR.scala:1637:{76,90}]
wire _any_T_85 = _any_T_84 | _any_T_22; // @[CSR.scala:1637:{76,90}]
wire _any_T_86 = _any_T_85 | _any_T_23; // @[CSR.scala:1637:{76,90}]
wire _any_T_87 = _any_T_86 | _any_T_24; // @[CSR.scala:1637:{76,90}]
wire _any_T_88 = _any_T_87 | _any_T_25; // @[CSR.scala:1637:{76,90}]
wire _any_T_89 = _any_T_88 | _any_T_26; // @[CSR.scala:1637:{76,90}]
wire _any_T_90 = _any_T_89 | _any_T_27; // @[CSR.scala:1637:{76,90}]
wire _any_T_91 = _any_T_90 | _any_T_28; // @[CSR.scala:1637:{76,90}]
wire _any_T_92 = _any_T_91 | _any_T_29; // @[CSR.scala:1637:{76,90}]
wire _any_T_93 = _any_T_92 | _any_T_30; // @[CSR.scala:1637:{76,90}]
wire _any_T_94 = _any_T_93 | _any_T_31; // @[CSR.scala:1637:{76,90}]
wire _any_T_95 = _any_T_94 | _any_T_32; // @[CSR.scala:1637:{76,90}]
wire _any_T_96 = _any_T_95 | _any_T_33; // @[CSR.scala:1637:{76,90}]
wire _any_T_97 = _any_T_96 | _any_T_34; // @[CSR.scala:1637:{76,90}]
wire _any_T_98 = _any_T_97 | _any_T_35; // @[CSR.scala:1637:{76,90}]
wire _any_T_99 = _any_T_98 | _any_T_36; // @[CSR.scala:1637:{76,90}]
wire _any_T_100 = _any_T_99 | _any_T_37; // @[CSR.scala:1637:{76,90}]
wire _any_T_101 = _any_T_100 | _any_T_38; // @[CSR.scala:1637:{76,90}]
wire _any_T_102 = _any_T_101 | _any_T_39; // @[CSR.scala:1637:{76,90}]
wire _any_T_103 = _any_T_102 | _any_T_40; // @[CSR.scala:1637:{76,90}]
wire _any_T_104 = _any_T_103 | _any_T_41; // @[CSR.scala:1637:{76,90}]
wire _any_T_105 = _any_T_104 | _any_T_42; // @[CSR.scala:1637:{76,90}]
wire _any_T_106 = _any_T_105 | _any_T_43; // @[CSR.scala:1637:{76,90}]
wire _any_T_107 = _any_T_106 | _any_T_44; // @[CSR.scala:1637:{76,90}]
wire _any_T_108 = _any_T_107 | _any_T_45; // @[CSR.scala:1637:{76,90}]
wire _any_T_109 = _any_T_108 | _any_T_46; // @[CSR.scala:1637:{76,90}]
wire _any_T_110 = _any_T_109; // @[CSR.scala:1637:90]
wire _any_T_111 = _any_T_110; // @[CSR.scala:1637:90]
wire _any_T_112 = _any_T_111; // @[CSR.scala:1637:90]
wire _any_T_113 = _any_T_112; // @[CSR.scala:1637:90]
wire _any_T_114 = _any_T_113; // @[CSR.scala:1637:90]
wire _any_T_115 = _any_T_114; // @[CSR.scala:1637:90]
wire _any_T_116 = _any_T_115; // @[CSR.scala:1637:90]
wire _any_T_117 = _any_T_116; // @[CSR.scala:1637:90]
wire _any_T_118 = _any_T_117; // @[CSR.scala:1637:90]
wire _any_T_119 = _any_T_118; // @[CSR.scala:1637:90]
wire _any_T_120 = _any_T_119; // @[CSR.scala:1637:90]
wire _any_T_121 = _any_T_120; // @[CSR.scala:1637:90]
wire _any_T_122 = _any_T_121; // @[CSR.scala:1637:90]
wire _any_T_123 = _any_T_122; // @[CSR.scala:1637:90]
wire _any_T_124 = _any_T_123; // @[CSR.scala:1637:90]
wire anyInterrupt = _any_T_124; // @[CSR.scala:1637:90]
wire [3:0] _which_T_79 = {1'h0, ~_which_T_45, 2'h0}; // @[Mux.scala:50:70]
wire [3:0] _which_T_80 = _which_T_44 ? 4'h8 : _which_T_79; // @[Mux.scala:50:70]
wire [3:0] _which_T_81 = _which_T_43 ? 4'h6 : _which_T_80; // @[Mux.scala:50:70]
wire [3:0] _which_T_82 = _which_T_42 ? 4'h2 : _which_T_81; // @[Mux.scala:50:70]
wire [3:0] _which_T_83 = _which_T_41 ? 4'hA : _which_T_82; // @[Mux.scala:50:70]
wire [3:0] _which_T_84 = _which_T_40 ? 4'h5 : _which_T_83; // @[Mux.scala:50:70]
wire [3:0] _which_T_85 = _which_T_39 ? 4'h1 : _which_T_84; // @[Mux.scala:50:70]
wire [3:0] _which_T_86 = _which_T_38 ? 4'h9 : _which_T_85; // @[Mux.scala:50:70]
wire [3:0] _which_T_87 = _which_T_37 ? 4'h7 : _which_T_86; // @[Mux.scala:50:70]
wire [3:0] _which_T_88 = _which_T_36 ? 4'h3 : _which_T_87; // @[Mux.scala:50:70]
wire [3:0] _which_T_89 = _which_T_35 ? 4'hB : _which_T_88; // @[Mux.scala:50:70]
wire [3:0] _which_T_90 = _which_T_34 ? 4'hC : _which_T_89; // @[Mux.scala:50:70]
wire [3:0] _which_T_91 = _which_T_33 ? 4'hD : _which_T_90; // @[Mux.scala:50:70]
wire [3:0] _which_T_92 = _which_T_32 ? 4'hE : _which_T_91; // @[Mux.scala:50:70]
wire [3:0] _which_T_93 = _which_T_31 ? 4'hF : _which_T_92; // @[Mux.scala:50:70]
wire [3:0] _which_T_94 = _which_T_30 ? 4'h4 : _which_T_93; // @[Mux.scala:50:70]
wire [3:0] _which_T_95 = _which_T_29 ? 4'h0 : _which_T_94; // @[Mux.scala:50:70]
wire [3:0] _which_T_96 = _which_T_28 ? 4'h8 : _which_T_95; // @[Mux.scala:50:70]
wire [3:0] _which_T_97 = _which_T_27 ? 4'h6 : _which_T_96; // @[Mux.scala:50:70]
wire [3:0] _which_T_98 = _which_T_26 ? 4'h2 : _which_T_97; // @[Mux.scala:50:70]
wire [3:0] _which_T_99 = _which_T_25 ? 4'hA : _which_T_98; // @[Mux.scala:50:70]
wire [3:0] _which_T_100 = _which_T_24 ? 4'h5 : _which_T_99; // @[Mux.scala:50:70]
wire [3:0] _which_T_101 = _which_T_23 ? 4'h1 : _which_T_100; // @[Mux.scala:50:70]
wire [3:0] _which_T_102 = _which_T_22 ? 4'h9 : _which_T_101; // @[Mux.scala:50:70]
wire [3:0] _which_T_103 = _which_T_21 ? 4'h7 : _which_T_102; // @[Mux.scala:50:70]
wire [3:0] _which_T_104 = _which_T_20 ? 4'h3 : _which_T_103; // @[Mux.scala:50:70]
wire [3:0] _which_T_105 = _which_T_19 ? 4'hB : _which_T_104; // @[Mux.scala:50:70]
wire [3:0] _which_T_106 = _which_T_18 ? 4'hC : _which_T_105; // @[Mux.scala:50:70]
wire [3:0] _which_T_107 = _which_T_17 ? 4'hD : _which_T_106; // @[Mux.scala:50:70]
wire [3:0] _which_T_108 = _which_T_16 ? 4'hE : _which_T_107; // @[Mux.scala:50:70]
wire [3:0] _which_T_109 = _which_T_15 ? 4'hF : _which_T_108; // @[Mux.scala:50:70]
wire [3:0] _which_T_110 = _which_T_109; // @[Mux.scala:50:70]
wire [3:0] _which_T_111 = _which_T_14 ? 4'h4 : _which_T_110; // @[Mux.scala:50:70]
wire [3:0] _which_T_112 = _which_T_13 ? 4'h0 : _which_T_111; // @[Mux.scala:50:70]
wire [3:0] _which_T_113 = _which_T_12 ? 4'h8 : _which_T_112; // @[Mux.scala:50:70]
wire [3:0] _which_T_114 = _which_T_11 ? 4'h6 : _which_T_113; // @[Mux.scala:50:70]
wire [3:0] _which_T_115 = _which_T_10 ? 4'h2 : _which_T_114; // @[Mux.scala:50:70]
wire [3:0] _which_T_116 = _which_T_9 ? 4'hA : _which_T_115; // @[Mux.scala:50:70]
wire [3:0] _which_T_117 = _which_T_8 ? 4'h5 : _which_T_116; // @[Mux.scala:50:70]
wire [3:0] _which_T_118 = _which_T_7 ? 4'h1 : _which_T_117; // @[Mux.scala:50:70]
wire [3:0] _which_T_119 = _which_T_6 ? 4'h9 : _which_T_118; // @[Mux.scala:50:70]
wire [3:0] _which_T_120 = _which_T_5 ? 4'h7 : _which_T_119; // @[Mux.scala:50:70]
wire [3:0] _which_T_121 = _which_T_4 ? 4'h3 : _which_T_120; // @[Mux.scala:50:70]
wire [3:0] _which_T_122 = _which_T_3 ? 4'hB : _which_T_121; // @[Mux.scala:50:70]
wire [3:0] _which_T_123 = _which_T_2 ? 4'hC : _which_T_122; // @[Mux.scala:50:70]
wire [3:0] _which_T_124 = _which_T_1 ? 4'hD : _which_T_123; // @[Mux.scala:50:70]
wire [3:0] whichInterrupt = _which_T ? 4'hE : _which_T_124; // @[Mux.scala:50:70]
wire [64:0] _interruptCause_T_3 = {61'h0, whichInterrupt} + 65'h8000000000000000; // @[Mux.scala:50:70]
assign interruptCause = _interruptCause_T_3[63:0]; // @[CSR.scala:625:63]
assign io_interrupt_cause_0 = interruptCause; // @[CSR.scala:377:7, :625:63]
wire _io_interrupt_T = ~io_singleStep_0; // @[CSR.scala:377:7, :626:36]
wire _io_interrupt_T_1 = anyInterrupt & _io_interrupt_T; // @[CSR.scala:626:{33,36}, :1637:90]
wire _io_interrupt_T_2 = _io_interrupt_T_1 | reg_singleStepped; // @[CSR.scala:486:30, :626:{33,51}]
wire _io_interrupt_T_3 = reg_debug | io_status_cease_0; // @[CSR.scala:377:7, :482:26, :626:88]
wire _io_interrupt_T_4 = ~_io_interrupt_T_3; // @[CSR.scala:626:{76,88}]
assign _io_interrupt_T_5 = _io_interrupt_T_2 & _io_interrupt_T_4; // @[CSR.scala:626:{51,73,76}]
assign io_interrupt_0 = _io_interrupt_T_5; // @[CSR.scala:377:7, :626:73]
wire _io_fiom_T = reg_mstatus_prv != 2'h3; // @[CSR.scala:395:28, :631:31]
wire _io_fiom_T_1 = _io_fiom_T & reg_menvcfg_fiom; // @[CSR.scala:525:28, :631:{31,41}]
wire _io_fiom_T_3 = _io_fiom_T_2 & reg_senvcfg_fiom; // @[CSR.scala:526:28, :631:{82,92}]
wire _io_fiom_T_4 = _io_fiom_T_1 | _io_fiom_T_3; // @[CSR.scala:631:{41,62,92}]
assign _io_fiom_T_6 = _io_fiom_T_4; // @[CSR.scala:631:{62,113}]
assign io_fiom = _io_fiom_T_6; // @[CSR.scala:377:7, :631:113]
assign io_pmp_0_cfg_l_0 = pmp_cfg_l; // @[PMP.scala:24:19]
assign io_pmp_0_cfg_a_0 = pmp_cfg_a; // @[PMP.scala:24:19]
assign io_pmp_0_cfg_x_0 = pmp_cfg_x; // @[PMP.scala:24:19]
assign io_pmp_0_cfg_w_0 = pmp_cfg_w; // @[PMP.scala:24:19]
assign io_pmp_0_cfg_r_0 = pmp_cfg_r; // @[PMP.scala:24:19]
assign io_pmp_0_addr_0 = pmp_addr; // @[PMP.scala:24:19]
assign io_pmp_0_mask_0 = pmp_mask; // @[PMP.scala:24:19]
wire _pmp_mask_base_T = pmp_cfg_a[0]; // @[PMP.scala:24:19, :57:31]
wire [30:0] _pmp_mask_base_T_1 = {pmp_addr, _pmp_mask_base_T}; // @[PMP.scala:24:19, :57:{19,31}]
wire [30:0] pmp_mask_base = _pmp_mask_base_T_1; // @[PMP.scala:57:{19,36}]
wire [31:0] _pmp_mask_T = {1'h0, pmp_mask_base} + 32'h1; // @[PMP.scala:57:36, :58:23]
wire [30:0] _pmp_mask_T_1 = _pmp_mask_T[30:0]; // @[PMP.scala:58:23]
wire [30:0] _pmp_mask_T_2 = ~_pmp_mask_T_1; // @[PMP.scala:58:{16,23}]
wire [30:0] _pmp_mask_T_3 = pmp_mask_base & _pmp_mask_T_2; // @[PMP.scala:57:36, :58:{14,16}]
wire [32:0] _pmp_mask_T_4 = {_pmp_mask_T_3, 2'h3}; // @[PMP.scala:58:{8,14}]
assign pmp_mask = _pmp_mask_T_4[31:0]; // @[PMP.scala:24:19, :27:14, :58:8]
assign io_pmp_1_cfg_l_0 = pmp_1_cfg_l; // @[PMP.scala:24:19]
assign io_pmp_1_cfg_a_0 = pmp_1_cfg_a; // @[PMP.scala:24:19]
assign io_pmp_1_cfg_x_0 = pmp_1_cfg_x; // @[PMP.scala:24:19]
assign io_pmp_1_cfg_w_0 = pmp_1_cfg_w; // @[PMP.scala:24:19]
assign io_pmp_1_cfg_r_0 = pmp_1_cfg_r; // @[PMP.scala:24:19]
assign io_pmp_1_addr_0 = pmp_1_addr; // @[PMP.scala:24:19]
assign io_pmp_1_mask_0 = pmp_1_mask; // @[PMP.scala:24:19]
wire _pmp_mask_base_T_3 = pmp_1_cfg_a[0]; // @[PMP.scala:24:19, :57:31]
wire [30:0] _pmp_mask_base_T_4 = {pmp_1_addr, _pmp_mask_base_T_3}; // @[PMP.scala:24:19, :57:{19,31}]
wire [30:0] pmp_mask_base_1 = _pmp_mask_base_T_4; // @[PMP.scala:57:{19,36}]
wire [31:0] _pmp_mask_T_5 = {1'h0, pmp_mask_base_1} + 32'h1; // @[PMP.scala:57:36, :58:23]
wire [30:0] _pmp_mask_T_6 = _pmp_mask_T_5[30:0]; // @[PMP.scala:58:23]
wire [30:0] _pmp_mask_T_7 = ~_pmp_mask_T_6; // @[PMP.scala:58:{16,23}]
wire [30:0] _pmp_mask_T_8 = pmp_mask_base_1 & _pmp_mask_T_7; // @[PMP.scala:57:36, :58:{14,16}]
wire [32:0] _pmp_mask_T_9 = {_pmp_mask_T_8, 2'h3}; // @[PMP.scala:58:{8,14}]
assign pmp_1_mask = _pmp_mask_T_9[31:0]; // @[PMP.scala:24:19, :27:14, :58:8]
assign io_pmp_2_cfg_l_0 = pmp_2_cfg_l; // @[PMP.scala:24:19]
assign io_pmp_2_cfg_a_0 = pmp_2_cfg_a; // @[PMP.scala:24:19]
assign io_pmp_2_cfg_x_0 = pmp_2_cfg_x; // @[PMP.scala:24:19]
assign io_pmp_2_cfg_w_0 = pmp_2_cfg_w; // @[PMP.scala:24:19]
assign io_pmp_2_cfg_r_0 = pmp_2_cfg_r; // @[PMP.scala:24:19]
assign io_pmp_2_addr_0 = pmp_2_addr; // @[PMP.scala:24:19]
assign io_pmp_2_mask_0 = pmp_2_mask; // @[PMP.scala:24:19]
wire _pmp_mask_base_T_6 = pmp_2_cfg_a[0]; // @[PMP.scala:24:19, :57:31]
wire [30:0] _pmp_mask_base_T_7 = {pmp_2_addr, _pmp_mask_base_T_6}; // @[PMP.scala:24:19, :57:{19,31}]
wire [30:0] pmp_mask_base_2 = _pmp_mask_base_T_7; // @[PMP.scala:57:{19,36}]
wire [31:0] _pmp_mask_T_10 = {1'h0, pmp_mask_base_2} + 32'h1; // @[PMP.scala:57:36, :58:23]
wire [30:0] _pmp_mask_T_11 = _pmp_mask_T_10[30:0]; // @[PMP.scala:58:23]
wire [30:0] _pmp_mask_T_12 = ~_pmp_mask_T_11; // @[PMP.scala:58:{16,23}]
wire [30:0] _pmp_mask_T_13 = pmp_mask_base_2 & _pmp_mask_T_12; // @[PMP.scala:57:36, :58:{14,16}]
wire [32:0] _pmp_mask_T_14 = {_pmp_mask_T_13, 2'h3}; // @[PMP.scala:58:{8,14}]
assign pmp_2_mask = _pmp_mask_T_14[31:0]; // @[PMP.scala:24:19, :27:14, :58:8]
assign io_pmp_3_cfg_l_0 = pmp_3_cfg_l; // @[PMP.scala:24:19]
assign io_pmp_3_cfg_a_0 = pmp_3_cfg_a; // @[PMP.scala:24:19]
assign io_pmp_3_cfg_x_0 = pmp_3_cfg_x; // @[PMP.scala:24:19]
assign io_pmp_3_cfg_w_0 = pmp_3_cfg_w; // @[PMP.scala:24:19]
assign io_pmp_3_cfg_r_0 = pmp_3_cfg_r; // @[PMP.scala:24:19]
assign io_pmp_3_addr_0 = pmp_3_addr; // @[PMP.scala:24:19]
assign io_pmp_3_mask_0 = pmp_3_mask; // @[PMP.scala:24:19]
wire _pmp_mask_base_T_9 = pmp_3_cfg_a[0]; // @[PMP.scala:24:19, :57:31]
wire [30:0] _pmp_mask_base_T_10 = {pmp_3_addr, _pmp_mask_base_T_9}; // @[PMP.scala:24:19, :57:{19,31}]
wire [30:0] pmp_mask_base_3 = _pmp_mask_base_T_10; // @[PMP.scala:57:{19,36}]
wire [31:0] _pmp_mask_T_15 = {1'h0, pmp_mask_base_3} + 32'h1; // @[PMP.scala:57:36, :58:23]
wire [30:0] _pmp_mask_T_16 = _pmp_mask_T_15[30:0]; // @[PMP.scala:58:23]
wire [30:0] _pmp_mask_T_17 = ~_pmp_mask_T_16; // @[PMP.scala:58:{16,23}]
wire [30:0] _pmp_mask_T_18 = pmp_mask_base_3 & _pmp_mask_T_17; // @[PMP.scala:57:36, :58:{14,16}]
wire [32:0] _pmp_mask_T_19 = {_pmp_mask_T_18, 2'h3}; // @[PMP.scala:58:{8,14}]
assign pmp_3_mask = _pmp_mask_T_19[31:0]; // @[PMP.scala:24:19, :27:14, :58:8]
assign io_pmp_4_cfg_l_0 = pmp_4_cfg_l; // @[PMP.scala:24:19]
assign io_pmp_4_cfg_a_0 = pmp_4_cfg_a; // @[PMP.scala:24:19]
assign io_pmp_4_cfg_x_0 = pmp_4_cfg_x; // @[PMP.scala:24:19]
assign io_pmp_4_cfg_w_0 = pmp_4_cfg_w; // @[PMP.scala:24:19]
assign io_pmp_4_cfg_r_0 = pmp_4_cfg_r; // @[PMP.scala:24:19]
assign io_pmp_4_addr_0 = pmp_4_addr; // @[PMP.scala:24:19]
assign io_pmp_4_mask_0 = pmp_4_mask; // @[PMP.scala:24:19]
wire _pmp_mask_base_T_12 = pmp_4_cfg_a[0]; // @[PMP.scala:24:19, :57:31]
wire [30:0] _pmp_mask_base_T_13 = {pmp_4_addr, _pmp_mask_base_T_12}; // @[PMP.scala:24:19, :57:{19,31}]
wire [30:0] pmp_mask_base_4 = _pmp_mask_base_T_13; // @[PMP.scala:57:{19,36}]
wire [31:0] _pmp_mask_T_20 = {1'h0, pmp_mask_base_4} + 32'h1; // @[PMP.scala:57:36, :58:23]
wire [30:0] _pmp_mask_T_21 = _pmp_mask_T_20[30:0]; // @[PMP.scala:58:23]
wire [30:0] _pmp_mask_T_22 = ~_pmp_mask_T_21; // @[PMP.scala:58:{16,23}]
wire [30:0] _pmp_mask_T_23 = pmp_mask_base_4 & _pmp_mask_T_22; // @[PMP.scala:57:36, :58:{14,16}]
wire [32:0] _pmp_mask_T_24 = {_pmp_mask_T_23, 2'h3}; // @[PMP.scala:58:{8,14}]
assign pmp_4_mask = _pmp_mask_T_24[31:0]; // @[PMP.scala:24:19, :27:14, :58:8]
assign io_pmp_5_cfg_l_0 = pmp_5_cfg_l; // @[PMP.scala:24:19]
assign io_pmp_5_cfg_a_0 = pmp_5_cfg_a; // @[PMP.scala:24:19]
assign io_pmp_5_cfg_x_0 = pmp_5_cfg_x; // @[PMP.scala:24:19]
assign io_pmp_5_cfg_w_0 = pmp_5_cfg_w; // @[PMP.scala:24:19]
assign io_pmp_5_cfg_r_0 = pmp_5_cfg_r; // @[PMP.scala:24:19]
assign io_pmp_5_addr_0 = pmp_5_addr; // @[PMP.scala:24:19]
assign io_pmp_5_mask_0 = pmp_5_mask; // @[PMP.scala:24:19]
wire _pmp_mask_base_T_15 = pmp_5_cfg_a[0]; // @[PMP.scala:24:19, :57:31]
wire [30:0] _pmp_mask_base_T_16 = {pmp_5_addr, _pmp_mask_base_T_15}; // @[PMP.scala:24:19, :57:{19,31}]
wire [30:0] pmp_mask_base_5 = _pmp_mask_base_T_16; // @[PMP.scala:57:{19,36}]
wire [31:0] _pmp_mask_T_25 = {1'h0, pmp_mask_base_5} + 32'h1; // @[PMP.scala:57:36, :58:23]
wire [30:0] _pmp_mask_T_26 = _pmp_mask_T_25[30:0]; // @[PMP.scala:58:23]
wire [30:0] _pmp_mask_T_27 = ~_pmp_mask_T_26; // @[PMP.scala:58:{16,23}]
wire [30:0] _pmp_mask_T_28 = pmp_mask_base_5 & _pmp_mask_T_27; // @[PMP.scala:57:36, :58:{14,16}]
wire [32:0] _pmp_mask_T_29 = {_pmp_mask_T_28, 2'h3}; // @[PMP.scala:58:{8,14}]
assign pmp_5_mask = _pmp_mask_T_29[31:0]; // @[PMP.scala:24:19, :27:14, :58:8]
assign io_pmp_6_cfg_l_0 = pmp_6_cfg_l; // @[PMP.scala:24:19]
assign io_pmp_6_cfg_a_0 = pmp_6_cfg_a; // @[PMP.scala:24:19]
assign io_pmp_6_cfg_x_0 = pmp_6_cfg_x; // @[PMP.scala:24:19]
assign io_pmp_6_cfg_w_0 = pmp_6_cfg_w; // @[PMP.scala:24:19]
assign io_pmp_6_cfg_r_0 = pmp_6_cfg_r; // @[PMP.scala:24:19]
assign io_pmp_6_addr_0 = pmp_6_addr; // @[PMP.scala:24:19]
assign io_pmp_6_mask_0 = pmp_6_mask; // @[PMP.scala:24:19]
wire _pmp_mask_base_T_18 = pmp_6_cfg_a[0]; // @[PMP.scala:24:19, :57:31]
wire [30:0] _pmp_mask_base_T_19 = {pmp_6_addr, _pmp_mask_base_T_18}; // @[PMP.scala:24:19, :57:{19,31}]
wire [30:0] pmp_mask_base_6 = _pmp_mask_base_T_19; // @[PMP.scala:57:{19,36}]
wire [31:0] _pmp_mask_T_30 = {1'h0, pmp_mask_base_6} + 32'h1; // @[PMP.scala:57:36, :58:23]
wire [30:0] _pmp_mask_T_31 = _pmp_mask_T_30[30:0]; // @[PMP.scala:58:23]
wire [30:0] _pmp_mask_T_32 = ~_pmp_mask_T_31; // @[PMP.scala:58:{16,23}]
wire [30:0] _pmp_mask_T_33 = pmp_mask_base_6 & _pmp_mask_T_32; // @[PMP.scala:57:36, :58:{14,16}]
wire [32:0] _pmp_mask_T_34 = {_pmp_mask_T_33, 2'h3}; // @[PMP.scala:58:{8,14}]
assign pmp_6_mask = _pmp_mask_T_34[31:0]; // @[PMP.scala:24:19, :27:14, :58:8]
assign io_pmp_7_cfg_l_0 = pmp_7_cfg_l; // @[PMP.scala:24:19]
assign io_pmp_7_cfg_a_0 = pmp_7_cfg_a; // @[PMP.scala:24:19]
assign io_pmp_7_cfg_x_0 = pmp_7_cfg_x; // @[PMP.scala:24:19]
assign io_pmp_7_cfg_w_0 = pmp_7_cfg_w; // @[PMP.scala:24:19]
assign io_pmp_7_cfg_r_0 = pmp_7_cfg_r; // @[PMP.scala:24:19]
assign io_pmp_7_addr_0 = pmp_7_addr; // @[PMP.scala:24:19]
assign io_pmp_7_mask_0 = pmp_7_mask; // @[PMP.scala:24:19]
wire _pmp_mask_base_T_21 = pmp_7_cfg_a[0]; // @[PMP.scala:24:19, :57:31]
wire [30:0] _pmp_mask_base_T_22 = {pmp_7_addr, _pmp_mask_base_T_21}; // @[PMP.scala:24:19, :57:{19,31}]
wire [30:0] pmp_mask_base_7 = _pmp_mask_base_T_22; // @[PMP.scala:57:{19,36}]
wire [31:0] _pmp_mask_T_35 = {1'h0, pmp_mask_base_7} + 32'h1; // @[PMP.scala:57:36, :58:23]
wire [30:0] _pmp_mask_T_36 = _pmp_mask_T_35[30:0]; // @[PMP.scala:58:23]
wire [30:0] _pmp_mask_T_37 = ~_pmp_mask_T_36; // @[PMP.scala:58:{16,23}]
wire [30:0] _pmp_mask_T_38 = pmp_mask_base_7 & _pmp_mask_T_37; // @[PMP.scala:57:36, :58:{14,16}]
wire [32:0] _pmp_mask_T_39 = {_pmp_mask_T_38, 2'h3}; // @[PMP.scala:58:{8,14}]
assign pmp_7_mask = _pmp_mask_T_39[31:0]; // @[PMP.scala:24:19, :27:14, :58:8]
wire [1:0] read_mstatus_lo_lo_lo_lo = {io_status_sie_0, 1'h0}; // @[CSR.scala:377:7, :649:32]
wire [1:0] read_mstatus_lo_lo_lo_hi = {io_status_mie_0, 1'h0}; // @[CSR.scala:377:7, :649:32]
wire [3:0] read_mstatus_lo_lo_lo = {read_mstatus_lo_lo_lo_hi, read_mstatus_lo_lo_lo_lo}; // @[CSR.scala:649:32]
wire [1:0] read_mstatus_lo_lo_hi_lo = {io_status_spie_0, 1'h0}; // @[CSR.scala:377:7, :649:32]
wire [1:0] read_mstatus_lo_lo_hi_hi_hi = {io_status_spp_0, io_status_mpie_0}; // @[CSR.scala:377:7, :649:32]
wire [2:0] read_mstatus_lo_lo_hi_hi = {read_mstatus_lo_lo_hi_hi_hi, 1'h0}; // @[CSR.scala:649:32]
wire [4:0] read_mstatus_lo_lo_hi = {read_mstatus_lo_lo_hi_hi, read_mstatus_lo_lo_hi_lo}; // @[CSR.scala:649:32]
wire [8:0] read_mstatus_lo_lo = {read_mstatus_lo_lo_hi, read_mstatus_lo_lo_lo}; // @[CSR.scala:649:32]
wire [3:0] read_mstatus_lo_hi_lo_lo = {io_status_mpp_0, 2'h0}; // @[CSR.scala:377:7, :649:32]
wire [3:0] read_mstatus_lo_hi_lo_hi = {2'h0, io_status_fs_0}; // @[CSR.scala:377:7, :649:32]
wire [7:0] read_mstatus_lo_hi_lo = {read_mstatus_lo_hi_lo_hi, read_mstatus_lo_hi_lo_lo}; // @[CSR.scala:649:32]
wire [1:0] read_mstatus_lo_hi_hi_lo = {io_status_sum_0, io_status_mprv_0}; // @[CSR.scala:377:7, :649:32]
wire [1:0] read_mstatus_lo_hi_hi_hi_hi = {io_status_tw_0, io_status_tvm_0}; // @[CSR.scala:377:7, :649:32]
wire [2:0] read_mstatus_lo_hi_hi_hi = {read_mstatus_lo_hi_hi_hi_hi, io_status_mxr_0}; // @[CSR.scala:377:7, :649:32]
wire [4:0] read_mstatus_lo_hi_hi = {read_mstatus_lo_hi_hi_hi, read_mstatus_lo_hi_hi_lo}; // @[CSR.scala:649:32]
wire [12:0] read_mstatus_lo_hi = {read_mstatus_lo_hi_hi, read_mstatus_lo_hi_lo}; // @[CSR.scala:649:32]
wire [21:0] read_mstatus_lo = {read_mstatus_lo_hi, read_mstatus_lo_lo}; // @[CSR.scala:649:32]
wire [8:0] read_mstatus_hi_lo_lo_lo = {8'h0, io_status_tsr_0}; // @[CSR.scala:377:7, :649:32]
wire [11:0] read_mstatus_hi_lo_lo = {3'h4, read_mstatus_hi_lo_lo_lo}; // @[CSR.scala:649:32]
wire [1:0] read_mstatus_hi_lo_hi_hi_hi = {io_status_mpv_0, io_status_gva_0}; // @[CSR.scala:377:7, :649:32]
wire [2:0] read_mstatus_hi_lo_hi_hi = {read_mstatus_hi_lo_hi_hi_hi, 1'h0}; // @[CSR.scala:649:32]
wire [5:0] read_mstatus_hi_lo_hi = {read_mstatus_hi_lo_hi_hi, 3'h2}; // @[CSR.scala:649:32]
wire [17:0] read_mstatus_hi_lo = {read_mstatus_hi_lo_hi, read_mstatus_hi_lo_lo}; // @[CSR.scala:649:32]
wire [23:0] read_mstatus_hi_hi_lo_lo = {io_status_sd_0, 23'h0}; // @[CSR.scala:377:7, :649:32]
wire [2:0] read_mstatus_hi_hi_lo_hi_hi = {io_status_dv_0, io_status_prv_0}; // @[CSR.scala:377:7, :649:32]
wire [3:0] read_mstatus_hi_hi_lo_hi = {read_mstatus_hi_hi_lo_hi_hi, io_status_v_0}; // @[CSR.scala:377:7, :649:32]
wire [27:0] read_mstatus_hi_hi_lo = {read_mstatus_hi_hi_lo_hi, read_mstatus_hi_hi_lo_lo}; // @[CSR.scala:649:32]
wire [33:0] read_mstatus_hi_hi_hi_lo = {32'h14112D, io_status_dprv_0}; // @[CSR.scala:377:7, :649:32]
wire [1:0] read_mstatus_hi_hi_hi_hi_hi = {io_status_debug_0, io_status_cease_0}; // @[CSR.scala:377:7, :649:32]
wire [2:0] read_mstatus_hi_hi_hi_hi = {read_mstatus_hi_hi_hi_hi_hi, io_status_wfi_0}; // @[CSR.scala:377:7, :649:32]
wire [36:0] read_mstatus_hi_hi_hi = {read_mstatus_hi_hi_hi_hi, read_mstatus_hi_hi_hi_lo}; // @[CSR.scala:649:32]
wire [64:0] read_mstatus_hi_hi = {read_mstatus_hi_hi_hi, read_mstatus_hi_hi_lo}; // @[CSR.scala:649:32]
wire [82:0] read_mstatus_hi = {read_mstatus_hi_hi, read_mstatus_hi_lo}; // @[CSR.scala:649:32]
wire [104:0] _read_mstatus_T = {read_mstatus_hi, read_mstatus_lo}; // @[CSR.scala:649:32]
wire [63:0] read_mstatus = _read_mstatus_T[63:0]; // @[package.scala:163:13]
wire _read_mtvec_T = reg_mtvec[0]; // @[CSR.scala:512:31, :1666:41]
wire [7:0] _read_mtvec_T_1 = _read_mtvec_T ? 8'hFE : 8'h2; // @[CSR.scala:1666:{39,41}]
wire [31:0] _read_mtvec_T_3 = {24'h0, _read_mtvec_T_1}; // @[package.scala:174:41]
wire [31:0] _read_mtvec_T_4 = ~_read_mtvec_T_3; // @[package.scala:174:{37,41}]
wire [31:0] _read_mtvec_T_5 = reg_mtvec & _read_mtvec_T_4; // @[package.scala:174:{35,37}]
wire [63:0] read_mtvec = {32'h0, _read_mtvec_T_5}; // @[package.scala:138:15, :174:35]
wire _read_stvec_T = reg_stvec[0]; // @[CSR.scala:573:22, :1666:41]
wire [7:0] _read_stvec_T_1 = _read_stvec_T ? 8'hFE : 8'h2; // @[CSR.scala:1666:{39,41}]
wire [38:0] _read_stvec_T_3 = {31'h0, _read_stvec_T_1}; // @[package.scala:174:41]
wire [38:0] _read_stvec_T_4 = ~_read_stvec_T_3; // @[package.scala:174:{37,41}]
wire [38:0] _read_stvec_T_5 = reg_stvec & _read_stvec_T_4; // @[package.scala:174:{35,37}]
wire _read_stvec_T_6 = _read_stvec_T_5[38]; // @[package.scala:132:38, :174:35]
wire [24:0] _read_stvec_T_7 = {25{_read_stvec_T_6}}; // @[package.scala:132:{20,38}]
wire [63:0] read_stvec = {_read_stvec_T_7, _read_stvec_T_5}; // @[package.scala:132:{15,20}, :174:35]
wire [39:0] _read_mapping_T_2 = ~reg_mepc; // @[CSR.scala:505:21, :1665:28]
wire [39:0] _read_mapping_T_5 = {_read_mapping_T_2[39:2], _read_mapping_T_2[1:0] | 2'h1}; // @[CSR.scala:1665:{28,31}]
wire [39:0] _read_mapping_T_6 = ~_read_mapping_T_5; // @[CSR.scala:1665:{26,31}]
wire _read_mapping_T_7 = _read_mapping_T_6[39]; // @[package.scala:132:38]
wire [23:0] _read_mapping_T_8 = {24{_read_mapping_T_7}}; // @[package.scala:132:{20,38}]
wire [63:0] read_mapping_10_2 = {_read_mapping_T_8, _read_mapping_T_6}; // @[package.scala:132:{15,20}]
wire _read_mapping_T_9 = reg_mtval[39]; // @[package.scala:132:38]
wire [23:0] _read_mapping_T_10 = {24{_read_mapping_T_9}}; // @[package.scala:132:{20,38}]
wire [63:0] read_mapping_11_2 = {_read_mapping_T_10, reg_mtval}; // @[package.scala:132:{15,20}]
wire [2:0] debug_csrs_lo_lo_hi = {2'h0, reg_dcsr_step}; // @[CSR.scala:403:25, :670:27]
wire [4:0] debug_csrs_lo_lo = {debug_csrs_lo_lo_hi, reg_dcsr_prv}; // @[CSR.scala:403:25, :670:27]
wire [3:0] debug_csrs_lo_hi_lo = {reg_dcsr_cause, reg_dcsr_v}; // @[CSR.scala:403:25, :670:27]
wire [5:0] debug_csrs_lo_hi = {2'h0, debug_csrs_lo_hi_lo}; // @[CSR.scala:670:27]
wire [10:0] debug_csrs_lo = {debug_csrs_lo_hi, debug_csrs_lo_lo}; // @[CSR.scala:670:27]
wire [1:0] debug_csrs_hi_lo_lo = {reg_dcsr_ebreaku, 1'h0}; // @[CSR.scala:403:25, :670:27]
wire [1:0] debug_csrs_hi_lo_hi = {1'h0, reg_dcsr_ebreaks}; // @[CSR.scala:403:25, :670:27]
wire [3:0] debug_csrs_hi_lo = {debug_csrs_hi_lo_hi, debug_csrs_hi_lo_lo}; // @[CSR.scala:670:27]
wire [12:0] debug_csrs_hi_hi_lo = {12'h0, reg_dcsr_ebreakm}; // @[CSR.scala:403:25, :670:27]
wire [16:0] debug_csrs_hi_hi = {4'h4, debug_csrs_hi_hi_lo}; // @[CSR.scala:670:27]
wire [20:0] debug_csrs_hi = {debug_csrs_hi_hi, debug_csrs_hi_lo}; // @[CSR.scala:670:27]
wire [31:0] debug_csrs_0_2 = {debug_csrs_hi, debug_csrs_lo}; // @[CSR.scala:670:27]
wire [39:0] _debug_csrs_T = ~reg_dpc; // @[CSR.scala:483:20, :1665:28]
wire [39:0] _debug_csrs_T_3 = {_debug_csrs_T[39:2], _debug_csrs_T[1:0] | 2'h1}; // @[CSR.scala:1665:{28,31}]
wire [39:0] _debug_csrs_T_4 = ~_debug_csrs_T_3; // @[CSR.scala:1665:{26,31}]
wire _debug_csrs_T_5 = _debug_csrs_T_4[39]; // @[package.scala:132:38]
wire [23:0] _debug_csrs_T_6 = {24{_debug_csrs_T_5}}; // @[package.scala:132:{20,38}]
wire [63:0] debug_csrs_1_2 = {_debug_csrs_T_6, _debug_csrs_T_4}; // @[package.scala:132:{15,20}]
wire [7:0] read_fcsr = {reg_frm, reg_fflags}; // @[CSR.scala:577:23, :578:20, :689:22]
wire [3:0] lo_lo_4 = {3'h0, reg_menvcfg_fiom}; // @[CSR.scala:525:28, :742:49]
wire [6:0] lo_4 = {3'h0, lo_lo_4}; // @[CSR.scala:742:49]
wire [63:0] sie_mask = {48'h0, read_mideleg[15:0] & 16'hEFFF}; // @[CSR.scala:498:14, :750:18]
wire [63:0] read_sie = reg_mie & sie_mask; // @[CSR.scala:495:20, :750:18, :753:28]
wire [63:0] read_sip = {48'h0, sie_mask[15:0] & read_mip}; // @[CSR.scala:610:29, :750:18, :754:29]
wire [1:0] lo_lo_lo_lo = {read_sstatus_sie, 1'h0}; // @[CSR.scala:755:35, :768:51]
wire [3:0] lo_lo_lo_4 = {2'h0, lo_lo_lo_lo}; // @[CSR.scala:768:51]
wire [1:0] lo_lo_hi_lo = {read_sstatus_spie, 1'h0}; // @[CSR.scala:755:35, :768:51]
wire [1:0] lo_lo_hi_hi_hi = {read_sstatus_spp, 1'h0}; // @[CSR.scala:755:35, :768:51]
wire [2:0] lo_lo_hi_hi = {lo_lo_hi_hi_hi, 1'h0}; // @[CSR.scala:768:51]
wire [4:0] lo_lo_hi_4 = {lo_lo_hi_hi, lo_lo_hi_lo}; // @[CSR.scala:768:51]
wire [8:0] lo_lo_5 = {lo_lo_hi_4, lo_lo_lo_4}; // @[CSR.scala:768:51]
wire [3:0] lo_hi_lo_hi = {2'h0, read_sstatus_fs}; // @[CSR.scala:755:35, :768:51]
wire [7:0] lo_hi_lo_4 = {lo_hi_lo_hi, 4'h0}; // @[CSR.scala:768:51]
wire [1:0] lo_hi_hi_lo = {read_sstatus_sum, 1'h0}; // @[CSR.scala:755:35, :768:51]
wire [2:0] lo_hi_hi_hi = {2'h0, read_sstatus_mxr}; // @[CSR.scala:755:35, :768:51]
wire [4:0] lo_hi_hi_4 = {lo_hi_hi_hi, lo_hi_hi_lo}; // @[CSR.scala:768:51]
wire [12:0] lo_hi_5 = {lo_hi_hi_4, lo_hi_lo_4}; // @[CSR.scala:768:51]
wire [21:0] lo_5 = {lo_hi_5, lo_lo_5}; // @[CSR.scala:768:51]
wire [23:0] hi_hi_lo_lo = {read_sstatus_sd, 23'h0}; // @[CSR.scala:755:35, :768:51]
wire [27:0] hi_hi_lo_4 = {4'h0, hi_hi_lo_lo}; // @[CSR.scala:768:51]
wire [64:0] hi_hi_5 = {37'h0, hi_hi_lo_4}; // @[CSR.scala:768:51]
wire [82:0] hi_7 = {hi_hi_5, 18'h800}; // @[CSR.scala:768:51]
wire [19:0] hi_8 = {reg_satp_mode, 16'h0}; // @[CSR.scala:574:21, :774:43]
wire [39:0] _io_evec_T = ~reg_sepc; // @[CSR.scala:569:21, :1665:28]
wire [39:0] _T_34 = ~{_io_evec_T[39:2], _io_evec_T[1:0] | 2'h1}; // @[CSR.scala:1665:{26,28,31}]
wire [3:0] lo_lo_6 = {3'h0, reg_senvcfg_fiom}; // @[CSR.scala:526:28, :780:49]
wire [6:0] lo_6 = {3'h0, lo_lo_6}; // @[CSR.scala:780:49]
wire [1:0] lo_hi_7 = {reg_pmp_0_cfg_x, reg_pmp_0_cfg_w}; // @[package.scala:45:36]
wire [2:0] lo_7 = {lo_hi_7, reg_pmp_0_cfg_r}; // @[package.scala:45:36]
wire [2:0] hi_hi_7 = {reg_pmp_0_cfg_l, 2'h0}; // @[package.scala:45:36]
wire [4:0] hi_10 = {hi_hi_7, reg_pmp_0_cfg_a}; // @[package.scala:45:36]
wire [1:0] lo_hi_8 = {reg_pmp_1_cfg_x, reg_pmp_1_cfg_w}; // @[package.scala:45:36]
wire [2:0] lo_8 = {lo_hi_8, reg_pmp_1_cfg_r}; // @[package.scala:45:36]
wire [2:0] hi_hi_8 = {reg_pmp_1_cfg_l, 2'h0}; // @[package.scala:45:36]
wire [4:0] hi_11 = {hi_hi_8, reg_pmp_1_cfg_a}; // @[package.scala:45:36]
wire [1:0] lo_hi_9 = {reg_pmp_2_cfg_x, reg_pmp_2_cfg_w}; // @[package.scala:45:36]
wire [2:0] lo_9 = {lo_hi_9, reg_pmp_2_cfg_r}; // @[package.scala:45:36]
wire [2:0] hi_hi_9 = {reg_pmp_2_cfg_l, 2'h0}; // @[package.scala:45:36]
wire [4:0] hi_12 = {hi_hi_9, reg_pmp_2_cfg_a}; // @[package.scala:45:36]
wire [1:0] lo_hi_10 = {reg_pmp_3_cfg_x, reg_pmp_3_cfg_w}; // @[package.scala:45:36]
wire [2:0] lo_10 = {lo_hi_10, reg_pmp_3_cfg_r}; // @[package.scala:45:36]
wire [2:0] hi_hi_10 = {reg_pmp_3_cfg_l, 2'h0}; // @[package.scala:45:36]
wire [4:0] hi_13 = {hi_hi_10, reg_pmp_3_cfg_a}; // @[package.scala:45:36]
wire [1:0] lo_hi_11 = {reg_pmp_4_cfg_x, reg_pmp_4_cfg_w}; // @[package.scala:45:36]
wire [2:0] lo_11 = {lo_hi_11, reg_pmp_4_cfg_r}; // @[package.scala:45:36]
wire [2:0] hi_hi_11 = {reg_pmp_4_cfg_l, 2'h0}; // @[package.scala:45:36]
wire [4:0] hi_14 = {hi_hi_11, reg_pmp_4_cfg_a}; // @[package.scala:45:36]
wire [1:0] lo_hi_12 = {reg_pmp_5_cfg_x, reg_pmp_5_cfg_w}; // @[package.scala:45:36]
wire [2:0] lo_12 = {lo_hi_12, reg_pmp_5_cfg_r}; // @[package.scala:45:36]
wire [2:0] hi_hi_12 = {reg_pmp_5_cfg_l, 2'h0}; // @[package.scala:45:36]
wire [4:0] hi_15 = {hi_hi_12, reg_pmp_5_cfg_a}; // @[package.scala:45:36]
wire [1:0] lo_hi_13 = {reg_pmp_6_cfg_x, reg_pmp_6_cfg_w}; // @[package.scala:45:36]
wire [2:0] lo_13 = {lo_hi_13, reg_pmp_6_cfg_r}; // @[package.scala:45:36]
wire [2:0] hi_hi_13 = {reg_pmp_6_cfg_l, 2'h0}; // @[package.scala:45:36]
wire [4:0] hi_16 = {hi_hi_13, reg_pmp_6_cfg_a}; // @[package.scala:45:36]
wire [1:0] lo_hi_14 = {reg_pmp_7_cfg_x, reg_pmp_7_cfg_w}; // @[package.scala:45:36]
wire [2:0] lo_14 = {lo_hi_14, reg_pmp_7_cfg_r}; // @[package.scala:45:36]
wire [2:0] hi_hi_14 = {reg_pmp_7_cfg_l, 2'h0}; // @[package.scala:45:36]
wire [4:0] hi_17 = {hi_hi_14, reg_pmp_7_cfg_a}; // @[package.scala:45:36]
wire [15:0] lo_lo_7 = {hi_11, lo_8, hi_10, lo_7}; // @[package.scala:45:{27,36}]
wire [15:0] lo_hi_15 = {hi_13, lo_10, hi_12, lo_9}; // @[package.scala:45:{27,36}]
wire [31:0] lo_15 = {lo_hi_15, lo_lo_7}; // @[package.scala:45:27]
wire [15:0] hi_lo_7 = {hi_15, lo_12, hi_14, lo_11}; // @[package.scala:45:{27,36}]
wire [15:0] hi_hi_15 = {hi_17, lo_14, hi_16, lo_13}; // @[package.scala:45:{27,36}]
wire [31:0] hi_18 = {hi_hi_15, hi_lo_7}; // @[package.scala:45:27]
reg [63:0] reg_custom_0; // @[CSR.scala:798:43]
assign io_customCSRs_0_value_0 = reg_custom_0; // @[CSR.scala:377:7, :798:43]
wire _reg_custom_read_T = |io_rw_cmd_0; // @[CSR.scala:377:7, :799:26]
wire _reg_custom_read_T_1 = io_rw_addr_0 == 12'h800; // @[CSR.scala:377:7, :799:50]
assign reg_custom_read = _reg_custom_read_T & _reg_custom_read_T_1; // @[CSR.scala:799:{26,36,50}]
assign io_customCSRs_0_ren_0 = reg_custom_read; // @[CSR.scala:377:7, :799:36]
reg [63:0] reg_custom_1; // @[CSR.scala:798:43]
assign io_customCSRs_1_value_0 = reg_custom_1; // @[CSR.scala:377:7, :798:43]
wire _reg_custom_read_T_2 = |io_rw_cmd_0; // @[CSR.scala:377:7, :799:26]
wire _reg_custom_read_T_3 = io_rw_addr_0 == 12'h808; // @[CSR.scala:377:7, :799:50]
assign reg_custom_read_1 = _reg_custom_read_T_2 & _reg_custom_read_T_3; // @[CSR.scala:799:{26,36,50}]
assign io_customCSRs_1_ren_0 = reg_custom_read_1; // @[CSR.scala:377:7, :799:36]
reg [63:0] reg_custom_2; // @[CSR.scala:798:43]
assign io_customCSRs_2_value_0 = reg_custom_2; // @[CSR.scala:377:7, :798:43]
wire _reg_custom_read_T_4 = |io_rw_cmd_0; // @[CSR.scala:377:7, :799:26]
wire _reg_custom_read_T_5 = io_rw_addr_0 == 12'h7C1; // @[CSR.scala:377:7, :799:50]
assign reg_custom_read_2 = _reg_custom_read_T_4 & _reg_custom_read_T_5; // @[CSR.scala:799:{26,36,50}]
assign io_customCSRs_2_ren_0 = reg_custom_read_2; // @[CSR.scala:377:7, :799:36]
reg [63:0] reg_custom_3; // @[CSR.scala:798:43]
assign io_customCSRs_3_value_0 = reg_custom_3; // @[CSR.scala:377:7, :798:43]
wire [63:0] _reg_custom_3_T_2 = reg_custom_3; // @[CSR.scala:798:43, :1506:38]
wire [63:0] _reg_custom_3_T_6 = reg_custom_3; // @[CSR.scala:798:43, :1531:39]
wire _reg_custom_read_T_6 = |io_rw_cmd_0; // @[CSR.scala:377:7, :799:26]
wire _reg_custom_read_T_7 = io_rw_addr_0 == 12'hF12; // @[CSR.scala:377:7, :799:50]
assign reg_custom_read_3 = _reg_custom_read_T_6 & _reg_custom_read_T_7; // @[CSR.scala:799:{26,36,50}]
assign io_customCSRs_3_ren_0 = reg_custom_read_3; // @[CSR.scala:377:7, :799:36]
wire [12:0] decoded_addr_addr = {io_status_v_0, io_rw_addr_0}; // @[CSR.scala:377:7, :851:19]
wire [11:0] decoded_addr_decoded_decoded_plaInput; // @[pla.scala:77:22]
wire [11:0] decoded_addr_decoded_decoded_invInputs = ~decoded_addr_decoded_decoded_plaInput; // @[pla.scala:77:22, :78:21]
wire [151:0] decoded_addr_decoded_decoded_invMatrixOutputs; // @[pla.scala:120:37]
wire [151:0] decoded_addr_decoded_decoded; // @[pla.scala:81:23]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_4 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_5 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_8 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_9 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_14 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_15 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_18 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_19 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_22 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_24 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_25 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_28 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_29 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_32 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_33 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_36 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_37 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_40 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_41 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_44 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_45 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_48 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_49 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_52 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_53 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_57 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_59 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_60 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_63 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_64 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_67 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_68 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_71 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_72 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_75 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_76 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_79 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_80 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_85 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_88 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_89 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_92 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_93 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_96 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_97 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_100 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_101 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_104 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_105 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_108 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_109 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_112 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_113 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_116 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_119 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_120 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_123 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_124 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_127 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_128 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_131 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_132 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_135 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_136 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_139 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_140 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_143 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_144 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_147 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_150 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_151 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_1 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_2 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_3 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_8 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_9 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_10 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_11 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_14 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_15 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_16 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_17 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_22 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_23 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_28 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_29 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_30 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_31 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_36 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_37 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_38 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_39 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_44 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_45 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_46 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_47 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_52 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_53 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_54 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_55 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_57 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_58 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_59 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_60 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_61 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_62 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_67 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_68 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_69 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_70 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_75 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_76 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_77 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_78 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_79 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_80 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_81 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_85 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_86 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_87 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_92 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_93 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_94 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_95 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_100 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_101 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_102 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_103 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_108 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_109 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_110 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_111 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_116 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_117 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_118 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_123 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_124 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_125 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_126 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_131 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_132 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_133 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_134 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_139 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_140 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_141 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_142 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_147 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_148 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_149 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_1 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_2 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_3 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_4 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_5 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_6 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_8 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_9 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_10 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_11 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_12 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_14 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_15 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_16 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_17 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_18 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_19 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_20 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_22 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_23 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_24 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_25 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_26 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_27 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_36 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_37 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_38 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_39 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_40 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_41 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_42 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_43 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_52 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_53 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_54 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_55 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_56 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_57 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_58 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_59 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_60 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_61 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_62 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_63 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_64 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_65 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_66 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_75 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_76 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_77 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_78 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_79 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_80 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_81 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_83 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_85 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_86 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_87 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_88 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_89 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_90 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_91 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_100 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_101 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_102 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_103 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_104 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_105 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_106 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_107 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_116 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_117 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_118 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_119 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_120 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_121 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_122 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_131 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_132 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_133 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_134 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_135 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_136 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_137 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_138 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_147 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_148 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_149 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_150 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_151 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_1 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_2 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_3 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_4 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_5 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_6 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_7 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_8 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_9 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_10 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_11 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_12 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_14 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_15 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_16 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_17 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_18 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_19 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_20 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_21 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_22 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_23 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_24 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_25 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_26 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_27 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_28 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_29 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_30 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_31 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_32 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_33 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_34 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_35 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_52 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_53 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_54 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_55 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_56 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_57 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_58 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_75 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_76 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_77 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_78 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_83 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_84 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_85 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_86 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_87 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_88 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_89 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_90 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_91 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_92 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_93 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_94 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_95 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_96 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_97 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_98 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_99 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_116 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_117 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_118 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_119 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_120 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_121 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_122 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_123 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_124 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_125 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_126 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_127 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_128 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_129 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_130 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_1 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_2 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_3 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_4 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_5 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_6 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_7 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_8 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_9 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_10 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_11 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_12 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_13 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_14 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_15 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_16 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_17 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_18 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_20 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_21 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_51 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_52 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_53 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_54 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_56 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_83 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_84 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_85 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_85 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_86 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_87 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_88 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_89 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_90 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_91 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_92 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_93 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_94 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_95 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_96 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_97 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_98 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_99 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_100 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_101 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_102 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_103 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_104 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_105 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_106 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_107 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_108 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_109 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_110 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_111 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_112 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_113 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_114 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_116 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_116 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_117 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_118 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_119 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_120 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_121 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_122 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_123 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_124 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_125 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_126 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_127 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_128 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_129 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_130 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_131 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_132 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_133 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_134 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_135 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_136 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_137 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_138 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_139 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_140 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_141 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_142 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_143 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_144 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_145 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_147 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_147 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_148 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_149 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_150 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_1 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_2 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_3 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_4 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_5 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_6 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_7 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_13 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_14 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_15 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_16 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_17 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_18 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_19 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_21 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_21 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_22 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_23 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_24 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_25 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_26 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_27 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_28 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_29 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_30 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_31 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_32 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_33 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_34 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_35 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_36 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_37 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_38 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_39 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_40 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_41 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_42 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_43 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_44 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_45 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_46 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_47 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_48 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_49 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_50 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_56 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_57 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_58 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_59 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_60 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_61 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_62 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_63 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_64 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_65 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_66 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_67 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_68 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_69 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_70 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_71 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_72 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_73 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_74 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_75 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_76 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_77 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_78 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_79 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_80 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_83 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_84 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_84 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_84 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_85 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_86 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_87 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_88 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_89 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_90 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_91 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_92 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_93 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_94 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_95 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_96 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_97 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_98 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_99 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_100 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_101 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_102 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_103 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_104 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_105 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_106 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_107 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_108 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_109 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_110 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_111 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_112 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_113 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_115 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_115 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_116 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_117 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_118 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_119 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_120 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_121 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_122 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_123 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_124 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_125 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_126 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_127 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_128 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_129 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_130 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_131 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_132 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_133 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_134 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_135 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_136 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_137 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_138 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_139 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_140 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_141 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_142 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_143 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_144 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_146 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_146 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_147 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_148 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_149 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_1 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_2 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_3 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_4 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_5 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_6 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_7 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_8 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_9 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_10 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_11 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_12 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_13 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_14 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_15 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_16 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_17 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_18 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_19 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_21 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_21 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_22 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_23 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_24 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_25 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_26 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_27 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_28 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_29 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_30 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_31 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_32 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_33 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_34 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_35 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_36 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_37 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_38 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_39 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_40 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_41 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_42 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_43 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_44 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_45 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_46 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_47 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_48 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_49 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_50 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_51 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_52 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_53 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_54 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_55 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_83 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_84 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_83 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_84 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_85 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_86 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_87 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_88 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_89 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_90 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_91 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_92 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_93 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_94 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_95 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_96 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_97 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_98 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_99 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_100 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_101 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_102 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_103 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_104 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_105 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_106 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_107 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_108 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_109 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_110 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_111 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_112 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_113 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_114 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_115 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_116 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_117 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_118 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_119 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_120 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_121 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_122 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_123 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_124 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_125 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_126 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_127 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_128 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_129 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_130 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_131 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_132 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_133 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_134 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_135 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_136 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_137 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_138 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_139 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_140 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_141 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_142 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_143 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_144 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_145 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_146 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_147 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_148 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_149 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_1 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_2 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_82 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_83 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_114 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_115 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_116 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_117 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_118 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_119 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_120 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_121 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_122 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_123 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_124 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_125 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_126 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_127 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_128 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_129 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_130 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_131 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_132 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_133 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_134 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_135 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_136 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_137 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_138 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_139 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_140 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_141 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_142 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_143 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_144 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_1 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_2 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_3 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_4 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_5 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_6 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_7 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_7 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_8 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_9 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_10 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_12 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_13 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_81 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_82 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_114 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_111 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_112 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_113 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_114 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_115 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_116 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_117 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_118 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_119 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_120 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_121 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_122 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_123 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_124 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_125 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_126 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_127 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_128 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_129 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_130 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_131 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_132 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_133 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_134 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_135 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_136 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_137 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_138 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_139 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_140 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_1 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_2 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_3 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_3 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_4 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_6 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_7 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_6 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_7 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_8 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_9 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_12 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_13 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_10 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_11 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_12 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_13 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_14 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_15 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_18 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_20 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_19 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_20 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_19 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_20 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_21 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_22 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_23 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_24 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_25 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_26 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_27 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_28 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_29 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_30 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_31 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_32 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_33 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_34 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_35 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_36 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_37 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_38 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_39 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_40 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_41 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_42 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_43 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_44 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_45 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_46 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_47 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_48 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_49 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_50 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_55 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_54 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_55 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_53 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_54 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_55 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_56 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_57 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_58 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_59 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_60 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_61 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_62 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_63 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_64 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_65 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_66 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_67 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_68 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_81 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_82 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_79 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_77 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_78 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_79 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_80 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_81 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_82 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_83 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_84 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_85 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_86 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_87 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_88 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_89 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_90 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_91 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_92 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_93 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_94 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_95 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_96 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_97 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_98 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_99 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_100 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_101 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_102 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_103 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_104 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_105 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_106 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_1 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_3 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_2 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_3 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_5 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_7 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_4 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_5 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_6 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_7 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_11 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_13 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_8 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_9 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_10 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_11 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_12 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_13 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_16 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_20 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_17 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_18 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_14 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_15 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_16 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_17 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_18 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_19 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_20 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_21 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_22 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_23 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_24 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_25 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_26 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_27 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_28 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_29 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_30 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_31 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_32 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_33 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_34 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_35 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_36 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_37 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_38 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_39 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_40 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_41 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_42 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_43 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_44 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_45 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_53 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_51 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_52 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_46 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_47 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_48 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_49 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_50 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_51 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_52 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_53 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_54 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_55 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_56 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_57 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_58 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_59 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_60 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_61 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_62 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_63 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_64 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_65 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_66 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_67 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_75 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_81 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53]
wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T = {decoded_addr_decoded_decoded_andMatrixOutputs_hi, decoded_addr_decoded_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_140_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_134 = decoded_addr_decoded_decoded_andMatrixOutputs_140_2; // @[pla.scala:98:70, :114:36]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_1 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_4 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_8 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_10 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_14 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_16 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_18 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_24 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_26 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_28 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_30 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_32 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_34 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_36 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_38 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_40 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_42 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_44 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_46 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_48 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_50 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_52 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_54 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_59 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_61 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_63 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_65 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_67 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_69 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_71 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_73 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_75 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_77 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_79 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_86 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_88 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_90 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_92 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_94 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_96 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_98 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_100 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_102 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_104 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_106 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_108 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_110 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_112 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_114 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_117 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_119 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_121 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_123 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_125 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_127 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_129 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_131 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_133 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_135 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_137 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_139 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_141 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_143 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_145 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_148 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_150 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_1 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_2 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_6 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_10 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_11 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_16 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_17 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_20 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_23 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_26 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_27 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_30 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_31 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_34 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_35 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_38 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_39 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_42 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_43 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_46 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_47 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_50 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_51 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_54 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_55 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_58 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_61 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_62 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_65 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_66 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_69 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_70 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_73 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_74 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_77 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_78 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_81 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_86 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_87 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_90 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_91 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_94 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_95 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_98 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_99 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_102 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_103 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_106 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_107 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_110 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_111 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_114 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_115 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_117 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_118 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_121 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_122 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_125 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_126 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_129 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_130 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_133 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_134 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_137 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_138 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_141 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_142 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_145 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_146 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_148 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_149 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_1}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_1}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_1}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_136_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_133 = decoded_addr_decoded_decoded_andMatrixOutputs_136_2; // @[pla.scala:98:70, :114:36]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_2 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_5 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_9 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_11 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_15 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_17 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_19 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_25 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_27 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_29 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_31 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_33 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_35 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_37 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_39 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_41 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_43 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_45 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_47 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_49 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_51 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_53 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_55 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_60 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_62 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_64 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_66 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_68 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_70 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_72 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_74 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_76 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_78 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_80 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_87 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_89 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_91 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_93 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_95 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_97 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_99 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_101 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_103 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_105 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_107 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_109 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_111 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_113 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_115 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_118 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_120 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_122 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_124 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_126 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_128 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_130 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_132 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_134 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_136 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_138 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_140 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_142 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_144 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_146 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_149 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_151 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_2}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_2}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_2}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_2}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_41_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_132 = decoded_addr_decoded_decoded_andMatrixOutputs_41_2; // @[pla.scala:98:70, :114:36]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_3 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_4 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_5 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_6 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_7 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_8 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_9 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_10 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_11 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_12 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_13 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_13 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_14 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_15 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_16 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_17 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_18 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_19 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_20 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_21 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_22 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_23 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_24 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_25 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_26 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_27 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_28 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_29 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_30 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_31 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_32 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_33 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_34 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_35 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_36 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_37 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_38 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_39 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_40 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_41 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_42 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_43 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_44 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_45 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_46 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_47 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_48 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_49 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_50 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_51 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_52 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_53 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_54 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_55 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_56 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_57 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_58 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_59 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_60 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_61 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_62 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_63 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_64 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_65 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_66 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_67 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_68 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_69 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_70 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_71 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_72 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_73 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_74 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_75 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_76 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_77 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_78 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_79 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_80 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_82 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_83 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_84 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_85 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_86 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_87 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_88 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_89 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_90 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_91 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_92 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_93 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_94 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_95 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_96 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_97 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_98 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_99 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_100 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_101 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_102 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_103 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_104 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_105 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_106 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_107 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_108 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_109 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_110 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_111 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_112 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_113 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_145 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_146 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_147 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_148 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_149 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_3}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_3}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53]
wire [9:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_1_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_37 = decoded_addr_decoded_decoded_andMatrixOutputs_1_2; // @[pla.scala:98:70, :114:36]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_4 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_5 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_6 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_12 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_18 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_19 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_20 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_24 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_25 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_26 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_27 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_32 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_33 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_34 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_35 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_40 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_41 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_42 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_43 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_48 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_49 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_50 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_51 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_56 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_63 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_64 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_65 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_66 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_71 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_72 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_73 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_74 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_88 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_89 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_90 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_91 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_96 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_97 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_98 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_99 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_104 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_105 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_106 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_107 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_112 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_113 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_114 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_115 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_119 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_120 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_121 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_122 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_127 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_128 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_129 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_130 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_135 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_136 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_137 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_138 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_143 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_144 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_145 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_146 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_150 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_151 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_3}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_4}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_4}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_4}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_4}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_89_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_35 = decoded_addr_decoded_decoded_andMatrixOutputs_89_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_4}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_5}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_125_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_29 = decoded_addr_decoded_decoded_andMatrixOutputs_125_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_6}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53]
wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_27_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_28 = decoded_addr_decoded_decoded_andMatrixOutputs_27_2; // @[pla.scala:98:70, :114:36]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_7 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_21 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_28 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_29 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_30 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_31 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_32 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_33 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_34 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_35 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_44 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_45 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_46 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_47 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_48 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_49 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_50 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_51 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_67 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_68 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_69 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_70 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_71 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_72 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_73 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_74 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_84 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_92 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_93 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_94 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_95 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_96 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_97 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_98 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_99 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_108 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_109 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_110 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_111 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_112 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_113 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_114 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_115 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_123 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_124 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_125 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_126 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_127 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_128 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_129 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_130 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_139 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_140 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_141 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_142 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_143 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_144 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_145 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_146 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_7}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53]
wire [8:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_0_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_25 = decoded_addr_decoded_decoded_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_8 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_9 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_10 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_11 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_12 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_51 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_52 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_53 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_54 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_56 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_82 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_6}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_8}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_8}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_8}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_92_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_34 = decoded_addr_decoded_decoded_andMatrixOutputs_92_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_7}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_9}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_9}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_9}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_9}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_59_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_30 = decoded_addr_decoded_decoded_andMatrixOutputs_59_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_8}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_10}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_10}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_10}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_10}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_24_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_33 = decoded_addr_decoded_decoded_andMatrixOutputs_24_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_9}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_11}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_11}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_11}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_11}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_118_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_32 = decoded_addr_decoded_decoded_andMatrixOutputs_118_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_12}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_12}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_12}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_12}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53]
wire [9:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_123_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_36 = decoded_addr_decoded_decoded_andMatrixOutputs_123_2; // @[pla.scala:98:70, :114:36]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_13 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_56 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_57 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_58 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_59 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_60 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_61 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_62 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_63 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_64 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_65 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_66 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_67 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_68 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_69 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_70 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_71 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_72 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_73 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_74 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_75 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_76 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_77 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_78 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_79 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_80 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_82 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_13}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_13}; // @[pla.scala:91:29, :98:53]
wire [4:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_74_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_31 = decoded_addr_decoded_decoded_andMatrixOutputs_74_2; // @[pla.scala:98:70, :114:36]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_12 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_13 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_14 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_15 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_16 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_17 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_19 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_20 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_21 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_22 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_21 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_22 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_23 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_24 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_25 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_26 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_27 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_28 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_29 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_30 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_31 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_32 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_33 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_34 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_35 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_36 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_37 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_38 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_39 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_40 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_41 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_42 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_43 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_44 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_45 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_46 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_47 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_48 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_49 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_50 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_51 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_52 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_55 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_56 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_57 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_56 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_57 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_58 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_59 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_60 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_61 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_62 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_63 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_64 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_65 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_66 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_67 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_68 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_69 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_70 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_71 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_72 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_73 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_74 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_75 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_76 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_77 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_80 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_82 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_83 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_80 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_81 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_82 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_83 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_84 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_85 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_86 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_87 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_88 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_89 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_90 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_91 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_92 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_93 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_94 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_95 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_96 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_97 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_98 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_99 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_100 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_101 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_102 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_103 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_104 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_105 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_106 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_107 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_108 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_109 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_145 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_142 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_143 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_144 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_145 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_10}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_8}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_13}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_13}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_14}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_14}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_116_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_146 = decoded_addr_decoded_decoded_andMatrixOutputs_116_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_11}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_9}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_14}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_14}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_14}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_15}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_15}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_106_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_147 = decoded_addr_decoded_decoded_andMatrixOutputs_106_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_12}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_15}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_15}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_15}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_16}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_16}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_82_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_26 = decoded_addr_decoded_decoded_andMatrixOutputs_82_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_13}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_16}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_16}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_16}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_17}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_16}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_17}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_16}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_28_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_27 = decoded_addr_decoded_decoded_andMatrixOutputs_28_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_14}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_12}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_17}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_17}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_17}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_18}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_17}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_18}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_17}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_91_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_143 = decoded_addr_decoded_decoded_andMatrixOutputs_91_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_15}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_13}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_18}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_18}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_18}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_19}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_19}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_18}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_68_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_145 = decoded_addr_decoded_decoded_andMatrixOutputs_68_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_16}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_19}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_19}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_19}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_20}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_20}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_19}; // @[pla.scala:98:53]
wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_84_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_41 = decoded_addr_decoded_decoded_andMatrixOutputs_84_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_20}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_20}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_20}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_21}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_21}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_20}; // @[pla.scala:98:53]
wire [8:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_40_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_38 = decoded_addr_decoded_decoded_andMatrixOutputs_40_2; // @[pla.scala:98:70, :114:36]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_22 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_23 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_23 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_24 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_25 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_26 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_27 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_28 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_29 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_30 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_31 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_32 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_33 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_34 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_35 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_36 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_37 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_38 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_39 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_40 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_41 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_42 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_43 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_44 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_45 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_46 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_47 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_48 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_49 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_50 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_57 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_58 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_58 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_59 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_60 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_61 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_62 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_63 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_64 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_65 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_66 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_67 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_68 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_69 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_70 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_71 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_72 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_73 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_74 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_75 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_76 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_77 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_78 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_79 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_81 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_17}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_21}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_21}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_21}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_22}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_21}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_22}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_21}; // @[pla.scala:98:53]
wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_34_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_131 = decoded_addr_decoded_decoded_andMatrixOutputs_34_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_18}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_22}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_22}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_22}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_23}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_22}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_23}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_22}; // @[pla.scala:98:53]
wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_138_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_128 = decoded_addr_decoded_decoded_andMatrixOutputs_138_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_19}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_14}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_23}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_23}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_23}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_24}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_23}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_24}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_23}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_lo_24}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_55_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_125 = decoded_addr_decoded_decoded_andMatrixOutputs_55_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_20}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_15}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_24}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_24}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_24}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_25}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_24}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_25}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_24}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_lo_25}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_107_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_122 = decoded_addr_decoded_decoded_andMatrixOutputs_107_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_21}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_16}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_25}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_25}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_25}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_26}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_25}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_26}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_25}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_lo_26}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_111_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_119 = decoded_addr_decoded_decoded_andMatrixOutputs_111_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_22}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_17}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_26}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_26}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_26}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_27}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_26}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_27}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_26}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_lo_27}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_7_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_116 = decoded_addr_decoded_decoded_andMatrixOutputs_7_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_23}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_18}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_27}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_27}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_27}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_28}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_27}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_28}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_28}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_27}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_lo_28}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_47_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_28; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_113 = decoded_addr_decoded_decoded_andMatrixOutputs_47_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_24}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_19}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_28}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_28}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_28}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_29}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_28}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_29}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_29}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_28}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_lo_29}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_143_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_29; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_110 = decoded_addr_decoded_decoded_andMatrixOutputs_143_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_25}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_20}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_29}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_29}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_29}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_30}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_29}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_30}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_30}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_29}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_lo_30}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_11_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_30; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_107 = decoded_addr_decoded_decoded_andMatrixOutputs_11_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_26}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_21}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_30}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_30}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_30}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_31}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_30}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_31}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_31}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_30}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_lo_31}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_120_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_31; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_104 = decoded_addr_decoded_decoded_andMatrixOutputs_120_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_27}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_22}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_31}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_31}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_31}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_32}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_31}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_32}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_32}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_31}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_lo_32}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_122_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_32; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_101 = decoded_addr_decoded_decoded_andMatrixOutputs_122_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_28}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_23}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_32}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_32}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_32}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_33}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_32}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_33}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_33}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_32}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_lo_33}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_141_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_33; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_98 = decoded_addr_decoded_decoded_andMatrixOutputs_141_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_29}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_24}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_33}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_33}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_33}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_34}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_33}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_34}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_34}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_33}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_lo_34}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_86_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_34; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_95 = decoded_addr_decoded_decoded_andMatrixOutputs_86_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_30}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_25}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_34}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_34}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_34}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_35}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_34}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_35}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_35}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_34}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_lo_35}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_8_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_35; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_92 = decoded_addr_decoded_decoded_andMatrixOutputs_8_2; // @[pla.scala:98:70, :114:36]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_36 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_37 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_38 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_39 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_40 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_41 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_42 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_43 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_44 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_45 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_46 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_47 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_48 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_49 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_50 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_51 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_59 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_60 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_61 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_62 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_63 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_64 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_65 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_66 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_67 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_68 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_69 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_70 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_71 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_72 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_73 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_74 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_79 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_80 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_81 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_100 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_101 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_102 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_103 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_104 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_105 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_106 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_107 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_108 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_109 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_110 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_111 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_112 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_113 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_114 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_115 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_131 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_132 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_133 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_134 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_135 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_136 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_137 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_138 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_139 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_140 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_141 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_142 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_143 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_144 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_145 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_146 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_147 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_148 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_149 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_150 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_151 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_31}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_26}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_35}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_35}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_35}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_36}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_35}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_36}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_36}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_35}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_lo_36}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_61_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_36; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_89 = decoded_addr_decoded_decoded_andMatrixOutputs_61_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_32}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_27}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_36}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_36}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_36}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_37}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_36}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_37}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_37}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_36}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_lo_37}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_83_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_37; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_86 = decoded_addr_decoded_decoded_andMatrixOutputs_83_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_33}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_28}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_37}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_37}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_37}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_38}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_37}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_38}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_38}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_37}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_lo_38}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_131_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_38; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_83 = decoded_addr_decoded_decoded_andMatrixOutputs_131_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_34}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_29}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_38}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_38}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_38}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_39}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_38}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_39}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_39}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_38}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_lo_39}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_17_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_39; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_80 = decoded_addr_decoded_decoded_andMatrixOutputs_17_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_35}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_30}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_39}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_39}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_39}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_40}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_39}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_40}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_40}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_39}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_lo_40}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_87_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_40; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_77 = decoded_addr_decoded_decoded_andMatrixOutputs_87_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_36}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_31}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_40}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_40}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_40}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_41}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_40}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_41}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_41}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_40}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_lo_41}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_135_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_41; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_74 = decoded_addr_decoded_decoded_andMatrixOutputs_135_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_37}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_32}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_41}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_41}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_41}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_42}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_41}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_42}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_42}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_41}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_lo_42}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_144_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_42; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_71 = decoded_addr_decoded_decoded_andMatrixOutputs_144_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_38}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_33}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_42}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_42}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_42}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_43}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_42}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_43}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_43}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_42}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_lo_43}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_22_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_43; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_68 = decoded_addr_decoded_decoded_andMatrixOutputs_22_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_39}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_34}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_43}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_43}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_43}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_44}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_43}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_44}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_44}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_43}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_lo_44}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_94_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_44; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_65 = decoded_addr_decoded_decoded_andMatrixOutputs_94_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_40}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_35}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_44}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_44}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_44}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_45}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_44}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_45}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_45}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_44}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_lo_45}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_65_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_45; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_62 = decoded_addr_decoded_decoded_andMatrixOutputs_65_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_41}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_36}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_45}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_45}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_45}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_46}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_45}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_46}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_46}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_45}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_lo_46}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_36_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_46; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_59 = decoded_addr_decoded_decoded_andMatrixOutputs_36_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_42}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_37}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_46}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_46}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_46}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_47}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_46}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_47}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_47}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_46}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_lo_47}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_33_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_47; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_56 = decoded_addr_decoded_decoded_andMatrixOutputs_33_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_43}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_38}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_47}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_47}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_47}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_48}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_47}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_48}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_48}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_47}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_lo_48}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_63_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_48; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_53 = decoded_addr_decoded_decoded_andMatrixOutputs_63_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_44}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_39}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_48}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_48}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_48}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_49}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_48}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_49}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_49}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_48}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_lo_49}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_39_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_49; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_50 = decoded_addr_decoded_decoded_andMatrixOutputs_39_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_45}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_40}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_49}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_49}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_49}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_50}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_49}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_50}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_50}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_49}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_lo_50}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_32_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_50; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_47 = decoded_addr_decoded_decoded_andMatrixOutputs_32_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_46}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_41}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_50}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_50}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_50}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_51}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_50}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_51}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_51}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_50}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_lo_51}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_146_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_51; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_44 = decoded_addr_decoded_decoded_andMatrixOutputs_146_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_47}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_42}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_51}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_51}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_51}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_52}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_51}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_52}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_52}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_51}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_lo_52}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_66_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_52; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_142 = decoded_addr_decoded_decoded_andMatrixOutputs_66_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_48}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_43}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_52}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_52}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_52}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_53}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_52}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_53}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_53}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_52}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_lo_53}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_108_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_53; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_141 = decoded_addr_decoded_decoded_andMatrixOutputs_108_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_49}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_44}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_53}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_53}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_53}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_54}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_53}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_54}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_54}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_53}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_lo_54}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_80_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_54; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_139 = decoded_addr_decoded_decoded_andMatrixOutputs_80_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_50}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_45}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_54}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_54}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_54}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_55}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_54}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_55}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_55}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_54}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_lo_55}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_124_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_55; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_140 = decoded_addr_decoded_decoded_andMatrixOutputs_124_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_53}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_55}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_55}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_55}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_56}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_56}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_56}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_55}; // @[pla.scala:98:53]
wire [9:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_lo_56}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_121_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_56; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_144 = decoded_addr_decoded_decoded_andMatrixOutputs_121_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_51}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_56}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_56}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_56}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_57}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_56}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_57}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_57}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_56}; // @[pla.scala:98:53]
wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_lo_57}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_67_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_57; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_24 = decoded_addr_decoded_decoded_andMatrixOutputs_67_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_52}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_57}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_57}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_57}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_58}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_57}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_58}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_58}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_57}; // @[pla.scala:98:53]
wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_lo_58}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_48_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_58; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_23 = decoded_addr_decoded_decoded_andMatrixOutputs_48_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_53}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_46}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_58}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_58}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_58}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_59}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_58}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_59}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_59}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_58}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_lo_59}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_10_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_59; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_22 = decoded_addr_decoded_decoded_andMatrixOutputs_10_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_54}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_47}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_59}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_59}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_59}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_60}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_59}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_60}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_60}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_59}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_lo_60}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_45_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_60; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_21 = decoded_addr_decoded_decoded_andMatrixOutputs_45_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_55}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_48}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_60}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_60}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_60}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_61}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_60}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_61}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_61}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_60}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_lo_61}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_18_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_61; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_20 = decoded_addr_decoded_decoded_andMatrixOutputs_18_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_56}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_49}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_61}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_61}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_61}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_62}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_61}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_62}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_62}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_61}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_lo_62}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_88_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_62; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_19 = decoded_addr_decoded_decoded_andMatrixOutputs_88_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_57}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_50}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_62}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_62}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_62}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_63}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_62}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_63}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_63}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_62}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_lo_63}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_57_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_63; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_18 = decoded_addr_decoded_decoded_andMatrixOutputs_57_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_58}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_51}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_63}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_63}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_63}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_64}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_63}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_64}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_64}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_63}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_lo_64}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_85_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_64; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_17 = decoded_addr_decoded_decoded_andMatrixOutputs_85_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_59}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_52}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_64}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_64}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_64}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_65}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_64}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_65}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_65}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_64}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_lo_65}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_101_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_65; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_16 = decoded_addr_decoded_decoded_andMatrixOutputs_101_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_60}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_53}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_65}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_65}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_65}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_66}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_65}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_66}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_66}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_65}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_lo_66}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_113_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_66; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_15 = decoded_addr_decoded_decoded_andMatrixOutputs_113_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_61}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_54}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_66}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_66}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_66}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_67}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_66}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_67}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_67}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_66}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_lo_67}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_93_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_67; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_14 = decoded_addr_decoded_decoded_andMatrixOutputs_93_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_62}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_55}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_67}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_67}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_67}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_68}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_67}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_68}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_68}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_67}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_lo_68}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_139_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_68; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_13 = decoded_addr_decoded_decoded_andMatrixOutputs_139_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_63}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_56}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_68}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_68}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_68}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_69}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_68}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_69}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_69}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_68}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_lo_69}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_72_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_69; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_12 = decoded_addr_decoded_decoded_andMatrixOutputs_72_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_64}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_57}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_69}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_69}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_69}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_70}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_69}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_70}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_70}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_69}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_lo_70}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_42_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_70; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_11 = decoded_addr_decoded_decoded_andMatrixOutputs_42_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_65}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_58}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_70}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_70}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_70}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_71}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_70}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_71}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_71}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_70}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_lo_71}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_147_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_71; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_10 = decoded_addr_decoded_decoded_andMatrixOutputs_147_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_66}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_59}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_71}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_71}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_71}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_72}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_71}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_72}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_72}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_71}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_lo_72}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_99_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_72; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_9 = decoded_addr_decoded_decoded_andMatrixOutputs_99_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_67}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_60}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_72}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_72}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_72}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_73}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_72}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_73}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_73}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_72}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_lo_73}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_115_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_73; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_8 = decoded_addr_decoded_decoded_andMatrixOutputs_115_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_68}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_61}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_73}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_73}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_73}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_74}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_73}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_74}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_74}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_73}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_lo_74}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_151_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_74; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_7 = decoded_addr_decoded_decoded_andMatrixOutputs_151_2; // @[pla.scala:98:70, :114:36]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_69 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_70 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_71 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_72 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_73 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_74 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_78 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_82 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_110 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_108 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_109 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_110 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_111 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_112 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_113 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_114 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_115 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_116 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_117 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_118 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_119 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_120 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_121 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_122 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_123 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_124 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_125 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_126 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_127 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_128 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_129 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_130 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_131 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_132 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_133 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_134 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_135 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_136 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_137 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_141 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_139 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_140 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_141 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_142 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_69}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_62}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_74}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_74}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_74}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_75}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_74}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_75}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_75}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_74}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_lo_75}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_2_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_75; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_151 = decoded_addr_decoded_decoded_andMatrixOutputs_2_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_70}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_63}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_75}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_75}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_75}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_76}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_75}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_76}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_76}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_75}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_lo_76}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_148_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_76; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_150 = decoded_addr_decoded_decoded_andMatrixOutputs_148_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_71}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_64}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_76}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_76}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_76}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_77}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_76}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_77}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_77}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_76}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_lo_77}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_130_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_77; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_149 = decoded_addr_decoded_decoded_andMatrixOutputs_130_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_72}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_65}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_77}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_77}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_77}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_78}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_77}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_78}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_78}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_77}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_lo_78}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_56_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_78; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_148 = decoded_addr_decoded_decoded_andMatrixOutputs_56_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_73}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_66}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_78}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_78}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_78}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_79}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_78}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_79}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_79}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_78}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_lo_79}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_3_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_79; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_137 = decoded_addr_decoded_decoded_andMatrixOutputs_3_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_74}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_67}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_79}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_79}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_79}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_80}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_79}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_80}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_80}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_79}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_lo_80}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_50_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_80; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_136 = decoded_addr_decoded_decoded_andMatrixOutputs_50_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_75}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_80}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_80}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_80}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_81}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_80}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_81}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_81}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_80}; // @[pla.scala:98:53]
wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_lo_81}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_23_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_81; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_135 = decoded_addr_decoded_decoded_andMatrixOutputs_23_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_82}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_81}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_82}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_82}; // @[pla.scala:90:45, :98:53]
wire [5:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_lo_82}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_12_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_82; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_4 = decoded_addr_decoded_decoded_andMatrixOutputs_12_2; // @[pla.scala:98:70, :114:36]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_81 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_82 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_76 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_68 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_69 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_70 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_71 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_72 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_73 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_74 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_75 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_76 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_77 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_78 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_79 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_80 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_81 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_82 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_83 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_84 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_85 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_86 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_87 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_88 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_89 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_90 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_91 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_92 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_93 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_94 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_95 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_96 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_97 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_107 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_98 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_99 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_100 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_101 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_102 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_103 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_104 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_105 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_106 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_107 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_108 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_109 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_110 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_111 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_112 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_113 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_114 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_115 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_116 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_117 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_118 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_119 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_120 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_121 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_122 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_123 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_124 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_125 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_126 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_127 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_138 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_128 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_129 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_130 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_131 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_81}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_81}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_81}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_83}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_83}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_83}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_81}; // @[pla.scala:98:53]
wire [8:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_lo_83}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_102_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_83; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_6 = decoded_addr_decoded_decoded_andMatrixOutputs_102_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_82}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_82}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_82}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_84}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_84}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_84}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_82}; // @[pla.scala:98:53]
wire [8:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_lo_84}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_97_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_84; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_5 = decoded_addr_decoded_decoded_andMatrixOutputs_97_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_76}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_83}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_83}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_83}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_85}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_84}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_85}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_85}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_83}; // @[pla.scala:98:53]
wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_lo_85}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_76_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_85; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_130 = decoded_addr_decoded_decoded_andMatrixOutputs_76_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_77}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_68}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_84}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_84}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_84}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_86}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_85}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_86}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_86}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_84}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_lo_86}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_79_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_86; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_129 = decoded_addr_decoded_decoded_andMatrixOutputs_79_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_78}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_69}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_85}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_85}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_85}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_87}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_86}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_87}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_87}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_85}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_lo_87}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_95_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_87; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_127 = decoded_addr_decoded_decoded_andMatrixOutputs_95_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_79}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_70}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_86}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_86}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_86}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_88}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_87}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_88}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_88}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_86}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_lo_88}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_26_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_88; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_124 = decoded_addr_decoded_decoded_andMatrixOutputs_26_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_80}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_71}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_87}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_87}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_87}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_89}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_88}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_89}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_89}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_87}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_lo_89}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_126_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_89; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_121 = decoded_addr_decoded_decoded_andMatrixOutputs_126_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_81}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_72}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_88}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_88}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_88}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_90}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_89}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_90}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_90}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_88}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_lo_90}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_149_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_90; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_118 = decoded_addr_decoded_decoded_andMatrixOutputs_149_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_82}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_73}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_89}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_89}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_89}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_91}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_90}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_91}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_91}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_89}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_lo_91}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_77_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_91; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_115 = decoded_addr_decoded_decoded_andMatrixOutputs_77_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_83}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_74}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_90}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_90}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_90}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_92}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_91}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_92}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_92}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_90}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_lo_92}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_142_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_92; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_112 = decoded_addr_decoded_decoded_andMatrixOutputs_142_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_84}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_75}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_91}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_91}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_91}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_93}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_92}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_93}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_93}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_91}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_lo_93}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_44_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_93; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_109 = decoded_addr_decoded_decoded_andMatrixOutputs_44_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_85}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_76}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_92}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_92}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_92}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_94}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_93}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_94}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_94}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_92}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_lo_94}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_31_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_94; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_106 = decoded_addr_decoded_decoded_andMatrixOutputs_31_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_86}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_77}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_93}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_93}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_93}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_95}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_94}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_95}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_95}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_93}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_lo_95}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_62_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_95; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_103 = decoded_addr_decoded_decoded_andMatrixOutputs_62_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_87}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_78}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_94}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_94}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_94}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_96}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_95}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_96}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_96}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_94}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_lo_96}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_58_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_96; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_100 = decoded_addr_decoded_decoded_andMatrixOutputs_58_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_88}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_79}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_95}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_95}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_95}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_97}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_96}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_97}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_97}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_95}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_lo_97}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_134_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_97; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_97 = decoded_addr_decoded_decoded_andMatrixOutputs_134_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_89}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_80}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_96}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_96}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_96}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_98}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_97}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_98}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_98}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_96}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_lo_98}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_9_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_98; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_94 = decoded_addr_decoded_decoded_andMatrixOutputs_9_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_90}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_81}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_97}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_97}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_97}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_99}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_98}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_99}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_99}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_97}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_lo_99}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_117_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_99; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_91 = decoded_addr_decoded_decoded_andMatrixOutputs_117_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_91}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_82}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_98}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_98}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_98}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_100}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_99}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_100}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_100}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_98}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_lo_100}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_5_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_100; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_88 = decoded_addr_decoded_decoded_andMatrixOutputs_5_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_92}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_83}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_99}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_99}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_99}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_101}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_100}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_101}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_101}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_99}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_lo_101}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_71_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_101; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_85 = decoded_addr_decoded_decoded_andMatrixOutputs_71_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_93}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_84}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_100}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_100}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_100}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_102}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_101}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_102}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_102}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_100}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_lo_102}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_132_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_102; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_82 = decoded_addr_decoded_decoded_andMatrixOutputs_132_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_94}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_85}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_101}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_101}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_101}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_103}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_102}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_103}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_103}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_101}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_lo_103}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_104_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_103; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_79 = decoded_addr_decoded_decoded_andMatrixOutputs_104_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_95}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_86}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_102}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_102}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_102}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_104}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_103}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_104}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_104}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_102}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_lo_104}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_4_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_104; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_76 = decoded_addr_decoded_decoded_andMatrixOutputs_4_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_96}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_87}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_103}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_103}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_103}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_105}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_104}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_105}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_105}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_103}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_lo_105}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_29_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_105; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_73 = decoded_addr_decoded_decoded_andMatrixOutputs_29_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_97}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_88}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_104}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_104}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_104}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_106}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_105}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_106}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_106}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_104}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_lo_106}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_16_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_106; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_70 = decoded_addr_decoded_decoded_andMatrixOutputs_16_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_98}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_89}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_105}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_105}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_105}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_107}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_106}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_107}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_107}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_105}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_lo_107}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_145_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_107; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_67 = decoded_addr_decoded_decoded_andMatrixOutputs_145_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_99}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_90}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_106}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_106}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_106}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_108}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_107}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_108}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_108}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_106}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_lo_108}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_133_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_108; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_64 = decoded_addr_decoded_decoded_andMatrixOutputs_133_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_100}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_91}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_107}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_107}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_107}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_109}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_108}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_109}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_109}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_107}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_lo_109}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_14_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_109; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_61 = decoded_addr_decoded_decoded_andMatrixOutputs_14_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_101}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_92}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_108}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_108}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_108}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_110}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_109}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_110}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_110}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_108}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_lo_110}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_90_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_110; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_58 = decoded_addr_decoded_decoded_andMatrixOutputs_90_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_102}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_93}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_109}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_109}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_109}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_111}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_110}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_111}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_111}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_109}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_lo_111}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_98_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_111; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_55 = decoded_addr_decoded_decoded_andMatrixOutputs_98_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_103}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_94}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_110}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_110}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_110}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_112}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_111}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_112}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_112}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_110}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_lo_112}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_60_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_112; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_52 = decoded_addr_decoded_decoded_andMatrixOutputs_60_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_104}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_95}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_111}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_111}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_111}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_113}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_112}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_113}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_113}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_111}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_lo_113}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_96_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_113; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_49 = decoded_addr_decoded_decoded_andMatrixOutputs_96_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_105}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_96}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_112}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_112}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_112}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_114}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_113}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_114}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_114}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_112}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_lo_114}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_54_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_114; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_46 = decoded_addr_decoded_decoded_andMatrixOutputs_54_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_106}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_97}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_113}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_113}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_113}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_115}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_114}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_115}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_115}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_113}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_lo_115}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_128_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_115; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_43 = decoded_addr_decoded_decoded_andMatrixOutputs_128_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_107}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_114}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_114}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_114}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_116}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_115}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_116}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_116}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_114}; // @[pla.scala:98:53]
wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_lo_116}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_49_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_116; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_40 = decoded_addr_decoded_decoded_andMatrixOutputs_49_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_108}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_98}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_115}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_115}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_115}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_117}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_116}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_117}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_117}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_115}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_lo_117}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_52_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_117; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_39 = decoded_addr_decoded_decoded_andMatrixOutputs_52_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_109}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_99}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_116}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_116}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_116}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_118}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_117}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_118}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_118}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_116}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_lo_118}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_20_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_118; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_126 = decoded_addr_decoded_decoded_andMatrixOutputs_20_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_110}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_100}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_117}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_117}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_117}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_119}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_118}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_119}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_119}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_117}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_lo_119}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_109_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_119; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_123 = decoded_addr_decoded_decoded_andMatrixOutputs_109_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_111}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_101}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_118}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_118}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_118}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_120}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_119}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_120}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_120}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_118}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_lo_120}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_6_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_120; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_120 = decoded_addr_decoded_decoded_andMatrixOutputs_6_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_112}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_102}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_119}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_119}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_119}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_121}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_120}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_121}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_121}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_119}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_lo_121}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_21_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_121; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_117 = decoded_addr_decoded_decoded_andMatrixOutputs_21_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_113}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_103}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_120}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_120}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_120}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_122}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_121}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_122}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_122}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_120}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_lo_122}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_30_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_122; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_114 = decoded_addr_decoded_decoded_andMatrixOutputs_30_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_114}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_104}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_121}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_121}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_121}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_123}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_122}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_123}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_123}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_121}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_lo_123}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_129_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_123; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_111 = decoded_addr_decoded_decoded_andMatrixOutputs_129_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_115}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_105}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_122}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_122}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_122}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_124}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_123}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_124}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_124}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_122}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_lo_124}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_35_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_124; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_108 = decoded_addr_decoded_decoded_andMatrixOutputs_35_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_116}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_106}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_123}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_123}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_123}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_125}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_124}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_125}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_125}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_123}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_lo_125}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_73_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_125; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_105 = decoded_addr_decoded_decoded_andMatrixOutputs_73_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_117}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_107}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_124}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_124}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_124}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_126}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_125}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_126}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_126}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_124}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_lo_126}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_53_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_126; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_102 = decoded_addr_decoded_decoded_andMatrixOutputs_53_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_118}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_108}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_125}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_125}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_125}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_127}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_126}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_127}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_127}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_125}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_lo_127}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_137_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_127; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_99 = decoded_addr_decoded_decoded_andMatrixOutputs_137_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_119}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_109}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_126}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_126}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_126}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_128}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_127}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_128}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_128}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_126}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_lo_128}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_37_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_128; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_96 = decoded_addr_decoded_decoded_andMatrixOutputs_37_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_120}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_110}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_127}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_127}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_127}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_129}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_128}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_129}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_129}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_127}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_lo_129}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_25_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_129; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_93 = decoded_addr_decoded_decoded_andMatrixOutputs_25_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_121}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_111}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_128}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_128}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_128}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_130}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_129}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_130}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_130}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_128}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_lo_130}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_64_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_130; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_90 = decoded_addr_decoded_decoded_andMatrixOutputs_64_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_122}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_112}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_129}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_129}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_129}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_131}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_130}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_131}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_131}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_129}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_lo_131}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_19_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_131; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_87 = decoded_addr_decoded_decoded_andMatrixOutputs_19_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_123}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_113}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_130}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_130}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_130}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_132}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_131}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_132}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_132}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_130}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_lo_132}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_114_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_132; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_84 = decoded_addr_decoded_decoded_andMatrixOutputs_114_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_124}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_114}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_131}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_131}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_131}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_133}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_132}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_133}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_133}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_131}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_lo_133}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_110_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_133; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_81 = decoded_addr_decoded_decoded_andMatrixOutputs_110_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_125}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_115}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_132}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_132}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_132}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_134}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_133}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_134}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_134}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_132}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_lo_134}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_150_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_134; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_78 = decoded_addr_decoded_decoded_andMatrixOutputs_150_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_126}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_116}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_133}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_133}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_133}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_135}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_134}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_135}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_135}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_133}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_lo_135}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_69_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_135; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_75 = decoded_addr_decoded_decoded_andMatrixOutputs_69_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_127}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_117}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_134}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_134}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_134}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_136}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_135}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_136}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_136}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_134}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_lo_136}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_105_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_136; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_72 = decoded_addr_decoded_decoded_andMatrixOutputs_105_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_128}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_118}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_135}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_135}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_135}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_137}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_136}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_137}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_137}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_135}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_lo_137}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_100_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_137; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_69 = decoded_addr_decoded_decoded_andMatrixOutputs_100_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_129}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_119}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_136}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_136}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_136}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_138}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_137}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_138}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_138}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_136}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_lo_138}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_127_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_138; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_66 = decoded_addr_decoded_decoded_andMatrixOutputs_127_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_130}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_120}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_137}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_137}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_137}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_139}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_138}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_139}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_139}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_137}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_lo_139}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_119_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_139; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_63 = decoded_addr_decoded_decoded_andMatrixOutputs_119_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_131}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_121}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_138}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_138}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_138}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_140}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_139}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_140}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_140}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_138}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_lo_140}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_46_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_140; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_60 = decoded_addr_decoded_decoded_andMatrixOutputs_46_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_132}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_122}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_139}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_139}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_139}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_141}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_140}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_141}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_141}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_139}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_lo_141}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_15_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_141; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_57 = decoded_addr_decoded_decoded_andMatrixOutputs_15_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_133}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_123}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_140}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_140}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_140}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_142}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_141}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_142}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_142}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_140}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_lo_142}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_51_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_142; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_54 = decoded_addr_decoded_decoded_andMatrixOutputs_51_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_134}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_124}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_141}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_141}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_141}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_143}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_142}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_143}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_143}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_141}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_lo_143}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_43_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_143; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_51 = decoded_addr_decoded_decoded_andMatrixOutputs_43_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_135}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_125}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_142}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_142}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_142}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_144}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_143}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_144}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_144}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_142}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_lo_144}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_70_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_144; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_48 = decoded_addr_decoded_decoded_andMatrixOutputs_70_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_136}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_126}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_143}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_143}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_143}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_145}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_144}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_145}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_145}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_143}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_lo_145}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_78_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_145; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_45 = decoded_addr_decoded_decoded_andMatrixOutputs_78_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_137}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_127}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_144}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_144}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_144}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_146}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_145}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_146}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_146}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_144}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_lo_146}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_112_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_146; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_42 = decoded_addr_decoded_decoded_andMatrixOutputs_112_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_138}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_145}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_145}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_145}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_147}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_146}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_147}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_147}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_145}; // @[pla.scala:98:53]
wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_lo_147}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_103_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_147; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_1 = decoded_addr_decoded_decoded_andMatrixOutputs_103_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_139}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_128}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_146}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_146}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_146}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_148}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_147}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_148}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_148}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_146}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_lo_148}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_38_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_148; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_3 = decoded_addr_decoded_decoded_andMatrixOutputs_38_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_140}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_129}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_147}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_147}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_147}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_149}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_148}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_149}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_149}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_147}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_lo_149}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_13_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_149; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_2 = decoded_addr_decoded_decoded_andMatrixOutputs_13_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_141}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_130}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_148}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_148}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_150 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_148}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_150, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_150}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_149}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_150, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_150}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_150 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_150}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_150 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_150, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_148}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_150 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_150, decoded_addr_decoded_decoded_andMatrixOutputs_lo_150}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_81_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_150; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_138 = decoded_addr_decoded_decoded_andMatrixOutputs_81_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_142}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_131}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_149}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_150 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_149}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_151 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_150, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_149}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_151, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_151}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_150}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_151, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_151}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_151 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_151}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_151 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_151, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_149}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_151 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_151, decoded_addr_decoded_decoded_andMatrixOutputs_lo_151}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_75_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_151; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T = decoded_addr_decoded_decoded_andMatrixOutputs_75_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_1, _decoded_addr_decoded_decoded_orMatrixOutputs_T}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_3, _decoded_addr_decoded_decoded_orMatrixOutputs_T_2}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_5, _decoded_addr_decoded_decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_8, _decoded_addr_decoded_decoded_orMatrixOutputs_T_7}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_6}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo}; // @[pla.scala:102:36]
wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_10, _decoded_addr_decoded_decoded_orMatrixOutputs_T_9}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_13, _decoded_addr_decoded_decoded_orMatrixOutputs_T_12}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_11}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_15, _decoded_addr_decoded_decoded_orMatrixOutputs_T_14}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_18, _decoded_addr_decoded_decoded_orMatrixOutputs_T_17}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_16}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo}; // @[pla.scala:102:36]
wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo}; // @[pla.scala:102:36]
wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_20, _decoded_addr_decoded_decoded_orMatrixOutputs_T_19}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_22, _decoded_addr_decoded_decoded_orMatrixOutputs_T_21}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_24, _decoded_addr_decoded_decoded_orMatrixOutputs_T_23}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_27, _decoded_addr_decoded_decoded_orMatrixOutputs_T_26}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_25}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo}; // @[pla.scala:102:36]
wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_29, _decoded_addr_decoded_decoded_orMatrixOutputs_T_28}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_32, _decoded_addr_decoded_decoded_orMatrixOutputs_T_31}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_30}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_34, _decoded_addr_decoded_decoded_orMatrixOutputs_T_33}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_37, _decoded_addr_decoded_decoded_orMatrixOutputs_T_36}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_35}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo}; // @[pla.scala:102:36]
wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:102:36]
wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:102:36]
wire [37:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_39, _decoded_addr_decoded_decoded_orMatrixOutputs_T_38}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_41, _decoded_addr_decoded_decoded_orMatrixOutputs_T_40}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_43, _decoded_addr_decoded_decoded_orMatrixOutputs_T_42}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_46, _decoded_addr_decoded_decoded_orMatrixOutputs_T_45}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_44}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo}; // @[pla.scala:102:36]
wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_48, _decoded_addr_decoded_decoded_orMatrixOutputs_T_47}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_51, _decoded_addr_decoded_decoded_orMatrixOutputs_T_50}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_49}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_53, _decoded_addr_decoded_decoded_orMatrixOutputs_T_52}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_56, _decoded_addr_decoded_decoded_orMatrixOutputs_T_55}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_54}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo}; // @[pla.scala:102:36]
wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo}; // @[pla.scala:102:36]
wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_58, _decoded_addr_decoded_decoded_orMatrixOutputs_T_57}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_60, _decoded_addr_decoded_decoded_orMatrixOutputs_T_59}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_62, _decoded_addr_decoded_decoded_orMatrixOutputs_T_61}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_65, _decoded_addr_decoded_decoded_orMatrixOutputs_T_64}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_63}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo}; // @[pla.scala:102:36]
wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_67, _decoded_addr_decoded_decoded_orMatrixOutputs_T_66}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_70, _decoded_addr_decoded_decoded_orMatrixOutputs_T_69}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_68}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_72, _decoded_addr_decoded_decoded_orMatrixOutputs_T_71}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_75, _decoded_addr_decoded_decoded_orMatrixOutputs_T_74}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_73}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo}; // @[pla.scala:102:36]
wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:102:36]
wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:102:36]
wire [37:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo}; // @[pla.scala:102:36]
wire [75:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_77, _decoded_addr_decoded_decoded_orMatrixOutputs_T_76}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_79, _decoded_addr_decoded_decoded_orMatrixOutputs_T_78}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_81, _decoded_addr_decoded_decoded_orMatrixOutputs_T_80}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_84, _decoded_addr_decoded_decoded_orMatrixOutputs_T_83}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_82}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo}; // @[pla.scala:102:36]
wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_86, _decoded_addr_decoded_decoded_orMatrixOutputs_T_85}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_89, _decoded_addr_decoded_decoded_orMatrixOutputs_T_88}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_87}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_91, _decoded_addr_decoded_decoded_orMatrixOutputs_T_90}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_94, _decoded_addr_decoded_decoded_orMatrixOutputs_T_93}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_92}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo}; // @[pla.scala:102:36]
wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo}; // @[pla.scala:102:36]
wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_96, _decoded_addr_decoded_decoded_orMatrixOutputs_T_95}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_98, _decoded_addr_decoded_decoded_orMatrixOutputs_T_97}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_100, _decoded_addr_decoded_decoded_orMatrixOutputs_T_99}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_103, _decoded_addr_decoded_decoded_orMatrixOutputs_T_102}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_101}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo}; // @[pla.scala:102:36]
wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_105, _decoded_addr_decoded_decoded_orMatrixOutputs_T_104}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_108, _decoded_addr_decoded_decoded_orMatrixOutputs_T_107}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_106}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_110, _decoded_addr_decoded_decoded_orMatrixOutputs_T_109}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_113, _decoded_addr_decoded_decoded_orMatrixOutputs_T_112}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_111}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo}; // @[pla.scala:102:36]
wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:102:36]
wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:102:36]
wire [37:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_115, _decoded_addr_decoded_decoded_orMatrixOutputs_T_114}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_117, _decoded_addr_decoded_decoded_orMatrixOutputs_T_116}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_119, _decoded_addr_decoded_decoded_orMatrixOutputs_T_118}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_122, _decoded_addr_decoded_decoded_orMatrixOutputs_T_121}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_120}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo}; // @[pla.scala:102:36]
wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_124, _decoded_addr_decoded_decoded_orMatrixOutputs_T_123}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_127, _decoded_addr_decoded_decoded_orMatrixOutputs_T_126}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_125}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_129, _decoded_addr_decoded_decoded_orMatrixOutputs_T_128}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_132, _decoded_addr_decoded_decoded_orMatrixOutputs_T_131}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_130}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo}; // @[pla.scala:102:36]
wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:102:36]
wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_134, _decoded_addr_decoded_decoded_orMatrixOutputs_T_133}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_136, _decoded_addr_decoded_decoded_orMatrixOutputs_T_135}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_138, _decoded_addr_decoded_decoded_orMatrixOutputs_T_137}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_141, _decoded_addr_decoded_decoded_orMatrixOutputs_T_140}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_139}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo}; // @[pla.scala:102:36]
wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_143, _decoded_addr_decoded_decoded_orMatrixOutputs_T_142}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_146, _decoded_addr_decoded_decoded_orMatrixOutputs_T_145}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_144}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_148, _decoded_addr_decoded_decoded_orMatrixOutputs_T_147}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_151, _decoded_addr_decoded_decoded_orMatrixOutputs_T_150}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_149}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo}; // @[pla.scala:102:36]
wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:102:36]
wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:102:36]
wire [37:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo}; // @[pla.scala:102:36]
wire [75:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:102:36]
wire [151:0] decoded_addr_decoded_decoded_orMatrixOutputs = {decoded_addr_decoded_decoded_orMatrixOutputs_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo}; // @[pla.scala:102:36]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T = decoded_addr_decoded_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_1 = decoded_addr_decoded_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_2 = decoded_addr_decoded_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_3 = decoded_addr_decoded_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_4 = decoded_addr_decoded_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_5 = decoded_addr_decoded_decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_6 = decoded_addr_decoded_decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_7 = decoded_addr_decoded_decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_8 = decoded_addr_decoded_decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_9 = decoded_addr_decoded_decoded_orMatrixOutputs[9]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_10 = decoded_addr_decoded_decoded_orMatrixOutputs[10]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_11 = decoded_addr_decoded_decoded_orMatrixOutputs[11]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_12 = decoded_addr_decoded_decoded_orMatrixOutputs[12]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_13 = decoded_addr_decoded_decoded_orMatrixOutputs[13]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_14 = decoded_addr_decoded_decoded_orMatrixOutputs[14]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_15 = decoded_addr_decoded_decoded_orMatrixOutputs[15]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_16 = decoded_addr_decoded_decoded_orMatrixOutputs[16]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_17 = decoded_addr_decoded_decoded_orMatrixOutputs[17]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_18 = decoded_addr_decoded_decoded_orMatrixOutputs[18]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_19 = decoded_addr_decoded_decoded_orMatrixOutputs[19]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_20 = decoded_addr_decoded_decoded_orMatrixOutputs[20]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_21 = decoded_addr_decoded_decoded_orMatrixOutputs[21]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_22 = decoded_addr_decoded_decoded_orMatrixOutputs[22]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_23 = decoded_addr_decoded_decoded_orMatrixOutputs[23]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_24 = decoded_addr_decoded_decoded_orMatrixOutputs[24]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_25 = decoded_addr_decoded_decoded_orMatrixOutputs[25]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_26 = decoded_addr_decoded_decoded_orMatrixOutputs[26]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_27 = decoded_addr_decoded_decoded_orMatrixOutputs[27]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_28 = decoded_addr_decoded_decoded_orMatrixOutputs[28]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_29 = decoded_addr_decoded_decoded_orMatrixOutputs[29]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_30 = decoded_addr_decoded_decoded_orMatrixOutputs[30]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_31 = decoded_addr_decoded_decoded_orMatrixOutputs[31]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_32 = decoded_addr_decoded_decoded_orMatrixOutputs[32]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_33 = decoded_addr_decoded_decoded_orMatrixOutputs[33]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_34 = decoded_addr_decoded_decoded_orMatrixOutputs[34]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_35 = decoded_addr_decoded_decoded_orMatrixOutputs[35]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_36 = decoded_addr_decoded_decoded_orMatrixOutputs[36]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_37 = decoded_addr_decoded_decoded_orMatrixOutputs[37]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_38 = decoded_addr_decoded_decoded_orMatrixOutputs[38]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_39 = decoded_addr_decoded_decoded_orMatrixOutputs[39]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_40 = decoded_addr_decoded_decoded_orMatrixOutputs[40]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_41 = decoded_addr_decoded_decoded_orMatrixOutputs[41]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_42 = decoded_addr_decoded_decoded_orMatrixOutputs[42]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_43 = decoded_addr_decoded_decoded_orMatrixOutputs[43]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_44 = decoded_addr_decoded_decoded_orMatrixOutputs[44]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_45 = decoded_addr_decoded_decoded_orMatrixOutputs[45]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_46 = decoded_addr_decoded_decoded_orMatrixOutputs[46]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_47 = decoded_addr_decoded_decoded_orMatrixOutputs[47]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_48 = decoded_addr_decoded_decoded_orMatrixOutputs[48]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_49 = decoded_addr_decoded_decoded_orMatrixOutputs[49]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_50 = decoded_addr_decoded_decoded_orMatrixOutputs[50]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_51 = decoded_addr_decoded_decoded_orMatrixOutputs[51]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_52 = decoded_addr_decoded_decoded_orMatrixOutputs[52]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_53 = decoded_addr_decoded_decoded_orMatrixOutputs[53]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_54 = decoded_addr_decoded_decoded_orMatrixOutputs[54]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_55 = decoded_addr_decoded_decoded_orMatrixOutputs[55]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_56 = decoded_addr_decoded_decoded_orMatrixOutputs[56]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_57 = decoded_addr_decoded_decoded_orMatrixOutputs[57]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_58 = decoded_addr_decoded_decoded_orMatrixOutputs[58]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_59 = decoded_addr_decoded_decoded_orMatrixOutputs[59]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_60 = decoded_addr_decoded_decoded_orMatrixOutputs[60]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_61 = decoded_addr_decoded_decoded_orMatrixOutputs[61]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_62 = decoded_addr_decoded_decoded_orMatrixOutputs[62]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_63 = decoded_addr_decoded_decoded_orMatrixOutputs[63]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_64 = decoded_addr_decoded_decoded_orMatrixOutputs[64]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_65 = decoded_addr_decoded_decoded_orMatrixOutputs[65]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_66 = decoded_addr_decoded_decoded_orMatrixOutputs[66]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_67 = decoded_addr_decoded_decoded_orMatrixOutputs[67]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_68 = decoded_addr_decoded_decoded_orMatrixOutputs[68]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_69 = decoded_addr_decoded_decoded_orMatrixOutputs[69]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_70 = decoded_addr_decoded_decoded_orMatrixOutputs[70]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_71 = decoded_addr_decoded_decoded_orMatrixOutputs[71]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_72 = decoded_addr_decoded_decoded_orMatrixOutputs[72]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_73 = decoded_addr_decoded_decoded_orMatrixOutputs[73]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_74 = decoded_addr_decoded_decoded_orMatrixOutputs[74]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_75 = decoded_addr_decoded_decoded_orMatrixOutputs[75]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_76 = decoded_addr_decoded_decoded_orMatrixOutputs[76]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_77 = decoded_addr_decoded_decoded_orMatrixOutputs[77]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_78 = decoded_addr_decoded_decoded_orMatrixOutputs[78]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_79 = decoded_addr_decoded_decoded_orMatrixOutputs[79]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_80 = decoded_addr_decoded_decoded_orMatrixOutputs[80]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_81 = decoded_addr_decoded_decoded_orMatrixOutputs[81]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_82 = decoded_addr_decoded_decoded_orMatrixOutputs[82]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_83 = decoded_addr_decoded_decoded_orMatrixOutputs[83]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_84 = decoded_addr_decoded_decoded_orMatrixOutputs[84]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_85 = decoded_addr_decoded_decoded_orMatrixOutputs[85]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_86 = decoded_addr_decoded_decoded_orMatrixOutputs[86]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_87 = decoded_addr_decoded_decoded_orMatrixOutputs[87]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_88 = decoded_addr_decoded_decoded_orMatrixOutputs[88]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_89 = decoded_addr_decoded_decoded_orMatrixOutputs[89]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_90 = decoded_addr_decoded_decoded_orMatrixOutputs[90]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_91 = decoded_addr_decoded_decoded_orMatrixOutputs[91]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_92 = decoded_addr_decoded_decoded_orMatrixOutputs[92]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_93 = decoded_addr_decoded_decoded_orMatrixOutputs[93]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_94 = decoded_addr_decoded_decoded_orMatrixOutputs[94]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_95 = decoded_addr_decoded_decoded_orMatrixOutputs[95]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_96 = decoded_addr_decoded_decoded_orMatrixOutputs[96]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_97 = decoded_addr_decoded_decoded_orMatrixOutputs[97]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_98 = decoded_addr_decoded_decoded_orMatrixOutputs[98]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_99 = decoded_addr_decoded_decoded_orMatrixOutputs[99]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_100 = decoded_addr_decoded_decoded_orMatrixOutputs[100]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_101 = decoded_addr_decoded_decoded_orMatrixOutputs[101]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_102 = decoded_addr_decoded_decoded_orMatrixOutputs[102]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_103 = decoded_addr_decoded_decoded_orMatrixOutputs[103]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_104 = decoded_addr_decoded_decoded_orMatrixOutputs[104]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_105 = decoded_addr_decoded_decoded_orMatrixOutputs[105]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_106 = decoded_addr_decoded_decoded_orMatrixOutputs[106]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_107 = decoded_addr_decoded_decoded_orMatrixOutputs[107]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_108 = decoded_addr_decoded_decoded_orMatrixOutputs[108]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_109 = decoded_addr_decoded_decoded_orMatrixOutputs[109]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_110 = decoded_addr_decoded_decoded_orMatrixOutputs[110]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_111 = decoded_addr_decoded_decoded_orMatrixOutputs[111]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_112 = decoded_addr_decoded_decoded_orMatrixOutputs[112]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_113 = decoded_addr_decoded_decoded_orMatrixOutputs[113]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_114 = decoded_addr_decoded_decoded_orMatrixOutputs[114]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_115 = decoded_addr_decoded_decoded_orMatrixOutputs[115]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_116 = decoded_addr_decoded_decoded_orMatrixOutputs[116]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_117 = decoded_addr_decoded_decoded_orMatrixOutputs[117]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_118 = decoded_addr_decoded_decoded_orMatrixOutputs[118]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_119 = decoded_addr_decoded_decoded_orMatrixOutputs[119]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_120 = decoded_addr_decoded_decoded_orMatrixOutputs[120]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_121 = decoded_addr_decoded_decoded_orMatrixOutputs[121]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_122 = decoded_addr_decoded_decoded_orMatrixOutputs[122]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_123 = decoded_addr_decoded_decoded_orMatrixOutputs[123]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_124 = decoded_addr_decoded_decoded_orMatrixOutputs[124]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_125 = decoded_addr_decoded_decoded_orMatrixOutputs[125]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_126 = decoded_addr_decoded_decoded_orMatrixOutputs[126]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_127 = decoded_addr_decoded_decoded_orMatrixOutputs[127]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_128 = decoded_addr_decoded_decoded_orMatrixOutputs[128]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_129 = decoded_addr_decoded_decoded_orMatrixOutputs[129]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_130 = decoded_addr_decoded_decoded_orMatrixOutputs[130]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_131 = decoded_addr_decoded_decoded_orMatrixOutputs[131]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_132 = decoded_addr_decoded_decoded_orMatrixOutputs[132]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_133 = decoded_addr_decoded_decoded_orMatrixOutputs[133]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_134 = decoded_addr_decoded_decoded_orMatrixOutputs[134]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_135 = decoded_addr_decoded_decoded_orMatrixOutputs[135]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_136 = decoded_addr_decoded_decoded_orMatrixOutputs[136]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_137 = decoded_addr_decoded_decoded_orMatrixOutputs[137]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_138 = decoded_addr_decoded_decoded_orMatrixOutputs[138]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_139 = decoded_addr_decoded_decoded_orMatrixOutputs[139]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_140 = decoded_addr_decoded_decoded_orMatrixOutputs[140]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_141 = decoded_addr_decoded_decoded_orMatrixOutputs[141]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_142 = decoded_addr_decoded_decoded_orMatrixOutputs[142]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_143 = decoded_addr_decoded_decoded_orMatrixOutputs[143]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_144 = decoded_addr_decoded_decoded_orMatrixOutputs[144]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_145 = decoded_addr_decoded_decoded_orMatrixOutputs[145]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_146 = decoded_addr_decoded_decoded_orMatrixOutputs[146]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_147 = decoded_addr_decoded_decoded_orMatrixOutputs[147]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_148 = decoded_addr_decoded_decoded_orMatrixOutputs[148]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_149 = decoded_addr_decoded_decoded_orMatrixOutputs[149]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_150 = decoded_addr_decoded_decoded_orMatrixOutputs[150]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_151 = decoded_addr_decoded_decoded_orMatrixOutputs[151]; // @[pla.scala:102:36, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_1, _decoded_addr_decoded_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_3, _decoded_addr_decoded_decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31]
wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_5, _decoded_addr_decoded_decoded_invMatrixOutputs_T_4}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_8, _decoded_addr_decoded_decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_6}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo}; // @[pla.scala:120:37]
wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_10, _decoded_addr_decoded_decoded_invMatrixOutputs_T_9}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_13, _decoded_addr_decoded_decoded_invMatrixOutputs_T_12}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_11}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_15, _decoded_addr_decoded_decoded_invMatrixOutputs_T_14}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_18, _decoded_addr_decoded_decoded_invMatrixOutputs_T_17}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo}; // @[pla.scala:120:37]
wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo}; // @[pla.scala:120:37]
wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_20, _decoded_addr_decoded_decoded_invMatrixOutputs_T_19}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_22, _decoded_addr_decoded_decoded_invMatrixOutputs_T_21}; // @[pla.scala:120:37, :124:31]
wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_24, _decoded_addr_decoded_decoded_invMatrixOutputs_T_23}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_27, _decoded_addr_decoded_decoded_invMatrixOutputs_T_26}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_25}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo}; // @[pla.scala:120:37]
wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_29, _decoded_addr_decoded_decoded_invMatrixOutputs_T_28}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_32, _decoded_addr_decoded_decoded_invMatrixOutputs_T_31}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_30}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_34, _decoded_addr_decoded_decoded_invMatrixOutputs_T_33}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_37, _decoded_addr_decoded_decoded_invMatrixOutputs_T_36}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_35}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo}; // @[pla.scala:120:37]
wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:120:37]
wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:120:37]
wire [37:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_39, _decoded_addr_decoded_decoded_invMatrixOutputs_T_38}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_41, _decoded_addr_decoded_decoded_invMatrixOutputs_T_40}; // @[pla.scala:120:37, :124:31]
wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_43, _decoded_addr_decoded_decoded_invMatrixOutputs_T_42}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_46, _decoded_addr_decoded_decoded_invMatrixOutputs_T_45}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_44}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo}; // @[pla.scala:120:37]
wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_48, _decoded_addr_decoded_decoded_invMatrixOutputs_T_47}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_51, _decoded_addr_decoded_decoded_invMatrixOutputs_T_50}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_49}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_53, _decoded_addr_decoded_decoded_invMatrixOutputs_T_52}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_56, _decoded_addr_decoded_decoded_invMatrixOutputs_T_55}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_54}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo}; // @[pla.scala:120:37]
wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo}; // @[pla.scala:120:37]
wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_58, _decoded_addr_decoded_decoded_invMatrixOutputs_T_57}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_60, _decoded_addr_decoded_decoded_invMatrixOutputs_T_59}; // @[pla.scala:120:37, :124:31]
wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_62, _decoded_addr_decoded_decoded_invMatrixOutputs_T_61}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_65, _decoded_addr_decoded_decoded_invMatrixOutputs_T_64}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_63}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo}; // @[pla.scala:120:37]
wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_67, _decoded_addr_decoded_decoded_invMatrixOutputs_T_66}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_70, _decoded_addr_decoded_decoded_invMatrixOutputs_T_69}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_68}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_72, _decoded_addr_decoded_decoded_invMatrixOutputs_T_71}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_75, _decoded_addr_decoded_decoded_invMatrixOutputs_T_74}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_73}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo}; // @[pla.scala:120:37]
wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:120:37]
wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:120:37]
wire [37:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo}; // @[pla.scala:120:37]
wire [75:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_77, _decoded_addr_decoded_decoded_invMatrixOutputs_T_76}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_79, _decoded_addr_decoded_decoded_invMatrixOutputs_T_78}; // @[pla.scala:120:37, :124:31]
wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_81, _decoded_addr_decoded_decoded_invMatrixOutputs_T_80}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_84, _decoded_addr_decoded_decoded_invMatrixOutputs_T_83}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_82}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo}; // @[pla.scala:120:37]
wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_86, _decoded_addr_decoded_decoded_invMatrixOutputs_T_85}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_89, _decoded_addr_decoded_decoded_invMatrixOutputs_T_88}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_87}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_91, _decoded_addr_decoded_decoded_invMatrixOutputs_T_90}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_94, _decoded_addr_decoded_decoded_invMatrixOutputs_T_93}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_92}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo}; // @[pla.scala:120:37]
wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo}; // @[pla.scala:120:37]
wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_96, _decoded_addr_decoded_decoded_invMatrixOutputs_T_95}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_98, _decoded_addr_decoded_decoded_invMatrixOutputs_T_97}; // @[pla.scala:120:37, :124:31]
wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_100, _decoded_addr_decoded_decoded_invMatrixOutputs_T_99}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_103, _decoded_addr_decoded_decoded_invMatrixOutputs_T_102}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_101}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo}; // @[pla.scala:120:37]
wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_105, _decoded_addr_decoded_decoded_invMatrixOutputs_T_104}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_108, _decoded_addr_decoded_decoded_invMatrixOutputs_T_107}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_106}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_110, _decoded_addr_decoded_decoded_invMatrixOutputs_T_109}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_113, _decoded_addr_decoded_decoded_invMatrixOutputs_T_112}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_111}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo}; // @[pla.scala:120:37]
wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:120:37]
wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:120:37]
wire [37:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_115, _decoded_addr_decoded_decoded_invMatrixOutputs_T_114}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_117, _decoded_addr_decoded_decoded_invMatrixOutputs_T_116}; // @[pla.scala:120:37, :124:31]
wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_119, _decoded_addr_decoded_decoded_invMatrixOutputs_T_118}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_122, _decoded_addr_decoded_decoded_invMatrixOutputs_T_121}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_120}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo}; // @[pla.scala:120:37]
wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_124, _decoded_addr_decoded_decoded_invMatrixOutputs_T_123}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_127, _decoded_addr_decoded_decoded_invMatrixOutputs_T_126}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_125}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_129, _decoded_addr_decoded_decoded_invMatrixOutputs_T_128}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_132, _decoded_addr_decoded_decoded_invMatrixOutputs_T_131}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_130}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo}; // @[pla.scala:120:37]
wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:120:37]
wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_134, _decoded_addr_decoded_decoded_invMatrixOutputs_T_133}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_136, _decoded_addr_decoded_decoded_invMatrixOutputs_T_135}; // @[pla.scala:120:37, :124:31]
wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_138, _decoded_addr_decoded_decoded_invMatrixOutputs_T_137}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_141, _decoded_addr_decoded_decoded_invMatrixOutputs_T_140}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_139}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo}; // @[pla.scala:120:37]
wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_143, _decoded_addr_decoded_decoded_invMatrixOutputs_T_142}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_146, _decoded_addr_decoded_decoded_invMatrixOutputs_T_145}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_144}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_148, _decoded_addr_decoded_decoded_invMatrixOutputs_T_147}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_151, _decoded_addr_decoded_decoded_invMatrixOutputs_T_150}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_149}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo}; // @[pla.scala:120:37]
wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:120:37]
wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:120:37]
wire [37:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo}; // @[pla.scala:120:37]
wire [75:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37]
assign decoded_addr_decoded_decoded_invMatrixOutputs = {decoded_addr_decoded_decoded_invMatrixOutputs_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37]
assign decoded_addr_decoded_decoded = decoded_addr_decoded_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37]
assign decoded_addr_decoded_decoded_plaInput = decoded_addr_addr[11:0]; // @[pla.scala:77:22]
wire decoded_addr_decoded_0 = decoded_addr_decoded_decoded[151]; // @[pla.scala:81:23]
wire decoded_addr_98_2 = decoded_addr_decoded_0; // @[Decode.scala:50:77]
wire decoded_addr_decoded_1 = decoded_addr_decoded_decoded[150]; // @[pla.scala:81:23]
wire decoded_addr_55_2 = decoded_addr_decoded_1; // @[Decode.scala:50:77]
wire decoded_addr_decoded_2 = decoded_addr_decoded_decoded[149]; // @[pla.scala:81:23]
wire decoded_addr_10_2 = decoded_addr_decoded_2; // @[Decode.scala:50:77]
wire decoded_addr_decoded_3 = decoded_addr_decoded_decoded[148]; // @[pla.scala:81:23]
wire decoded_addr_120_2 = decoded_addr_decoded_3; // @[Decode.scala:50:77]
wire decoded_addr_decoded_4 = decoded_addr_decoded_decoded[147]; // @[pla.scala:81:23]
wire decoded_addr_95_2 = decoded_addr_decoded_4; // @[Decode.scala:50:77]
wire decoded_addr_decoded_5 = decoded_addr_decoded_decoded[146]; // @[pla.scala:81:23]
wire decoded_addr_101_2 = decoded_addr_decoded_5; // @[Decode.scala:50:77]
wire decoded_addr_decoded_6 = decoded_addr_decoded_decoded[145]; // @[pla.scala:81:23]
wire decoded_addr_72_2 = decoded_addr_decoded_6; // @[Decode.scala:50:77]
wire decoded_addr_decoded_7 = decoded_addr_decoded_decoded[144]; // @[pla.scala:81:23]
wire decoded_addr_109_2 = decoded_addr_decoded_7; // @[Decode.scala:50:77]
wire decoded_addr_decoded_8 = decoded_addr_decoded_decoded[143]; // @[pla.scala:81:23]
wire decoded_addr_77_2 = decoded_addr_decoded_8; // @[Decode.scala:50:77]
wire decoded_addr_decoded_9 = decoded_addr_decoded_decoded[142]; // @[pla.scala:81:23]
wire decoded_addr_131_2 = decoded_addr_decoded_9; // @[Decode.scala:50:77]
wire decoded_addr_decoded_10 = decoded_addr_decoded_decoded[141]; // @[pla.scala:81:23]
wire decoded_addr_134_2 = decoded_addr_decoded_10; // @[Decode.scala:50:77]
wire decoded_addr_decoded_11 = decoded_addr_decoded_decoded[140]; // @[pla.scala:81:23]
wire decoded_addr_138_2 = decoded_addr_decoded_11; // @[Decode.scala:50:77]
wire decoded_addr_decoded_12 = decoded_addr_decoded_decoded[139]; // @[pla.scala:81:23]
wire decoded_addr_29_2 = decoded_addr_decoded_12; // @[Decode.scala:50:77]
wire decoded_addr_decoded_13 = decoded_addr_decoded_decoded[138]; // @[pla.scala:81:23]
wire decoded_addr_133_2 = decoded_addr_decoded_13; // @[Decode.scala:50:77]
wire decoded_addr_decoded_14 = decoded_addr_decoded_decoded[137]; // @[pla.scala:81:23]
wire decoded_addr_49_2 = decoded_addr_decoded_14; // @[Decode.scala:50:77]
wire decoded_addr_decoded_15 = decoded_addr_decoded_decoded[136]; // @[pla.scala:81:23]
wire decoded_addr_90_2 = decoded_addr_decoded_15; // @[Decode.scala:50:77]
wire decoded_addr_decoded_16 = decoded_addr_decoded_decoded[135]; // @[pla.scala:81:23]
wire decoded_addr_57_2 = decoded_addr_decoded_16; // @[Decode.scala:50:77]
wire decoded_addr_decoded_17 = decoded_addr_decoded_decoded[134]; // @[pla.scala:81:23]
wire decoded_addr_36_2 = decoded_addr_decoded_17; // @[Decode.scala:50:77]
wire decoded_addr_decoded_18 = decoded_addr_decoded_decoded[133]; // @[pla.scala:81:23]
wire decoded_addr_68_2 = decoded_addr_decoded_18; // @[Decode.scala:50:77]
wire decoded_addr_decoded_19 = decoded_addr_decoded_decoded[132]; // @[pla.scala:81:23]
wire decoded_addr_100_2 = decoded_addr_decoded_19; // @[Decode.scala:50:77]
wire decoded_addr_decoded_20 = decoded_addr_decoded_decoded[131]; // @[pla.scala:81:23]
wire decoded_addr_132_2 = decoded_addr_decoded_20; // @[Decode.scala:50:77]
wire decoded_addr_decoded_21 = decoded_addr_decoded_decoded[130]; // @[pla.scala:81:23]
wire decoded_addr_104_2 = decoded_addr_decoded_21; // @[Decode.scala:50:77]
wire decoded_addr_decoded_22 = decoded_addr_decoded_decoded[129]; // @[pla.scala:81:23]
wire decoded_addr_123_2 = decoded_addr_decoded_22; // @[Decode.scala:50:77]
wire decoded_addr_decoded_23 = decoded_addr_decoded_decoded[128]; // @[pla.scala:81:23]
wire decoded_addr_148_2 = decoded_addr_decoded_23; // @[Decode.scala:50:77]
wire decoded_addr_decoded_24 = decoded_addr_decoded_decoded[127]; // @[pla.scala:81:23]
wire decoded_addr_17_2 = decoded_addr_decoded_24; // @[Decode.scala:50:77]
wire decoded_addr_decoded_25 = decoded_addr_decoded_decoded[126]; // @[pla.scala:81:23]
wire decoded_addr_27_2 = decoded_addr_decoded_25; // @[Decode.scala:50:77]
wire decoded_addr_decoded_26 = decoded_addr_decoded_decoded[125]; // @[pla.scala:81:23]
wire decoded_addr_84_2 = decoded_addr_decoded_26; // @[Decode.scala:50:77]
wire decoded_addr_decoded_27 = decoded_addr_decoded_decoded[124]; // @[pla.scala:81:23]
wire decoded_addr_52_2 = decoded_addr_decoded_27; // @[Decode.scala:50:77]
wire decoded_addr_decoded_28 = decoded_addr_decoded_decoded[123]; // @[pla.scala:81:23]
wire decoded_addr_146_2 = decoded_addr_decoded_28; // @[Decode.scala:50:77]
wire decoded_addr_decoded_29 = decoded_addr_decoded_decoded[122]; // @[pla.scala:81:23]
wire decoded_addr_70_2 = decoded_addr_decoded_29; // @[Decode.scala:50:77]
wire decoded_addr_decoded_30 = decoded_addr_decoded_decoded[121]; // @[pla.scala:81:23]
wire decoded_addr_112_2 = decoded_addr_decoded_30; // @[Decode.scala:50:77]
wire decoded_addr_decoded_31 = decoded_addr_decoded_decoded[120]; // @[pla.scala:81:23]
wire decoded_addr_83_2 = decoded_addr_decoded_31; // @[Decode.scala:50:77]
wire decoded_addr_decoded_32 = decoded_addr_decoded_decoded[119]; // @[pla.scala:81:23]
wire decoded_addr_31_2 = decoded_addr_decoded_32; // @[Decode.scala:50:77]
wire decoded_addr_decoded_33 = decoded_addr_decoded_decoded[118]; // @[pla.scala:81:23]
wire decoded_addr_0_2 = decoded_addr_decoded_33; // @[Decode.scala:50:77]
wire decoded_addr_decoded_34 = decoded_addr_decoded_decoded[117]; // @[pla.scala:81:23]
wire decoded_addr_59_2 = decoded_addr_decoded_34; // @[Decode.scala:50:77]
wire decoded_addr_decoded_35 = decoded_addr_decoded_decoded[116]; // @[pla.scala:81:23]
wire decoded_addr_140_2 = decoded_addr_decoded_35; // @[Decode.scala:50:77]
wire decoded_addr_decoded_36 = decoded_addr_decoded_decoded[115]; // @[pla.scala:81:23]
wire decoded_addr_128_2 = decoded_addr_decoded_36; // @[Decode.scala:50:77]
wire decoded_addr_decoded_37 = decoded_addr_decoded_decoded[114]; // @[pla.scala:81:23]
wire decoded_addr_74_2 = decoded_addr_decoded_37; // @[Decode.scala:50:77]
wire decoded_addr_decoded_38 = decoded_addr_decoded_decoded[113]; // @[pla.scala:81:23]
wire decoded_addr_117_2 = decoded_addr_decoded_38; // @[Decode.scala:50:77]
wire decoded_addr_decoded_39 = decoded_addr_decoded_decoded[112]; // @[pla.scala:81:23]
wire decoded_addr_91_2 = decoded_addr_decoded_39; // @[Decode.scala:50:77]
wire decoded_addr_decoded_40 = decoded_addr_decoded_decoded[111]; // @[pla.scala:81:23]
wire decoded_addr_114_2 = decoded_addr_decoded_40; // @[Decode.scala:50:77]
wire decoded_addr_decoded_41 = decoded_addr_decoded_decoded[110]; // @[pla.scala:81:23]
wire decoded_addr_1_2 = decoded_addr_decoded_41; // @[Decode.scala:50:77]
wire decoded_addr_decoded_42 = decoded_addr_decoded_decoded[109]; // @[pla.scala:81:23]
wire decoded_addr_16_2 = decoded_addr_decoded_42; // @[Decode.scala:50:77]
wire decoded_addr_decoded_43 = decoded_addr_decoded_decoded[108]; // @[pla.scala:81:23]
wire decoded_addr_79_2 = decoded_addr_decoded_43; // @[Decode.scala:50:77]
wire decoded_addr_decoded_44 = decoded_addr_decoded_decoded[107]; // @[pla.scala:81:23]
wire decoded_addr_39_2 = decoded_addr_decoded_44; // @[Decode.scala:50:77]
wire decoded_addr_decoded_45 = decoded_addr_decoded_decoded[106]; // @[pla.scala:81:23]
wire decoded_addr_51_2 = decoded_addr_decoded_45; // @[Decode.scala:50:77]
wire decoded_addr_decoded_46 = decoded_addr_decoded_decoded[105]; // @[pla.scala:81:23]
wire decoded_addr_110_2 = decoded_addr_decoded_46; // @[Decode.scala:50:77]
wire decoded_addr_decoded_47 = decoded_addr_decoded_decoded[104]; // @[pla.scala:81:23]
wire decoded_addr_92_2 = decoded_addr_decoded_47; // @[Decode.scala:50:77]
wire decoded_addr_decoded_48 = decoded_addr_decoded_decoded[103]; // @[pla.scala:81:23]
wire decoded_addr_82_2 = decoded_addr_decoded_48; // @[Decode.scala:50:77]
wire decoded_addr_decoded_49 = decoded_addr_decoded_decoded[102]; // @[pla.scala:81:23]
wire decoded_addr_67_2 = decoded_addr_decoded_49; // @[Decode.scala:50:77]
wire decoded_addr_decoded_50 = decoded_addr_decoded_decoded[101]; // @[pla.scala:81:23]
wire decoded_addr_106_2 = decoded_addr_decoded_50; // @[Decode.scala:50:77]
wire decoded_addr_decoded_51 = decoded_addr_decoded_decoded[100]; // @[pla.scala:81:23]
wire decoded_addr_124_2 = decoded_addr_decoded_51; // @[Decode.scala:50:77]
wire decoded_addr_decoded_52 = decoded_addr_decoded_decoded[99]; // @[pla.scala:81:23]
wire decoded_addr_24_2 = decoded_addr_decoded_52; // @[Decode.scala:50:77]
wire decoded_addr_decoded_53 = decoded_addr_decoded_decoded[98]; // @[pla.scala:81:23]
wire decoded_addr_126_2 = decoded_addr_decoded_53; // @[Decode.scala:50:77]
wire decoded_addr_decoded_54 = decoded_addr_decoded_decoded[97]; // @[pla.scala:81:23]
wire decoded_addr_26_2 = decoded_addr_decoded_54; // @[Decode.scala:50:77]
wire decoded_addr_decoded_55 = decoded_addr_decoded_decoded[96]; // @[pla.scala:81:23]
wire decoded_addr_130_2 = decoded_addr_decoded_55; // @[Decode.scala:50:77]
wire decoded_addr_decoded_56 = decoded_addr_decoded_decoded[95]; // @[pla.scala:81:23]
wire decoded_addr_7_2 = decoded_addr_decoded_56; // @[Decode.scala:50:77]
wire decoded_addr_decoded_57 = decoded_addr_decoded_decoded[94]; // @[pla.scala:81:23]
wire decoded_addr_62_2 = decoded_addr_decoded_57; // @[Decode.scala:50:77]
wire decoded_addr_decoded_58 = decoded_addr_decoded_decoded[93]; // @[pla.scala:81:23]
wire decoded_addr_78_2 = decoded_addr_decoded_58; // @[Decode.scala:50:77]
wire decoded_addr_decoded_59 = decoded_addr_decoded_decoded[92]; // @[pla.scala:81:23]
wire decoded_addr_46_2 = decoded_addr_decoded_59; // @[Decode.scala:50:77]
wire decoded_addr_decoded_60 = decoded_addr_decoded_decoded[91]; // @[pla.scala:81:23]
wire decoded_addr_113_2 = decoded_addr_decoded_60; // @[Decode.scala:50:77]
wire decoded_addr_decoded_61 = decoded_addr_decoded_decoded[90]; // @[pla.scala:81:23]
wire decoded_addr_60_2 = decoded_addr_decoded_61; // @[Decode.scala:50:77]
wire decoded_addr_decoded_62 = decoded_addr_decoded_decoded[89]; // @[pla.scala:81:23]
wire decoded_addr_93_2 = decoded_addr_decoded_62; // @[Decode.scala:50:77]
wire decoded_addr_decoded_63 = decoded_addr_decoded_decoded[88]; // @[pla.scala:81:23]
wire decoded_addr_150_2 = decoded_addr_decoded_63; // @[Decode.scala:50:77]
wire decoded_addr_decoded_64 = decoded_addr_decoded_decoded[87]; // @[pla.scala:81:23]
wire decoded_addr_14_2 = decoded_addr_decoded_64; // @[Decode.scala:50:77]
wire decoded_addr_decoded_65 = decoded_addr_decoded_decoded[86]; // @[pla.scala:81:23]
wire decoded_addr_21_2 = decoded_addr_decoded_65; // @[Decode.scala:50:77]
wire decoded_addr_decoded_66 = decoded_addr_decoded_decoded[85]; // @[pla.scala:81:23]
wire decoded_addr_33_2 = decoded_addr_decoded_66; // @[Decode.scala:50:77]
wire decoded_addr_decoded_67 = decoded_addr_decoded_decoded[84]; // @[pla.scala:81:23]
wire decoded_addr_19_2 = decoded_addr_decoded_67; // @[Decode.scala:50:77]
wire decoded_addr_decoded_68 = decoded_addr_decoded_decoded[83]; // @[pla.scala:81:23]
wire decoded_addr_135_2 = decoded_addr_decoded_68; // @[Decode.scala:50:77]
wire decoded_addr_decoded_69 = decoded_addr_decoded_decoded[82]; // @[pla.scala:81:23]
wire decoded_addr_151_2 = decoded_addr_decoded_69; // @[Decode.scala:50:77]
wire decoded_addr_decoded_70 = decoded_addr_decoded_decoded[81]; // @[pla.scala:81:23]
wire decoded_addr_50_2 = decoded_addr_decoded_70; // @[Decode.scala:50:77]
wire decoded_addr_decoded_71 = decoded_addr_decoded_decoded[80]; // @[pla.scala:81:23]
wire decoded_addr_75_2 = decoded_addr_decoded_71; // @[Decode.scala:50:77]
wire decoded_addr_decoded_72 = decoded_addr_decoded_decoded[79]; // @[pla.scala:81:23]
wire decoded_addr_103_2 = decoded_addr_decoded_72; // @[Decode.scala:50:77]
wire decoded_addr_decoded_73 = decoded_addr_decoded_decoded[78]; // @[pla.scala:81:23]
wire decoded_addr_85_2 = decoded_addr_decoded_73; // @[Decode.scala:50:77]
wire decoded_addr_decoded_74 = decoded_addr_decoded_decoded[77]; // @[pla.scala:81:23]
wire decoded_addr_45_2 = decoded_addr_decoded_74; // @[Decode.scala:50:77]
wire decoded_addr_decoded_75 = decoded_addr_decoded_decoded[76]; // @[pla.scala:81:23]
wire decoded_addr_64_2 = decoded_addr_decoded_75; // @[Decode.scala:50:77]
wire decoded_addr_decoded_76 = decoded_addr_decoded_decoded[75]; // @[pla.scala:81:23]
wire decoded_addr_122_2 = decoded_addr_decoded_76; // @[Decode.scala:50:77]
wire decoded_addr_decoded_77 = decoded_addr_decoded_decoded[74]; // @[pla.scala:81:23]
wire decoded_addr_30_2 = decoded_addr_decoded_77; // @[Decode.scala:50:77]
wire decoded_addr_decoded_78 = decoded_addr_decoded_decoded[73]; // @[pla.scala:81:23]
wire decoded_addr_5_2 = decoded_addr_decoded_78; // @[Decode.scala:50:77]
wire decoded_addr_decoded_79 = decoded_addr_decoded_decoded[72]; // @[pla.scala:81:23]
wire decoded_addr_32_2 = decoded_addr_decoded_79; // @[Decode.scala:50:77]
wire decoded_addr_decoded_80 = decoded_addr_decoded_decoded[71]; // @[pla.scala:81:23]
wire decoded_addr_145_2 = decoded_addr_decoded_80; // @[Decode.scala:50:77]
wire decoded_addr_decoded_81 = decoded_addr_decoded_decoded[70]; // @[pla.scala:81:23]
wire decoded_addr_119_2 = decoded_addr_decoded_81; // @[Decode.scala:50:77]
wire decoded_addr_decoded_82 = decoded_addr_decoded_decoded[69]; // @[pla.scala:81:23]
wire decoded_addr_63_2 = decoded_addr_decoded_82; // @[Decode.scala:50:77]
wire decoded_addr_decoded_83 = decoded_addr_decoded_decoded[68]; // @[pla.scala:81:23]
wire decoded_addr_108_2 = decoded_addr_decoded_83; // @[Decode.scala:50:77]
wire decoded_addr_decoded_84 = decoded_addr_decoded_decoded[67]; // @[pla.scala:81:23]
wire decoded_addr_89_2 = decoded_addr_decoded_84; // @[Decode.scala:50:77]
wire decoded_addr_decoded_85 = decoded_addr_decoded_decoded[66]; // @[pla.scala:81:23]
wire decoded_addr_115_2 = decoded_addr_decoded_85; // @[Decode.scala:50:77]
wire decoded_addr_decoded_86 = decoded_addr_decoded_decoded[65]; // @[pla.scala:81:23]
wire decoded_addr_73_2 = decoded_addr_decoded_86; // @[Decode.scala:50:77]
wire decoded_addr_decoded_87 = decoded_addr_decoded_decoded[64]; // @[pla.scala:81:23]
wire decoded_addr_53_2 = decoded_addr_decoded_87; // @[Decode.scala:50:77]
wire decoded_addr_decoded_88 = decoded_addr_decoded_decoded[63]; // @[pla.scala:81:23]
wire decoded_addr_149_2 = decoded_addr_decoded_88; // @[Decode.scala:50:77]
wire decoded_addr_decoded_89 = decoded_addr_decoded_decoded[62]; // @[pla.scala:81:23]
wire decoded_addr_41_2 = decoded_addr_decoded_89; // @[Decode.scala:50:77]
wire decoded_addr_decoded_90 = decoded_addr_decoded_decoded[61]; // @[pla.scala:81:23]
wire decoded_addr_56_2 = decoded_addr_decoded_90; // @[Decode.scala:50:77]
wire decoded_addr_decoded_91 = decoded_addr_decoded_decoded[60]; // @[pla.scala:81:23]
wire decoded_addr_37_2 = decoded_addr_decoded_91; // @[Decode.scala:50:77]
wire decoded_addr_decoded_92 = decoded_addr_decoded_decoded[59]; // @[pla.scala:81:23]
wire decoded_addr_80_2 = decoded_addr_decoded_92; // @[Decode.scala:50:77]
wire decoded_addr_decoded_93 = decoded_addr_decoded_decoded[58]; // @[pla.scala:81:23]
wire decoded_addr_97_2 = decoded_addr_decoded_93; // @[Decode.scala:50:77]
wire decoded_addr_decoded_94 = decoded_addr_decoded_decoded[57]; // @[pla.scala:81:23]
wire decoded_addr_4_2 = decoded_addr_decoded_94; // @[Decode.scala:50:77]
wire decoded_addr_decoded_95 = decoded_addr_decoded_decoded[56]; // @[pla.scala:81:23]
wire decoded_addr_102_2 = decoded_addr_decoded_95; // @[Decode.scala:50:77]
wire decoded_addr_decoded_96 = decoded_addr_decoded_decoded[55]; // @[pla.scala:81:23]
wire decoded_addr_121_2 = decoded_addr_decoded_96; // @[Decode.scala:50:77]
wire decoded_addr_decoded_97 = decoded_addr_decoded_decoded[54]; // @[pla.scala:81:23]
wire decoded_addr_22_2 = decoded_addr_decoded_97; // @[Decode.scala:50:77]
wire decoded_addr_decoded_98 = decoded_addr_decoded_decoded[53]; // @[pla.scala:81:23]
wire decoded_addr_141_2 = decoded_addr_decoded_98; // @[Decode.scala:50:77]
wire decoded_addr_decoded_99 = decoded_addr_decoded_decoded[52]; // @[pla.scala:81:23]
wire decoded_addr_11_2 = decoded_addr_decoded_99; // @[Decode.scala:50:77]
wire decoded_addr_decoded_100 = decoded_addr_decoded_decoded[51]; // @[pla.scala:81:23]
wire decoded_addr_136_2 = decoded_addr_decoded_100; // @[Decode.scala:50:77]
wire decoded_addr_decoded_101 = decoded_addr_decoded_decoded[50]; // @[pla.scala:81:23]
wire decoded_addr_12_2 = decoded_addr_decoded_101; // @[Decode.scala:50:77]
wire decoded_addr_decoded_102 = decoded_addr_decoded_decoded[49]; // @[pla.scala:81:23]
wire decoded_addr_65_2 = decoded_addr_decoded_102; // @[Decode.scala:50:77]
wire decoded_addr_decoded_103 = decoded_addr_decoded_decoded[48]; // @[pla.scala:81:23]
wire decoded_addr_87_2 = decoded_addr_decoded_103; // @[Decode.scala:50:77]
wire decoded_addr_decoded_104 = decoded_addr_decoded_decoded[47]; // @[pla.scala:81:23]
wire decoded_addr_47_2 = decoded_addr_decoded_104; // @[Decode.scala:50:77]
wire decoded_addr_decoded_105 = decoded_addr_decoded_decoded[46]; // @[pla.scala:81:23]
wire decoded_addr_107_2 = decoded_addr_decoded_105; // @[Decode.scala:50:77]
wire decoded_addr_decoded_106 = decoded_addr_decoded_decoded[45]; // @[pla.scala:81:23]
wire decoded_addr_58_2 = decoded_addr_decoded_106; // @[Decode.scala:50:77]
wire decoded_addr_decoded_107 = decoded_addr_decoded_decoded[44]; // @[pla.scala:81:23]
wire decoded_addr_88_2 = decoded_addr_decoded_107; // @[Decode.scala:50:77]
wire decoded_addr_decoded_108 = decoded_addr_decoded_decoded[43]; // @[pla.scala:81:23]
wire decoded_addr_144_2 = decoded_addr_decoded_108; // @[Decode.scala:50:77]
wire decoded_addr_decoded_109 = decoded_addr_decoded_decoded[42]; // @[pla.scala:81:23]
wire decoded_addr_13_2 = decoded_addr_decoded_109; // @[Decode.scala:50:77]
wire decoded_addr_decoded_110 = decoded_addr_decoded_decoded[41]; // @[pla.scala:81:23]
wire decoded_addr_35_2 = decoded_addr_decoded_110; // @[Decode.scala:50:77]
wire decoded_addr_decoded_111 = decoded_addr_decoded_decoded[40]; // @[pla.scala:81:23]
wire decoded_addr_2_2 = decoded_addr_decoded_111; // @[Decode.scala:50:77]
wire decoded_addr_decoded_112 = decoded_addr_decoded_decoded[39]; // @[pla.scala:81:23]
wire decoded_addr_66_2 = decoded_addr_decoded_112; // @[Decode.scala:50:77]
wire decoded_addr_decoded_113 = decoded_addr_decoded_decoded[38]; // @[pla.scala:81:23]
wire decoded_addr_42_2 = decoded_addr_decoded_113; // @[Decode.scala:50:77]
wire decoded_addr_decoded_114 = decoded_addr_decoded_decoded[37]; // @[pla.scala:81:23]
wire decoded_addr_61_2 = decoded_addr_decoded_114; // @[Decode.scala:50:77]
wire decoded_addr_decoded_115 = decoded_addr_decoded_decoded[36]; // @[pla.scala:81:23]
wire decoded_addr_48_2 = decoded_addr_decoded_115; // @[Decode.scala:50:77]
wire decoded_addr_decoded_116 = decoded_addr_decoded_decoded[35]; // @[pla.scala:81:23]
wire decoded_addr_44_2 = decoded_addr_decoded_116; // @[Decode.scala:50:77]
wire decoded_addr_decoded_117 = decoded_addr_decoded_decoded[34]; // @[pla.scala:81:23]
wire decoded_addr_15_2 = decoded_addr_decoded_117; // @[Decode.scala:50:77]
wire decoded_addr_decoded_118 = decoded_addr_decoded_decoded[33]; // @[pla.scala:81:23]
wire decoded_addr_147_2 = decoded_addr_decoded_118; // @[Decode.scala:50:77]
wire decoded_addr_decoded_119 = decoded_addr_decoded_decoded[32]; // @[pla.scala:81:23]
wire decoded_addr_94_2 = decoded_addr_decoded_119; // @[Decode.scala:50:77]
wire decoded_addr_decoded_120 = decoded_addr_decoded_decoded[31]; // @[pla.scala:81:23]
wire decoded_addr_6_2 = decoded_addr_decoded_120; // @[Decode.scala:50:77]
wire decoded_addr_decoded_121 = decoded_addr_decoded_decoded[30]; // @[pla.scala:81:23]
wire decoded_addr_28_2 = decoded_addr_decoded_121; // @[Decode.scala:50:77]
wire decoded_addr_decoded_122 = decoded_addr_decoded_decoded[29]; // @[pla.scala:81:23]
wire decoded_addr_25_2 = decoded_addr_decoded_122; // @[Decode.scala:50:77]
wire decoded_addr_decoded_123 = decoded_addr_decoded_decoded[28]; // @[pla.scala:81:23]
wire decoded_addr_139_2 = decoded_addr_decoded_123; // @[Decode.scala:50:77]
wire decoded_addr_decoded_124 = decoded_addr_decoded_decoded[27]; // @[pla.scala:81:23]
wire decoded_addr_125_2 = decoded_addr_decoded_124; // @[Decode.scala:50:77]
wire decoded_addr_decoded_125 = decoded_addr_decoded_decoded[26]; // @[pla.scala:81:23]
wire decoded_addr_23_2 = decoded_addr_decoded_125; // @[Decode.scala:50:77]
wire decoded_addr_decoded_126 = decoded_addr_decoded_decoded[25]; // @[pla.scala:81:23]
wire decoded_addr_69_2 = decoded_addr_decoded_126; // @[Decode.scala:50:77]
wire decoded_addr_decoded_127 = decoded_addr_decoded_decoded[24]; // @[pla.scala:81:23]
wire decoded_addr_143_2 = decoded_addr_decoded_127; // @[Decode.scala:50:77]
wire decoded_addr_decoded_128 = decoded_addr_decoded_decoded[23]; // @[pla.scala:81:23]
wire decoded_addr_9_2 = decoded_addr_decoded_128; // @[Decode.scala:50:77]
wire decoded_addr_decoded_129 = decoded_addr_decoded_decoded[22]; // @[pla.scala:81:23]
wire decoded_addr_105_2 = decoded_addr_decoded_129; // @[Decode.scala:50:77]
wire decoded_addr_decoded_130 = decoded_addr_decoded_decoded[21]; // @[pla.scala:81:23]
wire decoded_addr_8_2 = decoded_addr_decoded_130; // @[Decode.scala:50:77]
wire decoded_addr_decoded_131 = decoded_addr_decoded_decoded[20]; // @[pla.scala:81:23]
wire decoded_addr_127_2 = decoded_addr_decoded_131; // @[Decode.scala:50:77]
wire decoded_addr_decoded_132 = decoded_addr_decoded_decoded[19]; // @[pla.scala:81:23]
wire decoded_addr_86_2 = decoded_addr_decoded_132; // @[Decode.scala:50:77]
wire decoded_addr_decoded_133 = decoded_addr_decoded_decoded[18]; // @[pla.scala:81:23]
wire decoded_addr_54_2 = decoded_addr_decoded_133; // @[Decode.scala:50:77]
wire decoded_addr_decoded_134 = decoded_addr_decoded_decoded[17]; // @[pla.scala:81:23]
wire decoded_addr_20_2 = decoded_addr_decoded_134; // @[Decode.scala:50:77]
wire decoded_addr_decoded_135 = decoded_addr_decoded_decoded[16]; // @[pla.scala:81:23]
wire decoded_addr_137_2 = decoded_addr_decoded_135; // @[Decode.scala:50:77]
wire decoded_addr_decoded_136 = decoded_addr_decoded_decoded[15]; // @[pla.scala:81:23]
wire decoded_addr_116_2 = decoded_addr_decoded_136; // @[Decode.scala:50:77]
wire decoded_addr_decoded_137 = decoded_addr_decoded_decoded[14]; // @[pla.scala:81:23]
wire decoded_addr_43_2 = decoded_addr_decoded_137; // @[Decode.scala:50:77]
wire decoded_addr_decoded_138 = decoded_addr_decoded_decoded[13]; // @[pla.scala:81:23]
wire decoded_addr_71_2 = decoded_addr_decoded_138; // @[Decode.scala:50:77]
wire decoded_addr_decoded_139 = decoded_addr_decoded_decoded[12]; // @[pla.scala:81:23]
wire decoded_addr_111_2 = decoded_addr_decoded_139; // @[Decode.scala:50:77]
wire decoded_addr_decoded_140 = decoded_addr_decoded_decoded[11]; // @[pla.scala:81:23]
wire decoded_addr_142_2 = decoded_addr_decoded_140; // @[Decode.scala:50:77]
wire decoded_addr_decoded_141 = decoded_addr_decoded_decoded[10]; // @[pla.scala:81:23]
wire decoded_addr_34_2 = decoded_addr_decoded_141; // @[Decode.scala:50:77]
wire decoded_addr_decoded_142 = decoded_addr_decoded_decoded[9]; // @[pla.scala:81:23]
wire decoded_addr_40_2 = decoded_addr_decoded_142; // @[Decode.scala:50:77]
wire decoded_addr_decoded_143 = decoded_addr_decoded_decoded[8]; // @[pla.scala:81:23]
wire decoded_addr_81_2 = decoded_addr_decoded_143; // @[Decode.scala:50:77]
wire decoded_addr_decoded_144 = decoded_addr_decoded_decoded[7]; // @[pla.scala:81:23]
wire decoded_addr_99_2 = decoded_addr_decoded_144; // @[Decode.scala:50:77]
wire decoded_addr_decoded_145 = decoded_addr_decoded_decoded[6]; // @[pla.scala:81:23]
wire decoded_addr_76_2 = decoded_addr_decoded_145; // @[Decode.scala:50:77]
wire decoded_addr_decoded_146 = decoded_addr_decoded_decoded[5]; // @[pla.scala:81:23]
wire decoded_addr_118_2 = decoded_addr_decoded_146; // @[Decode.scala:50:77]
wire decoded_addr_decoded_147 = decoded_addr_decoded_decoded[4]; // @[pla.scala:81:23]
wire decoded_addr_18_2 = decoded_addr_decoded_147; // @[Decode.scala:50:77]
wire decoded_addr_decoded_148 = decoded_addr_decoded_decoded[3]; // @[pla.scala:81:23]
wire decoded_addr_3_2 = decoded_addr_decoded_148; // @[Decode.scala:50:77]
wire decoded_addr_decoded_149 = decoded_addr_decoded_decoded[2]; // @[pla.scala:81:23]
wire decoded_addr_129_2 = decoded_addr_decoded_149; // @[Decode.scala:50:77]
wire decoded_addr_decoded_150 = decoded_addr_decoded_decoded[1]; // @[pla.scala:81:23]
wire decoded_addr_38_2 = decoded_addr_decoded_150; // @[Decode.scala:50:77]
wire decoded_addr_decoded_151 = decoded_addr_decoded_decoded[0]; // @[pla.scala:81:23]
wire decoded_addr_96_2 = decoded_addr_decoded_151; // @[Decode.scala:50:77]
wire _wdata_T = io_rw_cmd_0[1]; // @[CSR.scala:377:7, :1643:13]
wire _new_mip_T_1 = io_rw_cmd_0[1]; // @[CSR.scala:377:7, :1643:13]
wire [63:0] _wdata_T_1 = _wdata_T ? io_rw_rdata_0 : 64'h0; // @[CSR.scala:377:7, :1643:{9,13}]
wire [63:0] _wdata_T_2 = _wdata_T_1 | io_rw_wdata_0; // @[CSR.scala:377:7, :1643:{9,30}]
wire [1:0] _wdata_T_3 = io_rw_cmd_0[1:0]; // @[CSR.scala:377:7, :1643:49]
wire [1:0] _new_mip_T_4 = io_rw_cmd_0[1:0]; // @[CSR.scala:377:7, :1643:49]
wire _wdata_T_4 = &_wdata_T_3; // @[CSR.scala:1643:{49,55}]
wire [63:0] _wdata_T_5 = _wdata_T_4 ? io_rw_wdata_0 : 64'h0; // @[CSR.scala:377:7, :1643:{45,55}]
wire [63:0] _wdata_T_6 = ~_wdata_T_5; // @[CSR.scala:1643:{41,45}]
assign wdata = _wdata_T_2 & _wdata_T_6; // @[CSR.scala:1643:{30,39,41}]
assign io_customCSRs_0_wdata_0 = wdata; // @[CSR.scala:377:7, :1643:39]
assign io_customCSRs_1_wdata_0 = wdata; // @[CSR.scala:377:7, :1643:39]
assign io_customCSRs_2_wdata_0 = wdata; // @[CSR.scala:377:7, :1643:39]
assign io_customCSRs_3_wdata_0 = wdata; // @[CSR.scala:377:7, :1643:39]
wire [63:0] _new_satp_WIRE = wdata; // @[CSR.scala:1355:40, :1643:39]
wire [63:0] _new_envcfg_WIRE = wdata; // @[CSR.scala:137:36, :1643:39]
wire [63:0] _new_envcfg_WIRE_1 = wdata; // @[CSR.scala:137:36, :1643:39]
wire [63:0] _newCfg_T = wdata; // @[CSR.scala:1491:29, :1643:39]
wire system_insn = io_rw_cmd_0 == 3'h4; // @[CSR.scala:377:7, :876:31]
wire [31:0] _insn_T = {io_rw_addr_0, 20'h0}; // @[CSR.scala:377:7, :892:44]
wire [31:0] insn = {_insn_T[31:7], _insn_T[6:0] | 7'h73}; // @[CSR.scala:892:{30,44}]
wire [31:0] decoded_plaInput = insn; // @[pla.scala:77:22]
wire [31:0] decoded_invInputs = ~decoded_plaInput; // @[pla.scala:77:22, :78:21]
wire [8:0] decoded_invMatrixOutputs; // @[pla.scala:120:37]
wire [8:0] decoded; // @[pla.scala:81:23]
wire decoded_andMatrixOutputs_andMatrixInput_0 = decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1 = decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_1 = decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_2 = decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_2_1 = decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_2 = decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_1 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_2_2 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_3 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_5 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_1 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_2 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_2_3 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_2_5 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_5 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_5_1 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_2 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_3 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_5 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_6 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_6_1 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_5_2 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_3 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_11_2 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_5 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_7 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_7_1 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_6_2 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_5_3 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_12 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_5_5 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8 = decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_1 = decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_1 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_7_3 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_14 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_10 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_10_1 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_2 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_3 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_15 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_5 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_11 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_11_1 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_2 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_3 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_16 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_5 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_6 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire [1:0] decoded_andMatrixOutputs_lo_lo_hi = {decoded_andMatrixOutputs_andMatrixInput_9, decoded_andMatrixOutputs_andMatrixInput_10}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_lo = {decoded_andMatrixOutputs_lo_lo_hi, decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi = {decoded_andMatrixOutputs_andMatrixInput_6, decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_hi = {decoded_andMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_andMatrixOutputs_lo = {decoded_andMatrixOutputs_lo_hi, decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_hi = {decoded_andMatrixOutputs_andMatrixInput_3, decoded_andMatrixOutputs_andMatrixInput_4}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_lo = {decoded_andMatrixOutputs_hi_lo_hi, decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi = {decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi = {decoded_andMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_andMatrixOutputs_hi = {decoded_andMatrixOutputs_hi_hi, decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53]
wire [11:0] _decoded_andMatrixOutputs_T = {decoded_andMatrixOutputs_hi, decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_6_2 = &_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}]
wire _decoded_orMatrixOutputs_T_6 = decoded_andMatrixOutputs_6_2; // @[pla.scala:98:70, :114:36]
wire decoded_andMatrixOutputs_andMatrixInput_0_1 = decoded_plaInput[20]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_andMatrixOutputs_andMatrixInput_10_1}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_lo_1 = {decoded_andMatrixOutputs_lo_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_hi_1 = {decoded_andMatrixOutputs_lo_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_8_1}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_andMatrixOutputs_lo_1 = {decoded_andMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_lo_1 = {decoded_andMatrixOutputs_hi_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_1 = {decoded_andMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_1}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_andMatrixOutputs_hi_1 = {decoded_andMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53]
wire [11:0] _decoded_andMatrixOutputs_T_1 = {decoded_andMatrixOutputs_hi_1, decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_4_2 = &_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}]
wire _decoded_orMatrixOutputs_T_5 = decoded_andMatrixOutputs_4_2; // @[pla.scala:98:70, :114:36]
wire decoded_andMatrixOutputs_andMatrixInput_0_2 = decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_0_4 = decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_7_2 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_6_3 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_13 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_6_5 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_andMatrixOutputs_lo_lo_2 = {decoded_andMatrixOutputs_andMatrixInput_8_2, decoded_andMatrixOutputs_andMatrixInput_9_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_5_2, decoded_andMatrixOutputs_andMatrixInput_6_2}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_hi_2 = {decoded_andMatrixOutputs_lo_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_andMatrixOutputs_lo_2 = {decoded_andMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_2 = {decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_andMatrixOutputs_andMatrixInput_4_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_2 = {decoded_andMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_2_2}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_andMatrixOutputs_hi_2 = {decoded_andMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53]
wire [9:0] _decoded_andMatrixOutputs_T_2 = {decoded_andMatrixOutputs_hi_2, decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_3_2 = &_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}]
wire decoded_andMatrixOutputs_andMatrixInput_0_3 = decoded_plaInput[22]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_0_5 = decoded_plaInput[22]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_andMatrixOutputs_lo_lo_3 = {decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_hi_3 = {decoded_andMatrixOutputs_lo_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_7_3}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_andMatrixOutputs_lo_3 = {decoded_andMatrixOutputs_lo_hi_3, decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_3 = {decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_andMatrixOutputs_andMatrixInput_4_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_3 = {decoded_andMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_2_3}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_andMatrixOutputs_hi_3 = {decoded_andMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53]
wire [9:0] _decoded_andMatrixOutputs_T_3 = {decoded_andMatrixOutputs_hi_3, decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_1_2 = &_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}]
wire _decoded_orMatrixOutputs_T_1 = decoded_andMatrixOutputs_1_2; // @[pla.scala:98:70, :114:36]
wire decoded_andMatrixOutputs_andMatrixInput_1_4 = decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_2_4 = decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_4 = decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_4 = decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_5_4 = decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_6_4 = decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_7_4 = decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_4 = decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_4 = decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_10_2 = decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_andMatrixOutputs_lo_lo_lo = {decoded_andMatrixOutputs_andMatrixInput_15, decoded_andMatrixOutputs_andMatrixInput_16}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_13, decoded_andMatrixOutputs_andMatrixInput_14}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoded_andMatrixOutputs_lo_lo_4 = {decoded_andMatrixOutputs_lo_lo_hi_2, decoded_andMatrixOutputs_lo_lo_lo}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_lo = {decoded_andMatrixOutputs_andMatrixInput_11_2, decoded_andMatrixOutputs_andMatrixInput_12}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_4 = {decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_andMatrixOutputs_andMatrixInput_10_2}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoded_andMatrixOutputs_lo_hi_4 = {decoded_andMatrixOutputs_lo_hi_hi_4, decoded_andMatrixOutputs_lo_hi_lo}; // @[pla.scala:98:53]
wire [7:0] decoded_andMatrixOutputs_lo_4 = {decoded_andMatrixOutputs_lo_hi_4, decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_lo = {decoded_andMatrixOutputs_andMatrixInput_7_4, decoded_andMatrixOutputs_andMatrixInput_8_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_5_4, decoded_andMatrixOutputs_andMatrixInput_6_4}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoded_andMatrixOutputs_hi_lo_4 = {decoded_andMatrixOutputs_hi_lo_hi_2, decoded_andMatrixOutputs_hi_lo_lo}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_lo = {decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_andMatrixOutputs_andMatrixInput_4_4}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_hi = {decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_hi_4 = {decoded_andMatrixOutputs_hi_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2_4}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_andMatrixOutputs_hi_hi_4 = {decoded_andMatrixOutputs_hi_hi_hi_4, decoded_andMatrixOutputs_hi_hi_lo}; // @[pla.scala:98:53]
wire [8:0] decoded_andMatrixOutputs_hi_4 = {decoded_andMatrixOutputs_hi_hi_4, decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53]
wire [16:0] _decoded_andMatrixOutputs_T_4 = {decoded_andMatrixOutputs_hi_4, decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_0_2 = &_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}]
wire _decoded_orMatrixOutputs_T = decoded_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36]
wire decoded_andMatrixOutputs_andMatrixInput_7_5 = decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_andMatrixOutputs_lo_lo_5 = {decoded_andMatrixOutputs_andMatrixInput_8_5, decoded_andMatrixOutputs_andMatrixInput_9_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_5_5, decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_hi_5 = {decoded_andMatrixOutputs_lo_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_andMatrixOutputs_lo_5 = {decoded_andMatrixOutputs_lo_hi_5, decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_5 = {decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_5 = {decoded_andMatrixOutputs_hi_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_andMatrixOutputs_hi_5 = {decoded_andMatrixOutputs_hi_hi_5, decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53]
wire [9:0] _decoded_andMatrixOutputs_T_5 = {decoded_andMatrixOutputs_hi_5, decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_5_2 = &_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}]
wire _decoded_orMatrixOutputs_T_2 = decoded_andMatrixOutputs_5_2; // @[pla.scala:98:70, :114:36]
wire decoded_andMatrixOutputs_andMatrixInput_0_6 = decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire [1:0] _decoded_andMatrixOutputs_T_6 = {decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :91:29, :98:53]
wire decoded_andMatrixOutputs_2_2 = &_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}]
wire [1:0] _decoded_orMatrixOutputs_T_3 = {decoded_andMatrixOutputs_3_2, decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19]
wire _decoded_orMatrixOutputs_T_4 = |_decoded_orMatrixOutputs_T_3; // @[pla.scala:114:{19,36}]
wire [1:0] decoded_orMatrixOutputs_lo_hi = {_decoded_orMatrixOutputs_T, 1'h0}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoded_orMatrixOutputs_lo = {decoded_orMatrixOutputs_lo_hi, 2'h0}; // @[pla.scala:102:36]
wire [1:0] decoded_orMatrixOutputs_hi_lo = {_decoded_orMatrixOutputs_T_2, _decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_orMatrixOutputs_hi_hi_hi = {_decoded_orMatrixOutputs_T_6, _decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_orMatrixOutputs_hi_hi = {decoded_orMatrixOutputs_hi_hi_hi, _decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_orMatrixOutputs_hi = {decoded_orMatrixOutputs_hi_hi, decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:102:36]
wire [8:0] decoded_orMatrixOutputs = {decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo}; // @[pla.scala:102:36]
wire _decoded_invMatrixOutputs_T = decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_1 = decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_2 = decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_3 = decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_4 = decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_5 = decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_6 = decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_7 = decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_8 = decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31]
wire [1:0] decoded_invMatrixOutputs_lo_lo = {_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_invMatrixOutputs_lo_hi = {_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31]
wire [3:0] decoded_invMatrixOutputs_lo = {decoded_invMatrixOutputs_lo_hi, decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_invMatrixOutputs_hi_lo = {_decoded_invMatrixOutputs_T_5, _decoded_invMatrixOutputs_T_4}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_invMatrixOutputs_hi_hi_hi = {_decoded_invMatrixOutputs_T_8, _decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_invMatrixOutputs_hi_hi = {decoded_invMatrixOutputs_hi_hi_hi, _decoded_invMatrixOutputs_T_6}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_invMatrixOutputs_hi = {decoded_invMatrixOutputs_hi_hi, decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37]
assign decoded_invMatrixOutputs = {decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37]
assign decoded = decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37]
wire insn_call = system_insn & decoded[8]; // @[pla.scala:81:23]
wire insn_break = system_insn & decoded[7]; // @[pla.scala:81:23]
wire insn_ret = system_insn & decoded[6]; // @[pla.scala:81:23]
wire insn_cease = system_insn & decoded[5]; // @[pla.scala:81:23]
wire insn_wfi = system_insn & decoded[4]; // @[pla.scala:81:23]
wire [11:0] addr = io_decode_0_inst_0[31:20]; // @[CSR.scala:377:7, :897:27]
wire [11:0] io_decode_0_fp_csr_plaInput = addr; // @[pla.scala:77:22]
wire [11:0] io_decode_0_vector_csr_plaInput = addr; // @[pla.scala:77:22]
wire [11:0] io_decode_0_read_illegal_plaInput = addr; // @[pla.scala:77:22]
wire [11:0] io_decode_0_read_illegal_plaInput_1 = addr; // @[pla.scala:77:22]
wire [31:0] decoded_invInputs_1 = ~decoded_plaInput_1; // @[pla.scala:77:22, :78:21]
wire [8:0] decoded_invMatrixOutputs_1; // @[pla.scala:120:37]
wire [8:0] decoded_1; // @[pla.scala:81:23]
wire decoded_andMatrixOutputs_andMatrixInput_0_7 = decoded_invInputs_1[20]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_7 = decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_8 = decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_2_6 = decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_2_7 = decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_9 = decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_6 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_7 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_2_8 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_10 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_12 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_6 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_7 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_8 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_2_9 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_2_11 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_5_6 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_5_7 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_8 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_9 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_11 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_6_6 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_6_7 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_5_8 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_9 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_11_5 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_11 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_7_6 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_7_7 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_6_8 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_5_9 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_12_1 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_5_11 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_6 = decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_7 = decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_6 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_7 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_7_9 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_14_1 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_10_3 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_10_4 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_8 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_9 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_15_1 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_11 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_11_3 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_11_4 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_8 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_9 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_16_1 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_11 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_13 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29]
wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_andMatrixOutputs_andMatrixInput_10_3}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_lo_6 = {decoded_andMatrixOutputs_lo_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_6 = {decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_hi_6 = {decoded_andMatrixOutputs_lo_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_8_6}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_andMatrixOutputs_lo_6 = {decoded_andMatrixOutputs_lo_hi_6, decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_lo_6 = {decoded_andMatrixOutputs_hi_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_6 = {decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_6 = {decoded_andMatrixOutputs_hi_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_andMatrixOutputs_hi_6 = {decoded_andMatrixOutputs_hi_hi_6, decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53]
wire [11:0] _decoded_andMatrixOutputs_T_7 = {decoded_andMatrixOutputs_hi_6, decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_6_2_1 = &_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}]
wire _decoded_orMatrixOutputs_T_13 = decoded_andMatrixOutputs_6_2_1; // @[pla.scala:98:70, :114:36]
wire decoded_andMatrixOutputs_andMatrixInput_0_8 = decoded_plaInput_1[20]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_4 = {decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_andMatrixOutputs_andMatrixInput_10_4}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_lo_7 = {decoded_andMatrixOutputs_lo_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_7 = {decoded_andMatrixOutputs_andMatrixInput_6_7, decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_hi_7 = {decoded_andMatrixOutputs_lo_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_8_7}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_andMatrixOutputs_lo_7 = {decoded_andMatrixOutputs_lo_hi_7, decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_4 = {decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_lo_7 = {decoded_andMatrixOutputs_hi_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_5_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_7 = {decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_7 = {decoded_andMatrixOutputs_hi_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_andMatrixOutputs_hi_7 = {decoded_andMatrixOutputs_hi_hi_7, decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53]
wire [11:0] _decoded_andMatrixOutputs_T_8 = {decoded_andMatrixOutputs_hi_7, decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_4_2_1 = &_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}]
wire _decoded_orMatrixOutputs_T_12 = decoded_andMatrixOutputs_4_2_1; // @[pla.scala:98:70, :114:36]
wire decoded_andMatrixOutputs_andMatrixInput_0_9 = decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_0_11 = decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_7_8 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_6_9 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_13_1 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_6_11 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_andMatrixOutputs_lo_lo_8 = {decoded_andMatrixOutputs_andMatrixInput_8_8, decoded_andMatrixOutputs_andMatrixInput_9_8}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_8 = {decoded_andMatrixOutputs_andMatrixInput_5_8, decoded_andMatrixOutputs_andMatrixInput_6_8}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_hi_8 = {decoded_andMatrixOutputs_lo_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_andMatrixOutputs_lo_8 = {decoded_andMatrixOutputs_lo_hi_8, decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_8 = {decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_andMatrixOutputs_andMatrixInput_4_8}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_8 = {decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_8 = {decoded_andMatrixOutputs_hi_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_2_8}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_andMatrixOutputs_hi_8 = {decoded_andMatrixOutputs_hi_hi_8, decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53]
wire [9:0] _decoded_andMatrixOutputs_T_9 = {decoded_andMatrixOutputs_hi_8, decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_3_2_1 = &_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}]
wire decoded_andMatrixOutputs_andMatrixInput_0_10 = decoded_plaInput_1[22]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_0_12 = decoded_plaInput_1[22]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_andMatrixOutputs_lo_lo_9 = {decoded_andMatrixOutputs_andMatrixInput_8_9, decoded_andMatrixOutputs_andMatrixInput_9_9}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_9 = {decoded_andMatrixOutputs_andMatrixInput_5_9, decoded_andMatrixOutputs_andMatrixInput_6_9}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_hi_9 = {decoded_andMatrixOutputs_lo_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_7_9}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_andMatrixOutputs_lo_9 = {decoded_andMatrixOutputs_lo_hi_9, decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_9 = {decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_andMatrixOutputs_andMatrixInput_4_9}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_9 = {decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_9 = {decoded_andMatrixOutputs_hi_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_2_9}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_andMatrixOutputs_hi_9 = {decoded_andMatrixOutputs_hi_hi_9, decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53]
wire [9:0] _decoded_andMatrixOutputs_T_10 = {decoded_andMatrixOutputs_hi_9, decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_1_2_1 = &_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}]
wire _decoded_orMatrixOutputs_T_8 = decoded_andMatrixOutputs_1_2_1; // @[pla.scala:98:70, :114:36]
wire decoded_andMatrixOutputs_andMatrixInput_1_11 = decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_2_10 = decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_10 = decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_10 = decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_5_10 = decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_6_10 = decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_7_10 = decoded_invInputs_1[7]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_10 = decoded_invInputs_1[8]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_10 = decoded_invInputs_1[9]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_10_5 = decoded_plaInput_1[25]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_andMatrixOutputs_lo_lo_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_15_1, decoded_andMatrixOutputs_andMatrixInput_16_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_13_1, decoded_andMatrixOutputs_andMatrixInput_14_1}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoded_andMatrixOutputs_lo_lo_10 = {decoded_andMatrixOutputs_lo_lo_hi_5, decoded_andMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_11_5, decoded_andMatrixOutputs_andMatrixInput_12_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_10 = {decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_andMatrixOutputs_andMatrixInput_10_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoded_andMatrixOutputs_lo_hi_10 = {decoded_andMatrixOutputs_lo_hi_hi_10, decoded_andMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:98:53]
wire [7:0] decoded_andMatrixOutputs_lo_10 = {decoded_andMatrixOutputs_lo_hi_10, decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_7_10, decoded_andMatrixOutputs_andMatrixInput_8_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_5_10, decoded_andMatrixOutputs_andMatrixInput_6_10}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoded_andMatrixOutputs_hi_lo_10 = {decoded_andMatrixOutputs_hi_lo_hi_5, decoded_andMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_andMatrixOutputs_andMatrixInput_4_10}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_hi_10 = {decoded_andMatrixOutputs_hi_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_10}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_andMatrixOutputs_hi_hi_10 = {decoded_andMatrixOutputs_hi_hi_hi_10, decoded_andMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:98:53]
wire [8:0] decoded_andMatrixOutputs_hi_10 = {decoded_andMatrixOutputs_hi_hi_10, decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53]
wire [16:0] _decoded_andMatrixOutputs_T_11 = {decoded_andMatrixOutputs_hi_10, decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_0_2_1 = &_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}]
wire _decoded_orMatrixOutputs_T_7 = decoded_andMatrixOutputs_0_2_1; // @[pla.scala:98:70, :114:36]
wire decoded_andMatrixOutputs_andMatrixInput_7_11 = decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_andMatrixOutputs_lo_lo_11 = {decoded_andMatrixOutputs_andMatrixInput_8_11, decoded_andMatrixOutputs_andMatrixInput_9_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_11 = {decoded_andMatrixOutputs_andMatrixInput_5_11, decoded_andMatrixOutputs_andMatrixInput_6_11}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_hi_11 = {decoded_andMatrixOutputs_lo_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_7_11}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_andMatrixOutputs_lo_11 = {decoded_andMatrixOutputs_lo_hi_11, decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_11 = {decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_andMatrixOutputs_andMatrixInput_4_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_11 = {decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_11 = {decoded_andMatrixOutputs_hi_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_2_11}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_andMatrixOutputs_hi_11 = {decoded_andMatrixOutputs_hi_hi_11, decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53]
wire [9:0] _decoded_andMatrixOutputs_T_12 = {decoded_andMatrixOutputs_hi_11, decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_5_2_1 = &_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}]
wire _decoded_orMatrixOutputs_T_9 = decoded_andMatrixOutputs_5_2_1; // @[pla.scala:98:70, :114:36]
wire decoded_andMatrixOutputs_andMatrixInput_0_13 = decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45]
wire [1:0] _decoded_andMatrixOutputs_T_13 = {decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :91:29, :98:53]
wire decoded_andMatrixOutputs_2_2_1 = &_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}]
wire [1:0] _decoded_orMatrixOutputs_T_10 = {decoded_andMatrixOutputs_3_2_1, decoded_andMatrixOutputs_2_2_1}; // @[pla.scala:98:70, :114:19]
wire _decoded_orMatrixOutputs_T_11 = |_decoded_orMatrixOutputs_T_10; // @[pla.scala:114:{19,36}]
wire [1:0] decoded_orMatrixOutputs_lo_hi_1 = {_decoded_orMatrixOutputs_T_7, 1'h0}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoded_orMatrixOutputs_lo_1 = {decoded_orMatrixOutputs_lo_hi_1, 2'h0}; // @[pla.scala:102:36]
wire [1:0] decoded_orMatrixOutputs_hi_lo_1 = {_decoded_orMatrixOutputs_T_9, _decoded_orMatrixOutputs_T_8}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_orMatrixOutputs_hi_hi_hi_1 = {_decoded_orMatrixOutputs_T_13, _decoded_orMatrixOutputs_T_12}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_orMatrixOutputs_hi_hi_1 = {decoded_orMatrixOutputs_hi_hi_hi_1, _decoded_orMatrixOutputs_T_11}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_orMatrixOutputs_hi_1 = {decoded_orMatrixOutputs_hi_hi_1, decoded_orMatrixOutputs_hi_lo_1}; // @[pla.scala:102:36]
wire [8:0] decoded_orMatrixOutputs_1 = {decoded_orMatrixOutputs_hi_1, decoded_orMatrixOutputs_lo_1}; // @[pla.scala:102:36]
wire _decoded_invMatrixOutputs_T_9 = decoded_orMatrixOutputs_1[0]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_10 = decoded_orMatrixOutputs_1[1]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_11 = decoded_orMatrixOutputs_1[2]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_12 = decoded_orMatrixOutputs_1[3]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_13 = decoded_orMatrixOutputs_1[4]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_14 = decoded_orMatrixOutputs_1[5]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_15 = decoded_orMatrixOutputs_1[6]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_16 = decoded_orMatrixOutputs_1[7]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_17 = decoded_orMatrixOutputs_1[8]; // @[pla.scala:102:36, :124:31]
wire [1:0] decoded_invMatrixOutputs_lo_lo_1 = {_decoded_invMatrixOutputs_T_10, _decoded_invMatrixOutputs_T_9}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_invMatrixOutputs_lo_hi_1 = {_decoded_invMatrixOutputs_T_12, _decoded_invMatrixOutputs_T_11}; // @[pla.scala:120:37, :124:31]
wire [3:0] decoded_invMatrixOutputs_lo_1 = {decoded_invMatrixOutputs_lo_hi_1, decoded_invMatrixOutputs_lo_lo_1}; // @[pla.scala:120:37]
wire [1:0] decoded_invMatrixOutputs_hi_lo_1 = {_decoded_invMatrixOutputs_T_14, _decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_invMatrixOutputs_hi_hi_hi_1 = {_decoded_invMatrixOutputs_T_17, _decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_invMatrixOutputs_hi_hi_1 = {decoded_invMatrixOutputs_hi_hi_hi_1, _decoded_invMatrixOutputs_T_15}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_invMatrixOutputs_hi_1 = {decoded_invMatrixOutputs_hi_hi_1, decoded_invMatrixOutputs_hi_lo_1}; // @[pla.scala:120:37]
assign decoded_invMatrixOutputs_1 = {decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1}; // @[pla.scala:120:37]
assign decoded_1 = decoded_invMatrixOutputs_1; // @[pla.scala:81:23, :120:37]
wire is_break = decoded_1[7]; // @[pla.scala:81:23]
wire is_ret = decoded_1[6]; // @[pla.scala:81:23]
wire is_wfi = decoded_1[4]; // @[pla.scala:81:23]
wire is_sfence = decoded_1[3]; // @[pla.scala:81:23]
wire is_hfence_vvma = decoded_1[2]; // @[pla.scala:81:23]
wire is_hfence_gvma = decoded_1[1]; // @[pla.scala:81:23]
wire is_hlsv = decoded_1[0]; // @[pla.scala:81:23]
wire _is_counter_T = addr > 12'hBFF; // @[package.scala:213:47]
wire _is_counter_T_1 = addr < 12'hC20; // @[package.scala:213:60]
wire _is_counter_T_2 = _is_counter_T & _is_counter_T_1; // @[package.scala:213:{47,55,60}]
wire _is_counter_T_3 = addr > 12'hC7F; // @[package.scala:213:47]
wire _is_counter_T_4 = addr < 12'hCA0; // @[package.scala:213:60]
wire _is_counter_T_5 = _is_counter_T_3 & _is_counter_T_4; // @[package.scala:213:{47,55,60}]
wire is_counter = _is_counter_T_2 | _is_counter_T_5; // @[package.scala:213:55]
wire _allow_wfi_T_1 = _allow_wfi_T; // @[CSR.scala:906:{42,61}]
wire _allow_wfi_T_2 = ~reg_mstatus_tw; // @[CSR.scala:395:28, :906:74]
wire _allow_wfi_T_6 = _allow_wfi_T_2; // @[CSR.scala:906:{74,90}]
wire _allow_wfi_T_3 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94]
wire allow_wfi = _allow_wfi_T_1 | _allow_wfi_T_6; // @[CSR.scala:906:{42,71,90}]
wire _allow_sfence_vma_T_1 = _allow_sfence_vma_T; // @[CSR.scala:907:{41,60}]
wire _GEN_4 = ~reg_mstatus_v & reg_mstatus_tvm; // @[CSR.scala:395:28, :907:77]
wire _allow_sfence_vma_T_2; // @[CSR.scala:907:77]
assign _allow_sfence_vma_T_2 = _GEN_4; // @[CSR.scala:907:77]
wire _allow_sfence_vma_T_6; // @[CSR.scala:907:77]
assign _allow_sfence_vma_T_6 = _GEN_4; // @[CSR.scala:907:77]
wire _allow_sfence_vma_T_10; // @[CSR.scala:907:77]
assign _allow_sfence_vma_T_10 = _GEN_4; // @[CSR.scala:907:77]
wire _allow_sfence_vma_T_3 = ~_allow_sfence_vma_T_2; // @[CSR.scala:907:{73,77}]
wire allow_sfence_vma = _allow_sfence_vma_T_1 | _allow_sfence_vma_T_3; // @[CSR.scala:907:{41,70,73}]
wire _allow_hfence_vvma_T = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :908:53]
wire _allow_hfence_vvma_T_1 = |reg_mstatus_prv; // @[CSR.scala:395:28, :908:88]
wire _allow_hfence_vvma_T_2 = _allow_hfence_vvma_T & _allow_hfence_vvma_T_1; // @[CSR.scala:908:{53,68,88}]
wire _allow_hlsv_T = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :909:46]
wire _allow_hlsv_T_1 = |reg_mstatus_prv; // @[CSR.scala:395:28, :908:88, :909:81]
wire _allow_hlsv_T_2 = _allow_hlsv_T_1; // @[CSR.scala:909:{81,92}]
wire _allow_hlsv_T_3 = _allow_hlsv_T & _allow_hlsv_T_2; // @[CSR.scala:909:{46,61,92}]
wire _allow_sret_T_1 = _allow_sret_T; // @[CSR.scala:910:{43,62}]
wire _GEN_5 = ~reg_mstatus_v & reg_mstatus_tsr; // @[CSR.scala:395:28, :907:77, :910:79]
wire _allow_sret_T_2; // @[CSR.scala:910:79]
assign _allow_sret_T_2 = _GEN_5; // @[CSR.scala:910:79]
wire _allow_sret_T_6; // @[CSR.scala:910:79]
assign _allow_sret_T_6 = _GEN_5; // @[CSR.scala:910:79]
wire _allow_sret_T_10; // @[CSR.scala:910:79]
assign _allow_sret_T_10 = _GEN_5; // @[CSR.scala:910:79]
wire _allow_sret_T_3 = ~_allow_sret_T_2; // @[CSR.scala:910:{75,79}]
wire allow_sret = _allow_sret_T_1 | _allow_sret_T_3; // @[CSR.scala:910:{43,72,75}]
wire [4:0] counter_addr = addr[4:0]; // @[CSR.scala:897:27, :911:28]
wire [31:0] _GEN_6 = {27'h0, counter_addr}; // @[CSR.scala:911:28, :912:70]
wire [31:0] _GEN_7 = read_mcounteren >> _GEN_6; // @[CSR.scala:532:14, :912:70]
wire [31:0] _allow_counter_T_1; // @[CSR.scala:912:70]
assign _allow_counter_T_1 = _GEN_7; // @[CSR.scala:912:70]
wire [31:0] _io_decode_0_virtual_access_illegal_T_3; // @[CSR.scala:945:36]
assign _io_decode_0_virtual_access_illegal_T_3 = _GEN_7; // @[CSR.scala:912:70, :945:36]
wire _allow_counter_T_2 = _allow_counter_T_1[0]; // @[CSR.scala:912:70]
wire _allow_counter_T_3 = _allow_counter_T | _allow_counter_T_2; // @[CSR.scala:912:{42,52,70}]
wire _allow_counter_T_5 = |reg_mstatus_prv; // @[CSR.scala:395:28, :908:88, :913:46]
wire _allow_counter_T_6 = _allow_counter_T_5; // @[CSR.scala:913:{27,46}]
wire [31:0] _GEN_8 = read_scounteren >> _GEN_6; // @[CSR.scala:536:14, :912:70, :913:75]
wire [31:0] _allow_counter_T_7; // @[CSR.scala:913:75]
assign _allow_counter_T_7 = _GEN_8; // @[CSR.scala:913:75]
wire [31:0] _io_decode_0_virtual_access_illegal_T_11; // @[CSR.scala:945:128]
assign _io_decode_0_virtual_access_illegal_T_11 = _GEN_8; // @[CSR.scala:913:75, :945:128]
wire _allow_counter_T_8 = _allow_counter_T_7[0]; // @[CSR.scala:913:75]
wire _allow_counter_T_9 = _allow_counter_T_6 | _allow_counter_T_8; // @[CSR.scala:913:{27,57,75}]
wire _allow_counter_T_10 = _allow_counter_T_3 & _allow_counter_T_9; // @[CSR.scala:912:{52,86}, :913:57]
wire allow_counter = _allow_counter_T_10; // @[CSR.scala:912:86, :913:91]
wire _allow_counter_T_12 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :914:30]
wire [31:0] _GEN_9 = 32'h0 >> _GEN_6; // @[CSR.scala:912:70, :914:63]
wire [31:0] _allow_counter_T_14; // @[CSR.scala:914:63]
assign _allow_counter_T_14 = _GEN_9; // @[CSR.scala:914:63]
wire [31:0] _io_decode_0_virtual_access_illegal_T_6; // @[CSR.scala:945:71]
assign _io_decode_0_virtual_access_illegal_T_6 = _GEN_9; // @[CSR.scala:914:63, :945:71]
wire _allow_counter_T_15 = _allow_counter_T_14[0]; // @[CSR.scala:914:63]
wire _GEN_10 = io_status_fs_0 == 2'h0; // @[CSR.scala:377:7, :915:39]
wire _io_decode_0_fp_illegal_T; // @[CSR.scala:915:39]
assign _io_decode_0_fp_illegal_T = _GEN_10; // @[CSR.scala:915:39]
wire _io_decode_1_fp_illegal_T; // @[CSR.scala:915:39]
assign _io_decode_1_fp_illegal_T = _GEN_10; // @[CSR.scala:915:39]
wire _io_decode_2_fp_illegal_T; // @[CSR.scala:915:39]
assign _io_decode_2_fp_illegal_T = _GEN_10; // @[CSR.scala:915:39]
wire _io_decode_0_fp_illegal_T_3 = _io_decode_0_fp_illegal_T; // @[CSR.scala:915:{39,47}]
assign _io_decode_0_fp_illegal_T_6 = _io_decode_0_fp_illegal_T_3; // @[CSR.scala:915:{47,91}]
assign io_decode_0_fp_illegal_0 = _io_decode_0_fp_illegal_T_6; // @[CSR.scala:377:7, :915:91]
wire _io_decode_0_vector_illegal_T_2 = reg_mstatus_v & _io_decode_0_vector_illegal_T_1; // @[CSR.scala:395:28, :916:{68,87}]
wire [11:0] io_decode_0_fp_csr_invInputs = ~io_decode_0_fp_csr_plaInput; // @[pla.scala:77:22, :78:21]
wire io_decode_0_fp_csr_invMatrixOutputs; // @[pla.scala:124:31]
wire io_decode_0_fp_csr_plaOutput; // @[pla.scala:81:23]
assign _io_decode_0_fp_csr_T = io_decode_0_fp_csr_plaOutput; // @[pla.scala:81:23]
wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_0 = io_decode_0_fp_csr_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_1 = io_decode_0_fp_csr_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_2 = io_decode_0_fp_csr_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_3 = io_decode_0_fp_csr_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire [1:0] io_decode_0_fp_csr_andMatrixOutputs_lo = {io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_2, io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] io_decode_0_fp_csr_andMatrixOutputs_hi = {io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_0, io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53]
wire [3:0] _io_decode_0_fp_csr_andMatrixOutputs_T = {io_decode_0_fp_csr_andMatrixOutputs_hi, io_decode_0_fp_csr_andMatrixOutputs_lo}; // @[pla.scala:98:53]
wire io_decode_0_fp_csr_andMatrixOutputs_0_2 = &_io_decode_0_fp_csr_andMatrixOutputs_T; // @[pla.scala:98:{53,70}]
wire io_decode_0_fp_csr_orMatrixOutputs = io_decode_0_fp_csr_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36]
assign io_decode_0_fp_csr_invMatrixOutputs = io_decode_0_fp_csr_orMatrixOutputs; // @[pla.scala:114:36, :124:31]
assign io_decode_0_fp_csr_plaOutput = io_decode_0_fp_csr_invMatrixOutputs; // @[pla.scala:81:23, :124:31]
assign io_decode_0_fp_csr_0 = _io_decode_0_fp_csr_T; // @[Decode.scala:55:116]
wire [11:0] io_decode_0_vector_csr_invInputs = ~io_decode_0_vector_csr_plaInput; // @[pla.scala:77:22, :78:21]
wire [1:0] _csr_addr_legal_T = addr[9:8]; // @[CSR.scala:190:36, :897:27]
wire [1:0] _csr_addr_legal_T_6 = addr[9:8]; // @[CSR.scala:190:36, :897:27]
wire [1:0] _io_decode_0_virtual_access_illegal_T_1 = addr[9:8]; // @[CSR.scala:190:36, :897:27]
wire [1:0] _io_decode_0_virtual_access_illegal_T_18 = addr[9:8]; // @[CSR.scala:190:36, :897:27]
wire [1:0] _io_decode_0_virtual_system_illegal_T_9 = addr[9:8]; // @[CSR.scala:190:36, :897:27]
wire _csr_addr_legal_T_1 = reg_mstatus_prv >= _csr_addr_legal_T; // @[CSR.scala:190:36, :395:28, :920:42]
wire csr_addr_legal = _csr_addr_legal_T_1; // @[CSR.scala:920:{42,60}]
wire _csr_addr_legal_T_2 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :921:28]
wire _csr_addr_legal_T_7 = _csr_addr_legal_T_6 == 2'h2; // @[CSR.scala:190:36, :921:92]
wire _csr_exists_T = addr == 12'h7A0; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_1 = addr == 12'h7A1; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_2 = addr == 12'h7A2; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_3 = addr == 12'h7A3; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_4 = addr == 12'h301; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_5 = addr == 12'h300; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_6 = addr == 12'h305; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_7 = addr == 12'h344; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_8 = addr == 12'h304; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_9 = addr == 12'h340; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_10 = addr == 12'h341; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_11 = addr == 12'h343; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_12 = addr == 12'h342; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_13 = addr == 12'hF14; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_14 = addr == 12'h7B0; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_15 = addr == 12'h7B1; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_16 = addr == 12'h7B2; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_17 = addr == 12'h1; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_18 = addr == 12'h2; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_19 = addr == 12'h3; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_20 = addr == 12'h320; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_21 = addr == 12'hB00; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_22 = addr == 12'hB02; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_23 = addr == 12'h323; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_24 = addr == 12'hB03; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_25 = addr == 12'hC03; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_26 = addr == 12'h324; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_27 = addr == 12'hB04; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_28 = addr == 12'hC04; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_29 = addr == 12'h325; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_30 = addr == 12'hB05; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_31 = addr == 12'hC05; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_32 = addr == 12'h326; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_33 = addr == 12'hB06; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_34 = addr == 12'hC06; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_35 = addr == 12'h327; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_36 = addr == 12'hB07; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_37 = addr == 12'hC07; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_38 = addr == 12'h328; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_39 = addr == 12'hB08; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_40 = addr == 12'hC08; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_41 = addr == 12'h329; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_42 = addr == 12'hB09; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_43 = addr == 12'hC09; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_44 = addr == 12'h32A; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_45 = addr == 12'hB0A; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_46 = addr == 12'hC0A; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_47 = addr == 12'h32B; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_48 = addr == 12'hB0B; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_49 = addr == 12'hC0B; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_50 = addr == 12'h32C; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_51 = addr == 12'hB0C; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_52 = addr == 12'hC0C; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_53 = addr == 12'h32D; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_54 = addr == 12'hB0D; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_55 = addr == 12'hC0D; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_56 = addr == 12'h32E; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_57 = addr == 12'hB0E; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_58 = addr == 12'hC0E; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_59 = addr == 12'h32F; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_60 = addr == 12'hB0F; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_61 = addr == 12'hC0F; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_62 = addr == 12'h330; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_63 = addr == 12'hB10; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_64 = addr == 12'hC10; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_65 = addr == 12'h331; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_66 = addr == 12'hB11; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_67 = addr == 12'hC11; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_68 = addr == 12'h332; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_69 = addr == 12'hB12; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_70 = addr == 12'hC12; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_71 = addr == 12'h333; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_72 = addr == 12'hB13; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_73 = addr == 12'hC13; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_74 = addr == 12'h334; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_75 = addr == 12'hB14; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_76 = addr == 12'hC14; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_77 = addr == 12'h335; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_78 = addr == 12'hB15; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_79 = addr == 12'hC15; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_80 = addr == 12'h336; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_81 = addr == 12'hB16; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_82 = addr == 12'hC16; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_83 = addr == 12'h337; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_84 = addr == 12'hB17; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_85 = addr == 12'hC17; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_86 = addr == 12'h338; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_87 = addr == 12'hB18; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_88 = addr == 12'hC18; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_89 = addr == 12'h339; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_90 = addr == 12'hB19; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_91 = addr == 12'hC19; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_92 = addr == 12'h33A; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_93 = addr == 12'hB1A; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_94 = addr == 12'hC1A; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_95 = addr == 12'h33B; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_96 = addr == 12'hB1B; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_97 = addr == 12'hC1B; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_98 = addr == 12'h33C; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_99 = addr == 12'hB1C; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_100 = addr == 12'hC1C; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_101 = addr == 12'h33D; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_102 = addr == 12'hB1D; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_103 = addr == 12'hC1D; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_104 = addr == 12'h33E; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_105 = addr == 12'hB1E; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_106 = addr == 12'hC1E; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_107 = addr == 12'h33F; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_108 = addr == 12'hB1F; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_109 = addr == 12'hC1F; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_110 = addr == 12'h306; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_111 = addr == 12'hC00; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_112 = addr == 12'hC02; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_113 = addr == 12'h30A; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_114 = addr == 12'h100; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_115 = addr == 12'h144; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_116 = addr == 12'h104; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_117 = addr == 12'h140; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_118 = addr == 12'h142; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_119 = addr == 12'h143; // @[CSR.scala:897:27, :899:93]
wire _GEN_11 = addr == 12'h180; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_120; // @[CSR.scala:899:93]
assign _csr_exists_T_120 = _GEN_11; // @[CSR.scala:899:93]
wire _io_decode_0_read_illegal_T_3; // @[CSR.scala:925:14]
assign _io_decode_0_read_illegal_T_3 = _GEN_11; // @[CSR.scala:899:93, :925:14]
wire _io_decode_0_virtual_access_illegal_T_24; // @[CSR.scala:947:12]
assign _io_decode_0_virtual_access_illegal_T_24 = _GEN_11; // @[CSR.scala:899:93, :947:12]
wire _csr_exists_T_121 = addr == 12'h141; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_122 = addr == 12'h105; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_123 = addr == 12'h106; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_124 = addr == 12'h303; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_125 = addr == 12'h302; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_126 = addr == 12'h10A; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_127 = addr == 12'h3A0; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_128 = addr == 12'h3A2; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_129 = addr == 12'h3B0; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_130 = addr == 12'h3B1; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_131 = addr == 12'h3B2; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_132 = addr == 12'h3B3; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_133 = addr == 12'h3B4; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_134 = addr == 12'h3B5; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_135 = addr == 12'h3B6; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_136 = addr == 12'h3B7; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_137 = addr == 12'h3B8; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_138 = addr == 12'h3B9; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_139 = addr == 12'h3BA; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_140 = addr == 12'h3BB; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_141 = addr == 12'h3BC; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_142 = addr == 12'h3BD; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_143 = addr == 12'h3BE; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_144 = addr == 12'h3BF; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_145 = addr == 12'h800; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_146 = addr == 12'h808; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_147 = addr == 12'h7C1; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_148 = addr == 12'hF12; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_149 = addr == 12'hF13; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_150 = addr == 12'hF11; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_151 = addr == 12'hF15; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_152 = _csr_exists_T | _csr_exists_T_1; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_153 = _csr_exists_T_152 | _csr_exists_T_2; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_154 = _csr_exists_T_153 | _csr_exists_T_3; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_155 = _csr_exists_T_154 | _csr_exists_T_4; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_156 = _csr_exists_T_155 | _csr_exists_T_5; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_157 = _csr_exists_T_156 | _csr_exists_T_6; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_158 = _csr_exists_T_157 | _csr_exists_T_7; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_159 = _csr_exists_T_158 | _csr_exists_T_8; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_160 = _csr_exists_T_159 | _csr_exists_T_9; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_161 = _csr_exists_T_160 | _csr_exists_T_10; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_162 = _csr_exists_T_161 | _csr_exists_T_11; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_163 = _csr_exists_T_162 | _csr_exists_T_12; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_164 = _csr_exists_T_163 | _csr_exists_T_13; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_165 = _csr_exists_T_164 | _csr_exists_T_14; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_166 = _csr_exists_T_165 | _csr_exists_T_15; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_167 = _csr_exists_T_166 | _csr_exists_T_16; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_168 = _csr_exists_T_167 | _csr_exists_T_17; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_169 = _csr_exists_T_168 | _csr_exists_T_18; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_170 = _csr_exists_T_169 | _csr_exists_T_19; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_171 = _csr_exists_T_170 | _csr_exists_T_20; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_172 = _csr_exists_T_171 | _csr_exists_T_21; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_173 = _csr_exists_T_172 | _csr_exists_T_22; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_174 = _csr_exists_T_173 | _csr_exists_T_23; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_175 = _csr_exists_T_174 | _csr_exists_T_24; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_176 = _csr_exists_T_175 | _csr_exists_T_25; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_177 = _csr_exists_T_176 | _csr_exists_T_26; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_178 = _csr_exists_T_177 | _csr_exists_T_27; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_179 = _csr_exists_T_178 | _csr_exists_T_28; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_180 = _csr_exists_T_179 | _csr_exists_T_29; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_181 = _csr_exists_T_180 | _csr_exists_T_30; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_182 = _csr_exists_T_181 | _csr_exists_T_31; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_183 = _csr_exists_T_182 | _csr_exists_T_32; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_184 = _csr_exists_T_183 | _csr_exists_T_33; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_185 = _csr_exists_T_184 | _csr_exists_T_34; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_186 = _csr_exists_T_185 | _csr_exists_T_35; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_187 = _csr_exists_T_186 | _csr_exists_T_36; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_188 = _csr_exists_T_187 | _csr_exists_T_37; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_189 = _csr_exists_T_188 | _csr_exists_T_38; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_190 = _csr_exists_T_189 | _csr_exists_T_39; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_191 = _csr_exists_T_190 | _csr_exists_T_40; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_192 = _csr_exists_T_191 | _csr_exists_T_41; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_193 = _csr_exists_T_192 | _csr_exists_T_42; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_194 = _csr_exists_T_193 | _csr_exists_T_43; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_195 = _csr_exists_T_194 | _csr_exists_T_44; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_196 = _csr_exists_T_195 | _csr_exists_T_45; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_197 = _csr_exists_T_196 | _csr_exists_T_46; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_198 = _csr_exists_T_197 | _csr_exists_T_47; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_199 = _csr_exists_T_198 | _csr_exists_T_48; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_200 = _csr_exists_T_199 | _csr_exists_T_49; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_201 = _csr_exists_T_200 | _csr_exists_T_50; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_202 = _csr_exists_T_201 | _csr_exists_T_51; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_203 = _csr_exists_T_202 | _csr_exists_T_52; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_204 = _csr_exists_T_203 | _csr_exists_T_53; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_205 = _csr_exists_T_204 | _csr_exists_T_54; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_206 = _csr_exists_T_205 | _csr_exists_T_55; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_207 = _csr_exists_T_206 | _csr_exists_T_56; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_208 = _csr_exists_T_207 | _csr_exists_T_57; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_209 = _csr_exists_T_208 | _csr_exists_T_58; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_210 = _csr_exists_T_209 | _csr_exists_T_59; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_211 = _csr_exists_T_210 | _csr_exists_T_60; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_212 = _csr_exists_T_211 | _csr_exists_T_61; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_213 = _csr_exists_T_212 | _csr_exists_T_62; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_214 = _csr_exists_T_213 | _csr_exists_T_63; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_215 = _csr_exists_T_214 | _csr_exists_T_64; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_216 = _csr_exists_T_215 | _csr_exists_T_65; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_217 = _csr_exists_T_216 | _csr_exists_T_66; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_218 = _csr_exists_T_217 | _csr_exists_T_67; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_219 = _csr_exists_T_218 | _csr_exists_T_68; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_220 = _csr_exists_T_219 | _csr_exists_T_69; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_221 = _csr_exists_T_220 | _csr_exists_T_70; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_222 = _csr_exists_T_221 | _csr_exists_T_71; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_223 = _csr_exists_T_222 | _csr_exists_T_72; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_224 = _csr_exists_T_223 | _csr_exists_T_73; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_225 = _csr_exists_T_224 | _csr_exists_T_74; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_226 = _csr_exists_T_225 | _csr_exists_T_75; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_227 = _csr_exists_T_226 | _csr_exists_T_76; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_228 = _csr_exists_T_227 | _csr_exists_T_77; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_229 = _csr_exists_T_228 | _csr_exists_T_78; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_230 = _csr_exists_T_229 | _csr_exists_T_79; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_231 = _csr_exists_T_230 | _csr_exists_T_80; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_232 = _csr_exists_T_231 | _csr_exists_T_81; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_233 = _csr_exists_T_232 | _csr_exists_T_82; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_234 = _csr_exists_T_233 | _csr_exists_T_83; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_235 = _csr_exists_T_234 | _csr_exists_T_84; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_236 = _csr_exists_T_235 | _csr_exists_T_85; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_237 = _csr_exists_T_236 | _csr_exists_T_86; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_238 = _csr_exists_T_237 | _csr_exists_T_87; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_239 = _csr_exists_T_238 | _csr_exists_T_88; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_240 = _csr_exists_T_239 | _csr_exists_T_89; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_241 = _csr_exists_T_240 | _csr_exists_T_90; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_242 = _csr_exists_T_241 | _csr_exists_T_91; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_243 = _csr_exists_T_242 | _csr_exists_T_92; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_244 = _csr_exists_T_243 | _csr_exists_T_93; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_245 = _csr_exists_T_244 | _csr_exists_T_94; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_246 = _csr_exists_T_245 | _csr_exists_T_95; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_247 = _csr_exists_T_246 | _csr_exists_T_96; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_248 = _csr_exists_T_247 | _csr_exists_T_97; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_249 = _csr_exists_T_248 | _csr_exists_T_98; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_250 = _csr_exists_T_249 | _csr_exists_T_99; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_251 = _csr_exists_T_250 | _csr_exists_T_100; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_252 = _csr_exists_T_251 | _csr_exists_T_101; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_253 = _csr_exists_T_252 | _csr_exists_T_102; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_254 = _csr_exists_T_253 | _csr_exists_T_103; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_255 = _csr_exists_T_254 | _csr_exists_T_104; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_256 = _csr_exists_T_255 | _csr_exists_T_105; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_257 = _csr_exists_T_256 | _csr_exists_T_106; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_258 = _csr_exists_T_257 | _csr_exists_T_107; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_259 = _csr_exists_T_258 | _csr_exists_T_108; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_260 = _csr_exists_T_259 | _csr_exists_T_109; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_261 = _csr_exists_T_260 | _csr_exists_T_110; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_262 = _csr_exists_T_261 | _csr_exists_T_111; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_263 = _csr_exists_T_262 | _csr_exists_T_112; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_264 = _csr_exists_T_263 | _csr_exists_T_113; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_265 = _csr_exists_T_264 | _csr_exists_T_114; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_266 = _csr_exists_T_265 | _csr_exists_T_115; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_267 = _csr_exists_T_266 | _csr_exists_T_116; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_268 = _csr_exists_T_267 | _csr_exists_T_117; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_269 = _csr_exists_T_268 | _csr_exists_T_118; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_270 = _csr_exists_T_269 | _csr_exists_T_119; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_271 = _csr_exists_T_270 | _csr_exists_T_120; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_272 = _csr_exists_T_271 | _csr_exists_T_121; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_273 = _csr_exists_T_272 | _csr_exists_T_122; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_274 = _csr_exists_T_273 | _csr_exists_T_123; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_275 = _csr_exists_T_274 | _csr_exists_T_124; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_276 = _csr_exists_T_275 | _csr_exists_T_125; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_277 = _csr_exists_T_276 | _csr_exists_T_126; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_278 = _csr_exists_T_277 | _csr_exists_T_127; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_279 = _csr_exists_T_278 | _csr_exists_T_128; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_280 = _csr_exists_T_279 | _csr_exists_T_129; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_281 = _csr_exists_T_280 | _csr_exists_T_130; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_282 = _csr_exists_T_281 | _csr_exists_T_131; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_283 = _csr_exists_T_282 | _csr_exists_T_132; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_284 = _csr_exists_T_283 | _csr_exists_T_133; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_285 = _csr_exists_T_284 | _csr_exists_T_134; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_286 = _csr_exists_T_285 | _csr_exists_T_135; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_287 = _csr_exists_T_286 | _csr_exists_T_136; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_288 = _csr_exists_T_287 | _csr_exists_T_137; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_289 = _csr_exists_T_288 | _csr_exists_T_138; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_290 = _csr_exists_T_289 | _csr_exists_T_139; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_291 = _csr_exists_T_290 | _csr_exists_T_140; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_292 = _csr_exists_T_291 | _csr_exists_T_141; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_293 = _csr_exists_T_292 | _csr_exists_T_142; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_294 = _csr_exists_T_293 | _csr_exists_T_143; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_295 = _csr_exists_T_294 | _csr_exists_T_144; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_296 = _csr_exists_T_295 | _csr_exists_T_145; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_297 = _csr_exists_T_296 | _csr_exists_T_146; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_298 = _csr_exists_T_297 | _csr_exists_T_147; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_299 = _csr_exists_T_298 | _csr_exists_T_148; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_300 = _csr_exists_T_299 | _csr_exists_T_149; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_301 = _csr_exists_T_300 | _csr_exists_T_150; // @[CSR.scala:899:{93,111}]
wire csr_exists = _csr_exists_T_301 | _csr_exists_T_151; // @[CSR.scala:899:{93,111}]
wire _io_decode_0_read_illegal_T = ~csr_addr_legal; // @[CSR.scala:920:60, :923:28]
wire _io_decode_0_read_illegal_T_1 = ~csr_exists; // @[CSR.scala:899:111, :924:7]
wire _io_decode_0_read_illegal_T_2 = _io_decode_0_read_illegal_T | _io_decode_0_read_illegal_T_1; // @[CSR.scala:923:{28,44}, :924:7]
wire _io_decode_0_read_illegal_T_4 = addr == 12'h680; // @[CSR.scala:897:27, :925:38]
wire _io_decode_0_read_illegal_T_5 = _io_decode_0_read_illegal_T_3 | _io_decode_0_read_illegal_T_4; // @[CSR.scala:925:{14,30,38}]
wire _io_decode_0_read_illegal_T_6 = ~allow_sfence_vma; // @[CSR.scala:907:70, :925:59]
wire _io_decode_0_read_illegal_T_7 = _io_decode_0_read_illegal_T_5 & _io_decode_0_read_illegal_T_6; // @[CSR.scala:925:{30,56,59}]
wire _io_decode_0_read_illegal_T_8 = _io_decode_0_read_illegal_T_2 | _io_decode_0_read_illegal_T_7; // @[CSR.scala:923:44, :924:19, :925:56]
wire _io_decode_0_read_illegal_T_9 = ~allow_counter; // @[CSR.scala:913:91, :926:21]
wire _io_decode_0_read_illegal_T_10 = is_counter & _io_decode_0_read_illegal_T_9; // @[CSR.scala:904:81, :926:{18,21}]
wire _io_decode_0_read_illegal_T_11 = _io_decode_0_read_illegal_T_8 | _io_decode_0_read_illegal_T_10; // @[CSR.scala:924:19, :925:78, :926:18]
wire [11:0] io_decode_0_read_illegal_invInputs = ~io_decode_0_read_illegal_plaInput; // @[pla.scala:77:22, :78:21]
wire io_decode_0_read_illegal_invMatrixOutputs; // @[pla.scala:124:31]
wire io_decode_0_read_illegal_plaOutput; // @[pla.scala:81:23]
wire _io_decode_0_read_illegal_T_12 = io_decode_0_read_illegal_plaOutput; // @[pla.scala:81:23]
wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0 = io_decode_0_read_illegal_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1 = io_decode_0_read_illegal_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2 = io_decode_0_read_illegal_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3 = io_decode_0_read_illegal_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4 = io_decode_0_read_illegal_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5 = io_decode_0_read_illegal_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6 = io_decode_0_read_illegal_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7 = io_decode_0_read_illegal_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_lo_lo = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_lo_hi = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:90:45, :98:53]
wire [3:0] io_decode_0_read_illegal_andMatrixOutputs_lo = {io_decode_0_read_illegal_andMatrixOutputs_lo_hi, io_decode_0_read_illegal_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53]
wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_hi_lo = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_hi_hi = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53]
wire [3:0] io_decode_0_read_illegal_andMatrixOutputs_hi = {io_decode_0_read_illegal_andMatrixOutputs_hi_hi, io_decode_0_read_illegal_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53]
wire [7:0] _io_decode_0_read_illegal_andMatrixOutputs_T = {io_decode_0_read_illegal_andMatrixOutputs_hi, io_decode_0_read_illegal_andMatrixOutputs_lo}; // @[pla.scala:98:53]
wire io_decode_0_read_illegal_andMatrixOutputs_0_2 = &_io_decode_0_read_illegal_andMatrixOutputs_T; // @[pla.scala:98:{53,70}]
wire io_decode_0_read_illegal_orMatrixOutputs = io_decode_0_read_illegal_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36]
assign io_decode_0_read_illegal_invMatrixOutputs = io_decode_0_read_illegal_orMatrixOutputs; // @[pla.scala:114:36, :124:31]
assign io_decode_0_read_illegal_plaOutput = io_decode_0_read_illegal_invMatrixOutputs; // @[pla.scala:81:23, :124:31]
wire _io_decode_0_read_illegal_T_13 = ~reg_debug; // @[CSR.scala:482:26, :927:45]
wire _io_decode_0_read_illegal_T_14 = _io_decode_0_read_illegal_T_12 & _io_decode_0_read_illegal_T_13; // @[Decode.scala:55:116]
wire _io_decode_0_read_illegal_T_15 = _io_decode_0_read_illegal_T_11 | _io_decode_0_read_illegal_T_14; // @[CSR.scala:925:78, :926:36, :927:42]
wire _io_decode_0_read_illegal_T_18 = _io_decode_0_read_illegal_T_15; // @[CSR.scala:926:36, :927:56]
wire [11:0] io_decode_0_read_illegal_invInputs_1 = ~io_decode_0_read_illegal_plaInput_1; // @[pla.scala:77:22, :78:21]
wire _io_decode_0_read_illegal_T_19 = io_decode_0_fp_csr_0 & io_decode_0_fp_illegal_0; // @[CSR.scala:377:7, :929:21]
assign _io_decode_0_read_illegal_T_20 = _io_decode_0_read_illegal_T_18 | _io_decode_0_read_illegal_T_19; // @[CSR.scala:927:56, :928:68, :929:21]
assign io_decode_0_read_illegal_0 = _io_decode_0_read_illegal_T_20; // @[CSR.scala:377:7, :928:68]
wire [1:0] _io_decode_0_write_illegal_T = addr[11:10]; // @[CSR.scala:897:27, :930:33]
assign _io_decode_0_write_illegal_T_1 = &_io_decode_0_write_illegal_T; // @[CSR.scala:930:{33,41}]
assign io_decode_0_write_illegal_0 = _io_decode_0_write_illegal_T_1; // @[CSR.scala:377:7, :930:41]
wire [11:0] io_decode_0_write_flush_addr_m = {_io_decode_0_write_illegal_T, addr[9:0] | 10'h300}; // @[CSR.scala:897:27, :930:33, :932:25]
wire _io_decode_0_write_flush_T = io_decode_0_write_flush_addr_m > 12'h33F; // @[CSR.scala:932:25, :933:16]
wire _io_decode_0_write_flush_T_1 = io_decode_0_write_flush_addr_m < 12'h344; // @[CSR.scala:932:25, :933:45]
wire _io_decode_0_write_flush_T_2 = _io_decode_0_write_flush_T & _io_decode_0_write_flush_T_1; // @[CSR.scala:933:{16,35,45}]
assign _io_decode_0_write_flush_T_3 = ~_io_decode_0_write_flush_T_2; // @[CSR.scala:933:{7,35}]
assign io_decode_0_write_flush_0 = _io_decode_0_write_flush_T_3; // @[CSR.scala:377:7, :933:7]
wire _io_decode_0_system_illegal_T = ~csr_addr_legal; // @[CSR.scala:920:60, :923:28, :935:30]
wire _io_decode_0_system_illegal_T_1 = ~is_hlsv; // @[CSR.scala:903:82, :935:49]
wire _io_decode_0_system_illegal_T_2 = _io_decode_0_system_illegal_T & _io_decode_0_system_illegal_T_1; // @[CSR.scala:935:{30,46,49}]
wire _io_decode_0_system_illegal_T_3 = ~allow_wfi; // @[CSR.scala:906:71, :936:17]
wire _io_decode_0_system_illegal_T_4 = is_wfi & _io_decode_0_system_illegal_T_3; // @[CSR.scala:903:82, :936:{14,17}]
wire _io_decode_0_system_illegal_T_5 = _io_decode_0_system_illegal_T_2 | _io_decode_0_system_illegal_T_4; // @[CSR.scala:935:{46,58}, :936:14]
wire _io_decode_0_system_illegal_T_6 = ~allow_sret; // @[CSR.scala:910:72, :937:17]
wire _io_decode_0_system_illegal_T_7 = is_ret & _io_decode_0_system_illegal_T_6; // @[CSR.scala:903:82, :937:{14,17}]
wire _io_decode_0_system_illegal_T_8 = _io_decode_0_system_illegal_T_5 | _io_decode_0_system_illegal_T_7; // @[CSR.scala:935:58, :936:28, :937:14]
wire _io_decode_0_system_illegal_T_9 = addr[10]; // @[CSR.scala:897:27, :938:21]
wire _io_decode_0_system_illegal_T_10 = is_ret & _io_decode_0_system_illegal_T_9; // @[CSR.scala:903:82, :938:{14,21}]
wire _io_decode_0_system_illegal_T_11 = addr[7]; // @[CSR.scala:897:27, :938:33]
wire _io_decode_0_system_illegal_T_12 = _io_decode_0_system_illegal_T_10 & _io_decode_0_system_illegal_T_11; // @[CSR.scala:938:{14,26,33}]
wire _io_decode_0_system_illegal_T_13 = ~reg_debug; // @[CSR.scala:482:26, :927:45, :938:40]
wire _io_decode_0_system_illegal_T_14 = _io_decode_0_system_illegal_T_12 & _io_decode_0_system_illegal_T_13; // @[CSR.scala:938:{26,37,40}]
wire _io_decode_0_system_illegal_T_15 = _io_decode_0_system_illegal_T_8 | _io_decode_0_system_illegal_T_14; // @[CSR.scala:936:28, :937:29, :938:37]
wire _io_decode_0_system_illegal_T_16 = is_sfence | is_hfence_gvma; // @[CSR.scala:903:82, :939:18]
wire _io_decode_0_system_illegal_T_17 = ~allow_sfence_vma; // @[CSR.scala:907:70, :925:59, :939:40]
wire _io_decode_0_system_illegal_T_18 = _io_decode_0_system_illegal_T_16 & _io_decode_0_system_illegal_T_17; // @[CSR.scala:939:{18,37,40}]
wire _io_decode_0_system_illegal_T_19 = _io_decode_0_system_illegal_T_15 | _io_decode_0_system_illegal_T_18; // @[CSR.scala:937:29, :938:51, :939:37]
wire _io_decode_0_system_illegal_T_22 = _io_decode_0_system_illegal_T_19; // @[CSR.scala:938:51, :939:58]
assign _io_decode_0_system_illegal_T_25 = _io_decode_0_system_illegal_T_22; // @[CSR.scala:939:58, :940:44]
assign io_decode_0_system_illegal_0 = _io_decode_0_system_illegal_T_25; // @[CSR.scala:377:7, :940:44]
wire _io_decode_0_virtual_access_illegal_T = reg_mstatus_v & csr_exists; // @[CSR.scala:395:28, :899:111, :943:52]
wire _io_decode_0_virtual_access_illegal_T_2 = _io_decode_0_virtual_access_illegal_T_1 == 2'h2; // @[CSR.scala:190:36, :944:22]
wire _io_decode_0_virtual_access_illegal_T_4 = _io_decode_0_virtual_access_illegal_T_3[0]; // @[CSR.scala:945:36]
wire _io_decode_0_virtual_access_illegal_T_5 = is_counter & _io_decode_0_virtual_access_illegal_T_4; // @[CSR.scala:904:81, :945:{18,36}]
wire _io_decode_0_virtual_access_illegal_T_7 = _io_decode_0_virtual_access_illegal_T_6[0]; // @[CSR.scala:945:71]
wire _io_decode_0_virtual_access_illegal_T_8 = ~_io_decode_0_virtual_access_illegal_T_7; // @[CSR.scala:945:{55,71}]
wire _io_decode_0_virtual_access_illegal_T_9 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105]
wire _io_decode_0_virtual_access_illegal_T_20 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :946:53]
wire _io_decode_0_virtual_access_illegal_T_25 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :947:46]
wire _io_decode_0_virtual_system_illegal_T_2 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :953:34]
wire _io_decode_0_virtual_system_illegal_T_12 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :954:64]
wire _io_decode_0_virtual_system_illegal_T_17 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :955:37]
wire _io_decode_1_virtual_access_illegal_T_9 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105]
wire _io_decode_1_virtual_access_illegal_T_20 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :946:53]
wire _io_decode_1_virtual_access_illegal_T_25 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :947:46]
wire _io_decode_1_virtual_system_illegal_T_2 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :953:34]
wire _io_decode_1_virtual_system_illegal_T_12 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :954:64]
wire _io_decode_1_virtual_system_illegal_T_17 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :955:37]
wire _io_decode_2_virtual_access_illegal_T_9 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105]
wire _io_decode_2_virtual_access_illegal_T_20 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :946:53]
wire _io_decode_2_virtual_access_illegal_T_25 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :947:46]
wire _io_decode_2_virtual_system_illegal_T_2 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :953:34]
wire _io_decode_2_virtual_system_illegal_T_12 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :954:64]
wire _io_decode_2_virtual_system_illegal_T_17 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :955:37]
wire _cause_T = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :959:61]
wire _reg_hstatus_spvp_T = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :1067:61]
wire _io_decode_0_virtual_access_illegal_T_10 = ~_io_decode_0_virtual_access_illegal_T_9; // @[CSR.scala:945:{89,105}]
wire _io_decode_0_virtual_access_illegal_T_12 = _io_decode_0_virtual_access_illegal_T_11[0]; // @[CSR.scala:945:128]
wire _io_decode_0_virtual_access_illegal_T_13 = ~_io_decode_0_virtual_access_illegal_T_12; // @[CSR.scala:945:{112,128}]
wire _io_decode_0_virtual_access_illegal_T_14 = _io_decode_0_virtual_access_illegal_T_10 & _io_decode_0_virtual_access_illegal_T_13; // @[CSR.scala:945:{89,109,112}]
wire _io_decode_0_virtual_access_illegal_T_15 = _io_decode_0_virtual_access_illegal_T_8 | _io_decode_0_virtual_access_illegal_T_14; // @[CSR.scala:945:{55,86,109}]
wire _io_decode_0_virtual_access_illegal_T_16 = _io_decode_0_virtual_access_illegal_T_5 & _io_decode_0_virtual_access_illegal_T_15; // @[CSR.scala:945:{18,51,86}]
wire _io_decode_0_virtual_access_illegal_T_17 = _io_decode_0_virtual_access_illegal_T_2 | _io_decode_0_virtual_access_illegal_T_16; // @[CSR.scala:944:{22,34}, :945:51]
wire _io_decode_0_virtual_access_illegal_T_19 = _io_decode_0_virtual_access_illegal_T_18 == 2'h1; // @[CSR.scala:190:36, :946:22]
wire _io_decode_0_virtual_access_illegal_T_21 = ~_io_decode_0_virtual_access_illegal_T_20; // @[CSR.scala:946:{37,53}]
wire _io_decode_0_virtual_access_illegal_T_22 = _io_decode_0_virtual_access_illegal_T_19 & _io_decode_0_virtual_access_illegal_T_21; // @[CSR.scala:946:{22,34,37}]
wire _io_decode_0_virtual_access_illegal_T_23 = _io_decode_0_virtual_access_illegal_T_17 | _io_decode_0_virtual_access_illegal_T_22; // @[CSR.scala:944:34, :945:144, :946:34]
wire _io_decode_0_virtual_access_illegal_T_28 = _io_decode_0_virtual_access_illegal_T_23; // @[CSR.scala:945:144, :946:57]
wire _io_decode_0_virtual_access_illegal_T_26 = _io_decode_0_virtual_access_illegal_T_24 & _io_decode_0_virtual_access_illegal_T_25; // @[CSR.scala:947:{12,28,46}]
assign _io_decode_0_virtual_access_illegal_T_29 = _io_decode_0_virtual_access_illegal_T & _io_decode_0_virtual_access_illegal_T_28; // @[CSR.scala:943:{52,66}, :946:57]
assign io_decode_0_virtual_access_illegal_0 = _io_decode_0_virtual_access_illegal_T_29; // @[CSR.scala:377:7, :943:66]
wire _io_decode_0_virtual_system_illegal_T = is_hfence_vvma | is_hfence_gvma; // @[CSR.scala:903:82, :950:22]
wire _io_decode_0_virtual_system_illegal_T_1 = _io_decode_0_virtual_system_illegal_T | is_hlsv; // @[CSR.scala:903:82, :950:22, :951:22]
wire _io_decode_0_virtual_system_illegal_T_3 = ~_io_decode_0_virtual_system_illegal_T_2; // @[CSR.scala:953:{18,34}]
wire _io_decode_0_virtual_system_illegal_T_6 = _io_decode_0_virtual_system_illegal_T_3; // @[CSR.scala:953:{18,38}]
wire _io_decode_0_virtual_system_illegal_T_4 = ~reg_mstatus_tw; // @[CSR.scala:395:28, :906:74, :953:41]
wire _io_decode_0_virtual_system_illegal_T_7 = is_wfi & _io_decode_0_virtual_system_illegal_T_6; // @[CSR.scala:903:82, :953:{14,38}]
wire _io_decode_0_virtual_system_illegal_T_8 = _io_decode_0_virtual_system_illegal_T_1 | _io_decode_0_virtual_system_illegal_T_7; // @[CSR.scala:951:22, :952:15, :953:14]
wire _io_decode_0_virtual_system_illegal_T_10 = _io_decode_0_virtual_system_illegal_T_9 == 2'h1; // @[CSR.scala:190:36, :954:32]
wire _io_decode_0_virtual_system_illegal_T_11 = is_ret & _io_decode_0_virtual_system_illegal_T_10; // @[CSR.scala:903:82, :954:{14,32}]
wire _io_decode_0_virtual_system_illegal_T_13 = ~_io_decode_0_virtual_system_illegal_T_12; // @[CSR.scala:954:{48,64}]
wire _io_decode_0_virtual_system_illegal_T_14 = _io_decode_0_virtual_system_illegal_T_13; // @[CSR.scala:954:{48,68}]
wire _io_decode_0_virtual_system_illegal_T_15 = _io_decode_0_virtual_system_illegal_T_11 & _io_decode_0_virtual_system_illegal_T_14; // @[CSR.scala:954:{14,44,68}]
wire _io_decode_0_virtual_system_illegal_T_16 = _io_decode_0_virtual_system_illegal_T_8 | _io_decode_0_virtual_system_illegal_T_15; // @[CSR.scala:952:15, :953:77, :954:44]
wire _io_decode_0_virtual_system_illegal_T_18 = ~_io_decode_0_virtual_system_illegal_T_17; // @[CSR.scala:955:{21,37}]
wire _io_decode_0_virtual_system_illegal_T_19 = _io_decode_0_virtual_system_illegal_T_18; // @[CSR.scala:955:{21,41}]
wire _io_decode_0_virtual_system_illegal_T_20 = is_sfence & _io_decode_0_virtual_system_illegal_T_19; // @[CSR.scala:903:82, :955:{17,41}]
wire _io_decode_0_virtual_system_illegal_T_21 = _io_decode_0_virtual_system_illegal_T_16 | _io_decode_0_virtual_system_illegal_T_20; // @[CSR.scala:953:77, :954:89, :955:17]
assign _io_decode_0_virtual_system_illegal_T_22 = reg_mstatus_v & _io_decode_0_virtual_system_illegal_T_21; // @[CSR.scala:395:28, :949:52, :954:89]
assign io_decode_0_virtual_system_illegal_0 = _io_decode_0_virtual_system_illegal_T_22; // @[CSR.scala:377:7, :949:52]
wire [11:0] addr_1 = io_decode_1_inst_0[31:20]; // @[CSR.scala:377:7, :897:27]
wire [11:0] io_decode_1_fp_csr_plaInput = addr_1; // @[pla.scala:77:22]
wire [11:0] io_decode_1_vector_csr_plaInput = addr_1; // @[pla.scala:77:22]
wire [11:0] io_decode_1_read_illegal_plaInput = addr_1; // @[pla.scala:77:22]
wire [11:0] io_decode_1_read_illegal_plaInput_1 = addr_1; // @[pla.scala:77:22]
wire [31:0] decoded_invInputs_2 = ~decoded_plaInput_2; // @[pla.scala:77:22, :78:21]
wire [8:0] decoded_invMatrixOutputs_2; // @[pla.scala:120:37]
wire [8:0] decoded_2; // @[pla.scala:81:23]
wire decoded_andMatrixOutputs_andMatrixInput_0_14 = decoded_invInputs_2[20]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_14 = decoded_invInputs_2[21]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_15 = decoded_invInputs_2[21]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_2_12 = decoded_invInputs_2[22]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_2_13 = decoded_invInputs_2[22]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_16 = decoded_invInputs_2[22]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_12 = decoded_invInputs_2[23]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_13 = decoded_invInputs_2[23]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_2_14 = decoded_invInputs_2[23]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_17 = decoded_invInputs_2[23]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_19 = decoded_invInputs_2[23]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_12 = decoded_invInputs_2[24]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_13 = decoded_invInputs_2[24]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_14 = decoded_invInputs_2[24]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_2_15 = decoded_invInputs_2[24]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_2_17 = decoded_invInputs_2[24]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_5_12 = decoded_invInputs_2[25]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_5_13 = decoded_invInputs_2[25]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_14 = decoded_invInputs_2[25]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_15 = decoded_invInputs_2[25]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_17 = decoded_invInputs_2[25]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_6_12 = decoded_invInputs_2[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_6_13 = decoded_invInputs_2[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_5_14 = decoded_invInputs_2[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_15 = decoded_invInputs_2[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_11_8 = decoded_invInputs_2[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_17 = decoded_invInputs_2[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_7_12 = decoded_invInputs_2[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_7_13 = decoded_invInputs_2[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_6_14 = decoded_invInputs_2[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_5_15 = decoded_invInputs_2[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_12_2 = decoded_invInputs_2[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_5_17 = decoded_invInputs_2[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_12 = decoded_invInputs_2[28]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_13 = decoded_invInputs_2[28]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_12 = decoded_invInputs_2[29]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_13 = decoded_invInputs_2[29]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_7_15 = decoded_invInputs_2[29]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_14_2 = decoded_invInputs_2[29]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_10_6 = decoded_invInputs_2[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_10_7 = decoded_invInputs_2[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_14 = decoded_invInputs_2[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_15 = decoded_invInputs_2[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_15_2 = decoded_invInputs_2[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_17 = decoded_invInputs_2[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_11_6 = decoded_invInputs_2[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_11_7 = decoded_invInputs_2[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_14 = decoded_invInputs_2[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_15 = decoded_invInputs_2[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_16_2 = decoded_invInputs_2[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_17 = decoded_invInputs_2[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_20 = decoded_invInputs_2[31]; // @[pla.scala:78:21, :91:29]
wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_6 = {decoded_andMatrixOutputs_andMatrixInput_9_12, decoded_andMatrixOutputs_andMatrixInput_10_6}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_lo_12 = {decoded_andMatrixOutputs_lo_lo_hi_6, decoded_andMatrixOutputs_andMatrixInput_11_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_12 = {decoded_andMatrixOutputs_andMatrixInput_6_12, decoded_andMatrixOutputs_andMatrixInput_7_12}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_hi_12 = {decoded_andMatrixOutputs_lo_hi_hi_12, decoded_andMatrixOutputs_andMatrixInput_8_12}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_andMatrixOutputs_lo_12 = {decoded_andMatrixOutputs_lo_hi_12, decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_6 = {decoded_andMatrixOutputs_andMatrixInput_3_12, decoded_andMatrixOutputs_andMatrixInput_4_12}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_lo_12 = {decoded_andMatrixOutputs_hi_lo_hi_6, decoded_andMatrixOutputs_andMatrixInput_5_12}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_12 = {decoded_andMatrixOutputs_andMatrixInput_0_14, decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_12 = {decoded_andMatrixOutputs_hi_hi_hi_12, decoded_andMatrixOutputs_andMatrixInput_2_12}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_andMatrixOutputs_hi_12 = {decoded_andMatrixOutputs_hi_hi_12, decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53]
wire [11:0] _decoded_andMatrixOutputs_T_14 = {decoded_andMatrixOutputs_hi_12, decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_6_2_2 = &_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}]
wire _decoded_orMatrixOutputs_T_20 = decoded_andMatrixOutputs_6_2_2; // @[pla.scala:98:70, :114:36]
wire decoded_andMatrixOutputs_andMatrixInput_0_15 = decoded_plaInput_2[20]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_7 = {decoded_andMatrixOutputs_andMatrixInput_9_13, decoded_andMatrixOutputs_andMatrixInput_10_7}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_lo_13 = {decoded_andMatrixOutputs_lo_lo_hi_7, decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_13 = {decoded_andMatrixOutputs_andMatrixInput_6_13, decoded_andMatrixOutputs_andMatrixInput_7_13}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_hi_13 = {decoded_andMatrixOutputs_lo_hi_hi_13, decoded_andMatrixOutputs_andMatrixInput_8_13}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_andMatrixOutputs_lo_13 = {decoded_andMatrixOutputs_lo_hi_13, decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_7 = {decoded_andMatrixOutputs_andMatrixInput_3_13, decoded_andMatrixOutputs_andMatrixInput_4_13}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_lo_13 = {decoded_andMatrixOutputs_hi_lo_hi_7, decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_13 = {decoded_andMatrixOutputs_andMatrixInput_0_15, decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_13 = {decoded_andMatrixOutputs_hi_hi_hi_13, decoded_andMatrixOutputs_andMatrixInput_2_13}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_andMatrixOutputs_hi_13 = {decoded_andMatrixOutputs_hi_hi_13, decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53]
wire [11:0] _decoded_andMatrixOutputs_T_15 = {decoded_andMatrixOutputs_hi_13, decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_4_2_2 = &_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}]
wire _decoded_orMatrixOutputs_T_19 = decoded_andMatrixOutputs_4_2_2; // @[pla.scala:98:70, :114:36]
wire decoded_andMatrixOutputs_andMatrixInput_0_16 = decoded_plaInput_2[0]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_0_18 = decoded_plaInput_2[0]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_7_14 = decoded_plaInput_2[28]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_6_15 = decoded_plaInput_2[28]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_13_2 = decoded_plaInput_2[28]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_6_17 = decoded_plaInput_2[28]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_andMatrixOutputs_lo_lo_14 = {decoded_andMatrixOutputs_andMatrixInput_8_14, decoded_andMatrixOutputs_andMatrixInput_9_14}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_14 = {decoded_andMatrixOutputs_andMatrixInput_5_14, decoded_andMatrixOutputs_andMatrixInput_6_14}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_hi_14 = {decoded_andMatrixOutputs_lo_hi_hi_14, decoded_andMatrixOutputs_andMatrixInput_7_14}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_andMatrixOutputs_lo_14 = {decoded_andMatrixOutputs_lo_hi_14, decoded_andMatrixOutputs_lo_lo_14}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_14 = {decoded_andMatrixOutputs_andMatrixInput_3_14, decoded_andMatrixOutputs_andMatrixInput_4_14}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_14 = {decoded_andMatrixOutputs_andMatrixInput_0_16, decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_14 = {decoded_andMatrixOutputs_hi_hi_hi_14, decoded_andMatrixOutputs_andMatrixInput_2_14}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_andMatrixOutputs_hi_14 = {decoded_andMatrixOutputs_hi_hi_14, decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53]
wire [9:0] _decoded_andMatrixOutputs_T_16 = {decoded_andMatrixOutputs_hi_14, decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_3_2_2 = &_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}]
wire decoded_andMatrixOutputs_andMatrixInput_0_17 = decoded_plaInput_2[22]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_0_19 = decoded_plaInput_2[22]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_andMatrixOutputs_lo_lo_15 = {decoded_andMatrixOutputs_andMatrixInput_8_15, decoded_andMatrixOutputs_andMatrixInput_9_15}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_15 = {decoded_andMatrixOutputs_andMatrixInput_5_15, decoded_andMatrixOutputs_andMatrixInput_6_15}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_hi_15 = {decoded_andMatrixOutputs_lo_hi_hi_15, decoded_andMatrixOutputs_andMatrixInput_7_15}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_andMatrixOutputs_lo_15 = {decoded_andMatrixOutputs_lo_hi_15, decoded_andMatrixOutputs_lo_lo_15}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_15 = {decoded_andMatrixOutputs_andMatrixInput_3_15, decoded_andMatrixOutputs_andMatrixInput_4_15}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_15 = {decoded_andMatrixOutputs_andMatrixInput_0_17, decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_15 = {decoded_andMatrixOutputs_hi_hi_hi_15, decoded_andMatrixOutputs_andMatrixInput_2_15}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_andMatrixOutputs_hi_15 = {decoded_andMatrixOutputs_hi_hi_15, decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53]
wire [9:0] _decoded_andMatrixOutputs_T_17 = {decoded_andMatrixOutputs_hi_15, decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_1_2_2 = &_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}]
wire _decoded_orMatrixOutputs_T_15 = decoded_andMatrixOutputs_1_2_2; // @[pla.scala:98:70, :114:36]
wire decoded_andMatrixOutputs_andMatrixInput_1_18 = decoded_plaInput_2[1]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_2_16 = decoded_invInputs_2[2]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_16 = decoded_invInputs_2[3]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_16 = decoded_plaInput_2[4]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_5_16 = decoded_plaInput_2[5]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_6_16 = decoded_plaInput_2[6]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_7_16 = decoded_invInputs_2[7]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_16 = decoded_invInputs_2[8]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_16 = decoded_invInputs_2[9]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_10_8 = decoded_plaInput_2[25]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_andMatrixOutputs_lo_lo_lo_2 = {decoded_andMatrixOutputs_andMatrixInput_15_2, decoded_andMatrixOutputs_andMatrixInput_16_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_8 = {decoded_andMatrixOutputs_andMatrixInput_13_2, decoded_andMatrixOutputs_andMatrixInput_14_2}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoded_andMatrixOutputs_lo_lo_16 = {decoded_andMatrixOutputs_lo_lo_hi_8, decoded_andMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_lo_2 = {decoded_andMatrixOutputs_andMatrixInput_11_8, decoded_andMatrixOutputs_andMatrixInput_12_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_16 = {decoded_andMatrixOutputs_andMatrixInput_9_16, decoded_andMatrixOutputs_andMatrixInput_10_8}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoded_andMatrixOutputs_lo_hi_16 = {decoded_andMatrixOutputs_lo_hi_hi_16, decoded_andMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:98:53]
wire [7:0] decoded_andMatrixOutputs_lo_16 = {decoded_andMatrixOutputs_lo_hi_16, decoded_andMatrixOutputs_lo_lo_16}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_lo_2 = {decoded_andMatrixOutputs_andMatrixInput_7_16, decoded_andMatrixOutputs_andMatrixInput_8_16}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_8 = {decoded_andMatrixOutputs_andMatrixInput_5_16, decoded_andMatrixOutputs_andMatrixInput_6_16}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoded_andMatrixOutputs_hi_lo_16 = {decoded_andMatrixOutputs_hi_lo_hi_8, decoded_andMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_lo_2 = {decoded_andMatrixOutputs_andMatrixInput_3_16, decoded_andMatrixOutputs_andMatrixInput_4_16}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_0_18, decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_hi_16 = {decoded_andMatrixOutputs_hi_hi_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_2_16}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_andMatrixOutputs_hi_hi_16 = {decoded_andMatrixOutputs_hi_hi_hi_16, decoded_andMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:98:53]
wire [8:0] decoded_andMatrixOutputs_hi_16 = {decoded_andMatrixOutputs_hi_hi_16, decoded_andMatrixOutputs_hi_lo_16}; // @[pla.scala:98:53]
wire [16:0] _decoded_andMatrixOutputs_T_18 = {decoded_andMatrixOutputs_hi_16, decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_0_2_2 = &_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}]
wire _decoded_orMatrixOutputs_T_14 = decoded_andMatrixOutputs_0_2_2; // @[pla.scala:98:70, :114:36]
wire decoded_andMatrixOutputs_andMatrixInput_7_17 = decoded_plaInput_2[29]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_andMatrixOutputs_lo_lo_17 = {decoded_andMatrixOutputs_andMatrixInput_8_17, decoded_andMatrixOutputs_andMatrixInput_9_17}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_17 = {decoded_andMatrixOutputs_andMatrixInput_5_17, decoded_andMatrixOutputs_andMatrixInput_6_17}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_hi_17 = {decoded_andMatrixOutputs_lo_hi_hi_17, decoded_andMatrixOutputs_andMatrixInput_7_17}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_andMatrixOutputs_lo_17 = {decoded_andMatrixOutputs_lo_hi_17, decoded_andMatrixOutputs_lo_lo_17}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_17 = {decoded_andMatrixOutputs_andMatrixInput_3_17, decoded_andMatrixOutputs_andMatrixInput_4_17}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_17 = {decoded_andMatrixOutputs_andMatrixInput_0_19, decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_17 = {decoded_andMatrixOutputs_hi_hi_hi_17, decoded_andMatrixOutputs_andMatrixInput_2_17}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_andMatrixOutputs_hi_17 = {decoded_andMatrixOutputs_hi_hi_17, decoded_andMatrixOutputs_hi_lo_17}; // @[pla.scala:98:53]
wire [9:0] _decoded_andMatrixOutputs_T_19 = {decoded_andMatrixOutputs_hi_17, decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_5_2_2 = &_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}]
wire _decoded_orMatrixOutputs_T_16 = decoded_andMatrixOutputs_5_2_2; // @[pla.scala:98:70, :114:36]
wire decoded_andMatrixOutputs_andMatrixInput_0_20 = decoded_plaInput_2[30]; // @[pla.scala:77:22, :90:45]
wire [1:0] _decoded_andMatrixOutputs_T_20 = {decoded_andMatrixOutputs_andMatrixInput_0_20, decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:90:45, :91:29, :98:53]
wire decoded_andMatrixOutputs_2_2_2 = &_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}]
wire [1:0] _decoded_orMatrixOutputs_T_17 = {decoded_andMatrixOutputs_3_2_2, decoded_andMatrixOutputs_2_2_2}; // @[pla.scala:98:70, :114:19]
wire _decoded_orMatrixOutputs_T_18 = |_decoded_orMatrixOutputs_T_17; // @[pla.scala:114:{19,36}]
wire [1:0] decoded_orMatrixOutputs_lo_hi_2 = {_decoded_orMatrixOutputs_T_14, 1'h0}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoded_orMatrixOutputs_lo_2 = {decoded_orMatrixOutputs_lo_hi_2, 2'h0}; // @[pla.scala:102:36]
wire [1:0] decoded_orMatrixOutputs_hi_lo_2 = {_decoded_orMatrixOutputs_T_16, _decoded_orMatrixOutputs_T_15}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_orMatrixOutputs_hi_hi_hi_2 = {_decoded_orMatrixOutputs_T_20, _decoded_orMatrixOutputs_T_19}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_orMatrixOutputs_hi_hi_2 = {decoded_orMatrixOutputs_hi_hi_hi_2, _decoded_orMatrixOutputs_T_18}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_orMatrixOutputs_hi_2 = {decoded_orMatrixOutputs_hi_hi_2, decoded_orMatrixOutputs_hi_lo_2}; // @[pla.scala:102:36]
wire [8:0] decoded_orMatrixOutputs_2 = {decoded_orMatrixOutputs_hi_2, decoded_orMatrixOutputs_lo_2}; // @[pla.scala:102:36]
wire _decoded_invMatrixOutputs_T_18 = decoded_orMatrixOutputs_2[0]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_19 = decoded_orMatrixOutputs_2[1]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_20 = decoded_orMatrixOutputs_2[2]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_21 = decoded_orMatrixOutputs_2[3]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_22 = decoded_orMatrixOutputs_2[4]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_23 = decoded_orMatrixOutputs_2[5]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_24 = decoded_orMatrixOutputs_2[6]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_25 = decoded_orMatrixOutputs_2[7]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_26 = decoded_orMatrixOutputs_2[8]; // @[pla.scala:102:36, :124:31]
wire [1:0] decoded_invMatrixOutputs_lo_lo_2 = {_decoded_invMatrixOutputs_T_19, _decoded_invMatrixOutputs_T_18}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_invMatrixOutputs_lo_hi_2 = {_decoded_invMatrixOutputs_T_21, _decoded_invMatrixOutputs_T_20}; // @[pla.scala:120:37, :124:31]
wire [3:0] decoded_invMatrixOutputs_lo_2 = {decoded_invMatrixOutputs_lo_hi_2, decoded_invMatrixOutputs_lo_lo_2}; // @[pla.scala:120:37]
wire [1:0] decoded_invMatrixOutputs_hi_lo_2 = {_decoded_invMatrixOutputs_T_23, _decoded_invMatrixOutputs_T_22}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_invMatrixOutputs_hi_hi_hi_2 = {_decoded_invMatrixOutputs_T_26, _decoded_invMatrixOutputs_T_25}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_invMatrixOutputs_hi_hi_2 = {decoded_invMatrixOutputs_hi_hi_hi_2, _decoded_invMatrixOutputs_T_24}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_invMatrixOutputs_hi_2 = {decoded_invMatrixOutputs_hi_hi_2, decoded_invMatrixOutputs_hi_lo_2}; // @[pla.scala:120:37]
assign decoded_invMatrixOutputs_2 = {decoded_invMatrixOutputs_hi_2, decoded_invMatrixOutputs_lo_2}; // @[pla.scala:120:37]
assign decoded_2 = decoded_invMatrixOutputs_2; // @[pla.scala:81:23, :120:37]
wire is_break_1 = decoded_2[7]; // @[pla.scala:81:23]
wire is_ret_1 = decoded_2[6]; // @[pla.scala:81:23]
wire is_wfi_1 = decoded_2[4]; // @[pla.scala:81:23]
wire is_sfence_1 = decoded_2[3]; // @[pla.scala:81:23]
wire is_hfence_vvma_1 = decoded_2[2]; // @[pla.scala:81:23]
wire is_hfence_gvma_1 = decoded_2[1]; // @[pla.scala:81:23]
wire is_hlsv_1 = decoded_2[0]; // @[pla.scala:81:23]
wire _is_counter_T_6 = addr_1 > 12'hBFF; // @[package.scala:213:47]
wire _is_counter_T_7 = addr_1 < 12'hC20; // @[package.scala:213:60]
wire _is_counter_T_8 = _is_counter_T_6 & _is_counter_T_7; // @[package.scala:213:{47,55,60}]
wire _is_counter_T_9 = addr_1 > 12'hC7F; // @[package.scala:213:47]
wire _is_counter_T_10 = addr_1 < 12'hCA0; // @[package.scala:213:60]
wire _is_counter_T_11 = _is_counter_T_9 & _is_counter_T_10; // @[package.scala:213:{47,55,60}]
wire is_counter_1 = _is_counter_T_8 | _is_counter_T_11; // @[package.scala:213:55]
wire _allow_wfi_T_8 = _allow_wfi_T_7; // @[CSR.scala:906:{42,61}]
wire _allow_wfi_T_9 = ~reg_mstatus_tw; // @[CSR.scala:395:28, :906:74]
wire _allow_wfi_T_13 = _allow_wfi_T_9; // @[CSR.scala:906:{74,90}]
wire _allow_wfi_T_10 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94]
wire allow_wfi_1 = _allow_wfi_T_8 | _allow_wfi_T_13; // @[CSR.scala:906:{42,71,90}]
wire _allow_sfence_vma_T_5 = _allow_sfence_vma_T_4; // @[CSR.scala:907:{41,60}]
wire _allow_sfence_vma_T_7 = ~_allow_sfence_vma_T_6; // @[CSR.scala:907:{73,77}]
wire allow_sfence_vma_1 = _allow_sfence_vma_T_5 | _allow_sfence_vma_T_7; // @[CSR.scala:907:{41,70,73}]
wire _allow_hfence_vvma_T_3 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :908:53]
wire _allow_hfence_vvma_T_4 = |reg_mstatus_prv; // @[CSR.scala:395:28, :908:88]
wire _allow_hfence_vvma_T_5 = _allow_hfence_vvma_T_3 & _allow_hfence_vvma_T_4; // @[CSR.scala:908:{53,68,88}]
wire _allow_hlsv_T_4 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :909:46]
wire _allow_hlsv_T_5 = |reg_mstatus_prv; // @[CSR.scala:395:28, :908:88, :909:81]
wire _allow_hlsv_T_6 = _allow_hlsv_T_5; // @[CSR.scala:909:{81,92}]
wire _allow_hlsv_T_7 = _allow_hlsv_T_4 & _allow_hlsv_T_6; // @[CSR.scala:909:{46,61,92}]
wire _allow_sret_T_5 = _allow_sret_T_4; // @[CSR.scala:910:{43,62}]
wire _allow_sret_T_7 = ~_allow_sret_T_6; // @[CSR.scala:910:{75,79}]
wire allow_sret_1 = _allow_sret_T_5 | _allow_sret_T_7; // @[CSR.scala:910:{43,72,75}]
wire [4:0] counter_addr_1 = addr_1[4:0]; // @[CSR.scala:897:27, :911:28]
wire [31:0] _GEN_12 = {27'h0, counter_addr_1}; // @[CSR.scala:911:28, :912:70]
wire [31:0] _GEN_13 = read_mcounteren >> _GEN_12; // @[CSR.scala:532:14, :912:70]
wire [31:0] _allow_counter_T_18; // @[CSR.scala:912:70]
assign _allow_counter_T_18 = _GEN_13; // @[CSR.scala:912:70]
wire [31:0] _io_decode_1_virtual_access_illegal_T_3; // @[CSR.scala:945:36]
assign _io_decode_1_virtual_access_illegal_T_3 = _GEN_13; // @[CSR.scala:912:70, :945:36]
wire _allow_counter_T_19 = _allow_counter_T_18[0]; // @[CSR.scala:912:70]
wire _allow_counter_T_20 = _allow_counter_T_17 | _allow_counter_T_19; // @[CSR.scala:912:{42,52,70}]
wire _allow_counter_T_22 = |reg_mstatus_prv; // @[CSR.scala:395:28, :908:88, :913:46]
wire _allow_counter_T_23 = _allow_counter_T_22; // @[CSR.scala:913:{27,46}]
wire [31:0] _GEN_14 = read_scounteren >> _GEN_12; // @[CSR.scala:536:14, :912:70, :913:75]
wire [31:0] _allow_counter_T_24; // @[CSR.scala:913:75]
assign _allow_counter_T_24 = _GEN_14; // @[CSR.scala:913:75]
wire [31:0] _io_decode_1_virtual_access_illegal_T_11; // @[CSR.scala:945:128]
assign _io_decode_1_virtual_access_illegal_T_11 = _GEN_14; // @[CSR.scala:913:75, :945:128]
wire _allow_counter_T_25 = _allow_counter_T_24[0]; // @[CSR.scala:913:75]
wire _allow_counter_T_26 = _allow_counter_T_23 | _allow_counter_T_25; // @[CSR.scala:913:{27,57,75}]
wire _allow_counter_T_27 = _allow_counter_T_20 & _allow_counter_T_26; // @[CSR.scala:912:{52,86}, :913:57]
wire allow_counter_1 = _allow_counter_T_27; // @[CSR.scala:912:86, :913:91]
wire _allow_counter_T_29 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :914:30]
wire [31:0] _GEN_15 = 32'h0 >> _GEN_12; // @[CSR.scala:912:70, :914:63]
wire [31:0] _allow_counter_T_31; // @[CSR.scala:914:63]
assign _allow_counter_T_31 = _GEN_15; // @[CSR.scala:914:63]
wire [31:0] _io_decode_1_virtual_access_illegal_T_6; // @[CSR.scala:945:71]
assign _io_decode_1_virtual_access_illegal_T_6 = _GEN_15; // @[CSR.scala:914:63, :945:71]
wire _allow_counter_T_32 = _allow_counter_T_31[0]; // @[CSR.scala:914:63]
wire _io_decode_1_fp_illegal_T_3 = _io_decode_1_fp_illegal_T; // @[CSR.scala:915:{39,47}]
assign _io_decode_1_fp_illegal_T_6 = _io_decode_1_fp_illegal_T_3; // @[CSR.scala:915:{47,91}]
assign io_decode_1_fp_illegal_0 = _io_decode_1_fp_illegal_T_6; // @[CSR.scala:377:7, :915:91]
wire _io_decode_1_vector_illegal_T_2 = reg_mstatus_v & _io_decode_1_vector_illegal_T_1; // @[CSR.scala:395:28, :916:{68,87}]
wire [11:0] io_decode_1_fp_csr_invInputs = ~io_decode_1_fp_csr_plaInput; // @[pla.scala:77:22, :78:21]
wire io_decode_1_fp_csr_invMatrixOutputs; // @[pla.scala:124:31]
wire io_decode_1_fp_csr_plaOutput; // @[pla.scala:81:23]
assign _io_decode_1_fp_csr_T = io_decode_1_fp_csr_plaOutput; // @[pla.scala:81:23]
wire io_decode_1_fp_csr_andMatrixOutputs_andMatrixInput_0 = io_decode_1_fp_csr_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire io_decode_1_fp_csr_andMatrixOutputs_andMatrixInput_1 = io_decode_1_fp_csr_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire io_decode_1_fp_csr_andMatrixOutputs_andMatrixInput_2 = io_decode_1_fp_csr_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire io_decode_1_fp_csr_andMatrixOutputs_andMatrixInput_3 = io_decode_1_fp_csr_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire [1:0] io_decode_1_fp_csr_andMatrixOutputs_lo = {io_decode_1_fp_csr_andMatrixOutputs_andMatrixInput_2, io_decode_1_fp_csr_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] io_decode_1_fp_csr_andMatrixOutputs_hi = {io_decode_1_fp_csr_andMatrixOutputs_andMatrixInput_0, io_decode_1_fp_csr_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53]
wire [3:0] _io_decode_1_fp_csr_andMatrixOutputs_T = {io_decode_1_fp_csr_andMatrixOutputs_hi, io_decode_1_fp_csr_andMatrixOutputs_lo}; // @[pla.scala:98:53]
wire io_decode_1_fp_csr_andMatrixOutputs_0_2 = &_io_decode_1_fp_csr_andMatrixOutputs_T; // @[pla.scala:98:{53,70}]
wire io_decode_1_fp_csr_orMatrixOutputs = io_decode_1_fp_csr_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36]
assign io_decode_1_fp_csr_invMatrixOutputs = io_decode_1_fp_csr_orMatrixOutputs; // @[pla.scala:114:36, :124:31]
assign io_decode_1_fp_csr_plaOutput = io_decode_1_fp_csr_invMatrixOutputs; // @[pla.scala:81:23, :124:31]
assign io_decode_1_fp_csr_0 = _io_decode_1_fp_csr_T; // @[Decode.scala:55:116]
wire [11:0] io_decode_1_vector_csr_invInputs = ~io_decode_1_vector_csr_plaInput; // @[pla.scala:77:22, :78:21]
wire [1:0] _csr_addr_legal_T_9 = addr_1[9:8]; // @[CSR.scala:190:36, :897:27]
wire [1:0] _csr_addr_legal_T_15 = addr_1[9:8]; // @[CSR.scala:190:36, :897:27]
wire [1:0] _io_decode_1_virtual_access_illegal_T_1 = addr_1[9:8]; // @[CSR.scala:190:36, :897:27]
wire [1:0] _io_decode_1_virtual_access_illegal_T_18 = addr_1[9:8]; // @[CSR.scala:190:36, :897:27]
wire [1:0] _io_decode_1_virtual_system_illegal_T_9 = addr_1[9:8]; // @[CSR.scala:190:36, :897:27]
wire _csr_addr_legal_T_10 = reg_mstatus_prv >= _csr_addr_legal_T_9; // @[CSR.scala:190:36, :395:28, :920:42]
wire csr_addr_legal_1 = _csr_addr_legal_T_10; // @[CSR.scala:920:{42,60}]
wire _csr_addr_legal_T_11 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :921:28]
wire _csr_addr_legal_T_16 = _csr_addr_legal_T_15 == 2'h2; // @[CSR.scala:190:36, :921:92]
wire _csr_exists_T_302 = addr_1 == 12'h7A0; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_303 = addr_1 == 12'h7A1; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_304 = addr_1 == 12'h7A2; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_305 = addr_1 == 12'h7A3; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_306 = addr_1 == 12'h301; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_307 = addr_1 == 12'h300; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_308 = addr_1 == 12'h305; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_309 = addr_1 == 12'h344; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_310 = addr_1 == 12'h304; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_311 = addr_1 == 12'h340; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_312 = addr_1 == 12'h341; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_313 = addr_1 == 12'h343; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_314 = addr_1 == 12'h342; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_315 = addr_1 == 12'hF14; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_316 = addr_1 == 12'h7B0; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_317 = addr_1 == 12'h7B1; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_318 = addr_1 == 12'h7B2; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_319 = addr_1 == 12'h1; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_320 = addr_1 == 12'h2; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_321 = addr_1 == 12'h3; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_322 = addr_1 == 12'h320; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_323 = addr_1 == 12'hB00; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_324 = addr_1 == 12'hB02; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_325 = addr_1 == 12'h323; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_326 = addr_1 == 12'hB03; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_327 = addr_1 == 12'hC03; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_328 = addr_1 == 12'h324; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_329 = addr_1 == 12'hB04; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_330 = addr_1 == 12'hC04; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_331 = addr_1 == 12'h325; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_332 = addr_1 == 12'hB05; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_333 = addr_1 == 12'hC05; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_334 = addr_1 == 12'h326; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_335 = addr_1 == 12'hB06; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_336 = addr_1 == 12'hC06; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_337 = addr_1 == 12'h327; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_338 = addr_1 == 12'hB07; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_339 = addr_1 == 12'hC07; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_340 = addr_1 == 12'h328; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_341 = addr_1 == 12'hB08; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_342 = addr_1 == 12'hC08; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_343 = addr_1 == 12'h329; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_344 = addr_1 == 12'hB09; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_345 = addr_1 == 12'hC09; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_346 = addr_1 == 12'h32A; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_347 = addr_1 == 12'hB0A; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_348 = addr_1 == 12'hC0A; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_349 = addr_1 == 12'h32B; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_350 = addr_1 == 12'hB0B; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_351 = addr_1 == 12'hC0B; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_352 = addr_1 == 12'h32C; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_353 = addr_1 == 12'hB0C; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_354 = addr_1 == 12'hC0C; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_355 = addr_1 == 12'h32D; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_356 = addr_1 == 12'hB0D; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_357 = addr_1 == 12'hC0D; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_358 = addr_1 == 12'h32E; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_359 = addr_1 == 12'hB0E; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_360 = addr_1 == 12'hC0E; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_361 = addr_1 == 12'h32F; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_362 = addr_1 == 12'hB0F; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_363 = addr_1 == 12'hC0F; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_364 = addr_1 == 12'h330; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_365 = addr_1 == 12'hB10; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_366 = addr_1 == 12'hC10; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_367 = addr_1 == 12'h331; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_368 = addr_1 == 12'hB11; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_369 = addr_1 == 12'hC11; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_370 = addr_1 == 12'h332; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_371 = addr_1 == 12'hB12; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_372 = addr_1 == 12'hC12; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_373 = addr_1 == 12'h333; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_374 = addr_1 == 12'hB13; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_375 = addr_1 == 12'hC13; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_376 = addr_1 == 12'h334; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_377 = addr_1 == 12'hB14; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_378 = addr_1 == 12'hC14; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_379 = addr_1 == 12'h335; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_380 = addr_1 == 12'hB15; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_381 = addr_1 == 12'hC15; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_382 = addr_1 == 12'h336; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_383 = addr_1 == 12'hB16; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_384 = addr_1 == 12'hC16; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_385 = addr_1 == 12'h337; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_386 = addr_1 == 12'hB17; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_387 = addr_1 == 12'hC17; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_388 = addr_1 == 12'h338; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_389 = addr_1 == 12'hB18; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_390 = addr_1 == 12'hC18; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_391 = addr_1 == 12'h339; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_392 = addr_1 == 12'hB19; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_393 = addr_1 == 12'hC19; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_394 = addr_1 == 12'h33A; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_395 = addr_1 == 12'hB1A; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_396 = addr_1 == 12'hC1A; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_397 = addr_1 == 12'h33B; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_398 = addr_1 == 12'hB1B; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_399 = addr_1 == 12'hC1B; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_400 = addr_1 == 12'h33C; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_401 = addr_1 == 12'hB1C; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_402 = addr_1 == 12'hC1C; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_403 = addr_1 == 12'h33D; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_404 = addr_1 == 12'hB1D; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_405 = addr_1 == 12'hC1D; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_406 = addr_1 == 12'h33E; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_407 = addr_1 == 12'hB1E; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_408 = addr_1 == 12'hC1E; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_409 = addr_1 == 12'h33F; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_410 = addr_1 == 12'hB1F; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_411 = addr_1 == 12'hC1F; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_412 = addr_1 == 12'h306; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_413 = addr_1 == 12'hC00; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_414 = addr_1 == 12'hC02; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_415 = addr_1 == 12'h30A; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_416 = addr_1 == 12'h100; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_417 = addr_1 == 12'h144; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_418 = addr_1 == 12'h104; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_419 = addr_1 == 12'h140; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_420 = addr_1 == 12'h142; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_421 = addr_1 == 12'h143; // @[CSR.scala:897:27, :899:93]
wire _GEN_16 = addr_1 == 12'h180; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_422; // @[CSR.scala:899:93]
assign _csr_exists_T_422 = _GEN_16; // @[CSR.scala:899:93]
wire _io_decode_1_read_illegal_T_3; // @[CSR.scala:925:14]
assign _io_decode_1_read_illegal_T_3 = _GEN_16; // @[CSR.scala:899:93, :925:14]
wire _io_decode_1_virtual_access_illegal_T_24; // @[CSR.scala:947:12]
assign _io_decode_1_virtual_access_illegal_T_24 = _GEN_16; // @[CSR.scala:899:93, :947:12]
wire _csr_exists_T_423 = addr_1 == 12'h141; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_424 = addr_1 == 12'h105; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_425 = addr_1 == 12'h106; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_426 = addr_1 == 12'h303; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_427 = addr_1 == 12'h302; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_428 = addr_1 == 12'h10A; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_429 = addr_1 == 12'h3A0; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_430 = addr_1 == 12'h3A2; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_431 = addr_1 == 12'h3B0; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_432 = addr_1 == 12'h3B1; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_433 = addr_1 == 12'h3B2; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_434 = addr_1 == 12'h3B3; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_435 = addr_1 == 12'h3B4; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_436 = addr_1 == 12'h3B5; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_437 = addr_1 == 12'h3B6; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_438 = addr_1 == 12'h3B7; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_439 = addr_1 == 12'h3B8; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_440 = addr_1 == 12'h3B9; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_441 = addr_1 == 12'h3BA; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_442 = addr_1 == 12'h3BB; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_443 = addr_1 == 12'h3BC; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_444 = addr_1 == 12'h3BD; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_445 = addr_1 == 12'h3BE; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_446 = addr_1 == 12'h3BF; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_447 = addr_1 == 12'h800; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_448 = addr_1 == 12'h808; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_449 = addr_1 == 12'h7C1; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_450 = addr_1 == 12'hF12; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_451 = addr_1 == 12'hF13; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_452 = addr_1 == 12'hF11; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_453 = addr_1 == 12'hF15; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_454 = _csr_exists_T_302 | _csr_exists_T_303; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_455 = _csr_exists_T_454 | _csr_exists_T_304; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_456 = _csr_exists_T_455 | _csr_exists_T_305; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_457 = _csr_exists_T_456 | _csr_exists_T_306; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_458 = _csr_exists_T_457 | _csr_exists_T_307; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_459 = _csr_exists_T_458 | _csr_exists_T_308; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_460 = _csr_exists_T_459 | _csr_exists_T_309; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_461 = _csr_exists_T_460 | _csr_exists_T_310; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_462 = _csr_exists_T_461 | _csr_exists_T_311; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_463 = _csr_exists_T_462 | _csr_exists_T_312; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_464 = _csr_exists_T_463 | _csr_exists_T_313; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_465 = _csr_exists_T_464 | _csr_exists_T_314; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_466 = _csr_exists_T_465 | _csr_exists_T_315; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_467 = _csr_exists_T_466 | _csr_exists_T_316; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_468 = _csr_exists_T_467 | _csr_exists_T_317; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_469 = _csr_exists_T_468 | _csr_exists_T_318; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_470 = _csr_exists_T_469 | _csr_exists_T_319; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_471 = _csr_exists_T_470 | _csr_exists_T_320; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_472 = _csr_exists_T_471 | _csr_exists_T_321; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_473 = _csr_exists_T_472 | _csr_exists_T_322; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_474 = _csr_exists_T_473 | _csr_exists_T_323; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_475 = _csr_exists_T_474 | _csr_exists_T_324; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_476 = _csr_exists_T_475 | _csr_exists_T_325; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_477 = _csr_exists_T_476 | _csr_exists_T_326; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_478 = _csr_exists_T_477 | _csr_exists_T_327; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_479 = _csr_exists_T_478 | _csr_exists_T_328; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_480 = _csr_exists_T_479 | _csr_exists_T_329; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_481 = _csr_exists_T_480 | _csr_exists_T_330; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_482 = _csr_exists_T_481 | _csr_exists_T_331; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_483 = _csr_exists_T_482 | _csr_exists_T_332; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_484 = _csr_exists_T_483 | _csr_exists_T_333; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_485 = _csr_exists_T_484 | _csr_exists_T_334; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_486 = _csr_exists_T_485 | _csr_exists_T_335; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_487 = _csr_exists_T_486 | _csr_exists_T_336; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_488 = _csr_exists_T_487 | _csr_exists_T_337; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_489 = _csr_exists_T_488 | _csr_exists_T_338; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_490 = _csr_exists_T_489 | _csr_exists_T_339; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_491 = _csr_exists_T_490 | _csr_exists_T_340; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_492 = _csr_exists_T_491 | _csr_exists_T_341; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_493 = _csr_exists_T_492 | _csr_exists_T_342; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_494 = _csr_exists_T_493 | _csr_exists_T_343; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_495 = _csr_exists_T_494 | _csr_exists_T_344; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_496 = _csr_exists_T_495 | _csr_exists_T_345; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_497 = _csr_exists_T_496 | _csr_exists_T_346; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_498 = _csr_exists_T_497 | _csr_exists_T_347; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_499 = _csr_exists_T_498 | _csr_exists_T_348; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_500 = _csr_exists_T_499 | _csr_exists_T_349; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_501 = _csr_exists_T_500 | _csr_exists_T_350; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_502 = _csr_exists_T_501 | _csr_exists_T_351; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_503 = _csr_exists_T_502 | _csr_exists_T_352; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_504 = _csr_exists_T_503 | _csr_exists_T_353; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_505 = _csr_exists_T_504 | _csr_exists_T_354; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_506 = _csr_exists_T_505 | _csr_exists_T_355; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_507 = _csr_exists_T_506 | _csr_exists_T_356; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_508 = _csr_exists_T_507 | _csr_exists_T_357; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_509 = _csr_exists_T_508 | _csr_exists_T_358; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_510 = _csr_exists_T_509 | _csr_exists_T_359; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_511 = _csr_exists_T_510 | _csr_exists_T_360; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_512 = _csr_exists_T_511 | _csr_exists_T_361; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_513 = _csr_exists_T_512 | _csr_exists_T_362; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_514 = _csr_exists_T_513 | _csr_exists_T_363; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_515 = _csr_exists_T_514 | _csr_exists_T_364; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_516 = _csr_exists_T_515 | _csr_exists_T_365; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_517 = _csr_exists_T_516 | _csr_exists_T_366; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_518 = _csr_exists_T_517 | _csr_exists_T_367; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_519 = _csr_exists_T_518 | _csr_exists_T_368; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_520 = _csr_exists_T_519 | _csr_exists_T_369; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_521 = _csr_exists_T_520 | _csr_exists_T_370; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_522 = _csr_exists_T_521 | _csr_exists_T_371; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_523 = _csr_exists_T_522 | _csr_exists_T_372; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_524 = _csr_exists_T_523 | _csr_exists_T_373; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_525 = _csr_exists_T_524 | _csr_exists_T_374; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_526 = _csr_exists_T_525 | _csr_exists_T_375; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_527 = _csr_exists_T_526 | _csr_exists_T_376; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_528 = _csr_exists_T_527 | _csr_exists_T_377; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_529 = _csr_exists_T_528 | _csr_exists_T_378; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_530 = _csr_exists_T_529 | _csr_exists_T_379; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_531 = _csr_exists_T_530 | _csr_exists_T_380; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_532 = _csr_exists_T_531 | _csr_exists_T_381; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_533 = _csr_exists_T_532 | _csr_exists_T_382; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_534 = _csr_exists_T_533 | _csr_exists_T_383; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_535 = _csr_exists_T_534 | _csr_exists_T_384; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_536 = _csr_exists_T_535 | _csr_exists_T_385; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_537 = _csr_exists_T_536 | _csr_exists_T_386; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_538 = _csr_exists_T_537 | _csr_exists_T_387; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_539 = _csr_exists_T_538 | _csr_exists_T_388; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_540 = _csr_exists_T_539 | _csr_exists_T_389; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_541 = _csr_exists_T_540 | _csr_exists_T_390; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_542 = _csr_exists_T_541 | _csr_exists_T_391; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_543 = _csr_exists_T_542 | _csr_exists_T_392; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_544 = _csr_exists_T_543 | _csr_exists_T_393; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_545 = _csr_exists_T_544 | _csr_exists_T_394; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_546 = _csr_exists_T_545 | _csr_exists_T_395; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_547 = _csr_exists_T_546 | _csr_exists_T_396; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_548 = _csr_exists_T_547 | _csr_exists_T_397; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_549 = _csr_exists_T_548 | _csr_exists_T_398; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_550 = _csr_exists_T_549 | _csr_exists_T_399; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_551 = _csr_exists_T_550 | _csr_exists_T_400; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_552 = _csr_exists_T_551 | _csr_exists_T_401; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_553 = _csr_exists_T_552 | _csr_exists_T_402; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_554 = _csr_exists_T_553 | _csr_exists_T_403; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_555 = _csr_exists_T_554 | _csr_exists_T_404; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_556 = _csr_exists_T_555 | _csr_exists_T_405; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_557 = _csr_exists_T_556 | _csr_exists_T_406; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_558 = _csr_exists_T_557 | _csr_exists_T_407; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_559 = _csr_exists_T_558 | _csr_exists_T_408; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_560 = _csr_exists_T_559 | _csr_exists_T_409; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_561 = _csr_exists_T_560 | _csr_exists_T_410; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_562 = _csr_exists_T_561 | _csr_exists_T_411; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_563 = _csr_exists_T_562 | _csr_exists_T_412; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_564 = _csr_exists_T_563 | _csr_exists_T_413; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_565 = _csr_exists_T_564 | _csr_exists_T_414; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_566 = _csr_exists_T_565 | _csr_exists_T_415; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_567 = _csr_exists_T_566 | _csr_exists_T_416; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_568 = _csr_exists_T_567 | _csr_exists_T_417; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_569 = _csr_exists_T_568 | _csr_exists_T_418; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_570 = _csr_exists_T_569 | _csr_exists_T_419; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_571 = _csr_exists_T_570 | _csr_exists_T_420; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_572 = _csr_exists_T_571 | _csr_exists_T_421; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_573 = _csr_exists_T_572 | _csr_exists_T_422; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_574 = _csr_exists_T_573 | _csr_exists_T_423; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_575 = _csr_exists_T_574 | _csr_exists_T_424; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_576 = _csr_exists_T_575 | _csr_exists_T_425; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_577 = _csr_exists_T_576 | _csr_exists_T_426; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_578 = _csr_exists_T_577 | _csr_exists_T_427; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_579 = _csr_exists_T_578 | _csr_exists_T_428; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_580 = _csr_exists_T_579 | _csr_exists_T_429; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_581 = _csr_exists_T_580 | _csr_exists_T_430; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_582 = _csr_exists_T_581 | _csr_exists_T_431; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_583 = _csr_exists_T_582 | _csr_exists_T_432; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_584 = _csr_exists_T_583 | _csr_exists_T_433; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_585 = _csr_exists_T_584 | _csr_exists_T_434; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_586 = _csr_exists_T_585 | _csr_exists_T_435; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_587 = _csr_exists_T_586 | _csr_exists_T_436; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_588 = _csr_exists_T_587 | _csr_exists_T_437; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_589 = _csr_exists_T_588 | _csr_exists_T_438; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_590 = _csr_exists_T_589 | _csr_exists_T_439; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_591 = _csr_exists_T_590 | _csr_exists_T_440; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_592 = _csr_exists_T_591 | _csr_exists_T_441; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_593 = _csr_exists_T_592 | _csr_exists_T_442; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_594 = _csr_exists_T_593 | _csr_exists_T_443; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_595 = _csr_exists_T_594 | _csr_exists_T_444; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_596 = _csr_exists_T_595 | _csr_exists_T_445; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_597 = _csr_exists_T_596 | _csr_exists_T_446; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_598 = _csr_exists_T_597 | _csr_exists_T_447; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_599 = _csr_exists_T_598 | _csr_exists_T_448; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_600 = _csr_exists_T_599 | _csr_exists_T_449; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_601 = _csr_exists_T_600 | _csr_exists_T_450; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_602 = _csr_exists_T_601 | _csr_exists_T_451; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_603 = _csr_exists_T_602 | _csr_exists_T_452; // @[CSR.scala:899:{93,111}]
wire csr_exists_1 = _csr_exists_T_603 | _csr_exists_T_453; // @[CSR.scala:899:{93,111}]
wire _io_decode_1_read_illegal_T = ~csr_addr_legal_1; // @[CSR.scala:920:60, :923:28]
wire _io_decode_1_read_illegal_T_1 = ~csr_exists_1; // @[CSR.scala:899:111, :924:7]
wire _io_decode_1_read_illegal_T_2 = _io_decode_1_read_illegal_T | _io_decode_1_read_illegal_T_1; // @[CSR.scala:923:{28,44}, :924:7]
wire _io_decode_1_read_illegal_T_4 = addr_1 == 12'h680; // @[CSR.scala:897:27, :925:38]
wire _io_decode_1_read_illegal_T_5 = _io_decode_1_read_illegal_T_3 | _io_decode_1_read_illegal_T_4; // @[CSR.scala:925:{14,30,38}]
wire _io_decode_1_read_illegal_T_6 = ~allow_sfence_vma_1; // @[CSR.scala:907:70, :925:59]
wire _io_decode_1_read_illegal_T_7 = _io_decode_1_read_illegal_T_5 & _io_decode_1_read_illegal_T_6; // @[CSR.scala:925:{30,56,59}]
wire _io_decode_1_read_illegal_T_8 = _io_decode_1_read_illegal_T_2 | _io_decode_1_read_illegal_T_7; // @[CSR.scala:923:44, :924:19, :925:56]
wire _io_decode_1_read_illegal_T_9 = ~allow_counter_1; // @[CSR.scala:913:91, :926:21]
wire _io_decode_1_read_illegal_T_10 = is_counter_1 & _io_decode_1_read_illegal_T_9; // @[CSR.scala:904:81, :926:{18,21}]
wire _io_decode_1_read_illegal_T_11 = _io_decode_1_read_illegal_T_8 | _io_decode_1_read_illegal_T_10; // @[CSR.scala:924:19, :925:78, :926:18]
wire [11:0] io_decode_1_read_illegal_invInputs = ~io_decode_1_read_illegal_plaInput; // @[pla.scala:77:22, :78:21]
wire io_decode_1_read_illegal_invMatrixOutputs; // @[pla.scala:124:31]
wire io_decode_1_read_illegal_plaOutput; // @[pla.scala:81:23]
wire _io_decode_1_read_illegal_T_12 = io_decode_1_read_illegal_plaOutput; // @[pla.scala:81:23]
wire io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_0 = io_decode_1_read_illegal_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_1 = io_decode_1_read_illegal_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_2 = io_decode_1_read_illegal_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_3 = io_decode_1_read_illegal_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_4 = io_decode_1_read_illegal_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_5 = io_decode_1_read_illegal_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_6 = io_decode_1_read_illegal_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_7 = io_decode_1_read_illegal_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire [1:0] io_decode_1_read_illegal_andMatrixOutputs_lo_lo = {io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_6, io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] io_decode_1_read_illegal_andMatrixOutputs_lo_hi = {io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_4, io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:90:45, :98:53]
wire [3:0] io_decode_1_read_illegal_andMatrixOutputs_lo = {io_decode_1_read_illegal_andMatrixOutputs_lo_hi, io_decode_1_read_illegal_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53]
wire [1:0] io_decode_1_read_illegal_andMatrixOutputs_hi_lo = {io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_2, io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] io_decode_1_read_illegal_andMatrixOutputs_hi_hi = {io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_0, io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53]
wire [3:0] io_decode_1_read_illegal_andMatrixOutputs_hi = {io_decode_1_read_illegal_andMatrixOutputs_hi_hi, io_decode_1_read_illegal_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53]
wire [7:0] _io_decode_1_read_illegal_andMatrixOutputs_T = {io_decode_1_read_illegal_andMatrixOutputs_hi, io_decode_1_read_illegal_andMatrixOutputs_lo}; // @[pla.scala:98:53]
wire io_decode_1_read_illegal_andMatrixOutputs_0_2 = &_io_decode_1_read_illegal_andMatrixOutputs_T; // @[pla.scala:98:{53,70}]
wire io_decode_1_read_illegal_orMatrixOutputs = io_decode_1_read_illegal_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36]
assign io_decode_1_read_illegal_invMatrixOutputs = io_decode_1_read_illegal_orMatrixOutputs; // @[pla.scala:114:36, :124:31]
assign io_decode_1_read_illegal_plaOutput = io_decode_1_read_illegal_invMatrixOutputs; // @[pla.scala:81:23, :124:31]
wire _io_decode_1_read_illegal_T_13 = ~reg_debug; // @[CSR.scala:482:26, :927:45]
wire _io_decode_1_read_illegal_T_14 = _io_decode_1_read_illegal_T_12 & _io_decode_1_read_illegal_T_13; // @[Decode.scala:55:116]
wire _io_decode_1_read_illegal_T_15 = _io_decode_1_read_illegal_T_11 | _io_decode_1_read_illegal_T_14; // @[CSR.scala:925:78, :926:36, :927:42]
wire _io_decode_1_read_illegal_T_18 = _io_decode_1_read_illegal_T_15; // @[CSR.scala:926:36, :927:56]
wire [11:0] io_decode_1_read_illegal_invInputs_1 = ~io_decode_1_read_illegal_plaInput_1; // @[pla.scala:77:22, :78:21]
wire _io_decode_1_read_illegal_T_19 = io_decode_1_fp_csr_0 & io_decode_1_fp_illegal_0; // @[CSR.scala:377:7, :929:21]
assign _io_decode_1_read_illegal_T_20 = _io_decode_1_read_illegal_T_18 | _io_decode_1_read_illegal_T_19; // @[CSR.scala:927:56, :928:68, :929:21]
assign io_decode_1_read_illegal_0 = _io_decode_1_read_illegal_T_20; // @[CSR.scala:377:7, :928:68]
wire [1:0] _io_decode_1_write_illegal_T = addr_1[11:10]; // @[CSR.scala:897:27, :930:33]
assign _io_decode_1_write_illegal_T_1 = &_io_decode_1_write_illegal_T; // @[CSR.scala:930:{33,41}]
assign io_decode_1_write_illegal_0 = _io_decode_1_write_illegal_T_1; // @[CSR.scala:377:7, :930:41]
wire [11:0] io_decode_1_write_flush_addr_m = {_io_decode_1_write_illegal_T, addr_1[9:0] | 10'h300}; // @[CSR.scala:897:27, :930:33, :932:25]
wire _io_decode_1_write_flush_T = io_decode_1_write_flush_addr_m > 12'h33F; // @[CSR.scala:932:25, :933:16]
wire _io_decode_1_write_flush_T_1 = io_decode_1_write_flush_addr_m < 12'h344; // @[CSR.scala:932:25, :933:45]
wire _io_decode_1_write_flush_T_2 = _io_decode_1_write_flush_T & _io_decode_1_write_flush_T_1; // @[CSR.scala:933:{16,35,45}]
assign _io_decode_1_write_flush_T_3 = ~_io_decode_1_write_flush_T_2; // @[CSR.scala:933:{7,35}]
assign io_decode_1_write_flush_0 = _io_decode_1_write_flush_T_3; // @[CSR.scala:377:7, :933:7]
wire _io_decode_1_system_illegal_T = ~csr_addr_legal_1; // @[CSR.scala:920:60, :923:28, :935:30]
wire _io_decode_1_system_illegal_T_1 = ~is_hlsv_1; // @[CSR.scala:903:82, :935:49]
wire _io_decode_1_system_illegal_T_2 = _io_decode_1_system_illegal_T & _io_decode_1_system_illegal_T_1; // @[CSR.scala:935:{30,46,49}]
wire _io_decode_1_system_illegal_T_3 = ~allow_wfi_1; // @[CSR.scala:906:71, :936:17]
wire _io_decode_1_system_illegal_T_4 = is_wfi_1 & _io_decode_1_system_illegal_T_3; // @[CSR.scala:903:82, :936:{14,17}]
wire _io_decode_1_system_illegal_T_5 = _io_decode_1_system_illegal_T_2 | _io_decode_1_system_illegal_T_4; // @[CSR.scala:935:{46,58}, :936:14]
wire _io_decode_1_system_illegal_T_6 = ~allow_sret_1; // @[CSR.scala:910:72, :937:17]
wire _io_decode_1_system_illegal_T_7 = is_ret_1 & _io_decode_1_system_illegal_T_6; // @[CSR.scala:903:82, :937:{14,17}]
wire _io_decode_1_system_illegal_T_8 = _io_decode_1_system_illegal_T_5 | _io_decode_1_system_illegal_T_7; // @[CSR.scala:935:58, :936:28, :937:14]
wire _io_decode_1_system_illegal_T_9 = addr_1[10]; // @[CSR.scala:897:27, :938:21]
wire _io_decode_1_system_illegal_T_10 = is_ret_1 & _io_decode_1_system_illegal_T_9; // @[CSR.scala:903:82, :938:{14,21}]
wire _io_decode_1_system_illegal_T_11 = addr_1[7]; // @[CSR.scala:897:27, :938:33]
wire _io_decode_1_system_illegal_T_12 = _io_decode_1_system_illegal_T_10 & _io_decode_1_system_illegal_T_11; // @[CSR.scala:938:{14,26,33}]
wire _io_decode_1_system_illegal_T_13 = ~reg_debug; // @[CSR.scala:482:26, :927:45, :938:40]
wire _io_decode_1_system_illegal_T_14 = _io_decode_1_system_illegal_T_12 & _io_decode_1_system_illegal_T_13; // @[CSR.scala:938:{26,37,40}]
wire _io_decode_1_system_illegal_T_15 = _io_decode_1_system_illegal_T_8 | _io_decode_1_system_illegal_T_14; // @[CSR.scala:936:28, :937:29, :938:37]
wire _io_decode_1_system_illegal_T_16 = is_sfence_1 | is_hfence_gvma_1; // @[CSR.scala:903:82, :939:18]
wire _io_decode_1_system_illegal_T_17 = ~allow_sfence_vma_1; // @[CSR.scala:907:70, :925:59, :939:40]
wire _io_decode_1_system_illegal_T_18 = _io_decode_1_system_illegal_T_16 & _io_decode_1_system_illegal_T_17; // @[CSR.scala:939:{18,37,40}]
wire _io_decode_1_system_illegal_T_19 = _io_decode_1_system_illegal_T_15 | _io_decode_1_system_illegal_T_18; // @[CSR.scala:937:29, :938:51, :939:37]
wire _io_decode_1_system_illegal_T_22 = _io_decode_1_system_illegal_T_19; // @[CSR.scala:938:51, :939:58]
assign _io_decode_1_system_illegal_T_25 = _io_decode_1_system_illegal_T_22; // @[CSR.scala:939:58, :940:44]
assign io_decode_1_system_illegal_0 = _io_decode_1_system_illegal_T_25; // @[CSR.scala:377:7, :940:44]
wire _io_decode_1_virtual_access_illegal_T = reg_mstatus_v & csr_exists_1; // @[CSR.scala:395:28, :899:111, :943:52]
wire _io_decode_1_virtual_access_illegal_T_2 = _io_decode_1_virtual_access_illegal_T_1 == 2'h2; // @[CSR.scala:190:36, :944:22]
wire _io_decode_1_virtual_access_illegal_T_4 = _io_decode_1_virtual_access_illegal_T_3[0]; // @[CSR.scala:945:36]
wire _io_decode_1_virtual_access_illegal_T_5 = is_counter_1 & _io_decode_1_virtual_access_illegal_T_4; // @[CSR.scala:904:81, :945:{18,36}]
wire _io_decode_1_virtual_access_illegal_T_7 = _io_decode_1_virtual_access_illegal_T_6[0]; // @[CSR.scala:945:71]
wire _io_decode_1_virtual_access_illegal_T_8 = ~_io_decode_1_virtual_access_illegal_T_7; // @[CSR.scala:945:{55,71}]
wire _io_decode_1_virtual_access_illegal_T_10 = ~_io_decode_1_virtual_access_illegal_T_9; // @[CSR.scala:945:{89,105}]
wire _io_decode_1_virtual_access_illegal_T_12 = _io_decode_1_virtual_access_illegal_T_11[0]; // @[CSR.scala:945:128]
wire _io_decode_1_virtual_access_illegal_T_13 = ~_io_decode_1_virtual_access_illegal_T_12; // @[CSR.scala:945:{112,128}]
wire _io_decode_1_virtual_access_illegal_T_14 = _io_decode_1_virtual_access_illegal_T_10 & _io_decode_1_virtual_access_illegal_T_13; // @[CSR.scala:945:{89,109,112}]
wire _io_decode_1_virtual_access_illegal_T_15 = _io_decode_1_virtual_access_illegal_T_8 | _io_decode_1_virtual_access_illegal_T_14; // @[CSR.scala:945:{55,86,109}]
wire _io_decode_1_virtual_access_illegal_T_16 = _io_decode_1_virtual_access_illegal_T_5 & _io_decode_1_virtual_access_illegal_T_15; // @[CSR.scala:945:{18,51,86}]
wire _io_decode_1_virtual_access_illegal_T_17 = _io_decode_1_virtual_access_illegal_T_2 | _io_decode_1_virtual_access_illegal_T_16; // @[CSR.scala:944:{22,34}, :945:51]
wire _io_decode_1_virtual_access_illegal_T_19 = _io_decode_1_virtual_access_illegal_T_18 == 2'h1; // @[CSR.scala:190:36, :946:22]
wire _io_decode_1_virtual_access_illegal_T_21 = ~_io_decode_1_virtual_access_illegal_T_20; // @[CSR.scala:946:{37,53}]
wire _io_decode_1_virtual_access_illegal_T_22 = _io_decode_1_virtual_access_illegal_T_19 & _io_decode_1_virtual_access_illegal_T_21; // @[CSR.scala:946:{22,34,37}]
wire _io_decode_1_virtual_access_illegal_T_23 = _io_decode_1_virtual_access_illegal_T_17 | _io_decode_1_virtual_access_illegal_T_22; // @[CSR.scala:944:34, :945:144, :946:34]
wire _io_decode_1_virtual_access_illegal_T_28 = _io_decode_1_virtual_access_illegal_T_23; // @[CSR.scala:945:144, :946:57]
wire _io_decode_1_virtual_access_illegal_T_26 = _io_decode_1_virtual_access_illegal_T_24 & _io_decode_1_virtual_access_illegal_T_25; // @[CSR.scala:947:{12,28,46}]
assign _io_decode_1_virtual_access_illegal_T_29 = _io_decode_1_virtual_access_illegal_T & _io_decode_1_virtual_access_illegal_T_28; // @[CSR.scala:943:{52,66}, :946:57]
assign io_decode_1_virtual_access_illegal_0 = _io_decode_1_virtual_access_illegal_T_29; // @[CSR.scala:377:7, :943:66]
wire _io_decode_1_virtual_system_illegal_T = is_hfence_vvma_1 | is_hfence_gvma_1; // @[CSR.scala:903:82, :950:22]
wire _io_decode_1_virtual_system_illegal_T_1 = _io_decode_1_virtual_system_illegal_T | is_hlsv_1; // @[CSR.scala:903:82, :950:22, :951:22]
wire _io_decode_1_virtual_system_illegal_T_3 = ~_io_decode_1_virtual_system_illegal_T_2; // @[CSR.scala:953:{18,34}]
wire _io_decode_1_virtual_system_illegal_T_6 = _io_decode_1_virtual_system_illegal_T_3; // @[CSR.scala:953:{18,38}]
wire _io_decode_1_virtual_system_illegal_T_4 = ~reg_mstatus_tw; // @[CSR.scala:395:28, :906:74, :953:41]
wire _io_decode_1_virtual_system_illegal_T_7 = is_wfi_1 & _io_decode_1_virtual_system_illegal_T_6; // @[CSR.scala:903:82, :953:{14,38}]
wire _io_decode_1_virtual_system_illegal_T_8 = _io_decode_1_virtual_system_illegal_T_1 | _io_decode_1_virtual_system_illegal_T_7; // @[CSR.scala:951:22, :952:15, :953:14]
wire _io_decode_1_virtual_system_illegal_T_10 = _io_decode_1_virtual_system_illegal_T_9 == 2'h1; // @[CSR.scala:190:36, :954:32]
wire _io_decode_1_virtual_system_illegal_T_11 = is_ret_1 & _io_decode_1_virtual_system_illegal_T_10; // @[CSR.scala:903:82, :954:{14,32}]
wire _io_decode_1_virtual_system_illegal_T_13 = ~_io_decode_1_virtual_system_illegal_T_12; // @[CSR.scala:954:{48,64}]
wire _io_decode_1_virtual_system_illegal_T_14 = _io_decode_1_virtual_system_illegal_T_13; // @[CSR.scala:954:{48,68}]
wire _io_decode_1_virtual_system_illegal_T_15 = _io_decode_1_virtual_system_illegal_T_11 & _io_decode_1_virtual_system_illegal_T_14; // @[CSR.scala:954:{14,44,68}]
wire _io_decode_1_virtual_system_illegal_T_16 = _io_decode_1_virtual_system_illegal_T_8 | _io_decode_1_virtual_system_illegal_T_15; // @[CSR.scala:952:15, :953:77, :954:44]
wire _io_decode_1_virtual_system_illegal_T_18 = ~_io_decode_1_virtual_system_illegal_T_17; // @[CSR.scala:955:{21,37}]
wire _io_decode_1_virtual_system_illegal_T_19 = _io_decode_1_virtual_system_illegal_T_18; // @[CSR.scala:955:{21,41}]
wire _io_decode_1_virtual_system_illegal_T_20 = is_sfence_1 & _io_decode_1_virtual_system_illegal_T_19; // @[CSR.scala:903:82, :955:{17,41}]
wire _io_decode_1_virtual_system_illegal_T_21 = _io_decode_1_virtual_system_illegal_T_16 | _io_decode_1_virtual_system_illegal_T_20; // @[CSR.scala:953:77, :954:89, :955:17]
assign _io_decode_1_virtual_system_illegal_T_22 = reg_mstatus_v & _io_decode_1_virtual_system_illegal_T_21; // @[CSR.scala:395:28, :949:52, :954:89]
assign io_decode_1_virtual_system_illegal_0 = _io_decode_1_virtual_system_illegal_T_22; // @[CSR.scala:377:7, :949:52]
wire [11:0] addr_2 = io_decode_2_inst_0[31:20]; // @[CSR.scala:377:7, :897:27]
wire [11:0] io_decode_2_fp_csr_plaInput = addr_2; // @[pla.scala:77:22]
wire [11:0] io_decode_2_vector_csr_plaInput = addr_2; // @[pla.scala:77:22]
wire [11:0] io_decode_2_read_illegal_plaInput = addr_2; // @[pla.scala:77:22]
wire [11:0] io_decode_2_read_illegal_plaInput_1 = addr_2; // @[pla.scala:77:22]
wire [31:0] decoded_invInputs_3 = ~decoded_plaInput_3; // @[pla.scala:77:22, :78:21]
wire [8:0] decoded_invMatrixOutputs_3; // @[pla.scala:120:37]
wire [8:0] decoded_3; // @[pla.scala:81:23]
wire decoded_andMatrixOutputs_andMatrixInput_0_21 = decoded_invInputs_3[20]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_21 = decoded_invInputs_3[21]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_22 = decoded_invInputs_3[21]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_2_18 = decoded_invInputs_3[22]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_2_19 = decoded_invInputs_3[22]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_23 = decoded_invInputs_3[22]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_18 = decoded_invInputs_3[23]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_19 = decoded_invInputs_3[23]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_2_20 = decoded_invInputs_3[23]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_24 = decoded_invInputs_3[23]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_26 = decoded_invInputs_3[23]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_18 = decoded_invInputs_3[24]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_19 = decoded_invInputs_3[24]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_20 = decoded_invInputs_3[24]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_2_21 = decoded_invInputs_3[24]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_2_23 = decoded_invInputs_3[24]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_5_18 = decoded_invInputs_3[25]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_5_19 = decoded_invInputs_3[25]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_20 = decoded_invInputs_3[25]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_21 = decoded_invInputs_3[25]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_23 = decoded_invInputs_3[25]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_6_18 = decoded_invInputs_3[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_6_19 = decoded_invInputs_3[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_5_20 = decoded_invInputs_3[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_21 = decoded_invInputs_3[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_11_11 = decoded_invInputs_3[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_23 = decoded_invInputs_3[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_7_18 = decoded_invInputs_3[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_7_19 = decoded_invInputs_3[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_6_20 = decoded_invInputs_3[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_5_21 = decoded_invInputs_3[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_12_3 = decoded_invInputs_3[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_5_23 = decoded_invInputs_3[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_18 = decoded_invInputs_3[28]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_19 = decoded_invInputs_3[28]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_18 = decoded_invInputs_3[29]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_19 = decoded_invInputs_3[29]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_7_21 = decoded_invInputs_3[29]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_14_3 = decoded_invInputs_3[29]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_10_9 = decoded_invInputs_3[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_10_10 = decoded_invInputs_3[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_20 = decoded_invInputs_3[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_21 = decoded_invInputs_3[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_15_3 = decoded_invInputs_3[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_23 = decoded_invInputs_3[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_11_9 = decoded_invInputs_3[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_11_10 = decoded_invInputs_3[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_20 = decoded_invInputs_3[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_21 = decoded_invInputs_3[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_16_3 = decoded_invInputs_3[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_23 = decoded_invInputs_3[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_27 = decoded_invInputs_3[31]; // @[pla.scala:78:21, :91:29]
wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_9 = {decoded_andMatrixOutputs_andMatrixInput_9_18, decoded_andMatrixOutputs_andMatrixInput_10_9}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_lo_18 = {decoded_andMatrixOutputs_lo_lo_hi_9, decoded_andMatrixOutputs_andMatrixInput_11_9}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_18 = {decoded_andMatrixOutputs_andMatrixInput_6_18, decoded_andMatrixOutputs_andMatrixInput_7_18}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_hi_18 = {decoded_andMatrixOutputs_lo_hi_hi_18, decoded_andMatrixOutputs_andMatrixInput_8_18}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_andMatrixOutputs_lo_18 = {decoded_andMatrixOutputs_lo_hi_18, decoded_andMatrixOutputs_lo_lo_18}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_9 = {decoded_andMatrixOutputs_andMatrixInput_3_18, decoded_andMatrixOutputs_andMatrixInput_4_18}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_lo_18 = {decoded_andMatrixOutputs_hi_lo_hi_9, decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_18 = {decoded_andMatrixOutputs_andMatrixInput_0_21, decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_18 = {decoded_andMatrixOutputs_hi_hi_hi_18, decoded_andMatrixOutputs_andMatrixInput_2_18}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_andMatrixOutputs_hi_18 = {decoded_andMatrixOutputs_hi_hi_18, decoded_andMatrixOutputs_hi_lo_18}; // @[pla.scala:98:53]
wire [11:0] _decoded_andMatrixOutputs_T_21 = {decoded_andMatrixOutputs_hi_18, decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_6_2_3 = &_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}]
wire _decoded_orMatrixOutputs_T_27 = decoded_andMatrixOutputs_6_2_3; // @[pla.scala:98:70, :114:36]
wire decoded_andMatrixOutputs_andMatrixInput_0_22 = decoded_plaInput_3[20]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_10 = {decoded_andMatrixOutputs_andMatrixInput_9_19, decoded_andMatrixOutputs_andMatrixInput_10_10}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_lo_19 = {decoded_andMatrixOutputs_lo_lo_hi_10, decoded_andMatrixOutputs_andMatrixInput_11_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_19 = {decoded_andMatrixOutputs_andMatrixInput_6_19, decoded_andMatrixOutputs_andMatrixInput_7_19}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_hi_19 = {decoded_andMatrixOutputs_lo_hi_hi_19, decoded_andMatrixOutputs_andMatrixInput_8_19}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_andMatrixOutputs_lo_19 = {decoded_andMatrixOutputs_lo_hi_19, decoded_andMatrixOutputs_lo_lo_19}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_10 = {decoded_andMatrixOutputs_andMatrixInput_3_19, decoded_andMatrixOutputs_andMatrixInput_4_19}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_lo_19 = {decoded_andMatrixOutputs_hi_lo_hi_10, decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_19 = {decoded_andMatrixOutputs_andMatrixInput_0_22, decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_19 = {decoded_andMatrixOutputs_hi_hi_hi_19, decoded_andMatrixOutputs_andMatrixInput_2_19}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_andMatrixOutputs_hi_19 = {decoded_andMatrixOutputs_hi_hi_19, decoded_andMatrixOutputs_hi_lo_19}; // @[pla.scala:98:53]
wire [11:0] _decoded_andMatrixOutputs_T_22 = {decoded_andMatrixOutputs_hi_19, decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_4_2_3 = &_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}]
wire _decoded_orMatrixOutputs_T_26 = decoded_andMatrixOutputs_4_2_3; // @[pla.scala:98:70, :114:36]
wire decoded_andMatrixOutputs_andMatrixInput_0_23 = decoded_plaInput_3[0]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_0_25 = decoded_plaInput_3[0]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_7_20 = decoded_plaInput_3[28]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_6_21 = decoded_plaInput_3[28]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_13_3 = decoded_plaInput_3[28]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_6_23 = decoded_plaInput_3[28]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_andMatrixOutputs_lo_lo_20 = {decoded_andMatrixOutputs_andMatrixInput_8_20, decoded_andMatrixOutputs_andMatrixInput_9_20}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_20 = {decoded_andMatrixOutputs_andMatrixInput_5_20, decoded_andMatrixOutputs_andMatrixInput_6_20}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_hi_20 = {decoded_andMatrixOutputs_lo_hi_hi_20, decoded_andMatrixOutputs_andMatrixInput_7_20}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_andMatrixOutputs_lo_20 = {decoded_andMatrixOutputs_lo_hi_20, decoded_andMatrixOutputs_lo_lo_20}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_20 = {decoded_andMatrixOutputs_andMatrixInput_3_20, decoded_andMatrixOutputs_andMatrixInput_4_20}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_20 = {decoded_andMatrixOutputs_andMatrixInput_0_23, decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_20 = {decoded_andMatrixOutputs_hi_hi_hi_20, decoded_andMatrixOutputs_andMatrixInput_2_20}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_andMatrixOutputs_hi_20 = {decoded_andMatrixOutputs_hi_hi_20, decoded_andMatrixOutputs_hi_lo_20}; // @[pla.scala:98:53]
wire [9:0] _decoded_andMatrixOutputs_T_23 = {decoded_andMatrixOutputs_hi_20, decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_3_2_3 = &_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}]
wire decoded_andMatrixOutputs_andMatrixInput_0_24 = decoded_plaInput_3[22]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_0_26 = decoded_plaInput_3[22]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_andMatrixOutputs_lo_lo_21 = {decoded_andMatrixOutputs_andMatrixInput_8_21, decoded_andMatrixOutputs_andMatrixInput_9_21}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_21 = {decoded_andMatrixOutputs_andMatrixInput_5_21, decoded_andMatrixOutputs_andMatrixInput_6_21}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_hi_21 = {decoded_andMatrixOutputs_lo_hi_hi_21, decoded_andMatrixOutputs_andMatrixInput_7_21}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_andMatrixOutputs_lo_21 = {decoded_andMatrixOutputs_lo_hi_21, decoded_andMatrixOutputs_lo_lo_21}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_21 = {decoded_andMatrixOutputs_andMatrixInput_3_21, decoded_andMatrixOutputs_andMatrixInput_4_21}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_21 = {decoded_andMatrixOutputs_andMatrixInput_0_24, decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_21 = {decoded_andMatrixOutputs_hi_hi_hi_21, decoded_andMatrixOutputs_andMatrixInput_2_21}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_andMatrixOutputs_hi_21 = {decoded_andMatrixOutputs_hi_hi_21, decoded_andMatrixOutputs_hi_lo_21}; // @[pla.scala:98:53]
wire [9:0] _decoded_andMatrixOutputs_T_24 = {decoded_andMatrixOutputs_hi_21, decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_1_2_3 = &_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}]
wire _decoded_orMatrixOutputs_T_22 = decoded_andMatrixOutputs_1_2_3; // @[pla.scala:98:70, :114:36]
wire decoded_andMatrixOutputs_andMatrixInput_1_25 = decoded_plaInput_3[1]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_2_22 = decoded_invInputs_3[2]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_22 = decoded_invInputs_3[3]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_22 = decoded_plaInput_3[4]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_5_22 = decoded_plaInput_3[5]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_6_22 = decoded_plaInput_3[6]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_7_22 = decoded_invInputs_3[7]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_22 = decoded_invInputs_3[8]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_22 = decoded_invInputs_3[9]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_10_11 = decoded_plaInput_3[25]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_andMatrixOutputs_lo_lo_lo_3 = {decoded_andMatrixOutputs_andMatrixInput_15_3, decoded_andMatrixOutputs_andMatrixInput_16_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_11 = {decoded_andMatrixOutputs_andMatrixInput_13_3, decoded_andMatrixOutputs_andMatrixInput_14_3}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoded_andMatrixOutputs_lo_lo_22 = {decoded_andMatrixOutputs_lo_lo_hi_11, decoded_andMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_lo_3 = {decoded_andMatrixOutputs_andMatrixInput_11_11, decoded_andMatrixOutputs_andMatrixInput_12_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_22 = {decoded_andMatrixOutputs_andMatrixInput_9_22, decoded_andMatrixOutputs_andMatrixInput_10_11}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoded_andMatrixOutputs_lo_hi_22 = {decoded_andMatrixOutputs_lo_hi_hi_22, decoded_andMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:98:53]
wire [7:0] decoded_andMatrixOutputs_lo_22 = {decoded_andMatrixOutputs_lo_hi_22, decoded_andMatrixOutputs_lo_lo_22}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_lo_3 = {decoded_andMatrixOutputs_andMatrixInput_7_22, decoded_andMatrixOutputs_andMatrixInput_8_22}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_11 = {decoded_andMatrixOutputs_andMatrixInput_5_22, decoded_andMatrixOutputs_andMatrixInput_6_22}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoded_andMatrixOutputs_hi_lo_22 = {decoded_andMatrixOutputs_hi_lo_hi_11, decoded_andMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_lo_3 = {decoded_andMatrixOutputs_andMatrixInput_3_22, decoded_andMatrixOutputs_andMatrixInput_4_22}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_0_25, decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_hi_22 = {decoded_andMatrixOutputs_hi_hi_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_2_22}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_andMatrixOutputs_hi_hi_22 = {decoded_andMatrixOutputs_hi_hi_hi_22, decoded_andMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:98:53]
wire [8:0] decoded_andMatrixOutputs_hi_22 = {decoded_andMatrixOutputs_hi_hi_22, decoded_andMatrixOutputs_hi_lo_22}; // @[pla.scala:98:53]
wire [16:0] _decoded_andMatrixOutputs_T_25 = {decoded_andMatrixOutputs_hi_22, decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_0_2_3 = &_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}]
wire _decoded_orMatrixOutputs_T_21 = decoded_andMatrixOutputs_0_2_3; // @[pla.scala:98:70, :114:36]
wire decoded_andMatrixOutputs_andMatrixInput_7_23 = decoded_plaInput_3[29]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_andMatrixOutputs_lo_lo_23 = {decoded_andMatrixOutputs_andMatrixInput_8_23, decoded_andMatrixOutputs_andMatrixInput_9_23}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_23 = {decoded_andMatrixOutputs_andMatrixInput_5_23, decoded_andMatrixOutputs_andMatrixInput_6_23}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_hi_23 = {decoded_andMatrixOutputs_lo_hi_hi_23, decoded_andMatrixOutputs_andMatrixInput_7_23}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_andMatrixOutputs_lo_23 = {decoded_andMatrixOutputs_lo_hi_23, decoded_andMatrixOutputs_lo_lo_23}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_23 = {decoded_andMatrixOutputs_andMatrixInput_3_23, decoded_andMatrixOutputs_andMatrixInput_4_23}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_23 = {decoded_andMatrixOutputs_andMatrixInput_0_26, decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_23 = {decoded_andMatrixOutputs_hi_hi_hi_23, decoded_andMatrixOutputs_andMatrixInput_2_23}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_andMatrixOutputs_hi_23 = {decoded_andMatrixOutputs_hi_hi_23, decoded_andMatrixOutputs_hi_lo_23}; // @[pla.scala:98:53]
wire [9:0] _decoded_andMatrixOutputs_T_26 = {decoded_andMatrixOutputs_hi_23, decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_5_2_3 = &_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}]
wire _decoded_orMatrixOutputs_T_23 = decoded_andMatrixOutputs_5_2_3; // @[pla.scala:98:70, :114:36]
wire decoded_andMatrixOutputs_andMatrixInput_0_27 = decoded_plaInput_3[30]; // @[pla.scala:77:22, :90:45]
wire [1:0] _decoded_andMatrixOutputs_T_27 = {decoded_andMatrixOutputs_andMatrixInput_0_27, decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:90:45, :91:29, :98:53]
wire decoded_andMatrixOutputs_2_2_3 = &_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}]
wire [1:0] _decoded_orMatrixOutputs_T_24 = {decoded_andMatrixOutputs_3_2_3, decoded_andMatrixOutputs_2_2_3}; // @[pla.scala:98:70, :114:19]
wire _decoded_orMatrixOutputs_T_25 = |_decoded_orMatrixOutputs_T_24; // @[pla.scala:114:{19,36}]
wire [1:0] decoded_orMatrixOutputs_lo_hi_3 = {_decoded_orMatrixOutputs_T_21, 1'h0}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoded_orMatrixOutputs_lo_3 = {decoded_orMatrixOutputs_lo_hi_3, 2'h0}; // @[pla.scala:102:36]
wire [1:0] decoded_orMatrixOutputs_hi_lo_3 = {_decoded_orMatrixOutputs_T_23, _decoded_orMatrixOutputs_T_22}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_orMatrixOutputs_hi_hi_hi_3 = {_decoded_orMatrixOutputs_T_27, _decoded_orMatrixOutputs_T_26}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_orMatrixOutputs_hi_hi_3 = {decoded_orMatrixOutputs_hi_hi_hi_3, _decoded_orMatrixOutputs_T_25}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_orMatrixOutputs_hi_3 = {decoded_orMatrixOutputs_hi_hi_3, decoded_orMatrixOutputs_hi_lo_3}; // @[pla.scala:102:36]
wire [8:0] decoded_orMatrixOutputs_3 = {decoded_orMatrixOutputs_hi_3, decoded_orMatrixOutputs_lo_3}; // @[pla.scala:102:36]
wire _decoded_invMatrixOutputs_T_27 = decoded_orMatrixOutputs_3[0]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_28 = decoded_orMatrixOutputs_3[1]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_29 = decoded_orMatrixOutputs_3[2]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_30 = decoded_orMatrixOutputs_3[3]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_31 = decoded_orMatrixOutputs_3[4]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_32 = decoded_orMatrixOutputs_3[5]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_33 = decoded_orMatrixOutputs_3[6]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_34 = decoded_orMatrixOutputs_3[7]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_35 = decoded_orMatrixOutputs_3[8]; // @[pla.scala:102:36, :124:31]
wire [1:0] decoded_invMatrixOutputs_lo_lo_3 = {_decoded_invMatrixOutputs_T_28, _decoded_invMatrixOutputs_T_27}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_invMatrixOutputs_lo_hi_3 = {_decoded_invMatrixOutputs_T_30, _decoded_invMatrixOutputs_T_29}; // @[pla.scala:120:37, :124:31]
wire [3:0] decoded_invMatrixOutputs_lo_3 = {decoded_invMatrixOutputs_lo_hi_3, decoded_invMatrixOutputs_lo_lo_3}; // @[pla.scala:120:37]
wire [1:0] decoded_invMatrixOutputs_hi_lo_3 = {_decoded_invMatrixOutputs_T_32, _decoded_invMatrixOutputs_T_31}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_invMatrixOutputs_hi_hi_hi_3 = {_decoded_invMatrixOutputs_T_35, _decoded_invMatrixOutputs_T_34}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_invMatrixOutputs_hi_hi_3 = {decoded_invMatrixOutputs_hi_hi_hi_3, _decoded_invMatrixOutputs_T_33}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_invMatrixOutputs_hi_3 = {decoded_invMatrixOutputs_hi_hi_3, decoded_invMatrixOutputs_hi_lo_3}; // @[pla.scala:120:37]
assign decoded_invMatrixOutputs_3 = {decoded_invMatrixOutputs_hi_3, decoded_invMatrixOutputs_lo_3}; // @[pla.scala:120:37]
assign decoded_3 = decoded_invMatrixOutputs_3; // @[pla.scala:81:23, :120:37]
wire is_break_2 = decoded_3[7]; // @[pla.scala:81:23]
wire is_ret_2 = decoded_3[6]; // @[pla.scala:81:23]
wire is_wfi_2 = decoded_3[4]; // @[pla.scala:81:23]
wire is_sfence_2 = decoded_3[3]; // @[pla.scala:81:23]
wire is_hfence_vvma_2 = decoded_3[2]; // @[pla.scala:81:23]
wire is_hfence_gvma_2 = decoded_3[1]; // @[pla.scala:81:23]
wire is_hlsv_2 = decoded_3[0]; // @[pla.scala:81:23]
wire _is_counter_T_12 = addr_2 > 12'hBFF; // @[package.scala:213:47]
wire _is_counter_T_13 = addr_2 < 12'hC20; // @[package.scala:213:60]
wire _is_counter_T_14 = _is_counter_T_12 & _is_counter_T_13; // @[package.scala:213:{47,55,60}]
wire _is_counter_T_15 = addr_2 > 12'hC7F; // @[package.scala:213:47]
wire _is_counter_T_16 = addr_2 < 12'hCA0; // @[package.scala:213:60]
wire _is_counter_T_17 = _is_counter_T_15 & _is_counter_T_16; // @[package.scala:213:{47,55,60}]
wire is_counter_2 = _is_counter_T_14 | _is_counter_T_17; // @[package.scala:213:55]
wire _allow_wfi_T_15 = _allow_wfi_T_14; // @[CSR.scala:906:{42,61}]
wire _allow_wfi_T_16 = ~reg_mstatus_tw; // @[CSR.scala:395:28, :906:74]
wire _allow_wfi_T_20 = _allow_wfi_T_16; // @[CSR.scala:906:{74,90}]
wire _allow_wfi_T_17 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94]
wire allow_wfi_2 = _allow_wfi_T_15 | _allow_wfi_T_20; // @[CSR.scala:906:{42,71,90}]
wire _allow_sfence_vma_T_9 = _allow_sfence_vma_T_8; // @[CSR.scala:907:{41,60}]
wire _allow_sfence_vma_T_11 = ~_allow_sfence_vma_T_10; // @[CSR.scala:907:{73,77}]
wire allow_sfence_vma_2 = _allow_sfence_vma_T_9 | _allow_sfence_vma_T_11; // @[CSR.scala:907:{41,70,73}]
wire _allow_hfence_vvma_T_6 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :908:53]
wire _allow_hfence_vvma_T_7 = |reg_mstatus_prv; // @[CSR.scala:395:28, :908:88]
wire _allow_hfence_vvma_T_8 = _allow_hfence_vvma_T_6 & _allow_hfence_vvma_T_7; // @[CSR.scala:908:{53,68,88}]
wire _allow_hlsv_T_8 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :909:46]
wire _allow_hlsv_T_9 = |reg_mstatus_prv; // @[CSR.scala:395:28, :908:88, :909:81]
wire _allow_hlsv_T_10 = _allow_hlsv_T_9; // @[CSR.scala:909:{81,92}]
wire _allow_hlsv_T_11 = _allow_hlsv_T_8 & _allow_hlsv_T_10; // @[CSR.scala:909:{46,61,92}]
wire _allow_sret_T_9 = _allow_sret_T_8; // @[CSR.scala:910:{43,62}]
wire _allow_sret_T_11 = ~_allow_sret_T_10; // @[CSR.scala:910:{75,79}]
wire allow_sret_2 = _allow_sret_T_9 | _allow_sret_T_11; // @[CSR.scala:910:{43,72,75}]
wire [4:0] counter_addr_2 = addr_2[4:0]; // @[CSR.scala:897:27, :911:28]
wire [31:0] _GEN_17 = {27'h0, counter_addr_2}; // @[CSR.scala:911:28, :912:70]
wire [31:0] _GEN_18 = read_mcounteren >> _GEN_17; // @[CSR.scala:532:14, :912:70]
wire [31:0] _allow_counter_T_35; // @[CSR.scala:912:70]
assign _allow_counter_T_35 = _GEN_18; // @[CSR.scala:912:70]
wire [31:0] _io_decode_2_virtual_access_illegal_T_3; // @[CSR.scala:945:36]
assign _io_decode_2_virtual_access_illegal_T_3 = _GEN_18; // @[CSR.scala:912:70, :945:36]
wire _allow_counter_T_36 = _allow_counter_T_35[0]; // @[CSR.scala:912:70]
wire _allow_counter_T_37 = _allow_counter_T_34 | _allow_counter_T_36; // @[CSR.scala:912:{42,52,70}]
wire _allow_counter_T_39 = |reg_mstatus_prv; // @[CSR.scala:395:28, :908:88, :913:46]
wire _allow_counter_T_40 = _allow_counter_T_39; // @[CSR.scala:913:{27,46}]
wire [31:0] _GEN_19 = read_scounteren >> _GEN_17; // @[CSR.scala:536:14, :912:70, :913:75]
wire [31:0] _allow_counter_T_41; // @[CSR.scala:913:75]
assign _allow_counter_T_41 = _GEN_19; // @[CSR.scala:913:75]
wire [31:0] _io_decode_2_virtual_access_illegal_T_11; // @[CSR.scala:945:128]
assign _io_decode_2_virtual_access_illegal_T_11 = _GEN_19; // @[CSR.scala:913:75, :945:128]
wire _allow_counter_T_42 = _allow_counter_T_41[0]; // @[CSR.scala:913:75]
wire _allow_counter_T_43 = _allow_counter_T_40 | _allow_counter_T_42; // @[CSR.scala:913:{27,57,75}]
wire _allow_counter_T_44 = _allow_counter_T_37 & _allow_counter_T_43; // @[CSR.scala:912:{52,86}, :913:57]
wire allow_counter_2 = _allow_counter_T_44; // @[CSR.scala:912:86, :913:91]
wire _allow_counter_T_46 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :914:30]
wire [31:0] _GEN_20 = 32'h0 >> _GEN_17; // @[CSR.scala:912:70, :914:63]
wire [31:0] _allow_counter_T_48; // @[CSR.scala:914:63]
assign _allow_counter_T_48 = _GEN_20; // @[CSR.scala:914:63]
wire [31:0] _io_decode_2_virtual_access_illegal_T_6; // @[CSR.scala:945:71]
assign _io_decode_2_virtual_access_illegal_T_6 = _GEN_20; // @[CSR.scala:914:63, :945:71]
wire _allow_counter_T_49 = _allow_counter_T_48[0]; // @[CSR.scala:914:63]
wire _io_decode_2_fp_illegal_T_3 = _io_decode_2_fp_illegal_T; // @[CSR.scala:915:{39,47}]
assign _io_decode_2_fp_illegal_T_6 = _io_decode_2_fp_illegal_T_3; // @[CSR.scala:915:{47,91}]
assign io_decode_2_fp_illegal_0 = _io_decode_2_fp_illegal_T_6; // @[CSR.scala:377:7, :915:91]
wire _io_decode_2_vector_illegal_T_2 = reg_mstatus_v & _io_decode_2_vector_illegal_T_1; // @[CSR.scala:395:28, :916:{68,87}]
wire [11:0] io_decode_2_fp_csr_invInputs = ~io_decode_2_fp_csr_plaInput; // @[pla.scala:77:22, :78:21]
wire io_decode_2_fp_csr_invMatrixOutputs; // @[pla.scala:124:31]
wire io_decode_2_fp_csr_plaOutput; // @[pla.scala:81:23]
assign _io_decode_2_fp_csr_T = io_decode_2_fp_csr_plaOutput; // @[pla.scala:81:23]
wire io_decode_2_fp_csr_andMatrixOutputs_andMatrixInput_0 = io_decode_2_fp_csr_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire io_decode_2_fp_csr_andMatrixOutputs_andMatrixInput_1 = io_decode_2_fp_csr_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire io_decode_2_fp_csr_andMatrixOutputs_andMatrixInput_2 = io_decode_2_fp_csr_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire io_decode_2_fp_csr_andMatrixOutputs_andMatrixInput_3 = io_decode_2_fp_csr_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire [1:0] io_decode_2_fp_csr_andMatrixOutputs_lo = {io_decode_2_fp_csr_andMatrixOutputs_andMatrixInput_2, io_decode_2_fp_csr_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] io_decode_2_fp_csr_andMatrixOutputs_hi = {io_decode_2_fp_csr_andMatrixOutputs_andMatrixInput_0, io_decode_2_fp_csr_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53]
wire [3:0] _io_decode_2_fp_csr_andMatrixOutputs_T = {io_decode_2_fp_csr_andMatrixOutputs_hi, io_decode_2_fp_csr_andMatrixOutputs_lo}; // @[pla.scala:98:53]
wire io_decode_2_fp_csr_andMatrixOutputs_0_2 = &_io_decode_2_fp_csr_andMatrixOutputs_T; // @[pla.scala:98:{53,70}]
wire io_decode_2_fp_csr_orMatrixOutputs = io_decode_2_fp_csr_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36]
assign io_decode_2_fp_csr_invMatrixOutputs = io_decode_2_fp_csr_orMatrixOutputs; // @[pla.scala:114:36, :124:31]
assign io_decode_2_fp_csr_plaOutput = io_decode_2_fp_csr_invMatrixOutputs; // @[pla.scala:81:23, :124:31]
assign io_decode_2_fp_csr_0 = _io_decode_2_fp_csr_T; // @[Decode.scala:55:116]
wire [11:0] io_decode_2_vector_csr_invInputs = ~io_decode_2_vector_csr_plaInput; // @[pla.scala:77:22, :78:21]
wire [1:0] _csr_addr_legal_T_18 = addr_2[9:8]; // @[CSR.scala:190:36, :897:27]
wire [1:0] _csr_addr_legal_T_24 = addr_2[9:8]; // @[CSR.scala:190:36, :897:27]
wire [1:0] _io_decode_2_virtual_access_illegal_T_1 = addr_2[9:8]; // @[CSR.scala:190:36, :897:27]
wire [1:0] _io_decode_2_virtual_access_illegal_T_18 = addr_2[9:8]; // @[CSR.scala:190:36, :897:27]
wire [1:0] _io_decode_2_virtual_system_illegal_T_9 = addr_2[9:8]; // @[CSR.scala:190:36, :897:27]
wire _csr_addr_legal_T_19 = reg_mstatus_prv >= _csr_addr_legal_T_18; // @[CSR.scala:190:36, :395:28, :920:42]
wire csr_addr_legal_2 = _csr_addr_legal_T_19; // @[CSR.scala:920:{42,60}]
wire _csr_addr_legal_T_20 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :921:28]
wire _csr_addr_legal_T_25 = _csr_addr_legal_T_24 == 2'h2; // @[CSR.scala:190:36, :921:92]
wire _csr_exists_T_604 = addr_2 == 12'h7A0; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_605 = addr_2 == 12'h7A1; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_606 = addr_2 == 12'h7A2; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_607 = addr_2 == 12'h7A3; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_608 = addr_2 == 12'h301; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_609 = addr_2 == 12'h300; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_610 = addr_2 == 12'h305; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_611 = addr_2 == 12'h344; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_612 = addr_2 == 12'h304; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_613 = addr_2 == 12'h340; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_614 = addr_2 == 12'h341; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_615 = addr_2 == 12'h343; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_616 = addr_2 == 12'h342; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_617 = addr_2 == 12'hF14; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_618 = addr_2 == 12'h7B0; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_619 = addr_2 == 12'h7B1; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_620 = addr_2 == 12'h7B2; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_621 = addr_2 == 12'h1; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_622 = addr_2 == 12'h2; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_623 = addr_2 == 12'h3; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_624 = addr_2 == 12'h320; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_625 = addr_2 == 12'hB00; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_626 = addr_2 == 12'hB02; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_627 = addr_2 == 12'h323; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_628 = addr_2 == 12'hB03; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_629 = addr_2 == 12'hC03; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_630 = addr_2 == 12'h324; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_631 = addr_2 == 12'hB04; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_632 = addr_2 == 12'hC04; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_633 = addr_2 == 12'h325; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_634 = addr_2 == 12'hB05; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_635 = addr_2 == 12'hC05; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_636 = addr_2 == 12'h326; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_637 = addr_2 == 12'hB06; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_638 = addr_2 == 12'hC06; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_639 = addr_2 == 12'h327; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_640 = addr_2 == 12'hB07; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_641 = addr_2 == 12'hC07; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_642 = addr_2 == 12'h328; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_643 = addr_2 == 12'hB08; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_644 = addr_2 == 12'hC08; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_645 = addr_2 == 12'h329; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_646 = addr_2 == 12'hB09; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_647 = addr_2 == 12'hC09; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_648 = addr_2 == 12'h32A; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_649 = addr_2 == 12'hB0A; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_650 = addr_2 == 12'hC0A; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_651 = addr_2 == 12'h32B; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_652 = addr_2 == 12'hB0B; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_653 = addr_2 == 12'hC0B; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_654 = addr_2 == 12'h32C; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_655 = addr_2 == 12'hB0C; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_656 = addr_2 == 12'hC0C; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_657 = addr_2 == 12'h32D; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_658 = addr_2 == 12'hB0D; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_659 = addr_2 == 12'hC0D; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_660 = addr_2 == 12'h32E; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_661 = addr_2 == 12'hB0E; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_662 = addr_2 == 12'hC0E; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_663 = addr_2 == 12'h32F; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_664 = addr_2 == 12'hB0F; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_665 = addr_2 == 12'hC0F; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_666 = addr_2 == 12'h330; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_667 = addr_2 == 12'hB10; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_668 = addr_2 == 12'hC10; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_669 = addr_2 == 12'h331; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_670 = addr_2 == 12'hB11; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_671 = addr_2 == 12'hC11; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_672 = addr_2 == 12'h332; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_673 = addr_2 == 12'hB12; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_674 = addr_2 == 12'hC12; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_675 = addr_2 == 12'h333; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_676 = addr_2 == 12'hB13; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_677 = addr_2 == 12'hC13; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_678 = addr_2 == 12'h334; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_679 = addr_2 == 12'hB14; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_680 = addr_2 == 12'hC14; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_681 = addr_2 == 12'h335; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_682 = addr_2 == 12'hB15; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_683 = addr_2 == 12'hC15; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_684 = addr_2 == 12'h336; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_685 = addr_2 == 12'hB16; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_686 = addr_2 == 12'hC16; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_687 = addr_2 == 12'h337; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_688 = addr_2 == 12'hB17; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_689 = addr_2 == 12'hC17; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_690 = addr_2 == 12'h338; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_691 = addr_2 == 12'hB18; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_692 = addr_2 == 12'hC18; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_693 = addr_2 == 12'h339; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_694 = addr_2 == 12'hB19; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_695 = addr_2 == 12'hC19; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_696 = addr_2 == 12'h33A; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_697 = addr_2 == 12'hB1A; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_698 = addr_2 == 12'hC1A; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_699 = addr_2 == 12'h33B; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_700 = addr_2 == 12'hB1B; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_701 = addr_2 == 12'hC1B; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_702 = addr_2 == 12'h33C; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_703 = addr_2 == 12'hB1C; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_704 = addr_2 == 12'hC1C; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_705 = addr_2 == 12'h33D; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_706 = addr_2 == 12'hB1D; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_707 = addr_2 == 12'hC1D; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_708 = addr_2 == 12'h33E; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_709 = addr_2 == 12'hB1E; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_710 = addr_2 == 12'hC1E; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_711 = addr_2 == 12'h33F; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_712 = addr_2 == 12'hB1F; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_713 = addr_2 == 12'hC1F; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_714 = addr_2 == 12'h306; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_715 = addr_2 == 12'hC00; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_716 = addr_2 == 12'hC02; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_717 = addr_2 == 12'h30A; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_718 = addr_2 == 12'h100; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_719 = addr_2 == 12'h144; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_720 = addr_2 == 12'h104; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_721 = addr_2 == 12'h140; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_722 = addr_2 == 12'h142; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_723 = addr_2 == 12'h143; // @[CSR.scala:897:27, :899:93]
wire _GEN_21 = addr_2 == 12'h180; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_724; // @[CSR.scala:899:93]
assign _csr_exists_T_724 = _GEN_21; // @[CSR.scala:899:93]
wire _io_decode_2_read_illegal_T_3; // @[CSR.scala:925:14]
assign _io_decode_2_read_illegal_T_3 = _GEN_21; // @[CSR.scala:899:93, :925:14]
wire _io_decode_2_virtual_access_illegal_T_24; // @[CSR.scala:947:12]
assign _io_decode_2_virtual_access_illegal_T_24 = _GEN_21; // @[CSR.scala:899:93, :947:12]
wire _csr_exists_T_725 = addr_2 == 12'h141; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_726 = addr_2 == 12'h105; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_727 = addr_2 == 12'h106; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_728 = addr_2 == 12'h303; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_729 = addr_2 == 12'h302; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_730 = addr_2 == 12'h10A; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_731 = addr_2 == 12'h3A0; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_732 = addr_2 == 12'h3A2; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_733 = addr_2 == 12'h3B0; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_734 = addr_2 == 12'h3B1; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_735 = addr_2 == 12'h3B2; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_736 = addr_2 == 12'h3B3; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_737 = addr_2 == 12'h3B4; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_738 = addr_2 == 12'h3B5; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_739 = addr_2 == 12'h3B6; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_740 = addr_2 == 12'h3B7; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_741 = addr_2 == 12'h3B8; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_742 = addr_2 == 12'h3B9; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_743 = addr_2 == 12'h3BA; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_744 = addr_2 == 12'h3BB; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_745 = addr_2 == 12'h3BC; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_746 = addr_2 == 12'h3BD; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_747 = addr_2 == 12'h3BE; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_748 = addr_2 == 12'h3BF; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_749 = addr_2 == 12'h800; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_750 = addr_2 == 12'h808; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_751 = addr_2 == 12'h7C1; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_752 = addr_2 == 12'hF12; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_753 = addr_2 == 12'hF13; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_754 = addr_2 == 12'hF11; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_755 = addr_2 == 12'hF15; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_756 = _csr_exists_T_604 | _csr_exists_T_605; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_757 = _csr_exists_T_756 | _csr_exists_T_606; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_758 = _csr_exists_T_757 | _csr_exists_T_607; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_759 = _csr_exists_T_758 | _csr_exists_T_608; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_760 = _csr_exists_T_759 | _csr_exists_T_609; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_761 = _csr_exists_T_760 | _csr_exists_T_610; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_762 = _csr_exists_T_761 | _csr_exists_T_611; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_763 = _csr_exists_T_762 | _csr_exists_T_612; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_764 = _csr_exists_T_763 | _csr_exists_T_613; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_765 = _csr_exists_T_764 | _csr_exists_T_614; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_766 = _csr_exists_T_765 | _csr_exists_T_615; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_767 = _csr_exists_T_766 | _csr_exists_T_616; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_768 = _csr_exists_T_767 | _csr_exists_T_617; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_769 = _csr_exists_T_768 | _csr_exists_T_618; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_770 = _csr_exists_T_769 | _csr_exists_T_619; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_771 = _csr_exists_T_770 | _csr_exists_T_620; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_772 = _csr_exists_T_771 | _csr_exists_T_621; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_773 = _csr_exists_T_772 | _csr_exists_T_622; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_774 = _csr_exists_T_773 | _csr_exists_T_623; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_775 = _csr_exists_T_774 | _csr_exists_T_624; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_776 = _csr_exists_T_775 | _csr_exists_T_625; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_777 = _csr_exists_T_776 | _csr_exists_T_626; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_778 = _csr_exists_T_777 | _csr_exists_T_627; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_779 = _csr_exists_T_778 | _csr_exists_T_628; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_780 = _csr_exists_T_779 | _csr_exists_T_629; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_781 = _csr_exists_T_780 | _csr_exists_T_630; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_782 = _csr_exists_T_781 | _csr_exists_T_631; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_783 = _csr_exists_T_782 | _csr_exists_T_632; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_784 = _csr_exists_T_783 | _csr_exists_T_633; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_785 = _csr_exists_T_784 | _csr_exists_T_634; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_786 = _csr_exists_T_785 | _csr_exists_T_635; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_787 = _csr_exists_T_786 | _csr_exists_T_636; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_788 = _csr_exists_T_787 | _csr_exists_T_637; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_789 = _csr_exists_T_788 | _csr_exists_T_638; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_790 = _csr_exists_T_789 | _csr_exists_T_639; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_791 = _csr_exists_T_790 | _csr_exists_T_640; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_792 = _csr_exists_T_791 | _csr_exists_T_641; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_793 = _csr_exists_T_792 | _csr_exists_T_642; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_794 = _csr_exists_T_793 | _csr_exists_T_643; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_795 = _csr_exists_T_794 | _csr_exists_T_644; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_796 = _csr_exists_T_795 | _csr_exists_T_645; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_797 = _csr_exists_T_796 | _csr_exists_T_646; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_798 = _csr_exists_T_797 | _csr_exists_T_647; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_799 = _csr_exists_T_798 | _csr_exists_T_648; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_800 = _csr_exists_T_799 | _csr_exists_T_649; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_801 = _csr_exists_T_800 | _csr_exists_T_650; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_802 = _csr_exists_T_801 | _csr_exists_T_651; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_803 = _csr_exists_T_802 | _csr_exists_T_652; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_804 = _csr_exists_T_803 | _csr_exists_T_653; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_805 = _csr_exists_T_804 | _csr_exists_T_654; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_806 = _csr_exists_T_805 | _csr_exists_T_655; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_807 = _csr_exists_T_806 | _csr_exists_T_656; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_808 = _csr_exists_T_807 | _csr_exists_T_657; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_809 = _csr_exists_T_808 | _csr_exists_T_658; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_810 = _csr_exists_T_809 | _csr_exists_T_659; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_811 = _csr_exists_T_810 | _csr_exists_T_660; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_812 = _csr_exists_T_811 | _csr_exists_T_661; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_813 = _csr_exists_T_812 | _csr_exists_T_662; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_814 = _csr_exists_T_813 | _csr_exists_T_663; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_815 = _csr_exists_T_814 | _csr_exists_T_664; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_816 = _csr_exists_T_815 | _csr_exists_T_665; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_817 = _csr_exists_T_816 | _csr_exists_T_666; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_818 = _csr_exists_T_817 | _csr_exists_T_667; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_819 = _csr_exists_T_818 | _csr_exists_T_668; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_820 = _csr_exists_T_819 | _csr_exists_T_669; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_821 = _csr_exists_T_820 | _csr_exists_T_670; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_822 = _csr_exists_T_821 | _csr_exists_T_671; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_823 = _csr_exists_T_822 | _csr_exists_T_672; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_824 = _csr_exists_T_823 | _csr_exists_T_673; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_825 = _csr_exists_T_824 | _csr_exists_T_674; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_826 = _csr_exists_T_825 | _csr_exists_T_675; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_827 = _csr_exists_T_826 | _csr_exists_T_676; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_828 = _csr_exists_T_827 | _csr_exists_T_677; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_829 = _csr_exists_T_828 | _csr_exists_T_678; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_830 = _csr_exists_T_829 | _csr_exists_T_679; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_831 = _csr_exists_T_830 | _csr_exists_T_680; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_832 = _csr_exists_T_831 | _csr_exists_T_681; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_833 = _csr_exists_T_832 | _csr_exists_T_682; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_834 = _csr_exists_T_833 | _csr_exists_T_683; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_835 = _csr_exists_T_834 | _csr_exists_T_684; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_836 = _csr_exists_T_835 | _csr_exists_T_685; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_837 = _csr_exists_T_836 | _csr_exists_T_686; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_838 = _csr_exists_T_837 | _csr_exists_T_687; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_839 = _csr_exists_T_838 | _csr_exists_T_688; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_840 = _csr_exists_T_839 | _csr_exists_T_689; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_841 = _csr_exists_T_840 | _csr_exists_T_690; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_842 = _csr_exists_T_841 | _csr_exists_T_691; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_843 = _csr_exists_T_842 | _csr_exists_T_692; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_844 = _csr_exists_T_843 | _csr_exists_T_693; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_845 = _csr_exists_T_844 | _csr_exists_T_694; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_846 = _csr_exists_T_845 | _csr_exists_T_695; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_847 = _csr_exists_T_846 | _csr_exists_T_696; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_848 = _csr_exists_T_847 | _csr_exists_T_697; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_849 = _csr_exists_T_848 | _csr_exists_T_698; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_850 = _csr_exists_T_849 | _csr_exists_T_699; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_851 = _csr_exists_T_850 | _csr_exists_T_700; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_852 = _csr_exists_T_851 | _csr_exists_T_701; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_853 = _csr_exists_T_852 | _csr_exists_T_702; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_854 = _csr_exists_T_853 | _csr_exists_T_703; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_855 = _csr_exists_T_854 | _csr_exists_T_704; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_856 = _csr_exists_T_855 | _csr_exists_T_705; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_857 = _csr_exists_T_856 | _csr_exists_T_706; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_858 = _csr_exists_T_857 | _csr_exists_T_707; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_859 = _csr_exists_T_858 | _csr_exists_T_708; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_860 = _csr_exists_T_859 | _csr_exists_T_709; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_861 = _csr_exists_T_860 | _csr_exists_T_710; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_862 = _csr_exists_T_861 | _csr_exists_T_711; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_863 = _csr_exists_T_862 | _csr_exists_T_712; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_864 = _csr_exists_T_863 | _csr_exists_T_713; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_865 = _csr_exists_T_864 | _csr_exists_T_714; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_866 = _csr_exists_T_865 | _csr_exists_T_715; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_867 = _csr_exists_T_866 | _csr_exists_T_716; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_868 = _csr_exists_T_867 | _csr_exists_T_717; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_869 = _csr_exists_T_868 | _csr_exists_T_718; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_870 = _csr_exists_T_869 | _csr_exists_T_719; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_871 = _csr_exists_T_870 | _csr_exists_T_720; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_872 = _csr_exists_T_871 | _csr_exists_T_721; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_873 = _csr_exists_T_872 | _csr_exists_T_722; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_874 = _csr_exists_T_873 | _csr_exists_T_723; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_875 = _csr_exists_T_874 | _csr_exists_T_724; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_876 = _csr_exists_T_875 | _csr_exists_T_725; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_877 = _csr_exists_T_876 | _csr_exists_T_726; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_878 = _csr_exists_T_877 | _csr_exists_T_727; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_879 = _csr_exists_T_878 | _csr_exists_T_728; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_880 = _csr_exists_T_879 | _csr_exists_T_729; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_881 = _csr_exists_T_880 | _csr_exists_T_730; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_882 = _csr_exists_T_881 | _csr_exists_T_731; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_883 = _csr_exists_T_882 | _csr_exists_T_732; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_884 = _csr_exists_T_883 | _csr_exists_T_733; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_885 = _csr_exists_T_884 | _csr_exists_T_734; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_886 = _csr_exists_T_885 | _csr_exists_T_735; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_887 = _csr_exists_T_886 | _csr_exists_T_736; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_888 = _csr_exists_T_887 | _csr_exists_T_737; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_889 = _csr_exists_T_888 | _csr_exists_T_738; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_890 = _csr_exists_T_889 | _csr_exists_T_739; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_891 = _csr_exists_T_890 | _csr_exists_T_740; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_892 = _csr_exists_T_891 | _csr_exists_T_741; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_893 = _csr_exists_T_892 | _csr_exists_T_742; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_894 = _csr_exists_T_893 | _csr_exists_T_743; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_895 = _csr_exists_T_894 | _csr_exists_T_744; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_896 = _csr_exists_T_895 | _csr_exists_T_745; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_897 = _csr_exists_T_896 | _csr_exists_T_746; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_898 = _csr_exists_T_897 | _csr_exists_T_747; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_899 = _csr_exists_T_898 | _csr_exists_T_748; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_900 = _csr_exists_T_899 | _csr_exists_T_749; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_901 = _csr_exists_T_900 | _csr_exists_T_750; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_902 = _csr_exists_T_901 | _csr_exists_T_751; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_903 = _csr_exists_T_902 | _csr_exists_T_752; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_904 = _csr_exists_T_903 | _csr_exists_T_753; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_905 = _csr_exists_T_904 | _csr_exists_T_754; // @[CSR.scala:899:{93,111}]
wire csr_exists_2 = _csr_exists_T_905 | _csr_exists_T_755; // @[CSR.scala:899:{93,111}]
wire _io_decode_2_read_illegal_T = ~csr_addr_legal_2; // @[CSR.scala:920:60, :923:28]
wire _io_decode_2_read_illegal_T_1 = ~csr_exists_2; // @[CSR.scala:899:111, :924:7]
wire _io_decode_2_read_illegal_T_2 = _io_decode_2_read_illegal_T | _io_decode_2_read_illegal_T_1; // @[CSR.scala:923:{28,44}, :924:7]
wire _io_decode_2_read_illegal_T_4 = addr_2 == 12'h680; // @[CSR.scala:897:27, :925:38]
wire _io_decode_2_read_illegal_T_5 = _io_decode_2_read_illegal_T_3 | _io_decode_2_read_illegal_T_4; // @[CSR.scala:925:{14,30,38}]
wire _io_decode_2_read_illegal_T_6 = ~allow_sfence_vma_2; // @[CSR.scala:907:70, :925:59]
wire _io_decode_2_read_illegal_T_7 = _io_decode_2_read_illegal_T_5 & _io_decode_2_read_illegal_T_6; // @[CSR.scala:925:{30,56,59}]
wire _io_decode_2_read_illegal_T_8 = _io_decode_2_read_illegal_T_2 | _io_decode_2_read_illegal_T_7; // @[CSR.scala:923:44, :924:19, :925:56]
wire _io_decode_2_read_illegal_T_9 = ~allow_counter_2; // @[CSR.scala:913:91, :926:21]
wire _io_decode_2_read_illegal_T_10 = is_counter_2 & _io_decode_2_read_illegal_T_9; // @[CSR.scala:904:81, :926:{18,21}]
wire _io_decode_2_read_illegal_T_11 = _io_decode_2_read_illegal_T_8 | _io_decode_2_read_illegal_T_10; // @[CSR.scala:924:19, :925:78, :926:18]
wire [11:0] io_decode_2_read_illegal_invInputs = ~io_decode_2_read_illegal_plaInput; // @[pla.scala:77:22, :78:21]
wire io_decode_2_read_illegal_invMatrixOutputs; // @[pla.scala:124:31]
wire io_decode_2_read_illegal_plaOutput; // @[pla.scala:81:23]
wire _io_decode_2_read_illegal_T_12 = io_decode_2_read_illegal_plaOutput; // @[pla.scala:81:23]
wire io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_0 = io_decode_2_read_illegal_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_1 = io_decode_2_read_illegal_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_2 = io_decode_2_read_illegal_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_3 = io_decode_2_read_illegal_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_4 = io_decode_2_read_illegal_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_5 = io_decode_2_read_illegal_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_6 = io_decode_2_read_illegal_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_7 = io_decode_2_read_illegal_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire [1:0] io_decode_2_read_illegal_andMatrixOutputs_lo_lo = {io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_6, io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] io_decode_2_read_illegal_andMatrixOutputs_lo_hi = {io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_4, io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:90:45, :98:53]
wire [3:0] io_decode_2_read_illegal_andMatrixOutputs_lo = {io_decode_2_read_illegal_andMatrixOutputs_lo_hi, io_decode_2_read_illegal_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53]
wire [1:0] io_decode_2_read_illegal_andMatrixOutputs_hi_lo = {io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_2, io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] io_decode_2_read_illegal_andMatrixOutputs_hi_hi = {io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_0, io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53]
wire [3:0] io_decode_2_read_illegal_andMatrixOutputs_hi = {io_decode_2_read_illegal_andMatrixOutputs_hi_hi, io_decode_2_read_illegal_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53]
wire [7:0] _io_decode_2_read_illegal_andMatrixOutputs_T = {io_decode_2_read_illegal_andMatrixOutputs_hi, io_decode_2_read_illegal_andMatrixOutputs_lo}; // @[pla.scala:98:53]
wire io_decode_2_read_illegal_andMatrixOutputs_0_2 = &_io_decode_2_read_illegal_andMatrixOutputs_T; // @[pla.scala:98:{53,70}]
wire io_decode_2_read_illegal_orMatrixOutputs = io_decode_2_read_illegal_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36]
assign io_decode_2_read_illegal_invMatrixOutputs = io_decode_2_read_illegal_orMatrixOutputs; // @[pla.scala:114:36, :124:31]
assign io_decode_2_read_illegal_plaOutput = io_decode_2_read_illegal_invMatrixOutputs; // @[pla.scala:81:23, :124:31]
wire _io_decode_2_read_illegal_T_13 = ~reg_debug; // @[CSR.scala:482:26, :927:45]
wire _io_decode_2_read_illegal_T_14 = _io_decode_2_read_illegal_T_12 & _io_decode_2_read_illegal_T_13; // @[Decode.scala:55:116]
wire _io_decode_2_read_illegal_T_15 = _io_decode_2_read_illegal_T_11 | _io_decode_2_read_illegal_T_14; // @[CSR.scala:925:78, :926:36, :927:42]
wire _io_decode_2_read_illegal_T_18 = _io_decode_2_read_illegal_T_15; // @[CSR.scala:926:36, :927:56]
wire [11:0] io_decode_2_read_illegal_invInputs_1 = ~io_decode_2_read_illegal_plaInput_1; // @[pla.scala:77:22, :78:21]
wire _io_decode_2_read_illegal_T_19 = io_decode_2_fp_csr_0 & io_decode_2_fp_illegal_0; // @[CSR.scala:377:7, :929:21]
assign _io_decode_2_read_illegal_T_20 = _io_decode_2_read_illegal_T_18 | _io_decode_2_read_illegal_T_19; // @[CSR.scala:927:56, :928:68, :929:21]
assign io_decode_2_read_illegal_0 = _io_decode_2_read_illegal_T_20; // @[CSR.scala:377:7, :928:68]
wire [1:0] _io_decode_2_write_illegal_T = addr_2[11:10]; // @[CSR.scala:897:27, :930:33]
assign _io_decode_2_write_illegal_T_1 = &_io_decode_2_write_illegal_T; // @[CSR.scala:930:{33,41}]
assign io_decode_2_write_illegal_0 = _io_decode_2_write_illegal_T_1; // @[CSR.scala:377:7, :930:41]
wire [11:0] io_decode_2_write_flush_addr_m = {_io_decode_2_write_illegal_T, addr_2[9:0] | 10'h300}; // @[CSR.scala:897:27, :930:33, :932:25]
wire _io_decode_2_write_flush_T = io_decode_2_write_flush_addr_m > 12'h33F; // @[CSR.scala:932:25, :933:16]
wire _io_decode_2_write_flush_T_1 = io_decode_2_write_flush_addr_m < 12'h344; // @[CSR.scala:932:25, :933:45]
wire _io_decode_2_write_flush_T_2 = _io_decode_2_write_flush_T & _io_decode_2_write_flush_T_1; // @[CSR.scala:933:{16,35,45}]
assign _io_decode_2_write_flush_T_3 = ~_io_decode_2_write_flush_T_2; // @[CSR.scala:933:{7,35}]
assign io_decode_2_write_flush_0 = _io_decode_2_write_flush_T_3; // @[CSR.scala:377:7, :933:7]
wire _io_decode_2_system_illegal_T = ~csr_addr_legal_2; // @[CSR.scala:920:60, :923:28, :935:30]
wire _io_decode_2_system_illegal_T_1 = ~is_hlsv_2; // @[CSR.scala:903:82, :935:49]
wire _io_decode_2_system_illegal_T_2 = _io_decode_2_system_illegal_T & _io_decode_2_system_illegal_T_1; // @[CSR.scala:935:{30,46,49}]
wire _io_decode_2_system_illegal_T_3 = ~allow_wfi_2; // @[CSR.scala:906:71, :936:17]
wire _io_decode_2_system_illegal_T_4 = is_wfi_2 & _io_decode_2_system_illegal_T_3; // @[CSR.scala:903:82, :936:{14,17}]
wire _io_decode_2_system_illegal_T_5 = _io_decode_2_system_illegal_T_2 | _io_decode_2_system_illegal_T_4; // @[CSR.scala:935:{46,58}, :936:14]
wire _io_decode_2_system_illegal_T_6 = ~allow_sret_2; // @[CSR.scala:910:72, :937:17]
wire _io_decode_2_system_illegal_T_7 = is_ret_2 & _io_decode_2_system_illegal_T_6; // @[CSR.scala:903:82, :937:{14,17}]
wire _io_decode_2_system_illegal_T_8 = _io_decode_2_system_illegal_T_5 | _io_decode_2_system_illegal_T_7; // @[CSR.scala:935:58, :936:28, :937:14]
wire _io_decode_2_system_illegal_T_9 = addr_2[10]; // @[CSR.scala:897:27, :938:21]
wire _io_decode_2_system_illegal_T_10 = is_ret_2 & _io_decode_2_system_illegal_T_9; // @[CSR.scala:903:82, :938:{14,21}]
wire _io_decode_2_system_illegal_T_11 = addr_2[7]; // @[CSR.scala:897:27, :938:33]
wire _io_decode_2_system_illegal_T_12 = _io_decode_2_system_illegal_T_10 & _io_decode_2_system_illegal_T_11; // @[CSR.scala:938:{14,26,33}]
wire _io_decode_2_system_illegal_T_13 = ~reg_debug; // @[CSR.scala:482:26, :927:45, :938:40]
wire _io_decode_2_system_illegal_T_14 = _io_decode_2_system_illegal_T_12 & _io_decode_2_system_illegal_T_13; // @[CSR.scala:938:{26,37,40}]
wire _io_decode_2_system_illegal_T_15 = _io_decode_2_system_illegal_T_8 | _io_decode_2_system_illegal_T_14; // @[CSR.scala:936:28, :937:29, :938:37]
wire _io_decode_2_system_illegal_T_16 = is_sfence_2 | is_hfence_gvma_2; // @[CSR.scala:903:82, :939:18]
wire _io_decode_2_system_illegal_T_17 = ~allow_sfence_vma_2; // @[CSR.scala:907:70, :925:59, :939:40]
wire _io_decode_2_system_illegal_T_18 = _io_decode_2_system_illegal_T_16 & _io_decode_2_system_illegal_T_17; // @[CSR.scala:939:{18,37,40}]
wire _io_decode_2_system_illegal_T_19 = _io_decode_2_system_illegal_T_15 | _io_decode_2_system_illegal_T_18; // @[CSR.scala:937:29, :938:51, :939:37]
wire _io_decode_2_system_illegal_T_22 = _io_decode_2_system_illegal_T_19; // @[CSR.scala:938:51, :939:58]
assign _io_decode_2_system_illegal_T_25 = _io_decode_2_system_illegal_T_22; // @[CSR.scala:939:58, :940:44]
assign io_decode_2_system_illegal_0 = _io_decode_2_system_illegal_T_25; // @[CSR.scala:377:7, :940:44]
wire _io_decode_2_virtual_access_illegal_T = reg_mstatus_v & csr_exists_2; // @[CSR.scala:395:28, :899:111, :943:52]
wire _io_decode_2_virtual_access_illegal_T_2 = _io_decode_2_virtual_access_illegal_T_1 == 2'h2; // @[CSR.scala:190:36, :944:22]
wire _io_decode_2_virtual_access_illegal_T_4 = _io_decode_2_virtual_access_illegal_T_3[0]; // @[CSR.scala:945:36]
wire _io_decode_2_virtual_access_illegal_T_5 = is_counter_2 & _io_decode_2_virtual_access_illegal_T_4; // @[CSR.scala:904:81, :945:{18,36}]
wire _io_decode_2_virtual_access_illegal_T_7 = _io_decode_2_virtual_access_illegal_T_6[0]; // @[CSR.scala:945:71]
wire _io_decode_2_virtual_access_illegal_T_8 = ~_io_decode_2_virtual_access_illegal_T_7; // @[CSR.scala:945:{55,71}]
wire _io_decode_2_virtual_access_illegal_T_10 = ~_io_decode_2_virtual_access_illegal_T_9; // @[CSR.scala:945:{89,105}]
wire _io_decode_2_virtual_access_illegal_T_12 = _io_decode_2_virtual_access_illegal_T_11[0]; // @[CSR.scala:945:128]
wire _io_decode_2_virtual_access_illegal_T_13 = ~_io_decode_2_virtual_access_illegal_T_12; // @[CSR.scala:945:{112,128}]
wire _io_decode_2_virtual_access_illegal_T_14 = _io_decode_2_virtual_access_illegal_T_10 & _io_decode_2_virtual_access_illegal_T_13; // @[CSR.scala:945:{89,109,112}]
wire _io_decode_2_virtual_access_illegal_T_15 = _io_decode_2_virtual_access_illegal_T_8 | _io_decode_2_virtual_access_illegal_T_14; // @[CSR.scala:945:{55,86,109}]
wire _io_decode_2_virtual_access_illegal_T_16 = _io_decode_2_virtual_access_illegal_T_5 & _io_decode_2_virtual_access_illegal_T_15; // @[CSR.scala:945:{18,51,86}]
wire _io_decode_2_virtual_access_illegal_T_17 = _io_decode_2_virtual_access_illegal_T_2 | _io_decode_2_virtual_access_illegal_T_16; // @[CSR.scala:944:{22,34}, :945:51]
wire _io_decode_2_virtual_access_illegal_T_19 = _io_decode_2_virtual_access_illegal_T_18 == 2'h1; // @[CSR.scala:190:36, :946:22]
wire _io_decode_2_virtual_access_illegal_T_21 = ~_io_decode_2_virtual_access_illegal_T_20; // @[CSR.scala:946:{37,53}]
wire _io_decode_2_virtual_access_illegal_T_22 = _io_decode_2_virtual_access_illegal_T_19 & _io_decode_2_virtual_access_illegal_T_21; // @[CSR.scala:946:{22,34,37}]
wire _io_decode_2_virtual_access_illegal_T_23 = _io_decode_2_virtual_access_illegal_T_17 | _io_decode_2_virtual_access_illegal_T_22; // @[CSR.scala:944:34, :945:144, :946:34]
wire _io_decode_2_virtual_access_illegal_T_28 = _io_decode_2_virtual_access_illegal_T_23; // @[CSR.scala:945:144, :946:57]
wire _io_decode_2_virtual_access_illegal_T_26 = _io_decode_2_virtual_access_illegal_T_24 & _io_decode_2_virtual_access_illegal_T_25; // @[CSR.scala:947:{12,28,46}]
assign _io_decode_2_virtual_access_illegal_T_29 = _io_decode_2_virtual_access_illegal_T & _io_decode_2_virtual_access_illegal_T_28; // @[CSR.scala:943:{52,66}, :946:57]
assign io_decode_2_virtual_access_illegal_0 = _io_decode_2_virtual_access_illegal_T_29; // @[CSR.scala:377:7, :943:66]
wire _io_decode_2_virtual_system_illegal_T = is_hfence_vvma_2 | is_hfence_gvma_2; // @[CSR.scala:903:82, :950:22]
wire _io_decode_2_virtual_system_illegal_T_1 = _io_decode_2_virtual_system_illegal_T | is_hlsv_2; // @[CSR.scala:903:82, :950:22, :951:22]
wire _io_decode_2_virtual_system_illegal_T_3 = ~_io_decode_2_virtual_system_illegal_T_2; // @[CSR.scala:953:{18,34}]
wire _io_decode_2_virtual_system_illegal_T_6 = _io_decode_2_virtual_system_illegal_T_3; // @[CSR.scala:953:{18,38}]
wire _io_decode_2_virtual_system_illegal_T_4 = ~reg_mstatus_tw; // @[CSR.scala:395:28, :906:74, :953:41]
wire _io_decode_2_virtual_system_illegal_T_7 = is_wfi_2 & _io_decode_2_virtual_system_illegal_T_6; // @[CSR.scala:903:82, :953:{14,38}]
wire _io_decode_2_virtual_system_illegal_T_8 = _io_decode_2_virtual_system_illegal_T_1 | _io_decode_2_virtual_system_illegal_T_7; // @[CSR.scala:951:22, :952:15, :953:14]
wire _io_decode_2_virtual_system_illegal_T_10 = _io_decode_2_virtual_system_illegal_T_9 == 2'h1; // @[CSR.scala:190:36, :954:32]
wire _io_decode_2_virtual_system_illegal_T_11 = is_ret_2 & _io_decode_2_virtual_system_illegal_T_10; // @[CSR.scala:903:82, :954:{14,32}]
wire _io_decode_2_virtual_system_illegal_T_13 = ~_io_decode_2_virtual_system_illegal_T_12; // @[CSR.scala:954:{48,64}]
wire _io_decode_2_virtual_system_illegal_T_14 = _io_decode_2_virtual_system_illegal_T_13; // @[CSR.scala:954:{48,68}]
wire _io_decode_2_virtual_system_illegal_T_15 = _io_decode_2_virtual_system_illegal_T_11 & _io_decode_2_virtual_system_illegal_T_14; // @[CSR.scala:954:{14,44,68}]
wire _io_decode_2_virtual_system_illegal_T_16 = _io_decode_2_virtual_system_illegal_T_8 | _io_decode_2_virtual_system_illegal_T_15; // @[CSR.scala:952:15, :953:77, :954:44]
wire _io_decode_2_virtual_system_illegal_T_18 = ~_io_decode_2_virtual_system_illegal_T_17; // @[CSR.scala:955:{21,37}]
wire _io_decode_2_virtual_system_illegal_T_19 = _io_decode_2_virtual_system_illegal_T_18; // @[CSR.scala:955:{21,41}]
wire _io_decode_2_virtual_system_illegal_T_20 = is_sfence_2 & _io_decode_2_virtual_system_illegal_T_19; // @[CSR.scala:903:82, :955:{17,41}]
wire _io_decode_2_virtual_system_illegal_T_21 = _io_decode_2_virtual_system_illegal_T_16 | _io_decode_2_virtual_system_illegal_T_20; // @[CSR.scala:953:77, :954:89, :955:17]
assign _io_decode_2_virtual_system_illegal_T_22 = reg_mstatus_v & _io_decode_2_virtual_system_illegal_T_21; // @[CSR.scala:395:28, :949:52, :954:89]
assign io_decode_2_virtual_system_illegal_0 = _io_decode_2_virtual_system_illegal_T_22; // @[CSR.scala:377:7, :949:52]
wire _cause_T_1 = _cause_T & reg_mstatus_v; // @[CSR.scala:395:28, :959:{61,65}]
wire [1:0] _cause_T_2 = _cause_T_1 ? 2'h2 : reg_mstatus_prv; // @[CSR.scala:395:28, :959:{45,65}]
wire [4:0] _cause_T_3 = {3'h0, _cause_T_2} + 5'h8; // @[CSR.scala:959:{40,45}]
wire [3:0] _cause_T_4 = _cause_T_3[3:0]; // @[CSR.scala:959:40]
wire [63:0] _cause_T_5 = insn_break ? 64'h3 : io_cause_0; // @[CSR.scala:377:7, :893:83, :960:14]
assign cause = insn_call ? {60'h0, _cause_T_4} : _cause_T_5; // @[CSR.scala:893:83, :959:{8,40}, :960:14]
assign io_trace_0_cause = cause; // @[CSR.scala:377:7, :959:8]
assign io_trace_1_cause = cause; // @[CSR.scala:377:7, :959:8]
assign io_trace_2_cause = cause; // @[CSR.scala:377:7, :959:8]
wire [7:0] cause_lsbs = cause[7:0]; // @[CSR.scala:959:8, :961:25]
wire [5:0] cause_deleg_lsbs = cause[5:0]; // @[CSR.scala:959:8, :962:31]
wire [5:0] _notDebugTVec_interruptOffset_T = cause[5:0]; // @[CSR.scala:959:8, :962:31, :979:32]
wire _causeIsDebugInt_T = cause[63]; // @[CSR.scala:959:8, :963:30]
wire _causeIsDebugTrigger_T = cause[63]; // @[CSR.scala:959:8, :963:30, :964:35]
wire _causeIsDebugBreak_T = cause[63]; // @[CSR.scala:959:8, :963:30, :965:33]
wire _delegate_T_2 = cause[63]; // @[CSR.scala:959:8, :963:30, :970:78]
wire _delegateVS_T_1 = cause[63]; // @[CSR.scala:959:8, :963:30, :971:58]
wire _notDebugTVec_doVector_T_1 = cause[63]; // @[CSR.scala:959:8, :963:30, :981:36]
wire _causeIsRnmiInt_T = cause[63]; // @[CSR.scala:959:8, :963:30, :985:29]
wire _causeIsRnmiBEU_T = cause[63]; // @[CSR.scala:959:8, :963:30, :986:29]
wire _reg_vscause_T = cause[63]; // @[CSR.scala:959:8, :963:30, :1060:31]
assign _io_trace_0_interrupt_T = cause[63]; // @[CSR.scala:959:8, :963:30, :1626:25]
assign _io_trace_1_interrupt_T = cause[63]; // @[CSR.scala:959:8, :963:30, :1626:25]
assign _io_trace_2_interrupt_T = cause[63]; // @[CSR.scala:959:8, :963:30, :1626:25]
wire _GEN_22 = cause_lsbs == 8'hE; // @[CSR.scala:961:25, :963:53]
wire _causeIsDebugInt_T_1; // @[CSR.scala:963:53]
assign _causeIsDebugInt_T_1 = _GEN_22; // @[CSR.scala:963:53]
wire _causeIsDebugTrigger_T_2; // @[CSR.scala:964:58]
assign _causeIsDebugTrigger_T_2 = _GEN_22; // @[CSR.scala:963:53, :964:58]
wire causeIsDebugInt = _causeIsDebugInt_T & _causeIsDebugInt_T_1; // @[CSR.scala:963:{30,39,53}]
wire _causeIsDebugTrigger_T_1 = ~_causeIsDebugTrigger_T; // @[CSR.scala:964:{29,35}]
wire causeIsDebugTrigger = _causeIsDebugTrigger_T_1 & _causeIsDebugTrigger_T_2; // @[CSR.scala:964:{29,44,58}]
wire _causeIsDebugBreak_T_1 = ~_causeIsDebugBreak_T; // @[CSR.scala:965:{27,33}]
wire _causeIsDebugBreak_T_2 = _causeIsDebugBreak_T_1 & insn_break; // @[CSR.scala:893:83, :965:{27,42}]
wire [1:0] causeIsDebugBreak_lo = {reg_dcsr_ebreaks, reg_dcsr_ebreaku}; // @[CSR.scala:403:25, :965:62]
wire [1:0] causeIsDebugBreak_hi = {reg_dcsr_ebreakm, 1'h0}; // @[CSR.scala:403:25, :965:62]
wire [3:0] _causeIsDebugBreak_T_3 = {causeIsDebugBreak_hi, causeIsDebugBreak_lo}; // @[CSR.scala:965:62]
wire [3:0] _causeIsDebugBreak_T_4 = _causeIsDebugBreak_T_3 >> reg_mstatus_prv; // @[CSR.scala:395:28, :965:{62,134}]
wire _causeIsDebugBreak_T_5 = _causeIsDebugBreak_T_4[0]; // @[CSR.scala:965:134]
wire causeIsDebugBreak = _causeIsDebugBreak_T_2 & _causeIsDebugBreak_T_5; // @[CSR.scala:965:{42,56,134}]
wire _trapToDebug_T = reg_singleStepped | causeIsDebugInt; // @[CSR.scala:486:30, :963:39, :966:56]
wire _trapToDebug_T_1 = _trapToDebug_T | causeIsDebugTrigger; // @[CSR.scala:964:44, :966:{56,75}]
wire _trapToDebug_T_2 = _trapToDebug_T_1 | causeIsDebugBreak; // @[CSR.scala:965:56, :966:{75,98}]
wire _trapToDebug_T_3 = _trapToDebug_T_2 | reg_debug; // @[CSR.scala:482:26, :966:{98,119}]
wire trapToDebug = _trapToDebug_T_3; // @[CSR.scala:966:{34,119}]
wire [11:0] _debugTVec_T = {8'h80, ~insn_break, 3'h0}; // @[CSR.scala:893:83, :969:37]
wire [11:0] debugTVec = reg_debug ? _debugTVec_T : 12'h800; // @[CSR.scala:482:26, :969:{22,37}]
wire _delegate_T = ~(reg_mstatus_prv[1]); // @[CSR.scala:395:28, :620:51, :970:55]
wire _delegate_T_1 = _delegate_T; // @[CSR.scala:970:{36,55}]
wire [63:0] _GEN_23 = {58'h0, cause_deleg_lsbs}; // @[CSR.scala:962:31, :970:100]
wire [63:0] _delegate_T_3 = read_mideleg >> _GEN_23; // @[CSR.scala:498:14, :970:100]
wire _delegate_T_4 = _delegate_T_3[0]; // @[CSR.scala:970:100]
wire [63:0] _delegate_T_5 = read_medeleg >> _GEN_23; // @[CSR.scala:502:14, :970:{100,132}]
wire _delegate_T_6 = _delegate_T_5[0]; // @[CSR.scala:970:132]
wire _delegate_T_7 = _delegate_T_2 ? _delegate_T_4 : _delegate_T_6; // @[CSR.scala:970:{72,78,100,132}]
wire delegate = _delegate_T_1 & _delegate_T_7; // @[CSR.scala:970:{36,66,72}]
wire _delegateVS_T = reg_mstatus_v & delegate; // @[CSR.scala:395:28, :970:66, :971:34]
wire [63:0] _GEN_24 = 64'h0 >> _GEN_23; // @[CSR.scala:970:100, :971:80]
wire [63:0] _delegateVS_T_2; // @[CSR.scala:971:80]
assign _delegateVS_T_2 = _GEN_24; // @[CSR.scala:971:80]
wire [63:0] _delegateVS_T_4; // @[CSR.scala:971:112]
assign _delegateVS_T_4 = _GEN_24; // @[CSR.scala:971:{80,112}]
wire _delegateVS_T_3 = _delegateVS_T_2[0]; // @[CSR.scala:971:80]
wire _delegateVS_T_5 = _delegateVS_T_4[0]; // @[CSR.scala:971:112]
wire _delegateVS_T_6 = _delegateVS_T_1 ? _delegateVS_T_3 : _delegateVS_T_5; // @[CSR.scala:971:{52,58,80,112}]
wire delegateVS = _delegateVS_T & _delegateVS_T_6; // @[CSR.scala:971:{34,46,52}]
wire [63:0] _notDebugTVec_base_T = delegateVS ? read_vstvec : read_stvec; // @[package.scala:132:15]
wire [63:0] notDebugTVec_base = delegate ? _notDebugTVec_base_T : read_mtvec; // @[package.scala:138:15]
wire [7:0] notDebugTVec_interruptOffset = {_notDebugTVec_interruptOffset_T, 2'h0}; // @[CSR.scala:979:{32,59}]
wire [55:0] _notDebugTVec_interruptVec_T = notDebugTVec_base[63:8]; // @[CSR.scala:978:19, :980:33]
wire [63:0] notDebugTVec_interruptVec = {_notDebugTVec_interruptVec_T, notDebugTVec_interruptOffset}; // @[CSR.scala:979:59, :980:{27,33}]
wire _notDebugTVec_doVector_T = notDebugTVec_base[0]; // @[CSR.scala:978:19, :981:24]
wire _notDebugTVec_doVector_T_2 = _notDebugTVec_doVector_T & _notDebugTVec_doVector_T_1; // @[CSR.scala:981:{24,28,36}]
wire [1:0] _notDebugTVec_doVector_T_3 = cause_lsbs[7:6]; // @[CSR.scala:961:25, :981:70]
wire _notDebugTVec_doVector_T_4 = _notDebugTVec_doVector_T_3 == 2'h0; // @[CSR.scala:981:{70,94}]
wire notDebugTVec_doVector = _notDebugTVec_doVector_T_2 & _notDebugTVec_doVector_T_4; // @[CSR.scala:981:{28,55,94}]
wire [61:0] _notDebugTVec_T = notDebugTVec_base[63:2]; // @[CSR.scala:978:19, :982:38]
wire [63:0] _notDebugTVec_T_1 = {_notDebugTVec_T, 2'h0}; // @[CSR.scala:982:{38,56}]
wire [63:0] notDebugTVec = notDebugTVec_doVector ? notDebugTVec_interruptVec : _notDebugTVec_T_1; // @[CSR.scala:980:27, :981:55, :982:{8,56}]
wire [63:0] _tvec_T = notDebugTVec; // @[CSR.scala:982:8, :995:45]
wire _causeIsRnmiInt_T_1 = cause[62]; // @[CSR.scala:959:8, :985:46]
wire _causeIsRnmiBEU_T_1 = cause[62]; // @[CSR.scala:959:8, :985:46, :986:46]
wire _causeIsRnmiInt_T_2 = _causeIsRnmiInt_T & _causeIsRnmiInt_T_1; // @[CSR.scala:985:{29,38,46}]
wire _causeIsRnmiInt_T_3 = cause_lsbs == 8'hD; // @[CSR.scala:961:25, :985:70]
wire _GEN_25 = cause_lsbs == 8'hC; // @[CSR.scala:961:25, :985:107]
wire _causeIsRnmiInt_T_4; // @[CSR.scala:985:107]
assign _causeIsRnmiInt_T_4 = _GEN_25; // @[CSR.scala:985:107]
wire _causeIsRnmiBEU_T_3; // @[CSR.scala:986:69]
assign _causeIsRnmiBEU_T_3 = _GEN_25; // @[CSR.scala:985:107, :986:69]
wire _causeIsRnmiInt_T_5 = _causeIsRnmiInt_T_3 | _causeIsRnmiInt_T_4; // @[CSR.scala:985:{70,93,107}]
wire causeIsRnmiInt = _causeIsRnmiInt_T_2 & _causeIsRnmiInt_T_5; // @[CSR.scala:985:{38,55,93}]
wire _causeIsRnmiBEU_T_2 = _causeIsRnmiBEU_T & _causeIsRnmiBEU_T_1; // @[CSR.scala:986:{29,38,46}]
wire causeIsRnmiBEU = _causeIsRnmiBEU_T_2 & _causeIsRnmiBEU_T_3; // @[CSR.scala:986:{38,55,69}]
wire [63:0] tvec = trapToDebug ? {52'h0, debugTVec} : _tvec_T; // @[CSR.scala:966:34, :969:22, :995:{17,45}]
wire _GEN_26 = insn_call | insn_break; // @[CSR.scala:893:83, :1000:24]
wire _io_eret_T; // @[CSR.scala:1000:24]
assign _io_eret_T = _GEN_26; // @[CSR.scala:1000:24]
wire _exception_T; // @[CSR.scala:1020:29]
assign _exception_T = _GEN_26; // @[CSR.scala:1000:24, :1020:29]
assign _io_eret_T_1 = _io_eret_T | insn_ret; // @[CSR.scala:893:83, :1000:{24,38}]
assign io_eret = _io_eret_T_1; // @[CSR.scala:377:7, :1000:38]
wire _io_singleStep_T = ~reg_debug; // @[CSR.scala:482:26, :927:45, :1001:37]
assign _io_singleStep_T_1 = reg_dcsr_step & _io_singleStep_T; // @[CSR.scala:403:25, :1001:{34,37}]
assign io_singleStep_0 = _io_singleStep_T_1; // @[CSR.scala:377:7, :1001:34]
wire _io_status_sd_T = &io_status_fs_0; // @[CSR.scala:377:7, :1003:32]
wire _io_status_sd_T_2 = _io_status_sd_T; // @[CSR.scala:1003:{32,37}]
assign _io_status_sd_T_4 = _io_status_sd_T_2; // @[CSR.scala:1003:{37,58}]
assign io_status_sd_0 = _io_status_sd_T_4; // @[CSR.scala:377:7, :1003:58]
wire _io_status_dprv_T = ~reg_debug; // @[CSR.scala:482:26, :927:45, :1008:45]
wire _io_status_dprv_T_1 = reg_mstatus_mprv & _io_status_dprv_T; // @[CSR.scala:395:28, :1008:{42,45}]
assign _io_status_dprv_T_2 = _io_status_dprv_T_1 ? reg_mstatus_mpp : reg_mstatus_prv; // @[CSR.scala:395:28, :1008:{24,42}]
assign io_status_dprv_0 = _io_status_dprv_T_2; // @[CSR.scala:377:7, :1008:24]
wire _io_status_dv_T = ~reg_debug; // @[CSR.scala:482:26, :927:45, :1009:60]
wire _io_status_dv_T_1 = reg_mstatus_mprv & _io_status_dv_T; // @[CSR.scala:395:28, :1009:{57,60}]
wire _io_status_dv_T_2 = _io_status_dv_T_1 & reg_mstatus_mpv; // @[CSR.scala:395:28, :1009:{39,57}]
assign _io_status_dv_T_3 = reg_mstatus_v | _io_status_dv_T_2; // @[CSR.scala:395:28, :1009:{33,39}]
assign io_status_dv_0 = _io_status_dv_T_3; // @[CSR.scala:377:7, :1009:33]
wire _io_gstatus_sd_T_3 = &io_gstatus_vs; // @[CSR.scala:377:7, :1016:78]
wire exception = _exception_T | io_exception_0; // @[CSR.scala:377:7, :1020:{29,43}]
wire _en_T_8 = exception; // @[CSR.scala:1020:43, :1096:24]
wire _en_T_20 = exception; // @[CSR.scala:1020:43, :1096:24]
wire _en_T_32 = exception; // @[CSR.scala:1020:43, :1096:24]
wire _en_T_44 = exception; // @[CSR.scala:1020:43, :1096:24]
wire _en_T_56 = exception; // @[CSR.scala:1020:43, :1096:24]
wire _en_T_68 = exception; // @[CSR.scala:1020:43, :1096:24]
assign _io_trace_0_exception_T_1 = exception; // @[CSR.scala:1020:43, :1620:37]
wire _io_trace_1_valid_T = io_retire_0[1]; // @[CSR.scala:377:7, :1029:38, :1621:26]
wire _io_trace_2_exception_T = io_retire_0[1]; // @[CSR.scala:377:7, :1029:38, :1620:30]
wire [39:0] _epc_T = ~io_pc_0; // @[CSR.scala:377:7, :1664:28]
wire [39:0] _epc_T_1 = {_epc_T[39:1], 1'h1}; // @[CSR.scala:1664:{28,31}]
wire [39:0] epc = ~_epc_T_1; // @[CSR.scala:1664:{26,31}]
wire [39:0] tval = insn_break ? epc : io_tval_0; // @[CSR.scala:377:7, :893:83, :1033:17, :1664:26]
wire [1:0] _reg_dcsr_cause_T = causeIsDebugTrigger ? 2'h2 : 2'h1; // @[CSR.scala:964:44, :1041:90]
wire [1:0] _reg_dcsr_cause_T_1 = causeIsDebugInt ? 2'h3 : _reg_dcsr_cause_T; // @[CSR.scala:963:39, :1041:{58,90}]
wire [2:0] _reg_dcsr_cause_T_2 = reg_singleStepped ? 3'h4 : {1'h0, _reg_dcsr_cause_T_1}; // @[CSR.scala:486:30, :1041:{30,58}]
wire [1:0] _reg_mncause_T = {1'h1, causeIsRnmiBEU}; // @[CSR.scala:986:55, :1052:55]
wire [63:0] _reg_mncause_T_1 = {62'h2000000000000000, _reg_mncause_T}; // @[CSR.scala:1052:{50,55}]
wire [61:0] _reg_vscause_T_1 = cause[63:2]; // @[CSR.scala:959:8, :1060:50]
wire [63:0] _reg_vscause_T_2 = {_reg_vscause_T_1, 2'h1}; // @[CSR.scala:1060:{44,50}]
wire [63:0] _reg_vscause_T_3 = _reg_vscause_T ? _reg_vscause_T_2 : cause; // @[CSR.scala:959:8, :1060:{25,31,44}]
wire _reg_hstatus_spvp_T_1 = reg_mstatus_v ? _reg_hstatus_spvp_T : reg_hstatus_spvp; // @[CSR.scala:395:28, :552:28, :1067:{30,61}]
wire _GEN_27 = delegateVS | delegate; // @[CSR.scala:395:28, :970:66, :971:46, :1056:37, :1065:35, :1081:23]
wire _en_T_5 = cause == 64'h8000000000000000; // @[CSR.scala:959:8, :1096:88]
wire _en_T_11 = cause == 64'h8000000000000001; // @[CSR.scala:959:8, :1096:88]
wire en_1 = _en_T_8 & _en_T_11; // @[CSR.scala:1096:{24,79,88}]
wire _en_T_17 = cause == 64'h8000000000000002; // @[CSR.scala:959:8, :1096:88]
wire _en_T_23 = cause == 64'h8000000000000003; // @[CSR.scala:959:8, :1096:88]
wire en_3 = _en_T_20 & _en_T_23; // @[CSR.scala:1096:{24,79,88}]
wire _en_T_29 = cause == 64'h8000000000000004; // @[CSR.scala:959:8, :1096:88]
wire _en_T_35 = cause == 64'h8000000000000005; // @[CSR.scala:959:8, :1096:88]
wire en_5 = _en_T_32 & _en_T_35; // @[CSR.scala:1096:{24,79,88}]
wire _en_T_41 = cause == 64'h8000000000000006; // @[CSR.scala:959:8, :1096:88]
wire _en_T_47 = cause == 64'h8000000000000007; // @[CSR.scala:959:8, :1096:88]
wire en_7 = _en_T_44 & _en_T_47; // @[CSR.scala:1096:{24,79,88}]
wire _en_T_53 = cause == 64'h8000000000000008; // @[CSR.scala:959:8, :1096:88]
wire _en_T_59 = cause == 64'h8000000000000009; // @[CSR.scala:959:8, :1096:88]
wire en_9 = _en_T_56 & _en_T_59; // @[CSR.scala:1096:{24,79,88}]
wire _en_T_65 = cause == 64'h800000000000000A; // @[CSR.scala:959:8, :1096:88]
wire _en_T_71 = cause == 64'h800000000000000B; // @[CSR.scala:959:8, :1096:88]
wire en_11 = _en_T_68 & _en_T_71; // @[CSR.scala:1096:{24,79,88}]
wire _en_T_77 = cause == 64'h800000000000000C; // @[CSR.scala:959:8, :1096:88]
wire _en_T_83 = cause == 64'h800000000000000D; // @[CSR.scala:959:8, :1096:88]
wire _en_T_89 = cause == 64'h800000000000000E; // @[CSR.scala:959:8, :1096:88]
wire _en_T_95 = cause == 64'h800000000000000F; // @[CSR.scala:959:8, :1096:88]
wire _en_T_96 = cause == 64'h1; // @[CSR.scala:959:8, :1108:35]
wire en_16 = exception & _en_T_96; // @[CSR.scala:1020:43, :1108:{26,35}]
wire _en_T_97 = cause == 64'h2; // @[CSR.scala:959:8, :1108:35]
wire en_17 = exception & _en_T_97; // @[CSR.scala:1020:43, :1108:{26,35}]
wire _en_T_98 = cause == 64'h3; // @[CSR.scala:959:8, :1108:35]
wire en_18 = exception & _en_T_98; // @[CSR.scala:1020:43, :1108:{26,35}]
wire _en_T_99 = cause == 64'h4; // @[CSR.scala:959:8, :1108:35]
wire en_19 = exception & _en_T_99; // @[CSR.scala:1020:43, :1108:{26,35}]
wire _en_T_100 = cause == 64'h5; // @[CSR.scala:959:8, :1108:35]
wire en_20 = exception & _en_T_100; // @[CSR.scala:1020:43, :1108:{26,35}]
wire _en_T_101 = cause == 64'h6; // @[CSR.scala:959:8, :1108:35]
wire en_21 = exception & _en_T_101; // @[CSR.scala:1020:43, :1108:{26,35}]
wire _en_T_102 = cause == 64'h7; // @[CSR.scala:959:8, :1108:35]
wire en_22 = exception & _en_T_102; // @[CSR.scala:1020:43, :1108:{26,35}]
wire _en_T_103 = cause == 64'h8; // @[CSR.scala:959:8, :1108:35]
wire en_23 = exception & _en_T_103; // @[CSR.scala:1020:43, :1108:{26,35}]
wire _en_T_104 = cause == 64'h9; // @[CSR.scala:959:8, :1108:35]
wire en_24 = exception & _en_T_104; // @[CSR.scala:1020:43, :1108:{26,35}]
wire _en_T_105 = cause == 64'hB; // @[CSR.scala:959:8, :1108:35]
wire en_25 = exception & _en_T_105; // @[CSR.scala:1020:43, :1108:{26,35}]
wire _en_T_106 = cause == 64'hC; // @[CSR.scala:959:8, :1108:35]
wire en_26 = exception & _en_T_106; // @[CSR.scala:1020:43, :1108:{26,35}]
wire _en_T_107 = cause == 64'hD; // @[CSR.scala:959:8, :1108:35]
wire en_27 = exception & _en_T_107; // @[CSR.scala:1020:43, :1108:{26,35}]
wire _en_T_108 = cause == 64'hF; // @[CSR.scala:959:8, :1108:35]
wire en_28 = exception & _en_T_108; // @[CSR.scala:1020:43, :1108:{26,35}]
wire [1:0] ret_prv; // @[CSR.scala:1116:27]
wire [39:0] _io_evec_T_3 = {_io_evec_T[39:2], _io_evec_T[1:0] | 2'h1}; // @[CSR.scala:1665:{28,31}]
wire [39:0] _io_evec_T_4 = ~_io_evec_T_3; // @[CSR.scala:1665:{26,31}]
wire [39:0] _io_evec_T_5 = ~reg_vsepc; // @[CSR.scala:564:22, :1665:28]
wire [39:0] _io_evec_T_8 = {_io_evec_T_5[39:2], _io_evec_T_5[1:0] | 2'h1}; // @[CSR.scala:1665:{28,31}]
wire [39:0] _io_evec_T_9 = ~_io_evec_T_8; // @[CSR.scala:1665:{26,31}]
wire _T_270 = io_rw_addr_0[10] & io_rw_addr_0[7]; // @[CSR.scala:377:7, :1134:{43,48,61}]
wire _reg_mstatus_v_T_2 = ~(reg_dcsr_prv[1]); // @[CSR.scala:403:25, :1136:72]
wire [39:0] _io_evec_T_10 = ~reg_dpc; // @[CSR.scala:483:20, :1665:28]
wire [39:0] _io_evec_T_13 = {_io_evec_T_10[39:2], _io_evec_T_10[1:0] | 2'h1}; // @[CSR.scala:1665:{28,31}]
wire [39:0] _io_evec_T_14 = ~_io_evec_T_13; // @[CSR.scala:1665:{26,31}]
wire [39:0] _io_evec_T_18 = {_io_evec_T_15[39:2], _io_evec_T_15[1:0] | 2'h1}; // @[CSR.scala:1665:{28,31}]
wire [39:0] _io_evec_T_19 = ~_io_evec_T_18; // @[CSR.scala:1665:{26,31}]
assign ret_prv = io_rw_addr_0[9] ? (_T_270 ? reg_dcsr_prv : reg_mstatus_mpp) : {1'h0, reg_mstatus_v ? reg_vsstatus_spp : reg_mstatus_spp}; // @[CSR.scala:377:7, :395:28, :403:25, :562:25, :1116:27, :1117:{43,48}, :1118:29, :1122:17, :1130:17, :1134:{48,66}, :1135:15, :1139:65]
wire _reg_mstatus_v_T_8 = ~(reg_mstatus_mpp[1]); // @[CSR.scala:395:28, :1150:80]
wire [39:0] _io_evec_T_20 = ~reg_mepc; // @[CSR.scala:505:21, :1665:28]
wire [39:0] _io_evec_T_23 = {_io_evec_T_20[39:2], _io_evec_T_20[1:0] | 2'h1}; // @[CSR.scala:1665:{28,31}]
wire [39:0] _io_evec_T_24 = ~_io_evec_T_23; // @[CSR.scala:1665:{26,31}]
assign io_evec_0 = insn_ret ? (io_rw_addr_0[9] ? (_T_270 ? _io_evec_T_14 : _io_evec_T_24) : reg_mstatus_v ? _io_evec_T_9 : _io_evec_T_4) : tvec[39:0]; // @[CSR.scala:377:7, :395:28, :893:83, :995:17, :996:11, :1115:19, :1117:{43,48}, :1118:29, :1124:17, :1132:17, :1134:{48,66}, :1138:15, :1139:65, :1665:26]
assign new_prv = insn_ret ? ret_prv : exception ? (trapToDebug ? (reg_debug ? reg_mstatus_prv : 2'h3) : {~_GEN_27, 1'h1}) : reg_mstatus_prv; // @[CSR.scala:395:28, :397:28, :482:26, :893:83, :966:34, :1020:43, :1035:20, :1036:24, :1037:25, :1044:17, :1046:31, :1056:37, :1064:15, :1065:35, :1078:15, :1081:23, :1091:15, :1115:19, :1116:27, :1154:13]
assign _io_csr_stall_T = reg_wfi | io_status_cease_0; // @[CSR.scala:377:7, :575:54, :1161:27]
assign io_csr_stall_0 = _io_csr_stall_T; // @[CSR.scala:377:7, :1161:27]
reg io_status_cease_r; // @[CSR.scala:1162:31]
assign io_status_cease_0 = io_status_cease_r; // @[CSR.scala:377:7, :1162:31]
wire [63:0] _io_rw_rdata_T_4 = decoded_addr_95_2 ? 64'h800000000014112D : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_155 = _io_rw_rdata_T_4; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_5 = decoded_addr_101_2 ? read_mstatus : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_6 = decoded_addr_72_2 ? read_mtvec : 64'h0; // @[Mux.scala:30:73]
wire [15:0] _io_rw_rdata_T_7 = decoded_addr_109_2 ? read_mip : 16'h0; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_8 = decoded_addr_77_2 ? reg_mie : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_9 = decoded_addr_131_2 ? reg_mscratch : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_10 = decoded_addr_134_2 ? read_mapping_10_2 : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_11 = decoded_addr_138_2 ? read_mapping_11_2 : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_12 = decoded_addr_29_2 ? reg_mcause : 64'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_13 = decoded_addr_133_2 & io_hartid_0; // @[Mux.scala:30:73]
wire [31:0] _io_rw_rdata_T_14 = decoded_addr_49_2 ? debug_csrs_0_2 : 32'h0; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_15 = decoded_addr_90_2 ? debug_csrs_1_2 : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_16 = decoded_addr_57_2 ? reg_dscratch0 : 64'h0; // @[Mux.scala:30:73]
wire [4:0] _io_rw_rdata_T_17 = decoded_addr_36_2 ? reg_fflags : 5'h0; // @[Mux.scala:30:73]
wire [2:0] _io_rw_rdata_T_18 = decoded_addr_68_2 ? reg_frm : 3'h0; // @[Mux.scala:30:73]
wire [7:0] _io_rw_rdata_T_19 = decoded_addr_100_2 ? read_fcsr : 8'h0; // @[Mux.scala:30:73]
wire [4:0] _io_rw_rdata_T_20 = decoded_addr_132_2 ? reg_mcountinhibit : 5'h0; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_21 = decoded_addr_104_2 ? value_1 : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_22 = decoded_addr_123_2 ? value : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_23 = decoded_addr_148_2 ? reg_hpmevent_0 : 64'h0; // @[Mux.scala:30:73]
wire [39:0] _io_rw_rdata_T_24 = decoded_addr_17_2 ? value_2 : 40'h0; // @[Mux.scala:30:73]
wire [39:0] _io_rw_rdata_T_25 = decoded_addr_27_2 ? value_2 : 40'h0; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_26 = decoded_addr_84_2 ? reg_hpmevent_1 : 64'h0; // @[Mux.scala:30:73]
wire [39:0] _io_rw_rdata_T_27 = decoded_addr_52_2 ? value_3 : 40'h0; // @[Mux.scala:30:73]
wire [39:0] _io_rw_rdata_T_28 = decoded_addr_146_2 ? value_3 : 40'h0; // @[Mux.scala:30:73]
wire [31:0] _io_rw_rdata_T_110 = decoded_addr_35_2 ? read_mcounteren : 32'h0; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_111 = decoded_addr_2_2 ? value_1 : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_112 = decoded_addr_66_2 ? value : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_113 = decoded_addr_42_2 ? {57'h0, lo_4} : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_114 = decoded_addr_61_2 ? {hi_7[41:0], lo_5} : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_115 = decoded_addr_48_2 ? read_sip : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_116 = decoded_addr_44_2 ? read_sie : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_117 = decoded_addr_15_2 ? reg_sscratch : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_118 = decoded_addr_147_2 ? reg_scause : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_119 = decoded_addr_94_2 ? {{24{reg_stval[39]}}, reg_stval} : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_120 = decoded_addr_6_2 ? {hi_8, reg_satp_ppn} : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_121 = decoded_addr_28_2 ? {{24{_T_34[39]}}, _T_34} : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_122 = decoded_addr_25_2 ? read_stvec : 64'h0; // @[Mux.scala:30:73]
wire [31:0] _io_rw_rdata_T_123 = decoded_addr_139_2 ? read_scounteren : 32'h0; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_124 = decoded_addr_125_2 ? read_mideleg : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_125 = decoded_addr_23_2 ? read_medeleg : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_126 = decoded_addr_69_2 ? {57'h0, lo_6} : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_127 = decoded_addr_143_2 ? {hi_18, lo_15} : 64'h0; // @[Mux.scala:30:73]
wire [29:0] _io_rw_rdata_T_129 = decoded_addr_105_2 ? reg_pmp_0_addr : 30'h0; // @[Mux.scala:30:73]
wire [29:0] _io_rw_rdata_T_130 = decoded_addr_8_2 ? reg_pmp_1_addr : 30'h0; // @[Mux.scala:30:73]
wire [29:0] _io_rw_rdata_T_131 = decoded_addr_127_2 ? reg_pmp_2_addr : 30'h0; // @[Mux.scala:30:73]
wire [29:0] _io_rw_rdata_T_132 = decoded_addr_86_2 ? reg_pmp_3_addr : 30'h0; // @[Mux.scala:30:73]
wire [29:0] _io_rw_rdata_T_133 = decoded_addr_54_2 ? reg_pmp_4_addr : 30'h0; // @[Mux.scala:30:73]
wire [29:0] _io_rw_rdata_T_134 = decoded_addr_20_2 ? reg_pmp_5_addr : 30'h0; // @[Mux.scala:30:73]
wire [29:0] _io_rw_rdata_T_135 = decoded_addr_137_2 ? reg_pmp_6_addr : 30'h0; // @[Mux.scala:30:73]
wire [29:0] _io_rw_rdata_T_136 = decoded_addr_116_2 ? reg_pmp_7_addr : 30'h0; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_145 = decoded_addr_76_2 ? reg_custom_0 : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_146 = decoded_addr_118_2 ? reg_custom_1 : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_147 = decoded_addr_18_2 ? reg_custom_2 : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_148 = decoded_addr_3_2 ? reg_custom_3 : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_156 = _io_rw_rdata_T_155 | _io_rw_rdata_T_5; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_157 = _io_rw_rdata_T_156 | _io_rw_rdata_T_6; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_158 = {_io_rw_rdata_T_157[63:16], _io_rw_rdata_T_157[15:0] | _io_rw_rdata_T_7}; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_159 = _io_rw_rdata_T_158 | _io_rw_rdata_T_8; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_160 = _io_rw_rdata_T_159 | _io_rw_rdata_T_9; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_161 = _io_rw_rdata_T_160 | _io_rw_rdata_T_10; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_162 = _io_rw_rdata_T_161 | _io_rw_rdata_T_11; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_163 = _io_rw_rdata_T_162 | _io_rw_rdata_T_12; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_164 = {_io_rw_rdata_T_163[63:1], _io_rw_rdata_T_163[0] | _io_rw_rdata_T_13}; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_165 = {_io_rw_rdata_T_164[63:32], _io_rw_rdata_T_164[31:0] | _io_rw_rdata_T_14}; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_166 = _io_rw_rdata_T_165 | _io_rw_rdata_T_15; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_167 = _io_rw_rdata_T_166 | _io_rw_rdata_T_16; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_168 = {_io_rw_rdata_T_167[63:5], _io_rw_rdata_T_167[4:0] | _io_rw_rdata_T_17}; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_169 = {_io_rw_rdata_T_168[63:3], _io_rw_rdata_T_168[2:0] | _io_rw_rdata_T_18}; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_170 = {_io_rw_rdata_T_169[63:8], _io_rw_rdata_T_169[7:0] | _io_rw_rdata_T_19}; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_171 = {_io_rw_rdata_T_170[63:5], _io_rw_rdata_T_170[4:0] | _io_rw_rdata_T_20}; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_172 = _io_rw_rdata_T_171 | _io_rw_rdata_T_21; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_173 = _io_rw_rdata_T_172 | _io_rw_rdata_T_22; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_174 = _io_rw_rdata_T_173 | _io_rw_rdata_T_23; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_175 = {_io_rw_rdata_T_174[63:40], _io_rw_rdata_T_174[39:0] | _io_rw_rdata_T_24}; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_176 = {_io_rw_rdata_T_175[63:40], _io_rw_rdata_T_175[39:0] | _io_rw_rdata_T_25}; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_177 = _io_rw_rdata_T_176 | _io_rw_rdata_T_26; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_178 = {_io_rw_rdata_T_177[63:40], _io_rw_rdata_T_177[39:0] | _io_rw_rdata_T_27}; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_179 = {_io_rw_rdata_T_178[63:40], _io_rw_rdata_T_178[39:0] | _io_rw_rdata_T_28}; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_180 = _io_rw_rdata_T_179; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_181 = _io_rw_rdata_T_180; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_182 = _io_rw_rdata_T_181; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_183 = _io_rw_rdata_T_182; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_184 = _io_rw_rdata_T_183; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_185 = _io_rw_rdata_T_184; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_186 = _io_rw_rdata_T_185; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_187 = _io_rw_rdata_T_186; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_188 = _io_rw_rdata_T_187; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_189 = _io_rw_rdata_T_188; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_190 = _io_rw_rdata_T_189; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_191 = _io_rw_rdata_T_190; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_192 = _io_rw_rdata_T_191; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_193 = _io_rw_rdata_T_192; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_194 = _io_rw_rdata_T_193; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_195 = _io_rw_rdata_T_194; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_196 = _io_rw_rdata_T_195; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_197 = _io_rw_rdata_T_196; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_198 = _io_rw_rdata_T_197; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_199 = _io_rw_rdata_T_198; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_200 = _io_rw_rdata_T_199; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_201 = _io_rw_rdata_T_200; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_202 = _io_rw_rdata_T_201; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_203 = _io_rw_rdata_T_202; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_204 = _io_rw_rdata_T_203; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_205 = _io_rw_rdata_T_204; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_206 = _io_rw_rdata_T_205; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_207 = _io_rw_rdata_T_206; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_208 = _io_rw_rdata_T_207; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_209 = _io_rw_rdata_T_208; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_210 = _io_rw_rdata_T_209; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_211 = _io_rw_rdata_T_210; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_212 = _io_rw_rdata_T_211; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_213 = _io_rw_rdata_T_212; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_214 = _io_rw_rdata_T_213; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_215 = _io_rw_rdata_T_214; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_216 = _io_rw_rdata_T_215; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_217 = _io_rw_rdata_T_216; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_218 = _io_rw_rdata_T_217; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_219 = _io_rw_rdata_T_218; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_220 = _io_rw_rdata_T_219; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_221 = _io_rw_rdata_T_220; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_222 = _io_rw_rdata_T_221; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_223 = _io_rw_rdata_T_222; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_224 = _io_rw_rdata_T_223; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_225 = _io_rw_rdata_T_224; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_226 = _io_rw_rdata_T_225; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_227 = _io_rw_rdata_T_226; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_228 = _io_rw_rdata_T_227; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_229 = _io_rw_rdata_T_228; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_230 = _io_rw_rdata_T_229; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_231 = _io_rw_rdata_T_230; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_232 = _io_rw_rdata_T_231; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_233 = _io_rw_rdata_T_232; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_234 = _io_rw_rdata_T_233; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_235 = _io_rw_rdata_T_234; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_236 = _io_rw_rdata_T_235; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_237 = _io_rw_rdata_T_236; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_238 = _io_rw_rdata_T_237; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_239 = _io_rw_rdata_T_238; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_240 = _io_rw_rdata_T_239; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_241 = _io_rw_rdata_T_240; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_242 = _io_rw_rdata_T_241; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_243 = _io_rw_rdata_T_242; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_244 = _io_rw_rdata_T_243; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_245 = _io_rw_rdata_T_244; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_246 = _io_rw_rdata_T_245; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_247 = _io_rw_rdata_T_246; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_248 = _io_rw_rdata_T_247; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_249 = _io_rw_rdata_T_248; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_250 = _io_rw_rdata_T_249; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_251 = _io_rw_rdata_T_250; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_252 = _io_rw_rdata_T_251; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_253 = _io_rw_rdata_T_252; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_254 = _io_rw_rdata_T_253; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_255 = _io_rw_rdata_T_254; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_256 = _io_rw_rdata_T_255; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_257 = _io_rw_rdata_T_256; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_258 = _io_rw_rdata_T_257; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_259 = _io_rw_rdata_T_258; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_260 = _io_rw_rdata_T_259; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_261 = {_io_rw_rdata_T_260[63:32], _io_rw_rdata_T_260[31:0] | _io_rw_rdata_T_110}; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_262 = _io_rw_rdata_T_261 | _io_rw_rdata_T_111; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_263 = _io_rw_rdata_T_262 | _io_rw_rdata_T_112; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_264 = _io_rw_rdata_T_263 | _io_rw_rdata_T_113; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_265 = _io_rw_rdata_T_264 | _io_rw_rdata_T_114; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_266 = _io_rw_rdata_T_265 | _io_rw_rdata_T_115; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_267 = _io_rw_rdata_T_266 | _io_rw_rdata_T_116; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_268 = _io_rw_rdata_T_267 | _io_rw_rdata_T_117; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_269 = _io_rw_rdata_T_268 | _io_rw_rdata_T_118; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_270 = _io_rw_rdata_T_269 | _io_rw_rdata_T_119; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_271 = _io_rw_rdata_T_270 | _io_rw_rdata_T_120; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_272 = _io_rw_rdata_T_271 | _io_rw_rdata_T_121; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_273 = _io_rw_rdata_T_272 | _io_rw_rdata_T_122; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_274 = {_io_rw_rdata_T_273[63:32], _io_rw_rdata_T_273[31:0] | _io_rw_rdata_T_123}; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_275 = _io_rw_rdata_T_274 | _io_rw_rdata_T_124; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_276 = _io_rw_rdata_T_275 | _io_rw_rdata_T_125; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_277 = _io_rw_rdata_T_276 | _io_rw_rdata_T_126; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_278 = _io_rw_rdata_T_277 | _io_rw_rdata_T_127; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_279 = _io_rw_rdata_T_278; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_280 = {_io_rw_rdata_T_279[63:30], _io_rw_rdata_T_279[29:0] | _io_rw_rdata_T_129}; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_281 = {_io_rw_rdata_T_280[63:30], _io_rw_rdata_T_280[29:0] | _io_rw_rdata_T_130}; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_282 = {_io_rw_rdata_T_281[63:30], _io_rw_rdata_T_281[29:0] | _io_rw_rdata_T_131}; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_283 = {_io_rw_rdata_T_282[63:30], _io_rw_rdata_T_282[29:0] | _io_rw_rdata_T_132}; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_284 = {_io_rw_rdata_T_283[63:30], _io_rw_rdata_T_283[29:0] | _io_rw_rdata_T_133}; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_285 = {_io_rw_rdata_T_284[63:30], _io_rw_rdata_T_284[29:0] | _io_rw_rdata_T_134}; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_286 = {_io_rw_rdata_T_285[63:30], _io_rw_rdata_T_285[29:0] | _io_rw_rdata_T_135}; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_287 = {_io_rw_rdata_T_286[63:30], _io_rw_rdata_T_286[29:0] | _io_rw_rdata_T_136}; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_288 = _io_rw_rdata_T_287; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_289 = _io_rw_rdata_T_288; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_290 = _io_rw_rdata_T_289; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_291 = _io_rw_rdata_T_290; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_292 = _io_rw_rdata_T_291; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_293 = _io_rw_rdata_T_292; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_294 = _io_rw_rdata_T_293; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_295 = _io_rw_rdata_T_294; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_296 = _io_rw_rdata_T_295 | _io_rw_rdata_T_145; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_297 = _io_rw_rdata_T_296 | _io_rw_rdata_T_146; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_298 = _io_rw_rdata_T_297 | _io_rw_rdata_T_147; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_299 = _io_rw_rdata_T_298 | _io_rw_rdata_T_148; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_300 = _io_rw_rdata_T_299; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_301 = _io_rw_rdata_T_300; // @[Mux.scala:30:73]
wire [63:0] _io_rw_rdata_T_302 = _io_rw_rdata_T_301; // @[Mux.scala:30:73]
assign _io_rw_rdata_WIRE = _io_rw_rdata_T_302; // @[Mux.scala:30:73]
assign io_rw_rdata_0 = _io_rw_rdata_WIRE; // @[Mux.scala:30:73]
wire set_fs_dirty; // @[CSR.scala:1200:33] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_55 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0)
node _source_ok_T = shr(io.in.a.bits.source, 4)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits = bits(_uncommonBits_T, 3, 0)
node _T_4 = shr(io.in.a.bits.source, 4)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<4>(0h9))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0)
node _T_24 = shr(io.in.a.bits.source, 4)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<4>(0h9))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = and(_T_32, _T_37)
node _T_39 = or(UInt<1>(0h0), _T_38)
node _T_40 = and(_T_31, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_40, UInt<1>(0h1), "") : assert_2
node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_46 = and(_T_44, _T_45)
node _T_47 = or(UInt<1>(0h0), _T_46)
node _T_48 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = and(_T_47, _T_52)
node _T_54 = or(UInt<1>(0h0), _T_53)
node _T_55 = and(UInt<1>(0h0), _T_54)
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(_T_55, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_55, UInt<1>(0h1), "") : assert_3
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_62, UInt<1>(0h1), "") : assert_5
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(is_aligned, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_69, UInt<1>(0h1), "") : assert_7
node _T_73 = not(io.in.a.bits.mask)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_74, UInt<1>(0h1), "") : assert_8
node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_78, UInt<1>(0h1), "") : assert_9
node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_82 :
node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_85 = and(_T_83, _T_84)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0)
node _T_86 = shr(io.in.a.bits.source, 4)
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_89 = and(_T_87, _T_88)
node _T_90 = leq(uncommonBits_2, UInt<4>(0h9))
node _T_91 = and(_T_89, _T_90)
node _T_92 = and(_T_85, _T_91)
node _T_93 = or(UInt<1>(0h0), _T_92)
node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(_T_93, _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_102, UInt<1>(0h1), "") : assert_10
node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_108 = and(_T_106, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = and(_T_109, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_115)
node _T_117 = and(UInt<1>(0h0), _T_116)
node _T_118 = asUInt(reset)
node _T_119 = eq(_T_118, UInt<1>(0h0))
when _T_119 :
node _T_120 = eq(_T_117, UInt<1>(0h0))
when _T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_117, UInt<1>(0h1), "") : assert_11
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_124, UInt<1>(0h1), "") : assert_13
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(is_aligned, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_131, UInt<1>(0h1), "") : assert_15
node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_136 = asUInt(reset)
node _T_137 = eq(_T_136, UInt<1>(0h0))
when _T_137 :
node _T_138 = eq(_T_135, UInt<1>(0h0))
when _T_138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_135, UInt<1>(0h1), "") : assert_16
node _T_139 = not(io.in.a.bits.mask)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_140, UInt<1>(0h1), "") : assert_17
node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_T_144, UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_144, UInt<1>(0h1), "") : assert_18
node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_148 :
node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0)
node _T_152 = shr(io.in.a.bits.source, 4)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_3, UInt<4>(0h9))
node _T_157 = and(_T_155, _T_156)
node _T_158 = and(_T_151, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_159, UInt<1>(0h1), "") : assert_19
node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_164 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_165 = and(_T_163, _T_164)
node _T_166 = or(UInt<1>(0h0), _T_165)
node _T_167 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_168 = cvt(_T_167)
node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000)))
node _T_170 = asSInt(_T_169)
node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0)))
node _T_172 = and(_T_166, _T_171)
node _T_173 = or(UInt<1>(0h0), _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_173, UInt<1>(0h1), "") : assert_20
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(is_aligned, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(io.in.a.bits.mask, mask)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_187, UInt<1>(0h1), "") : assert_24
node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_191, UInt<1>(0h1), "") : assert_25
node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_195 :
node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0)
node _T_199 = shr(io.in.a.bits.source, 4)
node _T_200 = eq(_T_199, UInt<1>(0h0))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_4, UInt<4>(0h9))
node _T_204 = and(_T_202, _T_203)
node _T_205 = and(_T_198, _T_204)
node _T_206 = or(UInt<1>(0h0), _T_205)
node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_208 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_209 = and(_T_207, _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = and(_T_210, _T_215)
node _T_217 = or(UInt<1>(0h0), _T_216)
node _T_218 = and(_T_206, _T_217)
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_218, UInt<1>(0h1), "") : assert_26
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_225 = asUInt(reset)
node _T_226 = eq(_T_225, UInt<1>(0h0))
when _T_226 :
node _T_227 = eq(is_aligned, UInt<1>(0h0))
when _T_227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(_T_228, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_228, UInt<1>(0h1), "") : assert_29
node _T_232 = eq(io.in.a.bits.mask, mask)
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_236 :
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_239 = and(_T_237, _T_238)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0)
node _T_240 = shr(io.in.a.bits.source, 4)
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_243 = and(_T_241, _T_242)
node _T_244 = leq(uncommonBits_5, UInt<4>(0h9))
node _T_245 = and(_T_243, _T_244)
node _T_246 = and(_T_239, _T_245)
node _T_247 = or(UInt<1>(0h0), _T_246)
node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_249 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_253 = cvt(_T_252)
node _T_254 = and(_T_253, asSInt(UInt<17>(0h10000)))
node _T_255 = asSInt(_T_254)
node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0)))
node _T_257 = and(_T_251, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = and(_T_247, _T_258)
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(_T_259, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_259, UInt<1>(0h1), "") : assert_31
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_266 = asUInt(reset)
node _T_267 = eq(_T_266, UInt<1>(0h0))
when _T_267 :
node _T_268 = eq(is_aligned, UInt<1>(0h0))
when _T_268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_270 = asUInt(reset)
node _T_271 = eq(_T_270, UInt<1>(0h0))
when _T_271 :
node _T_272 = eq(_T_269, UInt<1>(0h0))
when _T_272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_269, UInt<1>(0h1), "") : assert_34
node _T_273 = not(mask)
node _T_274 = and(io.in.a.bits.mask, _T_273)
node _T_275 = eq(_T_274, UInt<1>(0h0))
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(_T_275, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_275, UInt<1>(0h1), "") : assert_35
node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_279 :
node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_282 = and(_T_280, _T_281)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0)
node _T_283 = shr(io.in.a.bits.source, 4)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_286 = and(_T_284, _T_285)
node _T_287 = leq(uncommonBits_6, UInt<4>(0h9))
node _T_288 = and(_T_286, _T_287)
node _T_289 = and(_T_282, _T_288)
node _T_290 = or(UInt<1>(0h0), _T_289)
node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_292 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_293 = cvt(_T_292)
node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000)))
node _T_295 = asSInt(_T_294)
node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0)))
node _T_297 = and(_T_291, _T_296)
node _T_298 = or(UInt<1>(0h0), _T_297)
node _T_299 = and(_T_290, _T_298)
node _T_300 = asUInt(reset)
node _T_301 = eq(_T_300, UInt<1>(0h0))
when _T_301 :
node _T_302 = eq(_T_299, UInt<1>(0h0))
when _T_302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_299, UInt<1>(0h1), "") : assert_36
node _T_303 = asUInt(reset)
node _T_304 = eq(_T_303, UInt<1>(0h0))
when _T_304 :
node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(is_aligned, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_309, UInt<1>(0h1), "") : assert_39
node _T_313 = eq(io.in.a.bits.mask, mask)
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_313, UInt<1>(0h1), "") : assert_40
node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_317 :
node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0)
node _T_321 = shr(io.in.a.bits.source, 4)
node _T_322 = eq(_T_321, UInt<1>(0h0))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_7, UInt<4>(0h9))
node _T_326 = and(_T_324, _T_325)
node _T_327 = and(_T_320, _T_326)
node _T_328 = or(UInt<1>(0h0), _T_327)
node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_330 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_331 = cvt(_T_330)
node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000)))
node _T_333 = asSInt(_T_332)
node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0)))
node _T_335 = and(_T_329, _T_334)
node _T_336 = or(UInt<1>(0h0), _T_335)
node _T_337 = and(_T_328, _T_336)
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(_T_337, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_337, UInt<1>(0h1), "") : assert_41
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(is_aligned, UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_347, UInt<1>(0h1), "") : assert_44
node _T_351 = eq(io.in.a.bits.mask, mask)
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_351, UInt<1>(0h1), "") : assert_45
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0)
node _T_359 = shr(io.in.a.bits.source, 4)
node _T_360 = eq(_T_359, UInt<1>(0h0))
node _T_361 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_362 = and(_T_360, _T_361)
node _T_363 = leq(uncommonBits_8, UInt<4>(0h9))
node _T_364 = and(_T_362, _T_363)
node _T_365 = and(_T_358, _T_364)
node _T_366 = or(UInt<1>(0h0), _T_365)
node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_368 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_369 = cvt(_T_368)
node _T_370 = and(_T_369, asSInt(UInt<17>(0h10000)))
node _T_371 = asSInt(_T_370)
node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0)))
node _T_373 = and(_T_367, _T_372)
node _T_374 = or(UInt<1>(0h0), _T_373)
node _T_375 = and(_T_366, _T_374)
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_375, UInt<1>(0h1), "") : assert_46
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(is_aligned, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_385, UInt<1>(0h1), "") : assert_49
node _T_389 = eq(io.in.a.bits.mask, mask)
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_389, UInt<1>(0h1), "") : assert_50
node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_393, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_397, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 4)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_401 :
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_405, UInt<1>(0h1), "") : assert_54
node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_409, UInt<1>(0h1), "") : assert_55
node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_414 = asUInt(reset)
node _T_415 = eq(_T_414, UInt<1>(0h0))
when _T_415 :
node _T_416 = eq(_T_413, UInt<1>(0h0))
when _T_416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_413, UInt<1>(0h1), "") : assert_56
node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_418 = asUInt(reset)
node _T_419 = eq(_T_418, UInt<1>(0h0))
when _T_419 :
node _T_420 = eq(_T_417, UInt<1>(0h0))
when _T_420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_417, UInt<1>(0h1), "") : assert_57
node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_421 :
node _T_422 = asUInt(reset)
node _T_423 = eq(_T_422, UInt<1>(0h0))
when _T_423 :
node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(sink_ok, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_T_428, UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_428, UInt<1>(0h1), "") : assert_60
node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_432, UInt<1>(0h1), "") : assert_61
node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_436, UInt<1>(0h1), "") : assert_62
node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(_T_440, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_440, UInt<1>(0h1), "") : assert_63
node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_445 = or(UInt<1>(0h0), _T_444)
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_445, UInt<1>(0h1), "") : assert_64
node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_449 :
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(sink_ok, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_457 = asUInt(reset)
node _T_458 = eq(_T_457, UInt<1>(0h0))
when _T_458 :
node _T_459 = eq(_T_456, UInt<1>(0h0))
when _T_459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_456, UInt<1>(0h1), "") : assert_67
node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(_T_460, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_460, UInt<1>(0h1), "") : assert_68
node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_464, UInt<1>(0h1), "") : assert_69
node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_469 = or(_T_468, io.in.d.bits.corrupt)
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_469, UInt<1>(0h1), "") : assert_70
node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_474 = or(UInt<1>(0h0), _T_473)
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_474, UInt<1>(0h1), "") : assert_71
node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_478 :
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_482, UInt<1>(0h1), "") : assert_73
node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_486, UInt<1>(0h1), "") : assert_74
node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_491 = or(UInt<1>(0h0), _T_490)
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_491, UInt<1>(0h1), "") : assert_75
node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_495 :
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_499, UInt<1>(0h1), "") : assert_77
node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_504 = or(_T_503, io.in.d.bits.corrupt)
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(_T_504, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_504, UInt<1>(0h1), "") : assert_78
node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_509, UInt<1>(0h1), "") : assert_79
node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_513 :
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_T_517, UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_517, UInt<1>(0h1), "") : assert_81
node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_521, UInt<1>(0h1), "") : assert_82
node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_526 = or(UInt<1>(0h0), _T_525)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_526, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<28>(0h0)
connect _WIRE.bits.source, UInt<4>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_530, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<28>(0h0)
connect _WIRE_2.bits.source, UInt<4>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_534, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_538, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_542 = eq(a_first, UInt<1>(0h0))
node _T_543 = and(io.in.a.valid, _T_542)
when _T_543 :
node _T_544 = eq(io.in.a.bits.opcode, opcode)
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_544, UInt<1>(0h1), "") : assert_87
node _T_548 = eq(io.in.a.bits.param, param)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_548, UInt<1>(0h1), "") : assert_88
node _T_552 = eq(io.in.a.bits.size, size)
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(_T_552, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_552, UInt<1>(0h1), "") : assert_89
node _T_556 = eq(io.in.a.bits.source, source)
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_556, UInt<1>(0h1), "") : assert_90
node _T_560 = eq(io.in.a.bits.address, address)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_560, UInt<1>(0h1), "") : assert_91
node _T_564 = and(io.in.a.ready, io.in.a.valid)
node _T_565 = and(_T_564, a_first)
when _T_565 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_566 = eq(d_first, UInt<1>(0h0))
node _T_567 = and(io.in.d.valid, _T_566)
when _T_567 :
node _T_568 = eq(io.in.d.bits.opcode, opcode_1)
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_568, UInt<1>(0h1), "") : assert_92
node _T_572 = eq(io.in.d.bits.param, param_1)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_572, UInt<1>(0h1), "") : assert_93
node _T_576 = eq(io.in.d.bits.size, size_1)
node _T_577 = asUInt(reset)
node _T_578 = eq(_T_577, UInt<1>(0h0))
when _T_578 :
node _T_579 = eq(_T_576, UInt<1>(0h0))
when _T_579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_576, UInt<1>(0h1), "") : assert_94
node _T_580 = eq(io.in.d.bits.source, source_1)
node _T_581 = asUInt(reset)
node _T_582 = eq(_T_581, UInt<1>(0h0))
when _T_582 :
node _T_583 = eq(_T_580, UInt<1>(0h0))
when _T_583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_580, UInt<1>(0h1), "") : assert_95
node _T_584 = eq(io.in.d.bits.sink, sink)
node _T_585 = asUInt(reset)
node _T_586 = eq(_T_585, UInt<1>(0h0))
when _T_586 :
node _T_587 = eq(_T_584, UInt<1>(0h0))
when _T_587 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_584, UInt<1>(0h1), "") : assert_96
node _T_588 = eq(io.in.d.bits.denied, denied)
node _T_589 = asUInt(reset)
node _T_590 = eq(_T_589, UInt<1>(0h0))
when _T_590 :
node _T_591 = eq(_T_588, UInt<1>(0h0))
when _T_591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_588, UInt<1>(0h1), "") : assert_97
node _T_592 = and(io.in.d.ready, io.in.d.valid)
node _T_593 = and(_T_592, d_first)
when _T_593 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0)
regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0)
regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<10>
connect a_set, UInt<10>(0h0)
wire a_set_wo_ready : UInt<10>
connect a_set_wo_ready, UInt<10>(0h0)
wire a_opcodes_set : UInt<40>
connect a_opcodes_set, UInt<40>(0h0)
wire a_sizes_set : UInt<40>
connect a_sizes_set, UInt<40>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_594 = and(io.in.a.valid, a_first_1)
node _T_595 = and(_T_594, UInt<1>(0h1))
when _T_595 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_596 = and(io.in.a.ready, io.in.a.valid)
node _T_597 = and(_T_596, a_first_1)
node _T_598 = and(_T_597, UInt<1>(0h1))
when _T_598 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_599 = dshr(inflight, io.in.a.bits.source)
node _T_600 = bits(_T_599, 0, 0)
node _T_601 = eq(_T_600, UInt<1>(0h0))
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_601, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<10>
connect d_clr, UInt<10>(0h0)
wire d_clr_wo_ready : UInt<10>
connect d_clr_wo_ready, UInt<10>(0h0)
wire d_opcodes_clr : UInt<40>
connect d_opcodes_clr, UInt<40>(0h0)
wire d_sizes_clr : UInt<40>
connect d_sizes_clr, UInt<40>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_605 = and(io.in.d.valid, d_first_1)
node _T_606 = and(_T_605, UInt<1>(0h1))
node _T_607 = eq(d_release_ack, UInt<1>(0h0))
node _T_608 = and(_T_606, _T_607)
when _T_608 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_609 = and(io.in.d.ready, io.in.d.valid)
node _T_610 = and(_T_609, d_first_1)
node _T_611 = and(_T_610, UInt<1>(0h1))
node _T_612 = eq(d_release_ack, UInt<1>(0h0))
node _T_613 = and(_T_611, _T_612)
when _T_613 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_614 = and(io.in.d.valid, d_first_1)
node _T_615 = and(_T_614, UInt<1>(0h1))
node _T_616 = eq(d_release_ack, UInt<1>(0h0))
node _T_617 = and(_T_615, _T_616)
when _T_617 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_618 = dshr(inflight, io.in.d.bits.source)
node _T_619 = bits(_T_618, 0, 0)
node _T_620 = or(_T_619, same_cycle_resp)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_620, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_626 = or(_T_624, _T_625)
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_626, UInt<1>(0h1), "") : assert_100
node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_630, UInt<1>(0h1), "") : assert_101
else :
node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_636 = or(_T_634, _T_635)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_636, UInt<1>(0h1), "") : assert_102
node _T_640 = eq(io.in.d.bits.size, a_size_lookup)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_640, UInt<1>(0h1), "") : assert_103
node _T_644 = and(io.in.d.valid, d_first_1)
node _T_645 = and(_T_644, a_first_1)
node _T_646 = and(_T_645, io.in.a.valid)
node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_648 = and(_T_646, _T_647)
node _T_649 = eq(d_release_ack, UInt<1>(0h0))
node _T_650 = and(_T_648, _T_649)
when _T_650 :
node _T_651 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_652 = or(_T_651, io.in.a.ready)
node _T_653 = asUInt(reset)
node _T_654 = eq(_T_653, UInt<1>(0h0))
when _T_654 :
node _T_655 = eq(_T_652, UInt<1>(0h0))
when _T_655 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_652, UInt<1>(0h1), "") : assert_104
node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_657 = orr(a_set_wo_ready)
node _T_658 = eq(_T_657, UInt<1>(0h0))
node _T_659 = or(_T_656, _T_658)
node _T_660 = asUInt(reset)
node _T_661 = eq(_T_660, UInt<1>(0h0))
when _T_661 :
node _T_662 = eq(_T_659, UInt<1>(0h0))
when _T_662 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_659, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_110
node _T_663 = orr(inflight)
node _T_664 = eq(_T_663, UInt<1>(0h0))
node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_666 = or(_T_664, _T_665)
node _T_667 = lt(watchdog, plusarg_reader.out)
node _T_668 = or(_T_666, _T_667)
node _T_669 = asUInt(reset)
node _T_670 = eq(_T_669, UInt<1>(0h0))
when _T_670 :
node _T_671 = eq(_T_668, UInt<1>(0h0))
when _T_671 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_668, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_672 = and(io.in.a.ready, io.in.a.valid)
node _T_673 = and(io.in.d.ready, io.in.d.valid)
node _T_674 = or(_T_672, _T_673)
when _T_674 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0)
regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0)
regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<28>(0h0)
connect _c_first_WIRE.bits.source, UInt<4>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<10>
connect c_set, UInt<10>(0h0)
wire c_set_wo_ready : UInt<10>
connect c_set_wo_ready, UInt<10>(0h0)
wire c_opcodes_set : UInt<40>
connect c_opcodes_set, UInt<40>(0h0)
wire c_sizes_set : UInt<40>
connect c_sizes_set, UInt<40>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<28>(0h0)
connect _WIRE_6.bits.source, UInt<4>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_675 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<28>(0h0)
connect _WIRE_8.bits.source, UInt<4>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_678 = and(_T_676, _T_677)
node _T_679 = and(_T_675, _T_678)
when _T_679 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<28>(0h0)
connect _WIRE_10.bits.source, UInt<4>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_681 = and(_T_680, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<28>(0h0)
connect _WIRE_12.bits.source, UInt<4>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_684 = and(_T_682, _T_683)
node _T_685 = and(_T_681, _T_684)
when _T_685 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<28>(0h0)
connect _WIRE_14.bits.source, UInt<4>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_686 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_687 = bits(_T_686, 0, 0)
node _T_688 = eq(_T_687, UInt<1>(0h0))
node _T_689 = asUInt(reset)
node _T_690 = eq(_T_689, UInt<1>(0h0))
when _T_690 :
node _T_691 = eq(_T_688, UInt<1>(0h0))
when _T_691 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_688, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<10>
connect d_clr_1, UInt<10>(0h0)
wire d_clr_wo_ready_1 : UInt<10>
connect d_clr_wo_ready_1, UInt<10>(0h0)
wire d_opcodes_clr_1 : UInt<40>
connect d_opcodes_clr_1, UInt<40>(0h0)
wire d_sizes_clr_1 : UInt<40>
connect d_sizes_clr_1, UInt<40>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_692 = and(io.in.d.valid, d_first_2)
node _T_693 = and(_T_692, UInt<1>(0h1))
node _T_694 = and(_T_693, d_release_ack_1)
when _T_694 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_695 = and(io.in.d.ready, io.in.d.valid)
node _T_696 = and(_T_695, d_first_2)
node _T_697 = and(_T_696, UInt<1>(0h1))
node _T_698 = and(_T_697, d_release_ack_1)
when _T_698 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_699 = and(io.in.d.valid, d_first_2)
node _T_700 = and(_T_699, UInt<1>(0h1))
node _T_701 = and(_T_700, d_release_ack_1)
when _T_701 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_702 = dshr(inflight_1, io.in.d.bits.source)
node _T_703 = bits(_T_702, 0, 0)
node _T_704 = or(_T_703, same_cycle_resp_1)
node _T_705 = asUInt(reset)
node _T_706 = eq(_T_705, UInt<1>(0h0))
when _T_706 :
node _T_707 = eq(_T_704, UInt<1>(0h0))
when _T_707 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_704, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<28>(0h0)
connect _WIRE_16.bits.source, UInt<4>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_709 = asUInt(reset)
node _T_710 = eq(_T_709, UInt<1>(0h0))
when _T_710 :
node _T_711 = eq(_T_708, UInt<1>(0h0))
when _T_711 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_708, UInt<1>(0h1), "") : assert_109
else :
node _T_712 = eq(io.in.d.bits.size, c_size_lookup)
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(_T_712, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_712, UInt<1>(0h1), "") : assert_110
node _T_716 = and(io.in.d.valid, d_first_2)
node _T_717 = and(_T_716, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<28>(0h0)
connect _WIRE_18.bits.source, UInt<4>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_718 = and(_T_717, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<28>(0h0)
connect _WIRE_20.bits.source, UInt<4>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_720 = and(_T_718, _T_719)
node _T_721 = and(_T_720, d_release_ack_1)
node _T_722 = eq(c_probe_ack, UInt<1>(0h0))
node _T_723 = and(_T_721, _T_722)
when _T_723 :
node _T_724 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<28>(0h0)
connect _WIRE_22.bits.source, UInt<4>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_725 = or(_T_724, _WIRE_23.ready)
node _T_726 = asUInt(reset)
node _T_727 = eq(_T_726, UInt<1>(0h0))
when _T_727 :
node _T_728 = eq(_T_725, UInt<1>(0h0))
when _T_728 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_725, UInt<1>(0h1), "") : assert_111
node _T_729 = orr(c_set_wo_ready)
when _T_729 :
node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_731 = asUInt(reset)
node _T_732 = eq(_T_731, UInt<1>(0h0))
when _T_732 :
node _T_733 = eq(_T_730, UInt<1>(0h0))
when _T_733 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_730, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_111
node _T_734 = orr(inflight_1)
node _T_735 = eq(_T_734, UInt<1>(0h0))
node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_737 = or(_T_735, _T_736)
node _T_738 = lt(watchdog_1, plusarg_reader_1.out)
node _T_739 = or(_T_737, _T_738)
node _T_740 = asUInt(reset)
node _T_741 = eq(_T_740, UInt<1>(0h0))
when _T_741 :
node _T_742 = eq(_T_739, UInt<1>(0h0))
when _T_742 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_739, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<28>(0h0)
connect _WIRE_24.bits.source, UInt<4>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_744 = and(io.in.d.ready, io.in.d.valid)
node _T_745 = or(_T_743, _T_744)
when _T_745 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_55( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54]
wire [130:0] _c_sizes_set_T_1 = 131'h0; // @[Monitor.scala:768:52]
wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79]
wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35]
wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35]
wire [39:0] c_opcodes_set = 40'h0; // @[Monitor.scala:740:34]
wire [39:0] c_sizes_set = 40'h0; // @[Monitor.scala:741:34]
wire [9:0] c_set = 10'h0; // @[Monitor.scala:738:34]
wire [9:0] c_set_wo_ready = 10'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 4'hA; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [3:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 4'hA; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_672; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [3:0] source; // @[Monitor.scala:390:22]
reg [27:0] address; // @[Monitor.scala:391:22]
wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_745; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [3:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [9:0] inflight; // @[Monitor.scala:614:27]
reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [39:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [9:0] a_set; // @[Monitor.scala:626:34]
wire [9:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [39:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [39:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [39:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [39:0] _a_opcode_lookup_T_6 = {36'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [39:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [39:0] _a_size_lookup_T_6 = {36'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [15:0] _GEN_2 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [15:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_598 ? _a_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [6:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [6:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [6:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [130:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [9:0] d_clr; // @[Monitor.scala:664:34]
wire [9:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [39:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [15:0] _GEN_5 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_613 ? _d_clr_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [142:0] _d_sizes_clr_T_5 = 143'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [9:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [9:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [9:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [39:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [39:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [39:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [39:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [9:0] inflight_1; // @[Monitor.scala:726:35]
wire [9:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [39:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [39:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [39:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [39:0] _c_opcode_lookup_T_6 = {36'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [39:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [39:0] _c_size_lookup_T_6 = {36'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [9:0] d_clr_1; // @[Monitor.scala:774:34]
wire [9:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [39:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_698 ? _d_clr_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [142:0] _d_sizes_clr_T_11 = 143'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113]
wire [9:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [9:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [39:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [39:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module EgressUnit_68 :
input clock : Clock
input reset : Reset
output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], credit_available : UInt<1>[1], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[1], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[1], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[1], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
regreset channel_empty : UInt<1>, clock, reset, UInt<1>(0h1)
reg flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, clock
inst q of Queue3_EgressFlit_68
connect q.clock, clock
connect q.reset, reset
connect q.io.enq.valid, io.in[0].valid
connect q.io.enq.bits.head, io.in[0].bits.head
connect q.io.enq.bits.tail, io.in[0].bits.tail
node _q_io_enq_bits_ingress_id_T = eq(UInt<2>(0h3), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_1 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_2 = and(_q_io_enq_bits_ingress_id_T, _q_io_enq_bits_ingress_id_T_1)
node _q_io_enq_bits_ingress_id_T_3 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_4 = eq(UInt<2>(0h3), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_5 = and(_q_io_enq_bits_ingress_id_T_3, _q_io_enq_bits_ingress_id_T_4)
node _q_io_enq_bits_ingress_id_T_6 = mux(_q_io_enq_bits_ingress_id_T_2, UInt<5>(0hf), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_7 = mux(_q_io_enq_bits_ingress_id_T_5, UInt<5>(0h15), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_8 = or(_q_io_enq_bits_ingress_id_T_6, _q_io_enq_bits_ingress_id_T_7)
wire _q_io_enq_bits_ingress_id_WIRE : UInt<5>
connect _q_io_enq_bits_ingress_id_WIRE, _q_io_enq_bits_ingress_id_T_8
connect q.io.enq.bits.ingress_id, _q_io_enq_bits_ingress_id_WIRE
connect q.io.enq.bits.payload, io.in[0].bits.payload
connect io.out.bits, q.io.deq.bits
connect io.out.valid, q.io.deq.valid
connect q.io.deq.ready, io.out.ready
node _T = eq(q.io.enq.ready, UInt<1>(0h0))
node _T_1 = and(q.io.enq.valid, _T)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at EgressUnit.scala:38 assert(!(q.io.enq.valid && !q.io.enq.ready))\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _io_credit_available_0_T = eq(q.io.count, UInt<1>(0h0))
connect io.credit_available[0], _io_credit_available_0_T
node _io_channel_status_0_occupied_T = eq(channel_empty, UInt<1>(0h0))
connect io.channel_status[0].occupied, _io_channel_status_0_occupied_T
connect io.channel_status[0].flow, flow
node _T_6 = and(io.credit_alloc[0].alloc, io.credit_alloc[0].tail)
when _T_6 :
connect channel_empty, UInt<1>(0h1)
when io.allocs[0].alloc :
connect channel_empty, UInt<1>(0h0)
connect flow, io.allocs[0].flow | module EgressUnit_68( // @[EgressUnit.scala:12:7]
input clock, // @[EgressUnit.scala:12:7]
input reset, // @[EgressUnit.scala:12:7]
input io_in_0_valid, // @[EgressUnit.scala:18:14]
input io_in_0_bits_head, // @[EgressUnit.scala:18:14]
input io_in_0_bits_tail, // @[EgressUnit.scala:18:14]
input [72:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14]
input [3:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14]
input [1:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14]
output io_credit_available_0, // @[EgressUnit.scala:18:14]
output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14]
input io_allocs_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14]
input io_out_ready, // @[EgressUnit.scala:18:14]
output io_out_valid, // @[EgressUnit.scala:18:14]
output io_out_bits_head, // @[EgressUnit.scala:18:14]
output io_out_bits_tail, // @[EgressUnit.scala:18:14]
output [72:0] io_out_bits_payload // @[EgressUnit.scala:18:14]
);
wire _q_io_enq_ready; // @[EgressUnit.scala:22:17]
wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17]
reg channel_empty; // @[EgressUnit.scala:20:30] |
Generate the Verilog code corresponding to this FIRRTL code module PE_479 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_223
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<8>, clock
reg c2 : SInt<8>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h0), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node _c1_T = bits(io.in_d, 7, 0)
node _c1_T_1 = asSInt(_c1_T)
connect c1, _c1_T_1
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node _c2_T = bits(io.in_d, 7, 0)
node _c2_T_1 = asSInt(_c2_T)
connect c2, _c2_T_1
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h0), _T_4)
node _T_6 = or(UInt<1>(0h1), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_479( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid // @[PE.scala:35:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7]
wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60]
wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [7:0] c1; // @[PE.scala:70:15]
wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [7:0] c2; // @[PE.scala:71:15]
wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25]
wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}]
wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16]
wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8]
c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15]
if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8]
c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15]
if (io_in_valid_0) // @[PE.scala:31:7]
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
always @(posedge)
MacUnit_223 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_b_0), // @[PE.scala:31:7]
.io_out_d (io_out_b_0)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RenameMapTable_1 :
input clock : Clock
input reset : Reset
output io : { flip map_reqs : { lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst : UInt<6>}[1], map_resps : { prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, stale_pdst : UInt<6>}[1], flip remap_reqs : { ldst : UInt<6>, pdst : UInt<6>, valid : UInt<1>}[1], flip ren_br_tags : { valid : UInt<1>, bits : UInt<3>}[1], flip brupdate : { b1 : { resolve_mask : UInt<8>, mispredict_mask : UInt<8>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip rollback : UInt<1>}
wire _map_table_WIRE : UInt<6>[32]
connect _map_table_WIRE[0], UInt<6>(0h0)
connect _map_table_WIRE[1], UInt<6>(0h0)
connect _map_table_WIRE[2], UInt<6>(0h0)
connect _map_table_WIRE[3], UInt<6>(0h0)
connect _map_table_WIRE[4], UInt<6>(0h0)
connect _map_table_WIRE[5], UInt<6>(0h0)
connect _map_table_WIRE[6], UInt<6>(0h0)
connect _map_table_WIRE[7], UInt<6>(0h0)
connect _map_table_WIRE[8], UInt<6>(0h0)
connect _map_table_WIRE[9], UInt<6>(0h0)
connect _map_table_WIRE[10], UInt<6>(0h0)
connect _map_table_WIRE[11], UInt<6>(0h0)
connect _map_table_WIRE[12], UInt<6>(0h0)
connect _map_table_WIRE[13], UInt<6>(0h0)
connect _map_table_WIRE[14], UInt<6>(0h0)
connect _map_table_WIRE[15], UInt<6>(0h0)
connect _map_table_WIRE[16], UInt<6>(0h0)
connect _map_table_WIRE[17], UInt<6>(0h0)
connect _map_table_WIRE[18], UInt<6>(0h0)
connect _map_table_WIRE[19], UInt<6>(0h0)
connect _map_table_WIRE[20], UInt<6>(0h0)
connect _map_table_WIRE[21], UInt<6>(0h0)
connect _map_table_WIRE[22], UInt<6>(0h0)
connect _map_table_WIRE[23], UInt<6>(0h0)
connect _map_table_WIRE[24], UInt<6>(0h0)
connect _map_table_WIRE[25], UInt<6>(0h0)
connect _map_table_WIRE[26], UInt<6>(0h0)
connect _map_table_WIRE[27], UInt<6>(0h0)
connect _map_table_WIRE[28], UInt<6>(0h0)
connect _map_table_WIRE[29], UInt<6>(0h0)
connect _map_table_WIRE[30], UInt<6>(0h0)
connect _map_table_WIRE[31], UInt<6>(0h0)
regreset map_table : UInt<6>[32], clock, reset, _map_table_WIRE
reg br_snapshots : UInt<6>[32][8], clock
wire remap_table : UInt<6>[32][2]
node _remap_ldsts_oh_T = dshl(UInt<1>(0h1), io.remap_reqs[0].ldst)
node _remap_ldsts_oh_T_1 = mux(io.remap_reqs[0].valid, UInt<32>(0hffffffff), UInt<32>(0h0))
node remap_ldsts_oh_0 = and(_remap_ldsts_oh_T, _remap_ldsts_oh_T_1)
node _remapped_row_T = bits(remap_ldsts_oh_0, 0, 0)
node remapped_row_1 = mux(_remapped_row_T, io.remap_reqs[0].pdst, map_table[0])
connect remap_table[0][0], map_table[0]
connect remap_table[1][0], remapped_row_1
node _remapped_row_T_1 = bits(remap_ldsts_oh_0, 1, 1)
node remapped_row_1_1 = mux(_remapped_row_T_1, io.remap_reqs[0].pdst, map_table[1])
connect remap_table[0][1], map_table[1]
connect remap_table[1][1], remapped_row_1_1
node _remapped_row_T_2 = bits(remap_ldsts_oh_0, 2, 2)
node remapped_row_1_2 = mux(_remapped_row_T_2, io.remap_reqs[0].pdst, map_table[2])
connect remap_table[0][2], map_table[2]
connect remap_table[1][2], remapped_row_1_2
node _remapped_row_T_3 = bits(remap_ldsts_oh_0, 3, 3)
node remapped_row_1_3 = mux(_remapped_row_T_3, io.remap_reqs[0].pdst, map_table[3])
connect remap_table[0][3], map_table[3]
connect remap_table[1][3], remapped_row_1_3
node _remapped_row_T_4 = bits(remap_ldsts_oh_0, 4, 4)
node remapped_row_1_4 = mux(_remapped_row_T_4, io.remap_reqs[0].pdst, map_table[4])
connect remap_table[0][4], map_table[4]
connect remap_table[1][4], remapped_row_1_4
node _remapped_row_T_5 = bits(remap_ldsts_oh_0, 5, 5)
node remapped_row_1_5 = mux(_remapped_row_T_5, io.remap_reqs[0].pdst, map_table[5])
connect remap_table[0][5], map_table[5]
connect remap_table[1][5], remapped_row_1_5
node _remapped_row_T_6 = bits(remap_ldsts_oh_0, 6, 6)
node remapped_row_1_6 = mux(_remapped_row_T_6, io.remap_reqs[0].pdst, map_table[6])
connect remap_table[0][6], map_table[6]
connect remap_table[1][6], remapped_row_1_6
node _remapped_row_T_7 = bits(remap_ldsts_oh_0, 7, 7)
node remapped_row_1_7 = mux(_remapped_row_T_7, io.remap_reqs[0].pdst, map_table[7])
connect remap_table[0][7], map_table[7]
connect remap_table[1][7], remapped_row_1_7
node _remapped_row_T_8 = bits(remap_ldsts_oh_0, 8, 8)
node remapped_row_1_8 = mux(_remapped_row_T_8, io.remap_reqs[0].pdst, map_table[8])
connect remap_table[0][8], map_table[8]
connect remap_table[1][8], remapped_row_1_8
node _remapped_row_T_9 = bits(remap_ldsts_oh_0, 9, 9)
node remapped_row_1_9 = mux(_remapped_row_T_9, io.remap_reqs[0].pdst, map_table[9])
connect remap_table[0][9], map_table[9]
connect remap_table[1][9], remapped_row_1_9
node _remapped_row_T_10 = bits(remap_ldsts_oh_0, 10, 10)
node remapped_row_1_10 = mux(_remapped_row_T_10, io.remap_reqs[0].pdst, map_table[10])
connect remap_table[0][10], map_table[10]
connect remap_table[1][10], remapped_row_1_10
node _remapped_row_T_11 = bits(remap_ldsts_oh_0, 11, 11)
node remapped_row_1_11 = mux(_remapped_row_T_11, io.remap_reqs[0].pdst, map_table[11])
connect remap_table[0][11], map_table[11]
connect remap_table[1][11], remapped_row_1_11
node _remapped_row_T_12 = bits(remap_ldsts_oh_0, 12, 12)
node remapped_row_1_12 = mux(_remapped_row_T_12, io.remap_reqs[0].pdst, map_table[12])
connect remap_table[0][12], map_table[12]
connect remap_table[1][12], remapped_row_1_12
node _remapped_row_T_13 = bits(remap_ldsts_oh_0, 13, 13)
node remapped_row_1_13 = mux(_remapped_row_T_13, io.remap_reqs[0].pdst, map_table[13])
connect remap_table[0][13], map_table[13]
connect remap_table[1][13], remapped_row_1_13
node _remapped_row_T_14 = bits(remap_ldsts_oh_0, 14, 14)
node remapped_row_1_14 = mux(_remapped_row_T_14, io.remap_reqs[0].pdst, map_table[14])
connect remap_table[0][14], map_table[14]
connect remap_table[1][14], remapped_row_1_14
node _remapped_row_T_15 = bits(remap_ldsts_oh_0, 15, 15)
node remapped_row_1_15 = mux(_remapped_row_T_15, io.remap_reqs[0].pdst, map_table[15])
connect remap_table[0][15], map_table[15]
connect remap_table[1][15], remapped_row_1_15
node _remapped_row_T_16 = bits(remap_ldsts_oh_0, 16, 16)
node remapped_row_1_16 = mux(_remapped_row_T_16, io.remap_reqs[0].pdst, map_table[16])
connect remap_table[0][16], map_table[16]
connect remap_table[1][16], remapped_row_1_16
node _remapped_row_T_17 = bits(remap_ldsts_oh_0, 17, 17)
node remapped_row_1_17 = mux(_remapped_row_T_17, io.remap_reqs[0].pdst, map_table[17])
connect remap_table[0][17], map_table[17]
connect remap_table[1][17], remapped_row_1_17
node _remapped_row_T_18 = bits(remap_ldsts_oh_0, 18, 18)
node remapped_row_1_18 = mux(_remapped_row_T_18, io.remap_reqs[0].pdst, map_table[18])
connect remap_table[0][18], map_table[18]
connect remap_table[1][18], remapped_row_1_18
node _remapped_row_T_19 = bits(remap_ldsts_oh_0, 19, 19)
node remapped_row_1_19 = mux(_remapped_row_T_19, io.remap_reqs[0].pdst, map_table[19])
connect remap_table[0][19], map_table[19]
connect remap_table[1][19], remapped_row_1_19
node _remapped_row_T_20 = bits(remap_ldsts_oh_0, 20, 20)
node remapped_row_1_20 = mux(_remapped_row_T_20, io.remap_reqs[0].pdst, map_table[20])
connect remap_table[0][20], map_table[20]
connect remap_table[1][20], remapped_row_1_20
node _remapped_row_T_21 = bits(remap_ldsts_oh_0, 21, 21)
node remapped_row_1_21 = mux(_remapped_row_T_21, io.remap_reqs[0].pdst, map_table[21])
connect remap_table[0][21], map_table[21]
connect remap_table[1][21], remapped_row_1_21
node _remapped_row_T_22 = bits(remap_ldsts_oh_0, 22, 22)
node remapped_row_1_22 = mux(_remapped_row_T_22, io.remap_reqs[0].pdst, map_table[22])
connect remap_table[0][22], map_table[22]
connect remap_table[1][22], remapped_row_1_22
node _remapped_row_T_23 = bits(remap_ldsts_oh_0, 23, 23)
node remapped_row_1_23 = mux(_remapped_row_T_23, io.remap_reqs[0].pdst, map_table[23])
connect remap_table[0][23], map_table[23]
connect remap_table[1][23], remapped_row_1_23
node _remapped_row_T_24 = bits(remap_ldsts_oh_0, 24, 24)
node remapped_row_1_24 = mux(_remapped_row_T_24, io.remap_reqs[0].pdst, map_table[24])
connect remap_table[0][24], map_table[24]
connect remap_table[1][24], remapped_row_1_24
node _remapped_row_T_25 = bits(remap_ldsts_oh_0, 25, 25)
node remapped_row_1_25 = mux(_remapped_row_T_25, io.remap_reqs[0].pdst, map_table[25])
connect remap_table[0][25], map_table[25]
connect remap_table[1][25], remapped_row_1_25
node _remapped_row_T_26 = bits(remap_ldsts_oh_0, 26, 26)
node remapped_row_1_26 = mux(_remapped_row_T_26, io.remap_reqs[0].pdst, map_table[26])
connect remap_table[0][26], map_table[26]
connect remap_table[1][26], remapped_row_1_26
node _remapped_row_T_27 = bits(remap_ldsts_oh_0, 27, 27)
node remapped_row_1_27 = mux(_remapped_row_T_27, io.remap_reqs[0].pdst, map_table[27])
connect remap_table[0][27], map_table[27]
connect remap_table[1][27], remapped_row_1_27
node _remapped_row_T_28 = bits(remap_ldsts_oh_0, 28, 28)
node remapped_row_1_28 = mux(_remapped_row_T_28, io.remap_reqs[0].pdst, map_table[28])
connect remap_table[0][28], map_table[28]
connect remap_table[1][28], remapped_row_1_28
node _remapped_row_T_29 = bits(remap_ldsts_oh_0, 29, 29)
node remapped_row_1_29 = mux(_remapped_row_T_29, io.remap_reqs[0].pdst, map_table[29])
connect remap_table[0][29], map_table[29]
connect remap_table[1][29], remapped_row_1_29
node _remapped_row_T_30 = bits(remap_ldsts_oh_0, 30, 30)
node remapped_row_1_30 = mux(_remapped_row_T_30, io.remap_reqs[0].pdst, map_table[30])
connect remap_table[0][30], map_table[30]
connect remap_table[1][30], remapped_row_1_30
node _remapped_row_T_31 = bits(remap_ldsts_oh_0, 31, 31)
node remapped_row_1_31 = mux(_remapped_row_T_31, io.remap_reqs[0].pdst, map_table[31])
connect remap_table[0][31], map_table[31]
connect remap_table[1][31], remapped_row_1_31
when io.ren_br_tags[0].valid :
connect br_snapshots[io.ren_br_tags[0].bits], remap_table[1]
when io.brupdate.b2.mispredict :
connect map_table, br_snapshots[io.brupdate.b2.uop.br_tag]
else :
connect map_table, remap_table[1]
node _io_map_resps_0_prs1_T = bits(io.map_reqs[0].lrs1, 4, 0)
connect io.map_resps[0].prs1, map_table[_io_map_resps_0_prs1_T]
node _io_map_resps_0_prs2_T = bits(io.map_reqs[0].lrs2, 4, 0)
connect io.map_resps[0].prs2, map_table[_io_map_resps_0_prs2_T]
node _io_map_resps_0_prs3_T = bits(io.map_reqs[0].lrs3, 4, 0)
connect io.map_resps[0].prs3, map_table[_io_map_resps_0_prs3_T]
node _io_map_resps_0_stale_pdst_T = bits(io.map_reqs[0].ldst, 4, 0)
connect io.map_resps[0].stale_pdst, map_table[_io_map_resps_0_stale_pdst_T]
node _T = eq(io.remap_reqs[0].valid, UInt<1>(0h0))
node _T_1 = eq(map_table[0], io.remap_reqs[0].pdst)
node _T_2 = eq(map_table[1], io.remap_reqs[0].pdst)
node _T_3 = eq(map_table[2], io.remap_reqs[0].pdst)
node _T_4 = eq(map_table[3], io.remap_reqs[0].pdst)
node _T_5 = eq(map_table[4], io.remap_reqs[0].pdst)
node _T_6 = eq(map_table[5], io.remap_reqs[0].pdst)
node _T_7 = eq(map_table[6], io.remap_reqs[0].pdst)
node _T_8 = eq(map_table[7], io.remap_reqs[0].pdst)
node _T_9 = eq(map_table[8], io.remap_reqs[0].pdst)
node _T_10 = eq(map_table[9], io.remap_reqs[0].pdst)
node _T_11 = eq(map_table[10], io.remap_reqs[0].pdst)
node _T_12 = eq(map_table[11], io.remap_reqs[0].pdst)
node _T_13 = eq(map_table[12], io.remap_reqs[0].pdst)
node _T_14 = eq(map_table[13], io.remap_reqs[0].pdst)
node _T_15 = eq(map_table[14], io.remap_reqs[0].pdst)
node _T_16 = eq(map_table[15], io.remap_reqs[0].pdst)
node _T_17 = eq(map_table[16], io.remap_reqs[0].pdst)
node _T_18 = eq(map_table[17], io.remap_reqs[0].pdst)
node _T_19 = eq(map_table[18], io.remap_reqs[0].pdst)
node _T_20 = eq(map_table[19], io.remap_reqs[0].pdst)
node _T_21 = eq(map_table[20], io.remap_reqs[0].pdst)
node _T_22 = eq(map_table[21], io.remap_reqs[0].pdst)
node _T_23 = eq(map_table[22], io.remap_reqs[0].pdst)
node _T_24 = eq(map_table[23], io.remap_reqs[0].pdst)
node _T_25 = eq(map_table[24], io.remap_reqs[0].pdst)
node _T_26 = eq(map_table[25], io.remap_reqs[0].pdst)
node _T_27 = eq(map_table[26], io.remap_reqs[0].pdst)
node _T_28 = eq(map_table[27], io.remap_reqs[0].pdst)
node _T_29 = eq(map_table[28], io.remap_reqs[0].pdst)
node _T_30 = eq(map_table[29], io.remap_reqs[0].pdst)
node _T_31 = eq(map_table[30], io.remap_reqs[0].pdst)
node _T_32 = eq(map_table[31], io.remap_reqs[0].pdst)
node _T_33 = or(UInt<1>(0h0), _T_1)
node _T_34 = or(_T_33, _T_2)
node _T_35 = or(_T_34, _T_3)
node _T_36 = or(_T_35, _T_4)
node _T_37 = or(_T_36, _T_5)
node _T_38 = or(_T_37, _T_6)
node _T_39 = or(_T_38, _T_7)
node _T_40 = or(_T_39, _T_8)
node _T_41 = or(_T_40, _T_9)
node _T_42 = or(_T_41, _T_10)
node _T_43 = or(_T_42, _T_11)
node _T_44 = or(_T_43, _T_12)
node _T_45 = or(_T_44, _T_13)
node _T_46 = or(_T_45, _T_14)
node _T_47 = or(_T_46, _T_15)
node _T_48 = or(_T_47, _T_16)
node _T_49 = or(_T_48, _T_17)
node _T_50 = or(_T_49, _T_18)
node _T_51 = or(_T_50, _T_19)
node _T_52 = or(_T_51, _T_20)
node _T_53 = or(_T_52, _T_21)
node _T_54 = or(_T_53, _T_22)
node _T_55 = or(_T_54, _T_23)
node _T_56 = or(_T_55, _T_24)
node _T_57 = or(_T_56, _T_25)
node _T_58 = or(_T_57, _T_26)
node _T_59 = or(_T_58, _T_27)
node _T_60 = or(_T_59, _T_28)
node _T_61 = or(_T_60, _T_29)
node _T_62 = or(_T_61, _T_30)
node _T_63 = or(_T_62, _T_31)
node _T_64 = or(_T_63, _T_32)
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = or(_T, _T_65)
node _T_67 = eq(io.remap_reqs[0].pdst, UInt<1>(0h0))
node _T_68 = and(_T_67, io.rollback)
node _T_69 = or(_T_66, _T_68)
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: [maptable] Trying to write a duplicate mapping.\n at rename-maptable.scala:128 assert (!r || !map_table.contains(p) || p === 0.U && io.rollback, \"[maptable] Trying to write a duplicate mapping.\")}\n") : printf
assert(clock, _T_69, UInt<1>(0h1), "") : assert | module RenameMapTable_1( // @[rename-maptable.scala:43:7]
input clock, // @[rename-maptable.scala:43:7]
input reset, // @[rename-maptable.scala:43:7]
input [5:0] io_map_reqs_0_lrs1, // @[rename-maptable.scala:53:14]
input [5:0] io_map_reqs_0_lrs2, // @[rename-maptable.scala:53:14]
input [5:0] io_map_reqs_0_lrs3, // @[rename-maptable.scala:53:14]
input [5:0] io_map_reqs_0_ldst, // @[rename-maptable.scala:53:14]
output [5:0] io_map_resps_0_prs1, // @[rename-maptable.scala:53:14]
output [5:0] io_map_resps_0_prs2, // @[rename-maptable.scala:53:14]
output [5:0] io_map_resps_0_prs3, // @[rename-maptable.scala:53:14]
output [5:0] io_map_resps_0_stale_pdst, // @[rename-maptable.scala:53:14]
input [5:0] io_remap_reqs_0_ldst, // @[rename-maptable.scala:53:14]
input [5:0] io_remap_reqs_0_pdst, // @[rename-maptable.scala:53:14]
input io_remap_reqs_0_valid, // @[rename-maptable.scala:53:14]
input io_ren_br_tags_0_valid, // @[rename-maptable.scala:53:14]
input [2:0] io_ren_br_tags_0_bits, // @[rename-maptable.scala:53:14]
input [7:0] io_brupdate_b1_resolve_mask, // @[rename-maptable.scala:53:14]
input [7:0] io_brupdate_b1_mispredict_mask, // @[rename-maptable.scala:53:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[rename-maptable.scala:53:14]
input [31:0] io_brupdate_b2_uop_inst, // @[rename-maptable.scala:53:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[rename-maptable.scala:53:14]
input io_brupdate_b2_uop_is_rvc, // @[rename-maptable.scala:53:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[rename-maptable.scala:53:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[rename-maptable.scala:53:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[rename-maptable.scala:53:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[rename-maptable.scala:53:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[rename-maptable.scala:53:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[rename-maptable.scala:53:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[rename-maptable.scala:53:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[rename-maptable.scala:53:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[rename-maptable.scala:53:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[rename-maptable.scala:53:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[rename-maptable.scala:53:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[rename-maptable.scala:53:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[rename-maptable.scala:53:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[rename-maptable.scala:53:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[rename-maptable.scala:53:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[rename-maptable.scala:53:14]
input io_brupdate_b2_uop_is_br, // @[rename-maptable.scala:53:14]
input io_brupdate_b2_uop_is_jalr, // @[rename-maptable.scala:53:14]
input io_brupdate_b2_uop_is_jal, // @[rename-maptable.scala:53:14]
input io_brupdate_b2_uop_is_sfb, // @[rename-maptable.scala:53:14]
input [7:0] io_brupdate_b2_uop_br_mask, // @[rename-maptable.scala:53:14]
input [2:0] io_brupdate_b2_uop_br_tag, // @[rename-maptable.scala:53:14]
input [3:0] io_brupdate_b2_uop_ftq_idx, // @[rename-maptable.scala:53:14]
input io_brupdate_b2_uop_edge_inst, // @[rename-maptable.scala:53:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[rename-maptable.scala:53:14]
input io_brupdate_b2_uop_taken, // @[rename-maptable.scala:53:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[rename-maptable.scala:53:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[rename-maptable.scala:53:14]
input [4:0] io_brupdate_b2_uop_rob_idx, // @[rename-maptable.scala:53:14]
input [2:0] io_brupdate_b2_uop_ldq_idx, // @[rename-maptable.scala:53:14]
input [2:0] io_brupdate_b2_uop_stq_idx, // @[rename-maptable.scala:53:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[rename-maptable.scala:53:14]
input [5:0] io_brupdate_b2_uop_pdst, // @[rename-maptable.scala:53:14]
input [5:0] io_brupdate_b2_uop_prs1, // @[rename-maptable.scala:53:14]
input [5:0] io_brupdate_b2_uop_prs2, // @[rename-maptable.scala:53:14]
input [5:0] io_brupdate_b2_uop_prs3, // @[rename-maptable.scala:53:14]
input [3:0] io_brupdate_b2_uop_ppred, // @[rename-maptable.scala:53:14]
input io_brupdate_b2_uop_prs1_busy, // @[rename-maptable.scala:53:14]
input io_brupdate_b2_uop_prs2_busy, // @[rename-maptable.scala:53:14]
input io_brupdate_b2_uop_prs3_busy, // @[rename-maptable.scala:53:14]
input io_brupdate_b2_uop_ppred_busy, // @[rename-maptable.scala:53:14]
input [5:0] io_brupdate_b2_uop_stale_pdst, // @[rename-maptable.scala:53:14]
input io_brupdate_b2_uop_exception, // @[rename-maptable.scala:53:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[rename-maptable.scala:53:14]
input io_brupdate_b2_uop_bypassable, // @[rename-maptable.scala:53:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[rename-maptable.scala:53:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[rename-maptable.scala:53:14]
input io_brupdate_b2_uop_mem_signed, // @[rename-maptable.scala:53:14]
input io_brupdate_b2_uop_is_fence, // @[rename-maptable.scala:53:14]
input io_brupdate_b2_uop_is_fencei, // @[rename-maptable.scala:53:14]
input io_brupdate_b2_uop_is_amo, // @[rename-maptable.scala:53:14]
input io_brupdate_b2_uop_uses_ldq, // @[rename-maptable.scala:53:14]
input io_brupdate_b2_uop_uses_stq, // @[rename-maptable.scala:53:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[rename-maptable.scala:53:14]
input io_brupdate_b2_uop_is_unique, // @[rename-maptable.scala:53:14]
input io_brupdate_b2_uop_flush_on_commit, // @[rename-maptable.scala:53:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[rename-maptable.scala:53:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[rename-maptable.scala:53:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[rename-maptable.scala:53:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[rename-maptable.scala:53:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[rename-maptable.scala:53:14]
input io_brupdate_b2_uop_ldst_val, // @[rename-maptable.scala:53:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[rename-maptable.scala:53:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[rename-maptable.scala:53:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[rename-maptable.scala:53:14]
input io_brupdate_b2_uop_frs3_en, // @[rename-maptable.scala:53:14]
input io_brupdate_b2_uop_fp_val, // @[rename-maptable.scala:53:14]
input io_brupdate_b2_uop_fp_single, // @[rename-maptable.scala:53:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[rename-maptable.scala:53:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[rename-maptable.scala:53:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[rename-maptable.scala:53:14]
input io_brupdate_b2_uop_bp_debug_if, // @[rename-maptable.scala:53:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[rename-maptable.scala:53:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[rename-maptable.scala:53:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[rename-maptable.scala:53:14]
input io_brupdate_b2_valid, // @[rename-maptable.scala:53:14]
input io_brupdate_b2_mispredict, // @[rename-maptable.scala:53:14]
input io_brupdate_b2_taken, // @[rename-maptable.scala:53:14]
input [2:0] io_brupdate_b2_cfi_type, // @[rename-maptable.scala:53:14]
input [1:0] io_brupdate_b2_pc_sel, // @[rename-maptable.scala:53:14]
input [39:0] io_brupdate_b2_jalr_target, // @[rename-maptable.scala:53:14]
input [20:0] io_brupdate_b2_target_offset, // @[rename-maptable.scala:53:14]
input io_rollback // @[rename-maptable.scala:53:14]
);
wire [5:0] io_map_reqs_0_lrs1_0 = io_map_reqs_0_lrs1; // @[rename-maptable.scala:43:7]
wire [5:0] io_map_reqs_0_lrs2_0 = io_map_reqs_0_lrs2; // @[rename-maptable.scala:43:7]
wire [5:0] io_map_reqs_0_lrs3_0 = io_map_reqs_0_lrs3; // @[rename-maptable.scala:43:7]
wire [5:0] io_map_reqs_0_ldst_0 = io_map_reqs_0_ldst; // @[rename-maptable.scala:43:7]
wire [5:0] io_remap_reqs_0_ldst_0 = io_remap_reqs_0_ldst; // @[rename-maptable.scala:43:7]
wire [5:0] io_remap_reqs_0_pdst_0 = io_remap_reqs_0_pdst; // @[rename-maptable.scala:43:7]
wire io_remap_reqs_0_valid_0 = io_remap_reqs_0_valid; // @[rename-maptable.scala:43:7]
wire io_ren_br_tags_0_valid_0 = io_ren_br_tags_0_valid; // @[rename-maptable.scala:43:7]
wire [2:0] io_ren_br_tags_0_bits_0 = io_ren_br_tags_0_bits; // @[rename-maptable.scala:43:7]
wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[rename-maptable.scala:43:7]
wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[rename-maptable.scala:43:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[rename-maptable.scala:43:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[rename-maptable.scala:43:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[rename-maptable.scala:43:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[rename-maptable.scala:43:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[rename-maptable.scala:43:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[rename-maptable.scala:43:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[rename-maptable.scala:43:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[rename-maptable.scala:43:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[rename-maptable.scala:43:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[rename-maptable.scala:43:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[rename-maptable.scala:43:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[rename-maptable.scala:43:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[rename-maptable.scala:43:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[rename-maptable.scala:43:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[rename-maptable.scala:43:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[rename-maptable.scala:43:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[rename-maptable.scala:43:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[rename-maptable.scala:43:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[rename-maptable.scala:43:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[rename-maptable.scala:43:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[rename-maptable.scala:43:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[rename-maptable.scala:43:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[rename-maptable.scala:43:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[rename-maptable.scala:43:7]
wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[rename-maptable.scala:43:7]
wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[rename-maptable.scala:43:7]
wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[rename-maptable.scala:43:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[rename-maptable.scala:43:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[rename-maptable.scala:43:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[rename-maptable.scala:43:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[rename-maptable.scala:43:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[rename-maptable.scala:43:7]
wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[rename-maptable.scala:43:7]
wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[rename-maptable.scala:43:7]
wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[rename-maptable.scala:43:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[rename-maptable.scala:43:7]
wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[rename-maptable.scala:43:7]
wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[rename-maptable.scala:43:7]
wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[rename-maptable.scala:43:7]
wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[rename-maptable.scala:43:7]
wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[rename-maptable.scala:43:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[rename-maptable.scala:43:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[rename-maptable.scala:43:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[rename-maptable.scala:43:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[rename-maptable.scala:43:7]
wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[rename-maptable.scala:43:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[rename-maptable.scala:43:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[rename-maptable.scala:43:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[rename-maptable.scala:43:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[rename-maptable.scala:43:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[rename-maptable.scala:43:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[rename-maptable.scala:43:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[rename-maptable.scala:43:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[rename-maptable.scala:43:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[rename-maptable.scala:43:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[rename-maptable.scala:43:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[rename-maptable.scala:43:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[rename-maptable.scala:43:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[rename-maptable.scala:43:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[rename-maptable.scala:43:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[rename-maptable.scala:43:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[rename-maptable.scala:43:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[rename-maptable.scala:43:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[rename-maptable.scala:43:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[rename-maptable.scala:43:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[rename-maptable.scala:43:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[rename-maptable.scala:43:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[rename-maptable.scala:43:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[rename-maptable.scala:43:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[rename-maptable.scala:43:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[rename-maptable.scala:43:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[rename-maptable.scala:43:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[rename-maptable.scala:43:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[rename-maptable.scala:43:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[rename-maptable.scala:43:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[rename-maptable.scala:43:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[rename-maptable.scala:43:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[rename-maptable.scala:43:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[rename-maptable.scala:43:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[rename-maptable.scala:43:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[rename-maptable.scala:43:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[rename-maptable.scala:43:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[rename-maptable.scala:43:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[rename-maptable.scala:43:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[rename-maptable.scala:43:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[rename-maptable.scala:43:7]
wire io_rollback_0 = io_rollback; // @[rename-maptable.scala:43:7]
wire [5:0] _map_table_WIRE_0 = 6'h0; // @[rename-maptable.scala:70:34]
wire [5:0] _map_table_WIRE_1 = 6'h0; // @[rename-maptable.scala:70:34]
wire [5:0] _map_table_WIRE_2 = 6'h0; // @[rename-maptable.scala:70:34]
wire [5:0] _map_table_WIRE_3 = 6'h0; // @[rename-maptable.scala:70:34]
wire [5:0] _map_table_WIRE_4 = 6'h0; // @[rename-maptable.scala:70:34]
wire [5:0] _map_table_WIRE_5 = 6'h0; // @[rename-maptable.scala:70:34]
wire [5:0] _map_table_WIRE_6 = 6'h0; // @[rename-maptable.scala:70:34]
wire [5:0] _map_table_WIRE_7 = 6'h0; // @[rename-maptable.scala:70:34]
wire [5:0] _map_table_WIRE_8 = 6'h0; // @[rename-maptable.scala:70:34]
wire [5:0] _map_table_WIRE_9 = 6'h0; // @[rename-maptable.scala:70:34]
wire [5:0] _map_table_WIRE_10 = 6'h0; // @[rename-maptable.scala:70:34]
wire [5:0] _map_table_WIRE_11 = 6'h0; // @[rename-maptable.scala:70:34]
wire [5:0] _map_table_WIRE_12 = 6'h0; // @[rename-maptable.scala:70:34]
wire [5:0] _map_table_WIRE_13 = 6'h0; // @[rename-maptable.scala:70:34]
wire [5:0] _map_table_WIRE_14 = 6'h0; // @[rename-maptable.scala:70:34]
wire [5:0] _map_table_WIRE_15 = 6'h0; // @[rename-maptable.scala:70:34]
wire [5:0] _map_table_WIRE_16 = 6'h0; // @[rename-maptable.scala:70:34]
wire [5:0] _map_table_WIRE_17 = 6'h0; // @[rename-maptable.scala:70:34]
wire [5:0] _map_table_WIRE_18 = 6'h0; // @[rename-maptable.scala:70:34]
wire [5:0] _map_table_WIRE_19 = 6'h0; // @[rename-maptable.scala:70:34]
wire [5:0] _map_table_WIRE_20 = 6'h0; // @[rename-maptable.scala:70:34]
wire [5:0] _map_table_WIRE_21 = 6'h0; // @[rename-maptable.scala:70:34]
wire [5:0] _map_table_WIRE_22 = 6'h0; // @[rename-maptable.scala:70:34]
wire [5:0] _map_table_WIRE_23 = 6'h0; // @[rename-maptable.scala:70:34]
wire [5:0] _map_table_WIRE_24 = 6'h0; // @[rename-maptable.scala:70:34]
wire [5:0] _map_table_WIRE_25 = 6'h0; // @[rename-maptable.scala:70:34]
wire [5:0] _map_table_WIRE_26 = 6'h0; // @[rename-maptable.scala:70:34]
wire [5:0] _map_table_WIRE_27 = 6'h0; // @[rename-maptable.scala:70:34]
wire [5:0] _map_table_WIRE_28 = 6'h0; // @[rename-maptable.scala:70:34]
wire [5:0] _map_table_WIRE_29 = 6'h0; // @[rename-maptable.scala:70:34]
wire [5:0] _map_table_WIRE_30 = 6'h0; // @[rename-maptable.scala:70:34]
wire [5:0] _map_table_WIRE_31 = 6'h0; // @[rename-maptable.scala:70:34]
wire [5:0] io_map_resps_0_prs1_0; // @[rename-maptable.scala:43:7]
wire [5:0] io_map_resps_0_prs2_0; // @[rename-maptable.scala:43:7]
wire [5:0] io_map_resps_0_prs3_0; // @[rename-maptable.scala:43:7]
wire [5:0] io_map_resps_0_stale_pdst_0; // @[rename-maptable.scala:43:7]
reg [5:0] map_table_0; // @[rename-maptable.scala:70:26]
wire [5:0] remap_table_0_0 = map_table_0; // @[rename-maptable.scala:70:26, :74:25]
reg [5:0] map_table_1; // @[rename-maptable.scala:70:26]
wire [5:0] remap_table_0_1 = map_table_1; // @[rename-maptable.scala:70:26, :74:25]
reg [5:0] map_table_2; // @[rename-maptable.scala:70:26]
wire [5:0] remap_table_0_2 = map_table_2; // @[rename-maptable.scala:70:26, :74:25]
reg [5:0] map_table_3; // @[rename-maptable.scala:70:26]
wire [5:0] remap_table_0_3 = map_table_3; // @[rename-maptable.scala:70:26, :74:25]
reg [5:0] map_table_4; // @[rename-maptable.scala:70:26]
wire [5:0] remap_table_0_4 = map_table_4; // @[rename-maptable.scala:70:26, :74:25]
reg [5:0] map_table_5; // @[rename-maptable.scala:70:26]
wire [5:0] remap_table_0_5 = map_table_5; // @[rename-maptable.scala:70:26, :74:25]
reg [5:0] map_table_6; // @[rename-maptable.scala:70:26]
wire [5:0] remap_table_0_6 = map_table_6; // @[rename-maptable.scala:70:26, :74:25]
reg [5:0] map_table_7; // @[rename-maptable.scala:70:26]
wire [5:0] remap_table_0_7 = map_table_7; // @[rename-maptable.scala:70:26, :74:25]
reg [5:0] map_table_8; // @[rename-maptable.scala:70:26]
wire [5:0] remap_table_0_8 = map_table_8; // @[rename-maptable.scala:70:26, :74:25]
reg [5:0] map_table_9; // @[rename-maptable.scala:70:26]
wire [5:0] remap_table_0_9 = map_table_9; // @[rename-maptable.scala:70:26, :74:25]
reg [5:0] map_table_10; // @[rename-maptable.scala:70:26]
wire [5:0] remap_table_0_10 = map_table_10; // @[rename-maptable.scala:70:26, :74:25]
reg [5:0] map_table_11; // @[rename-maptable.scala:70:26]
wire [5:0] remap_table_0_11 = map_table_11; // @[rename-maptable.scala:70:26, :74:25]
reg [5:0] map_table_12; // @[rename-maptable.scala:70:26]
wire [5:0] remap_table_0_12 = map_table_12; // @[rename-maptable.scala:70:26, :74:25]
reg [5:0] map_table_13; // @[rename-maptable.scala:70:26]
wire [5:0] remap_table_0_13 = map_table_13; // @[rename-maptable.scala:70:26, :74:25]
reg [5:0] map_table_14; // @[rename-maptable.scala:70:26]
wire [5:0] remap_table_0_14 = map_table_14; // @[rename-maptable.scala:70:26, :74:25]
reg [5:0] map_table_15; // @[rename-maptable.scala:70:26]
wire [5:0] remap_table_0_15 = map_table_15; // @[rename-maptable.scala:70:26, :74:25]
reg [5:0] map_table_16; // @[rename-maptable.scala:70:26]
wire [5:0] remap_table_0_16 = map_table_16; // @[rename-maptable.scala:70:26, :74:25]
reg [5:0] map_table_17; // @[rename-maptable.scala:70:26]
wire [5:0] remap_table_0_17 = map_table_17; // @[rename-maptable.scala:70:26, :74:25]
reg [5:0] map_table_18; // @[rename-maptable.scala:70:26]
wire [5:0] remap_table_0_18 = map_table_18; // @[rename-maptable.scala:70:26, :74:25]
reg [5:0] map_table_19; // @[rename-maptable.scala:70:26]
wire [5:0] remap_table_0_19 = map_table_19; // @[rename-maptable.scala:70:26, :74:25]
reg [5:0] map_table_20; // @[rename-maptable.scala:70:26]
wire [5:0] remap_table_0_20 = map_table_20; // @[rename-maptable.scala:70:26, :74:25]
reg [5:0] map_table_21; // @[rename-maptable.scala:70:26]
wire [5:0] remap_table_0_21 = map_table_21; // @[rename-maptable.scala:70:26, :74:25]
reg [5:0] map_table_22; // @[rename-maptable.scala:70:26]
wire [5:0] remap_table_0_22 = map_table_22; // @[rename-maptable.scala:70:26, :74:25]
reg [5:0] map_table_23; // @[rename-maptable.scala:70:26]
wire [5:0] remap_table_0_23 = map_table_23; // @[rename-maptable.scala:70:26, :74:25]
reg [5:0] map_table_24; // @[rename-maptable.scala:70:26]
wire [5:0] remap_table_0_24 = map_table_24; // @[rename-maptable.scala:70:26, :74:25]
reg [5:0] map_table_25; // @[rename-maptable.scala:70:26]
wire [5:0] remap_table_0_25 = map_table_25; // @[rename-maptable.scala:70:26, :74:25]
reg [5:0] map_table_26; // @[rename-maptable.scala:70:26]
wire [5:0] remap_table_0_26 = map_table_26; // @[rename-maptable.scala:70:26, :74:25]
reg [5:0] map_table_27; // @[rename-maptable.scala:70:26]
wire [5:0] remap_table_0_27 = map_table_27; // @[rename-maptable.scala:70:26, :74:25]
reg [5:0] map_table_28; // @[rename-maptable.scala:70:26]
wire [5:0] remap_table_0_28 = map_table_28; // @[rename-maptable.scala:70:26, :74:25]
reg [5:0] map_table_29; // @[rename-maptable.scala:70:26]
wire [5:0] remap_table_0_29 = map_table_29; // @[rename-maptable.scala:70:26, :74:25]
reg [5:0] map_table_30; // @[rename-maptable.scala:70:26]
wire [5:0] remap_table_0_30 = map_table_30; // @[rename-maptable.scala:70:26, :74:25]
reg [5:0] map_table_31; // @[rename-maptable.scala:70:26]
wire [5:0] remap_table_0_31 = map_table_31; // @[rename-maptable.scala:70:26, :74:25]
reg [5:0] br_snapshots_0_0; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_0_1; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_0_2; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_0_3; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_0_4; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_0_5; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_0_6; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_0_7; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_0_8; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_0_9; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_0_10; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_0_11; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_0_12; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_0_13; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_0_14; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_0_15; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_0_16; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_0_17; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_0_18; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_0_19; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_0_20; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_0_21; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_0_22; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_0_23; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_0_24; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_0_25; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_0_26; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_0_27; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_0_28; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_0_29; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_0_30; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_0_31; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_1_0; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_1_1; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_1_2; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_1_3; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_1_4; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_1_5; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_1_6; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_1_7; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_1_8; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_1_9; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_1_10; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_1_11; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_1_12; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_1_13; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_1_14; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_1_15; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_1_16; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_1_17; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_1_18; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_1_19; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_1_20; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_1_21; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_1_22; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_1_23; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_1_24; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_1_25; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_1_26; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_1_27; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_1_28; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_1_29; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_1_30; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_1_31; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_2_0; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_2_1; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_2_2; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_2_3; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_2_4; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_2_5; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_2_6; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_2_7; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_2_8; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_2_9; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_2_10; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_2_11; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_2_12; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_2_13; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_2_14; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_2_15; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_2_16; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_2_17; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_2_18; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_2_19; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_2_20; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_2_21; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_2_22; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_2_23; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_2_24; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_2_25; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_2_26; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_2_27; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_2_28; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_2_29; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_2_30; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_2_31; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_3_0; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_3_1; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_3_2; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_3_3; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_3_4; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_3_5; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_3_6; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_3_7; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_3_8; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_3_9; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_3_10; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_3_11; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_3_12; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_3_13; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_3_14; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_3_15; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_3_16; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_3_17; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_3_18; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_3_19; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_3_20; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_3_21; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_3_22; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_3_23; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_3_24; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_3_25; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_3_26; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_3_27; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_3_28; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_3_29; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_3_30; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_3_31; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_4_0; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_4_1; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_4_2; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_4_3; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_4_4; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_4_5; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_4_6; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_4_7; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_4_8; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_4_9; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_4_10; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_4_11; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_4_12; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_4_13; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_4_14; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_4_15; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_4_16; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_4_17; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_4_18; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_4_19; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_4_20; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_4_21; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_4_22; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_4_23; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_4_24; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_4_25; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_4_26; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_4_27; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_4_28; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_4_29; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_4_30; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_4_31; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_5_0; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_5_1; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_5_2; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_5_3; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_5_4; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_5_5; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_5_6; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_5_7; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_5_8; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_5_9; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_5_10; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_5_11; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_5_12; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_5_13; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_5_14; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_5_15; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_5_16; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_5_17; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_5_18; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_5_19; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_5_20; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_5_21; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_5_22; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_5_23; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_5_24; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_5_25; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_5_26; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_5_27; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_5_28; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_5_29; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_5_30; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_5_31; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_6_0; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_6_1; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_6_2; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_6_3; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_6_4; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_6_5; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_6_6; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_6_7; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_6_8; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_6_9; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_6_10; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_6_11; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_6_12; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_6_13; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_6_14; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_6_15; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_6_16; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_6_17; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_6_18; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_6_19; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_6_20; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_6_21; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_6_22; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_6_23; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_6_24; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_6_25; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_6_26; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_6_27; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_6_28; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_6_29; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_6_30; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_6_31; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_7_0; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_7_1; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_7_2; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_7_3; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_7_4; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_7_5; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_7_6; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_7_7; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_7_8; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_7_9; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_7_10; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_7_11; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_7_12; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_7_13; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_7_14; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_7_15; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_7_16; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_7_17; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_7_18; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_7_19; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_7_20; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_7_21; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_7_22; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_7_23; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_7_24; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_7_25; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_7_26; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_7_27; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_7_28; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_7_29; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_7_30; // @[rename-maptable.scala:71:25]
reg [5:0] br_snapshots_7_31; // @[rename-maptable.scala:71:25]
wire [5:0] remapped_row_1; // @[rename-maptable.scala:88:70]
wire [5:0] remapped_row_1_1; // @[rename-maptable.scala:88:70]
wire [5:0] remapped_row_1_2; // @[rename-maptable.scala:88:70]
wire [5:0] remapped_row_1_3; // @[rename-maptable.scala:88:70]
wire [5:0] remapped_row_1_4; // @[rename-maptable.scala:88:70]
wire [5:0] remapped_row_1_5; // @[rename-maptable.scala:88:70]
wire [5:0] remapped_row_1_6; // @[rename-maptable.scala:88:70]
wire [5:0] remapped_row_1_7; // @[rename-maptable.scala:88:70]
wire [5:0] remapped_row_1_8; // @[rename-maptable.scala:88:70]
wire [5:0] remapped_row_1_9; // @[rename-maptable.scala:88:70]
wire [5:0] remapped_row_1_10; // @[rename-maptable.scala:88:70]
wire [5:0] remapped_row_1_11; // @[rename-maptable.scala:88:70]
wire [5:0] remapped_row_1_12; // @[rename-maptable.scala:88:70]
wire [5:0] remapped_row_1_13; // @[rename-maptable.scala:88:70]
wire [5:0] remapped_row_1_14; // @[rename-maptable.scala:88:70]
wire [5:0] remapped_row_1_15; // @[rename-maptable.scala:88:70]
wire [5:0] remapped_row_1_16; // @[rename-maptable.scala:88:70]
wire [5:0] remapped_row_1_17; // @[rename-maptable.scala:88:70]
wire [5:0] remapped_row_1_18; // @[rename-maptable.scala:88:70]
wire [5:0] remapped_row_1_19; // @[rename-maptable.scala:88:70]
wire [5:0] remapped_row_1_20; // @[rename-maptable.scala:88:70]
wire [5:0] remapped_row_1_21; // @[rename-maptable.scala:88:70]
wire [5:0] remapped_row_1_22; // @[rename-maptable.scala:88:70]
wire [5:0] remapped_row_1_23; // @[rename-maptable.scala:88:70]
wire [5:0] remapped_row_1_24; // @[rename-maptable.scala:88:70]
wire [5:0] remapped_row_1_25; // @[rename-maptable.scala:88:70]
wire [5:0] remapped_row_1_26; // @[rename-maptable.scala:88:70]
wire [5:0] remapped_row_1_27; // @[rename-maptable.scala:88:70]
wire [5:0] remapped_row_1_28; // @[rename-maptable.scala:88:70]
wire [5:0] remapped_row_1_29; // @[rename-maptable.scala:88:70]
wire [5:0] remapped_row_1_30; // @[rename-maptable.scala:88:70]
wire [5:0] remapped_row_1_31; // @[rename-maptable.scala:88:70]
wire [5:0] remap_table_1_0; // @[rename-maptable.scala:74:25]
wire [5:0] remap_table_1_1; // @[rename-maptable.scala:74:25]
wire [5:0] remap_table_1_2; // @[rename-maptable.scala:74:25]
wire [5:0] remap_table_1_3; // @[rename-maptable.scala:74:25]
wire [5:0] remap_table_1_4; // @[rename-maptable.scala:74:25]
wire [5:0] remap_table_1_5; // @[rename-maptable.scala:74:25]
wire [5:0] remap_table_1_6; // @[rename-maptable.scala:74:25]
wire [5:0] remap_table_1_7; // @[rename-maptable.scala:74:25]
wire [5:0] remap_table_1_8; // @[rename-maptable.scala:74:25]
wire [5:0] remap_table_1_9; // @[rename-maptable.scala:74:25]
wire [5:0] remap_table_1_10; // @[rename-maptable.scala:74:25]
wire [5:0] remap_table_1_11; // @[rename-maptable.scala:74:25]
wire [5:0] remap_table_1_12; // @[rename-maptable.scala:74:25]
wire [5:0] remap_table_1_13; // @[rename-maptable.scala:74:25]
wire [5:0] remap_table_1_14; // @[rename-maptable.scala:74:25]
wire [5:0] remap_table_1_15; // @[rename-maptable.scala:74:25]
wire [5:0] remap_table_1_16; // @[rename-maptable.scala:74:25]
wire [5:0] remap_table_1_17; // @[rename-maptable.scala:74:25]
wire [5:0] remap_table_1_18; // @[rename-maptable.scala:74:25]
wire [5:0] remap_table_1_19; // @[rename-maptable.scala:74:25]
wire [5:0] remap_table_1_20; // @[rename-maptable.scala:74:25]
wire [5:0] remap_table_1_21; // @[rename-maptable.scala:74:25]
wire [5:0] remap_table_1_22; // @[rename-maptable.scala:74:25]
wire [5:0] remap_table_1_23; // @[rename-maptable.scala:74:25]
wire [5:0] remap_table_1_24; // @[rename-maptable.scala:74:25]
wire [5:0] remap_table_1_25; // @[rename-maptable.scala:74:25]
wire [5:0] remap_table_1_26; // @[rename-maptable.scala:74:25]
wire [5:0] remap_table_1_27; // @[rename-maptable.scala:74:25]
wire [5:0] remap_table_1_28; // @[rename-maptable.scala:74:25]
wire [5:0] remap_table_1_29; // @[rename-maptable.scala:74:25]
wire [5:0] remap_table_1_30; // @[rename-maptable.scala:74:25]
wire [5:0] remap_table_1_31; // @[rename-maptable.scala:74:25]
wire [63:0] _remap_ldsts_oh_T = 64'h1 << io_remap_reqs_0_ldst_0; // @[OneHot.scala:58:35]
wire [31:0] _remap_ldsts_oh_T_1 = {32{io_remap_reqs_0_valid_0}}; // @[rename-maptable.scala:43:7, :78:75]
wire [63:0] remap_ldsts_oh_0 = {32'h0, _remap_ldsts_oh_T[31:0] & _remap_ldsts_oh_T_1}; // @[OneHot.scala:58:35]
wire _remapped_row_T = remap_ldsts_oh_0[0]; // @[rename-maptable.scala:78:69, :87:58]
assign remapped_row_1 = _remapped_row_T ? io_remap_reqs_0_pdst_0 : map_table_0; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70]
assign remap_table_1_0 = remapped_row_1; // @[rename-maptable.scala:74:25, :88:70]
wire _remapped_row_T_1 = remap_ldsts_oh_0[1]; // @[rename-maptable.scala:78:69, :87:58]
assign remapped_row_1_1 = _remapped_row_T_1 ? io_remap_reqs_0_pdst_0 : map_table_1; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70]
assign remap_table_1_1 = remapped_row_1_1; // @[rename-maptable.scala:74:25, :88:70]
wire _remapped_row_T_2 = remap_ldsts_oh_0[2]; // @[rename-maptable.scala:78:69, :87:58]
assign remapped_row_1_2 = _remapped_row_T_2 ? io_remap_reqs_0_pdst_0 : map_table_2; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70]
assign remap_table_1_2 = remapped_row_1_2; // @[rename-maptable.scala:74:25, :88:70]
wire _remapped_row_T_3 = remap_ldsts_oh_0[3]; // @[rename-maptable.scala:78:69, :87:58]
assign remapped_row_1_3 = _remapped_row_T_3 ? io_remap_reqs_0_pdst_0 : map_table_3; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70]
assign remap_table_1_3 = remapped_row_1_3; // @[rename-maptable.scala:74:25, :88:70]
wire _remapped_row_T_4 = remap_ldsts_oh_0[4]; // @[rename-maptable.scala:78:69, :87:58]
assign remapped_row_1_4 = _remapped_row_T_4 ? io_remap_reqs_0_pdst_0 : map_table_4; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70]
assign remap_table_1_4 = remapped_row_1_4; // @[rename-maptable.scala:74:25, :88:70]
wire _remapped_row_T_5 = remap_ldsts_oh_0[5]; // @[rename-maptable.scala:78:69, :87:58]
assign remapped_row_1_5 = _remapped_row_T_5 ? io_remap_reqs_0_pdst_0 : map_table_5; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70]
assign remap_table_1_5 = remapped_row_1_5; // @[rename-maptable.scala:74:25, :88:70]
wire _remapped_row_T_6 = remap_ldsts_oh_0[6]; // @[rename-maptable.scala:78:69, :87:58]
assign remapped_row_1_6 = _remapped_row_T_6 ? io_remap_reqs_0_pdst_0 : map_table_6; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70]
assign remap_table_1_6 = remapped_row_1_6; // @[rename-maptable.scala:74:25, :88:70]
wire _remapped_row_T_7 = remap_ldsts_oh_0[7]; // @[rename-maptable.scala:78:69, :87:58]
assign remapped_row_1_7 = _remapped_row_T_7 ? io_remap_reqs_0_pdst_0 : map_table_7; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70]
assign remap_table_1_7 = remapped_row_1_7; // @[rename-maptable.scala:74:25, :88:70]
wire _remapped_row_T_8 = remap_ldsts_oh_0[8]; // @[rename-maptable.scala:78:69, :87:58]
assign remapped_row_1_8 = _remapped_row_T_8 ? io_remap_reqs_0_pdst_0 : map_table_8; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70]
assign remap_table_1_8 = remapped_row_1_8; // @[rename-maptable.scala:74:25, :88:70]
wire _remapped_row_T_9 = remap_ldsts_oh_0[9]; // @[rename-maptable.scala:78:69, :87:58]
assign remapped_row_1_9 = _remapped_row_T_9 ? io_remap_reqs_0_pdst_0 : map_table_9; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70]
assign remap_table_1_9 = remapped_row_1_9; // @[rename-maptable.scala:74:25, :88:70]
wire _remapped_row_T_10 = remap_ldsts_oh_0[10]; // @[rename-maptable.scala:78:69, :87:58]
assign remapped_row_1_10 = _remapped_row_T_10 ? io_remap_reqs_0_pdst_0 : map_table_10; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70]
assign remap_table_1_10 = remapped_row_1_10; // @[rename-maptable.scala:74:25, :88:70]
wire _remapped_row_T_11 = remap_ldsts_oh_0[11]; // @[rename-maptable.scala:78:69, :87:58]
assign remapped_row_1_11 = _remapped_row_T_11 ? io_remap_reqs_0_pdst_0 : map_table_11; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70]
assign remap_table_1_11 = remapped_row_1_11; // @[rename-maptable.scala:74:25, :88:70]
wire _remapped_row_T_12 = remap_ldsts_oh_0[12]; // @[rename-maptable.scala:78:69, :87:58]
assign remapped_row_1_12 = _remapped_row_T_12 ? io_remap_reqs_0_pdst_0 : map_table_12; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70]
assign remap_table_1_12 = remapped_row_1_12; // @[rename-maptable.scala:74:25, :88:70]
wire _remapped_row_T_13 = remap_ldsts_oh_0[13]; // @[rename-maptable.scala:78:69, :87:58]
assign remapped_row_1_13 = _remapped_row_T_13 ? io_remap_reqs_0_pdst_0 : map_table_13; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70]
assign remap_table_1_13 = remapped_row_1_13; // @[rename-maptable.scala:74:25, :88:70]
wire _remapped_row_T_14 = remap_ldsts_oh_0[14]; // @[rename-maptable.scala:78:69, :87:58]
assign remapped_row_1_14 = _remapped_row_T_14 ? io_remap_reqs_0_pdst_0 : map_table_14; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70]
assign remap_table_1_14 = remapped_row_1_14; // @[rename-maptable.scala:74:25, :88:70]
wire _remapped_row_T_15 = remap_ldsts_oh_0[15]; // @[rename-maptable.scala:78:69, :87:58]
assign remapped_row_1_15 = _remapped_row_T_15 ? io_remap_reqs_0_pdst_0 : map_table_15; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70]
assign remap_table_1_15 = remapped_row_1_15; // @[rename-maptable.scala:74:25, :88:70]
wire _remapped_row_T_16 = remap_ldsts_oh_0[16]; // @[rename-maptable.scala:78:69, :87:58]
assign remapped_row_1_16 = _remapped_row_T_16 ? io_remap_reqs_0_pdst_0 : map_table_16; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70]
assign remap_table_1_16 = remapped_row_1_16; // @[rename-maptable.scala:74:25, :88:70]
wire _remapped_row_T_17 = remap_ldsts_oh_0[17]; // @[rename-maptable.scala:78:69, :87:58]
assign remapped_row_1_17 = _remapped_row_T_17 ? io_remap_reqs_0_pdst_0 : map_table_17; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70]
assign remap_table_1_17 = remapped_row_1_17; // @[rename-maptable.scala:74:25, :88:70]
wire _remapped_row_T_18 = remap_ldsts_oh_0[18]; // @[rename-maptable.scala:78:69, :87:58]
assign remapped_row_1_18 = _remapped_row_T_18 ? io_remap_reqs_0_pdst_0 : map_table_18; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70]
assign remap_table_1_18 = remapped_row_1_18; // @[rename-maptable.scala:74:25, :88:70]
wire _remapped_row_T_19 = remap_ldsts_oh_0[19]; // @[rename-maptable.scala:78:69, :87:58]
assign remapped_row_1_19 = _remapped_row_T_19 ? io_remap_reqs_0_pdst_0 : map_table_19; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70]
assign remap_table_1_19 = remapped_row_1_19; // @[rename-maptable.scala:74:25, :88:70]
wire _remapped_row_T_20 = remap_ldsts_oh_0[20]; // @[rename-maptable.scala:78:69, :87:58]
assign remapped_row_1_20 = _remapped_row_T_20 ? io_remap_reqs_0_pdst_0 : map_table_20; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70]
assign remap_table_1_20 = remapped_row_1_20; // @[rename-maptable.scala:74:25, :88:70]
wire _remapped_row_T_21 = remap_ldsts_oh_0[21]; // @[rename-maptable.scala:78:69, :87:58]
assign remapped_row_1_21 = _remapped_row_T_21 ? io_remap_reqs_0_pdst_0 : map_table_21; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70]
assign remap_table_1_21 = remapped_row_1_21; // @[rename-maptable.scala:74:25, :88:70]
wire _remapped_row_T_22 = remap_ldsts_oh_0[22]; // @[rename-maptable.scala:78:69, :87:58]
assign remapped_row_1_22 = _remapped_row_T_22 ? io_remap_reqs_0_pdst_0 : map_table_22; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70]
assign remap_table_1_22 = remapped_row_1_22; // @[rename-maptable.scala:74:25, :88:70]
wire _remapped_row_T_23 = remap_ldsts_oh_0[23]; // @[rename-maptable.scala:78:69, :87:58]
assign remapped_row_1_23 = _remapped_row_T_23 ? io_remap_reqs_0_pdst_0 : map_table_23; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70]
assign remap_table_1_23 = remapped_row_1_23; // @[rename-maptable.scala:74:25, :88:70]
wire _remapped_row_T_24 = remap_ldsts_oh_0[24]; // @[rename-maptable.scala:78:69, :87:58]
assign remapped_row_1_24 = _remapped_row_T_24 ? io_remap_reqs_0_pdst_0 : map_table_24; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70]
assign remap_table_1_24 = remapped_row_1_24; // @[rename-maptable.scala:74:25, :88:70]
wire _remapped_row_T_25 = remap_ldsts_oh_0[25]; // @[rename-maptable.scala:78:69, :87:58]
assign remapped_row_1_25 = _remapped_row_T_25 ? io_remap_reqs_0_pdst_0 : map_table_25; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70]
assign remap_table_1_25 = remapped_row_1_25; // @[rename-maptable.scala:74:25, :88:70]
wire _remapped_row_T_26 = remap_ldsts_oh_0[26]; // @[rename-maptable.scala:78:69, :87:58]
assign remapped_row_1_26 = _remapped_row_T_26 ? io_remap_reqs_0_pdst_0 : map_table_26; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70]
assign remap_table_1_26 = remapped_row_1_26; // @[rename-maptable.scala:74:25, :88:70]
wire _remapped_row_T_27 = remap_ldsts_oh_0[27]; // @[rename-maptable.scala:78:69, :87:58]
assign remapped_row_1_27 = _remapped_row_T_27 ? io_remap_reqs_0_pdst_0 : map_table_27; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70]
assign remap_table_1_27 = remapped_row_1_27; // @[rename-maptable.scala:74:25, :88:70]
wire _remapped_row_T_28 = remap_ldsts_oh_0[28]; // @[rename-maptable.scala:78:69, :87:58]
assign remapped_row_1_28 = _remapped_row_T_28 ? io_remap_reqs_0_pdst_0 : map_table_28; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70]
assign remap_table_1_28 = remapped_row_1_28; // @[rename-maptable.scala:74:25, :88:70]
wire _remapped_row_T_29 = remap_ldsts_oh_0[29]; // @[rename-maptable.scala:78:69, :87:58]
assign remapped_row_1_29 = _remapped_row_T_29 ? io_remap_reqs_0_pdst_0 : map_table_29; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70]
assign remap_table_1_29 = remapped_row_1_29; // @[rename-maptable.scala:74:25, :88:70]
wire _remapped_row_T_30 = remap_ldsts_oh_0[30]; // @[rename-maptable.scala:78:69, :87:58]
assign remapped_row_1_30 = _remapped_row_T_30 ? io_remap_reqs_0_pdst_0 : map_table_30; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70]
assign remap_table_1_30 = remapped_row_1_30; // @[rename-maptable.scala:74:25, :88:70]
wire _remapped_row_T_31 = remap_ldsts_oh_0[31]; // @[rename-maptable.scala:78:69, :87:58]
assign remapped_row_1_31 = _remapped_row_T_31 ? io_remap_reqs_0_pdst_0 : map_table_31; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70]
assign remap_table_1_31 = remapped_row_1_31; // @[rename-maptable.scala:74:25, :88:70]
wire [4:0] _io_map_resps_0_prs1_T = io_map_reqs_0_lrs1_0[4:0]; // @[rename-maptable.scala:43:7]
wire [31:0][5:0] _GEN = {{map_table_31}, {map_table_30}, {map_table_29}, {map_table_28}, {map_table_27}, {map_table_26}, {map_table_25}, {map_table_24}, {map_table_23}, {map_table_22}, {map_table_21}, {map_table_20}, {map_table_19}, {map_table_18}, {map_table_17}, {map_table_16}, {map_table_15}, {map_table_14}, {map_table_13}, {map_table_12}, {map_table_11}, {map_table_10}, {map_table_9}, {map_table_8}, {map_table_7}, {map_table_6}, {map_table_5}, {map_table_4}, {map_table_3}, {map_table_2}, {map_table_1}, {map_table_0}}; // @[rename-maptable.scala:70:26, :113:32]
assign io_map_resps_0_prs1_0 = _GEN[_io_map_resps_0_prs1_T]; // @[rename-maptable.scala:43:7, :113:32]
wire [4:0] _io_map_resps_0_prs2_T = io_map_reqs_0_lrs2_0[4:0]; // @[rename-maptable.scala:43:7]
assign io_map_resps_0_prs2_0 = _GEN[_io_map_resps_0_prs2_T]; // @[rename-maptable.scala:43:7, :113:32, :115:32]
wire [4:0] _io_map_resps_0_prs3_T = io_map_reqs_0_lrs3_0[4:0]; // @[rename-maptable.scala:43:7]
assign io_map_resps_0_prs3_0 = _GEN[_io_map_resps_0_prs3_T]; // @[rename-maptable.scala:43:7, :113:32, :117:32]
wire [4:0] _io_map_resps_0_stale_pdst_T = io_map_reqs_0_ldst_0[4:0]; // @[rename-maptable.scala:43:7]
assign io_map_resps_0_stale_pdst_0 = _GEN[_io_map_resps_0_stale_pdst_T]; // @[rename-maptable.scala:43:7, :113:32, :119:32] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_12 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<4>, q : UInt<4>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_133
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
node _output_T_2 = asAsyncReset(reset)
node _output_T_3 = bits(io.d, 1, 1)
inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_134
connect output_chain_1.clock, clock
connect output_chain_1.reset, _output_T_2
connect output_chain_1.io.d, _output_T_3
wire output_1 : UInt<1>
connect output_1, output_chain_1.io.q
node _output_T_4 = asAsyncReset(reset)
node _output_T_5 = bits(io.d, 2, 2)
inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_135
connect output_chain_2.clock, clock
connect output_chain_2.reset, _output_T_4
connect output_chain_2.io.d, _output_T_5
wire output_2 : UInt<1>
connect output_2, output_chain_2.io.q
node _output_T_6 = asAsyncReset(reset)
node _output_T_7 = bits(io.d, 3, 3)
inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_136
connect output_chain_3.clock, clock
connect output_chain_3.reset, _output_T_6
connect output_chain_3.io.d, _output_T_7
wire output_3 : UInt<1>
connect output_3, output_chain_3.io.q
node io_q_lo = cat(output_1, output_0)
node io_q_hi = cat(output_3, output_2)
node _io_q_T = cat(io_q_hi, io_q_lo)
connect io.q, _io_q_T | module AsyncResetSynchronizerShiftReg_w4_d3_i0_12( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input [3:0] io_d, // @[ShiftReg.scala:36:14]
output [3:0] io_q // @[ShiftReg.scala:36:14]
);
wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21]
wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14]
wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7]
wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_1; // @[ShiftReg.scala:48:24]
wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_2; // @[ShiftReg.scala:48:24]
wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_3; // @[ShiftReg.scala:48:24]
wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14]
wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14]
assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14]
assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_133 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_134 output_chain_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_2), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_3), // @[SynchronizerReg.scala:87:41]
.io_q (output_1)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_135 output_chain_2 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_4), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_5), // @[SynchronizerReg.scala:87:41]
.io_q (output_2)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_136 output_chain_3 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_6), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_7), // @[SynchronizerReg.scala:87:41]
.io_q (output_3)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module BranchKillableQueue_17 :
input clock : Clock
input reset : Reset
output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>}}, flip brupdate : { b1 : { resolve_mask : UInt<4>, mispredict_mask : UInt<4>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<34>, target_offset : SInt<21>}}, flip flush : UInt<1>, empty : UInt<1>, count : UInt<3>}
cmem ram : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>} [8]
wire _valids_WIRE : UInt<1>[8]
connect _valids_WIRE[0], UInt<1>(0h0)
connect _valids_WIRE[1], UInt<1>(0h0)
connect _valids_WIRE[2], UInt<1>(0h0)
connect _valids_WIRE[3], UInt<1>(0h0)
connect _valids_WIRE[4], UInt<1>(0h0)
connect _valids_WIRE[5], UInt<1>(0h0)
connect _valids_WIRE[6], UInt<1>(0h0)
connect _valids_WIRE[7], UInt<1>(0h0)
regreset valids : UInt<1>[8], clock, reset, _valids_WIRE
reg uops : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[8], clock
regreset enq_ptr_value : UInt<3>, clock, reset, UInt<3>(0h0)
regreset deq_ptr_value : UInt<3>, clock, reset, UInt<3>(0h0)
regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0)
node ptr_match = eq(enq_ptr_value, deq_ptr_value)
node _io_empty_T = eq(maybe_full, UInt<1>(0h0))
node _io_empty_T_1 = and(ptr_match, _io_empty_T)
connect io.empty, _io_empty_T_1
node full = and(ptr_match, maybe_full)
node _do_enq_T = and(io.enq.ready, io.enq.valid)
node _do_enq_T_1 = and(io.brupdate.b1.mispredict_mask, io.enq.bits.uop.br_mask)
node _do_enq_T_2 = neq(_do_enq_T_1, UInt<1>(0h0))
node _do_enq_T_3 = or(_do_enq_T_2, UInt<1>(0h0))
node _do_enq_T_4 = eq(_do_enq_T_3, UInt<1>(0h0))
node _do_enq_T_5 = and(_do_enq_T, _do_enq_T_4)
node _do_enq_T_6 = and(io.flush, UInt<1>(0h1))
node _do_enq_T_7 = eq(_do_enq_T_6, UInt<1>(0h0))
node _do_enq_T_8 = and(_do_enq_T_5, _do_enq_T_7)
wire do_enq : UInt<1>
connect do_enq, _do_enq_T_8
node _do_deq_T = eq(valids[deq_ptr_value], UInt<1>(0h0))
node _do_deq_T_1 = or(io.deq.ready, _do_deq_T)
node _do_deq_T_2 = eq(io.empty, UInt<1>(0h0))
node _do_deq_T_3 = and(_do_deq_T_1, _do_deq_T_2)
wire do_deq : UInt<1>
connect do_deq, _do_deq_T_3
node _valids_0_T = and(io.brupdate.b1.mispredict_mask, uops[0].br_mask)
node _valids_0_T_1 = neq(_valids_0_T, UInt<1>(0h0))
node _valids_0_T_2 = or(_valids_0_T_1, UInt<1>(0h0))
node _valids_0_T_3 = eq(_valids_0_T_2, UInt<1>(0h0))
node _valids_0_T_4 = and(valids[0], _valids_0_T_3)
node _valids_0_T_5 = and(io.flush, UInt<1>(0h1))
node _valids_0_T_6 = eq(_valids_0_T_5, UInt<1>(0h0))
node _valids_0_T_7 = and(_valids_0_T_4, _valids_0_T_6)
connect valids[0], _valids_0_T_7
when valids[0] :
node _uops_0_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_0_br_mask_T_1 = and(uops[0].br_mask, _uops_0_br_mask_T)
connect uops[0].br_mask, _uops_0_br_mask_T_1
node _valids_1_T = and(io.brupdate.b1.mispredict_mask, uops[1].br_mask)
node _valids_1_T_1 = neq(_valids_1_T, UInt<1>(0h0))
node _valids_1_T_2 = or(_valids_1_T_1, UInt<1>(0h0))
node _valids_1_T_3 = eq(_valids_1_T_2, UInt<1>(0h0))
node _valids_1_T_4 = and(valids[1], _valids_1_T_3)
node _valids_1_T_5 = and(io.flush, UInt<1>(0h1))
node _valids_1_T_6 = eq(_valids_1_T_5, UInt<1>(0h0))
node _valids_1_T_7 = and(_valids_1_T_4, _valids_1_T_6)
connect valids[1], _valids_1_T_7
when valids[1] :
node _uops_1_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_1_br_mask_T_1 = and(uops[1].br_mask, _uops_1_br_mask_T)
connect uops[1].br_mask, _uops_1_br_mask_T_1
node _valids_2_T = and(io.brupdate.b1.mispredict_mask, uops[2].br_mask)
node _valids_2_T_1 = neq(_valids_2_T, UInt<1>(0h0))
node _valids_2_T_2 = or(_valids_2_T_1, UInt<1>(0h0))
node _valids_2_T_3 = eq(_valids_2_T_2, UInt<1>(0h0))
node _valids_2_T_4 = and(valids[2], _valids_2_T_3)
node _valids_2_T_5 = and(io.flush, UInt<1>(0h1))
node _valids_2_T_6 = eq(_valids_2_T_5, UInt<1>(0h0))
node _valids_2_T_7 = and(_valids_2_T_4, _valids_2_T_6)
connect valids[2], _valids_2_T_7
when valids[2] :
node _uops_2_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_2_br_mask_T_1 = and(uops[2].br_mask, _uops_2_br_mask_T)
connect uops[2].br_mask, _uops_2_br_mask_T_1
node _valids_3_T = and(io.brupdate.b1.mispredict_mask, uops[3].br_mask)
node _valids_3_T_1 = neq(_valids_3_T, UInt<1>(0h0))
node _valids_3_T_2 = or(_valids_3_T_1, UInt<1>(0h0))
node _valids_3_T_3 = eq(_valids_3_T_2, UInt<1>(0h0))
node _valids_3_T_4 = and(valids[3], _valids_3_T_3)
node _valids_3_T_5 = and(io.flush, UInt<1>(0h1))
node _valids_3_T_6 = eq(_valids_3_T_5, UInt<1>(0h0))
node _valids_3_T_7 = and(_valids_3_T_4, _valids_3_T_6)
connect valids[3], _valids_3_T_7
when valids[3] :
node _uops_3_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_3_br_mask_T_1 = and(uops[3].br_mask, _uops_3_br_mask_T)
connect uops[3].br_mask, _uops_3_br_mask_T_1
node _valids_4_T = and(io.brupdate.b1.mispredict_mask, uops[4].br_mask)
node _valids_4_T_1 = neq(_valids_4_T, UInt<1>(0h0))
node _valids_4_T_2 = or(_valids_4_T_1, UInt<1>(0h0))
node _valids_4_T_3 = eq(_valids_4_T_2, UInt<1>(0h0))
node _valids_4_T_4 = and(valids[4], _valids_4_T_3)
node _valids_4_T_5 = and(io.flush, UInt<1>(0h1))
node _valids_4_T_6 = eq(_valids_4_T_5, UInt<1>(0h0))
node _valids_4_T_7 = and(_valids_4_T_4, _valids_4_T_6)
connect valids[4], _valids_4_T_7
when valids[4] :
node _uops_4_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_4_br_mask_T_1 = and(uops[4].br_mask, _uops_4_br_mask_T)
connect uops[4].br_mask, _uops_4_br_mask_T_1
node _valids_5_T = and(io.brupdate.b1.mispredict_mask, uops[5].br_mask)
node _valids_5_T_1 = neq(_valids_5_T, UInt<1>(0h0))
node _valids_5_T_2 = or(_valids_5_T_1, UInt<1>(0h0))
node _valids_5_T_3 = eq(_valids_5_T_2, UInt<1>(0h0))
node _valids_5_T_4 = and(valids[5], _valids_5_T_3)
node _valids_5_T_5 = and(io.flush, UInt<1>(0h1))
node _valids_5_T_6 = eq(_valids_5_T_5, UInt<1>(0h0))
node _valids_5_T_7 = and(_valids_5_T_4, _valids_5_T_6)
connect valids[5], _valids_5_T_7
when valids[5] :
node _uops_5_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_5_br_mask_T_1 = and(uops[5].br_mask, _uops_5_br_mask_T)
connect uops[5].br_mask, _uops_5_br_mask_T_1
node _valids_6_T = and(io.brupdate.b1.mispredict_mask, uops[6].br_mask)
node _valids_6_T_1 = neq(_valids_6_T, UInt<1>(0h0))
node _valids_6_T_2 = or(_valids_6_T_1, UInt<1>(0h0))
node _valids_6_T_3 = eq(_valids_6_T_2, UInt<1>(0h0))
node _valids_6_T_4 = and(valids[6], _valids_6_T_3)
node _valids_6_T_5 = and(io.flush, UInt<1>(0h1))
node _valids_6_T_6 = eq(_valids_6_T_5, UInt<1>(0h0))
node _valids_6_T_7 = and(_valids_6_T_4, _valids_6_T_6)
connect valids[6], _valids_6_T_7
when valids[6] :
node _uops_6_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_6_br_mask_T_1 = and(uops[6].br_mask, _uops_6_br_mask_T)
connect uops[6].br_mask, _uops_6_br_mask_T_1
node _valids_7_T = and(io.brupdate.b1.mispredict_mask, uops[7].br_mask)
node _valids_7_T_1 = neq(_valids_7_T, UInt<1>(0h0))
node _valids_7_T_2 = or(_valids_7_T_1, UInt<1>(0h0))
node _valids_7_T_3 = eq(_valids_7_T_2, UInt<1>(0h0))
node _valids_7_T_4 = and(valids[7], _valids_7_T_3)
node _valids_7_T_5 = and(io.flush, UInt<1>(0h1))
node _valids_7_T_6 = eq(_valids_7_T_5, UInt<1>(0h0))
node _valids_7_T_7 = and(_valids_7_T_4, _valids_7_T_6)
connect valids[7], _valids_7_T_7
when valids[7] :
node _uops_7_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_7_br_mask_T_1 = and(uops[7].br_mask, _uops_7_br_mask_T)
connect uops[7].br_mask, _uops_7_br_mask_T_1
when do_enq :
infer mport MPORT = ram[enq_ptr_value], clock
connect MPORT, io.enq.bits
connect valids[enq_ptr_value], UInt<1>(0h1)
connect uops[enq_ptr_value], io.enq.bits.uop
node _uops_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_br_mask_T_1 = and(io.enq.bits.uop.br_mask, _uops_br_mask_T)
connect uops[enq_ptr_value].br_mask, _uops_br_mask_T_1
node wrap = eq(enq_ptr_value, UInt<3>(0h7))
node _value_T = add(enq_ptr_value, UInt<1>(0h1))
node _value_T_1 = tail(_value_T, 1)
connect enq_ptr_value, _value_T_1
when do_deq :
connect valids[deq_ptr_value], UInt<1>(0h0)
node wrap_1 = eq(deq_ptr_value, UInt<3>(0h7))
node _value_T_2 = add(deq_ptr_value, UInt<1>(0h1))
node _value_T_3 = tail(_value_T_2, 1)
connect deq_ptr_value, _value_T_3
node _T = neq(do_enq, do_deq)
when _T :
connect maybe_full, do_enq
node _io_enq_ready_T = eq(full, UInt<1>(0h0))
connect io.enq.ready, _io_enq_ready_T
wire out : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>}
infer mport out_MPORT = ram[deq_ptr_value], clock
connect out, out_MPORT
connect out.uop, uops[deq_ptr_value]
node _io_deq_valid_T = eq(io.empty, UInt<1>(0h0))
node _io_deq_valid_T_1 = and(_io_deq_valid_T, valids[deq_ptr_value])
connect io.deq.valid, _io_deq_valid_T_1
connect io.deq.bits, out
node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value)
node ptr_diff = tail(_ptr_diff_T, 1)
node _io_count_T = and(maybe_full, ptr_match)
node _io_count_T_1 = cat(_io_count_T, ptr_diff)
connect io.count, _io_count_T_1 | module BranchKillableQueue_17( // @[util.scala:458:7]
input clock, // @[util.scala:458:7]
input reset, // @[util.scala:458:7]
output io_enq_ready, // @[util.scala:463:14]
input io_enq_valid, // @[util.scala:463:14]
input [31:0] io_enq_bits_uop_inst, // @[util.scala:463:14]
input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:463:14]
input io_enq_bits_uop_is_rvc, // @[util.scala:463:14]
input [33:0] io_enq_bits_uop_debug_pc, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_0, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_1, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_2, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_3, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_0, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_1, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_2, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_3, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_4, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_5, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_6, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_7, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_8, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_9, // @[util.scala:463:14]
input io_enq_bits_uop_iw_issued, // @[util.scala:463:14]
input io_enq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14]
input io_enq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14]
input io_enq_bits_uop_dis_col_sel, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_br_mask, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_br_tag, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_br_type, // @[util.scala:463:14]
input io_enq_bits_uop_is_sfb, // @[util.scala:463:14]
input io_enq_bits_uop_is_fence, // @[util.scala:463:14]
input io_enq_bits_uop_is_fencei, // @[util.scala:463:14]
input io_enq_bits_uop_is_sfence, // @[util.scala:463:14]
input io_enq_bits_uop_is_amo, // @[util.scala:463:14]
input io_enq_bits_uop_is_eret, // @[util.scala:463:14]
input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14]
input io_enq_bits_uop_is_rocc, // @[util.scala:463:14]
input io_enq_bits_uop_is_mov, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_ftq_idx, // @[util.scala:463:14]
input io_enq_bits_uop_edge_inst, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:463:14]
input io_enq_bits_uop_taken, // @[util.scala:463:14]
input io_enq_bits_uop_imm_rename, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_imm_sel, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_pimm, // @[util.scala:463:14]
input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_op1_sel, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_op2_sel, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_div, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_rob_idx, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_ldq_idx, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_stq_idx, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_pdst, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_prs1, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_prs2, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_prs3, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_ppred, // @[util.scala:463:14]
input io_enq_bits_uop_prs1_busy, // @[util.scala:463:14]
input io_enq_bits_uop_prs2_busy, // @[util.scala:463:14]
input io_enq_bits_uop_prs3_busy, // @[util.scala:463:14]
input io_enq_bits_uop_ppred_busy, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_stale_pdst, // @[util.scala:463:14]
input io_enq_bits_uop_exception, // @[util.scala:463:14]
input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:463:14]
input io_enq_bits_uop_mem_signed, // @[util.scala:463:14]
input io_enq_bits_uop_uses_ldq, // @[util.scala:463:14]
input io_enq_bits_uop_uses_stq, // @[util.scala:463:14]
input io_enq_bits_uop_is_unique, // @[util.scala:463:14]
input io_enq_bits_uop_flush_on_commit, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_csr_cmd, // @[util.scala:463:14]
input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_ldst, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:463:14]
input io_enq_bits_uop_frs3_en, // @[util.scala:463:14]
input io_enq_bits_uop_fcn_dw, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_fcn_op, // @[util.scala:463:14]
input io_enq_bits_uop_fp_val, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_fp_rm, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_fp_typ, // @[util.scala:463:14]
input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:463:14]
input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:463:14]
input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:463:14]
input io_enq_bits_uop_bp_debug_if, // @[util.scala:463:14]
input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:463:14]
input [63:0] io_enq_bits_data, // @[util.scala:463:14]
input io_deq_ready, // @[util.scala:463:14]
output io_deq_valid, // @[util.scala:463:14]
output [31:0] io_deq_bits_uop_inst, // @[util.scala:463:14]
output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:463:14]
output io_deq_bits_uop_is_rvc, // @[util.scala:463:14]
output [33:0] io_deq_bits_uop_debug_pc, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_0, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_1, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_2, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_3, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_0, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_1, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_2, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_3, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_4, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_5, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_6, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_7, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_8, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_9, // @[util.scala:463:14]
output io_deq_bits_uop_iw_issued, // @[util.scala:463:14]
output io_deq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14]
output io_deq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14]
output io_deq_bits_uop_dis_col_sel, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_br_mask, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_br_tag, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_br_type, // @[util.scala:463:14]
output io_deq_bits_uop_is_sfb, // @[util.scala:463:14]
output io_deq_bits_uop_is_fence, // @[util.scala:463:14]
output io_deq_bits_uop_is_fencei, // @[util.scala:463:14]
output io_deq_bits_uop_is_sfence, // @[util.scala:463:14]
output io_deq_bits_uop_is_amo, // @[util.scala:463:14]
output io_deq_bits_uop_is_eret, // @[util.scala:463:14]
output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14]
output io_deq_bits_uop_is_rocc, // @[util.scala:463:14]
output io_deq_bits_uop_is_mov, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_ftq_idx, // @[util.scala:463:14]
output io_deq_bits_uop_edge_inst, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:463:14]
output io_deq_bits_uop_taken, // @[util.scala:463:14]
output io_deq_bits_uop_imm_rename, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_imm_sel, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_pimm, // @[util.scala:463:14]
output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_op1_sel, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_op2_sel, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_div, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_rob_idx, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_ldq_idx, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_stq_idx, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_pdst, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_prs1, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_prs2, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_prs3, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_ppred, // @[util.scala:463:14]
output io_deq_bits_uop_prs1_busy, // @[util.scala:463:14]
output io_deq_bits_uop_prs2_busy, // @[util.scala:463:14]
output io_deq_bits_uop_prs3_busy, // @[util.scala:463:14]
output io_deq_bits_uop_ppred_busy, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_stale_pdst, // @[util.scala:463:14]
output io_deq_bits_uop_exception, // @[util.scala:463:14]
output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:463:14]
output io_deq_bits_uop_mem_signed, // @[util.scala:463:14]
output io_deq_bits_uop_uses_ldq, // @[util.scala:463:14]
output io_deq_bits_uop_uses_stq, // @[util.scala:463:14]
output io_deq_bits_uop_is_unique, // @[util.scala:463:14]
output io_deq_bits_uop_flush_on_commit, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_csr_cmd, // @[util.scala:463:14]
output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_ldst, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:463:14]
output io_deq_bits_uop_frs3_en, // @[util.scala:463:14]
output io_deq_bits_uop_fcn_dw, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_fcn_op, // @[util.scala:463:14]
output io_deq_bits_uop_fp_val, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_fp_rm, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_fp_typ, // @[util.scala:463:14]
output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:463:14]
output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:463:14]
output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:463:14]
output io_deq_bits_uop_bp_debug_if, // @[util.scala:463:14]
output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:463:14]
output [63:0] io_deq_bits_data // @[util.scala:463:14]
);
wire io_enq_valid_0 = io_enq_valid; // @[util.scala:458:7]
wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:458:7]
wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:458:7]
wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:458:7]
wire [33:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_0_0 = io_enq_bits_uop_iq_type_0; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_1_0 = io_enq_bits_uop_iq_type_1; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_2_0 = io_enq_bits_uop_iq_type_2; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_3_0 = io_enq_bits_uop_iq_type_3; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_0_0 = io_enq_bits_uop_fu_code_0; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_1_0 = io_enq_bits_uop_fu_code_1; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_2_0 = io_enq_bits_uop_fu_code_2; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_3_0 = io_enq_bits_uop_fu_code_3; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_4_0 = io_enq_bits_uop_fu_code_4; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_5_0 = io_enq_bits_uop_fu_code_5; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_6_0 = io_enq_bits_uop_fu_code_6; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_7_0 = io_enq_bits_uop_fu_code_7; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_8_0 = io_enq_bits_uop_fu_code_8; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_9_0 = io_enq_bits_uop_fu_code_9; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_issued_0 = io_enq_bits_uop_iw_issued; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_issued_partial_agen_0 = io_enq_bits_uop_iw_issued_partial_agen; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_issued_partial_dgen_0 = io_enq_bits_uop_iw_issued_partial_dgen; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p1_speculative_child_0 = io_enq_bits_uop_iw_p1_speculative_child; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p2_speculative_child_0 = io_enq_bits_uop_iw_p2_speculative_child; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p1_bypass_hint_0 = io_enq_bits_uop_iw_p1_bypass_hint; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p2_bypass_hint_0 = io_enq_bits_uop_iw_p2_bypass_hint; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p3_bypass_hint_0 = io_enq_bits_uop_iw_p3_bypass_hint; // @[util.scala:458:7]
wire io_enq_bits_uop_dis_col_sel_0 = io_enq_bits_uop_dis_col_sel; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_br_type_0 = io_enq_bits_uop_br_type; // @[util.scala:458:7]
wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:458:7]
wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:458:7]
wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:458:7]
wire io_enq_bits_uop_is_sfence_0 = io_enq_bits_uop_is_sfence; // @[util.scala:458:7]
wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:458:7]
wire io_enq_bits_uop_is_eret_0 = io_enq_bits_uop_is_eret; // @[util.scala:458:7]
wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:458:7]
wire io_enq_bits_uop_is_rocc_0 = io_enq_bits_uop_is_rocc; // @[util.scala:458:7]
wire io_enq_bits_uop_is_mov_0 = io_enq_bits_uop_is_mov; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:458:7]
wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:458:7]
wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:458:7]
wire io_enq_bits_uop_imm_rename_0 = io_enq_bits_uop_imm_rename; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_imm_sel_0 = io_enq_bits_uop_imm_sel; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_pimm_0 = io_enq_bits_uop_pimm; // @[util.scala:458:7]
wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_op1_sel_0 = io_enq_bits_uop_op1_sel; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_op2_sel_0 = io_enq_bits_uop_op2_sel; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ldst_0 = io_enq_bits_uop_fp_ctrl_ldst; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_wen_0 = io_enq_bits_uop_fp_ctrl_wen; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ren1_0 = io_enq_bits_uop_fp_ctrl_ren1; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ren2_0 = io_enq_bits_uop_fp_ctrl_ren2; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ren3_0 = io_enq_bits_uop_fp_ctrl_ren3; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_swap12_0 = io_enq_bits_uop_fp_ctrl_swap12; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_swap23_0 = io_enq_bits_uop_fp_ctrl_swap23; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn_0 = io_enq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut_0 = io_enq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_fromint_0 = io_enq_bits_uop_fp_ctrl_fromint; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_toint_0 = io_enq_bits_uop_fp_ctrl_toint; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_fastpipe_0 = io_enq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_fma_0 = io_enq_bits_uop_fp_ctrl_fma; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_div_0 = io_enq_bits_uop_fp_ctrl_div; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_sqrt_0 = io_enq_bits_uop_fp_ctrl_sqrt; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_wflags_0 = io_enq_bits_uop_fp_ctrl_wflags; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_vec_0 = io_enq_bits_uop_fp_ctrl_vec; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:458:7]
wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:458:7]
wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:458:7]
wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:458:7]
wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:458:7]
wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:458:7]
wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:458:7]
wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:458:7]
wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:458:7]
wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:458:7]
wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:458:7]
wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_csr_cmd_0 = io_enq_bits_uop_csr_cmd; // @[util.scala:458:7]
wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:458:7]
wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:458:7]
wire io_enq_bits_uop_fcn_dw_0 = io_enq_bits_uop_fcn_dw; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_fcn_op_0 = io_enq_bits_uop_fcn_op; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_fp_rm_0 = io_enq_bits_uop_fp_rm; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_fp_typ_0 = io_enq_bits_uop_fp_typ; // @[util.scala:458:7]
wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:458:7]
wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:458:7]
wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:458:7]
wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:458:7]
wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:458:7]
wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:458:7]
wire io_deq_ready_0 = io_deq_ready; // @[util.scala:458:7]
wire _do_enq_T_4 = 1'h1; // @[util.scala:514:42]
wire _do_enq_T_7 = 1'h1; // @[util.scala:514:102]
wire _valids_0_T_3 = 1'h1; // @[util.scala:520:34]
wire _valids_0_T_6 = 1'h1; // @[util.scala:520:83]
wire _valids_1_T_3 = 1'h1; // @[util.scala:520:34]
wire _valids_1_T_6 = 1'h1; // @[util.scala:520:83]
wire _valids_2_T_3 = 1'h1; // @[util.scala:520:34]
wire _valids_2_T_6 = 1'h1; // @[util.scala:520:83]
wire _valids_3_T_3 = 1'h1; // @[util.scala:520:34]
wire _valids_3_T_6 = 1'h1; // @[util.scala:520:83]
wire _valids_4_T_3 = 1'h1; // @[util.scala:520:34]
wire _valids_4_T_6 = 1'h1; // @[util.scala:520:83]
wire _valids_5_T_3 = 1'h1; // @[util.scala:520:34]
wire _valids_5_T_6 = 1'h1; // @[util.scala:520:83]
wire _valids_6_T_3 = 1'h1; // @[util.scala:520:34]
wire _valids_6_T_6 = 1'h1; // @[util.scala:520:83]
wire _valids_7_T_3 = 1'h1; // @[util.scala:520:34]
wire _valids_7_T_6 = 1'h1; // @[util.scala:520:83]
wire [3:0] _uops_0_br_mask_T = 4'hF; // @[util.scala:93:27, :97:23]
wire [3:0] _uops_1_br_mask_T = 4'hF; // @[util.scala:93:27, :97:23]
wire [3:0] _uops_2_br_mask_T = 4'hF; // @[util.scala:93:27, :97:23]
wire [3:0] _uops_3_br_mask_T = 4'hF; // @[util.scala:93:27, :97:23]
wire [3:0] _uops_4_br_mask_T = 4'hF; // @[util.scala:93:27, :97:23]
wire [3:0] _uops_5_br_mask_T = 4'hF; // @[util.scala:93:27, :97:23]
wire [3:0] _uops_6_br_mask_T = 4'hF; // @[util.scala:93:27, :97:23]
wire [3:0] _uops_7_br_mask_T = 4'hF; // @[util.scala:93:27, :97:23]
wire [3:0] _uops_br_mask_T = 4'hF; // @[util.scala:93:27, :97:23]
wire [20:0] io_brupdate_b2_target_offset = 21'h0; // @[util.scala:458:7, :463:14]
wire [63:0] io_brupdate_b2_uop_exc_cause = 64'h0; // @[util.scala:458:7, :463:14]
wire [19:0] io_brupdate_b2_uop_imm_packed = 20'h0; // @[util.scala:458:7, :463:14]
wire [4:0] io_brupdate_b2_uop_pimm = 5'h0; // @[util.scala:458:7, :463:14]
wire [4:0] io_brupdate_b2_uop_rob_idx = 5'h0; // @[util.scala:458:7, :463:14]
wire [4:0] io_brupdate_b2_uop_mem_cmd = 5'h0; // @[util.scala:458:7, :463:14]
wire [4:0] io_brupdate_b2_uop_fcn_op = 5'h0; // @[util.scala:458:7, :463:14]
wire [2:0] io_brupdate_b2_uop_imm_sel = 3'h0; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_op2_sel = 3'h0; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_csr_cmd = 3'h0; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_fp_rm = 3'h0; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_debug_fsrc = 3'h0; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_debug_tsrc = 3'h0; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_cfi_type = 3'h0; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_pc_lob = 6'h0; // @[util.scala:458:7, :463:14]
wire [5:0] io_brupdate_b2_uop_pdst = 6'h0; // @[util.scala:458:7, :463:14]
wire [5:0] io_brupdate_b2_uop_prs1 = 6'h0; // @[util.scala:458:7, :463:14]
wire [5:0] io_brupdate_b2_uop_prs2 = 6'h0; // @[util.scala:458:7, :463:14]
wire [5:0] io_brupdate_b2_uop_prs3 = 6'h0; // @[util.scala:458:7, :463:14]
wire [5:0] io_brupdate_b2_uop_stale_pdst = 6'h0; // @[util.scala:458:7, :463:14]
wire [5:0] io_brupdate_b2_uop_ldst = 6'h0; // @[util.scala:458:7, :463:14]
wire [5:0] io_brupdate_b2_uop_lrs1 = 6'h0; // @[util.scala:458:7, :463:14]
wire [5:0] io_brupdate_b2_uop_lrs2 = 6'h0; // @[util.scala:458:7, :463:14]
wire [5:0] io_brupdate_b2_uop_lrs3 = 6'h0; // @[util.scala:458:7, :463:14]
wire [1:0] io_brupdate_b2_uop_br_tag = 2'h0; // @[util.scala:458:7, :463:14]
wire [1:0] io_brupdate_b2_uop_op1_sel = 2'h0; // @[util.scala:458:7, :463:14]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn = 2'h0; // @[util.scala:458:7, :463:14]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut = 2'h0; // @[util.scala:458:7, :463:14]
wire [1:0] io_brupdate_b2_uop_rxq_idx = 2'h0; // @[util.scala:458:7, :463:14]
wire [1:0] io_brupdate_b2_uop_mem_size = 2'h0; // @[util.scala:458:7, :463:14]
wire [1:0] io_brupdate_b2_uop_dst_rtype = 2'h0; // @[util.scala:458:7, :463:14]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[util.scala:458:7, :463:14]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[util.scala:458:7, :463:14]
wire [1:0] io_brupdate_b2_uop_fp_typ = 2'h0; // @[util.scala:458:7, :463:14]
wire [1:0] io_brupdate_b2_pc_sel = 2'h0; // @[util.scala:458:7, :463:14]
wire [33:0] io_brupdate_b2_uop_debug_pc = 34'h0; // @[util.scala:458:7, :463:14]
wire [33:0] io_brupdate_b2_jalr_target = 34'h0; // @[util.scala:458:7, :463:14]
wire io_brupdate_b2_uop_is_rvc = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_0 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_1 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_2 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_3 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_0 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_1 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_2 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_3 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_4 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_5 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_6 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_7 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_8 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_9 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_issued = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p1_speculative_child = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p2_speculative_child = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_dis_col_sel = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_sfb = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_fence = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_fencei = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_sfence = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_amo = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_eret = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_rocc = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_mov = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_edge_inst = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_taken = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_imm_rename = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_wen = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_toint = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_fma = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_div = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_vec = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_prs1_busy = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_prs2_busy = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_prs3_busy = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_ppred_busy = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_exception = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_mem_signed = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_uses_ldq = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_uses_stq = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_unique = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_flush_on_commit = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_frs3_en = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fcn_dw = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_val = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_bp_debug_if = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_mispredict = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_taken = 1'h0; // @[util.scala:458:7]
wire io_flush = 1'h0; // @[util.scala:458:7]
wire _valids_WIRE_0 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_1 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_2 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_3 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_4 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_5 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_6 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_7 = 1'h0; // @[util.scala:504:34]
wire _do_enq_T_2 = 1'h0; // @[util.scala:126:59]
wire _do_enq_T_3 = 1'h0; // @[util.scala:61:61]
wire _do_enq_T_6 = 1'h0; // @[util.scala:514:113]
wire _valids_0_T_1 = 1'h0; // @[util.scala:126:59]
wire _valids_0_T_2 = 1'h0; // @[util.scala:61:61]
wire _valids_0_T_5 = 1'h0; // @[util.scala:520:94]
wire _valids_1_T_1 = 1'h0; // @[util.scala:126:59]
wire _valids_1_T_2 = 1'h0; // @[util.scala:61:61]
wire _valids_1_T_5 = 1'h0; // @[util.scala:520:94]
wire _valids_2_T_1 = 1'h0; // @[util.scala:126:59]
wire _valids_2_T_2 = 1'h0; // @[util.scala:61:61]
wire _valids_2_T_5 = 1'h0; // @[util.scala:520:94]
wire _valids_3_T_1 = 1'h0; // @[util.scala:126:59]
wire _valids_3_T_2 = 1'h0; // @[util.scala:61:61]
wire _valids_3_T_5 = 1'h0; // @[util.scala:520:94]
wire _valids_4_T_1 = 1'h0; // @[util.scala:126:59]
wire _valids_4_T_2 = 1'h0; // @[util.scala:61:61]
wire _valids_4_T_5 = 1'h0; // @[util.scala:520:94]
wire _valids_5_T_1 = 1'h0; // @[util.scala:126:59]
wire _valids_5_T_2 = 1'h0; // @[util.scala:61:61]
wire _valids_5_T_5 = 1'h0; // @[util.scala:520:94]
wire _valids_6_T_1 = 1'h0; // @[util.scala:126:59]
wire _valids_6_T_2 = 1'h0; // @[util.scala:61:61]
wire _valids_6_T_5 = 1'h0; // @[util.scala:520:94]
wire _valids_7_T_1 = 1'h0; // @[util.scala:126:59]
wire _valids_7_T_2 = 1'h0; // @[util.scala:61:61]
wire _valids_7_T_5 = 1'h0; // @[util.scala:520:94]
wire [31:0] io_brupdate_b2_uop_inst = 32'h0; // @[util.scala:458:7, :463:14]
wire [31:0] io_brupdate_b2_uop_debug_inst = 32'h0; // @[util.scala:458:7, :463:14]
wire [3:0] io_brupdate_b1_resolve_mask = 4'h0; // @[util.scala:126:51, :458:7, :463:14]
wire [3:0] io_brupdate_b1_mispredict_mask = 4'h0; // @[util.scala:126:51, :458:7, :463:14]
wire [3:0] io_brupdate_b2_uop_br_mask = 4'h0; // @[util.scala:126:51, :458:7, :463:14]
wire [3:0] io_brupdate_b2_uop_br_type = 4'h0; // @[util.scala:126:51, :458:7, :463:14]
wire [3:0] io_brupdate_b2_uop_ftq_idx = 4'h0; // @[util.scala:126:51, :458:7, :463:14]
wire [3:0] io_brupdate_b2_uop_ldq_idx = 4'h0; // @[util.scala:126:51, :458:7, :463:14]
wire [3:0] io_brupdate_b2_uop_stq_idx = 4'h0; // @[util.scala:126:51, :458:7, :463:14]
wire [3:0] io_brupdate_b2_uop_ppred = 4'h0; // @[util.scala:126:51, :458:7, :463:14]
wire [3:0] _do_enq_T_1 = 4'h0; // @[util.scala:126:51, :458:7, :463:14]
wire [3:0] _valids_0_T = 4'h0; // @[util.scala:126:51, :458:7, :463:14]
wire [3:0] _valids_1_T = 4'h0; // @[util.scala:126:51, :458:7, :463:14]
wire [3:0] _valids_2_T = 4'h0; // @[util.scala:126:51, :458:7, :463:14]
wire [3:0] _valids_3_T = 4'h0; // @[util.scala:126:51, :458:7, :463:14]
wire [3:0] _valids_4_T = 4'h0; // @[util.scala:126:51, :458:7, :463:14]
wire [3:0] _valids_5_T = 4'h0; // @[util.scala:126:51, :458:7, :463:14]
wire [3:0] _valids_6_T = 4'h0; // @[util.scala:126:51, :458:7, :463:14]
wire [3:0] _valids_7_T = 4'h0; // @[util.scala:126:51, :458:7, :463:14]
wire _io_enq_ready_T; // @[util.scala:543:21]
wire [3:0] _uops_br_mask_T_1 = io_enq_bits_uop_br_mask_0; // @[util.scala:93:25, :458:7]
wire _io_deq_valid_T_1; // @[util.scala:548:42]
wire [31:0] out_uop_inst; // @[util.scala:545:19]
wire [31:0] out_uop_debug_inst; // @[util.scala:545:19]
wire out_uop_is_rvc; // @[util.scala:545:19]
wire [33:0] out_uop_debug_pc; // @[util.scala:545:19]
wire out_uop_iq_type_0; // @[util.scala:545:19]
wire out_uop_iq_type_1; // @[util.scala:545:19]
wire out_uop_iq_type_2; // @[util.scala:545:19]
wire out_uop_iq_type_3; // @[util.scala:545:19]
wire out_uop_fu_code_0; // @[util.scala:545:19]
wire out_uop_fu_code_1; // @[util.scala:545:19]
wire out_uop_fu_code_2; // @[util.scala:545:19]
wire out_uop_fu_code_3; // @[util.scala:545:19]
wire out_uop_fu_code_4; // @[util.scala:545:19]
wire out_uop_fu_code_5; // @[util.scala:545:19]
wire out_uop_fu_code_6; // @[util.scala:545:19]
wire out_uop_fu_code_7; // @[util.scala:545:19]
wire out_uop_fu_code_8; // @[util.scala:545:19]
wire out_uop_fu_code_9; // @[util.scala:545:19]
wire out_uop_iw_issued; // @[util.scala:545:19]
wire out_uop_iw_issued_partial_agen; // @[util.scala:545:19]
wire out_uop_iw_issued_partial_dgen; // @[util.scala:545:19]
wire out_uop_iw_p1_speculative_child; // @[util.scala:545:19]
wire out_uop_iw_p2_speculative_child; // @[util.scala:545:19]
wire out_uop_iw_p1_bypass_hint; // @[util.scala:545:19]
wire out_uop_iw_p2_bypass_hint; // @[util.scala:545:19]
wire out_uop_iw_p3_bypass_hint; // @[util.scala:545:19]
wire out_uop_dis_col_sel; // @[util.scala:545:19]
wire [3:0] out_uop_br_mask; // @[util.scala:545:19]
wire [1:0] out_uop_br_tag; // @[util.scala:545:19]
wire [3:0] out_uop_br_type; // @[util.scala:545:19]
wire out_uop_is_sfb; // @[util.scala:545:19]
wire out_uop_is_fence; // @[util.scala:545:19]
wire out_uop_is_fencei; // @[util.scala:545:19]
wire out_uop_is_sfence; // @[util.scala:545:19]
wire out_uop_is_amo; // @[util.scala:545:19]
wire out_uop_is_eret; // @[util.scala:545:19]
wire out_uop_is_sys_pc2epc; // @[util.scala:545:19]
wire out_uop_is_rocc; // @[util.scala:545:19]
wire out_uop_is_mov; // @[util.scala:545:19]
wire [3:0] out_uop_ftq_idx; // @[util.scala:545:19]
wire out_uop_edge_inst; // @[util.scala:545:19]
wire [5:0] out_uop_pc_lob; // @[util.scala:545:19]
wire out_uop_taken; // @[util.scala:545:19]
wire out_uop_imm_rename; // @[util.scala:545:19]
wire [2:0] out_uop_imm_sel; // @[util.scala:545:19]
wire [4:0] out_uop_pimm; // @[util.scala:545:19]
wire [19:0] out_uop_imm_packed; // @[util.scala:545:19]
wire [1:0] out_uop_op1_sel; // @[util.scala:545:19]
wire [2:0] out_uop_op2_sel; // @[util.scala:545:19]
wire out_uop_fp_ctrl_ldst; // @[util.scala:545:19]
wire out_uop_fp_ctrl_wen; // @[util.scala:545:19]
wire out_uop_fp_ctrl_ren1; // @[util.scala:545:19]
wire out_uop_fp_ctrl_ren2; // @[util.scala:545:19]
wire out_uop_fp_ctrl_ren3; // @[util.scala:545:19]
wire out_uop_fp_ctrl_swap12; // @[util.scala:545:19]
wire out_uop_fp_ctrl_swap23; // @[util.scala:545:19]
wire [1:0] out_uop_fp_ctrl_typeTagIn; // @[util.scala:545:19]
wire [1:0] out_uop_fp_ctrl_typeTagOut; // @[util.scala:545:19]
wire out_uop_fp_ctrl_fromint; // @[util.scala:545:19]
wire out_uop_fp_ctrl_toint; // @[util.scala:545:19]
wire out_uop_fp_ctrl_fastpipe; // @[util.scala:545:19]
wire out_uop_fp_ctrl_fma; // @[util.scala:545:19]
wire out_uop_fp_ctrl_div; // @[util.scala:545:19]
wire out_uop_fp_ctrl_sqrt; // @[util.scala:545:19]
wire out_uop_fp_ctrl_wflags; // @[util.scala:545:19]
wire out_uop_fp_ctrl_vec; // @[util.scala:545:19]
wire [4:0] out_uop_rob_idx; // @[util.scala:545:19]
wire [3:0] out_uop_ldq_idx; // @[util.scala:545:19]
wire [3:0] out_uop_stq_idx; // @[util.scala:545:19]
wire [1:0] out_uop_rxq_idx; // @[util.scala:545:19]
wire [5:0] out_uop_pdst; // @[util.scala:545:19]
wire [5:0] out_uop_prs1; // @[util.scala:545:19]
wire [5:0] out_uop_prs2; // @[util.scala:545:19]
wire [5:0] out_uop_prs3; // @[util.scala:545:19]
wire [3:0] out_uop_ppred; // @[util.scala:545:19]
wire out_uop_prs1_busy; // @[util.scala:545:19]
wire out_uop_prs2_busy; // @[util.scala:545:19]
wire out_uop_prs3_busy; // @[util.scala:545:19]
wire out_uop_ppred_busy; // @[util.scala:545:19]
wire [5:0] out_uop_stale_pdst; // @[util.scala:545:19]
wire out_uop_exception; // @[util.scala:545:19]
wire [63:0] out_uop_exc_cause; // @[util.scala:545:19]
wire [4:0] out_uop_mem_cmd; // @[util.scala:545:19]
wire [1:0] out_uop_mem_size; // @[util.scala:545:19]
wire out_uop_mem_signed; // @[util.scala:545:19]
wire out_uop_uses_ldq; // @[util.scala:545:19]
wire out_uop_uses_stq; // @[util.scala:545:19]
wire out_uop_is_unique; // @[util.scala:545:19]
wire out_uop_flush_on_commit; // @[util.scala:545:19]
wire [2:0] out_uop_csr_cmd; // @[util.scala:545:19]
wire out_uop_ldst_is_rs1; // @[util.scala:545:19]
wire [5:0] out_uop_ldst; // @[util.scala:545:19]
wire [5:0] out_uop_lrs1; // @[util.scala:545:19]
wire [5:0] out_uop_lrs2; // @[util.scala:545:19]
wire [5:0] out_uop_lrs3; // @[util.scala:545:19]
wire [1:0] out_uop_dst_rtype; // @[util.scala:545:19]
wire [1:0] out_uop_lrs1_rtype; // @[util.scala:545:19]
wire [1:0] out_uop_lrs2_rtype; // @[util.scala:545:19]
wire out_uop_frs3_en; // @[util.scala:545:19]
wire out_uop_fcn_dw; // @[util.scala:545:19]
wire [4:0] out_uop_fcn_op; // @[util.scala:545:19]
wire out_uop_fp_val; // @[util.scala:545:19]
wire [2:0] out_uop_fp_rm; // @[util.scala:545:19]
wire [1:0] out_uop_fp_typ; // @[util.scala:545:19]
wire out_uop_xcpt_pf_if; // @[util.scala:545:19]
wire out_uop_xcpt_ae_if; // @[util.scala:545:19]
wire out_uop_xcpt_ma_if; // @[util.scala:545:19]
wire out_uop_bp_debug_if; // @[util.scala:545:19]
wire out_uop_bp_xcpt_if; // @[util.scala:545:19]
wire [2:0] out_uop_debug_fsrc; // @[util.scala:545:19]
wire [2:0] out_uop_debug_tsrc; // @[util.scala:545:19]
wire [63:0] out_data; // @[util.scala:545:19]
wire _io_empty_T_1; // @[util.scala:512:27]
wire io_enq_ready_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7]
wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:458:7]
wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7]
wire [33:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_br_mask_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_br_tag_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_br_type_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_fence_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_amo_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_eret_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_mov_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7]
wire io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7]
wire io_deq_bits_uop_taken_0; // @[util.scala:458:7]
wire io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_pimm_0; // @[util.scala:458:7]
wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_pdst_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_prs1_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_prs2_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_prs3_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_ppred_0; // @[util.scala:458:7]
wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7]
wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7]
wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7]
wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7]
wire io_deq_bits_uop_exception_0; // @[util.scala:458:7]
wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:458:7]
wire io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7]
wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7]
wire io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_unique_0; // @[util.scala:458:7]
wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7]
wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7]
wire io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_val_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7]
wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7]
wire [63:0] io_deq_bits_data_0; // @[util.scala:458:7]
wire io_deq_valid_0; // @[util.scala:458:7]
wire io_empty; // @[util.scala:458:7]
wire [2:0] io_count; // @[util.scala:458:7]
reg valids_0; // @[util.scala:504:26]
wire _valids_0_T_4 = valids_0; // @[util.scala:504:26, :520:31]
reg valids_1; // @[util.scala:504:26]
wire _valids_1_T_4 = valids_1; // @[util.scala:504:26, :520:31]
reg valids_2; // @[util.scala:504:26]
wire _valids_2_T_4 = valids_2; // @[util.scala:504:26, :520:31]
reg valids_3; // @[util.scala:504:26]
wire _valids_3_T_4 = valids_3; // @[util.scala:504:26, :520:31]
reg valids_4; // @[util.scala:504:26]
wire _valids_4_T_4 = valids_4; // @[util.scala:504:26, :520:31]
reg valids_5; // @[util.scala:504:26]
wire _valids_5_T_4 = valids_5; // @[util.scala:504:26, :520:31]
reg valids_6; // @[util.scala:504:26]
wire _valids_6_T_4 = valids_6; // @[util.scala:504:26, :520:31]
reg valids_7; // @[util.scala:504:26]
wire _valids_7_T_4 = valids_7; // @[util.scala:504:26, :520:31]
reg [31:0] uops_0_inst; // @[util.scala:505:22]
reg [31:0] uops_0_debug_inst; // @[util.scala:505:22]
reg uops_0_is_rvc; // @[util.scala:505:22]
reg [33:0] uops_0_debug_pc; // @[util.scala:505:22]
reg uops_0_iq_type_0; // @[util.scala:505:22]
reg uops_0_iq_type_1; // @[util.scala:505:22]
reg uops_0_iq_type_2; // @[util.scala:505:22]
reg uops_0_iq_type_3; // @[util.scala:505:22]
reg uops_0_fu_code_0; // @[util.scala:505:22]
reg uops_0_fu_code_1; // @[util.scala:505:22]
reg uops_0_fu_code_2; // @[util.scala:505:22]
reg uops_0_fu_code_3; // @[util.scala:505:22]
reg uops_0_fu_code_4; // @[util.scala:505:22]
reg uops_0_fu_code_5; // @[util.scala:505:22]
reg uops_0_fu_code_6; // @[util.scala:505:22]
reg uops_0_fu_code_7; // @[util.scala:505:22]
reg uops_0_fu_code_8; // @[util.scala:505:22]
reg uops_0_fu_code_9; // @[util.scala:505:22]
reg uops_0_iw_issued; // @[util.scala:505:22]
reg uops_0_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_0_iw_issued_partial_dgen; // @[util.scala:505:22]
reg uops_0_iw_p1_speculative_child; // @[util.scala:505:22]
reg uops_0_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_0_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_0_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_0_iw_p3_bypass_hint; // @[util.scala:505:22]
reg uops_0_dis_col_sel; // @[util.scala:505:22]
reg [3:0] uops_0_br_mask; // @[util.scala:505:22]
wire [3:0] _uops_0_br_mask_T_1 = uops_0_br_mask; // @[util.scala:97:21, :505:22]
reg [1:0] uops_0_br_tag; // @[util.scala:505:22]
reg [3:0] uops_0_br_type; // @[util.scala:505:22]
reg uops_0_is_sfb; // @[util.scala:505:22]
reg uops_0_is_fence; // @[util.scala:505:22]
reg uops_0_is_fencei; // @[util.scala:505:22]
reg uops_0_is_sfence; // @[util.scala:505:22]
reg uops_0_is_amo; // @[util.scala:505:22]
reg uops_0_is_eret; // @[util.scala:505:22]
reg uops_0_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_0_is_rocc; // @[util.scala:505:22]
reg uops_0_is_mov; // @[util.scala:505:22]
reg [3:0] uops_0_ftq_idx; // @[util.scala:505:22]
reg uops_0_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_0_pc_lob; // @[util.scala:505:22]
reg uops_0_taken; // @[util.scala:505:22]
reg uops_0_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_0_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_0_pimm; // @[util.scala:505:22]
reg [19:0] uops_0_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_0_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_0_op2_sel; // @[util.scala:505:22]
reg uops_0_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_0_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_0_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_0_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_0_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_0_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_0_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_0_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_0_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_0_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_0_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_0_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_0_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_0_fp_ctrl_div; // @[util.scala:505:22]
reg uops_0_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_0_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_0_fp_ctrl_vec; // @[util.scala:505:22]
reg [4:0] uops_0_rob_idx; // @[util.scala:505:22]
reg [3:0] uops_0_ldq_idx; // @[util.scala:505:22]
reg [3:0] uops_0_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_0_rxq_idx; // @[util.scala:505:22]
reg [5:0] uops_0_pdst; // @[util.scala:505:22]
reg [5:0] uops_0_prs1; // @[util.scala:505:22]
reg [5:0] uops_0_prs2; // @[util.scala:505:22]
reg [5:0] uops_0_prs3; // @[util.scala:505:22]
reg [3:0] uops_0_ppred; // @[util.scala:505:22]
reg uops_0_prs1_busy; // @[util.scala:505:22]
reg uops_0_prs2_busy; // @[util.scala:505:22]
reg uops_0_prs3_busy; // @[util.scala:505:22]
reg uops_0_ppred_busy; // @[util.scala:505:22]
reg [5:0] uops_0_stale_pdst; // @[util.scala:505:22]
reg uops_0_exception; // @[util.scala:505:22]
reg [63:0] uops_0_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_0_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_0_mem_size; // @[util.scala:505:22]
reg uops_0_mem_signed; // @[util.scala:505:22]
reg uops_0_uses_ldq; // @[util.scala:505:22]
reg uops_0_uses_stq; // @[util.scala:505:22]
reg uops_0_is_unique; // @[util.scala:505:22]
reg uops_0_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_0_csr_cmd; // @[util.scala:505:22]
reg uops_0_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_0_ldst; // @[util.scala:505:22]
reg [5:0] uops_0_lrs1; // @[util.scala:505:22]
reg [5:0] uops_0_lrs2; // @[util.scala:505:22]
reg [5:0] uops_0_lrs3; // @[util.scala:505:22]
reg [1:0] uops_0_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_0_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_0_lrs2_rtype; // @[util.scala:505:22]
reg uops_0_frs3_en; // @[util.scala:505:22]
reg uops_0_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_0_fcn_op; // @[util.scala:505:22]
reg uops_0_fp_val; // @[util.scala:505:22]
reg [2:0] uops_0_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_0_fp_typ; // @[util.scala:505:22]
reg uops_0_xcpt_pf_if; // @[util.scala:505:22]
reg uops_0_xcpt_ae_if; // @[util.scala:505:22]
reg uops_0_xcpt_ma_if; // @[util.scala:505:22]
reg uops_0_bp_debug_if; // @[util.scala:505:22]
reg uops_0_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_0_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_0_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_1_inst; // @[util.scala:505:22]
reg [31:0] uops_1_debug_inst; // @[util.scala:505:22]
reg uops_1_is_rvc; // @[util.scala:505:22]
reg [33:0] uops_1_debug_pc; // @[util.scala:505:22]
reg uops_1_iq_type_0; // @[util.scala:505:22]
reg uops_1_iq_type_1; // @[util.scala:505:22]
reg uops_1_iq_type_2; // @[util.scala:505:22]
reg uops_1_iq_type_3; // @[util.scala:505:22]
reg uops_1_fu_code_0; // @[util.scala:505:22]
reg uops_1_fu_code_1; // @[util.scala:505:22]
reg uops_1_fu_code_2; // @[util.scala:505:22]
reg uops_1_fu_code_3; // @[util.scala:505:22]
reg uops_1_fu_code_4; // @[util.scala:505:22]
reg uops_1_fu_code_5; // @[util.scala:505:22]
reg uops_1_fu_code_6; // @[util.scala:505:22]
reg uops_1_fu_code_7; // @[util.scala:505:22]
reg uops_1_fu_code_8; // @[util.scala:505:22]
reg uops_1_fu_code_9; // @[util.scala:505:22]
reg uops_1_iw_issued; // @[util.scala:505:22]
reg uops_1_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_1_iw_issued_partial_dgen; // @[util.scala:505:22]
reg uops_1_iw_p1_speculative_child; // @[util.scala:505:22]
reg uops_1_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_1_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_1_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_1_iw_p3_bypass_hint; // @[util.scala:505:22]
reg uops_1_dis_col_sel; // @[util.scala:505:22]
reg [3:0] uops_1_br_mask; // @[util.scala:505:22]
wire [3:0] _uops_1_br_mask_T_1 = uops_1_br_mask; // @[util.scala:97:21, :505:22]
reg [1:0] uops_1_br_tag; // @[util.scala:505:22]
reg [3:0] uops_1_br_type; // @[util.scala:505:22]
reg uops_1_is_sfb; // @[util.scala:505:22]
reg uops_1_is_fence; // @[util.scala:505:22]
reg uops_1_is_fencei; // @[util.scala:505:22]
reg uops_1_is_sfence; // @[util.scala:505:22]
reg uops_1_is_amo; // @[util.scala:505:22]
reg uops_1_is_eret; // @[util.scala:505:22]
reg uops_1_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_1_is_rocc; // @[util.scala:505:22]
reg uops_1_is_mov; // @[util.scala:505:22]
reg [3:0] uops_1_ftq_idx; // @[util.scala:505:22]
reg uops_1_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_1_pc_lob; // @[util.scala:505:22]
reg uops_1_taken; // @[util.scala:505:22]
reg uops_1_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_1_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_1_pimm; // @[util.scala:505:22]
reg [19:0] uops_1_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_1_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_1_op2_sel; // @[util.scala:505:22]
reg uops_1_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_1_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_1_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_1_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_1_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_1_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_1_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_1_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_1_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_1_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_1_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_1_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_1_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_1_fp_ctrl_div; // @[util.scala:505:22]
reg uops_1_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_1_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_1_fp_ctrl_vec; // @[util.scala:505:22]
reg [4:0] uops_1_rob_idx; // @[util.scala:505:22]
reg [3:0] uops_1_ldq_idx; // @[util.scala:505:22]
reg [3:0] uops_1_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_1_rxq_idx; // @[util.scala:505:22]
reg [5:0] uops_1_pdst; // @[util.scala:505:22]
reg [5:0] uops_1_prs1; // @[util.scala:505:22]
reg [5:0] uops_1_prs2; // @[util.scala:505:22]
reg [5:0] uops_1_prs3; // @[util.scala:505:22]
reg [3:0] uops_1_ppred; // @[util.scala:505:22]
reg uops_1_prs1_busy; // @[util.scala:505:22]
reg uops_1_prs2_busy; // @[util.scala:505:22]
reg uops_1_prs3_busy; // @[util.scala:505:22]
reg uops_1_ppred_busy; // @[util.scala:505:22]
reg [5:0] uops_1_stale_pdst; // @[util.scala:505:22]
reg uops_1_exception; // @[util.scala:505:22]
reg [63:0] uops_1_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_1_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_1_mem_size; // @[util.scala:505:22]
reg uops_1_mem_signed; // @[util.scala:505:22]
reg uops_1_uses_ldq; // @[util.scala:505:22]
reg uops_1_uses_stq; // @[util.scala:505:22]
reg uops_1_is_unique; // @[util.scala:505:22]
reg uops_1_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_1_csr_cmd; // @[util.scala:505:22]
reg uops_1_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_1_ldst; // @[util.scala:505:22]
reg [5:0] uops_1_lrs1; // @[util.scala:505:22]
reg [5:0] uops_1_lrs2; // @[util.scala:505:22]
reg [5:0] uops_1_lrs3; // @[util.scala:505:22]
reg [1:0] uops_1_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_1_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_1_lrs2_rtype; // @[util.scala:505:22]
reg uops_1_frs3_en; // @[util.scala:505:22]
reg uops_1_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_1_fcn_op; // @[util.scala:505:22]
reg uops_1_fp_val; // @[util.scala:505:22]
reg [2:0] uops_1_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_1_fp_typ; // @[util.scala:505:22]
reg uops_1_xcpt_pf_if; // @[util.scala:505:22]
reg uops_1_xcpt_ae_if; // @[util.scala:505:22]
reg uops_1_xcpt_ma_if; // @[util.scala:505:22]
reg uops_1_bp_debug_if; // @[util.scala:505:22]
reg uops_1_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_1_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_1_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_2_inst; // @[util.scala:505:22]
reg [31:0] uops_2_debug_inst; // @[util.scala:505:22]
reg uops_2_is_rvc; // @[util.scala:505:22]
reg [33:0] uops_2_debug_pc; // @[util.scala:505:22]
reg uops_2_iq_type_0; // @[util.scala:505:22]
reg uops_2_iq_type_1; // @[util.scala:505:22]
reg uops_2_iq_type_2; // @[util.scala:505:22]
reg uops_2_iq_type_3; // @[util.scala:505:22]
reg uops_2_fu_code_0; // @[util.scala:505:22]
reg uops_2_fu_code_1; // @[util.scala:505:22]
reg uops_2_fu_code_2; // @[util.scala:505:22]
reg uops_2_fu_code_3; // @[util.scala:505:22]
reg uops_2_fu_code_4; // @[util.scala:505:22]
reg uops_2_fu_code_5; // @[util.scala:505:22]
reg uops_2_fu_code_6; // @[util.scala:505:22]
reg uops_2_fu_code_7; // @[util.scala:505:22]
reg uops_2_fu_code_8; // @[util.scala:505:22]
reg uops_2_fu_code_9; // @[util.scala:505:22]
reg uops_2_iw_issued; // @[util.scala:505:22]
reg uops_2_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_2_iw_issued_partial_dgen; // @[util.scala:505:22]
reg uops_2_iw_p1_speculative_child; // @[util.scala:505:22]
reg uops_2_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_2_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_2_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_2_iw_p3_bypass_hint; // @[util.scala:505:22]
reg uops_2_dis_col_sel; // @[util.scala:505:22]
reg [3:0] uops_2_br_mask; // @[util.scala:505:22]
wire [3:0] _uops_2_br_mask_T_1 = uops_2_br_mask; // @[util.scala:97:21, :505:22]
reg [1:0] uops_2_br_tag; // @[util.scala:505:22]
reg [3:0] uops_2_br_type; // @[util.scala:505:22]
reg uops_2_is_sfb; // @[util.scala:505:22]
reg uops_2_is_fence; // @[util.scala:505:22]
reg uops_2_is_fencei; // @[util.scala:505:22]
reg uops_2_is_sfence; // @[util.scala:505:22]
reg uops_2_is_amo; // @[util.scala:505:22]
reg uops_2_is_eret; // @[util.scala:505:22]
reg uops_2_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_2_is_rocc; // @[util.scala:505:22]
reg uops_2_is_mov; // @[util.scala:505:22]
reg [3:0] uops_2_ftq_idx; // @[util.scala:505:22]
reg uops_2_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_2_pc_lob; // @[util.scala:505:22]
reg uops_2_taken; // @[util.scala:505:22]
reg uops_2_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_2_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_2_pimm; // @[util.scala:505:22]
reg [19:0] uops_2_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_2_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_2_op2_sel; // @[util.scala:505:22]
reg uops_2_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_2_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_2_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_2_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_2_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_2_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_2_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_2_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_2_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_2_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_2_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_2_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_2_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_2_fp_ctrl_div; // @[util.scala:505:22]
reg uops_2_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_2_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_2_fp_ctrl_vec; // @[util.scala:505:22]
reg [4:0] uops_2_rob_idx; // @[util.scala:505:22]
reg [3:0] uops_2_ldq_idx; // @[util.scala:505:22]
reg [3:0] uops_2_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_2_rxq_idx; // @[util.scala:505:22]
reg [5:0] uops_2_pdst; // @[util.scala:505:22]
reg [5:0] uops_2_prs1; // @[util.scala:505:22]
reg [5:0] uops_2_prs2; // @[util.scala:505:22]
reg [5:0] uops_2_prs3; // @[util.scala:505:22]
reg [3:0] uops_2_ppred; // @[util.scala:505:22]
reg uops_2_prs1_busy; // @[util.scala:505:22]
reg uops_2_prs2_busy; // @[util.scala:505:22]
reg uops_2_prs3_busy; // @[util.scala:505:22]
reg uops_2_ppred_busy; // @[util.scala:505:22]
reg [5:0] uops_2_stale_pdst; // @[util.scala:505:22]
reg uops_2_exception; // @[util.scala:505:22]
reg [63:0] uops_2_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_2_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_2_mem_size; // @[util.scala:505:22]
reg uops_2_mem_signed; // @[util.scala:505:22]
reg uops_2_uses_ldq; // @[util.scala:505:22]
reg uops_2_uses_stq; // @[util.scala:505:22]
reg uops_2_is_unique; // @[util.scala:505:22]
reg uops_2_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_2_csr_cmd; // @[util.scala:505:22]
reg uops_2_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_2_ldst; // @[util.scala:505:22]
reg [5:0] uops_2_lrs1; // @[util.scala:505:22]
reg [5:0] uops_2_lrs2; // @[util.scala:505:22]
reg [5:0] uops_2_lrs3; // @[util.scala:505:22]
reg [1:0] uops_2_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_2_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_2_lrs2_rtype; // @[util.scala:505:22]
reg uops_2_frs3_en; // @[util.scala:505:22]
reg uops_2_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_2_fcn_op; // @[util.scala:505:22]
reg uops_2_fp_val; // @[util.scala:505:22]
reg [2:0] uops_2_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_2_fp_typ; // @[util.scala:505:22]
reg uops_2_xcpt_pf_if; // @[util.scala:505:22]
reg uops_2_xcpt_ae_if; // @[util.scala:505:22]
reg uops_2_xcpt_ma_if; // @[util.scala:505:22]
reg uops_2_bp_debug_if; // @[util.scala:505:22]
reg uops_2_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_2_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_2_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_3_inst; // @[util.scala:505:22]
reg [31:0] uops_3_debug_inst; // @[util.scala:505:22]
reg uops_3_is_rvc; // @[util.scala:505:22]
reg [33:0] uops_3_debug_pc; // @[util.scala:505:22]
reg uops_3_iq_type_0; // @[util.scala:505:22]
reg uops_3_iq_type_1; // @[util.scala:505:22]
reg uops_3_iq_type_2; // @[util.scala:505:22]
reg uops_3_iq_type_3; // @[util.scala:505:22]
reg uops_3_fu_code_0; // @[util.scala:505:22]
reg uops_3_fu_code_1; // @[util.scala:505:22]
reg uops_3_fu_code_2; // @[util.scala:505:22]
reg uops_3_fu_code_3; // @[util.scala:505:22]
reg uops_3_fu_code_4; // @[util.scala:505:22]
reg uops_3_fu_code_5; // @[util.scala:505:22]
reg uops_3_fu_code_6; // @[util.scala:505:22]
reg uops_3_fu_code_7; // @[util.scala:505:22]
reg uops_3_fu_code_8; // @[util.scala:505:22]
reg uops_3_fu_code_9; // @[util.scala:505:22]
reg uops_3_iw_issued; // @[util.scala:505:22]
reg uops_3_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_3_iw_issued_partial_dgen; // @[util.scala:505:22]
reg uops_3_iw_p1_speculative_child; // @[util.scala:505:22]
reg uops_3_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_3_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_3_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_3_iw_p3_bypass_hint; // @[util.scala:505:22]
reg uops_3_dis_col_sel; // @[util.scala:505:22]
reg [3:0] uops_3_br_mask; // @[util.scala:505:22]
wire [3:0] _uops_3_br_mask_T_1 = uops_3_br_mask; // @[util.scala:97:21, :505:22]
reg [1:0] uops_3_br_tag; // @[util.scala:505:22]
reg [3:0] uops_3_br_type; // @[util.scala:505:22]
reg uops_3_is_sfb; // @[util.scala:505:22]
reg uops_3_is_fence; // @[util.scala:505:22]
reg uops_3_is_fencei; // @[util.scala:505:22]
reg uops_3_is_sfence; // @[util.scala:505:22]
reg uops_3_is_amo; // @[util.scala:505:22]
reg uops_3_is_eret; // @[util.scala:505:22]
reg uops_3_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_3_is_rocc; // @[util.scala:505:22]
reg uops_3_is_mov; // @[util.scala:505:22]
reg [3:0] uops_3_ftq_idx; // @[util.scala:505:22]
reg uops_3_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_3_pc_lob; // @[util.scala:505:22]
reg uops_3_taken; // @[util.scala:505:22]
reg uops_3_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_3_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_3_pimm; // @[util.scala:505:22]
reg [19:0] uops_3_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_3_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_3_op2_sel; // @[util.scala:505:22]
reg uops_3_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_3_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_3_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_3_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_3_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_3_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_3_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_3_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_3_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_3_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_3_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_3_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_3_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_3_fp_ctrl_div; // @[util.scala:505:22]
reg uops_3_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_3_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_3_fp_ctrl_vec; // @[util.scala:505:22]
reg [4:0] uops_3_rob_idx; // @[util.scala:505:22]
reg [3:0] uops_3_ldq_idx; // @[util.scala:505:22]
reg [3:0] uops_3_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_3_rxq_idx; // @[util.scala:505:22]
reg [5:0] uops_3_pdst; // @[util.scala:505:22]
reg [5:0] uops_3_prs1; // @[util.scala:505:22]
reg [5:0] uops_3_prs2; // @[util.scala:505:22]
reg [5:0] uops_3_prs3; // @[util.scala:505:22]
reg [3:0] uops_3_ppred; // @[util.scala:505:22]
reg uops_3_prs1_busy; // @[util.scala:505:22]
reg uops_3_prs2_busy; // @[util.scala:505:22]
reg uops_3_prs3_busy; // @[util.scala:505:22]
reg uops_3_ppred_busy; // @[util.scala:505:22]
reg [5:0] uops_3_stale_pdst; // @[util.scala:505:22]
reg uops_3_exception; // @[util.scala:505:22]
reg [63:0] uops_3_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_3_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_3_mem_size; // @[util.scala:505:22]
reg uops_3_mem_signed; // @[util.scala:505:22]
reg uops_3_uses_ldq; // @[util.scala:505:22]
reg uops_3_uses_stq; // @[util.scala:505:22]
reg uops_3_is_unique; // @[util.scala:505:22]
reg uops_3_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_3_csr_cmd; // @[util.scala:505:22]
reg uops_3_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_3_ldst; // @[util.scala:505:22]
reg [5:0] uops_3_lrs1; // @[util.scala:505:22]
reg [5:0] uops_3_lrs2; // @[util.scala:505:22]
reg [5:0] uops_3_lrs3; // @[util.scala:505:22]
reg [1:0] uops_3_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_3_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_3_lrs2_rtype; // @[util.scala:505:22]
reg uops_3_frs3_en; // @[util.scala:505:22]
reg uops_3_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_3_fcn_op; // @[util.scala:505:22]
reg uops_3_fp_val; // @[util.scala:505:22]
reg [2:0] uops_3_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_3_fp_typ; // @[util.scala:505:22]
reg uops_3_xcpt_pf_if; // @[util.scala:505:22]
reg uops_3_xcpt_ae_if; // @[util.scala:505:22]
reg uops_3_xcpt_ma_if; // @[util.scala:505:22]
reg uops_3_bp_debug_if; // @[util.scala:505:22]
reg uops_3_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_3_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_3_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_4_inst; // @[util.scala:505:22]
reg [31:0] uops_4_debug_inst; // @[util.scala:505:22]
reg uops_4_is_rvc; // @[util.scala:505:22]
reg [33:0] uops_4_debug_pc; // @[util.scala:505:22]
reg uops_4_iq_type_0; // @[util.scala:505:22]
reg uops_4_iq_type_1; // @[util.scala:505:22]
reg uops_4_iq_type_2; // @[util.scala:505:22]
reg uops_4_iq_type_3; // @[util.scala:505:22]
reg uops_4_fu_code_0; // @[util.scala:505:22]
reg uops_4_fu_code_1; // @[util.scala:505:22]
reg uops_4_fu_code_2; // @[util.scala:505:22]
reg uops_4_fu_code_3; // @[util.scala:505:22]
reg uops_4_fu_code_4; // @[util.scala:505:22]
reg uops_4_fu_code_5; // @[util.scala:505:22]
reg uops_4_fu_code_6; // @[util.scala:505:22]
reg uops_4_fu_code_7; // @[util.scala:505:22]
reg uops_4_fu_code_8; // @[util.scala:505:22]
reg uops_4_fu_code_9; // @[util.scala:505:22]
reg uops_4_iw_issued; // @[util.scala:505:22]
reg uops_4_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_4_iw_issued_partial_dgen; // @[util.scala:505:22]
reg uops_4_iw_p1_speculative_child; // @[util.scala:505:22]
reg uops_4_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_4_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_4_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_4_iw_p3_bypass_hint; // @[util.scala:505:22]
reg uops_4_dis_col_sel; // @[util.scala:505:22]
reg [3:0] uops_4_br_mask; // @[util.scala:505:22]
wire [3:0] _uops_4_br_mask_T_1 = uops_4_br_mask; // @[util.scala:97:21, :505:22]
reg [1:0] uops_4_br_tag; // @[util.scala:505:22]
reg [3:0] uops_4_br_type; // @[util.scala:505:22]
reg uops_4_is_sfb; // @[util.scala:505:22]
reg uops_4_is_fence; // @[util.scala:505:22]
reg uops_4_is_fencei; // @[util.scala:505:22]
reg uops_4_is_sfence; // @[util.scala:505:22]
reg uops_4_is_amo; // @[util.scala:505:22]
reg uops_4_is_eret; // @[util.scala:505:22]
reg uops_4_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_4_is_rocc; // @[util.scala:505:22]
reg uops_4_is_mov; // @[util.scala:505:22]
reg [3:0] uops_4_ftq_idx; // @[util.scala:505:22]
reg uops_4_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_4_pc_lob; // @[util.scala:505:22]
reg uops_4_taken; // @[util.scala:505:22]
reg uops_4_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_4_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_4_pimm; // @[util.scala:505:22]
reg [19:0] uops_4_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_4_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_4_op2_sel; // @[util.scala:505:22]
reg uops_4_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_4_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_4_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_4_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_4_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_4_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_4_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_4_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_4_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_4_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_4_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_4_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_4_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_4_fp_ctrl_div; // @[util.scala:505:22]
reg uops_4_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_4_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_4_fp_ctrl_vec; // @[util.scala:505:22]
reg [4:0] uops_4_rob_idx; // @[util.scala:505:22]
reg [3:0] uops_4_ldq_idx; // @[util.scala:505:22]
reg [3:0] uops_4_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_4_rxq_idx; // @[util.scala:505:22]
reg [5:0] uops_4_pdst; // @[util.scala:505:22]
reg [5:0] uops_4_prs1; // @[util.scala:505:22]
reg [5:0] uops_4_prs2; // @[util.scala:505:22]
reg [5:0] uops_4_prs3; // @[util.scala:505:22]
reg [3:0] uops_4_ppred; // @[util.scala:505:22]
reg uops_4_prs1_busy; // @[util.scala:505:22]
reg uops_4_prs2_busy; // @[util.scala:505:22]
reg uops_4_prs3_busy; // @[util.scala:505:22]
reg uops_4_ppred_busy; // @[util.scala:505:22]
reg [5:0] uops_4_stale_pdst; // @[util.scala:505:22]
reg uops_4_exception; // @[util.scala:505:22]
reg [63:0] uops_4_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_4_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_4_mem_size; // @[util.scala:505:22]
reg uops_4_mem_signed; // @[util.scala:505:22]
reg uops_4_uses_ldq; // @[util.scala:505:22]
reg uops_4_uses_stq; // @[util.scala:505:22]
reg uops_4_is_unique; // @[util.scala:505:22]
reg uops_4_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_4_csr_cmd; // @[util.scala:505:22]
reg uops_4_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_4_ldst; // @[util.scala:505:22]
reg [5:0] uops_4_lrs1; // @[util.scala:505:22]
reg [5:0] uops_4_lrs2; // @[util.scala:505:22]
reg [5:0] uops_4_lrs3; // @[util.scala:505:22]
reg [1:0] uops_4_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_4_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_4_lrs2_rtype; // @[util.scala:505:22]
reg uops_4_frs3_en; // @[util.scala:505:22]
reg uops_4_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_4_fcn_op; // @[util.scala:505:22]
reg uops_4_fp_val; // @[util.scala:505:22]
reg [2:0] uops_4_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_4_fp_typ; // @[util.scala:505:22]
reg uops_4_xcpt_pf_if; // @[util.scala:505:22]
reg uops_4_xcpt_ae_if; // @[util.scala:505:22]
reg uops_4_xcpt_ma_if; // @[util.scala:505:22]
reg uops_4_bp_debug_if; // @[util.scala:505:22]
reg uops_4_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_4_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_4_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_5_inst; // @[util.scala:505:22]
reg [31:0] uops_5_debug_inst; // @[util.scala:505:22]
reg uops_5_is_rvc; // @[util.scala:505:22]
reg [33:0] uops_5_debug_pc; // @[util.scala:505:22]
reg uops_5_iq_type_0; // @[util.scala:505:22]
reg uops_5_iq_type_1; // @[util.scala:505:22]
reg uops_5_iq_type_2; // @[util.scala:505:22]
reg uops_5_iq_type_3; // @[util.scala:505:22]
reg uops_5_fu_code_0; // @[util.scala:505:22]
reg uops_5_fu_code_1; // @[util.scala:505:22]
reg uops_5_fu_code_2; // @[util.scala:505:22]
reg uops_5_fu_code_3; // @[util.scala:505:22]
reg uops_5_fu_code_4; // @[util.scala:505:22]
reg uops_5_fu_code_5; // @[util.scala:505:22]
reg uops_5_fu_code_6; // @[util.scala:505:22]
reg uops_5_fu_code_7; // @[util.scala:505:22]
reg uops_5_fu_code_8; // @[util.scala:505:22]
reg uops_5_fu_code_9; // @[util.scala:505:22]
reg uops_5_iw_issued; // @[util.scala:505:22]
reg uops_5_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_5_iw_issued_partial_dgen; // @[util.scala:505:22]
reg uops_5_iw_p1_speculative_child; // @[util.scala:505:22]
reg uops_5_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_5_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_5_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_5_iw_p3_bypass_hint; // @[util.scala:505:22]
reg uops_5_dis_col_sel; // @[util.scala:505:22]
reg [3:0] uops_5_br_mask; // @[util.scala:505:22]
wire [3:0] _uops_5_br_mask_T_1 = uops_5_br_mask; // @[util.scala:97:21, :505:22]
reg [1:0] uops_5_br_tag; // @[util.scala:505:22]
reg [3:0] uops_5_br_type; // @[util.scala:505:22]
reg uops_5_is_sfb; // @[util.scala:505:22]
reg uops_5_is_fence; // @[util.scala:505:22]
reg uops_5_is_fencei; // @[util.scala:505:22]
reg uops_5_is_sfence; // @[util.scala:505:22]
reg uops_5_is_amo; // @[util.scala:505:22]
reg uops_5_is_eret; // @[util.scala:505:22]
reg uops_5_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_5_is_rocc; // @[util.scala:505:22]
reg uops_5_is_mov; // @[util.scala:505:22]
reg [3:0] uops_5_ftq_idx; // @[util.scala:505:22]
reg uops_5_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_5_pc_lob; // @[util.scala:505:22]
reg uops_5_taken; // @[util.scala:505:22]
reg uops_5_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_5_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_5_pimm; // @[util.scala:505:22]
reg [19:0] uops_5_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_5_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_5_op2_sel; // @[util.scala:505:22]
reg uops_5_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_5_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_5_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_5_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_5_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_5_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_5_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_5_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_5_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_5_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_5_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_5_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_5_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_5_fp_ctrl_div; // @[util.scala:505:22]
reg uops_5_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_5_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_5_fp_ctrl_vec; // @[util.scala:505:22]
reg [4:0] uops_5_rob_idx; // @[util.scala:505:22]
reg [3:0] uops_5_ldq_idx; // @[util.scala:505:22]
reg [3:0] uops_5_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_5_rxq_idx; // @[util.scala:505:22]
reg [5:0] uops_5_pdst; // @[util.scala:505:22]
reg [5:0] uops_5_prs1; // @[util.scala:505:22]
reg [5:0] uops_5_prs2; // @[util.scala:505:22]
reg [5:0] uops_5_prs3; // @[util.scala:505:22]
reg [3:0] uops_5_ppred; // @[util.scala:505:22]
reg uops_5_prs1_busy; // @[util.scala:505:22]
reg uops_5_prs2_busy; // @[util.scala:505:22]
reg uops_5_prs3_busy; // @[util.scala:505:22]
reg uops_5_ppred_busy; // @[util.scala:505:22]
reg [5:0] uops_5_stale_pdst; // @[util.scala:505:22]
reg uops_5_exception; // @[util.scala:505:22]
reg [63:0] uops_5_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_5_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_5_mem_size; // @[util.scala:505:22]
reg uops_5_mem_signed; // @[util.scala:505:22]
reg uops_5_uses_ldq; // @[util.scala:505:22]
reg uops_5_uses_stq; // @[util.scala:505:22]
reg uops_5_is_unique; // @[util.scala:505:22]
reg uops_5_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_5_csr_cmd; // @[util.scala:505:22]
reg uops_5_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_5_ldst; // @[util.scala:505:22]
reg [5:0] uops_5_lrs1; // @[util.scala:505:22]
reg [5:0] uops_5_lrs2; // @[util.scala:505:22]
reg [5:0] uops_5_lrs3; // @[util.scala:505:22]
reg [1:0] uops_5_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_5_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_5_lrs2_rtype; // @[util.scala:505:22]
reg uops_5_frs3_en; // @[util.scala:505:22]
reg uops_5_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_5_fcn_op; // @[util.scala:505:22]
reg uops_5_fp_val; // @[util.scala:505:22]
reg [2:0] uops_5_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_5_fp_typ; // @[util.scala:505:22]
reg uops_5_xcpt_pf_if; // @[util.scala:505:22]
reg uops_5_xcpt_ae_if; // @[util.scala:505:22]
reg uops_5_xcpt_ma_if; // @[util.scala:505:22]
reg uops_5_bp_debug_if; // @[util.scala:505:22]
reg uops_5_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_5_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_5_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_6_inst; // @[util.scala:505:22]
reg [31:0] uops_6_debug_inst; // @[util.scala:505:22]
reg uops_6_is_rvc; // @[util.scala:505:22]
reg [33:0] uops_6_debug_pc; // @[util.scala:505:22]
reg uops_6_iq_type_0; // @[util.scala:505:22]
reg uops_6_iq_type_1; // @[util.scala:505:22]
reg uops_6_iq_type_2; // @[util.scala:505:22]
reg uops_6_iq_type_3; // @[util.scala:505:22]
reg uops_6_fu_code_0; // @[util.scala:505:22]
reg uops_6_fu_code_1; // @[util.scala:505:22]
reg uops_6_fu_code_2; // @[util.scala:505:22]
reg uops_6_fu_code_3; // @[util.scala:505:22]
reg uops_6_fu_code_4; // @[util.scala:505:22]
reg uops_6_fu_code_5; // @[util.scala:505:22]
reg uops_6_fu_code_6; // @[util.scala:505:22]
reg uops_6_fu_code_7; // @[util.scala:505:22]
reg uops_6_fu_code_8; // @[util.scala:505:22]
reg uops_6_fu_code_9; // @[util.scala:505:22]
reg uops_6_iw_issued; // @[util.scala:505:22]
reg uops_6_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_6_iw_issued_partial_dgen; // @[util.scala:505:22]
reg uops_6_iw_p1_speculative_child; // @[util.scala:505:22]
reg uops_6_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_6_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_6_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_6_iw_p3_bypass_hint; // @[util.scala:505:22]
reg uops_6_dis_col_sel; // @[util.scala:505:22]
reg [3:0] uops_6_br_mask; // @[util.scala:505:22]
wire [3:0] _uops_6_br_mask_T_1 = uops_6_br_mask; // @[util.scala:97:21, :505:22]
reg [1:0] uops_6_br_tag; // @[util.scala:505:22]
reg [3:0] uops_6_br_type; // @[util.scala:505:22]
reg uops_6_is_sfb; // @[util.scala:505:22]
reg uops_6_is_fence; // @[util.scala:505:22]
reg uops_6_is_fencei; // @[util.scala:505:22]
reg uops_6_is_sfence; // @[util.scala:505:22]
reg uops_6_is_amo; // @[util.scala:505:22]
reg uops_6_is_eret; // @[util.scala:505:22]
reg uops_6_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_6_is_rocc; // @[util.scala:505:22]
reg uops_6_is_mov; // @[util.scala:505:22]
reg [3:0] uops_6_ftq_idx; // @[util.scala:505:22]
reg uops_6_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_6_pc_lob; // @[util.scala:505:22]
reg uops_6_taken; // @[util.scala:505:22]
reg uops_6_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_6_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_6_pimm; // @[util.scala:505:22]
reg [19:0] uops_6_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_6_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_6_op2_sel; // @[util.scala:505:22]
reg uops_6_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_6_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_6_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_6_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_6_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_6_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_6_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_6_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_6_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_6_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_6_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_6_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_6_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_6_fp_ctrl_div; // @[util.scala:505:22]
reg uops_6_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_6_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_6_fp_ctrl_vec; // @[util.scala:505:22]
reg [4:0] uops_6_rob_idx; // @[util.scala:505:22]
reg [3:0] uops_6_ldq_idx; // @[util.scala:505:22]
reg [3:0] uops_6_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_6_rxq_idx; // @[util.scala:505:22]
reg [5:0] uops_6_pdst; // @[util.scala:505:22]
reg [5:0] uops_6_prs1; // @[util.scala:505:22]
reg [5:0] uops_6_prs2; // @[util.scala:505:22]
reg [5:0] uops_6_prs3; // @[util.scala:505:22]
reg [3:0] uops_6_ppred; // @[util.scala:505:22]
reg uops_6_prs1_busy; // @[util.scala:505:22]
reg uops_6_prs2_busy; // @[util.scala:505:22]
reg uops_6_prs3_busy; // @[util.scala:505:22]
reg uops_6_ppred_busy; // @[util.scala:505:22]
reg [5:0] uops_6_stale_pdst; // @[util.scala:505:22]
reg uops_6_exception; // @[util.scala:505:22]
reg [63:0] uops_6_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_6_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_6_mem_size; // @[util.scala:505:22]
reg uops_6_mem_signed; // @[util.scala:505:22]
reg uops_6_uses_ldq; // @[util.scala:505:22]
reg uops_6_uses_stq; // @[util.scala:505:22]
reg uops_6_is_unique; // @[util.scala:505:22]
reg uops_6_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_6_csr_cmd; // @[util.scala:505:22]
reg uops_6_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_6_ldst; // @[util.scala:505:22]
reg [5:0] uops_6_lrs1; // @[util.scala:505:22]
reg [5:0] uops_6_lrs2; // @[util.scala:505:22]
reg [5:0] uops_6_lrs3; // @[util.scala:505:22]
reg [1:0] uops_6_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_6_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_6_lrs2_rtype; // @[util.scala:505:22]
reg uops_6_frs3_en; // @[util.scala:505:22]
reg uops_6_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_6_fcn_op; // @[util.scala:505:22]
reg uops_6_fp_val; // @[util.scala:505:22]
reg [2:0] uops_6_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_6_fp_typ; // @[util.scala:505:22]
reg uops_6_xcpt_pf_if; // @[util.scala:505:22]
reg uops_6_xcpt_ae_if; // @[util.scala:505:22]
reg uops_6_xcpt_ma_if; // @[util.scala:505:22]
reg uops_6_bp_debug_if; // @[util.scala:505:22]
reg uops_6_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_6_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_6_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_7_inst; // @[util.scala:505:22]
reg [31:0] uops_7_debug_inst; // @[util.scala:505:22]
reg uops_7_is_rvc; // @[util.scala:505:22]
reg [33:0] uops_7_debug_pc; // @[util.scala:505:22]
reg uops_7_iq_type_0; // @[util.scala:505:22]
reg uops_7_iq_type_1; // @[util.scala:505:22]
reg uops_7_iq_type_2; // @[util.scala:505:22]
reg uops_7_iq_type_3; // @[util.scala:505:22]
reg uops_7_fu_code_0; // @[util.scala:505:22]
reg uops_7_fu_code_1; // @[util.scala:505:22]
reg uops_7_fu_code_2; // @[util.scala:505:22]
reg uops_7_fu_code_3; // @[util.scala:505:22]
reg uops_7_fu_code_4; // @[util.scala:505:22]
reg uops_7_fu_code_5; // @[util.scala:505:22]
reg uops_7_fu_code_6; // @[util.scala:505:22]
reg uops_7_fu_code_7; // @[util.scala:505:22]
reg uops_7_fu_code_8; // @[util.scala:505:22]
reg uops_7_fu_code_9; // @[util.scala:505:22]
reg uops_7_iw_issued; // @[util.scala:505:22]
reg uops_7_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_7_iw_issued_partial_dgen; // @[util.scala:505:22]
reg uops_7_iw_p1_speculative_child; // @[util.scala:505:22]
reg uops_7_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_7_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_7_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_7_iw_p3_bypass_hint; // @[util.scala:505:22]
reg uops_7_dis_col_sel; // @[util.scala:505:22]
reg [3:0] uops_7_br_mask; // @[util.scala:505:22]
wire [3:0] _uops_7_br_mask_T_1 = uops_7_br_mask; // @[util.scala:97:21, :505:22]
reg [1:0] uops_7_br_tag; // @[util.scala:505:22]
reg [3:0] uops_7_br_type; // @[util.scala:505:22]
reg uops_7_is_sfb; // @[util.scala:505:22]
reg uops_7_is_fence; // @[util.scala:505:22]
reg uops_7_is_fencei; // @[util.scala:505:22]
reg uops_7_is_sfence; // @[util.scala:505:22]
reg uops_7_is_amo; // @[util.scala:505:22]
reg uops_7_is_eret; // @[util.scala:505:22]
reg uops_7_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_7_is_rocc; // @[util.scala:505:22]
reg uops_7_is_mov; // @[util.scala:505:22]
reg [3:0] uops_7_ftq_idx; // @[util.scala:505:22]
reg uops_7_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_7_pc_lob; // @[util.scala:505:22]
reg uops_7_taken; // @[util.scala:505:22]
reg uops_7_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_7_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_7_pimm; // @[util.scala:505:22]
reg [19:0] uops_7_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_7_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_7_op2_sel; // @[util.scala:505:22]
reg uops_7_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_7_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_7_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_7_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_7_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_7_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_7_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_7_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_7_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_7_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_7_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_7_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_7_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_7_fp_ctrl_div; // @[util.scala:505:22]
reg uops_7_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_7_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_7_fp_ctrl_vec; // @[util.scala:505:22]
reg [4:0] uops_7_rob_idx; // @[util.scala:505:22]
reg [3:0] uops_7_ldq_idx; // @[util.scala:505:22]
reg [3:0] uops_7_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_7_rxq_idx; // @[util.scala:505:22]
reg [5:0] uops_7_pdst; // @[util.scala:505:22]
reg [5:0] uops_7_prs1; // @[util.scala:505:22]
reg [5:0] uops_7_prs2; // @[util.scala:505:22]
reg [5:0] uops_7_prs3; // @[util.scala:505:22]
reg [3:0] uops_7_ppred; // @[util.scala:505:22]
reg uops_7_prs1_busy; // @[util.scala:505:22]
reg uops_7_prs2_busy; // @[util.scala:505:22]
reg uops_7_prs3_busy; // @[util.scala:505:22]
reg uops_7_ppred_busy; // @[util.scala:505:22]
reg [5:0] uops_7_stale_pdst; // @[util.scala:505:22]
reg uops_7_exception; // @[util.scala:505:22]
reg [63:0] uops_7_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_7_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_7_mem_size; // @[util.scala:505:22]
reg uops_7_mem_signed; // @[util.scala:505:22]
reg uops_7_uses_ldq; // @[util.scala:505:22]
reg uops_7_uses_stq; // @[util.scala:505:22]
reg uops_7_is_unique; // @[util.scala:505:22]
reg uops_7_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_7_csr_cmd; // @[util.scala:505:22]
reg uops_7_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_7_ldst; // @[util.scala:505:22]
reg [5:0] uops_7_lrs1; // @[util.scala:505:22]
reg [5:0] uops_7_lrs2; // @[util.scala:505:22]
reg [5:0] uops_7_lrs3; // @[util.scala:505:22]
reg [1:0] uops_7_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_7_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_7_lrs2_rtype; // @[util.scala:505:22]
reg uops_7_frs3_en; // @[util.scala:505:22]
reg uops_7_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_7_fcn_op; // @[util.scala:505:22]
reg uops_7_fp_val; // @[util.scala:505:22]
reg [2:0] uops_7_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_7_fp_typ; // @[util.scala:505:22]
reg uops_7_xcpt_pf_if; // @[util.scala:505:22]
reg uops_7_xcpt_ae_if; // @[util.scala:505:22]
reg uops_7_xcpt_ma_if; // @[util.scala:505:22]
reg uops_7_bp_debug_if; // @[util.scala:505:22]
reg uops_7_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_7_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_7_debug_tsrc; // @[util.scala:505:22]
reg [2:0] enq_ptr_value; // @[Counter.scala:61:40]
reg [2:0] deq_ptr_value; // @[Counter.scala:61:40]
reg maybe_full; // @[util.scala:509:29]
wire ptr_match = enq_ptr_value == deq_ptr_value; // @[Counter.scala:61:40]
wire _io_empty_T = ~maybe_full; // @[util.scala:509:29, :512:30]
assign _io_empty_T_1 = ptr_match & _io_empty_T; // @[util.scala:511:35, :512:{27,30}]
assign io_empty = _io_empty_T_1; // @[util.scala:458:7, :512:27]
wire _GEN = ptr_match & maybe_full; // @[util.scala:509:29, :511:35, :513:26]
wire full; // @[util.scala:513:26]
assign full = _GEN; // @[util.scala:513:26]
wire _io_count_T; // @[util.scala:553:34]
assign _io_count_T = _GEN; // @[util.scala:513:26, :553:34]
wire _do_enq_T = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35]
wire _do_enq_T_5 = _do_enq_T; // @[Decoupled.scala:51:35]
wire _do_enq_T_8 = _do_enq_T_5; // @[util.scala:514:{39,99}]
wire do_enq = _do_enq_T_8; // @[util.scala:514:{26,99}]
wire [7:0] _GEN_0 = {{valids_7}, {valids_6}, {valids_5}, {valids_4}, {valids_3}, {valids_2}, {valids_1}, {valids_0}}; // @[util.scala:504:26, :515:44]
wire _GEN_1 = _GEN_0[deq_ptr_value]; // @[Counter.scala:61:40]
wire _do_deq_T = ~_GEN_1; // @[util.scala:515:44]
wire _do_deq_T_1 = io_deq_ready_0 | _do_deq_T; // @[util.scala:458:7, :515:{41,44}]
wire _do_deq_T_2 = ~io_empty; // @[util.scala:458:7, :515:71]
wire _do_deq_T_3 = _do_deq_T_1 & _do_deq_T_2; // @[util.scala:515:{41,68,71}]
wire do_deq = _do_deq_T_3; // @[util.scala:515:{26,68}]
wire _valids_0_T_7 = _valids_0_T_4; // @[util.scala:520:{31,80}]
wire _valids_1_T_7 = _valids_1_T_4; // @[util.scala:520:{31,80}]
wire _valids_2_T_7 = _valids_2_T_4; // @[util.scala:520:{31,80}]
wire _valids_3_T_7 = _valids_3_T_4; // @[util.scala:520:{31,80}]
wire _valids_4_T_7 = _valids_4_T_4; // @[util.scala:520:{31,80}]
wire _valids_5_T_7 = _valids_5_T_4; // @[util.scala:520:{31,80}]
wire _valids_6_T_7 = _valids_6_T_4; // @[util.scala:520:{31,80}]
wire _valids_7_T_7 = _valids_7_T_4; // @[util.scala:520:{31,80}]
wire wrap = &enq_ptr_value; // @[Counter.scala:61:40, :73:24]
wire [3:0] _GEN_2 = {1'h0, enq_ptr_value}; // @[Counter.scala:61:40, :77:24]
wire [3:0] _value_T = _GEN_2 + 4'h1; // @[Counter.scala:77:24]
wire [2:0] _value_T_1 = _value_T[2:0]; // @[Counter.scala:77:24]
wire wrap_1 = &deq_ptr_value; // @[Counter.scala:61:40, :73:24]
wire [3:0] _GEN_3 = {1'h0, deq_ptr_value}; // @[Counter.scala:61:40, :77:24]
wire [3:0] _value_T_2 = _GEN_3 + 4'h1; // @[Counter.scala:77:24]
wire [2:0] _value_T_3 = _value_T_2[2:0]; // @[Counter.scala:77:24]
assign _io_enq_ready_T = ~full; // @[util.scala:513:26, :543:21]
assign io_enq_ready_0 = _io_enq_ready_T; // @[util.scala:458:7, :543:21]
assign io_deq_bits_uop_inst_0 = out_uop_inst; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_debug_inst_0 = out_uop_debug_inst; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_rvc_0 = out_uop_is_rvc; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_debug_pc_0 = out_uop_debug_pc; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iq_type_0_0 = out_uop_iq_type_0; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iq_type_1_0 = out_uop_iq_type_1; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iq_type_2_0 = out_uop_iq_type_2; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iq_type_3_0 = out_uop_iq_type_3; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_0_0 = out_uop_fu_code_0; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_1_0 = out_uop_fu_code_1; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_2_0 = out_uop_fu_code_2; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_3_0 = out_uop_fu_code_3; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_4_0 = out_uop_fu_code_4; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_5_0 = out_uop_fu_code_5; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_6_0 = out_uop_fu_code_6; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_7_0 = out_uop_fu_code_7; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_8_0 = out_uop_fu_code_8; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_9_0 = out_uop_fu_code_9; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_issued_0 = out_uop_iw_issued; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_issued_partial_agen_0 = out_uop_iw_issued_partial_agen; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_issued_partial_dgen_0 = out_uop_iw_issued_partial_dgen; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_p1_speculative_child_0 = out_uop_iw_p1_speculative_child; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_p2_speculative_child_0 = out_uop_iw_p2_speculative_child; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_p1_bypass_hint_0 = out_uop_iw_p1_bypass_hint; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_p2_bypass_hint_0 = out_uop_iw_p2_bypass_hint; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_p3_bypass_hint_0 = out_uop_iw_p3_bypass_hint; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_dis_col_sel_0 = out_uop_dis_col_sel; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_br_mask_0 = out_uop_br_mask; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_br_tag_0 = out_uop_br_tag; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_br_type_0 = out_uop_br_type; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_sfb_0 = out_uop_is_sfb; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_fence_0 = out_uop_is_fence; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_fencei_0 = out_uop_is_fencei; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_sfence_0 = out_uop_is_sfence; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_amo_0 = out_uop_is_amo; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_eret_0 = out_uop_is_eret; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_sys_pc2epc_0 = out_uop_is_sys_pc2epc; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_rocc_0 = out_uop_is_rocc; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_mov_0 = out_uop_is_mov; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_ftq_idx_0 = out_uop_ftq_idx; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_edge_inst_0 = out_uop_edge_inst; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_pc_lob_0 = out_uop_pc_lob; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_taken_0 = out_uop_taken; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_imm_rename_0 = out_uop_imm_rename; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_imm_sel_0 = out_uop_imm_sel; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_pimm_0 = out_uop_pimm; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_imm_packed_0 = out_uop_imm_packed; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_op1_sel_0 = out_uop_op1_sel; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_op2_sel_0 = out_uop_op2_sel; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_ldst_0 = out_uop_fp_ctrl_ldst; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_wen_0 = out_uop_fp_ctrl_wen; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_ren1_0 = out_uop_fp_ctrl_ren1; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_ren2_0 = out_uop_fp_ctrl_ren2; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_ren3_0 = out_uop_fp_ctrl_ren3; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_swap12_0 = out_uop_fp_ctrl_swap12; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_swap23_0 = out_uop_fp_ctrl_swap23; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_typeTagIn_0 = out_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_typeTagOut_0 = out_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_fromint_0 = out_uop_fp_ctrl_fromint; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_toint_0 = out_uop_fp_ctrl_toint; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_fastpipe_0 = out_uop_fp_ctrl_fastpipe; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_fma_0 = out_uop_fp_ctrl_fma; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_div_0 = out_uop_fp_ctrl_div; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_sqrt_0 = out_uop_fp_ctrl_sqrt; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_wflags_0 = out_uop_fp_ctrl_wflags; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_vec_0 = out_uop_fp_ctrl_vec; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_rob_idx_0 = out_uop_rob_idx; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_ldq_idx_0 = out_uop_ldq_idx; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_stq_idx_0 = out_uop_stq_idx; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_rxq_idx_0 = out_uop_rxq_idx; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_pdst_0 = out_uop_pdst; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_prs1_0 = out_uop_prs1; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_prs2_0 = out_uop_prs2; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_prs3_0 = out_uop_prs3; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_ppred_0 = out_uop_ppred; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_prs1_busy_0 = out_uop_prs1_busy; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_prs2_busy_0 = out_uop_prs2_busy; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_prs3_busy_0 = out_uop_prs3_busy; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_ppred_busy_0 = out_uop_ppred_busy; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_stale_pdst_0 = out_uop_stale_pdst; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_exception_0 = out_uop_exception; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_exc_cause_0 = out_uop_exc_cause; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_mem_cmd_0 = out_uop_mem_cmd; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_mem_size_0 = out_uop_mem_size; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_mem_signed_0 = out_uop_mem_signed; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_uses_ldq_0 = out_uop_uses_ldq; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_uses_stq_0 = out_uop_uses_stq; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_unique_0 = out_uop_is_unique; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_flush_on_commit_0 = out_uop_flush_on_commit; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_csr_cmd_0 = out_uop_csr_cmd; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_ldst_is_rs1_0 = out_uop_ldst_is_rs1; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_ldst_0 = out_uop_ldst; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_lrs1_0 = out_uop_lrs1; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_lrs2_0 = out_uop_lrs2; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_lrs3_0 = out_uop_lrs3; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_dst_rtype_0 = out_uop_dst_rtype; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_lrs1_rtype_0 = out_uop_lrs1_rtype; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_lrs2_rtype_0 = out_uop_lrs2_rtype; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_frs3_en_0 = out_uop_frs3_en; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fcn_dw_0 = out_uop_fcn_dw; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fcn_op_0 = out_uop_fcn_op; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_val_0 = out_uop_fp_val; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_rm_0 = out_uop_fp_rm; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_typ_0 = out_uop_fp_typ; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_xcpt_pf_if_0 = out_uop_xcpt_pf_if; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_xcpt_ae_if_0 = out_uop_xcpt_ae_if; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_xcpt_ma_if_0 = out_uop_xcpt_ma_if; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_bp_debug_if_0 = out_uop_bp_debug_if; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_bp_xcpt_if_0 = out_uop_bp_xcpt_if; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_debug_fsrc_0 = out_uop_debug_fsrc; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_debug_tsrc_0 = out_uop_debug_tsrc; // @[util.scala:458:7, :545:19]
assign io_deq_bits_data_0 = out_data; // @[util.scala:458:7, :545:19]
wire [7:0][31:0] _GEN_4 = {{uops_7_inst}, {uops_6_inst}, {uops_5_inst}, {uops_4_inst}, {uops_3_inst}, {uops_2_inst}, {uops_1_inst}, {uops_0_inst}}; // @[util.scala:505:22, :547:21]
assign out_uop_inst = _GEN_4[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][31:0] _GEN_5 = {{uops_7_debug_inst}, {uops_6_debug_inst}, {uops_5_debug_inst}, {uops_4_debug_inst}, {uops_3_debug_inst}, {uops_2_debug_inst}, {uops_1_debug_inst}, {uops_0_debug_inst}}; // @[util.scala:505:22, :547:21]
assign out_uop_debug_inst = _GEN_5[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_6 = {{uops_7_is_rvc}, {uops_6_is_rvc}, {uops_5_is_rvc}, {uops_4_is_rvc}, {uops_3_is_rvc}, {uops_2_is_rvc}, {uops_1_is_rvc}, {uops_0_is_rvc}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_rvc = _GEN_6[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][33:0] _GEN_7 = {{uops_7_debug_pc}, {uops_6_debug_pc}, {uops_5_debug_pc}, {uops_4_debug_pc}, {uops_3_debug_pc}, {uops_2_debug_pc}, {uops_1_debug_pc}, {uops_0_debug_pc}}; // @[util.scala:505:22, :547:21]
assign out_uop_debug_pc = _GEN_7[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_8 = {{uops_7_iq_type_0}, {uops_6_iq_type_0}, {uops_5_iq_type_0}, {uops_4_iq_type_0}, {uops_3_iq_type_0}, {uops_2_iq_type_0}, {uops_1_iq_type_0}, {uops_0_iq_type_0}}; // @[util.scala:505:22, :547:21]
assign out_uop_iq_type_0 = _GEN_8[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_9 = {{uops_7_iq_type_1}, {uops_6_iq_type_1}, {uops_5_iq_type_1}, {uops_4_iq_type_1}, {uops_3_iq_type_1}, {uops_2_iq_type_1}, {uops_1_iq_type_1}, {uops_0_iq_type_1}}; // @[util.scala:505:22, :547:21]
assign out_uop_iq_type_1 = _GEN_9[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_10 = {{uops_7_iq_type_2}, {uops_6_iq_type_2}, {uops_5_iq_type_2}, {uops_4_iq_type_2}, {uops_3_iq_type_2}, {uops_2_iq_type_2}, {uops_1_iq_type_2}, {uops_0_iq_type_2}}; // @[util.scala:505:22, :547:21]
assign out_uop_iq_type_2 = _GEN_10[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_11 = {{uops_7_iq_type_3}, {uops_6_iq_type_3}, {uops_5_iq_type_3}, {uops_4_iq_type_3}, {uops_3_iq_type_3}, {uops_2_iq_type_3}, {uops_1_iq_type_3}, {uops_0_iq_type_3}}; // @[util.scala:505:22, :547:21]
assign out_uop_iq_type_3 = _GEN_11[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_12 = {{uops_7_fu_code_0}, {uops_6_fu_code_0}, {uops_5_fu_code_0}, {uops_4_fu_code_0}, {uops_3_fu_code_0}, {uops_2_fu_code_0}, {uops_1_fu_code_0}, {uops_0_fu_code_0}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_0 = _GEN_12[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_13 = {{uops_7_fu_code_1}, {uops_6_fu_code_1}, {uops_5_fu_code_1}, {uops_4_fu_code_1}, {uops_3_fu_code_1}, {uops_2_fu_code_1}, {uops_1_fu_code_1}, {uops_0_fu_code_1}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_1 = _GEN_13[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_14 = {{uops_7_fu_code_2}, {uops_6_fu_code_2}, {uops_5_fu_code_2}, {uops_4_fu_code_2}, {uops_3_fu_code_2}, {uops_2_fu_code_2}, {uops_1_fu_code_2}, {uops_0_fu_code_2}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_2 = _GEN_14[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_15 = {{uops_7_fu_code_3}, {uops_6_fu_code_3}, {uops_5_fu_code_3}, {uops_4_fu_code_3}, {uops_3_fu_code_3}, {uops_2_fu_code_3}, {uops_1_fu_code_3}, {uops_0_fu_code_3}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_3 = _GEN_15[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_16 = {{uops_7_fu_code_4}, {uops_6_fu_code_4}, {uops_5_fu_code_4}, {uops_4_fu_code_4}, {uops_3_fu_code_4}, {uops_2_fu_code_4}, {uops_1_fu_code_4}, {uops_0_fu_code_4}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_4 = _GEN_16[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_17 = {{uops_7_fu_code_5}, {uops_6_fu_code_5}, {uops_5_fu_code_5}, {uops_4_fu_code_5}, {uops_3_fu_code_5}, {uops_2_fu_code_5}, {uops_1_fu_code_5}, {uops_0_fu_code_5}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_5 = _GEN_17[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_18 = {{uops_7_fu_code_6}, {uops_6_fu_code_6}, {uops_5_fu_code_6}, {uops_4_fu_code_6}, {uops_3_fu_code_6}, {uops_2_fu_code_6}, {uops_1_fu_code_6}, {uops_0_fu_code_6}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_6 = _GEN_18[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_19 = {{uops_7_fu_code_7}, {uops_6_fu_code_7}, {uops_5_fu_code_7}, {uops_4_fu_code_7}, {uops_3_fu_code_7}, {uops_2_fu_code_7}, {uops_1_fu_code_7}, {uops_0_fu_code_7}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_7 = _GEN_19[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_20 = {{uops_7_fu_code_8}, {uops_6_fu_code_8}, {uops_5_fu_code_8}, {uops_4_fu_code_8}, {uops_3_fu_code_8}, {uops_2_fu_code_8}, {uops_1_fu_code_8}, {uops_0_fu_code_8}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_8 = _GEN_20[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_21 = {{uops_7_fu_code_9}, {uops_6_fu_code_9}, {uops_5_fu_code_9}, {uops_4_fu_code_9}, {uops_3_fu_code_9}, {uops_2_fu_code_9}, {uops_1_fu_code_9}, {uops_0_fu_code_9}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_9 = _GEN_21[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_22 = {{uops_7_iw_issued}, {uops_6_iw_issued}, {uops_5_iw_issued}, {uops_4_iw_issued}, {uops_3_iw_issued}, {uops_2_iw_issued}, {uops_1_iw_issued}, {uops_0_iw_issued}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_issued = _GEN_22[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_23 = {{uops_7_iw_issued_partial_agen}, {uops_6_iw_issued_partial_agen}, {uops_5_iw_issued_partial_agen}, {uops_4_iw_issued_partial_agen}, {uops_3_iw_issued_partial_agen}, {uops_2_iw_issued_partial_agen}, {uops_1_iw_issued_partial_agen}, {uops_0_iw_issued_partial_agen}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_issued_partial_agen = _GEN_23[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_24 = {{uops_7_iw_issued_partial_dgen}, {uops_6_iw_issued_partial_dgen}, {uops_5_iw_issued_partial_dgen}, {uops_4_iw_issued_partial_dgen}, {uops_3_iw_issued_partial_dgen}, {uops_2_iw_issued_partial_dgen}, {uops_1_iw_issued_partial_dgen}, {uops_0_iw_issued_partial_dgen}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_issued_partial_dgen = _GEN_24[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_25 = {{uops_7_iw_p1_speculative_child}, {uops_6_iw_p1_speculative_child}, {uops_5_iw_p1_speculative_child}, {uops_4_iw_p1_speculative_child}, {uops_3_iw_p1_speculative_child}, {uops_2_iw_p1_speculative_child}, {uops_1_iw_p1_speculative_child}, {uops_0_iw_p1_speculative_child}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_p1_speculative_child = _GEN_25[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_26 = {{uops_7_iw_p2_speculative_child}, {uops_6_iw_p2_speculative_child}, {uops_5_iw_p2_speculative_child}, {uops_4_iw_p2_speculative_child}, {uops_3_iw_p2_speculative_child}, {uops_2_iw_p2_speculative_child}, {uops_1_iw_p2_speculative_child}, {uops_0_iw_p2_speculative_child}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_p2_speculative_child = _GEN_26[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_27 = {{uops_7_iw_p1_bypass_hint}, {uops_6_iw_p1_bypass_hint}, {uops_5_iw_p1_bypass_hint}, {uops_4_iw_p1_bypass_hint}, {uops_3_iw_p1_bypass_hint}, {uops_2_iw_p1_bypass_hint}, {uops_1_iw_p1_bypass_hint}, {uops_0_iw_p1_bypass_hint}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_p1_bypass_hint = _GEN_27[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_28 = {{uops_7_iw_p2_bypass_hint}, {uops_6_iw_p2_bypass_hint}, {uops_5_iw_p2_bypass_hint}, {uops_4_iw_p2_bypass_hint}, {uops_3_iw_p2_bypass_hint}, {uops_2_iw_p2_bypass_hint}, {uops_1_iw_p2_bypass_hint}, {uops_0_iw_p2_bypass_hint}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_p2_bypass_hint = _GEN_28[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_29 = {{uops_7_iw_p3_bypass_hint}, {uops_6_iw_p3_bypass_hint}, {uops_5_iw_p3_bypass_hint}, {uops_4_iw_p3_bypass_hint}, {uops_3_iw_p3_bypass_hint}, {uops_2_iw_p3_bypass_hint}, {uops_1_iw_p3_bypass_hint}, {uops_0_iw_p3_bypass_hint}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_p3_bypass_hint = _GEN_29[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_30 = {{uops_7_dis_col_sel}, {uops_6_dis_col_sel}, {uops_5_dis_col_sel}, {uops_4_dis_col_sel}, {uops_3_dis_col_sel}, {uops_2_dis_col_sel}, {uops_1_dis_col_sel}, {uops_0_dis_col_sel}}; // @[util.scala:505:22, :547:21]
assign out_uop_dis_col_sel = _GEN_30[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][3:0] _GEN_31 = {{uops_7_br_mask}, {uops_6_br_mask}, {uops_5_br_mask}, {uops_4_br_mask}, {uops_3_br_mask}, {uops_2_br_mask}, {uops_1_br_mask}, {uops_0_br_mask}}; // @[util.scala:505:22, :547:21]
assign out_uop_br_mask = _GEN_31[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][1:0] _GEN_32 = {{uops_7_br_tag}, {uops_6_br_tag}, {uops_5_br_tag}, {uops_4_br_tag}, {uops_3_br_tag}, {uops_2_br_tag}, {uops_1_br_tag}, {uops_0_br_tag}}; // @[util.scala:505:22, :547:21]
assign out_uop_br_tag = _GEN_32[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][3:0] _GEN_33 = {{uops_7_br_type}, {uops_6_br_type}, {uops_5_br_type}, {uops_4_br_type}, {uops_3_br_type}, {uops_2_br_type}, {uops_1_br_type}, {uops_0_br_type}}; // @[util.scala:505:22, :547:21]
assign out_uop_br_type = _GEN_33[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_34 = {{uops_7_is_sfb}, {uops_6_is_sfb}, {uops_5_is_sfb}, {uops_4_is_sfb}, {uops_3_is_sfb}, {uops_2_is_sfb}, {uops_1_is_sfb}, {uops_0_is_sfb}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_sfb = _GEN_34[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_35 = {{uops_7_is_fence}, {uops_6_is_fence}, {uops_5_is_fence}, {uops_4_is_fence}, {uops_3_is_fence}, {uops_2_is_fence}, {uops_1_is_fence}, {uops_0_is_fence}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_fence = _GEN_35[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_36 = {{uops_7_is_fencei}, {uops_6_is_fencei}, {uops_5_is_fencei}, {uops_4_is_fencei}, {uops_3_is_fencei}, {uops_2_is_fencei}, {uops_1_is_fencei}, {uops_0_is_fencei}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_fencei = _GEN_36[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_37 = {{uops_7_is_sfence}, {uops_6_is_sfence}, {uops_5_is_sfence}, {uops_4_is_sfence}, {uops_3_is_sfence}, {uops_2_is_sfence}, {uops_1_is_sfence}, {uops_0_is_sfence}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_sfence = _GEN_37[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_38 = {{uops_7_is_amo}, {uops_6_is_amo}, {uops_5_is_amo}, {uops_4_is_amo}, {uops_3_is_amo}, {uops_2_is_amo}, {uops_1_is_amo}, {uops_0_is_amo}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_amo = _GEN_38[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_39 = {{uops_7_is_eret}, {uops_6_is_eret}, {uops_5_is_eret}, {uops_4_is_eret}, {uops_3_is_eret}, {uops_2_is_eret}, {uops_1_is_eret}, {uops_0_is_eret}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_eret = _GEN_39[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_40 = {{uops_7_is_sys_pc2epc}, {uops_6_is_sys_pc2epc}, {uops_5_is_sys_pc2epc}, {uops_4_is_sys_pc2epc}, {uops_3_is_sys_pc2epc}, {uops_2_is_sys_pc2epc}, {uops_1_is_sys_pc2epc}, {uops_0_is_sys_pc2epc}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_sys_pc2epc = _GEN_40[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_41 = {{uops_7_is_rocc}, {uops_6_is_rocc}, {uops_5_is_rocc}, {uops_4_is_rocc}, {uops_3_is_rocc}, {uops_2_is_rocc}, {uops_1_is_rocc}, {uops_0_is_rocc}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_rocc = _GEN_41[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_42 = {{uops_7_is_mov}, {uops_6_is_mov}, {uops_5_is_mov}, {uops_4_is_mov}, {uops_3_is_mov}, {uops_2_is_mov}, {uops_1_is_mov}, {uops_0_is_mov}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_mov = _GEN_42[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][3:0] _GEN_43 = {{uops_7_ftq_idx}, {uops_6_ftq_idx}, {uops_5_ftq_idx}, {uops_4_ftq_idx}, {uops_3_ftq_idx}, {uops_2_ftq_idx}, {uops_1_ftq_idx}, {uops_0_ftq_idx}}; // @[util.scala:505:22, :547:21]
assign out_uop_ftq_idx = _GEN_43[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_44 = {{uops_7_edge_inst}, {uops_6_edge_inst}, {uops_5_edge_inst}, {uops_4_edge_inst}, {uops_3_edge_inst}, {uops_2_edge_inst}, {uops_1_edge_inst}, {uops_0_edge_inst}}; // @[util.scala:505:22, :547:21]
assign out_uop_edge_inst = _GEN_44[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][5:0] _GEN_45 = {{uops_7_pc_lob}, {uops_6_pc_lob}, {uops_5_pc_lob}, {uops_4_pc_lob}, {uops_3_pc_lob}, {uops_2_pc_lob}, {uops_1_pc_lob}, {uops_0_pc_lob}}; // @[util.scala:505:22, :547:21]
assign out_uop_pc_lob = _GEN_45[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_46 = {{uops_7_taken}, {uops_6_taken}, {uops_5_taken}, {uops_4_taken}, {uops_3_taken}, {uops_2_taken}, {uops_1_taken}, {uops_0_taken}}; // @[util.scala:505:22, :547:21]
assign out_uop_taken = _GEN_46[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_47 = {{uops_7_imm_rename}, {uops_6_imm_rename}, {uops_5_imm_rename}, {uops_4_imm_rename}, {uops_3_imm_rename}, {uops_2_imm_rename}, {uops_1_imm_rename}, {uops_0_imm_rename}}; // @[util.scala:505:22, :547:21]
assign out_uop_imm_rename = _GEN_47[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][2:0] _GEN_48 = {{uops_7_imm_sel}, {uops_6_imm_sel}, {uops_5_imm_sel}, {uops_4_imm_sel}, {uops_3_imm_sel}, {uops_2_imm_sel}, {uops_1_imm_sel}, {uops_0_imm_sel}}; // @[util.scala:505:22, :547:21]
assign out_uop_imm_sel = _GEN_48[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][4:0] _GEN_49 = {{uops_7_pimm}, {uops_6_pimm}, {uops_5_pimm}, {uops_4_pimm}, {uops_3_pimm}, {uops_2_pimm}, {uops_1_pimm}, {uops_0_pimm}}; // @[util.scala:505:22, :547:21]
assign out_uop_pimm = _GEN_49[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][19:0] _GEN_50 = {{uops_7_imm_packed}, {uops_6_imm_packed}, {uops_5_imm_packed}, {uops_4_imm_packed}, {uops_3_imm_packed}, {uops_2_imm_packed}, {uops_1_imm_packed}, {uops_0_imm_packed}}; // @[util.scala:505:22, :547:21]
assign out_uop_imm_packed = _GEN_50[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][1:0] _GEN_51 = {{uops_7_op1_sel}, {uops_6_op1_sel}, {uops_5_op1_sel}, {uops_4_op1_sel}, {uops_3_op1_sel}, {uops_2_op1_sel}, {uops_1_op1_sel}, {uops_0_op1_sel}}; // @[util.scala:505:22, :547:21]
assign out_uop_op1_sel = _GEN_51[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][2:0] _GEN_52 = {{uops_7_op2_sel}, {uops_6_op2_sel}, {uops_5_op2_sel}, {uops_4_op2_sel}, {uops_3_op2_sel}, {uops_2_op2_sel}, {uops_1_op2_sel}, {uops_0_op2_sel}}; // @[util.scala:505:22, :547:21]
assign out_uop_op2_sel = _GEN_52[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_53 = {{uops_7_fp_ctrl_ldst}, {uops_6_fp_ctrl_ldst}, {uops_5_fp_ctrl_ldst}, {uops_4_fp_ctrl_ldst}, {uops_3_fp_ctrl_ldst}, {uops_2_fp_ctrl_ldst}, {uops_1_fp_ctrl_ldst}, {uops_0_fp_ctrl_ldst}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_ldst = _GEN_53[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_54 = {{uops_7_fp_ctrl_wen}, {uops_6_fp_ctrl_wen}, {uops_5_fp_ctrl_wen}, {uops_4_fp_ctrl_wen}, {uops_3_fp_ctrl_wen}, {uops_2_fp_ctrl_wen}, {uops_1_fp_ctrl_wen}, {uops_0_fp_ctrl_wen}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_wen = _GEN_54[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_55 = {{uops_7_fp_ctrl_ren1}, {uops_6_fp_ctrl_ren1}, {uops_5_fp_ctrl_ren1}, {uops_4_fp_ctrl_ren1}, {uops_3_fp_ctrl_ren1}, {uops_2_fp_ctrl_ren1}, {uops_1_fp_ctrl_ren1}, {uops_0_fp_ctrl_ren1}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_ren1 = _GEN_55[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_56 = {{uops_7_fp_ctrl_ren2}, {uops_6_fp_ctrl_ren2}, {uops_5_fp_ctrl_ren2}, {uops_4_fp_ctrl_ren2}, {uops_3_fp_ctrl_ren2}, {uops_2_fp_ctrl_ren2}, {uops_1_fp_ctrl_ren2}, {uops_0_fp_ctrl_ren2}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_ren2 = _GEN_56[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_57 = {{uops_7_fp_ctrl_ren3}, {uops_6_fp_ctrl_ren3}, {uops_5_fp_ctrl_ren3}, {uops_4_fp_ctrl_ren3}, {uops_3_fp_ctrl_ren3}, {uops_2_fp_ctrl_ren3}, {uops_1_fp_ctrl_ren3}, {uops_0_fp_ctrl_ren3}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_ren3 = _GEN_57[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_58 = {{uops_7_fp_ctrl_swap12}, {uops_6_fp_ctrl_swap12}, {uops_5_fp_ctrl_swap12}, {uops_4_fp_ctrl_swap12}, {uops_3_fp_ctrl_swap12}, {uops_2_fp_ctrl_swap12}, {uops_1_fp_ctrl_swap12}, {uops_0_fp_ctrl_swap12}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_swap12 = _GEN_58[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_59 = {{uops_7_fp_ctrl_swap23}, {uops_6_fp_ctrl_swap23}, {uops_5_fp_ctrl_swap23}, {uops_4_fp_ctrl_swap23}, {uops_3_fp_ctrl_swap23}, {uops_2_fp_ctrl_swap23}, {uops_1_fp_ctrl_swap23}, {uops_0_fp_ctrl_swap23}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_swap23 = _GEN_59[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][1:0] _GEN_60 = {{uops_7_fp_ctrl_typeTagIn}, {uops_6_fp_ctrl_typeTagIn}, {uops_5_fp_ctrl_typeTagIn}, {uops_4_fp_ctrl_typeTagIn}, {uops_3_fp_ctrl_typeTagIn}, {uops_2_fp_ctrl_typeTagIn}, {uops_1_fp_ctrl_typeTagIn}, {uops_0_fp_ctrl_typeTagIn}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_typeTagIn = _GEN_60[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][1:0] _GEN_61 = {{uops_7_fp_ctrl_typeTagOut}, {uops_6_fp_ctrl_typeTagOut}, {uops_5_fp_ctrl_typeTagOut}, {uops_4_fp_ctrl_typeTagOut}, {uops_3_fp_ctrl_typeTagOut}, {uops_2_fp_ctrl_typeTagOut}, {uops_1_fp_ctrl_typeTagOut}, {uops_0_fp_ctrl_typeTagOut}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_typeTagOut = _GEN_61[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_62 = {{uops_7_fp_ctrl_fromint}, {uops_6_fp_ctrl_fromint}, {uops_5_fp_ctrl_fromint}, {uops_4_fp_ctrl_fromint}, {uops_3_fp_ctrl_fromint}, {uops_2_fp_ctrl_fromint}, {uops_1_fp_ctrl_fromint}, {uops_0_fp_ctrl_fromint}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_fromint = _GEN_62[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_63 = {{uops_7_fp_ctrl_toint}, {uops_6_fp_ctrl_toint}, {uops_5_fp_ctrl_toint}, {uops_4_fp_ctrl_toint}, {uops_3_fp_ctrl_toint}, {uops_2_fp_ctrl_toint}, {uops_1_fp_ctrl_toint}, {uops_0_fp_ctrl_toint}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_toint = _GEN_63[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_64 = {{uops_7_fp_ctrl_fastpipe}, {uops_6_fp_ctrl_fastpipe}, {uops_5_fp_ctrl_fastpipe}, {uops_4_fp_ctrl_fastpipe}, {uops_3_fp_ctrl_fastpipe}, {uops_2_fp_ctrl_fastpipe}, {uops_1_fp_ctrl_fastpipe}, {uops_0_fp_ctrl_fastpipe}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_fastpipe = _GEN_64[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_65 = {{uops_7_fp_ctrl_fma}, {uops_6_fp_ctrl_fma}, {uops_5_fp_ctrl_fma}, {uops_4_fp_ctrl_fma}, {uops_3_fp_ctrl_fma}, {uops_2_fp_ctrl_fma}, {uops_1_fp_ctrl_fma}, {uops_0_fp_ctrl_fma}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_fma = _GEN_65[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_66 = {{uops_7_fp_ctrl_div}, {uops_6_fp_ctrl_div}, {uops_5_fp_ctrl_div}, {uops_4_fp_ctrl_div}, {uops_3_fp_ctrl_div}, {uops_2_fp_ctrl_div}, {uops_1_fp_ctrl_div}, {uops_0_fp_ctrl_div}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_div = _GEN_66[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_67 = {{uops_7_fp_ctrl_sqrt}, {uops_6_fp_ctrl_sqrt}, {uops_5_fp_ctrl_sqrt}, {uops_4_fp_ctrl_sqrt}, {uops_3_fp_ctrl_sqrt}, {uops_2_fp_ctrl_sqrt}, {uops_1_fp_ctrl_sqrt}, {uops_0_fp_ctrl_sqrt}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_sqrt = _GEN_67[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_68 = {{uops_7_fp_ctrl_wflags}, {uops_6_fp_ctrl_wflags}, {uops_5_fp_ctrl_wflags}, {uops_4_fp_ctrl_wflags}, {uops_3_fp_ctrl_wflags}, {uops_2_fp_ctrl_wflags}, {uops_1_fp_ctrl_wflags}, {uops_0_fp_ctrl_wflags}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_wflags = _GEN_68[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_69 = {{uops_7_fp_ctrl_vec}, {uops_6_fp_ctrl_vec}, {uops_5_fp_ctrl_vec}, {uops_4_fp_ctrl_vec}, {uops_3_fp_ctrl_vec}, {uops_2_fp_ctrl_vec}, {uops_1_fp_ctrl_vec}, {uops_0_fp_ctrl_vec}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_vec = _GEN_69[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][4:0] _GEN_70 = {{uops_7_rob_idx}, {uops_6_rob_idx}, {uops_5_rob_idx}, {uops_4_rob_idx}, {uops_3_rob_idx}, {uops_2_rob_idx}, {uops_1_rob_idx}, {uops_0_rob_idx}}; // @[util.scala:505:22, :547:21]
assign out_uop_rob_idx = _GEN_70[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][3:0] _GEN_71 = {{uops_7_ldq_idx}, {uops_6_ldq_idx}, {uops_5_ldq_idx}, {uops_4_ldq_idx}, {uops_3_ldq_idx}, {uops_2_ldq_idx}, {uops_1_ldq_idx}, {uops_0_ldq_idx}}; // @[util.scala:505:22, :547:21]
assign out_uop_ldq_idx = _GEN_71[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][3:0] _GEN_72 = {{uops_7_stq_idx}, {uops_6_stq_idx}, {uops_5_stq_idx}, {uops_4_stq_idx}, {uops_3_stq_idx}, {uops_2_stq_idx}, {uops_1_stq_idx}, {uops_0_stq_idx}}; // @[util.scala:505:22, :547:21]
assign out_uop_stq_idx = _GEN_72[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][1:0] _GEN_73 = {{uops_7_rxq_idx}, {uops_6_rxq_idx}, {uops_5_rxq_idx}, {uops_4_rxq_idx}, {uops_3_rxq_idx}, {uops_2_rxq_idx}, {uops_1_rxq_idx}, {uops_0_rxq_idx}}; // @[util.scala:505:22, :547:21]
assign out_uop_rxq_idx = _GEN_73[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][5:0] _GEN_74 = {{uops_7_pdst}, {uops_6_pdst}, {uops_5_pdst}, {uops_4_pdst}, {uops_3_pdst}, {uops_2_pdst}, {uops_1_pdst}, {uops_0_pdst}}; // @[util.scala:505:22, :547:21]
assign out_uop_pdst = _GEN_74[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][5:0] _GEN_75 = {{uops_7_prs1}, {uops_6_prs1}, {uops_5_prs1}, {uops_4_prs1}, {uops_3_prs1}, {uops_2_prs1}, {uops_1_prs1}, {uops_0_prs1}}; // @[util.scala:505:22, :547:21]
assign out_uop_prs1 = _GEN_75[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][5:0] _GEN_76 = {{uops_7_prs2}, {uops_6_prs2}, {uops_5_prs2}, {uops_4_prs2}, {uops_3_prs2}, {uops_2_prs2}, {uops_1_prs2}, {uops_0_prs2}}; // @[util.scala:505:22, :547:21]
assign out_uop_prs2 = _GEN_76[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][5:0] _GEN_77 = {{uops_7_prs3}, {uops_6_prs3}, {uops_5_prs3}, {uops_4_prs3}, {uops_3_prs3}, {uops_2_prs3}, {uops_1_prs3}, {uops_0_prs3}}; // @[util.scala:505:22, :547:21]
assign out_uop_prs3 = _GEN_77[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][3:0] _GEN_78 = {{uops_7_ppred}, {uops_6_ppred}, {uops_5_ppred}, {uops_4_ppred}, {uops_3_ppred}, {uops_2_ppred}, {uops_1_ppred}, {uops_0_ppred}}; // @[util.scala:505:22, :547:21]
assign out_uop_ppred = _GEN_78[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_79 = {{uops_7_prs1_busy}, {uops_6_prs1_busy}, {uops_5_prs1_busy}, {uops_4_prs1_busy}, {uops_3_prs1_busy}, {uops_2_prs1_busy}, {uops_1_prs1_busy}, {uops_0_prs1_busy}}; // @[util.scala:505:22, :547:21]
assign out_uop_prs1_busy = _GEN_79[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_80 = {{uops_7_prs2_busy}, {uops_6_prs2_busy}, {uops_5_prs2_busy}, {uops_4_prs2_busy}, {uops_3_prs2_busy}, {uops_2_prs2_busy}, {uops_1_prs2_busy}, {uops_0_prs2_busy}}; // @[util.scala:505:22, :547:21]
assign out_uop_prs2_busy = _GEN_80[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_81 = {{uops_7_prs3_busy}, {uops_6_prs3_busy}, {uops_5_prs3_busy}, {uops_4_prs3_busy}, {uops_3_prs3_busy}, {uops_2_prs3_busy}, {uops_1_prs3_busy}, {uops_0_prs3_busy}}; // @[util.scala:505:22, :547:21]
assign out_uop_prs3_busy = _GEN_81[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_82 = {{uops_7_ppred_busy}, {uops_6_ppred_busy}, {uops_5_ppred_busy}, {uops_4_ppred_busy}, {uops_3_ppred_busy}, {uops_2_ppred_busy}, {uops_1_ppred_busy}, {uops_0_ppred_busy}}; // @[util.scala:505:22, :547:21]
assign out_uop_ppred_busy = _GEN_82[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][5:0] _GEN_83 = {{uops_7_stale_pdst}, {uops_6_stale_pdst}, {uops_5_stale_pdst}, {uops_4_stale_pdst}, {uops_3_stale_pdst}, {uops_2_stale_pdst}, {uops_1_stale_pdst}, {uops_0_stale_pdst}}; // @[util.scala:505:22, :547:21]
assign out_uop_stale_pdst = _GEN_83[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_84 = {{uops_7_exception}, {uops_6_exception}, {uops_5_exception}, {uops_4_exception}, {uops_3_exception}, {uops_2_exception}, {uops_1_exception}, {uops_0_exception}}; // @[util.scala:505:22, :547:21]
assign out_uop_exception = _GEN_84[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][63:0] _GEN_85 = {{uops_7_exc_cause}, {uops_6_exc_cause}, {uops_5_exc_cause}, {uops_4_exc_cause}, {uops_3_exc_cause}, {uops_2_exc_cause}, {uops_1_exc_cause}, {uops_0_exc_cause}}; // @[util.scala:505:22, :547:21]
assign out_uop_exc_cause = _GEN_85[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][4:0] _GEN_86 = {{uops_7_mem_cmd}, {uops_6_mem_cmd}, {uops_5_mem_cmd}, {uops_4_mem_cmd}, {uops_3_mem_cmd}, {uops_2_mem_cmd}, {uops_1_mem_cmd}, {uops_0_mem_cmd}}; // @[util.scala:505:22, :547:21]
assign out_uop_mem_cmd = _GEN_86[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][1:0] _GEN_87 = {{uops_7_mem_size}, {uops_6_mem_size}, {uops_5_mem_size}, {uops_4_mem_size}, {uops_3_mem_size}, {uops_2_mem_size}, {uops_1_mem_size}, {uops_0_mem_size}}; // @[util.scala:505:22, :547:21]
assign out_uop_mem_size = _GEN_87[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_88 = {{uops_7_mem_signed}, {uops_6_mem_signed}, {uops_5_mem_signed}, {uops_4_mem_signed}, {uops_3_mem_signed}, {uops_2_mem_signed}, {uops_1_mem_signed}, {uops_0_mem_signed}}; // @[util.scala:505:22, :547:21]
assign out_uop_mem_signed = _GEN_88[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_89 = {{uops_7_uses_ldq}, {uops_6_uses_ldq}, {uops_5_uses_ldq}, {uops_4_uses_ldq}, {uops_3_uses_ldq}, {uops_2_uses_ldq}, {uops_1_uses_ldq}, {uops_0_uses_ldq}}; // @[util.scala:505:22, :547:21]
assign out_uop_uses_ldq = _GEN_89[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_90 = {{uops_7_uses_stq}, {uops_6_uses_stq}, {uops_5_uses_stq}, {uops_4_uses_stq}, {uops_3_uses_stq}, {uops_2_uses_stq}, {uops_1_uses_stq}, {uops_0_uses_stq}}; // @[util.scala:505:22, :547:21]
assign out_uop_uses_stq = _GEN_90[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_91 = {{uops_7_is_unique}, {uops_6_is_unique}, {uops_5_is_unique}, {uops_4_is_unique}, {uops_3_is_unique}, {uops_2_is_unique}, {uops_1_is_unique}, {uops_0_is_unique}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_unique = _GEN_91[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_92 = {{uops_7_flush_on_commit}, {uops_6_flush_on_commit}, {uops_5_flush_on_commit}, {uops_4_flush_on_commit}, {uops_3_flush_on_commit}, {uops_2_flush_on_commit}, {uops_1_flush_on_commit}, {uops_0_flush_on_commit}}; // @[util.scala:505:22, :547:21]
assign out_uop_flush_on_commit = _GEN_92[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][2:0] _GEN_93 = {{uops_7_csr_cmd}, {uops_6_csr_cmd}, {uops_5_csr_cmd}, {uops_4_csr_cmd}, {uops_3_csr_cmd}, {uops_2_csr_cmd}, {uops_1_csr_cmd}, {uops_0_csr_cmd}}; // @[util.scala:505:22, :547:21]
assign out_uop_csr_cmd = _GEN_93[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_94 = {{uops_7_ldst_is_rs1}, {uops_6_ldst_is_rs1}, {uops_5_ldst_is_rs1}, {uops_4_ldst_is_rs1}, {uops_3_ldst_is_rs1}, {uops_2_ldst_is_rs1}, {uops_1_ldst_is_rs1}, {uops_0_ldst_is_rs1}}; // @[util.scala:505:22, :547:21]
assign out_uop_ldst_is_rs1 = _GEN_94[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][5:0] _GEN_95 = {{uops_7_ldst}, {uops_6_ldst}, {uops_5_ldst}, {uops_4_ldst}, {uops_3_ldst}, {uops_2_ldst}, {uops_1_ldst}, {uops_0_ldst}}; // @[util.scala:505:22, :547:21]
assign out_uop_ldst = _GEN_95[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][5:0] _GEN_96 = {{uops_7_lrs1}, {uops_6_lrs1}, {uops_5_lrs1}, {uops_4_lrs1}, {uops_3_lrs1}, {uops_2_lrs1}, {uops_1_lrs1}, {uops_0_lrs1}}; // @[util.scala:505:22, :547:21]
assign out_uop_lrs1 = _GEN_96[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][5:0] _GEN_97 = {{uops_7_lrs2}, {uops_6_lrs2}, {uops_5_lrs2}, {uops_4_lrs2}, {uops_3_lrs2}, {uops_2_lrs2}, {uops_1_lrs2}, {uops_0_lrs2}}; // @[util.scala:505:22, :547:21]
assign out_uop_lrs2 = _GEN_97[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][5:0] _GEN_98 = {{uops_7_lrs3}, {uops_6_lrs3}, {uops_5_lrs3}, {uops_4_lrs3}, {uops_3_lrs3}, {uops_2_lrs3}, {uops_1_lrs3}, {uops_0_lrs3}}; // @[util.scala:505:22, :547:21]
assign out_uop_lrs3 = _GEN_98[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][1:0] _GEN_99 = {{uops_7_dst_rtype}, {uops_6_dst_rtype}, {uops_5_dst_rtype}, {uops_4_dst_rtype}, {uops_3_dst_rtype}, {uops_2_dst_rtype}, {uops_1_dst_rtype}, {uops_0_dst_rtype}}; // @[util.scala:505:22, :547:21]
assign out_uop_dst_rtype = _GEN_99[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][1:0] _GEN_100 = {{uops_7_lrs1_rtype}, {uops_6_lrs1_rtype}, {uops_5_lrs1_rtype}, {uops_4_lrs1_rtype}, {uops_3_lrs1_rtype}, {uops_2_lrs1_rtype}, {uops_1_lrs1_rtype}, {uops_0_lrs1_rtype}}; // @[util.scala:505:22, :547:21]
assign out_uop_lrs1_rtype = _GEN_100[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][1:0] _GEN_101 = {{uops_7_lrs2_rtype}, {uops_6_lrs2_rtype}, {uops_5_lrs2_rtype}, {uops_4_lrs2_rtype}, {uops_3_lrs2_rtype}, {uops_2_lrs2_rtype}, {uops_1_lrs2_rtype}, {uops_0_lrs2_rtype}}; // @[util.scala:505:22, :547:21]
assign out_uop_lrs2_rtype = _GEN_101[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_102 = {{uops_7_frs3_en}, {uops_6_frs3_en}, {uops_5_frs3_en}, {uops_4_frs3_en}, {uops_3_frs3_en}, {uops_2_frs3_en}, {uops_1_frs3_en}, {uops_0_frs3_en}}; // @[util.scala:505:22, :547:21]
assign out_uop_frs3_en = _GEN_102[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_103 = {{uops_7_fcn_dw}, {uops_6_fcn_dw}, {uops_5_fcn_dw}, {uops_4_fcn_dw}, {uops_3_fcn_dw}, {uops_2_fcn_dw}, {uops_1_fcn_dw}, {uops_0_fcn_dw}}; // @[util.scala:505:22, :547:21]
assign out_uop_fcn_dw = _GEN_103[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][4:0] _GEN_104 = {{uops_7_fcn_op}, {uops_6_fcn_op}, {uops_5_fcn_op}, {uops_4_fcn_op}, {uops_3_fcn_op}, {uops_2_fcn_op}, {uops_1_fcn_op}, {uops_0_fcn_op}}; // @[util.scala:505:22, :547:21]
assign out_uop_fcn_op = _GEN_104[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_105 = {{uops_7_fp_val}, {uops_6_fp_val}, {uops_5_fp_val}, {uops_4_fp_val}, {uops_3_fp_val}, {uops_2_fp_val}, {uops_1_fp_val}, {uops_0_fp_val}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_val = _GEN_105[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][2:0] _GEN_106 = {{uops_7_fp_rm}, {uops_6_fp_rm}, {uops_5_fp_rm}, {uops_4_fp_rm}, {uops_3_fp_rm}, {uops_2_fp_rm}, {uops_1_fp_rm}, {uops_0_fp_rm}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_rm = _GEN_106[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][1:0] _GEN_107 = {{uops_7_fp_typ}, {uops_6_fp_typ}, {uops_5_fp_typ}, {uops_4_fp_typ}, {uops_3_fp_typ}, {uops_2_fp_typ}, {uops_1_fp_typ}, {uops_0_fp_typ}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_typ = _GEN_107[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_108 = {{uops_7_xcpt_pf_if}, {uops_6_xcpt_pf_if}, {uops_5_xcpt_pf_if}, {uops_4_xcpt_pf_if}, {uops_3_xcpt_pf_if}, {uops_2_xcpt_pf_if}, {uops_1_xcpt_pf_if}, {uops_0_xcpt_pf_if}}; // @[util.scala:505:22, :547:21]
assign out_uop_xcpt_pf_if = _GEN_108[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_109 = {{uops_7_xcpt_ae_if}, {uops_6_xcpt_ae_if}, {uops_5_xcpt_ae_if}, {uops_4_xcpt_ae_if}, {uops_3_xcpt_ae_if}, {uops_2_xcpt_ae_if}, {uops_1_xcpt_ae_if}, {uops_0_xcpt_ae_if}}; // @[util.scala:505:22, :547:21]
assign out_uop_xcpt_ae_if = _GEN_109[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_110 = {{uops_7_xcpt_ma_if}, {uops_6_xcpt_ma_if}, {uops_5_xcpt_ma_if}, {uops_4_xcpt_ma_if}, {uops_3_xcpt_ma_if}, {uops_2_xcpt_ma_if}, {uops_1_xcpt_ma_if}, {uops_0_xcpt_ma_if}}; // @[util.scala:505:22, :547:21]
assign out_uop_xcpt_ma_if = _GEN_110[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_111 = {{uops_7_bp_debug_if}, {uops_6_bp_debug_if}, {uops_5_bp_debug_if}, {uops_4_bp_debug_if}, {uops_3_bp_debug_if}, {uops_2_bp_debug_if}, {uops_1_bp_debug_if}, {uops_0_bp_debug_if}}; // @[util.scala:505:22, :547:21]
assign out_uop_bp_debug_if = _GEN_111[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_112 = {{uops_7_bp_xcpt_if}, {uops_6_bp_xcpt_if}, {uops_5_bp_xcpt_if}, {uops_4_bp_xcpt_if}, {uops_3_bp_xcpt_if}, {uops_2_bp_xcpt_if}, {uops_1_bp_xcpt_if}, {uops_0_bp_xcpt_if}}; // @[util.scala:505:22, :547:21]
assign out_uop_bp_xcpt_if = _GEN_112[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][2:0] _GEN_113 = {{uops_7_debug_fsrc}, {uops_6_debug_fsrc}, {uops_5_debug_fsrc}, {uops_4_debug_fsrc}, {uops_3_debug_fsrc}, {uops_2_debug_fsrc}, {uops_1_debug_fsrc}, {uops_0_debug_fsrc}}; // @[util.scala:505:22, :547:21]
assign out_uop_debug_fsrc = _GEN_113[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][2:0] _GEN_114 = {{uops_7_debug_tsrc}, {uops_6_debug_tsrc}, {uops_5_debug_tsrc}, {uops_4_debug_tsrc}, {uops_3_debug_tsrc}, {uops_2_debug_tsrc}, {uops_1_debug_tsrc}, {uops_0_debug_tsrc}}; // @[util.scala:505:22, :547:21]
assign out_uop_debug_tsrc = _GEN_114[deq_ptr_value]; // @[Counter.scala:61:40]
wire _io_deq_valid_T = ~io_empty; // @[util.scala:458:7, :515:71, :548:32]
assign _io_deq_valid_T_1 = _io_deq_valid_T & _GEN_1; // @[util.scala:515:44, :548:{32,42}]
assign io_deq_valid_0 = _io_deq_valid_T_1; // @[util.scala:458:7, :548:42]
wire [3:0] _ptr_diff_T = _GEN_2 - _GEN_3; // @[Counter.scala:77:24]
wire [2:0] ptr_diff = _ptr_diff_T[2:0]; // @[util.scala:551:34]
wire [3:0] _io_count_T_1 = {_io_count_T, ptr_diff}; // @[util.scala:551:34, :553:{22,34}]
assign io_count = _io_count_T_1[2:0]; // @[util.scala:458:7, :553:{16,22}]
wire _GEN_115 = enq_ptr_value == 3'h0; // @[Counter.scala:61:40]
wire _GEN_116 = do_enq & _GEN_115; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_117 = enq_ptr_value == 3'h1; // @[Counter.scala:61:40]
wire _GEN_118 = do_enq & _GEN_117; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_119 = enq_ptr_value == 3'h2; // @[Counter.scala:61:40]
wire _GEN_120 = do_enq & _GEN_119; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_121 = enq_ptr_value == 3'h3; // @[Counter.scala:61:40]
wire _GEN_122 = do_enq & _GEN_121; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_123 = enq_ptr_value == 3'h4; // @[Counter.scala:61:40]
wire _GEN_124 = do_enq & _GEN_123; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_125 = enq_ptr_value == 3'h5; // @[Counter.scala:61:40]
wire _GEN_126 = do_enq & _GEN_125; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_127 = enq_ptr_value == 3'h6; // @[Counter.scala:61:40]
wire _GEN_128 = do_enq & _GEN_127; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_129 = do_enq & (&enq_ptr_value); // @[Counter.scala:61:40]
always @(posedge clock) begin // @[util.scala:458:7]
if (reset) begin // @[util.scala:458:7]
valids_0 <= 1'h0; // @[util.scala:504:26]
valids_1 <= 1'h0; // @[util.scala:504:26]
valids_2 <= 1'h0; // @[util.scala:504:26]
valids_3 <= 1'h0; // @[util.scala:504:26]
valids_4 <= 1'h0; // @[util.scala:504:26]
valids_5 <= 1'h0; // @[util.scala:504:26]
valids_6 <= 1'h0; // @[util.scala:504:26]
valids_7 <= 1'h0; // @[util.scala:504:26]
enq_ptr_value <= 3'h0; // @[Counter.scala:61:40]
deq_ptr_value <= 3'h0; // @[Counter.scala:61:40]
maybe_full <= 1'h0; // @[util.scala:509:29]
end
else begin // @[util.scala:458:7]
valids_0 <= ~(do_deq & deq_ptr_value == 3'h0) & (_GEN_116 | _valids_0_T_7); // @[Counter.scala:61:40]
valids_1 <= ~(do_deq & deq_ptr_value == 3'h1) & (_GEN_118 | _valids_1_T_7); // @[Counter.scala:61:40]
valids_2 <= ~(do_deq & deq_ptr_value == 3'h2) & (_GEN_120 | _valids_2_T_7); // @[Counter.scala:61:40]
valids_3 <= ~(do_deq & deq_ptr_value == 3'h3) & (_GEN_122 | _valids_3_T_7); // @[Counter.scala:61:40]
valids_4 <= ~(do_deq & deq_ptr_value == 3'h4) & (_GEN_124 | _valids_4_T_7); // @[Counter.scala:61:40]
valids_5 <= ~(do_deq & deq_ptr_value == 3'h5) & (_GEN_126 | _valids_5_T_7); // @[Counter.scala:61:40]
valids_6 <= ~(do_deq & deq_ptr_value == 3'h6) & (_GEN_128 | _valids_6_T_7); // @[Counter.scala:61:40]
valids_7 <= ~(do_deq & (&deq_ptr_value)) & (_GEN_129 | _valids_7_T_7); // @[Counter.scala:61:40]
if (do_enq) // @[util.scala:514:26]
enq_ptr_value <= _value_T_1; // @[Counter.scala:61:40, :77:24]
if (do_deq) // @[util.scala:515:26]
deq_ptr_value <= _value_T_3; // @[Counter.scala:61:40, :77:24]
if (~(do_enq == do_deq)) // @[util.scala:509:29, :514:26, :515:26, :539:{18,30}, :540:18]
maybe_full <= do_enq; // @[util.scala:509:29, :514:26]
end
if (_GEN_116) begin // @[util.scala:520:18, :526:19, :528:35]
uops_0_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_0_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_0_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_0_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_0_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_0_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_0_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_0_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_0_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_0_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_0_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_0_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_0_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_0_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_0_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_0_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_0_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_0_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_0_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_0_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_0_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_0_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_0_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_0_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_0_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_0_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_0_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_0_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_0_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_0_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_0_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_0_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_0_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_0_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_0_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_0_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_0_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_0_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_0_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_0_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_0_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_0_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_0_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_0_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_0_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_0_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_0_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_0_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_0_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_0_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_0_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_0_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_0_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_0_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_0_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_0_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_0_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_0_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_0_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_0_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_0_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_0_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_0_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_0_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_0_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_0_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_0_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_0_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_0_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_0_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_0_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_0_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_0_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_0_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_0_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_0_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_0_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_0_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_0_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_0_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_0_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_0_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_0_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_115) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_0_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_0) // @[util.scala:504:26]
uops_0_br_mask <= _uops_0_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_118) begin // @[util.scala:520:18, :526:19, :528:35]
uops_1_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_1_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_1_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_1_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_1_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_1_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_1_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_1_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_1_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_1_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_1_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_1_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_1_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_1_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_1_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_1_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_1_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_1_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_1_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_1_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_1_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_1_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_1_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_1_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_1_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_1_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_1_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_1_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_1_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_1_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_1_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_1_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_1_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_1_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_1_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_1_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_1_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_1_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_1_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_1_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_1_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_1_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_1_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_1_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_1_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_1_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_1_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_1_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_1_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_1_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_1_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_1_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_1_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_1_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_1_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_1_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_1_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_1_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_1_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_1_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_1_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_1_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_1_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_1_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_1_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_1_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_1_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_1_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_1_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_1_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_1_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_1_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_1_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_1_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_1_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_1_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_1_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_1_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_1_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_1_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_1_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_1_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_1_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_117) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_1_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_1) // @[util.scala:504:26]
uops_1_br_mask <= _uops_1_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_120) begin // @[util.scala:520:18, :526:19, :528:35]
uops_2_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_2_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_2_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_2_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_2_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_2_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_2_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_2_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_2_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_2_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_2_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_2_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_2_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_2_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_2_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_2_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_2_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_2_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_2_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_2_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_2_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_2_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_2_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_2_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_2_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_2_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_2_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_2_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_2_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_2_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_2_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_2_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_2_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_2_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_2_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_2_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_2_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_2_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_2_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_2_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_2_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_2_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_2_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_2_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_2_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_2_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_2_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_2_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_2_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_2_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_2_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_2_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_2_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_2_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_2_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_2_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_2_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_2_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_2_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_2_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_2_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_2_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_2_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_2_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_2_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_2_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_2_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_2_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_2_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_2_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_2_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_2_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_2_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_2_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_2_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_2_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_2_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_2_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_2_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_2_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_2_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_2_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_2_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_119) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_2_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_2) // @[util.scala:504:26]
uops_2_br_mask <= _uops_2_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_122) begin // @[util.scala:520:18, :526:19, :528:35]
uops_3_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_3_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_3_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_3_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_3_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_3_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_3_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_3_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_3_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_3_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_3_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_3_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_3_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_3_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_3_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_3_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_3_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_3_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_3_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_3_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_3_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_3_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_3_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_3_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_3_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_3_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_3_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_3_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_3_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_3_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_3_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_3_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_3_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_3_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_3_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_3_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_3_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_3_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_3_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_3_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_3_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_3_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_3_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_3_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_3_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_3_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_3_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_3_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_3_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_3_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_3_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_3_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_3_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_3_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_3_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_3_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_3_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_3_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_3_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_3_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_3_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_3_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_3_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_3_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_3_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_3_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_3_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_3_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_3_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_3_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_3_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_3_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_3_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_3_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_3_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_3_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_3_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_3_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_3_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_3_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_3_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_3_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_3_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_121) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_3_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_3) // @[util.scala:504:26]
uops_3_br_mask <= _uops_3_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_124) begin // @[util.scala:520:18, :526:19, :528:35]
uops_4_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_4_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_4_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_4_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_4_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_4_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_4_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_4_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_4_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_4_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_4_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_4_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_4_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_4_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_4_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_4_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_4_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_4_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_4_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_4_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_4_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_4_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_4_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_4_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_4_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_4_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_4_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_4_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_4_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_4_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_4_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_4_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_4_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_4_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_4_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_4_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_4_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_4_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_4_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_4_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_4_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_4_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_4_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_4_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_4_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_4_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_4_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_4_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_4_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_4_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_4_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_4_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_4_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_4_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_4_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_4_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_4_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_4_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_4_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_4_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_4_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_4_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_4_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_4_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_4_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_4_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_4_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_4_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_4_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_4_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_4_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_4_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_4_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_4_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_4_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_4_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_4_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_4_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_4_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_4_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_4_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_4_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_4_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_123) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_4_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_4) // @[util.scala:504:26]
uops_4_br_mask <= _uops_4_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_126) begin // @[util.scala:520:18, :526:19, :528:35]
uops_5_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_5_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_5_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_5_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_5_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_5_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_5_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_5_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_5_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_5_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_5_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_5_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_5_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_5_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_5_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_5_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_5_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_5_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_5_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_5_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_5_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_5_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_5_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_5_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_5_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_5_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_5_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_5_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_5_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_5_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_5_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_5_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_5_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_5_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_5_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_5_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_5_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_5_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_5_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_5_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_5_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_5_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_5_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_5_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_5_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_5_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_5_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_5_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_5_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_5_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_5_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_5_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_5_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_5_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_5_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_5_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_5_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_5_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_5_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_5_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_5_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_5_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_5_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_5_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_5_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_5_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_5_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_5_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_5_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_5_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_5_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_5_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_5_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_5_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_5_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_5_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_5_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_5_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_5_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_5_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_5_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_5_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_5_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_125) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_5_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_5) // @[util.scala:504:26]
uops_5_br_mask <= _uops_5_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_128) begin // @[util.scala:520:18, :526:19, :528:35]
uops_6_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_6_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_6_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_6_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_6_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_6_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_6_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_6_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_6_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_6_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_6_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_6_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_6_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_6_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_6_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_6_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_6_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_6_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_6_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_6_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_6_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_6_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_6_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_6_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_6_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_6_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_6_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_6_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_6_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_6_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_6_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_6_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_6_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_6_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_6_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_6_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_6_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_6_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_6_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_6_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_6_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_6_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_6_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_6_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_6_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_6_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_6_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_6_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_6_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_6_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_6_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_6_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_6_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_6_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_6_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_6_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_6_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_6_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_6_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_6_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_6_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_6_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_6_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_6_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_6_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_6_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_6_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_6_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_6_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_6_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_6_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_6_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_6_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_6_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_6_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_6_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_6_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_6_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_6_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_6_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_6_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_6_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_6_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_127) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_6_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_6) // @[util.scala:504:26]
uops_6_br_mask <= _uops_6_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_129) begin // @[util.scala:520:18, :526:19, :528:35]
uops_7_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_7_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_7_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_7_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_7_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_7_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_7_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_7_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_7_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_7_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_7_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_7_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_7_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_7_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_7_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_7_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_7_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_7_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_7_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_7_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_7_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_7_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_7_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_7_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_7_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_7_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_7_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_7_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_7_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_7_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_7_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_7_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_7_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_7_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_7_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_7_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_7_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_7_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_7_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_7_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_7_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_7_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_7_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_7_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_7_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_7_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_7_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_7_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_7_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_7_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_7_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_7_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_7_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_7_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_7_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_7_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_7_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_7_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_7_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_7_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_7_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_7_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_7_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_7_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_7_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_7_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_7_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_7_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_7_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_7_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_7_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_7_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_7_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_7_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_7_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_7_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_7_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_7_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_7_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_7_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_7_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_7_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_7_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & (&enq_ptr_value)) // @[Counter.scala:61:40]
uops_7_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_7) // @[util.scala:504:26]
uops_7_br_mask <= _uops_7_br_mask_T_1; // @[util.scala:97:21, :505:22]
always @(posedge)
ram_8x64 ram_ext ( // @[util.scala:503:22]
.R0_addr (deq_ptr_value), // @[Counter.scala:61:40]
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (out_data),
.W0_addr (enq_ptr_value), // @[Counter.scala:61:40]
.W0_en (do_enq), // @[util.scala:514:26]
.W0_clk (clock),
.W0_data (io_enq_bits_data_0) // @[util.scala:458:7]
); // @[util.scala:503:22]
assign io_enq_ready = io_enq_ready_0; // @[util.scala:458:7]
assign io_deq_valid = io_deq_valid_0; // @[util.scala:458:7]
assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_0 = io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_1 = io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_2 = io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_3 = io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_0 = io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_1 = io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_2 = io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_3 = io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_4 = io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_5 = io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_6 = io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_7 = io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_8 = io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_9 = io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_issued = io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_issued_partial_agen = io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_issued_partial_dgen = io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p1_speculative_child = io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p2_speculative_child = io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p1_bypass_hint = io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p2_bypass_hint = io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p3_bypass_hint = io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_dis_col_sel = io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:458:7]
assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:458:7]
assign io_deq_bits_uop_br_type = io_deq_bits_uop_br_type_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_sfence = io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_eret = io_deq_bits_uop_is_eret_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_rocc = io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_mov = io_deq_bits_uop_is_mov_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7]
assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:458:7]
assign io_deq_bits_uop_imm_rename = io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7]
assign io_deq_bits_uop_imm_sel = io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_pimm = io_deq_bits_uop_pimm_0; // @[util.scala:458:7]
assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7]
assign io_deq_bits_uop_op1_sel = io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_op2_sel = io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ldst = io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_wen = io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ren1 = io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ren2 = io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ren3 = io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_swap12 = io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_swap23 = io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_typeTagIn = io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_typeTagOut = io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_fromint = io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_toint = io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_fastpipe = io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_fma = io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_div = io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_sqrt = io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_wflags = io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_vec = io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7]
assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:458:7]
assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7]
assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7]
assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:458:7]
assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7]
assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7]
assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:458:7]
assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7]
assign io_deq_bits_uop_csr_cmd = io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7]
assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fcn_dw = io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fcn_op = io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_rm = io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_typ = io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7]
assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7]
assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:458:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_133 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_229
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_133( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_229 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MulRecFN_53 :
output io : { flip a : UInt<33>, flip b : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
inst mulRawFN of MulRawFN_53
node mulRawFN_io_a_exp = bits(io.a, 31, 23)
node _mulRawFN_io_a_isZero_T = bits(mulRawFN_io_a_exp, 8, 6)
node mulRawFN_io_a_isZero = eq(_mulRawFN_io_a_isZero_T, UInt<1>(0h0))
node _mulRawFN_io_a_isSpecial_T = bits(mulRawFN_io_a_exp, 8, 7)
node mulRawFN_io_a_isSpecial = eq(_mulRawFN_io_a_isSpecial_T, UInt<2>(0h3))
wire mulRawFN_io_a_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _mulRawFN_io_a_out_isNaN_T = bits(mulRawFN_io_a_exp, 6, 6)
node _mulRawFN_io_a_out_isNaN_T_1 = and(mulRawFN_io_a_isSpecial, _mulRawFN_io_a_out_isNaN_T)
connect mulRawFN_io_a_out.isNaN, _mulRawFN_io_a_out_isNaN_T_1
node _mulRawFN_io_a_out_isInf_T = bits(mulRawFN_io_a_exp, 6, 6)
node _mulRawFN_io_a_out_isInf_T_1 = eq(_mulRawFN_io_a_out_isInf_T, UInt<1>(0h0))
node _mulRawFN_io_a_out_isInf_T_2 = and(mulRawFN_io_a_isSpecial, _mulRawFN_io_a_out_isInf_T_1)
connect mulRawFN_io_a_out.isInf, _mulRawFN_io_a_out_isInf_T_2
connect mulRawFN_io_a_out.isZero, mulRawFN_io_a_isZero
node _mulRawFN_io_a_out_sign_T = bits(io.a, 32, 32)
connect mulRawFN_io_a_out.sign, _mulRawFN_io_a_out_sign_T
node _mulRawFN_io_a_out_sExp_T = cvt(mulRawFN_io_a_exp)
connect mulRawFN_io_a_out.sExp, _mulRawFN_io_a_out_sExp_T
node _mulRawFN_io_a_out_sig_T = eq(mulRawFN_io_a_isZero, UInt<1>(0h0))
node _mulRawFN_io_a_out_sig_T_1 = cat(UInt<1>(0h0), _mulRawFN_io_a_out_sig_T)
node _mulRawFN_io_a_out_sig_T_2 = bits(io.a, 22, 0)
node _mulRawFN_io_a_out_sig_T_3 = cat(_mulRawFN_io_a_out_sig_T_1, _mulRawFN_io_a_out_sig_T_2)
connect mulRawFN_io_a_out.sig, _mulRawFN_io_a_out_sig_T_3
connect mulRawFN.io.a.sig, mulRawFN_io_a_out.sig
connect mulRawFN.io.a.sExp, mulRawFN_io_a_out.sExp
connect mulRawFN.io.a.sign, mulRawFN_io_a_out.sign
connect mulRawFN.io.a.isZero, mulRawFN_io_a_out.isZero
connect mulRawFN.io.a.isInf, mulRawFN_io_a_out.isInf
connect mulRawFN.io.a.isNaN, mulRawFN_io_a_out.isNaN
node mulRawFN_io_b_exp = bits(io.b, 31, 23)
node _mulRawFN_io_b_isZero_T = bits(mulRawFN_io_b_exp, 8, 6)
node mulRawFN_io_b_isZero = eq(_mulRawFN_io_b_isZero_T, UInt<1>(0h0))
node _mulRawFN_io_b_isSpecial_T = bits(mulRawFN_io_b_exp, 8, 7)
node mulRawFN_io_b_isSpecial = eq(_mulRawFN_io_b_isSpecial_T, UInt<2>(0h3))
wire mulRawFN_io_b_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _mulRawFN_io_b_out_isNaN_T = bits(mulRawFN_io_b_exp, 6, 6)
node _mulRawFN_io_b_out_isNaN_T_1 = and(mulRawFN_io_b_isSpecial, _mulRawFN_io_b_out_isNaN_T)
connect mulRawFN_io_b_out.isNaN, _mulRawFN_io_b_out_isNaN_T_1
node _mulRawFN_io_b_out_isInf_T = bits(mulRawFN_io_b_exp, 6, 6)
node _mulRawFN_io_b_out_isInf_T_1 = eq(_mulRawFN_io_b_out_isInf_T, UInt<1>(0h0))
node _mulRawFN_io_b_out_isInf_T_2 = and(mulRawFN_io_b_isSpecial, _mulRawFN_io_b_out_isInf_T_1)
connect mulRawFN_io_b_out.isInf, _mulRawFN_io_b_out_isInf_T_2
connect mulRawFN_io_b_out.isZero, mulRawFN_io_b_isZero
node _mulRawFN_io_b_out_sign_T = bits(io.b, 32, 32)
connect mulRawFN_io_b_out.sign, _mulRawFN_io_b_out_sign_T
node _mulRawFN_io_b_out_sExp_T = cvt(mulRawFN_io_b_exp)
connect mulRawFN_io_b_out.sExp, _mulRawFN_io_b_out_sExp_T
node _mulRawFN_io_b_out_sig_T = eq(mulRawFN_io_b_isZero, UInt<1>(0h0))
node _mulRawFN_io_b_out_sig_T_1 = cat(UInt<1>(0h0), _mulRawFN_io_b_out_sig_T)
node _mulRawFN_io_b_out_sig_T_2 = bits(io.b, 22, 0)
node _mulRawFN_io_b_out_sig_T_3 = cat(_mulRawFN_io_b_out_sig_T_1, _mulRawFN_io_b_out_sig_T_2)
connect mulRawFN_io_b_out.sig, _mulRawFN_io_b_out_sig_T_3
connect mulRawFN.io.b.sig, mulRawFN_io_b_out.sig
connect mulRawFN.io.b.sExp, mulRawFN_io_b_out.sExp
connect mulRawFN.io.b.sign, mulRawFN_io_b_out.sign
connect mulRawFN.io.b.isZero, mulRawFN_io_b_out.isZero
connect mulRawFN.io.b.isInf, mulRawFN_io_b_out.isInf
connect mulRawFN.io.b.isNaN, mulRawFN_io_b_out.isNaN
inst roundRawFNToRecFN of RoundRawFNToRecFN_e8_s24_132
connect roundRawFNToRecFN.io.invalidExc, mulRawFN.io.invalidExc
connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0)
connect roundRawFNToRecFN.io.in.sig, mulRawFN.io.rawOut.sig
connect roundRawFNToRecFN.io.in.sExp, mulRawFN.io.rawOut.sExp
connect roundRawFNToRecFN.io.in.sign, mulRawFN.io.rawOut.sign
connect roundRawFNToRecFN.io.in.isZero, mulRawFN.io.rawOut.isZero
connect roundRawFNToRecFN.io.in.isInf, mulRawFN.io.rawOut.isInf
connect roundRawFNToRecFN.io.in.isNaN, mulRawFN.io.rawOut.isNaN
connect roundRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundRawFNToRecFN.io.out
connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags | module MulRecFN_53( // @[MulRecFN.scala:100:7]
input [32:0] io_a, // @[MulRecFN.scala:102:16]
input [32:0] io_b, // @[MulRecFN.scala:102:16]
output [32:0] io_out // @[MulRecFN.scala:102:16]
);
wire _mulRawFN_io_invalidExc; // @[MulRecFN.scala:113:26]
wire _mulRawFN_io_rawOut_isNaN; // @[MulRecFN.scala:113:26]
wire _mulRawFN_io_rawOut_isInf; // @[MulRecFN.scala:113:26]
wire _mulRawFN_io_rawOut_isZero; // @[MulRecFN.scala:113:26]
wire _mulRawFN_io_rawOut_sign; // @[MulRecFN.scala:113:26]
wire [9:0] _mulRawFN_io_rawOut_sExp; // @[MulRecFN.scala:113:26]
wire [26:0] _mulRawFN_io_rawOut_sig; // @[MulRecFN.scala:113:26]
wire [32:0] io_a_0 = io_a; // @[MulRecFN.scala:100:7]
wire [32:0] io_b_0 = io_b; // @[MulRecFN.scala:100:7]
wire io_detectTininess = 1'h1; // @[MulRecFN.scala:100:7, :102:16, :121:15]
wire [2:0] io_roundingMode = 3'h0; // @[MulRecFN.scala:100:7, :102:16, :121:15]
wire [32:0] io_out_0; // @[MulRecFN.scala:100:7]
wire [4:0] io_exceptionFlags; // @[MulRecFN.scala:100:7]
wire [8:0] mulRawFN_io_a_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _mulRawFN_io_a_isZero_T = mulRawFN_io_a_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire mulRawFN_io_a_isZero = _mulRawFN_io_a_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire mulRawFN_io_a_out_isZero = mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _mulRawFN_io_a_isSpecial_T = mulRawFN_io_a_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire mulRawFN_io_a_isSpecial = &_mulRawFN_io_a_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire mulRawFN_io_a_out_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire mulRawFN_io_a_out_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire mulRawFN_io_a_out_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] mulRawFN_io_a_out_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] mulRawFN_io_a_out_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _mulRawFN_io_a_out_isNaN_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _mulRawFN_io_a_out_isInf_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _mulRawFN_io_a_out_isNaN_T_1 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign mulRawFN_io_a_out_isNaN = _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _mulRawFN_io_a_out_isInf_T_1 = ~_mulRawFN_io_a_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _mulRawFN_io_a_out_isInf_T_2 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign mulRawFN_io_a_out_isInf = _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _mulRawFN_io_a_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign mulRawFN_io_a_out_sign = _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _mulRawFN_io_a_out_sExp_T = {1'h0, mulRawFN_io_a_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign mulRawFN_io_a_out_sExp = _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _mulRawFN_io_a_out_sig_T = ~mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _mulRawFN_io_a_out_sig_T_1 = {1'h0, _mulRawFN_io_a_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _mulRawFN_io_a_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _mulRawFN_io_a_out_sig_T_3 = {_mulRawFN_io_a_out_sig_T_1, _mulRawFN_io_a_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign mulRawFN_io_a_out_sig = _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [8:0] mulRawFN_io_b_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _mulRawFN_io_b_isZero_T = mulRawFN_io_b_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire mulRawFN_io_b_isZero = _mulRawFN_io_b_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire mulRawFN_io_b_out_isZero = mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _mulRawFN_io_b_isSpecial_T = mulRawFN_io_b_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire mulRawFN_io_b_isSpecial = &_mulRawFN_io_b_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire mulRawFN_io_b_out_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire mulRawFN_io_b_out_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire mulRawFN_io_b_out_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] mulRawFN_io_b_out_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] mulRawFN_io_b_out_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _mulRawFN_io_b_out_isNaN_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _mulRawFN_io_b_out_isInf_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _mulRawFN_io_b_out_isNaN_T_1 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign mulRawFN_io_b_out_isNaN = _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _mulRawFN_io_b_out_isInf_T_1 = ~_mulRawFN_io_b_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _mulRawFN_io_b_out_isInf_T_2 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign mulRawFN_io_b_out_isInf = _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _mulRawFN_io_b_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign mulRawFN_io_b_out_sign = _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _mulRawFN_io_b_out_sExp_T = {1'h0, mulRawFN_io_b_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign mulRawFN_io_b_out_sExp = _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _mulRawFN_io_b_out_sig_T = ~mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _mulRawFN_io_b_out_sig_T_1 = {1'h0, _mulRawFN_io_b_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _mulRawFN_io_b_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _mulRawFN_io_b_out_sig_T_3 = {_mulRawFN_io_b_out_sig_T_1, _mulRawFN_io_b_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign mulRawFN_io_b_out_sig = _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
MulRawFN_53 mulRawFN ( // @[MulRecFN.scala:113:26]
.io_a_isNaN (mulRawFN_io_a_out_isNaN), // @[rawFloatFromRecFN.scala:55:23]
.io_a_isInf (mulRawFN_io_a_out_isInf), // @[rawFloatFromRecFN.scala:55:23]
.io_a_isZero (mulRawFN_io_a_out_isZero), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sign (mulRawFN_io_a_out_sign), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sExp (mulRawFN_io_a_out_sExp), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sig (mulRawFN_io_a_out_sig), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isNaN (mulRawFN_io_b_out_isNaN), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isInf (mulRawFN_io_b_out_isInf), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isZero (mulRawFN_io_b_out_isZero), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sign (mulRawFN_io_b_out_sign), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sExp (mulRawFN_io_b_out_sExp), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sig (mulRawFN_io_b_out_sig), // @[rawFloatFromRecFN.scala:55:23]
.io_invalidExc (_mulRawFN_io_invalidExc),
.io_rawOut_isNaN (_mulRawFN_io_rawOut_isNaN),
.io_rawOut_isInf (_mulRawFN_io_rawOut_isInf),
.io_rawOut_isZero (_mulRawFN_io_rawOut_isZero),
.io_rawOut_sign (_mulRawFN_io_rawOut_sign),
.io_rawOut_sExp (_mulRawFN_io_rawOut_sExp),
.io_rawOut_sig (_mulRawFN_io_rawOut_sig)
); // @[MulRecFN.scala:113:26]
RoundRawFNToRecFN_e8_s24_132 roundRawFNToRecFN ( // @[MulRecFN.scala:121:15]
.io_invalidExc (_mulRawFN_io_invalidExc), // @[MulRecFN.scala:113:26]
.io_in_isNaN (_mulRawFN_io_rawOut_isNaN), // @[MulRecFN.scala:113:26]
.io_in_isInf (_mulRawFN_io_rawOut_isInf), // @[MulRecFN.scala:113:26]
.io_in_isZero (_mulRawFN_io_rawOut_isZero), // @[MulRecFN.scala:113:26]
.io_in_sign (_mulRawFN_io_rawOut_sign), // @[MulRecFN.scala:113:26]
.io_in_sExp (_mulRawFN_io_rawOut_sExp), // @[MulRecFN.scala:113:26]
.io_in_sig (_mulRawFN_io_rawOut_sig), // @[MulRecFN.scala:113:26]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags)
); // @[MulRecFN.scala:121:15]
assign io_out = io_out_0; // @[MulRecFN.scala:100:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_254 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_254( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_23 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_23
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_23( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
output io_q // @[ShiftReg.scala:36:14]
);
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_23 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Tile_123 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>}
inst tile_0_0 of PE_379
connect tile_0_0.clock, clock
connect tile_0_0.reset, reset
connect tile_0_0.io.in_a, io.in_a[0]
connect tile_0_0.io.in_b, io.in_b[0]
connect tile_0_0.io.in_d, io.in_d[0]
connect tile_0_0.io.in_control.shift, io.in_control[0].shift
connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate
connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow
connect tile_0_0.io.in_valid, io.in_valid[0]
connect tile_0_0.io.in_id, io.in_id[0]
connect tile_0_0.io.in_last, io.in_last[0]
connect io.out_c[0], tile_0_0.io.out_c
connect io.out_control[0], tile_0_0.io.out_control
connect io.out_id[0], tile_0_0.io.out_id
connect io.out_last[0], tile_0_0.io.out_last
connect io.out_valid[0], tile_0_0.io.out_valid
connect io.out_b[0], tile_0_0.io.out_b
connect io.bad_dataflow, tile_0_0.io.bad_dataflow
connect io.out_a[0], tile_0_0.io.out_a | module Tile_123( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0, // @[Tile.scala:17:14]
output io_bad_dataflow // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
wire io_bad_dataflow_0; // @[Tile.scala:16:7]
PE_379 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0),
.io_bad_dataflow (io_bad_dataflow_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module ClockSinkDomain_1 :
output auto : { flip nvdla_cfg_tl_node_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<15>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<15>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, nvdla_int_out : UInt<1>[1], nvdla_dbb_tl_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip clock_in : { clock : Clock, reset : Reset}}
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst nvdla of NVDLA
connect nvdla.clock, childClock
connect nvdla.reset, childReset
wire clockNodeIn : { clock : Clock, reset : Reset}
invalidate clockNodeIn.reset
invalidate clockNodeIn.clock
connect clockNodeIn, auto.clock_in
connect nvdla.auto.dbb_tl_out.d, auto.nvdla_dbb_tl_out.d
connect auto.nvdla_dbb_tl_out.a.bits, nvdla.auto.dbb_tl_out.a.bits
connect auto.nvdla_dbb_tl_out.a.valid, nvdla.auto.dbb_tl_out.a.valid
connect nvdla.auto.dbb_tl_out.a.ready, auto.nvdla_dbb_tl_out.a.ready
connect auto.nvdla_int_out, nvdla.auto.int_out
connect nvdla.auto.cfg_tl_node_in, auto.nvdla_cfg_tl_node_in
connect childClock, clockNodeIn.clock
connect childReset, clockNodeIn.reset
connect clock, clockNodeIn.clock
connect reset, clockNodeIn.reset
extmodule plusarg_reader_133 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_134 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module ClockSinkDomain_1( // @[ClockDomain.scala:14:9]
output auto_nvdla_cfg_tl_node_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_nvdla_cfg_tl_node_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_nvdla_cfg_tl_node_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_nvdla_cfg_tl_node_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_nvdla_cfg_tl_node_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [14:0] auto_nvdla_cfg_tl_node_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [28:0] auto_nvdla_cfg_tl_node_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_nvdla_cfg_tl_node_in_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25]
input auto_nvdla_cfg_tl_node_in_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25]
input auto_nvdla_cfg_tl_node_in_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25]
input auto_nvdla_cfg_tl_node_in_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25]
input auto_nvdla_cfg_tl_node_in_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25]
input auto_nvdla_cfg_tl_node_in_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25]
input auto_nvdla_cfg_tl_node_in_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_nvdla_cfg_tl_node_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_nvdla_cfg_tl_node_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_nvdla_cfg_tl_node_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_nvdla_cfg_tl_node_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_nvdla_cfg_tl_node_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_nvdla_cfg_tl_node_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_nvdla_cfg_tl_node_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_nvdla_cfg_tl_node_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [14:0] auto_nvdla_cfg_tl_node_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_nvdla_cfg_tl_node_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_nvdla_cfg_tl_node_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_nvdla_cfg_tl_node_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_nvdla_cfg_tl_node_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_nvdla_int_out_0, // @[LazyModuleImp.scala:107:25]
input auto_nvdla_dbb_tl_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_nvdla_dbb_tl_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_nvdla_dbb_tl_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_nvdla_dbb_tl_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_nvdla_dbb_tl_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_nvdla_dbb_tl_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_nvdla_dbb_tl_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output auto_nvdla_dbb_tl_out_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25]
output auto_nvdla_dbb_tl_out_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25]
output auto_nvdla_dbb_tl_out_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25]
output auto_nvdla_dbb_tl_out_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25]
output auto_nvdla_dbb_tl_out_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25]
output auto_nvdla_dbb_tl_out_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25]
output auto_nvdla_dbb_tl_out_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_nvdla_dbb_tl_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_nvdla_dbb_tl_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_nvdla_dbb_tl_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_nvdla_dbb_tl_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_nvdla_dbb_tl_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_nvdla_dbb_tl_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_nvdla_dbb_tl_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_nvdla_dbb_tl_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_nvdla_dbb_tl_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_nvdla_dbb_tl_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_nvdla_dbb_tl_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_nvdla_dbb_tl_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_nvdla_dbb_tl_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_reset // @[LazyModuleImp.scala:107:25]
);
NVDLA nvdla ( // @[Periphery.scala:20:29]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_cfg_tl_node_in_a_ready (auto_nvdla_cfg_tl_node_in_a_ready),
.auto_cfg_tl_node_in_a_valid (auto_nvdla_cfg_tl_node_in_a_valid),
.auto_cfg_tl_node_in_a_bits_opcode (auto_nvdla_cfg_tl_node_in_a_bits_opcode),
.auto_cfg_tl_node_in_a_bits_param (auto_nvdla_cfg_tl_node_in_a_bits_param),
.auto_cfg_tl_node_in_a_bits_size (auto_nvdla_cfg_tl_node_in_a_bits_size),
.auto_cfg_tl_node_in_a_bits_source (auto_nvdla_cfg_tl_node_in_a_bits_source),
.auto_cfg_tl_node_in_a_bits_address (auto_nvdla_cfg_tl_node_in_a_bits_address),
.auto_cfg_tl_node_in_a_bits_user_amba_prot_bufferable (auto_nvdla_cfg_tl_node_in_a_bits_user_amba_prot_bufferable),
.auto_cfg_tl_node_in_a_bits_user_amba_prot_modifiable (auto_nvdla_cfg_tl_node_in_a_bits_user_amba_prot_modifiable),
.auto_cfg_tl_node_in_a_bits_user_amba_prot_readalloc (auto_nvdla_cfg_tl_node_in_a_bits_user_amba_prot_readalloc),
.auto_cfg_tl_node_in_a_bits_user_amba_prot_writealloc (auto_nvdla_cfg_tl_node_in_a_bits_user_amba_prot_writealloc),
.auto_cfg_tl_node_in_a_bits_user_amba_prot_privileged (auto_nvdla_cfg_tl_node_in_a_bits_user_amba_prot_privileged),
.auto_cfg_tl_node_in_a_bits_user_amba_prot_secure (auto_nvdla_cfg_tl_node_in_a_bits_user_amba_prot_secure),
.auto_cfg_tl_node_in_a_bits_user_amba_prot_fetch (auto_nvdla_cfg_tl_node_in_a_bits_user_amba_prot_fetch),
.auto_cfg_tl_node_in_a_bits_mask (auto_nvdla_cfg_tl_node_in_a_bits_mask),
.auto_cfg_tl_node_in_a_bits_data (auto_nvdla_cfg_tl_node_in_a_bits_data),
.auto_cfg_tl_node_in_a_bits_corrupt (auto_nvdla_cfg_tl_node_in_a_bits_corrupt),
.auto_cfg_tl_node_in_d_ready (auto_nvdla_cfg_tl_node_in_d_ready),
.auto_cfg_tl_node_in_d_valid (auto_nvdla_cfg_tl_node_in_d_valid),
.auto_cfg_tl_node_in_d_bits_opcode (auto_nvdla_cfg_tl_node_in_d_bits_opcode),
.auto_cfg_tl_node_in_d_bits_param (auto_nvdla_cfg_tl_node_in_d_bits_param),
.auto_cfg_tl_node_in_d_bits_size (auto_nvdla_cfg_tl_node_in_d_bits_size),
.auto_cfg_tl_node_in_d_bits_source (auto_nvdla_cfg_tl_node_in_d_bits_source),
.auto_cfg_tl_node_in_d_bits_sink (auto_nvdla_cfg_tl_node_in_d_bits_sink),
.auto_cfg_tl_node_in_d_bits_denied (auto_nvdla_cfg_tl_node_in_d_bits_denied),
.auto_cfg_tl_node_in_d_bits_data (auto_nvdla_cfg_tl_node_in_d_bits_data),
.auto_cfg_tl_node_in_d_bits_corrupt (auto_nvdla_cfg_tl_node_in_d_bits_corrupt),
.auto_int_out_0 (auto_nvdla_int_out_0),
.auto_dbb_tl_out_a_ready (auto_nvdla_dbb_tl_out_a_ready),
.auto_dbb_tl_out_a_valid (auto_nvdla_dbb_tl_out_a_valid),
.auto_dbb_tl_out_a_bits_opcode (auto_nvdla_dbb_tl_out_a_bits_opcode),
.auto_dbb_tl_out_a_bits_param (auto_nvdla_dbb_tl_out_a_bits_param),
.auto_dbb_tl_out_a_bits_size (auto_nvdla_dbb_tl_out_a_bits_size),
.auto_dbb_tl_out_a_bits_source (auto_nvdla_dbb_tl_out_a_bits_source),
.auto_dbb_tl_out_a_bits_address (auto_nvdla_dbb_tl_out_a_bits_address),
.auto_dbb_tl_out_a_bits_user_amba_prot_bufferable (auto_nvdla_dbb_tl_out_a_bits_user_amba_prot_bufferable),
.auto_dbb_tl_out_a_bits_user_amba_prot_modifiable (auto_nvdla_dbb_tl_out_a_bits_user_amba_prot_modifiable),
.auto_dbb_tl_out_a_bits_user_amba_prot_readalloc (auto_nvdla_dbb_tl_out_a_bits_user_amba_prot_readalloc),
.auto_dbb_tl_out_a_bits_user_amba_prot_writealloc (auto_nvdla_dbb_tl_out_a_bits_user_amba_prot_writealloc),
.auto_dbb_tl_out_a_bits_user_amba_prot_privileged (auto_nvdla_dbb_tl_out_a_bits_user_amba_prot_privileged),
.auto_dbb_tl_out_a_bits_user_amba_prot_secure (auto_nvdla_dbb_tl_out_a_bits_user_amba_prot_secure),
.auto_dbb_tl_out_a_bits_user_amba_prot_fetch (auto_nvdla_dbb_tl_out_a_bits_user_amba_prot_fetch),
.auto_dbb_tl_out_a_bits_mask (auto_nvdla_dbb_tl_out_a_bits_mask),
.auto_dbb_tl_out_a_bits_data (auto_nvdla_dbb_tl_out_a_bits_data),
.auto_dbb_tl_out_a_bits_corrupt (auto_nvdla_dbb_tl_out_a_bits_corrupt),
.auto_dbb_tl_out_d_ready (auto_nvdla_dbb_tl_out_d_ready),
.auto_dbb_tl_out_d_valid (auto_nvdla_dbb_tl_out_d_valid),
.auto_dbb_tl_out_d_bits_opcode (auto_nvdla_dbb_tl_out_d_bits_opcode),
.auto_dbb_tl_out_d_bits_param (auto_nvdla_dbb_tl_out_d_bits_param),
.auto_dbb_tl_out_d_bits_size (auto_nvdla_dbb_tl_out_d_bits_size),
.auto_dbb_tl_out_d_bits_source (auto_nvdla_dbb_tl_out_d_bits_source),
.auto_dbb_tl_out_d_bits_sink (auto_nvdla_dbb_tl_out_d_bits_sink),
.auto_dbb_tl_out_d_bits_denied (auto_nvdla_dbb_tl_out_d_bits_denied),
.auto_dbb_tl_out_d_bits_data (auto_nvdla_dbb_tl_out_d_bits_data),
.auto_dbb_tl_out_d_bits_corrupt (auto_nvdla_dbb_tl_out_d_bits_corrupt)
); // @[Periphery.scala:20:29]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Router_9 :
input clock : Clock
input reset : Reset
output auto : { debug_out : { va_stall : UInt[2], sa_stall : UInt[2]}, egress_nodes_out_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, egress_nodes_out_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, flip ingress_nodes_in : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, source_nodes_out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<6>, flip vc_free : UInt<6>}, flip dest_nodes_in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<6>, flip vc_free : UInt<6>}}
wire destNodesIn : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<6>, flip vc_free : UInt<6>}
invalidate destNodesIn.vc_free
invalidate destNodesIn.credit_return
invalidate destNodesIn.flit[0].bits.virt_channel_id
invalidate destNodesIn.flit[0].bits.flow.egress_node_id
invalidate destNodesIn.flit[0].bits.flow.egress_node
invalidate destNodesIn.flit[0].bits.flow.ingress_node_id
invalidate destNodesIn.flit[0].bits.flow.ingress_node
invalidate destNodesIn.flit[0].bits.flow.vnet_id
invalidate destNodesIn.flit[0].bits.payload
invalidate destNodesIn.flit[0].bits.tail
invalidate destNodesIn.flit[0].bits.head
invalidate destNodesIn.flit[0].valid
inst monitor of NoCMonitor_9
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.vc_free, destNodesIn.vc_free
connect monitor.io.in.credit_return, destNodesIn.credit_return
connect monitor.io.in.flit[0].bits.virt_channel_id, destNodesIn.flit[0].bits.virt_channel_id
connect monitor.io.in.flit[0].bits.flow.egress_node_id, destNodesIn.flit[0].bits.flow.egress_node_id
connect monitor.io.in.flit[0].bits.flow.egress_node, destNodesIn.flit[0].bits.flow.egress_node
connect monitor.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn.flit[0].bits.flow.ingress_node_id
connect monitor.io.in.flit[0].bits.flow.ingress_node, destNodesIn.flit[0].bits.flow.ingress_node
connect monitor.io.in.flit[0].bits.flow.vnet_id, destNodesIn.flit[0].bits.flow.vnet_id
connect monitor.io.in.flit[0].bits.payload, destNodesIn.flit[0].bits.payload
connect monitor.io.in.flit[0].bits.tail, destNodesIn.flit[0].bits.tail
connect monitor.io.in.flit[0].bits.head, destNodesIn.flit[0].bits.head
connect monitor.io.in.flit[0].valid, destNodesIn.flit[0].valid
wire sourceNodesOut : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<6>, flip vc_free : UInt<6>}
invalidate sourceNodesOut.vc_free
invalidate sourceNodesOut.credit_return
invalidate sourceNodesOut.flit[0].bits.virt_channel_id
invalidate sourceNodesOut.flit[0].bits.flow.egress_node_id
invalidate sourceNodesOut.flit[0].bits.flow.egress_node
invalidate sourceNodesOut.flit[0].bits.flow.ingress_node_id
invalidate sourceNodesOut.flit[0].bits.flow.ingress_node
invalidate sourceNodesOut.flit[0].bits.flow.vnet_id
invalidate sourceNodesOut.flit[0].bits.payload
invalidate sourceNodesOut.flit[0].bits.tail
invalidate sourceNodesOut.flit[0].bits.head
invalidate sourceNodesOut.flit[0].valid
wire ingressNodesIn : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesIn.flit.bits.egress_id
invalidate ingressNodesIn.flit.bits.payload
invalidate ingressNodesIn.flit.bits.tail
invalidate ingressNodesIn.flit.bits.head
invalidate ingressNodesIn.flit.valid
invalidate ingressNodesIn.flit.ready
wire egressNodesOut : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesOut.flit.bits.ingress_id
invalidate egressNodesOut.flit.bits.payload
invalidate egressNodesOut.flit.bits.tail
invalidate egressNodesOut.flit.bits.head
invalidate egressNodesOut.flit.valid
invalidate egressNodesOut.flit.ready
wire egressNodesOut_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesOut_1.flit.bits.ingress_id
invalidate egressNodesOut_1.flit.bits.payload
invalidate egressNodesOut_1.flit.bits.tail
invalidate egressNodesOut_1.flit.bits.head
invalidate egressNodesOut_1.flit.valid
invalidate egressNodesOut_1.flit.ready
wire debugNodeOut : { va_stall : UInt[2], sa_stall : UInt[2]}
invalidate debugNodeOut.sa_stall[0]
invalidate debugNodeOut.sa_stall[1]
invalidate debugNodeOut.va_stall[0]
invalidate debugNodeOut.va_stall[1]
connect destNodesIn, auto.dest_nodes_in
connect auto.source_nodes_out, sourceNodesOut
connect ingressNodesIn, auto.ingress_nodes_in
connect auto.egress_nodes_out_0, egressNodesOut
connect auto.egress_nodes_out_1, egressNodesOut_1
connect auto.debug_out, debugNodeOut
inst input_unit_0_from_8 of InputUnit_9
connect input_unit_0_from_8.clock, clock
connect input_unit_0_from_8.reset, reset
inst ingress_unit_1_from_19 of IngressUnit_19
connect ingress_unit_1_from_19.clock, clock
connect ingress_unit_1_from_19.reset, reset
inst output_unit_0_to_10 of OutputUnit_9
connect output_unit_0_to_10.clock, clock
connect output_unit_0_to_10.reset, reset
inst egress_unit_1_to_11 of EgressUnit_11
connect egress_unit_1_to_11.clock, clock
connect egress_unit_1_to_11.reset, reset
inst egress_unit_2_to_12 of EgressUnit_12
connect egress_unit_2_to_12.clock, clock
connect egress_unit_2_to_12.reset, reset
inst switch of Switch_9
connect switch.clock, clock
connect switch.reset, reset
inst switch_allocator of SwitchAllocator_9
connect switch_allocator.clock, clock
connect switch_allocator.reset, reset
inst vc_allocator of RotatingSingleVCAllocator_9
connect vc_allocator.clock, clock
connect vc_allocator.reset, reset
inst route_computer of RouteComputer_9
connect route_computer.clock, clock
connect route_computer.reset, reset
node _fires_count_T = and(vc_allocator.io.req.`0`.ready, vc_allocator.io.req.`0`.valid)
node _fires_count_T_1 = and(vc_allocator.io.req.`1`.ready, vc_allocator.io.req.`1`.valid)
node _fires_count_T_2 = add(_fires_count_T, _fires_count_T_1)
node _fires_count_T_3 = bits(_fires_count_T_2, 1, 0)
wire fires_count : UInt
connect fires_count, _fires_count_T_3
connect input_unit_0_from_8.io.in, destNodesIn
connect ingress_unit_1_from_19.io.in, ingressNodesIn.flit
connect output_unit_0_to_10.io.out.vc_free, sourceNodesOut.vc_free
connect output_unit_0_to_10.io.out.credit_return, sourceNodesOut.credit_return
connect sourceNodesOut.flit, output_unit_0_to_10.io.out.flit
connect egressNodesOut.flit.bits, egress_unit_1_to_11.io.out.bits
connect egressNodesOut.flit.valid, egress_unit_1_to_11.io.out.valid
connect egress_unit_1_to_11.io.out.ready, egressNodesOut.flit.ready
connect egressNodesOut_1.flit.bits, egress_unit_2_to_12.io.out.bits
connect egressNodesOut_1.flit.valid, egress_unit_2_to_12.io.out.valid
connect egress_unit_2_to_12.io.out.ready, egressNodesOut_1.flit.ready
connect route_computer.io.req.`0`, input_unit_0_from_8.io.router_req
connect route_computer.io.req.`1`, ingress_unit_1_from_19.io.router_req
connect input_unit_0_from_8.io.router_resp, route_computer.io.resp.`0`
connect ingress_unit_1_from_19.io.router_resp, route_computer.io.resp.`1`
connect vc_allocator.io.req.`0`, input_unit_0_from_8.io.vcalloc_req
connect vc_allocator.io.req.`1`, ingress_unit_1_from_19.io.vcalloc_req
connect input_unit_0_from_8.io.vcalloc_resp, vc_allocator.io.resp.`0`
connect ingress_unit_1_from_19.io.vcalloc_resp, vc_allocator.io.resp.`1`
connect output_unit_0_to_10.io.allocs, vc_allocator.io.out_allocs.`0`
connect egress_unit_1_to_11.io.allocs, vc_allocator.io.out_allocs.`1`
connect egress_unit_2_to_12.io.allocs, vc_allocator.io.out_allocs.`2`
connect vc_allocator.io.channel_status.`0`[0].flow.egress_node_id, output_unit_0_to_10.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[0].flow.egress_node, output_unit_0_to_10.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node_id, output_unit_0_to_10.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node, output_unit_0_to_10.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[0].flow.vnet_id, output_unit_0_to_10.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[0].occupied, output_unit_0_to_10.io.channel_status[0].occupied
connect vc_allocator.io.channel_status.`0`[1].flow.egress_node_id, output_unit_0_to_10.io.channel_status[1].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[1].flow.egress_node, output_unit_0_to_10.io.channel_status[1].flow.egress_node
connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node_id, output_unit_0_to_10.io.channel_status[1].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node, output_unit_0_to_10.io.channel_status[1].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[1].flow.vnet_id, output_unit_0_to_10.io.channel_status[1].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[1].occupied, output_unit_0_to_10.io.channel_status[1].occupied
connect vc_allocator.io.channel_status.`0`[2].flow.egress_node_id, output_unit_0_to_10.io.channel_status[2].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[2].flow.egress_node, output_unit_0_to_10.io.channel_status[2].flow.egress_node
connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node_id, output_unit_0_to_10.io.channel_status[2].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node, output_unit_0_to_10.io.channel_status[2].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[2].flow.vnet_id, output_unit_0_to_10.io.channel_status[2].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[2].occupied, output_unit_0_to_10.io.channel_status[2].occupied
connect vc_allocator.io.channel_status.`0`[3].flow.egress_node_id, output_unit_0_to_10.io.channel_status[3].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[3].flow.egress_node, output_unit_0_to_10.io.channel_status[3].flow.egress_node
connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node_id, output_unit_0_to_10.io.channel_status[3].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node, output_unit_0_to_10.io.channel_status[3].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[3].flow.vnet_id, output_unit_0_to_10.io.channel_status[3].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[3].occupied, output_unit_0_to_10.io.channel_status[3].occupied
connect vc_allocator.io.channel_status.`0`[4].flow.egress_node_id, output_unit_0_to_10.io.channel_status[4].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[4].flow.egress_node, output_unit_0_to_10.io.channel_status[4].flow.egress_node
connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node_id, output_unit_0_to_10.io.channel_status[4].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node, output_unit_0_to_10.io.channel_status[4].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[4].flow.vnet_id, output_unit_0_to_10.io.channel_status[4].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[4].occupied, output_unit_0_to_10.io.channel_status[4].occupied
connect vc_allocator.io.channel_status.`0`[5].flow.egress_node_id, output_unit_0_to_10.io.channel_status[5].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[5].flow.egress_node, output_unit_0_to_10.io.channel_status[5].flow.egress_node
connect vc_allocator.io.channel_status.`0`[5].flow.ingress_node_id, output_unit_0_to_10.io.channel_status[5].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[5].flow.ingress_node, output_unit_0_to_10.io.channel_status[5].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[5].flow.vnet_id, output_unit_0_to_10.io.channel_status[5].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[5].occupied, output_unit_0_to_10.io.channel_status[5].occupied
connect vc_allocator.io.channel_status.`1`[0].flow.egress_node_id, egress_unit_1_to_11.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`1`[0].flow.egress_node, egress_unit_1_to_11.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node_id, egress_unit_1_to_11.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node, egress_unit_1_to_11.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`1`[0].flow.vnet_id, egress_unit_1_to_11.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`1`[0].occupied, egress_unit_1_to_11.io.channel_status[0].occupied
connect vc_allocator.io.channel_status.`2`[0].flow.egress_node_id, egress_unit_2_to_12.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`2`[0].flow.egress_node, egress_unit_2_to_12.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node_id, egress_unit_2_to_12.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node, egress_unit_2_to_12.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`2`[0].flow.vnet_id, egress_unit_2_to_12.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`2`[0].occupied, egress_unit_2_to_12.io.channel_status[0].occupied
connect input_unit_0_from_8.io.out_credit_available.`0`[0], output_unit_0_to_10.io.credit_available[0]
connect input_unit_0_from_8.io.out_credit_available.`0`[1], output_unit_0_to_10.io.credit_available[1]
connect input_unit_0_from_8.io.out_credit_available.`0`[2], output_unit_0_to_10.io.credit_available[2]
connect input_unit_0_from_8.io.out_credit_available.`0`[3], output_unit_0_to_10.io.credit_available[3]
connect input_unit_0_from_8.io.out_credit_available.`0`[4], output_unit_0_to_10.io.credit_available[4]
connect input_unit_0_from_8.io.out_credit_available.`0`[5], output_unit_0_to_10.io.credit_available[5]
connect input_unit_0_from_8.io.out_credit_available.`1`[0], egress_unit_1_to_11.io.credit_available[0]
connect input_unit_0_from_8.io.out_credit_available.`2`[0], egress_unit_2_to_12.io.credit_available[0]
connect ingress_unit_1_from_19.io.out_credit_available.`0`[0], output_unit_0_to_10.io.credit_available[0]
connect ingress_unit_1_from_19.io.out_credit_available.`0`[1], output_unit_0_to_10.io.credit_available[1]
connect ingress_unit_1_from_19.io.out_credit_available.`0`[2], output_unit_0_to_10.io.credit_available[2]
connect ingress_unit_1_from_19.io.out_credit_available.`0`[3], output_unit_0_to_10.io.credit_available[3]
connect ingress_unit_1_from_19.io.out_credit_available.`0`[4], output_unit_0_to_10.io.credit_available[4]
connect ingress_unit_1_from_19.io.out_credit_available.`0`[5], output_unit_0_to_10.io.credit_available[5]
connect ingress_unit_1_from_19.io.out_credit_available.`1`[0], egress_unit_1_to_11.io.credit_available[0]
connect ingress_unit_1_from_19.io.out_credit_available.`2`[0], egress_unit_2_to_12.io.credit_available[0]
connect switch_allocator.io.req.`0`[0], input_unit_0_from_8.io.salloc_req[0]
connect switch_allocator.io.req.`1`[0], ingress_unit_1_from_19.io.salloc_req[0]
connect output_unit_0_to_10.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`0`[0].tail
connect output_unit_0_to_10.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`0`[0].alloc
connect output_unit_0_to_10.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`0`[1].tail
connect output_unit_0_to_10.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`0`[1].alloc
connect output_unit_0_to_10.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`0`[2].tail
connect output_unit_0_to_10.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`0`[2].alloc
connect output_unit_0_to_10.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`0`[3].tail
connect output_unit_0_to_10.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`0`[3].alloc
connect output_unit_0_to_10.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`0`[4].tail
connect output_unit_0_to_10.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`0`[4].alloc
connect output_unit_0_to_10.io.credit_alloc[5].tail, switch_allocator.io.credit_alloc.`0`[5].tail
connect output_unit_0_to_10.io.credit_alloc[5].alloc, switch_allocator.io.credit_alloc.`0`[5].alloc
connect egress_unit_1_to_11.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`1`[0].tail
connect egress_unit_1_to_11.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`1`[0].alloc
connect egress_unit_2_to_12.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`2`[0].tail
connect egress_unit_2_to_12.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`2`[0].alloc
connect switch.io.in.`0`[0], input_unit_0_from_8.io.out[0]
connect switch.io.in.`1`[0], ingress_unit_1_from_19.io.out[0]
connect output_unit_0_to_10.io.in, switch.io.out.`0`
connect egress_unit_1_to_11.io.in, switch.io.out.`1`
connect egress_unit_2_to_12.io.in, switch.io.out.`2`
reg REG : { `2` : { `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `1` : { `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}, clock
connect REG, switch_allocator.io.switch_sel
connect switch.io.sel.`0`[0].`0`[0], REG.`0`[0].`0`[0]
connect switch.io.sel.`0`[0].`1`[0], REG.`0`[0].`1`[0]
connect switch.io.sel.`1`[0].`0`[0], REG.`1`[0].`0`[0]
connect switch.io.sel.`1`[0].`1`[0], REG.`1`[0].`1`[0]
connect switch.io.sel.`2`[0].`0`[0], REG.`2`[0].`0`[0]
connect switch.io.sel.`2`[0].`1`[0], REG.`2`[0].`1`[0]
connect input_unit_0_from_8.io.block, UInt<1>(0h0)
connect ingress_unit_1_from_19.io.block, UInt<1>(0h0)
connect debugNodeOut.va_stall[0], input_unit_0_from_8.io.debug.va_stall
connect debugNodeOut.va_stall[1], ingress_unit_1_from_19.io.debug.va_stall
connect debugNodeOut.sa_stall[0], input_unit_0_from_8.io.debug.sa_stall
connect debugNodeOut.sa_stall[1], ingress_unit_1_from_19.io.debug.sa_stall
regreset debug_tsc : UInt<64>, clock, reset, UInt<64>(0h0)
node _debug_tsc_T = add(debug_tsc, UInt<1>(0h1))
node _debug_tsc_T_1 = tail(_debug_tsc_T, 1)
connect debug_tsc, _debug_tsc_T_1
regreset debug_sample : UInt<64>, clock, reset, UInt<64>(0h0)
node _debug_sample_T = add(debug_sample, UInt<1>(0h1))
node _debug_sample_T_1 = tail(_debug_sample_T, 1)
connect debug_sample, _debug_sample_T_1
inst plusarg_reader of plusarg_reader_27
node _T = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_1 = tail(_T, 1)
node _T_2 = eq(debug_sample, _T_1)
when _T_2 :
connect debug_sample, UInt<1>(0h0)
regreset util_ctr : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T = add(util_ctr, destNodesIn.flit[0].valid)
node _util_ctr_T_1 = tail(_util_ctr_T, 1)
connect util_ctr, _util_ctr_T_1
node _fired_T = or(fired, destNodesIn.flit[0].valid)
connect fired, _fired_T
node _T_3 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_4 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_5 = tail(_T_4, 1)
node _T_6 = eq(debug_sample, _T_5)
node _T_7 = and(_T_3, _T_6)
node _T_8 = and(_T_7, fired)
when _T_8 :
node _T_9 = asUInt(reset)
node _T_10 = eq(_T_9, UInt<1>(0h0))
when _T_10 :
printf(clock, UInt<1>(0h1), "nocsample %d 8 9 %d\n", debug_tsc, util_ctr) : printf
connect fired, destNodesIn.flit[0].valid
node _T_11 = and(ingressNodesIn.flit.ready, ingressNodesIn.flit.valid)
regreset util_ctr_1 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_2 = add(util_ctr_1, _T_11)
node _util_ctr_T_3 = tail(_util_ctr_T_2, 1)
connect util_ctr_1, _util_ctr_T_3
node _fired_T_1 = or(fired_1, _T_11)
connect fired_1, _fired_T_1
node _T_12 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_13 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_14 = tail(_T_13, 1)
node _T_15 = eq(debug_sample, _T_14)
node _T_16 = and(_T_12, _T_15)
node _T_17 = and(_T_16, fired_1)
when _T_17 :
node _T_18 = asUInt(reset)
node _T_19 = eq(_T_18, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "nocsample %d i19 9 %d\n", debug_tsc, util_ctr_1) : printf_1
connect fired_1, _T_11
node _T_20 = and(egressNodesOut.flit.ready, egressNodesOut.flit.valid)
regreset util_ctr_2 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_4 = add(util_ctr_2, _T_20)
node _util_ctr_T_5 = tail(_util_ctr_T_4, 1)
connect util_ctr_2, _util_ctr_T_5
node _fired_T_2 = or(fired_2, _T_20)
connect fired_2, _fired_T_2
node _T_21 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_22 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_23 = tail(_T_22, 1)
node _T_24 = eq(debug_sample, _T_23)
node _T_25 = and(_T_21, _T_24)
node _T_26 = and(_T_25, fired_2)
when _T_26 :
node _T_27 = asUInt(reset)
node _T_28 = eq(_T_27, UInt<1>(0h0))
when _T_28 :
printf(clock, UInt<1>(0h1), "nocsample %d 9 e11 %d\n", debug_tsc, util_ctr_2) : printf_2
connect fired_2, _T_20
node _T_29 = and(egressNodesOut_1.flit.ready, egressNodesOut_1.flit.valid)
regreset util_ctr_3 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_3 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_6 = add(util_ctr_3, _T_29)
node _util_ctr_T_7 = tail(_util_ctr_T_6, 1)
connect util_ctr_3, _util_ctr_T_7
node _fired_T_3 = or(fired_3, _T_29)
connect fired_3, _fired_T_3
node _T_30 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_31 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_32 = tail(_T_31, 1)
node _T_33 = eq(debug_sample, _T_32)
node _T_34 = and(_T_30, _T_33)
node _T_35 = and(_T_34, fired_3)
when _T_35 :
node _T_36 = asUInt(reset)
node _T_37 = eq(_T_36, UInt<1>(0h0))
when _T_37 :
printf(clock, UInt<1>(0h1), "nocsample %d 9 e12 %d\n", debug_tsc, util_ctr_3) : printf_3
connect fired_3, _T_29 | module Router_9( // @[Router.scala:89:25]
input clock, // @[Router.scala:89:25]
input reset, // @[Router.scala:89:25]
output [2:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25]
input auto_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_egress_nodes_out_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_ingress_nodes_in_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_ingress_nodes_in_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_ingress_nodes_in_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_dest_nodes_in_vc_free // @[LazyModuleImp.scala:107:25]
);
wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire _route_computer_io_resp_1_vc_sel_0_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_2; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_3; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_4; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_5; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_2; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_3; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_4; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_5; // @[Router.scala:136:32]
wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_2_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_3; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_4; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_5; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_2_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_0_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_0_3; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_0_4; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_0_5; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_2_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_2_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_3_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_4_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_5_alloc; // @[Router.scala:133:30]
wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_2_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_2_0_tail; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_0_tail; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_2_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_3_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_4_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_5_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34]
wire _switch_io_out_2_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_1_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_0_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _egress_unit_2_to_12_io_credit_available_0; // @[Router.scala:125:13]
wire _egress_unit_2_to_12_io_channel_status_0_occupied; // @[Router.scala:125:13]
wire _egress_unit_2_to_12_io_out_valid; // @[Router.scala:125:13]
wire _egress_unit_1_to_11_io_credit_available_0; // @[Router.scala:125:13]
wire _egress_unit_1_to_11_io_channel_status_0_occupied; // @[Router.scala:125:13]
wire _egress_unit_1_to_11_io_out_valid; // @[Router.scala:125:13]
wire _output_unit_0_to_10_io_credit_available_1; // @[Router.scala:122:13]
wire _output_unit_0_to_10_io_credit_available_2; // @[Router.scala:122:13]
wire _output_unit_0_to_10_io_credit_available_3; // @[Router.scala:122:13]
wire _output_unit_0_to_10_io_credit_available_4; // @[Router.scala:122:13]
wire _output_unit_0_to_10_io_credit_available_5; // @[Router.scala:122:13]
wire _output_unit_0_to_10_io_channel_status_1_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_10_io_channel_status_2_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_10_io_channel_status_3_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_10_io_channel_status_4_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_10_io_channel_status_5_occupied; // @[Router.scala:122:13]
wire [3:0] _ingress_unit_1_from_19_io_router_req_bits_flow_egress_node; // @[Router.scala:116:13]
wire _ingress_unit_1_from_19_io_vcalloc_req_valid; // @[Router.scala:116:13]
wire _ingress_unit_1_from_19_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_19_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_19_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_19_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_1_from_19_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_1_from_19_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_1_from_19_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_1_from_19_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:116:13]
wire _ingress_unit_1_from_19_io_salloc_req_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_1_from_19_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_19_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_19_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_19_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_1_from_19_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_1_from_19_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_1_from_19_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_1_from_19_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:116:13]
wire _ingress_unit_1_from_19_io_salloc_req_0_bits_tail; // @[Router.scala:116:13]
wire _ingress_unit_1_from_19_io_out_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_1_from_19_io_out_0_bits_flit_head; // @[Router.scala:116:13]
wire _ingress_unit_1_from_19_io_out_0_bits_flit_tail; // @[Router.scala:116:13]
wire [72:0] _ingress_unit_1_from_19_io_out_0_bits_flit_payload; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_1_from_19_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_1_from_19_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_1_from_19_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_1_from_19_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_1_from_19_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_1_from_19_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13]
wire _ingress_unit_1_from_19_io_in_ready; // @[Router.scala:116:13]
wire [2:0] _input_unit_0_from_8_io_router_req_bits_src_virt_id; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_8_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_8_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_8_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_8_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_8_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_vcalloc_req_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_salloc_req_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_salloc_req_0_bits_tail; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_out_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_out_0_bits_flit_head; // @[Router.scala:112:13]
wire _input_unit_0_from_8_io_out_0_bits_flit_tail; // @[Router.scala:112:13]
wire [72:0] _input_unit_0_from_8_io_out_0_bits_flit_payload; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_8_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_8_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_8_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_8_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_8_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_8_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13]
wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_8_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _ingress_unit_1_from_19_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35]
reg REG_2_0_1_0; // @[Router.scala:178:14]
reg REG_2_0_0_0; // @[Router.scala:178:14]
reg REG_1_0_1_0; // @[Router.scala:178:14]
reg REG_1_0_0_0; // @[Router.scala:178:14]
reg REG_0_0_1_0; // @[Router.scala:178:14]
reg REG_0_0_0_0; // @[Router.scala:178:14]
reg [63:0] debug_tsc; // @[Router.scala:195:28]
reg [63:0] debug_sample; // @[Router.scala:197:31]
wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11]
reg [63:0] util_ctr; // @[Router.scala:203:29]
reg fired; // @[Router.scala:204:26]
wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11]
wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_1; // @[Router.scala:203:29]
reg fired_1; // @[Router.scala:204:26]
wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_2; // @[Router.scala:203:29]
reg fired_2; // @[Router.scala:204:26]
wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_3; // @[Router.scala:203:29]
reg fired_3; // @[Router.scala:204:26]
wire _GEN_4 = _GEN_0 & fired_3; // @[Router.scala:204:26, :207:{33,71}] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_100 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_100( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_178 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_326
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_178( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
output io_q // @[ShiftReg.scala:36:14]
);
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_326 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module InputBuffer_21 :
input clock : Clock
input reset : Reset
output io : { flip enq : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}}[1], deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>}}[4]}
cmem mem : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>} [2]
wire _heads_WIRE : UInt<1>[4]
connect _heads_WIRE[0], UInt<1>(0h0)
connect _heads_WIRE[1], UInt<1>(0h1)
connect _heads_WIRE[2], UInt<1>(0h0)
connect _heads_WIRE[3], UInt<1>(0h0)
regreset heads : UInt<1>[4], clock, reset, _heads_WIRE
wire _tails_WIRE : UInt<1>[4]
connect _tails_WIRE[0], UInt<1>(0h0)
connect _tails_WIRE[1], UInt<1>(0h1)
connect _tails_WIRE[2], UInt<1>(0h0)
connect _tails_WIRE[3], UInt<1>(0h0)
regreset tails : UInt<1>[4], clock, reset, _tails_WIRE
node empty_0 = eq(heads[0], tails[0])
node empty_1 = eq(heads[1], tails[1])
node empty_2 = eq(heads[2], tails[2])
node empty_3 = eq(heads[3], tails[3])
inst qs_0 of Queue1_BaseFlit_110
connect qs_0.clock, clock
connect qs_0.reset, reset
inst qs_1 of Queue1_BaseFlit_111
connect qs_1.clock, clock
connect qs_1.reset, reset
inst qs_2 of Queue1_BaseFlit_112
connect qs_2.clock, clock
connect qs_2.reset, reset
inst qs_3 of Queue1_BaseFlit_113
connect qs_3.clock, clock
connect qs_3.reset, reset
connect qs_0.io.enq.valid, UInt<1>(0h0)
connect qs_1.io.enq.valid, UInt<1>(0h0)
connect qs_2.io.enq.valid, UInt<1>(0h0)
connect qs_3.io.enq.valid, UInt<1>(0h0)
invalidate qs_0.io.enq.bits.payload
invalidate qs_0.io.enq.bits.tail
invalidate qs_0.io.enq.bits.head
invalidate qs_1.io.enq.bits.payload
invalidate qs_1.io.enq.bits.tail
invalidate qs_1.io.enq.bits.head
invalidate qs_2.io.enq.bits.payload
invalidate qs_2.io.enq.bits.tail
invalidate qs_2.io.enq.bits.head
invalidate qs_3.io.enq.bits.payload
invalidate qs_3.io.enq.bits.tail
invalidate qs_3.io.enq.bits.head
node vc_sel = dshl(UInt<1>(0h1), io.enq[0].bits.virt_channel_id)
wire flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>}
node _direct_to_q_T = bits(vc_sel, 0, 0)
node _direct_to_q_T_1 = bits(vc_sel, 1, 1)
node _direct_to_q_T_2 = bits(vc_sel, 2, 2)
node _direct_to_q_T_3 = bits(vc_sel, 3, 3)
node _direct_to_q_T_4 = mux(_direct_to_q_T, qs_0.io.enq.ready, UInt<1>(0h0))
node _direct_to_q_T_5 = mux(_direct_to_q_T_1, qs_1.io.enq.ready, UInt<1>(0h0))
node _direct_to_q_T_6 = mux(_direct_to_q_T_2, qs_2.io.enq.ready, UInt<1>(0h0))
node _direct_to_q_T_7 = mux(_direct_to_q_T_3, qs_3.io.enq.ready, UInt<1>(0h0))
node _direct_to_q_T_8 = or(_direct_to_q_T_4, _direct_to_q_T_5)
node _direct_to_q_T_9 = or(_direct_to_q_T_8, _direct_to_q_T_6)
node _direct_to_q_T_10 = or(_direct_to_q_T_9, _direct_to_q_T_7)
wire _direct_to_q_WIRE : UInt<1>
connect _direct_to_q_WIRE, _direct_to_q_T_10
node _direct_to_q_T_11 = bits(vc_sel, 0, 0)
node _direct_to_q_T_12 = bits(vc_sel, 1, 1)
node _direct_to_q_T_13 = bits(vc_sel, 2, 2)
node _direct_to_q_T_14 = bits(vc_sel, 3, 3)
node _direct_to_q_T_15 = mux(_direct_to_q_T_11, empty_0, UInt<1>(0h0))
node _direct_to_q_T_16 = mux(_direct_to_q_T_12, empty_1, UInt<1>(0h0))
node _direct_to_q_T_17 = mux(_direct_to_q_T_13, empty_2, UInt<1>(0h0))
node _direct_to_q_T_18 = mux(_direct_to_q_T_14, empty_3, UInt<1>(0h0))
node _direct_to_q_T_19 = or(_direct_to_q_T_15, _direct_to_q_T_16)
node _direct_to_q_T_20 = or(_direct_to_q_T_19, _direct_to_q_T_17)
node _direct_to_q_T_21 = or(_direct_to_q_T_20, _direct_to_q_T_18)
wire _direct_to_q_WIRE_1 : UInt<1>
connect _direct_to_q_WIRE_1, _direct_to_q_T_21
node _direct_to_q_T_22 = and(_direct_to_q_WIRE, _direct_to_q_WIRE_1)
node direct_to_q = and(_direct_to_q_T_22, UInt<1>(0h1))
connect flit.head, io.enq[0].bits.head
connect flit.tail, io.enq[0].bits.tail
connect flit.payload, io.enq[0].bits.payload
node _T = eq(direct_to_q, UInt<1>(0h0))
node _T_1 = and(io.enq[0].valid, _T)
when _T_1 :
write mport MPORT = mem[tails[io.enq[0].bits.virt_channel_id]], clock
connect MPORT, flit
node _tails_T = bits(vc_sel, 0, 0)
node _tails_T_1 = bits(vc_sel, 1, 1)
node _tails_T_2 = bits(vc_sel, 2, 2)
node _tails_T_3 = bits(vc_sel, 3, 3)
node _tails_T_4 = mux(_tails_T, UInt<1>(0h0), UInt<1>(0h0))
node _tails_T_5 = mux(_tails_T_1, UInt<1>(0h1), UInt<1>(0h0))
node _tails_T_6 = mux(_tails_T_2, UInt<1>(0h0), UInt<1>(0h0))
node _tails_T_7 = mux(_tails_T_3, UInt<1>(0h0), UInt<1>(0h0))
node _tails_T_8 = or(_tails_T_4, _tails_T_5)
node _tails_T_9 = or(_tails_T_8, _tails_T_6)
node _tails_T_10 = or(_tails_T_9, _tails_T_7)
wire _tails_WIRE_1 : UInt<1>
connect _tails_WIRE_1, _tails_T_10
node _tails_T_11 = eq(tails[io.enq[0].bits.virt_channel_id], _tails_WIRE_1)
node _tails_T_12 = bits(vc_sel, 0, 0)
node _tails_T_13 = bits(vc_sel, 1, 1)
node _tails_T_14 = bits(vc_sel, 2, 2)
node _tails_T_15 = bits(vc_sel, 3, 3)
node _tails_T_16 = mux(_tails_T_12, UInt<1>(0h0), UInt<1>(0h0))
node _tails_T_17 = mux(_tails_T_13, UInt<1>(0h1), UInt<1>(0h0))
node _tails_T_18 = mux(_tails_T_14, UInt<1>(0h0), UInt<1>(0h0))
node _tails_T_19 = mux(_tails_T_15, UInt<1>(0h0), UInt<1>(0h0))
node _tails_T_20 = or(_tails_T_16, _tails_T_17)
node _tails_T_21 = or(_tails_T_20, _tails_T_18)
node _tails_T_22 = or(_tails_T_21, _tails_T_19)
wire _tails_WIRE_2 : UInt<1>
connect _tails_WIRE_2, _tails_T_22
node _tails_T_23 = add(tails[io.enq[0].bits.virt_channel_id], UInt<1>(0h1))
node _tails_T_24 = tail(_tails_T_23, 1)
node _tails_T_25 = mux(_tails_T_11, _tails_WIRE_2, _tails_T_24)
connect tails[io.enq[0].bits.virt_channel_id], _tails_T_25
else :
node _T_2 = and(io.enq[0].valid, direct_to_q)
when _T_2 :
node _T_3 = eq(io.enq[0].bits.virt_channel_id, UInt<1>(0h0))
when _T_3 :
connect qs_0.io.enq.valid, UInt<1>(0h1)
connect qs_0.io.enq.bits.payload, flit.payload
connect qs_0.io.enq.bits.tail, flit.tail
connect qs_0.io.enq.bits.head, flit.head
node _T_4 = eq(io.enq[0].bits.virt_channel_id, UInt<1>(0h1))
when _T_4 :
connect qs_1.io.enq.valid, UInt<1>(0h1)
connect qs_1.io.enq.bits.payload, flit.payload
connect qs_1.io.enq.bits.tail, flit.tail
connect qs_1.io.enq.bits.head, flit.head
node _T_5 = eq(io.enq[0].bits.virt_channel_id, UInt<2>(0h2))
when _T_5 :
connect qs_2.io.enq.valid, UInt<1>(0h1)
connect qs_2.io.enq.bits.payload, flit.payload
connect qs_2.io.enq.bits.tail, flit.tail
connect qs_2.io.enq.bits.head, flit.head
node _T_6 = eq(io.enq[0].bits.virt_channel_id, UInt<2>(0h3))
when _T_6 :
connect qs_3.io.enq.valid, UInt<1>(0h1)
connect qs_3.io.enq.bits.payload, flit.payload
connect qs_3.io.enq.bits.tail, flit.tail
connect qs_3.io.enq.bits.head, flit.head
node _can_to_q_T = eq(empty_0, UInt<1>(0h0))
node can_to_q_0 = and(_can_to_q_T, qs_0.io.enq.ready)
node _can_to_q_T_1 = eq(empty_1, UInt<1>(0h0))
node can_to_q_1 = and(_can_to_q_T_1, qs_1.io.enq.ready)
node _can_to_q_T_2 = eq(empty_2, UInt<1>(0h0))
node can_to_q_2 = and(_can_to_q_T_2, qs_2.io.enq.ready)
node _can_to_q_T_3 = eq(empty_3, UInt<1>(0h0))
node can_to_q_3 = and(_can_to_q_T_3, qs_3.io.enq.ready)
node _to_q_oh_enc_T = mux(can_to_q_3, UInt<4>(0h8), UInt<4>(0h0))
node _to_q_oh_enc_T_1 = mux(can_to_q_2, UInt<4>(0h4), _to_q_oh_enc_T)
node _to_q_oh_enc_T_2 = mux(can_to_q_1, UInt<4>(0h2), _to_q_oh_enc_T_1)
node to_q_oh_enc = mux(can_to_q_0, UInt<4>(0h1), _to_q_oh_enc_T_2)
node to_q_oh_0 = bits(to_q_oh_enc, 0, 0)
node to_q_oh_1 = bits(to_q_oh_enc, 1, 1)
node to_q_oh_2 = bits(to_q_oh_enc, 2, 2)
node to_q_oh_3 = bits(to_q_oh_enc, 3, 3)
node to_q_lo = cat(to_q_oh_1, to_q_oh_0)
node to_q_hi = cat(to_q_oh_3, to_q_oh_2)
node _to_q_T = cat(to_q_hi, to_q_lo)
node to_q_hi_1 = bits(_to_q_T, 3, 2)
node to_q_lo_1 = bits(_to_q_T, 1, 0)
node _to_q_T_1 = orr(to_q_hi_1)
node _to_q_T_2 = or(to_q_hi_1, to_q_lo_1)
node _to_q_T_3 = bits(_to_q_T_2, 1, 1)
node to_q = cat(_to_q_T_1, _to_q_T_3)
node _T_7 = or(can_to_q_0, can_to_q_1)
node _T_8 = or(_T_7, can_to_q_2)
node _T_9 = or(_T_8, can_to_q_3)
when _T_9 :
node _head_T = mux(to_q_oh_0, heads[0], UInt<1>(0h0))
node _head_T_1 = mux(to_q_oh_1, heads[1], UInt<1>(0h0))
node _head_T_2 = mux(to_q_oh_2, heads[2], UInt<1>(0h0))
node _head_T_3 = mux(to_q_oh_3, heads[3], UInt<1>(0h0))
node _head_T_4 = or(_head_T, _head_T_1)
node _head_T_5 = or(_head_T_4, _head_T_2)
node _head_T_6 = or(_head_T_5, _head_T_3)
wire head : UInt<1>
connect head, _head_T_6
node _heads_T = mux(to_q_oh_0, UInt<1>(0h0), UInt<1>(0h0))
node _heads_T_1 = mux(to_q_oh_1, UInt<1>(0h1), UInt<1>(0h0))
node _heads_T_2 = mux(to_q_oh_2, UInt<1>(0h0), UInt<1>(0h0))
node _heads_T_3 = mux(to_q_oh_3, UInt<1>(0h0), UInt<1>(0h0))
node _heads_T_4 = or(_heads_T, _heads_T_1)
node _heads_T_5 = or(_heads_T_4, _heads_T_2)
node _heads_T_6 = or(_heads_T_5, _heads_T_3)
wire _heads_WIRE_1 : UInt<1>
connect _heads_WIRE_1, _heads_T_6
node _heads_T_7 = eq(head, _heads_WIRE_1)
node _heads_T_8 = mux(to_q_oh_0, UInt<1>(0h0), UInt<1>(0h0))
node _heads_T_9 = mux(to_q_oh_1, UInt<1>(0h1), UInt<1>(0h0))
node _heads_T_10 = mux(to_q_oh_2, UInt<1>(0h0), UInt<1>(0h0))
node _heads_T_11 = mux(to_q_oh_3, UInt<1>(0h0), UInt<1>(0h0))
node _heads_T_12 = or(_heads_T_8, _heads_T_9)
node _heads_T_13 = or(_heads_T_12, _heads_T_10)
node _heads_T_14 = or(_heads_T_13, _heads_T_11)
wire _heads_WIRE_2 : UInt<1>
connect _heads_WIRE_2, _heads_T_14
node _heads_T_15 = add(head, UInt<1>(0h1))
node _heads_T_16 = tail(_heads_T_15, 1)
node _heads_T_17 = mux(_heads_T_7, _heads_WIRE_2, _heads_T_16)
connect heads[to_q], _heads_T_17
when to_q_oh_0 :
connect qs_0.io.enq.valid, UInt<1>(0h1)
read mport qs_0_io_enq_bits_MPORT = mem[head], clock
connect qs_0.io.enq.bits.payload, qs_0_io_enq_bits_MPORT.payload
connect qs_0.io.enq.bits.tail, qs_0_io_enq_bits_MPORT.tail
connect qs_0.io.enq.bits.head, qs_0_io_enq_bits_MPORT.head
when to_q_oh_1 :
connect qs_1.io.enq.valid, UInt<1>(0h1)
read mport qs_1_io_enq_bits_MPORT = mem[head], clock
connect qs_1.io.enq.bits.payload, qs_1_io_enq_bits_MPORT.payload
connect qs_1.io.enq.bits.tail, qs_1_io_enq_bits_MPORT.tail
connect qs_1.io.enq.bits.head, qs_1_io_enq_bits_MPORT.head
when to_q_oh_2 :
connect qs_2.io.enq.valid, UInt<1>(0h1)
read mport qs_2_io_enq_bits_MPORT = mem[head], clock
connect qs_2.io.enq.bits.payload, qs_2_io_enq_bits_MPORT.payload
connect qs_2.io.enq.bits.tail, qs_2_io_enq_bits_MPORT.tail
connect qs_2.io.enq.bits.head, qs_2_io_enq_bits_MPORT.head
when to_q_oh_3 :
connect qs_3.io.enq.valid, UInt<1>(0h1)
read mport qs_3_io_enq_bits_MPORT = mem[head], clock
connect qs_3.io.enq.bits.payload, qs_3_io_enq_bits_MPORT.payload
connect qs_3.io.enq.bits.tail, qs_3_io_enq_bits_MPORT.tail
connect qs_3.io.enq.bits.head, qs_3_io_enq_bits_MPORT.head
connect io.deq[0].bits, qs_0.io.deq.bits
connect io.deq[0].valid, qs_0.io.deq.valid
connect qs_0.io.deq.ready, io.deq[0].ready
connect io.deq[1].bits, qs_1.io.deq.bits
connect io.deq[1].valid, qs_1.io.deq.valid
connect qs_1.io.deq.ready, io.deq[1].ready
connect io.deq[2].bits, qs_2.io.deq.bits
connect io.deq[2].valid, qs_2.io.deq.valid
connect qs_2.io.deq.ready, io.deq[2].ready
connect io.deq[3].bits, qs_3.io.deq.bits
connect io.deq[3].valid, qs_3.io.deq.valid
connect qs_3.io.deq.ready, io.deq[3].ready | module InputBuffer_21( // @[InputUnit.scala:49:7]
input clock, // @[InputUnit.scala:49:7]
input reset, // @[InputUnit.scala:49:7]
input io_enq_0_valid, // @[InputUnit.scala:51:14]
input io_enq_0_bits_head, // @[InputUnit.scala:51:14]
input io_enq_0_bits_tail, // @[InputUnit.scala:51:14]
input [36:0] io_enq_0_bits_payload, // @[InputUnit.scala:51:14]
input [1:0] io_enq_0_bits_virt_channel_id, // @[InputUnit.scala:51:14]
input io_deq_0_ready, // @[InputUnit.scala:51:14]
output io_deq_0_valid, // @[InputUnit.scala:51:14]
output io_deq_0_bits_head, // @[InputUnit.scala:51:14]
output io_deq_0_bits_tail, // @[InputUnit.scala:51:14]
output [36:0] io_deq_0_bits_payload, // @[InputUnit.scala:51:14]
input io_deq_1_ready, // @[InputUnit.scala:51:14]
output io_deq_1_valid, // @[InputUnit.scala:51:14]
output io_deq_1_bits_head, // @[InputUnit.scala:51:14]
output io_deq_1_bits_tail, // @[InputUnit.scala:51:14]
output [36:0] io_deq_1_bits_payload, // @[InputUnit.scala:51:14]
output io_deq_2_bits_head, // @[InputUnit.scala:51:14]
output io_deq_2_bits_tail, // @[InputUnit.scala:51:14]
output [36:0] io_deq_2_bits_payload, // @[InputUnit.scala:51:14]
output io_deq_3_bits_head, // @[InputUnit.scala:51:14]
output io_deq_3_bits_tail, // @[InputUnit.scala:51:14]
output [36:0] io_deq_3_bits_payload // @[InputUnit.scala:51:14]
);
wire _qs_3_io_enq_ready; // @[InputUnit.scala:90:49]
wire _qs_2_io_enq_ready; // @[InputUnit.scala:90:49]
wire _qs_1_io_enq_ready; // @[InputUnit.scala:90:49]
wire _qs_0_io_enq_ready; // @[InputUnit.scala:90:49]
wire [38:0] _mem_ext_R0_data; // @[InputUnit.scala:85:18]
wire [38:0] _mem_ext_R1_data; // @[InputUnit.scala:85:18]
wire [38:0] _mem_ext_R2_data; // @[InputUnit.scala:85:18]
wire [38:0] _mem_ext_R3_data; // @[InputUnit.scala:85:18]
reg heads_0; // @[InputUnit.scala:86:24]
reg heads_1; // @[InputUnit.scala:86:24]
reg heads_2; // @[InputUnit.scala:86:24]
reg heads_3; // @[InputUnit.scala:86:24]
reg tails_0; // @[InputUnit.scala:87:24]
reg tails_1; // @[InputUnit.scala:87:24]
reg tails_2; // @[InputUnit.scala:87:24]
reg tails_3; // @[InputUnit.scala:87:24]
wire _tails_T_12 = io_enq_0_bits_virt_channel_id == 2'h0; // @[Mux.scala:32:36]
wire _tails_T_22 = io_enq_0_bits_virt_channel_id == 2'h1; // @[Mux.scala:32:36]
wire _tails_T_14 = io_enq_0_bits_virt_channel_id == 2'h2; // @[Mux.scala:32:36]
wire direct_to_q = (_tails_T_12 & _qs_0_io_enq_ready | _tails_T_22 & _qs_1_io_enq_ready | _tails_T_14 & _qs_2_io_enq_ready | (&io_enq_0_bits_virt_channel_id) & _qs_3_io_enq_ready) & (_tails_T_12 & heads_0 == tails_0 | _tails_T_22 & heads_1 == tails_1 | _tails_T_14 & heads_2 == tails_2 | (&io_enq_0_bits_virt_channel_id) & heads_3 == tails_3); // @[Mux.scala:30:73, :32:36]
wire mem_MPORT_en = io_enq_0_valid & ~direct_to_q; // @[InputUnit.scala:96:62, :100:{27,30}]
wire [3:0] _GEN = {{tails_3}, {tails_2}, {tails_1}, {tails_0}}; // @[InputUnit.scala:87:24, :102:16]
wire _GEN_0 = io_enq_0_bits_virt_channel_id == 2'h0; // @[InputUnit.scala:103:45]
wire _GEN_1 = io_enq_0_bits_virt_channel_id == 2'h1; // @[InputUnit.scala:103:45]
wire _GEN_2 = io_enq_0_bits_virt_channel_id == 2'h2; // @[InputUnit.scala:103:45]
wire _GEN_3 = io_enq_0_valid & direct_to_q; // @[InputUnit.scala:96:62, :107:34]
wire can_to_q_0 = heads_0 != tails_0 & _qs_0_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire can_to_q_1 = heads_1 != tails_1 & _qs_1_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire can_to_q_2 = heads_2 != tails_2 & _qs_2_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire can_to_q_3 = heads_3 != tails_3 & _qs_3_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire [3:0] to_q_oh_enc = can_to_q_0 ? 4'h1 : can_to_q_1 ? 4'h2 : can_to_q_2 ? 4'h4 : {can_to_q_3, 3'h0}; // @[OneHot.scala:58:35]
wire _GEN_4 = can_to_q_0 | can_to_q_1 | can_to_q_2 | can_to_q_3; // @[package.scala:81:59]
wire head = to_q_oh_enc[0] & heads_0 | to_q_oh_enc[1] & heads_1 | to_q_oh_enc[2] & heads_2 | to_q_oh_enc[3] & heads_3; // @[OneHot.scala:83:30]
wire _GEN_5 = _GEN_4 & to_q_oh_enc[0]; // @[OneHot.scala:83:30]
wire _GEN_6 = _GEN_4 & to_q_oh_enc[1]; // @[OneHot.scala:83:30]
wire _GEN_7 = _GEN_4 & to_q_oh_enc[2]; // @[OneHot.scala:83:30]
wire _GEN_8 = _GEN_4 & to_q_oh_enc[3]; // @[OneHot.scala:83:30]
wire _tails_T_25 = _GEN[io_enq_0_bits_virt_channel_id] == _tails_T_22 ? _tails_T_22 : _GEN[io_enq_0_bits_virt_channel_id] - 1'h1; // @[Mux.scala:32:36]
wire _to_q_T_2 = to_q_oh_enc[3] | to_q_oh_enc[1]; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] to_q = {|(to_q_oh_enc[3:2]), _to_q_T_2}; // @[OneHot.scala:30:18, :32:{10,14,28}]
wire _heads_T_17 = head == to_q_oh_enc[1] ? to_q_oh_enc[1] : head - 1'h1; // @[OneHot.scala:83:30]
always @(posedge clock) begin // @[InputUnit.scala:49:7]
if (reset) begin // @[InputUnit.scala:49:7]
heads_0 <= 1'h0; // @[InputUnit.scala:49:7, :86:24]
heads_1 <= 1'h1; // @[InputUnit.scala:49:7, :86:24]
heads_2 <= 1'h0; // @[InputUnit.scala:49:7, :86:24]
heads_3 <= 1'h0; // @[InputUnit.scala:49:7, :86:24]
tails_0 <= 1'h0; // @[InputUnit.scala:49:7, :87:24]
tails_1 <= 1'h1; // @[InputUnit.scala:49:7, :87:24]
tails_2 <= 1'h0; // @[InputUnit.scala:49:7, :87:24]
tails_3 <= 1'h0; // @[InputUnit.scala:49:7, :87:24]
end
else begin // @[InputUnit.scala:49:7]
if (_GEN_4 & {to_q_oh_enc[3:2], _to_q_T_2} == 3'h0) // @[OneHot.scala:30:18, :32:{10,14,28}]
heads_0 <= _heads_T_17; // @[InputUnit.scala:86:24, :122:27]
if (_GEN_4 & to_q == 2'h1) // @[OneHot.scala:32:10]
heads_1 <= _heads_T_17; // @[InputUnit.scala:86:24, :122:27]
if (_GEN_4 & to_q == 2'h2) // @[OneHot.scala:32:10]
heads_2 <= _heads_T_17; // @[InputUnit.scala:86:24, :122:27]
if (_GEN_4 & (&to_q)) // @[OneHot.scala:32:10]
heads_3 <= _heads_T_17; // @[InputUnit.scala:86:24, :122:27]
if (mem_MPORT_en & _GEN_0) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_0 <= _tails_T_25; // @[InputUnit.scala:87:24, :103:51]
if (mem_MPORT_en & _GEN_1) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_1 <= _tails_T_25; // @[InputUnit.scala:87:24, :103:51]
if (mem_MPORT_en & _GEN_2) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_2 <= _tails_T_25; // @[InputUnit.scala:87:24, :103:51]
if (mem_MPORT_en & (&io_enq_0_bits_virt_channel_id)) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_3 <= _tails_T_25; // @[InputUnit.scala:87:24, :103:51]
end
always @(posedge) |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_48 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0)
node _source_ok_T = shr(io.in.a.bits.source, 11)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits = bits(_uncommonBits_T, 10, 0)
node _T_4 = shr(io.in.a.bits.source, 11)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<11>(0h40f))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0)
node _T_24 = shr(io.in.a.bits.source, 11)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = and(_T_32, _T_37)
node _T_39 = or(UInt<1>(0h0), _T_38)
node _T_40 = and(_T_31, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_40, UInt<1>(0h1), "") : assert_2
node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_46 = and(_T_44, _T_45)
node _T_47 = or(UInt<1>(0h0), _T_46)
node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = and(_T_47, _T_52)
node _T_54 = or(UInt<1>(0h0), _T_53)
node _T_55 = and(UInt<1>(0h0), _T_54)
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(_T_55, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_55, UInt<1>(0h1), "") : assert_3
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_62, UInt<1>(0h1), "") : assert_5
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(is_aligned, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_69, UInt<1>(0h1), "") : assert_7
node _T_73 = not(io.in.a.bits.mask)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_74, UInt<1>(0h1), "") : assert_8
node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_78, UInt<1>(0h1), "") : assert_9
node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_82 :
node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_85 = and(_T_83, _T_84)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0)
node _T_86 = shr(io.in.a.bits.source, 11)
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_89 = and(_T_87, _T_88)
node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f))
node _T_91 = and(_T_89, _T_90)
node _T_92 = and(_T_85, _T_91)
node _T_93 = or(UInt<1>(0h0), _T_92)
node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(_T_93, _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_102, UInt<1>(0h1), "") : assert_10
node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_108 = and(_T_106, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = and(_T_109, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_115)
node _T_117 = and(UInt<1>(0h0), _T_116)
node _T_118 = asUInt(reset)
node _T_119 = eq(_T_118, UInt<1>(0h0))
when _T_119 :
node _T_120 = eq(_T_117, UInt<1>(0h0))
when _T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_117, UInt<1>(0h1), "") : assert_11
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_124, UInt<1>(0h1), "") : assert_13
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(is_aligned, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_131, UInt<1>(0h1), "") : assert_15
node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_136 = asUInt(reset)
node _T_137 = eq(_T_136, UInt<1>(0h0))
when _T_137 :
node _T_138 = eq(_T_135, UInt<1>(0h0))
when _T_138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_135, UInt<1>(0h1), "") : assert_16
node _T_139 = not(io.in.a.bits.mask)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_140, UInt<1>(0h1), "") : assert_17
node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_T_144, UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_144, UInt<1>(0h1), "") : assert_18
node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_148 :
node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0)
node _T_152 = shr(io.in.a.bits.source, 11)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f))
node _T_157 = and(_T_155, _T_156)
node _T_158 = and(_T_151, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_159, UInt<1>(0h1), "") : assert_19
node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_165 = and(_T_163, _T_164)
node _T_166 = or(UInt<1>(0h0), _T_165)
node _T_167 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_168 = cvt(_T_167)
node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000)))
node _T_170 = asSInt(_T_169)
node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0)))
node _T_172 = and(_T_166, _T_171)
node _T_173 = or(UInt<1>(0h0), _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_173, UInt<1>(0h1), "") : assert_20
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(is_aligned, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(io.in.a.bits.mask, mask)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_187, UInt<1>(0h1), "") : assert_24
node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_191, UInt<1>(0h1), "") : assert_25
node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_195 :
node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0)
node _T_199 = shr(io.in.a.bits.source, 11)
node _T_200 = eq(_T_199, UInt<1>(0h0))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f))
node _T_204 = and(_T_202, _T_203)
node _T_205 = and(_T_198, _T_204)
node _T_206 = or(UInt<1>(0h0), _T_205)
node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_209 = and(_T_207, _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = and(_T_210, _T_215)
node _T_217 = or(UInt<1>(0h0), _T_216)
node _T_218 = and(_T_206, _T_217)
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_218, UInt<1>(0h1), "") : assert_26
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_225 = asUInt(reset)
node _T_226 = eq(_T_225, UInt<1>(0h0))
when _T_226 :
node _T_227 = eq(is_aligned, UInt<1>(0h0))
when _T_227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(_T_228, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_228, UInt<1>(0h1), "") : assert_29
node _T_232 = eq(io.in.a.bits.mask, mask)
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_236 :
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_239 = and(_T_237, _T_238)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0)
node _T_240 = shr(io.in.a.bits.source, 11)
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_243 = and(_T_241, _T_242)
node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f))
node _T_245 = and(_T_243, _T_244)
node _T_246 = and(_T_239, _T_245)
node _T_247 = or(UInt<1>(0h0), _T_246)
node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_253 = cvt(_T_252)
node _T_254 = and(_T_253, asSInt(UInt<17>(0h10000)))
node _T_255 = asSInt(_T_254)
node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0)))
node _T_257 = and(_T_251, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = and(_T_247, _T_258)
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(_T_259, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_259, UInt<1>(0h1), "") : assert_31
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_266 = asUInt(reset)
node _T_267 = eq(_T_266, UInt<1>(0h0))
when _T_267 :
node _T_268 = eq(is_aligned, UInt<1>(0h0))
when _T_268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_270 = asUInt(reset)
node _T_271 = eq(_T_270, UInt<1>(0h0))
when _T_271 :
node _T_272 = eq(_T_269, UInt<1>(0h0))
when _T_272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_269, UInt<1>(0h1), "") : assert_34
node _T_273 = not(mask)
node _T_274 = and(io.in.a.bits.mask, _T_273)
node _T_275 = eq(_T_274, UInt<1>(0h0))
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(_T_275, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_275, UInt<1>(0h1), "") : assert_35
node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_279 :
node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_282 = and(_T_280, _T_281)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0)
node _T_283 = shr(io.in.a.bits.source, 11)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_286 = and(_T_284, _T_285)
node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f))
node _T_288 = and(_T_286, _T_287)
node _T_289 = and(_T_282, _T_288)
node _T_290 = or(UInt<1>(0h0), _T_289)
node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_292 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_293 = cvt(_T_292)
node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000)))
node _T_295 = asSInt(_T_294)
node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0)))
node _T_297 = and(_T_291, _T_296)
node _T_298 = or(UInt<1>(0h0), _T_297)
node _T_299 = and(_T_290, _T_298)
node _T_300 = asUInt(reset)
node _T_301 = eq(_T_300, UInt<1>(0h0))
when _T_301 :
node _T_302 = eq(_T_299, UInt<1>(0h0))
when _T_302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_299, UInt<1>(0h1), "") : assert_36
node _T_303 = asUInt(reset)
node _T_304 = eq(_T_303, UInt<1>(0h0))
when _T_304 :
node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(is_aligned, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_309, UInt<1>(0h1), "") : assert_39
node _T_313 = eq(io.in.a.bits.mask, mask)
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_313, UInt<1>(0h1), "") : assert_40
node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_317 :
node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0)
node _T_321 = shr(io.in.a.bits.source, 11)
node _T_322 = eq(_T_321, UInt<1>(0h0))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f))
node _T_326 = and(_T_324, _T_325)
node _T_327 = and(_T_320, _T_326)
node _T_328 = or(UInt<1>(0h0), _T_327)
node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_330 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_331 = cvt(_T_330)
node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000)))
node _T_333 = asSInt(_T_332)
node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0)))
node _T_335 = and(_T_329, _T_334)
node _T_336 = or(UInt<1>(0h0), _T_335)
node _T_337 = and(_T_328, _T_336)
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(_T_337, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_337, UInt<1>(0h1), "") : assert_41
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(is_aligned, UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_347, UInt<1>(0h1), "") : assert_44
node _T_351 = eq(io.in.a.bits.mask, mask)
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_351, UInt<1>(0h1), "") : assert_45
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0)
node _T_359 = shr(io.in.a.bits.source, 11)
node _T_360 = eq(_T_359, UInt<1>(0h0))
node _T_361 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_362 = and(_T_360, _T_361)
node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f))
node _T_364 = and(_T_362, _T_363)
node _T_365 = and(_T_358, _T_364)
node _T_366 = or(UInt<1>(0h0), _T_365)
node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_368 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_369 = cvt(_T_368)
node _T_370 = and(_T_369, asSInt(UInt<17>(0h10000)))
node _T_371 = asSInt(_T_370)
node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0)))
node _T_373 = and(_T_367, _T_372)
node _T_374 = or(UInt<1>(0h0), _T_373)
node _T_375 = and(_T_366, _T_374)
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_375, UInt<1>(0h1), "") : assert_46
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(is_aligned, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_385, UInt<1>(0h1), "") : assert_49
node _T_389 = eq(io.in.a.bits.mask, mask)
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_389, UInt<1>(0h1), "") : assert_50
node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_393, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_397, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 11)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_401 :
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_405, UInt<1>(0h1), "") : assert_54
node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_409, UInt<1>(0h1), "") : assert_55
node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_414 = asUInt(reset)
node _T_415 = eq(_T_414, UInt<1>(0h0))
when _T_415 :
node _T_416 = eq(_T_413, UInt<1>(0h0))
when _T_416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_413, UInt<1>(0h1), "") : assert_56
node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_418 = asUInt(reset)
node _T_419 = eq(_T_418, UInt<1>(0h0))
when _T_419 :
node _T_420 = eq(_T_417, UInt<1>(0h0))
when _T_420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_417, UInt<1>(0h1), "") : assert_57
node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_421 :
node _T_422 = asUInt(reset)
node _T_423 = eq(_T_422, UInt<1>(0h0))
when _T_423 :
node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(sink_ok, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_T_428, UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_428, UInt<1>(0h1), "") : assert_60
node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_432, UInt<1>(0h1), "") : assert_61
node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_436, UInt<1>(0h1), "") : assert_62
node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(_T_440, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_440, UInt<1>(0h1), "") : assert_63
node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_445 = or(UInt<1>(0h0), _T_444)
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_445, UInt<1>(0h1), "") : assert_64
node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_449 :
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(sink_ok, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_457 = asUInt(reset)
node _T_458 = eq(_T_457, UInt<1>(0h0))
when _T_458 :
node _T_459 = eq(_T_456, UInt<1>(0h0))
when _T_459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_456, UInt<1>(0h1), "") : assert_67
node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(_T_460, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_460, UInt<1>(0h1), "") : assert_68
node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_464, UInt<1>(0h1), "") : assert_69
node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_469 = or(_T_468, io.in.d.bits.corrupt)
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_469, UInt<1>(0h1), "") : assert_70
node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_474 = or(UInt<1>(0h0), _T_473)
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_474, UInt<1>(0h1), "") : assert_71
node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_478 :
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_482, UInt<1>(0h1), "") : assert_73
node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_486, UInt<1>(0h1), "") : assert_74
node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_491 = or(UInt<1>(0h0), _T_490)
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_491, UInt<1>(0h1), "") : assert_75
node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_495 :
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_499, UInt<1>(0h1), "") : assert_77
node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_504 = or(_T_503, io.in.d.bits.corrupt)
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(_T_504, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_504, UInt<1>(0h1), "") : assert_78
node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_509, UInt<1>(0h1), "") : assert_79
node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_513 :
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_T_517, UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_517, UInt<1>(0h1), "") : assert_81
node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_521, UInt<1>(0h1), "") : assert_82
node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_526 = or(UInt<1>(0h0), _T_525)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_526, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<26>(0h0)
connect _WIRE.bits.source, UInt<11>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_530, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<26>(0h0)
connect _WIRE_2.bits.source, UInt<11>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_534, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_538, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_542 = eq(a_first, UInt<1>(0h0))
node _T_543 = and(io.in.a.valid, _T_542)
when _T_543 :
node _T_544 = eq(io.in.a.bits.opcode, opcode)
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_544, UInt<1>(0h1), "") : assert_87
node _T_548 = eq(io.in.a.bits.param, param)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_548, UInt<1>(0h1), "") : assert_88
node _T_552 = eq(io.in.a.bits.size, size)
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(_T_552, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_552, UInt<1>(0h1), "") : assert_89
node _T_556 = eq(io.in.a.bits.source, source)
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_556, UInt<1>(0h1), "") : assert_90
node _T_560 = eq(io.in.a.bits.address, address)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_560, UInt<1>(0h1), "") : assert_91
node _T_564 = and(io.in.a.ready, io.in.a.valid)
node _T_565 = and(_T_564, a_first)
when _T_565 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_566 = eq(d_first, UInt<1>(0h0))
node _T_567 = and(io.in.d.valid, _T_566)
when _T_567 :
node _T_568 = eq(io.in.d.bits.opcode, opcode_1)
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_568, UInt<1>(0h1), "") : assert_92
node _T_572 = eq(io.in.d.bits.param, param_1)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_572, UInt<1>(0h1), "") : assert_93
node _T_576 = eq(io.in.d.bits.size, size_1)
node _T_577 = asUInt(reset)
node _T_578 = eq(_T_577, UInt<1>(0h0))
when _T_578 :
node _T_579 = eq(_T_576, UInt<1>(0h0))
when _T_579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_576, UInt<1>(0h1), "") : assert_94
node _T_580 = eq(io.in.d.bits.source, source_1)
node _T_581 = asUInt(reset)
node _T_582 = eq(_T_581, UInt<1>(0h0))
when _T_582 :
node _T_583 = eq(_T_580, UInt<1>(0h0))
when _T_583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_580, UInt<1>(0h1), "") : assert_95
node _T_584 = eq(io.in.d.bits.sink, sink)
node _T_585 = asUInt(reset)
node _T_586 = eq(_T_585, UInt<1>(0h0))
when _T_586 :
node _T_587 = eq(_T_584, UInt<1>(0h0))
when _T_587 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_584, UInt<1>(0h1), "") : assert_96
node _T_588 = eq(io.in.d.bits.denied, denied)
node _T_589 = asUInt(reset)
node _T_590 = eq(_T_589, UInt<1>(0h0))
when _T_590 :
node _T_591 = eq(_T_588, UInt<1>(0h0))
when _T_591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_588, UInt<1>(0h1), "") : assert_97
node _T_592 = and(io.in.d.ready, io.in.d.valid)
node _T_593 = and(_T_592, d_first)
when _T_593 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0)
regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0)
regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1040>
connect a_set, UInt<1040>(0h0)
wire a_set_wo_ready : UInt<1040>
connect a_set_wo_ready, UInt<1040>(0h0)
wire a_opcodes_set : UInt<4160>
connect a_opcodes_set, UInt<4160>(0h0)
wire a_sizes_set : UInt<4160>
connect a_sizes_set, UInt<4160>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_594 = and(io.in.a.valid, a_first_1)
node _T_595 = and(_T_594, UInt<1>(0h1))
when _T_595 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_596 = and(io.in.a.ready, io.in.a.valid)
node _T_597 = and(_T_596, a_first_1)
node _T_598 = and(_T_597, UInt<1>(0h1))
when _T_598 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_599 = dshr(inflight, io.in.a.bits.source)
node _T_600 = bits(_T_599, 0, 0)
node _T_601 = eq(_T_600, UInt<1>(0h0))
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_601, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1040>
connect d_clr, UInt<1040>(0h0)
wire d_clr_wo_ready : UInt<1040>
connect d_clr_wo_ready, UInt<1040>(0h0)
wire d_opcodes_clr : UInt<4160>
connect d_opcodes_clr, UInt<4160>(0h0)
wire d_sizes_clr : UInt<4160>
connect d_sizes_clr, UInt<4160>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_605 = and(io.in.d.valid, d_first_1)
node _T_606 = and(_T_605, UInt<1>(0h1))
node _T_607 = eq(d_release_ack, UInt<1>(0h0))
node _T_608 = and(_T_606, _T_607)
when _T_608 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_609 = and(io.in.d.ready, io.in.d.valid)
node _T_610 = and(_T_609, d_first_1)
node _T_611 = and(_T_610, UInt<1>(0h1))
node _T_612 = eq(d_release_ack, UInt<1>(0h0))
node _T_613 = and(_T_611, _T_612)
when _T_613 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_614 = and(io.in.d.valid, d_first_1)
node _T_615 = and(_T_614, UInt<1>(0h1))
node _T_616 = eq(d_release_ack, UInt<1>(0h0))
node _T_617 = and(_T_615, _T_616)
when _T_617 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_618 = dshr(inflight, io.in.d.bits.source)
node _T_619 = bits(_T_618, 0, 0)
node _T_620 = or(_T_619, same_cycle_resp)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_620, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_626 = or(_T_624, _T_625)
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_626, UInt<1>(0h1), "") : assert_100
node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_630, UInt<1>(0h1), "") : assert_101
else :
node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_636 = or(_T_634, _T_635)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_636, UInt<1>(0h1), "") : assert_102
node _T_640 = eq(io.in.d.bits.size, a_size_lookup)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_640, UInt<1>(0h1), "") : assert_103
node _T_644 = and(io.in.d.valid, d_first_1)
node _T_645 = and(_T_644, a_first_1)
node _T_646 = and(_T_645, io.in.a.valid)
node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_648 = and(_T_646, _T_647)
node _T_649 = eq(d_release_ack, UInt<1>(0h0))
node _T_650 = and(_T_648, _T_649)
when _T_650 :
node _T_651 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_652 = or(_T_651, io.in.a.ready)
node _T_653 = asUInt(reset)
node _T_654 = eq(_T_653, UInt<1>(0h0))
when _T_654 :
node _T_655 = eq(_T_652, UInt<1>(0h0))
when _T_655 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_652, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_97
node _T_656 = orr(inflight)
node _T_657 = eq(_T_656, UInt<1>(0h0))
node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_659 = or(_T_657, _T_658)
node _T_660 = lt(watchdog, plusarg_reader.out)
node _T_661 = or(_T_659, _T_660)
node _T_662 = asUInt(reset)
node _T_663 = eq(_T_662, UInt<1>(0h0))
when _T_663 :
node _T_664 = eq(_T_661, UInt<1>(0h0))
when _T_664 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_661, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_665 = and(io.in.a.ready, io.in.a.valid)
node _T_666 = and(io.in.d.ready, io.in.d.valid)
node _T_667 = or(_T_665, _T_666)
when _T_667 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0)
regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0)
regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<26>(0h0)
connect _c_first_WIRE.bits.source, UInt<11>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<26>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<11>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1040>
connect c_set, UInt<1040>(0h0)
wire c_set_wo_ready : UInt<1040>
connect c_set_wo_ready, UInt<1040>(0h0)
wire c_opcodes_set : UInt<4160>
connect c_opcodes_set, UInt<4160>(0h0)
wire c_sizes_set : UInt<4160>
connect c_sizes_set, UInt<4160>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<26>(0h0)
connect _WIRE_6.bits.source, UInt<11>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_668 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<26>(0h0)
connect _WIRE_8.bits.source, UInt<11>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_671 = and(_T_669, _T_670)
node _T_672 = and(_T_668, _T_671)
when _T_672 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<26>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<26>(0h0)
connect _WIRE_10.bits.source, UInt<11>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_674 = and(_T_673, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<26>(0h0)
connect _WIRE_12.bits.source, UInt<11>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_677 = and(_T_675, _T_676)
node _T_678 = and(_T_674, _T_677)
when _T_678 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<26>(0h0)
connect _c_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<26>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<26>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<26>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<26>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<26>(0h0)
connect _WIRE_14.bits.source, UInt<11>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_679 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_680 = bits(_T_679, 0, 0)
node _T_681 = eq(_T_680, UInt<1>(0h0))
node _T_682 = asUInt(reset)
node _T_683 = eq(_T_682, UInt<1>(0h0))
when _T_683 :
node _T_684 = eq(_T_681, UInt<1>(0h0))
when _T_684 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_681, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<26>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<26>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1040>
connect d_clr_1, UInt<1040>(0h0)
wire d_clr_wo_ready_1 : UInt<1040>
connect d_clr_wo_ready_1, UInt<1040>(0h0)
wire d_opcodes_clr_1 : UInt<4160>
connect d_opcodes_clr_1, UInt<4160>(0h0)
wire d_sizes_clr_1 : UInt<4160>
connect d_sizes_clr_1, UInt<4160>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_685 = and(io.in.d.valid, d_first_2)
node _T_686 = and(_T_685, UInt<1>(0h1))
node _T_687 = and(_T_686, d_release_ack_1)
when _T_687 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_688 = and(io.in.d.ready, io.in.d.valid)
node _T_689 = and(_T_688, d_first_2)
node _T_690 = and(_T_689, UInt<1>(0h1))
node _T_691 = and(_T_690, d_release_ack_1)
when _T_691 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_692 = and(io.in.d.valid, d_first_2)
node _T_693 = and(_T_692, UInt<1>(0h1))
node _T_694 = and(_T_693, d_release_ack_1)
when _T_694 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<26>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<26>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<26>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_695 = dshr(inflight_1, io.in.d.bits.source)
node _T_696 = bits(_T_695, 0, 0)
node _T_697 = or(_T_696, same_cycle_resp_1)
node _T_698 = asUInt(reset)
node _T_699 = eq(_T_698, UInt<1>(0h0))
when _T_699 :
node _T_700 = eq(_T_697, UInt<1>(0h0))
when _T_700 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_697, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<26>(0h0)
connect _WIRE_16.bits.source, UInt<11>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_702 = asUInt(reset)
node _T_703 = eq(_T_702, UInt<1>(0h0))
when _T_703 :
node _T_704 = eq(_T_701, UInt<1>(0h0))
when _T_704 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_701, UInt<1>(0h1), "") : assert_108
else :
node _T_705 = eq(io.in.d.bits.size, c_size_lookup)
node _T_706 = asUInt(reset)
node _T_707 = eq(_T_706, UInt<1>(0h0))
when _T_707 :
node _T_708 = eq(_T_705, UInt<1>(0h0))
when _T_708 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_705, UInt<1>(0h1), "") : assert_109
node _T_709 = and(io.in.d.valid, d_first_2)
node _T_710 = and(_T_709, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<26>(0h0)
connect _WIRE_18.bits.source, UInt<11>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_711 = and(_T_710, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<26>(0h0)
connect _WIRE_20.bits.source, UInt<11>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_713 = and(_T_711, _T_712)
node _T_714 = and(_T_713, d_release_ack_1)
node _T_715 = eq(c_probe_ack, UInt<1>(0h0))
node _T_716 = and(_T_714, _T_715)
when _T_716 :
node _T_717 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<26>(0h0)
connect _WIRE_22.bits.source, UInt<11>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_718 = or(_T_717, _WIRE_23.ready)
node _T_719 = asUInt(reset)
node _T_720 = eq(_T_719, UInt<1>(0h0))
when _T_720 :
node _T_721 = eq(_T_718, UInt<1>(0h0))
when _T_721 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_718, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_98
node _T_722 = orr(inflight_1)
node _T_723 = eq(_T_722, UInt<1>(0h0))
node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_725 = or(_T_723, _T_724)
node _T_726 = lt(watchdog_1, plusarg_reader_1.out)
node _T_727 = or(_T_725, _T_726)
node _T_728 = asUInt(reset)
node _T_729 = eq(_T_728, UInt<1>(0h0))
when _T_729 :
node _T_730 = eq(_T_727, UInt<1>(0h0))
when _T_730 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_727, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<26>(0h0)
connect _WIRE_24.bits.source, UInt<11>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_732 = and(io.in.d.ready, io.in.d.valid)
node _T_733 = or(_T_731, _T_732)
when _T_733 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_48( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [25:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_first_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_first_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_first_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_first_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_set_wo_ready_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_set_wo_ready_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_opcodes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_opcodes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_sizes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_sizes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_opcodes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_opcodes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_sizes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_sizes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_probe_ack_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_probe_ack_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_probe_ack_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_probe_ack_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _same_cycle_resp_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _same_cycle_resp_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _same_cycle_resp_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _same_cycle_resp_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _same_cycle_resp_WIRE_4_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _same_cycle_resp_WIRE_5_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52]
wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79]
wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77]
wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35]
wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35]
wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34]
wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34]
wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34]
wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34]
wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76]
wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [25:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 26'h0; // @[Edges.scala:21:{16,24}]
wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_665; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [10:0] source; // @[Monitor.scala:390:22]
reg [25:0] address; // @[Monitor.scala:391:22]
wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_733; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [10:0] source_1; // @[Monitor.scala:541:22]
reg [1039:0] inflight; // @[Monitor.scala:614:27]
reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire [1039:0] a_set; // @[Monitor.scala:626:34]
wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [2047:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [1039:0] d_clr; // @[Monitor.scala:664:34]
wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [1039:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [4159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [4159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1039:0] inflight_1; // @[Monitor.scala:726:35]
wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [1039:0] d_clr_1; // @[Monitor.scala:774:34]
wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113]
wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_141 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_158
connect io_out_sink_valid_1.clock, clock
connect io_out_sink_valid_1.reset, reset
connect io_out_sink_valid_1.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_valid_1.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_141( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_158 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_59 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0)
node _source_ok_T_25 = shr(io.in.a.bits.source, 3)
node _source_ok_T_26 = eq(_source_ok_T_25, UInt<3>(0h4))
node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27)
node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<3>(0h7))
node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29)
node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h2a))
wire _source_ok_WIRE : UInt<1>[8]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_30
connect _source_ok_WIRE[6], _source_ok_T_31
connect _source_ok_WIRE[7], _source_ok_T_32
node _source_ok_T_33 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[2])
node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[3])
node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[4])
node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[5])
node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[6])
node source_ok = or(_source_ok_T_38, _source_ok_WIRE[7])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4))
node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3)
node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3)
node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit)
node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2)
node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T)
node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit)
node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2)
node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1)
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit)
node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2)
node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2)
node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit)
node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2)
node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit)
node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2)
node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4)
node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit)
node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2)
node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5)
node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit)
node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2)
node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6)
node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit)
node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2)
node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_eq_8 = and(mask_sub_4_2, mask_nbit)
node _mask_acc_T_8 = and(mask_size, mask_eq_8)
node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8)
node mask_eq_9 = and(mask_sub_4_2, mask_bit)
node _mask_acc_T_9 = and(mask_size, mask_eq_9)
node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9)
node mask_eq_10 = and(mask_sub_5_2, mask_nbit)
node _mask_acc_T_10 = and(mask_size, mask_eq_10)
node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10)
node mask_eq_11 = and(mask_sub_5_2, mask_bit)
node _mask_acc_T_11 = and(mask_size, mask_eq_11)
node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11)
node mask_eq_12 = and(mask_sub_6_2, mask_nbit)
node _mask_acc_T_12 = and(mask_size, mask_eq_12)
node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12)
node mask_eq_13 = and(mask_sub_6_2, mask_bit)
node _mask_acc_T_13 = and(mask_size, mask_eq_13)
node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13)
node mask_eq_14 = and(mask_sub_7_2, mask_nbit)
node _mask_acc_T_14 = and(mask_size, mask_eq_14)
node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14)
node mask_eq_15 = and(mask_sub_7_2, mask_bit)
node _mask_acc_T_15 = and(mask_size, mask_eq_15)
node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15)
node mask_lo_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo)
node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8)
node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10)
node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo)
node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12)
node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14)
node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0)
node _T_64 = shr(io.in.a.bits.source, 3)
node _T_65 = eq(_T_64, UInt<3>(0h4))
node _T_66 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_67 = and(_T_65, _T_66)
node _T_68 = leq(uncommonBits_4, UInt<3>(0h7))
node _T_69 = and(_T_67, _T_68)
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_72 = cvt(_T_71)
node _T_73 = and(_T_72, asSInt(UInt<1>(0h0)))
node _T_74 = asSInt(_T_73)
node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0)))
node _T_76 = or(_T_70, _T_75)
node _T_77 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_78 = eq(_T_77, UInt<1>(0h0))
node _T_79 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_80 = cvt(_T_79)
node _T_81 = and(_T_80, asSInt(UInt<1>(0h0)))
node _T_82 = asSInt(_T_81)
node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0)))
node _T_84 = or(_T_78, _T_83)
node _T_85 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_86 = eq(_T_85, UInt<1>(0h0))
node _T_87 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_88 = cvt(_T_87)
node _T_89 = and(_T_88, asSInt(UInt<1>(0h0)))
node _T_90 = asSInt(_T_89)
node _T_91 = eq(_T_90, asSInt(UInt<1>(0h0)))
node _T_92 = or(_T_86, _T_91)
node _T_93 = and(_T_11, _T_24)
node _T_94 = and(_T_93, _T_37)
node _T_95 = and(_T_94, _T_50)
node _T_96 = and(_T_95, _T_63)
node _T_97 = and(_T_96, _T_76)
node _T_98 = and(_T_97, _T_84)
node _T_99 = and(_T_98, _T_92)
node _T_100 = asUInt(reset)
node _T_101 = eq(_T_100, UInt<1>(0h0))
when _T_101 :
node _T_102 = eq(_T_99, UInt<1>(0h0))
when _T_102 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_99, UInt<1>(0h1), "") : assert_1
node _T_103 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_103 :
node _T_104 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_105 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_106 = and(_T_104, _T_105)
node _T_107 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_108 = shr(io.in.a.bits.source, 2)
node _T_109 = eq(_T_108, UInt<1>(0h0))
node _T_110 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_111 = and(_T_109, _T_110)
node _T_112 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_113 = and(_T_111, _T_112)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_114 = shr(io.in.a.bits.source, 2)
node _T_115 = eq(_T_114, UInt<1>(0h1))
node _T_116 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_117 = and(_T_115, _T_116)
node _T_118 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_119 = and(_T_117, _T_118)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_120 = shr(io.in.a.bits.source, 2)
node _T_121 = eq(_T_120, UInt<2>(0h2))
node _T_122 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_123 = and(_T_121, _T_122)
node _T_124 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_125 = and(_T_123, _T_124)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_126 = shr(io.in.a.bits.source, 2)
node _T_127 = eq(_T_126, UInt<2>(0h3))
node _T_128 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_129 = and(_T_127, _T_128)
node _T_130 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_131 = and(_T_129, _T_130)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 2, 0)
node _T_132 = shr(io.in.a.bits.source, 3)
node _T_133 = eq(_T_132, UInt<3>(0h4))
node _T_134 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_135 = and(_T_133, _T_134)
node _T_136 = leq(uncommonBits_9, UInt<3>(0h7))
node _T_137 = and(_T_135, _T_136)
node _T_138 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_139 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_140 = or(_T_107, _T_113)
node _T_141 = or(_T_140, _T_119)
node _T_142 = or(_T_141, _T_125)
node _T_143 = or(_T_142, _T_131)
node _T_144 = or(_T_143, _T_137)
node _T_145 = or(_T_144, _T_138)
node _T_146 = or(_T_145, _T_139)
node _T_147 = and(_T_106, _T_146)
node _T_148 = or(UInt<1>(0h0), _T_147)
node _T_149 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_150 = or(UInt<1>(0h0), _T_149)
node _T_151 = xor(io.in.a.bits.address, UInt<28>(0h8000040))
node _T_152 = cvt(_T_151)
node _T_153 = and(_T_152, asSInt(UInt<17>(0h101c0)))
node _T_154 = asSInt(_T_153)
node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0)))
node _T_156 = xor(io.in.a.bits.address, UInt<32>(0h80000040))
node _T_157 = cvt(_T_156)
node _T_158 = and(_T_157, asSInt(UInt<29>(0h100001c0)))
node _T_159 = asSInt(_T_158)
node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0)))
node _T_161 = or(_T_155, _T_160)
node _T_162 = and(_T_150, _T_161)
node _T_163 = or(UInt<1>(0h0), _T_162)
node _T_164 = and(_T_148, _T_163)
node _T_165 = asUInt(reset)
node _T_166 = eq(_T_165, UInt<1>(0h0))
when _T_166 :
node _T_167 = eq(_T_164, UInt<1>(0h0))
when _T_167 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_164, UInt<1>(0h1), "") : assert_2
node _T_168 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_169 = shr(io.in.a.bits.source, 2)
node _T_170 = eq(_T_169, UInt<1>(0h0))
node _T_171 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_172 = and(_T_170, _T_171)
node _T_173 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_174 = and(_T_172, _T_173)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_175 = shr(io.in.a.bits.source, 2)
node _T_176 = eq(_T_175, UInt<1>(0h1))
node _T_177 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_178 = and(_T_176, _T_177)
node _T_179 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_180 = and(_T_178, _T_179)
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_181 = shr(io.in.a.bits.source, 2)
node _T_182 = eq(_T_181, UInt<2>(0h2))
node _T_183 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_184 = and(_T_182, _T_183)
node _T_185 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_186 = and(_T_184, _T_185)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_187 = shr(io.in.a.bits.source, 2)
node _T_188 = eq(_T_187, UInt<2>(0h3))
node _T_189 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_190 = and(_T_188, _T_189)
node _T_191 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_192 = and(_T_190, _T_191)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 2, 0)
node _T_193 = shr(io.in.a.bits.source, 3)
node _T_194 = eq(_T_193, UInt<3>(0h4))
node _T_195 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_196 = and(_T_194, _T_195)
node _T_197 = leq(uncommonBits_14, UInt<3>(0h7))
node _T_198 = and(_T_196, _T_197)
node _T_199 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h2a))
wire _WIRE : UInt<1>[8]
connect _WIRE[0], _T_168
connect _WIRE[1], _T_174
connect _WIRE[2], _T_180
connect _WIRE[3], _T_186
connect _WIRE[4], _T_192
connect _WIRE[5], _T_198
connect _WIRE[6], _T_199
connect _WIRE[7], _T_200
node _T_201 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_202 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_203 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_204 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_205 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_206 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_207 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_208 = mux(_WIRE[6], _T_201, UInt<1>(0h0))
node _T_209 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_210 = or(_T_202, _T_203)
node _T_211 = or(_T_210, _T_204)
node _T_212 = or(_T_211, _T_205)
node _T_213 = or(_T_212, _T_206)
node _T_214 = or(_T_213, _T_207)
node _T_215 = or(_T_214, _T_208)
node _T_216 = or(_T_215, _T_209)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_216
node _T_217 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_218 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_219 = and(_T_217, _T_218)
node _T_220 = or(UInt<1>(0h0), _T_219)
node _T_221 = xor(io.in.a.bits.address, UInt<28>(0h8000040))
node _T_222 = cvt(_T_221)
node _T_223 = and(_T_222, asSInt(UInt<17>(0h101c0)))
node _T_224 = asSInt(_T_223)
node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0)))
node _T_226 = xor(io.in.a.bits.address, UInt<32>(0h80000040))
node _T_227 = cvt(_T_226)
node _T_228 = and(_T_227, asSInt(UInt<29>(0h100001c0)))
node _T_229 = asSInt(_T_228)
node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0)))
node _T_231 = or(_T_225, _T_230)
node _T_232 = and(_T_220, _T_231)
node _T_233 = or(UInt<1>(0h0), _T_232)
node _T_234 = and(_WIRE_1, _T_233)
node _T_235 = asUInt(reset)
node _T_236 = eq(_T_235, UInt<1>(0h0))
when _T_236 :
node _T_237 = eq(_T_234, UInt<1>(0h0))
when _T_237 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_234, UInt<1>(0h1), "") : assert_3
node _T_238 = asUInt(reset)
node _T_239 = eq(_T_238, UInt<1>(0h0))
when _T_239 :
node _T_240 = eq(source_ok, UInt<1>(0h0))
when _T_240 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_241 = geq(io.in.a.bits.size, UInt<3>(0h4))
node _T_242 = asUInt(reset)
node _T_243 = eq(_T_242, UInt<1>(0h0))
when _T_243 :
node _T_244 = eq(_T_241, UInt<1>(0h0))
when _T_244 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_241, UInt<1>(0h1), "") : assert_5
node _T_245 = asUInt(reset)
node _T_246 = eq(_T_245, UInt<1>(0h0))
when _T_246 :
node _T_247 = eq(is_aligned, UInt<1>(0h0))
when _T_247 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_248 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_249 = asUInt(reset)
node _T_250 = eq(_T_249, UInt<1>(0h0))
when _T_250 :
node _T_251 = eq(_T_248, UInt<1>(0h0))
when _T_251 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_248, UInt<1>(0h1), "") : assert_7
node _T_252 = not(io.in.a.bits.mask)
node _T_253 = eq(_T_252, UInt<1>(0h0))
node _T_254 = asUInt(reset)
node _T_255 = eq(_T_254, UInt<1>(0h0))
when _T_255 :
node _T_256 = eq(_T_253, UInt<1>(0h0))
when _T_256 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_253, UInt<1>(0h1), "") : assert_8
node _T_257 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_258 = asUInt(reset)
node _T_259 = eq(_T_258, UInt<1>(0h0))
when _T_259 :
node _T_260 = eq(_T_257, UInt<1>(0h0))
when _T_260 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_257, UInt<1>(0h1), "") : assert_9
node _T_261 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_261 :
node _T_262 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_263 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_264 = and(_T_262, _T_263)
node _T_265 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_266 = shr(io.in.a.bits.source, 2)
node _T_267 = eq(_T_266, UInt<1>(0h0))
node _T_268 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_269 = and(_T_267, _T_268)
node _T_270 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_271 = and(_T_269, _T_270)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_272 = shr(io.in.a.bits.source, 2)
node _T_273 = eq(_T_272, UInt<1>(0h1))
node _T_274 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_275 = and(_T_273, _T_274)
node _T_276 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_277 = and(_T_275, _T_276)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_278 = shr(io.in.a.bits.source, 2)
node _T_279 = eq(_T_278, UInt<2>(0h2))
node _T_280 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_281 = and(_T_279, _T_280)
node _T_282 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_283 = and(_T_281, _T_282)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_284 = shr(io.in.a.bits.source, 2)
node _T_285 = eq(_T_284, UInt<2>(0h3))
node _T_286 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_287 = and(_T_285, _T_286)
node _T_288 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_289 = and(_T_287, _T_288)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0)
node _T_290 = shr(io.in.a.bits.source, 3)
node _T_291 = eq(_T_290, UInt<3>(0h4))
node _T_292 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_293 = and(_T_291, _T_292)
node _T_294 = leq(uncommonBits_19, UInt<3>(0h7))
node _T_295 = and(_T_293, _T_294)
node _T_296 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_297 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_298 = or(_T_265, _T_271)
node _T_299 = or(_T_298, _T_277)
node _T_300 = or(_T_299, _T_283)
node _T_301 = or(_T_300, _T_289)
node _T_302 = or(_T_301, _T_295)
node _T_303 = or(_T_302, _T_296)
node _T_304 = or(_T_303, _T_297)
node _T_305 = and(_T_264, _T_304)
node _T_306 = or(UInt<1>(0h0), _T_305)
node _T_307 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_308 = or(UInt<1>(0h0), _T_307)
node _T_309 = xor(io.in.a.bits.address, UInt<28>(0h8000040))
node _T_310 = cvt(_T_309)
node _T_311 = and(_T_310, asSInt(UInt<17>(0h101c0)))
node _T_312 = asSInt(_T_311)
node _T_313 = eq(_T_312, asSInt(UInt<1>(0h0)))
node _T_314 = xor(io.in.a.bits.address, UInt<32>(0h80000040))
node _T_315 = cvt(_T_314)
node _T_316 = and(_T_315, asSInt(UInt<29>(0h100001c0)))
node _T_317 = asSInt(_T_316)
node _T_318 = eq(_T_317, asSInt(UInt<1>(0h0)))
node _T_319 = or(_T_313, _T_318)
node _T_320 = and(_T_308, _T_319)
node _T_321 = or(UInt<1>(0h0), _T_320)
node _T_322 = and(_T_306, _T_321)
node _T_323 = asUInt(reset)
node _T_324 = eq(_T_323, UInt<1>(0h0))
when _T_324 :
node _T_325 = eq(_T_322, UInt<1>(0h0))
when _T_325 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_322, UInt<1>(0h1), "") : assert_10
node _T_326 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_327 = shr(io.in.a.bits.source, 2)
node _T_328 = eq(_T_327, UInt<1>(0h0))
node _T_329 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_330 = and(_T_328, _T_329)
node _T_331 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_332 = and(_T_330, _T_331)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_333 = shr(io.in.a.bits.source, 2)
node _T_334 = eq(_T_333, UInt<1>(0h1))
node _T_335 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_336 = and(_T_334, _T_335)
node _T_337 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_338 = and(_T_336, _T_337)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_339 = shr(io.in.a.bits.source, 2)
node _T_340 = eq(_T_339, UInt<2>(0h2))
node _T_341 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_342 = and(_T_340, _T_341)
node _T_343 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_344 = and(_T_342, _T_343)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_345 = shr(io.in.a.bits.source, 2)
node _T_346 = eq(_T_345, UInt<2>(0h3))
node _T_347 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_348 = and(_T_346, _T_347)
node _T_349 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_350 = and(_T_348, _T_349)
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 2, 0)
node _T_351 = shr(io.in.a.bits.source, 3)
node _T_352 = eq(_T_351, UInt<3>(0h4))
node _T_353 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_354 = and(_T_352, _T_353)
node _T_355 = leq(uncommonBits_24, UInt<3>(0h7))
node _T_356 = and(_T_354, _T_355)
node _T_357 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_358 = eq(io.in.a.bits.source, UInt<6>(0h2a))
wire _WIRE_2 : UInt<1>[8]
connect _WIRE_2[0], _T_326
connect _WIRE_2[1], _T_332
connect _WIRE_2[2], _T_338
connect _WIRE_2[3], _T_344
connect _WIRE_2[4], _T_350
connect _WIRE_2[5], _T_356
connect _WIRE_2[6], _T_357
connect _WIRE_2[7], _T_358
node _T_359 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_360 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_361 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_362 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_363 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_364 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_365 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_366 = mux(_WIRE_2[6], _T_359, UInt<1>(0h0))
node _T_367 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_368 = or(_T_360, _T_361)
node _T_369 = or(_T_368, _T_362)
node _T_370 = or(_T_369, _T_363)
node _T_371 = or(_T_370, _T_364)
node _T_372 = or(_T_371, _T_365)
node _T_373 = or(_T_372, _T_366)
node _T_374 = or(_T_373, _T_367)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_374
node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_376 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_377 = and(_T_375, _T_376)
node _T_378 = or(UInt<1>(0h0), _T_377)
node _T_379 = xor(io.in.a.bits.address, UInt<28>(0h8000040))
node _T_380 = cvt(_T_379)
node _T_381 = and(_T_380, asSInt(UInt<17>(0h101c0)))
node _T_382 = asSInt(_T_381)
node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0)))
node _T_384 = xor(io.in.a.bits.address, UInt<32>(0h80000040))
node _T_385 = cvt(_T_384)
node _T_386 = and(_T_385, asSInt(UInt<29>(0h100001c0)))
node _T_387 = asSInt(_T_386)
node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0)))
node _T_389 = or(_T_383, _T_388)
node _T_390 = and(_T_378, _T_389)
node _T_391 = or(UInt<1>(0h0), _T_390)
node _T_392 = and(_WIRE_3, _T_391)
node _T_393 = asUInt(reset)
node _T_394 = eq(_T_393, UInt<1>(0h0))
when _T_394 :
node _T_395 = eq(_T_392, UInt<1>(0h0))
when _T_395 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_392, UInt<1>(0h1), "") : assert_11
node _T_396 = asUInt(reset)
node _T_397 = eq(_T_396, UInt<1>(0h0))
when _T_397 :
node _T_398 = eq(source_ok, UInt<1>(0h0))
when _T_398 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_399 = geq(io.in.a.bits.size, UInt<3>(0h4))
node _T_400 = asUInt(reset)
node _T_401 = eq(_T_400, UInt<1>(0h0))
when _T_401 :
node _T_402 = eq(_T_399, UInt<1>(0h0))
when _T_402 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_399, UInt<1>(0h1), "") : assert_13
node _T_403 = asUInt(reset)
node _T_404 = eq(_T_403, UInt<1>(0h0))
when _T_404 :
node _T_405 = eq(is_aligned, UInt<1>(0h0))
when _T_405 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_406 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_407 = asUInt(reset)
node _T_408 = eq(_T_407, UInt<1>(0h0))
when _T_408 :
node _T_409 = eq(_T_406, UInt<1>(0h0))
when _T_409 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_406, UInt<1>(0h1), "") : assert_15
node _T_410 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_411 = asUInt(reset)
node _T_412 = eq(_T_411, UInt<1>(0h0))
when _T_412 :
node _T_413 = eq(_T_410, UInt<1>(0h0))
when _T_413 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_410, UInt<1>(0h1), "") : assert_16
node _T_414 = not(io.in.a.bits.mask)
node _T_415 = eq(_T_414, UInt<1>(0h0))
node _T_416 = asUInt(reset)
node _T_417 = eq(_T_416, UInt<1>(0h0))
when _T_417 :
node _T_418 = eq(_T_415, UInt<1>(0h0))
when _T_418 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_415, UInt<1>(0h1), "") : assert_17
node _T_419 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_420 = asUInt(reset)
node _T_421 = eq(_T_420, UInt<1>(0h0))
when _T_421 :
node _T_422 = eq(_T_419, UInt<1>(0h0))
when _T_422 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_419, UInt<1>(0h1), "") : assert_18
node _T_423 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_423 :
node _T_424 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_425 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_426 = and(_T_424, _T_425)
node _T_427 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_428 = shr(io.in.a.bits.source, 2)
node _T_429 = eq(_T_428, UInt<1>(0h0))
node _T_430 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_431 = and(_T_429, _T_430)
node _T_432 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_433 = and(_T_431, _T_432)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_434 = shr(io.in.a.bits.source, 2)
node _T_435 = eq(_T_434, UInt<1>(0h1))
node _T_436 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_437 = and(_T_435, _T_436)
node _T_438 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_439 = and(_T_437, _T_438)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_440 = shr(io.in.a.bits.source, 2)
node _T_441 = eq(_T_440, UInt<2>(0h2))
node _T_442 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_443 = and(_T_441, _T_442)
node _T_444 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_445 = and(_T_443, _T_444)
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_446 = shr(io.in.a.bits.source, 2)
node _T_447 = eq(_T_446, UInt<2>(0h3))
node _T_448 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_449 = and(_T_447, _T_448)
node _T_450 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_451 = and(_T_449, _T_450)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 2, 0)
node _T_452 = shr(io.in.a.bits.source, 3)
node _T_453 = eq(_T_452, UInt<3>(0h4))
node _T_454 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_455 = and(_T_453, _T_454)
node _T_456 = leq(uncommonBits_29, UInt<3>(0h7))
node _T_457 = and(_T_455, _T_456)
node _T_458 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_459 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_460 = or(_T_427, _T_433)
node _T_461 = or(_T_460, _T_439)
node _T_462 = or(_T_461, _T_445)
node _T_463 = or(_T_462, _T_451)
node _T_464 = or(_T_463, _T_457)
node _T_465 = or(_T_464, _T_458)
node _T_466 = or(_T_465, _T_459)
node _T_467 = and(_T_426, _T_466)
node _T_468 = or(UInt<1>(0h0), _T_467)
node _T_469 = asUInt(reset)
node _T_470 = eq(_T_469, UInt<1>(0h0))
when _T_470 :
node _T_471 = eq(_T_468, UInt<1>(0h0))
when _T_471 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_468, UInt<1>(0h1), "") : assert_19
node _T_472 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_473 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_474 = and(_T_472, _T_473)
node _T_475 = or(UInt<1>(0h0), _T_474)
node _T_476 = xor(io.in.a.bits.address, UInt<28>(0h8000040))
node _T_477 = cvt(_T_476)
node _T_478 = and(_T_477, asSInt(UInt<17>(0h101c0)))
node _T_479 = asSInt(_T_478)
node _T_480 = eq(_T_479, asSInt(UInt<1>(0h0)))
node _T_481 = xor(io.in.a.bits.address, UInt<32>(0h80000040))
node _T_482 = cvt(_T_481)
node _T_483 = and(_T_482, asSInt(UInt<29>(0h100001c0)))
node _T_484 = asSInt(_T_483)
node _T_485 = eq(_T_484, asSInt(UInt<1>(0h0)))
node _T_486 = or(_T_480, _T_485)
node _T_487 = and(_T_475, _T_486)
node _T_488 = or(UInt<1>(0h0), _T_487)
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_488, UInt<1>(0h1), "") : assert_20
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(source_ok, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_495 = asUInt(reset)
node _T_496 = eq(_T_495, UInt<1>(0h0))
when _T_496 :
node _T_497 = eq(is_aligned, UInt<1>(0h0))
when _T_497 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_498 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_499 = asUInt(reset)
node _T_500 = eq(_T_499, UInt<1>(0h0))
when _T_500 :
node _T_501 = eq(_T_498, UInt<1>(0h0))
when _T_501 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_498, UInt<1>(0h1), "") : assert_23
node _T_502 = eq(io.in.a.bits.mask, mask)
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_502, UInt<1>(0h1), "") : assert_24
node _T_506 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_507 = asUInt(reset)
node _T_508 = eq(_T_507, UInt<1>(0h0))
when _T_508 :
node _T_509 = eq(_T_506, UInt<1>(0h0))
when _T_509 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_506, UInt<1>(0h1), "") : assert_25
node _T_510 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_510 :
node _T_511 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_512 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_513 = and(_T_511, _T_512)
node _T_514 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_515 = shr(io.in.a.bits.source, 2)
node _T_516 = eq(_T_515, UInt<1>(0h0))
node _T_517 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_518 = and(_T_516, _T_517)
node _T_519 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_520 = and(_T_518, _T_519)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_521 = shr(io.in.a.bits.source, 2)
node _T_522 = eq(_T_521, UInt<1>(0h1))
node _T_523 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_524 = and(_T_522, _T_523)
node _T_525 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_526 = and(_T_524, _T_525)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_527 = shr(io.in.a.bits.source, 2)
node _T_528 = eq(_T_527, UInt<2>(0h2))
node _T_529 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_530 = and(_T_528, _T_529)
node _T_531 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_532 = and(_T_530, _T_531)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_533 = shr(io.in.a.bits.source, 2)
node _T_534 = eq(_T_533, UInt<2>(0h3))
node _T_535 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_536 = and(_T_534, _T_535)
node _T_537 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_538 = and(_T_536, _T_537)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0)
node _T_539 = shr(io.in.a.bits.source, 3)
node _T_540 = eq(_T_539, UInt<3>(0h4))
node _T_541 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_542 = and(_T_540, _T_541)
node _T_543 = leq(uncommonBits_34, UInt<3>(0h7))
node _T_544 = and(_T_542, _T_543)
node _T_545 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_546 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_547 = or(_T_514, _T_520)
node _T_548 = or(_T_547, _T_526)
node _T_549 = or(_T_548, _T_532)
node _T_550 = or(_T_549, _T_538)
node _T_551 = or(_T_550, _T_544)
node _T_552 = or(_T_551, _T_545)
node _T_553 = or(_T_552, _T_546)
node _T_554 = and(_T_513, _T_553)
node _T_555 = or(UInt<1>(0h0), _T_554)
node _T_556 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_557 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_558 = and(_T_556, _T_557)
node _T_559 = or(UInt<1>(0h0), _T_558)
node _T_560 = xor(io.in.a.bits.address, UInt<28>(0h8000040))
node _T_561 = cvt(_T_560)
node _T_562 = and(_T_561, asSInt(UInt<17>(0h101c0)))
node _T_563 = asSInt(_T_562)
node _T_564 = eq(_T_563, asSInt(UInt<1>(0h0)))
node _T_565 = xor(io.in.a.bits.address, UInt<32>(0h80000040))
node _T_566 = cvt(_T_565)
node _T_567 = and(_T_566, asSInt(UInt<29>(0h100001c0)))
node _T_568 = asSInt(_T_567)
node _T_569 = eq(_T_568, asSInt(UInt<1>(0h0)))
node _T_570 = or(_T_564, _T_569)
node _T_571 = and(_T_559, _T_570)
node _T_572 = or(UInt<1>(0h0), _T_571)
node _T_573 = and(_T_555, _T_572)
node _T_574 = asUInt(reset)
node _T_575 = eq(_T_574, UInt<1>(0h0))
when _T_575 :
node _T_576 = eq(_T_573, UInt<1>(0h0))
when _T_576 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_573, UInt<1>(0h1), "") : assert_26
node _T_577 = asUInt(reset)
node _T_578 = eq(_T_577, UInt<1>(0h0))
when _T_578 :
node _T_579 = eq(source_ok, UInt<1>(0h0))
when _T_579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_580 = asUInt(reset)
node _T_581 = eq(_T_580, UInt<1>(0h0))
when _T_581 :
node _T_582 = eq(is_aligned, UInt<1>(0h0))
when _T_582 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_583 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_584 = asUInt(reset)
node _T_585 = eq(_T_584, UInt<1>(0h0))
when _T_585 :
node _T_586 = eq(_T_583, UInt<1>(0h0))
when _T_586 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_583, UInt<1>(0h1), "") : assert_29
node _T_587 = eq(io.in.a.bits.mask, mask)
node _T_588 = asUInt(reset)
node _T_589 = eq(_T_588, UInt<1>(0h0))
when _T_589 :
node _T_590 = eq(_T_587, UInt<1>(0h0))
when _T_590 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_587, UInt<1>(0h1), "") : assert_30
node _T_591 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_591 :
node _T_592 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_593 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_594 = and(_T_592, _T_593)
node _T_595 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_596 = shr(io.in.a.bits.source, 2)
node _T_597 = eq(_T_596, UInt<1>(0h0))
node _T_598 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_599 = and(_T_597, _T_598)
node _T_600 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_601 = and(_T_599, _T_600)
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_602 = shr(io.in.a.bits.source, 2)
node _T_603 = eq(_T_602, UInt<1>(0h1))
node _T_604 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_605 = and(_T_603, _T_604)
node _T_606 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_607 = and(_T_605, _T_606)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_608 = shr(io.in.a.bits.source, 2)
node _T_609 = eq(_T_608, UInt<2>(0h2))
node _T_610 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_611 = and(_T_609, _T_610)
node _T_612 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_613 = and(_T_611, _T_612)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_614 = shr(io.in.a.bits.source, 2)
node _T_615 = eq(_T_614, UInt<2>(0h3))
node _T_616 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_617 = and(_T_615, _T_616)
node _T_618 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_619 = and(_T_617, _T_618)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 2, 0)
node _T_620 = shr(io.in.a.bits.source, 3)
node _T_621 = eq(_T_620, UInt<3>(0h4))
node _T_622 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_623 = and(_T_621, _T_622)
node _T_624 = leq(uncommonBits_39, UInt<3>(0h7))
node _T_625 = and(_T_623, _T_624)
node _T_626 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_627 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_628 = or(_T_595, _T_601)
node _T_629 = or(_T_628, _T_607)
node _T_630 = or(_T_629, _T_613)
node _T_631 = or(_T_630, _T_619)
node _T_632 = or(_T_631, _T_625)
node _T_633 = or(_T_632, _T_626)
node _T_634 = or(_T_633, _T_627)
node _T_635 = and(_T_594, _T_634)
node _T_636 = or(UInt<1>(0h0), _T_635)
node _T_637 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_638 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_639 = and(_T_637, _T_638)
node _T_640 = or(UInt<1>(0h0), _T_639)
node _T_641 = xor(io.in.a.bits.address, UInt<28>(0h8000040))
node _T_642 = cvt(_T_641)
node _T_643 = and(_T_642, asSInt(UInt<17>(0h101c0)))
node _T_644 = asSInt(_T_643)
node _T_645 = eq(_T_644, asSInt(UInt<1>(0h0)))
node _T_646 = xor(io.in.a.bits.address, UInt<32>(0h80000040))
node _T_647 = cvt(_T_646)
node _T_648 = and(_T_647, asSInt(UInt<29>(0h100001c0)))
node _T_649 = asSInt(_T_648)
node _T_650 = eq(_T_649, asSInt(UInt<1>(0h0)))
node _T_651 = or(_T_645, _T_650)
node _T_652 = and(_T_640, _T_651)
node _T_653 = or(UInt<1>(0h0), _T_652)
node _T_654 = and(_T_636, _T_653)
node _T_655 = asUInt(reset)
node _T_656 = eq(_T_655, UInt<1>(0h0))
when _T_656 :
node _T_657 = eq(_T_654, UInt<1>(0h0))
when _T_657 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_654, UInt<1>(0h1), "") : assert_31
node _T_658 = asUInt(reset)
node _T_659 = eq(_T_658, UInt<1>(0h0))
when _T_659 :
node _T_660 = eq(source_ok, UInt<1>(0h0))
when _T_660 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_661 = asUInt(reset)
node _T_662 = eq(_T_661, UInt<1>(0h0))
when _T_662 :
node _T_663 = eq(is_aligned, UInt<1>(0h0))
when _T_663 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_664 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_665 = asUInt(reset)
node _T_666 = eq(_T_665, UInt<1>(0h0))
when _T_666 :
node _T_667 = eq(_T_664, UInt<1>(0h0))
when _T_667 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_664, UInt<1>(0h1), "") : assert_34
node _T_668 = not(mask)
node _T_669 = and(io.in.a.bits.mask, _T_668)
node _T_670 = eq(_T_669, UInt<1>(0h0))
node _T_671 = asUInt(reset)
node _T_672 = eq(_T_671, UInt<1>(0h0))
when _T_672 :
node _T_673 = eq(_T_670, UInt<1>(0h0))
when _T_673 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_670, UInt<1>(0h1), "") : assert_35
node _T_674 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_674 :
node _T_675 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_676 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_677 = and(_T_675, _T_676)
node _T_678 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0)
node _T_679 = shr(io.in.a.bits.source, 2)
node _T_680 = eq(_T_679, UInt<1>(0h0))
node _T_681 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_682 = and(_T_680, _T_681)
node _T_683 = leq(uncommonBits_40, UInt<2>(0h3))
node _T_684 = and(_T_682, _T_683)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0)
node _T_685 = shr(io.in.a.bits.source, 2)
node _T_686 = eq(_T_685, UInt<1>(0h1))
node _T_687 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_688 = and(_T_686, _T_687)
node _T_689 = leq(uncommonBits_41, UInt<2>(0h3))
node _T_690 = and(_T_688, _T_689)
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_691 = shr(io.in.a.bits.source, 2)
node _T_692 = eq(_T_691, UInt<2>(0h2))
node _T_693 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_694 = and(_T_692, _T_693)
node _T_695 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_696 = and(_T_694, _T_695)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_697 = shr(io.in.a.bits.source, 2)
node _T_698 = eq(_T_697, UInt<2>(0h3))
node _T_699 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_700 = and(_T_698, _T_699)
node _T_701 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_702 = and(_T_700, _T_701)
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 2, 0)
node _T_703 = shr(io.in.a.bits.source, 3)
node _T_704 = eq(_T_703, UInt<3>(0h4))
node _T_705 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_706 = and(_T_704, _T_705)
node _T_707 = leq(uncommonBits_44, UInt<3>(0h7))
node _T_708 = and(_T_706, _T_707)
node _T_709 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_710 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_711 = or(_T_678, _T_684)
node _T_712 = or(_T_711, _T_690)
node _T_713 = or(_T_712, _T_696)
node _T_714 = or(_T_713, _T_702)
node _T_715 = or(_T_714, _T_708)
node _T_716 = or(_T_715, _T_709)
node _T_717 = or(_T_716, _T_710)
node _T_718 = and(_T_677, _T_717)
node _T_719 = or(UInt<1>(0h0), _T_718)
node _T_720 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_721 = leq(io.in.a.bits.size, UInt<3>(0h4))
node _T_722 = and(_T_720, _T_721)
node _T_723 = or(UInt<1>(0h0), _T_722)
node _T_724 = xor(io.in.a.bits.address, UInt<28>(0h8000040))
node _T_725 = cvt(_T_724)
node _T_726 = and(_T_725, asSInt(UInt<17>(0h101c0)))
node _T_727 = asSInt(_T_726)
node _T_728 = eq(_T_727, asSInt(UInt<1>(0h0)))
node _T_729 = xor(io.in.a.bits.address, UInt<32>(0h80000040))
node _T_730 = cvt(_T_729)
node _T_731 = and(_T_730, asSInt(UInt<29>(0h100001c0)))
node _T_732 = asSInt(_T_731)
node _T_733 = eq(_T_732, asSInt(UInt<1>(0h0)))
node _T_734 = or(_T_728, _T_733)
node _T_735 = and(_T_723, _T_734)
node _T_736 = or(UInt<1>(0h0), _T_735)
node _T_737 = and(_T_719, _T_736)
node _T_738 = asUInt(reset)
node _T_739 = eq(_T_738, UInt<1>(0h0))
when _T_739 :
node _T_740 = eq(_T_737, UInt<1>(0h0))
when _T_740 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_737, UInt<1>(0h1), "") : assert_36
node _T_741 = asUInt(reset)
node _T_742 = eq(_T_741, UInt<1>(0h0))
when _T_742 :
node _T_743 = eq(source_ok, UInt<1>(0h0))
when _T_743 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_744 = asUInt(reset)
node _T_745 = eq(_T_744, UInt<1>(0h0))
when _T_745 :
node _T_746 = eq(is_aligned, UInt<1>(0h0))
when _T_746 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_747 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_748 = asUInt(reset)
node _T_749 = eq(_T_748, UInt<1>(0h0))
when _T_749 :
node _T_750 = eq(_T_747, UInt<1>(0h0))
when _T_750 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_747, UInt<1>(0h1), "") : assert_39
node _T_751 = eq(io.in.a.bits.mask, mask)
node _T_752 = asUInt(reset)
node _T_753 = eq(_T_752, UInt<1>(0h0))
when _T_753 :
node _T_754 = eq(_T_751, UInt<1>(0h0))
when _T_754 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_751, UInt<1>(0h1), "") : assert_40
node _T_755 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_755 :
node _T_756 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_757 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_758 = and(_T_756, _T_757)
node _T_759 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0)
node _T_760 = shr(io.in.a.bits.source, 2)
node _T_761 = eq(_T_760, UInt<1>(0h0))
node _T_762 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_763 = and(_T_761, _T_762)
node _T_764 = leq(uncommonBits_45, UInt<2>(0h3))
node _T_765 = and(_T_763, _T_764)
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0)
node _T_766 = shr(io.in.a.bits.source, 2)
node _T_767 = eq(_T_766, UInt<1>(0h1))
node _T_768 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_769 = and(_T_767, _T_768)
node _T_770 = leq(uncommonBits_46, UInt<2>(0h3))
node _T_771 = and(_T_769, _T_770)
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0)
node _T_772 = shr(io.in.a.bits.source, 2)
node _T_773 = eq(_T_772, UInt<2>(0h2))
node _T_774 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_775 = and(_T_773, _T_774)
node _T_776 = leq(uncommonBits_47, UInt<2>(0h3))
node _T_777 = and(_T_775, _T_776)
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0)
node _T_778 = shr(io.in.a.bits.source, 2)
node _T_779 = eq(_T_778, UInt<2>(0h3))
node _T_780 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_781 = and(_T_779, _T_780)
node _T_782 = leq(uncommonBits_48, UInt<2>(0h3))
node _T_783 = and(_T_781, _T_782)
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 2, 0)
node _T_784 = shr(io.in.a.bits.source, 3)
node _T_785 = eq(_T_784, UInt<3>(0h4))
node _T_786 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_787 = and(_T_785, _T_786)
node _T_788 = leq(uncommonBits_49, UInt<3>(0h7))
node _T_789 = and(_T_787, _T_788)
node _T_790 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_791 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_792 = or(_T_759, _T_765)
node _T_793 = or(_T_792, _T_771)
node _T_794 = or(_T_793, _T_777)
node _T_795 = or(_T_794, _T_783)
node _T_796 = or(_T_795, _T_789)
node _T_797 = or(_T_796, _T_790)
node _T_798 = or(_T_797, _T_791)
node _T_799 = and(_T_758, _T_798)
node _T_800 = or(UInt<1>(0h0), _T_799)
node _T_801 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_802 = leq(io.in.a.bits.size, UInt<3>(0h4))
node _T_803 = and(_T_801, _T_802)
node _T_804 = or(UInt<1>(0h0), _T_803)
node _T_805 = xor(io.in.a.bits.address, UInt<28>(0h8000040))
node _T_806 = cvt(_T_805)
node _T_807 = and(_T_806, asSInt(UInt<17>(0h101c0)))
node _T_808 = asSInt(_T_807)
node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0)))
node _T_810 = xor(io.in.a.bits.address, UInt<32>(0h80000040))
node _T_811 = cvt(_T_810)
node _T_812 = and(_T_811, asSInt(UInt<29>(0h100001c0)))
node _T_813 = asSInt(_T_812)
node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0)))
node _T_815 = or(_T_809, _T_814)
node _T_816 = and(_T_804, _T_815)
node _T_817 = or(UInt<1>(0h0), _T_816)
node _T_818 = and(_T_800, _T_817)
node _T_819 = asUInt(reset)
node _T_820 = eq(_T_819, UInt<1>(0h0))
when _T_820 :
node _T_821 = eq(_T_818, UInt<1>(0h0))
when _T_821 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_818, UInt<1>(0h1), "") : assert_41
node _T_822 = asUInt(reset)
node _T_823 = eq(_T_822, UInt<1>(0h0))
when _T_823 :
node _T_824 = eq(source_ok, UInt<1>(0h0))
when _T_824 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_825 = asUInt(reset)
node _T_826 = eq(_T_825, UInt<1>(0h0))
when _T_826 :
node _T_827 = eq(is_aligned, UInt<1>(0h0))
when _T_827 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_828 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_829 = asUInt(reset)
node _T_830 = eq(_T_829, UInt<1>(0h0))
when _T_830 :
node _T_831 = eq(_T_828, UInt<1>(0h0))
when _T_831 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_828, UInt<1>(0h1), "") : assert_44
node _T_832 = eq(io.in.a.bits.mask, mask)
node _T_833 = asUInt(reset)
node _T_834 = eq(_T_833, UInt<1>(0h0))
when _T_834 :
node _T_835 = eq(_T_832, UInt<1>(0h0))
when _T_835 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_832, UInt<1>(0h1), "") : assert_45
node _T_836 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_836 :
node _T_837 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_838 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_839 = and(_T_837, _T_838)
node _T_840 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_841 = shr(io.in.a.bits.source, 2)
node _T_842 = eq(_T_841, UInt<1>(0h0))
node _T_843 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_844 = and(_T_842, _T_843)
node _T_845 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_846 = and(_T_844, _T_845)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_847 = shr(io.in.a.bits.source, 2)
node _T_848 = eq(_T_847, UInt<1>(0h1))
node _T_849 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_850 = and(_T_848, _T_849)
node _T_851 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_852 = and(_T_850, _T_851)
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0)
node _T_853 = shr(io.in.a.bits.source, 2)
node _T_854 = eq(_T_853, UInt<2>(0h2))
node _T_855 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_856 = and(_T_854, _T_855)
node _T_857 = leq(uncommonBits_52, UInt<2>(0h3))
node _T_858 = and(_T_856, _T_857)
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0)
node _T_859 = shr(io.in.a.bits.source, 2)
node _T_860 = eq(_T_859, UInt<2>(0h3))
node _T_861 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_862 = and(_T_860, _T_861)
node _T_863 = leq(uncommonBits_53, UInt<2>(0h3))
node _T_864 = and(_T_862, _T_863)
node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_54 = bits(_uncommonBits_T_54, 2, 0)
node _T_865 = shr(io.in.a.bits.source, 3)
node _T_866 = eq(_T_865, UInt<3>(0h4))
node _T_867 = leq(UInt<1>(0h0), uncommonBits_54)
node _T_868 = and(_T_866, _T_867)
node _T_869 = leq(uncommonBits_54, UInt<3>(0h7))
node _T_870 = and(_T_868, _T_869)
node _T_871 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_872 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_873 = or(_T_840, _T_846)
node _T_874 = or(_T_873, _T_852)
node _T_875 = or(_T_874, _T_858)
node _T_876 = or(_T_875, _T_864)
node _T_877 = or(_T_876, _T_870)
node _T_878 = or(_T_877, _T_871)
node _T_879 = or(_T_878, _T_872)
node _T_880 = and(_T_839, _T_879)
node _T_881 = or(UInt<1>(0h0), _T_880)
node _T_882 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_883 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_884 = and(_T_882, _T_883)
node _T_885 = or(UInt<1>(0h0), _T_884)
node _T_886 = xor(io.in.a.bits.address, UInt<28>(0h8000040))
node _T_887 = cvt(_T_886)
node _T_888 = and(_T_887, asSInt(UInt<17>(0h101c0)))
node _T_889 = asSInt(_T_888)
node _T_890 = eq(_T_889, asSInt(UInt<1>(0h0)))
node _T_891 = xor(io.in.a.bits.address, UInt<32>(0h80000040))
node _T_892 = cvt(_T_891)
node _T_893 = and(_T_892, asSInt(UInt<29>(0h100001c0)))
node _T_894 = asSInt(_T_893)
node _T_895 = eq(_T_894, asSInt(UInt<1>(0h0)))
node _T_896 = or(_T_890, _T_895)
node _T_897 = and(_T_885, _T_896)
node _T_898 = or(UInt<1>(0h0), _T_897)
node _T_899 = and(_T_881, _T_898)
node _T_900 = asUInt(reset)
node _T_901 = eq(_T_900, UInt<1>(0h0))
when _T_901 :
node _T_902 = eq(_T_899, UInt<1>(0h0))
when _T_902 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_899, UInt<1>(0h1), "") : assert_46
node _T_903 = asUInt(reset)
node _T_904 = eq(_T_903, UInt<1>(0h0))
when _T_904 :
node _T_905 = eq(source_ok, UInt<1>(0h0))
when _T_905 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_906 = asUInt(reset)
node _T_907 = eq(_T_906, UInt<1>(0h0))
when _T_907 :
node _T_908 = eq(is_aligned, UInt<1>(0h0))
when _T_908 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_909 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_910 = asUInt(reset)
node _T_911 = eq(_T_910, UInt<1>(0h0))
when _T_911 :
node _T_912 = eq(_T_909, UInt<1>(0h0))
when _T_912 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_909, UInt<1>(0h1), "") : assert_49
node _T_913 = eq(io.in.a.bits.mask, mask)
node _T_914 = asUInt(reset)
node _T_915 = eq(_T_914, UInt<1>(0h0))
when _T_915 :
node _T_916 = eq(_T_913, UInt<1>(0h0))
when _T_916 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_913, UInt<1>(0h1), "") : assert_50
node _T_917 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_918 = asUInt(reset)
node _T_919 = eq(_T_918, UInt<1>(0h0))
when _T_919 :
node _T_920 = eq(_T_917, UInt<1>(0h0))
when _T_920 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_917, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_921 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_922 = asUInt(reset)
node _T_923 = eq(_T_922, UInt<1>(0h0))
when _T_923 :
node _T_924 = eq(_T_921, UInt<1>(0h0))
when _T_924 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_921, UInt<1>(0h1), "") : assert_52
node _source_ok_T_39 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_40 = shr(io.in.d.bits.source, 2)
node _source_ok_T_41 = eq(_source_ok_T_40, UInt<1>(0h0))
node _source_ok_T_42 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_43 = and(_source_ok_T_41, _source_ok_T_42)
node _source_ok_T_44 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_46 = shr(io.in.d.bits.source, 2)
node _source_ok_T_47 = eq(_source_ok_T_46, UInt<1>(0h1))
node _source_ok_T_48 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_49 = and(_source_ok_T_47, _source_ok_T_48)
node _source_ok_T_50 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_51 = and(_source_ok_T_49, _source_ok_T_50)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_52 = shr(io.in.d.bits.source, 2)
node _source_ok_T_53 = eq(_source_ok_T_52, UInt<2>(0h2))
node _source_ok_T_54 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_55 = and(_source_ok_T_53, _source_ok_T_54)
node _source_ok_T_56 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56)
node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0)
node _source_ok_T_58 = shr(io.in.d.bits.source, 2)
node _source_ok_T_59 = eq(_source_ok_T_58, UInt<2>(0h3))
node _source_ok_T_60 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_61 = and(_source_ok_T_59, _source_ok_T_60)
node _source_ok_T_62 = leq(source_ok_uncommonBits_8, UInt<2>(0h3))
node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62)
node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 2, 0)
node _source_ok_T_64 = shr(io.in.d.bits.source, 3)
node _source_ok_T_65 = eq(_source_ok_T_64, UInt<3>(0h4))
node _source_ok_T_66 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_67 = and(_source_ok_T_65, _source_ok_T_66)
node _source_ok_T_68 = leq(source_ok_uncommonBits_9, UInt<3>(0h7))
node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68)
node _source_ok_T_70 = eq(io.in.d.bits.source, UInt<6>(0h28))
node _source_ok_T_71 = eq(io.in.d.bits.source, UInt<6>(0h2a))
wire _source_ok_WIRE_1 : UInt<1>[8]
connect _source_ok_WIRE_1[0], _source_ok_T_39
connect _source_ok_WIRE_1[1], _source_ok_T_45
connect _source_ok_WIRE_1[2], _source_ok_T_51
connect _source_ok_WIRE_1[3], _source_ok_T_57
connect _source_ok_WIRE_1[4], _source_ok_T_63
connect _source_ok_WIRE_1[5], _source_ok_T_69
connect _source_ok_WIRE_1[6], _source_ok_T_70
connect _source_ok_WIRE_1[7], _source_ok_T_71
node _source_ok_T_72 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE_1[2])
node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE_1[3])
node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE_1[4])
node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE_1[5])
node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE_1[6])
node source_ok_1 = or(_source_ok_T_77, _source_ok_WIRE_1[7])
node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0hc))
node _T_925 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_925 :
node _T_926 = asUInt(reset)
node _T_927 = eq(_T_926, UInt<1>(0h0))
when _T_927 :
node _T_928 = eq(source_ok_1, UInt<1>(0h0))
when _T_928 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_929 = geq(io.in.d.bits.size, UInt<3>(0h4))
node _T_930 = asUInt(reset)
node _T_931 = eq(_T_930, UInt<1>(0h0))
when _T_931 :
node _T_932 = eq(_T_929, UInt<1>(0h0))
when _T_932 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_929, UInt<1>(0h1), "") : assert_54
node _T_933 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_934 = asUInt(reset)
node _T_935 = eq(_T_934, UInt<1>(0h0))
when _T_935 :
node _T_936 = eq(_T_933, UInt<1>(0h0))
when _T_936 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_933, UInt<1>(0h1), "") : assert_55
node _T_937 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_938 = asUInt(reset)
node _T_939 = eq(_T_938, UInt<1>(0h0))
when _T_939 :
node _T_940 = eq(_T_937, UInt<1>(0h0))
when _T_940 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_937, UInt<1>(0h1), "") : assert_56
node _T_941 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_942 = asUInt(reset)
node _T_943 = eq(_T_942, UInt<1>(0h0))
when _T_943 :
node _T_944 = eq(_T_941, UInt<1>(0h0))
when _T_944 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_941, UInt<1>(0h1), "") : assert_57
node _T_945 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_945 :
node _T_946 = asUInt(reset)
node _T_947 = eq(_T_946, UInt<1>(0h0))
when _T_947 :
node _T_948 = eq(source_ok_1, UInt<1>(0h0))
when _T_948 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_949 = asUInt(reset)
node _T_950 = eq(_T_949, UInt<1>(0h0))
when _T_950 :
node _T_951 = eq(sink_ok, UInt<1>(0h0))
when _T_951 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_952 = geq(io.in.d.bits.size, UInt<3>(0h4))
node _T_953 = asUInt(reset)
node _T_954 = eq(_T_953, UInt<1>(0h0))
when _T_954 :
node _T_955 = eq(_T_952, UInt<1>(0h0))
when _T_955 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_952, UInt<1>(0h1), "") : assert_60
node _T_956 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_957 = asUInt(reset)
node _T_958 = eq(_T_957, UInt<1>(0h0))
when _T_958 :
node _T_959 = eq(_T_956, UInt<1>(0h0))
when _T_959 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_956, UInt<1>(0h1), "") : assert_61
node _T_960 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_961 = asUInt(reset)
node _T_962 = eq(_T_961, UInt<1>(0h0))
when _T_962 :
node _T_963 = eq(_T_960, UInt<1>(0h0))
when _T_963 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_960, UInt<1>(0h1), "") : assert_62
node _T_964 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_965 = asUInt(reset)
node _T_966 = eq(_T_965, UInt<1>(0h0))
when _T_966 :
node _T_967 = eq(_T_964, UInt<1>(0h0))
when _T_967 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_964, UInt<1>(0h1), "") : assert_63
node _T_968 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_969 = or(UInt<1>(0h1), _T_968)
node _T_970 = asUInt(reset)
node _T_971 = eq(_T_970, UInt<1>(0h0))
when _T_971 :
node _T_972 = eq(_T_969, UInt<1>(0h0))
when _T_972 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_969, UInt<1>(0h1), "") : assert_64
node _T_973 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_973 :
node _T_974 = asUInt(reset)
node _T_975 = eq(_T_974, UInt<1>(0h0))
when _T_975 :
node _T_976 = eq(source_ok_1, UInt<1>(0h0))
when _T_976 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_977 = asUInt(reset)
node _T_978 = eq(_T_977, UInt<1>(0h0))
when _T_978 :
node _T_979 = eq(sink_ok, UInt<1>(0h0))
when _T_979 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_980 = geq(io.in.d.bits.size, UInt<3>(0h4))
node _T_981 = asUInt(reset)
node _T_982 = eq(_T_981, UInt<1>(0h0))
when _T_982 :
node _T_983 = eq(_T_980, UInt<1>(0h0))
when _T_983 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_980, UInt<1>(0h1), "") : assert_67
node _T_984 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_985 = asUInt(reset)
node _T_986 = eq(_T_985, UInt<1>(0h0))
when _T_986 :
node _T_987 = eq(_T_984, UInt<1>(0h0))
when _T_987 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_984, UInt<1>(0h1), "") : assert_68
node _T_988 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_989 = asUInt(reset)
node _T_990 = eq(_T_989, UInt<1>(0h0))
when _T_990 :
node _T_991 = eq(_T_988, UInt<1>(0h0))
when _T_991 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_988, UInt<1>(0h1), "") : assert_69
node _T_992 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_993 = or(_T_992, io.in.d.bits.corrupt)
node _T_994 = asUInt(reset)
node _T_995 = eq(_T_994, UInt<1>(0h0))
when _T_995 :
node _T_996 = eq(_T_993, UInt<1>(0h0))
when _T_996 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_993, UInt<1>(0h1), "") : assert_70
node _T_997 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_998 = or(UInt<1>(0h1), _T_997)
node _T_999 = asUInt(reset)
node _T_1000 = eq(_T_999, UInt<1>(0h0))
when _T_1000 :
node _T_1001 = eq(_T_998, UInt<1>(0h0))
when _T_1001 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_998, UInt<1>(0h1), "") : assert_71
node _T_1002 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1002 :
node _T_1003 = asUInt(reset)
node _T_1004 = eq(_T_1003, UInt<1>(0h0))
when _T_1004 :
node _T_1005 = eq(source_ok_1, UInt<1>(0h0))
when _T_1005 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1006 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1007 = asUInt(reset)
node _T_1008 = eq(_T_1007, UInt<1>(0h0))
when _T_1008 :
node _T_1009 = eq(_T_1006, UInt<1>(0h0))
when _T_1009 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1006, UInt<1>(0h1), "") : assert_73
node _T_1010 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1011 = asUInt(reset)
node _T_1012 = eq(_T_1011, UInt<1>(0h0))
when _T_1012 :
node _T_1013 = eq(_T_1010, UInt<1>(0h0))
when _T_1013 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1010, UInt<1>(0h1), "") : assert_74
node _T_1014 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1015 = or(UInt<1>(0h1), _T_1014)
node _T_1016 = asUInt(reset)
node _T_1017 = eq(_T_1016, UInt<1>(0h0))
when _T_1017 :
node _T_1018 = eq(_T_1015, UInt<1>(0h0))
when _T_1018 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1015, UInt<1>(0h1), "") : assert_75
node _T_1019 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1019 :
node _T_1020 = asUInt(reset)
node _T_1021 = eq(_T_1020, UInt<1>(0h0))
when _T_1021 :
node _T_1022 = eq(source_ok_1, UInt<1>(0h0))
when _T_1022 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1023 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1024 = asUInt(reset)
node _T_1025 = eq(_T_1024, UInt<1>(0h0))
when _T_1025 :
node _T_1026 = eq(_T_1023, UInt<1>(0h0))
when _T_1026 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1023, UInt<1>(0h1), "") : assert_77
node _T_1027 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1028 = or(_T_1027, io.in.d.bits.corrupt)
node _T_1029 = asUInt(reset)
node _T_1030 = eq(_T_1029, UInt<1>(0h0))
when _T_1030 :
node _T_1031 = eq(_T_1028, UInt<1>(0h0))
when _T_1031 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1028, UInt<1>(0h1), "") : assert_78
node _T_1032 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1033 = or(UInt<1>(0h1), _T_1032)
node _T_1034 = asUInt(reset)
node _T_1035 = eq(_T_1034, UInt<1>(0h0))
when _T_1035 :
node _T_1036 = eq(_T_1033, UInt<1>(0h0))
when _T_1036 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1033, UInt<1>(0h1), "") : assert_79
node _T_1037 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1037 :
node _T_1038 = asUInt(reset)
node _T_1039 = eq(_T_1038, UInt<1>(0h0))
when _T_1039 :
node _T_1040 = eq(source_ok_1, UInt<1>(0h0))
when _T_1040 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1041 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1042 = asUInt(reset)
node _T_1043 = eq(_T_1042, UInt<1>(0h0))
when _T_1043 :
node _T_1044 = eq(_T_1041, UInt<1>(0h0))
when _T_1044 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1041, UInt<1>(0h1), "") : assert_81
node _T_1045 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1046 = asUInt(reset)
node _T_1047 = eq(_T_1046, UInt<1>(0h0))
when _T_1047 :
node _T_1048 = eq(_T_1045, UInt<1>(0h0))
when _T_1048 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1045, UInt<1>(0h1), "") : assert_82
node _T_1049 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1050 = or(UInt<1>(0h1), _T_1049)
node _T_1051 = asUInt(reset)
node _T_1052 = eq(_T_1051, UInt<1>(0h0))
when _T_1052 :
node _T_1053 = eq(_T_1050, UInt<1>(0h0))
when _T_1053 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1050, UInt<1>(0h1), "") : assert_83
when io.in.b.valid :
node _T_1054 = leq(io.in.b.bits.opcode, UInt<3>(0h6))
node _T_1055 = asUInt(reset)
node _T_1056 = eq(_T_1055, UInt<1>(0h0))
when _T_1056 :
node _T_1057 = eq(_T_1054, UInt<1>(0h0))
when _T_1057 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1054, UInt<1>(0h1), "") : assert_84
node _T_1058 = eq(io.in.b.bits.source, UInt<5>(0h10))
node _T_1059 = eq(_T_1058, UInt<1>(0h0))
node _T_1060 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1061 = cvt(_T_1060)
node _T_1062 = and(_T_1061, asSInt(UInt<1>(0h0)))
node _T_1063 = asSInt(_T_1062)
node _T_1064 = eq(_T_1063, asSInt(UInt<1>(0h0)))
node _T_1065 = or(_T_1059, _T_1064)
node _uncommonBits_T_55 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0)
node _T_1066 = shr(io.in.b.bits.source, 2)
node _T_1067 = eq(_T_1066, UInt<1>(0h0))
node _T_1068 = leq(UInt<1>(0h0), uncommonBits_55)
node _T_1069 = and(_T_1067, _T_1068)
node _T_1070 = leq(uncommonBits_55, UInt<2>(0h3))
node _T_1071 = and(_T_1069, _T_1070)
node _T_1072 = eq(_T_1071, UInt<1>(0h0))
node _T_1073 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1074 = cvt(_T_1073)
node _T_1075 = and(_T_1074, asSInt(UInt<1>(0h0)))
node _T_1076 = asSInt(_T_1075)
node _T_1077 = eq(_T_1076, asSInt(UInt<1>(0h0)))
node _T_1078 = or(_T_1072, _T_1077)
node _uncommonBits_T_56 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0)
node _T_1079 = shr(io.in.b.bits.source, 2)
node _T_1080 = eq(_T_1079, UInt<1>(0h1))
node _T_1081 = leq(UInt<1>(0h0), uncommonBits_56)
node _T_1082 = and(_T_1080, _T_1081)
node _T_1083 = leq(uncommonBits_56, UInt<2>(0h3))
node _T_1084 = and(_T_1082, _T_1083)
node _T_1085 = eq(_T_1084, UInt<1>(0h0))
node _T_1086 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1087 = cvt(_T_1086)
node _T_1088 = and(_T_1087, asSInt(UInt<1>(0h0)))
node _T_1089 = asSInt(_T_1088)
node _T_1090 = eq(_T_1089, asSInt(UInt<1>(0h0)))
node _T_1091 = or(_T_1085, _T_1090)
node _uncommonBits_T_57 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0)
node _T_1092 = shr(io.in.b.bits.source, 2)
node _T_1093 = eq(_T_1092, UInt<2>(0h2))
node _T_1094 = leq(UInt<1>(0h0), uncommonBits_57)
node _T_1095 = and(_T_1093, _T_1094)
node _T_1096 = leq(uncommonBits_57, UInt<2>(0h3))
node _T_1097 = and(_T_1095, _T_1096)
node _T_1098 = eq(_T_1097, UInt<1>(0h0))
node _T_1099 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1100 = cvt(_T_1099)
node _T_1101 = and(_T_1100, asSInt(UInt<1>(0h0)))
node _T_1102 = asSInt(_T_1101)
node _T_1103 = eq(_T_1102, asSInt(UInt<1>(0h0)))
node _T_1104 = or(_T_1098, _T_1103)
node _uncommonBits_T_58 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_58 = bits(_uncommonBits_T_58, 1, 0)
node _T_1105 = shr(io.in.b.bits.source, 2)
node _T_1106 = eq(_T_1105, UInt<2>(0h3))
node _T_1107 = leq(UInt<1>(0h0), uncommonBits_58)
node _T_1108 = and(_T_1106, _T_1107)
node _T_1109 = leq(uncommonBits_58, UInt<2>(0h3))
node _T_1110 = and(_T_1108, _T_1109)
node _T_1111 = eq(_T_1110, UInt<1>(0h0))
node _T_1112 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1113 = cvt(_T_1112)
node _T_1114 = and(_T_1113, asSInt(UInt<1>(0h0)))
node _T_1115 = asSInt(_T_1114)
node _T_1116 = eq(_T_1115, asSInt(UInt<1>(0h0)))
node _T_1117 = or(_T_1111, _T_1116)
node _uncommonBits_T_59 = or(io.in.b.bits.source, UInt<3>(0h0))
node uncommonBits_59 = bits(_uncommonBits_T_59, 2, 0)
node _T_1118 = shr(io.in.b.bits.source, 3)
node _T_1119 = eq(_T_1118, UInt<3>(0h4))
node _T_1120 = leq(UInt<1>(0h0), uncommonBits_59)
node _T_1121 = and(_T_1119, _T_1120)
node _T_1122 = leq(uncommonBits_59, UInt<3>(0h7))
node _T_1123 = and(_T_1121, _T_1122)
node _T_1124 = eq(_T_1123, UInt<1>(0h0))
node _T_1125 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1126 = cvt(_T_1125)
node _T_1127 = and(_T_1126, asSInt(UInt<1>(0h0)))
node _T_1128 = asSInt(_T_1127)
node _T_1129 = eq(_T_1128, asSInt(UInt<1>(0h0)))
node _T_1130 = or(_T_1124, _T_1129)
node _T_1131 = eq(io.in.b.bits.source, UInt<6>(0h28))
node _T_1132 = eq(_T_1131, UInt<1>(0h0))
node _T_1133 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1134 = cvt(_T_1133)
node _T_1135 = and(_T_1134, asSInt(UInt<1>(0h0)))
node _T_1136 = asSInt(_T_1135)
node _T_1137 = eq(_T_1136, asSInt(UInt<1>(0h0)))
node _T_1138 = or(_T_1132, _T_1137)
node _T_1139 = eq(io.in.b.bits.source, UInt<6>(0h2a))
node _T_1140 = eq(_T_1139, UInt<1>(0h0))
node _T_1141 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1142 = cvt(_T_1141)
node _T_1143 = and(_T_1142, asSInt(UInt<1>(0h0)))
node _T_1144 = asSInt(_T_1143)
node _T_1145 = eq(_T_1144, asSInt(UInt<1>(0h0)))
node _T_1146 = or(_T_1140, _T_1145)
node _T_1147 = and(_T_1065, _T_1078)
node _T_1148 = and(_T_1147, _T_1091)
node _T_1149 = and(_T_1148, _T_1104)
node _T_1150 = and(_T_1149, _T_1117)
node _T_1151 = and(_T_1150, _T_1130)
node _T_1152 = and(_T_1151, _T_1138)
node _T_1153 = and(_T_1152, _T_1146)
node _T_1154 = asUInt(reset)
node _T_1155 = eq(_T_1154, UInt<1>(0h0))
when _T_1155 :
node _T_1156 = eq(_T_1153, UInt<1>(0h0))
when _T_1156 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1153, UInt<1>(0h1), "") : assert_85
node _address_ok_T = xor(io.in.b.bits.address, UInt<28>(0h8000040))
node _address_ok_T_1 = cvt(_address_ok_T)
node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<17>(0h101c0)))
node _address_ok_T_3 = asSInt(_address_ok_T_2)
node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0)))
node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<32>(0h80000040))
node _address_ok_T_6 = cvt(_address_ok_T_5)
node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<29>(0h100001c0)))
node _address_ok_T_8 = asSInt(_address_ok_T_7)
node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE : UInt<1>[2]
connect _address_ok_WIRE[0], _address_ok_T_4
connect _address_ok_WIRE[1], _address_ok_T_9
node address_ok = or(_address_ok_WIRE[0], _address_ok_WIRE[1])
node _is_aligned_mask_T_2 = dshl(UInt<6>(0h3f), io.in.b.bits.size)
node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 5, 0)
node is_aligned_mask_1 = not(_is_aligned_mask_T_3)
node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1)
node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0))
node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<4>(0h0))
node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0)
node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1)
node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 3, 0)
node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1))
node mask_sub_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<3>(0h4))
node mask_sub_sub_sub_size_1 = bits(mask_sizeOH_1, 3, 3)
node mask_sub_sub_sub_bit_1 = bits(io.in.b.bits.address, 3, 3)
node mask_sub_sub_sub_nbit_1 = eq(mask_sub_sub_sub_bit_1, UInt<1>(0h0))
node mask_sub_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit_1)
node _mask_sub_sub_sub_acc_T_2 = and(mask_sub_sub_sub_size_1, mask_sub_sub_sub_0_2_1)
node mask_sub_sub_sub_0_1_1 = or(mask_sub_sub_sub_sub_0_1_1, _mask_sub_sub_sub_acc_T_2)
node mask_sub_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_sub_bit_1)
node _mask_sub_sub_sub_acc_T_3 = and(mask_sub_sub_sub_size_1, mask_sub_sub_sub_1_2_1)
node mask_sub_sub_sub_1_1_1 = or(mask_sub_sub_sub_sub_0_1_1, _mask_sub_sub_sub_acc_T_3)
node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2)
node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2)
node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0))
node mask_sub_sub_0_2_1 = and(mask_sub_sub_sub_0_2_1, mask_sub_sub_nbit_1)
node _mask_sub_sub_acc_T_4 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1)
node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_4)
node mask_sub_sub_1_2_1 = and(mask_sub_sub_sub_0_2_1, mask_sub_sub_bit_1)
node _mask_sub_sub_acc_T_5 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1)
node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_5)
node mask_sub_sub_2_2_1 = and(mask_sub_sub_sub_1_2_1, mask_sub_sub_nbit_1)
node _mask_sub_sub_acc_T_6 = and(mask_sub_sub_size_1, mask_sub_sub_2_2_1)
node mask_sub_sub_2_1_1 = or(mask_sub_sub_sub_1_1_1, _mask_sub_sub_acc_T_6)
node mask_sub_sub_3_2_1 = and(mask_sub_sub_sub_1_2_1, mask_sub_sub_bit_1)
node _mask_sub_sub_acc_T_7 = and(mask_sub_sub_size_1, mask_sub_sub_3_2_1)
node mask_sub_sub_3_1_1 = or(mask_sub_sub_sub_1_1_1, _mask_sub_sub_acc_T_7)
node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1)
node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1)
node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0))
node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_8 = and(mask_sub_size_1, mask_sub_0_2_1)
node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_8)
node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_9 = and(mask_sub_size_1, mask_sub_1_2_1)
node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_9)
node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_10 = and(mask_sub_size_1, mask_sub_2_2_1)
node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_10)
node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_11 = and(mask_sub_size_1, mask_sub_3_2_1)
node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_11)
node mask_sub_4_2_1 = and(mask_sub_sub_2_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_12 = and(mask_sub_size_1, mask_sub_4_2_1)
node mask_sub_4_1_1 = or(mask_sub_sub_2_1_1, _mask_sub_acc_T_12)
node mask_sub_5_2_1 = and(mask_sub_sub_2_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_13 = and(mask_sub_size_1, mask_sub_5_2_1)
node mask_sub_5_1_1 = or(mask_sub_sub_2_1_1, _mask_sub_acc_T_13)
node mask_sub_6_2_1 = and(mask_sub_sub_3_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_14 = and(mask_sub_size_1, mask_sub_6_2_1)
node mask_sub_6_1_1 = or(mask_sub_sub_3_1_1, _mask_sub_acc_T_14)
node mask_sub_7_2_1 = and(mask_sub_sub_3_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_15 = and(mask_sub_size_1, mask_sub_7_2_1)
node mask_sub_7_1_1 = or(mask_sub_sub_3_1_1, _mask_sub_acc_T_15)
node mask_size_1 = bits(mask_sizeOH_1, 0, 0)
node mask_bit_1 = bits(io.in.b.bits.address, 0, 0)
node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0))
node mask_eq_16 = and(mask_sub_0_2_1, mask_nbit_1)
node _mask_acc_T_16 = and(mask_size_1, mask_eq_16)
node mask_acc_16 = or(mask_sub_0_1_1, _mask_acc_T_16)
node mask_eq_17 = and(mask_sub_0_2_1, mask_bit_1)
node _mask_acc_T_17 = and(mask_size_1, mask_eq_17)
node mask_acc_17 = or(mask_sub_0_1_1, _mask_acc_T_17)
node mask_eq_18 = and(mask_sub_1_2_1, mask_nbit_1)
node _mask_acc_T_18 = and(mask_size_1, mask_eq_18)
node mask_acc_18 = or(mask_sub_1_1_1, _mask_acc_T_18)
node mask_eq_19 = and(mask_sub_1_2_1, mask_bit_1)
node _mask_acc_T_19 = and(mask_size_1, mask_eq_19)
node mask_acc_19 = or(mask_sub_1_1_1, _mask_acc_T_19)
node mask_eq_20 = and(mask_sub_2_2_1, mask_nbit_1)
node _mask_acc_T_20 = and(mask_size_1, mask_eq_20)
node mask_acc_20 = or(mask_sub_2_1_1, _mask_acc_T_20)
node mask_eq_21 = and(mask_sub_2_2_1, mask_bit_1)
node _mask_acc_T_21 = and(mask_size_1, mask_eq_21)
node mask_acc_21 = or(mask_sub_2_1_1, _mask_acc_T_21)
node mask_eq_22 = and(mask_sub_3_2_1, mask_nbit_1)
node _mask_acc_T_22 = and(mask_size_1, mask_eq_22)
node mask_acc_22 = or(mask_sub_3_1_1, _mask_acc_T_22)
node mask_eq_23 = and(mask_sub_3_2_1, mask_bit_1)
node _mask_acc_T_23 = and(mask_size_1, mask_eq_23)
node mask_acc_23 = or(mask_sub_3_1_1, _mask_acc_T_23)
node mask_eq_24 = and(mask_sub_4_2_1, mask_nbit_1)
node _mask_acc_T_24 = and(mask_size_1, mask_eq_24)
node mask_acc_24 = or(mask_sub_4_1_1, _mask_acc_T_24)
node mask_eq_25 = and(mask_sub_4_2_1, mask_bit_1)
node _mask_acc_T_25 = and(mask_size_1, mask_eq_25)
node mask_acc_25 = or(mask_sub_4_1_1, _mask_acc_T_25)
node mask_eq_26 = and(mask_sub_5_2_1, mask_nbit_1)
node _mask_acc_T_26 = and(mask_size_1, mask_eq_26)
node mask_acc_26 = or(mask_sub_5_1_1, _mask_acc_T_26)
node mask_eq_27 = and(mask_sub_5_2_1, mask_bit_1)
node _mask_acc_T_27 = and(mask_size_1, mask_eq_27)
node mask_acc_27 = or(mask_sub_5_1_1, _mask_acc_T_27)
node mask_eq_28 = and(mask_sub_6_2_1, mask_nbit_1)
node _mask_acc_T_28 = and(mask_size_1, mask_eq_28)
node mask_acc_28 = or(mask_sub_6_1_1, _mask_acc_T_28)
node mask_eq_29 = and(mask_sub_6_2_1, mask_bit_1)
node _mask_acc_T_29 = and(mask_size_1, mask_eq_29)
node mask_acc_29 = or(mask_sub_6_1_1, _mask_acc_T_29)
node mask_eq_30 = and(mask_sub_7_2_1, mask_nbit_1)
node _mask_acc_T_30 = and(mask_size_1, mask_eq_30)
node mask_acc_30 = or(mask_sub_7_1_1, _mask_acc_T_30)
node mask_eq_31 = and(mask_sub_7_2_1, mask_bit_1)
node _mask_acc_T_31 = and(mask_size_1, mask_eq_31)
node mask_acc_31 = or(mask_sub_7_1_1, _mask_acc_T_31)
node mask_lo_lo_lo_1 = cat(mask_acc_17, mask_acc_16)
node mask_lo_lo_hi_1 = cat(mask_acc_19, mask_acc_18)
node mask_lo_lo_1 = cat(mask_lo_lo_hi_1, mask_lo_lo_lo_1)
node mask_lo_hi_lo_1 = cat(mask_acc_21, mask_acc_20)
node mask_lo_hi_hi_1 = cat(mask_acc_23, mask_acc_22)
node mask_lo_hi_1 = cat(mask_lo_hi_hi_1, mask_lo_hi_lo_1)
node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1)
node mask_hi_lo_lo_1 = cat(mask_acc_25, mask_acc_24)
node mask_hi_lo_hi_1 = cat(mask_acc_27, mask_acc_26)
node mask_hi_lo_1 = cat(mask_hi_lo_hi_1, mask_hi_lo_lo_1)
node mask_hi_hi_lo_1 = cat(mask_acc_29, mask_acc_28)
node mask_hi_hi_hi_1 = cat(mask_acc_31, mask_acc_30)
node mask_hi_hi_1 = cat(mask_hi_hi_hi_1, mask_hi_hi_lo_1)
node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1)
node mask_1 = cat(mask_hi_1, mask_lo_1)
node _legal_source_T = eq(io.in.b.bits.source, UInt<5>(0h10))
node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<2>(0h0))
node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 1, 0)
node _legal_source_T_1 = shr(io.in.b.bits.source, 2)
node _legal_source_T_2 = eq(_legal_source_T_1, UInt<1>(0h0))
node _legal_source_T_3 = leq(UInt<1>(0h0), legal_source_uncommonBits)
node _legal_source_T_4 = and(_legal_source_T_2, _legal_source_T_3)
node _legal_source_T_5 = leq(legal_source_uncommonBits, UInt<2>(0h3))
node _legal_source_T_6 = and(_legal_source_T_4, _legal_source_T_5)
node _legal_source_uncommonBits_T_1 = or(io.in.b.bits.source, UInt<2>(0h0))
node legal_source_uncommonBits_1 = bits(_legal_source_uncommonBits_T_1, 1, 0)
node _legal_source_T_7 = shr(io.in.b.bits.source, 2)
node _legal_source_T_8 = eq(_legal_source_T_7, UInt<1>(0h1))
node _legal_source_T_9 = leq(UInt<1>(0h0), legal_source_uncommonBits_1)
node _legal_source_T_10 = and(_legal_source_T_8, _legal_source_T_9)
node _legal_source_T_11 = leq(legal_source_uncommonBits_1, UInt<2>(0h3))
node _legal_source_T_12 = and(_legal_source_T_10, _legal_source_T_11)
node _legal_source_uncommonBits_T_2 = or(io.in.b.bits.source, UInt<2>(0h0))
node legal_source_uncommonBits_2 = bits(_legal_source_uncommonBits_T_2, 1, 0)
node _legal_source_T_13 = shr(io.in.b.bits.source, 2)
node _legal_source_T_14 = eq(_legal_source_T_13, UInt<2>(0h2))
node _legal_source_T_15 = leq(UInt<1>(0h0), legal_source_uncommonBits_2)
node _legal_source_T_16 = and(_legal_source_T_14, _legal_source_T_15)
node _legal_source_T_17 = leq(legal_source_uncommonBits_2, UInt<2>(0h3))
node _legal_source_T_18 = and(_legal_source_T_16, _legal_source_T_17)
node _legal_source_uncommonBits_T_3 = or(io.in.b.bits.source, UInt<2>(0h0))
node legal_source_uncommonBits_3 = bits(_legal_source_uncommonBits_T_3, 1, 0)
node _legal_source_T_19 = shr(io.in.b.bits.source, 2)
node _legal_source_T_20 = eq(_legal_source_T_19, UInt<2>(0h3))
node _legal_source_T_21 = leq(UInt<1>(0h0), legal_source_uncommonBits_3)
node _legal_source_T_22 = and(_legal_source_T_20, _legal_source_T_21)
node _legal_source_T_23 = leq(legal_source_uncommonBits_3, UInt<2>(0h3))
node _legal_source_T_24 = and(_legal_source_T_22, _legal_source_T_23)
node _legal_source_uncommonBits_T_4 = or(io.in.b.bits.source, UInt<3>(0h0))
node legal_source_uncommonBits_4 = bits(_legal_source_uncommonBits_T_4, 2, 0)
node _legal_source_T_25 = shr(io.in.b.bits.source, 3)
node _legal_source_T_26 = eq(_legal_source_T_25, UInt<3>(0h4))
node _legal_source_T_27 = leq(UInt<1>(0h0), legal_source_uncommonBits_4)
node _legal_source_T_28 = and(_legal_source_T_26, _legal_source_T_27)
node _legal_source_T_29 = leq(legal_source_uncommonBits_4, UInt<3>(0h7))
node _legal_source_T_30 = and(_legal_source_T_28, _legal_source_T_29)
node _legal_source_T_31 = eq(io.in.b.bits.source, UInt<6>(0h28))
node _legal_source_T_32 = eq(io.in.b.bits.source, UInt<6>(0h2a))
wire _legal_source_WIRE : UInt<1>[8]
connect _legal_source_WIRE[0], _legal_source_T
connect _legal_source_WIRE[1], _legal_source_T_6
connect _legal_source_WIRE[2], _legal_source_T_12
connect _legal_source_WIRE[3], _legal_source_T_18
connect _legal_source_WIRE[4], _legal_source_T_24
connect _legal_source_WIRE[5], _legal_source_T_30
connect _legal_source_WIRE[6], _legal_source_T_31
connect _legal_source_WIRE[7], _legal_source_T_32
node _legal_source_T_33 = mux(_legal_source_WIRE[0], UInt<5>(0h10), UInt<1>(0h0))
node _legal_source_T_34 = mux(_legal_source_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _legal_source_T_35 = mux(_legal_source_WIRE[2], UInt<3>(0h4), UInt<1>(0h0))
node _legal_source_T_36 = mux(_legal_source_WIRE[3], UInt<4>(0h8), UInt<1>(0h0))
node _legal_source_T_37 = mux(_legal_source_WIRE[4], UInt<4>(0hc), UInt<1>(0h0))
node _legal_source_T_38 = mux(_legal_source_WIRE[5], UInt<6>(0h20), UInt<1>(0h0))
node _legal_source_T_39 = mux(_legal_source_WIRE[6], UInt<6>(0h28), UInt<1>(0h0))
node _legal_source_T_40 = mux(_legal_source_WIRE[7], UInt<6>(0h2a), UInt<1>(0h0))
node _legal_source_T_41 = or(_legal_source_T_33, _legal_source_T_34)
node _legal_source_T_42 = or(_legal_source_T_41, _legal_source_T_35)
node _legal_source_T_43 = or(_legal_source_T_42, _legal_source_T_36)
node _legal_source_T_44 = or(_legal_source_T_43, _legal_source_T_37)
node _legal_source_T_45 = or(_legal_source_T_44, _legal_source_T_38)
node _legal_source_T_46 = or(_legal_source_T_45, _legal_source_T_39)
node _legal_source_T_47 = or(_legal_source_T_46, _legal_source_T_40)
wire _legal_source_WIRE_1 : UInt<6>
connect _legal_source_WIRE_1, _legal_source_T_47
node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source)
node _T_1157 = eq(io.in.b.bits.opcode, UInt<3>(0h6))
when _T_1157 :
node _T_1158 = eq(io.in.b.bits.source, UInt<5>(0h10))
node _uncommonBits_T_60 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0)
node _T_1159 = shr(io.in.b.bits.source, 2)
node _T_1160 = eq(_T_1159, UInt<1>(0h0))
node _T_1161 = leq(UInt<1>(0h0), uncommonBits_60)
node _T_1162 = and(_T_1160, _T_1161)
node _T_1163 = leq(uncommonBits_60, UInt<2>(0h3))
node _T_1164 = and(_T_1162, _T_1163)
node _uncommonBits_T_61 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0)
node _T_1165 = shr(io.in.b.bits.source, 2)
node _T_1166 = eq(_T_1165, UInt<1>(0h1))
node _T_1167 = leq(UInt<1>(0h0), uncommonBits_61)
node _T_1168 = and(_T_1166, _T_1167)
node _T_1169 = leq(uncommonBits_61, UInt<2>(0h3))
node _T_1170 = and(_T_1168, _T_1169)
node _uncommonBits_T_62 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0)
node _T_1171 = shr(io.in.b.bits.source, 2)
node _T_1172 = eq(_T_1171, UInt<2>(0h2))
node _T_1173 = leq(UInt<1>(0h0), uncommonBits_62)
node _T_1174 = and(_T_1172, _T_1173)
node _T_1175 = leq(uncommonBits_62, UInt<2>(0h3))
node _T_1176 = and(_T_1174, _T_1175)
node _uncommonBits_T_63 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0)
node _T_1177 = shr(io.in.b.bits.source, 2)
node _T_1178 = eq(_T_1177, UInt<2>(0h3))
node _T_1179 = leq(UInt<1>(0h0), uncommonBits_63)
node _T_1180 = and(_T_1178, _T_1179)
node _T_1181 = leq(uncommonBits_63, UInt<2>(0h3))
node _T_1182 = and(_T_1180, _T_1181)
node _uncommonBits_T_64 = or(io.in.b.bits.source, UInt<3>(0h0))
node uncommonBits_64 = bits(_uncommonBits_T_64, 2, 0)
node _T_1183 = shr(io.in.b.bits.source, 3)
node _T_1184 = eq(_T_1183, UInt<3>(0h4))
node _T_1185 = leq(UInt<1>(0h0), uncommonBits_64)
node _T_1186 = and(_T_1184, _T_1185)
node _T_1187 = leq(uncommonBits_64, UInt<3>(0h7))
node _T_1188 = and(_T_1186, _T_1187)
node _T_1189 = eq(io.in.b.bits.source, UInt<6>(0h28))
node _T_1190 = eq(io.in.b.bits.source, UInt<6>(0h2a))
wire _WIRE_4 : UInt<1>[8]
connect _WIRE_4[0], _T_1158
connect _WIRE_4[1], _T_1164
connect _WIRE_4[2], _T_1170
connect _WIRE_4[3], _T_1176
connect _WIRE_4[4], _T_1182
connect _WIRE_4[5], _T_1188
connect _WIRE_4[6], _T_1189
connect _WIRE_4[7], _T_1190
node _T_1191 = eq(UInt<3>(0h6), io.in.b.bits.size)
node _T_1192 = mux(_WIRE_4[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_1193 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_1194 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_1195 = mux(_WIRE_4[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_1196 = mux(_WIRE_4[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_1197 = mux(_WIRE_4[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_1198 = mux(_WIRE_4[6], _T_1191, UInt<1>(0h0))
node _T_1199 = mux(_WIRE_4[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_1200 = or(_T_1192, _T_1193)
node _T_1201 = or(_T_1200, _T_1194)
node _T_1202 = or(_T_1201, _T_1195)
node _T_1203 = or(_T_1202, _T_1196)
node _T_1204 = or(_T_1203, _T_1197)
node _T_1205 = or(_T_1204, _T_1198)
node _T_1206 = or(_T_1205, _T_1199)
wire _WIRE_5 : UInt<1>
connect _WIRE_5, _T_1206
node _T_1207 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1208 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1209 = and(_T_1207, _T_1208)
node _T_1210 = or(UInt<1>(0h0), _T_1209)
node _T_1211 = xor(io.in.b.bits.address, UInt<28>(0h8000040))
node _T_1212 = cvt(_T_1211)
node _T_1213 = and(_T_1212, asSInt(UInt<17>(0h101c0)))
node _T_1214 = asSInt(_T_1213)
node _T_1215 = eq(_T_1214, asSInt(UInt<1>(0h0)))
node _T_1216 = xor(io.in.b.bits.address, UInt<32>(0h80000040))
node _T_1217 = cvt(_T_1216)
node _T_1218 = and(_T_1217, asSInt(UInt<29>(0h100001c0)))
node _T_1219 = asSInt(_T_1218)
node _T_1220 = eq(_T_1219, asSInt(UInt<1>(0h0)))
node _T_1221 = or(_T_1215, _T_1220)
node _T_1222 = and(_T_1210, _T_1221)
node _T_1223 = or(UInt<1>(0h0), _T_1222)
node _T_1224 = and(_WIRE_5, _T_1223)
node _T_1225 = asUInt(reset)
node _T_1226 = eq(_T_1225, UInt<1>(0h0))
when _T_1226 :
node _T_1227 = eq(_T_1224, UInt<1>(0h0))
when _T_1227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86
assert(clock, _T_1224, UInt<1>(0h1), "") : assert_86
node _T_1228 = asUInt(reset)
node _T_1229 = eq(_T_1228, UInt<1>(0h0))
when _T_1229 :
node _T_1230 = eq(address_ok, UInt<1>(0h0))
when _T_1230 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87
assert(clock, address_ok, UInt<1>(0h1), "") : assert_87
node _T_1231 = asUInt(reset)
node _T_1232 = eq(_T_1231, UInt<1>(0h0))
when _T_1232 :
node _T_1233 = eq(legal_source, UInt<1>(0h0))
when _T_1233 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88
assert(clock, legal_source, UInt<1>(0h1), "") : assert_88
node _T_1234 = asUInt(reset)
node _T_1235 = eq(_T_1234, UInt<1>(0h0))
when _T_1235 :
node _T_1236 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1236 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89
node _T_1237 = leq(io.in.b.bits.param, UInt<2>(0h2))
node _T_1238 = asUInt(reset)
node _T_1239 = eq(_T_1238, UInt<1>(0h0))
when _T_1239 :
node _T_1240 = eq(_T_1237, UInt<1>(0h0))
when _T_1240 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90
assert(clock, _T_1237, UInt<1>(0h1), "") : assert_90
node _T_1241 = eq(io.in.b.bits.mask, mask_1)
node _T_1242 = asUInt(reset)
node _T_1243 = eq(_T_1242, UInt<1>(0h0))
when _T_1243 :
node _T_1244 = eq(_T_1241, UInt<1>(0h0))
when _T_1244 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91
assert(clock, _T_1241, UInt<1>(0h1), "") : assert_91
node _T_1245 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1246 = asUInt(reset)
node _T_1247 = eq(_T_1246, UInt<1>(0h0))
when _T_1247 :
node _T_1248 = eq(_T_1245, UInt<1>(0h0))
when _T_1248 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1245, UInt<1>(0h1), "") : assert_92
node _T_1249 = eq(io.in.b.bits.opcode, UInt<3>(0h4))
when _T_1249 :
node _T_1250 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1251 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1252 = and(_T_1250, _T_1251)
node _T_1253 = or(UInt<1>(0h0), _T_1252)
node _T_1254 = xor(io.in.b.bits.address, UInt<28>(0h8000040))
node _T_1255 = cvt(_T_1254)
node _T_1256 = and(_T_1255, asSInt(UInt<17>(0h101c0)))
node _T_1257 = asSInt(_T_1256)
node _T_1258 = eq(_T_1257, asSInt(UInt<1>(0h0)))
node _T_1259 = xor(io.in.b.bits.address, UInt<32>(0h80000040))
node _T_1260 = cvt(_T_1259)
node _T_1261 = and(_T_1260, asSInt(UInt<29>(0h100001c0)))
node _T_1262 = asSInt(_T_1261)
node _T_1263 = eq(_T_1262, asSInt(UInt<1>(0h0)))
node _T_1264 = or(_T_1258, _T_1263)
node _T_1265 = and(_T_1253, _T_1264)
node _T_1266 = or(UInt<1>(0h0), _T_1265)
node _T_1267 = and(UInt<1>(0h0), _T_1266)
node _T_1268 = asUInt(reset)
node _T_1269 = eq(_T_1268, UInt<1>(0h0))
when _T_1269 :
node _T_1270 = eq(_T_1267, UInt<1>(0h0))
when _T_1270 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93
assert(clock, _T_1267, UInt<1>(0h1), "") : assert_93
node _T_1271 = asUInt(reset)
node _T_1272 = eq(_T_1271, UInt<1>(0h0))
when _T_1272 :
node _T_1273 = eq(address_ok, UInt<1>(0h0))
when _T_1273 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94
assert(clock, address_ok, UInt<1>(0h1), "") : assert_94
node _T_1274 = asUInt(reset)
node _T_1275 = eq(_T_1274, UInt<1>(0h0))
when _T_1275 :
node _T_1276 = eq(legal_source, UInt<1>(0h0))
when _T_1276 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95
assert(clock, legal_source, UInt<1>(0h1), "") : assert_95
node _T_1277 = asUInt(reset)
node _T_1278 = eq(_T_1277, UInt<1>(0h0))
when _T_1278 :
node _T_1279 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1279 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96
node _T_1280 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1281 = asUInt(reset)
node _T_1282 = eq(_T_1281, UInt<1>(0h0))
when _T_1282 :
node _T_1283 = eq(_T_1280, UInt<1>(0h0))
when _T_1283 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97
assert(clock, _T_1280, UInt<1>(0h1), "") : assert_97
node _T_1284 = eq(io.in.b.bits.mask, mask_1)
node _T_1285 = asUInt(reset)
node _T_1286 = eq(_T_1285, UInt<1>(0h0))
when _T_1286 :
node _T_1287 = eq(_T_1284, UInt<1>(0h0))
when _T_1287 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1284, UInt<1>(0h1), "") : assert_98
node _T_1288 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1289 = asUInt(reset)
node _T_1290 = eq(_T_1289, UInt<1>(0h0))
when _T_1290 :
node _T_1291 = eq(_T_1288, UInt<1>(0h0))
when _T_1291 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99
assert(clock, _T_1288, UInt<1>(0h1), "") : assert_99
node _T_1292 = eq(io.in.b.bits.opcode, UInt<1>(0h0))
when _T_1292 :
node _T_1293 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1294 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1295 = and(_T_1293, _T_1294)
node _T_1296 = or(UInt<1>(0h0), _T_1295)
node _T_1297 = xor(io.in.b.bits.address, UInt<28>(0h8000040))
node _T_1298 = cvt(_T_1297)
node _T_1299 = and(_T_1298, asSInt(UInt<17>(0h101c0)))
node _T_1300 = asSInt(_T_1299)
node _T_1301 = eq(_T_1300, asSInt(UInt<1>(0h0)))
node _T_1302 = xor(io.in.b.bits.address, UInt<32>(0h80000040))
node _T_1303 = cvt(_T_1302)
node _T_1304 = and(_T_1303, asSInt(UInt<29>(0h100001c0)))
node _T_1305 = asSInt(_T_1304)
node _T_1306 = eq(_T_1305, asSInt(UInt<1>(0h0)))
node _T_1307 = or(_T_1301, _T_1306)
node _T_1308 = and(_T_1296, _T_1307)
node _T_1309 = or(UInt<1>(0h0), _T_1308)
node _T_1310 = and(UInt<1>(0h0), _T_1309)
node _T_1311 = asUInt(reset)
node _T_1312 = eq(_T_1311, UInt<1>(0h0))
when _T_1312 :
node _T_1313 = eq(_T_1310, UInt<1>(0h0))
when _T_1313 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100
assert(clock, _T_1310, UInt<1>(0h1), "") : assert_100
node _T_1314 = asUInt(reset)
node _T_1315 = eq(_T_1314, UInt<1>(0h0))
when _T_1315 :
node _T_1316 = eq(address_ok, UInt<1>(0h0))
when _T_1316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101
assert(clock, address_ok, UInt<1>(0h1), "") : assert_101
node _T_1317 = asUInt(reset)
node _T_1318 = eq(_T_1317, UInt<1>(0h0))
when _T_1318 :
node _T_1319 = eq(legal_source, UInt<1>(0h0))
when _T_1319 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102
assert(clock, legal_source, UInt<1>(0h1), "") : assert_102
node _T_1320 = asUInt(reset)
node _T_1321 = eq(_T_1320, UInt<1>(0h0))
when _T_1321 :
node _T_1322 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1322 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103
node _T_1323 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1324 = asUInt(reset)
node _T_1325 = eq(_T_1324, UInt<1>(0h0))
when _T_1325 :
node _T_1326 = eq(_T_1323, UInt<1>(0h0))
when _T_1326 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104
assert(clock, _T_1323, UInt<1>(0h1), "") : assert_104
node _T_1327 = eq(io.in.b.bits.mask, mask_1)
node _T_1328 = asUInt(reset)
node _T_1329 = eq(_T_1328, UInt<1>(0h0))
when _T_1329 :
node _T_1330 = eq(_T_1327, UInt<1>(0h0))
when _T_1330 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1327, UInt<1>(0h1), "") : assert_105
node _T_1331 = eq(io.in.b.bits.opcode, UInt<1>(0h1))
when _T_1331 :
node _T_1332 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1333 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1334 = and(_T_1332, _T_1333)
node _T_1335 = or(UInt<1>(0h0), _T_1334)
node _T_1336 = xor(io.in.b.bits.address, UInt<28>(0h8000040))
node _T_1337 = cvt(_T_1336)
node _T_1338 = and(_T_1337, asSInt(UInt<17>(0h101c0)))
node _T_1339 = asSInt(_T_1338)
node _T_1340 = eq(_T_1339, asSInt(UInt<1>(0h0)))
node _T_1341 = xor(io.in.b.bits.address, UInt<32>(0h80000040))
node _T_1342 = cvt(_T_1341)
node _T_1343 = and(_T_1342, asSInt(UInt<29>(0h100001c0)))
node _T_1344 = asSInt(_T_1343)
node _T_1345 = eq(_T_1344, asSInt(UInt<1>(0h0)))
node _T_1346 = or(_T_1340, _T_1345)
node _T_1347 = and(_T_1335, _T_1346)
node _T_1348 = or(UInt<1>(0h0), _T_1347)
node _T_1349 = and(UInt<1>(0h0), _T_1348)
node _T_1350 = asUInt(reset)
node _T_1351 = eq(_T_1350, UInt<1>(0h0))
when _T_1351 :
node _T_1352 = eq(_T_1349, UInt<1>(0h0))
when _T_1352 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1349, UInt<1>(0h1), "") : assert_106
node _T_1353 = asUInt(reset)
node _T_1354 = eq(_T_1353, UInt<1>(0h0))
when _T_1354 :
node _T_1355 = eq(address_ok, UInt<1>(0h0))
when _T_1355 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, address_ok, UInt<1>(0h1), "") : assert_107
node _T_1356 = asUInt(reset)
node _T_1357 = eq(_T_1356, UInt<1>(0h0))
when _T_1357 :
node _T_1358 = eq(legal_source, UInt<1>(0h0))
when _T_1358 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108
assert(clock, legal_source, UInt<1>(0h1), "") : assert_108
node _T_1359 = asUInt(reset)
node _T_1360 = eq(_T_1359, UInt<1>(0h0))
when _T_1360 :
node _T_1361 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1361 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109
node _T_1362 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1363 = asUInt(reset)
node _T_1364 = eq(_T_1363, UInt<1>(0h0))
when _T_1364 :
node _T_1365 = eq(_T_1362, UInt<1>(0h0))
when _T_1365 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110
assert(clock, _T_1362, UInt<1>(0h1), "") : assert_110
node _T_1366 = not(mask_1)
node _T_1367 = and(io.in.b.bits.mask, _T_1366)
node _T_1368 = eq(_T_1367, UInt<1>(0h0))
node _T_1369 = asUInt(reset)
node _T_1370 = eq(_T_1369, UInt<1>(0h0))
when _T_1370 :
node _T_1371 = eq(_T_1368, UInt<1>(0h0))
when _T_1371 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1368, UInt<1>(0h1), "") : assert_111
node _T_1372 = eq(io.in.b.bits.opcode, UInt<2>(0h2))
when _T_1372 :
node _T_1373 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1374 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1375 = and(_T_1373, _T_1374)
node _T_1376 = or(UInt<1>(0h0), _T_1375)
node _T_1377 = xor(io.in.b.bits.address, UInt<28>(0h8000040))
node _T_1378 = cvt(_T_1377)
node _T_1379 = and(_T_1378, asSInt(UInt<17>(0h101c0)))
node _T_1380 = asSInt(_T_1379)
node _T_1381 = eq(_T_1380, asSInt(UInt<1>(0h0)))
node _T_1382 = xor(io.in.b.bits.address, UInt<32>(0h80000040))
node _T_1383 = cvt(_T_1382)
node _T_1384 = and(_T_1383, asSInt(UInt<29>(0h100001c0)))
node _T_1385 = asSInt(_T_1384)
node _T_1386 = eq(_T_1385, asSInt(UInt<1>(0h0)))
node _T_1387 = or(_T_1381, _T_1386)
node _T_1388 = and(_T_1376, _T_1387)
node _T_1389 = or(UInt<1>(0h0), _T_1388)
node _T_1390 = and(UInt<1>(0h0), _T_1389)
node _T_1391 = asUInt(reset)
node _T_1392 = eq(_T_1391, UInt<1>(0h0))
when _T_1392 :
node _T_1393 = eq(_T_1390, UInt<1>(0h0))
when _T_1393 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112
assert(clock, _T_1390, UInt<1>(0h1), "") : assert_112
node _T_1394 = asUInt(reset)
node _T_1395 = eq(_T_1394, UInt<1>(0h0))
when _T_1395 :
node _T_1396 = eq(address_ok, UInt<1>(0h0))
when _T_1396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, address_ok, UInt<1>(0h1), "") : assert_113
node _T_1397 = asUInt(reset)
node _T_1398 = eq(_T_1397, UInt<1>(0h0))
when _T_1398 :
node _T_1399 = eq(legal_source, UInt<1>(0h0))
when _T_1399 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114
assert(clock, legal_source, UInt<1>(0h1), "") : assert_114
node _T_1400 = asUInt(reset)
node _T_1401 = eq(_T_1400, UInt<1>(0h0))
when _T_1401 :
node _T_1402 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1402 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115
node _T_1403 = leq(io.in.b.bits.param, UInt<3>(0h4))
node _T_1404 = asUInt(reset)
node _T_1405 = eq(_T_1404, UInt<1>(0h0))
when _T_1405 :
node _T_1406 = eq(_T_1403, UInt<1>(0h0))
when _T_1406 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116
assert(clock, _T_1403, UInt<1>(0h1), "") : assert_116
node _T_1407 = eq(io.in.b.bits.mask, mask_1)
node _T_1408 = asUInt(reset)
node _T_1409 = eq(_T_1408, UInt<1>(0h0))
when _T_1409 :
node _T_1410 = eq(_T_1407, UInt<1>(0h0))
when _T_1410 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117
assert(clock, _T_1407, UInt<1>(0h1), "") : assert_117
node _T_1411 = eq(io.in.b.bits.opcode, UInt<2>(0h3))
when _T_1411 :
node _T_1412 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1413 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1414 = and(_T_1412, _T_1413)
node _T_1415 = or(UInt<1>(0h0), _T_1414)
node _T_1416 = xor(io.in.b.bits.address, UInt<28>(0h8000040))
node _T_1417 = cvt(_T_1416)
node _T_1418 = and(_T_1417, asSInt(UInt<17>(0h101c0)))
node _T_1419 = asSInt(_T_1418)
node _T_1420 = eq(_T_1419, asSInt(UInt<1>(0h0)))
node _T_1421 = xor(io.in.b.bits.address, UInt<32>(0h80000040))
node _T_1422 = cvt(_T_1421)
node _T_1423 = and(_T_1422, asSInt(UInt<29>(0h100001c0)))
node _T_1424 = asSInt(_T_1423)
node _T_1425 = eq(_T_1424, asSInt(UInt<1>(0h0)))
node _T_1426 = or(_T_1420, _T_1425)
node _T_1427 = and(_T_1415, _T_1426)
node _T_1428 = or(UInt<1>(0h0), _T_1427)
node _T_1429 = and(UInt<1>(0h0), _T_1428)
node _T_1430 = asUInt(reset)
node _T_1431 = eq(_T_1430, UInt<1>(0h0))
when _T_1431 :
node _T_1432 = eq(_T_1429, UInt<1>(0h0))
when _T_1432 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118
assert(clock, _T_1429, UInt<1>(0h1), "") : assert_118
node _T_1433 = asUInt(reset)
node _T_1434 = eq(_T_1433, UInt<1>(0h0))
when _T_1434 :
node _T_1435 = eq(address_ok, UInt<1>(0h0))
when _T_1435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119
assert(clock, address_ok, UInt<1>(0h1), "") : assert_119
node _T_1436 = asUInt(reset)
node _T_1437 = eq(_T_1436, UInt<1>(0h0))
when _T_1437 :
node _T_1438 = eq(legal_source, UInt<1>(0h0))
when _T_1438 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120
assert(clock, legal_source, UInt<1>(0h1), "") : assert_120
node _T_1439 = asUInt(reset)
node _T_1440 = eq(_T_1439, UInt<1>(0h0))
when _T_1440 :
node _T_1441 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1441 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121
node _T_1442 = leq(io.in.b.bits.param, UInt<3>(0h3))
node _T_1443 = asUInt(reset)
node _T_1444 = eq(_T_1443, UInt<1>(0h0))
when _T_1444 :
node _T_1445 = eq(_T_1442, UInt<1>(0h0))
when _T_1445 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122
assert(clock, _T_1442, UInt<1>(0h1), "") : assert_122
node _T_1446 = eq(io.in.b.bits.mask, mask_1)
node _T_1447 = asUInt(reset)
node _T_1448 = eq(_T_1447, UInt<1>(0h0))
when _T_1448 :
node _T_1449 = eq(_T_1446, UInt<1>(0h0))
when _T_1449 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123
assert(clock, _T_1446, UInt<1>(0h1), "") : assert_123
node _T_1450 = eq(io.in.b.bits.opcode, UInt<3>(0h5))
when _T_1450 :
node _T_1451 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1452 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1453 = and(_T_1451, _T_1452)
node _T_1454 = or(UInt<1>(0h0), _T_1453)
node _T_1455 = xor(io.in.b.bits.address, UInt<28>(0h8000040))
node _T_1456 = cvt(_T_1455)
node _T_1457 = and(_T_1456, asSInt(UInt<17>(0h101c0)))
node _T_1458 = asSInt(_T_1457)
node _T_1459 = eq(_T_1458, asSInt(UInt<1>(0h0)))
node _T_1460 = xor(io.in.b.bits.address, UInt<32>(0h80000040))
node _T_1461 = cvt(_T_1460)
node _T_1462 = and(_T_1461, asSInt(UInt<29>(0h100001c0)))
node _T_1463 = asSInt(_T_1462)
node _T_1464 = eq(_T_1463, asSInt(UInt<1>(0h0)))
node _T_1465 = or(_T_1459, _T_1464)
node _T_1466 = and(_T_1454, _T_1465)
node _T_1467 = or(UInt<1>(0h0), _T_1466)
node _T_1468 = and(UInt<1>(0h0), _T_1467)
node _T_1469 = asUInt(reset)
node _T_1470 = eq(_T_1469, UInt<1>(0h0))
when _T_1470 :
node _T_1471 = eq(_T_1468, UInt<1>(0h0))
when _T_1471 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124
assert(clock, _T_1468, UInt<1>(0h1), "") : assert_124
node _T_1472 = asUInt(reset)
node _T_1473 = eq(_T_1472, UInt<1>(0h0))
when _T_1473 :
node _T_1474 = eq(address_ok, UInt<1>(0h0))
when _T_1474 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125
assert(clock, address_ok, UInt<1>(0h1), "") : assert_125
node _T_1475 = asUInt(reset)
node _T_1476 = eq(_T_1475, UInt<1>(0h0))
when _T_1476 :
node _T_1477 = eq(legal_source, UInt<1>(0h0))
when _T_1477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126
assert(clock, legal_source, UInt<1>(0h1), "") : assert_126
node _T_1478 = asUInt(reset)
node _T_1479 = eq(_T_1478, UInt<1>(0h0))
when _T_1479 :
node _T_1480 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1480 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127
node _T_1481 = eq(io.in.b.bits.mask, mask_1)
node _T_1482 = asUInt(reset)
node _T_1483 = eq(_T_1482, UInt<1>(0h0))
when _T_1483 :
node _T_1484 = eq(_T_1481, UInt<1>(0h0))
when _T_1484 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128
assert(clock, _T_1481, UInt<1>(0h1), "") : assert_128
node _T_1485 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1486 = asUInt(reset)
node _T_1487 = eq(_T_1486, UInt<1>(0h0))
when _T_1487 :
node _T_1488 = eq(_T_1485, UInt<1>(0h0))
when _T_1488 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129
assert(clock, _T_1485, UInt<1>(0h1), "") : assert_129
when io.in.c.valid :
node _T_1489 = leq(io.in.c.bits.opcode, UInt<3>(0h7))
node _T_1490 = asUInt(reset)
node _T_1491 = eq(_T_1490, UInt<1>(0h0))
when _T_1491 :
node _T_1492 = eq(_T_1489, UInt<1>(0h0))
when _T_1492 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130
assert(clock, _T_1489, UInt<1>(0h1), "") : assert_130
node _source_ok_T_78 = eq(io.in.c.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_10 = or(io.in.c.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0)
node _source_ok_T_79 = shr(io.in.c.bits.source, 2)
node _source_ok_T_80 = eq(_source_ok_T_79, UInt<1>(0h0))
node _source_ok_T_81 = leq(UInt<1>(0h0), source_ok_uncommonBits_10)
node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81)
node _source_ok_T_83 = leq(source_ok_uncommonBits_10, UInt<2>(0h3))
node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83)
node _source_ok_uncommonBits_T_11 = or(io.in.c.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 1, 0)
node _source_ok_T_85 = shr(io.in.c.bits.source, 2)
node _source_ok_T_86 = eq(_source_ok_T_85, UInt<1>(0h1))
node _source_ok_T_87 = leq(UInt<1>(0h0), source_ok_uncommonBits_11)
node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87)
node _source_ok_T_89 = leq(source_ok_uncommonBits_11, UInt<2>(0h3))
node _source_ok_T_90 = and(_source_ok_T_88, _source_ok_T_89)
node _source_ok_uncommonBits_T_12 = or(io.in.c.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 1, 0)
node _source_ok_T_91 = shr(io.in.c.bits.source, 2)
node _source_ok_T_92 = eq(_source_ok_T_91, UInt<2>(0h2))
node _source_ok_T_93 = leq(UInt<1>(0h0), source_ok_uncommonBits_12)
node _source_ok_T_94 = and(_source_ok_T_92, _source_ok_T_93)
node _source_ok_T_95 = leq(source_ok_uncommonBits_12, UInt<2>(0h3))
node _source_ok_T_96 = and(_source_ok_T_94, _source_ok_T_95)
node _source_ok_uncommonBits_T_13 = or(io.in.c.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 1, 0)
node _source_ok_T_97 = shr(io.in.c.bits.source, 2)
node _source_ok_T_98 = eq(_source_ok_T_97, UInt<2>(0h3))
node _source_ok_T_99 = leq(UInt<1>(0h0), source_ok_uncommonBits_13)
node _source_ok_T_100 = and(_source_ok_T_98, _source_ok_T_99)
node _source_ok_T_101 = leq(source_ok_uncommonBits_13, UInt<2>(0h3))
node _source_ok_T_102 = and(_source_ok_T_100, _source_ok_T_101)
node _source_ok_uncommonBits_T_14 = or(io.in.c.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_14 = bits(_source_ok_uncommonBits_T_14, 2, 0)
node _source_ok_T_103 = shr(io.in.c.bits.source, 3)
node _source_ok_T_104 = eq(_source_ok_T_103, UInt<3>(0h4))
node _source_ok_T_105 = leq(UInt<1>(0h0), source_ok_uncommonBits_14)
node _source_ok_T_106 = and(_source_ok_T_104, _source_ok_T_105)
node _source_ok_T_107 = leq(source_ok_uncommonBits_14, UInt<3>(0h7))
node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107)
node _source_ok_T_109 = eq(io.in.c.bits.source, UInt<6>(0h28))
node _source_ok_T_110 = eq(io.in.c.bits.source, UInt<6>(0h2a))
wire _source_ok_WIRE_2 : UInt<1>[8]
connect _source_ok_WIRE_2[0], _source_ok_T_78
connect _source_ok_WIRE_2[1], _source_ok_T_84
connect _source_ok_WIRE_2[2], _source_ok_T_90
connect _source_ok_WIRE_2[3], _source_ok_T_96
connect _source_ok_WIRE_2[4], _source_ok_T_102
connect _source_ok_WIRE_2[5], _source_ok_T_108
connect _source_ok_WIRE_2[6], _source_ok_T_109
connect _source_ok_WIRE_2[7], _source_ok_T_110
node _source_ok_T_111 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1])
node _source_ok_T_112 = or(_source_ok_T_111, _source_ok_WIRE_2[2])
node _source_ok_T_113 = or(_source_ok_T_112, _source_ok_WIRE_2[3])
node _source_ok_T_114 = or(_source_ok_T_113, _source_ok_WIRE_2[4])
node _source_ok_T_115 = or(_source_ok_T_114, _source_ok_WIRE_2[5])
node _source_ok_T_116 = or(_source_ok_T_115, _source_ok_WIRE_2[6])
node source_ok_2 = or(_source_ok_T_116, _source_ok_WIRE_2[7])
node _is_aligned_mask_T_4 = dshl(UInt<6>(0h3f), io.in.c.bits.size)
node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 5, 0)
node is_aligned_mask_2 = not(_is_aligned_mask_T_5)
node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2)
node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0))
node _address_ok_T_10 = xor(io.in.c.bits.address, UInt<28>(0h8000040))
node _address_ok_T_11 = cvt(_address_ok_T_10)
node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<17>(0h101c0)))
node _address_ok_T_13 = asSInt(_address_ok_T_12)
node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0)))
node _address_ok_T_15 = xor(io.in.c.bits.address, UInt<32>(0h80000040))
node _address_ok_T_16 = cvt(_address_ok_T_15)
node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<29>(0h100001c0)))
node _address_ok_T_18 = asSInt(_address_ok_T_17)
node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE_1 : UInt<1>[2]
connect _address_ok_WIRE_1[0], _address_ok_T_14
connect _address_ok_WIRE_1[1], _address_ok_T_19
node address_ok_1 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1])
node _T_1493 = eq(io.in.c.bits.source, UInt<5>(0h10))
node _T_1494 = eq(_T_1493, UInt<1>(0h0))
node _T_1495 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1496 = cvt(_T_1495)
node _T_1497 = and(_T_1496, asSInt(UInt<1>(0h0)))
node _T_1498 = asSInt(_T_1497)
node _T_1499 = eq(_T_1498, asSInt(UInt<1>(0h0)))
node _T_1500 = or(_T_1494, _T_1499)
node _uncommonBits_T_65 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_65 = bits(_uncommonBits_T_65, 1, 0)
node _T_1501 = shr(io.in.c.bits.source, 2)
node _T_1502 = eq(_T_1501, UInt<1>(0h0))
node _T_1503 = leq(UInt<1>(0h0), uncommonBits_65)
node _T_1504 = and(_T_1502, _T_1503)
node _T_1505 = leq(uncommonBits_65, UInt<2>(0h3))
node _T_1506 = and(_T_1504, _T_1505)
node _T_1507 = eq(_T_1506, UInt<1>(0h0))
node _T_1508 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1509 = cvt(_T_1508)
node _T_1510 = and(_T_1509, asSInt(UInt<1>(0h0)))
node _T_1511 = asSInt(_T_1510)
node _T_1512 = eq(_T_1511, asSInt(UInt<1>(0h0)))
node _T_1513 = or(_T_1507, _T_1512)
node _uncommonBits_T_66 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0)
node _T_1514 = shr(io.in.c.bits.source, 2)
node _T_1515 = eq(_T_1514, UInt<1>(0h1))
node _T_1516 = leq(UInt<1>(0h0), uncommonBits_66)
node _T_1517 = and(_T_1515, _T_1516)
node _T_1518 = leq(uncommonBits_66, UInt<2>(0h3))
node _T_1519 = and(_T_1517, _T_1518)
node _T_1520 = eq(_T_1519, UInt<1>(0h0))
node _T_1521 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1522 = cvt(_T_1521)
node _T_1523 = and(_T_1522, asSInt(UInt<1>(0h0)))
node _T_1524 = asSInt(_T_1523)
node _T_1525 = eq(_T_1524, asSInt(UInt<1>(0h0)))
node _T_1526 = or(_T_1520, _T_1525)
node _uncommonBits_T_67 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_67 = bits(_uncommonBits_T_67, 1, 0)
node _T_1527 = shr(io.in.c.bits.source, 2)
node _T_1528 = eq(_T_1527, UInt<2>(0h2))
node _T_1529 = leq(UInt<1>(0h0), uncommonBits_67)
node _T_1530 = and(_T_1528, _T_1529)
node _T_1531 = leq(uncommonBits_67, UInt<2>(0h3))
node _T_1532 = and(_T_1530, _T_1531)
node _T_1533 = eq(_T_1532, UInt<1>(0h0))
node _T_1534 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1535 = cvt(_T_1534)
node _T_1536 = and(_T_1535, asSInt(UInt<1>(0h0)))
node _T_1537 = asSInt(_T_1536)
node _T_1538 = eq(_T_1537, asSInt(UInt<1>(0h0)))
node _T_1539 = or(_T_1533, _T_1538)
node _uncommonBits_T_68 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_68 = bits(_uncommonBits_T_68, 1, 0)
node _T_1540 = shr(io.in.c.bits.source, 2)
node _T_1541 = eq(_T_1540, UInt<2>(0h3))
node _T_1542 = leq(UInt<1>(0h0), uncommonBits_68)
node _T_1543 = and(_T_1541, _T_1542)
node _T_1544 = leq(uncommonBits_68, UInt<2>(0h3))
node _T_1545 = and(_T_1543, _T_1544)
node _T_1546 = eq(_T_1545, UInt<1>(0h0))
node _T_1547 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1548 = cvt(_T_1547)
node _T_1549 = and(_T_1548, asSInt(UInt<1>(0h0)))
node _T_1550 = asSInt(_T_1549)
node _T_1551 = eq(_T_1550, asSInt(UInt<1>(0h0)))
node _T_1552 = or(_T_1546, _T_1551)
node _uncommonBits_T_69 = or(io.in.c.bits.source, UInt<3>(0h0))
node uncommonBits_69 = bits(_uncommonBits_T_69, 2, 0)
node _T_1553 = shr(io.in.c.bits.source, 3)
node _T_1554 = eq(_T_1553, UInt<3>(0h4))
node _T_1555 = leq(UInt<1>(0h0), uncommonBits_69)
node _T_1556 = and(_T_1554, _T_1555)
node _T_1557 = leq(uncommonBits_69, UInt<3>(0h7))
node _T_1558 = and(_T_1556, _T_1557)
node _T_1559 = eq(_T_1558, UInt<1>(0h0))
node _T_1560 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1561 = cvt(_T_1560)
node _T_1562 = and(_T_1561, asSInt(UInt<1>(0h0)))
node _T_1563 = asSInt(_T_1562)
node _T_1564 = eq(_T_1563, asSInt(UInt<1>(0h0)))
node _T_1565 = or(_T_1559, _T_1564)
node _T_1566 = eq(io.in.c.bits.source, UInt<6>(0h28))
node _T_1567 = eq(_T_1566, UInt<1>(0h0))
node _T_1568 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1569 = cvt(_T_1568)
node _T_1570 = and(_T_1569, asSInt(UInt<1>(0h0)))
node _T_1571 = asSInt(_T_1570)
node _T_1572 = eq(_T_1571, asSInt(UInt<1>(0h0)))
node _T_1573 = or(_T_1567, _T_1572)
node _T_1574 = eq(io.in.c.bits.source, UInt<6>(0h2a))
node _T_1575 = eq(_T_1574, UInt<1>(0h0))
node _T_1576 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1577 = cvt(_T_1576)
node _T_1578 = and(_T_1577, asSInt(UInt<1>(0h0)))
node _T_1579 = asSInt(_T_1578)
node _T_1580 = eq(_T_1579, asSInt(UInt<1>(0h0)))
node _T_1581 = or(_T_1575, _T_1580)
node _T_1582 = and(_T_1500, _T_1513)
node _T_1583 = and(_T_1582, _T_1526)
node _T_1584 = and(_T_1583, _T_1539)
node _T_1585 = and(_T_1584, _T_1552)
node _T_1586 = and(_T_1585, _T_1565)
node _T_1587 = and(_T_1586, _T_1573)
node _T_1588 = and(_T_1587, _T_1581)
node _T_1589 = asUInt(reset)
node _T_1590 = eq(_T_1589, UInt<1>(0h0))
when _T_1590 :
node _T_1591 = eq(_T_1588, UInt<1>(0h0))
when _T_1591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131
assert(clock, _T_1588, UInt<1>(0h1), "") : assert_131
node _T_1592 = eq(io.in.c.bits.opcode, UInt<3>(0h4))
when _T_1592 :
node _T_1593 = asUInt(reset)
node _T_1594 = eq(_T_1593, UInt<1>(0h0))
when _T_1594 :
node _T_1595 = eq(address_ok_1, UInt<1>(0h0))
when _T_1595 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132
node _T_1596 = asUInt(reset)
node _T_1597 = eq(_T_1596, UInt<1>(0h0))
when _T_1597 :
node _T_1598 = eq(source_ok_2, UInt<1>(0h0))
when _T_1598 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133
node _T_1599 = geq(io.in.c.bits.size, UInt<3>(0h4))
node _T_1600 = asUInt(reset)
node _T_1601 = eq(_T_1600, UInt<1>(0h0))
when _T_1601 :
node _T_1602 = eq(_T_1599, UInt<1>(0h0))
when _T_1602 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134
assert(clock, _T_1599, UInt<1>(0h1), "") : assert_134
node _T_1603 = asUInt(reset)
node _T_1604 = eq(_T_1603, UInt<1>(0h0))
when _T_1604 :
node _T_1605 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1605 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135
node _T_1606 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1607 = asUInt(reset)
node _T_1608 = eq(_T_1607, UInt<1>(0h0))
when _T_1608 :
node _T_1609 = eq(_T_1606, UInt<1>(0h0))
when _T_1609 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136
assert(clock, _T_1606, UInt<1>(0h1), "") : assert_136
node _T_1610 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_1611 = asUInt(reset)
node _T_1612 = eq(_T_1611, UInt<1>(0h0))
when _T_1612 :
node _T_1613 = eq(_T_1610, UInt<1>(0h0))
when _T_1613 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137
assert(clock, _T_1610, UInt<1>(0h1), "") : assert_137
node _T_1614 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
when _T_1614 :
node _T_1615 = asUInt(reset)
node _T_1616 = eq(_T_1615, UInt<1>(0h0))
when _T_1616 :
node _T_1617 = eq(address_ok_1, UInt<1>(0h0))
when _T_1617 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138
node _T_1618 = asUInt(reset)
node _T_1619 = eq(_T_1618, UInt<1>(0h0))
when _T_1619 :
node _T_1620 = eq(source_ok_2, UInt<1>(0h0))
when _T_1620 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139
node _T_1621 = geq(io.in.c.bits.size, UInt<3>(0h4))
node _T_1622 = asUInt(reset)
node _T_1623 = eq(_T_1622, UInt<1>(0h0))
when _T_1623 :
node _T_1624 = eq(_T_1621, UInt<1>(0h0))
when _T_1624 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140
assert(clock, _T_1621, UInt<1>(0h1), "") : assert_140
node _T_1625 = asUInt(reset)
node _T_1626 = eq(_T_1625, UInt<1>(0h0))
when _T_1626 :
node _T_1627 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1627 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141
node _T_1628 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1629 = asUInt(reset)
node _T_1630 = eq(_T_1629, UInt<1>(0h0))
when _T_1630 :
node _T_1631 = eq(_T_1628, UInt<1>(0h0))
when _T_1631 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142
assert(clock, _T_1628, UInt<1>(0h1), "") : assert_142
node _T_1632 = eq(io.in.c.bits.opcode, UInt<3>(0h6))
when _T_1632 :
node _T_1633 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1634 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_1635 = and(_T_1633, _T_1634)
node _T_1636 = eq(io.in.c.bits.source, UInt<5>(0h10))
node _uncommonBits_T_70 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_70 = bits(_uncommonBits_T_70, 1, 0)
node _T_1637 = shr(io.in.c.bits.source, 2)
node _T_1638 = eq(_T_1637, UInt<1>(0h0))
node _T_1639 = leq(UInt<1>(0h0), uncommonBits_70)
node _T_1640 = and(_T_1638, _T_1639)
node _T_1641 = leq(uncommonBits_70, UInt<2>(0h3))
node _T_1642 = and(_T_1640, _T_1641)
node _uncommonBits_T_71 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_71 = bits(_uncommonBits_T_71, 1, 0)
node _T_1643 = shr(io.in.c.bits.source, 2)
node _T_1644 = eq(_T_1643, UInt<1>(0h1))
node _T_1645 = leq(UInt<1>(0h0), uncommonBits_71)
node _T_1646 = and(_T_1644, _T_1645)
node _T_1647 = leq(uncommonBits_71, UInt<2>(0h3))
node _T_1648 = and(_T_1646, _T_1647)
node _uncommonBits_T_72 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_72 = bits(_uncommonBits_T_72, 1, 0)
node _T_1649 = shr(io.in.c.bits.source, 2)
node _T_1650 = eq(_T_1649, UInt<2>(0h2))
node _T_1651 = leq(UInt<1>(0h0), uncommonBits_72)
node _T_1652 = and(_T_1650, _T_1651)
node _T_1653 = leq(uncommonBits_72, UInt<2>(0h3))
node _T_1654 = and(_T_1652, _T_1653)
node _uncommonBits_T_73 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_73 = bits(_uncommonBits_T_73, 1, 0)
node _T_1655 = shr(io.in.c.bits.source, 2)
node _T_1656 = eq(_T_1655, UInt<2>(0h3))
node _T_1657 = leq(UInt<1>(0h0), uncommonBits_73)
node _T_1658 = and(_T_1656, _T_1657)
node _T_1659 = leq(uncommonBits_73, UInt<2>(0h3))
node _T_1660 = and(_T_1658, _T_1659)
node _uncommonBits_T_74 = or(io.in.c.bits.source, UInt<3>(0h0))
node uncommonBits_74 = bits(_uncommonBits_T_74, 2, 0)
node _T_1661 = shr(io.in.c.bits.source, 3)
node _T_1662 = eq(_T_1661, UInt<3>(0h4))
node _T_1663 = leq(UInt<1>(0h0), uncommonBits_74)
node _T_1664 = and(_T_1662, _T_1663)
node _T_1665 = leq(uncommonBits_74, UInt<3>(0h7))
node _T_1666 = and(_T_1664, _T_1665)
node _T_1667 = eq(io.in.c.bits.source, UInt<6>(0h28))
node _T_1668 = eq(io.in.c.bits.source, UInt<6>(0h2a))
node _T_1669 = or(_T_1636, _T_1642)
node _T_1670 = or(_T_1669, _T_1648)
node _T_1671 = or(_T_1670, _T_1654)
node _T_1672 = or(_T_1671, _T_1660)
node _T_1673 = or(_T_1672, _T_1666)
node _T_1674 = or(_T_1673, _T_1667)
node _T_1675 = or(_T_1674, _T_1668)
node _T_1676 = and(_T_1635, _T_1675)
node _T_1677 = or(UInt<1>(0h0), _T_1676)
node _T_1678 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_1679 = or(UInt<1>(0h0), _T_1678)
node _T_1680 = xor(io.in.c.bits.address, UInt<28>(0h8000040))
node _T_1681 = cvt(_T_1680)
node _T_1682 = and(_T_1681, asSInt(UInt<17>(0h101c0)))
node _T_1683 = asSInt(_T_1682)
node _T_1684 = eq(_T_1683, asSInt(UInt<1>(0h0)))
node _T_1685 = xor(io.in.c.bits.address, UInt<32>(0h80000040))
node _T_1686 = cvt(_T_1685)
node _T_1687 = and(_T_1686, asSInt(UInt<29>(0h100001c0)))
node _T_1688 = asSInt(_T_1687)
node _T_1689 = eq(_T_1688, asSInt(UInt<1>(0h0)))
node _T_1690 = or(_T_1684, _T_1689)
node _T_1691 = and(_T_1679, _T_1690)
node _T_1692 = or(UInt<1>(0h0), _T_1691)
node _T_1693 = and(_T_1677, _T_1692)
node _T_1694 = asUInt(reset)
node _T_1695 = eq(_T_1694, UInt<1>(0h0))
when _T_1695 :
node _T_1696 = eq(_T_1693, UInt<1>(0h0))
when _T_1696 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143
assert(clock, _T_1693, UInt<1>(0h1), "") : assert_143
node _T_1697 = eq(io.in.c.bits.source, UInt<5>(0h10))
node _uncommonBits_T_75 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_75 = bits(_uncommonBits_T_75, 1, 0)
node _T_1698 = shr(io.in.c.bits.source, 2)
node _T_1699 = eq(_T_1698, UInt<1>(0h0))
node _T_1700 = leq(UInt<1>(0h0), uncommonBits_75)
node _T_1701 = and(_T_1699, _T_1700)
node _T_1702 = leq(uncommonBits_75, UInt<2>(0h3))
node _T_1703 = and(_T_1701, _T_1702)
node _uncommonBits_T_76 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_76 = bits(_uncommonBits_T_76, 1, 0)
node _T_1704 = shr(io.in.c.bits.source, 2)
node _T_1705 = eq(_T_1704, UInt<1>(0h1))
node _T_1706 = leq(UInt<1>(0h0), uncommonBits_76)
node _T_1707 = and(_T_1705, _T_1706)
node _T_1708 = leq(uncommonBits_76, UInt<2>(0h3))
node _T_1709 = and(_T_1707, _T_1708)
node _uncommonBits_T_77 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_77 = bits(_uncommonBits_T_77, 1, 0)
node _T_1710 = shr(io.in.c.bits.source, 2)
node _T_1711 = eq(_T_1710, UInt<2>(0h2))
node _T_1712 = leq(UInt<1>(0h0), uncommonBits_77)
node _T_1713 = and(_T_1711, _T_1712)
node _T_1714 = leq(uncommonBits_77, UInt<2>(0h3))
node _T_1715 = and(_T_1713, _T_1714)
node _uncommonBits_T_78 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_78 = bits(_uncommonBits_T_78, 1, 0)
node _T_1716 = shr(io.in.c.bits.source, 2)
node _T_1717 = eq(_T_1716, UInt<2>(0h3))
node _T_1718 = leq(UInt<1>(0h0), uncommonBits_78)
node _T_1719 = and(_T_1717, _T_1718)
node _T_1720 = leq(uncommonBits_78, UInt<2>(0h3))
node _T_1721 = and(_T_1719, _T_1720)
node _uncommonBits_T_79 = or(io.in.c.bits.source, UInt<3>(0h0))
node uncommonBits_79 = bits(_uncommonBits_T_79, 2, 0)
node _T_1722 = shr(io.in.c.bits.source, 3)
node _T_1723 = eq(_T_1722, UInt<3>(0h4))
node _T_1724 = leq(UInt<1>(0h0), uncommonBits_79)
node _T_1725 = and(_T_1723, _T_1724)
node _T_1726 = leq(uncommonBits_79, UInt<3>(0h7))
node _T_1727 = and(_T_1725, _T_1726)
node _T_1728 = eq(io.in.c.bits.source, UInt<6>(0h28))
node _T_1729 = eq(io.in.c.bits.source, UInt<6>(0h2a))
wire _WIRE_6 : UInt<1>[8]
connect _WIRE_6[0], _T_1697
connect _WIRE_6[1], _T_1703
connect _WIRE_6[2], _T_1709
connect _WIRE_6[3], _T_1715
connect _WIRE_6[4], _T_1721
connect _WIRE_6[5], _T_1727
connect _WIRE_6[6], _T_1728
connect _WIRE_6[7], _T_1729
node _T_1730 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_1731 = mux(_WIRE_6[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_1732 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_1733 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_1734 = mux(_WIRE_6[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_1735 = mux(_WIRE_6[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_1736 = mux(_WIRE_6[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_1737 = mux(_WIRE_6[6], _T_1730, UInt<1>(0h0))
node _T_1738 = mux(_WIRE_6[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_1739 = or(_T_1731, _T_1732)
node _T_1740 = or(_T_1739, _T_1733)
node _T_1741 = or(_T_1740, _T_1734)
node _T_1742 = or(_T_1741, _T_1735)
node _T_1743 = or(_T_1742, _T_1736)
node _T_1744 = or(_T_1743, _T_1737)
node _T_1745 = or(_T_1744, _T_1738)
wire _WIRE_7 : UInt<1>
connect _WIRE_7, _T_1745
node _T_1746 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1747 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_1748 = and(_T_1746, _T_1747)
node _T_1749 = or(UInt<1>(0h0), _T_1748)
node _T_1750 = xor(io.in.c.bits.address, UInt<28>(0h8000040))
node _T_1751 = cvt(_T_1750)
node _T_1752 = and(_T_1751, asSInt(UInt<17>(0h101c0)))
node _T_1753 = asSInt(_T_1752)
node _T_1754 = eq(_T_1753, asSInt(UInt<1>(0h0)))
node _T_1755 = xor(io.in.c.bits.address, UInt<32>(0h80000040))
node _T_1756 = cvt(_T_1755)
node _T_1757 = and(_T_1756, asSInt(UInt<29>(0h100001c0)))
node _T_1758 = asSInt(_T_1757)
node _T_1759 = eq(_T_1758, asSInt(UInt<1>(0h0)))
node _T_1760 = or(_T_1754, _T_1759)
node _T_1761 = and(_T_1749, _T_1760)
node _T_1762 = or(UInt<1>(0h0), _T_1761)
node _T_1763 = and(_WIRE_7, _T_1762)
node _T_1764 = asUInt(reset)
node _T_1765 = eq(_T_1764, UInt<1>(0h0))
when _T_1765 :
node _T_1766 = eq(_T_1763, UInt<1>(0h0))
when _T_1766 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144
assert(clock, _T_1763, UInt<1>(0h1), "") : assert_144
node _T_1767 = asUInt(reset)
node _T_1768 = eq(_T_1767, UInt<1>(0h0))
when _T_1768 :
node _T_1769 = eq(source_ok_2, UInt<1>(0h0))
when _T_1769 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145
node _T_1770 = geq(io.in.c.bits.size, UInt<3>(0h4))
node _T_1771 = asUInt(reset)
node _T_1772 = eq(_T_1771, UInt<1>(0h0))
when _T_1772 :
node _T_1773 = eq(_T_1770, UInt<1>(0h0))
when _T_1773 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146
assert(clock, _T_1770, UInt<1>(0h1), "") : assert_146
node _T_1774 = asUInt(reset)
node _T_1775 = eq(_T_1774, UInt<1>(0h0))
when _T_1775 :
node _T_1776 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1776 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147
node _T_1777 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1778 = asUInt(reset)
node _T_1779 = eq(_T_1778, UInt<1>(0h0))
when _T_1779 :
node _T_1780 = eq(_T_1777, UInt<1>(0h0))
when _T_1780 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148
assert(clock, _T_1777, UInt<1>(0h1), "") : assert_148
node _T_1781 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_1782 = asUInt(reset)
node _T_1783 = eq(_T_1782, UInt<1>(0h0))
when _T_1783 :
node _T_1784 = eq(_T_1781, UInt<1>(0h0))
when _T_1784 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149
assert(clock, _T_1781, UInt<1>(0h1), "") : assert_149
node _T_1785 = eq(io.in.c.bits.opcode, UInt<3>(0h7))
when _T_1785 :
node _T_1786 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1787 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_1788 = and(_T_1786, _T_1787)
node _T_1789 = eq(io.in.c.bits.source, UInt<5>(0h10))
node _uncommonBits_T_80 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_80 = bits(_uncommonBits_T_80, 1, 0)
node _T_1790 = shr(io.in.c.bits.source, 2)
node _T_1791 = eq(_T_1790, UInt<1>(0h0))
node _T_1792 = leq(UInt<1>(0h0), uncommonBits_80)
node _T_1793 = and(_T_1791, _T_1792)
node _T_1794 = leq(uncommonBits_80, UInt<2>(0h3))
node _T_1795 = and(_T_1793, _T_1794)
node _uncommonBits_T_81 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_81 = bits(_uncommonBits_T_81, 1, 0)
node _T_1796 = shr(io.in.c.bits.source, 2)
node _T_1797 = eq(_T_1796, UInt<1>(0h1))
node _T_1798 = leq(UInt<1>(0h0), uncommonBits_81)
node _T_1799 = and(_T_1797, _T_1798)
node _T_1800 = leq(uncommonBits_81, UInt<2>(0h3))
node _T_1801 = and(_T_1799, _T_1800)
node _uncommonBits_T_82 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_82 = bits(_uncommonBits_T_82, 1, 0)
node _T_1802 = shr(io.in.c.bits.source, 2)
node _T_1803 = eq(_T_1802, UInt<2>(0h2))
node _T_1804 = leq(UInt<1>(0h0), uncommonBits_82)
node _T_1805 = and(_T_1803, _T_1804)
node _T_1806 = leq(uncommonBits_82, UInt<2>(0h3))
node _T_1807 = and(_T_1805, _T_1806)
node _uncommonBits_T_83 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_83 = bits(_uncommonBits_T_83, 1, 0)
node _T_1808 = shr(io.in.c.bits.source, 2)
node _T_1809 = eq(_T_1808, UInt<2>(0h3))
node _T_1810 = leq(UInt<1>(0h0), uncommonBits_83)
node _T_1811 = and(_T_1809, _T_1810)
node _T_1812 = leq(uncommonBits_83, UInt<2>(0h3))
node _T_1813 = and(_T_1811, _T_1812)
node _uncommonBits_T_84 = or(io.in.c.bits.source, UInt<3>(0h0))
node uncommonBits_84 = bits(_uncommonBits_T_84, 2, 0)
node _T_1814 = shr(io.in.c.bits.source, 3)
node _T_1815 = eq(_T_1814, UInt<3>(0h4))
node _T_1816 = leq(UInt<1>(0h0), uncommonBits_84)
node _T_1817 = and(_T_1815, _T_1816)
node _T_1818 = leq(uncommonBits_84, UInt<3>(0h7))
node _T_1819 = and(_T_1817, _T_1818)
node _T_1820 = eq(io.in.c.bits.source, UInt<6>(0h28))
node _T_1821 = eq(io.in.c.bits.source, UInt<6>(0h2a))
node _T_1822 = or(_T_1789, _T_1795)
node _T_1823 = or(_T_1822, _T_1801)
node _T_1824 = or(_T_1823, _T_1807)
node _T_1825 = or(_T_1824, _T_1813)
node _T_1826 = or(_T_1825, _T_1819)
node _T_1827 = or(_T_1826, _T_1820)
node _T_1828 = or(_T_1827, _T_1821)
node _T_1829 = and(_T_1788, _T_1828)
node _T_1830 = or(UInt<1>(0h0), _T_1829)
node _T_1831 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_1832 = or(UInt<1>(0h0), _T_1831)
node _T_1833 = xor(io.in.c.bits.address, UInt<28>(0h8000040))
node _T_1834 = cvt(_T_1833)
node _T_1835 = and(_T_1834, asSInt(UInt<17>(0h101c0)))
node _T_1836 = asSInt(_T_1835)
node _T_1837 = eq(_T_1836, asSInt(UInt<1>(0h0)))
node _T_1838 = xor(io.in.c.bits.address, UInt<32>(0h80000040))
node _T_1839 = cvt(_T_1838)
node _T_1840 = and(_T_1839, asSInt(UInt<29>(0h100001c0)))
node _T_1841 = asSInt(_T_1840)
node _T_1842 = eq(_T_1841, asSInt(UInt<1>(0h0)))
node _T_1843 = or(_T_1837, _T_1842)
node _T_1844 = and(_T_1832, _T_1843)
node _T_1845 = or(UInt<1>(0h0), _T_1844)
node _T_1846 = and(_T_1830, _T_1845)
node _T_1847 = asUInt(reset)
node _T_1848 = eq(_T_1847, UInt<1>(0h0))
when _T_1848 :
node _T_1849 = eq(_T_1846, UInt<1>(0h0))
when _T_1849 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150
assert(clock, _T_1846, UInt<1>(0h1), "") : assert_150
node _T_1850 = eq(io.in.c.bits.source, UInt<5>(0h10))
node _uncommonBits_T_85 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_85 = bits(_uncommonBits_T_85, 1, 0)
node _T_1851 = shr(io.in.c.bits.source, 2)
node _T_1852 = eq(_T_1851, UInt<1>(0h0))
node _T_1853 = leq(UInt<1>(0h0), uncommonBits_85)
node _T_1854 = and(_T_1852, _T_1853)
node _T_1855 = leq(uncommonBits_85, UInt<2>(0h3))
node _T_1856 = and(_T_1854, _T_1855)
node _uncommonBits_T_86 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_86 = bits(_uncommonBits_T_86, 1, 0)
node _T_1857 = shr(io.in.c.bits.source, 2)
node _T_1858 = eq(_T_1857, UInt<1>(0h1))
node _T_1859 = leq(UInt<1>(0h0), uncommonBits_86)
node _T_1860 = and(_T_1858, _T_1859)
node _T_1861 = leq(uncommonBits_86, UInt<2>(0h3))
node _T_1862 = and(_T_1860, _T_1861)
node _uncommonBits_T_87 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_87 = bits(_uncommonBits_T_87, 1, 0)
node _T_1863 = shr(io.in.c.bits.source, 2)
node _T_1864 = eq(_T_1863, UInt<2>(0h2))
node _T_1865 = leq(UInt<1>(0h0), uncommonBits_87)
node _T_1866 = and(_T_1864, _T_1865)
node _T_1867 = leq(uncommonBits_87, UInt<2>(0h3))
node _T_1868 = and(_T_1866, _T_1867)
node _uncommonBits_T_88 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_88 = bits(_uncommonBits_T_88, 1, 0)
node _T_1869 = shr(io.in.c.bits.source, 2)
node _T_1870 = eq(_T_1869, UInt<2>(0h3))
node _T_1871 = leq(UInt<1>(0h0), uncommonBits_88)
node _T_1872 = and(_T_1870, _T_1871)
node _T_1873 = leq(uncommonBits_88, UInt<2>(0h3))
node _T_1874 = and(_T_1872, _T_1873)
node _uncommonBits_T_89 = or(io.in.c.bits.source, UInt<3>(0h0))
node uncommonBits_89 = bits(_uncommonBits_T_89, 2, 0)
node _T_1875 = shr(io.in.c.bits.source, 3)
node _T_1876 = eq(_T_1875, UInt<3>(0h4))
node _T_1877 = leq(UInt<1>(0h0), uncommonBits_89)
node _T_1878 = and(_T_1876, _T_1877)
node _T_1879 = leq(uncommonBits_89, UInt<3>(0h7))
node _T_1880 = and(_T_1878, _T_1879)
node _T_1881 = eq(io.in.c.bits.source, UInt<6>(0h28))
node _T_1882 = eq(io.in.c.bits.source, UInt<6>(0h2a))
wire _WIRE_8 : UInt<1>[8]
connect _WIRE_8[0], _T_1850
connect _WIRE_8[1], _T_1856
connect _WIRE_8[2], _T_1862
connect _WIRE_8[3], _T_1868
connect _WIRE_8[4], _T_1874
connect _WIRE_8[5], _T_1880
connect _WIRE_8[6], _T_1881
connect _WIRE_8[7], _T_1882
node _T_1883 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_1884 = mux(_WIRE_8[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_1885 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_1886 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_1887 = mux(_WIRE_8[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_1888 = mux(_WIRE_8[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_1889 = mux(_WIRE_8[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_1890 = mux(_WIRE_8[6], _T_1883, UInt<1>(0h0))
node _T_1891 = mux(_WIRE_8[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_1892 = or(_T_1884, _T_1885)
node _T_1893 = or(_T_1892, _T_1886)
node _T_1894 = or(_T_1893, _T_1887)
node _T_1895 = or(_T_1894, _T_1888)
node _T_1896 = or(_T_1895, _T_1889)
node _T_1897 = or(_T_1896, _T_1890)
node _T_1898 = or(_T_1897, _T_1891)
wire _WIRE_9 : UInt<1>
connect _WIRE_9, _T_1898
node _T_1899 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1900 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_1901 = and(_T_1899, _T_1900)
node _T_1902 = or(UInt<1>(0h0), _T_1901)
node _T_1903 = xor(io.in.c.bits.address, UInt<28>(0h8000040))
node _T_1904 = cvt(_T_1903)
node _T_1905 = and(_T_1904, asSInt(UInt<17>(0h101c0)))
node _T_1906 = asSInt(_T_1905)
node _T_1907 = eq(_T_1906, asSInt(UInt<1>(0h0)))
node _T_1908 = xor(io.in.c.bits.address, UInt<32>(0h80000040))
node _T_1909 = cvt(_T_1908)
node _T_1910 = and(_T_1909, asSInt(UInt<29>(0h100001c0)))
node _T_1911 = asSInt(_T_1910)
node _T_1912 = eq(_T_1911, asSInt(UInt<1>(0h0)))
node _T_1913 = or(_T_1907, _T_1912)
node _T_1914 = and(_T_1902, _T_1913)
node _T_1915 = or(UInt<1>(0h0), _T_1914)
node _T_1916 = and(_WIRE_9, _T_1915)
node _T_1917 = asUInt(reset)
node _T_1918 = eq(_T_1917, UInt<1>(0h0))
when _T_1918 :
node _T_1919 = eq(_T_1916, UInt<1>(0h0))
when _T_1919 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151
assert(clock, _T_1916, UInt<1>(0h1), "") : assert_151
node _T_1920 = asUInt(reset)
node _T_1921 = eq(_T_1920, UInt<1>(0h0))
when _T_1921 :
node _T_1922 = eq(source_ok_2, UInt<1>(0h0))
when _T_1922 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152
node _T_1923 = geq(io.in.c.bits.size, UInt<3>(0h4))
node _T_1924 = asUInt(reset)
node _T_1925 = eq(_T_1924, UInt<1>(0h0))
when _T_1925 :
node _T_1926 = eq(_T_1923, UInt<1>(0h0))
when _T_1926 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153
assert(clock, _T_1923, UInt<1>(0h1), "") : assert_153
node _T_1927 = asUInt(reset)
node _T_1928 = eq(_T_1927, UInt<1>(0h0))
when _T_1928 :
node _T_1929 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1929 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154
node _T_1930 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1931 = asUInt(reset)
node _T_1932 = eq(_T_1931, UInt<1>(0h0))
when _T_1932 :
node _T_1933 = eq(_T_1930, UInt<1>(0h0))
when _T_1933 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155
assert(clock, _T_1930, UInt<1>(0h1), "") : assert_155
node _T_1934 = eq(io.in.c.bits.opcode, UInt<1>(0h0))
when _T_1934 :
node _T_1935 = asUInt(reset)
node _T_1936 = eq(_T_1935, UInt<1>(0h0))
when _T_1936 :
node _T_1937 = eq(address_ok_1, UInt<1>(0h0))
when _T_1937 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156
node _T_1938 = asUInt(reset)
node _T_1939 = eq(_T_1938, UInt<1>(0h0))
when _T_1939 :
node _T_1940 = eq(source_ok_2, UInt<1>(0h0))
when _T_1940 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157
node _T_1941 = asUInt(reset)
node _T_1942 = eq(_T_1941, UInt<1>(0h0))
when _T_1942 :
node _T_1943 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1943 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158
node _T_1944 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_1945 = asUInt(reset)
node _T_1946 = eq(_T_1945, UInt<1>(0h0))
when _T_1946 :
node _T_1947 = eq(_T_1944, UInt<1>(0h0))
when _T_1947 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159
assert(clock, _T_1944, UInt<1>(0h1), "") : assert_159
node _T_1948 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_1949 = asUInt(reset)
node _T_1950 = eq(_T_1949, UInt<1>(0h0))
when _T_1950 :
node _T_1951 = eq(_T_1948, UInt<1>(0h0))
when _T_1951 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160
assert(clock, _T_1948, UInt<1>(0h1), "") : assert_160
node _T_1952 = eq(io.in.c.bits.opcode, UInt<1>(0h1))
when _T_1952 :
node _T_1953 = asUInt(reset)
node _T_1954 = eq(_T_1953, UInt<1>(0h0))
when _T_1954 :
node _T_1955 = eq(address_ok_1, UInt<1>(0h0))
when _T_1955 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161
node _T_1956 = asUInt(reset)
node _T_1957 = eq(_T_1956, UInt<1>(0h0))
when _T_1957 :
node _T_1958 = eq(source_ok_2, UInt<1>(0h0))
when _T_1958 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162
node _T_1959 = asUInt(reset)
node _T_1960 = eq(_T_1959, UInt<1>(0h0))
when _T_1960 :
node _T_1961 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1961 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163
node _T_1962 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_1963 = asUInt(reset)
node _T_1964 = eq(_T_1963, UInt<1>(0h0))
when _T_1964 :
node _T_1965 = eq(_T_1962, UInt<1>(0h0))
when _T_1965 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164
assert(clock, _T_1962, UInt<1>(0h1), "") : assert_164
node _T_1966 = eq(io.in.c.bits.opcode, UInt<2>(0h2))
when _T_1966 :
node _T_1967 = asUInt(reset)
node _T_1968 = eq(_T_1967, UInt<1>(0h0))
when _T_1968 :
node _T_1969 = eq(address_ok_1, UInt<1>(0h0))
when _T_1969 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165
node _T_1970 = asUInt(reset)
node _T_1971 = eq(_T_1970, UInt<1>(0h0))
when _T_1971 :
node _T_1972 = eq(source_ok_2, UInt<1>(0h0))
when _T_1972 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166
node _T_1973 = asUInt(reset)
node _T_1974 = eq(_T_1973, UInt<1>(0h0))
when _T_1974 :
node _T_1975 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1975 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167
node _T_1976 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_1977 = asUInt(reset)
node _T_1978 = eq(_T_1977, UInt<1>(0h0))
when _T_1978 :
node _T_1979 = eq(_T_1976, UInt<1>(0h0))
when _T_1979 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168
assert(clock, _T_1976, UInt<1>(0h1), "") : assert_168
node _T_1980 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_1981 = asUInt(reset)
node _T_1982 = eq(_T_1981, UInt<1>(0h0))
when _T_1982 :
node _T_1983 = eq(_T_1980, UInt<1>(0h0))
when _T_1983 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169
assert(clock, _T_1980, UInt<1>(0h1), "") : assert_169
when io.in.e.valid :
node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0hc))
node _T_1984 = asUInt(reset)
node _T_1985 = eq(_T_1984, UInt<1>(0h0))
when _T_1985 :
node _T_1986 = eq(sink_ok_1, UInt<1>(0h0))
when _T_1986 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170
assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<2>, clock, reset, UInt<2>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1987 = eq(a_first, UInt<1>(0h0))
node _T_1988 = and(io.in.a.valid, _T_1987)
when _T_1988 :
node _T_1989 = eq(io.in.a.bits.opcode, opcode)
node _T_1990 = asUInt(reset)
node _T_1991 = eq(_T_1990, UInt<1>(0h0))
when _T_1991 :
node _T_1992 = eq(_T_1989, UInt<1>(0h0))
when _T_1992 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171
assert(clock, _T_1989, UInt<1>(0h1), "") : assert_171
node _T_1993 = eq(io.in.a.bits.param, param)
node _T_1994 = asUInt(reset)
node _T_1995 = eq(_T_1994, UInt<1>(0h0))
when _T_1995 :
node _T_1996 = eq(_T_1993, UInt<1>(0h0))
when _T_1996 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172
assert(clock, _T_1993, UInt<1>(0h1), "") : assert_172
node _T_1997 = eq(io.in.a.bits.size, size)
node _T_1998 = asUInt(reset)
node _T_1999 = eq(_T_1998, UInt<1>(0h0))
when _T_1999 :
node _T_2000 = eq(_T_1997, UInt<1>(0h0))
when _T_2000 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173
assert(clock, _T_1997, UInt<1>(0h1), "") : assert_173
node _T_2001 = eq(io.in.a.bits.source, source)
node _T_2002 = asUInt(reset)
node _T_2003 = eq(_T_2002, UInt<1>(0h0))
when _T_2003 :
node _T_2004 = eq(_T_2001, UInt<1>(0h0))
when _T_2004 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174
assert(clock, _T_2001, UInt<1>(0h1), "") : assert_174
node _T_2005 = eq(io.in.a.bits.address, address)
node _T_2006 = asUInt(reset)
node _T_2007 = eq(_T_2006, UInt<1>(0h0))
when _T_2007 :
node _T_2008 = eq(_T_2005, UInt<1>(0h0))
when _T_2008 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175
assert(clock, _T_2005, UInt<1>(0h1), "") : assert_175
node _T_2009 = and(io.in.a.ready, io.in.a.valid)
node _T_2010 = and(_T_2009, a_first)
when _T_2010 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<2>, clock, reset, UInt<2>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_2011 = eq(d_first, UInt<1>(0h0))
node _T_2012 = and(io.in.d.valid, _T_2011)
when _T_2012 :
node _T_2013 = eq(io.in.d.bits.opcode, opcode_1)
node _T_2014 = asUInt(reset)
node _T_2015 = eq(_T_2014, UInt<1>(0h0))
when _T_2015 :
node _T_2016 = eq(_T_2013, UInt<1>(0h0))
when _T_2016 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176
assert(clock, _T_2013, UInt<1>(0h1), "") : assert_176
node _T_2017 = eq(io.in.d.bits.param, param_1)
node _T_2018 = asUInt(reset)
node _T_2019 = eq(_T_2018, UInt<1>(0h0))
when _T_2019 :
node _T_2020 = eq(_T_2017, UInt<1>(0h0))
when _T_2020 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177
assert(clock, _T_2017, UInt<1>(0h1), "") : assert_177
node _T_2021 = eq(io.in.d.bits.size, size_1)
node _T_2022 = asUInt(reset)
node _T_2023 = eq(_T_2022, UInt<1>(0h0))
when _T_2023 :
node _T_2024 = eq(_T_2021, UInt<1>(0h0))
when _T_2024 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178
assert(clock, _T_2021, UInt<1>(0h1), "") : assert_178
node _T_2025 = eq(io.in.d.bits.source, source_1)
node _T_2026 = asUInt(reset)
node _T_2027 = eq(_T_2026, UInt<1>(0h0))
when _T_2027 :
node _T_2028 = eq(_T_2025, UInt<1>(0h0))
when _T_2028 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179
assert(clock, _T_2025, UInt<1>(0h1), "") : assert_179
node _T_2029 = eq(io.in.d.bits.sink, sink)
node _T_2030 = asUInt(reset)
node _T_2031 = eq(_T_2030, UInt<1>(0h0))
when _T_2031 :
node _T_2032 = eq(_T_2029, UInt<1>(0h0))
when _T_2032 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180
assert(clock, _T_2029, UInt<1>(0h1), "") : assert_180
node _T_2033 = eq(io.in.d.bits.denied, denied)
node _T_2034 = asUInt(reset)
node _T_2035 = eq(_T_2034, UInt<1>(0h0))
when _T_2035 :
node _T_2036 = eq(_T_2033, UInt<1>(0h0))
when _T_2036 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181
assert(clock, _T_2033, UInt<1>(0h1), "") : assert_181
node _T_2037 = and(io.in.d.ready, io.in.d.valid)
node _T_2038 = and(_T_2037, d_first)
when _T_2038 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
node _b_first_T = and(io.in.b.ready, io.in.b.valid)
node _b_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.b.bits.size)
node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 5, 0)
node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1)
node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 4)
node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2)
node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0))
node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0))
regreset b_first_counter : UInt<2>, clock, reset, UInt<2>(0h0)
node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1))
node b_first_counter1 = tail(_b_first_counter1_T, 1)
node b_first = eq(b_first_counter, UInt<1>(0h0))
node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1))
node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0))
node b_first_last = or(_b_first_last_T, _b_first_last_T_1)
node b_first_done = and(b_first_last, _b_first_T)
node _b_first_count_T = not(b_first_counter1)
node b_first_count = and(b_first_beats1, _b_first_count_T)
when _b_first_T :
node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1)
connect b_first_counter, _b_first_counter_T
reg opcode_2 : UInt, clock
reg param_2 : UInt, clock
reg size_2 : UInt, clock
reg source_2 : UInt, clock
reg address_1 : UInt, clock
node _T_2039 = eq(b_first, UInt<1>(0h0))
node _T_2040 = and(io.in.b.valid, _T_2039)
when _T_2040 :
node _T_2041 = eq(io.in.b.bits.opcode, opcode_2)
node _T_2042 = asUInt(reset)
node _T_2043 = eq(_T_2042, UInt<1>(0h0))
when _T_2043 :
node _T_2044 = eq(_T_2041, UInt<1>(0h0))
when _T_2044 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182
assert(clock, _T_2041, UInt<1>(0h1), "") : assert_182
node _T_2045 = eq(io.in.b.bits.param, param_2)
node _T_2046 = asUInt(reset)
node _T_2047 = eq(_T_2046, UInt<1>(0h0))
when _T_2047 :
node _T_2048 = eq(_T_2045, UInt<1>(0h0))
when _T_2048 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183
assert(clock, _T_2045, UInt<1>(0h1), "") : assert_183
node _T_2049 = eq(io.in.b.bits.size, size_2)
node _T_2050 = asUInt(reset)
node _T_2051 = eq(_T_2050, UInt<1>(0h0))
when _T_2051 :
node _T_2052 = eq(_T_2049, UInt<1>(0h0))
when _T_2052 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184
assert(clock, _T_2049, UInt<1>(0h1), "") : assert_184
node _T_2053 = eq(io.in.b.bits.source, source_2)
node _T_2054 = asUInt(reset)
node _T_2055 = eq(_T_2054, UInt<1>(0h0))
when _T_2055 :
node _T_2056 = eq(_T_2053, UInt<1>(0h0))
when _T_2056 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185
assert(clock, _T_2053, UInt<1>(0h1), "") : assert_185
node _T_2057 = eq(io.in.b.bits.address, address_1)
node _T_2058 = asUInt(reset)
node _T_2059 = eq(_T_2058, UInt<1>(0h0))
when _T_2059 :
node _T_2060 = eq(_T_2057, UInt<1>(0h0))
when _T_2060 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186
assert(clock, _T_2057, UInt<1>(0h1), "") : assert_186
node _T_2061 = and(io.in.b.ready, io.in.b.valid)
node _T_2062 = and(_T_2061, b_first)
when _T_2062 :
connect opcode_2, io.in.b.bits.opcode
connect param_2, io.in.b.bits.param
connect size_2, io.in.b.bits.size
connect source_2, io.in.b.bits.source
connect address_1, io.in.b.bits.address
node _c_first_T = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.c.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4)
node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<2>, clock, reset, UInt<2>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
reg opcode_3 : UInt, clock
reg param_3 : UInt, clock
reg size_3 : UInt, clock
reg source_3 : UInt, clock
reg address_2 : UInt, clock
node _T_2063 = eq(c_first, UInt<1>(0h0))
node _T_2064 = and(io.in.c.valid, _T_2063)
when _T_2064 :
node _T_2065 = eq(io.in.c.bits.opcode, opcode_3)
node _T_2066 = asUInt(reset)
node _T_2067 = eq(_T_2066, UInt<1>(0h0))
when _T_2067 :
node _T_2068 = eq(_T_2065, UInt<1>(0h0))
when _T_2068 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187
assert(clock, _T_2065, UInt<1>(0h1), "") : assert_187
node _T_2069 = eq(io.in.c.bits.param, param_3)
node _T_2070 = asUInt(reset)
node _T_2071 = eq(_T_2070, UInt<1>(0h0))
when _T_2071 :
node _T_2072 = eq(_T_2069, UInt<1>(0h0))
when _T_2072 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188
assert(clock, _T_2069, UInt<1>(0h1), "") : assert_188
node _T_2073 = eq(io.in.c.bits.size, size_3)
node _T_2074 = asUInt(reset)
node _T_2075 = eq(_T_2074, UInt<1>(0h0))
when _T_2075 :
node _T_2076 = eq(_T_2073, UInt<1>(0h0))
when _T_2076 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189
assert(clock, _T_2073, UInt<1>(0h1), "") : assert_189
node _T_2077 = eq(io.in.c.bits.source, source_3)
node _T_2078 = asUInt(reset)
node _T_2079 = eq(_T_2078, UInt<1>(0h0))
when _T_2079 :
node _T_2080 = eq(_T_2077, UInt<1>(0h0))
when _T_2080 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190
assert(clock, _T_2077, UInt<1>(0h1), "") : assert_190
node _T_2081 = eq(io.in.c.bits.address, address_2)
node _T_2082 = asUInt(reset)
node _T_2083 = eq(_T_2082, UInt<1>(0h0))
when _T_2083 :
node _T_2084 = eq(_T_2081, UInt<1>(0h0))
when _T_2084 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191
assert(clock, _T_2081, UInt<1>(0h1), "") : assert_191
node _T_2085 = and(io.in.c.ready, io.in.c.valid)
node _T_2086 = and(_T_2085, c_first)
when _T_2086 :
connect opcode_3, io.in.c.bits.opcode
connect param_3, io.in.c.bits.param
connect size_3, io.in.c.bits.size
connect source_3, io.in.c.bits.source
connect address_2, io.in.c.bits.address
regreset inflight : UInt<43>, clock, reset, UInt<43>(0h0)
regreset inflight_opcodes : UInt<172>, clock, reset, UInt<172>(0h0)
regreset inflight_sizes : UInt<172>, clock, reset, UInt<172>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<2>, clock, reset, UInt<2>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<2>, clock, reset, UInt<2>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<43>
connect a_set, UInt<43>(0h0)
wire a_set_wo_ready : UInt<43>
connect a_set_wo_ready, UInt<43>(0h0)
wire a_opcodes_set : UInt<172>
connect a_opcodes_set, UInt<172>(0h0)
wire a_sizes_set : UInt<172>
connect a_sizes_set, UInt<172>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_2087 = and(io.in.a.valid, a_first_1)
node _T_2088 = and(_T_2087, UInt<1>(0h1))
when _T_2088 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_2089 = and(io.in.a.ready, io.in.a.valid)
node _T_2090 = and(_T_2089, a_first_1)
node _T_2091 = and(_T_2090, UInt<1>(0h1))
when _T_2091 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_2092 = dshr(inflight, io.in.a.bits.source)
node _T_2093 = bits(_T_2092, 0, 0)
node _T_2094 = eq(_T_2093, UInt<1>(0h0))
node _T_2095 = asUInt(reset)
node _T_2096 = eq(_T_2095, UInt<1>(0h0))
when _T_2096 :
node _T_2097 = eq(_T_2094, UInt<1>(0h0))
when _T_2097 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192
assert(clock, _T_2094, UInt<1>(0h1), "") : assert_192
wire d_clr : UInt<43>
connect d_clr, UInt<43>(0h0)
wire d_clr_wo_ready : UInt<43>
connect d_clr_wo_ready, UInt<43>(0h0)
wire d_opcodes_clr : UInt<172>
connect d_opcodes_clr, UInt<172>(0h0)
wire d_sizes_clr : UInt<172>
connect d_sizes_clr, UInt<172>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2098 = and(io.in.d.valid, d_first_1)
node _T_2099 = and(_T_2098, UInt<1>(0h1))
node _T_2100 = eq(d_release_ack, UInt<1>(0h0))
node _T_2101 = and(_T_2099, _T_2100)
when _T_2101 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_2102 = and(io.in.d.ready, io.in.d.valid)
node _T_2103 = and(_T_2102, d_first_1)
node _T_2104 = and(_T_2103, UInt<1>(0h1))
node _T_2105 = eq(d_release_ack, UInt<1>(0h0))
node _T_2106 = and(_T_2104, _T_2105)
when _T_2106 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_2107 = and(io.in.d.valid, d_first_1)
node _T_2108 = and(_T_2107, UInt<1>(0h1))
node _T_2109 = eq(d_release_ack, UInt<1>(0h0))
node _T_2110 = and(_T_2108, _T_2109)
when _T_2110 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_2111 = dshr(inflight, io.in.d.bits.source)
node _T_2112 = bits(_T_2111, 0, 0)
node _T_2113 = or(_T_2112, same_cycle_resp)
node _T_2114 = asUInt(reset)
node _T_2115 = eq(_T_2114, UInt<1>(0h0))
when _T_2115 :
node _T_2116 = eq(_T_2113, UInt<1>(0h0))
when _T_2116 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193
assert(clock, _T_2113, UInt<1>(0h1), "") : assert_193
when same_cycle_resp :
node _T_2117 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_2118 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_2119 = or(_T_2117, _T_2118)
node _T_2120 = asUInt(reset)
node _T_2121 = eq(_T_2120, UInt<1>(0h0))
when _T_2121 :
node _T_2122 = eq(_T_2119, UInt<1>(0h0))
when _T_2122 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194
assert(clock, _T_2119, UInt<1>(0h1), "") : assert_194
node _T_2123 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_2124 = asUInt(reset)
node _T_2125 = eq(_T_2124, UInt<1>(0h0))
when _T_2125 :
node _T_2126 = eq(_T_2123, UInt<1>(0h0))
when _T_2126 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195
assert(clock, _T_2123, UInt<1>(0h1), "") : assert_195
else :
node _T_2127 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_2128 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_2129 = or(_T_2127, _T_2128)
node _T_2130 = asUInt(reset)
node _T_2131 = eq(_T_2130, UInt<1>(0h0))
when _T_2131 :
node _T_2132 = eq(_T_2129, UInt<1>(0h0))
when _T_2132 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196
assert(clock, _T_2129, UInt<1>(0h1), "") : assert_196
node _T_2133 = eq(io.in.d.bits.size, a_size_lookup)
node _T_2134 = asUInt(reset)
node _T_2135 = eq(_T_2134, UInt<1>(0h0))
when _T_2135 :
node _T_2136 = eq(_T_2133, UInt<1>(0h0))
when _T_2136 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197
assert(clock, _T_2133, UInt<1>(0h1), "") : assert_197
node _T_2137 = and(io.in.d.valid, d_first_1)
node _T_2138 = and(_T_2137, a_first_1)
node _T_2139 = and(_T_2138, io.in.a.valid)
node _T_2140 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_2141 = and(_T_2139, _T_2140)
node _T_2142 = eq(d_release_ack, UInt<1>(0h0))
node _T_2143 = and(_T_2141, _T_2142)
when _T_2143 :
node _T_2144 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_2145 = or(_T_2144, io.in.a.ready)
node _T_2146 = asUInt(reset)
node _T_2147 = eq(_T_2146, UInt<1>(0h0))
when _T_2147 :
node _T_2148 = eq(_T_2145, UInt<1>(0h0))
when _T_2148 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198
assert(clock, _T_2145, UInt<1>(0h1), "") : assert_198
node _T_2149 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_2150 = orr(a_set_wo_ready)
node _T_2151 = eq(_T_2150, UInt<1>(0h0))
node _T_2152 = or(_T_2149, _T_2151)
node _T_2153 = asUInt(reset)
node _T_2154 = eq(_T_2153, UInt<1>(0h0))
when _T_2154 :
node _T_2155 = eq(_T_2152, UInt<1>(0h0))
when _T_2155 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199
assert(clock, _T_2152, UInt<1>(0h1), "") : assert_199
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_118
node _T_2156 = orr(inflight)
node _T_2157 = eq(_T_2156, UInt<1>(0h0))
node _T_2158 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_2159 = or(_T_2157, _T_2158)
node _T_2160 = lt(watchdog, plusarg_reader.out)
node _T_2161 = or(_T_2159, _T_2160)
node _T_2162 = asUInt(reset)
node _T_2163 = eq(_T_2162, UInt<1>(0h0))
when _T_2163 :
node _T_2164 = eq(_T_2161, UInt<1>(0h0))
when _T_2164 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200
assert(clock, _T_2161, UInt<1>(0h1), "") : assert_200
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_2165 = and(io.in.a.ready, io.in.a.valid)
node _T_2166 = and(io.in.d.ready, io.in.d.valid)
node _T_2167 = or(_T_2165, _T_2166)
when _T_2167 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<43>, clock, reset, UInt<43>(0h0)
regreset inflight_opcodes_1 : UInt<172>, clock, reset, UInt<172>(0h0)
regreset inflight_sizes_1 : UInt<172>, clock, reset, UInt<172>(0h0)
node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.c.bits.size)
node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 5, 0)
node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4)
node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 4)
node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0))
regreset c_first_counter_1 : UInt<2>, clock, reset, UInt<2>(0h0)
node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1))
node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1)
node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0))
node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1))
node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0))
node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3)
node c_first_done_1 = and(c_first_last_1, _c_first_T_1)
node _c_first_count_T_1 = not(c_first_counter1_1)
node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1)
when _c_first_T_1 :
node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1)
connect c_first_counter_1, _c_first_counter_T_1
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<2>, clock, reset, UInt<2>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<43>
connect c_set, UInt<43>(0h0)
wire c_set_wo_ready : UInt<43>
connect c_set_wo_ready, UInt<43>(0h0)
wire c_opcodes_set : UInt<172>
connect c_opcodes_set, UInt<172>(0h0)
wire c_sizes_set : UInt<172>
connect c_sizes_set, UInt<172>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
node _T_2168 = and(io.in.c.valid, c_first_1)
node _T_2169 = bits(io.in.c.bits.opcode, 2, 2)
node _T_2170 = bits(io.in.c.bits.opcode, 1, 1)
node _T_2171 = and(_T_2169, _T_2170)
node _T_2172 = and(_T_2168, _T_2171)
when _T_2172 :
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
node _T_2173 = and(io.in.c.ready, io.in.c.valid)
node _T_2174 = and(_T_2173, c_first_1)
node _T_2175 = bits(io.in.c.bits.opcode, 2, 2)
node _T_2176 = bits(io.in.c.bits.opcode, 1, 1)
node _T_2177 = and(_T_2175, _T_2176)
node _T_2178 = and(_T_2174, _T_2177)
when _T_2178 :
node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set, _c_set_T
node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
node _T_2179 = dshr(inflight_1, io.in.c.bits.source)
node _T_2180 = bits(_T_2179, 0, 0)
node _T_2181 = eq(_T_2180, UInt<1>(0h0))
node _T_2182 = asUInt(reset)
node _T_2183 = eq(_T_2182, UInt<1>(0h0))
when _T_2183 :
node _T_2184 = eq(_T_2181, UInt<1>(0h0))
when _T_2184 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201
assert(clock, _T_2181, UInt<1>(0h1), "") : assert_201
node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4))
node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<43>
connect d_clr_1, UInt<43>(0h0)
wire d_clr_wo_ready_1 : UInt<43>
connect d_clr_wo_ready_1, UInt<43>(0h0)
wire d_opcodes_clr_1 : UInt<172>
connect d_opcodes_clr_1, UInt<172>(0h0)
wire d_sizes_clr_1 : UInt<172>
connect d_sizes_clr_1, UInt<172>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2185 = and(io.in.d.valid, d_first_2)
node _T_2186 = and(_T_2185, UInt<1>(0h1))
node _T_2187 = and(_T_2186, d_release_ack_1)
when _T_2187 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_2188 = and(io.in.d.ready, io.in.d.valid)
node _T_2189 = and(_T_2188, d_first_2)
node _T_2190 = and(_T_2189, UInt<1>(0h1))
node _T_2191 = and(_T_2190, d_release_ack_1)
when _T_2191 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_2192 = and(io.in.d.valid, d_first_2)
node _T_2193 = and(_T_2192, UInt<1>(0h1))
node _T_2194 = and(_T_2193, d_release_ack_1)
when _T_2194 :
node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1)
node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_2195 = dshr(inflight_1, io.in.d.bits.source)
node _T_2196 = bits(_T_2195, 0, 0)
node _T_2197 = or(_T_2196, same_cycle_resp_1)
node _T_2198 = asUInt(reset)
node _T_2199 = eq(_T_2198, UInt<1>(0h0))
when _T_2199 :
node _T_2200 = eq(_T_2197, UInt<1>(0h0))
when _T_2200 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202
assert(clock, _T_2197, UInt<1>(0h1), "") : assert_202
when same_cycle_resp_1 :
node _T_2201 = eq(io.in.d.bits.size, io.in.c.bits.size)
node _T_2202 = asUInt(reset)
node _T_2203 = eq(_T_2202, UInt<1>(0h0))
when _T_2203 :
node _T_2204 = eq(_T_2201, UInt<1>(0h0))
when _T_2204 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203
assert(clock, _T_2201, UInt<1>(0h1), "") : assert_203
else :
node _T_2205 = eq(io.in.d.bits.size, c_size_lookup)
node _T_2206 = asUInt(reset)
node _T_2207 = eq(_T_2206, UInt<1>(0h0))
when _T_2207 :
node _T_2208 = eq(_T_2205, UInt<1>(0h0))
when _T_2208 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204
assert(clock, _T_2205, UInt<1>(0h1), "") : assert_204
node _T_2209 = and(io.in.d.valid, d_first_2)
node _T_2210 = and(_T_2209, c_first_1)
node _T_2211 = and(_T_2210, io.in.c.valid)
node _T_2212 = eq(io.in.c.bits.source, io.in.d.bits.source)
node _T_2213 = and(_T_2211, _T_2212)
node _T_2214 = and(_T_2213, d_release_ack_1)
node _T_2215 = eq(c_probe_ack, UInt<1>(0h0))
node _T_2216 = and(_T_2214, _T_2215)
when _T_2216 :
node _T_2217 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_2218 = or(_T_2217, io.in.c.ready)
node _T_2219 = asUInt(reset)
node _T_2220 = eq(_T_2219, UInt<1>(0h0))
when _T_2220 :
node _T_2221 = eq(_T_2218, UInt<1>(0h0))
when _T_2221 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205
assert(clock, _T_2218, UInt<1>(0h1), "") : assert_205
node _T_2222 = orr(c_set_wo_ready)
when _T_2222 :
node _T_2223 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_2224 = asUInt(reset)
node _T_2225 = eq(_T_2224, UInt<1>(0h0))
when _T_2225 :
node _T_2226 = eq(_T_2223, UInt<1>(0h0))
when _T_2226 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206
assert(clock, _T_2223, UInt<1>(0h1), "") : assert_206
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_119
node _T_2227 = orr(inflight_1)
node _T_2228 = eq(_T_2227, UInt<1>(0h0))
node _T_2229 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_2230 = or(_T_2228, _T_2229)
node _T_2231 = lt(watchdog_1, plusarg_reader_1.out)
node _T_2232 = or(_T_2230, _T_2231)
node _T_2233 = asUInt(reset)
node _T_2234 = eq(_T_2233, UInt<1>(0h0))
when _T_2234 :
node _T_2235 = eq(_T_2232, UInt<1>(0h0))
when _T_2235 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207
assert(clock, _T_2232, UInt<1>(0h1), "") : assert_207
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
node _T_2236 = and(io.in.c.ready, io.in.c.valid)
node _T_2237 = and(io.in.d.ready, io.in.d.valid)
node _T_2238 = or(_T_2236, _T_2237)
when _T_2238 :
connect watchdog_1, UInt<1>(0h0)
regreset inflight_2 : UInt<12>, clock, reset, UInt<12>(0h0)
node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_9 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 5, 0)
node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10)
node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 4)
node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0))
regreset d_first_counter_3 : UInt<2>, clock, reset, UInt<2>(0h0)
node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1))
node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1)
node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0))
node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1))
node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0))
node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7)
node d_first_done_3 = and(d_first_last_3, _d_first_T_3)
node _d_first_count_T_3 = not(d_first_counter1_3)
node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3)
when _d_first_T_3 :
node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3)
connect d_first_counter_3, _d_first_counter_T_3
wire d_set : UInt<12>
connect d_set, UInt<12>(0h0)
node _T_2239 = and(io.in.d.ready, io.in.d.valid)
node _T_2240 = and(_T_2239, d_first_3)
node _T_2241 = bits(io.in.d.bits.opcode, 2, 2)
node _T_2242 = bits(io.in.d.bits.opcode, 1, 1)
node _T_2243 = eq(_T_2242, UInt<1>(0h0))
node _T_2244 = and(_T_2241, _T_2243)
node _T_2245 = and(_T_2240, _T_2244)
when _T_2245 :
node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink)
connect d_set, _d_set_T
node _T_2246 = dshr(inflight_2, io.in.d.bits.sink)
node _T_2247 = bits(_T_2246, 0, 0)
node _T_2248 = eq(_T_2247, UInt<1>(0h0))
node _T_2249 = asUInt(reset)
node _T_2250 = eq(_T_2249, UInt<1>(0h0))
when _T_2250 :
node _T_2251 = eq(_T_2248, UInt<1>(0h0))
when _T_2251 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208
assert(clock, _T_2248, UInt<1>(0h1), "") : assert_208
wire e_clr : UInt<12>
connect e_clr, UInt<12>(0h0)
node _T_2252 = and(io.in.e.ready, io.in.e.valid)
node _T_2253 = and(_T_2252, UInt<1>(0h1))
node _T_2254 = and(_T_2253, UInt<1>(0h1))
when _T_2254 :
node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink)
connect e_clr, _e_clr_T
node _T_2255 = or(d_set, inflight_2)
node _T_2256 = dshr(_T_2255, io.in.e.bits.sink)
node _T_2257 = bits(_T_2256, 0, 0)
node _T_2258 = asUInt(reset)
node _T_2259 = eq(_T_2258, UInt<1>(0h0))
when _T_2259 :
node _T_2260 = eq(_T_2257, UInt<1>(0h0))
when _T_2260 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209
assert(clock, _T_2257, UInt<1>(0h1), "") : assert_209
node _inflight_T_6 = or(inflight_2, d_set)
node _inflight_T_7 = not(e_clr)
node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7)
connect inflight_2, _inflight_T_8
extmodule plusarg_reader_120 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_121 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLMonitor_59( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_b_ready, // @[Monitor.scala:20:14]
input io_in_b_valid, // @[Monitor.scala:20:14]
input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14]
input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14]
input io_in_c_ready, // @[Monitor.scala:20:14]
input io_in_c_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_c_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14]
input [127:0] io_in_c_bits_data, // @[Monitor.scala:20:14]
input io_in_c_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_e_valid, // @[Monitor.scala:20:14]
input [3:0] io_in_e_bits_sink // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7]
wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7]
wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7]
wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7]
wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7]
wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7]
wire [5:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7]
wire [127:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7]
wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [5:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7]
wire [3:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7]
wire io_in_e_ready = 1'h1; // @[Monitor.scala:36:7]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_42 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_48 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_50 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_54 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_60 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_66 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:57:20]
wire mask_sub_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21]
wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26]
wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_4_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_5_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_6_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_7_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_size_1 = 1'h1; // @[Misc.scala:209:26]
wire mask_acc_16 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_17 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_18 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_19 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_20 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_21 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_22 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_23 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_24 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_25 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_26 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_27 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_28 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_29 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_30 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_31 = 1'h1; // @[Misc.scala:215:29]
wire _legal_source_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_T_31 = 1'h1; // @[Parameters.scala:46:9]
wire _legal_source_WIRE_6 = 1'h1; // @[Parameters.scala:1138:31]
wire legal_source = 1'h1; // @[Monitor.scala:168:113]
wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_89 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_93 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_95 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_99 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_101 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_105 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_107 = 1'h1; // @[Parameters.scala:57:20]
wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37]
wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire b_first_last = 1'h1; // @[Edges.scala:232:33]
wire [5:0] io_in_b_bits_source = 6'h28; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_55 = 6'h28; // @[Parameters.scala:52:29]
wire [5:0] _uncommonBits_T_56 = 6'h28; // @[Parameters.scala:52:29]
wire [5:0] _uncommonBits_T_57 = 6'h28; // @[Parameters.scala:52:29]
wire [5:0] _uncommonBits_T_58 = 6'h28; // @[Parameters.scala:52:29]
wire [5:0] _uncommonBits_T_59 = 6'h28; // @[Parameters.scala:52:29]
wire [5:0] _legal_source_uncommonBits_T = 6'h28; // @[Parameters.scala:52:29]
wire [5:0] _legal_source_uncommonBits_T_1 = 6'h28; // @[Parameters.scala:52:29]
wire [5:0] _legal_source_uncommonBits_T_2 = 6'h28; // @[Parameters.scala:52:29]
wire [5:0] _legal_source_uncommonBits_T_3 = 6'h28; // @[Parameters.scala:52:29]
wire [5:0] _legal_source_uncommonBits_T_4 = 6'h28; // @[Parameters.scala:52:29]
wire [5:0] _legal_source_T_39 = 6'h28; // @[Mux.scala:30:73]
wire [5:0] _legal_source_T_46 = 6'h28; // @[Mux.scala:30:73]
wire [5:0] _legal_source_T_47 = 6'h28; // @[Mux.scala:30:73]
wire [5:0] _legal_source_WIRE_1 = 6'h28; // @[Mux.scala:30:73]
wire [5:0] _uncommonBits_T_60 = 6'h28; // @[Parameters.scala:52:29]
wire [5:0] _uncommonBits_T_61 = 6'h28; // @[Parameters.scala:52:29]
wire [5:0] _uncommonBits_T_62 = 6'h28; // @[Parameters.scala:52:29]
wire [5:0] _uncommonBits_T_63 = 6'h28; // @[Parameters.scala:52:29]
wire [5:0] _uncommonBits_T_64 = 6'h28; // @[Parameters.scala:52:29]
wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7]
wire [2:0] io_in_b_bits_size = 3'h6; // @[Monitor.scala:36:7]
wire [15:0] io_in_b_bits_mask = 16'hFFFF; // @[Monitor.scala:36:7]
wire [15:0] mask_1 = 16'hFFFF; // @[Misc.scala:222:10]
wire [127:0] io_in_b_bits_data = 128'h0; // @[Monitor.scala:36:7]
wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire mask_sub_sub_sub_size_1 = 1'h0; // @[Misc.scala:209:26]
wire _mask_sub_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38]
wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26]
wire _mask_sub_acc_T_8 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_9 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_10 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_11 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_12 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_13 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_14 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_15 = 1'h0; // @[Misc.scala:215:38]
wire _legal_source_T = 1'h0; // @[Parameters.scala:46:9]
wire _legal_source_T_2 = 1'h0; // @[Parameters.scala:54:32]
wire _legal_source_T_4 = 1'h0; // @[Parameters.scala:54:67]
wire _legal_source_T_6 = 1'h0; // @[Parameters.scala:56:48]
wire _legal_source_T_8 = 1'h0; // @[Parameters.scala:54:32]
wire _legal_source_T_10 = 1'h0; // @[Parameters.scala:54:67]
wire _legal_source_T_12 = 1'h0; // @[Parameters.scala:56:48]
wire _legal_source_T_14 = 1'h0; // @[Parameters.scala:54:32]
wire _legal_source_T_16 = 1'h0; // @[Parameters.scala:54:67]
wire _legal_source_T_18 = 1'h0; // @[Parameters.scala:56:48]
wire _legal_source_T_20 = 1'h0; // @[Parameters.scala:54:32]
wire _legal_source_T_22 = 1'h0; // @[Parameters.scala:54:67]
wire _legal_source_T_24 = 1'h0; // @[Parameters.scala:56:48]
wire _legal_source_T_26 = 1'h0; // @[Parameters.scala:54:32]
wire _legal_source_T_28 = 1'h0; // @[Parameters.scala:54:67]
wire _legal_source_T_30 = 1'h0; // @[Parameters.scala:56:48]
wire _legal_source_T_32 = 1'h0; // @[Parameters.scala:46:9]
wire _legal_source_WIRE_0 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_1_0 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_2 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_3 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_4 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_5 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_7 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_T_34 = 1'h0; // @[Mux.scala:30:73]
wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12]
wire [3:0] _mask_sizeOH_T_5 = 4'h4; // @[OneHot.scala:65:27]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] _legal_source_T_25 = 3'h5; // @[Parameters.scala:54:10]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] uncommonBits_59 = 3'h0; // @[Parameters.scala:52:56]
wire [2:0] legal_source_uncommonBits_4 = 3'h0; // @[Parameters.scala:52:56]
wire [2:0] _legal_source_T_35 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] uncommonBits_64 = 3'h0; // @[Parameters.scala:52:56]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [1:0] uncommonBits_55 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_56 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_57 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_58 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] legal_source_uncommonBits = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] legal_source_uncommonBits_1 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] legal_source_uncommonBits_2 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] legal_source_uncommonBits_3 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_60 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_61 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_62 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_63 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] b_first_beats1 = 2'h0; // @[Edges.scala:221:14]
wire [1:0] b_first_count = 2'h0; // @[Edges.scala:234:25]
wire [1:0] mask_lo_lo_lo_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_lo_lo_hi_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_lo_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_hi_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_lo_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_hi_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_lo_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_hi_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] b_first_beats1_decode = 2'h3; // @[Edges.scala:220:59]
wire [5:0] is_aligned_mask_1 = 6'h3F; // @[package.scala:243:46]
wire [5:0] _b_first_beats1_decode_T_2 = 6'h3F; // @[package.scala:243:46]
wire [5:0] _is_aligned_mask_T_3 = 6'h0; // @[package.scala:243:76]
wire [5:0] _legal_source_T_38 = 6'h0; // @[Mux.scala:30:73]
wire [5:0] _legal_source_T_40 = 6'h0; // @[Mux.scala:30:73]
wire [5:0] _legal_source_T_45 = 6'h0; // @[Mux.scala:30:73]
wire [5:0] _b_first_beats1_decode_T_1 = 6'h0; // @[package.scala:243:76]
wire [12:0] _is_aligned_mask_T_2 = 13'hFC0; // @[package.scala:243:71]
wire [12:0] _b_first_beats1_decode_T = 13'hFC0; // @[package.scala:243:71]
wire [4:0] _legal_source_T_33 = 5'h0; // @[Mux.scala:30:73]
wire [4:0] _legal_source_T_41 = 5'h0; // @[Mux.scala:30:73]
wire [4:0] _legal_source_T_42 = 5'h0; // @[Mux.scala:30:73]
wire [4:0] _legal_source_T_43 = 5'h0; // @[Mux.scala:30:73]
wire [4:0] _legal_source_T_44 = 5'h0; // @[Mux.scala:30:73]
wire [3:0] _legal_source_T_36 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _legal_source_T_37 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _legal_source_T_1 = 4'hA; // @[Parameters.scala:54:10]
wire [3:0] _legal_source_T_7 = 4'hA; // @[Parameters.scala:54:10]
wire [3:0] _legal_source_T_13 = 4'hA; // @[Parameters.scala:54:10]
wire [3:0] _legal_source_T_19 = 4'hA; // @[Parameters.scala:54:10]
wire [7:0] mask_lo_1 = 8'hFF; // @[Misc.scala:222:10]
wire [7:0] mask_hi_1 = 8'hFF; // @[Misc.scala:222:10]
wire [3:0] mask_lo_lo_1 = 4'hF; // @[Misc.scala:222:10]
wire [3:0] mask_lo_hi_1 = 4'hF; // @[Misc.scala:222:10]
wire [3:0] mask_hi_lo_1 = 4'hF; // @[Misc.scala:222:10]
wire [3:0] mask_hi_hi_1 = 4'hF; // @[Misc.scala:222:10]
wire [3:0] mask_sizeOH_1 = 4'h5; // @[Misc.scala:202:81]
wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_3 = 4'h6; // @[Misc.scala:202:34]
wire [5:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_10 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_11 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_12 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_13 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_14 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_65 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_66 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_67 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_68 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_69 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_70 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_71 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_72 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_73 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_74 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_75 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_76 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_77 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_78 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_79 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_80 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_81 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_82 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_83 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_84 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_85 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_86 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_87 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_88 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_89 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 6'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_1 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_7 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_13 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_19 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 4'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 4'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_25 = io_in_a_bits_source_0[5:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_26 = _source_ok_T_25 == 3'h4; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire _source_ok_T_31 = io_in_a_bits_source_0 == 6'h28; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31]
wire _source_ok_T_32 = io_in_a_bits_source_0 == 6'h2A; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31]
wire _source_ok_T_33 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_34 = _source_ok_T_33 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_37 = _source_ok_T_36 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_38 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [3:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}]
wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_sub_0_1 = io_in_a_bits_size_0[2]; // @[Misc.scala:206:21]
wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26]
wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}]
wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}]
wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}]
wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}]
wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}]
wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}]
wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}]
wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_9 = _uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_14 = _uncommonBits_T_14[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_24 = _uncommonBits_T_24[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_29 = _uncommonBits_T_29[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_44 = _uncommonBits_T_44[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_49 = _uncommonBits_T_49[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_39 = io_in_d_bits_source_0 == 6'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_39; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_40 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_46 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_52 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_58 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_41 = _source_ok_T_40 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_43 = _source_ok_T_41; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_45; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_47 = _source_ok_T_46 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_49 = _source_ok_T_47; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_51 = _source_ok_T_49; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_51; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_53 = _source_ok_T_52 == 4'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_55 = _source_ok_T_53; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_57; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_59 = _source_ok_T_58 == 4'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_61 = _source_ok_T_59; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_63; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_64 = io_in_d_bits_source_0[5:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_65 = _source_ok_T_64 == 3'h4; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_67 = _source_ok_T_65; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_5 = _source_ok_T_69; // @[Parameters.scala:1138:31]
wire _source_ok_T_70 = io_in_d_bits_source_0 == 6'h28; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_70; // @[Parameters.scala:1138:31]
wire _source_ok_T_71 = io_in_d_bits_source_0 == 6'h2A; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_71; // @[Parameters.scala:1138:31]
wire _source_ok_T_72 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_73 = _source_ok_T_72 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_74 = _source_ok_T_73 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_75 = _source_ok_T_74 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_76 = _source_ok_T_75 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_77 = _source_ok_T_76 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_77 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire sink_ok = io_in_d_bits_sink_0[3:2] != 2'h3; // @[Monitor.scala:36:7, :309:31]
wire [27:0] _GEN_0 = io_in_b_bits_address_0[27:0] ^ 28'h8000040; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T = {io_in_b_bits_address_0[31:28], _GEN_0}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFF01C0; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46]
wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_5 = io_in_b_bits_address_0 ^ 32'h80000040; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1F00001C0; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46]
wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40]
wire address_ok = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64]
wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7]
wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}]
wire mask_sub_sub_sub_bit_1 = io_in_b_bits_address_0[3]; // @[Misc.scala:210:26]
wire mask_sub_sub_sub_1_2_1 = mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_sub_nbit_1 = ~mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_sub_0_2_1 = mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_4 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38]
wire mask_sub_sub_1_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_5 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38]
wire mask_sub_sub_2_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_6 = mask_sub_sub_2_2_1; // @[Misc.scala:214:27, :215:38]
wire mask_sub_sub_3_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_7 = mask_sub_sub_3_2_1; // @[Misc.scala:214:27, :215:38]
wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_4_2_1 = mask_sub_sub_2_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_5_2_1 = mask_sub_sub_2_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_6_2_1 = mask_sub_sub_3_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_7_2_1 = mask_sub_sub_3_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_eq_16 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_16 = mask_eq_16; // @[Misc.scala:214:27, :215:38]
wire mask_eq_17 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_17 = mask_eq_17; // @[Misc.scala:214:27, :215:38]
wire mask_eq_18 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_18 = mask_eq_18; // @[Misc.scala:214:27, :215:38]
wire mask_eq_19 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_19 = mask_eq_19; // @[Misc.scala:214:27, :215:38]
wire mask_eq_20 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_20 = mask_eq_20; // @[Misc.scala:214:27, :215:38]
wire mask_eq_21 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_21 = mask_eq_21; // @[Misc.scala:214:27, :215:38]
wire mask_eq_22 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_22 = mask_eq_22; // @[Misc.scala:214:27, :215:38]
wire mask_eq_23 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_23 = mask_eq_23; // @[Misc.scala:214:27, :215:38]
wire mask_eq_24 = mask_sub_4_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_24 = mask_eq_24; // @[Misc.scala:214:27, :215:38]
wire mask_eq_25 = mask_sub_4_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_25 = mask_eq_25; // @[Misc.scala:214:27, :215:38]
wire mask_eq_26 = mask_sub_5_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_26 = mask_eq_26; // @[Misc.scala:214:27, :215:38]
wire mask_eq_27 = mask_sub_5_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_27 = mask_eq_27; // @[Misc.scala:214:27, :215:38]
wire mask_eq_28 = mask_sub_6_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_28 = mask_eq_28; // @[Misc.scala:214:27, :215:38]
wire mask_eq_29 = mask_sub_6_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_29 = mask_eq_29; // @[Misc.scala:214:27, :215:38]
wire mask_eq_30 = mask_sub_7_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_30 = mask_eq_30; // @[Misc.scala:214:27, :215:38]
wire mask_eq_31 = mask_sub_7_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_31 = mask_eq_31; // @[Misc.scala:214:27, :215:38]
wire _source_ok_T_78 = io_in_c_bits_source_0 == 6'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_0 = _source_ok_T_78; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_79 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_85 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_91 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_97 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_80 = _source_ok_T_79 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2_1 = _source_ok_T_84; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_86 = _source_ok_T_85 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_90 = _source_ok_T_88; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2_2 = _source_ok_T_90; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_92 = _source_ok_T_91 == 4'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_94 = _source_ok_T_92; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_96 = _source_ok_T_94; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2_3 = _source_ok_T_96; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_98 = _source_ok_T_97 == 4'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_100 = _source_ok_T_98; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_102 = _source_ok_T_100; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2_4 = _source_ok_T_102; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_14 = _source_ok_uncommonBits_T_14[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_103 = io_in_c_bits_source_0[5:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_104 = _source_ok_T_103 == 3'h4; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_106 = _source_ok_T_104; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_108 = _source_ok_T_106; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2_5 = _source_ok_T_108; // @[Parameters.scala:1138:31]
wire _source_ok_T_109 = io_in_c_bits_source_0 == 6'h28; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_6 = _source_ok_T_109; // @[Parameters.scala:1138:31]
wire _source_ok_T_110 = io_in_c_bits_source_0 == 6'h2A; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_7 = _source_ok_T_110; // @[Parameters.scala:1138:31]
wire _source_ok_T_111 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_112 = _source_ok_T_111 | _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_113 = _source_ok_T_112 | _source_ok_WIRE_2_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_114 = _source_ok_T_113 | _source_ok_WIRE_2_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_115 = _source_ok_T_114 | _source_ok_WIRE_2_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_116 = _source_ok_T_115 | _source_ok_WIRE_2_6; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_2 = _source_ok_T_116 | _source_ok_WIRE_2_7; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN_1 = 13'h3F << io_in_c_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T_4; // @[package.scala:243:71]
assign _is_aligned_mask_T_4 = _GEN_1; // @[package.scala:243:71]
wire [12:0] _c_first_beats1_decode_T; // @[package.scala:243:71]
assign _c_first_beats1_decode_T = _GEN_1; // @[package.scala:243:71]
wire [12:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _c_first_beats1_decode_T_3 = _GEN_1; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T_2 = {26'h0, io_in_c_bits_address_0[5:0] & is_aligned_mask_2}; // @[package.scala:243:46]
wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}]
wire [27:0] _GEN_2 = io_in_c_bits_address_0[27:0] ^ 28'h8000040; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_10 = {io_in_c_bits_address_0[31:28], _GEN_2}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFF01C0; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46]
wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_0 = _address_ok_T_14; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_15 = io_in_c_bits_address_0 ^ 32'h80000040; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1F00001C0; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46]
wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_1 = _address_ok_T_19; // @[Parameters.scala:612:40]
wire address_ok_1 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64]
wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_67 = _uncommonBits_T_67[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_68 = _uncommonBits_T_68[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_69 = _uncommonBits_T_69[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_72 = _uncommonBits_T_72[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_73 = _uncommonBits_T_73[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_74 = _uncommonBits_T_74[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_75 = _uncommonBits_T_75[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_76 = _uncommonBits_T_76[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_77 = _uncommonBits_T_77[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_78 = _uncommonBits_T_78[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_79 = _uncommonBits_T_79[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_80 = _uncommonBits_T_80[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_81 = _uncommonBits_T_81[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_82 = _uncommonBits_T_82[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_83 = _uncommonBits_T_83[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_84 = _uncommonBits_T_84[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_85 = _uncommonBits_T_85[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_86 = _uncommonBits_T_86[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_87 = _uncommonBits_T_87[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_88 = _uncommonBits_T_88[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_89 = _uncommonBits_T_89[2:0]; // @[Parameters.scala:52:{29,56}]
wire sink_ok_1 = io_in_e_bits_sink_0[3:2] != 2'h3; // @[Monitor.scala:36:7, :367:31]
wire _T_2165 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_2165; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_2165; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [1:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:4]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [1:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 2'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [1:0] a_first_counter; // @[Edges.scala:229:27]
wire [2:0] _a_first_counter1_T = {1'h0, a_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] a_first_counter1 = _a_first_counter1_T[1:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [1:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [1:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [5:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_2239 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_2239; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_2239; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_2239; // @[Decoupled.scala:51:35]
wire _d_first_T_3; // @[Decoupled.scala:51:35]
assign _d_first_T_3 = _T_2239; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_3 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_3; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_3; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_3; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_9 = _GEN_3; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [1:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:4]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [1:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [1:0] d_first_counter; // @[Edges.scala:229:27]
wire [2:0] _d_first_counter1_T = {1'h0, d_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] d_first_counter1 = _d_first_counter1_T[1:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [1:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [5:0] source_1; // @[Monitor.scala:541:22]
reg [3:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35]
wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35]
reg [1:0] b_first_counter; // @[Edges.scala:229:27]
wire [2:0] _b_first_counter1_T = {1'h0, b_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] b_first_counter1 = _b_first_counter1_T[1:0]; // @[Edges.scala:230:28]
wire b_first = b_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _b_first_last_T = b_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [1:0] _b_first_counter_T = b_first ? 2'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [1:0] param_2; // @[Monitor.scala:411:22]
reg [31:0] address_1; // @[Monitor.scala:414:22]
wire _T_2236 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35]
wire _c_first_T; // @[Decoupled.scala:51:35]
assign _c_first_T = _T_2236; // @[Decoupled.scala:51:35]
wire _c_first_T_1; // @[Decoupled.scala:51:35]
assign _c_first_T_1 = _T_2236; // @[Decoupled.scala:51:35]
wire [5:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [1:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[5:4]; // @[package.scala:243:46]
wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [1:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 2'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [1:0] c_first_counter; // @[Edges.scala:229:27]
wire [2:0] _c_first_counter1_T = {1'h0, c_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] c_first_counter1 = _c_first_counter1_T[1:0]; // @[Edges.scala:230:28]
wire c_first = c_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _c_first_last_T = c_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _c_first_last_T_1 = c_first_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35]
wire [1:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [1:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_3; // @[Monitor.scala:515:22]
reg [2:0] param_3; // @[Monitor.scala:516:22]
reg [2:0] size_3; // @[Monitor.scala:517:22]
reg [5:0] source_3; // @[Monitor.scala:518:22]
reg [31:0] address_2; // @[Monitor.scala:519:22]
reg [42:0] inflight; // @[Monitor.scala:614:27]
reg [171:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [171:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [1:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:4]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [1:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 2'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [1:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [2:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] a_first_counter1_1 = _a_first_counter1_T_1[1:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [1:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [1:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [1:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:4]; // @[package.scala:243:46]
wire [1:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [1:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [2:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] d_first_counter1_1 = _d_first_counter1_T_1[1:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [1:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [42:0] a_set; // @[Monitor.scala:626:34]
wire [42:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [171:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [171:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [8:0] _GEN_4 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [8:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_4; // @[Monitor.scala:637:69]
wire [8:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :641:65]
wire [8:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_4; // @[Monitor.scala:637:69, :680:101]
wire [8:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_4; // @[Monitor.scala:637:69, :681:99]
wire [8:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :749:69]
wire [8:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :750:67]
wire [8:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_4; // @[Monitor.scala:637:69, :790:101]
wire [8:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_4; // @[Monitor.scala:637:69, :791:99]
wire [171:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [171:0] _a_opcode_lookup_T_6 = {168'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [171:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[171:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [171:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [171:0] _a_size_lookup_T_6 = {168'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [171:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[171:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [63:0] _GEN_5 = 64'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [63:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [63:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_5; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[42:0] : 43'h0; // @[OneHot.scala:58:35]
wire _T_2091 = _T_2165 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_2091 ? _a_set_T[42:0] : 43'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_2091 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_2091 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [8:0] _GEN_6 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [8:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_6; // @[Monitor.scala:659:79]
wire [8:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_6; // @[Monitor.scala:659:79, :660:77]
wire [514:0] _a_opcodes_set_T_1 = {511'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_2091 ? _a_opcodes_set_T_1[171:0] : 172'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [514:0] _a_sizes_set_T_1 = {511'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_2091 ? _a_sizes_set_T_1[171:0] : 172'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [42:0] d_clr; // @[Monitor.scala:664:34]
wire [42:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [171:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [171:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_7 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_7; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_7; // @[Monitor.scala:673:46, :783:46]
wire _T_2137 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [63:0] _GEN_8 = 64'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_8; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_8; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_8; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_8; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_2137 & ~d_release_ack ? _d_clr_wo_ready_T[42:0] : 43'h0; // @[OneHot.scala:58:35]
wire _T_2106 = _T_2239 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_2106 ? _d_clr_T[42:0] : 43'h0; // @[OneHot.scala:58:35]
wire [526:0] _d_opcodes_clr_T_5 = 527'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_2106 ? _d_opcodes_clr_T_5[171:0] : 172'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [526:0] _d_sizes_clr_T_5 = 527'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_2106 ? _d_sizes_clr_T_5[171:0] : 172'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [42:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [42:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [42:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [171:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [171:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [171:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [171:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [171:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [171:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [42:0] inflight_1; // @[Monitor.scala:726:35]
reg [171:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
reg [171:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [5:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [1:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[5:4]; // @[package.scala:243:46]
wire [1:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 2'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [1:0] c_first_counter_1; // @[Edges.scala:229:27]
wire [2:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] c_first_counter1_1 = _c_first_counter1_T_1[1:0]; // @[Edges.scala:230:28]
wire c_first_1 = c_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _c_first_last_T_2 = c_first_counter_1 == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _c_first_last_T_3 = c_first_beats1_1 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35]
wire [1:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [1:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [1:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:4]; // @[package.scala:243:46]
wire [1:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [1:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [2:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] d_first_counter1_2 = _d_first_counter1_T_2[1:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [1:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [42:0] c_set; // @[Monitor.scala:738:34]
wire [42:0] c_set_wo_ready; // @[Monitor.scala:739:34]
wire [171:0] c_opcodes_set; // @[Monitor.scala:740:34]
wire [171:0] c_sizes_set; // @[Monitor.scala:741:34]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [171:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [171:0] _c_opcode_lookup_T_6 = {168'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [171:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[171:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [171:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [171:0] _c_size_lookup_T_6 = {168'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [171:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[171:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm; // @[Monitor.scala:755:40]
wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44]
wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7]
wire [63:0] _GEN_9 = 64'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35]
wire [63:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _c_set_wo_ready_T = _GEN_9; // @[OneHot.scala:58:35]
wire [63:0] _c_set_T; // @[OneHot.scala:58:35]
assign _c_set_T = _GEN_9; // @[OneHot.scala:58:35]
assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[42:0] : 43'h0; // @[OneHot.scala:58:35]
wire _T_2178 = _T_2236 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35]
assign c_set = _T_2178 ? _c_set_T[42:0] : 43'h0; // @[OneHot.scala:58:35]
wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53]
wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}]
assign c_opcodes_set_interm = _T_2178 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}]
wire [3:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51]
wire [3:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:766:{51,59}]
assign c_sizes_set_interm = _T_2178 ? _c_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}]
wire [8:0] _GEN_10 = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79]
wire [8:0] _c_opcodes_set_T; // @[Monitor.scala:767:79]
assign _c_opcodes_set_T = _GEN_10; // @[Monitor.scala:767:79]
wire [8:0] _c_sizes_set_T; // @[Monitor.scala:768:77]
assign _c_sizes_set_T = _GEN_10; // @[Monitor.scala:767:79, :768:77]
wire [514:0] _c_opcodes_set_T_1 = {511'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}]
assign c_opcodes_set = _T_2178 ? _c_opcodes_set_T_1[171:0] : 172'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}]
wire [514:0] _c_sizes_set_T_1 = {511'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}]
assign c_sizes_set = _T_2178 ? _c_sizes_set_T_1[171:0] : 172'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}]
wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47]
wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95]
wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}]
wire [42:0] d_clr_1; // @[Monitor.scala:774:34]
wire [42:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [171:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [171:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_2209 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_2209 & d_release_ack_1 ? _d_clr_wo_ready_T_1[42:0] : 43'h0; // @[OneHot.scala:58:35]
wire _T_2191 = _T_2239 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_2191 ? _d_clr_T_1[42:0] : 43'h0; // @[OneHot.scala:58:35]
wire [526:0] _d_opcodes_clr_T_11 = 527'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_2191 ? _d_opcodes_clr_T_11[171:0] : 172'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [526:0] _d_sizes_clr_T_11 = 527'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_2191 ? _d_sizes_clr_T_11[171:0] : 172'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}]
wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}]
wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113]
wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}]
wire [42:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35]
wire [42:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [42:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [171:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43]
wire [171:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [171:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [171:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41]
wire [171:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [171:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26]
wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26]
reg [11:0] inflight_2; // @[Monitor.scala:828:27]
wire [5:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}]
wire [1:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[5:4]; // @[package.scala:243:46]
wire [1:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [1:0] d_first_counter_3; // @[Edges.scala:229:27]
wire [2:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] d_first_counter1_3 = _d_first_counter1_T_3[1:0]; // @[Edges.scala:230:28]
wire d_first_3 = d_first_counter_3 == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_6 = d_first_counter_3 == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_7 = d_first_beats1_3 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27]
wire [1:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] d_set; // @[Monitor.scala:833:25]
wire _T_2245 = _T_2239 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35]
wire [15:0] _d_set_T = 16'h1 << io_in_d_bits_sink_0; // @[OneHot.scala:58:35]
assign d_set = _T_2245 ? _d_set_T[11:0] : 12'h0; // @[OneHot.scala:58:35]
wire [11:0] e_clr; // @[Monitor.scala:839:25]
wire [15:0] _e_clr_T = 16'h1 << io_in_e_bits_sink_0; // @[OneHot.scala:58:35]
assign e_clr = io_in_e_valid_0 ? _e_clr_T[11:0] : 12'h0; // @[OneHot.scala:58:35] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_46 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_15 :
node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_18 = and(_T_16, _T_17)
node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_20 = and(_T_18, _T_19)
node _T_21 = or(UInt<1>(0h0), _T_20)
node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_24 = cvt(_T_23)
node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000)))
node _T_26 = asSInt(_T_25)
node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0)))
node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_29 = cvt(_T_28)
node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000)))
node _T_31 = asSInt(_T_30)
node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0)))
node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_39 = cvt(_T_38)
node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000)))
node _T_41 = asSInt(_T_40)
node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0)))
node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_44 = cvt(_T_43)
node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000)))
node _T_46 = asSInt(_T_45)
node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<27>(0h4000000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_54 = cvt(_T_53)
node _T_55 = and(_T_54, asSInt(UInt<13>(0h1000)))
node _T_56 = asSInt(_T_55)
node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0)))
node _T_58 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<19>(0h40000)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_27, _T_32)
node _T_64 = or(_T_63, _T_37)
node _T_65 = or(_T_64, _T_42)
node _T_66 = or(_T_65, _T_47)
node _T_67 = or(_T_66, _T_52)
node _T_68 = or(_T_67, _T_57)
node _T_69 = or(_T_68, _T_62)
node _T_70 = and(_T_22, _T_69)
node _T_71 = or(UInt<1>(0h0), _T_70)
node _T_72 = and(_T_21, _T_71)
node _T_73 = asUInt(reset)
node _T_74 = eq(_T_73, UInt<1>(0h0))
when _T_74 :
node _T_75 = eq(_T_72, UInt<1>(0h0))
when _T_75 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_72, UInt<1>(0h1), "") : assert_2
node _T_76 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_77 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_78 = and(_T_76, _T_77)
node _T_79 = or(UInt<1>(0h0), _T_78)
node _T_80 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_81 = cvt(_T_80)
node _T_82 = and(_T_81, asSInt(UInt<14>(0h2000)))
node _T_83 = asSInt(_T_82)
node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_86 = cvt(_T_85)
node _T_87 = and(_T_86, asSInt(UInt<13>(0h1000)))
node _T_88 = asSInt(_T_87)
node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0)))
node _T_90 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<17>(0h10000)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<18>(0h2f000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_101 = cvt(_T_100)
node _T_102 = and(_T_101, asSInt(UInt<17>(0h10000)))
node _T_103 = asSInt(_T_102)
node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0)))
node _T_105 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_106 = cvt(_T_105)
node _T_107 = and(_T_106, asSInt(UInt<27>(0h4000000)))
node _T_108 = asSInt(_T_107)
node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0)))
node _T_110 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_116 = cvt(_T_115)
node _T_117 = and(_T_116, asSInt(UInt<19>(0h40000)))
node _T_118 = asSInt(_T_117)
node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0)))
node _T_120 = or(_T_84, _T_89)
node _T_121 = or(_T_120, _T_94)
node _T_122 = or(_T_121, _T_99)
node _T_123 = or(_T_122, _T_104)
node _T_124 = or(_T_123, _T_109)
node _T_125 = or(_T_124, _T_114)
node _T_126 = or(_T_125, _T_119)
node _T_127 = and(_T_79, _T_126)
node _T_128 = or(UInt<1>(0h0), _T_127)
node _T_129 = and(UInt<1>(0h0), _T_128)
node _T_130 = asUInt(reset)
node _T_131 = eq(_T_130, UInt<1>(0h0))
when _T_131 :
node _T_132 = eq(_T_129, UInt<1>(0h0))
when _T_132 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_129, UInt<1>(0h1), "") : assert_3
node _T_133 = asUInt(reset)
node _T_134 = eq(_T_133, UInt<1>(0h0))
when _T_134 :
node _T_135 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_135 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_136 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_137 = asUInt(reset)
node _T_138 = eq(_T_137, UInt<1>(0h0))
when _T_138 :
node _T_139 = eq(_T_136, UInt<1>(0h0))
when _T_139 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_136, UInt<1>(0h1), "") : assert_5
node _T_140 = asUInt(reset)
node _T_141 = eq(_T_140, UInt<1>(0h0))
when _T_141 :
node _T_142 = eq(is_aligned, UInt<1>(0h0))
when _T_142 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_143 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_144 = asUInt(reset)
node _T_145 = eq(_T_144, UInt<1>(0h0))
when _T_145 :
node _T_146 = eq(_T_143, UInt<1>(0h0))
when _T_146 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_143, UInt<1>(0h1), "") : assert_7
node _T_147 = not(io.in.a.bits.mask)
node _T_148 = eq(_T_147, UInt<1>(0h0))
node _T_149 = asUInt(reset)
node _T_150 = eq(_T_149, UInt<1>(0h0))
when _T_150 :
node _T_151 = eq(_T_148, UInt<1>(0h0))
when _T_151 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_148, UInt<1>(0h1), "") : assert_8
node _T_152 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_153 = asUInt(reset)
node _T_154 = eq(_T_153, UInt<1>(0h0))
when _T_154 :
node _T_155 = eq(_T_152, UInt<1>(0h0))
when _T_155 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_152, UInt<1>(0h1), "") : assert_9
node _T_156 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_156 :
node _T_157 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_158 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_159 = and(_T_157, _T_158)
node _T_160 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_161 = and(_T_159, _T_160)
node _T_162 = or(UInt<1>(0h0), _T_161)
node _T_163 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_164 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_165 = cvt(_T_164)
node _T_166 = and(_T_165, asSInt(UInt<14>(0h2000)))
node _T_167 = asSInt(_T_166)
node _T_168 = eq(_T_167, asSInt(UInt<1>(0h0)))
node _T_169 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_170 = cvt(_T_169)
node _T_171 = and(_T_170, asSInt(UInt<13>(0h1000)))
node _T_172 = asSInt(_T_171)
node _T_173 = eq(_T_172, asSInt(UInt<1>(0h0)))
node _T_174 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_175 = cvt(_T_174)
node _T_176 = and(_T_175, asSInt(UInt<17>(0h10000)))
node _T_177 = asSInt(_T_176)
node _T_178 = eq(_T_177, asSInt(UInt<1>(0h0)))
node _T_179 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_180 = cvt(_T_179)
node _T_181 = and(_T_180, asSInt(UInt<18>(0h2f000)))
node _T_182 = asSInt(_T_181)
node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0)))
node _T_184 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_185 = cvt(_T_184)
node _T_186 = and(_T_185, asSInt(UInt<17>(0h10000)))
node _T_187 = asSInt(_T_186)
node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0)))
node _T_189 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_190 = cvt(_T_189)
node _T_191 = and(_T_190, asSInt(UInt<27>(0h4000000)))
node _T_192 = asSInt(_T_191)
node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0)))
node _T_194 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_195 = cvt(_T_194)
node _T_196 = and(_T_195, asSInt(UInt<13>(0h1000)))
node _T_197 = asSInt(_T_196)
node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0)))
node _T_199 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_200 = cvt(_T_199)
node _T_201 = and(_T_200, asSInt(UInt<19>(0h40000)))
node _T_202 = asSInt(_T_201)
node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0)))
node _T_204 = or(_T_168, _T_173)
node _T_205 = or(_T_204, _T_178)
node _T_206 = or(_T_205, _T_183)
node _T_207 = or(_T_206, _T_188)
node _T_208 = or(_T_207, _T_193)
node _T_209 = or(_T_208, _T_198)
node _T_210 = or(_T_209, _T_203)
node _T_211 = and(_T_163, _T_210)
node _T_212 = or(UInt<1>(0h0), _T_211)
node _T_213 = and(_T_162, _T_212)
node _T_214 = asUInt(reset)
node _T_215 = eq(_T_214, UInt<1>(0h0))
when _T_215 :
node _T_216 = eq(_T_213, UInt<1>(0h0))
when _T_216 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_213, UInt<1>(0h1), "") : assert_10
node _T_217 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_218 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_219 = and(_T_217, _T_218)
node _T_220 = or(UInt<1>(0h0), _T_219)
node _T_221 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_222 = cvt(_T_221)
node _T_223 = and(_T_222, asSInt(UInt<14>(0h2000)))
node _T_224 = asSInt(_T_223)
node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0)))
node _T_226 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_227 = cvt(_T_226)
node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000)))
node _T_229 = asSInt(_T_228)
node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0)))
node _T_231 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_232 = cvt(_T_231)
node _T_233 = and(_T_232, asSInt(UInt<17>(0h10000)))
node _T_234 = asSInt(_T_233)
node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0)))
node _T_236 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_237 = cvt(_T_236)
node _T_238 = and(_T_237, asSInt(UInt<18>(0h2f000)))
node _T_239 = asSInt(_T_238)
node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0)))
node _T_241 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_242 = cvt(_T_241)
node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000)))
node _T_244 = asSInt(_T_243)
node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0)))
node _T_246 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_247 = cvt(_T_246)
node _T_248 = and(_T_247, asSInt(UInt<27>(0h4000000)))
node _T_249 = asSInt(_T_248)
node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0)))
node _T_251 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_252 = cvt(_T_251)
node _T_253 = and(_T_252, asSInt(UInt<13>(0h1000)))
node _T_254 = asSInt(_T_253)
node _T_255 = eq(_T_254, asSInt(UInt<1>(0h0)))
node _T_256 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_257 = cvt(_T_256)
node _T_258 = and(_T_257, asSInt(UInt<19>(0h40000)))
node _T_259 = asSInt(_T_258)
node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0)))
node _T_261 = or(_T_225, _T_230)
node _T_262 = or(_T_261, _T_235)
node _T_263 = or(_T_262, _T_240)
node _T_264 = or(_T_263, _T_245)
node _T_265 = or(_T_264, _T_250)
node _T_266 = or(_T_265, _T_255)
node _T_267 = or(_T_266, _T_260)
node _T_268 = and(_T_220, _T_267)
node _T_269 = or(UInt<1>(0h0), _T_268)
node _T_270 = and(UInt<1>(0h0), _T_269)
node _T_271 = asUInt(reset)
node _T_272 = eq(_T_271, UInt<1>(0h0))
when _T_272 :
node _T_273 = eq(_T_270, UInt<1>(0h0))
when _T_273 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_270, UInt<1>(0h1), "") : assert_11
node _T_274 = asUInt(reset)
node _T_275 = eq(_T_274, UInt<1>(0h0))
when _T_275 :
node _T_276 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_276 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_277 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_278 = asUInt(reset)
node _T_279 = eq(_T_278, UInt<1>(0h0))
when _T_279 :
node _T_280 = eq(_T_277, UInt<1>(0h0))
when _T_280 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_277, UInt<1>(0h1), "") : assert_13
node _T_281 = asUInt(reset)
node _T_282 = eq(_T_281, UInt<1>(0h0))
when _T_282 :
node _T_283 = eq(is_aligned, UInt<1>(0h0))
when _T_283 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_284 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_285 = asUInt(reset)
node _T_286 = eq(_T_285, UInt<1>(0h0))
when _T_286 :
node _T_287 = eq(_T_284, UInt<1>(0h0))
when _T_287 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_284, UInt<1>(0h1), "") : assert_15
node _T_288 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_289 = asUInt(reset)
node _T_290 = eq(_T_289, UInt<1>(0h0))
when _T_290 :
node _T_291 = eq(_T_288, UInt<1>(0h0))
when _T_291 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_288, UInt<1>(0h1), "") : assert_16
node _T_292 = not(io.in.a.bits.mask)
node _T_293 = eq(_T_292, UInt<1>(0h0))
node _T_294 = asUInt(reset)
node _T_295 = eq(_T_294, UInt<1>(0h0))
when _T_295 :
node _T_296 = eq(_T_293, UInt<1>(0h0))
when _T_296 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_293, UInt<1>(0h1), "") : assert_17
node _T_297 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_298 = asUInt(reset)
node _T_299 = eq(_T_298, UInt<1>(0h0))
when _T_299 :
node _T_300 = eq(_T_297, UInt<1>(0h0))
when _T_300 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_297, UInt<1>(0h1), "") : assert_18
node _T_301 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_301 :
node _T_302 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_303 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_304 = and(_T_302, _T_303)
node _T_305 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_306 = and(_T_304, _T_305)
node _T_307 = or(UInt<1>(0h0), _T_306)
node _T_308 = asUInt(reset)
node _T_309 = eq(_T_308, UInt<1>(0h0))
when _T_309 :
node _T_310 = eq(_T_307, UInt<1>(0h0))
when _T_310 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_307, UInt<1>(0h1), "") : assert_19
node _T_311 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_312 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_313 = and(_T_311, _T_312)
node _T_314 = or(UInt<1>(0h0), _T_313)
node _T_315 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_316 = cvt(_T_315)
node _T_317 = and(_T_316, asSInt(UInt<13>(0h1000)))
node _T_318 = asSInt(_T_317)
node _T_319 = eq(_T_318, asSInt(UInt<1>(0h0)))
node _T_320 = and(_T_314, _T_319)
node _T_321 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_322 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_323 = and(_T_321, _T_322)
node _T_324 = or(UInt<1>(0h0), _T_323)
node _T_325 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_326 = cvt(_T_325)
node _T_327 = and(_T_326, asSInt(UInt<14>(0h2000)))
node _T_328 = asSInt(_T_327)
node _T_329 = eq(_T_328, asSInt(UInt<1>(0h0)))
node _T_330 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_331 = cvt(_T_330)
node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000)))
node _T_333 = asSInt(_T_332)
node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0)))
node _T_335 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_336 = cvt(_T_335)
node _T_337 = and(_T_336, asSInt(UInt<18>(0h2f000)))
node _T_338 = asSInt(_T_337)
node _T_339 = eq(_T_338, asSInt(UInt<1>(0h0)))
node _T_340 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_341 = cvt(_T_340)
node _T_342 = and(_T_341, asSInt(UInt<17>(0h10000)))
node _T_343 = asSInt(_T_342)
node _T_344 = eq(_T_343, asSInt(UInt<1>(0h0)))
node _T_345 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_346 = cvt(_T_345)
node _T_347 = and(_T_346, asSInt(UInt<27>(0h4000000)))
node _T_348 = asSInt(_T_347)
node _T_349 = eq(_T_348, asSInt(UInt<1>(0h0)))
node _T_350 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_351 = cvt(_T_350)
node _T_352 = and(_T_351, asSInt(UInt<13>(0h1000)))
node _T_353 = asSInt(_T_352)
node _T_354 = eq(_T_353, asSInt(UInt<1>(0h0)))
node _T_355 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_356 = cvt(_T_355)
node _T_357 = and(_T_356, asSInt(UInt<19>(0h40000)))
node _T_358 = asSInt(_T_357)
node _T_359 = eq(_T_358, asSInt(UInt<1>(0h0)))
node _T_360 = or(_T_329, _T_334)
node _T_361 = or(_T_360, _T_339)
node _T_362 = or(_T_361, _T_344)
node _T_363 = or(_T_362, _T_349)
node _T_364 = or(_T_363, _T_354)
node _T_365 = or(_T_364, _T_359)
node _T_366 = and(_T_324, _T_365)
node _T_367 = or(UInt<1>(0h0), _T_320)
node _T_368 = or(_T_367, _T_366)
node _T_369 = asUInt(reset)
node _T_370 = eq(_T_369, UInt<1>(0h0))
when _T_370 :
node _T_371 = eq(_T_368, UInt<1>(0h0))
when _T_371 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_368, UInt<1>(0h1), "") : assert_20
node _T_372 = asUInt(reset)
node _T_373 = eq(_T_372, UInt<1>(0h0))
when _T_373 :
node _T_374 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_374 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_375 = asUInt(reset)
node _T_376 = eq(_T_375, UInt<1>(0h0))
when _T_376 :
node _T_377 = eq(is_aligned, UInt<1>(0h0))
when _T_377 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_378 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_T_378, UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_378, UInt<1>(0h1), "") : assert_23
node _T_382 = eq(io.in.a.bits.mask, mask)
node _T_383 = asUInt(reset)
node _T_384 = eq(_T_383, UInt<1>(0h0))
when _T_384 :
node _T_385 = eq(_T_382, UInt<1>(0h0))
when _T_385 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_382, UInt<1>(0h1), "") : assert_24
node _T_386 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_387 = asUInt(reset)
node _T_388 = eq(_T_387, UInt<1>(0h0))
when _T_388 :
node _T_389 = eq(_T_386, UInt<1>(0h0))
when _T_389 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_386, UInt<1>(0h1), "") : assert_25
node _T_390 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_390 :
node _T_391 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_392 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_393 = and(_T_391, _T_392)
node _T_394 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_395 = and(_T_393, _T_394)
node _T_396 = or(UInt<1>(0h0), _T_395)
node _T_397 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_398 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_399 = and(_T_397, _T_398)
node _T_400 = or(UInt<1>(0h0), _T_399)
node _T_401 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_402 = cvt(_T_401)
node _T_403 = and(_T_402, asSInt(UInt<13>(0h1000)))
node _T_404 = asSInt(_T_403)
node _T_405 = eq(_T_404, asSInt(UInt<1>(0h0)))
node _T_406 = and(_T_400, _T_405)
node _T_407 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_408 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_409 = and(_T_407, _T_408)
node _T_410 = or(UInt<1>(0h0), _T_409)
node _T_411 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_412 = cvt(_T_411)
node _T_413 = and(_T_412, asSInt(UInt<14>(0h2000)))
node _T_414 = asSInt(_T_413)
node _T_415 = eq(_T_414, asSInt(UInt<1>(0h0)))
node _T_416 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_417 = cvt(_T_416)
node _T_418 = and(_T_417, asSInt(UInt<18>(0h2f000)))
node _T_419 = asSInt(_T_418)
node _T_420 = eq(_T_419, asSInt(UInt<1>(0h0)))
node _T_421 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_422 = cvt(_T_421)
node _T_423 = and(_T_422, asSInt(UInt<17>(0h10000)))
node _T_424 = asSInt(_T_423)
node _T_425 = eq(_T_424, asSInt(UInt<1>(0h0)))
node _T_426 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_427 = cvt(_T_426)
node _T_428 = and(_T_427, asSInt(UInt<27>(0h4000000)))
node _T_429 = asSInt(_T_428)
node _T_430 = eq(_T_429, asSInt(UInt<1>(0h0)))
node _T_431 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_432 = cvt(_T_431)
node _T_433 = and(_T_432, asSInt(UInt<13>(0h1000)))
node _T_434 = asSInt(_T_433)
node _T_435 = eq(_T_434, asSInt(UInt<1>(0h0)))
node _T_436 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_437 = cvt(_T_436)
node _T_438 = and(_T_437, asSInt(UInt<19>(0h40000)))
node _T_439 = asSInt(_T_438)
node _T_440 = eq(_T_439, asSInt(UInt<1>(0h0)))
node _T_441 = or(_T_415, _T_420)
node _T_442 = or(_T_441, _T_425)
node _T_443 = or(_T_442, _T_430)
node _T_444 = or(_T_443, _T_435)
node _T_445 = or(_T_444, _T_440)
node _T_446 = and(_T_410, _T_445)
node _T_447 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_448 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_449 = cvt(_T_448)
node _T_450 = and(_T_449, asSInt(UInt<17>(0h10000)))
node _T_451 = asSInt(_T_450)
node _T_452 = eq(_T_451, asSInt(UInt<1>(0h0)))
node _T_453 = and(_T_447, _T_452)
node _T_454 = or(UInt<1>(0h0), _T_406)
node _T_455 = or(_T_454, _T_446)
node _T_456 = or(_T_455, _T_453)
node _T_457 = and(_T_396, _T_456)
node _T_458 = asUInt(reset)
node _T_459 = eq(_T_458, UInt<1>(0h0))
when _T_459 :
node _T_460 = eq(_T_457, UInt<1>(0h0))
when _T_460 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_457, UInt<1>(0h1), "") : assert_26
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_464 = asUInt(reset)
node _T_465 = eq(_T_464, UInt<1>(0h0))
when _T_465 :
node _T_466 = eq(is_aligned, UInt<1>(0h0))
when _T_466 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_467 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_468 = asUInt(reset)
node _T_469 = eq(_T_468, UInt<1>(0h0))
when _T_469 :
node _T_470 = eq(_T_467, UInt<1>(0h0))
when _T_470 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_467, UInt<1>(0h1), "") : assert_29
node _T_471 = eq(io.in.a.bits.mask, mask)
node _T_472 = asUInt(reset)
node _T_473 = eq(_T_472, UInt<1>(0h0))
when _T_473 :
node _T_474 = eq(_T_471, UInt<1>(0h0))
when _T_474 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_471, UInt<1>(0h1), "") : assert_30
node _T_475 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_475 :
node _T_476 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_477 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_478 = and(_T_476, _T_477)
node _T_479 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_480 = and(_T_478, _T_479)
node _T_481 = or(UInt<1>(0h0), _T_480)
node _T_482 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_483 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_484 = and(_T_482, _T_483)
node _T_485 = or(UInt<1>(0h0), _T_484)
node _T_486 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_487 = cvt(_T_486)
node _T_488 = and(_T_487, asSInt(UInt<13>(0h1000)))
node _T_489 = asSInt(_T_488)
node _T_490 = eq(_T_489, asSInt(UInt<1>(0h0)))
node _T_491 = and(_T_485, _T_490)
node _T_492 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_493 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_494 = and(_T_492, _T_493)
node _T_495 = or(UInt<1>(0h0), _T_494)
node _T_496 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_497 = cvt(_T_496)
node _T_498 = and(_T_497, asSInt(UInt<14>(0h2000)))
node _T_499 = asSInt(_T_498)
node _T_500 = eq(_T_499, asSInt(UInt<1>(0h0)))
node _T_501 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_502 = cvt(_T_501)
node _T_503 = and(_T_502, asSInt(UInt<18>(0h2f000)))
node _T_504 = asSInt(_T_503)
node _T_505 = eq(_T_504, asSInt(UInt<1>(0h0)))
node _T_506 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_507 = cvt(_T_506)
node _T_508 = and(_T_507, asSInt(UInt<17>(0h10000)))
node _T_509 = asSInt(_T_508)
node _T_510 = eq(_T_509, asSInt(UInt<1>(0h0)))
node _T_511 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_512 = cvt(_T_511)
node _T_513 = and(_T_512, asSInt(UInt<27>(0h4000000)))
node _T_514 = asSInt(_T_513)
node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0)))
node _T_516 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_517 = cvt(_T_516)
node _T_518 = and(_T_517, asSInt(UInt<13>(0h1000)))
node _T_519 = asSInt(_T_518)
node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0)))
node _T_521 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_522 = cvt(_T_521)
node _T_523 = and(_T_522, asSInt(UInt<19>(0h40000)))
node _T_524 = asSInt(_T_523)
node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0)))
node _T_526 = or(_T_500, _T_505)
node _T_527 = or(_T_526, _T_510)
node _T_528 = or(_T_527, _T_515)
node _T_529 = or(_T_528, _T_520)
node _T_530 = or(_T_529, _T_525)
node _T_531 = and(_T_495, _T_530)
node _T_532 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_533 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_534 = cvt(_T_533)
node _T_535 = and(_T_534, asSInt(UInt<17>(0h10000)))
node _T_536 = asSInt(_T_535)
node _T_537 = eq(_T_536, asSInt(UInt<1>(0h0)))
node _T_538 = and(_T_532, _T_537)
node _T_539 = or(UInt<1>(0h0), _T_491)
node _T_540 = or(_T_539, _T_531)
node _T_541 = or(_T_540, _T_538)
node _T_542 = and(_T_481, _T_541)
node _T_543 = asUInt(reset)
node _T_544 = eq(_T_543, UInt<1>(0h0))
when _T_544 :
node _T_545 = eq(_T_542, UInt<1>(0h0))
when _T_545 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_542, UInt<1>(0h1), "") : assert_31
node _T_546 = asUInt(reset)
node _T_547 = eq(_T_546, UInt<1>(0h0))
when _T_547 :
node _T_548 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_548 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(is_aligned, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_552 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(_T_552, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_552, UInt<1>(0h1), "") : assert_34
node _T_556 = not(mask)
node _T_557 = and(io.in.a.bits.mask, _T_556)
node _T_558 = eq(_T_557, UInt<1>(0h0))
node _T_559 = asUInt(reset)
node _T_560 = eq(_T_559, UInt<1>(0h0))
when _T_560 :
node _T_561 = eq(_T_558, UInt<1>(0h0))
when _T_561 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_558, UInt<1>(0h1), "") : assert_35
node _T_562 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_562 :
node _T_563 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_564 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_565 = and(_T_563, _T_564)
node _T_566 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_567 = and(_T_565, _T_566)
node _T_568 = or(UInt<1>(0h0), _T_567)
node _T_569 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_570 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_571 = and(_T_569, _T_570)
node _T_572 = or(UInt<1>(0h0), _T_571)
node _T_573 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_574 = cvt(_T_573)
node _T_575 = and(_T_574, asSInt(UInt<14>(0h2000)))
node _T_576 = asSInt(_T_575)
node _T_577 = eq(_T_576, asSInt(UInt<1>(0h0)))
node _T_578 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_579 = cvt(_T_578)
node _T_580 = and(_T_579, asSInt(UInt<13>(0h1000)))
node _T_581 = asSInt(_T_580)
node _T_582 = eq(_T_581, asSInt(UInt<1>(0h0)))
node _T_583 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_584 = cvt(_T_583)
node _T_585 = and(_T_584, asSInt(UInt<18>(0h2f000)))
node _T_586 = asSInt(_T_585)
node _T_587 = eq(_T_586, asSInt(UInt<1>(0h0)))
node _T_588 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_589 = cvt(_T_588)
node _T_590 = and(_T_589, asSInt(UInt<17>(0h10000)))
node _T_591 = asSInt(_T_590)
node _T_592 = eq(_T_591, asSInt(UInt<1>(0h0)))
node _T_593 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_594 = cvt(_T_593)
node _T_595 = and(_T_594, asSInt(UInt<27>(0h4000000)))
node _T_596 = asSInt(_T_595)
node _T_597 = eq(_T_596, asSInt(UInt<1>(0h0)))
node _T_598 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_599 = cvt(_T_598)
node _T_600 = and(_T_599, asSInt(UInt<13>(0h1000)))
node _T_601 = asSInt(_T_600)
node _T_602 = eq(_T_601, asSInt(UInt<1>(0h0)))
node _T_603 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_604 = cvt(_T_603)
node _T_605 = and(_T_604, asSInt(UInt<19>(0h40000)))
node _T_606 = asSInt(_T_605)
node _T_607 = eq(_T_606, asSInt(UInt<1>(0h0)))
node _T_608 = or(_T_577, _T_582)
node _T_609 = or(_T_608, _T_587)
node _T_610 = or(_T_609, _T_592)
node _T_611 = or(_T_610, _T_597)
node _T_612 = or(_T_611, _T_602)
node _T_613 = or(_T_612, _T_607)
node _T_614 = and(_T_572, _T_613)
node _T_615 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_616 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_617 = cvt(_T_616)
node _T_618 = and(_T_617, asSInt(UInt<17>(0h10000)))
node _T_619 = asSInt(_T_618)
node _T_620 = eq(_T_619, asSInt(UInt<1>(0h0)))
node _T_621 = and(_T_615, _T_620)
node _T_622 = or(UInt<1>(0h0), _T_614)
node _T_623 = or(_T_622, _T_621)
node _T_624 = and(_T_568, _T_623)
node _T_625 = asUInt(reset)
node _T_626 = eq(_T_625, UInt<1>(0h0))
when _T_626 :
node _T_627 = eq(_T_624, UInt<1>(0h0))
when _T_627 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_624, UInt<1>(0h1), "") : assert_36
node _T_628 = asUInt(reset)
node _T_629 = eq(_T_628, UInt<1>(0h0))
when _T_629 :
node _T_630 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_630 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(is_aligned, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_634 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_635 = asUInt(reset)
node _T_636 = eq(_T_635, UInt<1>(0h0))
when _T_636 :
node _T_637 = eq(_T_634, UInt<1>(0h0))
when _T_637 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_634, UInt<1>(0h1), "") : assert_39
node _T_638 = eq(io.in.a.bits.mask, mask)
node _T_639 = asUInt(reset)
node _T_640 = eq(_T_639, UInt<1>(0h0))
when _T_640 :
node _T_641 = eq(_T_638, UInt<1>(0h0))
when _T_641 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_638, UInt<1>(0h1), "") : assert_40
node _T_642 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_642 :
node _T_643 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_644 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_645 = and(_T_643, _T_644)
node _T_646 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_647 = and(_T_645, _T_646)
node _T_648 = or(UInt<1>(0h0), _T_647)
node _T_649 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_650 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_651 = and(_T_649, _T_650)
node _T_652 = or(UInt<1>(0h0), _T_651)
node _T_653 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_654 = cvt(_T_653)
node _T_655 = and(_T_654, asSInt(UInt<14>(0h2000)))
node _T_656 = asSInt(_T_655)
node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0)))
node _T_658 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_659 = cvt(_T_658)
node _T_660 = and(_T_659, asSInt(UInt<13>(0h1000)))
node _T_661 = asSInt(_T_660)
node _T_662 = eq(_T_661, asSInt(UInt<1>(0h0)))
node _T_663 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_664 = cvt(_T_663)
node _T_665 = and(_T_664, asSInt(UInt<18>(0h2f000)))
node _T_666 = asSInt(_T_665)
node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0)))
node _T_668 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_669 = cvt(_T_668)
node _T_670 = and(_T_669, asSInt(UInt<17>(0h10000)))
node _T_671 = asSInt(_T_670)
node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0)))
node _T_673 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_674 = cvt(_T_673)
node _T_675 = and(_T_674, asSInt(UInt<27>(0h4000000)))
node _T_676 = asSInt(_T_675)
node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0)))
node _T_678 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_679 = cvt(_T_678)
node _T_680 = and(_T_679, asSInt(UInt<13>(0h1000)))
node _T_681 = asSInt(_T_680)
node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0)))
node _T_683 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_684 = cvt(_T_683)
node _T_685 = and(_T_684, asSInt(UInt<19>(0h40000)))
node _T_686 = asSInt(_T_685)
node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0)))
node _T_688 = or(_T_657, _T_662)
node _T_689 = or(_T_688, _T_667)
node _T_690 = or(_T_689, _T_672)
node _T_691 = or(_T_690, _T_677)
node _T_692 = or(_T_691, _T_682)
node _T_693 = or(_T_692, _T_687)
node _T_694 = and(_T_652, _T_693)
node _T_695 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_696 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_697 = cvt(_T_696)
node _T_698 = and(_T_697, asSInt(UInt<17>(0h10000)))
node _T_699 = asSInt(_T_698)
node _T_700 = eq(_T_699, asSInt(UInt<1>(0h0)))
node _T_701 = and(_T_695, _T_700)
node _T_702 = or(UInt<1>(0h0), _T_694)
node _T_703 = or(_T_702, _T_701)
node _T_704 = and(_T_648, _T_703)
node _T_705 = asUInt(reset)
node _T_706 = eq(_T_705, UInt<1>(0h0))
when _T_706 :
node _T_707 = eq(_T_704, UInt<1>(0h0))
when _T_707 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_704, UInt<1>(0h1), "") : assert_41
node _T_708 = asUInt(reset)
node _T_709 = eq(_T_708, UInt<1>(0h0))
when _T_709 :
node _T_710 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_710 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_711 = asUInt(reset)
node _T_712 = eq(_T_711, UInt<1>(0h0))
when _T_712 :
node _T_713 = eq(is_aligned, UInt<1>(0h0))
when _T_713 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_714 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_715 = asUInt(reset)
node _T_716 = eq(_T_715, UInt<1>(0h0))
when _T_716 :
node _T_717 = eq(_T_714, UInt<1>(0h0))
when _T_717 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_714, UInt<1>(0h1), "") : assert_44
node _T_718 = eq(io.in.a.bits.mask, mask)
node _T_719 = asUInt(reset)
node _T_720 = eq(_T_719, UInt<1>(0h0))
when _T_720 :
node _T_721 = eq(_T_718, UInt<1>(0h0))
when _T_721 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_718, UInt<1>(0h1), "") : assert_45
node _T_722 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_722 :
node _T_723 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_724 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_725 = and(_T_723, _T_724)
node _T_726 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_727 = and(_T_725, _T_726)
node _T_728 = or(UInt<1>(0h0), _T_727)
node _T_729 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_730 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_731 = and(_T_729, _T_730)
node _T_732 = or(UInt<1>(0h0), _T_731)
node _T_733 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_734 = cvt(_T_733)
node _T_735 = and(_T_734, asSInt(UInt<13>(0h1000)))
node _T_736 = asSInt(_T_735)
node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0)))
node _T_738 = and(_T_732, _T_737)
node _T_739 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_740 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_741 = cvt(_T_740)
node _T_742 = and(_T_741, asSInt(UInt<14>(0h2000)))
node _T_743 = asSInt(_T_742)
node _T_744 = eq(_T_743, asSInt(UInt<1>(0h0)))
node _T_745 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_746 = cvt(_T_745)
node _T_747 = and(_T_746, asSInt(UInt<17>(0h10000)))
node _T_748 = asSInt(_T_747)
node _T_749 = eq(_T_748, asSInt(UInt<1>(0h0)))
node _T_750 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_751 = cvt(_T_750)
node _T_752 = and(_T_751, asSInt(UInt<18>(0h2f000)))
node _T_753 = asSInt(_T_752)
node _T_754 = eq(_T_753, asSInt(UInt<1>(0h0)))
node _T_755 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_756 = cvt(_T_755)
node _T_757 = and(_T_756, asSInt(UInt<17>(0h10000)))
node _T_758 = asSInt(_T_757)
node _T_759 = eq(_T_758, asSInt(UInt<1>(0h0)))
node _T_760 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_761 = cvt(_T_760)
node _T_762 = and(_T_761, asSInt(UInt<27>(0h4000000)))
node _T_763 = asSInt(_T_762)
node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0)))
node _T_765 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_766 = cvt(_T_765)
node _T_767 = and(_T_766, asSInt(UInt<13>(0h1000)))
node _T_768 = asSInt(_T_767)
node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0)))
node _T_770 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_771 = cvt(_T_770)
node _T_772 = and(_T_771, asSInt(UInt<19>(0h40000)))
node _T_773 = asSInt(_T_772)
node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0)))
node _T_775 = or(_T_744, _T_749)
node _T_776 = or(_T_775, _T_754)
node _T_777 = or(_T_776, _T_759)
node _T_778 = or(_T_777, _T_764)
node _T_779 = or(_T_778, _T_769)
node _T_780 = or(_T_779, _T_774)
node _T_781 = and(_T_739, _T_780)
node _T_782 = or(UInt<1>(0h0), _T_738)
node _T_783 = or(_T_782, _T_781)
node _T_784 = and(_T_728, _T_783)
node _T_785 = asUInt(reset)
node _T_786 = eq(_T_785, UInt<1>(0h0))
when _T_786 :
node _T_787 = eq(_T_784, UInt<1>(0h0))
when _T_787 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_784, UInt<1>(0h1), "") : assert_46
node _T_788 = asUInt(reset)
node _T_789 = eq(_T_788, UInt<1>(0h0))
when _T_789 :
node _T_790 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_790 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_791 = asUInt(reset)
node _T_792 = eq(_T_791, UInt<1>(0h0))
when _T_792 :
node _T_793 = eq(is_aligned, UInt<1>(0h0))
when _T_793 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_794 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_795 = asUInt(reset)
node _T_796 = eq(_T_795, UInt<1>(0h0))
when _T_796 :
node _T_797 = eq(_T_794, UInt<1>(0h0))
when _T_797 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_794, UInt<1>(0h1), "") : assert_49
node _T_798 = eq(io.in.a.bits.mask, mask)
node _T_799 = asUInt(reset)
node _T_800 = eq(_T_799, UInt<1>(0h0))
when _T_800 :
node _T_801 = eq(_T_798, UInt<1>(0h0))
when _T_801 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_798, UInt<1>(0h1), "") : assert_50
node _T_802 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_803 = asUInt(reset)
node _T_804 = eq(_T_803, UInt<1>(0h0))
when _T_804 :
node _T_805 = eq(_T_802, UInt<1>(0h0))
when _T_805 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_802, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_806 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_807 = asUInt(reset)
node _T_808 = eq(_T_807, UInt<1>(0h0))
when _T_808 :
node _T_809 = eq(_T_806, UInt<1>(0h0))
when _T_809 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_806, UInt<1>(0h1), "") : assert_52
node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_1
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_810 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_810 :
node _T_811 = asUInt(reset)
node _T_812 = eq(_T_811, UInt<1>(0h0))
when _T_812 :
node _T_813 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_813 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_814 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_815 = asUInt(reset)
node _T_816 = eq(_T_815, UInt<1>(0h0))
when _T_816 :
node _T_817 = eq(_T_814, UInt<1>(0h0))
when _T_817 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_814, UInt<1>(0h1), "") : assert_54
node _T_818 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_819 = asUInt(reset)
node _T_820 = eq(_T_819, UInt<1>(0h0))
when _T_820 :
node _T_821 = eq(_T_818, UInt<1>(0h0))
when _T_821 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_818, UInt<1>(0h1), "") : assert_55
node _T_822 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_823 = asUInt(reset)
node _T_824 = eq(_T_823, UInt<1>(0h0))
when _T_824 :
node _T_825 = eq(_T_822, UInt<1>(0h0))
when _T_825 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_822, UInt<1>(0h1), "") : assert_56
node _T_826 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_827 = asUInt(reset)
node _T_828 = eq(_T_827, UInt<1>(0h0))
when _T_828 :
node _T_829 = eq(_T_826, UInt<1>(0h0))
when _T_829 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_826, UInt<1>(0h1), "") : assert_57
node _T_830 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_830 :
node _T_831 = asUInt(reset)
node _T_832 = eq(_T_831, UInt<1>(0h0))
when _T_832 :
node _T_833 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_833 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_834 = asUInt(reset)
node _T_835 = eq(_T_834, UInt<1>(0h0))
when _T_835 :
node _T_836 = eq(sink_ok, UInt<1>(0h0))
when _T_836 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_837 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_838 = asUInt(reset)
node _T_839 = eq(_T_838, UInt<1>(0h0))
when _T_839 :
node _T_840 = eq(_T_837, UInt<1>(0h0))
when _T_840 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_837, UInt<1>(0h1), "") : assert_60
node _T_841 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_842 = asUInt(reset)
node _T_843 = eq(_T_842, UInt<1>(0h0))
when _T_843 :
node _T_844 = eq(_T_841, UInt<1>(0h0))
when _T_844 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_841, UInt<1>(0h1), "") : assert_61
node _T_845 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_846 = asUInt(reset)
node _T_847 = eq(_T_846, UInt<1>(0h0))
when _T_847 :
node _T_848 = eq(_T_845, UInt<1>(0h0))
when _T_848 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_845, UInt<1>(0h1), "") : assert_62
node _T_849 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_850 = asUInt(reset)
node _T_851 = eq(_T_850, UInt<1>(0h0))
when _T_851 :
node _T_852 = eq(_T_849, UInt<1>(0h0))
when _T_852 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_849, UInt<1>(0h1), "") : assert_63
node _T_853 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_854 = or(UInt<1>(0h1), _T_853)
node _T_855 = asUInt(reset)
node _T_856 = eq(_T_855, UInt<1>(0h0))
when _T_856 :
node _T_857 = eq(_T_854, UInt<1>(0h0))
when _T_857 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_854, UInt<1>(0h1), "") : assert_64
node _T_858 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_858 :
node _T_859 = asUInt(reset)
node _T_860 = eq(_T_859, UInt<1>(0h0))
when _T_860 :
node _T_861 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_861 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_862 = asUInt(reset)
node _T_863 = eq(_T_862, UInt<1>(0h0))
when _T_863 :
node _T_864 = eq(sink_ok, UInt<1>(0h0))
when _T_864 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_865 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_866 = asUInt(reset)
node _T_867 = eq(_T_866, UInt<1>(0h0))
when _T_867 :
node _T_868 = eq(_T_865, UInt<1>(0h0))
when _T_868 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_865, UInt<1>(0h1), "") : assert_67
node _T_869 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_870 = asUInt(reset)
node _T_871 = eq(_T_870, UInt<1>(0h0))
when _T_871 :
node _T_872 = eq(_T_869, UInt<1>(0h0))
when _T_872 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_869, UInt<1>(0h1), "") : assert_68
node _T_873 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_874 = asUInt(reset)
node _T_875 = eq(_T_874, UInt<1>(0h0))
when _T_875 :
node _T_876 = eq(_T_873, UInt<1>(0h0))
when _T_876 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_873, UInt<1>(0h1), "") : assert_69
node _T_877 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_878 = or(_T_877, io.in.d.bits.corrupt)
node _T_879 = asUInt(reset)
node _T_880 = eq(_T_879, UInt<1>(0h0))
when _T_880 :
node _T_881 = eq(_T_878, UInt<1>(0h0))
when _T_881 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_878, UInt<1>(0h1), "") : assert_70
node _T_882 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_883 = or(UInt<1>(0h1), _T_882)
node _T_884 = asUInt(reset)
node _T_885 = eq(_T_884, UInt<1>(0h0))
when _T_885 :
node _T_886 = eq(_T_883, UInt<1>(0h0))
when _T_886 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_883, UInt<1>(0h1), "") : assert_71
node _T_887 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_887 :
node _T_888 = asUInt(reset)
node _T_889 = eq(_T_888, UInt<1>(0h0))
when _T_889 :
node _T_890 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_890 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_891 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_892 = asUInt(reset)
node _T_893 = eq(_T_892, UInt<1>(0h0))
when _T_893 :
node _T_894 = eq(_T_891, UInt<1>(0h0))
when _T_894 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_891, UInt<1>(0h1), "") : assert_73
node _T_895 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_896 = asUInt(reset)
node _T_897 = eq(_T_896, UInt<1>(0h0))
when _T_897 :
node _T_898 = eq(_T_895, UInt<1>(0h0))
when _T_898 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_895, UInt<1>(0h1), "") : assert_74
node _T_899 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_900 = or(UInt<1>(0h1), _T_899)
node _T_901 = asUInt(reset)
node _T_902 = eq(_T_901, UInt<1>(0h0))
when _T_902 :
node _T_903 = eq(_T_900, UInt<1>(0h0))
when _T_903 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_900, UInt<1>(0h1), "") : assert_75
node _T_904 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_904 :
node _T_905 = asUInt(reset)
node _T_906 = eq(_T_905, UInt<1>(0h0))
when _T_906 :
node _T_907 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_907 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_908 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_909 = asUInt(reset)
node _T_910 = eq(_T_909, UInt<1>(0h0))
when _T_910 :
node _T_911 = eq(_T_908, UInt<1>(0h0))
when _T_911 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_908, UInt<1>(0h1), "") : assert_77
node _T_912 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_913 = or(_T_912, io.in.d.bits.corrupt)
node _T_914 = asUInt(reset)
node _T_915 = eq(_T_914, UInt<1>(0h0))
when _T_915 :
node _T_916 = eq(_T_913, UInt<1>(0h0))
when _T_916 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_913, UInt<1>(0h1), "") : assert_78
node _T_917 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_918 = or(UInt<1>(0h1), _T_917)
node _T_919 = asUInt(reset)
node _T_920 = eq(_T_919, UInt<1>(0h0))
when _T_920 :
node _T_921 = eq(_T_918, UInt<1>(0h0))
when _T_921 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_918, UInt<1>(0h1), "") : assert_79
node _T_922 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_922 :
node _T_923 = asUInt(reset)
node _T_924 = eq(_T_923, UInt<1>(0h0))
when _T_924 :
node _T_925 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_925 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_926 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_927 = asUInt(reset)
node _T_928 = eq(_T_927, UInt<1>(0h0))
when _T_928 :
node _T_929 = eq(_T_926, UInt<1>(0h0))
when _T_929 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_926, UInt<1>(0h1), "") : assert_81
node _T_930 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_931 = asUInt(reset)
node _T_932 = eq(_T_931, UInt<1>(0h0))
when _T_932 :
node _T_933 = eq(_T_930, UInt<1>(0h0))
when _T_933 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_930, UInt<1>(0h1), "") : assert_82
node _T_934 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_935 = or(UInt<1>(0h1), _T_934)
node _T_936 = asUInt(reset)
node _T_937 = eq(_T_936, UInt<1>(0h0))
when _T_937 :
node _T_938 = eq(_T_935, UInt<1>(0h0))
when _T_938 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_935, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_939 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_940 = asUInt(reset)
node _T_941 = eq(_T_940, UInt<1>(0h0))
when _T_941 :
node _T_942 = eq(_T_939, UInt<1>(0h0))
when _T_942 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_939, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_943 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_944 = asUInt(reset)
node _T_945 = eq(_T_944, UInt<1>(0h0))
when _T_945 :
node _T_946 = eq(_T_943, UInt<1>(0h0))
when _T_946 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_943, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_947 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_948 = asUInt(reset)
node _T_949 = eq(_T_948, UInt<1>(0h0))
when _T_949 :
node _T_950 = eq(_T_947, UInt<1>(0h0))
when _T_950 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_947, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_951 = eq(a_first, UInt<1>(0h0))
node _T_952 = and(io.in.a.valid, _T_951)
when _T_952 :
node _T_953 = eq(io.in.a.bits.opcode, opcode)
node _T_954 = asUInt(reset)
node _T_955 = eq(_T_954, UInt<1>(0h0))
when _T_955 :
node _T_956 = eq(_T_953, UInt<1>(0h0))
when _T_956 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_953, UInt<1>(0h1), "") : assert_87
node _T_957 = eq(io.in.a.bits.param, param)
node _T_958 = asUInt(reset)
node _T_959 = eq(_T_958, UInt<1>(0h0))
when _T_959 :
node _T_960 = eq(_T_957, UInt<1>(0h0))
when _T_960 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_957, UInt<1>(0h1), "") : assert_88
node _T_961 = eq(io.in.a.bits.size, size)
node _T_962 = asUInt(reset)
node _T_963 = eq(_T_962, UInt<1>(0h0))
when _T_963 :
node _T_964 = eq(_T_961, UInt<1>(0h0))
when _T_964 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_961, UInt<1>(0h1), "") : assert_89
node _T_965 = eq(io.in.a.bits.source, source)
node _T_966 = asUInt(reset)
node _T_967 = eq(_T_966, UInt<1>(0h0))
when _T_967 :
node _T_968 = eq(_T_965, UInt<1>(0h0))
when _T_968 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_965, UInt<1>(0h1), "") : assert_90
node _T_969 = eq(io.in.a.bits.address, address)
node _T_970 = asUInt(reset)
node _T_971 = eq(_T_970, UInt<1>(0h0))
when _T_971 :
node _T_972 = eq(_T_969, UInt<1>(0h0))
when _T_972 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_969, UInt<1>(0h1), "") : assert_91
node _T_973 = and(io.in.a.ready, io.in.a.valid)
node _T_974 = and(_T_973, a_first)
when _T_974 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_975 = eq(d_first, UInt<1>(0h0))
node _T_976 = and(io.in.d.valid, _T_975)
when _T_976 :
node _T_977 = eq(io.in.d.bits.opcode, opcode_1)
node _T_978 = asUInt(reset)
node _T_979 = eq(_T_978, UInt<1>(0h0))
when _T_979 :
node _T_980 = eq(_T_977, UInt<1>(0h0))
when _T_980 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_977, UInt<1>(0h1), "") : assert_92
node _T_981 = eq(io.in.d.bits.param, param_1)
node _T_982 = asUInt(reset)
node _T_983 = eq(_T_982, UInt<1>(0h0))
when _T_983 :
node _T_984 = eq(_T_981, UInt<1>(0h0))
when _T_984 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_981, UInt<1>(0h1), "") : assert_93
node _T_985 = eq(io.in.d.bits.size, size_1)
node _T_986 = asUInt(reset)
node _T_987 = eq(_T_986, UInt<1>(0h0))
when _T_987 :
node _T_988 = eq(_T_985, UInt<1>(0h0))
when _T_988 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_985, UInt<1>(0h1), "") : assert_94
node _T_989 = eq(io.in.d.bits.source, source_1)
node _T_990 = asUInt(reset)
node _T_991 = eq(_T_990, UInt<1>(0h0))
when _T_991 :
node _T_992 = eq(_T_989, UInt<1>(0h0))
when _T_992 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_989, UInt<1>(0h1), "") : assert_95
node _T_993 = eq(io.in.d.bits.sink, sink)
node _T_994 = asUInt(reset)
node _T_995 = eq(_T_994, UInt<1>(0h0))
when _T_995 :
node _T_996 = eq(_T_993, UInt<1>(0h0))
when _T_996 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_993, UInt<1>(0h1), "") : assert_96
node _T_997 = eq(io.in.d.bits.denied, denied)
node _T_998 = asUInt(reset)
node _T_999 = eq(_T_998, UInt<1>(0h0))
when _T_999 :
node _T_1000 = eq(_T_997, UInt<1>(0h0))
when _T_1000 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_997, UInt<1>(0h1), "") : assert_97
node _T_1001 = and(io.in.d.ready, io.in.d.valid)
node _T_1002 = and(_T_1001, d_first)
when _T_1002 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1>
connect a_set, UInt<1>(0h0)
wire a_set_wo_ready : UInt<1>
connect a_set_wo_ready, UInt<1>(0h0)
wire a_opcodes_set : UInt<4>
connect a_opcodes_set, UInt<4>(0h0)
wire a_sizes_set : UInt<8>
connect a_sizes_set, UInt<8>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1003 = and(io.in.a.valid, a_first_1)
node _T_1004 = and(_T_1003, UInt<1>(0h1))
when _T_1004 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1005 = and(io.in.a.ready, io.in.a.valid)
node _T_1006 = and(_T_1005, a_first_1)
node _T_1007 = and(_T_1006, UInt<1>(0h1))
when _T_1007 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1008 = dshr(inflight, io.in.a.bits.source)
node _T_1009 = bits(_T_1008, 0, 0)
node _T_1010 = eq(_T_1009, UInt<1>(0h0))
node _T_1011 = asUInt(reset)
node _T_1012 = eq(_T_1011, UInt<1>(0h0))
when _T_1012 :
node _T_1013 = eq(_T_1010, UInt<1>(0h0))
when _T_1013 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1010, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1>
connect d_clr, UInt<1>(0h0)
wire d_clr_wo_ready : UInt<1>
connect d_clr_wo_ready, UInt<1>(0h0)
wire d_opcodes_clr : UInt<4>
connect d_opcodes_clr, UInt<4>(0h0)
wire d_sizes_clr : UInt<8>
connect d_sizes_clr, UInt<8>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1014 = and(io.in.d.valid, d_first_1)
node _T_1015 = and(_T_1014, UInt<1>(0h1))
node _T_1016 = eq(d_release_ack, UInt<1>(0h0))
node _T_1017 = and(_T_1015, _T_1016)
when _T_1017 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1018 = and(io.in.d.ready, io.in.d.valid)
node _T_1019 = and(_T_1018, d_first_1)
node _T_1020 = and(_T_1019, UInt<1>(0h1))
node _T_1021 = eq(d_release_ack, UInt<1>(0h0))
node _T_1022 = and(_T_1020, _T_1021)
when _T_1022 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1023 = and(io.in.d.valid, d_first_1)
node _T_1024 = and(_T_1023, UInt<1>(0h1))
node _T_1025 = eq(d_release_ack, UInt<1>(0h0))
node _T_1026 = and(_T_1024, _T_1025)
when _T_1026 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1027 = dshr(inflight, io.in.d.bits.source)
node _T_1028 = bits(_T_1027, 0, 0)
node _T_1029 = or(_T_1028, same_cycle_resp)
node _T_1030 = asUInt(reset)
node _T_1031 = eq(_T_1030, UInt<1>(0h0))
when _T_1031 :
node _T_1032 = eq(_T_1029, UInt<1>(0h0))
when _T_1032 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1029, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1033 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1034 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1035 = or(_T_1033, _T_1034)
node _T_1036 = asUInt(reset)
node _T_1037 = eq(_T_1036, UInt<1>(0h0))
when _T_1037 :
node _T_1038 = eq(_T_1035, UInt<1>(0h0))
when _T_1038 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1035, UInt<1>(0h1), "") : assert_100
node _T_1039 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1040 = asUInt(reset)
node _T_1041 = eq(_T_1040, UInt<1>(0h0))
when _T_1041 :
node _T_1042 = eq(_T_1039, UInt<1>(0h0))
when _T_1042 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1039, UInt<1>(0h1), "") : assert_101
else :
node _T_1043 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1044 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1045 = or(_T_1043, _T_1044)
node _T_1046 = asUInt(reset)
node _T_1047 = eq(_T_1046, UInt<1>(0h0))
when _T_1047 :
node _T_1048 = eq(_T_1045, UInt<1>(0h0))
when _T_1048 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1045, UInt<1>(0h1), "") : assert_102
node _T_1049 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1050 = asUInt(reset)
node _T_1051 = eq(_T_1050, UInt<1>(0h0))
when _T_1051 :
node _T_1052 = eq(_T_1049, UInt<1>(0h0))
when _T_1052 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1049, UInt<1>(0h1), "") : assert_103
node _T_1053 = and(io.in.d.valid, d_first_1)
node _T_1054 = and(_T_1053, a_first_1)
node _T_1055 = and(_T_1054, io.in.a.valid)
node _T_1056 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1057 = and(_T_1055, _T_1056)
node _T_1058 = eq(d_release_ack, UInt<1>(0h0))
node _T_1059 = and(_T_1057, _T_1058)
when _T_1059 :
node _T_1060 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1061 = or(_T_1060, io.in.a.ready)
node _T_1062 = asUInt(reset)
node _T_1063 = eq(_T_1062, UInt<1>(0h0))
when _T_1063 :
node _T_1064 = eq(_T_1061, UInt<1>(0h0))
when _T_1064 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1061, UInt<1>(0h1), "") : assert_104
node _T_1065 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1066 = orr(a_set_wo_ready)
node _T_1067 = eq(_T_1066, UInt<1>(0h0))
node _T_1068 = or(_T_1065, _T_1067)
node _T_1069 = asUInt(reset)
node _T_1070 = eq(_T_1069, UInt<1>(0h0))
when _T_1070 :
node _T_1071 = eq(_T_1068, UInt<1>(0h0))
when _T_1071 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1068, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_98
node _T_1072 = orr(inflight)
node _T_1073 = eq(_T_1072, UInt<1>(0h0))
node _T_1074 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1075 = or(_T_1073, _T_1074)
node _T_1076 = lt(watchdog, plusarg_reader.out)
node _T_1077 = or(_T_1075, _T_1076)
node _T_1078 = asUInt(reset)
node _T_1079 = eq(_T_1078, UInt<1>(0h0))
when _T_1079 :
node _T_1080 = eq(_T_1077, UInt<1>(0h0))
when _T_1080 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1077, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1081 = and(io.in.a.ready, io.in.a.valid)
node _T_1082 = and(io.in.d.ready, io.in.d.valid)
node _T_1083 = or(_T_1081, _T_1082)
when _T_1083 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<1>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1>
connect c_set, UInt<1>(0h0)
wire c_set_wo_ready : UInt<1>
connect c_set_wo_ready, UInt<1>(0h0)
wire c_opcodes_set : UInt<4>
connect c_opcodes_set, UInt<4>(0h0)
wire c_sizes_set : UInt<8>
connect c_sizes_set, UInt<8>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1084 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1085 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1086 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1087 = and(_T_1085, _T_1086)
node _T_1088 = and(_T_1084, _T_1087)
when _T_1088 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<1>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1089 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1090 = and(_T_1089, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<1>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1091 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1092 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1093 = and(_T_1091, _T_1092)
node _T_1094 = and(_T_1090, _T_1093)
when _T_1094 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<1>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1095 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1096 = bits(_T_1095, 0, 0)
node _T_1097 = eq(_T_1096, UInt<1>(0h0))
node _T_1098 = asUInt(reset)
node _T_1099 = eq(_T_1098, UInt<1>(0h0))
when _T_1099 :
node _T_1100 = eq(_T_1097, UInt<1>(0h0))
when _T_1100 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1097, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1>
connect d_clr_1, UInt<1>(0h0)
wire d_clr_wo_ready_1 : UInt<1>
connect d_clr_wo_ready_1, UInt<1>(0h0)
wire d_opcodes_clr_1 : UInt<4>
connect d_opcodes_clr_1, UInt<4>(0h0)
wire d_sizes_clr_1 : UInt<8>
connect d_sizes_clr_1, UInt<8>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1101 = and(io.in.d.valid, d_first_2)
node _T_1102 = and(_T_1101, UInt<1>(0h1))
node _T_1103 = and(_T_1102, d_release_ack_1)
when _T_1103 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1104 = and(io.in.d.ready, io.in.d.valid)
node _T_1105 = and(_T_1104, d_first_2)
node _T_1106 = and(_T_1105, UInt<1>(0h1))
node _T_1107 = and(_T_1106, d_release_ack_1)
when _T_1107 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1108 = and(io.in.d.valid, d_first_2)
node _T_1109 = and(_T_1108, UInt<1>(0h1))
node _T_1110 = and(_T_1109, d_release_ack_1)
when _T_1110 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1111 = dshr(inflight_1, io.in.d.bits.source)
node _T_1112 = bits(_T_1111, 0, 0)
node _T_1113 = or(_T_1112, same_cycle_resp_1)
node _T_1114 = asUInt(reset)
node _T_1115 = eq(_T_1114, UInt<1>(0h0))
when _T_1115 :
node _T_1116 = eq(_T_1113, UInt<1>(0h0))
when _T_1116 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1113, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<1>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1117 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1118 = asUInt(reset)
node _T_1119 = eq(_T_1118, UInt<1>(0h0))
when _T_1119 :
node _T_1120 = eq(_T_1117, UInt<1>(0h0))
when _T_1120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1117, UInt<1>(0h1), "") : assert_109
else :
node _T_1121 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1122 = asUInt(reset)
node _T_1123 = eq(_T_1122, UInt<1>(0h0))
when _T_1123 :
node _T_1124 = eq(_T_1121, UInt<1>(0h0))
when _T_1124 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1121, UInt<1>(0h1), "") : assert_110
node _T_1125 = and(io.in.d.valid, d_first_2)
node _T_1126 = and(_T_1125, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<1>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1127 = and(_T_1126, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<1>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1128 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1129 = and(_T_1127, _T_1128)
node _T_1130 = and(_T_1129, d_release_ack_1)
node _T_1131 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1132 = and(_T_1130, _T_1131)
when _T_1132 :
node _T_1133 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<1>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1134 = or(_T_1133, _WIRE_23.ready)
node _T_1135 = asUInt(reset)
node _T_1136 = eq(_T_1135, UInt<1>(0h0))
when _T_1136 :
node _T_1137 = eq(_T_1134, UInt<1>(0h0))
when _T_1137 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1134, UInt<1>(0h1), "") : assert_111
node _T_1138 = orr(c_set_wo_ready)
when _T_1138 :
node _T_1139 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1140 = asUInt(reset)
node _T_1141 = eq(_T_1140, UInt<1>(0h0))
when _T_1141 :
node _T_1142 = eq(_T_1139, UInt<1>(0h0))
when _T_1142 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1139, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_99
node _T_1143 = orr(inflight_1)
node _T_1144 = eq(_T_1143, UInt<1>(0h0))
node _T_1145 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1146 = or(_T_1144, _T_1145)
node _T_1147 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1148 = or(_T_1146, _T_1147)
node _T_1149 = asUInt(reset)
node _T_1150 = eq(_T_1149, UInt<1>(0h0))
when _T_1150 :
node _T_1151 = eq(_T_1148, UInt<1>(0h0))
when _T_1151 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1148, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<1>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1152 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1153 = and(io.in.d.ready, io.in.d.valid)
node _T_1154 = or(_T_1152, _T_1153)
when _T_1154 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_46( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire c_set = 1'h0; // @[Monitor.scala:738:34]
wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52]
wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31]
wire _T_1081 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1081; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1081; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1154 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1154; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1154; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1154; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [7:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire a_set; // @[Monitor.scala:626:34]
wire a_set_wo_ready; // @[Monitor.scala:627:34]
wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [7:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [3:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [3:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [7:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}]
wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [1:0] _GEN_3 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35]
wire [1:0] _GEN_4 = 2'h1 << _GEN_3; // @[OneHot.scala:58:35]
wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35]
wire [1:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T & _a_set_wo_ready_T[0]; // @[OneHot.scala:58:35]
wire _T_1007 = _T_1081 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1007 & _a_set_T[0]; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1007 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1007 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1007 ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :660:{52,77}]
assign a_sizes_set = _T_1007 ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire d_clr; // @[Monitor.scala:664:34]
wire d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46]
wire _T_1053 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [1:0] _GEN_6 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [1:0] _GEN_7 = 2'h1 << _GEN_6; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1053 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35]
wire _T_1022 = _T_1154 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1022 & _d_clr_T[0]; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1022 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1022 ? _d_sizes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27]
wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}]
wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}]
wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire d_clr_1; // @[Monitor.scala:774:34]
wire d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1125 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1125 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35]
wire _T_1107 = _T_1154 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1107 & _d_clr_T_1[0]; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1107 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1107 ? _d_sizes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113]
wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}]
wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module ALUExeUnit_1 :
input clock : Clock
input reset : Reset
output io : { fu_types : UInt<10>, flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, rs1_data : UInt<65>, rs2_data : UInt<65>, rs3_data : UInt<65>, pred_data : UInt<1>, kill : UInt<1>}}, iresp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}, ll_fresp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}, bypass : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}[3], flip brupdate : { b1 : { resolve_mask : UInt<8>, mispredict_mask : UInt<8>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, brinfo : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}, flip get_ftq_pc : { flip ftq_idx : UInt<4>, entry : { cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_type : UInt<3>, br_mask : UInt<4>, cfi_is_call : UInt<1>, cfi_is_ret : UInt<1>, cfi_npc_plus4 : UInt<1>, ras_top : UInt<40>, ras_idx : UInt<5>, start_bank : UInt<1>}, ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>}, pc : UInt<40>, com_pc : UInt<40>, next_val : UInt<1>, next_pc : UInt<40>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip fcsr_rm : UInt<3>}
connect io.req.ready, UInt<1>(0h0)
connect io.iresp.valid, UInt<1>(0h0)
invalidate io.iresp.bits.fflags.bits.flags
invalidate io.iresp.bits.fflags.bits.uop.debug_tsrc
invalidate io.iresp.bits.fflags.bits.uop.debug_fsrc
invalidate io.iresp.bits.fflags.bits.uop.bp_xcpt_if
invalidate io.iresp.bits.fflags.bits.uop.bp_debug_if
invalidate io.iresp.bits.fflags.bits.uop.xcpt_ma_if
invalidate io.iresp.bits.fflags.bits.uop.xcpt_ae_if
invalidate io.iresp.bits.fflags.bits.uop.xcpt_pf_if
invalidate io.iresp.bits.fflags.bits.uop.fp_single
invalidate io.iresp.bits.fflags.bits.uop.fp_val
invalidate io.iresp.bits.fflags.bits.uop.frs3_en
invalidate io.iresp.bits.fflags.bits.uop.lrs2_rtype
invalidate io.iresp.bits.fflags.bits.uop.lrs1_rtype
invalidate io.iresp.bits.fflags.bits.uop.dst_rtype
invalidate io.iresp.bits.fflags.bits.uop.ldst_val
invalidate io.iresp.bits.fflags.bits.uop.lrs3
invalidate io.iresp.bits.fflags.bits.uop.lrs2
invalidate io.iresp.bits.fflags.bits.uop.lrs1
invalidate io.iresp.bits.fflags.bits.uop.ldst
invalidate io.iresp.bits.fflags.bits.uop.ldst_is_rs1
invalidate io.iresp.bits.fflags.bits.uop.flush_on_commit
invalidate io.iresp.bits.fflags.bits.uop.is_unique
invalidate io.iresp.bits.fflags.bits.uop.is_sys_pc2epc
invalidate io.iresp.bits.fflags.bits.uop.uses_stq
invalidate io.iresp.bits.fflags.bits.uop.uses_ldq
invalidate io.iresp.bits.fflags.bits.uop.is_amo
invalidate io.iresp.bits.fflags.bits.uop.is_fencei
invalidate io.iresp.bits.fflags.bits.uop.is_fence
invalidate io.iresp.bits.fflags.bits.uop.mem_signed
invalidate io.iresp.bits.fflags.bits.uop.mem_size
invalidate io.iresp.bits.fflags.bits.uop.mem_cmd
invalidate io.iresp.bits.fflags.bits.uop.bypassable
invalidate io.iresp.bits.fflags.bits.uop.exc_cause
invalidate io.iresp.bits.fflags.bits.uop.exception
invalidate io.iresp.bits.fflags.bits.uop.stale_pdst
invalidate io.iresp.bits.fflags.bits.uop.ppred_busy
invalidate io.iresp.bits.fflags.bits.uop.prs3_busy
invalidate io.iresp.bits.fflags.bits.uop.prs2_busy
invalidate io.iresp.bits.fflags.bits.uop.prs1_busy
invalidate io.iresp.bits.fflags.bits.uop.ppred
invalidate io.iresp.bits.fflags.bits.uop.prs3
invalidate io.iresp.bits.fflags.bits.uop.prs2
invalidate io.iresp.bits.fflags.bits.uop.prs1
invalidate io.iresp.bits.fflags.bits.uop.pdst
invalidate io.iresp.bits.fflags.bits.uop.rxq_idx
invalidate io.iresp.bits.fflags.bits.uop.stq_idx
invalidate io.iresp.bits.fflags.bits.uop.ldq_idx
invalidate io.iresp.bits.fflags.bits.uop.rob_idx
invalidate io.iresp.bits.fflags.bits.uop.csr_addr
invalidate io.iresp.bits.fflags.bits.uop.imm_packed
invalidate io.iresp.bits.fflags.bits.uop.taken
invalidate io.iresp.bits.fflags.bits.uop.pc_lob
invalidate io.iresp.bits.fflags.bits.uop.edge_inst
invalidate io.iresp.bits.fflags.bits.uop.ftq_idx
invalidate io.iresp.bits.fflags.bits.uop.br_tag
invalidate io.iresp.bits.fflags.bits.uop.br_mask
invalidate io.iresp.bits.fflags.bits.uop.is_sfb
invalidate io.iresp.bits.fflags.bits.uop.is_jal
invalidate io.iresp.bits.fflags.bits.uop.is_jalr
invalidate io.iresp.bits.fflags.bits.uop.is_br
invalidate io.iresp.bits.fflags.bits.uop.iw_p2_poisoned
invalidate io.iresp.bits.fflags.bits.uop.iw_p1_poisoned
invalidate io.iresp.bits.fflags.bits.uop.iw_state
invalidate io.iresp.bits.fflags.bits.uop.ctrl.is_std
invalidate io.iresp.bits.fflags.bits.uop.ctrl.is_sta
invalidate io.iresp.bits.fflags.bits.uop.ctrl.is_load
invalidate io.iresp.bits.fflags.bits.uop.ctrl.csr_cmd
invalidate io.iresp.bits.fflags.bits.uop.ctrl.fcn_dw
invalidate io.iresp.bits.fflags.bits.uop.ctrl.op_fcn
invalidate io.iresp.bits.fflags.bits.uop.ctrl.imm_sel
invalidate io.iresp.bits.fflags.bits.uop.ctrl.op2_sel
invalidate io.iresp.bits.fflags.bits.uop.ctrl.op1_sel
invalidate io.iresp.bits.fflags.bits.uop.ctrl.br_type
invalidate io.iresp.bits.fflags.bits.uop.fu_code
invalidate io.iresp.bits.fflags.bits.uop.iq_type
invalidate io.iresp.bits.fflags.bits.uop.debug_pc
invalidate io.iresp.bits.fflags.bits.uop.is_rvc
invalidate io.iresp.bits.fflags.bits.uop.debug_inst
invalidate io.iresp.bits.fflags.bits.uop.inst
invalidate io.iresp.bits.fflags.bits.uop.uopc
invalidate io.iresp.bits.fflags.valid
invalidate io.iresp.bits.predicated
invalidate io.iresp.bits.data
invalidate io.iresp.bits.uop.debug_tsrc
invalidate io.iresp.bits.uop.debug_fsrc
invalidate io.iresp.bits.uop.bp_xcpt_if
invalidate io.iresp.bits.uop.bp_debug_if
invalidate io.iresp.bits.uop.xcpt_ma_if
invalidate io.iresp.bits.uop.xcpt_ae_if
invalidate io.iresp.bits.uop.xcpt_pf_if
invalidate io.iresp.bits.uop.fp_single
invalidate io.iresp.bits.uop.fp_val
invalidate io.iresp.bits.uop.frs3_en
invalidate io.iresp.bits.uop.lrs2_rtype
invalidate io.iresp.bits.uop.lrs1_rtype
invalidate io.iresp.bits.uop.dst_rtype
invalidate io.iresp.bits.uop.ldst_val
invalidate io.iresp.bits.uop.lrs3
invalidate io.iresp.bits.uop.lrs2
invalidate io.iresp.bits.uop.lrs1
invalidate io.iresp.bits.uop.ldst
invalidate io.iresp.bits.uop.ldst_is_rs1
invalidate io.iresp.bits.uop.flush_on_commit
invalidate io.iresp.bits.uop.is_unique
invalidate io.iresp.bits.uop.is_sys_pc2epc
invalidate io.iresp.bits.uop.uses_stq
invalidate io.iresp.bits.uop.uses_ldq
invalidate io.iresp.bits.uop.is_amo
invalidate io.iresp.bits.uop.is_fencei
invalidate io.iresp.bits.uop.is_fence
invalidate io.iresp.bits.uop.mem_signed
invalidate io.iresp.bits.uop.mem_size
invalidate io.iresp.bits.uop.mem_cmd
invalidate io.iresp.bits.uop.bypassable
invalidate io.iresp.bits.uop.exc_cause
invalidate io.iresp.bits.uop.exception
invalidate io.iresp.bits.uop.stale_pdst
invalidate io.iresp.bits.uop.ppred_busy
invalidate io.iresp.bits.uop.prs3_busy
invalidate io.iresp.bits.uop.prs2_busy
invalidate io.iresp.bits.uop.prs1_busy
invalidate io.iresp.bits.uop.ppred
invalidate io.iresp.bits.uop.prs3
invalidate io.iresp.bits.uop.prs2
invalidate io.iresp.bits.uop.prs1
invalidate io.iresp.bits.uop.pdst
invalidate io.iresp.bits.uop.rxq_idx
invalidate io.iresp.bits.uop.stq_idx
invalidate io.iresp.bits.uop.ldq_idx
invalidate io.iresp.bits.uop.rob_idx
invalidate io.iresp.bits.uop.csr_addr
invalidate io.iresp.bits.uop.imm_packed
invalidate io.iresp.bits.uop.taken
invalidate io.iresp.bits.uop.pc_lob
invalidate io.iresp.bits.uop.edge_inst
invalidate io.iresp.bits.uop.ftq_idx
invalidate io.iresp.bits.uop.br_tag
invalidate io.iresp.bits.uop.br_mask
invalidate io.iresp.bits.uop.is_sfb
invalidate io.iresp.bits.uop.is_jal
invalidate io.iresp.bits.uop.is_jalr
invalidate io.iresp.bits.uop.is_br
invalidate io.iresp.bits.uop.iw_p2_poisoned
invalidate io.iresp.bits.uop.iw_p1_poisoned
invalidate io.iresp.bits.uop.iw_state
invalidate io.iresp.bits.uop.ctrl.is_std
invalidate io.iresp.bits.uop.ctrl.is_sta
invalidate io.iresp.bits.uop.ctrl.is_load
invalidate io.iresp.bits.uop.ctrl.csr_cmd
invalidate io.iresp.bits.uop.ctrl.fcn_dw
invalidate io.iresp.bits.uop.ctrl.op_fcn
invalidate io.iresp.bits.uop.ctrl.imm_sel
invalidate io.iresp.bits.uop.ctrl.op2_sel
invalidate io.iresp.bits.uop.ctrl.op1_sel
invalidate io.iresp.bits.uop.ctrl.br_type
invalidate io.iresp.bits.uop.fu_code
invalidate io.iresp.bits.uop.iq_type
invalidate io.iresp.bits.uop.debug_pc
invalidate io.iresp.bits.uop.is_rvc
invalidate io.iresp.bits.uop.debug_inst
invalidate io.iresp.bits.uop.inst
invalidate io.iresp.bits.uop.uopc
connect io.iresp.bits.fflags.valid, UInt<1>(0h0)
connect io.iresp.bits.predicated, UInt<1>(0h0)
node _T = asUInt(reset)
node _T_1 = eq(_T, UInt<1>(0h0))
when _T_1 :
node _T_2 = eq(io.iresp.ready, UInt<1>(0h0))
when _T_2 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at execution-unit.scala:147 assert(io.iresp.ready)\n") : printf
assert(clock, io.iresp.ready, UInt<1>(0h1), "") : assert
connect io.ll_fresp.valid, UInt<1>(0h0)
invalidate io.ll_fresp.bits.fflags.bits.flags
invalidate io.ll_fresp.bits.fflags.bits.uop.debug_tsrc
invalidate io.ll_fresp.bits.fflags.bits.uop.debug_fsrc
invalidate io.ll_fresp.bits.fflags.bits.uop.bp_xcpt_if
invalidate io.ll_fresp.bits.fflags.bits.uop.bp_debug_if
invalidate io.ll_fresp.bits.fflags.bits.uop.xcpt_ma_if
invalidate io.ll_fresp.bits.fflags.bits.uop.xcpt_ae_if
invalidate io.ll_fresp.bits.fflags.bits.uop.xcpt_pf_if
invalidate io.ll_fresp.bits.fflags.bits.uop.fp_single
invalidate io.ll_fresp.bits.fflags.bits.uop.fp_val
invalidate io.ll_fresp.bits.fflags.bits.uop.frs3_en
invalidate io.ll_fresp.bits.fflags.bits.uop.lrs2_rtype
invalidate io.ll_fresp.bits.fflags.bits.uop.lrs1_rtype
invalidate io.ll_fresp.bits.fflags.bits.uop.dst_rtype
invalidate io.ll_fresp.bits.fflags.bits.uop.ldst_val
invalidate io.ll_fresp.bits.fflags.bits.uop.lrs3
invalidate io.ll_fresp.bits.fflags.bits.uop.lrs2
invalidate io.ll_fresp.bits.fflags.bits.uop.lrs1
invalidate io.ll_fresp.bits.fflags.bits.uop.ldst
invalidate io.ll_fresp.bits.fflags.bits.uop.ldst_is_rs1
invalidate io.ll_fresp.bits.fflags.bits.uop.flush_on_commit
invalidate io.ll_fresp.bits.fflags.bits.uop.is_unique
invalidate io.ll_fresp.bits.fflags.bits.uop.is_sys_pc2epc
invalidate io.ll_fresp.bits.fflags.bits.uop.uses_stq
invalidate io.ll_fresp.bits.fflags.bits.uop.uses_ldq
invalidate io.ll_fresp.bits.fflags.bits.uop.is_amo
invalidate io.ll_fresp.bits.fflags.bits.uop.is_fencei
invalidate io.ll_fresp.bits.fflags.bits.uop.is_fence
invalidate io.ll_fresp.bits.fflags.bits.uop.mem_signed
invalidate io.ll_fresp.bits.fflags.bits.uop.mem_size
invalidate io.ll_fresp.bits.fflags.bits.uop.mem_cmd
invalidate io.ll_fresp.bits.fflags.bits.uop.bypassable
invalidate io.ll_fresp.bits.fflags.bits.uop.exc_cause
invalidate io.ll_fresp.bits.fflags.bits.uop.exception
invalidate io.ll_fresp.bits.fflags.bits.uop.stale_pdst
invalidate io.ll_fresp.bits.fflags.bits.uop.ppred_busy
invalidate io.ll_fresp.bits.fflags.bits.uop.prs3_busy
invalidate io.ll_fresp.bits.fflags.bits.uop.prs2_busy
invalidate io.ll_fresp.bits.fflags.bits.uop.prs1_busy
invalidate io.ll_fresp.bits.fflags.bits.uop.ppred
invalidate io.ll_fresp.bits.fflags.bits.uop.prs3
invalidate io.ll_fresp.bits.fflags.bits.uop.prs2
invalidate io.ll_fresp.bits.fflags.bits.uop.prs1
invalidate io.ll_fresp.bits.fflags.bits.uop.pdst
invalidate io.ll_fresp.bits.fflags.bits.uop.rxq_idx
invalidate io.ll_fresp.bits.fflags.bits.uop.stq_idx
invalidate io.ll_fresp.bits.fflags.bits.uop.ldq_idx
invalidate io.ll_fresp.bits.fflags.bits.uop.rob_idx
invalidate io.ll_fresp.bits.fflags.bits.uop.csr_addr
invalidate io.ll_fresp.bits.fflags.bits.uop.imm_packed
invalidate io.ll_fresp.bits.fflags.bits.uop.taken
invalidate io.ll_fresp.bits.fflags.bits.uop.pc_lob
invalidate io.ll_fresp.bits.fflags.bits.uop.edge_inst
invalidate io.ll_fresp.bits.fflags.bits.uop.ftq_idx
invalidate io.ll_fresp.bits.fflags.bits.uop.br_tag
invalidate io.ll_fresp.bits.fflags.bits.uop.br_mask
invalidate io.ll_fresp.bits.fflags.bits.uop.is_sfb
invalidate io.ll_fresp.bits.fflags.bits.uop.is_jal
invalidate io.ll_fresp.bits.fflags.bits.uop.is_jalr
invalidate io.ll_fresp.bits.fflags.bits.uop.is_br
invalidate io.ll_fresp.bits.fflags.bits.uop.iw_p2_poisoned
invalidate io.ll_fresp.bits.fflags.bits.uop.iw_p1_poisoned
invalidate io.ll_fresp.bits.fflags.bits.uop.iw_state
invalidate io.ll_fresp.bits.fflags.bits.uop.ctrl.is_std
invalidate io.ll_fresp.bits.fflags.bits.uop.ctrl.is_sta
invalidate io.ll_fresp.bits.fflags.bits.uop.ctrl.is_load
invalidate io.ll_fresp.bits.fflags.bits.uop.ctrl.csr_cmd
invalidate io.ll_fresp.bits.fflags.bits.uop.ctrl.fcn_dw
invalidate io.ll_fresp.bits.fflags.bits.uop.ctrl.op_fcn
invalidate io.ll_fresp.bits.fflags.bits.uop.ctrl.imm_sel
invalidate io.ll_fresp.bits.fflags.bits.uop.ctrl.op2_sel
invalidate io.ll_fresp.bits.fflags.bits.uop.ctrl.op1_sel
invalidate io.ll_fresp.bits.fflags.bits.uop.ctrl.br_type
invalidate io.ll_fresp.bits.fflags.bits.uop.fu_code
invalidate io.ll_fresp.bits.fflags.bits.uop.iq_type
invalidate io.ll_fresp.bits.fflags.bits.uop.debug_pc
invalidate io.ll_fresp.bits.fflags.bits.uop.is_rvc
invalidate io.ll_fresp.bits.fflags.bits.uop.debug_inst
invalidate io.ll_fresp.bits.fflags.bits.uop.inst
invalidate io.ll_fresp.bits.fflags.bits.uop.uopc
invalidate io.ll_fresp.bits.fflags.valid
invalidate io.ll_fresp.bits.predicated
invalidate io.ll_fresp.bits.data
invalidate io.ll_fresp.bits.uop.debug_tsrc
invalidate io.ll_fresp.bits.uop.debug_fsrc
invalidate io.ll_fresp.bits.uop.bp_xcpt_if
invalidate io.ll_fresp.bits.uop.bp_debug_if
invalidate io.ll_fresp.bits.uop.xcpt_ma_if
invalidate io.ll_fresp.bits.uop.xcpt_ae_if
invalidate io.ll_fresp.bits.uop.xcpt_pf_if
invalidate io.ll_fresp.bits.uop.fp_single
invalidate io.ll_fresp.bits.uop.fp_val
invalidate io.ll_fresp.bits.uop.frs3_en
invalidate io.ll_fresp.bits.uop.lrs2_rtype
invalidate io.ll_fresp.bits.uop.lrs1_rtype
invalidate io.ll_fresp.bits.uop.dst_rtype
invalidate io.ll_fresp.bits.uop.ldst_val
invalidate io.ll_fresp.bits.uop.lrs3
invalidate io.ll_fresp.bits.uop.lrs2
invalidate io.ll_fresp.bits.uop.lrs1
invalidate io.ll_fresp.bits.uop.ldst
invalidate io.ll_fresp.bits.uop.ldst_is_rs1
invalidate io.ll_fresp.bits.uop.flush_on_commit
invalidate io.ll_fresp.bits.uop.is_unique
invalidate io.ll_fresp.bits.uop.is_sys_pc2epc
invalidate io.ll_fresp.bits.uop.uses_stq
invalidate io.ll_fresp.bits.uop.uses_ldq
invalidate io.ll_fresp.bits.uop.is_amo
invalidate io.ll_fresp.bits.uop.is_fencei
invalidate io.ll_fresp.bits.uop.is_fence
invalidate io.ll_fresp.bits.uop.mem_signed
invalidate io.ll_fresp.bits.uop.mem_size
invalidate io.ll_fresp.bits.uop.mem_cmd
invalidate io.ll_fresp.bits.uop.bypassable
invalidate io.ll_fresp.bits.uop.exc_cause
invalidate io.ll_fresp.bits.uop.exception
invalidate io.ll_fresp.bits.uop.stale_pdst
invalidate io.ll_fresp.bits.uop.ppred_busy
invalidate io.ll_fresp.bits.uop.prs3_busy
invalidate io.ll_fresp.bits.uop.prs2_busy
invalidate io.ll_fresp.bits.uop.prs1_busy
invalidate io.ll_fresp.bits.uop.ppred
invalidate io.ll_fresp.bits.uop.prs3
invalidate io.ll_fresp.bits.uop.prs2
invalidate io.ll_fresp.bits.uop.prs1
invalidate io.ll_fresp.bits.uop.pdst
invalidate io.ll_fresp.bits.uop.rxq_idx
invalidate io.ll_fresp.bits.uop.stq_idx
invalidate io.ll_fresp.bits.uop.ldq_idx
invalidate io.ll_fresp.bits.uop.rob_idx
invalidate io.ll_fresp.bits.uop.csr_addr
invalidate io.ll_fresp.bits.uop.imm_packed
invalidate io.ll_fresp.bits.uop.taken
invalidate io.ll_fresp.bits.uop.pc_lob
invalidate io.ll_fresp.bits.uop.edge_inst
invalidate io.ll_fresp.bits.uop.ftq_idx
invalidate io.ll_fresp.bits.uop.br_tag
invalidate io.ll_fresp.bits.uop.br_mask
invalidate io.ll_fresp.bits.uop.is_sfb
invalidate io.ll_fresp.bits.uop.is_jal
invalidate io.ll_fresp.bits.uop.is_jalr
invalidate io.ll_fresp.bits.uop.is_br
invalidate io.ll_fresp.bits.uop.iw_p2_poisoned
invalidate io.ll_fresp.bits.uop.iw_p1_poisoned
invalidate io.ll_fresp.bits.uop.iw_state
invalidate io.ll_fresp.bits.uop.ctrl.is_std
invalidate io.ll_fresp.bits.uop.ctrl.is_sta
invalidate io.ll_fresp.bits.uop.ctrl.is_load
invalidate io.ll_fresp.bits.uop.ctrl.csr_cmd
invalidate io.ll_fresp.bits.uop.ctrl.fcn_dw
invalidate io.ll_fresp.bits.uop.ctrl.op_fcn
invalidate io.ll_fresp.bits.uop.ctrl.imm_sel
invalidate io.ll_fresp.bits.uop.ctrl.op2_sel
invalidate io.ll_fresp.bits.uop.ctrl.op1_sel
invalidate io.ll_fresp.bits.uop.ctrl.br_type
invalidate io.ll_fresp.bits.uop.fu_code
invalidate io.ll_fresp.bits.uop.iq_type
invalidate io.ll_fresp.bits.uop.debug_pc
invalidate io.ll_fresp.bits.uop.is_rvc
invalidate io.ll_fresp.bits.uop.debug_inst
invalidate io.ll_fresp.bits.uop.inst
invalidate io.ll_fresp.bits.uop.uopc
connect io.ll_fresp.bits.fflags.valid, UInt<1>(0h0)
connect io.ll_fresp.bits.predicated, UInt<1>(0h0)
wire div_busy : UInt<1>
connect div_busy, UInt<1>(0h0)
wire ifpu_busy : UInt<1>
connect ifpu_busy, UInt<1>(0h0)
node _io_fu_types_T = mux(UInt<1>(0h1), UInt<10>(0h1), UInt<1>(0h0))
node _io_fu_types_T_1 = mux(UInt<1>(0h1), UInt<10>(0h8), UInt<1>(0h0))
node _io_fu_types_T_2 = or(_io_fu_types_T, _io_fu_types_T_1)
node _io_fu_types_T_3 = eq(div_busy, UInt<1>(0h0))
node _io_fu_types_T_4 = and(_io_fu_types_T_3, UInt<1>(0h1))
node _io_fu_types_T_5 = mux(_io_fu_types_T_4, UInt<10>(0h10), UInt<1>(0h0))
node _io_fu_types_T_6 = or(_io_fu_types_T_2, _io_fu_types_T_5)
node _io_fu_types_T_7 = mux(UInt<1>(0h1), UInt<10>(0h20), UInt<1>(0h0))
node _io_fu_types_T_8 = or(_io_fu_types_T_6, _io_fu_types_T_7)
node _io_fu_types_T_9 = mux(UInt<1>(0h1), UInt<10>(0h2), UInt<1>(0h0))
node _io_fu_types_T_10 = or(_io_fu_types_T_8, _io_fu_types_T_9)
node _io_fu_types_T_11 = eq(ifpu_busy, UInt<1>(0h0))
node _io_fu_types_T_12 = and(_io_fu_types_T_11, UInt<1>(0h1))
node _io_fu_types_T_13 = mux(_io_fu_types_T_12, UInt<10>(0h100), UInt<1>(0h0))
node _io_fu_types_T_14 = or(_io_fu_types_T_10, _io_fu_types_T_13)
node _io_fu_types_T_15 = mux(UInt<1>(0h0), UInt<10>(0h4), UInt<1>(0h0))
node _io_fu_types_T_16 = or(_io_fu_types_T_14, _io_fu_types_T_15)
connect io.fu_types, _io_fu_types_T_16
inst ALUUnit of ALUUnit
connect ALUUnit.clock, clock
connect ALUUnit.reset, reset
node _T_3 = eq(io.req.bits.uop.fu_code, UInt<10>(0h1))
node _T_4 = eq(io.req.bits.uop.fu_code, UInt<10>(0h2))
node _T_5 = or(_T_3, _T_4)
node _T_6 = eq(io.req.bits.uop.fu_code, UInt<10>(0h20))
node _T_7 = neq(io.req.bits.uop.uopc, UInt<7>(0h6c))
node _T_8 = and(_T_6, _T_7)
node _T_9 = or(_T_5, _T_8)
node _T_10 = and(io.req.valid, _T_9)
connect ALUUnit.io.req.valid, _T_10
connect ALUUnit.io.req.bits.uop.debug_tsrc, io.req.bits.uop.debug_tsrc
connect ALUUnit.io.req.bits.uop.debug_fsrc, io.req.bits.uop.debug_fsrc
connect ALUUnit.io.req.bits.uop.bp_xcpt_if, io.req.bits.uop.bp_xcpt_if
connect ALUUnit.io.req.bits.uop.bp_debug_if, io.req.bits.uop.bp_debug_if
connect ALUUnit.io.req.bits.uop.xcpt_ma_if, io.req.bits.uop.xcpt_ma_if
connect ALUUnit.io.req.bits.uop.xcpt_ae_if, io.req.bits.uop.xcpt_ae_if
connect ALUUnit.io.req.bits.uop.xcpt_pf_if, io.req.bits.uop.xcpt_pf_if
connect ALUUnit.io.req.bits.uop.fp_single, io.req.bits.uop.fp_single
connect ALUUnit.io.req.bits.uop.fp_val, io.req.bits.uop.fp_val
connect ALUUnit.io.req.bits.uop.frs3_en, io.req.bits.uop.frs3_en
connect ALUUnit.io.req.bits.uop.lrs2_rtype, io.req.bits.uop.lrs2_rtype
connect ALUUnit.io.req.bits.uop.lrs1_rtype, io.req.bits.uop.lrs1_rtype
connect ALUUnit.io.req.bits.uop.dst_rtype, io.req.bits.uop.dst_rtype
connect ALUUnit.io.req.bits.uop.ldst_val, io.req.bits.uop.ldst_val
connect ALUUnit.io.req.bits.uop.lrs3, io.req.bits.uop.lrs3
connect ALUUnit.io.req.bits.uop.lrs2, io.req.bits.uop.lrs2
connect ALUUnit.io.req.bits.uop.lrs1, io.req.bits.uop.lrs1
connect ALUUnit.io.req.bits.uop.ldst, io.req.bits.uop.ldst
connect ALUUnit.io.req.bits.uop.ldst_is_rs1, io.req.bits.uop.ldst_is_rs1
connect ALUUnit.io.req.bits.uop.flush_on_commit, io.req.bits.uop.flush_on_commit
connect ALUUnit.io.req.bits.uop.is_unique, io.req.bits.uop.is_unique
connect ALUUnit.io.req.bits.uop.is_sys_pc2epc, io.req.bits.uop.is_sys_pc2epc
connect ALUUnit.io.req.bits.uop.uses_stq, io.req.bits.uop.uses_stq
connect ALUUnit.io.req.bits.uop.uses_ldq, io.req.bits.uop.uses_ldq
connect ALUUnit.io.req.bits.uop.is_amo, io.req.bits.uop.is_amo
connect ALUUnit.io.req.bits.uop.is_fencei, io.req.bits.uop.is_fencei
connect ALUUnit.io.req.bits.uop.is_fence, io.req.bits.uop.is_fence
connect ALUUnit.io.req.bits.uop.mem_signed, io.req.bits.uop.mem_signed
connect ALUUnit.io.req.bits.uop.mem_size, io.req.bits.uop.mem_size
connect ALUUnit.io.req.bits.uop.mem_cmd, io.req.bits.uop.mem_cmd
connect ALUUnit.io.req.bits.uop.bypassable, io.req.bits.uop.bypassable
connect ALUUnit.io.req.bits.uop.exc_cause, io.req.bits.uop.exc_cause
connect ALUUnit.io.req.bits.uop.exception, io.req.bits.uop.exception
connect ALUUnit.io.req.bits.uop.stale_pdst, io.req.bits.uop.stale_pdst
connect ALUUnit.io.req.bits.uop.ppred_busy, io.req.bits.uop.ppred_busy
connect ALUUnit.io.req.bits.uop.prs3_busy, io.req.bits.uop.prs3_busy
connect ALUUnit.io.req.bits.uop.prs2_busy, io.req.bits.uop.prs2_busy
connect ALUUnit.io.req.bits.uop.prs1_busy, io.req.bits.uop.prs1_busy
connect ALUUnit.io.req.bits.uop.ppred, io.req.bits.uop.ppred
connect ALUUnit.io.req.bits.uop.prs3, io.req.bits.uop.prs3
connect ALUUnit.io.req.bits.uop.prs2, io.req.bits.uop.prs2
connect ALUUnit.io.req.bits.uop.prs1, io.req.bits.uop.prs1
connect ALUUnit.io.req.bits.uop.pdst, io.req.bits.uop.pdst
connect ALUUnit.io.req.bits.uop.rxq_idx, io.req.bits.uop.rxq_idx
connect ALUUnit.io.req.bits.uop.stq_idx, io.req.bits.uop.stq_idx
connect ALUUnit.io.req.bits.uop.ldq_idx, io.req.bits.uop.ldq_idx
connect ALUUnit.io.req.bits.uop.rob_idx, io.req.bits.uop.rob_idx
connect ALUUnit.io.req.bits.uop.csr_addr, io.req.bits.uop.csr_addr
connect ALUUnit.io.req.bits.uop.imm_packed, io.req.bits.uop.imm_packed
connect ALUUnit.io.req.bits.uop.taken, io.req.bits.uop.taken
connect ALUUnit.io.req.bits.uop.pc_lob, io.req.bits.uop.pc_lob
connect ALUUnit.io.req.bits.uop.edge_inst, io.req.bits.uop.edge_inst
connect ALUUnit.io.req.bits.uop.ftq_idx, io.req.bits.uop.ftq_idx
connect ALUUnit.io.req.bits.uop.br_tag, io.req.bits.uop.br_tag
connect ALUUnit.io.req.bits.uop.br_mask, io.req.bits.uop.br_mask
connect ALUUnit.io.req.bits.uop.is_sfb, io.req.bits.uop.is_sfb
connect ALUUnit.io.req.bits.uop.is_jal, io.req.bits.uop.is_jal
connect ALUUnit.io.req.bits.uop.is_jalr, io.req.bits.uop.is_jalr
connect ALUUnit.io.req.bits.uop.is_br, io.req.bits.uop.is_br
connect ALUUnit.io.req.bits.uop.iw_p2_poisoned, io.req.bits.uop.iw_p2_poisoned
connect ALUUnit.io.req.bits.uop.iw_p1_poisoned, io.req.bits.uop.iw_p1_poisoned
connect ALUUnit.io.req.bits.uop.iw_state, io.req.bits.uop.iw_state
connect ALUUnit.io.req.bits.uop.ctrl.is_std, io.req.bits.uop.ctrl.is_std
connect ALUUnit.io.req.bits.uop.ctrl.is_sta, io.req.bits.uop.ctrl.is_sta
connect ALUUnit.io.req.bits.uop.ctrl.is_load, io.req.bits.uop.ctrl.is_load
connect ALUUnit.io.req.bits.uop.ctrl.csr_cmd, io.req.bits.uop.ctrl.csr_cmd
connect ALUUnit.io.req.bits.uop.ctrl.fcn_dw, io.req.bits.uop.ctrl.fcn_dw
connect ALUUnit.io.req.bits.uop.ctrl.op_fcn, io.req.bits.uop.ctrl.op_fcn
connect ALUUnit.io.req.bits.uop.ctrl.imm_sel, io.req.bits.uop.ctrl.imm_sel
connect ALUUnit.io.req.bits.uop.ctrl.op2_sel, io.req.bits.uop.ctrl.op2_sel
connect ALUUnit.io.req.bits.uop.ctrl.op1_sel, io.req.bits.uop.ctrl.op1_sel
connect ALUUnit.io.req.bits.uop.ctrl.br_type, io.req.bits.uop.ctrl.br_type
connect ALUUnit.io.req.bits.uop.fu_code, io.req.bits.uop.fu_code
connect ALUUnit.io.req.bits.uop.iq_type, io.req.bits.uop.iq_type
connect ALUUnit.io.req.bits.uop.debug_pc, io.req.bits.uop.debug_pc
connect ALUUnit.io.req.bits.uop.is_rvc, io.req.bits.uop.is_rvc
connect ALUUnit.io.req.bits.uop.debug_inst, io.req.bits.uop.debug_inst
connect ALUUnit.io.req.bits.uop.inst, io.req.bits.uop.inst
connect ALUUnit.io.req.bits.uop.uopc, io.req.bits.uop.uopc
connect ALUUnit.io.req.bits.kill, io.req.bits.kill
connect ALUUnit.io.req.bits.rs1_data, io.req.bits.rs1_data
connect ALUUnit.io.req.bits.rs2_data, io.req.bits.rs2_data
invalidate ALUUnit.io.req.bits.rs3_data
connect ALUUnit.io.req.bits.pred_data, io.req.bits.pred_data
invalidate ALUUnit.io.resp.ready
connect ALUUnit.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect ALUUnit.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect ALUUnit.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect ALUUnit.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect ALUUnit.io.brupdate.b2.taken, io.brupdate.b2.taken
connect ALUUnit.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect ALUUnit.io.brupdate.b2.valid, io.brupdate.b2.valid
connect ALUUnit.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect ALUUnit.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect ALUUnit.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect ALUUnit.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect ALUUnit.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect ALUUnit.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect ALUUnit.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect ALUUnit.io.brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect ALUUnit.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect ALUUnit.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect ALUUnit.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect ALUUnit.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect ALUUnit.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect ALUUnit.io.brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect ALUUnit.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect ALUUnit.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect ALUUnit.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect ALUUnit.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect ALUUnit.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect ALUUnit.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect ALUUnit.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect ALUUnit.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect ALUUnit.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect ALUUnit.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect ALUUnit.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect ALUUnit.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect ALUUnit.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect ALUUnit.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect ALUUnit.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect ALUUnit.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect ALUUnit.io.brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect ALUUnit.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect ALUUnit.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect ALUUnit.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect ALUUnit.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect ALUUnit.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect ALUUnit.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect ALUUnit.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect ALUUnit.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect ALUUnit.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect ALUUnit.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect ALUUnit.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect ALUUnit.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect ALUUnit.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect ALUUnit.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect ALUUnit.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect ALUUnit.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect ALUUnit.io.brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect ALUUnit.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect ALUUnit.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect ALUUnit.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect ALUUnit.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect ALUUnit.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect ALUUnit.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect ALUUnit.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect ALUUnit.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect ALUUnit.io.brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect ALUUnit.io.brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect ALUUnit.io.brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect ALUUnit.io.brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect ALUUnit.io.brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect ALUUnit.io.brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect ALUUnit.io.brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect ALUUnit.io.brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect ALUUnit.io.brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect ALUUnit.io.brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect ALUUnit.io.brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect ALUUnit.io.brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect ALUUnit.io.brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect ALUUnit.io.brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect ALUUnit.io.brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect ALUUnit.io.brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect ALUUnit.io.brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect ALUUnit.io.brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect ALUUnit.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect ALUUnit.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect ALUUnit.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect ALUUnit.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect ALUUnit.io.brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect ALUUnit.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect ALUUnit.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect io.bypass, ALUUnit.io.bypass
connect io.brinfo, ALUUnit.io.brinfo
connect ALUUnit.io.get_ftq_pc, io.get_ftq_pc
inst PipelinedMulUnit of PipelinedMulUnit
connect PipelinedMulUnit.clock, clock
connect PipelinedMulUnit.reset, reset
invalidate PipelinedMulUnit.io.brupdate.b2.target_offset
invalidate PipelinedMulUnit.io.brupdate.b2.jalr_target
invalidate PipelinedMulUnit.io.brupdate.b2.pc_sel
invalidate PipelinedMulUnit.io.brupdate.b2.cfi_type
invalidate PipelinedMulUnit.io.brupdate.b2.taken
invalidate PipelinedMulUnit.io.brupdate.b2.mispredict
invalidate PipelinedMulUnit.io.brupdate.b2.valid
invalidate PipelinedMulUnit.io.brupdate.b2.uop.debug_tsrc
invalidate PipelinedMulUnit.io.brupdate.b2.uop.debug_fsrc
invalidate PipelinedMulUnit.io.brupdate.b2.uop.bp_xcpt_if
invalidate PipelinedMulUnit.io.brupdate.b2.uop.bp_debug_if
invalidate PipelinedMulUnit.io.brupdate.b2.uop.xcpt_ma_if
invalidate PipelinedMulUnit.io.brupdate.b2.uop.xcpt_ae_if
invalidate PipelinedMulUnit.io.brupdate.b2.uop.xcpt_pf_if
invalidate PipelinedMulUnit.io.brupdate.b2.uop.fp_single
invalidate PipelinedMulUnit.io.brupdate.b2.uop.fp_val
invalidate PipelinedMulUnit.io.brupdate.b2.uop.frs3_en
invalidate PipelinedMulUnit.io.brupdate.b2.uop.lrs2_rtype
invalidate PipelinedMulUnit.io.brupdate.b2.uop.lrs1_rtype
invalidate PipelinedMulUnit.io.brupdate.b2.uop.dst_rtype
invalidate PipelinedMulUnit.io.brupdate.b2.uop.ldst_val
invalidate PipelinedMulUnit.io.brupdate.b2.uop.lrs3
invalidate PipelinedMulUnit.io.brupdate.b2.uop.lrs2
invalidate PipelinedMulUnit.io.brupdate.b2.uop.lrs1
invalidate PipelinedMulUnit.io.brupdate.b2.uop.ldst
invalidate PipelinedMulUnit.io.brupdate.b2.uop.ldst_is_rs1
invalidate PipelinedMulUnit.io.brupdate.b2.uop.flush_on_commit
invalidate PipelinedMulUnit.io.brupdate.b2.uop.is_unique
invalidate PipelinedMulUnit.io.brupdate.b2.uop.is_sys_pc2epc
invalidate PipelinedMulUnit.io.brupdate.b2.uop.uses_stq
invalidate PipelinedMulUnit.io.brupdate.b2.uop.uses_ldq
invalidate PipelinedMulUnit.io.brupdate.b2.uop.is_amo
invalidate PipelinedMulUnit.io.brupdate.b2.uop.is_fencei
invalidate PipelinedMulUnit.io.brupdate.b2.uop.is_fence
invalidate PipelinedMulUnit.io.brupdate.b2.uop.mem_signed
invalidate PipelinedMulUnit.io.brupdate.b2.uop.mem_size
invalidate PipelinedMulUnit.io.brupdate.b2.uop.mem_cmd
invalidate PipelinedMulUnit.io.brupdate.b2.uop.bypassable
invalidate PipelinedMulUnit.io.brupdate.b2.uop.exc_cause
invalidate PipelinedMulUnit.io.brupdate.b2.uop.exception
invalidate PipelinedMulUnit.io.brupdate.b2.uop.stale_pdst
invalidate PipelinedMulUnit.io.brupdate.b2.uop.ppred_busy
invalidate PipelinedMulUnit.io.brupdate.b2.uop.prs3_busy
invalidate PipelinedMulUnit.io.brupdate.b2.uop.prs2_busy
invalidate PipelinedMulUnit.io.brupdate.b2.uop.prs1_busy
invalidate PipelinedMulUnit.io.brupdate.b2.uop.ppred
invalidate PipelinedMulUnit.io.brupdate.b2.uop.prs3
invalidate PipelinedMulUnit.io.brupdate.b2.uop.prs2
invalidate PipelinedMulUnit.io.brupdate.b2.uop.prs1
invalidate PipelinedMulUnit.io.brupdate.b2.uop.pdst
invalidate PipelinedMulUnit.io.brupdate.b2.uop.rxq_idx
invalidate PipelinedMulUnit.io.brupdate.b2.uop.stq_idx
invalidate PipelinedMulUnit.io.brupdate.b2.uop.ldq_idx
invalidate PipelinedMulUnit.io.brupdate.b2.uop.rob_idx
invalidate PipelinedMulUnit.io.brupdate.b2.uop.csr_addr
invalidate PipelinedMulUnit.io.brupdate.b2.uop.imm_packed
invalidate PipelinedMulUnit.io.brupdate.b2.uop.taken
invalidate PipelinedMulUnit.io.brupdate.b2.uop.pc_lob
invalidate PipelinedMulUnit.io.brupdate.b2.uop.edge_inst
invalidate PipelinedMulUnit.io.brupdate.b2.uop.ftq_idx
invalidate PipelinedMulUnit.io.brupdate.b2.uop.br_tag
invalidate PipelinedMulUnit.io.brupdate.b2.uop.br_mask
invalidate PipelinedMulUnit.io.brupdate.b2.uop.is_sfb
invalidate PipelinedMulUnit.io.brupdate.b2.uop.is_jal
invalidate PipelinedMulUnit.io.brupdate.b2.uop.is_jalr
invalidate PipelinedMulUnit.io.brupdate.b2.uop.is_br
invalidate PipelinedMulUnit.io.brupdate.b2.uop.iw_p2_poisoned
invalidate PipelinedMulUnit.io.brupdate.b2.uop.iw_p1_poisoned
invalidate PipelinedMulUnit.io.brupdate.b2.uop.iw_state
invalidate PipelinedMulUnit.io.brupdate.b2.uop.ctrl.is_std
invalidate PipelinedMulUnit.io.brupdate.b2.uop.ctrl.is_sta
invalidate PipelinedMulUnit.io.brupdate.b2.uop.ctrl.is_load
invalidate PipelinedMulUnit.io.brupdate.b2.uop.ctrl.csr_cmd
invalidate PipelinedMulUnit.io.brupdate.b2.uop.ctrl.fcn_dw
invalidate PipelinedMulUnit.io.brupdate.b2.uop.ctrl.op_fcn
invalidate PipelinedMulUnit.io.brupdate.b2.uop.ctrl.imm_sel
invalidate PipelinedMulUnit.io.brupdate.b2.uop.ctrl.op2_sel
invalidate PipelinedMulUnit.io.brupdate.b2.uop.ctrl.op1_sel
invalidate PipelinedMulUnit.io.brupdate.b2.uop.ctrl.br_type
invalidate PipelinedMulUnit.io.brupdate.b2.uop.fu_code
invalidate PipelinedMulUnit.io.brupdate.b2.uop.iq_type
invalidate PipelinedMulUnit.io.brupdate.b2.uop.debug_pc
invalidate PipelinedMulUnit.io.brupdate.b2.uop.is_rvc
invalidate PipelinedMulUnit.io.brupdate.b2.uop.debug_inst
invalidate PipelinedMulUnit.io.brupdate.b2.uop.inst
invalidate PipelinedMulUnit.io.brupdate.b2.uop.uopc
invalidate PipelinedMulUnit.io.brupdate.b1.mispredict_mask
invalidate PipelinedMulUnit.io.brupdate.b1.resolve_mask
invalidate PipelinedMulUnit.io.resp.bits.sfence.bits.hg
invalidate PipelinedMulUnit.io.resp.bits.sfence.bits.hv
invalidate PipelinedMulUnit.io.resp.bits.sfence.bits.asid
invalidate PipelinedMulUnit.io.resp.bits.sfence.bits.addr
invalidate PipelinedMulUnit.io.resp.bits.sfence.bits.rs2
invalidate PipelinedMulUnit.io.resp.bits.sfence.bits.rs1
invalidate PipelinedMulUnit.io.resp.bits.sfence.valid
invalidate PipelinedMulUnit.io.resp.bits.mxcpt.bits
invalidate PipelinedMulUnit.io.resp.bits.mxcpt.valid
invalidate PipelinedMulUnit.io.resp.bits.addr
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.flags
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.debug_tsrc
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.debug_fsrc
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.bp_xcpt_if
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.bp_debug_if
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.xcpt_ma_if
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.xcpt_ae_if
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.xcpt_pf_if
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.fp_single
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.fp_val
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.frs3_en
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.lrs2_rtype
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.lrs1_rtype
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.dst_rtype
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ldst_val
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.lrs3
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.lrs2
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.lrs1
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ldst
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ldst_is_rs1
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.flush_on_commit
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.is_unique
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.is_sys_pc2epc
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.uses_stq
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.uses_ldq
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.is_amo
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.is_fencei
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.is_fence
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.mem_signed
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.mem_size
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.mem_cmd
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.bypassable
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.exc_cause
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.exception
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.stale_pdst
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ppred_busy
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.prs3_busy
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.prs2_busy
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.prs1_busy
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ppred
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.prs3
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.prs2
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.prs1
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.pdst
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.rxq_idx
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.stq_idx
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ldq_idx
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.rob_idx
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.csr_addr
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.imm_packed
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.taken
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.pc_lob
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.edge_inst
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ftq_idx
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.br_tag
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.br_mask
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.is_sfb
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.is_jal
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.is_jalr
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.is_br
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.iw_p2_poisoned
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.iw_p1_poisoned
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.iw_state
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ctrl.is_std
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ctrl.is_sta
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ctrl.is_load
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ctrl.csr_cmd
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ctrl.fcn_dw
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ctrl.op_fcn
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ctrl.imm_sel
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ctrl.op2_sel
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ctrl.op1_sel
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ctrl.br_type
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.fu_code
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.iq_type
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.debug_pc
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.is_rvc
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.debug_inst
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.inst
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.uopc
invalidate PipelinedMulUnit.io.resp.bits.fflags.valid
invalidate PipelinedMulUnit.io.resp.bits.data
invalidate PipelinedMulUnit.io.resp.bits.predicated
invalidate PipelinedMulUnit.io.resp.bits.uop.debug_tsrc
invalidate PipelinedMulUnit.io.resp.bits.uop.debug_fsrc
invalidate PipelinedMulUnit.io.resp.bits.uop.bp_xcpt_if
invalidate PipelinedMulUnit.io.resp.bits.uop.bp_debug_if
invalidate PipelinedMulUnit.io.resp.bits.uop.xcpt_ma_if
invalidate PipelinedMulUnit.io.resp.bits.uop.xcpt_ae_if
invalidate PipelinedMulUnit.io.resp.bits.uop.xcpt_pf_if
invalidate PipelinedMulUnit.io.resp.bits.uop.fp_single
invalidate PipelinedMulUnit.io.resp.bits.uop.fp_val
invalidate PipelinedMulUnit.io.resp.bits.uop.frs3_en
invalidate PipelinedMulUnit.io.resp.bits.uop.lrs2_rtype
invalidate PipelinedMulUnit.io.resp.bits.uop.lrs1_rtype
invalidate PipelinedMulUnit.io.resp.bits.uop.dst_rtype
invalidate PipelinedMulUnit.io.resp.bits.uop.ldst_val
invalidate PipelinedMulUnit.io.resp.bits.uop.lrs3
invalidate PipelinedMulUnit.io.resp.bits.uop.lrs2
invalidate PipelinedMulUnit.io.resp.bits.uop.lrs1
invalidate PipelinedMulUnit.io.resp.bits.uop.ldst
invalidate PipelinedMulUnit.io.resp.bits.uop.ldst_is_rs1
invalidate PipelinedMulUnit.io.resp.bits.uop.flush_on_commit
invalidate PipelinedMulUnit.io.resp.bits.uop.is_unique
invalidate PipelinedMulUnit.io.resp.bits.uop.is_sys_pc2epc
invalidate PipelinedMulUnit.io.resp.bits.uop.uses_stq
invalidate PipelinedMulUnit.io.resp.bits.uop.uses_ldq
invalidate PipelinedMulUnit.io.resp.bits.uop.is_amo
invalidate PipelinedMulUnit.io.resp.bits.uop.is_fencei
invalidate PipelinedMulUnit.io.resp.bits.uop.is_fence
invalidate PipelinedMulUnit.io.resp.bits.uop.mem_signed
invalidate PipelinedMulUnit.io.resp.bits.uop.mem_size
invalidate PipelinedMulUnit.io.resp.bits.uop.mem_cmd
invalidate PipelinedMulUnit.io.resp.bits.uop.bypassable
invalidate PipelinedMulUnit.io.resp.bits.uop.exc_cause
invalidate PipelinedMulUnit.io.resp.bits.uop.exception
invalidate PipelinedMulUnit.io.resp.bits.uop.stale_pdst
invalidate PipelinedMulUnit.io.resp.bits.uop.ppred_busy
invalidate PipelinedMulUnit.io.resp.bits.uop.prs3_busy
invalidate PipelinedMulUnit.io.resp.bits.uop.prs2_busy
invalidate PipelinedMulUnit.io.resp.bits.uop.prs1_busy
invalidate PipelinedMulUnit.io.resp.bits.uop.ppred
invalidate PipelinedMulUnit.io.resp.bits.uop.prs3
invalidate PipelinedMulUnit.io.resp.bits.uop.prs2
invalidate PipelinedMulUnit.io.resp.bits.uop.prs1
invalidate PipelinedMulUnit.io.resp.bits.uop.pdst
invalidate PipelinedMulUnit.io.resp.bits.uop.rxq_idx
invalidate PipelinedMulUnit.io.resp.bits.uop.stq_idx
invalidate PipelinedMulUnit.io.resp.bits.uop.ldq_idx
invalidate PipelinedMulUnit.io.resp.bits.uop.rob_idx
invalidate PipelinedMulUnit.io.resp.bits.uop.csr_addr
invalidate PipelinedMulUnit.io.resp.bits.uop.imm_packed
invalidate PipelinedMulUnit.io.resp.bits.uop.taken
invalidate PipelinedMulUnit.io.resp.bits.uop.pc_lob
invalidate PipelinedMulUnit.io.resp.bits.uop.edge_inst
invalidate PipelinedMulUnit.io.resp.bits.uop.ftq_idx
invalidate PipelinedMulUnit.io.resp.bits.uop.br_tag
invalidate PipelinedMulUnit.io.resp.bits.uop.br_mask
invalidate PipelinedMulUnit.io.resp.bits.uop.is_sfb
invalidate PipelinedMulUnit.io.resp.bits.uop.is_jal
invalidate PipelinedMulUnit.io.resp.bits.uop.is_jalr
invalidate PipelinedMulUnit.io.resp.bits.uop.is_br
invalidate PipelinedMulUnit.io.resp.bits.uop.iw_p2_poisoned
invalidate PipelinedMulUnit.io.resp.bits.uop.iw_p1_poisoned
invalidate PipelinedMulUnit.io.resp.bits.uop.iw_state
invalidate PipelinedMulUnit.io.resp.bits.uop.ctrl.is_std
invalidate PipelinedMulUnit.io.resp.bits.uop.ctrl.is_sta
invalidate PipelinedMulUnit.io.resp.bits.uop.ctrl.is_load
invalidate PipelinedMulUnit.io.resp.bits.uop.ctrl.csr_cmd
invalidate PipelinedMulUnit.io.resp.bits.uop.ctrl.fcn_dw
invalidate PipelinedMulUnit.io.resp.bits.uop.ctrl.op_fcn
invalidate PipelinedMulUnit.io.resp.bits.uop.ctrl.imm_sel
invalidate PipelinedMulUnit.io.resp.bits.uop.ctrl.op2_sel
invalidate PipelinedMulUnit.io.resp.bits.uop.ctrl.op1_sel
invalidate PipelinedMulUnit.io.resp.bits.uop.ctrl.br_type
invalidate PipelinedMulUnit.io.resp.bits.uop.fu_code
invalidate PipelinedMulUnit.io.resp.bits.uop.iq_type
invalidate PipelinedMulUnit.io.resp.bits.uop.debug_pc
invalidate PipelinedMulUnit.io.resp.bits.uop.is_rvc
invalidate PipelinedMulUnit.io.resp.bits.uop.debug_inst
invalidate PipelinedMulUnit.io.resp.bits.uop.inst
invalidate PipelinedMulUnit.io.resp.bits.uop.uopc
invalidate PipelinedMulUnit.io.resp.valid
invalidate PipelinedMulUnit.io.resp.ready
invalidate PipelinedMulUnit.io.req.bits.kill
invalidate PipelinedMulUnit.io.req.bits.pred_data
invalidate PipelinedMulUnit.io.req.bits.rs3_data
invalidate PipelinedMulUnit.io.req.bits.rs2_data
invalidate PipelinedMulUnit.io.req.bits.rs1_data
invalidate PipelinedMulUnit.io.req.bits.uop.debug_tsrc
invalidate PipelinedMulUnit.io.req.bits.uop.debug_fsrc
invalidate PipelinedMulUnit.io.req.bits.uop.bp_xcpt_if
invalidate PipelinedMulUnit.io.req.bits.uop.bp_debug_if
invalidate PipelinedMulUnit.io.req.bits.uop.xcpt_ma_if
invalidate PipelinedMulUnit.io.req.bits.uop.xcpt_ae_if
invalidate PipelinedMulUnit.io.req.bits.uop.xcpt_pf_if
invalidate PipelinedMulUnit.io.req.bits.uop.fp_single
invalidate PipelinedMulUnit.io.req.bits.uop.fp_val
invalidate PipelinedMulUnit.io.req.bits.uop.frs3_en
invalidate PipelinedMulUnit.io.req.bits.uop.lrs2_rtype
invalidate PipelinedMulUnit.io.req.bits.uop.lrs1_rtype
invalidate PipelinedMulUnit.io.req.bits.uop.dst_rtype
invalidate PipelinedMulUnit.io.req.bits.uop.ldst_val
invalidate PipelinedMulUnit.io.req.bits.uop.lrs3
invalidate PipelinedMulUnit.io.req.bits.uop.lrs2
invalidate PipelinedMulUnit.io.req.bits.uop.lrs1
invalidate PipelinedMulUnit.io.req.bits.uop.ldst
invalidate PipelinedMulUnit.io.req.bits.uop.ldst_is_rs1
invalidate PipelinedMulUnit.io.req.bits.uop.flush_on_commit
invalidate PipelinedMulUnit.io.req.bits.uop.is_unique
invalidate PipelinedMulUnit.io.req.bits.uop.is_sys_pc2epc
invalidate PipelinedMulUnit.io.req.bits.uop.uses_stq
invalidate PipelinedMulUnit.io.req.bits.uop.uses_ldq
invalidate PipelinedMulUnit.io.req.bits.uop.is_amo
invalidate PipelinedMulUnit.io.req.bits.uop.is_fencei
invalidate PipelinedMulUnit.io.req.bits.uop.is_fence
invalidate PipelinedMulUnit.io.req.bits.uop.mem_signed
invalidate PipelinedMulUnit.io.req.bits.uop.mem_size
invalidate PipelinedMulUnit.io.req.bits.uop.mem_cmd
invalidate PipelinedMulUnit.io.req.bits.uop.bypassable
invalidate PipelinedMulUnit.io.req.bits.uop.exc_cause
invalidate PipelinedMulUnit.io.req.bits.uop.exception
invalidate PipelinedMulUnit.io.req.bits.uop.stale_pdst
invalidate PipelinedMulUnit.io.req.bits.uop.ppred_busy
invalidate PipelinedMulUnit.io.req.bits.uop.prs3_busy
invalidate PipelinedMulUnit.io.req.bits.uop.prs2_busy
invalidate PipelinedMulUnit.io.req.bits.uop.prs1_busy
invalidate PipelinedMulUnit.io.req.bits.uop.ppred
invalidate PipelinedMulUnit.io.req.bits.uop.prs3
invalidate PipelinedMulUnit.io.req.bits.uop.prs2
invalidate PipelinedMulUnit.io.req.bits.uop.prs1
invalidate PipelinedMulUnit.io.req.bits.uop.pdst
invalidate PipelinedMulUnit.io.req.bits.uop.rxq_idx
invalidate PipelinedMulUnit.io.req.bits.uop.stq_idx
invalidate PipelinedMulUnit.io.req.bits.uop.ldq_idx
invalidate PipelinedMulUnit.io.req.bits.uop.rob_idx
invalidate PipelinedMulUnit.io.req.bits.uop.csr_addr
invalidate PipelinedMulUnit.io.req.bits.uop.imm_packed
invalidate PipelinedMulUnit.io.req.bits.uop.taken
invalidate PipelinedMulUnit.io.req.bits.uop.pc_lob
invalidate PipelinedMulUnit.io.req.bits.uop.edge_inst
invalidate PipelinedMulUnit.io.req.bits.uop.ftq_idx
invalidate PipelinedMulUnit.io.req.bits.uop.br_tag
invalidate PipelinedMulUnit.io.req.bits.uop.br_mask
invalidate PipelinedMulUnit.io.req.bits.uop.is_sfb
invalidate PipelinedMulUnit.io.req.bits.uop.is_jal
invalidate PipelinedMulUnit.io.req.bits.uop.is_jalr
invalidate PipelinedMulUnit.io.req.bits.uop.is_br
invalidate PipelinedMulUnit.io.req.bits.uop.iw_p2_poisoned
invalidate PipelinedMulUnit.io.req.bits.uop.iw_p1_poisoned
invalidate PipelinedMulUnit.io.req.bits.uop.iw_state
invalidate PipelinedMulUnit.io.req.bits.uop.ctrl.is_std
invalidate PipelinedMulUnit.io.req.bits.uop.ctrl.is_sta
invalidate PipelinedMulUnit.io.req.bits.uop.ctrl.is_load
invalidate PipelinedMulUnit.io.req.bits.uop.ctrl.csr_cmd
invalidate PipelinedMulUnit.io.req.bits.uop.ctrl.fcn_dw
invalidate PipelinedMulUnit.io.req.bits.uop.ctrl.op_fcn
invalidate PipelinedMulUnit.io.req.bits.uop.ctrl.imm_sel
invalidate PipelinedMulUnit.io.req.bits.uop.ctrl.op2_sel
invalidate PipelinedMulUnit.io.req.bits.uop.ctrl.op1_sel
invalidate PipelinedMulUnit.io.req.bits.uop.ctrl.br_type
invalidate PipelinedMulUnit.io.req.bits.uop.fu_code
invalidate PipelinedMulUnit.io.req.bits.uop.iq_type
invalidate PipelinedMulUnit.io.req.bits.uop.debug_pc
invalidate PipelinedMulUnit.io.req.bits.uop.is_rvc
invalidate PipelinedMulUnit.io.req.bits.uop.debug_inst
invalidate PipelinedMulUnit.io.req.bits.uop.inst
invalidate PipelinedMulUnit.io.req.bits.uop.uopc
invalidate PipelinedMulUnit.io.req.valid
invalidate PipelinedMulUnit.io.req.ready
node _T_11 = and(io.req.bits.uop.fu_code, UInt<10>(0h8))
node _T_12 = neq(_T_11, UInt<1>(0h0))
node _T_13 = and(io.req.valid, _T_12)
connect PipelinedMulUnit.io.req.valid, _T_13
connect PipelinedMulUnit.io.req.bits.uop.debug_tsrc, io.req.bits.uop.debug_tsrc
connect PipelinedMulUnit.io.req.bits.uop.debug_fsrc, io.req.bits.uop.debug_fsrc
connect PipelinedMulUnit.io.req.bits.uop.bp_xcpt_if, io.req.bits.uop.bp_xcpt_if
connect PipelinedMulUnit.io.req.bits.uop.bp_debug_if, io.req.bits.uop.bp_debug_if
connect PipelinedMulUnit.io.req.bits.uop.xcpt_ma_if, io.req.bits.uop.xcpt_ma_if
connect PipelinedMulUnit.io.req.bits.uop.xcpt_ae_if, io.req.bits.uop.xcpt_ae_if
connect PipelinedMulUnit.io.req.bits.uop.xcpt_pf_if, io.req.bits.uop.xcpt_pf_if
connect PipelinedMulUnit.io.req.bits.uop.fp_single, io.req.bits.uop.fp_single
connect PipelinedMulUnit.io.req.bits.uop.fp_val, io.req.bits.uop.fp_val
connect PipelinedMulUnit.io.req.bits.uop.frs3_en, io.req.bits.uop.frs3_en
connect PipelinedMulUnit.io.req.bits.uop.lrs2_rtype, io.req.bits.uop.lrs2_rtype
connect PipelinedMulUnit.io.req.bits.uop.lrs1_rtype, io.req.bits.uop.lrs1_rtype
connect PipelinedMulUnit.io.req.bits.uop.dst_rtype, io.req.bits.uop.dst_rtype
connect PipelinedMulUnit.io.req.bits.uop.ldst_val, io.req.bits.uop.ldst_val
connect PipelinedMulUnit.io.req.bits.uop.lrs3, io.req.bits.uop.lrs3
connect PipelinedMulUnit.io.req.bits.uop.lrs2, io.req.bits.uop.lrs2
connect PipelinedMulUnit.io.req.bits.uop.lrs1, io.req.bits.uop.lrs1
connect PipelinedMulUnit.io.req.bits.uop.ldst, io.req.bits.uop.ldst
connect PipelinedMulUnit.io.req.bits.uop.ldst_is_rs1, io.req.bits.uop.ldst_is_rs1
connect PipelinedMulUnit.io.req.bits.uop.flush_on_commit, io.req.bits.uop.flush_on_commit
connect PipelinedMulUnit.io.req.bits.uop.is_unique, io.req.bits.uop.is_unique
connect PipelinedMulUnit.io.req.bits.uop.is_sys_pc2epc, io.req.bits.uop.is_sys_pc2epc
connect PipelinedMulUnit.io.req.bits.uop.uses_stq, io.req.bits.uop.uses_stq
connect PipelinedMulUnit.io.req.bits.uop.uses_ldq, io.req.bits.uop.uses_ldq
connect PipelinedMulUnit.io.req.bits.uop.is_amo, io.req.bits.uop.is_amo
connect PipelinedMulUnit.io.req.bits.uop.is_fencei, io.req.bits.uop.is_fencei
connect PipelinedMulUnit.io.req.bits.uop.is_fence, io.req.bits.uop.is_fence
connect PipelinedMulUnit.io.req.bits.uop.mem_signed, io.req.bits.uop.mem_signed
connect PipelinedMulUnit.io.req.bits.uop.mem_size, io.req.bits.uop.mem_size
connect PipelinedMulUnit.io.req.bits.uop.mem_cmd, io.req.bits.uop.mem_cmd
connect PipelinedMulUnit.io.req.bits.uop.bypassable, io.req.bits.uop.bypassable
connect PipelinedMulUnit.io.req.bits.uop.exc_cause, io.req.bits.uop.exc_cause
connect PipelinedMulUnit.io.req.bits.uop.exception, io.req.bits.uop.exception
connect PipelinedMulUnit.io.req.bits.uop.stale_pdst, io.req.bits.uop.stale_pdst
connect PipelinedMulUnit.io.req.bits.uop.ppred_busy, io.req.bits.uop.ppred_busy
connect PipelinedMulUnit.io.req.bits.uop.prs3_busy, io.req.bits.uop.prs3_busy
connect PipelinedMulUnit.io.req.bits.uop.prs2_busy, io.req.bits.uop.prs2_busy
connect PipelinedMulUnit.io.req.bits.uop.prs1_busy, io.req.bits.uop.prs1_busy
connect PipelinedMulUnit.io.req.bits.uop.ppred, io.req.bits.uop.ppred
connect PipelinedMulUnit.io.req.bits.uop.prs3, io.req.bits.uop.prs3
connect PipelinedMulUnit.io.req.bits.uop.prs2, io.req.bits.uop.prs2
connect PipelinedMulUnit.io.req.bits.uop.prs1, io.req.bits.uop.prs1
connect PipelinedMulUnit.io.req.bits.uop.pdst, io.req.bits.uop.pdst
connect PipelinedMulUnit.io.req.bits.uop.rxq_idx, io.req.bits.uop.rxq_idx
connect PipelinedMulUnit.io.req.bits.uop.stq_idx, io.req.bits.uop.stq_idx
connect PipelinedMulUnit.io.req.bits.uop.ldq_idx, io.req.bits.uop.ldq_idx
connect PipelinedMulUnit.io.req.bits.uop.rob_idx, io.req.bits.uop.rob_idx
connect PipelinedMulUnit.io.req.bits.uop.csr_addr, io.req.bits.uop.csr_addr
connect PipelinedMulUnit.io.req.bits.uop.imm_packed, io.req.bits.uop.imm_packed
connect PipelinedMulUnit.io.req.bits.uop.taken, io.req.bits.uop.taken
connect PipelinedMulUnit.io.req.bits.uop.pc_lob, io.req.bits.uop.pc_lob
connect PipelinedMulUnit.io.req.bits.uop.edge_inst, io.req.bits.uop.edge_inst
connect PipelinedMulUnit.io.req.bits.uop.ftq_idx, io.req.bits.uop.ftq_idx
connect PipelinedMulUnit.io.req.bits.uop.br_tag, io.req.bits.uop.br_tag
connect PipelinedMulUnit.io.req.bits.uop.br_mask, io.req.bits.uop.br_mask
connect PipelinedMulUnit.io.req.bits.uop.is_sfb, io.req.bits.uop.is_sfb
connect PipelinedMulUnit.io.req.bits.uop.is_jal, io.req.bits.uop.is_jal
connect PipelinedMulUnit.io.req.bits.uop.is_jalr, io.req.bits.uop.is_jalr
connect PipelinedMulUnit.io.req.bits.uop.is_br, io.req.bits.uop.is_br
connect PipelinedMulUnit.io.req.bits.uop.iw_p2_poisoned, io.req.bits.uop.iw_p2_poisoned
connect PipelinedMulUnit.io.req.bits.uop.iw_p1_poisoned, io.req.bits.uop.iw_p1_poisoned
connect PipelinedMulUnit.io.req.bits.uop.iw_state, io.req.bits.uop.iw_state
connect PipelinedMulUnit.io.req.bits.uop.ctrl.is_std, io.req.bits.uop.ctrl.is_std
connect PipelinedMulUnit.io.req.bits.uop.ctrl.is_sta, io.req.bits.uop.ctrl.is_sta
connect PipelinedMulUnit.io.req.bits.uop.ctrl.is_load, io.req.bits.uop.ctrl.is_load
connect PipelinedMulUnit.io.req.bits.uop.ctrl.csr_cmd, io.req.bits.uop.ctrl.csr_cmd
connect PipelinedMulUnit.io.req.bits.uop.ctrl.fcn_dw, io.req.bits.uop.ctrl.fcn_dw
connect PipelinedMulUnit.io.req.bits.uop.ctrl.op_fcn, io.req.bits.uop.ctrl.op_fcn
connect PipelinedMulUnit.io.req.bits.uop.ctrl.imm_sel, io.req.bits.uop.ctrl.imm_sel
connect PipelinedMulUnit.io.req.bits.uop.ctrl.op2_sel, io.req.bits.uop.ctrl.op2_sel
connect PipelinedMulUnit.io.req.bits.uop.ctrl.op1_sel, io.req.bits.uop.ctrl.op1_sel
connect PipelinedMulUnit.io.req.bits.uop.ctrl.br_type, io.req.bits.uop.ctrl.br_type
connect PipelinedMulUnit.io.req.bits.uop.fu_code, io.req.bits.uop.fu_code
connect PipelinedMulUnit.io.req.bits.uop.iq_type, io.req.bits.uop.iq_type
connect PipelinedMulUnit.io.req.bits.uop.debug_pc, io.req.bits.uop.debug_pc
connect PipelinedMulUnit.io.req.bits.uop.is_rvc, io.req.bits.uop.is_rvc
connect PipelinedMulUnit.io.req.bits.uop.debug_inst, io.req.bits.uop.debug_inst
connect PipelinedMulUnit.io.req.bits.uop.inst, io.req.bits.uop.inst
connect PipelinedMulUnit.io.req.bits.uop.uopc, io.req.bits.uop.uopc
connect PipelinedMulUnit.io.req.bits.rs1_data, io.req.bits.rs1_data
connect PipelinedMulUnit.io.req.bits.rs2_data, io.req.bits.rs2_data
connect PipelinedMulUnit.io.req.bits.kill, io.req.bits.kill
connect PipelinedMulUnit.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect PipelinedMulUnit.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect PipelinedMulUnit.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect PipelinedMulUnit.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect PipelinedMulUnit.io.brupdate.b2.taken, io.brupdate.b2.taken
connect PipelinedMulUnit.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect PipelinedMulUnit.io.brupdate.b2.valid, io.brupdate.b2.valid
connect PipelinedMulUnit.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect PipelinedMulUnit.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect PipelinedMulUnit.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect PipelinedMulUnit.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect PipelinedMulUnit.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect PipelinedMulUnit.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect PipelinedMulUnit.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect PipelinedMulUnit.io.brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect PipelinedMulUnit.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect PipelinedMulUnit.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect PipelinedMulUnit.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect PipelinedMulUnit.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect PipelinedMulUnit.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect PipelinedMulUnit.io.brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect PipelinedMulUnit.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect PipelinedMulUnit.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect PipelinedMulUnit.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect PipelinedMulUnit.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect PipelinedMulUnit.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect PipelinedMulUnit.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect PipelinedMulUnit.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect PipelinedMulUnit.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect PipelinedMulUnit.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect PipelinedMulUnit.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect PipelinedMulUnit.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect PipelinedMulUnit.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect PipelinedMulUnit.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect PipelinedMulUnit.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect PipelinedMulUnit.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect PipelinedMulUnit.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect PipelinedMulUnit.io.brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect PipelinedMulUnit.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect PipelinedMulUnit.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect PipelinedMulUnit.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect PipelinedMulUnit.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect PipelinedMulUnit.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect PipelinedMulUnit.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect PipelinedMulUnit.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect PipelinedMulUnit.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect PipelinedMulUnit.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect PipelinedMulUnit.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect PipelinedMulUnit.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect PipelinedMulUnit.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect PipelinedMulUnit.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect PipelinedMulUnit.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect PipelinedMulUnit.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect PipelinedMulUnit.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect PipelinedMulUnit.io.brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect PipelinedMulUnit.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect PipelinedMulUnit.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect PipelinedMulUnit.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect PipelinedMulUnit.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect PipelinedMulUnit.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect PipelinedMulUnit.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect PipelinedMulUnit.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect PipelinedMulUnit.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect PipelinedMulUnit.io.brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect PipelinedMulUnit.io.brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect PipelinedMulUnit.io.brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect PipelinedMulUnit.io.brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect PipelinedMulUnit.io.brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect PipelinedMulUnit.io.brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect PipelinedMulUnit.io.brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect PipelinedMulUnit.io.brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect PipelinedMulUnit.io.brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect PipelinedMulUnit.io.brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect PipelinedMulUnit.io.brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect PipelinedMulUnit.io.brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect PipelinedMulUnit.io.brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect PipelinedMulUnit.io.brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect PipelinedMulUnit.io.brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect PipelinedMulUnit.io.brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect PipelinedMulUnit.io.brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect PipelinedMulUnit.io.brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect PipelinedMulUnit.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect PipelinedMulUnit.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect PipelinedMulUnit.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect PipelinedMulUnit.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect PipelinedMulUnit.io.brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect PipelinedMulUnit.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect PipelinedMulUnit.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
inst IntToFPUnit of IntToFPUnit
connect IntToFPUnit.clock, clock
connect IntToFPUnit.reset, reset
connect IntToFPUnit.io.req, io.req
node _T_14 = and(io.req.bits.uop.fu_code, UInt<10>(0h100))
node _T_15 = neq(_T_14, UInt<1>(0h0))
node _T_16 = and(io.req.valid, _T_15)
connect IntToFPUnit.io.req.valid, _T_16
connect IntToFPUnit.io.fcsr_rm, io.fcsr_rm
connect IntToFPUnit.io.brupdate, io.brupdate
invalidate IntToFPUnit.io.resp.ready
inst queue of BranchKillableQueue_3
connect queue.clock, clock
connect queue.reset, reset
connect queue.io.enq.valid, IntToFPUnit.io.resp.valid
connect queue.io.enq.bits.uop.debug_tsrc, IntToFPUnit.io.resp.bits.uop.debug_tsrc
connect queue.io.enq.bits.uop.debug_fsrc, IntToFPUnit.io.resp.bits.uop.debug_fsrc
connect queue.io.enq.bits.uop.bp_xcpt_if, IntToFPUnit.io.resp.bits.uop.bp_xcpt_if
connect queue.io.enq.bits.uop.bp_debug_if, IntToFPUnit.io.resp.bits.uop.bp_debug_if
connect queue.io.enq.bits.uop.xcpt_ma_if, IntToFPUnit.io.resp.bits.uop.xcpt_ma_if
connect queue.io.enq.bits.uop.xcpt_ae_if, IntToFPUnit.io.resp.bits.uop.xcpt_ae_if
connect queue.io.enq.bits.uop.xcpt_pf_if, IntToFPUnit.io.resp.bits.uop.xcpt_pf_if
connect queue.io.enq.bits.uop.fp_single, IntToFPUnit.io.resp.bits.uop.fp_single
connect queue.io.enq.bits.uop.fp_val, IntToFPUnit.io.resp.bits.uop.fp_val
connect queue.io.enq.bits.uop.frs3_en, IntToFPUnit.io.resp.bits.uop.frs3_en
connect queue.io.enq.bits.uop.lrs2_rtype, IntToFPUnit.io.resp.bits.uop.lrs2_rtype
connect queue.io.enq.bits.uop.lrs1_rtype, IntToFPUnit.io.resp.bits.uop.lrs1_rtype
connect queue.io.enq.bits.uop.dst_rtype, IntToFPUnit.io.resp.bits.uop.dst_rtype
connect queue.io.enq.bits.uop.ldst_val, IntToFPUnit.io.resp.bits.uop.ldst_val
connect queue.io.enq.bits.uop.lrs3, IntToFPUnit.io.resp.bits.uop.lrs3
connect queue.io.enq.bits.uop.lrs2, IntToFPUnit.io.resp.bits.uop.lrs2
connect queue.io.enq.bits.uop.lrs1, IntToFPUnit.io.resp.bits.uop.lrs1
connect queue.io.enq.bits.uop.ldst, IntToFPUnit.io.resp.bits.uop.ldst
connect queue.io.enq.bits.uop.ldst_is_rs1, IntToFPUnit.io.resp.bits.uop.ldst_is_rs1
connect queue.io.enq.bits.uop.flush_on_commit, IntToFPUnit.io.resp.bits.uop.flush_on_commit
connect queue.io.enq.bits.uop.is_unique, IntToFPUnit.io.resp.bits.uop.is_unique
connect queue.io.enq.bits.uop.is_sys_pc2epc, IntToFPUnit.io.resp.bits.uop.is_sys_pc2epc
connect queue.io.enq.bits.uop.uses_stq, IntToFPUnit.io.resp.bits.uop.uses_stq
connect queue.io.enq.bits.uop.uses_ldq, IntToFPUnit.io.resp.bits.uop.uses_ldq
connect queue.io.enq.bits.uop.is_amo, IntToFPUnit.io.resp.bits.uop.is_amo
connect queue.io.enq.bits.uop.is_fencei, IntToFPUnit.io.resp.bits.uop.is_fencei
connect queue.io.enq.bits.uop.is_fence, IntToFPUnit.io.resp.bits.uop.is_fence
connect queue.io.enq.bits.uop.mem_signed, IntToFPUnit.io.resp.bits.uop.mem_signed
connect queue.io.enq.bits.uop.mem_size, IntToFPUnit.io.resp.bits.uop.mem_size
connect queue.io.enq.bits.uop.mem_cmd, IntToFPUnit.io.resp.bits.uop.mem_cmd
connect queue.io.enq.bits.uop.bypassable, IntToFPUnit.io.resp.bits.uop.bypassable
connect queue.io.enq.bits.uop.exc_cause, IntToFPUnit.io.resp.bits.uop.exc_cause
connect queue.io.enq.bits.uop.exception, IntToFPUnit.io.resp.bits.uop.exception
connect queue.io.enq.bits.uop.stale_pdst, IntToFPUnit.io.resp.bits.uop.stale_pdst
connect queue.io.enq.bits.uop.ppred_busy, IntToFPUnit.io.resp.bits.uop.ppred_busy
connect queue.io.enq.bits.uop.prs3_busy, IntToFPUnit.io.resp.bits.uop.prs3_busy
connect queue.io.enq.bits.uop.prs2_busy, IntToFPUnit.io.resp.bits.uop.prs2_busy
connect queue.io.enq.bits.uop.prs1_busy, IntToFPUnit.io.resp.bits.uop.prs1_busy
connect queue.io.enq.bits.uop.ppred, IntToFPUnit.io.resp.bits.uop.ppred
connect queue.io.enq.bits.uop.prs3, IntToFPUnit.io.resp.bits.uop.prs3
connect queue.io.enq.bits.uop.prs2, IntToFPUnit.io.resp.bits.uop.prs2
connect queue.io.enq.bits.uop.prs1, IntToFPUnit.io.resp.bits.uop.prs1
connect queue.io.enq.bits.uop.pdst, IntToFPUnit.io.resp.bits.uop.pdst
connect queue.io.enq.bits.uop.rxq_idx, IntToFPUnit.io.resp.bits.uop.rxq_idx
connect queue.io.enq.bits.uop.stq_idx, IntToFPUnit.io.resp.bits.uop.stq_idx
connect queue.io.enq.bits.uop.ldq_idx, IntToFPUnit.io.resp.bits.uop.ldq_idx
connect queue.io.enq.bits.uop.rob_idx, IntToFPUnit.io.resp.bits.uop.rob_idx
connect queue.io.enq.bits.uop.csr_addr, IntToFPUnit.io.resp.bits.uop.csr_addr
connect queue.io.enq.bits.uop.imm_packed, IntToFPUnit.io.resp.bits.uop.imm_packed
connect queue.io.enq.bits.uop.taken, IntToFPUnit.io.resp.bits.uop.taken
connect queue.io.enq.bits.uop.pc_lob, IntToFPUnit.io.resp.bits.uop.pc_lob
connect queue.io.enq.bits.uop.edge_inst, IntToFPUnit.io.resp.bits.uop.edge_inst
connect queue.io.enq.bits.uop.ftq_idx, IntToFPUnit.io.resp.bits.uop.ftq_idx
connect queue.io.enq.bits.uop.br_tag, IntToFPUnit.io.resp.bits.uop.br_tag
connect queue.io.enq.bits.uop.br_mask, IntToFPUnit.io.resp.bits.uop.br_mask
connect queue.io.enq.bits.uop.is_sfb, IntToFPUnit.io.resp.bits.uop.is_sfb
connect queue.io.enq.bits.uop.is_jal, IntToFPUnit.io.resp.bits.uop.is_jal
connect queue.io.enq.bits.uop.is_jalr, IntToFPUnit.io.resp.bits.uop.is_jalr
connect queue.io.enq.bits.uop.is_br, IntToFPUnit.io.resp.bits.uop.is_br
connect queue.io.enq.bits.uop.iw_p2_poisoned, IntToFPUnit.io.resp.bits.uop.iw_p2_poisoned
connect queue.io.enq.bits.uop.iw_p1_poisoned, IntToFPUnit.io.resp.bits.uop.iw_p1_poisoned
connect queue.io.enq.bits.uop.iw_state, IntToFPUnit.io.resp.bits.uop.iw_state
connect queue.io.enq.bits.uop.ctrl.is_std, IntToFPUnit.io.resp.bits.uop.ctrl.is_std
connect queue.io.enq.bits.uop.ctrl.is_sta, IntToFPUnit.io.resp.bits.uop.ctrl.is_sta
connect queue.io.enq.bits.uop.ctrl.is_load, IntToFPUnit.io.resp.bits.uop.ctrl.is_load
connect queue.io.enq.bits.uop.ctrl.csr_cmd, IntToFPUnit.io.resp.bits.uop.ctrl.csr_cmd
connect queue.io.enq.bits.uop.ctrl.fcn_dw, IntToFPUnit.io.resp.bits.uop.ctrl.fcn_dw
connect queue.io.enq.bits.uop.ctrl.op_fcn, IntToFPUnit.io.resp.bits.uop.ctrl.op_fcn
connect queue.io.enq.bits.uop.ctrl.imm_sel, IntToFPUnit.io.resp.bits.uop.ctrl.imm_sel
connect queue.io.enq.bits.uop.ctrl.op2_sel, IntToFPUnit.io.resp.bits.uop.ctrl.op2_sel
connect queue.io.enq.bits.uop.ctrl.op1_sel, IntToFPUnit.io.resp.bits.uop.ctrl.op1_sel
connect queue.io.enq.bits.uop.ctrl.br_type, IntToFPUnit.io.resp.bits.uop.ctrl.br_type
connect queue.io.enq.bits.uop.fu_code, IntToFPUnit.io.resp.bits.uop.fu_code
connect queue.io.enq.bits.uop.iq_type, IntToFPUnit.io.resp.bits.uop.iq_type
connect queue.io.enq.bits.uop.debug_pc, IntToFPUnit.io.resp.bits.uop.debug_pc
connect queue.io.enq.bits.uop.is_rvc, IntToFPUnit.io.resp.bits.uop.is_rvc
connect queue.io.enq.bits.uop.debug_inst, IntToFPUnit.io.resp.bits.uop.debug_inst
connect queue.io.enq.bits.uop.inst, IntToFPUnit.io.resp.bits.uop.inst
connect queue.io.enq.bits.uop.uopc, IntToFPUnit.io.resp.bits.uop.uopc
connect queue.io.enq.bits.data, IntToFPUnit.io.resp.bits.data
connect queue.io.enq.bits.predicated, IntToFPUnit.io.resp.bits.predicated
connect queue.io.enq.bits.fflags.bits.flags, IntToFPUnit.io.resp.bits.fflags.bits.flags
connect queue.io.enq.bits.fflags.bits.uop.debug_tsrc, IntToFPUnit.io.resp.bits.fflags.bits.uop.debug_tsrc
connect queue.io.enq.bits.fflags.bits.uop.debug_fsrc, IntToFPUnit.io.resp.bits.fflags.bits.uop.debug_fsrc
connect queue.io.enq.bits.fflags.bits.uop.bp_xcpt_if, IntToFPUnit.io.resp.bits.fflags.bits.uop.bp_xcpt_if
connect queue.io.enq.bits.fflags.bits.uop.bp_debug_if, IntToFPUnit.io.resp.bits.fflags.bits.uop.bp_debug_if
connect queue.io.enq.bits.fflags.bits.uop.xcpt_ma_if, IntToFPUnit.io.resp.bits.fflags.bits.uop.xcpt_ma_if
connect queue.io.enq.bits.fflags.bits.uop.xcpt_ae_if, IntToFPUnit.io.resp.bits.fflags.bits.uop.xcpt_ae_if
connect queue.io.enq.bits.fflags.bits.uop.xcpt_pf_if, IntToFPUnit.io.resp.bits.fflags.bits.uop.xcpt_pf_if
connect queue.io.enq.bits.fflags.bits.uop.fp_single, IntToFPUnit.io.resp.bits.fflags.bits.uop.fp_single
connect queue.io.enq.bits.fflags.bits.uop.fp_val, IntToFPUnit.io.resp.bits.fflags.bits.uop.fp_val
connect queue.io.enq.bits.fflags.bits.uop.frs3_en, IntToFPUnit.io.resp.bits.fflags.bits.uop.frs3_en
connect queue.io.enq.bits.fflags.bits.uop.lrs2_rtype, IntToFPUnit.io.resp.bits.fflags.bits.uop.lrs2_rtype
connect queue.io.enq.bits.fflags.bits.uop.lrs1_rtype, IntToFPUnit.io.resp.bits.fflags.bits.uop.lrs1_rtype
connect queue.io.enq.bits.fflags.bits.uop.dst_rtype, IntToFPUnit.io.resp.bits.fflags.bits.uop.dst_rtype
connect queue.io.enq.bits.fflags.bits.uop.ldst_val, IntToFPUnit.io.resp.bits.fflags.bits.uop.ldst_val
connect queue.io.enq.bits.fflags.bits.uop.lrs3, IntToFPUnit.io.resp.bits.fflags.bits.uop.lrs3
connect queue.io.enq.bits.fflags.bits.uop.lrs2, IntToFPUnit.io.resp.bits.fflags.bits.uop.lrs2
connect queue.io.enq.bits.fflags.bits.uop.lrs1, IntToFPUnit.io.resp.bits.fflags.bits.uop.lrs1
connect queue.io.enq.bits.fflags.bits.uop.ldst, IntToFPUnit.io.resp.bits.fflags.bits.uop.ldst
connect queue.io.enq.bits.fflags.bits.uop.ldst_is_rs1, IntToFPUnit.io.resp.bits.fflags.bits.uop.ldst_is_rs1
connect queue.io.enq.bits.fflags.bits.uop.flush_on_commit, IntToFPUnit.io.resp.bits.fflags.bits.uop.flush_on_commit
connect queue.io.enq.bits.fflags.bits.uop.is_unique, IntToFPUnit.io.resp.bits.fflags.bits.uop.is_unique
connect queue.io.enq.bits.fflags.bits.uop.is_sys_pc2epc, IntToFPUnit.io.resp.bits.fflags.bits.uop.is_sys_pc2epc
connect queue.io.enq.bits.fflags.bits.uop.uses_stq, IntToFPUnit.io.resp.bits.fflags.bits.uop.uses_stq
connect queue.io.enq.bits.fflags.bits.uop.uses_ldq, IntToFPUnit.io.resp.bits.fflags.bits.uop.uses_ldq
connect queue.io.enq.bits.fflags.bits.uop.is_amo, IntToFPUnit.io.resp.bits.fflags.bits.uop.is_amo
connect queue.io.enq.bits.fflags.bits.uop.is_fencei, IntToFPUnit.io.resp.bits.fflags.bits.uop.is_fencei
connect queue.io.enq.bits.fflags.bits.uop.is_fence, IntToFPUnit.io.resp.bits.fflags.bits.uop.is_fence
connect queue.io.enq.bits.fflags.bits.uop.mem_signed, IntToFPUnit.io.resp.bits.fflags.bits.uop.mem_signed
connect queue.io.enq.bits.fflags.bits.uop.mem_size, IntToFPUnit.io.resp.bits.fflags.bits.uop.mem_size
connect queue.io.enq.bits.fflags.bits.uop.mem_cmd, IntToFPUnit.io.resp.bits.fflags.bits.uop.mem_cmd
connect queue.io.enq.bits.fflags.bits.uop.bypassable, IntToFPUnit.io.resp.bits.fflags.bits.uop.bypassable
connect queue.io.enq.bits.fflags.bits.uop.exc_cause, IntToFPUnit.io.resp.bits.fflags.bits.uop.exc_cause
connect queue.io.enq.bits.fflags.bits.uop.exception, IntToFPUnit.io.resp.bits.fflags.bits.uop.exception
connect queue.io.enq.bits.fflags.bits.uop.stale_pdst, IntToFPUnit.io.resp.bits.fflags.bits.uop.stale_pdst
connect queue.io.enq.bits.fflags.bits.uop.ppred_busy, IntToFPUnit.io.resp.bits.fflags.bits.uop.ppred_busy
connect queue.io.enq.bits.fflags.bits.uop.prs3_busy, IntToFPUnit.io.resp.bits.fflags.bits.uop.prs3_busy
connect queue.io.enq.bits.fflags.bits.uop.prs2_busy, IntToFPUnit.io.resp.bits.fflags.bits.uop.prs2_busy
connect queue.io.enq.bits.fflags.bits.uop.prs1_busy, IntToFPUnit.io.resp.bits.fflags.bits.uop.prs1_busy
connect queue.io.enq.bits.fflags.bits.uop.ppred, IntToFPUnit.io.resp.bits.fflags.bits.uop.ppred
connect queue.io.enq.bits.fflags.bits.uop.prs3, IntToFPUnit.io.resp.bits.fflags.bits.uop.prs3
connect queue.io.enq.bits.fflags.bits.uop.prs2, IntToFPUnit.io.resp.bits.fflags.bits.uop.prs2
connect queue.io.enq.bits.fflags.bits.uop.prs1, IntToFPUnit.io.resp.bits.fflags.bits.uop.prs1
connect queue.io.enq.bits.fflags.bits.uop.pdst, IntToFPUnit.io.resp.bits.fflags.bits.uop.pdst
connect queue.io.enq.bits.fflags.bits.uop.rxq_idx, IntToFPUnit.io.resp.bits.fflags.bits.uop.rxq_idx
connect queue.io.enq.bits.fflags.bits.uop.stq_idx, IntToFPUnit.io.resp.bits.fflags.bits.uop.stq_idx
connect queue.io.enq.bits.fflags.bits.uop.ldq_idx, IntToFPUnit.io.resp.bits.fflags.bits.uop.ldq_idx
connect queue.io.enq.bits.fflags.bits.uop.rob_idx, IntToFPUnit.io.resp.bits.fflags.bits.uop.rob_idx
connect queue.io.enq.bits.fflags.bits.uop.csr_addr, IntToFPUnit.io.resp.bits.fflags.bits.uop.csr_addr
connect queue.io.enq.bits.fflags.bits.uop.imm_packed, IntToFPUnit.io.resp.bits.fflags.bits.uop.imm_packed
connect queue.io.enq.bits.fflags.bits.uop.taken, IntToFPUnit.io.resp.bits.fflags.bits.uop.taken
connect queue.io.enq.bits.fflags.bits.uop.pc_lob, IntToFPUnit.io.resp.bits.fflags.bits.uop.pc_lob
connect queue.io.enq.bits.fflags.bits.uop.edge_inst, IntToFPUnit.io.resp.bits.fflags.bits.uop.edge_inst
connect queue.io.enq.bits.fflags.bits.uop.ftq_idx, IntToFPUnit.io.resp.bits.fflags.bits.uop.ftq_idx
connect queue.io.enq.bits.fflags.bits.uop.br_tag, IntToFPUnit.io.resp.bits.fflags.bits.uop.br_tag
connect queue.io.enq.bits.fflags.bits.uop.br_mask, IntToFPUnit.io.resp.bits.fflags.bits.uop.br_mask
connect queue.io.enq.bits.fflags.bits.uop.is_sfb, IntToFPUnit.io.resp.bits.fflags.bits.uop.is_sfb
connect queue.io.enq.bits.fflags.bits.uop.is_jal, IntToFPUnit.io.resp.bits.fflags.bits.uop.is_jal
connect queue.io.enq.bits.fflags.bits.uop.is_jalr, IntToFPUnit.io.resp.bits.fflags.bits.uop.is_jalr
connect queue.io.enq.bits.fflags.bits.uop.is_br, IntToFPUnit.io.resp.bits.fflags.bits.uop.is_br
connect queue.io.enq.bits.fflags.bits.uop.iw_p2_poisoned, IntToFPUnit.io.resp.bits.fflags.bits.uop.iw_p2_poisoned
connect queue.io.enq.bits.fflags.bits.uop.iw_p1_poisoned, IntToFPUnit.io.resp.bits.fflags.bits.uop.iw_p1_poisoned
connect queue.io.enq.bits.fflags.bits.uop.iw_state, IntToFPUnit.io.resp.bits.fflags.bits.uop.iw_state
connect queue.io.enq.bits.fflags.bits.uop.ctrl.is_std, IntToFPUnit.io.resp.bits.fflags.bits.uop.ctrl.is_std
connect queue.io.enq.bits.fflags.bits.uop.ctrl.is_sta, IntToFPUnit.io.resp.bits.fflags.bits.uop.ctrl.is_sta
connect queue.io.enq.bits.fflags.bits.uop.ctrl.is_load, IntToFPUnit.io.resp.bits.fflags.bits.uop.ctrl.is_load
connect queue.io.enq.bits.fflags.bits.uop.ctrl.csr_cmd, IntToFPUnit.io.resp.bits.fflags.bits.uop.ctrl.csr_cmd
connect queue.io.enq.bits.fflags.bits.uop.ctrl.fcn_dw, IntToFPUnit.io.resp.bits.fflags.bits.uop.ctrl.fcn_dw
connect queue.io.enq.bits.fflags.bits.uop.ctrl.op_fcn, IntToFPUnit.io.resp.bits.fflags.bits.uop.ctrl.op_fcn
connect queue.io.enq.bits.fflags.bits.uop.ctrl.imm_sel, IntToFPUnit.io.resp.bits.fflags.bits.uop.ctrl.imm_sel
connect queue.io.enq.bits.fflags.bits.uop.ctrl.op2_sel, IntToFPUnit.io.resp.bits.fflags.bits.uop.ctrl.op2_sel
connect queue.io.enq.bits.fflags.bits.uop.ctrl.op1_sel, IntToFPUnit.io.resp.bits.fflags.bits.uop.ctrl.op1_sel
connect queue.io.enq.bits.fflags.bits.uop.ctrl.br_type, IntToFPUnit.io.resp.bits.fflags.bits.uop.ctrl.br_type
connect queue.io.enq.bits.fflags.bits.uop.fu_code, IntToFPUnit.io.resp.bits.fflags.bits.uop.fu_code
connect queue.io.enq.bits.fflags.bits.uop.iq_type, IntToFPUnit.io.resp.bits.fflags.bits.uop.iq_type
connect queue.io.enq.bits.fflags.bits.uop.debug_pc, IntToFPUnit.io.resp.bits.fflags.bits.uop.debug_pc
connect queue.io.enq.bits.fflags.bits.uop.is_rvc, IntToFPUnit.io.resp.bits.fflags.bits.uop.is_rvc
connect queue.io.enq.bits.fflags.bits.uop.debug_inst, IntToFPUnit.io.resp.bits.fflags.bits.uop.debug_inst
connect queue.io.enq.bits.fflags.bits.uop.inst, IntToFPUnit.io.resp.bits.fflags.bits.uop.inst
connect queue.io.enq.bits.fflags.bits.uop.uopc, IntToFPUnit.io.resp.bits.fflags.bits.uop.uopc
connect queue.io.enq.bits.fflags.valid, IntToFPUnit.io.resp.bits.fflags.valid
connect queue.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect queue.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect queue.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect queue.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect queue.io.brupdate.b2.taken, io.brupdate.b2.taken
connect queue.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect queue.io.brupdate.b2.valid, io.brupdate.b2.valid
connect queue.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect queue.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect queue.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect queue.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect queue.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect queue.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect queue.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect queue.io.brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect queue.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect queue.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect queue.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect queue.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect queue.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect queue.io.brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect queue.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect queue.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect queue.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect queue.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect queue.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect queue.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect queue.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect queue.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect queue.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect queue.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect queue.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect queue.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect queue.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect queue.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect queue.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect queue.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect queue.io.brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect queue.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect queue.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect queue.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect queue.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect queue.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect queue.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect queue.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect queue.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect queue.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect queue.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect queue.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect queue.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect queue.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect queue.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect queue.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect queue.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect queue.io.brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect queue.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect queue.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect queue.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect queue.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect queue.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect queue.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect queue.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect queue.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect queue.io.brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect queue.io.brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect queue.io.brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect queue.io.brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect queue.io.brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect queue.io.brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect queue.io.brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect queue.io.brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect queue.io.brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect queue.io.brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect queue.io.brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect queue.io.brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect queue.io.brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect queue.io.brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect queue.io.brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect queue.io.brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect queue.io.brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect queue.io.brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect queue.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect queue.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect queue.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect queue.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect queue.io.brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect queue.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect queue.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect queue.io.flush, io.req.bits.kill
connect io.ll_fresp.bits, queue.io.deq.bits
connect io.ll_fresp.valid, queue.io.deq.valid
connect queue.io.deq.ready, io.ll_fresp.ready
node _ifpu_busy_T = eq(queue.io.empty, UInt<1>(0h0))
connect ifpu_busy, _ifpu_busy_T
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(queue.io.enq.ready, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at execution-unit.scala:359 assert (queue.io.enq.ready)\n") : printf_1
assert(clock, queue.io.enq.ready, UInt<1>(0h1), "") : assert_1
wire div_resp_val : UInt<1>
connect div_resp_val, UInt<1>(0h0)
inst DivUnit of DivUnit
connect DivUnit.clock, clock
connect DivUnit.reset, reset
invalidate DivUnit.io.brupdate.b2.target_offset
invalidate DivUnit.io.brupdate.b2.jalr_target
invalidate DivUnit.io.brupdate.b2.pc_sel
invalidate DivUnit.io.brupdate.b2.cfi_type
invalidate DivUnit.io.brupdate.b2.taken
invalidate DivUnit.io.brupdate.b2.mispredict
invalidate DivUnit.io.brupdate.b2.valid
invalidate DivUnit.io.brupdate.b2.uop.debug_tsrc
invalidate DivUnit.io.brupdate.b2.uop.debug_fsrc
invalidate DivUnit.io.brupdate.b2.uop.bp_xcpt_if
invalidate DivUnit.io.brupdate.b2.uop.bp_debug_if
invalidate DivUnit.io.brupdate.b2.uop.xcpt_ma_if
invalidate DivUnit.io.brupdate.b2.uop.xcpt_ae_if
invalidate DivUnit.io.brupdate.b2.uop.xcpt_pf_if
invalidate DivUnit.io.brupdate.b2.uop.fp_single
invalidate DivUnit.io.brupdate.b2.uop.fp_val
invalidate DivUnit.io.brupdate.b2.uop.frs3_en
invalidate DivUnit.io.brupdate.b2.uop.lrs2_rtype
invalidate DivUnit.io.brupdate.b2.uop.lrs1_rtype
invalidate DivUnit.io.brupdate.b2.uop.dst_rtype
invalidate DivUnit.io.brupdate.b2.uop.ldst_val
invalidate DivUnit.io.brupdate.b2.uop.lrs3
invalidate DivUnit.io.brupdate.b2.uop.lrs2
invalidate DivUnit.io.brupdate.b2.uop.lrs1
invalidate DivUnit.io.brupdate.b2.uop.ldst
invalidate DivUnit.io.brupdate.b2.uop.ldst_is_rs1
invalidate DivUnit.io.brupdate.b2.uop.flush_on_commit
invalidate DivUnit.io.brupdate.b2.uop.is_unique
invalidate DivUnit.io.brupdate.b2.uop.is_sys_pc2epc
invalidate DivUnit.io.brupdate.b2.uop.uses_stq
invalidate DivUnit.io.brupdate.b2.uop.uses_ldq
invalidate DivUnit.io.brupdate.b2.uop.is_amo
invalidate DivUnit.io.brupdate.b2.uop.is_fencei
invalidate DivUnit.io.brupdate.b2.uop.is_fence
invalidate DivUnit.io.brupdate.b2.uop.mem_signed
invalidate DivUnit.io.brupdate.b2.uop.mem_size
invalidate DivUnit.io.brupdate.b2.uop.mem_cmd
invalidate DivUnit.io.brupdate.b2.uop.bypassable
invalidate DivUnit.io.brupdate.b2.uop.exc_cause
invalidate DivUnit.io.brupdate.b2.uop.exception
invalidate DivUnit.io.brupdate.b2.uop.stale_pdst
invalidate DivUnit.io.brupdate.b2.uop.ppred_busy
invalidate DivUnit.io.brupdate.b2.uop.prs3_busy
invalidate DivUnit.io.brupdate.b2.uop.prs2_busy
invalidate DivUnit.io.brupdate.b2.uop.prs1_busy
invalidate DivUnit.io.brupdate.b2.uop.ppred
invalidate DivUnit.io.brupdate.b2.uop.prs3
invalidate DivUnit.io.brupdate.b2.uop.prs2
invalidate DivUnit.io.brupdate.b2.uop.prs1
invalidate DivUnit.io.brupdate.b2.uop.pdst
invalidate DivUnit.io.brupdate.b2.uop.rxq_idx
invalidate DivUnit.io.brupdate.b2.uop.stq_idx
invalidate DivUnit.io.brupdate.b2.uop.ldq_idx
invalidate DivUnit.io.brupdate.b2.uop.rob_idx
invalidate DivUnit.io.brupdate.b2.uop.csr_addr
invalidate DivUnit.io.brupdate.b2.uop.imm_packed
invalidate DivUnit.io.brupdate.b2.uop.taken
invalidate DivUnit.io.brupdate.b2.uop.pc_lob
invalidate DivUnit.io.brupdate.b2.uop.edge_inst
invalidate DivUnit.io.brupdate.b2.uop.ftq_idx
invalidate DivUnit.io.brupdate.b2.uop.br_tag
invalidate DivUnit.io.brupdate.b2.uop.br_mask
invalidate DivUnit.io.brupdate.b2.uop.is_sfb
invalidate DivUnit.io.brupdate.b2.uop.is_jal
invalidate DivUnit.io.brupdate.b2.uop.is_jalr
invalidate DivUnit.io.brupdate.b2.uop.is_br
invalidate DivUnit.io.brupdate.b2.uop.iw_p2_poisoned
invalidate DivUnit.io.brupdate.b2.uop.iw_p1_poisoned
invalidate DivUnit.io.brupdate.b2.uop.iw_state
invalidate DivUnit.io.brupdate.b2.uop.ctrl.is_std
invalidate DivUnit.io.brupdate.b2.uop.ctrl.is_sta
invalidate DivUnit.io.brupdate.b2.uop.ctrl.is_load
invalidate DivUnit.io.brupdate.b2.uop.ctrl.csr_cmd
invalidate DivUnit.io.brupdate.b2.uop.ctrl.fcn_dw
invalidate DivUnit.io.brupdate.b2.uop.ctrl.op_fcn
invalidate DivUnit.io.brupdate.b2.uop.ctrl.imm_sel
invalidate DivUnit.io.brupdate.b2.uop.ctrl.op2_sel
invalidate DivUnit.io.brupdate.b2.uop.ctrl.op1_sel
invalidate DivUnit.io.brupdate.b2.uop.ctrl.br_type
invalidate DivUnit.io.brupdate.b2.uop.fu_code
invalidate DivUnit.io.brupdate.b2.uop.iq_type
invalidate DivUnit.io.brupdate.b2.uop.debug_pc
invalidate DivUnit.io.brupdate.b2.uop.is_rvc
invalidate DivUnit.io.brupdate.b2.uop.debug_inst
invalidate DivUnit.io.brupdate.b2.uop.inst
invalidate DivUnit.io.brupdate.b2.uop.uopc
invalidate DivUnit.io.brupdate.b1.mispredict_mask
invalidate DivUnit.io.brupdate.b1.resolve_mask
invalidate DivUnit.io.resp.bits.sfence.bits.hg
invalidate DivUnit.io.resp.bits.sfence.bits.hv
invalidate DivUnit.io.resp.bits.sfence.bits.asid
invalidate DivUnit.io.resp.bits.sfence.bits.addr
invalidate DivUnit.io.resp.bits.sfence.bits.rs2
invalidate DivUnit.io.resp.bits.sfence.bits.rs1
invalidate DivUnit.io.resp.bits.sfence.valid
invalidate DivUnit.io.resp.bits.mxcpt.bits
invalidate DivUnit.io.resp.bits.mxcpt.valid
invalidate DivUnit.io.resp.bits.addr
invalidate DivUnit.io.resp.bits.fflags.bits.flags
invalidate DivUnit.io.resp.bits.fflags.bits.uop.debug_tsrc
invalidate DivUnit.io.resp.bits.fflags.bits.uop.debug_fsrc
invalidate DivUnit.io.resp.bits.fflags.bits.uop.bp_xcpt_if
invalidate DivUnit.io.resp.bits.fflags.bits.uop.bp_debug_if
invalidate DivUnit.io.resp.bits.fflags.bits.uop.xcpt_ma_if
invalidate DivUnit.io.resp.bits.fflags.bits.uop.xcpt_ae_if
invalidate DivUnit.io.resp.bits.fflags.bits.uop.xcpt_pf_if
invalidate DivUnit.io.resp.bits.fflags.bits.uop.fp_single
invalidate DivUnit.io.resp.bits.fflags.bits.uop.fp_val
invalidate DivUnit.io.resp.bits.fflags.bits.uop.frs3_en
invalidate DivUnit.io.resp.bits.fflags.bits.uop.lrs2_rtype
invalidate DivUnit.io.resp.bits.fflags.bits.uop.lrs1_rtype
invalidate DivUnit.io.resp.bits.fflags.bits.uop.dst_rtype
invalidate DivUnit.io.resp.bits.fflags.bits.uop.ldst_val
invalidate DivUnit.io.resp.bits.fflags.bits.uop.lrs3
invalidate DivUnit.io.resp.bits.fflags.bits.uop.lrs2
invalidate DivUnit.io.resp.bits.fflags.bits.uop.lrs1
invalidate DivUnit.io.resp.bits.fflags.bits.uop.ldst
invalidate DivUnit.io.resp.bits.fflags.bits.uop.ldst_is_rs1
invalidate DivUnit.io.resp.bits.fflags.bits.uop.flush_on_commit
invalidate DivUnit.io.resp.bits.fflags.bits.uop.is_unique
invalidate DivUnit.io.resp.bits.fflags.bits.uop.is_sys_pc2epc
invalidate DivUnit.io.resp.bits.fflags.bits.uop.uses_stq
invalidate DivUnit.io.resp.bits.fflags.bits.uop.uses_ldq
invalidate DivUnit.io.resp.bits.fflags.bits.uop.is_amo
invalidate DivUnit.io.resp.bits.fflags.bits.uop.is_fencei
invalidate DivUnit.io.resp.bits.fflags.bits.uop.is_fence
invalidate DivUnit.io.resp.bits.fflags.bits.uop.mem_signed
invalidate DivUnit.io.resp.bits.fflags.bits.uop.mem_size
invalidate DivUnit.io.resp.bits.fflags.bits.uop.mem_cmd
invalidate DivUnit.io.resp.bits.fflags.bits.uop.bypassable
invalidate DivUnit.io.resp.bits.fflags.bits.uop.exc_cause
invalidate DivUnit.io.resp.bits.fflags.bits.uop.exception
invalidate DivUnit.io.resp.bits.fflags.bits.uop.stale_pdst
invalidate DivUnit.io.resp.bits.fflags.bits.uop.ppred_busy
invalidate DivUnit.io.resp.bits.fflags.bits.uop.prs3_busy
invalidate DivUnit.io.resp.bits.fflags.bits.uop.prs2_busy
invalidate DivUnit.io.resp.bits.fflags.bits.uop.prs1_busy
invalidate DivUnit.io.resp.bits.fflags.bits.uop.ppred
invalidate DivUnit.io.resp.bits.fflags.bits.uop.prs3
invalidate DivUnit.io.resp.bits.fflags.bits.uop.prs2
invalidate DivUnit.io.resp.bits.fflags.bits.uop.prs1
invalidate DivUnit.io.resp.bits.fflags.bits.uop.pdst
invalidate DivUnit.io.resp.bits.fflags.bits.uop.rxq_idx
invalidate DivUnit.io.resp.bits.fflags.bits.uop.stq_idx
invalidate DivUnit.io.resp.bits.fflags.bits.uop.ldq_idx
invalidate DivUnit.io.resp.bits.fflags.bits.uop.rob_idx
invalidate DivUnit.io.resp.bits.fflags.bits.uop.csr_addr
invalidate DivUnit.io.resp.bits.fflags.bits.uop.imm_packed
invalidate DivUnit.io.resp.bits.fflags.bits.uop.taken
invalidate DivUnit.io.resp.bits.fflags.bits.uop.pc_lob
invalidate DivUnit.io.resp.bits.fflags.bits.uop.edge_inst
invalidate DivUnit.io.resp.bits.fflags.bits.uop.ftq_idx
invalidate DivUnit.io.resp.bits.fflags.bits.uop.br_tag
invalidate DivUnit.io.resp.bits.fflags.bits.uop.br_mask
invalidate DivUnit.io.resp.bits.fflags.bits.uop.is_sfb
invalidate DivUnit.io.resp.bits.fflags.bits.uop.is_jal
invalidate DivUnit.io.resp.bits.fflags.bits.uop.is_jalr
invalidate DivUnit.io.resp.bits.fflags.bits.uop.is_br
invalidate DivUnit.io.resp.bits.fflags.bits.uop.iw_p2_poisoned
invalidate DivUnit.io.resp.bits.fflags.bits.uop.iw_p1_poisoned
invalidate DivUnit.io.resp.bits.fflags.bits.uop.iw_state
invalidate DivUnit.io.resp.bits.fflags.bits.uop.ctrl.is_std
invalidate DivUnit.io.resp.bits.fflags.bits.uop.ctrl.is_sta
invalidate DivUnit.io.resp.bits.fflags.bits.uop.ctrl.is_load
invalidate DivUnit.io.resp.bits.fflags.bits.uop.ctrl.csr_cmd
invalidate DivUnit.io.resp.bits.fflags.bits.uop.ctrl.fcn_dw
invalidate DivUnit.io.resp.bits.fflags.bits.uop.ctrl.op_fcn
invalidate DivUnit.io.resp.bits.fflags.bits.uop.ctrl.imm_sel
invalidate DivUnit.io.resp.bits.fflags.bits.uop.ctrl.op2_sel
invalidate DivUnit.io.resp.bits.fflags.bits.uop.ctrl.op1_sel
invalidate DivUnit.io.resp.bits.fflags.bits.uop.ctrl.br_type
invalidate DivUnit.io.resp.bits.fflags.bits.uop.fu_code
invalidate DivUnit.io.resp.bits.fflags.bits.uop.iq_type
invalidate DivUnit.io.resp.bits.fflags.bits.uop.debug_pc
invalidate DivUnit.io.resp.bits.fflags.bits.uop.is_rvc
invalidate DivUnit.io.resp.bits.fflags.bits.uop.debug_inst
invalidate DivUnit.io.resp.bits.fflags.bits.uop.inst
invalidate DivUnit.io.resp.bits.fflags.bits.uop.uopc
invalidate DivUnit.io.resp.bits.fflags.valid
invalidate DivUnit.io.resp.bits.data
invalidate DivUnit.io.resp.bits.predicated
invalidate DivUnit.io.resp.bits.uop.debug_tsrc
invalidate DivUnit.io.resp.bits.uop.debug_fsrc
invalidate DivUnit.io.resp.bits.uop.bp_xcpt_if
invalidate DivUnit.io.resp.bits.uop.bp_debug_if
invalidate DivUnit.io.resp.bits.uop.xcpt_ma_if
invalidate DivUnit.io.resp.bits.uop.xcpt_ae_if
invalidate DivUnit.io.resp.bits.uop.xcpt_pf_if
invalidate DivUnit.io.resp.bits.uop.fp_single
invalidate DivUnit.io.resp.bits.uop.fp_val
invalidate DivUnit.io.resp.bits.uop.frs3_en
invalidate DivUnit.io.resp.bits.uop.lrs2_rtype
invalidate DivUnit.io.resp.bits.uop.lrs1_rtype
invalidate DivUnit.io.resp.bits.uop.dst_rtype
invalidate DivUnit.io.resp.bits.uop.ldst_val
invalidate DivUnit.io.resp.bits.uop.lrs3
invalidate DivUnit.io.resp.bits.uop.lrs2
invalidate DivUnit.io.resp.bits.uop.lrs1
invalidate DivUnit.io.resp.bits.uop.ldst
invalidate DivUnit.io.resp.bits.uop.ldst_is_rs1
invalidate DivUnit.io.resp.bits.uop.flush_on_commit
invalidate DivUnit.io.resp.bits.uop.is_unique
invalidate DivUnit.io.resp.bits.uop.is_sys_pc2epc
invalidate DivUnit.io.resp.bits.uop.uses_stq
invalidate DivUnit.io.resp.bits.uop.uses_ldq
invalidate DivUnit.io.resp.bits.uop.is_amo
invalidate DivUnit.io.resp.bits.uop.is_fencei
invalidate DivUnit.io.resp.bits.uop.is_fence
invalidate DivUnit.io.resp.bits.uop.mem_signed
invalidate DivUnit.io.resp.bits.uop.mem_size
invalidate DivUnit.io.resp.bits.uop.mem_cmd
invalidate DivUnit.io.resp.bits.uop.bypassable
invalidate DivUnit.io.resp.bits.uop.exc_cause
invalidate DivUnit.io.resp.bits.uop.exception
invalidate DivUnit.io.resp.bits.uop.stale_pdst
invalidate DivUnit.io.resp.bits.uop.ppred_busy
invalidate DivUnit.io.resp.bits.uop.prs3_busy
invalidate DivUnit.io.resp.bits.uop.prs2_busy
invalidate DivUnit.io.resp.bits.uop.prs1_busy
invalidate DivUnit.io.resp.bits.uop.ppred
invalidate DivUnit.io.resp.bits.uop.prs3
invalidate DivUnit.io.resp.bits.uop.prs2
invalidate DivUnit.io.resp.bits.uop.prs1
invalidate DivUnit.io.resp.bits.uop.pdst
invalidate DivUnit.io.resp.bits.uop.rxq_idx
invalidate DivUnit.io.resp.bits.uop.stq_idx
invalidate DivUnit.io.resp.bits.uop.ldq_idx
invalidate DivUnit.io.resp.bits.uop.rob_idx
invalidate DivUnit.io.resp.bits.uop.csr_addr
invalidate DivUnit.io.resp.bits.uop.imm_packed
invalidate DivUnit.io.resp.bits.uop.taken
invalidate DivUnit.io.resp.bits.uop.pc_lob
invalidate DivUnit.io.resp.bits.uop.edge_inst
invalidate DivUnit.io.resp.bits.uop.ftq_idx
invalidate DivUnit.io.resp.bits.uop.br_tag
invalidate DivUnit.io.resp.bits.uop.br_mask
invalidate DivUnit.io.resp.bits.uop.is_sfb
invalidate DivUnit.io.resp.bits.uop.is_jal
invalidate DivUnit.io.resp.bits.uop.is_jalr
invalidate DivUnit.io.resp.bits.uop.is_br
invalidate DivUnit.io.resp.bits.uop.iw_p2_poisoned
invalidate DivUnit.io.resp.bits.uop.iw_p1_poisoned
invalidate DivUnit.io.resp.bits.uop.iw_state
invalidate DivUnit.io.resp.bits.uop.ctrl.is_std
invalidate DivUnit.io.resp.bits.uop.ctrl.is_sta
invalidate DivUnit.io.resp.bits.uop.ctrl.is_load
invalidate DivUnit.io.resp.bits.uop.ctrl.csr_cmd
invalidate DivUnit.io.resp.bits.uop.ctrl.fcn_dw
invalidate DivUnit.io.resp.bits.uop.ctrl.op_fcn
invalidate DivUnit.io.resp.bits.uop.ctrl.imm_sel
invalidate DivUnit.io.resp.bits.uop.ctrl.op2_sel
invalidate DivUnit.io.resp.bits.uop.ctrl.op1_sel
invalidate DivUnit.io.resp.bits.uop.ctrl.br_type
invalidate DivUnit.io.resp.bits.uop.fu_code
invalidate DivUnit.io.resp.bits.uop.iq_type
invalidate DivUnit.io.resp.bits.uop.debug_pc
invalidate DivUnit.io.resp.bits.uop.is_rvc
invalidate DivUnit.io.resp.bits.uop.debug_inst
invalidate DivUnit.io.resp.bits.uop.inst
invalidate DivUnit.io.resp.bits.uop.uopc
invalidate DivUnit.io.resp.valid
invalidate DivUnit.io.resp.ready
invalidate DivUnit.io.req.bits.kill
invalidate DivUnit.io.req.bits.pred_data
invalidate DivUnit.io.req.bits.rs3_data
invalidate DivUnit.io.req.bits.rs2_data
invalidate DivUnit.io.req.bits.rs1_data
invalidate DivUnit.io.req.bits.uop.debug_tsrc
invalidate DivUnit.io.req.bits.uop.debug_fsrc
invalidate DivUnit.io.req.bits.uop.bp_xcpt_if
invalidate DivUnit.io.req.bits.uop.bp_debug_if
invalidate DivUnit.io.req.bits.uop.xcpt_ma_if
invalidate DivUnit.io.req.bits.uop.xcpt_ae_if
invalidate DivUnit.io.req.bits.uop.xcpt_pf_if
invalidate DivUnit.io.req.bits.uop.fp_single
invalidate DivUnit.io.req.bits.uop.fp_val
invalidate DivUnit.io.req.bits.uop.frs3_en
invalidate DivUnit.io.req.bits.uop.lrs2_rtype
invalidate DivUnit.io.req.bits.uop.lrs1_rtype
invalidate DivUnit.io.req.bits.uop.dst_rtype
invalidate DivUnit.io.req.bits.uop.ldst_val
invalidate DivUnit.io.req.bits.uop.lrs3
invalidate DivUnit.io.req.bits.uop.lrs2
invalidate DivUnit.io.req.bits.uop.lrs1
invalidate DivUnit.io.req.bits.uop.ldst
invalidate DivUnit.io.req.bits.uop.ldst_is_rs1
invalidate DivUnit.io.req.bits.uop.flush_on_commit
invalidate DivUnit.io.req.bits.uop.is_unique
invalidate DivUnit.io.req.bits.uop.is_sys_pc2epc
invalidate DivUnit.io.req.bits.uop.uses_stq
invalidate DivUnit.io.req.bits.uop.uses_ldq
invalidate DivUnit.io.req.bits.uop.is_amo
invalidate DivUnit.io.req.bits.uop.is_fencei
invalidate DivUnit.io.req.bits.uop.is_fence
invalidate DivUnit.io.req.bits.uop.mem_signed
invalidate DivUnit.io.req.bits.uop.mem_size
invalidate DivUnit.io.req.bits.uop.mem_cmd
invalidate DivUnit.io.req.bits.uop.bypassable
invalidate DivUnit.io.req.bits.uop.exc_cause
invalidate DivUnit.io.req.bits.uop.exception
invalidate DivUnit.io.req.bits.uop.stale_pdst
invalidate DivUnit.io.req.bits.uop.ppred_busy
invalidate DivUnit.io.req.bits.uop.prs3_busy
invalidate DivUnit.io.req.bits.uop.prs2_busy
invalidate DivUnit.io.req.bits.uop.prs1_busy
invalidate DivUnit.io.req.bits.uop.ppred
invalidate DivUnit.io.req.bits.uop.prs3
invalidate DivUnit.io.req.bits.uop.prs2
invalidate DivUnit.io.req.bits.uop.prs1
invalidate DivUnit.io.req.bits.uop.pdst
invalidate DivUnit.io.req.bits.uop.rxq_idx
invalidate DivUnit.io.req.bits.uop.stq_idx
invalidate DivUnit.io.req.bits.uop.ldq_idx
invalidate DivUnit.io.req.bits.uop.rob_idx
invalidate DivUnit.io.req.bits.uop.csr_addr
invalidate DivUnit.io.req.bits.uop.imm_packed
invalidate DivUnit.io.req.bits.uop.taken
invalidate DivUnit.io.req.bits.uop.pc_lob
invalidate DivUnit.io.req.bits.uop.edge_inst
invalidate DivUnit.io.req.bits.uop.ftq_idx
invalidate DivUnit.io.req.bits.uop.br_tag
invalidate DivUnit.io.req.bits.uop.br_mask
invalidate DivUnit.io.req.bits.uop.is_sfb
invalidate DivUnit.io.req.bits.uop.is_jal
invalidate DivUnit.io.req.bits.uop.is_jalr
invalidate DivUnit.io.req.bits.uop.is_br
invalidate DivUnit.io.req.bits.uop.iw_p2_poisoned
invalidate DivUnit.io.req.bits.uop.iw_p1_poisoned
invalidate DivUnit.io.req.bits.uop.iw_state
invalidate DivUnit.io.req.bits.uop.ctrl.is_std
invalidate DivUnit.io.req.bits.uop.ctrl.is_sta
invalidate DivUnit.io.req.bits.uop.ctrl.is_load
invalidate DivUnit.io.req.bits.uop.ctrl.csr_cmd
invalidate DivUnit.io.req.bits.uop.ctrl.fcn_dw
invalidate DivUnit.io.req.bits.uop.ctrl.op_fcn
invalidate DivUnit.io.req.bits.uop.ctrl.imm_sel
invalidate DivUnit.io.req.bits.uop.ctrl.op2_sel
invalidate DivUnit.io.req.bits.uop.ctrl.op1_sel
invalidate DivUnit.io.req.bits.uop.ctrl.br_type
invalidate DivUnit.io.req.bits.uop.fu_code
invalidate DivUnit.io.req.bits.uop.iq_type
invalidate DivUnit.io.req.bits.uop.debug_pc
invalidate DivUnit.io.req.bits.uop.is_rvc
invalidate DivUnit.io.req.bits.uop.debug_inst
invalidate DivUnit.io.req.bits.uop.inst
invalidate DivUnit.io.req.bits.uop.uopc
invalidate DivUnit.io.req.valid
invalidate DivUnit.io.req.ready
node _T_20 = and(io.req.bits.uop.fu_code, UInt<10>(0h10))
node _T_21 = neq(_T_20, UInt<1>(0h0))
node _T_22 = and(io.req.valid, _T_21)
node _T_23 = and(_T_22, UInt<1>(0h1))
connect DivUnit.io.req.valid, _T_23
connect DivUnit.io.req.bits.uop.debug_tsrc, io.req.bits.uop.debug_tsrc
connect DivUnit.io.req.bits.uop.debug_fsrc, io.req.bits.uop.debug_fsrc
connect DivUnit.io.req.bits.uop.bp_xcpt_if, io.req.bits.uop.bp_xcpt_if
connect DivUnit.io.req.bits.uop.bp_debug_if, io.req.bits.uop.bp_debug_if
connect DivUnit.io.req.bits.uop.xcpt_ma_if, io.req.bits.uop.xcpt_ma_if
connect DivUnit.io.req.bits.uop.xcpt_ae_if, io.req.bits.uop.xcpt_ae_if
connect DivUnit.io.req.bits.uop.xcpt_pf_if, io.req.bits.uop.xcpt_pf_if
connect DivUnit.io.req.bits.uop.fp_single, io.req.bits.uop.fp_single
connect DivUnit.io.req.bits.uop.fp_val, io.req.bits.uop.fp_val
connect DivUnit.io.req.bits.uop.frs3_en, io.req.bits.uop.frs3_en
connect DivUnit.io.req.bits.uop.lrs2_rtype, io.req.bits.uop.lrs2_rtype
connect DivUnit.io.req.bits.uop.lrs1_rtype, io.req.bits.uop.lrs1_rtype
connect DivUnit.io.req.bits.uop.dst_rtype, io.req.bits.uop.dst_rtype
connect DivUnit.io.req.bits.uop.ldst_val, io.req.bits.uop.ldst_val
connect DivUnit.io.req.bits.uop.lrs3, io.req.bits.uop.lrs3
connect DivUnit.io.req.bits.uop.lrs2, io.req.bits.uop.lrs2
connect DivUnit.io.req.bits.uop.lrs1, io.req.bits.uop.lrs1
connect DivUnit.io.req.bits.uop.ldst, io.req.bits.uop.ldst
connect DivUnit.io.req.bits.uop.ldst_is_rs1, io.req.bits.uop.ldst_is_rs1
connect DivUnit.io.req.bits.uop.flush_on_commit, io.req.bits.uop.flush_on_commit
connect DivUnit.io.req.bits.uop.is_unique, io.req.bits.uop.is_unique
connect DivUnit.io.req.bits.uop.is_sys_pc2epc, io.req.bits.uop.is_sys_pc2epc
connect DivUnit.io.req.bits.uop.uses_stq, io.req.bits.uop.uses_stq
connect DivUnit.io.req.bits.uop.uses_ldq, io.req.bits.uop.uses_ldq
connect DivUnit.io.req.bits.uop.is_amo, io.req.bits.uop.is_amo
connect DivUnit.io.req.bits.uop.is_fencei, io.req.bits.uop.is_fencei
connect DivUnit.io.req.bits.uop.is_fence, io.req.bits.uop.is_fence
connect DivUnit.io.req.bits.uop.mem_signed, io.req.bits.uop.mem_signed
connect DivUnit.io.req.bits.uop.mem_size, io.req.bits.uop.mem_size
connect DivUnit.io.req.bits.uop.mem_cmd, io.req.bits.uop.mem_cmd
connect DivUnit.io.req.bits.uop.bypassable, io.req.bits.uop.bypassable
connect DivUnit.io.req.bits.uop.exc_cause, io.req.bits.uop.exc_cause
connect DivUnit.io.req.bits.uop.exception, io.req.bits.uop.exception
connect DivUnit.io.req.bits.uop.stale_pdst, io.req.bits.uop.stale_pdst
connect DivUnit.io.req.bits.uop.ppred_busy, io.req.bits.uop.ppred_busy
connect DivUnit.io.req.bits.uop.prs3_busy, io.req.bits.uop.prs3_busy
connect DivUnit.io.req.bits.uop.prs2_busy, io.req.bits.uop.prs2_busy
connect DivUnit.io.req.bits.uop.prs1_busy, io.req.bits.uop.prs1_busy
connect DivUnit.io.req.bits.uop.ppred, io.req.bits.uop.ppred
connect DivUnit.io.req.bits.uop.prs3, io.req.bits.uop.prs3
connect DivUnit.io.req.bits.uop.prs2, io.req.bits.uop.prs2
connect DivUnit.io.req.bits.uop.prs1, io.req.bits.uop.prs1
connect DivUnit.io.req.bits.uop.pdst, io.req.bits.uop.pdst
connect DivUnit.io.req.bits.uop.rxq_idx, io.req.bits.uop.rxq_idx
connect DivUnit.io.req.bits.uop.stq_idx, io.req.bits.uop.stq_idx
connect DivUnit.io.req.bits.uop.ldq_idx, io.req.bits.uop.ldq_idx
connect DivUnit.io.req.bits.uop.rob_idx, io.req.bits.uop.rob_idx
connect DivUnit.io.req.bits.uop.csr_addr, io.req.bits.uop.csr_addr
connect DivUnit.io.req.bits.uop.imm_packed, io.req.bits.uop.imm_packed
connect DivUnit.io.req.bits.uop.taken, io.req.bits.uop.taken
connect DivUnit.io.req.bits.uop.pc_lob, io.req.bits.uop.pc_lob
connect DivUnit.io.req.bits.uop.edge_inst, io.req.bits.uop.edge_inst
connect DivUnit.io.req.bits.uop.ftq_idx, io.req.bits.uop.ftq_idx
connect DivUnit.io.req.bits.uop.br_tag, io.req.bits.uop.br_tag
connect DivUnit.io.req.bits.uop.br_mask, io.req.bits.uop.br_mask
connect DivUnit.io.req.bits.uop.is_sfb, io.req.bits.uop.is_sfb
connect DivUnit.io.req.bits.uop.is_jal, io.req.bits.uop.is_jal
connect DivUnit.io.req.bits.uop.is_jalr, io.req.bits.uop.is_jalr
connect DivUnit.io.req.bits.uop.is_br, io.req.bits.uop.is_br
connect DivUnit.io.req.bits.uop.iw_p2_poisoned, io.req.bits.uop.iw_p2_poisoned
connect DivUnit.io.req.bits.uop.iw_p1_poisoned, io.req.bits.uop.iw_p1_poisoned
connect DivUnit.io.req.bits.uop.iw_state, io.req.bits.uop.iw_state
connect DivUnit.io.req.bits.uop.ctrl.is_std, io.req.bits.uop.ctrl.is_std
connect DivUnit.io.req.bits.uop.ctrl.is_sta, io.req.bits.uop.ctrl.is_sta
connect DivUnit.io.req.bits.uop.ctrl.is_load, io.req.bits.uop.ctrl.is_load
connect DivUnit.io.req.bits.uop.ctrl.csr_cmd, io.req.bits.uop.ctrl.csr_cmd
connect DivUnit.io.req.bits.uop.ctrl.fcn_dw, io.req.bits.uop.ctrl.fcn_dw
connect DivUnit.io.req.bits.uop.ctrl.op_fcn, io.req.bits.uop.ctrl.op_fcn
connect DivUnit.io.req.bits.uop.ctrl.imm_sel, io.req.bits.uop.ctrl.imm_sel
connect DivUnit.io.req.bits.uop.ctrl.op2_sel, io.req.bits.uop.ctrl.op2_sel
connect DivUnit.io.req.bits.uop.ctrl.op1_sel, io.req.bits.uop.ctrl.op1_sel
connect DivUnit.io.req.bits.uop.ctrl.br_type, io.req.bits.uop.ctrl.br_type
connect DivUnit.io.req.bits.uop.fu_code, io.req.bits.uop.fu_code
connect DivUnit.io.req.bits.uop.iq_type, io.req.bits.uop.iq_type
connect DivUnit.io.req.bits.uop.debug_pc, io.req.bits.uop.debug_pc
connect DivUnit.io.req.bits.uop.is_rvc, io.req.bits.uop.is_rvc
connect DivUnit.io.req.bits.uop.debug_inst, io.req.bits.uop.debug_inst
connect DivUnit.io.req.bits.uop.inst, io.req.bits.uop.inst
connect DivUnit.io.req.bits.uop.uopc, io.req.bits.uop.uopc
connect DivUnit.io.req.bits.rs1_data, io.req.bits.rs1_data
connect DivUnit.io.req.bits.rs2_data, io.req.bits.rs2_data
connect DivUnit.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect DivUnit.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect DivUnit.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect DivUnit.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect DivUnit.io.brupdate.b2.taken, io.brupdate.b2.taken
connect DivUnit.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect DivUnit.io.brupdate.b2.valid, io.brupdate.b2.valid
connect DivUnit.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect DivUnit.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect DivUnit.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect DivUnit.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect DivUnit.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect DivUnit.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect DivUnit.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect DivUnit.io.brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect DivUnit.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect DivUnit.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect DivUnit.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect DivUnit.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect DivUnit.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect DivUnit.io.brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect DivUnit.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect DivUnit.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect DivUnit.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect DivUnit.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect DivUnit.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect DivUnit.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect DivUnit.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect DivUnit.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect DivUnit.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect DivUnit.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect DivUnit.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect DivUnit.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect DivUnit.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect DivUnit.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect DivUnit.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect DivUnit.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect DivUnit.io.brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect DivUnit.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect DivUnit.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect DivUnit.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect DivUnit.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect DivUnit.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect DivUnit.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect DivUnit.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect DivUnit.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect DivUnit.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect DivUnit.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect DivUnit.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect DivUnit.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect DivUnit.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect DivUnit.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect DivUnit.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect DivUnit.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect DivUnit.io.brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect DivUnit.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect DivUnit.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect DivUnit.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect DivUnit.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect DivUnit.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect DivUnit.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect DivUnit.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect DivUnit.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect DivUnit.io.brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect DivUnit.io.brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect DivUnit.io.brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect DivUnit.io.brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect DivUnit.io.brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect DivUnit.io.brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect DivUnit.io.brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect DivUnit.io.brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect DivUnit.io.brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect DivUnit.io.brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect DivUnit.io.brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect DivUnit.io.brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect DivUnit.io.brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect DivUnit.io.brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect DivUnit.io.brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect DivUnit.io.brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect DivUnit.io.brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect DivUnit.io.brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect DivUnit.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect DivUnit.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect DivUnit.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect DivUnit.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect DivUnit.io.brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect DivUnit.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect DivUnit.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect DivUnit.io.req.bits.kill, io.req.bits.kill
node _T_24 = or(ALUUnit.io.resp.valid, PipelinedMulUnit.io.resp.valid)
node _T_25 = eq(_T_24, UInt<1>(0h0))
connect DivUnit.io.resp.ready, _T_25
connect div_resp_val, DivUnit.io.resp.valid
node _div_busy_T = eq(DivUnit.io.req.ready, UInt<1>(0h0))
node _div_busy_T_1 = and(io.req.bits.uop.fu_code, UInt<10>(0h10))
node _div_busy_T_2 = neq(_div_busy_T_1, UInt<1>(0h0))
node _div_busy_T_3 = and(io.req.valid, _div_busy_T_2)
node _div_busy_T_4 = or(_div_busy_T, _div_busy_T_3)
connect div_busy, _div_busy_T_4
node _io_iresp_valid_T = or(ALUUnit.io.resp.valid, PipelinedMulUnit.io.resp.valid)
node _io_iresp_valid_T_1 = or(_io_iresp_valid_T, DivUnit.io.resp.valid)
connect io.iresp.valid, _io_iresp_valid_T_1
node _io_iresp_bits_uop_T = mux(PipelinedMulUnit.io.resp.valid, PipelinedMulUnit.io.resp.bits.uop, DivUnit.io.resp.bits.uop)
node _io_iresp_bits_uop_T_1 = mux(ALUUnit.io.resp.valid, ALUUnit.io.resp.bits.uop, _io_iresp_bits_uop_T)
connect io.iresp.bits.uop, _io_iresp_bits_uop_T_1
node _io_iresp_bits_data_T = mux(PipelinedMulUnit.io.resp.valid, PipelinedMulUnit.io.resp.bits.data, DivUnit.io.resp.bits.data)
node _io_iresp_bits_data_T_1 = mux(ALUUnit.io.resp.valid, ALUUnit.io.resp.bits.data, _io_iresp_bits_data_T)
connect io.iresp.bits.data, _io_iresp_bits_data_T_1
node _io_iresp_bits_predicated_T = mux(PipelinedMulUnit.io.resp.valid, PipelinedMulUnit.io.resp.bits.predicated, DivUnit.io.resp.bits.predicated)
node _io_iresp_bits_predicated_T_1 = mux(ALUUnit.io.resp.valid, ALUUnit.io.resp.bits.predicated, _io_iresp_bits_predicated_T)
connect io.iresp.bits.predicated, _io_iresp_bits_predicated_T_1
node _io_iresp_bits_uop_csr_addr_sign_T = bits(ALUUnit.io.resp.bits.uop.imm_packed, 19, 19)
node io_iresp_bits_uop_csr_addr_sign = asSInt(_io_iresp_bits_uop_csr_addr_sign_T)
node _io_iresp_bits_uop_csr_addr_i30_20_T = eq(UInt<3>(0h0), UInt<3>(0h3))
node _io_iresp_bits_uop_csr_addr_i30_20_T_1 = bits(ALUUnit.io.resp.bits.uop.imm_packed, 18, 8)
node _io_iresp_bits_uop_csr_addr_i30_20_T_2 = asSInt(_io_iresp_bits_uop_csr_addr_i30_20_T_1)
node io_iresp_bits_uop_csr_addr_i30_20 = mux(_io_iresp_bits_uop_csr_addr_i30_20_T, _io_iresp_bits_uop_csr_addr_i30_20_T_2, io_iresp_bits_uop_csr_addr_sign)
node _io_iresp_bits_uop_csr_addr_i19_12_T = eq(UInt<3>(0h0), UInt<3>(0h3))
node _io_iresp_bits_uop_csr_addr_i19_12_T_1 = eq(UInt<3>(0h0), UInt<3>(0h4))
node _io_iresp_bits_uop_csr_addr_i19_12_T_2 = or(_io_iresp_bits_uop_csr_addr_i19_12_T, _io_iresp_bits_uop_csr_addr_i19_12_T_1)
node _io_iresp_bits_uop_csr_addr_i19_12_T_3 = bits(ALUUnit.io.resp.bits.uop.imm_packed, 7, 0)
node _io_iresp_bits_uop_csr_addr_i19_12_T_4 = asSInt(_io_iresp_bits_uop_csr_addr_i19_12_T_3)
node io_iresp_bits_uop_csr_addr_i19_12 = mux(_io_iresp_bits_uop_csr_addr_i19_12_T_2, _io_iresp_bits_uop_csr_addr_i19_12_T_4, io_iresp_bits_uop_csr_addr_sign)
node _io_iresp_bits_uop_csr_addr_i11_T = eq(UInt<3>(0h0), UInt<3>(0h3))
node _io_iresp_bits_uop_csr_addr_i11_T_1 = eq(UInt<3>(0h0), UInt<3>(0h4))
node _io_iresp_bits_uop_csr_addr_i11_T_2 = eq(UInt<3>(0h0), UInt<3>(0h2))
node _io_iresp_bits_uop_csr_addr_i11_T_3 = or(_io_iresp_bits_uop_csr_addr_i11_T_1, _io_iresp_bits_uop_csr_addr_i11_T_2)
node _io_iresp_bits_uop_csr_addr_i11_T_4 = bits(ALUUnit.io.resp.bits.uop.imm_packed, 8, 8)
node _io_iresp_bits_uop_csr_addr_i11_T_5 = asSInt(_io_iresp_bits_uop_csr_addr_i11_T_4)
node _io_iresp_bits_uop_csr_addr_i11_T_6 = mux(_io_iresp_bits_uop_csr_addr_i11_T_3, _io_iresp_bits_uop_csr_addr_i11_T_5, io_iresp_bits_uop_csr_addr_sign)
node io_iresp_bits_uop_csr_addr_i11 = mux(_io_iresp_bits_uop_csr_addr_i11_T, asSInt(UInt<1>(0h0)), _io_iresp_bits_uop_csr_addr_i11_T_6)
node _io_iresp_bits_uop_csr_addr_i10_5_T = eq(UInt<3>(0h0), UInt<3>(0h3))
node _io_iresp_bits_uop_csr_addr_i10_5_T_1 = bits(ALUUnit.io.resp.bits.uop.imm_packed, 18, 14)
node _io_iresp_bits_uop_csr_addr_i10_5_T_2 = asSInt(_io_iresp_bits_uop_csr_addr_i10_5_T_1)
node io_iresp_bits_uop_csr_addr_i10_5 = mux(_io_iresp_bits_uop_csr_addr_i10_5_T, asSInt(UInt<1>(0h0)), _io_iresp_bits_uop_csr_addr_i10_5_T_2)
node _io_iresp_bits_uop_csr_addr_i4_1_T = eq(UInt<3>(0h0), UInt<3>(0h3))
node _io_iresp_bits_uop_csr_addr_i4_1_T_1 = bits(ALUUnit.io.resp.bits.uop.imm_packed, 13, 9)
node _io_iresp_bits_uop_csr_addr_i4_1_T_2 = asSInt(_io_iresp_bits_uop_csr_addr_i4_1_T_1)
node io_iresp_bits_uop_csr_addr_i4_1 = mux(_io_iresp_bits_uop_csr_addr_i4_1_T, asSInt(UInt<1>(0h0)), _io_iresp_bits_uop_csr_addr_i4_1_T_2)
node _io_iresp_bits_uop_csr_addr_i0_T = eq(UInt<3>(0h0), UInt<3>(0h1))
node _io_iresp_bits_uop_csr_addr_i0_T_1 = eq(UInt<3>(0h0), UInt<3>(0h0))
node _io_iresp_bits_uop_csr_addr_i0_T_2 = or(_io_iresp_bits_uop_csr_addr_i0_T, _io_iresp_bits_uop_csr_addr_i0_T_1)
node _io_iresp_bits_uop_csr_addr_i0_T_3 = bits(ALUUnit.io.resp.bits.uop.imm_packed, 8, 8)
node _io_iresp_bits_uop_csr_addr_i0_T_4 = asSInt(_io_iresp_bits_uop_csr_addr_i0_T_3)
node io_iresp_bits_uop_csr_addr_i0 = mux(_io_iresp_bits_uop_csr_addr_i0_T_2, _io_iresp_bits_uop_csr_addr_i0_T_4, asSInt(UInt<1>(0h0)))
node io_iresp_bits_uop_csr_addr_lo_lo = asUInt(io_iresp_bits_uop_csr_addr_i0)
node io_iresp_bits_uop_csr_addr_lo_hi_lo = asUInt(io_iresp_bits_uop_csr_addr_i4_1)
node io_iresp_bits_uop_csr_addr_lo_hi_hi = asUInt(io_iresp_bits_uop_csr_addr_i10_5)
node io_iresp_bits_uop_csr_addr_lo_hi = cat(io_iresp_bits_uop_csr_addr_lo_hi_hi, io_iresp_bits_uop_csr_addr_lo_hi_lo)
node io_iresp_bits_uop_csr_addr_lo = cat(io_iresp_bits_uop_csr_addr_lo_hi, io_iresp_bits_uop_csr_addr_lo_lo)
node io_iresp_bits_uop_csr_addr_hi_lo_lo = asUInt(io_iresp_bits_uop_csr_addr_i11)
node io_iresp_bits_uop_csr_addr_hi_lo_hi = asUInt(io_iresp_bits_uop_csr_addr_i19_12)
node io_iresp_bits_uop_csr_addr_hi_lo = cat(io_iresp_bits_uop_csr_addr_hi_lo_hi, io_iresp_bits_uop_csr_addr_hi_lo_lo)
node io_iresp_bits_uop_csr_addr_hi_hi_lo = asUInt(io_iresp_bits_uop_csr_addr_i30_20)
node io_iresp_bits_uop_csr_addr_hi_hi_hi = asUInt(io_iresp_bits_uop_csr_addr_sign)
node io_iresp_bits_uop_csr_addr_hi_hi = cat(io_iresp_bits_uop_csr_addr_hi_hi_hi, io_iresp_bits_uop_csr_addr_hi_hi_lo)
node io_iresp_bits_uop_csr_addr_hi = cat(io_iresp_bits_uop_csr_addr_hi_hi, io_iresp_bits_uop_csr_addr_hi_lo)
node _io_iresp_bits_uop_csr_addr_T = cat(io_iresp_bits_uop_csr_addr_hi, io_iresp_bits_uop_csr_addr_lo)
node _io_iresp_bits_uop_csr_addr_T_1 = asSInt(_io_iresp_bits_uop_csr_addr_T)
node _io_iresp_bits_uop_csr_addr_T_2 = asUInt(_io_iresp_bits_uop_csr_addr_T_1)
connect io.iresp.bits.uop.csr_addr, _io_iresp_bits_uop_csr_addr_T_2
connect io.iresp.bits.uop.ctrl.csr_cmd, ALUUnit.io.resp.bits.uop.ctrl.csr_cmd
node _T_26 = add(PipelinedMulUnit.io.resp.valid, DivUnit.io.resp.valid)
node _T_27 = bits(_T_26, 1, 0)
node _T_28 = add(ALUUnit.io.resp.valid, _T_27)
node _T_29 = bits(_T_28, 1, 0)
node _T_30 = leq(_T_29, UInt<1>(0h1))
node _T_31 = eq(div_resp_val, UInt<1>(0h0))
node _T_32 = and(_T_30, _T_31)
node _T_33 = add(PipelinedMulUnit.io.resp.valid, DivUnit.io.resp.valid)
node _T_34 = bits(_T_33, 1, 0)
node _T_35 = add(ALUUnit.io.resp.valid, _T_34)
node _T_36 = bits(_T_35, 1, 0)
node _T_37 = leq(_T_36, UInt<2>(0h2))
node _T_38 = and(_T_37, div_resp_val)
node _T_39 = or(_T_32, _T_38)
node _T_40 = asUInt(reset)
node _T_41 = eq(_T_40, UInt<1>(0h0))
when _T_41 :
node _T_42 = eq(_T_39, UInt<1>(0h0))
when _T_42 :
printf(clock, UInt<1>(0h1), "Assertion failed: Multiple functional units are fighting over the write port.\n at execution-unit.scala:425 assert ((PopCount(iresp_fu_units.map(_.io.resp.valid)) <= 1.U && !div_resp_val) ||\n") : printf_2
assert(clock, _T_39, UInt<1>(0h1), "") : assert_2 | module ALUExeUnit_1( // @[execution-unit.scala:204:7]
input clock, // @[execution-unit.scala:204:7]
input reset, // @[execution-unit.scala:204:7]
output [9:0] io_fu_types, // @[execution-unit.scala:104:14]
input io_req_valid, // @[execution-unit.scala:104:14]
input [6:0] io_req_bits_uop_uopc, // @[execution-unit.scala:104:14]
input [31:0] io_req_bits_uop_inst, // @[execution-unit.scala:104:14]
input [31:0] io_req_bits_uop_debug_inst, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_rvc, // @[execution-unit.scala:104:14]
input [39:0] io_req_bits_uop_debug_pc, // @[execution-unit.scala:104:14]
input [2:0] io_req_bits_uop_iq_type, // @[execution-unit.scala:104:14]
input [9:0] io_req_bits_uop_fu_code, // @[execution-unit.scala:104:14]
input [3:0] io_req_bits_uop_ctrl_br_type, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14]
input [2:0] io_req_bits_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14]
input [2:0] io_req_bits_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14]
input [4:0] io_req_bits_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14]
input io_req_bits_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14]
input [2:0] io_req_bits_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14]
input io_req_bits_uop_ctrl_is_load, // @[execution-unit.scala:104:14]
input io_req_bits_uop_ctrl_is_sta, // @[execution-unit.scala:104:14]
input io_req_bits_uop_ctrl_is_std, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_iw_state, // @[execution-unit.scala:104:14]
input io_req_bits_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14]
input io_req_bits_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_br, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_jalr, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_jal, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_sfb, // @[execution-unit.scala:104:14]
input [7:0] io_req_bits_uop_br_mask, // @[execution-unit.scala:104:14]
input [2:0] io_req_bits_uop_br_tag, // @[execution-unit.scala:104:14]
input [3:0] io_req_bits_uop_ftq_idx, // @[execution-unit.scala:104:14]
input io_req_bits_uop_edge_inst, // @[execution-unit.scala:104:14]
input [5:0] io_req_bits_uop_pc_lob, // @[execution-unit.scala:104:14]
input io_req_bits_uop_taken, // @[execution-unit.scala:104:14]
input [19:0] io_req_bits_uop_imm_packed, // @[execution-unit.scala:104:14]
input [11:0] io_req_bits_uop_csr_addr, // @[execution-unit.scala:104:14]
input [4:0] io_req_bits_uop_rob_idx, // @[execution-unit.scala:104:14]
input [2:0] io_req_bits_uop_ldq_idx, // @[execution-unit.scala:104:14]
input [2:0] io_req_bits_uop_stq_idx, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_rxq_idx, // @[execution-unit.scala:104:14]
input [5:0] io_req_bits_uop_pdst, // @[execution-unit.scala:104:14]
input [5:0] io_req_bits_uop_prs1, // @[execution-unit.scala:104:14]
input [5:0] io_req_bits_uop_prs2, // @[execution-unit.scala:104:14]
input [5:0] io_req_bits_uop_prs3, // @[execution-unit.scala:104:14]
input [3:0] io_req_bits_uop_ppred, // @[execution-unit.scala:104:14]
input io_req_bits_uop_prs1_busy, // @[execution-unit.scala:104:14]
input io_req_bits_uop_prs2_busy, // @[execution-unit.scala:104:14]
input io_req_bits_uop_prs3_busy, // @[execution-unit.scala:104:14]
input io_req_bits_uop_ppred_busy, // @[execution-unit.scala:104:14]
input [5:0] io_req_bits_uop_stale_pdst, // @[execution-unit.scala:104:14]
input io_req_bits_uop_exception, // @[execution-unit.scala:104:14]
input [63:0] io_req_bits_uop_exc_cause, // @[execution-unit.scala:104:14]
input io_req_bits_uop_bypassable, // @[execution-unit.scala:104:14]
input [4:0] io_req_bits_uop_mem_cmd, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_mem_size, // @[execution-unit.scala:104:14]
input io_req_bits_uop_mem_signed, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_fence, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_fencei, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_amo, // @[execution-unit.scala:104:14]
input io_req_bits_uop_uses_ldq, // @[execution-unit.scala:104:14]
input io_req_bits_uop_uses_stq, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_unique, // @[execution-unit.scala:104:14]
input io_req_bits_uop_flush_on_commit, // @[execution-unit.scala:104:14]
input io_req_bits_uop_ldst_is_rs1, // @[execution-unit.scala:104:14]
input [5:0] io_req_bits_uop_ldst, // @[execution-unit.scala:104:14]
input [5:0] io_req_bits_uop_lrs1, // @[execution-unit.scala:104:14]
input [5:0] io_req_bits_uop_lrs2, // @[execution-unit.scala:104:14]
input [5:0] io_req_bits_uop_lrs3, // @[execution-unit.scala:104:14]
input io_req_bits_uop_ldst_val, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_dst_rtype, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_lrs1_rtype, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_lrs2_rtype, // @[execution-unit.scala:104:14]
input io_req_bits_uop_frs3_en, // @[execution-unit.scala:104:14]
input io_req_bits_uop_fp_val, // @[execution-unit.scala:104:14]
input io_req_bits_uop_fp_single, // @[execution-unit.scala:104:14]
input io_req_bits_uop_xcpt_pf_if, // @[execution-unit.scala:104:14]
input io_req_bits_uop_xcpt_ae_if, // @[execution-unit.scala:104:14]
input io_req_bits_uop_xcpt_ma_if, // @[execution-unit.scala:104:14]
input io_req_bits_uop_bp_debug_if, // @[execution-unit.scala:104:14]
input io_req_bits_uop_bp_xcpt_if, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_debug_fsrc, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_debug_tsrc, // @[execution-unit.scala:104:14]
input [64:0] io_req_bits_rs1_data, // @[execution-unit.scala:104:14]
input [64:0] io_req_bits_rs2_data, // @[execution-unit.scala:104:14]
input io_req_bits_kill, // @[execution-unit.scala:104:14]
output io_iresp_valid, // @[execution-unit.scala:104:14]
output [6:0] io_iresp_bits_uop_uopc, // @[execution-unit.scala:104:14]
output [31:0] io_iresp_bits_uop_inst, // @[execution-unit.scala:104:14]
output [31:0] io_iresp_bits_uop_debug_inst, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_is_rvc, // @[execution-unit.scala:104:14]
output [39:0] io_iresp_bits_uop_debug_pc, // @[execution-unit.scala:104:14]
output [2:0] io_iresp_bits_uop_iq_type, // @[execution-unit.scala:104:14]
output [9:0] io_iresp_bits_uop_fu_code, // @[execution-unit.scala:104:14]
output [3:0] io_iresp_bits_uop_ctrl_br_type, // @[execution-unit.scala:104:14]
output [1:0] io_iresp_bits_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14]
output [2:0] io_iresp_bits_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14]
output [2:0] io_iresp_bits_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14]
output [4:0] io_iresp_bits_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14]
output [2:0] io_iresp_bits_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_ctrl_is_load, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_ctrl_is_sta, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_ctrl_is_std, // @[execution-unit.scala:104:14]
output [1:0] io_iresp_bits_uop_iw_state, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_is_br, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_is_jalr, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_is_jal, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_is_sfb, // @[execution-unit.scala:104:14]
output [7:0] io_iresp_bits_uop_br_mask, // @[execution-unit.scala:104:14]
output [2:0] io_iresp_bits_uop_br_tag, // @[execution-unit.scala:104:14]
output [3:0] io_iresp_bits_uop_ftq_idx, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_edge_inst, // @[execution-unit.scala:104:14]
output [5:0] io_iresp_bits_uop_pc_lob, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_taken, // @[execution-unit.scala:104:14]
output [19:0] io_iresp_bits_uop_imm_packed, // @[execution-unit.scala:104:14]
output [11:0] io_iresp_bits_uop_csr_addr, // @[execution-unit.scala:104:14]
output [4:0] io_iresp_bits_uop_rob_idx, // @[execution-unit.scala:104:14]
output [2:0] io_iresp_bits_uop_ldq_idx, // @[execution-unit.scala:104:14]
output [2:0] io_iresp_bits_uop_stq_idx, // @[execution-unit.scala:104:14]
output [1:0] io_iresp_bits_uop_rxq_idx, // @[execution-unit.scala:104:14]
output [5:0] io_iresp_bits_uop_pdst, // @[execution-unit.scala:104:14]
output [5:0] io_iresp_bits_uop_prs1, // @[execution-unit.scala:104:14]
output [5:0] io_iresp_bits_uop_prs2, // @[execution-unit.scala:104:14]
output [5:0] io_iresp_bits_uop_prs3, // @[execution-unit.scala:104:14]
output [3:0] io_iresp_bits_uop_ppred, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_prs1_busy, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_prs2_busy, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_prs3_busy, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_ppred_busy, // @[execution-unit.scala:104:14]
output [5:0] io_iresp_bits_uop_stale_pdst, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_exception, // @[execution-unit.scala:104:14]
output [63:0] io_iresp_bits_uop_exc_cause, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_bypassable, // @[execution-unit.scala:104:14]
output [4:0] io_iresp_bits_uop_mem_cmd, // @[execution-unit.scala:104:14]
output [1:0] io_iresp_bits_uop_mem_size, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_mem_signed, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_is_fence, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_is_fencei, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_is_amo, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_uses_ldq, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_uses_stq, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_is_unique, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_flush_on_commit, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_ldst_is_rs1, // @[execution-unit.scala:104:14]
output [5:0] io_iresp_bits_uop_ldst, // @[execution-unit.scala:104:14]
output [5:0] io_iresp_bits_uop_lrs1, // @[execution-unit.scala:104:14]
output [5:0] io_iresp_bits_uop_lrs2, // @[execution-unit.scala:104:14]
output [5:0] io_iresp_bits_uop_lrs3, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_ldst_val, // @[execution-unit.scala:104:14]
output [1:0] io_iresp_bits_uop_dst_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_iresp_bits_uop_lrs1_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_iresp_bits_uop_lrs2_rtype, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_frs3_en, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_fp_val, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_fp_single, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_xcpt_pf_if, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_xcpt_ae_if, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_xcpt_ma_if, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_bp_debug_if, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_bp_xcpt_if, // @[execution-unit.scala:104:14]
output [1:0] io_iresp_bits_uop_debug_fsrc, // @[execution-unit.scala:104:14]
output [1:0] io_iresp_bits_uop_debug_tsrc, // @[execution-unit.scala:104:14]
output [64:0] io_iresp_bits_data, // @[execution-unit.scala:104:14]
input io_ll_fresp_ready, // @[execution-unit.scala:104:14]
output io_ll_fresp_valid, // @[execution-unit.scala:104:14]
output [6:0] io_ll_fresp_bits_uop_uopc, // @[execution-unit.scala:104:14]
output [31:0] io_ll_fresp_bits_uop_inst, // @[execution-unit.scala:104:14]
output [31:0] io_ll_fresp_bits_uop_debug_inst, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_is_rvc, // @[execution-unit.scala:104:14]
output [39:0] io_ll_fresp_bits_uop_debug_pc, // @[execution-unit.scala:104:14]
output [2:0] io_ll_fresp_bits_uop_iq_type, // @[execution-unit.scala:104:14]
output [9:0] io_ll_fresp_bits_uop_fu_code, // @[execution-unit.scala:104:14]
output [3:0] io_ll_fresp_bits_uop_ctrl_br_type, // @[execution-unit.scala:104:14]
output [1:0] io_ll_fresp_bits_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14]
output [2:0] io_ll_fresp_bits_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14]
output [2:0] io_ll_fresp_bits_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14]
output [4:0] io_ll_fresp_bits_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14]
output [2:0] io_ll_fresp_bits_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_ctrl_is_load, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_ctrl_is_sta, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_ctrl_is_std, // @[execution-unit.scala:104:14]
output [1:0] io_ll_fresp_bits_uop_iw_state, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_is_br, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_is_jalr, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_is_jal, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_is_sfb, // @[execution-unit.scala:104:14]
output [7:0] io_ll_fresp_bits_uop_br_mask, // @[execution-unit.scala:104:14]
output [2:0] io_ll_fresp_bits_uop_br_tag, // @[execution-unit.scala:104:14]
output [3:0] io_ll_fresp_bits_uop_ftq_idx, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_edge_inst, // @[execution-unit.scala:104:14]
output [5:0] io_ll_fresp_bits_uop_pc_lob, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_taken, // @[execution-unit.scala:104:14]
output [19:0] io_ll_fresp_bits_uop_imm_packed, // @[execution-unit.scala:104:14]
output [11:0] io_ll_fresp_bits_uop_csr_addr, // @[execution-unit.scala:104:14]
output [4:0] io_ll_fresp_bits_uop_rob_idx, // @[execution-unit.scala:104:14]
output [2:0] io_ll_fresp_bits_uop_ldq_idx, // @[execution-unit.scala:104:14]
output [2:0] io_ll_fresp_bits_uop_stq_idx, // @[execution-unit.scala:104:14]
output [1:0] io_ll_fresp_bits_uop_rxq_idx, // @[execution-unit.scala:104:14]
output [5:0] io_ll_fresp_bits_uop_pdst, // @[execution-unit.scala:104:14]
output [5:0] io_ll_fresp_bits_uop_prs1, // @[execution-unit.scala:104:14]
output [5:0] io_ll_fresp_bits_uop_prs2, // @[execution-unit.scala:104:14]
output [5:0] io_ll_fresp_bits_uop_prs3, // @[execution-unit.scala:104:14]
output [3:0] io_ll_fresp_bits_uop_ppred, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_prs1_busy, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_prs2_busy, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_prs3_busy, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_ppred_busy, // @[execution-unit.scala:104:14]
output [5:0] io_ll_fresp_bits_uop_stale_pdst, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_exception, // @[execution-unit.scala:104:14]
output [63:0] io_ll_fresp_bits_uop_exc_cause, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_bypassable, // @[execution-unit.scala:104:14]
output [4:0] io_ll_fresp_bits_uop_mem_cmd, // @[execution-unit.scala:104:14]
output [1:0] io_ll_fresp_bits_uop_mem_size, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_mem_signed, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_is_fence, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_is_fencei, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_is_amo, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_uses_ldq, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_uses_stq, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_is_unique, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_flush_on_commit, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_ldst_is_rs1, // @[execution-unit.scala:104:14]
output [5:0] io_ll_fresp_bits_uop_ldst, // @[execution-unit.scala:104:14]
output [5:0] io_ll_fresp_bits_uop_lrs1, // @[execution-unit.scala:104:14]
output [5:0] io_ll_fresp_bits_uop_lrs2, // @[execution-unit.scala:104:14]
output [5:0] io_ll_fresp_bits_uop_lrs3, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_ldst_val, // @[execution-unit.scala:104:14]
output [1:0] io_ll_fresp_bits_uop_dst_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_ll_fresp_bits_uop_lrs1_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_ll_fresp_bits_uop_lrs2_rtype, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_frs3_en, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_fp_val, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_fp_single, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_xcpt_pf_if, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_xcpt_ae_if, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_xcpt_ma_if, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_bp_debug_if, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_bp_xcpt_if, // @[execution-unit.scala:104:14]
output [1:0] io_ll_fresp_bits_uop_debug_fsrc, // @[execution-unit.scala:104:14]
output [1:0] io_ll_fresp_bits_uop_debug_tsrc, // @[execution-unit.scala:104:14]
output [64:0] io_ll_fresp_bits_data, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_predicated, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_fflags_valid, // @[execution-unit.scala:104:14]
output [6:0] io_ll_fresp_bits_fflags_bits_uop_uopc, // @[execution-unit.scala:104:14]
output [31:0] io_ll_fresp_bits_fflags_bits_uop_inst, // @[execution-unit.scala:104:14]
output [31:0] io_ll_fresp_bits_fflags_bits_uop_debug_inst, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_fflags_bits_uop_is_rvc, // @[execution-unit.scala:104:14]
output [39:0] io_ll_fresp_bits_fflags_bits_uop_debug_pc, // @[execution-unit.scala:104:14]
output [2:0] io_ll_fresp_bits_fflags_bits_uop_iq_type, // @[execution-unit.scala:104:14]
output [9:0] io_ll_fresp_bits_fflags_bits_uop_fu_code, // @[execution-unit.scala:104:14]
output [3:0] io_ll_fresp_bits_fflags_bits_uop_ctrl_br_type, // @[execution-unit.scala:104:14]
output [1:0] io_ll_fresp_bits_fflags_bits_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14]
output [2:0] io_ll_fresp_bits_fflags_bits_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14]
output [2:0] io_ll_fresp_bits_fflags_bits_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14]
output [4:0] io_ll_fresp_bits_fflags_bits_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_fflags_bits_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14]
output [2:0] io_ll_fresp_bits_fflags_bits_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_fflags_bits_uop_ctrl_is_load, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_fflags_bits_uop_ctrl_is_sta, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_fflags_bits_uop_ctrl_is_std, // @[execution-unit.scala:104:14]
output [1:0] io_ll_fresp_bits_fflags_bits_uop_iw_state, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_fflags_bits_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_fflags_bits_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_fflags_bits_uop_is_br, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_fflags_bits_uop_is_jalr, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_fflags_bits_uop_is_jal, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_fflags_bits_uop_is_sfb, // @[execution-unit.scala:104:14]
output [7:0] io_ll_fresp_bits_fflags_bits_uop_br_mask, // @[execution-unit.scala:104:14]
output [2:0] io_ll_fresp_bits_fflags_bits_uop_br_tag, // @[execution-unit.scala:104:14]
output [3:0] io_ll_fresp_bits_fflags_bits_uop_ftq_idx, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_fflags_bits_uop_edge_inst, // @[execution-unit.scala:104:14]
output [5:0] io_ll_fresp_bits_fflags_bits_uop_pc_lob, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_fflags_bits_uop_taken, // @[execution-unit.scala:104:14]
output [19:0] io_ll_fresp_bits_fflags_bits_uop_imm_packed, // @[execution-unit.scala:104:14]
output [11:0] io_ll_fresp_bits_fflags_bits_uop_csr_addr, // @[execution-unit.scala:104:14]
output [4:0] io_ll_fresp_bits_fflags_bits_uop_rob_idx, // @[execution-unit.scala:104:14]
output [2:0] io_ll_fresp_bits_fflags_bits_uop_ldq_idx, // @[execution-unit.scala:104:14]
output [2:0] io_ll_fresp_bits_fflags_bits_uop_stq_idx, // @[execution-unit.scala:104:14]
output [1:0] io_ll_fresp_bits_fflags_bits_uop_rxq_idx, // @[execution-unit.scala:104:14]
output [5:0] io_ll_fresp_bits_fflags_bits_uop_pdst, // @[execution-unit.scala:104:14]
output [5:0] io_ll_fresp_bits_fflags_bits_uop_prs1, // @[execution-unit.scala:104:14]
output [5:0] io_ll_fresp_bits_fflags_bits_uop_prs2, // @[execution-unit.scala:104:14]
output [5:0] io_ll_fresp_bits_fflags_bits_uop_prs3, // @[execution-unit.scala:104:14]
output [3:0] io_ll_fresp_bits_fflags_bits_uop_ppred, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_fflags_bits_uop_prs1_busy, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_fflags_bits_uop_prs2_busy, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_fflags_bits_uop_prs3_busy, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_fflags_bits_uop_ppred_busy, // @[execution-unit.scala:104:14]
output [5:0] io_ll_fresp_bits_fflags_bits_uop_stale_pdst, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_fflags_bits_uop_exception, // @[execution-unit.scala:104:14]
output [63:0] io_ll_fresp_bits_fflags_bits_uop_exc_cause, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_fflags_bits_uop_bypassable, // @[execution-unit.scala:104:14]
output [4:0] io_ll_fresp_bits_fflags_bits_uop_mem_cmd, // @[execution-unit.scala:104:14]
output [1:0] io_ll_fresp_bits_fflags_bits_uop_mem_size, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_fflags_bits_uop_mem_signed, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_fflags_bits_uop_is_fence, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_fflags_bits_uop_is_fencei, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_fflags_bits_uop_is_amo, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_fflags_bits_uop_uses_ldq, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_fflags_bits_uop_uses_stq, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_fflags_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_fflags_bits_uop_is_unique, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_fflags_bits_uop_flush_on_commit, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_fflags_bits_uop_ldst_is_rs1, // @[execution-unit.scala:104:14]
output [5:0] io_ll_fresp_bits_fflags_bits_uop_ldst, // @[execution-unit.scala:104:14]
output [5:0] io_ll_fresp_bits_fflags_bits_uop_lrs1, // @[execution-unit.scala:104:14]
output [5:0] io_ll_fresp_bits_fflags_bits_uop_lrs2, // @[execution-unit.scala:104:14]
output [5:0] io_ll_fresp_bits_fflags_bits_uop_lrs3, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_fflags_bits_uop_ldst_val, // @[execution-unit.scala:104:14]
output [1:0] io_ll_fresp_bits_fflags_bits_uop_dst_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_ll_fresp_bits_fflags_bits_uop_lrs1_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_ll_fresp_bits_fflags_bits_uop_lrs2_rtype, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_fflags_bits_uop_frs3_en, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_fflags_bits_uop_fp_val, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_fflags_bits_uop_fp_single, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_fflags_bits_uop_xcpt_pf_if, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_fflags_bits_uop_xcpt_ae_if, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_fflags_bits_uop_xcpt_ma_if, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_fflags_bits_uop_bp_debug_if, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_fflags_bits_uop_bp_xcpt_if, // @[execution-unit.scala:104:14]
output [1:0] io_ll_fresp_bits_fflags_bits_uop_debug_fsrc, // @[execution-unit.scala:104:14]
output [1:0] io_ll_fresp_bits_fflags_bits_uop_debug_tsrc, // @[execution-unit.scala:104:14]
output [4:0] io_ll_fresp_bits_fflags_bits_flags, // @[execution-unit.scala:104:14]
output io_bypass_0_valid, // @[execution-unit.scala:104:14]
output [6:0] io_bypass_0_bits_uop_uopc, // @[execution-unit.scala:104:14]
output [31:0] io_bypass_0_bits_uop_inst, // @[execution-unit.scala:104:14]
output [31:0] io_bypass_0_bits_uop_debug_inst, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_is_rvc, // @[execution-unit.scala:104:14]
output [39:0] io_bypass_0_bits_uop_debug_pc, // @[execution-unit.scala:104:14]
output [2:0] io_bypass_0_bits_uop_iq_type, // @[execution-unit.scala:104:14]
output [9:0] io_bypass_0_bits_uop_fu_code, // @[execution-unit.scala:104:14]
output [3:0] io_bypass_0_bits_uop_ctrl_br_type, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_0_bits_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14]
output [2:0] io_bypass_0_bits_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14]
output [2:0] io_bypass_0_bits_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14]
output [4:0] io_bypass_0_bits_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14]
output [2:0] io_bypass_0_bits_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_ctrl_is_load, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_ctrl_is_sta, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_ctrl_is_std, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_0_bits_uop_iw_state, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_is_br, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_is_jalr, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_is_jal, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_is_sfb, // @[execution-unit.scala:104:14]
output [7:0] io_bypass_0_bits_uop_br_mask, // @[execution-unit.scala:104:14]
output [2:0] io_bypass_0_bits_uop_br_tag, // @[execution-unit.scala:104:14]
output [3:0] io_bypass_0_bits_uop_ftq_idx, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_edge_inst, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_0_bits_uop_pc_lob, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_taken, // @[execution-unit.scala:104:14]
output [19:0] io_bypass_0_bits_uop_imm_packed, // @[execution-unit.scala:104:14]
output [11:0] io_bypass_0_bits_uop_csr_addr, // @[execution-unit.scala:104:14]
output [4:0] io_bypass_0_bits_uop_rob_idx, // @[execution-unit.scala:104:14]
output [2:0] io_bypass_0_bits_uop_ldq_idx, // @[execution-unit.scala:104:14]
output [2:0] io_bypass_0_bits_uop_stq_idx, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_0_bits_uop_rxq_idx, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_0_bits_uop_pdst, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_0_bits_uop_prs1, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_0_bits_uop_prs2, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_0_bits_uop_prs3, // @[execution-unit.scala:104:14]
output [3:0] io_bypass_0_bits_uop_ppred, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_prs1_busy, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_prs2_busy, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_prs3_busy, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_ppred_busy, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_0_bits_uop_stale_pdst, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_exception, // @[execution-unit.scala:104:14]
output [63:0] io_bypass_0_bits_uop_exc_cause, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_bypassable, // @[execution-unit.scala:104:14]
output [4:0] io_bypass_0_bits_uop_mem_cmd, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_0_bits_uop_mem_size, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_mem_signed, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_is_fence, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_is_fencei, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_is_amo, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_uses_ldq, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_uses_stq, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_is_unique, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_flush_on_commit, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_ldst_is_rs1, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_0_bits_uop_ldst, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_0_bits_uop_lrs1, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_0_bits_uop_lrs2, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_0_bits_uop_lrs3, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_ldst_val, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_0_bits_uop_dst_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_0_bits_uop_lrs1_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_0_bits_uop_lrs2_rtype, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_frs3_en, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_fp_val, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_fp_single, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_xcpt_pf_if, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_xcpt_ae_if, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_xcpt_ma_if, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_bp_debug_if, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_bp_xcpt_if, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_0_bits_uop_debug_fsrc, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_0_bits_uop_debug_tsrc, // @[execution-unit.scala:104:14]
output [64:0] io_bypass_0_bits_data, // @[execution-unit.scala:104:14]
output io_bypass_1_valid, // @[execution-unit.scala:104:14]
output [6:0] io_bypass_1_bits_uop_uopc, // @[execution-unit.scala:104:14]
output [31:0] io_bypass_1_bits_uop_inst, // @[execution-unit.scala:104:14]
output [31:0] io_bypass_1_bits_uop_debug_inst, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_is_rvc, // @[execution-unit.scala:104:14]
output [39:0] io_bypass_1_bits_uop_debug_pc, // @[execution-unit.scala:104:14]
output [2:0] io_bypass_1_bits_uop_iq_type, // @[execution-unit.scala:104:14]
output [9:0] io_bypass_1_bits_uop_fu_code, // @[execution-unit.scala:104:14]
output [3:0] io_bypass_1_bits_uop_ctrl_br_type, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_1_bits_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14]
output [2:0] io_bypass_1_bits_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14]
output [2:0] io_bypass_1_bits_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14]
output [4:0] io_bypass_1_bits_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14]
output [2:0] io_bypass_1_bits_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_ctrl_is_load, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_ctrl_is_sta, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_ctrl_is_std, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_1_bits_uop_iw_state, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_is_br, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_is_jalr, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_is_jal, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_is_sfb, // @[execution-unit.scala:104:14]
output [7:0] io_bypass_1_bits_uop_br_mask, // @[execution-unit.scala:104:14]
output [2:0] io_bypass_1_bits_uop_br_tag, // @[execution-unit.scala:104:14]
output [3:0] io_bypass_1_bits_uop_ftq_idx, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_edge_inst, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_1_bits_uop_pc_lob, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_taken, // @[execution-unit.scala:104:14]
output [19:0] io_bypass_1_bits_uop_imm_packed, // @[execution-unit.scala:104:14]
output [11:0] io_bypass_1_bits_uop_csr_addr, // @[execution-unit.scala:104:14]
output [4:0] io_bypass_1_bits_uop_rob_idx, // @[execution-unit.scala:104:14]
output [2:0] io_bypass_1_bits_uop_ldq_idx, // @[execution-unit.scala:104:14]
output [2:0] io_bypass_1_bits_uop_stq_idx, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_1_bits_uop_rxq_idx, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_1_bits_uop_pdst, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_1_bits_uop_prs1, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_1_bits_uop_prs2, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_1_bits_uop_prs3, // @[execution-unit.scala:104:14]
output [3:0] io_bypass_1_bits_uop_ppred, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_prs1_busy, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_prs2_busy, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_prs3_busy, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_ppred_busy, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_1_bits_uop_stale_pdst, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_exception, // @[execution-unit.scala:104:14]
output [63:0] io_bypass_1_bits_uop_exc_cause, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_bypassable, // @[execution-unit.scala:104:14]
output [4:0] io_bypass_1_bits_uop_mem_cmd, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_1_bits_uop_mem_size, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_mem_signed, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_is_fence, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_is_fencei, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_is_amo, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_uses_ldq, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_uses_stq, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_is_unique, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_flush_on_commit, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_ldst_is_rs1, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_1_bits_uop_ldst, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_1_bits_uop_lrs1, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_1_bits_uop_lrs2, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_1_bits_uop_lrs3, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_ldst_val, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_1_bits_uop_dst_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_1_bits_uop_lrs1_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_1_bits_uop_lrs2_rtype, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_frs3_en, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_fp_val, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_fp_single, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_xcpt_pf_if, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_xcpt_ae_if, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_xcpt_ma_if, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_bp_debug_if, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_bp_xcpt_if, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_1_bits_uop_debug_fsrc, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_1_bits_uop_debug_tsrc, // @[execution-unit.scala:104:14]
output [64:0] io_bypass_1_bits_data, // @[execution-unit.scala:104:14]
output io_bypass_2_valid, // @[execution-unit.scala:104:14]
output [6:0] io_bypass_2_bits_uop_uopc, // @[execution-unit.scala:104:14]
output [31:0] io_bypass_2_bits_uop_inst, // @[execution-unit.scala:104:14]
output [31:0] io_bypass_2_bits_uop_debug_inst, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_is_rvc, // @[execution-unit.scala:104:14]
output [39:0] io_bypass_2_bits_uop_debug_pc, // @[execution-unit.scala:104:14]
output [2:0] io_bypass_2_bits_uop_iq_type, // @[execution-unit.scala:104:14]
output [9:0] io_bypass_2_bits_uop_fu_code, // @[execution-unit.scala:104:14]
output [3:0] io_bypass_2_bits_uop_ctrl_br_type, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_2_bits_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14]
output [2:0] io_bypass_2_bits_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14]
output [2:0] io_bypass_2_bits_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14]
output [4:0] io_bypass_2_bits_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14]
output [2:0] io_bypass_2_bits_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_ctrl_is_load, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_ctrl_is_sta, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_ctrl_is_std, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_2_bits_uop_iw_state, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_is_br, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_is_jalr, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_is_jal, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_is_sfb, // @[execution-unit.scala:104:14]
output [7:0] io_bypass_2_bits_uop_br_mask, // @[execution-unit.scala:104:14]
output [2:0] io_bypass_2_bits_uop_br_tag, // @[execution-unit.scala:104:14]
output [3:0] io_bypass_2_bits_uop_ftq_idx, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_edge_inst, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_2_bits_uop_pc_lob, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_taken, // @[execution-unit.scala:104:14]
output [19:0] io_bypass_2_bits_uop_imm_packed, // @[execution-unit.scala:104:14]
output [11:0] io_bypass_2_bits_uop_csr_addr, // @[execution-unit.scala:104:14]
output [4:0] io_bypass_2_bits_uop_rob_idx, // @[execution-unit.scala:104:14]
output [2:0] io_bypass_2_bits_uop_ldq_idx, // @[execution-unit.scala:104:14]
output [2:0] io_bypass_2_bits_uop_stq_idx, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_2_bits_uop_rxq_idx, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_2_bits_uop_pdst, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_2_bits_uop_prs1, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_2_bits_uop_prs2, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_2_bits_uop_prs3, // @[execution-unit.scala:104:14]
output [3:0] io_bypass_2_bits_uop_ppred, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_prs1_busy, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_prs2_busy, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_prs3_busy, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_ppred_busy, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_2_bits_uop_stale_pdst, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_exception, // @[execution-unit.scala:104:14]
output [63:0] io_bypass_2_bits_uop_exc_cause, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_bypassable, // @[execution-unit.scala:104:14]
output [4:0] io_bypass_2_bits_uop_mem_cmd, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_2_bits_uop_mem_size, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_mem_signed, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_is_fence, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_is_fencei, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_is_amo, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_uses_ldq, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_uses_stq, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_is_unique, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_flush_on_commit, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_ldst_is_rs1, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_2_bits_uop_ldst, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_2_bits_uop_lrs1, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_2_bits_uop_lrs2, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_2_bits_uop_lrs3, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_ldst_val, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_2_bits_uop_dst_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_2_bits_uop_lrs1_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_2_bits_uop_lrs2_rtype, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_frs3_en, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_fp_val, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_fp_single, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_xcpt_pf_if, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_xcpt_ae_if, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_xcpt_ma_if, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_bp_debug_if, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_bp_xcpt_if, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_2_bits_uop_debug_fsrc, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_2_bits_uop_debug_tsrc, // @[execution-unit.scala:104:14]
output [64:0] io_bypass_2_bits_data, // @[execution-unit.scala:104:14]
input [7:0] io_brupdate_b1_resolve_mask, // @[execution-unit.scala:104:14]
input [7:0] io_brupdate_b1_mispredict_mask, // @[execution-unit.scala:104:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[execution-unit.scala:104:14]
input [31:0] io_brupdate_b2_uop_inst, // @[execution-unit.scala:104:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_rvc, // @[execution-unit.scala:104:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[execution-unit.scala:104:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[execution-unit.scala:104:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[execution-unit.scala:104:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_br, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_jalr, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_jal, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_sfb, // @[execution-unit.scala:104:14]
input [7:0] io_brupdate_b2_uop_br_mask, // @[execution-unit.scala:104:14]
input [2:0] io_brupdate_b2_uop_br_tag, // @[execution-unit.scala:104:14]
input [3:0] io_brupdate_b2_uop_ftq_idx, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_edge_inst, // @[execution-unit.scala:104:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_taken, // @[execution-unit.scala:104:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[execution-unit.scala:104:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[execution-unit.scala:104:14]
input [4:0] io_brupdate_b2_uop_rob_idx, // @[execution-unit.scala:104:14]
input [2:0] io_brupdate_b2_uop_ldq_idx, // @[execution-unit.scala:104:14]
input [2:0] io_brupdate_b2_uop_stq_idx, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[execution-unit.scala:104:14]
input [5:0] io_brupdate_b2_uop_pdst, // @[execution-unit.scala:104:14]
input [5:0] io_brupdate_b2_uop_prs1, // @[execution-unit.scala:104:14]
input [5:0] io_brupdate_b2_uop_prs2, // @[execution-unit.scala:104:14]
input [5:0] io_brupdate_b2_uop_prs3, // @[execution-unit.scala:104:14]
input [3:0] io_brupdate_b2_uop_ppred, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_prs1_busy, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_prs2_busy, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_prs3_busy, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_ppred_busy, // @[execution-unit.scala:104:14]
input [5:0] io_brupdate_b2_uop_stale_pdst, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_exception, // @[execution-unit.scala:104:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_bypassable, // @[execution-unit.scala:104:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_mem_signed, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_fence, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_fencei, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_amo, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_uses_ldq, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_uses_stq, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_unique, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_flush_on_commit, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[execution-unit.scala:104:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[execution-unit.scala:104:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[execution-unit.scala:104:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[execution-unit.scala:104:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_ldst_val, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_frs3_en, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_fp_val, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_fp_single, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_bp_debug_if, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[execution-unit.scala:104:14]
input io_brupdate_b2_valid, // @[execution-unit.scala:104:14]
input io_brupdate_b2_mispredict, // @[execution-unit.scala:104:14]
input io_brupdate_b2_taken, // @[execution-unit.scala:104:14]
input [2:0] io_brupdate_b2_cfi_type, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_pc_sel, // @[execution-unit.scala:104:14]
input [39:0] io_brupdate_b2_jalr_target, // @[execution-unit.scala:104:14]
input [20:0] io_brupdate_b2_target_offset, // @[execution-unit.scala:104:14]
output [6:0] io_brinfo_uop_uopc, // @[execution-unit.scala:104:14]
output [31:0] io_brinfo_uop_inst, // @[execution-unit.scala:104:14]
output [31:0] io_brinfo_uop_debug_inst, // @[execution-unit.scala:104:14]
output io_brinfo_uop_is_rvc, // @[execution-unit.scala:104:14]
output [39:0] io_brinfo_uop_debug_pc, // @[execution-unit.scala:104:14]
output [2:0] io_brinfo_uop_iq_type, // @[execution-unit.scala:104:14]
output [9:0] io_brinfo_uop_fu_code, // @[execution-unit.scala:104:14]
output [3:0] io_brinfo_uop_ctrl_br_type, // @[execution-unit.scala:104:14]
output [1:0] io_brinfo_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14]
output [2:0] io_brinfo_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14]
output [2:0] io_brinfo_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14]
output [4:0] io_brinfo_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14]
output io_brinfo_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14]
output [2:0] io_brinfo_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14]
output io_brinfo_uop_ctrl_is_load, // @[execution-unit.scala:104:14]
output io_brinfo_uop_ctrl_is_sta, // @[execution-unit.scala:104:14]
output io_brinfo_uop_ctrl_is_std, // @[execution-unit.scala:104:14]
output [1:0] io_brinfo_uop_iw_state, // @[execution-unit.scala:104:14]
output io_brinfo_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14]
output io_brinfo_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14]
output io_brinfo_uop_is_br, // @[execution-unit.scala:104:14]
output io_brinfo_uop_is_jalr, // @[execution-unit.scala:104:14]
output io_brinfo_uop_is_jal, // @[execution-unit.scala:104:14]
output io_brinfo_uop_is_sfb, // @[execution-unit.scala:104:14]
output [7:0] io_brinfo_uop_br_mask, // @[execution-unit.scala:104:14]
output [2:0] io_brinfo_uop_br_tag, // @[execution-unit.scala:104:14]
output [3:0] io_brinfo_uop_ftq_idx, // @[execution-unit.scala:104:14]
output io_brinfo_uop_edge_inst, // @[execution-unit.scala:104:14]
output [5:0] io_brinfo_uop_pc_lob, // @[execution-unit.scala:104:14]
output io_brinfo_uop_taken, // @[execution-unit.scala:104:14]
output [19:0] io_brinfo_uop_imm_packed, // @[execution-unit.scala:104:14]
output [11:0] io_brinfo_uop_csr_addr, // @[execution-unit.scala:104:14]
output [4:0] io_brinfo_uop_rob_idx, // @[execution-unit.scala:104:14]
output [2:0] io_brinfo_uop_ldq_idx, // @[execution-unit.scala:104:14]
output [2:0] io_brinfo_uop_stq_idx, // @[execution-unit.scala:104:14]
output [1:0] io_brinfo_uop_rxq_idx, // @[execution-unit.scala:104:14]
output [5:0] io_brinfo_uop_pdst, // @[execution-unit.scala:104:14]
output [5:0] io_brinfo_uop_prs1, // @[execution-unit.scala:104:14]
output [5:0] io_brinfo_uop_prs2, // @[execution-unit.scala:104:14]
output [5:0] io_brinfo_uop_prs3, // @[execution-unit.scala:104:14]
output [3:0] io_brinfo_uop_ppred, // @[execution-unit.scala:104:14]
output io_brinfo_uop_prs1_busy, // @[execution-unit.scala:104:14]
output io_brinfo_uop_prs2_busy, // @[execution-unit.scala:104:14]
output io_brinfo_uop_prs3_busy, // @[execution-unit.scala:104:14]
output io_brinfo_uop_ppred_busy, // @[execution-unit.scala:104:14]
output [5:0] io_brinfo_uop_stale_pdst, // @[execution-unit.scala:104:14]
output io_brinfo_uop_exception, // @[execution-unit.scala:104:14]
output [63:0] io_brinfo_uop_exc_cause, // @[execution-unit.scala:104:14]
output io_brinfo_uop_bypassable, // @[execution-unit.scala:104:14]
output [4:0] io_brinfo_uop_mem_cmd, // @[execution-unit.scala:104:14]
output [1:0] io_brinfo_uop_mem_size, // @[execution-unit.scala:104:14]
output io_brinfo_uop_mem_signed, // @[execution-unit.scala:104:14]
output io_brinfo_uop_is_fence, // @[execution-unit.scala:104:14]
output io_brinfo_uop_is_fencei, // @[execution-unit.scala:104:14]
output io_brinfo_uop_is_amo, // @[execution-unit.scala:104:14]
output io_brinfo_uop_uses_ldq, // @[execution-unit.scala:104:14]
output io_brinfo_uop_uses_stq, // @[execution-unit.scala:104:14]
output io_brinfo_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14]
output io_brinfo_uop_is_unique, // @[execution-unit.scala:104:14]
output io_brinfo_uop_flush_on_commit, // @[execution-unit.scala:104:14]
output io_brinfo_uop_ldst_is_rs1, // @[execution-unit.scala:104:14]
output [5:0] io_brinfo_uop_ldst, // @[execution-unit.scala:104:14]
output [5:0] io_brinfo_uop_lrs1, // @[execution-unit.scala:104:14]
output [5:0] io_brinfo_uop_lrs2, // @[execution-unit.scala:104:14]
output [5:0] io_brinfo_uop_lrs3, // @[execution-unit.scala:104:14]
output io_brinfo_uop_ldst_val, // @[execution-unit.scala:104:14]
output [1:0] io_brinfo_uop_dst_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_brinfo_uop_lrs1_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_brinfo_uop_lrs2_rtype, // @[execution-unit.scala:104:14]
output io_brinfo_uop_frs3_en, // @[execution-unit.scala:104:14]
output io_brinfo_uop_fp_val, // @[execution-unit.scala:104:14]
output io_brinfo_uop_fp_single, // @[execution-unit.scala:104:14]
output io_brinfo_uop_xcpt_pf_if, // @[execution-unit.scala:104:14]
output io_brinfo_uop_xcpt_ae_if, // @[execution-unit.scala:104:14]
output io_brinfo_uop_xcpt_ma_if, // @[execution-unit.scala:104:14]
output io_brinfo_uop_bp_debug_if, // @[execution-unit.scala:104:14]
output io_brinfo_uop_bp_xcpt_if, // @[execution-unit.scala:104:14]
output [1:0] io_brinfo_uop_debug_fsrc, // @[execution-unit.scala:104:14]
output [1:0] io_brinfo_uop_debug_tsrc, // @[execution-unit.scala:104:14]
output io_brinfo_valid, // @[execution-unit.scala:104:14]
output io_brinfo_mispredict, // @[execution-unit.scala:104:14]
output io_brinfo_taken, // @[execution-unit.scala:104:14]
output [2:0] io_brinfo_cfi_type, // @[execution-unit.scala:104:14]
output [1:0] io_brinfo_pc_sel, // @[execution-unit.scala:104:14]
output [39:0] io_brinfo_jalr_target, // @[execution-unit.scala:104:14]
output [20:0] io_brinfo_target_offset, // @[execution-unit.scala:104:14]
input io_get_ftq_pc_entry_cfi_idx_valid, // @[execution-unit.scala:104:14]
input [1:0] io_get_ftq_pc_entry_cfi_idx_bits, // @[execution-unit.scala:104:14]
input io_get_ftq_pc_entry_cfi_taken, // @[execution-unit.scala:104:14]
input io_get_ftq_pc_entry_cfi_mispredicted, // @[execution-unit.scala:104:14]
input [2:0] io_get_ftq_pc_entry_cfi_type, // @[execution-unit.scala:104:14]
input [3:0] io_get_ftq_pc_entry_br_mask, // @[execution-unit.scala:104:14]
input io_get_ftq_pc_entry_cfi_is_call, // @[execution-unit.scala:104:14]
input io_get_ftq_pc_entry_cfi_is_ret, // @[execution-unit.scala:104:14]
input io_get_ftq_pc_entry_cfi_npc_plus4, // @[execution-unit.scala:104:14]
input [39:0] io_get_ftq_pc_entry_ras_top, // @[execution-unit.scala:104:14]
input [4:0] io_get_ftq_pc_entry_ras_idx, // @[execution-unit.scala:104:14]
input io_get_ftq_pc_entry_start_bank, // @[execution-unit.scala:104:14]
input [39:0] io_get_ftq_pc_pc, // @[execution-unit.scala:104:14]
input io_get_ftq_pc_next_val, // @[execution-unit.scala:104:14]
input [39:0] io_get_ftq_pc_next_pc, // @[execution-unit.scala:104:14]
input io_status_debug, // @[execution-unit.scala:104:14]
input io_status_cease, // @[execution-unit.scala:104:14]
input io_status_wfi, // @[execution-unit.scala:104:14]
input [1:0] io_status_dprv, // @[execution-unit.scala:104:14]
input io_status_dv, // @[execution-unit.scala:104:14]
input [1:0] io_status_prv, // @[execution-unit.scala:104:14]
input io_status_v, // @[execution-unit.scala:104:14]
input io_status_sd, // @[execution-unit.scala:104:14]
input io_status_mpv, // @[execution-unit.scala:104:14]
input io_status_gva, // @[execution-unit.scala:104:14]
input io_status_tsr, // @[execution-unit.scala:104:14]
input io_status_tw, // @[execution-unit.scala:104:14]
input io_status_tvm, // @[execution-unit.scala:104:14]
input io_status_mxr, // @[execution-unit.scala:104:14]
input io_status_sum, // @[execution-unit.scala:104:14]
input io_status_mprv, // @[execution-unit.scala:104:14]
input [1:0] io_status_fs, // @[execution-unit.scala:104:14]
input [1:0] io_status_mpp, // @[execution-unit.scala:104:14]
input io_status_spp, // @[execution-unit.scala:104:14]
input io_status_mpie, // @[execution-unit.scala:104:14]
input io_status_spie, // @[execution-unit.scala:104:14]
input io_status_mie, // @[execution-unit.scala:104:14]
input io_status_sie, // @[execution-unit.scala:104:14]
input [2:0] io_fcsr_rm // @[execution-unit.scala:104:14]
);
wire _DivUnit_io_req_ready; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_valid; // @[execution-unit.scala:366:17]
wire [6:0] _DivUnit_io_resp_bits_uop_uopc; // @[execution-unit.scala:366:17]
wire [31:0] _DivUnit_io_resp_bits_uop_inst; // @[execution-unit.scala:366:17]
wire [31:0] _DivUnit_io_resp_bits_uop_debug_inst; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_is_rvc; // @[execution-unit.scala:366:17]
wire [39:0] _DivUnit_io_resp_bits_uop_debug_pc; // @[execution-unit.scala:366:17]
wire [2:0] _DivUnit_io_resp_bits_uop_iq_type; // @[execution-unit.scala:366:17]
wire [9:0] _DivUnit_io_resp_bits_uop_fu_code; // @[execution-unit.scala:366:17]
wire [3:0] _DivUnit_io_resp_bits_uop_ctrl_br_type; // @[execution-unit.scala:366:17]
wire [1:0] _DivUnit_io_resp_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:366:17]
wire [2:0] _DivUnit_io_resp_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:366:17]
wire [2:0] _DivUnit_io_resp_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:366:17]
wire [4:0] _DivUnit_io_resp_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:366:17]
wire [2:0] _DivUnit_io_resp_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_ctrl_is_load; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_ctrl_is_sta; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_ctrl_is_std; // @[execution-unit.scala:366:17]
wire [1:0] _DivUnit_io_resp_bits_uop_iw_state; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_is_br; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_is_jalr; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_is_jal; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_is_sfb; // @[execution-unit.scala:366:17]
wire [7:0] _DivUnit_io_resp_bits_uop_br_mask; // @[execution-unit.scala:366:17]
wire [2:0] _DivUnit_io_resp_bits_uop_br_tag; // @[execution-unit.scala:366:17]
wire [3:0] _DivUnit_io_resp_bits_uop_ftq_idx; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_edge_inst; // @[execution-unit.scala:366:17]
wire [5:0] _DivUnit_io_resp_bits_uop_pc_lob; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_taken; // @[execution-unit.scala:366:17]
wire [19:0] _DivUnit_io_resp_bits_uop_imm_packed; // @[execution-unit.scala:366:17]
wire [11:0] _DivUnit_io_resp_bits_uop_csr_addr; // @[execution-unit.scala:366:17]
wire [4:0] _DivUnit_io_resp_bits_uop_rob_idx; // @[execution-unit.scala:366:17]
wire [2:0] _DivUnit_io_resp_bits_uop_ldq_idx; // @[execution-unit.scala:366:17]
wire [2:0] _DivUnit_io_resp_bits_uop_stq_idx; // @[execution-unit.scala:366:17]
wire [1:0] _DivUnit_io_resp_bits_uop_rxq_idx; // @[execution-unit.scala:366:17]
wire [5:0] _DivUnit_io_resp_bits_uop_pdst; // @[execution-unit.scala:366:17]
wire [5:0] _DivUnit_io_resp_bits_uop_prs1; // @[execution-unit.scala:366:17]
wire [5:0] _DivUnit_io_resp_bits_uop_prs2; // @[execution-unit.scala:366:17]
wire [5:0] _DivUnit_io_resp_bits_uop_prs3; // @[execution-unit.scala:366:17]
wire [3:0] _DivUnit_io_resp_bits_uop_ppred; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_prs1_busy; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_prs2_busy; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_prs3_busy; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_ppred_busy; // @[execution-unit.scala:366:17]
wire [5:0] _DivUnit_io_resp_bits_uop_stale_pdst; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_exception; // @[execution-unit.scala:366:17]
wire [63:0] _DivUnit_io_resp_bits_uop_exc_cause; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_bypassable; // @[execution-unit.scala:366:17]
wire [4:0] _DivUnit_io_resp_bits_uop_mem_cmd; // @[execution-unit.scala:366:17]
wire [1:0] _DivUnit_io_resp_bits_uop_mem_size; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_mem_signed; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_is_fence; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_is_fencei; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_is_amo; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_uses_ldq; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_uses_stq; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_is_unique; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_flush_on_commit; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_ldst_is_rs1; // @[execution-unit.scala:366:17]
wire [5:0] _DivUnit_io_resp_bits_uop_ldst; // @[execution-unit.scala:366:17]
wire [5:0] _DivUnit_io_resp_bits_uop_lrs1; // @[execution-unit.scala:366:17]
wire [5:0] _DivUnit_io_resp_bits_uop_lrs2; // @[execution-unit.scala:366:17]
wire [5:0] _DivUnit_io_resp_bits_uop_lrs3; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_ldst_val; // @[execution-unit.scala:366:17]
wire [1:0] _DivUnit_io_resp_bits_uop_dst_rtype; // @[execution-unit.scala:366:17]
wire [1:0] _DivUnit_io_resp_bits_uop_lrs1_rtype; // @[execution-unit.scala:366:17]
wire [1:0] _DivUnit_io_resp_bits_uop_lrs2_rtype; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_frs3_en; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_fp_val; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_fp_single; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_xcpt_pf_if; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_xcpt_ae_if; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_xcpt_ma_if; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_bp_debug_if; // @[execution-unit.scala:366:17]
wire _DivUnit_io_resp_bits_uop_bp_xcpt_if; // @[execution-unit.scala:366:17]
wire [1:0] _DivUnit_io_resp_bits_uop_debug_fsrc; // @[execution-unit.scala:366:17]
wire [1:0] _DivUnit_io_resp_bits_uop_debug_tsrc; // @[execution-unit.scala:366:17]
wire [63:0] _DivUnit_io_resp_bits_data; // @[execution-unit.scala:366:17]
wire _queue_io_enq_ready; // @[execution-unit.scala:347:23]
wire _queue_io_empty; // @[execution-unit.scala:347:23]
wire _IntToFPUnit_io_resp_valid; // @[execution-unit.scala:339:18]
wire [6:0] _IntToFPUnit_io_resp_bits_uop_uopc; // @[execution-unit.scala:339:18]
wire [31:0] _IntToFPUnit_io_resp_bits_uop_inst; // @[execution-unit.scala:339:18]
wire [31:0] _IntToFPUnit_io_resp_bits_uop_debug_inst; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_uop_is_rvc; // @[execution-unit.scala:339:18]
wire [39:0] _IntToFPUnit_io_resp_bits_uop_debug_pc; // @[execution-unit.scala:339:18]
wire [2:0] _IntToFPUnit_io_resp_bits_uop_iq_type; // @[execution-unit.scala:339:18]
wire [9:0] _IntToFPUnit_io_resp_bits_uop_fu_code; // @[execution-unit.scala:339:18]
wire [3:0] _IntToFPUnit_io_resp_bits_uop_ctrl_br_type; // @[execution-unit.scala:339:18]
wire [1:0] _IntToFPUnit_io_resp_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:339:18]
wire [2:0] _IntToFPUnit_io_resp_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:339:18]
wire [2:0] _IntToFPUnit_io_resp_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:339:18]
wire [4:0] _IntToFPUnit_io_resp_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:339:18]
wire [2:0] _IntToFPUnit_io_resp_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_uop_ctrl_is_load; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_uop_ctrl_is_sta; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_uop_ctrl_is_std; // @[execution-unit.scala:339:18]
wire [1:0] _IntToFPUnit_io_resp_bits_uop_iw_state; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_uop_is_br; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_uop_is_jalr; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_uop_is_jal; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_uop_is_sfb; // @[execution-unit.scala:339:18]
wire [7:0] _IntToFPUnit_io_resp_bits_uop_br_mask; // @[execution-unit.scala:339:18]
wire [2:0] _IntToFPUnit_io_resp_bits_uop_br_tag; // @[execution-unit.scala:339:18]
wire [3:0] _IntToFPUnit_io_resp_bits_uop_ftq_idx; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_uop_edge_inst; // @[execution-unit.scala:339:18]
wire [5:0] _IntToFPUnit_io_resp_bits_uop_pc_lob; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_uop_taken; // @[execution-unit.scala:339:18]
wire [19:0] _IntToFPUnit_io_resp_bits_uop_imm_packed; // @[execution-unit.scala:339:18]
wire [11:0] _IntToFPUnit_io_resp_bits_uop_csr_addr; // @[execution-unit.scala:339:18]
wire [4:0] _IntToFPUnit_io_resp_bits_uop_rob_idx; // @[execution-unit.scala:339:18]
wire [2:0] _IntToFPUnit_io_resp_bits_uop_ldq_idx; // @[execution-unit.scala:339:18]
wire [2:0] _IntToFPUnit_io_resp_bits_uop_stq_idx; // @[execution-unit.scala:339:18]
wire [1:0] _IntToFPUnit_io_resp_bits_uop_rxq_idx; // @[execution-unit.scala:339:18]
wire [5:0] _IntToFPUnit_io_resp_bits_uop_pdst; // @[execution-unit.scala:339:18]
wire [5:0] _IntToFPUnit_io_resp_bits_uop_prs1; // @[execution-unit.scala:339:18]
wire [5:0] _IntToFPUnit_io_resp_bits_uop_prs2; // @[execution-unit.scala:339:18]
wire [5:0] _IntToFPUnit_io_resp_bits_uop_prs3; // @[execution-unit.scala:339:18]
wire [3:0] _IntToFPUnit_io_resp_bits_uop_ppred; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_uop_prs1_busy; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_uop_prs2_busy; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_uop_prs3_busy; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_uop_ppred_busy; // @[execution-unit.scala:339:18]
wire [5:0] _IntToFPUnit_io_resp_bits_uop_stale_pdst; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_uop_exception; // @[execution-unit.scala:339:18]
wire [63:0] _IntToFPUnit_io_resp_bits_uop_exc_cause; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_uop_bypassable; // @[execution-unit.scala:339:18]
wire [4:0] _IntToFPUnit_io_resp_bits_uop_mem_cmd; // @[execution-unit.scala:339:18]
wire [1:0] _IntToFPUnit_io_resp_bits_uop_mem_size; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_uop_mem_signed; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_uop_is_fence; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_uop_is_fencei; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_uop_is_amo; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_uop_uses_ldq; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_uop_uses_stq; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_uop_is_unique; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_uop_flush_on_commit; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_uop_ldst_is_rs1; // @[execution-unit.scala:339:18]
wire [5:0] _IntToFPUnit_io_resp_bits_uop_ldst; // @[execution-unit.scala:339:18]
wire [5:0] _IntToFPUnit_io_resp_bits_uop_lrs1; // @[execution-unit.scala:339:18]
wire [5:0] _IntToFPUnit_io_resp_bits_uop_lrs2; // @[execution-unit.scala:339:18]
wire [5:0] _IntToFPUnit_io_resp_bits_uop_lrs3; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_uop_ldst_val; // @[execution-unit.scala:339:18]
wire [1:0] _IntToFPUnit_io_resp_bits_uop_dst_rtype; // @[execution-unit.scala:339:18]
wire [1:0] _IntToFPUnit_io_resp_bits_uop_lrs1_rtype; // @[execution-unit.scala:339:18]
wire [1:0] _IntToFPUnit_io_resp_bits_uop_lrs2_rtype; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_uop_frs3_en; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_uop_fp_val; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_uop_fp_single; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_uop_xcpt_pf_if; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_uop_xcpt_ae_if; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_uop_xcpt_ma_if; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_uop_bp_debug_if; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_uop_bp_xcpt_if; // @[execution-unit.scala:339:18]
wire [1:0] _IntToFPUnit_io_resp_bits_uop_debug_fsrc; // @[execution-unit.scala:339:18]
wire [1:0] _IntToFPUnit_io_resp_bits_uop_debug_tsrc; // @[execution-unit.scala:339:18]
wire [64:0] _IntToFPUnit_io_resp_bits_data; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_fflags_valid; // @[execution-unit.scala:339:18]
wire [6:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_uopc; // @[execution-unit.scala:339:18]
wire [31:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_inst; // @[execution-unit.scala:339:18]
wire [31:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_debug_inst; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_is_rvc; // @[execution-unit.scala:339:18]
wire [39:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_debug_pc; // @[execution-unit.scala:339:18]
wire [2:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_iq_type; // @[execution-unit.scala:339:18]
wire [9:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_fu_code; // @[execution-unit.scala:339:18]
wire [3:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_ctrl_br_type; // @[execution-unit.scala:339:18]
wire [1:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:339:18]
wire [2:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:339:18]
wire [2:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:339:18]
wire [4:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:339:18]
wire [2:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_ctrl_is_load; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_ctrl_is_sta; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_ctrl_is_std; // @[execution-unit.scala:339:18]
wire [1:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_iw_state; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_is_br; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_is_jalr; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_is_jal; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_is_sfb; // @[execution-unit.scala:339:18]
wire [7:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_br_mask; // @[execution-unit.scala:339:18]
wire [2:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_br_tag; // @[execution-unit.scala:339:18]
wire [3:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_ftq_idx; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_edge_inst; // @[execution-unit.scala:339:18]
wire [5:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_pc_lob; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_taken; // @[execution-unit.scala:339:18]
wire [19:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_imm_packed; // @[execution-unit.scala:339:18]
wire [11:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_csr_addr; // @[execution-unit.scala:339:18]
wire [4:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_rob_idx; // @[execution-unit.scala:339:18]
wire [2:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_ldq_idx; // @[execution-unit.scala:339:18]
wire [2:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_stq_idx; // @[execution-unit.scala:339:18]
wire [1:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_rxq_idx; // @[execution-unit.scala:339:18]
wire [5:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_pdst; // @[execution-unit.scala:339:18]
wire [5:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_prs1; // @[execution-unit.scala:339:18]
wire [5:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_prs2; // @[execution-unit.scala:339:18]
wire [5:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_prs3; // @[execution-unit.scala:339:18]
wire [3:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_ppred; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_prs1_busy; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_prs2_busy; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_prs3_busy; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_ppred_busy; // @[execution-unit.scala:339:18]
wire [5:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_stale_pdst; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_exception; // @[execution-unit.scala:339:18]
wire [63:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_exc_cause; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_bypassable; // @[execution-unit.scala:339:18]
wire [4:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_mem_cmd; // @[execution-unit.scala:339:18]
wire [1:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_mem_size; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_mem_signed; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_is_fence; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_is_fencei; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_is_amo; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_uses_ldq; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_uses_stq; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_is_unique; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_flush_on_commit; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_ldst_is_rs1; // @[execution-unit.scala:339:18]
wire [5:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_ldst; // @[execution-unit.scala:339:18]
wire [5:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_lrs1; // @[execution-unit.scala:339:18]
wire [5:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_lrs2; // @[execution-unit.scala:339:18]
wire [5:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_lrs3; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_ldst_val; // @[execution-unit.scala:339:18]
wire [1:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_dst_rtype; // @[execution-unit.scala:339:18]
wire [1:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_lrs1_rtype; // @[execution-unit.scala:339:18]
wire [1:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_lrs2_rtype; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_frs3_en; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_fp_val; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_fp_single; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_xcpt_pf_if; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_xcpt_ae_if; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_xcpt_ma_if; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_bp_debug_if; // @[execution-unit.scala:339:18]
wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_bp_xcpt_if; // @[execution-unit.scala:339:18]
wire [1:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_debug_fsrc; // @[execution-unit.scala:339:18]
wire [1:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_debug_tsrc; // @[execution-unit.scala:339:18]
wire [4:0] _IntToFPUnit_io_resp_bits_fflags_bits_flags; // @[execution-unit.scala:339:18]
wire _PipelinedMulUnit_io_resp_valid; // @[execution-unit.scala:326:18]
wire [6:0] _PipelinedMulUnit_io_resp_bits_uop_uopc; // @[execution-unit.scala:326:18]
wire [31:0] _PipelinedMulUnit_io_resp_bits_uop_inst; // @[execution-unit.scala:326:18]
wire [31:0] _PipelinedMulUnit_io_resp_bits_uop_debug_inst; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_is_rvc; // @[execution-unit.scala:326:18]
wire [39:0] _PipelinedMulUnit_io_resp_bits_uop_debug_pc; // @[execution-unit.scala:326:18]
wire [2:0] _PipelinedMulUnit_io_resp_bits_uop_iq_type; // @[execution-unit.scala:326:18]
wire [9:0] _PipelinedMulUnit_io_resp_bits_uop_fu_code; // @[execution-unit.scala:326:18]
wire [3:0] _PipelinedMulUnit_io_resp_bits_uop_ctrl_br_type; // @[execution-unit.scala:326:18]
wire [1:0] _PipelinedMulUnit_io_resp_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:326:18]
wire [2:0] _PipelinedMulUnit_io_resp_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:326:18]
wire [2:0] _PipelinedMulUnit_io_resp_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:326:18]
wire [4:0] _PipelinedMulUnit_io_resp_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:326:18]
wire [2:0] _PipelinedMulUnit_io_resp_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_ctrl_is_load; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_ctrl_is_sta; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_ctrl_is_std; // @[execution-unit.scala:326:18]
wire [1:0] _PipelinedMulUnit_io_resp_bits_uop_iw_state; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_is_br; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_is_jalr; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_is_jal; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_is_sfb; // @[execution-unit.scala:326:18]
wire [7:0] _PipelinedMulUnit_io_resp_bits_uop_br_mask; // @[execution-unit.scala:326:18]
wire [2:0] _PipelinedMulUnit_io_resp_bits_uop_br_tag; // @[execution-unit.scala:326:18]
wire [3:0] _PipelinedMulUnit_io_resp_bits_uop_ftq_idx; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_edge_inst; // @[execution-unit.scala:326:18]
wire [5:0] _PipelinedMulUnit_io_resp_bits_uop_pc_lob; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_taken; // @[execution-unit.scala:326:18]
wire [19:0] _PipelinedMulUnit_io_resp_bits_uop_imm_packed; // @[execution-unit.scala:326:18]
wire [11:0] _PipelinedMulUnit_io_resp_bits_uop_csr_addr; // @[execution-unit.scala:326:18]
wire [4:0] _PipelinedMulUnit_io_resp_bits_uop_rob_idx; // @[execution-unit.scala:326:18]
wire [2:0] _PipelinedMulUnit_io_resp_bits_uop_ldq_idx; // @[execution-unit.scala:326:18]
wire [2:0] _PipelinedMulUnit_io_resp_bits_uop_stq_idx; // @[execution-unit.scala:326:18]
wire [1:0] _PipelinedMulUnit_io_resp_bits_uop_rxq_idx; // @[execution-unit.scala:326:18]
wire [5:0] _PipelinedMulUnit_io_resp_bits_uop_pdst; // @[execution-unit.scala:326:18]
wire [5:0] _PipelinedMulUnit_io_resp_bits_uop_prs1; // @[execution-unit.scala:326:18]
wire [5:0] _PipelinedMulUnit_io_resp_bits_uop_prs2; // @[execution-unit.scala:326:18]
wire [5:0] _PipelinedMulUnit_io_resp_bits_uop_prs3; // @[execution-unit.scala:326:18]
wire [3:0] _PipelinedMulUnit_io_resp_bits_uop_ppred; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_prs1_busy; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_prs2_busy; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_prs3_busy; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_ppred_busy; // @[execution-unit.scala:326:18]
wire [5:0] _PipelinedMulUnit_io_resp_bits_uop_stale_pdst; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_exception; // @[execution-unit.scala:326:18]
wire [63:0] _PipelinedMulUnit_io_resp_bits_uop_exc_cause; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_bypassable; // @[execution-unit.scala:326:18]
wire [4:0] _PipelinedMulUnit_io_resp_bits_uop_mem_cmd; // @[execution-unit.scala:326:18]
wire [1:0] _PipelinedMulUnit_io_resp_bits_uop_mem_size; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_mem_signed; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_is_fence; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_is_fencei; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_is_amo; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_uses_ldq; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_uses_stq; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_is_unique; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_flush_on_commit; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_ldst_is_rs1; // @[execution-unit.scala:326:18]
wire [5:0] _PipelinedMulUnit_io_resp_bits_uop_ldst; // @[execution-unit.scala:326:18]
wire [5:0] _PipelinedMulUnit_io_resp_bits_uop_lrs1; // @[execution-unit.scala:326:18]
wire [5:0] _PipelinedMulUnit_io_resp_bits_uop_lrs2; // @[execution-unit.scala:326:18]
wire [5:0] _PipelinedMulUnit_io_resp_bits_uop_lrs3; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_ldst_val; // @[execution-unit.scala:326:18]
wire [1:0] _PipelinedMulUnit_io_resp_bits_uop_dst_rtype; // @[execution-unit.scala:326:18]
wire [1:0] _PipelinedMulUnit_io_resp_bits_uop_lrs1_rtype; // @[execution-unit.scala:326:18]
wire [1:0] _PipelinedMulUnit_io_resp_bits_uop_lrs2_rtype; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_frs3_en; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_fp_val; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_fp_single; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_xcpt_pf_if; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_xcpt_ae_if; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_xcpt_ma_if; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_bp_debug_if; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_bp_xcpt_if; // @[execution-unit.scala:326:18]
wire [1:0] _PipelinedMulUnit_io_resp_bits_uop_debug_fsrc; // @[execution-unit.scala:326:18]
wire [1:0] _PipelinedMulUnit_io_resp_bits_uop_debug_tsrc; // @[execution-unit.scala:326:18]
wire [63:0] _PipelinedMulUnit_io_resp_bits_data; // @[execution-unit.scala:326:18]
wire _ALUUnit_io_resp_valid; // @[execution-unit.scala:271:17]
wire [6:0] _ALUUnit_io_resp_bits_uop_uopc; // @[execution-unit.scala:271:17]
wire [31:0] _ALUUnit_io_resp_bits_uop_inst; // @[execution-unit.scala:271:17]
wire [31:0] _ALUUnit_io_resp_bits_uop_debug_inst; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_is_rvc; // @[execution-unit.scala:271:17]
wire [39:0] _ALUUnit_io_resp_bits_uop_debug_pc; // @[execution-unit.scala:271:17]
wire [2:0] _ALUUnit_io_resp_bits_uop_iq_type; // @[execution-unit.scala:271:17]
wire [9:0] _ALUUnit_io_resp_bits_uop_fu_code; // @[execution-unit.scala:271:17]
wire [3:0] _ALUUnit_io_resp_bits_uop_ctrl_br_type; // @[execution-unit.scala:271:17]
wire [1:0] _ALUUnit_io_resp_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:271:17]
wire [2:0] _ALUUnit_io_resp_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:271:17]
wire [2:0] _ALUUnit_io_resp_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:271:17]
wire [4:0] _ALUUnit_io_resp_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:271:17]
wire [2:0] _ALUUnit_io_resp_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_ctrl_is_load; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_ctrl_is_sta; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_ctrl_is_std; // @[execution-unit.scala:271:17]
wire [1:0] _ALUUnit_io_resp_bits_uop_iw_state; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_is_br; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_is_jalr; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_is_jal; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_is_sfb; // @[execution-unit.scala:271:17]
wire [7:0] _ALUUnit_io_resp_bits_uop_br_mask; // @[execution-unit.scala:271:17]
wire [2:0] _ALUUnit_io_resp_bits_uop_br_tag; // @[execution-unit.scala:271:17]
wire [3:0] _ALUUnit_io_resp_bits_uop_ftq_idx; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_edge_inst; // @[execution-unit.scala:271:17]
wire [5:0] _ALUUnit_io_resp_bits_uop_pc_lob; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_taken; // @[execution-unit.scala:271:17]
wire [19:0] _ALUUnit_io_resp_bits_uop_imm_packed; // @[execution-unit.scala:271:17]
wire [11:0] _ALUUnit_io_resp_bits_uop_csr_addr; // @[execution-unit.scala:271:17]
wire [4:0] _ALUUnit_io_resp_bits_uop_rob_idx; // @[execution-unit.scala:271:17]
wire [2:0] _ALUUnit_io_resp_bits_uop_ldq_idx; // @[execution-unit.scala:271:17]
wire [2:0] _ALUUnit_io_resp_bits_uop_stq_idx; // @[execution-unit.scala:271:17]
wire [1:0] _ALUUnit_io_resp_bits_uop_rxq_idx; // @[execution-unit.scala:271:17]
wire [5:0] _ALUUnit_io_resp_bits_uop_pdst; // @[execution-unit.scala:271:17]
wire [5:0] _ALUUnit_io_resp_bits_uop_prs1; // @[execution-unit.scala:271:17]
wire [5:0] _ALUUnit_io_resp_bits_uop_prs2; // @[execution-unit.scala:271:17]
wire [5:0] _ALUUnit_io_resp_bits_uop_prs3; // @[execution-unit.scala:271:17]
wire [3:0] _ALUUnit_io_resp_bits_uop_ppred; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_prs1_busy; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_prs2_busy; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_prs3_busy; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_ppred_busy; // @[execution-unit.scala:271:17]
wire [5:0] _ALUUnit_io_resp_bits_uop_stale_pdst; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_exception; // @[execution-unit.scala:271:17]
wire [63:0] _ALUUnit_io_resp_bits_uop_exc_cause; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_bypassable; // @[execution-unit.scala:271:17]
wire [4:0] _ALUUnit_io_resp_bits_uop_mem_cmd; // @[execution-unit.scala:271:17]
wire [1:0] _ALUUnit_io_resp_bits_uop_mem_size; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_mem_signed; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_is_fence; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_is_fencei; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_is_amo; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_uses_ldq; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_uses_stq; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_is_unique; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_flush_on_commit; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_ldst_is_rs1; // @[execution-unit.scala:271:17]
wire [5:0] _ALUUnit_io_resp_bits_uop_ldst; // @[execution-unit.scala:271:17]
wire [5:0] _ALUUnit_io_resp_bits_uop_lrs1; // @[execution-unit.scala:271:17]
wire [5:0] _ALUUnit_io_resp_bits_uop_lrs2; // @[execution-unit.scala:271:17]
wire [5:0] _ALUUnit_io_resp_bits_uop_lrs3; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_ldst_val; // @[execution-unit.scala:271:17]
wire [1:0] _ALUUnit_io_resp_bits_uop_dst_rtype; // @[execution-unit.scala:271:17]
wire [1:0] _ALUUnit_io_resp_bits_uop_lrs1_rtype; // @[execution-unit.scala:271:17]
wire [1:0] _ALUUnit_io_resp_bits_uop_lrs2_rtype; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_frs3_en; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_fp_val; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_fp_single; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_xcpt_pf_if; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_xcpt_ae_if; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_xcpt_ma_if; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_bp_debug_if; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_bp_xcpt_if; // @[execution-unit.scala:271:17]
wire [1:0] _ALUUnit_io_resp_bits_uop_debug_fsrc; // @[execution-unit.scala:271:17]
wire [1:0] _ALUUnit_io_resp_bits_uop_debug_tsrc; // @[execution-unit.scala:271:17]
wire [63:0] _ALUUnit_io_resp_bits_data; // @[execution-unit.scala:271:17]
wire [63:0] _ALUUnit_io_bypass_0_bits_data; // @[execution-unit.scala:271:17]
wire [63:0] _ALUUnit_io_bypass_1_bits_data; // @[execution-unit.scala:271:17]
wire [63:0] _ALUUnit_io_bypass_2_bits_data; // @[execution-unit.scala:271:17]
wire io_req_valid_0 = io_req_valid; // @[execution-unit.scala:204:7]
wire [6:0] io_req_bits_uop_uopc_0 = io_req_bits_uop_uopc; // @[execution-unit.scala:204:7]
wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[execution-unit.scala:204:7]
wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[execution-unit.scala:204:7]
wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[execution-unit.scala:204:7]
wire [2:0] io_req_bits_uop_iq_type_0 = io_req_bits_uop_iq_type; // @[execution-unit.scala:204:7]
wire [9:0] io_req_bits_uop_fu_code_0 = io_req_bits_uop_fu_code; // @[execution-unit.scala:204:7]
wire [3:0] io_req_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type; // @[execution-unit.scala:204:7]
wire [1:0] io_req_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:204:7]
wire [2:0] io_req_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:204:7]
wire [2:0] io_req_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:204:7]
wire [4:0] io_req_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:204:7]
wire [2:0] io_req_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std; // @[execution-unit.scala:204:7]
wire [1:0] io_req_bits_uop_iw_state_0 = io_req_bits_uop_iw_state; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_is_br_0 = io_req_bits_uop_is_br; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_is_jal_0 = io_req_bits_uop_is_jal; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[execution-unit.scala:204:7]
wire [7:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[execution-unit.scala:204:7]
wire [2:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[execution-unit.scala:204:7]
wire [3:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[execution-unit.scala:204:7]
wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[execution-unit.scala:204:7]
wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[execution-unit.scala:204:7]
wire [11:0] io_req_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr; // @[execution-unit.scala:204:7]
wire [4:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[execution-unit.scala:204:7]
wire [2:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[execution-unit.scala:204:7]
wire [2:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[execution-unit.scala:204:7]
wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[execution-unit.scala:204:7]
wire [5:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[execution-unit.scala:204:7]
wire [5:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[execution-unit.scala:204:7]
wire [5:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[execution-unit.scala:204:7]
wire [5:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[execution-unit.scala:204:7]
wire [3:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[execution-unit.scala:204:7]
wire [5:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[execution-unit.scala:204:7]
wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_bypassable_0 = io_req_bits_uop_bypassable; // @[execution-unit.scala:204:7]
wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[execution-unit.scala:204:7]
wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[execution-unit.scala:204:7]
wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[execution-unit.scala:204:7]
wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[execution-unit.scala:204:7]
wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[execution-unit.scala:204:7]
wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val; // @[execution-unit.scala:204:7]
wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[execution-unit.scala:204:7]
wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[execution-unit.scala:204:7]
wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_fp_single_0 = io_req_bits_uop_fp_single; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[execution-unit.scala:204:7]
wire [1:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[execution-unit.scala:204:7]
wire [1:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[execution-unit.scala:204:7]
wire [64:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data; // @[execution-unit.scala:204:7]
wire [64:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data; // @[execution-unit.scala:204:7]
wire io_req_bits_kill_0 = io_req_bits_kill; // @[execution-unit.scala:204:7]
wire io_ll_fresp_ready_0 = io_ll_fresp_ready; // @[execution-unit.scala:204:7]
wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[execution-unit.scala:204:7]
wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[execution-unit.scala:204:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[execution-unit.scala:204:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[execution-unit.scala:204:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[execution-unit.scala:204:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[execution-unit.scala:204:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[execution-unit.scala:204:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[execution-unit.scala:204:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[execution-unit.scala:204:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[execution-unit.scala:204:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[execution-unit.scala:204:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[execution-unit.scala:204:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[execution-unit.scala:204:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[execution-unit.scala:204:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[execution-unit.scala:204:7]
wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[execution-unit.scala:204:7]
wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[execution-unit.scala:204:7]
wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[execution-unit.scala:204:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[execution-unit.scala:204:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[execution-unit.scala:204:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[execution-unit.scala:204:7]
wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[execution-unit.scala:204:7]
wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[execution-unit.scala:204:7]
wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[execution-unit.scala:204:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[execution-unit.scala:204:7]
wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[execution-unit.scala:204:7]
wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[execution-unit.scala:204:7]
wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[execution-unit.scala:204:7]
wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[execution-unit.scala:204:7]
wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[execution-unit.scala:204:7]
wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[execution-unit.scala:204:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[execution-unit.scala:204:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[execution-unit.scala:204:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[execution-unit.scala:204:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[execution-unit.scala:204:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[execution-unit.scala:204:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[execution-unit.scala:204:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[execution-unit.scala:204:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[execution-unit.scala:204:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[execution-unit.scala:204:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[execution-unit.scala:204:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[execution-unit.scala:204:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[execution-unit.scala:204:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[execution-unit.scala:204:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[execution-unit.scala:204:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[execution-unit.scala:204:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[execution-unit.scala:204:7]
wire io_get_ftq_pc_entry_cfi_idx_valid_0 = io_get_ftq_pc_entry_cfi_idx_valid; // @[execution-unit.scala:204:7]
wire [1:0] io_get_ftq_pc_entry_cfi_idx_bits_0 = io_get_ftq_pc_entry_cfi_idx_bits; // @[execution-unit.scala:204:7]
wire io_get_ftq_pc_entry_cfi_taken_0 = io_get_ftq_pc_entry_cfi_taken; // @[execution-unit.scala:204:7]
wire io_get_ftq_pc_entry_cfi_mispredicted_0 = io_get_ftq_pc_entry_cfi_mispredicted; // @[execution-unit.scala:204:7]
wire [2:0] io_get_ftq_pc_entry_cfi_type_0 = io_get_ftq_pc_entry_cfi_type; // @[execution-unit.scala:204:7]
wire [3:0] io_get_ftq_pc_entry_br_mask_0 = io_get_ftq_pc_entry_br_mask; // @[execution-unit.scala:204:7]
wire io_get_ftq_pc_entry_cfi_is_call_0 = io_get_ftq_pc_entry_cfi_is_call; // @[execution-unit.scala:204:7]
wire io_get_ftq_pc_entry_cfi_is_ret_0 = io_get_ftq_pc_entry_cfi_is_ret; // @[execution-unit.scala:204:7]
wire io_get_ftq_pc_entry_cfi_npc_plus4_0 = io_get_ftq_pc_entry_cfi_npc_plus4; // @[execution-unit.scala:204:7]
wire [39:0] io_get_ftq_pc_entry_ras_top_0 = io_get_ftq_pc_entry_ras_top; // @[execution-unit.scala:204:7]
wire [4:0] io_get_ftq_pc_entry_ras_idx_0 = io_get_ftq_pc_entry_ras_idx; // @[execution-unit.scala:204:7]
wire io_get_ftq_pc_entry_start_bank_0 = io_get_ftq_pc_entry_start_bank; // @[execution-unit.scala:204:7]
wire [39:0] io_get_ftq_pc_pc_0 = io_get_ftq_pc_pc; // @[execution-unit.scala:204:7]
wire io_get_ftq_pc_next_val_0 = io_get_ftq_pc_next_val; // @[execution-unit.scala:204:7]
wire [39:0] io_get_ftq_pc_next_pc_0 = io_get_ftq_pc_next_pc; // @[execution-unit.scala:204:7]
wire io_status_debug_0 = io_status_debug; // @[execution-unit.scala:204:7]
wire io_status_cease_0 = io_status_cease; // @[execution-unit.scala:204:7]
wire io_status_wfi_0 = io_status_wfi; // @[execution-unit.scala:204:7]
wire [1:0] io_status_dprv_0 = io_status_dprv; // @[execution-unit.scala:204:7]
wire io_status_dv_0 = io_status_dv; // @[execution-unit.scala:204:7]
wire [1:0] io_status_prv_0 = io_status_prv; // @[execution-unit.scala:204:7]
wire io_status_v_0 = io_status_v; // @[execution-unit.scala:204:7]
wire io_status_sd_0 = io_status_sd; // @[execution-unit.scala:204:7]
wire io_status_mpv_0 = io_status_mpv; // @[execution-unit.scala:204:7]
wire io_status_gva_0 = io_status_gva; // @[execution-unit.scala:204:7]
wire io_status_tsr_0 = io_status_tsr; // @[execution-unit.scala:204:7]
wire io_status_tw_0 = io_status_tw; // @[execution-unit.scala:204:7]
wire io_status_tvm_0 = io_status_tvm; // @[execution-unit.scala:204:7]
wire io_status_mxr_0 = io_status_mxr; // @[execution-unit.scala:204:7]
wire io_status_sum_0 = io_status_sum; // @[execution-unit.scala:204:7]
wire io_status_mprv_0 = io_status_mprv; // @[execution-unit.scala:204:7]
wire [1:0] io_status_fs_0 = io_status_fs; // @[execution-unit.scala:204:7]
wire [1:0] io_status_mpp_0 = io_status_mpp; // @[execution-unit.scala:204:7]
wire io_status_spp_0 = io_status_spp; // @[execution-unit.scala:204:7]
wire io_status_mpie_0 = io_status_mpie; // @[execution-unit.scala:204:7]
wire io_status_spie_0 = io_status_spie; // @[execution-unit.scala:204:7]
wire io_status_mie_0 = io_status_mie; // @[execution-unit.scala:204:7]
wire io_status_sie_0 = io_status_sie; // @[execution-unit.scala:204:7]
wire [2:0] io_fcsr_rm_0 = io_fcsr_rm; // @[execution-unit.scala:204:7]
wire io_req_bits_pred_data = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_predicated = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_valid = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_is_rvc = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_is_br = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_is_jalr = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_is_jal = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_is_sfb = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_edge_inst = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_taken = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_exception = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_bypassable = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_mem_signed = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_is_fence = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_is_fencei = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_is_amo = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_uses_stq = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_is_unique = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_ldst_val = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_frs3_en = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_fp_val = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_fp_single = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_predicated = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_valid = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_is_rvc = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_is_br = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_is_jalr = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_is_jal = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_is_sfb = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_edge_inst = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_taken = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_exception = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_bypassable = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_mem_signed = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_is_fence = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_is_fencei = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_is_amo = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_uses_stq = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_is_unique = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_ldst_val = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_frs3_en = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_fp_val = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_fp_single = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_predicated = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_valid = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_is_rvc = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_is_br = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_is_jalr = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_is_jal = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_is_sfb = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_edge_inst = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_taken = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_exception = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_bypassable = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_mem_signed = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_is_fence = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_is_fencei = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_is_amo = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_uses_stq = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_is_unique = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_ldst_val = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_frs3_en = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_fp_val = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_fp_single = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_predicated = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_valid = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_is_rvc = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_is_br = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_is_jalr = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_is_jal = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_is_sfb = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_edge_inst = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_taken = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_exception = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_bypassable = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_mem_signed = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_is_fence = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_is_fencei = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_is_amo = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_uses_stq = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_is_unique = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_ldst_val = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_frs3_en = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_fp_val = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_fp_single = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_get_ftq_pc_ghist_current_saw_branch_not_taken = 1'h0; // @[execution-unit.scala:204:7]
wire io_get_ftq_pc_ghist_new_saw_branch_not_taken = 1'h0; // @[execution-unit.scala:204:7]
wire io_get_ftq_pc_ghist_new_saw_branch_taken = 1'h0; // @[execution-unit.scala:204:7]
wire io_status_mbe = 1'h0; // @[execution-unit.scala:204:7]
wire io_status_sbe = 1'h0; // @[execution-unit.scala:204:7]
wire io_status_sd_rv32 = 1'h0; // @[execution-unit.scala:204:7]
wire io_status_ube = 1'h0; // @[execution-unit.scala:204:7]
wire io_status_upie = 1'h0; // @[execution-unit.scala:204:7]
wire io_status_hie = 1'h0; // @[execution-unit.scala:204:7]
wire io_status_uie = 1'h0; // @[execution-unit.scala:204:7]
wire _io_iresp_bits_predicated_T = 1'h0; // @[Mux.scala:50:70]
wire _io_iresp_bits_predicated_T_1 = 1'h0; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_csr_addr_i30_20_T = 1'h0; // @[util.scala:274:27]
wire _io_iresp_bits_uop_csr_addr_i19_12_T = 1'h0; // @[util.scala:275:27]
wire _io_iresp_bits_uop_csr_addr_i19_12_T_1 = 1'h0; // @[util.scala:275:44]
wire _io_iresp_bits_uop_csr_addr_i19_12_T_2 = 1'h0; // @[util.scala:275:36]
wire _io_iresp_bits_uop_csr_addr_i11_T = 1'h0; // @[util.scala:276:27]
wire _io_iresp_bits_uop_csr_addr_i11_T_1 = 1'h0; // @[util.scala:277:27]
wire _io_iresp_bits_uop_csr_addr_i11_T_2 = 1'h0; // @[util.scala:277:44]
wire _io_iresp_bits_uop_csr_addr_i11_T_3 = 1'h0; // @[util.scala:277:36]
wire _io_iresp_bits_uop_csr_addr_i10_5_T = 1'h0; // @[util.scala:278:27]
wire _io_iresp_bits_uop_csr_addr_i4_1_T = 1'h0; // @[util.scala:279:27]
wire _io_iresp_bits_uop_csr_addr_i0_T = 1'h0; // @[util.scala:280:27]
wire [31:0] io_status_isa = 32'h14112D; // @[execution-unit.scala:204:7]
wire [22:0] io_status_zero2 = 23'h0; // @[execution-unit.scala:204:7]
wire [7:0] io_iresp_bits_fflags_bits_uop_br_mask = 8'h0; // @[execution-unit.scala:204:7]
wire [7:0] io_bypass_0_bits_fflags_bits_uop_br_mask = 8'h0; // @[execution-unit.scala:204:7]
wire [7:0] io_bypass_1_bits_fflags_bits_uop_br_mask = 8'h0; // @[execution-unit.scala:204:7]
wire [7:0] io_bypass_2_bits_fflags_bits_uop_br_mask = 8'h0; // @[execution-unit.scala:204:7]
wire [7:0] io_status_zero1 = 8'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_fflags_bits_uop_iw_state = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_fflags_bits_uop_mem_size = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_iw_state = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_mem_size = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_1_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_1_bits_fflags_bits_uop_iw_state = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_1_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_1_bits_fflags_bits_uop_mem_size = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_1_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_1_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_1_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_1_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_1_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_2_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_2_bits_fflags_bits_uop_iw_state = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_2_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_2_bits_fflags_bits_uop_mem_size = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_2_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_2_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_2_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_2_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_2_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_status_xs = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_status_vs = 2'h0; // @[execution-unit.scala:204:7]
wire io_req_ready = 1'h1; // @[execution-unit.scala:204:7]
wire io_iresp_ready = 1'h1; // @[execution-unit.scala:204:7]
wire _io_iresp_bits_uop_csr_addr_i0_T_1 = 1'h1; // @[util.scala:280:44]
wire _io_iresp_bits_uop_csr_addr_i0_T_2 = 1'h1; // @[util.scala:280:36]
wire [64:0] io_req_bits_rs3_data = 65'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_iresp_bits_fflags_bits_uop_uopc = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_0_bits_fflags_bits_uop_uopc = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_1_bits_fflags_bits_uop_uopc = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_2_bits_fflags_bits_uop_uopc = 7'h0; // @[execution-unit.scala:204:7]
wire [31:0] io_iresp_bits_fflags_bits_uop_inst = 32'h0; // @[execution-unit.scala:204:7]
wire [31:0] io_iresp_bits_fflags_bits_uop_debug_inst = 32'h0; // @[execution-unit.scala:204:7]
wire [31:0] io_bypass_0_bits_fflags_bits_uop_inst = 32'h0; // @[execution-unit.scala:204:7]
wire [31:0] io_bypass_0_bits_fflags_bits_uop_debug_inst = 32'h0; // @[execution-unit.scala:204:7]
wire [31:0] io_bypass_1_bits_fflags_bits_uop_inst = 32'h0; // @[execution-unit.scala:204:7]
wire [31:0] io_bypass_1_bits_fflags_bits_uop_debug_inst = 32'h0; // @[execution-unit.scala:204:7]
wire [31:0] io_bypass_2_bits_fflags_bits_uop_inst = 32'h0; // @[execution-unit.scala:204:7]
wire [31:0] io_bypass_2_bits_fflags_bits_uop_debug_inst = 32'h0; // @[execution-unit.scala:204:7]
wire [39:0] io_iresp_bits_fflags_bits_uop_debug_pc = 40'h0; // @[execution-unit.scala:204:7]
wire [39:0] io_bypass_0_bits_fflags_bits_uop_debug_pc = 40'h0; // @[execution-unit.scala:204:7]
wire [39:0] io_bypass_1_bits_fflags_bits_uop_debug_pc = 40'h0; // @[execution-unit.scala:204:7]
wire [39:0] io_bypass_2_bits_fflags_bits_uop_debug_pc = 40'h0; // @[execution-unit.scala:204:7]
wire [39:0] io_get_ftq_pc_com_pc = 40'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_iresp_bits_fflags_bits_uop_iq_type = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_iresp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_iresp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_iresp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_iresp_bits_fflags_bits_uop_br_tag = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_iresp_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_iresp_bits_fflags_bits_uop_stq_idx = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_0_bits_fflags_bits_uop_iq_type = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_0_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_0_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_0_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_0_bits_fflags_bits_uop_br_tag = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_0_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_0_bits_fflags_bits_uop_stq_idx = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_1_bits_fflags_bits_uop_iq_type = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_1_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_1_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_1_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_1_bits_fflags_bits_uop_br_tag = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_1_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_1_bits_fflags_bits_uop_stq_idx = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_2_bits_fflags_bits_uop_iq_type = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_2_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_2_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_2_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_2_bits_fflags_bits_uop_br_tag = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_2_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_2_bits_fflags_bits_uop_stq_idx = 3'h0; // @[execution-unit.scala:204:7]
wire [9:0] io_iresp_bits_fflags_bits_uop_fu_code = 10'h0; // @[execution-unit.scala:204:7]
wire [9:0] io_bypass_0_bits_fflags_bits_uop_fu_code = 10'h0; // @[execution-unit.scala:204:7]
wire [9:0] io_bypass_1_bits_fflags_bits_uop_fu_code = 10'h0; // @[execution-unit.scala:204:7]
wire [9:0] io_bypass_2_bits_fflags_bits_uop_fu_code = 10'h0; // @[execution-unit.scala:204:7]
wire [9:0] _io_fu_types_T_15 = 10'h0; // @[execution-unit.scala:266:21]
wire [3:0] io_iresp_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[execution-unit.scala:204:7]
wire [3:0] io_iresp_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[execution-unit.scala:204:7]
wire [3:0] io_iresp_bits_fflags_bits_uop_ppred = 4'h0; // @[execution-unit.scala:204:7]
wire [3:0] io_bypass_0_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[execution-unit.scala:204:7]
wire [3:0] io_bypass_0_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[execution-unit.scala:204:7]
wire [3:0] io_bypass_0_bits_fflags_bits_uop_ppred = 4'h0; // @[execution-unit.scala:204:7]
wire [3:0] io_bypass_1_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[execution-unit.scala:204:7]
wire [3:0] io_bypass_1_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[execution-unit.scala:204:7]
wire [3:0] io_bypass_1_bits_fflags_bits_uop_ppred = 4'h0; // @[execution-unit.scala:204:7]
wire [3:0] io_bypass_2_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[execution-unit.scala:204:7]
wire [3:0] io_bypass_2_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[execution-unit.scala:204:7]
wire [3:0] io_bypass_2_bits_fflags_bits_uop_ppred = 4'h0; // @[execution-unit.scala:204:7]
wire [3:0] io_get_ftq_pc_ftq_idx = 4'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_iresp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_iresp_bits_fflags_bits_uop_rob_idx = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_iresp_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_iresp_bits_fflags_bits_flags = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_0_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_0_bits_fflags_bits_uop_rob_idx = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_0_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_0_bits_fflags_bits_flags = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_1_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_1_bits_fflags_bits_uop_rob_idx = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_1_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_1_bits_fflags_bits_flags = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_2_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_2_bits_fflags_bits_uop_rob_idx = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_2_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_2_bits_fflags_bits_flags = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_get_ftq_pc_ghist_ras_idx = 5'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_iresp_bits_fflags_bits_uop_pc_lob = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_iresp_bits_fflags_bits_uop_pdst = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_iresp_bits_fflags_bits_uop_prs1 = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_iresp_bits_fflags_bits_uop_prs2 = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_iresp_bits_fflags_bits_uop_prs3 = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_iresp_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_iresp_bits_fflags_bits_uop_ldst = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_iresp_bits_fflags_bits_uop_lrs1 = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_iresp_bits_fflags_bits_uop_lrs2 = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_iresp_bits_fflags_bits_uop_lrs3 = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_0_bits_fflags_bits_uop_pc_lob = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_0_bits_fflags_bits_uop_pdst = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_0_bits_fflags_bits_uop_prs1 = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_0_bits_fflags_bits_uop_prs2 = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_0_bits_fflags_bits_uop_prs3 = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_0_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_0_bits_fflags_bits_uop_ldst = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_0_bits_fflags_bits_uop_lrs1 = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_0_bits_fflags_bits_uop_lrs2 = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_0_bits_fflags_bits_uop_lrs3 = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_1_bits_fflags_bits_uop_pc_lob = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_1_bits_fflags_bits_uop_pdst = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_1_bits_fflags_bits_uop_prs1 = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_1_bits_fflags_bits_uop_prs2 = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_1_bits_fflags_bits_uop_prs3 = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_1_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_1_bits_fflags_bits_uop_ldst = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_1_bits_fflags_bits_uop_lrs1 = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_1_bits_fflags_bits_uop_lrs2 = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_1_bits_fflags_bits_uop_lrs3 = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_2_bits_fflags_bits_uop_pc_lob = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_2_bits_fflags_bits_uop_pdst = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_2_bits_fflags_bits_uop_prs1 = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_2_bits_fflags_bits_uop_prs2 = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_2_bits_fflags_bits_uop_prs3 = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_2_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_2_bits_fflags_bits_uop_ldst = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_2_bits_fflags_bits_uop_lrs1 = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_2_bits_fflags_bits_uop_lrs2 = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_2_bits_fflags_bits_uop_lrs3 = 6'h0; // @[execution-unit.scala:204:7]
wire [19:0] io_iresp_bits_fflags_bits_uop_imm_packed = 20'h0; // @[execution-unit.scala:204:7]
wire [19:0] io_bypass_0_bits_fflags_bits_uop_imm_packed = 20'h0; // @[execution-unit.scala:204:7]
wire [19:0] io_bypass_1_bits_fflags_bits_uop_imm_packed = 20'h0; // @[execution-unit.scala:204:7]
wire [19:0] io_bypass_2_bits_fflags_bits_uop_imm_packed = 20'h0; // @[execution-unit.scala:204:7]
wire [11:0] io_iresp_bits_fflags_bits_uop_csr_addr = 12'h0; // @[execution-unit.scala:204:7]
wire [11:0] io_bypass_0_bits_fflags_bits_uop_csr_addr = 12'h0; // @[execution-unit.scala:204:7]
wire [11:0] io_bypass_1_bits_fflags_bits_uop_csr_addr = 12'h0; // @[execution-unit.scala:204:7]
wire [11:0] io_bypass_2_bits_fflags_bits_uop_csr_addr = 12'h0; // @[execution-unit.scala:204:7]
wire [63:0] io_iresp_bits_fflags_bits_uop_exc_cause = 64'h0; // @[execution-unit.scala:204:7]
wire [63:0] io_bypass_0_bits_fflags_bits_uop_exc_cause = 64'h0; // @[execution-unit.scala:204:7]
wire [63:0] io_bypass_1_bits_fflags_bits_uop_exc_cause = 64'h0; // @[execution-unit.scala:204:7]
wire [63:0] io_bypass_2_bits_fflags_bits_uop_exc_cause = 64'h0; // @[execution-unit.scala:204:7]
wire [63:0] io_get_ftq_pc_ghist_old_history = 64'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_status_sxl = 2'h2; // @[execution-unit.scala:204:7]
wire [1:0] io_status_uxl = 2'h2; // @[execution-unit.scala:204:7]
wire [9:0] _io_fu_types_T_9 = 10'h2; // @[execution-unit.scala:264:21]
wire [9:0] _io_fu_types_T_7 = 10'h20; // @[execution-unit.scala:263:21]
wire [9:0] _io_fu_types_T_2 = 10'h9; // @[execution-unit.scala:260:45]
wire [9:0] _io_fu_types_T_1 = 10'h8; // @[execution-unit.scala:261:21]
wire [9:0] _io_fu_types_T = 10'h1; // @[execution-unit.scala:260:21]
wire [9:0] _io_fu_types_T_16; // @[execution-unit.scala:265:60]
wire _io_iresp_valid_T_1; // @[execution-unit.scala:409:71]
wire [6:0] _io_iresp_bits_uop_T_1_uopc; // @[Mux.scala:50:70]
wire [31:0] _io_iresp_bits_uop_T_1_inst; // @[Mux.scala:50:70]
wire [31:0] _io_iresp_bits_uop_T_1_debug_inst; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_1_is_rvc; // @[Mux.scala:50:70]
wire [39:0] _io_iresp_bits_uop_T_1_debug_pc; // @[Mux.scala:50:70]
wire [2:0] _io_iresp_bits_uop_T_1_iq_type; // @[Mux.scala:50:70]
wire [9:0] _io_iresp_bits_uop_T_1_fu_code; // @[Mux.scala:50:70]
wire [3:0] _io_iresp_bits_uop_T_1_ctrl_br_type; // @[Mux.scala:50:70]
wire [1:0] _io_iresp_bits_uop_T_1_ctrl_op1_sel; // @[Mux.scala:50:70]
wire [2:0] _io_iresp_bits_uop_T_1_ctrl_op2_sel; // @[Mux.scala:50:70]
wire [2:0] _io_iresp_bits_uop_T_1_ctrl_imm_sel; // @[Mux.scala:50:70]
wire [4:0] _io_iresp_bits_uop_T_1_ctrl_op_fcn; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_1_ctrl_fcn_dw; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_1_ctrl_is_load; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_1_ctrl_is_sta; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_1_ctrl_is_std; // @[Mux.scala:50:70]
wire [1:0] _io_iresp_bits_uop_T_1_iw_state; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_1_iw_p1_poisoned; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_1_iw_p2_poisoned; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_1_is_br; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_1_is_jalr; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_1_is_jal; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_1_is_sfb; // @[Mux.scala:50:70]
wire [7:0] _io_iresp_bits_uop_T_1_br_mask; // @[Mux.scala:50:70]
wire [2:0] _io_iresp_bits_uop_T_1_br_tag; // @[Mux.scala:50:70]
wire [3:0] _io_iresp_bits_uop_T_1_ftq_idx; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_1_edge_inst; // @[Mux.scala:50:70]
wire [5:0] _io_iresp_bits_uop_T_1_pc_lob; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_1_taken; // @[Mux.scala:50:70]
wire [19:0] _io_iresp_bits_uop_T_1_imm_packed; // @[Mux.scala:50:70]
wire [4:0] _io_iresp_bits_uop_T_1_rob_idx; // @[Mux.scala:50:70]
wire [2:0] _io_iresp_bits_uop_T_1_ldq_idx; // @[Mux.scala:50:70]
wire [2:0] _io_iresp_bits_uop_T_1_stq_idx; // @[Mux.scala:50:70]
wire [1:0] _io_iresp_bits_uop_T_1_rxq_idx; // @[Mux.scala:50:70]
wire [5:0] _io_iresp_bits_uop_T_1_pdst; // @[Mux.scala:50:70]
wire [5:0] _io_iresp_bits_uop_T_1_prs1; // @[Mux.scala:50:70]
wire [5:0] _io_iresp_bits_uop_T_1_prs2; // @[Mux.scala:50:70]
wire [5:0] _io_iresp_bits_uop_T_1_prs3; // @[Mux.scala:50:70]
wire [3:0] _io_iresp_bits_uop_T_1_ppred; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_1_prs1_busy; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_1_prs2_busy; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_1_prs3_busy; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_1_ppred_busy; // @[Mux.scala:50:70]
wire [5:0] _io_iresp_bits_uop_T_1_stale_pdst; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_1_exception; // @[Mux.scala:50:70]
wire [63:0] _io_iresp_bits_uop_T_1_exc_cause; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_1_bypassable; // @[Mux.scala:50:70]
wire [4:0] _io_iresp_bits_uop_T_1_mem_cmd; // @[Mux.scala:50:70]
wire [1:0] _io_iresp_bits_uop_T_1_mem_size; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_1_mem_signed; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_1_is_fence; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_1_is_fencei; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_1_is_amo; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_1_uses_ldq; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_1_uses_stq; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_1_is_sys_pc2epc; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_1_is_unique; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_1_flush_on_commit; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_1_ldst_is_rs1; // @[Mux.scala:50:70]
wire [5:0] _io_iresp_bits_uop_T_1_ldst; // @[Mux.scala:50:70]
wire [5:0] _io_iresp_bits_uop_T_1_lrs1; // @[Mux.scala:50:70]
wire [5:0] _io_iresp_bits_uop_T_1_lrs2; // @[Mux.scala:50:70]
wire [5:0] _io_iresp_bits_uop_T_1_lrs3; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_1_ldst_val; // @[Mux.scala:50:70]
wire [1:0] _io_iresp_bits_uop_T_1_dst_rtype; // @[Mux.scala:50:70]
wire [1:0] _io_iresp_bits_uop_T_1_lrs1_rtype; // @[Mux.scala:50:70]
wire [1:0] _io_iresp_bits_uop_T_1_lrs2_rtype; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_1_frs3_en; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_1_fp_val; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_1_fp_single; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_1_xcpt_pf_if; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_1_xcpt_ae_if; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_1_xcpt_ma_if; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_1_bp_debug_if; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_1_bp_xcpt_if; // @[Mux.scala:50:70]
wire [1:0] _io_iresp_bits_uop_T_1_debug_fsrc; // @[Mux.scala:50:70]
wire [1:0] _io_iresp_bits_uop_T_1_debug_tsrc; // @[Mux.scala:50:70]
wire [3:0] io_iresp_bits_uop_ctrl_br_type_0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_uop_ctrl_op1_sel_0; // @[execution-unit.scala:204:7]
wire [2:0] io_iresp_bits_uop_ctrl_op2_sel_0; // @[execution-unit.scala:204:7]
wire [2:0] io_iresp_bits_uop_ctrl_imm_sel_0; // @[execution-unit.scala:204:7]
wire [4:0] io_iresp_bits_uop_ctrl_op_fcn_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_ctrl_fcn_dw_0; // @[execution-unit.scala:204:7]
wire [2:0] io_iresp_bits_uop_ctrl_csr_cmd_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_ctrl_is_load_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_ctrl_is_sta_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_ctrl_is_std_0; // @[execution-unit.scala:204:7]
wire [6:0] io_iresp_bits_uop_uopc_0; // @[execution-unit.scala:204:7]
wire [31:0] io_iresp_bits_uop_inst_0; // @[execution-unit.scala:204:7]
wire [31:0] io_iresp_bits_uop_debug_inst_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_is_rvc_0; // @[execution-unit.scala:204:7]
wire [39:0] io_iresp_bits_uop_debug_pc_0; // @[execution-unit.scala:204:7]
wire [2:0] io_iresp_bits_uop_iq_type_0; // @[execution-unit.scala:204:7]
wire [9:0] io_iresp_bits_uop_fu_code_0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_uop_iw_state_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_iw_p1_poisoned_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_iw_p2_poisoned_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_is_br_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_is_jalr_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_is_jal_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_is_sfb_0; // @[execution-unit.scala:204:7]
wire [7:0] io_iresp_bits_uop_br_mask_0; // @[execution-unit.scala:204:7]
wire [2:0] io_iresp_bits_uop_br_tag_0; // @[execution-unit.scala:204:7]
wire [3:0] io_iresp_bits_uop_ftq_idx_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_edge_inst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_iresp_bits_uop_pc_lob_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_taken_0; // @[execution-unit.scala:204:7]
wire [19:0] io_iresp_bits_uop_imm_packed_0; // @[execution-unit.scala:204:7]
wire [11:0] io_iresp_bits_uop_csr_addr_0; // @[execution-unit.scala:204:7]
wire [4:0] io_iresp_bits_uop_rob_idx_0; // @[execution-unit.scala:204:7]
wire [2:0] io_iresp_bits_uop_ldq_idx_0; // @[execution-unit.scala:204:7]
wire [2:0] io_iresp_bits_uop_stq_idx_0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_uop_rxq_idx_0; // @[execution-unit.scala:204:7]
wire [5:0] io_iresp_bits_uop_pdst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_iresp_bits_uop_prs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_iresp_bits_uop_prs2_0; // @[execution-unit.scala:204:7]
wire [5:0] io_iresp_bits_uop_prs3_0; // @[execution-unit.scala:204:7]
wire [3:0] io_iresp_bits_uop_ppred_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_prs1_busy_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_prs2_busy_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_prs3_busy_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_ppred_busy_0; // @[execution-unit.scala:204:7]
wire [5:0] io_iresp_bits_uop_stale_pdst_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_exception_0; // @[execution-unit.scala:204:7]
wire [63:0] io_iresp_bits_uop_exc_cause_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_bypassable_0; // @[execution-unit.scala:204:7]
wire [4:0] io_iresp_bits_uop_mem_cmd_0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_uop_mem_size_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_mem_signed_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_is_fence_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_is_fencei_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_is_amo_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_uses_ldq_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_uses_stq_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_is_sys_pc2epc_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_is_unique_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_flush_on_commit_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_ldst_is_rs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_iresp_bits_uop_ldst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_iresp_bits_uop_lrs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_iresp_bits_uop_lrs2_0; // @[execution-unit.scala:204:7]
wire [5:0] io_iresp_bits_uop_lrs3_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_ldst_val_0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_uop_dst_rtype_0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_uop_lrs1_rtype_0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_uop_lrs2_rtype_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_frs3_en_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_fp_val_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_fp_single_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_xcpt_pf_if_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_xcpt_ae_if_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_xcpt_ma_if_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_bp_debug_if_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_bp_xcpt_if_0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_uop_debug_fsrc_0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_uop_debug_tsrc_0; // @[execution-unit.scala:204:7]
wire [64:0] io_iresp_bits_data_0; // @[execution-unit.scala:204:7]
wire io_iresp_valid_0; // @[execution-unit.scala:204:7]
wire [3:0] io_ll_fresp_bits_uop_ctrl_br_type_0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_fresp_bits_uop_ctrl_op1_sel_0; // @[execution-unit.scala:204:7]
wire [2:0] io_ll_fresp_bits_uop_ctrl_op2_sel_0; // @[execution-unit.scala:204:7]
wire [2:0] io_ll_fresp_bits_uop_ctrl_imm_sel_0; // @[execution-unit.scala:204:7]
wire [4:0] io_ll_fresp_bits_uop_ctrl_op_fcn_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_ctrl_fcn_dw_0; // @[execution-unit.scala:204:7]
wire [2:0] io_ll_fresp_bits_uop_ctrl_csr_cmd_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_ctrl_is_load_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_ctrl_is_sta_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_ctrl_is_std_0; // @[execution-unit.scala:204:7]
wire [6:0] io_ll_fresp_bits_uop_uopc_0; // @[execution-unit.scala:204:7]
wire [31:0] io_ll_fresp_bits_uop_inst_0; // @[execution-unit.scala:204:7]
wire [31:0] io_ll_fresp_bits_uop_debug_inst_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_is_rvc_0; // @[execution-unit.scala:204:7]
wire [39:0] io_ll_fresp_bits_uop_debug_pc_0; // @[execution-unit.scala:204:7]
wire [2:0] io_ll_fresp_bits_uop_iq_type_0; // @[execution-unit.scala:204:7]
wire [9:0] io_ll_fresp_bits_uop_fu_code_0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_fresp_bits_uop_iw_state_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_iw_p1_poisoned_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_iw_p2_poisoned_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_is_br_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_is_jalr_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_is_jal_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_is_sfb_0; // @[execution-unit.scala:204:7]
wire [7:0] io_ll_fresp_bits_uop_br_mask_0; // @[execution-unit.scala:204:7]
wire [2:0] io_ll_fresp_bits_uop_br_tag_0; // @[execution-unit.scala:204:7]
wire [3:0] io_ll_fresp_bits_uop_ftq_idx_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_edge_inst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_ll_fresp_bits_uop_pc_lob_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_taken_0; // @[execution-unit.scala:204:7]
wire [19:0] io_ll_fresp_bits_uop_imm_packed_0; // @[execution-unit.scala:204:7]
wire [11:0] io_ll_fresp_bits_uop_csr_addr_0; // @[execution-unit.scala:204:7]
wire [4:0] io_ll_fresp_bits_uop_rob_idx_0; // @[execution-unit.scala:204:7]
wire [2:0] io_ll_fresp_bits_uop_ldq_idx_0; // @[execution-unit.scala:204:7]
wire [2:0] io_ll_fresp_bits_uop_stq_idx_0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_fresp_bits_uop_rxq_idx_0; // @[execution-unit.scala:204:7]
wire [5:0] io_ll_fresp_bits_uop_pdst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_ll_fresp_bits_uop_prs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_ll_fresp_bits_uop_prs2_0; // @[execution-unit.scala:204:7]
wire [5:0] io_ll_fresp_bits_uop_prs3_0; // @[execution-unit.scala:204:7]
wire [3:0] io_ll_fresp_bits_uop_ppred_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_prs1_busy_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_prs2_busy_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_prs3_busy_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_ppred_busy_0; // @[execution-unit.scala:204:7]
wire [5:0] io_ll_fresp_bits_uop_stale_pdst_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_exception_0; // @[execution-unit.scala:204:7]
wire [63:0] io_ll_fresp_bits_uop_exc_cause_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_bypassable_0; // @[execution-unit.scala:204:7]
wire [4:0] io_ll_fresp_bits_uop_mem_cmd_0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_fresp_bits_uop_mem_size_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_mem_signed_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_is_fence_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_is_fencei_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_is_amo_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_uses_ldq_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_uses_stq_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_is_sys_pc2epc_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_is_unique_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_flush_on_commit_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_ldst_is_rs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_ll_fresp_bits_uop_ldst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_ll_fresp_bits_uop_lrs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_ll_fresp_bits_uop_lrs2_0; // @[execution-unit.scala:204:7]
wire [5:0] io_ll_fresp_bits_uop_lrs3_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_ldst_val_0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_fresp_bits_uop_dst_rtype_0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_fresp_bits_uop_lrs1_rtype_0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_fresp_bits_uop_lrs2_rtype_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_frs3_en_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_fp_val_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_fp_single_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_xcpt_pf_if_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_xcpt_ae_if_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_xcpt_ma_if_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_bp_debug_if_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_bp_xcpt_if_0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_fresp_bits_uop_debug_fsrc_0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_fresp_bits_uop_debug_tsrc_0; // @[execution-unit.scala:204:7]
wire [3:0] io_ll_fresp_bits_fflags_bits_uop_ctrl_br_type_0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_fresp_bits_fflags_bits_uop_ctrl_op1_sel_0; // @[execution-unit.scala:204:7]
wire [2:0] io_ll_fresp_bits_fflags_bits_uop_ctrl_op2_sel_0; // @[execution-unit.scala:204:7]
wire [2:0] io_ll_fresp_bits_fflags_bits_uop_ctrl_imm_sel_0; // @[execution-unit.scala:204:7]
wire [4:0] io_ll_fresp_bits_fflags_bits_uop_ctrl_op_fcn_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_ctrl_fcn_dw_0; // @[execution-unit.scala:204:7]
wire [2:0] io_ll_fresp_bits_fflags_bits_uop_ctrl_csr_cmd_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_ctrl_is_load_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_ctrl_is_sta_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_ctrl_is_std_0; // @[execution-unit.scala:204:7]
wire [6:0] io_ll_fresp_bits_fflags_bits_uop_uopc_0; // @[execution-unit.scala:204:7]
wire [31:0] io_ll_fresp_bits_fflags_bits_uop_inst_0; // @[execution-unit.scala:204:7]
wire [31:0] io_ll_fresp_bits_fflags_bits_uop_debug_inst_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_is_rvc_0; // @[execution-unit.scala:204:7]
wire [39:0] io_ll_fresp_bits_fflags_bits_uop_debug_pc_0; // @[execution-unit.scala:204:7]
wire [2:0] io_ll_fresp_bits_fflags_bits_uop_iq_type_0; // @[execution-unit.scala:204:7]
wire [9:0] io_ll_fresp_bits_fflags_bits_uop_fu_code_0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_fresp_bits_fflags_bits_uop_iw_state_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_iw_p1_poisoned_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_iw_p2_poisoned_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_is_br_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_is_jalr_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_is_jal_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_is_sfb_0; // @[execution-unit.scala:204:7]
wire [7:0] io_ll_fresp_bits_fflags_bits_uop_br_mask_0; // @[execution-unit.scala:204:7]
wire [2:0] io_ll_fresp_bits_fflags_bits_uop_br_tag_0; // @[execution-unit.scala:204:7]
wire [3:0] io_ll_fresp_bits_fflags_bits_uop_ftq_idx_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_edge_inst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_ll_fresp_bits_fflags_bits_uop_pc_lob_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_taken_0; // @[execution-unit.scala:204:7]
wire [19:0] io_ll_fresp_bits_fflags_bits_uop_imm_packed_0; // @[execution-unit.scala:204:7]
wire [11:0] io_ll_fresp_bits_fflags_bits_uop_csr_addr_0; // @[execution-unit.scala:204:7]
wire [4:0] io_ll_fresp_bits_fflags_bits_uop_rob_idx_0; // @[execution-unit.scala:204:7]
wire [2:0] io_ll_fresp_bits_fflags_bits_uop_ldq_idx_0; // @[execution-unit.scala:204:7]
wire [2:0] io_ll_fresp_bits_fflags_bits_uop_stq_idx_0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_fresp_bits_fflags_bits_uop_rxq_idx_0; // @[execution-unit.scala:204:7]
wire [5:0] io_ll_fresp_bits_fflags_bits_uop_pdst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_ll_fresp_bits_fflags_bits_uop_prs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_ll_fresp_bits_fflags_bits_uop_prs2_0; // @[execution-unit.scala:204:7]
wire [5:0] io_ll_fresp_bits_fflags_bits_uop_prs3_0; // @[execution-unit.scala:204:7]
wire [3:0] io_ll_fresp_bits_fflags_bits_uop_ppred_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_prs1_busy_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_prs2_busy_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_prs3_busy_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_ppred_busy_0; // @[execution-unit.scala:204:7]
wire [5:0] io_ll_fresp_bits_fflags_bits_uop_stale_pdst_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_exception_0; // @[execution-unit.scala:204:7]
wire [63:0] io_ll_fresp_bits_fflags_bits_uop_exc_cause_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_bypassable_0; // @[execution-unit.scala:204:7]
wire [4:0] io_ll_fresp_bits_fflags_bits_uop_mem_cmd_0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_fresp_bits_fflags_bits_uop_mem_size_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_mem_signed_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_is_fence_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_is_fencei_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_is_amo_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_uses_ldq_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_uses_stq_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_is_sys_pc2epc_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_is_unique_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_flush_on_commit_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_ldst_is_rs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_ll_fresp_bits_fflags_bits_uop_ldst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_ll_fresp_bits_fflags_bits_uop_lrs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_ll_fresp_bits_fflags_bits_uop_lrs2_0; // @[execution-unit.scala:204:7]
wire [5:0] io_ll_fresp_bits_fflags_bits_uop_lrs3_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_ldst_val_0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_fresp_bits_fflags_bits_uop_dst_rtype_0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_fresp_bits_fflags_bits_uop_lrs1_rtype_0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_fresp_bits_fflags_bits_uop_lrs2_rtype_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_frs3_en_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_fp_val_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_fp_single_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_xcpt_pf_if_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_xcpt_ae_if_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_xcpt_ma_if_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_bp_debug_if_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_bp_xcpt_if_0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_fresp_bits_fflags_bits_uop_debug_fsrc_0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_fresp_bits_fflags_bits_uop_debug_tsrc_0; // @[execution-unit.scala:204:7]
wire [4:0] io_ll_fresp_bits_fflags_bits_flags_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_valid_0; // @[execution-unit.scala:204:7]
wire [64:0] io_ll_fresp_bits_data_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_predicated_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_valid_0; // @[execution-unit.scala:204:7]
wire [3:0] io_bypass_0_bits_uop_ctrl_br_type_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_uop_ctrl_op1_sel_0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_0_bits_uop_ctrl_op2_sel_0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_0_bits_uop_ctrl_imm_sel_0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_0_bits_uop_ctrl_op_fcn_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_ctrl_fcn_dw_0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_0_bits_uop_ctrl_csr_cmd_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_ctrl_is_load_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_ctrl_is_sta_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_ctrl_is_std_0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_0_bits_uop_uopc_0; // @[execution-unit.scala:204:7]
wire [31:0] io_bypass_0_bits_uop_inst_0; // @[execution-unit.scala:204:7]
wire [31:0] io_bypass_0_bits_uop_debug_inst_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_is_rvc_0; // @[execution-unit.scala:204:7]
wire [39:0] io_bypass_0_bits_uop_debug_pc_0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_0_bits_uop_iq_type_0; // @[execution-unit.scala:204:7]
wire [9:0] io_bypass_0_bits_uop_fu_code_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_uop_iw_state_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_iw_p1_poisoned_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_iw_p2_poisoned_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_is_br_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_is_jalr_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_is_jal_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_is_sfb_0; // @[execution-unit.scala:204:7]
wire [7:0] io_bypass_0_bits_uop_br_mask_0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_0_bits_uop_br_tag_0; // @[execution-unit.scala:204:7]
wire [3:0] io_bypass_0_bits_uop_ftq_idx_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_edge_inst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_0_bits_uop_pc_lob_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_taken_0; // @[execution-unit.scala:204:7]
wire [19:0] io_bypass_0_bits_uop_imm_packed_0; // @[execution-unit.scala:204:7]
wire [11:0] io_bypass_0_bits_uop_csr_addr_0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_0_bits_uop_rob_idx_0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_0_bits_uop_ldq_idx_0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_0_bits_uop_stq_idx_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_uop_rxq_idx_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_0_bits_uop_pdst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_0_bits_uop_prs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_0_bits_uop_prs2_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_0_bits_uop_prs3_0; // @[execution-unit.scala:204:7]
wire [3:0] io_bypass_0_bits_uop_ppred_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_prs1_busy_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_prs2_busy_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_prs3_busy_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_ppred_busy_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_0_bits_uop_stale_pdst_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_exception_0; // @[execution-unit.scala:204:7]
wire [63:0] io_bypass_0_bits_uop_exc_cause_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_bypassable_0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_0_bits_uop_mem_cmd_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_uop_mem_size_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_mem_signed_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_is_fence_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_is_fencei_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_is_amo_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_uses_ldq_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_uses_stq_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_is_sys_pc2epc_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_is_unique_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_flush_on_commit_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_ldst_is_rs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_0_bits_uop_ldst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_0_bits_uop_lrs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_0_bits_uop_lrs2_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_0_bits_uop_lrs3_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_ldst_val_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_uop_dst_rtype_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_uop_lrs1_rtype_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_uop_lrs2_rtype_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_frs3_en_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_fp_val_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_fp_single_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_xcpt_pf_if_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_xcpt_ae_if_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_xcpt_ma_if_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_bp_debug_if_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_bp_xcpt_if_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_uop_debug_fsrc_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_uop_debug_tsrc_0; // @[execution-unit.scala:204:7]
wire [64:0] io_bypass_0_bits_data_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_valid_0; // @[execution-unit.scala:204:7]
wire [3:0] io_bypass_1_bits_uop_ctrl_br_type_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_1_bits_uop_ctrl_op1_sel_0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_1_bits_uop_ctrl_op2_sel_0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_1_bits_uop_ctrl_imm_sel_0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_1_bits_uop_ctrl_op_fcn_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_ctrl_fcn_dw_0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_1_bits_uop_ctrl_csr_cmd_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_ctrl_is_load_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_ctrl_is_sta_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_ctrl_is_std_0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_1_bits_uop_uopc_0; // @[execution-unit.scala:204:7]
wire [31:0] io_bypass_1_bits_uop_inst_0; // @[execution-unit.scala:204:7]
wire [31:0] io_bypass_1_bits_uop_debug_inst_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_is_rvc_0; // @[execution-unit.scala:204:7]
wire [39:0] io_bypass_1_bits_uop_debug_pc_0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_1_bits_uop_iq_type_0; // @[execution-unit.scala:204:7]
wire [9:0] io_bypass_1_bits_uop_fu_code_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_1_bits_uop_iw_state_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_iw_p1_poisoned_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_iw_p2_poisoned_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_is_br_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_is_jalr_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_is_jal_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_is_sfb_0; // @[execution-unit.scala:204:7]
wire [7:0] io_bypass_1_bits_uop_br_mask_0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_1_bits_uop_br_tag_0; // @[execution-unit.scala:204:7]
wire [3:0] io_bypass_1_bits_uop_ftq_idx_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_edge_inst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_1_bits_uop_pc_lob_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_taken_0; // @[execution-unit.scala:204:7]
wire [19:0] io_bypass_1_bits_uop_imm_packed_0; // @[execution-unit.scala:204:7]
wire [11:0] io_bypass_1_bits_uop_csr_addr_0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_1_bits_uop_rob_idx_0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_1_bits_uop_ldq_idx_0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_1_bits_uop_stq_idx_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_1_bits_uop_rxq_idx_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_1_bits_uop_pdst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_1_bits_uop_prs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_1_bits_uop_prs2_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_1_bits_uop_prs3_0; // @[execution-unit.scala:204:7]
wire [3:0] io_bypass_1_bits_uop_ppred_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_prs1_busy_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_prs2_busy_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_prs3_busy_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_ppred_busy_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_1_bits_uop_stale_pdst_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_exception_0; // @[execution-unit.scala:204:7]
wire [63:0] io_bypass_1_bits_uop_exc_cause_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_bypassable_0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_1_bits_uop_mem_cmd_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_1_bits_uop_mem_size_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_mem_signed_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_is_fence_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_is_fencei_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_is_amo_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_uses_ldq_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_uses_stq_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_is_sys_pc2epc_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_is_unique_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_flush_on_commit_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_ldst_is_rs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_1_bits_uop_ldst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_1_bits_uop_lrs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_1_bits_uop_lrs2_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_1_bits_uop_lrs3_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_ldst_val_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_1_bits_uop_dst_rtype_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_1_bits_uop_lrs1_rtype_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_1_bits_uop_lrs2_rtype_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_frs3_en_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_fp_val_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_fp_single_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_xcpt_pf_if_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_xcpt_ae_if_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_xcpt_ma_if_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_bp_debug_if_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_bp_xcpt_if_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_1_bits_uop_debug_fsrc_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_1_bits_uop_debug_tsrc_0; // @[execution-unit.scala:204:7]
wire [64:0] io_bypass_1_bits_data_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_valid_0; // @[execution-unit.scala:204:7]
wire [3:0] io_bypass_2_bits_uop_ctrl_br_type_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_2_bits_uop_ctrl_op1_sel_0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_2_bits_uop_ctrl_op2_sel_0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_2_bits_uop_ctrl_imm_sel_0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_2_bits_uop_ctrl_op_fcn_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_ctrl_fcn_dw_0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_2_bits_uop_ctrl_csr_cmd_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_ctrl_is_load_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_ctrl_is_sta_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_ctrl_is_std_0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_2_bits_uop_uopc_0; // @[execution-unit.scala:204:7]
wire [31:0] io_bypass_2_bits_uop_inst_0; // @[execution-unit.scala:204:7]
wire [31:0] io_bypass_2_bits_uop_debug_inst_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_is_rvc_0; // @[execution-unit.scala:204:7]
wire [39:0] io_bypass_2_bits_uop_debug_pc_0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_2_bits_uop_iq_type_0; // @[execution-unit.scala:204:7]
wire [9:0] io_bypass_2_bits_uop_fu_code_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_2_bits_uop_iw_state_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_iw_p1_poisoned_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_iw_p2_poisoned_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_is_br_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_is_jalr_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_is_jal_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_is_sfb_0; // @[execution-unit.scala:204:7]
wire [7:0] io_bypass_2_bits_uop_br_mask_0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_2_bits_uop_br_tag_0; // @[execution-unit.scala:204:7]
wire [3:0] io_bypass_2_bits_uop_ftq_idx_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_edge_inst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_2_bits_uop_pc_lob_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_taken_0; // @[execution-unit.scala:204:7]
wire [19:0] io_bypass_2_bits_uop_imm_packed_0; // @[execution-unit.scala:204:7]
wire [11:0] io_bypass_2_bits_uop_csr_addr_0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_2_bits_uop_rob_idx_0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_2_bits_uop_ldq_idx_0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_2_bits_uop_stq_idx_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_2_bits_uop_rxq_idx_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_2_bits_uop_pdst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_2_bits_uop_prs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_2_bits_uop_prs2_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_2_bits_uop_prs3_0; // @[execution-unit.scala:204:7]
wire [3:0] io_bypass_2_bits_uop_ppred_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_prs1_busy_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_prs2_busy_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_prs3_busy_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_ppred_busy_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_2_bits_uop_stale_pdst_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_exception_0; // @[execution-unit.scala:204:7]
wire [63:0] io_bypass_2_bits_uop_exc_cause_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_bypassable_0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_2_bits_uop_mem_cmd_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_2_bits_uop_mem_size_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_mem_signed_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_is_fence_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_is_fencei_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_is_amo_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_uses_ldq_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_uses_stq_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_is_sys_pc2epc_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_is_unique_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_flush_on_commit_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_ldst_is_rs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_2_bits_uop_ldst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_2_bits_uop_lrs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_2_bits_uop_lrs2_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_2_bits_uop_lrs3_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_ldst_val_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_2_bits_uop_dst_rtype_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_2_bits_uop_lrs1_rtype_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_2_bits_uop_lrs2_rtype_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_frs3_en_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_fp_val_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_fp_single_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_xcpt_pf_if_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_xcpt_ae_if_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_xcpt_ma_if_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_bp_debug_if_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_bp_xcpt_if_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_2_bits_uop_debug_fsrc_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_2_bits_uop_debug_tsrc_0; // @[execution-unit.scala:204:7]
wire [64:0] io_bypass_2_bits_data_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_valid_0; // @[execution-unit.scala:204:7]
wire [3:0] io_brinfo_uop_ctrl_br_type_0; // @[execution-unit.scala:204:7]
wire [1:0] io_brinfo_uop_ctrl_op1_sel_0; // @[execution-unit.scala:204:7]
wire [2:0] io_brinfo_uop_ctrl_op2_sel_0; // @[execution-unit.scala:204:7]
wire [2:0] io_brinfo_uop_ctrl_imm_sel_0; // @[execution-unit.scala:204:7]
wire [4:0] io_brinfo_uop_ctrl_op_fcn_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_ctrl_fcn_dw_0; // @[execution-unit.scala:204:7]
wire [2:0] io_brinfo_uop_ctrl_csr_cmd_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_ctrl_is_load_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_ctrl_is_sta_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_ctrl_is_std_0; // @[execution-unit.scala:204:7]
wire [6:0] io_brinfo_uop_uopc_0; // @[execution-unit.scala:204:7]
wire [31:0] io_brinfo_uop_inst_0; // @[execution-unit.scala:204:7]
wire [31:0] io_brinfo_uop_debug_inst_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_is_rvc_0; // @[execution-unit.scala:204:7]
wire [39:0] io_brinfo_uop_debug_pc_0; // @[execution-unit.scala:204:7]
wire [2:0] io_brinfo_uop_iq_type_0; // @[execution-unit.scala:204:7]
wire [9:0] io_brinfo_uop_fu_code_0; // @[execution-unit.scala:204:7]
wire [1:0] io_brinfo_uop_iw_state_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_iw_p1_poisoned_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_iw_p2_poisoned_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_is_br_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_is_jalr_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_is_jal_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_is_sfb_0; // @[execution-unit.scala:204:7]
wire [7:0] io_brinfo_uop_br_mask_0; // @[execution-unit.scala:204:7]
wire [2:0] io_brinfo_uop_br_tag_0; // @[execution-unit.scala:204:7]
wire [3:0] io_brinfo_uop_ftq_idx_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_edge_inst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_brinfo_uop_pc_lob_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_taken_0; // @[execution-unit.scala:204:7]
wire [19:0] io_brinfo_uop_imm_packed_0; // @[execution-unit.scala:204:7]
wire [11:0] io_brinfo_uop_csr_addr_0; // @[execution-unit.scala:204:7]
wire [4:0] io_brinfo_uop_rob_idx_0; // @[execution-unit.scala:204:7]
wire [2:0] io_brinfo_uop_ldq_idx_0; // @[execution-unit.scala:204:7]
wire [2:0] io_brinfo_uop_stq_idx_0; // @[execution-unit.scala:204:7]
wire [1:0] io_brinfo_uop_rxq_idx_0; // @[execution-unit.scala:204:7]
wire [5:0] io_brinfo_uop_pdst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_brinfo_uop_prs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_brinfo_uop_prs2_0; // @[execution-unit.scala:204:7]
wire [5:0] io_brinfo_uop_prs3_0; // @[execution-unit.scala:204:7]
wire [3:0] io_brinfo_uop_ppred_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_prs1_busy_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_prs2_busy_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_prs3_busy_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_ppred_busy_0; // @[execution-unit.scala:204:7]
wire [5:0] io_brinfo_uop_stale_pdst_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_exception_0; // @[execution-unit.scala:204:7]
wire [63:0] io_brinfo_uop_exc_cause_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_bypassable_0; // @[execution-unit.scala:204:7]
wire [4:0] io_brinfo_uop_mem_cmd_0; // @[execution-unit.scala:204:7]
wire [1:0] io_brinfo_uop_mem_size_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_mem_signed_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_is_fence_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_is_fencei_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_is_amo_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_uses_ldq_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_uses_stq_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_is_sys_pc2epc_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_is_unique_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_flush_on_commit_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_ldst_is_rs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_brinfo_uop_ldst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_brinfo_uop_lrs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_brinfo_uop_lrs2_0; // @[execution-unit.scala:204:7]
wire [5:0] io_brinfo_uop_lrs3_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_ldst_val_0; // @[execution-unit.scala:204:7]
wire [1:0] io_brinfo_uop_dst_rtype_0; // @[execution-unit.scala:204:7]
wire [1:0] io_brinfo_uop_lrs1_rtype_0; // @[execution-unit.scala:204:7]
wire [1:0] io_brinfo_uop_lrs2_rtype_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_frs3_en_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_fp_val_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_fp_single_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_xcpt_pf_if_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_xcpt_ae_if_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_xcpt_ma_if_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_bp_debug_if_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_bp_xcpt_if_0; // @[execution-unit.scala:204:7]
wire [1:0] io_brinfo_uop_debug_fsrc_0; // @[execution-unit.scala:204:7]
wire [1:0] io_brinfo_uop_debug_tsrc_0; // @[execution-unit.scala:204:7]
wire io_brinfo_valid_0; // @[execution-unit.scala:204:7]
wire io_brinfo_mispredict_0; // @[execution-unit.scala:204:7]
wire io_brinfo_taken_0; // @[execution-unit.scala:204:7]
wire [2:0] io_brinfo_cfi_type_0; // @[execution-unit.scala:204:7]
wire [1:0] io_brinfo_pc_sel_0; // @[execution-unit.scala:204:7]
wire [39:0] io_brinfo_jalr_target_0; // @[execution-unit.scala:204:7]
wire [20:0] io_brinfo_target_offset_0; // @[execution-unit.scala:204:7]
wire [9:0] io_fu_types_0; // @[execution-unit.scala:204:7]
wire _div_busy_T_4; // @[execution-unit.scala:379:39]
wire div_busy; // @[execution-unit.scala:253:27]
wire _ifpu_busy_T; // @[execution-unit.scala:358:18]
wire ifpu_busy; // @[execution-unit.scala:254:27]
wire _io_fu_types_T_3 = ~div_busy; // @[execution-unit.scala:253:27, :262:22]
wire _io_fu_types_T_4 = _io_fu_types_T_3; // @[execution-unit.scala:262:{22,32}]
wire [9:0] _io_fu_types_T_5 = {5'h0, _io_fu_types_T_4, 4'h0}; // @[execution-unit.scala:262:{21,32}]
wire [9:0] _io_fu_types_T_6 = _io_fu_types_T_5 | 10'h9; // @[execution-unit.scala:261:45, :262:21]
wire [9:0] _io_fu_types_T_8 = _io_fu_types_T_6 | 10'h20; // @[execution-unit.scala:261:45, :262:58]
wire [9:0] _io_fu_types_T_10 = _io_fu_types_T_8 | 10'h2; // @[execution-unit.scala:262:58, :263:45]
wire _io_fu_types_T_11 = ~ifpu_busy; // @[execution-unit.scala:254:27, :265:22]
wire _io_fu_types_T_12 = _io_fu_types_T_11; // @[execution-unit.scala:265:{22,33}]
wire [9:0] _io_fu_types_T_13 = {1'h0, _io_fu_types_T_12, 8'h0}; // @[execution-unit.scala:265:{21,33}]
wire [9:0] _io_fu_types_T_14 = _io_fu_types_T_10 | _io_fu_types_T_13; // @[execution-unit.scala:263:45, :264:49, :265:21]
assign _io_fu_types_T_16 = _io_fu_types_T_14; // @[execution-unit.scala:264:49, :265:60]
assign io_fu_types_0 = _io_fu_types_T_16; // @[execution-unit.scala:204:7, :265:60]
assign io_bypass_0_bits_data_0 = {1'h0, _ALUUnit_io_bypass_0_bits_data}; // @[execution-unit.scala:204:7, :271:17, :293:15]
assign io_bypass_1_bits_data_0 = {1'h0, _ALUUnit_io_bypass_1_bits_data}; // @[execution-unit.scala:204:7, :271:17, :293:15]
assign io_bypass_2_bits_data_0 = {1'h0, _ALUUnit_io_bypass_2_bits_data}; // @[execution-unit.scala:204:7, :271:17, :293:15]
assign _ifpu_busy_T = ~_queue_io_empty; // @[execution-unit.scala:347:23, :358:18]
assign ifpu_busy = _ifpu_busy_T; // @[execution-unit.scala:254:27, :358:18]
wire div_resp_val; // @[execution-unit.scala:364:30]
wire [9:0] _div_busy_T_1 = io_req_bits_uop_fu_code_0 & 10'h10; // @[execution-unit.scala:204:7]
wire _io_iresp_valid_T = _ALUUnit_io_resp_valid | _PipelinedMulUnit_io_resp_valid; // @[execution-unit.scala:271:17, :326:18, :376:72, :409:71]
wire _div_busy_T = ~_DivUnit_io_req_ready; // @[execution-unit.scala:366:17, :379:21]
wire _div_busy_T_2 = |_div_busy_T_1; // @[micro-op.scala:154:{40,47}]
wire _div_busy_T_3 = io_req_valid_0 & _div_busy_T_2; // @[execution-unit.scala:204:7, :380:35]
assign _div_busy_T_4 = _div_busy_T | _div_busy_T_3; // @[execution-unit.scala:379:{21,39}, :380:35]
assign div_busy = _div_busy_T_4; // @[execution-unit.scala:253:27, :379:39]
assign _io_iresp_valid_T_1 = _io_iresp_valid_T | _DivUnit_io_resp_valid; // @[execution-unit.scala:366:17, :409:71]
assign io_iresp_valid_0 = _io_iresp_valid_T_1; // @[execution-unit.scala:204:7, :409:71]
wire [6:0] _io_iresp_bits_uop_T_uopc = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_uopc : _DivUnit_io_resp_bits_uop_uopc; // @[Mux.scala:50:70]
wire [31:0] _io_iresp_bits_uop_T_inst = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_inst : _DivUnit_io_resp_bits_uop_inst; // @[Mux.scala:50:70]
wire [31:0] _io_iresp_bits_uop_T_debug_inst = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_debug_inst : _DivUnit_io_resp_bits_uop_debug_inst; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_is_rvc = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_is_rvc : _DivUnit_io_resp_bits_uop_is_rvc; // @[Mux.scala:50:70]
wire [39:0] _io_iresp_bits_uop_T_debug_pc = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_debug_pc : _DivUnit_io_resp_bits_uop_debug_pc; // @[Mux.scala:50:70]
wire [2:0] _io_iresp_bits_uop_T_iq_type = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_iq_type : _DivUnit_io_resp_bits_uop_iq_type; // @[Mux.scala:50:70]
wire [9:0] _io_iresp_bits_uop_T_fu_code = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_fu_code : _DivUnit_io_resp_bits_uop_fu_code; // @[Mux.scala:50:70]
wire [3:0] _io_iresp_bits_uop_T_ctrl_br_type = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_ctrl_br_type : _DivUnit_io_resp_bits_uop_ctrl_br_type; // @[Mux.scala:50:70]
wire [1:0] _io_iresp_bits_uop_T_ctrl_op1_sel = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_ctrl_op1_sel : _DivUnit_io_resp_bits_uop_ctrl_op1_sel; // @[Mux.scala:50:70]
wire [2:0] _io_iresp_bits_uop_T_ctrl_op2_sel = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_ctrl_op2_sel : _DivUnit_io_resp_bits_uop_ctrl_op2_sel; // @[Mux.scala:50:70]
wire [2:0] _io_iresp_bits_uop_T_ctrl_imm_sel = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_ctrl_imm_sel : _DivUnit_io_resp_bits_uop_ctrl_imm_sel; // @[Mux.scala:50:70]
wire [4:0] _io_iresp_bits_uop_T_ctrl_op_fcn = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_ctrl_op_fcn : _DivUnit_io_resp_bits_uop_ctrl_op_fcn; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_ctrl_fcn_dw = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_ctrl_fcn_dw : _DivUnit_io_resp_bits_uop_ctrl_fcn_dw; // @[Mux.scala:50:70]
wire [2:0] _io_iresp_bits_uop_T_ctrl_csr_cmd = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_ctrl_csr_cmd : _DivUnit_io_resp_bits_uop_ctrl_csr_cmd; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_ctrl_is_load = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_ctrl_is_load : _DivUnit_io_resp_bits_uop_ctrl_is_load; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_ctrl_is_sta = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_ctrl_is_sta : _DivUnit_io_resp_bits_uop_ctrl_is_sta; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_ctrl_is_std = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_ctrl_is_std : _DivUnit_io_resp_bits_uop_ctrl_is_std; // @[Mux.scala:50:70]
wire [1:0] _io_iresp_bits_uop_T_iw_state = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_iw_state : _DivUnit_io_resp_bits_uop_iw_state; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_iw_p1_poisoned = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_iw_p1_poisoned : _DivUnit_io_resp_bits_uop_iw_p1_poisoned; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_iw_p2_poisoned = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_iw_p2_poisoned : _DivUnit_io_resp_bits_uop_iw_p2_poisoned; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_is_br = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_is_br : _DivUnit_io_resp_bits_uop_is_br; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_is_jalr = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_is_jalr : _DivUnit_io_resp_bits_uop_is_jalr; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_is_jal = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_is_jal : _DivUnit_io_resp_bits_uop_is_jal; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_is_sfb = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_is_sfb : _DivUnit_io_resp_bits_uop_is_sfb; // @[Mux.scala:50:70]
wire [7:0] _io_iresp_bits_uop_T_br_mask = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_br_mask : _DivUnit_io_resp_bits_uop_br_mask; // @[Mux.scala:50:70]
wire [2:0] _io_iresp_bits_uop_T_br_tag = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_br_tag : _DivUnit_io_resp_bits_uop_br_tag; // @[Mux.scala:50:70]
wire [3:0] _io_iresp_bits_uop_T_ftq_idx = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_ftq_idx : _DivUnit_io_resp_bits_uop_ftq_idx; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_edge_inst = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_edge_inst : _DivUnit_io_resp_bits_uop_edge_inst; // @[Mux.scala:50:70]
wire [5:0] _io_iresp_bits_uop_T_pc_lob = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_pc_lob : _DivUnit_io_resp_bits_uop_pc_lob; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_taken = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_taken : _DivUnit_io_resp_bits_uop_taken; // @[Mux.scala:50:70]
wire [19:0] _io_iresp_bits_uop_T_imm_packed = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_imm_packed : _DivUnit_io_resp_bits_uop_imm_packed; // @[Mux.scala:50:70]
wire [11:0] _io_iresp_bits_uop_T_csr_addr = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_csr_addr : _DivUnit_io_resp_bits_uop_csr_addr; // @[Mux.scala:50:70]
wire [4:0] _io_iresp_bits_uop_T_rob_idx = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_rob_idx : _DivUnit_io_resp_bits_uop_rob_idx; // @[Mux.scala:50:70]
wire [2:0] _io_iresp_bits_uop_T_ldq_idx = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_ldq_idx : _DivUnit_io_resp_bits_uop_ldq_idx; // @[Mux.scala:50:70]
wire [2:0] _io_iresp_bits_uop_T_stq_idx = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_stq_idx : _DivUnit_io_resp_bits_uop_stq_idx; // @[Mux.scala:50:70]
wire [1:0] _io_iresp_bits_uop_T_rxq_idx = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_rxq_idx : _DivUnit_io_resp_bits_uop_rxq_idx; // @[Mux.scala:50:70]
wire [5:0] _io_iresp_bits_uop_T_pdst = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_pdst : _DivUnit_io_resp_bits_uop_pdst; // @[Mux.scala:50:70]
wire [5:0] _io_iresp_bits_uop_T_prs1 = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_prs1 : _DivUnit_io_resp_bits_uop_prs1; // @[Mux.scala:50:70]
wire [5:0] _io_iresp_bits_uop_T_prs2 = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_prs2 : _DivUnit_io_resp_bits_uop_prs2; // @[Mux.scala:50:70]
wire [5:0] _io_iresp_bits_uop_T_prs3 = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_prs3 : _DivUnit_io_resp_bits_uop_prs3; // @[Mux.scala:50:70]
wire [3:0] _io_iresp_bits_uop_T_ppred = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_ppred : _DivUnit_io_resp_bits_uop_ppred; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_prs1_busy = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_prs1_busy : _DivUnit_io_resp_bits_uop_prs1_busy; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_prs2_busy = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_prs2_busy : _DivUnit_io_resp_bits_uop_prs2_busy; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_prs3_busy = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_prs3_busy : _DivUnit_io_resp_bits_uop_prs3_busy; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_ppred_busy = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_ppred_busy : _DivUnit_io_resp_bits_uop_ppred_busy; // @[Mux.scala:50:70]
wire [5:0] _io_iresp_bits_uop_T_stale_pdst = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_stale_pdst : _DivUnit_io_resp_bits_uop_stale_pdst; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_exception = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_exception : _DivUnit_io_resp_bits_uop_exception; // @[Mux.scala:50:70]
wire [63:0] _io_iresp_bits_uop_T_exc_cause = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_exc_cause : _DivUnit_io_resp_bits_uop_exc_cause; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_bypassable = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_bypassable : _DivUnit_io_resp_bits_uop_bypassable; // @[Mux.scala:50:70]
wire [4:0] _io_iresp_bits_uop_T_mem_cmd = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_mem_cmd : _DivUnit_io_resp_bits_uop_mem_cmd; // @[Mux.scala:50:70]
wire [1:0] _io_iresp_bits_uop_T_mem_size = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_mem_size : _DivUnit_io_resp_bits_uop_mem_size; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_mem_signed = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_mem_signed : _DivUnit_io_resp_bits_uop_mem_signed; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_is_fence = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_is_fence : _DivUnit_io_resp_bits_uop_is_fence; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_is_fencei = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_is_fencei : _DivUnit_io_resp_bits_uop_is_fencei; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_is_amo = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_is_amo : _DivUnit_io_resp_bits_uop_is_amo; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_uses_ldq = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_uses_ldq : _DivUnit_io_resp_bits_uop_uses_ldq; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_uses_stq = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_uses_stq : _DivUnit_io_resp_bits_uop_uses_stq; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_is_sys_pc2epc = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_is_sys_pc2epc : _DivUnit_io_resp_bits_uop_is_sys_pc2epc; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_is_unique = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_is_unique : _DivUnit_io_resp_bits_uop_is_unique; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_flush_on_commit = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_flush_on_commit : _DivUnit_io_resp_bits_uop_flush_on_commit; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_ldst_is_rs1 = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_ldst_is_rs1 : _DivUnit_io_resp_bits_uop_ldst_is_rs1; // @[Mux.scala:50:70]
wire [5:0] _io_iresp_bits_uop_T_ldst = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_ldst : _DivUnit_io_resp_bits_uop_ldst; // @[Mux.scala:50:70]
wire [5:0] _io_iresp_bits_uop_T_lrs1 = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_lrs1 : _DivUnit_io_resp_bits_uop_lrs1; // @[Mux.scala:50:70]
wire [5:0] _io_iresp_bits_uop_T_lrs2 = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_lrs2 : _DivUnit_io_resp_bits_uop_lrs2; // @[Mux.scala:50:70]
wire [5:0] _io_iresp_bits_uop_T_lrs3 = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_lrs3 : _DivUnit_io_resp_bits_uop_lrs3; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_ldst_val = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_ldst_val : _DivUnit_io_resp_bits_uop_ldst_val; // @[Mux.scala:50:70]
wire [1:0] _io_iresp_bits_uop_T_dst_rtype = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_dst_rtype : _DivUnit_io_resp_bits_uop_dst_rtype; // @[Mux.scala:50:70]
wire [1:0] _io_iresp_bits_uop_T_lrs1_rtype = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_lrs1_rtype : _DivUnit_io_resp_bits_uop_lrs1_rtype; // @[Mux.scala:50:70]
wire [1:0] _io_iresp_bits_uop_T_lrs2_rtype = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_lrs2_rtype : _DivUnit_io_resp_bits_uop_lrs2_rtype; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_frs3_en = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_frs3_en : _DivUnit_io_resp_bits_uop_frs3_en; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_fp_val = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_fp_val : _DivUnit_io_resp_bits_uop_fp_val; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_fp_single = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_fp_single : _DivUnit_io_resp_bits_uop_fp_single; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_xcpt_pf_if = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_xcpt_pf_if : _DivUnit_io_resp_bits_uop_xcpt_pf_if; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_xcpt_ae_if = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_xcpt_ae_if : _DivUnit_io_resp_bits_uop_xcpt_ae_if; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_xcpt_ma_if = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_xcpt_ma_if : _DivUnit_io_resp_bits_uop_xcpt_ma_if; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_bp_debug_if = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_bp_debug_if : _DivUnit_io_resp_bits_uop_bp_debug_if; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_bp_xcpt_if = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_bp_xcpt_if : _DivUnit_io_resp_bits_uop_bp_xcpt_if; // @[Mux.scala:50:70]
wire [1:0] _io_iresp_bits_uop_T_debug_fsrc = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_debug_fsrc : _DivUnit_io_resp_bits_uop_debug_fsrc; // @[Mux.scala:50:70]
wire [1:0] _io_iresp_bits_uop_T_debug_tsrc = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_debug_tsrc : _DivUnit_io_resp_bits_uop_debug_tsrc; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_uopc = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_uopc : _io_iresp_bits_uop_T_uopc; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_inst = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_inst : _io_iresp_bits_uop_T_inst; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_debug_inst = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_debug_inst : _io_iresp_bits_uop_T_debug_inst; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_is_rvc = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_rvc : _io_iresp_bits_uop_T_is_rvc; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_debug_pc = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_debug_pc : _io_iresp_bits_uop_T_debug_pc; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_iq_type = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_iq_type : _io_iresp_bits_uop_T_iq_type; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_fu_code = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_fu_code : _io_iresp_bits_uop_T_fu_code; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_ctrl_br_type = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_br_type : _io_iresp_bits_uop_T_ctrl_br_type; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_ctrl_op1_sel = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_op1_sel : _io_iresp_bits_uop_T_ctrl_op1_sel; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_ctrl_op2_sel = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_op2_sel : _io_iresp_bits_uop_T_ctrl_op2_sel; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_ctrl_imm_sel = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_imm_sel : _io_iresp_bits_uop_T_ctrl_imm_sel; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_ctrl_op_fcn = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_op_fcn : _io_iresp_bits_uop_T_ctrl_op_fcn; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_ctrl_fcn_dw = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_fcn_dw : _io_iresp_bits_uop_T_ctrl_fcn_dw; // @[Mux.scala:50:70]
wire [2:0] _io_iresp_bits_uop_T_1_ctrl_csr_cmd = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_csr_cmd : _io_iresp_bits_uop_T_ctrl_csr_cmd; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_ctrl_is_load = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_is_load : _io_iresp_bits_uop_T_ctrl_is_load; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_ctrl_is_sta = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_is_sta : _io_iresp_bits_uop_T_ctrl_is_sta; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_ctrl_is_std = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_is_std : _io_iresp_bits_uop_T_ctrl_is_std; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_iw_state = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_iw_state : _io_iresp_bits_uop_T_iw_state; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_iw_p1_poisoned = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_iw_p1_poisoned : _io_iresp_bits_uop_T_iw_p1_poisoned; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_iw_p2_poisoned = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_iw_p2_poisoned : _io_iresp_bits_uop_T_iw_p2_poisoned; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_is_br = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_br : _io_iresp_bits_uop_T_is_br; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_is_jalr = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_jalr : _io_iresp_bits_uop_T_is_jalr; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_is_jal = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_jal : _io_iresp_bits_uop_T_is_jal; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_is_sfb = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_sfb : _io_iresp_bits_uop_T_is_sfb; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_br_mask = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_br_mask : _io_iresp_bits_uop_T_br_mask; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_br_tag = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_br_tag : _io_iresp_bits_uop_T_br_tag; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_ftq_idx = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ftq_idx : _io_iresp_bits_uop_T_ftq_idx; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_edge_inst = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_edge_inst : _io_iresp_bits_uop_T_edge_inst; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_pc_lob = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_pc_lob : _io_iresp_bits_uop_T_pc_lob; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_taken = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_taken : _io_iresp_bits_uop_T_taken; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_imm_packed = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_imm_packed : _io_iresp_bits_uop_T_imm_packed; // @[Mux.scala:50:70]
wire [11:0] _io_iresp_bits_uop_T_1_csr_addr = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_csr_addr : _io_iresp_bits_uop_T_csr_addr; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_rob_idx = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_rob_idx : _io_iresp_bits_uop_T_rob_idx; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_ldq_idx = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ldq_idx : _io_iresp_bits_uop_T_ldq_idx; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_stq_idx = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_stq_idx : _io_iresp_bits_uop_T_stq_idx; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_rxq_idx = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_rxq_idx : _io_iresp_bits_uop_T_rxq_idx; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_pdst = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_pdst : _io_iresp_bits_uop_T_pdst; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_prs1 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_prs1 : _io_iresp_bits_uop_T_prs1; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_prs2 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_prs2 : _io_iresp_bits_uop_T_prs2; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_prs3 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_prs3 : _io_iresp_bits_uop_T_prs3; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_ppred = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ppred : _io_iresp_bits_uop_T_ppred; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_prs1_busy = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_prs1_busy : _io_iresp_bits_uop_T_prs1_busy; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_prs2_busy = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_prs2_busy : _io_iresp_bits_uop_T_prs2_busy; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_prs3_busy = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_prs3_busy : _io_iresp_bits_uop_T_prs3_busy; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_ppred_busy = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ppred_busy : _io_iresp_bits_uop_T_ppred_busy; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_stale_pdst = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_stale_pdst : _io_iresp_bits_uop_T_stale_pdst; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_exception = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_exception : _io_iresp_bits_uop_T_exception; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_exc_cause = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_exc_cause : _io_iresp_bits_uop_T_exc_cause; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_bypassable = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_bypassable : _io_iresp_bits_uop_T_bypassable; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_mem_cmd = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_mem_cmd : _io_iresp_bits_uop_T_mem_cmd; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_mem_size = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_mem_size : _io_iresp_bits_uop_T_mem_size; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_mem_signed = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_mem_signed : _io_iresp_bits_uop_T_mem_signed; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_is_fence = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_fence : _io_iresp_bits_uop_T_is_fence; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_is_fencei = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_fencei : _io_iresp_bits_uop_T_is_fencei; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_is_amo = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_amo : _io_iresp_bits_uop_T_is_amo; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_uses_ldq = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_uses_ldq : _io_iresp_bits_uop_T_uses_ldq; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_uses_stq = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_uses_stq : _io_iresp_bits_uop_T_uses_stq; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_is_sys_pc2epc = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_sys_pc2epc : _io_iresp_bits_uop_T_is_sys_pc2epc; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_is_unique = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_unique : _io_iresp_bits_uop_T_is_unique; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_flush_on_commit = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_flush_on_commit : _io_iresp_bits_uop_T_flush_on_commit; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_ldst_is_rs1 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ldst_is_rs1 : _io_iresp_bits_uop_T_ldst_is_rs1; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_ldst = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ldst : _io_iresp_bits_uop_T_ldst; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_lrs1 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_lrs1 : _io_iresp_bits_uop_T_lrs1; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_lrs2 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_lrs2 : _io_iresp_bits_uop_T_lrs2; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_lrs3 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_lrs3 : _io_iresp_bits_uop_T_lrs3; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_ldst_val = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ldst_val : _io_iresp_bits_uop_T_ldst_val; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_dst_rtype = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_dst_rtype : _io_iresp_bits_uop_T_dst_rtype; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_lrs1_rtype = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_lrs1_rtype : _io_iresp_bits_uop_T_lrs1_rtype; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_lrs2_rtype = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_lrs2_rtype : _io_iresp_bits_uop_T_lrs2_rtype; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_frs3_en = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_frs3_en : _io_iresp_bits_uop_T_frs3_en; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_fp_val = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_fp_val : _io_iresp_bits_uop_T_fp_val; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_fp_single = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_fp_single : _io_iresp_bits_uop_T_fp_single; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_xcpt_pf_if = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_xcpt_pf_if : _io_iresp_bits_uop_T_xcpt_pf_if; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_xcpt_ae_if = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_xcpt_ae_if : _io_iresp_bits_uop_T_xcpt_ae_if; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_xcpt_ma_if = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_xcpt_ma_if : _io_iresp_bits_uop_T_xcpt_ma_if; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_bp_debug_if = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_bp_debug_if : _io_iresp_bits_uop_T_bp_debug_if; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_bp_xcpt_if = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_bp_xcpt_if : _io_iresp_bits_uop_T_bp_xcpt_if; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_debug_fsrc = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_debug_fsrc : _io_iresp_bits_uop_T_debug_fsrc; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_1_debug_tsrc = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_debug_tsrc : _io_iresp_bits_uop_T_debug_tsrc; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_uopc_0 = _io_iresp_bits_uop_T_1_uopc; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_inst_0 = _io_iresp_bits_uop_T_1_inst; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_debug_inst_0 = _io_iresp_bits_uop_T_1_debug_inst; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_is_rvc_0 = _io_iresp_bits_uop_T_1_is_rvc; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_debug_pc_0 = _io_iresp_bits_uop_T_1_debug_pc; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_iq_type_0 = _io_iresp_bits_uop_T_1_iq_type; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_fu_code_0 = _io_iresp_bits_uop_T_1_fu_code; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ctrl_br_type_0 = _io_iresp_bits_uop_T_1_ctrl_br_type; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ctrl_op1_sel_0 = _io_iresp_bits_uop_T_1_ctrl_op1_sel; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ctrl_op2_sel_0 = _io_iresp_bits_uop_T_1_ctrl_op2_sel; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ctrl_imm_sel_0 = _io_iresp_bits_uop_T_1_ctrl_imm_sel; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ctrl_op_fcn_0 = _io_iresp_bits_uop_T_1_ctrl_op_fcn; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ctrl_fcn_dw_0 = _io_iresp_bits_uop_T_1_ctrl_fcn_dw; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ctrl_is_load_0 = _io_iresp_bits_uop_T_1_ctrl_is_load; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ctrl_is_sta_0 = _io_iresp_bits_uop_T_1_ctrl_is_sta; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ctrl_is_std_0 = _io_iresp_bits_uop_T_1_ctrl_is_std; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_iw_state_0 = _io_iresp_bits_uop_T_1_iw_state; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_iw_p1_poisoned_0 = _io_iresp_bits_uop_T_1_iw_p1_poisoned; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_iw_p2_poisoned_0 = _io_iresp_bits_uop_T_1_iw_p2_poisoned; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_is_br_0 = _io_iresp_bits_uop_T_1_is_br; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_is_jalr_0 = _io_iresp_bits_uop_T_1_is_jalr; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_is_jal_0 = _io_iresp_bits_uop_T_1_is_jal; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_is_sfb_0 = _io_iresp_bits_uop_T_1_is_sfb; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_br_mask_0 = _io_iresp_bits_uop_T_1_br_mask; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_br_tag_0 = _io_iresp_bits_uop_T_1_br_tag; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ftq_idx_0 = _io_iresp_bits_uop_T_1_ftq_idx; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_edge_inst_0 = _io_iresp_bits_uop_T_1_edge_inst; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_pc_lob_0 = _io_iresp_bits_uop_T_1_pc_lob; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_taken_0 = _io_iresp_bits_uop_T_1_taken; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_imm_packed_0 = _io_iresp_bits_uop_T_1_imm_packed; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_rob_idx_0 = _io_iresp_bits_uop_T_1_rob_idx; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ldq_idx_0 = _io_iresp_bits_uop_T_1_ldq_idx; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_stq_idx_0 = _io_iresp_bits_uop_T_1_stq_idx; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_rxq_idx_0 = _io_iresp_bits_uop_T_1_rxq_idx; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_pdst_0 = _io_iresp_bits_uop_T_1_pdst; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_prs1_0 = _io_iresp_bits_uop_T_1_prs1; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_prs2_0 = _io_iresp_bits_uop_T_1_prs2; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_prs3_0 = _io_iresp_bits_uop_T_1_prs3; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ppred_0 = _io_iresp_bits_uop_T_1_ppred; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_prs1_busy_0 = _io_iresp_bits_uop_T_1_prs1_busy; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_prs2_busy_0 = _io_iresp_bits_uop_T_1_prs2_busy; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_prs3_busy_0 = _io_iresp_bits_uop_T_1_prs3_busy; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ppred_busy_0 = _io_iresp_bits_uop_T_1_ppred_busy; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_stale_pdst_0 = _io_iresp_bits_uop_T_1_stale_pdst; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_exception_0 = _io_iresp_bits_uop_T_1_exception; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_exc_cause_0 = _io_iresp_bits_uop_T_1_exc_cause; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_bypassable_0 = _io_iresp_bits_uop_T_1_bypassable; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_mem_cmd_0 = _io_iresp_bits_uop_T_1_mem_cmd; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_mem_size_0 = _io_iresp_bits_uop_T_1_mem_size; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_mem_signed_0 = _io_iresp_bits_uop_T_1_mem_signed; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_is_fence_0 = _io_iresp_bits_uop_T_1_is_fence; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_is_fencei_0 = _io_iresp_bits_uop_T_1_is_fencei; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_is_amo_0 = _io_iresp_bits_uop_T_1_is_amo; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_uses_ldq_0 = _io_iresp_bits_uop_T_1_uses_ldq; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_uses_stq_0 = _io_iresp_bits_uop_T_1_uses_stq; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_is_sys_pc2epc_0 = _io_iresp_bits_uop_T_1_is_sys_pc2epc; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_is_unique_0 = _io_iresp_bits_uop_T_1_is_unique; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_flush_on_commit_0 = _io_iresp_bits_uop_T_1_flush_on_commit; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ldst_is_rs1_0 = _io_iresp_bits_uop_T_1_ldst_is_rs1; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ldst_0 = _io_iresp_bits_uop_T_1_ldst; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_lrs1_0 = _io_iresp_bits_uop_T_1_lrs1; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_lrs2_0 = _io_iresp_bits_uop_T_1_lrs2; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_lrs3_0 = _io_iresp_bits_uop_T_1_lrs3; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ldst_val_0 = _io_iresp_bits_uop_T_1_ldst_val; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_dst_rtype_0 = _io_iresp_bits_uop_T_1_dst_rtype; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_lrs1_rtype_0 = _io_iresp_bits_uop_T_1_lrs1_rtype; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_lrs2_rtype_0 = _io_iresp_bits_uop_T_1_lrs2_rtype; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_frs3_en_0 = _io_iresp_bits_uop_T_1_frs3_en; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_fp_val_0 = _io_iresp_bits_uop_T_1_fp_val; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_fp_single_0 = _io_iresp_bits_uop_T_1_fp_single; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_xcpt_pf_if_0 = _io_iresp_bits_uop_T_1_xcpt_pf_if; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_xcpt_ae_if_0 = _io_iresp_bits_uop_T_1_xcpt_ae_if; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_xcpt_ma_if_0 = _io_iresp_bits_uop_T_1_xcpt_ma_if; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_bp_debug_if_0 = _io_iresp_bits_uop_T_1_bp_debug_if; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_bp_xcpt_if_0 = _io_iresp_bits_uop_T_1_bp_xcpt_if; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_debug_fsrc_0 = _io_iresp_bits_uop_T_1_debug_fsrc; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_debug_tsrc_0 = _io_iresp_bits_uop_T_1_debug_tsrc; // @[Mux.scala:50:70]
wire [63:0] _io_iresp_bits_data_T = _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_data : _DivUnit_io_resp_bits_data; // @[Mux.scala:50:70]
wire [63:0] _io_iresp_bits_data_T_1 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_data : _io_iresp_bits_data_T; // @[Mux.scala:50:70]
assign io_iresp_bits_data_0 = {1'h0, _io_iresp_bits_data_T_1}; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_csr_addr_sign_T = _ALUUnit_io_resp_bits_uop_imm_packed[19]; // @[util.scala:273:18]
wire io_iresp_bits_uop_csr_addr_sign = _io_iresp_bits_uop_csr_addr_sign_T; // @[util.scala:273:{18,37}]
wire _io_iresp_bits_uop_csr_addr_i11_T_6 = io_iresp_bits_uop_csr_addr_sign; // @[util.scala:273:37, :277:21]
wire io_iresp_bits_uop_csr_addr_hi_hi_hi = io_iresp_bits_uop_csr_addr_sign; // @[util.scala:273:37, :282:15]
wire [10:0] _io_iresp_bits_uop_csr_addr_i30_20_T_1 = _ALUUnit_io_resp_bits_uop_imm_packed[18:8]; // @[util.scala:274:39]
wire [10:0] _io_iresp_bits_uop_csr_addr_i30_20_T_2 = _io_iresp_bits_uop_csr_addr_i30_20_T_1; // @[util.scala:274:{39,46}]
wire [10:0] io_iresp_bits_uop_csr_addr_i30_20 = {11{io_iresp_bits_uop_csr_addr_sign}}; // @[util.scala:273:37, :274:21]
wire [10:0] io_iresp_bits_uop_csr_addr_hi_hi_lo = io_iresp_bits_uop_csr_addr_i30_20; // @[util.scala:274:21, :282:15]
wire [7:0] _io_iresp_bits_uop_csr_addr_i19_12_T_3 = _ALUUnit_io_resp_bits_uop_imm_packed[7:0]; // @[util.scala:275:56]
wire [7:0] _io_iresp_bits_uop_csr_addr_i19_12_T_4 = _io_iresp_bits_uop_csr_addr_i19_12_T_3; // @[util.scala:275:{56,62}]
wire [7:0] io_iresp_bits_uop_csr_addr_i19_12 = {8{io_iresp_bits_uop_csr_addr_sign}}; // @[util.scala:273:37, :275:21]
wire [7:0] io_iresp_bits_uop_csr_addr_hi_lo_hi = io_iresp_bits_uop_csr_addr_i19_12; // @[util.scala:275:21, :282:15]
wire _io_iresp_bits_uop_csr_addr_i11_T_4 = _ALUUnit_io_resp_bits_uop_imm_packed[8]; // @[util.scala:277:56]
wire _io_iresp_bits_uop_csr_addr_i0_T_3 = _ALUUnit_io_resp_bits_uop_imm_packed[8]; // @[util.scala:277:56, :280:56]
wire _io_iresp_bits_uop_csr_addr_i11_T_5 = _io_iresp_bits_uop_csr_addr_i11_T_4; // @[util.scala:277:{56,60}]
wire io_iresp_bits_uop_csr_addr_i11 = _io_iresp_bits_uop_csr_addr_i11_T_6; // @[util.scala:276:21, :277:21]
wire io_iresp_bits_uop_csr_addr_hi_lo_lo = io_iresp_bits_uop_csr_addr_i11; // @[util.scala:276:21, :282:15]
wire [4:0] _io_iresp_bits_uop_csr_addr_i10_5_T_1 = _ALUUnit_io_resp_bits_uop_imm_packed[18:14]; // @[util.scala:278:44]
wire [4:0] _io_iresp_bits_uop_csr_addr_i10_5_T_2 = _io_iresp_bits_uop_csr_addr_i10_5_T_1; // @[util.scala:278:{44,52}]
wire [4:0] io_iresp_bits_uop_csr_addr_i10_5 = _io_iresp_bits_uop_csr_addr_i10_5_T_2; // @[util.scala:278:{21,52}]
wire [4:0] io_iresp_bits_uop_csr_addr_lo_hi_hi = io_iresp_bits_uop_csr_addr_i10_5; // @[util.scala:278:21, :282:15]
wire [4:0] _io_iresp_bits_uop_csr_addr_i4_1_T_1 = _ALUUnit_io_resp_bits_uop_imm_packed[13:9]; // @[util.scala:279:44]
wire [4:0] _io_iresp_bits_uop_csr_addr_i4_1_T_2 = _io_iresp_bits_uop_csr_addr_i4_1_T_1; // @[util.scala:279:{44,51}]
wire [4:0] io_iresp_bits_uop_csr_addr_i4_1 = _io_iresp_bits_uop_csr_addr_i4_1_T_2; // @[util.scala:279:{21,51}]
wire [4:0] io_iresp_bits_uop_csr_addr_lo_hi_lo = io_iresp_bits_uop_csr_addr_i4_1; // @[util.scala:279:21, :282:15]
wire _io_iresp_bits_uop_csr_addr_i0_T_4 = _io_iresp_bits_uop_csr_addr_i0_T_3; // @[util.scala:280:{56,60}]
wire io_iresp_bits_uop_csr_addr_i0 = _io_iresp_bits_uop_csr_addr_i0_T_4; // @[util.scala:280:{21,60}]
wire io_iresp_bits_uop_csr_addr_lo_lo = io_iresp_bits_uop_csr_addr_i0; // @[util.scala:280:21, :282:15]
wire [9:0] io_iresp_bits_uop_csr_addr_lo_hi = {io_iresp_bits_uop_csr_addr_lo_hi_hi, io_iresp_bits_uop_csr_addr_lo_hi_lo}; // @[util.scala:282:15]
wire [10:0] io_iresp_bits_uop_csr_addr_lo = {io_iresp_bits_uop_csr_addr_lo_hi, io_iresp_bits_uop_csr_addr_lo_lo}; // @[util.scala:282:15]
wire [8:0] io_iresp_bits_uop_csr_addr_hi_lo = {io_iresp_bits_uop_csr_addr_hi_lo_hi, io_iresp_bits_uop_csr_addr_hi_lo_lo}; // @[util.scala:282:15]
wire [11:0] io_iresp_bits_uop_csr_addr_hi_hi = {io_iresp_bits_uop_csr_addr_hi_hi_hi, io_iresp_bits_uop_csr_addr_hi_hi_lo}; // @[util.scala:282:15]
wire [20:0] io_iresp_bits_uop_csr_addr_hi = {io_iresp_bits_uop_csr_addr_hi_hi, io_iresp_bits_uop_csr_addr_hi_lo}; // @[util.scala:282:15]
wire [31:0] _io_iresp_bits_uop_csr_addr_T = {io_iresp_bits_uop_csr_addr_hi, io_iresp_bits_uop_csr_addr_lo}; // @[util.scala:282:15]
wire [31:0] _io_iresp_bits_uop_csr_addr_T_1 = _io_iresp_bits_uop_csr_addr_T; // @[util.scala:282:{15,60}]
wire [31:0] _io_iresp_bits_uop_csr_addr_T_2 = _io_iresp_bits_uop_csr_addr_T_1; // @[util.scala:282:60]
assign io_iresp_bits_uop_csr_addr_0 = _io_iresp_bits_uop_csr_addr_T_2[11:0]; // @[execution-unit.scala:204:7, :420:{34,83}] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_50 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<7>(0h4c))
node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<7>(0h4e))
node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h4a))
node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _source_ok_T_35 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _source_ok_T_36 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _source_ok_T_41 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _source_ok_T_42 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _source_ok_T_44 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _source_ok_T_46 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _source_ok_T_47 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _source_ok_T_48 = eq(io.in.a.bits.source, UInt<6>(0h22))
wire _source_ok_WIRE : UInt<1>[29]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_25
connect _source_ok_WIRE[6], _source_ok_T_26
connect _source_ok_WIRE[7], _source_ok_T_27
connect _source_ok_WIRE[8], _source_ok_T_28
connect _source_ok_WIRE[9], _source_ok_T_29
connect _source_ok_WIRE[10], _source_ok_T_30
connect _source_ok_WIRE[11], _source_ok_T_31
connect _source_ok_WIRE[12], _source_ok_T_32
connect _source_ok_WIRE[13], _source_ok_T_33
connect _source_ok_WIRE[14], _source_ok_T_34
connect _source_ok_WIRE[15], _source_ok_T_35
connect _source_ok_WIRE[16], _source_ok_T_36
connect _source_ok_WIRE[17], _source_ok_T_37
connect _source_ok_WIRE[18], _source_ok_T_38
connect _source_ok_WIRE[19], _source_ok_T_39
connect _source_ok_WIRE[20], _source_ok_T_40
connect _source_ok_WIRE[21], _source_ok_T_41
connect _source_ok_WIRE[22], _source_ok_T_42
connect _source_ok_WIRE[23], _source_ok_T_43
connect _source_ok_WIRE[24], _source_ok_T_44
connect _source_ok_WIRE[25], _source_ok_T_45
connect _source_ok_WIRE[26], _source_ok_T_46
connect _source_ok_WIRE[27], _source_ok_T_47
connect _source_ok_WIRE[28], _source_ok_T_48
node _source_ok_T_49 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[2])
node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[3])
node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[4])
node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[5])
node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE[6])
node _source_ok_T_55 = or(_source_ok_T_54, _source_ok_WIRE[7])
node _source_ok_T_56 = or(_source_ok_T_55, _source_ok_WIRE[8])
node _source_ok_T_57 = or(_source_ok_T_56, _source_ok_WIRE[9])
node _source_ok_T_58 = or(_source_ok_T_57, _source_ok_WIRE[10])
node _source_ok_T_59 = or(_source_ok_T_58, _source_ok_WIRE[11])
node _source_ok_T_60 = or(_source_ok_T_59, _source_ok_WIRE[12])
node _source_ok_T_61 = or(_source_ok_T_60, _source_ok_WIRE[13])
node _source_ok_T_62 = or(_source_ok_T_61, _source_ok_WIRE[14])
node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE[15])
node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE[16])
node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE[17])
node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE[18])
node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE[19])
node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE[20])
node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE[21])
node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE[22])
node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE[23])
node _source_ok_T_72 = or(_source_ok_T_71, _source_ok_WIRE[24])
node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE[25])
node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE[26])
node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE[27])
node source_ok = or(_source_ok_T_75, _source_ok_WIRE[28])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4))
node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3)
node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3)
node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit)
node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2)
node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T)
node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit)
node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2)
node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1)
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit)
node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2)
node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2)
node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit)
node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2)
node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit)
node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2)
node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4)
node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit)
node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2)
node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5)
node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit)
node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2)
node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6)
node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit)
node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2)
node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_eq_8 = and(mask_sub_4_2, mask_nbit)
node _mask_acc_T_8 = and(mask_size, mask_eq_8)
node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8)
node mask_eq_9 = and(mask_sub_4_2, mask_bit)
node _mask_acc_T_9 = and(mask_size, mask_eq_9)
node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9)
node mask_eq_10 = and(mask_sub_5_2, mask_nbit)
node _mask_acc_T_10 = and(mask_size, mask_eq_10)
node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10)
node mask_eq_11 = and(mask_sub_5_2, mask_bit)
node _mask_acc_T_11 = and(mask_size, mask_eq_11)
node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11)
node mask_eq_12 = and(mask_sub_6_2, mask_nbit)
node _mask_acc_T_12 = and(mask_size, mask_eq_12)
node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12)
node mask_eq_13 = and(mask_sub_6_2, mask_bit)
node _mask_acc_T_13 = and(mask_size, mask_eq_13)
node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13)
node mask_eq_14 = and(mask_sub_7_2, mask_nbit)
node _mask_acc_T_14 = and(mask_size, mask_eq_14)
node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14)
node mask_eq_15 = and(mask_sub_7_2, mask_bit)
node _mask_acc_T_15 = and(mask_size, mask_eq_15)
node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15)
node mask_lo_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo)
node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8)
node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10)
node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo)
node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12)
node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14)
node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = eq(io.in.a.bits.source, UInt<7>(0h4c))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_67 = cvt(_T_66)
node _T_68 = and(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = asSInt(_T_68)
node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0)))
node _T_71 = or(_T_65, _T_70)
node _T_72 = eq(io.in.a.bits.source, UInt<7>(0h4e))
node _T_73 = eq(_T_72, UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<1>(0h0)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = or(_T_73, _T_78)
node _T_80 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_81 = eq(_T_80, UInt<1>(0h0))
node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_83 = cvt(_T_82)
node _T_84 = and(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = asSInt(_T_84)
node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = or(_T_81, _T_86)
node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h4a))
node _T_89 = eq(_T_88, UInt<1>(0h0))
node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<1>(0h0)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_89, _T_94)
node _T_96 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_99 = cvt(_T_98)
node _T_100 = and(_T_99, asSInt(UInt<1>(0h0)))
node _T_101 = asSInt(_T_100)
node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0)))
node _T_103 = or(_T_97, _T_102)
node _T_104 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_105 = eq(_T_104, UInt<1>(0h0))
node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_107 = cvt(_T_106)
node _T_108 = and(_T_107, asSInt(UInt<1>(0h0)))
node _T_109 = asSInt(_T_108)
node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = or(_T_105, _T_110)
node _T_112 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_113 = eq(_T_112, UInt<1>(0h0))
node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_115 = cvt(_T_114)
node _T_116 = and(_T_115, asSInt(UInt<1>(0h0)))
node _T_117 = asSInt(_T_116)
node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0)))
node _T_119 = or(_T_113, _T_118)
node _T_120 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_123 = cvt(_T_122)
node _T_124 = and(_T_123, asSInt(UInt<1>(0h0)))
node _T_125 = asSInt(_T_124)
node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0)))
node _T_127 = or(_T_121, _T_126)
node _T_128 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_129 = eq(_T_128, UInt<1>(0h0))
node _T_130 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_131 = cvt(_T_130)
node _T_132 = and(_T_131, asSInt(UInt<1>(0h0)))
node _T_133 = asSInt(_T_132)
node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0)))
node _T_135 = or(_T_129, _T_134)
node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_137 = eq(_T_136, UInt<1>(0h0))
node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_139 = cvt(_T_138)
node _T_140 = and(_T_139, asSInt(UInt<1>(0h0)))
node _T_141 = asSInt(_T_140)
node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0)))
node _T_143 = or(_T_137, _T_142)
node _T_144 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_145 = eq(_T_144, UInt<1>(0h0))
node _T_146 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_147 = cvt(_T_146)
node _T_148 = and(_T_147, asSInt(UInt<1>(0h0)))
node _T_149 = asSInt(_T_148)
node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0)))
node _T_151 = or(_T_145, _T_150)
node _T_152 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_155 = cvt(_T_154)
node _T_156 = and(_T_155, asSInt(UInt<1>(0h0)))
node _T_157 = asSInt(_T_156)
node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0)))
node _T_159 = or(_T_153, _T_158)
node _T_160 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_161 = eq(_T_160, UInt<1>(0h0))
node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_163 = cvt(_T_162)
node _T_164 = and(_T_163, asSInt(UInt<1>(0h0)))
node _T_165 = asSInt(_T_164)
node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0)))
node _T_167 = or(_T_161, _T_166)
node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_169 = eq(_T_168, UInt<1>(0h0))
node _T_170 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_171 = cvt(_T_170)
node _T_172 = and(_T_171, asSInt(UInt<1>(0h0)))
node _T_173 = asSInt(_T_172)
node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0)))
node _T_175 = or(_T_169, _T_174)
node _T_176 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_177 = eq(_T_176, UInt<1>(0h0))
node _T_178 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_179 = cvt(_T_178)
node _T_180 = and(_T_179, asSInt(UInt<1>(0h0)))
node _T_181 = asSInt(_T_180)
node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0)))
node _T_183 = or(_T_177, _T_182)
node _T_184 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_185 = eq(_T_184, UInt<1>(0h0))
node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_187 = cvt(_T_186)
node _T_188 = and(_T_187, asSInt(UInt<1>(0h0)))
node _T_189 = asSInt(_T_188)
node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0)))
node _T_191 = or(_T_185, _T_190)
node _T_192 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_193 = eq(_T_192, UInt<1>(0h0))
node _T_194 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_195 = cvt(_T_194)
node _T_196 = and(_T_195, asSInt(UInt<1>(0h0)))
node _T_197 = asSInt(_T_196)
node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0)))
node _T_199 = or(_T_193, _T_198)
node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_201 = eq(_T_200, UInt<1>(0h0))
node _T_202 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_203 = cvt(_T_202)
node _T_204 = and(_T_203, asSInt(UInt<1>(0h0)))
node _T_205 = asSInt(_T_204)
node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0)))
node _T_207 = or(_T_201, _T_206)
node _T_208 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_209 = eq(_T_208, UInt<1>(0h0))
node _T_210 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_211 = cvt(_T_210)
node _T_212 = and(_T_211, asSInt(UInt<1>(0h0)))
node _T_213 = asSInt(_T_212)
node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0)))
node _T_215 = or(_T_209, _T_214)
node _T_216 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_217 = eq(_T_216, UInt<1>(0h0))
node _T_218 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_219 = cvt(_T_218)
node _T_220 = and(_T_219, asSInt(UInt<1>(0h0)))
node _T_221 = asSInt(_T_220)
node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0)))
node _T_223 = or(_T_217, _T_222)
node _T_224 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_225 = eq(_T_224, UInt<1>(0h0))
node _T_226 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_227 = cvt(_T_226)
node _T_228 = and(_T_227, asSInt(UInt<1>(0h0)))
node _T_229 = asSInt(_T_228)
node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0)))
node _T_231 = or(_T_225, _T_230)
node _T_232 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_233 = eq(_T_232, UInt<1>(0h0))
node _T_234 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_235 = cvt(_T_234)
node _T_236 = and(_T_235, asSInt(UInt<1>(0h0)))
node _T_237 = asSInt(_T_236)
node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0)))
node _T_239 = or(_T_233, _T_238)
node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_243 = cvt(_T_242)
node _T_244 = and(_T_243, asSInt(UInt<1>(0h0)))
node _T_245 = asSInt(_T_244)
node _T_246 = eq(_T_245, asSInt(UInt<1>(0h0)))
node _T_247 = or(_T_241, _T_246)
node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_249 = eq(_T_248, UInt<1>(0h0))
node _T_250 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_251 = cvt(_T_250)
node _T_252 = and(_T_251, asSInt(UInt<1>(0h0)))
node _T_253 = asSInt(_T_252)
node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0)))
node _T_255 = or(_T_249, _T_254)
node _T_256 = and(_T_11, _T_24)
node _T_257 = and(_T_256, _T_37)
node _T_258 = and(_T_257, _T_50)
node _T_259 = and(_T_258, _T_63)
node _T_260 = and(_T_259, _T_71)
node _T_261 = and(_T_260, _T_79)
node _T_262 = and(_T_261, _T_87)
node _T_263 = and(_T_262, _T_95)
node _T_264 = and(_T_263, _T_103)
node _T_265 = and(_T_264, _T_111)
node _T_266 = and(_T_265, _T_119)
node _T_267 = and(_T_266, _T_127)
node _T_268 = and(_T_267, _T_135)
node _T_269 = and(_T_268, _T_143)
node _T_270 = and(_T_269, _T_151)
node _T_271 = and(_T_270, _T_159)
node _T_272 = and(_T_271, _T_167)
node _T_273 = and(_T_272, _T_175)
node _T_274 = and(_T_273, _T_183)
node _T_275 = and(_T_274, _T_191)
node _T_276 = and(_T_275, _T_199)
node _T_277 = and(_T_276, _T_207)
node _T_278 = and(_T_277, _T_215)
node _T_279 = and(_T_278, _T_223)
node _T_280 = and(_T_279, _T_231)
node _T_281 = and(_T_280, _T_239)
node _T_282 = and(_T_281, _T_247)
node _T_283 = and(_T_282, _T_255)
node _T_284 = asUInt(reset)
node _T_285 = eq(_T_284, UInt<1>(0h0))
when _T_285 :
node _T_286 = eq(_T_283, UInt<1>(0h0))
when _T_286 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_283, UInt<1>(0h1), "") : assert_1
node _T_287 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_287 :
node _T_288 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_289 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_290 = and(_T_288, _T_289)
node _T_291 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_292 = shr(io.in.a.bits.source, 2)
node _T_293 = eq(_T_292, UInt<1>(0h0))
node _T_294 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_295 = and(_T_293, _T_294)
node _T_296 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_297 = and(_T_295, _T_296)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_298 = shr(io.in.a.bits.source, 2)
node _T_299 = eq(_T_298, UInt<1>(0h1))
node _T_300 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_301 = and(_T_299, _T_300)
node _T_302 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_303 = and(_T_301, _T_302)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_304 = shr(io.in.a.bits.source, 2)
node _T_305 = eq(_T_304, UInt<2>(0h2))
node _T_306 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_307 = and(_T_305, _T_306)
node _T_308 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_309 = and(_T_307, _T_308)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_310 = shr(io.in.a.bits.source, 2)
node _T_311 = eq(_T_310, UInt<2>(0h3))
node _T_312 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_313 = and(_T_311, _T_312)
node _T_314 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_315 = and(_T_313, _T_314)
node _T_316 = eq(io.in.a.bits.source, UInt<7>(0h4c))
node _T_317 = eq(io.in.a.bits.source, UInt<7>(0h4e))
node _T_318 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_319 = eq(io.in.a.bits.source, UInt<7>(0h4a))
node _T_320 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_321 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_322 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_323 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_324 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_325 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_326 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_329 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_330 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_331 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_332 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_333 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_334 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_335 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_336 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_337 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_338 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_339 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_340 = or(_T_291, _T_297)
node _T_341 = or(_T_340, _T_303)
node _T_342 = or(_T_341, _T_309)
node _T_343 = or(_T_342, _T_315)
node _T_344 = or(_T_343, _T_316)
node _T_345 = or(_T_344, _T_317)
node _T_346 = or(_T_345, _T_318)
node _T_347 = or(_T_346, _T_319)
node _T_348 = or(_T_347, _T_320)
node _T_349 = or(_T_348, _T_321)
node _T_350 = or(_T_349, _T_322)
node _T_351 = or(_T_350, _T_323)
node _T_352 = or(_T_351, _T_324)
node _T_353 = or(_T_352, _T_325)
node _T_354 = or(_T_353, _T_326)
node _T_355 = or(_T_354, _T_327)
node _T_356 = or(_T_355, _T_328)
node _T_357 = or(_T_356, _T_329)
node _T_358 = or(_T_357, _T_330)
node _T_359 = or(_T_358, _T_331)
node _T_360 = or(_T_359, _T_332)
node _T_361 = or(_T_360, _T_333)
node _T_362 = or(_T_361, _T_334)
node _T_363 = or(_T_362, _T_335)
node _T_364 = or(_T_363, _T_336)
node _T_365 = or(_T_364, _T_337)
node _T_366 = or(_T_365, _T_338)
node _T_367 = or(_T_366, _T_339)
node _T_368 = and(_T_290, _T_367)
node _T_369 = or(UInt<1>(0h0), _T_368)
node _T_370 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_371 = or(UInt<1>(0h0), _T_370)
node _T_372 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_373 = cvt(_T_372)
node _T_374 = and(_T_373, asSInt(UInt<17>(0h100c0)))
node _T_375 = asSInt(_T_374)
node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0)))
node _T_377 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_378 = cvt(_T_377)
node _T_379 = and(_T_378, asSInt(UInt<29>(0h100000c0)))
node _T_380 = asSInt(_T_379)
node _T_381 = eq(_T_380, asSInt(UInt<1>(0h0)))
node _T_382 = or(_T_376, _T_381)
node _T_383 = and(_T_371, _T_382)
node _T_384 = or(UInt<1>(0h0), _T_383)
node _T_385 = and(_T_369, _T_384)
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_385, UInt<1>(0h1), "") : assert_2
node _T_389 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_390 = shr(io.in.a.bits.source, 2)
node _T_391 = eq(_T_390, UInt<1>(0h0))
node _T_392 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_393 = and(_T_391, _T_392)
node _T_394 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_395 = and(_T_393, _T_394)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_396 = shr(io.in.a.bits.source, 2)
node _T_397 = eq(_T_396, UInt<1>(0h1))
node _T_398 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_399 = and(_T_397, _T_398)
node _T_400 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_401 = and(_T_399, _T_400)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_402 = shr(io.in.a.bits.source, 2)
node _T_403 = eq(_T_402, UInt<2>(0h2))
node _T_404 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_405 = and(_T_403, _T_404)
node _T_406 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_407 = and(_T_405, _T_406)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_408 = shr(io.in.a.bits.source, 2)
node _T_409 = eq(_T_408, UInt<2>(0h3))
node _T_410 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_411 = and(_T_409, _T_410)
node _T_412 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_413 = and(_T_411, _T_412)
node _T_414 = eq(io.in.a.bits.source, UInt<7>(0h4c))
node _T_415 = eq(io.in.a.bits.source, UInt<7>(0h4e))
node _T_416 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_417 = eq(io.in.a.bits.source, UInt<7>(0h4a))
node _T_418 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_419 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_420 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_421 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_422 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_423 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_424 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_425 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_426 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_427 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_428 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_429 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_430 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_431 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_432 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_433 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_434 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_435 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_436 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_437 = eq(io.in.a.bits.source, UInt<6>(0h22))
wire _WIRE : UInt<1>[29]
connect _WIRE[0], _T_389
connect _WIRE[1], _T_395
connect _WIRE[2], _T_401
connect _WIRE[3], _T_407
connect _WIRE[4], _T_413
connect _WIRE[5], _T_414
connect _WIRE[6], _T_415
connect _WIRE[7], _T_416
connect _WIRE[8], _T_417
connect _WIRE[9], _T_418
connect _WIRE[10], _T_419
connect _WIRE[11], _T_420
connect _WIRE[12], _T_421
connect _WIRE[13], _T_422
connect _WIRE[14], _T_423
connect _WIRE[15], _T_424
connect _WIRE[16], _T_425
connect _WIRE[17], _T_426
connect _WIRE[18], _T_427
connect _WIRE[19], _T_428
connect _WIRE[20], _T_429
connect _WIRE[21], _T_430
connect _WIRE[22], _T_431
connect _WIRE[23], _T_432
connect _WIRE[24], _T_433
connect _WIRE[25], _T_434
connect _WIRE[26], _T_435
connect _WIRE[27], _T_436
connect _WIRE[28], _T_437
node _T_438 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_439 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_440 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_441 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_442 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_443 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_444 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_445 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_446 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_447 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_448 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_449 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_450 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_451 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_452 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_453 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_454 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_455 = mux(_WIRE[5], _T_438, UInt<1>(0h0))
node _T_456 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_457 = mux(_WIRE[7], _T_439, UInt<1>(0h0))
node _T_458 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_459 = mux(_WIRE[9], _T_440, UInt<1>(0h0))
node _T_460 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_461 = mux(_WIRE[11], _T_441, UInt<1>(0h0))
node _T_462 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0))
node _T_463 = mux(_WIRE[13], _T_442, UInt<1>(0h0))
node _T_464 = mux(_WIRE[14], UInt<1>(0h0), UInt<1>(0h0))
node _T_465 = mux(_WIRE[15], _T_443, UInt<1>(0h0))
node _T_466 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_467 = mux(_WIRE[17], _T_444, UInt<1>(0h0))
node _T_468 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0))
node _T_469 = mux(_WIRE[19], _T_445, UInt<1>(0h0))
node _T_470 = mux(_WIRE[20], UInt<1>(0h0), UInt<1>(0h0))
node _T_471 = mux(_WIRE[21], _T_446, UInt<1>(0h0))
node _T_472 = mux(_WIRE[22], UInt<1>(0h0), UInt<1>(0h0))
node _T_473 = mux(_WIRE[23], _T_447, UInt<1>(0h0))
node _T_474 = mux(_WIRE[24], UInt<1>(0h0), UInt<1>(0h0))
node _T_475 = mux(_WIRE[25], _T_448, UInt<1>(0h0))
node _T_476 = mux(_WIRE[26], UInt<1>(0h0), UInt<1>(0h0))
node _T_477 = mux(_WIRE[27], _T_449, UInt<1>(0h0))
node _T_478 = mux(_WIRE[28], UInt<1>(0h0), UInt<1>(0h0))
node _T_479 = or(_T_450, _T_451)
node _T_480 = or(_T_479, _T_452)
node _T_481 = or(_T_480, _T_453)
node _T_482 = or(_T_481, _T_454)
node _T_483 = or(_T_482, _T_455)
node _T_484 = or(_T_483, _T_456)
node _T_485 = or(_T_484, _T_457)
node _T_486 = or(_T_485, _T_458)
node _T_487 = or(_T_486, _T_459)
node _T_488 = or(_T_487, _T_460)
node _T_489 = or(_T_488, _T_461)
node _T_490 = or(_T_489, _T_462)
node _T_491 = or(_T_490, _T_463)
node _T_492 = or(_T_491, _T_464)
node _T_493 = or(_T_492, _T_465)
node _T_494 = or(_T_493, _T_466)
node _T_495 = or(_T_494, _T_467)
node _T_496 = or(_T_495, _T_468)
node _T_497 = or(_T_496, _T_469)
node _T_498 = or(_T_497, _T_470)
node _T_499 = or(_T_498, _T_471)
node _T_500 = or(_T_499, _T_472)
node _T_501 = or(_T_500, _T_473)
node _T_502 = or(_T_501, _T_474)
node _T_503 = or(_T_502, _T_475)
node _T_504 = or(_T_503, _T_476)
node _T_505 = or(_T_504, _T_477)
node _T_506 = or(_T_505, _T_478)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_506
node _T_507 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_508 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_509 = and(_T_507, _T_508)
node _T_510 = or(UInt<1>(0h0), _T_509)
node _T_511 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_512 = cvt(_T_511)
node _T_513 = and(_T_512, asSInt(UInt<17>(0h100c0)))
node _T_514 = asSInt(_T_513)
node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0)))
node _T_516 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_517 = cvt(_T_516)
node _T_518 = and(_T_517, asSInt(UInt<29>(0h100000c0)))
node _T_519 = asSInt(_T_518)
node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0)))
node _T_521 = or(_T_515, _T_520)
node _T_522 = and(_T_510, _T_521)
node _T_523 = or(UInt<1>(0h0), _T_522)
node _T_524 = and(_WIRE_1, _T_523)
node _T_525 = asUInt(reset)
node _T_526 = eq(_T_525, UInt<1>(0h0))
when _T_526 :
node _T_527 = eq(_T_524, UInt<1>(0h0))
when _T_527 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_524, UInt<1>(0h1), "") : assert_3
node _T_528 = asUInt(reset)
node _T_529 = eq(_T_528, UInt<1>(0h0))
when _T_529 :
node _T_530 = eq(source_ok, UInt<1>(0h0))
when _T_530 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_531 = geq(io.in.a.bits.size, UInt<3>(0h4))
node _T_532 = asUInt(reset)
node _T_533 = eq(_T_532, UInt<1>(0h0))
when _T_533 :
node _T_534 = eq(_T_531, UInt<1>(0h0))
when _T_534 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_531, UInt<1>(0h1), "") : assert_5
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(is_aligned, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_538 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_538, UInt<1>(0h1), "") : assert_7
node _T_542 = not(io.in.a.bits.mask)
node _T_543 = eq(_T_542, UInt<1>(0h0))
node _T_544 = asUInt(reset)
node _T_545 = eq(_T_544, UInt<1>(0h0))
when _T_545 :
node _T_546 = eq(_T_543, UInt<1>(0h0))
when _T_546 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_543, UInt<1>(0h1), "") : assert_8
node _T_547 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_548 = asUInt(reset)
node _T_549 = eq(_T_548, UInt<1>(0h0))
when _T_549 :
node _T_550 = eq(_T_547, UInt<1>(0h0))
when _T_550 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_547, UInt<1>(0h1), "") : assert_9
node _T_551 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_551 :
node _T_552 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_553 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_554 = and(_T_552, _T_553)
node _T_555 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_556 = shr(io.in.a.bits.source, 2)
node _T_557 = eq(_T_556, UInt<1>(0h0))
node _T_558 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_559 = and(_T_557, _T_558)
node _T_560 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_561 = and(_T_559, _T_560)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_562 = shr(io.in.a.bits.source, 2)
node _T_563 = eq(_T_562, UInt<1>(0h1))
node _T_564 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_565 = and(_T_563, _T_564)
node _T_566 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_567 = and(_T_565, _T_566)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_568 = shr(io.in.a.bits.source, 2)
node _T_569 = eq(_T_568, UInt<2>(0h2))
node _T_570 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_571 = and(_T_569, _T_570)
node _T_572 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_573 = and(_T_571, _T_572)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_574 = shr(io.in.a.bits.source, 2)
node _T_575 = eq(_T_574, UInt<2>(0h3))
node _T_576 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_577 = and(_T_575, _T_576)
node _T_578 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_579 = and(_T_577, _T_578)
node _T_580 = eq(io.in.a.bits.source, UInt<7>(0h4c))
node _T_581 = eq(io.in.a.bits.source, UInt<7>(0h4e))
node _T_582 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_583 = eq(io.in.a.bits.source, UInt<7>(0h4a))
node _T_584 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_585 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_586 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_587 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_588 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_589 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_590 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_591 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_592 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_593 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_594 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_595 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_596 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_597 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_598 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_599 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_600 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_601 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_602 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_603 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_604 = or(_T_555, _T_561)
node _T_605 = or(_T_604, _T_567)
node _T_606 = or(_T_605, _T_573)
node _T_607 = or(_T_606, _T_579)
node _T_608 = or(_T_607, _T_580)
node _T_609 = or(_T_608, _T_581)
node _T_610 = or(_T_609, _T_582)
node _T_611 = or(_T_610, _T_583)
node _T_612 = or(_T_611, _T_584)
node _T_613 = or(_T_612, _T_585)
node _T_614 = or(_T_613, _T_586)
node _T_615 = or(_T_614, _T_587)
node _T_616 = or(_T_615, _T_588)
node _T_617 = or(_T_616, _T_589)
node _T_618 = or(_T_617, _T_590)
node _T_619 = or(_T_618, _T_591)
node _T_620 = or(_T_619, _T_592)
node _T_621 = or(_T_620, _T_593)
node _T_622 = or(_T_621, _T_594)
node _T_623 = or(_T_622, _T_595)
node _T_624 = or(_T_623, _T_596)
node _T_625 = or(_T_624, _T_597)
node _T_626 = or(_T_625, _T_598)
node _T_627 = or(_T_626, _T_599)
node _T_628 = or(_T_627, _T_600)
node _T_629 = or(_T_628, _T_601)
node _T_630 = or(_T_629, _T_602)
node _T_631 = or(_T_630, _T_603)
node _T_632 = and(_T_554, _T_631)
node _T_633 = or(UInt<1>(0h0), _T_632)
node _T_634 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_635 = or(UInt<1>(0h0), _T_634)
node _T_636 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_637 = cvt(_T_636)
node _T_638 = and(_T_637, asSInt(UInt<17>(0h100c0)))
node _T_639 = asSInt(_T_638)
node _T_640 = eq(_T_639, asSInt(UInt<1>(0h0)))
node _T_641 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_642 = cvt(_T_641)
node _T_643 = and(_T_642, asSInt(UInt<29>(0h100000c0)))
node _T_644 = asSInt(_T_643)
node _T_645 = eq(_T_644, asSInt(UInt<1>(0h0)))
node _T_646 = or(_T_640, _T_645)
node _T_647 = and(_T_635, _T_646)
node _T_648 = or(UInt<1>(0h0), _T_647)
node _T_649 = and(_T_633, _T_648)
node _T_650 = asUInt(reset)
node _T_651 = eq(_T_650, UInt<1>(0h0))
when _T_651 :
node _T_652 = eq(_T_649, UInt<1>(0h0))
when _T_652 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_649, UInt<1>(0h1), "") : assert_10
node _T_653 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_654 = shr(io.in.a.bits.source, 2)
node _T_655 = eq(_T_654, UInt<1>(0h0))
node _T_656 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_657 = and(_T_655, _T_656)
node _T_658 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_659 = and(_T_657, _T_658)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_660 = shr(io.in.a.bits.source, 2)
node _T_661 = eq(_T_660, UInt<1>(0h1))
node _T_662 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_663 = and(_T_661, _T_662)
node _T_664 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_665 = and(_T_663, _T_664)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_666 = shr(io.in.a.bits.source, 2)
node _T_667 = eq(_T_666, UInt<2>(0h2))
node _T_668 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_669 = and(_T_667, _T_668)
node _T_670 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_671 = and(_T_669, _T_670)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_672 = shr(io.in.a.bits.source, 2)
node _T_673 = eq(_T_672, UInt<2>(0h3))
node _T_674 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_675 = and(_T_673, _T_674)
node _T_676 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_677 = and(_T_675, _T_676)
node _T_678 = eq(io.in.a.bits.source, UInt<7>(0h4c))
node _T_679 = eq(io.in.a.bits.source, UInt<7>(0h4e))
node _T_680 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_681 = eq(io.in.a.bits.source, UInt<7>(0h4a))
node _T_682 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_683 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_684 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_685 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_686 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_687 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_688 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_689 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_690 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_691 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_692 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_693 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_694 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_695 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_696 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_697 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_698 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_699 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_700 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_701 = eq(io.in.a.bits.source, UInt<6>(0h22))
wire _WIRE_2 : UInt<1>[29]
connect _WIRE_2[0], _T_653
connect _WIRE_2[1], _T_659
connect _WIRE_2[2], _T_665
connect _WIRE_2[3], _T_671
connect _WIRE_2[4], _T_677
connect _WIRE_2[5], _T_678
connect _WIRE_2[6], _T_679
connect _WIRE_2[7], _T_680
connect _WIRE_2[8], _T_681
connect _WIRE_2[9], _T_682
connect _WIRE_2[10], _T_683
connect _WIRE_2[11], _T_684
connect _WIRE_2[12], _T_685
connect _WIRE_2[13], _T_686
connect _WIRE_2[14], _T_687
connect _WIRE_2[15], _T_688
connect _WIRE_2[16], _T_689
connect _WIRE_2[17], _T_690
connect _WIRE_2[18], _T_691
connect _WIRE_2[19], _T_692
connect _WIRE_2[20], _T_693
connect _WIRE_2[21], _T_694
connect _WIRE_2[22], _T_695
connect _WIRE_2[23], _T_696
connect _WIRE_2[24], _T_697
connect _WIRE_2[25], _T_698
connect _WIRE_2[26], _T_699
connect _WIRE_2[27], _T_700
connect _WIRE_2[28], _T_701
node _T_702 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_703 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_704 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_705 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_706 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_707 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_708 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_709 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_710 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_711 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_712 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_713 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_714 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_715 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_716 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_717 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_718 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_719 = mux(_WIRE_2[5], _T_702, UInt<1>(0h0))
node _T_720 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_721 = mux(_WIRE_2[7], _T_703, UInt<1>(0h0))
node _T_722 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_723 = mux(_WIRE_2[9], _T_704, UInt<1>(0h0))
node _T_724 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_725 = mux(_WIRE_2[11], _T_705, UInt<1>(0h0))
node _T_726 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0))
node _T_727 = mux(_WIRE_2[13], _T_706, UInt<1>(0h0))
node _T_728 = mux(_WIRE_2[14], UInt<1>(0h0), UInt<1>(0h0))
node _T_729 = mux(_WIRE_2[15], _T_707, UInt<1>(0h0))
node _T_730 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_731 = mux(_WIRE_2[17], _T_708, UInt<1>(0h0))
node _T_732 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0))
node _T_733 = mux(_WIRE_2[19], _T_709, UInt<1>(0h0))
node _T_734 = mux(_WIRE_2[20], UInt<1>(0h0), UInt<1>(0h0))
node _T_735 = mux(_WIRE_2[21], _T_710, UInt<1>(0h0))
node _T_736 = mux(_WIRE_2[22], UInt<1>(0h0), UInt<1>(0h0))
node _T_737 = mux(_WIRE_2[23], _T_711, UInt<1>(0h0))
node _T_738 = mux(_WIRE_2[24], UInt<1>(0h0), UInt<1>(0h0))
node _T_739 = mux(_WIRE_2[25], _T_712, UInt<1>(0h0))
node _T_740 = mux(_WIRE_2[26], UInt<1>(0h0), UInt<1>(0h0))
node _T_741 = mux(_WIRE_2[27], _T_713, UInt<1>(0h0))
node _T_742 = mux(_WIRE_2[28], UInt<1>(0h0), UInt<1>(0h0))
node _T_743 = or(_T_714, _T_715)
node _T_744 = or(_T_743, _T_716)
node _T_745 = or(_T_744, _T_717)
node _T_746 = or(_T_745, _T_718)
node _T_747 = or(_T_746, _T_719)
node _T_748 = or(_T_747, _T_720)
node _T_749 = or(_T_748, _T_721)
node _T_750 = or(_T_749, _T_722)
node _T_751 = or(_T_750, _T_723)
node _T_752 = or(_T_751, _T_724)
node _T_753 = or(_T_752, _T_725)
node _T_754 = or(_T_753, _T_726)
node _T_755 = or(_T_754, _T_727)
node _T_756 = or(_T_755, _T_728)
node _T_757 = or(_T_756, _T_729)
node _T_758 = or(_T_757, _T_730)
node _T_759 = or(_T_758, _T_731)
node _T_760 = or(_T_759, _T_732)
node _T_761 = or(_T_760, _T_733)
node _T_762 = or(_T_761, _T_734)
node _T_763 = or(_T_762, _T_735)
node _T_764 = or(_T_763, _T_736)
node _T_765 = or(_T_764, _T_737)
node _T_766 = or(_T_765, _T_738)
node _T_767 = or(_T_766, _T_739)
node _T_768 = or(_T_767, _T_740)
node _T_769 = or(_T_768, _T_741)
node _T_770 = or(_T_769, _T_742)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_770
node _T_771 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_772 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_773 = and(_T_771, _T_772)
node _T_774 = or(UInt<1>(0h0), _T_773)
node _T_775 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_776 = cvt(_T_775)
node _T_777 = and(_T_776, asSInt(UInt<17>(0h100c0)))
node _T_778 = asSInt(_T_777)
node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0)))
node _T_780 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_781 = cvt(_T_780)
node _T_782 = and(_T_781, asSInt(UInt<29>(0h100000c0)))
node _T_783 = asSInt(_T_782)
node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0)))
node _T_785 = or(_T_779, _T_784)
node _T_786 = and(_T_774, _T_785)
node _T_787 = or(UInt<1>(0h0), _T_786)
node _T_788 = and(_WIRE_3, _T_787)
node _T_789 = asUInt(reset)
node _T_790 = eq(_T_789, UInt<1>(0h0))
when _T_790 :
node _T_791 = eq(_T_788, UInt<1>(0h0))
when _T_791 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_788, UInt<1>(0h1), "") : assert_11
node _T_792 = asUInt(reset)
node _T_793 = eq(_T_792, UInt<1>(0h0))
when _T_793 :
node _T_794 = eq(source_ok, UInt<1>(0h0))
when _T_794 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_795 = geq(io.in.a.bits.size, UInt<3>(0h4))
node _T_796 = asUInt(reset)
node _T_797 = eq(_T_796, UInt<1>(0h0))
when _T_797 :
node _T_798 = eq(_T_795, UInt<1>(0h0))
when _T_798 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_795, UInt<1>(0h1), "") : assert_13
node _T_799 = asUInt(reset)
node _T_800 = eq(_T_799, UInt<1>(0h0))
when _T_800 :
node _T_801 = eq(is_aligned, UInt<1>(0h0))
when _T_801 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_802 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_803 = asUInt(reset)
node _T_804 = eq(_T_803, UInt<1>(0h0))
when _T_804 :
node _T_805 = eq(_T_802, UInt<1>(0h0))
when _T_805 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_802, UInt<1>(0h1), "") : assert_15
node _T_806 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_807 = asUInt(reset)
node _T_808 = eq(_T_807, UInt<1>(0h0))
when _T_808 :
node _T_809 = eq(_T_806, UInt<1>(0h0))
when _T_809 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_806, UInt<1>(0h1), "") : assert_16
node _T_810 = not(io.in.a.bits.mask)
node _T_811 = eq(_T_810, UInt<1>(0h0))
node _T_812 = asUInt(reset)
node _T_813 = eq(_T_812, UInt<1>(0h0))
when _T_813 :
node _T_814 = eq(_T_811, UInt<1>(0h0))
when _T_814 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_811, UInt<1>(0h1), "") : assert_17
node _T_815 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_816 = asUInt(reset)
node _T_817 = eq(_T_816, UInt<1>(0h0))
when _T_817 :
node _T_818 = eq(_T_815, UInt<1>(0h0))
when _T_818 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_815, UInt<1>(0h1), "") : assert_18
node _T_819 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_819 :
node _T_820 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_821 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_822 = and(_T_820, _T_821)
node _T_823 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_824 = shr(io.in.a.bits.source, 2)
node _T_825 = eq(_T_824, UInt<1>(0h0))
node _T_826 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_827 = and(_T_825, _T_826)
node _T_828 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_829 = and(_T_827, _T_828)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_830 = shr(io.in.a.bits.source, 2)
node _T_831 = eq(_T_830, UInt<1>(0h1))
node _T_832 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_833 = and(_T_831, _T_832)
node _T_834 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_835 = and(_T_833, _T_834)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_836 = shr(io.in.a.bits.source, 2)
node _T_837 = eq(_T_836, UInt<2>(0h2))
node _T_838 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_839 = and(_T_837, _T_838)
node _T_840 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_841 = and(_T_839, _T_840)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_842 = shr(io.in.a.bits.source, 2)
node _T_843 = eq(_T_842, UInt<2>(0h3))
node _T_844 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_845 = and(_T_843, _T_844)
node _T_846 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_847 = and(_T_845, _T_846)
node _T_848 = eq(io.in.a.bits.source, UInt<7>(0h4c))
node _T_849 = eq(io.in.a.bits.source, UInt<7>(0h4e))
node _T_850 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_851 = eq(io.in.a.bits.source, UInt<7>(0h4a))
node _T_852 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_853 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_854 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_855 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_856 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_857 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_858 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_859 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_860 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_861 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_862 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_863 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_864 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_865 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_866 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_867 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_868 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_869 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_870 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_871 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_872 = or(_T_823, _T_829)
node _T_873 = or(_T_872, _T_835)
node _T_874 = or(_T_873, _T_841)
node _T_875 = or(_T_874, _T_847)
node _T_876 = or(_T_875, _T_848)
node _T_877 = or(_T_876, _T_849)
node _T_878 = or(_T_877, _T_850)
node _T_879 = or(_T_878, _T_851)
node _T_880 = or(_T_879, _T_852)
node _T_881 = or(_T_880, _T_853)
node _T_882 = or(_T_881, _T_854)
node _T_883 = or(_T_882, _T_855)
node _T_884 = or(_T_883, _T_856)
node _T_885 = or(_T_884, _T_857)
node _T_886 = or(_T_885, _T_858)
node _T_887 = or(_T_886, _T_859)
node _T_888 = or(_T_887, _T_860)
node _T_889 = or(_T_888, _T_861)
node _T_890 = or(_T_889, _T_862)
node _T_891 = or(_T_890, _T_863)
node _T_892 = or(_T_891, _T_864)
node _T_893 = or(_T_892, _T_865)
node _T_894 = or(_T_893, _T_866)
node _T_895 = or(_T_894, _T_867)
node _T_896 = or(_T_895, _T_868)
node _T_897 = or(_T_896, _T_869)
node _T_898 = or(_T_897, _T_870)
node _T_899 = or(_T_898, _T_871)
node _T_900 = and(_T_822, _T_899)
node _T_901 = or(UInt<1>(0h0), _T_900)
node _T_902 = asUInt(reset)
node _T_903 = eq(_T_902, UInt<1>(0h0))
when _T_903 :
node _T_904 = eq(_T_901, UInt<1>(0h0))
when _T_904 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_901, UInt<1>(0h1), "") : assert_19
node _T_905 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_906 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_907 = and(_T_905, _T_906)
node _T_908 = or(UInt<1>(0h0), _T_907)
node _T_909 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_910 = cvt(_T_909)
node _T_911 = and(_T_910, asSInt(UInt<17>(0h100c0)))
node _T_912 = asSInt(_T_911)
node _T_913 = eq(_T_912, asSInt(UInt<1>(0h0)))
node _T_914 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_915 = cvt(_T_914)
node _T_916 = and(_T_915, asSInt(UInt<29>(0h100000c0)))
node _T_917 = asSInt(_T_916)
node _T_918 = eq(_T_917, asSInt(UInt<1>(0h0)))
node _T_919 = or(_T_913, _T_918)
node _T_920 = and(_T_908, _T_919)
node _T_921 = or(UInt<1>(0h0), _T_920)
node _T_922 = asUInt(reset)
node _T_923 = eq(_T_922, UInt<1>(0h0))
when _T_923 :
node _T_924 = eq(_T_921, UInt<1>(0h0))
when _T_924 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_921, UInt<1>(0h1), "") : assert_20
node _T_925 = asUInt(reset)
node _T_926 = eq(_T_925, UInt<1>(0h0))
when _T_926 :
node _T_927 = eq(source_ok, UInt<1>(0h0))
when _T_927 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_928 = asUInt(reset)
node _T_929 = eq(_T_928, UInt<1>(0h0))
when _T_929 :
node _T_930 = eq(is_aligned, UInt<1>(0h0))
when _T_930 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_931 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_932 = asUInt(reset)
node _T_933 = eq(_T_932, UInt<1>(0h0))
when _T_933 :
node _T_934 = eq(_T_931, UInt<1>(0h0))
when _T_934 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_931, UInt<1>(0h1), "") : assert_23
node _T_935 = eq(io.in.a.bits.mask, mask)
node _T_936 = asUInt(reset)
node _T_937 = eq(_T_936, UInt<1>(0h0))
when _T_937 :
node _T_938 = eq(_T_935, UInt<1>(0h0))
when _T_938 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_935, UInt<1>(0h1), "") : assert_24
node _T_939 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_940 = asUInt(reset)
node _T_941 = eq(_T_940, UInt<1>(0h0))
when _T_941 :
node _T_942 = eq(_T_939, UInt<1>(0h0))
when _T_942 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_939, UInt<1>(0h1), "") : assert_25
node _T_943 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_943 :
node _T_944 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_945 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_946 = and(_T_944, _T_945)
node _T_947 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_948 = shr(io.in.a.bits.source, 2)
node _T_949 = eq(_T_948, UInt<1>(0h0))
node _T_950 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_951 = and(_T_949, _T_950)
node _T_952 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_953 = and(_T_951, _T_952)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_954 = shr(io.in.a.bits.source, 2)
node _T_955 = eq(_T_954, UInt<1>(0h1))
node _T_956 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_957 = and(_T_955, _T_956)
node _T_958 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_959 = and(_T_957, _T_958)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_960 = shr(io.in.a.bits.source, 2)
node _T_961 = eq(_T_960, UInt<2>(0h2))
node _T_962 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_963 = and(_T_961, _T_962)
node _T_964 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_965 = and(_T_963, _T_964)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_966 = shr(io.in.a.bits.source, 2)
node _T_967 = eq(_T_966, UInt<2>(0h3))
node _T_968 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_969 = and(_T_967, _T_968)
node _T_970 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_971 = and(_T_969, _T_970)
node _T_972 = eq(io.in.a.bits.source, UInt<7>(0h4c))
node _T_973 = eq(io.in.a.bits.source, UInt<7>(0h4e))
node _T_974 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_975 = eq(io.in.a.bits.source, UInt<7>(0h4a))
node _T_976 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_977 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_978 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_979 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_980 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_981 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_982 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_983 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_984 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_985 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_986 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_987 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_988 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_989 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_990 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_991 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_992 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_993 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_994 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_995 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_996 = or(_T_947, _T_953)
node _T_997 = or(_T_996, _T_959)
node _T_998 = or(_T_997, _T_965)
node _T_999 = or(_T_998, _T_971)
node _T_1000 = or(_T_999, _T_972)
node _T_1001 = or(_T_1000, _T_973)
node _T_1002 = or(_T_1001, _T_974)
node _T_1003 = or(_T_1002, _T_975)
node _T_1004 = or(_T_1003, _T_976)
node _T_1005 = or(_T_1004, _T_977)
node _T_1006 = or(_T_1005, _T_978)
node _T_1007 = or(_T_1006, _T_979)
node _T_1008 = or(_T_1007, _T_980)
node _T_1009 = or(_T_1008, _T_981)
node _T_1010 = or(_T_1009, _T_982)
node _T_1011 = or(_T_1010, _T_983)
node _T_1012 = or(_T_1011, _T_984)
node _T_1013 = or(_T_1012, _T_985)
node _T_1014 = or(_T_1013, _T_986)
node _T_1015 = or(_T_1014, _T_987)
node _T_1016 = or(_T_1015, _T_988)
node _T_1017 = or(_T_1016, _T_989)
node _T_1018 = or(_T_1017, _T_990)
node _T_1019 = or(_T_1018, _T_991)
node _T_1020 = or(_T_1019, _T_992)
node _T_1021 = or(_T_1020, _T_993)
node _T_1022 = or(_T_1021, _T_994)
node _T_1023 = or(_T_1022, _T_995)
node _T_1024 = and(_T_946, _T_1023)
node _T_1025 = or(UInt<1>(0h0), _T_1024)
node _T_1026 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1027 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1028 = and(_T_1026, _T_1027)
node _T_1029 = or(UInt<1>(0h0), _T_1028)
node _T_1030 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_1031 = cvt(_T_1030)
node _T_1032 = and(_T_1031, asSInt(UInt<17>(0h100c0)))
node _T_1033 = asSInt(_T_1032)
node _T_1034 = eq(_T_1033, asSInt(UInt<1>(0h0)))
node _T_1035 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_1036 = cvt(_T_1035)
node _T_1037 = and(_T_1036, asSInt(UInt<29>(0h100000c0)))
node _T_1038 = asSInt(_T_1037)
node _T_1039 = eq(_T_1038, asSInt(UInt<1>(0h0)))
node _T_1040 = or(_T_1034, _T_1039)
node _T_1041 = and(_T_1029, _T_1040)
node _T_1042 = or(UInt<1>(0h0), _T_1041)
node _T_1043 = and(_T_1025, _T_1042)
node _T_1044 = asUInt(reset)
node _T_1045 = eq(_T_1044, UInt<1>(0h0))
when _T_1045 :
node _T_1046 = eq(_T_1043, UInt<1>(0h0))
when _T_1046 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_1043, UInt<1>(0h1), "") : assert_26
node _T_1047 = asUInt(reset)
node _T_1048 = eq(_T_1047, UInt<1>(0h0))
when _T_1048 :
node _T_1049 = eq(source_ok, UInt<1>(0h0))
when _T_1049 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_1050 = asUInt(reset)
node _T_1051 = eq(_T_1050, UInt<1>(0h0))
when _T_1051 :
node _T_1052 = eq(is_aligned, UInt<1>(0h0))
when _T_1052 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_1053 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_1054 = asUInt(reset)
node _T_1055 = eq(_T_1054, UInt<1>(0h0))
when _T_1055 :
node _T_1056 = eq(_T_1053, UInt<1>(0h0))
when _T_1056 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_1053, UInt<1>(0h1), "") : assert_29
node _T_1057 = eq(io.in.a.bits.mask, mask)
node _T_1058 = asUInt(reset)
node _T_1059 = eq(_T_1058, UInt<1>(0h0))
when _T_1059 :
node _T_1060 = eq(_T_1057, UInt<1>(0h0))
when _T_1060 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_1057, UInt<1>(0h1), "") : assert_30
node _T_1061 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_1061 :
node _T_1062 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1063 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1064 = and(_T_1062, _T_1063)
node _T_1065 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_1066 = shr(io.in.a.bits.source, 2)
node _T_1067 = eq(_T_1066, UInt<1>(0h0))
node _T_1068 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_1069 = and(_T_1067, _T_1068)
node _T_1070 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_1071 = and(_T_1069, _T_1070)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_1072 = shr(io.in.a.bits.source, 2)
node _T_1073 = eq(_T_1072, UInt<1>(0h1))
node _T_1074 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_1075 = and(_T_1073, _T_1074)
node _T_1076 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_1077 = and(_T_1075, _T_1076)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_1078 = shr(io.in.a.bits.source, 2)
node _T_1079 = eq(_T_1078, UInt<2>(0h2))
node _T_1080 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_1081 = and(_T_1079, _T_1080)
node _T_1082 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_1083 = and(_T_1081, _T_1082)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_1084 = shr(io.in.a.bits.source, 2)
node _T_1085 = eq(_T_1084, UInt<2>(0h3))
node _T_1086 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_1087 = and(_T_1085, _T_1086)
node _T_1088 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_1089 = and(_T_1087, _T_1088)
node _T_1090 = eq(io.in.a.bits.source, UInt<7>(0h4c))
node _T_1091 = eq(io.in.a.bits.source, UInt<7>(0h4e))
node _T_1092 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_1093 = eq(io.in.a.bits.source, UInt<7>(0h4a))
node _T_1094 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_1095 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_1096 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1097 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_1098 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_1099 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_1100 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_1101 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_1102 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_1103 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_1104 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_1105 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_1106 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_1107 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_1108 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1109 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1110 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1111 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1112 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1113 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1114 = or(_T_1065, _T_1071)
node _T_1115 = or(_T_1114, _T_1077)
node _T_1116 = or(_T_1115, _T_1083)
node _T_1117 = or(_T_1116, _T_1089)
node _T_1118 = or(_T_1117, _T_1090)
node _T_1119 = or(_T_1118, _T_1091)
node _T_1120 = or(_T_1119, _T_1092)
node _T_1121 = or(_T_1120, _T_1093)
node _T_1122 = or(_T_1121, _T_1094)
node _T_1123 = or(_T_1122, _T_1095)
node _T_1124 = or(_T_1123, _T_1096)
node _T_1125 = or(_T_1124, _T_1097)
node _T_1126 = or(_T_1125, _T_1098)
node _T_1127 = or(_T_1126, _T_1099)
node _T_1128 = or(_T_1127, _T_1100)
node _T_1129 = or(_T_1128, _T_1101)
node _T_1130 = or(_T_1129, _T_1102)
node _T_1131 = or(_T_1130, _T_1103)
node _T_1132 = or(_T_1131, _T_1104)
node _T_1133 = or(_T_1132, _T_1105)
node _T_1134 = or(_T_1133, _T_1106)
node _T_1135 = or(_T_1134, _T_1107)
node _T_1136 = or(_T_1135, _T_1108)
node _T_1137 = or(_T_1136, _T_1109)
node _T_1138 = or(_T_1137, _T_1110)
node _T_1139 = or(_T_1138, _T_1111)
node _T_1140 = or(_T_1139, _T_1112)
node _T_1141 = or(_T_1140, _T_1113)
node _T_1142 = and(_T_1064, _T_1141)
node _T_1143 = or(UInt<1>(0h0), _T_1142)
node _T_1144 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1145 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1146 = and(_T_1144, _T_1145)
node _T_1147 = or(UInt<1>(0h0), _T_1146)
node _T_1148 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_1149 = cvt(_T_1148)
node _T_1150 = and(_T_1149, asSInt(UInt<17>(0h100c0)))
node _T_1151 = asSInt(_T_1150)
node _T_1152 = eq(_T_1151, asSInt(UInt<1>(0h0)))
node _T_1153 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_1154 = cvt(_T_1153)
node _T_1155 = and(_T_1154, asSInt(UInt<29>(0h100000c0)))
node _T_1156 = asSInt(_T_1155)
node _T_1157 = eq(_T_1156, asSInt(UInt<1>(0h0)))
node _T_1158 = or(_T_1152, _T_1157)
node _T_1159 = and(_T_1147, _T_1158)
node _T_1160 = or(UInt<1>(0h0), _T_1159)
node _T_1161 = and(_T_1143, _T_1160)
node _T_1162 = asUInt(reset)
node _T_1163 = eq(_T_1162, UInt<1>(0h0))
when _T_1163 :
node _T_1164 = eq(_T_1161, UInt<1>(0h0))
when _T_1164 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_1161, UInt<1>(0h1), "") : assert_31
node _T_1165 = asUInt(reset)
node _T_1166 = eq(_T_1165, UInt<1>(0h0))
when _T_1166 :
node _T_1167 = eq(source_ok, UInt<1>(0h0))
when _T_1167 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_1168 = asUInt(reset)
node _T_1169 = eq(_T_1168, UInt<1>(0h0))
when _T_1169 :
node _T_1170 = eq(is_aligned, UInt<1>(0h0))
when _T_1170 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_1171 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_1172 = asUInt(reset)
node _T_1173 = eq(_T_1172, UInt<1>(0h0))
when _T_1173 :
node _T_1174 = eq(_T_1171, UInt<1>(0h0))
when _T_1174 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_1171, UInt<1>(0h1), "") : assert_34
node _T_1175 = not(mask)
node _T_1176 = and(io.in.a.bits.mask, _T_1175)
node _T_1177 = eq(_T_1176, UInt<1>(0h0))
node _T_1178 = asUInt(reset)
node _T_1179 = eq(_T_1178, UInt<1>(0h0))
when _T_1179 :
node _T_1180 = eq(_T_1177, UInt<1>(0h0))
when _T_1180 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_1177, UInt<1>(0h1), "") : assert_35
node _T_1181 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_1181 :
node _T_1182 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1183 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1184 = and(_T_1182, _T_1183)
node _T_1185 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_1186 = shr(io.in.a.bits.source, 2)
node _T_1187 = eq(_T_1186, UInt<1>(0h0))
node _T_1188 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_1189 = and(_T_1187, _T_1188)
node _T_1190 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_1191 = and(_T_1189, _T_1190)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_1192 = shr(io.in.a.bits.source, 2)
node _T_1193 = eq(_T_1192, UInt<1>(0h1))
node _T_1194 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_1195 = and(_T_1193, _T_1194)
node _T_1196 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_1197 = and(_T_1195, _T_1196)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_1198 = shr(io.in.a.bits.source, 2)
node _T_1199 = eq(_T_1198, UInt<2>(0h2))
node _T_1200 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_1201 = and(_T_1199, _T_1200)
node _T_1202 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_1203 = and(_T_1201, _T_1202)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_1204 = shr(io.in.a.bits.source, 2)
node _T_1205 = eq(_T_1204, UInt<2>(0h3))
node _T_1206 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_1207 = and(_T_1205, _T_1206)
node _T_1208 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_1209 = and(_T_1207, _T_1208)
node _T_1210 = eq(io.in.a.bits.source, UInt<7>(0h4c))
node _T_1211 = eq(io.in.a.bits.source, UInt<7>(0h4e))
node _T_1212 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_1213 = eq(io.in.a.bits.source, UInt<7>(0h4a))
node _T_1214 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_1215 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_1216 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1217 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_1218 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_1219 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_1220 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_1221 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_1222 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_1223 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_1224 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_1225 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_1226 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_1227 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_1228 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1229 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1230 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1231 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1232 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1233 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1234 = or(_T_1185, _T_1191)
node _T_1235 = or(_T_1234, _T_1197)
node _T_1236 = or(_T_1235, _T_1203)
node _T_1237 = or(_T_1236, _T_1209)
node _T_1238 = or(_T_1237, _T_1210)
node _T_1239 = or(_T_1238, _T_1211)
node _T_1240 = or(_T_1239, _T_1212)
node _T_1241 = or(_T_1240, _T_1213)
node _T_1242 = or(_T_1241, _T_1214)
node _T_1243 = or(_T_1242, _T_1215)
node _T_1244 = or(_T_1243, _T_1216)
node _T_1245 = or(_T_1244, _T_1217)
node _T_1246 = or(_T_1245, _T_1218)
node _T_1247 = or(_T_1246, _T_1219)
node _T_1248 = or(_T_1247, _T_1220)
node _T_1249 = or(_T_1248, _T_1221)
node _T_1250 = or(_T_1249, _T_1222)
node _T_1251 = or(_T_1250, _T_1223)
node _T_1252 = or(_T_1251, _T_1224)
node _T_1253 = or(_T_1252, _T_1225)
node _T_1254 = or(_T_1253, _T_1226)
node _T_1255 = or(_T_1254, _T_1227)
node _T_1256 = or(_T_1255, _T_1228)
node _T_1257 = or(_T_1256, _T_1229)
node _T_1258 = or(_T_1257, _T_1230)
node _T_1259 = or(_T_1258, _T_1231)
node _T_1260 = or(_T_1259, _T_1232)
node _T_1261 = or(_T_1260, _T_1233)
node _T_1262 = and(_T_1184, _T_1261)
node _T_1263 = or(UInt<1>(0h0), _T_1262)
node _T_1264 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1265 = leq(io.in.a.bits.size, UInt<3>(0h4))
node _T_1266 = and(_T_1264, _T_1265)
node _T_1267 = or(UInt<1>(0h0), _T_1266)
node _T_1268 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_1269 = cvt(_T_1268)
node _T_1270 = and(_T_1269, asSInt(UInt<17>(0h100c0)))
node _T_1271 = asSInt(_T_1270)
node _T_1272 = eq(_T_1271, asSInt(UInt<1>(0h0)))
node _T_1273 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_1274 = cvt(_T_1273)
node _T_1275 = and(_T_1274, asSInt(UInt<29>(0h100000c0)))
node _T_1276 = asSInt(_T_1275)
node _T_1277 = eq(_T_1276, asSInt(UInt<1>(0h0)))
node _T_1278 = or(_T_1272, _T_1277)
node _T_1279 = and(_T_1267, _T_1278)
node _T_1280 = or(UInt<1>(0h0), _T_1279)
node _T_1281 = and(_T_1263, _T_1280)
node _T_1282 = asUInt(reset)
node _T_1283 = eq(_T_1282, UInt<1>(0h0))
when _T_1283 :
node _T_1284 = eq(_T_1281, UInt<1>(0h0))
when _T_1284 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_1281, UInt<1>(0h1), "") : assert_36
node _T_1285 = asUInt(reset)
node _T_1286 = eq(_T_1285, UInt<1>(0h0))
when _T_1286 :
node _T_1287 = eq(source_ok, UInt<1>(0h0))
when _T_1287 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_1288 = asUInt(reset)
node _T_1289 = eq(_T_1288, UInt<1>(0h0))
when _T_1289 :
node _T_1290 = eq(is_aligned, UInt<1>(0h0))
when _T_1290 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_1291 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_1292 = asUInt(reset)
node _T_1293 = eq(_T_1292, UInt<1>(0h0))
when _T_1293 :
node _T_1294 = eq(_T_1291, UInt<1>(0h0))
when _T_1294 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_1291, UInt<1>(0h1), "") : assert_39
node _T_1295 = eq(io.in.a.bits.mask, mask)
node _T_1296 = asUInt(reset)
node _T_1297 = eq(_T_1296, UInt<1>(0h0))
when _T_1297 :
node _T_1298 = eq(_T_1295, UInt<1>(0h0))
when _T_1298 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_1295, UInt<1>(0h1), "") : assert_40
node _T_1299 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_1299 :
node _T_1300 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1301 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1302 = and(_T_1300, _T_1301)
node _T_1303 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_1304 = shr(io.in.a.bits.source, 2)
node _T_1305 = eq(_T_1304, UInt<1>(0h0))
node _T_1306 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_1307 = and(_T_1305, _T_1306)
node _T_1308 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_1309 = and(_T_1307, _T_1308)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_1310 = shr(io.in.a.bits.source, 2)
node _T_1311 = eq(_T_1310, UInt<1>(0h1))
node _T_1312 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_1313 = and(_T_1311, _T_1312)
node _T_1314 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_1315 = and(_T_1313, _T_1314)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_1316 = shr(io.in.a.bits.source, 2)
node _T_1317 = eq(_T_1316, UInt<2>(0h2))
node _T_1318 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_1319 = and(_T_1317, _T_1318)
node _T_1320 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_1321 = and(_T_1319, _T_1320)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_1322 = shr(io.in.a.bits.source, 2)
node _T_1323 = eq(_T_1322, UInt<2>(0h3))
node _T_1324 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_1325 = and(_T_1323, _T_1324)
node _T_1326 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_1327 = and(_T_1325, _T_1326)
node _T_1328 = eq(io.in.a.bits.source, UInt<7>(0h4c))
node _T_1329 = eq(io.in.a.bits.source, UInt<7>(0h4e))
node _T_1330 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_1331 = eq(io.in.a.bits.source, UInt<7>(0h4a))
node _T_1332 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_1333 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_1334 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1335 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_1336 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_1337 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_1338 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_1339 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_1340 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_1341 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_1342 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_1343 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_1344 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_1345 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_1346 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1347 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1348 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1349 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1350 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1351 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1352 = or(_T_1303, _T_1309)
node _T_1353 = or(_T_1352, _T_1315)
node _T_1354 = or(_T_1353, _T_1321)
node _T_1355 = or(_T_1354, _T_1327)
node _T_1356 = or(_T_1355, _T_1328)
node _T_1357 = or(_T_1356, _T_1329)
node _T_1358 = or(_T_1357, _T_1330)
node _T_1359 = or(_T_1358, _T_1331)
node _T_1360 = or(_T_1359, _T_1332)
node _T_1361 = or(_T_1360, _T_1333)
node _T_1362 = or(_T_1361, _T_1334)
node _T_1363 = or(_T_1362, _T_1335)
node _T_1364 = or(_T_1363, _T_1336)
node _T_1365 = or(_T_1364, _T_1337)
node _T_1366 = or(_T_1365, _T_1338)
node _T_1367 = or(_T_1366, _T_1339)
node _T_1368 = or(_T_1367, _T_1340)
node _T_1369 = or(_T_1368, _T_1341)
node _T_1370 = or(_T_1369, _T_1342)
node _T_1371 = or(_T_1370, _T_1343)
node _T_1372 = or(_T_1371, _T_1344)
node _T_1373 = or(_T_1372, _T_1345)
node _T_1374 = or(_T_1373, _T_1346)
node _T_1375 = or(_T_1374, _T_1347)
node _T_1376 = or(_T_1375, _T_1348)
node _T_1377 = or(_T_1376, _T_1349)
node _T_1378 = or(_T_1377, _T_1350)
node _T_1379 = or(_T_1378, _T_1351)
node _T_1380 = and(_T_1302, _T_1379)
node _T_1381 = or(UInt<1>(0h0), _T_1380)
node _T_1382 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1383 = leq(io.in.a.bits.size, UInt<3>(0h4))
node _T_1384 = and(_T_1382, _T_1383)
node _T_1385 = or(UInt<1>(0h0), _T_1384)
node _T_1386 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_1387 = cvt(_T_1386)
node _T_1388 = and(_T_1387, asSInt(UInt<17>(0h100c0)))
node _T_1389 = asSInt(_T_1388)
node _T_1390 = eq(_T_1389, asSInt(UInt<1>(0h0)))
node _T_1391 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_1392 = cvt(_T_1391)
node _T_1393 = and(_T_1392, asSInt(UInt<29>(0h100000c0)))
node _T_1394 = asSInt(_T_1393)
node _T_1395 = eq(_T_1394, asSInt(UInt<1>(0h0)))
node _T_1396 = or(_T_1390, _T_1395)
node _T_1397 = and(_T_1385, _T_1396)
node _T_1398 = or(UInt<1>(0h0), _T_1397)
node _T_1399 = and(_T_1381, _T_1398)
node _T_1400 = asUInt(reset)
node _T_1401 = eq(_T_1400, UInt<1>(0h0))
when _T_1401 :
node _T_1402 = eq(_T_1399, UInt<1>(0h0))
when _T_1402 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_1399, UInt<1>(0h1), "") : assert_41
node _T_1403 = asUInt(reset)
node _T_1404 = eq(_T_1403, UInt<1>(0h0))
when _T_1404 :
node _T_1405 = eq(source_ok, UInt<1>(0h0))
when _T_1405 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_1406 = asUInt(reset)
node _T_1407 = eq(_T_1406, UInt<1>(0h0))
when _T_1407 :
node _T_1408 = eq(is_aligned, UInt<1>(0h0))
when _T_1408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_1409 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_1410 = asUInt(reset)
node _T_1411 = eq(_T_1410, UInt<1>(0h0))
when _T_1411 :
node _T_1412 = eq(_T_1409, UInt<1>(0h0))
when _T_1412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_1409, UInt<1>(0h1), "") : assert_44
node _T_1413 = eq(io.in.a.bits.mask, mask)
node _T_1414 = asUInt(reset)
node _T_1415 = eq(_T_1414, UInt<1>(0h0))
when _T_1415 :
node _T_1416 = eq(_T_1413, UInt<1>(0h0))
when _T_1416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_1413, UInt<1>(0h1), "") : assert_45
node _T_1417 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_1417 :
node _T_1418 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1419 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1420 = and(_T_1418, _T_1419)
node _T_1421 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0)
node _T_1422 = shr(io.in.a.bits.source, 2)
node _T_1423 = eq(_T_1422, UInt<1>(0h0))
node _T_1424 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_1425 = and(_T_1423, _T_1424)
node _T_1426 = leq(uncommonBits_40, UInt<2>(0h3))
node _T_1427 = and(_T_1425, _T_1426)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0)
node _T_1428 = shr(io.in.a.bits.source, 2)
node _T_1429 = eq(_T_1428, UInt<1>(0h1))
node _T_1430 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_1431 = and(_T_1429, _T_1430)
node _T_1432 = leq(uncommonBits_41, UInt<2>(0h3))
node _T_1433 = and(_T_1431, _T_1432)
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_1434 = shr(io.in.a.bits.source, 2)
node _T_1435 = eq(_T_1434, UInt<2>(0h2))
node _T_1436 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_1437 = and(_T_1435, _T_1436)
node _T_1438 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_1439 = and(_T_1437, _T_1438)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_1440 = shr(io.in.a.bits.source, 2)
node _T_1441 = eq(_T_1440, UInt<2>(0h3))
node _T_1442 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_1443 = and(_T_1441, _T_1442)
node _T_1444 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_1445 = and(_T_1443, _T_1444)
node _T_1446 = eq(io.in.a.bits.source, UInt<7>(0h4c))
node _T_1447 = eq(io.in.a.bits.source, UInt<7>(0h4e))
node _T_1448 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_1449 = eq(io.in.a.bits.source, UInt<7>(0h4a))
node _T_1450 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_1451 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_1452 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1453 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_1454 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_1455 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_1456 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_1457 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_1458 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_1459 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_1460 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_1461 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_1462 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_1463 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_1464 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1465 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1466 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1467 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1468 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1469 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1470 = or(_T_1421, _T_1427)
node _T_1471 = or(_T_1470, _T_1433)
node _T_1472 = or(_T_1471, _T_1439)
node _T_1473 = or(_T_1472, _T_1445)
node _T_1474 = or(_T_1473, _T_1446)
node _T_1475 = or(_T_1474, _T_1447)
node _T_1476 = or(_T_1475, _T_1448)
node _T_1477 = or(_T_1476, _T_1449)
node _T_1478 = or(_T_1477, _T_1450)
node _T_1479 = or(_T_1478, _T_1451)
node _T_1480 = or(_T_1479, _T_1452)
node _T_1481 = or(_T_1480, _T_1453)
node _T_1482 = or(_T_1481, _T_1454)
node _T_1483 = or(_T_1482, _T_1455)
node _T_1484 = or(_T_1483, _T_1456)
node _T_1485 = or(_T_1484, _T_1457)
node _T_1486 = or(_T_1485, _T_1458)
node _T_1487 = or(_T_1486, _T_1459)
node _T_1488 = or(_T_1487, _T_1460)
node _T_1489 = or(_T_1488, _T_1461)
node _T_1490 = or(_T_1489, _T_1462)
node _T_1491 = or(_T_1490, _T_1463)
node _T_1492 = or(_T_1491, _T_1464)
node _T_1493 = or(_T_1492, _T_1465)
node _T_1494 = or(_T_1493, _T_1466)
node _T_1495 = or(_T_1494, _T_1467)
node _T_1496 = or(_T_1495, _T_1468)
node _T_1497 = or(_T_1496, _T_1469)
node _T_1498 = and(_T_1420, _T_1497)
node _T_1499 = or(UInt<1>(0h0), _T_1498)
node _T_1500 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1501 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1502 = and(_T_1500, _T_1501)
node _T_1503 = or(UInt<1>(0h0), _T_1502)
node _T_1504 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_1505 = cvt(_T_1504)
node _T_1506 = and(_T_1505, asSInt(UInt<17>(0h100c0)))
node _T_1507 = asSInt(_T_1506)
node _T_1508 = eq(_T_1507, asSInt(UInt<1>(0h0)))
node _T_1509 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_1510 = cvt(_T_1509)
node _T_1511 = and(_T_1510, asSInt(UInt<29>(0h100000c0)))
node _T_1512 = asSInt(_T_1511)
node _T_1513 = eq(_T_1512, asSInt(UInt<1>(0h0)))
node _T_1514 = or(_T_1508, _T_1513)
node _T_1515 = and(_T_1503, _T_1514)
node _T_1516 = or(UInt<1>(0h0), _T_1515)
node _T_1517 = and(_T_1499, _T_1516)
node _T_1518 = asUInt(reset)
node _T_1519 = eq(_T_1518, UInt<1>(0h0))
when _T_1519 :
node _T_1520 = eq(_T_1517, UInt<1>(0h0))
when _T_1520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1517, UInt<1>(0h1), "") : assert_46
node _T_1521 = asUInt(reset)
node _T_1522 = eq(_T_1521, UInt<1>(0h0))
when _T_1522 :
node _T_1523 = eq(source_ok, UInt<1>(0h0))
when _T_1523 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1524 = asUInt(reset)
node _T_1525 = eq(_T_1524, UInt<1>(0h0))
when _T_1525 :
node _T_1526 = eq(is_aligned, UInt<1>(0h0))
when _T_1526 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1527 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1528 = asUInt(reset)
node _T_1529 = eq(_T_1528, UInt<1>(0h0))
when _T_1529 :
node _T_1530 = eq(_T_1527, UInt<1>(0h0))
when _T_1530 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1527, UInt<1>(0h1), "") : assert_49
node _T_1531 = eq(io.in.a.bits.mask, mask)
node _T_1532 = asUInt(reset)
node _T_1533 = eq(_T_1532, UInt<1>(0h0))
when _T_1533 :
node _T_1534 = eq(_T_1531, UInt<1>(0h0))
when _T_1534 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1531, UInt<1>(0h1), "") : assert_50
node _T_1535 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1536 = asUInt(reset)
node _T_1537 = eq(_T_1536, UInt<1>(0h0))
when _T_1537 :
node _T_1538 = eq(_T_1535, UInt<1>(0h0))
when _T_1538 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1535, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1539 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1540 = asUInt(reset)
node _T_1541 = eq(_T_1540, UInt<1>(0h0))
when _T_1541 :
node _T_1542 = eq(_T_1539, UInt<1>(0h0))
when _T_1542 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1539, UInt<1>(0h1), "") : assert_52
node _source_ok_T_76 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_77 = shr(io.in.d.bits.source, 2)
node _source_ok_T_78 = eq(_source_ok_T_77, UInt<1>(0h0))
node _source_ok_T_79 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_80 = and(_source_ok_T_78, _source_ok_T_79)
node _source_ok_T_81 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81)
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_83 = shr(io.in.d.bits.source, 2)
node _source_ok_T_84 = eq(_source_ok_T_83, UInt<1>(0h1))
node _source_ok_T_85 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_86 = and(_source_ok_T_84, _source_ok_T_85)
node _source_ok_T_87 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_89 = shr(io.in.d.bits.source, 2)
node _source_ok_T_90 = eq(_source_ok_T_89, UInt<2>(0h2))
node _source_ok_T_91 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_92 = and(_source_ok_T_90, _source_ok_T_91)
node _source_ok_T_93 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_94 = and(_source_ok_T_92, _source_ok_T_93)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_95 = shr(io.in.d.bits.source, 2)
node _source_ok_T_96 = eq(_source_ok_T_95, UInt<2>(0h3))
node _source_ok_T_97 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_98 = and(_source_ok_T_96, _source_ok_T_97)
node _source_ok_T_99 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_100 = and(_source_ok_T_98, _source_ok_T_99)
node _source_ok_T_101 = eq(io.in.d.bits.source, UInt<7>(0h4c))
node _source_ok_T_102 = eq(io.in.d.bits.source, UInt<7>(0h4e))
node _source_ok_T_103 = eq(io.in.d.bits.source, UInt<7>(0h48))
node _source_ok_T_104 = eq(io.in.d.bits.source, UInt<7>(0h4a))
node _source_ok_T_105 = eq(io.in.d.bits.source, UInt<7>(0h44))
node _source_ok_T_106 = eq(io.in.d.bits.source, UInt<7>(0h46))
node _source_ok_T_107 = eq(io.in.d.bits.source, UInt<7>(0h40))
node _source_ok_T_108 = eq(io.in.d.bits.source, UInt<7>(0h42))
node _source_ok_T_109 = eq(io.in.d.bits.source, UInt<6>(0h3c))
node _source_ok_T_110 = eq(io.in.d.bits.source, UInt<6>(0h3e))
node _source_ok_T_111 = eq(io.in.d.bits.source, UInt<6>(0h38))
node _source_ok_T_112 = eq(io.in.d.bits.source, UInt<6>(0h3a))
node _source_ok_T_113 = eq(io.in.d.bits.source, UInt<6>(0h34))
node _source_ok_T_114 = eq(io.in.d.bits.source, UInt<6>(0h36))
node _source_ok_T_115 = eq(io.in.d.bits.source, UInt<6>(0h30))
node _source_ok_T_116 = eq(io.in.d.bits.source, UInt<6>(0h32))
node _source_ok_T_117 = eq(io.in.d.bits.source, UInt<6>(0h2c))
node _source_ok_T_118 = eq(io.in.d.bits.source, UInt<6>(0h2e))
node _source_ok_T_119 = eq(io.in.d.bits.source, UInt<6>(0h28))
node _source_ok_T_120 = eq(io.in.d.bits.source, UInt<6>(0h2a))
node _source_ok_T_121 = eq(io.in.d.bits.source, UInt<6>(0h24))
node _source_ok_T_122 = eq(io.in.d.bits.source, UInt<6>(0h26))
node _source_ok_T_123 = eq(io.in.d.bits.source, UInt<6>(0h20))
node _source_ok_T_124 = eq(io.in.d.bits.source, UInt<6>(0h22))
wire _source_ok_WIRE_1 : UInt<1>[29]
connect _source_ok_WIRE_1[0], _source_ok_T_76
connect _source_ok_WIRE_1[1], _source_ok_T_82
connect _source_ok_WIRE_1[2], _source_ok_T_88
connect _source_ok_WIRE_1[3], _source_ok_T_94
connect _source_ok_WIRE_1[4], _source_ok_T_100
connect _source_ok_WIRE_1[5], _source_ok_T_101
connect _source_ok_WIRE_1[6], _source_ok_T_102
connect _source_ok_WIRE_1[7], _source_ok_T_103
connect _source_ok_WIRE_1[8], _source_ok_T_104
connect _source_ok_WIRE_1[9], _source_ok_T_105
connect _source_ok_WIRE_1[10], _source_ok_T_106
connect _source_ok_WIRE_1[11], _source_ok_T_107
connect _source_ok_WIRE_1[12], _source_ok_T_108
connect _source_ok_WIRE_1[13], _source_ok_T_109
connect _source_ok_WIRE_1[14], _source_ok_T_110
connect _source_ok_WIRE_1[15], _source_ok_T_111
connect _source_ok_WIRE_1[16], _source_ok_T_112
connect _source_ok_WIRE_1[17], _source_ok_T_113
connect _source_ok_WIRE_1[18], _source_ok_T_114
connect _source_ok_WIRE_1[19], _source_ok_T_115
connect _source_ok_WIRE_1[20], _source_ok_T_116
connect _source_ok_WIRE_1[21], _source_ok_T_117
connect _source_ok_WIRE_1[22], _source_ok_T_118
connect _source_ok_WIRE_1[23], _source_ok_T_119
connect _source_ok_WIRE_1[24], _source_ok_T_120
connect _source_ok_WIRE_1[25], _source_ok_T_121
connect _source_ok_WIRE_1[26], _source_ok_T_122
connect _source_ok_WIRE_1[27], _source_ok_T_123
connect _source_ok_WIRE_1[28], _source_ok_T_124
node _source_ok_T_125 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_126 = or(_source_ok_T_125, _source_ok_WIRE_1[2])
node _source_ok_T_127 = or(_source_ok_T_126, _source_ok_WIRE_1[3])
node _source_ok_T_128 = or(_source_ok_T_127, _source_ok_WIRE_1[4])
node _source_ok_T_129 = or(_source_ok_T_128, _source_ok_WIRE_1[5])
node _source_ok_T_130 = or(_source_ok_T_129, _source_ok_WIRE_1[6])
node _source_ok_T_131 = or(_source_ok_T_130, _source_ok_WIRE_1[7])
node _source_ok_T_132 = or(_source_ok_T_131, _source_ok_WIRE_1[8])
node _source_ok_T_133 = or(_source_ok_T_132, _source_ok_WIRE_1[9])
node _source_ok_T_134 = or(_source_ok_T_133, _source_ok_WIRE_1[10])
node _source_ok_T_135 = or(_source_ok_T_134, _source_ok_WIRE_1[11])
node _source_ok_T_136 = or(_source_ok_T_135, _source_ok_WIRE_1[12])
node _source_ok_T_137 = or(_source_ok_T_136, _source_ok_WIRE_1[13])
node _source_ok_T_138 = or(_source_ok_T_137, _source_ok_WIRE_1[14])
node _source_ok_T_139 = or(_source_ok_T_138, _source_ok_WIRE_1[15])
node _source_ok_T_140 = or(_source_ok_T_139, _source_ok_WIRE_1[16])
node _source_ok_T_141 = or(_source_ok_T_140, _source_ok_WIRE_1[17])
node _source_ok_T_142 = or(_source_ok_T_141, _source_ok_WIRE_1[18])
node _source_ok_T_143 = or(_source_ok_T_142, _source_ok_WIRE_1[19])
node _source_ok_T_144 = or(_source_ok_T_143, _source_ok_WIRE_1[20])
node _source_ok_T_145 = or(_source_ok_T_144, _source_ok_WIRE_1[21])
node _source_ok_T_146 = or(_source_ok_T_145, _source_ok_WIRE_1[22])
node _source_ok_T_147 = or(_source_ok_T_146, _source_ok_WIRE_1[23])
node _source_ok_T_148 = or(_source_ok_T_147, _source_ok_WIRE_1[24])
node _source_ok_T_149 = or(_source_ok_T_148, _source_ok_WIRE_1[25])
node _source_ok_T_150 = or(_source_ok_T_149, _source_ok_WIRE_1[26])
node _source_ok_T_151 = or(_source_ok_T_150, _source_ok_WIRE_1[27])
node source_ok_1 = or(_source_ok_T_151, _source_ok_WIRE_1[28])
node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0hc))
node _T_1543 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1543 :
node _T_1544 = asUInt(reset)
node _T_1545 = eq(_T_1544, UInt<1>(0h0))
when _T_1545 :
node _T_1546 = eq(source_ok_1, UInt<1>(0h0))
when _T_1546 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1547 = geq(io.in.d.bits.size, UInt<3>(0h4))
node _T_1548 = asUInt(reset)
node _T_1549 = eq(_T_1548, UInt<1>(0h0))
when _T_1549 :
node _T_1550 = eq(_T_1547, UInt<1>(0h0))
when _T_1550 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1547, UInt<1>(0h1), "") : assert_54
node _T_1551 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1552 = asUInt(reset)
node _T_1553 = eq(_T_1552, UInt<1>(0h0))
when _T_1553 :
node _T_1554 = eq(_T_1551, UInt<1>(0h0))
when _T_1554 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1551, UInt<1>(0h1), "") : assert_55
node _T_1555 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1556 = asUInt(reset)
node _T_1557 = eq(_T_1556, UInt<1>(0h0))
when _T_1557 :
node _T_1558 = eq(_T_1555, UInt<1>(0h0))
when _T_1558 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1555, UInt<1>(0h1), "") : assert_56
node _T_1559 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1560 = asUInt(reset)
node _T_1561 = eq(_T_1560, UInt<1>(0h0))
when _T_1561 :
node _T_1562 = eq(_T_1559, UInt<1>(0h0))
when _T_1562 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1559, UInt<1>(0h1), "") : assert_57
node _T_1563 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1563 :
node _T_1564 = asUInt(reset)
node _T_1565 = eq(_T_1564, UInt<1>(0h0))
when _T_1565 :
node _T_1566 = eq(source_ok_1, UInt<1>(0h0))
when _T_1566 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1567 = asUInt(reset)
node _T_1568 = eq(_T_1567, UInt<1>(0h0))
when _T_1568 :
node _T_1569 = eq(sink_ok, UInt<1>(0h0))
when _T_1569 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1570 = geq(io.in.d.bits.size, UInt<3>(0h4))
node _T_1571 = asUInt(reset)
node _T_1572 = eq(_T_1571, UInt<1>(0h0))
when _T_1572 :
node _T_1573 = eq(_T_1570, UInt<1>(0h0))
when _T_1573 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1570, UInt<1>(0h1), "") : assert_60
node _T_1574 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1575 = asUInt(reset)
node _T_1576 = eq(_T_1575, UInt<1>(0h0))
when _T_1576 :
node _T_1577 = eq(_T_1574, UInt<1>(0h0))
when _T_1577 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1574, UInt<1>(0h1), "") : assert_61
node _T_1578 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1579 = asUInt(reset)
node _T_1580 = eq(_T_1579, UInt<1>(0h0))
when _T_1580 :
node _T_1581 = eq(_T_1578, UInt<1>(0h0))
when _T_1581 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1578, UInt<1>(0h1), "") : assert_62
node _T_1582 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1583 = asUInt(reset)
node _T_1584 = eq(_T_1583, UInt<1>(0h0))
when _T_1584 :
node _T_1585 = eq(_T_1582, UInt<1>(0h0))
when _T_1585 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1582, UInt<1>(0h1), "") : assert_63
node _T_1586 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1587 = or(UInt<1>(0h1), _T_1586)
node _T_1588 = asUInt(reset)
node _T_1589 = eq(_T_1588, UInt<1>(0h0))
when _T_1589 :
node _T_1590 = eq(_T_1587, UInt<1>(0h0))
when _T_1590 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1587, UInt<1>(0h1), "") : assert_64
node _T_1591 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1591 :
node _T_1592 = asUInt(reset)
node _T_1593 = eq(_T_1592, UInt<1>(0h0))
when _T_1593 :
node _T_1594 = eq(source_ok_1, UInt<1>(0h0))
when _T_1594 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1595 = asUInt(reset)
node _T_1596 = eq(_T_1595, UInt<1>(0h0))
when _T_1596 :
node _T_1597 = eq(sink_ok, UInt<1>(0h0))
when _T_1597 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1598 = geq(io.in.d.bits.size, UInt<3>(0h4))
node _T_1599 = asUInt(reset)
node _T_1600 = eq(_T_1599, UInt<1>(0h0))
when _T_1600 :
node _T_1601 = eq(_T_1598, UInt<1>(0h0))
when _T_1601 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1598, UInt<1>(0h1), "") : assert_67
node _T_1602 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1603 = asUInt(reset)
node _T_1604 = eq(_T_1603, UInt<1>(0h0))
when _T_1604 :
node _T_1605 = eq(_T_1602, UInt<1>(0h0))
when _T_1605 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1602, UInt<1>(0h1), "") : assert_68
node _T_1606 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1607 = asUInt(reset)
node _T_1608 = eq(_T_1607, UInt<1>(0h0))
when _T_1608 :
node _T_1609 = eq(_T_1606, UInt<1>(0h0))
when _T_1609 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1606, UInt<1>(0h1), "") : assert_69
node _T_1610 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1611 = or(_T_1610, io.in.d.bits.corrupt)
node _T_1612 = asUInt(reset)
node _T_1613 = eq(_T_1612, UInt<1>(0h0))
when _T_1613 :
node _T_1614 = eq(_T_1611, UInt<1>(0h0))
when _T_1614 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1611, UInt<1>(0h1), "") : assert_70
node _T_1615 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1616 = or(UInt<1>(0h1), _T_1615)
node _T_1617 = asUInt(reset)
node _T_1618 = eq(_T_1617, UInt<1>(0h0))
when _T_1618 :
node _T_1619 = eq(_T_1616, UInt<1>(0h0))
when _T_1619 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1616, UInt<1>(0h1), "") : assert_71
node _T_1620 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1620 :
node _T_1621 = asUInt(reset)
node _T_1622 = eq(_T_1621, UInt<1>(0h0))
when _T_1622 :
node _T_1623 = eq(source_ok_1, UInt<1>(0h0))
when _T_1623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1624 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1625 = asUInt(reset)
node _T_1626 = eq(_T_1625, UInt<1>(0h0))
when _T_1626 :
node _T_1627 = eq(_T_1624, UInt<1>(0h0))
when _T_1627 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1624, UInt<1>(0h1), "") : assert_73
node _T_1628 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1629 = asUInt(reset)
node _T_1630 = eq(_T_1629, UInt<1>(0h0))
when _T_1630 :
node _T_1631 = eq(_T_1628, UInt<1>(0h0))
when _T_1631 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1628, UInt<1>(0h1), "") : assert_74
node _T_1632 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1633 = or(UInt<1>(0h1), _T_1632)
node _T_1634 = asUInt(reset)
node _T_1635 = eq(_T_1634, UInt<1>(0h0))
when _T_1635 :
node _T_1636 = eq(_T_1633, UInt<1>(0h0))
when _T_1636 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1633, UInt<1>(0h1), "") : assert_75
node _T_1637 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1637 :
node _T_1638 = asUInt(reset)
node _T_1639 = eq(_T_1638, UInt<1>(0h0))
when _T_1639 :
node _T_1640 = eq(source_ok_1, UInt<1>(0h0))
when _T_1640 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1641 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1642 = asUInt(reset)
node _T_1643 = eq(_T_1642, UInt<1>(0h0))
when _T_1643 :
node _T_1644 = eq(_T_1641, UInt<1>(0h0))
when _T_1644 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1641, UInt<1>(0h1), "") : assert_77
node _T_1645 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1646 = or(_T_1645, io.in.d.bits.corrupt)
node _T_1647 = asUInt(reset)
node _T_1648 = eq(_T_1647, UInt<1>(0h0))
when _T_1648 :
node _T_1649 = eq(_T_1646, UInt<1>(0h0))
when _T_1649 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1646, UInt<1>(0h1), "") : assert_78
node _T_1650 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1651 = or(UInt<1>(0h1), _T_1650)
node _T_1652 = asUInt(reset)
node _T_1653 = eq(_T_1652, UInt<1>(0h0))
when _T_1653 :
node _T_1654 = eq(_T_1651, UInt<1>(0h0))
when _T_1654 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1651, UInt<1>(0h1), "") : assert_79
node _T_1655 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1655 :
node _T_1656 = asUInt(reset)
node _T_1657 = eq(_T_1656, UInt<1>(0h0))
when _T_1657 :
node _T_1658 = eq(source_ok_1, UInt<1>(0h0))
when _T_1658 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1659 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1660 = asUInt(reset)
node _T_1661 = eq(_T_1660, UInt<1>(0h0))
when _T_1661 :
node _T_1662 = eq(_T_1659, UInt<1>(0h0))
when _T_1662 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1659, UInt<1>(0h1), "") : assert_81
node _T_1663 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1664 = asUInt(reset)
node _T_1665 = eq(_T_1664, UInt<1>(0h0))
when _T_1665 :
node _T_1666 = eq(_T_1663, UInt<1>(0h0))
when _T_1666 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1663, UInt<1>(0h1), "") : assert_82
node _T_1667 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1668 = or(UInt<1>(0h1), _T_1667)
node _T_1669 = asUInt(reset)
node _T_1670 = eq(_T_1669, UInt<1>(0h0))
when _T_1670 :
node _T_1671 = eq(_T_1668, UInt<1>(0h0))
when _T_1671 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1668, UInt<1>(0h1), "") : assert_83
when io.in.b.valid :
node _T_1672 = leq(io.in.b.bits.opcode, UInt<3>(0h6))
node _T_1673 = asUInt(reset)
node _T_1674 = eq(_T_1673, UInt<1>(0h0))
when _T_1674 :
node _T_1675 = eq(_T_1672, UInt<1>(0h0))
when _T_1675 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1672, UInt<1>(0h1), "") : assert_84
node _T_1676 = eq(io.in.b.bits.source, UInt<5>(0h10))
node _T_1677 = eq(_T_1676, UInt<1>(0h0))
node _T_1678 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1679 = cvt(_T_1678)
node _T_1680 = and(_T_1679, asSInt(UInt<1>(0h0)))
node _T_1681 = asSInt(_T_1680)
node _T_1682 = eq(_T_1681, asSInt(UInt<1>(0h0)))
node _T_1683 = or(_T_1677, _T_1682)
node _uncommonBits_T_44 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0)
node _T_1684 = shr(io.in.b.bits.source, 2)
node _T_1685 = eq(_T_1684, UInt<1>(0h0))
node _T_1686 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_1687 = and(_T_1685, _T_1686)
node _T_1688 = leq(uncommonBits_44, UInt<2>(0h3))
node _T_1689 = and(_T_1687, _T_1688)
node _T_1690 = eq(_T_1689, UInt<1>(0h0))
node _T_1691 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1692 = cvt(_T_1691)
node _T_1693 = and(_T_1692, asSInt(UInt<1>(0h0)))
node _T_1694 = asSInt(_T_1693)
node _T_1695 = eq(_T_1694, asSInt(UInt<1>(0h0)))
node _T_1696 = or(_T_1690, _T_1695)
node _uncommonBits_T_45 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0)
node _T_1697 = shr(io.in.b.bits.source, 2)
node _T_1698 = eq(_T_1697, UInt<1>(0h1))
node _T_1699 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_1700 = and(_T_1698, _T_1699)
node _T_1701 = leq(uncommonBits_45, UInt<2>(0h3))
node _T_1702 = and(_T_1700, _T_1701)
node _T_1703 = eq(_T_1702, UInt<1>(0h0))
node _T_1704 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1705 = cvt(_T_1704)
node _T_1706 = and(_T_1705, asSInt(UInt<1>(0h0)))
node _T_1707 = asSInt(_T_1706)
node _T_1708 = eq(_T_1707, asSInt(UInt<1>(0h0)))
node _T_1709 = or(_T_1703, _T_1708)
node _uncommonBits_T_46 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0)
node _T_1710 = shr(io.in.b.bits.source, 2)
node _T_1711 = eq(_T_1710, UInt<2>(0h2))
node _T_1712 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_1713 = and(_T_1711, _T_1712)
node _T_1714 = leq(uncommonBits_46, UInt<2>(0h3))
node _T_1715 = and(_T_1713, _T_1714)
node _T_1716 = eq(_T_1715, UInt<1>(0h0))
node _T_1717 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1718 = cvt(_T_1717)
node _T_1719 = and(_T_1718, asSInt(UInt<1>(0h0)))
node _T_1720 = asSInt(_T_1719)
node _T_1721 = eq(_T_1720, asSInt(UInt<1>(0h0)))
node _T_1722 = or(_T_1716, _T_1721)
node _uncommonBits_T_47 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0)
node _T_1723 = shr(io.in.b.bits.source, 2)
node _T_1724 = eq(_T_1723, UInt<2>(0h3))
node _T_1725 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_1726 = and(_T_1724, _T_1725)
node _T_1727 = leq(uncommonBits_47, UInt<2>(0h3))
node _T_1728 = and(_T_1726, _T_1727)
node _T_1729 = eq(_T_1728, UInt<1>(0h0))
node _T_1730 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1731 = cvt(_T_1730)
node _T_1732 = and(_T_1731, asSInt(UInt<1>(0h0)))
node _T_1733 = asSInt(_T_1732)
node _T_1734 = eq(_T_1733, asSInt(UInt<1>(0h0)))
node _T_1735 = or(_T_1729, _T_1734)
node _T_1736 = eq(io.in.b.bits.source, UInt<7>(0h4c))
node _T_1737 = eq(_T_1736, UInt<1>(0h0))
node _T_1738 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1739 = cvt(_T_1738)
node _T_1740 = and(_T_1739, asSInt(UInt<1>(0h0)))
node _T_1741 = asSInt(_T_1740)
node _T_1742 = eq(_T_1741, asSInt(UInt<1>(0h0)))
node _T_1743 = or(_T_1737, _T_1742)
node _T_1744 = eq(io.in.b.bits.source, UInt<7>(0h4e))
node _T_1745 = eq(_T_1744, UInt<1>(0h0))
node _T_1746 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1747 = cvt(_T_1746)
node _T_1748 = and(_T_1747, asSInt(UInt<1>(0h0)))
node _T_1749 = asSInt(_T_1748)
node _T_1750 = eq(_T_1749, asSInt(UInt<1>(0h0)))
node _T_1751 = or(_T_1745, _T_1750)
node _T_1752 = eq(io.in.b.bits.source, UInt<7>(0h48))
node _T_1753 = eq(_T_1752, UInt<1>(0h0))
node _T_1754 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1755 = cvt(_T_1754)
node _T_1756 = and(_T_1755, asSInt(UInt<1>(0h0)))
node _T_1757 = asSInt(_T_1756)
node _T_1758 = eq(_T_1757, asSInt(UInt<1>(0h0)))
node _T_1759 = or(_T_1753, _T_1758)
node _T_1760 = eq(io.in.b.bits.source, UInt<7>(0h4a))
node _T_1761 = eq(_T_1760, UInt<1>(0h0))
node _T_1762 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1763 = cvt(_T_1762)
node _T_1764 = and(_T_1763, asSInt(UInt<1>(0h0)))
node _T_1765 = asSInt(_T_1764)
node _T_1766 = eq(_T_1765, asSInt(UInt<1>(0h0)))
node _T_1767 = or(_T_1761, _T_1766)
node _T_1768 = eq(io.in.b.bits.source, UInt<7>(0h44))
node _T_1769 = eq(_T_1768, UInt<1>(0h0))
node _T_1770 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1771 = cvt(_T_1770)
node _T_1772 = and(_T_1771, asSInt(UInt<1>(0h0)))
node _T_1773 = asSInt(_T_1772)
node _T_1774 = eq(_T_1773, asSInt(UInt<1>(0h0)))
node _T_1775 = or(_T_1769, _T_1774)
node _T_1776 = eq(io.in.b.bits.source, UInt<7>(0h46))
node _T_1777 = eq(_T_1776, UInt<1>(0h0))
node _T_1778 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1779 = cvt(_T_1778)
node _T_1780 = and(_T_1779, asSInt(UInt<1>(0h0)))
node _T_1781 = asSInt(_T_1780)
node _T_1782 = eq(_T_1781, asSInt(UInt<1>(0h0)))
node _T_1783 = or(_T_1777, _T_1782)
node _T_1784 = eq(io.in.b.bits.source, UInt<7>(0h40))
node _T_1785 = eq(_T_1784, UInt<1>(0h0))
node _T_1786 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1787 = cvt(_T_1786)
node _T_1788 = and(_T_1787, asSInt(UInt<1>(0h0)))
node _T_1789 = asSInt(_T_1788)
node _T_1790 = eq(_T_1789, asSInt(UInt<1>(0h0)))
node _T_1791 = or(_T_1785, _T_1790)
node _T_1792 = eq(io.in.b.bits.source, UInt<7>(0h42))
node _T_1793 = eq(_T_1792, UInt<1>(0h0))
node _T_1794 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1795 = cvt(_T_1794)
node _T_1796 = and(_T_1795, asSInt(UInt<1>(0h0)))
node _T_1797 = asSInt(_T_1796)
node _T_1798 = eq(_T_1797, asSInt(UInt<1>(0h0)))
node _T_1799 = or(_T_1793, _T_1798)
node _T_1800 = eq(io.in.b.bits.source, UInt<6>(0h3c))
node _T_1801 = eq(_T_1800, UInt<1>(0h0))
node _T_1802 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1803 = cvt(_T_1802)
node _T_1804 = and(_T_1803, asSInt(UInt<1>(0h0)))
node _T_1805 = asSInt(_T_1804)
node _T_1806 = eq(_T_1805, asSInt(UInt<1>(0h0)))
node _T_1807 = or(_T_1801, _T_1806)
node _T_1808 = eq(io.in.b.bits.source, UInt<6>(0h3e))
node _T_1809 = eq(_T_1808, UInt<1>(0h0))
node _T_1810 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1811 = cvt(_T_1810)
node _T_1812 = and(_T_1811, asSInt(UInt<1>(0h0)))
node _T_1813 = asSInt(_T_1812)
node _T_1814 = eq(_T_1813, asSInt(UInt<1>(0h0)))
node _T_1815 = or(_T_1809, _T_1814)
node _T_1816 = eq(io.in.b.bits.source, UInt<6>(0h38))
node _T_1817 = eq(_T_1816, UInt<1>(0h0))
node _T_1818 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1819 = cvt(_T_1818)
node _T_1820 = and(_T_1819, asSInt(UInt<1>(0h0)))
node _T_1821 = asSInt(_T_1820)
node _T_1822 = eq(_T_1821, asSInt(UInt<1>(0h0)))
node _T_1823 = or(_T_1817, _T_1822)
node _T_1824 = eq(io.in.b.bits.source, UInt<6>(0h3a))
node _T_1825 = eq(_T_1824, UInt<1>(0h0))
node _T_1826 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1827 = cvt(_T_1826)
node _T_1828 = and(_T_1827, asSInt(UInt<1>(0h0)))
node _T_1829 = asSInt(_T_1828)
node _T_1830 = eq(_T_1829, asSInt(UInt<1>(0h0)))
node _T_1831 = or(_T_1825, _T_1830)
node _T_1832 = eq(io.in.b.bits.source, UInt<6>(0h34))
node _T_1833 = eq(_T_1832, UInt<1>(0h0))
node _T_1834 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1835 = cvt(_T_1834)
node _T_1836 = and(_T_1835, asSInt(UInt<1>(0h0)))
node _T_1837 = asSInt(_T_1836)
node _T_1838 = eq(_T_1837, asSInt(UInt<1>(0h0)))
node _T_1839 = or(_T_1833, _T_1838)
node _T_1840 = eq(io.in.b.bits.source, UInt<6>(0h36))
node _T_1841 = eq(_T_1840, UInt<1>(0h0))
node _T_1842 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1843 = cvt(_T_1842)
node _T_1844 = and(_T_1843, asSInt(UInt<1>(0h0)))
node _T_1845 = asSInt(_T_1844)
node _T_1846 = eq(_T_1845, asSInt(UInt<1>(0h0)))
node _T_1847 = or(_T_1841, _T_1846)
node _T_1848 = eq(io.in.b.bits.source, UInt<6>(0h30))
node _T_1849 = eq(_T_1848, UInt<1>(0h0))
node _T_1850 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1851 = cvt(_T_1850)
node _T_1852 = and(_T_1851, asSInt(UInt<1>(0h0)))
node _T_1853 = asSInt(_T_1852)
node _T_1854 = eq(_T_1853, asSInt(UInt<1>(0h0)))
node _T_1855 = or(_T_1849, _T_1854)
node _T_1856 = eq(io.in.b.bits.source, UInt<6>(0h32))
node _T_1857 = eq(_T_1856, UInt<1>(0h0))
node _T_1858 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1859 = cvt(_T_1858)
node _T_1860 = and(_T_1859, asSInt(UInt<1>(0h0)))
node _T_1861 = asSInt(_T_1860)
node _T_1862 = eq(_T_1861, asSInt(UInt<1>(0h0)))
node _T_1863 = or(_T_1857, _T_1862)
node _T_1864 = eq(io.in.b.bits.source, UInt<6>(0h2c))
node _T_1865 = eq(_T_1864, UInt<1>(0h0))
node _T_1866 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1867 = cvt(_T_1866)
node _T_1868 = and(_T_1867, asSInt(UInt<1>(0h0)))
node _T_1869 = asSInt(_T_1868)
node _T_1870 = eq(_T_1869, asSInt(UInt<1>(0h0)))
node _T_1871 = or(_T_1865, _T_1870)
node _T_1872 = eq(io.in.b.bits.source, UInt<6>(0h2e))
node _T_1873 = eq(_T_1872, UInt<1>(0h0))
node _T_1874 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1875 = cvt(_T_1874)
node _T_1876 = and(_T_1875, asSInt(UInt<1>(0h0)))
node _T_1877 = asSInt(_T_1876)
node _T_1878 = eq(_T_1877, asSInt(UInt<1>(0h0)))
node _T_1879 = or(_T_1873, _T_1878)
node _T_1880 = eq(io.in.b.bits.source, UInt<6>(0h28))
node _T_1881 = eq(_T_1880, UInt<1>(0h0))
node _T_1882 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1883 = cvt(_T_1882)
node _T_1884 = and(_T_1883, asSInt(UInt<1>(0h0)))
node _T_1885 = asSInt(_T_1884)
node _T_1886 = eq(_T_1885, asSInt(UInt<1>(0h0)))
node _T_1887 = or(_T_1881, _T_1886)
node _T_1888 = eq(io.in.b.bits.source, UInt<6>(0h2a))
node _T_1889 = eq(_T_1888, UInt<1>(0h0))
node _T_1890 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1891 = cvt(_T_1890)
node _T_1892 = and(_T_1891, asSInt(UInt<1>(0h0)))
node _T_1893 = asSInt(_T_1892)
node _T_1894 = eq(_T_1893, asSInt(UInt<1>(0h0)))
node _T_1895 = or(_T_1889, _T_1894)
node _T_1896 = eq(io.in.b.bits.source, UInt<6>(0h24))
node _T_1897 = eq(_T_1896, UInt<1>(0h0))
node _T_1898 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1899 = cvt(_T_1898)
node _T_1900 = and(_T_1899, asSInt(UInt<1>(0h0)))
node _T_1901 = asSInt(_T_1900)
node _T_1902 = eq(_T_1901, asSInt(UInt<1>(0h0)))
node _T_1903 = or(_T_1897, _T_1902)
node _T_1904 = eq(io.in.b.bits.source, UInt<6>(0h26))
node _T_1905 = eq(_T_1904, UInt<1>(0h0))
node _T_1906 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1907 = cvt(_T_1906)
node _T_1908 = and(_T_1907, asSInt(UInt<1>(0h0)))
node _T_1909 = asSInt(_T_1908)
node _T_1910 = eq(_T_1909, asSInt(UInt<1>(0h0)))
node _T_1911 = or(_T_1905, _T_1910)
node _T_1912 = eq(io.in.b.bits.source, UInt<6>(0h20))
node _T_1913 = eq(_T_1912, UInt<1>(0h0))
node _T_1914 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1915 = cvt(_T_1914)
node _T_1916 = and(_T_1915, asSInt(UInt<1>(0h0)))
node _T_1917 = asSInt(_T_1916)
node _T_1918 = eq(_T_1917, asSInt(UInt<1>(0h0)))
node _T_1919 = or(_T_1913, _T_1918)
node _T_1920 = eq(io.in.b.bits.source, UInt<6>(0h22))
node _T_1921 = eq(_T_1920, UInt<1>(0h0))
node _T_1922 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1923 = cvt(_T_1922)
node _T_1924 = and(_T_1923, asSInt(UInt<1>(0h0)))
node _T_1925 = asSInt(_T_1924)
node _T_1926 = eq(_T_1925, asSInt(UInt<1>(0h0)))
node _T_1927 = or(_T_1921, _T_1926)
node _T_1928 = and(_T_1683, _T_1696)
node _T_1929 = and(_T_1928, _T_1709)
node _T_1930 = and(_T_1929, _T_1722)
node _T_1931 = and(_T_1930, _T_1735)
node _T_1932 = and(_T_1931, _T_1743)
node _T_1933 = and(_T_1932, _T_1751)
node _T_1934 = and(_T_1933, _T_1759)
node _T_1935 = and(_T_1934, _T_1767)
node _T_1936 = and(_T_1935, _T_1775)
node _T_1937 = and(_T_1936, _T_1783)
node _T_1938 = and(_T_1937, _T_1791)
node _T_1939 = and(_T_1938, _T_1799)
node _T_1940 = and(_T_1939, _T_1807)
node _T_1941 = and(_T_1940, _T_1815)
node _T_1942 = and(_T_1941, _T_1823)
node _T_1943 = and(_T_1942, _T_1831)
node _T_1944 = and(_T_1943, _T_1839)
node _T_1945 = and(_T_1944, _T_1847)
node _T_1946 = and(_T_1945, _T_1855)
node _T_1947 = and(_T_1946, _T_1863)
node _T_1948 = and(_T_1947, _T_1871)
node _T_1949 = and(_T_1948, _T_1879)
node _T_1950 = and(_T_1949, _T_1887)
node _T_1951 = and(_T_1950, _T_1895)
node _T_1952 = and(_T_1951, _T_1903)
node _T_1953 = and(_T_1952, _T_1911)
node _T_1954 = and(_T_1953, _T_1919)
node _T_1955 = and(_T_1954, _T_1927)
node _T_1956 = asUInt(reset)
node _T_1957 = eq(_T_1956, UInt<1>(0h0))
when _T_1957 :
node _T_1958 = eq(_T_1955, UInt<1>(0h0))
when _T_1958 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1955, UInt<1>(0h1), "") : assert_85
node _address_ok_T = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _address_ok_T_1 = cvt(_address_ok_T)
node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<17>(0h100c0)))
node _address_ok_T_3 = asSInt(_address_ok_T_2)
node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0)))
node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _address_ok_T_6 = cvt(_address_ok_T_5)
node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<29>(0h100000c0)))
node _address_ok_T_8 = asSInt(_address_ok_T_7)
node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE : UInt<1>[2]
connect _address_ok_WIRE[0], _address_ok_T_4
connect _address_ok_WIRE[1], _address_ok_T_9
node address_ok = or(_address_ok_WIRE[0], _address_ok_WIRE[1])
node _is_aligned_mask_T_2 = dshl(UInt<6>(0h3f), io.in.b.bits.size)
node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 5, 0)
node is_aligned_mask_1 = not(_is_aligned_mask_T_3)
node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1)
node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0))
node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<4>(0h0))
node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0)
node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1)
node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 3, 0)
node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1))
node mask_sub_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<3>(0h4))
node mask_sub_sub_sub_size_1 = bits(mask_sizeOH_1, 3, 3)
node mask_sub_sub_sub_bit_1 = bits(io.in.b.bits.address, 3, 3)
node mask_sub_sub_sub_nbit_1 = eq(mask_sub_sub_sub_bit_1, UInt<1>(0h0))
node mask_sub_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit_1)
node _mask_sub_sub_sub_acc_T_2 = and(mask_sub_sub_sub_size_1, mask_sub_sub_sub_0_2_1)
node mask_sub_sub_sub_0_1_1 = or(mask_sub_sub_sub_sub_0_1_1, _mask_sub_sub_sub_acc_T_2)
node mask_sub_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_sub_bit_1)
node _mask_sub_sub_sub_acc_T_3 = and(mask_sub_sub_sub_size_1, mask_sub_sub_sub_1_2_1)
node mask_sub_sub_sub_1_1_1 = or(mask_sub_sub_sub_sub_0_1_1, _mask_sub_sub_sub_acc_T_3)
node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2)
node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2)
node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0))
node mask_sub_sub_0_2_1 = and(mask_sub_sub_sub_0_2_1, mask_sub_sub_nbit_1)
node _mask_sub_sub_acc_T_4 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1)
node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_4)
node mask_sub_sub_1_2_1 = and(mask_sub_sub_sub_0_2_1, mask_sub_sub_bit_1)
node _mask_sub_sub_acc_T_5 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1)
node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_5)
node mask_sub_sub_2_2_1 = and(mask_sub_sub_sub_1_2_1, mask_sub_sub_nbit_1)
node _mask_sub_sub_acc_T_6 = and(mask_sub_sub_size_1, mask_sub_sub_2_2_1)
node mask_sub_sub_2_1_1 = or(mask_sub_sub_sub_1_1_1, _mask_sub_sub_acc_T_6)
node mask_sub_sub_3_2_1 = and(mask_sub_sub_sub_1_2_1, mask_sub_sub_bit_1)
node _mask_sub_sub_acc_T_7 = and(mask_sub_sub_size_1, mask_sub_sub_3_2_1)
node mask_sub_sub_3_1_1 = or(mask_sub_sub_sub_1_1_1, _mask_sub_sub_acc_T_7)
node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1)
node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1)
node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0))
node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_8 = and(mask_sub_size_1, mask_sub_0_2_1)
node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_8)
node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_9 = and(mask_sub_size_1, mask_sub_1_2_1)
node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_9)
node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_10 = and(mask_sub_size_1, mask_sub_2_2_1)
node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_10)
node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_11 = and(mask_sub_size_1, mask_sub_3_2_1)
node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_11)
node mask_sub_4_2_1 = and(mask_sub_sub_2_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_12 = and(mask_sub_size_1, mask_sub_4_2_1)
node mask_sub_4_1_1 = or(mask_sub_sub_2_1_1, _mask_sub_acc_T_12)
node mask_sub_5_2_1 = and(mask_sub_sub_2_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_13 = and(mask_sub_size_1, mask_sub_5_2_1)
node mask_sub_5_1_1 = or(mask_sub_sub_2_1_1, _mask_sub_acc_T_13)
node mask_sub_6_2_1 = and(mask_sub_sub_3_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_14 = and(mask_sub_size_1, mask_sub_6_2_1)
node mask_sub_6_1_1 = or(mask_sub_sub_3_1_1, _mask_sub_acc_T_14)
node mask_sub_7_2_1 = and(mask_sub_sub_3_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_15 = and(mask_sub_size_1, mask_sub_7_2_1)
node mask_sub_7_1_1 = or(mask_sub_sub_3_1_1, _mask_sub_acc_T_15)
node mask_size_1 = bits(mask_sizeOH_1, 0, 0)
node mask_bit_1 = bits(io.in.b.bits.address, 0, 0)
node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0))
node mask_eq_16 = and(mask_sub_0_2_1, mask_nbit_1)
node _mask_acc_T_16 = and(mask_size_1, mask_eq_16)
node mask_acc_16 = or(mask_sub_0_1_1, _mask_acc_T_16)
node mask_eq_17 = and(mask_sub_0_2_1, mask_bit_1)
node _mask_acc_T_17 = and(mask_size_1, mask_eq_17)
node mask_acc_17 = or(mask_sub_0_1_1, _mask_acc_T_17)
node mask_eq_18 = and(mask_sub_1_2_1, mask_nbit_1)
node _mask_acc_T_18 = and(mask_size_1, mask_eq_18)
node mask_acc_18 = or(mask_sub_1_1_1, _mask_acc_T_18)
node mask_eq_19 = and(mask_sub_1_2_1, mask_bit_1)
node _mask_acc_T_19 = and(mask_size_1, mask_eq_19)
node mask_acc_19 = or(mask_sub_1_1_1, _mask_acc_T_19)
node mask_eq_20 = and(mask_sub_2_2_1, mask_nbit_1)
node _mask_acc_T_20 = and(mask_size_1, mask_eq_20)
node mask_acc_20 = or(mask_sub_2_1_1, _mask_acc_T_20)
node mask_eq_21 = and(mask_sub_2_2_1, mask_bit_1)
node _mask_acc_T_21 = and(mask_size_1, mask_eq_21)
node mask_acc_21 = or(mask_sub_2_1_1, _mask_acc_T_21)
node mask_eq_22 = and(mask_sub_3_2_1, mask_nbit_1)
node _mask_acc_T_22 = and(mask_size_1, mask_eq_22)
node mask_acc_22 = or(mask_sub_3_1_1, _mask_acc_T_22)
node mask_eq_23 = and(mask_sub_3_2_1, mask_bit_1)
node _mask_acc_T_23 = and(mask_size_1, mask_eq_23)
node mask_acc_23 = or(mask_sub_3_1_1, _mask_acc_T_23)
node mask_eq_24 = and(mask_sub_4_2_1, mask_nbit_1)
node _mask_acc_T_24 = and(mask_size_1, mask_eq_24)
node mask_acc_24 = or(mask_sub_4_1_1, _mask_acc_T_24)
node mask_eq_25 = and(mask_sub_4_2_1, mask_bit_1)
node _mask_acc_T_25 = and(mask_size_1, mask_eq_25)
node mask_acc_25 = or(mask_sub_4_1_1, _mask_acc_T_25)
node mask_eq_26 = and(mask_sub_5_2_1, mask_nbit_1)
node _mask_acc_T_26 = and(mask_size_1, mask_eq_26)
node mask_acc_26 = or(mask_sub_5_1_1, _mask_acc_T_26)
node mask_eq_27 = and(mask_sub_5_2_1, mask_bit_1)
node _mask_acc_T_27 = and(mask_size_1, mask_eq_27)
node mask_acc_27 = or(mask_sub_5_1_1, _mask_acc_T_27)
node mask_eq_28 = and(mask_sub_6_2_1, mask_nbit_1)
node _mask_acc_T_28 = and(mask_size_1, mask_eq_28)
node mask_acc_28 = or(mask_sub_6_1_1, _mask_acc_T_28)
node mask_eq_29 = and(mask_sub_6_2_1, mask_bit_1)
node _mask_acc_T_29 = and(mask_size_1, mask_eq_29)
node mask_acc_29 = or(mask_sub_6_1_1, _mask_acc_T_29)
node mask_eq_30 = and(mask_sub_7_2_1, mask_nbit_1)
node _mask_acc_T_30 = and(mask_size_1, mask_eq_30)
node mask_acc_30 = or(mask_sub_7_1_1, _mask_acc_T_30)
node mask_eq_31 = and(mask_sub_7_2_1, mask_bit_1)
node _mask_acc_T_31 = and(mask_size_1, mask_eq_31)
node mask_acc_31 = or(mask_sub_7_1_1, _mask_acc_T_31)
node mask_lo_lo_lo_1 = cat(mask_acc_17, mask_acc_16)
node mask_lo_lo_hi_1 = cat(mask_acc_19, mask_acc_18)
node mask_lo_lo_1 = cat(mask_lo_lo_hi_1, mask_lo_lo_lo_1)
node mask_lo_hi_lo_1 = cat(mask_acc_21, mask_acc_20)
node mask_lo_hi_hi_1 = cat(mask_acc_23, mask_acc_22)
node mask_lo_hi_1 = cat(mask_lo_hi_hi_1, mask_lo_hi_lo_1)
node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1)
node mask_hi_lo_lo_1 = cat(mask_acc_25, mask_acc_24)
node mask_hi_lo_hi_1 = cat(mask_acc_27, mask_acc_26)
node mask_hi_lo_1 = cat(mask_hi_lo_hi_1, mask_hi_lo_lo_1)
node mask_hi_hi_lo_1 = cat(mask_acc_29, mask_acc_28)
node mask_hi_hi_hi_1 = cat(mask_acc_31, mask_acc_30)
node mask_hi_hi_1 = cat(mask_hi_hi_hi_1, mask_hi_hi_lo_1)
node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1)
node mask_1 = cat(mask_hi_1, mask_lo_1)
node _legal_source_T = eq(io.in.b.bits.source, UInt<5>(0h10))
node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<2>(0h0))
node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 1, 0)
node _legal_source_T_1 = shr(io.in.b.bits.source, 2)
node _legal_source_T_2 = eq(_legal_source_T_1, UInt<1>(0h0))
node _legal_source_T_3 = leq(UInt<1>(0h0), legal_source_uncommonBits)
node _legal_source_T_4 = and(_legal_source_T_2, _legal_source_T_3)
node _legal_source_T_5 = leq(legal_source_uncommonBits, UInt<2>(0h3))
node _legal_source_T_6 = and(_legal_source_T_4, _legal_source_T_5)
node _legal_source_uncommonBits_T_1 = or(io.in.b.bits.source, UInt<2>(0h0))
node legal_source_uncommonBits_1 = bits(_legal_source_uncommonBits_T_1, 1, 0)
node _legal_source_T_7 = shr(io.in.b.bits.source, 2)
node _legal_source_T_8 = eq(_legal_source_T_7, UInt<1>(0h1))
node _legal_source_T_9 = leq(UInt<1>(0h0), legal_source_uncommonBits_1)
node _legal_source_T_10 = and(_legal_source_T_8, _legal_source_T_9)
node _legal_source_T_11 = leq(legal_source_uncommonBits_1, UInt<2>(0h3))
node _legal_source_T_12 = and(_legal_source_T_10, _legal_source_T_11)
node _legal_source_uncommonBits_T_2 = or(io.in.b.bits.source, UInt<2>(0h0))
node legal_source_uncommonBits_2 = bits(_legal_source_uncommonBits_T_2, 1, 0)
node _legal_source_T_13 = shr(io.in.b.bits.source, 2)
node _legal_source_T_14 = eq(_legal_source_T_13, UInt<2>(0h2))
node _legal_source_T_15 = leq(UInt<1>(0h0), legal_source_uncommonBits_2)
node _legal_source_T_16 = and(_legal_source_T_14, _legal_source_T_15)
node _legal_source_T_17 = leq(legal_source_uncommonBits_2, UInt<2>(0h3))
node _legal_source_T_18 = and(_legal_source_T_16, _legal_source_T_17)
node _legal_source_uncommonBits_T_3 = or(io.in.b.bits.source, UInt<2>(0h0))
node legal_source_uncommonBits_3 = bits(_legal_source_uncommonBits_T_3, 1, 0)
node _legal_source_T_19 = shr(io.in.b.bits.source, 2)
node _legal_source_T_20 = eq(_legal_source_T_19, UInt<2>(0h3))
node _legal_source_T_21 = leq(UInt<1>(0h0), legal_source_uncommonBits_3)
node _legal_source_T_22 = and(_legal_source_T_20, _legal_source_T_21)
node _legal_source_T_23 = leq(legal_source_uncommonBits_3, UInt<2>(0h3))
node _legal_source_T_24 = and(_legal_source_T_22, _legal_source_T_23)
node _legal_source_T_25 = eq(io.in.b.bits.source, UInt<7>(0h4c))
node _legal_source_T_26 = eq(io.in.b.bits.source, UInt<7>(0h4e))
node _legal_source_T_27 = eq(io.in.b.bits.source, UInt<7>(0h48))
node _legal_source_T_28 = eq(io.in.b.bits.source, UInt<7>(0h4a))
node _legal_source_T_29 = eq(io.in.b.bits.source, UInt<7>(0h44))
node _legal_source_T_30 = eq(io.in.b.bits.source, UInt<7>(0h46))
node _legal_source_T_31 = eq(io.in.b.bits.source, UInt<7>(0h40))
node _legal_source_T_32 = eq(io.in.b.bits.source, UInt<7>(0h42))
node _legal_source_T_33 = eq(io.in.b.bits.source, UInt<6>(0h3c))
node _legal_source_T_34 = eq(io.in.b.bits.source, UInt<6>(0h3e))
node _legal_source_T_35 = eq(io.in.b.bits.source, UInt<6>(0h38))
node _legal_source_T_36 = eq(io.in.b.bits.source, UInt<6>(0h3a))
node _legal_source_T_37 = eq(io.in.b.bits.source, UInt<6>(0h34))
node _legal_source_T_38 = eq(io.in.b.bits.source, UInt<6>(0h36))
node _legal_source_T_39 = eq(io.in.b.bits.source, UInt<6>(0h30))
node _legal_source_T_40 = eq(io.in.b.bits.source, UInt<6>(0h32))
node _legal_source_T_41 = eq(io.in.b.bits.source, UInt<6>(0h2c))
node _legal_source_T_42 = eq(io.in.b.bits.source, UInt<6>(0h2e))
node _legal_source_T_43 = eq(io.in.b.bits.source, UInt<6>(0h28))
node _legal_source_T_44 = eq(io.in.b.bits.source, UInt<6>(0h2a))
node _legal_source_T_45 = eq(io.in.b.bits.source, UInt<6>(0h24))
node _legal_source_T_46 = eq(io.in.b.bits.source, UInt<6>(0h26))
node _legal_source_T_47 = eq(io.in.b.bits.source, UInt<6>(0h20))
node _legal_source_T_48 = eq(io.in.b.bits.source, UInt<6>(0h22))
wire _legal_source_WIRE : UInt<1>[29]
connect _legal_source_WIRE[0], _legal_source_T
connect _legal_source_WIRE[1], _legal_source_T_6
connect _legal_source_WIRE[2], _legal_source_T_12
connect _legal_source_WIRE[3], _legal_source_T_18
connect _legal_source_WIRE[4], _legal_source_T_24
connect _legal_source_WIRE[5], _legal_source_T_25
connect _legal_source_WIRE[6], _legal_source_T_26
connect _legal_source_WIRE[7], _legal_source_T_27
connect _legal_source_WIRE[8], _legal_source_T_28
connect _legal_source_WIRE[9], _legal_source_T_29
connect _legal_source_WIRE[10], _legal_source_T_30
connect _legal_source_WIRE[11], _legal_source_T_31
connect _legal_source_WIRE[12], _legal_source_T_32
connect _legal_source_WIRE[13], _legal_source_T_33
connect _legal_source_WIRE[14], _legal_source_T_34
connect _legal_source_WIRE[15], _legal_source_T_35
connect _legal_source_WIRE[16], _legal_source_T_36
connect _legal_source_WIRE[17], _legal_source_T_37
connect _legal_source_WIRE[18], _legal_source_T_38
connect _legal_source_WIRE[19], _legal_source_T_39
connect _legal_source_WIRE[20], _legal_source_T_40
connect _legal_source_WIRE[21], _legal_source_T_41
connect _legal_source_WIRE[22], _legal_source_T_42
connect _legal_source_WIRE[23], _legal_source_T_43
connect _legal_source_WIRE[24], _legal_source_T_44
connect _legal_source_WIRE[25], _legal_source_T_45
connect _legal_source_WIRE[26], _legal_source_T_46
connect _legal_source_WIRE[27], _legal_source_T_47
connect _legal_source_WIRE[28], _legal_source_T_48
node _legal_source_T_49 = mux(_legal_source_WIRE[0], UInt<5>(0h10), UInt<1>(0h0))
node _legal_source_T_50 = mux(_legal_source_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _legal_source_T_51 = mux(_legal_source_WIRE[2], UInt<3>(0h4), UInt<1>(0h0))
node _legal_source_T_52 = mux(_legal_source_WIRE[3], UInt<4>(0h8), UInt<1>(0h0))
node _legal_source_T_53 = mux(_legal_source_WIRE[4], UInt<4>(0hc), UInt<1>(0h0))
node _legal_source_T_54 = mux(_legal_source_WIRE[5], UInt<7>(0h4c), UInt<1>(0h0))
node _legal_source_T_55 = mux(_legal_source_WIRE[6], UInt<7>(0h4e), UInt<1>(0h0))
node _legal_source_T_56 = mux(_legal_source_WIRE[7], UInt<7>(0h48), UInt<1>(0h0))
node _legal_source_T_57 = mux(_legal_source_WIRE[8], UInt<7>(0h4a), UInt<1>(0h0))
node _legal_source_T_58 = mux(_legal_source_WIRE[9], UInt<7>(0h44), UInt<1>(0h0))
node _legal_source_T_59 = mux(_legal_source_WIRE[10], UInt<7>(0h46), UInt<1>(0h0))
node _legal_source_T_60 = mux(_legal_source_WIRE[11], UInt<7>(0h40), UInt<1>(0h0))
node _legal_source_T_61 = mux(_legal_source_WIRE[12], UInt<7>(0h42), UInt<1>(0h0))
node _legal_source_T_62 = mux(_legal_source_WIRE[13], UInt<6>(0h3c), UInt<1>(0h0))
node _legal_source_T_63 = mux(_legal_source_WIRE[14], UInt<6>(0h3e), UInt<1>(0h0))
node _legal_source_T_64 = mux(_legal_source_WIRE[15], UInt<6>(0h38), UInt<1>(0h0))
node _legal_source_T_65 = mux(_legal_source_WIRE[16], UInt<6>(0h3a), UInt<1>(0h0))
node _legal_source_T_66 = mux(_legal_source_WIRE[17], UInt<6>(0h34), UInt<1>(0h0))
node _legal_source_T_67 = mux(_legal_source_WIRE[18], UInt<6>(0h36), UInt<1>(0h0))
node _legal_source_T_68 = mux(_legal_source_WIRE[19], UInt<6>(0h30), UInt<1>(0h0))
node _legal_source_T_69 = mux(_legal_source_WIRE[20], UInt<6>(0h32), UInt<1>(0h0))
node _legal_source_T_70 = mux(_legal_source_WIRE[21], UInt<6>(0h2c), UInt<1>(0h0))
node _legal_source_T_71 = mux(_legal_source_WIRE[22], UInt<6>(0h2e), UInt<1>(0h0))
node _legal_source_T_72 = mux(_legal_source_WIRE[23], UInt<6>(0h28), UInt<1>(0h0))
node _legal_source_T_73 = mux(_legal_source_WIRE[24], UInt<6>(0h2a), UInt<1>(0h0))
node _legal_source_T_74 = mux(_legal_source_WIRE[25], UInt<6>(0h24), UInt<1>(0h0))
node _legal_source_T_75 = mux(_legal_source_WIRE[26], UInt<6>(0h26), UInt<1>(0h0))
node _legal_source_T_76 = mux(_legal_source_WIRE[27], UInt<6>(0h20), UInt<1>(0h0))
node _legal_source_T_77 = mux(_legal_source_WIRE[28], UInt<6>(0h22), UInt<1>(0h0))
node _legal_source_T_78 = or(_legal_source_T_49, _legal_source_T_50)
node _legal_source_T_79 = or(_legal_source_T_78, _legal_source_T_51)
node _legal_source_T_80 = or(_legal_source_T_79, _legal_source_T_52)
node _legal_source_T_81 = or(_legal_source_T_80, _legal_source_T_53)
node _legal_source_T_82 = or(_legal_source_T_81, _legal_source_T_54)
node _legal_source_T_83 = or(_legal_source_T_82, _legal_source_T_55)
node _legal_source_T_84 = or(_legal_source_T_83, _legal_source_T_56)
node _legal_source_T_85 = or(_legal_source_T_84, _legal_source_T_57)
node _legal_source_T_86 = or(_legal_source_T_85, _legal_source_T_58)
node _legal_source_T_87 = or(_legal_source_T_86, _legal_source_T_59)
node _legal_source_T_88 = or(_legal_source_T_87, _legal_source_T_60)
node _legal_source_T_89 = or(_legal_source_T_88, _legal_source_T_61)
node _legal_source_T_90 = or(_legal_source_T_89, _legal_source_T_62)
node _legal_source_T_91 = or(_legal_source_T_90, _legal_source_T_63)
node _legal_source_T_92 = or(_legal_source_T_91, _legal_source_T_64)
node _legal_source_T_93 = or(_legal_source_T_92, _legal_source_T_65)
node _legal_source_T_94 = or(_legal_source_T_93, _legal_source_T_66)
node _legal_source_T_95 = or(_legal_source_T_94, _legal_source_T_67)
node _legal_source_T_96 = or(_legal_source_T_95, _legal_source_T_68)
node _legal_source_T_97 = or(_legal_source_T_96, _legal_source_T_69)
node _legal_source_T_98 = or(_legal_source_T_97, _legal_source_T_70)
node _legal_source_T_99 = or(_legal_source_T_98, _legal_source_T_71)
node _legal_source_T_100 = or(_legal_source_T_99, _legal_source_T_72)
node _legal_source_T_101 = or(_legal_source_T_100, _legal_source_T_73)
node _legal_source_T_102 = or(_legal_source_T_101, _legal_source_T_74)
node _legal_source_T_103 = or(_legal_source_T_102, _legal_source_T_75)
node _legal_source_T_104 = or(_legal_source_T_103, _legal_source_T_76)
node _legal_source_T_105 = or(_legal_source_T_104, _legal_source_T_77)
wire _legal_source_WIRE_1 : UInt<7>
connect _legal_source_WIRE_1, _legal_source_T_105
node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source)
node _T_1959 = eq(io.in.b.bits.opcode, UInt<3>(0h6))
when _T_1959 :
node _T_1960 = eq(io.in.b.bits.source, UInt<5>(0h10))
node _uncommonBits_T_48 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0)
node _T_1961 = shr(io.in.b.bits.source, 2)
node _T_1962 = eq(_T_1961, UInt<1>(0h0))
node _T_1963 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_1964 = and(_T_1962, _T_1963)
node _T_1965 = leq(uncommonBits_48, UInt<2>(0h3))
node _T_1966 = and(_T_1964, _T_1965)
node _uncommonBits_T_49 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0)
node _T_1967 = shr(io.in.b.bits.source, 2)
node _T_1968 = eq(_T_1967, UInt<1>(0h1))
node _T_1969 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_1970 = and(_T_1968, _T_1969)
node _T_1971 = leq(uncommonBits_49, UInt<2>(0h3))
node _T_1972 = and(_T_1970, _T_1971)
node _uncommonBits_T_50 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_1973 = shr(io.in.b.bits.source, 2)
node _T_1974 = eq(_T_1973, UInt<2>(0h2))
node _T_1975 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_1976 = and(_T_1974, _T_1975)
node _T_1977 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_1978 = and(_T_1976, _T_1977)
node _uncommonBits_T_51 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_1979 = shr(io.in.b.bits.source, 2)
node _T_1980 = eq(_T_1979, UInt<2>(0h3))
node _T_1981 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_1982 = and(_T_1980, _T_1981)
node _T_1983 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_1984 = and(_T_1982, _T_1983)
node _T_1985 = eq(io.in.b.bits.source, UInt<7>(0h4c))
node _T_1986 = eq(io.in.b.bits.source, UInt<7>(0h4e))
node _T_1987 = eq(io.in.b.bits.source, UInt<7>(0h48))
node _T_1988 = eq(io.in.b.bits.source, UInt<7>(0h4a))
node _T_1989 = eq(io.in.b.bits.source, UInt<7>(0h44))
node _T_1990 = eq(io.in.b.bits.source, UInt<7>(0h46))
node _T_1991 = eq(io.in.b.bits.source, UInt<7>(0h40))
node _T_1992 = eq(io.in.b.bits.source, UInt<7>(0h42))
node _T_1993 = eq(io.in.b.bits.source, UInt<6>(0h3c))
node _T_1994 = eq(io.in.b.bits.source, UInt<6>(0h3e))
node _T_1995 = eq(io.in.b.bits.source, UInt<6>(0h38))
node _T_1996 = eq(io.in.b.bits.source, UInt<6>(0h3a))
node _T_1997 = eq(io.in.b.bits.source, UInt<6>(0h34))
node _T_1998 = eq(io.in.b.bits.source, UInt<6>(0h36))
node _T_1999 = eq(io.in.b.bits.source, UInt<6>(0h30))
node _T_2000 = eq(io.in.b.bits.source, UInt<6>(0h32))
node _T_2001 = eq(io.in.b.bits.source, UInt<6>(0h2c))
node _T_2002 = eq(io.in.b.bits.source, UInt<6>(0h2e))
node _T_2003 = eq(io.in.b.bits.source, UInt<6>(0h28))
node _T_2004 = eq(io.in.b.bits.source, UInt<6>(0h2a))
node _T_2005 = eq(io.in.b.bits.source, UInt<6>(0h24))
node _T_2006 = eq(io.in.b.bits.source, UInt<6>(0h26))
node _T_2007 = eq(io.in.b.bits.source, UInt<6>(0h20))
node _T_2008 = eq(io.in.b.bits.source, UInt<6>(0h22))
wire _WIRE_4 : UInt<1>[29]
connect _WIRE_4[0], _T_1960
connect _WIRE_4[1], _T_1966
connect _WIRE_4[2], _T_1972
connect _WIRE_4[3], _T_1978
connect _WIRE_4[4], _T_1984
connect _WIRE_4[5], _T_1985
connect _WIRE_4[6], _T_1986
connect _WIRE_4[7], _T_1987
connect _WIRE_4[8], _T_1988
connect _WIRE_4[9], _T_1989
connect _WIRE_4[10], _T_1990
connect _WIRE_4[11], _T_1991
connect _WIRE_4[12], _T_1992
connect _WIRE_4[13], _T_1993
connect _WIRE_4[14], _T_1994
connect _WIRE_4[15], _T_1995
connect _WIRE_4[16], _T_1996
connect _WIRE_4[17], _T_1997
connect _WIRE_4[18], _T_1998
connect _WIRE_4[19], _T_1999
connect _WIRE_4[20], _T_2000
connect _WIRE_4[21], _T_2001
connect _WIRE_4[22], _T_2002
connect _WIRE_4[23], _T_2003
connect _WIRE_4[24], _T_2004
connect _WIRE_4[25], _T_2005
connect _WIRE_4[26], _T_2006
connect _WIRE_4[27], _T_2007
connect _WIRE_4[28], _T_2008
node _T_2009 = eq(UInt<3>(0h6), io.in.b.bits.size)
node _T_2010 = eq(UInt<3>(0h6), io.in.b.bits.size)
node _T_2011 = eq(UInt<3>(0h6), io.in.b.bits.size)
node _T_2012 = eq(UInt<3>(0h6), io.in.b.bits.size)
node _T_2013 = eq(UInt<3>(0h6), io.in.b.bits.size)
node _T_2014 = eq(UInt<3>(0h6), io.in.b.bits.size)
node _T_2015 = eq(UInt<3>(0h6), io.in.b.bits.size)
node _T_2016 = eq(UInt<3>(0h6), io.in.b.bits.size)
node _T_2017 = eq(UInt<3>(0h6), io.in.b.bits.size)
node _T_2018 = eq(UInt<3>(0h6), io.in.b.bits.size)
node _T_2019 = eq(UInt<3>(0h6), io.in.b.bits.size)
node _T_2020 = eq(UInt<3>(0h6), io.in.b.bits.size)
node _T_2021 = mux(_WIRE_4[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_2022 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_2023 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_2024 = mux(_WIRE_4[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_2025 = mux(_WIRE_4[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_2026 = mux(_WIRE_4[5], _T_2009, UInt<1>(0h0))
node _T_2027 = mux(_WIRE_4[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_2028 = mux(_WIRE_4[7], _T_2010, UInt<1>(0h0))
node _T_2029 = mux(_WIRE_4[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_2030 = mux(_WIRE_4[9], _T_2011, UInt<1>(0h0))
node _T_2031 = mux(_WIRE_4[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_2032 = mux(_WIRE_4[11], _T_2012, UInt<1>(0h0))
node _T_2033 = mux(_WIRE_4[12], UInt<1>(0h0), UInt<1>(0h0))
node _T_2034 = mux(_WIRE_4[13], _T_2013, UInt<1>(0h0))
node _T_2035 = mux(_WIRE_4[14], UInt<1>(0h0), UInt<1>(0h0))
node _T_2036 = mux(_WIRE_4[15], _T_2014, UInt<1>(0h0))
node _T_2037 = mux(_WIRE_4[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_2038 = mux(_WIRE_4[17], _T_2015, UInt<1>(0h0))
node _T_2039 = mux(_WIRE_4[18], UInt<1>(0h0), UInt<1>(0h0))
node _T_2040 = mux(_WIRE_4[19], _T_2016, UInt<1>(0h0))
node _T_2041 = mux(_WIRE_4[20], UInt<1>(0h0), UInt<1>(0h0))
node _T_2042 = mux(_WIRE_4[21], _T_2017, UInt<1>(0h0))
node _T_2043 = mux(_WIRE_4[22], UInt<1>(0h0), UInt<1>(0h0))
node _T_2044 = mux(_WIRE_4[23], _T_2018, UInt<1>(0h0))
node _T_2045 = mux(_WIRE_4[24], UInt<1>(0h0), UInt<1>(0h0))
node _T_2046 = mux(_WIRE_4[25], _T_2019, UInt<1>(0h0))
node _T_2047 = mux(_WIRE_4[26], UInt<1>(0h0), UInt<1>(0h0))
node _T_2048 = mux(_WIRE_4[27], _T_2020, UInt<1>(0h0))
node _T_2049 = mux(_WIRE_4[28], UInt<1>(0h0), UInt<1>(0h0))
node _T_2050 = or(_T_2021, _T_2022)
node _T_2051 = or(_T_2050, _T_2023)
node _T_2052 = or(_T_2051, _T_2024)
node _T_2053 = or(_T_2052, _T_2025)
node _T_2054 = or(_T_2053, _T_2026)
node _T_2055 = or(_T_2054, _T_2027)
node _T_2056 = or(_T_2055, _T_2028)
node _T_2057 = or(_T_2056, _T_2029)
node _T_2058 = or(_T_2057, _T_2030)
node _T_2059 = or(_T_2058, _T_2031)
node _T_2060 = or(_T_2059, _T_2032)
node _T_2061 = or(_T_2060, _T_2033)
node _T_2062 = or(_T_2061, _T_2034)
node _T_2063 = or(_T_2062, _T_2035)
node _T_2064 = or(_T_2063, _T_2036)
node _T_2065 = or(_T_2064, _T_2037)
node _T_2066 = or(_T_2065, _T_2038)
node _T_2067 = or(_T_2066, _T_2039)
node _T_2068 = or(_T_2067, _T_2040)
node _T_2069 = or(_T_2068, _T_2041)
node _T_2070 = or(_T_2069, _T_2042)
node _T_2071 = or(_T_2070, _T_2043)
node _T_2072 = or(_T_2071, _T_2044)
node _T_2073 = or(_T_2072, _T_2045)
node _T_2074 = or(_T_2073, _T_2046)
node _T_2075 = or(_T_2074, _T_2047)
node _T_2076 = or(_T_2075, _T_2048)
node _T_2077 = or(_T_2076, _T_2049)
wire _WIRE_5 : UInt<1>
connect _WIRE_5, _T_2077
node _T_2078 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_2079 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_2080 = and(_T_2078, _T_2079)
node _T_2081 = or(UInt<1>(0h0), _T_2080)
node _T_2082 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_2083 = cvt(_T_2082)
node _T_2084 = and(_T_2083, asSInt(UInt<17>(0h100c0)))
node _T_2085 = asSInt(_T_2084)
node _T_2086 = eq(_T_2085, asSInt(UInt<1>(0h0)))
node _T_2087 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_2088 = cvt(_T_2087)
node _T_2089 = and(_T_2088, asSInt(UInt<29>(0h100000c0)))
node _T_2090 = asSInt(_T_2089)
node _T_2091 = eq(_T_2090, asSInt(UInt<1>(0h0)))
node _T_2092 = or(_T_2086, _T_2091)
node _T_2093 = and(_T_2081, _T_2092)
node _T_2094 = or(UInt<1>(0h0), _T_2093)
node _T_2095 = and(_WIRE_5, _T_2094)
node _T_2096 = asUInt(reset)
node _T_2097 = eq(_T_2096, UInt<1>(0h0))
when _T_2097 :
node _T_2098 = eq(_T_2095, UInt<1>(0h0))
when _T_2098 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86
assert(clock, _T_2095, UInt<1>(0h1), "") : assert_86
node _T_2099 = asUInt(reset)
node _T_2100 = eq(_T_2099, UInt<1>(0h0))
when _T_2100 :
node _T_2101 = eq(address_ok, UInt<1>(0h0))
when _T_2101 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87
assert(clock, address_ok, UInt<1>(0h1), "") : assert_87
node _T_2102 = asUInt(reset)
node _T_2103 = eq(_T_2102, UInt<1>(0h0))
when _T_2103 :
node _T_2104 = eq(legal_source, UInt<1>(0h0))
when _T_2104 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88
assert(clock, legal_source, UInt<1>(0h1), "") : assert_88
node _T_2105 = asUInt(reset)
node _T_2106 = eq(_T_2105, UInt<1>(0h0))
when _T_2106 :
node _T_2107 = eq(is_aligned_1, UInt<1>(0h0))
when _T_2107 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89
node _T_2108 = leq(io.in.b.bits.param, UInt<2>(0h2))
node _T_2109 = asUInt(reset)
node _T_2110 = eq(_T_2109, UInt<1>(0h0))
when _T_2110 :
node _T_2111 = eq(_T_2108, UInt<1>(0h0))
when _T_2111 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90
assert(clock, _T_2108, UInt<1>(0h1), "") : assert_90
node _T_2112 = eq(io.in.b.bits.mask, mask_1)
node _T_2113 = asUInt(reset)
node _T_2114 = eq(_T_2113, UInt<1>(0h0))
when _T_2114 :
node _T_2115 = eq(_T_2112, UInt<1>(0h0))
when _T_2115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91
assert(clock, _T_2112, UInt<1>(0h1), "") : assert_91
node _T_2116 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_2117 = asUInt(reset)
node _T_2118 = eq(_T_2117, UInt<1>(0h0))
when _T_2118 :
node _T_2119 = eq(_T_2116, UInt<1>(0h0))
when _T_2119 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_2116, UInt<1>(0h1), "") : assert_92
node _T_2120 = eq(io.in.b.bits.opcode, UInt<3>(0h4))
when _T_2120 :
node _T_2121 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_2122 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_2123 = and(_T_2121, _T_2122)
node _T_2124 = or(UInt<1>(0h0), _T_2123)
node _T_2125 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_2126 = cvt(_T_2125)
node _T_2127 = and(_T_2126, asSInt(UInt<17>(0h100c0)))
node _T_2128 = asSInt(_T_2127)
node _T_2129 = eq(_T_2128, asSInt(UInt<1>(0h0)))
node _T_2130 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_2131 = cvt(_T_2130)
node _T_2132 = and(_T_2131, asSInt(UInt<29>(0h100000c0)))
node _T_2133 = asSInt(_T_2132)
node _T_2134 = eq(_T_2133, asSInt(UInt<1>(0h0)))
node _T_2135 = or(_T_2129, _T_2134)
node _T_2136 = and(_T_2124, _T_2135)
node _T_2137 = or(UInt<1>(0h0), _T_2136)
node _T_2138 = and(UInt<1>(0h0), _T_2137)
node _T_2139 = asUInt(reset)
node _T_2140 = eq(_T_2139, UInt<1>(0h0))
when _T_2140 :
node _T_2141 = eq(_T_2138, UInt<1>(0h0))
when _T_2141 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93
assert(clock, _T_2138, UInt<1>(0h1), "") : assert_93
node _T_2142 = asUInt(reset)
node _T_2143 = eq(_T_2142, UInt<1>(0h0))
when _T_2143 :
node _T_2144 = eq(address_ok, UInt<1>(0h0))
when _T_2144 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94
assert(clock, address_ok, UInt<1>(0h1), "") : assert_94
node _T_2145 = asUInt(reset)
node _T_2146 = eq(_T_2145, UInt<1>(0h0))
when _T_2146 :
node _T_2147 = eq(legal_source, UInt<1>(0h0))
when _T_2147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95
assert(clock, legal_source, UInt<1>(0h1), "") : assert_95
node _T_2148 = asUInt(reset)
node _T_2149 = eq(_T_2148, UInt<1>(0h0))
when _T_2149 :
node _T_2150 = eq(is_aligned_1, UInt<1>(0h0))
when _T_2150 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96
node _T_2151 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_2152 = asUInt(reset)
node _T_2153 = eq(_T_2152, UInt<1>(0h0))
when _T_2153 :
node _T_2154 = eq(_T_2151, UInt<1>(0h0))
when _T_2154 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97
assert(clock, _T_2151, UInt<1>(0h1), "") : assert_97
node _T_2155 = eq(io.in.b.bits.mask, mask_1)
node _T_2156 = asUInt(reset)
node _T_2157 = eq(_T_2156, UInt<1>(0h0))
when _T_2157 :
node _T_2158 = eq(_T_2155, UInt<1>(0h0))
when _T_2158 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_2155, UInt<1>(0h1), "") : assert_98
node _T_2159 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_2160 = asUInt(reset)
node _T_2161 = eq(_T_2160, UInt<1>(0h0))
when _T_2161 :
node _T_2162 = eq(_T_2159, UInt<1>(0h0))
when _T_2162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99
assert(clock, _T_2159, UInt<1>(0h1), "") : assert_99
node _T_2163 = eq(io.in.b.bits.opcode, UInt<1>(0h0))
when _T_2163 :
node _T_2164 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_2165 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_2166 = and(_T_2164, _T_2165)
node _T_2167 = or(UInt<1>(0h0), _T_2166)
node _T_2168 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_2169 = cvt(_T_2168)
node _T_2170 = and(_T_2169, asSInt(UInt<17>(0h100c0)))
node _T_2171 = asSInt(_T_2170)
node _T_2172 = eq(_T_2171, asSInt(UInt<1>(0h0)))
node _T_2173 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_2174 = cvt(_T_2173)
node _T_2175 = and(_T_2174, asSInt(UInt<29>(0h100000c0)))
node _T_2176 = asSInt(_T_2175)
node _T_2177 = eq(_T_2176, asSInt(UInt<1>(0h0)))
node _T_2178 = or(_T_2172, _T_2177)
node _T_2179 = and(_T_2167, _T_2178)
node _T_2180 = or(UInt<1>(0h0), _T_2179)
node _T_2181 = and(UInt<1>(0h0), _T_2180)
node _T_2182 = asUInt(reset)
node _T_2183 = eq(_T_2182, UInt<1>(0h0))
when _T_2183 :
node _T_2184 = eq(_T_2181, UInt<1>(0h0))
when _T_2184 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100
assert(clock, _T_2181, UInt<1>(0h1), "") : assert_100
node _T_2185 = asUInt(reset)
node _T_2186 = eq(_T_2185, UInt<1>(0h0))
when _T_2186 :
node _T_2187 = eq(address_ok, UInt<1>(0h0))
when _T_2187 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101
assert(clock, address_ok, UInt<1>(0h1), "") : assert_101
node _T_2188 = asUInt(reset)
node _T_2189 = eq(_T_2188, UInt<1>(0h0))
when _T_2189 :
node _T_2190 = eq(legal_source, UInt<1>(0h0))
when _T_2190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102
assert(clock, legal_source, UInt<1>(0h1), "") : assert_102
node _T_2191 = asUInt(reset)
node _T_2192 = eq(_T_2191, UInt<1>(0h0))
when _T_2192 :
node _T_2193 = eq(is_aligned_1, UInt<1>(0h0))
when _T_2193 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103
node _T_2194 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_2195 = asUInt(reset)
node _T_2196 = eq(_T_2195, UInt<1>(0h0))
when _T_2196 :
node _T_2197 = eq(_T_2194, UInt<1>(0h0))
when _T_2197 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104
assert(clock, _T_2194, UInt<1>(0h1), "") : assert_104
node _T_2198 = eq(io.in.b.bits.mask, mask_1)
node _T_2199 = asUInt(reset)
node _T_2200 = eq(_T_2199, UInt<1>(0h0))
when _T_2200 :
node _T_2201 = eq(_T_2198, UInt<1>(0h0))
when _T_2201 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_2198, UInt<1>(0h1), "") : assert_105
node _T_2202 = eq(io.in.b.bits.opcode, UInt<1>(0h1))
when _T_2202 :
node _T_2203 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_2204 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_2205 = and(_T_2203, _T_2204)
node _T_2206 = or(UInt<1>(0h0), _T_2205)
node _T_2207 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_2208 = cvt(_T_2207)
node _T_2209 = and(_T_2208, asSInt(UInt<17>(0h100c0)))
node _T_2210 = asSInt(_T_2209)
node _T_2211 = eq(_T_2210, asSInt(UInt<1>(0h0)))
node _T_2212 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_2213 = cvt(_T_2212)
node _T_2214 = and(_T_2213, asSInt(UInt<29>(0h100000c0)))
node _T_2215 = asSInt(_T_2214)
node _T_2216 = eq(_T_2215, asSInt(UInt<1>(0h0)))
node _T_2217 = or(_T_2211, _T_2216)
node _T_2218 = and(_T_2206, _T_2217)
node _T_2219 = or(UInt<1>(0h0), _T_2218)
node _T_2220 = and(UInt<1>(0h0), _T_2219)
node _T_2221 = asUInt(reset)
node _T_2222 = eq(_T_2221, UInt<1>(0h0))
when _T_2222 :
node _T_2223 = eq(_T_2220, UInt<1>(0h0))
when _T_2223 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_2220, UInt<1>(0h1), "") : assert_106
node _T_2224 = asUInt(reset)
node _T_2225 = eq(_T_2224, UInt<1>(0h0))
when _T_2225 :
node _T_2226 = eq(address_ok, UInt<1>(0h0))
when _T_2226 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, address_ok, UInt<1>(0h1), "") : assert_107
node _T_2227 = asUInt(reset)
node _T_2228 = eq(_T_2227, UInt<1>(0h0))
when _T_2228 :
node _T_2229 = eq(legal_source, UInt<1>(0h0))
when _T_2229 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108
assert(clock, legal_source, UInt<1>(0h1), "") : assert_108
node _T_2230 = asUInt(reset)
node _T_2231 = eq(_T_2230, UInt<1>(0h0))
when _T_2231 :
node _T_2232 = eq(is_aligned_1, UInt<1>(0h0))
when _T_2232 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109
node _T_2233 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_2234 = asUInt(reset)
node _T_2235 = eq(_T_2234, UInt<1>(0h0))
when _T_2235 :
node _T_2236 = eq(_T_2233, UInt<1>(0h0))
when _T_2236 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110
assert(clock, _T_2233, UInt<1>(0h1), "") : assert_110
node _T_2237 = not(mask_1)
node _T_2238 = and(io.in.b.bits.mask, _T_2237)
node _T_2239 = eq(_T_2238, UInt<1>(0h0))
node _T_2240 = asUInt(reset)
node _T_2241 = eq(_T_2240, UInt<1>(0h0))
when _T_2241 :
node _T_2242 = eq(_T_2239, UInt<1>(0h0))
when _T_2242 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_2239, UInt<1>(0h1), "") : assert_111
node _T_2243 = eq(io.in.b.bits.opcode, UInt<2>(0h2))
when _T_2243 :
node _T_2244 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_2245 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_2246 = and(_T_2244, _T_2245)
node _T_2247 = or(UInt<1>(0h0), _T_2246)
node _T_2248 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_2249 = cvt(_T_2248)
node _T_2250 = and(_T_2249, asSInt(UInt<17>(0h100c0)))
node _T_2251 = asSInt(_T_2250)
node _T_2252 = eq(_T_2251, asSInt(UInt<1>(0h0)))
node _T_2253 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_2254 = cvt(_T_2253)
node _T_2255 = and(_T_2254, asSInt(UInt<29>(0h100000c0)))
node _T_2256 = asSInt(_T_2255)
node _T_2257 = eq(_T_2256, asSInt(UInt<1>(0h0)))
node _T_2258 = or(_T_2252, _T_2257)
node _T_2259 = and(_T_2247, _T_2258)
node _T_2260 = or(UInt<1>(0h0), _T_2259)
node _T_2261 = and(UInt<1>(0h0), _T_2260)
node _T_2262 = asUInt(reset)
node _T_2263 = eq(_T_2262, UInt<1>(0h0))
when _T_2263 :
node _T_2264 = eq(_T_2261, UInt<1>(0h0))
when _T_2264 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112
assert(clock, _T_2261, UInt<1>(0h1), "") : assert_112
node _T_2265 = asUInt(reset)
node _T_2266 = eq(_T_2265, UInt<1>(0h0))
when _T_2266 :
node _T_2267 = eq(address_ok, UInt<1>(0h0))
when _T_2267 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, address_ok, UInt<1>(0h1), "") : assert_113
node _T_2268 = asUInt(reset)
node _T_2269 = eq(_T_2268, UInt<1>(0h0))
when _T_2269 :
node _T_2270 = eq(legal_source, UInt<1>(0h0))
when _T_2270 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114
assert(clock, legal_source, UInt<1>(0h1), "") : assert_114
node _T_2271 = asUInt(reset)
node _T_2272 = eq(_T_2271, UInt<1>(0h0))
when _T_2272 :
node _T_2273 = eq(is_aligned_1, UInt<1>(0h0))
when _T_2273 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115
node _T_2274 = leq(io.in.b.bits.param, UInt<3>(0h4))
node _T_2275 = asUInt(reset)
node _T_2276 = eq(_T_2275, UInt<1>(0h0))
when _T_2276 :
node _T_2277 = eq(_T_2274, UInt<1>(0h0))
when _T_2277 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116
assert(clock, _T_2274, UInt<1>(0h1), "") : assert_116
node _T_2278 = eq(io.in.b.bits.mask, mask_1)
node _T_2279 = asUInt(reset)
node _T_2280 = eq(_T_2279, UInt<1>(0h0))
when _T_2280 :
node _T_2281 = eq(_T_2278, UInt<1>(0h0))
when _T_2281 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117
assert(clock, _T_2278, UInt<1>(0h1), "") : assert_117
node _T_2282 = eq(io.in.b.bits.opcode, UInt<2>(0h3))
when _T_2282 :
node _T_2283 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_2284 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_2285 = and(_T_2283, _T_2284)
node _T_2286 = or(UInt<1>(0h0), _T_2285)
node _T_2287 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_2288 = cvt(_T_2287)
node _T_2289 = and(_T_2288, asSInt(UInt<17>(0h100c0)))
node _T_2290 = asSInt(_T_2289)
node _T_2291 = eq(_T_2290, asSInt(UInt<1>(0h0)))
node _T_2292 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_2293 = cvt(_T_2292)
node _T_2294 = and(_T_2293, asSInt(UInt<29>(0h100000c0)))
node _T_2295 = asSInt(_T_2294)
node _T_2296 = eq(_T_2295, asSInt(UInt<1>(0h0)))
node _T_2297 = or(_T_2291, _T_2296)
node _T_2298 = and(_T_2286, _T_2297)
node _T_2299 = or(UInt<1>(0h0), _T_2298)
node _T_2300 = and(UInt<1>(0h0), _T_2299)
node _T_2301 = asUInt(reset)
node _T_2302 = eq(_T_2301, UInt<1>(0h0))
when _T_2302 :
node _T_2303 = eq(_T_2300, UInt<1>(0h0))
when _T_2303 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118
assert(clock, _T_2300, UInt<1>(0h1), "") : assert_118
node _T_2304 = asUInt(reset)
node _T_2305 = eq(_T_2304, UInt<1>(0h0))
when _T_2305 :
node _T_2306 = eq(address_ok, UInt<1>(0h0))
when _T_2306 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119
assert(clock, address_ok, UInt<1>(0h1), "") : assert_119
node _T_2307 = asUInt(reset)
node _T_2308 = eq(_T_2307, UInt<1>(0h0))
when _T_2308 :
node _T_2309 = eq(legal_source, UInt<1>(0h0))
when _T_2309 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120
assert(clock, legal_source, UInt<1>(0h1), "") : assert_120
node _T_2310 = asUInt(reset)
node _T_2311 = eq(_T_2310, UInt<1>(0h0))
when _T_2311 :
node _T_2312 = eq(is_aligned_1, UInt<1>(0h0))
when _T_2312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121
node _T_2313 = leq(io.in.b.bits.param, UInt<3>(0h3))
node _T_2314 = asUInt(reset)
node _T_2315 = eq(_T_2314, UInt<1>(0h0))
when _T_2315 :
node _T_2316 = eq(_T_2313, UInt<1>(0h0))
when _T_2316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122
assert(clock, _T_2313, UInt<1>(0h1), "") : assert_122
node _T_2317 = eq(io.in.b.bits.mask, mask_1)
node _T_2318 = asUInt(reset)
node _T_2319 = eq(_T_2318, UInt<1>(0h0))
when _T_2319 :
node _T_2320 = eq(_T_2317, UInt<1>(0h0))
when _T_2320 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123
assert(clock, _T_2317, UInt<1>(0h1), "") : assert_123
node _T_2321 = eq(io.in.b.bits.opcode, UInt<3>(0h5))
when _T_2321 :
node _T_2322 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_2323 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_2324 = and(_T_2322, _T_2323)
node _T_2325 = or(UInt<1>(0h0), _T_2324)
node _T_2326 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_2327 = cvt(_T_2326)
node _T_2328 = and(_T_2327, asSInt(UInt<17>(0h100c0)))
node _T_2329 = asSInt(_T_2328)
node _T_2330 = eq(_T_2329, asSInt(UInt<1>(0h0)))
node _T_2331 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_2332 = cvt(_T_2331)
node _T_2333 = and(_T_2332, asSInt(UInt<29>(0h100000c0)))
node _T_2334 = asSInt(_T_2333)
node _T_2335 = eq(_T_2334, asSInt(UInt<1>(0h0)))
node _T_2336 = or(_T_2330, _T_2335)
node _T_2337 = and(_T_2325, _T_2336)
node _T_2338 = or(UInt<1>(0h0), _T_2337)
node _T_2339 = and(UInt<1>(0h0), _T_2338)
node _T_2340 = asUInt(reset)
node _T_2341 = eq(_T_2340, UInt<1>(0h0))
when _T_2341 :
node _T_2342 = eq(_T_2339, UInt<1>(0h0))
when _T_2342 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124
assert(clock, _T_2339, UInt<1>(0h1), "") : assert_124
node _T_2343 = asUInt(reset)
node _T_2344 = eq(_T_2343, UInt<1>(0h0))
when _T_2344 :
node _T_2345 = eq(address_ok, UInt<1>(0h0))
when _T_2345 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125
assert(clock, address_ok, UInt<1>(0h1), "") : assert_125
node _T_2346 = asUInt(reset)
node _T_2347 = eq(_T_2346, UInt<1>(0h0))
when _T_2347 :
node _T_2348 = eq(legal_source, UInt<1>(0h0))
when _T_2348 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126
assert(clock, legal_source, UInt<1>(0h1), "") : assert_126
node _T_2349 = asUInt(reset)
node _T_2350 = eq(_T_2349, UInt<1>(0h0))
when _T_2350 :
node _T_2351 = eq(is_aligned_1, UInt<1>(0h0))
when _T_2351 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127
node _T_2352 = eq(io.in.b.bits.mask, mask_1)
node _T_2353 = asUInt(reset)
node _T_2354 = eq(_T_2353, UInt<1>(0h0))
when _T_2354 :
node _T_2355 = eq(_T_2352, UInt<1>(0h0))
when _T_2355 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128
assert(clock, _T_2352, UInt<1>(0h1), "") : assert_128
node _T_2356 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_2357 = asUInt(reset)
node _T_2358 = eq(_T_2357, UInt<1>(0h0))
when _T_2358 :
node _T_2359 = eq(_T_2356, UInt<1>(0h0))
when _T_2359 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129
assert(clock, _T_2356, UInt<1>(0h1), "") : assert_129
when io.in.c.valid :
node _T_2360 = leq(io.in.c.bits.opcode, UInt<3>(0h7))
node _T_2361 = asUInt(reset)
node _T_2362 = eq(_T_2361, UInt<1>(0h0))
when _T_2362 :
node _T_2363 = eq(_T_2360, UInt<1>(0h0))
when _T_2363 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130
assert(clock, _T_2360, UInt<1>(0h1), "") : assert_130
node _source_ok_T_152 = eq(io.in.c.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_8 = or(io.in.c.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0)
node _source_ok_T_153 = shr(io.in.c.bits.source, 2)
node _source_ok_T_154 = eq(_source_ok_T_153, UInt<1>(0h0))
node _source_ok_T_155 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_156 = and(_source_ok_T_154, _source_ok_T_155)
node _source_ok_T_157 = leq(source_ok_uncommonBits_8, UInt<2>(0h3))
node _source_ok_T_158 = and(_source_ok_T_156, _source_ok_T_157)
node _source_ok_uncommonBits_T_9 = or(io.in.c.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0)
node _source_ok_T_159 = shr(io.in.c.bits.source, 2)
node _source_ok_T_160 = eq(_source_ok_T_159, UInt<1>(0h1))
node _source_ok_T_161 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_162 = and(_source_ok_T_160, _source_ok_T_161)
node _source_ok_T_163 = leq(source_ok_uncommonBits_9, UInt<2>(0h3))
node _source_ok_T_164 = and(_source_ok_T_162, _source_ok_T_163)
node _source_ok_uncommonBits_T_10 = or(io.in.c.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0)
node _source_ok_T_165 = shr(io.in.c.bits.source, 2)
node _source_ok_T_166 = eq(_source_ok_T_165, UInt<2>(0h2))
node _source_ok_T_167 = leq(UInt<1>(0h0), source_ok_uncommonBits_10)
node _source_ok_T_168 = and(_source_ok_T_166, _source_ok_T_167)
node _source_ok_T_169 = leq(source_ok_uncommonBits_10, UInt<2>(0h3))
node _source_ok_T_170 = and(_source_ok_T_168, _source_ok_T_169)
node _source_ok_uncommonBits_T_11 = or(io.in.c.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 1, 0)
node _source_ok_T_171 = shr(io.in.c.bits.source, 2)
node _source_ok_T_172 = eq(_source_ok_T_171, UInt<2>(0h3))
node _source_ok_T_173 = leq(UInt<1>(0h0), source_ok_uncommonBits_11)
node _source_ok_T_174 = and(_source_ok_T_172, _source_ok_T_173)
node _source_ok_T_175 = leq(source_ok_uncommonBits_11, UInt<2>(0h3))
node _source_ok_T_176 = and(_source_ok_T_174, _source_ok_T_175)
node _source_ok_T_177 = eq(io.in.c.bits.source, UInt<7>(0h4c))
node _source_ok_T_178 = eq(io.in.c.bits.source, UInt<7>(0h4e))
node _source_ok_T_179 = eq(io.in.c.bits.source, UInt<7>(0h48))
node _source_ok_T_180 = eq(io.in.c.bits.source, UInt<7>(0h4a))
node _source_ok_T_181 = eq(io.in.c.bits.source, UInt<7>(0h44))
node _source_ok_T_182 = eq(io.in.c.bits.source, UInt<7>(0h46))
node _source_ok_T_183 = eq(io.in.c.bits.source, UInt<7>(0h40))
node _source_ok_T_184 = eq(io.in.c.bits.source, UInt<7>(0h42))
node _source_ok_T_185 = eq(io.in.c.bits.source, UInt<6>(0h3c))
node _source_ok_T_186 = eq(io.in.c.bits.source, UInt<6>(0h3e))
node _source_ok_T_187 = eq(io.in.c.bits.source, UInt<6>(0h38))
node _source_ok_T_188 = eq(io.in.c.bits.source, UInt<6>(0h3a))
node _source_ok_T_189 = eq(io.in.c.bits.source, UInt<6>(0h34))
node _source_ok_T_190 = eq(io.in.c.bits.source, UInt<6>(0h36))
node _source_ok_T_191 = eq(io.in.c.bits.source, UInt<6>(0h30))
node _source_ok_T_192 = eq(io.in.c.bits.source, UInt<6>(0h32))
node _source_ok_T_193 = eq(io.in.c.bits.source, UInt<6>(0h2c))
node _source_ok_T_194 = eq(io.in.c.bits.source, UInt<6>(0h2e))
node _source_ok_T_195 = eq(io.in.c.bits.source, UInt<6>(0h28))
node _source_ok_T_196 = eq(io.in.c.bits.source, UInt<6>(0h2a))
node _source_ok_T_197 = eq(io.in.c.bits.source, UInt<6>(0h24))
node _source_ok_T_198 = eq(io.in.c.bits.source, UInt<6>(0h26))
node _source_ok_T_199 = eq(io.in.c.bits.source, UInt<6>(0h20))
node _source_ok_T_200 = eq(io.in.c.bits.source, UInt<6>(0h22))
wire _source_ok_WIRE_2 : UInt<1>[29]
connect _source_ok_WIRE_2[0], _source_ok_T_152
connect _source_ok_WIRE_2[1], _source_ok_T_158
connect _source_ok_WIRE_2[2], _source_ok_T_164
connect _source_ok_WIRE_2[3], _source_ok_T_170
connect _source_ok_WIRE_2[4], _source_ok_T_176
connect _source_ok_WIRE_2[5], _source_ok_T_177
connect _source_ok_WIRE_2[6], _source_ok_T_178
connect _source_ok_WIRE_2[7], _source_ok_T_179
connect _source_ok_WIRE_2[8], _source_ok_T_180
connect _source_ok_WIRE_2[9], _source_ok_T_181
connect _source_ok_WIRE_2[10], _source_ok_T_182
connect _source_ok_WIRE_2[11], _source_ok_T_183
connect _source_ok_WIRE_2[12], _source_ok_T_184
connect _source_ok_WIRE_2[13], _source_ok_T_185
connect _source_ok_WIRE_2[14], _source_ok_T_186
connect _source_ok_WIRE_2[15], _source_ok_T_187
connect _source_ok_WIRE_2[16], _source_ok_T_188
connect _source_ok_WIRE_2[17], _source_ok_T_189
connect _source_ok_WIRE_2[18], _source_ok_T_190
connect _source_ok_WIRE_2[19], _source_ok_T_191
connect _source_ok_WIRE_2[20], _source_ok_T_192
connect _source_ok_WIRE_2[21], _source_ok_T_193
connect _source_ok_WIRE_2[22], _source_ok_T_194
connect _source_ok_WIRE_2[23], _source_ok_T_195
connect _source_ok_WIRE_2[24], _source_ok_T_196
connect _source_ok_WIRE_2[25], _source_ok_T_197
connect _source_ok_WIRE_2[26], _source_ok_T_198
connect _source_ok_WIRE_2[27], _source_ok_T_199
connect _source_ok_WIRE_2[28], _source_ok_T_200
node _source_ok_T_201 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1])
node _source_ok_T_202 = or(_source_ok_T_201, _source_ok_WIRE_2[2])
node _source_ok_T_203 = or(_source_ok_T_202, _source_ok_WIRE_2[3])
node _source_ok_T_204 = or(_source_ok_T_203, _source_ok_WIRE_2[4])
node _source_ok_T_205 = or(_source_ok_T_204, _source_ok_WIRE_2[5])
node _source_ok_T_206 = or(_source_ok_T_205, _source_ok_WIRE_2[6])
node _source_ok_T_207 = or(_source_ok_T_206, _source_ok_WIRE_2[7])
node _source_ok_T_208 = or(_source_ok_T_207, _source_ok_WIRE_2[8])
node _source_ok_T_209 = or(_source_ok_T_208, _source_ok_WIRE_2[9])
node _source_ok_T_210 = or(_source_ok_T_209, _source_ok_WIRE_2[10])
node _source_ok_T_211 = or(_source_ok_T_210, _source_ok_WIRE_2[11])
node _source_ok_T_212 = or(_source_ok_T_211, _source_ok_WIRE_2[12])
node _source_ok_T_213 = or(_source_ok_T_212, _source_ok_WIRE_2[13])
node _source_ok_T_214 = or(_source_ok_T_213, _source_ok_WIRE_2[14])
node _source_ok_T_215 = or(_source_ok_T_214, _source_ok_WIRE_2[15])
node _source_ok_T_216 = or(_source_ok_T_215, _source_ok_WIRE_2[16])
node _source_ok_T_217 = or(_source_ok_T_216, _source_ok_WIRE_2[17])
node _source_ok_T_218 = or(_source_ok_T_217, _source_ok_WIRE_2[18])
node _source_ok_T_219 = or(_source_ok_T_218, _source_ok_WIRE_2[19])
node _source_ok_T_220 = or(_source_ok_T_219, _source_ok_WIRE_2[20])
node _source_ok_T_221 = or(_source_ok_T_220, _source_ok_WIRE_2[21])
node _source_ok_T_222 = or(_source_ok_T_221, _source_ok_WIRE_2[22])
node _source_ok_T_223 = or(_source_ok_T_222, _source_ok_WIRE_2[23])
node _source_ok_T_224 = or(_source_ok_T_223, _source_ok_WIRE_2[24])
node _source_ok_T_225 = or(_source_ok_T_224, _source_ok_WIRE_2[25])
node _source_ok_T_226 = or(_source_ok_T_225, _source_ok_WIRE_2[26])
node _source_ok_T_227 = or(_source_ok_T_226, _source_ok_WIRE_2[27])
node source_ok_2 = or(_source_ok_T_227, _source_ok_WIRE_2[28])
node _is_aligned_mask_T_4 = dshl(UInt<6>(0h3f), io.in.c.bits.size)
node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 5, 0)
node is_aligned_mask_2 = not(_is_aligned_mask_T_5)
node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2)
node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0))
node _address_ok_T_10 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _address_ok_T_11 = cvt(_address_ok_T_10)
node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<17>(0h100c0)))
node _address_ok_T_13 = asSInt(_address_ok_T_12)
node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0)))
node _address_ok_T_15 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _address_ok_T_16 = cvt(_address_ok_T_15)
node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<29>(0h100000c0)))
node _address_ok_T_18 = asSInt(_address_ok_T_17)
node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE_1 : UInt<1>[2]
connect _address_ok_WIRE_1[0], _address_ok_T_14
connect _address_ok_WIRE_1[1], _address_ok_T_19
node address_ok_1 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1])
node _T_2364 = eq(io.in.c.bits.source, UInt<5>(0h10))
node _T_2365 = eq(_T_2364, UInt<1>(0h0))
node _T_2366 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2367 = cvt(_T_2366)
node _T_2368 = and(_T_2367, asSInt(UInt<1>(0h0)))
node _T_2369 = asSInt(_T_2368)
node _T_2370 = eq(_T_2369, asSInt(UInt<1>(0h0)))
node _T_2371 = or(_T_2365, _T_2370)
node _uncommonBits_T_52 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0)
node _T_2372 = shr(io.in.c.bits.source, 2)
node _T_2373 = eq(_T_2372, UInt<1>(0h0))
node _T_2374 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_2375 = and(_T_2373, _T_2374)
node _T_2376 = leq(uncommonBits_52, UInt<2>(0h3))
node _T_2377 = and(_T_2375, _T_2376)
node _T_2378 = eq(_T_2377, UInt<1>(0h0))
node _T_2379 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2380 = cvt(_T_2379)
node _T_2381 = and(_T_2380, asSInt(UInt<1>(0h0)))
node _T_2382 = asSInt(_T_2381)
node _T_2383 = eq(_T_2382, asSInt(UInt<1>(0h0)))
node _T_2384 = or(_T_2378, _T_2383)
node _uncommonBits_T_53 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0)
node _T_2385 = shr(io.in.c.bits.source, 2)
node _T_2386 = eq(_T_2385, UInt<1>(0h1))
node _T_2387 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_2388 = and(_T_2386, _T_2387)
node _T_2389 = leq(uncommonBits_53, UInt<2>(0h3))
node _T_2390 = and(_T_2388, _T_2389)
node _T_2391 = eq(_T_2390, UInt<1>(0h0))
node _T_2392 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2393 = cvt(_T_2392)
node _T_2394 = and(_T_2393, asSInt(UInt<1>(0h0)))
node _T_2395 = asSInt(_T_2394)
node _T_2396 = eq(_T_2395, asSInt(UInt<1>(0h0)))
node _T_2397 = or(_T_2391, _T_2396)
node _uncommonBits_T_54 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0)
node _T_2398 = shr(io.in.c.bits.source, 2)
node _T_2399 = eq(_T_2398, UInt<2>(0h2))
node _T_2400 = leq(UInt<1>(0h0), uncommonBits_54)
node _T_2401 = and(_T_2399, _T_2400)
node _T_2402 = leq(uncommonBits_54, UInt<2>(0h3))
node _T_2403 = and(_T_2401, _T_2402)
node _T_2404 = eq(_T_2403, UInt<1>(0h0))
node _T_2405 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2406 = cvt(_T_2405)
node _T_2407 = and(_T_2406, asSInt(UInt<1>(0h0)))
node _T_2408 = asSInt(_T_2407)
node _T_2409 = eq(_T_2408, asSInt(UInt<1>(0h0)))
node _T_2410 = or(_T_2404, _T_2409)
node _uncommonBits_T_55 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0)
node _T_2411 = shr(io.in.c.bits.source, 2)
node _T_2412 = eq(_T_2411, UInt<2>(0h3))
node _T_2413 = leq(UInt<1>(0h0), uncommonBits_55)
node _T_2414 = and(_T_2412, _T_2413)
node _T_2415 = leq(uncommonBits_55, UInt<2>(0h3))
node _T_2416 = and(_T_2414, _T_2415)
node _T_2417 = eq(_T_2416, UInt<1>(0h0))
node _T_2418 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2419 = cvt(_T_2418)
node _T_2420 = and(_T_2419, asSInt(UInt<1>(0h0)))
node _T_2421 = asSInt(_T_2420)
node _T_2422 = eq(_T_2421, asSInt(UInt<1>(0h0)))
node _T_2423 = or(_T_2417, _T_2422)
node _T_2424 = eq(io.in.c.bits.source, UInt<7>(0h4c))
node _T_2425 = eq(_T_2424, UInt<1>(0h0))
node _T_2426 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2427 = cvt(_T_2426)
node _T_2428 = and(_T_2427, asSInt(UInt<1>(0h0)))
node _T_2429 = asSInt(_T_2428)
node _T_2430 = eq(_T_2429, asSInt(UInt<1>(0h0)))
node _T_2431 = or(_T_2425, _T_2430)
node _T_2432 = eq(io.in.c.bits.source, UInt<7>(0h4e))
node _T_2433 = eq(_T_2432, UInt<1>(0h0))
node _T_2434 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2435 = cvt(_T_2434)
node _T_2436 = and(_T_2435, asSInt(UInt<1>(0h0)))
node _T_2437 = asSInt(_T_2436)
node _T_2438 = eq(_T_2437, asSInt(UInt<1>(0h0)))
node _T_2439 = or(_T_2433, _T_2438)
node _T_2440 = eq(io.in.c.bits.source, UInt<7>(0h48))
node _T_2441 = eq(_T_2440, UInt<1>(0h0))
node _T_2442 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2443 = cvt(_T_2442)
node _T_2444 = and(_T_2443, asSInt(UInt<1>(0h0)))
node _T_2445 = asSInt(_T_2444)
node _T_2446 = eq(_T_2445, asSInt(UInt<1>(0h0)))
node _T_2447 = or(_T_2441, _T_2446)
node _T_2448 = eq(io.in.c.bits.source, UInt<7>(0h4a))
node _T_2449 = eq(_T_2448, UInt<1>(0h0))
node _T_2450 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2451 = cvt(_T_2450)
node _T_2452 = and(_T_2451, asSInt(UInt<1>(0h0)))
node _T_2453 = asSInt(_T_2452)
node _T_2454 = eq(_T_2453, asSInt(UInt<1>(0h0)))
node _T_2455 = or(_T_2449, _T_2454)
node _T_2456 = eq(io.in.c.bits.source, UInt<7>(0h44))
node _T_2457 = eq(_T_2456, UInt<1>(0h0))
node _T_2458 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2459 = cvt(_T_2458)
node _T_2460 = and(_T_2459, asSInt(UInt<1>(0h0)))
node _T_2461 = asSInt(_T_2460)
node _T_2462 = eq(_T_2461, asSInt(UInt<1>(0h0)))
node _T_2463 = or(_T_2457, _T_2462)
node _T_2464 = eq(io.in.c.bits.source, UInt<7>(0h46))
node _T_2465 = eq(_T_2464, UInt<1>(0h0))
node _T_2466 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2467 = cvt(_T_2466)
node _T_2468 = and(_T_2467, asSInt(UInt<1>(0h0)))
node _T_2469 = asSInt(_T_2468)
node _T_2470 = eq(_T_2469, asSInt(UInt<1>(0h0)))
node _T_2471 = or(_T_2465, _T_2470)
node _T_2472 = eq(io.in.c.bits.source, UInt<7>(0h40))
node _T_2473 = eq(_T_2472, UInt<1>(0h0))
node _T_2474 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2475 = cvt(_T_2474)
node _T_2476 = and(_T_2475, asSInt(UInt<1>(0h0)))
node _T_2477 = asSInt(_T_2476)
node _T_2478 = eq(_T_2477, asSInt(UInt<1>(0h0)))
node _T_2479 = or(_T_2473, _T_2478)
node _T_2480 = eq(io.in.c.bits.source, UInt<7>(0h42))
node _T_2481 = eq(_T_2480, UInt<1>(0h0))
node _T_2482 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2483 = cvt(_T_2482)
node _T_2484 = and(_T_2483, asSInt(UInt<1>(0h0)))
node _T_2485 = asSInt(_T_2484)
node _T_2486 = eq(_T_2485, asSInt(UInt<1>(0h0)))
node _T_2487 = or(_T_2481, _T_2486)
node _T_2488 = eq(io.in.c.bits.source, UInt<6>(0h3c))
node _T_2489 = eq(_T_2488, UInt<1>(0h0))
node _T_2490 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2491 = cvt(_T_2490)
node _T_2492 = and(_T_2491, asSInt(UInt<1>(0h0)))
node _T_2493 = asSInt(_T_2492)
node _T_2494 = eq(_T_2493, asSInt(UInt<1>(0h0)))
node _T_2495 = or(_T_2489, _T_2494)
node _T_2496 = eq(io.in.c.bits.source, UInt<6>(0h3e))
node _T_2497 = eq(_T_2496, UInt<1>(0h0))
node _T_2498 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2499 = cvt(_T_2498)
node _T_2500 = and(_T_2499, asSInt(UInt<1>(0h0)))
node _T_2501 = asSInt(_T_2500)
node _T_2502 = eq(_T_2501, asSInt(UInt<1>(0h0)))
node _T_2503 = or(_T_2497, _T_2502)
node _T_2504 = eq(io.in.c.bits.source, UInt<6>(0h38))
node _T_2505 = eq(_T_2504, UInt<1>(0h0))
node _T_2506 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2507 = cvt(_T_2506)
node _T_2508 = and(_T_2507, asSInt(UInt<1>(0h0)))
node _T_2509 = asSInt(_T_2508)
node _T_2510 = eq(_T_2509, asSInt(UInt<1>(0h0)))
node _T_2511 = or(_T_2505, _T_2510)
node _T_2512 = eq(io.in.c.bits.source, UInt<6>(0h3a))
node _T_2513 = eq(_T_2512, UInt<1>(0h0))
node _T_2514 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2515 = cvt(_T_2514)
node _T_2516 = and(_T_2515, asSInt(UInt<1>(0h0)))
node _T_2517 = asSInt(_T_2516)
node _T_2518 = eq(_T_2517, asSInt(UInt<1>(0h0)))
node _T_2519 = or(_T_2513, _T_2518)
node _T_2520 = eq(io.in.c.bits.source, UInt<6>(0h34))
node _T_2521 = eq(_T_2520, UInt<1>(0h0))
node _T_2522 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2523 = cvt(_T_2522)
node _T_2524 = and(_T_2523, asSInt(UInt<1>(0h0)))
node _T_2525 = asSInt(_T_2524)
node _T_2526 = eq(_T_2525, asSInt(UInt<1>(0h0)))
node _T_2527 = or(_T_2521, _T_2526)
node _T_2528 = eq(io.in.c.bits.source, UInt<6>(0h36))
node _T_2529 = eq(_T_2528, UInt<1>(0h0))
node _T_2530 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2531 = cvt(_T_2530)
node _T_2532 = and(_T_2531, asSInt(UInt<1>(0h0)))
node _T_2533 = asSInt(_T_2532)
node _T_2534 = eq(_T_2533, asSInt(UInt<1>(0h0)))
node _T_2535 = or(_T_2529, _T_2534)
node _T_2536 = eq(io.in.c.bits.source, UInt<6>(0h30))
node _T_2537 = eq(_T_2536, UInt<1>(0h0))
node _T_2538 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2539 = cvt(_T_2538)
node _T_2540 = and(_T_2539, asSInt(UInt<1>(0h0)))
node _T_2541 = asSInt(_T_2540)
node _T_2542 = eq(_T_2541, asSInt(UInt<1>(0h0)))
node _T_2543 = or(_T_2537, _T_2542)
node _T_2544 = eq(io.in.c.bits.source, UInt<6>(0h32))
node _T_2545 = eq(_T_2544, UInt<1>(0h0))
node _T_2546 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2547 = cvt(_T_2546)
node _T_2548 = and(_T_2547, asSInt(UInt<1>(0h0)))
node _T_2549 = asSInt(_T_2548)
node _T_2550 = eq(_T_2549, asSInt(UInt<1>(0h0)))
node _T_2551 = or(_T_2545, _T_2550)
node _T_2552 = eq(io.in.c.bits.source, UInt<6>(0h2c))
node _T_2553 = eq(_T_2552, UInt<1>(0h0))
node _T_2554 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2555 = cvt(_T_2554)
node _T_2556 = and(_T_2555, asSInt(UInt<1>(0h0)))
node _T_2557 = asSInt(_T_2556)
node _T_2558 = eq(_T_2557, asSInt(UInt<1>(0h0)))
node _T_2559 = or(_T_2553, _T_2558)
node _T_2560 = eq(io.in.c.bits.source, UInt<6>(0h2e))
node _T_2561 = eq(_T_2560, UInt<1>(0h0))
node _T_2562 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2563 = cvt(_T_2562)
node _T_2564 = and(_T_2563, asSInt(UInt<1>(0h0)))
node _T_2565 = asSInt(_T_2564)
node _T_2566 = eq(_T_2565, asSInt(UInt<1>(0h0)))
node _T_2567 = or(_T_2561, _T_2566)
node _T_2568 = eq(io.in.c.bits.source, UInt<6>(0h28))
node _T_2569 = eq(_T_2568, UInt<1>(0h0))
node _T_2570 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2571 = cvt(_T_2570)
node _T_2572 = and(_T_2571, asSInt(UInt<1>(0h0)))
node _T_2573 = asSInt(_T_2572)
node _T_2574 = eq(_T_2573, asSInt(UInt<1>(0h0)))
node _T_2575 = or(_T_2569, _T_2574)
node _T_2576 = eq(io.in.c.bits.source, UInt<6>(0h2a))
node _T_2577 = eq(_T_2576, UInt<1>(0h0))
node _T_2578 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2579 = cvt(_T_2578)
node _T_2580 = and(_T_2579, asSInt(UInt<1>(0h0)))
node _T_2581 = asSInt(_T_2580)
node _T_2582 = eq(_T_2581, asSInt(UInt<1>(0h0)))
node _T_2583 = or(_T_2577, _T_2582)
node _T_2584 = eq(io.in.c.bits.source, UInt<6>(0h24))
node _T_2585 = eq(_T_2584, UInt<1>(0h0))
node _T_2586 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2587 = cvt(_T_2586)
node _T_2588 = and(_T_2587, asSInt(UInt<1>(0h0)))
node _T_2589 = asSInt(_T_2588)
node _T_2590 = eq(_T_2589, asSInt(UInt<1>(0h0)))
node _T_2591 = or(_T_2585, _T_2590)
node _T_2592 = eq(io.in.c.bits.source, UInt<6>(0h26))
node _T_2593 = eq(_T_2592, UInt<1>(0h0))
node _T_2594 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2595 = cvt(_T_2594)
node _T_2596 = and(_T_2595, asSInt(UInt<1>(0h0)))
node _T_2597 = asSInt(_T_2596)
node _T_2598 = eq(_T_2597, asSInt(UInt<1>(0h0)))
node _T_2599 = or(_T_2593, _T_2598)
node _T_2600 = eq(io.in.c.bits.source, UInt<6>(0h20))
node _T_2601 = eq(_T_2600, UInt<1>(0h0))
node _T_2602 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2603 = cvt(_T_2602)
node _T_2604 = and(_T_2603, asSInt(UInt<1>(0h0)))
node _T_2605 = asSInt(_T_2604)
node _T_2606 = eq(_T_2605, asSInt(UInt<1>(0h0)))
node _T_2607 = or(_T_2601, _T_2606)
node _T_2608 = eq(io.in.c.bits.source, UInt<6>(0h22))
node _T_2609 = eq(_T_2608, UInt<1>(0h0))
node _T_2610 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2611 = cvt(_T_2610)
node _T_2612 = and(_T_2611, asSInt(UInt<1>(0h0)))
node _T_2613 = asSInt(_T_2612)
node _T_2614 = eq(_T_2613, asSInt(UInt<1>(0h0)))
node _T_2615 = or(_T_2609, _T_2614)
node _T_2616 = and(_T_2371, _T_2384)
node _T_2617 = and(_T_2616, _T_2397)
node _T_2618 = and(_T_2617, _T_2410)
node _T_2619 = and(_T_2618, _T_2423)
node _T_2620 = and(_T_2619, _T_2431)
node _T_2621 = and(_T_2620, _T_2439)
node _T_2622 = and(_T_2621, _T_2447)
node _T_2623 = and(_T_2622, _T_2455)
node _T_2624 = and(_T_2623, _T_2463)
node _T_2625 = and(_T_2624, _T_2471)
node _T_2626 = and(_T_2625, _T_2479)
node _T_2627 = and(_T_2626, _T_2487)
node _T_2628 = and(_T_2627, _T_2495)
node _T_2629 = and(_T_2628, _T_2503)
node _T_2630 = and(_T_2629, _T_2511)
node _T_2631 = and(_T_2630, _T_2519)
node _T_2632 = and(_T_2631, _T_2527)
node _T_2633 = and(_T_2632, _T_2535)
node _T_2634 = and(_T_2633, _T_2543)
node _T_2635 = and(_T_2634, _T_2551)
node _T_2636 = and(_T_2635, _T_2559)
node _T_2637 = and(_T_2636, _T_2567)
node _T_2638 = and(_T_2637, _T_2575)
node _T_2639 = and(_T_2638, _T_2583)
node _T_2640 = and(_T_2639, _T_2591)
node _T_2641 = and(_T_2640, _T_2599)
node _T_2642 = and(_T_2641, _T_2607)
node _T_2643 = and(_T_2642, _T_2615)
node _T_2644 = asUInt(reset)
node _T_2645 = eq(_T_2644, UInt<1>(0h0))
when _T_2645 :
node _T_2646 = eq(_T_2643, UInt<1>(0h0))
when _T_2646 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131
assert(clock, _T_2643, UInt<1>(0h1), "") : assert_131
node _T_2647 = eq(io.in.c.bits.opcode, UInt<3>(0h4))
when _T_2647 :
node _T_2648 = asUInt(reset)
node _T_2649 = eq(_T_2648, UInt<1>(0h0))
when _T_2649 :
node _T_2650 = eq(address_ok_1, UInt<1>(0h0))
when _T_2650 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132
node _T_2651 = asUInt(reset)
node _T_2652 = eq(_T_2651, UInt<1>(0h0))
when _T_2652 :
node _T_2653 = eq(source_ok_2, UInt<1>(0h0))
when _T_2653 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133
node _T_2654 = geq(io.in.c.bits.size, UInt<3>(0h4))
node _T_2655 = asUInt(reset)
node _T_2656 = eq(_T_2655, UInt<1>(0h0))
when _T_2656 :
node _T_2657 = eq(_T_2654, UInt<1>(0h0))
when _T_2657 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134
assert(clock, _T_2654, UInt<1>(0h1), "") : assert_134
node _T_2658 = asUInt(reset)
node _T_2659 = eq(_T_2658, UInt<1>(0h0))
when _T_2659 :
node _T_2660 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2660 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135
node _T_2661 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_2662 = asUInt(reset)
node _T_2663 = eq(_T_2662, UInt<1>(0h0))
when _T_2663 :
node _T_2664 = eq(_T_2661, UInt<1>(0h0))
when _T_2664 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136
assert(clock, _T_2661, UInt<1>(0h1), "") : assert_136
node _T_2665 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2666 = asUInt(reset)
node _T_2667 = eq(_T_2666, UInt<1>(0h0))
when _T_2667 :
node _T_2668 = eq(_T_2665, UInt<1>(0h0))
when _T_2668 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137
assert(clock, _T_2665, UInt<1>(0h1), "") : assert_137
node _T_2669 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
when _T_2669 :
node _T_2670 = asUInt(reset)
node _T_2671 = eq(_T_2670, UInt<1>(0h0))
when _T_2671 :
node _T_2672 = eq(address_ok_1, UInt<1>(0h0))
when _T_2672 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138
node _T_2673 = asUInt(reset)
node _T_2674 = eq(_T_2673, UInt<1>(0h0))
when _T_2674 :
node _T_2675 = eq(source_ok_2, UInt<1>(0h0))
when _T_2675 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139
node _T_2676 = geq(io.in.c.bits.size, UInt<3>(0h4))
node _T_2677 = asUInt(reset)
node _T_2678 = eq(_T_2677, UInt<1>(0h0))
when _T_2678 :
node _T_2679 = eq(_T_2676, UInt<1>(0h0))
when _T_2679 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140
assert(clock, _T_2676, UInt<1>(0h1), "") : assert_140
node _T_2680 = asUInt(reset)
node _T_2681 = eq(_T_2680, UInt<1>(0h0))
when _T_2681 :
node _T_2682 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2682 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141
node _T_2683 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_2684 = asUInt(reset)
node _T_2685 = eq(_T_2684, UInt<1>(0h0))
when _T_2685 :
node _T_2686 = eq(_T_2683, UInt<1>(0h0))
when _T_2686 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142
assert(clock, _T_2683, UInt<1>(0h1), "") : assert_142
node _T_2687 = eq(io.in.c.bits.opcode, UInt<3>(0h6))
when _T_2687 :
node _T_2688 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_2689 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_2690 = and(_T_2688, _T_2689)
node _T_2691 = eq(io.in.c.bits.source, UInt<5>(0h10))
node _uncommonBits_T_56 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0)
node _T_2692 = shr(io.in.c.bits.source, 2)
node _T_2693 = eq(_T_2692, UInt<1>(0h0))
node _T_2694 = leq(UInt<1>(0h0), uncommonBits_56)
node _T_2695 = and(_T_2693, _T_2694)
node _T_2696 = leq(uncommonBits_56, UInt<2>(0h3))
node _T_2697 = and(_T_2695, _T_2696)
node _uncommonBits_T_57 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0)
node _T_2698 = shr(io.in.c.bits.source, 2)
node _T_2699 = eq(_T_2698, UInt<1>(0h1))
node _T_2700 = leq(UInt<1>(0h0), uncommonBits_57)
node _T_2701 = and(_T_2699, _T_2700)
node _T_2702 = leq(uncommonBits_57, UInt<2>(0h3))
node _T_2703 = and(_T_2701, _T_2702)
node _uncommonBits_T_58 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_58 = bits(_uncommonBits_T_58, 1, 0)
node _T_2704 = shr(io.in.c.bits.source, 2)
node _T_2705 = eq(_T_2704, UInt<2>(0h2))
node _T_2706 = leq(UInt<1>(0h0), uncommonBits_58)
node _T_2707 = and(_T_2705, _T_2706)
node _T_2708 = leq(uncommonBits_58, UInt<2>(0h3))
node _T_2709 = and(_T_2707, _T_2708)
node _uncommonBits_T_59 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_59 = bits(_uncommonBits_T_59, 1, 0)
node _T_2710 = shr(io.in.c.bits.source, 2)
node _T_2711 = eq(_T_2710, UInt<2>(0h3))
node _T_2712 = leq(UInt<1>(0h0), uncommonBits_59)
node _T_2713 = and(_T_2711, _T_2712)
node _T_2714 = leq(uncommonBits_59, UInt<2>(0h3))
node _T_2715 = and(_T_2713, _T_2714)
node _T_2716 = eq(io.in.c.bits.source, UInt<7>(0h4c))
node _T_2717 = eq(io.in.c.bits.source, UInt<7>(0h4e))
node _T_2718 = eq(io.in.c.bits.source, UInt<7>(0h48))
node _T_2719 = eq(io.in.c.bits.source, UInt<7>(0h4a))
node _T_2720 = eq(io.in.c.bits.source, UInt<7>(0h44))
node _T_2721 = eq(io.in.c.bits.source, UInt<7>(0h46))
node _T_2722 = eq(io.in.c.bits.source, UInt<7>(0h40))
node _T_2723 = eq(io.in.c.bits.source, UInt<7>(0h42))
node _T_2724 = eq(io.in.c.bits.source, UInt<6>(0h3c))
node _T_2725 = eq(io.in.c.bits.source, UInt<6>(0h3e))
node _T_2726 = eq(io.in.c.bits.source, UInt<6>(0h38))
node _T_2727 = eq(io.in.c.bits.source, UInt<6>(0h3a))
node _T_2728 = eq(io.in.c.bits.source, UInt<6>(0h34))
node _T_2729 = eq(io.in.c.bits.source, UInt<6>(0h36))
node _T_2730 = eq(io.in.c.bits.source, UInt<6>(0h30))
node _T_2731 = eq(io.in.c.bits.source, UInt<6>(0h32))
node _T_2732 = eq(io.in.c.bits.source, UInt<6>(0h2c))
node _T_2733 = eq(io.in.c.bits.source, UInt<6>(0h2e))
node _T_2734 = eq(io.in.c.bits.source, UInt<6>(0h28))
node _T_2735 = eq(io.in.c.bits.source, UInt<6>(0h2a))
node _T_2736 = eq(io.in.c.bits.source, UInt<6>(0h24))
node _T_2737 = eq(io.in.c.bits.source, UInt<6>(0h26))
node _T_2738 = eq(io.in.c.bits.source, UInt<6>(0h20))
node _T_2739 = eq(io.in.c.bits.source, UInt<6>(0h22))
node _T_2740 = or(_T_2691, _T_2697)
node _T_2741 = or(_T_2740, _T_2703)
node _T_2742 = or(_T_2741, _T_2709)
node _T_2743 = or(_T_2742, _T_2715)
node _T_2744 = or(_T_2743, _T_2716)
node _T_2745 = or(_T_2744, _T_2717)
node _T_2746 = or(_T_2745, _T_2718)
node _T_2747 = or(_T_2746, _T_2719)
node _T_2748 = or(_T_2747, _T_2720)
node _T_2749 = or(_T_2748, _T_2721)
node _T_2750 = or(_T_2749, _T_2722)
node _T_2751 = or(_T_2750, _T_2723)
node _T_2752 = or(_T_2751, _T_2724)
node _T_2753 = or(_T_2752, _T_2725)
node _T_2754 = or(_T_2753, _T_2726)
node _T_2755 = or(_T_2754, _T_2727)
node _T_2756 = or(_T_2755, _T_2728)
node _T_2757 = or(_T_2756, _T_2729)
node _T_2758 = or(_T_2757, _T_2730)
node _T_2759 = or(_T_2758, _T_2731)
node _T_2760 = or(_T_2759, _T_2732)
node _T_2761 = or(_T_2760, _T_2733)
node _T_2762 = or(_T_2761, _T_2734)
node _T_2763 = or(_T_2762, _T_2735)
node _T_2764 = or(_T_2763, _T_2736)
node _T_2765 = or(_T_2764, _T_2737)
node _T_2766 = or(_T_2765, _T_2738)
node _T_2767 = or(_T_2766, _T_2739)
node _T_2768 = and(_T_2690, _T_2767)
node _T_2769 = or(UInt<1>(0h0), _T_2768)
node _T_2770 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2771 = or(UInt<1>(0h0), _T_2770)
node _T_2772 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_2773 = cvt(_T_2772)
node _T_2774 = and(_T_2773, asSInt(UInt<17>(0h100c0)))
node _T_2775 = asSInt(_T_2774)
node _T_2776 = eq(_T_2775, asSInt(UInt<1>(0h0)))
node _T_2777 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_2778 = cvt(_T_2777)
node _T_2779 = and(_T_2778, asSInt(UInt<29>(0h100000c0)))
node _T_2780 = asSInt(_T_2779)
node _T_2781 = eq(_T_2780, asSInt(UInt<1>(0h0)))
node _T_2782 = or(_T_2776, _T_2781)
node _T_2783 = and(_T_2771, _T_2782)
node _T_2784 = or(UInt<1>(0h0), _T_2783)
node _T_2785 = and(_T_2769, _T_2784)
node _T_2786 = asUInt(reset)
node _T_2787 = eq(_T_2786, UInt<1>(0h0))
when _T_2787 :
node _T_2788 = eq(_T_2785, UInt<1>(0h0))
when _T_2788 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143
assert(clock, _T_2785, UInt<1>(0h1), "") : assert_143
node _T_2789 = eq(io.in.c.bits.source, UInt<5>(0h10))
node _uncommonBits_T_60 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0)
node _T_2790 = shr(io.in.c.bits.source, 2)
node _T_2791 = eq(_T_2790, UInt<1>(0h0))
node _T_2792 = leq(UInt<1>(0h0), uncommonBits_60)
node _T_2793 = and(_T_2791, _T_2792)
node _T_2794 = leq(uncommonBits_60, UInt<2>(0h3))
node _T_2795 = and(_T_2793, _T_2794)
node _uncommonBits_T_61 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0)
node _T_2796 = shr(io.in.c.bits.source, 2)
node _T_2797 = eq(_T_2796, UInt<1>(0h1))
node _T_2798 = leq(UInt<1>(0h0), uncommonBits_61)
node _T_2799 = and(_T_2797, _T_2798)
node _T_2800 = leq(uncommonBits_61, UInt<2>(0h3))
node _T_2801 = and(_T_2799, _T_2800)
node _uncommonBits_T_62 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0)
node _T_2802 = shr(io.in.c.bits.source, 2)
node _T_2803 = eq(_T_2802, UInt<2>(0h2))
node _T_2804 = leq(UInt<1>(0h0), uncommonBits_62)
node _T_2805 = and(_T_2803, _T_2804)
node _T_2806 = leq(uncommonBits_62, UInt<2>(0h3))
node _T_2807 = and(_T_2805, _T_2806)
node _uncommonBits_T_63 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0)
node _T_2808 = shr(io.in.c.bits.source, 2)
node _T_2809 = eq(_T_2808, UInt<2>(0h3))
node _T_2810 = leq(UInt<1>(0h0), uncommonBits_63)
node _T_2811 = and(_T_2809, _T_2810)
node _T_2812 = leq(uncommonBits_63, UInt<2>(0h3))
node _T_2813 = and(_T_2811, _T_2812)
node _T_2814 = eq(io.in.c.bits.source, UInt<7>(0h4c))
node _T_2815 = eq(io.in.c.bits.source, UInt<7>(0h4e))
node _T_2816 = eq(io.in.c.bits.source, UInt<7>(0h48))
node _T_2817 = eq(io.in.c.bits.source, UInt<7>(0h4a))
node _T_2818 = eq(io.in.c.bits.source, UInt<7>(0h44))
node _T_2819 = eq(io.in.c.bits.source, UInt<7>(0h46))
node _T_2820 = eq(io.in.c.bits.source, UInt<7>(0h40))
node _T_2821 = eq(io.in.c.bits.source, UInt<7>(0h42))
node _T_2822 = eq(io.in.c.bits.source, UInt<6>(0h3c))
node _T_2823 = eq(io.in.c.bits.source, UInt<6>(0h3e))
node _T_2824 = eq(io.in.c.bits.source, UInt<6>(0h38))
node _T_2825 = eq(io.in.c.bits.source, UInt<6>(0h3a))
node _T_2826 = eq(io.in.c.bits.source, UInt<6>(0h34))
node _T_2827 = eq(io.in.c.bits.source, UInt<6>(0h36))
node _T_2828 = eq(io.in.c.bits.source, UInt<6>(0h30))
node _T_2829 = eq(io.in.c.bits.source, UInt<6>(0h32))
node _T_2830 = eq(io.in.c.bits.source, UInt<6>(0h2c))
node _T_2831 = eq(io.in.c.bits.source, UInt<6>(0h2e))
node _T_2832 = eq(io.in.c.bits.source, UInt<6>(0h28))
node _T_2833 = eq(io.in.c.bits.source, UInt<6>(0h2a))
node _T_2834 = eq(io.in.c.bits.source, UInt<6>(0h24))
node _T_2835 = eq(io.in.c.bits.source, UInt<6>(0h26))
node _T_2836 = eq(io.in.c.bits.source, UInt<6>(0h20))
node _T_2837 = eq(io.in.c.bits.source, UInt<6>(0h22))
wire _WIRE_6 : UInt<1>[29]
connect _WIRE_6[0], _T_2789
connect _WIRE_6[1], _T_2795
connect _WIRE_6[2], _T_2801
connect _WIRE_6[3], _T_2807
connect _WIRE_6[4], _T_2813
connect _WIRE_6[5], _T_2814
connect _WIRE_6[6], _T_2815
connect _WIRE_6[7], _T_2816
connect _WIRE_6[8], _T_2817
connect _WIRE_6[9], _T_2818
connect _WIRE_6[10], _T_2819
connect _WIRE_6[11], _T_2820
connect _WIRE_6[12], _T_2821
connect _WIRE_6[13], _T_2822
connect _WIRE_6[14], _T_2823
connect _WIRE_6[15], _T_2824
connect _WIRE_6[16], _T_2825
connect _WIRE_6[17], _T_2826
connect _WIRE_6[18], _T_2827
connect _WIRE_6[19], _T_2828
connect _WIRE_6[20], _T_2829
connect _WIRE_6[21], _T_2830
connect _WIRE_6[22], _T_2831
connect _WIRE_6[23], _T_2832
connect _WIRE_6[24], _T_2833
connect _WIRE_6[25], _T_2834
connect _WIRE_6[26], _T_2835
connect _WIRE_6[27], _T_2836
connect _WIRE_6[28], _T_2837
node _T_2838 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2839 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2840 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2841 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2842 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2843 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2844 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2845 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2846 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2847 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2848 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2849 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2850 = mux(_WIRE_6[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_2851 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_2852 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_2853 = mux(_WIRE_6[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_2854 = mux(_WIRE_6[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_2855 = mux(_WIRE_6[5], _T_2838, UInt<1>(0h0))
node _T_2856 = mux(_WIRE_6[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_2857 = mux(_WIRE_6[7], _T_2839, UInt<1>(0h0))
node _T_2858 = mux(_WIRE_6[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_2859 = mux(_WIRE_6[9], _T_2840, UInt<1>(0h0))
node _T_2860 = mux(_WIRE_6[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_2861 = mux(_WIRE_6[11], _T_2841, UInt<1>(0h0))
node _T_2862 = mux(_WIRE_6[12], UInt<1>(0h0), UInt<1>(0h0))
node _T_2863 = mux(_WIRE_6[13], _T_2842, UInt<1>(0h0))
node _T_2864 = mux(_WIRE_6[14], UInt<1>(0h0), UInt<1>(0h0))
node _T_2865 = mux(_WIRE_6[15], _T_2843, UInt<1>(0h0))
node _T_2866 = mux(_WIRE_6[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_2867 = mux(_WIRE_6[17], _T_2844, UInt<1>(0h0))
node _T_2868 = mux(_WIRE_6[18], UInt<1>(0h0), UInt<1>(0h0))
node _T_2869 = mux(_WIRE_6[19], _T_2845, UInt<1>(0h0))
node _T_2870 = mux(_WIRE_6[20], UInt<1>(0h0), UInt<1>(0h0))
node _T_2871 = mux(_WIRE_6[21], _T_2846, UInt<1>(0h0))
node _T_2872 = mux(_WIRE_6[22], UInt<1>(0h0), UInt<1>(0h0))
node _T_2873 = mux(_WIRE_6[23], _T_2847, UInt<1>(0h0))
node _T_2874 = mux(_WIRE_6[24], UInt<1>(0h0), UInt<1>(0h0))
node _T_2875 = mux(_WIRE_6[25], _T_2848, UInt<1>(0h0))
node _T_2876 = mux(_WIRE_6[26], UInt<1>(0h0), UInt<1>(0h0))
node _T_2877 = mux(_WIRE_6[27], _T_2849, UInt<1>(0h0))
node _T_2878 = mux(_WIRE_6[28], UInt<1>(0h0), UInt<1>(0h0))
node _T_2879 = or(_T_2850, _T_2851)
node _T_2880 = or(_T_2879, _T_2852)
node _T_2881 = or(_T_2880, _T_2853)
node _T_2882 = or(_T_2881, _T_2854)
node _T_2883 = or(_T_2882, _T_2855)
node _T_2884 = or(_T_2883, _T_2856)
node _T_2885 = or(_T_2884, _T_2857)
node _T_2886 = or(_T_2885, _T_2858)
node _T_2887 = or(_T_2886, _T_2859)
node _T_2888 = or(_T_2887, _T_2860)
node _T_2889 = or(_T_2888, _T_2861)
node _T_2890 = or(_T_2889, _T_2862)
node _T_2891 = or(_T_2890, _T_2863)
node _T_2892 = or(_T_2891, _T_2864)
node _T_2893 = or(_T_2892, _T_2865)
node _T_2894 = or(_T_2893, _T_2866)
node _T_2895 = or(_T_2894, _T_2867)
node _T_2896 = or(_T_2895, _T_2868)
node _T_2897 = or(_T_2896, _T_2869)
node _T_2898 = or(_T_2897, _T_2870)
node _T_2899 = or(_T_2898, _T_2871)
node _T_2900 = or(_T_2899, _T_2872)
node _T_2901 = or(_T_2900, _T_2873)
node _T_2902 = or(_T_2901, _T_2874)
node _T_2903 = or(_T_2902, _T_2875)
node _T_2904 = or(_T_2903, _T_2876)
node _T_2905 = or(_T_2904, _T_2877)
node _T_2906 = or(_T_2905, _T_2878)
wire _WIRE_7 : UInt<1>
connect _WIRE_7, _T_2906
node _T_2907 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_2908 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_2909 = and(_T_2907, _T_2908)
node _T_2910 = or(UInt<1>(0h0), _T_2909)
node _T_2911 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_2912 = cvt(_T_2911)
node _T_2913 = and(_T_2912, asSInt(UInt<17>(0h100c0)))
node _T_2914 = asSInt(_T_2913)
node _T_2915 = eq(_T_2914, asSInt(UInt<1>(0h0)))
node _T_2916 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_2917 = cvt(_T_2916)
node _T_2918 = and(_T_2917, asSInt(UInt<29>(0h100000c0)))
node _T_2919 = asSInt(_T_2918)
node _T_2920 = eq(_T_2919, asSInt(UInt<1>(0h0)))
node _T_2921 = or(_T_2915, _T_2920)
node _T_2922 = and(_T_2910, _T_2921)
node _T_2923 = or(UInt<1>(0h0), _T_2922)
node _T_2924 = and(_WIRE_7, _T_2923)
node _T_2925 = asUInt(reset)
node _T_2926 = eq(_T_2925, UInt<1>(0h0))
when _T_2926 :
node _T_2927 = eq(_T_2924, UInt<1>(0h0))
when _T_2927 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144
assert(clock, _T_2924, UInt<1>(0h1), "") : assert_144
node _T_2928 = asUInt(reset)
node _T_2929 = eq(_T_2928, UInt<1>(0h0))
when _T_2929 :
node _T_2930 = eq(source_ok_2, UInt<1>(0h0))
when _T_2930 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145
node _T_2931 = geq(io.in.c.bits.size, UInt<3>(0h4))
node _T_2932 = asUInt(reset)
node _T_2933 = eq(_T_2932, UInt<1>(0h0))
when _T_2933 :
node _T_2934 = eq(_T_2931, UInt<1>(0h0))
when _T_2934 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146
assert(clock, _T_2931, UInt<1>(0h1), "") : assert_146
node _T_2935 = asUInt(reset)
node _T_2936 = eq(_T_2935, UInt<1>(0h0))
when _T_2936 :
node _T_2937 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2937 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147
node _T_2938 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_2939 = asUInt(reset)
node _T_2940 = eq(_T_2939, UInt<1>(0h0))
when _T_2940 :
node _T_2941 = eq(_T_2938, UInt<1>(0h0))
when _T_2941 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148
assert(clock, _T_2938, UInt<1>(0h1), "") : assert_148
node _T_2942 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2943 = asUInt(reset)
node _T_2944 = eq(_T_2943, UInt<1>(0h0))
when _T_2944 :
node _T_2945 = eq(_T_2942, UInt<1>(0h0))
when _T_2945 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149
assert(clock, _T_2942, UInt<1>(0h1), "") : assert_149
node _T_2946 = eq(io.in.c.bits.opcode, UInt<3>(0h7))
when _T_2946 :
node _T_2947 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_2948 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_2949 = and(_T_2947, _T_2948)
node _T_2950 = eq(io.in.c.bits.source, UInt<5>(0h10))
node _uncommonBits_T_64 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_64 = bits(_uncommonBits_T_64, 1, 0)
node _T_2951 = shr(io.in.c.bits.source, 2)
node _T_2952 = eq(_T_2951, UInt<1>(0h0))
node _T_2953 = leq(UInt<1>(0h0), uncommonBits_64)
node _T_2954 = and(_T_2952, _T_2953)
node _T_2955 = leq(uncommonBits_64, UInt<2>(0h3))
node _T_2956 = and(_T_2954, _T_2955)
node _uncommonBits_T_65 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_65 = bits(_uncommonBits_T_65, 1, 0)
node _T_2957 = shr(io.in.c.bits.source, 2)
node _T_2958 = eq(_T_2957, UInt<1>(0h1))
node _T_2959 = leq(UInt<1>(0h0), uncommonBits_65)
node _T_2960 = and(_T_2958, _T_2959)
node _T_2961 = leq(uncommonBits_65, UInt<2>(0h3))
node _T_2962 = and(_T_2960, _T_2961)
node _uncommonBits_T_66 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0)
node _T_2963 = shr(io.in.c.bits.source, 2)
node _T_2964 = eq(_T_2963, UInt<2>(0h2))
node _T_2965 = leq(UInt<1>(0h0), uncommonBits_66)
node _T_2966 = and(_T_2964, _T_2965)
node _T_2967 = leq(uncommonBits_66, UInt<2>(0h3))
node _T_2968 = and(_T_2966, _T_2967)
node _uncommonBits_T_67 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_67 = bits(_uncommonBits_T_67, 1, 0)
node _T_2969 = shr(io.in.c.bits.source, 2)
node _T_2970 = eq(_T_2969, UInt<2>(0h3))
node _T_2971 = leq(UInt<1>(0h0), uncommonBits_67)
node _T_2972 = and(_T_2970, _T_2971)
node _T_2973 = leq(uncommonBits_67, UInt<2>(0h3))
node _T_2974 = and(_T_2972, _T_2973)
node _T_2975 = eq(io.in.c.bits.source, UInt<7>(0h4c))
node _T_2976 = eq(io.in.c.bits.source, UInt<7>(0h4e))
node _T_2977 = eq(io.in.c.bits.source, UInt<7>(0h48))
node _T_2978 = eq(io.in.c.bits.source, UInt<7>(0h4a))
node _T_2979 = eq(io.in.c.bits.source, UInt<7>(0h44))
node _T_2980 = eq(io.in.c.bits.source, UInt<7>(0h46))
node _T_2981 = eq(io.in.c.bits.source, UInt<7>(0h40))
node _T_2982 = eq(io.in.c.bits.source, UInt<7>(0h42))
node _T_2983 = eq(io.in.c.bits.source, UInt<6>(0h3c))
node _T_2984 = eq(io.in.c.bits.source, UInt<6>(0h3e))
node _T_2985 = eq(io.in.c.bits.source, UInt<6>(0h38))
node _T_2986 = eq(io.in.c.bits.source, UInt<6>(0h3a))
node _T_2987 = eq(io.in.c.bits.source, UInt<6>(0h34))
node _T_2988 = eq(io.in.c.bits.source, UInt<6>(0h36))
node _T_2989 = eq(io.in.c.bits.source, UInt<6>(0h30))
node _T_2990 = eq(io.in.c.bits.source, UInt<6>(0h32))
node _T_2991 = eq(io.in.c.bits.source, UInt<6>(0h2c))
node _T_2992 = eq(io.in.c.bits.source, UInt<6>(0h2e))
node _T_2993 = eq(io.in.c.bits.source, UInt<6>(0h28))
node _T_2994 = eq(io.in.c.bits.source, UInt<6>(0h2a))
node _T_2995 = eq(io.in.c.bits.source, UInt<6>(0h24))
node _T_2996 = eq(io.in.c.bits.source, UInt<6>(0h26))
node _T_2997 = eq(io.in.c.bits.source, UInt<6>(0h20))
node _T_2998 = eq(io.in.c.bits.source, UInt<6>(0h22))
node _T_2999 = or(_T_2950, _T_2956)
node _T_3000 = or(_T_2999, _T_2962)
node _T_3001 = or(_T_3000, _T_2968)
node _T_3002 = or(_T_3001, _T_2974)
node _T_3003 = or(_T_3002, _T_2975)
node _T_3004 = or(_T_3003, _T_2976)
node _T_3005 = or(_T_3004, _T_2977)
node _T_3006 = or(_T_3005, _T_2978)
node _T_3007 = or(_T_3006, _T_2979)
node _T_3008 = or(_T_3007, _T_2980)
node _T_3009 = or(_T_3008, _T_2981)
node _T_3010 = or(_T_3009, _T_2982)
node _T_3011 = or(_T_3010, _T_2983)
node _T_3012 = or(_T_3011, _T_2984)
node _T_3013 = or(_T_3012, _T_2985)
node _T_3014 = or(_T_3013, _T_2986)
node _T_3015 = or(_T_3014, _T_2987)
node _T_3016 = or(_T_3015, _T_2988)
node _T_3017 = or(_T_3016, _T_2989)
node _T_3018 = or(_T_3017, _T_2990)
node _T_3019 = or(_T_3018, _T_2991)
node _T_3020 = or(_T_3019, _T_2992)
node _T_3021 = or(_T_3020, _T_2993)
node _T_3022 = or(_T_3021, _T_2994)
node _T_3023 = or(_T_3022, _T_2995)
node _T_3024 = or(_T_3023, _T_2996)
node _T_3025 = or(_T_3024, _T_2997)
node _T_3026 = or(_T_3025, _T_2998)
node _T_3027 = and(_T_2949, _T_3026)
node _T_3028 = or(UInt<1>(0h0), _T_3027)
node _T_3029 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_3030 = or(UInt<1>(0h0), _T_3029)
node _T_3031 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_3032 = cvt(_T_3031)
node _T_3033 = and(_T_3032, asSInt(UInt<17>(0h100c0)))
node _T_3034 = asSInt(_T_3033)
node _T_3035 = eq(_T_3034, asSInt(UInt<1>(0h0)))
node _T_3036 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_3037 = cvt(_T_3036)
node _T_3038 = and(_T_3037, asSInt(UInt<29>(0h100000c0)))
node _T_3039 = asSInt(_T_3038)
node _T_3040 = eq(_T_3039, asSInt(UInt<1>(0h0)))
node _T_3041 = or(_T_3035, _T_3040)
node _T_3042 = and(_T_3030, _T_3041)
node _T_3043 = or(UInt<1>(0h0), _T_3042)
node _T_3044 = and(_T_3028, _T_3043)
node _T_3045 = asUInt(reset)
node _T_3046 = eq(_T_3045, UInt<1>(0h0))
when _T_3046 :
node _T_3047 = eq(_T_3044, UInt<1>(0h0))
when _T_3047 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150
assert(clock, _T_3044, UInt<1>(0h1), "") : assert_150
node _T_3048 = eq(io.in.c.bits.source, UInt<5>(0h10))
node _uncommonBits_T_68 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_68 = bits(_uncommonBits_T_68, 1, 0)
node _T_3049 = shr(io.in.c.bits.source, 2)
node _T_3050 = eq(_T_3049, UInt<1>(0h0))
node _T_3051 = leq(UInt<1>(0h0), uncommonBits_68)
node _T_3052 = and(_T_3050, _T_3051)
node _T_3053 = leq(uncommonBits_68, UInt<2>(0h3))
node _T_3054 = and(_T_3052, _T_3053)
node _uncommonBits_T_69 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_69 = bits(_uncommonBits_T_69, 1, 0)
node _T_3055 = shr(io.in.c.bits.source, 2)
node _T_3056 = eq(_T_3055, UInt<1>(0h1))
node _T_3057 = leq(UInt<1>(0h0), uncommonBits_69)
node _T_3058 = and(_T_3056, _T_3057)
node _T_3059 = leq(uncommonBits_69, UInt<2>(0h3))
node _T_3060 = and(_T_3058, _T_3059)
node _uncommonBits_T_70 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_70 = bits(_uncommonBits_T_70, 1, 0)
node _T_3061 = shr(io.in.c.bits.source, 2)
node _T_3062 = eq(_T_3061, UInt<2>(0h2))
node _T_3063 = leq(UInt<1>(0h0), uncommonBits_70)
node _T_3064 = and(_T_3062, _T_3063)
node _T_3065 = leq(uncommonBits_70, UInt<2>(0h3))
node _T_3066 = and(_T_3064, _T_3065)
node _uncommonBits_T_71 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_71 = bits(_uncommonBits_T_71, 1, 0)
node _T_3067 = shr(io.in.c.bits.source, 2)
node _T_3068 = eq(_T_3067, UInt<2>(0h3))
node _T_3069 = leq(UInt<1>(0h0), uncommonBits_71)
node _T_3070 = and(_T_3068, _T_3069)
node _T_3071 = leq(uncommonBits_71, UInt<2>(0h3))
node _T_3072 = and(_T_3070, _T_3071)
node _T_3073 = eq(io.in.c.bits.source, UInt<7>(0h4c))
node _T_3074 = eq(io.in.c.bits.source, UInt<7>(0h4e))
node _T_3075 = eq(io.in.c.bits.source, UInt<7>(0h48))
node _T_3076 = eq(io.in.c.bits.source, UInt<7>(0h4a))
node _T_3077 = eq(io.in.c.bits.source, UInt<7>(0h44))
node _T_3078 = eq(io.in.c.bits.source, UInt<7>(0h46))
node _T_3079 = eq(io.in.c.bits.source, UInt<7>(0h40))
node _T_3080 = eq(io.in.c.bits.source, UInt<7>(0h42))
node _T_3081 = eq(io.in.c.bits.source, UInt<6>(0h3c))
node _T_3082 = eq(io.in.c.bits.source, UInt<6>(0h3e))
node _T_3083 = eq(io.in.c.bits.source, UInt<6>(0h38))
node _T_3084 = eq(io.in.c.bits.source, UInt<6>(0h3a))
node _T_3085 = eq(io.in.c.bits.source, UInt<6>(0h34))
node _T_3086 = eq(io.in.c.bits.source, UInt<6>(0h36))
node _T_3087 = eq(io.in.c.bits.source, UInt<6>(0h30))
node _T_3088 = eq(io.in.c.bits.source, UInt<6>(0h32))
node _T_3089 = eq(io.in.c.bits.source, UInt<6>(0h2c))
node _T_3090 = eq(io.in.c.bits.source, UInt<6>(0h2e))
node _T_3091 = eq(io.in.c.bits.source, UInt<6>(0h28))
node _T_3092 = eq(io.in.c.bits.source, UInt<6>(0h2a))
node _T_3093 = eq(io.in.c.bits.source, UInt<6>(0h24))
node _T_3094 = eq(io.in.c.bits.source, UInt<6>(0h26))
node _T_3095 = eq(io.in.c.bits.source, UInt<6>(0h20))
node _T_3096 = eq(io.in.c.bits.source, UInt<6>(0h22))
wire _WIRE_8 : UInt<1>[29]
connect _WIRE_8[0], _T_3048
connect _WIRE_8[1], _T_3054
connect _WIRE_8[2], _T_3060
connect _WIRE_8[3], _T_3066
connect _WIRE_8[4], _T_3072
connect _WIRE_8[5], _T_3073
connect _WIRE_8[6], _T_3074
connect _WIRE_8[7], _T_3075
connect _WIRE_8[8], _T_3076
connect _WIRE_8[9], _T_3077
connect _WIRE_8[10], _T_3078
connect _WIRE_8[11], _T_3079
connect _WIRE_8[12], _T_3080
connect _WIRE_8[13], _T_3081
connect _WIRE_8[14], _T_3082
connect _WIRE_8[15], _T_3083
connect _WIRE_8[16], _T_3084
connect _WIRE_8[17], _T_3085
connect _WIRE_8[18], _T_3086
connect _WIRE_8[19], _T_3087
connect _WIRE_8[20], _T_3088
connect _WIRE_8[21], _T_3089
connect _WIRE_8[22], _T_3090
connect _WIRE_8[23], _T_3091
connect _WIRE_8[24], _T_3092
connect _WIRE_8[25], _T_3093
connect _WIRE_8[26], _T_3094
connect _WIRE_8[27], _T_3095
connect _WIRE_8[28], _T_3096
node _T_3097 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_3098 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_3099 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_3100 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_3101 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_3102 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_3103 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_3104 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_3105 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_3106 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_3107 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_3108 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_3109 = mux(_WIRE_8[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_3110 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_3111 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_3112 = mux(_WIRE_8[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_3113 = mux(_WIRE_8[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_3114 = mux(_WIRE_8[5], _T_3097, UInt<1>(0h0))
node _T_3115 = mux(_WIRE_8[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_3116 = mux(_WIRE_8[7], _T_3098, UInt<1>(0h0))
node _T_3117 = mux(_WIRE_8[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_3118 = mux(_WIRE_8[9], _T_3099, UInt<1>(0h0))
node _T_3119 = mux(_WIRE_8[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_3120 = mux(_WIRE_8[11], _T_3100, UInt<1>(0h0))
node _T_3121 = mux(_WIRE_8[12], UInt<1>(0h0), UInt<1>(0h0))
node _T_3122 = mux(_WIRE_8[13], _T_3101, UInt<1>(0h0))
node _T_3123 = mux(_WIRE_8[14], UInt<1>(0h0), UInt<1>(0h0))
node _T_3124 = mux(_WIRE_8[15], _T_3102, UInt<1>(0h0))
node _T_3125 = mux(_WIRE_8[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_3126 = mux(_WIRE_8[17], _T_3103, UInt<1>(0h0))
node _T_3127 = mux(_WIRE_8[18], UInt<1>(0h0), UInt<1>(0h0))
node _T_3128 = mux(_WIRE_8[19], _T_3104, UInt<1>(0h0))
node _T_3129 = mux(_WIRE_8[20], UInt<1>(0h0), UInt<1>(0h0))
node _T_3130 = mux(_WIRE_8[21], _T_3105, UInt<1>(0h0))
node _T_3131 = mux(_WIRE_8[22], UInt<1>(0h0), UInt<1>(0h0))
node _T_3132 = mux(_WIRE_8[23], _T_3106, UInt<1>(0h0))
node _T_3133 = mux(_WIRE_8[24], UInt<1>(0h0), UInt<1>(0h0))
node _T_3134 = mux(_WIRE_8[25], _T_3107, UInt<1>(0h0))
node _T_3135 = mux(_WIRE_8[26], UInt<1>(0h0), UInt<1>(0h0))
node _T_3136 = mux(_WIRE_8[27], _T_3108, UInt<1>(0h0))
node _T_3137 = mux(_WIRE_8[28], UInt<1>(0h0), UInt<1>(0h0))
node _T_3138 = or(_T_3109, _T_3110)
node _T_3139 = or(_T_3138, _T_3111)
node _T_3140 = or(_T_3139, _T_3112)
node _T_3141 = or(_T_3140, _T_3113)
node _T_3142 = or(_T_3141, _T_3114)
node _T_3143 = or(_T_3142, _T_3115)
node _T_3144 = or(_T_3143, _T_3116)
node _T_3145 = or(_T_3144, _T_3117)
node _T_3146 = or(_T_3145, _T_3118)
node _T_3147 = or(_T_3146, _T_3119)
node _T_3148 = or(_T_3147, _T_3120)
node _T_3149 = or(_T_3148, _T_3121)
node _T_3150 = or(_T_3149, _T_3122)
node _T_3151 = or(_T_3150, _T_3123)
node _T_3152 = or(_T_3151, _T_3124)
node _T_3153 = or(_T_3152, _T_3125)
node _T_3154 = or(_T_3153, _T_3126)
node _T_3155 = or(_T_3154, _T_3127)
node _T_3156 = or(_T_3155, _T_3128)
node _T_3157 = or(_T_3156, _T_3129)
node _T_3158 = or(_T_3157, _T_3130)
node _T_3159 = or(_T_3158, _T_3131)
node _T_3160 = or(_T_3159, _T_3132)
node _T_3161 = or(_T_3160, _T_3133)
node _T_3162 = or(_T_3161, _T_3134)
node _T_3163 = or(_T_3162, _T_3135)
node _T_3164 = or(_T_3163, _T_3136)
node _T_3165 = or(_T_3164, _T_3137)
wire _WIRE_9 : UInt<1>
connect _WIRE_9, _T_3165
node _T_3166 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_3167 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_3168 = and(_T_3166, _T_3167)
node _T_3169 = or(UInt<1>(0h0), _T_3168)
node _T_3170 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_3171 = cvt(_T_3170)
node _T_3172 = and(_T_3171, asSInt(UInt<17>(0h100c0)))
node _T_3173 = asSInt(_T_3172)
node _T_3174 = eq(_T_3173, asSInt(UInt<1>(0h0)))
node _T_3175 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_3176 = cvt(_T_3175)
node _T_3177 = and(_T_3176, asSInt(UInt<29>(0h100000c0)))
node _T_3178 = asSInt(_T_3177)
node _T_3179 = eq(_T_3178, asSInt(UInt<1>(0h0)))
node _T_3180 = or(_T_3174, _T_3179)
node _T_3181 = and(_T_3169, _T_3180)
node _T_3182 = or(UInt<1>(0h0), _T_3181)
node _T_3183 = and(_WIRE_9, _T_3182)
node _T_3184 = asUInt(reset)
node _T_3185 = eq(_T_3184, UInt<1>(0h0))
when _T_3185 :
node _T_3186 = eq(_T_3183, UInt<1>(0h0))
when _T_3186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151
assert(clock, _T_3183, UInt<1>(0h1), "") : assert_151
node _T_3187 = asUInt(reset)
node _T_3188 = eq(_T_3187, UInt<1>(0h0))
when _T_3188 :
node _T_3189 = eq(source_ok_2, UInt<1>(0h0))
when _T_3189 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152
node _T_3190 = geq(io.in.c.bits.size, UInt<3>(0h4))
node _T_3191 = asUInt(reset)
node _T_3192 = eq(_T_3191, UInt<1>(0h0))
when _T_3192 :
node _T_3193 = eq(_T_3190, UInt<1>(0h0))
when _T_3193 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153
assert(clock, _T_3190, UInt<1>(0h1), "") : assert_153
node _T_3194 = asUInt(reset)
node _T_3195 = eq(_T_3194, UInt<1>(0h0))
when _T_3195 :
node _T_3196 = eq(is_aligned_2, UInt<1>(0h0))
when _T_3196 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154
node _T_3197 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_3198 = asUInt(reset)
node _T_3199 = eq(_T_3198, UInt<1>(0h0))
when _T_3199 :
node _T_3200 = eq(_T_3197, UInt<1>(0h0))
when _T_3200 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155
assert(clock, _T_3197, UInt<1>(0h1), "") : assert_155
node _T_3201 = eq(io.in.c.bits.opcode, UInt<1>(0h0))
when _T_3201 :
node _T_3202 = asUInt(reset)
node _T_3203 = eq(_T_3202, UInt<1>(0h0))
when _T_3203 :
node _T_3204 = eq(address_ok_1, UInt<1>(0h0))
when _T_3204 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156
node _T_3205 = asUInt(reset)
node _T_3206 = eq(_T_3205, UInt<1>(0h0))
when _T_3206 :
node _T_3207 = eq(source_ok_2, UInt<1>(0h0))
when _T_3207 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157
node _T_3208 = asUInt(reset)
node _T_3209 = eq(_T_3208, UInt<1>(0h0))
when _T_3209 :
node _T_3210 = eq(is_aligned_2, UInt<1>(0h0))
when _T_3210 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158
node _T_3211 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_3212 = asUInt(reset)
node _T_3213 = eq(_T_3212, UInt<1>(0h0))
when _T_3213 :
node _T_3214 = eq(_T_3211, UInt<1>(0h0))
when _T_3214 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159
assert(clock, _T_3211, UInt<1>(0h1), "") : assert_159
node _T_3215 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_3216 = asUInt(reset)
node _T_3217 = eq(_T_3216, UInt<1>(0h0))
when _T_3217 :
node _T_3218 = eq(_T_3215, UInt<1>(0h0))
when _T_3218 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160
assert(clock, _T_3215, UInt<1>(0h1), "") : assert_160
node _T_3219 = eq(io.in.c.bits.opcode, UInt<1>(0h1))
when _T_3219 :
node _T_3220 = asUInt(reset)
node _T_3221 = eq(_T_3220, UInt<1>(0h0))
when _T_3221 :
node _T_3222 = eq(address_ok_1, UInt<1>(0h0))
when _T_3222 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161
node _T_3223 = asUInt(reset)
node _T_3224 = eq(_T_3223, UInt<1>(0h0))
when _T_3224 :
node _T_3225 = eq(source_ok_2, UInt<1>(0h0))
when _T_3225 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162
node _T_3226 = asUInt(reset)
node _T_3227 = eq(_T_3226, UInt<1>(0h0))
when _T_3227 :
node _T_3228 = eq(is_aligned_2, UInt<1>(0h0))
when _T_3228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163
node _T_3229 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_3230 = asUInt(reset)
node _T_3231 = eq(_T_3230, UInt<1>(0h0))
when _T_3231 :
node _T_3232 = eq(_T_3229, UInt<1>(0h0))
when _T_3232 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164
assert(clock, _T_3229, UInt<1>(0h1), "") : assert_164
node _T_3233 = eq(io.in.c.bits.opcode, UInt<2>(0h2))
when _T_3233 :
node _T_3234 = asUInt(reset)
node _T_3235 = eq(_T_3234, UInt<1>(0h0))
when _T_3235 :
node _T_3236 = eq(address_ok_1, UInt<1>(0h0))
when _T_3236 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165
node _T_3237 = asUInt(reset)
node _T_3238 = eq(_T_3237, UInt<1>(0h0))
when _T_3238 :
node _T_3239 = eq(source_ok_2, UInt<1>(0h0))
when _T_3239 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166
node _T_3240 = asUInt(reset)
node _T_3241 = eq(_T_3240, UInt<1>(0h0))
when _T_3241 :
node _T_3242 = eq(is_aligned_2, UInt<1>(0h0))
when _T_3242 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167
node _T_3243 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_3244 = asUInt(reset)
node _T_3245 = eq(_T_3244, UInt<1>(0h0))
when _T_3245 :
node _T_3246 = eq(_T_3243, UInt<1>(0h0))
when _T_3246 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168
assert(clock, _T_3243, UInt<1>(0h1), "") : assert_168
node _T_3247 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_3248 = asUInt(reset)
node _T_3249 = eq(_T_3248, UInt<1>(0h0))
when _T_3249 :
node _T_3250 = eq(_T_3247, UInt<1>(0h0))
when _T_3250 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169
assert(clock, _T_3247, UInt<1>(0h1), "") : assert_169
when io.in.e.valid :
node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0hc))
node _T_3251 = asUInt(reset)
node _T_3252 = eq(_T_3251, UInt<1>(0h0))
when _T_3252 :
node _T_3253 = eq(sink_ok_1, UInt<1>(0h0))
when _T_3253 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170
assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<2>, clock, reset, UInt<2>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_3254 = eq(a_first, UInt<1>(0h0))
node _T_3255 = and(io.in.a.valid, _T_3254)
when _T_3255 :
node _T_3256 = eq(io.in.a.bits.opcode, opcode)
node _T_3257 = asUInt(reset)
node _T_3258 = eq(_T_3257, UInt<1>(0h0))
when _T_3258 :
node _T_3259 = eq(_T_3256, UInt<1>(0h0))
when _T_3259 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171
assert(clock, _T_3256, UInt<1>(0h1), "") : assert_171
node _T_3260 = eq(io.in.a.bits.param, param)
node _T_3261 = asUInt(reset)
node _T_3262 = eq(_T_3261, UInt<1>(0h0))
when _T_3262 :
node _T_3263 = eq(_T_3260, UInt<1>(0h0))
when _T_3263 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172
assert(clock, _T_3260, UInt<1>(0h1), "") : assert_172
node _T_3264 = eq(io.in.a.bits.size, size)
node _T_3265 = asUInt(reset)
node _T_3266 = eq(_T_3265, UInt<1>(0h0))
when _T_3266 :
node _T_3267 = eq(_T_3264, UInt<1>(0h0))
when _T_3267 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173
assert(clock, _T_3264, UInt<1>(0h1), "") : assert_173
node _T_3268 = eq(io.in.a.bits.source, source)
node _T_3269 = asUInt(reset)
node _T_3270 = eq(_T_3269, UInt<1>(0h0))
when _T_3270 :
node _T_3271 = eq(_T_3268, UInt<1>(0h0))
when _T_3271 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174
assert(clock, _T_3268, UInt<1>(0h1), "") : assert_174
node _T_3272 = eq(io.in.a.bits.address, address)
node _T_3273 = asUInt(reset)
node _T_3274 = eq(_T_3273, UInt<1>(0h0))
when _T_3274 :
node _T_3275 = eq(_T_3272, UInt<1>(0h0))
when _T_3275 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175
assert(clock, _T_3272, UInt<1>(0h1), "") : assert_175
node _T_3276 = and(io.in.a.ready, io.in.a.valid)
node _T_3277 = and(_T_3276, a_first)
when _T_3277 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<2>, clock, reset, UInt<2>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_3278 = eq(d_first, UInt<1>(0h0))
node _T_3279 = and(io.in.d.valid, _T_3278)
when _T_3279 :
node _T_3280 = eq(io.in.d.bits.opcode, opcode_1)
node _T_3281 = asUInt(reset)
node _T_3282 = eq(_T_3281, UInt<1>(0h0))
when _T_3282 :
node _T_3283 = eq(_T_3280, UInt<1>(0h0))
when _T_3283 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176
assert(clock, _T_3280, UInt<1>(0h1), "") : assert_176
node _T_3284 = eq(io.in.d.bits.param, param_1)
node _T_3285 = asUInt(reset)
node _T_3286 = eq(_T_3285, UInt<1>(0h0))
when _T_3286 :
node _T_3287 = eq(_T_3284, UInt<1>(0h0))
when _T_3287 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177
assert(clock, _T_3284, UInt<1>(0h1), "") : assert_177
node _T_3288 = eq(io.in.d.bits.size, size_1)
node _T_3289 = asUInt(reset)
node _T_3290 = eq(_T_3289, UInt<1>(0h0))
when _T_3290 :
node _T_3291 = eq(_T_3288, UInt<1>(0h0))
when _T_3291 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178
assert(clock, _T_3288, UInt<1>(0h1), "") : assert_178
node _T_3292 = eq(io.in.d.bits.source, source_1)
node _T_3293 = asUInt(reset)
node _T_3294 = eq(_T_3293, UInt<1>(0h0))
when _T_3294 :
node _T_3295 = eq(_T_3292, UInt<1>(0h0))
when _T_3295 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179
assert(clock, _T_3292, UInt<1>(0h1), "") : assert_179
node _T_3296 = eq(io.in.d.bits.sink, sink)
node _T_3297 = asUInt(reset)
node _T_3298 = eq(_T_3297, UInt<1>(0h0))
when _T_3298 :
node _T_3299 = eq(_T_3296, UInt<1>(0h0))
when _T_3299 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180
assert(clock, _T_3296, UInt<1>(0h1), "") : assert_180
node _T_3300 = eq(io.in.d.bits.denied, denied)
node _T_3301 = asUInt(reset)
node _T_3302 = eq(_T_3301, UInt<1>(0h0))
when _T_3302 :
node _T_3303 = eq(_T_3300, UInt<1>(0h0))
when _T_3303 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181
assert(clock, _T_3300, UInt<1>(0h1), "") : assert_181
node _T_3304 = and(io.in.d.ready, io.in.d.valid)
node _T_3305 = and(_T_3304, d_first)
when _T_3305 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
node _b_first_T = and(io.in.b.ready, io.in.b.valid)
node _b_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.b.bits.size)
node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 5, 0)
node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1)
node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 4)
node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2)
node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0))
node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0))
regreset b_first_counter : UInt<2>, clock, reset, UInt<2>(0h0)
node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1))
node b_first_counter1 = tail(_b_first_counter1_T, 1)
node b_first = eq(b_first_counter, UInt<1>(0h0))
node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1))
node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0))
node b_first_last = or(_b_first_last_T, _b_first_last_T_1)
node b_first_done = and(b_first_last, _b_first_T)
node _b_first_count_T = not(b_first_counter1)
node b_first_count = and(b_first_beats1, _b_first_count_T)
when _b_first_T :
node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1)
connect b_first_counter, _b_first_counter_T
reg opcode_2 : UInt, clock
reg param_2 : UInt, clock
reg size_2 : UInt, clock
reg source_2 : UInt, clock
reg address_1 : UInt, clock
node _T_3306 = eq(b_first, UInt<1>(0h0))
node _T_3307 = and(io.in.b.valid, _T_3306)
when _T_3307 :
node _T_3308 = eq(io.in.b.bits.opcode, opcode_2)
node _T_3309 = asUInt(reset)
node _T_3310 = eq(_T_3309, UInt<1>(0h0))
when _T_3310 :
node _T_3311 = eq(_T_3308, UInt<1>(0h0))
when _T_3311 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182
assert(clock, _T_3308, UInt<1>(0h1), "") : assert_182
node _T_3312 = eq(io.in.b.bits.param, param_2)
node _T_3313 = asUInt(reset)
node _T_3314 = eq(_T_3313, UInt<1>(0h0))
when _T_3314 :
node _T_3315 = eq(_T_3312, UInt<1>(0h0))
when _T_3315 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183
assert(clock, _T_3312, UInt<1>(0h1), "") : assert_183
node _T_3316 = eq(io.in.b.bits.size, size_2)
node _T_3317 = asUInt(reset)
node _T_3318 = eq(_T_3317, UInt<1>(0h0))
when _T_3318 :
node _T_3319 = eq(_T_3316, UInt<1>(0h0))
when _T_3319 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184
assert(clock, _T_3316, UInt<1>(0h1), "") : assert_184
node _T_3320 = eq(io.in.b.bits.source, source_2)
node _T_3321 = asUInt(reset)
node _T_3322 = eq(_T_3321, UInt<1>(0h0))
when _T_3322 :
node _T_3323 = eq(_T_3320, UInt<1>(0h0))
when _T_3323 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185
assert(clock, _T_3320, UInt<1>(0h1), "") : assert_185
node _T_3324 = eq(io.in.b.bits.address, address_1)
node _T_3325 = asUInt(reset)
node _T_3326 = eq(_T_3325, UInt<1>(0h0))
when _T_3326 :
node _T_3327 = eq(_T_3324, UInt<1>(0h0))
when _T_3327 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186
assert(clock, _T_3324, UInt<1>(0h1), "") : assert_186
node _T_3328 = and(io.in.b.ready, io.in.b.valid)
node _T_3329 = and(_T_3328, b_first)
when _T_3329 :
connect opcode_2, io.in.b.bits.opcode
connect param_2, io.in.b.bits.param
connect size_2, io.in.b.bits.size
connect source_2, io.in.b.bits.source
connect address_1, io.in.b.bits.address
node _c_first_T = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.c.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4)
node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<2>, clock, reset, UInt<2>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
reg opcode_3 : UInt, clock
reg param_3 : UInt, clock
reg size_3 : UInt, clock
reg source_3 : UInt, clock
reg address_2 : UInt, clock
node _T_3330 = eq(c_first, UInt<1>(0h0))
node _T_3331 = and(io.in.c.valid, _T_3330)
when _T_3331 :
node _T_3332 = eq(io.in.c.bits.opcode, opcode_3)
node _T_3333 = asUInt(reset)
node _T_3334 = eq(_T_3333, UInt<1>(0h0))
when _T_3334 :
node _T_3335 = eq(_T_3332, UInt<1>(0h0))
when _T_3335 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187
assert(clock, _T_3332, UInt<1>(0h1), "") : assert_187
node _T_3336 = eq(io.in.c.bits.param, param_3)
node _T_3337 = asUInt(reset)
node _T_3338 = eq(_T_3337, UInt<1>(0h0))
when _T_3338 :
node _T_3339 = eq(_T_3336, UInt<1>(0h0))
when _T_3339 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188
assert(clock, _T_3336, UInt<1>(0h1), "") : assert_188
node _T_3340 = eq(io.in.c.bits.size, size_3)
node _T_3341 = asUInt(reset)
node _T_3342 = eq(_T_3341, UInt<1>(0h0))
when _T_3342 :
node _T_3343 = eq(_T_3340, UInt<1>(0h0))
when _T_3343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189
assert(clock, _T_3340, UInt<1>(0h1), "") : assert_189
node _T_3344 = eq(io.in.c.bits.source, source_3)
node _T_3345 = asUInt(reset)
node _T_3346 = eq(_T_3345, UInt<1>(0h0))
when _T_3346 :
node _T_3347 = eq(_T_3344, UInt<1>(0h0))
when _T_3347 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190
assert(clock, _T_3344, UInt<1>(0h1), "") : assert_190
node _T_3348 = eq(io.in.c.bits.address, address_2)
node _T_3349 = asUInt(reset)
node _T_3350 = eq(_T_3349, UInt<1>(0h0))
when _T_3350 :
node _T_3351 = eq(_T_3348, UInt<1>(0h0))
when _T_3351 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191
assert(clock, _T_3348, UInt<1>(0h1), "") : assert_191
node _T_3352 = and(io.in.c.ready, io.in.c.valid)
node _T_3353 = and(_T_3352, c_first)
when _T_3353 :
connect opcode_3, io.in.c.bits.opcode
connect param_3, io.in.c.bits.param
connect size_3, io.in.c.bits.size
connect source_3, io.in.c.bits.source
connect address_2, io.in.c.bits.address
regreset inflight : UInt<79>, clock, reset, UInt<79>(0h0)
regreset inflight_opcodes : UInt<316>, clock, reset, UInt<316>(0h0)
regreset inflight_sizes : UInt<316>, clock, reset, UInt<316>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<2>, clock, reset, UInt<2>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<2>, clock, reset, UInt<2>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<79>
connect a_set, UInt<79>(0h0)
wire a_set_wo_ready : UInt<79>
connect a_set_wo_ready, UInt<79>(0h0)
wire a_opcodes_set : UInt<316>
connect a_opcodes_set, UInt<316>(0h0)
wire a_sizes_set : UInt<316>
connect a_sizes_set, UInt<316>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_3354 = and(io.in.a.valid, a_first_1)
node _T_3355 = and(_T_3354, UInt<1>(0h1))
when _T_3355 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_3356 = and(io.in.a.ready, io.in.a.valid)
node _T_3357 = and(_T_3356, a_first_1)
node _T_3358 = and(_T_3357, UInt<1>(0h1))
when _T_3358 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_3359 = dshr(inflight, io.in.a.bits.source)
node _T_3360 = bits(_T_3359, 0, 0)
node _T_3361 = eq(_T_3360, UInt<1>(0h0))
node _T_3362 = asUInt(reset)
node _T_3363 = eq(_T_3362, UInt<1>(0h0))
when _T_3363 :
node _T_3364 = eq(_T_3361, UInt<1>(0h0))
when _T_3364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192
assert(clock, _T_3361, UInt<1>(0h1), "") : assert_192
wire d_clr : UInt<79>
connect d_clr, UInt<79>(0h0)
wire d_clr_wo_ready : UInt<79>
connect d_clr_wo_ready, UInt<79>(0h0)
wire d_opcodes_clr : UInt<316>
connect d_opcodes_clr, UInt<316>(0h0)
wire d_sizes_clr : UInt<316>
connect d_sizes_clr, UInt<316>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_3365 = and(io.in.d.valid, d_first_1)
node _T_3366 = and(_T_3365, UInt<1>(0h1))
node _T_3367 = eq(d_release_ack, UInt<1>(0h0))
node _T_3368 = and(_T_3366, _T_3367)
when _T_3368 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_3369 = and(io.in.d.ready, io.in.d.valid)
node _T_3370 = and(_T_3369, d_first_1)
node _T_3371 = and(_T_3370, UInt<1>(0h1))
node _T_3372 = eq(d_release_ack, UInt<1>(0h0))
node _T_3373 = and(_T_3371, _T_3372)
when _T_3373 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_3374 = and(io.in.d.valid, d_first_1)
node _T_3375 = and(_T_3374, UInt<1>(0h1))
node _T_3376 = eq(d_release_ack, UInt<1>(0h0))
node _T_3377 = and(_T_3375, _T_3376)
when _T_3377 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_3378 = dshr(inflight, io.in.d.bits.source)
node _T_3379 = bits(_T_3378, 0, 0)
node _T_3380 = or(_T_3379, same_cycle_resp)
node _T_3381 = asUInt(reset)
node _T_3382 = eq(_T_3381, UInt<1>(0h0))
when _T_3382 :
node _T_3383 = eq(_T_3380, UInt<1>(0h0))
when _T_3383 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193
assert(clock, _T_3380, UInt<1>(0h1), "") : assert_193
when same_cycle_resp :
node _T_3384 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_3385 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_3386 = or(_T_3384, _T_3385)
node _T_3387 = asUInt(reset)
node _T_3388 = eq(_T_3387, UInt<1>(0h0))
when _T_3388 :
node _T_3389 = eq(_T_3386, UInt<1>(0h0))
when _T_3389 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194
assert(clock, _T_3386, UInt<1>(0h1), "") : assert_194
node _T_3390 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_3391 = asUInt(reset)
node _T_3392 = eq(_T_3391, UInt<1>(0h0))
when _T_3392 :
node _T_3393 = eq(_T_3390, UInt<1>(0h0))
when _T_3393 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195
assert(clock, _T_3390, UInt<1>(0h1), "") : assert_195
else :
node _T_3394 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_3395 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_3396 = or(_T_3394, _T_3395)
node _T_3397 = asUInt(reset)
node _T_3398 = eq(_T_3397, UInt<1>(0h0))
when _T_3398 :
node _T_3399 = eq(_T_3396, UInt<1>(0h0))
when _T_3399 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196
assert(clock, _T_3396, UInt<1>(0h1), "") : assert_196
node _T_3400 = eq(io.in.d.bits.size, a_size_lookup)
node _T_3401 = asUInt(reset)
node _T_3402 = eq(_T_3401, UInt<1>(0h0))
when _T_3402 :
node _T_3403 = eq(_T_3400, UInt<1>(0h0))
when _T_3403 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197
assert(clock, _T_3400, UInt<1>(0h1), "") : assert_197
node _T_3404 = and(io.in.d.valid, d_first_1)
node _T_3405 = and(_T_3404, a_first_1)
node _T_3406 = and(_T_3405, io.in.a.valid)
node _T_3407 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_3408 = and(_T_3406, _T_3407)
node _T_3409 = eq(d_release_ack, UInt<1>(0h0))
node _T_3410 = and(_T_3408, _T_3409)
when _T_3410 :
node _T_3411 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_3412 = or(_T_3411, io.in.a.ready)
node _T_3413 = asUInt(reset)
node _T_3414 = eq(_T_3413, UInt<1>(0h0))
when _T_3414 :
node _T_3415 = eq(_T_3412, UInt<1>(0h0))
when _T_3415 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198
assert(clock, _T_3412, UInt<1>(0h1), "") : assert_198
node _T_3416 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_3417 = orr(a_set_wo_ready)
node _T_3418 = eq(_T_3417, UInt<1>(0h0))
node _T_3419 = or(_T_3416, _T_3418)
node _T_3420 = asUInt(reset)
node _T_3421 = eq(_T_3420, UInt<1>(0h0))
when _T_3421 :
node _T_3422 = eq(_T_3419, UInt<1>(0h0))
when _T_3422 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199
assert(clock, _T_3419, UInt<1>(0h1), "") : assert_199
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_132
node _T_3423 = orr(inflight)
node _T_3424 = eq(_T_3423, UInt<1>(0h0))
node _T_3425 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_3426 = or(_T_3424, _T_3425)
node _T_3427 = lt(watchdog, plusarg_reader.out)
node _T_3428 = or(_T_3426, _T_3427)
node _T_3429 = asUInt(reset)
node _T_3430 = eq(_T_3429, UInt<1>(0h0))
when _T_3430 :
node _T_3431 = eq(_T_3428, UInt<1>(0h0))
when _T_3431 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200
assert(clock, _T_3428, UInt<1>(0h1), "") : assert_200
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_3432 = and(io.in.a.ready, io.in.a.valid)
node _T_3433 = and(io.in.d.ready, io.in.d.valid)
node _T_3434 = or(_T_3432, _T_3433)
when _T_3434 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<79>, clock, reset, UInt<79>(0h0)
regreset inflight_opcodes_1 : UInt<316>, clock, reset, UInt<316>(0h0)
regreset inflight_sizes_1 : UInt<316>, clock, reset, UInt<316>(0h0)
node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.c.bits.size)
node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 5, 0)
node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4)
node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 4)
node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0))
regreset c_first_counter_1 : UInt<2>, clock, reset, UInt<2>(0h0)
node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1))
node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1)
node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0))
node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1))
node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0))
node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3)
node c_first_done_1 = and(c_first_last_1, _c_first_T_1)
node _c_first_count_T_1 = not(c_first_counter1_1)
node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1)
when _c_first_T_1 :
node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1)
connect c_first_counter_1, _c_first_counter_T_1
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<2>, clock, reset, UInt<2>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<79>
connect c_set, UInt<79>(0h0)
wire c_set_wo_ready : UInt<79>
connect c_set_wo_ready, UInt<79>(0h0)
wire c_opcodes_set : UInt<316>
connect c_opcodes_set, UInt<316>(0h0)
wire c_sizes_set : UInt<316>
connect c_sizes_set, UInt<316>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
node _T_3435 = and(io.in.c.valid, c_first_1)
node _T_3436 = bits(io.in.c.bits.opcode, 2, 2)
node _T_3437 = bits(io.in.c.bits.opcode, 1, 1)
node _T_3438 = and(_T_3436, _T_3437)
node _T_3439 = and(_T_3435, _T_3438)
when _T_3439 :
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
node _T_3440 = and(io.in.c.ready, io.in.c.valid)
node _T_3441 = and(_T_3440, c_first_1)
node _T_3442 = bits(io.in.c.bits.opcode, 2, 2)
node _T_3443 = bits(io.in.c.bits.opcode, 1, 1)
node _T_3444 = and(_T_3442, _T_3443)
node _T_3445 = and(_T_3441, _T_3444)
when _T_3445 :
node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set, _c_set_T
node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
node _T_3446 = dshr(inflight_1, io.in.c.bits.source)
node _T_3447 = bits(_T_3446, 0, 0)
node _T_3448 = eq(_T_3447, UInt<1>(0h0))
node _T_3449 = asUInt(reset)
node _T_3450 = eq(_T_3449, UInt<1>(0h0))
when _T_3450 :
node _T_3451 = eq(_T_3448, UInt<1>(0h0))
when _T_3451 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201
assert(clock, _T_3448, UInt<1>(0h1), "") : assert_201
node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4))
node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<79>
connect d_clr_1, UInt<79>(0h0)
wire d_clr_wo_ready_1 : UInt<79>
connect d_clr_wo_ready_1, UInt<79>(0h0)
wire d_opcodes_clr_1 : UInt<316>
connect d_opcodes_clr_1, UInt<316>(0h0)
wire d_sizes_clr_1 : UInt<316>
connect d_sizes_clr_1, UInt<316>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_3452 = and(io.in.d.valid, d_first_2)
node _T_3453 = and(_T_3452, UInt<1>(0h1))
node _T_3454 = and(_T_3453, d_release_ack_1)
when _T_3454 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_3455 = and(io.in.d.ready, io.in.d.valid)
node _T_3456 = and(_T_3455, d_first_2)
node _T_3457 = and(_T_3456, UInt<1>(0h1))
node _T_3458 = and(_T_3457, d_release_ack_1)
when _T_3458 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_3459 = and(io.in.d.valid, d_first_2)
node _T_3460 = and(_T_3459, UInt<1>(0h1))
node _T_3461 = and(_T_3460, d_release_ack_1)
when _T_3461 :
node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1)
node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_3462 = dshr(inflight_1, io.in.d.bits.source)
node _T_3463 = bits(_T_3462, 0, 0)
node _T_3464 = or(_T_3463, same_cycle_resp_1)
node _T_3465 = asUInt(reset)
node _T_3466 = eq(_T_3465, UInt<1>(0h0))
when _T_3466 :
node _T_3467 = eq(_T_3464, UInt<1>(0h0))
when _T_3467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202
assert(clock, _T_3464, UInt<1>(0h1), "") : assert_202
when same_cycle_resp_1 :
node _T_3468 = eq(io.in.d.bits.size, io.in.c.bits.size)
node _T_3469 = asUInt(reset)
node _T_3470 = eq(_T_3469, UInt<1>(0h0))
when _T_3470 :
node _T_3471 = eq(_T_3468, UInt<1>(0h0))
when _T_3471 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203
assert(clock, _T_3468, UInt<1>(0h1), "") : assert_203
else :
node _T_3472 = eq(io.in.d.bits.size, c_size_lookup)
node _T_3473 = asUInt(reset)
node _T_3474 = eq(_T_3473, UInt<1>(0h0))
when _T_3474 :
node _T_3475 = eq(_T_3472, UInt<1>(0h0))
when _T_3475 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204
assert(clock, _T_3472, UInt<1>(0h1), "") : assert_204
node _T_3476 = and(io.in.d.valid, d_first_2)
node _T_3477 = and(_T_3476, c_first_1)
node _T_3478 = and(_T_3477, io.in.c.valid)
node _T_3479 = eq(io.in.c.bits.source, io.in.d.bits.source)
node _T_3480 = and(_T_3478, _T_3479)
node _T_3481 = and(_T_3480, d_release_ack_1)
node _T_3482 = eq(c_probe_ack, UInt<1>(0h0))
node _T_3483 = and(_T_3481, _T_3482)
when _T_3483 :
node _T_3484 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_3485 = or(_T_3484, io.in.c.ready)
node _T_3486 = asUInt(reset)
node _T_3487 = eq(_T_3486, UInt<1>(0h0))
when _T_3487 :
node _T_3488 = eq(_T_3485, UInt<1>(0h0))
when _T_3488 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205
assert(clock, _T_3485, UInt<1>(0h1), "") : assert_205
node _T_3489 = orr(c_set_wo_ready)
when _T_3489 :
node _T_3490 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_3491 = asUInt(reset)
node _T_3492 = eq(_T_3491, UInt<1>(0h0))
when _T_3492 :
node _T_3493 = eq(_T_3490, UInt<1>(0h0))
when _T_3493 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206
assert(clock, _T_3490, UInt<1>(0h1), "") : assert_206
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_133
node _T_3494 = orr(inflight_1)
node _T_3495 = eq(_T_3494, UInt<1>(0h0))
node _T_3496 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_3497 = or(_T_3495, _T_3496)
node _T_3498 = lt(watchdog_1, plusarg_reader_1.out)
node _T_3499 = or(_T_3497, _T_3498)
node _T_3500 = asUInt(reset)
node _T_3501 = eq(_T_3500, UInt<1>(0h0))
when _T_3501 :
node _T_3502 = eq(_T_3499, UInt<1>(0h0))
when _T_3502 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207
assert(clock, _T_3499, UInt<1>(0h1), "") : assert_207
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
node _T_3503 = and(io.in.c.ready, io.in.c.valid)
node _T_3504 = and(io.in.d.ready, io.in.d.valid)
node _T_3505 = or(_T_3503, _T_3504)
when _T_3505 :
connect watchdog_1, UInt<1>(0h0)
regreset inflight_2 : UInt<12>, clock, reset, UInt<12>(0h0)
node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_9 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 5, 0)
node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10)
node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 4)
node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0))
regreset d_first_counter_3 : UInt<2>, clock, reset, UInt<2>(0h0)
node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1))
node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1)
node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0))
node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1))
node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0))
node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7)
node d_first_done_3 = and(d_first_last_3, _d_first_T_3)
node _d_first_count_T_3 = not(d_first_counter1_3)
node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3)
when _d_first_T_3 :
node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3)
connect d_first_counter_3, _d_first_counter_T_3
wire d_set : UInt<12>
connect d_set, UInt<12>(0h0)
node _T_3506 = and(io.in.d.ready, io.in.d.valid)
node _T_3507 = and(_T_3506, d_first_3)
node _T_3508 = bits(io.in.d.bits.opcode, 2, 2)
node _T_3509 = bits(io.in.d.bits.opcode, 1, 1)
node _T_3510 = eq(_T_3509, UInt<1>(0h0))
node _T_3511 = and(_T_3508, _T_3510)
node _T_3512 = and(_T_3507, _T_3511)
when _T_3512 :
node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink)
connect d_set, _d_set_T
node _T_3513 = dshr(inflight_2, io.in.d.bits.sink)
node _T_3514 = bits(_T_3513, 0, 0)
node _T_3515 = eq(_T_3514, UInt<1>(0h0))
node _T_3516 = asUInt(reset)
node _T_3517 = eq(_T_3516, UInt<1>(0h0))
when _T_3517 :
node _T_3518 = eq(_T_3515, UInt<1>(0h0))
when _T_3518 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208
assert(clock, _T_3515, UInt<1>(0h1), "") : assert_208
wire e_clr : UInt<12>
connect e_clr, UInt<12>(0h0)
node _T_3519 = and(io.in.e.ready, io.in.e.valid)
node _T_3520 = and(_T_3519, UInt<1>(0h1))
node _T_3521 = and(_T_3520, UInt<1>(0h1))
when _T_3521 :
node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink)
connect e_clr, _e_clr_T
node _T_3522 = or(d_set, inflight_2)
node _T_3523 = dshr(_T_3522, io.in.e.bits.sink)
node _T_3524 = bits(_T_3523, 0, 0)
node _T_3525 = asUInt(reset)
node _T_3526 = eq(_T_3525, UInt<1>(0h0))
when _T_3526 :
node _T_3527 = eq(_T_3524, UInt<1>(0h0))
when _T_3527 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209
assert(clock, _T_3524, UInt<1>(0h1), "") : assert_209
node _inflight_T_6 = or(inflight_2, d_set)
node _inflight_T_7 = not(e_clr)
node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7)
connect inflight_2, _inflight_T_8
extmodule plusarg_reader_134 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_135 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLMonitor_50( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_b_ready, // @[Monitor.scala:20:14]
input io_in_b_valid, // @[Monitor.scala:20:14]
input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14]
input [6:0] io_in_b_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14]
input io_in_c_ready, // @[Monitor.scala:20:14]
input io_in_c_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_c_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14]
input io_in_c_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_e_valid, // @[Monitor.scala:20:14]
input [3:0] io_in_e_bits_sink // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire [12:0] _GEN_0 = {10'h0, io_in_c_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [1:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _d_first_T_3 = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala:51:35]
reg [1:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg [3:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] b_first_counter; // @[Edges.scala:229:27]
reg [1:0] param_2; // @[Monitor.scala:411:22]
reg [6:0] source_2; // @[Monitor.scala:413:22]
reg [31:0] address_1; // @[Monitor.scala:414:22]
wire _c_first_T_1 = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala:51:35]
reg [1:0] c_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_3; // @[Monitor.scala:515:22]
reg [2:0] param_3; // @[Monitor.scala:516:22]
reg [2:0] size_3; // @[Monitor.scala:517:22]
reg [6:0] source_3; // @[Monitor.scala:518:22]
reg [31:0] address_2; // @[Monitor.scala:519:22]
reg [78:0] inflight; // @[Monitor.scala:614:27]
reg [315:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [315:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [1:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25]
reg [1:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25]
wire [127:0] _GEN_1 = {121'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_2 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_3 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [127:0] _GEN_4 = {121'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [78:0] inflight_1; // @[Monitor.scala:726:35]
reg [315:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [1:0] c_first_counter_1; // @[Edges.scala:229:27]
wire c_first_1 = c_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25]
reg [1:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _GEN_5 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala:68:{36,40,51}]
wire [127:0] _GEN_6 = {121'h0, io_in_c_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_7 = _c_first_T_1 & c_first_1 & _GEN_5; // @[Decoupled.scala:51:35]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
reg [11:0] inflight_2; // @[Monitor.scala:828:27]
reg [1:0] d_first_counter_3; // @[Edges.scala:229:27]
wire d_first_3 = d_first_counter_3 == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _GEN_8 = _d_first_T_3 & d_first_3 & io_in_d_bits_opcode[2] & ~(io_in_d_bits_opcode[1]); // @[Decoupled.scala:51:35]
wire [15:0] _d_set_T = 16'h1 << io_in_d_bits_sink; // @[OneHot.scala:58:35]
wire [11:0] d_set = _GEN_8 ? _d_set_T[11:0] : 12'h0; // @[OneHot.scala:58:35] |
Generate the Verilog code corresponding to this FIRRTL code module RegisterFileSynthesizable_4 :
input clock : Clock
input reset : Reset
output io : { read_ports : { flip addr : UInt<6>, data : UInt<64>}[4], flip write_ports : { valid : UInt<1>, bits : { addr : UInt<6>, data : UInt<64>}}[2]}
cmem regfile : UInt<64> [52]
wire read_data : UInt<64>[4]
reg read_addrs_0 : UInt, clock
connect read_addrs_0, io.read_ports[0].addr
reg read_addrs_1 : UInt, clock
connect read_addrs_1, io.read_ports[1].addr
reg read_addrs_2 : UInt, clock
connect read_addrs_2, io.read_ports[2].addr
reg read_addrs_3 : UInt, clock
connect read_addrs_3, io.read_ports[3].addr
node _read_data_0_T = or(read_addrs_0, UInt<6>(0h0))
node _read_data_0_T_1 = bits(_read_data_0_T, 5, 0)
infer mport read_data_0_MPORT = regfile[_read_data_0_T_1], clock
connect read_data[0], read_data_0_MPORT
node _read_data_1_T = or(read_addrs_1, UInt<6>(0h0))
node _read_data_1_T_1 = bits(_read_data_1_T, 5, 0)
infer mport read_data_1_MPORT = regfile[_read_data_1_T_1], clock
connect read_data[1], read_data_1_MPORT
node _read_data_2_T = or(read_addrs_2, UInt<6>(0h0))
node _read_data_2_T_1 = bits(_read_data_2_T, 5, 0)
infer mport read_data_2_MPORT = regfile[_read_data_2_T_1], clock
connect read_data[2], read_data_2_MPORT
node _read_data_3_T = or(read_addrs_3, UInt<6>(0h0))
node _read_data_3_T_1 = bits(_read_data_3_T, 5, 0)
infer mport read_data_3_MPORT = regfile[_read_data_3_T_1], clock
connect read_data[3], read_data_3_MPORT
node _bypass_ens_T = eq(io.write_ports[0].bits.addr, read_addrs_0)
node bypass_ens_0 = and(io.write_ports[0].valid, _bypass_ens_T)
node _bypass_ens_T_1 = eq(io.write_ports[1].bits.addr, read_addrs_0)
node bypass_ens_1 = and(io.write_ports[1].valid, _bypass_ens_T_1)
wire _bypass_data_WIRE : UInt<1>[2]
connect _bypass_data_WIRE[0], bypass_ens_0
connect _bypass_data_WIRE[1], bypass_ens_1
wire _bypass_data_WIRE_1 : UInt<64>[2]
connect _bypass_data_WIRE_1[0], io.write_ports[0].bits.data
connect _bypass_data_WIRE_1[1], io.write_ports[1].bits.data
node _bypass_data_T = mux(_bypass_data_WIRE[0], _bypass_data_WIRE_1[0], UInt<1>(0h0))
node _bypass_data_T_1 = mux(_bypass_data_WIRE[1], _bypass_data_WIRE_1[1], UInt<1>(0h0))
node _bypass_data_T_2 = or(_bypass_data_T, _bypass_data_T_1)
wire bypass_data : UInt<64>
connect bypass_data, _bypass_data_T_2
node _io_read_ports_0_data_T = or(bypass_ens_0, bypass_ens_1)
node _io_read_ports_0_data_T_1 = mux(_io_read_ports_0_data_T, bypass_data, read_data[0])
connect io.read_ports[0].data, _io_read_ports_0_data_T_1
node _bypass_ens_T_2 = eq(io.write_ports[0].bits.addr, read_addrs_1)
node bypass_ens_0_1 = and(io.write_ports[0].valid, _bypass_ens_T_2)
node _bypass_ens_T_3 = eq(io.write_ports[1].bits.addr, read_addrs_1)
node bypass_ens_1_1 = and(io.write_ports[1].valid, _bypass_ens_T_3)
wire _bypass_data_WIRE_2 : UInt<1>[2]
connect _bypass_data_WIRE_2[0], bypass_ens_0_1
connect _bypass_data_WIRE_2[1], bypass_ens_1_1
wire _bypass_data_WIRE_3 : UInt<64>[2]
connect _bypass_data_WIRE_3[0], io.write_ports[0].bits.data
connect _bypass_data_WIRE_3[1], io.write_ports[1].bits.data
node _bypass_data_T_3 = mux(_bypass_data_WIRE_2[0], _bypass_data_WIRE_3[0], UInt<1>(0h0))
node _bypass_data_T_4 = mux(_bypass_data_WIRE_2[1], _bypass_data_WIRE_3[1], UInt<1>(0h0))
node _bypass_data_T_5 = or(_bypass_data_T_3, _bypass_data_T_4)
wire bypass_data_1 : UInt<64>
connect bypass_data_1, _bypass_data_T_5
node _io_read_ports_1_data_T = or(bypass_ens_0_1, bypass_ens_1_1)
node _io_read_ports_1_data_T_1 = mux(_io_read_ports_1_data_T, bypass_data_1, read_data[1])
connect io.read_ports[1].data, _io_read_ports_1_data_T_1
node _bypass_ens_T_4 = eq(io.write_ports[0].bits.addr, read_addrs_2)
node bypass_ens_0_2 = and(io.write_ports[0].valid, _bypass_ens_T_4)
node _bypass_ens_T_5 = eq(io.write_ports[1].bits.addr, read_addrs_2)
node bypass_ens_1_2 = and(io.write_ports[1].valid, _bypass_ens_T_5)
wire _bypass_data_WIRE_4 : UInt<1>[2]
connect _bypass_data_WIRE_4[0], bypass_ens_0_2
connect _bypass_data_WIRE_4[1], bypass_ens_1_2
wire _bypass_data_WIRE_5 : UInt<64>[2]
connect _bypass_data_WIRE_5[0], io.write_ports[0].bits.data
connect _bypass_data_WIRE_5[1], io.write_ports[1].bits.data
node _bypass_data_T_6 = mux(_bypass_data_WIRE_4[0], _bypass_data_WIRE_5[0], UInt<1>(0h0))
node _bypass_data_T_7 = mux(_bypass_data_WIRE_4[1], _bypass_data_WIRE_5[1], UInt<1>(0h0))
node _bypass_data_T_8 = or(_bypass_data_T_6, _bypass_data_T_7)
wire bypass_data_2 : UInt<64>
connect bypass_data_2, _bypass_data_T_8
node _io_read_ports_2_data_T = or(bypass_ens_0_2, bypass_ens_1_2)
node _io_read_ports_2_data_T_1 = mux(_io_read_ports_2_data_T, bypass_data_2, read_data[2])
connect io.read_ports[2].data, _io_read_ports_2_data_T_1
node _bypass_ens_T_6 = eq(io.write_ports[0].bits.addr, read_addrs_3)
node bypass_ens_0_3 = and(io.write_ports[0].valid, _bypass_ens_T_6)
node _bypass_ens_T_7 = eq(io.write_ports[1].bits.addr, read_addrs_3)
node bypass_ens_1_3 = and(io.write_ports[1].valid, _bypass_ens_T_7)
wire _bypass_data_WIRE_6 : UInt<1>[2]
connect _bypass_data_WIRE_6[0], bypass_ens_0_3
connect _bypass_data_WIRE_6[1], bypass_ens_1_3
wire _bypass_data_WIRE_7 : UInt<64>[2]
connect _bypass_data_WIRE_7[0], io.write_ports[0].bits.data
connect _bypass_data_WIRE_7[1], io.write_ports[1].bits.data
node _bypass_data_T_9 = mux(_bypass_data_WIRE_6[0], _bypass_data_WIRE_7[0], UInt<1>(0h0))
node _bypass_data_T_10 = mux(_bypass_data_WIRE_6[1], _bypass_data_WIRE_7[1], UInt<1>(0h0))
node _bypass_data_T_11 = or(_bypass_data_T_9, _bypass_data_T_10)
wire bypass_data_3 : UInt<64>
connect bypass_data_3, _bypass_data_T_11
node _io_read_ports_3_data_T = or(bypass_ens_0_3, bypass_ens_1_3)
node _io_read_ports_3_data_T_1 = mux(_io_read_ports_3_data_T, bypass_data_3, read_data[3])
connect io.read_ports[3].data, _io_read_ports_3_data_T_1
when io.write_ports[0].valid :
infer mport MPORT = regfile[io.write_ports[0].bits.addr], clock
connect MPORT, io.write_ports[0].bits.data
when io.write_ports[1].valid :
infer mport MPORT_1 = regfile[io.write_ports[1].bits.addr], clock
connect MPORT_1, io.write_ports[1].bits.data
node _T = eq(io.write_ports[0].valid, UInt<1>(0h0))
node _T_1 = eq(io.write_ports[1].valid, UInt<1>(0h0))
node _T_2 = or(_T, _T_1)
node _T_3 = neq(io.write_ports[0].bits.addr, io.write_ports[1].bits.addr)
node _T_4 = or(_T_2, _T_3)
node _T_5 = eq(io.write_ports[0].bits.addr, UInt<1>(0h0))
node _T_6 = or(_T_4, _T_5)
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed: [regfile] too many writers a register\n at regfile.scala:171 assert(!io.write_ports(i).valid ||\n") : printf
assert(clock, _T_6, UInt<1>(0h1), "") : assert | module RegisterFileSynthesizable_4( // @[regfile.scala:106:7]
input clock, // @[regfile.scala:106:7]
input reset, // @[regfile.scala:106:7]
input [5:0] io_read_ports_0_addr, // @[regfile.scala:82:14]
output [63:0] io_read_ports_0_data, // @[regfile.scala:82:14]
input [5:0] io_read_ports_1_addr, // @[regfile.scala:82:14]
output [63:0] io_read_ports_1_data, // @[regfile.scala:82:14]
input [5:0] io_read_ports_2_addr, // @[regfile.scala:82:14]
output [63:0] io_read_ports_2_data, // @[regfile.scala:82:14]
input [5:0] io_read_ports_3_addr, // @[regfile.scala:82:14]
output [63:0] io_read_ports_3_data, // @[regfile.scala:82:14]
input io_write_ports_0_valid, // @[regfile.scala:82:14]
input [5:0] io_write_ports_0_bits_addr, // @[regfile.scala:82:14]
input [63:0] io_write_ports_0_bits_data, // @[regfile.scala:82:14]
input io_write_ports_1_valid, // @[regfile.scala:82:14]
input [5:0] io_write_ports_1_bits_addr, // @[regfile.scala:82:14]
input [63:0] io_write_ports_1_bits_data // @[regfile.scala:82:14]
);
wire [5:0] io_read_ports_0_addr_0 = io_read_ports_0_addr; // @[regfile.scala:106:7]
wire [5:0] io_read_ports_1_addr_0 = io_read_ports_1_addr; // @[regfile.scala:106:7]
wire [5:0] io_read_ports_2_addr_0 = io_read_ports_2_addr; // @[regfile.scala:106:7]
wire [5:0] io_read_ports_3_addr_0 = io_read_ports_3_addr; // @[regfile.scala:106:7]
wire io_write_ports_0_valid_0 = io_write_ports_0_valid; // @[regfile.scala:106:7]
wire [5:0] io_write_ports_0_bits_addr_0 = io_write_ports_0_bits_addr; // @[regfile.scala:106:7]
wire [63:0] io_write_ports_0_bits_data_0 = io_write_ports_0_bits_data; // @[regfile.scala:106:7]
wire io_write_ports_1_valid_0 = io_write_ports_1_valid; // @[regfile.scala:106:7]
wire [5:0] io_write_ports_1_bits_addr_0 = io_write_ports_1_bits_addr; // @[regfile.scala:106:7]
wire [63:0] io_write_ports_1_bits_data_0 = io_write_ports_1_bits_data; // @[regfile.scala:106:7]
wire [63:0] _io_read_ports_0_data_T_1; // @[regfile.scala:150:35]
wire [63:0] _io_read_ports_1_data_T_1; // @[regfile.scala:150:35]
wire [63:0] _io_read_ports_2_data_T_1; // @[regfile.scala:150:35]
wire [63:0] _io_read_ports_3_data_T_1; // @[regfile.scala:150:35]
wire [63:0] _bypass_data_WIRE_1_0 = io_write_ports_0_bits_data_0; // @[regfile.scala:106:7, :148:65]
wire [63:0] _bypass_data_WIRE_3_0 = io_write_ports_0_bits_data_0; // @[regfile.scala:106:7, :148:65]
wire [63:0] _bypass_data_WIRE_5_0 = io_write_ports_0_bits_data_0; // @[regfile.scala:106:7, :148:65]
wire [63:0] _bypass_data_WIRE_7_0 = io_write_ports_0_bits_data_0; // @[regfile.scala:106:7, :148:65]
wire [63:0] _bypass_data_WIRE_1_1 = io_write_ports_1_bits_data_0; // @[regfile.scala:106:7, :148:65]
wire [63:0] _bypass_data_WIRE_3_1 = io_write_ports_1_bits_data_0; // @[regfile.scala:106:7, :148:65]
wire [63:0] _bypass_data_WIRE_5_1 = io_write_ports_1_bits_data_0; // @[regfile.scala:106:7, :148:65]
wire [63:0] _bypass_data_WIRE_7_1 = io_write_ports_1_bits_data_0; // @[regfile.scala:106:7, :148:65]
wire [63:0] io_read_ports_0_data_0; // @[regfile.scala:106:7]
wire [63:0] io_read_ports_1_data_0; // @[regfile.scala:106:7]
wire [63:0] io_read_ports_2_data_0; // @[regfile.scala:106:7]
wire [63:0] io_read_ports_3_data_0; // @[regfile.scala:106:7]
wire [63:0] read_data_0; // @[regfile.scala:122:23]
wire [63:0] read_data_1; // @[regfile.scala:122:23]
wire [63:0] read_data_2; // @[regfile.scala:122:23]
wire [63:0] read_data_3; // @[regfile.scala:122:23]
reg [5:0] read_addrs_0; // @[regfile.scala:125:50]
wire [5:0] _read_data_0_T = read_addrs_0; // @[regfile.scala:125:50, :128:28]
reg [5:0] read_addrs_1; // @[regfile.scala:125:50]
wire [5:0] _read_data_1_T = read_addrs_1; // @[regfile.scala:125:50, :128:28]
reg [5:0] read_addrs_2; // @[regfile.scala:125:50]
wire [5:0] _read_data_2_T = read_addrs_2; // @[regfile.scala:125:50, :128:28]
reg [5:0] read_addrs_3; // @[regfile.scala:125:50]
wire [5:0] _read_data_3_T = read_addrs_3; // @[regfile.scala:125:50, :128:28]
wire [5:0] _read_data_0_T_1 = _read_data_0_T; // @[regfile.scala:128:28]
wire [5:0] _read_data_1_T_1 = _read_data_1_T; // @[regfile.scala:128:28]
wire [5:0] _read_data_2_T_1 = _read_data_2_T; // @[regfile.scala:128:28]
wire [5:0] _read_data_3_T_1 = _read_data_3_T; // @[regfile.scala:128:28]
wire _bypass_ens_T = io_write_ports_0_bits_addr_0 == read_addrs_0; // @[regfile.scala:106:7, :125:50, :146:21]
wire bypass_ens_0 = io_write_ports_0_valid_0 & _bypass_ens_T; // @[regfile.scala:106:7, :145:59, :146:21]
wire _bypass_data_WIRE_0 = bypass_ens_0; // @[regfile.scala:145:59, :148:38]
wire _bypass_ens_T_1 = io_write_ports_1_bits_addr_0 == read_addrs_0; // @[regfile.scala:106:7, :125:50, :146:21]
wire bypass_ens_1 = io_write_ports_1_valid_0 & _bypass_ens_T_1; // @[regfile.scala:106:7, :145:59, :146:21]
wire _bypass_data_WIRE_1 = bypass_ens_1; // @[regfile.scala:145:59, :148:38]
wire [63:0] _bypass_data_T = _bypass_data_WIRE_0 ? _bypass_data_WIRE_1_0 : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _bypass_data_T_1 = _bypass_data_WIRE_1 ? _bypass_data_WIRE_1_1 : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _bypass_data_T_2 = _bypass_data_T | _bypass_data_T_1; // @[Mux.scala:30:73]
wire [63:0] bypass_data = _bypass_data_T_2; // @[Mux.scala:30:73]
wire _io_read_ports_0_data_T = bypass_ens_0 | bypass_ens_1; // @[regfile.scala:145:59, :150:55]
assign _io_read_ports_0_data_T_1 = _io_read_ports_0_data_T ? bypass_data : read_data_0; // @[Mux.scala:30:73]
assign io_read_ports_0_data_0 = _io_read_ports_0_data_T_1; // @[regfile.scala:106:7, :150:35]
wire _bypass_ens_T_2 = io_write_ports_0_bits_addr_0 == read_addrs_1; // @[regfile.scala:106:7, :125:50, :146:21]
wire bypass_ens_0_1 = io_write_ports_0_valid_0 & _bypass_ens_T_2; // @[regfile.scala:106:7, :145:59, :146:21]
wire _bypass_data_WIRE_2_0 = bypass_ens_0_1; // @[regfile.scala:145:59, :148:38]
wire _bypass_ens_T_3 = io_write_ports_1_bits_addr_0 == read_addrs_1; // @[regfile.scala:106:7, :125:50, :146:21]
wire bypass_ens_1_1 = io_write_ports_1_valid_0 & _bypass_ens_T_3; // @[regfile.scala:106:7, :145:59, :146:21]
wire _bypass_data_WIRE_2_1 = bypass_ens_1_1; // @[regfile.scala:145:59, :148:38]
wire [63:0] _bypass_data_T_3 = _bypass_data_WIRE_2_0 ? _bypass_data_WIRE_3_0 : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _bypass_data_T_4 = _bypass_data_WIRE_2_1 ? _bypass_data_WIRE_3_1 : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _bypass_data_T_5 = _bypass_data_T_3 | _bypass_data_T_4; // @[Mux.scala:30:73]
wire [63:0] bypass_data_1 = _bypass_data_T_5; // @[Mux.scala:30:73]
wire _io_read_ports_1_data_T = bypass_ens_0_1 | bypass_ens_1_1; // @[regfile.scala:145:59, :150:55]
assign _io_read_ports_1_data_T_1 = _io_read_ports_1_data_T ? bypass_data_1 : read_data_1; // @[Mux.scala:30:73]
assign io_read_ports_1_data_0 = _io_read_ports_1_data_T_1; // @[regfile.scala:106:7, :150:35]
wire _bypass_ens_T_4 = io_write_ports_0_bits_addr_0 == read_addrs_2; // @[regfile.scala:106:7, :125:50, :146:21]
wire bypass_ens_0_2 = io_write_ports_0_valid_0 & _bypass_ens_T_4; // @[regfile.scala:106:7, :145:59, :146:21]
wire _bypass_data_WIRE_4_0 = bypass_ens_0_2; // @[regfile.scala:145:59, :148:38]
wire _bypass_ens_T_5 = io_write_ports_1_bits_addr_0 == read_addrs_2; // @[regfile.scala:106:7, :125:50, :146:21]
wire bypass_ens_1_2 = io_write_ports_1_valid_0 & _bypass_ens_T_5; // @[regfile.scala:106:7, :145:59, :146:21]
wire _bypass_data_WIRE_4_1 = bypass_ens_1_2; // @[regfile.scala:145:59, :148:38]
wire [63:0] _bypass_data_T_6 = _bypass_data_WIRE_4_0 ? _bypass_data_WIRE_5_0 : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _bypass_data_T_7 = _bypass_data_WIRE_4_1 ? _bypass_data_WIRE_5_1 : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _bypass_data_T_8 = _bypass_data_T_6 | _bypass_data_T_7; // @[Mux.scala:30:73]
wire [63:0] bypass_data_2 = _bypass_data_T_8; // @[Mux.scala:30:73]
wire _io_read_ports_2_data_T = bypass_ens_0_2 | bypass_ens_1_2; // @[regfile.scala:145:59, :150:55]
assign _io_read_ports_2_data_T_1 = _io_read_ports_2_data_T ? bypass_data_2 : read_data_2; // @[Mux.scala:30:73]
assign io_read_ports_2_data_0 = _io_read_ports_2_data_T_1; // @[regfile.scala:106:7, :150:35]
wire _bypass_ens_T_6 = io_write_ports_0_bits_addr_0 == read_addrs_3; // @[regfile.scala:106:7, :125:50, :146:21]
wire bypass_ens_0_3 = io_write_ports_0_valid_0 & _bypass_ens_T_6; // @[regfile.scala:106:7, :145:59, :146:21]
wire _bypass_data_WIRE_6_0 = bypass_ens_0_3; // @[regfile.scala:145:59, :148:38]
wire _bypass_ens_T_7 = io_write_ports_1_bits_addr_0 == read_addrs_3; // @[regfile.scala:106:7, :125:50, :146:21]
wire bypass_ens_1_3 = io_write_ports_1_valid_0 & _bypass_ens_T_7; // @[regfile.scala:106:7, :145:59, :146:21]
wire _bypass_data_WIRE_6_1 = bypass_ens_1_3; // @[regfile.scala:145:59, :148:38]
wire [63:0] _bypass_data_T_9 = _bypass_data_WIRE_6_0 ? _bypass_data_WIRE_7_0 : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _bypass_data_T_10 = _bypass_data_WIRE_6_1 ? _bypass_data_WIRE_7_1 : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _bypass_data_T_11 = _bypass_data_T_9 | _bypass_data_T_10; // @[Mux.scala:30:73]
wire [63:0] bypass_data_3 = _bypass_data_T_11; // @[Mux.scala:30:73]
wire _io_read_ports_3_data_T = bypass_ens_0_3 | bypass_ens_1_3; // @[regfile.scala:145:59, :150:55]
assign _io_read_ports_3_data_T_1 = _io_read_ports_3_data_T ? bypass_data_3 : read_data_3; // @[Mux.scala:30:73]
assign io_read_ports_3_data_0 = _io_read_ports_3_data_T_1; // @[regfile.scala:106:7, :150:35] |
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_24 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}}}, flip router_resp : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[4]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, in_vc : UInt<2>, vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[4]}}}, flip vcalloc_resp : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[4]}}, flip out_credit_available : { `1` : UInt<1>[1], `0` : UInt<1>[4]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[4]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}[1], debug : { va_stall : UInt<2>, sa_stall : UInt<2>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<4>, flip vc_free : UInt<4>}}
inst input_buffer of InputBuffer_24
connect input_buffer.clock, clock
connect input_buffer.reset, reset
connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id
connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id
connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node
connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id
connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node
connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id
connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload
connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail
connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head
connect input_buffer.io.enq[0].valid, io.in.flit[0].valid
connect input_buffer.io.deq[0].ready, UInt<1>(0h0)
connect input_buffer.io.deq[1].ready, UInt<1>(0h0)
connect input_buffer.io.deq[2].ready, UInt<1>(0h0)
connect input_buffer.io.deq[3].ready, UInt<1>(0h0)
inst route_arbiter of Arbiter4_RouteComputerReq_11
connect route_arbiter.clock, clock
connect route_arbiter.reset, reset
connect io.router_req.bits, route_arbiter.io.out.bits
connect io.router_req.valid, route_arbiter.io.out.valid
connect route_arbiter.io.out.ready, io.router_req.ready
reg states : { g : UInt<3>, vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[4]}, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, fifo_deps : UInt<4>}[4], clock
node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T :
node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4))
node _T_2 = asUInt(reset)
node _T_3 = eq(_T_2, UInt<1>(0h0))
when _T_3 :
node _T_4 = eq(_T_1, UInt<1>(0h0))
when _T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf
assert(clock, _T_1, UInt<1>(0h1), "") : assert
node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0))
node _T_6 = asUInt(reset)
node _T_7 = eq(_T_6, UInt<1>(0h0))
when _T_7 :
node _T_8 = eq(_T_5, UInt<1>(0h0))
when _T_8 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1
assert(clock, _T_5, UInt<1>(0h1), "") : assert_1
node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1))
connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0)
node _T_9 = eq(UInt<1>(0h0), io.in.flit[0].bits.flow.egress_node_id)
when _T_9 :
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h1)
connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow
node _route_arbiter_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h1))
connect route_arbiter.io.in[0].valid, _route_arbiter_io_in_0_valid_T
connect route_arbiter.io.in[0].bits.flow.egress_node_id, states[0].flow.egress_node_id
connect route_arbiter.io.in[0].bits.flow.egress_node, states[0].flow.egress_node
connect route_arbiter.io.in[0].bits.flow.ingress_node_id, states[0].flow.ingress_node_id
connect route_arbiter.io.in[0].bits.flow.ingress_node, states[0].flow.ingress_node
connect route_arbiter.io.in[0].bits.flow.vnet_id, states[0].flow.vnet_id
connect route_arbiter.io.in[0].bits.src_virt_id, UInt<1>(0h0)
node _T_10 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid)
when _T_10 :
connect states[0].g, UInt<3>(0h2)
node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1))
connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T
connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id
connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node
connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id
connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node
connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id
connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1)
node _T_11 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid)
when _T_11 :
connect states[1].g, UInt<3>(0h2)
connect route_arbiter.io.in[2].valid, UInt<1>(0h0)
invalidate route_arbiter.io.in[2].bits.flow.egress_node_id
invalidate route_arbiter.io.in[2].bits.flow.egress_node
invalidate route_arbiter.io.in[2].bits.flow.ingress_node_id
invalidate route_arbiter.io.in[2].bits.flow.ingress_node
invalidate route_arbiter.io.in[2].bits.flow.vnet_id
invalidate route_arbiter.io.in[2].bits.src_virt_id
node _route_arbiter_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h1))
connect route_arbiter.io.in[3].valid, _route_arbiter_io_in_3_valid_T
connect route_arbiter.io.in[3].bits.flow.egress_node_id, states[3].flow.egress_node_id
connect route_arbiter.io.in[3].bits.flow.egress_node, states[3].flow.egress_node
connect route_arbiter.io.in[3].bits.flow.ingress_node_id, states[3].flow.ingress_node_id
connect route_arbiter.io.in[3].bits.flow.ingress_node, states[3].flow.ingress_node
connect route_arbiter.io.in[3].bits.flow.vnet_id, states[3].flow.vnet_id
connect route_arbiter.io.in[3].bits.src_virt_id, UInt<2>(0h3)
node _T_12 = and(route_arbiter.io.in[3].ready, route_arbiter.io.in[3].valid)
when _T_12 :
connect states[3].g, UInt<3>(0h2)
node _T_13 = and(io.router_req.ready, io.router_req.valid)
when _T_13 :
node _T_14 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1))
node _T_15 = asUInt(reset)
node _T_16 = eq(_T_15, UInt<1>(0h0))
when _T_16 :
node _T_17 = eq(_T_14, UInt<1>(0h0))
when _T_17 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2
assert(clock, _T_14, UInt<1>(0h1), "") : assert_2
connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2)
node _T_18 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id)
when _T_18 :
connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1`
node _T_19 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id)
when _T_19 :
connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1`
node _T_20 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id)
when _T_20 :
connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1`
node _T_21 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id)
when _T_21 :
connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1`
regreset mask : UInt<4>, clock, reset, UInt<4>(0h0)
wire vcalloc_reqs : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, in_vc : UInt<2>, vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[4]}}[4]
wire vcalloc_vals : UInt<1>[4]
node vcalloc_filter_lo = cat(vcalloc_vals[1], vcalloc_vals[0])
node vcalloc_filter_hi = cat(vcalloc_vals[3], vcalloc_vals[2])
node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo)
node vcalloc_filter_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0])
node vcalloc_filter_hi_1 = cat(vcalloc_vals[3], vcalloc_vals[2])
node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1)
node _vcalloc_filter_T_2 = not(mask)
node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2)
node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3)
node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0)
node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1)
node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2)
node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3)
node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4)
node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5)
node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6)
node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7)
node _vcalloc_filter_T_13 = mux(_vcalloc_filter_T_12, UInt<8>(0h80), UInt<8>(0h0))
node _vcalloc_filter_T_14 = mux(_vcalloc_filter_T_11, UInt<8>(0h40), _vcalloc_filter_T_13)
node _vcalloc_filter_T_15 = mux(_vcalloc_filter_T_10, UInt<8>(0h20), _vcalloc_filter_T_14)
node _vcalloc_filter_T_16 = mux(_vcalloc_filter_T_9, UInt<8>(0h10), _vcalloc_filter_T_15)
node _vcalloc_filter_T_17 = mux(_vcalloc_filter_T_8, UInt<8>(0h8), _vcalloc_filter_T_16)
node _vcalloc_filter_T_18 = mux(_vcalloc_filter_T_7, UInt<8>(0h4), _vcalloc_filter_T_17)
node _vcalloc_filter_T_19 = mux(_vcalloc_filter_T_6, UInt<8>(0h2), _vcalloc_filter_T_18)
node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<8>(0h1), _vcalloc_filter_T_19)
node _vcalloc_sel_T = bits(vcalloc_filter, 3, 0)
node _vcalloc_sel_T_1 = shr(vcalloc_filter, 4)
node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1)
node _T_22 = and(io.router_req.ready, io.router_req.valid)
when _T_22 :
node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id)
node _mask_T_1 = sub(_mask_T, UInt<1>(0h1))
node _mask_T_2 = tail(_mask_T_1, 1)
connect mask, _mask_T_2
else :
node _T_23 = or(vcalloc_vals[0], vcalloc_vals[1])
node _T_24 = or(_T_23, vcalloc_vals[2])
node _T_25 = or(_T_24, vcalloc_vals[3])
when _T_25 :
node _mask_T_3 = not(UInt<1>(0h0))
node _mask_T_4 = not(UInt<2>(0h0))
node _mask_T_5 = not(UInt<3>(0h0))
node _mask_T_6 = not(UInt<4>(0h0))
node _mask_T_7 = bits(vcalloc_sel, 0, 0)
node _mask_T_8 = bits(vcalloc_sel, 1, 1)
node _mask_T_9 = bits(vcalloc_sel, 2, 2)
node _mask_T_10 = bits(vcalloc_sel, 3, 3)
node _mask_T_11 = mux(_mask_T_7, _mask_T_3, UInt<1>(0h0))
node _mask_T_12 = mux(_mask_T_8, _mask_T_4, UInt<1>(0h0))
node _mask_T_13 = mux(_mask_T_9, _mask_T_5, UInt<1>(0h0))
node _mask_T_14 = mux(_mask_T_10, _mask_T_6, UInt<1>(0h0))
node _mask_T_15 = or(_mask_T_11, _mask_T_12)
node _mask_T_16 = or(_mask_T_15, _mask_T_13)
node _mask_T_17 = or(_mask_T_16, _mask_T_14)
wire _mask_WIRE : UInt<4>
connect _mask_WIRE, _mask_T_17
connect mask, _mask_WIRE
node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1])
node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2])
node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3])
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_2
node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0)
node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1)
node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2)
node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3)
wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, in_vc : UInt<2>, vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[4]}}
wire _io_vcalloc_req_bits_WIRE_1 : { `1` : UInt<1>[1], `0` : UInt<1>[4]}
wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[4]
node _io_vcalloc_req_bits_T_4 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_5 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_6 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_7 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_8 = or(_io_vcalloc_req_bits_T_4, _io_vcalloc_req_bits_T_5)
node _io_vcalloc_req_bits_T_9 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_6)
node _io_vcalloc_req_bits_T_10 = or(_io_vcalloc_req_bits_T_9, _io_vcalloc_req_bits_T_7)
wire _io_vcalloc_req_bits_WIRE_3 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_10
connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3
node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_15 = or(_io_vcalloc_req_bits_T_11, _io_vcalloc_req_bits_T_12)
node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_15, _io_vcalloc_req_bits_T_13)
node _io_vcalloc_req_bits_T_17 = or(_io_vcalloc_req_bits_T_16, _io_vcalloc_req_bits_T_14)
wire _io_vcalloc_req_bits_WIRE_4 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_17
connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4
node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_19 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_20 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_21 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_18, _io_vcalloc_req_bits_T_19)
node _io_vcalloc_req_bits_T_23 = or(_io_vcalloc_req_bits_T_22, _io_vcalloc_req_bits_T_20)
node _io_vcalloc_req_bits_T_24 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_21)
wire _io_vcalloc_req_bits_WIRE_5 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_24
connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5
node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_26 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_27 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_29 = or(_io_vcalloc_req_bits_T_25, _io_vcalloc_req_bits_T_26)
node _io_vcalloc_req_bits_T_30 = or(_io_vcalloc_req_bits_T_29, _io_vcalloc_req_bits_T_27)
node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_30, _io_vcalloc_req_bits_T_28)
wire _io_vcalloc_req_bits_WIRE_6 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_31
connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6
connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2
wire _io_vcalloc_req_bits_WIRE_7 : UInt<1>[1]
node _io_vcalloc_req_bits_T_32 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_34 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_32, _io_vcalloc_req_bits_T_33)
node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_34)
node _io_vcalloc_req_bits_T_38 = or(_io_vcalloc_req_bits_T_37, _io_vcalloc_req_bits_T_35)
wire _io_vcalloc_req_bits_WIRE_8 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_38
connect _io_vcalloc_req_bits_WIRE_7[0], _io_vcalloc_req_bits_WIRE_8
connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_7
connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1
node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_41 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_42 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_43 = or(_io_vcalloc_req_bits_T_39, _io_vcalloc_req_bits_T_40)
node _io_vcalloc_req_bits_T_44 = or(_io_vcalloc_req_bits_T_43, _io_vcalloc_req_bits_T_41)
node _io_vcalloc_req_bits_T_45 = or(_io_vcalloc_req_bits_T_44, _io_vcalloc_req_bits_T_42)
wire _io_vcalloc_req_bits_WIRE_9 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_45
connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_9
wire _io_vcalloc_req_bits_WIRE_10 : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}
node _io_vcalloc_req_bits_T_46 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_47 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_48 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_49 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_50 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_47)
node _io_vcalloc_req_bits_T_51 = or(_io_vcalloc_req_bits_T_50, _io_vcalloc_req_bits_T_48)
node _io_vcalloc_req_bits_T_52 = or(_io_vcalloc_req_bits_T_51, _io_vcalloc_req_bits_T_49)
wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_11, _io_vcalloc_req_bits_T_52
connect _io_vcalloc_req_bits_WIRE_10.egress_node_id, _io_vcalloc_req_bits_WIRE_11
node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_56 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_57 = or(_io_vcalloc_req_bits_T_53, _io_vcalloc_req_bits_T_54)
node _io_vcalloc_req_bits_T_58 = or(_io_vcalloc_req_bits_T_57, _io_vcalloc_req_bits_T_55)
node _io_vcalloc_req_bits_T_59 = or(_io_vcalloc_req_bits_T_58, _io_vcalloc_req_bits_T_56)
wire _io_vcalloc_req_bits_WIRE_12 : UInt<4>
connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_59
connect _io_vcalloc_req_bits_WIRE_10.egress_node, _io_vcalloc_req_bits_WIRE_12
node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_61 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_62 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_63 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_60, _io_vcalloc_req_bits_T_61)
node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_62)
node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_63)
wire _io_vcalloc_req_bits_WIRE_13 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_66
connect _io_vcalloc_req_bits_WIRE_10.ingress_node_id, _io_vcalloc_req_bits_WIRE_13
node _io_vcalloc_req_bits_T_67 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_71 = or(_io_vcalloc_req_bits_T_67, _io_vcalloc_req_bits_T_68)
node _io_vcalloc_req_bits_T_72 = or(_io_vcalloc_req_bits_T_71, _io_vcalloc_req_bits_T_69)
node _io_vcalloc_req_bits_T_73 = or(_io_vcalloc_req_bits_T_72, _io_vcalloc_req_bits_T_70)
wire _io_vcalloc_req_bits_WIRE_14 : UInt<4>
connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_73
connect _io_vcalloc_req_bits_WIRE_10.ingress_node, _io_vcalloc_req_bits_WIRE_14
node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_76 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_77 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_78 = or(_io_vcalloc_req_bits_T_74, _io_vcalloc_req_bits_T_75)
node _io_vcalloc_req_bits_T_79 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_76)
node _io_vcalloc_req_bits_T_80 = or(_io_vcalloc_req_bits_T_79, _io_vcalloc_req_bits_T_77)
wire _io_vcalloc_req_bits_WIRE_15 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_80
connect _io_vcalloc_req_bits_WIRE_10.vnet_id, _io_vcalloc_req_bits_WIRE_15
connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_10
connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE
node _vcalloc_vals_0_T = eq(states[0].g, UInt<3>(0h2))
node _vcalloc_vals_0_T_1 = eq(states[0].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_0_T_2 = and(_vcalloc_vals_0_T, _vcalloc_vals_0_T_1)
connect vcalloc_vals[0], _vcalloc_vals_0_T_2
connect vcalloc_reqs[0].in_vc, UInt<1>(0h0)
connect vcalloc_reqs[0].vc_sel.`0`, states[0].vc_sel.`0`
connect vcalloc_reqs[0].vc_sel.`1`, states[0].vc_sel.`1`
connect vcalloc_reqs[0].flow, states[0].flow
node _T_26 = bits(vcalloc_sel, 0, 0)
node _T_27 = and(vcalloc_vals[0], _T_26)
node _T_28 = and(_T_27, io.vcalloc_req.ready)
when _T_28 :
connect states[0].g, UInt<3>(0h3)
node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2))
node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1)
connect vcalloc_vals[1], _vcalloc_vals_1_T_2
connect vcalloc_reqs[1].in_vc, UInt<1>(0h1)
connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0`
connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1`
connect vcalloc_reqs[1].flow, states[1].flow
node _T_29 = bits(vcalloc_sel, 1, 1)
node _T_30 = and(vcalloc_vals[1], _T_29)
node _T_31 = and(_T_30, io.vcalloc_req.ready)
when _T_31 :
connect states[1].g, UInt<3>(0h3)
connect vcalloc_vals[2], UInt<1>(0h0)
invalidate vcalloc_reqs[2].vc_sel.`0`[0]
invalidate vcalloc_reqs[2].vc_sel.`0`[1]
invalidate vcalloc_reqs[2].vc_sel.`0`[2]
invalidate vcalloc_reqs[2].vc_sel.`0`[3]
invalidate vcalloc_reqs[2].vc_sel.`1`[0]
invalidate vcalloc_reqs[2].in_vc
invalidate vcalloc_reqs[2].flow.egress_node_id
invalidate vcalloc_reqs[2].flow.egress_node
invalidate vcalloc_reqs[2].flow.ingress_node_id
invalidate vcalloc_reqs[2].flow.ingress_node
invalidate vcalloc_reqs[2].flow.vnet_id
node _vcalloc_vals_3_T = eq(states[3].g, UInt<3>(0h2))
node _vcalloc_vals_3_T_1 = eq(states[3].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_3_T_2 = and(_vcalloc_vals_3_T, _vcalloc_vals_3_T_1)
connect vcalloc_vals[3], _vcalloc_vals_3_T_2
connect vcalloc_reqs[3].in_vc, UInt<2>(0h3)
connect vcalloc_reqs[3].vc_sel.`0`, states[3].vc_sel.`0`
connect vcalloc_reqs[3].vc_sel.`1`, states[3].vc_sel.`1`
connect vcalloc_reqs[3].flow, states[3].flow
node _T_32 = bits(vcalloc_sel, 3, 3)
node _T_33 = and(vcalloc_vals[3], _T_32)
node _T_34 = and(_T_33, io.vcalloc_req.ready)
when _T_34 :
connect states[3].g, UInt<3>(0h3)
node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1])
node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0)
node _io_debug_va_stall_T_2 = add(vcalloc_vals[2], vcalloc_vals[3])
node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0)
node _io_debug_va_stall_T_4 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_3)
node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 2, 0)
node _io_debug_va_stall_T_6 = sub(_io_debug_va_stall_T_5, io.vcalloc_req.ready)
node _io_debug_va_stall_T_7 = tail(_io_debug_va_stall_T_6, 1)
connect io.debug.va_stall, _io_debug_va_stall_T_7
node _T_35 = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
when _T_35 :
node _T_36 = bits(vcalloc_sel, 0, 0)
when _T_36 :
connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[0].g, UInt<3>(0h3)
node _T_37 = eq(states[0].g, UInt<3>(0h2))
node _T_38 = asUInt(reset)
node _T_39 = eq(_T_38, UInt<1>(0h0))
when _T_39 :
node _T_40 = eq(_T_37, UInt<1>(0h0))
when _T_40 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3
assert(clock, _T_37, UInt<1>(0h1), "") : assert_3
node _T_41 = bits(vcalloc_sel, 1, 1)
when _T_41 :
connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[1].g, UInt<3>(0h3)
node _T_42 = eq(states[1].g, UInt<3>(0h2))
node _T_43 = asUInt(reset)
node _T_44 = eq(_T_43, UInt<1>(0h0))
when _T_44 :
node _T_45 = eq(_T_42, UInt<1>(0h0))
when _T_45 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4
assert(clock, _T_42, UInt<1>(0h1), "") : assert_4
node _T_46 = bits(vcalloc_sel, 2, 2)
when _T_46 :
connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[2].g, UInt<3>(0h3)
node _T_47 = eq(states[2].g, UInt<3>(0h2))
node _T_48 = asUInt(reset)
node _T_49 = eq(_T_48, UInt<1>(0h0))
when _T_49 :
node _T_50 = eq(_T_47, UInt<1>(0h0))
when _T_50 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5
assert(clock, _T_47, UInt<1>(0h1), "") : assert_5
node _T_51 = bits(vcalloc_sel, 3, 3)
when _T_51 :
connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[3].g, UInt<3>(0h3)
node _T_52 = eq(states[3].g, UInt<3>(0h2))
node _T_53 = asUInt(reset)
node _T_54 = eq(_T_53, UInt<1>(0h0))
when _T_54 :
node _T_55 = eq(_T_52, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6
assert(clock, _T_52, UInt<1>(0h1), "") : assert_6
inst salloc_arb of SwitchArbiter_79
connect salloc_arb.clock, clock
connect salloc_arb.reset, reset
node credit_available_lo = cat(states[0].vc_sel.`0`[1], states[0].vc_sel.`0`[0])
node credit_available_hi = cat(states[0].vc_sel.`0`[3], states[0].vc_sel.`0`[2])
node _credit_available_T = cat(credit_available_hi, credit_available_lo)
node _credit_available_T_1 = cat(states[0].vc_sel.`1`[0], _credit_available_T)
node credit_available_lo_1 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_hi_1 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node _credit_available_T_2 = cat(credit_available_hi_1, credit_available_lo_1)
node _credit_available_T_3 = cat(io.out_credit_available.`1`[0], _credit_available_T_2)
node _credit_available_T_4 = and(_credit_available_T_1, _credit_available_T_3)
node credit_available = neq(_credit_available_T_4, UInt<1>(0h0))
node _salloc_arb_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h3))
node _salloc_arb_io_in_0_valid_T_1 = and(_salloc_arb_io_in_0_valid_T, credit_available)
node _salloc_arb_io_in_0_valid_T_2 = and(_salloc_arb_io_in_0_valid_T_1, input_buffer.io.deq[0].valid)
connect salloc_arb.io.in[0].valid, _salloc_arb_io_in_0_valid_T_2
connect salloc_arb.io.in[0].bits.vc_sel.`0`[0], states[0].vc_sel.`0`[0]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[1], states[0].vc_sel.`0`[1]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[2], states[0].vc_sel.`0`[2]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[3], states[0].vc_sel.`0`[3]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[0], states[0].vc_sel.`1`[0]
connect salloc_arb.io.in[0].bits.tail, input_buffer.io.deq[0].bits.tail
node _T_56 = and(salloc_arb.io.in[0].ready, salloc_arb.io.in[0].valid)
node _T_57 = and(_T_56, input_buffer.io.deq[0].bits.tail)
when _T_57 :
connect states[0].g, UInt<3>(0h0)
connect input_buffer.io.deq[0].ready, salloc_arb.io.in[0].ready
node credit_available_lo_2 = cat(states[1].vc_sel.`0`[1], states[1].vc_sel.`0`[0])
node credit_available_hi_2 = cat(states[1].vc_sel.`0`[3], states[1].vc_sel.`0`[2])
node _credit_available_T_5 = cat(credit_available_hi_2, credit_available_lo_2)
node _credit_available_T_6 = cat(states[1].vc_sel.`1`[0], _credit_available_T_5)
node credit_available_lo_3 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_hi_3 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node _credit_available_T_7 = cat(credit_available_hi_3, credit_available_lo_3)
node _credit_available_T_8 = cat(io.out_credit_available.`1`[0], _credit_available_T_7)
node _credit_available_T_9 = and(_credit_available_T_6, _credit_available_T_8)
node credit_available_1 = neq(_credit_available_T_9, UInt<1>(0h0))
node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3))
node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available_1)
node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid)
connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2
connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[2], states[1].vc_sel.`0`[2]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[3], states[1].vc_sel.`0`[3]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0]
connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail
node _T_58 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid)
node _T_59 = and(_T_58, input_buffer.io.deq[1].bits.tail)
when _T_59 :
connect states[1].g, UInt<3>(0h0)
connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready
connect salloc_arb.io.in[2].valid, UInt<1>(0h0)
invalidate salloc_arb.io.in[2].bits.tail
invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[0]
invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[1]
invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[2]
invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[3]
invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[0]
node credit_available_lo_4 = cat(states[3].vc_sel.`0`[1], states[3].vc_sel.`0`[0])
node credit_available_hi_4 = cat(states[3].vc_sel.`0`[3], states[3].vc_sel.`0`[2])
node _credit_available_T_10 = cat(credit_available_hi_4, credit_available_lo_4)
node _credit_available_T_11 = cat(states[3].vc_sel.`1`[0], _credit_available_T_10)
node credit_available_lo_5 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_hi_5 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node _credit_available_T_12 = cat(credit_available_hi_5, credit_available_lo_5)
node _credit_available_T_13 = cat(io.out_credit_available.`1`[0], _credit_available_T_12)
node _credit_available_T_14 = and(_credit_available_T_11, _credit_available_T_13)
node credit_available_2 = neq(_credit_available_T_14, UInt<1>(0h0))
node _salloc_arb_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h3))
node _salloc_arb_io_in_3_valid_T_1 = and(_salloc_arb_io_in_3_valid_T, credit_available_2)
node _salloc_arb_io_in_3_valid_T_2 = and(_salloc_arb_io_in_3_valid_T_1, input_buffer.io.deq[3].valid)
connect salloc_arb.io.in[3].valid, _salloc_arb_io_in_3_valid_T_2
connect salloc_arb.io.in[3].bits.vc_sel.`0`[0], states[3].vc_sel.`0`[0]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[1], states[3].vc_sel.`0`[1]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[2], states[3].vc_sel.`0`[2]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[3], states[3].vc_sel.`0`[3]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[0], states[3].vc_sel.`1`[0]
connect salloc_arb.io.in[3].bits.tail, input_buffer.io.deq[3].bits.tail
node _T_60 = and(salloc_arb.io.in[3].ready, salloc_arb.io.in[3].valid)
node _T_61 = and(_T_60, input_buffer.io.deq[3].bits.tail)
when _T_61 :
connect states[3].g, UInt<3>(0h0)
connect input_buffer.io.deq[3].ready, salloc_arb.io.in[3].ready
node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T)
node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2)
node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4)
node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6)
node _io_debug_sa_stall_T_8 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3)
node _io_debug_sa_stall_T_9 = bits(_io_debug_sa_stall_T_8, 1, 0)
node _io_debug_sa_stall_T_10 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_7)
node _io_debug_sa_stall_T_11 = bits(_io_debug_sa_stall_T_10, 1, 0)
node _io_debug_sa_stall_T_12 = add(_io_debug_sa_stall_T_9, _io_debug_sa_stall_T_11)
node _io_debug_sa_stall_T_13 = bits(_io_debug_sa_stall_T_12, 2, 0)
connect io.debug.sa_stall, _io_debug_sa_stall_T_13
connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits
connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid
connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready
when io.block :
connect salloc_arb.io.out[0].ready, UInt<1>(0h0)
connect io.salloc_req[0].valid, UInt<1>(0h0)
reg salloc_outs : { valid : UInt<1>, vid : UInt<2>, out_vid : UInt<2>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}}[1], clock
node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.credit_return, _io_in_credit_return_T_1
node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _io_in_vc_free_T_5 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_6 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_7 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_8 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_9 = or(_io_in_vc_free_T_5, _io_in_vc_free_T_6)
node _io_in_vc_free_T_10 = or(_io_in_vc_free_T_9, _io_in_vc_free_T_7)
node _io_in_vc_free_T_11 = or(_io_in_vc_free_T_10, _io_in_vc_free_T_8)
wire _io_in_vc_free_WIRE : UInt<1>
connect _io_in_vc_free_WIRE, _io_in_vc_free_T_11
node _io_in_vc_free_T_12 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE)
node _io_in_vc_free_T_13 = mux(_io_in_vc_free_T_12, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.vc_free, _io_in_vc_free_T_13
node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
connect salloc_outs[0].valid, _salloc_outs_0_valid_T
node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 3, 2)
node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 1, 0)
node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi)
node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo)
node _salloc_outs_0_vid_T_2 = bits(_salloc_outs_0_vid_T_1, 1, 1)
node _salloc_outs_0_vid_T_3 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_2)
connect salloc_outs[0].vid, _salloc_outs_0_vid_T_3
node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
wire vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[4]}
wire _vc_sel_WIRE : UInt<1>[4]
node _vc_sel_T_4 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_5 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_6 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_7 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_8 = or(_vc_sel_T_4, _vc_sel_T_5)
node _vc_sel_T_9 = or(_vc_sel_T_8, _vc_sel_T_6)
node _vc_sel_T_10 = or(_vc_sel_T_9, _vc_sel_T_7)
wire _vc_sel_WIRE_1 : UInt<1>
connect _vc_sel_WIRE_1, _vc_sel_T_10
connect _vc_sel_WIRE[0], _vc_sel_WIRE_1
node _vc_sel_T_11 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_12 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_13 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_14 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_15 = or(_vc_sel_T_11, _vc_sel_T_12)
node _vc_sel_T_16 = or(_vc_sel_T_15, _vc_sel_T_13)
node _vc_sel_T_17 = or(_vc_sel_T_16, _vc_sel_T_14)
wire _vc_sel_WIRE_2 : UInt<1>
connect _vc_sel_WIRE_2, _vc_sel_T_17
connect _vc_sel_WIRE[1], _vc_sel_WIRE_2
node _vc_sel_T_18 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_19 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_20 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_21 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_22 = or(_vc_sel_T_18, _vc_sel_T_19)
node _vc_sel_T_23 = or(_vc_sel_T_22, _vc_sel_T_20)
node _vc_sel_T_24 = or(_vc_sel_T_23, _vc_sel_T_21)
wire _vc_sel_WIRE_3 : UInt<1>
connect _vc_sel_WIRE_3, _vc_sel_T_24
connect _vc_sel_WIRE[2], _vc_sel_WIRE_3
node _vc_sel_T_25 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_26 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_27 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_28 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_29 = or(_vc_sel_T_25, _vc_sel_T_26)
node _vc_sel_T_30 = or(_vc_sel_T_29, _vc_sel_T_27)
node _vc_sel_T_31 = or(_vc_sel_T_30, _vc_sel_T_28)
wire _vc_sel_WIRE_4 : UInt<1>
connect _vc_sel_WIRE_4, _vc_sel_T_31
connect _vc_sel_WIRE[3], _vc_sel_WIRE_4
connect vc_sel.`0`, _vc_sel_WIRE
wire _vc_sel_WIRE_5 : UInt<1>[1]
node _vc_sel_T_32 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_33 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_34 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_35 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_36 = or(_vc_sel_T_32, _vc_sel_T_33)
node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_34)
node _vc_sel_T_38 = or(_vc_sel_T_37, _vc_sel_T_35)
wire _vc_sel_WIRE_6 : UInt<1>
connect _vc_sel_WIRE_6, _vc_sel_T_38
connect _vc_sel_WIRE_5[0], _vc_sel_WIRE_6
connect vc_sel.`1`, _vc_sel_WIRE_5
node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1])
node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2])
node channel_oh_0 = or(_channel_oh_T_1, vc_sel.`0`[3])
node virt_channel_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0])
node virt_channel_hi = cat(vc_sel.`0`[3], vc_sel.`0`[2])
node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo)
node virt_channel_hi_1 = bits(_virt_channel_T, 3, 2)
node virt_channel_lo_1 = bits(_virt_channel_T, 1, 0)
node _virt_channel_T_1 = orr(virt_channel_hi_1)
node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1)
node _virt_channel_T_3 = bits(_virt_channel_T_2, 1, 1)
node _virt_channel_T_4 = cat(_virt_channel_T_1, _virt_channel_T_3)
node _virt_channel_T_5 = mux(channel_oh_0, _virt_channel_T_4, UInt<1>(0h0))
node _virt_channel_T_6 = mux(vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0))
node _virt_channel_T_7 = or(_virt_channel_T_5, _virt_channel_T_6)
wire virt_channel : UInt<2>
connect virt_channel, _virt_channel_T_7
node _T_62 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
when _T_62 :
connect salloc_outs[0].out_vid, virt_channel
node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_payload_T_4 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_5 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_6 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_7 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_8 = or(_salloc_outs_0_flit_payload_T_4, _salloc_outs_0_flit_payload_T_5)
node _salloc_outs_0_flit_payload_T_9 = or(_salloc_outs_0_flit_payload_T_8, _salloc_outs_0_flit_payload_T_6)
node _salloc_outs_0_flit_payload_T_10 = or(_salloc_outs_0_flit_payload_T_9, _salloc_outs_0_flit_payload_T_7)
wire _salloc_outs_0_flit_payload_WIRE : UInt<37>
connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_10
connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE
node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_head_T_4 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_5 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_6 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_7 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_8 = or(_salloc_outs_0_flit_head_T_4, _salloc_outs_0_flit_head_T_5)
node _salloc_outs_0_flit_head_T_9 = or(_salloc_outs_0_flit_head_T_8, _salloc_outs_0_flit_head_T_6)
node _salloc_outs_0_flit_head_T_10 = or(_salloc_outs_0_flit_head_T_9, _salloc_outs_0_flit_head_T_7)
wire _salloc_outs_0_flit_head_WIRE : UInt<1>
connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_10
connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE
node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_tail_T_4 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_5 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_6 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_7 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_8 = or(_salloc_outs_0_flit_tail_T_4, _salloc_outs_0_flit_tail_T_5)
node _salloc_outs_0_flit_tail_T_9 = or(_salloc_outs_0_flit_tail_T_8, _salloc_outs_0_flit_tail_T_6)
node _salloc_outs_0_flit_tail_T_10 = or(_salloc_outs_0_flit_tail_T_9, _salloc_outs_0_flit_tail_T_7)
wire _salloc_outs_0_flit_tail_WIRE : UInt<1>
connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_10
connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE
node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}
node _salloc_outs_0_flit_flow_T_4 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_5 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_6 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_7 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_8 = or(_salloc_outs_0_flit_flow_T_4, _salloc_outs_0_flit_flow_T_5)
node _salloc_outs_0_flit_flow_T_9 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_6)
node _salloc_outs_0_flit_flow_T_10 = or(_salloc_outs_0_flit_flow_T_9, _salloc_outs_0_flit_flow_T_7)
wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<1>
connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_10
connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1
node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_15 = or(_salloc_outs_0_flit_flow_T_11, _salloc_outs_0_flit_flow_T_12)
node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_15, _salloc_outs_0_flit_flow_T_13)
node _salloc_outs_0_flit_flow_T_17 = or(_salloc_outs_0_flit_flow_T_16, _salloc_outs_0_flit_flow_T_14)
wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4>
connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_17
connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2
node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_19 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_20 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_21 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_18, _salloc_outs_0_flit_flow_T_19)
node _salloc_outs_0_flit_flow_T_23 = or(_salloc_outs_0_flit_flow_T_22, _salloc_outs_0_flit_flow_T_20)
node _salloc_outs_0_flit_flow_T_24 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_21)
wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<1>
connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_24
connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3
node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_26 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_27 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_28 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_29 = or(_salloc_outs_0_flit_flow_T_25, _salloc_outs_0_flit_flow_T_26)
node _salloc_outs_0_flit_flow_T_30 = or(_salloc_outs_0_flit_flow_T_29, _salloc_outs_0_flit_flow_T_27)
node _salloc_outs_0_flit_flow_T_31 = or(_salloc_outs_0_flit_flow_T_30, _salloc_outs_0_flit_flow_T_28)
wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4>
connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_31
connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4
node _salloc_outs_0_flit_flow_T_32 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_33 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_34 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_35 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_36 = or(_salloc_outs_0_flit_flow_T_32, _salloc_outs_0_flit_flow_T_33)
node _salloc_outs_0_flit_flow_T_37 = or(_salloc_outs_0_flit_flow_T_36, _salloc_outs_0_flit_flow_T_34)
node _salloc_outs_0_flit_flow_T_38 = or(_salloc_outs_0_flit_flow_T_37, _salloc_outs_0_flit_flow_T_35)
wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<1>
connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_38
connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5
connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE
else :
invalidate salloc_outs[0].out_vid
invalidate salloc_outs[0].flit.virt_channel_id
invalidate salloc_outs[0].flit.flow.egress_node_id
invalidate salloc_outs[0].flit.flow.egress_node
invalidate salloc_outs[0].flit.flow.ingress_node_id
invalidate salloc_outs[0].flit.flow.ingress_node
invalidate salloc_outs[0].flit.flow.vnet_id
invalidate salloc_outs[0].flit.payload
invalidate salloc_outs[0].flit.tail
invalidate salloc_outs[0].flit.head
invalidate salloc_outs[0].flit.virt_channel_id
connect io.out[0].valid, salloc_outs[0].valid
connect io.out[0].bits.flit, salloc_outs[0].flit
connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid
connect states[0].vc_sel.`0`[1], UInt<1>(0h0)
connect states[0].vc_sel.`0`[2], UInt<1>(0h0)
connect states[0].vc_sel.`0`[3], UInt<1>(0h0)
connect states[1].vc_sel.`0`[2], UInt<1>(0h0)
connect states[1].vc_sel.`0`[3], UInt<1>(0h0)
invalidate states[2].fifo_deps
invalidate states[2].flow.egress_node_id
invalidate states[2].flow.egress_node
invalidate states[2].flow.ingress_node_id
invalidate states[2].flow.ingress_node
invalidate states[2].flow.vnet_id
invalidate states[2].vc_sel.`0`[0]
invalidate states[2].vc_sel.`0`[1]
invalidate states[2].vc_sel.`0`[2]
invalidate states[2].vc_sel.`0`[3]
invalidate states[2].vc_sel.`1`[0]
invalidate states[2].g
connect states[3].vc_sel.`0`[0], UInt<1>(0h0)
connect states[3].vc_sel.`0`[1], UInt<1>(0h0)
connect states[3].vc_sel.`0`[2], UInt<1>(0h0)
node _T_63 = asUInt(reset)
when _T_63 :
connect states[0].g, UInt<3>(0h0)
connect states[1].g, UInt<3>(0h0)
connect states[2].g, UInt<3>(0h0)
connect states[3].g, UInt<3>(0h0) | module InputUnit_24( // @[InputUnit.scala:158:7]
input clock, // @[InputUnit.scala:158:7]
input reset, // @[InputUnit.scala:158:7]
output [1:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14]
output io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
output io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14]
output io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_3, // @[InputUnit.scala:170:14]
input io_vcalloc_req_ready, // @[InputUnit.scala:170:14]
output io_vcalloc_req_valid, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_3, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_3, // @[InputUnit.scala:170:14]
input io_salloc_req_0_ready, // @[InputUnit.scala:170:14]
output io_salloc_req_0_valid, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14]
output io_out_0_valid, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14]
output [36:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14]
output [1:0] io_debug_va_stall, // @[InputUnit.scala:170:14]
output [1:0] io_debug_sa_stall, // @[InputUnit.scala:170:14]
input io_in_flit_0_valid, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14]
input [36:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14]
output [3:0] io_in_credit_return, // @[InputUnit.scala:170:14]
output [3:0] io_in_vc_free // @[InputUnit.scala:170:14]
);
wire vcalloc_vals_3; // @[InputUnit.scala:266:32]
wire vcalloc_vals_1; // @[InputUnit.scala:266:32]
wire vcalloc_vals_0; // @[InputUnit.scala:266:32]
wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26]
wire [3:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26]
wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29]
wire [1:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29]
wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28]
wire [36:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28]
wire [36:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28]
wire [36:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28]
wire [36:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28]
reg [2:0] states_0_g; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_0_0; // @[InputUnit.scala:192:19]
reg states_0_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19]
reg states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19]
reg states_0_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_1_g; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_0; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_1_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19]
reg states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19]
reg states_1_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_3_g; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_3_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19]
reg states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19]
reg states_3_flow_egress_node_id; // @[InputUnit.scala:192:19]
wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30]
wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:158:7, :192:19, :229:22]
wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:158:7, :192:19, :229:22]
wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:158:7, :192:19, :229:22]
reg [3:0] mask; // @[InputUnit.scala:250:21]
wire [3:0] _vcalloc_filter_T_3 = {vcalloc_vals_3, 1'h0, vcalloc_vals_1, vcalloc_vals_0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32]
wire [7:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 8'h1 : _vcalloc_filter_T_3[1] ? 8'h2 : _vcalloc_filter_T_3[2] ? 8'h4 : _vcalloc_filter_T_3[3] ? 8'h8 : vcalloc_vals_0 ? 8'h10 : vcalloc_vals_1 ? 8'h20 : {vcalloc_vals_3, 7'h0}; // @[OneHot.scala:85:71]
wire [3:0] vcalloc_sel = vcalloc_filter[3:0] | vcalloc_filter[7:4]; // @[Mux.scala:50:70]
wire io_vcalloc_req_valid_0 = vcalloc_vals_0 | vcalloc_vals_1 | vcalloc_vals_3; // @[package.scala:81:59]
assign vcalloc_vals_0 = states_0_g == 3'h2; // @[InputUnit.scala:158:7, :192:19, :266:32]
assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:158:7, :192:19, :266:32]
assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:158:7, :192:19, :266:32]
wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
wire _GEN_1 = _GEN_0 & vcalloc_sel[0]; // @[Mux.scala:32:36]
wire _GEN_2 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36]
wire _GEN_3 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36] |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_preMul_e11_s53_7 :
output io : { flip op : UInt<2>, flip a : UInt<65>, flip b : UInt<65>, flip c : UInt<65>, mulAddA : UInt<53>, mulAddB : UInt<53>, mulAddC : UInt<106>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<13>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<6>, highAlignedSigC : UInt<55>, bit0AlignedSigC : UInt<1>}}
node rawA_exp = bits(io.a, 63, 52)
node _rawA_isZero_T = bits(rawA_exp, 11, 9)
node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0))
node _rawA_isSpecial_T = bits(rawA_exp, 11, 10)
node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3))
wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>}
node _rawA_out_isNaN_T = bits(rawA_exp, 9, 9)
node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T)
connect rawA.isNaN, _rawA_out_isNaN_T_1
node _rawA_out_isInf_T = bits(rawA_exp, 9, 9)
node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0))
node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1)
connect rawA.isInf, _rawA_out_isInf_T_2
connect rawA.isZero, rawA_isZero
node _rawA_out_sign_T = bits(io.a, 64, 64)
connect rawA.sign, _rawA_out_sign_T
node _rawA_out_sExp_T = cvt(rawA_exp)
connect rawA.sExp, _rawA_out_sExp_T
node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0))
node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T)
node _rawA_out_sig_T_2 = bits(io.a, 51, 0)
node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2)
connect rawA.sig, _rawA_out_sig_T_3
node rawB_exp = bits(io.b, 63, 52)
node _rawB_isZero_T = bits(rawB_exp, 11, 9)
node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0))
node _rawB_isSpecial_T = bits(rawB_exp, 11, 10)
node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3))
wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>}
node _rawB_out_isNaN_T = bits(rawB_exp, 9, 9)
node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T)
connect rawB.isNaN, _rawB_out_isNaN_T_1
node _rawB_out_isInf_T = bits(rawB_exp, 9, 9)
node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0))
node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1)
connect rawB.isInf, _rawB_out_isInf_T_2
connect rawB.isZero, rawB_isZero
node _rawB_out_sign_T = bits(io.b, 64, 64)
connect rawB.sign, _rawB_out_sign_T
node _rawB_out_sExp_T = cvt(rawB_exp)
connect rawB.sExp, _rawB_out_sExp_T
node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0))
node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T)
node _rawB_out_sig_T_2 = bits(io.b, 51, 0)
node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2)
connect rawB.sig, _rawB_out_sig_T_3
node rawC_exp = bits(io.c, 63, 52)
node _rawC_isZero_T = bits(rawC_exp, 11, 9)
node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0))
node _rawC_isSpecial_T = bits(rawC_exp, 11, 10)
node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3))
wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>}
node _rawC_out_isNaN_T = bits(rawC_exp, 9, 9)
node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T)
connect rawC.isNaN, _rawC_out_isNaN_T_1
node _rawC_out_isInf_T = bits(rawC_exp, 9, 9)
node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0))
node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1)
connect rawC.isInf, _rawC_out_isInf_T_2
connect rawC.isZero, rawC_isZero
node _rawC_out_sign_T = bits(io.c, 64, 64)
connect rawC.sign, _rawC_out_sign_T
node _rawC_out_sExp_T = cvt(rawC_exp)
connect rawC.sExp, _rawC_out_sExp_T
node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0))
node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T)
node _rawC_out_sig_T_2 = bits(io.c, 51, 0)
node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2)
connect rawC.sig, _rawC_out_sig_T_3
node _signProd_T = xor(rawA.sign, rawB.sign)
node _signProd_T_1 = bits(io.op, 1, 1)
node signProd = xor(_signProd_T, _signProd_T_1)
node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp)
node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<12>(0h838)))
node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1)
node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2)
node _doSubMags_T = xor(signProd, rawC.sign)
node _doSubMags_T_1 = bits(io.op, 0, 0)
node doSubMags = xor(_doSubMags_T, _doSubMags_T_1)
node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp)
node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1)
node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1)
node posNatCAlignDist = bits(sNatCAlignDist, 12, 0)
node _isMinCAlign_T = or(rawA.isZero, rawB.isZero)
node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0)))
node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1)
node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0))
node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<6>(0h35))
node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1)
node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2)
node _CAlignDist_T = lt(posNatCAlignDist, UInt<8>(0ha1))
node _CAlignDist_T_1 = bits(posNatCAlignDist, 7, 0)
node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<8>(0ha1))
node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2)
node _mainAlignedSigC_T = not(rawC.sig)
node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig)
node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<111>(0h7fffffffffffffffffffffffffff), UInt<111>(0h0))
node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2)
node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3)
node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist)
node _reduced4CExtra_T = shl(rawC.sig, 0)
wire reduced4CExtra_reducedVec : UInt<1>[14]
node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0)
node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T)
connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1
node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4)
node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T)
connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1
node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8)
node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T)
connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1
node _reduced4CExtra_reducedVec_3_T = bits(_reduced4CExtra_T, 15, 12)
node _reduced4CExtra_reducedVec_3_T_1 = orr(_reduced4CExtra_reducedVec_3_T)
connect reduced4CExtra_reducedVec[3], _reduced4CExtra_reducedVec_3_T_1
node _reduced4CExtra_reducedVec_4_T = bits(_reduced4CExtra_T, 19, 16)
node _reduced4CExtra_reducedVec_4_T_1 = orr(_reduced4CExtra_reducedVec_4_T)
connect reduced4CExtra_reducedVec[4], _reduced4CExtra_reducedVec_4_T_1
node _reduced4CExtra_reducedVec_5_T = bits(_reduced4CExtra_T, 23, 20)
node _reduced4CExtra_reducedVec_5_T_1 = orr(_reduced4CExtra_reducedVec_5_T)
connect reduced4CExtra_reducedVec[5], _reduced4CExtra_reducedVec_5_T_1
node _reduced4CExtra_reducedVec_6_T = bits(_reduced4CExtra_T, 27, 24)
node _reduced4CExtra_reducedVec_6_T_1 = orr(_reduced4CExtra_reducedVec_6_T)
connect reduced4CExtra_reducedVec[6], _reduced4CExtra_reducedVec_6_T_1
node _reduced4CExtra_reducedVec_7_T = bits(_reduced4CExtra_T, 31, 28)
node _reduced4CExtra_reducedVec_7_T_1 = orr(_reduced4CExtra_reducedVec_7_T)
connect reduced4CExtra_reducedVec[7], _reduced4CExtra_reducedVec_7_T_1
node _reduced4CExtra_reducedVec_8_T = bits(_reduced4CExtra_T, 35, 32)
node _reduced4CExtra_reducedVec_8_T_1 = orr(_reduced4CExtra_reducedVec_8_T)
connect reduced4CExtra_reducedVec[8], _reduced4CExtra_reducedVec_8_T_1
node _reduced4CExtra_reducedVec_9_T = bits(_reduced4CExtra_T, 39, 36)
node _reduced4CExtra_reducedVec_9_T_1 = orr(_reduced4CExtra_reducedVec_9_T)
connect reduced4CExtra_reducedVec[9], _reduced4CExtra_reducedVec_9_T_1
node _reduced4CExtra_reducedVec_10_T = bits(_reduced4CExtra_T, 43, 40)
node _reduced4CExtra_reducedVec_10_T_1 = orr(_reduced4CExtra_reducedVec_10_T)
connect reduced4CExtra_reducedVec[10], _reduced4CExtra_reducedVec_10_T_1
node _reduced4CExtra_reducedVec_11_T = bits(_reduced4CExtra_T, 47, 44)
node _reduced4CExtra_reducedVec_11_T_1 = orr(_reduced4CExtra_reducedVec_11_T)
connect reduced4CExtra_reducedVec[11], _reduced4CExtra_reducedVec_11_T_1
node _reduced4CExtra_reducedVec_12_T = bits(_reduced4CExtra_T, 51, 48)
node _reduced4CExtra_reducedVec_12_T_1 = orr(_reduced4CExtra_reducedVec_12_T)
connect reduced4CExtra_reducedVec[12], _reduced4CExtra_reducedVec_12_T_1
node _reduced4CExtra_reducedVec_13_T = bits(_reduced4CExtra_T, 53, 52)
node _reduced4CExtra_reducedVec_13_T_1 = orr(_reduced4CExtra_reducedVec_13_T)
connect reduced4CExtra_reducedVec[13], _reduced4CExtra_reducedVec_13_T_1
node reduced4CExtra_lo_lo_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1])
node reduced4CExtra_lo_lo = cat(reduced4CExtra_lo_lo_hi, reduced4CExtra_reducedVec[0])
node reduced4CExtra_lo_hi_lo = cat(reduced4CExtra_reducedVec[4], reduced4CExtra_reducedVec[3])
node reduced4CExtra_lo_hi_hi = cat(reduced4CExtra_reducedVec[6], reduced4CExtra_reducedVec[5])
node reduced4CExtra_lo_hi = cat(reduced4CExtra_lo_hi_hi, reduced4CExtra_lo_hi_lo)
node reduced4CExtra_lo = cat(reduced4CExtra_lo_hi, reduced4CExtra_lo_lo)
node reduced4CExtra_hi_lo_hi = cat(reduced4CExtra_reducedVec[9], reduced4CExtra_reducedVec[8])
node reduced4CExtra_hi_lo = cat(reduced4CExtra_hi_lo_hi, reduced4CExtra_reducedVec[7])
node reduced4CExtra_hi_hi_lo = cat(reduced4CExtra_reducedVec[11], reduced4CExtra_reducedVec[10])
node reduced4CExtra_hi_hi_hi = cat(reduced4CExtra_reducedVec[13], reduced4CExtra_reducedVec[12])
node reduced4CExtra_hi_hi = cat(reduced4CExtra_hi_hi_hi, reduced4CExtra_hi_hi_lo)
node reduced4CExtra_hi = cat(reduced4CExtra_hi_hi, reduced4CExtra_hi_lo)
node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_lo)
node _reduced4CExtra_T_2 = shr(CAlignDist, 2)
node reduced4CExtra_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), _reduced4CExtra_T_2)
node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 36, 24)
node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 7, 0)
node _reduced4CExtra_T_5 = shl(UInt<4>(0hf), 4)
node _reduced4CExtra_T_6 = xor(UInt<8>(0hff), _reduced4CExtra_T_5)
node _reduced4CExtra_T_7 = shr(_reduced4CExtra_T_4, 4)
node _reduced4CExtra_T_8 = and(_reduced4CExtra_T_7, _reduced4CExtra_T_6)
node _reduced4CExtra_T_9 = bits(_reduced4CExtra_T_4, 3, 0)
node _reduced4CExtra_T_10 = shl(_reduced4CExtra_T_9, 4)
node _reduced4CExtra_T_11 = not(_reduced4CExtra_T_6)
node _reduced4CExtra_T_12 = and(_reduced4CExtra_T_10, _reduced4CExtra_T_11)
node _reduced4CExtra_T_13 = or(_reduced4CExtra_T_8, _reduced4CExtra_T_12)
node _reduced4CExtra_T_14 = bits(_reduced4CExtra_T_6, 5, 0)
node _reduced4CExtra_T_15 = shl(_reduced4CExtra_T_14, 2)
node _reduced4CExtra_T_16 = xor(_reduced4CExtra_T_6, _reduced4CExtra_T_15)
node _reduced4CExtra_T_17 = shr(_reduced4CExtra_T_13, 2)
node _reduced4CExtra_T_18 = and(_reduced4CExtra_T_17, _reduced4CExtra_T_16)
node _reduced4CExtra_T_19 = bits(_reduced4CExtra_T_13, 5, 0)
node _reduced4CExtra_T_20 = shl(_reduced4CExtra_T_19, 2)
node _reduced4CExtra_T_21 = not(_reduced4CExtra_T_16)
node _reduced4CExtra_T_22 = and(_reduced4CExtra_T_20, _reduced4CExtra_T_21)
node _reduced4CExtra_T_23 = or(_reduced4CExtra_T_18, _reduced4CExtra_T_22)
node _reduced4CExtra_T_24 = bits(_reduced4CExtra_T_16, 6, 0)
node _reduced4CExtra_T_25 = shl(_reduced4CExtra_T_24, 1)
node _reduced4CExtra_T_26 = xor(_reduced4CExtra_T_16, _reduced4CExtra_T_25)
node _reduced4CExtra_T_27 = shr(_reduced4CExtra_T_23, 1)
node _reduced4CExtra_T_28 = and(_reduced4CExtra_T_27, _reduced4CExtra_T_26)
node _reduced4CExtra_T_29 = bits(_reduced4CExtra_T_23, 6, 0)
node _reduced4CExtra_T_30 = shl(_reduced4CExtra_T_29, 1)
node _reduced4CExtra_T_31 = not(_reduced4CExtra_T_26)
node _reduced4CExtra_T_32 = and(_reduced4CExtra_T_30, _reduced4CExtra_T_31)
node _reduced4CExtra_T_33 = or(_reduced4CExtra_T_28, _reduced4CExtra_T_32)
node _reduced4CExtra_T_34 = bits(_reduced4CExtra_T_3, 12, 8)
node _reduced4CExtra_T_35 = bits(_reduced4CExtra_T_34, 3, 0)
node _reduced4CExtra_T_36 = bits(_reduced4CExtra_T_35, 1, 0)
node _reduced4CExtra_T_37 = bits(_reduced4CExtra_T_36, 0, 0)
node _reduced4CExtra_T_38 = bits(_reduced4CExtra_T_36, 1, 1)
node _reduced4CExtra_T_39 = cat(_reduced4CExtra_T_37, _reduced4CExtra_T_38)
node _reduced4CExtra_T_40 = bits(_reduced4CExtra_T_35, 3, 2)
node _reduced4CExtra_T_41 = bits(_reduced4CExtra_T_40, 0, 0)
node _reduced4CExtra_T_42 = bits(_reduced4CExtra_T_40, 1, 1)
node _reduced4CExtra_T_43 = cat(_reduced4CExtra_T_41, _reduced4CExtra_T_42)
node _reduced4CExtra_T_44 = cat(_reduced4CExtra_T_39, _reduced4CExtra_T_43)
node _reduced4CExtra_T_45 = bits(_reduced4CExtra_T_34, 4, 4)
node _reduced4CExtra_T_46 = cat(_reduced4CExtra_T_44, _reduced4CExtra_T_45)
node _reduced4CExtra_T_47 = cat(_reduced4CExtra_T_33, _reduced4CExtra_T_46)
node _reduced4CExtra_T_48 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_47)
node reduced4CExtra = orr(_reduced4CExtra_T_48)
node _alignedSigC_T = shr(mainAlignedSigC, 3)
node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0)
node _alignedSigC_T_2 = andr(_alignedSigC_T_1)
node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0))
node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3)
node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0)
node _alignedSigC_T_6 = orr(_alignedSigC_T_5)
node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra)
node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7)
node alignedSigC_hi = asUInt(_alignedSigC_T)
node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8)
connect io.mulAddA, rawA.sig
connect io.mulAddB, rawB.sig
node _io_mulAddC_T = bits(alignedSigC, 106, 1)
connect io.mulAddC, _io_mulAddC_T
node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 51, 51)
node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1)
node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 51, 51)
node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4)
node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5)
node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 51, 51)
node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8)
node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9)
connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10
node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN)
connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T
connect io.toPostMul.isInfA, rawA.isInf
connect io.toPostMul.isZeroA, rawA.isZero
connect io.toPostMul.isInfB, rawB.isInf
connect io.toPostMul.isZeroB, rawB.isZero
connect io.toPostMul.signProd, signProd
connect io.toPostMul.isNaNC, rawC.isNaN
connect io.toPostMul.isInfC, rawC.isInf
connect io.toPostMul.isZeroC, rawC.isZero
node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<7>(0h35)))
node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1)
node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1)
node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2)
connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3
connect io.toPostMul.doSubMags, doSubMags
connect io.toPostMul.CIsDominant, CIsDominant
node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 5, 0)
connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T
node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 161, 107)
connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T
node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0)
connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T | module MulAddRecFNToRaw_preMul_e11_s53_7( // @[MulAddRecFN.scala:71:7]
input [1:0] io_op, // @[MulAddRecFN.scala:74:16]
input [64:0] io_a, // @[MulAddRecFN.scala:74:16]
input [64:0] io_b, // @[MulAddRecFN.scala:74:16]
input [64:0] io_c, // @[MulAddRecFN.scala:74:16]
output [52:0] io_mulAddA, // @[MulAddRecFN.scala:74:16]
output [52:0] io_mulAddB, // @[MulAddRecFN.scala:74:16]
output [105:0] io_mulAddC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16]
output [12:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16]
output [5:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16]
output [54:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16]
);
wire [1:0] io_op_0 = io_op; // @[MulAddRecFN.scala:71:7]
wire [64:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7]
wire [64:0] io_b_0 = io_b; // @[MulAddRecFN.scala:71:7]
wire [64:0] io_c_0 = io_c; // @[MulAddRecFN.scala:71:7]
wire [7:0] _reduced4CExtra_T_6 = 8'hF; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_5 = 8'hF0; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_11 = 8'hF0; // @[primitives.scala:77:20]
wire [5:0] _reduced4CExtra_T_14 = 6'hF; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_15 = 8'h3C; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_16 = 8'h33; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_21 = 8'hCC; // @[primitives.scala:77:20]
wire [6:0] _reduced4CExtra_T_24 = 7'h33; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_25 = 8'h66; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_26 = 8'h55; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_31 = 8'hAA; // @[primitives.scala:77:20]
wire [105:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30]
wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58]
wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42]
wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire signProd; // @[MulAddRecFN.scala:97:42]
wire rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire doSubMags; // @[MulAddRecFN.scala:102:42]
wire CIsDominant; // @[MulAddRecFN.scala:110:23]
wire [5:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47]
wire [54:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20]
wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48]
wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7]
wire [12:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7]
wire [5:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
wire [54:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire [52:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
wire [52:0] io_mulAddB_0; // @[MulAddRecFN.scala:71:7]
wire [105:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
wire [11:0] rawA_exp = io_a_0[63:52]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawA_isZero_T = rawA_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawA_isSpecial_T = rawA_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [12:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [53:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [12:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_isNaN_T = rawA_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawA_out_isInf_T = rawA_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawA_out_sign_T = io_a_0[64]; // @[rawFloatFromRecFN.scala:59:25]
assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [51:0] _rawA_out_sig_T_2 = io_a_0[51:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [11:0] rawB_exp = io_b_0[63:52]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawB_isZero_T = rawB_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawB_isZero_0 = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawB_isZero = rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawB_isSpecial_T = rawB_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfB_0 = rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroB_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [12:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [53:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [12:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_isNaN_T = rawB_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawB_out_isInf_T = rawB_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawB_out_sign_T = io_b_0[64]; // @[rawFloatFromRecFN.scala:59:25]
assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawB_out_sig_T = ~rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [51:0] _rawB_out_sig_T_2 = io_b_0[51:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [11:0] rawC_exp = io_c_0[63:52]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawC_isZero_T = rawC_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawC_isZero_0 = _rawC_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawC_isZero = rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawC_isSpecial_T = rawC_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawC_isSpecial = &_rawC_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
assign io_toPostMul_isNaNC_0 = rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfC_0 = rawC_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroC_0 = rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [12:0] _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [53:0] _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawC_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [12:0] rawC_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] _reduced4CExtra_T = rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isNaN_T = rawC_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawC_out_isInf_T = rawC_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawC_out_isNaN_T_1 = rawC_isSpecial & _rawC_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawC_isNaN = _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawC_out_isInf_T_1 = ~_rawC_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawC_out_isInf_T_2 = rawC_isSpecial & _rawC_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawC_isInf = _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawC_out_sign_T = io_c_0[64]; // @[rawFloatFromRecFN.scala:59:25]
assign rawC_sign = _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawC_out_sExp_T = {1'h0, rawC_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawC_sExp = _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawC_out_sig_T = ~rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawC_out_sig_T_1 = {1'h0, _rawC_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [51:0] _rawC_out_sig_T_2 = io_c_0[51:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawC_out_sig_T_3 = {_rawC_out_sig_T_1, _rawC_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawC_sig = _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire _signProd_T = rawA_sign ^ rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _signProd_T_1 = io_op_0[1]; // @[MulAddRecFN.scala:71:7, :97:49]
assign signProd = _signProd_T ^ _signProd_T_1; // @[MulAddRecFN.scala:97:{30,42,49}]
assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42]
wire [13:0] _sExpAlignedProd_T = {rawA_sExp[12], rawA_sExp} + {rawB_sExp[12], rawB_sExp}; // @[rawFloatFromRecFN.scala:55:23]
wire [14:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[13], _sExpAlignedProd_T} - 15'h7C8; // @[MulAddRecFN.scala:100:{19,32}]
wire [13:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[13:0]; // @[MulAddRecFN.scala:100:32]
wire [13:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32]
wire _doSubMags_T = signProd ^ rawC_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _doSubMags_T_1 = io_op_0[0]; // @[MulAddRecFN.scala:71:7, :102:49]
assign doSubMags = _doSubMags_T ^ _doSubMags_T_1; // @[MulAddRecFN.scala:102:{30,42,49}]
assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42]
wire [14:0] _GEN = {sExpAlignedProd[13], sExpAlignedProd}; // @[MulAddRecFN.scala:100:32, :106:42]
wire [14:0] _sNatCAlignDist_T = _GEN - {{2{rawC_sExp[12]}}, rawC_sExp}; // @[rawFloatFromRecFN.scala:55:23]
wire [13:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[13:0]; // @[MulAddRecFN.scala:106:42]
wire [13:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42]
wire [12:0] posNatCAlignDist = sNatCAlignDist[12:0]; // @[MulAddRecFN.scala:106:42, :107:42]
wire _isMinCAlign_T = rawA_isZero | rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 14'sh0; // @[MulAddRecFN.scala:106:42, :108:69, :130:11]
wire isMinCAlign = _isMinCAlign_T | _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}]
wire _CIsDominant_T = ~rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _CIsDominant_T_1 = posNatCAlignDist < 13'h36; // @[MulAddRecFN.scala:107:42, :110:60]
wire _CIsDominant_T_2 = isMinCAlign | _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}]
assign CIsDominant = _CIsDominant_T & _CIsDominant_T_2; // @[MulAddRecFN.scala:110:{9,23,39}]
assign io_toPostMul_CIsDominant_0 = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23]
wire _CAlignDist_T = posNatCAlignDist < 13'hA1; // @[MulAddRecFN.scala:107:42, :114:34]
wire [7:0] _CAlignDist_T_1 = posNatCAlignDist[7:0]; // @[MulAddRecFN.scala:107:42, :115:33]
wire [7:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 8'hA1; // @[MulAddRecFN.scala:114:{16,34}, :115:33]
wire [7:0] CAlignDist = isMinCAlign ? 8'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16]
wire [53:0] _mainAlignedSigC_T = ~rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] _mainAlignedSigC_T_1 = doSubMags ? _mainAlignedSigC_T : rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [110:0] _mainAlignedSigC_T_2 = {111{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53]
wire [164:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}]
wire [164:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}]
wire [164:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}]
wire _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_7_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_8_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_9_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_10_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_11_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_12_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_13_T_1; // @[primitives.scala:123:57]
wire reduced4CExtra_reducedVec_0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_1; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_2; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_3; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_4; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_5; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_6; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_7; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_8; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_9; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_10; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_11; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_12; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_13; // @[primitives.scala:118:30]
wire [3:0] _reduced4CExtra_reducedVec_0_T = _reduced4CExtra_T[3:0]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_0_T_1 = |_reduced4CExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_0 = _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_1_T = _reduced4CExtra_T[7:4]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_1_T_1 = |_reduced4CExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_1 = _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_2_T = _reduced4CExtra_T[11:8]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_2_T_1 = |_reduced4CExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_2 = _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_3_T = _reduced4CExtra_T[15:12]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_3_T_1 = |_reduced4CExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_3 = _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_4_T = _reduced4CExtra_T[19:16]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_4_T_1 = |_reduced4CExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_4 = _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_5_T = _reduced4CExtra_T[23:20]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_5_T_1 = |_reduced4CExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_5 = _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_6_T = _reduced4CExtra_T[27:24]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_6_T_1 = |_reduced4CExtra_reducedVec_6_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_6 = _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_7_T = _reduced4CExtra_T[31:28]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_7_T_1 = |_reduced4CExtra_reducedVec_7_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_7 = _reduced4CExtra_reducedVec_7_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_8_T = _reduced4CExtra_T[35:32]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_8_T_1 = |_reduced4CExtra_reducedVec_8_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_8 = _reduced4CExtra_reducedVec_8_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_9_T = _reduced4CExtra_T[39:36]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_9_T_1 = |_reduced4CExtra_reducedVec_9_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_9 = _reduced4CExtra_reducedVec_9_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_10_T = _reduced4CExtra_T[43:40]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_10_T_1 = |_reduced4CExtra_reducedVec_10_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_10 = _reduced4CExtra_reducedVec_10_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_11_T = _reduced4CExtra_T[47:44]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_11_T_1 = |_reduced4CExtra_reducedVec_11_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_11 = _reduced4CExtra_reducedVec_11_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_12_T = _reduced4CExtra_T[51:48]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_12_T_1 = |_reduced4CExtra_reducedVec_12_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_12 = _reduced4CExtra_reducedVec_12_T_1; // @[primitives.scala:118:30, :120:54]
wire [1:0] _reduced4CExtra_reducedVec_13_T = _reduced4CExtra_T[53:52]; // @[primitives.scala:123:15]
assign _reduced4CExtra_reducedVec_13_T_1 = |_reduced4CExtra_reducedVec_13_T; // @[primitives.scala:123:{15,57}]
assign reduced4CExtra_reducedVec_13 = _reduced4CExtra_reducedVec_13_T_1; // @[primitives.scala:118:30, :123:57]
wire [1:0] reduced4CExtra_lo_lo_hi = {reduced4CExtra_reducedVec_2, reduced4CExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20]
wire [2:0] reduced4CExtra_lo_lo = {reduced4CExtra_lo_lo_hi, reduced4CExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_lo_hi_lo = {reduced4CExtra_reducedVec_4, reduced4CExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_lo_hi_hi = {reduced4CExtra_reducedVec_6, reduced4CExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20]
wire [3:0] reduced4CExtra_lo_hi = {reduced4CExtra_lo_hi_hi, reduced4CExtra_lo_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] reduced4CExtra_lo = {reduced4CExtra_lo_hi, reduced4CExtra_lo_lo}; // @[primitives.scala:124:20]
wire [1:0] reduced4CExtra_hi_lo_hi = {reduced4CExtra_reducedVec_9, reduced4CExtra_reducedVec_8}; // @[primitives.scala:118:30, :124:20]
wire [2:0] reduced4CExtra_hi_lo = {reduced4CExtra_hi_lo_hi, reduced4CExtra_reducedVec_7}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_hi_hi_lo = {reduced4CExtra_reducedVec_11, reduced4CExtra_reducedVec_10}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_hi_hi_hi = {reduced4CExtra_reducedVec_13, reduced4CExtra_reducedVec_12}; // @[primitives.scala:118:30, :124:20]
wire [3:0] reduced4CExtra_hi_hi = {reduced4CExtra_hi_hi_hi, reduced4CExtra_hi_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] reduced4CExtra_hi = {reduced4CExtra_hi_hi, reduced4CExtra_hi_lo}; // @[primitives.scala:124:20]
wire [13:0] _reduced4CExtra_T_1 = {reduced4CExtra_hi, reduced4CExtra_lo}; // @[primitives.scala:124:20]
wire [5:0] _reduced4CExtra_T_2 = CAlignDist[7:2]; // @[MulAddRecFN.scala:112:12, :124:28]
wire [64:0] reduced4CExtra_shift = $signed(65'sh10000000000000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56]
wire [12:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[36:24]; // @[primitives.scala:76:56, :78:22]
wire [7:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[7:0]; // @[primitives.scala:77:20, :78:22]
wire [3:0] _reduced4CExtra_T_7 = _reduced4CExtra_T_4[7:4]; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_8 = {4'h0, _reduced4CExtra_T_7}; // @[primitives.scala:77:20, :120:54]
wire [3:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:0]; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_10 = {_reduced4CExtra_T_9, 4'h0}; // @[primitives.scala:77:20, :120:54]
wire [7:0] _reduced4CExtra_T_12 = _reduced4CExtra_T_10 & 8'hF0; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_13 = _reduced4CExtra_T_8 | _reduced4CExtra_T_12; // @[primitives.scala:77:20]
wire [5:0] _reduced4CExtra_T_17 = _reduced4CExtra_T_13[7:2]; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_18 = {2'h0, _reduced4CExtra_T_17 & 6'h33}; // @[primitives.scala:77:20, :123:57]
wire [5:0] _reduced4CExtra_T_19 = _reduced4CExtra_T_13[5:0]; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_20 = {_reduced4CExtra_T_19, 2'h0}; // @[primitives.scala:77:20, :123:57]
wire [7:0] _reduced4CExtra_T_22 = _reduced4CExtra_T_20 & 8'hCC; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_23 = _reduced4CExtra_T_18 | _reduced4CExtra_T_22; // @[primitives.scala:77:20]
wire [6:0] _reduced4CExtra_T_27 = _reduced4CExtra_T_23[7:1]; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_28 = {1'h0, _reduced4CExtra_T_27 & 7'h55}; // @[primitives.scala:77:20]
wire [6:0] _reduced4CExtra_T_29 = _reduced4CExtra_T_23[6:0]; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_30 = {_reduced4CExtra_T_29, 1'h0}; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_32 = _reduced4CExtra_T_30 & 8'hAA; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_33 = _reduced4CExtra_T_28 | _reduced4CExtra_T_32; // @[primitives.scala:77:20]
wire [4:0] _reduced4CExtra_T_34 = _reduced4CExtra_T_3[12:8]; // @[primitives.scala:77:20, :78:22]
wire [3:0] _reduced4CExtra_T_35 = _reduced4CExtra_T_34[3:0]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_36 = _reduced4CExtra_T_35[1:0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_37 = _reduced4CExtra_T_36[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_38 = _reduced4CExtra_T_36[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_39 = {_reduced4CExtra_T_37, _reduced4CExtra_T_38}; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_40 = _reduced4CExtra_T_35[3:2]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_41 = _reduced4CExtra_T_40[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_42 = _reduced4CExtra_T_40[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_43 = {_reduced4CExtra_T_41, _reduced4CExtra_T_42}; // @[primitives.scala:77:20]
wire [3:0] _reduced4CExtra_T_44 = {_reduced4CExtra_T_39, _reduced4CExtra_T_43}; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_45 = _reduced4CExtra_T_34[4]; // @[primitives.scala:77:20]
wire [4:0] _reduced4CExtra_T_46 = {_reduced4CExtra_T_44, _reduced4CExtra_T_45}; // @[primitives.scala:77:20]
wire [12:0] _reduced4CExtra_T_47 = {_reduced4CExtra_T_33, _reduced4CExtra_T_46}; // @[primitives.scala:77:20]
wire [13:0] _reduced4CExtra_T_48 = {1'h0, _reduced4CExtra_T_1[12:0] & _reduced4CExtra_T_47}; // @[primitives.scala:77:20, :124:20]
wire reduced4CExtra = |_reduced4CExtra_T_48; // @[MulAddRecFN.scala:122:68, :130:11]
wire [161:0] _alignedSigC_T = mainAlignedSigC[164:3]; // @[MulAddRecFN.scala:120:100, :132:28]
wire [161:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}]
wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32]
wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32]
wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}]
wire _alignedSigC_T_3 = ~reduced4CExtra; // @[MulAddRecFN.scala:130:11, :134:47]
wire _alignedSigC_T_4 = _alignedSigC_T_2 & _alignedSigC_T_3; // @[MulAddRecFN.scala:134:{39,44,47}]
wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}]
wire _alignedSigC_T_7 = _alignedSigC_T_6 | reduced4CExtra; // @[MulAddRecFN.scala:130:11, :135:{39,44}]
wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44]
wire [162:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16]
assign io_mulAddA_0 = rawA_sig[52:0]; // @[rawFloatFromRecFN.scala:55:23]
assign io_mulAddB_0 = rawB_sig[52:0]; // @[rawFloatFromRecFN.scala:55:23]
assign _io_mulAddC_T = alignedSigC[106:1]; // @[MulAddRecFN.scala:132:12, :143:30]
assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30]
wire _io_toPostMul_isSigNaNAny_T = rawA_sig[51]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_3 = rawB_sig[51]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_4 = ~_io_toPostMul_isSigNaNAny_T_3; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_5 = rawB_isNaN & _io_toPostMul_isSigNaNAny_T_4; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2 | _io_toPostMul_isSigNaNAny_T_5; // @[common.scala:82:46]
wire _io_toPostMul_isSigNaNAny_T_7 = rawC_sig[51]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_8 = ~_io_toPostMul_isSigNaNAny_T_7; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_9 = rawC_isNaN & _io_toPostMul_isSigNaNAny_T_8; // @[rawFloatFromRecFN.scala:55:23]
assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6 | _io_toPostMul_isSigNaNAny_T_9; // @[common.scala:82:46]
assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58]
assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN | rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42]
wire [14:0] _io_toPostMul_sExpSum_T = _GEN - 15'h35; // @[MulAddRecFN.scala:106:42, :158:53]
wire [13:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[13:0]; // @[MulAddRecFN.scala:158:53]
wire [13:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53]
wire [13:0] _io_toPostMul_sExpSum_T_3 = CIsDominant ? {rawC_sExp[12], rawC_sExp} : _io_toPostMul_sExpSum_T_2; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[12:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12]
assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[5:0]; // @[MulAddRecFN.scala:112:12, :161:47]
assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47]
assign _io_toPostMul_highAlignedSigC_T = alignedSigC[161:107]; // @[MulAddRecFN.scala:132:12, :163:20]
assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20]
assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48]
assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48]
assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
assign io_mulAddB = io_mulAddB_0; // @[MulAddRecFN.scala:71:7]
assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfB = io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroB = io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNC = io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfC = io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroC = io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CIsDominant = io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_110 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_127
connect io_out_source_extend.clock, clock
connect io_out_source_extend.reset, reset
connect io_out_source_extend.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_extend.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_110( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_127 io_out_source_extend ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Repeater_TLBundleA_a32d64s7k1z3u :
input clock : Clock
input reset : Reset
output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}}
regreset full : UInt<1>, clock, reset, UInt<1>(0h0)
reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, clock
node _io_deq_valid_T = or(io.enq.valid, full)
connect io.deq.valid, _io_deq_valid_T
node _io_enq_ready_T = eq(full, UInt<1>(0h0))
node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T)
connect io.enq.ready, _io_enq_ready_T_1
node _io_deq_bits_T = mux(full, saved, io.enq.bits)
connect io.deq.bits, _io_deq_bits_T
connect io.full, full
node _T = and(io.enq.ready, io.enq.valid)
node _T_1 = and(_T, io.repeat)
when _T_1 :
connect full, UInt<1>(0h1)
connect saved, io.enq.bits
node _T_2 = and(io.deq.ready, io.deq.valid)
node _T_3 = eq(io.repeat, UInt<1>(0h0))
node _T_4 = and(_T_2, _T_3)
when _T_4 :
connect full, UInt<1>(0h0) | module Repeater_TLBundleA_a32d64s7k1z3u( // @[Repeater.scala:10:7]
input clock, // @[Repeater.scala:10:7]
input reset, // @[Repeater.scala:10:7]
input io_repeat, // @[Repeater.scala:13:14]
output io_enq_ready, // @[Repeater.scala:13:14]
input io_enq_valid, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_size, // @[Repeater.scala:13:14]
input [6:0] io_enq_bits_source, // @[Repeater.scala:13:14]
input [31:0] io_enq_bits_address, // @[Repeater.scala:13:14]
input [7:0] io_enq_bits_mask, // @[Repeater.scala:13:14]
input [63:0] io_enq_bits_data, // @[Repeater.scala:13:14]
input io_enq_bits_corrupt, // @[Repeater.scala:13:14]
input io_deq_ready, // @[Repeater.scala:13:14]
output io_deq_valid, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_size, // @[Repeater.scala:13:14]
output [6:0] io_deq_bits_source, // @[Repeater.scala:13:14]
output [31:0] io_deq_bits_address, // @[Repeater.scala:13:14]
output [7:0] io_deq_bits_mask, // @[Repeater.scala:13:14]
output [63:0] io_deq_bits_data, // @[Repeater.scala:13:14]
output io_deq_bits_corrupt // @[Repeater.scala:13:14]
);
wire io_repeat_0 = io_repeat; // @[Repeater.scala:10:7]
wire io_enq_valid_0 = io_enq_valid; // @[Repeater.scala:10:7]
wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[Repeater.scala:10:7]
wire [2:0] io_enq_bits_param_0 = io_enq_bits_param; // @[Repeater.scala:10:7]
wire [2:0] io_enq_bits_size_0 = io_enq_bits_size; // @[Repeater.scala:10:7]
wire [6:0] io_enq_bits_source_0 = io_enq_bits_source; // @[Repeater.scala:10:7]
wire [31:0] io_enq_bits_address_0 = io_enq_bits_address; // @[Repeater.scala:10:7]
wire [7:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[Repeater.scala:10:7]
wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[Repeater.scala:10:7]
wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[Repeater.scala:10:7]
wire io_deq_ready_0 = io_deq_ready; // @[Repeater.scala:10:7]
wire _io_enq_ready_T_1; // @[Repeater.scala:25:32]
wire _io_deq_valid_T; // @[Repeater.scala:24:32]
wire [2:0] _io_deq_bits_T_opcode; // @[Repeater.scala:26:21]
wire [2:0] _io_deq_bits_T_param; // @[Repeater.scala:26:21]
wire [2:0] _io_deq_bits_T_size; // @[Repeater.scala:26:21]
wire [6:0] _io_deq_bits_T_source; // @[Repeater.scala:26:21]
wire [31:0] _io_deq_bits_T_address; // @[Repeater.scala:26:21]
wire [7:0] _io_deq_bits_T_mask; // @[Repeater.scala:26:21]
wire [63:0] _io_deq_bits_T_data; // @[Repeater.scala:26:21]
wire _io_deq_bits_T_corrupt; // @[Repeater.scala:26:21]
wire io_enq_ready_0; // @[Repeater.scala:10:7]
wire [2:0] io_deq_bits_opcode_0; // @[Repeater.scala:10:7]
wire [2:0] io_deq_bits_param_0; // @[Repeater.scala:10:7]
wire [2:0] io_deq_bits_size_0; // @[Repeater.scala:10:7]
wire [6:0] io_deq_bits_source_0; // @[Repeater.scala:10:7]
wire [31:0] io_deq_bits_address_0; // @[Repeater.scala:10:7]
wire [7:0] io_deq_bits_mask_0; // @[Repeater.scala:10:7]
wire [63:0] io_deq_bits_data_0; // @[Repeater.scala:10:7]
wire io_deq_bits_corrupt_0; // @[Repeater.scala:10:7]
wire io_deq_valid_0; // @[Repeater.scala:10:7]
wire io_full; // @[Repeater.scala:10:7]
reg full; // @[Repeater.scala:20:21]
assign io_full = full; // @[Repeater.scala:10:7, :20:21]
reg [2:0] saved_opcode; // @[Repeater.scala:21:18]
reg [2:0] saved_param; // @[Repeater.scala:21:18]
reg [2:0] saved_size; // @[Repeater.scala:21:18]
reg [6:0] saved_source; // @[Repeater.scala:21:18]
reg [31:0] saved_address; // @[Repeater.scala:21:18]
reg [7:0] saved_mask; // @[Repeater.scala:21:18]
reg [63:0] saved_data; // @[Repeater.scala:21:18]
reg saved_corrupt; // @[Repeater.scala:21:18]
assign _io_deq_valid_T = io_enq_valid_0 | full; // @[Repeater.scala:10:7, :20:21, :24:32]
assign io_deq_valid_0 = _io_deq_valid_T; // @[Repeater.scala:10:7, :24:32]
wire _io_enq_ready_T = ~full; // @[Repeater.scala:20:21, :25:35]
assign _io_enq_ready_T_1 = io_deq_ready_0 & _io_enq_ready_T; // @[Repeater.scala:10:7, :25:{32,35}]
assign io_enq_ready_0 = _io_enq_ready_T_1; // @[Repeater.scala:10:7, :25:32]
assign _io_deq_bits_T_opcode = full ? saved_opcode : io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_param = full ? saved_param : io_enq_bits_param_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_size = full ? saved_size : io_enq_bits_size_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_source = full ? saved_source : io_enq_bits_source_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_address = full ? saved_address : io_enq_bits_address_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_mask = full ? saved_mask : io_enq_bits_mask_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_data = full ? saved_data : io_enq_bits_data_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_corrupt = full ? saved_corrupt : io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign io_deq_bits_opcode_0 = _io_deq_bits_T_opcode; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_param_0 = _io_deq_bits_T_param; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_size_0 = _io_deq_bits_T_size; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_source_0 = _io_deq_bits_T_source; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_address_0 = _io_deq_bits_T_address; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_mask_0 = _io_deq_bits_T_mask; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_data_0 = _io_deq_bits_T_data; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_corrupt_0 = _io_deq_bits_T_corrupt; // @[Repeater.scala:10:7, :26:21]
wire _T_1 = io_enq_ready_0 & io_enq_valid_0 & io_repeat_0; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[Repeater.scala:10:7]
if (reset) // @[Repeater.scala:10:7]
full <= 1'h0; // @[Repeater.scala:20:21]
else // @[Repeater.scala:10:7]
full <= ~(io_deq_ready_0 & io_deq_valid_0 & ~io_repeat_0) & (_T_1 | full); // @[Decoupled.scala:51:35]
if (_T_1) begin // @[Decoupled.scala:51:35]
saved_opcode <= io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :21:18]
saved_param <= io_enq_bits_param_0; // @[Repeater.scala:10:7, :21:18]
saved_size <= io_enq_bits_size_0; // @[Repeater.scala:10:7, :21:18]
saved_source <= io_enq_bits_source_0; // @[Repeater.scala:10:7, :21:18]
saved_address <= io_enq_bits_address_0; // @[Repeater.scala:10:7, :21:18]
saved_mask <= io_enq_bits_mask_0; // @[Repeater.scala:10:7, :21:18]
saved_data <= io_enq_bits_data_0; // @[Repeater.scala:10:7, :21:18]
saved_corrupt <= io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :21:18]
end
always @(posedge)
assign io_enq_ready = io_enq_ready_0; // @[Repeater.scala:10:7]
assign io_deq_valid = io_deq_valid_0; // @[Repeater.scala:10:7]
assign io_deq_bits_opcode = io_deq_bits_opcode_0; // @[Repeater.scala:10:7]
assign io_deq_bits_param = io_deq_bits_param_0; // @[Repeater.scala:10:7]
assign io_deq_bits_size = io_deq_bits_size_0; // @[Repeater.scala:10:7]
assign io_deq_bits_source = io_deq_bits_source_0; // @[Repeater.scala:10:7]
assign io_deq_bits_address = io_deq_bits_address_0; // @[Repeater.scala:10:7]
assign io_deq_bits_mask = io_deq_bits_mask_0; // @[Repeater.scala:10:7]
assign io_deq_bits_data = io_deq_bits_data_0; // @[Repeater.scala:10:7]
assign io_deq_bits_corrupt = io_deq_bits_corrupt_0; // @[Repeater.scala:10:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Tile_109 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>}
inst tile_0_0 of PE_365
connect tile_0_0.clock, clock
connect tile_0_0.reset, reset
connect tile_0_0.io.in_a, io.in_a[0]
connect tile_0_0.io.in_b, io.in_b[0]
connect tile_0_0.io.in_d, io.in_d[0]
connect tile_0_0.io.in_control.shift, io.in_control[0].shift
connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate
connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow
connect tile_0_0.io.in_valid, io.in_valid[0]
connect tile_0_0.io.in_id, io.in_id[0]
connect tile_0_0.io.in_last, io.in_last[0]
connect io.out_c[0], tile_0_0.io.out_c
connect io.out_control[0], tile_0_0.io.out_control
connect io.out_id[0], tile_0_0.io.out_id
connect io.out_last[0], tile_0_0.io.out_last
connect io.out_valid[0], tile_0_0.io.out_valid
connect io.out_b[0], tile_0_0.io.out_b
connect io.bad_dataflow, tile_0_0.io.bad_dataflow
connect io.out_a[0], tile_0_0.io.out_a | module Tile_109( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0, // @[Tile.scala:17:14]
output io_bad_dataflow // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
wire io_bad_dataflow_0; // @[Tile.scala:16:7]
PE_365 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0),
.io_bad_dataflow (io_bad_dataflow_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Repeater_TLBundleA_a28d64s7k1z3u :
input clock : Clock
input reset : Reset
output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}}
regreset full : UInt<1>, clock, reset, UInt<1>(0h0)
reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, clock
node _io_deq_valid_T = or(io.enq.valid, full)
connect io.deq.valid, _io_deq_valid_T
node _io_enq_ready_T = eq(full, UInt<1>(0h0))
node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T)
connect io.enq.ready, _io_enq_ready_T_1
node _io_deq_bits_T = mux(full, saved, io.enq.bits)
connect io.deq.bits, _io_deq_bits_T
connect io.full, full
node _T = and(io.enq.ready, io.enq.valid)
node _T_1 = and(_T, io.repeat)
when _T_1 :
connect full, UInt<1>(0h1)
connect saved, io.enq.bits
node _T_2 = and(io.deq.ready, io.deq.valid)
node _T_3 = eq(io.repeat, UInt<1>(0h0))
node _T_4 = and(_T_2, _T_3)
when _T_4 :
connect full, UInt<1>(0h0) | module Repeater_TLBundleA_a28d64s7k1z3u( // @[Repeater.scala:10:7]
input clock, // @[Repeater.scala:10:7]
input reset, // @[Repeater.scala:10:7]
input io_repeat, // @[Repeater.scala:13:14]
output io_full, // @[Repeater.scala:13:14]
output io_enq_ready, // @[Repeater.scala:13:14]
input io_enq_valid, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_size, // @[Repeater.scala:13:14]
input [6:0] io_enq_bits_source, // @[Repeater.scala:13:14]
input [27:0] io_enq_bits_address, // @[Repeater.scala:13:14]
input [7:0] io_enq_bits_mask, // @[Repeater.scala:13:14]
input io_enq_bits_corrupt, // @[Repeater.scala:13:14]
input io_deq_ready, // @[Repeater.scala:13:14]
output io_deq_valid, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_size, // @[Repeater.scala:13:14]
output [6:0] io_deq_bits_source, // @[Repeater.scala:13:14]
output [27:0] io_deq_bits_address, // @[Repeater.scala:13:14]
output [7:0] io_deq_bits_mask, // @[Repeater.scala:13:14]
output io_deq_bits_corrupt // @[Repeater.scala:13:14]
);
reg full; // @[Repeater.scala:20:21]
reg [2:0] saved_opcode; // @[Repeater.scala:21:18]
reg [2:0] saved_param; // @[Repeater.scala:21:18]
reg [2:0] saved_size; // @[Repeater.scala:21:18]
reg [6:0] saved_source; // @[Repeater.scala:21:18]
reg [27:0] saved_address; // @[Repeater.scala:21:18]
reg [7:0] saved_mask; // @[Repeater.scala:21:18]
reg saved_corrupt; // @[Repeater.scala:21:18]
wire io_deq_valid_0 = io_enq_valid | full; // @[Repeater.scala:20:21, :24:32]
wire io_enq_ready_0 = io_deq_ready & ~full; // @[Repeater.scala:20:21, :25:{32,35}]
wire _GEN = io_enq_ready_0 & io_enq_valid & io_repeat; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[Repeater.scala:10:7]
if (reset) // @[Repeater.scala:10:7]
full <= 1'h0; // @[Repeater.scala:20:21]
else // @[Repeater.scala:10:7]
full <= ~(io_deq_ready & io_deq_valid_0 & ~io_repeat) & (_GEN | full); // @[Decoupled.scala:51:35]
if (_GEN) begin // @[Decoupled.scala:51:35]
saved_opcode <= io_enq_bits_opcode; // @[Repeater.scala:21:18]
saved_param <= io_enq_bits_param; // @[Repeater.scala:21:18]
saved_size <= io_enq_bits_size; // @[Repeater.scala:21:18]
saved_source <= io_enq_bits_source; // @[Repeater.scala:21:18]
saved_address <= io_enq_bits_address; // @[Repeater.scala:21:18]
saved_mask <= io_enq_bits_mask; // @[Repeater.scala:21:18]
saved_corrupt <= io_enq_bits_corrupt; // @[Repeater.scala:21:18]
end
always @(posedge) |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_16 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<6>(0h20))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 2, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 3)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<2>(0h2))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<3>(0h7))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 2, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 3)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<2>(0h3))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<3>(0h7))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<1>(0h0))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<1>(0h1))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_25 = shr(io.in.a.bits.source, 2)
node _source_ok_T_26 = eq(_source_ok_T_25, UInt<2>(0h2))
node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27)
node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29)
node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_31 = shr(io.in.a.bits.source, 2)
node _source_ok_T_32 = eq(_source_ok_T_31, UInt<2>(0h3))
node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33)
node _source_ok_T_35 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35)
wire _source_ok_WIRE : UInt<1>[7]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_30
connect _source_ok_WIRE[6], _source_ok_T_36
node _source_ok_T_37 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[2])
node _source_ok_T_39 = or(_source_ok_T_38, _source_ok_WIRE[3])
node _source_ok_T_40 = or(_source_ok_T_39, _source_ok_WIRE[4])
node _source_ok_T_41 = or(_source_ok_T_40, _source_ok_WIRE[5])
node source_ok = or(_source_ok_T_41, _source_ok_WIRE[6])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits = bits(_uncommonBits_T, 2, 0)
node _T_12 = shr(io.in.a.bits.source, 3)
node _T_13 = eq(_T_12, UInt<2>(0h2))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<3>(0h7))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 2, 0)
node _T_25 = shr(io.in.a.bits.source, 3)
node _T_26 = eq(_T_25, UInt<2>(0h3))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<3>(0h7))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<1>(0h0))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<1>(0h1))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_64 = shr(io.in.a.bits.source, 2)
node _T_65 = eq(_T_64, UInt<2>(0h2))
node _T_66 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_67 = and(_T_65, _T_66)
node _T_68 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_69 = and(_T_67, _T_68)
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_72 = cvt(_T_71)
node _T_73 = and(_T_72, asSInt(UInt<1>(0h0)))
node _T_74 = asSInt(_T_73)
node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0)))
node _T_76 = or(_T_70, _T_75)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_77 = shr(io.in.a.bits.source, 2)
node _T_78 = eq(_T_77, UInt<2>(0h3))
node _T_79 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_80 = and(_T_78, _T_79)
node _T_81 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_82 = and(_T_80, _T_81)
node _T_83 = eq(_T_82, UInt<1>(0h0))
node _T_84 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_85 = cvt(_T_84)
node _T_86 = and(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = asSInt(_T_86)
node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0)))
node _T_89 = or(_T_83, _T_88)
node _T_90 = and(_T_11, _T_24)
node _T_91 = and(_T_90, _T_37)
node _T_92 = and(_T_91, _T_50)
node _T_93 = and(_T_92, _T_63)
node _T_94 = and(_T_93, _T_76)
node _T_95 = and(_T_94, _T_89)
node _T_96 = asUInt(reset)
node _T_97 = eq(_T_96, UInt<1>(0h0))
when _T_97 :
node _T_98 = eq(_T_95, UInt<1>(0h0))
when _T_98 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_95, UInt<1>(0h1), "") : assert_1
node _T_99 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_99 :
node _T_100 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_101 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_102 = and(_T_100, _T_101)
node _T_103 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 2, 0)
node _T_104 = shr(io.in.a.bits.source, 3)
node _T_105 = eq(_T_104, UInt<2>(0h2))
node _T_106 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_107 = and(_T_105, _T_106)
node _T_108 = leq(uncommonBits_6, UInt<3>(0h7))
node _T_109 = and(_T_107, _T_108)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 2, 0)
node _T_110 = shr(io.in.a.bits.source, 3)
node _T_111 = eq(_T_110, UInt<2>(0h3))
node _T_112 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_113 = and(_T_111, _T_112)
node _T_114 = leq(uncommonBits_7, UInt<3>(0h7))
node _T_115 = and(_T_113, _T_114)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_116 = shr(io.in.a.bits.source, 2)
node _T_117 = eq(_T_116, UInt<1>(0h0))
node _T_118 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_119 = and(_T_117, _T_118)
node _T_120 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_121 = and(_T_119, _T_120)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_122 = shr(io.in.a.bits.source, 2)
node _T_123 = eq(_T_122, UInt<1>(0h1))
node _T_124 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_125 = and(_T_123, _T_124)
node _T_126 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_127 = and(_T_125, _T_126)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_128 = shr(io.in.a.bits.source, 2)
node _T_129 = eq(_T_128, UInt<2>(0h2))
node _T_130 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_131 = and(_T_129, _T_130)
node _T_132 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_133 = and(_T_131, _T_132)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_134 = shr(io.in.a.bits.source, 2)
node _T_135 = eq(_T_134, UInt<2>(0h3))
node _T_136 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_137 = and(_T_135, _T_136)
node _T_138 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_139 = and(_T_137, _T_138)
node _T_140 = or(_T_103, _T_109)
node _T_141 = or(_T_140, _T_115)
node _T_142 = or(_T_141, _T_121)
node _T_143 = or(_T_142, _T_127)
node _T_144 = or(_T_143, _T_133)
node _T_145 = or(_T_144, _T_139)
node _T_146 = and(_T_102, _T_145)
node _T_147 = or(UInt<1>(0h0), _T_146)
node _T_148 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_149 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_150 = cvt(_T_149)
node _T_151 = and(_T_150, asSInt(UInt<14>(0h2000)))
node _T_152 = asSInt(_T_151)
node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0)))
node _T_154 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_155 = cvt(_T_154)
node _T_156 = and(_T_155, asSInt(UInt<13>(0h1000)))
node _T_157 = asSInt(_T_156)
node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0)))
node _T_159 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_160 = cvt(_T_159)
node _T_161 = and(_T_160, asSInt(UInt<17>(0h10000)))
node _T_162 = asSInt(_T_161)
node _T_163 = eq(_T_162, asSInt(UInt<1>(0h0)))
node _T_164 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_165 = cvt(_T_164)
node _T_166 = and(_T_165, asSInt(UInt<18>(0h2f000)))
node _T_167 = asSInt(_T_166)
node _T_168 = eq(_T_167, asSInt(UInt<1>(0h0)))
node _T_169 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_170 = cvt(_T_169)
node _T_171 = and(_T_170, asSInt(UInt<17>(0h10000)))
node _T_172 = asSInt(_T_171)
node _T_173 = eq(_T_172, asSInt(UInt<1>(0h0)))
node _T_174 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_175 = cvt(_T_174)
node _T_176 = and(_T_175, asSInt(UInt<27>(0h4000000)))
node _T_177 = asSInt(_T_176)
node _T_178 = eq(_T_177, asSInt(UInt<1>(0h0)))
node _T_179 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_180 = cvt(_T_179)
node _T_181 = and(_T_180, asSInt(UInt<13>(0h1000)))
node _T_182 = asSInt(_T_181)
node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0)))
node _T_184 = xor(io.in.a.bits.address, UInt<31>(0h60000000))
node _T_185 = cvt(_T_184)
node _T_186 = and(_T_185, asSInt(UInt<30>(0h20000000)))
node _T_187 = asSInt(_T_186)
node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0)))
node _T_189 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_190 = cvt(_T_189)
node _T_191 = and(_T_190, asSInt(UInt<15>(0h4000)))
node _T_192 = asSInt(_T_191)
node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0)))
node _T_194 = or(_T_153, _T_158)
node _T_195 = or(_T_194, _T_163)
node _T_196 = or(_T_195, _T_168)
node _T_197 = or(_T_196, _T_173)
node _T_198 = or(_T_197, _T_178)
node _T_199 = or(_T_198, _T_183)
node _T_200 = or(_T_199, _T_188)
node _T_201 = or(_T_200, _T_193)
node _T_202 = and(_T_148, _T_201)
node _T_203 = or(UInt<1>(0h0), _T_202)
node _T_204 = and(_T_147, _T_203)
node _T_205 = asUInt(reset)
node _T_206 = eq(_T_205, UInt<1>(0h0))
when _T_206 :
node _T_207 = eq(_T_204, UInt<1>(0h0))
when _T_207 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_204, UInt<1>(0h1), "") : assert_2
node _T_208 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_209 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_210 = and(_T_208, _T_209)
node _T_211 = or(UInt<1>(0h0), _T_210)
node _T_212 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_213 = cvt(_T_212)
node _T_214 = and(_T_213, asSInt(UInt<14>(0h2000)))
node _T_215 = asSInt(_T_214)
node _T_216 = eq(_T_215, asSInt(UInt<1>(0h0)))
node _T_217 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_218 = cvt(_T_217)
node _T_219 = and(_T_218, asSInt(UInt<13>(0h1000)))
node _T_220 = asSInt(_T_219)
node _T_221 = eq(_T_220, asSInt(UInt<1>(0h0)))
node _T_222 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_223 = cvt(_T_222)
node _T_224 = and(_T_223, asSInt(UInt<17>(0h10000)))
node _T_225 = asSInt(_T_224)
node _T_226 = eq(_T_225, asSInt(UInt<1>(0h0)))
node _T_227 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_228 = cvt(_T_227)
node _T_229 = and(_T_228, asSInt(UInt<18>(0h2f000)))
node _T_230 = asSInt(_T_229)
node _T_231 = eq(_T_230, asSInt(UInt<1>(0h0)))
node _T_232 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_233 = cvt(_T_232)
node _T_234 = and(_T_233, asSInt(UInt<17>(0h10000)))
node _T_235 = asSInt(_T_234)
node _T_236 = eq(_T_235, asSInt(UInt<1>(0h0)))
node _T_237 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_238 = cvt(_T_237)
node _T_239 = and(_T_238, asSInt(UInt<27>(0h4000000)))
node _T_240 = asSInt(_T_239)
node _T_241 = eq(_T_240, asSInt(UInt<1>(0h0)))
node _T_242 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_243 = cvt(_T_242)
node _T_244 = and(_T_243, asSInt(UInt<13>(0h1000)))
node _T_245 = asSInt(_T_244)
node _T_246 = eq(_T_245, asSInt(UInt<1>(0h0)))
node _T_247 = xor(io.in.a.bits.address, UInt<31>(0h60000000))
node _T_248 = cvt(_T_247)
node _T_249 = and(_T_248, asSInt(UInt<30>(0h20000000)))
node _T_250 = asSInt(_T_249)
node _T_251 = eq(_T_250, asSInt(UInt<1>(0h0)))
node _T_252 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_253 = cvt(_T_252)
node _T_254 = and(_T_253, asSInt(UInt<15>(0h4000)))
node _T_255 = asSInt(_T_254)
node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0)))
node _T_257 = or(_T_216, _T_221)
node _T_258 = or(_T_257, _T_226)
node _T_259 = or(_T_258, _T_231)
node _T_260 = or(_T_259, _T_236)
node _T_261 = or(_T_260, _T_241)
node _T_262 = or(_T_261, _T_246)
node _T_263 = or(_T_262, _T_251)
node _T_264 = or(_T_263, _T_256)
node _T_265 = and(_T_211, _T_264)
node _T_266 = or(UInt<1>(0h0), _T_265)
node _T_267 = and(UInt<1>(0h0), _T_266)
node _T_268 = asUInt(reset)
node _T_269 = eq(_T_268, UInt<1>(0h0))
when _T_269 :
node _T_270 = eq(_T_267, UInt<1>(0h0))
when _T_270 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_267, UInt<1>(0h1), "") : assert_3
node _T_271 = asUInt(reset)
node _T_272 = eq(_T_271, UInt<1>(0h0))
when _T_272 :
node _T_273 = eq(source_ok, UInt<1>(0h0))
when _T_273 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_274 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_275 = asUInt(reset)
node _T_276 = eq(_T_275, UInt<1>(0h0))
when _T_276 :
node _T_277 = eq(_T_274, UInt<1>(0h0))
when _T_277 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_274, UInt<1>(0h1), "") : assert_5
node _T_278 = asUInt(reset)
node _T_279 = eq(_T_278, UInt<1>(0h0))
when _T_279 :
node _T_280 = eq(is_aligned, UInt<1>(0h0))
when _T_280 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_281 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_282 = asUInt(reset)
node _T_283 = eq(_T_282, UInt<1>(0h0))
when _T_283 :
node _T_284 = eq(_T_281, UInt<1>(0h0))
when _T_284 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_281, UInt<1>(0h1), "") : assert_7
node _T_285 = not(io.in.a.bits.mask)
node _T_286 = eq(_T_285, UInt<1>(0h0))
node _T_287 = asUInt(reset)
node _T_288 = eq(_T_287, UInt<1>(0h0))
when _T_288 :
node _T_289 = eq(_T_286, UInt<1>(0h0))
when _T_289 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_286, UInt<1>(0h1), "") : assert_8
node _T_290 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_291 = asUInt(reset)
node _T_292 = eq(_T_291, UInt<1>(0h0))
when _T_292 :
node _T_293 = eq(_T_290, UInt<1>(0h0))
when _T_293 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_290, UInt<1>(0h1), "") : assert_9
node _T_294 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_294 :
node _T_295 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_296 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_297 = and(_T_295, _T_296)
node _T_298 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 2, 0)
node _T_299 = shr(io.in.a.bits.source, 3)
node _T_300 = eq(_T_299, UInt<2>(0h2))
node _T_301 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_302 = and(_T_300, _T_301)
node _T_303 = leq(uncommonBits_12, UInt<3>(0h7))
node _T_304 = and(_T_302, _T_303)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 2, 0)
node _T_305 = shr(io.in.a.bits.source, 3)
node _T_306 = eq(_T_305, UInt<2>(0h3))
node _T_307 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_308 = and(_T_306, _T_307)
node _T_309 = leq(uncommonBits_13, UInt<3>(0h7))
node _T_310 = and(_T_308, _T_309)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_311 = shr(io.in.a.bits.source, 2)
node _T_312 = eq(_T_311, UInt<1>(0h0))
node _T_313 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_314 = and(_T_312, _T_313)
node _T_315 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_316 = and(_T_314, _T_315)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_317 = shr(io.in.a.bits.source, 2)
node _T_318 = eq(_T_317, UInt<1>(0h1))
node _T_319 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_320 = and(_T_318, _T_319)
node _T_321 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_322 = and(_T_320, _T_321)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_323 = shr(io.in.a.bits.source, 2)
node _T_324 = eq(_T_323, UInt<2>(0h2))
node _T_325 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_326 = and(_T_324, _T_325)
node _T_327 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_328 = and(_T_326, _T_327)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_329 = shr(io.in.a.bits.source, 2)
node _T_330 = eq(_T_329, UInt<2>(0h3))
node _T_331 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_332 = and(_T_330, _T_331)
node _T_333 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_334 = and(_T_332, _T_333)
node _T_335 = or(_T_298, _T_304)
node _T_336 = or(_T_335, _T_310)
node _T_337 = or(_T_336, _T_316)
node _T_338 = or(_T_337, _T_322)
node _T_339 = or(_T_338, _T_328)
node _T_340 = or(_T_339, _T_334)
node _T_341 = and(_T_297, _T_340)
node _T_342 = or(UInt<1>(0h0), _T_341)
node _T_343 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_344 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_345 = cvt(_T_344)
node _T_346 = and(_T_345, asSInt(UInt<14>(0h2000)))
node _T_347 = asSInt(_T_346)
node _T_348 = eq(_T_347, asSInt(UInt<1>(0h0)))
node _T_349 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_350 = cvt(_T_349)
node _T_351 = and(_T_350, asSInt(UInt<13>(0h1000)))
node _T_352 = asSInt(_T_351)
node _T_353 = eq(_T_352, asSInt(UInt<1>(0h0)))
node _T_354 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_355 = cvt(_T_354)
node _T_356 = and(_T_355, asSInt(UInt<17>(0h10000)))
node _T_357 = asSInt(_T_356)
node _T_358 = eq(_T_357, asSInt(UInt<1>(0h0)))
node _T_359 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_360 = cvt(_T_359)
node _T_361 = and(_T_360, asSInt(UInt<18>(0h2f000)))
node _T_362 = asSInt(_T_361)
node _T_363 = eq(_T_362, asSInt(UInt<1>(0h0)))
node _T_364 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_365 = cvt(_T_364)
node _T_366 = and(_T_365, asSInt(UInt<17>(0h10000)))
node _T_367 = asSInt(_T_366)
node _T_368 = eq(_T_367, asSInt(UInt<1>(0h0)))
node _T_369 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_370 = cvt(_T_369)
node _T_371 = and(_T_370, asSInt(UInt<27>(0h4000000)))
node _T_372 = asSInt(_T_371)
node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0)))
node _T_374 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_375 = cvt(_T_374)
node _T_376 = and(_T_375, asSInt(UInt<13>(0h1000)))
node _T_377 = asSInt(_T_376)
node _T_378 = eq(_T_377, asSInt(UInt<1>(0h0)))
node _T_379 = xor(io.in.a.bits.address, UInt<31>(0h60000000))
node _T_380 = cvt(_T_379)
node _T_381 = and(_T_380, asSInt(UInt<30>(0h20000000)))
node _T_382 = asSInt(_T_381)
node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0)))
node _T_384 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_385 = cvt(_T_384)
node _T_386 = and(_T_385, asSInt(UInt<15>(0h4000)))
node _T_387 = asSInt(_T_386)
node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0)))
node _T_389 = or(_T_348, _T_353)
node _T_390 = or(_T_389, _T_358)
node _T_391 = or(_T_390, _T_363)
node _T_392 = or(_T_391, _T_368)
node _T_393 = or(_T_392, _T_373)
node _T_394 = or(_T_393, _T_378)
node _T_395 = or(_T_394, _T_383)
node _T_396 = or(_T_395, _T_388)
node _T_397 = and(_T_343, _T_396)
node _T_398 = or(UInt<1>(0h0), _T_397)
node _T_399 = and(_T_342, _T_398)
node _T_400 = asUInt(reset)
node _T_401 = eq(_T_400, UInt<1>(0h0))
when _T_401 :
node _T_402 = eq(_T_399, UInt<1>(0h0))
when _T_402 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_399, UInt<1>(0h1), "") : assert_10
node _T_403 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_404 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_405 = and(_T_403, _T_404)
node _T_406 = or(UInt<1>(0h0), _T_405)
node _T_407 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_408 = cvt(_T_407)
node _T_409 = and(_T_408, asSInt(UInt<14>(0h2000)))
node _T_410 = asSInt(_T_409)
node _T_411 = eq(_T_410, asSInt(UInt<1>(0h0)))
node _T_412 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_413 = cvt(_T_412)
node _T_414 = and(_T_413, asSInt(UInt<13>(0h1000)))
node _T_415 = asSInt(_T_414)
node _T_416 = eq(_T_415, asSInt(UInt<1>(0h0)))
node _T_417 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_418 = cvt(_T_417)
node _T_419 = and(_T_418, asSInt(UInt<17>(0h10000)))
node _T_420 = asSInt(_T_419)
node _T_421 = eq(_T_420, asSInt(UInt<1>(0h0)))
node _T_422 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_423 = cvt(_T_422)
node _T_424 = and(_T_423, asSInt(UInt<18>(0h2f000)))
node _T_425 = asSInt(_T_424)
node _T_426 = eq(_T_425, asSInt(UInt<1>(0h0)))
node _T_427 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_428 = cvt(_T_427)
node _T_429 = and(_T_428, asSInt(UInt<17>(0h10000)))
node _T_430 = asSInt(_T_429)
node _T_431 = eq(_T_430, asSInt(UInt<1>(0h0)))
node _T_432 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_433 = cvt(_T_432)
node _T_434 = and(_T_433, asSInt(UInt<27>(0h4000000)))
node _T_435 = asSInt(_T_434)
node _T_436 = eq(_T_435, asSInt(UInt<1>(0h0)))
node _T_437 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_438 = cvt(_T_437)
node _T_439 = and(_T_438, asSInt(UInt<13>(0h1000)))
node _T_440 = asSInt(_T_439)
node _T_441 = eq(_T_440, asSInt(UInt<1>(0h0)))
node _T_442 = xor(io.in.a.bits.address, UInt<31>(0h60000000))
node _T_443 = cvt(_T_442)
node _T_444 = and(_T_443, asSInt(UInt<30>(0h20000000)))
node _T_445 = asSInt(_T_444)
node _T_446 = eq(_T_445, asSInt(UInt<1>(0h0)))
node _T_447 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_448 = cvt(_T_447)
node _T_449 = and(_T_448, asSInt(UInt<15>(0h4000)))
node _T_450 = asSInt(_T_449)
node _T_451 = eq(_T_450, asSInt(UInt<1>(0h0)))
node _T_452 = or(_T_411, _T_416)
node _T_453 = or(_T_452, _T_421)
node _T_454 = or(_T_453, _T_426)
node _T_455 = or(_T_454, _T_431)
node _T_456 = or(_T_455, _T_436)
node _T_457 = or(_T_456, _T_441)
node _T_458 = or(_T_457, _T_446)
node _T_459 = or(_T_458, _T_451)
node _T_460 = and(_T_406, _T_459)
node _T_461 = or(UInt<1>(0h0), _T_460)
node _T_462 = and(UInt<1>(0h0), _T_461)
node _T_463 = asUInt(reset)
node _T_464 = eq(_T_463, UInt<1>(0h0))
when _T_464 :
node _T_465 = eq(_T_462, UInt<1>(0h0))
when _T_465 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_462, UInt<1>(0h1), "") : assert_11
node _T_466 = asUInt(reset)
node _T_467 = eq(_T_466, UInt<1>(0h0))
when _T_467 :
node _T_468 = eq(source_ok, UInt<1>(0h0))
when _T_468 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_469 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_469, UInt<1>(0h1), "") : assert_13
node _T_473 = asUInt(reset)
node _T_474 = eq(_T_473, UInt<1>(0h0))
when _T_474 :
node _T_475 = eq(is_aligned, UInt<1>(0h0))
when _T_475 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_476 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_477 = asUInt(reset)
node _T_478 = eq(_T_477, UInt<1>(0h0))
when _T_478 :
node _T_479 = eq(_T_476, UInt<1>(0h0))
when _T_479 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_476, UInt<1>(0h1), "") : assert_15
node _T_480 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_481 = asUInt(reset)
node _T_482 = eq(_T_481, UInt<1>(0h0))
when _T_482 :
node _T_483 = eq(_T_480, UInt<1>(0h0))
when _T_483 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_480, UInt<1>(0h1), "") : assert_16
node _T_484 = not(io.in.a.bits.mask)
node _T_485 = eq(_T_484, UInt<1>(0h0))
node _T_486 = asUInt(reset)
node _T_487 = eq(_T_486, UInt<1>(0h0))
when _T_487 :
node _T_488 = eq(_T_485, UInt<1>(0h0))
when _T_488 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_485, UInt<1>(0h1), "") : assert_17
node _T_489 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_490 = asUInt(reset)
node _T_491 = eq(_T_490, UInt<1>(0h0))
when _T_491 :
node _T_492 = eq(_T_489, UInt<1>(0h0))
when _T_492 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_489, UInt<1>(0h1), "") : assert_18
node _T_493 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_493 :
node _T_494 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_495 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_496 = and(_T_494, _T_495)
node _T_497 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 2, 0)
node _T_498 = shr(io.in.a.bits.source, 3)
node _T_499 = eq(_T_498, UInt<2>(0h2))
node _T_500 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_501 = and(_T_499, _T_500)
node _T_502 = leq(uncommonBits_18, UInt<3>(0h7))
node _T_503 = and(_T_501, _T_502)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0)
node _T_504 = shr(io.in.a.bits.source, 3)
node _T_505 = eq(_T_504, UInt<2>(0h3))
node _T_506 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_507 = and(_T_505, _T_506)
node _T_508 = leq(uncommonBits_19, UInt<3>(0h7))
node _T_509 = and(_T_507, _T_508)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_510 = shr(io.in.a.bits.source, 2)
node _T_511 = eq(_T_510, UInt<1>(0h0))
node _T_512 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_513 = and(_T_511, _T_512)
node _T_514 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_515 = and(_T_513, _T_514)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_516 = shr(io.in.a.bits.source, 2)
node _T_517 = eq(_T_516, UInt<1>(0h1))
node _T_518 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_519 = and(_T_517, _T_518)
node _T_520 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_521 = and(_T_519, _T_520)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_522 = shr(io.in.a.bits.source, 2)
node _T_523 = eq(_T_522, UInt<2>(0h2))
node _T_524 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_525 = and(_T_523, _T_524)
node _T_526 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_527 = and(_T_525, _T_526)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_528 = shr(io.in.a.bits.source, 2)
node _T_529 = eq(_T_528, UInt<2>(0h3))
node _T_530 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_531 = and(_T_529, _T_530)
node _T_532 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_533 = and(_T_531, _T_532)
node _T_534 = or(_T_497, _T_503)
node _T_535 = or(_T_534, _T_509)
node _T_536 = or(_T_535, _T_515)
node _T_537 = or(_T_536, _T_521)
node _T_538 = or(_T_537, _T_527)
node _T_539 = or(_T_538, _T_533)
node _T_540 = and(_T_496, _T_539)
node _T_541 = or(UInt<1>(0h0), _T_540)
node _T_542 = asUInt(reset)
node _T_543 = eq(_T_542, UInt<1>(0h0))
when _T_543 :
node _T_544 = eq(_T_541, UInt<1>(0h0))
when _T_544 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_541, UInt<1>(0h1), "") : assert_19
node _T_545 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_546 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_547 = and(_T_545, _T_546)
node _T_548 = or(UInt<1>(0h0), _T_547)
node _T_549 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_550 = cvt(_T_549)
node _T_551 = and(_T_550, asSInt(UInt<13>(0h1000)))
node _T_552 = asSInt(_T_551)
node _T_553 = eq(_T_552, asSInt(UInt<1>(0h0)))
node _T_554 = and(_T_548, _T_553)
node _T_555 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_556 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_557 = and(_T_555, _T_556)
node _T_558 = or(UInt<1>(0h0), _T_557)
node _T_559 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_560 = cvt(_T_559)
node _T_561 = and(_T_560, asSInt(UInt<14>(0h2000)))
node _T_562 = asSInt(_T_561)
node _T_563 = eq(_T_562, asSInt(UInt<1>(0h0)))
node _T_564 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_565 = cvt(_T_564)
node _T_566 = and(_T_565, asSInt(UInt<17>(0h10000)))
node _T_567 = asSInt(_T_566)
node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0)))
node _T_569 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_570 = cvt(_T_569)
node _T_571 = and(_T_570, asSInt(UInt<18>(0h2f000)))
node _T_572 = asSInt(_T_571)
node _T_573 = eq(_T_572, asSInt(UInt<1>(0h0)))
node _T_574 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_575 = cvt(_T_574)
node _T_576 = and(_T_575, asSInt(UInt<17>(0h10000)))
node _T_577 = asSInt(_T_576)
node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0)))
node _T_579 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_580 = cvt(_T_579)
node _T_581 = and(_T_580, asSInt(UInt<27>(0h4000000)))
node _T_582 = asSInt(_T_581)
node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0)))
node _T_584 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_585 = cvt(_T_584)
node _T_586 = and(_T_585, asSInt(UInt<13>(0h1000)))
node _T_587 = asSInt(_T_586)
node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0)))
node _T_589 = xor(io.in.a.bits.address, UInt<31>(0h60000000))
node _T_590 = cvt(_T_589)
node _T_591 = and(_T_590, asSInt(UInt<30>(0h20000000)))
node _T_592 = asSInt(_T_591)
node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0)))
node _T_594 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_595 = cvt(_T_594)
node _T_596 = and(_T_595, asSInt(UInt<15>(0h4000)))
node _T_597 = asSInt(_T_596)
node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0)))
node _T_599 = or(_T_563, _T_568)
node _T_600 = or(_T_599, _T_573)
node _T_601 = or(_T_600, _T_578)
node _T_602 = or(_T_601, _T_583)
node _T_603 = or(_T_602, _T_588)
node _T_604 = or(_T_603, _T_593)
node _T_605 = or(_T_604, _T_598)
node _T_606 = and(_T_558, _T_605)
node _T_607 = or(UInt<1>(0h0), _T_554)
node _T_608 = or(_T_607, _T_606)
node _T_609 = asUInt(reset)
node _T_610 = eq(_T_609, UInt<1>(0h0))
when _T_610 :
node _T_611 = eq(_T_608, UInt<1>(0h0))
when _T_611 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_608, UInt<1>(0h1), "") : assert_20
node _T_612 = asUInt(reset)
node _T_613 = eq(_T_612, UInt<1>(0h0))
when _T_613 :
node _T_614 = eq(source_ok, UInt<1>(0h0))
when _T_614 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_615 = asUInt(reset)
node _T_616 = eq(_T_615, UInt<1>(0h0))
when _T_616 :
node _T_617 = eq(is_aligned, UInt<1>(0h0))
when _T_617 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_618 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_619 = asUInt(reset)
node _T_620 = eq(_T_619, UInt<1>(0h0))
when _T_620 :
node _T_621 = eq(_T_618, UInt<1>(0h0))
when _T_621 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_618, UInt<1>(0h1), "") : assert_23
node _T_622 = eq(io.in.a.bits.mask, mask)
node _T_623 = asUInt(reset)
node _T_624 = eq(_T_623, UInt<1>(0h0))
when _T_624 :
node _T_625 = eq(_T_622, UInt<1>(0h0))
when _T_625 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_622, UInt<1>(0h1), "") : assert_24
node _T_626 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_626, UInt<1>(0h1), "") : assert_25
node _T_630 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_630 :
node _T_631 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_632 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_633 = and(_T_631, _T_632)
node _T_634 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 2, 0)
node _T_635 = shr(io.in.a.bits.source, 3)
node _T_636 = eq(_T_635, UInt<2>(0h2))
node _T_637 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_638 = and(_T_636, _T_637)
node _T_639 = leq(uncommonBits_24, UInt<3>(0h7))
node _T_640 = and(_T_638, _T_639)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 2, 0)
node _T_641 = shr(io.in.a.bits.source, 3)
node _T_642 = eq(_T_641, UInt<2>(0h3))
node _T_643 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_644 = and(_T_642, _T_643)
node _T_645 = leq(uncommonBits_25, UInt<3>(0h7))
node _T_646 = and(_T_644, _T_645)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_647 = shr(io.in.a.bits.source, 2)
node _T_648 = eq(_T_647, UInt<1>(0h0))
node _T_649 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_650 = and(_T_648, _T_649)
node _T_651 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_652 = and(_T_650, _T_651)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_653 = shr(io.in.a.bits.source, 2)
node _T_654 = eq(_T_653, UInt<1>(0h1))
node _T_655 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_656 = and(_T_654, _T_655)
node _T_657 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_658 = and(_T_656, _T_657)
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_659 = shr(io.in.a.bits.source, 2)
node _T_660 = eq(_T_659, UInt<2>(0h2))
node _T_661 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_662 = and(_T_660, _T_661)
node _T_663 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_664 = and(_T_662, _T_663)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_665 = shr(io.in.a.bits.source, 2)
node _T_666 = eq(_T_665, UInt<2>(0h3))
node _T_667 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_668 = and(_T_666, _T_667)
node _T_669 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_670 = and(_T_668, _T_669)
node _T_671 = or(_T_634, _T_640)
node _T_672 = or(_T_671, _T_646)
node _T_673 = or(_T_672, _T_652)
node _T_674 = or(_T_673, _T_658)
node _T_675 = or(_T_674, _T_664)
node _T_676 = or(_T_675, _T_670)
node _T_677 = and(_T_633, _T_676)
node _T_678 = or(UInt<1>(0h0), _T_677)
node _T_679 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_680 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_681 = and(_T_679, _T_680)
node _T_682 = or(UInt<1>(0h0), _T_681)
node _T_683 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_684 = cvt(_T_683)
node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000)))
node _T_686 = asSInt(_T_685)
node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0)))
node _T_688 = and(_T_682, _T_687)
node _T_689 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_690 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_691 = and(_T_689, _T_690)
node _T_692 = or(UInt<1>(0h0), _T_691)
node _T_693 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_694 = cvt(_T_693)
node _T_695 = and(_T_694, asSInt(UInt<14>(0h2000)))
node _T_696 = asSInt(_T_695)
node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0)))
node _T_698 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_699 = cvt(_T_698)
node _T_700 = and(_T_699, asSInt(UInt<18>(0h2f000)))
node _T_701 = asSInt(_T_700)
node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0)))
node _T_703 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_704 = cvt(_T_703)
node _T_705 = and(_T_704, asSInt(UInt<17>(0h10000)))
node _T_706 = asSInt(_T_705)
node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0)))
node _T_708 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_709 = cvt(_T_708)
node _T_710 = and(_T_709, asSInt(UInt<27>(0h4000000)))
node _T_711 = asSInt(_T_710)
node _T_712 = eq(_T_711, asSInt(UInt<1>(0h0)))
node _T_713 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_714 = cvt(_T_713)
node _T_715 = and(_T_714, asSInt(UInt<13>(0h1000)))
node _T_716 = asSInt(_T_715)
node _T_717 = eq(_T_716, asSInt(UInt<1>(0h0)))
node _T_718 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_719 = cvt(_T_718)
node _T_720 = and(_T_719, asSInt(UInt<15>(0h4000)))
node _T_721 = asSInt(_T_720)
node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0)))
node _T_723 = or(_T_697, _T_702)
node _T_724 = or(_T_723, _T_707)
node _T_725 = or(_T_724, _T_712)
node _T_726 = or(_T_725, _T_717)
node _T_727 = or(_T_726, _T_722)
node _T_728 = and(_T_692, _T_727)
node _T_729 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_730 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_731 = cvt(_T_730)
node _T_732 = and(_T_731, asSInt(UInt<17>(0h10000)))
node _T_733 = asSInt(_T_732)
node _T_734 = eq(_T_733, asSInt(UInt<1>(0h0)))
node _T_735 = and(_T_729, _T_734)
node _T_736 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_737 = leq(io.in.a.bits.size, UInt<4>(0h8))
node _T_738 = and(_T_736, _T_737)
node _T_739 = or(UInt<1>(0h0), _T_738)
node _T_740 = xor(io.in.a.bits.address, UInt<31>(0h60000000))
node _T_741 = cvt(_T_740)
node _T_742 = and(_T_741, asSInt(UInt<30>(0h20000000)))
node _T_743 = asSInt(_T_742)
node _T_744 = eq(_T_743, asSInt(UInt<1>(0h0)))
node _T_745 = and(_T_739, _T_744)
node _T_746 = or(UInt<1>(0h0), _T_688)
node _T_747 = or(_T_746, _T_728)
node _T_748 = or(_T_747, _T_735)
node _T_749 = or(_T_748, _T_745)
node _T_750 = and(_T_678, _T_749)
node _T_751 = asUInt(reset)
node _T_752 = eq(_T_751, UInt<1>(0h0))
when _T_752 :
node _T_753 = eq(_T_750, UInt<1>(0h0))
when _T_753 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_750, UInt<1>(0h1), "") : assert_26
node _T_754 = asUInt(reset)
node _T_755 = eq(_T_754, UInt<1>(0h0))
when _T_755 :
node _T_756 = eq(source_ok, UInt<1>(0h0))
when _T_756 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_757 = asUInt(reset)
node _T_758 = eq(_T_757, UInt<1>(0h0))
when _T_758 :
node _T_759 = eq(is_aligned, UInt<1>(0h0))
when _T_759 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_760 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_761 = asUInt(reset)
node _T_762 = eq(_T_761, UInt<1>(0h0))
when _T_762 :
node _T_763 = eq(_T_760, UInt<1>(0h0))
when _T_763 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_760, UInt<1>(0h1), "") : assert_29
node _T_764 = eq(io.in.a.bits.mask, mask)
node _T_765 = asUInt(reset)
node _T_766 = eq(_T_765, UInt<1>(0h0))
when _T_766 :
node _T_767 = eq(_T_764, UInt<1>(0h0))
when _T_767 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_764, UInt<1>(0h1), "") : assert_30
node _T_768 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_768 :
node _T_769 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_770 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_771 = and(_T_769, _T_770)
node _T_772 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 2, 0)
node _T_773 = shr(io.in.a.bits.source, 3)
node _T_774 = eq(_T_773, UInt<2>(0h2))
node _T_775 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_776 = and(_T_774, _T_775)
node _T_777 = leq(uncommonBits_30, UInt<3>(0h7))
node _T_778 = and(_T_776, _T_777)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 2, 0)
node _T_779 = shr(io.in.a.bits.source, 3)
node _T_780 = eq(_T_779, UInt<2>(0h3))
node _T_781 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_782 = and(_T_780, _T_781)
node _T_783 = leq(uncommonBits_31, UInt<3>(0h7))
node _T_784 = and(_T_782, _T_783)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_785 = shr(io.in.a.bits.source, 2)
node _T_786 = eq(_T_785, UInt<1>(0h0))
node _T_787 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_788 = and(_T_786, _T_787)
node _T_789 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_790 = and(_T_788, _T_789)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_791 = shr(io.in.a.bits.source, 2)
node _T_792 = eq(_T_791, UInt<1>(0h1))
node _T_793 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_794 = and(_T_792, _T_793)
node _T_795 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_796 = and(_T_794, _T_795)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_797 = shr(io.in.a.bits.source, 2)
node _T_798 = eq(_T_797, UInt<2>(0h2))
node _T_799 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_800 = and(_T_798, _T_799)
node _T_801 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_802 = and(_T_800, _T_801)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_803 = shr(io.in.a.bits.source, 2)
node _T_804 = eq(_T_803, UInt<2>(0h3))
node _T_805 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_806 = and(_T_804, _T_805)
node _T_807 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_808 = and(_T_806, _T_807)
node _T_809 = or(_T_772, _T_778)
node _T_810 = or(_T_809, _T_784)
node _T_811 = or(_T_810, _T_790)
node _T_812 = or(_T_811, _T_796)
node _T_813 = or(_T_812, _T_802)
node _T_814 = or(_T_813, _T_808)
node _T_815 = and(_T_771, _T_814)
node _T_816 = or(UInt<1>(0h0), _T_815)
node _T_817 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_818 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_819 = and(_T_817, _T_818)
node _T_820 = or(UInt<1>(0h0), _T_819)
node _T_821 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_822 = cvt(_T_821)
node _T_823 = and(_T_822, asSInt(UInt<13>(0h1000)))
node _T_824 = asSInt(_T_823)
node _T_825 = eq(_T_824, asSInt(UInt<1>(0h0)))
node _T_826 = and(_T_820, _T_825)
node _T_827 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_828 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_829 = and(_T_827, _T_828)
node _T_830 = or(UInt<1>(0h0), _T_829)
node _T_831 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_832 = cvt(_T_831)
node _T_833 = and(_T_832, asSInt(UInt<14>(0h2000)))
node _T_834 = asSInt(_T_833)
node _T_835 = eq(_T_834, asSInt(UInt<1>(0h0)))
node _T_836 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_837 = cvt(_T_836)
node _T_838 = and(_T_837, asSInt(UInt<18>(0h2f000)))
node _T_839 = asSInt(_T_838)
node _T_840 = eq(_T_839, asSInt(UInt<1>(0h0)))
node _T_841 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_842 = cvt(_T_841)
node _T_843 = and(_T_842, asSInt(UInt<17>(0h10000)))
node _T_844 = asSInt(_T_843)
node _T_845 = eq(_T_844, asSInt(UInt<1>(0h0)))
node _T_846 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_847 = cvt(_T_846)
node _T_848 = and(_T_847, asSInt(UInt<27>(0h4000000)))
node _T_849 = asSInt(_T_848)
node _T_850 = eq(_T_849, asSInt(UInt<1>(0h0)))
node _T_851 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_852 = cvt(_T_851)
node _T_853 = and(_T_852, asSInt(UInt<13>(0h1000)))
node _T_854 = asSInt(_T_853)
node _T_855 = eq(_T_854, asSInt(UInt<1>(0h0)))
node _T_856 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_857 = cvt(_T_856)
node _T_858 = and(_T_857, asSInt(UInt<15>(0h4000)))
node _T_859 = asSInt(_T_858)
node _T_860 = eq(_T_859, asSInt(UInt<1>(0h0)))
node _T_861 = or(_T_835, _T_840)
node _T_862 = or(_T_861, _T_845)
node _T_863 = or(_T_862, _T_850)
node _T_864 = or(_T_863, _T_855)
node _T_865 = or(_T_864, _T_860)
node _T_866 = and(_T_830, _T_865)
node _T_867 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_868 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_869 = cvt(_T_868)
node _T_870 = and(_T_869, asSInt(UInt<17>(0h10000)))
node _T_871 = asSInt(_T_870)
node _T_872 = eq(_T_871, asSInt(UInt<1>(0h0)))
node _T_873 = and(_T_867, _T_872)
node _T_874 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_875 = leq(io.in.a.bits.size, UInt<4>(0h8))
node _T_876 = and(_T_874, _T_875)
node _T_877 = or(UInt<1>(0h0), _T_876)
node _T_878 = xor(io.in.a.bits.address, UInt<31>(0h60000000))
node _T_879 = cvt(_T_878)
node _T_880 = and(_T_879, asSInt(UInt<30>(0h20000000)))
node _T_881 = asSInt(_T_880)
node _T_882 = eq(_T_881, asSInt(UInt<1>(0h0)))
node _T_883 = and(_T_877, _T_882)
node _T_884 = or(UInt<1>(0h0), _T_826)
node _T_885 = or(_T_884, _T_866)
node _T_886 = or(_T_885, _T_873)
node _T_887 = or(_T_886, _T_883)
node _T_888 = and(_T_816, _T_887)
node _T_889 = asUInt(reset)
node _T_890 = eq(_T_889, UInt<1>(0h0))
when _T_890 :
node _T_891 = eq(_T_888, UInt<1>(0h0))
when _T_891 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_888, UInt<1>(0h1), "") : assert_31
node _T_892 = asUInt(reset)
node _T_893 = eq(_T_892, UInt<1>(0h0))
when _T_893 :
node _T_894 = eq(source_ok, UInt<1>(0h0))
when _T_894 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_895 = asUInt(reset)
node _T_896 = eq(_T_895, UInt<1>(0h0))
when _T_896 :
node _T_897 = eq(is_aligned, UInt<1>(0h0))
when _T_897 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_898 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_899 = asUInt(reset)
node _T_900 = eq(_T_899, UInt<1>(0h0))
when _T_900 :
node _T_901 = eq(_T_898, UInt<1>(0h0))
when _T_901 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_898, UInt<1>(0h1), "") : assert_34
node _T_902 = not(mask)
node _T_903 = and(io.in.a.bits.mask, _T_902)
node _T_904 = eq(_T_903, UInt<1>(0h0))
node _T_905 = asUInt(reset)
node _T_906 = eq(_T_905, UInt<1>(0h0))
when _T_906 :
node _T_907 = eq(_T_904, UInt<1>(0h0))
when _T_907 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_904, UInt<1>(0h1), "") : assert_35
node _T_908 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_908 :
node _T_909 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_910 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_911 = and(_T_909, _T_910)
node _T_912 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 2, 0)
node _T_913 = shr(io.in.a.bits.source, 3)
node _T_914 = eq(_T_913, UInt<2>(0h2))
node _T_915 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_916 = and(_T_914, _T_915)
node _T_917 = leq(uncommonBits_36, UInt<3>(0h7))
node _T_918 = and(_T_916, _T_917)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 2, 0)
node _T_919 = shr(io.in.a.bits.source, 3)
node _T_920 = eq(_T_919, UInt<2>(0h3))
node _T_921 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_922 = and(_T_920, _T_921)
node _T_923 = leq(uncommonBits_37, UInt<3>(0h7))
node _T_924 = and(_T_922, _T_923)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_925 = shr(io.in.a.bits.source, 2)
node _T_926 = eq(_T_925, UInt<1>(0h0))
node _T_927 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_928 = and(_T_926, _T_927)
node _T_929 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_930 = and(_T_928, _T_929)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_931 = shr(io.in.a.bits.source, 2)
node _T_932 = eq(_T_931, UInt<1>(0h1))
node _T_933 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_934 = and(_T_932, _T_933)
node _T_935 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_936 = and(_T_934, _T_935)
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0)
node _T_937 = shr(io.in.a.bits.source, 2)
node _T_938 = eq(_T_937, UInt<2>(0h2))
node _T_939 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_940 = and(_T_938, _T_939)
node _T_941 = leq(uncommonBits_40, UInt<2>(0h3))
node _T_942 = and(_T_940, _T_941)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0)
node _T_943 = shr(io.in.a.bits.source, 2)
node _T_944 = eq(_T_943, UInt<2>(0h3))
node _T_945 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_946 = and(_T_944, _T_945)
node _T_947 = leq(uncommonBits_41, UInt<2>(0h3))
node _T_948 = and(_T_946, _T_947)
node _T_949 = or(_T_912, _T_918)
node _T_950 = or(_T_949, _T_924)
node _T_951 = or(_T_950, _T_930)
node _T_952 = or(_T_951, _T_936)
node _T_953 = or(_T_952, _T_942)
node _T_954 = or(_T_953, _T_948)
node _T_955 = and(_T_911, _T_954)
node _T_956 = or(UInt<1>(0h0), _T_955)
node _T_957 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_958 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_959 = and(_T_957, _T_958)
node _T_960 = or(UInt<1>(0h0), _T_959)
node _T_961 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_962 = cvt(_T_961)
node _T_963 = and(_T_962, asSInt(UInt<14>(0h2000)))
node _T_964 = asSInt(_T_963)
node _T_965 = eq(_T_964, asSInt(UInt<1>(0h0)))
node _T_966 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_967 = cvt(_T_966)
node _T_968 = and(_T_967, asSInt(UInt<13>(0h1000)))
node _T_969 = asSInt(_T_968)
node _T_970 = eq(_T_969, asSInt(UInt<1>(0h0)))
node _T_971 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_972 = cvt(_T_971)
node _T_973 = and(_T_972, asSInt(UInt<18>(0h2f000)))
node _T_974 = asSInt(_T_973)
node _T_975 = eq(_T_974, asSInt(UInt<1>(0h0)))
node _T_976 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_977 = cvt(_T_976)
node _T_978 = and(_T_977, asSInt(UInt<17>(0h10000)))
node _T_979 = asSInt(_T_978)
node _T_980 = eq(_T_979, asSInt(UInt<1>(0h0)))
node _T_981 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_982 = cvt(_T_981)
node _T_983 = and(_T_982, asSInt(UInt<27>(0h4000000)))
node _T_984 = asSInt(_T_983)
node _T_985 = eq(_T_984, asSInt(UInt<1>(0h0)))
node _T_986 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_987 = cvt(_T_986)
node _T_988 = and(_T_987, asSInt(UInt<13>(0h1000)))
node _T_989 = asSInt(_T_988)
node _T_990 = eq(_T_989, asSInt(UInt<1>(0h0)))
node _T_991 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_992 = cvt(_T_991)
node _T_993 = and(_T_992, asSInt(UInt<15>(0h4000)))
node _T_994 = asSInt(_T_993)
node _T_995 = eq(_T_994, asSInt(UInt<1>(0h0)))
node _T_996 = or(_T_965, _T_970)
node _T_997 = or(_T_996, _T_975)
node _T_998 = or(_T_997, _T_980)
node _T_999 = or(_T_998, _T_985)
node _T_1000 = or(_T_999, _T_990)
node _T_1001 = or(_T_1000, _T_995)
node _T_1002 = and(_T_960, _T_1001)
node _T_1003 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1004 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1005 = cvt(_T_1004)
node _T_1006 = and(_T_1005, asSInt(UInt<17>(0h10000)))
node _T_1007 = asSInt(_T_1006)
node _T_1008 = eq(_T_1007, asSInt(UInt<1>(0h0)))
node _T_1009 = xor(io.in.a.bits.address, UInt<31>(0h60000000))
node _T_1010 = cvt(_T_1009)
node _T_1011 = and(_T_1010, asSInt(UInt<30>(0h20000000)))
node _T_1012 = asSInt(_T_1011)
node _T_1013 = eq(_T_1012, asSInt(UInt<1>(0h0)))
node _T_1014 = or(_T_1008, _T_1013)
node _T_1015 = and(_T_1003, _T_1014)
node _T_1016 = or(UInt<1>(0h0), _T_1002)
node _T_1017 = or(_T_1016, _T_1015)
node _T_1018 = and(_T_956, _T_1017)
node _T_1019 = asUInt(reset)
node _T_1020 = eq(_T_1019, UInt<1>(0h0))
when _T_1020 :
node _T_1021 = eq(_T_1018, UInt<1>(0h0))
when _T_1021 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_1018, UInt<1>(0h1), "") : assert_36
node _T_1022 = asUInt(reset)
node _T_1023 = eq(_T_1022, UInt<1>(0h0))
when _T_1023 :
node _T_1024 = eq(source_ok, UInt<1>(0h0))
when _T_1024 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_1025 = asUInt(reset)
node _T_1026 = eq(_T_1025, UInt<1>(0h0))
when _T_1026 :
node _T_1027 = eq(is_aligned, UInt<1>(0h0))
when _T_1027 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_1028 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_1029 = asUInt(reset)
node _T_1030 = eq(_T_1029, UInt<1>(0h0))
when _T_1030 :
node _T_1031 = eq(_T_1028, UInt<1>(0h0))
when _T_1031 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_1028, UInt<1>(0h1), "") : assert_39
node _T_1032 = eq(io.in.a.bits.mask, mask)
node _T_1033 = asUInt(reset)
node _T_1034 = eq(_T_1033, UInt<1>(0h0))
when _T_1034 :
node _T_1035 = eq(_T_1032, UInt<1>(0h0))
when _T_1035 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_1032, UInt<1>(0h1), "") : assert_40
node _T_1036 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_1036 :
node _T_1037 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1038 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1039 = and(_T_1037, _T_1038)
node _T_1040 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 2, 0)
node _T_1041 = shr(io.in.a.bits.source, 3)
node _T_1042 = eq(_T_1041, UInt<2>(0h2))
node _T_1043 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_1044 = and(_T_1042, _T_1043)
node _T_1045 = leq(uncommonBits_42, UInt<3>(0h7))
node _T_1046 = and(_T_1044, _T_1045)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 2, 0)
node _T_1047 = shr(io.in.a.bits.source, 3)
node _T_1048 = eq(_T_1047, UInt<2>(0h3))
node _T_1049 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_1050 = and(_T_1048, _T_1049)
node _T_1051 = leq(uncommonBits_43, UInt<3>(0h7))
node _T_1052 = and(_T_1050, _T_1051)
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0)
node _T_1053 = shr(io.in.a.bits.source, 2)
node _T_1054 = eq(_T_1053, UInt<1>(0h0))
node _T_1055 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_1056 = and(_T_1054, _T_1055)
node _T_1057 = leq(uncommonBits_44, UInt<2>(0h3))
node _T_1058 = and(_T_1056, _T_1057)
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0)
node _T_1059 = shr(io.in.a.bits.source, 2)
node _T_1060 = eq(_T_1059, UInt<1>(0h1))
node _T_1061 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_1062 = and(_T_1060, _T_1061)
node _T_1063 = leq(uncommonBits_45, UInt<2>(0h3))
node _T_1064 = and(_T_1062, _T_1063)
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0)
node _T_1065 = shr(io.in.a.bits.source, 2)
node _T_1066 = eq(_T_1065, UInt<2>(0h2))
node _T_1067 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_1068 = and(_T_1066, _T_1067)
node _T_1069 = leq(uncommonBits_46, UInt<2>(0h3))
node _T_1070 = and(_T_1068, _T_1069)
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0)
node _T_1071 = shr(io.in.a.bits.source, 2)
node _T_1072 = eq(_T_1071, UInt<2>(0h3))
node _T_1073 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_1074 = and(_T_1072, _T_1073)
node _T_1075 = leq(uncommonBits_47, UInt<2>(0h3))
node _T_1076 = and(_T_1074, _T_1075)
node _T_1077 = or(_T_1040, _T_1046)
node _T_1078 = or(_T_1077, _T_1052)
node _T_1079 = or(_T_1078, _T_1058)
node _T_1080 = or(_T_1079, _T_1064)
node _T_1081 = or(_T_1080, _T_1070)
node _T_1082 = or(_T_1081, _T_1076)
node _T_1083 = and(_T_1039, _T_1082)
node _T_1084 = or(UInt<1>(0h0), _T_1083)
node _T_1085 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1086 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_1087 = and(_T_1085, _T_1086)
node _T_1088 = or(UInt<1>(0h0), _T_1087)
node _T_1089 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1090 = cvt(_T_1089)
node _T_1091 = and(_T_1090, asSInt(UInt<14>(0h2000)))
node _T_1092 = asSInt(_T_1091)
node _T_1093 = eq(_T_1092, asSInt(UInt<1>(0h0)))
node _T_1094 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1095 = cvt(_T_1094)
node _T_1096 = and(_T_1095, asSInt(UInt<13>(0h1000)))
node _T_1097 = asSInt(_T_1096)
node _T_1098 = eq(_T_1097, asSInt(UInt<1>(0h0)))
node _T_1099 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1100 = cvt(_T_1099)
node _T_1101 = and(_T_1100, asSInt(UInt<18>(0h2f000)))
node _T_1102 = asSInt(_T_1101)
node _T_1103 = eq(_T_1102, asSInt(UInt<1>(0h0)))
node _T_1104 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1105 = cvt(_T_1104)
node _T_1106 = and(_T_1105, asSInt(UInt<17>(0h10000)))
node _T_1107 = asSInt(_T_1106)
node _T_1108 = eq(_T_1107, asSInt(UInt<1>(0h0)))
node _T_1109 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1110 = cvt(_T_1109)
node _T_1111 = and(_T_1110, asSInt(UInt<27>(0h4000000)))
node _T_1112 = asSInt(_T_1111)
node _T_1113 = eq(_T_1112, asSInt(UInt<1>(0h0)))
node _T_1114 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1115 = cvt(_T_1114)
node _T_1116 = and(_T_1115, asSInt(UInt<13>(0h1000)))
node _T_1117 = asSInt(_T_1116)
node _T_1118 = eq(_T_1117, asSInt(UInt<1>(0h0)))
node _T_1119 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_1120 = cvt(_T_1119)
node _T_1121 = and(_T_1120, asSInt(UInt<15>(0h4000)))
node _T_1122 = asSInt(_T_1121)
node _T_1123 = eq(_T_1122, asSInt(UInt<1>(0h0)))
node _T_1124 = or(_T_1093, _T_1098)
node _T_1125 = or(_T_1124, _T_1103)
node _T_1126 = or(_T_1125, _T_1108)
node _T_1127 = or(_T_1126, _T_1113)
node _T_1128 = or(_T_1127, _T_1118)
node _T_1129 = or(_T_1128, _T_1123)
node _T_1130 = and(_T_1088, _T_1129)
node _T_1131 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1132 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1133 = cvt(_T_1132)
node _T_1134 = and(_T_1133, asSInt(UInt<17>(0h10000)))
node _T_1135 = asSInt(_T_1134)
node _T_1136 = eq(_T_1135, asSInt(UInt<1>(0h0)))
node _T_1137 = xor(io.in.a.bits.address, UInt<31>(0h60000000))
node _T_1138 = cvt(_T_1137)
node _T_1139 = and(_T_1138, asSInt(UInt<30>(0h20000000)))
node _T_1140 = asSInt(_T_1139)
node _T_1141 = eq(_T_1140, asSInt(UInt<1>(0h0)))
node _T_1142 = or(_T_1136, _T_1141)
node _T_1143 = and(_T_1131, _T_1142)
node _T_1144 = or(UInt<1>(0h0), _T_1130)
node _T_1145 = or(_T_1144, _T_1143)
node _T_1146 = and(_T_1084, _T_1145)
node _T_1147 = asUInt(reset)
node _T_1148 = eq(_T_1147, UInt<1>(0h0))
when _T_1148 :
node _T_1149 = eq(_T_1146, UInt<1>(0h0))
when _T_1149 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_1146, UInt<1>(0h1), "") : assert_41
node _T_1150 = asUInt(reset)
node _T_1151 = eq(_T_1150, UInt<1>(0h0))
when _T_1151 :
node _T_1152 = eq(source_ok, UInt<1>(0h0))
when _T_1152 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_1153 = asUInt(reset)
node _T_1154 = eq(_T_1153, UInt<1>(0h0))
when _T_1154 :
node _T_1155 = eq(is_aligned, UInt<1>(0h0))
when _T_1155 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_1156 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_1157 = asUInt(reset)
node _T_1158 = eq(_T_1157, UInt<1>(0h0))
when _T_1158 :
node _T_1159 = eq(_T_1156, UInt<1>(0h0))
when _T_1159 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_1156, UInt<1>(0h1), "") : assert_44
node _T_1160 = eq(io.in.a.bits.mask, mask)
node _T_1161 = asUInt(reset)
node _T_1162 = eq(_T_1161, UInt<1>(0h0))
when _T_1162 :
node _T_1163 = eq(_T_1160, UInt<1>(0h0))
when _T_1163 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_1160, UInt<1>(0h1), "") : assert_45
node _T_1164 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_1164 :
node _T_1165 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1166 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1167 = and(_T_1165, _T_1166)
node _T_1168 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 2, 0)
node _T_1169 = shr(io.in.a.bits.source, 3)
node _T_1170 = eq(_T_1169, UInt<2>(0h2))
node _T_1171 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_1172 = and(_T_1170, _T_1171)
node _T_1173 = leq(uncommonBits_48, UInt<3>(0h7))
node _T_1174 = and(_T_1172, _T_1173)
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 2, 0)
node _T_1175 = shr(io.in.a.bits.source, 3)
node _T_1176 = eq(_T_1175, UInt<2>(0h3))
node _T_1177 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_1178 = and(_T_1176, _T_1177)
node _T_1179 = leq(uncommonBits_49, UInt<3>(0h7))
node _T_1180 = and(_T_1178, _T_1179)
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_1181 = shr(io.in.a.bits.source, 2)
node _T_1182 = eq(_T_1181, UInt<1>(0h0))
node _T_1183 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_1184 = and(_T_1182, _T_1183)
node _T_1185 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_1186 = and(_T_1184, _T_1185)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_1187 = shr(io.in.a.bits.source, 2)
node _T_1188 = eq(_T_1187, UInt<1>(0h1))
node _T_1189 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_1190 = and(_T_1188, _T_1189)
node _T_1191 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_1192 = and(_T_1190, _T_1191)
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0)
node _T_1193 = shr(io.in.a.bits.source, 2)
node _T_1194 = eq(_T_1193, UInt<2>(0h2))
node _T_1195 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_1196 = and(_T_1194, _T_1195)
node _T_1197 = leq(uncommonBits_52, UInt<2>(0h3))
node _T_1198 = and(_T_1196, _T_1197)
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0)
node _T_1199 = shr(io.in.a.bits.source, 2)
node _T_1200 = eq(_T_1199, UInt<2>(0h3))
node _T_1201 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_1202 = and(_T_1200, _T_1201)
node _T_1203 = leq(uncommonBits_53, UInt<2>(0h3))
node _T_1204 = and(_T_1202, _T_1203)
node _T_1205 = or(_T_1168, _T_1174)
node _T_1206 = or(_T_1205, _T_1180)
node _T_1207 = or(_T_1206, _T_1186)
node _T_1208 = or(_T_1207, _T_1192)
node _T_1209 = or(_T_1208, _T_1198)
node _T_1210 = or(_T_1209, _T_1204)
node _T_1211 = and(_T_1167, _T_1210)
node _T_1212 = or(UInt<1>(0h0), _T_1211)
node _T_1213 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1214 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1215 = and(_T_1213, _T_1214)
node _T_1216 = or(UInt<1>(0h0), _T_1215)
node _T_1217 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1218 = cvt(_T_1217)
node _T_1219 = and(_T_1218, asSInt(UInt<13>(0h1000)))
node _T_1220 = asSInt(_T_1219)
node _T_1221 = eq(_T_1220, asSInt(UInt<1>(0h0)))
node _T_1222 = and(_T_1216, _T_1221)
node _T_1223 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1224 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1225 = cvt(_T_1224)
node _T_1226 = and(_T_1225, asSInt(UInt<14>(0h2000)))
node _T_1227 = asSInt(_T_1226)
node _T_1228 = eq(_T_1227, asSInt(UInt<1>(0h0)))
node _T_1229 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1230 = cvt(_T_1229)
node _T_1231 = and(_T_1230, asSInt(UInt<17>(0h10000)))
node _T_1232 = asSInt(_T_1231)
node _T_1233 = eq(_T_1232, asSInt(UInt<1>(0h0)))
node _T_1234 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1235 = cvt(_T_1234)
node _T_1236 = and(_T_1235, asSInt(UInt<18>(0h2f000)))
node _T_1237 = asSInt(_T_1236)
node _T_1238 = eq(_T_1237, asSInt(UInt<1>(0h0)))
node _T_1239 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1240 = cvt(_T_1239)
node _T_1241 = and(_T_1240, asSInt(UInt<17>(0h10000)))
node _T_1242 = asSInt(_T_1241)
node _T_1243 = eq(_T_1242, asSInt(UInt<1>(0h0)))
node _T_1244 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1245 = cvt(_T_1244)
node _T_1246 = and(_T_1245, asSInt(UInt<27>(0h4000000)))
node _T_1247 = asSInt(_T_1246)
node _T_1248 = eq(_T_1247, asSInt(UInt<1>(0h0)))
node _T_1249 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1250 = cvt(_T_1249)
node _T_1251 = and(_T_1250, asSInt(UInt<13>(0h1000)))
node _T_1252 = asSInt(_T_1251)
node _T_1253 = eq(_T_1252, asSInt(UInt<1>(0h0)))
node _T_1254 = xor(io.in.a.bits.address, UInt<31>(0h60000000))
node _T_1255 = cvt(_T_1254)
node _T_1256 = and(_T_1255, asSInt(UInt<30>(0h20000000)))
node _T_1257 = asSInt(_T_1256)
node _T_1258 = eq(_T_1257, asSInt(UInt<1>(0h0)))
node _T_1259 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_1260 = cvt(_T_1259)
node _T_1261 = and(_T_1260, asSInt(UInt<15>(0h4000)))
node _T_1262 = asSInt(_T_1261)
node _T_1263 = eq(_T_1262, asSInt(UInt<1>(0h0)))
node _T_1264 = or(_T_1228, _T_1233)
node _T_1265 = or(_T_1264, _T_1238)
node _T_1266 = or(_T_1265, _T_1243)
node _T_1267 = or(_T_1266, _T_1248)
node _T_1268 = or(_T_1267, _T_1253)
node _T_1269 = or(_T_1268, _T_1258)
node _T_1270 = or(_T_1269, _T_1263)
node _T_1271 = and(_T_1223, _T_1270)
node _T_1272 = or(UInt<1>(0h0), _T_1222)
node _T_1273 = or(_T_1272, _T_1271)
node _T_1274 = and(_T_1212, _T_1273)
node _T_1275 = asUInt(reset)
node _T_1276 = eq(_T_1275, UInt<1>(0h0))
when _T_1276 :
node _T_1277 = eq(_T_1274, UInt<1>(0h0))
when _T_1277 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1274, UInt<1>(0h1), "") : assert_46
node _T_1278 = asUInt(reset)
node _T_1279 = eq(_T_1278, UInt<1>(0h0))
when _T_1279 :
node _T_1280 = eq(source_ok, UInt<1>(0h0))
when _T_1280 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1281 = asUInt(reset)
node _T_1282 = eq(_T_1281, UInt<1>(0h0))
when _T_1282 :
node _T_1283 = eq(is_aligned, UInt<1>(0h0))
when _T_1283 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1284 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1285 = asUInt(reset)
node _T_1286 = eq(_T_1285, UInt<1>(0h0))
when _T_1286 :
node _T_1287 = eq(_T_1284, UInt<1>(0h0))
when _T_1287 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1284, UInt<1>(0h1), "") : assert_49
node _T_1288 = eq(io.in.a.bits.mask, mask)
node _T_1289 = asUInt(reset)
node _T_1290 = eq(_T_1289, UInt<1>(0h0))
when _T_1290 :
node _T_1291 = eq(_T_1288, UInt<1>(0h0))
when _T_1291 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1288, UInt<1>(0h1), "") : assert_50
node _T_1292 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1293 = asUInt(reset)
node _T_1294 = eq(_T_1293, UInt<1>(0h0))
when _T_1294 :
node _T_1295 = eq(_T_1292, UInt<1>(0h0))
when _T_1295 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1292, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1296 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1297 = asUInt(reset)
node _T_1298 = eq(_T_1297, UInt<1>(0h0))
when _T_1298 :
node _T_1299 = eq(_T_1296, UInt<1>(0h0))
when _T_1299 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1296, UInt<1>(0h1), "") : assert_52
node _source_ok_T_42 = eq(io.in.d.bits.source, UInt<6>(0h20))
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 2, 0)
node _source_ok_T_43 = shr(io.in.d.bits.source, 3)
node _source_ok_T_44 = eq(_source_ok_T_43, UInt<2>(0h2))
node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45)
node _source_ok_T_47 = leq(source_ok_uncommonBits_6, UInt<3>(0h7))
node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 2, 0)
node _source_ok_T_49 = shr(io.in.d.bits.source, 3)
node _source_ok_T_50 = eq(_source_ok_T_49, UInt<2>(0h3))
node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51)
node _source_ok_T_53 = leq(source_ok_uncommonBits_7, UInt<3>(0h7))
node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53)
node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0)
node _source_ok_T_55 = shr(io.in.d.bits.source, 2)
node _source_ok_T_56 = eq(_source_ok_T_55, UInt<1>(0h0))
node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57)
node _source_ok_T_59 = leq(source_ok_uncommonBits_8, UInt<2>(0h3))
node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59)
node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0)
node _source_ok_T_61 = shr(io.in.d.bits.source, 2)
node _source_ok_T_62 = eq(_source_ok_T_61, UInt<1>(0h1))
node _source_ok_T_63 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_64 = and(_source_ok_T_62, _source_ok_T_63)
node _source_ok_T_65 = leq(source_ok_uncommonBits_9, UInt<2>(0h3))
node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65)
node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0)
node _source_ok_T_67 = shr(io.in.d.bits.source, 2)
node _source_ok_T_68 = eq(_source_ok_T_67, UInt<2>(0h2))
node _source_ok_T_69 = leq(UInt<1>(0h0), source_ok_uncommonBits_10)
node _source_ok_T_70 = and(_source_ok_T_68, _source_ok_T_69)
node _source_ok_T_71 = leq(source_ok_uncommonBits_10, UInt<2>(0h3))
node _source_ok_T_72 = and(_source_ok_T_70, _source_ok_T_71)
node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 1, 0)
node _source_ok_T_73 = shr(io.in.d.bits.source, 2)
node _source_ok_T_74 = eq(_source_ok_T_73, UInt<2>(0h3))
node _source_ok_T_75 = leq(UInt<1>(0h0), source_ok_uncommonBits_11)
node _source_ok_T_76 = and(_source_ok_T_74, _source_ok_T_75)
node _source_ok_T_77 = leq(source_ok_uncommonBits_11, UInt<2>(0h3))
node _source_ok_T_78 = and(_source_ok_T_76, _source_ok_T_77)
wire _source_ok_WIRE_1 : UInt<1>[7]
connect _source_ok_WIRE_1[0], _source_ok_T_42
connect _source_ok_WIRE_1[1], _source_ok_T_48
connect _source_ok_WIRE_1[2], _source_ok_T_54
connect _source_ok_WIRE_1[3], _source_ok_T_60
connect _source_ok_WIRE_1[4], _source_ok_T_66
connect _source_ok_WIRE_1[5], _source_ok_T_72
connect _source_ok_WIRE_1[6], _source_ok_T_78
node _source_ok_T_79 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE_1[2])
node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE_1[3])
node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE_1[4])
node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE_1[5])
node source_ok_1 = or(_source_ok_T_83, _source_ok_WIRE_1[6])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1300 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1300 :
node _T_1301 = asUInt(reset)
node _T_1302 = eq(_T_1301, UInt<1>(0h0))
when _T_1302 :
node _T_1303 = eq(source_ok_1, UInt<1>(0h0))
when _T_1303 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1304 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1305 = asUInt(reset)
node _T_1306 = eq(_T_1305, UInt<1>(0h0))
when _T_1306 :
node _T_1307 = eq(_T_1304, UInt<1>(0h0))
when _T_1307 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1304, UInt<1>(0h1), "") : assert_54
node _T_1308 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1309 = asUInt(reset)
node _T_1310 = eq(_T_1309, UInt<1>(0h0))
when _T_1310 :
node _T_1311 = eq(_T_1308, UInt<1>(0h0))
when _T_1311 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1308, UInt<1>(0h1), "") : assert_55
node _T_1312 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1313 = asUInt(reset)
node _T_1314 = eq(_T_1313, UInt<1>(0h0))
when _T_1314 :
node _T_1315 = eq(_T_1312, UInt<1>(0h0))
when _T_1315 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1312, UInt<1>(0h1), "") : assert_56
node _T_1316 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1317 = asUInt(reset)
node _T_1318 = eq(_T_1317, UInt<1>(0h0))
when _T_1318 :
node _T_1319 = eq(_T_1316, UInt<1>(0h0))
when _T_1319 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1316, UInt<1>(0h1), "") : assert_57
node _T_1320 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1320 :
node _T_1321 = asUInt(reset)
node _T_1322 = eq(_T_1321, UInt<1>(0h0))
when _T_1322 :
node _T_1323 = eq(source_ok_1, UInt<1>(0h0))
when _T_1323 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1324 = asUInt(reset)
node _T_1325 = eq(_T_1324, UInt<1>(0h0))
when _T_1325 :
node _T_1326 = eq(sink_ok, UInt<1>(0h0))
when _T_1326 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1327 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1328 = asUInt(reset)
node _T_1329 = eq(_T_1328, UInt<1>(0h0))
when _T_1329 :
node _T_1330 = eq(_T_1327, UInt<1>(0h0))
when _T_1330 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1327, UInt<1>(0h1), "") : assert_60
node _T_1331 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1332 = asUInt(reset)
node _T_1333 = eq(_T_1332, UInt<1>(0h0))
when _T_1333 :
node _T_1334 = eq(_T_1331, UInt<1>(0h0))
when _T_1334 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1331, UInt<1>(0h1), "") : assert_61
node _T_1335 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1336 = asUInt(reset)
node _T_1337 = eq(_T_1336, UInt<1>(0h0))
when _T_1337 :
node _T_1338 = eq(_T_1335, UInt<1>(0h0))
when _T_1338 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1335, UInt<1>(0h1), "") : assert_62
node _T_1339 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1340 = asUInt(reset)
node _T_1341 = eq(_T_1340, UInt<1>(0h0))
when _T_1341 :
node _T_1342 = eq(_T_1339, UInt<1>(0h0))
when _T_1342 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1339, UInt<1>(0h1), "") : assert_63
node _T_1343 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1344 = or(UInt<1>(0h1), _T_1343)
node _T_1345 = asUInt(reset)
node _T_1346 = eq(_T_1345, UInt<1>(0h0))
when _T_1346 :
node _T_1347 = eq(_T_1344, UInt<1>(0h0))
when _T_1347 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1344, UInt<1>(0h1), "") : assert_64
node _T_1348 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1348 :
node _T_1349 = asUInt(reset)
node _T_1350 = eq(_T_1349, UInt<1>(0h0))
when _T_1350 :
node _T_1351 = eq(source_ok_1, UInt<1>(0h0))
when _T_1351 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1352 = asUInt(reset)
node _T_1353 = eq(_T_1352, UInt<1>(0h0))
when _T_1353 :
node _T_1354 = eq(sink_ok, UInt<1>(0h0))
when _T_1354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1355 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1356 = asUInt(reset)
node _T_1357 = eq(_T_1356, UInt<1>(0h0))
when _T_1357 :
node _T_1358 = eq(_T_1355, UInt<1>(0h0))
when _T_1358 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1355, UInt<1>(0h1), "") : assert_67
node _T_1359 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1360 = asUInt(reset)
node _T_1361 = eq(_T_1360, UInt<1>(0h0))
when _T_1361 :
node _T_1362 = eq(_T_1359, UInt<1>(0h0))
when _T_1362 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1359, UInt<1>(0h1), "") : assert_68
node _T_1363 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1364 = asUInt(reset)
node _T_1365 = eq(_T_1364, UInt<1>(0h0))
when _T_1365 :
node _T_1366 = eq(_T_1363, UInt<1>(0h0))
when _T_1366 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1363, UInt<1>(0h1), "") : assert_69
node _T_1367 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1368 = or(_T_1367, io.in.d.bits.corrupt)
node _T_1369 = asUInt(reset)
node _T_1370 = eq(_T_1369, UInt<1>(0h0))
when _T_1370 :
node _T_1371 = eq(_T_1368, UInt<1>(0h0))
when _T_1371 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1368, UInt<1>(0h1), "") : assert_70
node _T_1372 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1373 = or(UInt<1>(0h1), _T_1372)
node _T_1374 = asUInt(reset)
node _T_1375 = eq(_T_1374, UInt<1>(0h0))
when _T_1375 :
node _T_1376 = eq(_T_1373, UInt<1>(0h0))
when _T_1376 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1373, UInt<1>(0h1), "") : assert_71
node _T_1377 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1377 :
node _T_1378 = asUInt(reset)
node _T_1379 = eq(_T_1378, UInt<1>(0h0))
when _T_1379 :
node _T_1380 = eq(source_ok_1, UInt<1>(0h0))
when _T_1380 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1381 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1382 = asUInt(reset)
node _T_1383 = eq(_T_1382, UInt<1>(0h0))
when _T_1383 :
node _T_1384 = eq(_T_1381, UInt<1>(0h0))
when _T_1384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1381, UInt<1>(0h1), "") : assert_73
node _T_1385 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1386 = asUInt(reset)
node _T_1387 = eq(_T_1386, UInt<1>(0h0))
when _T_1387 :
node _T_1388 = eq(_T_1385, UInt<1>(0h0))
when _T_1388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1385, UInt<1>(0h1), "") : assert_74
node _T_1389 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1390 = or(UInt<1>(0h1), _T_1389)
node _T_1391 = asUInt(reset)
node _T_1392 = eq(_T_1391, UInt<1>(0h0))
when _T_1392 :
node _T_1393 = eq(_T_1390, UInt<1>(0h0))
when _T_1393 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1390, UInt<1>(0h1), "") : assert_75
node _T_1394 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1394 :
node _T_1395 = asUInt(reset)
node _T_1396 = eq(_T_1395, UInt<1>(0h0))
when _T_1396 :
node _T_1397 = eq(source_ok_1, UInt<1>(0h0))
when _T_1397 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1398 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1399 = asUInt(reset)
node _T_1400 = eq(_T_1399, UInt<1>(0h0))
when _T_1400 :
node _T_1401 = eq(_T_1398, UInt<1>(0h0))
when _T_1401 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1398, UInt<1>(0h1), "") : assert_77
node _T_1402 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1403 = or(_T_1402, io.in.d.bits.corrupt)
node _T_1404 = asUInt(reset)
node _T_1405 = eq(_T_1404, UInt<1>(0h0))
when _T_1405 :
node _T_1406 = eq(_T_1403, UInt<1>(0h0))
when _T_1406 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1403, UInt<1>(0h1), "") : assert_78
node _T_1407 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1408 = or(UInt<1>(0h1), _T_1407)
node _T_1409 = asUInt(reset)
node _T_1410 = eq(_T_1409, UInt<1>(0h0))
when _T_1410 :
node _T_1411 = eq(_T_1408, UInt<1>(0h0))
when _T_1411 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1408, UInt<1>(0h1), "") : assert_79
node _T_1412 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1412 :
node _T_1413 = asUInt(reset)
node _T_1414 = eq(_T_1413, UInt<1>(0h0))
when _T_1414 :
node _T_1415 = eq(source_ok_1, UInt<1>(0h0))
when _T_1415 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1416 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1417 = asUInt(reset)
node _T_1418 = eq(_T_1417, UInt<1>(0h0))
when _T_1418 :
node _T_1419 = eq(_T_1416, UInt<1>(0h0))
when _T_1419 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1416, UInt<1>(0h1), "") : assert_81
node _T_1420 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1421 = asUInt(reset)
node _T_1422 = eq(_T_1421, UInt<1>(0h0))
when _T_1422 :
node _T_1423 = eq(_T_1420, UInt<1>(0h0))
when _T_1423 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1420, UInt<1>(0h1), "") : assert_82
node _T_1424 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1425 = or(UInt<1>(0h1), _T_1424)
node _T_1426 = asUInt(reset)
node _T_1427 = eq(_T_1426, UInt<1>(0h0))
when _T_1427 :
node _T_1428 = eq(_T_1425, UInt<1>(0h0))
when _T_1428 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1425, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<6>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1429 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_1430 = asUInt(reset)
node _T_1431 = eq(_T_1430, UInt<1>(0h0))
when _T_1431 :
node _T_1432 = eq(_T_1429, UInt<1>(0h0))
when _T_1432 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1429, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<6>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_1433 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_1434 = asUInt(reset)
node _T_1435 = eq(_T_1434, UInt<1>(0h0))
when _T_1435 :
node _T_1436 = eq(_T_1433, UInt<1>(0h0))
when _T_1436 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1433, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1437 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1438 = asUInt(reset)
node _T_1439 = eq(_T_1438, UInt<1>(0h0))
when _T_1439 :
node _T_1440 = eq(_T_1437, UInt<1>(0h0))
when _T_1440 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1437, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1441 = eq(a_first, UInt<1>(0h0))
node _T_1442 = and(io.in.a.valid, _T_1441)
when _T_1442 :
node _T_1443 = eq(io.in.a.bits.opcode, opcode)
node _T_1444 = asUInt(reset)
node _T_1445 = eq(_T_1444, UInt<1>(0h0))
when _T_1445 :
node _T_1446 = eq(_T_1443, UInt<1>(0h0))
when _T_1446 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1443, UInt<1>(0h1), "") : assert_87
node _T_1447 = eq(io.in.a.bits.param, param)
node _T_1448 = asUInt(reset)
node _T_1449 = eq(_T_1448, UInt<1>(0h0))
when _T_1449 :
node _T_1450 = eq(_T_1447, UInt<1>(0h0))
when _T_1450 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1447, UInt<1>(0h1), "") : assert_88
node _T_1451 = eq(io.in.a.bits.size, size)
node _T_1452 = asUInt(reset)
node _T_1453 = eq(_T_1452, UInt<1>(0h0))
when _T_1453 :
node _T_1454 = eq(_T_1451, UInt<1>(0h0))
when _T_1454 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1451, UInt<1>(0h1), "") : assert_89
node _T_1455 = eq(io.in.a.bits.source, source)
node _T_1456 = asUInt(reset)
node _T_1457 = eq(_T_1456, UInt<1>(0h0))
when _T_1457 :
node _T_1458 = eq(_T_1455, UInt<1>(0h0))
when _T_1458 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1455, UInt<1>(0h1), "") : assert_90
node _T_1459 = eq(io.in.a.bits.address, address)
node _T_1460 = asUInt(reset)
node _T_1461 = eq(_T_1460, UInt<1>(0h0))
when _T_1461 :
node _T_1462 = eq(_T_1459, UInt<1>(0h0))
when _T_1462 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1459, UInt<1>(0h1), "") : assert_91
node _T_1463 = and(io.in.a.ready, io.in.a.valid)
node _T_1464 = and(_T_1463, a_first)
when _T_1464 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1465 = eq(d_first, UInt<1>(0h0))
node _T_1466 = and(io.in.d.valid, _T_1465)
when _T_1466 :
node _T_1467 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1468 = asUInt(reset)
node _T_1469 = eq(_T_1468, UInt<1>(0h0))
when _T_1469 :
node _T_1470 = eq(_T_1467, UInt<1>(0h0))
when _T_1470 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1467, UInt<1>(0h1), "") : assert_92
node _T_1471 = eq(io.in.d.bits.param, param_1)
node _T_1472 = asUInt(reset)
node _T_1473 = eq(_T_1472, UInt<1>(0h0))
when _T_1473 :
node _T_1474 = eq(_T_1471, UInt<1>(0h0))
when _T_1474 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1471, UInt<1>(0h1), "") : assert_93
node _T_1475 = eq(io.in.d.bits.size, size_1)
node _T_1476 = asUInt(reset)
node _T_1477 = eq(_T_1476, UInt<1>(0h0))
when _T_1477 :
node _T_1478 = eq(_T_1475, UInt<1>(0h0))
when _T_1478 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1475, UInt<1>(0h1), "") : assert_94
node _T_1479 = eq(io.in.d.bits.source, source_1)
node _T_1480 = asUInt(reset)
node _T_1481 = eq(_T_1480, UInt<1>(0h0))
when _T_1481 :
node _T_1482 = eq(_T_1479, UInt<1>(0h0))
when _T_1482 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1479, UInt<1>(0h1), "") : assert_95
node _T_1483 = eq(io.in.d.bits.sink, sink)
node _T_1484 = asUInt(reset)
node _T_1485 = eq(_T_1484, UInt<1>(0h0))
when _T_1485 :
node _T_1486 = eq(_T_1483, UInt<1>(0h0))
when _T_1486 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1483, UInt<1>(0h1), "") : assert_96
node _T_1487 = eq(io.in.d.bits.denied, denied)
node _T_1488 = asUInt(reset)
node _T_1489 = eq(_T_1488, UInt<1>(0h0))
when _T_1489 :
node _T_1490 = eq(_T_1487, UInt<1>(0h0))
when _T_1490 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1487, UInt<1>(0h1), "") : assert_97
node _T_1491 = and(io.in.d.ready, io.in.d.valid)
node _T_1492 = and(_T_1491, d_first)
when _T_1492 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<33>, clock, reset, UInt<33>(0h0)
regreset inflight_opcodes : UInt<132>, clock, reset, UInt<132>(0h0)
regreset inflight_sizes : UInt<264>, clock, reset, UInt<264>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<33>
connect a_set, UInt<33>(0h0)
wire a_set_wo_ready : UInt<33>
connect a_set_wo_ready, UInt<33>(0h0)
wire a_opcodes_set : UInt<132>
connect a_opcodes_set, UInt<132>(0h0)
wire a_sizes_set : UInt<264>
connect a_sizes_set, UInt<264>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1493 = and(io.in.a.valid, a_first_1)
node _T_1494 = and(_T_1493, UInt<1>(0h1))
when _T_1494 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1495 = and(io.in.a.ready, io.in.a.valid)
node _T_1496 = and(_T_1495, a_first_1)
node _T_1497 = and(_T_1496, UInt<1>(0h1))
when _T_1497 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1498 = dshr(inflight, io.in.a.bits.source)
node _T_1499 = bits(_T_1498, 0, 0)
node _T_1500 = eq(_T_1499, UInt<1>(0h0))
node _T_1501 = asUInt(reset)
node _T_1502 = eq(_T_1501, UInt<1>(0h0))
when _T_1502 :
node _T_1503 = eq(_T_1500, UInt<1>(0h0))
when _T_1503 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1500, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<33>
connect d_clr, UInt<33>(0h0)
wire d_clr_wo_ready : UInt<33>
connect d_clr_wo_ready, UInt<33>(0h0)
wire d_opcodes_clr : UInt<132>
connect d_opcodes_clr, UInt<132>(0h0)
wire d_sizes_clr : UInt<264>
connect d_sizes_clr, UInt<264>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1504 = and(io.in.d.valid, d_first_1)
node _T_1505 = and(_T_1504, UInt<1>(0h1))
node _T_1506 = eq(d_release_ack, UInt<1>(0h0))
node _T_1507 = and(_T_1505, _T_1506)
when _T_1507 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1508 = and(io.in.d.ready, io.in.d.valid)
node _T_1509 = and(_T_1508, d_first_1)
node _T_1510 = and(_T_1509, UInt<1>(0h1))
node _T_1511 = eq(d_release_ack, UInt<1>(0h0))
node _T_1512 = and(_T_1510, _T_1511)
when _T_1512 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1513 = and(io.in.d.valid, d_first_1)
node _T_1514 = and(_T_1513, UInt<1>(0h1))
node _T_1515 = eq(d_release_ack, UInt<1>(0h0))
node _T_1516 = and(_T_1514, _T_1515)
when _T_1516 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1517 = dshr(inflight, io.in.d.bits.source)
node _T_1518 = bits(_T_1517, 0, 0)
node _T_1519 = or(_T_1518, same_cycle_resp)
node _T_1520 = asUInt(reset)
node _T_1521 = eq(_T_1520, UInt<1>(0h0))
when _T_1521 :
node _T_1522 = eq(_T_1519, UInt<1>(0h0))
when _T_1522 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1519, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1523 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1524 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1525 = or(_T_1523, _T_1524)
node _T_1526 = asUInt(reset)
node _T_1527 = eq(_T_1526, UInt<1>(0h0))
when _T_1527 :
node _T_1528 = eq(_T_1525, UInt<1>(0h0))
when _T_1528 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1525, UInt<1>(0h1), "") : assert_100
node _T_1529 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1530 = asUInt(reset)
node _T_1531 = eq(_T_1530, UInt<1>(0h0))
when _T_1531 :
node _T_1532 = eq(_T_1529, UInt<1>(0h0))
when _T_1532 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1529, UInt<1>(0h1), "") : assert_101
else :
node _T_1533 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1534 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1535 = or(_T_1533, _T_1534)
node _T_1536 = asUInt(reset)
node _T_1537 = eq(_T_1536, UInt<1>(0h0))
when _T_1537 :
node _T_1538 = eq(_T_1535, UInt<1>(0h0))
when _T_1538 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1535, UInt<1>(0h1), "") : assert_102
node _T_1539 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1540 = asUInt(reset)
node _T_1541 = eq(_T_1540, UInt<1>(0h0))
when _T_1541 :
node _T_1542 = eq(_T_1539, UInt<1>(0h0))
when _T_1542 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1539, UInt<1>(0h1), "") : assert_103
node _T_1543 = and(io.in.d.valid, d_first_1)
node _T_1544 = and(_T_1543, a_first_1)
node _T_1545 = and(_T_1544, io.in.a.valid)
node _T_1546 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1547 = and(_T_1545, _T_1546)
node _T_1548 = eq(d_release_ack, UInt<1>(0h0))
node _T_1549 = and(_T_1547, _T_1548)
when _T_1549 :
node _T_1550 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1551 = or(_T_1550, io.in.a.ready)
node _T_1552 = asUInt(reset)
node _T_1553 = eq(_T_1552, UInt<1>(0h0))
when _T_1553 :
node _T_1554 = eq(_T_1551, UInt<1>(0h0))
when _T_1554 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1551, UInt<1>(0h1), "") : assert_104
node _T_1555 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1556 = orr(a_set_wo_ready)
node _T_1557 = eq(_T_1556, UInt<1>(0h0))
node _T_1558 = or(_T_1555, _T_1557)
node _T_1559 = asUInt(reset)
node _T_1560 = eq(_T_1559, UInt<1>(0h0))
when _T_1560 :
node _T_1561 = eq(_T_1558, UInt<1>(0h0))
when _T_1561 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1558, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_32
node _T_1562 = orr(inflight)
node _T_1563 = eq(_T_1562, UInt<1>(0h0))
node _T_1564 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1565 = or(_T_1563, _T_1564)
node _T_1566 = lt(watchdog, plusarg_reader.out)
node _T_1567 = or(_T_1565, _T_1566)
node _T_1568 = asUInt(reset)
node _T_1569 = eq(_T_1568, UInt<1>(0h0))
when _T_1569 :
node _T_1570 = eq(_T_1567, UInt<1>(0h0))
when _T_1570 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1567, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1571 = and(io.in.a.ready, io.in.a.valid)
node _T_1572 = and(io.in.d.ready, io.in.d.valid)
node _T_1573 = or(_T_1571, _T_1572)
when _T_1573 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<33>, clock, reset, UInt<33>(0h0)
regreset inflight_opcodes_1 : UInt<132>, clock, reset, UInt<132>(0h0)
regreset inflight_sizes_1 : UInt<264>, clock, reset, UInt<264>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_first_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_first_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_first_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_first_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_first_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_first_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<6>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<6>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<33>
connect c_set, UInt<33>(0h0)
wire c_set_wo_ready : UInt<33>
connect c_set_wo_ready, UInt<33>(0h0)
wire c_opcodes_set : UInt<132>
connect c_opcodes_set, UInt<132>(0h0)
wire c_sizes_set : UInt<264>
connect c_sizes_set, UInt<264>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_6.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_6.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_6.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_6.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_6.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_6.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<6>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1574 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<6>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1575 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1576 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1577 = and(_T_1575, _T_1576)
node _T_1578 = and(_T_1574, _T_1577)
when _T_1578 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<6>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<6>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1579 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1580 = and(_T_1579, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<6>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1581 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1582 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1583 = and(_T_1581, _T_1582)
node _T_1584 = and(_T_1580, _T_1583)
when _T_1584 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<6>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<6>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<6>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<6>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<6>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<6>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1585 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1586 = bits(_T_1585, 0, 0)
node _T_1587 = eq(_T_1586, UInt<1>(0h0))
node _T_1588 = asUInt(reset)
node _T_1589 = eq(_T_1588, UInt<1>(0h0))
when _T_1589 :
node _T_1590 = eq(_T_1587, UInt<1>(0h0))
when _T_1590 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1587, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<6>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<6>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<33>
connect d_clr_1, UInt<33>(0h0)
wire d_clr_wo_ready_1 : UInt<33>
connect d_clr_wo_ready_1, UInt<33>(0h0)
wire d_opcodes_clr_1 : UInt<132>
connect d_opcodes_clr_1, UInt<132>(0h0)
wire d_sizes_clr_1 : UInt<264>
connect d_sizes_clr_1, UInt<264>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1591 = and(io.in.d.valid, d_first_2)
node _T_1592 = and(_T_1591, UInt<1>(0h1))
node _T_1593 = and(_T_1592, d_release_ack_1)
when _T_1593 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1594 = and(io.in.d.ready, io.in.d.valid)
node _T_1595 = and(_T_1594, d_first_2)
node _T_1596 = and(_T_1595, UInt<1>(0h1))
node _T_1597 = and(_T_1596, d_release_ack_1)
when _T_1597 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1598 = and(io.in.d.valid, d_first_2)
node _T_1599 = and(_T_1598, UInt<1>(0h1))
node _T_1600 = and(_T_1599, d_release_ack_1)
when _T_1600 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<6>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<6>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<6>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1601 = dshr(inflight_1, io.in.d.bits.source)
node _T_1602 = bits(_T_1601, 0, 0)
node _T_1603 = or(_T_1602, same_cycle_resp_1)
node _T_1604 = asUInt(reset)
node _T_1605 = eq(_T_1604, UInt<1>(0h0))
when _T_1605 :
node _T_1606 = eq(_T_1603, UInt<1>(0h0))
when _T_1606 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1603, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_16.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_16.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_16.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_16.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_16.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_16.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<6>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1607 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1608 = asUInt(reset)
node _T_1609 = eq(_T_1608, UInt<1>(0h0))
when _T_1609 :
node _T_1610 = eq(_T_1607, UInt<1>(0h0))
when _T_1610 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1607, UInt<1>(0h1), "") : assert_109
else :
node _T_1611 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1612 = asUInt(reset)
node _T_1613 = eq(_T_1612, UInt<1>(0h0))
when _T_1613 :
node _T_1614 = eq(_T_1611, UInt<1>(0h0))
when _T_1614 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1611, UInt<1>(0h1), "") : assert_110
node _T_1615 = and(io.in.d.valid, d_first_2)
node _T_1616 = and(_T_1615, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_18.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_18.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_18.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_18.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_18.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_18.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<6>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1617 = and(_T_1616, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_20.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_20.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_20.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_20.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_20.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_20.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<6>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1618 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1619 = and(_T_1617, _T_1618)
node _T_1620 = and(_T_1619, d_release_ack_1)
node _T_1621 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1622 = and(_T_1620, _T_1621)
when _T_1622 :
node _T_1623 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_22.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_22.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_22.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_22.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_22.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_22.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<6>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1624 = or(_T_1623, _WIRE_23.ready)
node _T_1625 = asUInt(reset)
node _T_1626 = eq(_T_1625, UInt<1>(0h0))
when _T_1626 :
node _T_1627 = eq(_T_1624, UInt<1>(0h0))
when _T_1627 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1624, UInt<1>(0h1), "") : assert_111
node _T_1628 = orr(c_set_wo_ready)
when _T_1628 :
node _T_1629 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1630 = asUInt(reset)
node _T_1631 = eq(_T_1630, UInt<1>(0h0))
when _T_1631 :
node _T_1632 = eq(_T_1629, UInt<1>(0h0))
when _T_1632 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1629, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_33
node _T_1633 = orr(inflight_1)
node _T_1634 = eq(_T_1633, UInt<1>(0h0))
node _T_1635 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1636 = or(_T_1634, _T_1635)
node _T_1637 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1638 = or(_T_1636, _T_1637)
node _T_1639 = asUInt(reset)
node _T_1640 = eq(_T_1639, UInt<1>(0h0))
when _T_1640 :
node _T_1641 = eq(_T_1638, UInt<1>(0h0))
when _T_1641 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1638, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_24.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_24.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_24.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_24.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_24.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_24.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<6>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1642 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1643 = and(io.in.d.ready, io.in.d.valid)
node _T_1644 = or(_T_1642, _T_1643)
when _T_1644 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_16( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input io_in_a_bits_user_amba_prot_bufferable, // @[Monitor.scala:20:14]
input io_in_a_bits_user_amba_prot_modifiable, // @[Monitor.scala:20:14]
input io_in_a_bits_user_amba_prot_readalloc, // @[Monitor.scala:20:14]
input io_in_a_bits_user_amba_prot_writealloc, // @[Monitor.scala:20:14]
input io_in_a_bits_user_amba_prot_privileged, // @[Monitor.scala:20:14]
input io_in_a_bits_user_amba_prot_secure, // @[Monitor.scala:20:14]
input io_in_a_bits_user_amba_prot_fetch, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire io_in_a_bits_user_amba_prot_bufferable_0 = io_in_a_bits_user_amba_prot_bufferable; // @[Monitor.scala:36:7]
wire io_in_a_bits_user_amba_prot_modifiable_0 = io_in_a_bits_user_amba_prot_modifiable; // @[Monitor.scala:36:7]
wire io_in_a_bits_user_amba_prot_readalloc_0 = io_in_a_bits_user_amba_prot_readalloc; // @[Monitor.scala:36:7]
wire io_in_a_bits_user_amba_prot_writealloc_0 = io_in_a_bits_user_amba_prot_writealloc; // @[Monitor.scala:36:7]
wire io_in_a_bits_user_amba_prot_privileged_0 = io_in_a_bits_user_amba_prot_privileged; // @[Monitor.scala:36:7]
wire io_in_a_bits_user_amba_prot_secure_0 = io_in_a_bits_user_amba_prot_secure; // @[Monitor.scala:36:7]
wire io_in_a_bits_user_amba_prot_fetch_0 = io_in_a_bits_user_amba_prot_fetch; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [5:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire [8:0] _c_opcodes_set_T = 9'h0; // @[Monitor.scala:767:79]
wire [8:0] _c_sizes_set_T = 9'h0; // @[Monitor.scala:768:77]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_77 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_first_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_first_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_first_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_first_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_set_wo_ready_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_set_wo_ready_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_opcodes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_opcodes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_sizes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_sizes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_opcodes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_opcodes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_sizes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_sizes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_probe_ack_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_probe_ack_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_probe_ack_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_probe_ack_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _same_cycle_resp_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _same_cycle_resp_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _same_cycle_resp_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _same_cycle_resp_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _same_cycle_resp_WIRE_4_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _same_cycle_resp_WIRE_5_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [515:0] _c_sizes_set_T_1 = 516'h0; // @[Monitor.scala:768:52]
wire [514:0] _c_opcodes_set_T_1 = 515'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [63:0] _c_set_wo_ready_T = 64'h1; // @[OneHot.scala:58:35]
wire [63:0] _c_set_T = 64'h1; // @[OneHot.scala:58:35]
wire [263:0] c_sizes_set = 264'h0; // @[Monitor.scala:741:34]
wire [131:0] c_opcodes_set = 132'h0; // @[Monitor.scala:740:34]
wire [32:0] c_set = 33'h0; // @[Monitor.scala:738:34]
wire [32:0] c_set_wo_ready = 33'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [5:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 6'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_1 = io_in_a_bits_source_0[5:3]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_7 = io_in_a_bits_source_0[5:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 3'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 3'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_13 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_19 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_25 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_31 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_14 = _source_ok_T_13 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_26 = _source_ok_T_25 == 4'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_32 = _source_ok_T_31 == 4'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire _source_ok_T_37 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_39 = _source_ok_T_38 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_40 = _source_ok_T_39 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_41 = _source_ok_T_40 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_41 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [2:0] uncommonBits = _uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_1 = _uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_7 = _uncommonBits_T_7[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_12 = _uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_18 = _uncommonBits_T_18[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_24 = _uncommonBits_T_24[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_25 = _uncommonBits_T_25[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_30 = _uncommonBits_T_30[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_31 = _uncommonBits_T_31[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_36 = _uncommonBits_T_36[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_37 = _uncommonBits_T_37[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_42 = _uncommonBits_T_42[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_43 = _uncommonBits_T_43[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_48 = _uncommonBits_T_48[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_49 = _uncommonBits_T_49[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_42 = io_in_d_bits_source_0 == 6'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_42; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_43 = io_in_d_bits_source_0[5:3]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_49 = io_in_d_bits_source_0[5:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_44 = _source_ok_T_43 == 3'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_48; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_50 = _source_ok_T_49 == 3'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_54; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_55 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_61 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_67 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_73 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_56 = _source_ok_T_55 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_60; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_62 = _source_ok_T_61 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_66; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_68 = _source_ok_T_67 == 4'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_5 = _source_ok_T_72; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_74 = _source_ok_T_73 == 4'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_78 = _source_ok_T_76; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_6 = _source_ok_T_78; // @[Parameters.scala:1138:31]
wire _source_ok_T_79 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_80 = _source_ok_T_79 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_81 = _source_ok_T_80 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_82 = _source_ok_T_81 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_83 = _source_ok_T_82 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_83 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1571 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1571; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1571; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [5:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1644 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1644; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1644; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1644; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [5:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [32:0] inflight; // @[Monitor.scala:614:27]
reg [131:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [263:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [32:0] a_set; // @[Monitor.scala:626:34]
wire [32:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [131:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [263:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [8:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [8:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [8:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [8:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [8:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [131:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [131:0] _a_opcode_lookup_T_6 = {128'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [131:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[131:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [8:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [8:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [8:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [8:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [8:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [263:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [263:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [263:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[263:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [63:0] _GEN_3 = 64'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [63:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [63:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[32:0] : 33'h0; // @[OneHot.scala:58:35]
wire _T_1497 = _T_1571 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1497 ? _a_set_T[32:0] : 33'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1497 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1497 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [8:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [514:0] _a_opcodes_set_T_1 = {511'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1497 ? _a_opcodes_set_T_1[131:0] : 132'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [8:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [515:0] _a_sizes_set_T_1 = {511'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1497 ? _a_sizes_set_T_1[263:0] : 264'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [32:0] d_clr; // @[Monitor.scala:664:34]
wire [32:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [131:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [263:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1543 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [63:0] _GEN_5 = 64'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1543 & ~d_release_ack ? _d_clr_wo_ready_T[32:0] : 33'h0; // @[OneHot.scala:58:35]
wire _T_1512 = _T_1644 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1512 ? _d_clr_T[32:0] : 33'h0; // @[OneHot.scala:58:35]
wire [526:0] _d_opcodes_clr_T_5 = 527'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1512 ? _d_opcodes_clr_T_5[131:0] : 132'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [526:0] _d_sizes_clr_T_5 = 527'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1512 ? _d_sizes_clr_T_5[263:0] : 264'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [32:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [32:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [32:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [131:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [131:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [131:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [263:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [263:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [263:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [32:0] inflight_1; // @[Monitor.scala:726:35]
wire [32:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [131:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [131:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [263:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [263:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [131:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [131:0] _c_opcode_lookup_T_6 = {128'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [131:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[131:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [263:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [263:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [263:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[263:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [32:0] d_clr_1; // @[Monitor.scala:774:34]
wire [32:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [131:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [263:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1615 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1615 & d_release_ack_1 ? _d_clr_wo_ready_T_1[32:0] : 33'h0; // @[OneHot.scala:58:35]
wire _T_1597 = _T_1644 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1597 ? _d_clr_T_1[32:0] : 33'h0; // @[OneHot.scala:58:35]
wire [526:0] _d_opcodes_clr_T_11 = 527'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1597 ? _d_opcodes_clr_T_11[131:0] : 132'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [526:0] _d_sizes_clr_T_11 = 527'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1597 ? _d_sizes_clr_T_11[263:0] : 264'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 6'h0; // @[Monitor.scala:36:7, :795:113]
wire [32:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [32:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [131:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [131:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [263:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [263:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module PE_487 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_231
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<32>, clock
reg c2 : SInt<32>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h1), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node c1_sign = bits(io.in_d, 19, 19)
node c1_lo_lo_hi = cat(c1_sign, c1_sign)
node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign)
node c1_lo_hi_hi = cat(c1_sign, c1_sign)
node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign)
node c1_lo = cat(c1_lo_hi, c1_lo_lo)
node c1_hi_lo_hi = cat(c1_sign, c1_sign)
node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign)
node c1_hi_hi_hi = cat(c1_sign, c1_sign)
node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign)
node c1_hi = cat(c1_hi_hi, c1_hi_lo)
node _c1_T = cat(c1_hi, c1_lo)
node c1_lo_1 = asUInt(io.in_d)
node _c1_T_1 = cat(_c1_T, c1_lo_1)
wire _c1_WIRE : SInt<32>
node _c1_T_2 = asSInt(_c1_T_1)
connect _c1_WIRE, _c1_T_2
connect c1, _c1_WIRE
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node c2_sign = bits(io.in_d, 19, 19)
node c2_lo_lo_hi = cat(c2_sign, c2_sign)
node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign)
node c2_lo_hi_hi = cat(c2_sign, c2_sign)
node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign)
node c2_lo = cat(c2_lo_hi, c2_lo_lo)
node c2_hi_lo_hi = cat(c2_sign, c2_sign)
node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign)
node c2_hi_hi_hi = cat(c2_sign, c2_sign)
node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign)
node c2_hi = cat(c2_hi_hi, c2_hi_lo)
node _c2_T = cat(c2_hi, c2_lo)
node c2_lo_1 = asUInt(io.in_d)
node _c2_T_1 = cat(_c2_T, c2_lo_1)
wire _c2_WIRE : SInt<32>
node _c2_T_2 = asSInt(_c2_T_1)
connect _c2_WIRE, _c2_T_2
connect c2, _c2_WIRE
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h1), _T_4)
node _T_6 = or(UInt<1>(0h0), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_487( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_231 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLSerdesser_SerialRAM :
input clock : Clock
input reset : Reset
output auto : { flip manager_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
output io : { ser : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { flit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { flit : UInt<32>}}}[5], debug : { ser_busy : UInt<1>, des_busy : UInt<1>}}
wire managerNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate managerNodeIn.d.bits.corrupt
invalidate managerNodeIn.d.bits.data
invalidate managerNodeIn.d.bits.denied
invalidate managerNodeIn.d.bits.sink
invalidate managerNodeIn.d.bits.source
invalidate managerNodeIn.d.bits.size
invalidate managerNodeIn.d.bits.param
invalidate managerNodeIn.d.bits.opcode
invalidate managerNodeIn.d.valid
invalidate managerNodeIn.d.ready
invalidate managerNodeIn.a.bits.corrupt
invalidate managerNodeIn.a.bits.data
invalidate managerNodeIn.a.bits.mask
invalidate managerNodeIn.a.bits.address
invalidate managerNodeIn.a.bits.source
invalidate managerNodeIn.a.bits.size
invalidate managerNodeIn.a.bits.param
invalidate managerNodeIn.a.bits.opcode
invalidate managerNodeIn.a.valid
invalidate managerNodeIn.a.ready
inst monitor of TLMonitor_45
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, managerNodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, managerNodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, managerNodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, managerNodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, managerNodeIn.d.bits.source
connect monitor.io.in.d.bits.size, managerNodeIn.d.bits.size
connect monitor.io.in.d.bits.param, managerNodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, managerNodeIn.d.bits.opcode
connect monitor.io.in.d.valid, managerNodeIn.d.valid
connect monitor.io.in.d.ready, managerNodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, managerNodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, managerNodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, managerNodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, managerNodeIn.a.bits.address
connect monitor.io.in.a.bits.source, managerNodeIn.a.bits.source
connect monitor.io.in.a.bits.size, managerNodeIn.a.bits.size
connect monitor.io.in.a.bits.param, managerNodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, managerNodeIn.a.bits.opcode
connect monitor.io.in.a.valid, managerNodeIn.a.valid
connect monitor.io.in.a.ready, managerNodeIn.a.ready
connect managerNodeIn, auto.manager_in
wire client_tl : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<8>, source : UInt<8>, address : UInt<64>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<8>, source : UInt<8>, address : UInt<64>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<8>, source : UInt<8>, address : UInt<64>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<8>, source : UInt<8>, sink : UInt<8>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<8>}}}
connect client_tl.e.bits.sink, UInt<8>(0h0)
connect client_tl.e.valid, UInt<1>(0h0)
connect client_tl.e.ready, UInt<1>(0h0)
connect client_tl.d.bits.corrupt, UInt<1>(0h0)
connect client_tl.d.bits.data, UInt<64>(0h0)
connect client_tl.d.bits.denied, UInt<1>(0h0)
connect client_tl.d.bits.sink, UInt<8>(0h0)
connect client_tl.d.bits.source, UInt<8>(0h0)
connect client_tl.d.bits.size, UInt<8>(0h0)
connect client_tl.d.bits.param, UInt<2>(0h0)
connect client_tl.d.bits.opcode, UInt<3>(0h0)
connect client_tl.d.valid, UInt<1>(0h0)
connect client_tl.d.ready, UInt<1>(0h0)
connect client_tl.c.bits.corrupt, UInt<1>(0h0)
connect client_tl.c.bits.data, UInt<64>(0h0)
connect client_tl.c.bits.address, UInt<64>(0h0)
connect client_tl.c.bits.source, UInt<8>(0h0)
connect client_tl.c.bits.size, UInt<8>(0h0)
connect client_tl.c.bits.param, UInt<3>(0h0)
connect client_tl.c.bits.opcode, UInt<3>(0h0)
connect client_tl.c.valid, UInt<1>(0h0)
connect client_tl.c.ready, UInt<1>(0h0)
connect client_tl.b.bits.corrupt, UInt<1>(0h0)
connect client_tl.b.bits.data, UInt<64>(0h0)
connect client_tl.b.bits.mask, UInt<8>(0h0)
connect client_tl.b.bits.address, UInt<64>(0h0)
connect client_tl.b.bits.source, UInt<8>(0h0)
connect client_tl.b.bits.size, UInt<8>(0h0)
connect client_tl.b.bits.param, UInt<2>(0h0)
connect client_tl.b.bits.opcode, UInt<3>(0h0)
connect client_tl.b.valid, UInt<1>(0h0)
connect client_tl.b.ready, UInt<1>(0h0)
connect client_tl.a.bits.corrupt, UInt<1>(0h0)
connect client_tl.a.bits.data, UInt<64>(0h0)
connect client_tl.a.bits.mask, UInt<8>(0h0)
connect client_tl.a.bits.address, UInt<64>(0h0)
connect client_tl.a.bits.source, UInt<8>(0h0)
connect client_tl.a.bits.size, UInt<8>(0h0)
connect client_tl.a.bits.param, UInt<3>(0h0)
connect client_tl.a.bits.opcode, UInt<3>(0h0)
connect client_tl.a.valid, UInt<1>(0h0)
connect client_tl.a.ready, UInt<1>(0h0)
wire _out_channels_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _out_channels_WIRE.bits.sink, UInt<1>(0h0)
connect _out_channels_WIRE.valid, UInt<1>(0h0)
connect _out_channels_WIRE.ready, UInt<1>(0h0)
wire out_channels_0_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect out_channels_0_1.bits, _out_channels_WIRE.bits
connect out_channels_0_1.valid, _out_channels_WIRE.valid
connect out_channels_0_1.ready, _out_channels_WIRE.ready
inst out_channels_0_2 of TLEToBeat_SerialRAM_a64d64s8k8z8c
connect out_channels_0_2.clock, clock
connect out_channels_0_2.reset, reset
wire _out_channels_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _out_channels_WIRE_1.bits.corrupt, UInt<1>(0h0)
connect _out_channels_WIRE_1.bits.data, UInt<64>(0h0)
connect _out_channels_WIRE_1.bits.address, UInt<32>(0h0)
connect _out_channels_WIRE_1.bits.source, UInt<1>(0h0)
connect _out_channels_WIRE_1.bits.size, UInt<4>(0h0)
connect _out_channels_WIRE_1.bits.param, UInt<3>(0h0)
connect _out_channels_WIRE_1.bits.opcode, UInt<3>(0h0)
connect _out_channels_WIRE_1.valid, UInt<1>(0h0)
connect _out_channels_WIRE_1.ready, UInt<1>(0h0)
wire out_channels_2_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect out_channels_2_1.bits, _out_channels_WIRE_1.bits
connect out_channels_2_1.valid, _out_channels_WIRE_1.valid
connect out_channels_2_1.ready, _out_channels_WIRE_1.ready
inst out_channels_2_2 of TLCToBeat_SerialRAM_a64d64s8k8z8c
connect out_channels_2_2.clock, clock
connect out_channels_2_2.reset, reset
inst out_channels_4_2 of TLAToBeat_SerialRAM_a64d64s8k8z8c
connect out_channels_4_2.clock, clock
connect out_channels_4_2.reset, reset
connect io.ser[0].out.valid, UInt<1>(0h0)
connect io.ser[1].out.valid, UInt<1>(0h0)
connect io.ser[2].out.valid, UInt<1>(0h0)
connect io.ser[3].out.valid, UInt<1>(0h0)
connect io.ser[4].out.valid, UInt<1>(0h0)
invalidate io.ser[0].out.bits.flit
invalidate io.ser[1].out.bits.flit
invalidate io.ser[2].out.bits.flit
invalidate io.ser[3].out.bits.flit
invalidate io.ser[4].out.bits.flit
connect out_channels_0_2.io.protocol, out_channels_0_1
inst ser_0 of GenericSerializer_TLBeatw10_f32
connect ser_0.clock, clock
connect ser_0.reset, reset
connect ser_0.io.in, out_channels_0_2.io.beat
connect io.ser[0].out.bits, ser_0.io.out.bits
connect io.ser[0].out.valid, ser_0.io.out.valid
connect ser_0.io.out.ready, io.ser[0].out.ready
connect out_channels_2_2.io.protocol, out_channels_2_1
inst ser_2 of GenericSerializer_TLBeatw88_f32
connect ser_2.clock, clock
connect ser_2.reset, reset
connect ser_2.io.in, out_channels_2_2.io.beat
connect io.ser[2].out.bits, ser_2.io.out.bits
connect io.ser[2].out.valid, ser_2.io.out.valid
connect ser_2.io.out.ready, io.ser[2].out.ready
connect out_channels_4_2.io.protocol, managerNodeIn.a
inst ser_4 of GenericSerializer_TLBeatw88_f32_1
connect ser_4.clock, clock
connect ser_4.reset, reset
connect ser_4.io.in, out_channels_4_2.io.beat
connect io.ser[4].out.bits, ser_4.io.out.bits
connect io.ser[4].out.valid, ser_4.io.out.valid
connect ser_4.io.out.ready, io.ser[4].out.ready
node _io_debug_ser_busy_T = or(ser_0.io.busy, ser_2.io.busy)
node _io_debug_ser_busy_T_1 = or(_io_debug_ser_busy_T, ser_4.io.busy)
connect io.debug.ser_busy, _io_debug_ser_busy_T_1
inst in_channels_0_2 of TLEFromBeat_SerialRAM_a64d64s8k8z8c
connect in_channels_0_2.clock, clock
connect in_channels_0_2.reset, reset
inst in_channels_1_2 of TLDFromBeat_SerialRAM_a64d64s8k8z8c
connect in_channels_1_2.clock, clock
connect in_channels_1_2.reset, reset
inst in_channels_2_2 of TLCFromBeat_SerialRAM_a64d64s8k8z8c
connect in_channels_2_2.clock, clock
connect in_channels_2_2.reset, reset
wire _in_channels_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _in_channels_WIRE.bits.corrupt, UInt<1>(0h0)
connect _in_channels_WIRE.bits.data, UInt<64>(0h0)
connect _in_channels_WIRE.bits.mask, UInt<8>(0h0)
connect _in_channels_WIRE.bits.address, UInt<32>(0h0)
connect _in_channels_WIRE.bits.source, UInt<1>(0h0)
connect _in_channels_WIRE.bits.size, UInt<4>(0h0)
connect _in_channels_WIRE.bits.param, UInt<2>(0h0)
connect _in_channels_WIRE.bits.opcode, UInt<3>(0h0)
connect _in_channels_WIRE.valid, UInt<1>(0h0)
connect _in_channels_WIRE.ready, UInt<1>(0h0)
wire in_channels_3_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect in_channels_3_1.bits, _in_channels_WIRE.bits
connect in_channels_3_1.valid, _in_channels_WIRE.valid
connect in_channels_3_1.ready, _in_channels_WIRE.ready
inst in_channels_3_2 of TLBFromBeat_SerialRAM_a64d64s8k8z8c
connect in_channels_3_2.clock, clock
connect in_channels_3_2.reset, reset
inst in_channels_4_2 of TLAFromBeat_SerialRAM_a64d64s8k8z8c
connect in_channels_4_2.clock, clock
connect in_channels_4_2.reset, reset
connect client_tl.e.bits.sink, in_channels_0_2.io.protocol.bits.sink
connect client_tl.e.valid, in_channels_0_2.io.protocol.valid
connect in_channels_0_2.io.protocol.ready, client_tl.e.ready
inst des_0 of GenericDeserializer_TLBeatw10_f32_1
connect des_0.clock, clock
connect des_0.reset, reset
connect des_0.io.in, io.ser[0].in
connect in_channels_0_2.io.beat, des_0.io.out
connect managerNodeIn.d.bits, in_channels_1_2.io.protocol.bits
connect managerNodeIn.d.valid, in_channels_1_2.io.protocol.valid
connect in_channels_1_2.io.protocol.ready, managerNodeIn.d.ready
inst des_1 of GenericDeserializer_TLBeatw67_f32_1
connect des_1.clock, clock
connect des_1.reset, reset
connect des_1.io.in, io.ser[1].in
connect in_channels_1_2.io.beat, des_1.io.out
connect client_tl.c.bits.corrupt, in_channels_2_2.io.protocol.bits.corrupt
connect client_tl.c.bits.data, in_channels_2_2.io.protocol.bits.data
connect client_tl.c.bits.address, in_channels_2_2.io.protocol.bits.address
connect client_tl.c.bits.source, in_channels_2_2.io.protocol.bits.source
connect client_tl.c.bits.size, in_channels_2_2.io.protocol.bits.size
connect client_tl.c.bits.param, in_channels_2_2.io.protocol.bits.param
connect client_tl.c.bits.opcode, in_channels_2_2.io.protocol.bits.opcode
connect client_tl.c.valid, in_channels_2_2.io.protocol.valid
connect in_channels_2_2.io.protocol.ready, client_tl.c.ready
inst des_2 of GenericDeserializer_TLBeatw88_f32_2
connect des_2.clock, clock
connect des_2.reset, reset
connect des_2.io.in, io.ser[2].in
connect in_channels_2_2.io.beat, des_2.io.out
connect in_channels_3_1.bits, in_channels_3_2.io.protocol.bits
connect in_channels_3_1.valid, in_channels_3_2.io.protocol.valid
connect in_channels_3_2.io.protocol.ready, in_channels_3_1.ready
inst des_3 of GenericDeserializer_TLBeatw87_f32_1
connect des_3.clock, clock
connect des_3.reset, reset
connect des_3.io.in, io.ser[3].in
connect in_channels_3_2.io.beat, des_3.io.out
connect client_tl.a.bits.corrupt, in_channels_4_2.io.protocol.bits.corrupt
connect client_tl.a.bits.data, in_channels_4_2.io.protocol.bits.data
connect client_tl.a.bits.mask, in_channels_4_2.io.protocol.bits.mask
connect client_tl.a.bits.address, in_channels_4_2.io.protocol.bits.address
connect client_tl.a.bits.source, in_channels_4_2.io.protocol.bits.source
connect client_tl.a.bits.size, in_channels_4_2.io.protocol.bits.size
connect client_tl.a.bits.param, in_channels_4_2.io.protocol.bits.param
connect client_tl.a.bits.opcode, in_channels_4_2.io.protocol.bits.opcode
connect client_tl.a.valid, in_channels_4_2.io.protocol.valid
connect in_channels_4_2.io.protocol.ready, client_tl.a.ready
inst des_4 of GenericDeserializer_TLBeatw88_f32_3
connect des_4.clock, clock
connect des_4.reset, reset
connect des_4.io.in, io.ser[4].in
connect in_channels_4_2.io.beat, des_4.io.out
node _io_debug_des_busy_T = or(des_0.io.busy, des_1.io.busy)
node _io_debug_des_busy_T_1 = or(_io_debug_des_busy_T, des_2.io.busy)
node _io_debug_des_busy_T_2 = or(_io_debug_des_busy_T_1, des_3.io.busy)
node _io_debug_des_busy_T_3 = or(_io_debug_des_busy_T_2, des_4.io.busy)
connect io.debug.des_busy, _io_debug_des_busy_T_3 | module TLSerdesser_SerialRAM( // @[TLSerdes.scala:39:9]
input clock, // @[TLSerdes.scala:39:9]
input reset, // @[TLSerdes.scala:39:9]
output auto_manager_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_manager_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_manager_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_manager_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_manager_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_manager_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_manager_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_manager_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_manager_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_manager_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_manager_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_manager_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_manager_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_manager_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_manager_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_manager_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_manager_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_manager_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_manager_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_manager_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output io_ser_0_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_0_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_0_in_bits_flit, // @[TLSerdes.scala:40:16]
input io_ser_0_out_ready, // @[TLSerdes.scala:40:16]
output [31:0] io_ser_0_out_bits_flit, // @[TLSerdes.scala:40:16]
output io_ser_1_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_1_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_1_in_bits_flit, // @[TLSerdes.scala:40:16]
output io_ser_2_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_2_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_2_in_bits_flit, // @[TLSerdes.scala:40:16]
input io_ser_2_out_ready, // @[TLSerdes.scala:40:16]
output io_ser_2_out_valid, // @[TLSerdes.scala:40:16]
output [31:0] io_ser_2_out_bits_flit, // @[TLSerdes.scala:40:16]
output io_ser_3_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_3_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_3_in_bits_flit, // @[TLSerdes.scala:40:16]
output io_ser_4_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_4_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_4_in_bits_flit, // @[TLSerdes.scala:40:16]
input io_ser_4_out_ready, // @[TLSerdes.scala:40:16]
output io_ser_4_out_valid, // @[TLSerdes.scala:40:16]
output [31:0] io_ser_4_out_bits_flit // @[TLSerdes.scala:40:16]
);
wire _des_4_io_out_valid; // @[TLSerdes.scala:86:23]
wire [85:0] _des_4_io_out_bits_payload; // @[TLSerdes.scala:86:23]
wire _des_4_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_4_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire _des_4_io_busy; // @[TLSerdes.scala:86:23]
wire _des_3_io_out_valid; // @[TLSerdes.scala:86:23]
wire [84:0] _des_3_io_out_bits_payload; // @[TLSerdes.scala:86:23]
wire _des_3_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_3_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire _des_3_io_busy; // @[TLSerdes.scala:86:23]
wire _des_2_io_out_valid; // @[TLSerdes.scala:86:23]
wire [85:0] _des_2_io_out_bits_payload; // @[TLSerdes.scala:86:23]
wire _des_2_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_2_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire _des_2_io_busy; // @[TLSerdes.scala:86:23]
wire _des_1_io_out_valid; // @[TLSerdes.scala:86:23]
wire [64:0] _des_1_io_out_bits_payload; // @[TLSerdes.scala:86:23]
wire _des_1_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_1_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire _des_0_io_out_valid; // @[TLSerdes.scala:86:23]
wire [7:0] _des_0_io_out_bits_payload; // @[TLSerdes.scala:86:23]
wire _des_0_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_0_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire _in_channels_4_2_io_beat_ready; // @[TLSerdes.scala:82:28]
wire [7:0] _in_channels_3_2_io_protocol_bits_size; // @[TLSerdes.scala:81:28]
wire [7:0] _in_channels_3_2_io_protocol_bits_source; // @[TLSerdes.scala:81:28]
wire [63:0] _in_channels_3_2_io_protocol_bits_address; // @[TLSerdes.scala:81:28]
wire _in_channels_3_2_io_beat_ready; // @[TLSerdes.scala:81:28]
wire _in_channels_2_2_io_beat_ready; // @[TLSerdes.scala:80:28]
wire [7:0] _in_channels_1_2_io_protocol_bits_size; // @[TLSerdes.scala:79:28]
wire [7:0] _in_channels_1_2_io_protocol_bits_source; // @[TLSerdes.scala:79:28]
wire [7:0] _in_channels_1_2_io_protocol_bits_sink; // @[TLSerdes.scala:79:28]
wire _in_channels_1_2_io_beat_ready; // @[TLSerdes.scala:79:28]
wire _in_channels_0_2_io_beat_ready; // @[TLSerdes.scala:78:28]
wire _ser_4_io_in_ready; // @[TLSerdes.scala:69:23]
wire _ser_4_io_busy; // @[TLSerdes.scala:69:23]
wire _ser_2_io_in_ready; // @[TLSerdes.scala:69:23]
wire _ser_0_io_in_ready; // @[TLSerdes.scala:69:23]
wire _out_channels_4_2_io_beat_valid; // @[TLSerdes.scala:63:50]
wire [85:0] _out_channels_4_2_io_beat_bits_payload; // @[TLSerdes.scala:63:50]
wire _out_channels_4_2_io_beat_bits_head; // @[TLSerdes.scala:63:50]
wire _out_channels_4_2_io_beat_bits_tail; // @[TLSerdes.scala:63:50]
wire _out_channels_2_2_io_beat_bits_head; // @[TLSerdes.scala:61:50]
wire _out_channels_0_2_io_beat_bits_head; // @[TLSerdes.scala:59:50]
wire auto_manager_in_a_valid_0 = auto_manager_in_a_valid; // @[TLSerdes.scala:39:9]
wire [2:0] auto_manager_in_a_bits_opcode_0 = auto_manager_in_a_bits_opcode; // @[TLSerdes.scala:39:9]
wire [2:0] auto_manager_in_a_bits_param_0 = auto_manager_in_a_bits_param; // @[TLSerdes.scala:39:9]
wire [3:0] auto_manager_in_a_bits_size_0 = auto_manager_in_a_bits_size; // @[TLSerdes.scala:39:9]
wire auto_manager_in_a_bits_source_0 = auto_manager_in_a_bits_source; // @[TLSerdes.scala:39:9]
wire [31:0] auto_manager_in_a_bits_address_0 = auto_manager_in_a_bits_address; // @[TLSerdes.scala:39:9]
wire [7:0] auto_manager_in_a_bits_mask_0 = auto_manager_in_a_bits_mask; // @[TLSerdes.scala:39:9]
wire [63:0] auto_manager_in_a_bits_data_0 = auto_manager_in_a_bits_data; // @[TLSerdes.scala:39:9]
wire auto_manager_in_a_bits_corrupt_0 = auto_manager_in_a_bits_corrupt; // @[TLSerdes.scala:39:9]
wire auto_manager_in_d_ready_0 = auto_manager_in_d_ready; // @[TLSerdes.scala:39:9]
wire io_ser_0_in_valid_0 = io_ser_0_in_valid; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_0_in_bits_flit_0 = io_ser_0_in_bits_flit; // @[TLSerdes.scala:39:9]
wire io_ser_0_out_ready_0 = io_ser_0_out_ready; // @[TLSerdes.scala:39:9]
wire io_ser_1_in_valid_0 = io_ser_1_in_valid; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_1_in_bits_flit_0 = io_ser_1_in_bits_flit; // @[TLSerdes.scala:39:9]
wire io_ser_2_in_valid_0 = io_ser_2_in_valid; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_2_in_bits_flit_0 = io_ser_2_in_bits_flit; // @[TLSerdes.scala:39:9]
wire io_ser_2_out_ready_0 = io_ser_2_out_ready; // @[TLSerdes.scala:39:9]
wire io_ser_3_in_valid_0 = io_ser_3_in_valid; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_3_in_bits_flit_0 = io_ser_3_in_bits_flit; // @[TLSerdes.scala:39:9]
wire io_ser_4_in_valid_0 = io_ser_4_in_valid; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_4_in_bits_flit_0 = io_ser_4_in_bits_flit; // @[TLSerdes.scala:39:9]
wire io_ser_4_out_ready_0 = io_ser_4_out_ready; // @[TLSerdes.scala:39:9]
wire [2:0] client_tl_b_bits_opcode = 3'h0; // @[TLSerdes.scala:45:71]
wire [2:0] client_tl_d_bits_opcode = 3'h0; // @[TLSerdes.scala:45:71]
wire [2:0] _out_channels_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _out_channels_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] out_channels_2_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] out_channels_2_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _in_channels_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [1:0] client_tl_b_bits_param = 2'h0; // @[TLSerdes.scala:45:71]
wire [1:0] client_tl_d_bits_param = 2'h0; // @[TLSerdes.scala:45:71]
wire [1:0] _in_channels_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [3:0] _out_channels_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] out_channels_2_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _in_channels_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [7:0] client_tl_b_bits_size = 8'h0; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_b_bits_source = 8'h0; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_b_bits_mask = 8'h0; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_d_bits_size = 8'h0; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_d_bits_source = 8'h0; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_d_bits_sink = 8'h0; // @[TLSerdes.scala:45:71]
wire [7:0] _in_channels_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [63:0] client_tl_b_bits_address = 64'h0; // @[TLSerdes.scala:45:71]
wire [63:0] client_tl_b_bits_data = 64'h0; // @[TLSerdes.scala:45:71]
wire [63:0] client_tl_d_bits_data = 64'h0; // @[TLSerdes.scala:45:71]
wire [63:0] _out_channels_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] out_channels_2_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _in_channels_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [31:0] io_ser_1_out_bits_flit = 32'h0; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_3_out_bits_flit = 32'h0; // @[TLSerdes.scala:39:9]
wire [31:0] _out_channels_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] out_channels_2_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _in_channels_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire io_ser_1_out_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :59:50, :61:50]
wire io_ser_3_out_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :59:50, :61:50]
wire out_channels_0_1_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :59:50, :61:50]
wire out_channels_2_1_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :59:50, :61:50]
wire io_ser_0_out_valid = 1'h0; // @[TLSerdes.scala:39:9]
wire io_ser_1_out_valid = 1'h0; // @[TLSerdes.scala:39:9]
wire io_ser_3_out_valid = 1'h0; // @[TLSerdes.scala:39:9]
wire managerNodeIn_a_ready; // @[MixedNode.scala:551:17]
wire client_tl_a_ready = 1'h0; // @[TLSerdes.scala:45:71]
wire client_tl_b_ready = 1'h0; // @[TLSerdes.scala:45:71]
wire client_tl_b_valid = 1'h0; // @[TLSerdes.scala:45:71]
wire client_tl_b_bits_corrupt = 1'h0; // @[TLSerdes.scala:45:71]
wire client_tl_c_ready = 1'h0; // @[TLSerdes.scala:45:71]
wire client_tl_d_ready = 1'h0; // @[TLSerdes.scala:45:71]
wire client_tl_d_valid = 1'h0; // @[TLSerdes.scala:45:71]
wire client_tl_d_bits_denied = 1'h0; // @[TLSerdes.scala:45:71]
wire client_tl_d_bits_corrupt = 1'h0; // @[TLSerdes.scala:45:71]
wire client_tl_e_ready = 1'h0; // @[TLSerdes.scala:45:71]
wire _out_channels_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _out_channels_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire _out_channels_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire out_channels_0_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire out_channels_0_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire _out_channels_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:74]
wire _out_channels_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:74]
wire _out_channels_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _out_channels_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire out_channels_2_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire out_channels_2_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire out_channels_2_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _in_channels_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _in_channels_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _in_channels_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74]
wire _in_channels_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire in_channels_3_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire managerNodeIn_a_valid = auto_manager_in_a_valid_0; // @[TLSerdes.scala:39:9]
wire [2:0] managerNodeIn_a_bits_opcode = auto_manager_in_a_bits_opcode_0; // @[TLSerdes.scala:39:9]
wire [2:0] managerNodeIn_a_bits_param = auto_manager_in_a_bits_param_0; // @[TLSerdes.scala:39:9]
wire [3:0] managerNodeIn_a_bits_size = auto_manager_in_a_bits_size_0; // @[TLSerdes.scala:39:9]
wire managerNodeIn_a_bits_source = auto_manager_in_a_bits_source_0; // @[TLSerdes.scala:39:9]
wire [31:0] managerNodeIn_a_bits_address = auto_manager_in_a_bits_address_0; // @[TLSerdes.scala:39:9]
wire [7:0] managerNodeIn_a_bits_mask = auto_manager_in_a_bits_mask_0; // @[TLSerdes.scala:39:9]
wire [63:0] managerNodeIn_a_bits_data = auto_manager_in_a_bits_data_0; // @[TLSerdes.scala:39:9]
wire managerNodeIn_a_bits_corrupt = auto_manager_in_a_bits_corrupt_0; // @[TLSerdes.scala:39:9]
wire managerNodeIn_d_ready = auto_manager_in_d_ready_0; // @[TLSerdes.scala:39:9]
wire managerNodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] managerNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] managerNodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] managerNodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire managerNodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire managerNodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire managerNodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] managerNodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire managerNodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire _io_debug_ser_busy_T_1; // @[package.scala:81:59]
wire _io_debug_des_busy_T_3; // @[package.scala:81:59]
wire auto_manager_in_a_ready_0; // @[TLSerdes.scala:39:9]
wire [2:0] auto_manager_in_d_bits_opcode_0; // @[TLSerdes.scala:39:9]
wire [1:0] auto_manager_in_d_bits_param_0; // @[TLSerdes.scala:39:9]
wire [3:0] auto_manager_in_d_bits_size_0; // @[TLSerdes.scala:39:9]
wire auto_manager_in_d_bits_source_0; // @[TLSerdes.scala:39:9]
wire auto_manager_in_d_bits_sink_0; // @[TLSerdes.scala:39:9]
wire auto_manager_in_d_bits_denied_0; // @[TLSerdes.scala:39:9]
wire [63:0] auto_manager_in_d_bits_data_0; // @[TLSerdes.scala:39:9]
wire auto_manager_in_d_bits_corrupt_0; // @[TLSerdes.scala:39:9]
wire auto_manager_in_d_valid_0; // @[TLSerdes.scala:39:9]
wire io_ser_0_in_ready_0; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_0_out_bits_flit_0; // @[TLSerdes.scala:39:9]
wire io_ser_1_in_ready_0; // @[TLSerdes.scala:39:9]
wire io_ser_2_in_ready_0; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_2_out_bits_flit_0; // @[TLSerdes.scala:39:9]
wire io_ser_2_out_valid_0; // @[TLSerdes.scala:39:9]
wire io_ser_3_in_ready_0; // @[TLSerdes.scala:39:9]
wire io_ser_4_in_ready_0; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_4_out_bits_flit_0; // @[TLSerdes.scala:39:9]
wire io_ser_4_out_valid_0; // @[TLSerdes.scala:39:9]
wire io_debug_ser_busy; // @[TLSerdes.scala:39:9]
wire io_debug_des_busy; // @[TLSerdes.scala:39:9]
assign auto_manager_in_a_ready_0 = managerNodeIn_a_ready; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_valid_0 = managerNodeIn_d_valid; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_opcode_0 = managerNodeIn_d_bits_opcode; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_param_0 = managerNodeIn_d_bits_param; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_size_0 = managerNodeIn_d_bits_size; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_source_0 = managerNodeIn_d_bits_source; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_sink_0 = managerNodeIn_d_bits_sink; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_denied_0 = managerNodeIn_d_bits_denied; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_data_0 = managerNodeIn_d_bits_data; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_corrupt_0 = managerNodeIn_d_bits_corrupt; // @[TLSerdes.scala:39:9]
wire [2:0] client_tl_a_bits_opcode; // @[TLSerdes.scala:45:71]
wire [2:0] client_tl_a_bits_param; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_a_bits_size; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_a_bits_source; // @[TLSerdes.scala:45:71]
wire [63:0] client_tl_a_bits_address; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_a_bits_mask; // @[TLSerdes.scala:45:71]
wire [63:0] client_tl_a_bits_data; // @[TLSerdes.scala:45:71]
wire client_tl_a_bits_corrupt; // @[TLSerdes.scala:45:71]
wire client_tl_a_valid; // @[TLSerdes.scala:45:71]
wire [2:0] client_tl_c_bits_opcode; // @[TLSerdes.scala:45:71]
wire [2:0] client_tl_c_bits_param; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_c_bits_size; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_c_bits_source; // @[TLSerdes.scala:45:71]
wire [63:0] client_tl_c_bits_address; // @[TLSerdes.scala:45:71]
wire [63:0] client_tl_c_bits_data; // @[TLSerdes.scala:45:71]
wire client_tl_c_bits_corrupt; // @[TLSerdes.scala:45:71]
wire client_tl_c_valid; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_e_bits_sink; // @[TLSerdes.scala:45:71]
wire client_tl_e_valid; // @[TLSerdes.scala:45:71]
wire _io_debug_ser_busy_T; // @[package.scala:81:59]
assign _io_debug_ser_busy_T_1 = _io_debug_ser_busy_T | _ser_4_io_busy; // @[TLSerdes.scala:69:23]
assign io_debug_ser_busy = _io_debug_ser_busy_T_1; // @[TLSerdes.scala:39:9]
wire [2:0] in_channels_3_1_bits_opcode; // @[Bundles.scala:264:61]
wire [1:0] in_channels_3_1_bits_param; // @[Bundles.scala:264:61]
wire [3:0] in_channels_3_1_bits_size; // @[Bundles.scala:264:61]
wire in_channels_3_1_bits_source; // @[Bundles.scala:264:61]
wire [31:0] in_channels_3_1_bits_address; // @[Bundles.scala:264:61]
wire [7:0] in_channels_3_1_bits_mask; // @[Bundles.scala:264:61]
wire [63:0] in_channels_3_1_bits_data; // @[Bundles.scala:264:61]
wire in_channels_3_1_bits_corrupt; // @[Bundles.scala:264:61]
wire in_channels_3_1_valid; // @[Bundles.scala:264:61]
assign managerNodeIn_d_bits_size = _in_channels_1_2_io_protocol_bits_size[3:0]; // @[TLSerdes.scala:79:28, :85:9]
assign managerNodeIn_d_bits_source = _in_channels_1_2_io_protocol_bits_source[0]; // @[TLSerdes.scala:79:28, :85:9]
assign managerNodeIn_d_bits_sink = _in_channels_1_2_io_protocol_bits_sink[0]; // @[TLSerdes.scala:79:28, :85:9]
assign in_channels_3_1_bits_size = _in_channels_3_2_io_protocol_bits_size[3:0]; // @[TLSerdes.scala:81:28, :85:9]
assign in_channels_3_1_bits_source = _in_channels_3_2_io_protocol_bits_source[0]; // @[TLSerdes.scala:81:28, :85:9]
assign in_channels_3_1_bits_address = _in_channels_3_2_io_protocol_bits_address[31:0]; // @[TLSerdes.scala:81:28, :85:9]
wire _io_debug_des_busy_T; // @[package.scala:81:59]
wire _io_debug_des_busy_T_1 = _io_debug_des_busy_T | _des_2_io_busy; // @[TLSerdes.scala:86:23]
wire _io_debug_des_busy_T_2 = _io_debug_des_busy_T_1 | _des_3_io_busy; // @[TLSerdes.scala:86:23]
assign _io_debug_des_busy_T_3 = _io_debug_des_busy_T_2 | _des_4_io_busy; // @[TLSerdes.scala:86:23]
assign io_debug_des_busy = _io_debug_des_busy_T_3; // @[TLSerdes.scala:39:9]
TLMonitor_45 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (managerNodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (managerNodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (managerNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (managerNodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (managerNodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (managerNodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (managerNodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (managerNodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (managerNodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (managerNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (managerNodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (managerNodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (managerNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (managerNodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (managerNodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (managerNodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (managerNodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (managerNodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (managerNodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (managerNodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
TLEToBeat_SerialRAM_a64d64s8k8z8c out_channels_0_2 ( // @[TLSerdes.scala:59:50]
.clock (clock),
.reset (reset),
.io_beat_ready (_ser_0_io_in_ready), // @[TLSerdes.scala:69:23]
.io_beat_bits_head (_out_channels_0_2_io_beat_bits_head)
); // @[TLSerdes.scala:59:50]
TLCToBeat_SerialRAM_a64d64s8k8z8c out_channels_2_2 ( // @[TLSerdes.scala:61:50]
.clock (clock),
.reset (reset),
.io_beat_ready (_ser_2_io_in_ready), // @[TLSerdes.scala:69:23]
.io_beat_bits_head (_out_channels_2_2_io_beat_bits_head)
); // @[TLSerdes.scala:61:50]
TLAToBeat_SerialRAM_a64d64s8k8z8c out_channels_4_2 ( // @[TLSerdes.scala:63:50]
.clock (clock),
.reset (reset),
.io_protocol_ready (managerNodeIn_a_ready),
.io_protocol_valid (managerNodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_protocol_bits_opcode (managerNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_protocol_bits_param (managerNodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_protocol_bits_size ({4'h0, managerNodeIn_a_bits_size}), // @[TLSerdes.scala:68:21]
.io_protocol_bits_source ({7'h0, managerNodeIn_a_bits_source}), // @[TLSerdes.scala:68:21]
.io_protocol_bits_address ({32'h0, managerNodeIn_a_bits_address}), // @[TLSerdes.scala:68:21]
.io_protocol_bits_mask (managerNodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_protocol_bits_data (managerNodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_protocol_bits_corrupt (managerNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_beat_ready (_ser_4_io_in_ready), // @[TLSerdes.scala:69:23]
.io_beat_valid (_out_channels_4_2_io_beat_valid),
.io_beat_bits_payload (_out_channels_4_2_io_beat_bits_payload),
.io_beat_bits_head (_out_channels_4_2_io_beat_bits_head),
.io_beat_bits_tail (_out_channels_4_2_io_beat_bits_tail)
); // @[TLSerdes.scala:63:50]
GenericSerializer_TLBeatw10_f32 ser_0 ( // @[TLSerdes.scala:69:23]
.clock (clock),
.reset (reset),
.io_in_ready (_ser_0_io_in_ready),
.io_in_bits_head (_out_channels_0_2_io_beat_bits_head), // @[TLSerdes.scala:59:50]
.io_out_ready (io_ser_0_out_ready_0), // @[TLSerdes.scala:39:9]
.io_out_bits_flit (io_ser_0_out_bits_flit_0)
); // @[TLSerdes.scala:69:23]
GenericSerializer_TLBeatw88_f32 ser_2 ( // @[TLSerdes.scala:69:23]
.clock (clock),
.reset (reset),
.io_in_ready (_ser_2_io_in_ready),
.io_in_bits_head (_out_channels_2_2_io_beat_bits_head), // @[TLSerdes.scala:61:50]
.io_out_ready (io_ser_2_out_ready_0), // @[TLSerdes.scala:39:9]
.io_out_valid (io_ser_2_out_valid_0),
.io_out_bits_flit (io_ser_2_out_bits_flit_0),
.io_busy (_io_debug_ser_busy_T)
); // @[TLSerdes.scala:69:23]
GenericSerializer_TLBeatw88_f32_1 ser_4 ( // @[TLSerdes.scala:69:23]
.clock (clock),
.reset (reset),
.io_in_ready (_ser_4_io_in_ready),
.io_in_valid (_out_channels_4_2_io_beat_valid), // @[TLSerdes.scala:63:50]
.io_in_bits_payload (_out_channels_4_2_io_beat_bits_payload), // @[TLSerdes.scala:63:50]
.io_in_bits_head (_out_channels_4_2_io_beat_bits_head), // @[TLSerdes.scala:63:50]
.io_in_bits_tail (_out_channels_4_2_io_beat_bits_tail), // @[TLSerdes.scala:63:50]
.io_out_ready (io_ser_4_out_ready_0), // @[TLSerdes.scala:39:9]
.io_out_valid (io_ser_4_out_valid_0),
.io_out_bits_flit (io_ser_4_out_bits_flit_0),
.io_busy (_ser_4_io_busy)
); // @[TLSerdes.scala:69:23]
TLEFromBeat_SerialRAM_a64d64s8k8z8c in_channels_0_2 ( // @[TLSerdes.scala:78:28]
.clock (clock),
.reset (reset),
.io_protocol_valid (client_tl_e_valid),
.io_protocol_bits_sink (client_tl_e_bits_sink),
.io_beat_ready (_in_channels_0_2_io_beat_ready),
.io_beat_valid (_des_0_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_payload (_des_0_io_out_bits_payload), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_0_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_0_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:78:28]
TLDFromBeat_SerialRAM_a64d64s8k8z8c in_channels_1_2 ( // @[TLSerdes.scala:79:28]
.clock (clock),
.reset (reset),
.io_protocol_ready (managerNodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_protocol_valid (managerNodeIn_d_valid),
.io_protocol_bits_opcode (managerNodeIn_d_bits_opcode),
.io_protocol_bits_param (managerNodeIn_d_bits_param),
.io_protocol_bits_size (_in_channels_1_2_io_protocol_bits_size),
.io_protocol_bits_source (_in_channels_1_2_io_protocol_bits_source),
.io_protocol_bits_sink (_in_channels_1_2_io_protocol_bits_sink),
.io_protocol_bits_denied (managerNodeIn_d_bits_denied),
.io_protocol_bits_data (managerNodeIn_d_bits_data),
.io_protocol_bits_corrupt (managerNodeIn_d_bits_corrupt),
.io_beat_ready (_in_channels_1_2_io_beat_ready),
.io_beat_valid (_des_1_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_payload (_des_1_io_out_bits_payload), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_1_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_1_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:79:28]
TLCFromBeat_SerialRAM_a64d64s8k8z8c in_channels_2_2 ( // @[TLSerdes.scala:80:28]
.clock (clock),
.reset (reset),
.io_protocol_valid (client_tl_c_valid),
.io_protocol_bits_opcode (client_tl_c_bits_opcode),
.io_protocol_bits_param (client_tl_c_bits_param),
.io_protocol_bits_size (client_tl_c_bits_size),
.io_protocol_bits_source (client_tl_c_bits_source),
.io_protocol_bits_address (client_tl_c_bits_address),
.io_protocol_bits_data (client_tl_c_bits_data),
.io_protocol_bits_corrupt (client_tl_c_bits_corrupt),
.io_beat_ready (_in_channels_2_2_io_beat_ready),
.io_beat_valid (_des_2_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_payload (_des_2_io_out_bits_payload), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_2_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_2_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:80:28]
TLBFromBeat_SerialRAM_a64d64s8k8z8c in_channels_3_2 ( // @[TLSerdes.scala:81:28]
.clock (clock),
.reset (reset),
.io_protocol_valid (in_channels_3_1_valid),
.io_protocol_bits_opcode (in_channels_3_1_bits_opcode),
.io_protocol_bits_param (in_channels_3_1_bits_param),
.io_protocol_bits_size (_in_channels_3_2_io_protocol_bits_size),
.io_protocol_bits_source (_in_channels_3_2_io_protocol_bits_source),
.io_protocol_bits_address (_in_channels_3_2_io_protocol_bits_address),
.io_protocol_bits_mask (in_channels_3_1_bits_mask),
.io_protocol_bits_data (in_channels_3_1_bits_data),
.io_protocol_bits_corrupt (in_channels_3_1_bits_corrupt),
.io_beat_ready (_in_channels_3_2_io_beat_ready),
.io_beat_valid (_des_3_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_payload (_des_3_io_out_bits_payload), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_3_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_3_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:81:28]
TLAFromBeat_SerialRAM_a64d64s8k8z8c in_channels_4_2 ( // @[TLSerdes.scala:82:28]
.clock (clock),
.reset (reset),
.io_protocol_valid (client_tl_a_valid),
.io_protocol_bits_opcode (client_tl_a_bits_opcode),
.io_protocol_bits_param (client_tl_a_bits_param),
.io_protocol_bits_size (client_tl_a_bits_size),
.io_protocol_bits_source (client_tl_a_bits_source),
.io_protocol_bits_address (client_tl_a_bits_address),
.io_protocol_bits_mask (client_tl_a_bits_mask),
.io_protocol_bits_data (client_tl_a_bits_data),
.io_protocol_bits_corrupt (client_tl_a_bits_corrupt),
.io_beat_ready (_in_channels_4_2_io_beat_ready),
.io_beat_valid (_des_4_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_payload (_des_4_io_out_bits_payload), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_4_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_4_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:82:28]
GenericDeserializer_TLBeatw10_f32_1 des_0 ( // @[TLSerdes.scala:86:23]
.clock (clock),
.reset (reset),
.io_in_ready (io_ser_0_in_ready_0),
.io_in_valid (io_ser_0_in_valid_0), // @[TLSerdes.scala:39:9]
.io_in_bits_flit (io_ser_0_in_bits_flit_0), // @[TLSerdes.scala:39:9]
.io_out_ready (_in_channels_0_2_io_beat_ready), // @[TLSerdes.scala:78:28]
.io_out_valid (_des_0_io_out_valid),
.io_out_bits_payload (_des_0_io_out_bits_payload),
.io_out_bits_head (_des_0_io_out_bits_head),
.io_out_bits_tail (_des_0_io_out_bits_tail)
); // @[TLSerdes.scala:86:23]
GenericDeserializer_TLBeatw67_f32_1 des_1 ( // @[TLSerdes.scala:86:23]
.clock (clock),
.reset (reset),
.io_in_ready (io_ser_1_in_ready_0),
.io_in_valid (io_ser_1_in_valid_0), // @[TLSerdes.scala:39:9]
.io_in_bits_flit (io_ser_1_in_bits_flit_0), // @[TLSerdes.scala:39:9]
.io_out_ready (_in_channels_1_2_io_beat_ready), // @[TLSerdes.scala:79:28]
.io_out_valid (_des_1_io_out_valid),
.io_out_bits_payload (_des_1_io_out_bits_payload),
.io_out_bits_head (_des_1_io_out_bits_head),
.io_out_bits_tail (_des_1_io_out_bits_tail),
.io_busy (_io_debug_des_busy_T)
); // @[TLSerdes.scala:86:23]
GenericDeserializer_TLBeatw88_f32_2 des_2 ( // @[TLSerdes.scala:86:23]
.clock (clock),
.reset (reset),
.io_in_ready (io_ser_2_in_ready_0),
.io_in_valid (io_ser_2_in_valid_0), // @[TLSerdes.scala:39:9]
.io_in_bits_flit (io_ser_2_in_bits_flit_0), // @[TLSerdes.scala:39:9]
.io_out_ready (_in_channels_2_2_io_beat_ready), // @[TLSerdes.scala:80:28]
.io_out_valid (_des_2_io_out_valid),
.io_out_bits_payload (_des_2_io_out_bits_payload),
.io_out_bits_head (_des_2_io_out_bits_head),
.io_out_bits_tail (_des_2_io_out_bits_tail),
.io_busy (_des_2_io_busy)
); // @[TLSerdes.scala:86:23]
GenericDeserializer_TLBeatw87_f32_1 des_3 ( // @[TLSerdes.scala:86:23]
.clock (clock),
.reset (reset),
.io_in_ready (io_ser_3_in_ready_0),
.io_in_valid (io_ser_3_in_valid_0), // @[TLSerdes.scala:39:9]
.io_in_bits_flit (io_ser_3_in_bits_flit_0), // @[TLSerdes.scala:39:9]
.io_out_ready (_in_channels_3_2_io_beat_ready), // @[TLSerdes.scala:81:28]
.io_out_valid (_des_3_io_out_valid),
.io_out_bits_payload (_des_3_io_out_bits_payload),
.io_out_bits_head (_des_3_io_out_bits_head),
.io_out_bits_tail (_des_3_io_out_bits_tail),
.io_busy (_des_3_io_busy)
); // @[TLSerdes.scala:86:23]
GenericDeserializer_TLBeatw88_f32_3 des_4 ( // @[TLSerdes.scala:86:23]
.clock (clock),
.reset (reset),
.io_in_ready (io_ser_4_in_ready_0),
.io_in_valid (io_ser_4_in_valid_0), // @[TLSerdes.scala:39:9]
.io_in_bits_flit (io_ser_4_in_bits_flit_0), // @[TLSerdes.scala:39:9]
.io_out_ready (_in_channels_4_2_io_beat_ready), // @[TLSerdes.scala:82:28]
.io_out_valid (_des_4_io_out_valid),
.io_out_bits_payload (_des_4_io_out_bits_payload),
.io_out_bits_head (_des_4_io_out_bits_head),
.io_out_bits_tail (_des_4_io_out_bits_tail),
.io_busy (_des_4_io_busy)
); // @[TLSerdes.scala:86:23]
assign auto_manager_in_a_ready = auto_manager_in_a_ready_0; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_valid = auto_manager_in_d_valid_0; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_opcode = auto_manager_in_d_bits_opcode_0; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_param = auto_manager_in_d_bits_param_0; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_size = auto_manager_in_d_bits_size_0; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_source = auto_manager_in_d_bits_source_0; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_sink = auto_manager_in_d_bits_sink_0; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_denied = auto_manager_in_d_bits_denied_0; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_data = auto_manager_in_d_bits_data_0; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_corrupt = auto_manager_in_d_bits_corrupt_0; // @[TLSerdes.scala:39:9]
assign io_ser_0_in_ready = io_ser_0_in_ready_0; // @[TLSerdes.scala:39:9]
assign io_ser_0_out_bits_flit = io_ser_0_out_bits_flit_0; // @[TLSerdes.scala:39:9]
assign io_ser_1_in_ready = io_ser_1_in_ready_0; // @[TLSerdes.scala:39:9]
assign io_ser_2_in_ready = io_ser_2_in_ready_0; // @[TLSerdes.scala:39:9]
assign io_ser_2_out_valid = io_ser_2_out_valid_0; // @[TLSerdes.scala:39:9]
assign io_ser_2_out_bits_flit = io_ser_2_out_bits_flit_0; // @[TLSerdes.scala:39:9]
assign io_ser_3_in_ready = io_ser_3_in_ready_0; // @[TLSerdes.scala:39:9]
assign io_ser_4_in_ready = io_ser_4_in_ready_0; // @[TLSerdes.scala:39:9]
assign io_ser_4_out_valid = io_ser_4_out_valid_0; // @[TLSerdes.scala:39:9]
assign io_ser_4_out_bits_flit = io_ser_4_out_bits_flit_0; // @[TLSerdes.scala:39:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PE_329 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_73
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<8>, clock
reg c2 : SInt<8>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h0), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node _c1_T = bits(io.in_d, 7, 0)
node _c1_T_1 = asSInt(_c1_T)
connect c1, _c1_T_1
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node _c2_T = bits(io.in_d, 7, 0)
node _c2_T_1 = asSInt(_c2_T)
connect c2, _c2_T_1
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h0), _T_4)
node _T_6 = or(UInt<1>(0h1), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_329( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid // @[PE.scala:35:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7]
wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60]
wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [7:0] c1; // @[PE.scala:70:15]
wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [7:0] c2; // @[PE.scala:71:15]
wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25]
wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}]
wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16]
wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8]
c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15]
if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8]
c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15]
if (io_in_valid_0) // @[PE.scala:31:7]
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
always @(posedge)
MacUnit_73 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_b_0), // @[PE.scala:31:7]
.io_out_d (io_out_b_0)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_42 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0)
node _source_ok_T = shr(io.in.a.bits.source, 11)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits = bits(_uncommonBits_T, 10, 0)
node _T_4 = shr(io.in.a.bits.source, 11)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<11>(0h40f))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0)
node _T_24 = shr(io.in.a.bits.source, 11)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = and(_T_32, _T_37)
node _T_39 = or(UInt<1>(0h0), _T_38)
node _T_40 = and(_T_31, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_40, UInt<1>(0h1), "") : assert_2
node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_46 = and(_T_44, _T_45)
node _T_47 = or(UInt<1>(0h0), _T_46)
node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = and(_T_47, _T_52)
node _T_54 = or(UInt<1>(0h0), _T_53)
node _T_55 = and(UInt<1>(0h0), _T_54)
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(_T_55, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_55, UInt<1>(0h1), "") : assert_3
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_62, UInt<1>(0h1), "") : assert_5
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(is_aligned, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_69, UInt<1>(0h1), "") : assert_7
node _T_73 = not(io.in.a.bits.mask)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_74, UInt<1>(0h1), "") : assert_8
node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_78, UInt<1>(0h1), "") : assert_9
node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_82 :
node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_85 = and(_T_83, _T_84)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0)
node _T_86 = shr(io.in.a.bits.source, 11)
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_89 = and(_T_87, _T_88)
node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f))
node _T_91 = and(_T_89, _T_90)
node _T_92 = and(_T_85, _T_91)
node _T_93 = or(UInt<1>(0h0), _T_92)
node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(_T_93, _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_102, UInt<1>(0h1), "") : assert_10
node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_108 = and(_T_106, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = and(_T_109, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_115)
node _T_117 = and(UInt<1>(0h0), _T_116)
node _T_118 = asUInt(reset)
node _T_119 = eq(_T_118, UInt<1>(0h0))
when _T_119 :
node _T_120 = eq(_T_117, UInt<1>(0h0))
when _T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_117, UInt<1>(0h1), "") : assert_11
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_124, UInt<1>(0h1), "") : assert_13
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(is_aligned, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_131, UInt<1>(0h1), "") : assert_15
node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_136 = asUInt(reset)
node _T_137 = eq(_T_136, UInt<1>(0h0))
when _T_137 :
node _T_138 = eq(_T_135, UInt<1>(0h0))
when _T_138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_135, UInt<1>(0h1), "") : assert_16
node _T_139 = not(io.in.a.bits.mask)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_140, UInt<1>(0h1), "") : assert_17
node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_T_144, UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_144, UInt<1>(0h1), "") : assert_18
node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_148 :
node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0)
node _T_152 = shr(io.in.a.bits.source, 11)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f))
node _T_157 = and(_T_155, _T_156)
node _T_158 = and(_T_151, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_159, UInt<1>(0h1), "") : assert_19
node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_165 = and(_T_163, _T_164)
node _T_166 = or(UInt<1>(0h0), _T_165)
node _T_167 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_168 = cvt(_T_167)
node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000)))
node _T_170 = asSInt(_T_169)
node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0)))
node _T_172 = and(_T_166, _T_171)
node _T_173 = or(UInt<1>(0h0), _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_173, UInt<1>(0h1), "") : assert_20
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(is_aligned, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(io.in.a.bits.mask, mask)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_187, UInt<1>(0h1), "") : assert_24
node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_191, UInt<1>(0h1), "") : assert_25
node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_195 :
node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0)
node _T_199 = shr(io.in.a.bits.source, 11)
node _T_200 = eq(_T_199, UInt<1>(0h0))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f))
node _T_204 = and(_T_202, _T_203)
node _T_205 = and(_T_198, _T_204)
node _T_206 = or(UInt<1>(0h0), _T_205)
node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_209 = and(_T_207, _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = and(_T_210, _T_215)
node _T_217 = or(UInt<1>(0h0), _T_216)
node _T_218 = and(_T_206, _T_217)
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_218, UInt<1>(0h1), "") : assert_26
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_225 = asUInt(reset)
node _T_226 = eq(_T_225, UInt<1>(0h0))
when _T_226 :
node _T_227 = eq(is_aligned, UInt<1>(0h0))
when _T_227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(_T_228, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_228, UInt<1>(0h1), "") : assert_29
node _T_232 = eq(io.in.a.bits.mask, mask)
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_236 :
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_239 = and(_T_237, _T_238)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0)
node _T_240 = shr(io.in.a.bits.source, 11)
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_243 = and(_T_241, _T_242)
node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f))
node _T_245 = and(_T_243, _T_244)
node _T_246 = and(_T_239, _T_245)
node _T_247 = or(UInt<1>(0h0), _T_246)
node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_253 = cvt(_T_252)
node _T_254 = and(_T_253, asSInt(UInt<17>(0h10000)))
node _T_255 = asSInt(_T_254)
node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0)))
node _T_257 = and(_T_251, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = and(_T_247, _T_258)
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(_T_259, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_259, UInt<1>(0h1), "") : assert_31
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_266 = asUInt(reset)
node _T_267 = eq(_T_266, UInt<1>(0h0))
when _T_267 :
node _T_268 = eq(is_aligned, UInt<1>(0h0))
when _T_268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_270 = asUInt(reset)
node _T_271 = eq(_T_270, UInt<1>(0h0))
when _T_271 :
node _T_272 = eq(_T_269, UInt<1>(0h0))
when _T_272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_269, UInt<1>(0h1), "") : assert_34
node _T_273 = not(mask)
node _T_274 = and(io.in.a.bits.mask, _T_273)
node _T_275 = eq(_T_274, UInt<1>(0h0))
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(_T_275, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_275, UInt<1>(0h1), "") : assert_35
node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_279 :
node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_282 = and(_T_280, _T_281)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0)
node _T_283 = shr(io.in.a.bits.source, 11)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_286 = and(_T_284, _T_285)
node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f))
node _T_288 = and(_T_286, _T_287)
node _T_289 = and(_T_282, _T_288)
node _T_290 = or(UInt<1>(0h0), _T_289)
node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_292 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_293 = cvt(_T_292)
node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000)))
node _T_295 = asSInt(_T_294)
node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0)))
node _T_297 = and(_T_291, _T_296)
node _T_298 = or(UInt<1>(0h0), _T_297)
node _T_299 = and(_T_290, _T_298)
node _T_300 = asUInt(reset)
node _T_301 = eq(_T_300, UInt<1>(0h0))
when _T_301 :
node _T_302 = eq(_T_299, UInt<1>(0h0))
when _T_302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_299, UInt<1>(0h1), "") : assert_36
node _T_303 = asUInt(reset)
node _T_304 = eq(_T_303, UInt<1>(0h0))
when _T_304 :
node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(is_aligned, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_309, UInt<1>(0h1), "") : assert_39
node _T_313 = eq(io.in.a.bits.mask, mask)
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_313, UInt<1>(0h1), "") : assert_40
node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_317 :
node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0)
node _T_321 = shr(io.in.a.bits.source, 11)
node _T_322 = eq(_T_321, UInt<1>(0h0))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f))
node _T_326 = and(_T_324, _T_325)
node _T_327 = and(_T_320, _T_326)
node _T_328 = or(UInt<1>(0h0), _T_327)
node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_330 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_331 = cvt(_T_330)
node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000)))
node _T_333 = asSInt(_T_332)
node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0)))
node _T_335 = and(_T_329, _T_334)
node _T_336 = or(UInt<1>(0h0), _T_335)
node _T_337 = and(_T_328, _T_336)
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(_T_337, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_337, UInt<1>(0h1), "") : assert_41
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(is_aligned, UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_347, UInt<1>(0h1), "") : assert_44
node _T_351 = eq(io.in.a.bits.mask, mask)
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_351, UInt<1>(0h1), "") : assert_45
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0)
node _T_359 = shr(io.in.a.bits.source, 11)
node _T_360 = eq(_T_359, UInt<1>(0h0))
node _T_361 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_362 = and(_T_360, _T_361)
node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f))
node _T_364 = and(_T_362, _T_363)
node _T_365 = and(_T_358, _T_364)
node _T_366 = or(UInt<1>(0h0), _T_365)
node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_368 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_369 = cvt(_T_368)
node _T_370 = and(_T_369, asSInt(UInt<17>(0h10000)))
node _T_371 = asSInt(_T_370)
node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0)))
node _T_373 = and(_T_367, _T_372)
node _T_374 = or(UInt<1>(0h0), _T_373)
node _T_375 = and(_T_366, _T_374)
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_375, UInt<1>(0h1), "") : assert_46
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(is_aligned, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_385, UInt<1>(0h1), "") : assert_49
node _T_389 = eq(io.in.a.bits.mask, mask)
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_389, UInt<1>(0h1), "") : assert_50
node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_393, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_397, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 11)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_401 :
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_405, UInt<1>(0h1), "") : assert_54
node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_409, UInt<1>(0h1), "") : assert_55
node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_414 = asUInt(reset)
node _T_415 = eq(_T_414, UInt<1>(0h0))
when _T_415 :
node _T_416 = eq(_T_413, UInt<1>(0h0))
when _T_416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_413, UInt<1>(0h1), "") : assert_56
node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_418 = asUInt(reset)
node _T_419 = eq(_T_418, UInt<1>(0h0))
when _T_419 :
node _T_420 = eq(_T_417, UInt<1>(0h0))
when _T_420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_417, UInt<1>(0h1), "") : assert_57
node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_421 :
node _T_422 = asUInt(reset)
node _T_423 = eq(_T_422, UInt<1>(0h0))
when _T_423 :
node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(sink_ok, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_T_428, UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_428, UInt<1>(0h1), "") : assert_60
node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_432, UInt<1>(0h1), "") : assert_61
node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_436, UInt<1>(0h1), "") : assert_62
node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(_T_440, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_440, UInt<1>(0h1), "") : assert_63
node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_445 = or(UInt<1>(0h0), _T_444)
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_445, UInt<1>(0h1), "") : assert_64
node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_449 :
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(sink_ok, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_457 = asUInt(reset)
node _T_458 = eq(_T_457, UInt<1>(0h0))
when _T_458 :
node _T_459 = eq(_T_456, UInt<1>(0h0))
when _T_459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_456, UInt<1>(0h1), "") : assert_67
node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(_T_460, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_460, UInt<1>(0h1), "") : assert_68
node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_464, UInt<1>(0h1), "") : assert_69
node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_469 = or(_T_468, io.in.d.bits.corrupt)
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_469, UInt<1>(0h1), "") : assert_70
node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_474 = or(UInt<1>(0h0), _T_473)
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_474, UInt<1>(0h1), "") : assert_71
node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_478 :
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_482, UInt<1>(0h1), "") : assert_73
node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_486, UInt<1>(0h1), "") : assert_74
node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_491 = or(UInt<1>(0h0), _T_490)
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_491, UInt<1>(0h1), "") : assert_75
node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_495 :
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_499, UInt<1>(0h1), "") : assert_77
node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_504 = or(_T_503, io.in.d.bits.corrupt)
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(_T_504, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_504, UInt<1>(0h1), "") : assert_78
node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_509, UInt<1>(0h1), "") : assert_79
node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_513 :
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_T_517, UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_517, UInt<1>(0h1), "") : assert_81
node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_521, UInt<1>(0h1), "") : assert_82
node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_526 = or(UInt<1>(0h0), _T_525)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_526, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<26>(0h0)
connect _WIRE.bits.source, UInt<11>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_530, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<26>(0h0)
connect _WIRE_2.bits.source, UInt<11>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_534, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_538, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_542 = eq(a_first, UInt<1>(0h0))
node _T_543 = and(io.in.a.valid, _T_542)
when _T_543 :
node _T_544 = eq(io.in.a.bits.opcode, opcode)
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_544, UInt<1>(0h1), "") : assert_87
node _T_548 = eq(io.in.a.bits.param, param)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_548, UInt<1>(0h1), "") : assert_88
node _T_552 = eq(io.in.a.bits.size, size)
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(_T_552, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_552, UInt<1>(0h1), "") : assert_89
node _T_556 = eq(io.in.a.bits.source, source)
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_556, UInt<1>(0h1), "") : assert_90
node _T_560 = eq(io.in.a.bits.address, address)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_560, UInt<1>(0h1), "") : assert_91
node _T_564 = and(io.in.a.ready, io.in.a.valid)
node _T_565 = and(_T_564, a_first)
when _T_565 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_566 = eq(d_first, UInt<1>(0h0))
node _T_567 = and(io.in.d.valid, _T_566)
when _T_567 :
node _T_568 = eq(io.in.d.bits.opcode, opcode_1)
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_568, UInt<1>(0h1), "") : assert_92
node _T_572 = eq(io.in.d.bits.param, param_1)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_572, UInt<1>(0h1), "") : assert_93
node _T_576 = eq(io.in.d.bits.size, size_1)
node _T_577 = asUInt(reset)
node _T_578 = eq(_T_577, UInt<1>(0h0))
when _T_578 :
node _T_579 = eq(_T_576, UInt<1>(0h0))
when _T_579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_576, UInt<1>(0h1), "") : assert_94
node _T_580 = eq(io.in.d.bits.source, source_1)
node _T_581 = asUInt(reset)
node _T_582 = eq(_T_581, UInt<1>(0h0))
when _T_582 :
node _T_583 = eq(_T_580, UInt<1>(0h0))
when _T_583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_580, UInt<1>(0h1), "") : assert_95
node _T_584 = eq(io.in.d.bits.sink, sink)
node _T_585 = asUInt(reset)
node _T_586 = eq(_T_585, UInt<1>(0h0))
when _T_586 :
node _T_587 = eq(_T_584, UInt<1>(0h0))
when _T_587 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_584, UInt<1>(0h1), "") : assert_96
node _T_588 = eq(io.in.d.bits.denied, denied)
node _T_589 = asUInt(reset)
node _T_590 = eq(_T_589, UInt<1>(0h0))
when _T_590 :
node _T_591 = eq(_T_588, UInt<1>(0h0))
when _T_591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_588, UInt<1>(0h1), "") : assert_97
node _T_592 = and(io.in.d.ready, io.in.d.valid)
node _T_593 = and(_T_592, d_first)
when _T_593 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0)
regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0)
regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1040>
connect a_set, UInt<1040>(0h0)
wire a_set_wo_ready : UInt<1040>
connect a_set_wo_ready, UInt<1040>(0h0)
wire a_opcodes_set : UInt<4160>
connect a_opcodes_set, UInt<4160>(0h0)
wire a_sizes_set : UInt<4160>
connect a_sizes_set, UInt<4160>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_594 = and(io.in.a.valid, a_first_1)
node _T_595 = and(_T_594, UInt<1>(0h1))
when _T_595 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_596 = and(io.in.a.ready, io.in.a.valid)
node _T_597 = and(_T_596, a_first_1)
node _T_598 = and(_T_597, UInt<1>(0h1))
when _T_598 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_599 = dshr(inflight, io.in.a.bits.source)
node _T_600 = bits(_T_599, 0, 0)
node _T_601 = eq(_T_600, UInt<1>(0h0))
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_601, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1040>
connect d_clr, UInt<1040>(0h0)
wire d_clr_wo_ready : UInt<1040>
connect d_clr_wo_ready, UInt<1040>(0h0)
wire d_opcodes_clr : UInt<4160>
connect d_opcodes_clr, UInt<4160>(0h0)
wire d_sizes_clr : UInt<4160>
connect d_sizes_clr, UInt<4160>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_605 = and(io.in.d.valid, d_first_1)
node _T_606 = and(_T_605, UInt<1>(0h1))
node _T_607 = eq(d_release_ack, UInt<1>(0h0))
node _T_608 = and(_T_606, _T_607)
when _T_608 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_609 = and(io.in.d.ready, io.in.d.valid)
node _T_610 = and(_T_609, d_first_1)
node _T_611 = and(_T_610, UInt<1>(0h1))
node _T_612 = eq(d_release_ack, UInt<1>(0h0))
node _T_613 = and(_T_611, _T_612)
when _T_613 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_614 = and(io.in.d.valid, d_first_1)
node _T_615 = and(_T_614, UInt<1>(0h1))
node _T_616 = eq(d_release_ack, UInt<1>(0h0))
node _T_617 = and(_T_615, _T_616)
when _T_617 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_618 = dshr(inflight, io.in.d.bits.source)
node _T_619 = bits(_T_618, 0, 0)
node _T_620 = or(_T_619, same_cycle_resp)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_620, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_626 = or(_T_624, _T_625)
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_626, UInt<1>(0h1), "") : assert_100
node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_630, UInt<1>(0h1), "") : assert_101
else :
node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_636 = or(_T_634, _T_635)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_636, UInt<1>(0h1), "") : assert_102
node _T_640 = eq(io.in.d.bits.size, a_size_lookup)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_640, UInt<1>(0h1), "") : assert_103
node _T_644 = and(io.in.d.valid, d_first_1)
node _T_645 = and(_T_644, a_first_1)
node _T_646 = and(_T_645, io.in.a.valid)
node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_648 = and(_T_646, _T_647)
node _T_649 = eq(d_release_ack, UInt<1>(0h0))
node _T_650 = and(_T_648, _T_649)
when _T_650 :
node _T_651 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_652 = or(_T_651, io.in.a.ready)
node _T_653 = asUInt(reset)
node _T_654 = eq(_T_653, UInt<1>(0h0))
when _T_654 :
node _T_655 = eq(_T_652, UInt<1>(0h0))
when _T_655 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_652, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_85
node _T_656 = orr(inflight)
node _T_657 = eq(_T_656, UInt<1>(0h0))
node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_659 = or(_T_657, _T_658)
node _T_660 = lt(watchdog, plusarg_reader.out)
node _T_661 = or(_T_659, _T_660)
node _T_662 = asUInt(reset)
node _T_663 = eq(_T_662, UInt<1>(0h0))
when _T_663 :
node _T_664 = eq(_T_661, UInt<1>(0h0))
when _T_664 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_661, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_665 = and(io.in.a.ready, io.in.a.valid)
node _T_666 = and(io.in.d.ready, io.in.d.valid)
node _T_667 = or(_T_665, _T_666)
when _T_667 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0)
regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0)
regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<26>(0h0)
connect _c_first_WIRE.bits.source, UInt<11>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<26>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<11>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1040>
connect c_set, UInt<1040>(0h0)
wire c_set_wo_ready : UInt<1040>
connect c_set_wo_ready, UInt<1040>(0h0)
wire c_opcodes_set : UInt<4160>
connect c_opcodes_set, UInt<4160>(0h0)
wire c_sizes_set : UInt<4160>
connect c_sizes_set, UInt<4160>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<26>(0h0)
connect _WIRE_6.bits.source, UInt<11>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_668 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<26>(0h0)
connect _WIRE_8.bits.source, UInt<11>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_671 = and(_T_669, _T_670)
node _T_672 = and(_T_668, _T_671)
when _T_672 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<26>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<26>(0h0)
connect _WIRE_10.bits.source, UInt<11>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_674 = and(_T_673, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<26>(0h0)
connect _WIRE_12.bits.source, UInt<11>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_677 = and(_T_675, _T_676)
node _T_678 = and(_T_674, _T_677)
when _T_678 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<26>(0h0)
connect _c_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<26>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<26>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<26>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<26>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<26>(0h0)
connect _WIRE_14.bits.source, UInt<11>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_679 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_680 = bits(_T_679, 0, 0)
node _T_681 = eq(_T_680, UInt<1>(0h0))
node _T_682 = asUInt(reset)
node _T_683 = eq(_T_682, UInt<1>(0h0))
when _T_683 :
node _T_684 = eq(_T_681, UInt<1>(0h0))
when _T_684 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_681, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<26>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<26>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1040>
connect d_clr_1, UInt<1040>(0h0)
wire d_clr_wo_ready_1 : UInt<1040>
connect d_clr_wo_ready_1, UInt<1040>(0h0)
wire d_opcodes_clr_1 : UInt<4160>
connect d_opcodes_clr_1, UInt<4160>(0h0)
wire d_sizes_clr_1 : UInt<4160>
connect d_sizes_clr_1, UInt<4160>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_685 = and(io.in.d.valid, d_first_2)
node _T_686 = and(_T_685, UInt<1>(0h1))
node _T_687 = and(_T_686, d_release_ack_1)
when _T_687 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_688 = and(io.in.d.ready, io.in.d.valid)
node _T_689 = and(_T_688, d_first_2)
node _T_690 = and(_T_689, UInt<1>(0h1))
node _T_691 = and(_T_690, d_release_ack_1)
when _T_691 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_692 = and(io.in.d.valid, d_first_2)
node _T_693 = and(_T_692, UInt<1>(0h1))
node _T_694 = and(_T_693, d_release_ack_1)
when _T_694 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<26>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<26>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<26>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_695 = dshr(inflight_1, io.in.d.bits.source)
node _T_696 = bits(_T_695, 0, 0)
node _T_697 = or(_T_696, same_cycle_resp_1)
node _T_698 = asUInt(reset)
node _T_699 = eq(_T_698, UInt<1>(0h0))
when _T_699 :
node _T_700 = eq(_T_697, UInt<1>(0h0))
when _T_700 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_697, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<26>(0h0)
connect _WIRE_16.bits.source, UInt<11>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_702 = asUInt(reset)
node _T_703 = eq(_T_702, UInt<1>(0h0))
when _T_703 :
node _T_704 = eq(_T_701, UInt<1>(0h0))
when _T_704 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_701, UInt<1>(0h1), "") : assert_108
else :
node _T_705 = eq(io.in.d.bits.size, c_size_lookup)
node _T_706 = asUInt(reset)
node _T_707 = eq(_T_706, UInt<1>(0h0))
when _T_707 :
node _T_708 = eq(_T_705, UInt<1>(0h0))
when _T_708 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_705, UInt<1>(0h1), "") : assert_109
node _T_709 = and(io.in.d.valid, d_first_2)
node _T_710 = and(_T_709, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<26>(0h0)
connect _WIRE_18.bits.source, UInt<11>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_711 = and(_T_710, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<26>(0h0)
connect _WIRE_20.bits.source, UInt<11>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_713 = and(_T_711, _T_712)
node _T_714 = and(_T_713, d_release_ack_1)
node _T_715 = eq(c_probe_ack, UInt<1>(0h0))
node _T_716 = and(_T_714, _T_715)
when _T_716 :
node _T_717 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<26>(0h0)
connect _WIRE_22.bits.source, UInt<11>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_718 = or(_T_717, _WIRE_23.ready)
node _T_719 = asUInt(reset)
node _T_720 = eq(_T_719, UInt<1>(0h0))
when _T_720 :
node _T_721 = eq(_T_718, UInt<1>(0h0))
when _T_721 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_718, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_86
node _T_722 = orr(inflight_1)
node _T_723 = eq(_T_722, UInt<1>(0h0))
node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_725 = or(_T_723, _T_724)
node _T_726 = lt(watchdog_1, plusarg_reader_1.out)
node _T_727 = or(_T_725, _T_726)
node _T_728 = asUInt(reset)
node _T_729 = eq(_T_728, UInt<1>(0h0))
when _T_729 :
node _T_730 = eq(_T_727, UInt<1>(0h0))
when _T_730 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_727, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<26>(0h0)
connect _WIRE_24.bits.source, UInt<11>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_732 = and(io.in.d.ready, io.in.d.valid)
node _T_733 = or(_T_731, _T_732)
when _T_733 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_42( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [10:0] source; // @[Monitor.scala:390:22]
reg [25:0] address; // @[Monitor.scala:391:22]
reg d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [10:0] source_1; // @[Monitor.scala:541:22]
reg [1039:0] inflight; // @[Monitor.scala:614:27]
reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33]
reg a_first_counter_1; // @[Edges.scala:229:27]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _GEN = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [1039:0] inflight_1; // @[Monitor.scala:726:35]
reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg d_first_counter_2; // @[Edges.scala:229:27]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetRegVec_w2_i0_15 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<2>, q : UInt<2>, flip en : UInt<1>}
node _reg_T = asAsyncReset(reset)
regreset reg : UInt<2>, clock, _reg_T, UInt<2>(0h0)
when io.en :
connect reg, io.d
connect io.q, reg | module AsyncResetRegVec_w2_i0_15( // @[AsyncResetReg.scala:56:7]
input clock, // @[AsyncResetReg.scala:56:7]
input reset, // @[AsyncResetReg.scala:56:7]
input [1:0] io_d, // @[AsyncResetReg.scala:59:14]
output [1:0] io_q // @[AsyncResetReg.scala:59:14]
);
wire [1:0] io_d_0 = io_d; // @[AsyncResetReg.scala:56:7]
wire _reg_T = reset; // @[AsyncResetReg.scala:61:29]
wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14]
wire [1:0] io_q_0; // @[AsyncResetReg.scala:56:7]
reg [1:0] reg_0; // @[AsyncResetReg.scala:61:50]
assign io_q_0 = reg_0; // @[AsyncResetReg.scala:56:7, :61:50]
always @(posedge clock or posedge _reg_T) begin // @[AsyncResetReg.scala:56:7, :61:29]
if (_reg_T) // @[AsyncResetReg.scala:56:7, :61:29]
reg_0 <= 2'h0; // @[AsyncResetReg.scala:61:50]
else // @[AsyncResetReg.scala:56:7]
reg_0 <= io_d_0; // @[AsyncResetReg.scala:56:7, :61:50]
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_266 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_266( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_173 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_188
connect io_out_sink_valid_1.clock, clock
connect io_out_sink_valid_1.reset, reset
connect io_out_sink_valid_1.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_valid_1.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_173( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_188 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_42 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_EntryData_42( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_g, // @[package.scala:268:18]
output io_y_ae, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c, // @[package.scala:268:18]
output io_y_fragmented_superpage // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g_0 = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_0 = io_x_ae_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage_0 = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_g = io_y_g_0; // @[package.scala:267:30]
assign io_y_ae = io_y_ae_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
assign io_y_fragmented_superpage = io_y_fragmented_superpage_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module EgressUnit_20 :
input clock : Clock
input reset : Reset
output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_available : UInt<1>[1], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[1], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[1], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[1], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
regreset channel_empty : UInt<1>, clock, reset, UInt<1>(0h1)
reg flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, clock
inst q of Queue3_EgressFlit_20
connect q.clock, clock
connect q.reset, reset
connect q.io.enq.valid, io.in[0].valid
connect q.io.enq.bits.head, io.in[0].bits.head
connect q.io.enq.bits.tail, io.in[0].bits.tail
node _q_io_enq_bits_ingress_id_T = eq(UInt<3>(0h5), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_1 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_2 = and(_q_io_enq_bits_ingress_id_T, _q_io_enq_bits_ingress_id_T_1)
node _q_io_enq_bits_ingress_id_T_3 = eq(UInt<4>(0ha), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_4 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_5 = and(_q_io_enq_bits_ingress_id_T_3, _q_io_enq_bits_ingress_id_T_4)
node _q_io_enq_bits_ingress_id_T_6 = eq(UInt<4>(0h9), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_7 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_8 = and(_q_io_enq_bits_ingress_id_T_6, _q_io_enq_bits_ingress_id_T_7)
node _q_io_enq_bits_ingress_id_T_9 = eq(UInt<3>(0h6), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_10 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_11 = and(_q_io_enq_bits_ingress_id_T_9, _q_io_enq_bits_ingress_id_T_10)
node _q_io_enq_bits_ingress_id_T_12 = eq(UInt<2>(0h3), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_13 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_14 = and(_q_io_enq_bits_ingress_id_T_12, _q_io_enq_bits_ingress_id_T_13)
node _q_io_enq_bits_ingress_id_T_15 = mux(_q_io_enq_bits_ingress_id_T_2, UInt<6>(0h1e), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_16 = mux(_q_io_enq_bits_ingress_id_T_5, UInt<6>(0h24), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_17 = mux(_q_io_enq_bits_ingress_id_T_8, UInt<6>(0h22), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_18 = mux(_q_io_enq_bits_ingress_id_T_11, UInt<6>(0h20), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_19 = mux(_q_io_enq_bits_ingress_id_T_14, UInt<6>(0h1c), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_20 = or(_q_io_enq_bits_ingress_id_T_15, _q_io_enq_bits_ingress_id_T_16)
node _q_io_enq_bits_ingress_id_T_21 = or(_q_io_enq_bits_ingress_id_T_20, _q_io_enq_bits_ingress_id_T_17)
node _q_io_enq_bits_ingress_id_T_22 = or(_q_io_enq_bits_ingress_id_T_21, _q_io_enq_bits_ingress_id_T_18)
node _q_io_enq_bits_ingress_id_T_23 = or(_q_io_enq_bits_ingress_id_T_22, _q_io_enq_bits_ingress_id_T_19)
wire _q_io_enq_bits_ingress_id_WIRE : UInt<6>
connect _q_io_enq_bits_ingress_id_WIRE, _q_io_enq_bits_ingress_id_T_23
connect q.io.enq.bits.ingress_id, _q_io_enq_bits_ingress_id_WIRE
connect q.io.enq.bits.payload, io.in[0].bits.payload
connect io.out.bits, q.io.deq.bits
connect io.out.valid, q.io.deq.valid
connect q.io.deq.ready, io.out.ready
node _T = eq(q.io.enq.ready, UInt<1>(0h0))
node _T_1 = and(q.io.enq.valid, _T)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at EgressUnit.scala:38 assert(!(q.io.enq.valid && !q.io.enq.ready))\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _io_credit_available_0_T = eq(q.io.count, UInt<1>(0h0))
connect io.credit_available[0], _io_credit_available_0_T
node _io_channel_status_0_occupied_T = eq(channel_empty, UInt<1>(0h0))
connect io.channel_status[0].occupied, _io_channel_status_0_occupied_T
connect io.channel_status[0].flow, flow
node _T_6 = and(io.credit_alloc[0].alloc, io.credit_alloc[0].tail)
when _T_6 :
connect channel_empty, UInt<1>(0h1)
when io.allocs[0].alloc :
connect channel_empty, UInt<1>(0h0)
connect flow, io.allocs[0].flow | module EgressUnit_20( // @[EgressUnit.scala:12:7]
input clock, // @[EgressUnit.scala:12:7]
input reset, // @[EgressUnit.scala:12:7]
input io_in_0_valid, // @[EgressUnit.scala:18:14]
input io_in_0_bits_head, // @[EgressUnit.scala:18:14]
input io_in_0_bits_tail, // @[EgressUnit.scala:18:14]
input [72:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14]
input [4:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14]
input [1:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14]
output io_credit_available_0, // @[EgressUnit.scala:18:14]
output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14]
input io_allocs_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14]
input io_out_ready, // @[EgressUnit.scala:18:14]
output io_out_valid, // @[EgressUnit.scala:18:14]
output io_out_bits_head, // @[EgressUnit.scala:18:14]
output io_out_bits_tail, // @[EgressUnit.scala:18:14]
output [72:0] io_out_bits_payload // @[EgressUnit.scala:18:14]
);
wire _q_io_enq_ready; // @[EgressUnit.scala:22:17]
wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17]
reg channel_empty; // @[EgressUnit.scala:20:30]
wire _q_io_enq_bits_ingress_id_T_13 = io_in_0_bits_flow_ingress_node_id == 2'h1; // @[EgressUnit.scala:32:27] |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_203 :
output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node rawIn_exp = bits(io.in, 31, 23)
node _rawIn_isZero_T = bits(rawIn_exp, 8, 6)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 32, 32)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 22, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
node _io_out_T = shl(io.in, 0)
connect io.out, _io_out_T
node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22)
node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0))
node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0))
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RecFNToRecFN_203( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_70 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_106
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_70( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_106 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_38 :
input clock : Clock
input reset : Reset
output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_return : UInt<8>, vc_free : UInt<8>}}
wire _in_flight_WIRE : UInt<1>[8]
connect _in_flight_WIRE[0], UInt<1>(0h0)
connect _in_flight_WIRE[1], UInt<1>(0h0)
connect _in_flight_WIRE[2], UInt<1>(0h0)
connect _in_flight_WIRE[3], UInt<1>(0h0)
connect _in_flight_WIRE[4], UInt<1>(0h0)
connect _in_flight_WIRE[5], UInt<1>(0h0)
connect _in_flight_WIRE[6], UInt<1>(0h0)
connect _in_flight_WIRE[7], UInt<1>(0h0)
regreset in_flight : UInt<1>[8], clock, reset, _in_flight_WIRE
when io.in.flit[0].valid :
when io.in.flit[0].bits.head :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1)
node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
when io.in.flit[0].bits.tail :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)
node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T_4 :
node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0))
node _T_6 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_7 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_8 = and(_T_6, _T_7)
node _T_9 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_10 = and(_T_8, _T_9)
node _T_11 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_12 = and(_T_10, _T_11)
node _T_13 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_14 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_15 = and(_T_13, _T_14)
node _T_16 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_19 = and(_T_17, _T_18)
node _T_20 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_21 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_24 = and(_T_22, _T_23)
node _T_25 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_26 = and(_T_24, _T_25)
node _T_27 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_28 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_29 = and(_T_27, _T_28)
node _T_30 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_33 = and(_T_31, _T_32)
node _T_34 = or(_T_12, _T_19)
node _T_35 = or(_T_34, _T_26)
node _T_36 = or(_T_35, _T_33)
node _T_37 = or(_T_5, _T_36)
node _T_38 = asUInt(reset)
node _T_39 = eq(_T_38, UInt<1>(0h0))
when _T_39 :
node _T_40 = eq(_T_37, UInt<1>(0h0))
when _T_40 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1
assert(clock, _T_37, UInt<1>(0h1), "") : assert_1
node _T_41 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1))
node _T_42 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_43 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_44 = and(_T_42, _T_43)
node _T_45 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_46 = and(_T_44, _T_45)
node _T_47 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_48 = and(_T_46, _T_47)
node _T_49 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_50 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_51 = and(_T_49, _T_50)
node _T_52 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_53 = and(_T_51, _T_52)
node _T_54 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_55 = and(_T_53, _T_54)
node _T_56 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_57 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0he))
node _T_58 = and(_T_56, _T_57)
node _T_59 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_60 = and(_T_58, _T_59)
node _T_61 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_62 = and(_T_60, _T_61)
node _T_63 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_64 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_65 = and(_T_63, _T_64)
node _T_66 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_67 = and(_T_65, _T_66)
node _T_68 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_69 = and(_T_67, _T_68)
node _T_70 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_71 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_72 = and(_T_70, _T_71)
node _T_73 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_74 = and(_T_72, _T_73)
node _T_75 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_76 = and(_T_74, _T_75)
node _T_77 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_78 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_79 = and(_T_77, _T_78)
node _T_80 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_81 = and(_T_79, _T_80)
node _T_82 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_83 = and(_T_81, _T_82)
node _T_84 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_85 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_86 = and(_T_84, _T_85)
node _T_87 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_88 = and(_T_86, _T_87)
node _T_89 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_90 = and(_T_88, _T_89)
node _T_91 = or(_T_48, _T_55)
node _T_92 = or(_T_91, _T_62)
node _T_93 = or(_T_92, _T_69)
node _T_94 = or(_T_93, _T_76)
node _T_95 = or(_T_94, _T_83)
node _T_96 = or(_T_95, _T_90)
node _T_97 = or(_T_41, _T_96)
node _T_98 = asUInt(reset)
node _T_99 = eq(_T_98, UInt<1>(0h0))
when _T_99 :
node _T_100 = eq(_T_97, UInt<1>(0h0))
when _T_100 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2
assert(clock, _T_97, UInt<1>(0h1), "") : assert_2
node _T_101 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2))
node _T_102 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_103 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_104 = and(_T_102, _T_103)
node _T_105 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_106 = and(_T_104, _T_105)
node _T_107 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_108 = and(_T_106, _T_107)
node _T_109 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_110 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_111 = and(_T_109, _T_110)
node _T_112 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_113 = and(_T_111, _T_112)
node _T_114 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_115 = and(_T_113, _T_114)
node _T_116 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_117 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_118 = and(_T_116, _T_117)
node _T_119 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_120 = and(_T_118, _T_119)
node _T_121 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_122 = and(_T_120, _T_121)
node _T_123 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_124 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_125 = and(_T_123, _T_124)
node _T_126 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_127 = and(_T_125, _T_126)
node _T_128 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_129 = and(_T_127, _T_128)
node _T_130 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_131 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_132 = and(_T_130, _T_131)
node _T_133 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_134 = and(_T_132, _T_133)
node _T_135 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_136 = and(_T_134, _T_135)
node _T_137 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_138 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0he))
node _T_139 = and(_T_137, _T_138)
node _T_140 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_141 = and(_T_139, _T_140)
node _T_142 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_143 = and(_T_141, _T_142)
node _T_144 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_145 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_146 = and(_T_144, _T_145)
node _T_147 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_148 = and(_T_146, _T_147)
node _T_149 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_150 = and(_T_148, _T_149)
node _T_151 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_152 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_153 = and(_T_151, _T_152)
node _T_154 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_155 = and(_T_153, _T_154)
node _T_156 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_157 = and(_T_155, _T_156)
node _T_158 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_159 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4))
node _T_160 = and(_T_158, _T_159)
node _T_161 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_162 = and(_T_160, _T_161)
node _T_163 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_164 = and(_T_162, _T_163)
node _T_165 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_166 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_167 = and(_T_165, _T_166)
node _T_168 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_169 = and(_T_167, _T_168)
node _T_170 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_171 = and(_T_169, _T_170)
node _T_172 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_173 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_174 = and(_T_172, _T_173)
node _T_175 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_176 = and(_T_174, _T_175)
node _T_177 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_178 = and(_T_176, _T_177)
node _T_179 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_180 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_181 = and(_T_179, _T_180)
node _T_182 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_183 = and(_T_181, _T_182)
node _T_184 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_185 = and(_T_183, _T_184)
node _T_186 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_187 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_188 = and(_T_186, _T_187)
node _T_189 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_190 = and(_T_188, _T_189)
node _T_191 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_192 = and(_T_190, _T_191)
node _T_193 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_194 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_195 = and(_T_193, _T_194)
node _T_196 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_197 = and(_T_195, _T_196)
node _T_198 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_199 = and(_T_197, _T_198)
node _T_200 = or(_T_108, _T_115)
node _T_201 = or(_T_200, _T_122)
node _T_202 = or(_T_201, _T_129)
node _T_203 = or(_T_202, _T_136)
node _T_204 = or(_T_203, _T_143)
node _T_205 = or(_T_204, _T_150)
node _T_206 = or(_T_205, _T_157)
node _T_207 = or(_T_206, _T_164)
node _T_208 = or(_T_207, _T_171)
node _T_209 = or(_T_208, _T_178)
node _T_210 = or(_T_209, _T_185)
node _T_211 = or(_T_210, _T_192)
node _T_212 = or(_T_211, _T_199)
node _T_213 = or(_T_101, _T_212)
node _T_214 = asUInt(reset)
node _T_215 = eq(_T_214, UInt<1>(0h0))
when _T_215 :
node _T_216 = eq(_T_213, UInt<1>(0h0))
when _T_216 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3
assert(clock, _T_213, UInt<1>(0h1), "") : assert_3
node _T_217 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3))
node _T_218 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_219 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_220 = and(_T_218, _T_219)
node _T_221 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_222 = and(_T_220, _T_221)
node _T_223 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_224 = and(_T_222, _T_223)
node _T_225 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_226 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_227 = and(_T_225, _T_226)
node _T_228 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_229 = and(_T_227, _T_228)
node _T_230 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_231 = and(_T_229, _T_230)
node _T_232 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_233 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_234 = and(_T_232, _T_233)
node _T_235 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_236 = and(_T_234, _T_235)
node _T_237 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_238 = and(_T_236, _T_237)
node _T_239 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_240 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_241 = and(_T_239, _T_240)
node _T_242 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_243 = and(_T_241, _T_242)
node _T_244 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_245 = and(_T_243, _T_244)
node _T_246 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_247 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_248 = and(_T_246, _T_247)
node _T_249 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_250 = and(_T_248, _T_249)
node _T_251 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_252 = and(_T_250, _T_251)
node _T_253 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_254 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0he))
node _T_255 = and(_T_253, _T_254)
node _T_256 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_257 = and(_T_255, _T_256)
node _T_258 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_259 = and(_T_257, _T_258)
node _T_260 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_261 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_262 = and(_T_260, _T_261)
node _T_263 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_264 = and(_T_262, _T_263)
node _T_265 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_266 = and(_T_264, _T_265)
node _T_267 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_268 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_269 = and(_T_267, _T_268)
node _T_270 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_271 = and(_T_269, _T_270)
node _T_272 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_273 = and(_T_271, _T_272)
node _T_274 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_275 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4))
node _T_276 = and(_T_274, _T_275)
node _T_277 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_278 = and(_T_276, _T_277)
node _T_279 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_280 = and(_T_278, _T_279)
node _T_281 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_282 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_283 = and(_T_281, _T_282)
node _T_284 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_285 = and(_T_283, _T_284)
node _T_286 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_287 = and(_T_285, _T_286)
node _T_288 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_289 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_290 = and(_T_288, _T_289)
node _T_291 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_292 = and(_T_290, _T_291)
node _T_293 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_294 = and(_T_292, _T_293)
node _T_295 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_296 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_297 = and(_T_295, _T_296)
node _T_298 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_299 = and(_T_297, _T_298)
node _T_300 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_301 = and(_T_299, _T_300)
node _T_302 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_303 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_304 = and(_T_302, _T_303)
node _T_305 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_306 = and(_T_304, _T_305)
node _T_307 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_308 = and(_T_306, _T_307)
node _T_309 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_310 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_311 = and(_T_309, _T_310)
node _T_312 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_313 = and(_T_311, _T_312)
node _T_314 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_315 = and(_T_313, _T_314)
node _T_316 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_317 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_318 = and(_T_316, _T_317)
node _T_319 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_320 = and(_T_318, _T_319)
node _T_321 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_322 = and(_T_320, _T_321)
node _T_323 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_324 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_325 = and(_T_323, _T_324)
node _T_326 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_327 = and(_T_325, _T_326)
node _T_328 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_329 = and(_T_327, _T_328)
node _T_330 = or(_T_224, _T_231)
node _T_331 = or(_T_330, _T_238)
node _T_332 = or(_T_331, _T_245)
node _T_333 = or(_T_332, _T_252)
node _T_334 = or(_T_333, _T_259)
node _T_335 = or(_T_334, _T_266)
node _T_336 = or(_T_335, _T_273)
node _T_337 = or(_T_336, _T_280)
node _T_338 = or(_T_337, _T_287)
node _T_339 = or(_T_338, _T_294)
node _T_340 = or(_T_339, _T_301)
node _T_341 = or(_T_340, _T_308)
node _T_342 = or(_T_341, _T_315)
node _T_343 = or(_T_342, _T_322)
node _T_344 = or(_T_343, _T_329)
node _T_345 = or(_T_217, _T_344)
node _T_346 = asUInt(reset)
node _T_347 = eq(_T_346, UInt<1>(0h0))
when _T_347 :
node _T_348 = eq(_T_345, UInt<1>(0h0))
when _T_348 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4
assert(clock, _T_345, UInt<1>(0h1), "") : assert_4
node _T_349 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4))
node _T_350 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_351 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_352 = and(_T_350, _T_351)
node _T_353 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_354 = and(_T_352, _T_353)
node _T_355 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_356 = and(_T_354, _T_355)
node _T_357 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_358 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_359 = and(_T_357, _T_358)
node _T_360 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_361 = and(_T_359, _T_360)
node _T_362 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_363 = and(_T_361, _T_362)
node _T_364 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_365 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_366 = and(_T_364, _T_365)
node _T_367 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_368 = and(_T_366, _T_367)
node _T_369 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_370 = and(_T_368, _T_369)
node _T_371 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_372 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_373 = and(_T_371, _T_372)
node _T_374 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_375 = and(_T_373, _T_374)
node _T_376 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_377 = and(_T_375, _T_376)
node _T_378 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_379 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_380 = and(_T_378, _T_379)
node _T_381 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_382 = and(_T_380, _T_381)
node _T_383 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_384 = and(_T_382, _T_383)
node _T_385 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_386 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_387 = and(_T_385, _T_386)
node _T_388 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_389 = and(_T_387, _T_388)
node _T_390 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_391 = and(_T_389, _T_390)
node _T_392 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_393 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_394 = and(_T_392, _T_393)
node _T_395 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_396 = and(_T_394, _T_395)
node _T_397 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_398 = and(_T_396, _T_397)
node _T_399 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_400 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_401 = and(_T_399, _T_400)
node _T_402 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_403 = and(_T_401, _T_402)
node _T_404 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_405 = and(_T_403, _T_404)
node _T_406 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_407 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0he))
node _T_408 = and(_T_406, _T_407)
node _T_409 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_410 = and(_T_408, _T_409)
node _T_411 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_412 = and(_T_410, _T_411)
node _T_413 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_414 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_415 = and(_T_413, _T_414)
node _T_416 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_417 = and(_T_415, _T_416)
node _T_418 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_419 = and(_T_417, _T_418)
node _T_420 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_421 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_422 = and(_T_420, _T_421)
node _T_423 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_424 = and(_T_422, _T_423)
node _T_425 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_426 = and(_T_424, _T_425)
node _T_427 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_428 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4))
node _T_429 = and(_T_427, _T_428)
node _T_430 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_431 = and(_T_429, _T_430)
node _T_432 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_433 = and(_T_431, _T_432)
node _T_434 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_435 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_436 = and(_T_434, _T_435)
node _T_437 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_438 = and(_T_436, _T_437)
node _T_439 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_440 = and(_T_438, _T_439)
node _T_441 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_442 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_443 = and(_T_441, _T_442)
node _T_444 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_445 = and(_T_443, _T_444)
node _T_446 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_447 = and(_T_445, _T_446)
node _T_448 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_449 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_450 = and(_T_448, _T_449)
node _T_451 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_452 = and(_T_450, _T_451)
node _T_453 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_454 = and(_T_452, _T_453)
node _T_455 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_456 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_457 = and(_T_455, _T_456)
node _T_458 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_459 = and(_T_457, _T_458)
node _T_460 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_461 = and(_T_459, _T_460)
node _T_462 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_463 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_464 = and(_T_462, _T_463)
node _T_465 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_466 = and(_T_464, _T_465)
node _T_467 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_468 = and(_T_466, _T_467)
node _T_469 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_470 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_471 = and(_T_469, _T_470)
node _T_472 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_473 = and(_T_471, _T_472)
node _T_474 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_475 = and(_T_473, _T_474)
node _T_476 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_477 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_478 = and(_T_476, _T_477)
node _T_479 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_480 = and(_T_478, _T_479)
node _T_481 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_482 = and(_T_480, _T_481)
node _T_483 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_484 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_485 = and(_T_483, _T_484)
node _T_486 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_487 = and(_T_485, _T_486)
node _T_488 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_489 = and(_T_487, _T_488)
node _T_490 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_491 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_492 = and(_T_490, _T_491)
node _T_493 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_494 = and(_T_492, _T_493)
node _T_495 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_496 = and(_T_494, _T_495)
node _T_497 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_498 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_499 = and(_T_497, _T_498)
node _T_500 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_501 = and(_T_499, _T_500)
node _T_502 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_503 = and(_T_501, _T_502)
node _T_504 = or(_T_356, _T_363)
node _T_505 = or(_T_504, _T_370)
node _T_506 = or(_T_505, _T_377)
node _T_507 = or(_T_506, _T_384)
node _T_508 = or(_T_507, _T_391)
node _T_509 = or(_T_508, _T_398)
node _T_510 = or(_T_509, _T_405)
node _T_511 = or(_T_510, _T_412)
node _T_512 = or(_T_511, _T_419)
node _T_513 = or(_T_512, _T_426)
node _T_514 = or(_T_513, _T_433)
node _T_515 = or(_T_514, _T_440)
node _T_516 = or(_T_515, _T_447)
node _T_517 = or(_T_516, _T_454)
node _T_518 = or(_T_517, _T_461)
node _T_519 = or(_T_518, _T_468)
node _T_520 = or(_T_519, _T_475)
node _T_521 = or(_T_520, _T_482)
node _T_522 = or(_T_521, _T_489)
node _T_523 = or(_T_522, _T_496)
node _T_524 = or(_T_523, _T_503)
node _T_525 = or(_T_349, _T_524)
node _T_526 = asUInt(reset)
node _T_527 = eq(_T_526, UInt<1>(0h0))
when _T_527 :
node _T_528 = eq(_T_525, UInt<1>(0h0))
when _T_528 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5
assert(clock, _T_525, UInt<1>(0h1), "") : assert_5
node _T_529 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5))
node _T_530 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_531 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_532 = and(_T_530, _T_531)
node _T_533 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_534 = and(_T_532, _T_533)
node _T_535 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_536 = and(_T_534, _T_535)
node _T_537 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_538 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_539 = and(_T_537, _T_538)
node _T_540 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_541 = and(_T_539, _T_540)
node _T_542 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_543 = and(_T_541, _T_542)
node _T_544 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_545 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_546 = and(_T_544, _T_545)
node _T_547 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_548 = and(_T_546, _T_547)
node _T_549 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_550 = and(_T_548, _T_549)
node _T_551 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_552 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_553 = and(_T_551, _T_552)
node _T_554 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_555 = and(_T_553, _T_554)
node _T_556 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_557 = and(_T_555, _T_556)
node _T_558 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_559 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_560 = and(_T_558, _T_559)
node _T_561 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_562 = and(_T_560, _T_561)
node _T_563 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_564 = and(_T_562, _T_563)
node _T_565 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_566 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_567 = and(_T_565, _T_566)
node _T_568 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_569 = and(_T_567, _T_568)
node _T_570 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_571 = and(_T_569, _T_570)
node _T_572 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_573 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_574 = and(_T_572, _T_573)
node _T_575 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_576 = and(_T_574, _T_575)
node _T_577 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_578 = and(_T_576, _T_577)
node _T_579 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_580 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_581 = and(_T_579, _T_580)
node _T_582 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_583 = and(_T_581, _T_582)
node _T_584 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_585 = and(_T_583, _T_584)
node _T_586 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_587 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_588 = and(_T_586, _T_587)
node _T_589 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_590 = and(_T_588, _T_589)
node _T_591 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_592 = and(_T_590, _T_591)
node _T_593 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_594 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0he))
node _T_595 = and(_T_593, _T_594)
node _T_596 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_597 = and(_T_595, _T_596)
node _T_598 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_599 = and(_T_597, _T_598)
node _T_600 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_601 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_602 = and(_T_600, _T_601)
node _T_603 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_604 = and(_T_602, _T_603)
node _T_605 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_606 = and(_T_604, _T_605)
node _T_607 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_608 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_609 = and(_T_607, _T_608)
node _T_610 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_611 = and(_T_609, _T_610)
node _T_612 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_613 = and(_T_611, _T_612)
node _T_614 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_615 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4))
node _T_616 = and(_T_614, _T_615)
node _T_617 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_618 = and(_T_616, _T_617)
node _T_619 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_620 = and(_T_618, _T_619)
node _T_621 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_622 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_623 = and(_T_621, _T_622)
node _T_624 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_625 = and(_T_623, _T_624)
node _T_626 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_627 = and(_T_625, _T_626)
node _T_628 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_629 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_630 = and(_T_628, _T_629)
node _T_631 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_632 = and(_T_630, _T_631)
node _T_633 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_634 = and(_T_632, _T_633)
node _T_635 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_636 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_637 = and(_T_635, _T_636)
node _T_638 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_639 = and(_T_637, _T_638)
node _T_640 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_641 = and(_T_639, _T_640)
node _T_642 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_643 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_644 = and(_T_642, _T_643)
node _T_645 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_646 = and(_T_644, _T_645)
node _T_647 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_648 = and(_T_646, _T_647)
node _T_649 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_650 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_651 = and(_T_649, _T_650)
node _T_652 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_653 = and(_T_651, _T_652)
node _T_654 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_655 = and(_T_653, _T_654)
node _T_656 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_657 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_658 = and(_T_656, _T_657)
node _T_659 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_660 = and(_T_658, _T_659)
node _T_661 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_662 = and(_T_660, _T_661)
node _T_663 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_664 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_665 = and(_T_663, _T_664)
node _T_666 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_667 = and(_T_665, _T_666)
node _T_668 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_669 = and(_T_667, _T_668)
node _T_670 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_671 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_672 = and(_T_670, _T_671)
node _T_673 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_674 = and(_T_672, _T_673)
node _T_675 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_676 = and(_T_674, _T_675)
node _T_677 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_678 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_679 = and(_T_677, _T_678)
node _T_680 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_681 = and(_T_679, _T_680)
node _T_682 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_683 = and(_T_681, _T_682)
node _T_684 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_685 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_686 = and(_T_684, _T_685)
node _T_687 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_688 = and(_T_686, _T_687)
node _T_689 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_690 = and(_T_688, _T_689)
node _T_691 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_692 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_693 = and(_T_691, _T_692)
node _T_694 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_695 = and(_T_693, _T_694)
node _T_696 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_697 = and(_T_695, _T_696)
node _T_698 = or(_T_536, _T_543)
node _T_699 = or(_T_698, _T_550)
node _T_700 = or(_T_699, _T_557)
node _T_701 = or(_T_700, _T_564)
node _T_702 = or(_T_701, _T_571)
node _T_703 = or(_T_702, _T_578)
node _T_704 = or(_T_703, _T_585)
node _T_705 = or(_T_704, _T_592)
node _T_706 = or(_T_705, _T_599)
node _T_707 = or(_T_706, _T_606)
node _T_708 = or(_T_707, _T_613)
node _T_709 = or(_T_708, _T_620)
node _T_710 = or(_T_709, _T_627)
node _T_711 = or(_T_710, _T_634)
node _T_712 = or(_T_711, _T_641)
node _T_713 = or(_T_712, _T_648)
node _T_714 = or(_T_713, _T_655)
node _T_715 = or(_T_714, _T_662)
node _T_716 = or(_T_715, _T_669)
node _T_717 = or(_T_716, _T_676)
node _T_718 = or(_T_717, _T_683)
node _T_719 = or(_T_718, _T_690)
node _T_720 = or(_T_719, _T_697)
node _T_721 = or(_T_529, _T_720)
node _T_722 = asUInt(reset)
node _T_723 = eq(_T_722, UInt<1>(0h0))
when _T_723 :
node _T_724 = eq(_T_721, UInt<1>(0h0))
when _T_724 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_6
assert(clock, _T_721, UInt<1>(0h1), "") : assert_6
node _T_725 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h6))
node _T_726 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_727 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_728 = and(_T_726, _T_727)
node _T_729 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_730 = and(_T_728, _T_729)
node _T_731 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_732 = and(_T_730, _T_731)
node _T_733 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_734 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_735 = and(_T_733, _T_734)
node _T_736 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_737 = and(_T_735, _T_736)
node _T_738 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_739 = and(_T_737, _T_738)
node _T_740 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_741 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_742 = and(_T_740, _T_741)
node _T_743 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_744 = and(_T_742, _T_743)
node _T_745 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_746 = and(_T_744, _T_745)
node _T_747 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_748 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_749 = and(_T_747, _T_748)
node _T_750 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_751 = and(_T_749, _T_750)
node _T_752 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_753 = and(_T_751, _T_752)
node _T_754 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_755 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_756 = and(_T_754, _T_755)
node _T_757 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_758 = and(_T_756, _T_757)
node _T_759 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_760 = and(_T_758, _T_759)
node _T_761 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_762 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_763 = and(_T_761, _T_762)
node _T_764 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_765 = and(_T_763, _T_764)
node _T_766 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_767 = and(_T_765, _T_766)
node _T_768 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_769 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_770 = and(_T_768, _T_769)
node _T_771 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_772 = and(_T_770, _T_771)
node _T_773 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_774 = and(_T_772, _T_773)
node _T_775 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_776 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_777 = and(_T_775, _T_776)
node _T_778 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_779 = and(_T_777, _T_778)
node _T_780 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_781 = and(_T_779, _T_780)
node _T_782 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_783 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_784 = and(_T_782, _T_783)
node _T_785 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_786 = and(_T_784, _T_785)
node _T_787 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_788 = and(_T_786, _T_787)
node _T_789 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_790 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0he))
node _T_791 = and(_T_789, _T_790)
node _T_792 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_793 = and(_T_791, _T_792)
node _T_794 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_795 = and(_T_793, _T_794)
node _T_796 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_797 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_798 = and(_T_796, _T_797)
node _T_799 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_800 = and(_T_798, _T_799)
node _T_801 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_802 = and(_T_800, _T_801)
node _T_803 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_804 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_805 = and(_T_803, _T_804)
node _T_806 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_807 = and(_T_805, _T_806)
node _T_808 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_809 = and(_T_807, _T_808)
node _T_810 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_811 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4))
node _T_812 = and(_T_810, _T_811)
node _T_813 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_814 = and(_T_812, _T_813)
node _T_815 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_816 = and(_T_814, _T_815)
node _T_817 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_818 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_819 = and(_T_817, _T_818)
node _T_820 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_821 = and(_T_819, _T_820)
node _T_822 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_823 = and(_T_821, _T_822)
node _T_824 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_825 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_826 = and(_T_824, _T_825)
node _T_827 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_828 = and(_T_826, _T_827)
node _T_829 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_830 = and(_T_828, _T_829)
node _T_831 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_832 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_833 = and(_T_831, _T_832)
node _T_834 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_835 = and(_T_833, _T_834)
node _T_836 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_837 = and(_T_835, _T_836)
node _T_838 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_839 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_840 = and(_T_838, _T_839)
node _T_841 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_842 = and(_T_840, _T_841)
node _T_843 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_844 = and(_T_842, _T_843)
node _T_845 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_846 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_847 = and(_T_845, _T_846)
node _T_848 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_849 = and(_T_847, _T_848)
node _T_850 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_851 = and(_T_849, _T_850)
node _T_852 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_853 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_854 = and(_T_852, _T_853)
node _T_855 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_856 = and(_T_854, _T_855)
node _T_857 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_858 = and(_T_856, _T_857)
node _T_859 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_860 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_861 = and(_T_859, _T_860)
node _T_862 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_863 = and(_T_861, _T_862)
node _T_864 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_865 = and(_T_863, _T_864)
node _T_866 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_867 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_868 = and(_T_866, _T_867)
node _T_869 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_870 = and(_T_868, _T_869)
node _T_871 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_872 = and(_T_870, _T_871)
node _T_873 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_874 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_875 = and(_T_873, _T_874)
node _T_876 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_877 = and(_T_875, _T_876)
node _T_878 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_879 = and(_T_877, _T_878)
node _T_880 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_881 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_882 = and(_T_880, _T_881)
node _T_883 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_884 = and(_T_882, _T_883)
node _T_885 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_886 = and(_T_884, _T_885)
node _T_887 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_888 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_889 = and(_T_887, _T_888)
node _T_890 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_891 = and(_T_889, _T_890)
node _T_892 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_893 = and(_T_891, _T_892)
node _T_894 = or(_T_732, _T_739)
node _T_895 = or(_T_894, _T_746)
node _T_896 = or(_T_895, _T_753)
node _T_897 = or(_T_896, _T_760)
node _T_898 = or(_T_897, _T_767)
node _T_899 = or(_T_898, _T_774)
node _T_900 = or(_T_899, _T_781)
node _T_901 = or(_T_900, _T_788)
node _T_902 = or(_T_901, _T_795)
node _T_903 = or(_T_902, _T_802)
node _T_904 = or(_T_903, _T_809)
node _T_905 = or(_T_904, _T_816)
node _T_906 = or(_T_905, _T_823)
node _T_907 = or(_T_906, _T_830)
node _T_908 = or(_T_907, _T_837)
node _T_909 = or(_T_908, _T_844)
node _T_910 = or(_T_909, _T_851)
node _T_911 = or(_T_910, _T_858)
node _T_912 = or(_T_911, _T_865)
node _T_913 = or(_T_912, _T_872)
node _T_914 = or(_T_913, _T_879)
node _T_915 = or(_T_914, _T_886)
node _T_916 = or(_T_915, _T_893)
node _T_917 = or(_T_725, _T_916)
node _T_918 = asUInt(reset)
node _T_919 = eq(_T_918, UInt<1>(0h0))
when _T_919 :
node _T_920 = eq(_T_917, UInt<1>(0h0))
when _T_920 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_7
assert(clock, _T_917, UInt<1>(0h1), "") : assert_7
node _T_921 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h7))
node _T_922 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_923 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_924 = and(_T_922, _T_923)
node _T_925 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_926 = and(_T_924, _T_925)
node _T_927 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_928 = and(_T_926, _T_927)
node _T_929 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_930 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_931 = and(_T_929, _T_930)
node _T_932 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_933 = and(_T_931, _T_932)
node _T_934 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_935 = and(_T_933, _T_934)
node _T_936 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_937 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_938 = and(_T_936, _T_937)
node _T_939 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_940 = and(_T_938, _T_939)
node _T_941 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_942 = and(_T_940, _T_941)
node _T_943 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_944 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_945 = and(_T_943, _T_944)
node _T_946 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_947 = and(_T_945, _T_946)
node _T_948 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_949 = and(_T_947, _T_948)
node _T_950 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_951 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_952 = and(_T_950, _T_951)
node _T_953 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_954 = and(_T_952, _T_953)
node _T_955 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_956 = and(_T_954, _T_955)
node _T_957 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_958 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_959 = and(_T_957, _T_958)
node _T_960 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_961 = and(_T_959, _T_960)
node _T_962 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_963 = and(_T_961, _T_962)
node _T_964 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_965 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_966 = and(_T_964, _T_965)
node _T_967 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_968 = and(_T_966, _T_967)
node _T_969 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_970 = and(_T_968, _T_969)
node _T_971 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_972 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_973 = and(_T_971, _T_972)
node _T_974 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_975 = and(_T_973, _T_974)
node _T_976 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_977 = and(_T_975, _T_976)
node _T_978 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_979 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_980 = and(_T_978, _T_979)
node _T_981 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_982 = and(_T_980, _T_981)
node _T_983 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_984 = and(_T_982, _T_983)
node _T_985 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_986 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0he))
node _T_987 = and(_T_985, _T_986)
node _T_988 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_989 = and(_T_987, _T_988)
node _T_990 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_991 = and(_T_989, _T_990)
node _T_992 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_993 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_994 = and(_T_992, _T_993)
node _T_995 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_996 = and(_T_994, _T_995)
node _T_997 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_998 = and(_T_996, _T_997)
node _T_999 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_1000 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_1001 = and(_T_999, _T_1000)
node _T_1002 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_1003 = and(_T_1001, _T_1002)
node _T_1004 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_1005 = and(_T_1003, _T_1004)
node _T_1006 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_1007 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4))
node _T_1008 = and(_T_1006, _T_1007)
node _T_1009 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_1010 = and(_T_1008, _T_1009)
node _T_1011 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_1012 = and(_T_1010, _T_1011)
node _T_1013 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_1014 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_1015 = and(_T_1013, _T_1014)
node _T_1016 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_1017 = and(_T_1015, _T_1016)
node _T_1018 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_1019 = and(_T_1017, _T_1018)
node _T_1020 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_1021 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_1022 = and(_T_1020, _T_1021)
node _T_1023 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_1024 = and(_T_1022, _T_1023)
node _T_1025 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_1026 = and(_T_1024, _T_1025)
node _T_1027 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_1028 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_1029 = and(_T_1027, _T_1028)
node _T_1030 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_1031 = and(_T_1029, _T_1030)
node _T_1032 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_1033 = and(_T_1031, _T_1032)
node _T_1034 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_1035 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_1036 = and(_T_1034, _T_1035)
node _T_1037 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_1038 = and(_T_1036, _T_1037)
node _T_1039 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_1040 = and(_T_1038, _T_1039)
node _T_1041 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_1042 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_1043 = and(_T_1041, _T_1042)
node _T_1044 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_1045 = and(_T_1043, _T_1044)
node _T_1046 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_1047 = and(_T_1045, _T_1046)
node _T_1048 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_1049 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_1050 = and(_T_1048, _T_1049)
node _T_1051 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_1052 = and(_T_1050, _T_1051)
node _T_1053 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_1054 = and(_T_1052, _T_1053)
node _T_1055 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_1056 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_1057 = and(_T_1055, _T_1056)
node _T_1058 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_1059 = and(_T_1057, _T_1058)
node _T_1060 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_1061 = and(_T_1059, _T_1060)
node _T_1062 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_1063 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_1064 = and(_T_1062, _T_1063)
node _T_1065 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_1066 = and(_T_1064, _T_1065)
node _T_1067 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_1068 = and(_T_1066, _T_1067)
node _T_1069 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_1070 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_1071 = and(_T_1069, _T_1070)
node _T_1072 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_1073 = and(_T_1071, _T_1072)
node _T_1074 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_1075 = and(_T_1073, _T_1074)
node _T_1076 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_1077 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_1078 = and(_T_1076, _T_1077)
node _T_1079 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_1080 = and(_T_1078, _T_1079)
node _T_1081 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_1082 = and(_T_1080, _T_1081)
node _T_1083 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_1084 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_1085 = and(_T_1083, _T_1084)
node _T_1086 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_1087 = and(_T_1085, _T_1086)
node _T_1088 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_1089 = and(_T_1087, _T_1088)
node _T_1090 = or(_T_928, _T_935)
node _T_1091 = or(_T_1090, _T_942)
node _T_1092 = or(_T_1091, _T_949)
node _T_1093 = or(_T_1092, _T_956)
node _T_1094 = or(_T_1093, _T_963)
node _T_1095 = or(_T_1094, _T_970)
node _T_1096 = or(_T_1095, _T_977)
node _T_1097 = or(_T_1096, _T_984)
node _T_1098 = or(_T_1097, _T_991)
node _T_1099 = or(_T_1098, _T_998)
node _T_1100 = or(_T_1099, _T_1005)
node _T_1101 = or(_T_1100, _T_1012)
node _T_1102 = or(_T_1101, _T_1019)
node _T_1103 = or(_T_1102, _T_1026)
node _T_1104 = or(_T_1103, _T_1033)
node _T_1105 = or(_T_1104, _T_1040)
node _T_1106 = or(_T_1105, _T_1047)
node _T_1107 = or(_T_1106, _T_1054)
node _T_1108 = or(_T_1107, _T_1061)
node _T_1109 = or(_T_1108, _T_1068)
node _T_1110 = or(_T_1109, _T_1075)
node _T_1111 = or(_T_1110, _T_1082)
node _T_1112 = or(_T_1111, _T_1089)
node _T_1113 = or(_T_921, _T_1112)
node _T_1114 = asUInt(reset)
node _T_1115 = eq(_T_1114, UInt<1>(0h0))
when _T_1115 :
node _T_1116 = eq(_T_1113, UInt<1>(0h0))
when _T_1116 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_8
assert(clock, _T_1113, UInt<1>(0h1), "") : assert_8 | module NoCMonitor_38( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26]
reg in_flight_2; // @[Monitor.scala:16:26]
reg in_flight_3; // @[Monitor.scala:16:26]
reg in_flight_4; // @[Monitor.scala:16:26]
reg in_flight_5; // @[Monitor.scala:16:26]
reg in_flight_6; // @[Monitor.scala:16:26]
reg in_flight_7; // @[Monitor.scala:16:26] |
Generate the Verilog code corresponding to this FIRRTL code module BreakpointUnit_5 :
input clock : Clock
input reset : Reset
output io : { flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}[0], flip pc : UInt<39>, flip ea : UInt<39>, flip mcontext : UInt<0>, flip scontext : UInt<0>, xcpt_if : UInt<1>, xcpt_ld : UInt<1>, xcpt_st : UInt<1>, debug_if : UInt<1>, debug_ld : UInt<1>, debug_st : UInt<1>, bpwatch : { valid : UInt<1>[1], rvalid : UInt<1>[1], wvalid : UInt<1>[1], ivalid : UInt<1>[1], action : UInt<3>}[0]}
connect io.xcpt_if, UInt<1>(0h0)
connect io.xcpt_ld, UInt<1>(0h0)
connect io.xcpt_st, UInt<1>(0h0)
connect io.debug_if, UInt<1>(0h0)
connect io.debug_ld, UInt<1>(0h0)
connect io.debug_st, UInt<1>(0h0) | module BreakpointUnit_5( // @[Breakpoint.scala:79:7]
input clock, // @[Breakpoint.scala:79:7]
input reset, // @[Breakpoint.scala:79:7]
input io_status_debug, // @[Breakpoint.scala:80:14]
input io_status_cease, // @[Breakpoint.scala:80:14]
input io_status_wfi, // @[Breakpoint.scala:80:14]
input [1:0] io_status_dprv, // @[Breakpoint.scala:80:14]
input io_status_dv, // @[Breakpoint.scala:80:14]
input [1:0] io_status_prv, // @[Breakpoint.scala:80:14]
input io_status_v, // @[Breakpoint.scala:80:14]
input io_status_sd, // @[Breakpoint.scala:80:14]
input io_status_mpv, // @[Breakpoint.scala:80:14]
input io_status_gva, // @[Breakpoint.scala:80:14]
input io_status_tsr, // @[Breakpoint.scala:80:14]
input io_status_tw, // @[Breakpoint.scala:80:14]
input io_status_tvm, // @[Breakpoint.scala:80:14]
input io_status_mxr, // @[Breakpoint.scala:80:14]
input io_status_sum, // @[Breakpoint.scala:80:14]
input io_status_mprv, // @[Breakpoint.scala:80:14]
input [1:0] io_status_fs, // @[Breakpoint.scala:80:14]
input [1:0] io_status_mpp, // @[Breakpoint.scala:80:14]
input io_status_spp, // @[Breakpoint.scala:80:14]
input io_status_mpie, // @[Breakpoint.scala:80:14]
input io_status_spie, // @[Breakpoint.scala:80:14]
input io_status_mie, // @[Breakpoint.scala:80:14]
input io_status_sie, // @[Breakpoint.scala:80:14]
input [38:0] io_pc // @[Breakpoint.scala:80:14]
);
wire io_status_debug_0 = io_status_debug; // @[Breakpoint.scala:79:7]
wire io_status_cease_0 = io_status_cease; // @[Breakpoint.scala:79:7]
wire io_status_wfi_0 = io_status_wfi; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_dprv_0 = io_status_dprv; // @[Breakpoint.scala:79:7]
wire io_status_dv_0 = io_status_dv; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_prv_0 = io_status_prv; // @[Breakpoint.scala:79:7]
wire io_status_v_0 = io_status_v; // @[Breakpoint.scala:79:7]
wire io_status_sd_0 = io_status_sd; // @[Breakpoint.scala:79:7]
wire io_status_mpv_0 = io_status_mpv; // @[Breakpoint.scala:79:7]
wire io_status_gva_0 = io_status_gva; // @[Breakpoint.scala:79:7]
wire io_status_tsr_0 = io_status_tsr; // @[Breakpoint.scala:79:7]
wire io_status_tw_0 = io_status_tw; // @[Breakpoint.scala:79:7]
wire io_status_tvm_0 = io_status_tvm; // @[Breakpoint.scala:79:7]
wire io_status_mxr_0 = io_status_mxr; // @[Breakpoint.scala:79:7]
wire io_status_sum_0 = io_status_sum; // @[Breakpoint.scala:79:7]
wire io_status_mprv_0 = io_status_mprv; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_fs_0 = io_status_fs; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_mpp_0 = io_status_mpp; // @[Breakpoint.scala:79:7]
wire io_status_spp_0 = io_status_spp; // @[Breakpoint.scala:79:7]
wire io_status_mpie_0 = io_status_mpie; // @[Breakpoint.scala:79:7]
wire io_status_spie_0 = io_status_spie; // @[Breakpoint.scala:79:7]
wire io_status_mie_0 = io_status_mie; // @[Breakpoint.scala:79:7]
wire io_status_sie_0 = io_status_sie; // @[Breakpoint.scala:79:7]
wire [38:0] io_pc_0 = io_pc; // @[Breakpoint.scala:79:7]
wire [38:0] io_ea = 39'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_sxl = 2'h2; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_uxl = 2'h2; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_xs = 2'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_vs = 2'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [7:0] io_status_zero1 = 8'h0; // @[Breakpoint.scala:79:7, :80:14]
wire io_status_mbe = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_sbe = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_sd_rv32 = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_ube = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_upie = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_hie = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_uie = 1'h0; // @[Breakpoint.scala:79:7]
wire io_xcpt_if = 1'h0; // @[Breakpoint.scala:79:7]
wire io_xcpt_ld = 1'h0; // @[Breakpoint.scala:79:7]
wire io_xcpt_st = 1'h0; // @[Breakpoint.scala:79:7]
wire io_debug_if = 1'h0; // @[Breakpoint.scala:79:7]
wire io_debug_ld = 1'h0; // @[Breakpoint.scala:79:7]
wire io_debug_st = 1'h0; // @[Breakpoint.scala:79:7]
wire [22:0] io_status_zero2 = 23'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [31:0] io_status_isa = 32'h14112D; // @[Breakpoint.scala:79:7, :80:14]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module LoopConvLdBias :
input clock : Clock
input reset : Reset
output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { outer_bounds : { batch_size : UInt<16>, in_row_dim : UInt<16>, in_col_dim : UInt<16>, in_channels : UInt<16>, out_channels : UInt<16>, out_col_dim : UInt<16>, out_row_dim : UInt<16>, out_stride : UInt<16>, in_stride : UInt<16>, weight_stride : UInt<16>, pool_out_row_dim : UInt<16>, pool_out_col_dim : UInt<16>, stride : UInt<16>, padding : UInt<16>, kernel_dim : UInt<16>, kernel_dilation : UInt<16>, pool_size : UInt<16>, pool_stride : UInt<16>, pool_padding : UInt<16>}, inner_bounds : { batches : UInt<16>, porows : UInt<16>, pocols : UInt<16>, pochs : UInt<16>, krows : UInt<16>, kcols : UInt<16>, kchs : UInt<16>, lpad : UInt<16>, rpad : UInt<16>, upad : UInt<16>, dpad : UInt<16>, plpad : UInt<16>, prad : UInt<16>, pupad : UInt<16>, pdpad : UInt<16>, orows : UInt<16>, ocols : UInt<16>}, derived_params : { ochs : UInt<16>, irows : UInt<16>, icols : UInt<16>, irows_unpadded : UInt<16>, icols_unpadded : UInt<16>, ichs : UInt<16>, out_channels_per_bank : UInt<16>, in_channels_per_bank : UInt<16>, bias_spad_stride : UInt<16>, input_spad_stride : UInt<16>, weight_spad_stride : UInt<16>}, addr_start : UInt<12>, dram_addr : UInt<40>, no_bias : UInt<1>, loop_id : UInt<1>}}, cmd : { flip ready : UInt<1>, valid : UInt<1>, bits : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}}, idle : UInt<1>, flip rob_overloaded : UInt<1>, flip wait_for_prev_loop : UInt<1>, loop_id : UInt<1>}
regreset state : UInt<2>, clock, reset, UInt<1>(0h0)
reg req : { outer_bounds : { batch_size : UInt<16>, in_row_dim : UInt<16>, in_col_dim : UInt<16>, in_channels : UInt<16>, out_channels : UInt<16>, out_col_dim : UInt<16>, out_row_dim : UInt<16>, out_stride : UInt<16>, in_stride : UInt<16>, weight_stride : UInt<16>, pool_out_row_dim : UInt<16>, pool_out_col_dim : UInt<16>, stride : UInt<16>, padding : UInt<16>, kernel_dim : UInt<16>, kernel_dilation : UInt<16>, pool_size : UInt<16>, pool_stride : UInt<16>, pool_padding : UInt<16>}, inner_bounds : { batches : UInt<16>, porows : UInt<16>, pocols : UInt<16>, pochs : UInt<16>, krows : UInt<16>, kcols : UInt<16>, kchs : UInt<16>, lpad : UInt<16>, rpad : UInt<16>, upad : UInt<16>, dpad : UInt<16>, plpad : UInt<16>, prad : UInt<16>, pupad : UInt<16>, pdpad : UInt<16>, orows : UInt<16>, ocols : UInt<16>}, derived_params : { ochs : UInt<16>, irows : UInt<16>, icols : UInt<16>, irows_unpadded : UInt<16>, icols_unpadded : UInt<16>, ichs : UInt<16>, out_channels_per_bank : UInt<16>, in_channels_per_bank : UInt<16>, bias_spad_stride : UInt<16>, input_spad_stride : UInt<16>, weight_spad_stride : UInt<16>}, addr_start : UInt<12>, dram_addr : UInt<40>, no_bias : UInt<1>, loop_id : UInt<1>}, clock
node _max_ochs_per_mvin_T = lt(req.derived_params.ochs, UInt<5>(0h10))
node max_ochs_per_mvin = mux(_max_ochs_per_mvin_T, req.derived_params.ochs, UInt<5>(0h10))
node skip = eq(req.dram_addr, UInt<1>(0h0))
reg b : UInt<16>, clock
reg orow : UInt<16>, clock
reg ocol : UInt<16>, clock
reg och : UInt<16>, clock
node dram_offset = mul(och, UInt<3>(0h4))
node _dram_addr_T = and(dram_offset, UInt<32>(0hffffffff))
node _dram_addr_T_1 = add(req.dram_addr, _dram_addr_T)
node _dram_addr_T_2 = tail(_dram_addr_T_1, 1)
node dram_addr = mux(req.no_bias, UInt<1>(0h0), _dram_addr_T_2)
node _spad_addr_T = div(och, UInt<16>(0h4))
node _spad_addr_T_1 = mul(_spad_addr_T, req.inner_bounds.batches)
node _spad_addr_T_2 = mul(_spad_addr_T_1, req.inner_bounds.orows)
node _spad_addr_T_3 = mul(_spad_addr_T_2, req.inner_bounds.ocols)
node _spad_addr_T_4 = add(req.addr_start, _spad_addr_T_3)
node _spad_addr_T_5 = mul(b, req.inner_bounds.orows)
node _spad_addr_T_6 = mul(_spad_addr_T_5, req.inner_bounds.ocols)
node _spad_addr_T_7 = add(_spad_addr_T_4, _spad_addr_T_6)
node _spad_addr_T_8 = mul(orow, req.inner_bounds.ocols)
node _spad_addr_T_9 = add(_spad_addr_T_7, _spad_addr_T_8)
node spad_addr = add(_spad_addr_T_9, ocol)
node _I_T = sub(req.inner_bounds.ocols, ocol)
node _I_T_1 = tail(_I_T, 1)
node _I_T_2 = gt(_I_T_1, UInt<3>(0h4))
node _I_T_3 = sub(req.inner_bounds.ocols, ocol)
node _I_T_4 = tail(_I_T_3, 1)
node I = mux(_I_T_2, UInt<3>(0h4), _I_T_4)
node _J_T = sub(req.derived_params.ochs, och)
node _J_T_1 = tail(_J_T, 1)
node _J_T_2 = gt(_J_T_1, max_ochs_per_mvin)
node _J_T_3 = sub(req.derived_params.ochs, och)
node _J_T_4 = tail(_J_T_3, 1)
node J = mux(_J_T_2, max_ochs_per_mvin, _J_T_4)
inst command_p of Pipeline_11
connect command_p.clock, clock
connect command_p.reset, reset
wire config_cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}
invalidate config_cmd.status.uie
invalidate config_cmd.status.sie
invalidate config_cmd.status.hie
invalidate config_cmd.status.mie
invalidate config_cmd.status.upie
invalidate config_cmd.status.spie
invalidate config_cmd.status.ube
invalidate config_cmd.status.mpie
invalidate config_cmd.status.spp
invalidate config_cmd.status.vs
invalidate config_cmd.status.mpp
invalidate config_cmd.status.fs
invalidate config_cmd.status.xs
invalidate config_cmd.status.mprv
invalidate config_cmd.status.sum
invalidate config_cmd.status.mxr
invalidate config_cmd.status.tvm
invalidate config_cmd.status.tw
invalidate config_cmd.status.tsr
invalidate config_cmd.status.zero1
invalidate config_cmd.status.sd_rv32
invalidate config_cmd.status.uxl
invalidate config_cmd.status.sxl
invalidate config_cmd.status.sbe
invalidate config_cmd.status.mbe
invalidate config_cmd.status.gva
invalidate config_cmd.status.mpv
invalidate config_cmd.status.zero2
invalidate config_cmd.status.sd
invalidate config_cmd.status.v
invalidate config_cmd.status.prv
invalidate config_cmd.status.dv
invalidate config_cmd.status.dprv
invalidate config_cmd.status.isa
invalidate config_cmd.status.wfi
invalidate config_cmd.status.cease
invalidate config_cmd.status.debug
invalidate config_cmd.rs2
invalidate config_cmd.rs1
invalidate config_cmd.inst.opcode
invalidate config_cmd.inst.rd
invalidate config_cmd.inst.xs2
invalidate config_cmd.inst.xs1
invalidate config_cmd.inst.xd
invalidate config_cmd.inst.rs1
invalidate config_cmd.inst.rs2
invalidate config_cmd.inst.funct
connect config_cmd.inst.funct, UInt<1>(0h0)
wire config_cmd_rs1 : { _spacer3 : UInt<0>, scale : UInt<32>, _spacer2 : UInt<2>, stride : UInt<14>, _spacer1 : UInt<5>, pixel_repeats : UInt<3>, _spacer0 : UInt<3>, state_id : UInt<2>, shrink : UInt<1>, _unused : UInt<2>}
invalidate config_cmd_rs1._unused
invalidate config_cmd_rs1.shrink
invalidate config_cmd_rs1.state_id
invalidate config_cmd_rs1._spacer0
invalidate config_cmd_rs1.pixel_repeats
invalidate config_cmd_rs1._spacer1
invalidate config_cmd_rs1.stride
invalidate config_cmd_rs1._spacer2
invalidate config_cmd_rs1.scale
invalidate config_cmd_rs1._spacer3
connect config_cmd_rs1.scale, UInt<30>(0h3f800000)
connect config_cmd_rs1.stride, req.derived_params.bias_spad_stride
connect config_cmd_rs1.pixel_repeats, UInt<1>(0h1)
connect config_cmd_rs1.state_id, UInt<2>(0h2)
connect config_cmd_rs1.shrink, UInt<1>(0h0)
connect config_cmd_rs1._unused, UInt<1>(0h1)
node config_cmd_rs1_lo_lo = cat(config_cmd_rs1.shrink, config_cmd_rs1._unused)
node config_cmd_rs1_lo_hi_hi = cat(config_cmd_rs1.pixel_repeats, config_cmd_rs1._spacer0)
node config_cmd_rs1_lo_hi = cat(config_cmd_rs1_lo_hi_hi, config_cmd_rs1.state_id)
node config_cmd_rs1_lo = cat(config_cmd_rs1_lo_hi, config_cmd_rs1_lo_lo)
node config_cmd_rs1_hi_lo = cat(config_cmd_rs1.stride, config_cmd_rs1._spacer1)
node config_cmd_rs1_hi_hi_hi = cat(config_cmd_rs1._spacer3, config_cmd_rs1.scale)
node config_cmd_rs1_hi_hi = cat(config_cmd_rs1_hi_hi_hi, config_cmd_rs1._spacer2)
node config_cmd_rs1_hi = cat(config_cmd_rs1_hi_hi, config_cmd_rs1_hi_lo)
node _config_cmd_rs1_T = cat(config_cmd_rs1_hi, config_cmd_rs1_lo)
connect config_cmd.rs1, _config_cmd_rs1_T
connect config_cmd.rs2, UInt<1>(0h0)
wire mvin_cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}
invalidate mvin_cmd.status.uie
invalidate mvin_cmd.status.sie
invalidate mvin_cmd.status.hie
invalidate mvin_cmd.status.mie
invalidate mvin_cmd.status.upie
invalidate mvin_cmd.status.spie
invalidate mvin_cmd.status.ube
invalidate mvin_cmd.status.mpie
invalidate mvin_cmd.status.spp
invalidate mvin_cmd.status.vs
invalidate mvin_cmd.status.mpp
invalidate mvin_cmd.status.fs
invalidate mvin_cmd.status.xs
invalidate mvin_cmd.status.mprv
invalidate mvin_cmd.status.sum
invalidate mvin_cmd.status.mxr
invalidate mvin_cmd.status.tvm
invalidate mvin_cmd.status.tw
invalidate mvin_cmd.status.tsr
invalidate mvin_cmd.status.zero1
invalidate mvin_cmd.status.sd_rv32
invalidate mvin_cmd.status.uxl
invalidate mvin_cmd.status.sxl
invalidate mvin_cmd.status.sbe
invalidate mvin_cmd.status.mbe
invalidate mvin_cmd.status.gva
invalidate mvin_cmd.status.mpv
invalidate mvin_cmd.status.zero2
invalidate mvin_cmd.status.sd
invalidate mvin_cmd.status.v
invalidate mvin_cmd.status.prv
invalidate mvin_cmd.status.dv
invalidate mvin_cmd.status.dprv
invalidate mvin_cmd.status.isa
invalidate mvin_cmd.status.wfi
invalidate mvin_cmd.status.cease
invalidate mvin_cmd.status.debug
invalidate mvin_cmd.rs2
invalidate mvin_cmd.rs1
invalidate mvin_cmd.inst.opcode
invalidate mvin_cmd.inst.rd
invalidate mvin_cmd.inst.xs2
invalidate mvin_cmd.inst.xs1
invalidate mvin_cmd.inst.xd
invalidate mvin_cmd.inst.rs1
invalidate mvin_cmd.inst.rs2
invalidate mvin_cmd.inst.funct
connect mvin_cmd.inst.funct, UInt<4>(0he)
connect mvin_cmd.rs1, UInt<1>(0h0)
connect mvin_cmd.rs2, UInt<1>(0h0)
node _io_req_ready_T = eq(state, UInt<1>(0h0))
node _io_req_ready_T_1 = eq(command_p.io.busy, UInt<1>(0h0))
node _io_req_ready_T_2 = and(_io_req_ready_T, _io_req_ready_T_1)
connect io.req.ready, _io_req_ready_T_2
node _io_idle_T = eq(state, UInt<1>(0h0))
node _io_idle_T_1 = eq(command_p.io.busy, UInt<1>(0h0))
node _io_idle_T_2 = and(_io_idle_T, _io_idle_T_1)
connect io.idle, _io_idle_T_2
connect io.loop_id, req.loop_id
node _command_p_io_in_valid_T = neq(state, UInt<1>(0h0))
node _command_p_io_in_valid_T_1 = eq(io.wait_for_prev_loop, UInt<1>(0h0))
node _command_p_io_in_valid_T_2 = and(_command_p_io_in_valid_T, _command_p_io_in_valid_T_1)
node _command_p_io_in_valid_T_3 = eq(skip, UInt<1>(0h0))
node _command_p_io_in_valid_T_4 = and(_command_p_io_in_valid_T_2, _command_p_io_in_valid_T_3)
connect command_p.io.in.valid, _command_p_io_in_valid_T_4
node _command_p_io_in_bits_cmd_T = eq(state, UInt<1>(0h1))
node _command_p_io_in_bits_cmd_T_1 = mux(_command_p_io_in_bits_cmd_T, config_cmd, mvin_cmd)
connect command_p.io.in.bits.cmd.status.uie, _command_p_io_in_bits_cmd_T_1.status.uie
connect command_p.io.in.bits.cmd.status.sie, _command_p_io_in_bits_cmd_T_1.status.sie
connect command_p.io.in.bits.cmd.status.hie, _command_p_io_in_bits_cmd_T_1.status.hie
connect command_p.io.in.bits.cmd.status.mie, _command_p_io_in_bits_cmd_T_1.status.mie
connect command_p.io.in.bits.cmd.status.upie, _command_p_io_in_bits_cmd_T_1.status.upie
connect command_p.io.in.bits.cmd.status.spie, _command_p_io_in_bits_cmd_T_1.status.spie
connect command_p.io.in.bits.cmd.status.ube, _command_p_io_in_bits_cmd_T_1.status.ube
connect command_p.io.in.bits.cmd.status.mpie, _command_p_io_in_bits_cmd_T_1.status.mpie
connect command_p.io.in.bits.cmd.status.spp, _command_p_io_in_bits_cmd_T_1.status.spp
connect command_p.io.in.bits.cmd.status.vs, _command_p_io_in_bits_cmd_T_1.status.vs
connect command_p.io.in.bits.cmd.status.mpp, _command_p_io_in_bits_cmd_T_1.status.mpp
connect command_p.io.in.bits.cmd.status.fs, _command_p_io_in_bits_cmd_T_1.status.fs
connect command_p.io.in.bits.cmd.status.xs, _command_p_io_in_bits_cmd_T_1.status.xs
connect command_p.io.in.bits.cmd.status.mprv, _command_p_io_in_bits_cmd_T_1.status.mprv
connect command_p.io.in.bits.cmd.status.sum, _command_p_io_in_bits_cmd_T_1.status.sum
connect command_p.io.in.bits.cmd.status.mxr, _command_p_io_in_bits_cmd_T_1.status.mxr
connect command_p.io.in.bits.cmd.status.tvm, _command_p_io_in_bits_cmd_T_1.status.tvm
connect command_p.io.in.bits.cmd.status.tw, _command_p_io_in_bits_cmd_T_1.status.tw
connect command_p.io.in.bits.cmd.status.tsr, _command_p_io_in_bits_cmd_T_1.status.tsr
connect command_p.io.in.bits.cmd.status.zero1, _command_p_io_in_bits_cmd_T_1.status.zero1
connect command_p.io.in.bits.cmd.status.sd_rv32, _command_p_io_in_bits_cmd_T_1.status.sd_rv32
connect command_p.io.in.bits.cmd.status.uxl, _command_p_io_in_bits_cmd_T_1.status.uxl
connect command_p.io.in.bits.cmd.status.sxl, _command_p_io_in_bits_cmd_T_1.status.sxl
connect command_p.io.in.bits.cmd.status.sbe, _command_p_io_in_bits_cmd_T_1.status.sbe
connect command_p.io.in.bits.cmd.status.mbe, _command_p_io_in_bits_cmd_T_1.status.mbe
connect command_p.io.in.bits.cmd.status.gva, _command_p_io_in_bits_cmd_T_1.status.gva
connect command_p.io.in.bits.cmd.status.mpv, _command_p_io_in_bits_cmd_T_1.status.mpv
connect command_p.io.in.bits.cmd.status.zero2, _command_p_io_in_bits_cmd_T_1.status.zero2
connect command_p.io.in.bits.cmd.status.sd, _command_p_io_in_bits_cmd_T_1.status.sd
connect command_p.io.in.bits.cmd.status.v, _command_p_io_in_bits_cmd_T_1.status.v
connect command_p.io.in.bits.cmd.status.prv, _command_p_io_in_bits_cmd_T_1.status.prv
connect command_p.io.in.bits.cmd.status.dv, _command_p_io_in_bits_cmd_T_1.status.dv
connect command_p.io.in.bits.cmd.status.dprv, _command_p_io_in_bits_cmd_T_1.status.dprv
connect command_p.io.in.bits.cmd.status.isa, _command_p_io_in_bits_cmd_T_1.status.isa
connect command_p.io.in.bits.cmd.status.wfi, _command_p_io_in_bits_cmd_T_1.status.wfi
connect command_p.io.in.bits.cmd.status.cease, _command_p_io_in_bits_cmd_T_1.status.cease
connect command_p.io.in.bits.cmd.status.debug, _command_p_io_in_bits_cmd_T_1.status.debug
connect command_p.io.in.bits.cmd.rs2, _command_p_io_in_bits_cmd_T_1.rs2
connect command_p.io.in.bits.cmd.rs1, _command_p_io_in_bits_cmd_T_1.rs1
connect command_p.io.in.bits.cmd.inst.opcode, _command_p_io_in_bits_cmd_T_1.inst.opcode
connect command_p.io.in.bits.cmd.inst.rd, _command_p_io_in_bits_cmd_T_1.inst.rd
connect command_p.io.in.bits.cmd.inst.xs2, _command_p_io_in_bits_cmd_T_1.inst.xs2
connect command_p.io.in.bits.cmd.inst.xs1, _command_p_io_in_bits_cmd_T_1.inst.xs1
connect command_p.io.in.bits.cmd.inst.xd, _command_p_io_in_bits_cmd_T_1.inst.xd
connect command_p.io.in.bits.cmd.inst.rs1, _command_p_io_in_bits_cmd_T_1.inst.rs1
connect command_p.io.in.bits.cmd.inst.rs2, _command_p_io_in_bits_cmd_T_1.inst.rs2
connect command_p.io.in.bits.cmd.inst.funct, _command_p_io_in_bits_cmd_T_1.inst.funct
connect command_p.io.in.bits.dram_addr, dram_addr
connect command_p.io.in.bits.spad_addr, spad_addr
connect command_p.io.in.bits.I, I
connect command_p.io.in.bits.J, J
node _command_p_io_out_ready_T = eq(io.rob_overloaded, UInt<1>(0h0))
node _command_p_io_out_ready_T_1 = and(io.cmd.ready, _command_p_io_out_ready_T)
connect command_p.io.out.ready, _command_p_io_out_ready_T_1
node _io_cmd_valid_T = eq(io.rob_overloaded, UInt<1>(0h0))
node _io_cmd_valid_T_1 = and(command_p.io.out.valid, _io_cmd_valid_T)
connect io.cmd.valid, _io_cmd_valid_T_1
connect io.cmd.bits, command_p.io.out.bits.cmd
node _T = eq(command_p.io.out.bits.cmd.inst.funct, UInt<4>(0he))
when _T :
connect io.cmd.bits.rs1, command_p.io.out.bits.dram_addr
wire mvin_cmd_rs2 : { _spacer2 : UInt<13>, num_rows : UInt<3>, _spacer1 : UInt<11>, num_cols : UInt<5>, _spacer0 : UInt<0>, local_addr : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}}
invalidate mvin_cmd_rs2.local_addr.data
invalidate mvin_cmd_rs2.local_addr.garbage_bit
invalidate mvin_cmd_rs2.local_addr.garbage
invalidate mvin_cmd_rs2.local_addr.norm_cmd
invalidate mvin_cmd_rs2.local_addr.read_full_acc_row
invalidate mvin_cmd_rs2.local_addr.accumulate
invalidate mvin_cmd_rs2.local_addr.is_acc_addr
invalidate mvin_cmd_rs2._spacer0
invalidate mvin_cmd_rs2.num_cols
invalidate mvin_cmd_rs2._spacer1
invalidate mvin_cmd_rs2.num_rows
invalidate mvin_cmd_rs2._spacer2
connect mvin_cmd_rs2.num_rows, command_p.io.out.bits.I
connect mvin_cmd_rs2.num_cols, command_p.io.out.bits.J
wire _mvin_cmd_rs2_local_addr_result_result_WIRE : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _mvin_cmd_rs2_local_addr_result_result_WIRE_1 : UInt<32>
connect _mvin_cmd_rs2_local_addr_result_result_WIRE_1, command_p.io.out.bits.spad_addr
node _mvin_cmd_rs2_local_addr_result_result_T = bits(_mvin_cmd_rs2_local_addr_result_result_WIRE_1, 13, 0)
connect _mvin_cmd_rs2_local_addr_result_result_WIRE.data, _mvin_cmd_rs2_local_addr_result_result_T
node _mvin_cmd_rs2_local_addr_result_result_T_1 = bits(_mvin_cmd_rs2_local_addr_result_result_WIRE_1, 14, 14)
connect _mvin_cmd_rs2_local_addr_result_result_WIRE.garbage_bit, _mvin_cmd_rs2_local_addr_result_result_T_1
node _mvin_cmd_rs2_local_addr_result_result_T_2 = bits(_mvin_cmd_rs2_local_addr_result_result_WIRE_1, 25, 15)
connect _mvin_cmd_rs2_local_addr_result_result_WIRE.garbage, _mvin_cmd_rs2_local_addr_result_result_T_2
node _mvin_cmd_rs2_local_addr_result_result_T_3 = bits(_mvin_cmd_rs2_local_addr_result_result_WIRE_1, 28, 26)
wire _mvin_cmd_rs2_local_addr_result_result_WIRE_2 : UInt<3>
connect _mvin_cmd_rs2_local_addr_result_result_WIRE_2, _mvin_cmd_rs2_local_addr_result_result_T_3
wire _mvin_cmd_rs2_local_addr_result_result_WIRE_3 : UInt<3>
connect _mvin_cmd_rs2_local_addr_result_result_WIRE_3, _mvin_cmd_rs2_local_addr_result_result_WIRE_2
connect _mvin_cmd_rs2_local_addr_result_result_WIRE.norm_cmd, _mvin_cmd_rs2_local_addr_result_result_WIRE_3
node _mvin_cmd_rs2_local_addr_result_result_T_4 = bits(_mvin_cmd_rs2_local_addr_result_result_WIRE_1, 29, 29)
connect _mvin_cmd_rs2_local_addr_result_result_WIRE.read_full_acc_row, _mvin_cmd_rs2_local_addr_result_result_T_4
node _mvin_cmd_rs2_local_addr_result_result_T_5 = bits(_mvin_cmd_rs2_local_addr_result_result_WIRE_1, 30, 30)
connect _mvin_cmd_rs2_local_addr_result_result_WIRE.accumulate, _mvin_cmd_rs2_local_addr_result_result_T_5
node _mvin_cmd_rs2_local_addr_result_result_T_6 = bits(_mvin_cmd_rs2_local_addr_result_result_WIRE_1, 31, 31)
connect _mvin_cmd_rs2_local_addr_result_result_WIRE.is_acc_addr, _mvin_cmd_rs2_local_addr_result_result_T_6
wire mvin_cmd_rs2_local_addr_result_result : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
connect mvin_cmd_rs2_local_addr_result_result, _mvin_cmd_rs2_local_addr_result_result_WIRE
connect mvin_cmd_rs2_local_addr_result_result.garbage, UInt<1>(0h0)
wire mvin_cmd_rs2_local_addr_result : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
connect mvin_cmd_rs2_local_addr_result, mvin_cmd_rs2_local_addr_result_result
connect mvin_cmd_rs2_local_addr_result.is_acc_addr, UInt<1>(0h1)
connect mvin_cmd_rs2_local_addr_result.accumulate, UInt<1>(0h0)
connect mvin_cmd_rs2_local_addr_result.read_full_acc_row, UInt<1>(0h0)
connect mvin_cmd_rs2.local_addr, mvin_cmd_rs2_local_addr_result
node _io_cmd_bits_rs2_T = asUInt(mvin_cmd_rs2.local_addr.norm_cmd)
node io_cmd_bits_rs2_lo_hi = cat(mvin_cmd_rs2.local_addr.garbage, mvin_cmd_rs2.local_addr.garbage_bit)
node io_cmd_bits_rs2_lo = cat(io_cmd_bits_rs2_lo_hi, mvin_cmd_rs2.local_addr.data)
node io_cmd_bits_rs2_hi_lo = cat(mvin_cmd_rs2.local_addr.read_full_acc_row, _io_cmd_bits_rs2_T)
node io_cmd_bits_rs2_hi_hi = cat(mvin_cmd_rs2.local_addr.is_acc_addr, mvin_cmd_rs2.local_addr.accumulate)
node io_cmd_bits_rs2_hi = cat(io_cmd_bits_rs2_hi_hi, io_cmd_bits_rs2_hi_lo)
node _io_cmd_bits_rs2_T_1 = cat(io_cmd_bits_rs2_hi, io_cmd_bits_rs2_lo)
node io_cmd_bits_rs2_lo_hi_1 = cat(mvin_cmd_rs2.num_cols, mvin_cmd_rs2._spacer0)
node io_cmd_bits_rs2_lo_1 = cat(io_cmd_bits_rs2_lo_hi_1, _io_cmd_bits_rs2_T_1)
node io_cmd_bits_rs2_hi_hi_1 = cat(mvin_cmd_rs2._spacer2, mvin_cmd_rs2.num_rows)
node io_cmd_bits_rs2_hi_1 = cat(io_cmd_bits_rs2_hi_hi_1, mvin_cmd_rs2._spacer1)
node _io_cmd_bits_rs2_T_2 = cat(io_cmd_bits_rs2_hi_1, io_cmd_bits_rs2_lo_1)
connect io.cmd.bits.rs2, _io_cmd_bits_rs2_T_2
when skip :
connect state, UInt<1>(0h0)
else :
node _T_1 = and(command_p.io.in.ready, command_p.io.in.valid)
when _T_1 :
node _T_2 = eq(state, UInt<1>(0h1))
when _T_2 :
connect state, UInt<2>(0h2)
else :
node _next_och_max_T = sub(req.derived_params.ochs, UInt<1>(0h1))
node next_och_max = tail(_next_och_max_T, 1)
node _next_och_T = add(och, max_ochs_per_mvin)
node _next_och_T_1 = tail(_next_och_T, 1)
node _next_och_T_2 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _next_och_T_3 = add(och, max_ochs_per_mvin)
node _next_och_T_4 = gt(_next_och_T_3, next_och_max)
node _next_och_T_5 = mux(_next_och_T_4, UInt<1>(0h0), _next_och_T_1)
node next_och = mux(_next_och_T_2, och, _next_och_T_5)
node _next_ocol_T = eq(next_och, UInt<1>(0h0))
node _next_ocol_max_T = sub(req.inner_bounds.ocols, UInt<1>(0h1))
node next_ocol_max = tail(_next_ocol_max_T, 1)
node _next_ocol_T_1 = add(ocol, UInt<3>(0h4))
node _next_ocol_T_2 = tail(_next_ocol_T_1, 1)
node _next_ocol_T_3 = eq(_next_ocol_T, UInt<1>(0h0))
node _next_ocol_T_4 = add(ocol, UInt<3>(0h4))
node _next_ocol_T_5 = gt(_next_ocol_T_4, next_ocol_max)
node _next_ocol_T_6 = mux(_next_ocol_T_5, UInt<1>(0h0), _next_ocol_T_2)
node next_ocol = mux(_next_ocol_T_3, ocol, _next_ocol_T_6)
node _next_orow_T = eq(next_ocol, UInt<1>(0h0))
node _next_orow_T_1 = eq(next_och, UInt<1>(0h0))
node _next_orow_T_2 = and(_next_orow_T, _next_orow_T_1)
node _next_orow_max_T = sub(req.inner_bounds.orows, UInt<1>(0h1))
node next_orow_max = tail(_next_orow_max_T, 1)
node _next_orow_T_3 = add(orow, UInt<1>(0h1))
node _next_orow_T_4 = tail(_next_orow_T_3, 1)
node _next_orow_T_5 = eq(_next_orow_T_2, UInt<1>(0h0))
node _next_orow_T_6 = add(orow, UInt<1>(0h1))
node _next_orow_T_7 = gt(_next_orow_T_6, next_orow_max)
node _next_orow_T_8 = mux(_next_orow_T_7, UInt<1>(0h0), _next_orow_T_4)
node next_orow = mux(_next_orow_T_5, orow, _next_orow_T_8)
node _next_b_T = eq(next_orow, UInt<1>(0h0))
node _next_b_T_1 = eq(next_ocol, UInt<1>(0h0))
node _next_b_T_2 = and(_next_b_T, _next_b_T_1)
node _next_b_T_3 = eq(next_och, UInt<1>(0h0))
node _next_b_T_4 = and(_next_b_T_2, _next_b_T_3)
node _next_b_max_T = sub(req.inner_bounds.batches, UInt<1>(0h1))
node next_b_max = tail(_next_b_max_T, 1)
node _next_b_T_5 = add(b, UInt<1>(0h1))
node _next_b_T_6 = tail(_next_b_T_5, 1)
node _next_b_T_7 = eq(_next_b_T_4, UInt<1>(0h0))
node _next_b_T_8 = add(b, UInt<1>(0h1))
node _next_b_T_9 = gt(_next_b_T_8, next_b_max)
node _next_b_T_10 = mux(_next_b_T_9, UInt<1>(0h0), _next_b_T_6)
node next_b = mux(_next_b_T_7, b, _next_b_T_10)
connect och, next_och
connect ocol, next_ocol
connect orow, next_orow
connect b, next_b
node _state_T = eq(next_b, UInt<1>(0h0))
node _state_T_1 = eq(next_orow, UInt<1>(0h0))
node _state_T_2 = and(_state_T, _state_T_1)
node _state_T_3 = eq(next_ocol, UInt<1>(0h0))
node _state_T_4 = and(_state_T_2, _state_T_3)
node _state_T_5 = eq(next_och, UInt<1>(0h0))
node _state_T_6 = and(_state_T_4, _state_T_5)
node _state_T_7 = mux(_state_T_6, UInt<1>(0h0), UInt<2>(0h2))
connect state, _state_T_7
node _T_3 = and(io.req.ready, io.req.valid)
when _T_3 :
connect req, io.req.bits
connect state, UInt<1>(0h1)
connect b, UInt<1>(0h0)
connect orow, UInt<1>(0h0)
connect ocol, UInt<1>(0h0)
connect och, UInt<1>(0h0) | module LoopConvLdBias( // @[LoopConv.scala:84:7]
input clock, // @[LoopConv.scala:84:7]
input reset, // @[LoopConv.scala:84:7]
output io_req_ready, // @[LoopConv.scala:88:14]
input io_req_valid, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_outer_bounds_batch_size, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_outer_bounds_in_row_dim, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_outer_bounds_in_col_dim, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_outer_bounds_in_channels, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_outer_bounds_out_channels, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_outer_bounds_out_col_dim, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_outer_bounds_out_row_dim, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_outer_bounds_out_stride, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_outer_bounds_in_stride, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_outer_bounds_weight_stride, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_outer_bounds_pool_out_row_dim, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_outer_bounds_pool_out_col_dim, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_outer_bounds_stride, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_outer_bounds_padding, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_outer_bounds_kernel_dim, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_outer_bounds_kernel_dilation, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_outer_bounds_pool_size, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_outer_bounds_pool_stride, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_outer_bounds_pool_padding, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_inner_bounds_batches, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_inner_bounds_porows, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_inner_bounds_pocols, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_inner_bounds_pochs, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_inner_bounds_krows, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_inner_bounds_kcols, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_inner_bounds_kchs, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_inner_bounds_lpad, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_inner_bounds_rpad, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_inner_bounds_upad, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_inner_bounds_dpad, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_inner_bounds_plpad, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_inner_bounds_prad, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_inner_bounds_pupad, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_inner_bounds_pdpad, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_inner_bounds_orows, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_inner_bounds_ocols, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_derived_params_ochs, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_derived_params_irows, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_derived_params_icols, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_derived_params_irows_unpadded, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_derived_params_icols_unpadded, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_derived_params_ichs, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_derived_params_out_channels_per_bank, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_derived_params_in_channels_per_bank, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_derived_params_bias_spad_stride, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_derived_params_input_spad_stride, // @[LoopConv.scala:88:14]
input [15:0] io_req_bits_derived_params_weight_spad_stride, // @[LoopConv.scala:88:14]
input [11:0] io_req_bits_addr_start, // @[LoopConv.scala:88:14]
input [39:0] io_req_bits_dram_addr, // @[LoopConv.scala:88:14]
input io_req_bits_no_bias, // @[LoopConv.scala:88:14]
input io_req_bits_loop_id, // @[LoopConv.scala:88:14]
input io_cmd_ready, // @[LoopConv.scala:88:14]
output io_cmd_valid, // @[LoopConv.scala:88:14]
output [6:0] io_cmd_bits_inst_funct, // @[LoopConv.scala:88:14]
output [4:0] io_cmd_bits_inst_rs2, // @[LoopConv.scala:88:14]
output [4:0] io_cmd_bits_inst_rs1, // @[LoopConv.scala:88:14]
output io_cmd_bits_inst_xd, // @[LoopConv.scala:88:14]
output io_cmd_bits_inst_xs1, // @[LoopConv.scala:88:14]
output io_cmd_bits_inst_xs2, // @[LoopConv.scala:88:14]
output [4:0] io_cmd_bits_inst_rd, // @[LoopConv.scala:88:14]
output [6:0] io_cmd_bits_inst_opcode, // @[LoopConv.scala:88:14]
output [63:0] io_cmd_bits_rs1, // @[LoopConv.scala:88:14]
output [63:0] io_cmd_bits_rs2, // @[LoopConv.scala:88:14]
output io_cmd_bits_status_debug, // @[LoopConv.scala:88:14]
output io_cmd_bits_status_cease, // @[LoopConv.scala:88:14]
output io_cmd_bits_status_wfi, // @[LoopConv.scala:88:14]
output [31:0] io_cmd_bits_status_isa, // @[LoopConv.scala:88:14]
output [1:0] io_cmd_bits_status_dprv, // @[LoopConv.scala:88:14]
output io_cmd_bits_status_dv, // @[LoopConv.scala:88:14]
output [1:0] io_cmd_bits_status_prv, // @[LoopConv.scala:88:14]
output io_cmd_bits_status_v, // @[LoopConv.scala:88:14]
output io_cmd_bits_status_sd, // @[LoopConv.scala:88:14]
output [22:0] io_cmd_bits_status_zero2, // @[LoopConv.scala:88:14]
output io_cmd_bits_status_mpv, // @[LoopConv.scala:88:14]
output io_cmd_bits_status_gva, // @[LoopConv.scala:88:14]
output io_cmd_bits_status_mbe, // @[LoopConv.scala:88:14]
output io_cmd_bits_status_sbe, // @[LoopConv.scala:88:14]
output [1:0] io_cmd_bits_status_sxl, // @[LoopConv.scala:88:14]
output [1:0] io_cmd_bits_status_uxl, // @[LoopConv.scala:88:14]
output io_cmd_bits_status_sd_rv32, // @[LoopConv.scala:88:14]
output [7:0] io_cmd_bits_status_zero1, // @[LoopConv.scala:88:14]
output io_cmd_bits_status_tsr, // @[LoopConv.scala:88:14]
output io_cmd_bits_status_tw, // @[LoopConv.scala:88:14]
output io_cmd_bits_status_tvm, // @[LoopConv.scala:88:14]
output io_cmd_bits_status_mxr, // @[LoopConv.scala:88:14]
output io_cmd_bits_status_sum, // @[LoopConv.scala:88:14]
output io_cmd_bits_status_mprv, // @[LoopConv.scala:88:14]
output [1:0] io_cmd_bits_status_xs, // @[LoopConv.scala:88:14]
output [1:0] io_cmd_bits_status_fs, // @[LoopConv.scala:88:14]
output [1:0] io_cmd_bits_status_mpp, // @[LoopConv.scala:88:14]
output [1:0] io_cmd_bits_status_vs, // @[LoopConv.scala:88:14]
output io_cmd_bits_status_spp, // @[LoopConv.scala:88:14]
output io_cmd_bits_status_mpie, // @[LoopConv.scala:88:14]
output io_cmd_bits_status_ube, // @[LoopConv.scala:88:14]
output io_cmd_bits_status_spie, // @[LoopConv.scala:88:14]
output io_cmd_bits_status_upie, // @[LoopConv.scala:88:14]
output io_cmd_bits_status_mie, // @[LoopConv.scala:88:14]
output io_cmd_bits_status_hie, // @[LoopConv.scala:88:14]
output io_cmd_bits_status_sie, // @[LoopConv.scala:88:14]
output io_cmd_bits_status_uie, // @[LoopConv.scala:88:14]
output io_idle, // @[LoopConv.scala:88:14]
input io_rob_overloaded, // @[LoopConv.scala:88:14]
input io_wait_for_prev_loop, // @[LoopConv.scala:88:14]
output io_loop_id // @[LoopConv.scala:88:14]
);
wire _mvin_cmd_rs2_local_addr_result_result_WIRE_is_acc_addr; // @[LocalAddr.scala:108:37]
wire _mvin_cmd_rs2_local_addr_result_result_WIRE_accumulate; // @[LocalAddr.scala:108:37]
wire _mvin_cmd_rs2_local_addr_result_result_WIRE_read_full_acc_row; // @[LocalAddr.scala:108:37]
wire [2:0] _mvin_cmd_rs2_local_addr_result_result_WIRE_norm_cmd; // @[LocalAddr.scala:108:37]
wire _mvin_cmd_rs2_local_addr_result_result_WIRE_garbage_bit; // @[LocalAddr.scala:108:37]
wire [13:0] _mvin_cmd_rs2_local_addr_result_result_WIRE_data; // @[LocalAddr.scala:108:37]
wire [4:0] mvin_cmd_rs2_num_cols; // @[LoopConv.scala:181:28]
wire [2:0] mvin_cmd_rs2_local_addr_norm_cmd; // @[LoopConv.scala:181:28]
wire _command_p_io_in_ready; // @[LoopConv.scala:138:25]
wire _command_p_io_out_valid; // @[LoopConv.scala:138:25]
wire [6:0] _command_p_io_out_bits_cmd_inst_funct; // @[LoopConv.scala:138:25]
wire [63:0] _command_p_io_out_bits_cmd_rs1; // @[LoopConv.scala:138:25]
wire [63:0] _command_p_io_out_bits_cmd_rs2; // @[LoopConv.scala:138:25]
wire [39:0] _command_p_io_out_bits_dram_addr; // @[LoopConv.scala:138:25]
wire [67:0] _command_p_io_out_bits_spad_addr; // @[LoopConv.scala:138:25]
wire [15:0] _command_p_io_out_bits_I; // @[LoopConv.scala:138:25]
wire [15:0] _command_p_io_out_bits_J; // @[LoopConv.scala:138:25]
wire _command_p_io_busy; // @[LoopConv.scala:138:25]
wire io_req_valid_0 = io_req_valid; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_outer_bounds_batch_size_0 = io_req_bits_outer_bounds_batch_size; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_outer_bounds_in_row_dim_0 = io_req_bits_outer_bounds_in_row_dim; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_outer_bounds_in_col_dim_0 = io_req_bits_outer_bounds_in_col_dim; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_outer_bounds_in_channels_0 = io_req_bits_outer_bounds_in_channels; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_outer_bounds_out_channels_0 = io_req_bits_outer_bounds_out_channels; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_outer_bounds_out_col_dim_0 = io_req_bits_outer_bounds_out_col_dim; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_outer_bounds_out_row_dim_0 = io_req_bits_outer_bounds_out_row_dim; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_outer_bounds_out_stride_0 = io_req_bits_outer_bounds_out_stride; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_outer_bounds_in_stride_0 = io_req_bits_outer_bounds_in_stride; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_outer_bounds_weight_stride_0 = io_req_bits_outer_bounds_weight_stride; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_outer_bounds_pool_out_row_dim_0 = io_req_bits_outer_bounds_pool_out_row_dim; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_outer_bounds_pool_out_col_dim_0 = io_req_bits_outer_bounds_pool_out_col_dim; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_outer_bounds_stride_0 = io_req_bits_outer_bounds_stride; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_outer_bounds_padding_0 = io_req_bits_outer_bounds_padding; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_outer_bounds_kernel_dim_0 = io_req_bits_outer_bounds_kernel_dim; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_outer_bounds_kernel_dilation_0 = io_req_bits_outer_bounds_kernel_dilation; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_outer_bounds_pool_size_0 = io_req_bits_outer_bounds_pool_size; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_outer_bounds_pool_stride_0 = io_req_bits_outer_bounds_pool_stride; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_outer_bounds_pool_padding_0 = io_req_bits_outer_bounds_pool_padding; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_inner_bounds_batches_0 = io_req_bits_inner_bounds_batches; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_inner_bounds_porows_0 = io_req_bits_inner_bounds_porows; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_inner_bounds_pocols_0 = io_req_bits_inner_bounds_pocols; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_inner_bounds_pochs_0 = io_req_bits_inner_bounds_pochs; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_inner_bounds_krows_0 = io_req_bits_inner_bounds_krows; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_inner_bounds_kcols_0 = io_req_bits_inner_bounds_kcols; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_inner_bounds_kchs_0 = io_req_bits_inner_bounds_kchs; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_inner_bounds_lpad_0 = io_req_bits_inner_bounds_lpad; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_inner_bounds_rpad_0 = io_req_bits_inner_bounds_rpad; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_inner_bounds_upad_0 = io_req_bits_inner_bounds_upad; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_inner_bounds_dpad_0 = io_req_bits_inner_bounds_dpad; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_inner_bounds_plpad_0 = io_req_bits_inner_bounds_plpad; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_inner_bounds_prad_0 = io_req_bits_inner_bounds_prad; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_inner_bounds_pupad_0 = io_req_bits_inner_bounds_pupad; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_inner_bounds_pdpad_0 = io_req_bits_inner_bounds_pdpad; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_inner_bounds_orows_0 = io_req_bits_inner_bounds_orows; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_inner_bounds_ocols_0 = io_req_bits_inner_bounds_ocols; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_derived_params_ochs_0 = io_req_bits_derived_params_ochs; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_derived_params_irows_0 = io_req_bits_derived_params_irows; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_derived_params_icols_0 = io_req_bits_derived_params_icols; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_derived_params_irows_unpadded_0 = io_req_bits_derived_params_irows_unpadded; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_derived_params_icols_unpadded_0 = io_req_bits_derived_params_icols_unpadded; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_derived_params_ichs_0 = io_req_bits_derived_params_ichs; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_derived_params_out_channels_per_bank_0 = io_req_bits_derived_params_out_channels_per_bank; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_derived_params_in_channels_per_bank_0 = io_req_bits_derived_params_in_channels_per_bank; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_derived_params_bias_spad_stride_0 = io_req_bits_derived_params_bias_spad_stride; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_derived_params_input_spad_stride_0 = io_req_bits_derived_params_input_spad_stride; // @[LoopConv.scala:84:7]
wire [15:0] io_req_bits_derived_params_weight_spad_stride_0 = io_req_bits_derived_params_weight_spad_stride; // @[LoopConv.scala:84:7]
wire [11:0] io_req_bits_addr_start_0 = io_req_bits_addr_start; // @[LoopConv.scala:84:7]
wire [39:0] io_req_bits_dram_addr_0 = io_req_bits_dram_addr; // @[LoopConv.scala:84:7]
wire io_req_bits_no_bias_0 = io_req_bits_no_bias; // @[LoopConv.scala:84:7]
wire io_req_bits_loop_id_0 = io_req_bits_loop_id; // @[LoopConv.scala:84:7]
wire io_cmd_ready_0 = io_cmd_ready; // @[LoopConv.scala:84:7]
wire io_rob_overloaded_0 = io_rob_overloaded; // @[LoopConv.scala:84:7]
wire io_wait_for_prev_loop_0 = io_wait_for_prev_loop; // @[LoopConv.scala:84:7]
wire [2:0] config_cmd_rs1__spacer0 = 3'h0; // @[LoopConv.scala:145:28]
wire [1:0] config_cmd_rs1__unused = 2'h1; // @[LoopConv.scala:145:28, :169:41]
wire [2:0] config_cmd_rs1_pixel_repeats = 3'h1; // @[LoopConv.scala:145:28]
wire [2:0] config_cmd_rs1_lo_lo = 3'h1; // @[LoopConv.scala:153:36]
wire [5:0] config_cmd_rs1_lo_hi_hi = 6'h8; // @[LoopConv.scala:153:36]
wire [7:0] config_cmd_rs1_lo_hi = 8'h22; // @[LoopConv.scala:153:36]
wire [10:0] config_cmd_rs1_lo = 11'h111; // @[LoopConv.scala:153:36]
wire [31:0] config_cmd_rs1_scale = 32'h3F800000; // @[LoopConv.scala:145:28]
wire [31:0] config_cmd_rs1_hi_hi_hi = 32'h3F800000; // @[LoopConv.scala:153:36]
wire [33:0] config_cmd_rs1_hi_hi = 34'hFE000000; // @[LoopConv.scala:153:36]
wire [6:0] mvin_cmd_inst_funct = 7'hE; // @[LoopConv.scala:157:22, :178:46]
wire [4:0] config_cmd_inst_rs2 = 5'h0; // @[LoopConv.scala:141:24]
wire [4:0] config_cmd_inst_rs1 = 5'h0; // @[LoopConv.scala:141:24]
wire [4:0] config_cmd_inst_rd = 5'h0; // @[LoopConv.scala:141:24]
wire [4:0] config_cmd_rs1__spacer1 = 5'h0; // @[LoopConv.scala:145:28]
wire [4:0] mvin_cmd_inst_rs2 = 5'h0; // @[LoopConv.scala:157:22]
wire [4:0] mvin_cmd_inst_rs1 = 5'h0; // @[LoopConv.scala:157:22]
wire [4:0] mvin_cmd_inst_rd = 5'h0; // @[LoopConv.scala:157:22]
wire [4:0] _command_p_io_in_bits_cmd_T_1_inst_rs2 = 5'h0; // @[LoopConv.scala:169:34]
wire [4:0] _command_p_io_in_bits_cmd_T_1_inst_rs1 = 5'h0; // @[LoopConv.scala:169:34]
wire [4:0] _command_p_io_in_bits_cmd_T_1_inst_rd = 5'h0; // @[LoopConv.scala:169:34]
wire [6:0] config_cmd_inst_funct = 7'h0; // @[LoopConv.scala:141:24]
wire [6:0] config_cmd_inst_opcode = 7'h0; // @[LoopConv.scala:141:24]
wire [6:0] mvin_cmd_inst_opcode = 7'h0; // @[LoopConv.scala:157:22]
wire [6:0] _command_p_io_in_bits_cmd_T_1_inst_opcode = 7'h0; // @[LoopConv.scala:169:34]
wire [63:0] config_cmd_rs2 = 64'h0; // @[LoopConv.scala:141:24]
wire [63:0] mvin_cmd_rs1 = 64'h0; // @[LoopConv.scala:157:22]
wire [63:0] mvin_cmd_rs2 = 64'h0; // @[LoopConv.scala:157:22]
wire [63:0] _command_p_io_in_bits_cmd_T_1_rs2 = 64'h0; // @[LoopConv.scala:169:34]
wire [31:0] config_cmd_status_isa = 32'h0; // @[LoopConv.scala:141:24]
wire [31:0] mvin_cmd_status_isa = 32'h0; // @[LoopConv.scala:157:22]
wire [31:0] _command_p_io_in_bits_cmd_T_1_status_isa = 32'h0; // @[LoopConv.scala:169:34]
wire [22:0] config_cmd_status_zero2 = 23'h0; // @[LoopConv.scala:141:24]
wire [22:0] mvin_cmd_status_zero2 = 23'h0; // @[LoopConv.scala:157:22]
wire [22:0] _command_p_io_in_bits_cmd_T_1_status_zero2 = 23'h0; // @[LoopConv.scala:169:34]
wire [7:0] config_cmd_status_zero1 = 8'h0; // @[LoopConv.scala:141:24]
wire [7:0] mvin_cmd_status_zero1 = 8'h0; // @[LoopConv.scala:157:22]
wire [7:0] _command_p_io_in_bits_cmd_T_1_status_zero1 = 8'h0; // @[LoopConv.scala:169:34]
wire [1:0] config_cmd_status_dprv = 2'h0; // @[LoopConv.scala:141:24]
wire [1:0] config_cmd_status_prv = 2'h0; // @[LoopConv.scala:141:24]
wire [1:0] config_cmd_status_sxl = 2'h0; // @[LoopConv.scala:141:24]
wire [1:0] config_cmd_status_uxl = 2'h0; // @[LoopConv.scala:141:24]
wire [1:0] config_cmd_status_xs = 2'h0; // @[LoopConv.scala:141:24]
wire [1:0] config_cmd_status_fs = 2'h0; // @[LoopConv.scala:141:24]
wire [1:0] config_cmd_status_mpp = 2'h0; // @[LoopConv.scala:141:24]
wire [1:0] config_cmd_status_vs = 2'h0; // @[LoopConv.scala:141:24]
wire [1:0] config_cmd_rs1__spacer2 = 2'h0; // @[LoopConv.scala:145:28]
wire [1:0] mvin_cmd_status_dprv = 2'h0; // @[LoopConv.scala:157:22]
wire [1:0] mvin_cmd_status_prv = 2'h0; // @[LoopConv.scala:157:22]
wire [1:0] mvin_cmd_status_sxl = 2'h0; // @[LoopConv.scala:157:22]
wire [1:0] mvin_cmd_status_uxl = 2'h0; // @[LoopConv.scala:157:22]
wire [1:0] mvin_cmd_status_xs = 2'h0; // @[LoopConv.scala:157:22]
wire [1:0] mvin_cmd_status_fs = 2'h0; // @[LoopConv.scala:157:22]
wire [1:0] mvin_cmd_status_mpp = 2'h0; // @[LoopConv.scala:157:22]
wire [1:0] mvin_cmd_status_vs = 2'h0; // @[LoopConv.scala:157:22]
wire [1:0] _command_p_io_in_bits_cmd_T_1_status_dprv = 2'h0; // @[LoopConv.scala:169:34]
wire [1:0] _command_p_io_in_bits_cmd_T_1_status_prv = 2'h0; // @[LoopConv.scala:169:34]
wire [1:0] _command_p_io_in_bits_cmd_T_1_status_sxl = 2'h0; // @[LoopConv.scala:169:34]
wire [1:0] _command_p_io_in_bits_cmd_T_1_status_uxl = 2'h0; // @[LoopConv.scala:169:34]
wire [1:0] _command_p_io_in_bits_cmd_T_1_status_xs = 2'h0; // @[LoopConv.scala:169:34]
wire [1:0] _command_p_io_in_bits_cmd_T_1_status_fs = 2'h0; // @[LoopConv.scala:169:34]
wire [1:0] _command_p_io_in_bits_cmd_T_1_status_mpp = 2'h0; // @[LoopConv.scala:169:34]
wire [1:0] _command_p_io_in_bits_cmd_T_1_status_vs = 2'h0; // @[LoopConv.scala:169:34]
wire [12:0] mvin_cmd_rs2__spacer2 = 13'h0; // @[LoopConv.scala:181:28]
wire mvin_cmd_rs2_local_addr_is_acc_addr = 1'h1; // @[LoopConv.scala:181:28]
wire mvin_cmd_rs2_local_addr_result_is_acc_addr = 1'h1; // @[LocalAddr.scala:129:26]
wire [10:0] mvin_cmd_rs2__spacer1 = 11'h0; // @[LoopConv.scala:181:28]
wire [10:0] mvin_cmd_rs2_local_addr_garbage = 11'h0; // @[LoopConv.scala:181:28]
wire [10:0] mvin_cmd_rs2_local_addr_result_result_garbage = 11'h0; // @[LocalAddr.scala:108:26]
wire [10:0] mvin_cmd_rs2_local_addr_result_garbage = 11'h0; // @[LocalAddr.scala:129:26]
wire [1:0] config_cmd_rs1_state_id = 2'h2; // @[LoopConv.scala:145:28]
wire [1:0] io_cmd_bits_rs2_hi_hi = 2'h2; // @[LoopConv.scala:186:37]
wire config_cmd_inst_xd = 1'h0; // @[LoopConv.scala:141:24]
wire config_cmd_inst_xs1 = 1'h0; // @[LoopConv.scala:141:24]
wire config_cmd_inst_xs2 = 1'h0; // @[LoopConv.scala:141:24]
wire config_cmd_status_debug = 1'h0; // @[LoopConv.scala:141:24]
wire config_cmd_status_cease = 1'h0; // @[LoopConv.scala:141:24]
wire config_cmd_status_wfi = 1'h0; // @[LoopConv.scala:141:24]
wire config_cmd_status_dv = 1'h0; // @[LoopConv.scala:141:24]
wire config_cmd_status_v = 1'h0; // @[LoopConv.scala:141:24]
wire config_cmd_status_sd = 1'h0; // @[LoopConv.scala:141:24]
wire config_cmd_status_mpv = 1'h0; // @[LoopConv.scala:141:24]
wire config_cmd_status_gva = 1'h0; // @[LoopConv.scala:141:24]
wire config_cmd_status_mbe = 1'h0; // @[LoopConv.scala:141:24]
wire config_cmd_status_sbe = 1'h0; // @[LoopConv.scala:141:24]
wire config_cmd_status_sd_rv32 = 1'h0; // @[LoopConv.scala:141:24]
wire config_cmd_status_tsr = 1'h0; // @[LoopConv.scala:141:24]
wire config_cmd_status_tw = 1'h0; // @[LoopConv.scala:141:24]
wire config_cmd_status_tvm = 1'h0; // @[LoopConv.scala:141:24]
wire config_cmd_status_mxr = 1'h0; // @[LoopConv.scala:141:24]
wire config_cmd_status_sum = 1'h0; // @[LoopConv.scala:141:24]
wire config_cmd_status_mprv = 1'h0; // @[LoopConv.scala:141:24]
wire config_cmd_status_spp = 1'h0; // @[LoopConv.scala:141:24]
wire config_cmd_status_mpie = 1'h0; // @[LoopConv.scala:141:24]
wire config_cmd_status_ube = 1'h0; // @[LoopConv.scala:141:24]
wire config_cmd_status_spie = 1'h0; // @[LoopConv.scala:141:24]
wire config_cmd_status_upie = 1'h0; // @[LoopConv.scala:141:24]
wire config_cmd_status_mie = 1'h0; // @[LoopConv.scala:141:24]
wire config_cmd_status_hie = 1'h0; // @[LoopConv.scala:141:24]
wire config_cmd_status_sie = 1'h0; // @[LoopConv.scala:141:24]
wire config_cmd_status_uie = 1'h0; // @[LoopConv.scala:141:24]
wire config_cmd_rs1_shrink = 1'h0; // @[LoopConv.scala:145:28]
wire mvin_cmd_inst_xd = 1'h0; // @[LoopConv.scala:157:22]
wire mvin_cmd_inst_xs1 = 1'h0; // @[LoopConv.scala:157:22]
wire mvin_cmd_inst_xs2 = 1'h0; // @[LoopConv.scala:157:22]
wire mvin_cmd_status_debug = 1'h0; // @[LoopConv.scala:157:22]
wire mvin_cmd_status_cease = 1'h0; // @[LoopConv.scala:157:22]
wire mvin_cmd_status_wfi = 1'h0; // @[LoopConv.scala:157:22]
wire mvin_cmd_status_dv = 1'h0; // @[LoopConv.scala:157:22]
wire mvin_cmd_status_v = 1'h0; // @[LoopConv.scala:157:22]
wire mvin_cmd_status_sd = 1'h0; // @[LoopConv.scala:157:22]
wire mvin_cmd_status_mpv = 1'h0; // @[LoopConv.scala:157:22]
wire mvin_cmd_status_gva = 1'h0; // @[LoopConv.scala:157:22]
wire mvin_cmd_status_mbe = 1'h0; // @[LoopConv.scala:157:22]
wire mvin_cmd_status_sbe = 1'h0; // @[LoopConv.scala:157:22]
wire mvin_cmd_status_sd_rv32 = 1'h0; // @[LoopConv.scala:157:22]
wire mvin_cmd_status_tsr = 1'h0; // @[LoopConv.scala:157:22]
wire mvin_cmd_status_tw = 1'h0; // @[LoopConv.scala:157:22]
wire mvin_cmd_status_tvm = 1'h0; // @[LoopConv.scala:157:22]
wire mvin_cmd_status_mxr = 1'h0; // @[LoopConv.scala:157:22]
wire mvin_cmd_status_sum = 1'h0; // @[LoopConv.scala:157:22]
wire mvin_cmd_status_mprv = 1'h0; // @[LoopConv.scala:157:22]
wire mvin_cmd_status_spp = 1'h0; // @[LoopConv.scala:157:22]
wire mvin_cmd_status_mpie = 1'h0; // @[LoopConv.scala:157:22]
wire mvin_cmd_status_ube = 1'h0; // @[LoopConv.scala:157:22]
wire mvin_cmd_status_spie = 1'h0; // @[LoopConv.scala:157:22]
wire mvin_cmd_status_upie = 1'h0; // @[LoopConv.scala:157:22]
wire mvin_cmd_status_mie = 1'h0; // @[LoopConv.scala:157:22]
wire mvin_cmd_status_hie = 1'h0; // @[LoopConv.scala:157:22]
wire mvin_cmd_status_sie = 1'h0; // @[LoopConv.scala:157:22]
wire mvin_cmd_status_uie = 1'h0; // @[LoopConv.scala:157:22]
wire _io_req_ready_T_2; // @[LoopConv.scala:164:34]
wire _command_p_io_in_bits_cmd_T_1_inst_xd = 1'h0; // @[LoopConv.scala:169:34]
wire _command_p_io_in_bits_cmd_T_1_inst_xs1 = 1'h0; // @[LoopConv.scala:169:34]
wire _command_p_io_in_bits_cmd_T_1_inst_xs2 = 1'h0; // @[LoopConv.scala:169:34]
wire _command_p_io_in_bits_cmd_T_1_status_debug = 1'h0; // @[LoopConv.scala:169:34]
wire _command_p_io_in_bits_cmd_T_1_status_cease = 1'h0; // @[LoopConv.scala:169:34]
wire _command_p_io_in_bits_cmd_T_1_status_wfi = 1'h0; // @[LoopConv.scala:169:34]
wire _command_p_io_in_bits_cmd_T_1_status_dv = 1'h0; // @[LoopConv.scala:169:34]
wire _command_p_io_in_bits_cmd_T_1_status_v = 1'h0; // @[LoopConv.scala:169:34]
wire _command_p_io_in_bits_cmd_T_1_status_sd = 1'h0; // @[LoopConv.scala:169:34]
wire _command_p_io_in_bits_cmd_T_1_status_mpv = 1'h0; // @[LoopConv.scala:169:34]
wire _command_p_io_in_bits_cmd_T_1_status_gva = 1'h0; // @[LoopConv.scala:169:34]
wire _command_p_io_in_bits_cmd_T_1_status_mbe = 1'h0; // @[LoopConv.scala:169:34]
wire _command_p_io_in_bits_cmd_T_1_status_sbe = 1'h0; // @[LoopConv.scala:169:34]
wire _command_p_io_in_bits_cmd_T_1_status_sd_rv32 = 1'h0; // @[LoopConv.scala:169:34]
wire _command_p_io_in_bits_cmd_T_1_status_tsr = 1'h0; // @[LoopConv.scala:169:34]
wire _command_p_io_in_bits_cmd_T_1_status_tw = 1'h0; // @[LoopConv.scala:169:34]
wire _command_p_io_in_bits_cmd_T_1_status_tvm = 1'h0; // @[LoopConv.scala:169:34]
wire _command_p_io_in_bits_cmd_T_1_status_mxr = 1'h0; // @[LoopConv.scala:169:34]
wire _command_p_io_in_bits_cmd_T_1_status_sum = 1'h0; // @[LoopConv.scala:169:34]
wire _command_p_io_in_bits_cmd_T_1_status_mprv = 1'h0; // @[LoopConv.scala:169:34]
wire _command_p_io_in_bits_cmd_T_1_status_spp = 1'h0; // @[LoopConv.scala:169:34]
wire _command_p_io_in_bits_cmd_T_1_status_mpie = 1'h0; // @[LoopConv.scala:169:34]
wire _command_p_io_in_bits_cmd_T_1_status_ube = 1'h0; // @[LoopConv.scala:169:34]
wire _command_p_io_in_bits_cmd_T_1_status_spie = 1'h0; // @[LoopConv.scala:169:34]
wire _command_p_io_in_bits_cmd_T_1_status_upie = 1'h0; // @[LoopConv.scala:169:34]
wire _command_p_io_in_bits_cmd_T_1_status_mie = 1'h0; // @[LoopConv.scala:169:34]
wire _command_p_io_in_bits_cmd_T_1_status_hie = 1'h0; // @[LoopConv.scala:169:34]
wire _command_p_io_in_bits_cmd_T_1_status_sie = 1'h0; // @[LoopConv.scala:169:34]
wire _command_p_io_in_bits_cmd_T_1_status_uie = 1'h0; // @[LoopConv.scala:169:34]
wire mvin_cmd_rs2_local_addr_accumulate = 1'h0; // @[LoopConv.scala:181:28]
wire mvin_cmd_rs2_local_addr_read_full_acc_row = 1'h0; // @[LoopConv.scala:181:28]
wire mvin_cmd_rs2_local_addr_result_accumulate = 1'h0; // @[LocalAddr.scala:129:26]
wire mvin_cmd_rs2_local_addr_result_read_full_acc_row = 1'h0; // @[LocalAddr.scala:129:26]
wire _next_och_T_2 = 1'h0; // @[Util.scala:42:8]
wire _io_cmd_valid_T_1; // @[LoopConv.scala:176:42]
wire _io_idle_T_2; // @[LoopConv.scala:165:29]
wire io_req_ready_0; // @[LoopConv.scala:84:7]
wire [6:0] io_cmd_bits_inst_funct_0; // @[LoopConv.scala:84:7]
wire [4:0] io_cmd_bits_inst_rs2_0; // @[LoopConv.scala:84:7]
wire [4:0] io_cmd_bits_inst_rs1_0; // @[LoopConv.scala:84:7]
wire io_cmd_bits_inst_xd_0; // @[LoopConv.scala:84:7]
wire io_cmd_bits_inst_xs1_0; // @[LoopConv.scala:84:7]
wire io_cmd_bits_inst_xs2_0; // @[LoopConv.scala:84:7]
wire [4:0] io_cmd_bits_inst_rd_0; // @[LoopConv.scala:84:7]
wire [6:0] io_cmd_bits_inst_opcode_0; // @[LoopConv.scala:84:7]
wire io_cmd_bits_status_debug_0; // @[LoopConv.scala:84:7]
wire io_cmd_bits_status_cease_0; // @[LoopConv.scala:84:7]
wire io_cmd_bits_status_wfi_0; // @[LoopConv.scala:84:7]
wire [31:0] io_cmd_bits_status_isa_0; // @[LoopConv.scala:84:7]
wire [1:0] io_cmd_bits_status_dprv_0; // @[LoopConv.scala:84:7]
wire io_cmd_bits_status_dv_0; // @[LoopConv.scala:84:7]
wire [1:0] io_cmd_bits_status_prv_0; // @[LoopConv.scala:84:7]
wire io_cmd_bits_status_v_0; // @[LoopConv.scala:84:7]
wire io_cmd_bits_status_sd_0; // @[LoopConv.scala:84:7]
wire [22:0] io_cmd_bits_status_zero2_0; // @[LoopConv.scala:84:7]
wire io_cmd_bits_status_mpv_0; // @[LoopConv.scala:84:7]
wire io_cmd_bits_status_gva_0; // @[LoopConv.scala:84:7]
wire io_cmd_bits_status_mbe_0; // @[LoopConv.scala:84:7]
wire io_cmd_bits_status_sbe_0; // @[LoopConv.scala:84:7]
wire [1:0] io_cmd_bits_status_sxl_0; // @[LoopConv.scala:84:7]
wire [1:0] io_cmd_bits_status_uxl_0; // @[LoopConv.scala:84:7]
wire io_cmd_bits_status_sd_rv32_0; // @[LoopConv.scala:84:7]
wire [7:0] io_cmd_bits_status_zero1_0; // @[LoopConv.scala:84:7]
wire io_cmd_bits_status_tsr_0; // @[LoopConv.scala:84:7]
wire io_cmd_bits_status_tw_0; // @[LoopConv.scala:84:7]
wire io_cmd_bits_status_tvm_0; // @[LoopConv.scala:84:7]
wire io_cmd_bits_status_mxr_0; // @[LoopConv.scala:84:7]
wire io_cmd_bits_status_sum_0; // @[LoopConv.scala:84:7]
wire io_cmd_bits_status_mprv_0; // @[LoopConv.scala:84:7]
wire [1:0] io_cmd_bits_status_xs_0; // @[LoopConv.scala:84:7]
wire [1:0] io_cmd_bits_status_fs_0; // @[LoopConv.scala:84:7]
wire [1:0] io_cmd_bits_status_mpp_0; // @[LoopConv.scala:84:7]
wire [1:0] io_cmd_bits_status_vs_0; // @[LoopConv.scala:84:7]
wire io_cmd_bits_status_spp_0; // @[LoopConv.scala:84:7]
wire io_cmd_bits_status_mpie_0; // @[LoopConv.scala:84:7]
wire io_cmd_bits_status_ube_0; // @[LoopConv.scala:84:7]
wire io_cmd_bits_status_spie_0; // @[LoopConv.scala:84:7]
wire io_cmd_bits_status_upie_0; // @[LoopConv.scala:84:7]
wire io_cmd_bits_status_mie_0; // @[LoopConv.scala:84:7]
wire io_cmd_bits_status_hie_0; // @[LoopConv.scala:84:7]
wire io_cmd_bits_status_sie_0; // @[LoopConv.scala:84:7]
wire io_cmd_bits_status_uie_0; // @[LoopConv.scala:84:7]
wire [63:0] io_cmd_bits_rs1_0; // @[LoopConv.scala:84:7]
wire [63:0] io_cmd_bits_rs2_0; // @[LoopConv.scala:84:7]
wire io_cmd_valid_0; // @[LoopConv.scala:84:7]
wire io_idle_0; // @[LoopConv.scala:84:7]
wire io_loop_id_0; // @[LoopConv.scala:84:7]
reg [1:0] state; // @[LoopConv.scala:103:22]
reg [15:0] req_outer_bounds_batch_size; // @[LoopConv.scala:105:16]
reg [15:0] req_outer_bounds_in_row_dim; // @[LoopConv.scala:105:16]
reg [15:0] req_outer_bounds_in_col_dim; // @[LoopConv.scala:105:16]
reg [15:0] req_outer_bounds_in_channels; // @[LoopConv.scala:105:16]
reg [15:0] req_outer_bounds_out_channels; // @[LoopConv.scala:105:16]
reg [15:0] req_outer_bounds_out_col_dim; // @[LoopConv.scala:105:16]
reg [15:0] req_outer_bounds_out_row_dim; // @[LoopConv.scala:105:16]
reg [15:0] req_outer_bounds_out_stride; // @[LoopConv.scala:105:16]
reg [15:0] req_outer_bounds_in_stride; // @[LoopConv.scala:105:16]
reg [15:0] req_outer_bounds_weight_stride; // @[LoopConv.scala:105:16]
reg [15:0] req_outer_bounds_pool_out_row_dim; // @[LoopConv.scala:105:16]
reg [15:0] req_outer_bounds_pool_out_col_dim; // @[LoopConv.scala:105:16]
reg [15:0] req_outer_bounds_stride; // @[LoopConv.scala:105:16]
reg [15:0] req_outer_bounds_padding; // @[LoopConv.scala:105:16]
reg [15:0] req_outer_bounds_kernel_dim; // @[LoopConv.scala:105:16]
reg [15:0] req_outer_bounds_kernel_dilation; // @[LoopConv.scala:105:16]
reg [15:0] req_outer_bounds_pool_size; // @[LoopConv.scala:105:16]
reg [15:0] req_outer_bounds_pool_stride; // @[LoopConv.scala:105:16]
reg [15:0] req_outer_bounds_pool_padding; // @[LoopConv.scala:105:16]
reg [15:0] req_inner_bounds_batches; // @[LoopConv.scala:105:16]
reg [15:0] req_inner_bounds_porows; // @[LoopConv.scala:105:16]
reg [15:0] req_inner_bounds_pocols; // @[LoopConv.scala:105:16]
reg [15:0] req_inner_bounds_pochs; // @[LoopConv.scala:105:16]
reg [15:0] req_inner_bounds_krows; // @[LoopConv.scala:105:16]
reg [15:0] req_inner_bounds_kcols; // @[LoopConv.scala:105:16]
reg [15:0] req_inner_bounds_kchs; // @[LoopConv.scala:105:16]
reg [15:0] req_inner_bounds_lpad; // @[LoopConv.scala:105:16]
reg [15:0] req_inner_bounds_rpad; // @[LoopConv.scala:105:16]
reg [15:0] req_inner_bounds_upad; // @[LoopConv.scala:105:16]
reg [15:0] req_inner_bounds_dpad; // @[LoopConv.scala:105:16]
reg [15:0] req_inner_bounds_plpad; // @[LoopConv.scala:105:16]
reg [15:0] req_inner_bounds_prad; // @[LoopConv.scala:105:16]
reg [15:0] req_inner_bounds_pupad; // @[LoopConv.scala:105:16]
reg [15:0] req_inner_bounds_pdpad; // @[LoopConv.scala:105:16]
reg [15:0] req_inner_bounds_orows; // @[LoopConv.scala:105:16]
reg [15:0] req_inner_bounds_ocols; // @[LoopConv.scala:105:16]
reg [15:0] req_derived_params_ochs; // @[LoopConv.scala:105:16]
reg [15:0] req_derived_params_irows; // @[LoopConv.scala:105:16]
reg [15:0] req_derived_params_icols; // @[LoopConv.scala:105:16]
reg [15:0] req_derived_params_irows_unpadded; // @[LoopConv.scala:105:16]
reg [15:0] req_derived_params_icols_unpadded; // @[LoopConv.scala:105:16]
reg [15:0] req_derived_params_ichs; // @[LoopConv.scala:105:16]
reg [15:0] req_derived_params_out_channels_per_bank; // @[LoopConv.scala:105:16]
reg [15:0] req_derived_params_in_channels_per_bank; // @[LoopConv.scala:105:16]
reg [15:0] req_derived_params_bias_spad_stride; // @[LoopConv.scala:105:16]
reg [15:0] req_derived_params_input_spad_stride; // @[LoopConv.scala:105:16]
reg [15:0] req_derived_params_weight_spad_stride; // @[LoopConv.scala:105:16]
reg [11:0] req_addr_start; // @[LoopConv.scala:105:16]
reg [39:0] req_dram_addr; // @[LoopConv.scala:105:16]
reg req_no_bias; // @[LoopConv.scala:105:16]
reg req_loop_id; // @[LoopConv.scala:105:16]
assign io_loop_id_0 = req_loop_id; // @[LoopConv.scala:84:7, :105:16]
wire _max_ochs_per_mvin_T = req_derived_params_ochs < 16'h10; // @[LoopConv.scala:105:16, :112:36]
wire [15:0] max_ochs_per_mvin = _max_ochs_per_mvin_T ? req_derived_params_ochs : 16'h10; // @[LoopConv.scala:105:16, :112:{30,36}]
wire skip = req_dram_addr == 40'h0; // @[LoopConv.scala:105:16, :114:28]
reg [15:0] b; // @[LoopConv.scala:117:14]
reg [15:0] orow; // @[LoopConv.scala:118:17]
reg [15:0] ocol; // @[LoopConv.scala:119:17]
reg [15:0] och; // @[LoopConv.scala:120:16]
wire [18:0] dram_offset = {1'h0, och, 2'h0}; // @[LoopConv.scala:120:16, :123:25]
wire [31:0] _dram_addr_T = {13'h0, dram_offset}; // @[LoopConv.scala:123:25, :1556:17]
wire [40:0] _dram_addr_T_1 = {1'h0, req_dram_addr} + {9'h0, _dram_addr_T}; // @[LoopConv.scala:105:16, :124:55, :1556:17]
wire [39:0] _dram_addr_T_2 = _dram_addr_T_1[39:0]; // @[LoopConv.scala:124:55]
wire [39:0] dram_addr = req_no_bias ? 40'h0 : _dram_addr_T_2; // @[LoopConv.scala:105:16, :124:{22,55}]
wire [15:0] _spad_addr_T = och / 16'h4; // @[LoopConv.scala:120:16, :125:42, :128:28]
wire [31:0] _spad_addr_T_1 = {16'h0, _spad_addr_T} * {16'h0, req_inner_bounds_batches}; // @[LoopConv.scala:105:16, :125:{42,74}]
wire [47:0] _spad_addr_T_2 = {16'h0, _spad_addr_T_1} * {32'h0, req_inner_bounds_orows}; // @[LoopConv.scala:105:16, :125:{74,84}]
wire [63:0] _spad_addr_T_3 = {16'h0, _spad_addr_T_2} * {48'h0, req_inner_bounds_ocols}; // @[LoopConv.scala:105:16, :125:{84,92}]
wire [64:0] _spad_addr_T_4 = {53'h0, req_addr_start} + {1'h0, _spad_addr_T_3}; // @[LoopConv.scala:105:16, :125:{34,92}]
wire [31:0] _spad_addr_T_5 = {16'h0, b} * {16'h0, req_inner_bounds_orows}; // @[LoopConv.scala:105:16, :117:14, :125:105]
wire [47:0] _spad_addr_T_6 = {16'h0, _spad_addr_T_5} * {32'h0, req_inner_bounds_ocols}; // @[LoopConv.scala:105:16, :125:{105,113}]
wire [65:0] _spad_addr_T_7 = {1'h0, _spad_addr_T_4} + {18'h0, _spad_addr_T_6}; // @[LoopConv.scala:125:{34,100,113}]
wire [31:0] _spad_addr_T_8 = {16'h0, orow} * {16'h0, req_inner_bounds_ocols}; // @[LoopConv.scala:105:16, :118:17, :125:129]
wire [66:0] _spad_addr_T_9 = {1'h0, _spad_addr_T_7} + {35'h0, _spad_addr_T_8}; // @[LoopConv.scala:125:{100,121,129}]
wire [67:0] spad_addr = {1'h0, _spad_addr_T_9} + {52'h0, ocol}; // @[LoopConv.scala:119:17, :125:{121,137}]
wire [16:0] _GEN = {1'h0, req_inner_bounds_ocols}; // @[LoopConv.scala:105:16, :128:21]
wire [16:0] _GEN_0 = {1'h0, ocol}; // @[LoopConv.scala:119:17, :128:21]
wire [16:0] _GEN_1 = _GEN - _GEN_0; // @[LoopConv.scala:128:21]
wire [16:0] _I_T; // @[LoopConv.scala:128:21]
assign _I_T = _GEN_1; // @[LoopConv.scala:128:21]
wire [16:0] _I_T_3; // @[LoopConv.scala:128:64]
assign _I_T_3 = _GEN_1; // @[LoopConv.scala:128:{21,64}]
wire [15:0] _I_T_1 = _I_T[15:0]; // @[LoopConv.scala:128:21]
wire _I_T_2 = _I_T_1 > 16'h4; // @[LoopConv.scala:128:{21,28}]
wire [15:0] _I_T_4 = _I_T_3[15:0]; // @[LoopConv.scala:128:64]
wire [15:0] I = _I_T_2 ? 16'h4 : _I_T_4; // @[LoopConv.scala:128:{14,28,64}]
wire [16:0] _GEN_2 = {1'h0, req_derived_params_ochs}; // @[LoopConv.scala:105:16, :129:20]
wire [16:0] _GEN_3 = {1'h0, och}; // @[LoopConv.scala:120:16, :129:20]
wire [16:0] _GEN_4 = _GEN_2 - _GEN_3; // @[LoopConv.scala:129:20]
wire [16:0] _J_T; // @[LoopConv.scala:129:20]
assign _J_T = _GEN_4; // @[LoopConv.scala:129:20]
wire [16:0] _J_T_3; // @[LoopConv.scala:129:71]
assign _J_T_3 = _GEN_4; // @[LoopConv.scala:129:{20,71}]
wire [15:0] _J_T_1 = _J_T[15:0]; // @[LoopConv.scala:129:20]
wire _J_T_2 = _J_T_1 > max_ochs_per_mvin; // @[LoopConv.scala:112:30, :129:{20,26}]
wire [15:0] _J_T_4 = _J_T_3[15:0]; // @[LoopConv.scala:129:71]
wire [15:0] J = _J_T_2 ? max_ochs_per_mvin : _J_T_4; // @[LoopConv.scala:112:30, :129:{14,26,71}]
wire [63:0] _config_cmd_rs1_T; // @[LoopConv.scala:153:36]
wire [63:0] config_cmd_rs1; // @[LoopConv.scala:141:24]
wire [13:0] config_cmd_rs1_stride; // @[LoopConv.scala:145:28]
assign config_cmd_rs1_stride = req_derived_params_bias_spad_stride[13:0]; // @[LoopConv.scala:105:16, :145:28, :148:25]
wire [18:0] config_cmd_rs1_hi_lo = {config_cmd_rs1_stride, 5'h0}; // @[LoopConv.scala:145:28, :153:36]
wire [52:0] config_cmd_rs1_hi = {34'hFE000000, config_cmd_rs1_hi_lo}; // @[LoopConv.scala:153:36]
assign _config_cmd_rs1_T = {config_cmd_rs1_hi, 11'h111}; // @[LoopConv.scala:153:36]
assign config_cmd_rs1 = _config_cmd_rs1_T; // @[LoopConv.scala:141:24, :153:36]
wire _io_req_ready_T = ~(|state); // @[LoopConv.scala:103:22, :164:25]
wire _io_req_ready_T_1 = ~_command_p_io_busy; // @[LoopConv.scala:138:25, :164:37]
assign _io_req_ready_T_2 = _io_req_ready_T & _io_req_ready_T_1; // @[LoopConv.scala:164:{25,34,37}]
assign io_req_ready_0 = _io_req_ready_T_2; // @[LoopConv.scala:84:7, :164:34]
wire _io_idle_T = ~(|state); // @[LoopConv.scala:103:22, :164:25, :165:20]
wire _io_idle_T_1 = ~_command_p_io_busy; // @[LoopConv.scala:138:25, :164:37, :165:32]
assign _io_idle_T_2 = _io_idle_T & _io_idle_T_1; // @[LoopConv.scala:165:{20,29,32}]
assign io_idle_0 = _io_idle_T_2; // @[LoopConv.scala:84:7, :165:29]
wire _command_p_io_in_valid_T = |state; // @[LoopConv.scala:103:22, :164:25, :168:34]
wire _command_p_io_in_valid_T_1 = ~io_wait_for_prev_loop_0; // @[LoopConv.scala:84:7, :168:46]
wire _command_p_io_in_valid_T_2 = _command_p_io_in_valid_T & _command_p_io_in_valid_T_1; // @[LoopConv.scala:168:{34,43,46}]
wire _command_p_io_in_valid_T_3 = ~skip; // @[LoopConv.scala:114:28, :168:72]
wire _command_p_io_in_valid_T_4 = _command_p_io_in_valid_T_2 & _command_p_io_in_valid_T_3; // @[LoopConv.scala:168:{43,69,72}]
wire _command_p_io_in_bits_cmd_T = state == 2'h1; // @[LoopConv.scala:103:22, :169:41]
wire [6:0] _command_p_io_in_bits_cmd_T_1_inst_funct = _command_p_io_in_bits_cmd_T ? 7'h0 : 7'hE; // @[LoopConv.scala:169:{34,41}, :178:46]
wire [63:0] _command_p_io_in_bits_cmd_T_1_rs1 = _command_p_io_in_bits_cmd_T ? config_cmd_rs1 : 64'h0; // @[LoopConv.scala:141:24, :169:{34,41}]
wire _command_p_io_out_ready_T = ~io_rob_overloaded_0; // @[LoopConv.scala:84:7, :175:45]
wire _command_p_io_out_ready_T_1 = io_cmd_ready_0 & _command_p_io_out_ready_T; // @[LoopConv.scala:84:7, :175:{42,45}]
wire _io_cmd_valid_T = ~io_rob_overloaded_0; // @[LoopConv.scala:84:7, :175:45, :176:45]
assign _io_cmd_valid_T_1 = _command_p_io_out_valid & _io_cmd_valid_T; // @[LoopConv.scala:138:25, :176:{42,45}]
assign io_cmd_valid_0 = _io_cmd_valid_T_1; // @[LoopConv.scala:84:7, :176:42]
wire _T = _command_p_io_out_bits_cmd_inst_funct == 7'hE; // @[LoopConv.scala:138:25, :178:46]
assign io_cmd_bits_rs1_0 = _T ? {24'h0, _command_p_io_out_bits_dram_addr} : _command_p_io_out_bits_cmd_rs1; // @[LoopConv.scala:84:7, :138:25, :177:15, :178:{46,61}, :180:21]
wire [4:0] io_cmd_bits_rs2_lo_hi_1 = mvin_cmd_rs2_num_cols; // @[LoopConv.scala:181:28, :186:37]
wire [2:0] mvin_cmd_rs2_local_addr_result_norm_cmd; // @[LocalAddr.scala:129:26]
wire [2:0] _io_cmd_bits_rs2_T = mvin_cmd_rs2_local_addr_norm_cmd; // @[LoopConv.scala:181:28, :186:37]
wire mvin_cmd_rs2_local_addr_result_garbage_bit; // @[LocalAddr.scala:129:26]
wire [13:0] mvin_cmd_rs2_local_addr_result_data; // @[LocalAddr.scala:129:26]
wire mvin_cmd_rs2_local_addr_garbage_bit; // @[LoopConv.scala:181:28]
wire [13:0] mvin_cmd_rs2_local_addr_data; // @[LoopConv.scala:181:28]
wire [2:0] mvin_cmd_rs2_num_rows; // @[LoopConv.scala:181:28]
assign mvin_cmd_rs2_num_rows = _command_p_io_out_bits_I[2:0]; // @[LoopConv.scala:138:25, :181:28, :183:27]
assign mvin_cmd_rs2_num_cols = _command_p_io_out_bits_J[4:0]; // @[LoopConv.scala:138:25, :181:28, :184:27]
wire _mvin_cmd_rs2_local_addr_result_result_T_6; // @[LocalAddr.scala:108:37]
wire _mvin_cmd_rs2_local_addr_result_result_T_5; // @[LocalAddr.scala:108:37]
wire mvin_cmd_rs2_local_addr_result_result_is_acc_addr = _mvin_cmd_rs2_local_addr_result_result_WIRE_is_acc_addr; // @[LocalAddr.scala:108:{26,37}]
wire _mvin_cmd_rs2_local_addr_result_result_T_4; // @[LocalAddr.scala:108:37]
wire mvin_cmd_rs2_local_addr_result_result_accumulate = _mvin_cmd_rs2_local_addr_result_result_WIRE_accumulate; // @[LocalAddr.scala:108:{26,37}]
wire [2:0] _mvin_cmd_rs2_local_addr_result_result_WIRE_3; // @[LocalAddr.scala:108:37]
wire mvin_cmd_rs2_local_addr_result_result_read_full_acc_row = _mvin_cmd_rs2_local_addr_result_result_WIRE_read_full_acc_row; // @[LocalAddr.scala:108:{26,37}]
wire [10:0] _mvin_cmd_rs2_local_addr_result_result_T_2; // @[LocalAddr.scala:108:37]
wire [2:0] mvin_cmd_rs2_local_addr_result_result_norm_cmd = _mvin_cmd_rs2_local_addr_result_result_WIRE_norm_cmd; // @[LocalAddr.scala:108:{26,37}]
wire _mvin_cmd_rs2_local_addr_result_result_T_1; // @[LocalAddr.scala:108:37]
wire [13:0] _mvin_cmd_rs2_local_addr_result_result_T; // @[LocalAddr.scala:108:37]
wire mvin_cmd_rs2_local_addr_result_result_garbage_bit = _mvin_cmd_rs2_local_addr_result_result_WIRE_garbage_bit; // @[LocalAddr.scala:108:{26,37}]
wire [13:0] mvin_cmd_rs2_local_addr_result_result_data = _mvin_cmd_rs2_local_addr_result_result_WIRE_data; // @[LocalAddr.scala:108:{26,37}]
wire [31:0] _mvin_cmd_rs2_local_addr_result_result_WIRE_1 = _command_p_io_out_bits_spad_addr[31:0]; // @[LoopConv.scala:138:25]
assign _mvin_cmd_rs2_local_addr_result_result_T = _mvin_cmd_rs2_local_addr_result_result_WIRE_1[13:0]; // @[LocalAddr.scala:108:37]
assign _mvin_cmd_rs2_local_addr_result_result_WIRE_data = _mvin_cmd_rs2_local_addr_result_result_T; // @[LocalAddr.scala:108:37]
assign _mvin_cmd_rs2_local_addr_result_result_T_1 = _mvin_cmd_rs2_local_addr_result_result_WIRE_1[14]; // @[LocalAddr.scala:108:37]
assign _mvin_cmd_rs2_local_addr_result_result_WIRE_garbage_bit = _mvin_cmd_rs2_local_addr_result_result_T_1; // @[LocalAddr.scala:108:37]
assign _mvin_cmd_rs2_local_addr_result_result_T_2 = _mvin_cmd_rs2_local_addr_result_result_WIRE_1[25:15]; // @[LocalAddr.scala:108:37]
wire [10:0] _mvin_cmd_rs2_local_addr_result_result_WIRE_garbage = _mvin_cmd_rs2_local_addr_result_result_T_2; // @[LocalAddr.scala:108:37]
wire [2:0] _mvin_cmd_rs2_local_addr_result_result_T_3 = _mvin_cmd_rs2_local_addr_result_result_WIRE_1[28:26]; // @[LocalAddr.scala:108:37]
wire [2:0] _mvin_cmd_rs2_local_addr_result_result_WIRE_2 = _mvin_cmd_rs2_local_addr_result_result_T_3; // @[LocalAddr.scala:108:37]
assign _mvin_cmd_rs2_local_addr_result_result_WIRE_3 = _mvin_cmd_rs2_local_addr_result_result_WIRE_2; // @[LocalAddr.scala:108:37]
assign _mvin_cmd_rs2_local_addr_result_result_WIRE_norm_cmd = _mvin_cmd_rs2_local_addr_result_result_WIRE_3; // @[LocalAddr.scala:108:37]
assign _mvin_cmd_rs2_local_addr_result_result_T_4 = _mvin_cmd_rs2_local_addr_result_result_WIRE_1[29]; // @[LocalAddr.scala:108:37]
assign _mvin_cmd_rs2_local_addr_result_result_WIRE_read_full_acc_row = _mvin_cmd_rs2_local_addr_result_result_T_4; // @[LocalAddr.scala:108:37]
assign _mvin_cmd_rs2_local_addr_result_result_T_5 = _mvin_cmd_rs2_local_addr_result_result_WIRE_1[30]; // @[LocalAddr.scala:108:37]
assign _mvin_cmd_rs2_local_addr_result_result_WIRE_accumulate = _mvin_cmd_rs2_local_addr_result_result_T_5; // @[LocalAddr.scala:108:37]
assign _mvin_cmd_rs2_local_addr_result_result_T_6 = _mvin_cmd_rs2_local_addr_result_result_WIRE_1[31]; // @[LocalAddr.scala:108:37]
assign _mvin_cmd_rs2_local_addr_result_result_WIRE_is_acc_addr = _mvin_cmd_rs2_local_addr_result_result_T_6; // @[LocalAddr.scala:108:37]
assign mvin_cmd_rs2_local_addr_result_norm_cmd = mvin_cmd_rs2_local_addr_result_result_norm_cmd; // @[LocalAddr.scala:108:26, :129:26]
assign mvin_cmd_rs2_local_addr_result_garbage_bit = mvin_cmd_rs2_local_addr_result_result_garbage_bit; // @[LocalAddr.scala:108:26, :129:26]
assign mvin_cmd_rs2_local_addr_result_data = mvin_cmd_rs2_local_addr_result_result_data; // @[LocalAddr.scala:108:26, :129:26]
assign mvin_cmd_rs2_local_addr_norm_cmd = mvin_cmd_rs2_local_addr_result_norm_cmd; // @[LoopConv.scala:181:28]
assign mvin_cmd_rs2_local_addr_garbage_bit = mvin_cmd_rs2_local_addr_result_garbage_bit; // @[LoopConv.scala:181:28]
assign mvin_cmd_rs2_local_addr_data = mvin_cmd_rs2_local_addr_result_data; // @[LoopConv.scala:181:28]
wire [11:0] io_cmd_bits_rs2_lo_hi = {11'h0, mvin_cmd_rs2_local_addr_garbage_bit}; // @[LoopConv.scala:181:28, :186:37]
wire [25:0] io_cmd_bits_rs2_lo = {io_cmd_bits_rs2_lo_hi, mvin_cmd_rs2_local_addr_data}; // @[LoopConv.scala:181:28, :186:37]
wire [3:0] io_cmd_bits_rs2_hi_lo = {1'h0, _io_cmd_bits_rs2_T}; // @[LoopConv.scala:186:37]
wire [5:0] io_cmd_bits_rs2_hi = {2'h2, io_cmd_bits_rs2_hi_lo}; // @[LoopConv.scala:186:37]
wire [31:0] _io_cmd_bits_rs2_T_1 = {io_cmd_bits_rs2_hi, io_cmd_bits_rs2_lo}; // @[LoopConv.scala:186:37]
wire [36:0] io_cmd_bits_rs2_lo_1 = {io_cmd_bits_rs2_lo_hi_1, _io_cmd_bits_rs2_T_1}; // @[LoopConv.scala:186:37]
wire [15:0] io_cmd_bits_rs2_hi_hi_1 = {13'h0, mvin_cmd_rs2_num_rows}; // @[LoopConv.scala:181:28, :186:37]
wire [26:0] io_cmd_bits_rs2_hi_1 = {io_cmd_bits_rs2_hi_hi_1, 11'h0}; // @[LoopConv.scala:186:37]
wire [63:0] _io_cmd_bits_rs2_T_2 = {io_cmd_bits_rs2_hi_1, io_cmd_bits_rs2_lo_1}; // @[LoopConv.scala:186:37]
assign io_cmd_bits_rs2_0 = _T ? _io_cmd_bits_rs2_T_2 : _command_p_io_out_bits_cmd_rs2; // @[LoopConv.scala:84:7, :138:25, :177:15, :178:{46,61}, :186:{21,37}]
wire [16:0] _next_och_max_T = _GEN_2 - 17'h1; // @[Util.scala:39:28]
wire [15:0] next_och_max = _next_och_max_T[15:0]; // @[Util.scala:39:28]
wire [16:0] _GEN_5 = _GEN_3 + {1'h0, max_ochs_per_mvin}; // @[Util.scala:41:15]
wire [16:0] _next_och_T; // @[Util.scala:41:15]
assign _next_och_T = _GEN_5; // @[Util.scala:41:15]
wire [16:0] _next_och_T_3; // @[Util.scala:43:11]
assign _next_och_T_3 = _GEN_5; // @[Util.scala:41:15, :43:11]
wire [15:0] _next_och_T_1 = _next_och_T[15:0]; // @[Util.scala:41:15]
wire _next_och_T_4 = _next_och_T_3 > {1'h0, next_och_max}; // @[Util.scala:39:28, :43:{11,17}]
wire [15:0] _next_och_T_5 = _next_och_T_4 ? 16'h0 : _next_och_T_1; // @[Mux.scala:126:16]
wire [15:0] next_och = _next_och_T_5; // @[Mux.scala:126:16]
wire _GEN_6 = next_och == 16'h0; // @[Mux.scala:126:16]
wire _next_ocol_T; // @[LoopConv.scala:197:68]
assign _next_ocol_T = _GEN_6; // @[LoopConv.scala:197:68]
wire _next_orow_T_1; // @[LoopConv.scala:198:80]
assign _next_orow_T_1 = _GEN_6; // @[LoopConv.scala:197:68, :198:80]
wire _next_b_T_3; // @[LoopConv.scala:199:97]
assign _next_b_T_3 = _GEN_6; // @[LoopConv.scala:197:68, :199:97]
wire _state_T_5; // @[LoopConv.scala:206:89]
assign _state_T_5 = _GEN_6; // @[LoopConv.scala:197:68, :206:89]
wire [16:0] _next_ocol_max_T = _GEN - 17'h1; // @[Util.scala:39:28]
wire [15:0] next_ocol_max = _next_ocol_max_T[15:0]; // @[Util.scala:39:28]
wire [16:0] _GEN_7 = _GEN_0 + 17'h4; // @[Util.scala:41:15]
wire [16:0] _next_ocol_T_1; // @[Util.scala:41:15]
assign _next_ocol_T_1 = _GEN_7; // @[Util.scala:41:15]
wire [16:0] _next_ocol_T_4; // @[Util.scala:43:11]
assign _next_ocol_T_4 = _GEN_7; // @[Util.scala:41:15, :43:11]
wire [15:0] _next_ocol_T_2 = _next_ocol_T_1[15:0]; // @[Util.scala:41:15]
wire _next_ocol_T_3 = ~_next_ocol_T; // @[Util.scala:42:8]
wire _next_ocol_T_5 = _next_ocol_T_4 > {1'h0, next_ocol_max}; // @[Util.scala:39:28, :43:{11,17}]
wire [15:0] _next_ocol_T_6 = _next_ocol_T_5 ? 16'h0 : _next_ocol_T_2; // @[Mux.scala:126:16]
wire [15:0] next_ocol = _next_ocol_T_3 ? ocol : _next_ocol_T_6; // @[Mux.scala:126:16]
wire _GEN_8 = next_ocol == 16'h0; // @[Mux.scala:126:16]
wire _next_orow_T; // @[LoopConv.scala:198:60]
assign _next_orow_T = _GEN_8; // @[LoopConv.scala:198:60]
wire _next_b_T_1; // @[LoopConv.scala:199:77]
assign _next_b_T_1 = _GEN_8; // @[LoopConv.scala:198:60, :199:77]
wire _state_T_3; // @[LoopConv.scala:206:69]
assign _state_T_3 = _GEN_8; // @[LoopConv.scala:198:60, :206:69]
wire _next_orow_T_2 = _next_orow_T & _next_orow_T_1; // @[LoopConv.scala:198:{60,68,80}]
wire [16:0] _next_orow_max_T = {1'h0, req_inner_bounds_orows} - 17'h1; // @[Util.scala:39:28]
wire [15:0] next_orow_max = _next_orow_max_T[15:0]; // @[Util.scala:39:28]
wire [16:0] _GEN_9 = {1'h0, orow} + 17'h1; // @[Util.scala:41:15]
wire [16:0] _next_orow_T_3; // @[Util.scala:41:15]
assign _next_orow_T_3 = _GEN_9; // @[Util.scala:41:15]
wire [16:0] _next_orow_T_6; // @[Util.scala:43:11]
assign _next_orow_T_6 = _GEN_9; // @[Util.scala:41:15, :43:11]
wire [15:0] _next_orow_T_4 = _next_orow_T_3[15:0]; // @[Util.scala:41:15]
wire _next_orow_T_5 = ~_next_orow_T_2; // @[Util.scala:42:8]
wire _next_orow_T_7 = _next_orow_T_6 > {1'h0, next_orow_max}; // @[Util.scala:39:28, :43:{11,17}]
wire [15:0] _next_orow_T_8 = _next_orow_T_7 ? 16'h0 : _next_orow_T_4; // @[Mux.scala:126:16]
wire [15:0] next_orow = _next_orow_T_5 ? orow : _next_orow_T_8; // @[Mux.scala:126:16]
wire _GEN_10 = next_orow == 16'h0; // @[Mux.scala:126:16]
wire _next_b_T; // @[LoopConv.scala:199:56]
assign _next_b_T = _GEN_10; // @[LoopConv.scala:199:56]
wire _state_T_1; // @[LoopConv.scala:206:48]
assign _state_T_1 = _GEN_10; // @[LoopConv.scala:199:56, :206:48]
wire _next_b_T_2 = _next_b_T & _next_b_T_1; // @[LoopConv.scala:199:{56,64,77}]
wire _next_b_T_4 = _next_b_T_2 & _next_b_T_3; // @[LoopConv.scala:199:{64,85,97}]
wire [16:0] _next_b_max_T = {1'h0, req_inner_bounds_batches} - 17'h1; // @[Util.scala:39:28]
wire [15:0] next_b_max = _next_b_max_T[15:0]; // @[Util.scala:39:28]
wire [16:0] _GEN_11 = {1'h0, b} + 17'h1; // @[Util.scala:41:15]
wire [16:0] _next_b_T_5; // @[Util.scala:41:15]
assign _next_b_T_5 = _GEN_11; // @[Util.scala:41:15]
wire [16:0] _next_b_T_8; // @[Util.scala:43:11]
assign _next_b_T_8 = _GEN_11; // @[Util.scala:41:15, :43:11]
wire [15:0] _next_b_T_6 = _next_b_T_5[15:0]; // @[Util.scala:41:15]
wire _next_b_T_7 = ~_next_b_T_4; // @[Util.scala:42:8]
wire _next_b_T_9 = _next_b_T_8 > {1'h0, next_b_max}; // @[Util.scala:39:28, :43:{11,17}]
wire [15:0] _next_b_T_10 = _next_b_T_9 ? 16'h0 : _next_b_T_6; // @[Mux.scala:126:16]
wire [15:0] next_b = _next_b_T_7 ? b : _next_b_T_10; // @[Mux.scala:126:16]
wire _state_T = next_b == 16'h0; // @[Mux.scala:126:16]
wire _state_T_2 = _state_T & _state_T_1; // @[LoopConv.scala:206:{27,35,48}]
wire _state_T_4 = _state_T_2 & _state_T_3; // @[LoopConv.scala:206:{35,56,69}]
wire _state_T_6 = _state_T_4 & _state_T_5; // @[LoopConv.scala:206:{56,77,89}]
wire [1:0] _state_T_7 = {~_state_T_6, 1'h0}; // @[LoopConv.scala:206:{19,77}]
wire _T_1 = _command_p_io_in_ready & _command_p_io_in_valid_T_4; // @[Decoupled.scala:51:35]
wire _T_3 = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[LoopConv.scala:84:7]
if (reset) // @[LoopConv.scala:84:7]
state <= 2'h0; // @[LoopConv.scala:103:22]
else if (_T_3) // @[Decoupled.scala:51:35]
state <= 2'h1; // @[LoopConv.scala:103:22, :169:41]
else if (skip) // @[LoopConv.scala:114:28]
state <= 2'h0; // @[LoopConv.scala:103:22]
else if (_T_1) // @[Decoupled.scala:51:35]
state <= _command_p_io_in_bits_cmd_T ? 2'h2 : _state_T_7; // @[LoopConv.scala:103:22, :169:41, :193:29, :194:13, :206:{13,19}]
if (_T_3) begin // @[Decoupled.scala:51:35]
req_outer_bounds_batch_size <= io_req_bits_outer_bounds_batch_size_0; // @[LoopConv.scala:84:7, :105:16]
req_outer_bounds_in_row_dim <= io_req_bits_outer_bounds_in_row_dim_0; // @[LoopConv.scala:84:7, :105:16]
req_outer_bounds_in_col_dim <= io_req_bits_outer_bounds_in_col_dim_0; // @[LoopConv.scala:84:7, :105:16]
req_outer_bounds_in_channels <= io_req_bits_outer_bounds_in_channels_0; // @[LoopConv.scala:84:7, :105:16]
req_outer_bounds_out_channels <= io_req_bits_outer_bounds_out_channels_0; // @[LoopConv.scala:84:7, :105:16]
req_outer_bounds_out_col_dim <= io_req_bits_outer_bounds_out_col_dim_0; // @[LoopConv.scala:84:7, :105:16]
req_outer_bounds_out_row_dim <= io_req_bits_outer_bounds_out_row_dim_0; // @[LoopConv.scala:84:7, :105:16]
req_outer_bounds_out_stride <= io_req_bits_outer_bounds_out_stride_0; // @[LoopConv.scala:84:7, :105:16]
req_outer_bounds_in_stride <= io_req_bits_outer_bounds_in_stride_0; // @[LoopConv.scala:84:7, :105:16]
req_outer_bounds_weight_stride <= io_req_bits_outer_bounds_weight_stride_0; // @[LoopConv.scala:84:7, :105:16]
req_outer_bounds_pool_out_row_dim <= io_req_bits_outer_bounds_pool_out_row_dim_0; // @[LoopConv.scala:84:7, :105:16]
req_outer_bounds_pool_out_col_dim <= io_req_bits_outer_bounds_pool_out_col_dim_0; // @[LoopConv.scala:84:7, :105:16]
req_outer_bounds_stride <= io_req_bits_outer_bounds_stride_0; // @[LoopConv.scala:84:7, :105:16]
req_outer_bounds_padding <= io_req_bits_outer_bounds_padding_0; // @[LoopConv.scala:84:7, :105:16]
req_outer_bounds_kernel_dim <= io_req_bits_outer_bounds_kernel_dim_0; // @[LoopConv.scala:84:7, :105:16]
req_outer_bounds_kernel_dilation <= io_req_bits_outer_bounds_kernel_dilation_0; // @[LoopConv.scala:84:7, :105:16]
req_outer_bounds_pool_size <= io_req_bits_outer_bounds_pool_size_0; // @[LoopConv.scala:84:7, :105:16]
req_outer_bounds_pool_stride <= io_req_bits_outer_bounds_pool_stride_0; // @[LoopConv.scala:84:7, :105:16]
req_outer_bounds_pool_padding <= io_req_bits_outer_bounds_pool_padding_0; // @[LoopConv.scala:84:7, :105:16]
req_inner_bounds_batches <= io_req_bits_inner_bounds_batches_0; // @[LoopConv.scala:84:7, :105:16]
req_inner_bounds_porows <= io_req_bits_inner_bounds_porows_0; // @[LoopConv.scala:84:7, :105:16]
req_inner_bounds_pocols <= io_req_bits_inner_bounds_pocols_0; // @[LoopConv.scala:84:7, :105:16]
req_inner_bounds_pochs <= io_req_bits_inner_bounds_pochs_0; // @[LoopConv.scala:84:7, :105:16]
req_inner_bounds_krows <= io_req_bits_inner_bounds_krows_0; // @[LoopConv.scala:84:7, :105:16]
req_inner_bounds_kcols <= io_req_bits_inner_bounds_kcols_0; // @[LoopConv.scala:84:7, :105:16]
req_inner_bounds_kchs <= io_req_bits_inner_bounds_kchs_0; // @[LoopConv.scala:84:7, :105:16]
req_inner_bounds_lpad <= io_req_bits_inner_bounds_lpad_0; // @[LoopConv.scala:84:7, :105:16]
req_inner_bounds_rpad <= io_req_bits_inner_bounds_rpad_0; // @[LoopConv.scala:84:7, :105:16]
req_inner_bounds_upad <= io_req_bits_inner_bounds_upad_0; // @[LoopConv.scala:84:7, :105:16]
req_inner_bounds_dpad <= io_req_bits_inner_bounds_dpad_0; // @[LoopConv.scala:84:7, :105:16]
req_inner_bounds_plpad <= io_req_bits_inner_bounds_plpad_0; // @[LoopConv.scala:84:7, :105:16]
req_inner_bounds_prad <= io_req_bits_inner_bounds_prad_0; // @[LoopConv.scala:84:7, :105:16]
req_inner_bounds_pupad <= io_req_bits_inner_bounds_pupad_0; // @[LoopConv.scala:84:7, :105:16]
req_inner_bounds_pdpad <= io_req_bits_inner_bounds_pdpad_0; // @[LoopConv.scala:84:7, :105:16]
req_inner_bounds_orows <= io_req_bits_inner_bounds_orows_0; // @[LoopConv.scala:84:7, :105:16]
req_inner_bounds_ocols <= io_req_bits_inner_bounds_ocols_0; // @[LoopConv.scala:84:7, :105:16]
req_derived_params_ochs <= io_req_bits_derived_params_ochs_0; // @[LoopConv.scala:84:7, :105:16]
req_derived_params_irows <= io_req_bits_derived_params_irows_0; // @[LoopConv.scala:84:7, :105:16]
req_derived_params_icols <= io_req_bits_derived_params_icols_0; // @[LoopConv.scala:84:7, :105:16]
req_derived_params_irows_unpadded <= io_req_bits_derived_params_irows_unpadded_0; // @[LoopConv.scala:84:7, :105:16]
req_derived_params_icols_unpadded <= io_req_bits_derived_params_icols_unpadded_0; // @[LoopConv.scala:84:7, :105:16]
req_derived_params_ichs <= io_req_bits_derived_params_ichs_0; // @[LoopConv.scala:84:7, :105:16]
req_derived_params_out_channels_per_bank <= io_req_bits_derived_params_out_channels_per_bank_0; // @[LoopConv.scala:84:7, :105:16]
req_derived_params_in_channels_per_bank <= io_req_bits_derived_params_in_channels_per_bank_0; // @[LoopConv.scala:84:7, :105:16]
req_derived_params_bias_spad_stride <= io_req_bits_derived_params_bias_spad_stride_0; // @[LoopConv.scala:84:7, :105:16]
req_derived_params_input_spad_stride <= io_req_bits_derived_params_input_spad_stride_0; // @[LoopConv.scala:84:7, :105:16]
req_derived_params_weight_spad_stride <= io_req_bits_derived_params_weight_spad_stride_0; // @[LoopConv.scala:84:7, :105:16]
req_addr_start <= io_req_bits_addr_start_0; // @[LoopConv.scala:84:7, :105:16]
req_dram_addr <= io_req_bits_dram_addr_0; // @[LoopConv.scala:84:7, :105:16]
req_no_bias <= io_req_bits_no_bias_0; // @[LoopConv.scala:84:7, :105:16]
req_loop_id <= io_req_bits_loop_id_0; // @[LoopConv.scala:84:7, :105:16]
b <= 16'h0; // @[LoopConv.scala:117:14]
orow <= 16'h0; // @[LoopConv.scala:118:17]
ocol <= 16'h0; // @[LoopConv.scala:119:17]
och <= 16'h0; // @[LoopConv.scala:120:16]
end
else if (skip | ~_T_1 | _command_p_io_in_bits_cmd_T) begin // @[Decoupled.scala:51:35]
end
else begin // @[LoopConv.scala:120:16, :190:15, :192:36, :193:29]
b <= next_b; // @[Mux.scala:126:16]
orow <= next_orow; // @[Mux.scala:126:16]
ocol <= next_ocol; // @[Mux.scala:126:16]
och <= next_och; // @[Mux.scala:126:16]
end
always @(posedge)
Pipeline_11 command_p ( // @[LoopConv.scala:138:25]
.clock (clock),
.reset (reset),
.io_in_ready (_command_p_io_in_ready),
.io_in_valid (_command_p_io_in_valid_T_4), // @[LoopConv.scala:168:69]
.io_in_bits_cmd_inst_funct (_command_p_io_in_bits_cmd_T_1_inst_funct), // @[LoopConv.scala:169:34]
.io_in_bits_cmd_rs1 (_command_p_io_in_bits_cmd_T_1_rs1), // @[LoopConv.scala:169:34]
.io_in_bits_dram_addr (dram_addr), // @[LoopConv.scala:124:22]
.io_in_bits_spad_addr (spad_addr), // @[LoopConv.scala:125:137]
.io_in_bits_I (I), // @[LoopConv.scala:128:14]
.io_in_bits_J (J), // @[LoopConv.scala:129:14]
.io_out_ready (_command_p_io_out_ready_T_1), // @[LoopConv.scala:175:42]
.io_out_valid (_command_p_io_out_valid),
.io_out_bits_cmd_inst_funct (_command_p_io_out_bits_cmd_inst_funct),
.io_out_bits_cmd_inst_rs2 (io_cmd_bits_inst_rs2_0),
.io_out_bits_cmd_inst_rs1 (io_cmd_bits_inst_rs1_0),
.io_out_bits_cmd_inst_xd (io_cmd_bits_inst_xd_0),
.io_out_bits_cmd_inst_xs1 (io_cmd_bits_inst_xs1_0),
.io_out_bits_cmd_inst_xs2 (io_cmd_bits_inst_xs2_0),
.io_out_bits_cmd_inst_rd (io_cmd_bits_inst_rd_0),
.io_out_bits_cmd_inst_opcode (io_cmd_bits_inst_opcode_0),
.io_out_bits_cmd_rs1 (_command_p_io_out_bits_cmd_rs1),
.io_out_bits_cmd_rs2 (_command_p_io_out_bits_cmd_rs2),
.io_out_bits_cmd_status_debug (io_cmd_bits_status_debug_0),
.io_out_bits_cmd_status_cease (io_cmd_bits_status_cease_0),
.io_out_bits_cmd_status_wfi (io_cmd_bits_status_wfi_0),
.io_out_bits_cmd_status_isa (io_cmd_bits_status_isa_0),
.io_out_bits_cmd_status_dprv (io_cmd_bits_status_dprv_0),
.io_out_bits_cmd_status_dv (io_cmd_bits_status_dv_0),
.io_out_bits_cmd_status_prv (io_cmd_bits_status_prv_0),
.io_out_bits_cmd_status_v (io_cmd_bits_status_v_0),
.io_out_bits_cmd_status_sd (io_cmd_bits_status_sd_0),
.io_out_bits_cmd_status_zero2 (io_cmd_bits_status_zero2_0),
.io_out_bits_cmd_status_mpv (io_cmd_bits_status_mpv_0),
.io_out_bits_cmd_status_gva (io_cmd_bits_status_gva_0),
.io_out_bits_cmd_status_mbe (io_cmd_bits_status_mbe_0),
.io_out_bits_cmd_status_sbe (io_cmd_bits_status_sbe_0),
.io_out_bits_cmd_status_sxl (io_cmd_bits_status_sxl_0),
.io_out_bits_cmd_status_uxl (io_cmd_bits_status_uxl_0),
.io_out_bits_cmd_status_sd_rv32 (io_cmd_bits_status_sd_rv32_0),
.io_out_bits_cmd_status_zero1 (io_cmd_bits_status_zero1_0),
.io_out_bits_cmd_status_tsr (io_cmd_bits_status_tsr_0),
.io_out_bits_cmd_status_tw (io_cmd_bits_status_tw_0),
.io_out_bits_cmd_status_tvm (io_cmd_bits_status_tvm_0),
.io_out_bits_cmd_status_mxr (io_cmd_bits_status_mxr_0),
.io_out_bits_cmd_status_sum (io_cmd_bits_status_sum_0),
.io_out_bits_cmd_status_mprv (io_cmd_bits_status_mprv_0),
.io_out_bits_cmd_status_xs (io_cmd_bits_status_xs_0),
.io_out_bits_cmd_status_fs (io_cmd_bits_status_fs_0),
.io_out_bits_cmd_status_mpp (io_cmd_bits_status_mpp_0),
.io_out_bits_cmd_status_vs (io_cmd_bits_status_vs_0),
.io_out_bits_cmd_status_spp (io_cmd_bits_status_spp_0),
.io_out_bits_cmd_status_mpie (io_cmd_bits_status_mpie_0),
.io_out_bits_cmd_status_ube (io_cmd_bits_status_ube_0),
.io_out_bits_cmd_status_spie (io_cmd_bits_status_spie_0),
.io_out_bits_cmd_status_upie (io_cmd_bits_status_upie_0),
.io_out_bits_cmd_status_mie (io_cmd_bits_status_mie_0),
.io_out_bits_cmd_status_hie (io_cmd_bits_status_hie_0),
.io_out_bits_cmd_status_sie (io_cmd_bits_status_sie_0),
.io_out_bits_cmd_status_uie (io_cmd_bits_status_uie_0),
.io_out_bits_dram_addr (_command_p_io_out_bits_dram_addr),
.io_out_bits_spad_addr (_command_p_io_out_bits_spad_addr),
.io_out_bits_I (_command_p_io_out_bits_I),
.io_out_bits_J (_command_p_io_out_bits_J),
.io_busy (_command_p_io_busy)
); // @[LoopConv.scala:138:25]
assign io_cmd_bits_inst_funct_0 = _command_p_io_out_bits_cmd_inst_funct; // @[LoopConv.scala:84:7, :138:25]
assign io_req_ready = io_req_ready_0; // @[LoopConv.scala:84:7]
assign io_cmd_valid = io_cmd_valid_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_inst_funct = io_cmd_bits_inst_funct_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_inst_rs2 = io_cmd_bits_inst_rs2_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_inst_rs1 = io_cmd_bits_inst_rs1_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_inst_xd = io_cmd_bits_inst_xd_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_inst_xs1 = io_cmd_bits_inst_xs1_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_inst_xs2 = io_cmd_bits_inst_xs2_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_inst_rd = io_cmd_bits_inst_rd_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_inst_opcode = io_cmd_bits_inst_opcode_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_rs1 = io_cmd_bits_rs1_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_rs2 = io_cmd_bits_rs2_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_status_debug = io_cmd_bits_status_debug_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_status_cease = io_cmd_bits_status_cease_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_status_wfi = io_cmd_bits_status_wfi_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_status_isa = io_cmd_bits_status_isa_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_status_dprv = io_cmd_bits_status_dprv_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_status_dv = io_cmd_bits_status_dv_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_status_prv = io_cmd_bits_status_prv_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_status_v = io_cmd_bits_status_v_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_status_sd = io_cmd_bits_status_sd_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_status_zero2 = io_cmd_bits_status_zero2_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_status_mpv = io_cmd_bits_status_mpv_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_status_gva = io_cmd_bits_status_gva_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_status_mbe = io_cmd_bits_status_mbe_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_status_sbe = io_cmd_bits_status_sbe_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_status_sxl = io_cmd_bits_status_sxl_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_status_uxl = io_cmd_bits_status_uxl_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_status_sd_rv32 = io_cmd_bits_status_sd_rv32_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_status_zero1 = io_cmd_bits_status_zero1_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_status_tsr = io_cmd_bits_status_tsr_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_status_tw = io_cmd_bits_status_tw_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_status_tvm = io_cmd_bits_status_tvm_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_status_mxr = io_cmd_bits_status_mxr_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_status_sum = io_cmd_bits_status_sum_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_status_mprv = io_cmd_bits_status_mprv_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_status_xs = io_cmd_bits_status_xs_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_status_fs = io_cmd_bits_status_fs_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_status_mpp = io_cmd_bits_status_mpp_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_status_vs = io_cmd_bits_status_vs_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_status_spp = io_cmd_bits_status_spp_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_status_mpie = io_cmd_bits_status_mpie_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_status_ube = io_cmd_bits_status_ube_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_status_spie = io_cmd_bits_status_spie_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_status_upie = io_cmd_bits_status_upie_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_status_mie = io_cmd_bits_status_mie_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_status_hie = io_cmd_bits_status_hie_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_status_sie = io_cmd_bits_status_sie_0; // @[LoopConv.scala:84:7]
assign io_cmd_bits_status_uie = io_cmd_bits_status_uie_0; // @[LoopConv.scala:84:7]
assign io_idle = io_idle_0; // @[LoopConv.scala:84:7]
assign io_loop_id = io_loop_id_0; // @[LoopConv.scala:84:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MemAddrCalcUnit :
input clock : Clock
input reset : Reset
output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, rs1_data : UInt<65>, rs2_data : UInt<65>, rs3_data : UInt<65>, pred_data : UInt<1>, kill : UInt<1>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, predicated : UInt<1>, data : UInt<65>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}, addr : UInt<40>, mxcpt : { valid : UInt<1>, bits : UInt<25>}, sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}}}, flip brupdate : { b1 : { resolve_mask : UInt<8>, mispredict_mask : UInt<8>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, bypass : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}[0], flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}[0], flip mcontext : UInt<0>, flip scontext : UInt<0>}
connect io.resp.valid, UInt<1>(0h0)
invalidate io.resp.bits.sfence.bits.hg
invalidate io.resp.bits.sfence.bits.hv
invalidate io.resp.bits.sfence.bits.asid
invalidate io.resp.bits.sfence.bits.addr
invalidate io.resp.bits.sfence.bits.rs2
invalidate io.resp.bits.sfence.bits.rs1
invalidate io.resp.bits.sfence.valid
invalidate io.resp.bits.mxcpt.bits
invalidate io.resp.bits.mxcpt.valid
invalidate io.resp.bits.addr
invalidate io.resp.bits.fflags.bits.flags
invalidate io.resp.bits.fflags.bits.uop.debug_tsrc
invalidate io.resp.bits.fflags.bits.uop.debug_fsrc
invalidate io.resp.bits.fflags.bits.uop.bp_xcpt_if
invalidate io.resp.bits.fflags.bits.uop.bp_debug_if
invalidate io.resp.bits.fflags.bits.uop.xcpt_ma_if
invalidate io.resp.bits.fflags.bits.uop.xcpt_ae_if
invalidate io.resp.bits.fflags.bits.uop.xcpt_pf_if
invalidate io.resp.bits.fflags.bits.uop.fp_single
invalidate io.resp.bits.fflags.bits.uop.fp_val
invalidate io.resp.bits.fflags.bits.uop.frs3_en
invalidate io.resp.bits.fflags.bits.uop.lrs2_rtype
invalidate io.resp.bits.fflags.bits.uop.lrs1_rtype
invalidate io.resp.bits.fflags.bits.uop.dst_rtype
invalidate io.resp.bits.fflags.bits.uop.ldst_val
invalidate io.resp.bits.fflags.bits.uop.lrs3
invalidate io.resp.bits.fflags.bits.uop.lrs2
invalidate io.resp.bits.fflags.bits.uop.lrs1
invalidate io.resp.bits.fflags.bits.uop.ldst
invalidate io.resp.bits.fflags.bits.uop.ldst_is_rs1
invalidate io.resp.bits.fflags.bits.uop.flush_on_commit
invalidate io.resp.bits.fflags.bits.uop.is_unique
invalidate io.resp.bits.fflags.bits.uop.is_sys_pc2epc
invalidate io.resp.bits.fflags.bits.uop.uses_stq
invalidate io.resp.bits.fflags.bits.uop.uses_ldq
invalidate io.resp.bits.fflags.bits.uop.is_amo
invalidate io.resp.bits.fflags.bits.uop.is_fencei
invalidate io.resp.bits.fflags.bits.uop.is_fence
invalidate io.resp.bits.fflags.bits.uop.mem_signed
invalidate io.resp.bits.fflags.bits.uop.mem_size
invalidate io.resp.bits.fflags.bits.uop.mem_cmd
invalidate io.resp.bits.fflags.bits.uop.bypassable
invalidate io.resp.bits.fflags.bits.uop.exc_cause
invalidate io.resp.bits.fflags.bits.uop.exception
invalidate io.resp.bits.fflags.bits.uop.stale_pdst
invalidate io.resp.bits.fflags.bits.uop.ppred_busy
invalidate io.resp.bits.fflags.bits.uop.prs3_busy
invalidate io.resp.bits.fflags.bits.uop.prs2_busy
invalidate io.resp.bits.fflags.bits.uop.prs1_busy
invalidate io.resp.bits.fflags.bits.uop.ppred
invalidate io.resp.bits.fflags.bits.uop.prs3
invalidate io.resp.bits.fflags.bits.uop.prs2
invalidate io.resp.bits.fflags.bits.uop.prs1
invalidate io.resp.bits.fflags.bits.uop.pdst
invalidate io.resp.bits.fflags.bits.uop.rxq_idx
invalidate io.resp.bits.fflags.bits.uop.stq_idx
invalidate io.resp.bits.fflags.bits.uop.ldq_idx
invalidate io.resp.bits.fflags.bits.uop.rob_idx
invalidate io.resp.bits.fflags.bits.uop.csr_addr
invalidate io.resp.bits.fflags.bits.uop.imm_packed
invalidate io.resp.bits.fflags.bits.uop.taken
invalidate io.resp.bits.fflags.bits.uop.pc_lob
invalidate io.resp.bits.fflags.bits.uop.edge_inst
invalidate io.resp.bits.fflags.bits.uop.ftq_idx
invalidate io.resp.bits.fflags.bits.uop.br_tag
invalidate io.resp.bits.fflags.bits.uop.br_mask
invalidate io.resp.bits.fflags.bits.uop.is_sfb
invalidate io.resp.bits.fflags.bits.uop.is_jal
invalidate io.resp.bits.fflags.bits.uop.is_jalr
invalidate io.resp.bits.fflags.bits.uop.is_br
invalidate io.resp.bits.fflags.bits.uop.iw_p2_poisoned
invalidate io.resp.bits.fflags.bits.uop.iw_p1_poisoned
invalidate io.resp.bits.fflags.bits.uop.iw_state
invalidate io.resp.bits.fflags.bits.uop.ctrl.is_std
invalidate io.resp.bits.fflags.bits.uop.ctrl.is_sta
invalidate io.resp.bits.fflags.bits.uop.ctrl.is_load
invalidate io.resp.bits.fflags.bits.uop.ctrl.csr_cmd
invalidate io.resp.bits.fflags.bits.uop.ctrl.fcn_dw
invalidate io.resp.bits.fflags.bits.uop.ctrl.op_fcn
invalidate io.resp.bits.fflags.bits.uop.ctrl.imm_sel
invalidate io.resp.bits.fflags.bits.uop.ctrl.op2_sel
invalidate io.resp.bits.fflags.bits.uop.ctrl.op1_sel
invalidate io.resp.bits.fflags.bits.uop.ctrl.br_type
invalidate io.resp.bits.fflags.bits.uop.fu_code
invalidate io.resp.bits.fflags.bits.uop.iq_type
invalidate io.resp.bits.fflags.bits.uop.debug_pc
invalidate io.resp.bits.fflags.bits.uop.is_rvc
invalidate io.resp.bits.fflags.bits.uop.debug_inst
invalidate io.resp.bits.fflags.bits.uop.inst
invalidate io.resp.bits.fflags.bits.uop.uopc
invalidate io.resp.bits.fflags.valid
invalidate io.resp.bits.data
invalidate io.resp.bits.predicated
invalidate io.resp.bits.uop.debug_tsrc
invalidate io.resp.bits.uop.debug_fsrc
invalidate io.resp.bits.uop.bp_xcpt_if
invalidate io.resp.bits.uop.bp_debug_if
invalidate io.resp.bits.uop.xcpt_ma_if
invalidate io.resp.bits.uop.xcpt_ae_if
invalidate io.resp.bits.uop.xcpt_pf_if
invalidate io.resp.bits.uop.fp_single
invalidate io.resp.bits.uop.fp_val
invalidate io.resp.bits.uop.frs3_en
invalidate io.resp.bits.uop.lrs2_rtype
invalidate io.resp.bits.uop.lrs1_rtype
invalidate io.resp.bits.uop.dst_rtype
invalidate io.resp.bits.uop.ldst_val
invalidate io.resp.bits.uop.lrs3
invalidate io.resp.bits.uop.lrs2
invalidate io.resp.bits.uop.lrs1
invalidate io.resp.bits.uop.ldst
invalidate io.resp.bits.uop.ldst_is_rs1
invalidate io.resp.bits.uop.flush_on_commit
invalidate io.resp.bits.uop.is_unique
invalidate io.resp.bits.uop.is_sys_pc2epc
invalidate io.resp.bits.uop.uses_stq
invalidate io.resp.bits.uop.uses_ldq
invalidate io.resp.bits.uop.is_amo
invalidate io.resp.bits.uop.is_fencei
invalidate io.resp.bits.uop.is_fence
invalidate io.resp.bits.uop.mem_signed
invalidate io.resp.bits.uop.mem_size
invalidate io.resp.bits.uop.mem_cmd
invalidate io.resp.bits.uop.bypassable
invalidate io.resp.bits.uop.exc_cause
invalidate io.resp.bits.uop.exception
invalidate io.resp.bits.uop.stale_pdst
invalidate io.resp.bits.uop.ppred_busy
invalidate io.resp.bits.uop.prs3_busy
invalidate io.resp.bits.uop.prs2_busy
invalidate io.resp.bits.uop.prs1_busy
invalidate io.resp.bits.uop.ppred
invalidate io.resp.bits.uop.prs3
invalidate io.resp.bits.uop.prs2
invalidate io.resp.bits.uop.prs1
invalidate io.resp.bits.uop.pdst
invalidate io.resp.bits.uop.rxq_idx
invalidate io.resp.bits.uop.stq_idx
invalidate io.resp.bits.uop.ldq_idx
invalidate io.resp.bits.uop.rob_idx
invalidate io.resp.bits.uop.csr_addr
invalidate io.resp.bits.uop.imm_packed
invalidate io.resp.bits.uop.taken
invalidate io.resp.bits.uop.pc_lob
invalidate io.resp.bits.uop.edge_inst
invalidate io.resp.bits.uop.ftq_idx
invalidate io.resp.bits.uop.br_tag
invalidate io.resp.bits.uop.br_mask
invalidate io.resp.bits.uop.is_sfb
invalidate io.resp.bits.uop.is_jal
invalidate io.resp.bits.uop.is_jalr
invalidate io.resp.bits.uop.is_br
invalidate io.resp.bits.uop.iw_p2_poisoned
invalidate io.resp.bits.uop.iw_p1_poisoned
invalidate io.resp.bits.uop.iw_state
invalidate io.resp.bits.uop.ctrl.is_std
invalidate io.resp.bits.uop.ctrl.is_sta
invalidate io.resp.bits.uop.ctrl.is_load
invalidate io.resp.bits.uop.ctrl.csr_cmd
invalidate io.resp.bits.uop.ctrl.fcn_dw
invalidate io.resp.bits.uop.ctrl.op_fcn
invalidate io.resp.bits.uop.ctrl.imm_sel
invalidate io.resp.bits.uop.ctrl.op2_sel
invalidate io.resp.bits.uop.ctrl.op1_sel
invalidate io.resp.bits.uop.ctrl.br_type
invalidate io.resp.bits.uop.fu_code
invalidate io.resp.bits.uop.iq_type
invalidate io.resp.bits.uop.debug_pc
invalidate io.resp.bits.uop.is_rvc
invalidate io.resp.bits.uop.debug_inst
invalidate io.resp.bits.uop.inst
invalidate io.resp.bits.uop.uopc
connect io.req.ready, UInt<1>(0h1)
node _io_resp_valid_T = and(io.brupdate.b1.mispredict_mask, io.req.bits.uop.br_mask)
node _io_resp_valid_T_1 = neq(_io_resp_valid_T, UInt<1>(0h0))
node _io_resp_valid_T_2 = eq(_io_resp_valid_T_1, UInt<1>(0h0))
node _io_resp_valid_T_3 = and(io.req.valid, _io_resp_valid_T_2)
connect io.resp.valid, _io_resp_valid_T_3
connect io.resp.bits.predicated, UInt<1>(0h0)
connect io.resp.bits.uop, io.req.bits.uop
node _io_resp_bits_uop_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _io_resp_bits_uop_br_mask_T_1 = and(io.req.bits.uop.br_mask, _io_resp_bits_uop_br_mask_T)
connect io.resp.bits.uop.br_mask, _io_resp_bits_uop_br_mask_T_1
node _sum_T = asSInt(io.req.bits.rs1_data)
node _sum_T_1 = bits(io.req.bits.uop.imm_packed, 19, 8)
node _sum_T_2 = asSInt(_sum_T_1)
node _sum_T_3 = add(_sum_T, _sum_T_2)
node _sum_T_4 = tail(_sum_T_3, 1)
node _sum_T_5 = asSInt(_sum_T_4)
node sum = asUInt(_sum_T_5)
node _ea_sign_T = bits(sum, 38, 38)
node _ea_sign_T_1 = bits(sum, 63, 39)
node _ea_sign_T_2 = not(_ea_sign_T_1)
node _ea_sign_T_3 = eq(_ea_sign_T_2, UInt<1>(0h0))
node _ea_sign_T_4 = bits(sum, 63, 39)
node _ea_sign_T_5 = neq(_ea_sign_T_4, UInt<1>(0h0))
node ea_sign = mux(_ea_sign_T, _ea_sign_T_3, _ea_sign_T_5)
node _effective_address_T = bits(sum, 38, 0)
node effective_address = cat(ea_sign, _effective_address_T)
connect io.resp.bits.addr, effective_address
connect io.resp.bits.data, io.req.bits.rs2_data
node _T = and(io.req.valid, io.req.bits.uop.ctrl.is_std)
node _T_1 = bits(io.resp.bits.data, 64, 64)
node _T_2 = eq(_T_1, UInt<1>(0h1))
node _T_3 = and(_T, _T_2)
node _T_4 = eq(_T_3, UInt<1>(0h0))
node _T_5 = asUInt(reset)
node _T_6 = eq(_T_5, UInt<1>(0h0))
when _T_6 :
node _T_7 = eq(_T_4, UInt<1>(0h0))
when _T_7 :
printf(clock, UInt<1>(0h1), "Assertion failed: 65th bit set in MemAddrCalcUnit.\n at functional-unit.scala:504 assert (!(io.req.valid && io.req.bits.uop.ctrl.is_std &&\n") : printf
assert(clock, _T_4, UInt<1>(0h1), "") : assert
node _T_8 = and(io.req.valid, io.req.bits.uop.ctrl.is_std)
node _T_9 = and(_T_8, io.req.bits.uop.fp_val)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = asUInt(reset)
node _T_12 = eq(_T_11, UInt<1>(0h0))
when _T_12 :
node _T_13 = eq(_T_10, UInt<1>(0h0))
when _T_13 :
printf(clock, UInt<1>(0h1), "Assertion failed: FP store-data should now be going through a different unit.\n at functional-unit.scala:507 assert (!(io.req.valid && io.req.bits.uop.ctrl.is_std && io.req.bits.uop.fp_val),\n") : printf_1
assert(clock, _T_10, UInt<1>(0h1), "") : assert_1
node _T_14 = and(io.req.bits.uop.fp_val, io.req.valid)
node _T_15 = neq(io.req.bits.uop.uopc, UInt<7>(0h1))
node _T_16 = and(_T_14, _T_15)
node _T_17 = neq(io.req.bits.uop.uopc, UInt<7>(0h2))
node _T_18 = and(_T_16, _T_17)
node _T_19 = eq(_T_18, UInt<1>(0h0))
node _T_20 = asUInt(reset)
node _T_21 = eq(_T_20, UInt<1>(0h0))
when _T_21 :
node _T_22 = eq(_T_19, UInt<1>(0h0))
when _T_22 :
printf(clock, UInt<1>(0h1), "Assertion failed: [maddrcalc] assert we never get store data in here.\n at functional-unit.scala:511 assert (!(io.req.bits.uop.fp_val && io.req.valid && io.req.bits.uop.uopc =/=\n") : printf_2
assert(clock, _T_19, UInt<1>(0h1), "") : assert_2
node _misaligned_T = eq(io.req.bits.uop.mem_size, UInt<1>(0h1))
node _misaligned_T_1 = bits(effective_address, 0, 0)
node _misaligned_T_2 = neq(_misaligned_T_1, UInt<1>(0h0))
node _misaligned_T_3 = and(_misaligned_T, _misaligned_T_2)
node _misaligned_T_4 = eq(io.req.bits.uop.mem_size, UInt<2>(0h2))
node _misaligned_T_5 = bits(effective_address, 1, 0)
node _misaligned_T_6 = neq(_misaligned_T_5, UInt<1>(0h0))
node _misaligned_T_7 = and(_misaligned_T_4, _misaligned_T_6)
node _misaligned_T_8 = or(_misaligned_T_3, _misaligned_T_7)
node _misaligned_T_9 = eq(io.req.bits.uop.mem_size, UInt<2>(0h3))
node _misaligned_T_10 = bits(effective_address, 2, 0)
node _misaligned_T_11 = neq(_misaligned_T_10, UInt<1>(0h0))
node _misaligned_T_12 = and(_misaligned_T_9, _misaligned_T_11)
node misaligned = or(_misaligned_T_8, _misaligned_T_12)
inst bkptu of BreakpointUnit_4
connect bkptu.clock, clock
connect bkptu.reset, reset
connect bkptu.io.status.uie, io.status.uie
connect bkptu.io.status.sie, io.status.sie
connect bkptu.io.status.hie, io.status.hie
connect bkptu.io.status.mie, io.status.mie
connect bkptu.io.status.upie, io.status.upie
connect bkptu.io.status.spie, io.status.spie
connect bkptu.io.status.ube, io.status.ube
connect bkptu.io.status.mpie, io.status.mpie
connect bkptu.io.status.spp, io.status.spp
connect bkptu.io.status.vs, io.status.vs
connect bkptu.io.status.mpp, io.status.mpp
connect bkptu.io.status.fs, io.status.fs
connect bkptu.io.status.xs, io.status.xs
connect bkptu.io.status.mprv, io.status.mprv
connect bkptu.io.status.sum, io.status.sum
connect bkptu.io.status.mxr, io.status.mxr
connect bkptu.io.status.tvm, io.status.tvm
connect bkptu.io.status.tw, io.status.tw
connect bkptu.io.status.tsr, io.status.tsr
connect bkptu.io.status.zero1, io.status.zero1
connect bkptu.io.status.sd_rv32, io.status.sd_rv32
connect bkptu.io.status.uxl, io.status.uxl
connect bkptu.io.status.sxl, io.status.sxl
connect bkptu.io.status.sbe, io.status.sbe
connect bkptu.io.status.mbe, io.status.mbe
connect bkptu.io.status.gva, io.status.gva
connect bkptu.io.status.mpv, io.status.mpv
connect bkptu.io.status.zero2, io.status.zero2
connect bkptu.io.status.sd, io.status.sd
connect bkptu.io.status.v, io.status.v
connect bkptu.io.status.prv, io.status.prv
connect bkptu.io.status.dv, io.status.dv
connect bkptu.io.status.dprv, io.status.dprv
connect bkptu.io.status.isa, io.status.isa
connect bkptu.io.status.wfi, io.status.wfi
connect bkptu.io.status.cease, io.status.cease
connect bkptu.io.status.debug, io.status.debug
invalidate bkptu.io.pc
connect bkptu.io.ea, effective_address
connect bkptu.io.mcontext, io.mcontext
connect bkptu.io.scontext, io.scontext
node _ma_ld_T = eq(io.req.bits.uop.uopc, UInt<7>(0h1))
node _ma_ld_T_1 = and(io.req.valid, _ma_ld_T)
node ma_ld = and(_ma_ld_T_1, misaligned)
node _ma_st_T = eq(io.req.bits.uop.uopc, UInt<7>(0h2))
node _ma_st_T_1 = eq(io.req.bits.uop.uopc, UInt<7>(0h43))
node _ma_st_T_2 = or(_ma_st_T, _ma_st_T_1)
node _ma_st_T_3 = and(io.req.valid, _ma_st_T_2)
node ma_st = and(_ma_st_T_3, misaligned)
node _dbg_bp_T = eq(io.req.bits.uop.uopc, UInt<7>(0h1))
node _dbg_bp_T_1 = and(_dbg_bp_T, bkptu.io.debug_ld)
node _dbg_bp_T_2 = eq(io.req.bits.uop.uopc, UInt<7>(0h2))
node _dbg_bp_T_3 = and(_dbg_bp_T_2, bkptu.io.debug_st)
node _dbg_bp_T_4 = or(_dbg_bp_T_1, _dbg_bp_T_3)
node dbg_bp = and(io.req.valid, _dbg_bp_T_4)
node _bp_T = eq(io.req.bits.uop.uopc, UInt<7>(0h1))
node _bp_T_1 = and(_bp_T, bkptu.io.xcpt_ld)
node _bp_T_2 = eq(io.req.bits.uop.uopc, UInt<7>(0h2))
node _bp_T_3 = and(_bp_T_2, bkptu.io.xcpt_st)
node _bp_T_4 = or(_bp_T_1, _bp_T_3)
node bp = and(io.req.valid, _bp_T_4)
node _T_23 = or(ma_ld, ma_st)
node _T_24 = or(_T_23, dbg_bp)
node xcpt_val = or(_T_24, bp)
node _T_25 = mux(dbg_bp, UInt<4>(0he), UInt<2>(0h3))
node _T_26 = mux(ma_st, UInt<3>(0h6), _T_25)
node xcpt_cause = mux(ma_ld, UInt<3>(0h4), _T_26)
connect io.resp.bits.mxcpt.valid, xcpt_val
connect io.resp.bits.mxcpt.bits, xcpt_cause
node _T_27 = and(ma_ld, ma_st)
node _T_28 = eq(_T_27, UInt<1>(0h0))
node _T_29 = asUInt(reset)
node _T_30 = eq(_T_29, UInt<1>(0h0))
when _T_30 :
node _T_31 = eq(_T_28, UInt<1>(0h0))
when _T_31 :
printf(clock, UInt<1>(0h1), "Assertion failed: Mutually-exclusive exceptions are firing.\n at functional-unit.scala:547 assert (!(ma_ld && ma_st), \"Mutually-exclusive exceptions are firing.\")\n") : printf_3
assert(clock, _T_28, UInt<1>(0h1), "") : assert_3
node _io_resp_bits_sfence_valid_T = eq(io.req.bits.uop.mem_cmd, UInt<5>(0h14))
node _io_resp_bits_sfence_valid_T_1 = and(io.req.valid, _io_resp_bits_sfence_valid_T)
connect io.resp.bits.sfence.valid, _io_resp_bits_sfence_valid_T_1
node _io_resp_bits_sfence_bits_rs1_T = bits(io.req.bits.uop.mem_size, 0, 0)
connect io.resp.bits.sfence.bits.rs1, _io_resp_bits_sfence_bits_rs1_T
node _io_resp_bits_sfence_bits_rs2_T = bits(io.req.bits.uop.mem_size, 1, 1)
connect io.resp.bits.sfence.bits.rs2, _io_resp_bits_sfence_bits_rs2_T
connect io.resp.bits.sfence.bits.addr, io.req.bits.rs1_data
connect io.resp.bits.sfence.bits.asid, io.req.bits.rs2_data | module MemAddrCalcUnit( // @[functional-unit.scala:482:7]
input clock, // @[functional-unit.scala:482:7]
input reset, // @[functional-unit.scala:482:7]
input io_req_valid, // @[functional-unit.scala:168:14]
input [6:0] io_req_bits_uop_uopc, // @[functional-unit.scala:168:14]
input [31:0] io_req_bits_uop_inst, // @[functional-unit.scala:168:14]
input [31:0] io_req_bits_uop_debug_inst, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_rvc, // @[functional-unit.scala:168:14]
input [39:0] io_req_bits_uop_debug_pc, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_iq_type, // @[functional-unit.scala:168:14]
input [9:0] io_req_bits_uop_fu_code, // @[functional-unit.scala:168:14]
input [3:0] io_req_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14]
input [4:0] io_req_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_iw_state, // @[functional-unit.scala:168:14]
input io_req_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14]
input io_req_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_br, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_jalr, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_jal, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_sfb, // @[functional-unit.scala:168:14]
input [7:0] io_req_bits_uop_br_mask, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_br_tag, // @[functional-unit.scala:168:14]
input [3:0] io_req_bits_uop_ftq_idx, // @[functional-unit.scala:168:14]
input io_req_bits_uop_edge_inst, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_pc_lob, // @[functional-unit.scala:168:14]
input io_req_bits_uop_taken, // @[functional-unit.scala:168:14]
input [19:0] io_req_bits_uop_imm_packed, // @[functional-unit.scala:168:14]
input [11:0] io_req_bits_uop_csr_addr, // @[functional-unit.scala:168:14]
input [4:0] io_req_bits_uop_rob_idx, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_ldq_idx, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_stq_idx, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_rxq_idx, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_pdst, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_prs1, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_prs2, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_prs3, // @[functional-unit.scala:168:14]
input [3:0] io_req_bits_uop_ppred, // @[functional-unit.scala:168:14]
input io_req_bits_uop_prs1_busy, // @[functional-unit.scala:168:14]
input io_req_bits_uop_prs2_busy, // @[functional-unit.scala:168:14]
input io_req_bits_uop_prs3_busy, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ppred_busy, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_stale_pdst, // @[functional-unit.scala:168:14]
input io_req_bits_uop_exception, // @[functional-unit.scala:168:14]
input [63:0] io_req_bits_uop_exc_cause, // @[functional-unit.scala:168:14]
input io_req_bits_uop_bypassable, // @[functional-unit.scala:168:14]
input [4:0] io_req_bits_uop_mem_cmd, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_mem_size, // @[functional-unit.scala:168:14]
input io_req_bits_uop_mem_signed, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_fence, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_fencei, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_amo, // @[functional-unit.scala:168:14]
input io_req_bits_uop_uses_ldq, // @[functional-unit.scala:168:14]
input io_req_bits_uop_uses_stq, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_unique, // @[functional-unit.scala:168:14]
input io_req_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_ldst, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_lrs1, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_lrs2, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_lrs3, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ldst_val, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_dst_rtype, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14]
input io_req_bits_uop_frs3_en, // @[functional-unit.scala:168:14]
input io_req_bits_uop_fp_val, // @[functional-unit.scala:168:14]
input io_req_bits_uop_fp_single, // @[functional-unit.scala:168:14]
input io_req_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14]
input io_req_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14]
input io_req_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14]
input io_req_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14]
input io_req_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14]
input [64:0] io_req_bits_rs1_data, // @[functional-unit.scala:168:14]
input [64:0] io_req_bits_rs2_data, // @[functional-unit.scala:168:14]
input io_req_bits_kill, // @[functional-unit.scala:168:14]
output io_resp_valid, // @[functional-unit.scala:168:14]
output [6:0] io_resp_bits_uop_uopc, // @[functional-unit.scala:168:14]
output [31:0] io_resp_bits_uop_inst, // @[functional-unit.scala:168:14]
output [31:0] io_resp_bits_uop_debug_inst, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_rvc, // @[functional-unit.scala:168:14]
output [39:0] io_resp_bits_uop_debug_pc, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_iq_type, // @[functional-unit.scala:168:14]
output [9:0] io_resp_bits_uop_fu_code, // @[functional-unit.scala:168:14]
output [3:0] io_resp_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_iw_state, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_br, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_jalr, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_jal, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_sfb, // @[functional-unit.scala:168:14]
output [7:0] io_resp_bits_uop_br_mask, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_br_tag, // @[functional-unit.scala:168:14]
output [3:0] io_resp_bits_uop_ftq_idx, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_edge_inst, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_pc_lob, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_taken, // @[functional-unit.scala:168:14]
output [19:0] io_resp_bits_uop_imm_packed, // @[functional-unit.scala:168:14]
output [11:0] io_resp_bits_uop_csr_addr, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_uop_rob_idx, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_ldq_idx, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_stq_idx, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_rxq_idx, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_pdst, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_prs1, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_prs2, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_prs3, // @[functional-unit.scala:168:14]
output [3:0] io_resp_bits_uop_ppred, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_prs1_busy, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_prs2_busy, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_prs3_busy, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ppred_busy, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_stale_pdst, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_exception, // @[functional-unit.scala:168:14]
output [63:0] io_resp_bits_uop_exc_cause, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_bypassable, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_uop_mem_cmd, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_mem_size, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_mem_signed, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_fence, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_fencei, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_amo, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_uses_ldq, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_uses_stq, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_unique, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_ldst, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_lrs1, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_lrs2, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_lrs3, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ldst_val, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_dst_rtype, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_frs3_en, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_fp_val, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_fp_single, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14]
output [64:0] io_resp_bits_data, // @[functional-unit.scala:168:14]
output [39:0] io_resp_bits_addr, // @[functional-unit.scala:168:14]
output io_resp_bits_mxcpt_valid, // @[functional-unit.scala:168:14]
output [24:0] io_resp_bits_mxcpt_bits, // @[functional-unit.scala:168:14]
output io_resp_bits_sfence_valid, // @[functional-unit.scala:168:14]
output io_resp_bits_sfence_bits_rs1, // @[functional-unit.scala:168:14]
output io_resp_bits_sfence_bits_rs2, // @[functional-unit.scala:168:14]
output [38:0] io_resp_bits_sfence_bits_addr, // @[functional-unit.scala:168:14]
output io_resp_bits_sfence_bits_asid, // @[functional-unit.scala:168:14]
input [7:0] io_brupdate_b1_resolve_mask, // @[functional-unit.scala:168:14]
input [7:0] io_brupdate_b1_mispredict_mask, // @[functional-unit.scala:168:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[functional-unit.scala:168:14]
input [31:0] io_brupdate_b2_uop_inst, // @[functional-unit.scala:168:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_rvc, // @[functional-unit.scala:168:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[functional-unit.scala:168:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[functional-unit.scala:168:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_br, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_jalr, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_jal, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_sfb, // @[functional-unit.scala:168:14]
input [7:0] io_brupdate_b2_uop_br_mask, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_br_tag, // @[functional-unit.scala:168:14]
input [3:0] io_brupdate_b2_uop_ftq_idx, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_edge_inst, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_taken, // @[functional-unit.scala:168:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[functional-unit.scala:168:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[functional-unit.scala:168:14]
input [4:0] io_brupdate_b2_uop_rob_idx, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_ldq_idx, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_stq_idx, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_pdst, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_prs1, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_prs2, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_prs3, // @[functional-unit.scala:168:14]
input [3:0] io_brupdate_b2_uop_ppred, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_prs1_busy, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_prs2_busy, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_prs3_busy, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ppred_busy, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_stale_pdst, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_exception, // @[functional-unit.scala:168:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_bypassable, // @[functional-unit.scala:168:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_mem_signed, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_fence, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_fencei, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_amo, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_uses_ldq, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_uses_stq, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_unique, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_flush_on_commit, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ldst_val, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_frs3_en, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_fp_val, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_fp_single, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_bp_debug_if, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[functional-unit.scala:168:14]
input io_brupdate_b2_valid, // @[functional-unit.scala:168:14]
input io_brupdate_b2_mispredict, // @[functional-unit.scala:168:14]
input io_brupdate_b2_taken, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_cfi_type, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_pc_sel, // @[functional-unit.scala:168:14]
input [39:0] io_brupdate_b2_jalr_target, // @[functional-unit.scala:168:14]
input [20:0] io_brupdate_b2_target_offset, // @[functional-unit.scala:168:14]
input io_status_debug, // @[functional-unit.scala:168:14]
input io_status_cease, // @[functional-unit.scala:168:14]
input io_status_wfi, // @[functional-unit.scala:168:14]
input [1:0] io_status_dprv, // @[functional-unit.scala:168:14]
input io_status_dv, // @[functional-unit.scala:168:14]
input [1:0] io_status_prv, // @[functional-unit.scala:168:14]
input io_status_v, // @[functional-unit.scala:168:14]
input io_status_sd, // @[functional-unit.scala:168:14]
input io_status_mpv, // @[functional-unit.scala:168:14]
input io_status_gva, // @[functional-unit.scala:168:14]
input io_status_tsr, // @[functional-unit.scala:168:14]
input io_status_tw, // @[functional-unit.scala:168:14]
input io_status_tvm, // @[functional-unit.scala:168:14]
input io_status_mxr, // @[functional-unit.scala:168:14]
input io_status_sum, // @[functional-unit.scala:168:14]
input io_status_mprv, // @[functional-unit.scala:168:14]
input [1:0] io_status_fs, // @[functional-unit.scala:168:14]
input [1:0] io_status_mpp, // @[functional-unit.scala:168:14]
input io_status_spp, // @[functional-unit.scala:168:14]
input io_status_mpie, // @[functional-unit.scala:168:14]
input io_status_spie, // @[functional-unit.scala:168:14]
input io_status_mie, // @[functional-unit.scala:168:14]
input io_status_sie // @[functional-unit.scala:168:14]
);
wire io_req_valid_0 = io_req_valid; // @[functional-unit.scala:482:7]
wire [6:0] io_req_bits_uop_uopc_0 = io_req_bits_uop_uopc; // @[functional-unit.scala:482:7]
wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[functional-unit.scala:482:7]
wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[functional-unit.scala:482:7]
wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[functional-unit.scala:482:7]
wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[functional-unit.scala:482:7]
wire [2:0] io_req_bits_uop_iq_type_0 = io_req_bits_uop_iq_type; // @[functional-unit.scala:482:7]
wire [9:0] io_req_bits_uop_fu_code_0 = io_req_bits_uop_fu_code; // @[functional-unit.scala:482:7]
wire [3:0] io_req_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type; // @[functional-unit.scala:482:7]
wire [1:0] io_req_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel; // @[functional-unit.scala:482:7]
wire [2:0] io_req_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel; // @[functional-unit.scala:482:7]
wire [2:0] io_req_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel; // @[functional-unit.scala:482:7]
wire [4:0] io_req_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn; // @[functional-unit.scala:482:7]
wire io_req_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw; // @[functional-unit.scala:482:7]
wire [2:0] io_req_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd; // @[functional-unit.scala:482:7]
wire io_req_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load; // @[functional-unit.scala:482:7]
wire io_req_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta; // @[functional-unit.scala:482:7]
wire io_req_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std; // @[functional-unit.scala:482:7]
wire [1:0] io_req_bits_uop_iw_state_0 = io_req_bits_uop_iw_state; // @[functional-unit.scala:482:7]
wire io_req_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned; // @[functional-unit.scala:482:7]
wire io_req_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned; // @[functional-unit.scala:482:7]
wire io_req_bits_uop_is_br_0 = io_req_bits_uop_is_br; // @[functional-unit.scala:482:7]
wire io_req_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr; // @[functional-unit.scala:482:7]
wire io_req_bits_uop_is_jal_0 = io_req_bits_uop_is_jal; // @[functional-unit.scala:482:7]
wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[functional-unit.scala:482:7]
wire [7:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[functional-unit.scala:482:7]
wire [2:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[functional-unit.scala:482:7]
wire [3:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[functional-unit.scala:482:7]
wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[functional-unit.scala:482:7]
wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[functional-unit.scala:482:7]
wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[functional-unit.scala:482:7]
wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[functional-unit.scala:482:7]
wire [11:0] io_req_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr; // @[functional-unit.scala:482:7]
wire [4:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[functional-unit.scala:482:7]
wire [2:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[functional-unit.scala:482:7]
wire [2:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[functional-unit.scala:482:7]
wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[functional-unit.scala:482:7]
wire [5:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[functional-unit.scala:482:7]
wire [5:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[functional-unit.scala:482:7]
wire [5:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[functional-unit.scala:482:7]
wire [5:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[functional-unit.scala:482:7]
wire [3:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[functional-unit.scala:482:7]
wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[functional-unit.scala:482:7]
wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[functional-unit.scala:482:7]
wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[functional-unit.scala:482:7]
wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[functional-unit.scala:482:7]
wire [5:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[functional-unit.scala:482:7]
wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[functional-unit.scala:482:7]
wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[functional-unit.scala:482:7]
wire io_req_bits_uop_bypassable_0 = io_req_bits_uop_bypassable; // @[functional-unit.scala:482:7]
wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[functional-unit.scala:482:7]
wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[functional-unit.scala:482:7]
wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[functional-unit.scala:482:7]
wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[functional-unit.scala:482:7]
wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[functional-unit.scala:482:7]
wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[functional-unit.scala:482:7]
wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[functional-unit.scala:482:7]
wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[functional-unit.scala:482:7]
wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[functional-unit.scala:482:7]
wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[functional-unit.scala:482:7]
wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[functional-unit.scala:482:7]
wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[functional-unit.scala:482:7]
wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[functional-unit.scala:482:7]
wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[functional-unit.scala:482:7]
wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[functional-unit.scala:482:7]
wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[functional-unit.scala:482:7]
wire io_req_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val; // @[functional-unit.scala:482:7]
wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[functional-unit.scala:482:7]
wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[functional-unit.scala:482:7]
wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[functional-unit.scala:482:7]
wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[functional-unit.scala:482:7]
wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[functional-unit.scala:482:7]
wire io_req_bits_uop_fp_single_0 = io_req_bits_uop_fp_single; // @[functional-unit.scala:482:7]
wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[functional-unit.scala:482:7]
wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[functional-unit.scala:482:7]
wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[functional-unit.scala:482:7]
wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[functional-unit.scala:482:7]
wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[functional-unit.scala:482:7]
wire [1:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[functional-unit.scala:482:7]
wire [1:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[functional-unit.scala:482:7]
wire [64:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data; // @[functional-unit.scala:482:7]
wire [64:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data; // @[functional-unit.scala:482:7]
wire io_req_bits_kill_0 = io_req_bits_kill; // @[functional-unit.scala:482:7]
wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[functional-unit.scala:482:7]
wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[functional-unit.scala:482:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[functional-unit.scala:482:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[functional-unit.scala:482:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[functional-unit.scala:482:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[functional-unit.scala:482:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[functional-unit.scala:482:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[functional-unit.scala:482:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[functional-unit.scala:482:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[functional-unit.scala:482:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[functional-unit.scala:482:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[functional-unit.scala:482:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[functional-unit.scala:482:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[functional-unit.scala:482:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[functional-unit.scala:482:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[functional-unit.scala:482:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[functional-unit.scala:482:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[functional-unit.scala:482:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[functional-unit.scala:482:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[functional-unit.scala:482:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[functional-unit.scala:482:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[functional-unit.scala:482:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[functional-unit.scala:482:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[functional-unit.scala:482:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[functional-unit.scala:482:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[functional-unit.scala:482:7]
wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[functional-unit.scala:482:7]
wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[functional-unit.scala:482:7]
wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[functional-unit.scala:482:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[functional-unit.scala:482:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[functional-unit.scala:482:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[functional-unit.scala:482:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[functional-unit.scala:482:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[functional-unit.scala:482:7]
wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[functional-unit.scala:482:7]
wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[functional-unit.scala:482:7]
wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[functional-unit.scala:482:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[functional-unit.scala:482:7]
wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[functional-unit.scala:482:7]
wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[functional-unit.scala:482:7]
wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[functional-unit.scala:482:7]
wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[functional-unit.scala:482:7]
wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[functional-unit.scala:482:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[functional-unit.scala:482:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[functional-unit.scala:482:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[functional-unit.scala:482:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[functional-unit.scala:482:7]
wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[functional-unit.scala:482:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[functional-unit.scala:482:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[functional-unit.scala:482:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[functional-unit.scala:482:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[functional-unit.scala:482:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[functional-unit.scala:482:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[functional-unit.scala:482:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[functional-unit.scala:482:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[functional-unit.scala:482:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[functional-unit.scala:482:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[functional-unit.scala:482:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[functional-unit.scala:482:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[functional-unit.scala:482:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[functional-unit.scala:482:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[functional-unit.scala:482:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[functional-unit.scala:482:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[functional-unit.scala:482:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[functional-unit.scala:482:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[functional-unit.scala:482:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[functional-unit.scala:482:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[functional-unit.scala:482:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[functional-unit.scala:482:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[functional-unit.scala:482:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[functional-unit.scala:482:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[functional-unit.scala:482:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[functional-unit.scala:482:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[functional-unit.scala:482:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[functional-unit.scala:482:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[functional-unit.scala:482:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[functional-unit.scala:482:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[functional-unit.scala:482:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[functional-unit.scala:482:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[functional-unit.scala:482:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[functional-unit.scala:482:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[functional-unit.scala:482:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[functional-unit.scala:482:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[functional-unit.scala:482:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[functional-unit.scala:482:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[functional-unit.scala:482:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[functional-unit.scala:482:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[functional-unit.scala:482:7]
wire io_status_debug_0 = io_status_debug; // @[functional-unit.scala:482:7]
wire io_status_cease_0 = io_status_cease; // @[functional-unit.scala:482:7]
wire io_status_wfi_0 = io_status_wfi; // @[functional-unit.scala:482:7]
wire [1:0] io_status_dprv_0 = io_status_dprv; // @[functional-unit.scala:482:7]
wire io_status_dv_0 = io_status_dv; // @[functional-unit.scala:482:7]
wire [1:0] io_status_prv_0 = io_status_prv; // @[functional-unit.scala:482:7]
wire io_status_v_0 = io_status_v; // @[functional-unit.scala:482:7]
wire io_status_sd_0 = io_status_sd; // @[functional-unit.scala:482:7]
wire io_status_mpv_0 = io_status_mpv; // @[functional-unit.scala:482:7]
wire io_status_gva_0 = io_status_gva; // @[functional-unit.scala:482:7]
wire io_status_tsr_0 = io_status_tsr; // @[functional-unit.scala:482:7]
wire io_status_tw_0 = io_status_tw; // @[functional-unit.scala:482:7]
wire io_status_tvm_0 = io_status_tvm; // @[functional-unit.scala:482:7]
wire io_status_mxr_0 = io_status_mxr; // @[functional-unit.scala:482:7]
wire io_status_sum_0 = io_status_sum; // @[functional-unit.scala:482:7]
wire io_status_mprv_0 = io_status_mprv; // @[functional-unit.scala:482:7]
wire [1:0] io_status_fs_0 = io_status_fs; // @[functional-unit.scala:482:7]
wire [1:0] io_status_mpp_0 = io_status_mpp; // @[functional-unit.scala:482:7]
wire io_status_spp_0 = io_status_spp; // @[functional-unit.scala:482:7]
wire io_status_mpie_0 = io_status_mpie; // @[functional-unit.scala:482:7]
wire io_status_spie_0 = io_status_spie; // @[functional-unit.scala:482:7]
wire io_status_mie_0 = io_status_mie; // @[functional-unit.scala:482:7]
wire io_status_sie_0 = io_status_sie; // @[functional-unit.scala:482:7]
wire [31:0] io_status_isa = 32'h14112D; // @[functional-unit.scala:482:7]
wire [22:0] io_status_zero2 = 23'h0; // @[functional-unit.scala:482:7]
wire io_req_bits_pred_data = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_ready = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_bits_predicated = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_bits_fflags_valid = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_bits_fflags_bits_uop_is_rvc = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_bits_fflags_bits_uop_is_br = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_bits_fflags_bits_uop_is_jalr = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_bits_fflags_bits_uop_is_jal = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_bits_fflags_bits_uop_is_sfb = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_bits_fflags_bits_uop_edge_inst = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_bits_fflags_bits_uop_taken = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_bits_fflags_bits_uop_exception = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_bits_fflags_bits_uop_bypassable = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_bits_fflags_bits_uop_mem_signed = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_bits_fflags_bits_uop_is_fence = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_bits_fflags_bits_uop_is_fencei = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_bits_fflags_bits_uop_is_amo = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_bits_fflags_bits_uop_uses_stq = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_bits_fflags_bits_uop_is_unique = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_bits_fflags_bits_uop_ldst_val = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_bits_fflags_bits_uop_frs3_en = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_bits_fflags_bits_uop_fp_val = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_bits_fflags_bits_uop_fp_single = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_bits_sfence_bits_hv = 1'h0; // @[functional-unit.scala:482:7]
wire io_resp_bits_sfence_bits_hg = 1'h0; // @[functional-unit.scala:482:7]
wire io_status_mbe = 1'h0; // @[functional-unit.scala:482:7]
wire io_status_sbe = 1'h0; // @[functional-unit.scala:482:7]
wire io_status_sd_rv32 = 1'h0; // @[functional-unit.scala:482:7]
wire io_status_ube = 1'h0; // @[functional-unit.scala:482:7]
wire io_status_upie = 1'h0; // @[functional-unit.scala:482:7]
wire io_status_hie = 1'h0; // @[functional-unit.scala:482:7]
wire io_status_uie = 1'h0; // @[functional-unit.scala:482:7]
wire _dbg_bp_T_1 = 1'h0; // @[functional-unit.scala:532:66]
wire _dbg_bp_T_3 = 1'h0; // @[functional-unit.scala:533:66]
wire _dbg_bp_T_4 = 1'h0; // @[functional-unit.scala:532:88]
wire dbg_bp = 1'h0; // @[functional-unit.scala:532:29]
wire _bp_T_1 = 1'h0; // @[functional-unit.scala:534:66]
wire _bp_T_3 = 1'h0; // @[functional-unit.scala:535:66]
wire _bp_T_4 = 1'h0; // @[functional-unit.scala:534:87]
wire bp = 1'h0; // @[functional-unit.scala:534:29]
wire [7:0] io_resp_bits_fflags_bits_uop_br_mask = 8'h0; // @[functional-unit.scala:482:7]
wire [7:0] io_status_zero1 = 8'h0; // @[functional-unit.scala:482:7]
wire [1:0] io_resp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[functional-unit.scala:482:7]
wire [1:0] io_resp_bits_fflags_bits_uop_iw_state = 2'h0; // @[functional-unit.scala:482:7]
wire [1:0] io_resp_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[functional-unit.scala:482:7]
wire [1:0] io_resp_bits_fflags_bits_uop_mem_size = 2'h0; // @[functional-unit.scala:482:7]
wire [1:0] io_resp_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[functional-unit.scala:482:7]
wire [1:0] io_resp_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[functional-unit.scala:482:7]
wire [1:0] io_resp_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[functional-unit.scala:482:7]
wire [1:0] io_resp_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[functional-unit.scala:482:7]
wire [1:0] io_resp_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[functional-unit.scala:482:7]
wire [1:0] io_status_xs = 2'h0; // @[functional-unit.scala:482:7]
wire [1:0] io_status_vs = 2'h0; // @[functional-unit.scala:482:7]
wire io_req_ready = 1'h1; // @[functional-unit.scala:482:7]
wire [64:0] io_req_bits_rs3_data = 65'h0; // @[functional-unit.scala:482:7]
wire [6:0] io_resp_bits_fflags_bits_uop_uopc = 7'h0; // @[functional-unit.scala:482:7]
wire [31:0] io_resp_bits_fflags_bits_uop_inst = 32'h0; // @[functional-unit.scala:482:7]
wire [31:0] io_resp_bits_fflags_bits_uop_debug_inst = 32'h0; // @[functional-unit.scala:482:7]
wire [39:0] io_resp_bits_fflags_bits_uop_debug_pc = 40'h0; // @[functional-unit.scala:482:7]
wire [2:0] io_resp_bits_fflags_bits_uop_iq_type = 3'h0; // @[functional-unit.scala:482:7]
wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[functional-unit.scala:482:7]
wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[functional-unit.scala:482:7]
wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[functional-unit.scala:482:7]
wire [2:0] io_resp_bits_fflags_bits_uop_br_tag = 3'h0; // @[functional-unit.scala:482:7]
wire [2:0] io_resp_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[functional-unit.scala:482:7]
wire [2:0] io_resp_bits_fflags_bits_uop_stq_idx = 3'h0; // @[functional-unit.scala:482:7]
wire [9:0] io_resp_bits_fflags_bits_uop_fu_code = 10'h0; // @[functional-unit.scala:482:7]
wire [3:0] io_resp_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[functional-unit.scala:482:7]
wire [3:0] io_resp_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[functional-unit.scala:482:7]
wire [3:0] io_resp_bits_fflags_bits_uop_ppred = 4'h0; // @[functional-unit.scala:482:7]
wire [4:0] io_resp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[functional-unit.scala:482:7]
wire [4:0] io_resp_bits_fflags_bits_uop_rob_idx = 5'h0; // @[functional-unit.scala:482:7]
wire [4:0] io_resp_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[functional-unit.scala:482:7]
wire [4:0] io_resp_bits_fflags_bits_flags = 5'h0; // @[functional-unit.scala:482:7]
wire [5:0] io_resp_bits_fflags_bits_uop_pc_lob = 6'h0; // @[functional-unit.scala:482:7]
wire [5:0] io_resp_bits_fflags_bits_uop_pdst = 6'h0; // @[functional-unit.scala:482:7]
wire [5:0] io_resp_bits_fflags_bits_uop_prs1 = 6'h0; // @[functional-unit.scala:482:7]
wire [5:0] io_resp_bits_fflags_bits_uop_prs2 = 6'h0; // @[functional-unit.scala:482:7]
wire [5:0] io_resp_bits_fflags_bits_uop_prs3 = 6'h0; // @[functional-unit.scala:482:7]
wire [5:0] io_resp_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[functional-unit.scala:482:7]
wire [5:0] io_resp_bits_fflags_bits_uop_ldst = 6'h0; // @[functional-unit.scala:482:7]
wire [5:0] io_resp_bits_fflags_bits_uop_lrs1 = 6'h0; // @[functional-unit.scala:482:7]
wire [5:0] io_resp_bits_fflags_bits_uop_lrs2 = 6'h0; // @[functional-unit.scala:482:7]
wire [5:0] io_resp_bits_fflags_bits_uop_lrs3 = 6'h0; // @[functional-unit.scala:482:7]
wire [19:0] io_resp_bits_fflags_bits_uop_imm_packed = 20'h0; // @[functional-unit.scala:482:7]
wire [11:0] io_resp_bits_fflags_bits_uop_csr_addr = 12'h0; // @[functional-unit.scala:482:7]
wire [63:0] io_resp_bits_fflags_bits_uop_exc_cause = 64'h0; // @[functional-unit.scala:482:7]
wire [1:0] io_status_sxl = 2'h2; // @[functional-unit.scala:482:7]
wire [1:0] io_status_uxl = 2'h2; // @[functional-unit.scala:482:7]
wire [6:0] io_resp_bits_uop_uopc_0 = io_req_bits_uop_uopc_0; // @[functional-unit.scala:482:7]
wire [31:0] io_resp_bits_uop_inst_0 = io_req_bits_uop_inst_0; // @[functional-unit.scala:482:7]
wire [31:0] io_resp_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc_0; // @[functional-unit.scala:482:7]
wire [39:0] io_resp_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc_0; // @[functional-unit.scala:482:7]
wire [2:0] io_resp_bits_uop_iq_type_0 = io_req_bits_uop_iq_type_0; // @[functional-unit.scala:482:7]
wire [9:0] io_resp_bits_uop_fu_code_0 = io_req_bits_uop_fu_code_0; // @[functional-unit.scala:482:7]
wire [3:0] io_resp_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:482:7]
wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:482:7]
wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:482:7]
wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:482:7]
wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:482:7]
wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:482:7]
wire [1:0] io_resp_bits_uop_iw_state_0 = io_req_bits_uop_iw_state_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_uop_is_br_0 = io_req_bits_uop_is_br_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_uop_is_jal_0 = io_req_bits_uop_is_jal_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:482:7]
wire [2:0] io_resp_bits_uop_br_tag_0 = io_req_bits_uop_br_tag_0; // @[functional-unit.scala:482:7]
wire [3:0] io_resp_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst_0; // @[functional-unit.scala:482:7]
wire [5:0] io_resp_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_uop_taken_0 = io_req_bits_uop_taken_0; // @[functional-unit.scala:482:7]
wire [19:0] io_resp_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed_0; // @[functional-unit.scala:482:7]
wire [11:0] io_resp_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr_0; // @[functional-unit.scala:482:7]
wire [4:0] io_resp_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx_0; // @[functional-unit.scala:482:7]
wire [2:0] io_resp_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx_0; // @[functional-unit.scala:482:7]
wire [2:0] io_resp_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx_0; // @[functional-unit.scala:482:7]
wire [1:0] io_resp_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx_0; // @[functional-unit.scala:482:7]
wire [5:0] io_resp_bits_uop_pdst_0 = io_req_bits_uop_pdst_0; // @[functional-unit.scala:482:7]
wire [5:0] io_resp_bits_uop_prs1_0 = io_req_bits_uop_prs1_0; // @[functional-unit.scala:482:7]
wire [5:0] io_resp_bits_uop_prs2_0 = io_req_bits_uop_prs2_0; // @[functional-unit.scala:482:7]
wire [5:0] io_resp_bits_uop_prs3_0 = io_req_bits_uop_prs3_0; // @[functional-unit.scala:482:7]
wire [3:0] io_resp_bits_uop_ppred_0 = io_req_bits_uop_ppred_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy_0; // @[functional-unit.scala:482:7]
wire [5:0] io_resp_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_uop_exception_0 = io_req_bits_uop_exception_0; // @[functional-unit.scala:482:7]
wire [63:0] io_resp_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_uop_bypassable_0 = io_req_bits_uop_bypassable_0; // @[functional-unit.scala:482:7]
wire [4:0] io_resp_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd_0; // @[functional-unit.scala:482:7]
wire [1:0] io_resp_bits_uop_mem_size_0 = io_req_bits_uop_mem_size_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_uop_is_fence_0 = io_req_bits_uop_is_fence_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_uop_is_amo_0 = io_req_bits_uop_is_amo_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_uop_is_unique_0 = io_req_bits_uop_is_unique_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:482:7]
wire [5:0] io_resp_bits_uop_ldst_0 = io_req_bits_uop_ldst_0; // @[functional-unit.scala:482:7]
wire [5:0] io_resp_bits_uop_lrs1_0 = io_req_bits_uop_lrs1_0; // @[functional-unit.scala:482:7]
wire [5:0] io_resp_bits_uop_lrs2_0 = io_req_bits_uop_lrs2_0; // @[functional-unit.scala:482:7]
wire [5:0] io_resp_bits_uop_lrs3_0 = io_req_bits_uop_lrs3_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val_0; // @[functional-unit.scala:482:7]
wire [1:0] io_resp_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype_0; // @[functional-unit.scala:482:7]
wire [1:0] io_resp_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:482:7]
wire [1:0] io_resp_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_uop_fp_val_0 = io_req_bits_uop_fp_val_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_uop_fp_single_0 = io_req_bits_uop_fp_single_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:482:7]
wire [1:0] io_resp_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc_0; // @[functional-unit.scala:482:7]
wire [1:0] io_resp_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc_0; // @[functional-unit.scala:482:7]
wire [64:0] _sum_T = io_req_bits_rs1_data_0; // @[functional-unit.scala:482:7, :493:35]
wire [64:0] io_resp_bits_data_0 = io_req_bits_rs2_data_0; // @[functional-unit.scala:482:7]
wire _io_resp_valid_T_3; // @[functional-unit.scala:276:38]
wire [7:0] _io_resp_bits_uop_br_mask_T_1; // @[util.scala:85:25]
wire [39:0] effective_address; // @[functional-unit.scala:496:30]
wire xcpt_val; // @[functional-unit.scala:538:26]
wire _io_resp_bits_sfence_valid_T_1; // @[functional-unit.scala:549:45]
wire _io_resp_bits_sfence_bits_rs1_T; // @[functional-unit.scala:550:59]
wire _io_resp_bits_sfence_bits_rs2_T; // @[functional-unit.scala:551:59]
wire [7:0] io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_mxcpt_valid_0; // @[functional-unit.scala:482:7]
wire [24:0] io_resp_bits_mxcpt_bits_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_sfence_bits_rs1_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_sfence_bits_rs2_0; // @[functional-unit.scala:482:7]
wire [38:0] io_resp_bits_sfence_bits_addr_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_sfence_bits_asid_0; // @[functional-unit.scala:482:7]
wire io_resp_bits_sfence_valid_0; // @[functional-unit.scala:482:7]
wire [39:0] io_resp_bits_addr_0; // @[functional-unit.scala:482:7]
wire io_resp_valid_0; // @[functional-unit.scala:482:7]
wire [7:0] _io_resp_valid_T = io_brupdate_b1_mispredict_mask_0 & io_req_bits_uop_br_mask_0; // @[util.scala:118:51]
wire _io_resp_valid_T_1 = |_io_resp_valid_T; // @[util.scala:118:{51,59}]
wire _io_resp_valid_T_2 = ~_io_resp_valid_T_1; // @[util.scala:118:59]
assign _io_resp_valid_T_3 = io_req_valid_0 & _io_resp_valid_T_2; // @[functional-unit.scala:276:{38,41}, :482:7]
assign io_resp_valid_0 = _io_resp_valid_T_3; // @[functional-unit.scala:276:38, :482:7]
wire [7:0] _io_resp_bits_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
assign _io_resp_bits_uop_br_mask_T_1 = io_req_bits_uop_br_mask_0 & _io_resp_bits_uop_br_mask_T; // @[util.scala:85:{25,27}]
assign io_resp_bits_uop_br_mask_0 = _io_resp_bits_uop_br_mask_T_1; // @[util.scala:85:25]
wire [11:0] _sum_T_1 = io_req_bits_uop_imm_packed_0[19:8]; // @[functional-unit.scala:482:7, :493:70]
wire [11:0] _sum_T_2 = _sum_T_1; // @[functional-unit.scala:493:{70,77}]
wire [65:0] _sum_T_3 = {_sum_T[64], _sum_T} + {{54{_sum_T_2[11]}}, _sum_T_2}; // @[functional-unit.scala:493:{35,42,77}]
wire [64:0] _sum_T_4 = _sum_T_3[64:0]; // @[functional-unit.scala:493:42]
wire [64:0] _sum_T_5 = _sum_T_4; // @[functional-unit.scala:493:42]
wire [64:0] sum = _sum_T_5; // @[functional-unit.scala:493:{42,85}]
wire _ea_sign_T = sum[38]; // @[functional-unit.scala:493:85, :494:24]
wire [24:0] _ea_sign_T_1 = sum[63:39]; // @[functional-unit.scala:493:85, :494:43]
wire [24:0] _ea_sign_T_4 = sum[63:39]; // @[functional-unit.scala:493:85, :494:43, :495:43]
wire [24:0] _ea_sign_T_2 = ~_ea_sign_T_1; // @[functional-unit.scala:494:{39,43}]
wire _ea_sign_T_3 = _ea_sign_T_2 == 25'h0; // @[functional-unit.scala:494:{39,58}]
wire _ea_sign_T_5 = |_ea_sign_T_4; // @[functional-unit.scala:495:{43,58}]
wire ea_sign = _ea_sign_T ? _ea_sign_T_3 : _ea_sign_T_5; // @[functional-unit.scala:494:{20,24,58}, :495:58]
wire [38:0] _effective_address_T = sum[38:0]; // @[functional-unit.scala:493:85, :496:43]
assign effective_address = {ea_sign, _effective_address_T}; // @[functional-unit.scala:494:20, :496:{30,43}]
assign io_resp_bits_addr_0 = effective_address; // @[functional-unit.scala:482:7, :496:30]
wire _misaligned_T = io_req_bits_uop_mem_size_0 == 2'h1; // @[functional-unit.scala:482:7, :518:11]
wire _misaligned_T_1 = effective_address[0]; // @[functional-unit.scala:496:30, :518:40]
wire _misaligned_T_2 = _misaligned_T_1; // @[functional-unit.scala:518:{40,44}]
wire _misaligned_T_3 = _misaligned_T & _misaligned_T_2; // @[functional-unit.scala:518:{11,19,44}]
wire _misaligned_T_4 = io_req_bits_uop_mem_size_0 == 2'h2; // @[functional-unit.scala:482:7, :519:11]
wire [1:0] _misaligned_T_5 = effective_address[1:0]; // @[functional-unit.scala:496:30, :519:40]
wire _misaligned_T_6 = |_misaligned_T_5; // @[functional-unit.scala:519:{40,46}]
wire _misaligned_T_7 = _misaligned_T_4 & _misaligned_T_6; // @[functional-unit.scala:519:{11,19,46}]
wire _misaligned_T_8 = _misaligned_T_3 | _misaligned_T_7; // @[functional-unit.scala:518:{19,54}, :519:19]
wire _misaligned_T_9 = &io_req_bits_uop_mem_size_0; // @[functional-unit.scala:482:7, :520:11]
wire [2:0] _misaligned_T_10 = effective_address[2:0]; // @[functional-unit.scala:496:30, :520:40]
wire _misaligned_T_11 = |_misaligned_T_10; // @[functional-unit.scala:520:{40,46}]
wire _misaligned_T_12 = _misaligned_T_9 & _misaligned_T_11; // @[functional-unit.scala:520:{11,19,46}]
wire misaligned = _misaligned_T_8 | _misaligned_T_12; // @[functional-unit.scala:518:54, :519:56, :520:19]
wire _GEN = io_req_bits_uop_uopc_0 == 7'h1; // @[functional-unit.scala:482:7, :530:53]
wire _ma_ld_T; // @[functional-unit.scala:530:53]
assign _ma_ld_T = _GEN; // @[functional-unit.scala:530:53]
wire _dbg_bp_T; // @[functional-unit.scala:532:55]
assign _dbg_bp_T = _GEN; // @[functional-unit.scala:530:53, :532:55]
wire _bp_T; // @[functional-unit.scala:534:55]
assign _bp_T = _GEN; // @[functional-unit.scala:530:53, :534:55]
wire _ma_ld_T_1 = io_req_valid_0 & _ma_ld_T; // @[functional-unit.scala:482:7, :530:{29,53}]
wire ma_ld = _ma_ld_T_1 & misaligned; // @[functional-unit.scala:519:56, :530:{29,63}]
wire _GEN_0 = io_req_bits_uop_uopc_0 == 7'h2; // @[functional-unit.scala:482:7, :531:54]
wire _ma_st_T; // @[functional-unit.scala:531:54]
assign _ma_st_T = _GEN_0; // @[functional-unit.scala:531:54]
wire _dbg_bp_T_2; // @[functional-unit.scala:533:55]
assign _dbg_bp_T_2 = _GEN_0; // @[functional-unit.scala:531:54, :533:55]
wire _bp_T_2; // @[functional-unit.scala:535:55]
assign _bp_T_2 = _GEN_0; // @[functional-unit.scala:531:54, :535:55]
wire _ma_st_T_1 = io_req_bits_uop_uopc_0 == 7'h43; // @[functional-unit.scala:482:7, :531:89]
wire _ma_st_T_2 = _ma_st_T | _ma_st_T_1; // @[functional-unit.scala:531:{54,65,89}]
wire _ma_st_T_3 = io_req_valid_0 & _ma_st_T_2; // @[functional-unit.scala:482:7, :531:{29,65}]
wire ma_st = _ma_st_T_3 & misaligned; // @[functional-unit.scala:519:56, :531:{29,104}]
assign xcpt_val = ma_ld | ma_st; // @[functional-unit.scala:530:63, :531:104, :538:26]
assign io_resp_bits_mxcpt_valid_0 = xcpt_val; // @[functional-unit.scala:482:7, :538:26]
wire [3:0] xcpt_cause = ma_ld ? 4'h4 : ma_st ? 4'h6 : 4'h3; // @[Mux.scala:50:70]
assign io_resp_bits_mxcpt_bits_0 = {21'h0, xcpt_cause}; // @[Mux.scala:50:70] |
Generate the Verilog code corresponding to this FIRRTL code module PE_353 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_97
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<32>, clock
reg c2 : SInt<32>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h1), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node c1_sign = bits(io.in_d, 19, 19)
node c1_lo_lo_hi = cat(c1_sign, c1_sign)
node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign)
node c1_lo_hi_hi = cat(c1_sign, c1_sign)
node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign)
node c1_lo = cat(c1_lo_hi, c1_lo_lo)
node c1_hi_lo_hi = cat(c1_sign, c1_sign)
node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign)
node c1_hi_hi_hi = cat(c1_sign, c1_sign)
node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign)
node c1_hi = cat(c1_hi_hi, c1_hi_lo)
node _c1_T = cat(c1_hi, c1_lo)
node c1_lo_1 = asUInt(io.in_d)
node _c1_T_1 = cat(_c1_T, c1_lo_1)
wire _c1_WIRE : SInt<32>
node _c1_T_2 = asSInt(_c1_T_1)
connect _c1_WIRE, _c1_T_2
connect c1, _c1_WIRE
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node c2_sign = bits(io.in_d, 19, 19)
node c2_lo_lo_hi = cat(c2_sign, c2_sign)
node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign)
node c2_lo_hi_hi = cat(c2_sign, c2_sign)
node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign)
node c2_lo = cat(c2_lo_hi, c2_lo_lo)
node c2_hi_lo_hi = cat(c2_sign, c2_sign)
node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign)
node c2_hi_hi_hi = cat(c2_sign, c2_sign)
node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign)
node c2_hi = cat(c2_hi_hi, c2_hi_lo)
node _c2_T = cat(c2_hi, c2_lo)
node c2_lo_1 = asUInt(io.in_d)
node _c2_T_1 = cat(_c2_T, c2_lo_1)
wire _c2_WIRE : SInt<32>
node _c2_T_2 = asSInt(_c2_T_1)
connect _c2_WIRE, _c2_T_2
connect c2, _c2_WIRE
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h1), _T_4)
node _T_6 = or(UInt<1>(0h0), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_353( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_97 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module SerialTL0ClockSinkDomain :
output auto : { serdesser_client_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<7>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip clock_in : { clock : Clock, reset : Reset}}
output serial_tl_0 : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, flip clock_in : Clock}
output serial_tl_0_debug : { ser_busy : UInt<1>, des_busy : UInt<1>}
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst serdesser of TLSerdesser_serial_tl_0
connect serdesser.clock, childClock
connect serdesser.reset, childReset
wire clockNodeIn : { clock : Clock, reset : Reset}
invalidate clockNodeIn.reset
invalidate clockNodeIn.clock
connect clockNodeIn, auto.clock_in
connect serdesser.auto.client_out.d, auto.serdesser_client_out.d
connect auto.serdesser_client_out.a.bits, serdesser.auto.client_out.a.bits
connect auto.serdesser_client_out.a.valid, serdesser.auto.client_out.a.valid
connect serdesser.auto.client_out.a.ready, auto.serdesser_client_out.a.ready
node _outer_reset_T = asUInt(serdesser.reset)
inst outer_reset_catcher of ResetCatchAndSync_d3
connect outer_reset_catcher.clock, serial_tl_0.clock_in
connect outer_reset_catcher.reset, _outer_reset_T
wire _outer_reset_catcher_io_psd_WIRE : { test_mode : UInt<1>, test_mode_reset : UInt<1>}
connect _outer_reset_catcher_io_psd_WIRE.test_mode_reset, UInt<1>(0h0)
connect _outer_reset_catcher_io_psd_WIRE.test_mode, UInt<1>(0h0)
wire _outer_reset_catcher_io_psd_WIRE_1 : { test_mode : UInt<1>, test_mode_reset : UInt<1>}
connect _outer_reset_catcher_io_psd_WIRE_1, _outer_reset_catcher_io_psd_WIRE
connect outer_reset_catcher.io.psd, _outer_reset_catcher_io_psd_WIRE_1
inst phy of DecoupledSerialPhy
connect phy.io.outer_clock, serial_tl_0.clock_in
node _phy_io_outer_reset_T = asUInt(serdesser.reset)
inst phy_io_outer_reset_catcher of ResetCatchAndSync_d3_1
connect phy_io_outer_reset_catcher.clock, serial_tl_0.clock_in
connect phy_io_outer_reset_catcher.reset, _phy_io_outer_reset_T
wire _phy_io_outer_reset_catcher_io_psd_WIRE : { test_mode : UInt<1>, test_mode_reset : UInt<1>}
connect _phy_io_outer_reset_catcher_io_psd_WIRE.test_mode_reset, UInt<1>(0h0)
connect _phy_io_outer_reset_catcher_io_psd_WIRE.test_mode, UInt<1>(0h0)
wire _phy_io_outer_reset_catcher_io_psd_WIRE_1 : { test_mode : UInt<1>, test_mode_reset : UInt<1>}
connect _phy_io_outer_reset_catcher_io_psd_WIRE_1, _phy_io_outer_reset_catcher_io_psd_WIRE
connect phy_io_outer_reset_catcher.io.psd, _phy_io_outer_reset_catcher_io_psd_WIRE_1
connect phy.io.outer_reset, phy_io_outer_reset_catcher.io.sync_reset
connect phy.io.inner_clock, serdesser.clock
connect phy.io.inner_reset, serdesser.reset
connect serial_tl_0.out.bits, phy.io.outer_ser.out.bits
connect serial_tl_0.out.valid, phy.io.outer_ser.out.valid
connect phy.io.outer_ser.out.ready, serial_tl_0.out.ready
connect phy.io.outer_ser.in, serial_tl_0.in
connect phy.io.inner_ser, serdesser.io.ser
connect serial_tl_0_debug, serdesser.io.debug
connect childClock, clockNodeIn.clock
connect childReset, clockNodeIn.reset
connect clock, clockNodeIn.clock
connect reset, clockNodeIn.reset | module SerialTL0ClockSinkDomain( // @[ClockDomain.scala:14:9]
input auto_serdesser_client_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_serdesser_client_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_serdesser_client_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_serdesser_client_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_serdesser_client_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_serdesser_client_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_serdesser_client_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_serdesser_client_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_serdesser_client_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_serdesser_client_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_serdesser_client_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_serdesser_client_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_serdesser_client_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_serdesser_client_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_serdesser_client_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_serdesser_client_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_serdesser_client_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_serdesser_client_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_serdesser_client_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_serdesser_client_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_reset, // @[LazyModuleImp.scala:107:25]
output serial_tl_0_in_ready, // @[PeripheryTLSerial.scala:165:24]
input serial_tl_0_in_valid, // @[PeripheryTLSerial.scala:165:24]
input [31:0] serial_tl_0_in_bits_phit, // @[PeripheryTLSerial.scala:165:24]
input serial_tl_0_out_ready, // @[PeripheryTLSerial.scala:165:24]
output serial_tl_0_out_valid, // @[PeripheryTLSerial.scala:165:24]
output [31:0] serial_tl_0_out_bits_phit, // @[PeripheryTLSerial.scala:165:24]
input serial_tl_0_clock_in, // @[PeripheryTLSerial.scala:165:24]
output serial_tl_0_debug_ser_busy, // @[PeripheryTLSerial.scala:226:30]
output serial_tl_0_debug_des_busy // @[PeripheryTLSerial.scala:226:30]
);
wire _phy_io_outer_reset_catcher_io_sync_reset; // @[ResetCatchAndSync.scala:39:28]
wire _phy_io_inner_ser_0_in_valid; // @[PeripheryTLSerial.scala:186:27]
wire [31:0] _phy_io_inner_ser_0_in_bits_flit; // @[PeripheryTLSerial.scala:186:27]
wire _phy_io_inner_ser_1_in_valid; // @[PeripheryTLSerial.scala:186:27]
wire [31:0] _phy_io_inner_ser_1_in_bits_flit; // @[PeripheryTLSerial.scala:186:27]
wire _phy_io_inner_ser_1_out_ready; // @[PeripheryTLSerial.scala:186:27]
wire _phy_io_inner_ser_2_in_valid; // @[PeripheryTLSerial.scala:186:27]
wire [31:0] _phy_io_inner_ser_2_in_bits_flit; // @[PeripheryTLSerial.scala:186:27]
wire _phy_io_inner_ser_3_in_valid; // @[PeripheryTLSerial.scala:186:27]
wire [31:0] _phy_io_inner_ser_3_in_bits_flit; // @[PeripheryTLSerial.scala:186:27]
wire _phy_io_inner_ser_3_out_ready; // @[PeripheryTLSerial.scala:186:27]
wire _phy_io_inner_ser_4_in_valid; // @[PeripheryTLSerial.scala:186:27]
wire [31:0] _phy_io_inner_ser_4_in_bits_flit; // @[PeripheryTLSerial.scala:186:27]
wire _serdesser_io_ser_0_in_ready; // @[PeripheryTLSerial.scala:129:50]
wire _serdesser_io_ser_1_in_ready; // @[PeripheryTLSerial.scala:129:50]
wire _serdesser_io_ser_1_out_valid; // @[PeripheryTLSerial.scala:129:50]
wire [31:0] _serdesser_io_ser_1_out_bits_flit; // @[PeripheryTLSerial.scala:129:50]
wire _serdesser_io_ser_2_in_ready; // @[PeripheryTLSerial.scala:129:50]
wire _serdesser_io_ser_3_in_ready; // @[PeripheryTLSerial.scala:129:50]
wire _serdesser_io_ser_3_out_valid; // @[PeripheryTLSerial.scala:129:50]
wire [31:0] _serdesser_io_ser_3_out_bits_flit; // @[PeripheryTLSerial.scala:129:50]
wire _serdesser_io_ser_4_in_ready; // @[PeripheryTLSerial.scala:129:50]
wire _serdesser_io_debug_ser_busy; // @[PeripheryTLSerial.scala:129:50]
wire _serdesser_io_debug_des_busy; // @[PeripheryTLSerial.scala:129:50]
wire auto_serdesser_client_out_a_ready_0 = auto_serdesser_client_out_a_ready; // @[ClockDomain.scala:14:9]
wire auto_serdesser_client_out_d_valid_0 = auto_serdesser_client_out_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_serdesser_client_out_d_bits_opcode_0 = auto_serdesser_client_out_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] auto_serdesser_client_out_d_bits_param_0 = auto_serdesser_client_out_d_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] auto_serdesser_client_out_d_bits_size_0 = auto_serdesser_client_out_d_bits_size; // @[ClockDomain.scala:14:9]
wire [3:0] auto_serdesser_client_out_d_bits_source_0 = auto_serdesser_client_out_d_bits_source; // @[ClockDomain.scala:14:9]
wire [6:0] auto_serdesser_client_out_d_bits_sink_0 = auto_serdesser_client_out_d_bits_sink; // @[ClockDomain.scala:14:9]
wire auto_serdesser_client_out_d_bits_denied_0 = auto_serdesser_client_out_d_bits_denied; // @[ClockDomain.scala:14:9]
wire [63:0] auto_serdesser_client_out_d_bits_data_0 = auto_serdesser_client_out_d_bits_data; // @[ClockDomain.scala:14:9]
wire auto_serdesser_client_out_d_bits_corrupt_0 = auto_serdesser_client_out_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_clock_in_clock_0 = auto_clock_in_clock; // @[ClockDomain.scala:14:9]
wire auto_clock_in_reset_0 = auto_clock_in_reset; // @[ClockDomain.scala:14:9]
wire serial_tl_0_in_valid_0 = serial_tl_0_in_valid; // @[ClockDomain.scala:14:9]
wire [31:0] serial_tl_0_in_bits_phit_0 = serial_tl_0_in_bits_phit; // @[ClockDomain.scala:14:9]
wire serial_tl_0_out_ready_0 = serial_tl_0_out_ready; // @[ClockDomain.scala:14:9]
wire serial_tl_0_clock_in_0 = serial_tl_0_clock_in; // @[ClockDomain.scala:14:9]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire _outer_reset_catcher_io_psd_WIRE_test_mode = 1'h0; // @[ResetCatchAndSync.scala:41:63]
wire _outer_reset_catcher_io_psd_WIRE_test_mode_reset = 1'h0; // @[ResetCatchAndSync.scala:41:63]
wire _outer_reset_catcher_io_psd_WIRE_1_test_mode = 1'h0; // @[ResetCatchAndSync.scala:41:50]
wire _outer_reset_catcher_io_psd_WIRE_1_test_mode_reset = 1'h0; // @[ResetCatchAndSync.scala:41:50]
wire _phy_io_outer_reset_catcher_io_psd_WIRE_test_mode = 1'h0; // @[ResetCatchAndSync.scala:41:63]
wire _phy_io_outer_reset_catcher_io_psd_WIRE_test_mode_reset = 1'h0; // @[ResetCatchAndSync.scala:41:63]
wire _phy_io_outer_reset_catcher_io_psd_WIRE_1_test_mode = 1'h0; // @[ResetCatchAndSync.scala:41:50]
wire _phy_io_outer_reset_catcher_io_psd_WIRE_1_test_mode_reset = 1'h0; // @[ResetCatchAndSync.scala:41:50]
wire clockNodeIn_clock = auto_clock_in_clock_0; // @[ClockDomain.scala:14:9]
wire clockNodeIn_reset = auto_clock_in_reset_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_serdesser_client_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_serdesser_client_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_serdesser_client_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_serdesser_client_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_serdesser_client_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] auto_serdesser_client_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_serdesser_client_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_serdesser_client_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_serdesser_client_out_a_valid_0; // @[ClockDomain.scala:14:9]
wire auto_serdesser_client_out_d_ready_0; // @[ClockDomain.scala:14:9]
wire serial_tl_0_in_ready_0; // @[ClockDomain.scala:14:9]
wire [31:0] serial_tl_0_out_bits_phit_0; // @[ClockDomain.scala:14:9]
wire serial_tl_0_out_valid_0; // @[ClockDomain.scala:14:9]
wire childClock; // @[LazyModuleImp.scala:155:31]
wire childReset; // @[LazyModuleImp.scala:158:31]
wire _outer_reset_T = childReset; // @[PeripheryTLSerial.scala:185:83]
wire _phy_io_outer_reset_T = childReset; // @[PeripheryTLSerial.scala:188:87]
assign childClock = clockNodeIn_clock; // @[MixedNode.scala:551:17]
assign childReset = clockNodeIn_reset; // @[MixedNode.scala:551:17]
TLSerdesser_serial_tl_0 serdesser ( // @[PeripheryTLSerial.scala:129:50]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_client_out_a_ready (auto_serdesser_client_out_a_ready_0), // @[ClockDomain.scala:14:9]
.auto_client_out_a_valid (auto_serdesser_client_out_a_valid_0),
.auto_client_out_a_bits_opcode (auto_serdesser_client_out_a_bits_opcode_0),
.auto_client_out_a_bits_param (auto_serdesser_client_out_a_bits_param_0),
.auto_client_out_a_bits_size (auto_serdesser_client_out_a_bits_size_0),
.auto_client_out_a_bits_source (auto_serdesser_client_out_a_bits_source_0),
.auto_client_out_a_bits_address (auto_serdesser_client_out_a_bits_address_0),
.auto_client_out_a_bits_mask (auto_serdesser_client_out_a_bits_mask_0),
.auto_client_out_a_bits_data (auto_serdesser_client_out_a_bits_data_0),
.auto_client_out_a_bits_corrupt (auto_serdesser_client_out_a_bits_corrupt_0),
.auto_client_out_d_ready (auto_serdesser_client_out_d_ready_0),
.auto_client_out_d_valid (auto_serdesser_client_out_d_valid_0), // @[ClockDomain.scala:14:9]
.auto_client_out_d_bits_opcode (auto_serdesser_client_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9]
.auto_client_out_d_bits_param (auto_serdesser_client_out_d_bits_param_0), // @[ClockDomain.scala:14:9]
.auto_client_out_d_bits_size (auto_serdesser_client_out_d_bits_size_0), // @[ClockDomain.scala:14:9]
.auto_client_out_d_bits_source (auto_serdesser_client_out_d_bits_source_0), // @[ClockDomain.scala:14:9]
.auto_client_out_d_bits_sink (auto_serdesser_client_out_d_bits_sink_0), // @[ClockDomain.scala:14:9]
.auto_client_out_d_bits_denied (auto_serdesser_client_out_d_bits_denied_0), // @[ClockDomain.scala:14:9]
.auto_client_out_d_bits_data (auto_serdesser_client_out_d_bits_data_0), // @[ClockDomain.scala:14:9]
.auto_client_out_d_bits_corrupt (auto_serdesser_client_out_d_bits_corrupt_0), // @[ClockDomain.scala:14:9]
.io_ser_0_in_ready (_serdesser_io_ser_0_in_ready),
.io_ser_0_in_valid (_phy_io_inner_ser_0_in_valid), // @[PeripheryTLSerial.scala:186:27]
.io_ser_0_in_bits_flit (_phy_io_inner_ser_0_in_bits_flit), // @[PeripheryTLSerial.scala:186:27]
.io_ser_1_in_ready (_serdesser_io_ser_1_in_ready),
.io_ser_1_in_valid (_phy_io_inner_ser_1_in_valid), // @[PeripheryTLSerial.scala:186:27]
.io_ser_1_in_bits_flit (_phy_io_inner_ser_1_in_bits_flit), // @[PeripheryTLSerial.scala:186:27]
.io_ser_1_out_ready (_phy_io_inner_ser_1_out_ready), // @[PeripheryTLSerial.scala:186:27]
.io_ser_1_out_valid (_serdesser_io_ser_1_out_valid),
.io_ser_1_out_bits_flit (_serdesser_io_ser_1_out_bits_flit),
.io_ser_2_in_ready (_serdesser_io_ser_2_in_ready),
.io_ser_2_in_valid (_phy_io_inner_ser_2_in_valid), // @[PeripheryTLSerial.scala:186:27]
.io_ser_2_in_bits_flit (_phy_io_inner_ser_2_in_bits_flit), // @[PeripheryTLSerial.scala:186:27]
.io_ser_3_in_ready (_serdesser_io_ser_3_in_ready),
.io_ser_3_in_valid (_phy_io_inner_ser_3_in_valid), // @[PeripheryTLSerial.scala:186:27]
.io_ser_3_in_bits_flit (_phy_io_inner_ser_3_in_bits_flit), // @[PeripheryTLSerial.scala:186:27]
.io_ser_3_out_ready (_phy_io_inner_ser_3_out_ready), // @[PeripheryTLSerial.scala:186:27]
.io_ser_3_out_valid (_serdesser_io_ser_3_out_valid),
.io_ser_3_out_bits_flit (_serdesser_io_ser_3_out_bits_flit),
.io_ser_4_in_ready (_serdesser_io_ser_4_in_ready),
.io_ser_4_in_valid (_phy_io_inner_ser_4_in_valid), // @[PeripheryTLSerial.scala:186:27]
.io_ser_4_in_bits_flit (_phy_io_inner_ser_4_in_bits_flit), // @[PeripheryTLSerial.scala:186:27]
.io_debug_ser_busy (_serdesser_io_debug_ser_busy),
.io_debug_des_busy (_serdesser_io_debug_des_busy)
); // @[PeripheryTLSerial.scala:129:50]
ResetCatchAndSync_d3 outer_reset_catcher ( // @[ResetCatchAndSync.scala:39:28]
.clock (serial_tl_0_clock_in_0), // @[ClockDomain.scala:14:9]
.reset (_outer_reset_T) // @[PeripheryTLSerial.scala:185:83]
); // @[ResetCatchAndSync.scala:39:28]
DecoupledSerialPhy phy ( // @[PeripheryTLSerial.scala:186:27]
.io_outer_clock (serial_tl_0_clock_in_0), // @[ClockDomain.scala:14:9]
.io_outer_reset (_phy_io_outer_reset_catcher_io_sync_reset), // @[ResetCatchAndSync.scala:39:28]
.io_inner_clock (childClock), // @[LazyModuleImp.scala:155:31]
.io_inner_reset (childReset), // @[LazyModuleImp.scala:158:31]
.io_outer_ser_in_ready (serial_tl_0_in_ready_0),
.io_outer_ser_in_valid (serial_tl_0_in_valid_0), // @[ClockDomain.scala:14:9]
.io_outer_ser_in_bits_phit (serial_tl_0_in_bits_phit_0), // @[ClockDomain.scala:14:9]
.io_outer_ser_out_ready (serial_tl_0_out_ready_0), // @[ClockDomain.scala:14:9]
.io_outer_ser_out_valid (serial_tl_0_out_valid_0),
.io_outer_ser_out_bits_phit (serial_tl_0_out_bits_phit_0),
.io_inner_ser_0_in_ready (_serdesser_io_ser_0_in_ready), // @[PeripheryTLSerial.scala:129:50]
.io_inner_ser_0_in_valid (_phy_io_inner_ser_0_in_valid),
.io_inner_ser_0_in_bits_flit (_phy_io_inner_ser_0_in_bits_flit),
.io_inner_ser_1_in_ready (_serdesser_io_ser_1_in_ready), // @[PeripheryTLSerial.scala:129:50]
.io_inner_ser_1_in_valid (_phy_io_inner_ser_1_in_valid),
.io_inner_ser_1_in_bits_flit (_phy_io_inner_ser_1_in_bits_flit),
.io_inner_ser_1_out_ready (_phy_io_inner_ser_1_out_ready),
.io_inner_ser_1_out_valid (_serdesser_io_ser_1_out_valid), // @[PeripheryTLSerial.scala:129:50]
.io_inner_ser_1_out_bits_flit (_serdesser_io_ser_1_out_bits_flit), // @[PeripheryTLSerial.scala:129:50]
.io_inner_ser_2_in_ready (_serdesser_io_ser_2_in_ready), // @[PeripheryTLSerial.scala:129:50]
.io_inner_ser_2_in_valid (_phy_io_inner_ser_2_in_valid),
.io_inner_ser_2_in_bits_flit (_phy_io_inner_ser_2_in_bits_flit),
.io_inner_ser_3_in_ready (_serdesser_io_ser_3_in_ready), // @[PeripheryTLSerial.scala:129:50]
.io_inner_ser_3_in_valid (_phy_io_inner_ser_3_in_valid),
.io_inner_ser_3_in_bits_flit (_phy_io_inner_ser_3_in_bits_flit),
.io_inner_ser_3_out_ready (_phy_io_inner_ser_3_out_ready),
.io_inner_ser_3_out_valid (_serdesser_io_ser_3_out_valid), // @[PeripheryTLSerial.scala:129:50]
.io_inner_ser_3_out_bits_flit (_serdesser_io_ser_3_out_bits_flit), // @[PeripheryTLSerial.scala:129:50]
.io_inner_ser_4_in_ready (_serdesser_io_ser_4_in_ready), // @[PeripheryTLSerial.scala:129:50]
.io_inner_ser_4_in_valid (_phy_io_inner_ser_4_in_valid),
.io_inner_ser_4_in_bits_flit (_phy_io_inner_ser_4_in_bits_flit)
); // @[PeripheryTLSerial.scala:186:27]
ResetCatchAndSync_d3_1 phy_io_outer_reset_catcher ( // @[ResetCatchAndSync.scala:39:28]
.clock (serial_tl_0_clock_in_0), // @[ClockDomain.scala:14:9]
.reset (_phy_io_outer_reset_T), // @[PeripheryTLSerial.scala:188:87]
.io_sync_reset (_phy_io_outer_reset_catcher_io_sync_reset)
); // @[ResetCatchAndSync.scala:39:28]
assign auto_serdesser_client_out_a_valid = auto_serdesser_client_out_a_valid_0; // @[ClockDomain.scala:14:9]
assign auto_serdesser_client_out_a_bits_opcode = auto_serdesser_client_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_serdesser_client_out_a_bits_param = auto_serdesser_client_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_serdesser_client_out_a_bits_size = auto_serdesser_client_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_serdesser_client_out_a_bits_source = auto_serdesser_client_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_serdesser_client_out_a_bits_address = auto_serdesser_client_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_serdesser_client_out_a_bits_mask = auto_serdesser_client_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
assign auto_serdesser_client_out_a_bits_data = auto_serdesser_client_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_serdesser_client_out_a_bits_corrupt = auto_serdesser_client_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_serdesser_client_out_d_ready = auto_serdesser_client_out_d_ready_0; // @[ClockDomain.scala:14:9]
assign serial_tl_0_in_ready = serial_tl_0_in_ready_0; // @[ClockDomain.scala:14:9]
assign serial_tl_0_out_valid = serial_tl_0_out_valid_0; // @[ClockDomain.scala:14:9]
assign serial_tl_0_out_bits_phit = serial_tl_0_out_bits_phit_0; // @[ClockDomain.scala:14:9]
assign serial_tl_0_debug_ser_busy = _serdesser_io_debug_ser_busy; // @[PeripheryTLSerial.scala:129:50]
assign serial_tl_0_debug_des_busy = _serdesser_io_debug_des_busy; // @[PeripheryTLSerial.scala:129:50]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PE_317 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_61
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<32>, clock
reg c2 : SInt<32>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h1), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node c1_sign = bits(io.in_d, 19, 19)
node c1_lo_lo_hi = cat(c1_sign, c1_sign)
node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign)
node c1_lo_hi_hi = cat(c1_sign, c1_sign)
node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign)
node c1_lo = cat(c1_lo_hi, c1_lo_lo)
node c1_hi_lo_hi = cat(c1_sign, c1_sign)
node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign)
node c1_hi_hi_hi = cat(c1_sign, c1_sign)
node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign)
node c1_hi = cat(c1_hi_hi, c1_hi_lo)
node _c1_T = cat(c1_hi, c1_lo)
node c1_lo_1 = asUInt(io.in_d)
node _c1_T_1 = cat(_c1_T, c1_lo_1)
wire _c1_WIRE : SInt<32>
node _c1_T_2 = asSInt(_c1_T_1)
connect _c1_WIRE, _c1_T_2
connect c1, _c1_WIRE
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node c2_sign = bits(io.in_d, 19, 19)
node c2_lo_lo_hi = cat(c2_sign, c2_sign)
node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign)
node c2_lo_hi_hi = cat(c2_sign, c2_sign)
node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign)
node c2_lo = cat(c2_lo_hi, c2_lo_lo)
node c2_hi_lo_hi = cat(c2_sign, c2_sign)
node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign)
node c2_hi_hi_hi = cat(c2_sign, c2_sign)
node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign)
node c2_hi = cat(c2_hi_hi, c2_hi_lo)
node _c2_T = cat(c2_hi, c2_lo)
node c2_lo_1 = asUInt(io.in_d)
node _c2_T_1 = cat(_c2_T, c2_lo_1)
wire _c2_WIRE : SInt<32>
node _c2_T_2 = asSInt(_c2_T_1)
connect _c2_WIRE, _c2_T_2
connect c2, _c2_WIRE
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h1), _T_4)
node _T_6 = or(UInt<1>(0h0), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_317( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_61 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Switch_13 :
input clock : Clock
input reset : Reset
output io : { in : { flip `1` : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}[1], flip `0` : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}[1]}, out : { `1` : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}}[1], `0` : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}}[1]}, sel : { `1` : { flip `1` : UInt<1>[1], flip `0` : UInt<1>[1]}[1], `0` : { flip `1` : UInt<1>[1], flip `0` : UInt<1>[1]}[1]}}
wire in_flat : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}[2]
connect in_flat[0], io.in.`0`[0]
connect in_flat[1], io.in.`1`[0]
node sel_flat = cat(io.sel.`0`[0].`1`[0], io.sel.`0`[0].`0`[0])
node _T = bits(sel_flat, 0, 0)
node _T_1 = bits(sel_flat, 1, 1)
node _T_2 = add(_T, _T_1)
node _T_3 = bits(_T_2, 1, 0)
node _T_4 = leq(_T_3, UInt<1>(0h1))
node _T_5 = asUInt(reset)
node _T_6 = eq(_T_5, UInt<1>(0h0))
when _T_6 :
node _T_7 = eq(_T_4, UInt<1>(0h0))
when _T_7 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Switch.scala:47 assert(PopCount(sel_flat) <= 1.U)\n") : printf
assert(clock, _T_4, UInt<1>(0h1), "") : assert
node _io_out_0_0_valid_T = bits(sel_flat, 0, 0)
node _io_out_0_0_valid_T_1 = bits(sel_flat, 1, 1)
node _io_out_0_0_valid_T_2 = mux(_io_out_0_0_valid_T, in_flat[0].valid, UInt<1>(0h0))
node _io_out_0_0_valid_T_3 = mux(_io_out_0_0_valid_T_1, in_flat[1].valid, UInt<1>(0h0))
node _io_out_0_0_valid_T_4 = or(_io_out_0_0_valid_T_2, _io_out_0_0_valid_T_3)
wire _io_out_0_0_valid_WIRE : UInt<1>
connect _io_out_0_0_valid_WIRE, _io_out_0_0_valid_T_4
node _io_out_0_0_valid_T_5 = neq(sel_flat, UInt<1>(0h0))
node _io_out_0_0_valid_T_6 = and(_io_out_0_0_valid_WIRE, _io_out_0_0_valid_T_5)
connect io.out.`0`[0].valid, _io_out_0_0_valid_T_6
node _io_out_0_0_bits_T = bits(sel_flat, 0, 0)
node _io_out_0_0_bits_T_1 = bits(sel_flat, 1, 1)
wire _io_out_0_0_bits_WIRE : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}
node _io_out_0_0_bits_T_2 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.virt_channel_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_3 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.virt_channel_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_4 = or(_io_out_0_0_bits_T_2, _io_out_0_0_bits_T_3)
wire _io_out_0_0_bits_WIRE_1 : UInt<2>
connect _io_out_0_0_bits_WIRE_1, _io_out_0_0_bits_T_4
connect _io_out_0_0_bits_WIRE.virt_channel_id, _io_out_0_0_bits_WIRE_1
wire _io_out_0_0_bits_WIRE_2 : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}
node _io_out_0_0_bits_T_5 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.flow.egress_node_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_6 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_7 = or(_io_out_0_0_bits_T_5, _io_out_0_0_bits_T_6)
wire _io_out_0_0_bits_WIRE_3 : UInt<1>
connect _io_out_0_0_bits_WIRE_3, _io_out_0_0_bits_T_7
connect _io_out_0_0_bits_WIRE_2.egress_node_id, _io_out_0_0_bits_WIRE_3
node _io_out_0_0_bits_T_8 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.flow.egress_node, UInt<1>(0h0))
node _io_out_0_0_bits_T_9 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node, UInt<1>(0h0))
node _io_out_0_0_bits_T_10 = or(_io_out_0_0_bits_T_8, _io_out_0_0_bits_T_9)
wire _io_out_0_0_bits_WIRE_4 : UInt<4>
connect _io_out_0_0_bits_WIRE_4, _io_out_0_0_bits_T_10
connect _io_out_0_0_bits_WIRE_2.egress_node, _io_out_0_0_bits_WIRE_4
node _io_out_0_0_bits_T_11 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.flow.ingress_node_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_12 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_13 = or(_io_out_0_0_bits_T_11, _io_out_0_0_bits_T_12)
wire _io_out_0_0_bits_WIRE_5 : UInt<1>
connect _io_out_0_0_bits_WIRE_5, _io_out_0_0_bits_T_13
connect _io_out_0_0_bits_WIRE_2.ingress_node_id, _io_out_0_0_bits_WIRE_5
node _io_out_0_0_bits_T_14 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.flow.ingress_node, UInt<1>(0h0))
node _io_out_0_0_bits_T_15 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node, UInt<1>(0h0))
node _io_out_0_0_bits_T_16 = or(_io_out_0_0_bits_T_14, _io_out_0_0_bits_T_15)
wire _io_out_0_0_bits_WIRE_6 : UInt<4>
connect _io_out_0_0_bits_WIRE_6, _io_out_0_0_bits_T_16
connect _io_out_0_0_bits_WIRE_2.ingress_node, _io_out_0_0_bits_WIRE_6
node _io_out_0_0_bits_T_17 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.flow.vnet_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_18 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.flow.vnet_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_19 = or(_io_out_0_0_bits_T_17, _io_out_0_0_bits_T_18)
wire _io_out_0_0_bits_WIRE_7 : UInt<1>
connect _io_out_0_0_bits_WIRE_7, _io_out_0_0_bits_T_19
connect _io_out_0_0_bits_WIRE_2.vnet_id, _io_out_0_0_bits_WIRE_7
connect _io_out_0_0_bits_WIRE.flow, _io_out_0_0_bits_WIRE_2
node _io_out_0_0_bits_T_20 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.payload, UInt<1>(0h0))
node _io_out_0_0_bits_T_21 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.payload, UInt<1>(0h0))
node _io_out_0_0_bits_T_22 = or(_io_out_0_0_bits_T_20, _io_out_0_0_bits_T_21)
wire _io_out_0_0_bits_WIRE_8 : UInt<37>
connect _io_out_0_0_bits_WIRE_8, _io_out_0_0_bits_T_22
connect _io_out_0_0_bits_WIRE.payload, _io_out_0_0_bits_WIRE_8
node _io_out_0_0_bits_T_23 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.tail, UInt<1>(0h0))
node _io_out_0_0_bits_T_24 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.tail, UInt<1>(0h0))
node _io_out_0_0_bits_T_25 = or(_io_out_0_0_bits_T_23, _io_out_0_0_bits_T_24)
wire _io_out_0_0_bits_WIRE_9 : UInt<1>
connect _io_out_0_0_bits_WIRE_9, _io_out_0_0_bits_T_25
connect _io_out_0_0_bits_WIRE.tail, _io_out_0_0_bits_WIRE_9
node _io_out_0_0_bits_T_26 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.head, UInt<1>(0h0))
node _io_out_0_0_bits_T_27 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.head, UInt<1>(0h0))
node _io_out_0_0_bits_T_28 = or(_io_out_0_0_bits_T_26, _io_out_0_0_bits_T_27)
wire _io_out_0_0_bits_WIRE_10 : UInt<1>
connect _io_out_0_0_bits_WIRE_10, _io_out_0_0_bits_T_28
connect _io_out_0_0_bits_WIRE.head, _io_out_0_0_bits_WIRE_10
connect io.out.`0`[0].bits, _io_out_0_0_bits_WIRE
node _io_out_0_0_bits_virt_channel_id_T = bits(sel_flat, 0, 0)
node _io_out_0_0_bits_virt_channel_id_T_1 = bits(sel_flat, 1, 1)
node _io_out_0_0_bits_virt_channel_id_T_2 = mux(_io_out_0_0_bits_virt_channel_id_T, in_flat[0].bits.out_virt_channel, UInt<1>(0h0))
node _io_out_0_0_bits_virt_channel_id_T_3 = mux(_io_out_0_0_bits_virt_channel_id_T_1, in_flat[1].bits.out_virt_channel, UInt<1>(0h0))
node _io_out_0_0_bits_virt_channel_id_T_4 = or(_io_out_0_0_bits_virt_channel_id_T_2, _io_out_0_0_bits_virt_channel_id_T_3)
wire _io_out_0_0_bits_virt_channel_id_WIRE : UInt<2>
connect _io_out_0_0_bits_virt_channel_id_WIRE, _io_out_0_0_bits_virt_channel_id_T_4
connect io.out.`0`[0].bits.virt_channel_id, _io_out_0_0_bits_virt_channel_id_WIRE
node sel_flat_1 = cat(io.sel.`1`[0].`1`[0], io.sel.`1`[0].`0`[0])
node _T_8 = bits(sel_flat_1, 0, 0)
node _T_9 = bits(sel_flat_1, 1, 1)
node _T_10 = add(_T_8, _T_9)
node _T_11 = bits(_T_10, 1, 0)
node _T_12 = leq(_T_11, UInt<1>(0h1))
node _T_13 = asUInt(reset)
node _T_14 = eq(_T_13, UInt<1>(0h0))
when _T_14 :
node _T_15 = eq(_T_12, UInt<1>(0h0))
when _T_15 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Switch.scala:47 assert(PopCount(sel_flat) <= 1.U)\n") : printf_1
assert(clock, _T_12, UInt<1>(0h1), "") : assert_1
node _io_out_1_0_valid_T = bits(sel_flat_1, 0, 0)
node _io_out_1_0_valid_T_1 = bits(sel_flat_1, 1, 1)
node _io_out_1_0_valid_T_2 = mux(_io_out_1_0_valid_T, in_flat[0].valid, UInt<1>(0h0))
node _io_out_1_0_valid_T_3 = mux(_io_out_1_0_valid_T_1, in_flat[1].valid, UInt<1>(0h0))
node _io_out_1_0_valid_T_4 = or(_io_out_1_0_valid_T_2, _io_out_1_0_valid_T_3)
wire _io_out_1_0_valid_WIRE : UInt<1>
connect _io_out_1_0_valid_WIRE, _io_out_1_0_valid_T_4
node _io_out_1_0_valid_T_5 = neq(sel_flat_1, UInt<1>(0h0))
node _io_out_1_0_valid_T_6 = and(_io_out_1_0_valid_WIRE, _io_out_1_0_valid_T_5)
connect io.out.`1`[0].valid, _io_out_1_0_valid_T_6
node _io_out_1_0_bits_T = bits(sel_flat_1, 0, 0)
node _io_out_1_0_bits_T_1 = bits(sel_flat_1, 1, 1)
wire _io_out_1_0_bits_WIRE : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}
node _io_out_1_0_bits_T_2 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.virt_channel_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_3 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.virt_channel_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_4 = or(_io_out_1_0_bits_T_2, _io_out_1_0_bits_T_3)
wire _io_out_1_0_bits_WIRE_1 : UInt<2>
connect _io_out_1_0_bits_WIRE_1, _io_out_1_0_bits_T_4
connect _io_out_1_0_bits_WIRE.virt_channel_id, _io_out_1_0_bits_WIRE_1
wire _io_out_1_0_bits_WIRE_2 : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}
node _io_out_1_0_bits_T_5 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.flow.egress_node_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_6 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_7 = or(_io_out_1_0_bits_T_5, _io_out_1_0_bits_T_6)
wire _io_out_1_0_bits_WIRE_3 : UInt<1>
connect _io_out_1_0_bits_WIRE_3, _io_out_1_0_bits_T_7
connect _io_out_1_0_bits_WIRE_2.egress_node_id, _io_out_1_0_bits_WIRE_3
node _io_out_1_0_bits_T_8 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.flow.egress_node, UInt<1>(0h0))
node _io_out_1_0_bits_T_9 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node, UInt<1>(0h0))
node _io_out_1_0_bits_T_10 = or(_io_out_1_0_bits_T_8, _io_out_1_0_bits_T_9)
wire _io_out_1_0_bits_WIRE_4 : UInt<4>
connect _io_out_1_0_bits_WIRE_4, _io_out_1_0_bits_T_10
connect _io_out_1_0_bits_WIRE_2.egress_node, _io_out_1_0_bits_WIRE_4
node _io_out_1_0_bits_T_11 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.flow.ingress_node_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_12 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_13 = or(_io_out_1_0_bits_T_11, _io_out_1_0_bits_T_12)
wire _io_out_1_0_bits_WIRE_5 : UInt<1>
connect _io_out_1_0_bits_WIRE_5, _io_out_1_0_bits_T_13
connect _io_out_1_0_bits_WIRE_2.ingress_node_id, _io_out_1_0_bits_WIRE_5
node _io_out_1_0_bits_T_14 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.flow.ingress_node, UInt<1>(0h0))
node _io_out_1_0_bits_T_15 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node, UInt<1>(0h0))
node _io_out_1_0_bits_T_16 = or(_io_out_1_0_bits_T_14, _io_out_1_0_bits_T_15)
wire _io_out_1_0_bits_WIRE_6 : UInt<4>
connect _io_out_1_0_bits_WIRE_6, _io_out_1_0_bits_T_16
connect _io_out_1_0_bits_WIRE_2.ingress_node, _io_out_1_0_bits_WIRE_6
node _io_out_1_0_bits_T_17 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.flow.vnet_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_18 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.flow.vnet_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_19 = or(_io_out_1_0_bits_T_17, _io_out_1_0_bits_T_18)
wire _io_out_1_0_bits_WIRE_7 : UInt<1>
connect _io_out_1_0_bits_WIRE_7, _io_out_1_0_bits_T_19
connect _io_out_1_0_bits_WIRE_2.vnet_id, _io_out_1_0_bits_WIRE_7
connect _io_out_1_0_bits_WIRE.flow, _io_out_1_0_bits_WIRE_2
node _io_out_1_0_bits_T_20 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.payload, UInt<1>(0h0))
node _io_out_1_0_bits_T_21 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.payload, UInt<1>(0h0))
node _io_out_1_0_bits_T_22 = or(_io_out_1_0_bits_T_20, _io_out_1_0_bits_T_21)
wire _io_out_1_0_bits_WIRE_8 : UInt<37>
connect _io_out_1_0_bits_WIRE_8, _io_out_1_0_bits_T_22
connect _io_out_1_0_bits_WIRE.payload, _io_out_1_0_bits_WIRE_8
node _io_out_1_0_bits_T_23 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.tail, UInt<1>(0h0))
node _io_out_1_0_bits_T_24 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.tail, UInt<1>(0h0))
node _io_out_1_0_bits_T_25 = or(_io_out_1_0_bits_T_23, _io_out_1_0_bits_T_24)
wire _io_out_1_0_bits_WIRE_9 : UInt<1>
connect _io_out_1_0_bits_WIRE_9, _io_out_1_0_bits_T_25
connect _io_out_1_0_bits_WIRE.tail, _io_out_1_0_bits_WIRE_9
node _io_out_1_0_bits_T_26 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.head, UInt<1>(0h0))
node _io_out_1_0_bits_T_27 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.head, UInt<1>(0h0))
node _io_out_1_0_bits_T_28 = or(_io_out_1_0_bits_T_26, _io_out_1_0_bits_T_27)
wire _io_out_1_0_bits_WIRE_10 : UInt<1>
connect _io_out_1_0_bits_WIRE_10, _io_out_1_0_bits_T_28
connect _io_out_1_0_bits_WIRE.head, _io_out_1_0_bits_WIRE_10
connect io.out.`1`[0].bits, _io_out_1_0_bits_WIRE
node _io_out_1_0_bits_virt_channel_id_T = bits(sel_flat_1, 0, 0)
node _io_out_1_0_bits_virt_channel_id_T_1 = bits(sel_flat_1, 1, 1)
node _io_out_1_0_bits_virt_channel_id_T_2 = mux(_io_out_1_0_bits_virt_channel_id_T, in_flat[0].bits.out_virt_channel, UInt<1>(0h0))
node _io_out_1_0_bits_virt_channel_id_T_3 = mux(_io_out_1_0_bits_virt_channel_id_T_1, in_flat[1].bits.out_virt_channel, UInt<1>(0h0))
node _io_out_1_0_bits_virt_channel_id_T_4 = or(_io_out_1_0_bits_virt_channel_id_T_2, _io_out_1_0_bits_virt_channel_id_T_3)
wire _io_out_1_0_bits_virt_channel_id_WIRE : UInt<2>
connect _io_out_1_0_bits_virt_channel_id_WIRE, _io_out_1_0_bits_virt_channel_id_T_4
connect io.out.`1`[0].bits.virt_channel_id, _io_out_1_0_bits_virt_channel_id_WIRE | module Switch_13( // @[Switch.scala:16:7]
input clock, // @[Switch.scala:16:7]
input reset, // @[Switch.scala:16:7]
input io_in_1_0_valid, // @[Switch.scala:27:14]
input io_in_1_0_bits_flit_head, // @[Switch.scala:27:14]
input io_in_1_0_bits_flit_tail, // @[Switch.scala:27:14]
input [36:0] io_in_1_0_bits_flit_payload, // @[Switch.scala:27:14]
input io_in_1_0_bits_flit_flow_vnet_id, // @[Switch.scala:27:14]
input [3:0] io_in_1_0_bits_flit_flow_ingress_node, // @[Switch.scala:27:14]
input io_in_1_0_bits_flit_flow_ingress_node_id, // @[Switch.scala:27:14]
input [3:0] io_in_1_0_bits_flit_flow_egress_node, // @[Switch.scala:27:14]
input io_in_1_0_bits_flit_flow_egress_node_id, // @[Switch.scala:27:14]
input [1:0] io_in_1_0_bits_out_virt_channel, // @[Switch.scala:27:14]
input io_in_0_0_valid, // @[Switch.scala:27:14]
input io_in_0_0_bits_flit_head, // @[Switch.scala:27:14]
input io_in_0_0_bits_flit_tail, // @[Switch.scala:27:14]
input [36:0] io_in_0_0_bits_flit_payload, // @[Switch.scala:27:14]
input io_in_0_0_bits_flit_flow_vnet_id, // @[Switch.scala:27:14]
input [3:0] io_in_0_0_bits_flit_flow_ingress_node, // @[Switch.scala:27:14]
input io_in_0_0_bits_flit_flow_ingress_node_id, // @[Switch.scala:27:14]
input [3:0] io_in_0_0_bits_flit_flow_egress_node, // @[Switch.scala:27:14]
input io_in_0_0_bits_flit_flow_egress_node_id, // @[Switch.scala:27:14]
input [1:0] io_in_0_0_bits_out_virt_channel, // @[Switch.scala:27:14]
output io_out_1_0_valid, // @[Switch.scala:27:14]
output io_out_1_0_bits_head, // @[Switch.scala:27:14]
output io_out_1_0_bits_tail, // @[Switch.scala:27:14]
output [36:0] io_out_1_0_bits_payload, // @[Switch.scala:27:14]
output [3:0] io_out_1_0_bits_flow_ingress_node, // @[Switch.scala:27:14]
output io_out_1_0_bits_flow_ingress_node_id, // @[Switch.scala:27:14]
output io_out_0_0_valid, // @[Switch.scala:27:14]
output io_out_0_0_bits_head, // @[Switch.scala:27:14]
output io_out_0_0_bits_tail, // @[Switch.scala:27:14]
output [36:0] io_out_0_0_bits_payload, // @[Switch.scala:27:14]
output io_out_0_0_bits_flow_vnet_id, // @[Switch.scala:27:14]
output [3:0] io_out_0_0_bits_flow_ingress_node, // @[Switch.scala:27:14]
output io_out_0_0_bits_flow_ingress_node_id, // @[Switch.scala:27:14]
output [3:0] io_out_0_0_bits_flow_egress_node, // @[Switch.scala:27:14]
output io_out_0_0_bits_flow_egress_node_id, // @[Switch.scala:27:14]
output [1:0] io_out_0_0_bits_virt_channel_id, // @[Switch.scala:27:14]
input io_sel_1_0_1_0, // @[Switch.scala:27:14]
input io_sel_1_0_0_0, // @[Switch.scala:27:14]
input io_sel_0_0_1_0, // @[Switch.scala:27:14]
input io_sel_0_0_0_0 // @[Switch.scala:27:14]
); |
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_12 :
input clock : Clock
input reset : Reset
output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], credit_return : UInt<3>, vc_free : UInt<3>}}
wire _in_flight_WIRE : UInt<1>[3]
connect _in_flight_WIRE[0], UInt<1>(0h0)
connect _in_flight_WIRE[1], UInt<1>(0h0)
connect _in_flight_WIRE[2], UInt<1>(0h0)
regreset in_flight : UInt<1>[3], clock, reset, _in_flight_WIRE
when io.in.flit[0].valid :
when io.in.flit[0].bits.head :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1)
node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
when io.in.flit[0].bits.tail :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)
node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T_4 :
node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0))
node _T_6 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_7 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_8 = and(_T_6, _T_7)
node _T_9 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_10 = and(_T_8, _T_9)
node _T_11 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_12 = and(_T_10, _T_11)
node _T_13 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_14 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4))
node _T_15 = and(_T_13, _T_14)
node _T_16 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_19 = and(_T_17, _T_18)
node _T_20 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_21 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_24 = and(_T_22, _T_23)
node _T_25 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_26 = and(_T_24, _T_25)
node _T_27 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_28 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_29 = and(_T_27, _T_28)
node _T_30 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_33 = and(_T_31, _T_32)
node _T_34 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_35 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_36 = and(_T_34, _T_35)
node _T_37 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_38 = and(_T_36, _T_37)
node _T_39 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_40 = and(_T_38, _T_39)
node _T_41 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_42 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_45 = and(_T_43, _T_44)
node _T_46 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_47 = and(_T_45, _T_46)
node _T_48 = or(_T_12, _T_19)
node _T_49 = or(_T_48, _T_26)
node _T_50 = or(_T_49, _T_33)
node _T_51 = or(_T_50, _T_40)
node _T_52 = or(_T_51, _T_47)
node _T_53 = or(_T_5, _T_52)
node _T_54 = asUInt(reset)
node _T_55 = eq(_T_54, UInt<1>(0h0))
when _T_55 :
node _T_56 = eq(_T_53, UInt<1>(0h0))
when _T_56 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1
assert(clock, _T_53, UInt<1>(0h1), "") : assert_1
node _T_57 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1))
node _T_58 = or(_T_57, UInt<1>(0h0))
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_T_58, UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2
assert(clock, _T_58, UInt<1>(0h1), "") : assert_2
node _T_62 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2))
node _T_63 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hd))
node _T_64 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_65 = and(_T_63, _T_64)
node _T_66 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_67 = and(_T_65, _T_66)
node _T_68 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_69 = and(_T_67, _T_68)
node _T_70 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb))
node _T_71 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_72 = and(_T_70, _T_71)
node _T_73 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_74 = and(_T_72, _T_73)
node _T_75 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_76 = and(_T_74, _T_75)
node _T_77 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_78 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_79 = and(_T_77, _T_78)
node _T_80 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_81 = and(_T_79, _T_80)
node _T_82 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_83 = and(_T_81, _T_82)
node _T_84 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_85 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_86 = and(_T_84, _T_85)
node _T_87 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_88 = and(_T_86, _T_87)
node _T_89 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_90 = and(_T_88, _T_89)
node _T_91 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc))
node _T_92 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_93 = and(_T_91, _T_92)
node _T_94 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_95 = and(_T_93, _T_94)
node _T_96 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_97 = and(_T_95, _T_96)
node _T_98 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hf))
node _T_99 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_100 = and(_T_98, _T_99)
node _T_101 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_102 = and(_T_100, _T_101)
node _T_103 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_104 = and(_T_102, _T_103)
node _T_105 = or(_T_69, _T_76)
node _T_106 = or(_T_105, _T_83)
node _T_107 = or(_T_106, _T_90)
node _T_108 = or(_T_107, _T_97)
node _T_109 = or(_T_108, _T_104)
node _T_110 = or(_T_62, _T_109)
node _T_111 = asUInt(reset)
node _T_112 = eq(_T_111, UInt<1>(0h0))
when _T_112 :
node _T_113 = eq(_T_110, UInt<1>(0h0))
when _T_113 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3
assert(clock, _T_110, UInt<1>(0h1), "") : assert_3 | module NoCMonitor_12( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26]
reg in_flight_2; // @[Monitor.scala:16:26]
wire _GEN = io_in_flit_0_bits_virt_channel_id == 2'h1; // @[Monitor.scala:21:46] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_39 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_43
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_39( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_43 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLXbar_sbus_i2_o2_a32d64s6k3z4c :
input clock : Clock
input reset : Reset
output auto : { flip anon_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip anon_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, anon_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn.d.bits.corrupt
invalidate anonIn.d.bits.data
invalidate anonIn.d.bits.denied
invalidate anonIn.d.bits.sink
invalidate anonIn.d.bits.source
invalidate anonIn.d.bits.size
invalidate anonIn.d.bits.param
invalidate anonIn.d.bits.opcode
invalidate anonIn.d.valid
invalidate anonIn.d.ready
invalidate anonIn.a.bits.corrupt
invalidate anonIn.a.bits.data
invalidate anonIn.a.bits.mask
invalidate anonIn.a.bits.user.amba_prot.fetch
invalidate anonIn.a.bits.user.amba_prot.secure
invalidate anonIn.a.bits.user.amba_prot.privileged
invalidate anonIn.a.bits.user.amba_prot.writealloc
invalidate anonIn.a.bits.user.amba_prot.readalloc
invalidate anonIn.a.bits.user.amba_prot.modifiable
invalidate anonIn.a.bits.user.amba_prot.bufferable
invalidate anonIn.a.bits.address
invalidate anonIn.a.bits.source
invalidate anonIn.a.bits.size
invalidate anonIn.a.bits.param
invalidate anonIn.a.bits.opcode
invalidate anonIn.a.valid
invalidate anonIn.a.ready
wire anonIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate anonIn_1.e.bits.sink
invalidate anonIn_1.e.valid
invalidate anonIn_1.e.ready
invalidate anonIn_1.d.bits.corrupt
invalidate anonIn_1.d.bits.data
invalidate anonIn_1.d.bits.denied
invalidate anonIn_1.d.bits.sink
invalidate anonIn_1.d.bits.source
invalidate anonIn_1.d.bits.size
invalidate anonIn_1.d.bits.param
invalidate anonIn_1.d.bits.opcode
invalidate anonIn_1.d.valid
invalidate anonIn_1.d.ready
invalidate anonIn_1.c.bits.corrupt
invalidate anonIn_1.c.bits.data
invalidate anonIn_1.c.bits.address
invalidate anonIn_1.c.bits.source
invalidate anonIn_1.c.bits.size
invalidate anonIn_1.c.bits.param
invalidate anonIn_1.c.bits.opcode
invalidate anonIn_1.c.valid
invalidate anonIn_1.c.ready
invalidate anonIn_1.b.bits.corrupt
invalidate anonIn_1.b.bits.data
invalidate anonIn_1.b.bits.mask
invalidate anonIn_1.b.bits.address
invalidate anonIn_1.b.bits.source
invalidate anonIn_1.b.bits.size
invalidate anonIn_1.b.bits.param
invalidate anonIn_1.b.bits.opcode
invalidate anonIn_1.b.valid
invalidate anonIn_1.b.ready
invalidate anonIn_1.a.bits.corrupt
invalidate anonIn_1.a.bits.data
invalidate anonIn_1.a.bits.mask
invalidate anonIn_1.a.bits.address
invalidate anonIn_1.a.bits.source
invalidate anonIn_1.a.bits.size
invalidate anonIn_1.a.bits.param
invalidate anonIn_1.a.bits.opcode
invalidate anonIn_1.a.valid
invalidate anonIn_1.a.ready
inst monitor of TLMonitor
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, anonIn.d.bits.data
connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied
connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink
connect monitor.io.in.d.bits.source, anonIn.d.bits.source
connect monitor.io.in.d.bits.size, anonIn.d.bits.size
connect monitor.io.in.d.bits.param, anonIn.d.bits.param
connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode
connect monitor.io.in.d.valid, anonIn.d.valid
connect monitor.io.in.d.ready, anonIn.d.ready
connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, anonIn.a.bits.data
connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask
connect monitor.io.in.a.bits.user.amba_prot.fetch, anonIn.a.bits.user.amba_prot.fetch
connect monitor.io.in.a.bits.user.amba_prot.secure, anonIn.a.bits.user.amba_prot.secure
connect monitor.io.in.a.bits.user.amba_prot.privileged, anonIn.a.bits.user.amba_prot.privileged
connect monitor.io.in.a.bits.user.amba_prot.writealloc, anonIn.a.bits.user.amba_prot.writealloc
connect monitor.io.in.a.bits.user.amba_prot.readalloc, anonIn.a.bits.user.amba_prot.readalloc
connect monitor.io.in.a.bits.user.amba_prot.modifiable, anonIn.a.bits.user.amba_prot.modifiable
connect monitor.io.in.a.bits.user.amba_prot.bufferable, anonIn.a.bits.user.amba_prot.bufferable
connect monitor.io.in.a.bits.address, anonIn.a.bits.address
connect monitor.io.in.a.bits.source, anonIn.a.bits.source
connect monitor.io.in.a.bits.size, anonIn.a.bits.size
connect monitor.io.in.a.bits.param, anonIn.a.bits.param
connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode
connect monitor.io.in.a.valid, anonIn.a.valid
connect monitor.io.in.a.ready, anonIn.a.ready
inst monitor_1 of TLMonitor_1
connect monitor_1.clock, clock
connect monitor_1.reset, reset
connect monitor_1.io.in.e.bits.sink, anonIn_1.e.bits.sink
connect monitor_1.io.in.e.valid, anonIn_1.e.valid
connect monitor_1.io.in.e.ready, anonIn_1.e.ready
connect monitor_1.io.in.d.bits.corrupt, anonIn_1.d.bits.corrupt
connect monitor_1.io.in.d.bits.data, anonIn_1.d.bits.data
connect monitor_1.io.in.d.bits.denied, anonIn_1.d.bits.denied
connect monitor_1.io.in.d.bits.sink, anonIn_1.d.bits.sink
connect monitor_1.io.in.d.bits.source, anonIn_1.d.bits.source
connect monitor_1.io.in.d.bits.size, anonIn_1.d.bits.size
connect monitor_1.io.in.d.bits.param, anonIn_1.d.bits.param
connect monitor_1.io.in.d.bits.opcode, anonIn_1.d.bits.opcode
connect monitor_1.io.in.d.valid, anonIn_1.d.valid
connect monitor_1.io.in.d.ready, anonIn_1.d.ready
connect monitor_1.io.in.c.bits.corrupt, anonIn_1.c.bits.corrupt
connect monitor_1.io.in.c.bits.data, anonIn_1.c.bits.data
connect monitor_1.io.in.c.bits.address, anonIn_1.c.bits.address
connect monitor_1.io.in.c.bits.source, anonIn_1.c.bits.source
connect monitor_1.io.in.c.bits.size, anonIn_1.c.bits.size
connect monitor_1.io.in.c.bits.param, anonIn_1.c.bits.param
connect monitor_1.io.in.c.bits.opcode, anonIn_1.c.bits.opcode
connect monitor_1.io.in.c.valid, anonIn_1.c.valid
connect monitor_1.io.in.c.ready, anonIn_1.c.ready
connect monitor_1.io.in.b.bits.corrupt, anonIn_1.b.bits.corrupt
connect monitor_1.io.in.b.bits.data, anonIn_1.b.bits.data
connect monitor_1.io.in.b.bits.mask, anonIn_1.b.bits.mask
connect monitor_1.io.in.b.bits.address, anonIn_1.b.bits.address
connect monitor_1.io.in.b.bits.source, anonIn_1.b.bits.source
connect monitor_1.io.in.b.bits.size, anonIn_1.b.bits.size
connect monitor_1.io.in.b.bits.param, anonIn_1.b.bits.param
connect monitor_1.io.in.b.bits.opcode, anonIn_1.b.bits.opcode
connect monitor_1.io.in.b.valid, anonIn_1.b.valid
connect monitor_1.io.in.b.ready, anonIn_1.b.ready
connect monitor_1.io.in.a.bits.corrupt, anonIn_1.a.bits.corrupt
connect monitor_1.io.in.a.bits.data, anonIn_1.a.bits.data
connect monitor_1.io.in.a.bits.mask, anonIn_1.a.bits.mask
connect monitor_1.io.in.a.bits.address, anonIn_1.a.bits.address
connect monitor_1.io.in.a.bits.source, anonIn_1.a.bits.source
connect monitor_1.io.in.a.bits.size, anonIn_1.a.bits.size
connect monitor_1.io.in.a.bits.param, anonIn_1.a.bits.param
connect monitor_1.io.in.a.bits.opcode, anonIn_1.a.bits.opcode
connect monitor_1.io.in.a.valid, anonIn_1.a.valid
connect monitor_1.io.in.a.ready, anonIn_1.a.ready
wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonOut.d.bits.corrupt
invalidate anonOut.d.bits.data
invalidate anonOut.d.bits.denied
invalidate anonOut.d.bits.sink
invalidate anonOut.d.bits.source
invalidate anonOut.d.bits.size
invalidate anonOut.d.bits.param
invalidate anonOut.d.bits.opcode
invalidate anonOut.d.valid
invalidate anonOut.d.ready
invalidate anonOut.a.bits.corrupt
invalidate anonOut.a.bits.data
invalidate anonOut.a.bits.mask
invalidate anonOut.a.bits.user.amba_prot.fetch
invalidate anonOut.a.bits.user.amba_prot.secure
invalidate anonOut.a.bits.user.amba_prot.privileged
invalidate anonOut.a.bits.user.amba_prot.writealloc
invalidate anonOut.a.bits.user.amba_prot.readalloc
invalidate anonOut.a.bits.user.amba_prot.modifiable
invalidate anonOut.a.bits.user.amba_prot.bufferable
invalidate anonOut.a.bits.address
invalidate anonOut.a.bits.source
invalidate anonOut.a.bits.size
invalidate anonOut.a.bits.param
invalidate anonOut.a.bits.opcode
invalidate anonOut.a.valid
invalidate anonOut.a.ready
wire x1_anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate x1_anonOut.e.bits.sink
invalidate x1_anonOut.e.valid
invalidate x1_anonOut.e.ready
invalidate x1_anonOut.d.bits.corrupt
invalidate x1_anonOut.d.bits.data
invalidate x1_anonOut.d.bits.denied
invalidate x1_anonOut.d.bits.sink
invalidate x1_anonOut.d.bits.source
invalidate x1_anonOut.d.bits.size
invalidate x1_anonOut.d.bits.param
invalidate x1_anonOut.d.bits.opcode
invalidate x1_anonOut.d.valid
invalidate x1_anonOut.d.ready
invalidate x1_anonOut.c.bits.corrupt
invalidate x1_anonOut.c.bits.data
invalidate x1_anonOut.c.bits.address
invalidate x1_anonOut.c.bits.source
invalidate x1_anonOut.c.bits.size
invalidate x1_anonOut.c.bits.param
invalidate x1_anonOut.c.bits.opcode
invalidate x1_anonOut.c.valid
invalidate x1_anonOut.c.ready
invalidate x1_anonOut.b.bits.corrupt
invalidate x1_anonOut.b.bits.data
invalidate x1_anonOut.b.bits.mask
invalidate x1_anonOut.b.bits.address
invalidate x1_anonOut.b.bits.source
invalidate x1_anonOut.b.bits.size
invalidate x1_anonOut.b.bits.param
invalidate x1_anonOut.b.bits.opcode
invalidate x1_anonOut.b.valid
invalidate x1_anonOut.b.ready
invalidate x1_anonOut.a.bits.corrupt
invalidate x1_anonOut.a.bits.data
invalidate x1_anonOut.a.bits.mask
invalidate x1_anonOut.a.bits.address
invalidate x1_anonOut.a.bits.source
invalidate x1_anonOut.a.bits.size
invalidate x1_anonOut.a.bits.param
invalidate x1_anonOut.a.bits.opcode
invalidate x1_anonOut.a.valid
invalidate x1_anonOut.a.ready
connect auto.anon_out_0, anonOut
connect auto.anon_out_1, x1_anonOut
connect anonIn, auto.anon_in_0
connect anonIn_1, auto.anon_in_1
wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}[2]
invalidate in[0].a.bits.user.amba_prot.fetch
invalidate in[0].a.bits.user.amba_prot.secure
invalidate in[0].a.bits.user.amba_prot.privileged
invalidate in[0].a.bits.user.amba_prot.writealloc
invalidate in[0].a.bits.user.amba_prot.readalloc
invalidate in[0].a.bits.user.amba_prot.modifiable
invalidate in[0].a.bits.user.amba_prot.bufferable
connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt
connect in[0].a.bits.data, anonIn.a.bits.data
connect in[0].a.bits.mask, anonIn.a.bits.mask
connect in[0].a.bits.user.amba_prot.fetch, anonIn.a.bits.user.amba_prot.fetch
connect in[0].a.bits.user.amba_prot.secure, anonIn.a.bits.user.amba_prot.secure
connect in[0].a.bits.user.amba_prot.privileged, anonIn.a.bits.user.amba_prot.privileged
connect in[0].a.bits.user.amba_prot.writealloc, anonIn.a.bits.user.amba_prot.writealloc
connect in[0].a.bits.user.amba_prot.readalloc, anonIn.a.bits.user.amba_prot.readalloc
connect in[0].a.bits.user.amba_prot.modifiable, anonIn.a.bits.user.amba_prot.modifiable
connect in[0].a.bits.user.amba_prot.bufferable, anonIn.a.bits.user.amba_prot.bufferable
connect in[0].a.bits.address, anonIn.a.bits.address
connect in[0].a.bits.source, anonIn.a.bits.source
connect in[0].a.bits.size, anonIn.a.bits.size
connect in[0].a.bits.param, anonIn.a.bits.param
connect in[0].a.bits.opcode, anonIn.a.bits.opcode
connect in[0].a.valid, anonIn.a.valid
connect anonIn.a.ready, in[0].a.ready
node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h0))
connect in[0].a.bits.source, _in_0_a_bits_source_T
invalidate in[0].b.bits.corrupt
invalidate in[0].b.bits.data
invalidate in[0].b.bits.mask
invalidate in[0].b.bits.address
invalidate in[0].b.bits.source
invalidate in[0].b.bits.size
invalidate in[0].b.bits.param
invalidate in[0].b.bits.opcode
invalidate in[0].b.valid
invalidate in[0].b.ready
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<5>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
invalidate _WIRE_1.bits.corrupt
invalidate _WIRE_1.bits.data
invalidate _WIRE_1.bits.mask
invalidate _WIRE_1.bits.address
invalidate _WIRE_1.bits.source
invalidate _WIRE_1.bits.size
invalidate _WIRE_1.bits.param
invalidate _WIRE_1.bits.opcode
invalidate _WIRE_1.valid
invalidate _WIRE_1.ready
connect in[0].b.ready, UInt<1>(0h1)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.mask, UInt<8>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<5>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<2>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.valid, UInt<1>(0h0)
invalidate in[0].c.bits.corrupt
invalidate in[0].c.bits.data
invalidate in[0].c.bits.user.amba_prot.fetch
invalidate in[0].c.bits.user.amba_prot.secure
invalidate in[0].c.bits.user.amba_prot.privileged
invalidate in[0].c.bits.user.amba_prot.writealloc
invalidate in[0].c.bits.user.amba_prot.readalloc
invalidate in[0].c.bits.user.amba_prot.modifiable
invalidate in[0].c.bits.user.amba_prot.bufferable
invalidate in[0].c.bits.address
invalidate in[0].c.bits.source
invalidate in[0].c.bits.size
invalidate in[0].c.bits.param
invalidate in[0].c.bits.opcode
invalidate in[0].c.valid
invalidate in[0].c.ready
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_4.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_4.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_4.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_4.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_4.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_4.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_4.bits.address, UInt<32>(0h0)
connect _WIRE_4.bits.source, UInt<5>(0h0)
connect _WIRE_4.bits.size, UInt<4>(0h0)
connect _WIRE_4.bits.param, UInt<3>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
invalidate _WIRE_5.bits.corrupt
invalidate _WIRE_5.bits.data
invalidate _WIRE_5.bits.user.amba_prot.fetch
invalidate _WIRE_5.bits.user.amba_prot.secure
invalidate _WIRE_5.bits.user.amba_prot.privileged
invalidate _WIRE_5.bits.user.amba_prot.writealloc
invalidate _WIRE_5.bits.user.amba_prot.readalloc
invalidate _WIRE_5.bits.user.amba_prot.modifiable
invalidate _WIRE_5.bits.user.amba_prot.bufferable
invalidate _WIRE_5.bits.address
invalidate _WIRE_5.bits.source
invalidate _WIRE_5.bits.size
invalidate _WIRE_5.bits.param
invalidate _WIRE_5.bits.opcode
invalidate _WIRE_5.valid
invalidate _WIRE_5.ready
connect in[0].c.valid, UInt<1>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_6.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_6.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_6.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_6.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_6.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_6.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<5>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt
connect anonIn.d.bits.data, in[0].d.bits.data
connect anonIn.d.bits.denied, in[0].d.bits.denied
connect anonIn.d.bits.sink, in[0].d.bits.sink
connect anonIn.d.bits.source, in[0].d.bits.source
connect anonIn.d.bits.size, in[0].d.bits.size
connect anonIn.d.bits.param, in[0].d.bits.param
connect anonIn.d.bits.opcode, in[0].d.bits.opcode
connect anonIn.d.valid, in[0].d.valid
connect in[0].d.ready, anonIn.d.ready
node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 4, 0)
connect anonIn.d.bits.source, _anonIn_d_bits_source_T
invalidate in[0].e.bits.sink
invalidate in[0].e.valid
invalidate in[0].e.ready
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_8.bits.sink, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
invalidate _WIRE_9.bits.sink
invalidate _WIRE_9.valid
invalidate _WIRE_9.ready
connect in[0].e.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_10.bits.sink, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.ready, UInt<1>(0h1)
invalidate in[1].a.bits.user.amba_prot.fetch
invalidate in[1].a.bits.user.amba_prot.secure
invalidate in[1].a.bits.user.amba_prot.privileged
invalidate in[1].a.bits.user.amba_prot.writealloc
invalidate in[1].a.bits.user.amba_prot.readalloc
invalidate in[1].a.bits.user.amba_prot.modifiable
invalidate in[1].a.bits.user.amba_prot.bufferable
connect in[1].a.bits.corrupt, anonIn_1.a.bits.corrupt
connect in[1].a.bits.data, anonIn_1.a.bits.data
connect in[1].a.bits.mask, anonIn_1.a.bits.mask
connect in[1].a.bits.address, anonIn_1.a.bits.address
connect in[1].a.bits.source, anonIn_1.a.bits.source
connect in[1].a.bits.size, anonIn_1.a.bits.size
connect in[1].a.bits.param, anonIn_1.a.bits.param
connect in[1].a.bits.opcode, anonIn_1.a.bits.opcode
connect in[1].a.valid, anonIn_1.a.valid
connect anonIn_1.a.ready, in[1].a.ready
node _in_1_a_bits_source_T = or(anonIn_1.a.bits.source, UInt<6>(0h20))
connect in[1].a.bits.source, _in_1_a_bits_source_T
connect anonIn_1.b.bits.corrupt, in[1].b.bits.corrupt
connect anonIn_1.b.bits.data, in[1].b.bits.data
connect anonIn_1.b.bits.mask, in[1].b.bits.mask
connect anonIn_1.b.bits.address, in[1].b.bits.address
connect anonIn_1.b.bits.source, in[1].b.bits.source
connect anonIn_1.b.bits.size, in[1].b.bits.size
connect anonIn_1.b.bits.param, in[1].b.bits.param
connect anonIn_1.b.bits.opcode, in[1].b.bits.opcode
connect anonIn_1.b.valid, in[1].b.valid
connect in[1].b.ready, anonIn_1.b.ready
node _anonIn_b_bits_source_T = bits(in[1].b.bits.source, 1, 0)
connect anonIn_1.b.bits.source, _anonIn_b_bits_source_T
invalidate in[1].c.bits.user.amba_prot.fetch
invalidate in[1].c.bits.user.amba_prot.secure
invalidate in[1].c.bits.user.amba_prot.privileged
invalidate in[1].c.bits.user.amba_prot.writealloc
invalidate in[1].c.bits.user.amba_prot.readalloc
invalidate in[1].c.bits.user.amba_prot.modifiable
invalidate in[1].c.bits.user.amba_prot.bufferable
connect in[1].c.bits.corrupt, anonIn_1.c.bits.corrupt
connect in[1].c.bits.data, anonIn_1.c.bits.data
connect in[1].c.bits.address, anonIn_1.c.bits.address
connect in[1].c.bits.source, anonIn_1.c.bits.source
connect in[1].c.bits.size, anonIn_1.c.bits.size
connect in[1].c.bits.param, anonIn_1.c.bits.param
connect in[1].c.bits.opcode, anonIn_1.c.bits.opcode
connect in[1].c.valid, anonIn_1.c.valid
connect anonIn_1.c.ready, in[1].c.ready
node _in_1_c_bits_source_T = or(anonIn_1.c.bits.source, UInt<6>(0h20))
connect in[1].c.bits.source, _in_1_c_bits_source_T
connect anonIn_1.d.bits.corrupt, in[1].d.bits.corrupt
connect anonIn_1.d.bits.data, in[1].d.bits.data
connect anonIn_1.d.bits.denied, in[1].d.bits.denied
connect anonIn_1.d.bits.sink, in[1].d.bits.sink
connect anonIn_1.d.bits.source, in[1].d.bits.source
connect anonIn_1.d.bits.size, in[1].d.bits.size
connect anonIn_1.d.bits.param, in[1].d.bits.param
connect anonIn_1.d.bits.opcode, in[1].d.bits.opcode
connect anonIn_1.d.valid, in[1].d.valid
connect in[1].d.ready, anonIn_1.d.ready
node _anonIn_d_bits_source_T_1 = bits(in[1].d.bits.source, 1, 0)
connect anonIn_1.d.bits.source, _anonIn_d_bits_source_T_1
connect in[1].e.bits.sink, anonIn_1.e.bits.sink
connect in[1].e.valid, anonIn_1.e.valid
connect anonIn_1.e.ready, in[1].e.ready
wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}[2]
invalidate out[0].a.bits.user.amba_prot.fetch
invalidate out[0].a.bits.user.amba_prot.secure
invalidate out[0].a.bits.user.amba_prot.privileged
invalidate out[0].a.bits.user.amba_prot.writealloc
invalidate out[0].a.bits.user.amba_prot.readalloc
invalidate out[0].a.bits.user.amba_prot.modifiable
invalidate out[0].a.bits.user.amba_prot.bufferable
connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt
connect anonOut.a.bits.data, out[0].a.bits.data
connect anonOut.a.bits.mask, out[0].a.bits.mask
connect anonOut.a.bits.user.amba_prot.fetch, out[0].a.bits.user.amba_prot.fetch
connect anonOut.a.bits.user.amba_prot.secure, out[0].a.bits.user.amba_prot.secure
connect anonOut.a.bits.user.amba_prot.privileged, out[0].a.bits.user.amba_prot.privileged
connect anonOut.a.bits.user.amba_prot.writealloc, out[0].a.bits.user.amba_prot.writealloc
connect anonOut.a.bits.user.amba_prot.readalloc, out[0].a.bits.user.amba_prot.readalloc
connect anonOut.a.bits.user.amba_prot.modifiable, out[0].a.bits.user.amba_prot.modifiable
connect anonOut.a.bits.user.amba_prot.bufferable, out[0].a.bits.user.amba_prot.bufferable
connect anonOut.a.bits.address, out[0].a.bits.address
connect anonOut.a.bits.source, out[0].a.bits.source
connect anonOut.a.bits.size, out[0].a.bits.size
connect anonOut.a.bits.param, out[0].a.bits.param
connect anonOut.a.bits.opcode, out[0].a.bits.opcode
connect anonOut.a.valid, out[0].a.valid
connect out[0].a.ready, anonOut.a.ready
invalidate out[0].b.bits.corrupt
invalidate out[0].b.bits.data
invalidate out[0].b.bits.mask
invalidate out[0].b.bits.address
invalidate out[0].b.bits.source
invalidate out[0].b.bits.size
invalidate out[0].b.bits.param
invalidate out[0].b.bits.opcode
invalidate out[0].b.valid
invalidate out[0].b.ready
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.mask, UInt<8>(0h0)
connect _WIRE_12.bits.address, UInt<29>(0h0)
connect _WIRE_12.bits.source, UInt<6>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<2>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
invalidate _WIRE_13.bits.corrupt
invalidate _WIRE_13.bits.data
invalidate _WIRE_13.bits.mask
invalidate _WIRE_13.bits.address
invalidate _WIRE_13.bits.source
invalidate _WIRE_13.bits.size
invalidate _WIRE_13.bits.param
invalidate _WIRE_13.bits.opcode
invalidate _WIRE_13.valid
invalidate _WIRE_13.ready
connect out[0].b.valid, UInt<1>(0h0)
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.mask, UInt<8>(0h0)
connect _WIRE_14.bits.address, UInt<29>(0h0)
connect _WIRE_14.bits.source, UInt<6>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<2>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
connect _WIRE_15.ready, UInt<1>(0h1)
invalidate out[0].c.bits.corrupt
invalidate out[0].c.bits.data
invalidate out[0].c.bits.user.amba_prot.fetch
invalidate out[0].c.bits.user.amba_prot.secure
invalidate out[0].c.bits.user.amba_prot.privileged
invalidate out[0].c.bits.user.amba_prot.writealloc
invalidate out[0].c.bits.user.amba_prot.readalloc
invalidate out[0].c.bits.user.amba_prot.modifiable
invalidate out[0].c.bits.user.amba_prot.bufferable
invalidate out[0].c.bits.address
invalidate out[0].c.bits.source
invalidate out[0].c.bits.size
invalidate out[0].c.bits.param
invalidate out[0].c.bits.opcode
invalidate out[0].c.valid
invalidate out[0].c.ready
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_16.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_16.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_16.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_16.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_16.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_16.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_16.bits.address, UInt<29>(0h0)
connect _WIRE_16.bits.source, UInt<6>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
invalidate _WIRE_17.bits.corrupt
invalidate _WIRE_17.bits.data
invalidate _WIRE_17.bits.user.amba_prot.fetch
invalidate _WIRE_17.bits.user.amba_prot.secure
invalidate _WIRE_17.bits.user.amba_prot.privileged
invalidate _WIRE_17.bits.user.amba_prot.writealloc
invalidate _WIRE_17.bits.user.amba_prot.readalloc
invalidate _WIRE_17.bits.user.amba_prot.modifiable
invalidate _WIRE_17.bits.user.amba_prot.bufferable
invalidate _WIRE_17.bits.address
invalidate _WIRE_17.bits.source
invalidate _WIRE_17.bits.size
invalidate _WIRE_17.bits.param
invalidate _WIRE_17.bits.opcode
invalidate _WIRE_17.valid
invalidate _WIRE_17.ready
connect out[0].c.ready, UInt<1>(0h1)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_18.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_18.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_18.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_18.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_18.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_18.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_18.bits.address, UInt<29>(0h0)
connect _WIRE_18.bits.source, UInt<6>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
connect _WIRE_19.valid, UInt<1>(0h0)
connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt
connect out[0].d.bits.data, anonOut.d.bits.data
connect out[0].d.bits.denied, anonOut.d.bits.denied
connect out[0].d.bits.sink, anonOut.d.bits.sink
connect out[0].d.bits.source, anonOut.d.bits.source
connect out[0].d.bits.size, anonOut.d.bits.size
connect out[0].d.bits.param, anonOut.d.bits.param
connect out[0].d.bits.opcode, anonOut.d.bits.opcode
connect out[0].d.valid, anonOut.d.valid
connect anonOut.d.ready, out[0].d.ready
node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0))
connect out[0].d.bits.sink, _out_0_d_bits_sink_T
invalidate out[0].e.bits.sink
invalidate out[0].e.valid
invalidate out[0].e.ready
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_20.bits.sink, UInt<1>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
invalidate _WIRE_21.bits.sink
invalidate _WIRE_21.valid
invalidate _WIRE_21.ready
connect out[0].e.ready, UInt<1>(0h1)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_22.bits.sink, UInt<1>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
connect _WIRE_23.valid, UInt<1>(0h0)
invalidate out[1].a.bits.user.amba_prot.fetch
invalidate out[1].a.bits.user.amba_prot.secure
invalidate out[1].a.bits.user.amba_prot.privileged
invalidate out[1].a.bits.user.amba_prot.writealloc
invalidate out[1].a.bits.user.amba_prot.readalloc
invalidate out[1].a.bits.user.amba_prot.modifiable
invalidate out[1].a.bits.user.amba_prot.bufferable
connect x1_anonOut.a.bits.corrupt, out[1].a.bits.corrupt
connect x1_anonOut.a.bits.data, out[1].a.bits.data
connect x1_anonOut.a.bits.mask, out[1].a.bits.mask
connect x1_anonOut.a.bits.address, out[1].a.bits.address
connect x1_anonOut.a.bits.source, out[1].a.bits.source
connect x1_anonOut.a.bits.size, out[1].a.bits.size
connect x1_anonOut.a.bits.param, out[1].a.bits.param
connect x1_anonOut.a.bits.opcode, out[1].a.bits.opcode
connect x1_anonOut.a.valid, out[1].a.valid
connect out[1].a.ready, x1_anonOut.a.ready
connect out[1].b.bits.corrupt, x1_anonOut.b.bits.corrupt
connect out[1].b.bits.data, x1_anonOut.b.bits.data
connect out[1].b.bits.mask, x1_anonOut.b.bits.mask
connect out[1].b.bits.address, x1_anonOut.b.bits.address
connect out[1].b.bits.source, x1_anonOut.b.bits.source
connect out[1].b.bits.size, x1_anonOut.b.bits.size
connect out[1].b.bits.param, x1_anonOut.b.bits.param
connect out[1].b.bits.opcode, x1_anonOut.b.bits.opcode
connect out[1].b.valid, x1_anonOut.b.valid
connect x1_anonOut.b.ready, out[1].b.ready
invalidate out[1].c.bits.user.amba_prot.fetch
invalidate out[1].c.bits.user.amba_prot.secure
invalidate out[1].c.bits.user.amba_prot.privileged
invalidate out[1].c.bits.user.amba_prot.writealloc
invalidate out[1].c.bits.user.amba_prot.readalloc
invalidate out[1].c.bits.user.amba_prot.modifiable
invalidate out[1].c.bits.user.amba_prot.bufferable
connect x1_anonOut.c.bits.corrupt, out[1].c.bits.corrupt
connect x1_anonOut.c.bits.data, out[1].c.bits.data
connect x1_anonOut.c.bits.address, out[1].c.bits.address
connect x1_anonOut.c.bits.source, out[1].c.bits.source
connect x1_anonOut.c.bits.size, out[1].c.bits.size
connect x1_anonOut.c.bits.param, out[1].c.bits.param
connect x1_anonOut.c.bits.opcode, out[1].c.bits.opcode
connect x1_anonOut.c.valid, out[1].c.valid
connect out[1].c.ready, x1_anonOut.c.ready
connect out[1].d.bits.corrupt, x1_anonOut.d.bits.corrupt
connect out[1].d.bits.data, x1_anonOut.d.bits.data
connect out[1].d.bits.denied, x1_anonOut.d.bits.denied
connect out[1].d.bits.sink, x1_anonOut.d.bits.sink
connect out[1].d.bits.source, x1_anonOut.d.bits.source
connect out[1].d.bits.size, x1_anonOut.d.bits.size
connect out[1].d.bits.param, x1_anonOut.d.bits.param
connect out[1].d.bits.opcode, x1_anonOut.d.bits.opcode
connect out[1].d.valid, x1_anonOut.d.valid
connect x1_anonOut.d.ready, out[1].d.ready
node _out_1_d_bits_sink_T = or(x1_anonOut.d.bits.sink, UInt<1>(0h0))
connect out[1].d.bits.sink, _out_1_d_bits_sink_T
connect x1_anonOut.e.bits.sink, out[1].e.bits.sink
connect x1_anonOut.e.valid, out[1].e.valid
connect out[1].e.ready, x1_anonOut.e.ready
node _anonOut_e_bits_sink_T = bits(out[1].e.bits.sink, 2, 0)
connect x1_anonOut.e.bits.sink, _anonOut_e_bits_sink_T
node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_1 = cvt(_requestAIO_T)
node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_3 = asSInt(_requestAIO_T_2)
node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0)))
node _requestAIO_T_5 = xor(in[0].a.bits.address, UInt<17>(0h10000))
node _requestAIO_T_6 = cvt(_requestAIO_T_5)
node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<33>(0h8c011000)))
node _requestAIO_T_8 = asSInt(_requestAIO_T_7)
node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0)))
node _requestAIO_T_10 = xor(in[0].a.bits.address, UInt<28>(0hc000000))
node _requestAIO_T_11 = cvt(_requestAIO_T_10)
node _requestAIO_T_12 = and(_requestAIO_T_11, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_13 = asSInt(_requestAIO_T_12)
node _requestAIO_T_14 = eq(_requestAIO_T_13, asSInt(UInt<1>(0h0)))
node _requestAIO_T_15 = or(_requestAIO_T_4, _requestAIO_T_9)
node _requestAIO_T_16 = or(_requestAIO_T_15, _requestAIO_T_14)
node requestAIO_0_0 = or(UInt<1>(0h0), _requestAIO_T_16)
node _requestAIO_T_17 = xor(in[0].a.bits.address, UInt<28>(0h8000000))
node _requestAIO_T_18 = cvt(_requestAIO_T_17)
node _requestAIO_T_19 = and(_requestAIO_T_18, asSInt(UInt<33>(0h8c010000)))
node _requestAIO_T_20 = asSInt(_requestAIO_T_19)
node _requestAIO_T_21 = eq(_requestAIO_T_20, asSInt(UInt<1>(0h0)))
node _requestAIO_T_22 = xor(in[0].a.bits.address, UInt<32>(0h80000000))
node _requestAIO_T_23 = cvt(_requestAIO_T_22)
node _requestAIO_T_24 = and(_requestAIO_T_23, asSInt(UInt<33>(0h80000000)))
node _requestAIO_T_25 = asSInt(_requestAIO_T_24)
node _requestAIO_T_26 = eq(_requestAIO_T_25, asSInt(UInt<1>(0h0)))
node _requestAIO_T_27 = or(_requestAIO_T_21, _requestAIO_T_26)
node requestAIO_0_1 = or(UInt<1>(0h0), _requestAIO_T_27)
node _requestAIO_T_28 = xor(in[1].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_29 = cvt(_requestAIO_T_28)
node _requestAIO_T_30 = and(_requestAIO_T_29, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_31 = asSInt(_requestAIO_T_30)
node _requestAIO_T_32 = eq(_requestAIO_T_31, asSInt(UInt<1>(0h0)))
node _requestAIO_T_33 = xor(in[1].a.bits.address, UInt<17>(0h10000))
node _requestAIO_T_34 = cvt(_requestAIO_T_33)
node _requestAIO_T_35 = and(_requestAIO_T_34, asSInt(UInt<33>(0h8c011000)))
node _requestAIO_T_36 = asSInt(_requestAIO_T_35)
node _requestAIO_T_37 = eq(_requestAIO_T_36, asSInt(UInt<1>(0h0)))
node _requestAIO_T_38 = xor(in[1].a.bits.address, UInt<28>(0hc000000))
node _requestAIO_T_39 = cvt(_requestAIO_T_38)
node _requestAIO_T_40 = and(_requestAIO_T_39, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_41 = asSInt(_requestAIO_T_40)
node _requestAIO_T_42 = eq(_requestAIO_T_41, asSInt(UInt<1>(0h0)))
node _requestAIO_T_43 = or(_requestAIO_T_32, _requestAIO_T_37)
node _requestAIO_T_44 = or(_requestAIO_T_43, _requestAIO_T_42)
node requestAIO_1_0 = or(UInt<1>(0h0), _requestAIO_T_44)
node _requestAIO_T_45 = xor(in[1].a.bits.address, UInt<28>(0h8000000))
node _requestAIO_T_46 = cvt(_requestAIO_T_45)
node _requestAIO_T_47 = and(_requestAIO_T_46, asSInt(UInt<33>(0h8c010000)))
node _requestAIO_T_48 = asSInt(_requestAIO_T_47)
node _requestAIO_T_49 = eq(_requestAIO_T_48, asSInt(UInt<1>(0h0)))
node _requestAIO_T_50 = xor(in[1].a.bits.address, UInt<32>(0h80000000))
node _requestAIO_T_51 = cvt(_requestAIO_T_50)
node _requestAIO_T_52 = and(_requestAIO_T_51, asSInt(UInt<33>(0h80000000)))
node _requestAIO_T_53 = asSInt(_requestAIO_T_52)
node _requestAIO_T_54 = eq(_requestAIO_T_53, asSInt(UInt<1>(0h0)))
node _requestAIO_T_55 = or(_requestAIO_T_49, _requestAIO_T_54)
node requestAIO_1_1 = or(UInt<1>(0h0), _requestAIO_T_55)
node _requestCIO_T = xor(in[0].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_1 = cvt(_requestCIO_T)
node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0)))
node _requestCIO_T_3 = asSInt(_requestCIO_T_2)
node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0)))
node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4)
node _requestCIO_T_5 = xor(in[0].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_6 = cvt(_requestCIO_T_5)
node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0)))
node _requestCIO_T_8 = asSInt(_requestCIO_T_7)
node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0)))
node requestCIO_0_1 = or(UInt<1>(0h1), _requestCIO_T_9)
node _requestCIO_T_10 = xor(in[1].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_11 = cvt(_requestCIO_T_10)
node _requestCIO_T_12 = and(_requestCIO_T_11, asSInt(UInt<1>(0h0)))
node _requestCIO_T_13 = asSInt(_requestCIO_T_12)
node _requestCIO_T_14 = eq(_requestCIO_T_13, asSInt(UInt<1>(0h0)))
node requestCIO_1_0 = or(UInt<1>(0h1), _requestCIO_T_14)
node _requestCIO_T_15 = xor(in[1].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_16 = cvt(_requestCIO_T_15)
node _requestCIO_T_17 = and(_requestCIO_T_16, asSInt(UInt<1>(0h0)))
node _requestCIO_T_18 = asSInt(_requestCIO_T_17)
node _requestCIO_T_19 = eq(_requestCIO_T_18, asSInt(UInt<1>(0h0)))
node requestCIO_1_1 = or(UInt<1>(0h1), _requestCIO_T_19)
node _requestBOI_uncommonBits_T = or(out[0].b.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 4, 0)
node _requestBOI_T = shr(out[0].b.bits.source, 5)
node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h0))
node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits)
node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2)
node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<5>(0h1f))
node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4)
node _requestBOI_uncommonBits_T_1 = or(out[0].b.bits.source, UInt<2>(0h0))
node requestBOI_uncommonBits_1 = bits(_requestBOI_uncommonBits_T_1, 1, 0)
node _requestBOI_T_5 = shr(out[0].b.bits.source, 2)
node _requestBOI_T_6 = eq(_requestBOI_T_5, UInt<4>(0h8))
node _requestBOI_T_7 = leq(UInt<1>(0h0), requestBOI_uncommonBits_1)
node _requestBOI_T_8 = and(_requestBOI_T_6, _requestBOI_T_7)
node _requestBOI_T_9 = leq(requestBOI_uncommonBits_1, UInt<2>(0h3))
node requestBOI_0_1 = and(_requestBOI_T_8, _requestBOI_T_9)
node _requestBOI_uncommonBits_T_2 = or(out[1].b.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits_2 = bits(_requestBOI_uncommonBits_T_2, 4, 0)
node _requestBOI_T_10 = shr(out[1].b.bits.source, 5)
node _requestBOI_T_11 = eq(_requestBOI_T_10, UInt<1>(0h0))
node _requestBOI_T_12 = leq(UInt<1>(0h0), requestBOI_uncommonBits_2)
node _requestBOI_T_13 = and(_requestBOI_T_11, _requestBOI_T_12)
node _requestBOI_T_14 = leq(requestBOI_uncommonBits_2, UInt<5>(0h1f))
node requestBOI_1_0 = and(_requestBOI_T_13, _requestBOI_T_14)
node _requestBOI_uncommonBits_T_3 = or(out[1].b.bits.source, UInt<2>(0h0))
node requestBOI_uncommonBits_3 = bits(_requestBOI_uncommonBits_T_3, 1, 0)
node _requestBOI_T_15 = shr(out[1].b.bits.source, 2)
node _requestBOI_T_16 = eq(_requestBOI_T_15, UInt<4>(0h8))
node _requestBOI_T_17 = leq(UInt<1>(0h0), requestBOI_uncommonBits_3)
node _requestBOI_T_18 = and(_requestBOI_T_16, _requestBOI_T_17)
node _requestBOI_T_19 = leq(requestBOI_uncommonBits_3, UInt<2>(0h3))
node requestBOI_1_1 = and(_requestBOI_T_18, _requestBOI_T_19)
node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 4, 0)
node _requestDOI_T = shr(out[0].d.bits.source, 5)
node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h0))
node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits)
node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2)
node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<5>(0h1f))
node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4)
node _requestDOI_uncommonBits_T_1 = or(out[0].d.bits.source, UInt<2>(0h0))
node requestDOI_uncommonBits_1 = bits(_requestDOI_uncommonBits_T_1, 1, 0)
node _requestDOI_T_5 = shr(out[0].d.bits.source, 2)
node _requestDOI_T_6 = eq(_requestDOI_T_5, UInt<4>(0h8))
node _requestDOI_T_7 = leq(UInt<1>(0h0), requestDOI_uncommonBits_1)
node _requestDOI_T_8 = and(_requestDOI_T_6, _requestDOI_T_7)
node _requestDOI_T_9 = leq(requestDOI_uncommonBits_1, UInt<2>(0h3))
node requestDOI_0_1 = and(_requestDOI_T_8, _requestDOI_T_9)
node _requestDOI_uncommonBits_T_2 = or(out[1].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits_2 = bits(_requestDOI_uncommonBits_T_2, 4, 0)
node _requestDOI_T_10 = shr(out[1].d.bits.source, 5)
node _requestDOI_T_11 = eq(_requestDOI_T_10, UInt<1>(0h0))
node _requestDOI_T_12 = leq(UInt<1>(0h0), requestDOI_uncommonBits_2)
node _requestDOI_T_13 = and(_requestDOI_T_11, _requestDOI_T_12)
node _requestDOI_T_14 = leq(requestDOI_uncommonBits_2, UInt<5>(0h1f))
node requestDOI_1_0 = and(_requestDOI_T_13, _requestDOI_T_14)
node _requestDOI_uncommonBits_T_3 = or(out[1].d.bits.source, UInt<2>(0h0))
node requestDOI_uncommonBits_3 = bits(_requestDOI_uncommonBits_T_3, 1, 0)
node _requestDOI_T_15 = shr(out[1].d.bits.source, 2)
node _requestDOI_T_16 = eq(_requestDOI_T_15, UInt<4>(0h8))
node _requestDOI_T_17 = leq(UInt<1>(0h0), requestDOI_uncommonBits_3)
node _requestDOI_T_18 = and(_requestDOI_T_16, _requestDOI_T_17)
node _requestDOI_T_19 = leq(requestDOI_uncommonBits_3, UInt<2>(0h3))
node requestDOI_1_1 = and(_requestDOI_T_18, _requestDOI_T_19)
node _requestEIO_uncommonBits_T = or(in[0].e.bits.sink, UInt<3>(0h0))
node requestEIO_uncommonBits = bits(_requestEIO_uncommonBits_T, 2, 0)
node _requestEIO_T = shr(in[0].e.bits.sink, 3)
node _requestEIO_T_1 = eq(_requestEIO_T, UInt<1>(0h0))
node _requestEIO_T_2 = leq(UInt<1>(0h0), requestEIO_uncommonBits)
node _requestEIO_T_3 = and(_requestEIO_T_1, _requestEIO_T_2)
node _requestEIO_T_4 = leq(requestEIO_uncommonBits, UInt<3>(0h7))
node requestEIO_0_1 = and(_requestEIO_T_3, _requestEIO_T_4)
node _requestEIO_uncommonBits_T_1 = or(in[1].e.bits.sink, UInt<3>(0h0))
node requestEIO_uncommonBits_1 = bits(_requestEIO_uncommonBits_T_1, 2, 0)
node _requestEIO_T_5 = shr(in[1].e.bits.sink, 3)
node _requestEIO_T_6 = eq(_requestEIO_T_5, UInt<1>(0h0))
node _requestEIO_T_7 = leq(UInt<1>(0h0), requestEIO_uncommonBits_1)
node _requestEIO_T_8 = and(_requestEIO_T_6, _requestEIO_T_7)
node _requestEIO_T_9 = leq(requestEIO_uncommonBits_1, UInt<3>(0h7))
node requestEIO_1_1 = and(_requestEIO_T_8, _requestEIO_T_9)
node _beatsAI_decode_T = dshl(UInt<12>(0hfff), in[0].a.bits.size)
node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 11, 0)
node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1)
node beatsAI_decode = shr(_beatsAI_decode_T_2, 3)
node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2)
node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0))
node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0))
node _beatsAI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].a.bits.size)
node _beatsAI_decode_T_4 = bits(_beatsAI_decode_T_3, 11, 0)
node _beatsAI_decode_T_5 = not(_beatsAI_decode_T_4)
node beatsAI_decode_1 = shr(_beatsAI_decode_T_5, 3)
node _beatsAI_opdata_T_1 = bits(in[1].a.bits.opcode, 2, 2)
node beatsAI_opdata_1 = eq(_beatsAI_opdata_T_1, UInt<1>(0h0))
node beatsAI_1 = mux(beatsAI_opdata_1, beatsAI_decode_1, UInt<1>(0h0))
node _beatsBO_decode_T = dshl(UInt<12>(0hfff), out[0].b.bits.size)
node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 11, 0)
node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1)
node beatsBO_decode = shr(_beatsBO_decode_T_2, 3)
node _beatsBO_opdata_T = bits(out[0].b.bits.opcode, 2, 2)
node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0))
node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0))
node _beatsBO_decode_T_3 = dshl(UInt<6>(0h3f), out[1].b.bits.size)
node _beatsBO_decode_T_4 = bits(_beatsBO_decode_T_3, 5, 0)
node _beatsBO_decode_T_5 = not(_beatsBO_decode_T_4)
node beatsBO_decode_1 = shr(_beatsBO_decode_T_5, 3)
node _beatsBO_opdata_T_1 = bits(out[1].b.bits.opcode, 2, 2)
node beatsBO_opdata_1 = eq(_beatsBO_opdata_T_1, UInt<1>(0h0))
node beatsBO_1 = mux(UInt<1>(0h0), beatsBO_decode_1, UInt<1>(0h0))
node _beatsCI_decode_T = dshl(UInt<12>(0hfff), in[0].c.bits.size)
node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 11, 0)
node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1)
node beatsCI_decode = shr(_beatsCI_decode_T_2, 3)
node beatsCI_opdata = bits(in[0].c.bits.opcode, 0, 0)
node beatsCI_0 = mux(UInt<1>(0h0), beatsCI_decode, UInt<1>(0h0))
node _beatsCI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].c.bits.size)
node _beatsCI_decode_T_4 = bits(_beatsCI_decode_T_3, 11, 0)
node _beatsCI_decode_T_5 = not(_beatsCI_decode_T_4)
node beatsCI_decode_1 = shr(_beatsCI_decode_T_5, 3)
node beatsCI_opdata_1 = bits(in[1].c.bits.opcode, 0, 0)
node beatsCI_1 = mux(beatsCI_opdata_1, beatsCI_decode_1, UInt<1>(0h0))
node _beatsDO_decode_T = dshl(UInt<12>(0hfff), out[0].d.bits.size)
node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 11, 0)
node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1)
node beatsDO_decode = shr(_beatsDO_decode_T_2, 3)
node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0)
node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0))
node _beatsDO_decode_T_3 = dshl(UInt<6>(0h3f), out[1].d.bits.size)
node _beatsDO_decode_T_4 = bits(_beatsDO_decode_T_3, 5, 0)
node _beatsDO_decode_T_5 = not(_beatsDO_decode_T_4)
node beatsDO_decode_1 = shr(_beatsDO_decode_T_5, 3)
node beatsDO_opdata_1 = bits(out[1].d.bits.opcode, 0, 0)
node beatsDO_1 = mux(beatsDO_opdata_1, beatsDO_decode_1, UInt<1>(0h0))
wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsAOI_filtered[0].bits, in[0].a.bits
node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h0))
node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T)
connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1
connect portsAOI_filtered[1].bits, in[0].a.bits
node _portsAOI_filtered_1_valid_T = or(requestAIO_0_1, UInt<1>(0h0))
node _portsAOI_filtered_1_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_1_valid_T)
connect portsAOI_filtered[1].valid, _portsAOI_filtered_1_valid_T_1
node _portsAOI_in_0_a_ready_T = mux(requestAIO_0_0, portsAOI_filtered[0].ready, UInt<1>(0h0))
node _portsAOI_in_0_a_ready_T_1 = mux(requestAIO_0_1, portsAOI_filtered[1].ready, UInt<1>(0h0))
node _portsAOI_in_0_a_ready_T_2 = or(_portsAOI_in_0_a_ready_T, _portsAOI_in_0_a_ready_T_1)
wire _portsAOI_in_0_a_ready_WIRE : UInt<1>
connect _portsAOI_in_0_a_ready_WIRE, _portsAOI_in_0_a_ready_T_2
connect in[0].a.ready, _portsAOI_in_0_a_ready_WIRE
wire portsAOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsAOI_filtered_1[0].bits, in[1].a.bits
node _portsAOI_filtered_0_valid_T_2 = or(requestAIO_1_0, UInt<1>(0h0))
node _portsAOI_filtered_0_valid_T_3 = and(in[1].a.valid, _portsAOI_filtered_0_valid_T_2)
connect portsAOI_filtered_1[0].valid, _portsAOI_filtered_0_valid_T_3
connect portsAOI_filtered_1[1].bits, in[1].a.bits
node _portsAOI_filtered_1_valid_T_2 = or(requestAIO_1_1, UInt<1>(0h0))
node _portsAOI_filtered_1_valid_T_3 = and(in[1].a.valid, _portsAOI_filtered_1_valid_T_2)
connect portsAOI_filtered_1[1].valid, _portsAOI_filtered_1_valid_T_3
node _portsAOI_in_1_a_ready_T = mux(requestAIO_1_0, portsAOI_filtered_1[0].ready, UInt<1>(0h0))
node _portsAOI_in_1_a_ready_T_1 = mux(requestAIO_1_1, portsAOI_filtered_1[1].ready, UInt<1>(0h0))
node _portsAOI_in_1_a_ready_T_2 = or(_portsAOI_in_1_a_ready_T, _portsAOI_in_1_a_ready_T_1)
wire _portsAOI_in_1_a_ready_WIRE : UInt<1>
connect _portsAOI_in_1_a_ready_WIRE, _portsAOI_in_1_a_ready_T_2
connect in[1].a.ready, _portsAOI_in_1_a_ready_WIRE
wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsBIO_filtered[0].bits.corrupt, out[0].b.bits.corrupt
connect portsBIO_filtered[0].bits.data, out[0].b.bits.data
connect portsBIO_filtered[0].bits.mask, out[0].b.bits.mask
connect portsBIO_filtered[0].bits.address, out[0].b.bits.address
connect portsBIO_filtered[0].bits.source, out[0].b.bits.source
connect portsBIO_filtered[0].bits.size, out[0].b.bits.size
connect portsBIO_filtered[0].bits.param, out[0].b.bits.param
connect portsBIO_filtered[0].bits.opcode, out[0].b.bits.opcode
node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h0))
node _portsBIO_filtered_0_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_0_valid_T)
connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1
connect portsBIO_filtered[1].bits.corrupt, out[0].b.bits.corrupt
connect portsBIO_filtered[1].bits.data, out[0].b.bits.data
connect portsBIO_filtered[1].bits.mask, out[0].b.bits.mask
connect portsBIO_filtered[1].bits.address, out[0].b.bits.address
connect portsBIO_filtered[1].bits.source, out[0].b.bits.source
connect portsBIO_filtered[1].bits.size, out[0].b.bits.size
connect portsBIO_filtered[1].bits.param, out[0].b.bits.param
connect portsBIO_filtered[1].bits.opcode, out[0].b.bits.opcode
node _portsBIO_filtered_1_valid_T = or(requestBOI_0_1, UInt<1>(0h0))
node _portsBIO_filtered_1_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_1_valid_T)
connect portsBIO_filtered[1].valid, _portsBIO_filtered_1_valid_T_1
node _portsBIO_out_0_b_ready_T = mux(requestBOI_0_0, portsBIO_filtered[0].ready, UInt<1>(0h0))
node _portsBIO_out_0_b_ready_T_1 = mux(requestBOI_0_1, portsBIO_filtered[1].ready, UInt<1>(0h0))
node _portsBIO_out_0_b_ready_T_2 = or(_portsBIO_out_0_b_ready_T, _portsBIO_out_0_b_ready_T_1)
wire _portsBIO_out_0_b_ready_WIRE : UInt<1>
connect _portsBIO_out_0_b_ready_WIRE, _portsBIO_out_0_b_ready_T_2
connect out[0].b.ready, _portsBIO_out_0_b_ready_WIRE
wire portsBIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsBIO_filtered_1[0].bits.corrupt, out[1].b.bits.corrupt
connect portsBIO_filtered_1[0].bits.data, out[1].b.bits.data
connect portsBIO_filtered_1[0].bits.mask, out[1].b.bits.mask
connect portsBIO_filtered_1[0].bits.address, out[1].b.bits.address
connect portsBIO_filtered_1[0].bits.source, out[1].b.bits.source
connect portsBIO_filtered_1[0].bits.size, out[1].b.bits.size
connect portsBIO_filtered_1[0].bits.param, out[1].b.bits.param
connect portsBIO_filtered_1[0].bits.opcode, out[1].b.bits.opcode
node _portsBIO_filtered_0_valid_T_2 = or(requestBOI_1_0, UInt<1>(0h0))
node _portsBIO_filtered_0_valid_T_3 = and(out[1].b.valid, _portsBIO_filtered_0_valid_T_2)
connect portsBIO_filtered_1[0].valid, _portsBIO_filtered_0_valid_T_3
connect portsBIO_filtered_1[1].bits.corrupt, out[1].b.bits.corrupt
connect portsBIO_filtered_1[1].bits.data, out[1].b.bits.data
connect portsBIO_filtered_1[1].bits.mask, out[1].b.bits.mask
connect portsBIO_filtered_1[1].bits.address, out[1].b.bits.address
connect portsBIO_filtered_1[1].bits.source, out[1].b.bits.source
connect portsBIO_filtered_1[1].bits.size, out[1].b.bits.size
connect portsBIO_filtered_1[1].bits.param, out[1].b.bits.param
connect portsBIO_filtered_1[1].bits.opcode, out[1].b.bits.opcode
node _portsBIO_filtered_1_valid_T_2 = or(requestBOI_1_1, UInt<1>(0h0))
node _portsBIO_filtered_1_valid_T_3 = and(out[1].b.valid, _portsBIO_filtered_1_valid_T_2)
connect portsBIO_filtered_1[1].valid, _portsBIO_filtered_1_valid_T_3
node _portsBIO_out_1_b_ready_T = mux(requestBOI_1_0, portsBIO_filtered_1[0].ready, UInt<1>(0h0))
node _portsBIO_out_1_b_ready_T_1 = mux(requestBOI_1_1, portsBIO_filtered_1[1].ready, UInt<1>(0h0))
node _portsBIO_out_1_b_ready_T_2 = or(_portsBIO_out_1_b_ready_T, _portsBIO_out_1_b_ready_T_1)
wire _portsBIO_out_1_b_ready_WIRE : UInt<1>
connect _portsBIO_out_1_b_ready_WIRE, _portsBIO_out_1_b_ready_T_2
connect out[1].b.ready, _portsBIO_out_1_b_ready_WIRE
wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsCOI_filtered[0].bits, in[0].c.bits
node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h0))
node _portsCOI_filtered_0_valid_T_1 = and(in[0].c.valid, _portsCOI_filtered_0_valid_T)
connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1
connect portsCOI_filtered[1].bits, in[0].c.bits
node _portsCOI_filtered_1_valid_T = or(requestCIO_0_1, UInt<1>(0h0))
node _portsCOI_filtered_1_valid_T_1 = and(in[0].c.valid, _portsCOI_filtered_1_valid_T)
connect portsCOI_filtered[1].valid, _portsCOI_filtered_1_valid_T_1
node _portsCOI_in_0_c_ready_T = mux(requestCIO_0_0, portsCOI_filtered[0].ready, UInt<1>(0h0))
node _portsCOI_in_0_c_ready_T_1 = mux(requestCIO_0_1, portsCOI_filtered[1].ready, UInt<1>(0h0))
node _portsCOI_in_0_c_ready_T_2 = or(_portsCOI_in_0_c_ready_T, _portsCOI_in_0_c_ready_T_1)
wire _portsCOI_in_0_c_ready_WIRE : UInt<1>
connect _portsCOI_in_0_c_ready_WIRE, _portsCOI_in_0_c_ready_T_2
connect in[0].c.ready, _portsCOI_in_0_c_ready_WIRE
wire portsCOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsCOI_filtered_1[0].bits, in[1].c.bits
node _portsCOI_filtered_0_valid_T_2 = or(requestCIO_1_0, UInt<1>(0h0))
node _portsCOI_filtered_0_valid_T_3 = and(in[1].c.valid, _portsCOI_filtered_0_valid_T_2)
connect portsCOI_filtered_1[0].valid, _portsCOI_filtered_0_valid_T_3
connect portsCOI_filtered_1[1].bits, in[1].c.bits
node _portsCOI_filtered_1_valid_T_2 = or(requestCIO_1_1, UInt<1>(0h0))
node _portsCOI_filtered_1_valid_T_3 = and(in[1].c.valid, _portsCOI_filtered_1_valid_T_2)
connect portsCOI_filtered_1[1].valid, _portsCOI_filtered_1_valid_T_3
node _portsCOI_in_1_c_ready_T = mux(requestCIO_1_0, portsCOI_filtered_1[0].ready, UInt<1>(0h0))
node _portsCOI_in_1_c_ready_T_1 = mux(requestCIO_1_1, portsCOI_filtered_1[1].ready, UInt<1>(0h0))
node _portsCOI_in_1_c_ready_T_2 = or(_portsCOI_in_1_c_ready_T, _portsCOI_in_1_c_ready_T_1)
wire _portsCOI_in_1_c_ready_WIRE : UInt<1>
connect _portsCOI_in_1_c_ready_WIRE, _portsCOI_in_1_c_ready_T_2
connect in[1].c.ready, _portsCOI_in_1_c_ready_WIRE
wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[0].bits.data, out[0].d.bits.data
connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[0].bits.source, out[0].d.bits.source
connect portsDIO_filtered[0].bits.size, out[0].d.bits.size
connect portsDIO_filtered[0].bits.param, out[0].d.bits.param
connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h0))
node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T)
connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1
connect portsDIO_filtered[1].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[1].bits.data, out[0].d.bits.data
connect portsDIO_filtered[1].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[1].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[1].bits.source, out[0].d.bits.source
connect portsDIO_filtered[1].bits.size, out[0].d.bits.size
connect portsDIO_filtered[1].bits.param, out[0].d.bits.param
connect portsDIO_filtered[1].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_1_valid_T = or(requestDOI_0_1, UInt<1>(0h0))
node _portsDIO_filtered_1_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_1_valid_T)
connect portsDIO_filtered[1].valid, _portsDIO_filtered_1_valid_T_1
node _portsDIO_out_0_d_ready_T = mux(requestDOI_0_0, portsDIO_filtered[0].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_1 = mux(requestDOI_0_1, portsDIO_filtered[1].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_2 = or(_portsDIO_out_0_d_ready_T, _portsDIO_out_0_d_ready_T_1)
wire _portsDIO_out_0_d_ready_WIRE : UInt<1>
connect _portsDIO_out_0_d_ready_WIRE, _portsDIO_out_0_d_ready_T_2
connect out[0].d.ready, _portsDIO_out_0_d_ready_WIRE
wire portsDIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsDIO_filtered_1[0].bits.corrupt, out[1].d.bits.corrupt
connect portsDIO_filtered_1[0].bits.data, out[1].d.bits.data
connect portsDIO_filtered_1[0].bits.denied, out[1].d.bits.denied
connect portsDIO_filtered_1[0].bits.sink, out[1].d.bits.sink
connect portsDIO_filtered_1[0].bits.source, out[1].d.bits.source
connect portsDIO_filtered_1[0].bits.size, out[1].d.bits.size
connect portsDIO_filtered_1[0].bits.param, out[1].d.bits.param
connect portsDIO_filtered_1[0].bits.opcode, out[1].d.bits.opcode
node _portsDIO_filtered_0_valid_T_2 = or(requestDOI_1_0, UInt<1>(0h0))
node _portsDIO_filtered_0_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_0_valid_T_2)
connect portsDIO_filtered_1[0].valid, _portsDIO_filtered_0_valid_T_3
connect portsDIO_filtered_1[1].bits.corrupt, out[1].d.bits.corrupt
connect portsDIO_filtered_1[1].bits.data, out[1].d.bits.data
connect portsDIO_filtered_1[1].bits.denied, out[1].d.bits.denied
connect portsDIO_filtered_1[1].bits.sink, out[1].d.bits.sink
connect portsDIO_filtered_1[1].bits.source, out[1].d.bits.source
connect portsDIO_filtered_1[1].bits.size, out[1].d.bits.size
connect portsDIO_filtered_1[1].bits.param, out[1].d.bits.param
connect portsDIO_filtered_1[1].bits.opcode, out[1].d.bits.opcode
node _portsDIO_filtered_1_valid_T_2 = or(requestDOI_1_1, UInt<1>(0h0))
node _portsDIO_filtered_1_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_1_valid_T_2)
connect portsDIO_filtered_1[1].valid, _portsDIO_filtered_1_valid_T_3
node _portsDIO_out_1_d_ready_T = mux(requestDOI_1_0, portsDIO_filtered_1[0].ready, UInt<1>(0h0))
node _portsDIO_out_1_d_ready_T_1 = mux(requestDOI_1_1, portsDIO_filtered_1[1].ready, UInt<1>(0h0))
node _portsDIO_out_1_d_ready_T_2 = or(_portsDIO_out_1_d_ready_T, _portsDIO_out_1_d_ready_T_1)
wire _portsDIO_out_1_d_ready_WIRE : UInt<1>
connect _portsDIO_out_1_d_ready_WIRE, _portsDIO_out_1_d_ready_T_2
connect out[1].d.ready, _portsDIO_out_1_d_ready_WIRE
wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[2]
connect portsEOI_filtered[0].bits, in[0].e.bits
node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_0_valid_T_1 = and(in[0].e.valid, _portsEOI_filtered_0_valid_T)
connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1
connect portsEOI_filtered[1].bits, in[0].e.bits
node _portsEOI_filtered_1_valid_T = or(requestEIO_0_1, UInt<1>(0h0))
node _portsEOI_filtered_1_valid_T_1 = and(in[0].e.valid, _portsEOI_filtered_1_valid_T)
connect portsEOI_filtered[1].valid, _portsEOI_filtered_1_valid_T_1
node _portsEOI_in_0_e_ready_T = mux(UInt<1>(0h0), portsEOI_filtered[0].ready, UInt<1>(0h0))
node _portsEOI_in_0_e_ready_T_1 = mux(requestEIO_0_1, portsEOI_filtered[1].ready, UInt<1>(0h0))
node _portsEOI_in_0_e_ready_T_2 = or(_portsEOI_in_0_e_ready_T, _portsEOI_in_0_e_ready_T_1)
wire _portsEOI_in_0_e_ready_WIRE : UInt<1>
connect _portsEOI_in_0_e_ready_WIRE, _portsEOI_in_0_e_ready_T_2
connect in[0].e.ready, _portsEOI_in_0_e_ready_WIRE
wire portsEOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[2]
connect portsEOI_filtered_1[0].bits, in[1].e.bits
node _portsEOI_filtered_0_valid_T_2 = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_0_valid_T_3 = and(in[1].e.valid, _portsEOI_filtered_0_valid_T_2)
connect portsEOI_filtered_1[0].valid, _portsEOI_filtered_0_valid_T_3
connect portsEOI_filtered_1[1].bits, in[1].e.bits
node _portsEOI_filtered_1_valid_T_2 = or(requestEIO_1_1, UInt<1>(0h0))
node _portsEOI_filtered_1_valid_T_3 = and(in[1].e.valid, _portsEOI_filtered_1_valid_T_2)
connect portsEOI_filtered_1[1].valid, _portsEOI_filtered_1_valid_T_3
node _portsEOI_in_1_e_ready_T = mux(UInt<1>(0h0), portsEOI_filtered_1[0].ready, UInt<1>(0h0))
node _portsEOI_in_1_e_ready_T_1 = mux(requestEIO_1_1, portsEOI_filtered_1[1].ready, UInt<1>(0h0))
node _portsEOI_in_1_e_ready_T_2 = or(_portsEOI_in_1_e_ready_T, _portsEOI_in_1_e_ready_T_1)
wire _portsEOI_in_1_e_ready_WIRE : UInt<1>
connect _portsEOI_in_1_e_ready_WIRE, _portsEOI_in_1_e_ready_T_2
connect in[1].e.ready, _portsEOI_in_1_e_ready_WIRE
regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0)
node idle = eq(beatsLeft, UInt<1>(0h0))
node latch = and(idle, out[0].a.ready)
node _readys_T = cat(portsAOI_filtered_1[0].valid, portsAOI_filtered[0].valid)
node readys_valid = bits(_readys_T, 1, 0)
node _readys_T_1 = eq(readys_valid, _readys_T)
node _readys_T_2 = asUInt(reset)
node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0))
when _readys_T_3 :
node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0))
when _readys_T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf
assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert
regreset readys_mask : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T = not(readys_mask)
node _readys_filter_T_1 = and(readys_valid, _readys_filter_T)
node readys_filter = cat(_readys_filter_T_1, readys_valid)
node _readys_unready_T = shr(readys_filter, 1)
node _readys_unready_T_1 = or(readys_filter, _readys_unready_T)
node _readys_unready_T_2 = bits(_readys_unready_T_1, 3, 0)
node _readys_unready_T_3 = shr(_readys_unready_T_2, 1)
node _readys_unready_T_4 = shl(readys_mask, 2)
node readys_unready = or(_readys_unready_T_3, _readys_unready_T_4)
node _readys_readys_T = shr(readys_unready, 2)
node _readys_readys_T_1 = bits(readys_unready, 1, 0)
node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1)
node readys_readys = not(_readys_readys_T_2)
node _readys_T_5 = orr(readys_valid)
node _readys_T_6 = and(latch, _readys_T_5)
when _readys_T_6 :
node _readys_mask_T = and(readys_readys, readys_valid)
node _readys_mask_T_1 = shl(_readys_mask_T, 1)
node _readys_mask_T_2 = bits(_readys_mask_T_1, 1, 0)
node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2)
node _readys_mask_T_4 = bits(_readys_mask_T_3, 1, 0)
connect readys_mask, _readys_mask_T_4
node _readys_T_7 = bits(readys_readys, 1, 0)
node _readys_T_8 = bits(_readys_T_7, 0, 0)
node _readys_T_9 = bits(_readys_T_7, 1, 1)
wire readys : UInt<1>[2]
connect readys[0], _readys_T_8
connect readys[1], _readys_T_9
node _winner_T = and(readys[0], portsAOI_filtered[0].valid)
node _winner_T_1 = and(readys[1], portsAOI_filtered_1[0].valid)
wire winner : UInt<1>[2]
connect winner[0], _winner_T
connect winner[1], _winner_T_1
node prefixOR_1 = or(UInt<1>(0h0), winner[0])
node _prefixOR_T = or(prefixOR_1, winner[1])
node _T = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_1 = eq(winner[0], UInt<1>(0h0))
node _T_2 = or(_T, _T_1)
node _T_3 = eq(prefixOR_1, UInt<1>(0h0))
node _T_4 = eq(winner[1], UInt<1>(0h0))
node _T_5 = or(_T_3, _T_4)
node _T_6 = and(_T_2, _T_5)
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf
assert(clock, _T_6, UInt<1>(0h1), "") : assert
node _T_10 = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid)
node _T_11 = eq(_T_10, UInt<1>(0h0))
node _T_12 = or(winner[0], winner[1])
node _T_13 = or(_T_11, _T_12)
node _T_14 = asUInt(reset)
node _T_15 = eq(_T_14, UInt<1>(0h0))
when _T_15 :
node _T_16 = eq(_T_13, UInt<1>(0h0))
when _T_16 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1
assert(clock, _T_13, UInt<1>(0h1), "") : assert_1
node maskedBeats_0 = mux(winner[0], beatsAI_0, UInt<1>(0h0))
node maskedBeats_1 = mux(winner[1], beatsAI_1, UInt<1>(0h0))
node initBeats = or(maskedBeats_0, maskedBeats_1)
node _beatsLeft_T = and(out[0].a.ready, out[0].a.valid)
node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T)
node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1)
node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2)
connect beatsLeft, _beatsLeft_T_3
wire _state_WIRE : UInt<1>[2]
connect _state_WIRE[0], UInt<1>(0h0)
connect _state_WIRE[1], UInt<1>(0h0)
regreset state : UInt<1>[2], clock, reset, _state_WIRE
node muxState = mux(idle, winner, state)
connect state, muxState
node allowed = mux(idle, readys, state)
node _filtered_0_ready_T = and(out[0].a.ready, allowed[0])
connect portsAOI_filtered[0].ready, _filtered_0_ready_T
node _filtered_0_ready_T_1 = and(out[0].a.ready, allowed[1])
connect portsAOI_filtered_1[0].ready, _filtered_0_ready_T_1
node _out_0_a_valid_T = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid)
node _out_0_a_valid_T_1 = mux(state[0], portsAOI_filtered[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_2 = mux(state[1], portsAOI_filtered_1[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_3 = or(_out_0_a_valid_T_1, _out_0_a_valid_T_2)
wire _out_0_a_valid_WIRE : UInt<1>
connect _out_0_a_valid_WIRE, _out_0_a_valid_T_3
node _out_0_a_valid_T_4 = mux(idle, _out_0_a_valid_T, _out_0_a_valid_WIRE)
connect out[0].a.valid, _out_0_a_valid_T_4
wire _out_0_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
node _out_0_a_bits_T = mux(muxState[0], portsAOI_filtered[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_1 = mux(muxState[1], portsAOI_filtered_1[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_2 = or(_out_0_a_bits_T, _out_0_a_bits_T_1)
wire _out_0_a_bits_WIRE_1 : UInt<1>
connect _out_0_a_bits_WIRE_1, _out_0_a_bits_T_2
connect _out_0_a_bits_WIRE.corrupt, _out_0_a_bits_WIRE_1
node _out_0_a_bits_T_3 = mux(muxState[0], portsAOI_filtered[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_4 = mux(muxState[1], portsAOI_filtered_1[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_5 = or(_out_0_a_bits_T_3, _out_0_a_bits_T_4)
wire _out_0_a_bits_WIRE_2 : UInt<64>
connect _out_0_a_bits_WIRE_2, _out_0_a_bits_T_5
connect _out_0_a_bits_WIRE.data, _out_0_a_bits_WIRE_2
node _out_0_a_bits_T_6 = mux(muxState[0], portsAOI_filtered[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_7 = mux(muxState[1], portsAOI_filtered_1[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_8 = or(_out_0_a_bits_T_6, _out_0_a_bits_T_7)
wire _out_0_a_bits_WIRE_3 : UInt<8>
connect _out_0_a_bits_WIRE_3, _out_0_a_bits_T_8
connect _out_0_a_bits_WIRE.mask, _out_0_a_bits_WIRE_3
wire _out_0_a_bits_WIRE_4 : { }
connect _out_0_a_bits_WIRE.echo, _out_0_a_bits_WIRE_4
wire _out_0_a_bits_WIRE_5 : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}
wire _out_0_a_bits_WIRE_6 : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}
node _out_0_a_bits_T_9 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.fetch, UInt<1>(0h0))
node _out_0_a_bits_T_10 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.fetch, UInt<1>(0h0))
node _out_0_a_bits_T_11 = or(_out_0_a_bits_T_9, _out_0_a_bits_T_10)
wire _out_0_a_bits_WIRE_7 : UInt<1>
connect _out_0_a_bits_WIRE_7, _out_0_a_bits_T_11
connect _out_0_a_bits_WIRE_6.fetch, _out_0_a_bits_WIRE_7
node _out_0_a_bits_T_12 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.secure, UInt<1>(0h0))
node _out_0_a_bits_T_13 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.secure, UInt<1>(0h0))
node _out_0_a_bits_T_14 = or(_out_0_a_bits_T_12, _out_0_a_bits_T_13)
wire _out_0_a_bits_WIRE_8 : UInt<1>
connect _out_0_a_bits_WIRE_8, _out_0_a_bits_T_14
connect _out_0_a_bits_WIRE_6.secure, _out_0_a_bits_WIRE_8
node _out_0_a_bits_T_15 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.privileged, UInt<1>(0h0))
node _out_0_a_bits_T_16 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.privileged, UInt<1>(0h0))
node _out_0_a_bits_T_17 = or(_out_0_a_bits_T_15, _out_0_a_bits_T_16)
wire _out_0_a_bits_WIRE_9 : UInt<1>
connect _out_0_a_bits_WIRE_9, _out_0_a_bits_T_17
connect _out_0_a_bits_WIRE_6.privileged, _out_0_a_bits_WIRE_9
node _out_0_a_bits_T_18 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.writealloc, UInt<1>(0h0))
node _out_0_a_bits_T_19 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.writealloc, UInt<1>(0h0))
node _out_0_a_bits_T_20 = or(_out_0_a_bits_T_18, _out_0_a_bits_T_19)
wire _out_0_a_bits_WIRE_10 : UInt<1>
connect _out_0_a_bits_WIRE_10, _out_0_a_bits_T_20
connect _out_0_a_bits_WIRE_6.writealloc, _out_0_a_bits_WIRE_10
node _out_0_a_bits_T_21 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.readalloc, UInt<1>(0h0))
node _out_0_a_bits_T_22 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.readalloc, UInt<1>(0h0))
node _out_0_a_bits_T_23 = or(_out_0_a_bits_T_21, _out_0_a_bits_T_22)
wire _out_0_a_bits_WIRE_11 : UInt<1>
connect _out_0_a_bits_WIRE_11, _out_0_a_bits_T_23
connect _out_0_a_bits_WIRE_6.readalloc, _out_0_a_bits_WIRE_11
node _out_0_a_bits_T_24 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.modifiable, UInt<1>(0h0))
node _out_0_a_bits_T_25 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.modifiable, UInt<1>(0h0))
node _out_0_a_bits_T_26 = or(_out_0_a_bits_T_24, _out_0_a_bits_T_25)
wire _out_0_a_bits_WIRE_12 : UInt<1>
connect _out_0_a_bits_WIRE_12, _out_0_a_bits_T_26
connect _out_0_a_bits_WIRE_6.modifiable, _out_0_a_bits_WIRE_12
node _out_0_a_bits_T_27 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.bufferable, UInt<1>(0h0))
node _out_0_a_bits_T_28 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.bufferable, UInt<1>(0h0))
node _out_0_a_bits_T_29 = or(_out_0_a_bits_T_27, _out_0_a_bits_T_28)
wire _out_0_a_bits_WIRE_13 : UInt<1>
connect _out_0_a_bits_WIRE_13, _out_0_a_bits_T_29
connect _out_0_a_bits_WIRE_6.bufferable, _out_0_a_bits_WIRE_13
connect _out_0_a_bits_WIRE_5.amba_prot, _out_0_a_bits_WIRE_6
connect _out_0_a_bits_WIRE.user, _out_0_a_bits_WIRE_5
node _out_0_a_bits_T_30 = mux(muxState[0], portsAOI_filtered[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_31 = mux(muxState[1], portsAOI_filtered_1[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_32 = or(_out_0_a_bits_T_30, _out_0_a_bits_T_31)
wire _out_0_a_bits_WIRE_14 : UInt<32>
connect _out_0_a_bits_WIRE_14, _out_0_a_bits_T_32
connect _out_0_a_bits_WIRE.address, _out_0_a_bits_WIRE_14
node _out_0_a_bits_T_33 = mux(muxState[0], portsAOI_filtered[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_34 = mux(muxState[1], portsAOI_filtered_1[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_35 = or(_out_0_a_bits_T_33, _out_0_a_bits_T_34)
wire _out_0_a_bits_WIRE_15 : UInt<6>
connect _out_0_a_bits_WIRE_15, _out_0_a_bits_T_35
connect _out_0_a_bits_WIRE.source, _out_0_a_bits_WIRE_15
node _out_0_a_bits_T_36 = mux(muxState[0], portsAOI_filtered[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_37 = mux(muxState[1], portsAOI_filtered_1[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_38 = or(_out_0_a_bits_T_36, _out_0_a_bits_T_37)
wire _out_0_a_bits_WIRE_16 : UInt<4>
connect _out_0_a_bits_WIRE_16, _out_0_a_bits_T_38
connect _out_0_a_bits_WIRE.size, _out_0_a_bits_WIRE_16
node _out_0_a_bits_T_39 = mux(muxState[0], portsAOI_filtered[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_40 = mux(muxState[1], portsAOI_filtered_1[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_41 = or(_out_0_a_bits_T_39, _out_0_a_bits_T_40)
wire _out_0_a_bits_WIRE_17 : UInt<3>
connect _out_0_a_bits_WIRE_17, _out_0_a_bits_T_41
connect _out_0_a_bits_WIRE.param, _out_0_a_bits_WIRE_17
node _out_0_a_bits_T_42 = mux(muxState[0], portsAOI_filtered[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_43 = mux(muxState[1], portsAOI_filtered_1[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_44 = or(_out_0_a_bits_T_42, _out_0_a_bits_T_43)
wire _out_0_a_bits_WIRE_18 : UInt<3>
connect _out_0_a_bits_WIRE_18, _out_0_a_bits_T_44
connect _out_0_a_bits_WIRE.opcode, _out_0_a_bits_WIRE_18
connect out[0].a.bits.corrupt, _out_0_a_bits_WIRE.corrupt
connect out[0].a.bits.data, _out_0_a_bits_WIRE.data
connect out[0].a.bits.mask, _out_0_a_bits_WIRE.mask
connect out[0].a.bits.user.amba_prot.fetch, _out_0_a_bits_WIRE.user.amba_prot.fetch
connect out[0].a.bits.user.amba_prot.secure, _out_0_a_bits_WIRE.user.amba_prot.secure
connect out[0].a.bits.user.amba_prot.privileged, _out_0_a_bits_WIRE.user.amba_prot.privileged
connect out[0].a.bits.user.amba_prot.writealloc, _out_0_a_bits_WIRE.user.amba_prot.writealloc
connect out[0].a.bits.user.amba_prot.readalloc, _out_0_a_bits_WIRE.user.amba_prot.readalloc
connect out[0].a.bits.user.amba_prot.modifiable, _out_0_a_bits_WIRE.user.amba_prot.modifiable
connect out[0].a.bits.user.amba_prot.bufferable, _out_0_a_bits_WIRE.user.amba_prot.bufferable
connect out[0].a.bits.address, _out_0_a_bits_WIRE.address
connect out[0].a.bits.source, _out_0_a_bits_WIRE.source
connect out[0].a.bits.size, _out_0_a_bits_WIRE.size
connect out[0].a.bits.param, _out_0_a_bits_WIRE.param
connect out[0].a.bits.opcode, _out_0_a_bits_WIRE.opcode
invalidate out[0].c.bits.corrupt
invalidate out[0].c.bits.data
invalidate out[0].c.bits.user.amba_prot.fetch
invalidate out[0].c.bits.user.amba_prot.secure
invalidate out[0].c.bits.user.amba_prot.privileged
invalidate out[0].c.bits.user.amba_prot.writealloc
invalidate out[0].c.bits.user.amba_prot.readalloc
invalidate out[0].c.bits.user.amba_prot.modifiable
invalidate out[0].c.bits.user.amba_prot.bufferable
invalidate out[0].c.bits.address
invalidate out[0].c.bits.source
invalidate out[0].c.bits.size
invalidate out[0].c.bits.param
invalidate out[0].c.bits.opcode
invalidate out[0].e.bits.sink
connect portsCOI_filtered[0].ready, UInt<1>(0h0)
connect portsCOI_filtered_1[0].ready, UInt<1>(0h0)
connect portsEOI_filtered[0].ready, UInt<1>(0h0)
connect portsEOI_filtered_1[0].ready, UInt<1>(0h0)
regreset beatsLeft_1 : UInt, clock, reset, UInt<1>(0h0)
node idle_1 = eq(beatsLeft_1, UInt<1>(0h0))
node latch_1 = and(idle_1, out[1].a.ready)
node _readys_T_10 = cat(portsAOI_filtered_1[1].valid, portsAOI_filtered[1].valid)
node readys_valid_1 = bits(_readys_T_10, 1, 0)
node _readys_T_11 = eq(readys_valid_1, _readys_T_10)
node _readys_T_12 = asUInt(reset)
node _readys_T_13 = eq(_readys_T_12, UInt<1>(0h0))
when _readys_T_13 :
node _readys_T_14 = eq(_readys_T_11, UInt<1>(0h0))
when _readys_T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_1
assert(clock, _readys_T_11, UInt<1>(0h1), "") : readys_assert_1
regreset readys_mask_1 : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T_2 = not(readys_mask_1)
node _readys_filter_T_3 = and(readys_valid_1, _readys_filter_T_2)
node readys_filter_1 = cat(_readys_filter_T_3, readys_valid_1)
node _readys_unready_T_5 = shr(readys_filter_1, 1)
node _readys_unready_T_6 = or(readys_filter_1, _readys_unready_T_5)
node _readys_unready_T_7 = bits(_readys_unready_T_6, 3, 0)
node _readys_unready_T_8 = shr(_readys_unready_T_7, 1)
node _readys_unready_T_9 = shl(readys_mask_1, 2)
node readys_unready_1 = or(_readys_unready_T_8, _readys_unready_T_9)
node _readys_readys_T_3 = shr(readys_unready_1, 2)
node _readys_readys_T_4 = bits(readys_unready_1, 1, 0)
node _readys_readys_T_5 = and(_readys_readys_T_3, _readys_readys_T_4)
node readys_readys_1 = not(_readys_readys_T_5)
node _readys_T_15 = orr(readys_valid_1)
node _readys_T_16 = and(latch_1, _readys_T_15)
when _readys_T_16 :
node _readys_mask_T_5 = and(readys_readys_1, readys_valid_1)
node _readys_mask_T_6 = shl(_readys_mask_T_5, 1)
node _readys_mask_T_7 = bits(_readys_mask_T_6, 1, 0)
node _readys_mask_T_8 = or(_readys_mask_T_5, _readys_mask_T_7)
node _readys_mask_T_9 = bits(_readys_mask_T_8, 1, 0)
connect readys_mask_1, _readys_mask_T_9
node _readys_T_17 = bits(readys_readys_1, 1, 0)
node _readys_T_18 = bits(_readys_T_17, 0, 0)
node _readys_T_19 = bits(_readys_T_17, 1, 1)
wire readys_1 : UInt<1>[2]
connect readys_1[0], _readys_T_18
connect readys_1[1], _readys_T_19
node _winner_T_2 = and(readys_1[0], portsAOI_filtered[1].valid)
node _winner_T_3 = and(readys_1[1], portsAOI_filtered_1[1].valid)
wire winner_1 : UInt<1>[2]
connect winner_1[0], _winner_T_2
connect winner_1[1], _winner_T_3
node prefixOR_1_1 = or(UInt<1>(0h0), winner_1[0])
node _prefixOR_T_1 = or(prefixOR_1_1, winner_1[1])
node _T_17 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_18 = eq(winner_1[0], UInt<1>(0h0))
node _T_19 = or(_T_17, _T_18)
node _T_20 = eq(prefixOR_1_1, UInt<1>(0h0))
node _T_21 = eq(winner_1[1], UInt<1>(0h0))
node _T_22 = or(_T_20, _T_21)
node _T_23 = and(_T_19, _T_22)
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
node _T_26 = eq(_T_23, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_2
assert(clock, _T_23, UInt<1>(0h1), "") : assert_2
node _T_27 = or(portsAOI_filtered[1].valid, portsAOI_filtered_1[1].valid)
node _T_28 = eq(_T_27, UInt<1>(0h0))
node _T_29 = or(winner_1[0], winner_1[1])
node _T_30 = or(_T_28, _T_29)
node _T_31 = asUInt(reset)
node _T_32 = eq(_T_31, UInt<1>(0h0))
when _T_32 :
node _T_33 = eq(_T_30, UInt<1>(0h0))
when _T_33 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_3
assert(clock, _T_30, UInt<1>(0h1), "") : assert_3
node maskedBeats_0_1 = mux(winner_1[0], beatsAI_0, UInt<1>(0h0))
node maskedBeats_1_1 = mux(winner_1[1], beatsAI_1, UInt<1>(0h0))
node initBeats_1 = or(maskedBeats_0_1, maskedBeats_1_1)
node _beatsLeft_T_4 = and(out[1].a.ready, out[1].a.valid)
node _beatsLeft_T_5 = sub(beatsLeft_1, _beatsLeft_T_4)
node _beatsLeft_T_6 = tail(_beatsLeft_T_5, 1)
node _beatsLeft_T_7 = mux(latch_1, initBeats_1, _beatsLeft_T_6)
connect beatsLeft_1, _beatsLeft_T_7
wire _state_WIRE_1 : UInt<1>[2]
connect _state_WIRE_1[0], UInt<1>(0h0)
connect _state_WIRE_1[1], UInt<1>(0h0)
regreset state_1 : UInt<1>[2], clock, reset, _state_WIRE_1
node muxState_1 = mux(idle_1, winner_1, state_1)
connect state_1, muxState_1
node allowed_1 = mux(idle_1, readys_1, state_1)
node _filtered_1_ready_T = and(out[1].a.ready, allowed_1[0])
connect portsAOI_filtered[1].ready, _filtered_1_ready_T
node _filtered_1_ready_T_1 = and(out[1].a.ready, allowed_1[1])
connect portsAOI_filtered_1[1].ready, _filtered_1_ready_T_1
node _out_1_a_valid_T = or(portsAOI_filtered[1].valid, portsAOI_filtered_1[1].valid)
node _out_1_a_valid_T_1 = mux(state_1[0], portsAOI_filtered[1].valid, UInt<1>(0h0))
node _out_1_a_valid_T_2 = mux(state_1[1], portsAOI_filtered_1[1].valid, UInt<1>(0h0))
node _out_1_a_valid_T_3 = or(_out_1_a_valid_T_1, _out_1_a_valid_T_2)
wire _out_1_a_valid_WIRE : UInt<1>
connect _out_1_a_valid_WIRE, _out_1_a_valid_T_3
node _out_1_a_valid_T_4 = mux(idle_1, _out_1_a_valid_T, _out_1_a_valid_WIRE)
connect out[1].a.valid, _out_1_a_valid_T_4
wire _out_1_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
node _out_1_a_bits_T = mux(muxState_1[0], portsAOI_filtered[1].bits.corrupt, UInt<1>(0h0))
node _out_1_a_bits_T_1 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.corrupt, UInt<1>(0h0))
node _out_1_a_bits_T_2 = or(_out_1_a_bits_T, _out_1_a_bits_T_1)
wire _out_1_a_bits_WIRE_1 : UInt<1>
connect _out_1_a_bits_WIRE_1, _out_1_a_bits_T_2
connect _out_1_a_bits_WIRE.corrupt, _out_1_a_bits_WIRE_1
node _out_1_a_bits_T_3 = mux(muxState_1[0], portsAOI_filtered[1].bits.data, UInt<1>(0h0))
node _out_1_a_bits_T_4 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.data, UInt<1>(0h0))
node _out_1_a_bits_T_5 = or(_out_1_a_bits_T_3, _out_1_a_bits_T_4)
wire _out_1_a_bits_WIRE_2 : UInt<64>
connect _out_1_a_bits_WIRE_2, _out_1_a_bits_T_5
connect _out_1_a_bits_WIRE.data, _out_1_a_bits_WIRE_2
node _out_1_a_bits_T_6 = mux(muxState_1[0], portsAOI_filtered[1].bits.mask, UInt<1>(0h0))
node _out_1_a_bits_T_7 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.mask, UInt<1>(0h0))
node _out_1_a_bits_T_8 = or(_out_1_a_bits_T_6, _out_1_a_bits_T_7)
wire _out_1_a_bits_WIRE_3 : UInt<8>
connect _out_1_a_bits_WIRE_3, _out_1_a_bits_T_8
connect _out_1_a_bits_WIRE.mask, _out_1_a_bits_WIRE_3
wire _out_1_a_bits_WIRE_4 : { }
connect _out_1_a_bits_WIRE.echo, _out_1_a_bits_WIRE_4
wire _out_1_a_bits_WIRE_5 : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}
wire _out_1_a_bits_WIRE_6 : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}
node _out_1_a_bits_T_9 = mux(muxState_1[0], portsAOI_filtered[1].bits.user.amba_prot.fetch, UInt<1>(0h0))
node _out_1_a_bits_T_10 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.user.amba_prot.fetch, UInt<1>(0h0))
node _out_1_a_bits_T_11 = or(_out_1_a_bits_T_9, _out_1_a_bits_T_10)
wire _out_1_a_bits_WIRE_7 : UInt<1>
connect _out_1_a_bits_WIRE_7, _out_1_a_bits_T_11
connect _out_1_a_bits_WIRE_6.fetch, _out_1_a_bits_WIRE_7
node _out_1_a_bits_T_12 = mux(muxState_1[0], portsAOI_filtered[1].bits.user.amba_prot.secure, UInt<1>(0h0))
node _out_1_a_bits_T_13 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.user.amba_prot.secure, UInt<1>(0h0))
node _out_1_a_bits_T_14 = or(_out_1_a_bits_T_12, _out_1_a_bits_T_13)
wire _out_1_a_bits_WIRE_8 : UInt<1>
connect _out_1_a_bits_WIRE_8, _out_1_a_bits_T_14
connect _out_1_a_bits_WIRE_6.secure, _out_1_a_bits_WIRE_8
node _out_1_a_bits_T_15 = mux(muxState_1[0], portsAOI_filtered[1].bits.user.amba_prot.privileged, UInt<1>(0h0))
node _out_1_a_bits_T_16 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.user.amba_prot.privileged, UInt<1>(0h0))
node _out_1_a_bits_T_17 = or(_out_1_a_bits_T_15, _out_1_a_bits_T_16)
wire _out_1_a_bits_WIRE_9 : UInt<1>
connect _out_1_a_bits_WIRE_9, _out_1_a_bits_T_17
connect _out_1_a_bits_WIRE_6.privileged, _out_1_a_bits_WIRE_9
node _out_1_a_bits_T_18 = mux(muxState_1[0], portsAOI_filtered[1].bits.user.amba_prot.writealloc, UInt<1>(0h0))
node _out_1_a_bits_T_19 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.user.amba_prot.writealloc, UInt<1>(0h0))
node _out_1_a_bits_T_20 = or(_out_1_a_bits_T_18, _out_1_a_bits_T_19)
wire _out_1_a_bits_WIRE_10 : UInt<1>
connect _out_1_a_bits_WIRE_10, _out_1_a_bits_T_20
connect _out_1_a_bits_WIRE_6.writealloc, _out_1_a_bits_WIRE_10
node _out_1_a_bits_T_21 = mux(muxState_1[0], portsAOI_filtered[1].bits.user.amba_prot.readalloc, UInt<1>(0h0))
node _out_1_a_bits_T_22 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.user.amba_prot.readalloc, UInt<1>(0h0))
node _out_1_a_bits_T_23 = or(_out_1_a_bits_T_21, _out_1_a_bits_T_22)
wire _out_1_a_bits_WIRE_11 : UInt<1>
connect _out_1_a_bits_WIRE_11, _out_1_a_bits_T_23
connect _out_1_a_bits_WIRE_6.readalloc, _out_1_a_bits_WIRE_11
node _out_1_a_bits_T_24 = mux(muxState_1[0], portsAOI_filtered[1].bits.user.amba_prot.modifiable, UInt<1>(0h0))
node _out_1_a_bits_T_25 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.user.amba_prot.modifiable, UInt<1>(0h0))
node _out_1_a_bits_T_26 = or(_out_1_a_bits_T_24, _out_1_a_bits_T_25)
wire _out_1_a_bits_WIRE_12 : UInt<1>
connect _out_1_a_bits_WIRE_12, _out_1_a_bits_T_26
connect _out_1_a_bits_WIRE_6.modifiable, _out_1_a_bits_WIRE_12
node _out_1_a_bits_T_27 = mux(muxState_1[0], portsAOI_filtered[1].bits.user.amba_prot.bufferable, UInt<1>(0h0))
node _out_1_a_bits_T_28 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.user.amba_prot.bufferable, UInt<1>(0h0))
node _out_1_a_bits_T_29 = or(_out_1_a_bits_T_27, _out_1_a_bits_T_28)
wire _out_1_a_bits_WIRE_13 : UInt<1>
connect _out_1_a_bits_WIRE_13, _out_1_a_bits_T_29
connect _out_1_a_bits_WIRE_6.bufferable, _out_1_a_bits_WIRE_13
connect _out_1_a_bits_WIRE_5.amba_prot, _out_1_a_bits_WIRE_6
connect _out_1_a_bits_WIRE.user, _out_1_a_bits_WIRE_5
node _out_1_a_bits_T_30 = mux(muxState_1[0], portsAOI_filtered[1].bits.address, UInt<1>(0h0))
node _out_1_a_bits_T_31 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.address, UInt<1>(0h0))
node _out_1_a_bits_T_32 = or(_out_1_a_bits_T_30, _out_1_a_bits_T_31)
wire _out_1_a_bits_WIRE_14 : UInt<32>
connect _out_1_a_bits_WIRE_14, _out_1_a_bits_T_32
connect _out_1_a_bits_WIRE.address, _out_1_a_bits_WIRE_14
node _out_1_a_bits_T_33 = mux(muxState_1[0], portsAOI_filtered[1].bits.source, UInt<1>(0h0))
node _out_1_a_bits_T_34 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.source, UInt<1>(0h0))
node _out_1_a_bits_T_35 = or(_out_1_a_bits_T_33, _out_1_a_bits_T_34)
wire _out_1_a_bits_WIRE_15 : UInt<6>
connect _out_1_a_bits_WIRE_15, _out_1_a_bits_T_35
connect _out_1_a_bits_WIRE.source, _out_1_a_bits_WIRE_15
node _out_1_a_bits_T_36 = mux(muxState_1[0], portsAOI_filtered[1].bits.size, UInt<1>(0h0))
node _out_1_a_bits_T_37 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.size, UInt<1>(0h0))
node _out_1_a_bits_T_38 = or(_out_1_a_bits_T_36, _out_1_a_bits_T_37)
wire _out_1_a_bits_WIRE_16 : UInt<4>
connect _out_1_a_bits_WIRE_16, _out_1_a_bits_T_38
connect _out_1_a_bits_WIRE.size, _out_1_a_bits_WIRE_16
node _out_1_a_bits_T_39 = mux(muxState_1[0], portsAOI_filtered[1].bits.param, UInt<1>(0h0))
node _out_1_a_bits_T_40 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.param, UInt<1>(0h0))
node _out_1_a_bits_T_41 = or(_out_1_a_bits_T_39, _out_1_a_bits_T_40)
wire _out_1_a_bits_WIRE_17 : UInt<3>
connect _out_1_a_bits_WIRE_17, _out_1_a_bits_T_41
connect _out_1_a_bits_WIRE.param, _out_1_a_bits_WIRE_17
node _out_1_a_bits_T_42 = mux(muxState_1[0], portsAOI_filtered[1].bits.opcode, UInt<1>(0h0))
node _out_1_a_bits_T_43 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.opcode, UInt<1>(0h0))
node _out_1_a_bits_T_44 = or(_out_1_a_bits_T_42, _out_1_a_bits_T_43)
wire _out_1_a_bits_WIRE_18 : UInt<3>
connect _out_1_a_bits_WIRE_18, _out_1_a_bits_T_44
connect _out_1_a_bits_WIRE.opcode, _out_1_a_bits_WIRE_18
connect out[1].a.bits.corrupt, _out_1_a_bits_WIRE.corrupt
connect out[1].a.bits.data, _out_1_a_bits_WIRE.data
connect out[1].a.bits.mask, _out_1_a_bits_WIRE.mask
connect out[1].a.bits.user.amba_prot.fetch, _out_1_a_bits_WIRE.user.amba_prot.fetch
connect out[1].a.bits.user.amba_prot.secure, _out_1_a_bits_WIRE.user.amba_prot.secure
connect out[1].a.bits.user.amba_prot.privileged, _out_1_a_bits_WIRE.user.amba_prot.privileged
connect out[1].a.bits.user.amba_prot.writealloc, _out_1_a_bits_WIRE.user.amba_prot.writealloc
connect out[1].a.bits.user.amba_prot.readalloc, _out_1_a_bits_WIRE.user.amba_prot.readalloc
connect out[1].a.bits.user.amba_prot.modifiable, _out_1_a_bits_WIRE.user.amba_prot.modifiable
connect out[1].a.bits.user.amba_prot.bufferable, _out_1_a_bits_WIRE.user.amba_prot.bufferable
connect out[1].a.bits.address, _out_1_a_bits_WIRE.address
connect out[1].a.bits.source, _out_1_a_bits_WIRE.source
connect out[1].a.bits.size, _out_1_a_bits_WIRE.size
connect out[1].a.bits.param, _out_1_a_bits_WIRE.param
connect out[1].a.bits.opcode, _out_1_a_bits_WIRE.opcode
connect out[1].c, portsCOI_filtered_1[1]
connect out[1].e, portsEOI_filtered_1[1]
connect portsCOI_filtered[1].ready, UInt<1>(0h0)
connect portsEOI_filtered[1].ready, UInt<1>(0h0)
invalidate in[0].b.bits.corrupt
invalidate in[0].b.bits.data
invalidate in[0].b.bits.mask
invalidate in[0].b.bits.address
invalidate in[0].b.bits.source
invalidate in[0].b.bits.size
invalidate in[0].b.bits.param
invalidate in[0].b.bits.opcode
regreset beatsLeft_2 : UInt, clock, reset, UInt<1>(0h0)
node idle_2 = eq(beatsLeft_2, UInt<1>(0h0))
node latch_2 = and(idle_2, in[0].d.ready)
node _readys_T_20 = cat(portsDIO_filtered_1[0].valid, portsDIO_filtered[0].valid)
node readys_valid_2 = bits(_readys_T_20, 1, 0)
node _readys_T_21 = eq(readys_valid_2, _readys_T_20)
node _readys_T_22 = asUInt(reset)
node _readys_T_23 = eq(_readys_T_22, UInt<1>(0h0))
when _readys_T_23 :
node _readys_T_24 = eq(_readys_T_21, UInt<1>(0h0))
when _readys_T_24 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_2
assert(clock, _readys_T_21, UInt<1>(0h1), "") : readys_assert_2
regreset readys_mask_2 : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T_4 = not(readys_mask_2)
node _readys_filter_T_5 = and(readys_valid_2, _readys_filter_T_4)
node readys_filter_2 = cat(_readys_filter_T_5, readys_valid_2)
node _readys_unready_T_10 = shr(readys_filter_2, 1)
node _readys_unready_T_11 = or(readys_filter_2, _readys_unready_T_10)
node _readys_unready_T_12 = bits(_readys_unready_T_11, 3, 0)
node _readys_unready_T_13 = shr(_readys_unready_T_12, 1)
node _readys_unready_T_14 = shl(readys_mask_2, 2)
node readys_unready_2 = or(_readys_unready_T_13, _readys_unready_T_14)
node _readys_readys_T_6 = shr(readys_unready_2, 2)
node _readys_readys_T_7 = bits(readys_unready_2, 1, 0)
node _readys_readys_T_8 = and(_readys_readys_T_6, _readys_readys_T_7)
node readys_readys_2 = not(_readys_readys_T_8)
node _readys_T_25 = orr(readys_valid_2)
node _readys_T_26 = and(latch_2, _readys_T_25)
when _readys_T_26 :
node _readys_mask_T_10 = and(readys_readys_2, readys_valid_2)
node _readys_mask_T_11 = shl(_readys_mask_T_10, 1)
node _readys_mask_T_12 = bits(_readys_mask_T_11, 1, 0)
node _readys_mask_T_13 = or(_readys_mask_T_10, _readys_mask_T_12)
node _readys_mask_T_14 = bits(_readys_mask_T_13, 1, 0)
connect readys_mask_2, _readys_mask_T_14
node _readys_T_27 = bits(readys_readys_2, 1, 0)
node _readys_T_28 = bits(_readys_T_27, 0, 0)
node _readys_T_29 = bits(_readys_T_27, 1, 1)
wire readys_2 : UInt<1>[2]
connect readys_2[0], _readys_T_28
connect readys_2[1], _readys_T_29
node _winner_T_4 = and(readys_2[0], portsDIO_filtered[0].valid)
node _winner_T_5 = and(readys_2[1], portsDIO_filtered_1[0].valid)
wire winner_2 : UInt<1>[2]
connect winner_2[0], _winner_T_4
connect winner_2[1], _winner_T_5
node prefixOR_1_2 = or(UInt<1>(0h0), winner_2[0])
node _prefixOR_T_2 = or(prefixOR_1_2, winner_2[1])
node _T_34 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_35 = eq(winner_2[0], UInt<1>(0h0))
node _T_36 = or(_T_34, _T_35)
node _T_37 = eq(prefixOR_1_2, UInt<1>(0h0))
node _T_38 = eq(winner_2[1], UInt<1>(0h0))
node _T_39 = or(_T_37, _T_38)
node _T_40 = and(_T_36, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_4
assert(clock, _T_40, UInt<1>(0h1), "") : assert_4
node _T_44 = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid)
node _T_45 = eq(_T_44, UInt<1>(0h0))
node _T_46 = or(winner_2[0], winner_2[1])
node _T_47 = or(_T_45, _T_46)
node _T_48 = asUInt(reset)
node _T_49 = eq(_T_48, UInt<1>(0h0))
when _T_49 :
node _T_50 = eq(_T_47, UInt<1>(0h0))
when _T_50 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_5
assert(clock, _T_47, UInt<1>(0h1), "") : assert_5
node maskedBeats_0_2 = mux(winner_2[0], beatsDO_0, UInt<1>(0h0))
node maskedBeats_1_2 = mux(winner_2[1], beatsDO_1, UInt<1>(0h0))
node initBeats_2 = or(maskedBeats_0_2, maskedBeats_1_2)
node _beatsLeft_T_8 = and(in[0].d.ready, in[0].d.valid)
node _beatsLeft_T_9 = sub(beatsLeft_2, _beatsLeft_T_8)
node _beatsLeft_T_10 = tail(_beatsLeft_T_9, 1)
node _beatsLeft_T_11 = mux(latch_2, initBeats_2, _beatsLeft_T_10)
connect beatsLeft_2, _beatsLeft_T_11
wire _state_WIRE_2 : UInt<1>[2]
connect _state_WIRE_2[0], UInt<1>(0h0)
connect _state_WIRE_2[1], UInt<1>(0h0)
regreset state_2 : UInt<1>[2], clock, reset, _state_WIRE_2
node muxState_2 = mux(idle_2, winner_2, state_2)
connect state_2, muxState_2
node allowed_2 = mux(idle_2, readys_2, state_2)
node _filtered_0_ready_T_2 = and(in[0].d.ready, allowed_2[0])
connect portsDIO_filtered[0].ready, _filtered_0_ready_T_2
node _filtered_0_ready_T_3 = and(in[0].d.ready, allowed_2[1])
connect portsDIO_filtered_1[0].ready, _filtered_0_ready_T_3
node _in_0_d_valid_T = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid)
node _in_0_d_valid_T_1 = mux(state_2[0], portsDIO_filtered[0].valid, UInt<1>(0h0))
node _in_0_d_valid_T_2 = mux(state_2[1], portsDIO_filtered_1[0].valid, UInt<1>(0h0))
node _in_0_d_valid_T_3 = or(_in_0_d_valid_T_1, _in_0_d_valid_T_2)
wire _in_0_d_valid_WIRE : UInt<1>
connect _in_0_d_valid_WIRE, _in_0_d_valid_T_3
node _in_0_d_valid_T_4 = mux(idle_2, _in_0_d_valid_T, _in_0_d_valid_WIRE)
connect in[0].d.valid, _in_0_d_valid_T_4
wire _in_0_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_0_d_bits_T = mux(muxState_2[0], portsDIO_filtered[0].bits.corrupt, UInt<1>(0h0))
node _in_0_d_bits_T_1 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.corrupt, UInt<1>(0h0))
node _in_0_d_bits_T_2 = or(_in_0_d_bits_T, _in_0_d_bits_T_1)
wire _in_0_d_bits_WIRE_1 : UInt<1>
connect _in_0_d_bits_WIRE_1, _in_0_d_bits_T_2
connect _in_0_d_bits_WIRE.corrupt, _in_0_d_bits_WIRE_1
node _in_0_d_bits_T_3 = mux(muxState_2[0], portsDIO_filtered[0].bits.data, UInt<1>(0h0))
node _in_0_d_bits_T_4 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.data, UInt<1>(0h0))
node _in_0_d_bits_T_5 = or(_in_0_d_bits_T_3, _in_0_d_bits_T_4)
wire _in_0_d_bits_WIRE_2 : UInt<64>
connect _in_0_d_bits_WIRE_2, _in_0_d_bits_T_5
connect _in_0_d_bits_WIRE.data, _in_0_d_bits_WIRE_2
wire _in_0_d_bits_WIRE_3 : { }
connect _in_0_d_bits_WIRE.echo, _in_0_d_bits_WIRE_3
wire _in_0_d_bits_WIRE_4 : { }
connect _in_0_d_bits_WIRE.user, _in_0_d_bits_WIRE_4
node _in_0_d_bits_T_6 = mux(muxState_2[0], portsDIO_filtered[0].bits.denied, UInt<1>(0h0))
node _in_0_d_bits_T_7 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.denied, UInt<1>(0h0))
node _in_0_d_bits_T_8 = or(_in_0_d_bits_T_6, _in_0_d_bits_T_7)
wire _in_0_d_bits_WIRE_5 : UInt<1>
connect _in_0_d_bits_WIRE_5, _in_0_d_bits_T_8
connect _in_0_d_bits_WIRE.denied, _in_0_d_bits_WIRE_5
node _in_0_d_bits_T_9 = mux(muxState_2[0], portsDIO_filtered[0].bits.sink, UInt<1>(0h0))
node _in_0_d_bits_T_10 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.sink, UInt<1>(0h0))
node _in_0_d_bits_T_11 = or(_in_0_d_bits_T_9, _in_0_d_bits_T_10)
wire _in_0_d_bits_WIRE_6 : UInt<3>
connect _in_0_d_bits_WIRE_6, _in_0_d_bits_T_11
connect _in_0_d_bits_WIRE.sink, _in_0_d_bits_WIRE_6
node _in_0_d_bits_T_12 = mux(muxState_2[0], portsDIO_filtered[0].bits.source, UInt<1>(0h0))
node _in_0_d_bits_T_13 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.source, UInt<1>(0h0))
node _in_0_d_bits_T_14 = or(_in_0_d_bits_T_12, _in_0_d_bits_T_13)
wire _in_0_d_bits_WIRE_7 : UInt<6>
connect _in_0_d_bits_WIRE_7, _in_0_d_bits_T_14
connect _in_0_d_bits_WIRE.source, _in_0_d_bits_WIRE_7
node _in_0_d_bits_T_15 = mux(muxState_2[0], portsDIO_filtered[0].bits.size, UInt<1>(0h0))
node _in_0_d_bits_T_16 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.size, UInt<1>(0h0))
node _in_0_d_bits_T_17 = or(_in_0_d_bits_T_15, _in_0_d_bits_T_16)
wire _in_0_d_bits_WIRE_8 : UInt<4>
connect _in_0_d_bits_WIRE_8, _in_0_d_bits_T_17
connect _in_0_d_bits_WIRE.size, _in_0_d_bits_WIRE_8
node _in_0_d_bits_T_18 = mux(muxState_2[0], portsDIO_filtered[0].bits.param, UInt<1>(0h0))
node _in_0_d_bits_T_19 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.param, UInt<1>(0h0))
node _in_0_d_bits_T_20 = or(_in_0_d_bits_T_18, _in_0_d_bits_T_19)
wire _in_0_d_bits_WIRE_9 : UInt<2>
connect _in_0_d_bits_WIRE_9, _in_0_d_bits_T_20
connect _in_0_d_bits_WIRE.param, _in_0_d_bits_WIRE_9
node _in_0_d_bits_T_21 = mux(muxState_2[0], portsDIO_filtered[0].bits.opcode, UInt<1>(0h0))
node _in_0_d_bits_T_22 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.opcode, UInt<1>(0h0))
node _in_0_d_bits_T_23 = or(_in_0_d_bits_T_21, _in_0_d_bits_T_22)
wire _in_0_d_bits_WIRE_10 : UInt<3>
connect _in_0_d_bits_WIRE_10, _in_0_d_bits_T_23
connect _in_0_d_bits_WIRE.opcode, _in_0_d_bits_WIRE_10
connect in[0].d.bits.corrupt, _in_0_d_bits_WIRE.corrupt
connect in[0].d.bits.data, _in_0_d_bits_WIRE.data
connect in[0].d.bits.denied, _in_0_d_bits_WIRE.denied
connect in[0].d.bits.sink, _in_0_d_bits_WIRE.sink
connect in[0].d.bits.source, _in_0_d_bits_WIRE.source
connect in[0].d.bits.size, _in_0_d_bits_WIRE.size
connect in[0].d.bits.param, _in_0_d_bits_WIRE.param
connect in[0].d.bits.opcode, _in_0_d_bits_WIRE.opcode
connect portsBIO_filtered[0].ready, UInt<1>(0h0)
connect portsBIO_filtered_1[0].ready, UInt<1>(0h0)
connect in[1].b, portsBIO_filtered_1[1]
regreset beatsLeft_3 : UInt, clock, reset, UInt<1>(0h0)
node idle_3 = eq(beatsLeft_3, UInt<1>(0h0))
node latch_3 = and(idle_3, in[1].d.ready)
node _readys_T_30 = cat(portsDIO_filtered_1[1].valid, portsDIO_filtered[1].valid)
node readys_valid_3 = bits(_readys_T_30, 1, 0)
node _readys_T_31 = eq(readys_valid_3, _readys_T_30)
node _readys_T_32 = asUInt(reset)
node _readys_T_33 = eq(_readys_T_32, UInt<1>(0h0))
when _readys_T_33 :
node _readys_T_34 = eq(_readys_T_31, UInt<1>(0h0))
when _readys_T_34 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_3
assert(clock, _readys_T_31, UInt<1>(0h1), "") : readys_assert_3
regreset readys_mask_3 : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T_6 = not(readys_mask_3)
node _readys_filter_T_7 = and(readys_valid_3, _readys_filter_T_6)
node readys_filter_3 = cat(_readys_filter_T_7, readys_valid_3)
node _readys_unready_T_15 = shr(readys_filter_3, 1)
node _readys_unready_T_16 = or(readys_filter_3, _readys_unready_T_15)
node _readys_unready_T_17 = bits(_readys_unready_T_16, 3, 0)
node _readys_unready_T_18 = shr(_readys_unready_T_17, 1)
node _readys_unready_T_19 = shl(readys_mask_3, 2)
node readys_unready_3 = or(_readys_unready_T_18, _readys_unready_T_19)
node _readys_readys_T_9 = shr(readys_unready_3, 2)
node _readys_readys_T_10 = bits(readys_unready_3, 1, 0)
node _readys_readys_T_11 = and(_readys_readys_T_9, _readys_readys_T_10)
node readys_readys_3 = not(_readys_readys_T_11)
node _readys_T_35 = orr(readys_valid_3)
node _readys_T_36 = and(latch_3, _readys_T_35)
when _readys_T_36 :
node _readys_mask_T_15 = and(readys_readys_3, readys_valid_3)
node _readys_mask_T_16 = shl(_readys_mask_T_15, 1)
node _readys_mask_T_17 = bits(_readys_mask_T_16, 1, 0)
node _readys_mask_T_18 = or(_readys_mask_T_15, _readys_mask_T_17)
node _readys_mask_T_19 = bits(_readys_mask_T_18, 1, 0)
connect readys_mask_3, _readys_mask_T_19
node _readys_T_37 = bits(readys_readys_3, 1, 0)
node _readys_T_38 = bits(_readys_T_37, 0, 0)
node _readys_T_39 = bits(_readys_T_37, 1, 1)
wire readys_3 : UInt<1>[2]
connect readys_3[0], _readys_T_38
connect readys_3[1], _readys_T_39
node _winner_T_6 = and(readys_3[0], portsDIO_filtered[1].valid)
node _winner_T_7 = and(readys_3[1], portsDIO_filtered_1[1].valid)
wire winner_3 : UInt<1>[2]
connect winner_3[0], _winner_T_6
connect winner_3[1], _winner_T_7
node prefixOR_1_3 = or(UInt<1>(0h0), winner_3[0])
node _prefixOR_T_3 = or(prefixOR_1_3, winner_3[1])
node _T_51 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_52 = eq(winner_3[0], UInt<1>(0h0))
node _T_53 = or(_T_51, _T_52)
node _T_54 = eq(prefixOR_1_3, UInt<1>(0h0))
node _T_55 = eq(winner_3[1], UInt<1>(0h0))
node _T_56 = or(_T_54, _T_55)
node _T_57 = and(_T_53, _T_56)
node _T_58 = asUInt(reset)
node _T_59 = eq(_T_58, UInt<1>(0h0))
when _T_59 :
node _T_60 = eq(_T_57, UInt<1>(0h0))
when _T_60 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_6
assert(clock, _T_57, UInt<1>(0h1), "") : assert_6
node _T_61 = or(portsDIO_filtered[1].valid, portsDIO_filtered_1[1].valid)
node _T_62 = eq(_T_61, UInt<1>(0h0))
node _T_63 = or(winner_3[0], winner_3[1])
node _T_64 = or(_T_62, _T_63)
node _T_65 = asUInt(reset)
node _T_66 = eq(_T_65, UInt<1>(0h0))
when _T_66 :
node _T_67 = eq(_T_64, UInt<1>(0h0))
when _T_67 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_7
assert(clock, _T_64, UInt<1>(0h1), "") : assert_7
node maskedBeats_0_3 = mux(winner_3[0], beatsDO_0, UInt<1>(0h0))
node maskedBeats_1_3 = mux(winner_3[1], beatsDO_1, UInt<1>(0h0))
node initBeats_3 = or(maskedBeats_0_3, maskedBeats_1_3)
node _beatsLeft_T_12 = and(in[1].d.ready, in[1].d.valid)
node _beatsLeft_T_13 = sub(beatsLeft_3, _beatsLeft_T_12)
node _beatsLeft_T_14 = tail(_beatsLeft_T_13, 1)
node _beatsLeft_T_15 = mux(latch_3, initBeats_3, _beatsLeft_T_14)
connect beatsLeft_3, _beatsLeft_T_15
wire _state_WIRE_3 : UInt<1>[2]
connect _state_WIRE_3[0], UInt<1>(0h0)
connect _state_WIRE_3[1], UInt<1>(0h0)
regreset state_3 : UInt<1>[2], clock, reset, _state_WIRE_3
node muxState_3 = mux(idle_3, winner_3, state_3)
connect state_3, muxState_3
node allowed_3 = mux(idle_3, readys_3, state_3)
node _filtered_1_ready_T_2 = and(in[1].d.ready, allowed_3[0])
connect portsDIO_filtered[1].ready, _filtered_1_ready_T_2
node _filtered_1_ready_T_3 = and(in[1].d.ready, allowed_3[1])
connect portsDIO_filtered_1[1].ready, _filtered_1_ready_T_3
node _in_1_d_valid_T = or(portsDIO_filtered[1].valid, portsDIO_filtered_1[1].valid)
node _in_1_d_valid_T_1 = mux(state_3[0], portsDIO_filtered[1].valid, UInt<1>(0h0))
node _in_1_d_valid_T_2 = mux(state_3[1], portsDIO_filtered_1[1].valid, UInt<1>(0h0))
node _in_1_d_valid_T_3 = or(_in_1_d_valid_T_1, _in_1_d_valid_T_2)
wire _in_1_d_valid_WIRE : UInt<1>
connect _in_1_d_valid_WIRE, _in_1_d_valid_T_3
node _in_1_d_valid_T_4 = mux(idle_3, _in_1_d_valid_T, _in_1_d_valid_WIRE)
connect in[1].d.valid, _in_1_d_valid_T_4
wire _in_1_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_1_d_bits_T = mux(muxState_3[0], portsDIO_filtered[1].bits.corrupt, UInt<1>(0h0))
node _in_1_d_bits_T_1 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.corrupt, UInt<1>(0h0))
node _in_1_d_bits_T_2 = or(_in_1_d_bits_T, _in_1_d_bits_T_1)
wire _in_1_d_bits_WIRE_1 : UInt<1>
connect _in_1_d_bits_WIRE_1, _in_1_d_bits_T_2
connect _in_1_d_bits_WIRE.corrupt, _in_1_d_bits_WIRE_1
node _in_1_d_bits_T_3 = mux(muxState_3[0], portsDIO_filtered[1].bits.data, UInt<1>(0h0))
node _in_1_d_bits_T_4 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.data, UInt<1>(0h0))
node _in_1_d_bits_T_5 = or(_in_1_d_bits_T_3, _in_1_d_bits_T_4)
wire _in_1_d_bits_WIRE_2 : UInt<64>
connect _in_1_d_bits_WIRE_2, _in_1_d_bits_T_5
connect _in_1_d_bits_WIRE.data, _in_1_d_bits_WIRE_2
wire _in_1_d_bits_WIRE_3 : { }
connect _in_1_d_bits_WIRE.echo, _in_1_d_bits_WIRE_3
wire _in_1_d_bits_WIRE_4 : { }
connect _in_1_d_bits_WIRE.user, _in_1_d_bits_WIRE_4
node _in_1_d_bits_T_6 = mux(muxState_3[0], portsDIO_filtered[1].bits.denied, UInt<1>(0h0))
node _in_1_d_bits_T_7 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.denied, UInt<1>(0h0))
node _in_1_d_bits_T_8 = or(_in_1_d_bits_T_6, _in_1_d_bits_T_7)
wire _in_1_d_bits_WIRE_5 : UInt<1>
connect _in_1_d_bits_WIRE_5, _in_1_d_bits_T_8
connect _in_1_d_bits_WIRE.denied, _in_1_d_bits_WIRE_5
node _in_1_d_bits_T_9 = mux(muxState_3[0], portsDIO_filtered[1].bits.sink, UInt<1>(0h0))
node _in_1_d_bits_T_10 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.sink, UInt<1>(0h0))
node _in_1_d_bits_T_11 = or(_in_1_d_bits_T_9, _in_1_d_bits_T_10)
wire _in_1_d_bits_WIRE_6 : UInt<3>
connect _in_1_d_bits_WIRE_6, _in_1_d_bits_T_11
connect _in_1_d_bits_WIRE.sink, _in_1_d_bits_WIRE_6
node _in_1_d_bits_T_12 = mux(muxState_3[0], portsDIO_filtered[1].bits.source, UInt<1>(0h0))
node _in_1_d_bits_T_13 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.source, UInt<1>(0h0))
node _in_1_d_bits_T_14 = or(_in_1_d_bits_T_12, _in_1_d_bits_T_13)
wire _in_1_d_bits_WIRE_7 : UInt<6>
connect _in_1_d_bits_WIRE_7, _in_1_d_bits_T_14
connect _in_1_d_bits_WIRE.source, _in_1_d_bits_WIRE_7
node _in_1_d_bits_T_15 = mux(muxState_3[0], portsDIO_filtered[1].bits.size, UInt<1>(0h0))
node _in_1_d_bits_T_16 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.size, UInt<1>(0h0))
node _in_1_d_bits_T_17 = or(_in_1_d_bits_T_15, _in_1_d_bits_T_16)
wire _in_1_d_bits_WIRE_8 : UInt<4>
connect _in_1_d_bits_WIRE_8, _in_1_d_bits_T_17
connect _in_1_d_bits_WIRE.size, _in_1_d_bits_WIRE_8
node _in_1_d_bits_T_18 = mux(muxState_3[0], portsDIO_filtered[1].bits.param, UInt<1>(0h0))
node _in_1_d_bits_T_19 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.param, UInt<1>(0h0))
node _in_1_d_bits_T_20 = or(_in_1_d_bits_T_18, _in_1_d_bits_T_19)
wire _in_1_d_bits_WIRE_9 : UInt<2>
connect _in_1_d_bits_WIRE_9, _in_1_d_bits_T_20
connect _in_1_d_bits_WIRE.param, _in_1_d_bits_WIRE_9
node _in_1_d_bits_T_21 = mux(muxState_3[0], portsDIO_filtered[1].bits.opcode, UInt<1>(0h0))
node _in_1_d_bits_T_22 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.opcode, UInt<1>(0h0))
node _in_1_d_bits_T_23 = or(_in_1_d_bits_T_21, _in_1_d_bits_T_22)
wire _in_1_d_bits_WIRE_10 : UInt<3>
connect _in_1_d_bits_WIRE_10, _in_1_d_bits_T_23
connect _in_1_d_bits_WIRE.opcode, _in_1_d_bits_WIRE_10
connect in[1].d.bits.corrupt, _in_1_d_bits_WIRE.corrupt
connect in[1].d.bits.data, _in_1_d_bits_WIRE.data
connect in[1].d.bits.denied, _in_1_d_bits_WIRE.denied
connect in[1].d.bits.sink, _in_1_d_bits_WIRE.sink
connect in[1].d.bits.source, _in_1_d_bits_WIRE.source
connect in[1].d.bits.size, _in_1_d_bits_WIRE.size
connect in[1].d.bits.param, _in_1_d_bits_WIRE.param
connect in[1].d.bits.opcode, _in_1_d_bits_WIRE.opcode
connect portsBIO_filtered[1].ready, UInt<1>(0h0) | module TLXbar_sbus_i2_o2_a32d64s6k3z4c( // @[Xbar.scala:74:9]
input clock, // @[Xbar.scala:74:9]
input reset, // @[Xbar.scala:74:9]
output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_b_valid, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_1_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_in_1_b_bits_address, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_1_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_1_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_in_1_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_1_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_1_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_1_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_b_valid, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_1_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_out_1_b_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_anon_out_1_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_1_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_1_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire allowed_3_1; // @[Arbiter.scala:92:24]
wire allowed_3_0; // @[Arbiter.scala:92:24]
wire allowed_2_1; // @[Arbiter.scala:92:24]
wire allowed_2_0; // @[Arbiter.scala:92:24]
wire allowed_1_1; // @[Arbiter.scala:92:24]
wire allowed_1_0; // @[Arbiter.scala:92:24]
wire allowed_1; // @[Arbiter.scala:92:24]
wire allowed_0; // @[Arbiter.scala:92:24]
wire [5:0] in_0_a_bits_source = {1'h0, auto_anon_in_0_a_bits_source}; // @[Xbar.scala:74:9, :166:29]
wire [5:0] in_1_a_bits_source = {4'h8, auto_anon_in_1_a_bits_source}; // @[Xbar.scala:166:55]
wire [2:0] out_0_d_bits_sink = {2'h0, auto_anon_out_0_d_bits_sink}; // @[Xbar.scala:74:9, :251:28]
wire [3:0] out_1_d_bits_size = {1'h0, auto_anon_out_1_d_bits_size}; // @[Xbar.scala:74:9, :250:29]
wire requestAIO_0_0 = {auto_anon_in_0_a_bits_address[31], auto_anon_in_0_a_bits_address[27:26]} == 3'h0 | {auto_anon_in_0_a_bits_address[31], auto_anon_in_0_a_bits_address[27:26], ~(auto_anon_in_0_a_bits_address[16]), auto_anon_in_0_a_bits_address[12]} == 5'h0 | {auto_anon_in_0_a_bits_address[31], ~(auto_anon_in_0_a_bits_address[27:26])} == 3'h0; // @[Xbar.scala:291:92]
wire requestAIO_0_1 = {auto_anon_in_0_a_bits_address[31], auto_anon_in_0_a_bits_address[27:26] ^ 2'h2, auto_anon_in_0_a_bits_address[16]} == 4'h0 | auto_anon_in_0_a_bits_address[31]; // @[Xbar.scala:74:9, :291:92]
wire requestAIO_1_0 = {auto_anon_in_1_a_bits_address[31], auto_anon_in_1_a_bits_address[27:26]} == 3'h0 | {auto_anon_in_1_a_bits_address[31], auto_anon_in_1_a_bits_address[27:26], ~(auto_anon_in_1_a_bits_address[16]), auto_anon_in_1_a_bits_address[12]} == 5'h0 | {auto_anon_in_1_a_bits_address[31], ~(auto_anon_in_1_a_bits_address[27:26])} == 3'h0; // @[Xbar.scala:291:92]
wire requestAIO_1_1 = {auto_anon_in_1_a_bits_address[31], auto_anon_in_1_a_bits_address[27:26] ^ 2'h2, auto_anon_in_1_a_bits_address[16]} == 4'h0 | auto_anon_in_1_a_bits_address[31]; // @[Xbar.scala:74:9, :291:92]
wire requestDOI_0_1 = auto_anon_out_0_d_bits_source[5:2] == 4'h8; // @[Parameters.scala:54:{10,32}]
wire requestDOI_1_1 = auto_anon_out_1_d_bits_source[5:2] == 4'h8; // @[Parameters.scala:54:{10,32}]
wire portsAOI_filtered_0_valid = auto_anon_in_0_a_valid & requestAIO_0_0; // @[Xbar.scala:291:92, :355:40]
wire portsAOI_filtered_1_valid = auto_anon_in_0_a_valid & requestAIO_0_1; // @[Xbar.scala:291:92, :355:40]
wire _portsAOI_in_0_a_ready_T_2 = requestAIO_0_0 & auto_anon_out_0_a_ready & allowed_0 | requestAIO_0_1 & auto_anon_out_1_a_ready & allowed_1_0; // @[Mux.scala:30:73]
wire portsAOI_filtered_1_0_valid = auto_anon_in_1_a_valid & requestAIO_1_0; // @[Xbar.scala:291:92, :355:40]
wire portsAOI_filtered_1_1_valid = auto_anon_in_1_a_valid & requestAIO_1_1; // @[Xbar.scala:291:92, :355:40]
wire _portsAOI_in_1_a_ready_T_2 = requestAIO_1_0 & auto_anon_out_0_a_ready & allowed_1 | requestAIO_1_1 & auto_anon_out_1_a_ready & allowed_1_1; // @[Mux.scala:30:73]
wire portsDIO_filtered_0_valid = auto_anon_out_0_d_valid & ~(auto_anon_out_0_d_bits_source[5]); // @[Xbar.scala:355:40]
wire portsDIO_filtered_1_valid = auto_anon_out_0_d_valid & requestDOI_0_1; // @[Xbar.scala:355:40]
wire portsDIO_filtered_1_0_valid = auto_anon_out_1_d_valid & ~(auto_anon_out_1_d_bits_source[5]); // @[Xbar.scala:355:40]
wire portsDIO_filtered_1_1_valid = auto_anon_out_1_d_valid & requestDOI_1_1; // @[Xbar.scala:355:40]
reg [8:0] beatsLeft; // @[Arbiter.scala:60:30]
wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire [1:0] readys_valid = {portsAOI_filtered_1_0_valid, portsAOI_filtered_0_valid}; // @[Xbar.scala:355:40]
reg [1:0] readys_mask; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T_1 = readys_valid & ~readys_mask; // @[Arbiter.scala:23:23, :24:{28,30}, :68:51]
wire [1:0] readys_readys = ~({readys_mask[1], _readys_filter_T_1[1] | readys_mask[0]} & ({_readys_filter_T_1[0], portsAOI_filtered_1_0_valid} | _readys_filter_T_1)); // @[package.scala:262:43]
wire winner_0 = readys_readys[0] & portsAOI_filtered_0_valid; // @[Xbar.scala:355:40]
wire winner_1 = readys_readys[1] & portsAOI_filtered_1_0_valid; // @[Xbar.scala:355:40]
wire _out_0_a_valid_T = portsAOI_filtered_0_valid | portsAOI_filtered_1_0_valid; // @[Xbar.scala:355:40]
reg state_0; // @[Arbiter.scala:88:26]
reg state_1; // @[Arbiter.scala:88:26]
wire muxState_0 = idle ? winner_0 : state_0; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25]
wire muxState_1 = idle ? winner_1 : state_1; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25]
assign allowed_0 = idle ? readys_readys[0] : state_0; // @[Arbiter.scala:26:18, :61:28, :68:76, :88:26, :92:24]
assign allowed_1 = idle ? readys_readys[1] : state_1; // @[Arbiter.scala:26:18, :61:28, :68:76, :88:26, :92:24]
wire out_0_a_valid = idle ? _out_0_a_valid_T : state_0 & portsAOI_filtered_0_valid | state_1 & portsAOI_filtered_1_0_valid; // @[Mux.scala:30:73]
reg [8:0] beatsLeft_1; // @[Arbiter.scala:60:30]
wire idle_1 = beatsLeft_1 == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire [1:0] readys_valid_1 = {portsAOI_filtered_1_1_valid, portsAOI_filtered_1_valid}; // @[Xbar.scala:355:40]
reg [1:0] readys_mask_1; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T_3 = readys_valid_1 & ~readys_mask_1; // @[Arbiter.scala:23:23, :24:{28,30}, :68:51]
wire [1:0] readys_readys_1 = ~({readys_mask_1[1], _readys_filter_T_3[1] | readys_mask_1[0]} & ({_readys_filter_T_3[0], portsAOI_filtered_1_1_valid} | _readys_filter_T_3)); // @[package.scala:262:43]
wire winner_1_0 = readys_readys_1[0] & portsAOI_filtered_1_valid; // @[Xbar.scala:355:40]
wire winner_1_1 = readys_readys_1[1] & portsAOI_filtered_1_1_valid; // @[Xbar.scala:355:40]
wire _out_1_a_valid_T = portsAOI_filtered_1_valid | portsAOI_filtered_1_1_valid; // @[Xbar.scala:355:40]
reg state_1_0; // @[Arbiter.scala:88:26]
reg state_1_1; // @[Arbiter.scala:88:26]
wire muxState_1_0 = idle_1 ? winner_1_0 : state_1_0; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25]
wire muxState_1_1 = idle_1 ? winner_1_1 : state_1_1; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25]
assign allowed_1_0 = idle_1 ? readys_readys_1[0] : state_1_0; // @[Arbiter.scala:26:18, :61:28, :68:76, :88:26, :92:24]
assign allowed_1_1 = idle_1 ? readys_readys_1[1] : state_1_1; // @[Arbiter.scala:26:18, :61:28, :68:76, :88:26, :92:24]
wire out_1_a_valid = idle_1 ? _out_1_a_valid_T : state_1_0 & portsAOI_filtered_1_valid | state_1_1 & portsAOI_filtered_1_1_valid; // @[Mux.scala:30:73]
reg [8:0] beatsLeft_2; // @[Arbiter.scala:60:30]
wire idle_2 = beatsLeft_2 == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire [1:0] readys_valid_2 = {portsDIO_filtered_1_0_valid, portsDIO_filtered_0_valid}; // @[Xbar.scala:355:40]
reg [1:0] readys_mask_2; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T_5 = readys_valid_2 & ~readys_mask_2; // @[Arbiter.scala:23:23, :24:{28,30}, :68:51]
wire [1:0] readys_readys_2 = ~({readys_mask_2[1], _readys_filter_T_5[1] | readys_mask_2[0]} & ({_readys_filter_T_5[0], portsDIO_filtered_1_0_valid} | _readys_filter_T_5)); // @[package.scala:262:43]
wire winner_2_0 = readys_readys_2[0] & portsDIO_filtered_0_valid; // @[Xbar.scala:355:40]
wire winner_2_1 = readys_readys_2[1] & portsDIO_filtered_1_0_valid; // @[Xbar.scala:355:40]
wire _in_0_d_valid_T = portsDIO_filtered_0_valid | portsDIO_filtered_1_0_valid; // @[Xbar.scala:355:40]
reg state_2_0; // @[Arbiter.scala:88:26]
reg state_2_1; // @[Arbiter.scala:88:26]
wire muxState_2_0 = idle_2 ? winner_2_0 : state_2_0; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25]
wire muxState_2_1 = idle_2 ? winner_2_1 : state_2_1; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25]
assign allowed_2_0 = idle_2 ? readys_readys_2[0] : state_2_0; // @[Arbiter.scala:26:18, :61:28, :68:76, :88:26, :92:24]
assign allowed_2_1 = idle_2 ? readys_readys_2[1] : state_2_1; // @[Arbiter.scala:26:18, :61:28, :68:76, :88:26, :92:24]
wire in_0_d_valid = idle_2 ? _in_0_d_valid_T : state_2_0 & portsDIO_filtered_0_valid | state_2_1 & portsDIO_filtered_1_0_valid; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_2 = muxState_2_0 & auto_anon_out_0_d_bits_corrupt | muxState_2_1 & auto_anon_out_1_d_bits_corrupt; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_8 = muxState_2_0 & auto_anon_out_0_d_bits_denied | muxState_2_1 & auto_anon_out_1_d_bits_denied; // @[Mux.scala:30:73]
wire [2:0] _in_0_d_bits_T_11 = (muxState_2_0 ? out_0_d_bits_sink : 3'h0) | (muxState_2_1 ? auto_anon_out_1_d_bits_sink : 3'h0); // @[Mux.scala:30:73]
wire [4:0] _in_0_d_bits_T_14 = (muxState_2_0 ? auto_anon_out_0_d_bits_source[4:0] : 5'h0) | (muxState_2_1 ? auto_anon_out_1_d_bits_source[4:0] : 5'h0); // @[Mux.scala:30:73]
wire [3:0] _in_0_d_bits_T_17 = (muxState_2_0 ? auto_anon_out_0_d_bits_size : 4'h0) | (muxState_2_1 ? out_1_d_bits_size : 4'h0); // @[Mux.scala:30:73]
wire [1:0] _in_0_d_bits_T_20 = (muxState_2_0 ? auto_anon_out_0_d_bits_param : 2'h0) | (muxState_2_1 ? auto_anon_out_1_d_bits_param : 2'h0); // @[Mux.scala:30:73]
wire [2:0] _in_0_d_bits_T_23 = (muxState_2_0 ? auto_anon_out_0_d_bits_opcode : 3'h0) | (muxState_2_1 ? auto_anon_out_1_d_bits_opcode : 3'h0); // @[Mux.scala:30:73]
reg [8:0] beatsLeft_3; // @[Arbiter.scala:60:30]
wire idle_3 = beatsLeft_3 == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire [1:0] readys_valid_3 = {portsDIO_filtered_1_1_valid, portsDIO_filtered_1_valid}; // @[Xbar.scala:355:40]
reg [1:0] readys_mask_3; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T_7 = readys_valid_3 & ~readys_mask_3; // @[Arbiter.scala:23:23, :24:{28,30}, :68:51]
wire [1:0] readys_readys_3 = ~({readys_mask_3[1], _readys_filter_T_7[1] | readys_mask_3[0]} & ({_readys_filter_T_7[0], portsDIO_filtered_1_1_valid} | _readys_filter_T_7)); // @[package.scala:262:43]
wire winner_3_0 = readys_readys_3[0] & portsDIO_filtered_1_valid; // @[Xbar.scala:355:40]
wire winner_3_1 = readys_readys_3[1] & portsDIO_filtered_1_1_valid; // @[Xbar.scala:355:40]
wire _in_1_d_valid_T = portsDIO_filtered_1_valid | portsDIO_filtered_1_1_valid; // @[Xbar.scala:355:40] |
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is24_oe11_os53_1 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>}
node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0))
node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1))
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3))
node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4))
node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6))
node _roundMagUp_T = and(roundingMode_min, io.in.sign)
node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0))
node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1)
node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2)
node _sAdjustedExp_T = add(io.in.sExp, asSInt(UInt<12>(0h700)))
node _sAdjustedExp_T_1 = bits(_sAdjustedExp_T, 11, 0)
node sAdjustedExp = cvt(_sAdjustedExp_T_1)
node adjustedSig = shl(io.in.sig, 31)
wire common_expOut : UInt<12>
wire common_fractOut : UInt<52>
wire common_overflow : UInt<1>
wire common_totalUnderflow : UInt<1>
wire common_underflow : UInt<1>
wire common_inexact : UInt<1>
node _common_expOut_T = bits(sAdjustedExp, 11, 0)
node _common_expOut_T_1 = add(_common_expOut_T, UInt<1>(0h0))
node _common_expOut_T_2 = tail(_common_expOut_T_1, 1)
connect common_expOut, _common_expOut_T_2
node _common_fractOut_T = bits(adjustedSig, 54, 3)
node _common_fractOut_T_1 = bits(adjustedSig, 53, 2)
node _common_fractOut_T_2 = mux(UInt<1>(0h0), _common_fractOut_T, _common_fractOut_T_1)
connect common_fractOut, _common_fractOut_T_2
connect common_overflow, UInt<1>(0h0)
connect common_totalUnderflow, UInt<1>(0h0)
connect common_underflow, UInt<1>(0h0)
connect common_inexact, UInt<1>(0h0)
node isNaNOut = or(io.invalidExc, io.in.isNaN)
node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf)
node _commonCase_T = eq(isNaNOut, UInt<1>(0h0))
node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0))
node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1)
node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0))
node commonCase = and(_commonCase_T_2, _commonCase_T_3)
node overflow = and(commonCase, common_overflow)
node underflow = and(commonCase, common_underflow)
node _inexact_T = and(commonCase, common_inexact)
node inexact = or(overflow, _inexact_T)
node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp)
node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow)
node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd)
node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1)
node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0))
node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T)
node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp)
node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T)
node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign)
node _expOut_T = or(io.in.isZero, common_totalUnderflow)
node _expOut_T_1 = mux(_expOut_T, UInt<12>(0he00), UInt<1>(0h0))
node _expOut_T_2 = not(_expOut_T_1)
node _expOut_T_3 = and(common_expOut, _expOut_T_2)
node _expOut_T_4 = not(UInt<12>(0h3ce))
node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0))
node _expOut_T_6 = not(_expOut_T_5)
node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6)
node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<12>(0h400), UInt<1>(0h0))
node _expOut_T_9 = not(_expOut_T_8)
node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9)
node _expOut_T_11 = mux(notNaN_isInfOut, UInt<12>(0h200), UInt<1>(0h0))
node _expOut_T_12 = not(_expOut_T_11)
node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12)
node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<12>(0h3ce), UInt<1>(0h0))
node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14)
node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<12>(0hbff), UInt<1>(0h0))
node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16)
node _expOut_T_18 = mux(notNaN_isInfOut, UInt<12>(0hc00), UInt<1>(0h0))
node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18)
node _expOut_T_20 = mux(isNaNOut, UInt<12>(0he00), UInt<1>(0h0))
node expOut = or(_expOut_T_19, _expOut_T_20)
node _fractOut_T = or(isNaNOut, io.in.isZero)
node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow)
node _fractOut_T_2 = mux(isNaNOut, UInt<52>(0h8000000000000), UInt<1>(0h0))
node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut)
node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<52>(0hfffffffffffff), UInt<52>(0h0))
node fractOut = or(_fractOut_T_3, _fractOut_T_4)
node _io_out_T = cat(signOut, expOut)
node _io_out_T_1 = cat(_io_out_T, fractOut)
connect io.out, _io_out_T_1
node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc)
node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow)
node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact)
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RoundAnyRawFNToRecFN_ie8_is24_oe11_os53_1( // @[RoundAnyRawFNToRecFN.scala:48:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [24:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [64:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [24:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [11:0] _expOut_T_4 = 12'hC31; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53]
wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32]
wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60]
wire [11:0] _expOut_T_6 = 12'hFFF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14]
wire [11:0] _expOut_T_9 = 12'hFFF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14]
wire [11:0] _expOut_T_5 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:257:18]
wire [11:0] _expOut_T_8 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:261:18]
wire [11:0] _expOut_T_14 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:269:16]
wire [11:0] _expOut_T_16 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:273:16]
wire [51:0] _fractOut_T_4 = 52'h0; // @[RoundAnyRawFNToRecFN.scala:284:13]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_detectTininess = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53]
wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53]
wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53]
wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53]
wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53]
wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27]
wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63]
wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42]
wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire common_inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32]
wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32]
wire _inexact_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:43]
wire inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:28]
wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20]
wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60]
wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45]
wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42]
wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39]
wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45]
wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49]
wire _expOut_T = io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :253:32]
wire [64:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33]
wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66]
wire [64:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66]
wire [12:0] _sAdjustedExp_T = {{3{io_in_sExp_0[9]}}, io_in_sExp_0} + 13'h700; // @[RoundAnyRawFNToRecFN.scala:48:5, :104:25]
wire [11:0] _sAdjustedExp_T_1 = _sAdjustedExp_T[11:0]; // @[RoundAnyRawFNToRecFN.scala:104:25, :106:14]
wire [12:0] sAdjustedExp = {1'h0, _sAdjustedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:106:{14,31}]
wire [55:0] adjustedSig = {io_in_sig_0, 31'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22]
wire [11:0] _common_expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:136:55]
wire [11:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31]
wire [51:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:138:16]
wire [51:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31]
wire [11:0] _common_expOut_T = sAdjustedExp[11:0]; // @[RoundAnyRawFNToRecFN.scala:106:31, :136:38]
wire [12:0] _common_expOut_T_1 = {1'h0, _common_expOut_T}; // @[RoundAnyRawFNToRecFN.scala:136:{38,55}]
assign _common_expOut_T_2 = _common_expOut_T_1[11:0]; // @[RoundAnyRawFNToRecFN.scala:136:55]
assign common_expOut = _common_expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :136:55]
wire [51:0] _common_fractOut_T = adjustedSig[54:3]; // @[RoundAnyRawFNToRecFN.scala:114:22, :139:28]
wire [51:0] _common_fractOut_T_1 = adjustedSig[53:2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :140:28]
assign _common_fractOut_T_2 = _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:138:16, :140:28]
assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16]
wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34]
wire notNaN_isInfOut = notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:32]
wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22]
wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36]
wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}]
wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64]
wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}]
wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22]
wire [11:0] _expOut_T_1 = _expOut_T ? 12'hE00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}]
wire [11:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}]
wire [11:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14]
wire [11:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17]
wire [11:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17]
wire [11:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 9'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18]
wire [11:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}]
wire [11:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14]
wire [11:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18]
wire [11:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15]
wire [11:0] _expOut_T_18 = notNaN_isInfOut ? 12'hC00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16]
wire [11:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16]
wire [11:0] _expOut_T_20 = isNaNOut ? 12'hE00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16]
wire [11:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16]
wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22]
wire _fractOut_T_1 = _fractOut_T; // @[RoundAnyRawFNToRecFN.scala:280:{22,38}]
wire [51:0] _fractOut_T_2 = {isNaNOut, 51'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16]
wire [51:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16]
wire [51:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11]
wire [12:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23]
assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}]
assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33]
wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23]
wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:288:{23,41}]
wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:288:{41,53}]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:288:{53,66}]
assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TageBranchPredictorBank_1 :
input clock : Clock
input reset : Reset
output io : { flip f0_valid : UInt<1>, flip f0_pc : UInt<40>, flip f0_mask : UInt<4>, flip f1_ghist : UInt<64>, flip f1_lhist : UInt<1>, flip resp_in : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}[1], resp : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}, f3_meta : UInt<120>, flip f3_fire : UInt<1>, flip update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}}
connect io.resp, io.resp_in[0]
connect io.f3_meta, UInt<1>(0h0)
node s0_idx = shr(io.f0_pc, 4)
reg s1_idx : UInt, clock
connect s1_idx, s0_idx
reg s2_idx : UInt, clock
connect s2_idx, s1_idx
reg s3_idx : UInt, clock
connect s3_idx, s2_idx
reg s1_valid : UInt<1>, clock
connect s1_valid, io.f0_valid
reg s2_valid : UInt<1>, clock
connect s2_valid, s1_valid
reg s3_valid : UInt<1>, clock
connect s3_valid, s2_valid
reg s1_mask : UInt, clock
connect s1_mask, io.f0_mask
reg s2_mask : UInt, clock
connect s2_mask, s1_mask
reg s3_mask : UInt, clock
connect s3_mask, s2_mask
reg s1_pc : UInt, clock
connect s1_pc, io.f0_pc
node s0_update_idx = shr(io.update.bits.pc, 4)
reg s1_update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}, clock
connect s1_update.bits.meta, io.update.bits.meta
connect s1_update.bits.target, io.update.bits.target
connect s1_update.bits.lhist, io.update.bits.lhist
connect s1_update.bits.ghist, io.update.bits.ghist
connect s1_update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr
connect s1_update.bits.cfi_is_jal, io.update.bits.cfi_is_jal
connect s1_update.bits.cfi_is_br, io.update.bits.cfi_is_br
connect s1_update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted
connect s1_update.bits.cfi_taken, io.update.bits.cfi_taken
connect s1_update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits
connect s1_update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid
connect s1_update.bits.br_mask, io.update.bits.br_mask
connect s1_update.bits.pc, io.update.bits.pc
connect s1_update.bits.btb_mispredicts, io.update.bits.btb_mispredicts
connect s1_update.bits.is_repair_update, io.update.bits.is_repair_update
connect s1_update.bits.is_mispredict_update, io.update.bits.is_mispredict_update
connect s1_update.valid, io.update.valid
reg s1_update_idx : UInt, clock
connect s1_update_idx, s0_update_idx
reg s1_update_valid : UInt<1>, clock
connect s1_update_valid, io.update.valid
wire f3_meta : { provider : { valid : UInt<1>, bits : UInt<3>}[4], alt_differs : UInt<1>[4], provider_u : UInt<2>[4], provider_ctr : UInt<3>[4], allocate : { valid : UInt<1>, bits : UInt<3>}[4]}
node _T = cat(f3_meta.allocate[0].valid, f3_meta.allocate[0].bits)
node _T_1 = cat(f3_meta.allocate[1].valid, f3_meta.allocate[1].bits)
node _T_2 = cat(f3_meta.allocate[2].valid, f3_meta.allocate[2].bits)
node _T_3 = cat(f3_meta.allocate[3].valid, f3_meta.allocate[3].bits)
node lo = cat(_T_1, _T)
node hi = cat(_T_3, _T_2)
node _T_4 = cat(hi, lo)
node lo_1 = cat(f3_meta.provider_ctr[1], f3_meta.provider_ctr[0])
node hi_1 = cat(f3_meta.provider_ctr[3], f3_meta.provider_ctr[2])
node _T_5 = cat(hi_1, lo_1)
node lo_2 = cat(f3_meta.provider_u[1], f3_meta.provider_u[0])
node hi_2 = cat(f3_meta.provider_u[3], f3_meta.provider_u[2])
node _T_6 = cat(hi_2, lo_2)
node lo_3 = cat(f3_meta.alt_differs[1], f3_meta.alt_differs[0])
node hi_3 = cat(f3_meta.alt_differs[3], f3_meta.alt_differs[2])
node _T_7 = cat(hi_3, lo_3)
node _T_8 = cat(f3_meta.provider[0].valid, f3_meta.provider[0].bits)
node _T_9 = cat(f3_meta.provider[1].valid, f3_meta.provider[1].bits)
node _T_10 = cat(f3_meta.provider[2].valid, f3_meta.provider[2].bits)
node _T_11 = cat(f3_meta.provider[3].valid, f3_meta.provider[3].bits)
node lo_4 = cat(_T_9, _T_8)
node hi_4 = cat(_T_11, _T_10)
node _T_12 = cat(hi_4, lo_4)
node lo_5 = cat(_T_5, _T_4)
node hi_hi = cat(_T_12, _T_7)
node hi_5 = cat(hi_hi, _T_6)
node _T_13 = cat(hi_5, lo_5)
inst tt_0_1 of TageTable_6
connect tt_0_1.clock, clock
connect tt_0_1.reset, reset
reg t_io_f1_req_valid_REG : UInt<1>, clock
connect t_io_f1_req_valid_REG, io.f0_valid
connect tt_0_1.io.f1_req_valid, t_io_f1_req_valid_REG
reg t_io_f1_req_pc_REG : UInt, clock
connect t_io_f1_req_pc_REG, io.f0_pc
connect tt_0_1.io.f1_req_pc, t_io_f1_req_pc_REG
connect tt_0_1.io.f1_req_ghist, io.f1_ghist
inst tt_1_1 of TageTable_7
connect tt_1_1.clock, clock
connect tt_1_1.reset, reset
reg t_io_f1_req_valid_REG_1 : UInt<1>, clock
connect t_io_f1_req_valid_REG_1, io.f0_valid
connect tt_1_1.io.f1_req_valid, t_io_f1_req_valid_REG_1
reg t_io_f1_req_pc_REG_1 : UInt, clock
connect t_io_f1_req_pc_REG_1, io.f0_pc
connect tt_1_1.io.f1_req_pc, t_io_f1_req_pc_REG_1
connect tt_1_1.io.f1_req_ghist, io.f1_ghist
inst tt_2_1 of TageTable_8
connect tt_2_1.clock, clock
connect tt_2_1.reset, reset
reg t_io_f1_req_valid_REG_2 : UInt<1>, clock
connect t_io_f1_req_valid_REG_2, io.f0_valid
connect tt_2_1.io.f1_req_valid, t_io_f1_req_valid_REG_2
reg t_io_f1_req_pc_REG_2 : UInt, clock
connect t_io_f1_req_pc_REG_2, io.f0_pc
connect tt_2_1.io.f1_req_pc, t_io_f1_req_pc_REG_2
connect tt_2_1.io.f1_req_ghist, io.f1_ghist
inst tt_3_1 of TageTable_9
connect tt_3_1.clock, clock
connect tt_3_1.reset, reset
reg t_io_f1_req_valid_REG_3 : UInt<1>, clock
connect t_io_f1_req_valid_REG_3, io.f0_valid
connect tt_3_1.io.f1_req_valid, t_io_f1_req_valid_REG_3
reg t_io_f1_req_pc_REG_3 : UInt, clock
connect t_io_f1_req_pc_REG_3, io.f0_pc
connect tt_3_1.io.f1_req_pc, t_io_f1_req_pc_REG_3
connect tt_3_1.io.f1_req_ghist, io.f1_ghist
inst tt_4_1 of TageTable_10
connect tt_4_1.clock, clock
connect tt_4_1.reset, reset
reg t_io_f1_req_valid_REG_4 : UInt<1>, clock
connect t_io_f1_req_valid_REG_4, io.f0_valid
connect tt_4_1.io.f1_req_valid, t_io_f1_req_valid_REG_4
reg t_io_f1_req_pc_REG_4 : UInt, clock
connect t_io_f1_req_pc_REG_4, io.f0_pc
connect tt_4_1.io.f1_req_pc, t_io_f1_req_pc_REG_4
connect tt_4_1.io.f1_req_ghist, io.f1_ghist
inst tt_5_1 of TageTable_11
connect tt_5_1.clock, clock
connect tt_5_1.reset, reset
reg t_io_f1_req_valid_REG_5 : UInt<1>, clock
connect t_io_f1_req_valid_REG_5, io.f0_valid
connect tt_5_1.io.f1_req_valid, t_io_f1_req_valid_REG_5
reg t_io_f1_req_pc_REG_5 : UInt, clock
connect t_io_f1_req_pc_REG_5, io.f0_pc
connect tt_5_1.io.f1_req_pc, t_io_f1_req_pc_REG_5
connect tt_5_1.io.f1_req_ghist, io.f1_ghist
wire f3_resps : { valid : UInt<1>, bits : { ctr : UInt<3>, u : UInt<2>}}[4][6]
connect f3_resps[0], tt_0_1.io.f3_resp
connect f3_resps[1], tt_1_1.io.f3_resp
connect f3_resps[2], tt_2_1.io.f3_resp
connect f3_resps[3], tt_3_1.io.f3_resp
connect f3_resps[4], tt_4_1.io.f3_resp
connect f3_resps[5], tt_5_1.io.f3_resp
wire s1_update_meta : { provider : { valid : UInt<1>, bits : UInt<3>}[4], alt_differs : UInt<1>[4], provider_u : UInt<2>[4], provider_ctr : UInt<3>[4], allocate : { valid : UInt<1>, bits : UInt<3>}[4]}
wire _s1_update_meta_WIRE : UInt<56>
connect _s1_update_meta_WIRE, s1_update.bits.meta
node _s1_update_meta_T = bits(_s1_update_meta_WIRE, 2, 0)
connect s1_update_meta.allocate[0].bits, _s1_update_meta_T
node _s1_update_meta_T_1 = bits(_s1_update_meta_WIRE, 3, 3)
connect s1_update_meta.allocate[0].valid, _s1_update_meta_T_1
node _s1_update_meta_T_2 = bits(_s1_update_meta_WIRE, 6, 4)
connect s1_update_meta.allocate[1].bits, _s1_update_meta_T_2
node _s1_update_meta_T_3 = bits(_s1_update_meta_WIRE, 7, 7)
connect s1_update_meta.allocate[1].valid, _s1_update_meta_T_3
node _s1_update_meta_T_4 = bits(_s1_update_meta_WIRE, 10, 8)
connect s1_update_meta.allocate[2].bits, _s1_update_meta_T_4
node _s1_update_meta_T_5 = bits(_s1_update_meta_WIRE, 11, 11)
connect s1_update_meta.allocate[2].valid, _s1_update_meta_T_5
node _s1_update_meta_T_6 = bits(_s1_update_meta_WIRE, 14, 12)
connect s1_update_meta.allocate[3].bits, _s1_update_meta_T_6
node _s1_update_meta_T_7 = bits(_s1_update_meta_WIRE, 15, 15)
connect s1_update_meta.allocate[3].valid, _s1_update_meta_T_7
node _s1_update_meta_T_8 = bits(_s1_update_meta_WIRE, 18, 16)
connect s1_update_meta.provider_ctr[0], _s1_update_meta_T_8
node _s1_update_meta_T_9 = bits(_s1_update_meta_WIRE, 21, 19)
connect s1_update_meta.provider_ctr[1], _s1_update_meta_T_9
node _s1_update_meta_T_10 = bits(_s1_update_meta_WIRE, 24, 22)
connect s1_update_meta.provider_ctr[2], _s1_update_meta_T_10
node _s1_update_meta_T_11 = bits(_s1_update_meta_WIRE, 27, 25)
connect s1_update_meta.provider_ctr[3], _s1_update_meta_T_11
node _s1_update_meta_T_12 = bits(_s1_update_meta_WIRE, 29, 28)
connect s1_update_meta.provider_u[0], _s1_update_meta_T_12
node _s1_update_meta_T_13 = bits(_s1_update_meta_WIRE, 31, 30)
connect s1_update_meta.provider_u[1], _s1_update_meta_T_13
node _s1_update_meta_T_14 = bits(_s1_update_meta_WIRE, 33, 32)
connect s1_update_meta.provider_u[2], _s1_update_meta_T_14
node _s1_update_meta_T_15 = bits(_s1_update_meta_WIRE, 35, 34)
connect s1_update_meta.provider_u[3], _s1_update_meta_T_15
node _s1_update_meta_T_16 = bits(_s1_update_meta_WIRE, 36, 36)
connect s1_update_meta.alt_differs[0], _s1_update_meta_T_16
node _s1_update_meta_T_17 = bits(_s1_update_meta_WIRE, 37, 37)
connect s1_update_meta.alt_differs[1], _s1_update_meta_T_17
node _s1_update_meta_T_18 = bits(_s1_update_meta_WIRE, 38, 38)
connect s1_update_meta.alt_differs[2], _s1_update_meta_T_18
node _s1_update_meta_T_19 = bits(_s1_update_meta_WIRE, 39, 39)
connect s1_update_meta.alt_differs[3], _s1_update_meta_T_19
node _s1_update_meta_T_20 = bits(_s1_update_meta_WIRE, 42, 40)
connect s1_update_meta.provider[0].bits, _s1_update_meta_T_20
node _s1_update_meta_T_21 = bits(_s1_update_meta_WIRE, 43, 43)
connect s1_update_meta.provider[0].valid, _s1_update_meta_T_21
node _s1_update_meta_T_22 = bits(_s1_update_meta_WIRE, 46, 44)
connect s1_update_meta.provider[1].bits, _s1_update_meta_T_22
node _s1_update_meta_T_23 = bits(_s1_update_meta_WIRE, 47, 47)
connect s1_update_meta.provider[1].valid, _s1_update_meta_T_23
node _s1_update_meta_T_24 = bits(_s1_update_meta_WIRE, 50, 48)
connect s1_update_meta.provider[2].bits, _s1_update_meta_T_24
node _s1_update_meta_T_25 = bits(_s1_update_meta_WIRE, 51, 51)
connect s1_update_meta.provider[2].valid, _s1_update_meta_T_25
node _s1_update_meta_T_26 = bits(_s1_update_meta_WIRE, 54, 52)
connect s1_update_meta.provider[3].bits, _s1_update_meta_T_26
node _s1_update_meta_T_27 = bits(_s1_update_meta_WIRE, 55, 55)
connect s1_update_meta.provider[3].valid, _s1_update_meta_T_27
node _s1_update_mispredict_mask_T = dshl(UInt<1>(0h1), s1_update.bits.cfi_idx.bits)
node _s1_update_mispredict_mask_T_1 = mux(s1_update.bits.cfi_mispredicted, UInt<4>(0hf), UInt<4>(0h0))
node s1_update_mispredict_mask = and(_s1_update_mispredict_mask_T, _s1_update_mispredict_mask_T_1)
wire _s1_update_mask_WIRE : UInt<1>[4][6]
connect _s1_update_mask_WIRE[0][0], UInt<1>(0h0)
connect _s1_update_mask_WIRE[0][1], UInt<1>(0h0)
connect _s1_update_mask_WIRE[0][2], UInt<1>(0h0)
connect _s1_update_mask_WIRE[0][3], UInt<1>(0h0)
connect _s1_update_mask_WIRE[1][0], UInt<1>(0h0)
connect _s1_update_mask_WIRE[1][1], UInt<1>(0h0)
connect _s1_update_mask_WIRE[1][2], UInt<1>(0h0)
connect _s1_update_mask_WIRE[1][3], UInt<1>(0h0)
connect _s1_update_mask_WIRE[2][0], UInt<1>(0h0)
connect _s1_update_mask_WIRE[2][1], UInt<1>(0h0)
connect _s1_update_mask_WIRE[2][2], UInt<1>(0h0)
connect _s1_update_mask_WIRE[2][3], UInt<1>(0h0)
connect _s1_update_mask_WIRE[3][0], UInt<1>(0h0)
connect _s1_update_mask_WIRE[3][1], UInt<1>(0h0)
connect _s1_update_mask_WIRE[3][2], UInt<1>(0h0)
connect _s1_update_mask_WIRE[3][3], UInt<1>(0h0)
connect _s1_update_mask_WIRE[4][0], UInt<1>(0h0)
connect _s1_update_mask_WIRE[4][1], UInt<1>(0h0)
connect _s1_update_mask_WIRE[4][2], UInt<1>(0h0)
connect _s1_update_mask_WIRE[4][3], UInt<1>(0h0)
connect _s1_update_mask_WIRE[5][0], UInt<1>(0h0)
connect _s1_update_mask_WIRE[5][1], UInt<1>(0h0)
connect _s1_update_mask_WIRE[5][2], UInt<1>(0h0)
connect _s1_update_mask_WIRE[5][3], UInt<1>(0h0)
wire s1_update_mask : UInt<1>[4][6]
connect s1_update_mask, _s1_update_mask_WIRE
wire _s1_update_u_mask_WIRE : UInt<1>[4][6]
connect _s1_update_u_mask_WIRE[0][0], UInt<1>(0h0)
connect _s1_update_u_mask_WIRE[0][1], UInt<1>(0h0)
connect _s1_update_u_mask_WIRE[0][2], UInt<1>(0h0)
connect _s1_update_u_mask_WIRE[0][3], UInt<1>(0h0)
connect _s1_update_u_mask_WIRE[1][0], UInt<1>(0h0)
connect _s1_update_u_mask_WIRE[1][1], UInt<1>(0h0)
connect _s1_update_u_mask_WIRE[1][2], UInt<1>(0h0)
connect _s1_update_u_mask_WIRE[1][3], UInt<1>(0h0)
connect _s1_update_u_mask_WIRE[2][0], UInt<1>(0h0)
connect _s1_update_u_mask_WIRE[2][1], UInt<1>(0h0)
connect _s1_update_u_mask_WIRE[2][2], UInt<1>(0h0)
connect _s1_update_u_mask_WIRE[2][3], UInt<1>(0h0)
connect _s1_update_u_mask_WIRE[3][0], UInt<1>(0h0)
connect _s1_update_u_mask_WIRE[3][1], UInt<1>(0h0)
connect _s1_update_u_mask_WIRE[3][2], UInt<1>(0h0)
connect _s1_update_u_mask_WIRE[3][3], UInt<1>(0h0)
connect _s1_update_u_mask_WIRE[4][0], UInt<1>(0h0)
connect _s1_update_u_mask_WIRE[4][1], UInt<1>(0h0)
connect _s1_update_u_mask_WIRE[4][2], UInt<1>(0h0)
connect _s1_update_u_mask_WIRE[4][3], UInt<1>(0h0)
connect _s1_update_u_mask_WIRE[5][0], UInt<1>(0h0)
connect _s1_update_u_mask_WIRE[5][1], UInt<1>(0h0)
connect _s1_update_u_mask_WIRE[5][2], UInt<1>(0h0)
connect _s1_update_u_mask_WIRE[5][3], UInt<1>(0h0)
wire s1_update_u_mask : UInt<1>[4][6]
connect s1_update_u_mask, _s1_update_u_mask_WIRE
wire s1_update_taken : UInt<1>[4][6]
wire s1_update_old_ctr : UInt<3>[4][6]
wire s1_update_alloc : UInt<1>[4][6]
wire s1_update_u : UInt<2>[4][6]
invalidate s1_update_taken[0][0]
invalidate s1_update_taken[0][1]
invalidate s1_update_taken[0][2]
invalidate s1_update_taken[0][3]
invalidate s1_update_taken[1][0]
invalidate s1_update_taken[1][1]
invalidate s1_update_taken[1][2]
invalidate s1_update_taken[1][3]
invalidate s1_update_taken[2][0]
invalidate s1_update_taken[2][1]
invalidate s1_update_taken[2][2]
invalidate s1_update_taken[2][3]
invalidate s1_update_taken[3][0]
invalidate s1_update_taken[3][1]
invalidate s1_update_taken[3][2]
invalidate s1_update_taken[3][3]
invalidate s1_update_taken[4][0]
invalidate s1_update_taken[4][1]
invalidate s1_update_taken[4][2]
invalidate s1_update_taken[4][3]
invalidate s1_update_taken[5][0]
invalidate s1_update_taken[5][1]
invalidate s1_update_taken[5][2]
invalidate s1_update_taken[5][3]
invalidate s1_update_old_ctr[0][0]
invalidate s1_update_old_ctr[0][1]
invalidate s1_update_old_ctr[0][2]
invalidate s1_update_old_ctr[0][3]
invalidate s1_update_old_ctr[1][0]
invalidate s1_update_old_ctr[1][1]
invalidate s1_update_old_ctr[1][2]
invalidate s1_update_old_ctr[1][3]
invalidate s1_update_old_ctr[2][0]
invalidate s1_update_old_ctr[2][1]
invalidate s1_update_old_ctr[2][2]
invalidate s1_update_old_ctr[2][3]
invalidate s1_update_old_ctr[3][0]
invalidate s1_update_old_ctr[3][1]
invalidate s1_update_old_ctr[3][2]
invalidate s1_update_old_ctr[3][3]
invalidate s1_update_old_ctr[4][0]
invalidate s1_update_old_ctr[4][1]
invalidate s1_update_old_ctr[4][2]
invalidate s1_update_old_ctr[4][3]
invalidate s1_update_old_ctr[5][0]
invalidate s1_update_old_ctr[5][1]
invalidate s1_update_old_ctr[5][2]
invalidate s1_update_old_ctr[5][3]
invalidate s1_update_alloc[0][0]
invalidate s1_update_alloc[0][1]
invalidate s1_update_alloc[0][2]
invalidate s1_update_alloc[0][3]
invalidate s1_update_alloc[1][0]
invalidate s1_update_alloc[1][1]
invalidate s1_update_alloc[1][2]
invalidate s1_update_alloc[1][3]
invalidate s1_update_alloc[2][0]
invalidate s1_update_alloc[2][1]
invalidate s1_update_alloc[2][2]
invalidate s1_update_alloc[2][3]
invalidate s1_update_alloc[3][0]
invalidate s1_update_alloc[3][1]
invalidate s1_update_alloc[3][2]
invalidate s1_update_alloc[3][3]
invalidate s1_update_alloc[4][0]
invalidate s1_update_alloc[4][1]
invalidate s1_update_alloc[4][2]
invalidate s1_update_alloc[4][3]
invalidate s1_update_alloc[5][0]
invalidate s1_update_alloc[5][1]
invalidate s1_update_alloc[5][2]
invalidate s1_update_alloc[5][3]
invalidate s1_update_u[0][0]
invalidate s1_update_u[0][1]
invalidate s1_update_u[0][2]
invalidate s1_update_u[0][3]
invalidate s1_update_u[1][0]
invalidate s1_update_u[1][1]
invalidate s1_update_u[1][2]
invalidate s1_update_u[1][3]
invalidate s1_update_u[2][0]
invalidate s1_update_u[2][1]
invalidate s1_update_u[2][2]
invalidate s1_update_u[2][3]
invalidate s1_update_u[3][0]
invalidate s1_update_u[3][1]
invalidate s1_update_u[3][2]
invalidate s1_update_u[3][3]
invalidate s1_update_u[4][0]
invalidate s1_update_u[4][1]
invalidate s1_update_u[4][2]
invalidate s1_update_u[4][3]
invalidate s1_update_u[5][0]
invalidate s1_update_u[5][1]
invalidate s1_update_u[5][2]
invalidate s1_update_u[5][3]
wire final_altpred : UInt<1>
connect final_altpred, io.resp_in[0].f3[0].taken
connect io.resp.f3[0].taken, io.resp_in[0].f3[0].taken
when f3_resps[0][0].valid :
node _io_resp_f3_0_taken_T = eq(f3_resps[0][0].bits.ctr, UInt<2>(0h3))
node _io_resp_f3_0_taken_T_1 = eq(f3_resps[0][0].bits.ctr, UInt<3>(0h4))
node _io_resp_f3_0_taken_T_2 = or(_io_resp_f3_0_taken_T, _io_resp_f3_0_taken_T_1)
node _io_resp_f3_0_taken_T_3 = bits(f3_resps[0][0].bits.ctr, 2, 2)
node _io_resp_f3_0_taken_T_4 = mux(_io_resp_f3_0_taken_T_2, io.resp_in[0].f3[0].taken, _io_resp_f3_0_taken_T_3)
connect io.resp.f3[0].taken, _io_resp_f3_0_taken_T_4
connect final_altpred, io.resp_in[0].f3[0].taken
node _T_14 = or(UInt<1>(0h0), f3_resps[0][0].valid)
node _T_15 = mux(f3_resps[0][0].valid, UInt<1>(0h0), UInt<1>(0h0))
node _T_16 = bits(f3_resps[0][0].bits.ctr, 2, 2)
node _T_17 = mux(f3_resps[0][0].valid, _T_16, io.resp_in[0].f3[0].taken)
when f3_resps[1][0].valid :
node _io_resp_f3_0_taken_T_5 = eq(f3_resps[1][0].bits.ctr, UInt<2>(0h3))
node _io_resp_f3_0_taken_T_6 = eq(f3_resps[1][0].bits.ctr, UInt<3>(0h4))
node _io_resp_f3_0_taken_T_7 = or(_io_resp_f3_0_taken_T_5, _io_resp_f3_0_taken_T_6)
node _io_resp_f3_0_taken_T_8 = bits(f3_resps[1][0].bits.ctr, 2, 2)
node _io_resp_f3_0_taken_T_9 = mux(_io_resp_f3_0_taken_T_7, _T_17, _io_resp_f3_0_taken_T_8)
connect io.resp.f3[0].taken, _io_resp_f3_0_taken_T_9
connect final_altpred, _T_17
node _T_18 = or(_T_14, f3_resps[1][0].valid)
node _T_19 = mux(f3_resps[1][0].valid, UInt<1>(0h1), _T_15)
node _T_20 = bits(f3_resps[1][0].bits.ctr, 2, 2)
node _T_21 = mux(f3_resps[1][0].valid, _T_20, _T_17)
when f3_resps[2][0].valid :
node _io_resp_f3_0_taken_T_10 = eq(f3_resps[2][0].bits.ctr, UInt<2>(0h3))
node _io_resp_f3_0_taken_T_11 = eq(f3_resps[2][0].bits.ctr, UInt<3>(0h4))
node _io_resp_f3_0_taken_T_12 = or(_io_resp_f3_0_taken_T_10, _io_resp_f3_0_taken_T_11)
node _io_resp_f3_0_taken_T_13 = bits(f3_resps[2][0].bits.ctr, 2, 2)
node _io_resp_f3_0_taken_T_14 = mux(_io_resp_f3_0_taken_T_12, _T_21, _io_resp_f3_0_taken_T_13)
connect io.resp.f3[0].taken, _io_resp_f3_0_taken_T_14
connect final_altpred, _T_21
node _T_22 = or(_T_18, f3_resps[2][0].valid)
node _T_23 = mux(f3_resps[2][0].valid, UInt<2>(0h2), _T_19)
node _T_24 = bits(f3_resps[2][0].bits.ctr, 2, 2)
node _T_25 = mux(f3_resps[2][0].valid, _T_24, _T_21)
when f3_resps[3][0].valid :
node _io_resp_f3_0_taken_T_15 = eq(f3_resps[3][0].bits.ctr, UInt<2>(0h3))
node _io_resp_f3_0_taken_T_16 = eq(f3_resps[3][0].bits.ctr, UInt<3>(0h4))
node _io_resp_f3_0_taken_T_17 = or(_io_resp_f3_0_taken_T_15, _io_resp_f3_0_taken_T_16)
node _io_resp_f3_0_taken_T_18 = bits(f3_resps[3][0].bits.ctr, 2, 2)
node _io_resp_f3_0_taken_T_19 = mux(_io_resp_f3_0_taken_T_17, _T_25, _io_resp_f3_0_taken_T_18)
connect io.resp.f3[0].taken, _io_resp_f3_0_taken_T_19
connect final_altpred, _T_25
node _T_26 = or(_T_22, f3_resps[3][0].valid)
node _T_27 = mux(f3_resps[3][0].valid, UInt<2>(0h3), _T_23)
node _T_28 = bits(f3_resps[3][0].bits.ctr, 2, 2)
node _T_29 = mux(f3_resps[3][0].valid, _T_28, _T_25)
when f3_resps[4][0].valid :
node _io_resp_f3_0_taken_T_20 = eq(f3_resps[4][0].bits.ctr, UInt<2>(0h3))
node _io_resp_f3_0_taken_T_21 = eq(f3_resps[4][0].bits.ctr, UInt<3>(0h4))
node _io_resp_f3_0_taken_T_22 = or(_io_resp_f3_0_taken_T_20, _io_resp_f3_0_taken_T_21)
node _io_resp_f3_0_taken_T_23 = bits(f3_resps[4][0].bits.ctr, 2, 2)
node _io_resp_f3_0_taken_T_24 = mux(_io_resp_f3_0_taken_T_22, _T_29, _io_resp_f3_0_taken_T_23)
connect io.resp.f3[0].taken, _io_resp_f3_0_taken_T_24
connect final_altpred, _T_29
node _T_30 = or(_T_26, f3_resps[4][0].valid)
node _T_31 = mux(f3_resps[4][0].valid, UInt<3>(0h4), _T_27)
node _T_32 = bits(f3_resps[4][0].bits.ctr, 2, 2)
node _T_33 = mux(f3_resps[4][0].valid, _T_32, _T_29)
when f3_resps[5][0].valid :
node _io_resp_f3_0_taken_T_25 = eq(f3_resps[5][0].bits.ctr, UInt<2>(0h3))
node _io_resp_f3_0_taken_T_26 = eq(f3_resps[5][0].bits.ctr, UInt<3>(0h4))
node _io_resp_f3_0_taken_T_27 = or(_io_resp_f3_0_taken_T_25, _io_resp_f3_0_taken_T_26)
node _io_resp_f3_0_taken_T_28 = bits(f3_resps[5][0].bits.ctr, 2, 2)
node _io_resp_f3_0_taken_T_29 = mux(_io_resp_f3_0_taken_T_27, _T_33, _io_resp_f3_0_taken_T_28)
connect io.resp.f3[0].taken, _io_resp_f3_0_taken_T_29
connect final_altpred, _T_33
node _T_34 = or(_T_30, f3_resps[5][0].valid)
node _T_35 = mux(f3_resps[5][0].valid, UInt<3>(0h5), _T_31)
node _T_36 = bits(f3_resps[5][0].bits.ctr, 2, 2)
node _T_37 = mux(f3_resps[5][0].valid, _T_36, _T_33)
connect f3_meta.provider[0].valid, _T_34
connect f3_meta.provider[0].bits, _T_35
node _f3_meta_alt_differs_0_T = neq(final_altpred, io.resp.f3[0].taken)
connect f3_meta.alt_differs[0], _f3_meta_alt_differs_0_T
connect f3_meta.provider_u[0], f3_resps[_T_35][0].bits.u
connect f3_meta.provider_ctr[0], f3_resps[_T_35][0].bits.ctr
node _allocatable_slots_T = eq(f3_resps[0][0].valid, UInt<1>(0h0))
node _allocatable_slots_T_1 = eq(f3_resps[0][0].bits.u, UInt<1>(0h0))
node _allocatable_slots_T_2 = and(_allocatable_slots_T, _allocatable_slots_T_1)
node _allocatable_slots_T_3 = eq(f3_resps[1][0].valid, UInt<1>(0h0))
node _allocatable_slots_T_4 = eq(f3_resps[1][0].bits.u, UInt<1>(0h0))
node _allocatable_slots_T_5 = and(_allocatable_slots_T_3, _allocatable_slots_T_4)
node _allocatable_slots_T_6 = eq(f3_resps[2][0].valid, UInt<1>(0h0))
node _allocatable_slots_T_7 = eq(f3_resps[2][0].bits.u, UInt<1>(0h0))
node _allocatable_slots_T_8 = and(_allocatable_slots_T_6, _allocatable_slots_T_7)
node _allocatable_slots_T_9 = eq(f3_resps[3][0].valid, UInt<1>(0h0))
node _allocatable_slots_T_10 = eq(f3_resps[3][0].bits.u, UInt<1>(0h0))
node _allocatable_slots_T_11 = and(_allocatable_slots_T_9, _allocatable_slots_T_10)
node _allocatable_slots_T_12 = eq(f3_resps[4][0].valid, UInt<1>(0h0))
node _allocatable_slots_T_13 = eq(f3_resps[4][0].bits.u, UInt<1>(0h0))
node _allocatable_slots_T_14 = and(_allocatable_slots_T_12, _allocatable_slots_T_13)
node _allocatable_slots_T_15 = eq(f3_resps[5][0].valid, UInt<1>(0h0))
node _allocatable_slots_T_16 = eq(f3_resps[5][0].bits.u, UInt<1>(0h0))
node _allocatable_slots_T_17 = and(_allocatable_slots_T_15, _allocatable_slots_T_16)
wire _allocatable_slots_WIRE : UInt<1>[6]
connect _allocatable_slots_WIRE[0], _allocatable_slots_T_2
connect _allocatable_slots_WIRE[1], _allocatable_slots_T_5
connect _allocatable_slots_WIRE[2], _allocatable_slots_T_8
connect _allocatable_slots_WIRE[3], _allocatable_slots_T_11
connect _allocatable_slots_WIRE[4], _allocatable_slots_T_14
connect _allocatable_slots_WIRE[5], _allocatable_slots_T_17
node allocatable_slots_lo_hi = cat(_allocatable_slots_WIRE[2], _allocatable_slots_WIRE[1])
node allocatable_slots_lo = cat(allocatable_slots_lo_hi, _allocatable_slots_WIRE[0])
node allocatable_slots_hi_hi = cat(_allocatable_slots_WIRE[5], _allocatable_slots_WIRE[4])
node allocatable_slots_hi = cat(allocatable_slots_hi_hi, _allocatable_slots_WIRE[3])
node _allocatable_slots_T_18 = cat(allocatable_slots_hi, allocatable_slots_lo)
node _allocatable_slots_T_19 = dshl(UInt<1>(0h1), _T_35)
node _allocatable_slots_T_20 = dshr(_allocatable_slots_T_19, UInt<1>(0h0))
node _allocatable_slots_T_21 = dshr(_allocatable_slots_T_19, UInt<1>(0h1))
node _allocatable_slots_T_22 = dshr(_allocatable_slots_T_19, UInt<2>(0h2))
node _allocatable_slots_T_23 = dshr(_allocatable_slots_T_19, UInt<2>(0h3))
node _allocatable_slots_T_24 = dshr(_allocatable_slots_T_19, UInt<3>(0h4))
node _allocatable_slots_T_25 = dshr(_allocatable_slots_T_19, UInt<3>(0h5))
node _allocatable_slots_T_26 = dshr(_allocatable_slots_T_19, UInt<3>(0h6))
node _allocatable_slots_T_27 = dshr(_allocatable_slots_T_19, UInt<3>(0h7))
node _allocatable_slots_T_28 = or(_allocatable_slots_T_20, _allocatable_slots_T_21)
node _allocatable_slots_T_29 = or(_allocatable_slots_T_28, _allocatable_slots_T_22)
node _allocatable_slots_T_30 = or(_allocatable_slots_T_29, _allocatable_slots_T_23)
node _allocatable_slots_T_31 = or(_allocatable_slots_T_30, _allocatable_slots_T_24)
node _allocatable_slots_T_32 = or(_allocatable_slots_T_31, _allocatable_slots_T_25)
node _allocatable_slots_T_33 = or(_allocatable_slots_T_32, _allocatable_slots_T_26)
node _allocatable_slots_T_34 = or(_allocatable_slots_T_33, _allocatable_slots_T_27)
node _allocatable_slots_T_35 = mux(_T_34, UInt<6>(0h3f), UInt<6>(0h0))
node _allocatable_slots_T_36 = and(_allocatable_slots_T_34, _allocatable_slots_T_35)
node _allocatable_slots_T_37 = not(_allocatable_slots_T_36)
node allocatable_slots = and(_allocatable_slots_T_18, _allocatable_slots_T_37)
inst alloc_lfsr_prng of MaxPeriodFibonacciLFSR_11
connect alloc_lfsr_prng.clock, clock
connect alloc_lfsr_prng.reset, reset
connect alloc_lfsr_prng.io.seed.valid, UInt<1>(0h0)
invalidate alloc_lfsr_prng.io.seed.bits[0]
invalidate alloc_lfsr_prng.io.seed.bits[1]
invalidate alloc_lfsr_prng.io.seed.bits[2]
invalidate alloc_lfsr_prng.io.seed.bits[3]
invalidate alloc_lfsr_prng.io.seed.bits[4]
invalidate alloc_lfsr_prng.io.seed.bits[5]
connect alloc_lfsr_prng.io.increment, UInt<1>(0h1)
node alloc_lfsr_lo_hi = cat(alloc_lfsr_prng.io.out[2], alloc_lfsr_prng.io.out[1])
node alloc_lfsr_lo = cat(alloc_lfsr_lo_hi, alloc_lfsr_prng.io.out[0])
node alloc_lfsr_hi_hi = cat(alloc_lfsr_prng.io.out[5], alloc_lfsr_prng.io.out[4])
node alloc_lfsr_hi = cat(alloc_lfsr_hi_hi, alloc_lfsr_prng.io.out[3])
node alloc_lfsr = cat(alloc_lfsr_hi, alloc_lfsr_lo)
node _first_entry_T = bits(allocatable_slots, 0, 0)
node _first_entry_T_1 = bits(allocatable_slots, 1, 1)
node _first_entry_T_2 = bits(allocatable_slots, 2, 2)
node _first_entry_T_3 = bits(allocatable_slots, 3, 3)
node _first_entry_T_4 = bits(allocatable_slots, 4, 4)
node _first_entry_T_5 = bits(allocatable_slots, 5, 5)
node _first_entry_T_6 = bits(allocatable_slots, 6, 6)
node _first_entry_T_7 = bits(allocatable_slots, 7, 7)
node _first_entry_T_8 = mux(_first_entry_T_6, UInt<3>(0h6), UInt<3>(0h7))
node _first_entry_T_9 = mux(_first_entry_T_5, UInt<3>(0h5), _first_entry_T_8)
node _first_entry_T_10 = mux(_first_entry_T_4, UInt<3>(0h4), _first_entry_T_9)
node _first_entry_T_11 = mux(_first_entry_T_3, UInt<2>(0h3), _first_entry_T_10)
node _first_entry_T_12 = mux(_first_entry_T_2, UInt<2>(0h2), _first_entry_T_11)
node _first_entry_T_13 = mux(_first_entry_T_1, UInt<1>(0h1), _first_entry_T_12)
node first_entry = mux(_first_entry_T, UInt<1>(0h0), _first_entry_T_13)
node _masked_entry_T = and(allocatable_slots, alloc_lfsr)
node _masked_entry_T_1 = bits(_masked_entry_T, 0, 0)
node _masked_entry_T_2 = bits(_masked_entry_T, 1, 1)
node _masked_entry_T_3 = bits(_masked_entry_T, 2, 2)
node _masked_entry_T_4 = bits(_masked_entry_T, 3, 3)
node _masked_entry_T_5 = bits(_masked_entry_T, 4, 4)
node _masked_entry_T_6 = bits(_masked_entry_T, 5, 5)
node _masked_entry_T_7 = bits(_masked_entry_T, 6, 6)
node _masked_entry_T_8 = bits(_masked_entry_T, 7, 7)
node _masked_entry_T_9 = mux(_masked_entry_T_7, UInt<3>(0h6), UInt<3>(0h7))
node _masked_entry_T_10 = mux(_masked_entry_T_6, UInt<3>(0h5), _masked_entry_T_9)
node _masked_entry_T_11 = mux(_masked_entry_T_5, UInt<3>(0h4), _masked_entry_T_10)
node _masked_entry_T_12 = mux(_masked_entry_T_4, UInt<2>(0h3), _masked_entry_T_11)
node _masked_entry_T_13 = mux(_masked_entry_T_3, UInt<2>(0h2), _masked_entry_T_12)
node _masked_entry_T_14 = mux(_masked_entry_T_2, UInt<1>(0h1), _masked_entry_T_13)
node masked_entry = mux(_masked_entry_T_1, UInt<1>(0h0), _masked_entry_T_14)
node _alloc_entry_T = dshr(allocatable_slots, masked_entry)
node _alloc_entry_T_1 = bits(_alloc_entry_T, 0, 0)
node alloc_entry = mux(_alloc_entry_T_1, masked_entry, first_entry)
node _f3_meta_allocate_0_valid_T = neq(allocatable_slots, UInt<1>(0h0))
connect f3_meta.allocate[0].valid, _f3_meta_allocate_0_valid_T
connect f3_meta.allocate[0].bits, alloc_entry
node _update_was_taken_T = eq(s1_update.bits.cfi_idx.bits, UInt<1>(0h0))
node _update_was_taken_T_1 = and(s1_update.bits.cfi_idx.valid, _update_was_taken_T)
node update_was_taken = and(_update_was_taken_T_1, s1_update.bits.cfi_taken)
node _T_38 = bits(s1_update.bits.br_mask, 0, 0)
node _T_39 = and(_T_38, s1_update.valid)
node _T_40 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update)
node _T_41 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0))
node _T_42 = or(_T_40, _T_41)
node _T_43 = eq(_T_42, UInt<1>(0h0))
node _T_44 = and(_T_39, _T_43)
when _T_44 :
when s1_update_meta.provider[0].valid :
connect s1_update_mask[s1_update_meta.provider[0].bits][0], UInt<1>(0h1)
connect s1_update_u_mask[s1_update_meta.provider[0].bits][0], UInt<1>(0h1)
node _new_u_T = bits(s1_update_mispredict_mask, 0, 0)
node _new_u_T_1 = eq(s1_update_meta.alt_differs[0], UInt<1>(0h0))
node _new_u_T_2 = eq(s1_update_meta.provider_u[0], UInt<1>(0h0))
node _new_u_T_3 = sub(s1_update_meta.provider_u[0], UInt<1>(0h1))
node _new_u_T_4 = tail(_new_u_T_3, 1)
node _new_u_T_5 = mux(_new_u_T_2, UInt<1>(0h0), _new_u_T_4)
node _new_u_T_6 = eq(s1_update_meta.provider_u[0], UInt<2>(0h3))
node _new_u_T_7 = add(s1_update_meta.provider_u[0], UInt<1>(0h1))
node _new_u_T_8 = tail(_new_u_T_7, 1)
node _new_u_T_9 = mux(_new_u_T_6, UInt<2>(0h3), _new_u_T_8)
node _new_u_T_10 = mux(_new_u_T, _new_u_T_5, _new_u_T_9)
node new_u = mux(_new_u_T_1, s1_update_meta.provider_u[0], _new_u_T_10)
connect s1_update_u[s1_update_meta.provider[0].bits][0], new_u
connect s1_update_taken[s1_update_meta.provider[0].bits][0], update_was_taken
connect s1_update_old_ctr[s1_update_meta.provider[0].bits][0], s1_update_meta.provider_ctr[0]
connect s1_update_alloc[s1_update_meta.provider[0].bits][0], UInt<1>(0h0)
wire final_altpred_1 : UInt<1>
connect final_altpred_1, io.resp_in[0].f3[1].taken
connect io.resp.f3[1].taken, io.resp_in[0].f3[1].taken
when f3_resps[0][1].valid :
node _io_resp_f3_1_taken_T = eq(f3_resps[0][1].bits.ctr, UInt<2>(0h3))
node _io_resp_f3_1_taken_T_1 = eq(f3_resps[0][1].bits.ctr, UInt<3>(0h4))
node _io_resp_f3_1_taken_T_2 = or(_io_resp_f3_1_taken_T, _io_resp_f3_1_taken_T_1)
node _io_resp_f3_1_taken_T_3 = bits(f3_resps[0][1].bits.ctr, 2, 2)
node _io_resp_f3_1_taken_T_4 = mux(_io_resp_f3_1_taken_T_2, io.resp_in[0].f3[1].taken, _io_resp_f3_1_taken_T_3)
connect io.resp.f3[1].taken, _io_resp_f3_1_taken_T_4
connect final_altpred_1, io.resp_in[0].f3[1].taken
node _T_45 = or(UInt<1>(0h0), f3_resps[0][1].valid)
node _T_46 = mux(f3_resps[0][1].valid, UInt<1>(0h0), UInt<1>(0h0))
node _T_47 = bits(f3_resps[0][1].bits.ctr, 2, 2)
node _T_48 = mux(f3_resps[0][1].valid, _T_47, io.resp_in[0].f3[1].taken)
when f3_resps[1][1].valid :
node _io_resp_f3_1_taken_T_5 = eq(f3_resps[1][1].bits.ctr, UInt<2>(0h3))
node _io_resp_f3_1_taken_T_6 = eq(f3_resps[1][1].bits.ctr, UInt<3>(0h4))
node _io_resp_f3_1_taken_T_7 = or(_io_resp_f3_1_taken_T_5, _io_resp_f3_1_taken_T_6)
node _io_resp_f3_1_taken_T_8 = bits(f3_resps[1][1].bits.ctr, 2, 2)
node _io_resp_f3_1_taken_T_9 = mux(_io_resp_f3_1_taken_T_7, _T_48, _io_resp_f3_1_taken_T_8)
connect io.resp.f3[1].taken, _io_resp_f3_1_taken_T_9
connect final_altpred_1, _T_48
node _T_49 = or(_T_45, f3_resps[1][1].valid)
node _T_50 = mux(f3_resps[1][1].valid, UInt<1>(0h1), _T_46)
node _T_51 = bits(f3_resps[1][1].bits.ctr, 2, 2)
node _T_52 = mux(f3_resps[1][1].valid, _T_51, _T_48)
when f3_resps[2][1].valid :
node _io_resp_f3_1_taken_T_10 = eq(f3_resps[2][1].bits.ctr, UInt<2>(0h3))
node _io_resp_f3_1_taken_T_11 = eq(f3_resps[2][1].bits.ctr, UInt<3>(0h4))
node _io_resp_f3_1_taken_T_12 = or(_io_resp_f3_1_taken_T_10, _io_resp_f3_1_taken_T_11)
node _io_resp_f3_1_taken_T_13 = bits(f3_resps[2][1].bits.ctr, 2, 2)
node _io_resp_f3_1_taken_T_14 = mux(_io_resp_f3_1_taken_T_12, _T_52, _io_resp_f3_1_taken_T_13)
connect io.resp.f3[1].taken, _io_resp_f3_1_taken_T_14
connect final_altpred_1, _T_52
node _T_53 = or(_T_49, f3_resps[2][1].valid)
node _T_54 = mux(f3_resps[2][1].valid, UInt<2>(0h2), _T_50)
node _T_55 = bits(f3_resps[2][1].bits.ctr, 2, 2)
node _T_56 = mux(f3_resps[2][1].valid, _T_55, _T_52)
when f3_resps[3][1].valid :
node _io_resp_f3_1_taken_T_15 = eq(f3_resps[3][1].bits.ctr, UInt<2>(0h3))
node _io_resp_f3_1_taken_T_16 = eq(f3_resps[3][1].bits.ctr, UInt<3>(0h4))
node _io_resp_f3_1_taken_T_17 = or(_io_resp_f3_1_taken_T_15, _io_resp_f3_1_taken_T_16)
node _io_resp_f3_1_taken_T_18 = bits(f3_resps[3][1].bits.ctr, 2, 2)
node _io_resp_f3_1_taken_T_19 = mux(_io_resp_f3_1_taken_T_17, _T_56, _io_resp_f3_1_taken_T_18)
connect io.resp.f3[1].taken, _io_resp_f3_1_taken_T_19
connect final_altpred_1, _T_56
node _T_57 = or(_T_53, f3_resps[3][1].valid)
node _T_58 = mux(f3_resps[3][1].valid, UInt<2>(0h3), _T_54)
node _T_59 = bits(f3_resps[3][1].bits.ctr, 2, 2)
node _T_60 = mux(f3_resps[3][1].valid, _T_59, _T_56)
when f3_resps[4][1].valid :
node _io_resp_f3_1_taken_T_20 = eq(f3_resps[4][1].bits.ctr, UInt<2>(0h3))
node _io_resp_f3_1_taken_T_21 = eq(f3_resps[4][1].bits.ctr, UInt<3>(0h4))
node _io_resp_f3_1_taken_T_22 = or(_io_resp_f3_1_taken_T_20, _io_resp_f3_1_taken_T_21)
node _io_resp_f3_1_taken_T_23 = bits(f3_resps[4][1].bits.ctr, 2, 2)
node _io_resp_f3_1_taken_T_24 = mux(_io_resp_f3_1_taken_T_22, _T_60, _io_resp_f3_1_taken_T_23)
connect io.resp.f3[1].taken, _io_resp_f3_1_taken_T_24
connect final_altpred_1, _T_60
node _T_61 = or(_T_57, f3_resps[4][1].valid)
node _T_62 = mux(f3_resps[4][1].valid, UInt<3>(0h4), _T_58)
node _T_63 = bits(f3_resps[4][1].bits.ctr, 2, 2)
node _T_64 = mux(f3_resps[4][1].valid, _T_63, _T_60)
when f3_resps[5][1].valid :
node _io_resp_f3_1_taken_T_25 = eq(f3_resps[5][1].bits.ctr, UInt<2>(0h3))
node _io_resp_f3_1_taken_T_26 = eq(f3_resps[5][1].bits.ctr, UInt<3>(0h4))
node _io_resp_f3_1_taken_T_27 = or(_io_resp_f3_1_taken_T_25, _io_resp_f3_1_taken_T_26)
node _io_resp_f3_1_taken_T_28 = bits(f3_resps[5][1].bits.ctr, 2, 2)
node _io_resp_f3_1_taken_T_29 = mux(_io_resp_f3_1_taken_T_27, _T_64, _io_resp_f3_1_taken_T_28)
connect io.resp.f3[1].taken, _io_resp_f3_1_taken_T_29
connect final_altpred_1, _T_64
node _T_65 = or(_T_61, f3_resps[5][1].valid)
node _T_66 = mux(f3_resps[5][1].valid, UInt<3>(0h5), _T_62)
node _T_67 = bits(f3_resps[5][1].bits.ctr, 2, 2)
node _T_68 = mux(f3_resps[5][1].valid, _T_67, _T_64)
connect f3_meta.provider[1].valid, _T_65
connect f3_meta.provider[1].bits, _T_66
node _f3_meta_alt_differs_1_T = neq(final_altpred_1, io.resp.f3[1].taken)
connect f3_meta.alt_differs[1], _f3_meta_alt_differs_1_T
connect f3_meta.provider_u[1], f3_resps[_T_66][1].bits.u
connect f3_meta.provider_ctr[1], f3_resps[_T_66][1].bits.ctr
node _allocatable_slots_T_38 = eq(f3_resps[0][1].valid, UInt<1>(0h0))
node _allocatable_slots_T_39 = eq(f3_resps[0][1].bits.u, UInt<1>(0h0))
node _allocatable_slots_T_40 = and(_allocatable_slots_T_38, _allocatable_slots_T_39)
node _allocatable_slots_T_41 = eq(f3_resps[1][1].valid, UInt<1>(0h0))
node _allocatable_slots_T_42 = eq(f3_resps[1][1].bits.u, UInt<1>(0h0))
node _allocatable_slots_T_43 = and(_allocatable_slots_T_41, _allocatable_slots_T_42)
node _allocatable_slots_T_44 = eq(f3_resps[2][1].valid, UInt<1>(0h0))
node _allocatable_slots_T_45 = eq(f3_resps[2][1].bits.u, UInt<1>(0h0))
node _allocatable_slots_T_46 = and(_allocatable_slots_T_44, _allocatable_slots_T_45)
node _allocatable_slots_T_47 = eq(f3_resps[3][1].valid, UInt<1>(0h0))
node _allocatable_slots_T_48 = eq(f3_resps[3][1].bits.u, UInt<1>(0h0))
node _allocatable_slots_T_49 = and(_allocatable_slots_T_47, _allocatable_slots_T_48)
node _allocatable_slots_T_50 = eq(f3_resps[4][1].valid, UInt<1>(0h0))
node _allocatable_slots_T_51 = eq(f3_resps[4][1].bits.u, UInt<1>(0h0))
node _allocatable_slots_T_52 = and(_allocatable_slots_T_50, _allocatable_slots_T_51)
node _allocatable_slots_T_53 = eq(f3_resps[5][1].valid, UInt<1>(0h0))
node _allocatable_slots_T_54 = eq(f3_resps[5][1].bits.u, UInt<1>(0h0))
node _allocatable_slots_T_55 = and(_allocatable_slots_T_53, _allocatable_slots_T_54)
wire _allocatable_slots_WIRE_1 : UInt<1>[6]
connect _allocatable_slots_WIRE_1[0], _allocatable_slots_T_40
connect _allocatable_slots_WIRE_1[1], _allocatable_slots_T_43
connect _allocatable_slots_WIRE_1[2], _allocatable_slots_T_46
connect _allocatable_slots_WIRE_1[3], _allocatable_slots_T_49
connect _allocatable_slots_WIRE_1[4], _allocatable_slots_T_52
connect _allocatable_slots_WIRE_1[5], _allocatable_slots_T_55
node allocatable_slots_lo_hi_1 = cat(_allocatable_slots_WIRE_1[2], _allocatable_slots_WIRE_1[1])
node allocatable_slots_lo_1 = cat(allocatable_slots_lo_hi_1, _allocatable_slots_WIRE_1[0])
node allocatable_slots_hi_hi_1 = cat(_allocatable_slots_WIRE_1[5], _allocatable_slots_WIRE_1[4])
node allocatable_slots_hi_1 = cat(allocatable_slots_hi_hi_1, _allocatable_slots_WIRE_1[3])
node _allocatable_slots_T_56 = cat(allocatable_slots_hi_1, allocatable_slots_lo_1)
node _allocatable_slots_T_57 = dshl(UInt<1>(0h1), _T_66)
node _allocatable_slots_T_58 = dshr(_allocatable_slots_T_57, UInt<1>(0h0))
node _allocatable_slots_T_59 = dshr(_allocatable_slots_T_57, UInt<1>(0h1))
node _allocatable_slots_T_60 = dshr(_allocatable_slots_T_57, UInt<2>(0h2))
node _allocatable_slots_T_61 = dshr(_allocatable_slots_T_57, UInt<2>(0h3))
node _allocatable_slots_T_62 = dshr(_allocatable_slots_T_57, UInt<3>(0h4))
node _allocatable_slots_T_63 = dshr(_allocatable_slots_T_57, UInt<3>(0h5))
node _allocatable_slots_T_64 = dshr(_allocatable_slots_T_57, UInt<3>(0h6))
node _allocatable_slots_T_65 = dshr(_allocatable_slots_T_57, UInt<3>(0h7))
node _allocatable_slots_T_66 = or(_allocatable_slots_T_58, _allocatable_slots_T_59)
node _allocatable_slots_T_67 = or(_allocatable_slots_T_66, _allocatable_slots_T_60)
node _allocatable_slots_T_68 = or(_allocatable_slots_T_67, _allocatable_slots_T_61)
node _allocatable_slots_T_69 = or(_allocatable_slots_T_68, _allocatable_slots_T_62)
node _allocatable_slots_T_70 = or(_allocatable_slots_T_69, _allocatable_slots_T_63)
node _allocatable_slots_T_71 = or(_allocatable_slots_T_70, _allocatable_slots_T_64)
node _allocatable_slots_T_72 = or(_allocatable_slots_T_71, _allocatable_slots_T_65)
node _allocatable_slots_T_73 = mux(_T_65, UInt<6>(0h3f), UInt<6>(0h0))
node _allocatable_slots_T_74 = and(_allocatable_slots_T_72, _allocatable_slots_T_73)
node _allocatable_slots_T_75 = not(_allocatable_slots_T_74)
node allocatable_slots_1 = and(_allocatable_slots_T_56, _allocatable_slots_T_75)
inst alloc_lfsr_prng_1 of MaxPeriodFibonacciLFSR_12
connect alloc_lfsr_prng_1.clock, clock
connect alloc_lfsr_prng_1.reset, reset
connect alloc_lfsr_prng_1.io.seed.valid, UInt<1>(0h0)
invalidate alloc_lfsr_prng_1.io.seed.bits[0]
invalidate alloc_lfsr_prng_1.io.seed.bits[1]
invalidate alloc_lfsr_prng_1.io.seed.bits[2]
invalidate alloc_lfsr_prng_1.io.seed.bits[3]
invalidate alloc_lfsr_prng_1.io.seed.bits[4]
invalidate alloc_lfsr_prng_1.io.seed.bits[5]
connect alloc_lfsr_prng_1.io.increment, UInt<1>(0h1)
node alloc_lfsr_lo_hi_1 = cat(alloc_lfsr_prng_1.io.out[2], alloc_lfsr_prng_1.io.out[1])
node alloc_lfsr_lo_1 = cat(alloc_lfsr_lo_hi_1, alloc_lfsr_prng_1.io.out[0])
node alloc_lfsr_hi_hi_1 = cat(alloc_lfsr_prng_1.io.out[5], alloc_lfsr_prng_1.io.out[4])
node alloc_lfsr_hi_1 = cat(alloc_lfsr_hi_hi_1, alloc_lfsr_prng_1.io.out[3])
node alloc_lfsr_1 = cat(alloc_lfsr_hi_1, alloc_lfsr_lo_1)
node _first_entry_T_14 = bits(allocatable_slots_1, 0, 0)
node _first_entry_T_15 = bits(allocatable_slots_1, 1, 1)
node _first_entry_T_16 = bits(allocatable_slots_1, 2, 2)
node _first_entry_T_17 = bits(allocatable_slots_1, 3, 3)
node _first_entry_T_18 = bits(allocatable_slots_1, 4, 4)
node _first_entry_T_19 = bits(allocatable_slots_1, 5, 5)
node _first_entry_T_20 = bits(allocatable_slots_1, 6, 6)
node _first_entry_T_21 = bits(allocatable_slots_1, 7, 7)
node _first_entry_T_22 = mux(_first_entry_T_20, UInt<3>(0h6), UInt<3>(0h7))
node _first_entry_T_23 = mux(_first_entry_T_19, UInt<3>(0h5), _first_entry_T_22)
node _first_entry_T_24 = mux(_first_entry_T_18, UInt<3>(0h4), _first_entry_T_23)
node _first_entry_T_25 = mux(_first_entry_T_17, UInt<2>(0h3), _first_entry_T_24)
node _first_entry_T_26 = mux(_first_entry_T_16, UInt<2>(0h2), _first_entry_T_25)
node _first_entry_T_27 = mux(_first_entry_T_15, UInt<1>(0h1), _first_entry_T_26)
node first_entry_1 = mux(_first_entry_T_14, UInt<1>(0h0), _first_entry_T_27)
node _masked_entry_T_15 = and(allocatable_slots_1, alloc_lfsr_1)
node _masked_entry_T_16 = bits(_masked_entry_T_15, 0, 0)
node _masked_entry_T_17 = bits(_masked_entry_T_15, 1, 1)
node _masked_entry_T_18 = bits(_masked_entry_T_15, 2, 2)
node _masked_entry_T_19 = bits(_masked_entry_T_15, 3, 3)
node _masked_entry_T_20 = bits(_masked_entry_T_15, 4, 4)
node _masked_entry_T_21 = bits(_masked_entry_T_15, 5, 5)
node _masked_entry_T_22 = bits(_masked_entry_T_15, 6, 6)
node _masked_entry_T_23 = bits(_masked_entry_T_15, 7, 7)
node _masked_entry_T_24 = mux(_masked_entry_T_22, UInt<3>(0h6), UInt<3>(0h7))
node _masked_entry_T_25 = mux(_masked_entry_T_21, UInt<3>(0h5), _masked_entry_T_24)
node _masked_entry_T_26 = mux(_masked_entry_T_20, UInt<3>(0h4), _masked_entry_T_25)
node _masked_entry_T_27 = mux(_masked_entry_T_19, UInt<2>(0h3), _masked_entry_T_26)
node _masked_entry_T_28 = mux(_masked_entry_T_18, UInt<2>(0h2), _masked_entry_T_27)
node _masked_entry_T_29 = mux(_masked_entry_T_17, UInt<1>(0h1), _masked_entry_T_28)
node masked_entry_1 = mux(_masked_entry_T_16, UInt<1>(0h0), _masked_entry_T_29)
node _alloc_entry_T_2 = dshr(allocatable_slots_1, masked_entry_1)
node _alloc_entry_T_3 = bits(_alloc_entry_T_2, 0, 0)
node alloc_entry_1 = mux(_alloc_entry_T_3, masked_entry_1, first_entry_1)
node _f3_meta_allocate_1_valid_T = neq(allocatable_slots_1, UInt<1>(0h0))
connect f3_meta.allocate[1].valid, _f3_meta_allocate_1_valid_T
connect f3_meta.allocate[1].bits, alloc_entry_1
node _update_was_taken_T_2 = eq(s1_update.bits.cfi_idx.bits, UInt<1>(0h1))
node _update_was_taken_T_3 = and(s1_update.bits.cfi_idx.valid, _update_was_taken_T_2)
node update_was_taken_1 = and(_update_was_taken_T_3, s1_update.bits.cfi_taken)
node _T_69 = bits(s1_update.bits.br_mask, 1, 1)
node _T_70 = and(_T_69, s1_update.valid)
node _T_71 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update)
node _T_72 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0))
node _T_73 = or(_T_71, _T_72)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = and(_T_70, _T_74)
when _T_75 :
when s1_update_meta.provider[1].valid :
connect s1_update_mask[s1_update_meta.provider[1].bits][1], UInt<1>(0h1)
connect s1_update_u_mask[s1_update_meta.provider[1].bits][1], UInt<1>(0h1)
node _new_u_T_11 = bits(s1_update_mispredict_mask, 1, 1)
node _new_u_T_12 = eq(s1_update_meta.alt_differs[1], UInt<1>(0h0))
node _new_u_T_13 = eq(s1_update_meta.provider_u[1], UInt<1>(0h0))
node _new_u_T_14 = sub(s1_update_meta.provider_u[1], UInt<1>(0h1))
node _new_u_T_15 = tail(_new_u_T_14, 1)
node _new_u_T_16 = mux(_new_u_T_13, UInt<1>(0h0), _new_u_T_15)
node _new_u_T_17 = eq(s1_update_meta.provider_u[1], UInt<2>(0h3))
node _new_u_T_18 = add(s1_update_meta.provider_u[1], UInt<1>(0h1))
node _new_u_T_19 = tail(_new_u_T_18, 1)
node _new_u_T_20 = mux(_new_u_T_17, UInt<2>(0h3), _new_u_T_19)
node _new_u_T_21 = mux(_new_u_T_11, _new_u_T_16, _new_u_T_20)
node new_u_1 = mux(_new_u_T_12, s1_update_meta.provider_u[1], _new_u_T_21)
connect s1_update_u[s1_update_meta.provider[1].bits][1], new_u_1
connect s1_update_taken[s1_update_meta.provider[1].bits][1], update_was_taken_1
connect s1_update_old_ctr[s1_update_meta.provider[1].bits][1], s1_update_meta.provider_ctr[1]
connect s1_update_alloc[s1_update_meta.provider[1].bits][1], UInt<1>(0h0)
wire final_altpred_2 : UInt<1>
connect final_altpred_2, io.resp_in[0].f3[2].taken
connect io.resp.f3[2].taken, io.resp_in[0].f3[2].taken
when f3_resps[0][2].valid :
node _io_resp_f3_2_taken_T = eq(f3_resps[0][2].bits.ctr, UInt<2>(0h3))
node _io_resp_f3_2_taken_T_1 = eq(f3_resps[0][2].bits.ctr, UInt<3>(0h4))
node _io_resp_f3_2_taken_T_2 = or(_io_resp_f3_2_taken_T, _io_resp_f3_2_taken_T_1)
node _io_resp_f3_2_taken_T_3 = bits(f3_resps[0][2].bits.ctr, 2, 2)
node _io_resp_f3_2_taken_T_4 = mux(_io_resp_f3_2_taken_T_2, io.resp_in[0].f3[2].taken, _io_resp_f3_2_taken_T_3)
connect io.resp.f3[2].taken, _io_resp_f3_2_taken_T_4
connect final_altpred_2, io.resp_in[0].f3[2].taken
node _T_76 = or(UInt<1>(0h0), f3_resps[0][2].valid)
node _T_77 = mux(f3_resps[0][2].valid, UInt<1>(0h0), UInt<1>(0h0))
node _T_78 = bits(f3_resps[0][2].bits.ctr, 2, 2)
node _T_79 = mux(f3_resps[0][2].valid, _T_78, io.resp_in[0].f3[2].taken)
when f3_resps[1][2].valid :
node _io_resp_f3_2_taken_T_5 = eq(f3_resps[1][2].bits.ctr, UInt<2>(0h3))
node _io_resp_f3_2_taken_T_6 = eq(f3_resps[1][2].bits.ctr, UInt<3>(0h4))
node _io_resp_f3_2_taken_T_7 = or(_io_resp_f3_2_taken_T_5, _io_resp_f3_2_taken_T_6)
node _io_resp_f3_2_taken_T_8 = bits(f3_resps[1][2].bits.ctr, 2, 2)
node _io_resp_f3_2_taken_T_9 = mux(_io_resp_f3_2_taken_T_7, _T_79, _io_resp_f3_2_taken_T_8)
connect io.resp.f3[2].taken, _io_resp_f3_2_taken_T_9
connect final_altpred_2, _T_79
node _T_80 = or(_T_76, f3_resps[1][2].valid)
node _T_81 = mux(f3_resps[1][2].valid, UInt<1>(0h1), _T_77)
node _T_82 = bits(f3_resps[1][2].bits.ctr, 2, 2)
node _T_83 = mux(f3_resps[1][2].valid, _T_82, _T_79)
when f3_resps[2][2].valid :
node _io_resp_f3_2_taken_T_10 = eq(f3_resps[2][2].bits.ctr, UInt<2>(0h3))
node _io_resp_f3_2_taken_T_11 = eq(f3_resps[2][2].bits.ctr, UInt<3>(0h4))
node _io_resp_f3_2_taken_T_12 = or(_io_resp_f3_2_taken_T_10, _io_resp_f3_2_taken_T_11)
node _io_resp_f3_2_taken_T_13 = bits(f3_resps[2][2].bits.ctr, 2, 2)
node _io_resp_f3_2_taken_T_14 = mux(_io_resp_f3_2_taken_T_12, _T_83, _io_resp_f3_2_taken_T_13)
connect io.resp.f3[2].taken, _io_resp_f3_2_taken_T_14
connect final_altpred_2, _T_83
node _T_84 = or(_T_80, f3_resps[2][2].valid)
node _T_85 = mux(f3_resps[2][2].valid, UInt<2>(0h2), _T_81)
node _T_86 = bits(f3_resps[2][2].bits.ctr, 2, 2)
node _T_87 = mux(f3_resps[2][2].valid, _T_86, _T_83)
when f3_resps[3][2].valid :
node _io_resp_f3_2_taken_T_15 = eq(f3_resps[3][2].bits.ctr, UInt<2>(0h3))
node _io_resp_f3_2_taken_T_16 = eq(f3_resps[3][2].bits.ctr, UInt<3>(0h4))
node _io_resp_f3_2_taken_T_17 = or(_io_resp_f3_2_taken_T_15, _io_resp_f3_2_taken_T_16)
node _io_resp_f3_2_taken_T_18 = bits(f3_resps[3][2].bits.ctr, 2, 2)
node _io_resp_f3_2_taken_T_19 = mux(_io_resp_f3_2_taken_T_17, _T_87, _io_resp_f3_2_taken_T_18)
connect io.resp.f3[2].taken, _io_resp_f3_2_taken_T_19
connect final_altpred_2, _T_87
node _T_88 = or(_T_84, f3_resps[3][2].valid)
node _T_89 = mux(f3_resps[3][2].valid, UInt<2>(0h3), _T_85)
node _T_90 = bits(f3_resps[3][2].bits.ctr, 2, 2)
node _T_91 = mux(f3_resps[3][2].valid, _T_90, _T_87)
when f3_resps[4][2].valid :
node _io_resp_f3_2_taken_T_20 = eq(f3_resps[4][2].bits.ctr, UInt<2>(0h3))
node _io_resp_f3_2_taken_T_21 = eq(f3_resps[4][2].bits.ctr, UInt<3>(0h4))
node _io_resp_f3_2_taken_T_22 = or(_io_resp_f3_2_taken_T_20, _io_resp_f3_2_taken_T_21)
node _io_resp_f3_2_taken_T_23 = bits(f3_resps[4][2].bits.ctr, 2, 2)
node _io_resp_f3_2_taken_T_24 = mux(_io_resp_f3_2_taken_T_22, _T_91, _io_resp_f3_2_taken_T_23)
connect io.resp.f3[2].taken, _io_resp_f3_2_taken_T_24
connect final_altpred_2, _T_91
node _T_92 = or(_T_88, f3_resps[4][2].valid)
node _T_93 = mux(f3_resps[4][2].valid, UInt<3>(0h4), _T_89)
node _T_94 = bits(f3_resps[4][2].bits.ctr, 2, 2)
node _T_95 = mux(f3_resps[4][2].valid, _T_94, _T_91)
when f3_resps[5][2].valid :
node _io_resp_f3_2_taken_T_25 = eq(f3_resps[5][2].bits.ctr, UInt<2>(0h3))
node _io_resp_f3_2_taken_T_26 = eq(f3_resps[5][2].bits.ctr, UInt<3>(0h4))
node _io_resp_f3_2_taken_T_27 = or(_io_resp_f3_2_taken_T_25, _io_resp_f3_2_taken_T_26)
node _io_resp_f3_2_taken_T_28 = bits(f3_resps[5][2].bits.ctr, 2, 2)
node _io_resp_f3_2_taken_T_29 = mux(_io_resp_f3_2_taken_T_27, _T_95, _io_resp_f3_2_taken_T_28)
connect io.resp.f3[2].taken, _io_resp_f3_2_taken_T_29
connect final_altpred_2, _T_95
node _T_96 = or(_T_92, f3_resps[5][2].valid)
node _T_97 = mux(f3_resps[5][2].valid, UInt<3>(0h5), _T_93)
node _T_98 = bits(f3_resps[5][2].bits.ctr, 2, 2)
node _T_99 = mux(f3_resps[5][2].valid, _T_98, _T_95)
connect f3_meta.provider[2].valid, _T_96
connect f3_meta.provider[2].bits, _T_97
node _f3_meta_alt_differs_2_T = neq(final_altpred_2, io.resp.f3[2].taken)
connect f3_meta.alt_differs[2], _f3_meta_alt_differs_2_T
connect f3_meta.provider_u[2], f3_resps[_T_97][2].bits.u
connect f3_meta.provider_ctr[2], f3_resps[_T_97][2].bits.ctr
node _allocatable_slots_T_76 = eq(f3_resps[0][2].valid, UInt<1>(0h0))
node _allocatable_slots_T_77 = eq(f3_resps[0][2].bits.u, UInt<1>(0h0))
node _allocatable_slots_T_78 = and(_allocatable_slots_T_76, _allocatable_slots_T_77)
node _allocatable_slots_T_79 = eq(f3_resps[1][2].valid, UInt<1>(0h0))
node _allocatable_slots_T_80 = eq(f3_resps[1][2].bits.u, UInt<1>(0h0))
node _allocatable_slots_T_81 = and(_allocatable_slots_T_79, _allocatable_slots_T_80)
node _allocatable_slots_T_82 = eq(f3_resps[2][2].valid, UInt<1>(0h0))
node _allocatable_slots_T_83 = eq(f3_resps[2][2].bits.u, UInt<1>(0h0))
node _allocatable_slots_T_84 = and(_allocatable_slots_T_82, _allocatable_slots_T_83)
node _allocatable_slots_T_85 = eq(f3_resps[3][2].valid, UInt<1>(0h0))
node _allocatable_slots_T_86 = eq(f3_resps[3][2].bits.u, UInt<1>(0h0))
node _allocatable_slots_T_87 = and(_allocatable_slots_T_85, _allocatable_slots_T_86)
node _allocatable_slots_T_88 = eq(f3_resps[4][2].valid, UInt<1>(0h0))
node _allocatable_slots_T_89 = eq(f3_resps[4][2].bits.u, UInt<1>(0h0))
node _allocatable_slots_T_90 = and(_allocatable_slots_T_88, _allocatable_slots_T_89)
node _allocatable_slots_T_91 = eq(f3_resps[5][2].valid, UInt<1>(0h0))
node _allocatable_slots_T_92 = eq(f3_resps[5][2].bits.u, UInt<1>(0h0))
node _allocatable_slots_T_93 = and(_allocatable_slots_T_91, _allocatable_slots_T_92)
wire _allocatable_slots_WIRE_2 : UInt<1>[6]
connect _allocatable_slots_WIRE_2[0], _allocatable_slots_T_78
connect _allocatable_slots_WIRE_2[1], _allocatable_slots_T_81
connect _allocatable_slots_WIRE_2[2], _allocatable_slots_T_84
connect _allocatable_slots_WIRE_2[3], _allocatable_slots_T_87
connect _allocatable_slots_WIRE_2[4], _allocatable_slots_T_90
connect _allocatable_slots_WIRE_2[5], _allocatable_slots_T_93
node allocatable_slots_lo_hi_2 = cat(_allocatable_slots_WIRE_2[2], _allocatable_slots_WIRE_2[1])
node allocatable_slots_lo_2 = cat(allocatable_slots_lo_hi_2, _allocatable_slots_WIRE_2[0])
node allocatable_slots_hi_hi_2 = cat(_allocatable_slots_WIRE_2[5], _allocatable_slots_WIRE_2[4])
node allocatable_slots_hi_2 = cat(allocatable_slots_hi_hi_2, _allocatable_slots_WIRE_2[3])
node _allocatable_slots_T_94 = cat(allocatable_slots_hi_2, allocatable_slots_lo_2)
node _allocatable_slots_T_95 = dshl(UInt<1>(0h1), _T_97)
node _allocatable_slots_T_96 = dshr(_allocatable_slots_T_95, UInt<1>(0h0))
node _allocatable_slots_T_97 = dshr(_allocatable_slots_T_95, UInt<1>(0h1))
node _allocatable_slots_T_98 = dshr(_allocatable_slots_T_95, UInt<2>(0h2))
node _allocatable_slots_T_99 = dshr(_allocatable_slots_T_95, UInt<2>(0h3))
node _allocatable_slots_T_100 = dshr(_allocatable_slots_T_95, UInt<3>(0h4))
node _allocatable_slots_T_101 = dshr(_allocatable_slots_T_95, UInt<3>(0h5))
node _allocatable_slots_T_102 = dshr(_allocatable_slots_T_95, UInt<3>(0h6))
node _allocatable_slots_T_103 = dshr(_allocatable_slots_T_95, UInt<3>(0h7))
node _allocatable_slots_T_104 = or(_allocatable_slots_T_96, _allocatable_slots_T_97)
node _allocatable_slots_T_105 = or(_allocatable_slots_T_104, _allocatable_slots_T_98)
node _allocatable_slots_T_106 = or(_allocatable_slots_T_105, _allocatable_slots_T_99)
node _allocatable_slots_T_107 = or(_allocatable_slots_T_106, _allocatable_slots_T_100)
node _allocatable_slots_T_108 = or(_allocatable_slots_T_107, _allocatable_slots_T_101)
node _allocatable_slots_T_109 = or(_allocatable_slots_T_108, _allocatable_slots_T_102)
node _allocatable_slots_T_110 = or(_allocatable_slots_T_109, _allocatable_slots_T_103)
node _allocatable_slots_T_111 = mux(_T_96, UInt<6>(0h3f), UInt<6>(0h0))
node _allocatable_slots_T_112 = and(_allocatable_slots_T_110, _allocatable_slots_T_111)
node _allocatable_slots_T_113 = not(_allocatable_slots_T_112)
node allocatable_slots_2 = and(_allocatable_slots_T_94, _allocatable_slots_T_113)
inst alloc_lfsr_prng_2 of MaxPeriodFibonacciLFSR_13
connect alloc_lfsr_prng_2.clock, clock
connect alloc_lfsr_prng_2.reset, reset
connect alloc_lfsr_prng_2.io.seed.valid, UInt<1>(0h0)
invalidate alloc_lfsr_prng_2.io.seed.bits[0]
invalidate alloc_lfsr_prng_2.io.seed.bits[1]
invalidate alloc_lfsr_prng_2.io.seed.bits[2]
invalidate alloc_lfsr_prng_2.io.seed.bits[3]
invalidate alloc_lfsr_prng_2.io.seed.bits[4]
invalidate alloc_lfsr_prng_2.io.seed.bits[5]
connect alloc_lfsr_prng_2.io.increment, UInt<1>(0h1)
node alloc_lfsr_lo_hi_2 = cat(alloc_lfsr_prng_2.io.out[2], alloc_lfsr_prng_2.io.out[1])
node alloc_lfsr_lo_2 = cat(alloc_lfsr_lo_hi_2, alloc_lfsr_prng_2.io.out[0])
node alloc_lfsr_hi_hi_2 = cat(alloc_lfsr_prng_2.io.out[5], alloc_lfsr_prng_2.io.out[4])
node alloc_lfsr_hi_2 = cat(alloc_lfsr_hi_hi_2, alloc_lfsr_prng_2.io.out[3])
node alloc_lfsr_2 = cat(alloc_lfsr_hi_2, alloc_lfsr_lo_2)
node _first_entry_T_28 = bits(allocatable_slots_2, 0, 0)
node _first_entry_T_29 = bits(allocatable_slots_2, 1, 1)
node _first_entry_T_30 = bits(allocatable_slots_2, 2, 2)
node _first_entry_T_31 = bits(allocatable_slots_2, 3, 3)
node _first_entry_T_32 = bits(allocatable_slots_2, 4, 4)
node _first_entry_T_33 = bits(allocatable_slots_2, 5, 5)
node _first_entry_T_34 = bits(allocatable_slots_2, 6, 6)
node _first_entry_T_35 = bits(allocatable_slots_2, 7, 7)
node _first_entry_T_36 = mux(_first_entry_T_34, UInt<3>(0h6), UInt<3>(0h7))
node _first_entry_T_37 = mux(_first_entry_T_33, UInt<3>(0h5), _first_entry_T_36)
node _first_entry_T_38 = mux(_first_entry_T_32, UInt<3>(0h4), _first_entry_T_37)
node _first_entry_T_39 = mux(_first_entry_T_31, UInt<2>(0h3), _first_entry_T_38)
node _first_entry_T_40 = mux(_first_entry_T_30, UInt<2>(0h2), _first_entry_T_39)
node _first_entry_T_41 = mux(_first_entry_T_29, UInt<1>(0h1), _first_entry_T_40)
node first_entry_2 = mux(_first_entry_T_28, UInt<1>(0h0), _first_entry_T_41)
node _masked_entry_T_30 = and(allocatable_slots_2, alloc_lfsr_2)
node _masked_entry_T_31 = bits(_masked_entry_T_30, 0, 0)
node _masked_entry_T_32 = bits(_masked_entry_T_30, 1, 1)
node _masked_entry_T_33 = bits(_masked_entry_T_30, 2, 2)
node _masked_entry_T_34 = bits(_masked_entry_T_30, 3, 3)
node _masked_entry_T_35 = bits(_masked_entry_T_30, 4, 4)
node _masked_entry_T_36 = bits(_masked_entry_T_30, 5, 5)
node _masked_entry_T_37 = bits(_masked_entry_T_30, 6, 6)
node _masked_entry_T_38 = bits(_masked_entry_T_30, 7, 7)
node _masked_entry_T_39 = mux(_masked_entry_T_37, UInt<3>(0h6), UInt<3>(0h7))
node _masked_entry_T_40 = mux(_masked_entry_T_36, UInt<3>(0h5), _masked_entry_T_39)
node _masked_entry_T_41 = mux(_masked_entry_T_35, UInt<3>(0h4), _masked_entry_T_40)
node _masked_entry_T_42 = mux(_masked_entry_T_34, UInt<2>(0h3), _masked_entry_T_41)
node _masked_entry_T_43 = mux(_masked_entry_T_33, UInt<2>(0h2), _masked_entry_T_42)
node _masked_entry_T_44 = mux(_masked_entry_T_32, UInt<1>(0h1), _masked_entry_T_43)
node masked_entry_2 = mux(_masked_entry_T_31, UInt<1>(0h0), _masked_entry_T_44)
node _alloc_entry_T_4 = dshr(allocatable_slots_2, masked_entry_2)
node _alloc_entry_T_5 = bits(_alloc_entry_T_4, 0, 0)
node alloc_entry_2 = mux(_alloc_entry_T_5, masked_entry_2, first_entry_2)
node _f3_meta_allocate_2_valid_T = neq(allocatable_slots_2, UInt<1>(0h0))
connect f3_meta.allocate[2].valid, _f3_meta_allocate_2_valid_T
connect f3_meta.allocate[2].bits, alloc_entry_2
node _update_was_taken_T_4 = eq(s1_update.bits.cfi_idx.bits, UInt<2>(0h2))
node _update_was_taken_T_5 = and(s1_update.bits.cfi_idx.valid, _update_was_taken_T_4)
node update_was_taken_2 = and(_update_was_taken_T_5, s1_update.bits.cfi_taken)
node _T_100 = bits(s1_update.bits.br_mask, 2, 2)
node _T_101 = and(_T_100, s1_update.valid)
node _T_102 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update)
node _T_103 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0))
node _T_104 = or(_T_102, _T_103)
node _T_105 = eq(_T_104, UInt<1>(0h0))
node _T_106 = and(_T_101, _T_105)
when _T_106 :
when s1_update_meta.provider[2].valid :
connect s1_update_mask[s1_update_meta.provider[2].bits][2], UInt<1>(0h1)
connect s1_update_u_mask[s1_update_meta.provider[2].bits][2], UInt<1>(0h1)
node _new_u_T_22 = bits(s1_update_mispredict_mask, 2, 2)
node _new_u_T_23 = eq(s1_update_meta.alt_differs[2], UInt<1>(0h0))
node _new_u_T_24 = eq(s1_update_meta.provider_u[2], UInt<1>(0h0))
node _new_u_T_25 = sub(s1_update_meta.provider_u[2], UInt<1>(0h1))
node _new_u_T_26 = tail(_new_u_T_25, 1)
node _new_u_T_27 = mux(_new_u_T_24, UInt<1>(0h0), _new_u_T_26)
node _new_u_T_28 = eq(s1_update_meta.provider_u[2], UInt<2>(0h3))
node _new_u_T_29 = add(s1_update_meta.provider_u[2], UInt<1>(0h1))
node _new_u_T_30 = tail(_new_u_T_29, 1)
node _new_u_T_31 = mux(_new_u_T_28, UInt<2>(0h3), _new_u_T_30)
node _new_u_T_32 = mux(_new_u_T_22, _new_u_T_27, _new_u_T_31)
node new_u_2 = mux(_new_u_T_23, s1_update_meta.provider_u[2], _new_u_T_32)
connect s1_update_u[s1_update_meta.provider[2].bits][2], new_u_2
connect s1_update_taken[s1_update_meta.provider[2].bits][2], update_was_taken_2
connect s1_update_old_ctr[s1_update_meta.provider[2].bits][2], s1_update_meta.provider_ctr[2]
connect s1_update_alloc[s1_update_meta.provider[2].bits][2], UInt<1>(0h0)
wire final_altpred_3 : UInt<1>
connect final_altpred_3, io.resp_in[0].f3[3].taken
connect io.resp.f3[3].taken, io.resp_in[0].f3[3].taken
when f3_resps[0][3].valid :
node _io_resp_f3_3_taken_T = eq(f3_resps[0][3].bits.ctr, UInt<2>(0h3))
node _io_resp_f3_3_taken_T_1 = eq(f3_resps[0][3].bits.ctr, UInt<3>(0h4))
node _io_resp_f3_3_taken_T_2 = or(_io_resp_f3_3_taken_T, _io_resp_f3_3_taken_T_1)
node _io_resp_f3_3_taken_T_3 = bits(f3_resps[0][3].bits.ctr, 2, 2)
node _io_resp_f3_3_taken_T_4 = mux(_io_resp_f3_3_taken_T_2, io.resp_in[0].f3[3].taken, _io_resp_f3_3_taken_T_3)
connect io.resp.f3[3].taken, _io_resp_f3_3_taken_T_4
connect final_altpred_3, io.resp_in[0].f3[3].taken
node _T_107 = or(UInt<1>(0h0), f3_resps[0][3].valid)
node _T_108 = mux(f3_resps[0][3].valid, UInt<1>(0h0), UInt<1>(0h0))
node _T_109 = bits(f3_resps[0][3].bits.ctr, 2, 2)
node _T_110 = mux(f3_resps[0][3].valid, _T_109, io.resp_in[0].f3[3].taken)
when f3_resps[1][3].valid :
node _io_resp_f3_3_taken_T_5 = eq(f3_resps[1][3].bits.ctr, UInt<2>(0h3))
node _io_resp_f3_3_taken_T_6 = eq(f3_resps[1][3].bits.ctr, UInt<3>(0h4))
node _io_resp_f3_3_taken_T_7 = or(_io_resp_f3_3_taken_T_5, _io_resp_f3_3_taken_T_6)
node _io_resp_f3_3_taken_T_8 = bits(f3_resps[1][3].bits.ctr, 2, 2)
node _io_resp_f3_3_taken_T_9 = mux(_io_resp_f3_3_taken_T_7, _T_110, _io_resp_f3_3_taken_T_8)
connect io.resp.f3[3].taken, _io_resp_f3_3_taken_T_9
connect final_altpred_3, _T_110
node _T_111 = or(_T_107, f3_resps[1][3].valid)
node _T_112 = mux(f3_resps[1][3].valid, UInt<1>(0h1), _T_108)
node _T_113 = bits(f3_resps[1][3].bits.ctr, 2, 2)
node _T_114 = mux(f3_resps[1][3].valid, _T_113, _T_110)
when f3_resps[2][3].valid :
node _io_resp_f3_3_taken_T_10 = eq(f3_resps[2][3].bits.ctr, UInt<2>(0h3))
node _io_resp_f3_3_taken_T_11 = eq(f3_resps[2][3].bits.ctr, UInt<3>(0h4))
node _io_resp_f3_3_taken_T_12 = or(_io_resp_f3_3_taken_T_10, _io_resp_f3_3_taken_T_11)
node _io_resp_f3_3_taken_T_13 = bits(f3_resps[2][3].bits.ctr, 2, 2)
node _io_resp_f3_3_taken_T_14 = mux(_io_resp_f3_3_taken_T_12, _T_114, _io_resp_f3_3_taken_T_13)
connect io.resp.f3[3].taken, _io_resp_f3_3_taken_T_14
connect final_altpred_3, _T_114
node _T_115 = or(_T_111, f3_resps[2][3].valid)
node _T_116 = mux(f3_resps[2][3].valid, UInt<2>(0h2), _T_112)
node _T_117 = bits(f3_resps[2][3].bits.ctr, 2, 2)
node _T_118 = mux(f3_resps[2][3].valid, _T_117, _T_114)
when f3_resps[3][3].valid :
node _io_resp_f3_3_taken_T_15 = eq(f3_resps[3][3].bits.ctr, UInt<2>(0h3))
node _io_resp_f3_3_taken_T_16 = eq(f3_resps[3][3].bits.ctr, UInt<3>(0h4))
node _io_resp_f3_3_taken_T_17 = or(_io_resp_f3_3_taken_T_15, _io_resp_f3_3_taken_T_16)
node _io_resp_f3_3_taken_T_18 = bits(f3_resps[3][3].bits.ctr, 2, 2)
node _io_resp_f3_3_taken_T_19 = mux(_io_resp_f3_3_taken_T_17, _T_118, _io_resp_f3_3_taken_T_18)
connect io.resp.f3[3].taken, _io_resp_f3_3_taken_T_19
connect final_altpred_3, _T_118
node _T_119 = or(_T_115, f3_resps[3][3].valid)
node _T_120 = mux(f3_resps[3][3].valid, UInt<2>(0h3), _T_116)
node _T_121 = bits(f3_resps[3][3].bits.ctr, 2, 2)
node _T_122 = mux(f3_resps[3][3].valid, _T_121, _T_118)
when f3_resps[4][3].valid :
node _io_resp_f3_3_taken_T_20 = eq(f3_resps[4][3].bits.ctr, UInt<2>(0h3))
node _io_resp_f3_3_taken_T_21 = eq(f3_resps[4][3].bits.ctr, UInt<3>(0h4))
node _io_resp_f3_3_taken_T_22 = or(_io_resp_f3_3_taken_T_20, _io_resp_f3_3_taken_T_21)
node _io_resp_f3_3_taken_T_23 = bits(f3_resps[4][3].bits.ctr, 2, 2)
node _io_resp_f3_3_taken_T_24 = mux(_io_resp_f3_3_taken_T_22, _T_122, _io_resp_f3_3_taken_T_23)
connect io.resp.f3[3].taken, _io_resp_f3_3_taken_T_24
connect final_altpred_3, _T_122
node _T_123 = or(_T_119, f3_resps[4][3].valid)
node _T_124 = mux(f3_resps[4][3].valid, UInt<3>(0h4), _T_120)
node _T_125 = bits(f3_resps[4][3].bits.ctr, 2, 2)
node _T_126 = mux(f3_resps[4][3].valid, _T_125, _T_122)
when f3_resps[5][3].valid :
node _io_resp_f3_3_taken_T_25 = eq(f3_resps[5][3].bits.ctr, UInt<2>(0h3))
node _io_resp_f3_3_taken_T_26 = eq(f3_resps[5][3].bits.ctr, UInt<3>(0h4))
node _io_resp_f3_3_taken_T_27 = or(_io_resp_f3_3_taken_T_25, _io_resp_f3_3_taken_T_26)
node _io_resp_f3_3_taken_T_28 = bits(f3_resps[5][3].bits.ctr, 2, 2)
node _io_resp_f3_3_taken_T_29 = mux(_io_resp_f3_3_taken_T_27, _T_126, _io_resp_f3_3_taken_T_28)
connect io.resp.f3[3].taken, _io_resp_f3_3_taken_T_29
connect final_altpred_3, _T_126
node _T_127 = or(_T_123, f3_resps[5][3].valid)
node _T_128 = mux(f3_resps[5][3].valid, UInt<3>(0h5), _T_124)
node _T_129 = bits(f3_resps[5][3].bits.ctr, 2, 2)
node _T_130 = mux(f3_resps[5][3].valid, _T_129, _T_126)
connect f3_meta.provider[3].valid, _T_127
connect f3_meta.provider[3].bits, _T_128
node _f3_meta_alt_differs_3_T = neq(final_altpred_3, io.resp.f3[3].taken)
connect f3_meta.alt_differs[3], _f3_meta_alt_differs_3_T
connect f3_meta.provider_u[3], f3_resps[_T_128][3].bits.u
connect f3_meta.provider_ctr[3], f3_resps[_T_128][3].bits.ctr
node _allocatable_slots_T_114 = eq(f3_resps[0][3].valid, UInt<1>(0h0))
node _allocatable_slots_T_115 = eq(f3_resps[0][3].bits.u, UInt<1>(0h0))
node _allocatable_slots_T_116 = and(_allocatable_slots_T_114, _allocatable_slots_T_115)
node _allocatable_slots_T_117 = eq(f3_resps[1][3].valid, UInt<1>(0h0))
node _allocatable_slots_T_118 = eq(f3_resps[1][3].bits.u, UInt<1>(0h0))
node _allocatable_slots_T_119 = and(_allocatable_slots_T_117, _allocatable_slots_T_118)
node _allocatable_slots_T_120 = eq(f3_resps[2][3].valid, UInt<1>(0h0))
node _allocatable_slots_T_121 = eq(f3_resps[2][3].bits.u, UInt<1>(0h0))
node _allocatable_slots_T_122 = and(_allocatable_slots_T_120, _allocatable_slots_T_121)
node _allocatable_slots_T_123 = eq(f3_resps[3][3].valid, UInt<1>(0h0))
node _allocatable_slots_T_124 = eq(f3_resps[3][3].bits.u, UInt<1>(0h0))
node _allocatable_slots_T_125 = and(_allocatable_slots_T_123, _allocatable_slots_T_124)
node _allocatable_slots_T_126 = eq(f3_resps[4][3].valid, UInt<1>(0h0))
node _allocatable_slots_T_127 = eq(f3_resps[4][3].bits.u, UInt<1>(0h0))
node _allocatable_slots_T_128 = and(_allocatable_slots_T_126, _allocatable_slots_T_127)
node _allocatable_slots_T_129 = eq(f3_resps[5][3].valid, UInt<1>(0h0))
node _allocatable_slots_T_130 = eq(f3_resps[5][3].bits.u, UInt<1>(0h0))
node _allocatable_slots_T_131 = and(_allocatable_slots_T_129, _allocatable_slots_T_130)
wire _allocatable_slots_WIRE_3 : UInt<1>[6]
connect _allocatable_slots_WIRE_3[0], _allocatable_slots_T_116
connect _allocatable_slots_WIRE_3[1], _allocatable_slots_T_119
connect _allocatable_slots_WIRE_3[2], _allocatable_slots_T_122
connect _allocatable_slots_WIRE_3[3], _allocatable_slots_T_125
connect _allocatable_slots_WIRE_3[4], _allocatable_slots_T_128
connect _allocatable_slots_WIRE_3[5], _allocatable_slots_T_131
node allocatable_slots_lo_hi_3 = cat(_allocatable_slots_WIRE_3[2], _allocatable_slots_WIRE_3[1])
node allocatable_slots_lo_3 = cat(allocatable_slots_lo_hi_3, _allocatable_slots_WIRE_3[0])
node allocatable_slots_hi_hi_3 = cat(_allocatable_slots_WIRE_3[5], _allocatable_slots_WIRE_3[4])
node allocatable_slots_hi_3 = cat(allocatable_slots_hi_hi_3, _allocatable_slots_WIRE_3[3])
node _allocatable_slots_T_132 = cat(allocatable_slots_hi_3, allocatable_slots_lo_3)
node _allocatable_slots_T_133 = dshl(UInt<1>(0h1), _T_128)
node _allocatable_slots_T_134 = dshr(_allocatable_slots_T_133, UInt<1>(0h0))
node _allocatable_slots_T_135 = dshr(_allocatable_slots_T_133, UInt<1>(0h1))
node _allocatable_slots_T_136 = dshr(_allocatable_slots_T_133, UInt<2>(0h2))
node _allocatable_slots_T_137 = dshr(_allocatable_slots_T_133, UInt<2>(0h3))
node _allocatable_slots_T_138 = dshr(_allocatable_slots_T_133, UInt<3>(0h4))
node _allocatable_slots_T_139 = dshr(_allocatable_slots_T_133, UInt<3>(0h5))
node _allocatable_slots_T_140 = dshr(_allocatable_slots_T_133, UInt<3>(0h6))
node _allocatable_slots_T_141 = dshr(_allocatable_slots_T_133, UInt<3>(0h7))
node _allocatable_slots_T_142 = or(_allocatable_slots_T_134, _allocatable_slots_T_135)
node _allocatable_slots_T_143 = or(_allocatable_slots_T_142, _allocatable_slots_T_136)
node _allocatable_slots_T_144 = or(_allocatable_slots_T_143, _allocatable_slots_T_137)
node _allocatable_slots_T_145 = or(_allocatable_slots_T_144, _allocatable_slots_T_138)
node _allocatable_slots_T_146 = or(_allocatable_slots_T_145, _allocatable_slots_T_139)
node _allocatable_slots_T_147 = or(_allocatable_slots_T_146, _allocatable_slots_T_140)
node _allocatable_slots_T_148 = or(_allocatable_slots_T_147, _allocatable_slots_T_141)
node _allocatable_slots_T_149 = mux(_T_127, UInt<6>(0h3f), UInt<6>(0h0))
node _allocatable_slots_T_150 = and(_allocatable_slots_T_148, _allocatable_slots_T_149)
node _allocatable_slots_T_151 = not(_allocatable_slots_T_150)
node allocatable_slots_3 = and(_allocatable_slots_T_132, _allocatable_slots_T_151)
inst alloc_lfsr_prng_3 of MaxPeriodFibonacciLFSR_14
connect alloc_lfsr_prng_3.clock, clock
connect alloc_lfsr_prng_3.reset, reset
connect alloc_lfsr_prng_3.io.seed.valid, UInt<1>(0h0)
invalidate alloc_lfsr_prng_3.io.seed.bits[0]
invalidate alloc_lfsr_prng_3.io.seed.bits[1]
invalidate alloc_lfsr_prng_3.io.seed.bits[2]
invalidate alloc_lfsr_prng_3.io.seed.bits[3]
invalidate alloc_lfsr_prng_3.io.seed.bits[4]
invalidate alloc_lfsr_prng_3.io.seed.bits[5]
connect alloc_lfsr_prng_3.io.increment, UInt<1>(0h1)
node alloc_lfsr_lo_hi_3 = cat(alloc_lfsr_prng_3.io.out[2], alloc_lfsr_prng_3.io.out[1])
node alloc_lfsr_lo_3 = cat(alloc_lfsr_lo_hi_3, alloc_lfsr_prng_3.io.out[0])
node alloc_lfsr_hi_hi_3 = cat(alloc_lfsr_prng_3.io.out[5], alloc_lfsr_prng_3.io.out[4])
node alloc_lfsr_hi_3 = cat(alloc_lfsr_hi_hi_3, alloc_lfsr_prng_3.io.out[3])
node alloc_lfsr_3 = cat(alloc_lfsr_hi_3, alloc_lfsr_lo_3)
node _first_entry_T_42 = bits(allocatable_slots_3, 0, 0)
node _first_entry_T_43 = bits(allocatable_slots_3, 1, 1)
node _first_entry_T_44 = bits(allocatable_slots_3, 2, 2)
node _first_entry_T_45 = bits(allocatable_slots_3, 3, 3)
node _first_entry_T_46 = bits(allocatable_slots_3, 4, 4)
node _first_entry_T_47 = bits(allocatable_slots_3, 5, 5)
node _first_entry_T_48 = bits(allocatable_slots_3, 6, 6)
node _first_entry_T_49 = bits(allocatable_slots_3, 7, 7)
node _first_entry_T_50 = mux(_first_entry_T_48, UInt<3>(0h6), UInt<3>(0h7))
node _first_entry_T_51 = mux(_first_entry_T_47, UInt<3>(0h5), _first_entry_T_50)
node _first_entry_T_52 = mux(_first_entry_T_46, UInt<3>(0h4), _first_entry_T_51)
node _first_entry_T_53 = mux(_first_entry_T_45, UInt<2>(0h3), _first_entry_T_52)
node _first_entry_T_54 = mux(_first_entry_T_44, UInt<2>(0h2), _first_entry_T_53)
node _first_entry_T_55 = mux(_first_entry_T_43, UInt<1>(0h1), _first_entry_T_54)
node first_entry_3 = mux(_first_entry_T_42, UInt<1>(0h0), _first_entry_T_55)
node _masked_entry_T_45 = and(allocatable_slots_3, alloc_lfsr_3)
node _masked_entry_T_46 = bits(_masked_entry_T_45, 0, 0)
node _masked_entry_T_47 = bits(_masked_entry_T_45, 1, 1)
node _masked_entry_T_48 = bits(_masked_entry_T_45, 2, 2)
node _masked_entry_T_49 = bits(_masked_entry_T_45, 3, 3)
node _masked_entry_T_50 = bits(_masked_entry_T_45, 4, 4)
node _masked_entry_T_51 = bits(_masked_entry_T_45, 5, 5)
node _masked_entry_T_52 = bits(_masked_entry_T_45, 6, 6)
node _masked_entry_T_53 = bits(_masked_entry_T_45, 7, 7)
node _masked_entry_T_54 = mux(_masked_entry_T_52, UInt<3>(0h6), UInt<3>(0h7))
node _masked_entry_T_55 = mux(_masked_entry_T_51, UInt<3>(0h5), _masked_entry_T_54)
node _masked_entry_T_56 = mux(_masked_entry_T_50, UInt<3>(0h4), _masked_entry_T_55)
node _masked_entry_T_57 = mux(_masked_entry_T_49, UInt<2>(0h3), _masked_entry_T_56)
node _masked_entry_T_58 = mux(_masked_entry_T_48, UInt<2>(0h2), _masked_entry_T_57)
node _masked_entry_T_59 = mux(_masked_entry_T_47, UInt<1>(0h1), _masked_entry_T_58)
node masked_entry_3 = mux(_masked_entry_T_46, UInt<1>(0h0), _masked_entry_T_59)
node _alloc_entry_T_6 = dshr(allocatable_slots_3, masked_entry_3)
node _alloc_entry_T_7 = bits(_alloc_entry_T_6, 0, 0)
node alloc_entry_3 = mux(_alloc_entry_T_7, masked_entry_3, first_entry_3)
node _f3_meta_allocate_3_valid_T = neq(allocatable_slots_3, UInt<1>(0h0))
connect f3_meta.allocate[3].valid, _f3_meta_allocate_3_valid_T
connect f3_meta.allocate[3].bits, alloc_entry_3
node _update_was_taken_T_6 = eq(s1_update.bits.cfi_idx.bits, UInt<2>(0h3))
node _update_was_taken_T_7 = and(s1_update.bits.cfi_idx.valid, _update_was_taken_T_6)
node update_was_taken_3 = and(_update_was_taken_T_7, s1_update.bits.cfi_taken)
node _T_131 = bits(s1_update.bits.br_mask, 3, 3)
node _T_132 = and(_T_131, s1_update.valid)
node _T_133 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update)
node _T_134 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0))
node _T_135 = or(_T_133, _T_134)
node _T_136 = eq(_T_135, UInt<1>(0h0))
node _T_137 = and(_T_132, _T_136)
when _T_137 :
when s1_update_meta.provider[3].valid :
connect s1_update_mask[s1_update_meta.provider[3].bits][3], UInt<1>(0h1)
connect s1_update_u_mask[s1_update_meta.provider[3].bits][3], UInt<1>(0h1)
node _new_u_T_33 = bits(s1_update_mispredict_mask, 3, 3)
node _new_u_T_34 = eq(s1_update_meta.alt_differs[3], UInt<1>(0h0))
node _new_u_T_35 = eq(s1_update_meta.provider_u[3], UInt<1>(0h0))
node _new_u_T_36 = sub(s1_update_meta.provider_u[3], UInt<1>(0h1))
node _new_u_T_37 = tail(_new_u_T_36, 1)
node _new_u_T_38 = mux(_new_u_T_35, UInt<1>(0h0), _new_u_T_37)
node _new_u_T_39 = eq(s1_update_meta.provider_u[3], UInt<2>(0h3))
node _new_u_T_40 = add(s1_update_meta.provider_u[3], UInt<1>(0h1))
node _new_u_T_41 = tail(_new_u_T_40, 1)
node _new_u_T_42 = mux(_new_u_T_39, UInt<2>(0h3), _new_u_T_41)
node _new_u_T_43 = mux(_new_u_T_33, _new_u_T_38, _new_u_T_42)
node new_u_3 = mux(_new_u_T_34, s1_update_meta.provider_u[3], _new_u_T_43)
connect s1_update_u[s1_update_meta.provider[3].bits][3], new_u_3
connect s1_update_taken[s1_update_meta.provider[3].bits][3], update_was_taken_3
connect s1_update_old_ctr[s1_update_meta.provider[3].bits][3], s1_update_meta.provider_ctr[3]
connect s1_update_alloc[s1_update_meta.provider[3].bits][3], UInt<1>(0h0)
node _T_138 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update)
node _T_139 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0))
node _T_140 = or(_T_138, _T_139)
node _T_141 = eq(_T_140, UInt<1>(0h0))
node _T_142 = and(s1_update.valid, _T_141)
node _T_143 = and(_T_142, s1_update.bits.cfi_mispredicted)
node _T_144 = and(_T_143, s1_update.bits.cfi_idx.valid)
when _T_144 :
when s1_update_meta.allocate[s1_update.bits.cfi_idx.bits].valid :
connect s1_update_mask[s1_update_meta.allocate[s1_update.bits.cfi_idx.bits].bits][s1_update.bits.cfi_idx.bits], UInt<1>(0h1)
connect s1_update_taken[s1_update_meta.allocate[s1_update.bits.cfi_idx.bits].bits][s1_update.bits.cfi_idx.bits], s1_update.bits.cfi_taken
connect s1_update_alloc[s1_update_meta.allocate[s1_update.bits.cfi_idx.bits].bits][s1_update.bits.cfi_idx.bits], UInt<1>(0h1)
connect s1_update_u_mask[s1_update_meta.allocate[s1_update.bits.cfi_idx.bits].bits][s1_update.bits.cfi_idx.bits], UInt<1>(0h1)
connect s1_update_u[s1_update_meta.allocate[s1_update.bits.cfi_idx.bits].bits][s1_update.bits.cfi_idx.bits], UInt<1>(0h0)
else :
node _decr_mask_T = dshl(UInt<1>(0h1), s1_update_meta.provider[s1_update.bits.cfi_idx.bits].bits)
node _decr_mask_T_1 = dshr(_decr_mask_T, UInt<1>(0h0))
node _decr_mask_T_2 = dshr(_decr_mask_T, UInt<1>(0h1))
node _decr_mask_T_3 = dshr(_decr_mask_T, UInt<2>(0h2))
node _decr_mask_T_4 = dshr(_decr_mask_T, UInt<2>(0h3))
node _decr_mask_T_5 = dshr(_decr_mask_T, UInt<3>(0h4))
node _decr_mask_T_6 = dshr(_decr_mask_T, UInt<3>(0h5))
node _decr_mask_T_7 = dshr(_decr_mask_T, UInt<3>(0h6))
node _decr_mask_T_8 = dshr(_decr_mask_T, UInt<3>(0h7))
node _decr_mask_T_9 = or(_decr_mask_T_1, _decr_mask_T_2)
node _decr_mask_T_10 = or(_decr_mask_T_9, _decr_mask_T_3)
node _decr_mask_T_11 = or(_decr_mask_T_10, _decr_mask_T_4)
node _decr_mask_T_12 = or(_decr_mask_T_11, _decr_mask_T_5)
node _decr_mask_T_13 = or(_decr_mask_T_12, _decr_mask_T_6)
node _decr_mask_T_14 = or(_decr_mask_T_13, _decr_mask_T_7)
node _decr_mask_T_15 = or(_decr_mask_T_14, _decr_mask_T_8)
node _decr_mask_T_16 = not(_decr_mask_T_15)
node decr_mask = mux(s1_update_meta.provider[s1_update.bits.cfi_idx.bits].valid, _decr_mask_T_16, UInt<1>(0h0))
node _T_145 = bits(decr_mask, 0, 0)
when _T_145 :
connect s1_update_u_mask[0][s1_update.bits.cfi_idx.bits], UInt<1>(0h1)
connect s1_update_u[0][s1_update.bits.cfi_idx.bits], UInt<1>(0h0)
node _T_146 = bits(decr_mask, 1, 1)
when _T_146 :
connect s1_update_u_mask[1][s1_update.bits.cfi_idx.bits], UInt<1>(0h1)
connect s1_update_u[1][s1_update.bits.cfi_idx.bits], UInt<1>(0h0)
node _T_147 = bits(decr_mask, 2, 2)
when _T_147 :
connect s1_update_u_mask[2][s1_update.bits.cfi_idx.bits], UInt<1>(0h1)
connect s1_update_u[2][s1_update.bits.cfi_idx.bits], UInt<1>(0h0)
node _T_148 = bits(decr_mask, 3, 3)
when _T_148 :
connect s1_update_u_mask[3][s1_update.bits.cfi_idx.bits], UInt<1>(0h1)
connect s1_update_u[3][s1_update.bits.cfi_idx.bits], UInt<1>(0h0)
node _T_149 = bits(decr_mask, 4, 4)
when _T_149 :
connect s1_update_u_mask[4][s1_update.bits.cfi_idx.bits], UInt<1>(0h1)
connect s1_update_u[4][s1_update.bits.cfi_idx.bits], UInt<1>(0h0)
node _T_150 = bits(decr_mask, 5, 5)
when _T_150 :
connect s1_update_u_mask[5][s1_update.bits.cfi_idx.bits], UInt<1>(0h1)
connect s1_update_u[5][s1_update.bits.cfi_idx.bits], UInt<1>(0h0)
reg tt_0_1_io_update_mask_0_REG : UInt<1>, clock
connect tt_0_1_io_update_mask_0_REG, s1_update_mask[0][0]
connect tt_0_1.io.update_mask[0], tt_0_1_io_update_mask_0_REG
reg tt_0_1_io_update_taken_0_REG : UInt<1>, clock
connect tt_0_1_io_update_taken_0_REG, s1_update_taken[0][0]
connect tt_0_1.io.update_taken[0], tt_0_1_io_update_taken_0_REG
reg tt_0_1_io_update_alloc_0_REG : UInt<1>, clock
connect tt_0_1_io_update_alloc_0_REG, s1_update_alloc[0][0]
connect tt_0_1.io.update_alloc[0], tt_0_1_io_update_alloc_0_REG
reg tt_0_1_io_update_old_ctr_0_REG : UInt, clock
connect tt_0_1_io_update_old_ctr_0_REG, s1_update_old_ctr[0][0]
connect tt_0_1.io.update_old_ctr[0], tt_0_1_io_update_old_ctr_0_REG
reg tt_0_1_io_update_u_mask_0_REG : UInt, clock
connect tt_0_1_io_update_u_mask_0_REG, s1_update_u_mask[0][0]
connect tt_0_1.io.update_u_mask[0], tt_0_1_io_update_u_mask_0_REG
reg tt_0_1_io_update_u_0_REG : UInt, clock
connect tt_0_1_io_update_u_0_REG, s1_update_u[0][0]
connect tt_0_1.io.update_u[0], tt_0_1_io_update_u_0_REG
reg tt_0_1_io_update_mask_1_REG : UInt<1>, clock
connect tt_0_1_io_update_mask_1_REG, s1_update_mask[0][1]
connect tt_0_1.io.update_mask[1], tt_0_1_io_update_mask_1_REG
reg tt_0_1_io_update_taken_1_REG : UInt<1>, clock
connect tt_0_1_io_update_taken_1_REG, s1_update_taken[0][1]
connect tt_0_1.io.update_taken[1], tt_0_1_io_update_taken_1_REG
reg tt_0_1_io_update_alloc_1_REG : UInt<1>, clock
connect tt_0_1_io_update_alloc_1_REG, s1_update_alloc[0][1]
connect tt_0_1.io.update_alloc[1], tt_0_1_io_update_alloc_1_REG
reg tt_0_1_io_update_old_ctr_1_REG : UInt, clock
connect tt_0_1_io_update_old_ctr_1_REG, s1_update_old_ctr[0][1]
connect tt_0_1.io.update_old_ctr[1], tt_0_1_io_update_old_ctr_1_REG
reg tt_0_1_io_update_u_mask_1_REG : UInt, clock
connect tt_0_1_io_update_u_mask_1_REG, s1_update_u_mask[0][1]
connect tt_0_1.io.update_u_mask[1], tt_0_1_io_update_u_mask_1_REG
reg tt_0_1_io_update_u_1_REG : UInt, clock
connect tt_0_1_io_update_u_1_REG, s1_update_u[0][1]
connect tt_0_1.io.update_u[1], tt_0_1_io_update_u_1_REG
reg tt_0_1_io_update_mask_2_REG : UInt<1>, clock
connect tt_0_1_io_update_mask_2_REG, s1_update_mask[0][2]
connect tt_0_1.io.update_mask[2], tt_0_1_io_update_mask_2_REG
reg tt_0_1_io_update_taken_2_REG : UInt<1>, clock
connect tt_0_1_io_update_taken_2_REG, s1_update_taken[0][2]
connect tt_0_1.io.update_taken[2], tt_0_1_io_update_taken_2_REG
reg tt_0_1_io_update_alloc_2_REG : UInt<1>, clock
connect tt_0_1_io_update_alloc_2_REG, s1_update_alloc[0][2]
connect tt_0_1.io.update_alloc[2], tt_0_1_io_update_alloc_2_REG
reg tt_0_1_io_update_old_ctr_2_REG : UInt, clock
connect tt_0_1_io_update_old_ctr_2_REG, s1_update_old_ctr[0][2]
connect tt_0_1.io.update_old_ctr[2], tt_0_1_io_update_old_ctr_2_REG
reg tt_0_1_io_update_u_mask_2_REG : UInt, clock
connect tt_0_1_io_update_u_mask_2_REG, s1_update_u_mask[0][2]
connect tt_0_1.io.update_u_mask[2], tt_0_1_io_update_u_mask_2_REG
reg tt_0_1_io_update_u_2_REG : UInt, clock
connect tt_0_1_io_update_u_2_REG, s1_update_u[0][2]
connect tt_0_1.io.update_u[2], tt_0_1_io_update_u_2_REG
reg tt_0_1_io_update_mask_3_REG : UInt<1>, clock
connect tt_0_1_io_update_mask_3_REG, s1_update_mask[0][3]
connect tt_0_1.io.update_mask[3], tt_0_1_io_update_mask_3_REG
reg tt_0_1_io_update_taken_3_REG : UInt<1>, clock
connect tt_0_1_io_update_taken_3_REG, s1_update_taken[0][3]
connect tt_0_1.io.update_taken[3], tt_0_1_io_update_taken_3_REG
reg tt_0_1_io_update_alloc_3_REG : UInt<1>, clock
connect tt_0_1_io_update_alloc_3_REG, s1_update_alloc[0][3]
connect tt_0_1.io.update_alloc[3], tt_0_1_io_update_alloc_3_REG
reg tt_0_1_io_update_old_ctr_3_REG : UInt, clock
connect tt_0_1_io_update_old_ctr_3_REG, s1_update_old_ctr[0][3]
connect tt_0_1.io.update_old_ctr[3], tt_0_1_io_update_old_ctr_3_REG
reg tt_0_1_io_update_u_mask_3_REG : UInt, clock
connect tt_0_1_io_update_u_mask_3_REG, s1_update_u_mask[0][3]
connect tt_0_1.io.update_u_mask[3], tt_0_1_io_update_u_mask_3_REG
reg tt_0_1_io_update_u_3_REG : UInt, clock
connect tt_0_1_io_update_u_3_REG, s1_update_u[0][3]
connect tt_0_1.io.update_u[3], tt_0_1_io_update_u_3_REG
reg tt_0_1_io_update_pc_REG : UInt, clock
connect tt_0_1_io_update_pc_REG, s1_update.bits.pc
connect tt_0_1.io.update_pc, tt_0_1_io_update_pc_REG
reg tt_0_1_io_update_hist_REG : UInt, clock
connect tt_0_1_io_update_hist_REG, s1_update.bits.ghist
connect tt_0_1.io.update_hist, tt_0_1_io_update_hist_REG
reg tt_1_1_io_update_mask_0_REG : UInt<1>, clock
connect tt_1_1_io_update_mask_0_REG, s1_update_mask[1][0]
connect tt_1_1.io.update_mask[0], tt_1_1_io_update_mask_0_REG
reg tt_1_1_io_update_taken_0_REG : UInt<1>, clock
connect tt_1_1_io_update_taken_0_REG, s1_update_taken[1][0]
connect tt_1_1.io.update_taken[0], tt_1_1_io_update_taken_0_REG
reg tt_1_1_io_update_alloc_0_REG : UInt<1>, clock
connect tt_1_1_io_update_alloc_0_REG, s1_update_alloc[1][0]
connect tt_1_1.io.update_alloc[0], tt_1_1_io_update_alloc_0_REG
reg tt_1_1_io_update_old_ctr_0_REG : UInt, clock
connect tt_1_1_io_update_old_ctr_0_REG, s1_update_old_ctr[1][0]
connect tt_1_1.io.update_old_ctr[0], tt_1_1_io_update_old_ctr_0_REG
reg tt_1_1_io_update_u_mask_0_REG : UInt, clock
connect tt_1_1_io_update_u_mask_0_REG, s1_update_u_mask[1][0]
connect tt_1_1.io.update_u_mask[0], tt_1_1_io_update_u_mask_0_REG
reg tt_1_1_io_update_u_0_REG : UInt, clock
connect tt_1_1_io_update_u_0_REG, s1_update_u[1][0]
connect tt_1_1.io.update_u[0], tt_1_1_io_update_u_0_REG
reg tt_1_1_io_update_mask_1_REG : UInt<1>, clock
connect tt_1_1_io_update_mask_1_REG, s1_update_mask[1][1]
connect tt_1_1.io.update_mask[1], tt_1_1_io_update_mask_1_REG
reg tt_1_1_io_update_taken_1_REG : UInt<1>, clock
connect tt_1_1_io_update_taken_1_REG, s1_update_taken[1][1]
connect tt_1_1.io.update_taken[1], tt_1_1_io_update_taken_1_REG
reg tt_1_1_io_update_alloc_1_REG : UInt<1>, clock
connect tt_1_1_io_update_alloc_1_REG, s1_update_alloc[1][1]
connect tt_1_1.io.update_alloc[1], tt_1_1_io_update_alloc_1_REG
reg tt_1_1_io_update_old_ctr_1_REG : UInt, clock
connect tt_1_1_io_update_old_ctr_1_REG, s1_update_old_ctr[1][1]
connect tt_1_1.io.update_old_ctr[1], tt_1_1_io_update_old_ctr_1_REG
reg tt_1_1_io_update_u_mask_1_REG : UInt, clock
connect tt_1_1_io_update_u_mask_1_REG, s1_update_u_mask[1][1]
connect tt_1_1.io.update_u_mask[1], tt_1_1_io_update_u_mask_1_REG
reg tt_1_1_io_update_u_1_REG : UInt, clock
connect tt_1_1_io_update_u_1_REG, s1_update_u[1][1]
connect tt_1_1.io.update_u[1], tt_1_1_io_update_u_1_REG
reg tt_1_1_io_update_mask_2_REG : UInt<1>, clock
connect tt_1_1_io_update_mask_2_REG, s1_update_mask[1][2]
connect tt_1_1.io.update_mask[2], tt_1_1_io_update_mask_2_REG
reg tt_1_1_io_update_taken_2_REG : UInt<1>, clock
connect tt_1_1_io_update_taken_2_REG, s1_update_taken[1][2]
connect tt_1_1.io.update_taken[2], tt_1_1_io_update_taken_2_REG
reg tt_1_1_io_update_alloc_2_REG : UInt<1>, clock
connect tt_1_1_io_update_alloc_2_REG, s1_update_alloc[1][2]
connect tt_1_1.io.update_alloc[2], tt_1_1_io_update_alloc_2_REG
reg tt_1_1_io_update_old_ctr_2_REG : UInt, clock
connect tt_1_1_io_update_old_ctr_2_REG, s1_update_old_ctr[1][2]
connect tt_1_1.io.update_old_ctr[2], tt_1_1_io_update_old_ctr_2_REG
reg tt_1_1_io_update_u_mask_2_REG : UInt, clock
connect tt_1_1_io_update_u_mask_2_REG, s1_update_u_mask[1][2]
connect tt_1_1.io.update_u_mask[2], tt_1_1_io_update_u_mask_2_REG
reg tt_1_1_io_update_u_2_REG : UInt, clock
connect tt_1_1_io_update_u_2_REG, s1_update_u[1][2]
connect tt_1_1.io.update_u[2], tt_1_1_io_update_u_2_REG
reg tt_1_1_io_update_mask_3_REG : UInt<1>, clock
connect tt_1_1_io_update_mask_3_REG, s1_update_mask[1][3]
connect tt_1_1.io.update_mask[3], tt_1_1_io_update_mask_3_REG
reg tt_1_1_io_update_taken_3_REG : UInt<1>, clock
connect tt_1_1_io_update_taken_3_REG, s1_update_taken[1][3]
connect tt_1_1.io.update_taken[3], tt_1_1_io_update_taken_3_REG
reg tt_1_1_io_update_alloc_3_REG : UInt<1>, clock
connect tt_1_1_io_update_alloc_3_REG, s1_update_alloc[1][3]
connect tt_1_1.io.update_alloc[3], tt_1_1_io_update_alloc_3_REG
reg tt_1_1_io_update_old_ctr_3_REG : UInt, clock
connect tt_1_1_io_update_old_ctr_3_REG, s1_update_old_ctr[1][3]
connect tt_1_1.io.update_old_ctr[3], tt_1_1_io_update_old_ctr_3_REG
reg tt_1_1_io_update_u_mask_3_REG : UInt, clock
connect tt_1_1_io_update_u_mask_3_REG, s1_update_u_mask[1][3]
connect tt_1_1.io.update_u_mask[3], tt_1_1_io_update_u_mask_3_REG
reg tt_1_1_io_update_u_3_REG : UInt, clock
connect tt_1_1_io_update_u_3_REG, s1_update_u[1][3]
connect tt_1_1.io.update_u[3], tt_1_1_io_update_u_3_REG
reg tt_1_1_io_update_pc_REG : UInt, clock
connect tt_1_1_io_update_pc_REG, s1_update.bits.pc
connect tt_1_1.io.update_pc, tt_1_1_io_update_pc_REG
reg tt_1_1_io_update_hist_REG : UInt, clock
connect tt_1_1_io_update_hist_REG, s1_update.bits.ghist
connect tt_1_1.io.update_hist, tt_1_1_io_update_hist_REG
reg tt_2_1_io_update_mask_0_REG : UInt<1>, clock
connect tt_2_1_io_update_mask_0_REG, s1_update_mask[2][0]
connect tt_2_1.io.update_mask[0], tt_2_1_io_update_mask_0_REG
reg tt_2_1_io_update_taken_0_REG : UInt<1>, clock
connect tt_2_1_io_update_taken_0_REG, s1_update_taken[2][0]
connect tt_2_1.io.update_taken[0], tt_2_1_io_update_taken_0_REG
reg tt_2_1_io_update_alloc_0_REG : UInt<1>, clock
connect tt_2_1_io_update_alloc_0_REG, s1_update_alloc[2][0]
connect tt_2_1.io.update_alloc[0], tt_2_1_io_update_alloc_0_REG
reg tt_2_1_io_update_old_ctr_0_REG : UInt, clock
connect tt_2_1_io_update_old_ctr_0_REG, s1_update_old_ctr[2][0]
connect tt_2_1.io.update_old_ctr[0], tt_2_1_io_update_old_ctr_0_REG
reg tt_2_1_io_update_u_mask_0_REG : UInt, clock
connect tt_2_1_io_update_u_mask_0_REG, s1_update_u_mask[2][0]
connect tt_2_1.io.update_u_mask[0], tt_2_1_io_update_u_mask_0_REG
reg tt_2_1_io_update_u_0_REG : UInt, clock
connect tt_2_1_io_update_u_0_REG, s1_update_u[2][0]
connect tt_2_1.io.update_u[0], tt_2_1_io_update_u_0_REG
reg tt_2_1_io_update_mask_1_REG : UInt<1>, clock
connect tt_2_1_io_update_mask_1_REG, s1_update_mask[2][1]
connect tt_2_1.io.update_mask[1], tt_2_1_io_update_mask_1_REG
reg tt_2_1_io_update_taken_1_REG : UInt<1>, clock
connect tt_2_1_io_update_taken_1_REG, s1_update_taken[2][1]
connect tt_2_1.io.update_taken[1], tt_2_1_io_update_taken_1_REG
reg tt_2_1_io_update_alloc_1_REG : UInt<1>, clock
connect tt_2_1_io_update_alloc_1_REG, s1_update_alloc[2][1]
connect tt_2_1.io.update_alloc[1], tt_2_1_io_update_alloc_1_REG
reg tt_2_1_io_update_old_ctr_1_REG : UInt, clock
connect tt_2_1_io_update_old_ctr_1_REG, s1_update_old_ctr[2][1]
connect tt_2_1.io.update_old_ctr[1], tt_2_1_io_update_old_ctr_1_REG
reg tt_2_1_io_update_u_mask_1_REG : UInt, clock
connect tt_2_1_io_update_u_mask_1_REG, s1_update_u_mask[2][1]
connect tt_2_1.io.update_u_mask[1], tt_2_1_io_update_u_mask_1_REG
reg tt_2_1_io_update_u_1_REG : UInt, clock
connect tt_2_1_io_update_u_1_REG, s1_update_u[2][1]
connect tt_2_1.io.update_u[1], tt_2_1_io_update_u_1_REG
reg tt_2_1_io_update_mask_2_REG : UInt<1>, clock
connect tt_2_1_io_update_mask_2_REG, s1_update_mask[2][2]
connect tt_2_1.io.update_mask[2], tt_2_1_io_update_mask_2_REG
reg tt_2_1_io_update_taken_2_REG : UInt<1>, clock
connect tt_2_1_io_update_taken_2_REG, s1_update_taken[2][2]
connect tt_2_1.io.update_taken[2], tt_2_1_io_update_taken_2_REG
reg tt_2_1_io_update_alloc_2_REG : UInt<1>, clock
connect tt_2_1_io_update_alloc_2_REG, s1_update_alloc[2][2]
connect tt_2_1.io.update_alloc[2], tt_2_1_io_update_alloc_2_REG
reg tt_2_1_io_update_old_ctr_2_REG : UInt, clock
connect tt_2_1_io_update_old_ctr_2_REG, s1_update_old_ctr[2][2]
connect tt_2_1.io.update_old_ctr[2], tt_2_1_io_update_old_ctr_2_REG
reg tt_2_1_io_update_u_mask_2_REG : UInt, clock
connect tt_2_1_io_update_u_mask_2_REG, s1_update_u_mask[2][2]
connect tt_2_1.io.update_u_mask[2], tt_2_1_io_update_u_mask_2_REG
reg tt_2_1_io_update_u_2_REG : UInt, clock
connect tt_2_1_io_update_u_2_REG, s1_update_u[2][2]
connect tt_2_1.io.update_u[2], tt_2_1_io_update_u_2_REG
reg tt_2_1_io_update_mask_3_REG : UInt<1>, clock
connect tt_2_1_io_update_mask_3_REG, s1_update_mask[2][3]
connect tt_2_1.io.update_mask[3], tt_2_1_io_update_mask_3_REG
reg tt_2_1_io_update_taken_3_REG : UInt<1>, clock
connect tt_2_1_io_update_taken_3_REG, s1_update_taken[2][3]
connect tt_2_1.io.update_taken[3], tt_2_1_io_update_taken_3_REG
reg tt_2_1_io_update_alloc_3_REG : UInt<1>, clock
connect tt_2_1_io_update_alloc_3_REG, s1_update_alloc[2][3]
connect tt_2_1.io.update_alloc[3], tt_2_1_io_update_alloc_3_REG
reg tt_2_1_io_update_old_ctr_3_REG : UInt, clock
connect tt_2_1_io_update_old_ctr_3_REG, s1_update_old_ctr[2][3]
connect tt_2_1.io.update_old_ctr[3], tt_2_1_io_update_old_ctr_3_REG
reg tt_2_1_io_update_u_mask_3_REG : UInt, clock
connect tt_2_1_io_update_u_mask_3_REG, s1_update_u_mask[2][3]
connect tt_2_1.io.update_u_mask[3], tt_2_1_io_update_u_mask_3_REG
reg tt_2_1_io_update_u_3_REG : UInt, clock
connect tt_2_1_io_update_u_3_REG, s1_update_u[2][3]
connect tt_2_1.io.update_u[3], tt_2_1_io_update_u_3_REG
reg tt_2_1_io_update_pc_REG : UInt, clock
connect tt_2_1_io_update_pc_REG, s1_update.bits.pc
connect tt_2_1.io.update_pc, tt_2_1_io_update_pc_REG
reg tt_2_1_io_update_hist_REG : UInt, clock
connect tt_2_1_io_update_hist_REG, s1_update.bits.ghist
connect tt_2_1.io.update_hist, tt_2_1_io_update_hist_REG
reg tt_3_1_io_update_mask_0_REG : UInt<1>, clock
connect tt_3_1_io_update_mask_0_REG, s1_update_mask[3][0]
connect tt_3_1.io.update_mask[0], tt_3_1_io_update_mask_0_REG
reg tt_3_1_io_update_taken_0_REG : UInt<1>, clock
connect tt_3_1_io_update_taken_0_REG, s1_update_taken[3][0]
connect tt_3_1.io.update_taken[0], tt_3_1_io_update_taken_0_REG
reg tt_3_1_io_update_alloc_0_REG : UInt<1>, clock
connect tt_3_1_io_update_alloc_0_REG, s1_update_alloc[3][0]
connect tt_3_1.io.update_alloc[0], tt_3_1_io_update_alloc_0_REG
reg tt_3_1_io_update_old_ctr_0_REG : UInt, clock
connect tt_3_1_io_update_old_ctr_0_REG, s1_update_old_ctr[3][0]
connect tt_3_1.io.update_old_ctr[0], tt_3_1_io_update_old_ctr_0_REG
reg tt_3_1_io_update_u_mask_0_REG : UInt, clock
connect tt_3_1_io_update_u_mask_0_REG, s1_update_u_mask[3][0]
connect tt_3_1.io.update_u_mask[0], tt_3_1_io_update_u_mask_0_REG
reg tt_3_1_io_update_u_0_REG : UInt, clock
connect tt_3_1_io_update_u_0_REG, s1_update_u[3][0]
connect tt_3_1.io.update_u[0], tt_3_1_io_update_u_0_REG
reg tt_3_1_io_update_mask_1_REG : UInt<1>, clock
connect tt_3_1_io_update_mask_1_REG, s1_update_mask[3][1]
connect tt_3_1.io.update_mask[1], tt_3_1_io_update_mask_1_REG
reg tt_3_1_io_update_taken_1_REG : UInt<1>, clock
connect tt_3_1_io_update_taken_1_REG, s1_update_taken[3][1]
connect tt_3_1.io.update_taken[1], tt_3_1_io_update_taken_1_REG
reg tt_3_1_io_update_alloc_1_REG : UInt<1>, clock
connect tt_3_1_io_update_alloc_1_REG, s1_update_alloc[3][1]
connect tt_3_1.io.update_alloc[1], tt_3_1_io_update_alloc_1_REG
reg tt_3_1_io_update_old_ctr_1_REG : UInt, clock
connect tt_3_1_io_update_old_ctr_1_REG, s1_update_old_ctr[3][1]
connect tt_3_1.io.update_old_ctr[1], tt_3_1_io_update_old_ctr_1_REG
reg tt_3_1_io_update_u_mask_1_REG : UInt, clock
connect tt_3_1_io_update_u_mask_1_REG, s1_update_u_mask[3][1]
connect tt_3_1.io.update_u_mask[1], tt_3_1_io_update_u_mask_1_REG
reg tt_3_1_io_update_u_1_REG : UInt, clock
connect tt_3_1_io_update_u_1_REG, s1_update_u[3][1]
connect tt_3_1.io.update_u[1], tt_3_1_io_update_u_1_REG
reg tt_3_1_io_update_mask_2_REG : UInt<1>, clock
connect tt_3_1_io_update_mask_2_REG, s1_update_mask[3][2]
connect tt_3_1.io.update_mask[2], tt_3_1_io_update_mask_2_REG
reg tt_3_1_io_update_taken_2_REG : UInt<1>, clock
connect tt_3_1_io_update_taken_2_REG, s1_update_taken[3][2]
connect tt_3_1.io.update_taken[2], tt_3_1_io_update_taken_2_REG
reg tt_3_1_io_update_alloc_2_REG : UInt<1>, clock
connect tt_3_1_io_update_alloc_2_REG, s1_update_alloc[3][2]
connect tt_3_1.io.update_alloc[2], tt_3_1_io_update_alloc_2_REG
reg tt_3_1_io_update_old_ctr_2_REG : UInt, clock
connect tt_3_1_io_update_old_ctr_2_REG, s1_update_old_ctr[3][2]
connect tt_3_1.io.update_old_ctr[2], tt_3_1_io_update_old_ctr_2_REG
reg tt_3_1_io_update_u_mask_2_REG : UInt, clock
connect tt_3_1_io_update_u_mask_2_REG, s1_update_u_mask[3][2]
connect tt_3_1.io.update_u_mask[2], tt_3_1_io_update_u_mask_2_REG
reg tt_3_1_io_update_u_2_REG : UInt, clock
connect tt_3_1_io_update_u_2_REG, s1_update_u[3][2]
connect tt_3_1.io.update_u[2], tt_3_1_io_update_u_2_REG
reg tt_3_1_io_update_mask_3_REG : UInt<1>, clock
connect tt_3_1_io_update_mask_3_REG, s1_update_mask[3][3]
connect tt_3_1.io.update_mask[3], tt_3_1_io_update_mask_3_REG
reg tt_3_1_io_update_taken_3_REG : UInt<1>, clock
connect tt_3_1_io_update_taken_3_REG, s1_update_taken[3][3]
connect tt_3_1.io.update_taken[3], tt_3_1_io_update_taken_3_REG
reg tt_3_1_io_update_alloc_3_REG : UInt<1>, clock
connect tt_3_1_io_update_alloc_3_REG, s1_update_alloc[3][3]
connect tt_3_1.io.update_alloc[3], tt_3_1_io_update_alloc_3_REG
reg tt_3_1_io_update_old_ctr_3_REG : UInt, clock
connect tt_3_1_io_update_old_ctr_3_REG, s1_update_old_ctr[3][3]
connect tt_3_1.io.update_old_ctr[3], tt_3_1_io_update_old_ctr_3_REG
reg tt_3_1_io_update_u_mask_3_REG : UInt, clock
connect tt_3_1_io_update_u_mask_3_REG, s1_update_u_mask[3][3]
connect tt_3_1.io.update_u_mask[3], tt_3_1_io_update_u_mask_3_REG
reg tt_3_1_io_update_u_3_REG : UInt, clock
connect tt_3_1_io_update_u_3_REG, s1_update_u[3][3]
connect tt_3_1.io.update_u[3], tt_3_1_io_update_u_3_REG
reg tt_3_1_io_update_pc_REG : UInt, clock
connect tt_3_1_io_update_pc_REG, s1_update.bits.pc
connect tt_3_1.io.update_pc, tt_3_1_io_update_pc_REG
reg tt_3_1_io_update_hist_REG : UInt, clock
connect tt_3_1_io_update_hist_REG, s1_update.bits.ghist
connect tt_3_1.io.update_hist, tt_3_1_io_update_hist_REG
reg tt_4_1_io_update_mask_0_REG : UInt<1>, clock
connect tt_4_1_io_update_mask_0_REG, s1_update_mask[4][0]
connect tt_4_1.io.update_mask[0], tt_4_1_io_update_mask_0_REG
reg tt_4_1_io_update_taken_0_REG : UInt<1>, clock
connect tt_4_1_io_update_taken_0_REG, s1_update_taken[4][0]
connect tt_4_1.io.update_taken[0], tt_4_1_io_update_taken_0_REG
reg tt_4_1_io_update_alloc_0_REG : UInt<1>, clock
connect tt_4_1_io_update_alloc_0_REG, s1_update_alloc[4][0]
connect tt_4_1.io.update_alloc[0], tt_4_1_io_update_alloc_0_REG
reg tt_4_1_io_update_old_ctr_0_REG : UInt, clock
connect tt_4_1_io_update_old_ctr_0_REG, s1_update_old_ctr[4][0]
connect tt_4_1.io.update_old_ctr[0], tt_4_1_io_update_old_ctr_0_REG
reg tt_4_1_io_update_u_mask_0_REG : UInt, clock
connect tt_4_1_io_update_u_mask_0_REG, s1_update_u_mask[4][0]
connect tt_4_1.io.update_u_mask[0], tt_4_1_io_update_u_mask_0_REG
reg tt_4_1_io_update_u_0_REG : UInt, clock
connect tt_4_1_io_update_u_0_REG, s1_update_u[4][0]
connect tt_4_1.io.update_u[0], tt_4_1_io_update_u_0_REG
reg tt_4_1_io_update_mask_1_REG : UInt<1>, clock
connect tt_4_1_io_update_mask_1_REG, s1_update_mask[4][1]
connect tt_4_1.io.update_mask[1], tt_4_1_io_update_mask_1_REG
reg tt_4_1_io_update_taken_1_REG : UInt<1>, clock
connect tt_4_1_io_update_taken_1_REG, s1_update_taken[4][1]
connect tt_4_1.io.update_taken[1], tt_4_1_io_update_taken_1_REG
reg tt_4_1_io_update_alloc_1_REG : UInt<1>, clock
connect tt_4_1_io_update_alloc_1_REG, s1_update_alloc[4][1]
connect tt_4_1.io.update_alloc[1], tt_4_1_io_update_alloc_1_REG
reg tt_4_1_io_update_old_ctr_1_REG : UInt, clock
connect tt_4_1_io_update_old_ctr_1_REG, s1_update_old_ctr[4][1]
connect tt_4_1.io.update_old_ctr[1], tt_4_1_io_update_old_ctr_1_REG
reg tt_4_1_io_update_u_mask_1_REG : UInt, clock
connect tt_4_1_io_update_u_mask_1_REG, s1_update_u_mask[4][1]
connect tt_4_1.io.update_u_mask[1], tt_4_1_io_update_u_mask_1_REG
reg tt_4_1_io_update_u_1_REG : UInt, clock
connect tt_4_1_io_update_u_1_REG, s1_update_u[4][1]
connect tt_4_1.io.update_u[1], tt_4_1_io_update_u_1_REG
reg tt_4_1_io_update_mask_2_REG : UInt<1>, clock
connect tt_4_1_io_update_mask_2_REG, s1_update_mask[4][2]
connect tt_4_1.io.update_mask[2], tt_4_1_io_update_mask_2_REG
reg tt_4_1_io_update_taken_2_REG : UInt<1>, clock
connect tt_4_1_io_update_taken_2_REG, s1_update_taken[4][2]
connect tt_4_1.io.update_taken[2], tt_4_1_io_update_taken_2_REG
reg tt_4_1_io_update_alloc_2_REG : UInt<1>, clock
connect tt_4_1_io_update_alloc_2_REG, s1_update_alloc[4][2]
connect tt_4_1.io.update_alloc[2], tt_4_1_io_update_alloc_2_REG
reg tt_4_1_io_update_old_ctr_2_REG : UInt, clock
connect tt_4_1_io_update_old_ctr_2_REG, s1_update_old_ctr[4][2]
connect tt_4_1.io.update_old_ctr[2], tt_4_1_io_update_old_ctr_2_REG
reg tt_4_1_io_update_u_mask_2_REG : UInt, clock
connect tt_4_1_io_update_u_mask_2_REG, s1_update_u_mask[4][2]
connect tt_4_1.io.update_u_mask[2], tt_4_1_io_update_u_mask_2_REG
reg tt_4_1_io_update_u_2_REG : UInt, clock
connect tt_4_1_io_update_u_2_REG, s1_update_u[4][2]
connect tt_4_1.io.update_u[2], tt_4_1_io_update_u_2_REG
reg tt_4_1_io_update_mask_3_REG : UInt<1>, clock
connect tt_4_1_io_update_mask_3_REG, s1_update_mask[4][3]
connect tt_4_1.io.update_mask[3], tt_4_1_io_update_mask_3_REG
reg tt_4_1_io_update_taken_3_REG : UInt<1>, clock
connect tt_4_1_io_update_taken_3_REG, s1_update_taken[4][3]
connect tt_4_1.io.update_taken[3], tt_4_1_io_update_taken_3_REG
reg tt_4_1_io_update_alloc_3_REG : UInt<1>, clock
connect tt_4_1_io_update_alloc_3_REG, s1_update_alloc[4][3]
connect tt_4_1.io.update_alloc[3], tt_4_1_io_update_alloc_3_REG
reg tt_4_1_io_update_old_ctr_3_REG : UInt, clock
connect tt_4_1_io_update_old_ctr_3_REG, s1_update_old_ctr[4][3]
connect tt_4_1.io.update_old_ctr[3], tt_4_1_io_update_old_ctr_3_REG
reg tt_4_1_io_update_u_mask_3_REG : UInt, clock
connect tt_4_1_io_update_u_mask_3_REG, s1_update_u_mask[4][3]
connect tt_4_1.io.update_u_mask[3], tt_4_1_io_update_u_mask_3_REG
reg tt_4_1_io_update_u_3_REG : UInt, clock
connect tt_4_1_io_update_u_3_REG, s1_update_u[4][3]
connect tt_4_1.io.update_u[3], tt_4_1_io_update_u_3_REG
reg tt_4_1_io_update_pc_REG : UInt, clock
connect tt_4_1_io_update_pc_REG, s1_update.bits.pc
connect tt_4_1.io.update_pc, tt_4_1_io_update_pc_REG
reg tt_4_1_io_update_hist_REG : UInt, clock
connect tt_4_1_io_update_hist_REG, s1_update.bits.ghist
connect tt_4_1.io.update_hist, tt_4_1_io_update_hist_REG
reg tt_5_1_io_update_mask_0_REG : UInt<1>, clock
connect tt_5_1_io_update_mask_0_REG, s1_update_mask[5][0]
connect tt_5_1.io.update_mask[0], tt_5_1_io_update_mask_0_REG
reg tt_5_1_io_update_taken_0_REG : UInt<1>, clock
connect tt_5_1_io_update_taken_0_REG, s1_update_taken[5][0]
connect tt_5_1.io.update_taken[0], tt_5_1_io_update_taken_0_REG
reg tt_5_1_io_update_alloc_0_REG : UInt<1>, clock
connect tt_5_1_io_update_alloc_0_REG, s1_update_alloc[5][0]
connect tt_5_1.io.update_alloc[0], tt_5_1_io_update_alloc_0_REG
reg tt_5_1_io_update_old_ctr_0_REG : UInt, clock
connect tt_5_1_io_update_old_ctr_0_REG, s1_update_old_ctr[5][0]
connect tt_5_1.io.update_old_ctr[0], tt_5_1_io_update_old_ctr_0_REG
reg tt_5_1_io_update_u_mask_0_REG : UInt, clock
connect tt_5_1_io_update_u_mask_0_REG, s1_update_u_mask[5][0]
connect tt_5_1.io.update_u_mask[0], tt_5_1_io_update_u_mask_0_REG
reg tt_5_1_io_update_u_0_REG : UInt, clock
connect tt_5_1_io_update_u_0_REG, s1_update_u[5][0]
connect tt_5_1.io.update_u[0], tt_5_1_io_update_u_0_REG
reg tt_5_1_io_update_mask_1_REG : UInt<1>, clock
connect tt_5_1_io_update_mask_1_REG, s1_update_mask[5][1]
connect tt_5_1.io.update_mask[1], tt_5_1_io_update_mask_1_REG
reg tt_5_1_io_update_taken_1_REG : UInt<1>, clock
connect tt_5_1_io_update_taken_1_REG, s1_update_taken[5][1]
connect tt_5_1.io.update_taken[1], tt_5_1_io_update_taken_1_REG
reg tt_5_1_io_update_alloc_1_REG : UInt<1>, clock
connect tt_5_1_io_update_alloc_1_REG, s1_update_alloc[5][1]
connect tt_5_1.io.update_alloc[1], tt_5_1_io_update_alloc_1_REG
reg tt_5_1_io_update_old_ctr_1_REG : UInt, clock
connect tt_5_1_io_update_old_ctr_1_REG, s1_update_old_ctr[5][1]
connect tt_5_1.io.update_old_ctr[1], tt_5_1_io_update_old_ctr_1_REG
reg tt_5_1_io_update_u_mask_1_REG : UInt, clock
connect tt_5_1_io_update_u_mask_1_REG, s1_update_u_mask[5][1]
connect tt_5_1.io.update_u_mask[1], tt_5_1_io_update_u_mask_1_REG
reg tt_5_1_io_update_u_1_REG : UInt, clock
connect tt_5_1_io_update_u_1_REG, s1_update_u[5][1]
connect tt_5_1.io.update_u[1], tt_5_1_io_update_u_1_REG
reg tt_5_1_io_update_mask_2_REG : UInt<1>, clock
connect tt_5_1_io_update_mask_2_REG, s1_update_mask[5][2]
connect tt_5_1.io.update_mask[2], tt_5_1_io_update_mask_2_REG
reg tt_5_1_io_update_taken_2_REG : UInt<1>, clock
connect tt_5_1_io_update_taken_2_REG, s1_update_taken[5][2]
connect tt_5_1.io.update_taken[2], tt_5_1_io_update_taken_2_REG
reg tt_5_1_io_update_alloc_2_REG : UInt<1>, clock
connect tt_5_1_io_update_alloc_2_REG, s1_update_alloc[5][2]
connect tt_5_1.io.update_alloc[2], tt_5_1_io_update_alloc_2_REG
reg tt_5_1_io_update_old_ctr_2_REG : UInt, clock
connect tt_5_1_io_update_old_ctr_2_REG, s1_update_old_ctr[5][2]
connect tt_5_1.io.update_old_ctr[2], tt_5_1_io_update_old_ctr_2_REG
reg tt_5_1_io_update_u_mask_2_REG : UInt, clock
connect tt_5_1_io_update_u_mask_2_REG, s1_update_u_mask[5][2]
connect tt_5_1.io.update_u_mask[2], tt_5_1_io_update_u_mask_2_REG
reg tt_5_1_io_update_u_2_REG : UInt, clock
connect tt_5_1_io_update_u_2_REG, s1_update_u[5][2]
connect tt_5_1.io.update_u[2], tt_5_1_io_update_u_2_REG
reg tt_5_1_io_update_mask_3_REG : UInt<1>, clock
connect tt_5_1_io_update_mask_3_REG, s1_update_mask[5][3]
connect tt_5_1.io.update_mask[3], tt_5_1_io_update_mask_3_REG
reg tt_5_1_io_update_taken_3_REG : UInt<1>, clock
connect tt_5_1_io_update_taken_3_REG, s1_update_taken[5][3]
connect tt_5_1.io.update_taken[3], tt_5_1_io_update_taken_3_REG
reg tt_5_1_io_update_alloc_3_REG : UInt<1>, clock
connect tt_5_1_io_update_alloc_3_REG, s1_update_alloc[5][3]
connect tt_5_1.io.update_alloc[3], tt_5_1_io_update_alloc_3_REG
reg tt_5_1_io_update_old_ctr_3_REG : UInt, clock
connect tt_5_1_io_update_old_ctr_3_REG, s1_update_old_ctr[5][3]
connect tt_5_1.io.update_old_ctr[3], tt_5_1_io_update_old_ctr_3_REG
reg tt_5_1_io_update_u_mask_3_REG : UInt, clock
connect tt_5_1_io_update_u_mask_3_REG, s1_update_u_mask[5][3]
connect tt_5_1.io.update_u_mask[3], tt_5_1_io_update_u_mask_3_REG
reg tt_5_1_io_update_u_3_REG : UInt, clock
connect tt_5_1_io_update_u_3_REG, s1_update_u[5][3]
connect tt_5_1.io.update_u[3], tt_5_1_io_update_u_3_REG
reg tt_5_1_io_update_pc_REG : UInt, clock
connect tt_5_1_io_update_pc_REG, s1_update.bits.pc
connect tt_5_1.io.update_pc, tt_5_1_io_update_pc_REG
reg tt_5_1_io_update_hist_REG : UInt, clock
connect tt_5_1_io_update_hist_REG, s1_update.bits.ghist
connect tt_5_1.io.update_hist, tt_5_1_io_update_hist_REG
node _io_f3_meta_T = cat(f3_meta.allocate[0].valid, f3_meta.allocate[0].bits)
node _io_f3_meta_T_1 = cat(f3_meta.allocate[1].valid, f3_meta.allocate[1].bits)
node _io_f3_meta_T_2 = cat(f3_meta.allocate[2].valid, f3_meta.allocate[2].bits)
node _io_f3_meta_T_3 = cat(f3_meta.allocate[3].valid, f3_meta.allocate[3].bits)
node io_f3_meta_lo = cat(_io_f3_meta_T_1, _io_f3_meta_T)
node io_f3_meta_hi = cat(_io_f3_meta_T_3, _io_f3_meta_T_2)
node _io_f3_meta_T_4 = cat(io_f3_meta_hi, io_f3_meta_lo)
node io_f3_meta_lo_1 = cat(f3_meta.provider_ctr[1], f3_meta.provider_ctr[0])
node io_f3_meta_hi_1 = cat(f3_meta.provider_ctr[3], f3_meta.provider_ctr[2])
node _io_f3_meta_T_5 = cat(io_f3_meta_hi_1, io_f3_meta_lo_1)
node io_f3_meta_lo_2 = cat(f3_meta.provider_u[1], f3_meta.provider_u[0])
node io_f3_meta_hi_2 = cat(f3_meta.provider_u[3], f3_meta.provider_u[2])
node _io_f3_meta_T_6 = cat(io_f3_meta_hi_2, io_f3_meta_lo_2)
node io_f3_meta_lo_3 = cat(f3_meta.alt_differs[1], f3_meta.alt_differs[0])
node io_f3_meta_hi_3 = cat(f3_meta.alt_differs[3], f3_meta.alt_differs[2])
node _io_f3_meta_T_7 = cat(io_f3_meta_hi_3, io_f3_meta_lo_3)
node _io_f3_meta_T_8 = cat(f3_meta.provider[0].valid, f3_meta.provider[0].bits)
node _io_f3_meta_T_9 = cat(f3_meta.provider[1].valid, f3_meta.provider[1].bits)
node _io_f3_meta_T_10 = cat(f3_meta.provider[2].valid, f3_meta.provider[2].bits)
node _io_f3_meta_T_11 = cat(f3_meta.provider[3].valid, f3_meta.provider[3].bits)
node io_f3_meta_lo_4 = cat(_io_f3_meta_T_9, _io_f3_meta_T_8)
node io_f3_meta_hi_4 = cat(_io_f3_meta_T_11, _io_f3_meta_T_10)
node _io_f3_meta_T_12 = cat(io_f3_meta_hi_4, io_f3_meta_lo_4)
node io_f3_meta_lo_5 = cat(_io_f3_meta_T_5, _io_f3_meta_T_4)
node io_f3_meta_hi_hi = cat(_io_f3_meta_T_12, _io_f3_meta_T_7)
node io_f3_meta_hi_5 = cat(io_f3_meta_hi_hi, _io_f3_meta_T_6)
node _io_f3_meta_T_13 = cat(io_f3_meta_hi_5, io_f3_meta_lo_5)
connect io.f3_meta, _io_f3_meta_T_13 | module TageBranchPredictorBank_1( // @[tage.scala:198:7]
input clock, // @[tage.scala:198:7]
input reset, // @[tage.scala:198:7]
input io_f0_valid, // @[predictor.scala:140:14]
input [39:0] io_f0_pc, // @[predictor.scala:140:14]
input [3:0] io_f0_mask, // @[predictor.scala:140:14]
input [63:0] io_f1_ghist, // @[predictor.scala:140:14]
input io_resp_in_0_f1_0_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f1_0_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f1_0_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f1_0_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f1_0_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f1_1_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f1_1_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f1_1_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f1_1_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f1_1_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f1_2_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f1_2_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f1_2_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f1_2_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f1_2_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f1_3_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f1_3_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f1_3_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f1_3_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f1_3_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f2_0_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f2_0_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f2_0_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f2_0_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f2_0_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f2_1_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f2_1_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f2_1_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f2_1_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f2_1_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f2_2_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f2_2_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f2_2_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f2_2_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f2_2_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f2_3_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f2_3_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f2_3_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f2_3_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f2_3_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f3_0_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f3_0_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f3_0_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f3_0_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f3_0_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f3_1_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f3_1_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f3_1_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f3_1_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f3_1_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f3_2_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f3_2_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f3_2_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f3_2_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f3_2_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f3_3_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f3_3_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f3_3_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f3_3_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f3_3_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f1_0_taken, // @[predictor.scala:140:14]
output io_resp_f1_0_is_br, // @[predictor.scala:140:14]
output io_resp_f1_0_is_jal, // @[predictor.scala:140:14]
output io_resp_f1_0_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f1_0_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f1_1_taken, // @[predictor.scala:140:14]
output io_resp_f1_1_is_br, // @[predictor.scala:140:14]
output io_resp_f1_1_is_jal, // @[predictor.scala:140:14]
output io_resp_f1_1_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f1_1_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f1_2_taken, // @[predictor.scala:140:14]
output io_resp_f1_2_is_br, // @[predictor.scala:140:14]
output io_resp_f1_2_is_jal, // @[predictor.scala:140:14]
output io_resp_f1_2_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f1_2_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f1_3_taken, // @[predictor.scala:140:14]
output io_resp_f1_3_is_br, // @[predictor.scala:140:14]
output io_resp_f1_3_is_jal, // @[predictor.scala:140:14]
output io_resp_f1_3_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f1_3_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f2_0_taken, // @[predictor.scala:140:14]
output io_resp_f2_0_is_br, // @[predictor.scala:140:14]
output io_resp_f2_0_is_jal, // @[predictor.scala:140:14]
output io_resp_f2_0_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f2_0_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f2_1_taken, // @[predictor.scala:140:14]
output io_resp_f2_1_is_br, // @[predictor.scala:140:14]
output io_resp_f2_1_is_jal, // @[predictor.scala:140:14]
output io_resp_f2_1_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f2_1_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f2_2_taken, // @[predictor.scala:140:14]
output io_resp_f2_2_is_br, // @[predictor.scala:140:14]
output io_resp_f2_2_is_jal, // @[predictor.scala:140:14]
output io_resp_f2_2_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f2_2_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f2_3_taken, // @[predictor.scala:140:14]
output io_resp_f2_3_is_br, // @[predictor.scala:140:14]
output io_resp_f2_3_is_jal, // @[predictor.scala:140:14]
output io_resp_f2_3_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f2_3_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f3_0_taken, // @[predictor.scala:140:14]
output io_resp_f3_0_is_br, // @[predictor.scala:140:14]
output io_resp_f3_0_is_jal, // @[predictor.scala:140:14]
output io_resp_f3_0_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f3_0_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f3_1_taken, // @[predictor.scala:140:14]
output io_resp_f3_1_is_br, // @[predictor.scala:140:14]
output io_resp_f3_1_is_jal, // @[predictor.scala:140:14]
output io_resp_f3_1_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f3_1_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f3_2_taken, // @[predictor.scala:140:14]
output io_resp_f3_2_is_br, // @[predictor.scala:140:14]
output io_resp_f3_2_is_jal, // @[predictor.scala:140:14]
output io_resp_f3_2_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f3_2_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f3_3_taken, // @[predictor.scala:140:14]
output io_resp_f3_3_is_br, // @[predictor.scala:140:14]
output io_resp_f3_3_is_jal, // @[predictor.scala:140:14]
output io_resp_f3_3_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f3_3_predicted_pc_bits, // @[predictor.scala:140:14]
output [119:0] io_f3_meta, // @[predictor.scala:140:14]
input io_f3_fire, // @[predictor.scala:140:14]
input io_update_valid, // @[predictor.scala:140:14]
input io_update_bits_is_mispredict_update, // @[predictor.scala:140:14]
input io_update_bits_is_repair_update, // @[predictor.scala:140:14]
input [3:0] io_update_bits_btb_mispredicts, // @[predictor.scala:140:14]
input [39:0] io_update_bits_pc, // @[predictor.scala:140:14]
input [3:0] io_update_bits_br_mask, // @[predictor.scala:140:14]
input io_update_bits_cfi_idx_valid, // @[predictor.scala:140:14]
input [1:0] io_update_bits_cfi_idx_bits, // @[predictor.scala:140:14]
input io_update_bits_cfi_taken, // @[predictor.scala:140:14]
input io_update_bits_cfi_mispredicted, // @[predictor.scala:140:14]
input io_update_bits_cfi_is_br, // @[predictor.scala:140:14]
input io_update_bits_cfi_is_jal, // @[predictor.scala:140:14]
input io_update_bits_cfi_is_jalr, // @[predictor.scala:140:14]
input [63:0] io_update_bits_ghist, // @[predictor.scala:140:14]
input io_update_bits_lhist, // @[predictor.scala:140:14]
input [39:0] io_update_bits_target, // @[predictor.scala:140:14]
input [119:0] io_update_bits_meta // @[predictor.scala:140:14]
);
wire [2:0] s1_update_meta_provider_ctr_3; // @[tage.scala:236:52]
wire [2:0] s1_update_meta_provider_ctr_2; // @[tage.scala:236:52]
wire [2:0] s1_update_meta_provider_ctr_1; // @[tage.scala:236:52]
wire [2:0] s1_update_meta_provider_ctr_0; // @[tage.scala:236:52]
wire _alloc_lfsr_prng_3_io_out_0; // @[PRNG.scala:91:22]
wire _alloc_lfsr_prng_3_io_out_1; // @[PRNG.scala:91:22]
wire _alloc_lfsr_prng_3_io_out_2; // @[PRNG.scala:91:22]
wire _alloc_lfsr_prng_3_io_out_3; // @[PRNG.scala:91:22]
wire _alloc_lfsr_prng_3_io_out_4; // @[PRNG.scala:91:22]
wire _alloc_lfsr_prng_3_io_out_5; // @[PRNG.scala:91:22]
wire _alloc_lfsr_prng_2_io_out_0; // @[PRNG.scala:91:22]
wire _alloc_lfsr_prng_2_io_out_1; // @[PRNG.scala:91:22]
wire _alloc_lfsr_prng_2_io_out_2; // @[PRNG.scala:91:22]
wire _alloc_lfsr_prng_2_io_out_3; // @[PRNG.scala:91:22]
wire _alloc_lfsr_prng_2_io_out_4; // @[PRNG.scala:91:22]
wire _alloc_lfsr_prng_2_io_out_5; // @[PRNG.scala:91:22]
wire _alloc_lfsr_prng_1_io_out_0; // @[PRNG.scala:91:22]
wire _alloc_lfsr_prng_1_io_out_1; // @[PRNG.scala:91:22]
wire _alloc_lfsr_prng_1_io_out_2; // @[PRNG.scala:91:22]
wire _alloc_lfsr_prng_1_io_out_3; // @[PRNG.scala:91:22]
wire _alloc_lfsr_prng_1_io_out_4; // @[PRNG.scala:91:22]
wire _alloc_lfsr_prng_1_io_out_5; // @[PRNG.scala:91:22]
wire _alloc_lfsr_prng_io_out_0; // @[PRNG.scala:91:22]
wire _alloc_lfsr_prng_io_out_1; // @[PRNG.scala:91:22]
wire _alloc_lfsr_prng_io_out_2; // @[PRNG.scala:91:22]
wire _alloc_lfsr_prng_io_out_3; // @[PRNG.scala:91:22]
wire _alloc_lfsr_prng_io_out_4; // @[PRNG.scala:91:22]
wire _alloc_lfsr_prng_io_out_5; // @[PRNG.scala:91:22]
wire io_f0_valid_0 = io_f0_valid; // @[tage.scala:198:7]
wire [39:0] io_f0_pc_0 = io_f0_pc; // @[tage.scala:198:7]
wire [3:0] io_f0_mask_0 = io_f0_mask; // @[tage.scala:198:7]
wire [63:0] io_f1_ghist_0 = io_f1_ghist; // @[tage.scala:198:7]
wire io_resp_in_0_f1_0_taken_0 = io_resp_in_0_f1_0_taken; // @[tage.scala:198:7]
wire io_resp_in_0_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br; // @[tage.scala:198:7]
wire io_resp_in_0_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal; // @[tage.scala:198:7]
wire io_resp_in_0_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid; // @[tage.scala:198:7]
wire [39:0] io_resp_in_0_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits; // @[tage.scala:198:7]
wire io_resp_in_0_f1_1_taken_0 = io_resp_in_0_f1_1_taken; // @[tage.scala:198:7]
wire io_resp_in_0_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br; // @[tage.scala:198:7]
wire io_resp_in_0_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal; // @[tage.scala:198:7]
wire io_resp_in_0_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid; // @[tage.scala:198:7]
wire [39:0] io_resp_in_0_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits; // @[tage.scala:198:7]
wire io_resp_in_0_f1_2_taken_0 = io_resp_in_0_f1_2_taken; // @[tage.scala:198:7]
wire io_resp_in_0_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br; // @[tage.scala:198:7]
wire io_resp_in_0_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal; // @[tage.scala:198:7]
wire io_resp_in_0_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid; // @[tage.scala:198:7]
wire [39:0] io_resp_in_0_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits; // @[tage.scala:198:7]
wire io_resp_in_0_f1_3_taken_0 = io_resp_in_0_f1_3_taken; // @[tage.scala:198:7]
wire io_resp_in_0_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br; // @[tage.scala:198:7]
wire io_resp_in_0_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal; // @[tage.scala:198:7]
wire io_resp_in_0_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid; // @[tage.scala:198:7]
wire [39:0] io_resp_in_0_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits; // @[tage.scala:198:7]
wire io_resp_in_0_f2_0_taken_0 = io_resp_in_0_f2_0_taken; // @[tage.scala:198:7]
wire io_resp_in_0_f2_0_is_br_0 = io_resp_in_0_f2_0_is_br; // @[tage.scala:198:7]
wire io_resp_in_0_f2_0_is_jal_0 = io_resp_in_0_f2_0_is_jal; // @[tage.scala:198:7]
wire io_resp_in_0_f2_0_predicted_pc_valid_0 = io_resp_in_0_f2_0_predicted_pc_valid; // @[tage.scala:198:7]
wire [39:0] io_resp_in_0_f2_0_predicted_pc_bits_0 = io_resp_in_0_f2_0_predicted_pc_bits; // @[tage.scala:198:7]
wire io_resp_in_0_f2_1_taken_0 = io_resp_in_0_f2_1_taken; // @[tage.scala:198:7]
wire io_resp_in_0_f2_1_is_br_0 = io_resp_in_0_f2_1_is_br; // @[tage.scala:198:7]
wire io_resp_in_0_f2_1_is_jal_0 = io_resp_in_0_f2_1_is_jal; // @[tage.scala:198:7]
wire io_resp_in_0_f2_1_predicted_pc_valid_0 = io_resp_in_0_f2_1_predicted_pc_valid; // @[tage.scala:198:7]
wire [39:0] io_resp_in_0_f2_1_predicted_pc_bits_0 = io_resp_in_0_f2_1_predicted_pc_bits; // @[tage.scala:198:7]
wire io_resp_in_0_f2_2_taken_0 = io_resp_in_0_f2_2_taken; // @[tage.scala:198:7]
wire io_resp_in_0_f2_2_is_br_0 = io_resp_in_0_f2_2_is_br; // @[tage.scala:198:7]
wire io_resp_in_0_f2_2_is_jal_0 = io_resp_in_0_f2_2_is_jal; // @[tage.scala:198:7]
wire io_resp_in_0_f2_2_predicted_pc_valid_0 = io_resp_in_0_f2_2_predicted_pc_valid; // @[tage.scala:198:7]
wire [39:0] io_resp_in_0_f2_2_predicted_pc_bits_0 = io_resp_in_0_f2_2_predicted_pc_bits; // @[tage.scala:198:7]
wire io_resp_in_0_f2_3_taken_0 = io_resp_in_0_f2_3_taken; // @[tage.scala:198:7]
wire io_resp_in_0_f2_3_is_br_0 = io_resp_in_0_f2_3_is_br; // @[tage.scala:198:7]
wire io_resp_in_0_f2_3_is_jal_0 = io_resp_in_0_f2_3_is_jal; // @[tage.scala:198:7]
wire io_resp_in_0_f2_3_predicted_pc_valid_0 = io_resp_in_0_f2_3_predicted_pc_valid; // @[tage.scala:198:7]
wire [39:0] io_resp_in_0_f2_3_predicted_pc_bits_0 = io_resp_in_0_f2_3_predicted_pc_bits; // @[tage.scala:198:7]
wire io_resp_in_0_f3_0_taken_0 = io_resp_in_0_f3_0_taken; // @[tage.scala:198:7]
wire io_resp_in_0_f3_0_is_br_0 = io_resp_in_0_f3_0_is_br; // @[tage.scala:198:7]
wire io_resp_in_0_f3_0_is_jal_0 = io_resp_in_0_f3_0_is_jal; // @[tage.scala:198:7]
wire io_resp_in_0_f3_0_predicted_pc_valid_0 = io_resp_in_0_f3_0_predicted_pc_valid; // @[tage.scala:198:7]
wire [39:0] io_resp_in_0_f3_0_predicted_pc_bits_0 = io_resp_in_0_f3_0_predicted_pc_bits; // @[tage.scala:198:7]
wire io_resp_in_0_f3_1_taken_0 = io_resp_in_0_f3_1_taken; // @[tage.scala:198:7]
wire io_resp_in_0_f3_1_is_br_0 = io_resp_in_0_f3_1_is_br; // @[tage.scala:198:7]
wire io_resp_in_0_f3_1_is_jal_0 = io_resp_in_0_f3_1_is_jal; // @[tage.scala:198:7]
wire io_resp_in_0_f3_1_predicted_pc_valid_0 = io_resp_in_0_f3_1_predicted_pc_valid; // @[tage.scala:198:7]
wire [39:0] io_resp_in_0_f3_1_predicted_pc_bits_0 = io_resp_in_0_f3_1_predicted_pc_bits; // @[tage.scala:198:7]
wire io_resp_in_0_f3_2_taken_0 = io_resp_in_0_f3_2_taken; // @[tage.scala:198:7]
wire io_resp_in_0_f3_2_is_br_0 = io_resp_in_0_f3_2_is_br; // @[tage.scala:198:7]
wire io_resp_in_0_f3_2_is_jal_0 = io_resp_in_0_f3_2_is_jal; // @[tage.scala:198:7]
wire io_resp_in_0_f3_2_predicted_pc_valid_0 = io_resp_in_0_f3_2_predicted_pc_valid; // @[tage.scala:198:7]
wire [39:0] io_resp_in_0_f3_2_predicted_pc_bits_0 = io_resp_in_0_f3_2_predicted_pc_bits; // @[tage.scala:198:7]
wire io_resp_in_0_f3_3_taken_0 = io_resp_in_0_f3_3_taken; // @[tage.scala:198:7]
wire io_resp_in_0_f3_3_is_br_0 = io_resp_in_0_f3_3_is_br; // @[tage.scala:198:7]
wire io_resp_in_0_f3_3_is_jal_0 = io_resp_in_0_f3_3_is_jal; // @[tage.scala:198:7]
wire io_resp_in_0_f3_3_predicted_pc_valid_0 = io_resp_in_0_f3_3_predicted_pc_valid; // @[tage.scala:198:7]
wire [39:0] io_resp_in_0_f3_3_predicted_pc_bits_0 = io_resp_in_0_f3_3_predicted_pc_bits; // @[tage.scala:198:7]
wire io_f3_fire_0 = io_f3_fire; // @[tage.scala:198:7]
wire io_update_valid_0 = io_update_valid; // @[tage.scala:198:7]
wire io_update_bits_is_mispredict_update_0 = io_update_bits_is_mispredict_update; // @[tage.scala:198:7]
wire io_update_bits_is_repair_update_0 = io_update_bits_is_repair_update; // @[tage.scala:198:7]
wire [3:0] io_update_bits_btb_mispredicts_0 = io_update_bits_btb_mispredicts; // @[tage.scala:198:7]
wire [39:0] io_update_bits_pc_0 = io_update_bits_pc; // @[tage.scala:198:7]
wire [3:0] io_update_bits_br_mask_0 = io_update_bits_br_mask; // @[tage.scala:198:7]
wire io_update_bits_cfi_idx_valid_0 = io_update_bits_cfi_idx_valid; // @[tage.scala:198:7]
wire [1:0] io_update_bits_cfi_idx_bits_0 = io_update_bits_cfi_idx_bits; // @[tage.scala:198:7]
wire io_update_bits_cfi_taken_0 = io_update_bits_cfi_taken; // @[tage.scala:198:7]
wire io_update_bits_cfi_mispredicted_0 = io_update_bits_cfi_mispredicted; // @[tage.scala:198:7]
wire io_update_bits_cfi_is_br_0 = io_update_bits_cfi_is_br; // @[tage.scala:198:7]
wire io_update_bits_cfi_is_jal_0 = io_update_bits_cfi_is_jal; // @[tage.scala:198:7]
wire io_update_bits_cfi_is_jalr_0 = io_update_bits_cfi_is_jalr; // @[tage.scala:198:7]
wire [63:0] io_update_bits_ghist_0 = io_update_bits_ghist; // @[tage.scala:198:7]
wire io_update_bits_lhist_0 = io_update_bits_lhist; // @[tage.scala:198:7]
wire [39:0] io_update_bits_target_0 = io_update_bits_target; // @[tage.scala:198:7]
wire [119:0] io_update_bits_meta_0 = io_update_bits_meta; // @[tage.scala:198:7]
wire io_f1_lhist = 1'h0; // @[tage.scala:198:7]
wire _s1_update_mask_WIRE_0_0 = 1'h0; // @[tage.scala:240:48]
wire _s1_update_mask_WIRE_0_1 = 1'h0; // @[tage.scala:240:48]
wire _s1_update_mask_WIRE_0_2 = 1'h0; // @[tage.scala:240:48]
wire _s1_update_mask_WIRE_0_3 = 1'h0; // @[tage.scala:240:48]
wire _s1_update_mask_WIRE_1_0 = 1'h0; // @[tage.scala:240:48]
wire _s1_update_mask_WIRE_1_1 = 1'h0; // @[tage.scala:240:48]
wire _s1_update_mask_WIRE_1_2 = 1'h0; // @[tage.scala:240:48]
wire _s1_update_mask_WIRE_1_3 = 1'h0; // @[tage.scala:240:48]
wire _s1_update_mask_WIRE_2_0 = 1'h0; // @[tage.scala:240:48]
wire _s1_update_mask_WIRE_2_1 = 1'h0; // @[tage.scala:240:48]
wire _s1_update_mask_WIRE_2_2 = 1'h0; // @[tage.scala:240:48]
wire _s1_update_mask_WIRE_2_3 = 1'h0; // @[tage.scala:240:48]
wire _s1_update_mask_WIRE_3_0 = 1'h0; // @[tage.scala:240:48]
wire _s1_update_mask_WIRE_3_1 = 1'h0; // @[tage.scala:240:48]
wire _s1_update_mask_WIRE_3_2 = 1'h0; // @[tage.scala:240:48]
wire _s1_update_mask_WIRE_3_3 = 1'h0; // @[tage.scala:240:48]
wire _s1_update_mask_WIRE_4_0 = 1'h0; // @[tage.scala:240:48]
wire _s1_update_mask_WIRE_4_1 = 1'h0; // @[tage.scala:240:48]
wire _s1_update_mask_WIRE_4_2 = 1'h0; // @[tage.scala:240:48]
wire _s1_update_mask_WIRE_4_3 = 1'h0; // @[tage.scala:240:48]
wire _s1_update_mask_WIRE_5_0 = 1'h0; // @[tage.scala:240:48]
wire _s1_update_mask_WIRE_5_1 = 1'h0; // @[tage.scala:240:48]
wire _s1_update_mask_WIRE_5_2 = 1'h0; // @[tage.scala:240:48]
wire _s1_update_mask_WIRE_5_3 = 1'h0; // @[tage.scala:240:48]
wire _s1_update_u_mask_WIRE_0_0 = 1'h0; // @[tage.scala:241:50]
wire _s1_update_u_mask_WIRE_0_1 = 1'h0; // @[tage.scala:241:50]
wire _s1_update_u_mask_WIRE_0_2 = 1'h0; // @[tage.scala:241:50]
wire _s1_update_u_mask_WIRE_0_3 = 1'h0; // @[tage.scala:241:50]
wire _s1_update_u_mask_WIRE_1_0 = 1'h0; // @[tage.scala:241:50]
wire _s1_update_u_mask_WIRE_1_1 = 1'h0; // @[tage.scala:241:50]
wire _s1_update_u_mask_WIRE_1_2 = 1'h0; // @[tage.scala:241:50]
wire _s1_update_u_mask_WIRE_1_3 = 1'h0; // @[tage.scala:241:50]
wire _s1_update_u_mask_WIRE_2_0 = 1'h0; // @[tage.scala:241:50]
wire _s1_update_u_mask_WIRE_2_1 = 1'h0; // @[tage.scala:241:50]
wire _s1_update_u_mask_WIRE_2_2 = 1'h0; // @[tage.scala:241:50]
wire _s1_update_u_mask_WIRE_2_3 = 1'h0; // @[tage.scala:241:50]
wire _s1_update_u_mask_WIRE_3_0 = 1'h0; // @[tage.scala:241:50]
wire _s1_update_u_mask_WIRE_3_1 = 1'h0; // @[tage.scala:241:50]
wire _s1_update_u_mask_WIRE_3_2 = 1'h0; // @[tage.scala:241:50]
wire _s1_update_u_mask_WIRE_3_3 = 1'h0; // @[tage.scala:241:50]
wire _s1_update_u_mask_WIRE_4_0 = 1'h0; // @[tage.scala:241:50]
wire _s1_update_u_mask_WIRE_4_1 = 1'h0; // @[tage.scala:241:50]
wire _s1_update_u_mask_WIRE_4_2 = 1'h0; // @[tage.scala:241:50]
wire _s1_update_u_mask_WIRE_4_3 = 1'h0; // @[tage.scala:241:50]
wire _s1_update_u_mask_WIRE_5_0 = 1'h0; // @[tage.scala:241:50]
wire _s1_update_u_mask_WIRE_5_1 = 1'h0; // @[tage.scala:241:50]
wire _s1_update_u_mask_WIRE_5_2 = 1'h0; // @[tage.scala:241:50]
wire _s1_update_u_mask_WIRE_5_3 = 1'h0; // @[tage.scala:241:50]
wire io_resp_f1_0_taken_0 = io_resp_in_0_f1_0_taken_0; // @[tage.scala:198:7]
wire io_resp_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br_0; // @[tage.scala:198:7]
wire io_resp_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal_0; // @[tage.scala:198:7]
wire io_resp_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid_0; // @[tage.scala:198:7]
wire [39:0] io_resp_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits_0; // @[tage.scala:198:7]
wire io_resp_f1_1_taken_0 = io_resp_in_0_f1_1_taken_0; // @[tage.scala:198:7]
wire io_resp_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br_0; // @[tage.scala:198:7]
wire io_resp_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal_0; // @[tage.scala:198:7]
wire io_resp_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid_0; // @[tage.scala:198:7]
wire [39:0] io_resp_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits_0; // @[tage.scala:198:7]
wire io_resp_f1_2_taken_0 = io_resp_in_0_f1_2_taken_0; // @[tage.scala:198:7]
wire io_resp_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br_0; // @[tage.scala:198:7]
wire io_resp_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal_0; // @[tage.scala:198:7]
wire io_resp_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid_0; // @[tage.scala:198:7]
wire [39:0] io_resp_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits_0; // @[tage.scala:198:7]
wire io_resp_f1_3_taken_0 = io_resp_in_0_f1_3_taken_0; // @[tage.scala:198:7]
wire io_resp_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br_0; // @[tage.scala:198:7]
wire io_resp_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal_0; // @[tage.scala:198:7]
wire io_resp_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid_0; // @[tage.scala:198:7]
wire [39:0] io_resp_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits_0; // @[tage.scala:198:7]
wire io_resp_f2_0_taken_0 = io_resp_in_0_f2_0_taken_0; // @[tage.scala:198:7]
wire io_resp_f2_0_is_br_0 = io_resp_in_0_f2_0_is_br_0; // @[tage.scala:198:7]
wire io_resp_f2_0_is_jal_0 = io_resp_in_0_f2_0_is_jal_0; // @[tage.scala:198:7]
wire io_resp_f2_0_predicted_pc_valid_0 = io_resp_in_0_f2_0_predicted_pc_valid_0; // @[tage.scala:198:7]
wire [39:0] io_resp_f2_0_predicted_pc_bits_0 = io_resp_in_0_f2_0_predicted_pc_bits_0; // @[tage.scala:198:7]
wire io_resp_f2_1_taken_0 = io_resp_in_0_f2_1_taken_0; // @[tage.scala:198:7]
wire io_resp_f2_1_is_br_0 = io_resp_in_0_f2_1_is_br_0; // @[tage.scala:198:7]
wire io_resp_f2_1_is_jal_0 = io_resp_in_0_f2_1_is_jal_0; // @[tage.scala:198:7]
wire io_resp_f2_1_predicted_pc_valid_0 = io_resp_in_0_f2_1_predicted_pc_valid_0; // @[tage.scala:198:7]
wire [39:0] io_resp_f2_1_predicted_pc_bits_0 = io_resp_in_0_f2_1_predicted_pc_bits_0; // @[tage.scala:198:7]
wire io_resp_f2_2_taken_0 = io_resp_in_0_f2_2_taken_0; // @[tage.scala:198:7]
wire io_resp_f2_2_is_br_0 = io_resp_in_0_f2_2_is_br_0; // @[tage.scala:198:7]
wire io_resp_f2_2_is_jal_0 = io_resp_in_0_f2_2_is_jal_0; // @[tage.scala:198:7]
wire io_resp_f2_2_predicted_pc_valid_0 = io_resp_in_0_f2_2_predicted_pc_valid_0; // @[tage.scala:198:7]
wire [39:0] io_resp_f2_2_predicted_pc_bits_0 = io_resp_in_0_f2_2_predicted_pc_bits_0; // @[tage.scala:198:7]
wire io_resp_f2_3_taken_0 = io_resp_in_0_f2_3_taken_0; // @[tage.scala:198:7]
wire io_resp_f2_3_is_br_0 = io_resp_in_0_f2_3_is_br_0; // @[tage.scala:198:7]
wire io_resp_f2_3_is_jal_0 = io_resp_in_0_f2_3_is_jal_0; // @[tage.scala:198:7]
wire io_resp_f2_3_predicted_pc_valid_0 = io_resp_in_0_f2_3_predicted_pc_valid_0; // @[tage.scala:198:7]
wire [39:0] io_resp_f2_3_predicted_pc_bits_0 = io_resp_in_0_f2_3_predicted_pc_bits_0; // @[tage.scala:198:7]
wire io_resp_f3_0_is_br_0 = io_resp_in_0_f3_0_is_br_0; // @[tage.scala:198:7]
wire io_resp_f3_0_is_jal_0 = io_resp_in_0_f3_0_is_jal_0; // @[tage.scala:198:7]
wire io_resp_f3_0_predicted_pc_valid_0 = io_resp_in_0_f3_0_predicted_pc_valid_0; // @[tage.scala:198:7]
wire [39:0] io_resp_f3_0_predicted_pc_bits_0 = io_resp_in_0_f3_0_predicted_pc_bits_0; // @[tage.scala:198:7]
wire io_resp_f3_1_is_br_0 = io_resp_in_0_f3_1_is_br_0; // @[tage.scala:198:7]
wire io_resp_f3_1_is_jal_0 = io_resp_in_0_f3_1_is_jal_0; // @[tage.scala:198:7]
wire io_resp_f3_1_predicted_pc_valid_0 = io_resp_in_0_f3_1_predicted_pc_valid_0; // @[tage.scala:198:7]
wire [39:0] io_resp_f3_1_predicted_pc_bits_0 = io_resp_in_0_f3_1_predicted_pc_bits_0; // @[tage.scala:198:7]
wire io_resp_f3_2_is_br_0 = io_resp_in_0_f3_2_is_br_0; // @[tage.scala:198:7]
wire io_resp_f3_2_is_jal_0 = io_resp_in_0_f3_2_is_jal_0; // @[tage.scala:198:7]
wire io_resp_f3_2_predicted_pc_valid_0 = io_resp_in_0_f3_2_predicted_pc_valid_0; // @[tage.scala:198:7]
wire [39:0] io_resp_f3_2_predicted_pc_bits_0 = io_resp_in_0_f3_2_predicted_pc_bits_0; // @[tage.scala:198:7]
wire io_resp_f3_3_is_br_0 = io_resp_in_0_f3_3_is_br_0; // @[tage.scala:198:7]
wire io_resp_f3_3_is_jal_0 = io_resp_in_0_f3_3_is_jal_0; // @[tage.scala:198:7]
wire io_resp_f3_3_predicted_pc_valid_0 = io_resp_in_0_f3_3_predicted_pc_valid_0; // @[tage.scala:198:7]
wire [39:0] io_resp_f3_3_predicted_pc_bits_0 = io_resp_in_0_f3_3_predicted_pc_bits_0; // @[tage.scala:198:7]
wire io_resp_f3_0_taken_0; // @[tage.scala:198:7]
wire io_resp_f3_1_taken_0; // @[tage.scala:198:7]
wire io_resp_f3_2_taken_0; // @[tage.scala:198:7]
wire io_resp_f3_3_taken_0; // @[tage.scala:198:7]
wire [119:0] io_f3_meta_0; // @[tage.scala:198:7]
wire [35:0] s0_idx = io_f0_pc_0[39:4]; // @[frontend.scala:162:35]
reg [35:0] s1_idx; // @[predictor.scala:163:29]
reg [35:0] s2_idx; // @[predictor.scala:164:29]
reg [35:0] s3_idx; // @[predictor.scala:165:29]
reg s1_valid; // @[predictor.scala:168:25]
reg s2_valid; // @[predictor.scala:169:25]
reg s3_valid; // @[predictor.scala:170:25]
reg [3:0] s1_mask; // @[predictor.scala:173:24]
reg [3:0] s2_mask; // @[predictor.scala:174:24]
reg [3:0] s3_mask; // @[predictor.scala:175:24]
reg [39:0] s1_pc; // @[predictor.scala:178:22]
wire [35:0] s0_update_idx = io_update_bits_pc_0[39:4]; // @[frontend.scala:162:35]
reg s1_update_valid; // @[predictor.scala:184:30]
reg s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30]
reg s1_update_bits_is_repair_update; // @[predictor.scala:184:30]
reg [3:0] s1_update_bits_btb_mispredicts; // @[predictor.scala:184:30]
reg [39:0] s1_update_bits_pc; // @[predictor.scala:184:30]
reg [3:0] s1_update_bits_br_mask; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_idx_valid; // @[predictor.scala:184:30]
reg [1:0] s1_update_bits_cfi_idx_bits; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_taken; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_is_br; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_is_jal; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_is_jalr; // @[predictor.scala:184:30]
reg [63:0] s1_update_bits_ghist; // @[predictor.scala:184:30]
reg s1_update_bits_lhist; // @[predictor.scala:184:30]
reg [39:0] s1_update_bits_target; // @[predictor.scala:184:30]
reg [119:0] s1_update_bits_meta; // @[predictor.scala:184:30]
reg [35:0] s1_update_idx; // @[predictor.scala:185:30]
reg s1_update_valid_0; // @[predictor.scala:186:32]
wire _f3_meta_alt_differs_0_T; // @[tage.scala:275:48]
wire _f3_meta_alt_differs_1_T; // @[tage.scala:275:48]
wire _f3_meta_alt_differs_2_T; // @[tage.scala:275:48]
wire _f3_meta_alt_differs_3_T; // @[tage.scala:275:48]
wire _f3_meta_allocate_0_valid_T; // @[tage.scala:293:52]
wire [2:0] alloc_entry; // @[tage.scala:289:26]
wire _f3_meta_allocate_1_valid_T; // @[tage.scala:293:52]
wire [2:0] alloc_entry_1; // @[tage.scala:289:26]
wire _f3_meta_allocate_2_valid_T; // @[tage.scala:293:52]
wire [2:0] alloc_entry_2; // @[tage.scala:289:26]
wire _f3_meta_allocate_3_valid_T; // @[tage.scala:293:52]
wire [2:0] alloc_entry_3; // @[tage.scala:289:26]
wire f3_meta_provider_0_valid; // @[tage.scala:212:21]
wire [2:0] f3_meta_provider_0_bits; // @[tage.scala:212:21]
wire f3_meta_provider_1_valid; // @[tage.scala:212:21]
wire [2:0] f3_meta_provider_1_bits; // @[tage.scala:212:21]
wire f3_meta_provider_2_valid; // @[tage.scala:212:21]
wire [2:0] f3_meta_provider_2_bits; // @[tage.scala:212:21]
wire f3_meta_provider_3_valid; // @[tage.scala:212:21]
wire [2:0] f3_meta_provider_3_bits; // @[tage.scala:212:21]
wire f3_meta_alt_differs_0; // @[tage.scala:212:21]
wire f3_meta_alt_differs_1; // @[tage.scala:212:21]
wire f3_meta_alt_differs_2; // @[tage.scala:212:21]
wire f3_meta_alt_differs_3; // @[tage.scala:212:21]
wire [1:0] f3_meta_provider_u_0; // @[tage.scala:212:21]
wire [1:0] f3_meta_provider_u_1; // @[tage.scala:212:21]
wire [1:0] f3_meta_provider_u_2; // @[tage.scala:212:21]
wire [1:0] f3_meta_provider_u_3; // @[tage.scala:212:21]
wire [2:0] f3_meta_provider_ctr_0; // @[tage.scala:212:21]
wire [2:0] f3_meta_provider_ctr_1; // @[tage.scala:212:21]
wire [2:0] f3_meta_provider_ctr_2; // @[tage.scala:212:21]
wire [2:0] f3_meta_provider_ctr_3; // @[tage.scala:212:21]
wire f3_meta_allocate_0_valid; // @[tage.scala:212:21]
wire [2:0] f3_meta_allocate_0_bits; // @[tage.scala:212:21]
wire f3_meta_allocate_1_valid; // @[tage.scala:212:21]
wire [2:0] f3_meta_allocate_1_bits; // @[tage.scala:212:21]
wire f3_meta_allocate_2_valid; // @[tage.scala:212:21]
wire [2:0] f3_meta_allocate_2_bits; // @[tage.scala:212:21]
wire f3_meta_allocate_3_valid; // @[tage.scala:212:21]
wire [2:0] f3_meta_allocate_3_bits; // @[tage.scala:212:21]
wire [3:0] _io_f3_meta_T = {f3_meta_allocate_0_valid, f3_meta_allocate_0_bits}; // @[tage.scala:212:21, :213:33, :359:25]
wire [3:0] _io_f3_meta_T_1 = {f3_meta_allocate_1_valid, f3_meta_allocate_1_bits}; // @[tage.scala:212:21, :213:33, :359:25]
wire [3:0] _io_f3_meta_T_2 = {f3_meta_allocate_2_valid, f3_meta_allocate_2_bits}; // @[tage.scala:212:21, :213:33, :359:25]
wire [3:0] _io_f3_meta_T_3 = {f3_meta_allocate_3_valid, f3_meta_allocate_3_bits}; // @[tage.scala:212:21, :213:33, :359:25]
wire [7:0] lo = {f3_meta_allocate_1_valid, f3_meta_allocate_1_bits, f3_meta_allocate_0_valid, f3_meta_allocate_0_bits}; // @[tage.scala:212:21, :213:33]
wire [7:0] hi = {f3_meta_allocate_3_valid, f3_meta_allocate_3_bits, f3_meta_allocate_2_valid, f3_meta_allocate_2_bits}; // @[tage.scala:212:21, :213:33]
wire [5:0] _GEN = {f3_meta_provider_ctr_1, f3_meta_provider_ctr_0}; // @[tage.scala:212:21, :213:33]
wire [5:0] lo_1; // @[tage.scala:213:33]
assign lo_1 = _GEN; // @[tage.scala:213:33]
wire [5:0] io_f3_meta_lo_1; // @[tage.scala:359:25]
assign io_f3_meta_lo_1 = _GEN; // @[tage.scala:213:33, :359:25]
wire [5:0] _GEN_0 = {f3_meta_provider_ctr_3, f3_meta_provider_ctr_2}; // @[tage.scala:212:21, :213:33]
wire [5:0] hi_1; // @[tage.scala:213:33]
assign hi_1 = _GEN_0; // @[tage.scala:213:33]
wire [5:0] io_f3_meta_hi_1; // @[tage.scala:359:25]
assign io_f3_meta_hi_1 = _GEN_0; // @[tage.scala:213:33, :359:25]
wire [3:0] _GEN_1 = {f3_meta_provider_u_1, f3_meta_provider_u_0}; // @[tage.scala:212:21, :213:33]
wire [3:0] lo_2; // @[tage.scala:213:33]
assign lo_2 = _GEN_1; // @[tage.scala:213:33]
wire [3:0] io_f3_meta_lo_2; // @[tage.scala:359:25]
assign io_f3_meta_lo_2 = _GEN_1; // @[tage.scala:213:33, :359:25]
wire [3:0] _GEN_2 = {f3_meta_provider_u_3, f3_meta_provider_u_2}; // @[tage.scala:212:21, :213:33]
wire [3:0] hi_2; // @[tage.scala:213:33]
assign hi_2 = _GEN_2; // @[tage.scala:213:33]
wire [3:0] io_f3_meta_hi_2; // @[tage.scala:359:25]
assign io_f3_meta_hi_2 = _GEN_2; // @[tage.scala:213:33, :359:25]
wire [1:0] _GEN_3 = {f3_meta_alt_differs_1, f3_meta_alt_differs_0}; // @[tage.scala:212:21, :213:33]
wire [1:0] lo_3; // @[tage.scala:213:33]
assign lo_3 = _GEN_3; // @[tage.scala:213:33]
wire [1:0] io_f3_meta_lo_3; // @[tage.scala:359:25]
assign io_f3_meta_lo_3 = _GEN_3; // @[tage.scala:213:33, :359:25]
wire [1:0] _GEN_4 = {f3_meta_alt_differs_3, f3_meta_alt_differs_2}; // @[tage.scala:212:21, :213:33]
wire [1:0] hi_3; // @[tage.scala:213:33]
assign hi_3 = _GEN_4; // @[tage.scala:213:33]
wire [1:0] io_f3_meta_hi_3; // @[tage.scala:359:25]
assign io_f3_meta_hi_3 = _GEN_4; // @[tage.scala:213:33, :359:25]
wire [3:0] _io_f3_meta_T_8 = {f3_meta_provider_0_valid, f3_meta_provider_0_bits}; // @[tage.scala:212:21, :213:33, :359:25]
wire [3:0] _io_f3_meta_T_9 = {f3_meta_provider_1_valid, f3_meta_provider_1_bits}; // @[tage.scala:212:21, :213:33, :359:25]
wire [3:0] _io_f3_meta_T_10 = {f3_meta_provider_2_valid, f3_meta_provider_2_bits}; // @[tage.scala:212:21, :213:33, :359:25]
wire [3:0] _io_f3_meta_T_11 = {f3_meta_provider_3_valid, f3_meta_provider_3_bits}; // @[tage.scala:212:21, :213:33, :359:25]
wire [7:0] lo_4 = {f3_meta_provider_1_valid, f3_meta_provider_1_bits, f3_meta_provider_0_valid, f3_meta_provider_0_bits}; // @[tage.scala:212:21, :213:33]
wire [7:0] hi_4 = {f3_meta_provider_3_valid, f3_meta_provider_3_bits, f3_meta_provider_2_valid, f3_meta_provider_2_bits}; // @[tage.scala:212:21, :213:33]
wire [27:0] lo_5 = {hi_1, lo_1, hi, lo}; // @[tage.scala:213:33]
wire [19:0] hi_hi = {hi_4, lo_4, hi_3, lo_3}; // @[tage.scala:213:33]
wire [27:0] hi_5 = {hi_hi, hi_2, lo_2}; // @[tage.scala:213:33]
reg t_io_f1_req_valid_REG; // @[tage.scala:225:35]
reg [39:0] t_io_f1_req_pc_REG; // @[tage.scala:226:35]
reg t_io_f1_req_valid_REG_1; // @[tage.scala:225:35]
reg [39:0] t_io_f1_req_pc_REG_1; // @[tage.scala:226:35]
reg t_io_f1_req_valid_REG_2; // @[tage.scala:225:35]
reg [39:0] t_io_f1_req_pc_REG_2; // @[tage.scala:226:35]
reg t_io_f1_req_valid_REG_3; // @[tage.scala:225:35]
reg [39:0] t_io_f1_req_pc_REG_3; // @[tage.scala:226:35]
reg t_io_f1_req_valid_REG_4; // @[tage.scala:225:35]
reg [39:0] t_io_f1_req_pc_REG_4; // @[tage.scala:226:35]
reg t_io_f1_req_valid_REG_5; // @[tage.scala:225:35]
reg [39:0] t_io_f1_req_pc_REG_5; // @[tage.scala:226:35]
wire [2:0] f3_resps_0_0_bits_ctr; // @[tage.scala:234:25]
wire [1:0] f3_resps_0_0_bits_u; // @[tage.scala:234:25]
wire f3_resps_0_0_valid; // @[tage.scala:234:25]
wire [2:0] f3_resps_0_1_bits_ctr; // @[tage.scala:234:25]
wire [1:0] f3_resps_0_1_bits_u; // @[tage.scala:234:25]
wire f3_resps_0_1_valid; // @[tage.scala:234:25]
wire [2:0] f3_resps_0_2_bits_ctr; // @[tage.scala:234:25]
wire [1:0] f3_resps_0_2_bits_u; // @[tage.scala:234:25]
wire f3_resps_0_2_valid; // @[tage.scala:234:25]
wire [2:0] f3_resps_0_3_bits_ctr; // @[tage.scala:234:25]
wire [1:0] f3_resps_0_3_bits_u; // @[tage.scala:234:25]
wire f3_resps_0_3_valid; // @[tage.scala:234:25]
wire [2:0] f3_resps_1_0_bits_ctr; // @[tage.scala:234:25]
wire [1:0] f3_resps_1_0_bits_u; // @[tage.scala:234:25]
wire f3_resps_1_0_valid; // @[tage.scala:234:25]
wire [2:0] f3_resps_1_1_bits_ctr; // @[tage.scala:234:25]
wire [1:0] f3_resps_1_1_bits_u; // @[tage.scala:234:25]
wire f3_resps_1_1_valid; // @[tage.scala:234:25]
wire [2:0] f3_resps_1_2_bits_ctr; // @[tage.scala:234:25]
wire [1:0] f3_resps_1_2_bits_u; // @[tage.scala:234:25]
wire f3_resps_1_2_valid; // @[tage.scala:234:25]
wire [2:0] f3_resps_1_3_bits_ctr; // @[tage.scala:234:25]
wire [1:0] f3_resps_1_3_bits_u; // @[tage.scala:234:25]
wire f3_resps_1_3_valid; // @[tage.scala:234:25]
wire [2:0] f3_resps_2_0_bits_ctr; // @[tage.scala:234:25]
wire [1:0] f3_resps_2_0_bits_u; // @[tage.scala:234:25]
wire f3_resps_2_0_valid; // @[tage.scala:234:25]
wire [2:0] f3_resps_2_1_bits_ctr; // @[tage.scala:234:25]
wire [1:0] f3_resps_2_1_bits_u; // @[tage.scala:234:25]
wire f3_resps_2_1_valid; // @[tage.scala:234:25]
wire [2:0] f3_resps_2_2_bits_ctr; // @[tage.scala:234:25]
wire [1:0] f3_resps_2_2_bits_u; // @[tage.scala:234:25]
wire f3_resps_2_2_valid; // @[tage.scala:234:25]
wire [2:0] f3_resps_2_3_bits_ctr; // @[tage.scala:234:25]
wire [1:0] f3_resps_2_3_bits_u; // @[tage.scala:234:25]
wire f3_resps_2_3_valid; // @[tage.scala:234:25]
wire [2:0] f3_resps_3_0_bits_ctr; // @[tage.scala:234:25]
wire [1:0] f3_resps_3_0_bits_u; // @[tage.scala:234:25]
wire f3_resps_3_0_valid; // @[tage.scala:234:25]
wire [2:0] f3_resps_3_1_bits_ctr; // @[tage.scala:234:25]
wire [1:0] f3_resps_3_1_bits_u; // @[tage.scala:234:25]
wire f3_resps_3_1_valid; // @[tage.scala:234:25]
wire [2:0] f3_resps_3_2_bits_ctr; // @[tage.scala:234:25]
wire [1:0] f3_resps_3_2_bits_u; // @[tage.scala:234:25]
wire f3_resps_3_2_valid; // @[tage.scala:234:25]
wire [2:0] f3_resps_3_3_bits_ctr; // @[tage.scala:234:25]
wire [1:0] f3_resps_3_3_bits_u; // @[tage.scala:234:25]
wire f3_resps_3_3_valid; // @[tage.scala:234:25]
wire [2:0] f3_resps_4_0_bits_ctr; // @[tage.scala:234:25]
wire [1:0] f3_resps_4_0_bits_u; // @[tage.scala:234:25]
wire f3_resps_4_0_valid; // @[tage.scala:234:25]
wire [2:0] f3_resps_4_1_bits_ctr; // @[tage.scala:234:25]
wire [1:0] f3_resps_4_1_bits_u; // @[tage.scala:234:25]
wire f3_resps_4_1_valid; // @[tage.scala:234:25]
wire [2:0] f3_resps_4_2_bits_ctr; // @[tage.scala:234:25]
wire [1:0] f3_resps_4_2_bits_u; // @[tage.scala:234:25]
wire f3_resps_4_2_valid; // @[tage.scala:234:25]
wire [2:0] f3_resps_4_3_bits_ctr; // @[tage.scala:234:25]
wire [1:0] f3_resps_4_3_bits_u; // @[tage.scala:234:25]
wire f3_resps_4_3_valid; // @[tage.scala:234:25]
wire [2:0] f3_resps_5_0_bits_ctr; // @[tage.scala:234:25]
wire [1:0] f3_resps_5_0_bits_u; // @[tage.scala:234:25]
wire f3_resps_5_0_valid; // @[tage.scala:234:25]
wire [2:0] f3_resps_5_1_bits_ctr; // @[tage.scala:234:25]
wire [1:0] f3_resps_5_1_bits_u; // @[tage.scala:234:25]
wire f3_resps_5_1_valid; // @[tage.scala:234:25]
wire [2:0] f3_resps_5_2_bits_ctr; // @[tage.scala:234:25]
wire [1:0] f3_resps_5_2_bits_u; // @[tage.scala:234:25]
wire f3_resps_5_2_valid; // @[tage.scala:234:25]
wire [2:0] f3_resps_5_3_bits_ctr; // @[tage.scala:234:25]
wire [1:0] f3_resps_5_3_bits_u; // @[tage.scala:234:25]
wire f3_resps_5_3_valid; // @[tage.scala:234:25]
wire _s1_update_meta_T_21; // @[tage.scala:236:52]
wire [2:0] _s1_update_meta_T_20; // @[tage.scala:236:52]
wire _s1_update_meta_T_23; // @[tage.scala:236:52]
wire [2:0] _s1_update_meta_T_22; // @[tage.scala:236:52]
wire _s1_update_meta_T_25; // @[tage.scala:236:52]
wire [2:0] _s1_update_meta_T_24; // @[tage.scala:236:52]
wire _s1_update_meta_T_27; // @[tage.scala:236:52]
wire [2:0] _s1_update_meta_T_26; // @[tage.scala:236:52]
wire _s1_update_meta_T_16; // @[tage.scala:236:52]
wire _s1_update_meta_T_17; // @[tage.scala:236:52]
wire _s1_update_meta_T_18; // @[tage.scala:236:52]
wire _s1_update_meta_T_19; // @[tage.scala:236:52]
wire [1:0] _s1_update_meta_T_12; // @[tage.scala:236:52]
wire [1:0] _s1_update_meta_T_13; // @[tage.scala:236:52]
wire [1:0] _s1_update_meta_T_14; // @[tage.scala:236:52]
wire [1:0] _s1_update_meta_T_15; // @[tage.scala:236:52]
wire [2:0] _s1_update_meta_T_8; // @[tage.scala:236:52]
wire [2:0] _s1_update_meta_T_9; // @[tage.scala:236:52]
wire [2:0] s1_update_old_ctr_0_0 = s1_update_meta_provider_ctr_0; // @[tage.scala:236:52, :244:31]
wire [2:0] s1_update_old_ctr_1_0 = s1_update_meta_provider_ctr_0; // @[tage.scala:236:52, :244:31]
wire [2:0] s1_update_old_ctr_2_0 = s1_update_meta_provider_ctr_0; // @[tage.scala:236:52, :244:31]
wire [2:0] s1_update_old_ctr_3_0 = s1_update_meta_provider_ctr_0; // @[tage.scala:236:52, :244:31]
wire [2:0] s1_update_old_ctr_4_0 = s1_update_meta_provider_ctr_0; // @[tage.scala:236:52, :244:31]
wire [2:0] s1_update_old_ctr_5_0 = s1_update_meta_provider_ctr_0; // @[tage.scala:236:52, :244:31]
wire [2:0] _s1_update_meta_T_10; // @[tage.scala:236:52]
wire [2:0] s1_update_old_ctr_0_1 = s1_update_meta_provider_ctr_1; // @[tage.scala:236:52, :244:31]
wire [2:0] s1_update_old_ctr_1_1 = s1_update_meta_provider_ctr_1; // @[tage.scala:236:52, :244:31]
wire [2:0] s1_update_old_ctr_2_1 = s1_update_meta_provider_ctr_1; // @[tage.scala:236:52, :244:31]
wire [2:0] s1_update_old_ctr_3_1 = s1_update_meta_provider_ctr_1; // @[tage.scala:236:52, :244:31]
wire [2:0] s1_update_old_ctr_4_1 = s1_update_meta_provider_ctr_1; // @[tage.scala:236:52, :244:31]
wire [2:0] s1_update_old_ctr_5_1 = s1_update_meta_provider_ctr_1; // @[tage.scala:236:52, :244:31]
wire [2:0] _s1_update_meta_T_11; // @[tage.scala:236:52]
wire [2:0] s1_update_old_ctr_0_2 = s1_update_meta_provider_ctr_2; // @[tage.scala:236:52, :244:31]
wire [2:0] s1_update_old_ctr_1_2 = s1_update_meta_provider_ctr_2; // @[tage.scala:236:52, :244:31]
wire [2:0] s1_update_old_ctr_2_2 = s1_update_meta_provider_ctr_2; // @[tage.scala:236:52, :244:31]
wire [2:0] s1_update_old_ctr_3_2 = s1_update_meta_provider_ctr_2; // @[tage.scala:236:52, :244:31]
wire [2:0] s1_update_old_ctr_4_2 = s1_update_meta_provider_ctr_2; // @[tage.scala:236:52, :244:31]
wire [2:0] s1_update_old_ctr_5_2 = s1_update_meta_provider_ctr_2; // @[tage.scala:236:52, :244:31]
wire _s1_update_meta_T_1; // @[tage.scala:236:52]
wire [2:0] s1_update_old_ctr_0_3 = s1_update_meta_provider_ctr_3; // @[tage.scala:236:52, :244:31]
wire [2:0] s1_update_old_ctr_1_3 = s1_update_meta_provider_ctr_3; // @[tage.scala:236:52, :244:31]
wire [2:0] s1_update_old_ctr_2_3 = s1_update_meta_provider_ctr_3; // @[tage.scala:236:52, :244:31]
wire [2:0] s1_update_old_ctr_3_3 = s1_update_meta_provider_ctr_3; // @[tage.scala:236:52, :244:31]
wire [2:0] s1_update_old_ctr_4_3 = s1_update_meta_provider_ctr_3; // @[tage.scala:236:52, :244:31]
wire [2:0] s1_update_old_ctr_5_3 = s1_update_meta_provider_ctr_3; // @[tage.scala:236:52, :244:31]
wire [2:0] _s1_update_meta_T; // @[tage.scala:236:52]
wire _s1_update_meta_T_3; // @[tage.scala:236:52]
wire [2:0] _s1_update_meta_T_2; // @[tage.scala:236:52]
wire _s1_update_meta_T_5; // @[tage.scala:236:52]
wire [2:0] _s1_update_meta_T_4; // @[tage.scala:236:52]
wire _s1_update_meta_T_7; // @[tage.scala:236:52]
wire [2:0] _s1_update_meta_T_6; // @[tage.scala:236:52]
wire s1_update_meta_provider_0_valid; // @[tage.scala:236:52]
wire [2:0] s1_update_meta_provider_0_bits; // @[tage.scala:236:52]
wire s1_update_meta_provider_1_valid; // @[tage.scala:236:52]
wire [2:0] s1_update_meta_provider_1_bits; // @[tage.scala:236:52]
wire s1_update_meta_provider_2_valid; // @[tage.scala:236:52]
wire [2:0] s1_update_meta_provider_2_bits; // @[tage.scala:236:52]
wire s1_update_meta_provider_3_valid; // @[tage.scala:236:52]
wire [2:0] s1_update_meta_provider_3_bits; // @[tage.scala:236:52]
wire s1_update_meta_alt_differs_0; // @[tage.scala:236:52]
wire s1_update_meta_alt_differs_1; // @[tage.scala:236:52]
wire s1_update_meta_alt_differs_2; // @[tage.scala:236:52]
wire s1_update_meta_alt_differs_3; // @[tage.scala:236:52]
wire [1:0] s1_update_meta_provider_u_0; // @[tage.scala:236:52]
wire [1:0] s1_update_meta_provider_u_1; // @[tage.scala:236:52]
wire [1:0] s1_update_meta_provider_u_2; // @[tage.scala:236:52]
wire [1:0] s1_update_meta_provider_u_3; // @[tage.scala:236:52]
wire s1_update_meta_allocate_0_valid; // @[tage.scala:236:52]
wire [2:0] s1_update_meta_allocate_0_bits; // @[tage.scala:236:52]
wire s1_update_meta_allocate_1_valid; // @[tage.scala:236:52]
wire [2:0] s1_update_meta_allocate_1_bits; // @[tage.scala:236:52]
wire s1_update_meta_allocate_2_valid; // @[tage.scala:236:52]
wire [2:0] s1_update_meta_allocate_2_bits; // @[tage.scala:236:52]
wire s1_update_meta_allocate_3_valid; // @[tage.scala:236:52]
wire [2:0] s1_update_meta_allocate_3_bits; // @[tage.scala:236:52]
wire [55:0] _s1_update_meta_WIRE = s1_update_bits_meta[55:0]; // @[tage.scala:236:52]
assign _s1_update_meta_T = _s1_update_meta_WIRE[2:0]; // @[tage.scala:236:52]
assign s1_update_meta_allocate_0_bits = _s1_update_meta_T; // @[tage.scala:236:52]
assign _s1_update_meta_T_1 = _s1_update_meta_WIRE[3]; // @[tage.scala:236:52]
assign s1_update_meta_allocate_0_valid = _s1_update_meta_T_1; // @[tage.scala:236:52]
assign _s1_update_meta_T_2 = _s1_update_meta_WIRE[6:4]; // @[tage.scala:236:52]
assign s1_update_meta_allocate_1_bits = _s1_update_meta_T_2; // @[tage.scala:236:52]
assign _s1_update_meta_T_3 = _s1_update_meta_WIRE[7]; // @[tage.scala:236:52]
assign s1_update_meta_allocate_1_valid = _s1_update_meta_T_3; // @[tage.scala:236:52]
assign _s1_update_meta_T_4 = _s1_update_meta_WIRE[10:8]; // @[tage.scala:236:52]
assign s1_update_meta_allocate_2_bits = _s1_update_meta_T_4; // @[tage.scala:236:52]
assign _s1_update_meta_T_5 = _s1_update_meta_WIRE[11]; // @[tage.scala:236:52]
assign s1_update_meta_allocate_2_valid = _s1_update_meta_T_5; // @[tage.scala:236:52]
assign _s1_update_meta_T_6 = _s1_update_meta_WIRE[14:12]; // @[tage.scala:236:52]
assign s1_update_meta_allocate_3_bits = _s1_update_meta_T_6; // @[tage.scala:236:52]
assign _s1_update_meta_T_7 = _s1_update_meta_WIRE[15]; // @[tage.scala:236:52]
assign s1_update_meta_allocate_3_valid = _s1_update_meta_T_7; // @[tage.scala:236:52]
assign _s1_update_meta_T_8 = _s1_update_meta_WIRE[18:16]; // @[tage.scala:236:52]
assign s1_update_meta_provider_ctr_0 = _s1_update_meta_T_8; // @[tage.scala:236:52]
assign _s1_update_meta_T_9 = _s1_update_meta_WIRE[21:19]; // @[tage.scala:236:52]
assign s1_update_meta_provider_ctr_1 = _s1_update_meta_T_9; // @[tage.scala:236:52]
assign _s1_update_meta_T_10 = _s1_update_meta_WIRE[24:22]; // @[tage.scala:236:52]
assign s1_update_meta_provider_ctr_2 = _s1_update_meta_T_10; // @[tage.scala:236:52]
assign _s1_update_meta_T_11 = _s1_update_meta_WIRE[27:25]; // @[tage.scala:236:52]
assign s1_update_meta_provider_ctr_3 = _s1_update_meta_T_11; // @[tage.scala:236:52]
assign _s1_update_meta_T_12 = _s1_update_meta_WIRE[29:28]; // @[tage.scala:236:52]
assign s1_update_meta_provider_u_0 = _s1_update_meta_T_12; // @[tage.scala:236:52]
assign _s1_update_meta_T_13 = _s1_update_meta_WIRE[31:30]; // @[tage.scala:236:52]
assign s1_update_meta_provider_u_1 = _s1_update_meta_T_13; // @[tage.scala:236:52]
assign _s1_update_meta_T_14 = _s1_update_meta_WIRE[33:32]; // @[tage.scala:236:52]
assign s1_update_meta_provider_u_2 = _s1_update_meta_T_14; // @[tage.scala:236:52]
assign _s1_update_meta_T_15 = _s1_update_meta_WIRE[35:34]; // @[tage.scala:236:52]
assign s1_update_meta_provider_u_3 = _s1_update_meta_T_15; // @[tage.scala:236:52]
assign _s1_update_meta_T_16 = _s1_update_meta_WIRE[36]; // @[tage.scala:236:52]
assign s1_update_meta_alt_differs_0 = _s1_update_meta_T_16; // @[tage.scala:236:52]
assign _s1_update_meta_T_17 = _s1_update_meta_WIRE[37]; // @[tage.scala:236:52]
assign s1_update_meta_alt_differs_1 = _s1_update_meta_T_17; // @[tage.scala:236:52]
assign _s1_update_meta_T_18 = _s1_update_meta_WIRE[38]; // @[tage.scala:236:52]
assign s1_update_meta_alt_differs_2 = _s1_update_meta_T_18; // @[tage.scala:236:52]
assign _s1_update_meta_T_19 = _s1_update_meta_WIRE[39]; // @[tage.scala:236:52]
assign s1_update_meta_alt_differs_3 = _s1_update_meta_T_19; // @[tage.scala:236:52]
assign _s1_update_meta_T_20 = _s1_update_meta_WIRE[42:40]; // @[tage.scala:236:52]
assign s1_update_meta_provider_0_bits = _s1_update_meta_T_20; // @[tage.scala:236:52]
assign _s1_update_meta_T_21 = _s1_update_meta_WIRE[43]; // @[tage.scala:236:52]
assign s1_update_meta_provider_0_valid = _s1_update_meta_T_21; // @[tage.scala:236:52]
assign _s1_update_meta_T_22 = _s1_update_meta_WIRE[46:44]; // @[tage.scala:236:52]
assign s1_update_meta_provider_1_bits = _s1_update_meta_T_22; // @[tage.scala:236:52]
assign _s1_update_meta_T_23 = _s1_update_meta_WIRE[47]; // @[tage.scala:236:52]
assign s1_update_meta_provider_1_valid = _s1_update_meta_T_23; // @[tage.scala:236:52]
assign _s1_update_meta_T_24 = _s1_update_meta_WIRE[50:48]; // @[tage.scala:236:52]
assign s1_update_meta_provider_2_bits = _s1_update_meta_T_24; // @[tage.scala:236:52]
assign _s1_update_meta_T_25 = _s1_update_meta_WIRE[51]; // @[tage.scala:236:52]
assign s1_update_meta_provider_2_valid = _s1_update_meta_T_25; // @[tage.scala:236:52]
assign _s1_update_meta_T_26 = _s1_update_meta_WIRE[54:52]; // @[tage.scala:236:52]
assign s1_update_meta_provider_3_bits = _s1_update_meta_T_26; // @[tage.scala:236:52]
assign _s1_update_meta_T_27 = _s1_update_meta_WIRE[55]; // @[tage.scala:236:52]
assign s1_update_meta_provider_3_valid = _s1_update_meta_T_27; // @[tage.scala:236:52]
wire [3:0] _s1_update_mispredict_mask_T = 4'h1 << s1_update_bits_cfi_idx_bits; // @[OneHot.scala:58:35]
wire [3:0] _s1_update_mispredict_mask_T_1 = {4{s1_update_bits_cfi_mispredicted}}; // @[tage.scala:238:9]
wire [3:0] s1_update_mispredict_mask = _s1_update_mispredict_mask_T & _s1_update_mispredict_mask_T_1; // @[OneHot.scala:58:35]
wire s1_update_mask_0_0; // @[tage.scala:240:33]
wire s1_update_mask_0_1; // @[tage.scala:240:33]
wire s1_update_mask_0_2; // @[tage.scala:240:33]
wire s1_update_mask_0_3; // @[tage.scala:240:33]
wire s1_update_mask_1_0; // @[tage.scala:240:33]
wire s1_update_mask_1_1; // @[tage.scala:240:33]
wire s1_update_mask_1_2; // @[tage.scala:240:33]
wire s1_update_mask_1_3; // @[tage.scala:240:33]
wire s1_update_mask_2_0; // @[tage.scala:240:33]
wire s1_update_mask_2_1; // @[tage.scala:240:33]
wire s1_update_mask_2_2; // @[tage.scala:240:33]
wire s1_update_mask_2_3; // @[tage.scala:240:33]
wire s1_update_mask_3_0; // @[tage.scala:240:33]
wire s1_update_mask_3_1; // @[tage.scala:240:33]
wire s1_update_mask_3_2; // @[tage.scala:240:33]
wire s1_update_mask_3_3; // @[tage.scala:240:33]
wire s1_update_mask_4_0; // @[tage.scala:240:33]
wire s1_update_mask_4_1; // @[tage.scala:240:33]
wire s1_update_mask_4_2; // @[tage.scala:240:33]
wire s1_update_mask_4_3; // @[tage.scala:240:33]
wire s1_update_mask_5_0; // @[tage.scala:240:33]
wire s1_update_mask_5_1; // @[tage.scala:240:33]
wire s1_update_mask_5_2; // @[tage.scala:240:33]
wire s1_update_mask_5_3; // @[tage.scala:240:33]
wire s1_update_u_mask_0_0; // @[tage.scala:241:35]
wire s1_update_u_mask_0_1; // @[tage.scala:241:35]
wire s1_update_u_mask_0_2; // @[tage.scala:241:35]
wire s1_update_u_mask_0_3; // @[tage.scala:241:35]
wire s1_update_u_mask_1_0; // @[tage.scala:241:35]
wire s1_update_u_mask_1_1; // @[tage.scala:241:35]
wire s1_update_u_mask_1_2; // @[tage.scala:241:35]
wire s1_update_u_mask_1_3; // @[tage.scala:241:35]
wire s1_update_u_mask_2_0; // @[tage.scala:241:35]
wire s1_update_u_mask_2_1; // @[tage.scala:241:35]
wire s1_update_u_mask_2_2; // @[tage.scala:241:35]
wire s1_update_u_mask_2_3; // @[tage.scala:241:35]
wire s1_update_u_mask_3_0; // @[tage.scala:241:35]
wire s1_update_u_mask_3_1; // @[tage.scala:241:35]
wire s1_update_u_mask_3_2; // @[tage.scala:241:35]
wire s1_update_u_mask_3_3; // @[tage.scala:241:35]
wire s1_update_u_mask_4_0; // @[tage.scala:241:35]
wire s1_update_u_mask_4_1; // @[tage.scala:241:35]
wire s1_update_u_mask_4_2; // @[tage.scala:241:35]
wire s1_update_u_mask_4_3; // @[tage.scala:241:35]
wire s1_update_u_mask_5_0; // @[tage.scala:241:35]
wire s1_update_u_mask_5_1; // @[tage.scala:241:35]
wire s1_update_u_mask_5_2; // @[tage.scala:241:35]
wire s1_update_u_mask_5_3; // @[tage.scala:241:35]
wire s1_update_taken_0_0; // @[tage.scala:243:31]
wire s1_update_taken_0_1; // @[tage.scala:243:31]
wire s1_update_taken_0_2; // @[tage.scala:243:31]
wire s1_update_taken_0_3; // @[tage.scala:243:31]
wire s1_update_taken_1_0; // @[tage.scala:243:31]
wire s1_update_taken_1_1; // @[tage.scala:243:31]
wire s1_update_taken_1_2; // @[tage.scala:243:31]
wire s1_update_taken_1_3; // @[tage.scala:243:31]
wire s1_update_taken_2_0; // @[tage.scala:243:31]
wire s1_update_taken_2_1; // @[tage.scala:243:31]
wire s1_update_taken_2_2; // @[tage.scala:243:31]
wire s1_update_taken_2_3; // @[tage.scala:243:31]
wire s1_update_taken_3_0; // @[tage.scala:243:31]
wire s1_update_taken_3_1; // @[tage.scala:243:31]
wire s1_update_taken_3_2; // @[tage.scala:243:31]
wire s1_update_taken_3_3; // @[tage.scala:243:31]
wire s1_update_taken_4_0; // @[tage.scala:243:31]
wire s1_update_taken_4_1; // @[tage.scala:243:31]
wire s1_update_taken_4_2; // @[tage.scala:243:31]
wire s1_update_taken_4_3; // @[tage.scala:243:31]
wire s1_update_taken_5_0; // @[tage.scala:243:31]
wire s1_update_taken_5_1; // @[tage.scala:243:31]
wire s1_update_taken_5_2; // @[tage.scala:243:31]
wire s1_update_taken_5_3; // @[tage.scala:243:31]
wire s1_update_alloc_0_0; // @[tage.scala:245:31]
wire s1_update_alloc_0_1; // @[tage.scala:245:31]
wire s1_update_alloc_0_2; // @[tage.scala:245:31]
wire s1_update_alloc_0_3; // @[tage.scala:245:31]
wire s1_update_alloc_1_0; // @[tage.scala:245:31]
wire s1_update_alloc_1_1; // @[tage.scala:245:31]
wire s1_update_alloc_1_2; // @[tage.scala:245:31]
wire s1_update_alloc_1_3; // @[tage.scala:245:31]
wire s1_update_alloc_2_0; // @[tage.scala:245:31]
wire s1_update_alloc_2_1; // @[tage.scala:245:31]
wire s1_update_alloc_2_2; // @[tage.scala:245:31]
wire s1_update_alloc_2_3; // @[tage.scala:245:31]
wire s1_update_alloc_3_0; // @[tage.scala:245:31]
wire s1_update_alloc_3_1; // @[tage.scala:245:31]
wire s1_update_alloc_3_2; // @[tage.scala:245:31]
wire s1_update_alloc_3_3; // @[tage.scala:245:31]
wire s1_update_alloc_4_0; // @[tage.scala:245:31]
wire s1_update_alloc_4_1; // @[tage.scala:245:31]
wire s1_update_alloc_4_2; // @[tage.scala:245:31]
wire s1_update_alloc_4_3; // @[tage.scala:245:31]
wire s1_update_alloc_5_0; // @[tage.scala:245:31]
wire s1_update_alloc_5_1; // @[tage.scala:245:31]
wire s1_update_alloc_5_2; // @[tage.scala:245:31]
wire s1_update_alloc_5_3; // @[tage.scala:245:31]
wire [1:0] s1_update_u_0_0; // @[tage.scala:246:31]
wire [1:0] s1_update_u_0_1; // @[tage.scala:246:31]
wire [1:0] s1_update_u_0_2; // @[tage.scala:246:31]
wire [1:0] s1_update_u_0_3; // @[tage.scala:246:31]
wire [1:0] s1_update_u_1_0; // @[tage.scala:246:31]
wire [1:0] s1_update_u_1_1; // @[tage.scala:246:31]
wire [1:0] s1_update_u_1_2; // @[tage.scala:246:31]
wire [1:0] s1_update_u_1_3; // @[tage.scala:246:31]
wire [1:0] s1_update_u_2_0; // @[tage.scala:246:31]
wire [1:0] s1_update_u_2_1; // @[tage.scala:246:31]
wire [1:0] s1_update_u_2_2; // @[tage.scala:246:31]
wire [1:0] s1_update_u_2_3; // @[tage.scala:246:31]
wire [1:0] s1_update_u_3_0; // @[tage.scala:246:31]
wire [1:0] s1_update_u_3_1; // @[tage.scala:246:31]
wire [1:0] s1_update_u_3_2; // @[tage.scala:246:31]
wire [1:0] s1_update_u_3_3; // @[tage.scala:246:31]
wire [1:0] s1_update_u_4_0; // @[tage.scala:246:31]
wire [1:0] s1_update_u_4_1; // @[tage.scala:246:31]
wire [1:0] s1_update_u_4_2; // @[tage.scala:246:31]
wire [1:0] s1_update_u_4_3; // @[tage.scala:246:31]
wire [1:0] s1_update_u_5_0; // @[tage.scala:246:31]
wire [1:0] s1_update_u_5_1; // @[tage.scala:246:31]
wire [1:0] s1_update_u_5_2; // @[tage.scala:246:31]
wire [1:0] s1_update_u_5_3; // @[tage.scala:246:31]
wire final_altpred; // @[tage.scala:256:33]
wire _io_resp_f3_0_taken_T = f3_resps_0_0_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40]
wire _io_resp_f3_0_taken_T_1 = f3_resps_0_0_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55]
wire _io_resp_f3_0_taken_T_2 = _io_resp_f3_0_taken_T | _io_resp_f3_0_taken_T_1; // @[tage.scala:265:{40,48,55}]
wire _io_resp_f3_0_taken_T_3 = f3_resps_0_0_bits_ctr[2]; // @[tage.scala:234:25, :265:76]
wire _io_resp_f3_0_taken_T_4 = _io_resp_f3_0_taken_T_2 ? io_resp_in_0_f3_0_taken_0 : _io_resp_f3_0_taken_T_3; // @[tage.scala:198:7, :265:{35,48,76}]
wire _T_17 = f3_resps_0_0_valid ? f3_resps_0_0_bits_ctr[2] : io_resp_in_0_f3_0_taken_0; // @[tage.scala:198:7, :234:25, :271:{21,50}]
wire _io_resp_f3_0_taken_T_5 = f3_resps_1_0_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40]
wire _io_resp_f3_0_taken_T_6 = f3_resps_1_0_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55]
wire _io_resp_f3_0_taken_T_7 = _io_resp_f3_0_taken_T_5 | _io_resp_f3_0_taken_T_6; // @[tage.scala:265:{40,48,55}]
wire _io_resp_f3_0_taken_T_8 = f3_resps_1_0_bits_ctr[2]; // @[tage.scala:234:25, :265:76]
wire _io_resp_f3_0_taken_T_9 = _io_resp_f3_0_taken_T_7 ? _T_17 : _io_resp_f3_0_taken_T_8; // @[tage.scala:265:{35,48,76}, :271:21]
wire _T_21 = f3_resps_1_0_valid ? f3_resps_1_0_bits_ctr[2] : _T_17; // @[tage.scala:234:25, :271:{21,50}]
wire _io_resp_f3_0_taken_T_10 = f3_resps_2_0_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40]
wire _io_resp_f3_0_taken_T_11 = f3_resps_2_0_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55]
wire _io_resp_f3_0_taken_T_12 = _io_resp_f3_0_taken_T_10 | _io_resp_f3_0_taken_T_11; // @[tage.scala:265:{40,48,55}]
wire _io_resp_f3_0_taken_T_13 = f3_resps_2_0_bits_ctr[2]; // @[tage.scala:234:25, :265:76]
wire _io_resp_f3_0_taken_T_14 = _io_resp_f3_0_taken_T_12 ? _T_21 : _io_resp_f3_0_taken_T_13; // @[tage.scala:265:{35,48,76}, :271:21]
wire _T_25 = f3_resps_2_0_valid ? f3_resps_2_0_bits_ctr[2] : _T_21; // @[tage.scala:234:25, :271:{21,50}]
wire _io_resp_f3_0_taken_T_15 = f3_resps_3_0_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40]
wire _io_resp_f3_0_taken_T_16 = f3_resps_3_0_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55]
wire _io_resp_f3_0_taken_T_17 = _io_resp_f3_0_taken_T_15 | _io_resp_f3_0_taken_T_16; // @[tage.scala:265:{40,48,55}]
wire _io_resp_f3_0_taken_T_18 = f3_resps_3_0_bits_ctr[2]; // @[tage.scala:234:25, :265:76]
wire _io_resp_f3_0_taken_T_19 = _io_resp_f3_0_taken_T_17 ? _T_25 : _io_resp_f3_0_taken_T_18; // @[tage.scala:265:{35,48,76}, :271:21]
wire _T_29 = f3_resps_3_0_valid ? f3_resps_3_0_bits_ctr[2] : _T_25; // @[tage.scala:234:25, :271:{21,50}]
wire _io_resp_f3_0_taken_T_20 = f3_resps_4_0_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40]
wire _io_resp_f3_0_taken_T_21 = f3_resps_4_0_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55]
wire _io_resp_f3_0_taken_T_22 = _io_resp_f3_0_taken_T_20 | _io_resp_f3_0_taken_T_21; // @[tage.scala:265:{40,48,55}]
wire _io_resp_f3_0_taken_T_23 = f3_resps_4_0_bits_ctr[2]; // @[tage.scala:234:25, :265:76]
wire _io_resp_f3_0_taken_T_24 = _io_resp_f3_0_taken_T_22 ? _T_29 : _io_resp_f3_0_taken_T_23; // @[tage.scala:265:{35,48,76}, :271:21]
wire _T_33 = f3_resps_4_0_valid ? f3_resps_4_0_bits_ctr[2] : _T_29; // @[tage.scala:234:25, :271:{21,50}]
wire _io_resp_f3_0_taken_T_25 = f3_resps_5_0_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40]
wire _io_resp_f3_0_taken_T_26 = f3_resps_5_0_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55]
wire _io_resp_f3_0_taken_T_27 = _io_resp_f3_0_taken_T_25 | _io_resp_f3_0_taken_T_26; // @[tage.scala:265:{40,48,55}]
wire _io_resp_f3_0_taken_T_28 = f3_resps_5_0_bits_ctr[2]; // @[tage.scala:234:25, :265:76]
wire _io_resp_f3_0_taken_T_29 = _io_resp_f3_0_taken_T_27 ? _T_33 : _io_resp_f3_0_taken_T_28; // @[tage.scala:265:{35,48,76}, :271:21]
assign io_resp_f3_0_taken_0 = f3_resps_5_0_valid ? _io_resp_f3_0_taken_T_29 : f3_resps_4_0_valid ? _io_resp_f3_0_taken_T_24 : f3_resps_3_0_valid ? _io_resp_f3_0_taken_T_19 : f3_resps_2_0_valid ? _io_resp_f3_0_taken_T_14 : f3_resps_1_0_valid ? _io_resp_f3_0_taken_T_9 : f3_resps_0_0_valid ? _io_resp_f3_0_taken_T_4 : io_resp_in_0_f3_0_taken_0; // @[tage.scala:198:7, :234:25, :259:25, :264:18, :265:{29,35}]
assign final_altpred = f3_resps_5_0_valid ? _T_33 : f3_resps_4_0_valid ? _T_29 : f3_resps_3_0_valid ? _T_25 : f3_resps_2_0_valid ? _T_21 : f3_resps_1_0_valid & f3_resps_0_0_valid ? f3_resps_0_0_bits_ctr[2] : io_resp_in_0_f3_0_taken_0; // @[tage.scala:198:7, :234:25, :256:33, :264:18, :266:29, :271:{21,50}]
assign f3_meta_provider_0_valid = f3_resps_0_0_valid | f3_resps_1_0_valid | f3_resps_2_0_valid | f3_resps_3_0_valid | f3_resps_4_0_valid | f3_resps_5_0_valid; // @[tage.scala:212:21, :234:25, :269:27]
assign f3_meta_provider_0_bits = f3_resps_5_0_valid ? 3'h5 : f3_resps_4_0_valid ? 3'h4 : {1'h0, f3_resps_3_0_valid ? 2'h3 : f3_resps_2_0_valid ? 2'h2 : {1'h0, f3_resps_1_0_valid}}; // @[tage.scala:212:21, :234:25, :270:21]
assign _f3_meta_alt_differs_0_T = final_altpred != io_resp_f3_0_taken_0; // @[tage.scala:198:7, :256:33, :275:48]
assign f3_meta_alt_differs_0 = _f3_meta_alt_differs_0_T; // @[tage.scala:212:21, :275:48]
wire [7:0][2:0] _GEN_5 = {{f3_resps_0_0_bits_ctr}, {f3_resps_0_0_bits_ctr}, {f3_resps_5_0_bits_ctr}, {f3_resps_4_0_bits_ctr}, {f3_resps_3_0_bits_ctr}, {f3_resps_2_0_bits_ctr}, {f3_resps_1_0_bits_ctr}, {f3_resps_0_0_bits_ctr}}; // @[tage.scala:234:25, :276:31]
assign f3_meta_provider_ctr_0 = _GEN_5[f3_meta_provider_0_bits]; // @[tage.scala:212:21, :276:31]
wire [7:0][1:0] _GEN_6 = {{f3_resps_0_0_bits_u}, {f3_resps_0_0_bits_u}, {f3_resps_5_0_bits_u}, {f3_resps_4_0_bits_u}, {f3_resps_3_0_bits_u}, {f3_resps_2_0_bits_u}, {f3_resps_1_0_bits_u}, {f3_resps_0_0_bits_u}}; // @[tage.scala:234:25, :276:31]
assign f3_meta_provider_u_0 = _GEN_6[f3_meta_provider_0_bits]; // @[tage.scala:212:21, :276:31]
wire _allocatable_slots_T = ~f3_resps_0_0_valid; // @[tage.scala:234:25, :282:33]
wire _allocatable_slots_T_1 = f3_resps_0_0_bits_u == 2'h0; // @[tage.scala:234:25, :282:60]
wire _allocatable_slots_T_2 = _allocatable_slots_T & _allocatable_slots_T_1; // @[tage.scala:282:{33,45,60}]
wire _allocatable_slots_WIRE_0 = _allocatable_slots_T_2; // @[tage.scala:282:{14,45}]
wire _allocatable_slots_T_3 = ~f3_resps_1_0_valid; // @[tage.scala:234:25, :282:33]
wire _allocatable_slots_T_4 = f3_resps_1_0_bits_u == 2'h0; // @[tage.scala:234:25, :282:60]
wire _allocatable_slots_T_5 = _allocatable_slots_T_3 & _allocatable_slots_T_4; // @[tage.scala:282:{33,45,60}]
wire _allocatable_slots_WIRE_1 = _allocatable_slots_T_5; // @[tage.scala:282:{14,45}]
wire _allocatable_slots_T_6 = ~f3_resps_2_0_valid; // @[tage.scala:234:25, :282:33]
wire _allocatable_slots_T_7 = f3_resps_2_0_bits_u == 2'h0; // @[tage.scala:234:25, :282:60]
wire _allocatable_slots_T_8 = _allocatable_slots_T_6 & _allocatable_slots_T_7; // @[tage.scala:282:{33,45,60}]
wire _allocatable_slots_WIRE_2 = _allocatable_slots_T_8; // @[tage.scala:282:{14,45}]
wire _allocatable_slots_T_9 = ~f3_resps_3_0_valid; // @[tage.scala:234:25, :282:33]
wire _allocatable_slots_T_10 = f3_resps_3_0_bits_u == 2'h0; // @[tage.scala:234:25, :282:60]
wire _allocatable_slots_T_11 = _allocatable_slots_T_9 & _allocatable_slots_T_10; // @[tage.scala:282:{33,45,60}]
wire _allocatable_slots_WIRE_3 = _allocatable_slots_T_11; // @[tage.scala:282:{14,45}]
wire _allocatable_slots_T_12 = ~f3_resps_4_0_valid; // @[tage.scala:234:25, :282:33]
wire _allocatable_slots_T_13 = f3_resps_4_0_bits_u == 2'h0; // @[tage.scala:234:25, :282:60]
wire _allocatable_slots_T_14 = _allocatable_slots_T_12 & _allocatable_slots_T_13; // @[tage.scala:282:{33,45,60}]
wire _allocatable_slots_WIRE_4 = _allocatable_slots_T_14; // @[tage.scala:282:{14,45}]
wire _allocatable_slots_T_15 = ~f3_resps_5_0_valid; // @[tage.scala:234:25, :282:33]
wire _allocatable_slots_T_16 = f3_resps_5_0_bits_u == 2'h0; // @[tage.scala:234:25, :282:60]
wire _allocatable_slots_T_17 = _allocatable_slots_T_15 & _allocatable_slots_T_16; // @[tage.scala:282:{33,45,60}]
wire _allocatable_slots_WIRE_5 = _allocatable_slots_T_17; // @[tage.scala:282:{14,45}]
wire [1:0] allocatable_slots_lo_hi = {_allocatable_slots_WIRE_2, _allocatable_slots_WIRE_1}; // @[tage.scala:282:{14,70}]
wire [2:0] allocatable_slots_lo = {allocatable_slots_lo_hi, _allocatable_slots_WIRE_0}; // @[tage.scala:282:{14,70}]
wire [1:0] allocatable_slots_hi_hi = {_allocatable_slots_WIRE_5, _allocatable_slots_WIRE_4}; // @[tage.scala:282:{14,70}]
wire [2:0] allocatable_slots_hi = {allocatable_slots_hi_hi, _allocatable_slots_WIRE_3}; // @[tage.scala:282:{14,70}]
wire [5:0] _allocatable_slots_T_18 = {allocatable_slots_hi, allocatable_slots_lo}; // @[tage.scala:282:70]
wire [7:0] _allocatable_slots_T_19 = 8'h1 << f3_meta_provider_0_bits; // @[OneHot.scala:58:35]
wire [7:0] _allocatable_slots_T_20 = _allocatable_slots_T_19; // @[OneHot.scala:58:35]
wire [7:0] _allocatable_slots_T_21 = {1'h0, _allocatable_slots_T_19[7:1]}; // @[OneHot.scala:58:35]
wire [7:0] _allocatable_slots_T_22 = {2'h0, _allocatable_slots_T_19[7:2]}; // @[OneHot.scala:58:35]
wire [7:0] _allocatable_slots_T_23 = {3'h0, _allocatable_slots_T_19[7:3]}; // @[OneHot.scala:58:35]
wire [7:0] _allocatable_slots_T_24 = {4'h0, _allocatable_slots_T_19[7:4]}; // @[OneHot.scala:58:35]
wire [7:0] _allocatable_slots_T_25 = {5'h0, _allocatable_slots_T_19[7:5]}; // @[OneHot.scala:58:35]
wire [7:0] _allocatable_slots_T_26 = {6'h0, _allocatable_slots_T_19[7:6]}; // @[OneHot.scala:58:35]
wire [7:0] _allocatable_slots_T_27 = {7'h0, _allocatable_slots_T_19[7]}; // @[OneHot.scala:58:35]
wire [7:0] _allocatable_slots_T_28 = _allocatable_slots_T_20 | _allocatable_slots_T_21; // @[util.scala:373:{29,45}]
wire [7:0] _allocatable_slots_T_29 = _allocatable_slots_T_28 | _allocatable_slots_T_22; // @[util.scala:373:{29,45}]
wire [7:0] _allocatable_slots_T_30 = _allocatable_slots_T_29 | _allocatable_slots_T_23; // @[util.scala:373:{29,45}]
wire [7:0] _allocatable_slots_T_31 = _allocatable_slots_T_30 | _allocatable_slots_T_24; // @[util.scala:373:{29,45}]
wire [7:0] _allocatable_slots_T_32 = _allocatable_slots_T_31 | _allocatable_slots_T_25; // @[util.scala:373:{29,45}]
wire [7:0] _allocatable_slots_T_33 = _allocatable_slots_T_32 | _allocatable_slots_T_26; // @[util.scala:373:{29,45}]
wire [7:0] _allocatable_slots_T_34 = _allocatable_slots_T_33 | _allocatable_slots_T_27; // @[util.scala:373:{29,45}]
wire [5:0] _allocatable_slots_T_35 = {6{f3_meta_provider_0_valid}}; // @[tage.scala:212:21, :283:45]
wire [7:0] _allocatable_slots_T_36 = {2'h0, _allocatable_slots_T_34[5:0] & _allocatable_slots_T_35}; // @[util.scala:373:45]
wire [7:0] _allocatable_slots_T_37 = ~_allocatable_slots_T_36; // @[tage.scala:283:{7,39}]
wire [7:0] allocatable_slots = {2'h0, _allocatable_slots_T_37[5:0] & _allocatable_slots_T_18}; // @[tage.scala:282:{70,77}, :283:7]
wire [1:0] alloc_lfsr_lo_hi = {_alloc_lfsr_prng_io_out_2, _alloc_lfsr_prng_io_out_1}; // @[PRNG.scala:91:22, :95:17]
wire [2:0] alloc_lfsr_lo = {alloc_lfsr_lo_hi, _alloc_lfsr_prng_io_out_0}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] alloc_lfsr_hi_hi = {_alloc_lfsr_prng_io_out_5, _alloc_lfsr_prng_io_out_4}; // @[PRNG.scala:91:22, :95:17]
wire [2:0] alloc_lfsr_hi = {alloc_lfsr_hi_hi, _alloc_lfsr_prng_io_out_3}; // @[PRNG.scala:91:22, :95:17]
wire [5:0] alloc_lfsr = {alloc_lfsr_hi, alloc_lfsr_lo}; // @[PRNG.scala:95:17]
wire _first_entry_T = allocatable_slots[0]; // @[OneHot.scala:48:45]
wire _first_entry_T_1 = allocatable_slots[1]; // @[OneHot.scala:48:45]
wire _first_entry_T_2 = allocatable_slots[2]; // @[OneHot.scala:48:45]
wire _first_entry_T_3 = allocatable_slots[3]; // @[OneHot.scala:48:45]
wire _first_entry_T_4 = allocatable_slots[4]; // @[OneHot.scala:48:45]
wire _first_entry_T_5 = allocatable_slots[5]; // @[OneHot.scala:48:45]
wire _first_entry_T_6 = allocatable_slots[6]; // @[OneHot.scala:48:45]
wire _first_entry_T_7 = allocatable_slots[7]; // @[OneHot.scala:48:45]
wire [2:0] _first_entry_T_8 = {2'h3, ~_first_entry_T_6}; // @[OneHot.scala:48:45]
wire [2:0] _first_entry_T_9 = _first_entry_T_5 ? 3'h5 : _first_entry_T_8; // @[OneHot.scala:48:45]
wire [2:0] _first_entry_T_10 = _first_entry_T_4 ? 3'h4 : _first_entry_T_9; // @[OneHot.scala:48:45]
wire [2:0] _first_entry_T_11 = _first_entry_T_3 ? 3'h3 : _first_entry_T_10; // @[OneHot.scala:48:45]
wire [2:0] _first_entry_T_12 = _first_entry_T_2 ? 3'h2 : _first_entry_T_11; // @[OneHot.scala:48:45]
wire [2:0] _first_entry_T_13 = _first_entry_T_1 ? 3'h1 : _first_entry_T_12; // @[OneHot.scala:48:45]
wire [2:0] first_entry = _first_entry_T ? 3'h0 : _first_entry_T_13; // @[OneHot.scala:48:45]
wire [7:0] _masked_entry_T = {2'h0, allocatable_slots[5:0] & alloc_lfsr}; // @[PRNG.scala:95:17]
wire _masked_entry_T_1 = _masked_entry_T[0]; // @[OneHot.scala:48:45]
wire _masked_entry_T_2 = _masked_entry_T[1]; // @[OneHot.scala:48:45]
wire _masked_entry_T_3 = _masked_entry_T[2]; // @[OneHot.scala:48:45]
wire _masked_entry_T_4 = _masked_entry_T[3]; // @[OneHot.scala:48:45]
wire _masked_entry_T_5 = _masked_entry_T[4]; // @[OneHot.scala:48:45]
wire _masked_entry_T_6 = _masked_entry_T[5]; // @[OneHot.scala:48:45]
wire _masked_entry_T_7 = _masked_entry_T[6]; // @[OneHot.scala:48:45]
wire _masked_entry_T_8 = _masked_entry_T[7]; // @[OneHot.scala:48:45]
wire [2:0] _masked_entry_T_9 = {2'h3, ~_masked_entry_T_7}; // @[OneHot.scala:48:45]
wire [2:0] _masked_entry_T_10 = _masked_entry_T_6 ? 3'h5 : _masked_entry_T_9; // @[OneHot.scala:48:45]
wire [2:0] _masked_entry_T_11 = _masked_entry_T_5 ? 3'h4 : _masked_entry_T_10; // @[OneHot.scala:48:45]
wire [2:0] _masked_entry_T_12 = _masked_entry_T_4 ? 3'h3 : _masked_entry_T_11; // @[OneHot.scala:48:45]
wire [2:0] _masked_entry_T_13 = _masked_entry_T_3 ? 3'h2 : _masked_entry_T_12; // @[OneHot.scala:48:45]
wire [2:0] _masked_entry_T_14 = _masked_entry_T_2 ? 3'h1 : _masked_entry_T_13; // @[OneHot.scala:48:45]
wire [2:0] masked_entry = _masked_entry_T_1 ? 3'h0 : _masked_entry_T_14; // @[OneHot.scala:48:45]
wire [7:0] _alloc_entry_T = allocatable_slots >> masked_entry; // @[Mux.scala:50:70]
wire _alloc_entry_T_1 = _alloc_entry_T[0]; // @[tage.scala:289:44]
assign alloc_entry = _alloc_entry_T_1 ? masked_entry : first_entry; // @[Mux.scala:50:70]
assign f3_meta_allocate_0_bits = alloc_entry; // @[tage.scala:212:21, :289:26]
assign _f3_meta_allocate_0_valid_T = |allocatable_slots; // @[tage.scala:282:77, :293:52]
assign f3_meta_allocate_0_valid = _f3_meta_allocate_0_valid_T; // @[tage.scala:212:21, :293:52]
wire _update_was_taken_T = s1_update_bits_cfi_idx_bits == 2'h0; // @[tage.scala:297:58]
wire _update_was_taken_T_1 = s1_update_bits_cfi_idx_valid & _update_was_taken_T; // @[tage.scala:296:58, :297:58]
wire update_was_taken = _update_was_taken_T_1 & s1_update_bits_cfi_taken; // @[tage.scala:296:58, :297:67]
wire [4:0] _GEN_7 = {s1_update_bits_is_mispredict_update | s1_update_bits_is_repair_update, s1_update_bits_btb_mispredicts}; // @[predictor.scala:94:50, :96:{49,69}, :184:30]
wire _T_44 = s1_update_bits_br_mask[0] & s1_update_valid & _GEN_7 == 5'h0; // @[OneHot.scala:58:35]
wire _GEN_8 = _T_44 & s1_update_meta_provider_0_valid & s1_update_meta_provider_0_bits == 3'h0; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37]
wire _GEN_9 = _T_44 & s1_update_meta_provider_0_valid & s1_update_meta_provider_0_bits == 3'h1; // @[tage.scala:218:43, :236:52, :240:33, :299:{37,56,92}, :300:47, :303:37]
wire _GEN_10 = _T_44 & s1_update_meta_provider_0_valid & s1_update_meta_provider_0_bits == 3'h2; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37]
wire _GEN_11 = _T_44 & s1_update_meta_provider_0_valid & s1_update_meta_provider_0_bits == 3'h3; // @[tage.scala:236:52, :240:33, :265:40, :299:{37,56,92}, :300:47, :303:37]
wire _GEN_12 = _T_44 & s1_update_meta_provider_0_valid & s1_update_meta_provider_0_bits == 3'h4; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37]
wire _GEN_13 = _T_44 & s1_update_meta_provider_0_valid & s1_update_meta_provider_0_bits == 3'h5; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37]
wire _new_u_T = s1_update_mispredict_mask[0]; // @[tage.scala:237:73, :308:52]
wire _new_u_T_1 = ~s1_update_meta_alt_differs_0; // @[tage.scala:217:9, :236:52]
wire _new_u_T_2 = s1_update_meta_provider_u_0 == 2'h0; // @[tage.scala:218:27, :236:52]
wire [2:0] _GEN_14 = {1'h0, s1_update_meta_provider_u_0}; // @[tage.scala:218:43, :236:52]
wire [2:0] _new_u_T_3 = _GEN_14 - 3'h1; // @[tage.scala:218:43]
wire [1:0] _new_u_T_4 = _new_u_T_3[1:0]; // @[tage.scala:218:43]
wire [1:0] _new_u_T_5 = _new_u_T_2 ? 2'h0 : _new_u_T_4; // @[tage.scala:218:{24,27,43}]
wire _new_u_T_6 = &s1_update_meta_provider_u_0; // @[tage.scala:219:27, :236:52]
wire [2:0] _new_u_T_7 = _GEN_14 + 3'h1; // @[tage.scala:218:43, :219:43]
wire [1:0] _new_u_T_8 = _new_u_T_7[1:0]; // @[tage.scala:219:43]
wire [1:0] _new_u_T_9 = _new_u_T_6 ? 2'h3 : _new_u_T_8; // @[tage.scala:219:{24,27,43}]
wire [1:0] _new_u_T_10 = _new_u_T ? _new_u_T_5 : _new_u_T_9; // @[tage.scala:218:{8,24}, :219:24, :308:52]
wire [1:0] new_u = _new_u_T_1 ? s1_update_meta_provider_u_0 : _new_u_T_10; // @[tage.scala:217:{8,9}, :218:8, :236:52]
wire final_altpred_1; // @[tage.scala:256:33]
wire _io_resp_f3_1_taken_T = f3_resps_0_1_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40]
wire _io_resp_f3_1_taken_T_1 = f3_resps_0_1_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55]
wire _io_resp_f3_1_taken_T_2 = _io_resp_f3_1_taken_T | _io_resp_f3_1_taken_T_1; // @[tage.scala:265:{40,48,55}]
wire _io_resp_f3_1_taken_T_3 = f3_resps_0_1_bits_ctr[2]; // @[tage.scala:234:25, :265:76]
wire _io_resp_f3_1_taken_T_4 = _io_resp_f3_1_taken_T_2 ? io_resp_in_0_f3_1_taken_0 : _io_resp_f3_1_taken_T_3; // @[tage.scala:198:7, :265:{35,48,76}]
wire _T_48 = f3_resps_0_1_valid ? f3_resps_0_1_bits_ctr[2] : io_resp_in_0_f3_1_taken_0; // @[tage.scala:198:7, :234:25, :271:{21,50}]
wire _io_resp_f3_1_taken_T_5 = f3_resps_1_1_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40]
wire _io_resp_f3_1_taken_T_6 = f3_resps_1_1_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55]
wire _io_resp_f3_1_taken_T_7 = _io_resp_f3_1_taken_T_5 | _io_resp_f3_1_taken_T_6; // @[tage.scala:265:{40,48,55}]
wire _io_resp_f3_1_taken_T_8 = f3_resps_1_1_bits_ctr[2]; // @[tage.scala:234:25, :265:76]
wire _io_resp_f3_1_taken_T_9 = _io_resp_f3_1_taken_T_7 ? _T_48 : _io_resp_f3_1_taken_T_8; // @[tage.scala:265:{35,48,76}, :271:21]
wire _T_52 = f3_resps_1_1_valid ? f3_resps_1_1_bits_ctr[2] : _T_48; // @[tage.scala:234:25, :271:{21,50}]
wire _io_resp_f3_1_taken_T_10 = f3_resps_2_1_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40]
wire _io_resp_f3_1_taken_T_11 = f3_resps_2_1_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55]
wire _io_resp_f3_1_taken_T_12 = _io_resp_f3_1_taken_T_10 | _io_resp_f3_1_taken_T_11; // @[tage.scala:265:{40,48,55}]
wire _io_resp_f3_1_taken_T_13 = f3_resps_2_1_bits_ctr[2]; // @[tage.scala:234:25, :265:76]
wire _io_resp_f3_1_taken_T_14 = _io_resp_f3_1_taken_T_12 ? _T_52 : _io_resp_f3_1_taken_T_13; // @[tage.scala:265:{35,48,76}, :271:21]
wire _T_56 = f3_resps_2_1_valid ? f3_resps_2_1_bits_ctr[2] : _T_52; // @[tage.scala:234:25, :271:{21,50}]
wire _io_resp_f3_1_taken_T_15 = f3_resps_3_1_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40]
wire _io_resp_f3_1_taken_T_16 = f3_resps_3_1_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55]
wire _io_resp_f3_1_taken_T_17 = _io_resp_f3_1_taken_T_15 | _io_resp_f3_1_taken_T_16; // @[tage.scala:265:{40,48,55}]
wire _io_resp_f3_1_taken_T_18 = f3_resps_3_1_bits_ctr[2]; // @[tage.scala:234:25, :265:76]
wire _io_resp_f3_1_taken_T_19 = _io_resp_f3_1_taken_T_17 ? _T_56 : _io_resp_f3_1_taken_T_18; // @[tage.scala:265:{35,48,76}, :271:21]
wire _T_60 = f3_resps_3_1_valid ? f3_resps_3_1_bits_ctr[2] : _T_56; // @[tage.scala:234:25, :271:{21,50}]
wire _io_resp_f3_1_taken_T_20 = f3_resps_4_1_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40]
wire _io_resp_f3_1_taken_T_21 = f3_resps_4_1_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55]
wire _io_resp_f3_1_taken_T_22 = _io_resp_f3_1_taken_T_20 | _io_resp_f3_1_taken_T_21; // @[tage.scala:265:{40,48,55}]
wire _io_resp_f3_1_taken_T_23 = f3_resps_4_1_bits_ctr[2]; // @[tage.scala:234:25, :265:76]
wire _io_resp_f3_1_taken_T_24 = _io_resp_f3_1_taken_T_22 ? _T_60 : _io_resp_f3_1_taken_T_23; // @[tage.scala:265:{35,48,76}, :271:21]
wire _T_64 = f3_resps_4_1_valid ? f3_resps_4_1_bits_ctr[2] : _T_60; // @[tage.scala:234:25, :271:{21,50}]
wire _io_resp_f3_1_taken_T_25 = f3_resps_5_1_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40]
wire _io_resp_f3_1_taken_T_26 = f3_resps_5_1_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55]
wire _io_resp_f3_1_taken_T_27 = _io_resp_f3_1_taken_T_25 | _io_resp_f3_1_taken_T_26; // @[tage.scala:265:{40,48,55}]
wire _io_resp_f3_1_taken_T_28 = f3_resps_5_1_bits_ctr[2]; // @[tage.scala:234:25, :265:76]
wire _io_resp_f3_1_taken_T_29 = _io_resp_f3_1_taken_T_27 ? _T_64 : _io_resp_f3_1_taken_T_28; // @[tage.scala:265:{35,48,76}, :271:21]
assign io_resp_f3_1_taken_0 = f3_resps_5_1_valid ? _io_resp_f3_1_taken_T_29 : f3_resps_4_1_valid ? _io_resp_f3_1_taken_T_24 : f3_resps_3_1_valid ? _io_resp_f3_1_taken_T_19 : f3_resps_2_1_valid ? _io_resp_f3_1_taken_T_14 : f3_resps_1_1_valid ? _io_resp_f3_1_taken_T_9 : f3_resps_0_1_valid ? _io_resp_f3_1_taken_T_4 : io_resp_in_0_f3_1_taken_0; // @[tage.scala:198:7, :234:25, :259:25, :264:18, :265:{29,35}]
assign final_altpred_1 = f3_resps_5_1_valid ? _T_64 : f3_resps_4_1_valid ? _T_60 : f3_resps_3_1_valid ? _T_56 : f3_resps_2_1_valid ? _T_52 : f3_resps_1_1_valid & f3_resps_0_1_valid ? f3_resps_0_1_bits_ctr[2] : io_resp_in_0_f3_1_taken_0; // @[tage.scala:198:7, :234:25, :256:33, :264:18, :266:29, :271:{21,50}]
assign f3_meta_provider_1_valid = f3_resps_0_1_valid | f3_resps_1_1_valid | f3_resps_2_1_valid | f3_resps_3_1_valid | f3_resps_4_1_valid | f3_resps_5_1_valid; // @[tage.scala:212:21, :234:25, :269:27]
assign f3_meta_provider_1_bits = f3_resps_5_1_valid ? 3'h5 : f3_resps_4_1_valid ? 3'h4 : {1'h0, f3_resps_3_1_valid ? 2'h3 : f3_resps_2_1_valid ? 2'h2 : {1'h0, f3_resps_1_1_valid}}; // @[tage.scala:212:21, :234:25, :270:21]
assign _f3_meta_alt_differs_1_T = final_altpred_1 != io_resp_f3_1_taken_0; // @[tage.scala:198:7, :256:33, :275:48]
assign f3_meta_alt_differs_1 = _f3_meta_alt_differs_1_T; // @[tage.scala:212:21, :275:48]
wire [7:0][2:0] _GEN_15 = {{f3_resps_0_1_bits_ctr}, {f3_resps_0_1_bits_ctr}, {f3_resps_5_1_bits_ctr}, {f3_resps_4_1_bits_ctr}, {f3_resps_3_1_bits_ctr}, {f3_resps_2_1_bits_ctr}, {f3_resps_1_1_bits_ctr}, {f3_resps_0_1_bits_ctr}}; // @[tage.scala:234:25, :276:31]
assign f3_meta_provider_ctr_1 = _GEN_15[f3_meta_provider_1_bits]; // @[tage.scala:212:21, :276:31]
wire [7:0][1:0] _GEN_16 = {{f3_resps_0_1_bits_u}, {f3_resps_0_1_bits_u}, {f3_resps_5_1_bits_u}, {f3_resps_4_1_bits_u}, {f3_resps_3_1_bits_u}, {f3_resps_2_1_bits_u}, {f3_resps_1_1_bits_u}, {f3_resps_0_1_bits_u}}; // @[tage.scala:234:25, :276:31]
assign f3_meta_provider_u_1 = _GEN_16[f3_meta_provider_1_bits]; // @[tage.scala:212:21, :276:31]
wire _allocatable_slots_T_38 = ~f3_resps_0_1_valid; // @[tage.scala:234:25, :282:33]
wire _allocatable_slots_T_39 = f3_resps_0_1_bits_u == 2'h0; // @[tage.scala:234:25, :282:60]
wire _allocatable_slots_T_40 = _allocatable_slots_T_38 & _allocatable_slots_T_39; // @[tage.scala:282:{33,45,60}]
wire _allocatable_slots_WIRE_1_0 = _allocatable_slots_T_40; // @[tage.scala:282:{14,45}]
wire _allocatable_slots_T_41 = ~f3_resps_1_1_valid; // @[tage.scala:234:25, :282:33]
wire _allocatable_slots_T_42 = f3_resps_1_1_bits_u == 2'h0; // @[tage.scala:234:25, :282:60]
wire _allocatable_slots_T_43 = _allocatable_slots_T_41 & _allocatable_slots_T_42; // @[tage.scala:282:{33,45,60}]
wire _allocatable_slots_WIRE_1_1 = _allocatable_slots_T_43; // @[tage.scala:282:{14,45}]
wire _allocatable_slots_T_44 = ~f3_resps_2_1_valid; // @[tage.scala:234:25, :282:33]
wire _allocatable_slots_T_45 = f3_resps_2_1_bits_u == 2'h0; // @[tage.scala:234:25, :282:60]
wire _allocatable_slots_T_46 = _allocatable_slots_T_44 & _allocatable_slots_T_45; // @[tage.scala:282:{33,45,60}]
wire _allocatable_slots_WIRE_1_2 = _allocatable_slots_T_46; // @[tage.scala:282:{14,45}]
wire _allocatable_slots_T_47 = ~f3_resps_3_1_valid; // @[tage.scala:234:25, :282:33]
wire _allocatable_slots_T_48 = f3_resps_3_1_bits_u == 2'h0; // @[tage.scala:234:25, :282:60]
wire _allocatable_slots_T_49 = _allocatable_slots_T_47 & _allocatable_slots_T_48; // @[tage.scala:282:{33,45,60}]
wire _allocatable_slots_WIRE_1_3 = _allocatable_slots_T_49; // @[tage.scala:282:{14,45}]
wire _allocatable_slots_T_50 = ~f3_resps_4_1_valid; // @[tage.scala:234:25, :282:33]
wire _allocatable_slots_T_51 = f3_resps_4_1_bits_u == 2'h0; // @[tage.scala:234:25, :282:60]
wire _allocatable_slots_T_52 = _allocatable_slots_T_50 & _allocatable_slots_T_51; // @[tage.scala:282:{33,45,60}]
wire _allocatable_slots_WIRE_1_4 = _allocatable_slots_T_52; // @[tage.scala:282:{14,45}]
wire _allocatable_slots_T_53 = ~f3_resps_5_1_valid; // @[tage.scala:234:25, :282:33]
wire _allocatable_slots_T_54 = f3_resps_5_1_bits_u == 2'h0; // @[tage.scala:234:25, :282:60]
wire _allocatable_slots_T_55 = _allocatable_slots_T_53 & _allocatable_slots_T_54; // @[tage.scala:282:{33,45,60}]
wire _allocatable_slots_WIRE_1_5 = _allocatable_slots_T_55; // @[tage.scala:282:{14,45}]
wire [1:0] allocatable_slots_lo_hi_1 = {_allocatable_slots_WIRE_1_2, _allocatable_slots_WIRE_1_1}; // @[tage.scala:282:{14,70}]
wire [2:0] allocatable_slots_lo_1 = {allocatable_slots_lo_hi_1, _allocatable_slots_WIRE_1_0}; // @[tage.scala:282:{14,70}]
wire [1:0] allocatable_slots_hi_hi_1 = {_allocatable_slots_WIRE_1_5, _allocatable_slots_WIRE_1_4}; // @[tage.scala:282:{14,70}]
wire [2:0] allocatable_slots_hi_1 = {allocatable_slots_hi_hi_1, _allocatable_slots_WIRE_1_3}; // @[tage.scala:282:{14,70}]
wire [5:0] _allocatable_slots_T_56 = {allocatable_slots_hi_1, allocatable_slots_lo_1}; // @[tage.scala:282:70]
wire [7:0] _allocatable_slots_T_57 = 8'h1 << f3_meta_provider_1_bits; // @[OneHot.scala:58:35]
wire [7:0] _allocatable_slots_T_58 = _allocatable_slots_T_57; // @[OneHot.scala:58:35]
wire [7:0] _allocatable_slots_T_59 = {1'h0, _allocatable_slots_T_57[7:1]}; // @[OneHot.scala:58:35]
wire [7:0] _allocatable_slots_T_60 = {2'h0, _allocatable_slots_T_57[7:2]}; // @[OneHot.scala:58:35]
wire [7:0] _allocatable_slots_T_61 = {3'h0, _allocatable_slots_T_57[7:3]}; // @[OneHot.scala:58:35]
wire [7:0] _allocatable_slots_T_62 = {4'h0, _allocatable_slots_T_57[7:4]}; // @[OneHot.scala:58:35]
wire [7:0] _allocatable_slots_T_63 = {5'h0, _allocatable_slots_T_57[7:5]}; // @[OneHot.scala:58:35]
wire [7:0] _allocatable_slots_T_64 = {6'h0, _allocatable_slots_T_57[7:6]}; // @[OneHot.scala:58:35]
wire [7:0] _allocatable_slots_T_65 = {7'h0, _allocatable_slots_T_57[7]}; // @[OneHot.scala:58:35]
wire [7:0] _allocatable_slots_T_66 = _allocatable_slots_T_58 | _allocatable_slots_T_59; // @[util.scala:373:{29,45}]
wire [7:0] _allocatable_slots_T_67 = _allocatable_slots_T_66 | _allocatable_slots_T_60; // @[util.scala:373:{29,45}]
wire [7:0] _allocatable_slots_T_68 = _allocatable_slots_T_67 | _allocatable_slots_T_61; // @[util.scala:373:{29,45}]
wire [7:0] _allocatable_slots_T_69 = _allocatable_slots_T_68 | _allocatable_slots_T_62; // @[util.scala:373:{29,45}]
wire [7:0] _allocatable_slots_T_70 = _allocatable_slots_T_69 | _allocatable_slots_T_63; // @[util.scala:373:{29,45}]
wire [7:0] _allocatable_slots_T_71 = _allocatable_slots_T_70 | _allocatable_slots_T_64; // @[util.scala:373:{29,45}]
wire [7:0] _allocatable_slots_T_72 = _allocatable_slots_T_71 | _allocatable_slots_T_65; // @[util.scala:373:{29,45}]
wire [5:0] _allocatable_slots_T_73 = {6{f3_meta_provider_1_valid}}; // @[tage.scala:212:21, :283:45]
wire [7:0] _allocatable_slots_T_74 = {2'h0, _allocatable_slots_T_72[5:0] & _allocatable_slots_T_73}; // @[util.scala:373:45]
wire [7:0] _allocatable_slots_T_75 = ~_allocatable_slots_T_74; // @[tage.scala:283:{7,39}]
wire [7:0] allocatable_slots_1 = {2'h0, _allocatable_slots_T_75[5:0] & _allocatable_slots_T_56}; // @[tage.scala:282:{70,77}, :283:7]
wire [1:0] alloc_lfsr_lo_hi_1 = {_alloc_lfsr_prng_1_io_out_2, _alloc_lfsr_prng_1_io_out_1}; // @[PRNG.scala:91:22, :95:17]
wire [2:0] alloc_lfsr_lo_1 = {alloc_lfsr_lo_hi_1, _alloc_lfsr_prng_1_io_out_0}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] alloc_lfsr_hi_hi_1 = {_alloc_lfsr_prng_1_io_out_5, _alloc_lfsr_prng_1_io_out_4}; // @[PRNG.scala:91:22, :95:17]
wire [2:0] alloc_lfsr_hi_1 = {alloc_lfsr_hi_hi_1, _alloc_lfsr_prng_1_io_out_3}; // @[PRNG.scala:91:22, :95:17]
wire [5:0] alloc_lfsr_1 = {alloc_lfsr_hi_1, alloc_lfsr_lo_1}; // @[PRNG.scala:95:17]
wire _first_entry_T_14 = allocatable_slots_1[0]; // @[OneHot.scala:48:45]
wire _first_entry_T_15 = allocatable_slots_1[1]; // @[OneHot.scala:48:45]
wire _first_entry_T_16 = allocatable_slots_1[2]; // @[OneHot.scala:48:45]
wire _first_entry_T_17 = allocatable_slots_1[3]; // @[OneHot.scala:48:45]
wire _first_entry_T_18 = allocatable_slots_1[4]; // @[OneHot.scala:48:45]
wire _first_entry_T_19 = allocatable_slots_1[5]; // @[OneHot.scala:48:45]
wire _first_entry_T_20 = allocatable_slots_1[6]; // @[OneHot.scala:48:45]
wire _first_entry_T_21 = allocatable_slots_1[7]; // @[OneHot.scala:48:45]
wire [2:0] _first_entry_T_22 = {2'h3, ~_first_entry_T_20}; // @[OneHot.scala:48:45]
wire [2:0] _first_entry_T_23 = _first_entry_T_19 ? 3'h5 : _first_entry_T_22; // @[OneHot.scala:48:45]
wire [2:0] _first_entry_T_24 = _first_entry_T_18 ? 3'h4 : _first_entry_T_23; // @[OneHot.scala:48:45]
wire [2:0] _first_entry_T_25 = _first_entry_T_17 ? 3'h3 : _first_entry_T_24; // @[OneHot.scala:48:45]
wire [2:0] _first_entry_T_26 = _first_entry_T_16 ? 3'h2 : _first_entry_T_25; // @[OneHot.scala:48:45]
wire [2:0] _first_entry_T_27 = _first_entry_T_15 ? 3'h1 : _first_entry_T_26; // @[OneHot.scala:48:45]
wire [2:0] first_entry_1 = _first_entry_T_14 ? 3'h0 : _first_entry_T_27; // @[OneHot.scala:48:45]
wire [7:0] _masked_entry_T_15 = {2'h0, allocatable_slots_1[5:0] & alloc_lfsr_1}; // @[PRNG.scala:95:17]
wire _masked_entry_T_16 = _masked_entry_T_15[0]; // @[OneHot.scala:48:45]
wire _masked_entry_T_17 = _masked_entry_T_15[1]; // @[OneHot.scala:48:45]
wire _masked_entry_T_18 = _masked_entry_T_15[2]; // @[OneHot.scala:48:45]
wire _masked_entry_T_19 = _masked_entry_T_15[3]; // @[OneHot.scala:48:45]
wire _masked_entry_T_20 = _masked_entry_T_15[4]; // @[OneHot.scala:48:45]
wire _masked_entry_T_21 = _masked_entry_T_15[5]; // @[OneHot.scala:48:45]
wire _masked_entry_T_22 = _masked_entry_T_15[6]; // @[OneHot.scala:48:45]
wire _masked_entry_T_23 = _masked_entry_T_15[7]; // @[OneHot.scala:48:45]
wire [2:0] _masked_entry_T_24 = {2'h3, ~_masked_entry_T_22}; // @[OneHot.scala:48:45]
wire [2:0] _masked_entry_T_25 = _masked_entry_T_21 ? 3'h5 : _masked_entry_T_24; // @[OneHot.scala:48:45]
wire [2:0] _masked_entry_T_26 = _masked_entry_T_20 ? 3'h4 : _masked_entry_T_25; // @[OneHot.scala:48:45]
wire [2:0] _masked_entry_T_27 = _masked_entry_T_19 ? 3'h3 : _masked_entry_T_26; // @[OneHot.scala:48:45]
wire [2:0] _masked_entry_T_28 = _masked_entry_T_18 ? 3'h2 : _masked_entry_T_27; // @[OneHot.scala:48:45]
wire [2:0] _masked_entry_T_29 = _masked_entry_T_17 ? 3'h1 : _masked_entry_T_28; // @[OneHot.scala:48:45]
wire [2:0] masked_entry_1 = _masked_entry_T_16 ? 3'h0 : _masked_entry_T_29; // @[OneHot.scala:48:45]
wire [7:0] _alloc_entry_T_2 = allocatable_slots_1 >> masked_entry_1; // @[Mux.scala:50:70]
wire _alloc_entry_T_3 = _alloc_entry_T_2[0]; // @[tage.scala:289:44]
assign alloc_entry_1 = _alloc_entry_T_3 ? masked_entry_1 : first_entry_1; // @[Mux.scala:50:70]
assign f3_meta_allocate_1_bits = alloc_entry_1; // @[tage.scala:212:21, :289:26]
assign _f3_meta_allocate_1_valid_T = |allocatable_slots_1; // @[tage.scala:282:77, :293:52]
assign f3_meta_allocate_1_valid = _f3_meta_allocate_1_valid_T; // @[tage.scala:212:21, :293:52]
wire _update_was_taken_T_2 = s1_update_bits_cfi_idx_bits == 2'h1; // @[tage.scala:297:58]
wire _update_was_taken_T_3 = s1_update_bits_cfi_idx_valid & _update_was_taken_T_2; // @[tage.scala:296:58, :297:58]
wire update_was_taken_1 = _update_was_taken_T_3 & s1_update_bits_cfi_taken; // @[tage.scala:296:58, :297:67]
wire _T_75 = s1_update_bits_br_mask[1] & s1_update_valid & _GEN_7 == 5'h0; // @[OneHot.scala:58:35]
wire _GEN_17 = _T_75 & s1_update_meta_provider_1_valid & s1_update_meta_provider_1_bits == 3'h0; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37]
wire _GEN_18 = _T_75 & s1_update_meta_provider_1_valid & s1_update_meta_provider_1_bits == 3'h1; // @[tage.scala:218:43, :236:52, :240:33, :299:{37,56,92}, :300:47, :303:37]
wire _GEN_19 = _T_75 & s1_update_meta_provider_1_valid & s1_update_meta_provider_1_bits == 3'h2; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37]
wire _GEN_20 = _T_75 & s1_update_meta_provider_1_valid & s1_update_meta_provider_1_bits == 3'h3; // @[tage.scala:236:52, :240:33, :265:40, :299:{37,56,92}, :300:47, :303:37]
wire _GEN_21 = _T_75 & s1_update_meta_provider_1_valid & s1_update_meta_provider_1_bits == 3'h4; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37]
wire _GEN_22 = _T_75 & s1_update_meta_provider_1_valid & s1_update_meta_provider_1_bits == 3'h5; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37]
wire _new_u_T_11 = s1_update_mispredict_mask[1]; // @[tage.scala:237:73, :308:52]
wire _new_u_T_12 = ~s1_update_meta_alt_differs_1; // @[tage.scala:217:9, :236:52]
wire _new_u_T_13 = s1_update_meta_provider_u_1 == 2'h0; // @[tage.scala:218:27, :236:52]
wire [2:0] _GEN_23 = {1'h0, s1_update_meta_provider_u_1}; // @[tage.scala:218:43, :236:52]
wire [2:0] _new_u_T_14 = _GEN_23 - 3'h1; // @[tage.scala:218:43]
wire [1:0] _new_u_T_15 = _new_u_T_14[1:0]; // @[tage.scala:218:43]
wire [1:0] _new_u_T_16 = _new_u_T_13 ? 2'h0 : _new_u_T_15; // @[tage.scala:218:{24,27,43}]
wire _new_u_T_17 = &s1_update_meta_provider_u_1; // @[tage.scala:219:27, :236:52]
wire [2:0] _new_u_T_18 = _GEN_23 + 3'h1; // @[tage.scala:218:43, :219:43]
wire [1:0] _new_u_T_19 = _new_u_T_18[1:0]; // @[tage.scala:219:43]
wire [1:0] _new_u_T_20 = _new_u_T_17 ? 2'h3 : _new_u_T_19; // @[tage.scala:219:{24,27,43}]
wire [1:0] _new_u_T_21 = _new_u_T_11 ? _new_u_T_16 : _new_u_T_20; // @[tage.scala:218:{8,24}, :219:24, :308:52]
wire [1:0] new_u_1 = _new_u_T_12 ? s1_update_meta_provider_u_1 : _new_u_T_21; // @[tage.scala:217:{8,9}, :218:8, :236:52]
wire final_altpred_2; // @[tage.scala:256:33]
wire _io_resp_f3_2_taken_T = f3_resps_0_2_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40]
wire _io_resp_f3_2_taken_T_1 = f3_resps_0_2_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55]
wire _io_resp_f3_2_taken_T_2 = _io_resp_f3_2_taken_T | _io_resp_f3_2_taken_T_1; // @[tage.scala:265:{40,48,55}]
wire _io_resp_f3_2_taken_T_3 = f3_resps_0_2_bits_ctr[2]; // @[tage.scala:234:25, :265:76]
wire _io_resp_f3_2_taken_T_4 = _io_resp_f3_2_taken_T_2 ? io_resp_in_0_f3_2_taken_0 : _io_resp_f3_2_taken_T_3; // @[tage.scala:198:7, :265:{35,48,76}]
wire _T_79 = f3_resps_0_2_valid ? f3_resps_0_2_bits_ctr[2] : io_resp_in_0_f3_2_taken_0; // @[tage.scala:198:7, :234:25, :271:{21,50}]
wire _io_resp_f3_2_taken_T_5 = f3_resps_1_2_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40]
wire _io_resp_f3_2_taken_T_6 = f3_resps_1_2_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55]
wire _io_resp_f3_2_taken_T_7 = _io_resp_f3_2_taken_T_5 | _io_resp_f3_2_taken_T_6; // @[tage.scala:265:{40,48,55}]
wire _io_resp_f3_2_taken_T_8 = f3_resps_1_2_bits_ctr[2]; // @[tage.scala:234:25, :265:76]
wire _io_resp_f3_2_taken_T_9 = _io_resp_f3_2_taken_T_7 ? _T_79 : _io_resp_f3_2_taken_T_8; // @[tage.scala:265:{35,48,76}, :271:21]
wire _T_83 = f3_resps_1_2_valid ? f3_resps_1_2_bits_ctr[2] : _T_79; // @[tage.scala:234:25, :271:{21,50}]
wire _io_resp_f3_2_taken_T_10 = f3_resps_2_2_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40]
wire _io_resp_f3_2_taken_T_11 = f3_resps_2_2_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55]
wire _io_resp_f3_2_taken_T_12 = _io_resp_f3_2_taken_T_10 | _io_resp_f3_2_taken_T_11; // @[tage.scala:265:{40,48,55}]
wire _io_resp_f3_2_taken_T_13 = f3_resps_2_2_bits_ctr[2]; // @[tage.scala:234:25, :265:76]
wire _io_resp_f3_2_taken_T_14 = _io_resp_f3_2_taken_T_12 ? _T_83 : _io_resp_f3_2_taken_T_13; // @[tage.scala:265:{35,48,76}, :271:21]
wire _T_87 = f3_resps_2_2_valid ? f3_resps_2_2_bits_ctr[2] : _T_83; // @[tage.scala:234:25, :271:{21,50}]
wire _io_resp_f3_2_taken_T_15 = f3_resps_3_2_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40]
wire _io_resp_f3_2_taken_T_16 = f3_resps_3_2_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55]
wire _io_resp_f3_2_taken_T_17 = _io_resp_f3_2_taken_T_15 | _io_resp_f3_2_taken_T_16; // @[tage.scala:265:{40,48,55}]
wire _io_resp_f3_2_taken_T_18 = f3_resps_3_2_bits_ctr[2]; // @[tage.scala:234:25, :265:76]
wire _io_resp_f3_2_taken_T_19 = _io_resp_f3_2_taken_T_17 ? _T_87 : _io_resp_f3_2_taken_T_18; // @[tage.scala:265:{35,48,76}, :271:21]
wire _T_91 = f3_resps_3_2_valid ? f3_resps_3_2_bits_ctr[2] : _T_87; // @[tage.scala:234:25, :271:{21,50}]
wire _io_resp_f3_2_taken_T_20 = f3_resps_4_2_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40]
wire _io_resp_f3_2_taken_T_21 = f3_resps_4_2_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55]
wire _io_resp_f3_2_taken_T_22 = _io_resp_f3_2_taken_T_20 | _io_resp_f3_2_taken_T_21; // @[tage.scala:265:{40,48,55}]
wire _io_resp_f3_2_taken_T_23 = f3_resps_4_2_bits_ctr[2]; // @[tage.scala:234:25, :265:76]
wire _io_resp_f3_2_taken_T_24 = _io_resp_f3_2_taken_T_22 ? _T_91 : _io_resp_f3_2_taken_T_23; // @[tage.scala:265:{35,48,76}, :271:21]
wire _T_95 = f3_resps_4_2_valid ? f3_resps_4_2_bits_ctr[2] : _T_91; // @[tage.scala:234:25, :271:{21,50}]
wire _io_resp_f3_2_taken_T_25 = f3_resps_5_2_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40]
wire _io_resp_f3_2_taken_T_26 = f3_resps_5_2_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55]
wire _io_resp_f3_2_taken_T_27 = _io_resp_f3_2_taken_T_25 | _io_resp_f3_2_taken_T_26; // @[tage.scala:265:{40,48,55}]
wire _io_resp_f3_2_taken_T_28 = f3_resps_5_2_bits_ctr[2]; // @[tage.scala:234:25, :265:76]
wire _io_resp_f3_2_taken_T_29 = _io_resp_f3_2_taken_T_27 ? _T_95 : _io_resp_f3_2_taken_T_28; // @[tage.scala:265:{35,48,76}, :271:21]
assign io_resp_f3_2_taken_0 = f3_resps_5_2_valid ? _io_resp_f3_2_taken_T_29 : f3_resps_4_2_valid ? _io_resp_f3_2_taken_T_24 : f3_resps_3_2_valid ? _io_resp_f3_2_taken_T_19 : f3_resps_2_2_valid ? _io_resp_f3_2_taken_T_14 : f3_resps_1_2_valid ? _io_resp_f3_2_taken_T_9 : f3_resps_0_2_valid ? _io_resp_f3_2_taken_T_4 : io_resp_in_0_f3_2_taken_0; // @[tage.scala:198:7, :234:25, :259:25, :264:18, :265:{29,35}]
assign final_altpred_2 = f3_resps_5_2_valid ? _T_95 : f3_resps_4_2_valid ? _T_91 : f3_resps_3_2_valid ? _T_87 : f3_resps_2_2_valid ? _T_83 : f3_resps_1_2_valid & f3_resps_0_2_valid ? f3_resps_0_2_bits_ctr[2] : io_resp_in_0_f3_2_taken_0; // @[tage.scala:198:7, :234:25, :256:33, :264:18, :266:29, :271:{21,50}]
assign f3_meta_provider_2_valid = f3_resps_0_2_valid | f3_resps_1_2_valid | f3_resps_2_2_valid | f3_resps_3_2_valid | f3_resps_4_2_valid | f3_resps_5_2_valid; // @[tage.scala:212:21, :234:25, :269:27]
assign f3_meta_provider_2_bits = f3_resps_5_2_valid ? 3'h5 : f3_resps_4_2_valid ? 3'h4 : {1'h0, f3_resps_3_2_valid ? 2'h3 : f3_resps_2_2_valid ? 2'h2 : {1'h0, f3_resps_1_2_valid}}; // @[tage.scala:212:21, :234:25, :270:21]
assign _f3_meta_alt_differs_2_T = final_altpred_2 != io_resp_f3_2_taken_0; // @[tage.scala:198:7, :256:33, :275:48]
assign f3_meta_alt_differs_2 = _f3_meta_alt_differs_2_T; // @[tage.scala:212:21, :275:48]
wire [7:0][2:0] _GEN_24 = {{f3_resps_0_2_bits_ctr}, {f3_resps_0_2_bits_ctr}, {f3_resps_5_2_bits_ctr}, {f3_resps_4_2_bits_ctr}, {f3_resps_3_2_bits_ctr}, {f3_resps_2_2_bits_ctr}, {f3_resps_1_2_bits_ctr}, {f3_resps_0_2_bits_ctr}}; // @[tage.scala:234:25, :276:31]
assign f3_meta_provider_ctr_2 = _GEN_24[f3_meta_provider_2_bits]; // @[tage.scala:212:21, :276:31]
wire [7:0][1:0] _GEN_25 = {{f3_resps_0_2_bits_u}, {f3_resps_0_2_bits_u}, {f3_resps_5_2_bits_u}, {f3_resps_4_2_bits_u}, {f3_resps_3_2_bits_u}, {f3_resps_2_2_bits_u}, {f3_resps_1_2_bits_u}, {f3_resps_0_2_bits_u}}; // @[tage.scala:234:25, :276:31]
assign f3_meta_provider_u_2 = _GEN_25[f3_meta_provider_2_bits]; // @[tage.scala:212:21, :276:31]
wire _allocatable_slots_T_76 = ~f3_resps_0_2_valid; // @[tage.scala:234:25, :282:33]
wire _allocatable_slots_T_77 = f3_resps_0_2_bits_u == 2'h0; // @[tage.scala:234:25, :282:60]
wire _allocatable_slots_T_78 = _allocatable_slots_T_76 & _allocatable_slots_T_77; // @[tage.scala:282:{33,45,60}]
wire _allocatable_slots_WIRE_2_0 = _allocatable_slots_T_78; // @[tage.scala:282:{14,45}]
wire _allocatable_slots_T_79 = ~f3_resps_1_2_valid; // @[tage.scala:234:25, :282:33]
wire _allocatable_slots_T_80 = f3_resps_1_2_bits_u == 2'h0; // @[tage.scala:234:25, :282:60]
wire _allocatable_slots_T_81 = _allocatable_slots_T_79 & _allocatable_slots_T_80; // @[tage.scala:282:{33,45,60}]
wire _allocatable_slots_WIRE_2_1 = _allocatable_slots_T_81; // @[tage.scala:282:{14,45}]
wire _allocatable_slots_T_82 = ~f3_resps_2_2_valid; // @[tage.scala:234:25, :282:33]
wire _allocatable_slots_T_83 = f3_resps_2_2_bits_u == 2'h0; // @[tage.scala:234:25, :282:60]
wire _allocatable_slots_T_84 = _allocatable_slots_T_82 & _allocatable_slots_T_83; // @[tage.scala:282:{33,45,60}]
wire _allocatable_slots_WIRE_2_2 = _allocatable_slots_T_84; // @[tage.scala:282:{14,45}]
wire _allocatable_slots_T_85 = ~f3_resps_3_2_valid; // @[tage.scala:234:25, :282:33]
wire _allocatable_slots_T_86 = f3_resps_3_2_bits_u == 2'h0; // @[tage.scala:234:25, :282:60]
wire _allocatable_slots_T_87 = _allocatable_slots_T_85 & _allocatable_slots_T_86; // @[tage.scala:282:{33,45,60}]
wire _allocatable_slots_WIRE_2_3 = _allocatable_slots_T_87; // @[tage.scala:282:{14,45}]
wire _allocatable_slots_T_88 = ~f3_resps_4_2_valid; // @[tage.scala:234:25, :282:33]
wire _allocatable_slots_T_89 = f3_resps_4_2_bits_u == 2'h0; // @[tage.scala:234:25, :282:60]
wire _allocatable_slots_T_90 = _allocatable_slots_T_88 & _allocatable_slots_T_89; // @[tage.scala:282:{33,45,60}]
wire _allocatable_slots_WIRE_2_4 = _allocatable_slots_T_90; // @[tage.scala:282:{14,45}]
wire _allocatable_slots_T_91 = ~f3_resps_5_2_valid; // @[tage.scala:234:25, :282:33]
wire _allocatable_slots_T_92 = f3_resps_5_2_bits_u == 2'h0; // @[tage.scala:234:25, :282:60]
wire _allocatable_slots_T_93 = _allocatable_slots_T_91 & _allocatable_slots_T_92; // @[tage.scala:282:{33,45,60}]
wire _allocatable_slots_WIRE_2_5 = _allocatable_slots_T_93; // @[tage.scala:282:{14,45}]
wire [1:0] allocatable_slots_lo_hi_2 = {_allocatable_slots_WIRE_2_2, _allocatable_slots_WIRE_2_1}; // @[tage.scala:282:{14,70}]
wire [2:0] allocatable_slots_lo_2 = {allocatable_slots_lo_hi_2, _allocatable_slots_WIRE_2_0}; // @[tage.scala:282:{14,70}]
wire [1:0] allocatable_slots_hi_hi_2 = {_allocatable_slots_WIRE_2_5, _allocatable_slots_WIRE_2_4}; // @[tage.scala:282:{14,70}]
wire [2:0] allocatable_slots_hi_2 = {allocatable_slots_hi_hi_2, _allocatable_slots_WIRE_2_3}; // @[tage.scala:282:{14,70}]
wire [5:0] _allocatable_slots_T_94 = {allocatable_slots_hi_2, allocatable_slots_lo_2}; // @[tage.scala:282:70]
wire [7:0] _allocatable_slots_T_95 = 8'h1 << f3_meta_provider_2_bits; // @[OneHot.scala:58:35]
wire [7:0] _allocatable_slots_T_96 = _allocatable_slots_T_95; // @[OneHot.scala:58:35]
wire [7:0] _allocatable_slots_T_97 = {1'h0, _allocatable_slots_T_95[7:1]}; // @[OneHot.scala:58:35]
wire [7:0] _allocatable_slots_T_98 = {2'h0, _allocatable_slots_T_95[7:2]}; // @[OneHot.scala:58:35]
wire [7:0] _allocatable_slots_T_99 = {3'h0, _allocatable_slots_T_95[7:3]}; // @[OneHot.scala:58:35]
wire [7:0] _allocatable_slots_T_100 = {4'h0, _allocatable_slots_T_95[7:4]}; // @[OneHot.scala:58:35]
wire [7:0] _allocatable_slots_T_101 = {5'h0, _allocatable_slots_T_95[7:5]}; // @[OneHot.scala:58:35]
wire [7:0] _allocatable_slots_T_102 = {6'h0, _allocatable_slots_T_95[7:6]}; // @[OneHot.scala:58:35]
wire [7:0] _allocatable_slots_T_103 = {7'h0, _allocatable_slots_T_95[7]}; // @[OneHot.scala:58:35]
wire [7:0] _allocatable_slots_T_104 = _allocatable_slots_T_96 | _allocatable_slots_T_97; // @[util.scala:373:{29,45}]
wire [7:0] _allocatable_slots_T_105 = _allocatable_slots_T_104 | _allocatable_slots_T_98; // @[util.scala:373:{29,45}]
wire [7:0] _allocatable_slots_T_106 = _allocatable_slots_T_105 | _allocatable_slots_T_99; // @[util.scala:373:{29,45}]
wire [7:0] _allocatable_slots_T_107 = _allocatable_slots_T_106 | _allocatable_slots_T_100; // @[util.scala:373:{29,45}]
wire [7:0] _allocatable_slots_T_108 = _allocatable_slots_T_107 | _allocatable_slots_T_101; // @[util.scala:373:{29,45}]
wire [7:0] _allocatable_slots_T_109 = _allocatable_slots_T_108 | _allocatable_slots_T_102; // @[util.scala:373:{29,45}]
wire [7:0] _allocatable_slots_T_110 = _allocatable_slots_T_109 | _allocatable_slots_T_103; // @[util.scala:373:{29,45}]
wire [5:0] _allocatable_slots_T_111 = {6{f3_meta_provider_2_valid}}; // @[tage.scala:212:21, :283:45]
wire [7:0] _allocatable_slots_T_112 = {2'h0, _allocatable_slots_T_110[5:0] & _allocatable_slots_T_111}; // @[util.scala:373:45]
wire [7:0] _allocatable_slots_T_113 = ~_allocatable_slots_T_112; // @[tage.scala:283:{7,39}]
wire [7:0] allocatable_slots_2 = {2'h0, _allocatable_slots_T_113[5:0] & _allocatable_slots_T_94}; // @[tage.scala:282:{70,77}, :283:7]
wire [1:0] alloc_lfsr_lo_hi_2 = {_alloc_lfsr_prng_2_io_out_2, _alloc_lfsr_prng_2_io_out_1}; // @[PRNG.scala:91:22, :95:17]
wire [2:0] alloc_lfsr_lo_2 = {alloc_lfsr_lo_hi_2, _alloc_lfsr_prng_2_io_out_0}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] alloc_lfsr_hi_hi_2 = {_alloc_lfsr_prng_2_io_out_5, _alloc_lfsr_prng_2_io_out_4}; // @[PRNG.scala:91:22, :95:17]
wire [2:0] alloc_lfsr_hi_2 = {alloc_lfsr_hi_hi_2, _alloc_lfsr_prng_2_io_out_3}; // @[PRNG.scala:91:22, :95:17]
wire [5:0] alloc_lfsr_2 = {alloc_lfsr_hi_2, alloc_lfsr_lo_2}; // @[PRNG.scala:95:17]
wire _first_entry_T_28 = allocatable_slots_2[0]; // @[OneHot.scala:48:45]
wire _first_entry_T_29 = allocatable_slots_2[1]; // @[OneHot.scala:48:45]
wire _first_entry_T_30 = allocatable_slots_2[2]; // @[OneHot.scala:48:45]
wire _first_entry_T_31 = allocatable_slots_2[3]; // @[OneHot.scala:48:45]
wire _first_entry_T_32 = allocatable_slots_2[4]; // @[OneHot.scala:48:45]
wire _first_entry_T_33 = allocatable_slots_2[5]; // @[OneHot.scala:48:45]
wire _first_entry_T_34 = allocatable_slots_2[6]; // @[OneHot.scala:48:45]
wire _first_entry_T_35 = allocatable_slots_2[7]; // @[OneHot.scala:48:45]
wire [2:0] _first_entry_T_36 = {2'h3, ~_first_entry_T_34}; // @[OneHot.scala:48:45]
wire [2:0] _first_entry_T_37 = _first_entry_T_33 ? 3'h5 : _first_entry_T_36; // @[OneHot.scala:48:45]
wire [2:0] _first_entry_T_38 = _first_entry_T_32 ? 3'h4 : _first_entry_T_37; // @[OneHot.scala:48:45]
wire [2:0] _first_entry_T_39 = _first_entry_T_31 ? 3'h3 : _first_entry_T_38; // @[OneHot.scala:48:45]
wire [2:0] _first_entry_T_40 = _first_entry_T_30 ? 3'h2 : _first_entry_T_39; // @[OneHot.scala:48:45]
wire [2:0] _first_entry_T_41 = _first_entry_T_29 ? 3'h1 : _first_entry_T_40; // @[OneHot.scala:48:45]
wire [2:0] first_entry_2 = _first_entry_T_28 ? 3'h0 : _first_entry_T_41; // @[OneHot.scala:48:45]
wire [7:0] _masked_entry_T_30 = {2'h0, allocatable_slots_2[5:0] & alloc_lfsr_2}; // @[PRNG.scala:95:17]
wire _masked_entry_T_31 = _masked_entry_T_30[0]; // @[OneHot.scala:48:45]
wire _masked_entry_T_32 = _masked_entry_T_30[1]; // @[OneHot.scala:48:45]
wire _masked_entry_T_33 = _masked_entry_T_30[2]; // @[OneHot.scala:48:45]
wire _masked_entry_T_34 = _masked_entry_T_30[3]; // @[OneHot.scala:48:45]
wire _masked_entry_T_35 = _masked_entry_T_30[4]; // @[OneHot.scala:48:45]
wire _masked_entry_T_36 = _masked_entry_T_30[5]; // @[OneHot.scala:48:45]
wire _masked_entry_T_37 = _masked_entry_T_30[6]; // @[OneHot.scala:48:45]
wire _masked_entry_T_38 = _masked_entry_T_30[7]; // @[OneHot.scala:48:45]
wire [2:0] _masked_entry_T_39 = {2'h3, ~_masked_entry_T_37}; // @[OneHot.scala:48:45]
wire [2:0] _masked_entry_T_40 = _masked_entry_T_36 ? 3'h5 : _masked_entry_T_39; // @[OneHot.scala:48:45]
wire [2:0] _masked_entry_T_41 = _masked_entry_T_35 ? 3'h4 : _masked_entry_T_40; // @[OneHot.scala:48:45]
wire [2:0] _masked_entry_T_42 = _masked_entry_T_34 ? 3'h3 : _masked_entry_T_41; // @[OneHot.scala:48:45]
wire [2:0] _masked_entry_T_43 = _masked_entry_T_33 ? 3'h2 : _masked_entry_T_42; // @[OneHot.scala:48:45]
wire [2:0] _masked_entry_T_44 = _masked_entry_T_32 ? 3'h1 : _masked_entry_T_43; // @[OneHot.scala:48:45]
wire [2:0] masked_entry_2 = _masked_entry_T_31 ? 3'h0 : _masked_entry_T_44; // @[OneHot.scala:48:45]
wire [7:0] _alloc_entry_T_4 = allocatable_slots_2 >> masked_entry_2; // @[Mux.scala:50:70]
wire _alloc_entry_T_5 = _alloc_entry_T_4[0]; // @[tage.scala:289:44]
assign alloc_entry_2 = _alloc_entry_T_5 ? masked_entry_2 : first_entry_2; // @[Mux.scala:50:70]
assign f3_meta_allocate_2_bits = alloc_entry_2; // @[tage.scala:212:21, :289:26]
assign _f3_meta_allocate_2_valid_T = |allocatable_slots_2; // @[tage.scala:282:77, :293:52]
assign f3_meta_allocate_2_valid = _f3_meta_allocate_2_valid_T; // @[tage.scala:212:21, :293:52]
wire _update_was_taken_T_4 = s1_update_bits_cfi_idx_bits == 2'h2; // @[tage.scala:297:58]
wire _update_was_taken_T_5 = s1_update_bits_cfi_idx_valid & _update_was_taken_T_4; // @[tage.scala:296:58, :297:58]
wire update_was_taken_2 = _update_was_taken_T_5 & s1_update_bits_cfi_taken; // @[tage.scala:296:58, :297:67]
wire _T_106 = s1_update_bits_br_mask[2] & s1_update_valid & _GEN_7 == 5'h0; // @[OneHot.scala:58:35]
wire _GEN_26 = _T_106 & s1_update_meta_provider_2_valid & s1_update_meta_provider_2_bits == 3'h0; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37]
wire _GEN_27 = _T_106 & s1_update_meta_provider_2_valid & s1_update_meta_provider_2_bits == 3'h1; // @[tage.scala:218:43, :236:52, :240:33, :299:{37,56,92}, :300:47, :303:37]
wire _GEN_28 = _T_106 & s1_update_meta_provider_2_valid & s1_update_meta_provider_2_bits == 3'h2; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37]
wire _GEN_29 = _T_106 & s1_update_meta_provider_2_valid & s1_update_meta_provider_2_bits == 3'h3; // @[tage.scala:236:52, :240:33, :265:40, :299:{37,56,92}, :300:47, :303:37]
wire _GEN_30 = _T_106 & s1_update_meta_provider_2_valid & s1_update_meta_provider_2_bits == 3'h4; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37]
wire _GEN_31 = _T_106 & s1_update_meta_provider_2_valid & s1_update_meta_provider_2_bits == 3'h5; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37]
wire _new_u_T_22 = s1_update_mispredict_mask[2]; // @[tage.scala:237:73, :308:52]
wire _new_u_T_23 = ~s1_update_meta_alt_differs_2; // @[tage.scala:217:9, :236:52]
wire _new_u_T_24 = s1_update_meta_provider_u_2 == 2'h0; // @[tage.scala:218:27, :236:52]
wire [2:0] _GEN_32 = {1'h0, s1_update_meta_provider_u_2}; // @[tage.scala:218:43, :236:52]
wire [2:0] _new_u_T_25 = _GEN_32 - 3'h1; // @[tage.scala:218:43]
wire [1:0] _new_u_T_26 = _new_u_T_25[1:0]; // @[tage.scala:218:43]
wire [1:0] _new_u_T_27 = _new_u_T_24 ? 2'h0 : _new_u_T_26; // @[tage.scala:218:{24,27,43}]
wire _new_u_T_28 = &s1_update_meta_provider_u_2; // @[tage.scala:219:27, :236:52]
wire [2:0] _new_u_T_29 = _GEN_32 + 3'h1; // @[tage.scala:218:43, :219:43]
wire [1:0] _new_u_T_30 = _new_u_T_29[1:0]; // @[tage.scala:219:43]
wire [1:0] _new_u_T_31 = _new_u_T_28 ? 2'h3 : _new_u_T_30; // @[tage.scala:219:{24,27,43}]
wire [1:0] _new_u_T_32 = _new_u_T_22 ? _new_u_T_27 : _new_u_T_31; // @[tage.scala:218:{8,24}, :219:24, :308:52]
wire [1:0] new_u_2 = _new_u_T_23 ? s1_update_meta_provider_u_2 : _new_u_T_32; // @[tage.scala:217:{8,9}, :218:8, :236:52]
wire final_altpred_3; // @[tage.scala:256:33]
wire _io_resp_f3_3_taken_T = f3_resps_0_3_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40]
wire _io_resp_f3_3_taken_T_1 = f3_resps_0_3_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55]
wire _io_resp_f3_3_taken_T_2 = _io_resp_f3_3_taken_T | _io_resp_f3_3_taken_T_1; // @[tage.scala:265:{40,48,55}]
wire _io_resp_f3_3_taken_T_3 = f3_resps_0_3_bits_ctr[2]; // @[tage.scala:234:25, :265:76]
wire _io_resp_f3_3_taken_T_4 = _io_resp_f3_3_taken_T_2 ? io_resp_in_0_f3_3_taken_0 : _io_resp_f3_3_taken_T_3; // @[tage.scala:198:7, :265:{35,48,76}]
wire _T_110 = f3_resps_0_3_valid ? f3_resps_0_3_bits_ctr[2] : io_resp_in_0_f3_3_taken_0; // @[tage.scala:198:7, :234:25, :271:{21,50}]
wire _io_resp_f3_3_taken_T_5 = f3_resps_1_3_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40]
wire _io_resp_f3_3_taken_T_6 = f3_resps_1_3_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55]
wire _io_resp_f3_3_taken_T_7 = _io_resp_f3_3_taken_T_5 | _io_resp_f3_3_taken_T_6; // @[tage.scala:265:{40,48,55}]
wire _io_resp_f3_3_taken_T_8 = f3_resps_1_3_bits_ctr[2]; // @[tage.scala:234:25, :265:76]
wire _io_resp_f3_3_taken_T_9 = _io_resp_f3_3_taken_T_7 ? _T_110 : _io_resp_f3_3_taken_T_8; // @[tage.scala:265:{35,48,76}, :271:21]
wire _T_114 = f3_resps_1_3_valid ? f3_resps_1_3_bits_ctr[2] : _T_110; // @[tage.scala:234:25, :271:{21,50}]
wire _io_resp_f3_3_taken_T_10 = f3_resps_2_3_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40]
wire _io_resp_f3_3_taken_T_11 = f3_resps_2_3_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55]
wire _io_resp_f3_3_taken_T_12 = _io_resp_f3_3_taken_T_10 | _io_resp_f3_3_taken_T_11; // @[tage.scala:265:{40,48,55}]
wire _io_resp_f3_3_taken_T_13 = f3_resps_2_3_bits_ctr[2]; // @[tage.scala:234:25, :265:76]
wire _io_resp_f3_3_taken_T_14 = _io_resp_f3_3_taken_T_12 ? _T_114 : _io_resp_f3_3_taken_T_13; // @[tage.scala:265:{35,48,76}, :271:21]
wire _T_118 = f3_resps_2_3_valid ? f3_resps_2_3_bits_ctr[2] : _T_114; // @[tage.scala:234:25, :271:{21,50}]
wire _io_resp_f3_3_taken_T_15 = f3_resps_3_3_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40]
wire _io_resp_f3_3_taken_T_16 = f3_resps_3_3_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55]
wire _io_resp_f3_3_taken_T_17 = _io_resp_f3_3_taken_T_15 | _io_resp_f3_3_taken_T_16; // @[tage.scala:265:{40,48,55}]
wire _io_resp_f3_3_taken_T_18 = f3_resps_3_3_bits_ctr[2]; // @[tage.scala:234:25, :265:76]
wire _io_resp_f3_3_taken_T_19 = _io_resp_f3_3_taken_T_17 ? _T_118 : _io_resp_f3_3_taken_T_18; // @[tage.scala:265:{35,48,76}, :271:21]
wire _T_122 = f3_resps_3_3_valid ? f3_resps_3_3_bits_ctr[2] : _T_118; // @[tage.scala:234:25, :271:{21,50}]
wire _io_resp_f3_3_taken_T_20 = f3_resps_4_3_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40]
wire _io_resp_f3_3_taken_T_21 = f3_resps_4_3_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55]
wire _io_resp_f3_3_taken_T_22 = _io_resp_f3_3_taken_T_20 | _io_resp_f3_3_taken_T_21; // @[tage.scala:265:{40,48,55}]
wire _io_resp_f3_3_taken_T_23 = f3_resps_4_3_bits_ctr[2]; // @[tage.scala:234:25, :265:76]
wire _io_resp_f3_3_taken_T_24 = _io_resp_f3_3_taken_T_22 ? _T_122 : _io_resp_f3_3_taken_T_23; // @[tage.scala:265:{35,48,76}, :271:21]
wire _T_126 = f3_resps_4_3_valid ? f3_resps_4_3_bits_ctr[2] : _T_122; // @[tage.scala:234:25, :271:{21,50}]
wire _io_resp_f3_3_taken_T_25 = f3_resps_5_3_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40]
wire _io_resp_f3_3_taken_T_26 = f3_resps_5_3_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55]
wire _io_resp_f3_3_taken_T_27 = _io_resp_f3_3_taken_T_25 | _io_resp_f3_3_taken_T_26; // @[tage.scala:265:{40,48,55}]
wire _io_resp_f3_3_taken_T_28 = f3_resps_5_3_bits_ctr[2]; // @[tage.scala:234:25, :265:76]
wire _io_resp_f3_3_taken_T_29 = _io_resp_f3_3_taken_T_27 ? _T_126 : _io_resp_f3_3_taken_T_28; // @[tage.scala:265:{35,48,76}, :271:21]
assign io_resp_f3_3_taken_0 = f3_resps_5_3_valid ? _io_resp_f3_3_taken_T_29 : f3_resps_4_3_valid ? _io_resp_f3_3_taken_T_24 : f3_resps_3_3_valid ? _io_resp_f3_3_taken_T_19 : f3_resps_2_3_valid ? _io_resp_f3_3_taken_T_14 : f3_resps_1_3_valid ? _io_resp_f3_3_taken_T_9 : f3_resps_0_3_valid ? _io_resp_f3_3_taken_T_4 : io_resp_in_0_f3_3_taken_0; // @[tage.scala:198:7, :234:25, :259:25, :264:18, :265:{29,35}]
assign final_altpred_3 = f3_resps_5_3_valid ? _T_126 : f3_resps_4_3_valid ? _T_122 : f3_resps_3_3_valid ? _T_118 : f3_resps_2_3_valid ? _T_114 : f3_resps_1_3_valid & f3_resps_0_3_valid ? f3_resps_0_3_bits_ctr[2] : io_resp_in_0_f3_3_taken_0; // @[tage.scala:198:7, :234:25, :256:33, :264:18, :266:29, :271:{21,50}]
assign f3_meta_provider_3_valid = f3_resps_0_3_valid | f3_resps_1_3_valid | f3_resps_2_3_valid | f3_resps_3_3_valid | f3_resps_4_3_valid | f3_resps_5_3_valid; // @[tage.scala:212:21, :234:25, :269:27]
assign f3_meta_provider_3_bits = f3_resps_5_3_valid ? 3'h5 : f3_resps_4_3_valid ? 3'h4 : {1'h0, f3_resps_3_3_valid ? 2'h3 : f3_resps_2_3_valid ? 2'h2 : {1'h0, f3_resps_1_3_valid}}; // @[tage.scala:212:21, :234:25, :270:21]
assign _f3_meta_alt_differs_3_T = final_altpred_3 != io_resp_f3_3_taken_0; // @[tage.scala:198:7, :256:33, :275:48]
assign f3_meta_alt_differs_3 = _f3_meta_alt_differs_3_T; // @[tage.scala:212:21, :275:48]
wire [7:0][2:0] _GEN_33 = {{f3_resps_0_3_bits_ctr}, {f3_resps_0_3_bits_ctr}, {f3_resps_5_3_bits_ctr}, {f3_resps_4_3_bits_ctr}, {f3_resps_3_3_bits_ctr}, {f3_resps_2_3_bits_ctr}, {f3_resps_1_3_bits_ctr}, {f3_resps_0_3_bits_ctr}}; // @[tage.scala:234:25, :276:31]
assign f3_meta_provider_ctr_3 = _GEN_33[f3_meta_provider_3_bits]; // @[tage.scala:212:21, :276:31]
wire [7:0][1:0] _GEN_34 = {{f3_resps_0_3_bits_u}, {f3_resps_0_3_bits_u}, {f3_resps_5_3_bits_u}, {f3_resps_4_3_bits_u}, {f3_resps_3_3_bits_u}, {f3_resps_2_3_bits_u}, {f3_resps_1_3_bits_u}, {f3_resps_0_3_bits_u}}; // @[tage.scala:234:25, :276:31]
assign f3_meta_provider_u_3 = _GEN_34[f3_meta_provider_3_bits]; // @[tage.scala:212:21, :276:31]
wire _allocatable_slots_T_114 = ~f3_resps_0_3_valid; // @[tage.scala:234:25, :282:33]
wire _allocatable_slots_T_115 = f3_resps_0_3_bits_u == 2'h0; // @[tage.scala:234:25, :282:60]
wire _allocatable_slots_T_116 = _allocatable_slots_T_114 & _allocatable_slots_T_115; // @[tage.scala:282:{33,45,60}]
wire _allocatable_slots_WIRE_3_0 = _allocatable_slots_T_116; // @[tage.scala:282:{14,45}]
wire _allocatable_slots_T_117 = ~f3_resps_1_3_valid; // @[tage.scala:234:25, :282:33]
wire _allocatable_slots_T_118 = f3_resps_1_3_bits_u == 2'h0; // @[tage.scala:234:25, :282:60]
wire _allocatable_slots_T_119 = _allocatable_slots_T_117 & _allocatable_slots_T_118; // @[tage.scala:282:{33,45,60}]
wire _allocatable_slots_WIRE_3_1 = _allocatable_slots_T_119; // @[tage.scala:282:{14,45}]
wire _allocatable_slots_T_120 = ~f3_resps_2_3_valid; // @[tage.scala:234:25, :282:33]
wire _allocatable_slots_T_121 = f3_resps_2_3_bits_u == 2'h0; // @[tage.scala:234:25, :282:60]
wire _allocatable_slots_T_122 = _allocatable_slots_T_120 & _allocatable_slots_T_121; // @[tage.scala:282:{33,45,60}]
wire _allocatable_slots_WIRE_3_2 = _allocatable_slots_T_122; // @[tage.scala:282:{14,45}]
wire _allocatable_slots_T_123 = ~f3_resps_3_3_valid; // @[tage.scala:234:25, :282:33]
wire _allocatable_slots_T_124 = f3_resps_3_3_bits_u == 2'h0; // @[tage.scala:234:25, :282:60]
wire _allocatable_slots_T_125 = _allocatable_slots_T_123 & _allocatable_slots_T_124; // @[tage.scala:282:{33,45,60}]
wire _allocatable_slots_WIRE_3_3 = _allocatable_slots_T_125; // @[tage.scala:282:{14,45}]
wire _allocatable_slots_T_126 = ~f3_resps_4_3_valid; // @[tage.scala:234:25, :282:33]
wire _allocatable_slots_T_127 = f3_resps_4_3_bits_u == 2'h0; // @[tage.scala:234:25, :282:60]
wire _allocatable_slots_T_128 = _allocatable_slots_T_126 & _allocatable_slots_T_127; // @[tage.scala:282:{33,45,60}]
wire _allocatable_slots_WIRE_3_4 = _allocatable_slots_T_128; // @[tage.scala:282:{14,45}]
wire _allocatable_slots_T_129 = ~f3_resps_5_3_valid; // @[tage.scala:234:25, :282:33]
wire _allocatable_slots_T_130 = f3_resps_5_3_bits_u == 2'h0; // @[tage.scala:234:25, :282:60]
wire _allocatable_slots_T_131 = _allocatable_slots_T_129 & _allocatable_slots_T_130; // @[tage.scala:282:{33,45,60}]
wire _allocatable_slots_WIRE_3_5 = _allocatable_slots_T_131; // @[tage.scala:282:{14,45}]
wire [1:0] allocatable_slots_lo_hi_3 = {_allocatable_slots_WIRE_3_2, _allocatable_slots_WIRE_3_1}; // @[tage.scala:282:{14,70}]
wire [2:0] allocatable_slots_lo_3 = {allocatable_slots_lo_hi_3, _allocatable_slots_WIRE_3_0}; // @[tage.scala:282:{14,70}]
wire [1:0] allocatable_slots_hi_hi_3 = {_allocatable_slots_WIRE_3_5, _allocatable_slots_WIRE_3_4}; // @[tage.scala:282:{14,70}]
wire [2:0] allocatable_slots_hi_3 = {allocatable_slots_hi_hi_3, _allocatable_slots_WIRE_3_3}; // @[tage.scala:282:{14,70}]
wire [5:0] _allocatable_slots_T_132 = {allocatable_slots_hi_3, allocatable_slots_lo_3}; // @[tage.scala:282:70]
wire [7:0] _allocatable_slots_T_133 = 8'h1 << f3_meta_provider_3_bits; // @[OneHot.scala:58:35]
wire [7:0] _allocatable_slots_T_134 = _allocatable_slots_T_133; // @[OneHot.scala:58:35]
wire [7:0] _allocatable_slots_T_135 = {1'h0, _allocatable_slots_T_133[7:1]}; // @[OneHot.scala:58:35]
wire [7:0] _allocatable_slots_T_136 = {2'h0, _allocatable_slots_T_133[7:2]}; // @[OneHot.scala:58:35]
wire [7:0] _allocatable_slots_T_137 = {3'h0, _allocatable_slots_T_133[7:3]}; // @[OneHot.scala:58:35]
wire [7:0] _allocatable_slots_T_138 = {4'h0, _allocatable_slots_T_133[7:4]}; // @[OneHot.scala:58:35]
wire [7:0] _allocatable_slots_T_139 = {5'h0, _allocatable_slots_T_133[7:5]}; // @[OneHot.scala:58:35]
wire [7:0] _allocatable_slots_T_140 = {6'h0, _allocatable_slots_T_133[7:6]}; // @[OneHot.scala:58:35]
wire [7:0] _allocatable_slots_T_141 = {7'h0, _allocatable_slots_T_133[7]}; // @[OneHot.scala:58:35]
wire [7:0] _allocatable_slots_T_142 = _allocatable_slots_T_134 | _allocatable_slots_T_135; // @[util.scala:373:{29,45}]
wire [7:0] _allocatable_slots_T_143 = _allocatable_slots_T_142 | _allocatable_slots_T_136; // @[util.scala:373:{29,45}]
wire [7:0] _allocatable_slots_T_144 = _allocatable_slots_T_143 | _allocatable_slots_T_137; // @[util.scala:373:{29,45}]
wire [7:0] _allocatable_slots_T_145 = _allocatable_slots_T_144 | _allocatable_slots_T_138; // @[util.scala:373:{29,45}]
wire [7:0] _allocatable_slots_T_146 = _allocatable_slots_T_145 | _allocatable_slots_T_139; // @[util.scala:373:{29,45}]
wire [7:0] _allocatable_slots_T_147 = _allocatable_slots_T_146 | _allocatable_slots_T_140; // @[util.scala:373:{29,45}]
wire [7:0] _allocatable_slots_T_148 = _allocatable_slots_T_147 | _allocatable_slots_T_141; // @[util.scala:373:{29,45}]
wire [5:0] _allocatable_slots_T_149 = {6{f3_meta_provider_3_valid}}; // @[tage.scala:212:21, :283:45]
wire [7:0] _allocatable_slots_T_150 = {2'h0, _allocatable_slots_T_148[5:0] & _allocatable_slots_T_149}; // @[util.scala:373:45]
wire [7:0] _allocatable_slots_T_151 = ~_allocatable_slots_T_150; // @[tage.scala:283:{7,39}]
wire [7:0] allocatable_slots_3 = {2'h0, _allocatable_slots_T_151[5:0] & _allocatable_slots_T_132}; // @[tage.scala:282:{70,77}, :283:7]
wire [1:0] alloc_lfsr_lo_hi_3 = {_alloc_lfsr_prng_3_io_out_2, _alloc_lfsr_prng_3_io_out_1}; // @[PRNG.scala:91:22, :95:17]
wire [2:0] alloc_lfsr_lo_3 = {alloc_lfsr_lo_hi_3, _alloc_lfsr_prng_3_io_out_0}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] alloc_lfsr_hi_hi_3 = {_alloc_lfsr_prng_3_io_out_5, _alloc_lfsr_prng_3_io_out_4}; // @[PRNG.scala:91:22, :95:17]
wire [2:0] alloc_lfsr_hi_3 = {alloc_lfsr_hi_hi_3, _alloc_lfsr_prng_3_io_out_3}; // @[PRNG.scala:91:22, :95:17]
wire [5:0] alloc_lfsr_3 = {alloc_lfsr_hi_3, alloc_lfsr_lo_3}; // @[PRNG.scala:95:17]
wire _first_entry_T_42 = allocatable_slots_3[0]; // @[OneHot.scala:48:45]
wire _first_entry_T_43 = allocatable_slots_3[1]; // @[OneHot.scala:48:45]
wire _first_entry_T_44 = allocatable_slots_3[2]; // @[OneHot.scala:48:45]
wire _first_entry_T_45 = allocatable_slots_3[3]; // @[OneHot.scala:48:45]
wire _first_entry_T_46 = allocatable_slots_3[4]; // @[OneHot.scala:48:45]
wire _first_entry_T_47 = allocatable_slots_3[5]; // @[OneHot.scala:48:45]
wire _first_entry_T_48 = allocatable_slots_3[6]; // @[OneHot.scala:48:45]
wire _first_entry_T_49 = allocatable_slots_3[7]; // @[OneHot.scala:48:45]
wire [2:0] _first_entry_T_50 = {2'h3, ~_first_entry_T_48}; // @[OneHot.scala:48:45]
wire [2:0] _first_entry_T_51 = _first_entry_T_47 ? 3'h5 : _first_entry_T_50; // @[OneHot.scala:48:45]
wire [2:0] _first_entry_T_52 = _first_entry_T_46 ? 3'h4 : _first_entry_T_51; // @[OneHot.scala:48:45]
wire [2:0] _first_entry_T_53 = _first_entry_T_45 ? 3'h3 : _first_entry_T_52; // @[OneHot.scala:48:45]
wire [2:0] _first_entry_T_54 = _first_entry_T_44 ? 3'h2 : _first_entry_T_53; // @[OneHot.scala:48:45]
wire [2:0] _first_entry_T_55 = _first_entry_T_43 ? 3'h1 : _first_entry_T_54; // @[OneHot.scala:48:45]
wire [2:0] first_entry_3 = _first_entry_T_42 ? 3'h0 : _first_entry_T_55; // @[OneHot.scala:48:45]
wire [7:0] _masked_entry_T_45 = {2'h0, allocatable_slots_3[5:0] & alloc_lfsr_3}; // @[PRNG.scala:95:17]
wire _masked_entry_T_46 = _masked_entry_T_45[0]; // @[OneHot.scala:48:45]
wire _masked_entry_T_47 = _masked_entry_T_45[1]; // @[OneHot.scala:48:45]
wire _masked_entry_T_48 = _masked_entry_T_45[2]; // @[OneHot.scala:48:45]
wire _masked_entry_T_49 = _masked_entry_T_45[3]; // @[OneHot.scala:48:45]
wire _masked_entry_T_50 = _masked_entry_T_45[4]; // @[OneHot.scala:48:45]
wire _masked_entry_T_51 = _masked_entry_T_45[5]; // @[OneHot.scala:48:45]
wire _masked_entry_T_52 = _masked_entry_T_45[6]; // @[OneHot.scala:48:45]
wire _masked_entry_T_53 = _masked_entry_T_45[7]; // @[OneHot.scala:48:45]
wire [2:0] _masked_entry_T_54 = {2'h3, ~_masked_entry_T_52}; // @[OneHot.scala:48:45]
wire [2:0] _masked_entry_T_55 = _masked_entry_T_51 ? 3'h5 : _masked_entry_T_54; // @[OneHot.scala:48:45]
wire [2:0] _masked_entry_T_56 = _masked_entry_T_50 ? 3'h4 : _masked_entry_T_55; // @[OneHot.scala:48:45]
wire [2:0] _masked_entry_T_57 = _masked_entry_T_49 ? 3'h3 : _masked_entry_T_56; // @[OneHot.scala:48:45]
wire [2:0] _masked_entry_T_58 = _masked_entry_T_48 ? 3'h2 : _masked_entry_T_57; // @[OneHot.scala:48:45]
wire [2:0] _masked_entry_T_59 = _masked_entry_T_47 ? 3'h1 : _masked_entry_T_58; // @[OneHot.scala:48:45]
wire [2:0] masked_entry_3 = _masked_entry_T_46 ? 3'h0 : _masked_entry_T_59; // @[OneHot.scala:48:45]
wire [7:0] _alloc_entry_T_6 = allocatable_slots_3 >> masked_entry_3; // @[Mux.scala:50:70]
wire _alloc_entry_T_7 = _alloc_entry_T_6[0]; // @[tage.scala:289:44]
assign alloc_entry_3 = _alloc_entry_T_7 ? masked_entry_3 : first_entry_3; // @[Mux.scala:50:70]
assign f3_meta_allocate_3_bits = alloc_entry_3; // @[tage.scala:212:21, :289:26]
assign _f3_meta_allocate_3_valid_T = |allocatable_slots_3; // @[tage.scala:282:77, :293:52]
assign f3_meta_allocate_3_valid = _f3_meta_allocate_3_valid_T; // @[tage.scala:212:21, :293:52]
wire _update_was_taken_T_6 = &s1_update_bits_cfi_idx_bits; // @[tage.scala:297:58]
wire _update_was_taken_T_7 = s1_update_bits_cfi_idx_valid & _update_was_taken_T_6; // @[tage.scala:296:58, :297:58]
wire update_was_taken_3 = _update_was_taken_T_7 & s1_update_bits_cfi_taken; // @[tage.scala:296:58, :297:67]
wire _T_137 = s1_update_bits_br_mask[3] & s1_update_valid & _GEN_7 == 5'h0; // @[OneHot.scala:58:35]
wire _GEN_35 = _T_137 & s1_update_meta_provider_3_valid & s1_update_meta_provider_3_bits == 3'h0; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37]
wire _GEN_36 = _T_137 & s1_update_meta_provider_3_valid & s1_update_meta_provider_3_bits == 3'h1; // @[tage.scala:218:43, :236:52, :240:33, :299:{37,56,92}, :300:47, :303:37]
wire _GEN_37 = _T_137 & s1_update_meta_provider_3_valid & s1_update_meta_provider_3_bits == 3'h2; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37]
wire _GEN_38 = _T_137 & s1_update_meta_provider_3_valid & s1_update_meta_provider_3_bits == 3'h3; // @[tage.scala:236:52, :240:33, :265:40, :299:{37,56,92}, :300:47, :303:37]
wire _GEN_39 = _T_137 & s1_update_meta_provider_3_valid & s1_update_meta_provider_3_bits == 3'h4; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37]
wire _GEN_40 = _T_137 & s1_update_meta_provider_3_valid & s1_update_meta_provider_3_bits == 3'h5; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37]
wire _new_u_T_33 = s1_update_mispredict_mask[3]; // @[tage.scala:237:73, :308:52]
wire _new_u_T_34 = ~s1_update_meta_alt_differs_3; // @[tage.scala:217:9, :236:52]
wire _new_u_T_35 = s1_update_meta_provider_u_3 == 2'h0; // @[tage.scala:218:27, :236:52]
wire [2:0] _GEN_41 = {1'h0, s1_update_meta_provider_u_3}; // @[tage.scala:218:43, :236:52]
wire [2:0] _new_u_T_36 = _GEN_41 - 3'h1; // @[tage.scala:218:43]
wire [1:0] _new_u_T_37 = _new_u_T_36[1:0]; // @[tage.scala:218:43]
wire [1:0] _new_u_T_38 = _new_u_T_35 ? 2'h0 : _new_u_T_37; // @[tage.scala:218:{24,27,43}]
wire _new_u_T_39 = &s1_update_meta_provider_u_3; // @[tage.scala:219:27, :236:52]
wire [2:0] _new_u_T_40 = _GEN_41 + 3'h1; // @[tage.scala:218:43, :219:43]
wire [1:0] _new_u_T_41 = _new_u_T_40[1:0]; // @[tage.scala:219:43]
wire [1:0] _new_u_T_42 = _new_u_T_39 ? 2'h3 : _new_u_T_41; // @[tage.scala:219:{24,27,43}]
wire [1:0] _new_u_T_43 = _new_u_T_33 ? _new_u_T_38 : _new_u_T_42; // @[tage.scala:218:{8,24}, :219:24, :308:52]
wire [1:0] new_u_3 = _new_u_T_34 ? s1_update_meta_provider_u_3 : _new_u_T_43; // @[tage.scala:217:{8,9}, :218:8, :236:52]
wire _T_144 = s1_update_valid & _GEN_7 == 5'h0 & s1_update_bits_cfi_mispredicted & s1_update_bits_cfi_idx_valid; // @[OneHot.scala:58:35]
wire [3:0] _GEN_42 = {{s1_update_meta_allocate_3_valid}, {s1_update_meta_allocate_2_valid}, {s1_update_meta_allocate_1_valid}, {s1_update_meta_allocate_0_valid}}; // @[tage.scala:236:52, :320:27]
wire _GEN_43 = _GEN_42[s1_update_bits_cfi_idx_bits]; // @[tage.scala:320:27]
wire [3:0][2:0] _GEN_44 = {{s1_update_meta_allocate_3_bits}, {s1_update_meta_allocate_2_bits}, {s1_update_meta_allocate_1_bits}, {s1_update_meta_allocate_0_bits}}; // @[tage.scala:236:52, :320:27]
wire [2:0] _GEN_45 = _GEN_44[s1_update_bits_cfi_idx_bits]; // @[tage.scala:320:27]
wire _GEN_46 = _GEN_45 == 3'h0; // @[tage.scala:320:27, :321:43]
wire _GEN_47 = _T_144 & _GEN_43 & _GEN_46; // @[tage.scala:299:92, :317:{25,60,95,128}, :320:27, :321:43]
assign s1_update_alloc_0_0 = _GEN_47 & _update_was_taken_T; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43]
assign s1_update_mask_0_0 = s1_update_alloc_0_0 | _GEN_8; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43]
assign s1_update_alloc_0_1 = _GEN_47 & _update_was_taken_T_2; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43]
assign s1_update_mask_0_1 = s1_update_alloc_0_1 | _GEN_17; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43]
assign s1_update_alloc_0_2 = _GEN_47 & _update_was_taken_T_4; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43]
assign s1_update_mask_0_2 = s1_update_alloc_0_2 | _GEN_26; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43]
assign s1_update_alloc_0_3 = _GEN_47 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43]
assign s1_update_mask_0_3 = s1_update_alloc_0_3 | _GEN_35; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43]
wire _GEN_48 = _GEN_45 == 3'h1; // @[tage.scala:218:43, :320:27, :321:43]
wire _GEN_49 = _T_144 & _GEN_43 & _GEN_48; // @[tage.scala:299:92, :317:{25,60,95,128}, :320:27, :321:43]
assign s1_update_alloc_1_0 = _GEN_49 & _update_was_taken_T; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43]
assign s1_update_mask_1_0 = s1_update_alloc_1_0 | _GEN_9; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43]
assign s1_update_alloc_1_1 = _GEN_49 & _update_was_taken_T_2; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43]
assign s1_update_mask_1_1 = s1_update_alloc_1_1 | _GEN_18; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43]
assign s1_update_alloc_1_2 = _GEN_49 & _update_was_taken_T_4; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43]
assign s1_update_mask_1_2 = s1_update_alloc_1_2 | _GEN_27; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43]
assign s1_update_alloc_1_3 = _GEN_49 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43]
assign s1_update_mask_1_3 = s1_update_alloc_1_3 | _GEN_36; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43]
wire _GEN_50 = _GEN_45 == 3'h2; // @[tage.scala:320:27, :321:43]
wire _GEN_51 = _T_144 & _GEN_43 & _GEN_50; // @[tage.scala:299:92, :317:{25,60,95,128}, :320:27, :321:43]
assign s1_update_alloc_2_0 = _GEN_51 & _update_was_taken_T; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43]
assign s1_update_mask_2_0 = s1_update_alloc_2_0 | _GEN_10; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43]
assign s1_update_alloc_2_1 = _GEN_51 & _update_was_taken_T_2; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43]
assign s1_update_mask_2_1 = s1_update_alloc_2_1 | _GEN_19; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43]
assign s1_update_alloc_2_2 = _GEN_51 & _update_was_taken_T_4; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43]
assign s1_update_mask_2_2 = s1_update_alloc_2_2 | _GEN_28; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43]
assign s1_update_alloc_2_3 = _GEN_51 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43]
assign s1_update_mask_2_3 = s1_update_alloc_2_3 | _GEN_37; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43]
wire _GEN_52 = _GEN_45 == 3'h3; // @[tage.scala:265:40, :320:27, :321:43]
wire _GEN_53 = _T_144 & _GEN_43 & _GEN_52; // @[tage.scala:299:92, :317:{25,60,95,128}, :320:27, :321:43]
assign s1_update_alloc_3_0 = _GEN_53 & _update_was_taken_T; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43]
assign s1_update_mask_3_0 = s1_update_alloc_3_0 | _GEN_11; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43]
assign s1_update_alloc_3_1 = _GEN_53 & _update_was_taken_T_2; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43]
assign s1_update_mask_3_1 = s1_update_alloc_3_1 | _GEN_20; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43]
assign s1_update_alloc_3_2 = _GEN_53 & _update_was_taken_T_4; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43]
assign s1_update_mask_3_2 = s1_update_alloc_3_2 | _GEN_29; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43]
assign s1_update_alloc_3_3 = _GEN_53 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43]
assign s1_update_mask_3_3 = s1_update_alloc_3_3 | _GEN_38; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43]
wire _GEN_54 = _GEN_45 == 3'h4; // @[tage.scala:320:27, :321:43]
wire _GEN_55 = _T_144 & _GEN_43 & _GEN_54; // @[tage.scala:299:92, :317:{25,60,95,128}, :320:27, :321:43]
assign s1_update_alloc_4_0 = _GEN_55 & _update_was_taken_T; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43]
assign s1_update_mask_4_0 = s1_update_alloc_4_0 | _GEN_12; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43]
assign s1_update_alloc_4_1 = _GEN_55 & _update_was_taken_T_2; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43]
assign s1_update_mask_4_1 = s1_update_alloc_4_1 | _GEN_21; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43]
assign s1_update_alloc_4_2 = _GEN_55 & _update_was_taken_T_4; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43]
assign s1_update_mask_4_2 = s1_update_alloc_4_2 | _GEN_30; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43]
assign s1_update_alloc_4_3 = _GEN_55 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43]
assign s1_update_mask_4_3 = s1_update_alloc_4_3 | _GEN_39; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43]
wire _GEN_56 = _GEN_45 == 3'h5; // @[tage.scala:320:27, :321:43]
wire _GEN_57 = _T_144 & _GEN_43 & _GEN_56; // @[tage.scala:299:92, :317:{25,60,95,128}, :320:27, :321:43]
assign s1_update_alloc_5_0 = _GEN_57 & _update_was_taken_T; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43]
assign s1_update_mask_5_0 = s1_update_alloc_5_0 | _GEN_13; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43]
assign s1_update_alloc_5_1 = _GEN_57 & _update_was_taken_T_2; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43]
assign s1_update_mask_5_1 = s1_update_alloc_5_1 | _GEN_22; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43]
assign s1_update_alloc_5_2 = _GEN_57 & _update_was_taken_T_4; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43]
assign s1_update_mask_5_2 = s1_update_alloc_5_2 | _GEN_31; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43]
assign s1_update_alloc_5_3 = _GEN_57 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43]
assign s1_update_mask_5_3 = s1_update_alloc_5_3 | _GEN_40; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43]
wire _GEN_58 = _GEN_46 & _update_was_taken_T; // @[tage.scala:297:58, :299:92, :321:43, :322:43]
assign s1_update_taken_0_0 = _T_144 & _GEN_43 & _GEN_58 ? s1_update_bits_cfi_taken : update_was_taken; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43]
wire _GEN_59 = _GEN_46 & _update_was_taken_T_2; // @[tage.scala:297:58, :299:92, :321:43, :322:43]
assign s1_update_taken_0_1 = _T_144 & _GEN_43 & _GEN_59 ? s1_update_bits_cfi_taken : update_was_taken_1; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43]
wire _GEN_60 = _GEN_46 & _update_was_taken_T_4; // @[tage.scala:297:58, :299:92, :321:43, :322:43]
assign s1_update_taken_0_2 = _T_144 & _GEN_43 & _GEN_60 ? s1_update_bits_cfi_taken : update_was_taken_2; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43]
wire _GEN_61 = _GEN_46 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:297:58, :299:92, :321:43, :322:43]
assign s1_update_taken_0_3 = _T_144 & _GEN_43 & _GEN_61 ? s1_update_bits_cfi_taken : update_was_taken_3; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43]
wire _GEN_62 = _GEN_48 & _update_was_taken_T; // @[tage.scala:297:58, :299:92, :321:43, :322:43]
assign s1_update_taken_1_0 = _T_144 & _GEN_43 & _GEN_62 ? s1_update_bits_cfi_taken : update_was_taken; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43]
wire _GEN_63 = _GEN_48 & _update_was_taken_T_2; // @[tage.scala:297:58, :299:92, :321:43, :322:43]
assign s1_update_taken_1_1 = _T_144 & _GEN_43 & _GEN_63 ? s1_update_bits_cfi_taken : update_was_taken_1; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43]
wire _GEN_64 = _GEN_48 & _update_was_taken_T_4; // @[tage.scala:297:58, :299:92, :321:43, :322:43]
assign s1_update_taken_1_2 = _T_144 & _GEN_43 & _GEN_64 ? s1_update_bits_cfi_taken : update_was_taken_2; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43]
wire _GEN_65 = _GEN_48 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:297:58, :299:92, :321:43, :322:43]
assign s1_update_taken_1_3 = _T_144 & _GEN_43 & _GEN_65 ? s1_update_bits_cfi_taken : update_was_taken_3; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43]
wire _GEN_66 = _GEN_50 & _update_was_taken_T; // @[tage.scala:297:58, :299:92, :321:43, :322:43]
assign s1_update_taken_2_0 = _T_144 & _GEN_43 & _GEN_66 ? s1_update_bits_cfi_taken : update_was_taken; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43]
wire _GEN_67 = _GEN_50 & _update_was_taken_T_2; // @[tage.scala:297:58, :299:92, :321:43, :322:43]
assign s1_update_taken_2_1 = _T_144 & _GEN_43 & _GEN_67 ? s1_update_bits_cfi_taken : update_was_taken_1; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43]
wire _GEN_68 = _GEN_50 & _update_was_taken_T_4; // @[tage.scala:297:58, :299:92, :321:43, :322:43]
assign s1_update_taken_2_2 = _T_144 & _GEN_43 & _GEN_68 ? s1_update_bits_cfi_taken : update_was_taken_2; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43]
wire _GEN_69 = _GEN_50 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:297:58, :299:92, :321:43, :322:43]
assign s1_update_taken_2_3 = _T_144 & _GEN_43 & _GEN_69 ? s1_update_bits_cfi_taken : update_was_taken_3; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43]
wire _GEN_70 = _GEN_52 & _update_was_taken_T; // @[tage.scala:297:58, :299:92, :321:43, :322:43]
assign s1_update_taken_3_0 = _T_144 & _GEN_43 & _GEN_70 ? s1_update_bits_cfi_taken : update_was_taken; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43]
wire _GEN_71 = _GEN_52 & _update_was_taken_T_2; // @[tage.scala:297:58, :299:92, :321:43, :322:43]
assign s1_update_taken_3_1 = _T_144 & _GEN_43 & _GEN_71 ? s1_update_bits_cfi_taken : update_was_taken_1; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43]
wire _GEN_72 = _GEN_52 & _update_was_taken_T_4; // @[tage.scala:297:58, :299:92, :321:43, :322:43]
assign s1_update_taken_3_2 = _T_144 & _GEN_43 & _GEN_72 ? s1_update_bits_cfi_taken : update_was_taken_2; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43]
wire _GEN_73 = _GEN_52 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:297:58, :299:92, :321:43, :322:43]
assign s1_update_taken_3_3 = _T_144 & _GEN_43 & _GEN_73 ? s1_update_bits_cfi_taken : update_was_taken_3; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43]
wire _GEN_74 = _GEN_54 & _update_was_taken_T; // @[tage.scala:297:58, :299:92, :321:43, :322:43]
assign s1_update_taken_4_0 = _T_144 & _GEN_43 & _GEN_74 ? s1_update_bits_cfi_taken : update_was_taken; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43]
wire _GEN_75 = _GEN_54 & _update_was_taken_T_2; // @[tage.scala:297:58, :299:92, :321:43, :322:43]
assign s1_update_taken_4_1 = _T_144 & _GEN_43 & _GEN_75 ? s1_update_bits_cfi_taken : update_was_taken_1; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43]
wire _GEN_76 = _GEN_54 & _update_was_taken_T_4; // @[tage.scala:297:58, :299:92, :321:43, :322:43]
assign s1_update_taken_4_2 = _T_144 & _GEN_43 & _GEN_76 ? s1_update_bits_cfi_taken : update_was_taken_2; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43]
wire _GEN_77 = _GEN_54 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:297:58, :299:92, :321:43, :322:43]
assign s1_update_taken_4_3 = _T_144 & _GEN_43 & _GEN_77 ? s1_update_bits_cfi_taken : update_was_taken_3; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43]
wire _GEN_78 = _GEN_56 & _update_was_taken_T; // @[tage.scala:297:58, :299:92, :321:43, :322:43]
assign s1_update_taken_5_0 = _T_144 & _GEN_43 & _GEN_78 ? s1_update_bits_cfi_taken : update_was_taken; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43]
wire _GEN_79 = _GEN_56 & _update_was_taken_T_2; // @[tage.scala:297:58, :299:92, :321:43, :322:43]
assign s1_update_taken_5_1 = _T_144 & _GEN_43 & _GEN_79 ? s1_update_bits_cfi_taken : update_was_taken_1; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43]
wire _GEN_80 = _GEN_56 & _update_was_taken_T_4; // @[tage.scala:297:58, :299:92, :321:43, :322:43]
assign s1_update_taken_5_2 = _T_144 & _GEN_43 & _GEN_80 ? s1_update_bits_cfi_taken : update_was_taken_2; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43]
wire _GEN_81 = _GEN_56 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:297:58, :299:92, :321:43, :322:43]
assign s1_update_taken_5_3 = _T_144 & _GEN_43 & _GEN_81 ? s1_update_bits_cfi_taken : update_was_taken_3; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43]
wire [3:0] _GEN_82 = {{s1_update_meta_provider_3_valid}, {s1_update_meta_provider_2_valid}, {s1_update_meta_provider_1_valid}, {s1_update_meta_provider_0_valid}}; // @[OneHot.scala:58:35]
wire [3:0][2:0] _GEN_83 = {{s1_update_meta_provider_3_bits}, {s1_update_meta_provider_2_bits}, {s1_update_meta_provider_1_bits}, {s1_update_meta_provider_0_bits}}; // @[OneHot.scala:58:35]
wire [7:0] _decr_mask_T = 8'h1 << _GEN_83[s1_update_bits_cfi_idx_bits]; // @[OneHot.scala:58:35]
wire [7:0] _decr_mask_T_1 = _decr_mask_T; // @[OneHot.scala:58:35]
wire [7:0] _decr_mask_T_2 = {1'h0, _decr_mask_T[7:1]}; // @[OneHot.scala:58:35]
wire [7:0] _decr_mask_T_3 = {2'h0, _decr_mask_T[7:2]}; // @[OneHot.scala:58:35]
wire [7:0] _decr_mask_T_4 = {3'h0, _decr_mask_T[7:3]}; // @[OneHot.scala:58:35]
wire [7:0] _decr_mask_T_5 = {4'h0, _decr_mask_T[7:4]}; // @[OneHot.scala:58:35]
wire [7:0] _decr_mask_T_6 = {5'h0, _decr_mask_T[7:5]}; // @[OneHot.scala:58:35]
wire [7:0] _decr_mask_T_7 = {6'h0, _decr_mask_T[7:6]}; // @[OneHot.scala:58:35]
wire [7:0] _decr_mask_T_8 = {7'h0, _decr_mask_T[7]}; // @[OneHot.scala:58:35]
wire [7:0] _decr_mask_T_9 = _decr_mask_T_1 | _decr_mask_T_2; // @[util.scala:373:{29,45}]
wire [7:0] _decr_mask_T_10 = _decr_mask_T_9 | _decr_mask_T_3; // @[util.scala:373:{29,45}]
wire [7:0] _decr_mask_T_11 = _decr_mask_T_10 | _decr_mask_T_4; // @[util.scala:373:{29,45}]
wire [7:0] _decr_mask_T_12 = _decr_mask_T_11 | _decr_mask_T_5; // @[util.scala:373:{29,45}]
wire [7:0] _decr_mask_T_13 = _decr_mask_T_12 | _decr_mask_T_6; // @[util.scala:373:{29,45}]
wire [7:0] _decr_mask_T_14 = _decr_mask_T_13 | _decr_mask_T_7; // @[util.scala:373:{29,45}]
wire [7:0] _decr_mask_T_15 = _decr_mask_T_14 | _decr_mask_T_8; // @[util.scala:373:{29,45}]
wire [7:0] _decr_mask_T_16 = ~_decr_mask_T_15; // @[util.scala:373:45]
wire [7:0] decr_mask = _GEN_82[s1_update_bits_cfi_idx_bits] ? _decr_mask_T_16 : 8'h0; // @[OneHot.scala:58:35]
assign s1_update_u_mask_0_0 = _T_144 ? (_GEN_43 ? _GEN_46 & _update_was_taken_T | _GEN_8 : decr_mask[0] & _update_was_taken_T | _GEN_8) : _GEN_8; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36]
assign s1_update_u_mask_0_1 = _T_144 ? (_GEN_43 ? _GEN_46 & _update_was_taken_T_2 | _GEN_17 : decr_mask[0] & _update_was_taken_T_2 | _GEN_17) : _GEN_17; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36]
assign s1_update_u_mask_0_2 = _T_144 ? (_GEN_43 ? _GEN_46 & _update_was_taken_T_4 | _GEN_26 : decr_mask[0] & _update_was_taken_T_4 | _GEN_26) : _GEN_26; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36]
assign s1_update_u_mask_0_3 = _T_144 ? (_GEN_43 ? _GEN_46 & (&s1_update_bits_cfi_idx_bits) | _GEN_35 : decr_mask[0] & (&s1_update_bits_cfi_idx_bits) | _GEN_35) : _GEN_35; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36]
assign s1_update_u_0_0 = _T_144 & (_GEN_43 ? _GEN_58 : decr_mask[0] & _update_was_taken_T) ? 2'h0 : new_u; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36]
assign s1_update_u_0_1 = _T_144 & (_GEN_43 ? _GEN_59 : decr_mask[0] & _update_was_taken_T_2) ? 2'h0 : new_u_1; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36]
assign s1_update_u_0_2 = _T_144 & (_GEN_43 ? _GEN_60 : decr_mask[0] & _update_was_taken_T_4) ? 2'h0 : new_u_2; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36]
assign s1_update_u_0_3 = _T_144 & (_GEN_43 ? _GEN_61 : decr_mask[0] & (&s1_update_bits_cfi_idx_bits)) ? 2'h0 : new_u_3; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36]
assign s1_update_u_mask_1_0 = _T_144 ? (_GEN_43 ? _GEN_48 & _update_was_taken_T | _GEN_9 : decr_mask[1] & _update_was_taken_T | _GEN_9) : _GEN_9; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36]
assign s1_update_u_mask_1_1 = _T_144 ? (_GEN_43 ? _GEN_48 & _update_was_taken_T_2 | _GEN_18 : decr_mask[1] & _update_was_taken_T_2 | _GEN_18) : _GEN_18; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36]
assign s1_update_u_mask_1_2 = _T_144 ? (_GEN_43 ? _GEN_48 & _update_was_taken_T_4 | _GEN_27 : decr_mask[1] & _update_was_taken_T_4 | _GEN_27) : _GEN_27; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36]
assign s1_update_u_mask_1_3 = _T_144 ? (_GEN_43 ? _GEN_48 & (&s1_update_bits_cfi_idx_bits) | _GEN_36 : decr_mask[1] & (&s1_update_bits_cfi_idx_bits) | _GEN_36) : _GEN_36; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36]
assign s1_update_u_1_0 = _T_144 & (_GEN_43 ? _GEN_62 : decr_mask[1] & _update_was_taken_T) ? 2'h0 : new_u; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36]
assign s1_update_u_1_1 = _T_144 & (_GEN_43 ? _GEN_63 : decr_mask[1] & _update_was_taken_T_2) ? 2'h0 : new_u_1; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36]
assign s1_update_u_1_2 = _T_144 & (_GEN_43 ? _GEN_64 : decr_mask[1] & _update_was_taken_T_4) ? 2'h0 : new_u_2; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36]
assign s1_update_u_1_3 = _T_144 & (_GEN_43 ? _GEN_65 : decr_mask[1] & (&s1_update_bits_cfi_idx_bits)) ? 2'h0 : new_u_3; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36]
assign s1_update_u_mask_2_0 = _T_144 ? (_GEN_43 ? _GEN_50 & _update_was_taken_T | _GEN_10 : decr_mask[2] & _update_was_taken_T | _GEN_10) : _GEN_10; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36]
assign s1_update_u_mask_2_1 = _T_144 ? (_GEN_43 ? _GEN_50 & _update_was_taken_T_2 | _GEN_19 : decr_mask[2] & _update_was_taken_T_2 | _GEN_19) : _GEN_19; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36]
assign s1_update_u_mask_2_2 = _T_144 ? (_GEN_43 ? _GEN_50 & _update_was_taken_T_4 | _GEN_28 : decr_mask[2] & _update_was_taken_T_4 | _GEN_28) : _GEN_28; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36]
assign s1_update_u_mask_2_3 = _T_144 ? (_GEN_43 ? _GEN_50 & (&s1_update_bits_cfi_idx_bits) | _GEN_37 : decr_mask[2] & (&s1_update_bits_cfi_idx_bits) | _GEN_37) : _GEN_37; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36]
assign s1_update_u_2_0 = _T_144 & (_GEN_43 ? _GEN_66 : decr_mask[2] & _update_was_taken_T) ? 2'h0 : new_u; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36]
assign s1_update_u_2_1 = _T_144 & (_GEN_43 ? _GEN_67 : decr_mask[2] & _update_was_taken_T_2) ? 2'h0 : new_u_1; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36]
assign s1_update_u_2_2 = _T_144 & (_GEN_43 ? _GEN_68 : decr_mask[2] & _update_was_taken_T_4) ? 2'h0 : new_u_2; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36]
assign s1_update_u_2_3 = _T_144 & (_GEN_43 ? _GEN_69 : decr_mask[2] & (&s1_update_bits_cfi_idx_bits)) ? 2'h0 : new_u_3; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36]
assign s1_update_u_mask_3_0 = _T_144 ? (_GEN_43 ? _GEN_52 & _update_was_taken_T | _GEN_11 : decr_mask[3] & _update_was_taken_T | _GEN_11) : _GEN_11; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36]
assign s1_update_u_mask_3_1 = _T_144 ? (_GEN_43 ? _GEN_52 & _update_was_taken_T_2 | _GEN_20 : decr_mask[3] & _update_was_taken_T_2 | _GEN_20) : _GEN_20; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36]
assign s1_update_u_mask_3_2 = _T_144 ? (_GEN_43 ? _GEN_52 & _update_was_taken_T_4 | _GEN_29 : decr_mask[3] & _update_was_taken_T_4 | _GEN_29) : _GEN_29; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36]
assign s1_update_u_mask_3_3 = _T_144 ? (_GEN_43 ? _GEN_52 & (&s1_update_bits_cfi_idx_bits) | _GEN_38 : decr_mask[3] & (&s1_update_bits_cfi_idx_bits) | _GEN_38) : _GEN_38; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36]
assign s1_update_u_3_0 = _T_144 & (_GEN_43 ? _GEN_70 : decr_mask[3] & _update_was_taken_T) ? 2'h0 : new_u; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36]
assign s1_update_u_3_1 = _T_144 & (_GEN_43 ? _GEN_71 : decr_mask[3] & _update_was_taken_T_2) ? 2'h0 : new_u_1; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36]
assign s1_update_u_3_2 = _T_144 & (_GEN_43 ? _GEN_72 : decr_mask[3] & _update_was_taken_T_4) ? 2'h0 : new_u_2; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36]
assign s1_update_u_3_3 = _T_144 & (_GEN_43 ? _GEN_73 : decr_mask[3] & (&s1_update_bits_cfi_idx_bits)) ? 2'h0 : new_u_3; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36]
assign s1_update_u_mask_4_0 = _T_144 ? (_GEN_43 ? _GEN_54 & _update_was_taken_T | _GEN_12 : decr_mask[4] & _update_was_taken_T | _GEN_12) : _GEN_12; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36]
assign s1_update_u_mask_4_1 = _T_144 ? (_GEN_43 ? _GEN_54 & _update_was_taken_T_2 | _GEN_21 : decr_mask[4] & _update_was_taken_T_2 | _GEN_21) : _GEN_21; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36]
assign s1_update_u_mask_4_2 = _T_144 ? (_GEN_43 ? _GEN_54 & _update_was_taken_T_4 | _GEN_30 : decr_mask[4] & _update_was_taken_T_4 | _GEN_30) : _GEN_30; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36]
assign s1_update_u_mask_4_3 = _T_144 ? (_GEN_43 ? _GEN_54 & (&s1_update_bits_cfi_idx_bits) | _GEN_39 : decr_mask[4] & (&s1_update_bits_cfi_idx_bits) | _GEN_39) : _GEN_39; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36]
assign s1_update_u_4_0 = _T_144 & (_GEN_43 ? _GEN_74 : decr_mask[4] & _update_was_taken_T) ? 2'h0 : new_u; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36]
assign s1_update_u_4_1 = _T_144 & (_GEN_43 ? _GEN_75 : decr_mask[4] & _update_was_taken_T_2) ? 2'h0 : new_u_1; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36]
assign s1_update_u_4_2 = _T_144 & (_GEN_43 ? _GEN_76 : decr_mask[4] & _update_was_taken_T_4) ? 2'h0 : new_u_2; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36]
assign s1_update_u_4_3 = _T_144 & (_GEN_43 ? _GEN_77 : decr_mask[4] & (&s1_update_bits_cfi_idx_bits)) ? 2'h0 : new_u_3; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36]
assign s1_update_u_mask_5_0 = _T_144 ? (_GEN_43 ? _GEN_56 & _update_was_taken_T | _GEN_13 : decr_mask[5] & _update_was_taken_T | _GEN_13) : _GEN_13; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36]
assign s1_update_u_mask_5_1 = _T_144 ? (_GEN_43 ? _GEN_56 & _update_was_taken_T_2 | _GEN_22 : decr_mask[5] & _update_was_taken_T_2 | _GEN_22) : _GEN_22; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36]
assign s1_update_u_mask_5_2 = _T_144 ? (_GEN_43 ? _GEN_56 & _update_was_taken_T_4 | _GEN_31 : decr_mask[5] & _update_was_taken_T_4 | _GEN_31) : _GEN_31; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36]
assign s1_update_u_mask_5_3 = _T_144 ? (_GEN_43 ? _GEN_56 & (&s1_update_bits_cfi_idx_bits) | _GEN_40 : decr_mask[5] & (&s1_update_bits_cfi_idx_bits) | _GEN_40) : _GEN_40; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36]
assign s1_update_u_5_0 = _T_144 & (_GEN_43 ? _GEN_78 : decr_mask[5] & _update_was_taken_T) ? 2'h0 : new_u; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36]
assign s1_update_u_5_1 = _T_144 & (_GEN_43 ? _GEN_79 : decr_mask[5] & _update_was_taken_T_2) ? 2'h0 : new_u_1; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36]
assign s1_update_u_5_2 = _T_144 & (_GEN_43 ? _GEN_80 : decr_mask[5] & _update_was_taken_T_4) ? 2'h0 : new_u_2; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36]
assign s1_update_u_5_3 = _T_144 & (_GEN_43 ? _GEN_81 : decr_mask[5] & (&s1_update_bits_cfi_idx_bits)) ? 2'h0 : new_u_3; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36]
reg tt_0_1_io_update_mask_0_REG; // @[tage.scala:345:48]
reg tt_0_1_io_update_taken_0_REG; // @[tage.scala:346:48]
reg tt_0_1_io_update_alloc_0_REG; // @[tage.scala:347:48]
reg [2:0] tt_0_1_io_update_old_ctr_0_REG; // @[tage.scala:348:48]
reg tt_0_1_io_update_u_mask_0_REG; // @[tage.scala:350:47]
reg [1:0] tt_0_1_io_update_u_0_REG; // @[tage.scala:351:47]
reg tt_0_1_io_update_mask_1_REG; // @[tage.scala:345:48]
reg tt_0_1_io_update_taken_1_REG; // @[tage.scala:346:48]
reg tt_0_1_io_update_alloc_1_REG; // @[tage.scala:347:48]
reg [2:0] tt_0_1_io_update_old_ctr_1_REG; // @[tage.scala:348:48]
reg tt_0_1_io_update_u_mask_1_REG; // @[tage.scala:350:47]
reg [1:0] tt_0_1_io_update_u_1_REG; // @[tage.scala:351:47]
reg tt_0_1_io_update_mask_2_REG; // @[tage.scala:345:48]
reg tt_0_1_io_update_taken_2_REG; // @[tage.scala:346:48]
reg tt_0_1_io_update_alloc_2_REG; // @[tage.scala:347:48]
reg [2:0] tt_0_1_io_update_old_ctr_2_REG; // @[tage.scala:348:48]
reg tt_0_1_io_update_u_mask_2_REG; // @[tage.scala:350:47]
reg [1:0] tt_0_1_io_update_u_2_REG; // @[tage.scala:351:47]
reg tt_0_1_io_update_mask_3_REG; // @[tage.scala:345:48]
reg tt_0_1_io_update_taken_3_REG; // @[tage.scala:346:48]
reg tt_0_1_io_update_alloc_3_REG; // @[tage.scala:347:48]
reg [2:0] tt_0_1_io_update_old_ctr_3_REG; // @[tage.scala:348:48]
reg tt_0_1_io_update_u_mask_3_REG; // @[tage.scala:350:47]
reg [1:0] tt_0_1_io_update_u_3_REG; // @[tage.scala:351:47]
reg [39:0] tt_0_1_io_update_pc_REG; // @[tage.scala:353:41]
reg [63:0] tt_0_1_io_update_hist_REG; // @[tage.scala:354:41]
reg tt_1_1_io_update_mask_0_REG; // @[tage.scala:345:48]
reg tt_1_1_io_update_taken_0_REG; // @[tage.scala:346:48]
reg tt_1_1_io_update_alloc_0_REG; // @[tage.scala:347:48]
reg [2:0] tt_1_1_io_update_old_ctr_0_REG; // @[tage.scala:348:48]
reg tt_1_1_io_update_u_mask_0_REG; // @[tage.scala:350:47]
reg [1:0] tt_1_1_io_update_u_0_REG; // @[tage.scala:351:47]
reg tt_1_1_io_update_mask_1_REG; // @[tage.scala:345:48]
reg tt_1_1_io_update_taken_1_REG; // @[tage.scala:346:48]
reg tt_1_1_io_update_alloc_1_REG; // @[tage.scala:347:48]
reg [2:0] tt_1_1_io_update_old_ctr_1_REG; // @[tage.scala:348:48]
reg tt_1_1_io_update_u_mask_1_REG; // @[tage.scala:350:47]
reg [1:0] tt_1_1_io_update_u_1_REG; // @[tage.scala:351:47]
reg tt_1_1_io_update_mask_2_REG; // @[tage.scala:345:48]
reg tt_1_1_io_update_taken_2_REG; // @[tage.scala:346:48]
reg tt_1_1_io_update_alloc_2_REG; // @[tage.scala:347:48]
reg [2:0] tt_1_1_io_update_old_ctr_2_REG; // @[tage.scala:348:48]
reg tt_1_1_io_update_u_mask_2_REG; // @[tage.scala:350:47]
reg [1:0] tt_1_1_io_update_u_2_REG; // @[tage.scala:351:47]
reg tt_1_1_io_update_mask_3_REG; // @[tage.scala:345:48]
reg tt_1_1_io_update_taken_3_REG; // @[tage.scala:346:48]
reg tt_1_1_io_update_alloc_3_REG; // @[tage.scala:347:48]
reg [2:0] tt_1_1_io_update_old_ctr_3_REG; // @[tage.scala:348:48]
reg tt_1_1_io_update_u_mask_3_REG; // @[tage.scala:350:47]
reg [1:0] tt_1_1_io_update_u_3_REG; // @[tage.scala:351:47]
reg [39:0] tt_1_1_io_update_pc_REG; // @[tage.scala:353:41]
reg [63:0] tt_1_1_io_update_hist_REG; // @[tage.scala:354:41]
reg tt_2_1_io_update_mask_0_REG; // @[tage.scala:345:48]
reg tt_2_1_io_update_taken_0_REG; // @[tage.scala:346:48]
reg tt_2_1_io_update_alloc_0_REG; // @[tage.scala:347:48]
reg [2:0] tt_2_1_io_update_old_ctr_0_REG; // @[tage.scala:348:48]
reg tt_2_1_io_update_u_mask_0_REG; // @[tage.scala:350:47]
reg [1:0] tt_2_1_io_update_u_0_REG; // @[tage.scala:351:47]
reg tt_2_1_io_update_mask_1_REG; // @[tage.scala:345:48]
reg tt_2_1_io_update_taken_1_REG; // @[tage.scala:346:48]
reg tt_2_1_io_update_alloc_1_REG; // @[tage.scala:347:48]
reg [2:0] tt_2_1_io_update_old_ctr_1_REG; // @[tage.scala:348:48]
reg tt_2_1_io_update_u_mask_1_REG; // @[tage.scala:350:47]
reg [1:0] tt_2_1_io_update_u_1_REG; // @[tage.scala:351:47]
reg tt_2_1_io_update_mask_2_REG; // @[tage.scala:345:48]
reg tt_2_1_io_update_taken_2_REG; // @[tage.scala:346:48]
reg tt_2_1_io_update_alloc_2_REG; // @[tage.scala:347:48]
reg [2:0] tt_2_1_io_update_old_ctr_2_REG; // @[tage.scala:348:48]
reg tt_2_1_io_update_u_mask_2_REG; // @[tage.scala:350:47]
reg [1:0] tt_2_1_io_update_u_2_REG; // @[tage.scala:351:47]
reg tt_2_1_io_update_mask_3_REG; // @[tage.scala:345:48]
reg tt_2_1_io_update_taken_3_REG; // @[tage.scala:346:48]
reg tt_2_1_io_update_alloc_3_REG; // @[tage.scala:347:48]
reg [2:0] tt_2_1_io_update_old_ctr_3_REG; // @[tage.scala:348:48]
reg tt_2_1_io_update_u_mask_3_REG; // @[tage.scala:350:47]
reg [1:0] tt_2_1_io_update_u_3_REG; // @[tage.scala:351:47]
reg [39:0] tt_2_1_io_update_pc_REG; // @[tage.scala:353:41]
reg [63:0] tt_2_1_io_update_hist_REG; // @[tage.scala:354:41]
reg tt_3_1_io_update_mask_0_REG; // @[tage.scala:345:48]
reg tt_3_1_io_update_taken_0_REG; // @[tage.scala:346:48]
reg tt_3_1_io_update_alloc_0_REG; // @[tage.scala:347:48]
reg [2:0] tt_3_1_io_update_old_ctr_0_REG; // @[tage.scala:348:48]
reg tt_3_1_io_update_u_mask_0_REG; // @[tage.scala:350:47]
reg [1:0] tt_3_1_io_update_u_0_REG; // @[tage.scala:351:47]
reg tt_3_1_io_update_mask_1_REG; // @[tage.scala:345:48]
reg tt_3_1_io_update_taken_1_REG; // @[tage.scala:346:48]
reg tt_3_1_io_update_alloc_1_REG; // @[tage.scala:347:48]
reg [2:0] tt_3_1_io_update_old_ctr_1_REG; // @[tage.scala:348:48]
reg tt_3_1_io_update_u_mask_1_REG; // @[tage.scala:350:47]
reg [1:0] tt_3_1_io_update_u_1_REG; // @[tage.scala:351:47]
reg tt_3_1_io_update_mask_2_REG; // @[tage.scala:345:48]
reg tt_3_1_io_update_taken_2_REG; // @[tage.scala:346:48]
reg tt_3_1_io_update_alloc_2_REG; // @[tage.scala:347:48]
reg [2:0] tt_3_1_io_update_old_ctr_2_REG; // @[tage.scala:348:48]
reg tt_3_1_io_update_u_mask_2_REG; // @[tage.scala:350:47]
reg [1:0] tt_3_1_io_update_u_2_REG; // @[tage.scala:351:47]
reg tt_3_1_io_update_mask_3_REG; // @[tage.scala:345:48]
reg tt_3_1_io_update_taken_3_REG; // @[tage.scala:346:48]
reg tt_3_1_io_update_alloc_3_REG; // @[tage.scala:347:48]
reg [2:0] tt_3_1_io_update_old_ctr_3_REG; // @[tage.scala:348:48]
reg tt_3_1_io_update_u_mask_3_REG; // @[tage.scala:350:47]
reg [1:0] tt_3_1_io_update_u_3_REG; // @[tage.scala:351:47]
reg [39:0] tt_3_1_io_update_pc_REG; // @[tage.scala:353:41]
reg [63:0] tt_3_1_io_update_hist_REG; // @[tage.scala:354:41]
reg tt_4_1_io_update_mask_0_REG; // @[tage.scala:345:48]
reg tt_4_1_io_update_taken_0_REG; // @[tage.scala:346:48]
reg tt_4_1_io_update_alloc_0_REG; // @[tage.scala:347:48]
reg [2:0] tt_4_1_io_update_old_ctr_0_REG; // @[tage.scala:348:48]
reg tt_4_1_io_update_u_mask_0_REG; // @[tage.scala:350:47]
reg [1:0] tt_4_1_io_update_u_0_REG; // @[tage.scala:351:47]
reg tt_4_1_io_update_mask_1_REG; // @[tage.scala:345:48]
reg tt_4_1_io_update_taken_1_REG; // @[tage.scala:346:48]
reg tt_4_1_io_update_alloc_1_REG; // @[tage.scala:347:48]
reg [2:0] tt_4_1_io_update_old_ctr_1_REG; // @[tage.scala:348:48]
reg tt_4_1_io_update_u_mask_1_REG; // @[tage.scala:350:47]
reg [1:0] tt_4_1_io_update_u_1_REG; // @[tage.scala:351:47]
reg tt_4_1_io_update_mask_2_REG; // @[tage.scala:345:48]
reg tt_4_1_io_update_taken_2_REG; // @[tage.scala:346:48]
reg tt_4_1_io_update_alloc_2_REG; // @[tage.scala:347:48]
reg [2:0] tt_4_1_io_update_old_ctr_2_REG; // @[tage.scala:348:48]
reg tt_4_1_io_update_u_mask_2_REG; // @[tage.scala:350:47]
reg [1:0] tt_4_1_io_update_u_2_REG; // @[tage.scala:351:47]
reg tt_4_1_io_update_mask_3_REG; // @[tage.scala:345:48]
reg tt_4_1_io_update_taken_3_REG; // @[tage.scala:346:48]
reg tt_4_1_io_update_alloc_3_REG; // @[tage.scala:347:48]
reg [2:0] tt_4_1_io_update_old_ctr_3_REG; // @[tage.scala:348:48]
reg tt_4_1_io_update_u_mask_3_REG; // @[tage.scala:350:47]
reg [1:0] tt_4_1_io_update_u_3_REG; // @[tage.scala:351:47]
reg [39:0] tt_4_1_io_update_pc_REG; // @[tage.scala:353:41]
reg [63:0] tt_4_1_io_update_hist_REG; // @[tage.scala:354:41]
reg tt_5_1_io_update_mask_0_REG; // @[tage.scala:345:48]
reg tt_5_1_io_update_taken_0_REG; // @[tage.scala:346:48]
reg tt_5_1_io_update_alloc_0_REG; // @[tage.scala:347:48]
reg [2:0] tt_5_1_io_update_old_ctr_0_REG; // @[tage.scala:348:48]
reg tt_5_1_io_update_u_mask_0_REG; // @[tage.scala:350:47]
reg [1:0] tt_5_1_io_update_u_0_REG; // @[tage.scala:351:47]
reg tt_5_1_io_update_mask_1_REG; // @[tage.scala:345:48]
reg tt_5_1_io_update_taken_1_REG; // @[tage.scala:346:48]
reg tt_5_1_io_update_alloc_1_REG; // @[tage.scala:347:48]
reg [2:0] tt_5_1_io_update_old_ctr_1_REG; // @[tage.scala:348:48]
reg tt_5_1_io_update_u_mask_1_REG; // @[tage.scala:350:47]
reg [1:0] tt_5_1_io_update_u_1_REG; // @[tage.scala:351:47]
reg tt_5_1_io_update_mask_2_REG; // @[tage.scala:345:48]
reg tt_5_1_io_update_taken_2_REG; // @[tage.scala:346:48]
reg tt_5_1_io_update_alloc_2_REG; // @[tage.scala:347:48]
reg [2:0] tt_5_1_io_update_old_ctr_2_REG; // @[tage.scala:348:48]
reg tt_5_1_io_update_u_mask_2_REG; // @[tage.scala:350:47]
reg [1:0] tt_5_1_io_update_u_2_REG; // @[tage.scala:351:47]
reg tt_5_1_io_update_mask_3_REG; // @[tage.scala:345:48]
reg tt_5_1_io_update_taken_3_REG; // @[tage.scala:346:48]
reg tt_5_1_io_update_alloc_3_REG; // @[tage.scala:347:48]
reg [2:0] tt_5_1_io_update_old_ctr_3_REG; // @[tage.scala:348:48]
reg tt_5_1_io_update_u_mask_3_REG; // @[tage.scala:350:47]
reg [1:0] tt_5_1_io_update_u_3_REG; // @[tage.scala:351:47]
reg [39:0] tt_5_1_io_update_pc_REG; // @[tage.scala:353:41]
reg [63:0] tt_5_1_io_update_hist_REG; // @[tage.scala:354:41]
wire [7:0] io_f3_meta_lo = {_io_f3_meta_T_1, _io_f3_meta_T}; // @[tage.scala:359:25]
wire [7:0] io_f3_meta_hi = {_io_f3_meta_T_3, _io_f3_meta_T_2}; // @[tage.scala:359:25]
wire [15:0] _io_f3_meta_T_4 = {io_f3_meta_hi, io_f3_meta_lo}; // @[tage.scala:359:25]
wire [11:0] _io_f3_meta_T_5 = {io_f3_meta_hi_1, io_f3_meta_lo_1}; // @[tage.scala:359:25]
wire [7:0] _io_f3_meta_T_6 = {io_f3_meta_hi_2, io_f3_meta_lo_2}; // @[tage.scala:359:25]
wire [3:0] _io_f3_meta_T_7 = {io_f3_meta_hi_3, io_f3_meta_lo_3}; // @[tage.scala:359:25]
wire [7:0] io_f3_meta_lo_4 = {_io_f3_meta_T_9, _io_f3_meta_T_8}; // @[tage.scala:359:25]
wire [7:0] io_f3_meta_hi_4 = {_io_f3_meta_T_11, _io_f3_meta_T_10}; // @[tage.scala:359:25]
wire [15:0] _io_f3_meta_T_12 = {io_f3_meta_hi_4, io_f3_meta_lo_4}; // @[tage.scala:359:25]
wire [27:0] io_f3_meta_lo_5 = {_io_f3_meta_T_5, _io_f3_meta_T_4}; // @[tage.scala:359:25]
wire [19:0] io_f3_meta_hi_hi = {_io_f3_meta_T_12, _io_f3_meta_T_7}; // @[tage.scala:359:25]
wire [27:0] io_f3_meta_hi_5 = {io_f3_meta_hi_hi, _io_f3_meta_T_6}; // @[tage.scala:359:25]
wire [55:0] _io_f3_meta_T_13 = {io_f3_meta_hi_5, io_f3_meta_lo_5}; // @[tage.scala:359:25]
assign io_f3_meta_0 = {64'h0, _io_f3_meta_T_13}; // @[tage.scala:198:7, :359:{14,25}]
always @(posedge clock) begin // @[tage.scala:198:7]
s1_idx <= s0_idx; // @[frontend.scala:162:35]
s2_idx <= s1_idx; // @[predictor.scala:163:29, :164:29]
s3_idx <= s2_idx; // @[predictor.scala:164:29, :165:29]
s1_valid <= io_f0_valid_0; // @[tage.scala:198:7]
s2_valid <= s1_valid; // @[predictor.scala:168:25, :169:25]
s3_valid <= s2_valid; // @[predictor.scala:169:25, :170:25]
s1_mask <= io_f0_mask_0; // @[tage.scala:198:7]
s2_mask <= s1_mask; // @[predictor.scala:173:24, :174:24]
s3_mask <= s2_mask; // @[predictor.scala:174:24, :175:24]
s1_pc <= io_f0_pc_0; // @[tage.scala:198:7]
s1_update_valid <= io_update_valid_0; // @[tage.scala:198:7]
s1_update_bits_is_mispredict_update <= io_update_bits_is_mispredict_update_0; // @[tage.scala:198:7]
s1_update_bits_is_repair_update <= io_update_bits_is_repair_update_0; // @[tage.scala:198:7]
s1_update_bits_btb_mispredicts <= io_update_bits_btb_mispredicts_0; // @[tage.scala:198:7]
s1_update_bits_pc <= io_update_bits_pc_0; // @[tage.scala:198:7]
s1_update_bits_br_mask <= io_update_bits_br_mask_0; // @[tage.scala:198:7]
s1_update_bits_cfi_idx_valid <= io_update_bits_cfi_idx_valid_0; // @[tage.scala:198:7]
s1_update_bits_cfi_idx_bits <= io_update_bits_cfi_idx_bits_0; // @[tage.scala:198:7]
s1_update_bits_cfi_taken <= io_update_bits_cfi_taken_0; // @[tage.scala:198:7]
s1_update_bits_cfi_mispredicted <= io_update_bits_cfi_mispredicted_0; // @[tage.scala:198:7]
s1_update_bits_cfi_is_br <= io_update_bits_cfi_is_br_0; // @[tage.scala:198:7]
s1_update_bits_cfi_is_jal <= io_update_bits_cfi_is_jal_0; // @[tage.scala:198:7]
s1_update_bits_cfi_is_jalr <= io_update_bits_cfi_is_jalr_0; // @[tage.scala:198:7]
s1_update_bits_ghist <= io_update_bits_ghist_0; // @[tage.scala:198:7]
s1_update_bits_lhist <= io_update_bits_lhist_0; // @[tage.scala:198:7]
s1_update_bits_target <= io_update_bits_target_0; // @[tage.scala:198:7]
s1_update_bits_meta <= io_update_bits_meta_0; // @[tage.scala:198:7]
s1_update_idx <= s0_update_idx; // @[frontend.scala:162:35]
s1_update_valid_0 <= io_update_valid_0; // @[tage.scala:198:7]
t_io_f1_req_valid_REG <= io_f0_valid_0; // @[tage.scala:198:7, :225:35]
t_io_f1_req_pc_REG <= io_f0_pc_0; // @[tage.scala:198:7, :226:35]
t_io_f1_req_valid_REG_1 <= io_f0_valid_0; // @[tage.scala:198:7, :225:35]
t_io_f1_req_pc_REG_1 <= io_f0_pc_0; // @[tage.scala:198:7, :226:35]
t_io_f1_req_valid_REG_2 <= io_f0_valid_0; // @[tage.scala:198:7, :225:35]
t_io_f1_req_pc_REG_2 <= io_f0_pc_0; // @[tage.scala:198:7, :226:35]
t_io_f1_req_valid_REG_3 <= io_f0_valid_0; // @[tage.scala:198:7, :225:35]
t_io_f1_req_pc_REG_3 <= io_f0_pc_0; // @[tage.scala:198:7, :226:35]
t_io_f1_req_valid_REG_4 <= io_f0_valid_0; // @[tage.scala:198:7, :225:35]
t_io_f1_req_pc_REG_4 <= io_f0_pc_0; // @[tage.scala:198:7, :226:35]
t_io_f1_req_valid_REG_5 <= io_f0_valid_0; // @[tage.scala:198:7, :225:35]
t_io_f1_req_pc_REG_5 <= io_f0_pc_0; // @[tage.scala:198:7, :226:35]
tt_0_1_io_update_mask_0_REG <= s1_update_mask_0_0; // @[tage.scala:240:33, :345:48]
tt_0_1_io_update_taken_0_REG <= s1_update_taken_0_0; // @[tage.scala:243:31, :346:48]
tt_0_1_io_update_alloc_0_REG <= s1_update_alloc_0_0; // @[tage.scala:245:31, :347:48]
tt_0_1_io_update_old_ctr_0_REG <= s1_update_old_ctr_0_0; // @[tage.scala:244:31, :348:48]
tt_0_1_io_update_u_mask_0_REG <= s1_update_u_mask_0_0; // @[tage.scala:241:35, :350:47]
tt_0_1_io_update_u_0_REG <= s1_update_u_0_0; // @[tage.scala:246:31, :351:47]
tt_0_1_io_update_mask_1_REG <= s1_update_mask_0_1; // @[tage.scala:240:33, :345:48]
tt_0_1_io_update_taken_1_REG <= s1_update_taken_0_1; // @[tage.scala:243:31, :346:48]
tt_0_1_io_update_alloc_1_REG <= s1_update_alloc_0_1; // @[tage.scala:245:31, :347:48]
tt_0_1_io_update_old_ctr_1_REG <= s1_update_old_ctr_0_1; // @[tage.scala:244:31, :348:48]
tt_0_1_io_update_u_mask_1_REG <= s1_update_u_mask_0_1; // @[tage.scala:241:35, :350:47]
tt_0_1_io_update_u_1_REG <= s1_update_u_0_1; // @[tage.scala:246:31, :351:47]
tt_0_1_io_update_mask_2_REG <= s1_update_mask_0_2; // @[tage.scala:240:33, :345:48]
tt_0_1_io_update_taken_2_REG <= s1_update_taken_0_2; // @[tage.scala:243:31, :346:48]
tt_0_1_io_update_alloc_2_REG <= s1_update_alloc_0_2; // @[tage.scala:245:31, :347:48]
tt_0_1_io_update_old_ctr_2_REG <= s1_update_old_ctr_0_2; // @[tage.scala:244:31, :348:48]
tt_0_1_io_update_u_mask_2_REG <= s1_update_u_mask_0_2; // @[tage.scala:241:35, :350:47]
tt_0_1_io_update_u_2_REG <= s1_update_u_0_2; // @[tage.scala:246:31, :351:47]
tt_0_1_io_update_mask_3_REG <= s1_update_mask_0_3; // @[tage.scala:240:33, :345:48]
tt_0_1_io_update_taken_3_REG <= s1_update_taken_0_3; // @[tage.scala:243:31, :346:48]
tt_0_1_io_update_alloc_3_REG <= s1_update_alloc_0_3; // @[tage.scala:245:31, :347:48]
tt_0_1_io_update_old_ctr_3_REG <= s1_update_old_ctr_0_3; // @[tage.scala:244:31, :348:48]
tt_0_1_io_update_u_mask_3_REG <= s1_update_u_mask_0_3; // @[tage.scala:241:35, :350:47]
tt_0_1_io_update_u_3_REG <= s1_update_u_0_3; // @[tage.scala:246:31, :351:47]
tt_0_1_io_update_pc_REG <= s1_update_bits_pc; // @[tage.scala:353:41]
tt_0_1_io_update_hist_REG <= s1_update_bits_ghist; // @[tage.scala:354:41]
tt_1_1_io_update_mask_0_REG <= s1_update_mask_1_0; // @[tage.scala:240:33, :345:48]
tt_1_1_io_update_taken_0_REG <= s1_update_taken_1_0; // @[tage.scala:243:31, :346:48]
tt_1_1_io_update_alloc_0_REG <= s1_update_alloc_1_0; // @[tage.scala:245:31, :347:48]
tt_1_1_io_update_old_ctr_0_REG <= s1_update_old_ctr_1_0; // @[tage.scala:244:31, :348:48]
tt_1_1_io_update_u_mask_0_REG <= s1_update_u_mask_1_0; // @[tage.scala:241:35, :350:47]
tt_1_1_io_update_u_0_REG <= s1_update_u_1_0; // @[tage.scala:246:31, :351:47]
tt_1_1_io_update_mask_1_REG <= s1_update_mask_1_1; // @[tage.scala:240:33, :345:48]
tt_1_1_io_update_taken_1_REG <= s1_update_taken_1_1; // @[tage.scala:243:31, :346:48]
tt_1_1_io_update_alloc_1_REG <= s1_update_alloc_1_1; // @[tage.scala:245:31, :347:48]
tt_1_1_io_update_old_ctr_1_REG <= s1_update_old_ctr_1_1; // @[tage.scala:244:31, :348:48]
tt_1_1_io_update_u_mask_1_REG <= s1_update_u_mask_1_1; // @[tage.scala:241:35, :350:47]
tt_1_1_io_update_u_1_REG <= s1_update_u_1_1; // @[tage.scala:246:31, :351:47]
tt_1_1_io_update_mask_2_REG <= s1_update_mask_1_2; // @[tage.scala:240:33, :345:48]
tt_1_1_io_update_taken_2_REG <= s1_update_taken_1_2; // @[tage.scala:243:31, :346:48]
tt_1_1_io_update_alloc_2_REG <= s1_update_alloc_1_2; // @[tage.scala:245:31, :347:48]
tt_1_1_io_update_old_ctr_2_REG <= s1_update_old_ctr_1_2; // @[tage.scala:244:31, :348:48]
tt_1_1_io_update_u_mask_2_REG <= s1_update_u_mask_1_2; // @[tage.scala:241:35, :350:47]
tt_1_1_io_update_u_2_REG <= s1_update_u_1_2; // @[tage.scala:246:31, :351:47]
tt_1_1_io_update_mask_3_REG <= s1_update_mask_1_3; // @[tage.scala:240:33, :345:48]
tt_1_1_io_update_taken_3_REG <= s1_update_taken_1_3; // @[tage.scala:243:31, :346:48]
tt_1_1_io_update_alloc_3_REG <= s1_update_alloc_1_3; // @[tage.scala:245:31, :347:48]
tt_1_1_io_update_old_ctr_3_REG <= s1_update_old_ctr_1_3; // @[tage.scala:244:31, :348:48]
tt_1_1_io_update_u_mask_3_REG <= s1_update_u_mask_1_3; // @[tage.scala:241:35, :350:47]
tt_1_1_io_update_u_3_REG <= s1_update_u_1_3; // @[tage.scala:246:31, :351:47]
tt_1_1_io_update_pc_REG <= s1_update_bits_pc; // @[tage.scala:353:41]
tt_1_1_io_update_hist_REG <= s1_update_bits_ghist; // @[tage.scala:354:41]
tt_2_1_io_update_mask_0_REG <= s1_update_mask_2_0; // @[tage.scala:240:33, :345:48]
tt_2_1_io_update_taken_0_REG <= s1_update_taken_2_0; // @[tage.scala:243:31, :346:48]
tt_2_1_io_update_alloc_0_REG <= s1_update_alloc_2_0; // @[tage.scala:245:31, :347:48]
tt_2_1_io_update_old_ctr_0_REG <= s1_update_old_ctr_2_0; // @[tage.scala:244:31, :348:48]
tt_2_1_io_update_u_mask_0_REG <= s1_update_u_mask_2_0; // @[tage.scala:241:35, :350:47]
tt_2_1_io_update_u_0_REG <= s1_update_u_2_0; // @[tage.scala:246:31, :351:47]
tt_2_1_io_update_mask_1_REG <= s1_update_mask_2_1; // @[tage.scala:240:33, :345:48]
tt_2_1_io_update_taken_1_REG <= s1_update_taken_2_1; // @[tage.scala:243:31, :346:48]
tt_2_1_io_update_alloc_1_REG <= s1_update_alloc_2_1; // @[tage.scala:245:31, :347:48]
tt_2_1_io_update_old_ctr_1_REG <= s1_update_old_ctr_2_1; // @[tage.scala:244:31, :348:48]
tt_2_1_io_update_u_mask_1_REG <= s1_update_u_mask_2_1; // @[tage.scala:241:35, :350:47]
tt_2_1_io_update_u_1_REG <= s1_update_u_2_1; // @[tage.scala:246:31, :351:47]
tt_2_1_io_update_mask_2_REG <= s1_update_mask_2_2; // @[tage.scala:240:33, :345:48]
tt_2_1_io_update_taken_2_REG <= s1_update_taken_2_2; // @[tage.scala:243:31, :346:48]
tt_2_1_io_update_alloc_2_REG <= s1_update_alloc_2_2; // @[tage.scala:245:31, :347:48]
tt_2_1_io_update_old_ctr_2_REG <= s1_update_old_ctr_2_2; // @[tage.scala:244:31, :348:48]
tt_2_1_io_update_u_mask_2_REG <= s1_update_u_mask_2_2; // @[tage.scala:241:35, :350:47]
tt_2_1_io_update_u_2_REG <= s1_update_u_2_2; // @[tage.scala:246:31, :351:47]
tt_2_1_io_update_mask_3_REG <= s1_update_mask_2_3; // @[tage.scala:240:33, :345:48]
tt_2_1_io_update_taken_3_REG <= s1_update_taken_2_3; // @[tage.scala:243:31, :346:48]
tt_2_1_io_update_alloc_3_REG <= s1_update_alloc_2_3; // @[tage.scala:245:31, :347:48]
tt_2_1_io_update_old_ctr_3_REG <= s1_update_old_ctr_2_3; // @[tage.scala:244:31, :348:48]
tt_2_1_io_update_u_mask_3_REG <= s1_update_u_mask_2_3; // @[tage.scala:241:35, :350:47]
tt_2_1_io_update_u_3_REG <= s1_update_u_2_3; // @[tage.scala:246:31, :351:47]
tt_2_1_io_update_pc_REG <= s1_update_bits_pc; // @[tage.scala:353:41]
tt_2_1_io_update_hist_REG <= s1_update_bits_ghist; // @[tage.scala:354:41]
tt_3_1_io_update_mask_0_REG <= s1_update_mask_3_0; // @[tage.scala:240:33, :345:48]
tt_3_1_io_update_taken_0_REG <= s1_update_taken_3_0; // @[tage.scala:243:31, :346:48]
tt_3_1_io_update_alloc_0_REG <= s1_update_alloc_3_0; // @[tage.scala:245:31, :347:48]
tt_3_1_io_update_old_ctr_0_REG <= s1_update_old_ctr_3_0; // @[tage.scala:244:31, :348:48]
tt_3_1_io_update_u_mask_0_REG <= s1_update_u_mask_3_0; // @[tage.scala:241:35, :350:47]
tt_3_1_io_update_u_0_REG <= s1_update_u_3_0; // @[tage.scala:246:31, :351:47]
tt_3_1_io_update_mask_1_REG <= s1_update_mask_3_1; // @[tage.scala:240:33, :345:48]
tt_3_1_io_update_taken_1_REG <= s1_update_taken_3_1; // @[tage.scala:243:31, :346:48]
tt_3_1_io_update_alloc_1_REG <= s1_update_alloc_3_1; // @[tage.scala:245:31, :347:48]
tt_3_1_io_update_old_ctr_1_REG <= s1_update_old_ctr_3_1; // @[tage.scala:244:31, :348:48]
tt_3_1_io_update_u_mask_1_REG <= s1_update_u_mask_3_1; // @[tage.scala:241:35, :350:47]
tt_3_1_io_update_u_1_REG <= s1_update_u_3_1; // @[tage.scala:246:31, :351:47]
tt_3_1_io_update_mask_2_REG <= s1_update_mask_3_2; // @[tage.scala:240:33, :345:48]
tt_3_1_io_update_taken_2_REG <= s1_update_taken_3_2; // @[tage.scala:243:31, :346:48]
tt_3_1_io_update_alloc_2_REG <= s1_update_alloc_3_2; // @[tage.scala:245:31, :347:48]
tt_3_1_io_update_old_ctr_2_REG <= s1_update_old_ctr_3_2; // @[tage.scala:244:31, :348:48]
tt_3_1_io_update_u_mask_2_REG <= s1_update_u_mask_3_2; // @[tage.scala:241:35, :350:47]
tt_3_1_io_update_u_2_REG <= s1_update_u_3_2; // @[tage.scala:246:31, :351:47]
tt_3_1_io_update_mask_3_REG <= s1_update_mask_3_3; // @[tage.scala:240:33, :345:48]
tt_3_1_io_update_taken_3_REG <= s1_update_taken_3_3; // @[tage.scala:243:31, :346:48]
tt_3_1_io_update_alloc_3_REG <= s1_update_alloc_3_3; // @[tage.scala:245:31, :347:48]
tt_3_1_io_update_old_ctr_3_REG <= s1_update_old_ctr_3_3; // @[tage.scala:244:31, :348:48]
tt_3_1_io_update_u_mask_3_REG <= s1_update_u_mask_3_3; // @[tage.scala:241:35, :350:47]
tt_3_1_io_update_u_3_REG <= s1_update_u_3_3; // @[tage.scala:246:31, :351:47]
tt_3_1_io_update_pc_REG <= s1_update_bits_pc; // @[tage.scala:353:41]
tt_3_1_io_update_hist_REG <= s1_update_bits_ghist; // @[tage.scala:354:41]
tt_4_1_io_update_mask_0_REG <= s1_update_mask_4_0; // @[tage.scala:240:33, :345:48]
tt_4_1_io_update_taken_0_REG <= s1_update_taken_4_0; // @[tage.scala:243:31, :346:48]
tt_4_1_io_update_alloc_0_REG <= s1_update_alloc_4_0; // @[tage.scala:245:31, :347:48]
tt_4_1_io_update_old_ctr_0_REG <= s1_update_old_ctr_4_0; // @[tage.scala:244:31, :348:48]
tt_4_1_io_update_u_mask_0_REG <= s1_update_u_mask_4_0; // @[tage.scala:241:35, :350:47]
tt_4_1_io_update_u_0_REG <= s1_update_u_4_0; // @[tage.scala:246:31, :351:47]
tt_4_1_io_update_mask_1_REG <= s1_update_mask_4_1; // @[tage.scala:240:33, :345:48]
tt_4_1_io_update_taken_1_REG <= s1_update_taken_4_1; // @[tage.scala:243:31, :346:48]
tt_4_1_io_update_alloc_1_REG <= s1_update_alloc_4_1; // @[tage.scala:245:31, :347:48]
tt_4_1_io_update_old_ctr_1_REG <= s1_update_old_ctr_4_1; // @[tage.scala:244:31, :348:48]
tt_4_1_io_update_u_mask_1_REG <= s1_update_u_mask_4_1; // @[tage.scala:241:35, :350:47]
tt_4_1_io_update_u_1_REG <= s1_update_u_4_1; // @[tage.scala:246:31, :351:47]
tt_4_1_io_update_mask_2_REG <= s1_update_mask_4_2; // @[tage.scala:240:33, :345:48]
tt_4_1_io_update_taken_2_REG <= s1_update_taken_4_2; // @[tage.scala:243:31, :346:48]
tt_4_1_io_update_alloc_2_REG <= s1_update_alloc_4_2; // @[tage.scala:245:31, :347:48]
tt_4_1_io_update_old_ctr_2_REG <= s1_update_old_ctr_4_2; // @[tage.scala:244:31, :348:48]
tt_4_1_io_update_u_mask_2_REG <= s1_update_u_mask_4_2; // @[tage.scala:241:35, :350:47]
tt_4_1_io_update_u_2_REG <= s1_update_u_4_2; // @[tage.scala:246:31, :351:47]
tt_4_1_io_update_mask_3_REG <= s1_update_mask_4_3; // @[tage.scala:240:33, :345:48]
tt_4_1_io_update_taken_3_REG <= s1_update_taken_4_3; // @[tage.scala:243:31, :346:48]
tt_4_1_io_update_alloc_3_REG <= s1_update_alloc_4_3; // @[tage.scala:245:31, :347:48]
tt_4_1_io_update_old_ctr_3_REG <= s1_update_old_ctr_4_3; // @[tage.scala:244:31, :348:48]
tt_4_1_io_update_u_mask_3_REG <= s1_update_u_mask_4_3; // @[tage.scala:241:35, :350:47]
tt_4_1_io_update_u_3_REG <= s1_update_u_4_3; // @[tage.scala:246:31, :351:47]
tt_4_1_io_update_pc_REG <= s1_update_bits_pc; // @[tage.scala:353:41]
tt_4_1_io_update_hist_REG <= s1_update_bits_ghist; // @[tage.scala:354:41]
tt_5_1_io_update_mask_0_REG <= s1_update_mask_5_0; // @[tage.scala:240:33, :345:48]
tt_5_1_io_update_taken_0_REG <= s1_update_taken_5_0; // @[tage.scala:243:31, :346:48]
tt_5_1_io_update_alloc_0_REG <= s1_update_alloc_5_0; // @[tage.scala:245:31, :347:48]
tt_5_1_io_update_old_ctr_0_REG <= s1_update_old_ctr_5_0; // @[tage.scala:244:31, :348:48]
tt_5_1_io_update_u_mask_0_REG <= s1_update_u_mask_5_0; // @[tage.scala:241:35, :350:47]
tt_5_1_io_update_u_0_REG <= s1_update_u_5_0; // @[tage.scala:246:31, :351:47]
tt_5_1_io_update_mask_1_REG <= s1_update_mask_5_1; // @[tage.scala:240:33, :345:48]
tt_5_1_io_update_taken_1_REG <= s1_update_taken_5_1; // @[tage.scala:243:31, :346:48]
tt_5_1_io_update_alloc_1_REG <= s1_update_alloc_5_1; // @[tage.scala:245:31, :347:48]
tt_5_1_io_update_old_ctr_1_REG <= s1_update_old_ctr_5_1; // @[tage.scala:244:31, :348:48]
tt_5_1_io_update_u_mask_1_REG <= s1_update_u_mask_5_1; // @[tage.scala:241:35, :350:47]
tt_5_1_io_update_u_1_REG <= s1_update_u_5_1; // @[tage.scala:246:31, :351:47]
tt_5_1_io_update_mask_2_REG <= s1_update_mask_5_2; // @[tage.scala:240:33, :345:48]
tt_5_1_io_update_taken_2_REG <= s1_update_taken_5_2; // @[tage.scala:243:31, :346:48]
tt_5_1_io_update_alloc_2_REG <= s1_update_alloc_5_2; // @[tage.scala:245:31, :347:48]
tt_5_1_io_update_old_ctr_2_REG <= s1_update_old_ctr_5_2; // @[tage.scala:244:31, :348:48]
tt_5_1_io_update_u_mask_2_REG <= s1_update_u_mask_5_2; // @[tage.scala:241:35, :350:47]
tt_5_1_io_update_u_2_REG <= s1_update_u_5_2; // @[tage.scala:246:31, :351:47]
tt_5_1_io_update_mask_3_REG <= s1_update_mask_5_3; // @[tage.scala:240:33, :345:48]
tt_5_1_io_update_taken_3_REG <= s1_update_taken_5_3; // @[tage.scala:243:31, :346:48]
tt_5_1_io_update_alloc_3_REG <= s1_update_alloc_5_3; // @[tage.scala:245:31, :347:48]
tt_5_1_io_update_old_ctr_3_REG <= s1_update_old_ctr_5_3; // @[tage.scala:244:31, :348:48]
tt_5_1_io_update_u_mask_3_REG <= s1_update_u_mask_5_3; // @[tage.scala:241:35, :350:47]
tt_5_1_io_update_u_3_REG <= s1_update_u_5_3; // @[tage.scala:246:31, :351:47]
tt_5_1_io_update_pc_REG <= s1_update_bits_pc; // @[tage.scala:353:41]
tt_5_1_io_update_hist_REG <= s1_update_bits_ghist; // @[tage.scala:354:41]
always @(posedge)
TageTable_6 tt_0_1 ( // @[tage.scala:224:21]
.clock (clock),
.reset (reset),
.io_f1_req_valid (t_io_f1_req_valid_REG), // @[tage.scala:225:35]
.io_f1_req_pc (t_io_f1_req_pc_REG), // @[tage.scala:226:35]
.io_f1_req_ghist (io_f1_ghist_0), // @[tage.scala:198:7]
.io_f3_resp_0_valid (f3_resps_0_0_valid),
.io_f3_resp_0_bits_ctr (f3_resps_0_0_bits_ctr),
.io_f3_resp_0_bits_u (f3_resps_0_0_bits_u),
.io_f3_resp_1_valid (f3_resps_0_1_valid),
.io_f3_resp_1_bits_ctr (f3_resps_0_1_bits_ctr),
.io_f3_resp_1_bits_u (f3_resps_0_1_bits_u),
.io_f3_resp_2_valid (f3_resps_0_2_valid),
.io_f3_resp_2_bits_ctr (f3_resps_0_2_bits_ctr),
.io_f3_resp_2_bits_u (f3_resps_0_2_bits_u),
.io_f3_resp_3_valid (f3_resps_0_3_valid),
.io_f3_resp_3_bits_ctr (f3_resps_0_3_bits_ctr),
.io_f3_resp_3_bits_u (f3_resps_0_3_bits_u),
.io_update_mask_0 (tt_0_1_io_update_mask_0_REG), // @[tage.scala:345:48]
.io_update_mask_1 (tt_0_1_io_update_mask_1_REG), // @[tage.scala:345:48]
.io_update_mask_2 (tt_0_1_io_update_mask_2_REG), // @[tage.scala:345:48]
.io_update_mask_3 (tt_0_1_io_update_mask_3_REG), // @[tage.scala:345:48]
.io_update_taken_0 (tt_0_1_io_update_taken_0_REG), // @[tage.scala:346:48]
.io_update_taken_1 (tt_0_1_io_update_taken_1_REG), // @[tage.scala:346:48]
.io_update_taken_2 (tt_0_1_io_update_taken_2_REG), // @[tage.scala:346:48]
.io_update_taken_3 (tt_0_1_io_update_taken_3_REG), // @[tage.scala:346:48]
.io_update_alloc_0 (tt_0_1_io_update_alloc_0_REG), // @[tage.scala:347:48]
.io_update_alloc_1 (tt_0_1_io_update_alloc_1_REG), // @[tage.scala:347:48]
.io_update_alloc_2 (tt_0_1_io_update_alloc_2_REG), // @[tage.scala:347:48]
.io_update_alloc_3 (tt_0_1_io_update_alloc_3_REG), // @[tage.scala:347:48]
.io_update_old_ctr_0 (tt_0_1_io_update_old_ctr_0_REG), // @[tage.scala:348:48]
.io_update_old_ctr_1 (tt_0_1_io_update_old_ctr_1_REG), // @[tage.scala:348:48]
.io_update_old_ctr_2 (tt_0_1_io_update_old_ctr_2_REG), // @[tage.scala:348:48]
.io_update_old_ctr_3 (tt_0_1_io_update_old_ctr_3_REG), // @[tage.scala:348:48]
.io_update_pc (tt_0_1_io_update_pc_REG), // @[tage.scala:353:41]
.io_update_hist (tt_0_1_io_update_hist_REG), // @[tage.scala:354:41]
.io_update_u_mask_0 (tt_0_1_io_update_u_mask_0_REG), // @[tage.scala:350:47]
.io_update_u_mask_1 (tt_0_1_io_update_u_mask_1_REG), // @[tage.scala:350:47]
.io_update_u_mask_2 (tt_0_1_io_update_u_mask_2_REG), // @[tage.scala:350:47]
.io_update_u_mask_3 (tt_0_1_io_update_u_mask_3_REG), // @[tage.scala:350:47]
.io_update_u_0 (tt_0_1_io_update_u_0_REG), // @[tage.scala:351:47]
.io_update_u_1 (tt_0_1_io_update_u_1_REG), // @[tage.scala:351:47]
.io_update_u_2 (tt_0_1_io_update_u_2_REG), // @[tage.scala:351:47]
.io_update_u_3 (tt_0_1_io_update_u_3_REG) // @[tage.scala:351:47]
); // @[tage.scala:224:21]
TageTable_7 tt_1_1 ( // @[tage.scala:224:21]
.clock (clock),
.reset (reset),
.io_f1_req_valid (t_io_f1_req_valid_REG_1), // @[tage.scala:225:35]
.io_f1_req_pc (t_io_f1_req_pc_REG_1), // @[tage.scala:226:35]
.io_f1_req_ghist (io_f1_ghist_0), // @[tage.scala:198:7]
.io_f3_resp_0_valid (f3_resps_1_0_valid),
.io_f3_resp_0_bits_ctr (f3_resps_1_0_bits_ctr),
.io_f3_resp_0_bits_u (f3_resps_1_0_bits_u),
.io_f3_resp_1_valid (f3_resps_1_1_valid),
.io_f3_resp_1_bits_ctr (f3_resps_1_1_bits_ctr),
.io_f3_resp_1_bits_u (f3_resps_1_1_bits_u),
.io_f3_resp_2_valid (f3_resps_1_2_valid),
.io_f3_resp_2_bits_ctr (f3_resps_1_2_bits_ctr),
.io_f3_resp_2_bits_u (f3_resps_1_2_bits_u),
.io_f3_resp_3_valid (f3_resps_1_3_valid),
.io_f3_resp_3_bits_ctr (f3_resps_1_3_bits_ctr),
.io_f3_resp_3_bits_u (f3_resps_1_3_bits_u),
.io_update_mask_0 (tt_1_1_io_update_mask_0_REG), // @[tage.scala:345:48]
.io_update_mask_1 (tt_1_1_io_update_mask_1_REG), // @[tage.scala:345:48]
.io_update_mask_2 (tt_1_1_io_update_mask_2_REG), // @[tage.scala:345:48]
.io_update_mask_3 (tt_1_1_io_update_mask_3_REG), // @[tage.scala:345:48]
.io_update_taken_0 (tt_1_1_io_update_taken_0_REG), // @[tage.scala:346:48]
.io_update_taken_1 (tt_1_1_io_update_taken_1_REG), // @[tage.scala:346:48]
.io_update_taken_2 (tt_1_1_io_update_taken_2_REG), // @[tage.scala:346:48]
.io_update_taken_3 (tt_1_1_io_update_taken_3_REG), // @[tage.scala:346:48]
.io_update_alloc_0 (tt_1_1_io_update_alloc_0_REG), // @[tage.scala:347:48]
.io_update_alloc_1 (tt_1_1_io_update_alloc_1_REG), // @[tage.scala:347:48]
.io_update_alloc_2 (tt_1_1_io_update_alloc_2_REG), // @[tage.scala:347:48]
.io_update_alloc_3 (tt_1_1_io_update_alloc_3_REG), // @[tage.scala:347:48]
.io_update_old_ctr_0 (tt_1_1_io_update_old_ctr_0_REG), // @[tage.scala:348:48]
.io_update_old_ctr_1 (tt_1_1_io_update_old_ctr_1_REG), // @[tage.scala:348:48]
.io_update_old_ctr_2 (tt_1_1_io_update_old_ctr_2_REG), // @[tage.scala:348:48]
.io_update_old_ctr_3 (tt_1_1_io_update_old_ctr_3_REG), // @[tage.scala:348:48]
.io_update_pc (tt_1_1_io_update_pc_REG), // @[tage.scala:353:41]
.io_update_hist (tt_1_1_io_update_hist_REG), // @[tage.scala:354:41]
.io_update_u_mask_0 (tt_1_1_io_update_u_mask_0_REG), // @[tage.scala:350:47]
.io_update_u_mask_1 (tt_1_1_io_update_u_mask_1_REG), // @[tage.scala:350:47]
.io_update_u_mask_2 (tt_1_1_io_update_u_mask_2_REG), // @[tage.scala:350:47]
.io_update_u_mask_3 (tt_1_1_io_update_u_mask_3_REG), // @[tage.scala:350:47]
.io_update_u_0 (tt_1_1_io_update_u_0_REG), // @[tage.scala:351:47]
.io_update_u_1 (tt_1_1_io_update_u_1_REG), // @[tage.scala:351:47]
.io_update_u_2 (tt_1_1_io_update_u_2_REG), // @[tage.scala:351:47]
.io_update_u_3 (tt_1_1_io_update_u_3_REG) // @[tage.scala:351:47]
); // @[tage.scala:224:21]
TageTable_8 tt_2_1 ( // @[tage.scala:224:21]
.clock (clock),
.reset (reset),
.io_f1_req_valid (t_io_f1_req_valid_REG_2), // @[tage.scala:225:35]
.io_f1_req_pc (t_io_f1_req_pc_REG_2), // @[tage.scala:226:35]
.io_f1_req_ghist (io_f1_ghist_0), // @[tage.scala:198:7]
.io_f3_resp_0_valid (f3_resps_2_0_valid),
.io_f3_resp_0_bits_ctr (f3_resps_2_0_bits_ctr),
.io_f3_resp_0_bits_u (f3_resps_2_0_bits_u),
.io_f3_resp_1_valid (f3_resps_2_1_valid),
.io_f3_resp_1_bits_ctr (f3_resps_2_1_bits_ctr),
.io_f3_resp_1_bits_u (f3_resps_2_1_bits_u),
.io_f3_resp_2_valid (f3_resps_2_2_valid),
.io_f3_resp_2_bits_ctr (f3_resps_2_2_bits_ctr),
.io_f3_resp_2_bits_u (f3_resps_2_2_bits_u),
.io_f3_resp_3_valid (f3_resps_2_3_valid),
.io_f3_resp_3_bits_ctr (f3_resps_2_3_bits_ctr),
.io_f3_resp_3_bits_u (f3_resps_2_3_bits_u),
.io_update_mask_0 (tt_2_1_io_update_mask_0_REG), // @[tage.scala:345:48]
.io_update_mask_1 (tt_2_1_io_update_mask_1_REG), // @[tage.scala:345:48]
.io_update_mask_2 (tt_2_1_io_update_mask_2_REG), // @[tage.scala:345:48]
.io_update_mask_3 (tt_2_1_io_update_mask_3_REG), // @[tage.scala:345:48]
.io_update_taken_0 (tt_2_1_io_update_taken_0_REG), // @[tage.scala:346:48]
.io_update_taken_1 (tt_2_1_io_update_taken_1_REG), // @[tage.scala:346:48]
.io_update_taken_2 (tt_2_1_io_update_taken_2_REG), // @[tage.scala:346:48]
.io_update_taken_3 (tt_2_1_io_update_taken_3_REG), // @[tage.scala:346:48]
.io_update_alloc_0 (tt_2_1_io_update_alloc_0_REG), // @[tage.scala:347:48]
.io_update_alloc_1 (tt_2_1_io_update_alloc_1_REG), // @[tage.scala:347:48]
.io_update_alloc_2 (tt_2_1_io_update_alloc_2_REG), // @[tage.scala:347:48]
.io_update_alloc_3 (tt_2_1_io_update_alloc_3_REG), // @[tage.scala:347:48]
.io_update_old_ctr_0 (tt_2_1_io_update_old_ctr_0_REG), // @[tage.scala:348:48]
.io_update_old_ctr_1 (tt_2_1_io_update_old_ctr_1_REG), // @[tage.scala:348:48]
.io_update_old_ctr_2 (tt_2_1_io_update_old_ctr_2_REG), // @[tage.scala:348:48]
.io_update_old_ctr_3 (tt_2_1_io_update_old_ctr_3_REG), // @[tage.scala:348:48]
.io_update_pc (tt_2_1_io_update_pc_REG), // @[tage.scala:353:41]
.io_update_hist (tt_2_1_io_update_hist_REG), // @[tage.scala:354:41]
.io_update_u_mask_0 (tt_2_1_io_update_u_mask_0_REG), // @[tage.scala:350:47]
.io_update_u_mask_1 (tt_2_1_io_update_u_mask_1_REG), // @[tage.scala:350:47]
.io_update_u_mask_2 (tt_2_1_io_update_u_mask_2_REG), // @[tage.scala:350:47]
.io_update_u_mask_3 (tt_2_1_io_update_u_mask_3_REG), // @[tage.scala:350:47]
.io_update_u_0 (tt_2_1_io_update_u_0_REG), // @[tage.scala:351:47]
.io_update_u_1 (tt_2_1_io_update_u_1_REG), // @[tage.scala:351:47]
.io_update_u_2 (tt_2_1_io_update_u_2_REG), // @[tage.scala:351:47]
.io_update_u_3 (tt_2_1_io_update_u_3_REG) // @[tage.scala:351:47]
); // @[tage.scala:224:21]
TageTable_9 tt_3_1 ( // @[tage.scala:224:21]
.clock (clock),
.reset (reset),
.io_f1_req_valid (t_io_f1_req_valid_REG_3), // @[tage.scala:225:35]
.io_f1_req_pc (t_io_f1_req_pc_REG_3), // @[tage.scala:226:35]
.io_f1_req_ghist (io_f1_ghist_0), // @[tage.scala:198:7]
.io_f3_resp_0_valid (f3_resps_3_0_valid),
.io_f3_resp_0_bits_ctr (f3_resps_3_0_bits_ctr),
.io_f3_resp_0_bits_u (f3_resps_3_0_bits_u),
.io_f3_resp_1_valid (f3_resps_3_1_valid),
.io_f3_resp_1_bits_ctr (f3_resps_3_1_bits_ctr),
.io_f3_resp_1_bits_u (f3_resps_3_1_bits_u),
.io_f3_resp_2_valid (f3_resps_3_2_valid),
.io_f3_resp_2_bits_ctr (f3_resps_3_2_bits_ctr),
.io_f3_resp_2_bits_u (f3_resps_3_2_bits_u),
.io_f3_resp_3_valid (f3_resps_3_3_valid),
.io_f3_resp_3_bits_ctr (f3_resps_3_3_bits_ctr),
.io_f3_resp_3_bits_u (f3_resps_3_3_bits_u),
.io_update_mask_0 (tt_3_1_io_update_mask_0_REG), // @[tage.scala:345:48]
.io_update_mask_1 (tt_3_1_io_update_mask_1_REG), // @[tage.scala:345:48]
.io_update_mask_2 (tt_3_1_io_update_mask_2_REG), // @[tage.scala:345:48]
.io_update_mask_3 (tt_3_1_io_update_mask_3_REG), // @[tage.scala:345:48]
.io_update_taken_0 (tt_3_1_io_update_taken_0_REG), // @[tage.scala:346:48]
.io_update_taken_1 (tt_3_1_io_update_taken_1_REG), // @[tage.scala:346:48]
.io_update_taken_2 (tt_3_1_io_update_taken_2_REG), // @[tage.scala:346:48]
.io_update_taken_3 (tt_3_1_io_update_taken_3_REG), // @[tage.scala:346:48]
.io_update_alloc_0 (tt_3_1_io_update_alloc_0_REG), // @[tage.scala:347:48]
.io_update_alloc_1 (tt_3_1_io_update_alloc_1_REG), // @[tage.scala:347:48]
.io_update_alloc_2 (tt_3_1_io_update_alloc_2_REG), // @[tage.scala:347:48]
.io_update_alloc_3 (tt_3_1_io_update_alloc_3_REG), // @[tage.scala:347:48]
.io_update_old_ctr_0 (tt_3_1_io_update_old_ctr_0_REG), // @[tage.scala:348:48]
.io_update_old_ctr_1 (tt_3_1_io_update_old_ctr_1_REG), // @[tage.scala:348:48]
.io_update_old_ctr_2 (tt_3_1_io_update_old_ctr_2_REG), // @[tage.scala:348:48]
.io_update_old_ctr_3 (tt_3_1_io_update_old_ctr_3_REG), // @[tage.scala:348:48]
.io_update_pc (tt_3_1_io_update_pc_REG), // @[tage.scala:353:41]
.io_update_hist (tt_3_1_io_update_hist_REG), // @[tage.scala:354:41]
.io_update_u_mask_0 (tt_3_1_io_update_u_mask_0_REG), // @[tage.scala:350:47]
.io_update_u_mask_1 (tt_3_1_io_update_u_mask_1_REG), // @[tage.scala:350:47]
.io_update_u_mask_2 (tt_3_1_io_update_u_mask_2_REG), // @[tage.scala:350:47]
.io_update_u_mask_3 (tt_3_1_io_update_u_mask_3_REG), // @[tage.scala:350:47]
.io_update_u_0 (tt_3_1_io_update_u_0_REG), // @[tage.scala:351:47]
.io_update_u_1 (tt_3_1_io_update_u_1_REG), // @[tage.scala:351:47]
.io_update_u_2 (tt_3_1_io_update_u_2_REG), // @[tage.scala:351:47]
.io_update_u_3 (tt_3_1_io_update_u_3_REG) // @[tage.scala:351:47]
); // @[tage.scala:224:21]
TageTable_10 tt_4_1 ( // @[tage.scala:224:21]
.clock (clock),
.reset (reset),
.io_f1_req_valid (t_io_f1_req_valid_REG_4), // @[tage.scala:225:35]
.io_f1_req_pc (t_io_f1_req_pc_REG_4), // @[tage.scala:226:35]
.io_f1_req_ghist (io_f1_ghist_0), // @[tage.scala:198:7]
.io_f3_resp_0_valid (f3_resps_4_0_valid),
.io_f3_resp_0_bits_ctr (f3_resps_4_0_bits_ctr),
.io_f3_resp_0_bits_u (f3_resps_4_0_bits_u),
.io_f3_resp_1_valid (f3_resps_4_1_valid),
.io_f3_resp_1_bits_ctr (f3_resps_4_1_bits_ctr),
.io_f3_resp_1_bits_u (f3_resps_4_1_bits_u),
.io_f3_resp_2_valid (f3_resps_4_2_valid),
.io_f3_resp_2_bits_ctr (f3_resps_4_2_bits_ctr),
.io_f3_resp_2_bits_u (f3_resps_4_2_bits_u),
.io_f3_resp_3_valid (f3_resps_4_3_valid),
.io_f3_resp_3_bits_ctr (f3_resps_4_3_bits_ctr),
.io_f3_resp_3_bits_u (f3_resps_4_3_bits_u),
.io_update_mask_0 (tt_4_1_io_update_mask_0_REG), // @[tage.scala:345:48]
.io_update_mask_1 (tt_4_1_io_update_mask_1_REG), // @[tage.scala:345:48]
.io_update_mask_2 (tt_4_1_io_update_mask_2_REG), // @[tage.scala:345:48]
.io_update_mask_3 (tt_4_1_io_update_mask_3_REG), // @[tage.scala:345:48]
.io_update_taken_0 (tt_4_1_io_update_taken_0_REG), // @[tage.scala:346:48]
.io_update_taken_1 (tt_4_1_io_update_taken_1_REG), // @[tage.scala:346:48]
.io_update_taken_2 (tt_4_1_io_update_taken_2_REG), // @[tage.scala:346:48]
.io_update_taken_3 (tt_4_1_io_update_taken_3_REG), // @[tage.scala:346:48]
.io_update_alloc_0 (tt_4_1_io_update_alloc_0_REG), // @[tage.scala:347:48]
.io_update_alloc_1 (tt_4_1_io_update_alloc_1_REG), // @[tage.scala:347:48]
.io_update_alloc_2 (tt_4_1_io_update_alloc_2_REG), // @[tage.scala:347:48]
.io_update_alloc_3 (tt_4_1_io_update_alloc_3_REG), // @[tage.scala:347:48]
.io_update_old_ctr_0 (tt_4_1_io_update_old_ctr_0_REG), // @[tage.scala:348:48]
.io_update_old_ctr_1 (tt_4_1_io_update_old_ctr_1_REG), // @[tage.scala:348:48]
.io_update_old_ctr_2 (tt_4_1_io_update_old_ctr_2_REG), // @[tage.scala:348:48]
.io_update_old_ctr_3 (tt_4_1_io_update_old_ctr_3_REG), // @[tage.scala:348:48]
.io_update_pc (tt_4_1_io_update_pc_REG), // @[tage.scala:353:41]
.io_update_hist (tt_4_1_io_update_hist_REG), // @[tage.scala:354:41]
.io_update_u_mask_0 (tt_4_1_io_update_u_mask_0_REG), // @[tage.scala:350:47]
.io_update_u_mask_1 (tt_4_1_io_update_u_mask_1_REG), // @[tage.scala:350:47]
.io_update_u_mask_2 (tt_4_1_io_update_u_mask_2_REG), // @[tage.scala:350:47]
.io_update_u_mask_3 (tt_4_1_io_update_u_mask_3_REG), // @[tage.scala:350:47]
.io_update_u_0 (tt_4_1_io_update_u_0_REG), // @[tage.scala:351:47]
.io_update_u_1 (tt_4_1_io_update_u_1_REG), // @[tage.scala:351:47]
.io_update_u_2 (tt_4_1_io_update_u_2_REG), // @[tage.scala:351:47]
.io_update_u_3 (tt_4_1_io_update_u_3_REG) // @[tage.scala:351:47]
); // @[tage.scala:224:21]
TageTable_11 tt_5_1 ( // @[tage.scala:224:21]
.clock (clock),
.reset (reset),
.io_f1_req_valid (t_io_f1_req_valid_REG_5), // @[tage.scala:225:35]
.io_f1_req_pc (t_io_f1_req_pc_REG_5), // @[tage.scala:226:35]
.io_f1_req_ghist (io_f1_ghist_0), // @[tage.scala:198:7]
.io_f3_resp_0_valid (f3_resps_5_0_valid),
.io_f3_resp_0_bits_ctr (f3_resps_5_0_bits_ctr),
.io_f3_resp_0_bits_u (f3_resps_5_0_bits_u),
.io_f3_resp_1_valid (f3_resps_5_1_valid),
.io_f3_resp_1_bits_ctr (f3_resps_5_1_bits_ctr),
.io_f3_resp_1_bits_u (f3_resps_5_1_bits_u),
.io_f3_resp_2_valid (f3_resps_5_2_valid),
.io_f3_resp_2_bits_ctr (f3_resps_5_2_bits_ctr),
.io_f3_resp_2_bits_u (f3_resps_5_2_bits_u),
.io_f3_resp_3_valid (f3_resps_5_3_valid),
.io_f3_resp_3_bits_ctr (f3_resps_5_3_bits_ctr),
.io_f3_resp_3_bits_u (f3_resps_5_3_bits_u),
.io_update_mask_0 (tt_5_1_io_update_mask_0_REG), // @[tage.scala:345:48]
.io_update_mask_1 (tt_5_1_io_update_mask_1_REG), // @[tage.scala:345:48]
.io_update_mask_2 (tt_5_1_io_update_mask_2_REG), // @[tage.scala:345:48]
.io_update_mask_3 (tt_5_1_io_update_mask_3_REG), // @[tage.scala:345:48]
.io_update_taken_0 (tt_5_1_io_update_taken_0_REG), // @[tage.scala:346:48]
.io_update_taken_1 (tt_5_1_io_update_taken_1_REG), // @[tage.scala:346:48]
.io_update_taken_2 (tt_5_1_io_update_taken_2_REG), // @[tage.scala:346:48]
.io_update_taken_3 (tt_5_1_io_update_taken_3_REG), // @[tage.scala:346:48]
.io_update_alloc_0 (tt_5_1_io_update_alloc_0_REG), // @[tage.scala:347:48]
.io_update_alloc_1 (tt_5_1_io_update_alloc_1_REG), // @[tage.scala:347:48]
.io_update_alloc_2 (tt_5_1_io_update_alloc_2_REG), // @[tage.scala:347:48]
.io_update_alloc_3 (tt_5_1_io_update_alloc_3_REG), // @[tage.scala:347:48]
.io_update_old_ctr_0 (tt_5_1_io_update_old_ctr_0_REG), // @[tage.scala:348:48]
.io_update_old_ctr_1 (tt_5_1_io_update_old_ctr_1_REG), // @[tage.scala:348:48]
.io_update_old_ctr_2 (tt_5_1_io_update_old_ctr_2_REG), // @[tage.scala:348:48]
.io_update_old_ctr_3 (tt_5_1_io_update_old_ctr_3_REG), // @[tage.scala:348:48]
.io_update_pc (tt_5_1_io_update_pc_REG), // @[tage.scala:353:41]
.io_update_hist (tt_5_1_io_update_hist_REG), // @[tage.scala:354:41]
.io_update_u_mask_0 (tt_5_1_io_update_u_mask_0_REG), // @[tage.scala:350:47]
.io_update_u_mask_1 (tt_5_1_io_update_u_mask_1_REG), // @[tage.scala:350:47]
.io_update_u_mask_2 (tt_5_1_io_update_u_mask_2_REG), // @[tage.scala:350:47]
.io_update_u_mask_3 (tt_5_1_io_update_u_mask_3_REG), // @[tage.scala:350:47]
.io_update_u_0 (tt_5_1_io_update_u_0_REG), // @[tage.scala:351:47]
.io_update_u_1 (tt_5_1_io_update_u_1_REG), // @[tage.scala:351:47]
.io_update_u_2 (tt_5_1_io_update_u_2_REG), // @[tage.scala:351:47]
.io_update_u_3 (tt_5_1_io_update_u_3_REG) // @[tage.scala:351:47]
); // @[tage.scala:224:21]
MaxPeriodFibonacciLFSR_11 alloc_lfsr_prng ( // @[PRNG.scala:91:22]
.clock (clock),
.reset (reset),
.io_out_0 (_alloc_lfsr_prng_io_out_0),
.io_out_1 (_alloc_lfsr_prng_io_out_1),
.io_out_2 (_alloc_lfsr_prng_io_out_2),
.io_out_3 (_alloc_lfsr_prng_io_out_3),
.io_out_4 (_alloc_lfsr_prng_io_out_4),
.io_out_5 (_alloc_lfsr_prng_io_out_5)
); // @[PRNG.scala:91:22]
MaxPeriodFibonacciLFSR_12 alloc_lfsr_prng_1 ( // @[PRNG.scala:91:22]
.clock (clock),
.reset (reset),
.io_out_0 (_alloc_lfsr_prng_1_io_out_0),
.io_out_1 (_alloc_lfsr_prng_1_io_out_1),
.io_out_2 (_alloc_lfsr_prng_1_io_out_2),
.io_out_3 (_alloc_lfsr_prng_1_io_out_3),
.io_out_4 (_alloc_lfsr_prng_1_io_out_4),
.io_out_5 (_alloc_lfsr_prng_1_io_out_5)
); // @[PRNG.scala:91:22]
MaxPeriodFibonacciLFSR_13 alloc_lfsr_prng_2 ( // @[PRNG.scala:91:22]
.clock (clock),
.reset (reset),
.io_out_0 (_alloc_lfsr_prng_2_io_out_0),
.io_out_1 (_alloc_lfsr_prng_2_io_out_1),
.io_out_2 (_alloc_lfsr_prng_2_io_out_2),
.io_out_3 (_alloc_lfsr_prng_2_io_out_3),
.io_out_4 (_alloc_lfsr_prng_2_io_out_4),
.io_out_5 (_alloc_lfsr_prng_2_io_out_5)
); // @[PRNG.scala:91:22]
MaxPeriodFibonacciLFSR_14 alloc_lfsr_prng_3 ( // @[PRNG.scala:91:22]
.clock (clock),
.reset (reset),
.io_out_0 (_alloc_lfsr_prng_3_io_out_0),
.io_out_1 (_alloc_lfsr_prng_3_io_out_1),
.io_out_2 (_alloc_lfsr_prng_3_io_out_2),
.io_out_3 (_alloc_lfsr_prng_3_io_out_3),
.io_out_4 (_alloc_lfsr_prng_3_io_out_4),
.io_out_5 (_alloc_lfsr_prng_3_io_out_5)
); // @[PRNG.scala:91:22]
assign io_resp_f1_0_taken = io_resp_f1_0_taken_0; // @[tage.scala:198:7]
assign io_resp_f1_0_is_br = io_resp_f1_0_is_br_0; // @[tage.scala:198:7]
assign io_resp_f1_0_is_jal = io_resp_f1_0_is_jal_0; // @[tage.scala:198:7]
assign io_resp_f1_0_predicted_pc_valid = io_resp_f1_0_predicted_pc_valid_0; // @[tage.scala:198:7]
assign io_resp_f1_0_predicted_pc_bits = io_resp_f1_0_predicted_pc_bits_0; // @[tage.scala:198:7]
assign io_resp_f1_1_taken = io_resp_f1_1_taken_0; // @[tage.scala:198:7]
assign io_resp_f1_1_is_br = io_resp_f1_1_is_br_0; // @[tage.scala:198:7]
assign io_resp_f1_1_is_jal = io_resp_f1_1_is_jal_0; // @[tage.scala:198:7]
assign io_resp_f1_1_predicted_pc_valid = io_resp_f1_1_predicted_pc_valid_0; // @[tage.scala:198:7]
assign io_resp_f1_1_predicted_pc_bits = io_resp_f1_1_predicted_pc_bits_0; // @[tage.scala:198:7]
assign io_resp_f1_2_taken = io_resp_f1_2_taken_0; // @[tage.scala:198:7]
assign io_resp_f1_2_is_br = io_resp_f1_2_is_br_0; // @[tage.scala:198:7]
assign io_resp_f1_2_is_jal = io_resp_f1_2_is_jal_0; // @[tage.scala:198:7]
assign io_resp_f1_2_predicted_pc_valid = io_resp_f1_2_predicted_pc_valid_0; // @[tage.scala:198:7]
assign io_resp_f1_2_predicted_pc_bits = io_resp_f1_2_predicted_pc_bits_0; // @[tage.scala:198:7]
assign io_resp_f1_3_taken = io_resp_f1_3_taken_0; // @[tage.scala:198:7]
assign io_resp_f1_3_is_br = io_resp_f1_3_is_br_0; // @[tage.scala:198:7]
assign io_resp_f1_3_is_jal = io_resp_f1_3_is_jal_0; // @[tage.scala:198:7]
assign io_resp_f1_3_predicted_pc_valid = io_resp_f1_3_predicted_pc_valid_0; // @[tage.scala:198:7]
assign io_resp_f1_3_predicted_pc_bits = io_resp_f1_3_predicted_pc_bits_0; // @[tage.scala:198:7]
assign io_resp_f2_0_taken = io_resp_f2_0_taken_0; // @[tage.scala:198:7]
assign io_resp_f2_0_is_br = io_resp_f2_0_is_br_0; // @[tage.scala:198:7]
assign io_resp_f2_0_is_jal = io_resp_f2_0_is_jal_0; // @[tage.scala:198:7]
assign io_resp_f2_0_predicted_pc_valid = io_resp_f2_0_predicted_pc_valid_0; // @[tage.scala:198:7]
assign io_resp_f2_0_predicted_pc_bits = io_resp_f2_0_predicted_pc_bits_0; // @[tage.scala:198:7]
assign io_resp_f2_1_taken = io_resp_f2_1_taken_0; // @[tage.scala:198:7]
assign io_resp_f2_1_is_br = io_resp_f2_1_is_br_0; // @[tage.scala:198:7]
assign io_resp_f2_1_is_jal = io_resp_f2_1_is_jal_0; // @[tage.scala:198:7]
assign io_resp_f2_1_predicted_pc_valid = io_resp_f2_1_predicted_pc_valid_0; // @[tage.scala:198:7]
assign io_resp_f2_1_predicted_pc_bits = io_resp_f2_1_predicted_pc_bits_0; // @[tage.scala:198:7]
assign io_resp_f2_2_taken = io_resp_f2_2_taken_0; // @[tage.scala:198:7]
assign io_resp_f2_2_is_br = io_resp_f2_2_is_br_0; // @[tage.scala:198:7]
assign io_resp_f2_2_is_jal = io_resp_f2_2_is_jal_0; // @[tage.scala:198:7]
assign io_resp_f2_2_predicted_pc_valid = io_resp_f2_2_predicted_pc_valid_0; // @[tage.scala:198:7]
assign io_resp_f2_2_predicted_pc_bits = io_resp_f2_2_predicted_pc_bits_0; // @[tage.scala:198:7]
assign io_resp_f2_3_taken = io_resp_f2_3_taken_0; // @[tage.scala:198:7]
assign io_resp_f2_3_is_br = io_resp_f2_3_is_br_0; // @[tage.scala:198:7]
assign io_resp_f2_3_is_jal = io_resp_f2_3_is_jal_0; // @[tage.scala:198:7]
assign io_resp_f2_3_predicted_pc_valid = io_resp_f2_3_predicted_pc_valid_0; // @[tage.scala:198:7]
assign io_resp_f2_3_predicted_pc_bits = io_resp_f2_3_predicted_pc_bits_0; // @[tage.scala:198:7]
assign io_resp_f3_0_taken = io_resp_f3_0_taken_0; // @[tage.scala:198:7]
assign io_resp_f3_0_is_br = io_resp_f3_0_is_br_0; // @[tage.scala:198:7]
assign io_resp_f3_0_is_jal = io_resp_f3_0_is_jal_0; // @[tage.scala:198:7]
assign io_resp_f3_0_predicted_pc_valid = io_resp_f3_0_predicted_pc_valid_0; // @[tage.scala:198:7]
assign io_resp_f3_0_predicted_pc_bits = io_resp_f3_0_predicted_pc_bits_0; // @[tage.scala:198:7]
assign io_resp_f3_1_taken = io_resp_f3_1_taken_0; // @[tage.scala:198:7]
assign io_resp_f3_1_is_br = io_resp_f3_1_is_br_0; // @[tage.scala:198:7]
assign io_resp_f3_1_is_jal = io_resp_f3_1_is_jal_0; // @[tage.scala:198:7]
assign io_resp_f3_1_predicted_pc_valid = io_resp_f3_1_predicted_pc_valid_0; // @[tage.scala:198:7]
assign io_resp_f3_1_predicted_pc_bits = io_resp_f3_1_predicted_pc_bits_0; // @[tage.scala:198:7]
assign io_resp_f3_2_taken = io_resp_f3_2_taken_0; // @[tage.scala:198:7]
assign io_resp_f3_2_is_br = io_resp_f3_2_is_br_0; // @[tage.scala:198:7]
assign io_resp_f3_2_is_jal = io_resp_f3_2_is_jal_0; // @[tage.scala:198:7]
assign io_resp_f3_2_predicted_pc_valid = io_resp_f3_2_predicted_pc_valid_0; // @[tage.scala:198:7]
assign io_resp_f3_2_predicted_pc_bits = io_resp_f3_2_predicted_pc_bits_0; // @[tage.scala:198:7]
assign io_resp_f3_3_taken = io_resp_f3_3_taken_0; // @[tage.scala:198:7]
assign io_resp_f3_3_is_br = io_resp_f3_3_is_br_0; // @[tage.scala:198:7]
assign io_resp_f3_3_is_jal = io_resp_f3_3_is_jal_0; // @[tage.scala:198:7]
assign io_resp_f3_3_predicted_pc_valid = io_resp_f3_3_predicted_pc_valid_0; // @[tage.scala:198:7]
assign io_resp_f3_3_predicted_pc_bits = io_resp_f3_3_predicted_pc_bits_0; // @[tage.scala:198:7]
assign io_f3_meta = io_f3_meta_0; // @[tage.scala:198:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_97 :
input clock : Clock
input reset : Reset
output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_return : UInt<5>, vc_free : UInt<5>}}
wire _in_flight_WIRE : UInt<1>[5]
connect _in_flight_WIRE[0], UInt<1>(0h0)
connect _in_flight_WIRE[1], UInt<1>(0h0)
connect _in_flight_WIRE[2], UInt<1>(0h0)
connect _in_flight_WIRE[3], UInt<1>(0h0)
connect _in_flight_WIRE[4], UInt<1>(0h0)
regreset in_flight : UInt<1>[5], clock, reset, _in_flight_WIRE
when io.in.flit[0].valid :
when io.in.flit[0].bits.head :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1)
node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
when io.in.flit[0].bits.tail :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)
node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T_4 :
node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0))
node _T_6 = or(_T_5, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1))
node _T_11 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_12 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_13 = and(_T_11, _T_12)
node _T_14 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_15 = and(_T_13, _T_14)
node _T_16 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_19 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_20 = and(_T_18, _T_19)
node _T_21 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_24 = and(_T_22, _T_23)
node _T_25 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_26 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_27 = and(_T_25, _T_26)
node _T_28 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_29 = and(_T_27, _T_28)
node _T_30 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_31 = and(_T_29, _T_30)
node _T_32 = or(_T_17, _T_24)
node _T_33 = or(_T_32, _T_31)
node _T_34 = or(_T_10, _T_33)
node _T_35 = asUInt(reset)
node _T_36 = eq(_T_35, UInt<1>(0h0))
when _T_36 :
node _T_37 = eq(_T_34, UInt<1>(0h0))
when _T_37 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2
assert(clock, _T_34, UInt<1>(0h1), "") : assert_2
node _T_38 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2))
node _T_39 = or(_T_38, UInt<1>(0h0))
node _T_40 = asUInt(reset)
node _T_41 = eq(_T_40, UInt<1>(0h0))
when _T_41 :
node _T_42 = eq(_T_39, UInt<1>(0h0))
when _T_42 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3
assert(clock, _T_39, UInt<1>(0h1), "") : assert_3
node _T_43 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3))
node _T_44 = or(_T_43, UInt<1>(0h0))
node _T_45 = asUInt(reset)
node _T_46 = eq(_T_45, UInt<1>(0h0))
when _T_46 :
node _T_47 = eq(_T_44, UInt<1>(0h0))
when _T_47 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4
assert(clock, _T_44, UInt<1>(0h1), "") : assert_4
node _T_48 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4))
node _T_49 = or(_T_48, UInt<1>(0h0))
node _T_50 = asUInt(reset)
node _T_51 = eq(_T_50, UInt<1>(0h0))
when _T_51 :
node _T_52 = eq(_T_49, UInt<1>(0h0))
when _T_52 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5
assert(clock, _T_49, UInt<1>(0h1), "") : assert_5 | module NoCMonitor_97( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26]
reg in_flight_2; // @[Monitor.scala:16:26]
reg in_flight_3; // @[Monitor.scala:16:26]
reg in_flight_4; // @[Monitor.scala:16:26]
wire _GEN = io_in_flit_0_bits_virt_channel_id == 3'h0; // @[Monitor.scala:21:46]
wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 3'h2; // @[Monitor.scala:21:46]
wire _GEN_1 = io_in_flit_0_bits_virt_channel_id == 3'h3; // @[Monitor.scala:21:46]
wire _GEN_2 = io_in_flit_0_bits_virt_channel_id == 3'h4; // @[Monitor.scala:21:46] |
Generate the Verilog code corresponding to this FIRRTL code module TLWidthWidget8 :
input clock : Clock
input reset : Reset
output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}}
wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn.d.bits.corrupt
invalidate anonIn.d.bits.data
invalidate anonIn.d.bits.denied
invalidate anonIn.d.bits.sink
invalidate anonIn.d.bits.source
invalidate anonIn.d.bits.size
invalidate anonIn.d.bits.param
invalidate anonIn.d.bits.opcode
invalidate anonIn.d.valid
invalidate anonIn.d.ready
invalidate anonIn.a.bits.corrupt
invalidate anonIn.a.bits.data
invalidate anonIn.a.bits.mask
invalidate anonIn.a.bits.address
invalidate anonIn.a.bits.source
invalidate anonIn.a.bits.size
invalidate anonIn.a.bits.param
invalidate anonIn.a.bits.opcode
invalidate anonIn.a.valid
invalidate anonIn.a.ready
inst monitor of TLMonitor_3
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, anonIn.d.bits.data
connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied
connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink
connect monitor.io.in.d.bits.source, anonIn.d.bits.source
connect monitor.io.in.d.bits.size, anonIn.d.bits.size
connect monitor.io.in.d.bits.param, anonIn.d.bits.param
connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode
connect monitor.io.in.d.valid, anonIn.d.valid
connect monitor.io.in.d.ready, anonIn.d.ready
connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, anonIn.a.bits.data
connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask
connect monitor.io.in.a.bits.address, anonIn.a.bits.address
connect monitor.io.in.a.bits.source, anonIn.a.bits.source
connect monitor.io.in.a.bits.size, anonIn.a.bits.size
connect monitor.io.in.a.bits.param, anonIn.a.bits.param
connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode
connect monitor.io.in.a.valid, anonIn.a.valid
connect monitor.io.in.a.ready, anonIn.a.ready
wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}
invalidate anonOut.d.bits.corrupt
invalidate anonOut.d.bits.data
invalidate anonOut.d.bits.denied
invalidate anonOut.d.bits.sink
invalidate anonOut.d.bits.source
invalidate anonOut.d.bits.size
invalidate anonOut.d.bits.param
invalidate anonOut.d.bits.opcode
invalidate anonOut.d.valid
invalidate anonOut.d.ready
invalidate anonOut.a.bits.corrupt
invalidate anonOut.a.bits.data
invalidate anonOut.a.bits.mask
invalidate anonOut.a.bits.address
invalidate anonOut.a.bits.source
invalidate anonOut.a.bits.size
invalidate anonOut.a.bits.param
invalidate anonOut.a.bits.opcode
invalidate anonOut.a.valid
invalidate anonOut.a.ready
connect auto.anon_out, anonOut
connect anonIn, auto.anon_in
wire repeat : UInt<1>
inst repeated_repeater of Repeater_TLBundleA_a32d64s5k1z4u
connect repeated_repeater.clock, clock
connect repeated_repeater.reset, reset
connect repeated_repeater.io.repeat, repeat
connect repeated_repeater.io.enq, anonIn.a
wire cated : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect cated.bits, repeated_repeater.io.deq.bits
connect cated.valid, repeated_repeater.io.deq.valid
connect repeated_repeater.io.deq.ready, cated.ready
node _cated_bits_data_T = bits(repeated_repeater.io.deq.bits.data, 63, 32)
node _cated_bits_data_T_1 = bits(anonIn.a.bits.data, 31, 0)
node _cated_bits_data_T_2 = cat(_cated_bits_data_T, _cated_bits_data_T_1)
connect cated.bits.data, _cated_bits_data_T_2
node _repeat_hasData_opdata_T = bits(cated.bits.opcode, 2, 2)
node repeat_hasData = eq(_repeat_hasData_opdata_T, UInt<1>(0h0))
node _repeat_limit_T = dshl(UInt<3>(0h7), cated.bits.size)
node _repeat_limit_T_1 = bits(_repeat_limit_T, 2, 0)
node _repeat_limit_T_2 = not(_repeat_limit_T_1)
node repeat_limit = shr(_repeat_limit_T_2, 2)
regreset repeat_count : UInt<1>, clock, reset, UInt<1>(0h0)
node repeat_first = eq(repeat_count, UInt<1>(0h0))
node _repeat_last_T = eq(repeat_count, repeat_limit)
node _repeat_last_T_1 = eq(repeat_hasData, UInt<1>(0h0))
node repeat_last = or(_repeat_last_T, _repeat_last_T_1)
node _repeat_T = and(anonOut.a.ready, anonOut.a.valid)
when _repeat_T :
node _repeat_count_T = add(repeat_count, UInt<1>(0h1))
node _repeat_count_T_1 = tail(_repeat_count_T, 1)
connect repeat_count, _repeat_count_T_1
when repeat_last :
connect repeat_count, UInt<1>(0h0)
node repeat_sel = bits(cated.bits.address, 2, 2)
node repeat_index = or(repeat_sel, repeat_count)
connect anonOut.a.bits, cated.bits
connect anonOut.a.valid, cated.valid
connect cated.ready, anonOut.a.ready
node _repeat_anonOut_a_bits_data_mux_T = bits(cated.bits.data, 31, 0)
node _repeat_anonOut_a_bits_data_mux_T_1 = bits(cated.bits.data, 63, 32)
wire repeat_anonOut_a_bits_data_mux : UInt<32>[2]
connect repeat_anonOut_a_bits_data_mux[0], _repeat_anonOut_a_bits_data_mux_T
connect repeat_anonOut_a_bits_data_mux[1], _repeat_anonOut_a_bits_data_mux_T_1
connect anonOut.a.bits.data, repeat_anonOut_a_bits_data_mux[repeat_index]
node _repeat_anonOut_a_bits_mask_mux_T = bits(cated.bits.mask, 3, 0)
node _repeat_anonOut_a_bits_mask_mux_T_1 = bits(cated.bits.mask, 7, 4)
wire repeat_anonOut_a_bits_mask_mux : UInt<4>[2]
connect repeat_anonOut_a_bits_mask_mux[0], _repeat_anonOut_a_bits_mask_mux_T
connect repeat_anonOut_a_bits_mask_mux[1], _repeat_anonOut_a_bits_mask_mux_T_1
connect anonOut.a.bits.mask, repeat_anonOut_a_bits_mask_mux[repeat_index]
node _repeat_T_1 = eq(repeat_last, UInt<1>(0h0))
connect repeat, _repeat_T_1
node hasData = bits(anonOut.d.bits.opcode, 0, 0)
node _limit_T = dshl(UInt<3>(0h7), anonOut.d.bits.size)
node _limit_T_1 = bits(_limit_T, 2, 0)
node _limit_T_2 = not(_limit_T_1)
node limit = shr(_limit_T_2, 2)
regreset count : UInt<1>, clock, reset, UInt<1>(0h0)
node first = eq(count, UInt<1>(0h0))
node _last_T = eq(count, limit)
node _last_T_1 = eq(hasData, UInt<1>(0h0))
node last = or(_last_T, _last_T_1)
node _enable_T = xor(count, UInt<1>(0h0))
node _enable_T_1 = and(_enable_T, limit)
node _enable_T_2 = orr(_enable_T_1)
node enable_0 = eq(_enable_T_2, UInt<1>(0h0))
node _enable_T_3 = xor(count, UInt<1>(0h1))
node _enable_T_4 = and(_enable_T_3, limit)
node _enable_T_5 = orr(_enable_T_4)
node enable_1 = eq(_enable_T_5, UInt<1>(0h0))
regreset corrupt_reg : UInt<1>, clock, reset, UInt<1>(0h0)
node corrupt_out = or(anonOut.d.bits.corrupt, corrupt_reg)
node _T = and(anonOut.d.ready, anonOut.d.valid)
when _T :
node _count_T = add(count, UInt<1>(0h1))
node _count_T_1 = tail(_count_T, 1)
connect count, _count_T_1
connect corrupt_reg, corrupt_out
when last :
connect count, UInt<1>(0h0)
connect corrupt_reg, UInt<1>(0h0)
node _anonOut_d_ready_T = eq(last, UInt<1>(0h0))
node _anonOut_d_ready_T_1 = or(anonIn.d.ready, _anonOut_d_ready_T)
connect anonOut.d.ready, _anonOut_d_ready_T_1
node _anonIn_d_valid_T = and(anonOut.d.valid, last)
connect anonIn.d.valid, _anonIn_d_valid_T
connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt
connect anonIn.d.bits.data, anonOut.d.bits.data
connect anonIn.d.bits.denied, anonOut.d.bits.denied
connect anonIn.d.bits.sink, anonOut.d.bits.sink
connect anonIn.d.bits.source, anonOut.d.bits.source
connect anonIn.d.bits.size, anonOut.d.bits.size
connect anonIn.d.bits.param, anonOut.d.bits.param
connect anonIn.d.bits.opcode, anonOut.d.bits.opcode
regreset anonIn_d_bits_data_rdata_written_once : UInt<1>, clock, reset, UInt<1>(0h0)
node _anonIn_d_bits_data_masked_enable_T = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0))
node anonIn_d_bits_data_masked_enable_0 = or(enable_0, _anonIn_d_bits_data_masked_enable_T)
node _anonIn_d_bits_data_masked_enable_T_1 = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0))
node anonIn_d_bits_data_masked_enable_1 = or(enable_1, _anonIn_d_bits_data_masked_enable_T_1)
wire anonIn_d_bits_data_odata_0 : UInt
connect anonIn_d_bits_data_odata_0, anonOut.d.bits.data
wire anonIn_d_bits_data_odata_1 : UInt
connect anonIn_d_bits_data_odata_1, anonOut.d.bits.data
reg anonIn_d_bits_data_rdata : UInt<32>[1], clock
node anonIn_d_bits_data_mdata_0 = mux(anonIn_d_bits_data_masked_enable_0, anonIn_d_bits_data_odata_0, anonIn_d_bits_data_rdata[0])
node anonIn_d_bits_data_mdata_1 = mux(anonIn_d_bits_data_masked_enable_1, anonIn_d_bits_data_odata_1, anonOut.d.bits.data)
node _anonIn_d_bits_data_T = and(anonOut.d.ready, anonOut.d.valid)
node _anonIn_d_bits_data_T_1 = eq(last, UInt<1>(0h0))
node _anonIn_d_bits_data_T_2 = and(_anonIn_d_bits_data_T, _anonIn_d_bits_data_T_1)
when _anonIn_d_bits_data_T_2 :
connect anonIn_d_bits_data_rdata_written_once, UInt<1>(0h1)
connect anonIn_d_bits_data_rdata[0], anonIn_d_bits_data_mdata_0
node _anonIn_d_bits_data_T_3 = cat(anonIn_d_bits_data_mdata_1, anonIn_d_bits_data_mdata_0)
connect anonIn.d.bits.data, _anonIn_d_bits_data_T_3
connect anonIn.d.bits.corrupt, corrupt_out
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<5>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<5>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<32>(0h0)
connect _WIRE_6.bits.mask, UInt<4>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<5>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<32>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<5>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
connect _WIRE_9.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_10.bits.sink, UInt<1>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.valid, UInt<1>(0h0) | module TLWidthWidget8( // @[WidthWidget.scala:27:9]
input clock, // @[WidthWidget.scala:27:9]
input reset, // @[WidthWidget.scala:27:9]
output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire [63:0] _repeated_repeater_io_deq_bits_data; // @[Repeater.scala:36:26]
wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [4:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [4:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [31:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire anonIn_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[WidthWidget.scala:27:9]
wire [3:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[WidthWidget.scala:27:9]
wire [4:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[WidthWidget.scala:27:9]
wire [31:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[WidthWidget.scala:27:9]
wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[WidthWidget.scala:27:9]
wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[WidthWidget.scala:27:9]
wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[WidthWidget.scala:27:9]
wire anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[WidthWidget.scala:27:9]
wire anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [3:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [31:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire anonOut_d_ready; // @[MixedNode.scala:542:17]
wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[WidthWidget.scala:27:9]
wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[WidthWidget.scala:27:9]
wire [4:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[WidthWidget.scala:27:9]
wire anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[WidthWidget.scala:27:9]
wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[WidthWidget.scala:27:9]
wire [31:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[WidthWidget.scala:27:9]
wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [1:0] auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9]
wire [4:0] auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9]
wire [63:0] auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9]
wire [4:0] auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9]
wire [31:0] auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9]
wire [31:0] auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9]
wire auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[WidthWidget.scala:27:9]
wire _anonIn_d_valid_T; // @[WidthWidget.scala:77:29]
assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12]
assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[WidthWidget.scala:27:9]
wire corrupt_out; // @[WidthWidget.scala:47:36]
assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire cated_ready = anonOut_a_ready; // @[WidthWidget.scala:161:25]
wire cated_valid; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] cated_bits_opcode; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] cated_bits_param; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] cated_bits_size; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[WidthWidget.scala:27:9]
wire [4:0] cated_bits_source; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] cated_bits_address; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[WidthWidget.scala:27:9]
wire cated_bits_corrupt; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29]
assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[WidthWidget.scala:27:9]
assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_param = anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_size = anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_source = anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_sink = anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_denied = anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] anonIn_d_bits_data_odata_0 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47]
wire [31:0] anonIn_d_bits_data_odata_1 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47]
wire _repeat_T_1; // @[WidthWidget.scala:148:7]
wire repeat_0; // @[WidthWidget.scala:159:26]
assign anonOut_a_valid = cated_valid; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_opcode = cated_bits_opcode; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_param = cated_bits_param; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_size = cated_bits_size; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_source = cated_bits_source; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_address = cated_bits_address; // @[WidthWidget.scala:161:25]
wire [63:0] _cated_bits_data_T_2; // @[WidthWidget.scala:163:39]
assign anonOut_a_bits_corrupt = cated_bits_corrupt; // @[WidthWidget.scala:161:25]
wire [7:0] cated_bits_mask; // @[WidthWidget.scala:161:25]
wire [63:0] cated_bits_data; // @[WidthWidget.scala:161:25]
wire [31:0] _cated_bits_data_T = _repeated_repeater_io_deq_bits_data[63:32]; // @[Repeater.scala:36:26]
wire [31:0] _cated_bits_data_T_1 = anonIn_a_bits_data[31:0]; // @[WidthWidget.scala:165:31]
assign _cated_bits_data_T_2 = {_cated_bits_data_T, _cated_bits_data_T_1}; // @[WidthWidget.scala:163:39, :164:37, :165:31]
assign cated_bits_data = _cated_bits_data_T_2; // @[WidthWidget.scala:161:25, :163:39]
wire _repeat_hasData_opdata_T = cated_bits_opcode[2]; // @[WidthWidget.scala:161:25]
wire repeat_hasData = ~_repeat_hasData_opdata_T; // @[Edges.scala:92:{28,37}]
wire [17:0] _repeat_limit_T = 18'h7 << cated_bits_size; // @[package.scala:243:71]
wire [2:0] _repeat_limit_T_1 = _repeat_limit_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _repeat_limit_T_2 = ~_repeat_limit_T_1; // @[package.scala:243:{46,76}]
wire repeat_limit = _repeat_limit_T_2[2]; // @[package.scala:243:46]
reg repeat_count; // @[WidthWidget.scala:105:26]
wire repeat_first = ~repeat_count; // @[WidthWidget.scala:105:26, :106:25]
wire _repeat_last_T = repeat_count == repeat_limit; // @[WidthWidget.scala:103:47, :105:26, :107:25]
wire _repeat_last_T_1 = ~repeat_hasData; // @[WidthWidget.scala:107:38]
wire repeat_last = _repeat_last_T | _repeat_last_T_1; // @[WidthWidget.scala:107:{25,35,38}]
wire _repeat_T = anonOut_a_ready & anonOut_a_valid; // @[Decoupled.scala:51:35]
wire [1:0] _repeat_count_T = {1'h0, repeat_count} + 2'h1; // @[WidthWidget.scala:105:26, :110:24]
wire _repeat_count_T_1 = _repeat_count_T[0]; // @[WidthWidget.scala:110:24]
wire repeat_sel = cated_bits_address[2]; // @[WidthWidget.scala:116:39, :161:25]
wire repeat_index = repeat_sel | repeat_count; // @[WidthWidget.scala:105:26, :116:39, :126:24]
wire [31:0] _repeat_anonOut_a_bits_data_mux_T = cated_bits_data[31:0]; // @[WidthWidget.scala:128:55, :161:25]
wire [31:0] repeat_anonOut_a_bits_data_mux_0 = _repeat_anonOut_a_bits_data_mux_T; // @[WidthWidget.scala:128:{43,55}]
wire [31:0] _repeat_anonOut_a_bits_data_mux_T_1 = cated_bits_data[63:32]; // @[WidthWidget.scala:128:55, :161:25]
wire [31:0] repeat_anonOut_a_bits_data_mux_1 = _repeat_anonOut_a_bits_data_mux_T_1; // @[WidthWidget.scala:128:{43,55}]
assign anonOut_a_bits_data = repeat_index ? repeat_anonOut_a_bits_data_mux_1 : repeat_anonOut_a_bits_data_mux_0; // @[WidthWidget.scala:126:24, :128:43, :137:30]
wire [3:0] _repeat_anonOut_a_bits_mask_mux_T = cated_bits_mask[3:0]; // @[WidthWidget.scala:128:55, :161:25]
wire [3:0] repeat_anonOut_a_bits_mask_mux_0 = _repeat_anonOut_a_bits_mask_mux_T; // @[WidthWidget.scala:128:{43,55}]
wire [3:0] _repeat_anonOut_a_bits_mask_mux_T_1 = cated_bits_mask[7:4]; // @[WidthWidget.scala:128:55, :161:25]
wire [3:0] repeat_anonOut_a_bits_mask_mux_1 = _repeat_anonOut_a_bits_mask_mux_T_1; // @[WidthWidget.scala:128:{43,55}]
assign anonOut_a_bits_mask = repeat_index ? repeat_anonOut_a_bits_mask_mux_1 : repeat_anonOut_a_bits_mask_mux_0; // @[WidthWidget.scala:126:24, :128:43, :140:53]
assign _repeat_T_1 = ~repeat_last; // @[WidthWidget.scala:107:35, :148:7]
assign repeat_0 = _repeat_T_1; // @[WidthWidget.scala:148:7, :159:26]
wire hasData = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36]
wire [17:0] _limit_T = 18'h7 << anonOut_d_bits_size; // @[package.scala:243:71]
wire [2:0] _limit_T_1 = _limit_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _limit_T_2 = ~_limit_T_1; // @[package.scala:243:{46,76}]
wire limit = _limit_T_2[2]; // @[package.scala:243:46]
reg count; // @[WidthWidget.scala:40:27]
wire _enable_T = count; // @[WidthWidget.scala:40:27, :43:56]
wire first = ~count; // @[WidthWidget.scala:40:27, :41:26]
wire _last_T = count == limit; // @[WidthWidget.scala:38:47, :40:27, :42:26]
wire _last_T_1 = ~hasData; // @[WidthWidget.scala:42:39]
wire last = _last_T | _last_T_1; // @[WidthWidget.scala:42:{26,36,39}]
wire _enable_T_1 = _enable_T & limit; // @[WidthWidget.scala:38:47, :43:{56,63}]
wire _enable_T_2 = _enable_T_1; // @[WidthWidget.scala:43:{63,72}]
wire enable_0 = ~_enable_T_2; // @[WidthWidget.scala:43:{47,72}]
wire _enable_T_3 = ~count; // @[WidthWidget.scala:40:27, :41:26, :43:56]
wire _enable_T_4 = _enable_T_3 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}]
wire _enable_T_5 = _enable_T_4; // @[WidthWidget.scala:43:{63,72}]
wire enable_1 = ~_enable_T_5; // @[WidthWidget.scala:43:{47,72}]
reg corrupt_reg; // @[WidthWidget.scala:45:32]
assign corrupt_out = anonOut_d_bits_corrupt | corrupt_reg; // @[WidthWidget.scala:45:32, :47:36]
assign anonIn_d_bits_corrupt = corrupt_out; // @[WidthWidget.scala:47:36]
wire _anonIn_d_bits_data_T = anonOut_d_ready & anonOut_d_valid; // @[Decoupled.scala:51:35]
wire [1:0] _count_T = {1'h0, count} + 2'h1; // @[WidthWidget.scala:40:27, :50:24]
wire _count_T_1 = _count_T[0]; // @[WidthWidget.scala:50:24]
wire _anonOut_d_ready_T = ~last; // @[WidthWidget.scala:42:36, :76:32]
assign _anonOut_d_ready_T_1 = anonIn_d_ready | _anonOut_d_ready_T; // @[WidthWidget.scala:76:{29,32}]
assign anonOut_d_ready = _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29]
assign _anonIn_d_valid_T = anonOut_d_valid & last; // @[WidthWidget.scala:42:36, :77:29]
assign anonIn_d_valid = _anonIn_d_valid_T; // @[WidthWidget.scala:77:29]
reg anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41]
wire _anonIn_d_bits_data_masked_enable_T = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonIn_d_bits_data_masked_enable_0 = enable_0 | _anonIn_d_bits_data_masked_enable_T; // @[WidthWidget.scala:43:47, :63:{42,45}]
wire _anonIn_d_bits_data_masked_enable_T_1 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonIn_d_bits_data_masked_enable_1 = enable_1 | _anonIn_d_bits_data_masked_enable_T_1; // @[WidthWidget.scala:43:47, :63:{42,45}]
reg [31:0] anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:66:24]
wire [31:0] anonIn_d_bits_data_mdata_0 = anonIn_d_bits_data_masked_enable_0 ? anonIn_d_bits_data_odata_0 : anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88]
wire [31:0] anonIn_d_bits_data_mdata_1 = anonIn_d_bits_data_masked_enable_1 ? anonIn_d_bits_data_odata_1 : anonOut_d_bits_data; // @[WidthWidget.scala:63:42, :65:47, :68:88]
wire _anonIn_d_bits_data_T_1 = ~last; // @[WidthWidget.scala:42:36, :69:26, :76:32]
wire _anonIn_d_bits_data_T_2 = _anonIn_d_bits_data_T & _anonIn_d_bits_data_T_1; // @[Decoupled.scala:51:35]
assign _anonIn_d_bits_data_T_3 = {anonIn_d_bits_data_mdata_1, anonIn_d_bits_data_mdata_0}; // @[WidthWidget.scala:68:88, :73:12]
assign anonIn_d_bits_data = _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12]
always @(posedge clock) begin // @[WidthWidget.scala:27:9]
if (reset) begin // @[WidthWidget.scala:27:9]
repeat_count <= 1'h0; // @[WidthWidget.scala:105:26]
count <= 1'h0; // @[WidthWidget.scala:40:27]
corrupt_reg <= 1'h0; // @[WidthWidget.scala:45:32]
anonIn_d_bits_data_rdata_written_once <= 1'h0; // @[WidthWidget.scala:62:41]
end
else begin // @[WidthWidget.scala:27:9]
if (_repeat_T) // @[Decoupled.scala:51:35]
repeat_count <= ~repeat_last & _repeat_count_T_1; // @[WidthWidget.scala:105:26, :107:35, :110:{15,24}, :111:{21,29}]
if (_anonIn_d_bits_data_T) begin // @[Decoupled.scala:51:35]
count <= ~last & _count_T_1; // @[WidthWidget.scala:40:27, :42:36, :50:{15,24}, :52:21, :53:17]
corrupt_reg <= ~last & corrupt_out; // @[WidthWidget.scala:42:36, :45:32, :47:36, :50:15, :51:21, :52:21, :53:17, :54:23]
end
anonIn_d_bits_data_rdata_written_once <= _anonIn_d_bits_data_T_2 | anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30]
end
if (_anonIn_d_bits_data_T_2) // @[WidthWidget.scala:69:23]
anonIn_d_bits_data_rdata_0 <= anonIn_d_bits_data_mdata_0; // @[WidthWidget.scala:66:24, :68:88]
always @(posedge)
TLMonitor_3 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (anonIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (anonIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (anonIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (anonIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (anonIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (anonIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (anonIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (anonIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (anonIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (anonIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (anonIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (anonIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Repeater_TLBundleA_a32d64s5k1z4u repeated_repeater ( // @[Repeater.scala:36:26]
.clock (clock),
.reset (reset),
.io_repeat (repeat_0), // @[WidthWidget.scala:159:26]
.io_enq_ready (anonIn_a_ready),
.io_enq_valid (anonIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (cated_ready), // @[WidthWidget.scala:161:25]
.io_deq_valid (cated_valid),
.io_deq_bits_opcode (cated_bits_opcode),
.io_deq_bits_param (cated_bits_param),
.io_deq_bits_size (cated_bits_size),
.io_deq_bits_source (cated_bits_source),
.io_deq_bits_address (cated_bits_address),
.io_deq_bits_mask (cated_bits_mask),
.io_deq_bits_data (_repeated_repeater_io_deq_bits_data),
.io_deq_bits_corrupt (cated_bits_corrupt)
); // @[Repeater.scala:36:26]
assign auto_anon_in_a_ready = auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_valid = auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_opcode = auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_param = auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_size = auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_source = auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_sink = auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_denied = auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_data = auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_corrupt = auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_valid = auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_opcode = auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_param = auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_size = auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_source = auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_address = auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_mask = auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_data = auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_corrupt = auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_d_ready = auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module LoopConv :
input clock : Clock
input reset : Reset
output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, rob_id : { valid : UInt<1>, bits : UInt<6>}, from_matmul_fsm : UInt<1>, from_conv_fsm : UInt<1>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, rob_id : { valid : UInt<1>, bits : UInt<6>}, from_matmul_fsm : UInt<1>, from_conv_fsm : UInt<1>}}, flip ld_completed : UInt<6>, flip st_completed : UInt<6>, flip ex_completed : UInt<6>, busy : UInt<1>}
reg loops : { outer_bounds : { batch_size : UInt<16>, in_row_dim : UInt<16>, in_col_dim : UInt<16>, in_channels : UInt<16>, out_channels : UInt<16>, out_col_dim : UInt<16>, out_row_dim : UInt<16>, out_stride : UInt<16>, in_stride : UInt<16>, weight_stride : UInt<16>, pool_out_row_dim : UInt<16>, pool_out_col_dim : UInt<16>, stride : UInt<16>, padding : UInt<16>, kernel_dim : UInt<16>, kernel_dilation : UInt<16>, pool_size : UInt<16>, pool_stride : UInt<16>, pool_padding : UInt<16>}, inner_bounds : { batches : UInt<16>, porows : UInt<16>, pocols : UInt<16>, pochs : UInt<16>, krows : UInt<16>, kcols : UInt<16>, kchs : UInt<16>, lpad : UInt<16>, rpad : UInt<16>, upad : UInt<16>, dpad : UInt<16>, plpad : UInt<16>, prad : UInt<16>, pupad : UInt<16>, pdpad : UInt<16>, orows : UInt<16>, ocols : UInt<16>}, bias_dram_addr : UInt<40>, weights_dram_addr : UInt<40>, input_dram_addr : UInt<40>, output_dram_addr : UInt<40>, no_bias : UInt<1>, wrot180 : UInt<1>, no_pool : UInt<1>, downsample : UInt<1>, input_dilated : UInt<1>, activation : UInt<2>, trans_output_1203 : UInt<1>, trans_weight_1203 : UInt<1>, trans_weight_0132 : UInt<1>, trans_input_3120 : UInt<1>, dw : UInt<1>, max_pixels_per_row : UInt<16>, a_ex_spad_id : UInt<2>, b_ex_spad_id : UInt<2>, configured : UInt<1>, running : UInt<1>, ld_bias_started : UInt<1>, ld_input_started : UInt<1>, ld_weights_started : UInt<1>, ex_started : UInt<1>, st_started : UInt<1>, ld_bias_completed : UInt<1>, ld_input_completed : UInt<1>, ld_weights_completed : UInt<1>, ex_completed : UInt<1>, st_completed : UInt<1>, a_addr_start : UInt<14>, b_addr_end : UInt<15>}[2], clock
regreset head_loop_id : UInt<1>, clock, reset, UInt<1>(0h0)
node tail_loop_id = not(head_loop_id)
node loop_configured = or(loops[0].configured, loops[1].configured)
node loop_being_configured_id = mux(loops[head_loop_id].configured, tail_loop_id, head_loop_id)
inst ld_bias of LoopConvLdBias
connect ld_bias.clock, clock
connect ld_bias.reset, reset
inst ld_input of LoopConvLdInput
connect ld_input.clock, clock
connect ld_input.reset, reset
inst ld_weights of LoopConvLdWeight
connect ld_weights.clock, clock
connect ld_weights.reset, reset
inst ex of LoopConvExecute
connect ex.clock, clock
connect ex.reset, reset
inst st of LoopConvSt
connect st.clock, clock
connect st.reset, reset
inst cmd_q of Queue2_GemminiCmd_1
connect cmd_q.clock, clock
connect cmd_q.reset, reset
connect cmd_q.io.enq.valid, io.in.valid
connect cmd_q.io.enq.bits.from_conv_fsm, io.in.bits.from_conv_fsm
connect cmd_q.io.enq.bits.from_matmul_fsm, io.in.bits.from_matmul_fsm
connect cmd_q.io.enq.bits.rob_id.bits, io.in.bits.rob_id.bits
connect cmd_q.io.enq.bits.rob_id.valid, io.in.bits.rob_id.valid
connect cmd_q.io.enq.bits.cmd.status.uie, io.in.bits.cmd.status.uie
connect cmd_q.io.enq.bits.cmd.status.sie, io.in.bits.cmd.status.sie
connect cmd_q.io.enq.bits.cmd.status.hie, io.in.bits.cmd.status.hie
connect cmd_q.io.enq.bits.cmd.status.mie, io.in.bits.cmd.status.mie
connect cmd_q.io.enq.bits.cmd.status.upie, io.in.bits.cmd.status.upie
connect cmd_q.io.enq.bits.cmd.status.spie, io.in.bits.cmd.status.spie
connect cmd_q.io.enq.bits.cmd.status.ube, io.in.bits.cmd.status.ube
connect cmd_q.io.enq.bits.cmd.status.mpie, io.in.bits.cmd.status.mpie
connect cmd_q.io.enq.bits.cmd.status.spp, io.in.bits.cmd.status.spp
connect cmd_q.io.enq.bits.cmd.status.vs, io.in.bits.cmd.status.vs
connect cmd_q.io.enq.bits.cmd.status.mpp, io.in.bits.cmd.status.mpp
connect cmd_q.io.enq.bits.cmd.status.fs, io.in.bits.cmd.status.fs
connect cmd_q.io.enq.bits.cmd.status.xs, io.in.bits.cmd.status.xs
connect cmd_q.io.enq.bits.cmd.status.mprv, io.in.bits.cmd.status.mprv
connect cmd_q.io.enq.bits.cmd.status.sum, io.in.bits.cmd.status.sum
connect cmd_q.io.enq.bits.cmd.status.mxr, io.in.bits.cmd.status.mxr
connect cmd_q.io.enq.bits.cmd.status.tvm, io.in.bits.cmd.status.tvm
connect cmd_q.io.enq.bits.cmd.status.tw, io.in.bits.cmd.status.tw
connect cmd_q.io.enq.bits.cmd.status.tsr, io.in.bits.cmd.status.tsr
connect cmd_q.io.enq.bits.cmd.status.zero1, io.in.bits.cmd.status.zero1
connect cmd_q.io.enq.bits.cmd.status.sd_rv32, io.in.bits.cmd.status.sd_rv32
connect cmd_q.io.enq.bits.cmd.status.uxl, io.in.bits.cmd.status.uxl
connect cmd_q.io.enq.bits.cmd.status.sxl, io.in.bits.cmd.status.sxl
connect cmd_q.io.enq.bits.cmd.status.sbe, io.in.bits.cmd.status.sbe
connect cmd_q.io.enq.bits.cmd.status.mbe, io.in.bits.cmd.status.mbe
connect cmd_q.io.enq.bits.cmd.status.gva, io.in.bits.cmd.status.gva
connect cmd_q.io.enq.bits.cmd.status.mpv, io.in.bits.cmd.status.mpv
connect cmd_q.io.enq.bits.cmd.status.zero2, io.in.bits.cmd.status.zero2
connect cmd_q.io.enq.bits.cmd.status.sd, io.in.bits.cmd.status.sd
connect cmd_q.io.enq.bits.cmd.status.v, io.in.bits.cmd.status.v
connect cmd_q.io.enq.bits.cmd.status.prv, io.in.bits.cmd.status.prv
connect cmd_q.io.enq.bits.cmd.status.dv, io.in.bits.cmd.status.dv
connect cmd_q.io.enq.bits.cmd.status.dprv, io.in.bits.cmd.status.dprv
connect cmd_q.io.enq.bits.cmd.status.isa, io.in.bits.cmd.status.isa
connect cmd_q.io.enq.bits.cmd.status.wfi, io.in.bits.cmd.status.wfi
connect cmd_q.io.enq.bits.cmd.status.cease, io.in.bits.cmd.status.cease
connect cmd_q.io.enq.bits.cmd.status.debug, io.in.bits.cmd.status.debug
connect cmd_q.io.enq.bits.cmd.rs2, io.in.bits.cmd.rs2
connect cmd_q.io.enq.bits.cmd.rs1, io.in.bits.cmd.rs1
connect cmd_q.io.enq.bits.cmd.inst.opcode, io.in.bits.cmd.inst.opcode
connect cmd_q.io.enq.bits.cmd.inst.rd, io.in.bits.cmd.inst.rd
connect cmd_q.io.enq.bits.cmd.inst.xs2, io.in.bits.cmd.inst.xs2
connect cmd_q.io.enq.bits.cmd.inst.xs1, io.in.bits.cmd.inst.xs1
connect cmd_q.io.enq.bits.cmd.inst.xd, io.in.bits.cmd.inst.xd
connect cmd_q.io.enq.bits.cmd.inst.rs1, io.in.bits.cmd.inst.rs1
connect cmd_q.io.enq.bits.cmd.inst.rs2, io.in.bits.cmd.inst.rs2
connect cmd_q.io.enq.bits.cmd.inst.funct, io.in.bits.cmd.inst.funct
connect io.in.ready, cmd_q.io.enq.ready
node _io_busy_T = or(cmd_q.io.deq.valid, loop_configured)
connect io.busy, _io_busy_T
inst arb of Arbiter5_RoCCCommand
connect arb.clock, clock
connect arb.reset, reset
connect arb.io.in[0], st.io.cmd
connect arb.io.in[1], ex.io.cmd
connect arb.io.in[2], ld_bias.io.cmd
connect arb.io.in[3], ld_weights.io.cmd
connect arb.io.in[4], ld_input.io.cmd
regreset ld_utilization : UInt<4>, clock, reset, UInt<4>(0h0)
regreset st_utilization : UInt<3>, clock, reset, UInt<3>(0h0)
regreset ex_utilization : UInt<5>, clock, reset, UInt<5>(0h0)
node _ld_utilization_T = and(ld_bias.io.cmd.ready, ld_bias.io.cmd.valid)
node _ld_utilization_T_1 = and(ld_weights.io.cmd.ready, ld_weights.io.cmd.valid)
node _ld_utilization_T_2 = or(_ld_utilization_T, _ld_utilization_T_1)
node _ld_utilization_T_3 = and(ld_input.io.cmd.ready, ld_input.io.cmd.valid)
node _ld_utilization_T_4 = or(_ld_utilization_T_2, _ld_utilization_T_3)
node _ld_utilization_T_5 = add(ld_utilization, _ld_utilization_T_4)
node _ld_utilization_T_6 = sub(_ld_utilization_T_5, io.ld_completed)
node _ld_utilization_T_7 = asUInt(_ld_utilization_T_6)
connect ld_utilization, _ld_utilization_T_7
node _st_utilization_T = and(st.io.cmd.ready, st.io.cmd.valid)
node _st_utilization_T_1 = add(st_utilization, _st_utilization_T)
node _st_utilization_T_2 = sub(_st_utilization_T_1, io.st_completed)
node _st_utilization_T_3 = asUInt(_st_utilization_T_2)
connect st_utilization, _st_utilization_T_3
node _ex_utilization_T = and(ex.io.cmd.ready, ex.io.cmd.valid)
node _ex_utilization_T_1 = add(ex_utilization, _ex_utilization_T)
node _ex_utilization_T_2 = sub(_ex_utilization_T_1, io.ex_completed)
node _ex_utilization_T_3 = asUInt(_ex_utilization_T_2)
connect ex_utilization, _ex_utilization_T_3
node _T = geq(ld_utilization, io.ld_completed)
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: ld utilization underflow\n at LoopConv.scala:1237 assert(ld_utilization >= io.ld_completed, \"ld utilization underflow\")\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _T_4 = geq(st_utilization, io.st_completed)
node _T_5 = asUInt(reset)
node _T_6 = eq(_T_5, UInt<1>(0h0))
when _T_6 :
node _T_7 = eq(_T_4, UInt<1>(0h0))
when _T_7 :
printf(clock, UInt<1>(0h1), "Assertion failed: st utilization underflow\n at LoopConv.scala:1238 assert(st_utilization >= io.st_completed, \"st utilization underflow\")\n") : printf_1
assert(clock, _T_4, UInt<1>(0h1), "") : assert_1
node _T_8 = geq(ex_utilization, io.ex_completed)
node _T_9 = asUInt(reset)
node _T_10 = eq(_T_9, UInt<1>(0h0))
when _T_10 :
node _T_11 = eq(_T_8, UInt<1>(0h0))
when _T_11 :
printf(clock, UInt<1>(0h1), "Assertion failed: ex utilization underflow\n at LoopConv.scala:1239 assert(ex_utilization >= io.ex_completed, \"ex utilization underflow\")\n") : printf_2
assert(clock, _T_8, UInt<1>(0h1), "") : assert_2
node is_loop_run_cmd = eq(cmd_q.io.deq.bits.cmd.inst.funct, UInt<4>(0hf))
node _is_loop_config_cmd_T = geq(cmd_q.io.deq.bits.cmd.inst.funct, UInt<5>(0h10))
node _is_loop_config_cmd_T_1 = leq(cmd_q.io.deq.bits.cmd.inst.funct, UInt<5>(0h15))
node is_loop_config_cmd = and(_is_loop_config_cmd_T, _is_loop_config_cmd_T_1)
node is_loop_cmd = or(is_loop_run_cmd, is_loop_config_cmd)
node _io_out_bits_cmd_T = mux(loop_configured, arb.io.out.bits, cmd_q.io.deq.bits.cmd)
connect io.out.bits.cmd, _io_out_bits_cmd_T
connect io.out.bits.cmd.status, cmd_q.io.deq.bits.cmd.status
invalidate io.out.bits.rob_id.bits
invalidate io.out.bits.rob_id.valid
node _io_out_bits_from_matmul_fsm_T = mux(loop_configured, UInt<1>(0h0), cmd_q.io.deq.bits.from_matmul_fsm)
connect io.out.bits.from_matmul_fsm, _io_out_bits_from_matmul_fsm_T
node _io_out_bits_from_conv_fsm_T = mux(loop_configured, UInt<1>(0h1), cmd_q.io.deq.bits.from_conv_fsm)
connect io.out.bits.from_conv_fsm, _io_out_bits_from_conv_fsm_T
node _io_out_valid_T = eq(is_loop_config_cmd, UInt<1>(0h0))
node _io_out_valid_T_1 = and(cmd_q.io.deq.valid, _io_out_valid_T)
node _io_out_valid_T_2 = eq(is_loop_run_cmd, UInt<1>(0h0))
node _io_out_valid_T_3 = and(_io_out_valid_T_1, _io_out_valid_T_2)
node _io_out_valid_T_4 = mux(loop_configured, arb.io.out.valid, _io_out_valid_T_3)
connect io.out.valid, _io_out_valid_T_4
node _q_io_deq_ready_T = eq(loops[loop_being_configured_id].configured, UInt<1>(0h0))
node _q_io_deq_ready_T_1 = eq(loop_configured, UInt<1>(0h0))
node _q_io_deq_ready_T_2 = and(_q_io_deq_ready_T_1, io.out.ready)
node _q_io_deq_ready_T_3 = mux(is_loop_cmd, _q_io_deq_ready_T, _q_io_deq_ready_T_2)
connect cmd_q.io.deq.ready, _q_io_deq_ready_T_3
connect arb.io.out.ready, io.out.ready
node _ex_is_waiting_for_loads_T = eq(loops[ex.io.loop_id].ex_completed, UInt<1>(0h0))
node _ex_is_waiting_for_loads_T_1 = and(loops[ex.io.loop_id].ex_started, _ex_is_waiting_for_loads_T)
node _ex_is_waiting_for_loads_T_2 = and(loops[ex.io.loop_id].ld_input_completed, loops[ex.io.loop_id].ld_weights_completed)
node _ex_is_waiting_for_loads_T_3 = and(_ex_is_waiting_for_loads_T_2, loops[ex.io.loop_id].ld_bias_completed)
node _ex_is_waiting_for_loads_T_4 = eq(_ex_is_waiting_for_loads_T_3, UInt<1>(0h0))
node ex_is_waiting_for_loads = and(_ex_is_waiting_for_loads_T_1, _ex_is_waiting_for_loads_T_4)
node _ld_bias_io_wait_for_prev_loop_T = neq(ld_bias.io.loop_id, ex.io.loop_id)
node _ld_bias_io_wait_for_prev_loop_T_1 = and(ex_is_waiting_for_loads, _ld_bias_io_wait_for_prev_loop_T)
connect ld_bias.io.wait_for_prev_loop, _ld_bias_io_wait_for_prev_loop_T_1
node _ld_weights_io_wait_for_prev_loop_T = neq(ld_weights.io.loop_id, ex.io.loop_id)
node _ld_weights_io_wait_for_prev_loop_T_1 = and(ex_is_waiting_for_loads, _ld_weights_io_wait_for_prev_loop_T)
connect ld_weights.io.wait_for_prev_loop, _ld_weights_io_wait_for_prev_loop_T_1
node _ld_input_io_wait_for_prev_loop_T = neq(ld_input.io.loop_id, ex.io.loop_id)
node _ld_input_io_wait_for_prev_loop_T_1 = and(ex_is_waiting_for_loads, _ld_input_io_wait_for_prev_loop_T)
connect ld_input.io.wait_for_prev_loop, _ld_input_io_wait_for_prev_loop_T_1
node _ld_bias_io_rob_overloaded_T = geq(ld_utilization, UInt<4>(0h8))
connect ld_bias.io.rob_overloaded, _ld_bias_io_rob_overloaded_T
node _ld_input_io_rob_overloaded_T = geq(ld_utilization, UInt<4>(0h8))
connect ld_input.io.rob_overloaded, _ld_input_io_rob_overloaded_T
node _ld_weights_io_rob_overloaded_T = geq(ld_utilization, UInt<4>(0h8))
connect ld_weights.io.rob_overloaded, _ld_weights_io_rob_overloaded_T
node _ex_io_rob_overloaded_T = geq(ex_utilization, UInt<5>(0h10))
connect ex.io.rob_overloaded, _ex_io_rob_overloaded_T
node _st_io_rob_overloaded_T = geq(st_utilization, UInt<3>(0h4))
connect st.io.rob_overloaded, _st_io_rob_overloaded_T
node _ex_io_lda_completed_T = neq(ld_input.io.loop_id, ex.io.loop_id)
node _ex_io_lda_completed_T_1 = or(_ex_io_lda_completed_T, ld_input.io.idle)
connect ex.io.lda_completed, _ex_io_lda_completed_T_1
node _ex_io_ldb_completed_T = neq(ld_weights.io.loop_id, ex.io.loop_id)
node _ex_io_ldb_completed_T_1 = or(_ex_io_ldb_completed_T, ld_weights.io.idle)
connect ex.io.ldb_completed, _ex_io_ldb_completed_T_1
node _ex_io_ldd_completed_T = neq(ld_bias.io.loop_id, ex.io.loop_id)
node _ex_io_ldd_completed_T_1 = or(_ex_io_ldd_completed_T, ld_bias.io.idle)
connect ex.io.ldd_completed, _ex_io_ldd_completed_T_1
node _st_io_ex_completed_T = neq(ex.io.loop_id, st.io.loop_id)
node _st_io_ex_completed_T_1 = or(_st_io_ex_completed_T, ex.io.idle)
connect st.io.ex_completed, _st_io_ex_completed_T_1
node _T_12 = and(cmd_q.io.deq.valid, is_loop_cmd)
node _T_13 = eq(loops[loop_being_configured_id].configured, UInt<1>(0h0))
node _T_14 = and(_T_12, _T_13)
when _T_14 :
node _T_15 = eq(UInt<5>(0h10), cmd_q.io.deq.bits.cmd.inst.funct)
when _T_15 :
node _loops_outer_bounds_out_channels_T = bits(cmd_q.io.deq.bits.cmd.rs1, 63, 48)
connect loops[loop_being_configured_id].outer_bounds.out_channels, _loops_outer_bounds_out_channels_T
node _loops_outer_bounds_in_channels_T = bits(cmd_q.io.deq.bits.cmd.rs1, 47, 32)
connect loops[loop_being_configured_id].outer_bounds.in_channels, _loops_outer_bounds_in_channels_T
node _loops_outer_bounds_in_row_dim_T = bits(cmd_q.io.deq.bits.cmd.rs1, 31, 16)
connect loops[loop_being_configured_id].outer_bounds.in_row_dim, _loops_outer_bounds_in_row_dim_T
node _loops_outer_bounds_batch_size_T = bits(cmd_q.io.deq.bits.cmd.rs1, 15, 0)
connect loops[loop_being_configured_id].outer_bounds.batch_size, _loops_outer_bounds_batch_size_T
node _loops_outer_bounds_padding_T = bits(cmd_q.io.deq.bits.cmd.rs2, 63, 56)
connect loops[loop_being_configured_id].outer_bounds.padding, _loops_outer_bounds_padding_T
node _loops_outer_bounds_stride_T = bits(cmd_q.io.deq.bits.cmd.rs2, 55, 48)
connect loops[loop_being_configured_id].outer_bounds.stride, _loops_outer_bounds_stride_T
node _loops_outer_bounds_out_col_dim_T = bits(cmd_q.io.deq.bits.cmd.rs2, 47, 32)
connect loops[loop_being_configured_id].outer_bounds.out_col_dim, _loops_outer_bounds_out_col_dim_T
node _loops_outer_bounds_pool_out_row_dim_T = bits(cmd_q.io.deq.bits.cmd.rs2, 31, 16)
connect loops[loop_being_configured_id].outer_bounds.pool_out_row_dim, _loops_outer_bounds_pool_out_row_dim_T
node _loops_outer_bounds_out_row_dim_T = bits(cmd_q.io.deq.bits.cmd.rs2, 15, 0)
connect loops[loop_being_configured_id].outer_bounds.out_row_dim, _loops_outer_bounds_out_row_dim_T
else :
node _T_16 = eq(UInt<5>(0h11), cmd_q.io.deq.bits.cmd.inst.funct)
when _T_16 :
node _loops_outer_bounds_kernel_dim_T = bits(cmd_q.io.deq.bits.cmd.rs1, 63, 48)
connect loops[loop_being_configured_id].outer_bounds.kernel_dim, _loops_outer_bounds_kernel_dim_T
node _loops_outer_bounds_pool_out_col_dim_T = bits(cmd_q.io.deq.bits.cmd.rs1, 47, 32)
connect loops[loop_being_configured_id].outer_bounds.pool_out_col_dim, _loops_outer_bounds_pool_out_col_dim_T
node _loops_outer_bounds_pool_size_T = bits(cmd_q.io.deq.bits.cmd.rs1, 31, 16)
connect loops[loop_being_configured_id].outer_bounds.pool_size, _loops_outer_bounds_pool_size_T
node _loops_outer_bounds_pool_stride_T = bits(cmd_q.io.deq.bits.cmd.rs1, 15, 8)
connect loops[loop_being_configured_id].outer_bounds.pool_stride, _loops_outer_bounds_pool_stride_T
node _loops_outer_bounds_pool_padding_T = bits(cmd_q.io.deq.bits.cmd.rs1, 7, 0)
connect loops[loop_being_configured_id].outer_bounds.pool_padding, _loops_outer_bounds_pool_padding_T
node _loops_inner_bounds_batches_T = bits(cmd_q.io.deq.bits.cmd.rs2, 63, 48)
connect loops[loop_being_configured_id].inner_bounds.batches, _loops_inner_bounds_batches_T
node _loops_inner_bounds_porows_T = bits(cmd_q.io.deq.bits.cmd.rs2, 47, 32)
connect loops[loop_being_configured_id].inner_bounds.porows, _loops_inner_bounds_porows_T
node _loops_inner_bounds_pocols_T = bits(cmd_q.io.deq.bits.cmd.rs2, 31, 16)
connect loops[loop_being_configured_id].inner_bounds.pocols, _loops_inner_bounds_pocols_T
node _loops_inner_bounds_pochs_T = bits(cmd_q.io.deq.bits.cmd.rs2, 15, 0)
connect loops[loop_being_configured_id].inner_bounds.pochs, _loops_inner_bounds_pochs_T
else :
node _T_17 = eq(UInt<5>(0h12), cmd_q.io.deq.bits.cmd.inst.funct)
when _T_17 :
node _loops_inner_bounds_krows_T = bits(cmd_q.io.deq.bits.cmd.rs1, 63, 48)
connect loops[loop_being_configured_id].inner_bounds.krows, _loops_inner_bounds_krows_T
node _loops_inner_bounds_kcols_T = bits(cmd_q.io.deq.bits.cmd.rs1, 47, 32)
connect loops[loop_being_configured_id].inner_bounds.kcols, _loops_inner_bounds_kcols_T
node _loops_inner_bounds_kchs_T = bits(cmd_q.io.deq.bits.cmd.rs1, 31, 16)
connect loops[loop_being_configured_id].inner_bounds.kchs, _loops_inner_bounds_kchs_T
node _loops_inner_bounds_lpad_T = bits(cmd_q.io.deq.bits.cmd.rs1, 15, 0)
connect loops[loop_being_configured_id].inner_bounds.lpad, _loops_inner_bounds_lpad_T
node _loops_inner_bounds_rpad_T = bits(cmd_q.io.deq.bits.cmd.rs2, 63, 48)
connect loops[loop_being_configured_id].inner_bounds.rpad, _loops_inner_bounds_rpad_T
node _loops_inner_bounds_upad_T = bits(cmd_q.io.deq.bits.cmd.rs2, 47, 32)
connect loops[loop_being_configured_id].inner_bounds.upad, _loops_inner_bounds_upad_T
node _loops_inner_bounds_dpad_T = bits(cmd_q.io.deq.bits.cmd.rs2, 31, 24)
connect loops[loop_being_configured_id].inner_bounds.dpad, _loops_inner_bounds_dpad_T
node _loops_inner_bounds_plpad_T = bits(cmd_q.io.deq.bits.cmd.rs2, 23, 16)
connect loops[loop_being_configured_id].inner_bounds.plpad, _loops_inner_bounds_plpad_T
node _loops_outer_bounds_in_col_dim_T = bits(cmd_q.io.deq.bits.cmd.rs2, 15, 0)
connect loops[loop_being_configured_id].outer_bounds.in_col_dim, _loops_outer_bounds_in_col_dim_T
else :
node _T_18 = eq(UInt<5>(0h13), cmd_q.io.deq.bits.cmd.inst.funct)
when _T_18 :
node _loops_inner_bounds_orows_T = bits(cmd_q.io.deq.bits.cmd.rs1, 63, 48)
connect loops[loop_being_configured_id].inner_bounds.orows, _loops_inner_bounds_orows_T
node _loops_inner_bounds_prad_T = bits(cmd_q.io.deq.bits.cmd.rs1, 47, 32)
connect loops[loop_being_configured_id].inner_bounds.prad, _loops_inner_bounds_prad_T
node _loops_inner_bounds_pupad_T = bits(cmd_q.io.deq.bits.cmd.rs1, 31, 21)
connect loops[loop_being_configured_id].inner_bounds.pupad, _loops_inner_bounds_pupad_T
node _loops_inner_bounds_pdpad_T = bits(cmd_q.io.deq.bits.cmd.rs1, 20, 10)
connect loops[loop_being_configured_id].inner_bounds.pdpad, _loops_inner_bounds_pdpad_T
node _loops_outer_bounds_kernel_dilation_T = bits(cmd_q.io.deq.bits.cmd.rs1, 9, 0)
connect loops[loop_being_configured_id].outer_bounds.kernel_dilation, _loops_outer_bounds_kernel_dilation_T
node _loops_inner_bounds_ocols_T = bits(cmd_q.io.deq.bits.cmd.rs2, 15, 0)
connect loops[loop_being_configured_id].inner_bounds.ocols, _loops_inner_bounds_ocols_T
node _loops_outer_bounds_in_stride_T = bits(cmd_q.io.deq.bits.cmd.rs2, 63, 48)
connect loops[loop_being_configured_id].outer_bounds.in_stride, _loops_outer_bounds_in_stride_T
node _loops_outer_bounds_weight_stride_T = bits(cmd_q.io.deq.bits.cmd.rs2, 47, 32)
connect loops[loop_being_configured_id].outer_bounds.weight_stride, _loops_outer_bounds_weight_stride_T
node _loops_outer_bounds_out_stride_T = bits(cmd_q.io.deq.bits.cmd.rs2, 31, 16)
connect loops[loop_being_configured_id].outer_bounds.out_stride, _loops_outer_bounds_out_stride_T
else :
node _T_19 = eq(UInt<5>(0h14), cmd_q.io.deq.bits.cmd.inst.funct)
when _T_19 :
connect loops[loop_being_configured_id].weights_dram_addr, cmd_q.io.deq.bits.cmd.rs1
connect loops[loop_being_configured_id].output_dram_addr, cmd_q.io.deq.bits.cmd.rs2
else :
node _T_20 = eq(UInt<5>(0h15), cmd_q.io.deq.bits.cmd.inst.funct)
when _T_20 :
connect loops[loop_being_configured_id].bias_dram_addr, cmd_q.io.deq.bits.cmd.rs1
connect loops[loop_being_configured_id].input_dram_addr, cmd_q.io.deq.bits.cmd.rs2
else :
node _T_21 = eq(UInt<4>(0hf), cmd_q.io.deq.bits.cmd.inst.funct)
when _T_21 :
node _loops_no_bias_T = bits(cmd_q.io.deq.bits.cmd.rs1, 0, 0)
connect loops[loop_being_configured_id].no_bias, _loops_no_bias_T
node config_max_pixels_per_row = bits(cmd_q.io.deq.bits.cmd.rs1, 15, 8)
node _loops_max_pixels_per_row_T = eq(UInt<1>(0h1), UInt<1>(0h0))
node _loops_max_pixels_per_row_T_1 = eq(config_max_pixels_per_row, UInt<1>(0h0))
node _loops_max_pixels_per_row_T_2 = or(_loops_max_pixels_per_row_T, _loops_max_pixels_per_row_T_1)
node _loops_max_pixels_per_row_T_3 = mux(_loops_max_pixels_per_row_T_2, UInt<1>(0h1), config_max_pixels_per_row)
connect loops[loop_being_configured_id].max_pixels_per_row, _loops_max_pixels_per_row_T_3
node _loops_a_ex_spad_id_T = bits(cmd_q.io.deq.bits.cmd.rs1, 19, 18)
connect loops[loop_being_configured_id].a_ex_spad_id, _loops_a_ex_spad_id_T
node _loops_b_ex_spad_id_T = bits(cmd_q.io.deq.bits.cmd.rs1, 17, 16)
connect loops[loop_being_configured_id].b_ex_spad_id, _loops_b_ex_spad_id_T
node _loops_wrot180_T = bits(cmd_q.io.deq.bits.cmd.rs1, 1, 1)
node _loops_wrot180_T_1 = and(UInt<1>(0h0), _loops_wrot180_T)
connect loops[loop_being_configured_id].wrot180, _loops_wrot180_T_1
node _loops_input_dilated_T = bits(cmd_q.io.deq.bits.cmd.rs2, 2, 2)
node _loops_input_dilated_T_1 = and(UInt<1>(0h0), _loops_input_dilated_T)
connect loops[loop_being_configured_id].input_dilated, _loops_input_dilated_T_1
node _loops_trans_output_1203_T = bits(cmd_q.io.deq.bits.cmd.rs1, 2, 2)
node _loops_trans_output_1203_T_1 = and(UInt<1>(0h0), _loops_trans_output_1203_T)
connect loops[loop_being_configured_id].trans_output_1203, _loops_trans_output_1203_T_1
node _loops_trans_weight_1203_T = bits(cmd_q.io.deq.bits.cmd.rs1, 3, 3)
node _loops_trans_weight_1203_T_1 = and(UInt<1>(0h0), _loops_trans_weight_1203_T)
connect loops[loop_being_configured_id].trans_weight_1203, _loops_trans_weight_1203_T_1
node _loops_trans_weight_0132_T = bits(cmd_q.io.deq.bits.cmd.rs1, 4, 4)
node _loops_trans_weight_0132_T_1 = and(UInt<1>(0h0), _loops_trans_weight_0132_T)
connect loops[loop_being_configured_id].trans_weight_0132, _loops_trans_weight_0132_T_1
node _loops_trans_input_3120_T = bits(cmd_q.io.deq.bits.cmd.rs1, 5, 5)
node _loops_trans_input_3120_T_1 = and(UInt<1>(0h0), _loops_trans_input_3120_T)
connect loops[loop_being_configured_id].trans_input_3120, _loops_trans_input_3120_T_1
node _loops_dw_T = bits(cmd_q.io.deq.bits.cmd.rs1, 6, 6)
node _loops_dw_T_1 = and(UInt<1>(0h1), _loops_dw_T)
connect loops[loop_being_configured_id].dw, _loops_dw_T_1
node _loops_no_pool_T = eq(UInt<1>(0h1), UInt<1>(0h0))
node _loops_no_pool_T_1 = bits(cmd_q.io.deq.bits.cmd.rs2, 0, 0)
node _loops_no_pool_T_2 = or(_loops_no_pool_T, _loops_no_pool_T_1)
connect loops[loop_being_configured_id].no_pool, _loops_no_pool_T_2
node _loops_activation_T = bits(cmd_q.io.deq.bits.cmd.rs2, 4, 3)
connect loops[loop_being_configured_id].activation, _loops_activation_T
node _loops_downsample_T = bits(cmd_q.io.deq.bits.cmd.rs2, 1, 1)
connect loops[loop_being_configured_id].downsample, _loops_downsample_T
connect loops[loop_being_configured_id].configured, UInt<1>(0h1)
regreset ld_bias_addr_start : UInt<12>, clock, reset, UInt<12>(0h0)
regreset ex_c_addr_start : UInt<12>, clock, reset, UInt<12>(0h0)
regreset st_addr_start : UInt<12>, clock, reset, UInt<12>(0h0)
node loop_requesting_ld_bias_id = mux(loops[head_loop_id].ld_bias_started, tail_loop_id, head_loop_id)
connect ld_bias.io.req.bits.outer_bounds.pool_padding, loops[loop_requesting_ld_bias_id].outer_bounds.pool_padding
connect ld_bias.io.req.bits.outer_bounds.pool_stride, loops[loop_requesting_ld_bias_id].outer_bounds.pool_stride
connect ld_bias.io.req.bits.outer_bounds.pool_size, loops[loop_requesting_ld_bias_id].outer_bounds.pool_size
connect ld_bias.io.req.bits.outer_bounds.kernel_dilation, loops[loop_requesting_ld_bias_id].outer_bounds.kernel_dilation
connect ld_bias.io.req.bits.outer_bounds.kernel_dim, loops[loop_requesting_ld_bias_id].outer_bounds.kernel_dim
connect ld_bias.io.req.bits.outer_bounds.padding, loops[loop_requesting_ld_bias_id].outer_bounds.padding
connect ld_bias.io.req.bits.outer_bounds.stride, loops[loop_requesting_ld_bias_id].outer_bounds.stride
connect ld_bias.io.req.bits.outer_bounds.pool_out_col_dim, loops[loop_requesting_ld_bias_id].outer_bounds.pool_out_col_dim
connect ld_bias.io.req.bits.outer_bounds.pool_out_row_dim, loops[loop_requesting_ld_bias_id].outer_bounds.pool_out_row_dim
connect ld_bias.io.req.bits.outer_bounds.weight_stride, loops[loop_requesting_ld_bias_id].outer_bounds.weight_stride
connect ld_bias.io.req.bits.outer_bounds.in_stride, loops[loop_requesting_ld_bias_id].outer_bounds.in_stride
connect ld_bias.io.req.bits.outer_bounds.out_stride, loops[loop_requesting_ld_bias_id].outer_bounds.out_stride
connect ld_bias.io.req.bits.outer_bounds.out_row_dim, loops[loop_requesting_ld_bias_id].outer_bounds.out_row_dim
connect ld_bias.io.req.bits.outer_bounds.out_col_dim, loops[loop_requesting_ld_bias_id].outer_bounds.out_col_dim
connect ld_bias.io.req.bits.outer_bounds.out_channels, loops[loop_requesting_ld_bias_id].outer_bounds.out_channels
connect ld_bias.io.req.bits.outer_bounds.in_channels, loops[loop_requesting_ld_bias_id].outer_bounds.in_channels
connect ld_bias.io.req.bits.outer_bounds.in_col_dim, loops[loop_requesting_ld_bias_id].outer_bounds.in_col_dim
connect ld_bias.io.req.bits.outer_bounds.in_row_dim, loops[loop_requesting_ld_bias_id].outer_bounds.in_row_dim
connect ld_bias.io.req.bits.outer_bounds.batch_size, loops[loop_requesting_ld_bias_id].outer_bounds.batch_size
connect ld_bias.io.req.bits.inner_bounds.ocols, loops[loop_requesting_ld_bias_id].inner_bounds.ocols
connect ld_bias.io.req.bits.inner_bounds.orows, loops[loop_requesting_ld_bias_id].inner_bounds.orows
connect ld_bias.io.req.bits.inner_bounds.pdpad, loops[loop_requesting_ld_bias_id].inner_bounds.pdpad
connect ld_bias.io.req.bits.inner_bounds.pupad, loops[loop_requesting_ld_bias_id].inner_bounds.pupad
connect ld_bias.io.req.bits.inner_bounds.prad, loops[loop_requesting_ld_bias_id].inner_bounds.prad
connect ld_bias.io.req.bits.inner_bounds.plpad, loops[loop_requesting_ld_bias_id].inner_bounds.plpad
connect ld_bias.io.req.bits.inner_bounds.dpad, loops[loop_requesting_ld_bias_id].inner_bounds.dpad
connect ld_bias.io.req.bits.inner_bounds.upad, loops[loop_requesting_ld_bias_id].inner_bounds.upad
connect ld_bias.io.req.bits.inner_bounds.rpad, loops[loop_requesting_ld_bias_id].inner_bounds.rpad
connect ld_bias.io.req.bits.inner_bounds.lpad, loops[loop_requesting_ld_bias_id].inner_bounds.lpad
connect ld_bias.io.req.bits.inner_bounds.kchs, loops[loop_requesting_ld_bias_id].inner_bounds.kchs
connect ld_bias.io.req.bits.inner_bounds.kcols, loops[loop_requesting_ld_bias_id].inner_bounds.kcols
connect ld_bias.io.req.bits.inner_bounds.krows, loops[loop_requesting_ld_bias_id].inner_bounds.krows
connect ld_bias.io.req.bits.inner_bounds.pochs, loops[loop_requesting_ld_bias_id].inner_bounds.pochs
connect ld_bias.io.req.bits.inner_bounds.pocols, loops[loop_requesting_ld_bias_id].inner_bounds.pocols
connect ld_bias.io.req.bits.inner_bounds.porows, loops[loop_requesting_ld_bias_id].inner_bounds.porows
connect ld_bias.io.req.bits.inner_bounds.batches, loops[loop_requesting_ld_bias_id].inner_bounds.batches
wire ld_bias_io_req_bits_derived_params_result : { ochs : UInt<16>, irows : UInt<16>, icols : UInt<16>, irows_unpadded : UInt<16>, icols_unpadded : UInt<16>, ichs : UInt<16>, out_channels_per_bank : UInt<16>, in_channels_per_bank : UInt<16>, bias_spad_stride : UInt<16>, input_spad_stride : UInt<16>, weight_spad_stride : UInt<16>}
connect ld_bias_io_req_bits_derived_params_result.ochs, loops[loop_requesting_ld_bias_id].inner_bounds.pochs
node _ld_bias_io_req_bits_derived_params_dilated_krows_T = sub(loops[loop_requesting_ld_bias_id].outer_bounds.kernel_dilation, UInt<1>(0h1))
node _ld_bias_io_req_bits_derived_params_dilated_krows_T_1 = tail(_ld_bias_io_req_bits_derived_params_dilated_krows_T, 1)
node _ld_bias_io_req_bits_derived_params_dilated_krows_T_2 = sub(loops[loop_requesting_ld_bias_id].inner_bounds.krows, UInt<1>(0h1))
node _ld_bias_io_req_bits_derived_params_dilated_krows_T_3 = tail(_ld_bias_io_req_bits_derived_params_dilated_krows_T_2, 1)
node _ld_bias_io_req_bits_derived_params_dilated_krows_T_4 = mul(_ld_bias_io_req_bits_derived_params_dilated_krows_T_1, _ld_bias_io_req_bits_derived_params_dilated_krows_T_3)
node _ld_bias_io_req_bits_derived_params_dilated_krows_T_5 = add(loops[loop_requesting_ld_bias_id].inner_bounds.krows, _ld_bias_io_req_bits_derived_params_dilated_krows_T_4)
node ld_bias_io_req_bits_derived_params_dilated_krows = tail(_ld_bias_io_req_bits_derived_params_dilated_krows_T_5, 1)
node _ld_bias_io_req_bits_derived_params_dilated_kcols_T = sub(loops[loop_requesting_ld_bias_id].outer_bounds.kernel_dilation, UInt<1>(0h1))
node _ld_bias_io_req_bits_derived_params_dilated_kcols_T_1 = tail(_ld_bias_io_req_bits_derived_params_dilated_kcols_T, 1)
node _ld_bias_io_req_bits_derived_params_dilated_kcols_T_2 = sub(loops[loop_requesting_ld_bias_id].inner_bounds.kcols, UInt<1>(0h1))
node _ld_bias_io_req_bits_derived_params_dilated_kcols_T_3 = tail(_ld_bias_io_req_bits_derived_params_dilated_kcols_T_2, 1)
node _ld_bias_io_req_bits_derived_params_dilated_kcols_T_4 = mul(_ld_bias_io_req_bits_derived_params_dilated_kcols_T_1, _ld_bias_io_req_bits_derived_params_dilated_kcols_T_3)
node _ld_bias_io_req_bits_derived_params_dilated_kcols_T_5 = add(loops[loop_requesting_ld_bias_id].inner_bounds.kcols, _ld_bias_io_req_bits_derived_params_dilated_kcols_T_4)
node ld_bias_io_req_bits_derived_params_dilated_kcols = tail(_ld_bias_io_req_bits_derived_params_dilated_kcols_T_5, 1)
node _ld_bias_io_req_bits_derived_params_irows_without_dilation_T = mul(loops[loop_requesting_ld_bias_id].inner_bounds.orows, loops[loop_requesting_ld_bias_id].outer_bounds.stride)
node _ld_bias_io_req_bits_derived_params_irows_without_dilation_T_1 = add(_ld_bias_io_req_bits_derived_params_irows_without_dilation_T, ld_bias_io_req_bits_derived_params_dilated_krows)
node _ld_bias_io_req_bits_derived_params_irows_without_dilation_T_2 = sub(_ld_bias_io_req_bits_derived_params_irows_without_dilation_T_1, UInt<1>(0h1))
node ld_bias_io_req_bits_derived_params_irows_without_dilation = asUInt(_ld_bias_io_req_bits_derived_params_irows_without_dilation_T_2)
node _ld_bias_io_req_bits_derived_params_icols_without_dilation_T = mul(loops[loop_requesting_ld_bias_id].inner_bounds.ocols, loops[loop_requesting_ld_bias_id].outer_bounds.stride)
node _ld_bias_io_req_bits_derived_params_icols_without_dilation_T_1 = add(_ld_bias_io_req_bits_derived_params_icols_without_dilation_T, ld_bias_io_req_bits_derived_params_dilated_kcols)
node _ld_bias_io_req_bits_derived_params_icols_without_dilation_T_2 = sub(_ld_bias_io_req_bits_derived_params_icols_without_dilation_T_1, UInt<1>(0h1))
node ld_bias_io_req_bits_derived_params_icols_without_dilation = asUInt(_ld_bias_io_req_bits_derived_params_icols_without_dilation_T_2)
node _ld_bias_io_req_bits_derived_params_irows_unpadded_without_dilation_T = sub(ld_bias_io_req_bits_derived_params_irows_without_dilation, loops[loop_requesting_ld_bias_id].inner_bounds.upad)
node _ld_bias_io_req_bits_derived_params_irows_unpadded_without_dilation_T_1 = asUInt(_ld_bias_io_req_bits_derived_params_irows_unpadded_without_dilation_T)
node _ld_bias_io_req_bits_derived_params_irows_unpadded_without_dilation_T_2 = sub(_ld_bias_io_req_bits_derived_params_irows_unpadded_without_dilation_T_1, loops[loop_requesting_ld_bias_id].inner_bounds.dpad)
node ld_bias_io_req_bits_derived_params_irows_unpadded_without_dilation = asUInt(_ld_bias_io_req_bits_derived_params_irows_unpadded_without_dilation_T_2)
node _ld_bias_io_req_bits_derived_params_icols_unpadded_without_dilation_T = sub(ld_bias_io_req_bits_derived_params_icols_without_dilation, loops[loop_requesting_ld_bias_id].inner_bounds.lpad)
node _ld_bias_io_req_bits_derived_params_icols_unpadded_without_dilation_T_1 = asUInt(_ld_bias_io_req_bits_derived_params_icols_unpadded_without_dilation_T)
node _ld_bias_io_req_bits_derived_params_icols_unpadded_without_dilation_T_2 = sub(_ld_bias_io_req_bits_derived_params_icols_unpadded_without_dilation_T_1, loops[loop_requesting_ld_bias_id].inner_bounds.rpad)
node ld_bias_io_req_bits_derived_params_icols_unpadded_without_dilation = asUInt(_ld_bias_io_req_bits_derived_params_icols_unpadded_without_dilation_T_2)
node _ld_bias_io_req_bits_derived_params_irows_unpadded_T = add(ld_bias_io_req_bits_derived_params_irows_unpadded_without_dilation, loops[loop_requesting_ld_bias_id].input_dilated)
node ld_bias_io_req_bits_derived_params_irows_unpadded = dshr(_ld_bias_io_req_bits_derived_params_irows_unpadded_T, loops[loop_requesting_ld_bias_id].input_dilated)
node _ld_bias_io_req_bits_derived_params_icols_unpadded_T = add(ld_bias_io_req_bits_derived_params_icols_unpadded_without_dilation, loops[loop_requesting_ld_bias_id].input_dilated)
node ld_bias_io_req_bits_derived_params_icols_unpadded = dshr(_ld_bias_io_req_bits_derived_params_icols_unpadded_T, loops[loop_requesting_ld_bias_id].input_dilated)
node _ld_bias_io_req_bits_derived_params_result_irows_T = add(loops[loop_requesting_ld_bias_id].inner_bounds.upad, loops[loop_requesting_ld_bias_id].input_dilated)
node _ld_bias_io_req_bits_derived_params_result_irows_T_1 = dshr(_ld_bias_io_req_bits_derived_params_result_irows_T, loops[loop_requesting_ld_bias_id].input_dilated)
node _ld_bias_io_req_bits_derived_params_result_irows_T_2 = add(ld_bias_io_req_bits_derived_params_irows_unpadded, _ld_bias_io_req_bits_derived_params_result_irows_T_1)
node _ld_bias_io_req_bits_derived_params_result_irows_T_3 = add(loops[loop_requesting_ld_bias_id].inner_bounds.dpad, loops[loop_requesting_ld_bias_id].input_dilated)
node _ld_bias_io_req_bits_derived_params_result_irows_T_4 = dshr(_ld_bias_io_req_bits_derived_params_result_irows_T_3, loops[loop_requesting_ld_bias_id].input_dilated)
node _ld_bias_io_req_bits_derived_params_result_irows_T_5 = add(_ld_bias_io_req_bits_derived_params_result_irows_T_2, _ld_bias_io_req_bits_derived_params_result_irows_T_4)
node _ld_bias_io_req_bits_derived_params_result_irows_T_6 = mux(loops[loop_requesting_ld_bias_id].input_dilated, _ld_bias_io_req_bits_derived_params_result_irows_T_5, ld_bias_io_req_bits_derived_params_irows_without_dilation)
connect ld_bias_io_req_bits_derived_params_result.irows, _ld_bias_io_req_bits_derived_params_result_irows_T_6
node _ld_bias_io_req_bits_derived_params_result_icols_T = add(loops[loop_requesting_ld_bias_id].inner_bounds.lpad, loops[loop_requesting_ld_bias_id].input_dilated)
node _ld_bias_io_req_bits_derived_params_result_icols_T_1 = dshr(_ld_bias_io_req_bits_derived_params_result_icols_T, loops[loop_requesting_ld_bias_id].input_dilated)
node _ld_bias_io_req_bits_derived_params_result_icols_T_2 = add(ld_bias_io_req_bits_derived_params_icols_unpadded, _ld_bias_io_req_bits_derived_params_result_icols_T_1)
node _ld_bias_io_req_bits_derived_params_result_icols_T_3 = add(loops[loop_requesting_ld_bias_id].inner_bounds.rpad, loops[loop_requesting_ld_bias_id].input_dilated)
node _ld_bias_io_req_bits_derived_params_result_icols_T_4 = dshr(_ld_bias_io_req_bits_derived_params_result_icols_T_3, loops[loop_requesting_ld_bias_id].input_dilated)
node _ld_bias_io_req_bits_derived_params_result_icols_T_5 = add(_ld_bias_io_req_bits_derived_params_result_icols_T_2, _ld_bias_io_req_bits_derived_params_result_icols_T_4)
node _ld_bias_io_req_bits_derived_params_result_icols_T_6 = mux(loops[loop_requesting_ld_bias_id].input_dilated, _ld_bias_io_req_bits_derived_params_result_icols_T_5, ld_bias_io_req_bits_derived_params_icols_without_dilation)
connect ld_bias_io_req_bits_derived_params_result.icols, _ld_bias_io_req_bits_derived_params_result_icols_T_6
connect ld_bias_io_req_bits_derived_params_result.irows_unpadded, ld_bias_io_req_bits_derived_params_irows_unpadded
connect ld_bias_io_req_bits_derived_params_result.icols_unpadded, ld_bias_io_req_bits_derived_params_icols_unpadded
connect ld_bias_io_req_bits_derived_params_result.ichs, loops[loop_requesting_ld_bias_id].inner_bounds.kchs
node _ld_bias_io_req_bits_derived_params_result_out_channels_per_bank_T = div(ld_bias_io_req_bits_derived_params_result.ochs, UInt<16>(0h4))
node _ld_bias_io_req_bits_derived_params_result_out_channels_per_bank_T_1 = rem(ld_bias_io_req_bits_derived_params_result.ochs, UInt<3>(0h4))
node _ld_bias_io_req_bits_derived_params_result_out_channels_per_bank_T_2 = neq(_ld_bias_io_req_bits_derived_params_result_out_channels_per_bank_T_1, UInt<1>(0h0))
node _ld_bias_io_req_bits_derived_params_result_out_channels_per_bank_T_3 = add(_ld_bias_io_req_bits_derived_params_result_out_channels_per_bank_T, _ld_bias_io_req_bits_derived_params_result_out_channels_per_bank_T_2)
connect ld_bias_io_req_bits_derived_params_result.out_channels_per_bank, _ld_bias_io_req_bits_derived_params_result_out_channels_per_bank_T_3
node _ld_bias_io_req_bits_derived_params_result_in_channels_per_bank_T = div(ld_bias_io_req_bits_derived_params_result.ichs, UInt<16>(0h4))
node _ld_bias_io_req_bits_derived_params_result_in_channels_per_bank_T_1 = rem(ld_bias_io_req_bits_derived_params_result.ichs, UInt<3>(0h4))
node _ld_bias_io_req_bits_derived_params_result_in_channels_per_bank_T_2 = neq(_ld_bias_io_req_bits_derived_params_result_in_channels_per_bank_T_1, UInt<1>(0h0))
node _ld_bias_io_req_bits_derived_params_result_in_channels_per_bank_T_3 = add(_ld_bias_io_req_bits_derived_params_result_in_channels_per_bank_T, _ld_bias_io_req_bits_derived_params_result_in_channels_per_bank_T_2)
connect ld_bias_io_req_bits_derived_params_result.in_channels_per_bank, _ld_bias_io_req_bits_derived_params_result_in_channels_per_bank_T_3
node _ld_bias_io_req_bits_derived_params_result_bias_spad_stride_T = mul(loops[loop_requesting_ld_bias_id].inner_bounds.batches, loops[loop_requesting_ld_bias_id].inner_bounds.orows)
node _ld_bias_io_req_bits_derived_params_result_bias_spad_stride_T_1 = mul(_ld_bias_io_req_bits_derived_params_result_bias_spad_stride_T, loops[loop_requesting_ld_bias_id].inner_bounds.ocols)
connect ld_bias_io_req_bits_derived_params_result.bias_spad_stride, _ld_bias_io_req_bits_derived_params_result_bias_spad_stride_T_1
node _ld_bias_io_req_bits_derived_params_result_input_spad_stride_T = dshr(ld_bias_io_req_bits_derived_params_result.irows, loops[loop_requesting_ld_bias_id].downsample)
node _ld_bias_io_req_bits_derived_params_result_input_spad_stride_T_1 = mul(ld_bias_io_req_bits_derived_params_result.ichs, _ld_bias_io_req_bits_derived_params_result_input_spad_stride_T)
node _ld_bias_io_req_bits_derived_params_result_input_spad_stride_T_2 = dshr(ld_bias_io_req_bits_derived_params_result.icols, loops[loop_requesting_ld_bias_id].downsample)
node _ld_bias_io_req_bits_derived_params_result_input_spad_stride_T_3 = mul(_ld_bias_io_req_bits_derived_params_result_input_spad_stride_T_1, _ld_bias_io_req_bits_derived_params_result_input_spad_stride_T_2)
node _ld_bias_io_req_bits_derived_params_result_input_spad_stride_T_4 = dshr(ld_bias_io_req_bits_derived_params_result.irows, loops[loop_requesting_ld_bias_id].downsample)
node _ld_bias_io_req_bits_derived_params_result_input_spad_stride_T_5 = mul(loops[loop_requesting_ld_bias_id].inner_bounds.batches, _ld_bias_io_req_bits_derived_params_result_input_spad_stride_T_4)
node _ld_bias_io_req_bits_derived_params_result_input_spad_stride_T_6 = dshr(ld_bias_io_req_bits_derived_params_result.icols, loops[loop_requesting_ld_bias_id].downsample)
node _ld_bias_io_req_bits_derived_params_result_input_spad_stride_T_7 = mul(_ld_bias_io_req_bits_derived_params_result_input_spad_stride_T_5, _ld_bias_io_req_bits_derived_params_result_input_spad_stride_T_6)
node _ld_bias_io_req_bits_derived_params_result_input_spad_stride_T_8 = mux(loops[loop_requesting_ld_bias_id].trans_input_3120, _ld_bias_io_req_bits_derived_params_result_input_spad_stride_T_3, _ld_bias_io_req_bits_derived_params_result_input_spad_stride_T_7)
connect ld_bias_io_req_bits_derived_params_result.input_spad_stride, _ld_bias_io_req_bits_derived_params_result_input_spad_stride_T_8
node _ld_bias_io_req_bits_derived_params_result_weight_spad_stride_T = mul(loops[loop_requesting_ld_bias_id].inner_bounds.krows, loops[loop_requesting_ld_bias_id].inner_bounds.kcols)
node _ld_bias_io_req_bits_derived_params_result_weight_spad_stride_T_1 = mul(_ld_bias_io_req_bits_derived_params_result_weight_spad_stride_T, loops[loop_requesting_ld_bias_id].inner_bounds.pochs)
node _ld_bias_io_req_bits_derived_params_result_weight_spad_stride_T_2 = mul(loops[loop_requesting_ld_bias_id].inner_bounds.krows, loops[loop_requesting_ld_bias_id].inner_bounds.kcols)
node _ld_bias_io_req_bits_derived_params_result_weight_spad_stride_T_3 = mul(_ld_bias_io_req_bits_derived_params_result_weight_spad_stride_T_2, loops[loop_requesting_ld_bias_id].inner_bounds.kchs)
node _ld_bias_io_req_bits_derived_params_result_weight_spad_stride_T_4 = mux(loops[loop_requesting_ld_bias_id].trans_weight_0132, _ld_bias_io_req_bits_derived_params_result_weight_spad_stride_T_1, _ld_bias_io_req_bits_derived_params_result_weight_spad_stride_T_3)
connect ld_bias_io_req_bits_derived_params_result.weight_spad_stride, _ld_bias_io_req_bits_derived_params_result_weight_spad_stride_T_4
connect ld_bias.io.req.bits.derived_params.weight_spad_stride, ld_bias_io_req_bits_derived_params_result.weight_spad_stride
connect ld_bias.io.req.bits.derived_params.input_spad_stride, ld_bias_io_req_bits_derived_params_result.input_spad_stride
connect ld_bias.io.req.bits.derived_params.bias_spad_stride, ld_bias_io_req_bits_derived_params_result.bias_spad_stride
connect ld_bias.io.req.bits.derived_params.in_channels_per_bank, ld_bias_io_req_bits_derived_params_result.in_channels_per_bank
connect ld_bias.io.req.bits.derived_params.out_channels_per_bank, ld_bias_io_req_bits_derived_params_result.out_channels_per_bank
connect ld_bias.io.req.bits.derived_params.ichs, ld_bias_io_req_bits_derived_params_result.ichs
connect ld_bias.io.req.bits.derived_params.icols_unpadded, ld_bias_io_req_bits_derived_params_result.icols_unpadded
connect ld_bias.io.req.bits.derived_params.irows_unpadded, ld_bias_io_req_bits_derived_params_result.irows_unpadded
connect ld_bias.io.req.bits.derived_params.icols, ld_bias_io_req_bits_derived_params_result.icols
connect ld_bias.io.req.bits.derived_params.irows, ld_bias_io_req_bits_derived_params_result.irows
connect ld_bias.io.req.bits.derived_params.ochs, ld_bias_io_req_bits_derived_params_result.ochs
connect ld_bias.io.req.bits.addr_start, ld_bias_addr_start
connect ld_bias.io.req.bits.dram_addr, loops[loop_requesting_ld_bias_id].bias_dram_addr
connect ld_bias.io.req.bits.no_bias, loops[loop_requesting_ld_bias_id].no_bias
connect ld_bias.io.req.bits.loop_id, loop_requesting_ld_bias_id
node _ld_bias_io_req_valid_T = eq(loops[loop_requesting_ld_bias_id].ld_bias_started, UInt<1>(0h0))
node _ld_bias_io_req_valid_T_1 = and(_ld_bias_io_req_valid_T, loops[loop_requesting_ld_bias_id].configured)
connect ld_bias.io.req.valid, _ld_bias_io_req_valid_T_1
node _T_22 = and(ld_bias.io.req.ready, ld_bias.io.req.valid)
when _T_22 :
connect loops[loop_requesting_ld_bias_id].running, UInt<1>(0h1)
connect loops[loop_requesting_ld_bias_id].ld_bias_started, UInt<1>(0h1)
node _T_23 = neq(loops[loop_requesting_ld_bias_id].output_dram_addr, UInt<1>(0h0))
when _T_23 :
node _ld_bias_addr_start_max_T = sub(UInt<13>(0h1000), UInt<1>(0h1))
node ld_bias_addr_start_max = tail(_ld_bias_addr_start_max_T, 1)
node _ld_bias_addr_start_T = add(ld_bias_addr_start, UInt<12>(0h800))
node _ld_bias_addr_start_T_1 = tail(_ld_bias_addr_start_T, 1)
node _ld_bias_addr_start_T_2 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _ld_bias_addr_start_T_3 = add(ld_bias_addr_start, UInt<12>(0h800))
node _ld_bias_addr_start_T_4 = gt(_ld_bias_addr_start_T_3, ld_bias_addr_start_max)
node _ld_bias_addr_start_T_5 = mux(_ld_bias_addr_start_T_4, UInt<1>(0h0), _ld_bias_addr_start_T_1)
node _ld_bias_addr_start_T_6 = mux(_ld_bias_addr_start_T_2, ld_bias_addr_start, _ld_bias_addr_start_T_5)
connect ld_bias_addr_start, _ld_bias_addr_start_T_6
node loop_requesting_ld_input_id = mux(loops[head_loop_id].ld_input_started, tail_loop_id, head_loop_id)
connect ld_input.io.req.bits.outer_bounds.pool_padding, loops[loop_requesting_ld_input_id].outer_bounds.pool_padding
connect ld_input.io.req.bits.outer_bounds.pool_stride, loops[loop_requesting_ld_input_id].outer_bounds.pool_stride
connect ld_input.io.req.bits.outer_bounds.pool_size, loops[loop_requesting_ld_input_id].outer_bounds.pool_size
connect ld_input.io.req.bits.outer_bounds.kernel_dilation, loops[loop_requesting_ld_input_id].outer_bounds.kernel_dilation
connect ld_input.io.req.bits.outer_bounds.kernel_dim, loops[loop_requesting_ld_input_id].outer_bounds.kernel_dim
connect ld_input.io.req.bits.outer_bounds.padding, loops[loop_requesting_ld_input_id].outer_bounds.padding
connect ld_input.io.req.bits.outer_bounds.stride, loops[loop_requesting_ld_input_id].outer_bounds.stride
connect ld_input.io.req.bits.outer_bounds.pool_out_col_dim, loops[loop_requesting_ld_input_id].outer_bounds.pool_out_col_dim
connect ld_input.io.req.bits.outer_bounds.pool_out_row_dim, loops[loop_requesting_ld_input_id].outer_bounds.pool_out_row_dim
connect ld_input.io.req.bits.outer_bounds.weight_stride, loops[loop_requesting_ld_input_id].outer_bounds.weight_stride
connect ld_input.io.req.bits.outer_bounds.in_stride, loops[loop_requesting_ld_input_id].outer_bounds.in_stride
connect ld_input.io.req.bits.outer_bounds.out_stride, loops[loop_requesting_ld_input_id].outer_bounds.out_stride
connect ld_input.io.req.bits.outer_bounds.out_row_dim, loops[loop_requesting_ld_input_id].outer_bounds.out_row_dim
connect ld_input.io.req.bits.outer_bounds.out_col_dim, loops[loop_requesting_ld_input_id].outer_bounds.out_col_dim
connect ld_input.io.req.bits.outer_bounds.out_channels, loops[loop_requesting_ld_input_id].outer_bounds.out_channels
connect ld_input.io.req.bits.outer_bounds.in_channels, loops[loop_requesting_ld_input_id].outer_bounds.in_channels
connect ld_input.io.req.bits.outer_bounds.in_col_dim, loops[loop_requesting_ld_input_id].outer_bounds.in_col_dim
connect ld_input.io.req.bits.outer_bounds.in_row_dim, loops[loop_requesting_ld_input_id].outer_bounds.in_row_dim
connect ld_input.io.req.bits.outer_bounds.batch_size, loops[loop_requesting_ld_input_id].outer_bounds.batch_size
connect ld_input.io.req.bits.inner_bounds.ocols, loops[loop_requesting_ld_input_id].inner_bounds.ocols
connect ld_input.io.req.bits.inner_bounds.orows, loops[loop_requesting_ld_input_id].inner_bounds.orows
connect ld_input.io.req.bits.inner_bounds.pdpad, loops[loop_requesting_ld_input_id].inner_bounds.pdpad
connect ld_input.io.req.bits.inner_bounds.pupad, loops[loop_requesting_ld_input_id].inner_bounds.pupad
connect ld_input.io.req.bits.inner_bounds.prad, loops[loop_requesting_ld_input_id].inner_bounds.prad
connect ld_input.io.req.bits.inner_bounds.plpad, loops[loop_requesting_ld_input_id].inner_bounds.plpad
connect ld_input.io.req.bits.inner_bounds.dpad, loops[loop_requesting_ld_input_id].inner_bounds.dpad
connect ld_input.io.req.bits.inner_bounds.upad, loops[loop_requesting_ld_input_id].inner_bounds.upad
connect ld_input.io.req.bits.inner_bounds.rpad, loops[loop_requesting_ld_input_id].inner_bounds.rpad
connect ld_input.io.req.bits.inner_bounds.lpad, loops[loop_requesting_ld_input_id].inner_bounds.lpad
connect ld_input.io.req.bits.inner_bounds.kchs, loops[loop_requesting_ld_input_id].inner_bounds.kchs
connect ld_input.io.req.bits.inner_bounds.kcols, loops[loop_requesting_ld_input_id].inner_bounds.kcols
connect ld_input.io.req.bits.inner_bounds.krows, loops[loop_requesting_ld_input_id].inner_bounds.krows
connect ld_input.io.req.bits.inner_bounds.pochs, loops[loop_requesting_ld_input_id].inner_bounds.pochs
connect ld_input.io.req.bits.inner_bounds.pocols, loops[loop_requesting_ld_input_id].inner_bounds.pocols
connect ld_input.io.req.bits.inner_bounds.porows, loops[loop_requesting_ld_input_id].inner_bounds.porows
connect ld_input.io.req.bits.inner_bounds.batches, loops[loop_requesting_ld_input_id].inner_bounds.batches
wire ld_input_io_req_bits_derived_params_result : { ochs : UInt<16>, irows : UInt<16>, icols : UInt<16>, irows_unpadded : UInt<16>, icols_unpadded : UInt<16>, ichs : UInt<16>, out_channels_per_bank : UInt<16>, in_channels_per_bank : UInt<16>, bias_spad_stride : UInt<16>, input_spad_stride : UInt<16>, weight_spad_stride : UInt<16>}
connect ld_input_io_req_bits_derived_params_result.ochs, loops[loop_requesting_ld_input_id].inner_bounds.pochs
node _ld_input_io_req_bits_derived_params_dilated_krows_T = sub(loops[loop_requesting_ld_input_id].outer_bounds.kernel_dilation, UInt<1>(0h1))
node _ld_input_io_req_bits_derived_params_dilated_krows_T_1 = tail(_ld_input_io_req_bits_derived_params_dilated_krows_T, 1)
node _ld_input_io_req_bits_derived_params_dilated_krows_T_2 = sub(loops[loop_requesting_ld_input_id].inner_bounds.krows, UInt<1>(0h1))
node _ld_input_io_req_bits_derived_params_dilated_krows_T_3 = tail(_ld_input_io_req_bits_derived_params_dilated_krows_T_2, 1)
node _ld_input_io_req_bits_derived_params_dilated_krows_T_4 = mul(_ld_input_io_req_bits_derived_params_dilated_krows_T_1, _ld_input_io_req_bits_derived_params_dilated_krows_T_3)
node _ld_input_io_req_bits_derived_params_dilated_krows_T_5 = add(loops[loop_requesting_ld_input_id].inner_bounds.krows, _ld_input_io_req_bits_derived_params_dilated_krows_T_4)
node ld_input_io_req_bits_derived_params_dilated_krows = tail(_ld_input_io_req_bits_derived_params_dilated_krows_T_5, 1)
node _ld_input_io_req_bits_derived_params_dilated_kcols_T = sub(loops[loop_requesting_ld_input_id].outer_bounds.kernel_dilation, UInt<1>(0h1))
node _ld_input_io_req_bits_derived_params_dilated_kcols_T_1 = tail(_ld_input_io_req_bits_derived_params_dilated_kcols_T, 1)
node _ld_input_io_req_bits_derived_params_dilated_kcols_T_2 = sub(loops[loop_requesting_ld_input_id].inner_bounds.kcols, UInt<1>(0h1))
node _ld_input_io_req_bits_derived_params_dilated_kcols_T_3 = tail(_ld_input_io_req_bits_derived_params_dilated_kcols_T_2, 1)
node _ld_input_io_req_bits_derived_params_dilated_kcols_T_4 = mul(_ld_input_io_req_bits_derived_params_dilated_kcols_T_1, _ld_input_io_req_bits_derived_params_dilated_kcols_T_3)
node _ld_input_io_req_bits_derived_params_dilated_kcols_T_5 = add(loops[loop_requesting_ld_input_id].inner_bounds.kcols, _ld_input_io_req_bits_derived_params_dilated_kcols_T_4)
node ld_input_io_req_bits_derived_params_dilated_kcols = tail(_ld_input_io_req_bits_derived_params_dilated_kcols_T_5, 1)
node _ld_input_io_req_bits_derived_params_irows_without_dilation_T = mul(loops[loop_requesting_ld_input_id].inner_bounds.orows, loops[loop_requesting_ld_input_id].outer_bounds.stride)
node _ld_input_io_req_bits_derived_params_irows_without_dilation_T_1 = add(_ld_input_io_req_bits_derived_params_irows_without_dilation_T, ld_input_io_req_bits_derived_params_dilated_krows)
node _ld_input_io_req_bits_derived_params_irows_without_dilation_T_2 = sub(_ld_input_io_req_bits_derived_params_irows_without_dilation_T_1, UInt<1>(0h1))
node ld_input_io_req_bits_derived_params_irows_without_dilation = asUInt(_ld_input_io_req_bits_derived_params_irows_without_dilation_T_2)
node _ld_input_io_req_bits_derived_params_icols_without_dilation_T = mul(loops[loop_requesting_ld_input_id].inner_bounds.ocols, loops[loop_requesting_ld_input_id].outer_bounds.stride)
node _ld_input_io_req_bits_derived_params_icols_without_dilation_T_1 = add(_ld_input_io_req_bits_derived_params_icols_without_dilation_T, ld_input_io_req_bits_derived_params_dilated_kcols)
node _ld_input_io_req_bits_derived_params_icols_without_dilation_T_2 = sub(_ld_input_io_req_bits_derived_params_icols_without_dilation_T_1, UInt<1>(0h1))
node ld_input_io_req_bits_derived_params_icols_without_dilation = asUInt(_ld_input_io_req_bits_derived_params_icols_without_dilation_T_2)
node _ld_input_io_req_bits_derived_params_irows_unpadded_without_dilation_T = sub(ld_input_io_req_bits_derived_params_irows_without_dilation, loops[loop_requesting_ld_input_id].inner_bounds.upad)
node _ld_input_io_req_bits_derived_params_irows_unpadded_without_dilation_T_1 = asUInt(_ld_input_io_req_bits_derived_params_irows_unpadded_without_dilation_T)
node _ld_input_io_req_bits_derived_params_irows_unpadded_without_dilation_T_2 = sub(_ld_input_io_req_bits_derived_params_irows_unpadded_without_dilation_T_1, loops[loop_requesting_ld_input_id].inner_bounds.dpad)
node ld_input_io_req_bits_derived_params_irows_unpadded_without_dilation = asUInt(_ld_input_io_req_bits_derived_params_irows_unpadded_without_dilation_T_2)
node _ld_input_io_req_bits_derived_params_icols_unpadded_without_dilation_T = sub(ld_input_io_req_bits_derived_params_icols_without_dilation, loops[loop_requesting_ld_input_id].inner_bounds.lpad)
node _ld_input_io_req_bits_derived_params_icols_unpadded_without_dilation_T_1 = asUInt(_ld_input_io_req_bits_derived_params_icols_unpadded_without_dilation_T)
node _ld_input_io_req_bits_derived_params_icols_unpadded_without_dilation_T_2 = sub(_ld_input_io_req_bits_derived_params_icols_unpadded_without_dilation_T_1, loops[loop_requesting_ld_input_id].inner_bounds.rpad)
node ld_input_io_req_bits_derived_params_icols_unpadded_without_dilation = asUInt(_ld_input_io_req_bits_derived_params_icols_unpadded_without_dilation_T_2)
node _ld_input_io_req_bits_derived_params_irows_unpadded_T = add(ld_input_io_req_bits_derived_params_irows_unpadded_without_dilation, loops[loop_requesting_ld_input_id].input_dilated)
node ld_input_io_req_bits_derived_params_irows_unpadded = dshr(_ld_input_io_req_bits_derived_params_irows_unpadded_T, loops[loop_requesting_ld_input_id].input_dilated)
node _ld_input_io_req_bits_derived_params_icols_unpadded_T = add(ld_input_io_req_bits_derived_params_icols_unpadded_without_dilation, loops[loop_requesting_ld_input_id].input_dilated)
node ld_input_io_req_bits_derived_params_icols_unpadded = dshr(_ld_input_io_req_bits_derived_params_icols_unpadded_T, loops[loop_requesting_ld_input_id].input_dilated)
node _ld_input_io_req_bits_derived_params_result_irows_T = add(loops[loop_requesting_ld_input_id].inner_bounds.upad, loops[loop_requesting_ld_input_id].input_dilated)
node _ld_input_io_req_bits_derived_params_result_irows_T_1 = dshr(_ld_input_io_req_bits_derived_params_result_irows_T, loops[loop_requesting_ld_input_id].input_dilated)
node _ld_input_io_req_bits_derived_params_result_irows_T_2 = add(ld_input_io_req_bits_derived_params_irows_unpadded, _ld_input_io_req_bits_derived_params_result_irows_T_1)
node _ld_input_io_req_bits_derived_params_result_irows_T_3 = add(loops[loop_requesting_ld_input_id].inner_bounds.dpad, loops[loop_requesting_ld_input_id].input_dilated)
node _ld_input_io_req_bits_derived_params_result_irows_T_4 = dshr(_ld_input_io_req_bits_derived_params_result_irows_T_3, loops[loop_requesting_ld_input_id].input_dilated)
node _ld_input_io_req_bits_derived_params_result_irows_T_5 = add(_ld_input_io_req_bits_derived_params_result_irows_T_2, _ld_input_io_req_bits_derived_params_result_irows_T_4)
node _ld_input_io_req_bits_derived_params_result_irows_T_6 = mux(loops[loop_requesting_ld_input_id].input_dilated, _ld_input_io_req_bits_derived_params_result_irows_T_5, ld_input_io_req_bits_derived_params_irows_without_dilation)
connect ld_input_io_req_bits_derived_params_result.irows, _ld_input_io_req_bits_derived_params_result_irows_T_6
node _ld_input_io_req_bits_derived_params_result_icols_T = add(loops[loop_requesting_ld_input_id].inner_bounds.lpad, loops[loop_requesting_ld_input_id].input_dilated)
node _ld_input_io_req_bits_derived_params_result_icols_T_1 = dshr(_ld_input_io_req_bits_derived_params_result_icols_T, loops[loop_requesting_ld_input_id].input_dilated)
node _ld_input_io_req_bits_derived_params_result_icols_T_2 = add(ld_input_io_req_bits_derived_params_icols_unpadded, _ld_input_io_req_bits_derived_params_result_icols_T_1)
node _ld_input_io_req_bits_derived_params_result_icols_T_3 = add(loops[loop_requesting_ld_input_id].inner_bounds.rpad, loops[loop_requesting_ld_input_id].input_dilated)
node _ld_input_io_req_bits_derived_params_result_icols_T_4 = dshr(_ld_input_io_req_bits_derived_params_result_icols_T_3, loops[loop_requesting_ld_input_id].input_dilated)
node _ld_input_io_req_bits_derived_params_result_icols_T_5 = add(_ld_input_io_req_bits_derived_params_result_icols_T_2, _ld_input_io_req_bits_derived_params_result_icols_T_4)
node _ld_input_io_req_bits_derived_params_result_icols_T_6 = mux(loops[loop_requesting_ld_input_id].input_dilated, _ld_input_io_req_bits_derived_params_result_icols_T_5, ld_input_io_req_bits_derived_params_icols_without_dilation)
connect ld_input_io_req_bits_derived_params_result.icols, _ld_input_io_req_bits_derived_params_result_icols_T_6
connect ld_input_io_req_bits_derived_params_result.irows_unpadded, ld_input_io_req_bits_derived_params_irows_unpadded
connect ld_input_io_req_bits_derived_params_result.icols_unpadded, ld_input_io_req_bits_derived_params_icols_unpadded
connect ld_input_io_req_bits_derived_params_result.ichs, loops[loop_requesting_ld_input_id].inner_bounds.kchs
node _ld_input_io_req_bits_derived_params_result_out_channels_per_bank_T = div(ld_input_io_req_bits_derived_params_result.ochs, UInt<16>(0h4))
node _ld_input_io_req_bits_derived_params_result_out_channels_per_bank_T_1 = rem(ld_input_io_req_bits_derived_params_result.ochs, UInt<3>(0h4))
node _ld_input_io_req_bits_derived_params_result_out_channels_per_bank_T_2 = neq(_ld_input_io_req_bits_derived_params_result_out_channels_per_bank_T_1, UInt<1>(0h0))
node _ld_input_io_req_bits_derived_params_result_out_channels_per_bank_T_3 = add(_ld_input_io_req_bits_derived_params_result_out_channels_per_bank_T, _ld_input_io_req_bits_derived_params_result_out_channels_per_bank_T_2)
connect ld_input_io_req_bits_derived_params_result.out_channels_per_bank, _ld_input_io_req_bits_derived_params_result_out_channels_per_bank_T_3
node _ld_input_io_req_bits_derived_params_result_in_channels_per_bank_T = div(ld_input_io_req_bits_derived_params_result.ichs, UInt<16>(0h4))
node _ld_input_io_req_bits_derived_params_result_in_channels_per_bank_T_1 = rem(ld_input_io_req_bits_derived_params_result.ichs, UInt<3>(0h4))
node _ld_input_io_req_bits_derived_params_result_in_channels_per_bank_T_2 = neq(_ld_input_io_req_bits_derived_params_result_in_channels_per_bank_T_1, UInt<1>(0h0))
node _ld_input_io_req_bits_derived_params_result_in_channels_per_bank_T_3 = add(_ld_input_io_req_bits_derived_params_result_in_channels_per_bank_T, _ld_input_io_req_bits_derived_params_result_in_channels_per_bank_T_2)
connect ld_input_io_req_bits_derived_params_result.in_channels_per_bank, _ld_input_io_req_bits_derived_params_result_in_channels_per_bank_T_3
node _ld_input_io_req_bits_derived_params_result_bias_spad_stride_T = mul(loops[loop_requesting_ld_input_id].inner_bounds.batches, loops[loop_requesting_ld_input_id].inner_bounds.orows)
node _ld_input_io_req_bits_derived_params_result_bias_spad_stride_T_1 = mul(_ld_input_io_req_bits_derived_params_result_bias_spad_stride_T, loops[loop_requesting_ld_input_id].inner_bounds.ocols)
connect ld_input_io_req_bits_derived_params_result.bias_spad_stride, _ld_input_io_req_bits_derived_params_result_bias_spad_stride_T_1
node _ld_input_io_req_bits_derived_params_result_input_spad_stride_T = dshr(ld_input_io_req_bits_derived_params_result.irows, loops[loop_requesting_ld_input_id].downsample)
node _ld_input_io_req_bits_derived_params_result_input_spad_stride_T_1 = mul(ld_input_io_req_bits_derived_params_result.ichs, _ld_input_io_req_bits_derived_params_result_input_spad_stride_T)
node _ld_input_io_req_bits_derived_params_result_input_spad_stride_T_2 = dshr(ld_input_io_req_bits_derived_params_result.icols, loops[loop_requesting_ld_input_id].downsample)
node _ld_input_io_req_bits_derived_params_result_input_spad_stride_T_3 = mul(_ld_input_io_req_bits_derived_params_result_input_spad_stride_T_1, _ld_input_io_req_bits_derived_params_result_input_spad_stride_T_2)
node _ld_input_io_req_bits_derived_params_result_input_spad_stride_T_4 = dshr(ld_input_io_req_bits_derived_params_result.irows, loops[loop_requesting_ld_input_id].downsample)
node _ld_input_io_req_bits_derived_params_result_input_spad_stride_T_5 = mul(loops[loop_requesting_ld_input_id].inner_bounds.batches, _ld_input_io_req_bits_derived_params_result_input_spad_stride_T_4)
node _ld_input_io_req_bits_derived_params_result_input_spad_stride_T_6 = dshr(ld_input_io_req_bits_derived_params_result.icols, loops[loop_requesting_ld_input_id].downsample)
node _ld_input_io_req_bits_derived_params_result_input_spad_stride_T_7 = mul(_ld_input_io_req_bits_derived_params_result_input_spad_stride_T_5, _ld_input_io_req_bits_derived_params_result_input_spad_stride_T_6)
node _ld_input_io_req_bits_derived_params_result_input_spad_stride_T_8 = mux(loops[loop_requesting_ld_input_id].trans_input_3120, _ld_input_io_req_bits_derived_params_result_input_spad_stride_T_3, _ld_input_io_req_bits_derived_params_result_input_spad_stride_T_7)
connect ld_input_io_req_bits_derived_params_result.input_spad_stride, _ld_input_io_req_bits_derived_params_result_input_spad_stride_T_8
node _ld_input_io_req_bits_derived_params_result_weight_spad_stride_T = mul(loops[loop_requesting_ld_input_id].inner_bounds.krows, loops[loop_requesting_ld_input_id].inner_bounds.kcols)
node _ld_input_io_req_bits_derived_params_result_weight_spad_stride_T_1 = mul(_ld_input_io_req_bits_derived_params_result_weight_spad_stride_T, loops[loop_requesting_ld_input_id].inner_bounds.pochs)
node _ld_input_io_req_bits_derived_params_result_weight_spad_stride_T_2 = mul(loops[loop_requesting_ld_input_id].inner_bounds.krows, loops[loop_requesting_ld_input_id].inner_bounds.kcols)
node _ld_input_io_req_bits_derived_params_result_weight_spad_stride_T_3 = mul(_ld_input_io_req_bits_derived_params_result_weight_spad_stride_T_2, loops[loop_requesting_ld_input_id].inner_bounds.kchs)
node _ld_input_io_req_bits_derived_params_result_weight_spad_stride_T_4 = mux(loops[loop_requesting_ld_input_id].trans_weight_0132, _ld_input_io_req_bits_derived_params_result_weight_spad_stride_T_1, _ld_input_io_req_bits_derived_params_result_weight_spad_stride_T_3)
connect ld_input_io_req_bits_derived_params_result.weight_spad_stride, _ld_input_io_req_bits_derived_params_result_weight_spad_stride_T_4
connect ld_input.io.req.bits.derived_params.weight_spad_stride, ld_input_io_req_bits_derived_params_result.weight_spad_stride
connect ld_input.io.req.bits.derived_params.input_spad_stride, ld_input_io_req_bits_derived_params_result.input_spad_stride
connect ld_input.io.req.bits.derived_params.bias_spad_stride, ld_input_io_req_bits_derived_params_result.bias_spad_stride
connect ld_input.io.req.bits.derived_params.in_channels_per_bank, ld_input_io_req_bits_derived_params_result.in_channels_per_bank
connect ld_input.io.req.bits.derived_params.out_channels_per_bank, ld_input_io_req_bits_derived_params_result.out_channels_per_bank
connect ld_input.io.req.bits.derived_params.ichs, ld_input_io_req_bits_derived_params_result.ichs
connect ld_input.io.req.bits.derived_params.icols_unpadded, ld_input_io_req_bits_derived_params_result.icols_unpadded
connect ld_input.io.req.bits.derived_params.irows_unpadded, ld_input_io_req_bits_derived_params_result.irows_unpadded
connect ld_input.io.req.bits.derived_params.icols, ld_input_io_req_bits_derived_params_result.icols
connect ld_input.io.req.bits.derived_params.irows, ld_input_io_req_bits_derived_params_result.irows
connect ld_input.io.req.bits.derived_params.ochs, ld_input_io_req_bits_derived_params_result.ochs
node _ld_input_io_req_bits_addr_start_T = eq(loops[loop_requesting_ld_input_id].a_ex_spad_id, UInt<1>(0h0))
node _ld_input_io_req_bits_addr_start_T_1 = sub(loops[loop_requesting_ld_input_id].a_ex_spad_id, UInt<1>(0h1))
node _ld_input_io_req_bits_addr_start_T_2 = tail(_ld_input_io_req_bits_addr_start_T_1, 1)
node _ld_input_io_req_bits_addr_start_T_3 = mul(_ld_input_io_req_bits_addr_start_T_2, UInt<14>(0h2000))
node _ld_input_io_req_bits_addr_start_T_4 = mux(_ld_input_io_req_bits_addr_start_T, loops[loop_requesting_ld_input_id].a_addr_start, _ld_input_io_req_bits_addr_start_T_3)
connect ld_input.io.req.bits.addr_start, _ld_input_io_req_bits_addr_start_T_4
connect ld_input.io.req.bits.dram_addr, loops[loop_requesting_ld_input_id].input_dram_addr
connect ld_input.io.req.bits.downsample, loops[loop_requesting_ld_input_id].downsample
connect ld_input.io.req.bits.max_pixels_per_row, loops[loop_requesting_ld_input_id].max_pixels_per_row
connect ld_input.io.req.bits.input_dilated, loops[loop_requesting_ld_input_id].input_dilated
connect ld_input.io.req.bits.trans_input_3120, loops[loop_requesting_ld_input_id].trans_input_3120
connect ld_input.io.req.bits.loop_id, loop_requesting_ld_input_id
node _ld_input_io_req_valid_T = eq(loops[loop_requesting_ld_input_id].ld_input_started, UInt<1>(0h0))
node _ld_input_io_req_valid_T_1 = and(_ld_input_io_req_valid_T, loops[loop_requesting_ld_input_id].configured)
connect ld_input.io.req.valid, _ld_input_io_req_valid_T_1
node _T_24 = and(ld_input.io.req.ready, ld_input.io.req.valid)
when _T_24 :
connect loops[loop_requesting_ld_input_id].running, UInt<1>(0h1)
connect loops[loop_requesting_ld_input_id].ld_input_started, UInt<1>(0h1)
node loop_requesting_ld_weights_id = mux(loops[head_loop_id].ld_weights_started, tail_loop_id, head_loop_id)
connect ld_weights.io.req.bits.outer_bounds.pool_padding, loops[loop_requesting_ld_weights_id].outer_bounds.pool_padding
connect ld_weights.io.req.bits.outer_bounds.pool_stride, loops[loop_requesting_ld_weights_id].outer_bounds.pool_stride
connect ld_weights.io.req.bits.outer_bounds.pool_size, loops[loop_requesting_ld_weights_id].outer_bounds.pool_size
connect ld_weights.io.req.bits.outer_bounds.kernel_dilation, loops[loop_requesting_ld_weights_id].outer_bounds.kernel_dilation
connect ld_weights.io.req.bits.outer_bounds.kernel_dim, loops[loop_requesting_ld_weights_id].outer_bounds.kernel_dim
connect ld_weights.io.req.bits.outer_bounds.padding, loops[loop_requesting_ld_weights_id].outer_bounds.padding
connect ld_weights.io.req.bits.outer_bounds.stride, loops[loop_requesting_ld_weights_id].outer_bounds.stride
connect ld_weights.io.req.bits.outer_bounds.pool_out_col_dim, loops[loop_requesting_ld_weights_id].outer_bounds.pool_out_col_dim
connect ld_weights.io.req.bits.outer_bounds.pool_out_row_dim, loops[loop_requesting_ld_weights_id].outer_bounds.pool_out_row_dim
connect ld_weights.io.req.bits.outer_bounds.weight_stride, loops[loop_requesting_ld_weights_id].outer_bounds.weight_stride
connect ld_weights.io.req.bits.outer_bounds.in_stride, loops[loop_requesting_ld_weights_id].outer_bounds.in_stride
connect ld_weights.io.req.bits.outer_bounds.out_stride, loops[loop_requesting_ld_weights_id].outer_bounds.out_stride
connect ld_weights.io.req.bits.outer_bounds.out_row_dim, loops[loop_requesting_ld_weights_id].outer_bounds.out_row_dim
connect ld_weights.io.req.bits.outer_bounds.out_col_dim, loops[loop_requesting_ld_weights_id].outer_bounds.out_col_dim
connect ld_weights.io.req.bits.outer_bounds.out_channels, loops[loop_requesting_ld_weights_id].outer_bounds.out_channels
connect ld_weights.io.req.bits.outer_bounds.in_channels, loops[loop_requesting_ld_weights_id].outer_bounds.in_channels
connect ld_weights.io.req.bits.outer_bounds.in_col_dim, loops[loop_requesting_ld_weights_id].outer_bounds.in_col_dim
connect ld_weights.io.req.bits.outer_bounds.in_row_dim, loops[loop_requesting_ld_weights_id].outer_bounds.in_row_dim
connect ld_weights.io.req.bits.outer_bounds.batch_size, loops[loop_requesting_ld_weights_id].outer_bounds.batch_size
connect ld_weights.io.req.bits.inner_bounds.ocols, loops[loop_requesting_ld_weights_id].inner_bounds.ocols
connect ld_weights.io.req.bits.inner_bounds.orows, loops[loop_requesting_ld_weights_id].inner_bounds.orows
connect ld_weights.io.req.bits.inner_bounds.pdpad, loops[loop_requesting_ld_weights_id].inner_bounds.pdpad
connect ld_weights.io.req.bits.inner_bounds.pupad, loops[loop_requesting_ld_weights_id].inner_bounds.pupad
connect ld_weights.io.req.bits.inner_bounds.prad, loops[loop_requesting_ld_weights_id].inner_bounds.prad
connect ld_weights.io.req.bits.inner_bounds.plpad, loops[loop_requesting_ld_weights_id].inner_bounds.plpad
connect ld_weights.io.req.bits.inner_bounds.dpad, loops[loop_requesting_ld_weights_id].inner_bounds.dpad
connect ld_weights.io.req.bits.inner_bounds.upad, loops[loop_requesting_ld_weights_id].inner_bounds.upad
connect ld_weights.io.req.bits.inner_bounds.rpad, loops[loop_requesting_ld_weights_id].inner_bounds.rpad
connect ld_weights.io.req.bits.inner_bounds.lpad, loops[loop_requesting_ld_weights_id].inner_bounds.lpad
connect ld_weights.io.req.bits.inner_bounds.kchs, loops[loop_requesting_ld_weights_id].inner_bounds.kchs
connect ld_weights.io.req.bits.inner_bounds.kcols, loops[loop_requesting_ld_weights_id].inner_bounds.kcols
connect ld_weights.io.req.bits.inner_bounds.krows, loops[loop_requesting_ld_weights_id].inner_bounds.krows
connect ld_weights.io.req.bits.inner_bounds.pochs, loops[loop_requesting_ld_weights_id].inner_bounds.pochs
connect ld_weights.io.req.bits.inner_bounds.pocols, loops[loop_requesting_ld_weights_id].inner_bounds.pocols
connect ld_weights.io.req.bits.inner_bounds.porows, loops[loop_requesting_ld_weights_id].inner_bounds.porows
connect ld_weights.io.req.bits.inner_bounds.batches, loops[loop_requesting_ld_weights_id].inner_bounds.batches
wire ld_weights_io_req_bits_derived_params_result : { ochs : UInt<16>, irows : UInt<16>, icols : UInt<16>, irows_unpadded : UInt<16>, icols_unpadded : UInt<16>, ichs : UInt<16>, out_channels_per_bank : UInt<16>, in_channels_per_bank : UInt<16>, bias_spad_stride : UInt<16>, input_spad_stride : UInt<16>, weight_spad_stride : UInt<16>}
connect ld_weights_io_req_bits_derived_params_result.ochs, loops[loop_requesting_ld_weights_id].inner_bounds.pochs
node _ld_weights_io_req_bits_derived_params_dilated_krows_T = sub(loops[loop_requesting_ld_weights_id].outer_bounds.kernel_dilation, UInt<1>(0h1))
node _ld_weights_io_req_bits_derived_params_dilated_krows_T_1 = tail(_ld_weights_io_req_bits_derived_params_dilated_krows_T, 1)
node _ld_weights_io_req_bits_derived_params_dilated_krows_T_2 = sub(loops[loop_requesting_ld_weights_id].inner_bounds.krows, UInt<1>(0h1))
node _ld_weights_io_req_bits_derived_params_dilated_krows_T_3 = tail(_ld_weights_io_req_bits_derived_params_dilated_krows_T_2, 1)
node _ld_weights_io_req_bits_derived_params_dilated_krows_T_4 = mul(_ld_weights_io_req_bits_derived_params_dilated_krows_T_1, _ld_weights_io_req_bits_derived_params_dilated_krows_T_3)
node _ld_weights_io_req_bits_derived_params_dilated_krows_T_5 = add(loops[loop_requesting_ld_weights_id].inner_bounds.krows, _ld_weights_io_req_bits_derived_params_dilated_krows_T_4)
node ld_weights_io_req_bits_derived_params_dilated_krows = tail(_ld_weights_io_req_bits_derived_params_dilated_krows_T_5, 1)
node _ld_weights_io_req_bits_derived_params_dilated_kcols_T = sub(loops[loop_requesting_ld_weights_id].outer_bounds.kernel_dilation, UInt<1>(0h1))
node _ld_weights_io_req_bits_derived_params_dilated_kcols_T_1 = tail(_ld_weights_io_req_bits_derived_params_dilated_kcols_T, 1)
node _ld_weights_io_req_bits_derived_params_dilated_kcols_T_2 = sub(loops[loop_requesting_ld_weights_id].inner_bounds.kcols, UInt<1>(0h1))
node _ld_weights_io_req_bits_derived_params_dilated_kcols_T_3 = tail(_ld_weights_io_req_bits_derived_params_dilated_kcols_T_2, 1)
node _ld_weights_io_req_bits_derived_params_dilated_kcols_T_4 = mul(_ld_weights_io_req_bits_derived_params_dilated_kcols_T_1, _ld_weights_io_req_bits_derived_params_dilated_kcols_T_3)
node _ld_weights_io_req_bits_derived_params_dilated_kcols_T_5 = add(loops[loop_requesting_ld_weights_id].inner_bounds.kcols, _ld_weights_io_req_bits_derived_params_dilated_kcols_T_4)
node ld_weights_io_req_bits_derived_params_dilated_kcols = tail(_ld_weights_io_req_bits_derived_params_dilated_kcols_T_5, 1)
node _ld_weights_io_req_bits_derived_params_irows_without_dilation_T = mul(loops[loop_requesting_ld_weights_id].inner_bounds.orows, loops[loop_requesting_ld_weights_id].outer_bounds.stride)
node _ld_weights_io_req_bits_derived_params_irows_without_dilation_T_1 = add(_ld_weights_io_req_bits_derived_params_irows_without_dilation_T, ld_weights_io_req_bits_derived_params_dilated_krows)
node _ld_weights_io_req_bits_derived_params_irows_without_dilation_T_2 = sub(_ld_weights_io_req_bits_derived_params_irows_without_dilation_T_1, UInt<1>(0h1))
node ld_weights_io_req_bits_derived_params_irows_without_dilation = asUInt(_ld_weights_io_req_bits_derived_params_irows_without_dilation_T_2)
node _ld_weights_io_req_bits_derived_params_icols_without_dilation_T = mul(loops[loop_requesting_ld_weights_id].inner_bounds.ocols, loops[loop_requesting_ld_weights_id].outer_bounds.stride)
node _ld_weights_io_req_bits_derived_params_icols_without_dilation_T_1 = add(_ld_weights_io_req_bits_derived_params_icols_without_dilation_T, ld_weights_io_req_bits_derived_params_dilated_kcols)
node _ld_weights_io_req_bits_derived_params_icols_without_dilation_T_2 = sub(_ld_weights_io_req_bits_derived_params_icols_without_dilation_T_1, UInt<1>(0h1))
node ld_weights_io_req_bits_derived_params_icols_without_dilation = asUInt(_ld_weights_io_req_bits_derived_params_icols_without_dilation_T_2)
node _ld_weights_io_req_bits_derived_params_irows_unpadded_without_dilation_T = sub(ld_weights_io_req_bits_derived_params_irows_without_dilation, loops[loop_requesting_ld_weights_id].inner_bounds.upad)
node _ld_weights_io_req_bits_derived_params_irows_unpadded_without_dilation_T_1 = asUInt(_ld_weights_io_req_bits_derived_params_irows_unpadded_without_dilation_T)
node _ld_weights_io_req_bits_derived_params_irows_unpadded_without_dilation_T_2 = sub(_ld_weights_io_req_bits_derived_params_irows_unpadded_without_dilation_T_1, loops[loop_requesting_ld_weights_id].inner_bounds.dpad)
node ld_weights_io_req_bits_derived_params_irows_unpadded_without_dilation = asUInt(_ld_weights_io_req_bits_derived_params_irows_unpadded_without_dilation_T_2)
node _ld_weights_io_req_bits_derived_params_icols_unpadded_without_dilation_T = sub(ld_weights_io_req_bits_derived_params_icols_without_dilation, loops[loop_requesting_ld_weights_id].inner_bounds.lpad)
node _ld_weights_io_req_bits_derived_params_icols_unpadded_without_dilation_T_1 = asUInt(_ld_weights_io_req_bits_derived_params_icols_unpadded_without_dilation_T)
node _ld_weights_io_req_bits_derived_params_icols_unpadded_without_dilation_T_2 = sub(_ld_weights_io_req_bits_derived_params_icols_unpadded_without_dilation_T_1, loops[loop_requesting_ld_weights_id].inner_bounds.rpad)
node ld_weights_io_req_bits_derived_params_icols_unpadded_without_dilation = asUInt(_ld_weights_io_req_bits_derived_params_icols_unpadded_without_dilation_T_2)
node _ld_weights_io_req_bits_derived_params_irows_unpadded_T = add(ld_weights_io_req_bits_derived_params_irows_unpadded_without_dilation, loops[loop_requesting_ld_weights_id].input_dilated)
node ld_weights_io_req_bits_derived_params_irows_unpadded = dshr(_ld_weights_io_req_bits_derived_params_irows_unpadded_T, loops[loop_requesting_ld_weights_id].input_dilated)
node _ld_weights_io_req_bits_derived_params_icols_unpadded_T = add(ld_weights_io_req_bits_derived_params_icols_unpadded_without_dilation, loops[loop_requesting_ld_weights_id].input_dilated)
node ld_weights_io_req_bits_derived_params_icols_unpadded = dshr(_ld_weights_io_req_bits_derived_params_icols_unpadded_T, loops[loop_requesting_ld_weights_id].input_dilated)
node _ld_weights_io_req_bits_derived_params_result_irows_T = add(loops[loop_requesting_ld_weights_id].inner_bounds.upad, loops[loop_requesting_ld_weights_id].input_dilated)
node _ld_weights_io_req_bits_derived_params_result_irows_T_1 = dshr(_ld_weights_io_req_bits_derived_params_result_irows_T, loops[loop_requesting_ld_weights_id].input_dilated)
node _ld_weights_io_req_bits_derived_params_result_irows_T_2 = add(ld_weights_io_req_bits_derived_params_irows_unpadded, _ld_weights_io_req_bits_derived_params_result_irows_T_1)
node _ld_weights_io_req_bits_derived_params_result_irows_T_3 = add(loops[loop_requesting_ld_weights_id].inner_bounds.dpad, loops[loop_requesting_ld_weights_id].input_dilated)
node _ld_weights_io_req_bits_derived_params_result_irows_T_4 = dshr(_ld_weights_io_req_bits_derived_params_result_irows_T_3, loops[loop_requesting_ld_weights_id].input_dilated)
node _ld_weights_io_req_bits_derived_params_result_irows_T_5 = add(_ld_weights_io_req_bits_derived_params_result_irows_T_2, _ld_weights_io_req_bits_derived_params_result_irows_T_4)
node _ld_weights_io_req_bits_derived_params_result_irows_T_6 = mux(loops[loop_requesting_ld_weights_id].input_dilated, _ld_weights_io_req_bits_derived_params_result_irows_T_5, ld_weights_io_req_bits_derived_params_irows_without_dilation)
connect ld_weights_io_req_bits_derived_params_result.irows, _ld_weights_io_req_bits_derived_params_result_irows_T_6
node _ld_weights_io_req_bits_derived_params_result_icols_T = add(loops[loop_requesting_ld_weights_id].inner_bounds.lpad, loops[loop_requesting_ld_weights_id].input_dilated)
node _ld_weights_io_req_bits_derived_params_result_icols_T_1 = dshr(_ld_weights_io_req_bits_derived_params_result_icols_T, loops[loop_requesting_ld_weights_id].input_dilated)
node _ld_weights_io_req_bits_derived_params_result_icols_T_2 = add(ld_weights_io_req_bits_derived_params_icols_unpadded, _ld_weights_io_req_bits_derived_params_result_icols_T_1)
node _ld_weights_io_req_bits_derived_params_result_icols_T_3 = add(loops[loop_requesting_ld_weights_id].inner_bounds.rpad, loops[loop_requesting_ld_weights_id].input_dilated)
node _ld_weights_io_req_bits_derived_params_result_icols_T_4 = dshr(_ld_weights_io_req_bits_derived_params_result_icols_T_3, loops[loop_requesting_ld_weights_id].input_dilated)
node _ld_weights_io_req_bits_derived_params_result_icols_T_5 = add(_ld_weights_io_req_bits_derived_params_result_icols_T_2, _ld_weights_io_req_bits_derived_params_result_icols_T_4)
node _ld_weights_io_req_bits_derived_params_result_icols_T_6 = mux(loops[loop_requesting_ld_weights_id].input_dilated, _ld_weights_io_req_bits_derived_params_result_icols_T_5, ld_weights_io_req_bits_derived_params_icols_without_dilation)
connect ld_weights_io_req_bits_derived_params_result.icols, _ld_weights_io_req_bits_derived_params_result_icols_T_6
connect ld_weights_io_req_bits_derived_params_result.irows_unpadded, ld_weights_io_req_bits_derived_params_irows_unpadded
connect ld_weights_io_req_bits_derived_params_result.icols_unpadded, ld_weights_io_req_bits_derived_params_icols_unpadded
connect ld_weights_io_req_bits_derived_params_result.ichs, loops[loop_requesting_ld_weights_id].inner_bounds.kchs
node _ld_weights_io_req_bits_derived_params_result_out_channels_per_bank_T = div(ld_weights_io_req_bits_derived_params_result.ochs, UInt<16>(0h4))
node _ld_weights_io_req_bits_derived_params_result_out_channels_per_bank_T_1 = rem(ld_weights_io_req_bits_derived_params_result.ochs, UInt<3>(0h4))
node _ld_weights_io_req_bits_derived_params_result_out_channels_per_bank_T_2 = neq(_ld_weights_io_req_bits_derived_params_result_out_channels_per_bank_T_1, UInt<1>(0h0))
node _ld_weights_io_req_bits_derived_params_result_out_channels_per_bank_T_3 = add(_ld_weights_io_req_bits_derived_params_result_out_channels_per_bank_T, _ld_weights_io_req_bits_derived_params_result_out_channels_per_bank_T_2)
connect ld_weights_io_req_bits_derived_params_result.out_channels_per_bank, _ld_weights_io_req_bits_derived_params_result_out_channels_per_bank_T_3
node _ld_weights_io_req_bits_derived_params_result_in_channels_per_bank_T = div(ld_weights_io_req_bits_derived_params_result.ichs, UInt<16>(0h4))
node _ld_weights_io_req_bits_derived_params_result_in_channels_per_bank_T_1 = rem(ld_weights_io_req_bits_derived_params_result.ichs, UInt<3>(0h4))
node _ld_weights_io_req_bits_derived_params_result_in_channels_per_bank_T_2 = neq(_ld_weights_io_req_bits_derived_params_result_in_channels_per_bank_T_1, UInt<1>(0h0))
node _ld_weights_io_req_bits_derived_params_result_in_channels_per_bank_T_3 = add(_ld_weights_io_req_bits_derived_params_result_in_channels_per_bank_T, _ld_weights_io_req_bits_derived_params_result_in_channels_per_bank_T_2)
connect ld_weights_io_req_bits_derived_params_result.in_channels_per_bank, _ld_weights_io_req_bits_derived_params_result_in_channels_per_bank_T_3
node _ld_weights_io_req_bits_derived_params_result_bias_spad_stride_T = mul(loops[loop_requesting_ld_weights_id].inner_bounds.batches, loops[loop_requesting_ld_weights_id].inner_bounds.orows)
node _ld_weights_io_req_bits_derived_params_result_bias_spad_stride_T_1 = mul(_ld_weights_io_req_bits_derived_params_result_bias_spad_stride_T, loops[loop_requesting_ld_weights_id].inner_bounds.ocols)
connect ld_weights_io_req_bits_derived_params_result.bias_spad_stride, _ld_weights_io_req_bits_derived_params_result_bias_spad_stride_T_1
node _ld_weights_io_req_bits_derived_params_result_input_spad_stride_T = dshr(ld_weights_io_req_bits_derived_params_result.irows, loops[loop_requesting_ld_weights_id].downsample)
node _ld_weights_io_req_bits_derived_params_result_input_spad_stride_T_1 = mul(ld_weights_io_req_bits_derived_params_result.ichs, _ld_weights_io_req_bits_derived_params_result_input_spad_stride_T)
node _ld_weights_io_req_bits_derived_params_result_input_spad_stride_T_2 = dshr(ld_weights_io_req_bits_derived_params_result.icols, loops[loop_requesting_ld_weights_id].downsample)
node _ld_weights_io_req_bits_derived_params_result_input_spad_stride_T_3 = mul(_ld_weights_io_req_bits_derived_params_result_input_spad_stride_T_1, _ld_weights_io_req_bits_derived_params_result_input_spad_stride_T_2)
node _ld_weights_io_req_bits_derived_params_result_input_spad_stride_T_4 = dshr(ld_weights_io_req_bits_derived_params_result.irows, loops[loop_requesting_ld_weights_id].downsample)
node _ld_weights_io_req_bits_derived_params_result_input_spad_stride_T_5 = mul(loops[loop_requesting_ld_weights_id].inner_bounds.batches, _ld_weights_io_req_bits_derived_params_result_input_spad_stride_T_4)
node _ld_weights_io_req_bits_derived_params_result_input_spad_stride_T_6 = dshr(ld_weights_io_req_bits_derived_params_result.icols, loops[loop_requesting_ld_weights_id].downsample)
node _ld_weights_io_req_bits_derived_params_result_input_spad_stride_T_7 = mul(_ld_weights_io_req_bits_derived_params_result_input_spad_stride_T_5, _ld_weights_io_req_bits_derived_params_result_input_spad_stride_T_6)
node _ld_weights_io_req_bits_derived_params_result_input_spad_stride_T_8 = mux(loops[loop_requesting_ld_weights_id].trans_input_3120, _ld_weights_io_req_bits_derived_params_result_input_spad_stride_T_3, _ld_weights_io_req_bits_derived_params_result_input_spad_stride_T_7)
connect ld_weights_io_req_bits_derived_params_result.input_spad_stride, _ld_weights_io_req_bits_derived_params_result_input_spad_stride_T_8
node _ld_weights_io_req_bits_derived_params_result_weight_spad_stride_T = mul(loops[loop_requesting_ld_weights_id].inner_bounds.krows, loops[loop_requesting_ld_weights_id].inner_bounds.kcols)
node _ld_weights_io_req_bits_derived_params_result_weight_spad_stride_T_1 = mul(_ld_weights_io_req_bits_derived_params_result_weight_spad_stride_T, loops[loop_requesting_ld_weights_id].inner_bounds.pochs)
node _ld_weights_io_req_bits_derived_params_result_weight_spad_stride_T_2 = mul(loops[loop_requesting_ld_weights_id].inner_bounds.krows, loops[loop_requesting_ld_weights_id].inner_bounds.kcols)
node _ld_weights_io_req_bits_derived_params_result_weight_spad_stride_T_3 = mul(_ld_weights_io_req_bits_derived_params_result_weight_spad_stride_T_2, loops[loop_requesting_ld_weights_id].inner_bounds.kchs)
node _ld_weights_io_req_bits_derived_params_result_weight_spad_stride_T_4 = mux(loops[loop_requesting_ld_weights_id].trans_weight_0132, _ld_weights_io_req_bits_derived_params_result_weight_spad_stride_T_1, _ld_weights_io_req_bits_derived_params_result_weight_spad_stride_T_3)
connect ld_weights_io_req_bits_derived_params_result.weight_spad_stride, _ld_weights_io_req_bits_derived_params_result_weight_spad_stride_T_4
connect ld_weights.io.req.bits.derived_params.weight_spad_stride, ld_weights_io_req_bits_derived_params_result.weight_spad_stride
connect ld_weights.io.req.bits.derived_params.input_spad_stride, ld_weights_io_req_bits_derived_params_result.input_spad_stride
connect ld_weights.io.req.bits.derived_params.bias_spad_stride, ld_weights_io_req_bits_derived_params_result.bias_spad_stride
connect ld_weights.io.req.bits.derived_params.in_channels_per_bank, ld_weights_io_req_bits_derived_params_result.in_channels_per_bank
connect ld_weights.io.req.bits.derived_params.out_channels_per_bank, ld_weights_io_req_bits_derived_params_result.out_channels_per_bank
connect ld_weights.io.req.bits.derived_params.ichs, ld_weights_io_req_bits_derived_params_result.ichs
connect ld_weights.io.req.bits.derived_params.icols_unpadded, ld_weights_io_req_bits_derived_params_result.icols_unpadded
connect ld_weights.io.req.bits.derived_params.irows_unpadded, ld_weights_io_req_bits_derived_params_result.irows_unpadded
connect ld_weights.io.req.bits.derived_params.icols, ld_weights_io_req_bits_derived_params_result.icols
connect ld_weights.io.req.bits.derived_params.irows, ld_weights_io_req_bits_derived_params_result.irows
connect ld_weights.io.req.bits.derived_params.ochs, ld_weights_io_req_bits_derived_params_result.ochs
node _ld_weights_io_req_bits_addr_end_T = eq(loops[loop_requesting_ld_weights_id].b_ex_spad_id, UInt<1>(0h0))
node _ld_weights_io_req_bits_addr_end_T_1 = mul(loops[loop_requesting_ld_weights_id].b_ex_spad_id, UInt<14>(0h2000))
node _ld_weights_io_req_bits_addr_end_T_2 = mux(_ld_weights_io_req_bits_addr_end_T, loops[loop_requesting_ld_weights_id].b_addr_end, _ld_weights_io_req_bits_addr_end_T_1)
connect ld_weights.io.req.bits.addr_end, _ld_weights_io_req_bits_addr_end_T_2
connect ld_weights.io.req.bits.dram_addr, loops[loop_requesting_ld_weights_id].weights_dram_addr
connect ld_weights.io.req.bits.trans_weight_1203, loops[loop_requesting_ld_weights_id].trans_weight_1203
connect ld_weights.io.req.bits.trans_weight_0132, loops[loop_requesting_ld_weights_id].trans_weight_0132
connect ld_weights.io.req.bits.dw, loops[loop_requesting_ld_weights_id].dw
connect ld_weights.io.req.bits.loop_id, loop_requesting_ld_weights_id
node _ld_weights_io_req_valid_T = eq(loops[loop_requesting_ld_weights_id].ld_weights_started, UInt<1>(0h0))
node _ld_weights_io_req_valid_T_1 = and(_ld_weights_io_req_valid_T, loops[loop_requesting_ld_weights_id].configured)
connect ld_weights.io.req.valid, _ld_weights_io_req_valid_T_1
node _T_25 = and(ld_weights.io.req.ready, ld_weights.io.req.valid)
when _T_25 :
connect loops[loop_requesting_ld_weights_id].running, UInt<1>(0h1)
connect loops[loop_requesting_ld_weights_id].ld_weights_started, UInt<1>(0h1)
node loop_requesting_ex_id = mux(loops[head_loop_id].ex_started, tail_loop_id, head_loop_id)
connect ex.io.req.bits.outer_bounds.pool_padding, loops[loop_requesting_ex_id].outer_bounds.pool_padding
connect ex.io.req.bits.outer_bounds.pool_stride, loops[loop_requesting_ex_id].outer_bounds.pool_stride
connect ex.io.req.bits.outer_bounds.pool_size, loops[loop_requesting_ex_id].outer_bounds.pool_size
connect ex.io.req.bits.outer_bounds.kernel_dilation, loops[loop_requesting_ex_id].outer_bounds.kernel_dilation
connect ex.io.req.bits.outer_bounds.kernel_dim, loops[loop_requesting_ex_id].outer_bounds.kernel_dim
connect ex.io.req.bits.outer_bounds.padding, loops[loop_requesting_ex_id].outer_bounds.padding
connect ex.io.req.bits.outer_bounds.stride, loops[loop_requesting_ex_id].outer_bounds.stride
connect ex.io.req.bits.outer_bounds.pool_out_col_dim, loops[loop_requesting_ex_id].outer_bounds.pool_out_col_dim
connect ex.io.req.bits.outer_bounds.pool_out_row_dim, loops[loop_requesting_ex_id].outer_bounds.pool_out_row_dim
connect ex.io.req.bits.outer_bounds.weight_stride, loops[loop_requesting_ex_id].outer_bounds.weight_stride
connect ex.io.req.bits.outer_bounds.in_stride, loops[loop_requesting_ex_id].outer_bounds.in_stride
connect ex.io.req.bits.outer_bounds.out_stride, loops[loop_requesting_ex_id].outer_bounds.out_stride
connect ex.io.req.bits.outer_bounds.out_row_dim, loops[loop_requesting_ex_id].outer_bounds.out_row_dim
connect ex.io.req.bits.outer_bounds.out_col_dim, loops[loop_requesting_ex_id].outer_bounds.out_col_dim
connect ex.io.req.bits.outer_bounds.out_channels, loops[loop_requesting_ex_id].outer_bounds.out_channels
connect ex.io.req.bits.outer_bounds.in_channels, loops[loop_requesting_ex_id].outer_bounds.in_channels
connect ex.io.req.bits.outer_bounds.in_col_dim, loops[loop_requesting_ex_id].outer_bounds.in_col_dim
connect ex.io.req.bits.outer_bounds.in_row_dim, loops[loop_requesting_ex_id].outer_bounds.in_row_dim
connect ex.io.req.bits.outer_bounds.batch_size, loops[loop_requesting_ex_id].outer_bounds.batch_size
connect ex.io.req.bits.inner_bounds.ocols, loops[loop_requesting_ex_id].inner_bounds.ocols
connect ex.io.req.bits.inner_bounds.orows, loops[loop_requesting_ex_id].inner_bounds.orows
connect ex.io.req.bits.inner_bounds.pdpad, loops[loop_requesting_ex_id].inner_bounds.pdpad
connect ex.io.req.bits.inner_bounds.pupad, loops[loop_requesting_ex_id].inner_bounds.pupad
connect ex.io.req.bits.inner_bounds.prad, loops[loop_requesting_ex_id].inner_bounds.prad
connect ex.io.req.bits.inner_bounds.plpad, loops[loop_requesting_ex_id].inner_bounds.plpad
connect ex.io.req.bits.inner_bounds.dpad, loops[loop_requesting_ex_id].inner_bounds.dpad
connect ex.io.req.bits.inner_bounds.upad, loops[loop_requesting_ex_id].inner_bounds.upad
connect ex.io.req.bits.inner_bounds.rpad, loops[loop_requesting_ex_id].inner_bounds.rpad
connect ex.io.req.bits.inner_bounds.lpad, loops[loop_requesting_ex_id].inner_bounds.lpad
connect ex.io.req.bits.inner_bounds.kchs, loops[loop_requesting_ex_id].inner_bounds.kchs
connect ex.io.req.bits.inner_bounds.kcols, loops[loop_requesting_ex_id].inner_bounds.kcols
connect ex.io.req.bits.inner_bounds.krows, loops[loop_requesting_ex_id].inner_bounds.krows
connect ex.io.req.bits.inner_bounds.pochs, loops[loop_requesting_ex_id].inner_bounds.pochs
connect ex.io.req.bits.inner_bounds.pocols, loops[loop_requesting_ex_id].inner_bounds.pocols
connect ex.io.req.bits.inner_bounds.porows, loops[loop_requesting_ex_id].inner_bounds.porows
connect ex.io.req.bits.inner_bounds.batches, loops[loop_requesting_ex_id].inner_bounds.batches
wire ex_io_req_bits_derived_params_result : { ochs : UInt<16>, irows : UInt<16>, icols : UInt<16>, irows_unpadded : UInt<16>, icols_unpadded : UInt<16>, ichs : UInt<16>, out_channels_per_bank : UInt<16>, in_channels_per_bank : UInt<16>, bias_spad_stride : UInt<16>, input_spad_stride : UInt<16>, weight_spad_stride : UInt<16>}
connect ex_io_req_bits_derived_params_result.ochs, loops[loop_requesting_ex_id].inner_bounds.pochs
node _ex_io_req_bits_derived_params_dilated_krows_T = sub(loops[loop_requesting_ex_id].outer_bounds.kernel_dilation, UInt<1>(0h1))
node _ex_io_req_bits_derived_params_dilated_krows_T_1 = tail(_ex_io_req_bits_derived_params_dilated_krows_T, 1)
node _ex_io_req_bits_derived_params_dilated_krows_T_2 = sub(loops[loop_requesting_ex_id].inner_bounds.krows, UInt<1>(0h1))
node _ex_io_req_bits_derived_params_dilated_krows_T_3 = tail(_ex_io_req_bits_derived_params_dilated_krows_T_2, 1)
node _ex_io_req_bits_derived_params_dilated_krows_T_4 = mul(_ex_io_req_bits_derived_params_dilated_krows_T_1, _ex_io_req_bits_derived_params_dilated_krows_T_3)
node _ex_io_req_bits_derived_params_dilated_krows_T_5 = add(loops[loop_requesting_ex_id].inner_bounds.krows, _ex_io_req_bits_derived_params_dilated_krows_T_4)
node ex_io_req_bits_derived_params_dilated_krows = tail(_ex_io_req_bits_derived_params_dilated_krows_T_5, 1)
node _ex_io_req_bits_derived_params_dilated_kcols_T = sub(loops[loop_requesting_ex_id].outer_bounds.kernel_dilation, UInt<1>(0h1))
node _ex_io_req_bits_derived_params_dilated_kcols_T_1 = tail(_ex_io_req_bits_derived_params_dilated_kcols_T, 1)
node _ex_io_req_bits_derived_params_dilated_kcols_T_2 = sub(loops[loop_requesting_ex_id].inner_bounds.kcols, UInt<1>(0h1))
node _ex_io_req_bits_derived_params_dilated_kcols_T_3 = tail(_ex_io_req_bits_derived_params_dilated_kcols_T_2, 1)
node _ex_io_req_bits_derived_params_dilated_kcols_T_4 = mul(_ex_io_req_bits_derived_params_dilated_kcols_T_1, _ex_io_req_bits_derived_params_dilated_kcols_T_3)
node _ex_io_req_bits_derived_params_dilated_kcols_T_5 = add(loops[loop_requesting_ex_id].inner_bounds.kcols, _ex_io_req_bits_derived_params_dilated_kcols_T_4)
node ex_io_req_bits_derived_params_dilated_kcols = tail(_ex_io_req_bits_derived_params_dilated_kcols_T_5, 1)
node _ex_io_req_bits_derived_params_irows_without_dilation_T = mul(loops[loop_requesting_ex_id].inner_bounds.orows, loops[loop_requesting_ex_id].outer_bounds.stride)
node _ex_io_req_bits_derived_params_irows_without_dilation_T_1 = add(_ex_io_req_bits_derived_params_irows_without_dilation_T, ex_io_req_bits_derived_params_dilated_krows)
node _ex_io_req_bits_derived_params_irows_without_dilation_T_2 = sub(_ex_io_req_bits_derived_params_irows_without_dilation_T_1, UInt<1>(0h1))
node ex_io_req_bits_derived_params_irows_without_dilation = asUInt(_ex_io_req_bits_derived_params_irows_without_dilation_T_2)
node _ex_io_req_bits_derived_params_icols_without_dilation_T = mul(loops[loop_requesting_ex_id].inner_bounds.ocols, loops[loop_requesting_ex_id].outer_bounds.stride)
node _ex_io_req_bits_derived_params_icols_without_dilation_T_1 = add(_ex_io_req_bits_derived_params_icols_without_dilation_T, ex_io_req_bits_derived_params_dilated_kcols)
node _ex_io_req_bits_derived_params_icols_without_dilation_T_2 = sub(_ex_io_req_bits_derived_params_icols_without_dilation_T_1, UInt<1>(0h1))
node ex_io_req_bits_derived_params_icols_without_dilation = asUInt(_ex_io_req_bits_derived_params_icols_without_dilation_T_2)
node _ex_io_req_bits_derived_params_irows_unpadded_without_dilation_T = sub(ex_io_req_bits_derived_params_irows_without_dilation, loops[loop_requesting_ex_id].inner_bounds.upad)
node _ex_io_req_bits_derived_params_irows_unpadded_without_dilation_T_1 = asUInt(_ex_io_req_bits_derived_params_irows_unpadded_without_dilation_T)
node _ex_io_req_bits_derived_params_irows_unpadded_without_dilation_T_2 = sub(_ex_io_req_bits_derived_params_irows_unpadded_without_dilation_T_1, loops[loop_requesting_ex_id].inner_bounds.dpad)
node ex_io_req_bits_derived_params_irows_unpadded_without_dilation = asUInt(_ex_io_req_bits_derived_params_irows_unpadded_without_dilation_T_2)
node _ex_io_req_bits_derived_params_icols_unpadded_without_dilation_T = sub(ex_io_req_bits_derived_params_icols_without_dilation, loops[loop_requesting_ex_id].inner_bounds.lpad)
node _ex_io_req_bits_derived_params_icols_unpadded_without_dilation_T_1 = asUInt(_ex_io_req_bits_derived_params_icols_unpadded_without_dilation_T)
node _ex_io_req_bits_derived_params_icols_unpadded_without_dilation_T_2 = sub(_ex_io_req_bits_derived_params_icols_unpadded_without_dilation_T_1, loops[loop_requesting_ex_id].inner_bounds.rpad)
node ex_io_req_bits_derived_params_icols_unpadded_without_dilation = asUInt(_ex_io_req_bits_derived_params_icols_unpadded_without_dilation_T_2)
node _ex_io_req_bits_derived_params_irows_unpadded_T = add(ex_io_req_bits_derived_params_irows_unpadded_without_dilation, loops[loop_requesting_ex_id].input_dilated)
node ex_io_req_bits_derived_params_irows_unpadded = dshr(_ex_io_req_bits_derived_params_irows_unpadded_T, loops[loop_requesting_ex_id].input_dilated)
node _ex_io_req_bits_derived_params_icols_unpadded_T = add(ex_io_req_bits_derived_params_icols_unpadded_without_dilation, loops[loop_requesting_ex_id].input_dilated)
node ex_io_req_bits_derived_params_icols_unpadded = dshr(_ex_io_req_bits_derived_params_icols_unpadded_T, loops[loop_requesting_ex_id].input_dilated)
node _ex_io_req_bits_derived_params_result_irows_T = add(loops[loop_requesting_ex_id].inner_bounds.upad, loops[loop_requesting_ex_id].input_dilated)
node _ex_io_req_bits_derived_params_result_irows_T_1 = dshr(_ex_io_req_bits_derived_params_result_irows_T, loops[loop_requesting_ex_id].input_dilated)
node _ex_io_req_bits_derived_params_result_irows_T_2 = add(ex_io_req_bits_derived_params_irows_unpadded, _ex_io_req_bits_derived_params_result_irows_T_1)
node _ex_io_req_bits_derived_params_result_irows_T_3 = add(loops[loop_requesting_ex_id].inner_bounds.dpad, loops[loop_requesting_ex_id].input_dilated)
node _ex_io_req_bits_derived_params_result_irows_T_4 = dshr(_ex_io_req_bits_derived_params_result_irows_T_3, loops[loop_requesting_ex_id].input_dilated)
node _ex_io_req_bits_derived_params_result_irows_T_5 = add(_ex_io_req_bits_derived_params_result_irows_T_2, _ex_io_req_bits_derived_params_result_irows_T_4)
node _ex_io_req_bits_derived_params_result_irows_T_6 = mux(loops[loop_requesting_ex_id].input_dilated, _ex_io_req_bits_derived_params_result_irows_T_5, ex_io_req_bits_derived_params_irows_without_dilation)
connect ex_io_req_bits_derived_params_result.irows, _ex_io_req_bits_derived_params_result_irows_T_6
node _ex_io_req_bits_derived_params_result_icols_T = add(loops[loop_requesting_ex_id].inner_bounds.lpad, loops[loop_requesting_ex_id].input_dilated)
node _ex_io_req_bits_derived_params_result_icols_T_1 = dshr(_ex_io_req_bits_derived_params_result_icols_T, loops[loop_requesting_ex_id].input_dilated)
node _ex_io_req_bits_derived_params_result_icols_T_2 = add(ex_io_req_bits_derived_params_icols_unpadded, _ex_io_req_bits_derived_params_result_icols_T_1)
node _ex_io_req_bits_derived_params_result_icols_T_3 = add(loops[loop_requesting_ex_id].inner_bounds.rpad, loops[loop_requesting_ex_id].input_dilated)
node _ex_io_req_bits_derived_params_result_icols_T_4 = dshr(_ex_io_req_bits_derived_params_result_icols_T_3, loops[loop_requesting_ex_id].input_dilated)
node _ex_io_req_bits_derived_params_result_icols_T_5 = add(_ex_io_req_bits_derived_params_result_icols_T_2, _ex_io_req_bits_derived_params_result_icols_T_4)
node _ex_io_req_bits_derived_params_result_icols_T_6 = mux(loops[loop_requesting_ex_id].input_dilated, _ex_io_req_bits_derived_params_result_icols_T_5, ex_io_req_bits_derived_params_icols_without_dilation)
connect ex_io_req_bits_derived_params_result.icols, _ex_io_req_bits_derived_params_result_icols_T_6
connect ex_io_req_bits_derived_params_result.irows_unpadded, ex_io_req_bits_derived_params_irows_unpadded
connect ex_io_req_bits_derived_params_result.icols_unpadded, ex_io_req_bits_derived_params_icols_unpadded
connect ex_io_req_bits_derived_params_result.ichs, loops[loop_requesting_ex_id].inner_bounds.kchs
node _ex_io_req_bits_derived_params_result_out_channels_per_bank_T = div(ex_io_req_bits_derived_params_result.ochs, UInt<16>(0h4))
node _ex_io_req_bits_derived_params_result_out_channels_per_bank_T_1 = rem(ex_io_req_bits_derived_params_result.ochs, UInt<3>(0h4))
node _ex_io_req_bits_derived_params_result_out_channels_per_bank_T_2 = neq(_ex_io_req_bits_derived_params_result_out_channels_per_bank_T_1, UInt<1>(0h0))
node _ex_io_req_bits_derived_params_result_out_channels_per_bank_T_3 = add(_ex_io_req_bits_derived_params_result_out_channels_per_bank_T, _ex_io_req_bits_derived_params_result_out_channels_per_bank_T_2)
connect ex_io_req_bits_derived_params_result.out_channels_per_bank, _ex_io_req_bits_derived_params_result_out_channels_per_bank_T_3
node _ex_io_req_bits_derived_params_result_in_channels_per_bank_T = div(ex_io_req_bits_derived_params_result.ichs, UInt<16>(0h4))
node _ex_io_req_bits_derived_params_result_in_channels_per_bank_T_1 = rem(ex_io_req_bits_derived_params_result.ichs, UInt<3>(0h4))
node _ex_io_req_bits_derived_params_result_in_channels_per_bank_T_2 = neq(_ex_io_req_bits_derived_params_result_in_channels_per_bank_T_1, UInt<1>(0h0))
node _ex_io_req_bits_derived_params_result_in_channels_per_bank_T_3 = add(_ex_io_req_bits_derived_params_result_in_channels_per_bank_T, _ex_io_req_bits_derived_params_result_in_channels_per_bank_T_2)
connect ex_io_req_bits_derived_params_result.in_channels_per_bank, _ex_io_req_bits_derived_params_result_in_channels_per_bank_T_3
node _ex_io_req_bits_derived_params_result_bias_spad_stride_T = mul(loops[loop_requesting_ex_id].inner_bounds.batches, loops[loop_requesting_ex_id].inner_bounds.orows)
node _ex_io_req_bits_derived_params_result_bias_spad_stride_T_1 = mul(_ex_io_req_bits_derived_params_result_bias_spad_stride_T, loops[loop_requesting_ex_id].inner_bounds.ocols)
connect ex_io_req_bits_derived_params_result.bias_spad_stride, _ex_io_req_bits_derived_params_result_bias_spad_stride_T_1
node _ex_io_req_bits_derived_params_result_input_spad_stride_T = dshr(ex_io_req_bits_derived_params_result.irows, loops[loop_requesting_ex_id].downsample)
node _ex_io_req_bits_derived_params_result_input_spad_stride_T_1 = mul(ex_io_req_bits_derived_params_result.ichs, _ex_io_req_bits_derived_params_result_input_spad_stride_T)
node _ex_io_req_bits_derived_params_result_input_spad_stride_T_2 = dshr(ex_io_req_bits_derived_params_result.icols, loops[loop_requesting_ex_id].downsample)
node _ex_io_req_bits_derived_params_result_input_spad_stride_T_3 = mul(_ex_io_req_bits_derived_params_result_input_spad_stride_T_1, _ex_io_req_bits_derived_params_result_input_spad_stride_T_2)
node _ex_io_req_bits_derived_params_result_input_spad_stride_T_4 = dshr(ex_io_req_bits_derived_params_result.irows, loops[loop_requesting_ex_id].downsample)
node _ex_io_req_bits_derived_params_result_input_spad_stride_T_5 = mul(loops[loop_requesting_ex_id].inner_bounds.batches, _ex_io_req_bits_derived_params_result_input_spad_stride_T_4)
node _ex_io_req_bits_derived_params_result_input_spad_stride_T_6 = dshr(ex_io_req_bits_derived_params_result.icols, loops[loop_requesting_ex_id].downsample)
node _ex_io_req_bits_derived_params_result_input_spad_stride_T_7 = mul(_ex_io_req_bits_derived_params_result_input_spad_stride_T_5, _ex_io_req_bits_derived_params_result_input_spad_stride_T_6)
node _ex_io_req_bits_derived_params_result_input_spad_stride_T_8 = mux(loops[loop_requesting_ex_id].trans_input_3120, _ex_io_req_bits_derived_params_result_input_spad_stride_T_3, _ex_io_req_bits_derived_params_result_input_spad_stride_T_7)
connect ex_io_req_bits_derived_params_result.input_spad_stride, _ex_io_req_bits_derived_params_result_input_spad_stride_T_8
node _ex_io_req_bits_derived_params_result_weight_spad_stride_T = mul(loops[loop_requesting_ex_id].inner_bounds.krows, loops[loop_requesting_ex_id].inner_bounds.kcols)
node _ex_io_req_bits_derived_params_result_weight_spad_stride_T_1 = mul(_ex_io_req_bits_derived_params_result_weight_spad_stride_T, loops[loop_requesting_ex_id].inner_bounds.pochs)
node _ex_io_req_bits_derived_params_result_weight_spad_stride_T_2 = mul(loops[loop_requesting_ex_id].inner_bounds.krows, loops[loop_requesting_ex_id].inner_bounds.kcols)
node _ex_io_req_bits_derived_params_result_weight_spad_stride_T_3 = mul(_ex_io_req_bits_derived_params_result_weight_spad_stride_T_2, loops[loop_requesting_ex_id].inner_bounds.kchs)
node _ex_io_req_bits_derived_params_result_weight_spad_stride_T_4 = mux(loops[loop_requesting_ex_id].trans_weight_0132, _ex_io_req_bits_derived_params_result_weight_spad_stride_T_1, _ex_io_req_bits_derived_params_result_weight_spad_stride_T_3)
connect ex_io_req_bits_derived_params_result.weight_spad_stride, _ex_io_req_bits_derived_params_result_weight_spad_stride_T_4
connect ex.io.req.bits.derived_params.weight_spad_stride, ex_io_req_bits_derived_params_result.weight_spad_stride
connect ex.io.req.bits.derived_params.input_spad_stride, ex_io_req_bits_derived_params_result.input_spad_stride
connect ex.io.req.bits.derived_params.bias_spad_stride, ex_io_req_bits_derived_params_result.bias_spad_stride
connect ex.io.req.bits.derived_params.in_channels_per_bank, ex_io_req_bits_derived_params_result.in_channels_per_bank
connect ex.io.req.bits.derived_params.out_channels_per_bank, ex_io_req_bits_derived_params_result.out_channels_per_bank
connect ex.io.req.bits.derived_params.ichs, ex_io_req_bits_derived_params_result.ichs
connect ex.io.req.bits.derived_params.icols_unpadded, ex_io_req_bits_derived_params_result.icols_unpadded
connect ex.io.req.bits.derived_params.irows_unpadded, ex_io_req_bits_derived_params_result.irows_unpadded
connect ex.io.req.bits.derived_params.icols, ex_io_req_bits_derived_params_result.icols
connect ex.io.req.bits.derived_params.irows, ex_io_req_bits_derived_params_result.irows
connect ex.io.req.bits.derived_params.ochs, ex_io_req_bits_derived_params_result.ochs
node _ex_io_req_bits_a_addr_start_T = eq(loops[loop_requesting_ex_id].a_ex_spad_id, UInt<1>(0h0))
node _ex_io_req_bits_a_addr_start_T_1 = sub(loops[loop_requesting_ex_id].a_ex_spad_id, UInt<1>(0h1))
node _ex_io_req_bits_a_addr_start_T_2 = tail(_ex_io_req_bits_a_addr_start_T_1, 1)
node _ex_io_req_bits_a_addr_start_T_3 = mul(_ex_io_req_bits_a_addr_start_T_2, UInt<14>(0h2000))
node _ex_io_req_bits_a_addr_start_T_4 = mux(_ex_io_req_bits_a_addr_start_T, loops[loop_requesting_ex_id].a_addr_start, _ex_io_req_bits_a_addr_start_T_3)
connect ex.io.req.bits.a_addr_start, _ex_io_req_bits_a_addr_start_T_4
node _ex_io_req_bits_b_addr_end_T = eq(loops[loop_requesting_ex_id].b_ex_spad_id, UInt<1>(0h0))
node _ex_io_req_bits_b_addr_end_T_1 = mul(loops[loop_requesting_ex_id].b_ex_spad_id, UInt<14>(0h2000))
node _ex_io_req_bits_b_addr_end_T_2 = mux(_ex_io_req_bits_b_addr_end_T, loops[loop_requesting_ex_id].b_addr_end, _ex_io_req_bits_b_addr_end_T_1)
connect ex.io.req.bits.b_addr_end, _ex_io_req_bits_b_addr_end_T_2
connect ex.io.req.bits.c_addr_start, ex_c_addr_start
connect ex.io.req.bits.wrot180, loops[loop_requesting_ex_id].wrot180
connect ex.io.req.bits.downsample, loops[loop_requesting_ex_id].downsample
connect ex.io.req.bits.max_pixels_per_row, loops[loop_requesting_ex_id].max_pixels_per_row
connect ex.io.req.bits.input_dilated, loops[loop_requesting_ex_id].input_dilated
connect ex.io.req.bits.trans_weight_0132, loops[loop_requesting_ex_id].trans_weight_0132
connect ex.io.req.bits.trans_input_3120, loops[loop_requesting_ex_id].trans_input_3120
connect ex.io.req.bits.loop_id, loop_requesting_ex_id
node _ex_io_req_valid_T = eq(loops[loop_requesting_ex_id].ex_started, UInt<1>(0h0))
node _ex_io_req_valid_T_1 = and(_ex_io_req_valid_T, loops[loop_requesting_ex_id].ld_bias_started)
node _ex_io_req_valid_T_2 = and(_ex_io_req_valid_T_1, loops[loop_requesting_ex_id].ld_input_started)
node _ex_io_req_valid_T_3 = and(_ex_io_req_valid_T_2, loops[loop_requesting_ex_id].ld_weights_started)
node _ex_io_req_valid_T_4 = and(_ex_io_req_valid_T_3, loops[loop_requesting_ex_id].configured)
connect ex.io.req.valid, _ex_io_req_valid_T_4
node _T_26 = and(ex.io.req.ready, ex.io.req.valid)
when _T_26 :
connect loops[loop_requesting_ex_id].running, UInt<1>(0h1)
connect loops[loop_requesting_ex_id].ex_started, UInt<1>(0h1)
node _T_27 = neq(loops[loop_requesting_ex_id].output_dram_addr, UInt<1>(0h0))
when _T_27 :
node _ex_c_addr_start_max_T = sub(UInt<13>(0h1000), UInt<1>(0h1))
node ex_c_addr_start_max = tail(_ex_c_addr_start_max_T, 1)
node _ex_c_addr_start_T = add(ex_c_addr_start, UInt<12>(0h800))
node _ex_c_addr_start_T_1 = tail(_ex_c_addr_start_T, 1)
node _ex_c_addr_start_T_2 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _ex_c_addr_start_T_3 = add(ex_c_addr_start, UInt<12>(0h800))
node _ex_c_addr_start_T_4 = gt(_ex_c_addr_start_T_3, ex_c_addr_start_max)
node _ex_c_addr_start_T_5 = mux(_ex_c_addr_start_T_4, UInt<1>(0h0), _ex_c_addr_start_T_1)
node _ex_c_addr_start_T_6 = mux(_ex_c_addr_start_T_2, ex_c_addr_start, _ex_c_addr_start_T_5)
connect ex_c_addr_start, _ex_c_addr_start_T_6
node loop_requesting_st_id = mux(loops[head_loop_id].st_started, tail_loop_id, head_loop_id)
connect st.io.req.bits.outer_bounds.pool_padding, loops[loop_requesting_st_id].outer_bounds.pool_padding
connect st.io.req.bits.outer_bounds.pool_stride, loops[loop_requesting_st_id].outer_bounds.pool_stride
connect st.io.req.bits.outer_bounds.pool_size, loops[loop_requesting_st_id].outer_bounds.pool_size
connect st.io.req.bits.outer_bounds.kernel_dilation, loops[loop_requesting_st_id].outer_bounds.kernel_dilation
connect st.io.req.bits.outer_bounds.kernel_dim, loops[loop_requesting_st_id].outer_bounds.kernel_dim
connect st.io.req.bits.outer_bounds.padding, loops[loop_requesting_st_id].outer_bounds.padding
connect st.io.req.bits.outer_bounds.stride, loops[loop_requesting_st_id].outer_bounds.stride
connect st.io.req.bits.outer_bounds.pool_out_col_dim, loops[loop_requesting_st_id].outer_bounds.pool_out_col_dim
connect st.io.req.bits.outer_bounds.pool_out_row_dim, loops[loop_requesting_st_id].outer_bounds.pool_out_row_dim
connect st.io.req.bits.outer_bounds.weight_stride, loops[loop_requesting_st_id].outer_bounds.weight_stride
connect st.io.req.bits.outer_bounds.in_stride, loops[loop_requesting_st_id].outer_bounds.in_stride
connect st.io.req.bits.outer_bounds.out_stride, loops[loop_requesting_st_id].outer_bounds.out_stride
connect st.io.req.bits.outer_bounds.out_row_dim, loops[loop_requesting_st_id].outer_bounds.out_row_dim
connect st.io.req.bits.outer_bounds.out_col_dim, loops[loop_requesting_st_id].outer_bounds.out_col_dim
connect st.io.req.bits.outer_bounds.out_channels, loops[loop_requesting_st_id].outer_bounds.out_channels
connect st.io.req.bits.outer_bounds.in_channels, loops[loop_requesting_st_id].outer_bounds.in_channels
connect st.io.req.bits.outer_bounds.in_col_dim, loops[loop_requesting_st_id].outer_bounds.in_col_dim
connect st.io.req.bits.outer_bounds.in_row_dim, loops[loop_requesting_st_id].outer_bounds.in_row_dim
connect st.io.req.bits.outer_bounds.batch_size, loops[loop_requesting_st_id].outer_bounds.batch_size
connect st.io.req.bits.inner_bounds.ocols, loops[loop_requesting_st_id].inner_bounds.ocols
connect st.io.req.bits.inner_bounds.orows, loops[loop_requesting_st_id].inner_bounds.orows
connect st.io.req.bits.inner_bounds.pdpad, loops[loop_requesting_st_id].inner_bounds.pdpad
connect st.io.req.bits.inner_bounds.pupad, loops[loop_requesting_st_id].inner_bounds.pupad
connect st.io.req.bits.inner_bounds.prad, loops[loop_requesting_st_id].inner_bounds.prad
connect st.io.req.bits.inner_bounds.plpad, loops[loop_requesting_st_id].inner_bounds.plpad
connect st.io.req.bits.inner_bounds.dpad, loops[loop_requesting_st_id].inner_bounds.dpad
connect st.io.req.bits.inner_bounds.upad, loops[loop_requesting_st_id].inner_bounds.upad
connect st.io.req.bits.inner_bounds.rpad, loops[loop_requesting_st_id].inner_bounds.rpad
connect st.io.req.bits.inner_bounds.lpad, loops[loop_requesting_st_id].inner_bounds.lpad
connect st.io.req.bits.inner_bounds.kchs, loops[loop_requesting_st_id].inner_bounds.kchs
connect st.io.req.bits.inner_bounds.kcols, loops[loop_requesting_st_id].inner_bounds.kcols
connect st.io.req.bits.inner_bounds.krows, loops[loop_requesting_st_id].inner_bounds.krows
connect st.io.req.bits.inner_bounds.pochs, loops[loop_requesting_st_id].inner_bounds.pochs
connect st.io.req.bits.inner_bounds.pocols, loops[loop_requesting_st_id].inner_bounds.pocols
connect st.io.req.bits.inner_bounds.porows, loops[loop_requesting_st_id].inner_bounds.porows
connect st.io.req.bits.inner_bounds.batches, loops[loop_requesting_st_id].inner_bounds.batches
wire st_io_req_bits_derived_params_result : { ochs : UInt<16>, irows : UInt<16>, icols : UInt<16>, irows_unpadded : UInt<16>, icols_unpadded : UInt<16>, ichs : UInt<16>, out_channels_per_bank : UInt<16>, in_channels_per_bank : UInt<16>, bias_spad_stride : UInt<16>, input_spad_stride : UInt<16>, weight_spad_stride : UInt<16>}
connect st_io_req_bits_derived_params_result.ochs, loops[loop_requesting_st_id].inner_bounds.pochs
node _st_io_req_bits_derived_params_dilated_krows_T = sub(loops[loop_requesting_st_id].outer_bounds.kernel_dilation, UInt<1>(0h1))
node _st_io_req_bits_derived_params_dilated_krows_T_1 = tail(_st_io_req_bits_derived_params_dilated_krows_T, 1)
node _st_io_req_bits_derived_params_dilated_krows_T_2 = sub(loops[loop_requesting_st_id].inner_bounds.krows, UInt<1>(0h1))
node _st_io_req_bits_derived_params_dilated_krows_T_3 = tail(_st_io_req_bits_derived_params_dilated_krows_T_2, 1)
node _st_io_req_bits_derived_params_dilated_krows_T_4 = mul(_st_io_req_bits_derived_params_dilated_krows_T_1, _st_io_req_bits_derived_params_dilated_krows_T_3)
node _st_io_req_bits_derived_params_dilated_krows_T_5 = add(loops[loop_requesting_st_id].inner_bounds.krows, _st_io_req_bits_derived_params_dilated_krows_T_4)
node st_io_req_bits_derived_params_dilated_krows = tail(_st_io_req_bits_derived_params_dilated_krows_T_5, 1)
node _st_io_req_bits_derived_params_dilated_kcols_T = sub(loops[loop_requesting_st_id].outer_bounds.kernel_dilation, UInt<1>(0h1))
node _st_io_req_bits_derived_params_dilated_kcols_T_1 = tail(_st_io_req_bits_derived_params_dilated_kcols_T, 1)
node _st_io_req_bits_derived_params_dilated_kcols_T_2 = sub(loops[loop_requesting_st_id].inner_bounds.kcols, UInt<1>(0h1))
node _st_io_req_bits_derived_params_dilated_kcols_T_3 = tail(_st_io_req_bits_derived_params_dilated_kcols_T_2, 1)
node _st_io_req_bits_derived_params_dilated_kcols_T_4 = mul(_st_io_req_bits_derived_params_dilated_kcols_T_1, _st_io_req_bits_derived_params_dilated_kcols_T_3)
node _st_io_req_bits_derived_params_dilated_kcols_T_5 = add(loops[loop_requesting_st_id].inner_bounds.kcols, _st_io_req_bits_derived_params_dilated_kcols_T_4)
node st_io_req_bits_derived_params_dilated_kcols = tail(_st_io_req_bits_derived_params_dilated_kcols_T_5, 1)
node _st_io_req_bits_derived_params_irows_without_dilation_T = mul(loops[loop_requesting_st_id].inner_bounds.orows, loops[loop_requesting_st_id].outer_bounds.stride)
node _st_io_req_bits_derived_params_irows_without_dilation_T_1 = add(_st_io_req_bits_derived_params_irows_without_dilation_T, st_io_req_bits_derived_params_dilated_krows)
node _st_io_req_bits_derived_params_irows_without_dilation_T_2 = sub(_st_io_req_bits_derived_params_irows_without_dilation_T_1, UInt<1>(0h1))
node st_io_req_bits_derived_params_irows_without_dilation = asUInt(_st_io_req_bits_derived_params_irows_without_dilation_T_2)
node _st_io_req_bits_derived_params_icols_without_dilation_T = mul(loops[loop_requesting_st_id].inner_bounds.ocols, loops[loop_requesting_st_id].outer_bounds.stride)
node _st_io_req_bits_derived_params_icols_without_dilation_T_1 = add(_st_io_req_bits_derived_params_icols_without_dilation_T, st_io_req_bits_derived_params_dilated_kcols)
node _st_io_req_bits_derived_params_icols_without_dilation_T_2 = sub(_st_io_req_bits_derived_params_icols_without_dilation_T_1, UInt<1>(0h1))
node st_io_req_bits_derived_params_icols_without_dilation = asUInt(_st_io_req_bits_derived_params_icols_without_dilation_T_2)
node _st_io_req_bits_derived_params_irows_unpadded_without_dilation_T = sub(st_io_req_bits_derived_params_irows_without_dilation, loops[loop_requesting_st_id].inner_bounds.upad)
node _st_io_req_bits_derived_params_irows_unpadded_without_dilation_T_1 = asUInt(_st_io_req_bits_derived_params_irows_unpadded_without_dilation_T)
node _st_io_req_bits_derived_params_irows_unpadded_without_dilation_T_2 = sub(_st_io_req_bits_derived_params_irows_unpadded_without_dilation_T_1, loops[loop_requesting_st_id].inner_bounds.dpad)
node st_io_req_bits_derived_params_irows_unpadded_without_dilation = asUInt(_st_io_req_bits_derived_params_irows_unpadded_without_dilation_T_2)
node _st_io_req_bits_derived_params_icols_unpadded_without_dilation_T = sub(st_io_req_bits_derived_params_icols_without_dilation, loops[loop_requesting_st_id].inner_bounds.lpad)
node _st_io_req_bits_derived_params_icols_unpadded_without_dilation_T_1 = asUInt(_st_io_req_bits_derived_params_icols_unpadded_without_dilation_T)
node _st_io_req_bits_derived_params_icols_unpadded_without_dilation_T_2 = sub(_st_io_req_bits_derived_params_icols_unpadded_without_dilation_T_1, loops[loop_requesting_st_id].inner_bounds.rpad)
node st_io_req_bits_derived_params_icols_unpadded_without_dilation = asUInt(_st_io_req_bits_derived_params_icols_unpadded_without_dilation_T_2)
node _st_io_req_bits_derived_params_irows_unpadded_T = add(st_io_req_bits_derived_params_irows_unpadded_without_dilation, loops[loop_requesting_st_id].input_dilated)
node st_io_req_bits_derived_params_irows_unpadded = dshr(_st_io_req_bits_derived_params_irows_unpadded_T, loops[loop_requesting_st_id].input_dilated)
node _st_io_req_bits_derived_params_icols_unpadded_T = add(st_io_req_bits_derived_params_icols_unpadded_without_dilation, loops[loop_requesting_st_id].input_dilated)
node st_io_req_bits_derived_params_icols_unpadded = dshr(_st_io_req_bits_derived_params_icols_unpadded_T, loops[loop_requesting_st_id].input_dilated)
node _st_io_req_bits_derived_params_result_irows_T = add(loops[loop_requesting_st_id].inner_bounds.upad, loops[loop_requesting_st_id].input_dilated)
node _st_io_req_bits_derived_params_result_irows_T_1 = dshr(_st_io_req_bits_derived_params_result_irows_T, loops[loop_requesting_st_id].input_dilated)
node _st_io_req_bits_derived_params_result_irows_T_2 = add(st_io_req_bits_derived_params_irows_unpadded, _st_io_req_bits_derived_params_result_irows_T_1)
node _st_io_req_bits_derived_params_result_irows_T_3 = add(loops[loop_requesting_st_id].inner_bounds.dpad, loops[loop_requesting_st_id].input_dilated)
node _st_io_req_bits_derived_params_result_irows_T_4 = dshr(_st_io_req_bits_derived_params_result_irows_T_3, loops[loop_requesting_st_id].input_dilated)
node _st_io_req_bits_derived_params_result_irows_T_5 = add(_st_io_req_bits_derived_params_result_irows_T_2, _st_io_req_bits_derived_params_result_irows_T_4)
node _st_io_req_bits_derived_params_result_irows_T_6 = mux(loops[loop_requesting_st_id].input_dilated, _st_io_req_bits_derived_params_result_irows_T_5, st_io_req_bits_derived_params_irows_without_dilation)
connect st_io_req_bits_derived_params_result.irows, _st_io_req_bits_derived_params_result_irows_T_6
node _st_io_req_bits_derived_params_result_icols_T = add(loops[loop_requesting_st_id].inner_bounds.lpad, loops[loop_requesting_st_id].input_dilated)
node _st_io_req_bits_derived_params_result_icols_T_1 = dshr(_st_io_req_bits_derived_params_result_icols_T, loops[loop_requesting_st_id].input_dilated)
node _st_io_req_bits_derived_params_result_icols_T_2 = add(st_io_req_bits_derived_params_icols_unpadded, _st_io_req_bits_derived_params_result_icols_T_1)
node _st_io_req_bits_derived_params_result_icols_T_3 = add(loops[loop_requesting_st_id].inner_bounds.rpad, loops[loop_requesting_st_id].input_dilated)
node _st_io_req_bits_derived_params_result_icols_T_4 = dshr(_st_io_req_bits_derived_params_result_icols_T_3, loops[loop_requesting_st_id].input_dilated)
node _st_io_req_bits_derived_params_result_icols_T_5 = add(_st_io_req_bits_derived_params_result_icols_T_2, _st_io_req_bits_derived_params_result_icols_T_4)
node _st_io_req_bits_derived_params_result_icols_T_6 = mux(loops[loop_requesting_st_id].input_dilated, _st_io_req_bits_derived_params_result_icols_T_5, st_io_req_bits_derived_params_icols_without_dilation)
connect st_io_req_bits_derived_params_result.icols, _st_io_req_bits_derived_params_result_icols_T_6
connect st_io_req_bits_derived_params_result.irows_unpadded, st_io_req_bits_derived_params_irows_unpadded
connect st_io_req_bits_derived_params_result.icols_unpadded, st_io_req_bits_derived_params_icols_unpadded
connect st_io_req_bits_derived_params_result.ichs, loops[loop_requesting_st_id].inner_bounds.kchs
node _st_io_req_bits_derived_params_result_out_channels_per_bank_T = div(st_io_req_bits_derived_params_result.ochs, UInt<16>(0h4))
node _st_io_req_bits_derived_params_result_out_channels_per_bank_T_1 = rem(st_io_req_bits_derived_params_result.ochs, UInt<3>(0h4))
node _st_io_req_bits_derived_params_result_out_channels_per_bank_T_2 = neq(_st_io_req_bits_derived_params_result_out_channels_per_bank_T_1, UInt<1>(0h0))
node _st_io_req_bits_derived_params_result_out_channels_per_bank_T_3 = add(_st_io_req_bits_derived_params_result_out_channels_per_bank_T, _st_io_req_bits_derived_params_result_out_channels_per_bank_T_2)
connect st_io_req_bits_derived_params_result.out_channels_per_bank, _st_io_req_bits_derived_params_result_out_channels_per_bank_T_3
node _st_io_req_bits_derived_params_result_in_channels_per_bank_T = div(st_io_req_bits_derived_params_result.ichs, UInt<16>(0h4))
node _st_io_req_bits_derived_params_result_in_channels_per_bank_T_1 = rem(st_io_req_bits_derived_params_result.ichs, UInt<3>(0h4))
node _st_io_req_bits_derived_params_result_in_channels_per_bank_T_2 = neq(_st_io_req_bits_derived_params_result_in_channels_per_bank_T_1, UInt<1>(0h0))
node _st_io_req_bits_derived_params_result_in_channels_per_bank_T_3 = add(_st_io_req_bits_derived_params_result_in_channels_per_bank_T, _st_io_req_bits_derived_params_result_in_channels_per_bank_T_2)
connect st_io_req_bits_derived_params_result.in_channels_per_bank, _st_io_req_bits_derived_params_result_in_channels_per_bank_T_3
node _st_io_req_bits_derived_params_result_bias_spad_stride_T = mul(loops[loop_requesting_st_id].inner_bounds.batches, loops[loop_requesting_st_id].inner_bounds.orows)
node _st_io_req_bits_derived_params_result_bias_spad_stride_T_1 = mul(_st_io_req_bits_derived_params_result_bias_spad_stride_T, loops[loop_requesting_st_id].inner_bounds.ocols)
connect st_io_req_bits_derived_params_result.bias_spad_stride, _st_io_req_bits_derived_params_result_bias_spad_stride_T_1
node _st_io_req_bits_derived_params_result_input_spad_stride_T = dshr(st_io_req_bits_derived_params_result.irows, loops[loop_requesting_st_id].downsample)
node _st_io_req_bits_derived_params_result_input_spad_stride_T_1 = mul(st_io_req_bits_derived_params_result.ichs, _st_io_req_bits_derived_params_result_input_spad_stride_T)
node _st_io_req_bits_derived_params_result_input_spad_stride_T_2 = dshr(st_io_req_bits_derived_params_result.icols, loops[loop_requesting_st_id].downsample)
node _st_io_req_bits_derived_params_result_input_spad_stride_T_3 = mul(_st_io_req_bits_derived_params_result_input_spad_stride_T_1, _st_io_req_bits_derived_params_result_input_spad_stride_T_2)
node _st_io_req_bits_derived_params_result_input_spad_stride_T_4 = dshr(st_io_req_bits_derived_params_result.irows, loops[loop_requesting_st_id].downsample)
node _st_io_req_bits_derived_params_result_input_spad_stride_T_5 = mul(loops[loop_requesting_st_id].inner_bounds.batches, _st_io_req_bits_derived_params_result_input_spad_stride_T_4)
node _st_io_req_bits_derived_params_result_input_spad_stride_T_6 = dshr(st_io_req_bits_derived_params_result.icols, loops[loop_requesting_st_id].downsample)
node _st_io_req_bits_derived_params_result_input_spad_stride_T_7 = mul(_st_io_req_bits_derived_params_result_input_spad_stride_T_5, _st_io_req_bits_derived_params_result_input_spad_stride_T_6)
node _st_io_req_bits_derived_params_result_input_spad_stride_T_8 = mux(loops[loop_requesting_st_id].trans_input_3120, _st_io_req_bits_derived_params_result_input_spad_stride_T_3, _st_io_req_bits_derived_params_result_input_spad_stride_T_7)
connect st_io_req_bits_derived_params_result.input_spad_stride, _st_io_req_bits_derived_params_result_input_spad_stride_T_8
node _st_io_req_bits_derived_params_result_weight_spad_stride_T = mul(loops[loop_requesting_st_id].inner_bounds.krows, loops[loop_requesting_st_id].inner_bounds.kcols)
node _st_io_req_bits_derived_params_result_weight_spad_stride_T_1 = mul(_st_io_req_bits_derived_params_result_weight_spad_stride_T, loops[loop_requesting_st_id].inner_bounds.pochs)
node _st_io_req_bits_derived_params_result_weight_spad_stride_T_2 = mul(loops[loop_requesting_st_id].inner_bounds.krows, loops[loop_requesting_st_id].inner_bounds.kcols)
node _st_io_req_bits_derived_params_result_weight_spad_stride_T_3 = mul(_st_io_req_bits_derived_params_result_weight_spad_stride_T_2, loops[loop_requesting_st_id].inner_bounds.kchs)
node _st_io_req_bits_derived_params_result_weight_spad_stride_T_4 = mux(loops[loop_requesting_st_id].trans_weight_0132, _st_io_req_bits_derived_params_result_weight_spad_stride_T_1, _st_io_req_bits_derived_params_result_weight_spad_stride_T_3)
connect st_io_req_bits_derived_params_result.weight_spad_stride, _st_io_req_bits_derived_params_result_weight_spad_stride_T_4
connect st.io.req.bits.derived_params.weight_spad_stride, st_io_req_bits_derived_params_result.weight_spad_stride
connect st.io.req.bits.derived_params.input_spad_stride, st_io_req_bits_derived_params_result.input_spad_stride
connect st.io.req.bits.derived_params.bias_spad_stride, st_io_req_bits_derived_params_result.bias_spad_stride
connect st.io.req.bits.derived_params.in_channels_per_bank, st_io_req_bits_derived_params_result.in_channels_per_bank
connect st.io.req.bits.derived_params.out_channels_per_bank, st_io_req_bits_derived_params_result.out_channels_per_bank
connect st.io.req.bits.derived_params.ichs, st_io_req_bits_derived_params_result.ichs
connect st.io.req.bits.derived_params.icols_unpadded, st_io_req_bits_derived_params_result.icols_unpadded
connect st.io.req.bits.derived_params.irows_unpadded, st_io_req_bits_derived_params_result.irows_unpadded
connect st.io.req.bits.derived_params.icols, st_io_req_bits_derived_params_result.icols
connect st.io.req.bits.derived_params.irows, st_io_req_bits_derived_params_result.irows
connect st.io.req.bits.derived_params.ochs, st_io_req_bits_derived_params_result.ochs
connect st.io.req.bits.addr_start, st_addr_start
connect st.io.req.bits.dram_addr, loops[loop_requesting_st_id].output_dram_addr
connect st.io.req.bits.no_pool, loops[loop_requesting_st_id].no_pool
connect st.io.req.bits.activation, loops[loop_requesting_st_id].activation
connect st.io.req.bits.trans_output_1203, loops[loop_requesting_st_id].trans_output_1203
connect st.io.req.bits.loop_id, loop_requesting_st_id
node _st_io_req_valid_T = eq(loops[loop_requesting_st_id].st_started, UInt<1>(0h0))
node _st_io_req_valid_T_1 = and(_st_io_req_valid_T, loops[loop_requesting_st_id].ex_started)
node _st_io_req_valid_T_2 = and(_st_io_req_valid_T_1, loops[loop_requesting_st_id].configured)
connect st.io.req.valid, _st_io_req_valid_T_2
node _T_28 = and(st.io.req.ready, st.io.req.valid)
when _T_28 :
connect loops[loop_requesting_st_id].running, UInt<1>(0h1)
connect loops[loop_requesting_st_id].st_started, UInt<1>(0h1)
node _T_29 = neq(loops[loop_requesting_st_id].output_dram_addr, UInt<1>(0h0))
when _T_29 :
node _st_addr_start_max_T = sub(UInt<13>(0h1000), UInt<1>(0h1))
node st_addr_start_max = tail(_st_addr_start_max_T, 1)
node _st_addr_start_T = add(st_addr_start, UInt<12>(0h800))
node _st_addr_start_T_1 = tail(_st_addr_start_T, 1)
node _st_addr_start_T_2 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _st_addr_start_T_3 = add(st_addr_start, UInt<12>(0h800))
node _st_addr_start_T_4 = gt(_st_addr_start_T_3, st_addr_start_max)
node _st_addr_start_T_5 = mux(_st_addr_start_T_4, UInt<1>(0h0), _st_addr_start_T_1)
node _st_addr_start_T_6 = mux(_st_addr_start_T_2, st_addr_start, _st_addr_start_T_5)
connect st_addr_start, _st_addr_start_T_6
node _T_30 = and(ld_bias.io.idle, loops[ld_bias.io.loop_id].running)
node _T_31 = and(_T_30, loops[ld_bias.io.loop_id].ld_bias_started)
when _T_31 :
connect loops[ld_bias.io.loop_id].ld_bias_completed, UInt<1>(0h1)
node _T_32 = and(ld_input.io.idle, loops[ld_input.io.loop_id].running)
node _T_33 = and(_T_32, loops[ld_input.io.loop_id].ld_input_started)
when _T_33 :
connect loops[ld_input.io.loop_id].ld_input_completed, UInt<1>(0h1)
node _T_34 = and(ld_weights.io.idle, loops[ld_weights.io.loop_id].running)
node _T_35 = and(_T_34, loops[ld_weights.io.loop_id].ld_weights_started)
when _T_35 :
connect loops[ld_weights.io.loop_id].ld_weights_completed, UInt<1>(0h1)
node _T_36 = and(ex.io.idle, loops[ex.io.loop_id].running)
node _T_37 = and(_T_36, loops[ex.io.loop_id].ex_started)
when _T_37 :
connect loops[ex.io.loop_id].ex_completed, UInt<1>(0h1)
node _T_38 = and(st.io.idle, loops[st.io.loop_id].running)
node _T_39 = and(_T_38, loops[st.io.loop_id].st_started)
when _T_39 :
connect loops[st.io.loop_id].st_completed, UInt<1>(0h1)
node _T_40 = and(loops[head_loop_id].ld_bias_completed, loops[head_loop_id].ld_input_completed)
node _T_41 = and(_T_40, loops[head_loop_id].ld_weights_completed)
node _T_42 = and(_T_41, loops[head_loop_id].ex_completed)
node _T_43 = and(_T_42, loops[head_loop_id].st_completed)
node _T_44 = and(loops[head_loop_id].running, _T_43)
when _T_44 :
connect loops[head_loop_id].configured, UInt<1>(0h0)
connect loops[head_loop_id].running, UInt<1>(0h0)
connect loops[head_loop_id].ld_bias_started, UInt<1>(0h0)
connect loops[head_loop_id].ld_input_started, UInt<1>(0h0)
connect loops[head_loop_id].ld_weights_started, UInt<1>(0h0)
connect loops[head_loop_id].ex_started, UInt<1>(0h0)
connect loops[head_loop_id].st_started, UInt<1>(0h0)
connect loops[head_loop_id].ld_bias_completed, UInt<1>(0h0)
connect loops[head_loop_id].ld_input_completed, UInt<1>(0h0)
connect loops[head_loop_id].ld_weights_completed, UInt<1>(0h0)
connect loops[head_loop_id].ex_completed, UInt<1>(0h0)
connect loops[head_loop_id].st_completed, UInt<1>(0h0)
node _head_loop_id_T = not(head_loop_id)
connect head_loop_id, _head_loop_id_T
node _T_45 = asUInt(reset)
when _T_45 :
connect loops[0].configured, UInt<1>(0h0)
connect loops[0].running, UInt<1>(0h0)
connect loops[0].ld_bias_started, UInt<1>(0h0)
connect loops[0].ld_input_started, UInt<1>(0h0)
connect loops[0].ld_weights_started, UInt<1>(0h0)
connect loops[0].ex_started, UInt<1>(0h0)
connect loops[0].st_started, UInt<1>(0h0)
connect loops[0].ld_bias_completed, UInt<1>(0h0)
connect loops[0].ld_input_completed, UInt<1>(0h0)
connect loops[0].ld_weights_completed, UInt<1>(0h0)
connect loops[0].ex_completed, UInt<1>(0h0)
connect loops[0].st_completed, UInt<1>(0h0)
connect loops[0].a_addr_start, UInt<1>(0h0)
connect loops[0].b_addr_end, UInt<14>(0h2000)
connect loops[1].configured, UInt<1>(0h0)
connect loops[1].running, UInt<1>(0h0)
connect loops[1].ld_bias_started, UInt<1>(0h0)
connect loops[1].ld_input_started, UInt<1>(0h0)
connect loops[1].ld_weights_started, UInt<1>(0h0)
connect loops[1].ex_started, UInt<1>(0h0)
connect loops[1].st_started, UInt<1>(0h0)
connect loops[1].ld_bias_completed, UInt<1>(0h0)
connect loops[1].ld_input_completed, UInt<1>(0h0)
connect loops[1].ld_weights_completed, UInt<1>(0h0)
connect loops[1].ex_completed, UInt<1>(0h0)
connect loops[1].st_completed, UInt<1>(0h0)
connect loops[1].a_addr_start, UInt<14>(0h2000)
connect loops[1].b_addr_end, UInt<15>(0h4000) | module LoopConv( // @[LoopConv.scala:1169:7]
input clock, // @[LoopConv.scala:1169:7]
input reset, // @[LoopConv.scala:1169:7]
output io_in_ready, // @[LoopConv.scala:1184:14]
input io_in_valid, // @[LoopConv.scala:1184:14]
input [6:0] io_in_bits_cmd_inst_funct, // @[LoopConv.scala:1184:14]
input [4:0] io_in_bits_cmd_inst_rs2, // @[LoopConv.scala:1184:14]
input [4:0] io_in_bits_cmd_inst_rs1, // @[LoopConv.scala:1184:14]
input io_in_bits_cmd_inst_xd, // @[LoopConv.scala:1184:14]
input io_in_bits_cmd_inst_xs1, // @[LoopConv.scala:1184:14]
input io_in_bits_cmd_inst_xs2, // @[LoopConv.scala:1184:14]
input [4:0] io_in_bits_cmd_inst_rd, // @[LoopConv.scala:1184:14]
input [6:0] io_in_bits_cmd_inst_opcode, // @[LoopConv.scala:1184:14]
input [63:0] io_in_bits_cmd_rs1, // @[LoopConv.scala:1184:14]
input [63:0] io_in_bits_cmd_rs2, // @[LoopConv.scala:1184:14]
input io_in_bits_cmd_status_debug, // @[LoopConv.scala:1184:14]
input io_in_bits_cmd_status_cease, // @[LoopConv.scala:1184:14]
input io_in_bits_cmd_status_wfi, // @[LoopConv.scala:1184:14]
input [31:0] io_in_bits_cmd_status_isa, // @[LoopConv.scala:1184:14]
input [1:0] io_in_bits_cmd_status_dprv, // @[LoopConv.scala:1184:14]
input io_in_bits_cmd_status_dv, // @[LoopConv.scala:1184:14]
input [1:0] io_in_bits_cmd_status_prv, // @[LoopConv.scala:1184:14]
input io_in_bits_cmd_status_v, // @[LoopConv.scala:1184:14]
input io_in_bits_cmd_status_sd, // @[LoopConv.scala:1184:14]
input [22:0] io_in_bits_cmd_status_zero2, // @[LoopConv.scala:1184:14]
input io_in_bits_cmd_status_mpv, // @[LoopConv.scala:1184:14]
input io_in_bits_cmd_status_gva, // @[LoopConv.scala:1184:14]
input io_in_bits_cmd_status_mbe, // @[LoopConv.scala:1184:14]
input io_in_bits_cmd_status_sbe, // @[LoopConv.scala:1184:14]
input [1:0] io_in_bits_cmd_status_sxl, // @[LoopConv.scala:1184:14]
input [1:0] io_in_bits_cmd_status_uxl, // @[LoopConv.scala:1184:14]
input io_in_bits_cmd_status_sd_rv32, // @[LoopConv.scala:1184:14]
input [7:0] io_in_bits_cmd_status_zero1, // @[LoopConv.scala:1184:14]
input io_in_bits_cmd_status_tsr, // @[LoopConv.scala:1184:14]
input io_in_bits_cmd_status_tw, // @[LoopConv.scala:1184:14]
input io_in_bits_cmd_status_tvm, // @[LoopConv.scala:1184:14]
input io_in_bits_cmd_status_mxr, // @[LoopConv.scala:1184:14]
input io_in_bits_cmd_status_sum, // @[LoopConv.scala:1184:14]
input io_in_bits_cmd_status_mprv, // @[LoopConv.scala:1184:14]
input [1:0] io_in_bits_cmd_status_xs, // @[LoopConv.scala:1184:14]
input [1:0] io_in_bits_cmd_status_fs, // @[LoopConv.scala:1184:14]
input [1:0] io_in_bits_cmd_status_mpp, // @[LoopConv.scala:1184:14]
input [1:0] io_in_bits_cmd_status_vs, // @[LoopConv.scala:1184:14]
input io_in_bits_cmd_status_spp, // @[LoopConv.scala:1184:14]
input io_in_bits_cmd_status_mpie, // @[LoopConv.scala:1184:14]
input io_in_bits_cmd_status_ube, // @[LoopConv.scala:1184:14]
input io_in_bits_cmd_status_spie, // @[LoopConv.scala:1184:14]
input io_in_bits_cmd_status_upie, // @[LoopConv.scala:1184:14]
input io_in_bits_cmd_status_mie, // @[LoopConv.scala:1184:14]
input io_in_bits_cmd_status_hie, // @[LoopConv.scala:1184:14]
input io_in_bits_cmd_status_sie, // @[LoopConv.scala:1184:14]
input io_in_bits_cmd_status_uie, // @[LoopConv.scala:1184:14]
input io_in_bits_rob_id_valid, // @[LoopConv.scala:1184:14]
input [5:0] io_in_bits_rob_id_bits, // @[LoopConv.scala:1184:14]
input io_in_bits_from_matmul_fsm, // @[LoopConv.scala:1184:14]
input io_in_bits_from_conv_fsm, // @[LoopConv.scala:1184:14]
input io_out_ready, // @[LoopConv.scala:1184:14]
output io_out_valid, // @[LoopConv.scala:1184:14]
output [6:0] io_out_bits_cmd_inst_funct, // @[LoopConv.scala:1184:14]
output [4:0] io_out_bits_cmd_inst_rs2, // @[LoopConv.scala:1184:14]
output [4:0] io_out_bits_cmd_inst_rs1, // @[LoopConv.scala:1184:14]
output io_out_bits_cmd_inst_xd, // @[LoopConv.scala:1184:14]
output io_out_bits_cmd_inst_xs1, // @[LoopConv.scala:1184:14]
output io_out_bits_cmd_inst_xs2, // @[LoopConv.scala:1184:14]
output [4:0] io_out_bits_cmd_inst_rd, // @[LoopConv.scala:1184:14]
output [6:0] io_out_bits_cmd_inst_opcode, // @[LoopConv.scala:1184:14]
output [63:0] io_out_bits_cmd_rs1, // @[LoopConv.scala:1184:14]
output [63:0] io_out_bits_cmd_rs2, // @[LoopConv.scala:1184:14]
output io_out_bits_cmd_status_debug, // @[LoopConv.scala:1184:14]
output io_out_bits_cmd_status_cease, // @[LoopConv.scala:1184:14]
output io_out_bits_cmd_status_wfi, // @[LoopConv.scala:1184:14]
output [31:0] io_out_bits_cmd_status_isa, // @[LoopConv.scala:1184:14]
output [1:0] io_out_bits_cmd_status_dprv, // @[LoopConv.scala:1184:14]
output io_out_bits_cmd_status_dv, // @[LoopConv.scala:1184:14]
output [1:0] io_out_bits_cmd_status_prv, // @[LoopConv.scala:1184:14]
output io_out_bits_cmd_status_v, // @[LoopConv.scala:1184:14]
output io_out_bits_cmd_status_sd, // @[LoopConv.scala:1184:14]
output [22:0] io_out_bits_cmd_status_zero2, // @[LoopConv.scala:1184:14]
output io_out_bits_cmd_status_mpv, // @[LoopConv.scala:1184:14]
output io_out_bits_cmd_status_gva, // @[LoopConv.scala:1184:14]
output io_out_bits_cmd_status_mbe, // @[LoopConv.scala:1184:14]
output io_out_bits_cmd_status_sbe, // @[LoopConv.scala:1184:14]
output [1:0] io_out_bits_cmd_status_sxl, // @[LoopConv.scala:1184:14]
output [1:0] io_out_bits_cmd_status_uxl, // @[LoopConv.scala:1184:14]
output io_out_bits_cmd_status_sd_rv32, // @[LoopConv.scala:1184:14]
output [7:0] io_out_bits_cmd_status_zero1, // @[LoopConv.scala:1184:14]
output io_out_bits_cmd_status_tsr, // @[LoopConv.scala:1184:14]
output io_out_bits_cmd_status_tw, // @[LoopConv.scala:1184:14]
output io_out_bits_cmd_status_tvm, // @[LoopConv.scala:1184:14]
output io_out_bits_cmd_status_mxr, // @[LoopConv.scala:1184:14]
output io_out_bits_cmd_status_sum, // @[LoopConv.scala:1184:14]
output io_out_bits_cmd_status_mprv, // @[LoopConv.scala:1184:14]
output [1:0] io_out_bits_cmd_status_xs, // @[LoopConv.scala:1184:14]
output [1:0] io_out_bits_cmd_status_fs, // @[LoopConv.scala:1184:14]
output [1:0] io_out_bits_cmd_status_mpp, // @[LoopConv.scala:1184:14]
output [1:0] io_out_bits_cmd_status_vs, // @[LoopConv.scala:1184:14]
output io_out_bits_cmd_status_spp, // @[LoopConv.scala:1184:14]
output io_out_bits_cmd_status_mpie, // @[LoopConv.scala:1184:14]
output io_out_bits_cmd_status_ube, // @[LoopConv.scala:1184:14]
output io_out_bits_cmd_status_spie, // @[LoopConv.scala:1184:14]
output io_out_bits_cmd_status_upie, // @[LoopConv.scala:1184:14]
output io_out_bits_cmd_status_mie, // @[LoopConv.scala:1184:14]
output io_out_bits_cmd_status_hie, // @[LoopConv.scala:1184:14]
output io_out_bits_cmd_status_sie, // @[LoopConv.scala:1184:14]
output io_out_bits_cmd_status_uie, // @[LoopConv.scala:1184:14]
output io_out_bits_from_matmul_fsm, // @[LoopConv.scala:1184:14]
output io_out_bits_from_conv_fsm, // @[LoopConv.scala:1184:14]
input [5:0] io_ld_completed, // @[LoopConv.scala:1184:14]
input [5:0] io_st_completed, // @[LoopConv.scala:1184:14]
input [5:0] io_ex_completed, // @[LoopConv.scala:1184:14]
output io_busy // @[LoopConv.scala:1184:14]
);
wire _arb_io_in_0_ready; // @[LoopConv.scala:1220:19]
wire _arb_io_in_1_ready; // @[LoopConv.scala:1220:19]
wire _arb_io_in_2_ready; // @[LoopConv.scala:1220:19]
wire _arb_io_in_3_ready; // @[LoopConv.scala:1220:19]
wire _arb_io_in_4_ready; // @[LoopConv.scala:1220:19]
wire _arb_io_out_valid; // @[LoopConv.scala:1220:19]
wire [6:0] _arb_io_out_bits_inst_funct; // @[LoopConv.scala:1220:19]
wire [4:0] _arb_io_out_bits_inst_rs2; // @[LoopConv.scala:1220:19]
wire [4:0] _arb_io_out_bits_inst_rs1; // @[LoopConv.scala:1220:19]
wire _arb_io_out_bits_inst_xd; // @[LoopConv.scala:1220:19]
wire _arb_io_out_bits_inst_xs1; // @[LoopConv.scala:1220:19]
wire _arb_io_out_bits_inst_xs2; // @[LoopConv.scala:1220:19]
wire [4:0] _arb_io_out_bits_inst_rd; // @[LoopConv.scala:1220:19]
wire [6:0] _arb_io_out_bits_inst_opcode; // @[LoopConv.scala:1220:19]
wire [63:0] _arb_io_out_bits_rs1; // @[LoopConv.scala:1220:19]
wire [63:0] _arb_io_out_bits_rs2; // @[LoopConv.scala:1220:19]
wire _arb_io_out_bits_status_debug; // @[LoopConv.scala:1220:19]
wire _arb_io_out_bits_status_cease; // @[LoopConv.scala:1220:19]
wire _arb_io_out_bits_status_wfi; // @[LoopConv.scala:1220:19]
wire [31:0] _arb_io_out_bits_status_isa; // @[LoopConv.scala:1220:19]
wire [1:0] _arb_io_out_bits_status_dprv; // @[LoopConv.scala:1220:19]
wire _arb_io_out_bits_status_dv; // @[LoopConv.scala:1220:19]
wire [1:0] _arb_io_out_bits_status_prv; // @[LoopConv.scala:1220:19]
wire _arb_io_out_bits_status_v; // @[LoopConv.scala:1220:19]
wire _arb_io_out_bits_status_sd; // @[LoopConv.scala:1220:19]
wire [22:0] _arb_io_out_bits_status_zero2; // @[LoopConv.scala:1220:19]
wire _arb_io_out_bits_status_mpv; // @[LoopConv.scala:1220:19]
wire _arb_io_out_bits_status_gva; // @[LoopConv.scala:1220:19]
wire _arb_io_out_bits_status_mbe; // @[LoopConv.scala:1220:19]
wire _arb_io_out_bits_status_sbe; // @[LoopConv.scala:1220:19]
wire [1:0] _arb_io_out_bits_status_sxl; // @[LoopConv.scala:1220:19]
wire [1:0] _arb_io_out_bits_status_uxl; // @[LoopConv.scala:1220:19]
wire _arb_io_out_bits_status_sd_rv32; // @[LoopConv.scala:1220:19]
wire [7:0] _arb_io_out_bits_status_zero1; // @[LoopConv.scala:1220:19]
wire _arb_io_out_bits_status_tsr; // @[LoopConv.scala:1220:19]
wire _arb_io_out_bits_status_tw; // @[LoopConv.scala:1220:19]
wire _arb_io_out_bits_status_tvm; // @[LoopConv.scala:1220:19]
wire _arb_io_out_bits_status_mxr; // @[LoopConv.scala:1220:19]
wire _arb_io_out_bits_status_sum; // @[LoopConv.scala:1220:19]
wire _arb_io_out_bits_status_mprv; // @[LoopConv.scala:1220:19]
wire [1:0] _arb_io_out_bits_status_xs; // @[LoopConv.scala:1220:19]
wire [1:0] _arb_io_out_bits_status_fs; // @[LoopConv.scala:1220:19]
wire [1:0] _arb_io_out_bits_status_mpp; // @[LoopConv.scala:1220:19]
wire [1:0] _arb_io_out_bits_status_vs; // @[LoopConv.scala:1220:19]
wire _arb_io_out_bits_status_spp; // @[LoopConv.scala:1220:19]
wire _arb_io_out_bits_status_mpie; // @[LoopConv.scala:1220:19]
wire _arb_io_out_bits_status_ube; // @[LoopConv.scala:1220:19]
wire _arb_io_out_bits_status_spie; // @[LoopConv.scala:1220:19]
wire _arb_io_out_bits_status_upie; // @[LoopConv.scala:1220:19]
wire _arb_io_out_bits_status_mie; // @[LoopConv.scala:1220:19]
wire _arb_io_out_bits_status_hie; // @[LoopConv.scala:1220:19]
wire _arb_io_out_bits_status_sie; // @[LoopConv.scala:1220:19]
wire _arb_io_out_bits_status_uie; // @[LoopConv.scala:1220:19]
wire _cmd_q_io_deq_valid; // @[Decoupled.scala:362:21]
wire [6:0] _cmd_q_io_deq_bits_cmd_inst_funct; // @[Decoupled.scala:362:21]
wire [4:0] _cmd_q_io_deq_bits_cmd_inst_rs2; // @[Decoupled.scala:362:21]
wire [4:0] _cmd_q_io_deq_bits_cmd_inst_rs1; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_inst_xd; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_inst_xs1; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_inst_xs2; // @[Decoupled.scala:362:21]
wire [4:0] _cmd_q_io_deq_bits_cmd_inst_rd; // @[Decoupled.scala:362:21]
wire [6:0] _cmd_q_io_deq_bits_cmd_inst_opcode; // @[Decoupled.scala:362:21]
wire [63:0] _cmd_q_io_deq_bits_cmd_rs1; // @[Decoupled.scala:362:21]
wire [63:0] _cmd_q_io_deq_bits_cmd_rs2; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_debug; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_cease; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_wfi; // @[Decoupled.scala:362:21]
wire [31:0] _cmd_q_io_deq_bits_cmd_status_isa; // @[Decoupled.scala:362:21]
wire [1:0] _cmd_q_io_deq_bits_cmd_status_dprv; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_dv; // @[Decoupled.scala:362:21]
wire [1:0] _cmd_q_io_deq_bits_cmd_status_prv; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_v; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_sd; // @[Decoupled.scala:362:21]
wire [22:0] _cmd_q_io_deq_bits_cmd_status_zero2; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_mpv; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_gva; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_mbe; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_sbe; // @[Decoupled.scala:362:21]
wire [1:0] _cmd_q_io_deq_bits_cmd_status_sxl; // @[Decoupled.scala:362:21]
wire [1:0] _cmd_q_io_deq_bits_cmd_status_uxl; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_sd_rv32; // @[Decoupled.scala:362:21]
wire [7:0] _cmd_q_io_deq_bits_cmd_status_zero1; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_tsr; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_tw; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_tvm; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_mxr; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_sum; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_mprv; // @[Decoupled.scala:362:21]
wire [1:0] _cmd_q_io_deq_bits_cmd_status_xs; // @[Decoupled.scala:362:21]
wire [1:0] _cmd_q_io_deq_bits_cmd_status_fs; // @[Decoupled.scala:362:21]
wire [1:0] _cmd_q_io_deq_bits_cmd_status_mpp; // @[Decoupled.scala:362:21]
wire [1:0] _cmd_q_io_deq_bits_cmd_status_vs; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_spp; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_mpie; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_ube; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_spie; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_upie; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_mie; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_hie; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_sie; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_uie; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_from_matmul_fsm; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_from_conv_fsm; // @[Decoupled.scala:362:21]
wire _st_io_req_ready; // @[LoopConv.scala:1212:18]
wire _st_io_cmd_valid; // @[LoopConv.scala:1212:18]
wire [6:0] _st_io_cmd_bits_inst_funct; // @[LoopConv.scala:1212:18]
wire [4:0] _st_io_cmd_bits_inst_rs2; // @[LoopConv.scala:1212:18]
wire [4:0] _st_io_cmd_bits_inst_rs1; // @[LoopConv.scala:1212:18]
wire _st_io_cmd_bits_inst_xd; // @[LoopConv.scala:1212:18]
wire _st_io_cmd_bits_inst_xs1; // @[LoopConv.scala:1212:18]
wire _st_io_cmd_bits_inst_xs2; // @[LoopConv.scala:1212:18]
wire [4:0] _st_io_cmd_bits_inst_rd; // @[LoopConv.scala:1212:18]
wire [6:0] _st_io_cmd_bits_inst_opcode; // @[LoopConv.scala:1212:18]
wire [63:0] _st_io_cmd_bits_rs1; // @[LoopConv.scala:1212:18]
wire [63:0] _st_io_cmd_bits_rs2; // @[LoopConv.scala:1212:18]
wire _st_io_cmd_bits_status_debug; // @[LoopConv.scala:1212:18]
wire _st_io_cmd_bits_status_cease; // @[LoopConv.scala:1212:18]
wire _st_io_cmd_bits_status_wfi; // @[LoopConv.scala:1212:18]
wire [31:0] _st_io_cmd_bits_status_isa; // @[LoopConv.scala:1212:18]
wire [1:0] _st_io_cmd_bits_status_dprv; // @[LoopConv.scala:1212:18]
wire _st_io_cmd_bits_status_dv; // @[LoopConv.scala:1212:18]
wire [1:0] _st_io_cmd_bits_status_prv; // @[LoopConv.scala:1212:18]
wire _st_io_cmd_bits_status_v; // @[LoopConv.scala:1212:18]
wire _st_io_cmd_bits_status_sd; // @[LoopConv.scala:1212:18]
wire [22:0] _st_io_cmd_bits_status_zero2; // @[LoopConv.scala:1212:18]
wire _st_io_cmd_bits_status_mpv; // @[LoopConv.scala:1212:18]
wire _st_io_cmd_bits_status_gva; // @[LoopConv.scala:1212:18]
wire _st_io_cmd_bits_status_mbe; // @[LoopConv.scala:1212:18]
wire _st_io_cmd_bits_status_sbe; // @[LoopConv.scala:1212:18]
wire [1:0] _st_io_cmd_bits_status_sxl; // @[LoopConv.scala:1212:18]
wire [1:0] _st_io_cmd_bits_status_uxl; // @[LoopConv.scala:1212:18]
wire _st_io_cmd_bits_status_sd_rv32; // @[LoopConv.scala:1212:18]
wire [7:0] _st_io_cmd_bits_status_zero1; // @[LoopConv.scala:1212:18]
wire _st_io_cmd_bits_status_tsr; // @[LoopConv.scala:1212:18]
wire _st_io_cmd_bits_status_tw; // @[LoopConv.scala:1212:18]
wire _st_io_cmd_bits_status_tvm; // @[LoopConv.scala:1212:18]
wire _st_io_cmd_bits_status_mxr; // @[LoopConv.scala:1212:18]
wire _st_io_cmd_bits_status_sum; // @[LoopConv.scala:1212:18]
wire _st_io_cmd_bits_status_mprv; // @[LoopConv.scala:1212:18]
wire [1:0] _st_io_cmd_bits_status_xs; // @[LoopConv.scala:1212:18]
wire [1:0] _st_io_cmd_bits_status_fs; // @[LoopConv.scala:1212:18]
wire [1:0] _st_io_cmd_bits_status_mpp; // @[LoopConv.scala:1212:18]
wire [1:0] _st_io_cmd_bits_status_vs; // @[LoopConv.scala:1212:18]
wire _st_io_cmd_bits_status_spp; // @[LoopConv.scala:1212:18]
wire _st_io_cmd_bits_status_mpie; // @[LoopConv.scala:1212:18]
wire _st_io_cmd_bits_status_ube; // @[LoopConv.scala:1212:18]
wire _st_io_cmd_bits_status_spie; // @[LoopConv.scala:1212:18]
wire _st_io_cmd_bits_status_upie; // @[LoopConv.scala:1212:18]
wire _st_io_cmd_bits_status_mie; // @[LoopConv.scala:1212:18]
wire _st_io_cmd_bits_status_hie; // @[LoopConv.scala:1212:18]
wire _st_io_cmd_bits_status_sie; // @[LoopConv.scala:1212:18]
wire _st_io_cmd_bits_status_uie; // @[LoopConv.scala:1212:18]
wire _st_io_idle; // @[LoopConv.scala:1212:18]
wire _st_io_loop_id; // @[LoopConv.scala:1212:18]
wire _ex_io_req_ready; // @[LoopConv.scala:1211:18]
wire _ex_io_cmd_valid; // @[LoopConv.scala:1211:18]
wire [6:0] _ex_io_cmd_bits_inst_funct; // @[LoopConv.scala:1211:18]
wire [4:0] _ex_io_cmd_bits_inst_rs2; // @[LoopConv.scala:1211:18]
wire [4:0] _ex_io_cmd_bits_inst_rs1; // @[LoopConv.scala:1211:18]
wire _ex_io_cmd_bits_inst_xd; // @[LoopConv.scala:1211:18]
wire _ex_io_cmd_bits_inst_xs1; // @[LoopConv.scala:1211:18]
wire _ex_io_cmd_bits_inst_xs2; // @[LoopConv.scala:1211:18]
wire [4:0] _ex_io_cmd_bits_inst_rd; // @[LoopConv.scala:1211:18]
wire [6:0] _ex_io_cmd_bits_inst_opcode; // @[LoopConv.scala:1211:18]
wire [63:0] _ex_io_cmd_bits_rs1; // @[LoopConv.scala:1211:18]
wire [63:0] _ex_io_cmd_bits_rs2; // @[LoopConv.scala:1211:18]
wire _ex_io_cmd_bits_status_debug; // @[LoopConv.scala:1211:18]
wire _ex_io_cmd_bits_status_cease; // @[LoopConv.scala:1211:18]
wire _ex_io_cmd_bits_status_wfi; // @[LoopConv.scala:1211:18]
wire [31:0] _ex_io_cmd_bits_status_isa; // @[LoopConv.scala:1211:18]
wire [1:0] _ex_io_cmd_bits_status_dprv; // @[LoopConv.scala:1211:18]
wire _ex_io_cmd_bits_status_dv; // @[LoopConv.scala:1211:18]
wire [1:0] _ex_io_cmd_bits_status_prv; // @[LoopConv.scala:1211:18]
wire _ex_io_cmd_bits_status_v; // @[LoopConv.scala:1211:18]
wire _ex_io_cmd_bits_status_sd; // @[LoopConv.scala:1211:18]
wire [22:0] _ex_io_cmd_bits_status_zero2; // @[LoopConv.scala:1211:18]
wire _ex_io_cmd_bits_status_mpv; // @[LoopConv.scala:1211:18]
wire _ex_io_cmd_bits_status_gva; // @[LoopConv.scala:1211:18]
wire _ex_io_cmd_bits_status_mbe; // @[LoopConv.scala:1211:18]
wire _ex_io_cmd_bits_status_sbe; // @[LoopConv.scala:1211:18]
wire [1:0] _ex_io_cmd_bits_status_sxl; // @[LoopConv.scala:1211:18]
wire [1:0] _ex_io_cmd_bits_status_uxl; // @[LoopConv.scala:1211:18]
wire _ex_io_cmd_bits_status_sd_rv32; // @[LoopConv.scala:1211:18]
wire [7:0] _ex_io_cmd_bits_status_zero1; // @[LoopConv.scala:1211:18]
wire _ex_io_cmd_bits_status_tsr; // @[LoopConv.scala:1211:18]
wire _ex_io_cmd_bits_status_tw; // @[LoopConv.scala:1211:18]
wire _ex_io_cmd_bits_status_tvm; // @[LoopConv.scala:1211:18]
wire _ex_io_cmd_bits_status_mxr; // @[LoopConv.scala:1211:18]
wire _ex_io_cmd_bits_status_sum; // @[LoopConv.scala:1211:18]
wire _ex_io_cmd_bits_status_mprv; // @[LoopConv.scala:1211:18]
wire [1:0] _ex_io_cmd_bits_status_xs; // @[LoopConv.scala:1211:18]
wire [1:0] _ex_io_cmd_bits_status_fs; // @[LoopConv.scala:1211:18]
wire [1:0] _ex_io_cmd_bits_status_mpp; // @[LoopConv.scala:1211:18]
wire [1:0] _ex_io_cmd_bits_status_vs; // @[LoopConv.scala:1211:18]
wire _ex_io_cmd_bits_status_spp; // @[LoopConv.scala:1211:18]
wire _ex_io_cmd_bits_status_mpie; // @[LoopConv.scala:1211:18]
wire _ex_io_cmd_bits_status_ube; // @[LoopConv.scala:1211:18]
wire _ex_io_cmd_bits_status_spie; // @[LoopConv.scala:1211:18]
wire _ex_io_cmd_bits_status_upie; // @[LoopConv.scala:1211:18]
wire _ex_io_cmd_bits_status_mie; // @[LoopConv.scala:1211:18]
wire _ex_io_cmd_bits_status_hie; // @[LoopConv.scala:1211:18]
wire _ex_io_cmd_bits_status_sie; // @[LoopConv.scala:1211:18]
wire _ex_io_cmd_bits_status_uie; // @[LoopConv.scala:1211:18]
wire _ex_io_idle; // @[LoopConv.scala:1211:18]
wire _ex_io_loop_id; // @[LoopConv.scala:1211:18]
wire _ld_weights_io_req_ready; // @[LoopConv.scala:1210:26]
wire _ld_weights_io_cmd_valid; // @[LoopConv.scala:1210:26]
wire [6:0] _ld_weights_io_cmd_bits_inst_funct; // @[LoopConv.scala:1210:26]
wire [4:0] _ld_weights_io_cmd_bits_inst_rs2; // @[LoopConv.scala:1210:26]
wire [4:0] _ld_weights_io_cmd_bits_inst_rs1; // @[LoopConv.scala:1210:26]
wire _ld_weights_io_cmd_bits_inst_xd; // @[LoopConv.scala:1210:26]
wire _ld_weights_io_cmd_bits_inst_xs1; // @[LoopConv.scala:1210:26]
wire _ld_weights_io_cmd_bits_inst_xs2; // @[LoopConv.scala:1210:26]
wire [4:0] _ld_weights_io_cmd_bits_inst_rd; // @[LoopConv.scala:1210:26]
wire [6:0] _ld_weights_io_cmd_bits_inst_opcode; // @[LoopConv.scala:1210:26]
wire [63:0] _ld_weights_io_cmd_bits_rs1; // @[LoopConv.scala:1210:26]
wire [63:0] _ld_weights_io_cmd_bits_rs2; // @[LoopConv.scala:1210:26]
wire _ld_weights_io_cmd_bits_status_debug; // @[LoopConv.scala:1210:26]
wire _ld_weights_io_cmd_bits_status_cease; // @[LoopConv.scala:1210:26]
wire _ld_weights_io_cmd_bits_status_wfi; // @[LoopConv.scala:1210:26]
wire [31:0] _ld_weights_io_cmd_bits_status_isa; // @[LoopConv.scala:1210:26]
wire [1:0] _ld_weights_io_cmd_bits_status_dprv; // @[LoopConv.scala:1210:26]
wire _ld_weights_io_cmd_bits_status_dv; // @[LoopConv.scala:1210:26]
wire [1:0] _ld_weights_io_cmd_bits_status_prv; // @[LoopConv.scala:1210:26]
wire _ld_weights_io_cmd_bits_status_v; // @[LoopConv.scala:1210:26]
wire _ld_weights_io_cmd_bits_status_sd; // @[LoopConv.scala:1210:26]
wire [22:0] _ld_weights_io_cmd_bits_status_zero2; // @[LoopConv.scala:1210:26]
wire _ld_weights_io_cmd_bits_status_mpv; // @[LoopConv.scala:1210:26]
wire _ld_weights_io_cmd_bits_status_gva; // @[LoopConv.scala:1210:26]
wire _ld_weights_io_cmd_bits_status_mbe; // @[LoopConv.scala:1210:26]
wire _ld_weights_io_cmd_bits_status_sbe; // @[LoopConv.scala:1210:26]
wire [1:0] _ld_weights_io_cmd_bits_status_sxl; // @[LoopConv.scala:1210:26]
wire [1:0] _ld_weights_io_cmd_bits_status_uxl; // @[LoopConv.scala:1210:26]
wire _ld_weights_io_cmd_bits_status_sd_rv32; // @[LoopConv.scala:1210:26]
wire [7:0] _ld_weights_io_cmd_bits_status_zero1; // @[LoopConv.scala:1210:26]
wire _ld_weights_io_cmd_bits_status_tsr; // @[LoopConv.scala:1210:26]
wire _ld_weights_io_cmd_bits_status_tw; // @[LoopConv.scala:1210:26]
wire _ld_weights_io_cmd_bits_status_tvm; // @[LoopConv.scala:1210:26]
wire _ld_weights_io_cmd_bits_status_mxr; // @[LoopConv.scala:1210:26]
wire _ld_weights_io_cmd_bits_status_sum; // @[LoopConv.scala:1210:26]
wire _ld_weights_io_cmd_bits_status_mprv; // @[LoopConv.scala:1210:26]
wire [1:0] _ld_weights_io_cmd_bits_status_xs; // @[LoopConv.scala:1210:26]
wire [1:0] _ld_weights_io_cmd_bits_status_fs; // @[LoopConv.scala:1210:26]
wire [1:0] _ld_weights_io_cmd_bits_status_mpp; // @[LoopConv.scala:1210:26]
wire [1:0] _ld_weights_io_cmd_bits_status_vs; // @[LoopConv.scala:1210:26]
wire _ld_weights_io_cmd_bits_status_spp; // @[LoopConv.scala:1210:26]
wire _ld_weights_io_cmd_bits_status_mpie; // @[LoopConv.scala:1210:26]
wire _ld_weights_io_cmd_bits_status_ube; // @[LoopConv.scala:1210:26]
wire _ld_weights_io_cmd_bits_status_spie; // @[LoopConv.scala:1210:26]
wire _ld_weights_io_cmd_bits_status_upie; // @[LoopConv.scala:1210:26]
wire _ld_weights_io_cmd_bits_status_mie; // @[LoopConv.scala:1210:26]
wire _ld_weights_io_cmd_bits_status_hie; // @[LoopConv.scala:1210:26]
wire _ld_weights_io_cmd_bits_status_sie; // @[LoopConv.scala:1210:26]
wire _ld_weights_io_cmd_bits_status_uie; // @[LoopConv.scala:1210:26]
wire _ld_weights_io_idle; // @[LoopConv.scala:1210:26]
wire _ld_weights_io_loop_id; // @[LoopConv.scala:1210:26]
wire _ld_input_io_req_ready; // @[LoopConv.scala:1209:24]
wire _ld_input_io_cmd_valid; // @[LoopConv.scala:1209:24]
wire [6:0] _ld_input_io_cmd_bits_inst_funct; // @[LoopConv.scala:1209:24]
wire [4:0] _ld_input_io_cmd_bits_inst_rs2; // @[LoopConv.scala:1209:24]
wire [4:0] _ld_input_io_cmd_bits_inst_rs1; // @[LoopConv.scala:1209:24]
wire _ld_input_io_cmd_bits_inst_xd; // @[LoopConv.scala:1209:24]
wire _ld_input_io_cmd_bits_inst_xs1; // @[LoopConv.scala:1209:24]
wire _ld_input_io_cmd_bits_inst_xs2; // @[LoopConv.scala:1209:24]
wire [4:0] _ld_input_io_cmd_bits_inst_rd; // @[LoopConv.scala:1209:24]
wire [6:0] _ld_input_io_cmd_bits_inst_opcode; // @[LoopConv.scala:1209:24]
wire [63:0] _ld_input_io_cmd_bits_rs1; // @[LoopConv.scala:1209:24]
wire [63:0] _ld_input_io_cmd_bits_rs2; // @[LoopConv.scala:1209:24]
wire _ld_input_io_cmd_bits_status_debug; // @[LoopConv.scala:1209:24]
wire _ld_input_io_cmd_bits_status_cease; // @[LoopConv.scala:1209:24]
wire _ld_input_io_cmd_bits_status_wfi; // @[LoopConv.scala:1209:24]
wire [31:0] _ld_input_io_cmd_bits_status_isa; // @[LoopConv.scala:1209:24]
wire [1:0] _ld_input_io_cmd_bits_status_dprv; // @[LoopConv.scala:1209:24]
wire _ld_input_io_cmd_bits_status_dv; // @[LoopConv.scala:1209:24]
wire [1:0] _ld_input_io_cmd_bits_status_prv; // @[LoopConv.scala:1209:24]
wire _ld_input_io_cmd_bits_status_v; // @[LoopConv.scala:1209:24]
wire _ld_input_io_cmd_bits_status_sd; // @[LoopConv.scala:1209:24]
wire [22:0] _ld_input_io_cmd_bits_status_zero2; // @[LoopConv.scala:1209:24]
wire _ld_input_io_cmd_bits_status_mpv; // @[LoopConv.scala:1209:24]
wire _ld_input_io_cmd_bits_status_gva; // @[LoopConv.scala:1209:24]
wire _ld_input_io_cmd_bits_status_mbe; // @[LoopConv.scala:1209:24]
wire _ld_input_io_cmd_bits_status_sbe; // @[LoopConv.scala:1209:24]
wire [1:0] _ld_input_io_cmd_bits_status_sxl; // @[LoopConv.scala:1209:24]
wire [1:0] _ld_input_io_cmd_bits_status_uxl; // @[LoopConv.scala:1209:24]
wire _ld_input_io_cmd_bits_status_sd_rv32; // @[LoopConv.scala:1209:24]
wire [7:0] _ld_input_io_cmd_bits_status_zero1; // @[LoopConv.scala:1209:24]
wire _ld_input_io_cmd_bits_status_tsr; // @[LoopConv.scala:1209:24]
wire _ld_input_io_cmd_bits_status_tw; // @[LoopConv.scala:1209:24]
wire _ld_input_io_cmd_bits_status_tvm; // @[LoopConv.scala:1209:24]
wire _ld_input_io_cmd_bits_status_mxr; // @[LoopConv.scala:1209:24]
wire _ld_input_io_cmd_bits_status_sum; // @[LoopConv.scala:1209:24]
wire _ld_input_io_cmd_bits_status_mprv; // @[LoopConv.scala:1209:24]
wire [1:0] _ld_input_io_cmd_bits_status_xs; // @[LoopConv.scala:1209:24]
wire [1:0] _ld_input_io_cmd_bits_status_fs; // @[LoopConv.scala:1209:24]
wire [1:0] _ld_input_io_cmd_bits_status_mpp; // @[LoopConv.scala:1209:24]
wire [1:0] _ld_input_io_cmd_bits_status_vs; // @[LoopConv.scala:1209:24]
wire _ld_input_io_cmd_bits_status_spp; // @[LoopConv.scala:1209:24]
wire _ld_input_io_cmd_bits_status_mpie; // @[LoopConv.scala:1209:24]
wire _ld_input_io_cmd_bits_status_ube; // @[LoopConv.scala:1209:24]
wire _ld_input_io_cmd_bits_status_spie; // @[LoopConv.scala:1209:24]
wire _ld_input_io_cmd_bits_status_upie; // @[LoopConv.scala:1209:24]
wire _ld_input_io_cmd_bits_status_mie; // @[LoopConv.scala:1209:24]
wire _ld_input_io_cmd_bits_status_hie; // @[LoopConv.scala:1209:24]
wire _ld_input_io_cmd_bits_status_sie; // @[LoopConv.scala:1209:24]
wire _ld_input_io_cmd_bits_status_uie; // @[LoopConv.scala:1209:24]
wire _ld_input_io_idle; // @[LoopConv.scala:1209:24]
wire _ld_input_io_loop_id; // @[LoopConv.scala:1209:24]
wire _ld_bias_io_req_ready; // @[LoopConv.scala:1208:23]
wire _ld_bias_io_cmd_valid; // @[LoopConv.scala:1208:23]
wire [6:0] _ld_bias_io_cmd_bits_inst_funct; // @[LoopConv.scala:1208:23]
wire [4:0] _ld_bias_io_cmd_bits_inst_rs2; // @[LoopConv.scala:1208:23]
wire [4:0] _ld_bias_io_cmd_bits_inst_rs1; // @[LoopConv.scala:1208:23]
wire _ld_bias_io_cmd_bits_inst_xd; // @[LoopConv.scala:1208:23]
wire _ld_bias_io_cmd_bits_inst_xs1; // @[LoopConv.scala:1208:23]
wire _ld_bias_io_cmd_bits_inst_xs2; // @[LoopConv.scala:1208:23]
wire [4:0] _ld_bias_io_cmd_bits_inst_rd; // @[LoopConv.scala:1208:23]
wire [6:0] _ld_bias_io_cmd_bits_inst_opcode; // @[LoopConv.scala:1208:23]
wire [63:0] _ld_bias_io_cmd_bits_rs1; // @[LoopConv.scala:1208:23]
wire [63:0] _ld_bias_io_cmd_bits_rs2; // @[LoopConv.scala:1208:23]
wire _ld_bias_io_cmd_bits_status_debug; // @[LoopConv.scala:1208:23]
wire _ld_bias_io_cmd_bits_status_cease; // @[LoopConv.scala:1208:23]
wire _ld_bias_io_cmd_bits_status_wfi; // @[LoopConv.scala:1208:23]
wire [31:0] _ld_bias_io_cmd_bits_status_isa; // @[LoopConv.scala:1208:23]
wire [1:0] _ld_bias_io_cmd_bits_status_dprv; // @[LoopConv.scala:1208:23]
wire _ld_bias_io_cmd_bits_status_dv; // @[LoopConv.scala:1208:23]
wire [1:0] _ld_bias_io_cmd_bits_status_prv; // @[LoopConv.scala:1208:23]
wire _ld_bias_io_cmd_bits_status_v; // @[LoopConv.scala:1208:23]
wire _ld_bias_io_cmd_bits_status_sd; // @[LoopConv.scala:1208:23]
wire [22:0] _ld_bias_io_cmd_bits_status_zero2; // @[LoopConv.scala:1208:23]
wire _ld_bias_io_cmd_bits_status_mpv; // @[LoopConv.scala:1208:23]
wire _ld_bias_io_cmd_bits_status_gva; // @[LoopConv.scala:1208:23]
wire _ld_bias_io_cmd_bits_status_mbe; // @[LoopConv.scala:1208:23]
wire _ld_bias_io_cmd_bits_status_sbe; // @[LoopConv.scala:1208:23]
wire [1:0] _ld_bias_io_cmd_bits_status_sxl; // @[LoopConv.scala:1208:23]
wire [1:0] _ld_bias_io_cmd_bits_status_uxl; // @[LoopConv.scala:1208:23]
wire _ld_bias_io_cmd_bits_status_sd_rv32; // @[LoopConv.scala:1208:23]
wire [7:0] _ld_bias_io_cmd_bits_status_zero1; // @[LoopConv.scala:1208:23]
wire _ld_bias_io_cmd_bits_status_tsr; // @[LoopConv.scala:1208:23]
wire _ld_bias_io_cmd_bits_status_tw; // @[LoopConv.scala:1208:23]
wire _ld_bias_io_cmd_bits_status_tvm; // @[LoopConv.scala:1208:23]
wire _ld_bias_io_cmd_bits_status_mxr; // @[LoopConv.scala:1208:23]
wire _ld_bias_io_cmd_bits_status_sum; // @[LoopConv.scala:1208:23]
wire _ld_bias_io_cmd_bits_status_mprv; // @[LoopConv.scala:1208:23]
wire [1:0] _ld_bias_io_cmd_bits_status_xs; // @[LoopConv.scala:1208:23]
wire [1:0] _ld_bias_io_cmd_bits_status_fs; // @[LoopConv.scala:1208:23]
wire [1:0] _ld_bias_io_cmd_bits_status_mpp; // @[LoopConv.scala:1208:23]
wire [1:0] _ld_bias_io_cmd_bits_status_vs; // @[LoopConv.scala:1208:23]
wire _ld_bias_io_cmd_bits_status_spp; // @[LoopConv.scala:1208:23]
wire _ld_bias_io_cmd_bits_status_mpie; // @[LoopConv.scala:1208:23]
wire _ld_bias_io_cmd_bits_status_ube; // @[LoopConv.scala:1208:23]
wire _ld_bias_io_cmd_bits_status_spie; // @[LoopConv.scala:1208:23]
wire _ld_bias_io_cmd_bits_status_upie; // @[LoopConv.scala:1208:23]
wire _ld_bias_io_cmd_bits_status_mie; // @[LoopConv.scala:1208:23]
wire _ld_bias_io_cmd_bits_status_hie; // @[LoopConv.scala:1208:23]
wire _ld_bias_io_cmd_bits_status_sie; // @[LoopConv.scala:1208:23]
wire _ld_bias_io_cmd_bits_status_uie; // @[LoopConv.scala:1208:23]
wire _ld_bias_io_idle; // @[LoopConv.scala:1208:23]
wire _ld_bias_io_loop_id; // @[LoopConv.scala:1208:23]
wire io_in_valid_0 = io_in_valid; // @[LoopConv.scala:1169:7]
wire [6:0] io_in_bits_cmd_inst_funct_0 = io_in_bits_cmd_inst_funct; // @[LoopConv.scala:1169:7]
wire [4:0] io_in_bits_cmd_inst_rs2_0 = io_in_bits_cmd_inst_rs2; // @[LoopConv.scala:1169:7]
wire [4:0] io_in_bits_cmd_inst_rs1_0 = io_in_bits_cmd_inst_rs1; // @[LoopConv.scala:1169:7]
wire io_in_bits_cmd_inst_xd_0 = io_in_bits_cmd_inst_xd; // @[LoopConv.scala:1169:7]
wire io_in_bits_cmd_inst_xs1_0 = io_in_bits_cmd_inst_xs1; // @[LoopConv.scala:1169:7]
wire io_in_bits_cmd_inst_xs2_0 = io_in_bits_cmd_inst_xs2; // @[LoopConv.scala:1169:7]
wire [4:0] io_in_bits_cmd_inst_rd_0 = io_in_bits_cmd_inst_rd; // @[LoopConv.scala:1169:7]
wire [6:0] io_in_bits_cmd_inst_opcode_0 = io_in_bits_cmd_inst_opcode; // @[LoopConv.scala:1169:7]
wire [63:0] io_in_bits_cmd_rs1_0 = io_in_bits_cmd_rs1; // @[LoopConv.scala:1169:7]
wire [63:0] io_in_bits_cmd_rs2_0 = io_in_bits_cmd_rs2; // @[LoopConv.scala:1169:7]
wire io_in_bits_cmd_status_debug_0 = io_in_bits_cmd_status_debug; // @[LoopConv.scala:1169:7]
wire io_in_bits_cmd_status_cease_0 = io_in_bits_cmd_status_cease; // @[LoopConv.scala:1169:7]
wire io_in_bits_cmd_status_wfi_0 = io_in_bits_cmd_status_wfi; // @[LoopConv.scala:1169:7]
wire [31:0] io_in_bits_cmd_status_isa_0 = io_in_bits_cmd_status_isa; // @[LoopConv.scala:1169:7]
wire [1:0] io_in_bits_cmd_status_dprv_0 = io_in_bits_cmd_status_dprv; // @[LoopConv.scala:1169:7]
wire io_in_bits_cmd_status_dv_0 = io_in_bits_cmd_status_dv; // @[LoopConv.scala:1169:7]
wire [1:0] io_in_bits_cmd_status_prv_0 = io_in_bits_cmd_status_prv; // @[LoopConv.scala:1169:7]
wire io_in_bits_cmd_status_v_0 = io_in_bits_cmd_status_v; // @[LoopConv.scala:1169:7]
wire io_in_bits_cmd_status_sd_0 = io_in_bits_cmd_status_sd; // @[LoopConv.scala:1169:7]
wire [22:0] io_in_bits_cmd_status_zero2_0 = io_in_bits_cmd_status_zero2; // @[LoopConv.scala:1169:7]
wire io_in_bits_cmd_status_mpv_0 = io_in_bits_cmd_status_mpv; // @[LoopConv.scala:1169:7]
wire io_in_bits_cmd_status_gva_0 = io_in_bits_cmd_status_gva; // @[LoopConv.scala:1169:7]
wire io_in_bits_cmd_status_mbe_0 = io_in_bits_cmd_status_mbe; // @[LoopConv.scala:1169:7]
wire io_in_bits_cmd_status_sbe_0 = io_in_bits_cmd_status_sbe; // @[LoopConv.scala:1169:7]
wire [1:0] io_in_bits_cmd_status_sxl_0 = io_in_bits_cmd_status_sxl; // @[LoopConv.scala:1169:7]
wire [1:0] io_in_bits_cmd_status_uxl_0 = io_in_bits_cmd_status_uxl; // @[LoopConv.scala:1169:7]
wire io_in_bits_cmd_status_sd_rv32_0 = io_in_bits_cmd_status_sd_rv32; // @[LoopConv.scala:1169:7]
wire [7:0] io_in_bits_cmd_status_zero1_0 = io_in_bits_cmd_status_zero1; // @[LoopConv.scala:1169:7]
wire io_in_bits_cmd_status_tsr_0 = io_in_bits_cmd_status_tsr; // @[LoopConv.scala:1169:7]
wire io_in_bits_cmd_status_tw_0 = io_in_bits_cmd_status_tw; // @[LoopConv.scala:1169:7]
wire io_in_bits_cmd_status_tvm_0 = io_in_bits_cmd_status_tvm; // @[LoopConv.scala:1169:7]
wire io_in_bits_cmd_status_mxr_0 = io_in_bits_cmd_status_mxr; // @[LoopConv.scala:1169:7]
wire io_in_bits_cmd_status_sum_0 = io_in_bits_cmd_status_sum; // @[LoopConv.scala:1169:7]
wire io_in_bits_cmd_status_mprv_0 = io_in_bits_cmd_status_mprv; // @[LoopConv.scala:1169:7]
wire [1:0] io_in_bits_cmd_status_xs_0 = io_in_bits_cmd_status_xs; // @[LoopConv.scala:1169:7]
wire [1:0] io_in_bits_cmd_status_fs_0 = io_in_bits_cmd_status_fs; // @[LoopConv.scala:1169:7]
wire [1:0] io_in_bits_cmd_status_mpp_0 = io_in_bits_cmd_status_mpp; // @[LoopConv.scala:1169:7]
wire [1:0] io_in_bits_cmd_status_vs_0 = io_in_bits_cmd_status_vs; // @[LoopConv.scala:1169:7]
wire io_in_bits_cmd_status_spp_0 = io_in_bits_cmd_status_spp; // @[LoopConv.scala:1169:7]
wire io_in_bits_cmd_status_mpie_0 = io_in_bits_cmd_status_mpie; // @[LoopConv.scala:1169:7]
wire io_in_bits_cmd_status_ube_0 = io_in_bits_cmd_status_ube; // @[LoopConv.scala:1169:7]
wire io_in_bits_cmd_status_spie_0 = io_in_bits_cmd_status_spie; // @[LoopConv.scala:1169:7]
wire io_in_bits_cmd_status_upie_0 = io_in_bits_cmd_status_upie; // @[LoopConv.scala:1169:7]
wire io_in_bits_cmd_status_mie_0 = io_in_bits_cmd_status_mie; // @[LoopConv.scala:1169:7]
wire io_in_bits_cmd_status_hie_0 = io_in_bits_cmd_status_hie; // @[LoopConv.scala:1169:7]
wire io_in_bits_cmd_status_sie_0 = io_in_bits_cmd_status_sie; // @[LoopConv.scala:1169:7]
wire io_in_bits_cmd_status_uie_0 = io_in_bits_cmd_status_uie; // @[LoopConv.scala:1169:7]
wire io_in_bits_rob_id_valid_0 = io_in_bits_rob_id_valid; // @[LoopConv.scala:1169:7]
wire [5:0] io_in_bits_rob_id_bits_0 = io_in_bits_rob_id_bits; // @[LoopConv.scala:1169:7]
wire io_in_bits_from_matmul_fsm_0 = io_in_bits_from_matmul_fsm; // @[LoopConv.scala:1169:7]
wire io_in_bits_from_conv_fsm_0 = io_in_bits_from_conv_fsm; // @[LoopConv.scala:1169:7]
wire io_out_ready_0 = io_out_ready; // @[LoopConv.scala:1169:7]
wire [5:0] io_ld_completed_0 = io_ld_completed; // @[LoopConv.scala:1169:7]
wire [5:0] io_st_completed_0 = io_st_completed; // @[LoopConv.scala:1169:7]
wire [5:0] io_ex_completed_0 = io_ex_completed; // @[LoopConv.scala:1169:7]
wire io_out_bits_rob_id_valid = 1'h0; // @[LoopConv.scala:1169:7]
wire _loops_max_pixels_per_row_T = 1'h0; // @[LoopConv.scala:1352:11]
wire _loops_wrot180_T_1 = 1'h0; // @[LoopConv.scala:1358:63]
wire _loops_input_dilated_T_1 = 1'h0; // @[LoopConv.scala:1359:69]
wire _loops_trans_output_1203_T_1 = 1'h0; // @[LoopConv.scala:1360:73]
wire _loops_trans_weight_1203_T_1 = 1'h0; // @[LoopConv.scala:1361:73]
wire _loops_trans_weight_0132_T_1 = 1'h0; // @[LoopConv.scala:1362:73]
wire _loops_trans_input_3120_T_1 = 1'h0; // @[LoopConv.scala:1363:72]
wire _loops_no_pool_T = 1'h0; // @[LoopConv.scala:1366:42]
wire _ld_bias_addr_start_T_2 = 1'h0; // @[Util.scala:42:8]
wire _ex_c_addr_start_T_2 = 1'h0; // @[Util.scala:42:8]
wire _st_addr_start_T_2 = 1'h0; // @[Util.scala:42:8]
wire [5:0] io_out_bits_rob_id_bits = 6'h0; // @[LoopConv.scala:1169:7]
wire [12:0] ld_bias_addr_start_max = 13'hFFF; // @[Util.scala:39:28]
wire [12:0] ex_c_addr_start_max = 13'hFFF; // @[Util.scala:39:28]
wire [12:0] st_addr_start_max = 13'hFFF; // @[Util.scala:39:28]
wire [13:0] _ld_bias_addr_start_max_T = 14'hFFF; // @[Util.scala:39:28]
wire [13:0] _ex_c_addr_start_max_T = 14'hFFF; // @[Util.scala:39:28]
wire [13:0] _st_addr_start_max_T = 14'hFFF; // @[Util.scala:39:28]
wire _io_out_valid_T_4; // @[LoopConv.scala:1251:22]
wire [6:0] _io_out_bits_cmd_T_inst_funct; // @[LoopConv.scala:1246:25]
wire [4:0] _io_out_bits_cmd_T_inst_rs2; // @[LoopConv.scala:1246:25]
wire [4:0] _io_out_bits_cmd_T_inst_rs1; // @[LoopConv.scala:1246:25]
wire _io_out_bits_cmd_T_inst_xd; // @[LoopConv.scala:1246:25]
wire _io_out_bits_cmd_T_inst_xs1; // @[LoopConv.scala:1246:25]
wire _io_out_bits_cmd_T_inst_xs2; // @[LoopConv.scala:1246:25]
wire [4:0] _io_out_bits_cmd_T_inst_rd; // @[LoopConv.scala:1246:25]
wire [6:0] _io_out_bits_cmd_T_inst_opcode; // @[LoopConv.scala:1246:25]
wire [63:0] _io_out_bits_cmd_T_rs1; // @[LoopConv.scala:1246:25]
wire [63:0] _io_out_bits_cmd_T_rs2; // @[LoopConv.scala:1246:25]
wire _io_out_bits_from_matmul_fsm_T; // @[LoopConv.scala:1249:37]
wire _io_out_bits_from_conv_fsm_T; // @[LoopConv.scala:1250:35]
wire _io_busy_T; // @[LoopConv.scala:1217:24]
wire io_in_ready_0; // @[LoopConv.scala:1169:7]
wire [6:0] io_out_bits_cmd_inst_funct_0; // @[LoopConv.scala:1169:7]
wire [4:0] io_out_bits_cmd_inst_rs2_0; // @[LoopConv.scala:1169:7]
wire [4:0] io_out_bits_cmd_inst_rs1_0; // @[LoopConv.scala:1169:7]
wire io_out_bits_cmd_inst_xd_0; // @[LoopConv.scala:1169:7]
wire io_out_bits_cmd_inst_xs1_0; // @[LoopConv.scala:1169:7]
wire io_out_bits_cmd_inst_xs2_0; // @[LoopConv.scala:1169:7]
wire [4:0] io_out_bits_cmd_inst_rd_0; // @[LoopConv.scala:1169:7]
wire [6:0] io_out_bits_cmd_inst_opcode_0; // @[LoopConv.scala:1169:7]
wire io_out_bits_cmd_status_debug_0; // @[LoopConv.scala:1169:7]
wire io_out_bits_cmd_status_cease_0; // @[LoopConv.scala:1169:7]
wire io_out_bits_cmd_status_wfi_0; // @[LoopConv.scala:1169:7]
wire [31:0] io_out_bits_cmd_status_isa_0; // @[LoopConv.scala:1169:7]
wire [1:0] io_out_bits_cmd_status_dprv_0; // @[LoopConv.scala:1169:7]
wire io_out_bits_cmd_status_dv_0; // @[LoopConv.scala:1169:7]
wire [1:0] io_out_bits_cmd_status_prv_0; // @[LoopConv.scala:1169:7]
wire io_out_bits_cmd_status_v_0; // @[LoopConv.scala:1169:7]
wire io_out_bits_cmd_status_sd_0; // @[LoopConv.scala:1169:7]
wire [22:0] io_out_bits_cmd_status_zero2_0; // @[LoopConv.scala:1169:7]
wire io_out_bits_cmd_status_mpv_0; // @[LoopConv.scala:1169:7]
wire io_out_bits_cmd_status_gva_0; // @[LoopConv.scala:1169:7]
wire io_out_bits_cmd_status_mbe_0; // @[LoopConv.scala:1169:7]
wire io_out_bits_cmd_status_sbe_0; // @[LoopConv.scala:1169:7]
wire [1:0] io_out_bits_cmd_status_sxl_0; // @[LoopConv.scala:1169:7]
wire [1:0] io_out_bits_cmd_status_uxl_0; // @[LoopConv.scala:1169:7]
wire io_out_bits_cmd_status_sd_rv32_0; // @[LoopConv.scala:1169:7]
wire [7:0] io_out_bits_cmd_status_zero1_0; // @[LoopConv.scala:1169:7]
wire io_out_bits_cmd_status_tsr_0; // @[LoopConv.scala:1169:7]
wire io_out_bits_cmd_status_tw_0; // @[LoopConv.scala:1169:7]
wire io_out_bits_cmd_status_tvm_0; // @[LoopConv.scala:1169:7]
wire io_out_bits_cmd_status_mxr_0; // @[LoopConv.scala:1169:7]
wire io_out_bits_cmd_status_sum_0; // @[LoopConv.scala:1169:7]
wire io_out_bits_cmd_status_mprv_0; // @[LoopConv.scala:1169:7]
wire [1:0] io_out_bits_cmd_status_xs_0; // @[LoopConv.scala:1169:7]
wire [1:0] io_out_bits_cmd_status_fs_0; // @[LoopConv.scala:1169:7]
wire [1:0] io_out_bits_cmd_status_mpp_0; // @[LoopConv.scala:1169:7]
wire [1:0] io_out_bits_cmd_status_vs_0; // @[LoopConv.scala:1169:7]
wire io_out_bits_cmd_status_spp_0; // @[LoopConv.scala:1169:7]
wire io_out_bits_cmd_status_mpie_0; // @[LoopConv.scala:1169:7]
wire io_out_bits_cmd_status_ube_0; // @[LoopConv.scala:1169:7]
wire io_out_bits_cmd_status_spie_0; // @[LoopConv.scala:1169:7]
wire io_out_bits_cmd_status_upie_0; // @[LoopConv.scala:1169:7]
wire io_out_bits_cmd_status_mie_0; // @[LoopConv.scala:1169:7]
wire io_out_bits_cmd_status_hie_0; // @[LoopConv.scala:1169:7]
wire io_out_bits_cmd_status_sie_0; // @[LoopConv.scala:1169:7]
wire io_out_bits_cmd_status_uie_0; // @[LoopConv.scala:1169:7]
wire [63:0] io_out_bits_cmd_rs1_0; // @[LoopConv.scala:1169:7]
wire [63:0] io_out_bits_cmd_rs2_0; // @[LoopConv.scala:1169:7]
wire io_out_bits_from_matmul_fsm_0; // @[LoopConv.scala:1169:7]
wire io_out_bits_from_conv_fsm_0; // @[LoopConv.scala:1169:7]
wire io_out_valid_0; // @[LoopConv.scala:1169:7]
wire io_busy_0; // @[LoopConv.scala:1169:7]
reg [15:0] loops_0_outer_bounds_batch_size; // @[LoopConv.scala:1195:18]
reg [15:0] loops_0_outer_bounds_in_row_dim; // @[LoopConv.scala:1195:18]
reg [15:0] loops_0_outer_bounds_in_col_dim; // @[LoopConv.scala:1195:18]
reg [15:0] loops_0_outer_bounds_in_channels; // @[LoopConv.scala:1195:18]
reg [15:0] loops_0_outer_bounds_out_channels; // @[LoopConv.scala:1195:18]
reg [15:0] loops_0_outer_bounds_out_col_dim; // @[LoopConv.scala:1195:18]
reg [15:0] loops_0_outer_bounds_out_row_dim; // @[LoopConv.scala:1195:18]
reg [15:0] loops_0_outer_bounds_out_stride; // @[LoopConv.scala:1195:18]
reg [15:0] loops_0_outer_bounds_in_stride; // @[LoopConv.scala:1195:18]
reg [15:0] loops_0_outer_bounds_weight_stride; // @[LoopConv.scala:1195:18]
reg [15:0] loops_0_outer_bounds_pool_out_row_dim; // @[LoopConv.scala:1195:18]
reg [15:0] loops_0_outer_bounds_pool_out_col_dim; // @[LoopConv.scala:1195:18]
reg [15:0] loops_0_outer_bounds_stride; // @[LoopConv.scala:1195:18]
reg [15:0] loops_0_outer_bounds_padding; // @[LoopConv.scala:1195:18]
reg [15:0] loops_0_outer_bounds_kernel_dim; // @[LoopConv.scala:1195:18]
reg [15:0] loops_0_outer_bounds_kernel_dilation; // @[LoopConv.scala:1195:18]
reg [15:0] loops_0_outer_bounds_pool_size; // @[LoopConv.scala:1195:18]
reg [15:0] loops_0_outer_bounds_pool_stride; // @[LoopConv.scala:1195:18]
reg [15:0] loops_0_outer_bounds_pool_padding; // @[LoopConv.scala:1195:18]
reg [15:0] loops_0_inner_bounds_batches; // @[LoopConv.scala:1195:18]
reg [15:0] loops_0_inner_bounds_porows; // @[LoopConv.scala:1195:18]
reg [15:0] loops_0_inner_bounds_pocols; // @[LoopConv.scala:1195:18]
reg [15:0] loops_0_inner_bounds_pochs; // @[LoopConv.scala:1195:18]
reg [15:0] loops_0_inner_bounds_krows; // @[LoopConv.scala:1195:18]
reg [15:0] loops_0_inner_bounds_kcols; // @[LoopConv.scala:1195:18]
reg [15:0] loops_0_inner_bounds_kchs; // @[LoopConv.scala:1195:18]
reg [15:0] loops_0_inner_bounds_lpad; // @[LoopConv.scala:1195:18]
reg [15:0] loops_0_inner_bounds_rpad; // @[LoopConv.scala:1195:18]
reg [15:0] loops_0_inner_bounds_upad; // @[LoopConv.scala:1195:18]
reg [15:0] loops_0_inner_bounds_dpad; // @[LoopConv.scala:1195:18]
reg [15:0] loops_0_inner_bounds_plpad; // @[LoopConv.scala:1195:18]
reg [15:0] loops_0_inner_bounds_prad; // @[LoopConv.scala:1195:18]
reg [15:0] loops_0_inner_bounds_pupad; // @[LoopConv.scala:1195:18]
reg [15:0] loops_0_inner_bounds_pdpad; // @[LoopConv.scala:1195:18]
reg [15:0] loops_0_inner_bounds_orows; // @[LoopConv.scala:1195:18]
reg [15:0] loops_0_inner_bounds_ocols; // @[LoopConv.scala:1195:18]
reg [39:0] loops_0_bias_dram_addr; // @[LoopConv.scala:1195:18]
reg [39:0] loops_0_weights_dram_addr; // @[LoopConv.scala:1195:18]
reg [39:0] loops_0_input_dram_addr; // @[LoopConv.scala:1195:18]
reg [39:0] loops_0_output_dram_addr; // @[LoopConv.scala:1195:18]
reg loops_0_no_bias; // @[LoopConv.scala:1195:18]
reg loops_0_wrot180; // @[LoopConv.scala:1195:18]
reg loops_0_no_pool; // @[LoopConv.scala:1195:18]
reg loops_0_downsample; // @[LoopConv.scala:1195:18]
reg loops_0_input_dilated; // @[LoopConv.scala:1195:18]
reg [1:0] loops_0_activation; // @[LoopConv.scala:1195:18]
reg loops_0_trans_output_1203; // @[LoopConv.scala:1195:18]
reg loops_0_trans_weight_1203; // @[LoopConv.scala:1195:18]
reg loops_0_trans_weight_0132; // @[LoopConv.scala:1195:18]
reg loops_0_trans_input_3120; // @[LoopConv.scala:1195:18]
reg loops_0_dw; // @[LoopConv.scala:1195:18]
reg [15:0] loops_0_max_pixels_per_row; // @[LoopConv.scala:1195:18]
reg [1:0] loops_0_a_ex_spad_id; // @[LoopConv.scala:1195:18]
reg [1:0] loops_0_b_ex_spad_id; // @[LoopConv.scala:1195:18]
reg loops_0_configured; // @[LoopConv.scala:1195:18]
reg loops_0_running; // @[LoopConv.scala:1195:18]
reg loops_0_ld_bias_started; // @[LoopConv.scala:1195:18]
reg loops_0_ld_input_started; // @[LoopConv.scala:1195:18]
reg loops_0_ld_weights_started; // @[LoopConv.scala:1195:18]
reg loops_0_ex_started; // @[LoopConv.scala:1195:18]
reg loops_0_st_started; // @[LoopConv.scala:1195:18]
reg loops_0_ld_bias_completed; // @[LoopConv.scala:1195:18]
reg loops_0_ld_input_completed; // @[LoopConv.scala:1195:18]
reg loops_0_ld_weights_completed; // @[LoopConv.scala:1195:18]
reg loops_0_ex_completed; // @[LoopConv.scala:1195:18]
reg loops_0_st_completed; // @[LoopConv.scala:1195:18]
reg [15:0] loops_1_outer_bounds_batch_size; // @[LoopConv.scala:1195:18]
reg [15:0] loops_1_outer_bounds_in_row_dim; // @[LoopConv.scala:1195:18]
reg [15:0] loops_1_outer_bounds_in_col_dim; // @[LoopConv.scala:1195:18]
reg [15:0] loops_1_outer_bounds_in_channels; // @[LoopConv.scala:1195:18]
reg [15:0] loops_1_outer_bounds_out_channels; // @[LoopConv.scala:1195:18]
reg [15:0] loops_1_outer_bounds_out_col_dim; // @[LoopConv.scala:1195:18]
reg [15:0] loops_1_outer_bounds_out_row_dim; // @[LoopConv.scala:1195:18]
reg [15:0] loops_1_outer_bounds_out_stride; // @[LoopConv.scala:1195:18]
reg [15:0] loops_1_outer_bounds_in_stride; // @[LoopConv.scala:1195:18]
reg [15:0] loops_1_outer_bounds_weight_stride; // @[LoopConv.scala:1195:18]
reg [15:0] loops_1_outer_bounds_pool_out_row_dim; // @[LoopConv.scala:1195:18]
reg [15:0] loops_1_outer_bounds_pool_out_col_dim; // @[LoopConv.scala:1195:18]
reg [15:0] loops_1_outer_bounds_stride; // @[LoopConv.scala:1195:18]
reg [15:0] loops_1_outer_bounds_padding; // @[LoopConv.scala:1195:18]
reg [15:0] loops_1_outer_bounds_kernel_dim; // @[LoopConv.scala:1195:18]
reg [15:0] loops_1_outer_bounds_kernel_dilation; // @[LoopConv.scala:1195:18]
reg [15:0] loops_1_outer_bounds_pool_size; // @[LoopConv.scala:1195:18]
reg [15:0] loops_1_outer_bounds_pool_stride; // @[LoopConv.scala:1195:18]
reg [15:0] loops_1_outer_bounds_pool_padding; // @[LoopConv.scala:1195:18]
reg [15:0] loops_1_inner_bounds_batches; // @[LoopConv.scala:1195:18]
reg [15:0] loops_1_inner_bounds_porows; // @[LoopConv.scala:1195:18]
reg [15:0] loops_1_inner_bounds_pocols; // @[LoopConv.scala:1195:18]
reg [15:0] loops_1_inner_bounds_pochs; // @[LoopConv.scala:1195:18]
reg [15:0] loops_1_inner_bounds_krows; // @[LoopConv.scala:1195:18]
reg [15:0] loops_1_inner_bounds_kcols; // @[LoopConv.scala:1195:18]
reg [15:0] loops_1_inner_bounds_kchs; // @[LoopConv.scala:1195:18]
reg [15:0] loops_1_inner_bounds_lpad; // @[LoopConv.scala:1195:18]
reg [15:0] loops_1_inner_bounds_rpad; // @[LoopConv.scala:1195:18]
reg [15:0] loops_1_inner_bounds_upad; // @[LoopConv.scala:1195:18]
reg [15:0] loops_1_inner_bounds_dpad; // @[LoopConv.scala:1195:18]
reg [15:0] loops_1_inner_bounds_plpad; // @[LoopConv.scala:1195:18]
reg [15:0] loops_1_inner_bounds_prad; // @[LoopConv.scala:1195:18]
reg [15:0] loops_1_inner_bounds_pupad; // @[LoopConv.scala:1195:18]
reg [15:0] loops_1_inner_bounds_pdpad; // @[LoopConv.scala:1195:18]
reg [15:0] loops_1_inner_bounds_orows; // @[LoopConv.scala:1195:18]
reg [15:0] loops_1_inner_bounds_ocols; // @[LoopConv.scala:1195:18]
reg [39:0] loops_1_bias_dram_addr; // @[LoopConv.scala:1195:18]
reg [39:0] loops_1_weights_dram_addr; // @[LoopConv.scala:1195:18]
reg [39:0] loops_1_input_dram_addr; // @[LoopConv.scala:1195:18]
reg [39:0] loops_1_output_dram_addr; // @[LoopConv.scala:1195:18]
reg loops_1_no_bias; // @[LoopConv.scala:1195:18]
reg loops_1_wrot180; // @[LoopConv.scala:1195:18]
reg loops_1_no_pool; // @[LoopConv.scala:1195:18]
reg loops_1_downsample; // @[LoopConv.scala:1195:18]
reg loops_1_input_dilated; // @[LoopConv.scala:1195:18]
reg [1:0] loops_1_activation; // @[LoopConv.scala:1195:18]
reg loops_1_trans_output_1203; // @[LoopConv.scala:1195:18]
reg loops_1_trans_weight_1203; // @[LoopConv.scala:1195:18]
reg loops_1_trans_weight_0132; // @[LoopConv.scala:1195:18]
reg loops_1_trans_input_3120; // @[LoopConv.scala:1195:18]
reg loops_1_dw; // @[LoopConv.scala:1195:18]
reg [15:0] loops_1_max_pixels_per_row; // @[LoopConv.scala:1195:18]
reg [1:0] loops_1_a_ex_spad_id; // @[LoopConv.scala:1195:18]
reg [1:0] loops_1_b_ex_spad_id; // @[LoopConv.scala:1195:18]
reg loops_1_configured; // @[LoopConv.scala:1195:18]
reg loops_1_running; // @[LoopConv.scala:1195:18]
reg loops_1_ld_bias_started; // @[LoopConv.scala:1195:18]
reg loops_1_ld_input_started; // @[LoopConv.scala:1195:18]
reg loops_1_ld_weights_started; // @[LoopConv.scala:1195:18]
reg loops_1_ex_started; // @[LoopConv.scala:1195:18]
reg loops_1_st_started; // @[LoopConv.scala:1195:18]
reg loops_1_ld_bias_completed; // @[LoopConv.scala:1195:18]
reg loops_1_ld_input_completed; // @[LoopConv.scala:1195:18]
reg loops_1_ld_weights_completed; // @[LoopConv.scala:1195:18]
reg loops_1_ex_completed; // @[LoopConv.scala:1195:18]
reg loops_1_st_completed; // @[LoopConv.scala:1195:18]
reg head_loop_id; // @[LoopConv.scala:1196:29]
wire tail_loop_id = ~head_loop_id; // @[LoopConv.scala:1196:29, :1197:23]
wire loop_configured = loops_0_configured | loops_1_configured; // @[LoopConv.scala:1195:18, :1201:58]
wire loop_being_configured_id = (head_loop_id ? loops_1_configured : loops_0_configured) ? tail_loop_id : head_loop_id; // @[LoopConv.scala:1195:18, :1196:29, :1197:23, :1203:37]
assign _io_busy_T = _cmd_q_io_deq_valid | loop_configured; // @[Decoupled.scala:362:21]
assign io_busy_0 = _io_busy_T; // @[LoopConv.scala:1169:7, :1217:24]
reg [3:0] ld_utilization; // @[LoopConv.scala:1229:31]
reg [2:0] st_utilization; // @[LoopConv.scala:1230:31]
reg [4:0] ex_utilization; // @[LoopConv.scala:1231:31]
wire _ld_utilization_T = _arb_io_in_2_ready & _ld_bias_io_cmd_valid; // @[Decoupled.scala:51:35]
wire _ld_utilization_T_1 = _arb_io_in_3_ready & _ld_weights_io_cmd_valid; // @[Decoupled.scala:51:35]
wire _ld_utilization_T_2 = _ld_utilization_T | _ld_utilization_T_1; // @[Decoupled.scala:51:35]
wire _ld_utilization_T_3 = _arb_io_in_4_ready & _ld_input_io_cmd_valid; // @[Decoupled.scala:51:35]
wire _ld_utilization_T_4 = _ld_utilization_T_2 | _ld_utilization_T_3; // @[Decoupled.scala:51:35]
wire [4:0] _ld_utilization_T_5 = {1'h0, ld_utilization} + {4'h0, _ld_utilization_T_4}; // @[LoopConv.scala:1229:31, :1233:{36,86}]
wire [6:0] _ld_utilization_T_6 = {2'h0, _ld_utilization_T_5} - {1'h0, io_ld_completed_0}; // @[LoopConv.scala:1169:7, :1233:{36,111}]
wire [6:0] _ld_utilization_T_7 = _ld_utilization_T_6; // @[LoopConv.scala:1233:111]
wire _st_utilization_T = _arb_io_in_0_ready & _st_io_cmd_valid; // @[Decoupled.scala:51:35]
wire [3:0] _st_utilization_T_1 = {1'h0, st_utilization} + {3'h0, _st_utilization_T}; // @[Decoupled.scala:51:35]
wire [6:0] _st_utilization_T_2 = {3'h0, _st_utilization_T_1} - {1'h0, io_st_completed_0}; // @[LoopConv.scala:1169:7, :1234:{36,54}]
wire [6:0] _st_utilization_T_3 = _st_utilization_T_2; // @[LoopConv.scala:1234:54]
wire _ex_utilization_T = _arb_io_in_1_ready & _ex_io_cmd_valid; // @[Decoupled.scala:51:35]
wire [5:0] _GEN = {1'h0, ex_utilization}; // @[LoopConv.scala:1231:31, :1235:36]
wire [5:0] _ex_utilization_T_1 = _GEN + {5'h0, _ex_utilization_T}; // @[Decoupled.scala:51:35]
wire [6:0] _ex_utilization_T_2 = {1'h0, _ex_utilization_T_1} - {1'h0, io_ex_completed_0}; // @[LoopConv.scala:1169:7, :1235:{36,54}]
wire [6:0] _ex_utilization_T_3 = _ex_utilization_T_2; // @[LoopConv.scala:1235:54] |
Generate the Verilog code corresponding to this FIRRTL code module PhitToFlit_p32_f32_3 :
input clock : Clock
input reset : Reset
output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { flit : UInt<32>}}}
reg data : UInt<32>[0], clock
regreset beat : UInt<0>, clock, reset, UInt<0>(0h0)
node _io_in_ready_T = neq(beat, UInt<1>(0h0))
node _io_in_ready_T_1 = or(io.out.ready, _io_in_ready_T)
connect io.in.ready, _io_in_ready_T_1
node _io_out_valid_T = eq(beat, UInt<1>(0h0))
node _io_out_valid_T_1 = and(io.in.valid, _io_out_valid_T)
connect io.out.valid, _io_out_valid_T_1
connect io.out.bits.flit, io.in.bits.phit
node _T = and(io.in.ready, io.in.valid)
when _T :
node _beat_T = eq(beat, UInt<1>(0h0))
node _beat_T_1 = add(beat, UInt<1>(0h1))
node _beat_T_2 = tail(_beat_T_1, 1)
node _beat_T_3 = mux(_beat_T, UInt<1>(0h0), _beat_T_2)
connect beat, _beat_T_3 | module PhitToFlit_p32_f32_3( // @[Serdes.scala:103:7]
input clock, // @[Serdes.scala:103:7]
input reset, // @[Serdes.scala:103:7]
output io_in_ready, // @[Serdes.scala:105:14]
input io_in_valid, // @[Serdes.scala:105:14]
input [31:0] io_in_bits_phit, // @[Serdes.scala:105:14]
input io_out_ready, // @[Serdes.scala:105:14]
output io_out_valid, // @[Serdes.scala:105:14]
output [31:0] io_out_bits_flit // @[Serdes.scala:105:14]
);
wire io_in_valid_0 = io_in_valid; // @[Serdes.scala:103:7]
wire [31:0] io_in_bits_phit_0 = io_in_bits_phit; // @[Serdes.scala:103:7]
wire io_out_ready_0 = io_out_ready; // @[Serdes.scala:103:7]
wire [1:0] _beat_T_1 = 2'h1; // @[Serdes.scala:120:53]
wire _io_out_valid_T = 1'h1; // @[Serdes.scala:116:39]
wire _beat_T = 1'h1; // @[Serdes.scala:120:22]
wire _beat_T_2 = 1'h1; // @[Serdes.scala:120:53]
wire _io_in_ready_T = 1'h0; // @[Serdes.scala:115:39]
wire _io_in_ready_T_1; // @[Serdes.scala:115:31]
wire _beat_T_3 = 1'h0; // @[Serdes.scala:120:16]
wire _io_out_valid_T_1 = io_in_valid_0; // @[Serdes.scala:103:7, :116:31]
wire [31:0] io_out_bits_flit_0 = io_in_bits_phit_0; // @[Serdes.scala:103:7]
assign _io_in_ready_T_1 = io_out_ready_0; // @[Serdes.scala:103:7, :115:31]
wire io_in_ready_0; // @[Serdes.scala:103:7]
wire io_out_valid_0; // @[Serdes.scala:103:7]
assign io_in_ready_0 = _io_in_ready_T_1; // @[Serdes.scala:103:7, :115:31]
assign io_out_valid_0 = _io_out_valid_T_1; // @[Serdes.scala:103:7, :116:31]
assign io_in_ready = io_in_ready_0; // @[Serdes.scala:103:7]
assign io_out_valid = io_out_valid_0; // @[Serdes.scala:103:7]
assign io_out_bits_flit = io_out_bits_flit_0; // @[Serdes.scala:103:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_183 :
output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node rawIn_exp = bits(io.in, 31, 23)
node _rawIn_isZero_T = bits(rawIn_exp, 8, 6)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 32, 32)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 22, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
node _io_out_T = shl(io.in, 0)
connect io.out, _io_out_T
node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22)
node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0))
node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0))
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RecFNToRecFN_183( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module DigitalTop :
output auto : { flip chipyard_prcictrl_domain_reset_setter_clock_in : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, mbus_fixedClockNode_anon_out : { clock : Clock, reset : Reset}, cbus_fixedClockNode_anon_out : { clock : Clock, reset : Reset}}
output psd : { }
output resetctrl : { flip hartIsInReset : UInt<1>[1]}
output debug : { flip clock : Clock, flip reset : Reset, systemjtag : { flip jtag : { TCK : Clock, TMS : UInt<1>, TDI : UInt<1>, flip TDO : { data : UInt<1>, driven : UInt<1>}}, flip reset : Reset, flip mfr_id : UInt<11>, flip part_number : UInt<16>, flip version : UInt<4>}, ndreset : UInt<1>, dmactive : UInt<1>, flip dmactiveAck : UInt<1>}
output mem_tl : { }
output mem_axi4 : { `0` : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}}}
output mmio_axi4 : { }
input l2_frontend_bus_axi4 : { }
input custom_boot : UInt<1>
output serial_tl_0 : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, flip clock_in : Clock}
output serial_tl_0_debug : { ser_busy : UInt<1>, des_busy : UInt<1>}
output uart_0 : { txd : UInt<1>, flip rxd : UInt<1>}
output clock_tap : Clock
input interrupts : UInt<0>
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst ibus of ClockSinkDomain
inst sbus of SystemBus
inst pbus of PeripheryBus_pbus
inst fbus of FrontBus
inst cbus of PeripheryBus_cbus
inst mbus of MemoryBus
inst coh_wrapper of CoherenceManagerWrapper
inst tile_prci_domain of TilePRCIDomain
inst xbar of IntXbar_i1_o1_1
inst xbar_1 of IntXbar_i1_o1_2
inst xbar_2 of IntXbar_i1_o1_3
inst tileHartIdNexusNode of BundleBridgeNexus_UInt1_1
inst broadcast of BundleBridgeNexus_UInt32_1
inst clint_domain of CLINTClockSinkDomain
inst plic_domain of PLICClockSinkDomain
inst tlDM of TLDebugModule
inst debugCustomXbarOpt of DebugCustomXbar
inst nexus of BundleBridgeNexus_TraceBundle
inst nexus_1 of BundleBridgeNexus_TraceCoreInterface
inst bootrom_domain of BootROMClockSinkDomain
inst bank of ScratchpadBank
inst serial_tl_domain of SerialTL0ClockSinkDomain
inst uartClockDomainWrapper of TLUARTClockSinkDomain
inst intsink of IntSyncSyncCrossingSink_n1x1_5
inst chipyard_prcictrl_domain of ChipyardPRCICtrlClockSinkDomain
inst aggregator of ClockGroupAggregator_allClocks
inst clockNamePrefixer of ClockGroupParameterModifier
inst frequencySpecifier of ClockGroupParameterModifier_1
inst clockGroupCombiner of ClockGroupCombiner
inst clockTapNode of ClockGroup_6
inst globalNoCDomain of ClockSinkDomain_1
inst reRoCCManagerIdNexusNode of BundleBridgeNexus_NoOutput_8
wire allClockGroupsNodeOut : { member : { sbus_1 : { clock : Clock, reset : Reset}, sbus_0 : { clock : Clock, reset : Reset}}}
invalidate allClockGroupsNodeOut.member.sbus_0.reset
invalidate allClockGroupsNodeOut.member.sbus_0.clock
invalidate allClockGroupsNodeOut.member.sbus_1.reset
invalidate allClockGroupsNodeOut.member.sbus_1.clock
wire x1_allClockGroupsNodeOut : { member : { pbus_0 : { clock : Clock, reset : Reset}}}
invalidate x1_allClockGroupsNodeOut.member.pbus_0.reset
invalidate x1_allClockGroupsNodeOut.member.pbus_0.clock
wire x1_allClockGroupsNodeOut_1 : { member : { fbus_0 : { clock : Clock, reset : Reset}}}
invalidate x1_allClockGroupsNodeOut_1.member.fbus_0.reset
invalidate x1_allClockGroupsNodeOut_1.member.fbus_0.clock
wire x1_allClockGroupsNodeOut_2 : { member : { mbus_0 : { clock : Clock, reset : Reset}}}
invalidate x1_allClockGroupsNodeOut_2.member.mbus_0.reset
invalidate x1_allClockGroupsNodeOut_2.member.mbus_0.clock
wire x1_allClockGroupsNodeOut_3 : { member : { cbus_0 : { clock : Clock, reset : Reset}}}
invalidate x1_allClockGroupsNodeOut_3.member.cbus_0.reset
invalidate x1_allClockGroupsNodeOut_3.member.cbus_0.clock
wire x1_allClockGroupsNodeOut_4 : { member : { clockTapNode_clock_tap : { clock : Clock, reset : Reset}}}
invalidate x1_allClockGroupsNodeOut_4.member.clockTapNode_clock_tap.reset
invalidate x1_allClockGroupsNodeOut_4.member.clockTapNode_clock_tap.clock
wire allClockGroupsNodeIn : { member : { sbus_1 : { clock : Clock, reset : Reset}, sbus_0 : { clock : Clock, reset : Reset}}}
invalidate allClockGroupsNodeIn.member.sbus_0.reset
invalidate allClockGroupsNodeIn.member.sbus_0.clock
invalidate allClockGroupsNodeIn.member.sbus_1.reset
invalidate allClockGroupsNodeIn.member.sbus_1.clock
wire x1_allClockGroupsNodeIn : { member : { pbus_0 : { clock : Clock, reset : Reset}}}
invalidate x1_allClockGroupsNodeIn.member.pbus_0.reset
invalidate x1_allClockGroupsNodeIn.member.pbus_0.clock
wire x1_allClockGroupsNodeIn_1 : { member : { fbus_0 : { clock : Clock, reset : Reset}}}
invalidate x1_allClockGroupsNodeIn_1.member.fbus_0.reset
invalidate x1_allClockGroupsNodeIn_1.member.fbus_0.clock
wire x1_allClockGroupsNodeIn_2 : { member : { mbus_0 : { clock : Clock, reset : Reset}}}
invalidate x1_allClockGroupsNodeIn_2.member.mbus_0.reset
invalidate x1_allClockGroupsNodeIn_2.member.mbus_0.clock
wire x1_allClockGroupsNodeIn_3 : { member : { cbus_0 : { clock : Clock, reset : Reset}}}
invalidate x1_allClockGroupsNodeIn_3.member.cbus_0.reset
invalidate x1_allClockGroupsNodeIn_3.member.cbus_0.clock
wire x1_allClockGroupsNodeIn_4 : { member : { clockTapNode_clock_tap : { clock : Clock, reset : Reset}}}
invalidate x1_allClockGroupsNodeIn_4.member.clockTapNode_clock_tap.reset
invalidate x1_allClockGroupsNodeIn_4.member.clockTapNode_clock_tap.clock
connect allClockGroupsNodeOut, allClockGroupsNodeIn
connect x1_allClockGroupsNodeOut, x1_allClockGroupsNodeIn
connect x1_allClockGroupsNodeOut_1, x1_allClockGroupsNodeIn_1
connect x1_allClockGroupsNodeOut_2, x1_allClockGroupsNodeIn_2
connect x1_allClockGroupsNodeOut_3, x1_allClockGroupsNodeIn_3
connect x1_allClockGroupsNodeOut_4, x1_allClockGroupsNodeIn_4
wire tileHaltSinkNodeIn : UInt<1>[1]
invalidate tileHaltSinkNodeIn[0]
wire tileWFISinkNodeIn : UInt<1>[1]
invalidate tileWFISinkNodeIn[0]
wire tileCeaseSinkNodeIn : UInt<1>[1]
invalidate tileCeaseSinkNodeIn[0]
wire domainIn : { clock : Clock, reset : Reset}
invalidate domainIn.reset
invalidate domainIn.clock
wire debugNodesOut : { sync : UInt<1>[1]}
invalidate debugNodesOut.sync[0]
wire debugNodesIn : { sync : UInt<1>[1]}
invalidate debugNodesIn.sync[0]
connect debugNodesOut, debugNodesIn
wire traceCoreNodesIn : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>}
invalidate traceCoreNodesIn.cause
invalidate traceCoreNodesIn.tval
invalidate traceCoreNodesIn.priv
invalidate traceCoreNodesIn.group[0].ilastsize
invalidate traceCoreNodesIn.group[0].itype
invalidate traceCoreNodesIn.group[0].iaddr
invalidate traceCoreNodesIn.group[0].iretire
wire traceNodesIn : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>, custom : { rob_empty : UInt<1>}}
invalidate traceNodesIn.custom.rob_empty
invalidate traceNodesIn.time
invalidate traceNodesIn.insns[0].tval
invalidate traceNodesIn.insns[0].cause
invalidate traceNodesIn.insns[0].interrupt
invalidate traceNodesIn.insns[0].exception
invalidate traceNodesIn.insns[0].priv
invalidate traceNodesIn.insns[0].insn
invalidate traceNodesIn.insns[0].iaddr
invalidate traceNodesIn.insns[0].valid
wire memAXI4NodeIn : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}}
invalidate memAXI4NodeIn.r.bits.last
invalidate memAXI4NodeIn.r.bits.resp
invalidate memAXI4NodeIn.r.bits.data
invalidate memAXI4NodeIn.r.bits.id
invalidate memAXI4NodeIn.r.valid
invalidate memAXI4NodeIn.r.ready
invalidate memAXI4NodeIn.ar.bits.qos
invalidate memAXI4NodeIn.ar.bits.prot
invalidate memAXI4NodeIn.ar.bits.cache
invalidate memAXI4NodeIn.ar.bits.lock
invalidate memAXI4NodeIn.ar.bits.burst
invalidate memAXI4NodeIn.ar.bits.size
invalidate memAXI4NodeIn.ar.bits.len
invalidate memAXI4NodeIn.ar.bits.addr
invalidate memAXI4NodeIn.ar.bits.id
invalidate memAXI4NodeIn.ar.valid
invalidate memAXI4NodeIn.ar.ready
invalidate memAXI4NodeIn.b.bits.resp
invalidate memAXI4NodeIn.b.bits.id
invalidate memAXI4NodeIn.b.valid
invalidate memAXI4NodeIn.b.ready
invalidate memAXI4NodeIn.w.bits.last
invalidate memAXI4NodeIn.w.bits.strb
invalidate memAXI4NodeIn.w.bits.data
invalidate memAXI4NodeIn.w.valid
invalidate memAXI4NodeIn.w.ready
invalidate memAXI4NodeIn.aw.bits.qos
invalidate memAXI4NodeIn.aw.bits.prot
invalidate memAXI4NodeIn.aw.bits.cache
invalidate memAXI4NodeIn.aw.bits.lock
invalidate memAXI4NodeIn.aw.bits.burst
invalidate memAXI4NodeIn.aw.bits.size
invalidate memAXI4NodeIn.aw.bits.len
invalidate memAXI4NodeIn.aw.bits.addr
invalidate memAXI4NodeIn.aw.bits.id
invalidate memAXI4NodeIn.aw.valid
invalidate memAXI4NodeIn.aw.ready
wire bootROMResetVectorSourceNodeOut : UInt<32>
invalidate bootROMResetVectorSourceNodeOut
wire intXingOut : { sync : UInt<1>[1]}
invalidate intXingOut.sync[0]
wire intXingIn : { sync : UInt<1>[1]}
invalidate intXingIn.sync[0]
connect intXingOut, intXingIn
wire ioNodeIn : { txd : UInt<1>, flip rxd : UInt<1>}
invalidate ioNodeIn.rxd
invalidate ioNodeIn.txd
wire clockTapIn : { clock : Clock, reset : Reset}
invalidate clockTapIn.reset
invalidate clockTapIn.clock
connect plic_domain.auto.plic_int_in[0], ibus.auto.int_bus_anon_out[0]
connect sbus.auto.sbus_clock_groups_in, allClockGroupsNodeOut
connect pbus.auto.pbus_clock_groups_in, x1_allClockGroupsNodeOut
connect fbus.auto.fbus_clock_groups_in, x1_allClockGroupsNodeOut_1
connect mbus.auto.mbus_clock_groups_in, x1_allClockGroupsNodeOut_2
connect cbus.auto.cbus_clock_groups_in, x1_allClockGroupsNodeOut_3
connect clockTapNode.auto.in, x1_allClockGroupsNodeOut_4
connect coh_wrapper.auto.coh_clock_groups_in, sbus.auto.sbus_clock_groups_out
connect ibus.auto.clock_in, sbus.auto.fixedClockNode_anon_out_0
connect tile_prci_domain.auto.tap_clock_in, sbus.auto.fixedClockNode_anon_out_1
connect globalNoCDomain.auto.clock_in, sbus.auto.fixedClockNode_anon_out_2
connect uartClockDomainWrapper.auto.clock_in, pbus.auto.fixedClockNode_anon_out
connect serial_tl_domain.auto.clock_in, fbus.auto.fixedClockNode_anon_out
connect clint_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_0
connect plic_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_1
connect domainIn, cbus.auto.fixedClockNode_anon_out_2
connect bootrom_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_3
connect chipyard_prcictrl_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_4
connect bank.auto.clock_in, mbus.auto.fixedClockNode_anon_out_0
connect coh_wrapper.auto.l2_ctrls_ctrl_in, cbus.auto.coupler_to_l2_ctrl_buffer_out
connect cbus.auto.bus_xing_in, sbus.auto.coupler_to_bus_named_cbus_bus_xing_out
connect pbus.auto.bus_xing_in, cbus.auto.coupler_to_bus_named_pbus_bus_xing_out
connect sbus.auto.coupler_from_bus_named_fbus_bus_xing_in, fbus.auto.bus_xing_out
connect coh_wrapper.auto.coherent_jbar_anon_in, sbus.auto.coupler_to_bus_named_coh_widget_anon_out
connect mbus.auto.bus_xing_in, coh_wrapper.auto.coupler_to_bus_named_mbus_bus_xing_out
connect nexus.auto.in, tile_prci_domain.auto.element_reset_domain_boom_tile_trace_source_out
connect nexus_1.auto.in, tile_prci_domain.auto.element_reset_domain_boom_tile_trace_core_source_out
connect tileHaltSinkNodeIn, xbar.auto.anon_out
connect tileWFISinkNodeIn, xbar_1.auto.anon_out
connect tileCeaseSinkNodeIn, xbar_2.auto.anon_out
connect tile_prci_domain.auto.element_reset_domain_boom_tile_hartid_in, tileHartIdNexusNode.auto.out
connect tile_prci_domain.auto.element_reset_domain_boom_tile_reset_vector_in, broadcast.auto.out
connect clint_domain.auto.clint_in, cbus.auto.coupler_to_clint_fragmenter_anon_out
connect plic_domain.auto.plic_in, cbus.auto.coupler_to_plic_fragmenter_anon_out
connect debugNodesIn, tlDM.auto.dmOuter_int_out
connect fbus.auto.coupler_from_debug_sb_widget_anon_in, tlDM.auto.dmInner_dmInner_sb2tlOpt_out
connect tlDM.auto.dmInner_dmInner_tl_in, cbus.auto.coupler_to_debug_fragmenter_anon_out
connect tlDM.auto.dmInner_dmInner_custom_in, debugCustomXbarOpt.auto.out
connect tile_prci_domain.auto.intsink_in.sync[0], debugNodesOut.sync[0]
connect sbus.auto.coupler_from_boom_tile_tl_master_clock_xing_in, tile_prci_domain.auto.tl_master_clock_xing_out
connect tile_prci_domain.auto.int_in_clock_xing_in_0.sync[0], clint_domain.auto.int_in_clock_xing_out.sync[0]
connect tile_prci_domain.auto.int_in_clock_xing_in_0.sync[1], clint_domain.auto.int_in_clock_xing_out.sync[1]
connect tile_prci_domain.auto.int_in_clock_xing_in_1.sync[0], plic_domain.auto.int_in_clock_xing_out_0.sync[0]
connect tile_prci_domain.auto.int_in_clock_xing_in_2.sync[0], plic_domain.auto.int_in_clock_xing_out_1.sync[0]
connect xbar.auto.anon_in[0], tile_prci_domain.auto.intsink_out_0[0]
connect xbar_1.auto.anon_in[0], tile_prci_domain.auto.intsink_out_1[0]
connect xbar_2.auto.anon_in[0], tile_prci_domain.auto.intsink_out_2[0]
connect traceNodesIn, nexus.auto.out
connect traceCoreNodesIn, nexus_1.auto.out
connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.r, memAXI4NodeIn.r
connect memAXI4NodeIn.ar.bits, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.ar.bits
connect memAXI4NodeIn.ar.valid, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.ar.valid
connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.ar.ready, memAXI4NodeIn.ar.ready
connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.b, memAXI4NodeIn.b
connect memAXI4NodeIn.w.bits, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.w.bits
connect memAXI4NodeIn.w.valid, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.w.valid
connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.w.ready, memAXI4NodeIn.w.ready
connect memAXI4NodeIn.aw.bits, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.aw.bits
connect memAXI4NodeIn.aw.valid, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.aw.valid
connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.aw.ready, memAXI4NodeIn.aw.ready
connect broadcast.auto.in, bootROMResetVectorSourceNodeOut
connect bootrom_domain.auto.bootrom_in, cbus.auto.coupler_to_bootrom_fragmenter_anon_out
connect bank.auto.xbar_anon_in, mbus.auto.buffer_out
connect fbus.auto.coupler_from_port_named_serial_tl_0_in_buffer_in, serial_tl_domain.auto.serdesser_client_out
connect uartClockDomainWrapper.auto.uart_0_io_out.rxd, ioNodeIn.rxd
connect ioNodeIn.txd, uartClockDomainWrapper.auto.uart_0_io_out.txd
connect uartClockDomainWrapper.auto.uart_0_control_xing_in, pbus.auto.coupler_to_device_named_uart_0_control_xing_out
connect ibus.auto.int_bus_anon_in[0], intsink.auto.out[0]
connect intsink.auto.in.sync[0], intXingOut.sync[0]
connect intXingIn, uartClockDomainWrapper.auto.uart_0_int_xing_out
connect chipyard_prcictrl_domain.auto.xbar_anon_in, cbus.auto.coupler_to_prci_ctrl_fixer_anon_out
connect clockNamePrefixer.auto.clock_name_prefixer_in_0, aggregator.auto.out_0
connect clockNamePrefixer.auto.clock_name_prefixer_in_1, aggregator.auto.out_1
connect clockNamePrefixer.auto.clock_name_prefixer_in_2, aggregator.auto.out_2
connect clockNamePrefixer.auto.clock_name_prefixer_in_3, aggregator.auto.out_3
connect clockNamePrefixer.auto.clock_name_prefixer_in_4, aggregator.auto.out_4
connect clockNamePrefixer.auto.clock_name_prefixer_in_5, aggregator.auto.out_5
connect allClockGroupsNodeIn, clockNamePrefixer.auto.clock_name_prefixer_out_0
connect x1_allClockGroupsNodeIn, clockNamePrefixer.auto.clock_name_prefixer_out_1
connect x1_allClockGroupsNodeIn_1, clockNamePrefixer.auto.clock_name_prefixer_out_2
connect x1_allClockGroupsNodeIn_2, clockNamePrefixer.auto.clock_name_prefixer_out_3
connect x1_allClockGroupsNodeIn_3, clockNamePrefixer.auto.clock_name_prefixer_out_4
connect x1_allClockGroupsNodeIn_4, clockNamePrefixer.auto.clock_name_prefixer_out_5
connect aggregator.auto.in, frequencySpecifier.auto.frequency_specifier_out
connect frequencySpecifier.auto.frequency_specifier_in, clockGroupCombiner.auto.clock_group_combiner_out
connect clockGroupCombiner.auto.clock_group_combiner_in, chipyard_prcictrl_domain.auto.resetSynchronizer_out
connect clockTapIn, clockTapNode.auto.out
connect auto.cbus_fixedClockNode_anon_out, cbus.auto.fixedClockNode_anon_out_5
connect auto.mbus_fixedClockNode_anon_out, mbus.auto.fixedClockNode_anon_out_1
connect chipyard_prcictrl_domain.auto.reset_setter_clock_in, auto.chipyard_prcictrl_domain_reset_setter_clock_in
connect tlDM.io.tl_reset, domainIn.reset
connect tlDM.io.tl_clock, domainIn.clock
connect tlDM.io.hartIsInReset[0], resetctrl.hartIsInReset[0]
connect tlDM.io.debug_reset, debug.reset
connect tlDM.io.debug_clock, debug.clock
connect debug.ndreset, tlDM.io.ctrl.ndreset
connect debug.dmactive, tlDM.io.ctrl.dmactive
connect tlDM.io.ctrl.dmactiveAck, debug.dmactiveAck
connect tlDM.io.ctrl.debugUnavail[0], UInt<1>(0h0)
inst dtm of DebugTransportModuleJTAG
connect dtm.io.jtag, debug.systemjtag.jtag
connect dtm.io.jtag_clock, debug.systemjtag.jtag.TCK
connect dtm.io.jtag_reset, debug.systemjtag.reset
connect dtm.io.jtag_mfr_id, debug.systemjtag.mfr_id
connect dtm.io.jtag_part_number, debug.systemjtag.part_number
connect dtm.io.jtag_version, debug.systemjtag.version
connect dtm.rf_reset, debug.systemjtag.reset
connect tlDM.io.dmi.dmi, dtm.io.dmi
connect tlDM.io.dmi.dmiClock, debug.systemjtag.jtag.TCK
connect tlDM.io.dmi.dmiReset, debug.systemjtag.reset
connect mem_axi4.`0`, memAXI4NodeIn
connect bootROMResetVectorSourceNodeOut, UInt<17>(0h10000)
connect cbus.custom_boot, custom_boot
connect serial_tl_domain.serial_tl_0.clock_in, serial_tl_0.clock_in
connect serial_tl_0.out.bits, serial_tl_domain.serial_tl_0.out.bits
connect serial_tl_0.out.valid, serial_tl_domain.serial_tl_0.out.valid
connect serial_tl_domain.serial_tl_0.out.ready, serial_tl_0.out.ready
connect serial_tl_domain.serial_tl_0.in, serial_tl_0.in
connect serial_tl_0_debug, serial_tl_domain.serial_tl_0_debug
connect uart_0, ioNodeIn
connect clock_tap, clockTapIn.clock
regreset int_rtc_tick_c_value : UInt<10>, clint_domain.clock, clint_domain.reset, UInt<10>(0h0)
wire int_rtc_tick : UInt<1>
connect int_rtc_tick, UInt<1>(0h0)
when UInt<1>(0h1) :
node int_rtc_tick_wrap_wrap = eq(int_rtc_tick_c_value, UInt<10>(0h3e7))
node _int_rtc_tick_wrap_value_T = add(int_rtc_tick_c_value, UInt<1>(0h1))
node _int_rtc_tick_wrap_value_T_1 = tail(_int_rtc_tick_wrap_value_T, 1)
connect int_rtc_tick_c_value, _int_rtc_tick_wrap_value_T_1
when int_rtc_tick_wrap_wrap :
connect int_rtc_tick_c_value, UInt<1>(0h0)
connect int_rtc_tick, int_rtc_tick_wrap_wrap
connect clint_domain.tick, int_rtc_tick
extmodule GenericDigitalInIOCell :
input pad : UInt<1>
output i : UInt<1>
input ie : UInt<1>
defname = GenericDigitalInIOCell
extmodule GenericDigitalOutIOCell :
output pad : UInt<1>
input o : UInt<1>
input oe : UInt<1>
defname = GenericDigitalOutIOCell
extmodule GenericDigitalInIOCell_1 :
input pad : UInt<1>
output i : UInt<1>
input ie : UInt<1>
defname = GenericDigitalInIOCell | module DigitalTop( // @[DigitalTop.scala:47:7]
input auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25]
input auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25]
output auto_mbus_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25]
output auto_mbus_fixedClockNode_anon_out_reset, // @[LazyModuleImp.scala:107:25]
output auto_cbus_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25]
output auto_cbus_fixedClockNode_anon_out_reset, // @[LazyModuleImp.scala:107:25]
input resetctrl_hartIsInReset_0, // @[Periphery.scala:116:25]
input debug_clock, // @[Periphery.scala:125:19]
input debug_reset, // @[Periphery.scala:125:19]
input debug_systemjtag_jtag_TCK, // @[Periphery.scala:125:19]
input debug_systemjtag_jtag_TMS, // @[Periphery.scala:125:19]
input debug_systemjtag_jtag_TDI, // @[Periphery.scala:125:19]
output debug_systemjtag_jtag_TDO_data, // @[Periphery.scala:125:19]
input debug_systemjtag_reset, // @[Periphery.scala:125:19]
output debug_dmactive, // @[Periphery.scala:125:19]
input debug_dmactiveAck, // @[Periphery.scala:125:19]
input mem_axi4_0_aw_ready, // @[SinkNode.scala:76:21]
output mem_axi4_0_aw_valid, // @[SinkNode.scala:76:21]
output [3:0] mem_axi4_0_aw_bits_id, // @[SinkNode.scala:76:21]
output [31:0] mem_axi4_0_aw_bits_addr, // @[SinkNode.scala:76:21]
output [7:0] mem_axi4_0_aw_bits_len, // @[SinkNode.scala:76:21]
output [2:0] mem_axi4_0_aw_bits_size, // @[SinkNode.scala:76:21]
output [1:0] mem_axi4_0_aw_bits_burst, // @[SinkNode.scala:76:21]
output mem_axi4_0_aw_bits_lock, // @[SinkNode.scala:76:21]
output [3:0] mem_axi4_0_aw_bits_cache, // @[SinkNode.scala:76:21]
output [2:0] mem_axi4_0_aw_bits_prot, // @[SinkNode.scala:76:21]
output [3:0] mem_axi4_0_aw_bits_qos, // @[SinkNode.scala:76:21]
input mem_axi4_0_w_ready, // @[SinkNode.scala:76:21]
output mem_axi4_0_w_valid, // @[SinkNode.scala:76:21]
output [63:0] mem_axi4_0_w_bits_data, // @[SinkNode.scala:76:21]
output [7:0] mem_axi4_0_w_bits_strb, // @[SinkNode.scala:76:21]
output mem_axi4_0_w_bits_last, // @[SinkNode.scala:76:21]
output mem_axi4_0_b_ready, // @[SinkNode.scala:76:21]
input mem_axi4_0_b_valid, // @[SinkNode.scala:76:21]
input [3:0] mem_axi4_0_b_bits_id, // @[SinkNode.scala:76:21]
input [1:0] mem_axi4_0_b_bits_resp, // @[SinkNode.scala:76:21]
input mem_axi4_0_ar_ready, // @[SinkNode.scala:76:21]
output mem_axi4_0_ar_valid, // @[SinkNode.scala:76:21]
output [3:0] mem_axi4_0_ar_bits_id, // @[SinkNode.scala:76:21]
output [31:0] mem_axi4_0_ar_bits_addr, // @[SinkNode.scala:76:21]
output [7:0] mem_axi4_0_ar_bits_len, // @[SinkNode.scala:76:21]
output [2:0] mem_axi4_0_ar_bits_size, // @[SinkNode.scala:76:21]
output [1:0] mem_axi4_0_ar_bits_burst, // @[SinkNode.scala:76:21]
output mem_axi4_0_ar_bits_lock, // @[SinkNode.scala:76:21]
output [3:0] mem_axi4_0_ar_bits_cache, // @[SinkNode.scala:76:21]
output [2:0] mem_axi4_0_ar_bits_prot, // @[SinkNode.scala:76:21]
output [3:0] mem_axi4_0_ar_bits_qos, // @[SinkNode.scala:76:21]
output mem_axi4_0_r_ready, // @[SinkNode.scala:76:21]
input mem_axi4_0_r_valid, // @[SinkNode.scala:76:21]
input [3:0] mem_axi4_0_r_bits_id, // @[SinkNode.scala:76:21]
input [63:0] mem_axi4_0_r_bits_data, // @[SinkNode.scala:76:21]
input [1:0] mem_axi4_0_r_bits_resp, // @[SinkNode.scala:76:21]
input mem_axi4_0_r_bits_last, // @[SinkNode.scala:76:21]
input custom_boot, // @[CustomBootPin.scala:73:27]
output serial_tl_0_in_ready, // @[PeripheryTLSerial.scala:220:24]
input serial_tl_0_in_valid, // @[PeripheryTLSerial.scala:220:24]
input [31:0] serial_tl_0_in_bits_phit, // @[PeripheryTLSerial.scala:220:24]
input serial_tl_0_out_ready, // @[PeripheryTLSerial.scala:220:24]
output serial_tl_0_out_valid, // @[PeripheryTLSerial.scala:220:24]
output [31:0] serial_tl_0_out_bits_phit, // @[PeripheryTLSerial.scala:220:24]
input serial_tl_0_clock_in, // @[PeripheryTLSerial.scala:220:24]
output uart_0_txd, // @[BundleBridgeSink.scala:25:19]
input uart_0_rxd, // @[BundleBridgeSink.scala:25:19]
output clock_tap // @[CanHaveClockTap.scala:23:23]
);
wire clockTapNode_auto_out_reset; // @[ClockGroup.scala:24:9]
wire clockTapNode_auto_out_clock; // @[ClockGroup.scala:24:9]
wire clockTapNode_auto_in_member_clockTapNode_clock_tap_reset; // @[ClockGroup.scala:24:9]
wire clockTapNode_auto_in_member_clockTapNode_clock_tap_clock; // @[ClockGroup.scala:24:9]
wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire [63:0] nexus_auto_out_time; // @[BundleBridgeNexus.scala:20:9]
wire nexus_auto_out_custom_rob_empty; // @[BundleBridgeNexus.scala:20:9]
wire [63:0] nexus_auto_in_time; // @[BundleBridgeNexus.scala:20:9]
wire nexus_auto_in_custom_rob_empty; // @[BundleBridgeNexus.scala:20:9]
wire ibus_auto_clock_in_reset; // @[ClockDomain.scala:14:9]
wire ibus_auto_clock_in_clock; // @[ClockDomain.scala:14:9]
wire _dtm_io_dmi_req_valid; // @[Periphery.scala:166:21]
wire [6:0] _dtm_io_dmi_req_bits_addr; // @[Periphery.scala:166:21]
wire [31:0] _dtm_io_dmi_req_bits_data; // @[Periphery.scala:166:21]
wire [1:0] _dtm_io_dmi_req_bits_op; // @[Periphery.scala:166:21]
wire _dtm_io_dmi_resp_ready; // @[Periphery.scala:166:21]
wire _chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_clock; // @[BusWrapper.scala:89:28]
wire _chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_reset; // @[BusWrapper.scala:89:28]
wire _chipyard_prcictrl_domain_auto_xbar_anon_in_a_ready; // @[BusWrapper.scala:89:28]
wire _chipyard_prcictrl_domain_auto_xbar_anon_in_d_valid; // @[BusWrapper.scala:89:28]
wire [2:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_opcode; // @[BusWrapper.scala:89:28]
wire [2:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_size; // @[BusWrapper.scala:89:28]
wire [6:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_source; // @[BusWrapper.scala:89:28]
wire [63:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_data; // @[BusWrapper.scala:89:28]
wire _uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready; // @[UART.scala:270:44]
wire _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid; // @[UART.scala:270:44]
wire [2:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode; // @[UART.scala:270:44]
wire [1:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size; // @[UART.scala:270:44]
wire [10:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source; // @[UART.scala:270:44]
wire [63:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data; // @[UART.scala:270:44]
wire _serial_tl_domain_auto_serdesser_client_out_a_valid; // @[PeripheryTLSerial.scala:116:38]
wire [2:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_opcode; // @[PeripheryTLSerial.scala:116:38]
wire [2:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_param; // @[PeripheryTLSerial.scala:116:38]
wire [3:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_size; // @[PeripheryTLSerial.scala:116:38]
wire [3:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_source; // @[PeripheryTLSerial.scala:116:38]
wire [31:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_address; // @[PeripheryTLSerial.scala:116:38]
wire [7:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_mask; // @[PeripheryTLSerial.scala:116:38]
wire [63:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_data; // @[PeripheryTLSerial.scala:116:38]
wire _serial_tl_domain_auto_serdesser_client_out_a_bits_corrupt; // @[PeripheryTLSerial.scala:116:38]
wire _serial_tl_domain_auto_serdesser_client_out_d_ready; // @[PeripheryTLSerial.scala:116:38]
wire _serial_tl_domain_serial_tl_0_debug_ser_busy; // @[PeripheryTLSerial.scala:116:38]
wire _serial_tl_domain_serial_tl_0_debug_des_busy; // @[PeripheryTLSerial.scala:116:38]
wire _bank_auto_xbar_anon_in_a_ready; // @[Scratchpad.scala:65:28]
wire _bank_auto_xbar_anon_in_d_valid; // @[Scratchpad.scala:65:28]
wire [2:0] _bank_auto_xbar_anon_in_d_bits_opcode; // @[Scratchpad.scala:65:28]
wire [1:0] _bank_auto_xbar_anon_in_d_bits_param; // @[Scratchpad.scala:65:28]
wire [2:0] _bank_auto_xbar_anon_in_d_bits_size; // @[Scratchpad.scala:65:28]
wire [3:0] _bank_auto_xbar_anon_in_d_bits_source; // @[Scratchpad.scala:65:28]
wire _bank_auto_xbar_anon_in_d_bits_sink; // @[Scratchpad.scala:65:28]
wire _bank_auto_xbar_anon_in_d_bits_denied; // @[Scratchpad.scala:65:28]
wire [63:0] _bank_auto_xbar_anon_in_d_bits_data; // @[Scratchpad.scala:65:28]
wire _bank_auto_xbar_anon_in_d_bits_corrupt; // @[Scratchpad.scala:65:28]
wire _bootrom_domain_auto_bootrom_in_a_ready; // @[BusWrapper.scala:89:28]
wire _bootrom_domain_auto_bootrom_in_d_valid; // @[BusWrapper.scala:89:28]
wire [1:0] _bootrom_domain_auto_bootrom_in_d_bits_size; // @[BusWrapper.scala:89:28]
wire [10:0] _bootrom_domain_auto_bootrom_in_d_bits_source; // @[BusWrapper.scala:89:28]
wire [63:0] _bootrom_domain_auto_bootrom_in_d_bits_data; // @[BusWrapper.scala:89:28]
wire _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_valid; // @[Periphery.scala:88:26]
wire [2:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode; // @[Periphery.scala:88:26]
wire [3:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size; // @[Periphery.scala:88:26]
wire [31:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address; // @[Periphery.scala:88:26]
wire [7:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data; // @[Periphery.scala:88:26]
wire _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_d_ready; // @[Periphery.scala:88:26]
wire _tlDM_auto_dmInner_dmInner_tl_in_a_ready; // @[Periphery.scala:88:26]
wire _tlDM_auto_dmInner_dmInner_tl_in_d_valid; // @[Periphery.scala:88:26]
wire [2:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_opcode; // @[Periphery.scala:88:26]
wire [1:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_size; // @[Periphery.scala:88:26]
wire [10:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_source; // @[Periphery.scala:88:26]
wire [63:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_data; // @[Periphery.scala:88:26]
wire _tlDM_io_dmi_dmi_req_ready; // @[Periphery.scala:88:26]
wire _tlDM_io_dmi_dmi_resp_valid; // @[Periphery.scala:88:26]
wire [31:0] _tlDM_io_dmi_dmi_resp_bits_data; // @[Periphery.scala:88:26]
wire [1:0] _tlDM_io_dmi_dmi_resp_bits_resp; // @[Periphery.scala:88:26]
wire _plic_domain_auto_plic_in_a_ready; // @[BusWrapper.scala:89:28]
wire _plic_domain_auto_plic_in_d_valid; // @[BusWrapper.scala:89:28]
wire [2:0] _plic_domain_auto_plic_in_d_bits_opcode; // @[BusWrapper.scala:89:28]
wire [1:0] _plic_domain_auto_plic_in_d_bits_size; // @[BusWrapper.scala:89:28]
wire [10:0] _plic_domain_auto_plic_in_d_bits_source; // @[BusWrapper.scala:89:28]
wire [63:0] _plic_domain_auto_plic_in_d_bits_data; // @[BusWrapper.scala:89:28]
wire _plic_domain_auto_int_in_clock_xing_out_1_sync_0; // @[BusWrapper.scala:89:28]
wire _plic_domain_auto_int_in_clock_xing_out_0_sync_0; // @[BusWrapper.scala:89:28]
wire _clint_domain_auto_clint_in_a_ready; // @[BusWrapper.scala:89:28]
wire _clint_domain_auto_clint_in_d_valid; // @[BusWrapper.scala:89:28]
wire [2:0] _clint_domain_auto_clint_in_d_bits_opcode; // @[BusWrapper.scala:89:28]
wire [1:0] _clint_domain_auto_clint_in_d_bits_size; // @[BusWrapper.scala:89:28]
wire [10:0] _clint_domain_auto_clint_in_d_bits_source; // @[BusWrapper.scala:89:28]
wire [63:0] _clint_domain_auto_clint_in_d_bits_data; // @[BusWrapper.scala:89:28]
wire _clint_domain_auto_int_in_clock_xing_out_sync_0; // @[BusWrapper.scala:89:28]
wire _clint_domain_auto_int_in_clock_xing_out_sync_1; // @[BusWrapper.scala:89:28]
wire _clint_domain_clock; // @[BusWrapper.scala:89:28]
wire _clint_domain_reset; // @[BusWrapper.scala:89:28]
wire _tileHartIdNexusNode_auto_out; // @[HasTiles.scala:75:39]
wire _tile_prci_domain_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38]
wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38]
wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38]
wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38]
wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38]
wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38]
wire [7:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38]
wire [63:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38]
wire _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38]
wire _tile_prci_domain_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38]
wire _tile_prci_domain_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38]
wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38]
wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38]
wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38]
wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38]
wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38]
wire [63:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38]
wire _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38]
wire _tile_prci_domain_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38]
wire _tile_prci_domain_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38]
wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38]
wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid; // @[BankedCoherenceParams.scala:56:31]
wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode; // @[BankedCoherenceParams.scala:56:31]
wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param; // @[BankedCoherenceParams.scala:56:31]
wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size; // @[BankedCoherenceParams.scala:56:31]
wire [3:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source; // @[BankedCoherenceParams.scala:56:31]
wire [31:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address; // @[BankedCoherenceParams.scala:56:31]
wire [7:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask; // @[BankedCoherenceParams.scala:56:31]
wire [63:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data; // @[BankedCoherenceParams.scala:56:31]
wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt; // @[BankedCoherenceParams.scala:56:31]
wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready; // @[BankedCoherenceParams.scala:56:31]
wire _coh_wrapper_auto_coherent_jbar_anon_in_a_ready; // @[BankedCoherenceParams.scala:56:31]
wire _coh_wrapper_auto_coherent_jbar_anon_in_b_valid; // @[BankedCoherenceParams.scala:56:31]
wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_b_bits_param; // @[BankedCoherenceParams.scala:56:31]
wire [31:0] _coh_wrapper_auto_coherent_jbar_anon_in_b_bits_address; // @[BankedCoherenceParams.scala:56:31]
wire _coh_wrapper_auto_coherent_jbar_anon_in_c_ready; // @[BankedCoherenceParams.scala:56:31]
wire _coh_wrapper_auto_coherent_jbar_anon_in_d_valid; // @[BankedCoherenceParams.scala:56:31]
wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_opcode; // @[BankedCoherenceParams.scala:56:31]
wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_param; // @[BankedCoherenceParams.scala:56:31]
wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_size; // @[BankedCoherenceParams.scala:56:31]
wire [5:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_source; // @[BankedCoherenceParams.scala:56:31]
wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_sink; // @[BankedCoherenceParams.scala:56:31]
wire _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_denied; // @[BankedCoherenceParams.scala:56:31]
wire [63:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_data; // @[BankedCoherenceParams.scala:56:31]
wire _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_corrupt; // @[BankedCoherenceParams.scala:56:31]
wire _coh_wrapper_auto_l2_ctrls_ctrl_in_a_ready; // @[BankedCoherenceParams.scala:56:31]
wire _coh_wrapper_auto_l2_ctrls_ctrl_in_d_valid; // @[BankedCoherenceParams.scala:56:31]
wire [2:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_opcode; // @[BankedCoherenceParams.scala:56:31]
wire [1:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_size; // @[BankedCoherenceParams.scala:56:31]
wire [10:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_source; // @[BankedCoherenceParams.scala:56:31]
wire [63:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_data; // @[BankedCoherenceParams.scala:56:31]
wire _mbus_auto_buffer_out_a_valid; // @[MemoryBus.scala:30:26]
wire [2:0] _mbus_auto_buffer_out_a_bits_opcode; // @[MemoryBus.scala:30:26]
wire [2:0] _mbus_auto_buffer_out_a_bits_param; // @[MemoryBus.scala:30:26]
wire [2:0] _mbus_auto_buffer_out_a_bits_size; // @[MemoryBus.scala:30:26]
wire [3:0] _mbus_auto_buffer_out_a_bits_source; // @[MemoryBus.scala:30:26]
wire [27:0] _mbus_auto_buffer_out_a_bits_address; // @[MemoryBus.scala:30:26]
wire [7:0] _mbus_auto_buffer_out_a_bits_mask; // @[MemoryBus.scala:30:26]
wire [63:0] _mbus_auto_buffer_out_a_bits_data; // @[MemoryBus.scala:30:26]
wire _mbus_auto_buffer_out_a_bits_corrupt; // @[MemoryBus.scala:30:26]
wire _mbus_auto_buffer_out_d_ready; // @[MemoryBus.scala:30:26]
wire _mbus_auto_fixedClockNode_anon_out_0_clock; // @[MemoryBus.scala:30:26]
wire _mbus_auto_fixedClockNode_anon_out_0_reset; // @[MemoryBus.scala:30:26]
wire _mbus_auto_bus_xing_in_a_ready; // @[MemoryBus.scala:30:26]
wire _mbus_auto_bus_xing_in_d_valid; // @[MemoryBus.scala:30:26]
wire [2:0] _mbus_auto_bus_xing_in_d_bits_opcode; // @[MemoryBus.scala:30:26]
wire [1:0] _mbus_auto_bus_xing_in_d_bits_param; // @[MemoryBus.scala:30:26]
wire [2:0] _mbus_auto_bus_xing_in_d_bits_size; // @[MemoryBus.scala:30:26]
wire [3:0] _mbus_auto_bus_xing_in_d_bits_source; // @[MemoryBus.scala:30:26]
wire _mbus_auto_bus_xing_in_d_bits_sink; // @[MemoryBus.scala:30:26]
wire _mbus_auto_bus_xing_in_d_bits_denied; // @[MemoryBus.scala:30:26]
wire [63:0] _mbus_auto_bus_xing_in_d_bits_data; // @[MemoryBus.scala:30:26]
wire _mbus_auto_bus_xing_in_d_bits_corrupt; // @[MemoryBus.scala:30:26]
wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26]
wire [6:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26]
wire [20:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26]
wire [7:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26]
wire [63:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26]
wire [1:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26]
wire [10:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26]
wire [16:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26]
wire [7:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26]
wire [63:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26]
wire [1:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26]
wire [10:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26]
wire [11:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26]
wire [7:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26]
wire [63:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26]
wire [1:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26]
wire [10:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26]
wire [27:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26]
wire [7:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26]
wire [63:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26]
wire [1:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26]
wire [10:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26]
wire [25:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26]
wire [7:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26]
wire [63:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size; // @[PeripheryBus.scala:37:26]
wire [6:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source; // @[PeripheryBus.scala:37:26]
wire [28:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address; // @[PeripheryBus.scala:37:26]
wire [7:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask; // @[PeripheryBus.scala:37:26]
wire [63:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_valid; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_param; // @[PeripheryBus.scala:37:26]
wire [1:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_size; // @[PeripheryBus.scala:37:26]
wire [10:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_source; // @[PeripheryBus.scala:37:26]
wire [25:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_address; // @[PeripheryBus.scala:37:26]
wire [7:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask; // @[PeripheryBus.scala:37:26]
wire [63:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_data; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_d_ready; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_fixedClockNode_anon_out_4_clock; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_fixedClockNode_anon_out_4_reset; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_fixedClockNode_anon_out_3_clock; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_fixedClockNode_anon_out_3_reset; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_fixedClockNode_anon_out_1_clock; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_fixedClockNode_anon_out_1_reset; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_fixedClockNode_anon_out_0_clock; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_fixedClockNode_anon_out_0_reset; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_bus_xing_in_a_ready; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_bus_xing_in_d_valid; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_bus_xing_in_d_bits_opcode; // @[PeripheryBus.scala:37:26]
wire [1:0] _cbus_auto_bus_xing_in_d_bits_param; // @[PeripheryBus.scala:37:26]
wire [3:0] _cbus_auto_bus_xing_in_d_bits_size; // @[PeripheryBus.scala:37:26]
wire [5:0] _cbus_auto_bus_xing_in_d_bits_source; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_bus_xing_in_d_bits_sink; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_bus_xing_in_d_bits_denied; // @[PeripheryBus.scala:37:26]
wire [63:0] _cbus_auto_bus_xing_in_d_bits_data; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_bus_xing_in_d_bits_corrupt; // @[PeripheryBus.scala:37:26]
wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready; // @[FrontBus.scala:23:26]
wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid; // @[FrontBus.scala:23:26]
wire [2:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode; // @[FrontBus.scala:23:26]
wire [1:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param; // @[FrontBus.scala:23:26]
wire [3:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size; // @[FrontBus.scala:23:26]
wire [3:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source; // @[FrontBus.scala:23:26]
wire [2:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink; // @[FrontBus.scala:23:26]
wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied; // @[FrontBus.scala:23:26]
wire [63:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data; // @[FrontBus.scala:23:26]
wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt; // @[FrontBus.scala:23:26]
wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_a_ready; // @[FrontBus.scala:23:26]
wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_valid; // @[FrontBus.scala:23:26]
wire [2:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode; // @[FrontBus.scala:23:26]
wire [1:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_param; // @[FrontBus.scala:23:26]
wire [3:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_size; // @[FrontBus.scala:23:26]
wire [2:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink; // @[FrontBus.scala:23:26]
wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied; // @[FrontBus.scala:23:26]
wire [7:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_data; // @[FrontBus.scala:23:26]
wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt; // @[FrontBus.scala:23:26]
wire _fbus_auto_fixedClockNode_anon_out_clock; // @[FrontBus.scala:23:26]
wire _fbus_auto_fixedClockNode_anon_out_reset; // @[FrontBus.scala:23:26]
wire _fbus_auto_bus_xing_out_a_valid; // @[FrontBus.scala:23:26]
wire [2:0] _fbus_auto_bus_xing_out_a_bits_opcode; // @[FrontBus.scala:23:26]
wire [2:0] _fbus_auto_bus_xing_out_a_bits_param; // @[FrontBus.scala:23:26]
wire [3:0] _fbus_auto_bus_xing_out_a_bits_size; // @[FrontBus.scala:23:26]
wire [4:0] _fbus_auto_bus_xing_out_a_bits_source; // @[FrontBus.scala:23:26]
wire [31:0] _fbus_auto_bus_xing_out_a_bits_address; // @[FrontBus.scala:23:26]
wire [7:0] _fbus_auto_bus_xing_out_a_bits_mask; // @[FrontBus.scala:23:26]
wire [63:0] _fbus_auto_bus_xing_out_a_bits_data; // @[FrontBus.scala:23:26]
wire _fbus_auto_bus_xing_out_a_bits_corrupt; // @[FrontBus.scala:23:26]
wire _fbus_auto_bus_xing_out_d_ready; // @[FrontBus.scala:23:26]
wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid; // @[PeripheryBus.scala:37:26]
wire [2:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode; // @[PeripheryBus.scala:37:26]
wire [2:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param; // @[PeripheryBus.scala:37:26]
wire [1:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size; // @[PeripheryBus.scala:37:26]
wire [10:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source; // @[PeripheryBus.scala:37:26]
wire [28:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address; // @[PeripheryBus.scala:37:26]
wire [7:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask; // @[PeripheryBus.scala:37:26]
wire [63:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data; // @[PeripheryBus.scala:37:26]
wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26]
wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready; // @[PeripheryBus.scala:37:26]
wire _pbus_auto_fixedClockNode_anon_out_clock; // @[PeripheryBus.scala:37:26]
wire _pbus_auto_fixedClockNode_anon_out_reset; // @[PeripheryBus.scala:37:26]
wire _pbus_auto_bus_xing_in_a_ready; // @[PeripheryBus.scala:37:26]
wire _pbus_auto_bus_xing_in_d_valid; // @[PeripheryBus.scala:37:26]
wire [2:0] _pbus_auto_bus_xing_in_d_bits_opcode; // @[PeripheryBus.scala:37:26]
wire [1:0] _pbus_auto_bus_xing_in_d_bits_param; // @[PeripheryBus.scala:37:26]
wire [2:0] _pbus_auto_bus_xing_in_d_bits_size; // @[PeripheryBus.scala:37:26]
wire [6:0] _pbus_auto_bus_xing_in_d_bits_source; // @[PeripheryBus.scala:37:26]
wire _pbus_auto_bus_xing_in_d_bits_sink; // @[PeripheryBus.scala:37:26]
wire _pbus_auto_bus_xing_in_d_bits_denied; // @[PeripheryBus.scala:37:26]
wire [63:0] _pbus_auto_bus_xing_in_d_bits_data; // @[PeripheryBus.scala:37:26]
wire _pbus_auto_bus_xing_in_d_bits_corrupt; // @[PeripheryBus.scala:37:26]
wire _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_ready; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_valid; // @[SystemBus.scala:31:26]
wire [1:0] _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_bits_param; // @[SystemBus.scala:31:26]
wire [31:0] _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_bits_address; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_ready; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_valid; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_opcode; // @[SystemBus.scala:31:26]
wire [1:0] _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_param; // @[SystemBus.scala:31:26]
wire [3:0] _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_size; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_source; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_sink; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_denied; // @[SystemBus.scala:31:26]
wire [63:0] _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_data; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_corrupt; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_valid; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size; // @[SystemBus.scala:31:26]
wire [5:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source; // @[SystemBus.scala:31:26]
wire [31:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address; // @[SystemBus.scala:31:26]
wire [7:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask; // @[SystemBus.scala:31:26]
wire [63:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_b_ready; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_valid; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size; // @[SystemBus.scala:31:26]
wire [5:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source; // @[SystemBus.scala:31:26]
wire [31:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address; // @[SystemBus.scala:31:26]
wire [63:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_d_ready; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_valid; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode; // @[SystemBus.scala:31:26]
wire [1:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param; // @[SystemBus.scala:31:26]
wire [3:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size; // @[SystemBus.scala:31:26]
wire [4:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied; // @[SystemBus.scala:31:26]
wire [63:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param; // @[SystemBus.scala:31:26]
wire [3:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size; // @[SystemBus.scala:31:26]
wire [5:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source; // @[SystemBus.scala:31:26]
wire [28:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address; // @[SystemBus.scala:31:26]
wire [7:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask; // @[SystemBus.scala:31:26]
wire [63:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready; // @[SystemBus.scala:31:26]
wire _sbus_auto_fixedClockNode_anon_out_2_clock; // @[SystemBus.scala:31:26]
wire _sbus_auto_fixedClockNode_anon_out_2_reset; // @[SystemBus.scala:31:26]
wire _sbus_auto_fixedClockNode_anon_out_1_clock; // @[SystemBus.scala:31:26]
wire _sbus_auto_fixedClockNode_anon_out_1_reset; // @[SystemBus.scala:31:26]
wire _sbus_auto_sbus_clock_groups_out_member_coh_0_clock; // @[SystemBus.scala:31:26]
wire _sbus_auto_sbus_clock_groups_out_member_coh_0_reset; // @[SystemBus.scala:31:26]
wire auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock_0 = auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock; // @[DigitalTop.scala:47:7]
wire auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset_0 = auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset; // @[DigitalTop.scala:47:7]
wire resetctrl_hartIsInReset_0_0 = resetctrl_hartIsInReset_0; // @[DigitalTop.scala:47:7]
wire debug_clock_0 = debug_clock; // @[DigitalTop.scala:47:7]
wire debug_reset_0 = debug_reset; // @[DigitalTop.scala:47:7]
wire debug_systemjtag_jtag_TCK_0 = debug_systemjtag_jtag_TCK; // @[DigitalTop.scala:47:7]
wire debug_systemjtag_jtag_TMS_0 = debug_systemjtag_jtag_TMS; // @[DigitalTop.scala:47:7]
wire debug_systemjtag_jtag_TDI_0 = debug_systemjtag_jtag_TDI; // @[DigitalTop.scala:47:7]
wire debug_systemjtag_reset_0 = debug_systemjtag_reset; // @[DigitalTop.scala:47:7]
wire debug_dmactiveAck_0 = debug_dmactiveAck; // @[DigitalTop.scala:47:7]
wire mem_axi4_0_aw_ready_0 = mem_axi4_0_aw_ready; // @[DigitalTop.scala:47:7]
wire mem_axi4_0_w_ready_0 = mem_axi4_0_w_ready; // @[DigitalTop.scala:47:7]
wire mem_axi4_0_b_valid_0 = mem_axi4_0_b_valid; // @[DigitalTop.scala:47:7]
wire [3:0] mem_axi4_0_b_bits_id_0 = mem_axi4_0_b_bits_id; // @[DigitalTop.scala:47:7]
wire [1:0] mem_axi4_0_b_bits_resp_0 = mem_axi4_0_b_bits_resp; // @[DigitalTop.scala:47:7]
wire mem_axi4_0_ar_ready_0 = mem_axi4_0_ar_ready; // @[DigitalTop.scala:47:7]
wire mem_axi4_0_r_valid_0 = mem_axi4_0_r_valid; // @[DigitalTop.scala:47:7]
wire [3:0] mem_axi4_0_r_bits_id_0 = mem_axi4_0_r_bits_id; // @[DigitalTop.scala:47:7]
wire [63:0] mem_axi4_0_r_bits_data_0 = mem_axi4_0_r_bits_data; // @[DigitalTop.scala:47:7]
wire [1:0] mem_axi4_0_r_bits_resp_0 = mem_axi4_0_r_bits_resp; // @[DigitalTop.scala:47:7]
wire mem_axi4_0_r_bits_last_0 = mem_axi4_0_r_bits_last; // @[DigitalTop.scala:47:7]
wire serial_tl_0_in_valid_0 = serial_tl_0_in_valid; // @[DigitalTop.scala:47:7]
wire [31:0] serial_tl_0_in_bits_phit_0 = serial_tl_0_in_bits_phit; // @[DigitalTop.scala:47:7]
wire serial_tl_0_out_ready_0 = serial_tl_0_out_ready; // @[DigitalTop.scala:47:7]
wire serial_tl_0_clock_in_0 = serial_tl_0_clock_in; // @[DigitalTop.scala:47:7]
wire uart_0_rxd_0 = uart_0_rxd; // @[DigitalTop.scala:47:7]
wire [10:0] debug_systemjtag_mfr_id = 11'h0; // @[DigitalTop.scala:47:7]
wire [15:0] debug_systemjtag_part_number = 16'h0; // @[DigitalTop.scala:47:7]
wire [3:0] debug_systemjtag_version = 4'h0; // @[DigitalTop.scala:47:7]
wire [3:0] nexus_1_auto_in_group_0_itype = 4'h0; // @[BundleBridgeNexus.scala:20:9]
wire [3:0] nexus_1_auto_in_priv = 4'h0; // @[BundleBridgeNexus.scala:20:9]
wire [3:0] nexus_1_auto_out_group_0_itype = 4'h0; // @[BundleBridgeNexus.scala:20:9]
wire [3:0] nexus_1_auto_out_priv = 4'h0; // @[BundleBridgeNexus.scala:20:9]
wire [3:0] nexus_1_nodeIn_group_0_itype = 4'h0; // @[MixedNode.scala:551:17]
wire [3:0] nexus_1_nodeIn_priv = 4'h0; // @[MixedNode.scala:551:17]
wire [3:0] nexus_1_nodeOut_group_0_itype = 4'h0; // @[MixedNode.scala:542:17]
wire [3:0] nexus_1_nodeOut_priv = 4'h0; // @[MixedNode.scala:542:17]
wire [3:0] traceCoreNodesIn_group_0_itype = 4'h0; // @[MixedNode.scala:551:17]
wire [3:0] traceCoreNodesIn_priv = 4'h0; // @[MixedNode.scala:551:17]
wire [31:0] broadcast_auto_in = 32'h10000; // @[BundleBridgeNexus.scala:20:9]
wire [31:0] broadcast_auto_out = 32'h10000; // @[BundleBridgeNexus.scala:20:9]
wire [31:0] broadcast_nodeIn = 32'h10000; // @[MixedNode.scala:551:17]
wire [31:0] broadcast_nodeOut = 32'h10000; // @[MixedNode.scala:542:17]
wire [31:0] bootROMResetVectorSourceNodeOut = 32'h10000; // @[MixedNode.scala:542:17]
wire [39:0] nexus_auto_in_insns_0_iaddr = 40'h0; // @[BundleBridgeNexus.scala:20:9]
wire [39:0] nexus_auto_in_insns_0_tval = 40'h0; // @[BundleBridgeNexus.scala:20:9]
wire [39:0] nexus_auto_out_insns_0_iaddr = 40'h0; // @[BundleBridgeNexus.scala:20:9]
wire [39:0] nexus_auto_out_insns_0_tval = 40'h0; // @[BundleBridgeNexus.scala:20:9]
wire [39:0] nexus_nodeIn_insns_0_iaddr = 40'h0; // @[MixedNode.scala:551:17]
wire [39:0] nexus_nodeIn_insns_0_tval = 40'h0; // @[MixedNode.scala:551:17]
wire [39:0] nexus_nodeOut_insns_0_iaddr = 40'h0; // @[MixedNode.scala:542:17]
wire [39:0] nexus_nodeOut_insns_0_tval = 40'h0; // @[MixedNode.scala:542:17]
wire [39:0] traceNodesIn_insns_0_iaddr = 40'h0; // @[MixedNode.scala:551:17]
wire [39:0] traceNodesIn_insns_0_tval = 40'h0; // @[MixedNode.scala:551:17]
wire [63:0] nexus_auto_in_insns_0_cause = 64'h0; // @[BundleBridgeNexus.scala:20:9]
wire [63:0] nexus_auto_out_insns_0_cause = 64'h0; // @[BundleBridgeNexus.scala:20:9]
wire [63:0] nexus_nodeIn_insns_0_cause = 64'h0; // @[MixedNode.scala:551:17]
wire [63:0] nexus_nodeOut_insns_0_cause = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] traceNodesIn_insns_0_cause = 64'h0; // @[MixedNode.scala:551:17]
wire [2:0] nexus_auto_in_insns_0_priv = 3'h0; // @[BundleBridgeNexus.scala:20:9]
wire [2:0] nexus_auto_out_insns_0_priv = 3'h0; // @[BundleBridgeNexus.scala:20:9]
wire [2:0] nexus_nodeIn_insns_0_priv = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] nexus_nodeOut_insns_0_priv = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] traceNodesIn_insns_0_priv = 3'h0; // @[MixedNode.scala:551:17]
wire [31:0] nexus_auto_in_insns_0_insn = 32'h0; // @[BundleBridgeNexus.scala:20:9]
wire [31:0] nexus_auto_out_insns_0_insn = 32'h0; // @[BundleBridgeNexus.scala:20:9]
wire [31:0] nexus_nodeIn_insns_0_insn = 32'h0; // @[MixedNode.scala:551:17]
wire [31:0] nexus_nodeOut_insns_0_insn = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] nexus_1_auto_in_group_0_iaddr = 32'h0; // @[BundleBridgeNexus.scala:20:9]
wire [31:0] nexus_1_auto_in_tval = 32'h0; // @[BundleBridgeNexus.scala:20:9]
wire [31:0] nexus_1_auto_in_cause = 32'h0; // @[BundleBridgeNexus.scala:20:9]
wire [31:0] nexus_1_auto_out_group_0_iaddr = 32'h0; // @[BundleBridgeNexus.scala:20:9]
wire [31:0] nexus_1_auto_out_tval = 32'h0; // @[BundleBridgeNexus.scala:20:9]
wire [31:0] nexus_1_auto_out_cause = 32'h0; // @[BundleBridgeNexus.scala:20:9]
wire [31:0] nexus_1_nodeIn_group_0_iaddr = 32'h0; // @[MixedNode.scala:551:17]
wire [31:0] nexus_1_nodeIn_tval = 32'h0; // @[MixedNode.scala:551:17]
wire [31:0] nexus_1_nodeIn_cause = 32'h0; // @[MixedNode.scala:551:17]
wire [31:0] nexus_1_nodeOut_group_0_iaddr = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] nexus_1_nodeOut_tval = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] nexus_1_nodeOut_cause = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] traceCoreNodesIn_group_0_iaddr = 32'h0; // @[MixedNode.scala:551:17]
wire [31:0] traceCoreNodesIn_tval = 32'h0; // @[MixedNode.scala:551:17]
wire [31:0] traceCoreNodesIn_cause = 32'h0; // @[MixedNode.scala:551:17]
wire [31:0] traceNodesIn_insns_0_insn = 32'h0; // @[MixedNode.scala:551:17]
wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire ibus__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire nexus_auto_in_insns_0_valid = 1'h0; // @[BundleBridgeNexus.scala:20:9]
wire nexus_auto_in_insns_0_exception = 1'h0; // @[BundleBridgeNexus.scala:20:9]
wire nexus_auto_in_insns_0_interrupt = 1'h0; // @[BundleBridgeNexus.scala:20:9]
wire nexus_auto_out_insns_0_valid = 1'h0; // @[BundleBridgeNexus.scala:20:9]
wire nexus_auto_out_insns_0_exception = 1'h0; // @[BundleBridgeNexus.scala:20:9]
wire nexus_auto_out_insns_0_interrupt = 1'h0; // @[BundleBridgeNexus.scala:20:9]
wire nexus_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire nexus_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire nexus__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire nexus_nodeIn_insns_0_valid = 1'h0; // @[MixedNode.scala:551:17]
wire nexus_nodeIn_insns_0_exception = 1'h0; // @[MixedNode.scala:551:17]
wire nexus_nodeIn_insns_0_interrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nexus_nodeOut_insns_0_valid = 1'h0; // @[MixedNode.scala:542:17]
wire nexus_nodeOut_insns_0_exception = 1'h0; // @[MixedNode.scala:542:17]
wire nexus_nodeOut_insns_0_interrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nexus_1_auto_in_group_0_iretire = 1'h0; // @[BundleBridgeNexus.scala:20:9]
wire nexus_1_auto_in_group_0_ilastsize = 1'h0; // @[BundleBridgeNexus.scala:20:9]
wire nexus_1_auto_out_group_0_iretire = 1'h0; // @[BundleBridgeNexus.scala:20:9]
wire nexus_1_auto_out_group_0_ilastsize = 1'h0; // @[BundleBridgeNexus.scala:20:9]
wire nexus_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire nexus_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire nexus_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire nexus_1_nodeIn_group_0_iretire = 1'h0; // @[MixedNode.scala:551:17]
wire nexus_1_nodeIn_group_0_ilastsize = 1'h0; // @[MixedNode.scala:551:17]
wire nexus_1_nodeOut_group_0_iretire = 1'h0; // @[MixedNode.scala:542:17]
wire nexus_1_nodeOut_group_0_ilastsize = 1'h0; // @[MixedNode.scala:542:17]
wire clockNamePrefixer_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire clockNamePrefixer_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire clockNamePrefixer__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire frequencySpecifier_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire frequencySpecifier_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire frequencySpecifier__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire clockTapNode_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire clockTapNode_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire clockTapNode__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire tileHaltSinkNodeIn_0 = 1'h0; // @[MixedNode.scala:551:17]
wire tileWFISinkNodeIn_0 = 1'h0; // @[MixedNode.scala:551:17]
wire tileCeaseSinkNodeIn_0 = 1'h0; // @[MixedNode.scala:551:17]
wire traceCoreNodesIn_group_0_iretire = 1'h0; // @[MixedNode.scala:551:17]
wire traceCoreNodesIn_group_0_ilastsize = 1'h0; // @[MixedNode.scala:551:17]
wire traceNodesIn_insns_0_valid = 1'h0; // @[MixedNode.scala:551:17]
wire traceNodesIn_insns_0_exception = 1'h0; // @[MixedNode.scala:551:17]
wire traceNodesIn_insns_0_interrupt = 1'h0; // @[MixedNode.scala:551:17]
wire memAXI4NodeIn_aw_ready = mem_axi4_0_aw_ready_0; // @[MixedNode.scala:551:17]
wire memAXI4NodeIn_aw_valid; // @[MixedNode.scala:551:17]
wire [3:0] memAXI4NodeIn_aw_bits_id; // @[MixedNode.scala:551:17]
wire [31:0] memAXI4NodeIn_aw_bits_addr; // @[MixedNode.scala:551:17]
wire [7:0] memAXI4NodeIn_aw_bits_len; // @[MixedNode.scala:551:17]
wire [2:0] memAXI4NodeIn_aw_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] memAXI4NodeIn_aw_bits_burst; // @[MixedNode.scala:551:17]
wire memAXI4NodeIn_aw_bits_lock; // @[MixedNode.scala:551:17]
wire [3:0] memAXI4NodeIn_aw_bits_cache; // @[MixedNode.scala:551:17]
wire [2:0] memAXI4NodeIn_aw_bits_prot; // @[MixedNode.scala:551:17]
wire [3:0] memAXI4NodeIn_aw_bits_qos; // @[MixedNode.scala:551:17]
wire memAXI4NodeIn_w_ready = mem_axi4_0_w_ready_0; // @[MixedNode.scala:551:17]
wire memAXI4NodeIn_w_valid; // @[MixedNode.scala:551:17]
wire [63:0] memAXI4NodeIn_w_bits_data; // @[MixedNode.scala:551:17]
wire [7:0] memAXI4NodeIn_w_bits_strb; // @[MixedNode.scala:551:17]
wire memAXI4NodeIn_w_bits_last; // @[MixedNode.scala:551:17]
wire memAXI4NodeIn_b_ready; // @[MixedNode.scala:551:17]
wire memAXI4NodeIn_b_valid = mem_axi4_0_b_valid_0; // @[MixedNode.scala:551:17]
wire [3:0] memAXI4NodeIn_b_bits_id = mem_axi4_0_b_bits_id_0; // @[MixedNode.scala:551:17]
wire [1:0] memAXI4NodeIn_b_bits_resp = mem_axi4_0_b_bits_resp_0; // @[MixedNode.scala:551:17]
wire memAXI4NodeIn_ar_ready = mem_axi4_0_ar_ready_0; // @[MixedNode.scala:551:17]
wire memAXI4NodeIn_ar_valid; // @[MixedNode.scala:551:17]
wire [3:0] memAXI4NodeIn_ar_bits_id; // @[MixedNode.scala:551:17]
wire [31:0] memAXI4NodeIn_ar_bits_addr; // @[MixedNode.scala:551:17]
wire [7:0] memAXI4NodeIn_ar_bits_len; // @[MixedNode.scala:551:17]
wire [2:0] memAXI4NodeIn_ar_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] memAXI4NodeIn_ar_bits_burst; // @[MixedNode.scala:551:17]
wire memAXI4NodeIn_ar_bits_lock; // @[MixedNode.scala:551:17]
wire [3:0] memAXI4NodeIn_ar_bits_cache; // @[MixedNode.scala:551:17]
wire [2:0] memAXI4NodeIn_ar_bits_prot; // @[MixedNode.scala:551:17]
wire [3:0] memAXI4NodeIn_ar_bits_qos; // @[MixedNode.scala:551:17]
wire memAXI4NodeIn_r_ready; // @[MixedNode.scala:551:17]
wire memAXI4NodeIn_r_valid = mem_axi4_0_r_valid_0; // @[MixedNode.scala:551:17]
wire [3:0] memAXI4NodeIn_r_bits_id = mem_axi4_0_r_bits_id_0; // @[MixedNode.scala:551:17]
wire [63:0] memAXI4NodeIn_r_bits_data = mem_axi4_0_r_bits_data_0; // @[MixedNode.scala:551:17]
wire [1:0] memAXI4NodeIn_r_bits_resp = mem_axi4_0_r_bits_resp_0; // @[MixedNode.scala:551:17]
wire memAXI4NodeIn_r_bits_last = mem_axi4_0_r_bits_last_0; // @[MixedNode.scala:551:17]
wire ioNodeIn_txd; // @[MixedNode.scala:551:17]
wire ioNodeIn_rxd = uart_0_rxd_0; // @[MixedNode.scala:551:17]
wire auto_mbus_fixedClockNode_anon_out_clock_0; // @[DigitalTop.scala:47:7]
wire auto_mbus_fixedClockNode_anon_out_reset_0; // @[DigitalTop.scala:47:7]
wire auto_cbus_fixedClockNode_anon_out_clock_0; // @[DigitalTop.scala:47:7]
wire auto_cbus_fixedClockNode_anon_out_reset_0; // @[DigitalTop.scala:47:7]
wire debug_systemjtag_jtag_TDO_data_0; // @[DigitalTop.scala:47:7]
wire debug_systemjtag_jtag_TDO_driven; // @[DigitalTop.scala:47:7]
wire debug_ndreset; // @[DigitalTop.scala:47:7]
wire debug_dmactive_0; // @[DigitalTop.scala:47:7]
wire [3:0] mem_axi4_0_aw_bits_id_0; // @[DigitalTop.scala:47:7]
wire [31:0] mem_axi4_0_aw_bits_addr_0; // @[DigitalTop.scala:47:7]
wire [7:0] mem_axi4_0_aw_bits_len_0; // @[DigitalTop.scala:47:7]
wire [2:0] mem_axi4_0_aw_bits_size_0; // @[DigitalTop.scala:47:7]
wire [1:0] mem_axi4_0_aw_bits_burst_0; // @[DigitalTop.scala:47:7]
wire mem_axi4_0_aw_bits_lock_0; // @[DigitalTop.scala:47:7]
wire [3:0] mem_axi4_0_aw_bits_cache_0; // @[DigitalTop.scala:47:7]
wire [2:0] mem_axi4_0_aw_bits_prot_0; // @[DigitalTop.scala:47:7]
wire [3:0] mem_axi4_0_aw_bits_qos_0; // @[DigitalTop.scala:47:7]
wire mem_axi4_0_aw_valid_0; // @[DigitalTop.scala:47:7]
wire [63:0] mem_axi4_0_w_bits_data_0; // @[DigitalTop.scala:47:7]
wire [7:0] mem_axi4_0_w_bits_strb_0; // @[DigitalTop.scala:47:7]
wire mem_axi4_0_w_bits_last_0; // @[DigitalTop.scala:47:7]
wire mem_axi4_0_w_valid_0; // @[DigitalTop.scala:47:7]
wire mem_axi4_0_b_ready_0; // @[DigitalTop.scala:47:7]
wire [3:0] mem_axi4_0_ar_bits_id_0; // @[DigitalTop.scala:47:7]
wire [31:0] mem_axi4_0_ar_bits_addr_0; // @[DigitalTop.scala:47:7]
wire [7:0] mem_axi4_0_ar_bits_len_0; // @[DigitalTop.scala:47:7]
wire [2:0] mem_axi4_0_ar_bits_size_0; // @[DigitalTop.scala:47:7]
wire [1:0] mem_axi4_0_ar_bits_burst_0; // @[DigitalTop.scala:47:7]
wire mem_axi4_0_ar_bits_lock_0; // @[DigitalTop.scala:47:7]
wire [3:0] mem_axi4_0_ar_bits_cache_0; // @[DigitalTop.scala:47:7]
wire [2:0] mem_axi4_0_ar_bits_prot_0; // @[DigitalTop.scala:47:7]
wire [3:0] mem_axi4_0_ar_bits_qos_0; // @[DigitalTop.scala:47:7]
wire mem_axi4_0_ar_valid_0; // @[DigitalTop.scala:47:7]
wire mem_axi4_0_r_ready_0; // @[DigitalTop.scala:47:7]
wire serial_tl_0_in_ready_0; // @[DigitalTop.scala:47:7]
wire [31:0] serial_tl_0_out_bits_phit_0; // @[DigitalTop.scala:47:7]
wire serial_tl_0_out_valid_0; // @[DigitalTop.scala:47:7]
wire uart_0_txd_0; // @[DigitalTop.scala:47:7]
wire clockTapIn_clock; // @[MixedNode.scala:551:17]
wire ibus_clockNodeIn_clock = ibus_auto_clock_in_clock; // @[ClockDomain.scala:14:9]
wire ibus_auto_int_bus_anon_in_0; // @[ClockDomain.scala:14:9]
wire ibus_clockNodeIn_reset = ibus_auto_clock_in_reset; // @[ClockDomain.scala:14:9]
wire ibus_auto_int_bus_anon_out_0; // @[ClockDomain.scala:14:9]
wire ibus_childClock; // @[LazyModuleImp.scala:155:31]
wire ibus_childReset; // @[LazyModuleImp.scala:158:31]
assign ibus_childClock = ibus_clockNodeIn_clock; // @[MixedNode.scala:551:17]
assign ibus_childReset = ibus_clockNodeIn_reset; // @[MixedNode.scala:551:17]
wire [63:0] nexus_nodeIn_time = nexus_auto_in_time; // @[MixedNode.scala:551:17]
wire nexus_nodeIn_custom_rob_empty = nexus_auto_in_custom_rob_empty; // @[MixedNode.scala:551:17]
wire [63:0] nexus_nodeOut_time; // @[MixedNode.scala:542:17]
wire nexus_nodeOut_custom_rob_empty; // @[MixedNode.scala:542:17]
wire [63:0] traceNodesIn_time = nexus_auto_out_time; // @[MixedNode.scala:551:17]
wire traceNodesIn_custom_rob_empty = nexus_auto_out_custom_rob_empty; // @[MixedNode.scala:551:17]
assign nexus_nodeOut_time = nexus_nodeIn_time; // @[MixedNode.scala:542:17, :551:17]
assign nexus_nodeOut_custom_rob_empty = nexus_nodeIn_custom_rob_empty; // @[MixedNode.scala:542:17, :551:17]
assign nexus_auto_out_time = nexus_nodeOut_time; // @[MixedNode.scala:542:17]
assign nexus_auto_out_custom_rob_empty = nexus_nodeOut_custom_rob_empty; // @[MixedNode.scala:542:17]
wire clockNamePrefixer_clockNamePrefixerIn_5_member_clockTapNode_clockTapNode_clock_tap_clock = clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_clock; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerIn_5_member_clockTapNode_clockTapNode_clock_tap_reset = clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_reset; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerIn_4_member_cbus_cbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_clock; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerIn_4_member_cbus_cbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_reset; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerIn_3_member_mbus_mbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_clock; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerIn_3_member_mbus_mbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_reset; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerIn_2_member_fbus_fbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_clock; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerIn_2_member_fbus_fbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_reset; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerIn_1_member_pbus_pbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_clock; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerIn_1_member_pbus_pbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_reset; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_1_clock = clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_clock; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_1_reset = clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_reset; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_clock; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_reset; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17]
wire clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeIn_4_member_clockTapNode_clock_tap_clock = clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_clock; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeIn_4_member_clockTapNode_clock_tap_reset = clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_reset; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeIn_3_member_cbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_clock; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_clock; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeIn_3_member_cbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_reset; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_reset; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeIn_2_member_mbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_clock; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_clock; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeIn_2_member_mbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_reset; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_reset; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeIn_1_member_fbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_clock; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_clock; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeIn_1_member_fbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_reset; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_reset; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeIn_member_pbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_clock; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_clock; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeIn_member_pbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_reset; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_reset; // @[MixedNode.scala:542:17]
wire allClockGroupsNodeIn_member_sbus_1_clock = clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_clock; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_clock; // @[MixedNode.scala:542:17]
wire allClockGroupsNodeIn_member_sbus_1_reset = clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_reset; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_reset; // @[MixedNode.scala:542:17]
wire allClockGroupsNodeIn_member_sbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_clock; // @[MixedNode.scala:551:17]
wire allClockGroupsNodeIn_member_sbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_reset; // @[MixedNode.scala:551:17]
assign clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_clock = clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_1_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_reset = clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_1_reset; // @[MixedNode.scala:542:17, :551:17]
assign clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_1_member_pbus_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_1_member_pbus_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_2_member_fbus_fbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_2_member_fbus_fbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_3_member_mbus_mbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_3_member_mbus_mbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_4_member_cbus_cbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_4_member_cbus_cbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_clock = clockNamePrefixer_clockNamePrefixerIn_5_member_clockTapNode_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_reset = clockNamePrefixer_clockNamePrefixerIn_5_member_clockTapNode_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17, :551:17]
assign clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_clock = clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_clock; // @[MixedNode.scala:542:17]
assign clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_reset = clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_reset; // @[MixedNode.scala:542:17]
assign clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_clock = clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_clock; // @[MixedNode.scala:542:17]
assign clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_reset = clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_reset; // @[MixedNode.scala:542:17]
assign clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_clock = clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_clock; // @[MixedNode.scala:542:17]
assign clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_reset = clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_reset; // @[MixedNode.scala:542:17]
assign clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_clock = clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_clock; // @[MixedNode.scala:542:17]
assign clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_reset = clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_reset; // @[MixedNode.scala:542:17]
assign clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_clock = clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_clock; // @[MixedNode.scala:542:17]
assign clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_reset = clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_reset; // @[MixedNode.scala:542:17]
assign clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_clock = clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_clock; // @[MixedNode.scala:542:17]
assign clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_reset = clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_reset; // @[MixedNode.scala:542:17]
assign clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_clock = clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17]
assign clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_reset = clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17]
wire frequencySpecifier_frequencySpecifierIn_member_allClocks_clockTapNode_clock_tap_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_clock; // @[MixedNode.scala:551:17]
wire frequencySpecifier_frequencySpecifierIn_member_allClocks_clockTapNode_clock_tap_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_reset; // @[MixedNode.scala:551:17]
wire frequencySpecifier_frequencySpecifierIn_member_allClocks_cbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_clock; // @[MixedNode.scala:551:17]
wire frequencySpecifier_frequencySpecifierIn_member_allClocks_cbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_reset; // @[MixedNode.scala:551:17]
wire frequencySpecifier_frequencySpecifierIn_member_allClocks_mbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_clock; // @[MixedNode.scala:551:17]
wire frequencySpecifier_frequencySpecifierIn_member_allClocks_mbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_reset; // @[MixedNode.scala:551:17]
wire frequencySpecifier_frequencySpecifierIn_member_allClocks_fbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_clock; // @[MixedNode.scala:551:17]
wire frequencySpecifier_frequencySpecifierIn_member_allClocks_fbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_reset; // @[MixedNode.scala:551:17]
wire frequencySpecifier_frequencySpecifierIn_member_allClocks_pbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_clock; // @[MixedNode.scala:551:17]
wire frequencySpecifier_frequencySpecifierIn_member_allClocks_pbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_reset; // @[MixedNode.scala:551:17]
wire frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_1_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_clock; // @[MixedNode.scala:551:17]
wire frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_1_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_reset; // @[MixedNode.scala:551:17]
wire frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_clock; // @[MixedNode.scala:551:17]
wire frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_reset; // @[MixedNode.scala:551:17]
wire frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17]
wire frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17]
wire frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_clock; // @[MixedNode.scala:542:17]
wire frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_reset; // @[MixedNode.scala:542:17]
wire frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_clock; // @[MixedNode.scala:542:17]
wire frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_reset; // @[MixedNode.scala:542:17]
wire frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_clock; // @[MixedNode.scala:542:17]
wire frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_reset; // @[MixedNode.scala:542:17]
wire frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_clock; // @[MixedNode.scala:542:17]
wire frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_reset; // @[MixedNode.scala:542:17]
wire frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_clock; // @[MixedNode.scala:542:17]
wire frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_reset; // @[MixedNode.scala:542:17]
wire frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_clock; // @[MixedNode.scala:542:17]
wire frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_reset; // @[MixedNode.scala:542:17]
wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
assign frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17, :551:17]
assign frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17, :551:17]
assign frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_cbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_cbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_mbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_mbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_fbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_fbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_1_clock; // @[MixedNode.scala:542:17, :551:17]
assign frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_1_reset; // @[MixedNode.scala:542:17, :551:17]
assign frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17]
assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17]
assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_clock; // @[MixedNode.scala:542:17]
assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_reset; // @[MixedNode.scala:542:17]
assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_clock; // @[MixedNode.scala:542:17]
assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_reset; // @[MixedNode.scala:542:17]
assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_clock; // @[MixedNode.scala:542:17]
assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_reset; // @[MixedNode.scala:542:17]
assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_clock; // @[MixedNode.scala:542:17]
assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_reset; // @[MixedNode.scala:542:17]
assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_clock; // @[MixedNode.scala:542:17]
assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_reset; // @[MixedNode.scala:542:17]
assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_clock; // @[MixedNode.scala:542:17]
assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_reset; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17]
wire clockTapNode_nodeIn_member_clockTapNode_clock_tap_clock = clockTapNode_auto_in_member_clockTapNode_clock_tap_clock; // @[ClockGroup.scala:24:9]
wire x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17]
wire clockTapNode_nodeOut_clock; // @[MixedNode.scala:542:17]
wire clockTapNode_nodeIn_member_clockTapNode_clock_tap_reset = clockTapNode_auto_in_member_clockTapNode_clock_tap_reset; // @[ClockGroup.scala:24:9]
wire clockTapNode_nodeOut_reset; // @[MixedNode.scala:542:17]
assign clockTapIn_clock = clockTapNode_auto_out_clock; // @[ClockGroup.scala:24:9]
wire clockTapIn_reset = clockTapNode_auto_out_reset; // @[ClockGroup.scala:24:9]
assign clockTapNode_auto_out_clock = clockTapNode_nodeOut_clock; // @[ClockGroup.scala:24:9]
assign clockTapNode_auto_out_reset = clockTapNode_nodeOut_reset; // @[ClockGroup.scala:24:9]
assign clockTapNode_nodeOut_clock = clockTapNode_nodeIn_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockTapNode_nodeOut_reset = clockTapNode_nodeIn_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17, :551:17]
wire allClockGroupsNodeOut_member_sbus_1_clock; // @[MixedNode.scala:542:17]
wire allClockGroupsNodeOut_member_sbus_1_reset; // @[MixedNode.scala:542:17]
wire allClockGroupsNodeOut_member_sbus_0_clock; // @[MixedNode.scala:542:17]
wire allClockGroupsNodeOut_member_sbus_0_reset; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeOut_member_pbus_0_clock; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeOut_member_pbus_0_reset; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeOut_1_member_fbus_0_clock; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeOut_1_member_fbus_0_reset; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeOut_2_member_mbus_0_clock; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeOut_2_member_mbus_0_reset; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeOut_3_member_cbus_0_clock; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeOut_3_member_cbus_0_reset; // @[MixedNode.scala:542:17]
assign clockTapNode_auto_in_member_clockTapNode_clock_tap_clock = x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_clock; // @[ClockGroup.scala:24:9]
assign clockTapNode_auto_in_member_clockTapNode_clock_tap_reset = x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_reset; // @[ClockGroup.scala:24:9]
assign allClockGroupsNodeOut_member_sbus_1_clock = allClockGroupsNodeIn_member_sbus_1_clock; // @[MixedNode.scala:542:17, :551:17]
assign allClockGroupsNodeOut_member_sbus_1_reset = allClockGroupsNodeIn_member_sbus_1_reset; // @[MixedNode.scala:542:17, :551:17]
assign allClockGroupsNodeOut_member_sbus_0_clock = allClockGroupsNodeIn_member_sbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign allClockGroupsNodeOut_member_sbus_0_reset = allClockGroupsNodeIn_member_sbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign x1_allClockGroupsNodeOut_member_pbus_0_clock = x1_allClockGroupsNodeIn_member_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign x1_allClockGroupsNodeOut_member_pbus_0_reset = x1_allClockGroupsNodeIn_member_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign x1_allClockGroupsNodeOut_1_member_fbus_0_clock = x1_allClockGroupsNodeIn_1_member_fbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign x1_allClockGroupsNodeOut_1_member_fbus_0_reset = x1_allClockGroupsNodeIn_1_member_fbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign x1_allClockGroupsNodeOut_2_member_mbus_0_clock = x1_allClockGroupsNodeIn_2_member_mbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign x1_allClockGroupsNodeOut_2_member_mbus_0_reset = x1_allClockGroupsNodeIn_2_member_mbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign x1_allClockGroupsNodeOut_3_member_cbus_0_clock = x1_allClockGroupsNodeIn_3_member_cbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign x1_allClockGroupsNodeOut_3_member_cbus_0_reset = x1_allClockGroupsNodeIn_3_member_cbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_clock = x1_allClockGroupsNodeIn_4_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17, :551:17]
assign x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_reset = x1_allClockGroupsNodeIn_4_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17, :551:17]
wire domainIn_clock; // @[MixedNode.scala:551:17]
wire domainIn_reset; // @[MixedNode.scala:551:17]
wire debugNodesIn_sync_0; // @[MixedNode.scala:551:17]
wire debugNodesOut_sync_0; // @[MixedNode.scala:542:17]
assign debugNodesOut_sync_0 = debugNodesIn_sync_0; // @[MixedNode.scala:542:17, :551:17]
assign mem_axi4_0_aw_valid_0 = memAXI4NodeIn_aw_valid; // @[MixedNode.scala:551:17]
assign mem_axi4_0_aw_bits_id_0 = memAXI4NodeIn_aw_bits_id; // @[MixedNode.scala:551:17]
assign mem_axi4_0_aw_bits_addr_0 = memAXI4NodeIn_aw_bits_addr; // @[MixedNode.scala:551:17]
assign mem_axi4_0_aw_bits_len_0 = memAXI4NodeIn_aw_bits_len; // @[MixedNode.scala:551:17]
assign mem_axi4_0_aw_bits_size_0 = memAXI4NodeIn_aw_bits_size; // @[MixedNode.scala:551:17]
assign mem_axi4_0_aw_bits_burst_0 = memAXI4NodeIn_aw_bits_burst; // @[MixedNode.scala:551:17]
assign mem_axi4_0_aw_bits_lock_0 = memAXI4NodeIn_aw_bits_lock; // @[MixedNode.scala:551:17]
assign mem_axi4_0_aw_bits_cache_0 = memAXI4NodeIn_aw_bits_cache; // @[MixedNode.scala:551:17]
assign mem_axi4_0_aw_bits_prot_0 = memAXI4NodeIn_aw_bits_prot; // @[MixedNode.scala:551:17]
assign mem_axi4_0_aw_bits_qos_0 = memAXI4NodeIn_aw_bits_qos; // @[MixedNode.scala:551:17]
assign mem_axi4_0_w_valid_0 = memAXI4NodeIn_w_valid; // @[MixedNode.scala:551:17]
assign mem_axi4_0_w_bits_data_0 = memAXI4NodeIn_w_bits_data; // @[MixedNode.scala:551:17]
assign mem_axi4_0_w_bits_strb_0 = memAXI4NodeIn_w_bits_strb; // @[MixedNode.scala:551:17]
assign mem_axi4_0_w_bits_last_0 = memAXI4NodeIn_w_bits_last; // @[MixedNode.scala:551:17]
assign mem_axi4_0_b_ready_0 = memAXI4NodeIn_b_ready; // @[MixedNode.scala:551:17]
assign mem_axi4_0_ar_valid_0 = memAXI4NodeIn_ar_valid; // @[MixedNode.scala:551:17]
assign mem_axi4_0_ar_bits_id_0 = memAXI4NodeIn_ar_bits_id; // @[MixedNode.scala:551:17]
assign mem_axi4_0_ar_bits_addr_0 = memAXI4NodeIn_ar_bits_addr; // @[MixedNode.scala:551:17]
assign mem_axi4_0_ar_bits_len_0 = memAXI4NodeIn_ar_bits_len; // @[MixedNode.scala:551:17]
assign mem_axi4_0_ar_bits_size_0 = memAXI4NodeIn_ar_bits_size; // @[MixedNode.scala:551:17]
assign mem_axi4_0_ar_bits_burst_0 = memAXI4NodeIn_ar_bits_burst; // @[MixedNode.scala:551:17]
assign mem_axi4_0_ar_bits_lock_0 = memAXI4NodeIn_ar_bits_lock; // @[MixedNode.scala:551:17]
assign mem_axi4_0_ar_bits_cache_0 = memAXI4NodeIn_ar_bits_cache; // @[MixedNode.scala:551:17]
assign mem_axi4_0_ar_bits_prot_0 = memAXI4NodeIn_ar_bits_prot; // @[MixedNode.scala:551:17]
assign mem_axi4_0_ar_bits_qos_0 = memAXI4NodeIn_ar_bits_qos; // @[MixedNode.scala:551:17]
assign mem_axi4_0_r_ready_0 = memAXI4NodeIn_r_ready; // @[MixedNode.scala:551:17]
wire intXingIn_sync_0; // @[MixedNode.scala:551:17]
wire intXingOut_sync_0; // @[MixedNode.scala:542:17]
assign intXingOut_sync_0 = intXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17]
assign uart_0_txd_0 = ioNodeIn_txd; // @[MixedNode.scala:551:17]
reg [9:0] int_rtc_tick_c_value; // @[Counter.scala:61:40]
wire int_rtc_tick_wrap_wrap; // @[Counter.scala:73:24]
wire int_rtc_tick; // @[Counter.scala:117:24]
assign int_rtc_tick_wrap_wrap = int_rtc_tick_c_value == 10'h3E7; // @[Counter.scala:61:40, :73:24]
assign int_rtc_tick = int_rtc_tick_wrap_wrap; // @[Counter.scala:73:24, :117:24]
wire [10:0] _int_rtc_tick_wrap_value_T = {1'h0, int_rtc_tick_c_value} + 11'h1; // @[Counter.scala:61:40, :77:24]
wire [9:0] _int_rtc_tick_wrap_value_T_1 = _int_rtc_tick_wrap_value_T[9:0]; // @[Counter.scala:77:24]
always @(posedge _clint_domain_clock) begin // @[BusWrapper.scala:89:28]
if (_clint_domain_reset) // @[BusWrapper.scala:89:28]
int_rtc_tick_c_value <= 10'h0; // @[Counter.scala:61:40]
else // @[BusWrapper.scala:89:28]
int_rtc_tick_c_value <= int_rtc_tick_wrap_wrap ? 10'h0 : _int_rtc_tick_wrap_value_T_1; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}]
always @(posedge)
IntXbar_i1_o1 ibus_int_bus ( // @[InterruptBus.scala:19:27]
.auto_anon_in_0 (ibus_auto_int_bus_anon_in_0), // @[ClockDomain.scala:14:9]
.auto_anon_out_0 (ibus_auto_int_bus_anon_out_0)
); // @[InterruptBus.scala:19:27]
SystemBus sbus ( // @[SystemBus.scala:31:26]
.auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_ready (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_ready),
.auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_a_valid), // @[HasTiles.scala:163:38]
.auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_opcode), // @[HasTiles.scala:163:38]
.auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_param), // @[HasTiles.scala:163:38]
.auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_size), // @[HasTiles.scala:163:38]
.auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_source), // @[HasTiles.scala:163:38]
.auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_address), // @[HasTiles.scala:163:38]
.auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_mask), // @[HasTiles.scala:163:38]
.auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_data), // @[HasTiles.scala:163:38]
.auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_corrupt), // @[HasTiles.scala:163:38]
.auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_b_ready), // @[HasTiles.scala:163:38]
.auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_valid (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_valid),
.auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_bits_param (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_bits_param),
.auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_bits_address (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_bits_address),
.auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_ready (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_ready),
.auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_c_valid), // @[HasTiles.scala:163:38]
.auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_opcode), // @[HasTiles.scala:163:38]
.auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_param), // @[HasTiles.scala:163:38]
.auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_size), // @[HasTiles.scala:163:38]
.auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_source), // @[HasTiles.scala:163:38]
.auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_address), // @[HasTiles.scala:163:38]
.auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_data), // @[HasTiles.scala:163:38]
.auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_corrupt), // @[HasTiles.scala:163:38]
.auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_d_ready), // @[HasTiles.scala:163:38]
.auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_valid (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_valid),
.auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_opcode (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_opcode),
.auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_param (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_param),
.auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_size (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_size),
.auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_source (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_source),
.auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_sink (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_sink),
.auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_denied (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_denied),
.auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_data (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_data),
.auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_corrupt (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_corrupt),
.auto_coupler_from_boom_tile_tl_master_clock_xing_in_e_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_e_valid), // @[HasTiles.scala:163:38]
.auto_coupler_from_boom_tile_tl_master_clock_xing_in_e_bits_sink (_tile_prci_domain_auto_tl_master_clock_xing_out_e_bits_sink), // @[HasTiles.scala:163:38]
.auto_coupler_to_bus_named_coh_widget_anon_out_a_ready (_coh_wrapper_auto_coherent_jbar_anon_in_a_ready), // @[BankedCoherenceParams.scala:56:31]
.auto_coupler_to_bus_named_coh_widget_anon_out_a_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_valid),
.auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode),
.auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param),
.auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size),
.auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source),
.auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address),
.auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask),
.auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data),
.auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt),
.auto_coupler_to_bus_named_coh_widget_anon_out_b_ready (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_b_ready),
.auto_coupler_to_bus_named_coh_widget_anon_out_b_valid (_coh_wrapper_auto_coherent_jbar_anon_in_b_valid), // @[BankedCoherenceParams.scala:56:31]
.auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_param (_coh_wrapper_auto_coherent_jbar_anon_in_b_bits_param), // @[BankedCoherenceParams.scala:56:31]
.auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_address (_coh_wrapper_auto_coherent_jbar_anon_in_b_bits_address), // @[BankedCoherenceParams.scala:56:31]
.auto_coupler_to_bus_named_coh_widget_anon_out_c_ready (_coh_wrapper_auto_coherent_jbar_anon_in_c_ready), // @[BankedCoherenceParams.scala:56:31]
.auto_coupler_to_bus_named_coh_widget_anon_out_c_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_valid),
.auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode),
.auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param),
.auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size),
.auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source),
.auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address),
.auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data),
.auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt),
.auto_coupler_to_bus_named_coh_widget_anon_out_d_ready (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_d_ready),
.auto_coupler_to_bus_named_coh_widget_anon_out_d_valid (_coh_wrapper_auto_coherent_jbar_anon_in_d_valid), // @[BankedCoherenceParams.scala:56:31]
.auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_opcode (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_opcode), // @[BankedCoherenceParams.scala:56:31]
.auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_param (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_param), // @[BankedCoherenceParams.scala:56:31]
.auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_size (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_size), // @[BankedCoherenceParams.scala:56:31]
.auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_source (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_source), // @[BankedCoherenceParams.scala:56:31]
.auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_sink (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_sink), // @[BankedCoherenceParams.scala:56:31]
.auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_denied (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_denied), // @[BankedCoherenceParams.scala:56:31]
.auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_data (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_data), // @[BankedCoherenceParams.scala:56:31]
.auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_corrupt (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_corrupt), // @[BankedCoherenceParams.scala:56:31]
.auto_coupler_to_bus_named_coh_widget_anon_out_e_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_valid),
.auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink),
.auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready),
.auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid (_fbus_auto_bus_xing_out_a_valid), // @[FrontBus.scala:23:26]
.auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode (_fbus_auto_bus_xing_out_a_bits_opcode), // @[FrontBus.scala:23:26]
.auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param (_fbus_auto_bus_xing_out_a_bits_param), // @[FrontBus.scala:23:26]
.auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size (_fbus_auto_bus_xing_out_a_bits_size), // @[FrontBus.scala:23:26]
.auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source (_fbus_auto_bus_xing_out_a_bits_source), // @[FrontBus.scala:23:26]
.auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address (_fbus_auto_bus_xing_out_a_bits_address), // @[FrontBus.scala:23:26]
.auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask (_fbus_auto_bus_xing_out_a_bits_mask), // @[FrontBus.scala:23:26]
.auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data (_fbus_auto_bus_xing_out_a_bits_data), // @[FrontBus.scala:23:26]
.auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt (_fbus_auto_bus_xing_out_a_bits_corrupt), // @[FrontBus.scala:23:26]
.auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready (_fbus_auto_bus_xing_out_d_ready), // @[FrontBus.scala:23:26]
.auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid),
.auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode),
.auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param),
.auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size),
.auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source),
.auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink),
.auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied),
.auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data),
.auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt),
.auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready (_cbus_auto_bus_xing_in_a_ready), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid),
.auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode),
.auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param),
.auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size),
.auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source),
.auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address),
.auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask),
.auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data),
.auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt),
.auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready),
.auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid (_cbus_auto_bus_xing_in_d_valid), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode (_cbus_auto_bus_xing_in_d_bits_opcode), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param (_cbus_auto_bus_xing_in_d_bits_param), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size (_cbus_auto_bus_xing_in_d_bits_size), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source (_cbus_auto_bus_xing_in_d_bits_source), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink (_cbus_auto_bus_xing_in_d_bits_sink), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied (_cbus_auto_bus_xing_in_d_bits_denied), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data (_cbus_auto_bus_xing_in_d_bits_data), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt (_cbus_auto_bus_xing_in_d_bits_corrupt), // @[PeripheryBus.scala:37:26]
.auto_fixedClockNode_anon_out_2_clock (_sbus_auto_fixedClockNode_anon_out_2_clock),
.auto_fixedClockNode_anon_out_2_reset (_sbus_auto_fixedClockNode_anon_out_2_reset),
.auto_fixedClockNode_anon_out_1_clock (_sbus_auto_fixedClockNode_anon_out_1_clock),
.auto_fixedClockNode_anon_out_1_reset (_sbus_auto_fixedClockNode_anon_out_1_reset),
.auto_fixedClockNode_anon_out_0_clock (ibus_auto_clock_in_clock),
.auto_fixedClockNode_anon_out_0_reset (ibus_auto_clock_in_reset),
.auto_sbus_clock_groups_in_member_sbus_1_clock (allClockGroupsNodeOut_member_sbus_1_clock), // @[MixedNode.scala:542:17]
.auto_sbus_clock_groups_in_member_sbus_1_reset (allClockGroupsNodeOut_member_sbus_1_reset), // @[MixedNode.scala:542:17]
.auto_sbus_clock_groups_in_member_sbus_0_clock (allClockGroupsNodeOut_member_sbus_0_clock), // @[MixedNode.scala:542:17]
.auto_sbus_clock_groups_in_member_sbus_0_reset (allClockGroupsNodeOut_member_sbus_0_reset), // @[MixedNode.scala:542:17]
.auto_sbus_clock_groups_out_member_coh_0_clock (_sbus_auto_sbus_clock_groups_out_member_coh_0_clock),
.auto_sbus_clock_groups_out_member_coh_0_reset (_sbus_auto_sbus_clock_groups_out_member_coh_0_reset)
); // @[SystemBus.scala:31:26]
PeripheryBus_pbus pbus ( // @[PeripheryBus.scala:37:26]
.auto_coupler_to_device_named_uart_0_control_xing_out_a_ready (_uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready), // @[UART.scala:270:44]
.auto_coupler_to_device_named_uart_0_control_xing_out_a_valid (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid),
.auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode),
.auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param),
.auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size),
.auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source),
.auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address),
.auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask),
.auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data),
.auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt),
.auto_coupler_to_device_named_uart_0_control_xing_out_d_ready (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready),
.auto_coupler_to_device_named_uart_0_control_xing_out_d_valid (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid), // @[UART.scala:270:44]
.auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode), // @[UART.scala:270:44]
.auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size), // @[UART.scala:270:44]
.auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source), // @[UART.scala:270:44]
.auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data), // @[UART.scala:270:44]
.auto_fixedClockNode_anon_out_clock (_pbus_auto_fixedClockNode_anon_out_clock),
.auto_fixedClockNode_anon_out_reset (_pbus_auto_fixedClockNode_anon_out_reset),
.auto_pbus_clock_groups_in_member_pbus_0_clock (x1_allClockGroupsNodeOut_member_pbus_0_clock), // @[MixedNode.scala:542:17]
.auto_pbus_clock_groups_in_member_pbus_0_reset (x1_allClockGroupsNodeOut_member_pbus_0_reset), // @[MixedNode.scala:542:17]
.auto_bus_xing_in_a_ready (_pbus_auto_bus_xing_in_a_ready),
.auto_bus_xing_in_a_valid (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid), // @[PeripheryBus.scala:37:26]
.auto_bus_xing_in_a_bits_opcode (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode), // @[PeripheryBus.scala:37:26]
.auto_bus_xing_in_a_bits_param (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param), // @[PeripheryBus.scala:37:26]
.auto_bus_xing_in_a_bits_size (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size), // @[PeripheryBus.scala:37:26]
.auto_bus_xing_in_a_bits_source (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source), // @[PeripheryBus.scala:37:26]
.auto_bus_xing_in_a_bits_address (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address), // @[PeripheryBus.scala:37:26]
.auto_bus_xing_in_a_bits_mask (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask), // @[PeripheryBus.scala:37:26]
.auto_bus_xing_in_a_bits_data (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data), // @[PeripheryBus.scala:37:26]
.auto_bus_xing_in_a_bits_corrupt (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26]
.auto_bus_xing_in_d_ready (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready), // @[PeripheryBus.scala:37:26]
.auto_bus_xing_in_d_valid (_pbus_auto_bus_xing_in_d_valid),
.auto_bus_xing_in_d_bits_opcode (_pbus_auto_bus_xing_in_d_bits_opcode),
.auto_bus_xing_in_d_bits_param (_pbus_auto_bus_xing_in_d_bits_param),
.auto_bus_xing_in_d_bits_size (_pbus_auto_bus_xing_in_d_bits_size),
.auto_bus_xing_in_d_bits_source (_pbus_auto_bus_xing_in_d_bits_source),
.auto_bus_xing_in_d_bits_sink (_pbus_auto_bus_xing_in_d_bits_sink),
.auto_bus_xing_in_d_bits_denied (_pbus_auto_bus_xing_in_d_bits_denied),
.auto_bus_xing_in_d_bits_data (_pbus_auto_bus_xing_in_d_bits_data),
.auto_bus_xing_in_d_bits_corrupt (_pbus_auto_bus_xing_in_d_bits_corrupt)
); // @[PeripheryBus.scala:37:26]
FrontBus fbus ( // @[FrontBus.scala:23:26]
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready),
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_valid (_serial_tl_domain_auto_serdesser_client_out_a_valid), // @[PeripheryTLSerial.scala:116:38]
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_opcode (_serial_tl_domain_auto_serdesser_client_out_a_bits_opcode), // @[PeripheryTLSerial.scala:116:38]
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_param (_serial_tl_domain_auto_serdesser_client_out_a_bits_param), // @[PeripheryTLSerial.scala:116:38]
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_size (_serial_tl_domain_auto_serdesser_client_out_a_bits_size), // @[PeripheryTLSerial.scala:116:38]
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_source (_serial_tl_domain_auto_serdesser_client_out_a_bits_source), // @[PeripheryTLSerial.scala:116:38]
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_address (_serial_tl_domain_auto_serdesser_client_out_a_bits_address), // @[PeripheryTLSerial.scala:116:38]
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_mask (_serial_tl_domain_auto_serdesser_client_out_a_bits_mask), // @[PeripheryTLSerial.scala:116:38]
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_data (_serial_tl_domain_auto_serdesser_client_out_a_bits_data), // @[PeripheryTLSerial.scala:116:38]
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_corrupt (_serial_tl_domain_auto_serdesser_client_out_a_bits_corrupt), // @[PeripheryTLSerial.scala:116:38]
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_ready (_serial_tl_domain_auto_serdesser_client_out_d_ready), // @[PeripheryTLSerial.scala:116:38]
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid),
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode),
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param),
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size),
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source),
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink),
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied),
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data),
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt),
.auto_coupler_from_debug_sb_widget_anon_in_a_ready (_fbus_auto_coupler_from_debug_sb_widget_anon_in_a_ready),
.auto_coupler_from_debug_sb_widget_anon_in_a_valid (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_valid), // @[Periphery.scala:88:26]
.auto_coupler_from_debug_sb_widget_anon_in_a_bits_opcode (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode), // @[Periphery.scala:88:26]
.auto_coupler_from_debug_sb_widget_anon_in_a_bits_size (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size), // @[Periphery.scala:88:26]
.auto_coupler_from_debug_sb_widget_anon_in_a_bits_address (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address), // @[Periphery.scala:88:26]
.auto_coupler_from_debug_sb_widget_anon_in_a_bits_data (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data), // @[Periphery.scala:88:26]
.auto_coupler_from_debug_sb_widget_anon_in_d_ready (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_d_ready), // @[Periphery.scala:88:26]
.auto_coupler_from_debug_sb_widget_anon_in_d_valid (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_valid),
.auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode),
.auto_coupler_from_debug_sb_widget_anon_in_d_bits_param (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_param),
.auto_coupler_from_debug_sb_widget_anon_in_d_bits_size (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_size),
.auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink),
.auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied),
.auto_coupler_from_debug_sb_widget_anon_in_d_bits_data (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_data),
.auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt),
.auto_fixedClockNode_anon_out_clock (_fbus_auto_fixedClockNode_anon_out_clock),
.auto_fixedClockNode_anon_out_reset (_fbus_auto_fixedClockNode_anon_out_reset),
.auto_fbus_clock_groups_in_member_fbus_0_clock (x1_allClockGroupsNodeOut_1_member_fbus_0_clock), // @[MixedNode.scala:542:17]
.auto_fbus_clock_groups_in_member_fbus_0_reset (x1_allClockGroupsNodeOut_1_member_fbus_0_reset), // @[MixedNode.scala:542:17]
.auto_bus_xing_out_a_ready (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready), // @[SystemBus.scala:31:26]
.auto_bus_xing_out_a_valid (_fbus_auto_bus_xing_out_a_valid),
.auto_bus_xing_out_a_bits_opcode (_fbus_auto_bus_xing_out_a_bits_opcode),
.auto_bus_xing_out_a_bits_param (_fbus_auto_bus_xing_out_a_bits_param),
.auto_bus_xing_out_a_bits_size (_fbus_auto_bus_xing_out_a_bits_size),
.auto_bus_xing_out_a_bits_source (_fbus_auto_bus_xing_out_a_bits_source),
.auto_bus_xing_out_a_bits_address (_fbus_auto_bus_xing_out_a_bits_address),
.auto_bus_xing_out_a_bits_mask (_fbus_auto_bus_xing_out_a_bits_mask),
.auto_bus_xing_out_a_bits_data (_fbus_auto_bus_xing_out_a_bits_data),
.auto_bus_xing_out_a_bits_corrupt (_fbus_auto_bus_xing_out_a_bits_corrupt),
.auto_bus_xing_out_d_ready (_fbus_auto_bus_xing_out_d_ready),
.auto_bus_xing_out_d_valid (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid), // @[SystemBus.scala:31:26]
.auto_bus_xing_out_d_bits_opcode (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode), // @[SystemBus.scala:31:26]
.auto_bus_xing_out_d_bits_param (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param), // @[SystemBus.scala:31:26]
.auto_bus_xing_out_d_bits_size (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size), // @[SystemBus.scala:31:26]
.auto_bus_xing_out_d_bits_source (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source), // @[SystemBus.scala:31:26]
.auto_bus_xing_out_d_bits_sink (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink), // @[SystemBus.scala:31:26]
.auto_bus_xing_out_d_bits_denied (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied), // @[SystemBus.scala:31:26]
.auto_bus_xing_out_d_bits_data (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data), // @[SystemBus.scala:31:26]
.auto_bus_xing_out_d_bits_corrupt (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt) // @[SystemBus.scala:31:26]
); // @[FrontBus.scala:23:26]
PeripheryBus_cbus cbus ( // @[PeripheryBus.scala:37:26]
.auto_coupler_to_prci_ctrl_fixer_anon_out_a_ready (_chipyard_prcictrl_domain_auto_xbar_anon_in_a_ready), // @[BusWrapper.scala:89:28]
.auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid),
.auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode),
.auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param),
.auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size),
.auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source),
.auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address),
.auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask),
.auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data),
.auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt),
.auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready),
.auto_coupler_to_prci_ctrl_fixer_anon_out_d_valid (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_valid), // @[BusWrapper.scala:89:28]
.auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_opcode (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_opcode), // @[BusWrapper.scala:89:28]
.auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_size (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_size), // @[BusWrapper.scala:89:28]
.auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_source (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_source), // @[BusWrapper.scala:89:28]
.auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_data (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_data), // @[BusWrapper.scala:89:28]
.auto_coupler_to_bootrom_fragmenter_anon_out_a_ready (_bootrom_domain_auto_bootrom_in_a_ready), // @[BusWrapper.scala:89:28]
.auto_coupler_to_bootrom_fragmenter_anon_out_a_valid (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_valid),
.auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode),
.auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param),
.auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size),
.auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source),
.auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address),
.auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask),
.auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data),
.auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt),
.auto_coupler_to_bootrom_fragmenter_anon_out_d_ready (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_d_ready),
.auto_coupler_to_bootrom_fragmenter_anon_out_d_valid (_bootrom_domain_auto_bootrom_in_d_valid), // @[BusWrapper.scala:89:28]
.auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_size (_bootrom_domain_auto_bootrom_in_d_bits_size), // @[BusWrapper.scala:89:28]
.auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_source (_bootrom_domain_auto_bootrom_in_d_bits_source), // @[BusWrapper.scala:89:28]
.auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_data (_bootrom_domain_auto_bootrom_in_d_bits_data), // @[BusWrapper.scala:89:28]
.auto_coupler_to_debug_fragmenter_anon_out_a_ready (_tlDM_auto_dmInner_dmInner_tl_in_a_ready), // @[Periphery.scala:88:26]
.auto_coupler_to_debug_fragmenter_anon_out_a_valid (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_valid),
.auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode),
.auto_coupler_to_debug_fragmenter_anon_out_a_bits_param (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_param),
.auto_coupler_to_debug_fragmenter_anon_out_a_bits_size (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_size),
.auto_coupler_to_debug_fragmenter_anon_out_a_bits_source (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_source),
.auto_coupler_to_debug_fragmenter_anon_out_a_bits_address (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_address),
.auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask),
.auto_coupler_to_debug_fragmenter_anon_out_a_bits_data (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_data),
.auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt),
.auto_coupler_to_debug_fragmenter_anon_out_d_ready (_cbus_auto_coupler_to_debug_fragmenter_anon_out_d_ready),
.auto_coupler_to_debug_fragmenter_anon_out_d_valid (_tlDM_auto_dmInner_dmInner_tl_in_d_valid), // @[Periphery.scala:88:26]
.auto_coupler_to_debug_fragmenter_anon_out_d_bits_opcode (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_opcode), // @[Periphery.scala:88:26]
.auto_coupler_to_debug_fragmenter_anon_out_d_bits_size (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_size), // @[Periphery.scala:88:26]
.auto_coupler_to_debug_fragmenter_anon_out_d_bits_source (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_source), // @[Periphery.scala:88:26]
.auto_coupler_to_debug_fragmenter_anon_out_d_bits_data (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_data), // @[Periphery.scala:88:26]
.auto_coupler_to_plic_fragmenter_anon_out_a_ready (_plic_domain_auto_plic_in_a_ready), // @[BusWrapper.scala:89:28]
.auto_coupler_to_plic_fragmenter_anon_out_a_valid (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_valid),
.auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode),
.auto_coupler_to_plic_fragmenter_anon_out_a_bits_param (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_param),
.auto_coupler_to_plic_fragmenter_anon_out_a_bits_size (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_size),
.auto_coupler_to_plic_fragmenter_anon_out_a_bits_source (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_source),
.auto_coupler_to_plic_fragmenter_anon_out_a_bits_address (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_address),
.auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask),
.auto_coupler_to_plic_fragmenter_anon_out_a_bits_data (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_data),
.auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt),
.auto_coupler_to_plic_fragmenter_anon_out_d_ready (_cbus_auto_coupler_to_plic_fragmenter_anon_out_d_ready),
.auto_coupler_to_plic_fragmenter_anon_out_d_valid (_plic_domain_auto_plic_in_d_valid), // @[BusWrapper.scala:89:28]
.auto_coupler_to_plic_fragmenter_anon_out_d_bits_opcode (_plic_domain_auto_plic_in_d_bits_opcode), // @[BusWrapper.scala:89:28]
.auto_coupler_to_plic_fragmenter_anon_out_d_bits_size (_plic_domain_auto_plic_in_d_bits_size), // @[BusWrapper.scala:89:28]
.auto_coupler_to_plic_fragmenter_anon_out_d_bits_source (_plic_domain_auto_plic_in_d_bits_source), // @[BusWrapper.scala:89:28]
.auto_coupler_to_plic_fragmenter_anon_out_d_bits_data (_plic_domain_auto_plic_in_d_bits_data), // @[BusWrapper.scala:89:28]
.auto_coupler_to_clint_fragmenter_anon_out_a_ready (_clint_domain_auto_clint_in_a_ready), // @[BusWrapper.scala:89:28]
.auto_coupler_to_clint_fragmenter_anon_out_a_valid (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_valid),
.auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode),
.auto_coupler_to_clint_fragmenter_anon_out_a_bits_param (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_param),
.auto_coupler_to_clint_fragmenter_anon_out_a_bits_size (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_size),
.auto_coupler_to_clint_fragmenter_anon_out_a_bits_source (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_source),
.auto_coupler_to_clint_fragmenter_anon_out_a_bits_address (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_address),
.auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask),
.auto_coupler_to_clint_fragmenter_anon_out_a_bits_data (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_data),
.auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt),
.auto_coupler_to_clint_fragmenter_anon_out_d_ready (_cbus_auto_coupler_to_clint_fragmenter_anon_out_d_ready),
.auto_coupler_to_clint_fragmenter_anon_out_d_valid (_clint_domain_auto_clint_in_d_valid), // @[BusWrapper.scala:89:28]
.auto_coupler_to_clint_fragmenter_anon_out_d_bits_opcode (_clint_domain_auto_clint_in_d_bits_opcode), // @[BusWrapper.scala:89:28]
.auto_coupler_to_clint_fragmenter_anon_out_d_bits_size (_clint_domain_auto_clint_in_d_bits_size), // @[BusWrapper.scala:89:28]
.auto_coupler_to_clint_fragmenter_anon_out_d_bits_source (_clint_domain_auto_clint_in_d_bits_source), // @[BusWrapper.scala:89:28]
.auto_coupler_to_clint_fragmenter_anon_out_d_bits_data (_clint_domain_auto_clint_in_d_bits_data), // @[BusWrapper.scala:89:28]
.auto_coupler_to_bus_named_pbus_bus_xing_out_a_ready (_pbus_auto_bus_xing_in_a_ready), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid),
.auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode),
.auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param),
.auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size),
.auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source),
.auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address),
.auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask),
.auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data),
.auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt),
.auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready),
.auto_coupler_to_bus_named_pbus_bus_xing_out_d_valid (_pbus_auto_bus_xing_in_d_valid), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_opcode (_pbus_auto_bus_xing_in_d_bits_opcode), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_param (_pbus_auto_bus_xing_in_d_bits_param), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_size (_pbus_auto_bus_xing_in_d_bits_size), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_source (_pbus_auto_bus_xing_in_d_bits_source), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_sink (_pbus_auto_bus_xing_in_d_bits_sink), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_denied (_pbus_auto_bus_xing_in_d_bits_denied), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_data (_pbus_auto_bus_xing_in_d_bits_data), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_corrupt (_pbus_auto_bus_xing_in_d_bits_corrupt), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_l2_ctrl_buffer_out_a_ready (_coh_wrapper_auto_l2_ctrls_ctrl_in_a_ready), // @[BankedCoherenceParams.scala:56:31]
.auto_coupler_to_l2_ctrl_buffer_out_a_valid (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_valid),
.auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode),
.auto_coupler_to_l2_ctrl_buffer_out_a_bits_param (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_param),
.auto_coupler_to_l2_ctrl_buffer_out_a_bits_size (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_size),
.auto_coupler_to_l2_ctrl_buffer_out_a_bits_source (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_source),
.auto_coupler_to_l2_ctrl_buffer_out_a_bits_address (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_address),
.auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask),
.auto_coupler_to_l2_ctrl_buffer_out_a_bits_data (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_data),
.auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt),
.auto_coupler_to_l2_ctrl_buffer_out_d_ready (_cbus_auto_coupler_to_l2_ctrl_buffer_out_d_ready),
.auto_coupler_to_l2_ctrl_buffer_out_d_valid (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_valid), // @[BankedCoherenceParams.scala:56:31]
.auto_coupler_to_l2_ctrl_buffer_out_d_bits_opcode (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_opcode), // @[BankedCoherenceParams.scala:56:31]
.auto_coupler_to_l2_ctrl_buffer_out_d_bits_size (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_size), // @[BankedCoherenceParams.scala:56:31]
.auto_coupler_to_l2_ctrl_buffer_out_d_bits_source (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_source), // @[BankedCoherenceParams.scala:56:31]
.auto_coupler_to_l2_ctrl_buffer_out_d_bits_data (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_data), // @[BankedCoherenceParams.scala:56:31]
.auto_fixedClockNode_anon_out_5_clock (auto_cbus_fixedClockNode_anon_out_clock_0),
.auto_fixedClockNode_anon_out_5_reset (auto_cbus_fixedClockNode_anon_out_reset_0),
.auto_fixedClockNode_anon_out_4_clock (_cbus_auto_fixedClockNode_anon_out_4_clock),
.auto_fixedClockNode_anon_out_4_reset (_cbus_auto_fixedClockNode_anon_out_4_reset),
.auto_fixedClockNode_anon_out_3_clock (_cbus_auto_fixedClockNode_anon_out_3_clock),
.auto_fixedClockNode_anon_out_3_reset (_cbus_auto_fixedClockNode_anon_out_3_reset),
.auto_fixedClockNode_anon_out_2_clock (domainIn_clock),
.auto_fixedClockNode_anon_out_2_reset (domainIn_reset),
.auto_fixedClockNode_anon_out_1_clock (_cbus_auto_fixedClockNode_anon_out_1_clock),
.auto_fixedClockNode_anon_out_1_reset (_cbus_auto_fixedClockNode_anon_out_1_reset),
.auto_fixedClockNode_anon_out_0_clock (_cbus_auto_fixedClockNode_anon_out_0_clock),
.auto_fixedClockNode_anon_out_0_reset (_cbus_auto_fixedClockNode_anon_out_0_reset),
.auto_cbus_clock_groups_in_member_cbus_0_clock (x1_allClockGroupsNodeOut_3_member_cbus_0_clock), // @[MixedNode.scala:542:17]
.auto_cbus_clock_groups_in_member_cbus_0_reset (x1_allClockGroupsNodeOut_3_member_cbus_0_reset), // @[MixedNode.scala:542:17]
.auto_bus_xing_in_a_ready (_cbus_auto_bus_xing_in_a_ready),
.auto_bus_xing_in_a_valid (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid), // @[SystemBus.scala:31:26]
.auto_bus_xing_in_a_bits_opcode (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode), // @[SystemBus.scala:31:26]
.auto_bus_xing_in_a_bits_param (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param), // @[SystemBus.scala:31:26]
.auto_bus_xing_in_a_bits_size (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size), // @[SystemBus.scala:31:26]
.auto_bus_xing_in_a_bits_source (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source), // @[SystemBus.scala:31:26]
.auto_bus_xing_in_a_bits_address (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address), // @[SystemBus.scala:31:26]
.auto_bus_xing_in_a_bits_mask (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask), // @[SystemBus.scala:31:26]
.auto_bus_xing_in_a_bits_data (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data), // @[SystemBus.scala:31:26]
.auto_bus_xing_in_a_bits_corrupt (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt), // @[SystemBus.scala:31:26]
.auto_bus_xing_in_d_ready (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready), // @[SystemBus.scala:31:26]
.auto_bus_xing_in_d_valid (_cbus_auto_bus_xing_in_d_valid),
.auto_bus_xing_in_d_bits_opcode (_cbus_auto_bus_xing_in_d_bits_opcode),
.auto_bus_xing_in_d_bits_param (_cbus_auto_bus_xing_in_d_bits_param),
.auto_bus_xing_in_d_bits_size (_cbus_auto_bus_xing_in_d_bits_size),
.auto_bus_xing_in_d_bits_source (_cbus_auto_bus_xing_in_d_bits_source),
.auto_bus_xing_in_d_bits_sink (_cbus_auto_bus_xing_in_d_bits_sink),
.auto_bus_xing_in_d_bits_denied (_cbus_auto_bus_xing_in_d_bits_denied),
.auto_bus_xing_in_d_bits_data (_cbus_auto_bus_xing_in_d_bits_data),
.auto_bus_xing_in_d_bits_corrupt (_cbus_auto_bus_xing_in_d_bits_corrupt),
.custom_boot (custom_boot)
); // @[PeripheryBus.scala:37:26]
MemoryBus mbus ( // @[MemoryBus.scala:30:26]
.auto_buffer_out_a_ready (_bank_auto_xbar_anon_in_a_ready), // @[Scratchpad.scala:65:28]
.auto_buffer_out_a_valid (_mbus_auto_buffer_out_a_valid),
.auto_buffer_out_a_bits_opcode (_mbus_auto_buffer_out_a_bits_opcode),
.auto_buffer_out_a_bits_param (_mbus_auto_buffer_out_a_bits_param),
.auto_buffer_out_a_bits_size (_mbus_auto_buffer_out_a_bits_size),
.auto_buffer_out_a_bits_source (_mbus_auto_buffer_out_a_bits_source),
.auto_buffer_out_a_bits_address (_mbus_auto_buffer_out_a_bits_address),
.auto_buffer_out_a_bits_mask (_mbus_auto_buffer_out_a_bits_mask),
.auto_buffer_out_a_bits_data (_mbus_auto_buffer_out_a_bits_data),
.auto_buffer_out_a_bits_corrupt (_mbus_auto_buffer_out_a_bits_corrupt),
.auto_buffer_out_d_ready (_mbus_auto_buffer_out_d_ready),
.auto_buffer_out_d_valid (_bank_auto_xbar_anon_in_d_valid), // @[Scratchpad.scala:65:28]
.auto_buffer_out_d_bits_opcode (_bank_auto_xbar_anon_in_d_bits_opcode), // @[Scratchpad.scala:65:28]
.auto_buffer_out_d_bits_param (_bank_auto_xbar_anon_in_d_bits_param), // @[Scratchpad.scala:65:28]
.auto_buffer_out_d_bits_size (_bank_auto_xbar_anon_in_d_bits_size), // @[Scratchpad.scala:65:28]
.auto_buffer_out_d_bits_source (_bank_auto_xbar_anon_in_d_bits_source), // @[Scratchpad.scala:65:28]
.auto_buffer_out_d_bits_sink (_bank_auto_xbar_anon_in_d_bits_sink), // @[Scratchpad.scala:65:28]
.auto_buffer_out_d_bits_denied (_bank_auto_xbar_anon_in_d_bits_denied), // @[Scratchpad.scala:65:28]
.auto_buffer_out_d_bits_data (_bank_auto_xbar_anon_in_d_bits_data), // @[Scratchpad.scala:65:28]
.auto_buffer_out_d_bits_corrupt (_bank_auto_xbar_anon_in_d_bits_corrupt), // @[Scratchpad.scala:65:28]
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_ready (memAXI4NodeIn_aw_ready), // @[MixedNode.scala:551:17]
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_valid (memAXI4NodeIn_aw_valid),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_id (memAXI4NodeIn_aw_bits_id),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_addr (memAXI4NodeIn_aw_bits_addr),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_len (memAXI4NodeIn_aw_bits_len),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_size (memAXI4NodeIn_aw_bits_size),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_burst (memAXI4NodeIn_aw_bits_burst),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_lock (memAXI4NodeIn_aw_bits_lock),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_cache (memAXI4NodeIn_aw_bits_cache),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_prot (memAXI4NodeIn_aw_bits_prot),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_qos (memAXI4NodeIn_aw_bits_qos),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_ready (memAXI4NodeIn_w_ready), // @[MixedNode.scala:551:17]
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_valid (memAXI4NodeIn_w_valid),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_data (memAXI4NodeIn_w_bits_data),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_strb (memAXI4NodeIn_w_bits_strb),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_last (memAXI4NodeIn_w_bits_last),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_ready (memAXI4NodeIn_b_ready),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_valid (memAXI4NodeIn_b_valid), // @[MixedNode.scala:551:17]
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_id (memAXI4NodeIn_b_bits_id), // @[MixedNode.scala:551:17]
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_resp (memAXI4NodeIn_b_bits_resp), // @[MixedNode.scala:551:17]
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_ready (memAXI4NodeIn_ar_ready), // @[MixedNode.scala:551:17]
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_valid (memAXI4NodeIn_ar_valid),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_id (memAXI4NodeIn_ar_bits_id),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_addr (memAXI4NodeIn_ar_bits_addr),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_len (memAXI4NodeIn_ar_bits_len),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_size (memAXI4NodeIn_ar_bits_size),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_burst (memAXI4NodeIn_ar_bits_burst),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_lock (memAXI4NodeIn_ar_bits_lock),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_cache (memAXI4NodeIn_ar_bits_cache),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_prot (memAXI4NodeIn_ar_bits_prot),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_qos (memAXI4NodeIn_ar_bits_qos),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_ready (memAXI4NodeIn_r_ready),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_valid (memAXI4NodeIn_r_valid), // @[MixedNode.scala:551:17]
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_id (memAXI4NodeIn_r_bits_id), // @[MixedNode.scala:551:17]
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_data (memAXI4NodeIn_r_bits_data), // @[MixedNode.scala:551:17]
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_resp (memAXI4NodeIn_r_bits_resp), // @[MixedNode.scala:551:17]
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_last (memAXI4NodeIn_r_bits_last), // @[MixedNode.scala:551:17]
.auto_fixedClockNode_anon_out_1_clock (auto_mbus_fixedClockNode_anon_out_clock_0),
.auto_fixedClockNode_anon_out_1_reset (auto_mbus_fixedClockNode_anon_out_reset_0),
.auto_fixedClockNode_anon_out_0_clock (_mbus_auto_fixedClockNode_anon_out_0_clock),
.auto_fixedClockNode_anon_out_0_reset (_mbus_auto_fixedClockNode_anon_out_0_reset),
.auto_mbus_clock_groups_in_member_mbus_0_clock (x1_allClockGroupsNodeOut_2_member_mbus_0_clock), // @[MixedNode.scala:542:17]
.auto_mbus_clock_groups_in_member_mbus_0_reset (x1_allClockGroupsNodeOut_2_member_mbus_0_reset), // @[MixedNode.scala:542:17]
.auto_bus_xing_in_a_ready (_mbus_auto_bus_xing_in_a_ready),
.auto_bus_xing_in_a_valid (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid), // @[BankedCoherenceParams.scala:56:31]
.auto_bus_xing_in_a_bits_opcode (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode), // @[BankedCoherenceParams.scala:56:31]
.auto_bus_xing_in_a_bits_param (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param), // @[BankedCoherenceParams.scala:56:31]
.auto_bus_xing_in_a_bits_size (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size), // @[BankedCoherenceParams.scala:56:31]
.auto_bus_xing_in_a_bits_source (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source), // @[BankedCoherenceParams.scala:56:31]
.auto_bus_xing_in_a_bits_address (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address), // @[BankedCoherenceParams.scala:56:31]
.auto_bus_xing_in_a_bits_mask (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask), // @[BankedCoherenceParams.scala:56:31]
.auto_bus_xing_in_a_bits_data (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data), // @[BankedCoherenceParams.scala:56:31]
.auto_bus_xing_in_a_bits_corrupt (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt), // @[BankedCoherenceParams.scala:56:31]
.auto_bus_xing_in_d_ready (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready), // @[BankedCoherenceParams.scala:56:31]
.auto_bus_xing_in_d_valid (_mbus_auto_bus_xing_in_d_valid),
.auto_bus_xing_in_d_bits_opcode (_mbus_auto_bus_xing_in_d_bits_opcode),
.auto_bus_xing_in_d_bits_param (_mbus_auto_bus_xing_in_d_bits_param),
.auto_bus_xing_in_d_bits_size (_mbus_auto_bus_xing_in_d_bits_size),
.auto_bus_xing_in_d_bits_source (_mbus_auto_bus_xing_in_d_bits_source),
.auto_bus_xing_in_d_bits_sink (_mbus_auto_bus_xing_in_d_bits_sink),
.auto_bus_xing_in_d_bits_denied (_mbus_auto_bus_xing_in_d_bits_denied),
.auto_bus_xing_in_d_bits_data (_mbus_auto_bus_xing_in_d_bits_data),
.auto_bus_xing_in_d_bits_corrupt (_mbus_auto_bus_xing_in_d_bits_corrupt)
); // @[MemoryBus.scala:30:26]
CoherenceManagerWrapper coh_wrapper ( // @[BankedCoherenceParams.scala:56:31]
.auto_coupler_to_bus_named_mbus_bus_xing_out_a_ready (_mbus_auto_bus_xing_in_a_ready), // @[MemoryBus.scala:30:26]
.auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid),
.auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode),
.auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param),
.auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size),
.auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source),
.auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address),
.auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask),
.auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data),
.auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt),
.auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready),
.auto_coupler_to_bus_named_mbus_bus_xing_out_d_valid (_mbus_auto_bus_xing_in_d_valid), // @[MemoryBus.scala:30:26]
.auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_opcode (_mbus_auto_bus_xing_in_d_bits_opcode), // @[MemoryBus.scala:30:26]
.auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_param (_mbus_auto_bus_xing_in_d_bits_param), // @[MemoryBus.scala:30:26]
.auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_size (_mbus_auto_bus_xing_in_d_bits_size), // @[MemoryBus.scala:30:26]
.auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_source (_mbus_auto_bus_xing_in_d_bits_source), // @[MemoryBus.scala:30:26]
.auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_sink (_mbus_auto_bus_xing_in_d_bits_sink), // @[MemoryBus.scala:30:26]
.auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_denied (_mbus_auto_bus_xing_in_d_bits_denied), // @[MemoryBus.scala:30:26]
.auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_data (_mbus_auto_bus_xing_in_d_bits_data), // @[MemoryBus.scala:30:26]
.auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_corrupt (_mbus_auto_bus_xing_in_d_bits_corrupt), // @[MemoryBus.scala:30:26]
.auto_coherent_jbar_anon_in_a_ready (_coh_wrapper_auto_coherent_jbar_anon_in_a_ready),
.auto_coherent_jbar_anon_in_a_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_valid), // @[SystemBus.scala:31:26]
.auto_coherent_jbar_anon_in_a_bits_opcode (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode), // @[SystemBus.scala:31:26]
.auto_coherent_jbar_anon_in_a_bits_param (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param), // @[SystemBus.scala:31:26]
.auto_coherent_jbar_anon_in_a_bits_size (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size), // @[SystemBus.scala:31:26]
.auto_coherent_jbar_anon_in_a_bits_source (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source), // @[SystemBus.scala:31:26]
.auto_coherent_jbar_anon_in_a_bits_address (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address), // @[SystemBus.scala:31:26]
.auto_coherent_jbar_anon_in_a_bits_mask (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask), // @[SystemBus.scala:31:26]
.auto_coherent_jbar_anon_in_a_bits_data (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data), // @[SystemBus.scala:31:26]
.auto_coherent_jbar_anon_in_a_bits_corrupt (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt), // @[SystemBus.scala:31:26]
.auto_coherent_jbar_anon_in_b_ready (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_b_ready), // @[SystemBus.scala:31:26]
.auto_coherent_jbar_anon_in_b_valid (_coh_wrapper_auto_coherent_jbar_anon_in_b_valid),
.auto_coherent_jbar_anon_in_b_bits_param (_coh_wrapper_auto_coherent_jbar_anon_in_b_bits_param),
.auto_coherent_jbar_anon_in_b_bits_address (_coh_wrapper_auto_coherent_jbar_anon_in_b_bits_address),
.auto_coherent_jbar_anon_in_c_ready (_coh_wrapper_auto_coherent_jbar_anon_in_c_ready),
.auto_coherent_jbar_anon_in_c_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_valid), // @[SystemBus.scala:31:26]
.auto_coherent_jbar_anon_in_c_bits_opcode (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode), // @[SystemBus.scala:31:26]
.auto_coherent_jbar_anon_in_c_bits_param (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param), // @[SystemBus.scala:31:26]
.auto_coherent_jbar_anon_in_c_bits_size (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size), // @[SystemBus.scala:31:26]
.auto_coherent_jbar_anon_in_c_bits_source (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source), // @[SystemBus.scala:31:26]
.auto_coherent_jbar_anon_in_c_bits_address (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address), // @[SystemBus.scala:31:26]
.auto_coherent_jbar_anon_in_c_bits_data (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data), // @[SystemBus.scala:31:26]
.auto_coherent_jbar_anon_in_c_bits_corrupt (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt), // @[SystemBus.scala:31:26]
.auto_coherent_jbar_anon_in_d_ready (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_d_ready), // @[SystemBus.scala:31:26]
.auto_coherent_jbar_anon_in_d_valid (_coh_wrapper_auto_coherent_jbar_anon_in_d_valid),
.auto_coherent_jbar_anon_in_d_bits_opcode (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_opcode),
.auto_coherent_jbar_anon_in_d_bits_param (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_param),
.auto_coherent_jbar_anon_in_d_bits_size (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_size),
.auto_coherent_jbar_anon_in_d_bits_source (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_source),
.auto_coherent_jbar_anon_in_d_bits_sink (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_sink),
.auto_coherent_jbar_anon_in_d_bits_denied (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_denied),
.auto_coherent_jbar_anon_in_d_bits_data (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_data),
.auto_coherent_jbar_anon_in_d_bits_corrupt (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_corrupt),
.auto_coherent_jbar_anon_in_e_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_valid), // @[SystemBus.scala:31:26]
.auto_coherent_jbar_anon_in_e_bits_sink (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink), // @[SystemBus.scala:31:26]
.auto_l2_ctrls_ctrl_in_a_ready (_coh_wrapper_auto_l2_ctrls_ctrl_in_a_ready),
.auto_l2_ctrls_ctrl_in_a_valid (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_valid), // @[PeripheryBus.scala:37:26]
.auto_l2_ctrls_ctrl_in_a_bits_opcode (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode), // @[PeripheryBus.scala:37:26]
.auto_l2_ctrls_ctrl_in_a_bits_param (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_param), // @[PeripheryBus.scala:37:26]
.auto_l2_ctrls_ctrl_in_a_bits_size (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_size), // @[PeripheryBus.scala:37:26]
.auto_l2_ctrls_ctrl_in_a_bits_source (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_source), // @[PeripheryBus.scala:37:26]
.auto_l2_ctrls_ctrl_in_a_bits_address (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_address), // @[PeripheryBus.scala:37:26]
.auto_l2_ctrls_ctrl_in_a_bits_mask (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask), // @[PeripheryBus.scala:37:26]
.auto_l2_ctrls_ctrl_in_a_bits_data (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_data), // @[PeripheryBus.scala:37:26]
.auto_l2_ctrls_ctrl_in_a_bits_corrupt (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26]
.auto_l2_ctrls_ctrl_in_d_ready (_cbus_auto_coupler_to_l2_ctrl_buffer_out_d_ready), // @[PeripheryBus.scala:37:26]
.auto_l2_ctrls_ctrl_in_d_valid (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_valid),
.auto_l2_ctrls_ctrl_in_d_bits_opcode (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_opcode),
.auto_l2_ctrls_ctrl_in_d_bits_size (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_size),
.auto_l2_ctrls_ctrl_in_d_bits_source (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_source),
.auto_l2_ctrls_ctrl_in_d_bits_data (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_data),
.auto_coh_clock_groups_in_member_coh_0_clock (_sbus_auto_sbus_clock_groups_out_member_coh_0_clock), // @[SystemBus.scala:31:26]
.auto_coh_clock_groups_in_member_coh_0_reset (_sbus_auto_sbus_clock_groups_out_member_coh_0_reset) // @[SystemBus.scala:31:26]
); // @[BankedCoherenceParams.scala:56:31]
TilePRCIDomain tile_prci_domain ( // @[HasTiles.scala:163:38]
.auto_intsink_in_sync_0 (debugNodesOut_sync_0), // @[MixedNode.scala:542:17]
.auto_element_reset_domain_boom_tile_trace_source_out_time (nexus_auto_in_time),
.auto_element_reset_domain_boom_tile_trace_source_out_custom_rob_empty (nexus_auto_in_custom_rob_empty),
.auto_element_reset_domain_boom_tile_hartid_in (_tileHartIdNexusNode_auto_out), // @[HasTiles.scala:75:39]
.auto_int_in_clock_xing_in_2_sync_0 (_plic_domain_auto_int_in_clock_xing_out_1_sync_0), // @[BusWrapper.scala:89:28]
.auto_int_in_clock_xing_in_1_sync_0 (_plic_domain_auto_int_in_clock_xing_out_0_sync_0), // @[BusWrapper.scala:89:28]
.auto_int_in_clock_xing_in_0_sync_0 (_clint_domain_auto_int_in_clock_xing_out_sync_0), // @[BusWrapper.scala:89:28]
.auto_int_in_clock_xing_in_0_sync_1 (_clint_domain_auto_int_in_clock_xing_out_sync_1), // @[BusWrapper.scala:89:28]
.auto_tl_master_clock_xing_out_a_ready (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_ready), // @[SystemBus.scala:31:26]
.auto_tl_master_clock_xing_out_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_a_valid),
.auto_tl_master_clock_xing_out_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_opcode),
.auto_tl_master_clock_xing_out_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_param),
.auto_tl_master_clock_xing_out_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_size),
.auto_tl_master_clock_xing_out_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_source),
.auto_tl_master_clock_xing_out_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_address),
.auto_tl_master_clock_xing_out_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_mask),
.auto_tl_master_clock_xing_out_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_data),
.auto_tl_master_clock_xing_out_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_corrupt),
.auto_tl_master_clock_xing_out_b_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_b_ready),
.auto_tl_master_clock_xing_out_b_valid (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_valid), // @[SystemBus.scala:31:26]
.auto_tl_master_clock_xing_out_b_bits_param (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_bits_param), // @[SystemBus.scala:31:26]
.auto_tl_master_clock_xing_out_b_bits_address (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_bits_address), // @[SystemBus.scala:31:26]
.auto_tl_master_clock_xing_out_c_ready (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_ready), // @[SystemBus.scala:31:26]
.auto_tl_master_clock_xing_out_c_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_c_valid),
.auto_tl_master_clock_xing_out_c_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_opcode),
.auto_tl_master_clock_xing_out_c_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_param),
.auto_tl_master_clock_xing_out_c_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_size),
.auto_tl_master_clock_xing_out_c_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_source),
.auto_tl_master_clock_xing_out_c_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_address),
.auto_tl_master_clock_xing_out_c_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_data),
.auto_tl_master_clock_xing_out_c_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_corrupt),
.auto_tl_master_clock_xing_out_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_d_ready),
.auto_tl_master_clock_xing_out_d_valid (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_valid), // @[SystemBus.scala:31:26]
.auto_tl_master_clock_xing_out_d_bits_opcode (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_opcode), // @[SystemBus.scala:31:26]
.auto_tl_master_clock_xing_out_d_bits_param (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_param), // @[SystemBus.scala:31:26]
.auto_tl_master_clock_xing_out_d_bits_size (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_size), // @[SystemBus.scala:31:26]
.auto_tl_master_clock_xing_out_d_bits_source (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_source), // @[SystemBus.scala:31:26]
.auto_tl_master_clock_xing_out_d_bits_sink (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_sink), // @[SystemBus.scala:31:26]
.auto_tl_master_clock_xing_out_d_bits_denied (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_denied), // @[SystemBus.scala:31:26]
.auto_tl_master_clock_xing_out_d_bits_data (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_data), // @[SystemBus.scala:31:26]
.auto_tl_master_clock_xing_out_d_bits_corrupt (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_corrupt), // @[SystemBus.scala:31:26]
.auto_tl_master_clock_xing_out_e_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_e_valid),
.auto_tl_master_clock_xing_out_e_bits_sink (_tile_prci_domain_auto_tl_master_clock_xing_out_e_bits_sink),
.auto_tap_clock_in_clock (_sbus_auto_fixedClockNode_anon_out_1_clock), // @[SystemBus.scala:31:26]
.auto_tap_clock_in_reset (_sbus_auto_fixedClockNode_anon_out_1_reset) // @[SystemBus.scala:31:26]
); // @[HasTiles.scala:163:38]
IntXbar_i1_o1_1 xbar (); // @[Xbar.scala:52:26]
IntXbar_i1_o1_2 xbar_1 (); // @[Xbar.scala:52:26]
IntXbar_i1_o1_3 xbar_2 (); // @[Xbar.scala:52:26]
BundleBridgeNexus_UInt1_1 tileHartIdNexusNode ( // @[HasTiles.scala:75:39]
.auto_out (_tileHartIdNexusNode_auto_out)
); // @[HasTiles.scala:75:39]
CLINTClockSinkDomain clint_domain ( // @[BusWrapper.scala:89:28]
.auto_clint_in_a_ready (_clint_domain_auto_clint_in_a_ready),
.auto_clint_in_a_valid (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_valid), // @[PeripheryBus.scala:37:26]
.auto_clint_in_a_bits_opcode (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26]
.auto_clint_in_a_bits_param (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26]
.auto_clint_in_a_bits_size (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26]
.auto_clint_in_a_bits_source (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26]
.auto_clint_in_a_bits_address (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26]
.auto_clint_in_a_bits_mask (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26]
.auto_clint_in_a_bits_data (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26]
.auto_clint_in_a_bits_corrupt (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26]
.auto_clint_in_d_ready (_cbus_auto_coupler_to_clint_fragmenter_anon_out_d_ready), // @[PeripheryBus.scala:37:26]
.auto_clint_in_d_valid (_clint_domain_auto_clint_in_d_valid),
.auto_clint_in_d_bits_opcode (_clint_domain_auto_clint_in_d_bits_opcode),
.auto_clint_in_d_bits_size (_clint_domain_auto_clint_in_d_bits_size),
.auto_clint_in_d_bits_source (_clint_domain_auto_clint_in_d_bits_source),
.auto_clint_in_d_bits_data (_clint_domain_auto_clint_in_d_bits_data),
.auto_int_in_clock_xing_out_sync_0 (_clint_domain_auto_int_in_clock_xing_out_sync_0),
.auto_int_in_clock_xing_out_sync_1 (_clint_domain_auto_int_in_clock_xing_out_sync_1),
.auto_clock_in_clock (_cbus_auto_fixedClockNode_anon_out_0_clock), // @[PeripheryBus.scala:37:26]
.auto_clock_in_reset (_cbus_auto_fixedClockNode_anon_out_0_reset), // @[PeripheryBus.scala:37:26]
.tick (int_rtc_tick), // @[Counter.scala:117:24]
.clock (_clint_domain_clock),
.reset (_clint_domain_reset)
); // @[BusWrapper.scala:89:28]
PLICClockSinkDomain plic_domain ( // @[BusWrapper.scala:89:28]
.auto_plic_int_in_0 (ibus_auto_int_bus_anon_out_0), // @[ClockDomain.scala:14:9]
.auto_plic_in_a_ready (_plic_domain_auto_plic_in_a_ready),
.auto_plic_in_a_valid (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_valid), // @[PeripheryBus.scala:37:26]
.auto_plic_in_a_bits_opcode (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26]
.auto_plic_in_a_bits_param (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26]
.auto_plic_in_a_bits_size (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26]
.auto_plic_in_a_bits_source (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26]
.auto_plic_in_a_bits_address (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26]
.auto_plic_in_a_bits_mask (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26]
.auto_plic_in_a_bits_data (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26]
.auto_plic_in_a_bits_corrupt (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26]
.auto_plic_in_d_ready (_cbus_auto_coupler_to_plic_fragmenter_anon_out_d_ready), // @[PeripheryBus.scala:37:26]
.auto_plic_in_d_valid (_plic_domain_auto_plic_in_d_valid),
.auto_plic_in_d_bits_opcode (_plic_domain_auto_plic_in_d_bits_opcode),
.auto_plic_in_d_bits_size (_plic_domain_auto_plic_in_d_bits_size),
.auto_plic_in_d_bits_source (_plic_domain_auto_plic_in_d_bits_source),
.auto_plic_in_d_bits_data (_plic_domain_auto_plic_in_d_bits_data),
.auto_int_in_clock_xing_out_1_sync_0 (_plic_domain_auto_int_in_clock_xing_out_1_sync_0),
.auto_int_in_clock_xing_out_0_sync_0 (_plic_domain_auto_int_in_clock_xing_out_0_sync_0),
.auto_clock_in_clock (_cbus_auto_fixedClockNode_anon_out_1_clock), // @[PeripheryBus.scala:37:26]
.auto_clock_in_reset (_cbus_auto_fixedClockNode_anon_out_1_reset) // @[PeripheryBus.scala:37:26]
); // @[BusWrapper.scala:89:28]
TLDebugModule tlDM ( // @[Periphery.scala:88:26]
.auto_dmInner_dmInner_sb2tlOpt_out_a_ready (_fbus_auto_coupler_from_debug_sb_widget_anon_in_a_ready), // @[FrontBus.scala:23:26]
.auto_dmInner_dmInner_sb2tlOpt_out_a_valid (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_valid),
.auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode),
.auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size),
.auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address),
.auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data),
.auto_dmInner_dmInner_sb2tlOpt_out_d_ready (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_d_ready),
.auto_dmInner_dmInner_sb2tlOpt_out_d_valid (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_valid), // @[FrontBus.scala:23:26]
.auto_dmInner_dmInner_sb2tlOpt_out_d_bits_opcode (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode), // @[FrontBus.scala:23:26]
.auto_dmInner_dmInner_sb2tlOpt_out_d_bits_param (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_param), // @[FrontBus.scala:23:26]
.auto_dmInner_dmInner_sb2tlOpt_out_d_bits_size (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_size), // @[FrontBus.scala:23:26]
.auto_dmInner_dmInner_sb2tlOpt_out_d_bits_sink (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink), // @[FrontBus.scala:23:26]
.auto_dmInner_dmInner_sb2tlOpt_out_d_bits_denied (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied), // @[FrontBus.scala:23:26]
.auto_dmInner_dmInner_sb2tlOpt_out_d_bits_data (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_data), // @[FrontBus.scala:23:26]
.auto_dmInner_dmInner_sb2tlOpt_out_d_bits_corrupt (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt), // @[FrontBus.scala:23:26]
.auto_dmInner_dmInner_tl_in_a_ready (_tlDM_auto_dmInner_dmInner_tl_in_a_ready),
.auto_dmInner_dmInner_tl_in_a_valid (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_valid), // @[PeripheryBus.scala:37:26]
.auto_dmInner_dmInner_tl_in_a_bits_opcode (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26]
.auto_dmInner_dmInner_tl_in_a_bits_param (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26]
.auto_dmInner_dmInner_tl_in_a_bits_size (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26]
.auto_dmInner_dmInner_tl_in_a_bits_source (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26]
.auto_dmInner_dmInner_tl_in_a_bits_address (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26]
.auto_dmInner_dmInner_tl_in_a_bits_mask (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26]
.auto_dmInner_dmInner_tl_in_a_bits_data (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26]
.auto_dmInner_dmInner_tl_in_a_bits_corrupt (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26]
.auto_dmInner_dmInner_tl_in_d_ready (_cbus_auto_coupler_to_debug_fragmenter_anon_out_d_ready), // @[PeripheryBus.scala:37:26]
.auto_dmInner_dmInner_tl_in_d_valid (_tlDM_auto_dmInner_dmInner_tl_in_d_valid),
.auto_dmInner_dmInner_tl_in_d_bits_opcode (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_opcode),
.auto_dmInner_dmInner_tl_in_d_bits_size (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_size),
.auto_dmInner_dmInner_tl_in_d_bits_source (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_source),
.auto_dmInner_dmInner_tl_in_d_bits_data (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_data),
.auto_dmOuter_int_out_sync_0 (debugNodesIn_sync_0),
.io_debug_clock (debug_clock_0), // @[DigitalTop.scala:47:7]
.io_debug_reset (debug_reset_0), // @[DigitalTop.scala:47:7]
.io_tl_clock (domainIn_clock), // @[MixedNode.scala:551:17]
.io_tl_reset (domainIn_reset), // @[MixedNode.scala:551:17]
.io_ctrl_ndreset (debug_ndreset),
.io_ctrl_dmactive (debug_dmactive_0),
.io_ctrl_dmactiveAck (debug_dmactiveAck_0), // @[DigitalTop.scala:47:7]
.io_dmi_dmi_req_ready (_tlDM_io_dmi_dmi_req_ready),
.io_dmi_dmi_req_valid (_dtm_io_dmi_req_valid), // @[Periphery.scala:166:21]
.io_dmi_dmi_req_bits_addr (_dtm_io_dmi_req_bits_addr), // @[Periphery.scala:166:21]
.io_dmi_dmi_req_bits_data (_dtm_io_dmi_req_bits_data), // @[Periphery.scala:166:21]
.io_dmi_dmi_req_bits_op (_dtm_io_dmi_req_bits_op), // @[Periphery.scala:166:21]
.io_dmi_dmi_resp_ready (_dtm_io_dmi_resp_ready), // @[Periphery.scala:166:21]
.io_dmi_dmi_resp_valid (_tlDM_io_dmi_dmi_resp_valid),
.io_dmi_dmi_resp_bits_data (_tlDM_io_dmi_dmi_resp_bits_data),
.io_dmi_dmi_resp_bits_resp (_tlDM_io_dmi_dmi_resp_bits_resp),
.io_dmi_dmiClock (debug_systemjtag_jtag_TCK_0), // @[DigitalTop.scala:47:7]
.io_dmi_dmiReset (debug_systemjtag_reset_0), // @[DigitalTop.scala:47:7]
.io_hartIsInReset_0 (resetctrl_hartIsInReset_0_0) // @[DigitalTop.scala:47:7]
); // @[Periphery.scala:88:26]
DebugCustomXbar debugCustomXbarOpt (); // @[Periphery.scala:80:75]
BootROMClockSinkDomain bootrom_domain ( // @[BusWrapper.scala:89:28]
.auto_bootrom_in_a_ready (_bootrom_domain_auto_bootrom_in_a_ready),
.auto_bootrom_in_a_valid (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_valid), // @[PeripheryBus.scala:37:26]
.auto_bootrom_in_a_bits_opcode (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26]
.auto_bootrom_in_a_bits_param (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26]
.auto_bootrom_in_a_bits_size (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26]
.auto_bootrom_in_a_bits_source (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26]
.auto_bootrom_in_a_bits_address (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26]
.auto_bootrom_in_a_bits_mask (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26]
.auto_bootrom_in_a_bits_data (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26]
.auto_bootrom_in_a_bits_corrupt (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26]
.auto_bootrom_in_d_ready (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_d_ready), // @[PeripheryBus.scala:37:26]
.auto_bootrom_in_d_valid (_bootrom_domain_auto_bootrom_in_d_valid),
.auto_bootrom_in_d_bits_size (_bootrom_domain_auto_bootrom_in_d_bits_size),
.auto_bootrom_in_d_bits_source (_bootrom_domain_auto_bootrom_in_d_bits_source),
.auto_bootrom_in_d_bits_data (_bootrom_domain_auto_bootrom_in_d_bits_data),
.auto_clock_in_clock (_cbus_auto_fixedClockNode_anon_out_3_clock), // @[PeripheryBus.scala:37:26]
.auto_clock_in_reset (_cbus_auto_fixedClockNode_anon_out_3_reset) // @[PeripheryBus.scala:37:26]
); // @[BusWrapper.scala:89:28]
ScratchpadBank bank ( // @[Scratchpad.scala:65:28]
.auto_xbar_anon_in_a_ready (_bank_auto_xbar_anon_in_a_ready),
.auto_xbar_anon_in_a_valid (_mbus_auto_buffer_out_a_valid), // @[MemoryBus.scala:30:26]
.auto_xbar_anon_in_a_bits_opcode (_mbus_auto_buffer_out_a_bits_opcode), // @[MemoryBus.scala:30:26]
.auto_xbar_anon_in_a_bits_param (_mbus_auto_buffer_out_a_bits_param), // @[MemoryBus.scala:30:26]
.auto_xbar_anon_in_a_bits_size (_mbus_auto_buffer_out_a_bits_size), // @[MemoryBus.scala:30:26]
.auto_xbar_anon_in_a_bits_source (_mbus_auto_buffer_out_a_bits_source), // @[MemoryBus.scala:30:26]
.auto_xbar_anon_in_a_bits_address (_mbus_auto_buffer_out_a_bits_address), // @[MemoryBus.scala:30:26]
.auto_xbar_anon_in_a_bits_mask (_mbus_auto_buffer_out_a_bits_mask), // @[MemoryBus.scala:30:26]
.auto_xbar_anon_in_a_bits_data (_mbus_auto_buffer_out_a_bits_data), // @[MemoryBus.scala:30:26]
.auto_xbar_anon_in_a_bits_corrupt (_mbus_auto_buffer_out_a_bits_corrupt), // @[MemoryBus.scala:30:26]
.auto_xbar_anon_in_d_ready (_mbus_auto_buffer_out_d_ready), // @[MemoryBus.scala:30:26]
.auto_xbar_anon_in_d_valid (_bank_auto_xbar_anon_in_d_valid),
.auto_xbar_anon_in_d_bits_opcode (_bank_auto_xbar_anon_in_d_bits_opcode),
.auto_xbar_anon_in_d_bits_param (_bank_auto_xbar_anon_in_d_bits_param),
.auto_xbar_anon_in_d_bits_size (_bank_auto_xbar_anon_in_d_bits_size),
.auto_xbar_anon_in_d_bits_source (_bank_auto_xbar_anon_in_d_bits_source),
.auto_xbar_anon_in_d_bits_sink (_bank_auto_xbar_anon_in_d_bits_sink),
.auto_xbar_anon_in_d_bits_denied (_bank_auto_xbar_anon_in_d_bits_denied),
.auto_xbar_anon_in_d_bits_data (_bank_auto_xbar_anon_in_d_bits_data),
.auto_xbar_anon_in_d_bits_corrupt (_bank_auto_xbar_anon_in_d_bits_corrupt),
.auto_clock_in_clock (_mbus_auto_fixedClockNode_anon_out_0_clock), // @[MemoryBus.scala:30:26]
.auto_clock_in_reset (_mbus_auto_fixedClockNode_anon_out_0_reset) // @[MemoryBus.scala:30:26]
); // @[Scratchpad.scala:65:28]
SerialTL0ClockSinkDomain serial_tl_domain ( // @[PeripheryTLSerial.scala:116:38]
.auto_serdesser_client_out_a_ready (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready), // @[FrontBus.scala:23:26]
.auto_serdesser_client_out_a_valid (_serial_tl_domain_auto_serdesser_client_out_a_valid),
.auto_serdesser_client_out_a_bits_opcode (_serial_tl_domain_auto_serdesser_client_out_a_bits_opcode),
.auto_serdesser_client_out_a_bits_param (_serial_tl_domain_auto_serdesser_client_out_a_bits_param),
.auto_serdesser_client_out_a_bits_size (_serial_tl_domain_auto_serdesser_client_out_a_bits_size),
.auto_serdesser_client_out_a_bits_source (_serial_tl_domain_auto_serdesser_client_out_a_bits_source),
.auto_serdesser_client_out_a_bits_address (_serial_tl_domain_auto_serdesser_client_out_a_bits_address),
.auto_serdesser_client_out_a_bits_mask (_serial_tl_domain_auto_serdesser_client_out_a_bits_mask),
.auto_serdesser_client_out_a_bits_data (_serial_tl_domain_auto_serdesser_client_out_a_bits_data),
.auto_serdesser_client_out_a_bits_corrupt (_serial_tl_domain_auto_serdesser_client_out_a_bits_corrupt),
.auto_serdesser_client_out_d_ready (_serial_tl_domain_auto_serdesser_client_out_d_ready),
.auto_serdesser_client_out_d_valid (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid), // @[FrontBus.scala:23:26]
.auto_serdesser_client_out_d_bits_opcode (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode), // @[FrontBus.scala:23:26]
.auto_serdesser_client_out_d_bits_param (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param), // @[FrontBus.scala:23:26]
.auto_serdesser_client_out_d_bits_size (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size), // @[FrontBus.scala:23:26]
.auto_serdesser_client_out_d_bits_source (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source), // @[FrontBus.scala:23:26]
.auto_serdesser_client_out_d_bits_sink (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink), // @[FrontBus.scala:23:26]
.auto_serdesser_client_out_d_bits_denied (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied), // @[FrontBus.scala:23:26]
.auto_serdesser_client_out_d_bits_data (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data), // @[FrontBus.scala:23:26]
.auto_serdesser_client_out_d_bits_corrupt (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt), // @[FrontBus.scala:23:26]
.auto_clock_in_clock (_fbus_auto_fixedClockNode_anon_out_clock), // @[FrontBus.scala:23:26]
.auto_clock_in_reset (_fbus_auto_fixedClockNode_anon_out_reset), // @[FrontBus.scala:23:26]
.serial_tl_0_in_ready (serial_tl_0_in_ready_0),
.serial_tl_0_in_valid (serial_tl_0_in_valid_0), // @[DigitalTop.scala:47:7]
.serial_tl_0_in_bits_phit (serial_tl_0_in_bits_phit_0), // @[DigitalTop.scala:47:7]
.serial_tl_0_out_ready (serial_tl_0_out_ready_0), // @[DigitalTop.scala:47:7]
.serial_tl_0_out_valid (serial_tl_0_out_valid_0),
.serial_tl_0_out_bits_phit (serial_tl_0_out_bits_phit_0),
.serial_tl_0_clock_in (serial_tl_0_clock_in_0), // @[DigitalTop.scala:47:7]
.serial_tl_0_debug_ser_busy (_serial_tl_domain_serial_tl_0_debug_ser_busy),
.serial_tl_0_debug_des_busy (_serial_tl_domain_serial_tl_0_debug_des_busy)
); // @[PeripheryTLSerial.scala:116:38]
TLUARTClockSinkDomain uartClockDomainWrapper ( // @[UART.scala:270:44]
.auto_uart_0_int_xing_out_sync_0 (intXingIn_sync_0),
.auto_uart_0_control_xing_in_a_ready (_uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready),
.auto_uart_0_control_xing_in_a_valid (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid), // @[PeripheryBus.scala:37:26]
.auto_uart_0_control_xing_in_a_bits_opcode (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode), // @[PeripheryBus.scala:37:26]
.auto_uart_0_control_xing_in_a_bits_param (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param), // @[PeripheryBus.scala:37:26]
.auto_uart_0_control_xing_in_a_bits_size (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size), // @[PeripheryBus.scala:37:26]
.auto_uart_0_control_xing_in_a_bits_source (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source), // @[PeripheryBus.scala:37:26]
.auto_uart_0_control_xing_in_a_bits_address (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address), // @[PeripheryBus.scala:37:26]
.auto_uart_0_control_xing_in_a_bits_mask (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask), // @[PeripheryBus.scala:37:26]
.auto_uart_0_control_xing_in_a_bits_data (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data), // @[PeripheryBus.scala:37:26]
.auto_uart_0_control_xing_in_a_bits_corrupt (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26]
.auto_uart_0_control_xing_in_d_ready (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready), // @[PeripheryBus.scala:37:26]
.auto_uart_0_control_xing_in_d_valid (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid),
.auto_uart_0_control_xing_in_d_bits_opcode (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode),
.auto_uart_0_control_xing_in_d_bits_size (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size),
.auto_uart_0_control_xing_in_d_bits_source (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source),
.auto_uart_0_control_xing_in_d_bits_data (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data),
.auto_uart_0_io_out_txd (ioNodeIn_txd),
.auto_uart_0_io_out_rxd (ioNodeIn_rxd), // @[MixedNode.scala:551:17]
.auto_clock_in_clock (_pbus_auto_fixedClockNode_anon_out_clock), // @[PeripheryBus.scala:37:26]
.auto_clock_in_reset (_pbus_auto_fixedClockNode_anon_out_reset) // @[PeripheryBus.scala:37:26]
); // @[UART.scala:270:44]
IntSyncSyncCrossingSink_n1x1_5 intsink ( // @[Crossing.scala:109:29]
.auto_in_sync_0 (intXingOut_sync_0), // @[MixedNode.scala:542:17]
.auto_out_0 (ibus_auto_int_bus_anon_in_0)
); // @[Crossing.scala:109:29]
ChipyardPRCICtrlClockSinkDomain chipyard_prcictrl_domain ( // @[BusWrapper.scala:89:28]
.auto_reset_setter_clock_in_member_allClocks_uncore_clock (auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock_0), // @[DigitalTop.scala:47:7]
.auto_reset_setter_clock_in_member_allClocks_uncore_reset (auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset_0), // @[DigitalTop.scala:47:7]
.auto_resetSynchronizer_out_member_allClocks_uncore_clock (_chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_clock),
.auto_resetSynchronizer_out_member_allClocks_uncore_reset (_chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_reset),
.auto_xbar_anon_in_a_ready (_chipyard_prcictrl_domain_auto_xbar_anon_in_a_ready),
.auto_xbar_anon_in_a_valid (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid), // @[PeripheryBus.scala:37:26]
.auto_xbar_anon_in_a_bits_opcode (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26]
.auto_xbar_anon_in_a_bits_param (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26]
.auto_xbar_anon_in_a_bits_size (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26]
.auto_xbar_anon_in_a_bits_source (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26]
.auto_xbar_anon_in_a_bits_address (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26]
.auto_xbar_anon_in_a_bits_mask (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26]
.auto_xbar_anon_in_a_bits_data (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26]
.auto_xbar_anon_in_a_bits_corrupt (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26]
.auto_xbar_anon_in_d_ready (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready), // @[PeripheryBus.scala:37:26]
.auto_xbar_anon_in_d_valid (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_valid),
.auto_xbar_anon_in_d_bits_opcode (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_opcode),
.auto_xbar_anon_in_d_bits_size (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_size),
.auto_xbar_anon_in_d_bits_source (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_source),
.auto_xbar_anon_in_d_bits_data (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_data),
.auto_clock_in_clock (_cbus_auto_fixedClockNode_anon_out_4_clock), // @[PeripheryBus.scala:37:26]
.auto_clock_in_reset (_cbus_auto_fixedClockNode_anon_out_4_reset) // @[PeripheryBus.scala:37:26]
); // @[BusWrapper.scala:89:28]
ClockGroupAggregator_allClocks aggregator ( // @[HasChipyardPRCI.scala:51:30]
.auto_in_member_allClocks_clockTapNode_clock_tap_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_clock), // @[ClockGroupNamePrefixer.scala:32:25]
.auto_in_member_allClocks_clockTapNode_clock_tap_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_reset), // @[ClockGroupNamePrefixer.scala:32:25]
.auto_in_member_allClocks_cbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25]
.auto_in_member_allClocks_cbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25]
.auto_in_member_allClocks_mbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25]
.auto_in_member_allClocks_mbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25]
.auto_in_member_allClocks_fbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25]
.auto_in_member_allClocks_fbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25]
.auto_in_member_allClocks_pbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25]
.auto_in_member_allClocks_pbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25]
.auto_in_member_allClocks_sbus_1_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_clock), // @[ClockGroupNamePrefixer.scala:32:25]
.auto_in_member_allClocks_sbus_1_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_reset), // @[ClockGroupNamePrefixer.scala:32:25]
.auto_in_member_allClocks_sbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25]
.auto_in_member_allClocks_sbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25]
.auto_out_5_member_clockTapNode_clockTapNode_clock_tap_clock (clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_clock),
.auto_out_5_member_clockTapNode_clockTapNode_clock_tap_reset (clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_reset),
.auto_out_4_member_cbus_cbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_clock),
.auto_out_4_member_cbus_cbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_reset),
.auto_out_3_member_mbus_mbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_clock),
.auto_out_3_member_mbus_mbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_reset),
.auto_out_2_member_fbus_fbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_clock),
.auto_out_2_member_fbus_fbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_reset),
.auto_out_1_member_pbus_pbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_clock),
.auto_out_1_member_pbus_pbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_reset),
.auto_out_0_member_sbus_sbus_1_clock (clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_clock),
.auto_out_0_member_sbus_sbus_1_reset (clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_reset),
.auto_out_0_member_sbus_sbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_clock),
.auto_out_0_member_sbus_sbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_reset)
); // @[HasChipyardPRCI.scala:51:30]
ClockGroupCombiner clockGroupCombiner ( // @[ClockGroupCombiner.scala:19:15]
.auto_clock_group_combiner_in_member_allClocks_uncore_clock (_chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_clock), // @[BusWrapper.scala:89:28]
.auto_clock_group_combiner_in_member_allClocks_uncore_reset (_chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_reset), // @[BusWrapper.scala:89:28]
.auto_clock_group_combiner_out_member_allClocks_clockTapNode_clock_tap_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_clock),
.auto_clock_group_combiner_out_member_allClocks_clockTapNode_clock_tap_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_reset),
.auto_clock_group_combiner_out_member_allClocks_cbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_clock),
.auto_clock_group_combiner_out_member_allClocks_cbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_reset),
.auto_clock_group_combiner_out_member_allClocks_mbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_clock),
.auto_clock_group_combiner_out_member_allClocks_mbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_reset),
.auto_clock_group_combiner_out_member_allClocks_fbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_clock),
.auto_clock_group_combiner_out_member_allClocks_fbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_reset),
.auto_clock_group_combiner_out_member_allClocks_pbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_clock),
.auto_clock_group_combiner_out_member_allClocks_pbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_reset),
.auto_clock_group_combiner_out_member_allClocks_sbus_1_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_clock),
.auto_clock_group_combiner_out_member_allClocks_sbus_1_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_reset),
.auto_clock_group_combiner_out_member_allClocks_sbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_clock),
.auto_clock_group_combiner_out_member_allClocks_sbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_reset)
); // @[ClockGroupCombiner.scala:19:15]
ClockSinkDomain_1 globalNoCDomain ( // @[GlobalNoC.scala:45:40]
.auto_clock_in_clock (_sbus_auto_fixedClockNode_anon_out_2_clock), // @[SystemBus.scala:31:26]
.auto_clock_in_reset (_sbus_auto_fixedClockNode_anon_out_2_reset) // @[SystemBus.scala:31:26]
); // @[GlobalNoC.scala:45:40]
BundleBridgeNexus_NoOutput_8 reRoCCManagerIdNexusNode (); // @[Integration.scala:34:44]
DebugTransportModuleJTAG dtm ( // @[Periphery.scala:166:21]
.io_jtag_clock (debug_systemjtag_jtag_TCK_0), // @[DigitalTop.scala:47:7]
.io_jtag_reset (debug_systemjtag_reset_0), // @[DigitalTop.scala:47:7]
.io_dmi_req_ready (_tlDM_io_dmi_dmi_req_ready), // @[Periphery.scala:88:26]
.io_dmi_req_valid (_dtm_io_dmi_req_valid),
.io_dmi_req_bits_addr (_dtm_io_dmi_req_bits_addr),
.io_dmi_req_bits_data (_dtm_io_dmi_req_bits_data),
.io_dmi_req_bits_op (_dtm_io_dmi_req_bits_op),
.io_dmi_resp_ready (_dtm_io_dmi_resp_ready),
.io_dmi_resp_valid (_tlDM_io_dmi_dmi_resp_valid), // @[Periphery.scala:88:26]
.io_dmi_resp_bits_data (_tlDM_io_dmi_dmi_resp_bits_data), // @[Periphery.scala:88:26]
.io_dmi_resp_bits_resp (_tlDM_io_dmi_dmi_resp_bits_resp), // @[Periphery.scala:88:26]
.io_jtag_TCK (debug_systemjtag_jtag_TCK_0), // @[DigitalTop.scala:47:7]
.io_jtag_TMS (debug_systemjtag_jtag_TMS_0), // @[DigitalTop.scala:47:7]
.io_jtag_TDI (debug_systemjtag_jtag_TDI_0), // @[DigitalTop.scala:47:7]
.io_jtag_TDO_data (debug_systemjtag_jtag_TDO_data_0),
.io_jtag_TDO_driven (debug_systemjtag_jtag_TDO_driven),
.rf_reset (debug_systemjtag_reset_0) // @[DigitalTop.scala:47:7]
); // @[Periphery.scala:166:21]
assign auto_mbus_fixedClockNode_anon_out_clock = auto_mbus_fixedClockNode_anon_out_clock_0; // @[DigitalTop.scala:47:7]
assign auto_mbus_fixedClockNode_anon_out_reset = auto_mbus_fixedClockNode_anon_out_reset_0; // @[DigitalTop.scala:47:7]
assign auto_cbus_fixedClockNode_anon_out_clock = auto_cbus_fixedClockNode_anon_out_clock_0; // @[DigitalTop.scala:47:7]
assign auto_cbus_fixedClockNode_anon_out_reset = auto_cbus_fixedClockNode_anon_out_reset_0; // @[DigitalTop.scala:47:7]
assign debug_systemjtag_jtag_TDO_data = debug_systemjtag_jtag_TDO_data_0; // @[DigitalTop.scala:47:7]
assign debug_dmactive = debug_dmactive_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_aw_valid = mem_axi4_0_aw_valid_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_aw_bits_id = mem_axi4_0_aw_bits_id_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_aw_bits_addr = mem_axi4_0_aw_bits_addr_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_aw_bits_len = mem_axi4_0_aw_bits_len_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_aw_bits_size = mem_axi4_0_aw_bits_size_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_aw_bits_burst = mem_axi4_0_aw_bits_burst_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_aw_bits_lock = mem_axi4_0_aw_bits_lock_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_aw_bits_cache = mem_axi4_0_aw_bits_cache_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_aw_bits_prot = mem_axi4_0_aw_bits_prot_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_aw_bits_qos = mem_axi4_0_aw_bits_qos_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_w_valid = mem_axi4_0_w_valid_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_w_bits_data = mem_axi4_0_w_bits_data_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_w_bits_strb = mem_axi4_0_w_bits_strb_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_w_bits_last = mem_axi4_0_w_bits_last_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_b_ready = mem_axi4_0_b_ready_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_ar_valid = mem_axi4_0_ar_valid_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_ar_bits_id = mem_axi4_0_ar_bits_id_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_ar_bits_addr = mem_axi4_0_ar_bits_addr_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_ar_bits_len = mem_axi4_0_ar_bits_len_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_ar_bits_size = mem_axi4_0_ar_bits_size_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_ar_bits_burst = mem_axi4_0_ar_bits_burst_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_ar_bits_lock = mem_axi4_0_ar_bits_lock_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_ar_bits_cache = mem_axi4_0_ar_bits_cache_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_ar_bits_prot = mem_axi4_0_ar_bits_prot_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_ar_bits_qos = mem_axi4_0_ar_bits_qos_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_r_ready = mem_axi4_0_r_ready_0; // @[DigitalTop.scala:47:7]
assign serial_tl_0_in_ready = serial_tl_0_in_ready_0; // @[DigitalTop.scala:47:7]
assign serial_tl_0_out_valid = serial_tl_0_out_valid_0; // @[DigitalTop.scala:47:7]
assign serial_tl_0_out_bits_phit = serial_tl_0_out_bits_phit_0; // @[DigitalTop.scala:47:7]
assign uart_0_txd = uart_0_txd_0; // @[DigitalTop.scala:47:7]
assign clock_tap = clockTapIn_clock; // @[MixedNode.scala:551:17]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module BundleBridgeNexus_UInt4_12 :
output auto : { out_11 : UInt<4>, out_10 : UInt<4>, out_9 : UInt<4>, out_8 : UInt<4>, out_7 : UInt<4>, out_6 : UInt<4>, out_5 : UInt<4>, out_4 : UInt<4>, out_3 : UInt<4>, out_2 : UInt<4>, out_1 : UInt<4>, out_0 : UInt<4>}
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
wire nodeOut : UInt<4>
invalidate nodeOut
wire x1_nodeOut : UInt<4>
invalidate x1_nodeOut
wire x1_nodeOut_1 : UInt<4>
invalidate x1_nodeOut_1
wire x1_nodeOut_2 : UInt<4>
invalidate x1_nodeOut_2
wire x1_nodeOut_3 : UInt<4>
invalidate x1_nodeOut_3
wire x1_nodeOut_4 : UInt<4>
invalidate x1_nodeOut_4
wire x1_nodeOut_5 : UInt<4>
invalidate x1_nodeOut_5
wire x1_nodeOut_6 : UInt<4>
invalidate x1_nodeOut_6
wire x1_nodeOut_7 : UInt<4>
invalidate x1_nodeOut_7
wire x1_nodeOut_8 : UInt<4>
invalidate x1_nodeOut_8
wire x1_nodeOut_9 : UInt<4>
invalidate x1_nodeOut_9
wire x1_nodeOut_10 : UInt<4>
invalidate x1_nodeOut_10
connect auto.out_0, nodeOut
connect auto.out_1, x1_nodeOut
connect auto.out_2, x1_nodeOut_1
connect auto.out_3, x1_nodeOut_2
connect auto.out_4, x1_nodeOut_3
connect auto.out_5, x1_nodeOut_4
connect auto.out_6, x1_nodeOut_5
connect auto.out_7, x1_nodeOut_6
connect auto.out_8, x1_nodeOut_7
connect auto.out_9, x1_nodeOut_8
connect auto.out_10, x1_nodeOut_9
connect auto.out_11, x1_nodeOut_10
node outputs_0 = or(UInt<4>(0h0), UInt<4>(0h0))
node outputs_1 = or(UInt<4>(0h0), UInt<4>(0h1))
node outputs_2 = or(UInt<4>(0h0), UInt<4>(0h2))
node outputs_3 = or(UInt<4>(0h0), UInt<4>(0h3))
node outputs_4 = or(UInt<4>(0h0), UInt<4>(0h4))
node outputs_5 = or(UInt<4>(0h0), UInt<4>(0h5))
node outputs_6 = or(UInt<4>(0h0), UInt<4>(0h6))
node outputs_7 = or(UInt<4>(0h0), UInt<4>(0h7))
node outputs_8 = or(UInt<4>(0h0), UInt<4>(0h8))
node outputs_9 = or(UInt<4>(0h0), UInt<4>(0h9))
node outputs_10 = or(UInt<4>(0h0), UInt<4>(0ha))
node outputs_11 = or(UInt<4>(0h0), UInt<4>(0hb))
connect nodeOut, outputs_0
connect x1_nodeOut, outputs_1
connect x1_nodeOut_1, outputs_2
connect x1_nodeOut_2, outputs_3
connect x1_nodeOut_3, outputs_4
connect x1_nodeOut_4, outputs_5
connect x1_nodeOut_5, outputs_6
connect x1_nodeOut_6, outputs_7
connect x1_nodeOut_7, outputs_8
connect x1_nodeOut_8, outputs_9
connect x1_nodeOut_9, outputs_10
connect x1_nodeOut_10, outputs_11 | module BundleBridgeNexus_UInt4_12( // @[BundleBridgeNexus.scala:20:9]
output [3:0] auto_out_11, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_10, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_9, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_8, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_7, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_6, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_5, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_4, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_3, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_2, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_1, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_0 // @[LazyModuleImp.scala:107:25]
);
wire [3:0] outputs_0 = 4'h0; // @[HasTiles.scala:78:32]
wire [3:0] outputs_1 = 4'h1; // @[HasTiles.scala:78:32]
wire [3:0] outputs_2 = 4'h2; // @[HasTiles.scala:78:32]
wire [3:0] outputs_3 = 4'h3; // @[HasTiles.scala:78:32]
wire [3:0] outputs_4 = 4'h4; // @[HasTiles.scala:78:32]
wire [3:0] outputs_5 = 4'h5; // @[HasTiles.scala:78:32]
wire [3:0] outputs_6 = 4'h6; // @[HasTiles.scala:78:32]
wire [3:0] outputs_7 = 4'h7; // @[HasTiles.scala:78:32]
wire [3:0] outputs_8 = 4'h8; // @[HasTiles.scala:78:32]
wire [3:0] outputs_9 = 4'h9; // @[HasTiles.scala:78:32]
wire [3:0] outputs_10 = 4'hA; // @[HasTiles.scala:78:32]
wire [3:0] outputs_11 = 4'hB; // @[HasTiles.scala:78:32]
assign auto_out_11 = outputs_11; // @[HasTiles.scala:78:32]
assign auto_out_10 = outputs_10; // @[HasTiles.scala:78:32]
assign auto_out_9 = outputs_9; // @[HasTiles.scala:78:32]
assign auto_out_8 = outputs_8; // @[HasTiles.scala:78:32]
assign auto_out_7 = outputs_7; // @[HasTiles.scala:78:32]
assign auto_out_6 = outputs_6; // @[HasTiles.scala:78:32]
assign auto_out_5 = outputs_5; // @[HasTiles.scala:78:32]
assign auto_out_4 = outputs_4; // @[HasTiles.scala:78:32]
assign auto_out_3 = outputs_3; // @[HasTiles.scala:78:32]
assign auto_out_2 = outputs_2; // @[HasTiles.scala:78:32]
assign auto_out_1 = outputs_1; // @[HasTiles.scala:78:32]
assign auto_out_0 = outputs_0; // @[HasTiles.scala:78:32]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PMPChecker_s3_4 :
input clock : Clock
input reset : Reset
output io : { flip prv : UInt<2>, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip addr : UInt<32>, flip size : UInt<2>, r : UInt<1>, w : UInt<1>, x : UInt<1>}
node default = gt(io.prv, UInt<1>(0h1))
wire _pmp0_WIRE : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect _pmp0_WIRE.mask, UInt<32>(0h0)
connect _pmp0_WIRE.addr, UInt<30>(0h0)
connect _pmp0_WIRE.cfg.r, UInt<1>(0h0)
connect _pmp0_WIRE.cfg.w, UInt<1>(0h0)
connect _pmp0_WIRE.cfg.x, UInt<1>(0h0)
connect _pmp0_WIRE.cfg.a, UInt<2>(0h0)
connect _pmp0_WIRE.cfg.res, UInt<2>(0h0)
connect _pmp0_WIRE.cfg.l, UInt<1>(0h0)
wire pmp0 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect pmp0, _pmp0_WIRE
connect pmp0.cfg.r, default
connect pmp0.cfg.w, default
connect pmp0.cfg.x, default
node _res_hit_T = bits(io.pmp[7].cfg.a, 1, 1)
node _res_hit_lsbMask_T = dshl(UInt<3>(0h7), io.size)
node _res_hit_lsbMask_T_1 = bits(_res_hit_lsbMask_T, 2, 0)
node _res_hit_lsbMask_T_2 = not(_res_hit_lsbMask_T_1)
node res_hit_lsbMask = or(io.pmp[7].mask, _res_hit_lsbMask_T_2)
node _res_hit_msbMatch_T = shr(io.addr, 3)
node _res_hit_msbMatch_T_1 = shl(io.pmp[7].addr, 2)
node _res_hit_msbMatch_T_2 = not(_res_hit_msbMatch_T_1)
node _res_hit_msbMatch_T_3 = or(_res_hit_msbMatch_T_2, UInt<2>(0h3))
node _res_hit_msbMatch_T_4 = not(_res_hit_msbMatch_T_3)
node _res_hit_msbMatch_T_5 = shr(_res_hit_msbMatch_T_4, 3)
node _res_hit_msbMatch_T_6 = shr(io.pmp[7].mask, 3)
node _res_hit_msbMatch_T_7 = xor(_res_hit_msbMatch_T, _res_hit_msbMatch_T_5)
node _res_hit_msbMatch_T_8 = not(_res_hit_msbMatch_T_6)
node _res_hit_msbMatch_T_9 = and(_res_hit_msbMatch_T_7, _res_hit_msbMatch_T_8)
node res_hit_msbMatch = eq(_res_hit_msbMatch_T_9, UInt<1>(0h0))
node _res_hit_lsbMatch_T = bits(io.addr, 2, 0)
node _res_hit_lsbMatch_T_1 = shl(io.pmp[7].addr, 2)
node _res_hit_lsbMatch_T_2 = not(_res_hit_lsbMatch_T_1)
node _res_hit_lsbMatch_T_3 = or(_res_hit_lsbMatch_T_2, UInt<2>(0h3))
node _res_hit_lsbMatch_T_4 = not(_res_hit_lsbMatch_T_3)
node _res_hit_lsbMatch_T_5 = bits(_res_hit_lsbMatch_T_4, 2, 0)
node _res_hit_lsbMatch_T_6 = bits(res_hit_lsbMask, 2, 0)
node _res_hit_lsbMatch_T_7 = xor(_res_hit_lsbMatch_T, _res_hit_lsbMatch_T_5)
node _res_hit_lsbMatch_T_8 = not(_res_hit_lsbMatch_T_6)
node _res_hit_lsbMatch_T_9 = and(_res_hit_lsbMatch_T_7, _res_hit_lsbMatch_T_8)
node res_hit_lsbMatch = eq(_res_hit_lsbMatch_T_9, UInt<1>(0h0))
node _res_hit_T_1 = and(res_hit_msbMatch, res_hit_lsbMatch)
node _res_hit_T_2 = bits(io.pmp[7].cfg.a, 0, 0)
node _res_hit_T_3 = dshl(UInt<3>(0h7), io.size)
node _res_hit_T_4 = bits(_res_hit_T_3, 2, 0)
node _res_hit_T_5 = not(_res_hit_T_4)
node _res_hit_msbsLess_T = shr(io.addr, 3)
node _res_hit_msbsLess_T_1 = shl(io.pmp[6].addr, 2)
node _res_hit_msbsLess_T_2 = not(_res_hit_msbsLess_T_1)
node _res_hit_msbsLess_T_3 = or(_res_hit_msbsLess_T_2, UInt<2>(0h3))
node _res_hit_msbsLess_T_4 = not(_res_hit_msbsLess_T_3)
node _res_hit_msbsLess_T_5 = shr(_res_hit_msbsLess_T_4, 3)
node res_hit_msbsLess = lt(_res_hit_msbsLess_T, _res_hit_msbsLess_T_5)
node _res_hit_msbsEqual_T = shr(io.addr, 3)
node _res_hit_msbsEqual_T_1 = shl(io.pmp[6].addr, 2)
node _res_hit_msbsEqual_T_2 = not(_res_hit_msbsEqual_T_1)
node _res_hit_msbsEqual_T_3 = or(_res_hit_msbsEqual_T_2, UInt<2>(0h3))
node _res_hit_msbsEqual_T_4 = not(_res_hit_msbsEqual_T_3)
node _res_hit_msbsEqual_T_5 = shr(_res_hit_msbsEqual_T_4, 3)
node _res_hit_msbsEqual_T_6 = xor(_res_hit_msbsEqual_T, _res_hit_msbsEqual_T_5)
node res_hit_msbsEqual = eq(_res_hit_msbsEqual_T_6, UInt<1>(0h0))
node _res_hit_lsbsLess_T = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_1 = or(_res_hit_lsbsLess_T, _res_hit_T_5)
node _res_hit_lsbsLess_T_2 = shl(io.pmp[6].addr, 2)
node _res_hit_lsbsLess_T_3 = not(_res_hit_lsbsLess_T_2)
node _res_hit_lsbsLess_T_4 = or(_res_hit_lsbsLess_T_3, UInt<2>(0h3))
node _res_hit_lsbsLess_T_5 = not(_res_hit_lsbsLess_T_4)
node _res_hit_lsbsLess_T_6 = bits(_res_hit_lsbsLess_T_5, 2, 0)
node res_hit_lsbsLess = lt(_res_hit_lsbsLess_T_1, _res_hit_lsbsLess_T_6)
node _res_hit_T_6 = and(res_hit_msbsEqual, res_hit_lsbsLess)
node _res_hit_T_7 = or(res_hit_msbsLess, _res_hit_T_6)
node _res_hit_T_8 = eq(_res_hit_T_7, UInt<1>(0h0))
node _res_hit_msbsLess_T_6 = shr(io.addr, 3)
node _res_hit_msbsLess_T_7 = shl(io.pmp[7].addr, 2)
node _res_hit_msbsLess_T_8 = not(_res_hit_msbsLess_T_7)
node _res_hit_msbsLess_T_9 = or(_res_hit_msbsLess_T_8, UInt<2>(0h3))
node _res_hit_msbsLess_T_10 = not(_res_hit_msbsLess_T_9)
node _res_hit_msbsLess_T_11 = shr(_res_hit_msbsLess_T_10, 3)
node res_hit_msbsLess_1 = lt(_res_hit_msbsLess_T_6, _res_hit_msbsLess_T_11)
node _res_hit_msbsEqual_T_7 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_8 = shl(io.pmp[7].addr, 2)
node _res_hit_msbsEqual_T_9 = not(_res_hit_msbsEqual_T_8)
node _res_hit_msbsEqual_T_10 = or(_res_hit_msbsEqual_T_9, UInt<2>(0h3))
node _res_hit_msbsEqual_T_11 = not(_res_hit_msbsEqual_T_10)
node _res_hit_msbsEqual_T_12 = shr(_res_hit_msbsEqual_T_11, 3)
node _res_hit_msbsEqual_T_13 = xor(_res_hit_msbsEqual_T_7, _res_hit_msbsEqual_T_12)
node res_hit_msbsEqual_1 = eq(_res_hit_msbsEqual_T_13, UInt<1>(0h0))
node _res_hit_lsbsLess_T_7 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_8 = or(_res_hit_lsbsLess_T_7, UInt<1>(0h0))
node _res_hit_lsbsLess_T_9 = shl(io.pmp[7].addr, 2)
node _res_hit_lsbsLess_T_10 = not(_res_hit_lsbsLess_T_9)
node _res_hit_lsbsLess_T_11 = or(_res_hit_lsbsLess_T_10, UInt<2>(0h3))
node _res_hit_lsbsLess_T_12 = not(_res_hit_lsbsLess_T_11)
node _res_hit_lsbsLess_T_13 = bits(_res_hit_lsbsLess_T_12, 2, 0)
node res_hit_lsbsLess_1 = lt(_res_hit_lsbsLess_T_8, _res_hit_lsbsLess_T_13)
node _res_hit_T_9 = and(res_hit_msbsEqual_1, res_hit_lsbsLess_1)
node _res_hit_T_10 = or(res_hit_msbsLess_1, _res_hit_T_9)
node _res_hit_T_11 = and(_res_hit_T_8, _res_hit_T_10)
node _res_hit_T_12 = and(_res_hit_T_2, _res_hit_T_11)
node res_hit = mux(_res_hit_T, _res_hit_T_1, _res_hit_T_12)
node _res_ignore_T = eq(io.pmp[7].cfg.l, UInt<1>(0h0))
node res_ignore = and(default, _res_ignore_T)
node _res_aligned_lsbMask_T = dshl(UInt<3>(0h7), io.size)
node _res_aligned_lsbMask_T_1 = bits(_res_aligned_lsbMask_T, 2, 0)
node res_aligned_lsbMask = not(_res_aligned_lsbMask_T_1)
node _res_aligned_straddlesLowerBound_T = shr(io.addr, 3)
node _res_aligned_straddlesLowerBound_T_1 = shl(io.pmp[6].addr, 2)
node _res_aligned_straddlesLowerBound_T_2 = not(_res_aligned_straddlesLowerBound_T_1)
node _res_aligned_straddlesLowerBound_T_3 = or(_res_aligned_straddlesLowerBound_T_2, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_4 = not(_res_aligned_straddlesLowerBound_T_3)
node _res_aligned_straddlesLowerBound_T_5 = shr(_res_aligned_straddlesLowerBound_T_4, 3)
node _res_aligned_straddlesLowerBound_T_6 = xor(_res_aligned_straddlesLowerBound_T, _res_aligned_straddlesLowerBound_T_5)
node _res_aligned_straddlesLowerBound_T_7 = eq(_res_aligned_straddlesLowerBound_T_6, UInt<1>(0h0))
node _res_aligned_straddlesLowerBound_T_8 = shl(io.pmp[6].addr, 2)
node _res_aligned_straddlesLowerBound_T_9 = not(_res_aligned_straddlesLowerBound_T_8)
node _res_aligned_straddlesLowerBound_T_10 = or(_res_aligned_straddlesLowerBound_T_9, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_11 = not(_res_aligned_straddlesLowerBound_T_10)
node _res_aligned_straddlesLowerBound_T_12 = bits(_res_aligned_straddlesLowerBound_T_11, 2, 0)
node _res_aligned_straddlesLowerBound_T_13 = bits(io.addr, 2, 0)
node _res_aligned_straddlesLowerBound_T_14 = not(_res_aligned_straddlesLowerBound_T_13)
node _res_aligned_straddlesLowerBound_T_15 = and(_res_aligned_straddlesLowerBound_T_12, _res_aligned_straddlesLowerBound_T_14)
node _res_aligned_straddlesLowerBound_T_16 = neq(_res_aligned_straddlesLowerBound_T_15, UInt<1>(0h0))
node res_aligned_straddlesLowerBound = and(_res_aligned_straddlesLowerBound_T_7, _res_aligned_straddlesLowerBound_T_16)
node _res_aligned_straddlesUpperBound_T = shr(io.addr, 3)
node _res_aligned_straddlesUpperBound_T_1 = shl(io.pmp[7].addr, 2)
node _res_aligned_straddlesUpperBound_T_2 = not(_res_aligned_straddlesUpperBound_T_1)
node _res_aligned_straddlesUpperBound_T_3 = or(_res_aligned_straddlesUpperBound_T_2, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_4 = not(_res_aligned_straddlesUpperBound_T_3)
node _res_aligned_straddlesUpperBound_T_5 = shr(_res_aligned_straddlesUpperBound_T_4, 3)
node _res_aligned_straddlesUpperBound_T_6 = xor(_res_aligned_straddlesUpperBound_T, _res_aligned_straddlesUpperBound_T_5)
node _res_aligned_straddlesUpperBound_T_7 = eq(_res_aligned_straddlesUpperBound_T_6, UInt<1>(0h0))
node _res_aligned_straddlesUpperBound_T_8 = shl(io.pmp[7].addr, 2)
node _res_aligned_straddlesUpperBound_T_9 = not(_res_aligned_straddlesUpperBound_T_8)
node _res_aligned_straddlesUpperBound_T_10 = or(_res_aligned_straddlesUpperBound_T_9, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_11 = not(_res_aligned_straddlesUpperBound_T_10)
node _res_aligned_straddlesUpperBound_T_12 = bits(_res_aligned_straddlesUpperBound_T_11, 2, 0)
node _res_aligned_straddlesUpperBound_T_13 = bits(io.addr, 2, 0)
node _res_aligned_straddlesUpperBound_T_14 = or(_res_aligned_straddlesUpperBound_T_13, res_aligned_lsbMask)
node _res_aligned_straddlesUpperBound_T_15 = and(_res_aligned_straddlesUpperBound_T_12, _res_aligned_straddlesUpperBound_T_14)
node _res_aligned_straddlesUpperBound_T_16 = neq(_res_aligned_straddlesUpperBound_T_15, UInt<1>(0h0))
node res_aligned_straddlesUpperBound = and(_res_aligned_straddlesUpperBound_T_7, _res_aligned_straddlesUpperBound_T_16)
node _res_aligned_rangeAligned_T = or(res_aligned_straddlesLowerBound, res_aligned_straddlesUpperBound)
node res_aligned_rangeAligned = eq(_res_aligned_rangeAligned_T, UInt<1>(0h0))
node _res_aligned_pow2Aligned_T = bits(io.pmp[7].mask, 2, 0)
node _res_aligned_pow2Aligned_T_1 = not(_res_aligned_pow2Aligned_T)
node _res_aligned_pow2Aligned_T_2 = and(res_aligned_lsbMask, _res_aligned_pow2Aligned_T_1)
node res_aligned_pow2Aligned = eq(_res_aligned_pow2Aligned_T_2, UInt<1>(0h0))
node _res_aligned_T = bits(io.pmp[7].cfg.a, 1, 1)
node res_aligned = mux(_res_aligned_T, res_aligned_pow2Aligned, res_aligned_rangeAligned)
node _res_T = eq(io.pmp[7].cfg.a, UInt<1>(0h0))
node _res_T_1 = eq(io.pmp[7].cfg.a, UInt<1>(0h1))
node _res_T_2 = eq(io.pmp[7].cfg.a, UInt<2>(0h2))
node _res_T_3 = eq(io.pmp[7].cfg.a, UInt<2>(0h3))
node _res_T_4 = eq(io.pmp[7].cfg.l, UInt<1>(0h1))
node res_hi = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w)
node _res_T_5 = cat(res_hi, io.pmp[7].cfg.r)
node _res_T_6 = eq(_res_T_5, UInt<1>(0h0))
node res_hi_1 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w)
node _res_T_7 = cat(res_hi_1, io.pmp[7].cfg.r)
node _res_T_8 = eq(_res_T_7, UInt<1>(0h1))
node res_hi_2 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w)
node _res_T_9 = cat(res_hi_2, io.pmp[7].cfg.r)
node _res_T_10 = eq(_res_T_9, UInt<2>(0h3))
node res_hi_3 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w)
node _res_T_11 = cat(res_hi_3, io.pmp[7].cfg.r)
node _res_T_12 = eq(_res_T_11, UInt<3>(0h4))
node res_hi_4 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w)
node _res_T_13 = cat(res_hi_4, io.pmp[7].cfg.r)
node _res_T_14 = eq(_res_T_13, UInt<3>(0h5))
node res_hi_5 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w)
node _res_T_15 = cat(res_hi_5, io.pmp[7].cfg.r)
node _res_T_16 = eq(_res_T_15, UInt<3>(0h7))
node _res_T_17 = eq(res_ignore, UInt<1>(0h0))
node _res_T_18 = and(_res_T_17, res_hit)
node _res_T_19 = and(_res_T_18, res_aligned)
node _res_T_20 = eq(io.pmp[7].cfg.a, UInt<1>(0h1))
node _res_T_21 = and(_res_T_19, _res_T_20)
node _res_T_22 = and(io.pmp[7].cfg.l, res_hit)
node _res_T_23 = and(_res_T_22, res_aligned)
node _res_T_24 = eq(io.pmp[7].cfg.a, UInt<1>(0h1))
node _res_T_25 = and(_res_T_23, _res_T_24)
node _res_T_26 = eq(res_ignore, UInt<1>(0h0))
node _res_T_27 = and(_res_T_26, res_hit)
node _res_T_28 = and(_res_T_27, res_aligned)
node _res_T_29 = eq(io.pmp[7].cfg.a, UInt<2>(0h2))
node _res_T_30 = and(_res_T_28, _res_T_29)
node _res_T_31 = and(io.pmp[7].cfg.l, res_hit)
node _res_T_32 = and(_res_T_31, res_aligned)
node _res_T_33 = eq(io.pmp[7].cfg.a, UInt<2>(0h2))
node _res_T_34 = and(_res_T_32, _res_T_33)
node _res_T_35 = eq(res_ignore, UInt<1>(0h0))
node _res_T_36 = and(_res_T_35, res_hit)
node _res_T_37 = and(_res_T_36, res_aligned)
node _res_T_38 = eq(io.pmp[7].cfg.a, UInt<2>(0h3))
node _res_T_39 = and(_res_T_37, _res_T_38)
node _res_T_40 = and(io.pmp[7].cfg.l, res_hit)
node _res_T_41 = and(_res_T_40, res_aligned)
node _res_T_42 = eq(io.pmp[7].cfg.a, UInt<2>(0h3))
node _res_T_43 = and(_res_T_41, _res_T_42)
wire res_cur : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur, io.pmp[7]
node _res_cur_cfg_r_T = or(io.pmp[7].cfg.r, res_ignore)
node _res_cur_cfg_r_T_1 = and(res_aligned, _res_cur_cfg_r_T)
connect res_cur.cfg.r, _res_cur_cfg_r_T_1
node _res_cur_cfg_w_T = or(io.pmp[7].cfg.w, res_ignore)
node _res_cur_cfg_w_T_1 = and(res_aligned, _res_cur_cfg_w_T)
connect res_cur.cfg.w, _res_cur_cfg_w_T_1
node _res_cur_cfg_x_T = or(io.pmp[7].cfg.x, res_ignore)
node _res_cur_cfg_x_T_1 = and(res_aligned, _res_cur_cfg_x_T)
connect res_cur.cfg.x, _res_cur_cfg_x_T_1
node _res_T_44 = mux(res_hit, res_cur, pmp0)
node _res_hit_T_13 = bits(io.pmp[6].cfg.a, 1, 1)
node _res_hit_lsbMask_T_3 = dshl(UInt<3>(0h7), io.size)
node _res_hit_lsbMask_T_4 = bits(_res_hit_lsbMask_T_3, 2, 0)
node _res_hit_lsbMask_T_5 = not(_res_hit_lsbMask_T_4)
node res_hit_lsbMask_1 = or(io.pmp[6].mask, _res_hit_lsbMask_T_5)
node _res_hit_msbMatch_T_10 = shr(io.addr, 3)
node _res_hit_msbMatch_T_11 = shl(io.pmp[6].addr, 2)
node _res_hit_msbMatch_T_12 = not(_res_hit_msbMatch_T_11)
node _res_hit_msbMatch_T_13 = or(_res_hit_msbMatch_T_12, UInt<2>(0h3))
node _res_hit_msbMatch_T_14 = not(_res_hit_msbMatch_T_13)
node _res_hit_msbMatch_T_15 = shr(_res_hit_msbMatch_T_14, 3)
node _res_hit_msbMatch_T_16 = shr(io.pmp[6].mask, 3)
node _res_hit_msbMatch_T_17 = xor(_res_hit_msbMatch_T_10, _res_hit_msbMatch_T_15)
node _res_hit_msbMatch_T_18 = not(_res_hit_msbMatch_T_16)
node _res_hit_msbMatch_T_19 = and(_res_hit_msbMatch_T_17, _res_hit_msbMatch_T_18)
node res_hit_msbMatch_1 = eq(_res_hit_msbMatch_T_19, UInt<1>(0h0))
node _res_hit_lsbMatch_T_10 = bits(io.addr, 2, 0)
node _res_hit_lsbMatch_T_11 = shl(io.pmp[6].addr, 2)
node _res_hit_lsbMatch_T_12 = not(_res_hit_lsbMatch_T_11)
node _res_hit_lsbMatch_T_13 = or(_res_hit_lsbMatch_T_12, UInt<2>(0h3))
node _res_hit_lsbMatch_T_14 = not(_res_hit_lsbMatch_T_13)
node _res_hit_lsbMatch_T_15 = bits(_res_hit_lsbMatch_T_14, 2, 0)
node _res_hit_lsbMatch_T_16 = bits(res_hit_lsbMask_1, 2, 0)
node _res_hit_lsbMatch_T_17 = xor(_res_hit_lsbMatch_T_10, _res_hit_lsbMatch_T_15)
node _res_hit_lsbMatch_T_18 = not(_res_hit_lsbMatch_T_16)
node _res_hit_lsbMatch_T_19 = and(_res_hit_lsbMatch_T_17, _res_hit_lsbMatch_T_18)
node res_hit_lsbMatch_1 = eq(_res_hit_lsbMatch_T_19, UInt<1>(0h0))
node _res_hit_T_14 = and(res_hit_msbMatch_1, res_hit_lsbMatch_1)
node _res_hit_T_15 = bits(io.pmp[6].cfg.a, 0, 0)
node _res_hit_T_16 = dshl(UInt<3>(0h7), io.size)
node _res_hit_T_17 = bits(_res_hit_T_16, 2, 0)
node _res_hit_T_18 = not(_res_hit_T_17)
node _res_hit_msbsLess_T_12 = shr(io.addr, 3)
node _res_hit_msbsLess_T_13 = shl(io.pmp[5].addr, 2)
node _res_hit_msbsLess_T_14 = not(_res_hit_msbsLess_T_13)
node _res_hit_msbsLess_T_15 = or(_res_hit_msbsLess_T_14, UInt<2>(0h3))
node _res_hit_msbsLess_T_16 = not(_res_hit_msbsLess_T_15)
node _res_hit_msbsLess_T_17 = shr(_res_hit_msbsLess_T_16, 3)
node res_hit_msbsLess_2 = lt(_res_hit_msbsLess_T_12, _res_hit_msbsLess_T_17)
node _res_hit_msbsEqual_T_14 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_15 = shl(io.pmp[5].addr, 2)
node _res_hit_msbsEqual_T_16 = not(_res_hit_msbsEqual_T_15)
node _res_hit_msbsEqual_T_17 = or(_res_hit_msbsEqual_T_16, UInt<2>(0h3))
node _res_hit_msbsEqual_T_18 = not(_res_hit_msbsEqual_T_17)
node _res_hit_msbsEqual_T_19 = shr(_res_hit_msbsEqual_T_18, 3)
node _res_hit_msbsEqual_T_20 = xor(_res_hit_msbsEqual_T_14, _res_hit_msbsEqual_T_19)
node res_hit_msbsEqual_2 = eq(_res_hit_msbsEqual_T_20, UInt<1>(0h0))
node _res_hit_lsbsLess_T_14 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_15 = or(_res_hit_lsbsLess_T_14, _res_hit_T_18)
node _res_hit_lsbsLess_T_16 = shl(io.pmp[5].addr, 2)
node _res_hit_lsbsLess_T_17 = not(_res_hit_lsbsLess_T_16)
node _res_hit_lsbsLess_T_18 = or(_res_hit_lsbsLess_T_17, UInt<2>(0h3))
node _res_hit_lsbsLess_T_19 = not(_res_hit_lsbsLess_T_18)
node _res_hit_lsbsLess_T_20 = bits(_res_hit_lsbsLess_T_19, 2, 0)
node res_hit_lsbsLess_2 = lt(_res_hit_lsbsLess_T_15, _res_hit_lsbsLess_T_20)
node _res_hit_T_19 = and(res_hit_msbsEqual_2, res_hit_lsbsLess_2)
node _res_hit_T_20 = or(res_hit_msbsLess_2, _res_hit_T_19)
node _res_hit_T_21 = eq(_res_hit_T_20, UInt<1>(0h0))
node _res_hit_msbsLess_T_18 = shr(io.addr, 3)
node _res_hit_msbsLess_T_19 = shl(io.pmp[6].addr, 2)
node _res_hit_msbsLess_T_20 = not(_res_hit_msbsLess_T_19)
node _res_hit_msbsLess_T_21 = or(_res_hit_msbsLess_T_20, UInt<2>(0h3))
node _res_hit_msbsLess_T_22 = not(_res_hit_msbsLess_T_21)
node _res_hit_msbsLess_T_23 = shr(_res_hit_msbsLess_T_22, 3)
node res_hit_msbsLess_3 = lt(_res_hit_msbsLess_T_18, _res_hit_msbsLess_T_23)
node _res_hit_msbsEqual_T_21 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_22 = shl(io.pmp[6].addr, 2)
node _res_hit_msbsEqual_T_23 = not(_res_hit_msbsEqual_T_22)
node _res_hit_msbsEqual_T_24 = or(_res_hit_msbsEqual_T_23, UInt<2>(0h3))
node _res_hit_msbsEqual_T_25 = not(_res_hit_msbsEqual_T_24)
node _res_hit_msbsEqual_T_26 = shr(_res_hit_msbsEqual_T_25, 3)
node _res_hit_msbsEqual_T_27 = xor(_res_hit_msbsEqual_T_21, _res_hit_msbsEqual_T_26)
node res_hit_msbsEqual_3 = eq(_res_hit_msbsEqual_T_27, UInt<1>(0h0))
node _res_hit_lsbsLess_T_21 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_22 = or(_res_hit_lsbsLess_T_21, UInt<1>(0h0))
node _res_hit_lsbsLess_T_23 = shl(io.pmp[6].addr, 2)
node _res_hit_lsbsLess_T_24 = not(_res_hit_lsbsLess_T_23)
node _res_hit_lsbsLess_T_25 = or(_res_hit_lsbsLess_T_24, UInt<2>(0h3))
node _res_hit_lsbsLess_T_26 = not(_res_hit_lsbsLess_T_25)
node _res_hit_lsbsLess_T_27 = bits(_res_hit_lsbsLess_T_26, 2, 0)
node res_hit_lsbsLess_3 = lt(_res_hit_lsbsLess_T_22, _res_hit_lsbsLess_T_27)
node _res_hit_T_22 = and(res_hit_msbsEqual_3, res_hit_lsbsLess_3)
node _res_hit_T_23 = or(res_hit_msbsLess_3, _res_hit_T_22)
node _res_hit_T_24 = and(_res_hit_T_21, _res_hit_T_23)
node _res_hit_T_25 = and(_res_hit_T_15, _res_hit_T_24)
node res_hit_1 = mux(_res_hit_T_13, _res_hit_T_14, _res_hit_T_25)
node _res_ignore_T_1 = eq(io.pmp[6].cfg.l, UInt<1>(0h0))
node res_ignore_1 = and(default, _res_ignore_T_1)
node _res_aligned_lsbMask_T_2 = dshl(UInt<3>(0h7), io.size)
node _res_aligned_lsbMask_T_3 = bits(_res_aligned_lsbMask_T_2, 2, 0)
node res_aligned_lsbMask_1 = not(_res_aligned_lsbMask_T_3)
node _res_aligned_straddlesLowerBound_T_17 = shr(io.addr, 3)
node _res_aligned_straddlesLowerBound_T_18 = shl(io.pmp[5].addr, 2)
node _res_aligned_straddlesLowerBound_T_19 = not(_res_aligned_straddlesLowerBound_T_18)
node _res_aligned_straddlesLowerBound_T_20 = or(_res_aligned_straddlesLowerBound_T_19, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_21 = not(_res_aligned_straddlesLowerBound_T_20)
node _res_aligned_straddlesLowerBound_T_22 = shr(_res_aligned_straddlesLowerBound_T_21, 3)
node _res_aligned_straddlesLowerBound_T_23 = xor(_res_aligned_straddlesLowerBound_T_17, _res_aligned_straddlesLowerBound_T_22)
node _res_aligned_straddlesLowerBound_T_24 = eq(_res_aligned_straddlesLowerBound_T_23, UInt<1>(0h0))
node _res_aligned_straddlesLowerBound_T_25 = shl(io.pmp[5].addr, 2)
node _res_aligned_straddlesLowerBound_T_26 = not(_res_aligned_straddlesLowerBound_T_25)
node _res_aligned_straddlesLowerBound_T_27 = or(_res_aligned_straddlesLowerBound_T_26, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_28 = not(_res_aligned_straddlesLowerBound_T_27)
node _res_aligned_straddlesLowerBound_T_29 = bits(_res_aligned_straddlesLowerBound_T_28, 2, 0)
node _res_aligned_straddlesLowerBound_T_30 = bits(io.addr, 2, 0)
node _res_aligned_straddlesLowerBound_T_31 = not(_res_aligned_straddlesLowerBound_T_30)
node _res_aligned_straddlesLowerBound_T_32 = and(_res_aligned_straddlesLowerBound_T_29, _res_aligned_straddlesLowerBound_T_31)
node _res_aligned_straddlesLowerBound_T_33 = neq(_res_aligned_straddlesLowerBound_T_32, UInt<1>(0h0))
node res_aligned_straddlesLowerBound_1 = and(_res_aligned_straddlesLowerBound_T_24, _res_aligned_straddlesLowerBound_T_33)
node _res_aligned_straddlesUpperBound_T_17 = shr(io.addr, 3)
node _res_aligned_straddlesUpperBound_T_18 = shl(io.pmp[6].addr, 2)
node _res_aligned_straddlesUpperBound_T_19 = not(_res_aligned_straddlesUpperBound_T_18)
node _res_aligned_straddlesUpperBound_T_20 = or(_res_aligned_straddlesUpperBound_T_19, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_21 = not(_res_aligned_straddlesUpperBound_T_20)
node _res_aligned_straddlesUpperBound_T_22 = shr(_res_aligned_straddlesUpperBound_T_21, 3)
node _res_aligned_straddlesUpperBound_T_23 = xor(_res_aligned_straddlesUpperBound_T_17, _res_aligned_straddlesUpperBound_T_22)
node _res_aligned_straddlesUpperBound_T_24 = eq(_res_aligned_straddlesUpperBound_T_23, UInt<1>(0h0))
node _res_aligned_straddlesUpperBound_T_25 = shl(io.pmp[6].addr, 2)
node _res_aligned_straddlesUpperBound_T_26 = not(_res_aligned_straddlesUpperBound_T_25)
node _res_aligned_straddlesUpperBound_T_27 = or(_res_aligned_straddlesUpperBound_T_26, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_28 = not(_res_aligned_straddlesUpperBound_T_27)
node _res_aligned_straddlesUpperBound_T_29 = bits(_res_aligned_straddlesUpperBound_T_28, 2, 0)
node _res_aligned_straddlesUpperBound_T_30 = bits(io.addr, 2, 0)
node _res_aligned_straddlesUpperBound_T_31 = or(_res_aligned_straddlesUpperBound_T_30, res_aligned_lsbMask_1)
node _res_aligned_straddlesUpperBound_T_32 = and(_res_aligned_straddlesUpperBound_T_29, _res_aligned_straddlesUpperBound_T_31)
node _res_aligned_straddlesUpperBound_T_33 = neq(_res_aligned_straddlesUpperBound_T_32, UInt<1>(0h0))
node res_aligned_straddlesUpperBound_1 = and(_res_aligned_straddlesUpperBound_T_24, _res_aligned_straddlesUpperBound_T_33)
node _res_aligned_rangeAligned_T_1 = or(res_aligned_straddlesLowerBound_1, res_aligned_straddlesUpperBound_1)
node res_aligned_rangeAligned_1 = eq(_res_aligned_rangeAligned_T_1, UInt<1>(0h0))
node _res_aligned_pow2Aligned_T_3 = bits(io.pmp[6].mask, 2, 0)
node _res_aligned_pow2Aligned_T_4 = not(_res_aligned_pow2Aligned_T_3)
node _res_aligned_pow2Aligned_T_5 = and(res_aligned_lsbMask_1, _res_aligned_pow2Aligned_T_4)
node res_aligned_pow2Aligned_1 = eq(_res_aligned_pow2Aligned_T_5, UInt<1>(0h0))
node _res_aligned_T_1 = bits(io.pmp[6].cfg.a, 1, 1)
node res_aligned_1 = mux(_res_aligned_T_1, res_aligned_pow2Aligned_1, res_aligned_rangeAligned_1)
node _res_T_45 = eq(io.pmp[6].cfg.a, UInt<1>(0h0))
node _res_T_46 = eq(io.pmp[6].cfg.a, UInt<1>(0h1))
node _res_T_47 = eq(io.pmp[6].cfg.a, UInt<2>(0h2))
node _res_T_48 = eq(io.pmp[6].cfg.a, UInt<2>(0h3))
node _res_T_49 = eq(io.pmp[6].cfg.l, UInt<1>(0h1))
node res_hi_6 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w)
node _res_T_50 = cat(res_hi_6, io.pmp[6].cfg.r)
node _res_T_51 = eq(_res_T_50, UInt<1>(0h0))
node res_hi_7 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w)
node _res_T_52 = cat(res_hi_7, io.pmp[6].cfg.r)
node _res_T_53 = eq(_res_T_52, UInt<1>(0h1))
node res_hi_8 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w)
node _res_T_54 = cat(res_hi_8, io.pmp[6].cfg.r)
node _res_T_55 = eq(_res_T_54, UInt<2>(0h3))
node res_hi_9 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w)
node _res_T_56 = cat(res_hi_9, io.pmp[6].cfg.r)
node _res_T_57 = eq(_res_T_56, UInt<3>(0h4))
node res_hi_10 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w)
node _res_T_58 = cat(res_hi_10, io.pmp[6].cfg.r)
node _res_T_59 = eq(_res_T_58, UInt<3>(0h5))
node res_hi_11 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w)
node _res_T_60 = cat(res_hi_11, io.pmp[6].cfg.r)
node _res_T_61 = eq(_res_T_60, UInt<3>(0h7))
node _res_T_62 = eq(res_ignore_1, UInt<1>(0h0))
node _res_T_63 = and(_res_T_62, res_hit_1)
node _res_T_64 = and(_res_T_63, res_aligned_1)
node _res_T_65 = eq(io.pmp[6].cfg.a, UInt<1>(0h1))
node _res_T_66 = and(_res_T_64, _res_T_65)
node _res_T_67 = and(io.pmp[6].cfg.l, res_hit_1)
node _res_T_68 = and(_res_T_67, res_aligned_1)
node _res_T_69 = eq(io.pmp[6].cfg.a, UInt<1>(0h1))
node _res_T_70 = and(_res_T_68, _res_T_69)
node _res_T_71 = eq(res_ignore_1, UInt<1>(0h0))
node _res_T_72 = and(_res_T_71, res_hit_1)
node _res_T_73 = and(_res_T_72, res_aligned_1)
node _res_T_74 = eq(io.pmp[6].cfg.a, UInt<2>(0h2))
node _res_T_75 = and(_res_T_73, _res_T_74)
node _res_T_76 = and(io.pmp[6].cfg.l, res_hit_1)
node _res_T_77 = and(_res_T_76, res_aligned_1)
node _res_T_78 = eq(io.pmp[6].cfg.a, UInt<2>(0h2))
node _res_T_79 = and(_res_T_77, _res_T_78)
node _res_T_80 = eq(res_ignore_1, UInt<1>(0h0))
node _res_T_81 = and(_res_T_80, res_hit_1)
node _res_T_82 = and(_res_T_81, res_aligned_1)
node _res_T_83 = eq(io.pmp[6].cfg.a, UInt<2>(0h3))
node _res_T_84 = and(_res_T_82, _res_T_83)
node _res_T_85 = and(io.pmp[6].cfg.l, res_hit_1)
node _res_T_86 = and(_res_T_85, res_aligned_1)
node _res_T_87 = eq(io.pmp[6].cfg.a, UInt<2>(0h3))
node _res_T_88 = and(_res_T_86, _res_T_87)
wire res_cur_1 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_1, io.pmp[6]
node _res_cur_cfg_r_T_2 = or(io.pmp[6].cfg.r, res_ignore_1)
node _res_cur_cfg_r_T_3 = and(res_aligned_1, _res_cur_cfg_r_T_2)
connect res_cur_1.cfg.r, _res_cur_cfg_r_T_3
node _res_cur_cfg_w_T_2 = or(io.pmp[6].cfg.w, res_ignore_1)
node _res_cur_cfg_w_T_3 = and(res_aligned_1, _res_cur_cfg_w_T_2)
connect res_cur_1.cfg.w, _res_cur_cfg_w_T_3
node _res_cur_cfg_x_T_2 = or(io.pmp[6].cfg.x, res_ignore_1)
node _res_cur_cfg_x_T_3 = and(res_aligned_1, _res_cur_cfg_x_T_2)
connect res_cur_1.cfg.x, _res_cur_cfg_x_T_3
node _res_T_89 = mux(res_hit_1, res_cur_1, _res_T_44)
node _res_hit_T_26 = bits(io.pmp[5].cfg.a, 1, 1)
node _res_hit_lsbMask_T_6 = dshl(UInt<3>(0h7), io.size)
node _res_hit_lsbMask_T_7 = bits(_res_hit_lsbMask_T_6, 2, 0)
node _res_hit_lsbMask_T_8 = not(_res_hit_lsbMask_T_7)
node res_hit_lsbMask_2 = or(io.pmp[5].mask, _res_hit_lsbMask_T_8)
node _res_hit_msbMatch_T_20 = shr(io.addr, 3)
node _res_hit_msbMatch_T_21 = shl(io.pmp[5].addr, 2)
node _res_hit_msbMatch_T_22 = not(_res_hit_msbMatch_T_21)
node _res_hit_msbMatch_T_23 = or(_res_hit_msbMatch_T_22, UInt<2>(0h3))
node _res_hit_msbMatch_T_24 = not(_res_hit_msbMatch_T_23)
node _res_hit_msbMatch_T_25 = shr(_res_hit_msbMatch_T_24, 3)
node _res_hit_msbMatch_T_26 = shr(io.pmp[5].mask, 3)
node _res_hit_msbMatch_T_27 = xor(_res_hit_msbMatch_T_20, _res_hit_msbMatch_T_25)
node _res_hit_msbMatch_T_28 = not(_res_hit_msbMatch_T_26)
node _res_hit_msbMatch_T_29 = and(_res_hit_msbMatch_T_27, _res_hit_msbMatch_T_28)
node res_hit_msbMatch_2 = eq(_res_hit_msbMatch_T_29, UInt<1>(0h0))
node _res_hit_lsbMatch_T_20 = bits(io.addr, 2, 0)
node _res_hit_lsbMatch_T_21 = shl(io.pmp[5].addr, 2)
node _res_hit_lsbMatch_T_22 = not(_res_hit_lsbMatch_T_21)
node _res_hit_lsbMatch_T_23 = or(_res_hit_lsbMatch_T_22, UInt<2>(0h3))
node _res_hit_lsbMatch_T_24 = not(_res_hit_lsbMatch_T_23)
node _res_hit_lsbMatch_T_25 = bits(_res_hit_lsbMatch_T_24, 2, 0)
node _res_hit_lsbMatch_T_26 = bits(res_hit_lsbMask_2, 2, 0)
node _res_hit_lsbMatch_T_27 = xor(_res_hit_lsbMatch_T_20, _res_hit_lsbMatch_T_25)
node _res_hit_lsbMatch_T_28 = not(_res_hit_lsbMatch_T_26)
node _res_hit_lsbMatch_T_29 = and(_res_hit_lsbMatch_T_27, _res_hit_lsbMatch_T_28)
node res_hit_lsbMatch_2 = eq(_res_hit_lsbMatch_T_29, UInt<1>(0h0))
node _res_hit_T_27 = and(res_hit_msbMatch_2, res_hit_lsbMatch_2)
node _res_hit_T_28 = bits(io.pmp[5].cfg.a, 0, 0)
node _res_hit_T_29 = dshl(UInt<3>(0h7), io.size)
node _res_hit_T_30 = bits(_res_hit_T_29, 2, 0)
node _res_hit_T_31 = not(_res_hit_T_30)
node _res_hit_msbsLess_T_24 = shr(io.addr, 3)
node _res_hit_msbsLess_T_25 = shl(io.pmp[4].addr, 2)
node _res_hit_msbsLess_T_26 = not(_res_hit_msbsLess_T_25)
node _res_hit_msbsLess_T_27 = or(_res_hit_msbsLess_T_26, UInt<2>(0h3))
node _res_hit_msbsLess_T_28 = not(_res_hit_msbsLess_T_27)
node _res_hit_msbsLess_T_29 = shr(_res_hit_msbsLess_T_28, 3)
node res_hit_msbsLess_4 = lt(_res_hit_msbsLess_T_24, _res_hit_msbsLess_T_29)
node _res_hit_msbsEqual_T_28 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_29 = shl(io.pmp[4].addr, 2)
node _res_hit_msbsEqual_T_30 = not(_res_hit_msbsEqual_T_29)
node _res_hit_msbsEqual_T_31 = or(_res_hit_msbsEqual_T_30, UInt<2>(0h3))
node _res_hit_msbsEqual_T_32 = not(_res_hit_msbsEqual_T_31)
node _res_hit_msbsEqual_T_33 = shr(_res_hit_msbsEqual_T_32, 3)
node _res_hit_msbsEqual_T_34 = xor(_res_hit_msbsEqual_T_28, _res_hit_msbsEqual_T_33)
node res_hit_msbsEqual_4 = eq(_res_hit_msbsEqual_T_34, UInt<1>(0h0))
node _res_hit_lsbsLess_T_28 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_29 = or(_res_hit_lsbsLess_T_28, _res_hit_T_31)
node _res_hit_lsbsLess_T_30 = shl(io.pmp[4].addr, 2)
node _res_hit_lsbsLess_T_31 = not(_res_hit_lsbsLess_T_30)
node _res_hit_lsbsLess_T_32 = or(_res_hit_lsbsLess_T_31, UInt<2>(0h3))
node _res_hit_lsbsLess_T_33 = not(_res_hit_lsbsLess_T_32)
node _res_hit_lsbsLess_T_34 = bits(_res_hit_lsbsLess_T_33, 2, 0)
node res_hit_lsbsLess_4 = lt(_res_hit_lsbsLess_T_29, _res_hit_lsbsLess_T_34)
node _res_hit_T_32 = and(res_hit_msbsEqual_4, res_hit_lsbsLess_4)
node _res_hit_T_33 = or(res_hit_msbsLess_4, _res_hit_T_32)
node _res_hit_T_34 = eq(_res_hit_T_33, UInt<1>(0h0))
node _res_hit_msbsLess_T_30 = shr(io.addr, 3)
node _res_hit_msbsLess_T_31 = shl(io.pmp[5].addr, 2)
node _res_hit_msbsLess_T_32 = not(_res_hit_msbsLess_T_31)
node _res_hit_msbsLess_T_33 = or(_res_hit_msbsLess_T_32, UInt<2>(0h3))
node _res_hit_msbsLess_T_34 = not(_res_hit_msbsLess_T_33)
node _res_hit_msbsLess_T_35 = shr(_res_hit_msbsLess_T_34, 3)
node res_hit_msbsLess_5 = lt(_res_hit_msbsLess_T_30, _res_hit_msbsLess_T_35)
node _res_hit_msbsEqual_T_35 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_36 = shl(io.pmp[5].addr, 2)
node _res_hit_msbsEqual_T_37 = not(_res_hit_msbsEqual_T_36)
node _res_hit_msbsEqual_T_38 = or(_res_hit_msbsEqual_T_37, UInt<2>(0h3))
node _res_hit_msbsEqual_T_39 = not(_res_hit_msbsEqual_T_38)
node _res_hit_msbsEqual_T_40 = shr(_res_hit_msbsEqual_T_39, 3)
node _res_hit_msbsEqual_T_41 = xor(_res_hit_msbsEqual_T_35, _res_hit_msbsEqual_T_40)
node res_hit_msbsEqual_5 = eq(_res_hit_msbsEqual_T_41, UInt<1>(0h0))
node _res_hit_lsbsLess_T_35 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_36 = or(_res_hit_lsbsLess_T_35, UInt<1>(0h0))
node _res_hit_lsbsLess_T_37 = shl(io.pmp[5].addr, 2)
node _res_hit_lsbsLess_T_38 = not(_res_hit_lsbsLess_T_37)
node _res_hit_lsbsLess_T_39 = or(_res_hit_lsbsLess_T_38, UInt<2>(0h3))
node _res_hit_lsbsLess_T_40 = not(_res_hit_lsbsLess_T_39)
node _res_hit_lsbsLess_T_41 = bits(_res_hit_lsbsLess_T_40, 2, 0)
node res_hit_lsbsLess_5 = lt(_res_hit_lsbsLess_T_36, _res_hit_lsbsLess_T_41)
node _res_hit_T_35 = and(res_hit_msbsEqual_5, res_hit_lsbsLess_5)
node _res_hit_T_36 = or(res_hit_msbsLess_5, _res_hit_T_35)
node _res_hit_T_37 = and(_res_hit_T_34, _res_hit_T_36)
node _res_hit_T_38 = and(_res_hit_T_28, _res_hit_T_37)
node res_hit_2 = mux(_res_hit_T_26, _res_hit_T_27, _res_hit_T_38)
node _res_ignore_T_2 = eq(io.pmp[5].cfg.l, UInt<1>(0h0))
node res_ignore_2 = and(default, _res_ignore_T_2)
node _res_aligned_lsbMask_T_4 = dshl(UInt<3>(0h7), io.size)
node _res_aligned_lsbMask_T_5 = bits(_res_aligned_lsbMask_T_4, 2, 0)
node res_aligned_lsbMask_2 = not(_res_aligned_lsbMask_T_5)
node _res_aligned_straddlesLowerBound_T_34 = shr(io.addr, 3)
node _res_aligned_straddlesLowerBound_T_35 = shl(io.pmp[4].addr, 2)
node _res_aligned_straddlesLowerBound_T_36 = not(_res_aligned_straddlesLowerBound_T_35)
node _res_aligned_straddlesLowerBound_T_37 = or(_res_aligned_straddlesLowerBound_T_36, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_38 = not(_res_aligned_straddlesLowerBound_T_37)
node _res_aligned_straddlesLowerBound_T_39 = shr(_res_aligned_straddlesLowerBound_T_38, 3)
node _res_aligned_straddlesLowerBound_T_40 = xor(_res_aligned_straddlesLowerBound_T_34, _res_aligned_straddlesLowerBound_T_39)
node _res_aligned_straddlesLowerBound_T_41 = eq(_res_aligned_straddlesLowerBound_T_40, UInt<1>(0h0))
node _res_aligned_straddlesLowerBound_T_42 = shl(io.pmp[4].addr, 2)
node _res_aligned_straddlesLowerBound_T_43 = not(_res_aligned_straddlesLowerBound_T_42)
node _res_aligned_straddlesLowerBound_T_44 = or(_res_aligned_straddlesLowerBound_T_43, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_45 = not(_res_aligned_straddlesLowerBound_T_44)
node _res_aligned_straddlesLowerBound_T_46 = bits(_res_aligned_straddlesLowerBound_T_45, 2, 0)
node _res_aligned_straddlesLowerBound_T_47 = bits(io.addr, 2, 0)
node _res_aligned_straddlesLowerBound_T_48 = not(_res_aligned_straddlesLowerBound_T_47)
node _res_aligned_straddlesLowerBound_T_49 = and(_res_aligned_straddlesLowerBound_T_46, _res_aligned_straddlesLowerBound_T_48)
node _res_aligned_straddlesLowerBound_T_50 = neq(_res_aligned_straddlesLowerBound_T_49, UInt<1>(0h0))
node res_aligned_straddlesLowerBound_2 = and(_res_aligned_straddlesLowerBound_T_41, _res_aligned_straddlesLowerBound_T_50)
node _res_aligned_straddlesUpperBound_T_34 = shr(io.addr, 3)
node _res_aligned_straddlesUpperBound_T_35 = shl(io.pmp[5].addr, 2)
node _res_aligned_straddlesUpperBound_T_36 = not(_res_aligned_straddlesUpperBound_T_35)
node _res_aligned_straddlesUpperBound_T_37 = or(_res_aligned_straddlesUpperBound_T_36, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_38 = not(_res_aligned_straddlesUpperBound_T_37)
node _res_aligned_straddlesUpperBound_T_39 = shr(_res_aligned_straddlesUpperBound_T_38, 3)
node _res_aligned_straddlesUpperBound_T_40 = xor(_res_aligned_straddlesUpperBound_T_34, _res_aligned_straddlesUpperBound_T_39)
node _res_aligned_straddlesUpperBound_T_41 = eq(_res_aligned_straddlesUpperBound_T_40, UInt<1>(0h0))
node _res_aligned_straddlesUpperBound_T_42 = shl(io.pmp[5].addr, 2)
node _res_aligned_straddlesUpperBound_T_43 = not(_res_aligned_straddlesUpperBound_T_42)
node _res_aligned_straddlesUpperBound_T_44 = or(_res_aligned_straddlesUpperBound_T_43, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_45 = not(_res_aligned_straddlesUpperBound_T_44)
node _res_aligned_straddlesUpperBound_T_46 = bits(_res_aligned_straddlesUpperBound_T_45, 2, 0)
node _res_aligned_straddlesUpperBound_T_47 = bits(io.addr, 2, 0)
node _res_aligned_straddlesUpperBound_T_48 = or(_res_aligned_straddlesUpperBound_T_47, res_aligned_lsbMask_2)
node _res_aligned_straddlesUpperBound_T_49 = and(_res_aligned_straddlesUpperBound_T_46, _res_aligned_straddlesUpperBound_T_48)
node _res_aligned_straddlesUpperBound_T_50 = neq(_res_aligned_straddlesUpperBound_T_49, UInt<1>(0h0))
node res_aligned_straddlesUpperBound_2 = and(_res_aligned_straddlesUpperBound_T_41, _res_aligned_straddlesUpperBound_T_50)
node _res_aligned_rangeAligned_T_2 = or(res_aligned_straddlesLowerBound_2, res_aligned_straddlesUpperBound_2)
node res_aligned_rangeAligned_2 = eq(_res_aligned_rangeAligned_T_2, UInt<1>(0h0))
node _res_aligned_pow2Aligned_T_6 = bits(io.pmp[5].mask, 2, 0)
node _res_aligned_pow2Aligned_T_7 = not(_res_aligned_pow2Aligned_T_6)
node _res_aligned_pow2Aligned_T_8 = and(res_aligned_lsbMask_2, _res_aligned_pow2Aligned_T_7)
node res_aligned_pow2Aligned_2 = eq(_res_aligned_pow2Aligned_T_8, UInt<1>(0h0))
node _res_aligned_T_2 = bits(io.pmp[5].cfg.a, 1, 1)
node res_aligned_2 = mux(_res_aligned_T_2, res_aligned_pow2Aligned_2, res_aligned_rangeAligned_2)
node _res_T_90 = eq(io.pmp[5].cfg.a, UInt<1>(0h0))
node _res_T_91 = eq(io.pmp[5].cfg.a, UInt<1>(0h1))
node _res_T_92 = eq(io.pmp[5].cfg.a, UInt<2>(0h2))
node _res_T_93 = eq(io.pmp[5].cfg.a, UInt<2>(0h3))
node _res_T_94 = eq(io.pmp[5].cfg.l, UInt<1>(0h1))
node res_hi_12 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w)
node _res_T_95 = cat(res_hi_12, io.pmp[5].cfg.r)
node _res_T_96 = eq(_res_T_95, UInt<1>(0h0))
node res_hi_13 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w)
node _res_T_97 = cat(res_hi_13, io.pmp[5].cfg.r)
node _res_T_98 = eq(_res_T_97, UInt<1>(0h1))
node res_hi_14 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w)
node _res_T_99 = cat(res_hi_14, io.pmp[5].cfg.r)
node _res_T_100 = eq(_res_T_99, UInt<2>(0h3))
node res_hi_15 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w)
node _res_T_101 = cat(res_hi_15, io.pmp[5].cfg.r)
node _res_T_102 = eq(_res_T_101, UInt<3>(0h4))
node res_hi_16 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w)
node _res_T_103 = cat(res_hi_16, io.pmp[5].cfg.r)
node _res_T_104 = eq(_res_T_103, UInt<3>(0h5))
node res_hi_17 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w)
node _res_T_105 = cat(res_hi_17, io.pmp[5].cfg.r)
node _res_T_106 = eq(_res_T_105, UInt<3>(0h7))
node _res_T_107 = eq(res_ignore_2, UInt<1>(0h0))
node _res_T_108 = and(_res_T_107, res_hit_2)
node _res_T_109 = and(_res_T_108, res_aligned_2)
node _res_T_110 = eq(io.pmp[5].cfg.a, UInt<1>(0h1))
node _res_T_111 = and(_res_T_109, _res_T_110)
node _res_T_112 = and(io.pmp[5].cfg.l, res_hit_2)
node _res_T_113 = and(_res_T_112, res_aligned_2)
node _res_T_114 = eq(io.pmp[5].cfg.a, UInt<1>(0h1))
node _res_T_115 = and(_res_T_113, _res_T_114)
node _res_T_116 = eq(res_ignore_2, UInt<1>(0h0))
node _res_T_117 = and(_res_T_116, res_hit_2)
node _res_T_118 = and(_res_T_117, res_aligned_2)
node _res_T_119 = eq(io.pmp[5].cfg.a, UInt<2>(0h2))
node _res_T_120 = and(_res_T_118, _res_T_119)
node _res_T_121 = and(io.pmp[5].cfg.l, res_hit_2)
node _res_T_122 = and(_res_T_121, res_aligned_2)
node _res_T_123 = eq(io.pmp[5].cfg.a, UInt<2>(0h2))
node _res_T_124 = and(_res_T_122, _res_T_123)
node _res_T_125 = eq(res_ignore_2, UInt<1>(0h0))
node _res_T_126 = and(_res_T_125, res_hit_2)
node _res_T_127 = and(_res_T_126, res_aligned_2)
node _res_T_128 = eq(io.pmp[5].cfg.a, UInt<2>(0h3))
node _res_T_129 = and(_res_T_127, _res_T_128)
node _res_T_130 = and(io.pmp[5].cfg.l, res_hit_2)
node _res_T_131 = and(_res_T_130, res_aligned_2)
node _res_T_132 = eq(io.pmp[5].cfg.a, UInt<2>(0h3))
node _res_T_133 = and(_res_T_131, _res_T_132)
wire res_cur_2 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_2, io.pmp[5]
node _res_cur_cfg_r_T_4 = or(io.pmp[5].cfg.r, res_ignore_2)
node _res_cur_cfg_r_T_5 = and(res_aligned_2, _res_cur_cfg_r_T_4)
connect res_cur_2.cfg.r, _res_cur_cfg_r_T_5
node _res_cur_cfg_w_T_4 = or(io.pmp[5].cfg.w, res_ignore_2)
node _res_cur_cfg_w_T_5 = and(res_aligned_2, _res_cur_cfg_w_T_4)
connect res_cur_2.cfg.w, _res_cur_cfg_w_T_5
node _res_cur_cfg_x_T_4 = or(io.pmp[5].cfg.x, res_ignore_2)
node _res_cur_cfg_x_T_5 = and(res_aligned_2, _res_cur_cfg_x_T_4)
connect res_cur_2.cfg.x, _res_cur_cfg_x_T_5
node _res_T_134 = mux(res_hit_2, res_cur_2, _res_T_89)
node _res_hit_T_39 = bits(io.pmp[4].cfg.a, 1, 1)
node _res_hit_lsbMask_T_9 = dshl(UInt<3>(0h7), io.size)
node _res_hit_lsbMask_T_10 = bits(_res_hit_lsbMask_T_9, 2, 0)
node _res_hit_lsbMask_T_11 = not(_res_hit_lsbMask_T_10)
node res_hit_lsbMask_3 = or(io.pmp[4].mask, _res_hit_lsbMask_T_11)
node _res_hit_msbMatch_T_30 = shr(io.addr, 3)
node _res_hit_msbMatch_T_31 = shl(io.pmp[4].addr, 2)
node _res_hit_msbMatch_T_32 = not(_res_hit_msbMatch_T_31)
node _res_hit_msbMatch_T_33 = or(_res_hit_msbMatch_T_32, UInt<2>(0h3))
node _res_hit_msbMatch_T_34 = not(_res_hit_msbMatch_T_33)
node _res_hit_msbMatch_T_35 = shr(_res_hit_msbMatch_T_34, 3)
node _res_hit_msbMatch_T_36 = shr(io.pmp[4].mask, 3)
node _res_hit_msbMatch_T_37 = xor(_res_hit_msbMatch_T_30, _res_hit_msbMatch_T_35)
node _res_hit_msbMatch_T_38 = not(_res_hit_msbMatch_T_36)
node _res_hit_msbMatch_T_39 = and(_res_hit_msbMatch_T_37, _res_hit_msbMatch_T_38)
node res_hit_msbMatch_3 = eq(_res_hit_msbMatch_T_39, UInt<1>(0h0))
node _res_hit_lsbMatch_T_30 = bits(io.addr, 2, 0)
node _res_hit_lsbMatch_T_31 = shl(io.pmp[4].addr, 2)
node _res_hit_lsbMatch_T_32 = not(_res_hit_lsbMatch_T_31)
node _res_hit_lsbMatch_T_33 = or(_res_hit_lsbMatch_T_32, UInt<2>(0h3))
node _res_hit_lsbMatch_T_34 = not(_res_hit_lsbMatch_T_33)
node _res_hit_lsbMatch_T_35 = bits(_res_hit_lsbMatch_T_34, 2, 0)
node _res_hit_lsbMatch_T_36 = bits(res_hit_lsbMask_3, 2, 0)
node _res_hit_lsbMatch_T_37 = xor(_res_hit_lsbMatch_T_30, _res_hit_lsbMatch_T_35)
node _res_hit_lsbMatch_T_38 = not(_res_hit_lsbMatch_T_36)
node _res_hit_lsbMatch_T_39 = and(_res_hit_lsbMatch_T_37, _res_hit_lsbMatch_T_38)
node res_hit_lsbMatch_3 = eq(_res_hit_lsbMatch_T_39, UInt<1>(0h0))
node _res_hit_T_40 = and(res_hit_msbMatch_3, res_hit_lsbMatch_3)
node _res_hit_T_41 = bits(io.pmp[4].cfg.a, 0, 0)
node _res_hit_T_42 = dshl(UInt<3>(0h7), io.size)
node _res_hit_T_43 = bits(_res_hit_T_42, 2, 0)
node _res_hit_T_44 = not(_res_hit_T_43)
node _res_hit_msbsLess_T_36 = shr(io.addr, 3)
node _res_hit_msbsLess_T_37 = shl(io.pmp[3].addr, 2)
node _res_hit_msbsLess_T_38 = not(_res_hit_msbsLess_T_37)
node _res_hit_msbsLess_T_39 = or(_res_hit_msbsLess_T_38, UInt<2>(0h3))
node _res_hit_msbsLess_T_40 = not(_res_hit_msbsLess_T_39)
node _res_hit_msbsLess_T_41 = shr(_res_hit_msbsLess_T_40, 3)
node res_hit_msbsLess_6 = lt(_res_hit_msbsLess_T_36, _res_hit_msbsLess_T_41)
node _res_hit_msbsEqual_T_42 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_43 = shl(io.pmp[3].addr, 2)
node _res_hit_msbsEqual_T_44 = not(_res_hit_msbsEqual_T_43)
node _res_hit_msbsEqual_T_45 = or(_res_hit_msbsEqual_T_44, UInt<2>(0h3))
node _res_hit_msbsEqual_T_46 = not(_res_hit_msbsEqual_T_45)
node _res_hit_msbsEqual_T_47 = shr(_res_hit_msbsEqual_T_46, 3)
node _res_hit_msbsEqual_T_48 = xor(_res_hit_msbsEqual_T_42, _res_hit_msbsEqual_T_47)
node res_hit_msbsEqual_6 = eq(_res_hit_msbsEqual_T_48, UInt<1>(0h0))
node _res_hit_lsbsLess_T_42 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_43 = or(_res_hit_lsbsLess_T_42, _res_hit_T_44)
node _res_hit_lsbsLess_T_44 = shl(io.pmp[3].addr, 2)
node _res_hit_lsbsLess_T_45 = not(_res_hit_lsbsLess_T_44)
node _res_hit_lsbsLess_T_46 = or(_res_hit_lsbsLess_T_45, UInt<2>(0h3))
node _res_hit_lsbsLess_T_47 = not(_res_hit_lsbsLess_T_46)
node _res_hit_lsbsLess_T_48 = bits(_res_hit_lsbsLess_T_47, 2, 0)
node res_hit_lsbsLess_6 = lt(_res_hit_lsbsLess_T_43, _res_hit_lsbsLess_T_48)
node _res_hit_T_45 = and(res_hit_msbsEqual_6, res_hit_lsbsLess_6)
node _res_hit_T_46 = or(res_hit_msbsLess_6, _res_hit_T_45)
node _res_hit_T_47 = eq(_res_hit_T_46, UInt<1>(0h0))
node _res_hit_msbsLess_T_42 = shr(io.addr, 3)
node _res_hit_msbsLess_T_43 = shl(io.pmp[4].addr, 2)
node _res_hit_msbsLess_T_44 = not(_res_hit_msbsLess_T_43)
node _res_hit_msbsLess_T_45 = or(_res_hit_msbsLess_T_44, UInt<2>(0h3))
node _res_hit_msbsLess_T_46 = not(_res_hit_msbsLess_T_45)
node _res_hit_msbsLess_T_47 = shr(_res_hit_msbsLess_T_46, 3)
node res_hit_msbsLess_7 = lt(_res_hit_msbsLess_T_42, _res_hit_msbsLess_T_47)
node _res_hit_msbsEqual_T_49 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_50 = shl(io.pmp[4].addr, 2)
node _res_hit_msbsEqual_T_51 = not(_res_hit_msbsEqual_T_50)
node _res_hit_msbsEqual_T_52 = or(_res_hit_msbsEqual_T_51, UInt<2>(0h3))
node _res_hit_msbsEqual_T_53 = not(_res_hit_msbsEqual_T_52)
node _res_hit_msbsEqual_T_54 = shr(_res_hit_msbsEqual_T_53, 3)
node _res_hit_msbsEqual_T_55 = xor(_res_hit_msbsEqual_T_49, _res_hit_msbsEqual_T_54)
node res_hit_msbsEqual_7 = eq(_res_hit_msbsEqual_T_55, UInt<1>(0h0))
node _res_hit_lsbsLess_T_49 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_50 = or(_res_hit_lsbsLess_T_49, UInt<1>(0h0))
node _res_hit_lsbsLess_T_51 = shl(io.pmp[4].addr, 2)
node _res_hit_lsbsLess_T_52 = not(_res_hit_lsbsLess_T_51)
node _res_hit_lsbsLess_T_53 = or(_res_hit_lsbsLess_T_52, UInt<2>(0h3))
node _res_hit_lsbsLess_T_54 = not(_res_hit_lsbsLess_T_53)
node _res_hit_lsbsLess_T_55 = bits(_res_hit_lsbsLess_T_54, 2, 0)
node res_hit_lsbsLess_7 = lt(_res_hit_lsbsLess_T_50, _res_hit_lsbsLess_T_55)
node _res_hit_T_48 = and(res_hit_msbsEqual_7, res_hit_lsbsLess_7)
node _res_hit_T_49 = or(res_hit_msbsLess_7, _res_hit_T_48)
node _res_hit_T_50 = and(_res_hit_T_47, _res_hit_T_49)
node _res_hit_T_51 = and(_res_hit_T_41, _res_hit_T_50)
node res_hit_3 = mux(_res_hit_T_39, _res_hit_T_40, _res_hit_T_51)
node _res_ignore_T_3 = eq(io.pmp[4].cfg.l, UInt<1>(0h0))
node res_ignore_3 = and(default, _res_ignore_T_3)
node _res_aligned_lsbMask_T_6 = dshl(UInt<3>(0h7), io.size)
node _res_aligned_lsbMask_T_7 = bits(_res_aligned_lsbMask_T_6, 2, 0)
node res_aligned_lsbMask_3 = not(_res_aligned_lsbMask_T_7)
node _res_aligned_straddlesLowerBound_T_51 = shr(io.addr, 3)
node _res_aligned_straddlesLowerBound_T_52 = shl(io.pmp[3].addr, 2)
node _res_aligned_straddlesLowerBound_T_53 = not(_res_aligned_straddlesLowerBound_T_52)
node _res_aligned_straddlesLowerBound_T_54 = or(_res_aligned_straddlesLowerBound_T_53, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_55 = not(_res_aligned_straddlesLowerBound_T_54)
node _res_aligned_straddlesLowerBound_T_56 = shr(_res_aligned_straddlesLowerBound_T_55, 3)
node _res_aligned_straddlesLowerBound_T_57 = xor(_res_aligned_straddlesLowerBound_T_51, _res_aligned_straddlesLowerBound_T_56)
node _res_aligned_straddlesLowerBound_T_58 = eq(_res_aligned_straddlesLowerBound_T_57, UInt<1>(0h0))
node _res_aligned_straddlesLowerBound_T_59 = shl(io.pmp[3].addr, 2)
node _res_aligned_straddlesLowerBound_T_60 = not(_res_aligned_straddlesLowerBound_T_59)
node _res_aligned_straddlesLowerBound_T_61 = or(_res_aligned_straddlesLowerBound_T_60, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_62 = not(_res_aligned_straddlesLowerBound_T_61)
node _res_aligned_straddlesLowerBound_T_63 = bits(_res_aligned_straddlesLowerBound_T_62, 2, 0)
node _res_aligned_straddlesLowerBound_T_64 = bits(io.addr, 2, 0)
node _res_aligned_straddlesLowerBound_T_65 = not(_res_aligned_straddlesLowerBound_T_64)
node _res_aligned_straddlesLowerBound_T_66 = and(_res_aligned_straddlesLowerBound_T_63, _res_aligned_straddlesLowerBound_T_65)
node _res_aligned_straddlesLowerBound_T_67 = neq(_res_aligned_straddlesLowerBound_T_66, UInt<1>(0h0))
node res_aligned_straddlesLowerBound_3 = and(_res_aligned_straddlesLowerBound_T_58, _res_aligned_straddlesLowerBound_T_67)
node _res_aligned_straddlesUpperBound_T_51 = shr(io.addr, 3)
node _res_aligned_straddlesUpperBound_T_52 = shl(io.pmp[4].addr, 2)
node _res_aligned_straddlesUpperBound_T_53 = not(_res_aligned_straddlesUpperBound_T_52)
node _res_aligned_straddlesUpperBound_T_54 = or(_res_aligned_straddlesUpperBound_T_53, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_55 = not(_res_aligned_straddlesUpperBound_T_54)
node _res_aligned_straddlesUpperBound_T_56 = shr(_res_aligned_straddlesUpperBound_T_55, 3)
node _res_aligned_straddlesUpperBound_T_57 = xor(_res_aligned_straddlesUpperBound_T_51, _res_aligned_straddlesUpperBound_T_56)
node _res_aligned_straddlesUpperBound_T_58 = eq(_res_aligned_straddlesUpperBound_T_57, UInt<1>(0h0))
node _res_aligned_straddlesUpperBound_T_59 = shl(io.pmp[4].addr, 2)
node _res_aligned_straddlesUpperBound_T_60 = not(_res_aligned_straddlesUpperBound_T_59)
node _res_aligned_straddlesUpperBound_T_61 = or(_res_aligned_straddlesUpperBound_T_60, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_62 = not(_res_aligned_straddlesUpperBound_T_61)
node _res_aligned_straddlesUpperBound_T_63 = bits(_res_aligned_straddlesUpperBound_T_62, 2, 0)
node _res_aligned_straddlesUpperBound_T_64 = bits(io.addr, 2, 0)
node _res_aligned_straddlesUpperBound_T_65 = or(_res_aligned_straddlesUpperBound_T_64, res_aligned_lsbMask_3)
node _res_aligned_straddlesUpperBound_T_66 = and(_res_aligned_straddlesUpperBound_T_63, _res_aligned_straddlesUpperBound_T_65)
node _res_aligned_straddlesUpperBound_T_67 = neq(_res_aligned_straddlesUpperBound_T_66, UInt<1>(0h0))
node res_aligned_straddlesUpperBound_3 = and(_res_aligned_straddlesUpperBound_T_58, _res_aligned_straddlesUpperBound_T_67)
node _res_aligned_rangeAligned_T_3 = or(res_aligned_straddlesLowerBound_3, res_aligned_straddlesUpperBound_3)
node res_aligned_rangeAligned_3 = eq(_res_aligned_rangeAligned_T_3, UInt<1>(0h0))
node _res_aligned_pow2Aligned_T_9 = bits(io.pmp[4].mask, 2, 0)
node _res_aligned_pow2Aligned_T_10 = not(_res_aligned_pow2Aligned_T_9)
node _res_aligned_pow2Aligned_T_11 = and(res_aligned_lsbMask_3, _res_aligned_pow2Aligned_T_10)
node res_aligned_pow2Aligned_3 = eq(_res_aligned_pow2Aligned_T_11, UInt<1>(0h0))
node _res_aligned_T_3 = bits(io.pmp[4].cfg.a, 1, 1)
node res_aligned_3 = mux(_res_aligned_T_3, res_aligned_pow2Aligned_3, res_aligned_rangeAligned_3)
node _res_T_135 = eq(io.pmp[4].cfg.a, UInt<1>(0h0))
node _res_T_136 = eq(io.pmp[4].cfg.a, UInt<1>(0h1))
node _res_T_137 = eq(io.pmp[4].cfg.a, UInt<2>(0h2))
node _res_T_138 = eq(io.pmp[4].cfg.a, UInt<2>(0h3))
node _res_T_139 = eq(io.pmp[4].cfg.l, UInt<1>(0h1))
node res_hi_18 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w)
node _res_T_140 = cat(res_hi_18, io.pmp[4].cfg.r)
node _res_T_141 = eq(_res_T_140, UInt<1>(0h0))
node res_hi_19 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w)
node _res_T_142 = cat(res_hi_19, io.pmp[4].cfg.r)
node _res_T_143 = eq(_res_T_142, UInt<1>(0h1))
node res_hi_20 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w)
node _res_T_144 = cat(res_hi_20, io.pmp[4].cfg.r)
node _res_T_145 = eq(_res_T_144, UInt<2>(0h3))
node res_hi_21 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w)
node _res_T_146 = cat(res_hi_21, io.pmp[4].cfg.r)
node _res_T_147 = eq(_res_T_146, UInt<3>(0h4))
node res_hi_22 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w)
node _res_T_148 = cat(res_hi_22, io.pmp[4].cfg.r)
node _res_T_149 = eq(_res_T_148, UInt<3>(0h5))
node res_hi_23 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w)
node _res_T_150 = cat(res_hi_23, io.pmp[4].cfg.r)
node _res_T_151 = eq(_res_T_150, UInt<3>(0h7))
node _res_T_152 = eq(res_ignore_3, UInt<1>(0h0))
node _res_T_153 = and(_res_T_152, res_hit_3)
node _res_T_154 = and(_res_T_153, res_aligned_3)
node _res_T_155 = eq(io.pmp[4].cfg.a, UInt<1>(0h1))
node _res_T_156 = and(_res_T_154, _res_T_155)
node _res_T_157 = and(io.pmp[4].cfg.l, res_hit_3)
node _res_T_158 = and(_res_T_157, res_aligned_3)
node _res_T_159 = eq(io.pmp[4].cfg.a, UInt<1>(0h1))
node _res_T_160 = and(_res_T_158, _res_T_159)
node _res_T_161 = eq(res_ignore_3, UInt<1>(0h0))
node _res_T_162 = and(_res_T_161, res_hit_3)
node _res_T_163 = and(_res_T_162, res_aligned_3)
node _res_T_164 = eq(io.pmp[4].cfg.a, UInt<2>(0h2))
node _res_T_165 = and(_res_T_163, _res_T_164)
node _res_T_166 = and(io.pmp[4].cfg.l, res_hit_3)
node _res_T_167 = and(_res_T_166, res_aligned_3)
node _res_T_168 = eq(io.pmp[4].cfg.a, UInt<2>(0h2))
node _res_T_169 = and(_res_T_167, _res_T_168)
node _res_T_170 = eq(res_ignore_3, UInt<1>(0h0))
node _res_T_171 = and(_res_T_170, res_hit_3)
node _res_T_172 = and(_res_T_171, res_aligned_3)
node _res_T_173 = eq(io.pmp[4].cfg.a, UInt<2>(0h3))
node _res_T_174 = and(_res_T_172, _res_T_173)
node _res_T_175 = and(io.pmp[4].cfg.l, res_hit_3)
node _res_T_176 = and(_res_T_175, res_aligned_3)
node _res_T_177 = eq(io.pmp[4].cfg.a, UInt<2>(0h3))
node _res_T_178 = and(_res_T_176, _res_T_177)
wire res_cur_3 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_3, io.pmp[4]
node _res_cur_cfg_r_T_6 = or(io.pmp[4].cfg.r, res_ignore_3)
node _res_cur_cfg_r_T_7 = and(res_aligned_3, _res_cur_cfg_r_T_6)
connect res_cur_3.cfg.r, _res_cur_cfg_r_T_7
node _res_cur_cfg_w_T_6 = or(io.pmp[4].cfg.w, res_ignore_3)
node _res_cur_cfg_w_T_7 = and(res_aligned_3, _res_cur_cfg_w_T_6)
connect res_cur_3.cfg.w, _res_cur_cfg_w_T_7
node _res_cur_cfg_x_T_6 = or(io.pmp[4].cfg.x, res_ignore_3)
node _res_cur_cfg_x_T_7 = and(res_aligned_3, _res_cur_cfg_x_T_6)
connect res_cur_3.cfg.x, _res_cur_cfg_x_T_7
node _res_T_179 = mux(res_hit_3, res_cur_3, _res_T_134)
node _res_hit_T_52 = bits(io.pmp[3].cfg.a, 1, 1)
node _res_hit_lsbMask_T_12 = dshl(UInt<3>(0h7), io.size)
node _res_hit_lsbMask_T_13 = bits(_res_hit_lsbMask_T_12, 2, 0)
node _res_hit_lsbMask_T_14 = not(_res_hit_lsbMask_T_13)
node res_hit_lsbMask_4 = or(io.pmp[3].mask, _res_hit_lsbMask_T_14)
node _res_hit_msbMatch_T_40 = shr(io.addr, 3)
node _res_hit_msbMatch_T_41 = shl(io.pmp[3].addr, 2)
node _res_hit_msbMatch_T_42 = not(_res_hit_msbMatch_T_41)
node _res_hit_msbMatch_T_43 = or(_res_hit_msbMatch_T_42, UInt<2>(0h3))
node _res_hit_msbMatch_T_44 = not(_res_hit_msbMatch_T_43)
node _res_hit_msbMatch_T_45 = shr(_res_hit_msbMatch_T_44, 3)
node _res_hit_msbMatch_T_46 = shr(io.pmp[3].mask, 3)
node _res_hit_msbMatch_T_47 = xor(_res_hit_msbMatch_T_40, _res_hit_msbMatch_T_45)
node _res_hit_msbMatch_T_48 = not(_res_hit_msbMatch_T_46)
node _res_hit_msbMatch_T_49 = and(_res_hit_msbMatch_T_47, _res_hit_msbMatch_T_48)
node res_hit_msbMatch_4 = eq(_res_hit_msbMatch_T_49, UInt<1>(0h0))
node _res_hit_lsbMatch_T_40 = bits(io.addr, 2, 0)
node _res_hit_lsbMatch_T_41 = shl(io.pmp[3].addr, 2)
node _res_hit_lsbMatch_T_42 = not(_res_hit_lsbMatch_T_41)
node _res_hit_lsbMatch_T_43 = or(_res_hit_lsbMatch_T_42, UInt<2>(0h3))
node _res_hit_lsbMatch_T_44 = not(_res_hit_lsbMatch_T_43)
node _res_hit_lsbMatch_T_45 = bits(_res_hit_lsbMatch_T_44, 2, 0)
node _res_hit_lsbMatch_T_46 = bits(res_hit_lsbMask_4, 2, 0)
node _res_hit_lsbMatch_T_47 = xor(_res_hit_lsbMatch_T_40, _res_hit_lsbMatch_T_45)
node _res_hit_lsbMatch_T_48 = not(_res_hit_lsbMatch_T_46)
node _res_hit_lsbMatch_T_49 = and(_res_hit_lsbMatch_T_47, _res_hit_lsbMatch_T_48)
node res_hit_lsbMatch_4 = eq(_res_hit_lsbMatch_T_49, UInt<1>(0h0))
node _res_hit_T_53 = and(res_hit_msbMatch_4, res_hit_lsbMatch_4)
node _res_hit_T_54 = bits(io.pmp[3].cfg.a, 0, 0)
node _res_hit_T_55 = dshl(UInt<3>(0h7), io.size)
node _res_hit_T_56 = bits(_res_hit_T_55, 2, 0)
node _res_hit_T_57 = not(_res_hit_T_56)
node _res_hit_msbsLess_T_48 = shr(io.addr, 3)
node _res_hit_msbsLess_T_49 = shl(io.pmp[2].addr, 2)
node _res_hit_msbsLess_T_50 = not(_res_hit_msbsLess_T_49)
node _res_hit_msbsLess_T_51 = or(_res_hit_msbsLess_T_50, UInt<2>(0h3))
node _res_hit_msbsLess_T_52 = not(_res_hit_msbsLess_T_51)
node _res_hit_msbsLess_T_53 = shr(_res_hit_msbsLess_T_52, 3)
node res_hit_msbsLess_8 = lt(_res_hit_msbsLess_T_48, _res_hit_msbsLess_T_53)
node _res_hit_msbsEqual_T_56 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_57 = shl(io.pmp[2].addr, 2)
node _res_hit_msbsEqual_T_58 = not(_res_hit_msbsEqual_T_57)
node _res_hit_msbsEqual_T_59 = or(_res_hit_msbsEqual_T_58, UInt<2>(0h3))
node _res_hit_msbsEqual_T_60 = not(_res_hit_msbsEqual_T_59)
node _res_hit_msbsEqual_T_61 = shr(_res_hit_msbsEqual_T_60, 3)
node _res_hit_msbsEqual_T_62 = xor(_res_hit_msbsEqual_T_56, _res_hit_msbsEqual_T_61)
node res_hit_msbsEqual_8 = eq(_res_hit_msbsEqual_T_62, UInt<1>(0h0))
node _res_hit_lsbsLess_T_56 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_57 = or(_res_hit_lsbsLess_T_56, _res_hit_T_57)
node _res_hit_lsbsLess_T_58 = shl(io.pmp[2].addr, 2)
node _res_hit_lsbsLess_T_59 = not(_res_hit_lsbsLess_T_58)
node _res_hit_lsbsLess_T_60 = or(_res_hit_lsbsLess_T_59, UInt<2>(0h3))
node _res_hit_lsbsLess_T_61 = not(_res_hit_lsbsLess_T_60)
node _res_hit_lsbsLess_T_62 = bits(_res_hit_lsbsLess_T_61, 2, 0)
node res_hit_lsbsLess_8 = lt(_res_hit_lsbsLess_T_57, _res_hit_lsbsLess_T_62)
node _res_hit_T_58 = and(res_hit_msbsEqual_8, res_hit_lsbsLess_8)
node _res_hit_T_59 = or(res_hit_msbsLess_8, _res_hit_T_58)
node _res_hit_T_60 = eq(_res_hit_T_59, UInt<1>(0h0))
node _res_hit_msbsLess_T_54 = shr(io.addr, 3)
node _res_hit_msbsLess_T_55 = shl(io.pmp[3].addr, 2)
node _res_hit_msbsLess_T_56 = not(_res_hit_msbsLess_T_55)
node _res_hit_msbsLess_T_57 = or(_res_hit_msbsLess_T_56, UInt<2>(0h3))
node _res_hit_msbsLess_T_58 = not(_res_hit_msbsLess_T_57)
node _res_hit_msbsLess_T_59 = shr(_res_hit_msbsLess_T_58, 3)
node res_hit_msbsLess_9 = lt(_res_hit_msbsLess_T_54, _res_hit_msbsLess_T_59)
node _res_hit_msbsEqual_T_63 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_64 = shl(io.pmp[3].addr, 2)
node _res_hit_msbsEqual_T_65 = not(_res_hit_msbsEqual_T_64)
node _res_hit_msbsEqual_T_66 = or(_res_hit_msbsEqual_T_65, UInt<2>(0h3))
node _res_hit_msbsEqual_T_67 = not(_res_hit_msbsEqual_T_66)
node _res_hit_msbsEqual_T_68 = shr(_res_hit_msbsEqual_T_67, 3)
node _res_hit_msbsEqual_T_69 = xor(_res_hit_msbsEqual_T_63, _res_hit_msbsEqual_T_68)
node res_hit_msbsEqual_9 = eq(_res_hit_msbsEqual_T_69, UInt<1>(0h0))
node _res_hit_lsbsLess_T_63 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_64 = or(_res_hit_lsbsLess_T_63, UInt<1>(0h0))
node _res_hit_lsbsLess_T_65 = shl(io.pmp[3].addr, 2)
node _res_hit_lsbsLess_T_66 = not(_res_hit_lsbsLess_T_65)
node _res_hit_lsbsLess_T_67 = or(_res_hit_lsbsLess_T_66, UInt<2>(0h3))
node _res_hit_lsbsLess_T_68 = not(_res_hit_lsbsLess_T_67)
node _res_hit_lsbsLess_T_69 = bits(_res_hit_lsbsLess_T_68, 2, 0)
node res_hit_lsbsLess_9 = lt(_res_hit_lsbsLess_T_64, _res_hit_lsbsLess_T_69)
node _res_hit_T_61 = and(res_hit_msbsEqual_9, res_hit_lsbsLess_9)
node _res_hit_T_62 = or(res_hit_msbsLess_9, _res_hit_T_61)
node _res_hit_T_63 = and(_res_hit_T_60, _res_hit_T_62)
node _res_hit_T_64 = and(_res_hit_T_54, _res_hit_T_63)
node res_hit_4 = mux(_res_hit_T_52, _res_hit_T_53, _res_hit_T_64)
node _res_ignore_T_4 = eq(io.pmp[3].cfg.l, UInt<1>(0h0))
node res_ignore_4 = and(default, _res_ignore_T_4)
node _res_aligned_lsbMask_T_8 = dshl(UInt<3>(0h7), io.size)
node _res_aligned_lsbMask_T_9 = bits(_res_aligned_lsbMask_T_8, 2, 0)
node res_aligned_lsbMask_4 = not(_res_aligned_lsbMask_T_9)
node _res_aligned_straddlesLowerBound_T_68 = shr(io.addr, 3)
node _res_aligned_straddlesLowerBound_T_69 = shl(io.pmp[2].addr, 2)
node _res_aligned_straddlesLowerBound_T_70 = not(_res_aligned_straddlesLowerBound_T_69)
node _res_aligned_straddlesLowerBound_T_71 = or(_res_aligned_straddlesLowerBound_T_70, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_72 = not(_res_aligned_straddlesLowerBound_T_71)
node _res_aligned_straddlesLowerBound_T_73 = shr(_res_aligned_straddlesLowerBound_T_72, 3)
node _res_aligned_straddlesLowerBound_T_74 = xor(_res_aligned_straddlesLowerBound_T_68, _res_aligned_straddlesLowerBound_T_73)
node _res_aligned_straddlesLowerBound_T_75 = eq(_res_aligned_straddlesLowerBound_T_74, UInt<1>(0h0))
node _res_aligned_straddlesLowerBound_T_76 = shl(io.pmp[2].addr, 2)
node _res_aligned_straddlesLowerBound_T_77 = not(_res_aligned_straddlesLowerBound_T_76)
node _res_aligned_straddlesLowerBound_T_78 = or(_res_aligned_straddlesLowerBound_T_77, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_79 = not(_res_aligned_straddlesLowerBound_T_78)
node _res_aligned_straddlesLowerBound_T_80 = bits(_res_aligned_straddlesLowerBound_T_79, 2, 0)
node _res_aligned_straddlesLowerBound_T_81 = bits(io.addr, 2, 0)
node _res_aligned_straddlesLowerBound_T_82 = not(_res_aligned_straddlesLowerBound_T_81)
node _res_aligned_straddlesLowerBound_T_83 = and(_res_aligned_straddlesLowerBound_T_80, _res_aligned_straddlesLowerBound_T_82)
node _res_aligned_straddlesLowerBound_T_84 = neq(_res_aligned_straddlesLowerBound_T_83, UInt<1>(0h0))
node res_aligned_straddlesLowerBound_4 = and(_res_aligned_straddlesLowerBound_T_75, _res_aligned_straddlesLowerBound_T_84)
node _res_aligned_straddlesUpperBound_T_68 = shr(io.addr, 3)
node _res_aligned_straddlesUpperBound_T_69 = shl(io.pmp[3].addr, 2)
node _res_aligned_straddlesUpperBound_T_70 = not(_res_aligned_straddlesUpperBound_T_69)
node _res_aligned_straddlesUpperBound_T_71 = or(_res_aligned_straddlesUpperBound_T_70, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_72 = not(_res_aligned_straddlesUpperBound_T_71)
node _res_aligned_straddlesUpperBound_T_73 = shr(_res_aligned_straddlesUpperBound_T_72, 3)
node _res_aligned_straddlesUpperBound_T_74 = xor(_res_aligned_straddlesUpperBound_T_68, _res_aligned_straddlesUpperBound_T_73)
node _res_aligned_straddlesUpperBound_T_75 = eq(_res_aligned_straddlesUpperBound_T_74, UInt<1>(0h0))
node _res_aligned_straddlesUpperBound_T_76 = shl(io.pmp[3].addr, 2)
node _res_aligned_straddlesUpperBound_T_77 = not(_res_aligned_straddlesUpperBound_T_76)
node _res_aligned_straddlesUpperBound_T_78 = or(_res_aligned_straddlesUpperBound_T_77, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_79 = not(_res_aligned_straddlesUpperBound_T_78)
node _res_aligned_straddlesUpperBound_T_80 = bits(_res_aligned_straddlesUpperBound_T_79, 2, 0)
node _res_aligned_straddlesUpperBound_T_81 = bits(io.addr, 2, 0)
node _res_aligned_straddlesUpperBound_T_82 = or(_res_aligned_straddlesUpperBound_T_81, res_aligned_lsbMask_4)
node _res_aligned_straddlesUpperBound_T_83 = and(_res_aligned_straddlesUpperBound_T_80, _res_aligned_straddlesUpperBound_T_82)
node _res_aligned_straddlesUpperBound_T_84 = neq(_res_aligned_straddlesUpperBound_T_83, UInt<1>(0h0))
node res_aligned_straddlesUpperBound_4 = and(_res_aligned_straddlesUpperBound_T_75, _res_aligned_straddlesUpperBound_T_84)
node _res_aligned_rangeAligned_T_4 = or(res_aligned_straddlesLowerBound_4, res_aligned_straddlesUpperBound_4)
node res_aligned_rangeAligned_4 = eq(_res_aligned_rangeAligned_T_4, UInt<1>(0h0))
node _res_aligned_pow2Aligned_T_12 = bits(io.pmp[3].mask, 2, 0)
node _res_aligned_pow2Aligned_T_13 = not(_res_aligned_pow2Aligned_T_12)
node _res_aligned_pow2Aligned_T_14 = and(res_aligned_lsbMask_4, _res_aligned_pow2Aligned_T_13)
node res_aligned_pow2Aligned_4 = eq(_res_aligned_pow2Aligned_T_14, UInt<1>(0h0))
node _res_aligned_T_4 = bits(io.pmp[3].cfg.a, 1, 1)
node res_aligned_4 = mux(_res_aligned_T_4, res_aligned_pow2Aligned_4, res_aligned_rangeAligned_4)
node _res_T_180 = eq(io.pmp[3].cfg.a, UInt<1>(0h0))
node _res_T_181 = eq(io.pmp[3].cfg.a, UInt<1>(0h1))
node _res_T_182 = eq(io.pmp[3].cfg.a, UInt<2>(0h2))
node _res_T_183 = eq(io.pmp[3].cfg.a, UInt<2>(0h3))
node _res_T_184 = eq(io.pmp[3].cfg.l, UInt<1>(0h1))
node res_hi_24 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w)
node _res_T_185 = cat(res_hi_24, io.pmp[3].cfg.r)
node _res_T_186 = eq(_res_T_185, UInt<1>(0h0))
node res_hi_25 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w)
node _res_T_187 = cat(res_hi_25, io.pmp[3].cfg.r)
node _res_T_188 = eq(_res_T_187, UInt<1>(0h1))
node res_hi_26 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w)
node _res_T_189 = cat(res_hi_26, io.pmp[3].cfg.r)
node _res_T_190 = eq(_res_T_189, UInt<2>(0h3))
node res_hi_27 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w)
node _res_T_191 = cat(res_hi_27, io.pmp[3].cfg.r)
node _res_T_192 = eq(_res_T_191, UInt<3>(0h4))
node res_hi_28 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w)
node _res_T_193 = cat(res_hi_28, io.pmp[3].cfg.r)
node _res_T_194 = eq(_res_T_193, UInt<3>(0h5))
node res_hi_29 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w)
node _res_T_195 = cat(res_hi_29, io.pmp[3].cfg.r)
node _res_T_196 = eq(_res_T_195, UInt<3>(0h7))
node _res_T_197 = eq(res_ignore_4, UInt<1>(0h0))
node _res_T_198 = and(_res_T_197, res_hit_4)
node _res_T_199 = and(_res_T_198, res_aligned_4)
node _res_T_200 = eq(io.pmp[3].cfg.a, UInt<1>(0h1))
node _res_T_201 = and(_res_T_199, _res_T_200)
node _res_T_202 = and(io.pmp[3].cfg.l, res_hit_4)
node _res_T_203 = and(_res_T_202, res_aligned_4)
node _res_T_204 = eq(io.pmp[3].cfg.a, UInt<1>(0h1))
node _res_T_205 = and(_res_T_203, _res_T_204)
node _res_T_206 = eq(res_ignore_4, UInt<1>(0h0))
node _res_T_207 = and(_res_T_206, res_hit_4)
node _res_T_208 = and(_res_T_207, res_aligned_4)
node _res_T_209 = eq(io.pmp[3].cfg.a, UInt<2>(0h2))
node _res_T_210 = and(_res_T_208, _res_T_209)
node _res_T_211 = and(io.pmp[3].cfg.l, res_hit_4)
node _res_T_212 = and(_res_T_211, res_aligned_4)
node _res_T_213 = eq(io.pmp[3].cfg.a, UInt<2>(0h2))
node _res_T_214 = and(_res_T_212, _res_T_213)
node _res_T_215 = eq(res_ignore_4, UInt<1>(0h0))
node _res_T_216 = and(_res_T_215, res_hit_4)
node _res_T_217 = and(_res_T_216, res_aligned_4)
node _res_T_218 = eq(io.pmp[3].cfg.a, UInt<2>(0h3))
node _res_T_219 = and(_res_T_217, _res_T_218)
node _res_T_220 = and(io.pmp[3].cfg.l, res_hit_4)
node _res_T_221 = and(_res_T_220, res_aligned_4)
node _res_T_222 = eq(io.pmp[3].cfg.a, UInt<2>(0h3))
node _res_T_223 = and(_res_T_221, _res_T_222)
wire res_cur_4 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_4, io.pmp[3]
node _res_cur_cfg_r_T_8 = or(io.pmp[3].cfg.r, res_ignore_4)
node _res_cur_cfg_r_T_9 = and(res_aligned_4, _res_cur_cfg_r_T_8)
connect res_cur_4.cfg.r, _res_cur_cfg_r_T_9
node _res_cur_cfg_w_T_8 = or(io.pmp[3].cfg.w, res_ignore_4)
node _res_cur_cfg_w_T_9 = and(res_aligned_4, _res_cur_cfg_w_T_8)
connect res_cur_4.cfg.w, _res_cur_cfg_w_T_9
node _res_cur_cfg_x_T_8 = or(io.pmp[3].cfg.x, res_ignore_4)
node _res_cur_cfg_x_T_9 = and(res_aligned_4, _res_cur_cfg_x_T_8)
connect res_cur_4.cfg.x, _res_cur_cfg_x_T_9
node _res_T_224 = mux(res_hit_4, res_cur_4, _res_T_179)
node _res_hit_T_65 = bits(io.pmp[2].cfg.a, 1, 1)
node _res_hit_lsbMask_T_15 = dshl(UInt<3>(0h7), io.size)
node _res_hit_lsbMask_T_16 = bits(_res_hit_lsbMask_T_15, 2, 0)
node _res_hit_lsbMask_T_17 = not(_res_hit_lsbMask_T_16)
node res_hit_lsbMask_5 = or(io.pmp[2].mask, _res_hit_lsbMask_T_17)
node _res_hit_msbMatch_T_50 = shr(io.addr, 3)
node _res_hit_msbMatch_T_51 = shl(io.pmp[2].addr, 2)
node _res_hit_msbMatch_T_52 = not(_res_hit_msbMatch_T_51)
node _res_hit_msbMatch_T_53 = or(_res_hit_msbMatch_T_52, UInt<2>(0h3))
node _res_hit_msbMatch_T_54 = not(_res_hit_msbMatch_T_53)
node _res_hit_msbMatch_T_55 = shr(_res_hit_msbMatch_T_54, 3)
node _res_hit_msbMatch_T_56 = shr(io.pmp[2].mask, 3)
node _res_hit_msbMatch_T_57 = xor(_res_hit_msbMatch_T_50, _res_hit_msbMatch_T_55)
node _res_hit_msbMatch_T_58 = not(_res_hit_msbMatch_T_56)
node _res_hit_msbMatch_T_59 = and(_res_hit_msbMatch_T_57, _res_hit_msbMatch_T_58)
node res_hit_msbMatch_5 = eq(_res_hit_msbMatch_T_59, UInt<1>(0h0))
node _res_hit_lsbMatch_T_50 = bits(io.addr, 2, 0)
node _res_hit_lsbMatch_T_51 = shl(io.pmp[2].addr, 2)
node _res_hit_lsbMatch_T_52 = not(_res_hit_lsbMatch_T_51)
node _res_hit_lsbMatch_T_53 = or(_res_hit_lsbMatch_T_52, UInt<2>(0h3))
node _res_hit_lsbMatch_T_54 = not(_res_hit_lsbMatch_T_53)
node _res_hit_lsbMatch_T_55 = bits(_res_hit_lsbMatch_T_54, 2, 0)
node _res_hit_lsbMatch_T_56 = bits(res_hit_lsbMask_5, 2, 0)
node _res_hit_lsbMatch_T_57 = xor(_res_hit_lsbMatch_T_50, _res_hit_lsbMatch_T_55)
node _res_hit_lsbMatch_T_58 = not(_res_hit_lsbMatch_T_56)
node _res_hit_lsbMatch_T_59 = and(_res_hit_lsbMatch_T_57, _res_hit_lsbMatch_T_58)
node res_hit_lsbMatch_5 = eq(_res_hit_lsbMatch_T_59, UInt<1>(0h0))
node _res_hit_T_66 = and(res_hit_msbMatch_5, res_hit_lsbMatch_5)
node _res_hit_T_67 = bits(io.pmp[2].cfg.a, 0, 0)
node _res_hit_T_68 = dshl(UInt<3>(0h7), io.size)
node _res_hit_T_69 = bits(_res_hit_T_68, 2, 0)
node _res_hit_T_70 = not(_res_hit_T_69)
node _res_hit_msbsLess_T_60 = shr(io.addr, 3)
node _res_hit_msbsLess_T_61 = shl(io.pmp[1].addr, 2)
node _res_hit_msbsLess_T_62 = not(_res_hit_msbsLess_T_61)
node _res_hit_msbsLess_T_63 = or(_res_hit_msbsLess_T_62, UInt<2>(0h3))
node _res_hit_msbsLess_T_64 = not(_res_hit_msbsLess_T_63)
node _res_hit_msbsLess_T_65 = shr(_res_hit_msbsLess_T_64, 3)
node res_hit_msbsLess_10 = lt(_res_hit_msbsLess_T_60, _res_hit_msbsLess_T_65)
node _res_hit_msbsEqual_T_70 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_71 = shl(io.pmp[1].addr, 2)
node _res_hit_msbsEqual_T_72 = not(_res_hit_msbsEqual_T_71)
node _res_hit_msbsEqual_T_73 = or(_res_hit_msbsEqual_T_72, UInt<2>(0h3))
node _res_hit_msbsEqual_T_74 = not(_res_hit_msbsEqual_T_73)
node _res_hit_msbsEqual_T_75 = shr(_res_hit_msbsEqual_T_74, 3)
node _res_hit_msbsEqual_T_76 = xor(_res_hit_msbsEqual_T_70, _res_hit_msbsEqual_T_75)
node res_hit_msbsEqual_10 = eq(_res_hit_msbsEqual_T_76, UInt<1>(0h0))
node _res_hit_lsbsLess_T_70 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_71 = or(_res_hit_lsbsLess_T_70, _res_hit_T_70)
node _res_hit_lsbsLess_T_72 = shl(io.pmp[1].addr, 2)
node _res_hit_lsbsLess_T_73 = not(_res_hit_lsbsLess_T_72)
node _res_hit_lsbsLess_T_74 = or(_res_hit_lsbsLess_T_73, UInt<2>(0h3))
node _res_hit_lsbsLess_T_75 = not(_res_hit_lsbsLess_T_74)
node _res_hit_lsbsLess_T_76 = bits(_res_hit_lsbsLess_T_75, 2, 0)
node res_hit_lsbsLess_10 = lt(_res_hit_lsbsLess_T_71, _res_hit_lsbsLess_T_76)
node _res_hit_T_71 = and(res_hit_msbsEqual_10, res_hit_lsbsLess_10)
node _res_hit_T_72 = or(res_hit_msbsLess_10, _res_hit_T_71)
node _res_hit_T_73 = eq(_res_hit_T_72, UInt<1>(0h0))
node _res_hit_msbsLess_T_66 = shr(io.addr, 3)
node _res_hit_msbsLess_T_67 = shl(io.pmp[2].addr, 2)
node _res_hit_msbsLess_T_68 = not(_res_hit_msbsLess_T_67)
node _res_hit_msbsLess_T_69 = or(_res_hit_msbsLess_T_68, UInt<2>(0h3))
node _res_hit_msbsLess_T_70 = not(_res_hit_msbsLess_T_69)
node _res_hit_msbsLess_T_71 = shr(_res_hit_msbsLess_T_70, 3)
node res_hit_msbsLess_11 = lt(_res_hit_msbsLess_T_66, _res_hit_msbsLess_T_71)
node _res_hit_msbsEqual_T_77 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_78 = shl(io.pmp[2].addr, 2)
node _res_hit_msbsEqual_T_79 = not(_res_hit_msbsEqual_T_78)
node _res_hit_msbsEqual_T_80 = or(_res_hit_msbsEqual_T_79, UInt<2>(0h3))
node _res_hit_msbsEqual_T_81 = not(_res_hit_msbsEqual_T_80)
node _res_hit_msbsEqual_T_82 = shr(_res_hit_msbsEqual_T_81, 3)
node _res_hit_msbsEqual_T_83 = xor(_res_hit_msbsEqual_T_77, _res_hit_msbsEqual_T_82)
node res_hit_msbsEqual_11 = eq(_res_hit_msbsEqual_T_83, UInt<1>(0h0))
node _res_hit_lsbsLess_T_77 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_78 = or(_res_hit_lsbsLess_T_77, UInt<1>(0h0))
node _res_hit_lsbsLess_T_79 = shl(io.pmp[2].addr, 2)
node _res_hit_lsbsLess_T_80 = not(_res_hit_lsbsLess_T_79)
node _res_hit_lsbsLess_T_81 = or(_res_hit_lsbsLess_T_80, UInt<2>(0h3))
node _res_hit_lsbsLess_T_82 = not(_res_hit_lsbsLess_T_81)
node _res_hit_lsbsLess_T_83 = bits(_res_hit_lsbsLess_T_82, 2, 0)
node res_hit_lsbsLess_11 = lt(_res_hit_lsbsLess_T_78, _res_hit_lsbsLess_T_83)
node _res_hit_T_74 = and(res_hit_msbsEqual_11, res_hit_lsbsLess_11)
node _res_hit_T_75 = or(res_hit_msbsLess_11, _res_hit_T_74)
node _res_hit_T_76 = and(_res_hit_T_73, _res_hit_T_75)
node _res_hit_T_77 = and(_res_hit_T_67, _res_hit_T_76)
node res_hit_5 = mux(_res_hit_T_65, _res_hit_T_66, _res_hit_T_77)
node _res_ignore_T_5 = eq(io.pmp[2].cfg.l, UInt<1>(0h0))
node res_ignore_5 = and(default, _res_ignore_T_5)
node _res_aligned_lsbMask_T_10 = dshl(UInt<3>(0h7), io.size)
node _res_aligned_lsbMask_T_11 = bits(_res_aligned_lsbMask_T_10, 2, 0)
node res_aligned_lsbMask_5 = not(_res_aligned_lsbMask_T_11)
node _res_aligned_straddlesLowerBound_T_85 = shr(io.addr, 3)
node _res_aligned_straddlesLowerBound_T_86 = shl(io.pmp[1].addr, 2)
node _res_aligned_straddlesLowerBound_T_87 = not(_res_aligned_straddlesLowerBound_T_86)
node _res_aligned_straddlesLowerBound_T_88 = or(_res_aligned_straddlesLowerBound_T_87, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_89 = not(_res_aligned_straddlesLowerBound_T_88)
node _res_aligned_straddlesLowerBound_T_90 = shr(_res_aligned_straddlesLowerBound_T_89, 3)
node _res_aligned_straddlesLowerBound_T_91 = xor(_res_aligned_straddlesLowerBound_T_85, _res_aligned_straddlesLowerBound_T_90)
node _res_aligned_straddlesLowerBound_T_92 = eq(_res_aligned_straddlesLowerBound_T_91, UInt<1>(0h0))
node _res_aligned_straddlesLowerBound_T_93 = shl(io.pmp[1].addr, 2)
node _res_aligned_straddlesLowerBound_T_94 = not(_res_aligned_straddlesLowerBound_T_93)
node _res_aligned_straddlesLowerBound_T_95 = or(_res_aligned_straddlesLowerBound_T_94, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_96 = not(_res_aligned_straddlesLowerBound_T_95)
node _res_aligned_straddlesLowerBound_T_97 = bits(_res_aligned_straddlesLowerBound_T_96, 2, 0)
node _res_aligned_straddlesLowerBound_T_98 = bits(io.addr, 2, 0)
node _res_aligned_straddlesLowerBound_T_99 = not(_res_aligned_straddlesLowerBound_T_98)
node _res_aligned_straddlesLowerBound_T_100 = and(_res_aligned_straddlesLowerBound_T_97, _res_aligned_straddlesLowerBound_T_99)
node _res_aligned_straddlesLowerBound_T_101 = neq(_res_aligned_straddlesLowerBound_T_100, UInt<1>(0h0))
node res_aligned_straddlesLowerBound_5 = and(_res_aligned_straddlesLowerBound_T_92, _res_aligned_straddlesLowerBound_T_101)
node _res_aligned_straddlesUpperBound_T_85 = shr(io.addr, 3)
node _res_aligned_straddlesUpperBound_T_86 = shl(io.pmp[2].addr, 2)
node _res_aligned_straddlesUpperBound_T_87 = not(_res_aligned_straddlesUpperBound_T_86)
node _res_aligned_straddlesUpperBound_T_88 = or(_res_aligned_straddlesUpperBound_T_87, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_89 = not(_res_aligned_straddlesUpperBound_T_88)
node _res_aligned_straddlesUpperBound_T_90 = shr(_res_aligned_straddlesUpperBound_T_89, 3)
node _res_aligned_straddlesUpperBound_T_91 = xor(_res_aligned_straddlesUpperBound_T_85, _res_aligned_straddlesUpperBound_T_90)
node _res_aligned_straddlesUpperBound_T_92 = eq(_res_aligned_straddlesUpperBound_T_91, UInt<1>(0h0))
node _res_aligned_straddlesUpperBound_T_93 = shl(io.pmp[2].addr, 2)
node _res_aligned_straddlesUpperBound_T_94 = not(_res_aligned_straddlesUpperBound_T_93)
node _res_aligned_straddlesUpperBound_T_95 = or(_res_aligned_straddlesUpperBound_T_94, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_96 = not(_res_aligned_straddlesUpperBound_T_95)
node _res_aligned_straddlesUpperBound_T_97 = bits(_res_aligned_straddlesUpperBound_T_96, 2, 0)
node _res_aligned_straddlesUpperBound_T_98 = bits(io.addr, 2, 0)
node _res_aligned_straddlesUpperBound_T_99 = or(_res_aligned_straddlesUpperBound_T_98, res_aligned_lsbMask_5)
node _res_aligned_straddlesUpperBound_T_100 = and(_res_aligned_straddlesUpperBound_T_97, _res_aligned_straddlesUpperBound_T_99)
node _res_aligned_straddlesUpperBound_T_101 = neq(_res_aligned_straddlesUpperBound_T_100, UInt<1>(0h0))
node res_aligned_straddlesUpperBound_5 = and(_res_aligned_straddlesUpperBound_T_92, _res_aligned_straddlesUpperBound_T_101)
node _res_aligned_rangeAligned_T_5 = or(res_aligned_straddlesLowerBound_5, res_aligned_straddlesUpperBound_5)
node res_aligned_rangeAligned_5 = eq(_res_aligned_rangeAligned_T_5, UInt<1>(0h0))
node _res_aligned_pow2Aligned_T_15 = bits(io.pmp[2].mask, 2, 0)
node _res_aligned_pow2Aligned_T_16 = not(_res_aligned_pow2Aligned_T_15)
node _res_aligned_pow2Aligned_T_17 = and(res_aligned_lsbMask_5, _res_aligned_pow2Aligned_T_16)
node res_aligned_pow2Aligned_5 = eq(_res_aligned_pow2Aligned_T_17, UInt<1>(0h0))
node _res_aligned_T_5 = bits(io.pmp[2].cfg.a, 1, 1)
node res_aligned_5 = mux(_res_aligned_T_5, res_aligned_pow2Aligned_5, res_aligned_rangeAligned_5)
node _res_T_225 = eq(io.pmp[2].cfg.a, UInt<1>(0h0))
node _res_T_226 = eq(io.pmp[2].cfg.a, UInt<1>(0h1))
node _res_T_227 = eq(io.pmp[2].cfg.a, UInt<2>(0h2))
node _res_T_228 = eq(io.pmp[2].cfg.a, UInt<2>(0h3))
node _res_T_229 = eq(io.pmp[2].cfg.l, UInt<1>(0h1))
node res_hi_30 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w)
node _res_T_230 = cat(res_hi_30, io.pmp[2].cfg.r)
node _res_T_231 = eq(_res_T_230, UInt<1>(0h0))
node res_hi_31 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w)
node _res_T_232 = cat(res_hi_31, io.pmp[2].cfg.r)
node _res_T_233 = eq(_res_T_232, UInt<1>(0h1))
node res_hi_32 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w)
node _res_T_234 = cat(res_hi_32, io.pmp[2].cfg.r)
node _res_T_235 = eq(_res_T_234, UInt<2>(0h3))
node res_hi_33 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w)
node _res_T_236 = cat(res_hi_33, io.pmp[2].cfg.r)
node _res_T_237 = eq(_res_T_236, UInt<3>(0h4))
node res_hi_34 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w)
node _res_T_238 = cat(res_hi_34, io.pmp[2].cfg.r)
node _res_T_239 = eq(_res_T_238, UInt<3>(0h5))
node res_hi_35 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w)
node _res_T_240 = cat(res_hi_35, io.pmp[2].cfg.r)
node _res_T_241 = eq(_res_T_240, UInt<3>(0h7))
node _res_T_242 = eq(res_ignore_5, UInt<1>(0h0))
node _res_T_243 = and(_res_T_242, res_hit_5)
node _res_T_244 = and(_res_T_243, res_aligned_5)
node _res_T_245 = eq(io.pmp[2].cfg.a, UInt<1>(0h1))
node _res_T_246 = and(_res_T_244, _res_T_245)
node _res_T_247 = and(io.pmp[2].cfg.l, res_hit_5)
node _res_T_248 = and(_res_T_247, res_aligned_5)
node _res_T_249 = eq(io.pmp[2].cfg.a, UInt<1>(0h1))
node _res_T_250 = and(_res_T_248, _res_T_249)
node _res_T_251 = eq(res_ignore_5, UInt<1>(0h0))
node _res_T_252 = and(_res_T_251, res_hit_5)
node _res_T_253 = and(_res_T_252, res_aligned_5)
node _res_T_254 = eq(io.pmp[2].cfg.a, UInt<2>(0h2))
node _res_T_255 = and(_res_T_253, _res_T_254)
node _res_T_256 = and(io.pmp[2].cfg.l, res_hit_5)
node _res_T_257 = and(_res_T_256, res_aligned_5)
node _res_T_258 = eq(io.pmp[2].cfg.a, UInt<2>(0h2))
node _res_T_259 = and(_res_T_257, _res_T_258)
node _res_T_260 = eq(res_ignore_5, UInt<1>(0h0))
node _res_T_261 = and(_res_T_260, res_hit_5)
node _res_T_262 = and(_res_T_261, res_aligned_5)
node _res_T_263 = eq(io.pmp[2].cfg.a, UInt<2>(0h3))
node _res_T_264 = and(_res_T_262, _res_T_263)
node _res_T_265 = and(io.pmp[2].cfg.l, res_hit_5)
node _res_T_266 = and(_res_T_265, res_aligned_5)
node _res_T_267 = eq(io.pmp[2].cfg.a, UInt<2>(0h3))
node _res_T_268 = and(_res_T_266, _res_T_267)
wire res_cur_5 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_5, io.pmp[2]
node _res_cur_cfg_r_T_10 = or(io.pmp[2].cfg.r, res_ignore_5)
node _res_cur_cfg_r_T_11 = and(res_aligned_5, _res_cur_cfg_r_T_10)
connect res_cur_5.cfg.r, _res_cur_cfg_r_T_11
node _res_cur_cfg_w_T_10 = or(io.pmp[2].cfg.w, res_ignore_5)
node _res_cur_cfg_w_T_11 = and(res_aligned_5, _res_cur_cfg_w_T_10)
connect res_cur_5.cfg.w, _res_cur_cfg_w_T_11
node _res_cur_cfg_x_T_10 = or(io.pmp[2].cfg.x, res_ignore_5)
node _res_cur_cfg_x_T_11 = and(res_aligned_5, _res_cur_cfg_x_T_10)
connect res_cur_5.cfg.x, _res_cur_cfg_x_T_11
node _res_T_269 = mux(res_hit_5, res_cur_5, _res_T_224)
node _res_hit_T_78 = bits(io.pmp[1].cfg.a, 1, 1)
node _res_hit_lsbMask_T_18 = dshl(UInt<3>(0h7), io.size)
node _res_hit_lsbMask_T_19 = bits(_res_hit_lsbMask_T_18, 2, 0)
node _res_hit_lsbMask_T_20 = not(_res_hit_lsbMask_T_19)
node res_hit_lsbMask_6 = or(io.pmp[1].mask, _res_hit_lsbMask_T_20)
node _res_hit_msbMatch_T_60 = shr(io.addr, 3)
node _res_hit_msbMatch_T_61 = shl(io.pmp[1].addr, 2)
node _res_hit_msbMatch_T_62 = not(_res_hit_msbMatch_T_61)
node _res_hit_msbMatch_T_63 = or(_res_hit_msbMatch_T_62, UInt<2>(0h3))
node _res_hit_msbMatch_T_64 = not(_res_hit_msbMatch_T_63)
node _res_hit_msbMatch_T_65 = shr(_res_hit_msbMatch_T_64, 3)
node _res_hit_msbMatch_T_66 = shr(io.pmp[1].mask, 3)
node _res_hit_msbMatch_T_67 = xor(_res_hit_msbMatch_T_60, _res_hit_msbMatch_T_65)
node _res_hit_msbMatch_T_68 = not(_res_hit_msbMatch_T_66)
node _res_hit_msbMatch_T_69 = and(_res_hit_msbMatch_T_67, _res_hit_msbMatch_T_68)
node res_hit_msbMatch_6 = eq(_res_hit_msbMatch_T_69, UInt<1>(0h0))
node _res_hit_lsbMatch_T_60 = bits(io.addr, 2, 0)
node _res_hit_lsbMatch_T_61 = shl(io.pmp[1].addr, 2)
node _res_hit_lsbMatch_T_62 = not(_res_hit_lsbMatch_T_61)
node _res_hit_lsbMatch_T_63 = or(_res_hit_lsbMatch_T_62, UInt<2>(0h3))
node _res_hit_lsbMatch_T_64 = not(_res_hit_lsbMatch_T_63)
node _res_hit_lsbMatch_T_65 = bits(_res_hit_lsbMatch_T_64, 2, 0)
node _res_hit_lsbMatch_T_66 = bits(res_hit_lsbMask_6, 2, 0)
node _res_hit_lsbMatch_T_67 = xor(_res_hit_lsbMatch_T_60, _res_hit_lsbMatch_T_65)
node _res_hit_lsbMatch_T_68 = not(_res_hit_lsbMatch_T_66)
node _res_hit_lsbMatch_T_69 = and(_res_hit_lsbMatch_T_67, _res_hit_lsbMatch_T_68)
node res_hit_lsbMatch_6 = eq(_res_hit_lsbMatch_T_69, UInt<1>(0h0))
node _res_hit_T_79 = and(res_hit_msbMatch_6, res_hit_lsbMatch_6)
node _res_hit_T_80 = bits(io.pmp[1].cfg.a, 0, 0)
node _res_hit_T_81 = dshl(UInt<3>(0h7), io.size)
node _res_hit_T_82 = bits(_res_hit_T_81, 2, 0)
node _res_hit_T_83 = not(_res_hit_T_82)
node _res_hit_msbsLess_T_72 = shr(io.addr, 3)
node _res_hit_msbsLess_T_73 = shl(io.pmp[0].addr, 2)
node _res_hit_msbsLess_T_74 = not(_res_hit_msbsLess_T_73)
node _res_hit_msbsLess_T_75 = or(_res_hit_msbsLess_T_74, UInt<2>(0h3))
node _res_hit_msbsLess_T_76 = not(_res_hit_msbsLess_T_75)
node _res_hit_msbsLess_T_77 = shr(_res_hit_msbsLess_T_76, 3)
node res_hit_msbsLess_12 = lt(_res_hit_msbsLess_T_72, _res_hit_msbsLess_T_77)
node _res_hit_msbsEqual_T_84 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_85 = shl(io.pmp[0].addr, 2)
node _res_hit_msbsEqual_T_86 = not(_res_hit_msbsEqual_T_85)
node _res_hit_msbsEqual_T_87 = or(_res_hit_msbsEqual_T_86, UInt<2>(0h3))
node _res_hit_msbsEqual_T_88 = not(_res_hit_msbsEqual_T_87)
node _res_hit_msbsEqual_T_89 = shr(_res_hit_msbsEqual_T_88, 3)
node _res_hit_msbsEqual_T_90 = xor(_res_hit_msbsEqual_T_84, _res_hit_msbsEqual_T_89)
node res_hit_msbsEqual_12 = eq(_res_hit_msbsEqual_T_90, UInt<1>(0h0))
node _res_hit_lsbsLess_T_84 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_85 = or(_res_hit_lsbsLess_T_84, _res_hit_T_83)
node _res_hit_lsbsLess_T_86 = shl(io.pmp[0].addr, 2)
node _res_hit_lsbsLess_T_87 = not(_res_hit_lsbsLess_T_86)
node _res_hit_lsbsLess_T_88 = or(_res_hit_lsbsLess_T_87, UInt<2>(0h3))
node _res_hit_lsbsLess_T_89 = not(_res_hit_lsbsLess_T_88)
node _res_hit_lsbsLess_T_90 = bits(_res_hit_lsbsLess_T_89, 2, 0)
node res_hit_lsbsLess_12 = lt(_res_hit_lsbsLess_T_85, _res_hit_lsbsLess_T_90)
node _res_hit_T_84 = and(res_hit_msbsEqual_12, res_hit_lsbsLess_12)
node _res_hit_T_85 = or(res_hit_msbsLess_12, _res_hit_T_84)
node _res_hit_T_86 = eq(_res_hit_T_85, UInt<1>(0h0))
node _res_hit_msbsLess_T_78 = shr(io.addr, 3)
node _res_hit_msbsLess_T_79 = shl(io.pmp[1].addr, 2)
node _res_hit_msbsLess_T_80 = not(_res_hit_msbsLess_T_79)
node _res_hit_msbsLess_T_81 = or(_res_hit_msbsLess_T_80, UInt<2>(0h3))
node _res_hit_msbsLess_T_82 = not(_res_hit_msbsLess_T_81)
node _res_hit_msbsLess_T_83 = shr(_res_hit_msbsLess_T_82, 3)
node res_hit_msbsLess_13 = lt(_res_hit_msbsLess_T_78, _res_hit_msbsLess_T_83)
node _res_hit_msbsEqual_T_91 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_92 = shl(io.pmp[1].addr, 2)
node _res_hit_msbsEqual_T_93 = not(_res_hit_msbsEqual_T_92)
node _res_hit_msbsEqual_T_94 = or(_res_hit_msbsEqual_T_93, UInt<2>(0h3))
node _res_hit_msbsEqual_T_95 = not(_res_hit_msbsEqual_T_94)
node _res_hit_msbsEqual_T_96 = shr(_res_hit_msbsEqual_T_95, 3)
node _res_hit_msbsEqual_T_97 = xor(_res_hit_msbsEqual_T_91, _res_hit_msbsEqual_T_96)
node res_hit_msbsEqual_13 = eq(_res_hit_msbsEqual_T_97, UInt<1>(0h0))
node _res_hit_lsbsLess_T_91 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_92 = or(_res_hit_lsbsLess_T_91, UInt<1>(0h0))
node _res_hit_lsbsLess_T_93 = shl(io.pmp[1].addr, 2)
node _res_hit_lsbsLess_T_94 = not(_res_hit_lsbsLess_T_93)
node _res_hit_lsbsLess_T_95 = or(_res_hit_lsbsLess_T_94, UInt<2>(0h3))
node _res_hit_lsbsLess_T_96 = not(_res_hit_lsbsLess_T_95)
node _res_hit_lsbsLess_T_97 = bits(_res_hit_lsbsLess_T_96, 2, 0)
node res_hit_lsbsLess_13 = lt(_res_hit_lsbsLess_T_92, _res_hit_lsbsLess_T_97)
node _res_hit_T_87 = and(res_hit_msbsEqual_13, res_hit_lsbsLess_13)
node _res_hit_T_88 = or(res_hit_msbsLess_13, _res_hit_T_87)
node _res_hit_T_89 = and(_res_hit_T_86, _res_hit_T_88)
node _res_hit_T_90 = and(_res_hit_T_80, _res_hit_T_89)
node res_hit_6 = mux(_res_hit_T_78, _res_hit_T_79, _res_hit_T_90)
node _res_ignore_T_6 = eq(io.pmp[1].cfg.l, UInt<1>(0h0))
node res_ignore_6 = and(default, _res_ignore_T_6)
node _res_aligned_lsbMask_T_12 = dshl(UInt<3>(0h7), io.size)
node _res_aligned_lsbMask_T_13 = bits(_res_aligned_lsbMask_T_12, 2, 0)
node res_aligned_lsbMask_6 = not(_res_aligned_lsbMask_T_13)
node _res_aligned_straddlesLowerBound_T_102 = shr(io.addr, 3)
node _res_aligned_straddlesLowerBound_T_103 = shl(io.pmp[0].addr, 2)
node _res_aligned_straddlesLowerBound_T_104 = not(_res_aligned_straddlesLowerBound_T_103)
node _res_aligned_straddlesLowerBound_T_105 = or(_res_aligned_straddlesLowerBound_T_104, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_106 = not(_res_aligned_straddlesLowerBound_T_105)
node _res_aligned_straddlesLowerBound_T_107 = shr(_res_aligned_straddlesLowerBound_T_106, 3)
node _res_aligned_straddlesLowerBound_T_108 = xor(_res_aligned_straddlesLowerBound_T_102, _res_aligned_straddlesLowerBound_T_107)
node _res_aligned_straddlesLowerBound_T_109 = eq(_res_aligned_straddlesLowerBound_T_108, UInt<1>(0h0))
node _res_aligned_straddlesLowerBound_T_110 = shl(io.pmp[0].addr, 2)
node _res_aligned_straddlesLowerBound_T_111 = not(_res_aligned_straddlesLowerBound_T_110)
node _res_aligned_straddlesLowerBound_T_112 = or(_res_aligned_straddlesLowerBound_T_111, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_113 = not(_res_aligned_straddlesLowerBound_T_112)
node _res_aligned_straddlesLowerBound_T_114 = bits(_res_aligned_straddlesLowerBound_T_113, 2, 0)
node _res_aligned_straddlesLowerBound_T_115 = bits(io.addr, 2, 0)
node _res_aligned_straddlesLowerBound_T_116 = not(_res_aligned_straddlesLowerBound_T_115)
node _res_aligned_straddlesLowerBound_T_117 = and(_res_aligned_straddlesLowerBound_T_114, _res_aligned_straddlesLowerBound_T_116)
node _res_aligned_straddlesLowerBound_T_118 = neq(_res_aligned_straddlesLowerBound_T_117, UInt<1>(0h0))
node res_aligned_straddlesLowerBound_6 = and(_res_aligned_straddlesLowerBound_T_109, _res_aligned_straddlesLowerBound_T_118)
node _res_aligned_straddlesUpperBound_T_102 = shr(io.addr, 3)
node _res_aligned_straddlesUpperBound_T_103 = shl(io.pmp[1].addr, 2)
node _res_aligned_straddlesUpperBound_T_104 = not(_res_aligned_straddlesUpperBound_T_103)
node _res_aligned_straddlesUpperBound_T_105 = or(_res_aligned_straddlesUpperBound_T_104, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_106 = not(_res_aligned_straddlesUpperBound_T_105)
node _res_aligned_straddlesUpperBound_T_107 = shr(_res_aligned_straddlesUpperBound_T_106, 3)
node _res_aligned_straddlesUpperBound_T_108 = xor(_res_aligned_straddlesUpperBound_T_102, _res_aligned_straddlesUpperBound_T_107)
node _res_aligned_straddlesUpperBound_T_109 = eq(_res_aligned_straddlesUpperBound_T_108, UInt<1>(0h0))
node _res_aligned_straddlesUpperBound_T_110 = shl(io.pmp[1].addr, 2)
node _res_aligned_straddlesUpperBound_T_111 = not(_res_aligned_straddlesUpperBound_T_110)
node _res_aligned_straddlesUpperBound_T_112 = or(_res_aligned_straddlesUpperBound_T_111, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_113 = not(_res_aligned_straddlesUpperBound_T_112)
node _res_aligned_straddlesUpperBound_T_114 = bits(_res_aligned_straddlesUpperBound_T_113, 2, 0)
node _res_aligned_straddlesUpperBound_T_115 = bits(io.addr, 2, 0)
node _res_aligned_straddlesUpperBound_T_116 = or(_res_aligned_straddlesUpperBound_T_115, res_aligned_lsbMask_6)
node _res_aligned_straddlesUpperBound_T_117 = and(_res_aligned_straddlesUpperBound_T_114, _res_aligned_straddlesUpperBound_T_116)
node _res_aligned_straddlesUpperBound_T_118 = neq(_res_aligned_straddlesUpperBound_T_117, UInt<1>(0h0))
node res_aligned_straddlesUpperBound_6 = and(_res_aligned_straddlesUpperBound_T_109, _res_aligned_straddlesUpperBound_T_118)
node _res_aligned_rangeAligned_T_6 = or(res_aligned_straddlesLowerBound_6, res_aligned_straddlesUpperBound_6)
node res_aligned_rangeAligned_6 = eq(_res_aligned_rangeAligned_T_6, UInt<1>(0h0))
node _res_aligned_pow2Aligned_T_18 = bits(io.pmp[1].mask, 2, 0)
node _res_aligned_pow2Aligned_T_19 = not(_res_aligned_pow2Aligned_T_18)
node _res_aligned_pow2Aligned_T_20 = and(res_aligned_lsbMask_6, _res_aligned_pow2Aligned_T_19)
node res_aligned_pow2Aligned_6 = eq(_res_aligned_pow2Aligned_T_20, UInt<1>(0h0))
node _res_aligned_T_6 = bits(io.pmp[1].cfg.a, 1, 1)
node res_aligned_6 = mux(_res_aligned_T_6, res_aligned_pow2Aligned_6, res_aligned_rangeAligned_6)
node _res_T_270 = eq(io.pmp[1].cfg.a, UInt<1>(0h0))
node _res_T_271 = eq(io.pmp[1].cfg.a, UInt<1>(0h1))
node _res_T_272 = eq(io.pmp[1].cfg.a, UInt<2>(0h2))
node _res_T_273 = eq(io.pmp[1].cfg.a, UInt<2>(0h3))
node _res_T_274 = eq(io.pmp[1].cfg.l, UInt<1>(0h1))
node res_hi_36 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w)
node _res_T_275 = cat(res_hi_36, io.pmp[1].cfg.r)
node _res_T_276 = eq(_res_T_275, UInt<1>(0h0))
node res_hi_37 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w)
node _res_T_277 = cat(res_hi_37, io.pmp[1].cfg.r)
node _res_T_278 = eq(_res_T_277, UInt<1>(0h1))
node res_hi_38 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w)
node _res_T_279 = cat(res_hi_38, io.pmp[1].cfg.r)
node _res_T_280 = eq(_res_T_279, UInt<2>(0h3))
node res_hi_39 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w)
node _res_T_281 = cat(res_hi_39, io.pmp[1].cfg.r)
node _res_T_282 = eq(_res_T_281, UInt<3>(0h4))
node res_hi_40 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w)
node _res_T_283 = cat(res_hi_40, io.pmp[1].cfg.r)
node _res_T_284 = eq(_res_T_283, UInt<3>(0h5))
node res_hi_41 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w)
node _res_T_285 = cat(res_hi_41, io.pmp[1].cfg.r)
node _res_T_286 = eq(_res_T_285, UInt<3>(0h7))
node _res_T_287 = eq(res_ignore_6, UInt<1>(0h0))
node _res_T_288 = and(_res_T_287, res_hit_6)
node _res_T_289 = and(_res_T_288, res_aligned_6)
node _res_T_290 = eq(io.pmp[1].cfg.a, UInt<1>(0h1))
node _res_T_291 = and(_res_T_289, _res_T_290)
node _res_T_292 = and(io.pmp[1].cfg.l, res_hit_6)
node _res_T_293 = and(_res_T_292, res_aligned_6)
node _res_T_294 = eq(io.pmp[1].cfg.a, UInt<1>(0h1))
node _res_T_295 = and(_res_T_293, _res_T_294)
node _res_T_296 = eq(res_ignore_6, UInt<1>(0h0))
node _res_T_297 = and(_res_T_296, res_hit_6)
node _res_T_298 = and(_res_T_297, res_aligned_6)
node _res_T_299 = eq(io.pmp[1].cfg.a, UInt<2>(0h2))
node _res_T_300 = and(_res_T_298, _res_T_299)
node _res_T_301 = and(io.pmp[1].cfg.l, res_hit_6)
node _res_T_302 = and(_res_T_301, res_aligned_6)
node _res_T_303 = eq(io.pmp[1].cfg.a, UInt<2>(0h2))
node _res_T_304 = and(_res_T_302, _res_T_303)
node _res_T_305 = eq(res_ignore_6, UInt<1>(0h0))
node _res_T_306 = and(_res_T_305, res_hit_6)
node _res_T_307 = and(_res_T_306, res_aligned_6)
node _res_T_308 = eq(io.pmp[1].cfg.a, UInt<2>(0h3))
node _res_T_309 = and(_res_T_307, _res_T_308)
node _res_T_310 = and(io.pmp[1].cfg.l, res_hit_6)
node _res_T_311 = and(_res_T_310, res_aligned_6)
node _res_T_312 = eq(io.pmp[1].cfg.a, UInt<2>(0h3))
node _res_T_313 = and(_res_T_311, _res_T_312)
wire res_cur_6 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_6, io.pmp[1]
node _res_cur_cfg_r_T_12 = or(io.pmp[1].cfg.r, res_ignore_6)
node _res_cur_cfg_r_T_13 = and(res_aligned_6, _res_cur_cfg_r_T_12)
connect res_cur_6.cfg.r, _res_cur_cfg_r_T_13
node _res_cur_cfg_w_T_12 = or(io.pmp[1].cfg.w, res_ignore_6)
node _res_cur_cfg_w_T_13 = and(res_aligned_6, _res_cur_cfg_w_T_12)
connect res_cur_6.cfg.w, _res_cur_cfg_w_T_13
node _res_cur_cfg_x_T_12 = or(io.pmp[1].cfg.x, res_ignore_6)
node _res_cur_cfg_x_T_13 = and(res_aligned_6, _res_cur_cfg_x_T_12)
connect res_cur_6.cfg.x, _res_cur_cfg_x_T_13
node _res_T_314 = mux(res_hit_6, res_cur_6, _res_T_269)
node _res_hit_T_91 = bits(io.pmp[0].cfg.a, 1, 1)
node _res_hit_lsbMask_T_21 = dshl(UInt<3>(0h7), io.size)
node _res_hit_lsbMask_T_22 = bits(_res_hit_lsbMask_T_21, 2, 0)
node _res_hit_lsbMask_T_23 = not(_res_hit_lsbMask_T_22)
node res_hit_lsbMask_7 = or(io.pmp[0].mask, _res_hit_lsbMask_T_23)
node _res_hit_msbMatch_T_70 = shr(io.addr, 3)
node _res_hit_msbMatch_T_71 = shl(io.pmp[0].addr, 2)
node _res_hit_msbMatch_T_72 = not(_res_hit_msbMatch_T_71)
node _res_hit_msbMatch_T_73 = or(_res_hit_msbMatch_T_72, UInt<2>(0h3))
node _res_hit_msbMatch_T_74 = not(_res_hit_msbMatch_T_73)
node _res_hit_msbMatch_T_75 = shr(_res_hit_msbMatch_T_74, 3)
node _res_hit_msbMatch_T_76 = shr(io.pmp[0].mask, 3)
node _res_hit_msbMatch_T_77 = xor(_res_hit_msbMatch_T_70, _res_hit_msbMatch_T_75)
node _res_hit_msbMatch_T_78 = not(_res_hit_msbMatch_T_76)
node _res_hit_msbMatch_T_79 = and(_res_hit_msbMatch_T_77, _res_hit_msbMatch_T_78)
node res_hit_msbMatch_7 = eq(_res_hit_msbMatch_T_79, UInt<1>(0h0))
node _res_hit_lsbMatch_T_70 = bits(io.addr, 2, 0)
node _res_hit_lsbMatch_T_71 = shl(io.pmp[0].addr, 2)
node _res_hit_lsbMatch_T_72 = not(_res_hit_lsbMatch_T_71)
node _res_hit_lsbMatch_T_73 = or(_res_hit_lsbMatch_T_72, UInt<2>(0h3))
node _res_hit_lsbMatch_T_74 = not(_res_hit_lsbMatch_T_73)
node _res_hit_lsbMatch_T_75 = bits(_res_hit_lsbMatch_T_74, 2, 0)
node _res_hit_lsbMatch_T_76 = bits(res_hit_lsbMask_7, 2, 0)
node _res_hit_lsbMatch_T_77 = xor(_res_hit_lsbMatch_T_70, _res_hit_lsbMatch_T_75)
node _res_hit_lsbMatch_T_78 = not(_res_hit_lsbMatch_T_76)
node _res_hit_lsbMatch_T_79 = and(_res_hit_lsbMatch_T_77, _res_hit_lsbMatch_T_78)
node res_hit_lsbMatch_7 = eq(_res_hit_lsbMatch_T_79, UInt<1>(0h0))
node _res_hit_T_92 = and(res_hit_msbMatch_7, res_hit_lsbMatch_7)
node _res_hit_T_93 = bits(io.pmp[0].cfg.a, 0, 0)
node _res_hit_T_94 = dshl(UInt<3>(0h7), io.size)
node _res_hit_T_95 = bits(_res_hit_T_94, 2, 0)
node _res_hit_T_96 = not(_res_hit_T_95)
node _res_hit_msbsLess_T_84 = shr(io.addr, 3)
node _res_hit_msbsLess_T_85 = shl(pmp0.addr, 2)
node _res_hit_msbsLess_T_86 = not(_res_hit_msbsLess_T_85)
node _res_hit_msbsLess_T_87 = or(_res_hit_msbsLess_T_86, UInt<2>(0h3))
node _res_hit_msbsLess_T_88 = not(_res_hit_msbsLess_T_87)
node _res_hit_msbsLess_T_89 = shr(_res_hit_msbsLess_T_88, 3)
node res_hit_msbsLess_14 = lt(_res_hit_msbsLess_T_84, _res_hit_msbsLess_T_89)
node _res_hit_msbsEqual_T_98 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_99 = shl(pmp0.addr, 2)
node _res_hit_msbsEqual_T_100 = not(_res_hit_msbsEqual_T_99)
node _res_hit_msbsEqual_T_101 = or(_res_hit_msbsEqual_T_100, UInt<2>(0h3))
node _res_hit_msbsEqual_T_102 = not(_res_hit_msbsEqual_T_101)
node _res_hit_msbsEqual_T_103 = shr(_res_hit_msbsEqual_T_102, 3)
node _res_hit_msbsEqual_T_104 = xor(_res_hit_msbsEqual_T_98, _res_hit_msbsEqual_T_103)
node res_hit_msbsEqual_14 = eq(_res_hit_msbsEqual_T_104, UInt<1>(0h0))
node _res_hit_lsbsLess_T_98 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_99 = or(_res_hit_lsbsLess_T_98, _res_hit_T_96)
node _res_hit_lsbsLess_T_100 = shl(pmp0.addr, 2)
node _res_hit_lsbsLess_T_101 = not(_res_hit_lsbsLess_T_100)
node _res_hit_lsbsLess_T_102 = or(_res_hit_lsbsLess_T_101, UInt<2>(0h3))
node _res_hit_lsbsLess_T_103 = not(_res_hit_lsbsLess_T_102)
node _res_hit_lsbsLess_T_104 = bits(_res_hit_lsbsLess_T_103, 2, 0)
node res_hit_lsbsLess_14 = lt(_res_hit_lsbsLess_T_99, _res_hit_lsbsLess_T_104)
node _res_hit_T_97 = and(res_hit_msbsEqual_14, res_hit_lsbsLess_14)
node _res_hit_T_98 = or(res_hit_msbsLess_14, _res_hit_T_97)
node _res_hit_T_99 = eq(_res_hit_T_98, UInt<1>(0h0))
node _res_hit_msbsLess_T_90 = shr(io.addr, 3)
node _res_hit_msbsLess_T_91 = shl(io.pmp[0].addr, 2)
node _res_hit_msbsLess_T_92 = not(_res_hit_msbsLess_T_91)
node _res_hit_msbsLess_T_93 = or(_res_hit_msbsLess_T_92, UInt<2>(0h3))
node _res_hit_msbsLess_T_94 = not(_res_hit_msbsLess_T_93)
node _res_hit_msbsLess_T_95 = shr(_res_hit_msbsLess_T_94, 3)
node res_hit_msbsLess_15 = lt(_res_hit_msbsLess_T_90, _res_hit_msbsLess_T_95)
node _res_hit_msbsEqual_T_105 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_106 = shl(io.pmp[0].addr, 2)
node _res_hit_msbsEqual_T_107 = not(_res_hit_msbsEqual_T_106)
node _res_hit_msbsEqual_T_108 = or(_res_hit_msbsEqual_T_107, UInt<2>(0h3))
node _res_hit_msbsEqual_T_109 = not(_res_hit_msbsEqual_T_108)
node _res_hit_msbsEqual_T_110 = shr(_res_hit_msbsEqual_T_109, 3)
node _res_hit_msbsEqual_T_111 = xor(_res_hit_msbsEqual_T_105, _res_hit_msbsEqual_T_110)
node res_hit_msbsEqual_15 = eq(_res_hit_msbsEqual_T_111, UInt<1>(0h0))
node _res_hit_lsbsLess_T_105 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_106 = or(_res_hit_lsbsLess_T_105, UInt<1>(0h0))
node _res_hit_lsbsLess_T_107 = shl(io.pmp[0].addr, 2)
node _res_hit_lsbsLess_T_108 = not(_res_hit_lsbsLess_T_107)
node _res_hit_lsbsLess_T_109 = or(_res_hit_lsbsLess_T_108, UInt<2>(0h3))
node _res_hit_lsbsLess_T_110 = not(_res_hit_lsbsLess_T_109)
node _res_hit_lsbsLess_T_111 = bits(_res_hit_lsbsLess_T_110, 2, 0)
node res_hit_lsbsLess_15 = lt(_res_hit_lsbsLess_T_106, _res_hit_lsbsLess_T_111)
node _res_hit_T_100 = and(res_hit_msbsEqual_15, res_hit_lsbsLess_15)
node _res_hit_T_101 = or(res_hit_msbsLess_15, _res_hit_T_100)
node _res_hit_T_102 = and(_res_hit_T_99, _res_hit_T_101)
node _res_hit_T_103 = and(_res_hit_T_93, _res_hit_T_102)
node res_hit_7 = mux(_res_hit_T_91, _res_hit_T_92, _res_hit_T_103)
node _res_ignore_T_7 = eq(io.pmp[0].cfg.l, UInt<1>(0h0))
node res_ignore_7 = and(default, _res_ignore_T_7)
node _res_aligned_lsbMask_T_14 = dshl(UInt<3>(0h7), io.size)
node _res_aligned_lsbMask_T_15 = bits(_res_aligned_lsbMask_T_14, 2, 0)
node res_aligned_lsbMask_7 = not(_res_aligned_lsbMask_T_15)
node _res_aligned_straddlesLowerBound_T_119 = shr(io.addr, 3)
node _res_aligned_straddlesLowerBound_T_120 = shl(pmp0.addr, 2)
node _res_aligned_straddlesLowerBound_T_121 = not(_res_aligned_straddlesLowerBound_T_120)
node _res_aligned_straddlesLowerBound_T_122 = or(_res_aligned_straddlesLowerBound_T_121, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_123 = not(_res_aligned_straddlesLowerBound_T_122)
node _res_aligned_straddlesLowerBound_T_124 = shr(_res_aligned_straddlesLowerBound_T_123, 3)
node _res_aligned_straddlesLowerBound_T_125 = xor(_res_aligned_straddlesLowerBound_T_119, _res_aligned_straddlesLowerBound_T_124)
node _res_aligned_straddlesLowerBound_T_126 = eq(_res_aligned_straddlesLowerBound_T_125, UInt<1>(0h0))
node _res_aligned_straddlesLowerBound_T_127 = shl(pmp0.addr, 2)
node _res_aligned_straddlesLowerBound_T_128 = not(_res_aligned_straddlesLowerBound_T_127)
node _res_aligned_straddlesLowerBound_T_129 = or(_res_aligned_straddlesLowerBound_T_128, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_130 = not(_res_aligned_straddlesLowerBound_T_129)
node _res_aligned_straddlesLowerBound_T_131 = bits(_res_aligned_straddlesLowerBound_T_130, 2, 0)
node _res_aligned_straddlesLowerBound_T_132 = bits(io.addr, 2, 0)
node _res_aligned_straddlesLowerBound_T_133 = not(_res_aligned_straddlesLowerBound_T_132)
node _res_aligned_straddlesLowerBound_T_134 = and(_res_aligned_straddlesLowerBound_T_131, _res_aligned_straddlesLowerBound_T_133)
node _res_aligned_straddlesLowerBound_T_135 = neq(_res_aligned_straddlesLowerBound_T_134, UInt<1>(0h0))
node res_aligned_straddlesLowerBound_7 = and(_res_aligned_straddlesLowerBound_T_126, _res_aligned_straddlesLowerBound_T_135)
node _res_aligned_straddlesUpperBound_T_119 = shr(io.addr, 3)
node _res_aligned_straddlesUpperBound_T_120 = shl(io.pmp[0].addr, 2)
node _res_aligned_straddlesUpperBound_T_121 = not(_res_aligned_straddlesUpperBound_T_120)
node _res_aligned_straddlesUpperBound_T_122 = or(_res_aligned_straddlesUpperBound_T_121, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_123 = not(_res_aligned_straddlesUpperBound_T_122)
node _res_aligned_straddlesUpperBound_T_124 = shr(_res_aligned_straddlesUpperBound_T_123, 3)
node _res_aligned_straddlesUpperBound_T_125 = xor(_res_aligned_straddlesUpperBound_T_119, _res_aligned_straddlesUpperBound_T_124)
node _res_aligned_straddlesUpperBound_T_126 = eq(_res_aligned_straddlesUpperBound_T_125, UInt<1>(0h0))
node _res_aligned_straddlesUpperBound_T_127 = shl(io.pmp[0].addr, 2)
node _res_aligned_straddlesUpperBound_T_128 = not(_res_aligned_straddlesUpperBound_T_127)
node _res_aligned_straddlesUpperBound_T_129 = or(_res_aligned_straddlesUpperBound_T_128, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_130 = not(_res_aligned_straddlesUpperBound_T_129)
node _res_aligned_straddlesUpperBound_T_131 = bits(_res_aligned_straddlesUpperBound_T_130, 2, 0)
node _res_aligned_straddlesUpperBound_T_132 = bits(io.addr, 2, 0)
node _res_aligned_straddlesUpperBound_T_133 = or(_res_aligned_straddlesUpperBound_T_132, res_aligned_lsbMask_7)
node _res_aligned_straddlesUpperBound_T_134 = and(_res_aligned_straddlesUpperBound_T_131, _res_aligned_straddlesUpperBound_T_133)
node _res_aligned_straddlesUpperBound_T_135 = neq(_res_aligned_straddlesUpperBound_T_134, UInt<1>(0h0))
node res_aligned_straddlesUpperBound_7 = and(_res_aligned_straddlesUpperBound_T_126, _res_aligned_straddlesUpperBound_T_135)
node _res_aligned_rangeAligned_T_7 = or(res_aligned_straddlesLowerBound_7, res_aligned_straddlesUpperBound_7)
node res_aligned_rangeAligned_7 = eq(_res_aligned_rangeAligned_T_7, UInt<1>(0h0))
node _res_aligned_pow2Aligned_T_21 = bits(io.pmp[0].mask, 2, 0)
node _res_aligned_pow2Aligned_T_22 = not(_res_aligned_pow2Aligned_T_21)
node _res_aligned_pow2Aligned_T_23 = and(res_aligned_lsbMask_7, _res_aligned_pow2Aligned_T_22)
node res_aligned_pow2Aligned_7 = eq(_res_aligned_pow2Aligned_T_23, UInt<1>(0h0))
node _res_aligned_T_7 = bits(io.pmp[0].cfg.a, 1, 1)
node res_aligned_7 = mux(_res_aligned_T_7, res_aligned_pow2Aligned_7, res_aligned_rangeAligned_7)
node _res_T_315 = eq(io.pmp[0].cfg.a, UInt<1>(0h0))
node _res_T_316 = eq(io.pmp[0].cfg.a, UInt<1>(0h1))
node _res_T_317 = eq(io.pmp[0].cfg.a, UInt<2>(0h2))
node _res_T_318 = eq(io.pmp[0].cfg.a, UInt<2>(0h3))
node _res_T_319 = eq(io.pmp[0].cfg.l, UInt<1>(0h1))
node res_hi_42 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w)
node _res_T_320 = cat(res_hi_42, io.pmp[0].cfg.r)
node _res_T_321 = eq(_res_T_320, UInt<1>(0h0))
node res_hi_43 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w)
node _res_T_322 = cat(res_hi_43, io.pmp[0].cfg.r)
node _res_T_323 = eq(_res_T_322, UInt<1>(0h1))
node res_hi_44 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w)
node _res_T_324 = cat(res_hi_44, io.pmp[0].cfg.r)
node _res_T_325 = eq(_res_T_324, UInt<2>(0h3))
node res_hi_45 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w)
node _res_T_326 = cat(res_hi_45, io.pmp[0].cfg.r)
node _res_T_327 = eq(_res_T_326, UInt<3>(0h4))
node res_hi_46 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w)
node _res_T_328 = cat(res_hi_46, io.pmp[0].cfg.r)
node _res_T_329 = eq(_res_T_328, UInt<3>(0h5))
node res_hi_47 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w)
node _res_T_330 = cat(res_hi_47, io.pmp[0].cfg.r)
node _res_T_331 = eq(_res_T_330, UInt<3>(0h7))
node _res_T_332 = eq(res_ignore_7, UInt<1>(0h0))
node _res_T_333 = and(_res_T_332, res_hit_7)
node _res_T_334 = and(_res_T_333, res_aligned_7)
node _res_T_335 = eq(io.pmp[0].cfg.a, UInt<1>(0h1))
node _res_T_336 = and(_res_T_334, _res_T_335)
node _res_T_337 = and(io.pmp[0].cfg.l, res_hit_7)
node _res_T_338 = and(_res_T_337, res_aligned_7)
node _res_T_339 = eq(io.pmp[0].cfg.a, UInt<1>(0h1))
node _res_T_340 = and(_res_T_338, _res_T_339)
node _res_T_341 = eq(res_ignore_7, UInt<1>(0h0))
node _res_T_342 = and(_res_T_341, res_hit_7)
node _res_T_343 = and(_res_T_342, res_aligned_7)
node _res_T_344 = eq(io.pmp[0].cfg.a, UInt<2>(0h2))
node _res_T_345 = and(_res_T_343, _res_T_344)
node _res_T_346 = and(io.pmp[0].cfg.l, res_hit_7)
node _res_T_347 = and(_res_T_346, res_aligned_7)
node _res_T_348 = eq(io.pmp[0].cfg.a, UInt<2>(0h2))
node _res_T_349 = and(_res_T_347, _res_T_348)
node _res_T_350 = eq(res_ignore_7, UInt<1>(0h0))
node _res_T_351 = and(_res_T_350, res_hit_7)
node _res_T_352 = and(_res_T_351, res_aligned_7)
node _res_T_353 = eq(io.pmp[0].cfg.a, UInt<2>(0h3))
node _res_T_354 = and(_res_T_352, _res_T_353)
node _res_T_355 = and(io.pmp[0].cfg.l, res_hit_7)
node _res_T_356 = and(_res_T_355, res_aligned_7)
node _res_T_357 = eq(io.pmp[0].cfg.a, UInt<2>(0h3))
node _res_T_358 = and(_res_T_356, _res_T_357)
wire res_cur_7 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_7, io.pmp[0]
node _res_cur_cfg_r_T_14 = or(io.pmp[0].cfg.r, res_ignore_7)
node _res_cur_cfg_r_T_15 = and(res_aligned_7, _res_cur_cfg_r_T_14)
connect res_cur_7.cfg.r, _res_cur_cfg_r_T_15
node _res_cur_cfg_w_T_14 = or(io.pmp[0].cfg.w, res_ignore_7)
node _res_cur_cfg_w_T_15 = and(res_aligned_7, _res_cur_cfg_w_T_14)
connect res_cur_7.cfg.w, _res_cur_cfg_w_T_15
node _res_cur_cfg_x_T_14 = or(io.pmp[0].cfg.x, res_ignore_7)
node _res_cur_cfg_x_T_15 = and(res_aligned_7, _res_cur_cfg_x_T_14)
connect res_cur_7.cfg.x, _res_cur_cfg_x_T_15
node res = mux(res_hit_7, res_cur_7, _res_T_314)
connect io.r, res.cfg.r
connect io.w, res.cfg.w
connect io.x, res.cfg.x | module PMPChecker_s3_4( // @[PMP.scala:143:7]
input clock, // @[PMP.scala:143:7]
input reset, // @[PMP.scala:143:7]
input [1:0] io_prv, // @[PMP.scala:146:14]
input io_pmp_0_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_0_cfg_a, // @[PMP.scala:146:14]
input io_pmp_0_cfg_x, // @[PMP.scala:146:14]
input io_pmp_0_cfg_w, // @[PMP.scala:146:14]
input io_pmp_0_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_0_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_0_mask, // @[PMP.scala:146:14]
input io_pmp_1_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_1_cfg_a, // @[PMP.scala:146:14]
input io_pmp_1_cfg_x, // @[PMP.scala:146:14]
input io_pmp_1_cfg_w, // @[PMP.scala:146:14]
input io_pmp_1_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_1_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_1_mask, // @[PMP.scala:146:14]
input io_pmp_2_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_2_cfg_a, // @[PMP.scala:146:14]
input io_pmp_2_cfg_x, // @[PMP.scala:146:14]
input io_pmp_2_cfg_w, // @[PMP.scala:146:14]
input io_pmp_2_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_2_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_2_mask, // @[PMP.scala:146:14]
input io_pmp_3_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_3_cfg_a, // @[PMP.scala:146:14]
input io_pmp_3_cfg_x, // @[PMP.scala:146:14]
input io_pmp_3_cfg_w, // @[PMP.scala:146:14]
input io_pmp_3_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_3_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_3_mask, // @[PMP.scala:146:14]
input io_pmp_4_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_4_cfg_a, // @[PMP.scala:146:14]
input io_pmp_4_cfg_x, // @[PMP.scala:146:14]
input io_pmp_4_cfg_w, // @[PMP.scala:146:14]
input io_pmp_4_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_4_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_4_mask, // @[PMP.scala:146:14]
input io_pmp_5_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_5_cfg_a, // @[PMP.scala:146:14]
input io_pmp_5_cfg_x, // @[PMP.scala:146:14]
input io_pmp_5_cfg_w, // @[PMP.scala:146:14]
input io_pmp_5_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_5_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_5_mask, // @[PMP.scala:146:14]
input io_pmp_6_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_6_cfg_a, // @[PMP.scala:146:14]
input io_pmp_6_cfg_x, // @[PMP.scala:146:14]
input io_pmp_6_cfg_w, // @[PMP.scala:146:14]
input io_pmp_6_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_6_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_6_mask, // @[PMP.scala:146:14]
input io_pmp_7_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_7_cfg_a, // @[PMP.scala:146:14]
input io_pmp_7_cfg_x, // @[PMP.scala:146:14]
input io_pmp_7_cfg_w, // @[PMP.scala:146:14]
input io_pmp_7_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_7_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_7_mask, // @[PMP.scala:146:14]
input [31:0] io_addr, // @[PMP.scala:146:14]
input [1:0] io_size, // @[PMP.scala:146:14]
output io_r, // @[PMP.scala:146:14]
output io_w, // @[PMP.scala:146:14]
output io_x // @[PMP.scala:146:14]
);
wire [1:0] io_prv_0 = io_prv; // @[PMP.scala:143:7]
wire io_pmp_0_cfg_l_0 = io_pmp_0_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_0_cfg_a_0 = io_pmp_0_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_0_cfg_x_0 = io_pmp_0_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_0_cfg_w_0 = io_pmp_0_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_0_cfg_r_0 = io_pmp_0_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_0_addr_0 = io_pmp_0_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_0_mask_0 = io_pmp_0_mask; // @[PMP.scala:143:7]
wire io_pmp_1_cfg_l_0 = io_pmp_1_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_1_cfg_a_0 = io_pmp_1_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_1_cfg_x_0 = io_pmp_1_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_1_cfg_w_0 = io_pmp_1_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_1_cfg_r_0 = io_pmp_1_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_1_addr_0 = io_pmp_1_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_1_mask_0 = io_pmp_1_mask; // @[PMP.scala:143:7]
wire io_pmp_2_cfg_l_0 = io_pmp_2_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_2_cfg_a_0 = io_pmp_2_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_2_cfg_x_0 = io_pmp_2_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_2_cfg_w_0 = io_pmp_2_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_2_cfg_r_0 = io_pmp_2_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_2_addr_0 = io_pmp_2_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_2_mask_0 = io_pmp_2_mask; // @[PMP.scala:143:7]
wire io_pmp_3_cfg_l_0 = io_pmp_3_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_3_cfg_a_0 = io_pmp_3_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_3_cfg_x_0 = io_pmp_3_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_3_cfg_w_0 = io_pmp_3_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_3_cfg_r_0 = io_pmp_3_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_3_addr_0 = io_pmp_3_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_3_mask_0 = io_pmp_3_mask; // @[PMP.scala:143:7]
wire io_pmp_4_cfg_l_0 = io_pmp_4_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_4_cfg_a_0 = io_pmp_4_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_4_cfg_x_0 = io_pmp_4_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_4_cfg_w_0 = io_pmp_4_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_4_cfg_r_0 = io_pmp_4_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_4_addr_0 = io_pmp_4_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_4_mask_0 = io_pmp_4_mask; // @[PMP.scala:143:7]
wire io_pmp_5_cfg_l_0 = io_pmp_5_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_5_cfg_a_0 = io_pmp_5_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_5_cfg_x_0 = io_pmp_5_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_5_cfg_w_0 = io_pmp_5_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_5_cfg_r_0 = io_pmp_5_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_5_addr_0 = io_pmp_5_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_5_mask_0 = io_pmp_5_mask; // @[PMP.scala:143:7]
wire io_pmp_6_cfg_l_0 = io_pmp_6_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_6_cfg_a_0 = io_pmp_6_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_6_cfg_x_0 = io_pmp_6_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_6_cfg_w_0 = io_pmp_6_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_6_cfg_r_0 = io_pmp_6_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_6_addr_0 = io_pmp_6_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_6_mask_0 = io_pmp_6_mask; // @[PMP.scala:143:7]
wire io_pmp_7_cfg_l_0 = io_pmp_7_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_7_cfg_a_0 = io_pmp_7_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_7_cfg_x_0 = io_pmp_7_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_7_cfg_w_0 = io_pmp_7_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_7_cfg_r_0 = io_pmp_7_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_7_addr_0 = io_pmp_7_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_7_mask_0 = io_pmp_7_mask; // @[PMP.scala:143:7]
wire [31:0] io_addr_0 = io_addr; // @[PMP.scala:143:7]
wire [1:0] io_size_0 = io_size; // @[PMP.scala:143:7]
wire [29:0] _pmp0_WIRE_addr = 30'h0; // @[PMP.scala:157:35]
wire [29:0] pmp0_addr = 30'h0; // @[PMP.scala:157:22]
wire _res_hit_T_99 = 1'h1; // @[PMP.scala:88:5]
wire [28:0] _res_hit_msbsLess_T_89 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67]
wire [28:0] _res_hit_msbsEqual_T_103 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_124 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67]
wire [31:0] _res_hit_msbsLess_T_86 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_87 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_100 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_101 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_101 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_102 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_121 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_122 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_128 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_129 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmp0_WIRE_mask = 32'h0; // @[PMP.scala:157:35]
wire [31:0] pmp0_mask = 32'h0; // @[PMP.scala:157:22]
wire [31:0] _res_hit_msbsLess_T_85 = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_88 = 32'h0; // @[PMP.scala:60:27]
wire [31:0] _res_hit_msbsEqual_T_99 = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_102 = 32'h0; // @[PMP.scala:60:27]
wire [31:0] _res_hit_lsbsLess_T_100 = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_103 = 32'h0; // @[PMP.scala:60:27]
wire [31:0] _res_aligned_straddlesLowerBound_T_120 = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_123 = 32'h0; // @[PMP.scala:60:27]
wire [31:0] _res_aligned_straddlesLowerBound_T_127 = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_130 = 32'h0; // @[PMP.scala:60:27]
wire [2:0] _res_hit_lsbsLess_T_104 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}]
wire [2:0] _res_aligned_straddlesLowerBound_T_131 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}]
wire [2:0] _res_aligned_straddlesLowerBound_T_134 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}]
wire _pmp0_WIRE_cfg_l = 1'h0; // @[PMP.scala:157:35]
wire _pmp0_WIRE_cfg_x = 1'h0; // @[PMP.scala:157:35]
wire _pmp0_WIRE_cfg_w = 1'h0; // @[PMP.scala:157:35]
wire _pmp0_WIRE_cfg_r = 1'h0; // @[PMP.scala:157:35]
wire pmp0_cfg_l = 1'h0; // @[PMP.scala:157:22]
wire res_hit_msbsLess_14 = 1'h0; // @[PMP.scala:80:39]
wire res_hit_lsbsLess_14 = 1'h0; // @[PMP.scala:82:53]
wire _res_hit_T_97 = 1'h0; // @[PMP.scala:83:30]
wire _res_hit_T_98 = 1'h0; // @[PMP.scala:83:16]
wire _res_aligned_straddlesLowerBound_T_135 = 1'h0; // @[PMP.scala:123:147]
wire res_aligned_straddlesLowerBound_7 = 1'h0; // @[PMP.scala:123:90]
wire [1:0] io_pmp_0_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_1_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_2_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_3_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_4_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_5_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_6_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_7_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] _pmp0_WIRE_cfg_res = 2'h0; // @[PMP.scala:157:35]
wire [1:0] _pmp0_WIRE_cfg_a = 2'h0; // @[PMP.scala:157:35]
wire [1:0] pmp0_cfg_res = 2'h0; // @[PMP.scala:157:22]
wire [1:0] pmp0_cfg_a = 2'h0; // @[PMP.scala:157:22]
wire [1:0] res_cur_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_44_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_1_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_89_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_2_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_134_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_3_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_179_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_4_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_224_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_5_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_269_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_6_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_314_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_7_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] res_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire _res_T_319 = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_7_cfg_l = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_7_cfg_a = io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_7_addr = io_pmp_0_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_7_mask = io_pmp_0_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_274 = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_6_cfg_l = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_6_cfg_a = io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_6_addr = io_pmp_1_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_6_mask = io_pmp_1_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_229 = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_5_cfg_l = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_5_cfg_a = io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_5_addr = io_pmp_2_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_5_mask = io_pmp_2_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_184 = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_4_cfg_l = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_4_cfg_a = io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_4_addr = io_pmp_3_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_4_mask = io_pmp_3_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_139 = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_3_cfg_l = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_3_cfg_a = io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_3_addr = io_pmp_4_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_3_mask = io_pmp_4_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_94 = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_2_cfg_l = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_2_cfg_a = io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_2_addr = io_pmp_5_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_2_mask = io_pmp_5_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_49 = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_1_cfg_l = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_1_cfg_a = io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_1_addr = io_pmp_6_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_1_mask = io_pmp_6_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_4 = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_cfg_l = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_cfg_a = io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_addr = io_pmp_7_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_mask = io_pmp_7_mask_0; // @[PMP.scala:143:7, :181:23]
wire res_cfg_r; // @[PMP.scala:185:8]
wire res_cfg_w; // @[PMP.scala:185:8]
wire res_cfg_x; // @[PMP.scala:185:8]
wire io_r_0; // @[PMP.scala:143:7]
wire io_w_0; // @[PMP.scala:143:7]
wire io_x_0; // @[PMP.scala:143:7]
wire default_0 = io_prv_0[1]; // @[PMP.scala:143:7, :156:56]
wire pmp0_cfg_x = default_0; // @[PMP.scala:156:56, :157:22]
wire pmp0_cfg_w = default_0; // @[PMP.scala:156:56, :157:22]
wire pmp0_cfg_r = default_0; // @[PMP.scala:156:56, :157:22]
wire _res_hit_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [5:0] _GEN = 6'h7 << io_size_0; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T; // @[package.scala:243:71]
assign _res_hit_lsbMask_T = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_3; // @[package.scala:243:71]
assign _res_hit_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_3; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_16; // @[package.scala:243:71]
assign _res_hit_T_16 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_2; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_2 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_6; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_6 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_29; // @[package.scala:243:71]
assign _res_hit_T_29 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_4; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_4 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_9; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_9 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_42; // @[package.scala:243:71]
assign _res_hit_T_42 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_6; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_6 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_12; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_12 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_55; // @[package.scala:243:71]
assign _res_hit_T_55 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_8; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_8 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_15; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_15 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_68; // @[package.scala:243:71]
assign _res_hit_T_68 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_10; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_10 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_18; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_18 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_81; // @[package.scala:243:71]
assign _res_hit_T_81 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_12; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_12 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_21; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_21 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_94; // @[package.scala:243:71]
assign _res_hit_T_94 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_14; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_14 = _GEN; // @[package.scala:243:71]
wire [2:0] _res_hit_lsbMask_T_1 = _res_hit_lsbMask_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_2 = ~_res_hit_lsbMask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_6 = io_pmp_7_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T = io_pmp_7_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask = {_res_hit_msbMatch_T_6, _res_aligned_pow2Aligned_T | _res_hit_lsbMask_T_2}; // @[package.scala:243:46]
wire [28:0] _res_hit_msbMatch_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_6 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_7 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_10 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_12 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_14 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_18 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_21 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_17 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_17 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_20 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_24 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_28 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_30 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_35 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_34 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_34 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_30 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_36 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_42 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_42 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_49 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_51 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_51 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_40 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_48 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_56 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_54 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_63 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_68 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_68 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_50 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_60 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_70 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_66 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_77 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_85 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_85 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_60 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_72 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_84 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_78 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_91 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_102 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_102 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_70 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_84 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_98 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_90 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_105 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_119 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_119 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [31:0] _GEN_0 = {io_pmp_7_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbMatch_T_1; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_1 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_1; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_1 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_7; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_7 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_8; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_8 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_9; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_9 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_1; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_1 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_8; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_8 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_2 = ~_res_hit_msbMatch_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_3 = {_res_hit_msbMatch_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_4 = ~_res_hit_msbMatch_T_3; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_5 = _res_hit_msbMatch_T_4[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_7 = _res_hit_msbMatch_T ^ _res_hit_msbMatch_T_5; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_8 = ~_res_hit_msbMatch_T_6; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_9 = _res_hit_msbMatch_T_7 & _res_hit_msbMatch_T_8; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch = _res_hit_msbMatch_T_9 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [2:0] _res_hit_lsbMatch_T = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_7 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_13 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_13 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_10 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_14 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_21 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_20 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_28 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_35 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_47 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_47 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_42 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_49 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_64 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_64 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_40 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_56 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_63 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_81 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_81 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_50 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_70 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_77 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_60 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_84 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_91 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_115 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_115 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_70 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_105 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_132 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_132 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [31:0] _res_hit_lsbMatch_T_2 = ~_res_hit_lsbMatch_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_3 = {_res_hit_lsbMatch_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_4 = ~_res_hit_lsbMatch_T_3; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_5 = _res_hit_lsbMatch_T_4[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_6 = res_hit_lsbMask[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_7 = _res_hit_lsbMatch_T ^ _res_hit_lsbMatch_T_5; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_8 = ~_res_hit_lsbMatch_T_6; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_9 = _res_hit_lsbMatch_T_7 & _res_hit_lsbMatch_T_8; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch = _res_hit_lsbMatch_T_9 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_1 = res_hit_msbMatch & res_hit_lsbMatch; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_2 = io_pmp_7_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_4 = _res_hit_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_5 = ~_res_hit_T_4; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_1 = {io_pmp_6_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_1; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_1 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_1; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_1 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_2; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_2 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_1; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_1 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_8; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_8 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_11; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_11 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_11; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_11 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_19; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_19 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_22; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_22 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_23; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_23 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_18; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_18 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_25; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_25 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_2 = ~_res_hit_msbsLess_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_3 = {_res_hit_msbsLess_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_4 = ~_res_hit_msbsLess_T_3; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_5 = _res_hit_msbsLess_T_4[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess = _res_hit_msbsLess_T < _res_hit_msbsLess_T_5; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_2 = ~_res_hit_msbsEqual_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_3 = {_res_hit_msbsEqual_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_4 = ~_res_hit_msbsEqual_T_3; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_5 = _res_hit_msbsEqual_T_4[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_6 = _res_hit_msbsEqual_T ^ _res_hit_msbsEqual_T_5; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual = _res_hit_msbsEqual_T_6 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_1 = _res_hit_lsbsLess_T | _res_hit_T_5; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_3 = ~_res_hit_lsbsLess_T_2; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_4 = {_res_hit_lsbsLess_T_3[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_5 = ~_res_hit_lsbsLess_T_4; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_6 = _res_hit_lsbsLess_T_5[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess = _res_hit_lsbsLess_T_1 < _res_hit_lsbsLess_T_6; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_6 = res_hit_msbsEqual & res_hit_lsbsLess; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_7 = res_hit_msbsLess | _res_hit_T_6; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_8 = ~_res_hit_T_7; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_8 = ~_res_hit_msbsLess_T_7; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_9 = {_res_hit_msbsLess_T_8[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_10 = ~_res_hit_msbsLess_T_9; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_11 = _res_hit_msbsLess_T_10[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_1 = _res_hit_msbsLess_T_6 < _res_hit_msbsLess_T_11; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_9 = ~_res_hit_msbsEqual_T_8; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_10 = {_res_hit_msbsEqual_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_11 = ~_res_hit_msbsEqual_T_10; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_12 = _res_hit_msbsEqual_T_11[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_13 = _res_hit_msbsEqual_T_7 ^ _res_hit_msbsEqual_T_12; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_1 = _res_hit_msbsEqual_T_13 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_8 = _res_hit_lsbsLess_T_7; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_10 = ~_res_hit_lsbsLess_T_9; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_11 = {_res_hit_lsbsLess_T_10[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_12 = ~_res_hit_lsbsLess_T_11; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_13 = _res_hit_lsbsLess_T_12[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_1 = _res_hit_lsbsLess_T_8 < _res_hit_lsbsLess_T_13; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_9 = res_hit_msbsEqual_1 & res_hit_lsbsLess_1; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_10 = res_hit_msbsLess_1 | _res_hit_T_9; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_11 = _res_hit_T_8 & _res_hit_T_10; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_12 = _res_hit_T_2 & _res_hit_T_11; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit = _res_hit_T ? _res_hit_T_1 : _res_hit_T_12; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T = ~io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore = default_0 & _res_ignore_T; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_1 = _res_aligned_lsbMask_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask = ~_res_aligned_lsbMask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_2 = ~_res_aligned_straddlesLowerBound_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_3 = {_res_aligned_straddlesLowerBound_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_4 = ~_res_aligned_straddlesLowerBound_T_3; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_5 = _res_aligned_straddlesLowerBound_T_4[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_6 = _res_aligned_straddlesLowerBound_T ^ _res_aligned_straddlesLowerBound_T_5; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_7 = _res_aligned_straddlesLowerBound_T_6 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_9 = ~_res_aligned_straddlesLowerBound_T_8; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_10 = {_res_aligned_straddlesLowerBound_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_11 = ~_res_aligned_straddlesLowerBound_T_10; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_12 = _res_aligned_straddlesLowerBound_T_11[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_14 = ~_res_aligned_straddlesLowerBound_T_13; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_15 = _res_aligned_straddlesLowerBound_T_12 & _res_aligned_straddlesLowerBound_T_14; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_16 = |_res_aligned_straddlesLowerBound_T_15; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound = _res_aligned_straddlesLowerBound_T_7 & _res_aligned_straddlesLowerBound_T_16; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_2 = ~_res_aligned_straddlesUpperBound_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_3 = {_res_aligned_straddlesUpperBound_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_4 = ~_res_aligned_straddlesUpperBound_T_3; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_5 = _res_aligned_straddlesUpperBound_T_4[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_6 = _res_aligned_straddlesUpperBound_T ^ _res_aligned_straddlesUpperBound_T_5; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_7 = _res_aligned_straddlesUpperBound_T_6 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_9 = ~_res_aligned_straddlesUpperBound_T_8; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_10 = {_res_aligned_straddlesUpperBound_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_11 = ~_res_aligned_straddlesUpperBound_T_10; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_12 = _res_aligned_straddlesUpperBound_T_11[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_14 = _res_aligned_straddlesUpperBound_T_13 | res_aligned_lsbMask; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_15 = _res_aligned_straddlesUpperBound_T_12 & _res_aligned_straddlesUpperBound_T_14; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_16 = |_res_aligned_straddlesUpperBound_T_15; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound = _res_aligned_straddlesUpperBound_T_7 & _res_aligned_straddlesUpperBound_T_16; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T = res_aligned_straddlesLowerBound | res_aligned_straddlesUpperBound; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned = ~_res_aligned_rangeAligned_T; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_1 = ~_res_aligned_pow2Aligned_T; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_2 = res_aligned_lsbMask & _res_aligned_pow2Aligned_T_1; // @[package.scala:243:46]
wire res_aligned_pow2Aligned = _res_aligned_pow2Aligned_T_2 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned = _res_aligned_T ? res_aligned_pow2Aligned : res_aligned_rangeAligned; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T = io_pmp_7_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_2 = io_pmp_7_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_1; // @[PMP.scala:168:32]
assign _res_T_1 = _GEN_2; // @[PMP.scala:168:32]
wire _res_T_20; // @[PMP.scala:177:61]
assign _res_T_20 = _GEN_2; // @[PMP.scala:168:32, :177:61]
wire _res_T_24; // @[PMP.scala:178:63]
assign _res_T_24 = _GEN_2; // @[PMP.scala:168:32, :178:63]
wire _GEN_3 = io_pmp_7_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_2; // @[PMP.scala:168:32]
assign _res_T_2 = _GEN_3; // @[PMP.scala:168:32]
wire _res_T_29; // @[PMP.scala:177:61]
assign _res_T_29 = _GEN_3; // @[PMP.scala:168:32, :177:61]
wire _res_T_33; // @[PMP.scala:178:63]
assign _res_T_33 = _GEN_3; // @[PMP.scala:168:32, :178:63]
wire _res_T_3 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_4 = {io_pmp_7_cfg_x_0, io_pmp_7_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi; // @[PMP.scala:174:26]
assign res_hi = _GEN_4; // @[PMP.scala:174:26]
wire [1:0] res_hi_1; // @[PMP.scala:174:26]
assign res_hi_1 = _GEN_4; // @[PMP.scala:174:26]
wire [1:0] res_hi_2; // @[PMP.scala:174:26]
assign res_hi_2 = _GEN_4; // @[PMP.scala:174:26]
wire [1:0] res_hi_3; // @[PMP.scala:174:26]
assign res_hi_3 = _GEN_4; // @[PMP.scala:174:26]
wire [1:0] res_hi_4; // @[PMP.scala:174:26]
assign res_hi_4 = _GEN_4; // @[PMP.scala:174:26]
wire [1:0] res_hi_5; // @[PMP.scala:174:26]
assign res_hi_5 = _GEN_4; // @[PMP.scala:174:26]
wire [2:0] _res_T_5 = {res_hi, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_6 = _res_T_5 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_7 = {res_hi_1, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_8 = _res_T_7 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_9 = {res_hi_2, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_10 = _res_T_9 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_11 = {res_hi_3, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_12 = _res_T_11 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_13 = {res_hi_4, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_14 = _res_T_13 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_15 = {res_hi_5, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_16 = &_res_T_15; // @[PMP.scala:174:{26,60}]
wire _res_T_17 = ~res_ignore; // @[PMP.scala:164:26, :177:22]
wire _res_T_18 = _res_T_17 & res_hit; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_19 = _res_T_18 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_21 = _res_T_19 & _res_T_20; // @[PMP.scala:177:{37,48,61}]
wire _GEN_5 = io_pmp_7_cfg_l_0 & res_hit; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_22; // @[PMP.scala:178:32]
assign _res_T_22 = _GEN_5; // @[PMP.scala:178:32]
wire _res_T_31; // @[PMP.scala:178:32]
assign _res_T_31 = _GEN_5; // @[PMP.scala:178:32]
wire _res_T_40; // @[PMP.scala:178:32]
assign _res_T_40 = _GEN_5; // @[PMP.scala:178:32]
wire _res_T_23 = _res_T_22 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_25 = _res_T_23 & _res_T_24; // @[PMP.scala:178:{39,50,63}]
wire _res_T_26 = ~res_ignore; // @[PMP.scala:164:26, :177:22]
wire _res_T_27 = _res_T_26 & res_hit; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_28 = _res_T_27 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_30 = _res_T_28 & _res_T_29; // @[PMP.scala:177:{37,48,61}]
wire _res_T_32 = _res_T_31 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_34 = _res_T_32 & _res_T_33; // @[PMP.scala:178:{39,50,63}]
wire _res_T_35 = ~res_ignore; // @[PMP.scala:164:26, :177:22]
wire _res_T_36 = _res_T_35 & res_hit; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_37 = _res_T_36 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_38 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_39 = _res_T_37 & _res_T_38; // @[PMP.scala:177:{37,48,61}]
wire _res_T_41 = _res_T_40 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_42 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_43 = _res_T_41 & _res_T_42; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_1; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_1; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_1; // @[PMP.scala:182:26]
wire res_cur_cfg_x; // @[PMP.scala:181:23]
wire res_cur_cfg_w; // @[PMP.scala:181:23]
wire res_cur_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T = io_pmp_7_cfg_r_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_1 = res_aligned & _res_cur_cfg_r_T; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_cfg_r = _res_cur_cfg_r_T_1; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T = io_pmp_7_cfg_w_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_1 = res_aligned & _res_cur_cfg_w_T; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_cfg_w = _res_cur_cfg_w_T_1; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T = io_pmp_7_cfg_x_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_1 = res_aligned & _res_cur_cfg_x_T; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_cfg_x = _res_cur_cfg_x_T_1; // @[PMP.scala:181:23, :184:26]
wire _res_T_44_cfg_l = res_hit & res_cur_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_44_cfg_a = res_hit ? res_cur_cfg_a : 2'h0; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_44_cfg_x = res_hit ? res_cur_cfg_x : pmp0_cfg_x; // @[PMP.scala:132:8, :157:22, :181:23, :185:8]
wire _res_T_44_cfg_w = res_hit ? res_cur_cfg_w : pmp0_cfg_w; // @[PMP.scala:132:8, :157:22, :181:23, :185:8]
wire _res_T_44_cfg_r = res_hit ? res_cur_cfg_r : pmp0_cfg_r; // @[PMP.scala:132:8, :157:22, :181:23, :185:8]
wire [29:0] _res_T_44_addr = res_hit ? res_cur_addr : 30'h0; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_44_mask = res_hit ? res_cur_mask : 32'h0; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_13 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_1 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_4 = _res_hit_lsbMask_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_5 = ~_res_hit_lsbMask_T_4; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_16 = io_pmp_6_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_3 = io_pmp_6_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_1 = {_res_hit_msbMatch_T_16, _res_aligned_pow2Aligned_T_3 | _res_hit_lsbMask_T_5}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_12 = ~_res_hit_msbMatch_T_11; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_13 = {_res_hit_msbMatch_T_12[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_14 = ~_res_hit_msbMatch_T_13; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_15 = _res_hit_msbMatch_T_14[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_17 = _res_hit_msbMatch_T_10 ^ _res_hit_msbMatch_T_15; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_18 = ~_res_hit_msbMatch_T_16; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_19 = _res_hit_msbMatch_T_17 & _res_hit_msbMatch_T_18; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_1 = _res_hit_msbMatch_T_19 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_12 = ~_res_hit_lsbMatch_T_11; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_13 = {_res_hit_lsbMatch_T_12[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_14 = ~_res_hit_lsbMatch_T_13; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_15 = _res_hit_lsbMatch_T_14[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_16 = res_hit_lsbMask_1[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_17 = _res_hit_lsbMatch_T_10 ^ _res_hit_lsbMatch_T_15; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_18 = ~_res_hit_lsbMatch_T_16; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_19 = _res_hit_lsbMatch_T_17 & _res_hit_lsbMatch_T_18; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_1 = _res_hit_lsbMatch_T_19 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_14 = res_hit_msbMatch_1 & res_hit_lsbMatch_1; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_15 = io_pmp_6_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_17 = _res_hit_T_16[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_18 = ~_res_hit_T_17; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_6 = {io_pmp_5_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_13; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_13 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_15; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_15 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_16; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_16 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_18; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_18 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_25; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_25 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_21; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_21 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_21; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_21 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_31; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_31 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_36; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_36 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_37; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_37 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_35; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_35 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_42; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_42 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_14 = ~_res_hit_msbsLess_T_13; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_15 = {_res_hit_msbsLess_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_16 = ~_res_hit_msbsLess_T_15; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_17 = _res_hit_msbsLess_T_16[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_2 = _res_hit_msbsLess_T_12 < _res_hit_msbsLess_T_17; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_16 = ~_res_hit_msbsEqual_T_15; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_17 = {_res_hit_msbsEqual_T_16[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_18 = ~_res_hit_msbsEqual_T_17; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_19 = _res_hit_msbsEqual_T_18[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_20 = _res_hit_msbsEqual_T_14 ^ _res_hit_msbsEqual_T_19; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_2 = _res_hit_msbsEqual_T_20 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_15 = _res_hit_lsbsLess_T_14 | _res_hit_T_18; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_17 = ~_res_hit_lsbsLess_T_16; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_18 = {_res_hit_lsbsLess_T_17[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_19 = ~_res_hit_lsbsLess_T_18; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_20 = _res_hit_lsbsLess_T_19[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_2 = _res_hit_lsbsLess_T_15 < _res_hit_lsbsLess_T_20; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_19 = res_hit_msbsEqual_2 & res_hit_lsbsLess_2; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_20 = res_hit_msbsLess_2 | _res_hit_T_19; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_21 = ~_res_hit_T_20; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_20 = ~_res_hit_msbsLess_T_19; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_21 = {_res_hit_msbsLess_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_22 = ~_res_hit_msbsLess_T_21; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_23 = _res_hit_msbsLess_T_22[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_3 = _res_hit_msbsLess_T_18 < _res_hit_msbsLess_T_23; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_23 = ~_res_hit_msbsEqual_T_22; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_24 = {_res_hit_msbsEqual_T_23[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_25 = ~_res_hit_msbsEqual_T_24; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_26 = _res_hit_msbsEqual_T_25[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_27 = _res_hit_msbsEqual_T_21 ^ _res_hit_msbsEqual_T_26; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_3 = _res_hit_msbsEqual_T_27 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_22 = _res_hit_lsbsLess_T_21; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_24 = ~_res_hit_lsbsLess_T_23; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_25 = {_res_hit_lsbsLess_T_24[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_26 = ~_res_hit_lsbsLess_T_25; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_27 = _res_hit_lsbsLess_T_26[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_3 = _res_hit_lsbsLess_T_22 < _res_hit_lsbsLess_T_27; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_22 = res_hit_msbsEqual_3 & res_hit_lsbsLess_3; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_23 = res_hit_msbsLess_3 | _res_hit_T_22; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_24 = _res_hit_T_21 & _res_hit_T_23; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_25 = _res_hit_T_15 & _res_hit_T_24; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_1 = _res_hit_T_13 ? _res_hit_T_14 : _res_hit_T_25; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_1 = ~io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_1 = default_0 & _res_ignore_T_1; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_3 = _res_aligned_lsbMask_T_2[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_1 = ~_res_aligned_lsbMask_T_3; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_19 = ~_res_aligned_straddlesLowerBound_T_18; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_20 = {_res_aligned_straddlesLowerBound_T_19[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_21 = ~_res_aligned_straddlesLowerBound_T_20; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_22 = _res_aligned_straddlesLowerBound_T_21[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_23 = _res_aligned_straddlesLowerBound_T_17 ^ _res_aligned_straddlesLowerBound_T_22; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_24 = _res_aligned_straddlesLowerBound_T_23 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_26 = ~_res_aligned_straddlesLowerBound_T_25; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_27 = {_res_aligned_straddlesLowerBound_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_28 = ~_res_aligned_straddlesLowerBound_T_27; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_29 = _res_aligned_straddlesLowerBound_T_28[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_31 = ~_res_aligned_straddlesLowerBound_T_30; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_32 = _res_aligned_straddlesLowerBound_T_29 & _res_aligned_straddlesLowerBound_T_31; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_33 = |_res_aligned_straddlesLowerBound_T_32; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound_1 = _res_aligned_straddlesLowerBound_T_24 & _res_aligned_straddlesLowerBound_T_33; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_19 = ~_res_aligned_straddlesUpperBound_T_18; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_20 = {_res_aligned_straddlesUpperBound_T_19[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_21 = ~_res_aligned_straddlesUpperBound_T_20; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_22 = _res_aligned_straddlesUpperBound_T_21[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_23 = _res_aligned_straddlesUpperBound_T_17 ^ _res_aligned_straddlesUpperBound_T_22; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_24 = _res_aligned_straddlesUpperBound_T_23 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_26 = ~_res_aligned_straddlesUpperBound_T_25; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_27 = {_res_aligned_straddlesUpperBound_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_28 = ~_res_aligned_straddlesUpperBound_T_27; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_29 = _res_aligned_straddlesUpperBound_T_28[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_31 = _res_aligned_straddlesUpperBound_T_30 | res_aligned_lsbMask_1; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_32 = _res_aligned_straddlesUpperBound_T_29 & _res_aligned_straddlesUpperBound_T_31; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_33 = |_res_aligned_straddlesUpperBound_T_32; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_1 = _res_aligned_straddlesUpperBound_T_24 & _res_aligned_straddlesUpperBound_T_33; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_1 = res_aligned_straddlesLowerBound_1 | res_aligned_straddlesUpperBound_1; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned_1 = ~_res_aligned_rangeAligned_T_1; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_4 = ~_res_aligned_pow2Aligned_T_3; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_5 = res_aligned_lsbMask_1 & _res_aligned_pow2Aligned_T_4; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_1 = _res_aligned_pow2Aligned_T_5 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_1 = _res_aligned_T_1 ? res_aligned_pow2Aligned_1 : res_aligned_rangeAligned_1; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_45 = io_pmp_6_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_7 = io_pmp_6_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_46; // @[PMP.scala:168:32]
assign _res_T_46 = _GEN_7; // @[PMP.scala:168:32]
wire _res_T_65; // @[PMP.scala:177:61]
assign _res_T_65 = _GEN_7; // @[PMP.scala:168:32, :177:61]
wire _res_T_69; // @[PMP.scala:178:63]
assign _res_T_69 = _GEN_7; // @[PMP.scala:168:32, :178:63]
wire _GEN_8 = io_pmp_6_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_47; // @[PMP.scala:168:32]
assign _res_T_47 = _GEN_8; // @[PMP.scala:168:32]
wire _res_T_74; // @[PMP.scala:177:61]
assign _res_T_74 = _GEN_8; // @[PMP.scala:168:32, :177:61]
wire _res_T_78; // @[PMP.scala:178:63]
assign _res_T_78 = _GEN_8; // @[PMP.scala:168:32, :178:63]
wire _res_T_48 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_9 = {io_pmp_6_cfg_x_0, io_pmp_6_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_6; // @[PMP.scala:174:26]
assign res_hi_6 = _GEN_9; // @[PMP.scala:174:26]
wire [1:0] res_hi_7; // @[PMP.scala:174:26]
assign res_hi_7 = _GEN_9; // @[PMP.scala:174:26]
wire [1:0] res_hi_8; // @[PMP.scala:174:26]
assign res_hi_8 = _GEN_9; // @[PMP.scala:174:26]
wire [1:0] res_hi_9; // @[PMP.scala:174:26]
assign res_hi_9 = _GEN_9; // @[PMP.scala:174:26]
wire [1:0] res_hi_10; // @[PMP.scala:174:26]
assign res_hi_10 = _GEN_9; // @[PMP.scala:174:26]
wire [1:0] res_hi_11; // @[PMP.scala:174:26]
assign res_hi_11 = _GEN_9; // @[PMP.scala:174:26]
wire [2:0] _res_T_50 = {res_hi_6, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_51 = _res_T_50 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_52 = {res_hi_7, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_53 = _res_T_52 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_54 = {res_hi_8, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_55 = _res_T_54 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_56 = {res_hi_9, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_57 = _res_T_56 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_58 = {res_hi_10, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_59 = _res_T_58 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_60 = {res_hi_11, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_61 = &_res_T_60; // @[PMP.scala:174:{26,60}]
wire _res_T_62 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22]
wire _res_T_63 = _res_T_62 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_64 = _res_T_63 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_66 = _res_T_64 & _res_T_65; // @[PMP.scala:177:{37,48,61}]
wire _GEN_10 = io_pmp_6_cfg_l_0 & res_hit_1; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_67; // @[PMP.scala:178:32]
assign _res_T_67 = _GEN_10; // @[PMP.scala:178:32]
wire _res_T_76; // @[PMP.scala:178:32]
assign _res_T_76 = _GEN_10; // @[PMP.scala:178:32]
wire _res_T_85; // @[PMP.scala:178:32]
assign _res_T_85 = _GEN_10; // @[PMP.scala:178:32]
wire _res_T_68 = _res_T_67 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_70 = _res_T_68 & _res_T_69; // @[PMP.scala:178:{39,50,63}]
wire _res_T_71 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22]
wire _res_T_72 = _res_T_71 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_73 = _res_T_72 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_75 = _res_T_73 & _res_T_74; // @[PMP.scala:177:{37,48,61}]
wire _res_T_77 = _res_T_76 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_79 = _res_T_77 & _res_T_78; // @[PMP.scala:178:{39,50,63}]
wire _res_T_80 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22]
wire _res_T_81 = _res_T_80 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_82 = _res_T_81 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_83 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_84 = _res_T_82 & _res_T_83; // @[PMP.scala:177:{37,48,61}]
wire _res_T_86 = _res_T_85 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_87 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_88 = _res_T_86 & _res_T_87; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_3; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_3; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_3; // @[PMP.scala:182:26]
wire res_cur_1_cfg_x; // @[PMP.scala:181:23]
wire res_cur_1_cfg_w; // @[PMP.scala:181:23]
wire res_cur_1_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_2 = io_pmp_6_cfg_r_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_3 = res_aligned_1 & _res_cur_cfg_r_T_2; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_1_cfg_r = _res_cur_cfg_r_T_3; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_2 = io_pmp_6_cfg_w_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_3 = res_aligned_1 & _res_cur_cfg_w_T_2; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_1_cfg_w = _res_cur_cfg_w_T_3; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_2 = io_pmp_6_cfg_x_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_3 = res_aligned_1 & _res_cur_cfg_x_T_2; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_1_cfg_x = _res_cur_cfg_x_T_3; // @[PMP.scala:181:23, :184:26]
wire _res_T_89_cfg_l = res_hit_1 ? res_cur_1_cfg_l : _res_T_44_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_89_cfg_a = res_hit_1 ? res_cur_1_cfg_a : _res_T_44_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_89_cfg_x = res_hit_1 ? res_cur_1_cfg_x : _res_T_44_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_89_cfg_w = res_hit_1 ? res_cur_1_cfg_w : _res_T_44_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_89_cfg_r = res_hit_1 ? res_cur_1_cfg_r : _res_T_44_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_89_addr = res_hit_1 ? res_cur_1_addr : _res_T_44_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_89_mask = res_hit_1 ? res_cur_1_mask : _res_T_44_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_26 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_2 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_7 = _res_hit_lsbMask_T_6[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_8 = ~_res_hit_lsbMask_T_7; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_26 = io_pmp_5_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_6 = io_pmp_5_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_2 = {_res_hit_msbMatch_T_26, _res_aligned_pow2Aligned_T_6 | _res_hit_lsbMask_T_8}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_22 = ~_res_hit_msbMatch_T_21; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_23 = {_res_hit_msbMatch_T_22[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_24 = ~_res_hit_msbMatch_T_23; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_25 = _res_hit_msbMatch_T_24[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_27 = _res_hit_msbMatch_T_20 ^ _res_hit_msbMatch_T_25; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_28 = ~_res_hit_msbMatch_T_26; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_29 = _res_hit_msbMatch_T_27 & _res_hit_msbMatch_T_28; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_2 = _res_hit_msbMatch_T_29 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_22 = ~_res_hit_lsbMatch_T_21; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_23 = {_res_hit_lsbMatch_T_22[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_24 = ~_res_hit_lsbMatch_T_23; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_25 = _res_hit_lsbMatch_T_24[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_26 = res_hit_lsbMask_2[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_27 = _res_hit_lsbMatch_T_20 ^ _res_hit_lsbMatch_T_25; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_28 = ~_res_hit_lsbMatch_T_26; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_29 = _res_hit_lsbMatch_T_27 & _res_hit_lsbMatch_T_28; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_2 = _res_hit_lsbMatch_T_29 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_27 = res_hit_msbMatch_2 & res_hit_lsbMatch_2; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_28 = io_pmp_5_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_30 = _res_hit_T_29[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_31 = ~_res_hit_T_30; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_11 = {io_pmp_4_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_25; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_25 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_29; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_29 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_30; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_30 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_35; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_35 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_42; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_42 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_31; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_31 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_31; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_31 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_43; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_43 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_50; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_50 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_51; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_51 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_52; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_52 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_59; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_59 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_26 = ~_res_hit_msbsLess_T_25; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_27 = {_res_hit_msbsLess_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_28 = ~_res_hit_msbsLess_T_27; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_29 = _res_hit_msbsLess_T_28[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_4 = _res_hit_msbsLess_T_24 < _res_hit_msbsLess_T_29; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_30 = ~_res_hit_msbsEqual_T_29; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_31 = {_res_hit_msbsEqual_T_30[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_32 = ~_res_hit_msbsEqual_T_31; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_33 = _res_hit_msbsEqual_T_32[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_34 = _res_hit_msbsEqual_T_28 ^ _res_hit_msbsEqual_T_33; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_4 = _res_hit_msbsEqual_T_34 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_29 = _res_hit_lsbsLess_T_28 | _res_hit_T_31; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_31 = ~_res_hit_lsbsLess_T_30; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_32 = {_res_hit_lsbsLess_T_31[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_33 = ~_res_hit_lsbsLess_T_32; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_34 = _res_hit_lsbsLess_T_33[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_4 = _res_hit_lsbsLess_T_29 < _res_hit_lsbsLess_T_34; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_32 = res_hit_msbsEqual_4 & res_hit_lsbsLess_4; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_33 = res_hit_msbsLess_4 | _res_hit_T_32; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_34 = ~_res_hit_T_33; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_32 = ~_res_hit_msbsLess_T_31; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_33 = {_res_hit_msbsLess_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_34 = ~_res_hit_msbsLess_T_33; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_35 = _res_hit_msbsLess_T_34[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_5 = _res_hit_msbsLess_T_30 < _res_hit_msbsLess_T_35; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_37 = ~_res_hit_msbsEqual_T_36; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_38 = {_res_hit_msbsEqual_T_37[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_39 = ~_res_hit_msbsEqual_T_38; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_40 = _res_hit_msbsEqual_T_39[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_41 = _res_hit_msbsEqual_T_35 ^ _res_hit_msbsEqual_T_40; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_5 = _res_hit_msbsEqual_T_41 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_36 = _res_hit_lsbsLess_T_35; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_38 = ~_res_hit_lsbsLess_T_37; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_39 = {_res_hit_lsbsLess_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_40 = ~_res_hit_lsbsLess_T_39; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_41 = _res_hit_lsbsLess_T_40[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_5 = _res_hit_lsbsLess_T_36 < _res_hit_lsbsLess_T_41; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_35 = res_hit_msbsEqual_5 & res_hit_lsbsLess_5; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_36 = res_hit_msbsLess_5 | _res_hit_T_35; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_37 = _res_hit_T_34 & _res_hit_T_36; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_38 = _res_hit_T_28 & _res_hit_T_37; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_2 = _res_hit_T_26 ? _res_hit_T_27 : _res_hit_T_38; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_2 = ~io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_2 = default_0 & _res_ignore_T_2; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_5 = _res_aligned_lsbMask_T_4[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_2 = ~_res_aligned_lsbMask_T_5; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_36 = ~_res_aligned_straddlesLowerBound_T_35; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_37 = {_res_aligned_straddlesLowerBound_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_38 = ~_res_aligned_straddlesLowerBound_T_37; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_39 = _res_aligned_straddlesLowerBound_T_38[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_40 = _res_aligned_straddlesLowerBound_T_34 ^ _res_aligned_straddlesLowerBound_T_39; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_41 = _res_aligned_straddlesLowerBound_T_40 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_43 = ~_res_aligned_straddlesLowerBound_T_42; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_44 = {_res_aligned_straddlesLowerBound_T_43[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_45 = ~_res_aligned_straddlesLowerBound_T_44; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_46 = _res_aligned_straddlesLowerBound_T_45[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_48 = ~_res_aligned_straddlesLowerBound_T_47; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_49 = _res_aligned_straddlesLowerBound_T_46 & _res_aligned_straddlesLowerBound_T_48; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_50 = |_res_aligned_straddlesLowerBound_T_49; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound_2 = _res_aligned_straddlesLowerBound_T_41 & _res_aligned_straddlesLowerBound_T_50; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_36 = ~_res_aligned_straddlesUpperBound_T_35; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_37 = {_res_aligned_straddlesUpperBound_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_38 = ~_res_aligned_straddlesUpperBound_T_37; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_39 = _res_aligned_straddlesUpperBound_T_38[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_40 = _res_aligned_straddlesUpperBound_T_34 ^ _res_aligned_straddlesUpperBound_T_39; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_41 = _res_aligned_straddlesUpperBound_T_40 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_43 = ~_res_aligned_straddlesUpperBound_T_42; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_44 = {_res_aligned_straddlesUpperBound_T_43[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_45 = ~_res_aligned_straddlesUpperBound_T_44; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_46 = _res_aligned_straddlesUpperBound_T_45[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_48 = _res_aligned_straddlesUpperBound_T_47 | res_aligned_lsbMask_2; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_49 = _res_aligned_straddlesUpperBound_T_46 & _res_aligned_straddlesUpperBound_T_48; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_50 = |_res_aligned_straddlesUpperBound_T_49; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_2 = _res_aligned_straddlesUpperBound_T_41 & _res_aligned_straddlesUpperBound_T_50; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_2 = res_aligned_straddlesLowerBound_2 | res_aligned_straddlesUpperBound_2; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned_2 = ~_res_aligned_rangeAligned_T_2; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_7 = ~_res_aligned_pow2Aligned_T_6; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_8 = res_aligned_lsbMask_2 & _res_aligned_pow2Aligned_T_7; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_2 = _res_aligned_pow2Aligned_T_8 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_2 = _res_aligned_T_2 ? res_aligned_pow2Aligned_2 : res_aligned_rangeAligned_2; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_90 = io_pmp_5_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_12 = io_pmp_5_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_91; // @[PMP.scala:168:32]
assign _res_T_91 = _GEN_12; // @[PMP.scala:168:32]
wire _res_T_110; // @[PMP.scala:177:61]
assign _res_T_110 = _GEN_12; // @[PMP.scala:168:32, :177:61]
wire _res_T_114; // @[PMP.scala:178:63]
assign _res_T_114 = _GEN_12; // @[PMP.scala:168:32, :178:63]
wire _GEN_13 = io_pmp_5_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_92; // @[PMP.scala:168:32]
assign _res_T_92 = _GEN_13; // @[PMP.scala:168:32]
wire _res_T_119; // @[PMP.scala:177:61]
assign _res_T_119 = _GEN_13; // @[PMP.scala:168:32, :177:61]
wire _res_T_123; // @[PMP.scala:178:63]
assign _res_T_123 = _GEN_13; // @[PMP.scala:168:32, :178:63]
wire _res_T_93 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_14 = {io_pmp_5_cfg_x_0, io_pmp_5_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_12; // @[PMP.scala:174:26]
assign res_hi_12 = _GEN_14; // @[PMP.scala:174:26]
wire [1:0] res_hi_13; // @[PMP.scala:174:26]
assign res_hi_13 = _GEN_14; // @[PMP.scala:174:26]
wire [1:0] res_hi_14; // @[PMP.scala:174:26]
assign res_hi_14 = _GEN_14; // @[PMP.scala:174:26]
wire [1:0] res_hi_15; // @[PMP.scala:174:26]
assign res_hi_15 = _GEN_14; // @[PMP.scala:174:26]
wire [1:0] res_hi_16; // @[PMP.scala:174:26]
assign res_hi_16 = _GEN_14; // @[PMP.scala:174:26]
wire [1:0] res_hi_17; // @[PMP.scala:174:26]
assign res_hi_17 = _GEN_14; // @[PMP.scala:174:26]
wire [2:0] _res_T_95 = {res_hi_12, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_96 = _res_T_95 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_97 = {res_hi_13, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_98 = _res_T_97 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_99 = {res_hi_14, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_100 = _res_T_99 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_101 = {res_hi_15, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_102 = _res_T_101 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_103 = {res_hi_16, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_104 = _res_T_103 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_105 = {res_hi_17, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_106 = &_res_T_105; // @[PMP.scala:174:{26,60}]
wire _res_T_107 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22]
wire _res_T_108 = _res_T_107 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_109 = _res_T_108 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_111 = _res_T_109 & _res_T_110; // @[PMP.scala:177:{37,48,61}]
wire _GEN_15 = io_pmp_5_cfg_l_0 & res_hit_2; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_112; // @[PMP.scala:178:32]
assign _res_T_112 = _GEN_15; // @[PMP.scala:178:32]
wire _res_T_121; // @[PMP.scala:178:32]
assign _res_T_121 = _GEN_15; // @[PMP.scala:178:32]
wire _res_T_130; // @[PMP.scala:178:32]
assign _res_T_130 = _GEN_15; // @[PMP.scala:178:32]
wire _res_T_113 = _res_T_112 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_115 = _res_T_113 & _res_T_114; // @[PMP.scala:178:{39,50,63}]
wire _res_T_116 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22]
wire _res_T_117 = _res_T_116 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_118 = _res_T_117 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_120 = _res_T_118 & _res_T_119; // @[PMP.scala:177:{37,48,61}]
wire _res_T_122 = _res_T_121 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_124 = _res_T_122 & _res_T_123; // @[PMP.scala:178:{39,50,63}]
wire _res_T_125 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22]
wire _res_T_126 = _res_T_125 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_127 = _res_T_126 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_128 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_129 = _res_T_127 & _res_T_128; // @[PMP.scala:177:{37,48,61}]
wire _res_T_131 = _res_T_130 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_132 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_133 = _res_T_131 & _res_T_132; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_5; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_5; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_5; // @[PMP.scala:182:26]
wire res_cur_2_cfg_x; // @[PMP.scala:181:23]
wire res_cur_2_cfg_w; // @[PMP.scala:181:23]
wire res_cur_2_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_4 = io_pmp_5_cfg_r_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_5 = res_aligned_2 & _res_cur_cfg_r_T_4; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_2_cfg_r = _res_cur_cfg_r_T_5; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_4 = io_pmp_5_cfg_w_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_5 = res_aligned_2 & _res_cur_cfg_w_T_4; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_2_cfg_w = _res_cur_cfg_w_T_5; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_4 = io_pmp_5_cfg_x_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_5 = res_aligned_2 & _res_cur_cfg_x_T_4; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_2_cfg_x = _res_cur_cfg_x_T_5; // @[PMP.scala:181:23, :184:26]
wire _res_T_134_cfg_l = res_hit_2 ? res_cur_2_cfg_l : _res_T_89_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_134_cfg_a = res_hit_2 ? res_cur_2_cfg_a : _res_T_89_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_134_cfg_x = res_hit_2 ? res_cur_2_cfg_x : _res_T_89_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_134_cfg_w = res_hit_2 ? res_cur_2_cfg_w : _res_T_89_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_134_cfg_r = res_hit_2 ? res_cur_2_cfg_r : _res_T_89_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_134_addr = res_hit_2 ? res_cur_2_addr : _res_T_89_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_134_mask = res_hit_2 ? res_cur_2_mask : _res_T_89_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_39 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_3 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_10 = _res_hit_lsbMask_T_9[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_11 = ~_res_hit_lsbMask_T_10; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_36 = io_pmp_4_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_9 = io_pmp_4_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_3 = {_res_hit_msbMatch_T_36, _res_aligned_pow2Aligned_T_9 | _res_hit_lsbMask_T_11}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_32 = ~_res_hit_msbMatch_T_31; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_33 = {_res_hit_msbMatch_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_34 = ~_res_hit_msbMatch_T_33; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_35 = _res_hit_msbMatch_T_34[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_37 = _res_hit_msbMatch_T_30 ^ _res_hit_msbMatch_T_35; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_38 = ~_res_hit_msbMatch_T_36; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_39 = _res_hit_msbMatch_T_37 & _res_hit_msbMatch_T_38; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_3 = _res_hit_msbMatch_T_39 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_32 = ~_res_hit_lsbMatch_T_31; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_33 = {_res_hit_lsbMatch_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_34 = ~_res_hit_lsbMatch_T_33; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_35 = _res_hit_lsbMatch_T_34[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_36 = res_hit_lsbMask_3[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_37 = _res_hit_lsbMatch_T_30 ^ _res_hit_lsbMatch_T_35; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_38 = ~_res_hit_lsbMatch_T_36; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_39 = _res_hit_lsbMatch_T_37 & _res_hit_lsbMatch_T_38; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_3 = _res_hit_lsbMatch_T_39 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_40 = res_hit_msbMatch_3 & res_hit_lsbMatch_3; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_41 = io_pmp_4_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_43 = _res_hit_T_42[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_44 = ~_res_hit_T_43; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_16 = {io_pmp_3_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_37; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_37 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_43; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_43 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_44; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_44 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_52; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_52 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_59; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_59 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_41; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_41 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_41; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_41 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_55; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_55 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_64; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_64 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_65; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_65 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_69; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_69 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_76; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_76 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_38 = ~_res_hit_msbsLess_T_37; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_39 = {_res_hit_msbsLess_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_40 = ~_res_hit_msbsLess_T_39; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_41 = _res_hit_msbsLess_T_40[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_6 = _res_hit_msbsLess_T_36 < _res_hit_msbsLess_T_41; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_44 = ~_res_hit_msbsEqual_T_43; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_45 = {_res_hit_msbsEqual_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_46 = ~_res_hit_msbsEqual_T_45; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_47 = _res_hit_msbsEqual_T_46[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_48 = _res_hit_msbsEqual_T_42 ^ _res_hit_msbsEqual_T_47; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_6 = _res_hit_msbsEqual_T_48 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_43 = _res_hit_lsbsLess_T_42 | _res_hit_T_44; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_45 = ~_res_hit_lsbsLess_T_44; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_46 = {_res_hit_lsbsLess_T_45[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_47 = ~_res_hit_lsbsLess_T_46; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_48 = _res_hit_lsbsLess_T_47[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_6 = _res_hit_lsbsLess_T_43 < _res_hit_lsbsLess_T_48; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_45 = res_hit_msbsEqual_6 & res_hit_lsbsLess_6; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_46 = res_hit_msbsLess_6 | _res_hit_T_45; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_47 = ~_res_hit_T_46; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_44 = ~_res_hit_msbsLess_T_43; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_45 = {_res_hit_msbsLess_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_46 = ~_res_hit_msbsLess_T_45; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_47 = _res_hit_msbsLess_T_46[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_7 = _res_hit_msbsLess_T_42 < _res_hit_msbsLess_T_47; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_51 = ~_res_hit_msbsEqual_T_50; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_52 = {_res_hit_msbsEqual_T_51[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_53 = ~_res_hit_msbsEqual_T_52; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_54 = _res_hit_msbsEqual_T_53[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_55 = _res_hit_msbsEqual_T_49 ^ _res_hit_msbsEqual_T_54; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_7 = _res_hit_msbsEqual_T_55 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_50 = _res_hit_lsbsLess_T_49; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_52 = ~_res_hit_lsbsLess_T_51; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_53 = {_res_hit_lsbsLess_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_54 = ~_res_hit_lsbsLess_T_53; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_55 = _res_hit_lsbsLess_T_54[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_7 = _res_hit_lsbsLess_T_50 < _res_hit_lsbsLess_T_55; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_48 = res_hit_msbsEqual_7 & res_hit_lsbsLess_7; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_49 = res_hit_msbsLess_7 | _res_hit_T_48; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_50 = _res_hit_T_47 & _res_hit_T_49; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_51 = _res_hit_T_41 & _res_hit_T_50; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_3 = _res_hit_T_39 ? _res_hit_T_40 : _res_hit_T_51; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_3 = ~io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_3 = default_0 & _res_ignore_T_3; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_7 = _res_aligned_lsbMask_T_6[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_3 = ~_res_aligned_lsbMask_T_7; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_53 = ~_res_aligned_straddlesLowerBound_T_52; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_54 = {_res_aligned_straddlesLowerBound_T_53[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_55 = ~_res_aligned_straddlesLowerBound_T_54; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_56 = _res_aligned_straddlesLowerBound_T_55[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_57 = _res_aligned_straddlesLowerBound_T_51 ^ _res_aligned_straddlesLowerBound_T_56; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_58 = _res_aligned_straddlesLowerBound_T_57 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_60 = ~_res_aligned_straddlesLowerBound_T_59; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_61 = {_res_aligned_straddlesLowerBound_T_60[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_62 = ~_res_aligned_straddlesLowerBound_T_61; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_63 = _res_aligned_straddlesLowerBound_T_62[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_65 = ~_res_aligned_straddlesLowerBound_T_64; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_66 = _res_aligned_straddlesLowerBound_T_63 & _res_aligned_straddlesLowerBound_T_65; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_67 = |_res_aligned_straddlesLowerBound_T_66; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound_3 = _res_aligned_straddlesLowerBound_T_58 & _res_aligned_straddlesLowerBound_T_67; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_53 = ~_res_aligned_straddlesUpperBound_T_52; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_54 = {_res_aligned_straddlesUpperBound_T_53[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_55 = ~_res_aligned_straddlesUpperBound_T_54; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_56 = _res_aligned_straddlesUpperBound_T_55[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_57 = _res_aligned_straddlesUpperBound_T_51 ^ _res_aligned_straddlesUpperBound_T_56; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_58 = _res_aligned_straddlesUpperBound_T_57 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_60 = ~_res_aligned_straddlesUpperBound_T_59; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_61 = {_res_aligned_straddlesUpperBound_T_60[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_62 = ~_res_aligned_straddlesUpperBound_T_61; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_63 = _res_aligned_straddlesUpperBound_T_62[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_65 = _res_aligned_straddlesUpperBound_T_64 | res_aligned_lsbMask_3; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_66 = _res_aligned_straddlesUpperBound_T_63 & _res_aligned_straddlesUpperBound_T_65; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_67 = |_res_aligned_straddlesUpperBound_T_66; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_3 = _res_aligned_straddlesUpperBound_T_58 & _res_aligned_straddlesUpperBound_T_67; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_3 = res_aligned_straddlesLowerBound_3 | res_aligned_straddlesUpperBound_3; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned_3 = ~_res_aligned_rangeAligned_T_3; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_10 = ~_res_aligned_pow2Aligned_T_9; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_11 = res_aligned_lsbMask_3 & _res_aligned_pow2Aligned_T_10; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_3 = _res_aligned_pow2Aligned_T_11 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_3 = _res_aligned_T_3 ? res_aligned_pow2Aligned_3 : res_aligned_rangeAligned_3; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_135 = io_pmp_4_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_17 = io_pmp_4_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_136; // @[PMP.scala:168:32]
assign _res_T_136 = _GEN_17; // @[PMP.scala:168:32]
wire _res_T_155; // @[PMP.scala:177:61]
assign _res_T_155 = _GEN_17; // @[PMP.scala:168:32, :177:61]
wire _res_T_159; // @[PMP.scala:178:63]
assign _res_T_159 = _GEN_17; // @[PMP.scala:168:32, :178:63]
wire _GEN_18 = io_pmp_4_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_137; // @[PMP.scala:168:32]
assign _res_T_137 = _GEN_18; // @[PMP.scala:168:32]
wire _res_T_164; // @[PMP.scala:177:61]
assign _res_T_164 = _GEN_18; // @[PMP.scala:168:32, :177:61]
wire _res_T_168; // @[PMP.scala:178:63]
assign _res_T_168 = _GEN_18; // @[PMP.scala:168:32, :178:63]
wire _res_T_138 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_19 = {io_pmp_4_cfg_x_0, io_pmp_4_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_18; // @[PMP.scala:174:26]
assign res_hi_18 = _GEN_19; // @[PMP.scala:174:26]
wire [1:0] res_hi_19; // @[PMP.scala:174:26]
assign res_hi_19 = _GEN_19; // @[PMP.scala:174:26]
wire [1:0] res_hi_20; // @[PMP.scala:174:26]
assign res_hi_20 = _GEN_19; // @[PMP.scala:174:26]
wire [1:0] res_hi_21; // @[PMP.scala:174:26]
assign res_hi_21 = _GEN_19; // @[PMP.scala:174:26]
wire [1:0] res_hi_22; // @[PMP.scala:174:26]
assign res_hi_22 = _GEN_19; // @[PMP.scala:174:26]
wire [1:0] res_hi_23; // @[PMP.scala:174:26]
assign res_hi_23 = _GEN_19; // @[PMP.scala:174:26]
wire [2:0] _res_T_140 = {res_hi_18, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_141 = _res_T_140 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_142 = {res_hi_19, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_143 = _res_T_142 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_144 = {res_hi_20, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_145 = _res_T_144 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_146 = {res_hi_21, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_147 = _res_T_146 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_148 = {res_hi_22, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_149 = _res_T_148 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_150 = {res_hi_23, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_151 = &_res_T_150; // @[PMP.scala:174:{26,60}]
wire _res_T_152 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22]
wire _res_T_153 = _res_T_152 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_154 = _res_T_153 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_156 = _res_T_154 & _res_T_155; // @[PMP.scala:177:{37,48,61}]
wire _GEN_20 = io_pmp_4_cfg_l_0 & res_hit_3; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_157; // @[PMP.scala:178:32]
assign _res_T_157 = _GEN_20; // @[PMP.scala:178:32]
wire _res_T_166; // @[PMP.scala:178:32]
assign _res_T_166 = _GEN_20; // @[PMP.scala:178:32]
wire _res_T_175; // @[PMP.scala:178:32]
assign _res_T_175 = _GEN_20; // @[PMP.scala:178:32]
wire _res_T_158 = _res_T_157 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_160 = _res_T_158 & _res_T_159; // @[PMP.scala:178:{39,50,63}]
wire _res_T_161 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22]
wire _res_T_162 = _res_T_161 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_163 = _res_T_162 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_165 = _res_T_163 & _res_T_164; // @[PMP.scala:177:{37,48,61}]
wire _res_T_167 = _res_T_166 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_169 = _res_T_167 & _res_T_168; // @[PMP.scala:178:{39,50,63}]
wire _res_T_170 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22]
wire _res_T_171 = _res_T_170 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_172 = _res_T_171 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_173 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_174 = _res_T_172 & _res_T_173; // @[PMP.scala:177:{37,48,61}]
wire _res_T_176 = _res_T_175 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_177 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_178 = _res_T_176 & _res_T_177; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_7; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_7; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_7; // @[PMP.scala:182:26]
wire res_cur_3_cfg_x; // @[PMP.scala:181:23]
wire res_cur_3_cfg_w; // @[PMP.scala:181:23]
wire res_cur_3_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_6 = io_pmp_4_cfg_r_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_7 = res_aligned_3 & _res_cur_cfg_r_T_6; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_3_cfg_r = _res_cur_cfg_r_T_7; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_6 = io_pmp_4_cfg_w_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_7 = res_aligned_3 & _res_cur_cfg_w_T_6; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_3_cfg_w = _res_cur_cfg_w_T_7; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_6 = io_pmp_4_cfg_x_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_7 = res_aligned_3 & _res_cur_cfg_x_T_6; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_3_cfg_x = _res_cur_cfg_x_T_7; // @[PMP.scala:181:23, :184:26]
wire _res_T_179_cfg_l = res_hit_3 ? res_cur_3_cfg_l : _res_T_134_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_179_cfg_a = res_hit_3 ? res_cur_3_cfg_a : _res_T_134_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_179_cfg_x = res_hit_3 ? res_cur_3_cfg_x : _res_T_134_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_179_cfg_w = res_hit_3 ? res_cur_3_cfg_w : _res_T_134_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_179_cfg_r = res_hit_3 ? res_cur_3_cfg_r : _res_T_134_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_179_addr = res_hit_3 ? res_cur_3_addr : _res_T_134_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_179_mask = res_hit_3 ? res_cur_3_mask : _res_T_134_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_52 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_4 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_13 = _res_hit_lsbMask_T_12[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_14 = ~_res_hit_lsbMask_T_13; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_46 = io_pmp_3_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_12 = io_pmp_3_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_4 = {_res_hit_msbMatch_T_46, _res_aligned_pow2Aligned_T_12 | _res_hit_lsbMask_T_14}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_42 = ~_res_hit_msbMatch_T_41; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_43 = {_res_hit_msbMatch_T_42[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_44 = ~_res_hit_msbMatch_T_43; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_45 = _res_hit_msbMatch_T_44[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_47 = _res_hit_msbMatch_T_40 ^ _res_hit_msbMatch_T_45; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_48 = ~_res_hit_msbMatch_T_46; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_49 = _res_hit_msbMatch_T_47 & _res_hit_msbMatch_T_48; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_4 = _res_hit_msbMatch_T_49 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_42 = ~_res_hit_lsbMatch_T_41; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_43 = {_res_hit_lsbMatch_T_42[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_44 = ~_res_hit_lsbMatch_T_43; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_45 = _res_hit_lsbMatch_T_44[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_46 = res_hit_lsbMask_4[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_47 = _res_hit_lsbMatch_T_40 ^ _res_hit_lsbMatch_T_45; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_48 = ~_res_hit_lsbMatch_T_46; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_49 = _res_hit_lsbMatch_T_47 & _res_hit_lsbMatch_T_48; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_4 = _res_hit_lsbMatch_T_49 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_53 = res_hit_msbMatch_4 & res_hit_lsbMatch_4; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_54 = io_pmp_3_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_56 = _res_hit_T_55[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_57 = ~_res_hit_T_56; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_21 = {io_pmp_2_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_49; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_49 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_57; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_57 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_58; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_58 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_69; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_69 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_76; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_76 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_51; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_51 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_51; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_51 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_67; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_67 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_78; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_78 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_79; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_79 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_86; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_86 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_93; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_93 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_50 = ~_res_hit_msbsLess_T_49; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_51 = {_res_hit_msbsLess_T_50[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_52 = ~_res_hit_msbsLess_T_51; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_53 = _res_hit_msbsLess_T_52[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_8 = _res_hit_msbsLess_T_48 < _res_hit_msbsLess_T_53; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_58 = ~_res_hit_msbsEqual_T_57; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_59 = {_res_hit_msbsEqual_T_58[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_60 = ~_res_hit_msbsEqual_T_59; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_61 = _res_hit_msbsEqual_T_60[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_62 = _res_hit_msbsEqual_T_56 ^ _res_hit_msbsEqual_T_61; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_8 = _res_hit_msbsEqual_T_62 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_57 = _res_hit_lsbsLess_T_56 | _res_hit_T_57; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_59 = ~_res_hit_lsbsLess_T_58; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_60 = {_res_hit_lsbsLess_T_59[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_61 = ~_res_hit_lsbsLess_T_60; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_62 = _res_hit_lsbsLess_T_61[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_8 = _res_hit_lsbsLess_T_57 < _res_hit_lsbsLess_T_62; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_58 = res_hit_msbsEqual_8 & res_hit_lsbsLess_8; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_59 = res_hit_msbsLess_8 | _res_hit_T_58; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_60 = ~_res_hit_T_59; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_56 = ~_res_hit_msbsLess_T_55; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_57 = {_res_hit_msbsLess_T_56[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_58 = ~_res_hit_msbsLess_T_57; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_59 = _res_hit_msbsLess_T_58[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_9 = _res_hit_msbsLess_T_54 < _res_hit_msbsLess_T_59; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_65 = ~_res_hit_msbsEqual_T_64; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_66 = {_res_hit_msbsEqual_T_65[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_67 = ~_res_hit_msbsEqual_T_66; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_68 = _res_hit_msbsEqual_T_67[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_69 = _res_hit_msbsEqual_T_63 ^ _res_hit_msbsEqual_T_68; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_9 = _res_hit_msbsEqual_T_69 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_64 = _res_hit_lsbsLess_T_63; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_66 = ~_res_hit_lsbsLess_T_65; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_67 = {_res_hit_lsbsLess_T_66[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_68 = ~_res_hit_lsbsLess_T_67; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_69 = _res_hit_lsbsLess_T_68[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_9 = _res_hit_lsbsLess_T_64 < _res_hit_lsbsLess_T_69; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_61 = res_hit_msbsEqual_9 & res_hit_lsbsLess_9; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_62 = res_hit_msbsLess_9 | _res_hit_T_61; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_63 = _res_hit_T_60 & _res_hit_T_62; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_64 = _res_hit_T_54 & _res_hit_T_63; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_4 = _res_hit_T_52 ? _res_hit_T_53 : _res_hit_T_64; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_4 = ~io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_4 = default_0 & _res_ignore_T_4; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_9 = _res_aligned_lsbMask_T_8[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_4 = ~_res_aligned_lsbMask_T_9; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_70 = ~_res_aligned_straddlesLowerBound_T_69; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_71 = {_res_aligned_straddlesLowerBound_T_70[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_72 = ~_res_aligned_straddlesLowerBound_T_71; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_73 = _res_aligned_straddlesLowerBound_T_72[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_74 = _res_aligned_straddlesLowerBound_T_68 ^ _res_aligned_straddlesLowerBound_T_73; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_75 = _res_aligned_straddlesLowerBound_T_74 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_77 = ~_res_aligned_straddlesLowerBound_T_76; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_78 = {_res_aligned_straddlesLowerBound_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_79 = ~_res_aligned_straddlesLowerBound_T_78; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_80 = _res_aligned_straddlesLowerBound_T_79[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_82 = ~_res_aligned_straddlesLowerBound_T_81; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_83 = _res_aligned_straddlesLowerBound_T_80 & _res_aligned_straddlesLowerBound_T_82; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_84 = |_res_aligned_straddlesLowerBound_T_83; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound_4 = _res_aligned_straddlesLowerBound_T_75 & _res_aligned_straddlesLowerBound_T_84; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_70 = ~_res_aligned_straddlesUpperBound_T_69; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_71 = {_res_aligned_straddlesUpperBound_T_70[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_72 = ~_res_aligned_straddlesUpperBound_T_71; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_73 = _res_aligned_straddlesUpperBound_T_72[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_74 = _res_aligned_straddlesUpperBound_T_68 ^ _res_aligned_straddlesUpperBound_T_73; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_75 = _res_aligned_straddlesUpperBound_T_74 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_77 = ~_res_aligned_straddlesUpperBound_T_76; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_78 = {_res_aligned_straddlesUpperBound_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_79 = ~_res_aligned_straddlesUpperBound_T_78; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_80 = _res_aligned_straddlesUpperBound_T_79[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_82 = _res_aligned_straddlesUpperBound_T_81 | res_aligned_lsbMask_4; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_83 = _res_aligned_straddlesUpperBound_T_80 & _res_aligned_straddlesUpperBound_T_82; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_84 = |_res_aligned_straddlesUpperBound_T_83; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_4 = _res_aligned_straddlesUpperBound_T_75 & _res_aligned_straddlesUpperBound_T_84; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_4 = res_aligned_straddlesLowerBound_4 | res_aligned_straddlesUpperBound_4; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned_4 = ~_res_aligned_rangeAligned_T_4; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_13 = ~_res_aligned_pow2Aligned_T_12; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_14 = res_aligned_lsbMask_4 & _res_aligned_pow2Aligned_T_13; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_4 = _res_aligned_pow2Aligned_T_14 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_4 = _res_aligned_T_4 ? res_aligned_pow2Aligned_4 : res_aligned_rangeAligned_4; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_180 = io_pmp_3_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_22 = io_pmp_3_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_181; // @[PMP.scala:168:32]
assign _res_T_181 = _GEN_22; // @[PMP.scala:168:32]
wire _res_T_200; // @[PMP.scala:177:61]
assign _res_T_200 = _GEN_22; // @[PMP.scala:168:32, :177:61]
wire _res_T_204; // @[PMP.scala:178:63]
assign _res_T_204 = _GEN_22; // @[PMP.scala:168:32, :178:63]
wire _GEN_23 = io_pmp_3_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_182; // @[PMP.scala:168:32]
assign _res_T_182 = _GEN_23; // @[PMP.scala:168:32]
wire _res_T_209; // @[PMP.scala:177:61]
assign _res_T_209 = _GEN_23; // @[PMP.scala:168:32, :177:61]
wire _res_T_213; // @[PMP.scala:178:63]
assign _res_T_213 = _GEN_23; // @[PMP.scala:168:32, :178:63]
wire _res_T_183 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_24 = {io_pmp_3_cfg_x_0, io_pmp_3_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_24; // @[PMP.scala:174:26]
assign res_hi_24 = _GEN_24; // @[PMP.scala:174:26]
wire [1:0] res_hi_25; // @[PMP.scala:174:26]
assign res_hi_25 = _GEN_24; // @[PMP.scala:174:26]
wire [1:0] res_hi_26; // @[PMP.scala:174:26]
assign res_hi_26 = _GEN_24; // @[PMP.scala:174:26]
wire [1:0] res_hi_27; // @[PMP.scala:174:26]
assign res_hi_27 = _GEN_24; // @[PMP.scala:174:26]
wire [1:0] res_hi_28; // @[PMP.scala:174:26]
assign res_hi_28 = _GEN_24; // @[PMP.scala:174:26]
wire [1:0] res_hi_29; // @[PMP.scala:174:26]
assign res_hi_29 = _GEN_24; // @[PMP.scala:174:26]
wire [2:0] _res_T_185 = {res_hi_24, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_186 = _res_T_185 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_187 = {res_hi_25, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_188 = _res_T_187 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_189 = {res_hi_26, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_190 = _res_T_189 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_191 = {res_hi_27, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_192 = _res_T_191 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_193 = {res_hi_28, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_194 = _res_T_193 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_195 = {res_hi_29, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_196 = &_res_T_195; // @[PMP.scala:174:{26,60}]
wire _res_T_197 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22]
wire _res_T_198 = _res_T_197 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_199 = _res_T_198 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_201 = _res_T_199 & _res_T_200; // @[PMP.scala:177:{37,48,61}]
wire _GEN_25 = io_pmp_3_cfg_l_0 & res_hit_4; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_202; // @[PMP.scala:178:32]
assign _res_T_202 = _GEN_25; // @[PMP.scala:178:32]
wire _res_T_211; // @[PMP.scala:178:32]
assign _res_T_211 = _GEN_25; // @[PMP.scala:178:32]
wire _res_T_220; // @[PMP.scala:178:32]
assign _res_T_220 = _GEN_25; // @[PMP.scala:178:32]
wire _res_T_203 = _res_T_202 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_205 = _res_T_203 & _res_T_204; // @[PMP.scala:178:{39,50,63}]
wire _res_T_206 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22]
wire _res_T_207 = _res_T_206 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_208 = _res_T_207 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_210 = _res_T_208 & _res_T_209; // @[PMP.scala:177:{37,48,61}]
wire _res_T_212 = _res_T_211 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_214 = _res_T_212 & _res_T_213; // @[PMP.scala:178:{39,50,63}]
wire _res_T_215 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22]
wire _res_T_216 = _res_T_215 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_217 = _res_T_216 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_218 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_219 = _res_T_217 & _res_T_218; // @[PMP.scala:177:{37,48,61}]
wire _res_T_221 = _res_T_220 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_222 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_223 = _res_T_221 & _res_T_222; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_9; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_9; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_9; // @[PMP.scala:182:26]
wire res_cur_4_cfg_x; // @[PMP.scala:181:23]
wire res_cur_4_cfg_w; // @[PMP.scala:181:23]
wire res_cur_4_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_8 = io_pmp_3_cfg_r_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_9 = res_aligned_4 & _res_cur_cfg_r_T_8; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_4_cfg_r = _res_cur_cfg_r_T_9; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_8 = io_pmp_3_cfg_w_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_9 = res_aligned_4 & _res_cur_cfg_w_T_8; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_4_cfg_w = _res_cur_cfg_w_T_9; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_8 = io_pmp_3_cfg_x_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_9 = res_aligned_4 & _res_cur_cfg_x_T_8; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_4_cfg_x = _res_cur_cfg_x_T_9; // @[PMP.scala:181:23, :184:26]
wire _res_T_224_cfg_l = res_hit_4 ? res_cur_4_cfg_l : _res_T_179_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_224_cfg_a = res_hit_4 ? res_cur_4_cfg_a : _res_T_179_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_224_cfg_x = res_hit_4 ? res_cur_4_cfg_x : _res_T_179_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_224_cfg_w = res_hit_4 ? res_cur_4_cfg_w : _res_T_179_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_224_cfg_r = res_hit_4 ? res_cur_4_cfg_r : _res_T_179_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_224_addr = res_hit_4 ? res_cur_4_addr : _res_T_179_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_224_mask = res_hit_4 ? res_cur_4_mask : _res_T_179_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_65 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_5 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_16 = _res_hit_lsbMask_T_15[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_17 = ~_res_hit_lsbMask_T_16; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_56 = io_pmp_2_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_15 = io_pmp_2_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_5 = {_res_hit_msbMatch_T_56, _res_aligned_pow2Aligned_T_15 | _res_hit_lsbMask_T_17}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_52 = ~_res_hit_msbMatch_T_51; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_53 = {_res_hit_msbMatch_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_54 = ~_res_hit_msbMatch_T_53; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_55 = _res_hit_msbMatch_T_54[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_57 = _res_hit_msbMatch_T_50 ^ _res_hit_msbMatch_T_55; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_58 = ~_res_hit_msbMatch_T_56; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_59 = _res_hit_msbMatch_T_57 & _res_hit_msbMatch_T_58; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_5 = _res_hit_msbMatch_T_59 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_52 = ~_res_hit_lsbMatch_T_51; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_53 = {_res_hit_lsbMatch_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_54 = ~_res_hit_lsbMatch_T_53; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_55 = _res_hit_lsbMatch_T_54[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_56 = res_hit_lsbMask_5[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_57 = _res_hit_lsbMatch_T_50 ^ _res_hit_lsbMatch_T_55; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_58 = ~_res_hit_lsbMatch_T_56; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_59 = _res_hit_lsbMatch_T_57 & _res_hit_lsbMatch_T_58; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_5 = _res_hit_lsbMatch_T_59 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_66 = res_hit_msbMatch_5 & res_hit_lsbMatch_5; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_67 = io_pmp_2_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_69 = _res_hit_T_68[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_70 = ~_res_hit_T_69; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_26 = {io_pmp_1_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_61; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_61 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_71; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_71 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_72; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_72 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_86; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_86 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_93; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_93 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_61; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_61 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_61; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_61 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_79; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_79 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_92; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_92 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_93; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_93 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_103; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_103 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_110; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_110 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_62 = ~_res_hit_msbsLess_T_61; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_63 = {_res_hit_msbsLess_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_64 = ~_res_hit_msbsLess_T_63; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_65 = _res_hit_msbsLess_T_64[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_10 = _res_hit_msbsLess_T_60 < _res_hit_msbsLess_T_65; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_72 = ~_res_hit_msbsEqual_T_71; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_73 = {_res_hit_msbsEqual_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_74 = ~_res_hit_msbsEqual_T_73; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_75 = _res_hit_msbsEqual_T_74[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_76 = _res_hit_msbsEqual_T_70 ^ _res_hit_msbsEqual_T_75; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_10 = _res_hit_msbsEqual_T_76 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_71 = _res_hit_lsbsLess_T_70 | _res_hit_T_70; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_73 = ~_res_hit_lsbsLess_T_72; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_74 = {_res_hit_lsbsLess_T_73[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_75 = ~_res_hit_lsbsLess_T_74; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_76 = _res_hit_lsbsLess_T_75[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_10 = _res_hit_lsbsLess_T_71 < _res_hit_lsbsLess_T_76; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_71 = res_hit_msbsEqual_10 & res_hit_lsbsLess_10; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_72 = res_hit_msbsLess_10 | _res_hit_T_71; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_73 = ~_res_hit_T_72; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_68 = ~_res_hit_msbsLess_T_67; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_69 = {_res_hit_msbsLess_T_68[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_70 = ~_res_hit_msbsLess_T_69; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_71 = _res_hit_msbsLess_T_70[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_11 = _res_hit_msbsLess_T_66 < _res_hit_msbsLess_T_71; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_79 = ~_res_hit_msbsEqual_T_78; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_80 = {_res_hit_msbsEqual_T_79[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_81 = ~_res_hit_msbsEqual_T_80; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_82 = _res_hit_msbsEqual_T_81[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_83 = _res_hit_msbsEqual_T_77 ^ _res_hit_msbsEqual_T_82; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_11 = _res_hit_msbsEqual_T_83 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_78 = _res_hit_lsbsLess_T_77; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_80 = ~_res_hit_lsbsLess_T_79; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_81 = {_res_hit_lsbsLess_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_82 = ~_res_hit_lsbsLess_T_81; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_83 = _res_hit_lsbsLess_T_82[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_11 = _res_hit_lsbsLess_T_78 < _res_hit_lsbsLess_T_83; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_74 = res_hit_msbsEqual_11 & res_hit_lsbsLess_11; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_75 = res_hit_msbsLess_11 | _res_hit_T_74; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_76 = _res_hit_T_73 & _res_hit_T_75; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_77 = _res_hit_T_67 & _res_hit_T_76; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_5 = _res_hit_T_65 ? _res_hit_T_66 : _res_hit_T_77; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_5 = ~io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_5 = default_0 & _res_ignore_T_5; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_11 = _res_aligned_lsbMask_T_10[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_5 = ~_res_aligned_lsbMask_T_11; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_87 = ~_res_aligned_straddlesLowerBound_T_86; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_88 = {_res_aligned_straddlesLowerBound_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_89 = ~_res_aligned_straddlesLowerBound_T_88; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_90 = _res_aligned_straddlesLowerBound_T_89[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_91 = _res_aligned_straddlesLowerBound_T_85 ^ _res_aligned_straddlesLowerBound_T_90; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_92 = _res_aligned_straddlesLowerBound_T_91 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_94 = ~_res_aligned_straddlesLowerBound_T_93; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_95 = {_res_aligned_straddlesLowerBound_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_96 = ~_res_aligned_straddlesLowerBound_T_95; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_97 = _res_aligned_straddlesLowerBound_T_96[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_99 = ~_res_aligned_straddlesLowerBound_T_98; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_100 = _res_aligned_straddlesLowerBound_T_97 & _res_aligned_straddlesLowerBound_T_99; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_101 = |_res_aligned_straddlesLowerBound_T_100; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound_5 = _res_aligned_straddlesLowerBound_T_92 & _res_aligned_straddlesLowerBound_T_101; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_87 = ~_res_aligned_straddlesUpperBound_T_86; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_88 = {_res_aligned_straddlesUpperBound_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_89 = ~_res_aligned_straddlesUpperBound_T_88; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_90 = _res_aligned_straddlesUpperBound_T_89[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_91 = _res_aligned_straddlesUpperBound_T_85 ^ _res_aligned_straddlesUpperBound_T_90; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_92 = _res_aligned_straddlesUpperBound_T_91 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_94 = ~_res_aligned_straddlesUpperBound_T_93; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_95 = {_res_aligned_straddlesUpperBound_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_96 = ~_res_aligned_straddlesUpperBound_T_95; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_97 = _res_aligned_straddlesUpperBound_T_96[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_99 = _res_aligned_straddlesUpperBound_T_98 | res_aligned_lsbMask_5; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_100 = _res_aligned_straddlesUpperBound_T_97 & _res_aligned_straddlesUpperBound_T_99; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_101 = |_res_aligned_straddlesUpperBound_T_100; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_5 = _res_aligned_straddlesUpperBound_T_92 & _res_aligned_straddlesUpperBound_T_101; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_5 = res_aligned_straddlesLowerBound_5 | res_aligned_straddlesUpperBound_5; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned_5 = ~_res_aligned_rangeAligned_T_5; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_16 = ~_res_aligned_pow2Aligned_T_15; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_17 = res_aligned_lsbMask_5 & _res_aligned_pow2Aligned_T_16; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_5 = _res_aligned_pow2Aligned_T_17 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_5 = _res_aligned_T_5 ? res_aligned_pow2Aligned_5 : res_aligned_rangeAligned_5; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_225 = io_pmp_2_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_27 = io_pmp_2_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_226; // @[PMP.scala:168:32]
assign _res_T_226 = _GEN_27; // @[PMP.scala:168:32]
wire _res_T_245; // @[PMP.scala:177:61]
assign _res_T_245 = _GEN_27; // @[PMP.scala:168:32, :177:61]
wire _res_T_249; // @[PMP.scala:178:63]
assign _res_T_249 = _GEN_27; // @[PMP.scala:168:32, :178:63]
wire _GEN_28 = io_pmp_2_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_227; // @[PMP.scala:168:32]
assign _res_T_227 = _GEN_28; // @[PMP.scala:168:32]
wire _res_T_254; // @[PMP.scala:177:61]
assign _res_T_254 = _GEN_28; // @[PMP.scala:168:32, :177:61]
wire _res_T_258; // @[PMP.scala:178:63]
assign _res_T_258 = _GEN_28; // @[PMP.scala:168:32, :178:63]
wire _res_T_228 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_29 = {io_pmp_2_cfg_x_0, io_pmp_2_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_30; // @[PMP.scala:174:26]
assign res_hi_30 = _GEN_29; // @[PMP.scala:174:26]
wire [1:0] res_hi_31; // @[PMP.scala:174:26]
assign res_hi_31 = _GEN_29; // @[PMP.scala:174:26]
wire [1:0] res_hi_32; // @[PMP.scala:174:26]
assign res_hi_32 = _GEN_29; // @[PMP.scala:174:26]
wire [1:0] res_hi_33; // @[PMP.scala:174:26]
assign res_hi_33 = _GEN_29; // @[PMP.scala:174:26]
wire [1:0] res_hi_34; // @[PMP.scala:174:26]
assign res_hi_34 = _GEN_29; // @[PMP.scala:174:26]
wire [1:0] res_hi_35; // @[PMP.scala:174:26]
assign res_hi_35 = _GEN_29; // @[PMP.scala:174:26]
wire [2:0] _res_T_230 = {res_hi_30, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_231 = _res_T_230 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_232 = {res_hi_31, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_233 = _res_T_232 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_234 = {res_hi_32, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_235 = _res_T_234 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_236 = {res_hi_33, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_237 = _res_T_236 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_238 = {res_hi_34, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_239 = _res_T_238 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_240 = {res_hi_35, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_241 = &_res_T_240; // @[PMP.scala:174:{26,60}]
wire _res_T_242 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22]
wire _res_T_243 = _res_T_242 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_244 = _res_T_243 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_246 = _res_T_244 & _res_T_245; // @[PMP.scala:177:{37,48,61}]
wire _GEN_30 = io_pmp_2_cfg_l_0 & res_hit_5; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_247; // @[PMP.scala:178:32]
assign _res_T_247 = _GEN_30; // @[PMP.scala:178:32]
wire _res_T_256; // @[PMP.scala:178:32]
assign _res_T_256 = _GEN_30; // @[PMP.scala:178:32]
wire _res_T_265; // @[PMP.scala:178:32]
assign _res_T_265 = _GEN_30; // @[PMP.scala:178:32]
wire _res_T_248 = _res_T_247 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_250 = _res_T_248 & _res_T_249; // @[PMP.scala:178:{39,50,63}]
wire _res_T_251 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22]
wire _res_T_252 = _res_T_251 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_253 = _res_T_252 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_255 = _res_T_253 & _res_T_254; // @[PMP.scala:177:{37,48,61}]
wire _res_T_257 = _res_T_256 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_259 = _res_T_257 & _res_T_258; // @[PMP.scala:178:{39,50,63}]
wire _res_T_260 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22]
wire _res_T_261 = _res_T_260 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_262 = _res_T_261 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_263 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_264 = _res_T_262 & _res_T_263; // @[PMP.scala:177:{37,48,61}]
wire _res_T_266 = _res_T_265 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_267 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_268 = _res_T_266 & _res_T_267; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_11; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_11; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_11; // @[PMP.scala:182:26]
wire res_cur_5_cfg_x; // @[PMP.scala:181:23]
wire res_cur_5_cfg_w; // @[PMP.scala:181:23]
wire res_cur_5_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_10 = io_pmp_2_cfg_r_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_11 = res_aligned_5 & _res_cur_cfg_r_T_10; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_5_cfg_r = _res_cur_cfg_r_T_11; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_10 = io_pmp_2_cfg_w_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_11 = res_aligned_5 & _res_cur_cfg_w_T_10; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_5_cfg_w = _res_cur_cfg_w_T_11; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_10 = io_pmp_2_cfg_x_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_11 = res_aligned_5 & _res_cur_cfg_x_T_10; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_5_cfg_x = _res_cur_cfg_x_T_11; // @[PMP.scala:181:23, :184:26]
wire _res_T_269_cfg_l = res_hit_5 ? res_cur_5_cfg_l : _res_T_224_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_269_cfg_a = res_hit_5 ? res_cur_5_cfg_a : _res_T_224_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_269_cfg_x = res_hit_5 ? res_cur_5_cfg_x : _res_T_224_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_269_cfg_w = res_hit_5 ? res_cur_5_cfg_w : _res_T_224_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_269_cfg_r = res_hit_5 ? res_cur_5_cfg_r : _res_T_224_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_269_addr = res_hit_5 ? res_cur_5_addr : _res_T_224_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_269_mask = res_hit_5 ? res_cur_5_mask : _res_T_224_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_78 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_6 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_19 = _res_hit_lsbMask_T_18[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_20 = ~_res_hit_lsbMask_T_19; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_66 = io_pmp_1_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_18 = io_pmp_1_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_6 = {_res_hit_msbMatch_T_66, _res_aligned_pow2Aligned_T_18 | _res_hit_lsbMask_T_20}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_62 = ~_res_hit_msbMatch_T_61; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_63 = {_res_hit_msbMatch_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_64 = ~_res_hit_msbMatch_T_63; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_65 = _res_hit_msbMatch_T_64[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_67 = _res_hit_msbMatch_T_60 ^ _res_hit_msbMatch_T_65; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_68 = ~_res_hit_msbMatch_T_66; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_69 = _res_hit_msbMatch_T_67 & _res_hit_msbMatch_T_68; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_6 = _res_hit_msbMatch_T_69 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_62 = ~_res_hit_lsbMatch_T_61; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_63 = {_res_hit_lsbMatch_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_64 = ~_res_hit_lsbMatch_T_63; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_65 = _res_hit_lsbMatch_T_64[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_66 = res_hit_lsbMask_6[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_67 = _res_hit_lsbMatch_T_60 ^ _res_hit_lsbMatch_T_65; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_68 = ~_res_hit_lsbMatch_T_66; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_69 = _res_hit_lsbMatch_T_67 & _res_hit_lsbMatch_T_68; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_6 = _res_hit_lsbMatch_T_69 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_79 = res_hit_msbMatch_6 & res_hit_lsbMatch_6; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_80 = io_pmp_1_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_82 = _res_hit_T_81[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_83 = ~_res_hit_T_82; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_31 = {io_pmp_0_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_73; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_73 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_85; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_85 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_86; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_86 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_103; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_103 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_110; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_110 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_71; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_71 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_71; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_71 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_91; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_91 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_106; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_106 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_107; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_107 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_120; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_120 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_127; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_127 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_74 = ~_res_hit_msbsLess_T_73; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_75 = {_res_hit_msbsLess_T_74[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_76 = ~_res_hit_msbsLess_T_75; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_77 = _res_hit_msbsLess_T_76[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_12 = _res_hit_msbsLess_T_72 < _res_hit_msbsLess_T_77; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_86 = ~_res_hit_msbsEqual_T_85; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_87 = {_res_hit_msbsEqual_T_86[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_88 = ~_res_hit_msbsEqual_T_87; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_89 = _res_hit_msbsEqual_T_88[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_90 = _res_hit_msbsEqual_T_84 ^ _res_hit_msbsEqual_T_89; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_12 = _res_hit_msbsEqual_T_90 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_85 = _res_hit_lsbsLess_T_84 | _res_hit_T_83; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_87 = ~_res_hit_lsbsLess_T_86; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_88 = {_res_hit_lsbsLess_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_89 = ~_res_hit_lsbsLess_T_88; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_90 = _res_hit_lsbsLess_T_89[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_12 = _res_hit_lsbsLess_T_85 < _res_hit_lsbsLess_T_90; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_84 = res_hit_msbsEqual_12 & res_hit_lsbsLess_12; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_85 = res_hit_msbsLess_12 | _res_hit_T_84; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_86 = ~_res_hit_T_85; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_80 = ~_res_hit_msbsLess_T_79; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_81 = {_res_hit_msbsLess_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_82 = ~_res_hit_msbsLess_T_81; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_83 = _res_hit_msbsLess_T_82[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_13 = _res_hit_msbsLess_T_78 < _res_hit_msbsLess_T_83; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_93 = ~_res_hit_msbsEqual_T_92; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_94 = {_res_hit_msbsEqual_T_93[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_95 = ~_res_hit_msbsEqual_T_94; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_96 = _res_hit_msbsEqual_T_95[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_97 = _res_hit_msbsEqual_T_91 ^ _res_hit_msbsEqual_T_96; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_13 = _res_hit_msbsEqual_T_97 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_92 = _res_hit_lsbsLess_T_91; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_94 = ~_res_hit_lsbsLess_T_93; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_95 = {_res_hit_lsbsLess_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_96 = ~_res_hit_lsbsLess_T_95; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_97 = _res_hit_lsbsLess_T_96[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_13 = _res_hit_lsbsLess_T_92 < _res_hit_lsbsLess_T_97; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_87 = res_hit_msbsEqual_13 & res_hit_lsbsLess_13; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_88 = res_hit_msbsLess_13 | _res_hit_T_87; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_89 = _res_hit_T_86 & _res_hit_T_88; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_90 = _res_hit_T_80 & _res_hit_T_89; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_6 = _res_hit_T_78 ? _res_hit_T_79 : _res_hit_T_90; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_6 = ~io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_6 = default_0 & _res_ignore_T_6; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_13 = _res_aligned_lsbMask_T_12[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_6 = ~_res_aligned_lsbMask_T_13; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_104 = ~_res_aligned_straddlesLowerBound_T_103; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_105 = {_res_aligned_straddlesLowerBound_T_104[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_106 = ~_res_aligned_straddlesLowerBound_T_105; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_107 = _res_aligned_straddlesLowerBound_T_106[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_108 = _res_aligned_straddlesLowerBound_T_102 ^ _res_aligned_straddlesLowerBound_T_107; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_109 = _res_aligned_straddlesLowerBound_T_108 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_111 = ~_res_aligned_straddlesLowerBound_T_110; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_112 = {_res_aligned_straddlesLowerBound_T_111[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_113 = ~_res_aligned_straddlesLowerBound_T_112; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_114 = _res_aligned_straddlesLowerBound_T_113[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_116 = ~_res_aligned_straddlesLowerBound_T_115; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_117 = _res_aligned_straddlesLowerBound_T_114 & _res_aligned_straddlesLowerBound_T_116; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_118 = |_res_aligned_straddlesLowerBound_T_117; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound_6 = _res_aligned_straddlesLowerBound_T_109 & _res_aligned_straddlesLowerBound_T_118; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_104 = ~_res_aligned_straddlesUpperBound_T_103; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_105 = {_res_aligned_straddlesUpperBound_T_104[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_106 = ~_res_aligned_straddlesUpperBound_T_105; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_107 = _res_aligned_straddlesUpperBound_T_106[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_108 = _res_aligned_straddlesUpperBound_T_102 ^ _res_aligned_straddlesUpperBound_T_107; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_109 = _res_aligned_straddlesUpperBound_T_108 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_111 = ~_res_aligned_straddlesUpperBound_T_110; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_112 = {_res_aligned_straddlesUpperBound_T_111[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_113 = ~_res_aligned_straddlesUpperBound_T_112; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_114 = _res_aligned_straddlesUpperBound_T_113[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_116 = _res_aligned_straddlesUpperBound_T_115 | res_aligned_lsbMask_6; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_117 = _res_aligned_straddlesUpperBound_T_114 & _res_aligned_straddlesUpperBound_T_116; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_118 = |_res_aligned_straddlesUpperBound_T_117; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_6 = _res_aligned_straddlesUpperBound_T_109 & _res_aligned_straddlesUpperBound_T_118; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_6 = res_aligned_straddlesLowerBound_6 | res_aligned_straddlesUpperBound_6; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned_6 = ~_res_aligned_rangeAligned_T_6; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_19 = ~_res_aligned_pow2Aligned_T_18; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_20 = res_aligned_lsbMask_6 & _res_aligned_pow2Aligned_T_19; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_6 = _res_aligned_pow2Aligned_T_20 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_6 = _res_aligned_T_6 ? res_aligned_pow2Aligned_6 : res_aligned_rangeAligned_6; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_270 = io_pmp_1_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_32 = io_pmp_1_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_271; // @[PMP.scala:168:32]
assign _res_T_271 = _GEN_32; // @[PMP.scala:168:32]
wire _res_T_290; // @[PMP.scala:177:61]
assign _res_T_290 = _GEN_32; // @[PMP.scala:168:32, :177:61]
wire _res_T_294; // @[PMP.scala:178:63]
assign _res_T_294 = _GEN_32; // @[PMP.scala:168:32, :178:63]
wire _GEN_33 = io_pmp_1_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_272; // @[PMP.scala:168:32]
assign _res_T_272 = _GEN_33; // @[PMP.scala:168:32]
wire _res_T_299; // @[PMP.scala:177:61]
assign _res_T_299 = _GEN_33; // @[PMP.scala:168:32, :177:61]
wire _res_T_303; // @[PMP.scala:178:63]
assign _res_T_303 = _GEN_33; // @[PMP.scala:168:32, :178:63]
wire _res_T_273 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_34 = {io_pmp_1_cfg_x_0, io_pmp_1_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_36; // @[PMP.scala:174:26]
assign res_hi_36 = _GEN_34; // @[PMP.scala:174:26]
wire [1:0] res_hi_37; // @[PMP.scala:174:26]
assign res_hi_37 = _GEN_34; // @[PMP.scala:174:26]
wire [1:0] res_hi_38; // @[PMP.scala:174:26]
assign res_hi_38 = _GEN_34; // @[PMP.scala:174:26]
wire [1:0] res_hi_39; // @[PMP.scala:174:26]
assign res_hi_39 = _GEN_34; // @[PMP.scala:174:26]
wire [1:0] res_hi_40; // @[PMP.scala:174:26]
assign res_hi_40 = _GEN_34; // @[PMP.scala:174:26]
wire [1:0] res_hi_41; // @[PMP.scala:174:26]
assign res_hi_41 = _GEN_34; // @[PMP.scala:174:26]
wire [2:0] _res_T_275 = {res_hi_36, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_276 = _res_T_275 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_277 = {res_hi_37, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_278 = _res_T_277 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_279 = {res_hi_38, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_280 = _res_T_279 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_281 = {res_hi_39, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_282 = _res_T_281 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_283 = {res_hi_40, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_284 = _res_T_283 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_285 = {res_hi_41, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_286 = &_res_T_285; // @[PMP.scala:174:{26,60}]
wire _res_T_287 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22]
wire _res_T_288 = _res_T_287 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_289 = _res_T_288 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_291 = _res_T_289 & _res_T_290; // @[PMP.scala:177:{37,48,61}]
wire _GEN_35 = io_pmp_1_cfg_l_0 & res_hit_6; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_292; // @[PMP.scala:178:32]
assign _res_T_292 = _GEN_35; // @[PMP.scala:178:32]
wire _res_T_301; // @[PMP.scala:178:32]
assign _res_T_301 = _GEN_35; // @[PMP.scala:178:32]
wire _res_T_310; // @[PMP.scala:178:32]
assign _res_T_310 = _GEN_35; // @[PMP.scala:178:32]
wire _res_T_293 = _res_T_292 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_295 = _res_T_293 & _res_T_294; // @[PMP.scala:178:{39,50,63}]
wire _res_T_296 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22]
wire _res_T_297 = _res_T_296 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_298 = _res_T_297 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_300 = _res_T_298 & _res_T_299; // @[PMP.scala:177:{37,48,61}]
wire _res_T_302 = _res_T_301 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_304 = _res_T_302 & _res_T_303; // @[PMP.scala:178:{39,50,63}]
wire _res_T_305 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22]
wire _res_T_306 = _res_T_305 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_307 = _res_T_306 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_308 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_309 = _res_T_307 & _res_T_308; // @[PMP.scala:177:{37,48,61}]
wire _res_T_311 = _res_T_310 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_312 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_313 = _res_T_311 & _res_T_312; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_13; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_13; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_13; // @[PMP.scala:182:26]
wire res_cur_6_cfg_x; // @[PMP.scala:181:23]
wire res_cur_6_cfg_w; // @[PMP.scala:181:23]
wire res_cur_6_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_12 = io_pmp_1_cfg_r_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_13 = res_aligned_6 & _res_cur_cfg_r_T_12; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_6_cfg_r = _res_cur_cfg_r_T_13; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_12 = io_pmp_1_cfg_w_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_13 = res_aligned_6 & _res_cur_cfg_w_T_12; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_6_cfg_w = _res_cur_cfg_w_T_13; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_12 = io_pmp_1_cfg_x_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_13 = res_aligned_6 & _res_cur_cfg_x_T_12; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_6_cfg_x = _res_cur_cfg_x_T_13; // @[PMP.scala:181:23, :184:26]
wire _res_T_314_cfg_l = res_hit_6 ? res_cur_6_cfg_l : _res_T_269_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_314_cfg_a = res_hit_6 ? res_cur_6_cfg_a : _res_T_269_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_314_cfg_x = res_hit_6 ? res_cur_6_cfg_x : _res_T_269_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_314_cfg_w = res_hit_6 ? res_cur_6_cfg_w : _res_T_269_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_314_cfg_r = res_hit_6 ? res_cur_6_cfg_r : _res_T_269_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_314_addr = res_hit_6 ? res_cur_6_addr : _res_T_269_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_314_mask = res_hit_6 ? res_cur_6_mask : _res_T_269_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_91 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_7 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_22 = _res_hit_lsbMask_T_21[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_23 = ~_res_hit_lsbMask_T_22; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_76 = io_pmp_0_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_21 = io_pmp_0_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_7 = {_res_hit_msbMatch_T_76, _res_aligned_pow2Aligned_T_21 | _res_hit_lsbMask_T_23}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_72 = ~_res_hit_msbMatch_T_71; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_73 = {_res_hit_msbMatch_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_74 = ~_res_hit_msbMatch_T_73; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_75 = _res_hit_msbMatch_T_74[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_77 = _res_hit_msbMatch_T_70 ^ _res_hit_msbMatch_T_75; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_78 = ~_res_hit_msbMatch_T_76; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_79 = _res_hit_msbMatch_T_77 & _res_hit_msbMatch_T_78; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_7 = _res_hit_msbMatch_T_79 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_72 = ~_res_hit_lsbMatch_T_71; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_73 = {_res_hit_lsbMatch_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_74 = ~_res_hit_lsbMatch_T_73; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_75 = _res_hit_lsbMatch_T_74[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_76 = res_hit_lsbMask_7[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_77 = _res_hit_lsbMatch_T_70 ^ _res_hit_lsbMatch_T_75; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_78 = ~_res_hit_lsbMatch_T_76; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_79 = _res_hit_lsbMatch_T_77 & _res_hit_lsbMatch_T_78; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_7 = _res_hit_lsbMatch_T_79 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_92 = res_hit_msbMatch_7 & res_hit_lsbMatch_7; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_93 = io_pmp_0_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_95 = _res_hit_T_94[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_96 = ~_res_hit_T_95; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbsEqual_T_104 = _res_hit_msbsEqual_T_98; // @[PMP.scala:81:{27,41}]
wire res_hit_msbsEqual_14 = _res_hit_msbsEqual_T_104 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_99 = _res_hit_lsbsLess_T_98 | _res_hit_T_96; // @[package.scala:243:46]
wire [31:0] _res_hit_msbsLess_T_92 = ~_res_hit_msbsLess_T_91; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_93 = {_res_hit_msbsLess_T_92[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_94 = ~_res_hit_msbsLess_T_93; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_95 = _res_hit_msbsLess_T_94[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_15 = _res_hit_msbsLess_T_90 < _res_hit_msbsLess_T_95; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_107 = ~_res_hit_msbsEqual_T_106; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_108 = {_res_hit_msbsEqual_T_107[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_109 = ~_res_hit_msbsEqual_T_108; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_110 = _res_hit_msbsEqual_T_109[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_111 = _res_hit_msbsEqual_T_105 ^ _res_hit_msbsEqual_T_110; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_15 = _res_hit_msbsEqual_T_111 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_106 = _res_hit_lsbsLess_T_105; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_108 = ~_res_hit_lsbsLess_T_107; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_109 = {_res_hit_lsbsLess_T_108[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_110 = ~_res_hit_lsbsLess_T_109; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_111 = _res_hit_lsbsLess_T_110[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_15 = _res_hit_lsbsLess_T_106 < _res_hit_lsbsLess_T_111; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_100 = res_hit_msbsEqual_15 & res_hit_lsbsLess_15; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_101 = res_hit_msbsLess_15 | _res_hit_T_100; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_102 = _res_hit_T_101; // @[PMP.scala:83:16, :94:48]
wire _res_hit_T_103 = _res_hit_T_93 & _res_hit_T_102; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_7 = _res_hit_T_91 ? _res_hit_T_92 : _res_hit_T_103; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_7 = ~io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_7 = default_0 & _res_ignore_T_7; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_15 = _res_aligned_lsbMask_T_14[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_7 = ~_res_aligned_lsbMask_T_15; // @[package.scala:243:{46,76}]
wire [28:0] _res_aligned_straddlesLowerBound_T_125 = _res_aligned_straddlesLowerBound_T_119; // @[PMP.scala:123:{35,49}]
wire _res_aligned_straddlesLowerBound_T_126 = _res_aligned_straddlesLowerBound_T_125 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [2:0] _res_aligned_straddlesLowerBound_T_133 = ~_res_aligned_straddlesLowerBound_T_132; // @[PMP.scala:123:{127,129}]
wire [31:0] _res_aligned_straddlesUpperBound_T_121 = ~_res_aligned_straddlesUpperBound_T_120; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_122 = {_res_aligned_straddlesUpperBound_T_121[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_123 = ~_res_aligned_straddlesUpperBound_T_122; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_124 = _res_aligned_straddlesUpperBound_T_123[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_125 = _res_aligned_straddlesUpperBound_T_119 ^ _res_aligned_straddlesUpperBound_T_124; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_126 = _res_aligned_straddlesUpperBound_T_125 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_128 = ~_res_aligned_straddlesUpperBound_T_127; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_129 = {_res_aligned_straddlesUpperBound_T_128[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_130 = ~_res_aligned_straddlesUpperBound_T_129; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_131 = _res_aligned_straddlesUpperBound_T_130[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_133 = _res_aligned_straddlesUpperBound_T_132 | res_aligned_lsbMask_7; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_134 = _res_aligned_straddlesUpperBound_T_131 & _res_aligned_straddlesUpperBound_T_133; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_135 = |_res_aligned_straddlesUpperBound_T_134; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_7 = _res_aligned_straddlesUpperBound_T_126 & _res_aligned_straddlesUpperBound_T_135; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_7 = res_aligned_straddlesUpperBound_7; // @[PMP.scala:124:85, :125:46]
wire res_aligned_rangeAligned_7 = ~_res_aligned_rangeAligned_T_7; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_22 = ~_res_aligned_pow2Aligned_T_21; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_23 = res_aligned_lsbMask_7 & _res_aligned_pow2Aligned_T_22; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_7 = _res_aligned_pow2Aligned_T_23 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_7 = _res_aligned_T_7 ? res_aligned_pow2Aligned_7 : res_aligned_rangeAligned_7; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_315 = io_pmp_0_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_36 = io_pmp_0_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_316; // @[PMP.scala:168:32]
assign _res_T_316 = _GEN_36; // @[PMP.scala:168:32]
wire _res_T_335; // @[PMP.scala:177:61]
assign _res_T_335 = _GEN_36; // @[PMP.scala:168:32, :177:61]
wire _res_T_339; // @[PMP.scala:178:63]
assign _res_T_339 = _GEN_36; // @[PMP.scala:168:32, :178:63]
wire _GEN_37 = io_pmp_0_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_317; // @[PMP.scala:168:32]
assign _res_T_317 = _GEN_37; // @[PMP.scala:168:32]
wire _res_T_344; // @[PMP.scala:177:61]
assign _res_T_344 = _GEN_37; // @[PMP.scala:168:32, :177:61]
wire _res_T_348; // @[PMP.scala:178:63]
assign _res_T_348 = _GEN_37; // @[PMP.scala:168:32, :178:63]
wire _res_T_318 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_38 = {io_pmp_0_cfg_x_0, io_pmp_0_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_42; // @[PMP.scala:174:26]
assign res_hi_42 = _GEN_38; // @[PMP.scala:174:26]
wire [1:0] res_hi_43; // @[PMP.scala:174:26]
assign res_hi_43 = _GEN_38; // @[PMP.scala:174:26]
wire [1:0] res_hi_44; // @[PMP.scala:174:26]
assign res_hi_44 = _GEN_38; // @[PMP.scala:174:26]
wire [1:0] res_hi_45; // @[PMP.scala:174:26]
assign res_hi_45 = _GEN_38; // @[PMP.scala:174:26]
wire [1:0] res_hi_46; // @[PMP.scala:174:26]
assign res_hi_46 = _GEN_38; // @[PMP.scala:174:26]
wire [1:0] res_hi_47; // @[PMP.scala:174:26]
assign res_hi_47 = _GEN_38; // @[PMP.scala:174:26]
wire [2:0] _res_T_320 = {res_hi_42, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_321 = _res_T_320 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_322 = {res_hi_43, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_323 = _res_T_322 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_324 = {res_hi_44, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_325 = _res_T_324 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_326 = {res_hi_45, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_327 = _res_T_326 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_328 = {res_hi_46, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_329 = _res_T_328 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_330 = {res_hi_47, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_331 = &_res_T_330; // @[PMP.scala:174:{26,60}]
wire _res_T_332 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22]
wire _res_T_333 = _res_T_332 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_334 = _res_T_333 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_336 = _res_T_334 & _res_T_335; // @[PMP.scala:177:{37,48,61}]
wire _GEN_39 = io_pmp_0_cfg_l_0 & res_hit_7; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_337; // @[PMP.scala:178:32]
assign _res_T_337 = _GEN_39; // @[PMP.scala:178:32]
wire _res_T_346; // @[PMP.scala:178:32]
assign _res_T_346 = _GEN_39; // @[PMP.scala:178:32]
wire _res_T_355; // @[PMP.scala:178:32]
assign _res_T_355 = _GEN_39; // @[PMP.scala:178:32]
wire _res_T_338 = _res_T_337 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_340 = _res_T_338 & _res_T_339; // @[PMP.scala:178:{39,50,63}]
wire _res_T_341 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22]
wire _res_T_342 = _res_T_341 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_343 = _res_T_342 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_345 = _res_T_343 & _res_T_344; // @[PMP.scala:177:{37,48,61}]
wire _res_T_347 = _res_T_346 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_349 = _res_T_347 & _res_T_348; // @[PMP.scala:178:{39,50,63}]
wire _res_T_350 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22]
wire _res_T_351 = _res_T_350 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_352 = _res_T_351 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_353 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_354 = _res_T_352 & _res_T_353; // @[PMP.scala:177:{37,48,61}]
wire _res_T_356 = _res_T_355 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_357 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_358 = _res_T_356 & _res_T_357; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_15; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_15; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_15; // @[PMP.scala:182:26]
wire res_cur_7_cfg_x; // @[PMP.scala:181:23]
wire res_cur_7_cfg_w; // @[PMP.scala:181:23]
wire res_cur_7_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_14 = io_pmp_0_cfg_r_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_15 = res_aligned_7 & _res_cur_cfg_r_T_14; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_7_cfg_r = _res_cur_cfg_r_T_15; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_14 = io_pmp_0_cfg_w_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_15 = res_aligned_7 & _res_cur_cfg_w_T_14; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_7_cfg_w = _res_cur_cfg_w_T_15; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_14 = io_pmp_0_cfg_x_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_15 = res_aligned_7 & _res_cur_cfg_x_T_14; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_7_cfg_x = _res_cur_cfg_x_T_15; // @[PMP.scala:181:23, :184:26]
wire res_cfg_l = res_hit_7 ? res_cur_7_cfg_l : _res_T_314_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] res_cfg_a = res_hit_7 ? res_cur_7_cfg_a : _res_T_314_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
assign res_cfg_x = res_hit_7 ? res_cur_7_cfg_x : _res_T_314_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
assign res_cfg_w = res_hit_7 ? res_cur_7_cfg_w : _res_T_314_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
assign res_cfg_r = res_hit_7 ? res_cur_7_cfg_r : _res_T_314_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] res_addr = res_hit_7 ? res_cur_7_addr : _res_T_314_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] res_mask = res_hit_7 ? res_cur_7_mask : _res_T_314_mask; // @[PMP.scala:132:8, :181:23, :185:8]
assign io_x_0 = res_cfg_x; // @[PMP.scala:143:7, :185:8]
assign io_w_0 = res_cfg_w; // @[PMP.scala:143:7, :185:8]
assign io_r_0 = res_cfg_r; // @[PMP.scala:143:7, :185:8]
assign io_r = io_r_0; // @[PMP.scala:143:7]
assign io_w = io_w_0; // @[PMP.scala:143:7]
assign io_x = io_x_0; // @[PMP.scala:143:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_238 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>}
node _io_out_d_T = mul(io.in_a, io.in_b)
node _io_out_d_T_1 = add(_io_out_d_T, io.in_c)
node _io_out_d_T_2 = tail(_io_out_d_T_1, 1)
node _io_out_d_T_3 = asSInt(_io_out_d_T_2)
connect io.out_d, _io_out_d_T_3 | module MacUnit_238( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [19:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54]
assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_23 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T = shr(io.in.a.bits.source, 2)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_6 = shr(io.in.a.bits.source, 2)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h1))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_12 = shr(io.in.a.bits.source, 2)
node _source_ok_T_13 = eq(_source_ok_T_12, UInt<2>(0h2))
node _source_ok_T_14 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14)
node _source_ok_T_16 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_18 = shr(io.in.a.bits.source, 2)
node _source_ok_T_19 = eq(_source_ok_T_18, UInt<2>(0h3))
node _source_ok_T_20 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20)
node _source_ok_T_22 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_23 = and(_source_ok_T_21, _source_ok_T_22)
wire _source_ok_WIRE : UInt<1>[4]
connect _source_ok_WIRE[0], _source_ok_T_5
connect _source_ok_WIRE[1], _source_ok_T_11
connect _source_ok_WIRE[2], _source_ok_T_17
connect _source_ok_WIRE[3], _source_ok_T_23
node _source_ok_T_24 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_25 = or(_source_ok_T_24, _source_ok_WIRE[2])
node source_ok = or(_source_ok_T_25, _source_ok_WIRE[3])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_4 = shr(io.in.a.bits.source, 2)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<2>(0h3))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_17 = shr(io.in.a.bits.source, 2)
node _T_18 = eq(_T_17, UInt<1>(0h1))
node _T_19 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_20 = and(_T_18, _T_19)
node _T_21 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_25 = cvt(_T_24)
node _T_26 = and(_T_25, asSInt(UInt<1>(0h0)))
node _T_27 = asSInt(_T_26)
node _T_28 = eq(_T_27, asSInt(UInt<1>(0h0)))
node _T_29 = or(_T_23, _T_28)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_30 = shr(io.in.a.bits.source, 2)
node _T_31 = eq(_T_30, UInt<2>(0h2))
node _T_32 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_33 = and(_T_31, _T_32)
node _T_34 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_35 = and(_T_33, _T_34)
node _T_36 = eq(_T_35, UInt<1>(0h0))
node _T_37 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_38 = cvt(_T_37)
node _T_39 = and(_T_38, asSInt(UInt<1>(0h0)))
node _T_40 = asSInt(_T_39)
node _T_41 = eq(_T_40, asSInt(UInt<1>(0h0)))
node _T_42 = or(_T_36, _T_41)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_43 = shr(io.in.a.bits.source, 2)
node _T_44 = eq(_T_43, UInt<2>(0h3))
node _T_45 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_46 = and(_T_44, _T_45)
node _T_47 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_48 = and(_T_46, _T_47)
node _T_49 = eq(_T_48, UInt<1>(0h0))
node _T_50 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_51 = cvt(_T_50)
node _T_52 = and(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = asSInt(_T_52)
node _T_54 = eq(_T_53, asSInt(UInt<1>(0h0)))
node _T_55 = or(_T_49, _T_54)
node _T_56 = and(_T_16, _T_29)
node _T_57 = and(_T_56, _T_42)
node _T_58 = and(_T_57, _T_55)
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_T_58, UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_58, UInt<1>(0h1), "") : assert_1
node _T_62 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_62 :
node _T_63 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_64 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_65 = and(_T_63, _T_64)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_66 = shr(io.in.a.bits.source, 2)
node _T_67 = eq(_T_66, UInt<1>(0h0))
node _T_68 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_69 = and(_T_67, _T_68)
node _T_70 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_71 = and(_T_69, _T_70)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_72 = shr(io.in.a.bits.source, 2)
node _T_73 = eq(_T_72, UInt<1>(0h1))
node _T_74 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_75 = and(_T_73, _T_74)
node _T_76 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_77 = and(_T_75, _T_76)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_78 = shr(io.in.a.bits.source, 2)
node _T_79 = eq(_T_78, UInt<2>(0h2))
node _T_80 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_81 = and(_T_79, _T_80)
node _T_82 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_83 = and(_T_81, _T_82)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_84 = shr(io.in.a.bits.source, 2)
node _T_85 = eq(_T_84, UInt<2>(0h3))
node _T_86 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_87 = and(_T_85, _T_86)
node _T_88 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_89 = and(_T_87, _T_88)
node _T_90 = or(_T_71, _T_77)
node _T_91 = or(_T_90, _T_83)
node _T_92 = or(_T_91, _T_89)
node _T_93 = and(_T_65, _T_92)
node _T_94 = or(UInt<1>(0h0), _T_93)
node _T_95 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_96 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_97 = cvt(_T_96)
node _T_98 = and(_T_97, asSInt(UInt<14>(0h2000)))
node _T_99 = asSInt(_T_98)
node _T_100 = eq(_T_99, asSInt(UInt<1>(0h0)))
node _T_101 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_102 = cvt(_T_101)
node _T_103 = and(_T_102, asSInt(UInt<13>(0h1000)))
node _T_104 = asSInt(_T_103)
node _T_105 = eq(_T_104, asSInt(UInt<1>(0h0)))
node _T_106 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_107 = cvt(_T_106)
node _T_108 = and(_T_107, asSInt(UInt<17>(0h10000)))
node _T_109 = asSInt(_T_108)
node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = xor(io.in.a.bits.address, UInt<18>(0h20000))
node _T_112 = cvt(_T_111)
node _T_113 = and(_T_112, asSInt(UInt<15>(0h4000)))
node _T_114 = asSInt(_T_113)
node _T_115 = eq(_T_114, asSInt(UInt<1>(0h0)))
node _T_116 = xor(io.in.a.bits.address, UInt<18>(0h24000))
node _T_117 = cvt(_T_116)
node _T_118 = and(_T_117, asSInt(UInt<13>(0h1000)))
node _T_119 = asSInt(_T_118)
node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0)))
node _T_121 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_122 = cvt(_T_121)
node _T_123 = and(_T_122, asSInt(UInt<18>(0h2f000)))
node _T_124 = asSInt(_T_123)
node _T_125 = eq(_T_124, asSInt(UInt<1>(0h0)))
node _T_126 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_127 = cvt(_T_126)
node _T_128 = and(_T_127, asSInt(UInt<17>(0h10000)))
node _T_129 = asSInt(_T_128)
node _T_130 = eq(_T_129, asSInt(UInt<1>(0h0)))
node _T_131 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_132 = cvt(_T_131)
node _T_133 = and(_T_132, asSInt(UInt<13>(0h1000)))
node _T_134 = asSInt(_T_133)
node _T_135 = eq(_T_134, asSInt(UInt<1>(0h0)))
node _T_136 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_137 = cvt(_T_136)
node _T_138 = and(_T_137, asSInt(UInt<27>(0h4000000)))
node _T_139 = asSInt(_T_138)
node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0)))
node _T_141 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_142 = cvt(_T_141)
node _T_143 = and(_T_142, asSInt(UInt<13>(0h1000)))
node _T_144 = asSInt(_T_143)
node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0)))
node _T_146 = or(_T_100, _T_105)
node _T_147 = or(_T_146, _T_110)
node _T_148 = or(_T_147, _T_115)
node _T_149 = or(_T_148, _T_120)
node _T_150 = or(_T_149, _T_125)
node _T_151 = or(_T_150, _T_130)
node _T_152 = or(_T_151, _T_135)
node _T_153 = or(_T_152, _T_140)
node _T_154 = or(_T_153, _T_145)
node _T_155 = and(_T_95, _T_154)
node _T_156 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_157 = or(UInt<1>(0h0), _T_156)
node _T_158 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_159 = cvt(_T_158)
node _T_160 = and(_T_159, asSInt(UInt<17>(0h10000)))
node _T_161 = asSInt(_T_160)
node _T_162 = eq(_T_161, asSInt(UInt<1>(0h0)))
node _T_163 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_164 = cvt(_T_163)
node _T_165 = and(_T_164, asSInt(UInt<29>(0h10000000)))
node _T_166 = asSInt(_T_165)
node _T_167 = eq(_T_166, asSInt(UInt<1>(0h0)))
node _T_168 = or(_T_162, _T_167)
node _T_169 = and(_T_157, _T_168)
node _T_170 = or(UInt<1>(0h0), _T_155)
node _T_171 = or(_T_170, _T_169)
node _T_172 = and(_T_94, _T_171)
node _T_173 = asUInt(reset)
node _T_174 = eq(_T_173, UInt<1>(0h0))
when _T_174 :
node _T_175 = eq(_T_172, UInt<1>(0h0))
when _T_175 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_172, UInt<1>(0h1), "") : assert_2
node _T_176 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_177 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_178 = and(_T_176, _T_177)
node _T_179 = or(UInt<1>(0h0), _T_178)
node _T_180 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_181 = cvt(_T_180)
node _T_182 = and(_T_181, asSInt(UInt<14>(0h2000)))
node _T_183 = asSInt(_T_182)
node _T_184 = eq(_T_183, asSInt(UInt<1>(0h0)))
node _T_185 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_186 = cvt(_T_185)
node _T_187 = and(_T_186, asSInt(UInt<13>(0h1000)))
node _T_188 = asSInt(_T_187)
node _T_189 = eq(_T_188, asSInt(UInt<1>(0h0)))
node _T_190 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_191 = cvt(_T_190)
node _T_192 = and(_T_191, asSInt(UInt<17>(0h10000)))
node _T_193 = asSInt(_T_192)
node _T_194 = eq(_T_193, asSInt(UInt<1>(0h0)))
node _T_195 = xor(io.in.a.bits.address, UInt<18>(0h20000))
node _T_196 = cvt(_T_195)
node _T_197 = and(_T_196, asSInt(UInt<15>(0h4000)))
node _T_198 = asSInt(_T_197)
node _T_199 = eq(_T_198, asSInt(UInt<1>(0h0)))
node _T_200 = xor(io.in.a.bits.address, UInt<18>(0h24000))
node _T_201 = cvt(_T_200)
node _T_202 = and(_T_201, asSInt(UInt<13>(0h1000)))
node _T_203 = asSInt(_T_202)
node _T_204 = eq(_T_203, asSInt(UInt<1>(0h0)))
node _T_205 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_206 = cvt(_T_205)
node _T_207 = and(_T_206, asSInt(UInt<18>(0h2f000)))
node _T_208 = asSInt(_T_207)
node _T_209 = eq(_T_208, asSInt(UInt<1>(0h0)))
node _T_210 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_211 = cvt(_T_210)
node _T_212 = and(_T_211, asSInt(UInt<17>(0h10000)))
node _T_213 = asSInt(_T_212)
node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0)))
node _T_215 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_216 = cvt(_T_215)
node _T_217 = and(_T_216, asSInt(UInt<13>(0h1000)))
node _T_218 = asSInt(_T_217)
node _T_219 = eq(_T_218, asSInt(UInt<1>(0h0)))
node _T_220 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_221 = cvt(_T_220)
node _T_222 = and(_T_221, asSInt(UInt<17>(0h10000)))
node _T_223 = asSInt(_T_222)
node _T_224 = eq(_T_223, asSInt(UInt<1>(0h0)))
node _T_225 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_226 = cvt(_T_225)
node _T_227 = and(_T_226, asSInt(UInt<27>(0h4000000)))
node _T_228 = asSInt(_T_227)
node _T_229 = eq(_T_228, asSInt(UInt<1>(0h0)))
node _T_230 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_231 = cvt(_T_230)
node _T_232 = and(_T_231, asSInt(UInt<13>(0h1000)))
node _T_233 = asSInt(_T_232)
node _T_234 = eq(_T_233, asSInt(UInt<1>(0h0)))
node _T_235 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_236 = cvt(_T_235)
node _T_237 = and(_T_236, asSInt(UInt<29>(0h10000000)))
node _T_238 = asSInt(_T_237)
node _T_239 = eq(_T_238, asSInt(UInt<1>(0h0)))
node _T_240 = or(_T_184, _T_189)
node _T_241 = or(_T_240, _T_194)
node _T_242 = or(_T_241, _T_199)
node _T_243 = or(_T_242, _T_204)
node _T_244 = or(_T_243, _T_209)
node _T_245 = or(_T_244, _T_214)
node _T_246 = or(_T_245, _T_219)
node _T_247 = or(_T_246, _T_224)
node _T_248 = or(_T_247, _T_229)
node _T_249 = or(_T_248, _T_234)
node _T_250 = or(_T_249, _T_239)
node _T_251 = and(_T_179, _T_250)
node _T_252 = or(UInt<1>(0h0), _T_251)
node _T_253 = and(UInt<1>(0h0), _T_252)
node _T_254 = asUInt(reset)
node _T_255 = eq(_T_254, UInt<1>(0h0))
when _T_255 :
node _T_256 = eq(_T_253, UInt<1>(0h0))
when _T_256 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_253, UInt<1>(0h1), "") : assert_3
node _T_257 = asUInt(reset)
node _T_258 = eq(_T_257, UInt<1>(0h0))
when _T_258 :
node _T_259 = eq(source_ok, UInt<1>(0h0))
when _T_259 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_260 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_261 = asUInt(reset)
node _T_262 = eq(_T_261, UInt<1>(0h0))
when _T_262 :
node _T_263 = eq(_T_260, UInt<1>(0h0))
when _T_263 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_260, UInt<1>(0h1), "") : assert_5
node _T_264 = asUInt(reset)
node _T_265 = eq(_T_264, UInt<1>(0h0))
when _T_265 :
node _T_266 = eq(is_aligned, UInt<1>(0h0))
when _T_266 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_267 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_268 = asUInt(reset)
node _T_269 = eq(_T_268, UInt<1>(0h0))
when _T_269 :
node _T_270 = eq(_T_267, UInt<1>(0h0))
when _T_270 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_267, UInt<1>(0h1), "") : assert_7
node _T_271 = not(io.in.a.bits.mask)
node _T_272 = eq(_T_271, UInt<1>(0h0))
node _T_273 = asUInt(reset)
node _T_274 = eq(_T_273, UInt<1>(0h0))
when _T_274 :
node _T_275 = eq(_T_272, UInt<1>(0h0))
when _T_275 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_272, UInt<1>(0h1), "") : assert_8
node _T_276 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_277 = asUInt(reset)
node _T_278 = eq(_T_277, UInt<1>(0h0))
when _T_278 :
node _T_279 = eq(_T_276, UInt<1>(0h0))
when _T_279 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_276, UInt<1>(0h1), "") : assert_9
node _T_280 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_280 :
node _T_281 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_282 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_283 = and(_T_281, _T_282)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_284 = shr(io.in.a.bits.source, 2)
node _T_285 = eq(_T_284, UInt<1>(0h0))
node _T_286 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_287 = and(_T_285, _T_286)
node _T_288 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_289 = and(_T_287, _T_288)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_290 = shr(io.in.a.bits.source, 2)
node _T_291 = eq(_T_290, UInt<1>(0h1))
node _T_292 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_293 = and(_T_291, _T_292)
node _T_294 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_295 = and(_T_293, _T_294)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_296 = shr(io.in.a.bits.source, 2)
node _T_297 = eq(_T_296, UInt<2>(0h2))
node _T_298 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_299 = and(_T_297, _T_298)
node _T_300 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_301 = and(_T_299, _T_300)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_302 = shr(io.in.a.bits.source, 2)
node _T_303 = eq(_T_302, UInt<2>(0h3))
node _T_304 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_305 = and(_T_303, _T_304)
node _T_306 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_307 = and(_T_305, _T_306)
node _T_308 = or(_T_289, _T_295)
node _T_309 = or(_T_308, _T_301)
node _T_310 = or(_T_309, _T_307)
node _T_311 = and(_T_283, _T_310)
node _T_312 = or(UInt<1>(0h0), _T_311)
node _T_313 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_314 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_315 = cvt(_T_314)
node _T_316 = and(_T_315, asSInt(UInt<14>(0h2000)))
node _T_317 = asSInt(_T_316)
node _T_318 = eq(_T_317, asSInt(UInt<1>(0h0)))
node _T_319 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_320 = cvt(_T_319)
node _T_321 = and(_T_320, asSInt(UInt<13>(0h1000)))
node _T_322 = asSInt(_T_321)
node _T_323 = eq(_T_322, asSInt(UInt<1>(0h0)))
node _T_324 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_325 = cvt(_T_324)
node _T_326 = and(_T_325, asSInt(UInt<17>(0h10000)))
node _T_327 = asSInt(_T_326)
node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0)))
node _T_329 = xor(io.in.a.bits.address, UInt<18>(0h20000))
node _T_330 = cvt(_T_329)
node _T_331 = and(_T_330, asSInt(UInt<15>(0h4000)))
node _T_332 = asSInt(_T_331)
node _T_333 = eq(_T_332, asSInt(UInt<1>(0h0)))
node _T_334 = xor(io.in.a.bits.address, UInt<18>(0h24000))
node _T_335 = cvt(_T_334)
node _T_336 = and(_T_335, asSInt(UInt<13>(0h1000)))
node _T_337 = asSInt(_T_336)
node _T_338 = eq(_T_337, asSInt(UInt<1>(0h0)))
node _T_339 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_340 = cvt(_T_339)
node _T_341 = and(_T_340, asSInt(UInt<18>(0h2f000)))
node _T_342 = asSInt(_T_341)
node _T_343 = eq(_T_342, asSInt(UInt<1>(0h0)))
node _T_344 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_345 = cvt(_T_344)
node _T_346 = and(_T_345, asSInt(UInt<17>(0h10000)))
node _T_347 = asSInt(_T_346)
node _T_348 = eq(_T_347, asSInt(UInt<1>(0h0)))
node _T_349 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_350 = cvt(_T_349)
node _T_351 = and(_T_350, asSInt(UInt<13>(0h1000)))
node _T_352 = asSInt(_T_351)
node _T_353 = eq(_T_352, asSInt(UInt<1>(0h0)))
node _T_354 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_355 = cvt(_T_354)
node _T_356 = and(_T_355, asSInt(UInt<27>(0h4000000)))
node _T_357 = asSInt(_T_356)
node _T_358 = eq(_T_357, asSInt(UInt<1>(0h0)))
node _T_359 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_360 = cvt(_T_359)
node _T_361 = and(_T_360, asSInt(UInt<13>(0h1000)))
node _T_362 = asSInt(_T_361)
node _T_363 = eq(_T_362, asSInt(UInt<1>(0h0)))
node _T_364 = or(_T_318, _T_323)
node _T_365 = or(_T_364, _T_328)
node _T_366 = or(_T_365, _T_333)
node _T_367 = or(_T_366, _T_338)
node _T_368 = or(_T_367, _T_343)
node _T_369 = or(_T_368, _T_348)
node _T_370 = or(_T_369, _T_353)
node _T_371 = or(_T_370, _T_358)
node _T_372 = or(_T_371, _T_363)
node _T_373 = and(_T_313, _T_372)
node _T_374 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_375 = or(UInt<1>(0h0), _T_374)
node _T_376 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_377 = cvt(_T_376)
node _T_378 = and(_T_377, asSInt(UInt<17>(0h10000)))
node _T_379 = asSInt(_T_378)
node _T_380 = eq(_T_379, asSInt(UInt<1>(0h0)))
node _T_381 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_382 = cvt(_T_381)
node _T_383 = and(_T_382, asSInt(UInt<29>(0h10000000)))
node _T_384 = asSInt(_T_383)
node _T_385 = eq(_T_384, asSInt(UInt<1>(0h0)))
node _T_386 = or(_T_380, _T_385)
node _T_387 = and(_T_375, _T_386)
node _T_388 = or(UInt<1>(0h0), _T_373)
node _T_389 = or(_T_388, _T_387)
node _T_390 = and(_T_312, _T_389)
node _T_391 = asUInt(reset)
node _T_392 = eq(_T_391, UInt<1>(0h0))
when _T_392 :
node _T_393 = eq(_T_390, UInt<1>(0h0))
when _T_393 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_390, UInt<1>(0h1), "") : assert_10
node _T_394 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_395 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_396 = and(_T_394, _T_395)
node _T_397 = or(UInt<1>(0h0), _T_396)
node _T_398 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_399 = cvt(_T_398)
node _T_400 = and(_T_399, asSInt(UInt<14>(0h2000)))
node _T_401 = asSInt(_T_400)
node _T_402 = eq(_T_401, asSInt(UInt<1>(0h0)))
node _T_403 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_404 = cvt(_T_403)
node _T_405 = and(_T_404, asSInt(UInt<13>(0h1000)))
node _T_406 = asSInt(_T_405)
node _T_407 = eq(_T_406, asSInt(UInt<1>(0h0)))
node _T_408 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_409 = cvt(_T_408)
node _T_410 = and(_T_409, asSInt(UInt<17>(0h10000)))
node _T_411 = asSInt(_T_410)
node _T_412 = eq(_T_411, asSInt(UInt<1>(0h0)))
node _T_413 = xor(io.in.a.bits.address, UInt<18>(0h20000))
node _T_414 = cvt(_T_413)
node _T_415 = and(_T_414, asSInt(UInt<15>(0h4000)))
node _T_416 = asSInt(_T_415)
node _T_417 = eq(_T_416, asSInt(UInt<1>(0h0)))
node _T_418 = xor(io.in.a.bits.address, UInt<18>(0h24000))
node _T_419 = cvt(_T_418)
node _T_420 = and(_T_419, asSInt(UInt<13>(0h1000)))
node _T_421 = asSInt(_T_420)
node _T_422 = eq(_T_421, asSInt(UInt<1>(0h0)))
node _T_423 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_424 = cvt(_T_423)
node _T_425 = and(_T_424, asSInt(UInt<18>(0h2f000)))
node _T_426 = asSInt(_T_425)
node _T_427 = eq(_T_426, asSInt(UInt<1>(0h0)))
node _T_428 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_429 = cvt(_T_428)
node _T_430 = and(_T_429, asSInt(UInt<17>(0h10000)))
node _T_431 = asSInt(_T_430)
node _T_432 = eq(_T_431, asSInt(UInt<1>(0h0)))
node _T_433 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_434 = cvt(_T_433)
node _T_435 = and(_T_434, asSInt(UInt<13>(0h1000)))
node _T_436 = asSInt(_T_435)
node _T_437 = eq(_T_436, asSInt(UInt<1>(0h0)))
node _T_438 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_439 = cvt(_T_438)
node _T_440 = and(_T_439, asSInt(UInt<17>(0h10000)))
node _T_441 = asSInt(_T_440)
node _T_442 = eq(_T_441, asSInt(UInt<1>(0h0)))
node _T_443 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_444 = cvt(_T_443)
node _T_445 = and(_T_444, asSInt(UInt<27>(0h4000000)))
node _T_446 = asSInt(_T_445)
node _T_447 = eq(_T_446, asSInt(UInt<1>(0h0)))
node _T_448 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_449 = cvt(_T_448)
node _T_450 = and(_T_449, asSInt(UInt<13>(0h1000)))
node _T_451 = asSInt(_T_450)
node _T_452 = eq(_T_451, asSInt(UInt<1>(0h0)))
node _T_453 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_454 = cvt(_T_453)
node _T_455 = and(_T_454, asSInt(UInt<29>(0h10000000)))
node _T_456 = asSInt(_T_455)
node _T_457 = eq(_T_456, asSInt(UInt<1>(0h0)))
node _T_458 = or(_T_402, _T_407)
node _T_459 = or(_T_458, _T_412)
node _T_460 = or(_T_459, _T_417)
node _T_461 = or(_T_460, _T_422)
node _T_462 = or(_T_461, _T_427)
node _T_463 = or(_T_462, _T_432)
node _T_464 = or(_T_463, _T_437)
node _T_465 = or(_T_464, _T_442)
node _T_466 = or(_T_465, _T_447)
node _T_467 = or(_T_466, _T_452)
node _T_468 = or(_T_467, _T_457)
node _T_469 = and(_T_397, _T_468)
node _T_470 = or(UInt<1>(0h0), _T_469)
node _T_471 = and(UInt<1>(0h0), _T_470)
node _T_472 = asUInt(reset)
node _T_473 = eq(_T_472, UInt<1>(0h0))
when _T_473 :
node _T_474 = eq(_T_471, UInt<1>(0h0))
when _T_474 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_471, UInt<1>(0h1), "") : assert_11
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(source_ok, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_478 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_T_478, UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_478, UInt<1>(0h1), "") : assert_13
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(is_aligned, UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_485 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_486 = asUInt(reset)
node _T_487 = eq(_T_486, UInt<1>(0h0))
when _T_487 :
node _T_488 = eq(_T_485, UInt<1>(0h0))
when _T_488 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_485, UInt<1>(0h1), "") : assert_15
node _T_489 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_490 = asUInt(reset)
node _T_491 = eq(_T_490, UInt<1>(0h0))
when _T_491 :
node _T_492 = eq(_T_489, UInt<1>(0h0))
when _T_492 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_489, UInt<1>(0h1), "") : assert_16
node _T_493 = not(io.in.a.bits.mask)
node _T_494 = eq(_T_493, UInt<1>(0h0))
node _T_495 = asUInt(reset)
node _T_496 = eq(_T_495, UInt<1>(0h0))
when _T_496 :
node _T_497 = eq(_T_494, UInt<1>(0h0))
when _T_497 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_494, UInt<1>(0h1), "") : assert_17
node _T_498 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_499 = asUInt(reset)
node _T_500 = eq(_T_499, UInt<1>(0h0))
when _T_500 :
node _T_501 = eq(_T_498, UInt<1>(0h0))
when _T_501 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_498, UInt<1>(0h1), "") : assert_18
node _T_502 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_502 :
node _T_503 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_504 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_505 = and(_T_503, _T_504)
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_506 = shr(io.in.a.bits.source, 2)
node _T_507 = eq(_T_506, UInt<1>(0h0))
node _T_508 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_509 = and(_T_507, _T_508)
node _T_510 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_511 = and(_T_509, _T_510)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_512 = shr(io.in.a.bits.source, 2)
node _T_513 = eq(_T_512, UInt<1>(0h1))
node _T_514 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_515 = and(_T_513, _T_514)
node _T_516 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_517 = and(_T_515, _T_516)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_518 = shr(io.in.a.bits.source, 2)
node _T_519 = eq(_T_518, UInt<2>(0h2))
node _T_520 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_521 = and(_T_519, _T_520)
node _T_522 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_523 = and(_T_521, _T_522)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_524 = shr(io.in.a.bits.source, 2)
node _T_525 = eq(_T_524, UInt<2>(0h3))
node _T_526 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_527 = and(_T_525, _T_526)
node _T_528 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_529 = and(_T_527, _T_528)
node _T_530 = or(_T_511, _T_517)
node _T_531 = or(_T_530, _T_523)
node _T_532 = or(_T_531, _T_529)
node _T_533 = and(_T_505, _T_532)
node _T_534 = or(UInt<1>(0h0), _T_533)
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_534, UInt<1>(0h1), "") : assert_19
node _T_538 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_539 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_540 = and(_T_538, _T_539)
node _T_541 = or(UInt<1>(0h0), _T_540)
node _T_542 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_543 = cvt(_T_542)
node _T_544 = and(_T_543, asSInt(UInt<13>(0h1000)))
node _T_545 = asSInt(_T_544)
node _T_546 = eq(_T_545, asSInt(UInt<1>(0h0)))
node _T_547 = and(_T_541, _T_546)
node _T_548 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_549 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_550 = and(_T_548, _T_549)
node _T_551 = or(UInt<1>(0h0), _T_550)
node _T_552 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_553 = cvt(_T_552)
node _T_554 = and(_T_553, asSInt(UInt<14>(0h2000)))
node _T_555 = asSInt(_T_554)
node _T_556 = eq(_T_555, asSInt(UInt<1>(0h0)))
node _T_557 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_558 = cvt(_T_557)
node _T_559 = and(_T_558, asSInt(UInt<17>(0h10000)))
node _T_560 = asSInt(_T_559)
node _T_561 = eq(_T_560, asSInt(UInt<1>(0h0)))
node _T_562 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_563 = cvt(_T_562)
node _T_564 = and(_T_563, asSInt(UInt<18>(0h2f000)))
node _T_565 = asSInt(_T_564)
node _T_566 = eq(_T_565, asSInt(UInt<1>(0h0)))
node _T_567 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_568 = cvt(_T_567)
node _T_569 = and(_T_568, asSInt(UInt<17>(0h10000)))
node _T_570 = asSInt(_T_569)
node _T_571 = eq(_T_570, asSInt(UInt<1>(0h0)))
node _T_572 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_573 = cvt(_T_572)
node _T_574 = and(_T_573, asSInt(UInt<13>(0h1000)))
node _T_575 = asSInt(_T_574)
node _T_576 = eq(_T_575, asSInt(UInt<1>(0h0)))
node _T_577 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_578 = cvt(_T_577)
node _T_579 = and(_T_578, asSInt(UInt<17>(0h10000)))
node _T_580 = asSInt(_T_579)
node _T_581 = eq(_T_580, asSInt(UInt<1>(0h0)))
node _T_582 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_583 = cvt(_T_582)
node _T_584 = and(_T_583, asSInt(UInt<27>(0h4000000)))
node _T_585 = asSInt(_T_584)
node _T_586 = eq(_T_585, asSInt(UInt<1>(0h0)))
node _T_587 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_588 = cvt(_T_587)
node _T_589 = and(_T_588, asSInt(UInt<13>(0h1000)))
node _T_590 = asSInt(_T_589)
node _T_591 = eq(_T_590, asSInt(UInt<1>(0h0)))
node _T_592 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_593 = cvt(_T_592)
node _T_594 = and(_T_593, asSInt(UInt<29>(0h10000000)))
node _T_595 = asSInt(_T_594)
node _T_596 = eq(_T_595, asSInt(UInt<1>(0h0)))
node _T_597 = or(_T_556, _T_561)
node _T_598 = or(_T_597, _T_566)
node _T_599 = or(_T_598, _T_571)
node _T_600 = or(_T_599, _T_576)
node _T_601 = or(_T_600, _T_581)
node _T_602 = or(_T_601, _T_586)
node _T_603 = or(_T_602, _T_591)
node _T_604 = or(_T_603, _T_596)
node _T_605 = and(_T_551, _T_604)
node _T_606 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_607 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_608 = and(_T_606, _T_607)
node _T_609 = or(UInt<1>(0h0), _T_608)
node _T_610 = xor(io.in.a.bits.address, UInt<18>(0h20000))
node _T_611 = cvt(_T_610)
node _T_612 = and(_T_611, asSInt(UInt<15>(0h4000)))
node _T_613 = asSInt(_T_612)
node _T_614 = eq(_T_613, asSInt(UInt<1>(0h0)))
node _T_615 = xor(io.in.a.bits.address, UInt<18>(0h24000))
node _T_616 = cvt(_T_615)
node _T_617 = and(_T_616, asSInt(UInt<13>(0h1000)))
node _T_618 = asSInt(_T_617)
node _T_619 = eq(_T_618, asSInt(UInt<1>(0h0)))
node _T_620 = or(_T_614, _T_619)
node _T_621 = and(_T_609, _T_620)
node _T_622 = or(UInt<1>(0h0), _T_547)
node _T_623 = or(_T_622, _T_605)
node _T_624 = or(_T_623, _T_621)
node _T_625 = asUInt(reset)
node _T_626 = eq(_T_625, UInt<1>(0h0))
when _T_626 :
node _T_627 = eq(_T_624, UInt<1>(0h0))
when _T_627 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_624, UInt<1>(0h1), "") : assert_20
node _T_628 = asUInt(reset)
node _T_629 = eq(_T_628, UInt<1>(0h0))
when _T_629 :
node _T_630 = eq(source_ok, UInt<1>(0h0))
when _T_630 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(is_aligned, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_634 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_635 = asUInt(reset)
node _T_636 = eq(_T_635, UInt<1>(0h0))
when _T_636 :
node _T_637 = eq(_T_634, UInt<1>(0h0))
when _T_637 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_634, UInt<1>(0h1), "") : assert_23
node _T_638 = eq(io.in.a.bits.mask, mask)
node _T_639 = asUInt(reset)
node _T_640 = eq(_T_639, UInt<1>(0h0))
when _T_640 :
node _T_641 = eq(_T_638, UInt<1>(0h0))
when _T_641 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_638, UInt<1>(0h1), "") : assert_24
node _T_642 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_643 = asUInt(reset)
node _T_644 = eq(_T_643, UInt<1>(0h0))
when _T_644 :
node _T_645 = eq(_T_642, UInt<1>(0h0))
when _T_645 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_642, UInt<1>(0h1), "") : assert_25
node _T_646 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_646 :
node _T_647 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_648 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_649 = and(_T_647, _T_648)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_650 = shr(io.in.a.bits.source, 2)
node _T_651 = eq(_T_650, UInt<1>(0h0))
node _T_652 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_653 = and(_T_651, _T_652)
node _T_654 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_655 = and(_T_653, _T_654)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_656 = shr(io.in.a.bits.source, 2)
node _T_657 = eq(_T_656, UInt<1>(0h1))
node _T_658 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_659 = and(_T_657, _T_658)
node _T_660 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_661 = and(_T_659, _T_660)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_662 = shr(io.in.a.bits.source, 2)
node _T_663 = eq(_T_662, UInt<2>(0h2))
node _T_664 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_665 = and(_T_663, _T_664)
node _T_666 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_667 = and(_T_665, _T_666)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_668 = shr(io.in.a.bits.source, 2)
node _T_669 = eq(_T_668, UInt<2>(0h3))
node _T_670 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_671 = and(_T_669, _T_670)
node _T_672 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_673 = and(_T_671, _T_672)
node _T_674 = or(_T_655, _T_661)
node _T_675 = or(_T_674, _T_667)
node _T_676 = or(_T_675, _T_673)
node _T_677 = and(_T_649, _T_676)
node _T_678 = or(UInt<1>(0h0), _T_677)
node _T_679 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_680 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_681 = and(_T_679, _T_680)
node _T_682 = or(UInt<1>(0h0), _T_681)
node _T_683 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_684 = cvt(_T_683)
node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000)))
node _T_686 = asSInt(_T_685)
node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0)))
node _T_688 = and(_T_682, _T_687)
node _T_689 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_690 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_691 = and(_T_689, _T_690)
node _T_692 = or(UInt<1>(0h0), _T_691)
node _T_693 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_694 = cvt(_T_693)
node _T_695 = and(_T_694, asSInt(UInt<14>(0h2000)))
node _T_696 = asSInt(_T_695)
node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0)))
node _T_698 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_699 = cvt(_T_698)
node _T_700 = and(_T_699, asSInt(UInt<18>(0h2f000)))
node _T_701 = asSInt(_T_700)
node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0)))
node _T_703 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_704 = cvt(_T_703)
node _T_705 = and(_T_704, asSInt(UInt<17>(0h10000)))
node _T_706 = asSInt(_T_705)
node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0)))
node _T_708 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_709 = cvt(_T_708)
node _T_710 = and(_T_709, asSInt(UInt<13>(0h1000)))
node _T_711 = asSInt(_T_710)
node _T_712 = eq(_T_711, asSInt(UInt<1>(0h0)))
node _T_713 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_714 = cvt(_T_713)
node _T_715 = and(_T_714, asSInt(UInt<17>(0h10000)))
node _T_716 = asSInt(_T_715)
node _T_717 = eq(_T_716, asSInt(UInt<1>(0h0)))
node _T_718 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_719 = cvt(_T_718)
node _T_720 = and(_T_719, asSInt(UInt<27>(0h4000000)))
node _T_721 = asSInt(_T_720)
node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0)))
node _T_723 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_724 = cvt(_T_723)
node _T_725 = and(_T_724, asSInt(UInt<13>(0h1000)))
node _T_726 = asSInt(_T_725)
node _T_727 = eq(_T_726, asSInt(UInt<1>(0h0)))
node _T_728 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_729 = cvt(_T_728)
node _T_730 = and(_T_729, asSInt(UInt<29>(0h10000000)))
node _T_731 = asSInt(_T_730)
node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0)))
node _T_733 = or(_T_697, _T_702)
node _T_734 = or(_T_733, _T_707)
node _T_735 = or(_T_734, _T_712)
node _T_736 = or(_T_735, _T_717)
node _T_737 = or(_T_736, _T_722)
node _T_738 = or(_T_737, _T_727)
node _T_739 = or(_T_738, _T_732)
node _T_740 = and(_T_692, _T_739)
node _T_741 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_742 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_743 = cvt(_T_742)
node _T_744 = and(_T_743, asSInt(UInt<17>(0h10000)))
node _T_745 = asSInt(_T_744)
node _T_746 = eq(_T_745, asSInt(UInt<1>(0h0)))
node _T_747 = and(_T_741, _T_746)
node _T_748 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_749 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_750 = and(_T_748, _T_749)
node _T_751 = or(UInt<1>(0h0), _T_750)
node _T_752 = xor(io.in.a.bits.address, UInt<18>(0h20000))
node _T_753 = cvt(_T_752)
node _T_754 = and(_T_753, asSInt(UInt<15>(0h4000)))
node _T_755 = asSInt(_T_754)
node _T_756 = eq(_T_755, asSInt(UInt<1>(0h0)))
node _T_757 = xor(io.in.a.bits.address, UInt<18>(0h24000))
node _T_758 = cvt(_T_757)
node _T_759 = and(_T_758, asSInt(UInt<13>(0h1000)))
node _T_760 = asSInt(_T_759)
node _T_761 = eq(_T_760, asSInt(UInt<1>(0h0)))
node _T_762 = or(_T_756, _T_761)
node _T_763 = and(_T_751, _T_762)
node _T_764 = or(UInt<1>(0h0), _T_688)
node _T_765 = or(_T_764, _T_740)
node _T_766 = or(_T_765, _T_747)
node _T_767 = or(_T_766, _T_763)
node _T_768 = and(_T_678, _T_767)
node _T_769 = asUInt(reset)
node _T_770 = eq(_T_769, UInt<1>(0h0))
when _T_770 :
node _T_771 = eq(_T_768, UInt<1>(0h0))
when _T_771 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_768, UInt<1>(0h1), "") : assert_26
node _T_772 = asUInt(reset)
node _T_773 = eq(_T_772, UInt<1>(0h0))
when _T_773 :
node _T_774 = eq(source_ok, UInt<1>(0h0))
when _T_774 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_775 = asUInt(reset)
node _T_776 = eq(_T_775, UInt<1>(0h0))
when _T_776 :
node _T_777 = eq(is_aligned, UInt<1>(0h0))
when _T_777 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_778 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_779 = asUInt(reset)
node _T_780 = eq(_T_779, UInt<1>(0h0))
when _T_780 :
node _T_781 = eq(_T_778, UInt<1>(0h0))
when _T_781 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_778, UInt<1>(0h1), "") : assert_29
node _T_782 = eq(io.in.a.bits.mask, mask)
node _T_783 = asUInt(reset)
node _T_784 = eq(_T_783, UInt<1>(0h0))
when _T_784 :
node _T_785 = eq(_T_782, UInt<1>(0h0))
when _T_785 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_782, UInt<1>(0h1), "") : assert_30
node _T_786 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_786 :
node _T_787 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_788 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_789 = and(_T_787, _T_788)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_790 = shr(io.in.a.bits.source, 2)
node _T_791 = eq(_T_790, UInt<1>(0h0))
node _T_792 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_793 = and(_T_791, _T_792)
node _T_794 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_795 = and(_T_793, _T_794)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_796 = shr(io.in.a.bits.source, 2)
node _T_797 = eq(_T_796, UInt<1>(0h1))
node _T_798 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_799 = and(_T_797, _T_798)
node _T_800 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_801 = and(_T_799, _T_800)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_802 = shr(io.in.a.bits.source, 2)
node _T_803 = eq(_T_802, UInt<2>(0h2))
node _T_804 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_805 = and(_T_803, _T_804)
node _T_806 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_807 = and(_T_805, _T_806)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_808 = shr(io.in.a.bits.source, 2)
node _T_809 = eq(_T_808, UInt<2>(0h3))
node _T_810 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_811 = and(_T_809, _T_810)
node _T_812 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_813 = and(_T_811, _T_812)
node _T_814 = or(_T_795, _T_801)
node _T_815 = or(_T_814, _T_807)
node _T_816 = or(_T_815, _T_813)
node _T_817 = and(_T_789, _T_816)
node _T_818 = or(UInt<1>(0h0), _T_817)
node _T_819 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_820 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_821 = and(_T_819, _T_820)
node _T_822 = or(UInt<1>(0h0), _T_821)
node _T_823 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_824 = cvt(_T_823)
node _T_825 = and(_T_824, asSInt(UInt<13>(0h1000)))
node _T_826 = asSInt(_T_825)
node _T_827 = eq(_T_826, asSInt(UInt<1>(0h0)))
node _T_828 = and(_T_822, _T_827)
node _T_829 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_830 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_831 = and(_T_829, _T_830)
node _T_832 = or(UInt<1>(0h0), _T_831)
node _T_833 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_834 = cvt(_T_833)
node _T_835 = and(_T_834, asSInt(UInt<14>(0h2000)))
node _T_836 = asSInt(_T_835)
node _T_837 = eq(_T_836, asSInt(UInt<1>(0h0)))
node _T_838 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_839 = cvt(_T_838)
node _T_840 = and(_T_839, asSInt(UInt<18>(0h2f000)))
node _T_841 = asSInt(_T_840)
node _T_842 = eq(_T_841, asSInt(UInt<1>(0h0)))
node _T_843 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_844 = cvt(_T_843)
node _T_845 = and(_T_844, asSInt(UInt<17>(0h10000)))
node _T_846 = asSInt(_T_845)
node _T_847 = eq(_T_846, asSInt(UInt<1>(0h0)))
node _T_848 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_849 = cvt(_T_848)
node _T_850 = and(_T_849, asSInt(UInt<13>(0h1000)))
node _T_851 = asSInt(_T_850)
node _T_852 = eq(_T_851, asSInt(UInt<1>(0h0)))
node _T_853 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_854 = cvt(_T_853)
node _T_855 = and(_T_854, asSInt(UInt<17>(0h10000)))
node _T_856 = asSInt(_T_855)
node _T_857 = eq(_T_856, asSInt(UInt<1>(0h0)))
node _T_858 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_859 = cvt(_T_858)
node _T_860 = and(_T_859, asSInt(UInt<27>(0h4000000)))
node _T_861 = asSInt(_T_860)
node _T_862 = eq(_T_861, asSInt(UInt<1>(0h0)))
node _T_863 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_864 = cvt(_T_863)
node _T_865 = and(_T_864, asSInt(UInt<13>(0h1000)))
node _T_866 = asSInt(_T_865)
node _T_867 = eq(_T_866, asSInt(UInt<1>(0h0)))
node _T_868 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_869 = cvt(_T_868)
node _T_870 = and(_T_869, asSInt(UInt<29>(0h10000000)))
node _T_871 = asSInt(_T_870)
node _T_872 = eq(_T_871, asSInt(UInt<1>(0h0)))
node _T_873 = or(_T_837, _T_842)
node _T_874 = or(_T_873, _T_847)
node _T_875 = or(_T_874, _T_852)
node _T_876 = or(_T_875, _T_857)
node _T_877 = or(_T_876, _T_862)
node _T_878 = or(_T_877, _T_867)
node _T_879 = or(_T_878, _T_872)
node _T_880 = and(_T_832, _T_879)
node _T_881 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_882 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_883 = cvt(_T_882)
node _T_884 = and(_T_883, asSInt(UInt<17>(0h10000)))
node _T_885 = asSInt(_T_884)
node _T_886 = eq(_T_885, asSInt(UInt<1>(0h0)))
node _T_887 = and(_T_881, _T_886)
node _T_888 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_889 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_890 = and(_T_888, _T_889)
node _T_891 = or(UInt<1>(0h0), _T_890)
node _T_892 = xor(io.in.a.bits.address, UInt<18>(0h20000))
node _T_893 = cvt(_T_892)
node _T_894 = and(_T_893, asSInt(UInt<15>(0h4000)))
node _T_895 = asSInt(_T_894)
node _T_896 = eq(_T_895, asSInt(UInt<1>(0h0)))
node _T_897 = xor(io.in.a.bits.address, UInt<18>(0h24000))
node _T_898 = cvt(_T_897)
node _T_899 = and(_T_898, asSInt(UInt<13>(0h1000)))
node _T_900 = asSInt(_T_899)
node _T_901 = eq(_T_900, asSInt(UInt<1>(0h0)))
node _T_902 = or(_T_896, _T_901)
node _T_903 = and(_T_891, _T_902)
node _T_904 = or(UInt<1>(0h0), _T_828)
node _T_905 = or(_T_904, _T_880)
node _T_906 = or(_T_905, _T_887)
node _T_907 = or(_T_906, _T_903)
node _T_908 = and(_T_818, _T_907)
node _T_909 = asUInt(reset)
node _T_910 = eq(_T_909, UInt<1>(0h0))
when _T_910 :
node _T_911 = eq(_T_908, UInt<1>(0h0))
when _T_911 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_908, UInt<1>(0h1), "") : assert_31
node _T_912 = asUInt(reset)
node _T_913 = eq(_T_912, UInt<1>(0h0))
when _T_913 :
node _T_914 = eq(source_ok, UInt<1>(0h0))
when _T_914 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_915 = asUInt(reset)
node _T_916 = eq(_T_915, UInt<1>(0h0))
when _T_916 :
node _T_917 = eq(is_aligned, UInt<1>(0h0))
when _T_917 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_918 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_919 = asUInt(reset)
node _T_920 = eq(_T_919, UInt<1>(0h0))
when _T_920 :
node _T_921 = eq(_T_918, UInt<1>(0h0))
when _T_921 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_918, UInt<1>(0h1), "") : assert_34
node _T_922 = not(mask)
node _T_923 = and(io.in.a.bits.mask, _T_922)
node _T_924 = eq(_T_923, UInt<1>(0h0))
node _T_925 = asUInt(reset)
node _T_926 = eq(_T_925, UInt<1>(0h0))
when _T_926 :
node _T_927 = eq(_T_924, UInt<1>(0h0))
when _T_927 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_924, UInt<1>(0h1), "") : assert_35
node _T_928 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_928 :
node _T_929 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_930 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_931 = and(_T_929, _T_930)
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_932 = shr(io.in.a.bits.source, 2)
node _T_933 = eq(_T_932, UInt<1>(0h0))
node _T_934 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_935 = and(_T_933, _T_934)
node _T_936 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_937 = and(_T_935, _T_936)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_938 = shr(io.in.a.bits.source, 2)
node _T_939 = eq(_T_938, UInt<1>(0h1))
node _T_940 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_941 = and(_T_939, _T_940)
node _T_942 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_943 = and(_T_941, _T_942)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_944 = shr(io.in.a.bits.source, 2)
node _T_945 = eq(_T_944, UInt<2>(0h2))
node _T_946 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_947 = and(_T_945, _T_946)
node _T_948 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_949 = and(_T_947, _T_948)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_950 = shr(io.in.a.bits.source, 2)
node _T_951 = eq(_T_950, UInt<2>(0h3))
node _T_952 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_953 = and(_T_951, _T_952)
node _T_954 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_955 = and(_T_953, _T_954)
node _T_956 = or(_T_937, _T_943)
node _T_957 = or(_T_956, _T_949)
node _T_958 = or(_T_957, _T_955)
node _T_959 = and(_T_931, _T_958)
node _T_960 = or(UInt<1>(0h0), _T_959)
node _T_961 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_962 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_963 = and(_T_961, _T_962)
node _T_964 = or(UInt<1>(0h0), _T_963)
node _T_965 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_966 = cvt(_T_965)
node _T_967 = and(_T_966, asSInt(UInt<14>(0h2000)))
node _T_968 = asSInt(_T_967)
node _T_969 = eq(_T_968, asSInt(UInt<1>(0h0)))
node _T_970 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_971 = cvt(_T_970)
node _T_972 = and(_T_971, asSInt(UInt<13>(0h1000)))
node _T_973 = asSInt(_T_972)
node _T_974 = eq(_T_973, asSInt(UInt<1>(0h0)))
node _T_975 = xor(io.in.a.bits.address, UInt<18>(0h20000))
node _T_976 = cvt(_T_975)
node _T_977 = and(_T_976, asSInt(UInt<15>(0h4000)))
node _T_978 = asSInt(_T_977)
node _T_979 = eq(_T_978, asSInt(UInt<1>(0h0)))
node _T_980 = xor(io.in.a.bits.address, UInt<18>(0h24000))
node _T_981 = cvt(_T_980)
node _T_982 = and(_T_981, asSInt(UInt<13>(0h1000)))
node _T_983 = asSInt(_T_982)
node _T_984 = eq(_T_983, asSInt(UInt<1>(0h0)))
node _T_985 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_986 = cvt(_T_985)
node _T_987 = and(_T_986, asSInt(UInt<18>(0h2f000)))
node _T_988 = asSInt(_T_987)
node _T_989 = eq(_T_988, asSInt(UInt<1>(0h0)))
node _T_990 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_991 = cvt(_T_990)
node _T_992 = and(_T_991, asSInt(UInt<17>(0h10000)))
node _T_993 = asSInt(_T_992)
node _T_994 = eq(_T_993, asSInt(UInt<1>(0h0)))
node _T_995 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_996 = cvt(_T_995)
node _T_997 = and(_T_996, asSInt(UInt<13>(0h1000)))
node _T_998 = asSInt(_T_997)
node _T_999 = eq(_T_998, asSInt(UInt<1>(0h0)))
node _T_1000 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_1001 = cvt(_T_1000)
node _T_1002 = and(_T_1001, asSInt(UInt<17>(0h10000)))
node _T_1003 = asSInt(_T_1002)
node _T_1004 = eq(_T_1003, asSInt(UInt<1>(0h0)))
node _T_1005 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1006 = cvt(_T_1005)
node _T_1007 = and(_T_1006, asSInt(UInt<27>(0h4000000)))
node _T_1008 = asSInt(_T_1007)
node _T_1009 = eq(_T_1008, asSInt(UInt<1>(0h0)))
node _T_1010 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1011 = cvt(_T_1010)
node _T_1012 = and(_T_1011, asSInt(UInt<13>(0h1000)))
node _T_1013 = asSInt(_T_1012)
node _T_1014 = eq(_T_1013, asSInt(UInt<1>(0h0)))
node _T_1015 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_1016 = cvt(_T_1015)
node _T_1017 = and(_T_1016, asSInt(UInt<29>(0h10000000)))
node _T_1018 = asSInt(_T_1017)
node _T_1019 = eq(_T_1018, asSInt(UInt<1>(0h0)))
node _T_1020 = or(_T_969, _T_974)
node _T_1021 = or(_T_1020, _T_979)
node _T_1022 = or(_T_1021, _T_984)
node _T_1023 = or(_T_1022, _T_989)
node _T_1024 = or(_T_1023, _T_994)
node _T_1025 = or(_T_1024, _T_999)
node _T_1026 = or(_T_1025, _T_1004)
node _T_1027 = or(_T_1026, _T_1009)
node _T_1028 = or(_T_1027, _T_1014)
node _T_1029 = or(_T_1028, _T_1019)
node _T_1030 = and(_T_964, _T_1029)
node _T_1031 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1032 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1033 = cvt(_T_1032)
node _T_1034 = and(_T_1033, asSInt(UInt<17>(0h10000)))
node _T_1035 = asSInt(_T_1034)
node _T_1036 = eq(_T_1035, asSInt(UInt<1>(0h0)))
node _T_1037 = and(_T_1031, _T_1036)
node _T_1038 = or(UInt<1>(0h0), _T_1030)
node _T_1039 = or(_T_1038, _T_1037)
node _T_1040 = and(_T_960, _T_1039)
node _T_1041 = asUInt(reset)
node _T_1042 = eq(_T_1041, UInt<1>(0h0))
when _T_1042 :
node _T_1043 = eq(_T_1040, UInt<1>(0h0))
when _T_1043 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_1040, UInt<1>(0h1), "") : assert_36
node _T_1044 = asUInt(reset)
node _T_1045 = eq(_T_1044, UInt<1>(0h0))
when _T_1045 :
node _T_1046 = eq(source_ok, UInt<1>(0h0))
when _T_1046 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_1047 = asUInt(reset)
node _T_1048 = eq(_T_1047, UInt<1>(0h0))
when _T_1048 :
node _T_1049 = eq(is_aligned, UInt<1>(0h0))
when _T_1049 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_1050 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_1051 = asUInt(reset)
node _T_1052 = eq(_T_1051, UInt<1>(0h0))
when _T_1052 :
node _T_1053 = eq(_T_1050, UInt<1>(0h0))
when _T_1053 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_1050, UInt<1>(0h1), "") : assert_39
node _T_1054 = eq(io.in.a.bits.mask, mask)
node _T_1055 = asUInt(reset)
node _T_1056 = eq(_T_1055, UInt<1>(0h0))
when _T_1056 :
node _T_1057 = eq(_T_1054, UInt<1>(0h0))
when _T_1057 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_1054, UInt<1>(0h1), "") : assert_40
node _T_1058 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_1058 :
node _T_1059 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1060 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1061 = and(_T_1059, _T_1060)
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_1062 = shr(io.in.a.bits.source, 2)
node _T_1063 = eq(_T_1062, UInt<1>(0h0))
node _T_1064 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_1065 = and(_T_1063, _T_1064)
node _T_1066 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_1067 = and(_T_1065, _T_1066)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_1068 = shr(io.in.a.bits.source, 2)
node _T_1069 = eq(_T_1068, UInt<1>(0h1))
node _T_1070 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_1071 = and(_T_1069, _T_1070)
node _T_1072 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_1073 = and(_T_1071, _T_1072)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_1074 = shr(io.in.a.bits.source, 2)
node _T_1075 = eq(_T_1074, UInt<2>(0h2))
node _T_1076 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_1077 = and(_T_1075, _T_1076)
node _T_1078 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_1079 = and(_T_1077, _T_1078)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_1080 = shr(io.in.a.bits.source, 2)
node _T_1081 = eq(_T_1080, UInt<2>(0h3))
node _T_1082 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_1083 = and(_T_1081, _T_1082)
node _T_1084 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_1085 = and(_T_1083, _T_1084)
node _T_1086 = or(_T_1067, _T_1073)
node _T_1087 = or(_T_1086, _T_1079)
node _T_1088 = or(_T_1087, _T_1085)
node _T_1089 = and(_T_1061, _T_1088)
node _T_1090 = or(UInt<1>(0h0), _T_1089)
node _T_1091 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1092 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_1093 = and(_T_1091, _T_1092)
node _T_1094 = or(UInt<1>(0h0), _T_1093)
node _T_1095 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1096 = cvt(_T_1095)
node _T_1097 = and(_T_1096, asSInt(UInt<14>(0h2000)))
node _T_1098 = asSInt(_T_1097)
node _T_1099 = eq(_T_1098, asSInt(UInt<1>(0h0)))
node _T_1100 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1101 = cvt(_T_1100)
node _T_1102 = and(_T_1101, asSInt(UInt<13>(0h1000)))
node _T_1103 = asSInt(_T_1102)
node _T_1104 = eq(_T_1103, asSInt(UInt<1>(0h0)))
node _T_1105 = xor(io.in.a.bits.address, UInt<18>(0h20000))
node _T_1106 = cvt(_T_1105)
node _T_1107 = and(_T_1106, asSInt(UInt<15>(0h4000)))
node _T_1108 = asSInt(_T_1107)
node _T_1109 = eq(_T_1108, asSInt(UInt<1>(0h0)))
node _T_1110 = xor(io.in.a.bits.address, UInt<18>(0h24000))
node _T_1111 = cvt(_T_1110)
node _T_1112 = and(_T_1111, asSInt(UInt<13>(0h1000)))
node _T_1113 = asSInt(_T_1112)
node _T_1114 = eq(_T_1113, asSInt(UInt<1>(0h0)))
node _T_1115 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1116 = cvt(_T_1115)
node _T_1117 = and(_T_1116, asSInt(UInt<18>(0h2f000)))
node _T_1118 = asSInt(_T_1117)
node _T_1119 = eq(_T_1118, asSInt(UInt<1>(0h0)))
node _T_1120 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1121 = cvt(_T_1120)
node _T_1122 = and(_T_1121, asSInt(UInt<17>(0h10000)))
node _T_1123 = asSInt(_T_1122)
node _T_1124 = eq(_T_1123, asSInt(UInt<1>(0h0)))
node _T_1125 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1126 = cvt(_T_1125)
node _T_1127 = and(_T_1126, asSInt(UInt<13>(0h1000)))
node _T_1128 = asSInt(_T_1127)
node _T_1129 = eq(_T_1128, asSInt(UInt<1>(0h0)))
node _T_1130 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_1131 = cvt(_T_1130)
node _T_1132 = and(_T_1131, asSInt(UInt<17>(0h10000)))
node _T_1133 = asSInt(_T_1132)
node _T_1134 = eq(_T_1133, asSInt(UInt<1>(0h0)))
node _T_1135 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1136 = cvt(_T_1135)
node _T_1137 = and(_T_1136, asSInt(UInt<27>(0h4000000)))
node _T_1138 = asSInt(_T_1137)
node _T_1139 = eq(_T_1138, asSInt(UInt<1>(0h0)))
node _T_1140 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1141 = cvt(_T_1140)
node _T_1142 = and(_T_1141, asSInt(UInt<13>(0h1000)))
node _T_1143 = asSInt(_T_1142)
node _T_1144 = eq(_T_1143, asSInt(UInt<1>(0h0)))
node _T_1145 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_1146 = cvt(_T_1145)
node _T_1147 = and(_T_1146, asSInt(UInt<29>(0h10000000)))
node _T_1148 = asSInt(_T_1147)
node _T_1149 = eq(_T_1148, asSInt(UInt<1>(0h0)))
node _T_1150 = or(_T_1099, _T_1104)
node _T_1151 = or(_T_1150, _T_1109)
node _T_1152 = or(_T_1151, _T_1114)
node _T_1153 = or(_T_1152, _T_1119)
node _T_1154 = or(_T_1153, _T_1124)
node _T_1155 = or(_T_1154, _T_1129)
node _T_1156 = or(_T_1155, _T_1134)
node _T_1157 = or(_T_1156, _T_1139)
node _T_1158 = or(_T_1157, _T_1144)
node _T_1159 = or(_T_1158, _T_1149)
node _T_1160 = and(_T_1094, _T_1159)
node _T_1161 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1162 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1163 = cvt(_T_1162)
node _T_1164 = and(_T_1163, asSInt(UInt<17>(0h10000)))
node _T_1165 = asSInt(_T_1164)
node _T_1166 = eq(_T_1165, asSInt(UInt<1>(0h0)))
node _T_1167 = and(_T_1161, _T_1166)
node _T_1168 = or(UInt<1>(0h0), _T_1160)
node _T_1169 = or(_T_1168, _T_1167)
node _T_1170 = and(_T_1090, _T_1169)
node _T_1171 = asUInt(reset)
node _T_1172 = eq(_T_1171, UInt<1>(0h0))
when _T_1172 :
node _T_1173 = eq(_T_1170, UInt<1>(0h0))
when _T_1173 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_1170, UInt<1>(0h1), "") : assert_41
node _T_1174 = asUInt(reset)
node _T_1175 = eq(_T_1174, UInt<1>(0h0))
when _T_1175 :
node _T_1176 = eq(source_ok, UInt<1>(0h0))
when _T_1176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_1177 = asUInt(reset)
node _T_1178 = eq(_T_1177, UInt<1>(0h0))
when _T_1178 :
node _T_1179 = eq(is_aligned, UInt<1>(0h0))
when _T_1179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_1180 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_1181 = asUInt(reset)
node _T_1182 = eq(_T_1181, UInt<1>(0h0))
when _T_1182 :
node _T_1183 = eq(_T_1180, UInt<1>(0h0))
when _T_1183 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_1180, UInt<1>(0h1), "") : assert_44
node _T_1184 = eq(io.in.a.bits.mask, mask)
node _T_1185 = asUInt(reset)
node _T_1186 = eq(_T_1185, UInt<1>(0h0))
when _T_1186 :
node _T_1187 = eq(_T_1184, UInt<1>(0h0))
when _T_1187 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_1184, UInt<1>(0h1), "") : assert_45
node _T_1188 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_1188 :
node _T_1189 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1190 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1191 = and(_T_1189, _T_1190)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_1192 = shr(io.in.a.bits.source, 2)
node _T_1193 = eq(_T_1192, UInt<1>(0h0))
node _T_1194 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_1195 = and(_T_1193, _T_1194)
node _T_1196 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_1197 = and(_T_1195, _T_1196)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_1198 = shr(io.in.a.bits.source, 2)
node _T_1199 = eq(_T_1198, UInt<1>(0h1))
node _T_1200 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_1201 = and(_T_1199, _T_1200)
node _T_1202 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_1203 = and(_T_1201, _T_1202)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_1204 = shr(io.in.a.bits.source, 2)
node _T_1205 = eq(_T_1204, UInt<2>(0h2))
node _T_1206 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_1207 = and(_T_1205, _T_1206)
node _T_1208 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_1209 = and(_T_1207, _T_1208)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_1210 = shr(io.in.a.bits.source, 2)
node _T_1211 = eq(_T_1210, UInt<2>(0h3))
node _T_1212 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_1213 = and(_T_1211, _T_1212)
node _T_1214 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_1215 = and(_T_1213, _T_1214)
node _T_1216 = or(_T_1197, _T_1203)
node _T_1217 = or(_T_1216, _T_1209)
node _T_1218 = or(_T_1217, _T_1215)
node _T_1219 = and(_T_1191, _T_1218)
node _T_1220 = or(UInt<1>(0h0), _T_1219)
node _T_1221 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1222 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1223 = and(_T_1221, _T_1222)
node _T_1224 = or(UInt<1>(0h0), _T_1223)
node _T_1225 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1226 = cvt(_T_1225)
node _T_1227 = and(_T_1226, asSInt(UInt<13>(0h1000)))
node _T_1228 = asSInt(_T_1227)
node _T_1229 = eq(_T_1228, asSInt(UInt<1>(0h0)))
node _T_1230 = and(_T_1224, _T_1229)
node _T_1231 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1232 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1233 = cvt(_T_1232)
node _T_1234 = and(_T_1233, asSInt(UInt<14>(0h2000)))
node _T_1235 = asSInt(_T_1234)
node _T_1236 = eq(_T_1235, asSInt(UInt<1>(0h0)))
node _T_1237 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1238 = cvt(_T_1237)
node _T_1239 = and(_T_1238, asSInt(UInt<17>(0h10000)))
node _T_1240 = asSInt(_T_1239)
node _T_1241 = eq(_T_1240, asSInt(UInt<1>(0h0)))
node _T_1242 = xor(io.in.a.bits.address, UInt<18>(0h20000))
node _T_1243 = cvt(_T_1242)
node _T_1244 = and(_T_1243, asSInt(UInt<15>(0h4000)))
node _T_1245 = asSInt(_T_1244)
node _T_1246 = eq(_T_1245, asSInt(UInt<1>(0h0)))
node _T_1247 = xor(io.in.a.bits.address, UInt<18>(0h24000))
node _T_1248 = cvt(_T_1247)
node _T_1249 = and(_T_1248, asSInt(UInt<13>(0h1000)))
node _T_1250 = asSInt(_T_1249)
node _T_1251 = eq(_T_1250, asSInt(UInt<1>(0h0)))
node _T_1252 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1253 = cvt(_T_1252)
node _T_1254 = and(_T_1253, asSInt(UInt<18>(0h2f000)))
node _T_1255 = asSInt(_T_1254)
node _T_1256 = eq(_T_1255, asSInt(UInt<1>(0h0)))
node _T_1257 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1258 = cvt(_T_1257)
node _T_1259 = and(_T_1258, asSInt(UInt<17>(0h10000)))
node _T_1260 = asSInt(_T_1259)
node _T_1261 = eq(_T_1260, asSInt(UInt<1>(0h0)))
node _T_1262 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1263 = cvt(_T_1262)
node _T_1264 = and(_T_1263, asSInt(UInt<13>(0h1000)))
node _T_1265 = asSInt(_T_1264)
node _T_1266 = eq(_T_1265, asSInt(UInt<1>(0h0)))
node _T_1267 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1268 = cvt(_T_1267)
node _T_1269 = and(_T_1268, asSInt(UInt<27>(0h4000000)))
node _T_1270 = asSInt(_T_1269)
node _T_1271 = eq(_T_1270, asSInt(UInt<1>(0h0)))
node _T_1272 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1273 = cvt(_T_1272)
node _T_1274 = and(_T_1273, asSInt(UInt<13>(0h1000)))
node _T_1275 = asSInt(_T_1274)
node _T_1276 = eq(_T_1275, asSInt(UInt<1>(0h0)))
node _T_1277 = or(_T_1236, _T_1241)
node _T_1278 = or(_T_1277, _T_1246)
node _T_1279 = or(_T_1278, _T_1251)
node _T_1280 = or(_T_1279, _T_1256)
node _T_1281 = or(_T_1280, _T_1261)
node _T_1282 = or(_T_1281, _T_1266)
node _T_1283 = or(_T_1282, _T_1271)
node _T_1284 = or(_T_1283, _T_1276)
node _T_1285 = and(_T_1231, _T_1284)
node _T_1286 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1287 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1288 = and(_T_1286, _T_1287)
node _T_1289 = or(UInt<1>(0h0), _T_1288)
node _T_1290 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_1291 = cvt(_T_1290)
node _T_1292 = and(_T_1291, asSInt(UInt<17>(0h10000)))
node _T_1293 = asSInt(_T_1292)
node _T_1294 = eq(_T_1293, asSInt(UInt<1>(0h0)))
node _T_1295 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_1296 = cvt(_T_1295)
node _T_1297 = and(_T_1296, asSInt(UInt<29>(0h10000000)))
node _T_1298 = asSInt(_T_1297)
node _T_1299 = eq(_T_1298, asSInt(UInt<1>(0h0)))
node _T_1300 = or(_T_1294, _T_1299)
node _T_1301 = and(_T_1289, _T_1300)
node _T_1302 = or(UInt<1>(0h0), _T_1230)
node _T_1303 = or(_T_1302, _T_1285)
node _T_1304 = or(_T_1303, _T_1301)
node _T_1305 = and(_T_1220, _T_1304)
node _T_1306 = asUInt(reset)
node _T_1307 = eq(_T_1306, UInt<1>(0h0))
when _T_1307 :
node _T_1308 = eq(_T_1305, UInt<1>(0h0))
when _T_1308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1305, UInt<1>(0h1), "") : assert_46
node _T_1309 = asUInt(reset)
node _T_1310 = eq(_T_1309, UInt<1>(0h0))
when _T_1310 :
node _T_1311 = eq(source_ok, UInt<1>(0h0))
when _T_1311 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1312 = asUInt(reset)
node _T_1313 = eq(_T_1312, UInt<1>(0h0))
when _T_1313 :
node _T_1314 = eq(is_aligned, UInt<1>(0h0))
when _T_1314 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1315 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1316 = asUInt(reset)
node _T_1317 = eq(_T_1316, UInt<1>(0h0))
when _T_1317 :
node _T_1318 = eq(_T_1315, UInt<1>(0h0))
when _T_1318 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1315, UInt<1>(0h1), "") : assert_49
node _T_1319 = eq(io.in.a.bits.mask, mask)
node _T_1320 = asUInt(reset)
node _T_1321 = eq(_T_1320, UInt<1>(0h0))
when _T_1321 :
node _T_1322 = eq(_T_1319, UInt<1>(0h0))
when _T_1322 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1319, UInt<1>(0h1), "") : assert_50
node _T_1323 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1324 = asUInt(reset)
node _T_1325 = eq(_T_1324, UInt<1>(0h0))
when _T_1325 :
node _T_1326 = eq(_T_1323, UInt<1>(0h0))
when _T_1326 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1323, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1327 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1328 = asUInt(reset)
node _T_1329 = eq(_T_1328, UInt<1>(0h0))
when _T_1329 :
node _T_1330 = eq(_T_1327, UInt<1>(0h0))
when _T_1330 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1327, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_26 = shr(io.in.d.bits.source, 2)
node _source_ok_T_27 = eq(_source_ok_T_26, UInt<1>(0h0))
node _source_ok_T_28 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_29 = and(_source_ok_T_27, _source_ok_T_28)
node _source_ok_T_30 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_31 = and(_source_ok_T_29, _source_ok_T_30)
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_32 = shr(io.in.d.bits.source, 2)
node _source_ok_T_33 = eq(_source_ok_T_32, UInt<1>(0h1))
node _source_ok_T_34 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_35 = and(_source_ok_T_33, _source_ok_T_34)
node _source_ok_T_36 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_37 = and(_source_ok_T_35, _source_ok_T_36)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_38 = shr(io.in.d.bits.source, 2)
node _source_ok_T_39 = eq(_source_ok_T_38, UInt<2>(0h2))
node _source_ok_T_40 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_41 = and(_source_ok_T_39, _source_ok_T_40)
node _source_ok_T_42 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_43 = and(_source_ok_T_41, _source_ok_T_42)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_44 = shr(io.in.d.bits.source, 2)
node _source_ok_T_45 = eq(_source_ok_T_44, UInt<2>(0h3))
node _source_ok_T_46 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46)
node _source_ok_T_48 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_49 = and(_source_ok_T_47, _source_ok_T_48)
wire _source_ok_WIRE_1 : UInt<1>[4]
connect _source_ok_WIRE_1[0], _source_ok_T_31
connect _source_ok_WIRE_1[1], _source_ok_T_37
connect _source_ok_WIRE_1[2], _source_ok_T_43
connect _source_ok_WIRE_1[3], _source_ok_T_49
node _source_ok_T_50 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE_1[2])
node source_ok_1 = or(_source_ok_T_51, _source_ok_WIRE_1[3])
node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8))
node _T_1331 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1331 :
node _T_1332 = asUInt(reset)
node _T_1333 = eq(_T_1332, UInt<1>(0h0))
when _T_1333 :
node _T_1334 = eq(source_ok_1, UInt<1>(0h0))
when _T_1334 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1335 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1336 = asUInt(reset)
node _T_1337 = eq(_T_1336, UInt<1>(0h0))
when _T_1337 :
node _T_1338 = eq(_T_1335, UInt<1>(0h0))
when _T_1338 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1335, UInt<1>(0h1), "") : assert_54
node _T_1339 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1340 = asUInt(reset)
node _T_1341 = eq(_T_1340, UInt<1>(0h0))
when _T_1341 :
node _T_1342 = eq(_T_1339, UInt<1>(0h0))
when _T_1342 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1339, UInt<1>(0h1), "") : assert_55
node _T_1343 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1344 = asUInt(reset)
node _T_1345 = eq(_T_1344, UInt<1>(0h0))
when _T_1345 :
node _T_1346 = eq(_T_1343, UInt<1>(0h0))
when _T_1346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1343, UInt<1>(0h1), "") : assert_56
node _T_1347 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1348 = asUInt(reset)
node _T_1349 = eq(_T_1348, UInt<1>(0h0))
when _T_1349 :
node _T_1350 = eq(_T_1347, UInt<1>(0h0))
when _T_1350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1347, UInt<1>(0h1), "") : assert_57
node _T_1351 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1351 :
node _T_1352 = asUInt(reset)
node _T_1353 = eq(_T_1352, UInt<1>(0h0))
when _T_1353 :
node _T_1354 = eq(source_ok_1, UInt<1>(0h0))
when _T_1354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1355 = asUInt(reset)
node _T_1356 = eq(_T_1355, UInt<1>(0h0))
when _T_1356 :
node _T_1357 = eq(sink_ok, UInt<1>(0h0))
when _T_1357 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1358 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1359 = asUInt(reset)
node _T_1360 = eq(_T_1359, UInt<1>(0h0))
when _T_1360 :
node _T_1361 = eq(_T_1358, UInt<1>(0h0))
when _T_1361 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1358, UInt<1>(0h1), "") : assert_60
node _T_1362 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1363 = asUInt(reset)
node _T_1364 = eq(_T_1363, UInt<1>(0h0))
when _T_1364 :
node _T_1365 = eq(_T_1362, UInt<1>(0h0))
when _T_1365 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1362, UInt<1>(0h1), "") : assert_61
node _T_1366 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1367 = asUInt(reset)
node _T_1368 = eq(_T_1367, UInt<1>(0h0))
when _T_1368 :
node _T_1369 = eq(_T_1366, UInt<1>(0h0))
when _T_1369 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1366, UInt<1>(0h1), "") : assert_62
node _T_1370 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1371 = asUInt(reset)
node _T_1372 = eq(_T_1371, UInt<1>(0h0))
when _T_1372 :
node _T_1373 = eq(_T_1370, UInt<1>(0h0))
when _T_1373 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1370, UInt<1>(0h1), "") : assert_63
node _T_1374 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1375 = or(UInt<1>(0h1), _T_1374)
node _T_1376 = asUInt(reset)
node _T_1377 = eq(_T_1376, UInt<1>(0h0))
when _T_1377 :
node _T_1378 = eq(_T_1375, UInt<1>(0h0))
when _T_1378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1375, UInt<1>(0h1), "") : assert_64
node _T_1379 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1379 :
node _T_1380 = asUInt(reset)
node _T_1381 = eq(_T_1380, UInt<1>(0h0))
when _T_1381 :
node _T_1382 = eq(source_ok_1, UInt<1>(0h0))
when _T_1382 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1383 = asUInt(reset)
node _T_1384 = eq(_T_1383, UInt<1>(0h0))
when _T_1384 :
node _T_1385 = eq(sink_ok, UInt<1>(0h0))
when _T_1385 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1386 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1387 = asUInt(reset)
node _T_1388 = eq(_T_1387, UInt<1>(0h0))
when _T_1388 :
node _T_1389 = eq(_T_1386, UInt<1>(0h0))
when _T_1389 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1386, UInt<1>(0h1), "") : assert_67
node _T_1390 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1391 = asUInt(reset)
node _T_1392 = eq(_T_1391, UInt<1>(0h0))
when _T_1392 :
node _T_1393 = eq(_T_1390, UInt<1>(0h0))
when _T_1393 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1390, UInt<1>(0h1), "") : assert_68
node _T_1394 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1395 = asUInt(reset)
node _T_1396 = eq(_T_1395, UInt<1>(0h0))
when _T_1396 :
node _T_1397 = eq(_T_1394, UInt<1>(0h0))
when _T_1397 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1394, UInt<1>(0h1), "") : assert_69
node _T_1398 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1399 = or(_T_1398, io.in.d.bits.corrupt)
node _T_1400 = asUInt(reset)
node _T_1401 = eq(_T_1400, UInt<1>(0h0))
when _T_1401 :
node _T_1402 = eq(_T_1399, UInt<1>(0h0))
when _T_1402 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1399, UInt<1>(0h1), "") : assert_70
node _T_1403 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1404 = or(UInt<1>(0h1), _T_1403)
node _T_1405 = asUInt(reset)
node _T_1406 = eq(_T_1405, UInt<1>(0h0))
when _T_1406 :
node _T_1407 = eq(_T_1404, UInt<1>(0h0))
when _T_1407 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1404, UInt<1>(0h1), "") : assert_71
node _T_1408 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1408 :
node _T_1409 = asUInt(reset)
node _T_1410 = eq(_T_1409, UInt<1>(0h0))
when _T_1410 :
node _T_1411 = eq(source_ok_1, UInt<1>(0h0))
when _T_1411 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1412 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1413 = asUInt(reset)
node _T_1414 = eq(_T_1413, UInt<1>(0h0))
when _T_1414 :
node _T_1415 = eq(_T_1412, UInt<1>(0h0))
when _T_1415 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1412, UInt<1>(0h1), "") : assert_73
node _T_1416 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1417 = asUInt(reset)
node _T_1418 = eq(_T_1417, UInt<1>(0h0))
when _T_1418 :
node _T_1419 = eq(_T_1416, UInt<1>(0h0))
when _T_1419 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1416, UInt<1>(0h1), "") : assert_74
node _T_1420 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1421 = or(UInt<1>(0h1), _T_1420)
node _T_1422 = asUInt(reset)
node _T_1423 = eq(_T_1422, UInt<1>(0h0))
when _T_1423 :
node _T_1424 = eq(_T_1421, UInt<1>(0h0))
when _T_1424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1421, UInt<1>(0h1), "") : assert_75
node _T_1425 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1425 :
node _T_1426 = asUInt(reset)
node _T_1427 = eq(_T_1426, UInt<1>(0h0))
when _T_1427 :
node _T_1428 = eq(source_ok_1, UInt<1>(0h0))
when _T_1428 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1429 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1430 = asUInt(reset)
node _T_1431 = eq(_T_1430, UInt<1>(0h0))
when _T_1431 :
node _T_1432 = eq(_T_1429, UInt<1>(0h0))
when _T_1432 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1429, UInt<1>(0h1), "") : assert_77
node _T_1433 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1434 = or(_T_1433, io.in.d.bits.corrupt)
node _T_1435 = asUInt(reset)
node _T_1436 = eq(_T_1435, UInt<1>(0h0))
when _T_1436 :
node _T_1437 = eq(_T_1434, UInt<1>(0h0))
when _T_1437 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1434, UInt<1>(0h1), "") : assert_78
node _T_1438 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1439 = or(UInt<1>(0h1), _T_1438)
node _T_1440 = asUInt(reset)
node _T_1441 = eq(_T_1440, UInt<1>(0h0))
when _T_1441 :
node _T_1442 = eq(_T_1439, UInt<1>(0h0))
when _T_1442 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1439, UInt<1>(0h1), "") : assert_79
node _T_1443 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1443 :
node _T_1444 = asUInt(reset)
node _T_1445 = eq(_T_1444, UInt<1>(0h0))
when _T_1445 :
node _T_1446 = eq(source_ok_1, UInt<1>(0h0))
when _T_1446 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1447 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1448 = asUInt(reset)
node _T_1449 = eq(_T_1448, UInt<1>(0h0))
when _T_1449 :
node _T_1450 = eq(_T_1447, UInt<1>(0h0))
when _T_1450 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1447, UInt<1>(0h1), "") : assert_81
node _T_1451 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1452 = asUInt(reset)
node _T_1453 = eq(_T_1452, UInt<1>(0h0))
when _T_1453 :
node _T_1454 = eq(_T_1451, UInt<1>(0h0))
when _T_1454 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1451, UInt<1>(0h1), "") : assert_82
node _T_1455 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1456 = or(UInt<1>(0h1), _T_1455)
node _T_1457 = asUInt(reset)
node _T_1458 = eq(_T_1457, UInt<1>(0h0))
when _T_1458 :
node _T_1459 = eq(_T_1456, UInt<1>(0h0))
when _T_1459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1456, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<4>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1460 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_1461 = asUInt(reset)
node _T_1462 = eq(_T_1461, UInt<1>(0h0))
when _T_1462 :
node _T_1463 = eq(_T_1460, UInt<1>(0h0))
when _T_1463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1460, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<4>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_1464 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_1465 = asUInt(reset)
node _T_1466 = eq(_T_1465, UInt<1>(0h0))
when _T_1466 :
node _T_1467 = eq(_T_1464, UInt<1>(0h0))
when _T_1467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1464, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_4.bits.sink, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1468 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1469 = asUInt(reset)
node _T_1470 = eq(_T_1469, UInt<1>(0h0))
when _T_1470 :
node _T_1471 = eq(_T_1468, UInt<1>(0h0))
when _T_1471 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1468, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1472 = eq(a_first, UInt<1>(0h0))
node _T_1473 = and(io.in.a.valid, _T_1472)
when _T_1473 :
node _T_1474 = eq(io.in.a.bits.opcode, opcode)
node _T_1475 = asUInt(reset)
node _T_1476 = eq(_T_1475, UInt<1>(0h0))
when _T_1476 :
node _T_1477 = eq(_T_1474, UInt<1>(0h0))
when _T_1477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1474, UInt<1>(0h1), "") : assert_87
node _T_1478 = eq(io.in.a.bits.param, param)
node _T_1479 = asUInt(reset)
node _T_1480 = eq(_T_1479, UInt<1>(0h0))
when _T_1480 :
node _T_1481 = eq(_T_1478, UInt<1>(0h0))
when _T_1481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1478, UInt<1>(0h1), "") : assert_88
node _T_1482 = eq(io.in.a.bits.size, size)
node _T_1483 = asUInt(reset)
node _T_1484 = eq(_T_1483, UInt<1>(0h0))
when _T_1484 :
node _T_1485 = eq(_T_1482, UInt<1>(0h0))
when _T_1485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1482, UInt<1>(0h1), "") : assert_89
node _T_1486 = eq(io.in.a.bits.source, source)
node _T_1487 = asUInt(reset)
node _T_1488 = eq(_T_1487, UInt<1>(0h0))
when _T_1488 :
node _T_1489 = eq(_T_1486, UInt<1>(0h0))
when _T_1489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1486, UInt<1>(0h1), "") : assert_90
node _T_1490 = eq(io.in.a.bits.address, address)
node _T_1491 = asUInt(reset)
node _T_1492 = eq(_T_1491, UInt<1>(0h0))
when _T_1492 :
node _T_1493 = eq(_T_1490, UInt<1>(0h0))
when _T_1493 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1490, UInt<1>(0h1), "") : assert_91
node _T_1494 = and(io.in.a.ready, io.in.a.valid)
node _T_1495 = and(_T_1494, a_first)
when _T_1495 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1496 = eq(d_first, UInt<1>(0h0))
node _T_1497 = and(io.in.d.valid, _T_1496)
when _T_1497 :
node _T_1498 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1499 = asUInt(reset)
node _T_1500 = eq(_T_1499, UInt<1>(0h0))
when _T_1500 :
node _T_1501 = eq(_T_1498, UInt<1>(0h0))
when _T_1501 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1498, UInt<1>(0h1), "") : assert_92
node _T_1502 = eq(io.in.d.bits.param, param_1)
node _T_1503 = asUInt(reset)
node _T_1504 = eq(_T_1503, UInt<1>(0h0))
when _T_1504 :
node _T_1505 = eq(_T_1502, UInt<1>(0h0))
when _T_1505 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1502, UInt<1>(0h1), "") : assert_93
node _T_1506 = eq(io.in.d.bits.size, size_1)
node _T_1507 = asUInt(reset)
node _T_1508 = eq(_T_1507, UInt<1>(0h0))
when _T_1508 :
node _T_1509 = eq(_T_1506, UInt<1>(0h0))
when _T_1509 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1506, UInt<1>(0h1), "") : assert_94
node _T_1510 = eq(io.in.d.bits.source, source_1)
node _T_1511 = asUInt(reset)
node _T_1512 = eq(_T_1511, UInt<1>(0h0))
when _T_1512 :
node _T_1513 = eq(_T_1510, UInt<1>(0h0))
when _T_1513 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1510, UInt<1>(0h1), "") : assert_95
node _T_1514 = eq(io.in.d.bits.sink, sink)
node _T_1515 = asUInt(reset)
node _T_1516 = eq(_T_1515, UInt<1>(0h0))
when _T_1516 :
node _T_1517 = eq(_T_1514, UInt<1>(0h0))
when _T_1517 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1514, UInt<1>(0h1), "") : assert_96
node _T_1518 = eq(io.in.d.bits.denied, denied)
node _T_1519 = asUInt(reset)
node _T_1520 = eq(_T_1519, UInt<1>(0h0))
when _T_1520 :
node _T_1521 = eq(_T_1518, UInt<1>(0h0))
when _T_1521 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1518, UInt<1>(0h1), "") : assert_97
node _T_1522 = and(io.in.d.ready, io.in.d.valid)
node _T_1523 = and(_T_1522, d_first)
when _T_1523 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<16>, clock, reset, UInt<16>(0h0)
regreset inflight_opcodes : UInt<64>, clock, reset, UInt<64>(0h0)
regreset inflight_sizes : UInt<128>, clock, reset, UInt<128>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<16>
connect a_set, UInt<16>(0h0)
wire a_set_wo_ready : UInt<16>
connect a_set_wo_ready, UInt<16>(0h0)
wire a_opcodes_set : UInt<64>
connect a_opcodes_set, UInt<64>(0h0)
wire a_sizes_set : UInt<128>
connect a_sizes_set, UInt<128>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1524 = and(io.in.a.valid, a_first_1)
node _T_1525 = and(_T_1524, UInt<1>(0h1))
when _T_1525 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1526 = and(io.in.a.ready, io.in.a.valid)
node _T_1527 = and(_T_1526, a_first_1)
node _T_1528 = and(_T_1527, UInt<1>(0h1))
when _T_1528 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1529 = dshr(inflight, io.in.a.bits.source)
node _T_1530 = bits(_T_1529, 0, 0)
node _T_1531 = eq(_T_1530, UInt<1>(0h0))
node _T_1532 = asUInt(reset)
node _T_1533 = eq(_T_1532, UInt<1>(0h0))
when _T_1533 :
node _T_1534 = eq(_T_1531, UInt<1>(0h0))
when _T_1534 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1531, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<16>
connect d_clr, UInt<16>(0h0)
wire d_clr_wo_ready : UInt<16>
connect d_clr_wo_ready, UInt<16>(0h0)
wire d_opcodes_clr : UInt<64>
connect d_opcodes_clr, UInt<64>(0h0)
wire d_sizes_clr : UInt<128>
connect d_sizes_clr, UInt<128>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1535 = and(io.in.d.valid, d_first_1)
node _T_1536 = and(_T_1535, UInt<1>(0h1))
node _T_1537 = eq(d_release_ack, UInt<1>(0h0))
node _T_1538 = and(_T_1536, _T_1537)
when _T_1538 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1539 = and(io.in.d.ready, io.in.d.valid)
node _T_1540 = and(_T_1539, d_first_1)
node _T_1541 = and(_T_1540, UInt<1>(0h1))
node _T_1542 = eq(d_release_ack, UInt<1>(0h0))
node _T_1543 = and(_T_1541, _T_1542)
when _T_1543 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1544 = and(io.in.d.valid, d_first_1)
node _T_1545 = and(_T_1544, UInt<1>(0h1))
node _T_1546 = eq(d_release_ack, UInt<1>(0h0))
node _T_1547 = and(_T_1545, _T_1546)
when _T_1547 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1548 = dshr(inflight, io.in.d.bits.source)
node _T_1549 = bits(_T_1548, 0, 0)
node _T_1550 = or(_T_1549, same_cycle_resp)
node _T_1551 = asUInt(reset)
node _T_1552 = eq(_T_1551, UInt<1>(0h0))
when _T_1552 :
node _T_1553 = eq(_T_1550, UInt<1>(0h0))
when _T_1553 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1550, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1554 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1555 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1556 = or(_T_1554, _T_1555)
node _T_1557 = asUInt(reset)
node _T_1558 = eq(_T_1557, UInt<1>(0h0))
when _T_1558 :
node _T_1559 = eq(_T_1556, UInt<1>(0h0))
when _T_1559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1556, UInt<1>(0h1), "") : assert_100
node _T_1560 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1561 = asUInt(reset)
node _T_1562 = eq(_T_1561, UInt<1>(0h0))
when _T_1562 :
node _T_1563 = eq(_T_1560, UInt<1>(0h0))
when _T_1563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1560, UInt<1>(0h1), "") : assert_101
else :
node _T_1564 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1565 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1566 = or(_T_1564, _T_1565)
node _T_1567 = asUInt(reset)
node _T_1568 = eq(_T_1567, UInt<1>(0h0))
when _T_1568 :
node _T_1569 = eq(_T_1566, UInt<1>(0h0))
when _T_1569 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1566, UInt<1>(0h1), "") : assert_102
node _T_1570 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1571 = asUInt(reset)
node _T_1572 = eq(_T_1571, UInt<1>(0h0))
when _T_1572 :
node _T_1573 = eq(_T_1570, UInt<1>(0h0))
when _T_1573 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1570, UInt<1>(0h1), "") : assert_103
node _T_1574 = and(io.in.d.valid, d_first_1)
node _T_1575 = and(_T_1574, a_first_1)
node _T_1576 = and(_T_1575, io.in.a.valid)
node _T_1577 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1578 = and(_T_1576, _T_1577)
node _T_1579 = eq(d_release_ack, UInt<1>(0h0))
node _T_1580 = and(_T_1578, _T_1579)
when _T_1580 :
node _T_1581 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1582 = or(_T_1581, io.in.a.ready)
node _T_1583 = asUInt(reset)
node _T_1584 = eq(_T_1583, UInt<1>(0h0))
when _T_1584 :
node _T_1585 = eq(_T_1582, UInt<1>(0h0))
when _T_1585 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1582, UInt<1>(0h1), "") : assert_104
node _T_1586 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1587 = orr(a_set_wo_ready)
node _T_1588 = eq(_T_1587, UInt<1>(0h0))
node _T_1589 = or(_T_1586, _T_1588)
node _T_1590 = asUInt(reset)
node _T_1591 = eq(_T_1590, UInt<1>(0h0))
when _T_1591 :
node _T_1592 = eq(_T_1589, UInt<1>(0h0))
when _T_1592 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1589, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_46
node _T_1593 = orr(inflight)
node _T_1594 = eq(_T_1593, UInt<1>(0h0))
node _T_1595 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1596 = or(_T_1594, _T_1595)
node _T_1597 = lt(watchdog, plusarg_reader.out)
node _T_1598 = or(_T_1596, _T_1597)
node _T_1599 = asUInt(reset)
node _T_1600 = eq(_T_1599, UInt<1>(0h0))
when _T_1600 :
node _T_1601 = eq(_T_1598, UInt<1>(0h0))
when _T_1601 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1598, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1602 = and(io.in.a.ready, io.in.a.valid)
node _T_1603 = and(io.in.d.ready, io.in.d.valid)
node _T_1604 = or(_T_1602, _T_1603)
when _T_1604 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<16>, clock, reset, UInt<16>(0h0)
regreset inflight_opcodes_1 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset inflight_sizes_1 : UInt<128>, clock, reset, UInt<128>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<4>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<16>
connect c_set, UInt<16>(0h0)
wire c_set_wo_ready : UInt<16>
connect c_set_wo_ready, UInt<16>(0h0)
wire c_opcodes_set : UInt<64>
connect c_opcodes_set, UInt<64>(0h0)
wire c_sizes_set : UInt<128>
connect c_sizes_set, UInt<128>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<4>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1605 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<4>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1606 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1607 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1608 = and(_T_1606, _T_1607)
node _T_1609 = and(_T_1605, _T_1608)
when _T_1609 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<4>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1610 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1611 = and(_T_1610, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<4>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1612 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1613 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1614 = and(_T_1612, _T_1613)
node _T_1615 = and(_T_1611, _T_1614)
when _T_1615 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<4>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1616 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1617 = bits(_T_1616, 0, 0)
node _T_1618 = eq(_T_1617, UInt<1>(0h0))
node _T_1619 = asUInt(reset)
node _T_1620 = eq(_T_1619, UInt<1>(0h0))
when _T_1620 :
node _T_1621 = eq(_T_1618, UInt<1>(0h0))
when _T_1621 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1618, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<16>
connect d_clr_1, UInt<16>(0h0)
wire d_clr_wo_ready_1 : UInt<16>
connect d_clr_wo_ready_1, UInt<16>(0h0)
wire d_opcodes_clr_1 : UInt<64>
connect d_opcodes_clr_1, UInt<64>(0h0)
wire d_sizes_clr_1 : UInt<128>
connect d_sizes_clr_1, UInt<128>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1622 = and(io.in.d.valid, d_first_2)
node _T_1623 = and(_T_1622, UInt<1>(0h1))
node _T_1624 = and(_T_1623, d_release_ack_1)
when _T_1624 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1625 = and(io.in.d.ready, io.in.d.valid)
node _T_1626 = and(_T_1625, d_first_2)
node _T_1627 = and(_T_1626, UInt<1>(0h1))
node _T_1628 = and(_T_1627, d_release_ack_1)
when _T_1628 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1629 = and(io.in.d.valid, d_first_2)
node _T_1630 = and(_T_1629, UInt<1>(0h1))
node _T_1631 = and(_T_1630, d_release_ack_1)
when _T_1631 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1632 = dshr(inflight_1, io.in.d.bits.source)
node _T_1633 = bits(_T_1632, 0, 0)
node _T_1634 = or(_T_1633, same_cycle_resp_1)
node _T_1635 = asUInt(reset)
node _T_1636 = eq(_T_1635, UInt<1>(0h0))
when _T_1636 :
node _T_1637 = eq(_T_1634, UInt<1>(0h0))
when _T_1637 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1634, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<4>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1638 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1639 = asUInt(reset)
node _T_1640 = eq(_T_1639, UInt<1>(0h0))
when _T_1640 :
node _T_1641 = eq(_T_1638, UInt<1>(0h0))
when _T_1641 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1638, UInt<1>(0h1), "") : assert_109
else :
node _T_1642 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1643 = asUInt(reset)
node _T_1644 = eq(_T_1643, UInt<1>(0h0))
when _T_1644 :
node _T_1645 = eq(_T_1642, UInt<1>(0h0))
when _T_1645 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1642, UInt<1>(0h1), "") : assert_110
node _T_1646 = and(io.in.d.valid, d_first_2)
node _T_1647 = and(_T_1646, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<4>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1648 = and(_T_1647, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<4>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1649 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1650 = and(_T_1648, _T_1649)
node _T_1651 = and(_T_1650, d_release_ack_1)
node _T_1652 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1653 = and(_T_1651, _T_1652)
when _T_1653 :
node _T_1654 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<4>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1655 = or(_T_1654, _WIRE_23.ready)
node _T_1656 = asUInt(reset)
node _T_1657 = eq(_T_1656, UInt<1>(0h0))
when _T_1657 :
node _T_1658 = eq(_T_1655, UInt<1>(0h0))
when _T_1658 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1655, UInt<1>(0h1), "") : assert_111
node _T_1659 = orr(c_set_wo_ready)
when _T_1659 :
node _T_1660 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1661 = asUInt(reset)
node _T_1662 = eq(_T_1661, UInt<1>(0h0))
when _T_1662 :
node _T_1663 = eq(_T_1660, UInt<1>(0h0))
when _T_1663 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1660, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_47
node _T_1664 = orr(inflight_1)
node _T_1665 = eq(_T_1664, UInt<1>(0h0))
node _T_1666 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1667 = or(_T_1665, _T_1666)
node _T_1668 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1669 = or(_T_1667, _T_1668)
node _T_1670 = asUInt(reset)
node _T_1671 = eq(_T_1670, UInt<1>(0h0))
when _T_1671 :
node _T_1672 = eq(_T_1669, UInt<1>(0h0))
when _T_1672 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1669, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<4>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1673 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1674 = and(io.in.d.ready, io.in.d.valid)
node _T_1675 = or(_T_1673, _T_1674)
when _T_1675 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_23( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_14 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_16 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_20 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_22 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_28 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_30 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_34 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_36 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_40 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_42 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_48 = 1'h1; // @[Parameters.scala:57:20]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] c_opcodes_set = 64'h0; // @[Monitor.scala:740:34]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [131:0] _c_sizes_set_T_1 = 132'h0; // @[Monitor.scala:768:52]
wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79]
wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77]
wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35]
wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35]
wire [127:0] c_sizes_set = 128'h0; // @[Monitor.scala:741:34]
wire [15:0] c_set = 16'h0; // @[Monitor.scala:738:34]
wire [15:0] c_set_wo_ready = 16'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] _source_ok_T = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_T_6 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_T_12 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_T_18 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_1 = _source_ok_T == 2'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_5 = _source_ok_T_3; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_7 = _source_ok_T_6 == 2'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_9 = _source_ok_T_7; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_11 = _source_ok_T_9; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_13 = _source_ok_T_12 == 2'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_15 = _source_ok_T_13; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_17 = _source_ok_T_15; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_17; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_19 = &_source_ok_T_18; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_21 = _source_ok_T_19; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_23 = _source_ok_T_21; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_23; // @[Parameters.scala:1138:31]
wire _source_ok_T_24 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_25 = _source_ok_T_24 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_25 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] _source_ok_T_26 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_T_32 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_T_38 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_T_44 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_27 = _source_ok_T_26 == 2'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_29 = _source_ok_T_27; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_31 = _source_ok_T_29; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_0 = _source_ok_T_31; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_33 = _source_ok_T_32 == 2'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_35 = _source_ok_T_33; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_37 = _source_ok_T_35; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_37; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_39 = _source_ok_T_38 == 2'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_41 = _source_ok_T_39; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_43 = _source_ok_T_41; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_43; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_45 = &_source_ok_T_44; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_49 = _source_ok_T_47; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_49; // @[Parameters.scala:1138:31]
wire _source_ok_T_50 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_51 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1602 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1602; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1602; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [3:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1675 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1675; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1675; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1675; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [3:0] source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [15:0] inflight; // @[Monitor.scala:614:27]
reg [63:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [127:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [15:0] a_set; // @[Monitor.scala:626:34]
wire [15:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [63:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [127:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [63:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [63:0] _a_opcode_lookup_T_6 = {60'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [63:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[63:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [6:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [127:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [127:0] _a_size_lookup_T_6 = {120'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [127:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[127:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [15:0] _GEN_3 = {12'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35]
wire [15:0] _GEN_4 = 16'h1 << _GEN_3; // @[OneHot.scala:58:35]
wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35]
wire [15:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 16'h0; // @[OneHot.scala:58:35]
wire _T_1528 = _T_1602 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1528 ? _a_set_T : 16'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1528 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1528 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [6:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1528 ? _a_opcodes_set_T_1[63:0] : 64'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [6:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [131:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1528 ? _a_sizes_set_T_1[127:0] : 128'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [15:0] d_clr; // @[Monitor.scala:664:34]
wire [15:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [63:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [127:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46]
wire _T_1574 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [15:0] _GEN_6 = {12'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [15:0] _GEN_7 = 16'h1 << _GEN_6; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1574 & ~d_release_ack ? _d_clr_wo_ready_T : 16'h0; // @[OneHot.scala:58:35]
wire _T_1543 = _T_1675 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1543 ? _d_clr_T : 16'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1543 ? _d_opcodes_clr_T_5[63:0] : 64'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [142:0] _d_sizes_clr_T_5 = 143'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1543 ? _d_sizes_clr_T_5[127:0] : 128'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [15:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [15:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [15:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [63:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [63:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [63:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [127:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [127:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [127:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [15:0] inflight_1; // @[Monitor.scala:726:35]
wire [15:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [63:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [63:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [127:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [127:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [63:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [63:0] _c_opcode_lookup_T_6 = {60'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [63:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[63:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [127:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [127:0] _c_size_lookup_T_6 = {120'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [127:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[127:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [15:0] d_clr_1; // @[Monitor.scala:774:34]
wire [15:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [63:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [127:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1646 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1646 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 16'h0; // @[OneHot.scala:58:35]
wire _T_1628 = _T_1675 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1628 ? _d_clr_T_1 : 16'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1628 ? _d_opcodes_clr_T_11[63:0] : 64'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [142:0] _d_sizes_clr_T_11 = 143'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1628 ? _d_sizes_clr_T_11[127:0] : 128'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113]
wire [15:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [15:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [63:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [63:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [127:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [127:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module DivUnit_1 :
input clock : Clock
input reset : Reset
output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, pred_data : UInt<1>, kill : UInt<1>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, predicated : UInt<1>, data : UInt<64>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}, addr : UInt<40>, mxcpt : { valid : UInt<1>, bits : UInt<25>}, sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}}}, flip brupdate : { b1 : { resolve_mask : UInt<8>, mispredict_mask : UInt<8>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, bypass : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}[0]}
connect io.resp.valid, UInt<1>(0h0)
invalidate io.resp.bits.sfence.bits.hg
invalidate io.resp.bits.sfence.bits.hv
invalidate io.resp.bits.sfence.bits.asid
invalidate io.resp.bits.sfence.bits.addr
invalidate io.resp.bits.sfence.bits.rs2
invalidate io.resp.bits.sfence.bits.rs1
invalidate io.resp.bits.sfence.valid
invalidate io.resp.bits.mxcpt.bits
invalidate io.resp.bits.mxcpt.valid
invalidate io.resp.bits.addr
invalidate io.resp.bits.fflags.bits.flags
invalidate io.resp.bits.fflags.bits.uop.debug_tsrc
invalidate io.resp.bits.fflags.bits.uop.debug_fsrc
invalidate io.resp.bits.fflags.bits.uop.bp_xcpt_if
invalidate io.resp.bits.fflags.bits.uop.bp_debug_if
invalidate io.resp.bits.fflags.bits.uop.xcpt_ma_if
invalidate io.resp.bits.fflags.bits.uop.xcpt_ae_if
invalidate io.resp.bits.fflags.bits.uop.xcpt_pf_if
invalidate io.resp.bits.fflags.bits.uop.fp_single
invalidate io.resp.bits.fflags.bits.uop.fp_val
invalidate io.resp.bits.fflags.bits.uop.frs3_en
invalidate io.resp.bits.fflags.bits.uop.lrs2_rtype
invalidate io.resp.bits.fflags.bits.uop.lrs1_rtype
invalidate io.resp.bits.fflags.bits.uop.dst_rtype
invalidate io.resp.bits.fflags.bits.uop.ldst_val
invalidate io.resp.bits.fflags.bits.uop.lrs3
invalidate io.resp.bits.fflags.bits.uop.lrs2
invalidate io.resp.bits.fflags.bits.uop.lrs1
invalidate io.resp.bits.fflags.bits.uop.ldst
invalidate io.resp.bits.fflags.bits.uop.ldst_is_rs1
invalidate io.resp.bits.fflags.bits.uop.flush_on_commit
invalidate io.resp.bits.fflags.bits.uop.is_unique
invalidate io.resp.bits.fflags.bits.uop.is_sys_pc2epc
invalidate io.resp.bits.fflags.bits.uop.uses_stq
invalidate io.resp.bits.fflags.bits.uop.uses_ldq
invalidate io.resp.bits.fflags.bits.uop.is_amo
invalidate io.resp.bits.fflags.bits.uop.is_fencei
invalidate io.resp.bits.fflags.bits.uop.is_fence
invalidate io.resp.bits.fflags.bits.uop.mem_signed
invalidate io.resp.bits.fflags.bits.uop.mem_size
invalidate io.resp.bits.fflags.bits.uop.mem_cmd
invalidate io.resp.bits.fflags.bits.uop.bypassable
invalidate io.resp.bits.fflags.bits.uop.exc_cause
invalidate io.resp.bits.fflags.bits.uop.exception
invalidate io.resp.bits.fflags.bits.uop.stale_pdst
invalidate io.resp.bits.fflags.bits.uop.ppred_busy
invalidate io.resp.bits.fflags.bits.uop.prs3_busy
invalidate io.resp.bits.fflags.bits.uop.prs2_busy
invalidate io.resp.bits.fflags.bits.uop.prs1_busy
invalidate io.resp.bits.fflags.bits.uop.ppred
invalidate io.resp.bits.fflags.bits.uop.prs3
invalidate io.resp.bits.fflags.bits.uop.prs2
invalidate io.resp.bits.fflags.bits.uop.prs1
invalidate io.resp.bits.fflags.bits.uop.pdst
invalidate io.resp.bits.fflags.bits.uop.rxq_idx
invalidate io.resp.bits.fflags.bits.uop.stq_idx
invalidate io.resp.bits.fflags.bits.uop.ldq_idx
invalidate io.resp.bits.fflags.bits.uop.rob_idx
invalidate io.resp.bits.fflags.bits.uop.csr_addr
invalidate io.resp.bits.fflags.bits.uop.imm_packed
invalidate io.resp.bits.fflags.bits.uop.taken
invalidate io.resp.bits.fflags.bits.uop.pc_lob
invalidate io.resp.bits.fflags.bits.uop.edge_inst
invalidate io.resp.bits.fflags.bits.uop.ftq_idx
invalidate io.resp.bits.fflags.bits.uop.br_tag
invalidate io.resp.bits.fflags.bits.uop.br_mask
invalidate io.resp.bits.fflags.bits.uop.is_sfb
invalidate io.resp.bits.fflags.bits.uop.is_jal
invalidate io.resp.bits.fflags.bits.uop.is_jalr
invalidate io.resp.bits.fflags.bits.uop.is_br
invalidate io.resp.bits.fflags.bits.uop.iw_p2_poisoned
invalidate io.resp.bits.fflags.bits.uop.iw_p1_poisoned
invalidate io.resp.bits.fflags.bits.uop.iw_state
invalidate io.resp.bits.fflags.bits.uop.ctrl.is_std
invalidate io.resp.bits.fflags.bits.uop.ctrl.is_sta
invalidate io.resp.bits.fflags.bits.uop.ctrl.is_load
invalidate io.resp.bits.fflags.bits.uop.ctrl.csr_cmd
invalidate io.resp.bits.fflags.bits.uop.ctrl.fcn_dw
invalidate io.resp.bits.fflags.bits.uop.ctrl.op_fcn
invalidate io.resp.bits.fflags.bits.uop.ctrl.imm_sel
invalidate io.resp.bits.fflags.bits.uop.ctrl.op2_sel
invalidate io.resp.bits.fflags.bits.uop.ctrl.op1_sel
invalidate io.resp.bits.fflags.bits.uop.ctrl.br_type
invalidate io.resp.bits.fflags.bits.uop.fu_code
invalidate io.resp.bits.fflags.bits.uop.iq_type
invalidate io.resp.bits.fflags.bits.uop.debug_pc
invalidate io.resp.bits.fflags.bits.uop.is_rvc
invalidate io.resp.bits.fflags.bits.uop.debug_inst
invalidate io.resp.bits.fflags.bits.uop.inst
invalidate io.resp.bits.fflags.bits.uop.uopc
invalidate io.resp.bits.fflags.valid
invalidate io.resp.bits.data
invalidate io.resp.bits.predicated
invalidate io.resp.bits.uop.debug_tsrc
invalidate io.resp.bits.uop.debug_fsrc
invalidate io.resp.bits.uop.bp_xcpt_if
invalidate io.resp.bits.uop.bp_debug_if
invalidate io.resp.bits.uop.xcpt_ma_if
invalidate io.resp.bits.uop.xcpt_ae_if
invalidate io.resp.bits.uop.xcpt_pf_if
invalidate io.resp.bits.uop.fp_single
invalidate io.resp.bits.uop.fp_val
invalidate io.resp.bits.uop.frs3_en
invalidate io.resp.bits.uop.lrs2_rtype
invalidate io.resp.bits.uop.lrs1_rtype
invalidate io.resp.bits.uop.dst_rtype
invalidate io.resp.bits.uop.ldst_val
invalidate io.resp.bits.uop.lrs3
invalidate io.resp.bits.uop.lrs2
invalidate io.resp.bits.uop.lrs1
invalidate io.resp.bits.uop.ldst
invalidate io.resp.bits.uop.ldst_is_rs1
invalidate io.resp.bits.uop.flush_on_commit
invalidate io.resp.bits.uop.is_unique
invalidate io.resp.bits.uop.is_sys_pc2epc
invalidate io.resp.bits.uop.uses_stq
invalidate io.resp.bits.uop.uses_ldq
invalidate io.resp.bits.uop.is_amo
invalidate io.resp.bits.uop.is_fencei
invalidate io.resp.bits.uop.is_fence
invalidate io.resp.bits.uop.mem_signed
invalidate io.resp.bits.uop.mem_size
invalidate io.resp.bits.uop.mem_cmd
invalidate io.resp.bits.uop.bypassable
invalidate io.resp.bits.uop.exc_cause
invalidate io.resp.bits.uop.exception
invalidate io.resp.bits.uop.stale_pdst
invalidate io.resp.bits.uop.ppred_busy
invalidate io.resp.bits.uop.prs3_busy
invalidate io.resp.bits.uop.prs2_busy
invalidate io.resp.bits.uop.prs1_busy
invalidate io.resp.bits.uop.ppred
invalidate io.resp.bits.uop.prs3
invalidate io.resp.bits.uop.prs2
invalidate io.resp.bits.uop.prs1
invalidate io.resp.bits.uop.pdst
invalidate io.resp.bits.uop.rxq_idx
invalidate io.resp.bits.uop.stq_idx
invalidate io.resp.bits.uop.ldq_idx
invalidate io.resp.bits.uop.rob_idx
invalidate io.resp.bits.uop.csr_addr
invalidate io.resp.bits.uop.imm_packed
invalidate io.resp.bits.uop.taken
invalidate io.resp.bits.uop.pc_lob
invalidate io.resp.bits.uop.edge_inst
invalidate io.resp.bits.uop.ftq_idx
invalidate io.resp.bits.uop.br_tag
invalidate io.resp.bits.uop.br_mask
invalidate io.resp.bits.uop.is_sfb
invalidate io.resp.bits.uop.is_jal
invalidate io.resp.bits.uop.is_jalr
invalidate io.resp.bits.uop.is_br
invalidate io.resp.bits.uop.iw_p2_poisoned
invalidate io.resp.bits.uop.iw_p1_poisoned
invalidate io.resp.bits.uop.iw_state
invalidate io.resp.bits.uop.ctrl.is_std
invalidate io.resp.bits.uop.ctrl.is_sta
invalidate io.resp.bits.uop.ctrl.is_load
invalidate io.resp.bits.uop.ctrl.csr_cmd
invalidate io.resp.bits.uop.ctrl.fcn_dw
invalidate io.resp.bits.uop.ctrl.op_fcn
invalidate io.resp.bits.uop.ctrl.imm_sel
invalidate io.resp.bits.uop.ctrl.op2_sel
invalidate io.resp.bits.uop.ctrl.op1_sel
invalidate io.resp.bits.uop.ctrl.br_type
invalidate io.resp.bits.uop.fu_code
invalidate io.resp.bits.uop.iq_type
invalidate io.resp.bits.uop.debug_pc
invalidate io.resp.bits.uop.is_rvc
invalidate io.resp.bits.uop.debug_inst
invalidate io.resp.bits.uop.inst
invalidate io.resp.bits.uop.uopc
reg r_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock
wire do_kill : UInt<1>
connect do_kill, io.req.bits.kill
node _T = and(io.req.ready, io.req.valid)
when _T :
node _do_kill_T = and(io.brupdate.b1.mispredict_mask, io.req.bits.uop.br_mask)
node _do_kill_T_1 = neq(_do_kill_T, UInt<1>(0h0))
node _do_kill_T_2 = or(_do_kill_T_1, io.req.bits.kill)
connect do_kill, _do_kill_T_2
connect r_uop, io.req.bits.uop
node _r_uop_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _r_uop_br_mask_T_1 = and(io.req.bits.uop.br_mask, _r_uop_br_mask_T)
connect r_uop.br_mask, _r_uop_br_mask_T_1
else :
node _do_kill_T_3 = and(io.brupdate.b1.mispredict_mask, r_uop.br_mask)
node _do_kill_T_4 = neq(_do_kill_T_3, UInt<1>(0h0))
node _do_kill_T_5 = or(_do_kill_T_4, io.req.bits.kill)
connect do_kill, _do_kill_T_5
node _r_uop_br_mask_T_2 = not(io.brupdate.b1.resolve_mask)
node _r_uop_br_mask_T_3 = and(r_uop.br_mask, _r_uop_br_mask_T_2)
connect r_uop.br_mask, _r_uop_br_mask_T_3
connect io.resp.bits.uop, r_uop
inst div of MulDiv_1
connect div.clock, clock
connect div.reset, reset
node _div_io_req_valid_T = eq(do_kill, UInt<1>(0h0))
node _div_io_req_valid_T_1 = and(io.req.valid, _div_io_req_valid_T)
connect div.io.req.valid, _div_io_req_valid_T_1
connect div.io.req.bits.dw, io.req.bits.uop.ctrl.fcn_dw
connect div.io.req.bits.fn, io.req.bits.uop.ctrl.op_fcn
connect div.io.req.bits.in1, io.req.bits.rs1_data
connect div.io.req.bits.in2, io.req.bits.rs2_data
invalidate div.io.req.bits.tag
connect io.req.ready, div.io.req.ready
connect div.io.kill, do_kill
node _io_resp_valid_T = eq(do_kill, UInt<1>(0h0))
node _io_resp_valid_T_1 = and(div.io.resp.valid, _io_resp_valid_T)
connect io.resp.valid, _io_resp_valid_T_1
connect div.io.resp.ready, io.resp.ready
connect io.resp.bits.data, div.io.resp.bits.data | module DivUnit_1( // @[functional-unit.scala:676:7]
input clock, // @[functional-unit.scala:676:7]
input reset, // @[functional-unit.scala:676:7]
output io_req_ready, // @[functional-unit.scala:168:14]
input io_req_valid, // @[functional-unit.scala:168:14]
input [6:0] io_req_bits_uop_uopc, // @[functional-unit.scala:168:14]
input [31:0] io_req_bits_uop_inst, // @[functional-unit.scala:168:14]
input [31:0] io_req_bits_uop_debug_inst, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_rvc, // @[functional-unit.scala:168:14]
input [39:0] io_req_bits_uop_debug_pc, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_iq_type, // @[functional-unit.scala:168:14]
input [9:0] io_req_bits_uop_fu_code, // @[functional-unit.scala:168:14]
input [3:0] io_req_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14]
input [4:0] io_req_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_iw_state, // @[functional-unit.scala:168:14]
input io_req_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14]
input io_req_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_br, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_jalr, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_jal, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_sfb, // @[functional-unit.scala:168:14]
input [7:0] io_req_bits_uop_br_mask, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_br_tag, // @[functional-unit.scala:168:14]
input [3:0] io_req_bits_uop_ftq_idx, // @[functional-unit.scala:168:14]
input io_req_bits_uop_edge_inst, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_pc_lob, // @[functional-unit.scala:168:14]
input io_req_bits_uop_taken, // @[functional-unit.scala:168:14]
input [19:0] io_req_bits_uop_imm_packed, // @[functional-unit.scala:168:14]
input [11:0] io_req_bits_uop_csr_addr, // @[functional-unit.scala:168:14]
input [4:0] io_req_bits_uop_rob_idx, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_ldq_idx, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_stq_idx, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_rxq_idx, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_pdst, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_prs1, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_prs2, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_prs3, // @[functional-unit.scala:168:14]
input [3:0] io_req_bits_uop_ppred, // @[functional-unit.scala:168:14]
input io_req_bits_uop_prs1_busy, // @[functional-unit.scala:168:14]
input io_req_bits_uop_prs2_busy, // @[functional-unit.scala:168:14]
input io_req_bits_uop_prs3_busy, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ppred_busy, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_stale_pdst, // @[functional-unit.scala:168:14]
input io_req_bits_uop_exception, // @[functional-unit.scala:168:14]
input [63:0] io_req_bits_uop_exc_cause, // @[functional-unit.scala:168:14]
input io_req_bits_uop_bypassable, // @[functional-unit.scala:168:14]
input [4:0] io_req_bits_uop_mem_cmd, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_mem_size, // @[functional-unit.scala:168:14]
input io_req_bits_uop_mem_signed, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_fence, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_fencei, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_amo, // @[functional-unit.scala:168:14]
input io_req_bits_uop_uses_ldq, // @[functional-unit.scala:168:14]
input io_req_bits_uop_uses_stq, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_unique, // @[functional-unit.scala:168:14]
input io_req_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_ldst, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_lrs1, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_lrs2, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_lrs3, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ldst_val, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_dst_rtype, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14]
input io_req_bits_uop_frs3_en, // @[functional-unit.scala:168:14]
input io_req_bits_uop_fp_val, // @[functional-unit.scala:168:14]
input io_req_bits_uop_fp_single, // @[functional-unit.scala:168:14]
input io_req_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14]
input io_req_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14]
input io_req_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14]
input io_req_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14]
input io_req_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14]
input [63:0] io_req_bits_rs1_data, // @[functional-unit.scala:168:14]
input [63:0] io_req_bits_rs2_data, // @[functional-unit.scala:168:14]
input io_req_bits_kill, // @[functional-unit.scala:168:14]
input io_resp_ready, // @[functional-unit.scala:168:14]
output io_resp_valid, // @[functional-unit.scala:168:14]
output [6:0] io_resp_bits_uop_uopc, // @[functional-unit.scala:168:14]
output [31:0] io_resp_bits_uop_inst, // @[functional-unit.scala:168:14]
output [31:0] io_resp_bits_uop_debug_inst, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_rvc, // @[functional-unit.scala:168:14]
output [39:0] io_resp_bits_uop_debug_pc, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_iq_type, // @[functional-unit.scala:168:14]
output [9:0] io_resp_bits_uop_fu_code, // @[functional-unit.scala:168:14]
output [3:0] io_resp_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_iw_state, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_br, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_jalr, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_jal, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_sfb, // @[functional-unit.scala:168:14]
output [7:0] io_resp_bits_uop_br_mask, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_br_tag, // @[functional-unit.scala:168:14]
output [3:0] io_resp_bits_uop_ftq_idx, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_edge_inst, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_pc_lob, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_taken, // @[functional-unit.scala:168:14]
output [19:0] io_resp_bits_uop_imm_packed, // @[functional-unit.scala:168:14]
output [11:0] io_resp_bits_uop_csr_addr, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_uop_rob_idx, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_ldq_idx, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_stq_idx, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_rxq_idx, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_pdst, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_prs1, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_prs2, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_prs3, // @[functional-unit.scala:168:14]
output [3:0] io_resp_bits_uop_ppred, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_prs1_busy, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_prs2_busy, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_prs3_busy, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ppred_busy, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_stale_pdst, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_exception, // @[functional-unit.scala:168:14]
output [63:0] io_resp_bits_uop_exc_cause, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_bypassable, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_uop_mem_cmd, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_mem_size, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_mem_signed, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_fence, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_fencei, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_amo, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_uses_ldq, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_uses_stq, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_unique, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_ldst, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_lrs1, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_lrs2, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_lrs3, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ldst_val, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_dst_rtype, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_frs3_en, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_fp_val, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_fp_single, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14]
output [63:0] io_resp_bits_data, // @[functional-unit.scala:168:14]
input [7:0] io_brupdate_b1_resolve_mask, // @[functional-unit.scala:168:14]
input [7:0] io_brupdate_b1_mispredict_mask, // @[functional-unit.scala:168:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[functional-unit.scala:168:14]
input [31:0] io_brupdate_b2_uop_inst, // @[functional-unit.scala:168:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_rvc, // @[functional-unit.scala:168:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[functional-unit.scala:168:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[functional-unit.scala:168:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_br, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_jalr, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_jal, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_sfb, // @[functional-unit.scala:168:14]
input [7:0] io_brupdate_b2_uop_br_mask, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_br_tag, // @[functional-unit.scala:168:14]
input [3:0] io_brupdate_b2_uop_ftq_idx, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_edge_inst, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_taken, // @[functional-unit.scala:168:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[functional-unit.scala:168:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[functional-unit.scala:168:14]
input [4:0] io_brupdate_b2_uop_rob_idx, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_ldq_idx, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_stq_idx, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_pdst, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_prs1, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_prs2, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_prs3, // @[functional-unit.scala:168:14]
input [3:0] io_brupdate_b2_uop_ppred, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_prs1_busy, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_prs2_busy, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_prs3_busy, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ppred_busy, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_stale_pdst, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_exception, // @[functional-unit.scala:168:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_bypassable, // @[functional-unit.scala:168:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_mem_signed, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_fence, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_fencei, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_amo, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_uses_ldq, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_uses_stq, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_unique, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_flush_on_commit, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ldst_val, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_frs3_en, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_fp_val, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_fp_single, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_bp_debug_if, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[functional-unit.scala:168:14]
input io_brupdate_b2_valid, // @[functional-unit.scala:168:14]
input io_brupdate_b2_mispredict, // @[functional-unit.scala:168:14]
input io_brupdate_b2_taken, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_cfi_type, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_pc_sel, // @[functional-unit.scala:168:14]
input [39:0] io_brupdate_b2_jalr_target, // @[functional-unit.scala:168:14]
input [20:0] io_brupdate_b2_target_offset // @[functional-unit.scala:168:14]
);
wire _div_io_resp_valid; // @[functional-unit.scala:682:19]
wire io_req_valid_0 = io_req_valid; // @[functional-unit.scala:676:7]
wire [6:0] io_req_bits_uop_uopc_0 = io_req_bits_uop_uopc; // @[functional-unit.scala:676:7]
wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[functional-unit.scala:676:7]
wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[functional-unit.scala:676:7]
wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[functional-unit.scala:676:7]
wire [2:0] io_req_bits_uop_iq_type_0 = io_req_bits_uop_iq_type; // @[functional-unit.scala:676:7]
wire [9:0] io_req_bits_uop_fu_code_0 = io_req_bits_uop_fu_code; // @[functional-unit.scala:676:7]
wire [3:0] io_req_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type; // @[functional-unit.scala:676:7]
wire [1:0] io_req_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel; // @[functional-unit.scala:676:7]
wire [2:0] io_req_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel; // @[functional-unit.scala:676:7]
wire [2:0] io_req_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel; // @[functional-unit.scala:676:7]
wire [4:0] io_req_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw; // @[functional-unit.scala:676:7]
wire [2:0] io_req_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std; // @[functional-unit.scala:676:7]
wire [1:0] io_req_bits_uop_iw_state_0 = io_req_bits_uop_iw_state; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_is_br_0 = io_req_bits_uop_is_br; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_is_jal_0 = io_req_bits_uop_is_jal; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[functional-unit.scala:676:7]
wire [7:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[functional-unit.scala:676:7]
wire [2:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[functional-unit.scala:676:7]
wire [3:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[functional-unit.scala:676:7]
wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[functional-unit.scala:676:7]
wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[functional-unit.scala:676:7]
wire [11:0] io_req_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr; // @[functional-unit.scala:676:7]
wire [4:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[functional-unit.scala:676:7]
wire [2:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[functional-unit.scala:676:7]
wire [2:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[functional-unit.scala:676:7]
wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[functional-unit.scala:676:7]
wire [5:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[functional-unit.scala:676:7]
wire [5:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[functional-unit.scala:676:7]
wire [5:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[functional-unit.scala:676:7]
wire [5:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[functional-unit.scala:676:7]
wire [3:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[functional-unit.scala:676:7]
wire [5:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[functional-unit.scala:676:7]
wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_bypassable_0 = io_req_bits_uop_bypassable; // @[functional-unit.scala:676:7]
wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[functional-unit.scala:676:7]
wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[functional-unit.scala:676:7]
wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[functional-unit.scala:676:7]
wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[functional-unit.scala:676:7]
wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[functional-unit.scala:676:7]
wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val; // @[functional-unit.scala:676:7]
wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[functional-unit.scala:676:7]
wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[functional-unit.scala:676:7]
wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_fp_single_0 = io_req_bits_uop_fp_single; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[functional-unit.scala:676:7]
wire [1:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[functional-unit.scala:676:7]
wire [1:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[functional-unit.scala:676:7]
wire [63:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data; // @[functional-unit.scala:676:7]
wire [63:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data; // @[functional-unit.scala:676:7]
wire io_req_bits_kill_0 = io_req_bits_kill; // @[functional-unit.scala:676:7]
wire io_resp_ready_0 = io_resp_ready; // @[functional-unit.scala:676:7]
wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[functional-unit.scala:676:7]
wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[functional-unit.scala:676:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[functional-unit.scala:676:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[functional-unit.scala:676:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[functional-unit.scala:676:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[functional-unit.scala:676:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[functional-unit.scala:676:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[functional-unit.scala:676:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[functional-unit.scala:676:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[functional-unit.scala:676:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[functional-unit.scala:676:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[functional-unit.scala:676:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[functional-unit.scala:676:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[functional-unit.scala:676:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[functional-unit.scala:676:7]
wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[functional-unit.scala:676:7]
wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[functional-unit.scala:676:7]
wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[functional-unit.scala:676:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[functional-unit.scala:676:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[functional-unit.scala:676:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[functional-unit.scala:676:7]
wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[functional-unit.scala:676:7]
wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[functional-unit.scala:676:7]
wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[functional-unit.scala:676:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[functional-unit.scala:676:7]
wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[functional-unit.scala:676:7]
wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[functional-unit.scala:676:7]
wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[functional-unit.scala:676:7]
wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[functional-unit.scala:676:7]
wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[functional-unit.scala:676:7]
wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[functional-unit.scala:676:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[functional-unit.scala:676:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[functional-unit.scala:676:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[functional-unit.scala:676:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[functional-unit.scala:676:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[functional-unit.scala:676:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[functional-unit.scala:676:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[functional-unit.scala:676:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[functional-unit.scala:676:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[functional-unit.scala:676:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[functional-unit.scala:676:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[functional-unit.scala:676:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[functional-unit.scala:676:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[functional-unit.scala:676:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[functional-unit.scala:676:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[functional-unit.scala:676:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[functional-unit.scala:676:7]
wire [38:0] io_resp_bits_sfence_bits_addr = 39'h0; // @[functional-unit.scala:676:7]
wire [24:0] io_resp_bits_mxcpt_bits = 25'h0; // @[functional-unit.scala:676:7]
wire [11:0] io_resp_bits_fflags_bits_uop_csr_addr = 12'h0; // @[functional-unit.scala:676:7]
wire [19:0] io_resp_bits_fflags_bits_uop_imm_packed = 20'h0; // @[functional-unit.scala:676:7]
wire [5:0] io_resp_bits_fflags_bits_uop_pc_lob = 6'h0; // @[functional-unit.scala:676:7]
wire [5:0] io_resp_bits_fflags_bits_uop_pdst = 6'h0; // @[functional-unit.scala:676:7]
wire [5:0] io_resp_bits_fflags_bits_uop_prs1 = 6'h0; // @[functional-unit.scala:676:7]
wire [5:0] io_resp_bits_fflags_bits_uop_prs2 = 6'h0; // @[functional-unit.scala:676:7]
wire [5:0] io_resp_bits_fflags_bits_uop_prs3 = 6'h0; // @[functional-unit.scala:676:7]
wire [5:0] io_resp_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[functional-unit.scala:676:7]
wire [5:0] io_resp_bits_fflags_bits_uop_ldst = 6'h0; // @[functional-unit.scala:676:7]
wire [5:0] io_resp_bits_fflags_bits_uop_lrs1 = 6'h0; // @[functional-unit.scala:676:7]
wire [5:0] io_resp_bits_fflags_bits_uop_lrs2 = 6'h0; // @[functional-unit.scala:676:7]
wire [5:0] io_resp_bits_fflags_bits_uop_lrs3 = 6'h0; // @[functional-unit.scala:676:7]
wire [7:0] io_resp_bits_fflags_bits_uop_br_mask = 8'h0; // @[functional-unit.scala:676:7]
wire [4:0] io_resp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[functional-unit.scala:676:7]
wire [4:0] io_resp_bits_fflags_bits_uop_rob_idx = 5'h0; // @[functional-unit.scala:676:7]
wire [4:0] io_resp_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[functional-unit.scala:676:7]
wire [4:0] io_resp_bits_fflags_bits_flags = 5'h0; // @[functional-unit.scala:676:7]
wire [1:0] io_resp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[functional-unit.scala:676:7]
wire [1:0] io_resp_bits_fflags_bits_uop_iw_state = 2'h0; // @[functional-unit.scala:676:7]
wire [1:0] io_resp_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[functional-unit.scala:676:7]
wire [1:0] io_resp_bits_fflags_bits_uop_mem_size = 2'h0; // @[functional-unit.scala:676:7]
wire [1:0] io_resp_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[functional-unit.scala:676:7]
wire [1:0] io_resp_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[functional-unit.scala:676:7]
wire [1:0] io_resp_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[functional-unit.scala:676:7]
wire [1:0] io_resp_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[functional-unit.scala:676:7]
wire [1:0] io_resp_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[functional-unit.scala:676:7]
wire [3:0] io_resp_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[functional-unit.scala:676:7]
wire [3:0] io_resp_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[functional-unit.scala:676:7]
wire [3:0] io_resp_bits_fflags_bits_uop_ppred = 4'h0; // @[functional-unit.scala:676:7]
wire [9:0] io_resp_bits_fflags_bits_uop_fu_code = 10'h0; // @[functional-unit.scala:676:7]
wire [2:0] io_resp_bits_fflags_bits_uop_iq_type = 3'h0; // @[functional-unit.scala:676:7]
wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[functional-unit.scala:676:7]
wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[functional-unit.scala:676:7]
wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[functional-unit.scala:676:7]
wire [2:0] io_resp_bits_fflags_bits_uop_br_tag = 3'h0; // @[functional-unit.scala:676:7]
wire [2:0] io_resp_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[functional-unit.scala:676:7]
wire [2:0] io_resp_bits_fflags_bits_uop_stq_idx = 3'h0; // @[functional-unit.scala:676:7]
wire [39:0] io_resp_bits_fflags_bits_uop_debug_pc = 40'h0; // @[functional-unit.scala:676:7]
wire [39:0] io_resp_bits_addr = 40'h0; // @[functional-unit.scala:676:7]
wire [31:0] io_resp_bits_fflags_bits_uop_inst = 32'h0; // @[functional-unit.scala:676:7]
wire [31:0] io_resp_bits_fflags_bits_uop_debug_inst = 32'h0; // @[functional-unit.scala:676:7]
wire [6:0] io_resp_bits_fflags_bits_uop_uopc = 7'h0; // @[functional-unit.scala:676:7]
wire io_req_bits_pred_data = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_predicated = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_valid = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_is_rvc = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_is_br = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_is_jalr = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_is_jal = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_is_sfb = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_edge_inst = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_taken = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_exception = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_bypassable = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_mem_signed = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_is_fence = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_is_fencei = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_is_amo = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_uses_stq = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_is_unique = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_ldst_val = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_frs3_en = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_fp_val = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_fp_single = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_mxcpt_valid = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_sfence_valid = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_sfence_bits_rs1 = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_sfence_bits_rs2 = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_sfence_bits_asid = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_sfence_bits_hv = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_sfence_bits_hg = 1'h0; // @[functional-unit.scala:676:7]
wire [63:0] io_req_bits_rs3_data = 64'h0; // @[functional-unit.scala:676:7]
wire [63:0] io_resp_bits_fflags_bits_uop_exc_cause = 64'h0; // @[functional-unit.scala:676:7]
wire _io_resp_valid_T_1; // @[functional-unit.scala:697:44]
wire io_req_ready_0; // @[functional-unit.scala:676:7]
wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:676:7]
wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:676:7]
wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:676:7]
wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:676:7]
wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:676:7]
wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:676:7]
wire [6:0] io_resp_bits_uop_uopc_0; // @[functional-unit.scala:676:7]
wire [31:0] io_resp_bits_uop_inst_0; // @[functional-unit.scala:676:7]
wire [31:0] io_resp_bits_uop_debug_inst_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_is_rvc_0; // @[functional-unit.scala:676:7]
wire [39:0] io_resp_bits_uop_debug_pc_0; // @[functional-unit.scala:676:7]
wire [2:0] io_resp_bits_uop_iq_type_0; // @[functional-unit.scala:676:7]
wire [9:0] io_resp_bits_uop_fu_code_0; // @[functional-unit.scala:676:7]
wire [1:0] io_resp_bits_uop_iw_state_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_is_br_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_is_jalr_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_is_jal_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_is_sfb_0; // @[functional-unit.scala:676:7]
wire [7:0] io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:676:7]
wire [2:0] io_resp_bits_uop_br_tag_0; // @[functional-unit.scala:676:7]
wire [3:0] io_resp_bits_uop_ftq_idx_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_edge_inst_0; // @[functional-unit.scala:676:7]
wire [5:0] io_resp_bits_uop_pc_lob_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_taken_0; // @[functional-unit.scala:676:7]
wire [19:0] io_resp_bits_uop_imm_packed_0; // @[functional-unit.scala:676:7]
wire [11:0] io_resp_bits_uop_csr_addr_0; // @[functional-unit.scala:676:7]
wire [4:0] io_resp_bits_uop_rob_idx_0; // @[functional-unit.scala:676:7]
wire [2:0] io_resp_bits_uop_ldq_idx_0; // @[functional-unit.scala:676:7]
wire [2:0] io_resp_bits_uop_stq_idx_0; // @[functional-unit.scala:676:7]
wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[functional-unit.scala:676:7]
wire [5:0] io_resp_bits_uop_pdst_0; // @[functional-unit.scala:676:7]
wire [5:0] io_resp_bits_uop_prs1_0; // @[functional-unit.scala:676:7]
wire [5:0] io_resp_bits_uop_prs2_0; // @[functional-unit.scala:676:7]
wire [5:0] io_resp_bits_uop_prs3_0; // @[functional-unit.scala:676:7]
wire [3:0] io_resp_bits_uop_ppred_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_prs1_busy_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_prs2_busy_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_prs3_busy_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_ppred_busy_0; // @[functional-unit.scala:676:7]
wire [5:0] io_resp_bits_uop_stale_pdst_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_exception_0; // @[functional-unit.scala:676:7]
wire [63:0] io_resp_bits_uop_exc_cause_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_bypassable_0; // @[functional-unit.scala:676:7]
wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[functional-unit.scala:676:7]
wire [1:0] io_resp_bits_uop_mem_size_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_mem_signed_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_is_fence_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_is_fencei_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_is_amo_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_uses_ldq_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_uses_stq_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_is_unique_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_flush_on_commit_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:676:7]
wire [5:0] io_resp_bits_uop_ldst_0; // @[functional-unit.scala:676:7]
wire [5:0] io_resp_bits_uop_lrs1_0; // @[functional-unit.scala:676:7]
wire [5:0] io_resp_bits_uop_lrs2_0; // @[functional-unit.scala:676:7]
wire [5:0] io_resp_bits_uop_lrs3_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_ldst_val_0; // @[functional-unit.scala:676:7]
wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[functional-unit.scala:676:7]
wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:676:7]
wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_frs3_en_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_fp_val_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_fp_single_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_bp_debug_if_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:676:7]
wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[functional-unit.scala:676:7]
wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[functional-unit.scala:676:7]
wire [63:0] io_resp_bits_data_0; // @[functional-unit.scala:676:7]
wire io_resp_valid_0; // @[functional-unit.scala:676:7]
reg [6:0] r_uop_uopc; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_uopc_0 = r_uop_uopc; // @[functional-unit.scala:652:18, :676:7]
reg [31:0] r_uop_inst; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_inst_0 = r_uop_inst; // @[functional-unit.scala:652:18, :676:7]
reg [31:0] r_uop_debug_inst; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_debug_inst_0 = r_uop_debug_inst; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_is_rvc; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_is_rvc_0 = r_uop_is_rvc; // @[functional-unit.scala:652:18, :676:7]
reg [39:0] r_uop_debug_pc; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_debug_pc_0 = r_uop_debug_pc; // @[functional-unit.scala:652:18, :676:7]
reg [2:0] r_uop_iq_type; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_iq_type_0 = r_uop_iq_type; // @[functional-unit.scala:652:18, :676:7]
reg [9:0] r_uop_fu_code; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_fu_code_0 = r_uop_fu_code; // @[functional-unit.scala:652:18, :676:7]
reg [3:0] r_uop_ctrl_br_type; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_ctrl_br_type_0 = r_uop_ctrl_br_type; // @[functional-unit.scala:652:18, :676:7]
reg [1:0] r_uop_ctrl_op1_sel; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_ctrl_op1_sel_0 = r_uop_ctrl_op1_sel; // @[functional-unit.scala:652:18, :676:7]
reg [2:0] r_uop_ctrl_op2_sel; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_ctrl_op2_sel_0 = r_uop_ctrl_op2_sel; // @[functional-unit.scala:652:18, :676:7]
reg [2:0] r_uop_ctrl_imm_sel; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_ctrl_imm_sel_0 = r_uop_ctrl_imm_sel; // @[functional-unit.scala:652:18, :676:7]
reg [4:0] r_uop_ctrl_op_fcn; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_ctrl_op_fcn_0 = r_uop_ctrl_op_fcn; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_ctrl_fcn_dw; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_ctrl_fcn_dw_0 = r_uop_ctrl_fcn_dw; // @[functional-unit.scala:652:18, :676:7]
reg [2:0] r_uop_ctrl_csr_cmd; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_ctrl_csr_cmd_0 = r_uop_ctrl_csr_cmd; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_ctrl_is_load; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_ctrl_is_load_0 = r_uop_ctrl_is_load; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_ctrl_is_sta; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_ctrl_is_sta_0 = r_uop_ctrl_is_sta; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_ctrl_is_std; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_ctrl_is_std_0 = r_uop_ctrl_is_std; // @[functional-unit.scala:652:18, :676:7]
reg [1:0] r_uop_iw_state; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_iw_state_0 = r_uop_iw_state; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_iw_p1_poisoned; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_iw_p1_poisoned_0 = r_uop_iw_p1_poisoned; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_iw_p2_poisoned; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_iw_p2_poisoned_0 = r_uop_iw_p2_poisoned; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_is_br; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_is_br_0 = r_uop_is_br; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_is_jalr; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_is_jalr_0 = r_uop_is_jalr; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_is_jal; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_is_jal_0 = r_uop_is_jal; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_is_sfb; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_is_sfb_0 = r_uop_is_sfb; // @[functional-unit.scala:652:18, :676:7]
reg [7:0] r_uop_br_mask; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_br_mask_0 = r_uop_br_mask; // @[functional-unit.scala:652:18, :676:7]
reg [2:0] r_uop_br_tag; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_br_tag_0 = r_uop_br_tag; // @[functional-unit.scala:652:18, :676:7]
reg [3:0] r_uop_ftq_idx; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_ftq_idx_0 = r_uop_ftq_idx; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_edge_inst; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_edge_inst_0 = r_uop_edge_inst; // @[functional-unit.scala:652:18, :676:7]
reg [5:0] r_uop_pc_lob; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_pc_lob_0 = r_uop_pc_lob; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_taken; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_taken_0 = r_uop_taken; // @[functional-unit.scala:652:18, :676:7]
reg [19:0] r_uop_imm_packed; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_imm_packed_0 = r_uop_imm_packed; // @[functional-unit.scala:652:18, :676:7]
reg [11:0] r_uop_csr_addr; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_csr_addr_0 = r_uop_csr_addr; // @[functional-unit.scala:652:18, :676:7]
reg [4:0] r_uop_rob_idx; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_rob_idx_0 = r_uop_rob_idx; // @[functional-unit.scala:652:18, :676:7]
reg [2:0] r_uop_ldq_idx; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_ldq_idx_0 = r_uop_ldq_idx; // @[functional-unit.scala:652:18, :676:7]
reg [2:0] r_uop_stq_idx; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_stq_idx_0 = r_uop_stq_idx; // @[functional-unit.scala:652:18, :676:7]
reg [1:0] r_uop_rxq_idx; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_rxq_idx_0 = r_uop_rxq_idx; // @[functional-unit.scala:652:18, :676:7]
reg [5:0] r_uop_pdst; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_pdst_0 = r_uop_pdst; // @[functional-unit.scala:652:18, :676:7]
reg [5:0] r_uop_prs1; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_prs1_0 = r_uop_prs1; // @[functional-unit.scala:652:18, :676:7]
reg [5:0] r_uop_prs2; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_prs2_0 = r_uop_prs2; // @[functional-unit.scala:652:18, :676:7]
reg [5:0] r_uop_prs3; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_prs3_0 = r_uop_prs3; // @[functional-unit.scala:652:18, :676:7]
reg [3:0] r_uop_ppred; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_ppred_0 = r_uop_ppred; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_prs1_busy; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_prs1_busy_0 = r_uop_prs1_busy; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_prs2_busy; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_prs2_busy_0 = r_uop_prs2_busy; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_prs3_busy; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_prs3_busy_0 = r_uop_prs3_busy; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_ppred_busy; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_ppred_busy_0 = r_uop_ppred_busy; // @[functional-unit.scala:652:18, :676:7]
reg [5:0] r_uop_stale_pdst; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_stale_pdst_0 = r_uop_stale_pdst; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_exception; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_exception_0 = r_uop_exception; // @[functional-unit.scala:652:18, :676:7]
reg [63:0] r_uop_exc_cause; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_exc_cause_0 = r_uop_exc_cause; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_bypassable; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_bypassable_0 = r_uop_bypassable; // @[functional-unit.scala:652:18, :676:7]
reg [4:0] r_uop_mem_cmd; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_mem_cmd_0 = r_uop_mem_cmd; // @[functional-unit.scala:652:18, :676:7]
reg [1:0] r_uop_mem_size; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_mem_size_0 = r_uop_mem_size; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_mem_signed; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_mem_signed_0 = r_uop_mem_signed; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_is_fence; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_is_fence_0 = r_uop_is_fence; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_is_fencei; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_is_fencei_0 = r_uop_is_fencei; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_is_amo; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_is_amo_0 = r_uop_is_amo; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_uses_ldq; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_uses_ldq_0 = r_uop_uses_ldq; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_uses_stq; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_uses_stq_0 = r_uop_uses_stq; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_is_sys_pc2epc; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_is_sys_pc2epc_0 = r_uop_is_sys_pc2epc; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_is_unique; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_is_unique_0 = r_uop_is_unique; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_flush_on_commit; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_flush_on_commit_0 = r_uop_flush_on_commit; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_ldst_is_rs1; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_ldst_is_rs1_0 = r_uop_ldst_is_rs1; // @[functional-unit.scala:652:18, :676:7]
reg [5:0] r_uop_ldst; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_ldst_0 = r_uop_ldst; // @[functional-unit.scala:652:18, :676:7]
reg [5:0] r_uop_lrs1; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_lrs1_0 = r_uop_lrs1; // @[functional-unit.scala:652:18, :676:7]
reg [5:0] r_uop_lrs2; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_lrs2_0 = r_uop_lrs2; // @[functional-unit.scala:652:18, :676:7]
reg [5:0] r_uop_lrs3; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_lrs3_0 = r_uop_lrs3; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_ldst_val; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_ldst_val_0 = r_uop_ldst_val; // @[functional-unit.scala:652:18, :676:7]
reg [1:0] r_uop_dst_rtype; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_dst_rtype_0 = r_uop_dst_rtype; // @[functional-unit.scala:652:18, :676:7]
reg [1:0] r_uop_lrs1_rtype; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_lrs1_rtype_0 = r_uop_lrs1_rtype; // @[functional-unit.scala:652:18, :676:7]
reg [1:0] r_uop_lrs2_rtype; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_lrs2_rtype_0 = r_uop_lrs2_rtype; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_frs3_en; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_frs3_en_0 = r_uop_frs3_en; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_fp_val; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_fp_val_0 = r_uop_fp_val; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_fp_single; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_fp_single_0 = r_uop_fp_single; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_xcpt_pf_if; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_xcpt_pf_if_0 = r_uop_xcpt_pf_if; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_xcpt_ae_if; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_xcpt_ae_if_0 = r_uop_xcpt_ae_if; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_xcpt_ma_if; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_xcpt_ma_if_0 = r_uop_xcpt_ma_if; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_bp_debug_if; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_bp_debug_if_0 = r_uop_bp_debug_if; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_bp_xcpt_if; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_bp_xcpt_if_0 = r_uop_bp_xcpt_if; // @[functional-unit.scala:652:18, :676:7]
reg [1:0] r_uop_debug_fsrc; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_debug_fsrc_0 = r_uop_debug_fsrc; // @[functional-unit.scala:652:18, :676:7]
reg [1:0] r_uop_debug_tsrc; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_debug_tsrc_0 = r_uop_debug_tsrc; // @[functional-unit.scala:652:18, :676:7]
wire do_kill; // @[functional-unit.scala:654:21]
wire _T = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35]
wire [7:0] _do_kill_T = io_brupdate_b1_mispredict_mask_0 & io_req_bits_uop_br_mask_0; // @[util.scala:118:51]
wire _do_kill_T_1 = |_do_kill_T; // @[util.scala:118:{51,59}]
wire _do_kill_T_2 = _do_kill_T_1 | io_req_bits_kill_0; // @[util.scala:118:59]
wire [7:0] _r_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
wire [7:0] _r_uop_br_mask_T_1 = io_req_bits_uop_br_mask_0 & _r_uop_br_mask_T; // @[util.scala:85:{25,27}]
wire [7:0] _do_kill_T_3 = io_brupdate_b1_mispredict_mask_0 & r_uop_br_mask; // @[util.scala:118:51]
wire _do_kill_T_4 = |_do_kill_T_3; // @[util.scala:118:{51,59}]
wire _do_kill_T_5 = _do_kill_T_4 | io_req_bits_kill_0; // @[util.scala:118:59]
assign do_kill = _T ? _do_kill_T_2 : _do_kill_T_5; // @[Decoupled.scala:51:35]
wire [7:0] _r_uop_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
wire [7:0] _r_uop_br_mask_T_3 = r_uop_br_mask & _r_uop_br_mask_T_2; // @[util.scala:85:{25,27}]
wire _div_io_req_valid_T = ~do_kill; // @[functional-unit.scala:654:21, :685:42]
wire _div_io_req_valid_T_1 = io_req_valid_0 & _div_io_req_valid_T; // @[functional-unit.scala:676:7, :685:{39,42}]
wire _io_resp_valid_T = ~do_kill; // @[functional-unit.scala:654:21, :685:42, :697:47]
assign _io_resp_valid_T_1 = _div_io_resp_valid & _io_resp_valid_T; // @[functional-unit.scala:682:19, :697:{44,47}]
assign io_resp_valid_0 = _io_resp_valid_T_1; // @[functional-unit.scala:676:7, :697:44]
always @(posedge clock) begin // @[functional-unit.scala:676:7]
if (_T) begin // @[Decoupled.scala:51:35]
r_uop_uopc <= io_req_bits_uop_uopc_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_inst <= io_req_bits_uop_inst_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_debug_inst <= io_req_bits_uop_debug_inst_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_is_rvc <= io_req_bits_uop_is_rvc_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_debug_pc <= io_req_bits_uop_debug_pc_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_iq_type <= io_req_bits_uop_iq_type_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_fu_code <= io_req_bits_uop_fu_code_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_ctrl_br_type <= io_req_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_ctrl_op1_sel <= io_req_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_ctrl_op2_sel <= io_req_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_ctrl_imm_sel <= io_req_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_ctrl_op_fcn <= io_req_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_ctrl_fcn_dw <= io_req_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_ctrl_csr_cmd <= io_req_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_ctrl_is_load <= io_req_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_ctrl_is_sta <= io_req_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_ctrl_is_std <= io_req_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_iw_state <= io_req_bits_uop_iw_state_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_iw_p1_poisoned <= io_req_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_iw_p2_poisoned <= io_req_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_is_br <= io_req_bits_uop_is_br_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_is_jalr <= io_req_bits_uop_is_jalr_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_is_jal <= io_req_bits_uop_is_jal_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_is_sfb <= io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_br_tag <= io_req_bits_uop_br_tag_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_ftq_idx <= io_req_bits_uop_ftq_idx_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_edge_inst <= io_req_bits_uop_edge_inst_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_pc_lob <= io_req_bits_uop_pc_lob_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_taken <= io_req_bits_uop_taken_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_imm_packed <= io_req_bits_uop_imm_packed_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_csr_addr <= io_req_bits_uop_csr_addr_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_rob_idx <= io_req_bits_uop_rob_idx_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_ldq_idx <= io_req_bits_uop_ldq_idx_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_stq_idx <= io_req_bits_uop_stq_idx_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_rxq_idx <= io_req_bits_uop_rxq_idx_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_pdst <= io_req_bits_uop_pdst_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_prs1 <= io_req_bits_uop_prs1_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_prs2 <= io_req_bits_uop_prs2_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_prs3 <= io_req_bits_uop_prs3_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_ppred <= io_req_bits_uop_ppred_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_prs1_busy <= io_req_bits_uop_prs1_busy_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_prs2_busy <= io_req_bits_uop_prs2_busy_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_prs3_busy <= io_req_bits_uop_prs3_busy_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_ppred_busy <= io_req_bits_uop_ppred_busy_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_stale_pdst <= io_req_bits_uop_stale_pdst_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_exception <= io_req_bits_uop_exception_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_exc_cause <= io_req_bits_uop_exc_cause_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_bypassable <= io_req_bits_uop_bypassable_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_mem_cmd <= io_req_bits_uop_mem_cmd_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_mem_size <= io_req_bits_uop_mem_size_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_mem_signed <= io_req_bits_uop_mem_signed_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_is_fence <= io_req_bits_uop_is_fence_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_is_fencei <= io_req_bits_uop_is_fencei_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_is_amo <= io_req_bits_uop_is_amo_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_uses_ldq <= io_req_bits_uop_uses_ldq_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_uses_stq <= io_req_bits_uop_uses_stq_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_is_sys_pc2epc <= io_req_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_is_unique <= io_req_bits_uop_is_unique_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_flush_on_commit <= io_req_bits_uop_flush_on_commit_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_ldst_is_rs1 <= io_req_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_ldst <= io_req_bits_uop_ldst_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_lrs1 <= io_req_bits_uop_lrs1_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_lrs2 <= io_req_bits_uop_lrs2_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_lrs3 <= io_req_bits_uop_lrs3_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_ldst_val <= io_req_bits_uop_ldst_val_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_dst_rtype <= io_req_bits_uop_dst_rtype_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_lrs1_rtype <= io_req_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_lrs2_rtype <= io_req_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_frs3_en <= io_req_bits_uop_frs3_en_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_fp_val <= io_req_bits_uop_fp_val_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_fp_single <= io_req_bits_uop_fp_single_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_xcpt_pf_if <= io_req_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_xcpt_ae_if <= io_req_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_xcpt_ma_if <= io_req_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_bp_debug_if <= io_req_bits_uop_bp_debug_if_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_bp_xcpt_if <= io_req_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_debug_fsrc <= io_req_bits_uop_debug_fsrc_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_debug_tsrc <= io_req_bits_uop_debug_tsrc_0; // @[functional-unit.scala:652:18, :676:7]
end
r_uop_br_mask <= _T ? _r_uop_br_mask_T_1 : _r_uop_br_mask_T_3; // @[Decoupled.scala:51:35]
always @(posedge)
MulDiv_1 div ( // @[functional-unit.scala:682:19]
.clock (clock),
.reset (reset),
.io_req_ready (io_req_ready_0),
.io_req_valid (_div_io_req_valid_T_1), // @[functional-unit.scala:685:39]
.io_req_bits_fn (io_req_bits_uop_ctrl_op_fcn_0), // @[functional-unit.scala:676:7]
.io_req_bits_dw (io_req_bits_uop_ctrl_fcn_dw_0), // @[functional-unit.scala:676:7]
.io_req_bits_in1 (io_req_bits_rs1_data_0), // @[functional-unit.scala:676:7]
.io_req_bits_in2 (io_req_bits_rs2_data_0), // @[functional-unit.scala:676:7]
.io_kill (do_kill), // @[functional-unit.scala:654:21]
.io_resp_ready (io_resp_ready_0), // @[functional-unit.scala:676:7]
.io_resp_valid (_div_io_resp_valid),
.io_resp_bits_data (io_resp_bits_data_0)
); // @[functional-unit.scala:682:19]
assign io_req_ready = io_req_ready_0; // @[functional-unit.scala:676:7]
assign io_resp_valid = io_resp_valid_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_uopc = io_resp_bits_uop_uopc_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_inst = io_resp_bits_uop_inst_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_debug_inst = io_resp_bits_uop_debug_inst_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_is_rvc = io_resp_bits_uop_is_rvc_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_debug_pc = io_resp_bits_uop_debug_pc_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_iq_type = io_resp_bits_uop_iq_type_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_fu_code = io_resp_bits_uop_fu_code_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_ctrl_br_type = io_resp_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_ctrl_op1_sel = io_resp_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_ctrl_op2_sel = io_resp_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_ctrl_imm_sel = io_resp_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_ctrl_op_fcn = io_resp_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_ctrl_fcn_dw = io_resp_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_ctrl_csr_cmd = io_resp_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_ctrl_is_load = io_resp_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_ctrl_is_sta = io_resp_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_ctrl_is_std = io_resp_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_iw_state = io_resp_bits_uop_iw_state_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_iw_p1_poisoned = io_resp_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_iw_p2_poisoned = io_resp_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_is_br = io_resp_bits_uop_is_br_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_is_jalr = io_resp_bits_uop_is_jalr_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_is_jal = io_resp_bits_uop_is_jal_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_is_sfb = io_resp_bits_uop_is_sfb_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_br_mask = io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_br_tag = io_resp_bits_uop_br_tag_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_ftq_idx = io_resp_bits_uop_ftq_idx_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_edge_inst = io_resp_bits_uop_edge_inst_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_pc_lob = io_resp_bits_uop_pc_lob_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_taken = io_resp_bits_uop_taken_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_imm_packed = io_resp_bits_uop_imm_packed_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_csr_addr = io_resp_bits_uop_csr_addr_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_rob_idx = io_resp_bits_uop_rob_idx_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_ldq_idx = io_resp_bits_uop_ldq_idx_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_stq_idx = io_resp_bits_uop_stq_idx_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_rxq_idx = io_resp_bits_uop_rxq_idx_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_pdst = io_resp_bits_uop_pdst_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_prs1 = io_resp_bits_uop_prs1_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_prs2 = io_resp_bits_uop_prs2_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_prs3 = io_resp_bits_uop_prs3_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_ppred = io_resp_bits_uop_ppred_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_prs1_busy = io_resp_bits_uop_prs1_busy_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_prs2_busy = io_resp_bits_uop_prs2_busy_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_prs3_busy = io_resp_bits_uop_prs3_busy_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_ppred_busy = io_resp_bits_uop_ppred_busy_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_stale_pdst = io_resp_bits_uop_stale_pdst_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_exception = io_resp_bits_uop_exception_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_exc_cause = io_resp_bits_uop_exc_cause_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_bypassable = io_resp_bits_uop_bypassable_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_mem_cmd = io_resp_bits_uop_mem_cmd_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_mem_size = io_resp_bits_uop_mem_size_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_mem_signed = io_resp_bits_uop_mem_signed_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_is_fence = io_resp_bits_uop_is_fence_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_is_fencei = io_resp_bits_uop_is_fencei_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_is_amo = io_resp_bits_uop_is_amo_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_uses_ldq = io_resp_bits_uop_uses_ldq_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_uses_stq = io_resp_bits_uop_uses_stq_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_is_sys_pc2epc = io_resp_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_is_unique = io_resp_bits_uop_is_unique_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_flush_on_commit = io_resp_bits_uop_flush_on_commit_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_ldst_is_rs1 = io_resp_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_ldst = io_resp_bits_uop_ldst_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_lrs1 = io_resp_bits_uop_lrs1_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_lrs2 = io_resp_bits_uop_lrs2_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_lrs3 = io_resp_bits_uop_lrs3_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_ldst_val = io_resp_bits_uop_ldst_val_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_dst_rtype = io_resp_bits_uop_dst_rtype_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_lrs1_rtype = io_resp_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_lrs2_rtype = io_resp_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_frs3_en = io_resp_bits_uop_frs3_en_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_fp_val = io_resp_bits_uop_fp_val_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_fp_single = io_resp_bits_uop_fp_single_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_xcpt_pf_if = io_resp_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_xcpt_ae_if = io_resp_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_xcpt_ma_if = io_resp_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_bp_debug_if = io_resp_bits_uop_bp_debug_if_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_bp_xcpt_if = io_resp_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_debug_fsrc = io_resp_bits_uop_debug_fsrc_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_debug_tsrc = io_resp_bits_uop_debug_tsrc_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_data = io_resp_bits_data_0; // @[functional-unit.scala:676:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TilePRCIDomain_1 :
output auto : { intsink_out_2 : UInt<1>[1], intsink_out_1 : UInt<1>[1], intsink_out_0 : UInt<1>[1], flip intsink_in : { sync : UInt<1>[1]}, element_reset_domain_rockettile_trace_core_source_out : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>}, element_reset_domain_rockettile_trace_source_out : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>}, flip element_reset_domain_rockettile_reset_vector_in : UInt<32>, flip element_reset_domain_rockettile_hartid_in : UInt<3>, flip int_in_clock_xing_in_2 : { sync : UInt<1>[1]}, flip int_in_clock_xing_in_1 : { sync : UInt<1>[1]}, flip int_in_clock_xing_in_0 : { sync : UInt<1>[2]}, tl_master_clock_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip tap_clock_in : { clock : Clock, reset : Reset}}
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst element_reset_domain of HierarchicalElementResetDomain_1
inst clockNode of FixedClockBroadcast_1_3
inst buffer of TLBuffer_a32d64s2k3z4c_3
connect buffer.clock, childClock
connect buffer.reset, childReset
inst buffer_1 of TLBuffer_5
connect buffer_1.clock, childClock
connect buffer_1.reset, childReset
inst intsink of IntSyncAsyncCrossingSink_n1x1_1
connect intsink.clock, childClock
connect intsink.reset, childReset
inst intsink_1 of IntSyncSyncCrossingSink_n1x2_1
inst intsink_2 of IntSyncSyncCrossingSink_n1x1_5
inst intsink_3 of IntSyncSyncCrossingSink_n1x1_6
inst intsink_4 of IntSyncSyncCrossingSink_n1x1_7
inst intsource of IntSyncCrossingSource_n1x1_3
connect intsource.clock, childClock
connect intsource.reset, childReset
inst intsink_5 of IntSyncSyncCrossingSink_n1x1_8
inst intsource_1 of IntSyncCrossingSource_n1x1_4
connect intsource_1.clock, childClock
connect intsource_1.reset, childReset
inst intsink_6 of IntSyncSyncCrossingSink_n1x1_9
inst intsource_2 of IntSyncCrossingSource_n1x1_5
connect intsource_2.clock, childClock
connect intsource_2.reset, childReset
wire tapClockNodeOut : { clock : Clock, reset : Reset}
invalidate tapClockNodeOut.reset
invalidate tapClockNodeOut.clock
wire tapClockNodeIn : { clock : Clock, reset : Reset}
invalidate tapClockNodeIn.reset
invalidate tapClockNodeIn.clock
connect tapClockNodeOut, tapClockNodeIn
wire tlMasterClockXingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate tlMasterClockXingOut.e.bits.sink
invalidate tlMasterClockXingOut.e.valid
invalidate tlMasterClockXingOut.e.ready
invalidate tlMasterClockXingOut.d.bits.corrupt
invalidate tlMasterClockXingOut.d.bits.data
invalidate tlMasterClockXingOut.d.bits.denied
invalidate tlMasterClockXingOut.d.bits.sink
invalidate tlMasterClockXingOut.d.bits.source
invalidate tlMasterClockXingOut.d.bits.size
invalidate tlMasterClockXingOut.d.bits.param
invalidate tlMasterClockXingOut.d.bits.opcode
invalidate tlMasterClockXingOut.d.valid
invalidate tlMasterClockXingOut.d.ready
invalidate tlMasterClockXingOut.c.bits.corrupt
invalidate tlMasterClockXingOut.c.bits.data
invalidate tlMasterClockXingOut.c.bits.address
invalidate tlMasterClockXingOut.c.bits.source
invalidate tlMasterClockXingOut.c.bits.size
invalidate tlMasterClockXingOut.c.bits.param
invalidate tlMasterClockXingOut.c.bits.opcode
invalidate tlMasterClockXingOut.c.valid
invalidate tlMasterClockXingOut.c.ready
invalidate tlMasterClockXingOut.b.bits.corrupt
invalidate tlMasterClockXingOut.b.bits.data
invalidate tlMasterClockXingOut.b.bits.mask
invalidate tlMasterClockXingOut.b.bits.address
invalidate tlMasterClockXingOut.b.bits.source
invalidate tlMasterClockXingOut.b.bits.size
invalidate tlMasterClockXingOut.b.bits.param
invalidate tlMasterClockXingOut.b.bits.opcode
invalidate tlMasterClockXingOut.b.valid
invalidate tlMasterClockXingOut.b.ready
invalidate tlMasterClockXingOut.a.bits.corrupt
invalidate tlMasterClockXingOut.a.bits.data
invalidate tlMasterClockXingOut.a.bits.mask
invalidate tlMasterClockXingOut.a.bits.address
invalidate tlMasterClockXingOut.a.bits.source
invalidate tlMasterClockXingOut.a.bits.size
invalidate tlMasterClockXingOut.a.bits.param
invalidate tlMasterClockXingOut.a.bits.opcode
invalidate tlMasterClockXingOut.a.valid
invalidate tlMasterClockXingOut.a.ready
wire tlMasterClockXingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate tlMasterClockXingIn.e.bits.sink
invalidate tlMasterClockXingIn.e.valid
invalidate tlMasterClockXingIn.e.ready
invalidate tlMasterClockXingIn.d.bits.corrupt
invalidate tlMasterClockXingIn.d.bits.data
invalidate tlMasterClockXingIn.d.bits.denied
invalidate tlMasterClockXingIn.d.bits.sink
invalidate tlMasterClockXingIn.d.bits.source
invalidate tlMasterClockXingIn.d.bits.size
invalidate tlMasterClockXingIn.d.bits.param
invalidate tlMasterClockXingIn.d.bits.opcode
invalidate tlMasterClockXingIn.d.valid
invalidate tlMasterClockXingIn.d.ready
invalidate tlMasterClockXingIn.c.bits.corrupt
invalidate tlMasterClockXingIn.c.bits.data
invalidate tlMasterClockXingIn.c.bits.address
invalidate tlMasterClockXingIn.c.bits.source
invalidate tlMasterClockXingIn.c.bits.size
invalidate tlMasterClockXingIn.c.bits.param
invalidate tlMasterClockXingIn.c.bits.opcode
invalidate tlMasterClockXingIn.c.valid
invalidate tlMasterClockXingIn.c.ready
invalidate tlMasterClockXingIn.b.bits.corrupt
invalidate tlMasterClockXingIn.b.bits.data
invalidate tlMasterClockXingIn.b.bits.mask
invalidate tlMasterClockXingIn.b.bits.address
invalidate tlMasterClockXingIn.b.bits.source
invalidate tlMasterClockXingIn.b.bits.size
invalidate tlMasterClockXingIn.b.bits.param
invalidate tlMasterClockXingIn.b.bits.opcode
invalidate tlMasterClockXingIn.b.valid
invalidate tlMasterClockXingIn.b.ready
invalidate tlMasterClockXingIn.a.bits.corrupt
invalidate tlMasterClockXingIn.a.bits.data
invalidate tlMasterClockXingIn.a.bits.mask
invalidate tlMasterClockXingIn.a.bits.address
invalidate tlMasterClockXingIn.a.bits.source
invalidate tlMasterClockXingIn.a.bits.size
invalidate tlMasterClockXingIn.a.bits.param
invalidate tlMasterClockXingIn.a.bits.opcode
invalidate tlMasterClockXingIn.a.valid
invalidate tlMasterClockXingIn.a.ready
connect tlMasterClockXingOut, tlMasterClockXingIn
wire intInClockXingOut : { sync : UInt<1>[2]}
invalidate intInClockXingOut.sync[0]
invalidate intInClockXingOut.sync[1]
wire intInClockXingIn : { sync : UInt<1>[2]}
invalidate intInClockXingIn.sync[0]
invalidate intInClockXingIn.sync[1]
connect intInClockXingOut, intInClockXingIn
wire intInClockXingOut_1 : { sync : UInt<1>[1]}
invalidate intInClockXingOut_1.sync[0]
wire intInClockXingIn_1 : { sync : UInt<1>[1]}
invalidate intInClockXingIn_1.sync[0]
connect intInClockXingOut_1, intInClockXingIn_1
wire intInClockXingOut_2 : { sync : UInt<1>[1]}
invalidate intInClockXingOut_2.sync[0]
wire intInClockXingIn_2 : { sync : UInt<1>[1]}
invalidate intInClockXingIn_2.sync[0]
connect intInClockXingOut_2, intInClockXingIn_2
wire intOutClockXingOut : { sync : UInt<1>[1]}
invalidate intOutClockXingOut.sync[0]
wire intOutClockXingIn : { sync : UInt<1>[1]}
invalidate intOutClockXingIn.sync[0]
connect intOutClockXingOut, intOutClockXingIn
wire intOutClockXingOut_1 : { sync : UInt<1>[1]}
invalidate intOutClockXingOut_1.sync[0]
wire intOutClockXingIn_1 : { sync : UInt<1>[1]}
invalidate intOutClockXingIn_1.sync[0]
connect intOutClockXingOut_1, intOutClockXingIn_1
wire intOutClockXingOut_2 : { sync : UInt<1>[1]}
invalidate intOutClockXingOut_2.sync[0]
wire intOutClockXingIn_2 : { sync : UInt<1>[1]}
invalidate intOutClockXingIn_2.sync[0]
connect intOutClockXingOut_2, intOutClockXingIn_2
wire intOutClockXingOut_3 : { sync : UInt<1>[1]}
invalidate intOutClockXingOut_3.sync[0]
wire intOutClockXingIn_3 : { sync : UInt<1>[1]}
invalidate intOutClockXingIn_3.sync[0]
connect intOutClockXingOut_3, intOutClockXingIn_3
wire intOutClockXingOut_4 : { sync : UInt<1>[1]}
invalidate intOutClockXingOut_4.sync[0]
wire intOutClockXingIn_4 : { sync : UInt<1>[1]}
invalidate intOutClockXingIn_4.sync[0]
connect intOutClockXingOut_4, intOutClockXingIn_4
wire intOutClockXingOut_5 : { sync : UInt<1>[1]}
invalidate intOutClockXingOut_5.sync[0]
wire intOutClockXingIn_5 : { sync : UInt<1>[1]}
invalidate intOutClockXingIn_5.sync[0]
connect intOutClockXingOut_5, intOutClockXingIn_5
connect clockNode.auto.anon_in, tapClockNodeOut
connect element_reset_domain.auto.clock_in, clockNode.auto.anon_out
connect intsource.auto.in[0], element_reset_domain.auto.rockettile_halt_out[0]
connect intsource_2.auto.in[0], element_reset_domain.auto.rockettile_cease_out[0]
connect intsource_1.auto.in[0], element_reset_domain.auto.rockettile_wfi_out[0]
connect buffer.auto.in, element_reset_domain.auto.rockettile_buffer_out
connect tlMasterClockXingIn.e.bits, buffer.auto.out.e.bits
connect tlMasterClockXingIn.e.valid, buffer.auto.out.e.valid
connect buffer.auto.out.e.ready, tlMasterClockXingIn.e.ready
connect buffer.auto.out.d, tlMasterClockXingIn.d
connect tlMasterClockXingIn.c.bits, buffer.auto.out.c.bits
connect tlMasterClockXingIn.c.valid, buffer.auto.out.c.valid
connect buffer.auto.out.c.ready, tlMasterClockXingIn.c.ready
connect buffer.auto.out.b, tlMasterClockXingIn.b
connect tlMasterClockXingIn.a.bits, buffer.auto.out.a.bits
connect tlMasterClockXingIn.a.valid, buffer.auto.out.a.valid
connect buffer.auto.out.a.ready, tlMasterClockXingIn.a.ready
connect element_reset_domain.auto.rockettile_int_local_in_0[0], intsink.auto.out[0]
connect element_reset_domain.auto.rockettile_int_local_in_1[0], intsink_1.auto.out[0]
connect element_reset_domain.auto.rockettile_int_local_in_1[1], intsink_1.auto.out[1]
connect intsink_1.auto.in.sync[0], intInClockXingOut.sync[0]
connect intsink_1.auto.in.sync[1], intInClockXingOut.sync[1]
connect element_reset_domain.auto.rockettile_int_local_in_2[0], intsink_2.auto.out[0]
connect intsink_2.auto.in.sync[0], intInClockXingOut_1.sync[0]
connect element_reset_domain.auto.rockettile_int_local_in_3[0], intsink_3.auto.out[0]
connect intsink_3.auto.in.sync[0], intInClockXingOut_2.sync[0]
connect intsink_4.auto.in.sync[0], intOutClockXingOut.sync[0]
connect intOutClockXingIn, intOutClockXingOut_1
connect intOutClockXingIn_1, intsource.auto.out
connect intsink_5.auto.in.sync[0], intOutClockXingOut_2.sync[0]
connect intOutClockXingIn_2, intOutClockXingOut_3
connect intOutClockXingIn_3, intsource_1.auto.out
connect intsink_6.auto.in.sync[0], intOutClockXingOut_4.sync[0]
connect intOutClockXingIn_4, intOutClockXingOut_5
connect intOutClockXingIn_5, intsource_2.auto.out
connect tapClockNodeIn, auto.tap_clock_in
connect auto.tl_master_clock_xing_out, tlMasterClockXingOut
connect intInClockXingIn, auto.int_in_clock_xing_in_0
connect intInClockXingIn_1, auto.int_in_clock_xing_in_1
connect intInClockXingIn_2, auto.int_in_clock_xing_in_2
connect element_reset_domain.auto.rockettile_hartid_in, auto.element_reset_domain_rockettile_hartid_in
connect element_reset_domain.auto.rockettile_reset_vector_in, auto.element_reset_domain_rockettile_reset_vector_in
connect auto.element_reset_domain_rockettile_trace_source_out.time, element_reset_domain.auto.rockettile_trace_source_out.time
connect auto.element_reset_domain_rockettile_trace_source_out.insns, element_reset_domain.auto.rockettile_trace_source_out.insns
connect auto.element_reset_domain_rockettile_trace_core_source_out.cause, element_reset_domain.auto.rockettile_trace_core_source_out.cause
connect auto.element_reset_domain_rockettile_trace_core_source_out.tval, element_reset_domain.auto.rockettile_trace_core_source_out.tval
connect auto.element_reset_domain_rockettile_trace_core_source_out.priv, element_reset_domain.auto.rockettile_trace_core_source_out.priv
connect auto.element_reset_domain_rockettile_trace_core_source_out.group, element_reset_domain.auto.rockettile_trace_core_source_out.group
connect intsink.auto.in.sync[0], auto.intsink_in.sync[0]
connect auto.intsink_out_0, intsink_4.auto.out
connect auto.intsink_out_1, intsink_5.auto.out
connect auto.intsink_out_2, intsink_6.auto.out
connect childClock, tapClockNodeIn.clock
connect childReset, tapClockNodeIn.reset
connect clock, tapClockNodeIn.clock
connect reset, tapClockNodeIn.reset
extmodule plusarg_reader_100 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_101 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TilePRCIDomain_1( // @[ClockDomain.scala:14:9]
output auto_intsink_out_1_0, // @[LazyModuleImp.scala:107:25]
input auto_intsink_in_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid, // @[LazyModuleImp.scala:107:25]
output [39:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv, // @[LazyModuleImp.scala:107:25]
output auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception, // @[LazyModuleImp.scala:107:25]
output auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause, // @[LazyModuleImp.scala:107:25]
output [39:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_element_reset_domain_rockettile_trace_source_out_time, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_element_reset_domain_rockettile_hartid_in, // @[LazyModuleImp.scala:107:25]
input auto_int_in_clock_xing_in_2_sync_0, // @[LazyModuleImp.scala:107:25]
input auto_int_in_clock_xing_in_1_sync_0, // @[LazyModuleImp.scala:107:25]
input auto_int_in_clock_xing_in_0_sync_0, // @[LazyModuleImp.scala:107:25]
input auto_int_in_clock_xing_in_0_sync_1, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_master_clock_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_master_clock_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_master_clock_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_tl_master_clock_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_master_clock_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_tl_master_clock_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_master_clock_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_master_clock_xing_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_master_clock_xing_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_master_clock_xing_out_b_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_master_clock_xing_out_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_tl_master_clock_xing_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_tl_master_clock_xing_out_b_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_master_clock_xing_out_b_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_master_clock_xing_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_master_clock_xing_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_master_clock_xing_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_tl_master_clock_xing_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_master_clock_xing_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_master_clock_xing_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_master_clock_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_master_clock_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_master_clock_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_master_clock_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_master_clock_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_master_clock_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_e_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_master_clock_xing_out_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_tap_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_tap_clock_in_reset // @[LazyModuleImp.scala:107:25]
);
wire clockNode_auto_anon_in_reset; // @[ClockGroup.scala:104:9]
wire clockNode_auto_anon_in_clock; // @[ClockGroup.scala:104:9]
wire element_reset_domain_auto_clock_in_reset; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_clock_in_clock; // @[ClockDomain.scala:14:9]
wire auto_intsink_in_sync_0_0 = auto_intsink_in_sync_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_element_reset_domain_rockettile_hartid_in_0 = auto_element_reset_domain_rockettile_hartid_in; // @[ClockDomain.scala:14:9]
wire auto_int_in_clock_xing_in_2_sync_0_0 = auto_int_in_clock_xing_in_2_sync_0; // @[ClockDomain.scala:14:9]
wire auto_int_in_clock_xing_in_1_sync_0_0 = auto_int_in_clock_xing_in_1_sync_0; // @[ClockDomain.scala:14:9]
wire auto_int_in_clock_xing_in_0_sync_0_0 = auto_int_in_clock_xing_in_0_sync_0; // @[ClockDomain.scala:14:9]
wire auto_int_in_clock_xing_in_0_sync_1_0 = auto_int_in_clock_xing_in_0_sync_1; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_a_ready_0 = auto_tl_master_clock_xing_out_a_ready; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_b_valid_0 = auto_tl_master_clock_xing_out_b_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_b_bits_opcode_0 = auto_tl_master_clock_xing_out_b_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] auto_tl_master_clock_xing_out_b_bits_param_0 = auto_tl_master_clock_xing_out_b_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] auto_tl_master_clock_xing_out_b_bits_size_0 = auto_tl_master_clock_xing_out_b_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] auto_tl_master_clock_xing_out_b_bits_source_0 = auto_tl_master_clock_xing_out_b_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] auto_tl_master_clock_xing_out_b_bits_address_0 = auto_tl_master_clock_xing_out_b_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] auto_tl_master_clock_xing_out_b_bits_mask_0 = auto_tl_master_clock_xing_out_b_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] auto_tl_master_clock_xing_out_b_bits_data_0 = auto_tl_master_clock_xing_out_b_bits_data; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_b_bits_corrupt_0 = auto_tl_master_clock_xing_out_b_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_c_ready_0 = auto_tl_master_clock_xing_out_c_ready; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_d_valid_0 = auto_tl_master_clock_xing_out_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_d_bits_opcode_0 = auto_tl_master_clock_xing_out_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] auto_tl_master_clock_xing_out_d_bits_param_0 = auto_tl_master_clock_xing_out_d_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] auto_tl_master_clock_xing_out_d_bits_size_0 = auto_tl_master_clock_xing_out_d_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] auto_tl_master_clock_xing_out_d_bits_source_0 = auto_tl_master_clock_xing_out_d_bits_source; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_d_bits_sink_0 = auto_tl_master_clock_xing_out_d_bits_sink; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_d_bits_denied_0 = auto_tl_master_clock_xing_out_d_bits_denied; // @[ClockDomain.scala:14:9]
wire [63:0] auto_tl_master_clock_xing_out_d_bits_data_0 = auto_tl_master_clock_xing_out_d_bits_data; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_d_bits_corrupt_0 = auto_tl_master_clock_xing_out_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_e_ready_0 = auto_tl_master_clock_xing_out_e_ready; // @[ClockDomain.scala:14:9]
wire auto_tap_clock_in_clock_0 = auto_tap_clock_in_clock; // @[ClockDomain.scala:14:9]
wire auto_tap_clock_in_reset_0 = auto_tap_clock_in_reset; // @[ClockDomain.scala:14:9]
wire [31:0] auto_element_reset_domain_rockettile_trace_core_source_out_group_0_iaddr = 32'h0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_element_reset_domain_rockettile_trace_core_source_out_tval = 32'h0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_element_reset_domain_rockettile_trace_core_source_out_cause = 32'h0; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_rockettile_trace_core_source_out_group_0_iaddr = 32'h0; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_rockettile_trace_core_source_out_tval = 32'h0; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_rockettile_trace_core_source_out_cause = 32'h0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_element_reset_domain_rockettile_trace_core_source_out_group_0_itype = 4'h0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_element_reset_domain_rockettile_trace_core_source_out_priv = 4'h0; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_rockettile_trace_core_source_out_group_0_itype = 4'h0; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_rockettile_trace_core_source_out_priv = 4'h0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_element_reset_domain_rockettile_reset_vector_in = 32'h10000; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_rockettile_reset_vector_in = 32'h10000; // @[ClockDomain.scala:14:9]
wire auto_intsink_out_2_0 = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_intsink_out_0_0 = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_element_reset_domain_rockettile_trace_core_source_out_group_0_iretire = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_element_reset_domain_rockettile_trace_core_source_out_group_0_ilastsize = 1'h0; // @[ClockDomain.scala:14:9]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire element_reset_domain_auto_rockettile_buffer_out_a_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_c_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_cease_out_0 = 1'h0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_halt_out_0 = 1'h0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_trace_core_source_out_group_0_iretire = 1'h0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_trace_core_source_out_group_0_ilastsize = 1'h0; // @[ClockDomain.scala:14:9]
wire element_reset_domain__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire clockNode_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire clockNode_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire clockNode__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire intOutClockXingOut_sync_0 = 1'h0; // @[MixedNode.scala:542:17]
wire intOutClockXingIn_sync_0 = 1'h0; // @[MixedNode.scala:551:17]
wire intOutClockXingOut_1_sync_0 = 1'h0; // @[MixedNode.scala:542:17]
wire intOutClockXingIn_1_sync_0 = 1'h0; // @[MixedNode.scala:551:17]
wire intOutClockXingOut_4_sync_0 = 1'h0; // @[MixedNode.scala:542:17]
wire intOutClockXingIn_4_sync_0 = 1'h0; // @[MixedNode.scala:551:17]
wire intOutClockXingOut_5_sync_0 = 1'h0; // @[MixedNode.scala:542:17]
wire intOutClockXingIn_5_sync_0 = 1'h0; // @[MixedNode.scala:551:17]
wire element_reset_domain_auto_rockettile_trace_source_out_insns_0_valid; // @[ClockDomain.scala:14:9]
wire [39:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_iaddr; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_insn; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_priv; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_trace_source_out_insns_0_exception; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_trace_source_out_insns_0_interrupt; // @[ClockDomain.scala:14:9]
wire [63:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_cause; // @[ClockDomain.scala:14:9]
wire [39:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_tval; // @[ClockDomain.scala:14:9]
wire [63:0] element_reset_domain_auto_rockettile_trace_source_out_time; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_rockettile_hartid_in = auto_element_reset_domain_rockettile_hartid_in_0; // @[ClockDomain.scala:14:9]
wire intInClockXingIn_2_sync_0 = auto_int_in_clock_xing_in_2_sync_0_0; // @[ClockDomain.scala:14:9]
wire intInClockXingIn_1_sync_0 = auto_int_in_clock_xing_in_1_sync_0_0; // @[ClockDomain.scala:14:9]
wire intInClockXingIn_sync_0 = auto_int_in_clock_xing_in_0_sync_0_0; // @[ClockDomain.scala:14:9]
wire intInClockXingIn_sync_1 = auto_int_in_clock_xing_in_0_sync_1_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_a_ready = auto_tl_master_clock_xing_out_a_ready_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17]
wire tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire tlMasterClockXingOut_b_ready; // @[MixedNode.scala:542:17]
wire tlMasterClockXingOut_b_valid = auto_tl_master_clock_xing_out_b_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] tlMasterClockXingOut_b_bits_opcode = auto_tl_master_clock_xing_out_b_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] tlMasterClockXingOut_b_bits_param = auto_tl_master_clock_xing_out_b_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] tlMasterClockXingOut_b_bits_size = auto_tl_master_clock_xing_out_b_bits_size_0; // @[ClockDomain.scala:14:9]
wire [1:0] tlMasterClockXingOut_b_bits_source = auto_tl_master_clock_xing_out_b_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] tlMasterClockXingOut_b_bits_address = auto_tl_master_clock_xing_out_b_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] tlMasterClockXingOut_b_bits_mask = auto_tl_master_clock_xing_out_b_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] tlMasterClockXingOut_b_bits_data = auto_tl_master_clock_xing_out_b_bits_data_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_b_bits_corrupt = auto_tl_master_clock_xing_out_b_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_c_ready = auto_tl_master_clock_xing_out_c_ready_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] tlMasterClockXingOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] tlMasterClockXingOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] tlMasterClockXingOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] tlMasterClockXingOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] tlMasterClockXingOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] tlMasterClockXingOut_c_bits_data; // @[MixedNode.scala:542:17]
wire tlMasterClockXingOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17]
wire tlMasterClockXingOut_d_valid = auto_tl_master_clock_xing_out_d_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] tlMasterClockXingOut_d_bits_opcode = auto_tl_master_clock_xing_out_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] tlMasterClockXingOut_d_bits_param = auto_tl_master_clock_xing_out_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] tlMasterClockXingOut_d_bits_size = auto_tl_master_clock_xing_out_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [1:0] tlMasterClockXingOut_d_bits_source = auto_tl_master_clock_xing_out_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire [2:0] tlMasterClockXingOut_d_bits_sink = auto_tl_master_clock_xing_out_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_d_bits_denied = auto_tl_master_clock_xing_out_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [63:0] tlMasterClockXingOut_d_bits_data = auto_tl_master_clock_xing_out_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_d_bits_corrupt = auto_tl_master_clock_xing_out_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_e_ready = auto_tl_master_clock_xing_out_e_ready_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] tlMasterClockXingOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire tapClockNodeIn_clock = auto_tap_clock_in_clock_0; // @[ClockDomain.scala:14:9]
wire tapClockNodeIn_reset = auto_tap_clock_in_reset_0; // @[ClockDomain.scala:14:9]
wire auto_intsink_out_1_0_0; // @[ClockDomain.scala:14:9]
wire auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid_0; // @[ClockDomain.scala:14:9]
wire [39:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv_0; // @[ClockDomain.scala:14:9]
wire auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception_0; // @[ClockDomain.scala:14:9]
wire auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause_0; // @[ClockDomain.scala:14:9]
wire [39:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_element_reset_domain_rockettile_trace_source_out_time_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_tl_master_clock_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_tl_master_clock_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_tl_master_clock_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] auto_tl_master_clock_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_tl_master_clock_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_a_valid_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_b_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_c_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_c_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_tl_master_clock_xing_out_c_bits_size_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_tl_master_clock_xing_out_c_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_tl_master_clock_xing_out_c_bits_address_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_tl_master_clock_xing_out_c_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_c_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_c_valid_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_d_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_e_bits_sink_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_e_valid_0; // @[ClockDomain.scala:14:9]
wire childClock; // @[LazyModuleImp.scala:155:31]
wire childReset; // @[LazyModuleImp.scala:158:31]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_valid; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_iaddr; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_insn; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_priv; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_exception; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_interrupt; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_cause; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_tval; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_time_0 = element_reset_domain_auto_rockettile_trace_source_out_time; // @[ClockDomain.scala:14:9]
wire clockNode_auto_anon_out_clock; // @[ClockGroup.scala:104:9]
wire element_reset_domain_clockNodeIn_clock = element_reset_domain_auto_clock_in_clock; // @[ClockDomain.scala:14:9]
wire clockNode_auto_anon_out_reset; // @[ClockGroup.scala:104:9]
wire [2:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_data; // @[ClockDomain.scala:14:9]
wire element_reset_domain_clockNodeIn_reset = element_reset_domain_auto_clock_in_reset; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_a_ready; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_data; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_b_bits_corrupt; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_b_ready; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_b_valid; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_rockettile_buffer_out_c_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_rockettile_buffer_out_c_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_rockettile_buffer_out_c_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] element_reset_domain_auto_rockettile_buffer_out_c_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_rockettile_buffer_out_c_bits_address; // @[ClockDomain.scala:14:9]
wire [63:0] element_reset_domain_auto_rockettile_buffer_out_c_bits_data; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_c_ready; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_c_valid; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_rockettile_buffer_out_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] element_reset_domain_auto_rockettile_buffer_out_d_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_rockettile_buffer_out_d_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] element_reset_domain_auto_rockettile_buffer_out_d_bits_source; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_rockettile_buffer_out_d_bits_sink; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_d_bits_denied; // @[ClockDomain.scala:14:9]
wire [63:0] element_reset_domain_auto_rockettile_buffer_out_d_bits_data; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_d_ready; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_rockettile_buffer_out_e_bits_sink; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_e_ready; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_e_valid; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_wfi_out_0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_int_local_in_3_0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_int_local_in_2_0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_int_local_in_1_0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_int_local_in_1_1; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_int_local_in_0_0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_childClock; // @[LazyModuleImp.scala:155:31]
wire element_reset_domain_childReset; // @[LazyModuleImp.scala:158:31]
assign element_reset_domain_childClock = element_reset_domain_clockNodeIn_clock; // @[MixedNode.scala:551:17]
assign element_reset_domain_childReset = element_reset_domain_clockNodeIn_reset; // @[MixedNode.scala:551:17]
wire tapClockNodeOut_clock; // @[MixedNode.scala:542:17]
wire clockNode_anonIn_clock = clockNode_auto_anon_in_clock; // @[ClockGroup.scala:104:9]
wire tapClockNodeOut_reset; // @[MixedNode.scala:542:17]
wire clockNode_anonOut_clock; // @[MixedNode.scala:542:17]
wire clockNode_anonIn_reset = clockNode_auto_anon_in_reset; // @[ClockGroup.scala:104:9]
assign element_reset_domain_auto_clock_in_clock = clockNode_auto_anon_out_clock; // @[ClockGroup.scala:104:9]
wire clockNode_anonOut_reset; // @[MixedNode.scala:542:17]
assign element_reset_domain_auto_clock_in_reset = clockNode_auto_anon_out_reset; // @[ClockGroup.scala:104:9]
assign clockNode_auto_anon_out_clock = clockNode_anonOut_clock; // @[ClockGroup.scala:104:9]
assign clockNode_auto_anon_out_reset = clockNode_anonOut_reset; // @[ClockGroup.scala:104:9]
assign clockNode_anonOut_clock = clockNode_anonIn_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockNode_anonOut_reset = clockNode_anonIn_reset; // @[MixedNode.scala:542:17, :551:17]
assign clockNode_auto_anon_in_clock = tapClockNodeOut_clock; // @[ClockGroup.scala:104:9]
assign clockNode_auto_anon_in_reset = tapClockNodeOut_reset; // @[ClockGroup.scala:104:9]
assign childClock = tapClockNodeIn_clock; // @[MixedNode.scala:551:17]
assign tapClockNodeOut_clock = tapClockNodeIn_clock; // @[MixedNode.scala:542:17, :551:17]
assign childReset = tapClockNodeIn_reset; // @[MixedNode.scala:551:17]
assign tapClockNodeOut_reset = tapClockNodeIn_reset; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_a_ready = tlMasterClockXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_a_valid; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_valid_0 = tlMasterClockXingOut_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_bits_opcode_0 = tlMasterClockXingOut_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_bits_param_0 = tlMasterClockXingOut_a_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_bits_size_0 = tlMasterClockXingOut_a_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_bits_source_0 = tlMasterClockXingOut_a_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_bits_address_0 = tlMasterClockXingOut_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_bits_mask_0 = tlMasterClockXingOut_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_bits_data_0 = tlMasterClockXingOut_a_bits_data; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_bits_corrupt_0 = tlMasterClockXingOut_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingIn_b_ready; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_b_ready_0 = tlMasterClockXingOut_b_ready; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingIn_b_valid = tlMasterClockXingOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] tlMasterClockXingIn_b_bits_opcode = tlMasterClockXingOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] tlMasterClockXingIn_b_bits_param = tlMasterClockXingOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] tlMasterClockXingIn_b_bits_size = tlMasterClockXingOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] tlMasterClockXingIn_b_bits_source = tlMasterClockXingOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] tlMasterClockXingIn_b_bits_address = tlMasterClockXingOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [7:0] tlMasterClockXingIn_b_bits_mask = tlMasterClockXingOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] tlMasterClockXingIn_b_bits_data = tlMasterClockXingOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_b_bits_corrupt = tlMasterClockXingOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_c_ready = tlMasterClockXingOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_c_valid; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_c_valid_0 = tlMasterClockXingOut_c_valid; // @[ClockDomain.scala:14:9]
wire [2:0] tlMasterClockXingIn_c_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_c_bits_opcode_0 = tlMasterClockXingOut_c_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] tlMasterClockXingIn_c_bits_param; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_c_bits_param_0 = tlMasterClockXingOut_c_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] tlMasterClockXingIn_c_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_c_bits_size_0 = tlMasterClockXingOut_c_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] tlMasterClockXingIn_c_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_c_bits_source_0 = tlMasterClockXingOut_c_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] tlMasterClockXingIn_c_bits_address; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_c_bits_address_0 = tlMasterClockXingOut_c_bits_address; // @[ClockDomain.scala:14:9]
wire [63:0] tlMasterClockXingIn_c_bits_data; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_c_bits_data_0 = tlMasterClockXingOut_c_bits_data; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingIn_c_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_c_bits_corrupt_0 = tlMasterClockXingOut_c_bits_corrupt; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingIn_d_ready; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_d_ready_0 = tlMasterClockXingOut_d_ready; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingIn_d_valid = tlMasterClockXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] tlMasterClockXingIn_d_bits_opcode = tlMasterClockXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] tlMasterClockXingIn_d_bits_param = tlMasterClockXingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] tlMasterClockXingIn_d_bits_size = tlMasterClockXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] tlMasterClockXingIn_d_bits_source = tlMasterClockXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] tlMasterClockXingIn_d_bits_sink = tlMasterClockXingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_d_bits_denied = tlMasterClockXingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] tlMasterClockXingIn_d_bits_data = tlMasterClockXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_d_bits_corrupt = tlMasterClockXingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_e_ready = tlMasterClockXingOut_e_ready; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_e_valid; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_e_valid_0 = tlMasterClockXingOut_e_valid; // @[ClockDomain.scala:14:9]
wire [2:0] tlMasterClockXingIn_e_bits_sink; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_e_bits_sink_0 = tlMasterClockXingOut_e_bits_sink; // @[ClockDomain.scala:14:9]
assign tlMasterClockXingOut_a_valid = tlMasterClockXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_opcode = tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_param = tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_size = tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_source = tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_address = tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_mask = tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_data = tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_corrupt = tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_b_ready = tlMasterClockXingIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_c_valid = tlMasterClockXingIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_c_bits_opcode = tlMasterClockXingIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_c_bits_param = tlMasterClockXingIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_c_bits_size = tlMasterClockXingIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_c_bits_source = tlMasterClockXingIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_c_bits_address = tlMasterClockXingIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_c_bits_data = tlMasterClockXingIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_c_bits_corrupt = tlMasterClockXingIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_d_ready = tlMasterClockXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_e_valid = tlMasterClockXingIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_e_bits_sink = tlMasterClockXingIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire intInClockXingOut_sync_0; // @[MixedNode.scala:542:17]
wire intInClockXingOut_sync_1; // @[MixedNode.scala:542:17]
assign intInClockXingOut_sync_0 = intInClockXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17]
assign intInClockXingOut_sync_1 = intInClockXingIn_sync_1; // @[MixedNode.scala:542:17, :551:17]
wire intInClockXingOut_1_sync_0; // @[MixedNode.scala:542:17]
assign intInClockXingOut_1_sync_0 = intInClockXingIn_1_sync_0; // @[MixedNode.scala:542:17, :551:17]
wire intInClockXingOut_2_sync_0; // @[MixedNode.scala:542:17]
assign intInClockXingOut_2_sync_0 = intInClockXingIn_2_sync_0; // @[MixedNode.scala:542:17, :551:17]
wire intOutClockXingIn_2_sync_0; // @[MixedNode.scala:551:17]
wire intOutClockXingOut_2_sync_0; // @[MixedNode.scala:542:17]
wire intOutClockXingOut_3_sync_0; // @[MixedNode.scala:542:17]
assign intOutClockXingOut_2_sync_0 = intOutClockXingIn_2_sync_0; // @[MixedNode.scala:542:17, :551:17]
wire intOutClockXingIn_3_sync_0; // @[MixedNode.scala:551:17]
assign intOutClockXingIn_2_sync_0 = intOutClockXingOut_3_sync_0; // @[MixedNode.scala:542:17, :551:17]
assign intOutClockXingOut_3_sync_0 = intOutClockXingIn_3_sync_0; // @[MixedNode.scala:542:17, :551:17]
RocketTile_1 element_reset_domain_rockettile ( // @[HasTiles.scala:164:59]
.clock (element_reset_domain_childClock), // @[LazyModuleImp.scala:155:31]
.reset (element_reset_domain_childReset), // @[LazyModuleImp.scala:158:31]
.auto_buffer_out_a_ready (element_reset_domain_auto_rockettile_buffer_out_a_ready), // @[ClockDomain.scala:14:9]
.auto_buffer_out_a_valid (element_reset_domain_auto_rockettile_buffer_out_a_valid),
.auto_buffer_out_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_a_bits_opcode),
.auto_buffer_out_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_a_bits_param),
.auto_buffer_out_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_a_bits_size),
.auto_buffer_out_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_a_bits_source),
.auto_buffer_out_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_a_bits_address),
.auto_buffer_out_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_a_bits_mask),
.auto_buffer_out_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_a_bits_data),
.auto_buffer_out_b_ready (element_reset_domain_auto_rockettile_buffer_out_b_ready),
.auto_buffer_out_b_valid (element_reset_domain_auto_rockettile_buffer_out_b_valid), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_b_bits_opcode), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_param (element_reset_domain_auto_rockettile_buffer_out_b_bits_param), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_size (element_reset_domain_auto_rockettile_buffer_out_b_bits_size), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_source (element_reset_domain_auto_rockettile_buffer_out_b_bits_source), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_address (element_reset_domain_auto_rockettile_buffer_out_b_bits_address), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_mask (element_reset_domain_auto_rockettile_buffer_out_b_bits_mask), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_data (element_reset_domain_auto_rockettile_buffer_out_b_bits_data), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_b_bits_corrupt), // @[ClockDomain.scala:14:9]
.auto_buffer_out_c_ready (element_reset_domain_auto_rockettile_buffer_out_c_ready), // @[ClockDomain.scala:14:9]
.auto_buffer_out_c_valid (element_reset_domain_auto_rockettile_buffer_out_c_valid),
.auto_buffer_out_c_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_c_bits_opcode),
.auto_buffer_out_c_bits_param (element_reset_domain_auto_rockettile_buffer_out_c_bits_param),
.auto_buffer_out_c_bits_size (element_reset_domain_auto_rockettile_buffer_out_c_bits_size),
.auto_buffer_out_c_bits_source (element_reset_domain_auto_rockettile_buffer_out_c_bits_source),
.auto_buffer_out_c_bits_address (element_reset_domain_auto_rockettile_buffer_out_c_bits_address),
.auto_buffer_out_c_bits_data (element_reset_domain_auto_rockettile_buffer_out_c_bits_data),
.auto_buffer_out_d_ready (element_reset_domain_auto_rockettile_buffer_out_d_ready),
.auto_buffer_out_d_valid (element_reset_domain_auto_rockettile_buffer_out_d_valid), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_d_bits_opcode), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_d_bits_param), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_d_bits_size), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_d_bits_source), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_d_bits_sink), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_d_bits_denied), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_d_bits_data), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_d_bits_corrupt), // @[ClockDomain.scala:14:9]
.auto_buffer_out_e_ready (element_reset_domain_auto_rockettile_buffer_out_e_ready), // @[ClockDomain.scala:14:9]
.auto_buffer_out_e_valid (element_reset_domain_auto_rockettile_buffer_out_e_valid),
.auto_buffer_out_e_bits_sink (element_reset_domain_auto_rockettile_buffer_out_e_bits_sink),
.auto_wfi_out_0 (element_reset_domain_auto_rockettile_wfi_out_0),
.auto_int_local_in_3_0 (element_reset_domain_auto_rockettile_int_local_in_3_0), // @[ClockDomain.scala:14:9]
.auto_int_local_in_2_0 (element_reset_domain_auto_rockettile_int_local_in_2_0), // @[ClockDomain.scala:14:9]
.auto_int_local_in_1_0 (element_reset_domain_auto_rockettile_int_local_in_1_0), // @[ClockDomain.scala:14:9]
.auto_int_local_in_1_1 (element_reset_domain_auto_rockettile_int_local_in_1_1), // @[ClockDomain.scala:14:9]
.auto_int_local_in_0_0 (element_reset_domain_auto_rockettile_int_local_in_0_0), // @[ClockDomain.scala:14:9]
.auto_trace_source_out_insns_0_valid (element_reset_domain_auto_rockettile_trace_source_out_insns_0_valid),
.auto_trace_source_out_insns_0_iaddr (element_reset_domain_auto_rockettile_trace_source_out_insns_0_iaddr),
.auto_trace_source_out_insns_0_insn (element_reset_domain_auto_rockettile_trace_source_out_insns_0_insn),
.auto_trace_source_out_insns_0_priv (element_reset_domain_auto_rockettile_trace_source_out_insns_0_priv),
.auto_trace_source_out_insns_0_exception (element_reset_domain_auto_rockettile_trace_source_out_insns_0_exception),
.auto_trace_source_out_insns_0_interrupt (element_reset_domain_auto_rockettile_trace_source_out_insns_0_interrupt),
.auto_trace_source_out_insns_0_cause (element_reset_domain_auto_rockettile_trace_source_out_insns_0_cause),
.auto_trace_source_out_insns_0_tval (element_reset_domain_auto_rockettile_trace_source_out_insns_0_tval),
.auto_trace_source_out_time (element_reset_domain_auto_rockettile_trace_source_out_time),
.auto_hartid_in (element_reset_domain_auto_rockettile_hartid_in) // @[ClockDomain.scala:14:9]
); // @[HasTiles.scala:164:59]
TLBuffer_a32d64s2k3z4c_3 buffer ( // @[Buffer.scala:75:28]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_a_ready (element_reset_domain_auto_rockettile_buffer_out_a_ready),
.auto_in_a_valid (element_reset_domain_auto_rockettile_buffer_out_a_valid), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_a_bits_opcode), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_a_bits_param), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_a_bits_size), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_a_bits_source), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_a_bits_address), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_a_bits_mask), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_a_bits_data), // @[ClockDomain.scala:14:9]
.auto_in_b_ready (element_reset_domain_auto_rockettile_buffer_out_b_ready), // @[ClockDomain.scala:14:9]
.auto_in_b_valid (element_reset_domain_auto_rockettile_buffer_out_b_valid),
.auto_in_b_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_b_bits_opcode),
.auto_in_b_bits_param (element_reset_domain_auto_rockettile_buffer_out_b_bits_param),
.auto_in_b_bits_size (element_reset_domain_auto_rockettile_buffer_out_b_bits_size),
.auto_in_b_bits_source (element_reset_domain_auto_rockettile_buffer_out_b_bits_source),
.auto_in_b_bits_address (element_reset_domain_auto_rockettile_buffer_out_b_bits_address),
.auto_in_b_bits_mask (element_reset_domain_auto_rockettile_buffer_out_b_bits_mask),
.auto_in_b_bits_data (element_reset_domain_auto_rockettile_buffer_out_b_bits_data),
.auto_in_b_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_b_bits_corrupt),
.auto_in_c_ready (element_reset_domain_auto_rockettile_buffer_out_c_ready),
.auto_in_c_valid (element_reset_domain_auto_rockettile_buffer_out_c_valid), // @[ClockDomain.scala:14:9]
.auto_in_c_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_c_bits_opcode), // @[ClockDomain.scala:14:9]
.auto_in_c_bits_param (element_reset_domain_auto_rockettile_buffer_out_c_bits_param), // @[ClockDomain.scala:14:9]
.auto_in_c_bits_size (element_reset_domain_auto_rockettile_buffer_out_c_bits_size), // @[ClockDomain.scala:14:9]
.auto_in_c_bits_source (element_reset_domain_auto_rockettile_buffer_out_c_bits_source), // @[ClockDomain.scala:14:9]
.auto_in_c_bits_address (element_reset_domain_auto_rockettile_buffer_out_c_bits_address), // @[ClockDomain.scala:14:9]
.auto_in_c_bits_data (element_reset_domain_auto_rockettile_buffer_out_c_bits_data), // @[ClockDomain.scala:14:9]
.auto_in_d_ready (element_reset_domain_auto_rockettile_buffer_out_d_ready), // @[ClockDomain.scala:14:9]
.auto_in_d_valid (element_reset_domain_auto_rockettile_buffer_out_d_valid),
.auto_in_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_d_bits_opcode),
.auto_in_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_d_bits_param),
.auto_in_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_d_bits_size),
.auto_in_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_d_bits_source),
.auto_in_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_d_bits_sink),
.auto_in_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_d_bits_denied),
.auto_in_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_d_bits_data),
.auto_in_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_d_bits_corrupt),
.auto_in_e_ready (element_reset_domain_auto_rockettile_buffer_out_e_ready),
.auto_in_e_valid (element_reset_domain_auto_rockettile_buffer_out_e_valid), // @[ClockDomain.scala:14:9]
.auto_in_e_bits_sink (element_reset_domain_auto_rockettile_buffer_out_e_bits_sink), // @[ClockDomain.scala:14:9]
.auto_out_a_ready (tlMasterClockXingIn_a_ready), // @[MixedNode.scala:551:17]
.auto_out_a_valid (tlMasterClockXingIn_a_valid),
.auto_out_a_bits_opcode (tlMasterClockXingIn_a_bits_opcode),
.auto_out_a_bits_param (tlMasterClockXingIn_a_bits_param),
.auto_out_a_bits_size (tlMasterClockXingIn_a_bits_size),
.auto_out_a_bits_source (tlMasterClockXingIn_a_bits_source),
.auto_out_a_bits_address (tlMasterClockXingIn_a_bits_address),
.auto_out_a_bits_mask (tlMasterClockXingIn_a_bits_mask),
.auto_out_a_bits_data (tlMasterClockXingIn_a_bits_data),
.auto_out_a_bits_corrupt (tlMasterClockXingIn_a_bits_corrupt),
.auto_out_b_ready (tlMasterClockXingIn_b_ready),
.auto_out_b_valid (tlMasterClockXingIn_b_valid), // @[MixedNode.scala:551:17]
.auto_out_b_bits_opcode (tlMasterClockXingIn_b_bits_opcode), // @[MixedNode.scala:551:17]
.auto_out_b_bits_param (tlMasterClockXingIn_b_bits_param), // @[MixedNode.scala:551:17]
.auto_out_b_bits_size (tlMasterClockXingIn_b_bits_size), // @[MixedNode.scala:551:17]
.auto_out_b_bits_source (tlMasterClockXingIn_b_bits_source), // @[MixedNode.scala:551:17]
.auto_out_b_bits_address (tlMasterClockXingIn_b_bits_address), // @[MixedNode.scala:551:17]
.auto_out_b_bits_mask (tlMasterClockXingIn_b_bits_mask), // @[MixedNode.scala:551:17]
.auto_out_b_bits_data (tlMasterClockXingIn_b_bits_data), // @[MixedNode.scala:551:17]
.auto_out_b_bits_corrupt (tlMasterClockXingIn_b_bits_corrupt), // @[MixedNode.scala:551:17]
.auto_out_c_ready (tlMasterClockXingIn_c_ready), // @[MixedNode.scala:551:17]
.auto_out_c_valid (tlMasterClockXingIn_c_valid),
.auto_out_c_bits_opcode (tlMasterClockXingIn_c_bits_opcode),
.auto_out_c_bits_param (tlMasterClockXingIn_c_bits_param),
.auto_out_c_bits_size (tlMasterClockXingIn_c_bits_size),
.auto_out_c_bits_source (tlMasterClockXingIn_c_bits_source),
.auto_out_c_bits_address (tlMasterClockXingIn_c_bits_address),
.auto_out_c_bits_data (tlMasterClockXingIn_c_bits_data),
.auto_out_c_bits_corrupt (tlMasterClockXingIn_c_bits_corrupt),
.auto_out_d_ready (tlMasterClockXingIn_d_ready),
.auto_out_d_valid (tlMasterClockXingIn_d_valid), // @[MixedNode.scala:551:17]
.auto_out_d_bits_opcode (tlMasterClockXingIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.auto_out_d_bits_param (tlMasterClockXingIn_d_bits_param), // @[MixedNode.scala:551:17]
.auto_out_d_bits_size (tlMasterClockXingIn_d_bits_size), // @[MixedNode.scala:551:17]
.auto_out_d_bits_source (tlMasterClockXingIn_d_bits_source), // @[MixedNode.scala:551:17]
.auto_out_d_bits_sink (tlMasterClockXingIn_d_bits_sink), // @[MixedNode.scala:551:17]
.auto_out_d_bits_denied (tlMasterClockXingIn_d_bits_denied), // @[MixedNode.scala:551:17]
.auto_out_d_bits_data (tlMasterClockXingIn_d_bits_data), // @[MixedNode.scala:551:17]
.auto_out_d_bits_corrupt (tlMasterClockXingIn_d_bits_corrupt), // @[MixedNode.scala:551:17]
.auto_out_e_ready (tlMasterClockXingIn_e_ready), // @[MixedNode.scala:551:17]
.auto_out_e_valid (tlMasterClockXingIn_e_valid),
.auto_out_e_bits_sink (tlMasterClockXingIn_e_bits_sink)
); // @[Buffer.scala:75:28]
TLBuffer_5 buffer_1 ( // @[Buffer.scala:75:28]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset) // @[LazyModuleImp.scala:158:31]
); // @[Buffer.scala:75:28]
IntSyncAsyncCrossingSink_n1x1_1 intsink ( // @[Crossing.scala:86:29]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_sync_0 (auto_intsink_in_sync_0_0), // @[ClockDomain.scala:14:9]
.auto_out_0 (element_reset_domain_auto_rockettile_int_local_in_0_0)
); // @[Crossing.scala:86:29]
IntSyncSyncCrossingSink_n1x2_1 intsink_1 ( // @[Crossing.scala:109:29]
.auto_in_sync_0 (intInClockXingOut_sync_0), // @[MixedNode.scala:542:17]
.auto_in_sync_1 (intInClockXingOut_sync_1), // @[MixedNode.scala:542:17]
.auto_out_0 (element_reset_domain_auto_rockettile_int_local_in_1_0),
.auto_out_1 (element_reset_domain_auto_rockettile_int_local_in_1_1)
); // @[Crossing.scala:109:29]
IntSyncSyncCrossingSink_n1x1_5 intsink_2 ( // @[Crossing.scala:109:29]
.auto_in_sync_0 (intInClockXingOut_1_sync_0), // @[MixedNode.scala:542:17]
.auto_out_0 (element_reset_domain_auto_rockettile_int_local_in_2_0)
); // @[Crossing.scala:109:29]
IntSyncSyncCrossingSink_n1x1_6 intsink_3 ( // @[Crossing.scala:109:29]
.auto_in_sync_0 (intInClockXingOut_2_sync_0), // @[MixedNode.scala:542:17]
.auto_out_0 (element_reset_domain_auto_rockettile_int_local_in_3_0)
); // @[Crossing.scala:109:29]
IntSyncSyncCrossingSink_n1x1_7 intsink_4 (); // @[Crossing.scala:109:29]
IntSyncCrossingSource_n1x1_3 intsource ( // @[Crossing.scala:29:31]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset) // @[LazyModuleImp.scala:158:31]
); // @[Crossing.scala:29:31]
IntSyncSyncCrossingSink_n1x1_8 intsink_5 ( // @[Crossing.scala:109:29]
.auto_in_sync_0 (intOutClockXingOut_2_sync_0), // @[MixedNode.scala:542:17]
.auto_out_0 (auto_intsink_out_1_0_0)
); // @[Crossing.scala:109:29]
IntSyncCrossingSource_n1x1_4 intsource_1 ( // @[Crossing.scala:29:31]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_0 (element_reset_domain_auto_rockettile_wfi_out_0), // @[ClockDomain.scala:14:9]
.auto_out_sync_0 (intOutClockXingIn_3_sync_0)
); // @[Crossing.scala:29:31]
IntSyncSyncCrossingSink_n1x1_9 intsink_6 (); // @[Crossing.scala:109:29]
IntSyncCrossingSource_n1x1_5 intsource_2 ( // @[Crossing.scala:29:31]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset) // @[LazyModuleImp.scala:158:31]
); // @[Crossing.scala:29:31]
assign auto_intsink_out_1_0 = auto_intsink_out_1_0_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid = auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr = auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn = auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv = auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception = auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt = auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause = auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval = auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_time = auto_element_reset_domain_rockettile_trace_source_out_time_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_valid = auto_tl_master_clock_xing_out_a_valid_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_bits_opcode = auto_tl_master_clock_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_bits_param = auto_tl_master_clock_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_bits_size = auto_tl_master_clock_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_bits_source = auto_tl_master_clock_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_bits_address = auto_tl_master_clock_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_bits_mask = auto_tl_master_clock_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_bits_data = auto_tl_master_clock_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_bits_corrupt = auto_tl_master_clock_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_b_ready = auto_tl_master_clock_xing_out_b_ready_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_c_valid = auto_tl_master_clock_xing_out_c_valid_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_c_bits_opcode = auto_tl_master_clock_xing_out_c_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_c_bits_param = auto_tl_master_clock_xing_out_c_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_c_bits_size = auto_tl_master_clock_xing_out_c_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_c_bits_source = auto_tl_master_clock_xing_out_c_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_c_bits_address = auto_tl_master_clock_xing_out_c_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_c_bits_data = auto_tl_master_clock_xing_out_c_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_c_bits_corrupt = auto_tl_master_clock_xing_out_c_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_d_ready = auto_tl_master_clock_xing_out_d_ready_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_e_valid = auto_tl_master_clock_xing_out_e_valid_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_e_bits_sink = auto_tl_master_clock_xing_out_e_bits_sink_0; // @[ClockDomain.scala:14:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IntSyncCrossingSource_n1x1_1 :
input clock : Clock
input reset : Reset
output auto : { flip in : UInt<1>[1], out : { sync : UInt<1>[1]}}
wire nodeIn : UInt<1>[1]
invalidate nodeIn[0]
wire nodeOut : { sync : UInt<1>[1]}
invalidate nodeOut.sync[0]
connect auto.out, nodeOut
connect nodeIn, auto.in
inst reg of AsyncResetRegVec_w1_i0_1
connect reg.clock, clock
connect reg.reset, reset
connect reg.io.d, nodeIn[0]
connect reg.io.en, UInt<1>(0h1)
node _T = bits(reg.io.q, 0, 0)
connect nodeOut.sync[0], _T | module IntSyncCrossingSource_n1x1_1( // @[Crossing.scala:41:9]
input clock, // @[Crossing.scala:41:9]
input reset // @[Crossing.scala:41:9]
);
wire auto_in_0 = 1'h0; // @[Crossing.scala:41:9]
wire auto_out_sync_0 = 1'h0; // @[Crossing.scala:41:9]
wire nodeIn_0 = 1'h0; // @[MixedNode.scala:551:17]
wire nodeOut_sync_0 = 1'h0; // @[MixedNode.scala:542:17]
AsyncResetRegVec_w1_i0_1 reg_0 ( // @[AsyncResetReg.scala:86:21]
.clock (clock),
.reset (reset)
); // @[AsyncResetReg.scala:86:21]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module SwitchArbiter :
input clock : Clock
input reset : Reset
output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}, tail : UInt<1>}}[3], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}, tail : UInt<1>}}[1], chosen_oh : UInt<3>[1]}
regreset lock_0 : UInt<3>, clock, reset, UInt<3>(0h0)
node unassigned_hi = cat(io.in[2].valid, io.in[1].valid)
node _unassigned_T = cat(unassigned_hi, io.in[0].valid)
node _unassigned_T_1 = not(lock_0)
node unassigned = and(_unassigned_T, _unassigned_T_1)
regreset mask : UInt<3>, clock, reset, UInt<3>(0h0)
wire choices : UInt<3>[1]
node _sel_T = not(mask)
node _sel_T_1 = and(unassigned, _sel_T)
node _sel_T_2 = cat(unassigned, _sel_T_1)
node _sel_T_3 = bits(_sel_T_2, 0, 0)
node _sel_T_4 = bits(_sel_T_2, 1, 1)
node _sel_T_5 = bits(_sel_T_2, 2, 2)
node _sel_T_6 = bits(_sel_T_2, 3, 3)
node _sel_T_7 = bits(_sel_T_2, 4, 4)
node _sel_T_8 = bits(_sel_T_2, 5, 5)
node _sel_T_9 = mux(_sel_T_8, UInt<6>(0h20), UInt<6>(0h0))
node _sel_T_10 = mux(_sel_T_7, UInt<6>(0h10), _sel_T_9)
node _sel_T_11 = mux(_sel_T_6, UInt<6>(0h8), _sel_T_10)
node _sel_T_12 = mux(_sel_T_5, UInt<6>(0h4), _sel_T_11)
node _sel_T_13 = mux(_sel_T_4, UInt<6>(0h2), _sel_T_12)
node sel = mux(_sel_T_3, UInt<6>(0h1), _sel_T_13)
node _choices_0_T = shr(sel, 3)
node _choices_0_T_1 = or(sel, _choices_0_T)
connect choices[0], _choices_0_T_1
node _T = not(choices[0])
node _T_1 = and(unassigned, _T)
node _T_2 = bits(_T_1, 0, 0)
node _T_3 = bits(_T_1, 1, 1)
node _T_4 = bits(_T_1, 2, 2)
node _T_5 = mux(_T_4, UInt<3>(0h4), UInt<3>(0h0))
node _T_6 = mux(_T_3, UInt<3>(0h2), _T_5)
node _T_7 = mux(_T_2, UInt<3>(0h1), _T_6)
connect io.in[0].ready, UInt<1>(0h0)
connect io.in[1].ready, UInt<1>(0h0)
connect io.in[2].ready, UInt<1>(0h0)
node in_tails_hi = cat(io.in[2].bits.tail, io.in[1].bits.tail)
node in_tails = cat(in_tails_hi, io.in[0].bits.tail)
node _in_valids_T = eq(UInt<1>(0h0), UInt<1>(0h0))
node _in_valids_T_1 = and(io.in[0].valid, _in_valids_T)
node _in_valids_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _in_valids_T_3 = and(io.in[1].valid, _in_valids_T_2)
node _in_valids_T_4 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _in_valids_T_5 = and(io.in[2].valid, _in_valids_T_4)
node in_valids_hi = cat(_in_valids_T_5, _in_valids_T_3)
node in_valids = cat(in_valids_hi, _in_valids_T_1)
node _chosen_T = and(in_valids, lock_0)
node _chosen_T_1 = not(UInt<3>(0h0))
node _chosen_T_2 = and(_chosen_T, _chosen_T_1)
node _chosen_T_3 = orr(_chosen_T_2)
node chosen = mux(_chosen_T_3, lock_0, choices[0])
connect io.chosen_oh[0], chosen
node _io_out_0_valid_T = and(in_valids, chosen)
node _io_out_0_valid_T_1 = orr(_io_out_0_valid_T)
connect io.out[0].valid, _io_out_0_valid_T_1
node _io_out_0_bits_T = bits(chosen, 0, 0)
node _io_out_0_bits_T_1 = bits(chosen, 1, 1)
node _io_out_0_bits_T_2 = bits(chosen, 2, 2)
wire _io_out_0_bits_WIRE : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}, tail : UInt<1>}
node _io_out_0_bits_T_3 = mux(_io_out_0_bits_T, io.in[0].bits.tail, UInt<1>(0h0))
node _io_out_0_bits_T_4 = mux(_io_out_0_bits_T_1, io.in[1].bits.tail, UInt<1>(0h0))
node _io_out_0_bits_T_5 = mux(_io_out_0_bits_T_2, io.in[2].bits.tail, UInt<1>(0h0))
node _io_out_0_bits_T_6 = or(_io_out_0_bits_T_3, _io_out_0_bits_T_4)
node _io_out_0_bits_T_7 = or(_io_out_0_bits_T_6, _io_out_0_bits_T_5)
wire _io_out_0_bits_WIRE_1 : UInt<1>
connect _io_out_0_bits_WIRE_1, _io_out_0_bits_T_7
connect _io_out_0_bits_WIRE.tail, _io_out_0_bits_WIRE_1
wire _io_out_0_bits_WIRE_2 : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}
wire _io_out_0_bits_WIRE_3 : UInt<1>[3]
node _io_out_0_bits_T_8 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[0], UInt<1>(0h0))
node _io_out_0_bits_T_9 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[0], UInt<1>(0h0))
node _io_out_0_bits_T_10 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[0], UInt<1>(0h0))
node _io_out_0_bits_T_11 = or(_io_out_0_bits_T_8, _io_out_0_bits_T_9)
node _io_out_0_bits_T_12 = or(_io_out_0_bits_T_11, _io_out_0_bits_T_10)
wire _io_out_0_bits_WIRE_4 : UInt<1>
connect _io_out_0_bits_WIRE_4, _io_out_0_bits_T_12
connect _io_out_0_bits_WIRE_3[0], _io_out_0_bits_WIRE_4
node _io_out_0_bits_T_13 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[1], UInt<1>(0h0))
node _io_out_0_bits_T_14 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[1], UInt<1>(0h0))
node _io_out_0_bits_T_15 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[1], UInt<1>(0h0))
node _io_out_0_bits_T_16 = or(_io_out_0_bits_T_13, _io_out_0_bits_T_14)
node _io_out_0_bits_T_17 = or(_io_out_0_bits_T_16, _io_out_0_bits_T_15)
wire _io_out_0_bits_WIRE_5 : UInt<1>
connect _io_out_0_bits_WIRE_5, _io_out_0_bits_T_17
connect _io_out_0_bits_WIRE_3[1], _io_out_0_bits_WIRE_5
node _io_out_0_bits_T_18 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[2], UInt<1>(0h0))
node _io_out_0_bits_T_19 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[2], UInt<1>(0h0))
node _io_out_0_bits_T_20 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[2], UInt<1>(0h0))
node _io_out_0_bits_T_21 = or(_io_out_0_bits_T_18, _io_out_0_bits_T_19)
node _io_out_0_bits_T_22 = or(_io_out_0_bits_T_21, _io_out_0_bits_T_20)
wire _io_out_0_bits_WIRE_6 : UInt<1>
connect _io_out_0_bits_WIRE_6, _io_out_0_bits_T_22
connect _io_out_0_bits_WIRE_3[2], _io_out_0_bits_WIRE_6
connect _io_out_0_bits_WIRE_2.`0`, _io_out_0_bits_WIRE_3
wire _io_out_0_bits_WIRE_7 : UInt<1>[3]
node _io_out_0_bits_T_23 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[0], UInt<1>(0h0))
node _io_out_0_bits_T_24 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[0], UInt<1>(0h0))
node _io_out_0_bits_T_25 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`1`[0], UInt<1>(0h0))
node _io_out_0_bits_T_26 = or(_io_out_0_bits_T_23, _io_out_0_bits_T_24)
node _io_out_0_bits_T_27 = or(_io_out_0_bits_T_26, _io_out_0_bits_T_25)
wire _io_out_0_bits_WIRE_8 : UInt<1>
connect _io_out_0_bits_WIRE_8, _io_out_0_bits_T_27
connect _io_out_0_bits_WIRE_7[0], _io_out_0_bits_WIRE_8
node _io_out_0_bits_T_28 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[1], UInt<1>(0h0))
node _io_out_0_bits_T_29 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[1], UInt<1>(0h0))
node _io_out_0_bits_T_30 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`1`[1], UInt<1>(0h0))
node _io_out_0_bits_T_31 = or(_io_out_0_bits_T_28, _io_out_0_bits_T_29)
node _io_out_0_bits_T_32 = or(_io_out_0_bits_T_31, _io_out_0_bits_T_30)
wire _io_out_0_bits_WIRE_9 : UInt<1>
connect _io_out_0_bits_WIRE_9, _io_out_0_bits_T_32
connect _io_out_0_bits_WIRE_7[1], _io_out_0_bits_WIRE_9
node _io_out_0_bits_T_33 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[2], UInt<1>(0h0))
node _io_out_0_bits_T_34 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[2], UInt<1>(0h0))
node _io_out_0_bits_T_35 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`1`[2], UInt<1>(0h0))
node _io_out_0_bits_T_36 = or(_io_out_0_bits_T_33, _io_out_0_bits_T_34)
node _io_out_0_bits_T_37 = or(_io_out_0_bits_T_36, _io_out_0_bits_T_35)
wire _io_out_0_bits_WIRE_10 : UInt<1>
connect _io_out_0_bits_WIRE_10, _io_out_0_bits_T_37
connect _io_out_0_bits_WIRE_7[2], _io_out_0_bits_WIRE_10
connect _io_out_0_bits_WIRE_2.`1`, _io_out_0_bits_WIRE_7
wire _io_out_0_bits_WIRE_11 : UInt<1>[1]
node _io_out_0_bits_T_38 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`2`[0], UInt<1>(0h0))
node _io_out_0_bits_T_39 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`2`[0], UInt<1>(0h0))
node _io_out_0_bits_T_40 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`2`[0], UInt<1>(0h0))
node _io_out_0_bits_T_41 = or(_io_out_0_bits_T_38, _io_out_0_bits_T_39)
node _io_out_0_bits_T_42 = or(_io_out_0_bits_T_41, _io_out_0_bits_T_40)
wire _io_out_0_bits_WIRE_12 : UInt<1>
connect _io_out_0_bits_WIRE_12, _io_out_0_bits_T_42
connect _io_out_0_bits_WIRE_11[0], _io_out_0_bits_WIRE_12
connect _io_out_0_bits_WIRE_2.`2`, _io_out_0_bits_WIRE_11
wire _io_out_0_bits_WIRE_13 : UInt<1>[1]
node _io_out_0_bits_T_43 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`3`[0], UInt<1>(0h0))
node _io_out_0_bits_T_44 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`3`[0], UInt<1>(0h0))
node _io_out_0_bits_T_45 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`3`[0], UInt<1>(0h0))
node _io_out_0_bits_T_46 = or(_io_out_0_bits_T_43, _io_out_0_bits_T_44)
node _io_out_0_bits_T_47 = or(_io_out_0_bits_T_46, _io_out_0_bits_T_45)
wire _io_out_0_bits_WIRE_14 : UInt<1>
connect _io_out_0_bits_WIRE_14, _io_out_0_bits_T_47
connect _io_out_0_bits_WIRE_13[0], _io_out_0_bits_WIRE_14
connect _io_out_0_bits_WIRE_2.`3`, _io_out_0_bits_WIRE_13
wire _io_out_0_bits_WIRE_15 : UInt<1>[1]
node _io_out_0_bits_T_48 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`4`[0], UInt<1>(0h0))
node _io_out_0_bits_T_49 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`4`[0], UInt<1>(0h0))
node _io_out_0_bits_T_50 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`4`[0], UInt<1>(0h0))
node _io_out_0_bits_T_51 = or(_io_out_0_bits_T_48, _io_out_0_bits_T_49)
node _io_out_0_bits_T_52 = or(_io_out_0_bits_T_51, _io_out_0_bits_T_50)
wire _io_out_0_bits_WIRE_16 : UInt<1>
connect _io_out_0_bits_WIRE_16, _io_out_0_bits_T_52
connect _io_out_0_bits_WIRE_15[0], _io_out_0_bits_WIRE_16
connect _io_out_0_bits_WIRE_2.`4`, _io_out_0_bits_WIRE_15
wire _io_out_0_bits_WIRE_17 : UInt<1>[1]
node _io_out_0_bits_T_53 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`5`[0], UInt<1>(0h0))
node _io_out_0_bits_T_54 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`5`[0], UInt<1>(0h0))
node _io_out_0_bits_T_55 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`5`[0], UInt<1>(0h0))
node _io_out_0_bits_T_56 = or(_io_out_0_bits_T_53, _io_out_0_bits_T_54)
node _io_out_0_bits_T_57 = or(_io_out_0_bits_T_56, _io_out_0_bits_T_55)
wire _io_out_0_bits_WIRE_18 : UInt<1>
connect _io_out_0_bits_WIRE_18, _io_out_0_bits_T_57
connect _io_out_0_bits_WIRE_17[0], _io_out_0_bits_WIRE_18
connect _io_out_0_bits_WIRE_2.`5`, _io_out_0_bits_WIRE_17
connect _io_out_0_bits_WIRE.vc_sel, _io_out_0_bits_WIRE_2
connect io.out[0].bits, _io_out_0_bits_WIRE
node _T_8 = bits(chosen, 0, 0)
node _T_9 = and(_T_8, io.out[0].ready)
when _T_9 :
connect io.in[0].ready, UInt<1>(0h1)
node _T_10 = bits(chosen, 1, 1)
node _T_11 = and(_T_10, io.out[0].ready)
when _T_11 :
connect io.in[1].ready, UInt<1>(0h1)
node _T_12 = bits(chosen, 2, 2)
node _T_13 = and(_T_12, io.out[0].ready)
when _T_13 :
connect io.in[2].ready, UInt<1>(0h1)
node _T_14 = or(UInt<3>(0h0), chosen)
node _T_15 = and(io.out[0].ready, io.out[0].valid)
when _T_15 :
node _lock_0_T = not(in_tails)
node _lock_0_T_1 = and(chosen, _lock_0_T)
connect lock_0, _lock_0_T_1
node _T_16 = and(io.out[0].ready, io.out[0].valid)
when _T_16 :
node _mask_T = shr(io.chosen_oh[0], 0)
node _mask_T_1 = shr(io.chosen_oh[0], 1)
node _mask_T_2 = shr(io.chosen_oh[0], 2)
node _mask_T_3 = or(_mask_T, _mask_T_1)
node _mask_T_4 = or(_mask_T_3, _mask_T_2)
connect mask, _mask_T_4
else :
node _mask_T_5 = not(mask)
node _mask_T_6 = eq(_mask_T_5, UInt<1>(0h0))
node _mask_T_7 = shl(mask, 1)
node _mask_T_8 = or(_mask_T_7, UInt<1>(0h1))
node _mask_T_9 = mux(_mask_T_6, UInt<1>(0h0), _mask_T_8)
connect mask, _mask_T_9 | module SwitchArbiter( // @[SwitchAllocator.scala:17:7]
input clock, // @[SwitchAllocator.scala:17:7]
input reset, // @[SwitchAllocator.scala:17:7]
output io_in_0_ready, // @[SwitchAllocator.scala:18:14]
input io_in_0_valid, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_5_0, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_4_0, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_tail, // @[SwitchAllocator.scala:18:14]
output io_in_2_ready, // @[SwitchAllocator.scala:18:14]
input io_in_2_valid, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_5_0, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_4_0, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_tail, // @[SwitchAllocator.scala:18:14]
input io_out_0_ready, // @[SwitchAllocator.scala:18:14]
output io_out_0_valid, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_5_0, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_4_0, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_tail, // @[SwitchAllocator.scala:18:14]
output [2:0] io_chosen_oh_0 // @[SwitchAllocator.scala:18:14]
);
reg [2:0] lock_0; // @[SwitchAllocator.scala:24:38]
wire [2:0] unassigned = {io_in_2_valid, 1'h0, io_in_0_valid} & ~lock_0; // @[SwitchAllocator.scala:17:7, :24:38, :25:{23,52,54}]
reg [2:0] mask; // @[SwitchAllocator.scala:27:21]
wire [2:0] _sel_T_1 = unassigned & ~mask; // @[SwitchAllocator.scala:25:52, :27:21, :30:{58,60}]
wire [5:0] sel = _sel_T_1[0] ? 6'h1 : _sel_T_1[1] ? 6'h2 : _sel_T_1[2] ? 6'h4 : unassigned[0] ? 6'h8 : unassigned[1] ? 6'h10 : {unassigned[2], 5'h0}; // @[OneHot.scala:85:71]
wire [2:0] in_valids = {io_in_2_valid, 1'h0, io_in_0_valid}; // @[SwitchAllocator.scala:17:7, :41:24]
wire [2:0] _chosen_T_2 = in_valids & lock_0; // @[SwitchAllocator.scala:24:38, :41:24, :42:33]
wire [2:0] chosen = (|{_chosen_T_2[2], _chosen_T_2[0]}) ? lock_0 : sel[2:0] | sel[5:3]; // @[Mux.scala:50:70]
wire [2:0] _io_out_0_valid_T = in_valids & chosen; // @[SwitchAllocator.scala:41:24, :42:21, :44:35]
wire [1:0] _GEN = {_io_out_0_valid_T[2], _io_out_0_valid_T[0]}; // @[SwitchAllocator.scala:44:35]
wire _GEN_0 = io_out_0_ready & (|_GEN); // @[Decoupled.scala:51:35]
wire [1:0] _GEN_1 = chosen[1:0] | chosen[2:1]; // @[SwitchAllocator.scala:42:21, :58:{55,71}]
always @(posedge clock) begin // @[SwitchAllocator.scala:17:7]
if (reset) begin // @[SwitchAllocator.scala:17:7]
lock_0 <= 3'h0; // @[SwitchAllocator.scala:24:38]
mask <= 3'h0; // @[SwitchAllocator.scala:27:21]
end
else begin // @[SwitchAllocator.scala:17:7]
if (_GEN_0) // @[Decoupled.scala:51:35]
lock_0 <= chosen & {~io_in_2_bits_tail, 1'h1, ~io_in_0_bits_tail}; // @[SwitchAllocator.scala:17:7, :24:38, :39:21, :42:21, :53:{25,27}]
mask <= _GEN_0 ? {chosen[2], _GEN_1[1], _GEN_1[0] | chosen[2]} : (&mask) ? 3'h0 : {mask[1:0], 1'h1}; // @[Decoupled.scala:51:35]
end
always @(posedge) |
Generate the Verilog code corresponding to this FIRRTL code module AXI4RAM :
input clock : Clock
input reset : Reset
output auto : { flip in : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<29>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { real_last : UInt<1>}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { real_last : UInt<1>}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<29>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { real_last : UInt<1>}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { real_last : UInt<1>}, last : UInt<1>}}}}
wire nodeIn : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<29>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { real_last : UInt<1>}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { real_last : UInt<1>}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<29>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { real_last : UInt<1>}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { real_last : UInt<1>}, last : UInt<1>}}}
invalidate nodeIn.r.bits.last
invalidate nodeIn.r.bits.echo.real_last
invalidate nodeIn.r.bits.resp
invalidate nodeIn.r.bits.data
invalidate nodeIn.r.bits.id
invalidate nodeIn.r.valid
invalidate nodeIn.r.ready
invalidate nodeIn.ar.bits.echo.real_last
invalidate nodeIn.ar.bits.qos
invalidate nodeIn.ar.bits.prot
invalidate nodeIn.ar.bits.cache
invalidate nodeIn.ar.bits.lock
invalidate nodeIn.ar.bits.burst
invalidate nodeIn.ar.bits.size
invalidate nodeIn.ar.bits.len
invalidate nodeIn.ar.bits.addr
invalidate nodeIn.ar.bits.id
invalidate nodeIn.ar.valid
invalidate nodeIn.ar.ready
invalidate nodeIn.b.bits.echo.real_last
invalidate nodeIn.b.bits.resp
invalidate nodeIn.b.bits.id
invalidate nodeIn.b.valid
invalidate nodeIn.b.ready
invalidate nodeIn.w.bits.last
invalidate nodeIn.w.bits.strb
invalidate nodeIn.w.bits.data
invalidate nodeIn.w.valid
invalidate nodeIn.w.ready
invalidate nodeIn.aw.bits.echo.real_last
invalidate nodeIn.aw.bits.qos
invalidate nodeIn.aw.bits.prot
invalidate nodeIn.aw.bits.cache
invalidate nodeIn.aw.bits.lock
invalidate nodeIn.aw.bits.burst
invalidate nodeIn.aw.bits.size
invalidate nodeIn.aw.bits.len
invalidate nodeIn.aw.bits.addr
invalidate nodeIn.aw.bits.id
invalidate nodeIn.aw.valid
invalidate nodeIn.aw.ready
connect nodeIn, auto.in
smem mem : UInt<8>[8] [67108864]
node _r_addr_T = shr(nodeIn.ar.bits.addr, 3)
node _r_addr_T_1 = bits(_r_addr_T, 0, 0)
node _r_addr_T_2 = bits(_r_addr_T, 1, 1)
node _r_addr_T_3 = bits(_r_addr_T, 2, 2)
node _r_addr_T_4 = bits(_r_addr_T, 3, 3)
node _r_addr_T_5 = bits(_r_addr_T, 4, 4)
node _r_addr_T_6 = bits(_r_addr_T, 5, 5)
node _r_addr_T_7 = bits(_r_addr_T, 6, 6)
node _r_addr_T_8 = bits(_r_addr_T, 7, 7)
node _r_addr_T_9 = bits(_r_addr_T, 8, 8)
node _r_addr_T_10 = bits(_r_addr_T, 9, 9)
node _r_addr_T_11 = bits(_r_addr_T, 10, 10)
node _r_addr_T_12 = bits(_r_addr_T, 11, 11)
node _r_addr_T_13 = bits(_r_addr_T, 12, 12)
node _r_addr_T_14 = bits(_r_addr_T, 13, 13)
node _r_addr_T_15 = bits(_r_addr_T, 14, 14)
node _r_addr_T_16 = bits(_r_addr_T, 15, 15)
node _r_addr_T_17 = bits(_r_addr_T, 16, 16)
node _r_addr_T_18 = bits(_r_addr_T, 17, 17)
node _r_addr_T_19 = bits(_r_addr_T, 18, 18)
node _r_addr_T_20 = bits(_r_addr_T, 19, 19)
node _r_addr_T_21 = bits(_r_addr_T, 20, 20)
node _r_addr_T_22 = bits(_r_addr_T, 21, 21)
node _r_addr_T_23 = bits(_r_addr_T, 22, 22)
node _r_addr_T_24 = bits(_r_addr_T, 23, 23)
node _r_addr_T_25 = bits(_r_addr_T, 24, 24)
node _r_addr_T_26 = bits(_r_addr_T, 25, 25)
node r_addr_lo_lo_lo_hi = cat(_r_addr_T_3, _r_addr_T_2)
node r_addr_lo_lo_lo = cat(r_addr_lo_lo_lo_hi, _r_addr_T_1)
node r_addr_lo_lo_hi_hi = cat(_r_addr_T_6, _r_addr_T_5)
node r_addr_lo_lo_hi = cat(r_addr_lo_lo_hi_hi, _r_addr_T_4)
node r_addr_lo_lo = cat(r_addr_lo_lo_hi, r_addr_lo_lo_lo)
node r_addr_lo_hi_lo_hi = cat(_r_addr_T_9, _r_addr_T_8)
node r_addr_lo_hi_lo = cat(r_addr_lo_hi_lo_hi, _r_addr_T_7)
node r_addr_lo_hi_hi_lo = cat(_r_addr_T_11, _r_addr_T_10)
node r_addr_lo_hi_hi_hi = cat(_r_addr_T_13, _r_addr_T_12)
node r_addr_lo_hi_hi = cat(r_addr_lo_hi_hi_hi, r_addr_lo_hi_hi_lo)
node r_addr_lo_hi = cat(r_addr_lo_hi_hi, r_addr_lo_hi_lo)
node r_addr_lo = cat(r_addr_lo_hi, r_addr_lo_lo)
node r_addr_hi_lo_lo_hi = cat(_r_addr_T_16, _r_addr_T_15)
node r_addr_hi_lo_lo = cat(r_addr_hi_lo_lo_hi, _r_addr_T_14)
node r_addr_hi_lo_hi_hi = cat(_r_addr_T_19, _r_addr_T_18)
node r_addr_hi_lo_hi = cat(r_addr_hi_lo_hi_hi, _r_addr_T_17)
node r_addr_hi_lo = cat(r_addr_hi_lo_hi, r_addr_hi_lo_lo)
node r_addr_hi_hi_lo_hi = cat(_r_addr_T_22, _r_addr_T_21)
node r_addr_hi_hi_lo = cat(r_addr_hi_hi_lo_hi, _r_addr_T_20)
node r_addr_hi_hi_hi_lo = cat(_r_addr_T_24, _r_addr_T_23)
node r_addr_hi_hi_hi_hi = cat(_r_addr_T_26, _r_addr_T_25)
node r_addr_hi_hi_hi = cat(r_addr_hi_hi_hi_hi, r_addr_hi_hi_hi_lo)
node r_addr_hi_hi = cat(r_addr_hi_hi_hi, r_addr_hi_hi_lo)
node r_addr_hi = cat(r_addr_hi_hi, r_addr_hi_lo)
node r_addr = cat(r_addr_hi, r_addr_lo)
node _w_addr_T = shr(nodeIn.aw.bits.addr, 3)
node _w_addr_T_1 = bits(_w_addr_T, 0, 0)
node _w_addr_T_2 = bits(_w_addr_T, 1, 1)
node _w_addr_T_3 = bits(_w_addr_T, 2, 2)
node _w_addr_T_4 = bits(_w_addr_T, 3, 3)
node _w_addr_T_5 = bits(_w_addr_T, 4, 4)
node _w_addr_T_6 = bits(_w_addr_T, 5, 5)
node _w_addr_T_7 = bits(_w_addr_T, 6, 6)
node _w_addr_T_8 = bits(_w_addr_T, 7, 7)
node _w_addr_T_9 = bits(_w_addr_T, 8, 8)
node _w_addr_T_10 = bits(_w_addr_T, 9, 9)
node _w_addr_T_11 = bits(_w_addr_T, 10, 10)
node _w_addr_T_12 = bits(_w_addr_T, 11, 11)
node _w_addr_T_13 = bits(_w_addr_T, 12, 12)
node _w_addr_T_14 = bits(_w_addr_T, 13, 13)
node _w_addr_T_15 = bits(_w_addr_T, 14, 14)
node _w_addr_T_16 = bits(_w_addr_T, 15, 15)
node _w_addr_T_17 = bits(_w_addr_T, 16, 16)
node _w_addr_T_18 = bits(_w_addr_T, 17, 17)
node _w_addr_T_19 = bits(_w_addr_T, 18, 18)
node _w_addr_T_20 = bits(_w_addr_T, 19, 19)
node _w_addr_T_21 = bits(_w_addr_T, 20, 20)
node _w_addr_T_22 = bits(_w_addr_T, 21, 21)
node _w_addr_T_23 = bits(_w_addr_T, 22, 22)
node _w_addr_T_24 = bits(_w_addr_T, 23, 23)
node _w_addr_T_25 = bits(_w_addr_T, 24, 24)
node _w_addr_T_26 = bits(_w_addr_T, 25, 25)
node w_addr_lo_lo_lo_hi = cat(_w_addr_T_3, _w_addr_T_2)
node w_addr_lo_lo_lo = cat(w_addr_lo_lo_lo_hi, _w_addr_T_1)
node w_addr_lo_lo_hi_hi = cat(_w_addr_T_6, _w_addr_T_5)
node w_addr_lo_lo_hi = cat(w_addr_lo_lo_hi_hi, _w_addr_T_4)
node w_addr_lo_lo = cat(w_addr_lo_lo_hi, w_addr_lo_lo_lo)
node w_addr_lo_hi_lo_hi = cat(_w_addr_T_9, _w_addr_T_8)
node w_addr_lo_hi_lo = cat(w_addr_lo_hi_lo_hi, _w_addr_T_7)
node w_addr_lo_hi_hi_lo = cat(_w_addr_T_11, _w_addr_T_10)
node w_addr_lo_hi_hi_hi = cat(_w_addr_T_13, _w_addr_T_12)
node w_addr_lo_hi_hi = cat(w_addr_lo_hi_hi_hi, w_addr_lo_hi_hi_lo)
node w_addr_lo_hi = cat(w_addr_lo_hi_hi, w_addr_lo_hi_lo)
node w_addr_lo = cat(w_addr_lo_hi, w_addr_lo_lo)
node w_addr_hi_lo_lo_hi = cat(_w_addr_T_16, _w_addr_T_15)
node w_addr_hi_lo_lo = cat(w_addr_hi_lo_lo_hi, _w_addr_T_14)
node w_addr_hi_lo_hi_hi = cat(_w_addr_T_19, _w_addr_T_18)
node w_addr_hi_lo_hi = cat(w_addr_hi_lo_hi_hi, _w_addr_T_17)
node w_addr_hi_lo = cat(w_addr_hi_lo_hi, w_addr_hi_lo_lo)
node w_addr_hi_hi_lo_hi = cat(_w_addr_T_22, _w_addr_T_21)
node w_addr_hi_hi_lo = cat(w_addr_hi_hi_lo_hi, _w_addr_T_20)
node w_addr_hi_hi_hi_lo = cat(_w_addr_T_24, _w_addr_T_23)
node w_addr_hi_hi_hi_hi = cat(_w_addr_T_26, _w_addr_T_25)
node w_addr_hi_hi_hi = cat(w_addr_hi_hi_hi_hi, w_addr_hi_hi_hi_lo)
node w_addr_hi_hi = cat(w_addr_hi_hi_hi, w_addr_hi_hi_lo)
node w_addr_hi = cat(w_addr_hi_hi, w_addr_hi_lo)
node w_addr = cat(w_addr_hi, w_addr_lo)
node _r_sel0_T = xor(nodeIn.ar.bits.addr, UInt<1>(0h0))
node _r_sel0_T_1 = cvt(_r_sel0_T)
node _r_sel0_T_2 = and(_r_sel0_T_1, asSInt(UInt<30>(0h20000000)))
node _r_sel0_T_3 = asSInt(_r_sel0_T_2)
node r_sel0 = eq(_r_sel0_T_3, asSInt(UInt<1>(0h0)))
node _w_sel0_T = xor(nodeIn.aw.bits.addr, UInt<1>(0h0))
node _w_sel0_T_1 = cvt(_w_sel0_T)
node _w_sel0_T_2 = and(_w_sel0_T_1, asSInt(UInt<30>(0h20000000)))
node _w_sel0_T_3 = asSInt(_w_sel0_T_2)
node w_sel0 = eq(_w_sel0_T_3, asSInt(UInt<1>(0h0)))
regreset w_full : UInt<1>, clock, reset, UInt<1>(0h0)
reg w_id : UInt, clock
reg w_echo : { real_last : UInt<1>}, clock
reg r_sel1 : UInt<1>, clock
connect r_sel1, r_sel0
reg w_sel1 : UInt<1>, clock
connect w_sel1, w_sel0
node _T = and(nodeIn.b.ready, nodeIn.b.valid)
when _T :
connect w_full, UInt<1>(0h0)
node _T_1 = and(nodeIn.aw.ready, nodeIn.aw.valid)
when _T_1 :
connect w_full, UInt<1>(0h1)
node _T_2 = and(nodeIn.aw.ready, nodeIn.aw.valid)
when _T_2 :
connect w_id, nodeIn.aw.bits.id
connect w_sel1, w_sel0
connect w_echo.real_last, nodeIn.aw.bits.echo.real_last
node _wdata_T = bits(nodeIn.w.bits.data, 7, 0)
node _wdata_T_1 = bits(nodeIn.w.bits.data, 15, 8)
node _wdata_T_2 = bits(nodeIn.w.bits.data, 23, 16)
node _wdata_T_3 = bits(nodeIn.w.bits.data, 31, 24)
node _wdata_T_4 = bits(nodeIn.w.bits.data, 39, 32)
node _wdata_T_5 = bits(nodeIn.w.bits.data, 47, 40)
node _wdata_T_6 = bits(nodeIn.w.bits.data, 55, 48)
node _wdata_T_7 = bits(nodeIn.w.bits.data, 63, 56)
wire wdata : UInt<8>[8]
connect wdata[0], _wdata_T
connect wdata[1], _wdata_T_1
connect wdata[2], _wdata_T_2
connect wdata[3], _wdata_T_3
connect wdata[4], _wdata_T_4
connect wdata[5], _wdata_T_5
connect wdata[6], _wdata_T_6
connect wdata[7], _wdata_T_7
node _T_3 = and(nodeIn.aw.ready, nodeIn.aw.valid)
node _T_4 = and(_T_3, w_sel0)
when _T_4 :
node _T_5 = bits(nodeIn.w.bits.strb, 0, 0)
node _T_6 = bits(nodeIn.w.bits.strb, 1, 1)
node _T_7 = bits(nodeIn.w.bits.strb, 2, 2)
node _T_8 = bits(nodeIn.w.bits.strb, 3, 3)
node _T_9 = bits(nodeIn.w.bits.strb, 4, 4)
node _T_10 = bits(nodeIn.w.bits.strb, 5, 5)
node _T_11 = bits(nodeIn.w.bits.strb, 6, 6)
node _T_12 = bits(nodeIn.w.bits.strb, 7, 7)
write mport MPORT = mem[w_addr], clock
when _T_5 :
connect MPORT[0], wdata[0]
when _T_6 :
connect MPORT[1], wdata[1]
when _T_7 :
connect MPORT[2], wdata[2]
when _T_8 :
connect MPORT[3], wdata[3]
when _T_9 :
connect MPORT[4], wdata[4]
when _T_10 :
connect MPORT[5], wdata[5]
when _T_11 :
connect MPORT[6], wdata[6]
when _T_12 :
connect MPORT[7], wdata[7]
connect nodeIn.b.valid, w_full
node _nodeIn_aw_ready_T = eq(w_full, UInt<1>(0h0))
node _nodeIn_aw_ready_T_1 = or(nodeIn.b.ready, _nodeIn_aw_ready_T)
node _nodeIn_aw_ready_T_2 = and(nodeIn.w.valid, _nodeIn_aw_ready_T_1)
connect nodeIn.aw.ready, _nodeIn_aw_ready_T_2
node _nodeIn_w_ready_T = eq(w_full, UInt<1>(0h0))
node _nodeIn_w_ready_T_1 = or(nodeIn.b.ready, _nodeIn_w_ready_T)
node _nodeIn_w_ready_T_2 = and(nodeIn.aw.valid, _nodeIn_w_ready_T_1)
connect nodeIn.w.ready, _nodeIn_w_ready_T_2
connect nodeIn.b.bits.id, w_id
node _nodeIn_b_bits_resp_T = mux(w_sel1, UInt<2>(0h0), UInt<2>(0h3))
connect nodeIn.b.bits.resp, _nodeIn_b_bits_resp_T
connect nodeIn.b.bits.echo.real_last, w_echo.real_last
regreset r_full : UInt<1>, clock, reset, UInt<1>(0h0)
reg r_id : UInt, clock
reg r_echo : { real_last : UInt<1>}, clock
node _T_13 = and(nodeIn.r.ready, nodeIn.r.valid)
when _T_13 :
connect r_full, UInt<1>(0h0)
node _T_14 = and(nodeIn.ar.ready, nodeIn.ar.valid)
when _T_14 :
connect r_full, UInt<1>(0h1)
node _T_15 = and(nodeIn.ar.ready, nodeIn.ar.valid)
when _T_15 :
connect r_id, nodeIn.ar.bits.id
connect r_sel1, r_sel0
connect r_echo.real_last, nodeIn.ar.bits.echo.real_last
node ren = and(nodeIn.ar.ready, nodeIn.ar.valid)
wire _rdata_WIRE : UInt<26>
invalidate _rdata_WIRE
when ren :
connect _rdata_WIRE, r_addr
read mport rdata_MPORT = mem[_rdata_WIRE], clock
reg rdata_REG : UInt<1>, clock
connect rdata_REG, ren
reg rdata_r : UInt<8>[8], clock
when rdata_REG :
connect rdata_r, rdata_MPORT
node rdata = mux(rdata_REG, rdata_MPORT, rdata_r)
connect nodeIn.r.valid, r_full
node _nodeIn_ar_ready_T = eq(r_full, UInt<1>(0h0))
node _nodeIn_ar_ready_T_1 = or(nodeIn.r.ready, _nodeIn_ar_ready_T)
connect nodeIn.ar.ready, _nodeIn_ar_ready_T_1
connect nodeIn.r.bits.id, r_id
node _nodeIn_r_bits_resp_T = mux(UInt<1>(0h0), UInt<2>(0h2), UInt<2>(0h0))
node _nodeIn_r_bits_resp_T_1 = mux(r_sel1, _nodeIn_r_bits_resp_T, UInt<2>(0h3))
connect nodeIn.r.bits.resp, _nodeIn_r_bits_resp_T_1
node nodeIn_r_bits_data_lo_lo = cat(rdata[1], rdata[0])
node nodeIn_r_bits_data_lo_hi = cat(rdata[3], rdata[2])
node nodeIn_r_bits_data_lo = cat(nodeIn_r_bits_data_lo_hi, nodeIn_r_bits_data_lo_lo)
node nodeIn_r_bits_data_hi_lo = cat(rdata[5], rdata[4])
node nodeIn_r_bits_data_hi_hi = cat(rdata[7], rdata[6])
node nodeIn_r_bits_data_hi = cat(nodeIn_r_bits_data_hi_hi, nodeIn_r_bits_data_hi_lo)
node _nodeIn_r_bits_data_T = cat(nodeIn_r_bits_data_hi, nodeIn_r_bits_data_lo)
connect nodeIn.r.bits.data, _nodeIn_r_bits_data_T
connect nodeIn.r.bits.echo.real_last, r_echo.real_last
connect nodeIn.r.bits.last, UInt<1>(0h1) | module AXI4RAM( // @[SRAM.scala:58:9]
input clock, // @[SRAM.scala:58:9]
input reset, // @[SRAM.scala:58:9]
output auto_in_aw_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_aw_valid, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_aw_bits_id, // @[LazyModuleImp.scala:107:25]
input [28:0] auto_in_aw_bits_addr, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_aw_bits_len, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_aw_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_aw_bits_burst, // @[LazyModuleImp.scala:107:25]
input auto_in_aw_bits_lock, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_aw_bits_cache, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_aw_bits_prot, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_aw_bits_qos, // @[LazyModuleImp.scala:107:25]
input auto_in_aw_bits_echo_real_last, // @[LazyModuleImp.scala:107:25]
output auto_in_w_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_w_valid, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_w_bits_data, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_w_bits_strb, // @[LazyModuleImp.scala:107:25]
input auto_in_w_bits_last, // @[LazyModuleImp.scala:107:25]
input auto_in_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_b_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_b_bits_id, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_bits_resp, // @[LazyModuleImp.scala:107:25]
output auto_in_b_bits_echo_real_last, // @[LazyModuleImp.scala:107:25]
output auto_in_ar_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_ar_valid, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_ar_bits_id, // @[LazyModuleImp.scala:107:25]
input [28:0] auto_in_ar_bits_addr, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_ar_bits_len, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_ar_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_ar_bits_burst, // @[LazyModuleImp.scala:107:25]
input auto_in_ar_bits_lock, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_ar_bits_cache, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_ar_bits_prot, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_ar_bits_qos, // @[LazyModuleImp.scala:107:25]
input auto_in_ar_bits_echo_real_last, // @[LazyModuleImp.scala:107:25]
input auto_in_r_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_r_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_r_bits_id, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_r_bits_data, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_r_bits_resp, // @[LazyModuleImp.scala:107:25]
output auto_in_r_bits_echo_real_last // @[LazyModuleImp.scala:107:25]
);
wire [63:0] _mem_R0_data; // @[DescribedSRAM.scala:17:26]
wire auto_in_aw_valid_0 = auto_in_aw_valid; // @[SRAM.scala:58:9]
wire [3:0] auto_in_aw_bits_id_0 = auto_in_aw_bits_id; // @[SRAM.scala:58:9]
wire [28:0] auto_in_aw_bits_addr_0 = auto_in_aw_bits_addr; // @[SRAM.scala:58:9]
wire [7:0] auto_in_aw_bits_len_0 = auto_in_aw_bits_len; // @[SRAM.scala:58:9]
wire [2:0] auto_in_aw_bits_size_0 = auto_in_aw_bits_size; // @[SRAM.scala:58:9]
wire [1:0] auto_in_aw_bits_burst_0 = auto_in_aw_bits_burst; // @[SRAM.scala:58:9]
wire auto_in_aw_bits_lock_0 = auto_in_aw_bits_lock; // @[SRAM.scala:58:9]
wire [3:0] auto_in_aw_bits_cache_0 = auto_in_aw_bits_cache; // @[SRAM.scala:58:9]
wire [2:0] auto_in_aw_bits_prot_0 = auto_in_aw_bits_prot; // @[SRAM.scala:58:9]
wire [3:0] auto_in_aw_bits_qos_0 = auto_in_aw_bits_qos; // @[SRAM.scala:58:9]
wire auto_in_aw_bits_echo_real_last_0 = auto_in_aw_bits_echo_real_last; // @[SRAM.scala:58:9]
wire auto_in_w_valid_0 = auto_in_w_valid; // @[SRAM.scala:58:9]
wire [63:0] auto_in_w_bits_data_0 = auto_in_w_bits_data; // @[SRAM.scala:58:9]
wire [7:0] auto_in_w_bits_strb_0 = auto_in_w_bits_strb; // @[SRAM.scala:58:9]
wire auto_in_w_bits_last_0 = auto_in_w_bits_last; // @[SRAM.scala:58:9]
wire auto_in_b_ready_0 = auto_in_b_ready; // @[SRAM.scala:58:9]
wire auto_in_ar_valid_0 = auto_in_ar_valid; // @[SRAM.scala:58:9]
wire [3:0] auto_in_ar_bits_id_0 = auto_in_ar_bits_id; // @[SRAM.scala:58:9]
wire [28:0] auto_in_ar_bits_addr_0 = auto_in_ar_bits_addr; // @[SRAM.scala:58:9]
wire [7:0] auto_in_ar_bits_len_0 = auto_in_ar_bits_len; // @[SRAM.scala:58:9]
wire [2:0] auto_in_ar_bits_size_0 = auto_in_ar_bits_size; // @[SRAM.scala:58:9]
wire [1:0] auto_in_ar_bits_burst_0 = auto_in_ar_bits_burst; // @[SRAM.scala:58:9]
wire auto_in_ar_bits_lock_0 = auto_in_ar_bits_lock; // @[SRAM.scala:58:9]
wire [3:0] auto_in_ar_bits_cache_0 = auto_in_ar_bits_cache; // @[SRAM.scala:58:9]
wire [2:0] auto_in_ar_bits_prot_0 = auto_in_ar_bits_prot; // @[SRAM.scala:58:9]
wire [3:0] auto_in_ar_bits_qos_0 = auto_in_ar_bits_qos; // @[SRAM.scala:58:9]
wire auto_in_ar_bits_echo_real_last_0 = auto_in_ar_bits_echo_real_last; // @[SRAM.scala:58:9]
wire auto_in_r_ready_0 = auto_in_r_ready; // @[SRAM.scala:58:9]
wire [1:0] _nodeIn_r_bits_resp_T = 2'h0; // @[SRAM.scala:125:38]
wire auto_in_r_bits_last = 1'h1; // @[SRAM.scala:58:9]
wire nodeIn_aw_ready; // @[MixedNode.scala:551:17]
wire nodeIn_r_bits_last = 1'h1; // @[MixedNode.scala:551:17]
wire nodeIn_aw_valid = auto_in_aw_valid_0; // @[SRAM.scala:58:9]
wire [3:0] nodeIn_aw_bits_id = auto_in_aw_bits_id_0; // @[SRAM.scala:58:9]
wire [28:0] nodeIn_aw_bits_addr = auto_in_aw_bits_addr_0; // @[SRAM.scala:58:9]
wire [7:0] nodeIn_aw_bits_len = auto_in_aw_bits_len_0; // @[SRAM.scala:58:9]
wire [2:0] nodeIn_aw_bits_size = auto_in_aw_bits_size_0; // @[SRAM.scala:58:9]
wire [1:0] nodeIn_aw_bits_burst = auto_in_aw_bits_burst_0; // @[SRAM.scala:58:9]
wire nodeIn_aw_bits_lock = auto_in_aw_bits_lock_0; // @[SRAM.scala:58:9]
wire [3:0] nodeIn_aw_bits_cache = auto_in_aw_bits_cache_0; // @[SRAM.scala:58:9]
wire [2:0] nodeIn_aw_bits_prot = auto_in_aw_bits_prot_0; // @[SRAM.scala:58:9]
wire [3:0] nodeIn_aw_bits_qos = auto_in_aw_bits_qos_0; // @[SRAM.scala:58:9]
wire nodeIn_aw_bits_echo_real_last = auto_in_aw_bits_echo_real_last_0; // @[SRAM.scala:58:9]
wire nodeIn_w_ready; // @[MixedNode.scala:551:17]
wire nodeIn_w_valid = auto_in_w_valid_0; // @[SRAM.scala:58:9]
wire [63:0] nodeIn_w_bits_data = auto_in_w_bits_data_0; // @[SRAM.scala:58:9]
wire [7:0] nodeIn_w_bits_strb = auto_in_w_bits_strb_0; // @[SRAM.scala:58:9]
wire nodeIn_w_bits_last = auto_in_w_bits_last_0; // @[SRAM.scala:58:9]
wire nodeIn_b_ready = auto_in_b_ready_0; // @[SRAM.scala:58:9]
wire nodeIn_b_valid; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_b_bits_id; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_bits_resp; // @[MixedNode.scala:551:17]
wire nodeIn_b_bits_echo_real_last; // @[MixedNode.scala:551:17]
wire nodeIn_ar_ready; // @[MixedNode.scala:551:17]
wire nodeIn_ar_valid = auto_in_ar_valid_0; // @[SRAM.scala:58:9]
wire [3:0] nodeIn_ar_bits_id = auto_in_ar_bits_id_0; // @[SRAM.scala:58:9]
wire [28:0] nodeIn_ar_bits_addr = auto_in_ar_bits_addr_0; // @[SRAM.scala:58:9]
wire [7:0] nodeIn_ar_bits_len = auto_in_ar_bits_len_0; // @[SRAM.scala:58:9]
wire [2:0] nodeIn_ar_bits_size = auto_in_ar_bits_size_0; // @[SRAM.scala:58:9]
wire [1:0] nodeIn_ar_bits_burst = auto_in_ar_bits_burst_0; // @[SRAM.scala:58:9]
wire nodeIn_ar_bits_lock = auto_in_ar_bits_lock_0; // @[SRAM.scala:58:9]
wire [3:0] nodeIn_ar_bits_cache = auto_in_ar_bits_cache_0; // @[SRAM.scala:58:9]
wire [2:0] nodeIn_ar_bits_prot = auto_in_ar_bits_prot_0; // @[SRAM.scala:58:9]
wire [3:0] nodeIn_ar_bits_qos = auto_in_ar_bits_qos_0; // @[SRAM.scala:58:9]
wire nodeIn_ar_bits_echo_real_last = auto_in_ar_bits_echo_real_last_0; // @[SRAM.scala:58:9]
wire nodeIn_r_ready = auto_in_r_ready_0; // @[SRAM.scala:58:9]
wire nodeIn_r_valid; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_r_bits_id; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_r_bits_data; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_r_bits_resp; // @[MixedNode.scala:551:17]
wire nodeIn_r_bits_echo_real_last; // @[MixedNode.scala:551:17]
wire auto_in_aw_ready_0; // @[SRAM.scala:58:9]
wire auto_in_w_ready_0; // @[SRAM.scala:58:9]
wire auto_in_b_bits_echo_real_last_0; // @[SRAM.scala:58:9]
wire [3:0] auto_in_b_bits_id_0; // @[SRAM.scala:58:9]
wire [1:0] auto_in_b_bits_resp_0; // @[SRAM.scala:58:9]
wire auto_in_b_valid_0; // @[SRAM.scala:58:9]
wire auto_in_ar_ready_0; // @[SRAM.scala:58:9]
wire auto_in_r_bits_echo_real_last_0; // @[SRAM.scala:58:9]
wire [3:0] auto_in_r_bits_id_0; // @[SRAM.scala:58:9]
wire [63:0] auto_in_r_bits_data_0; // @[SRAM.scala:58:9]
wire [1:0] auto_in_r_bits_resp_0; // @[SRAM.scala:58:9]
wire auto_in_r_valid_0; // @[SRAM.scala:58:9]
wire _nodeIn_aw_ready_T_2; // @[SRAM.scala:97:32]
assign auto_in_aw_ready_0 = nodeIn_aw_ready; // @[SRAM.scala:58:9]
wire [28:0] _w_sel0_T = nodeIn_aw_bits_addr; // @[Parameters.scala:137:31]
wire _nodeIn_w_ready_T_2; // @[SRAM.scala:98:32]
assign auto_in_w_ready_0 = nodeIn_w_ready; // @[SRAM.scala:58:9]
assign auto_in_b_valid_0 = nodeIn_b_valid; // @[SRAM.scala:58:9]
assign auto_in_b_bits_id_0 = nodeIn_b_bits_id; // @[SRAM.scala:58:9]
wire [1:0] _nodeIn_b_bits_resp_T; // @[SRAM.scala:101:26]
assign auto_in_b_bits_resp_0 = nodeIn_b_bits_resp; // @[SRAM.scala:58:9]
assign auto_in_b_bits_echo_real_last_0 = nodeIn_b_bits_echo_real_last; // @[SRAM.scala:58:9]
wire _nodeIn_ar_ready_T_1; // @[SRAM.scala:122:31]
assign auto_in_ar_ready_0 = nodeIn_ar_ready; // @[SRAM.scala:58:9]
wire [28:0] _r_sel0_T = nodeIn_ar_bits_addr; // @[Parameters.scala:137:31]
assign auto_in_r_valid_0 = nodeIn_r_valid; // @[SRAM.scala:58:9]
assign auto_in_r_bits_id_0 = nodeIn_r_bits_id; // @[SRAM.scala:58:9]
wire [63:0] _nodeIn_r_bits_data_T; // @[SRAM.scala:126:26]
assign auto_in_r_bits_data_0 = nodeIn_r_bits_data; // @[SRAM.scala:58:9]
wire [1:0] _nodeIn_r_bits_resp_T_1; // @[SRAM.scala:125:26]
assign auto_in_r_bits_resp_0 = nodeIn_r_bits_resp; // @[SRAM.scala:58:9]
assign auto_in_r_bits_echo_real_last_0 = nodeIn_r_bits_echo_real_last; // @[SRAM.scala:58:9]
wire [7:0] wdata_0; // @[SRAM.scala:90:45]
wire [7:0] wdata_1; // @[SRAM.scala:90:45]
wire [7:0] wdata_2; // @[SRAM.scala:90:45]
wire [7:0] wdata_3; // @[SRAM.scala:90:45]
wire [7:0] wdata_4; // @[SRAM.scala:90:45]
wire [7:0] wdata_5; // @[SRAM.scala:90:45]
wire [7:0] wdata_6; // @[SRAM.scala:90:45]
wire [7:0] wdata_7; // @[SRAM.scala:90:45]
wire [25:0] _r_addr_T = nodeIn_ar_bits_addr[28:3]; // @[SRAM.scala:70:49]
wire _r_addr_T_1 = _r_addr_T[0]; // @[SRAM.scala:70:{49,73}]
wire _r_addr_T_2 = _r_addr_T[1]; // @[SRAM.scala:70:{49,73}]
wire _r_addr_T_3 = _r_addr_T[2]; // @[SRAM.scala:70:{49,73}]
wire _r_addr_T_4 = _r_addr_T[3]; // @[SRAM.scala:70:{49,73}]
wire _r_addr_T_5 = _r_addr_T[4]; // @[SRAM.scala:70:{49,73}]
wire _r_addr_T_6 = _r_addr_T[5]; // @[SRAM.scala:70:{49,73}]
wire _r_addr_T_7 = _r_addr_T[6]; // @[SRAM.scala:70:{49,73}]
wire _r_addr_T_8 = _r_addr_T[7]; // @[SRAM.scala:70:{49,73}]
wire _r_addr_T_9 = _r_addr_T[8]; // @[SRAM.scala:70:{49,73}]
wire _r_addr_T_10 = _r_addr_T[9]; // @[SRAM.scala:70:{49,73}]
wire _r_addr_T_11 = _r_addr_T[10]; // @[SRAM.scala:70:{49,73}]
wire _r_addr_T_12 = _r_addr_T[11]; // @[SRAM.scala:70:{49,73}]
wire _r_addr_T_13 = _r_addr_T[12]; // @[SRAM.scala:70:{49,73}]
wire _r_addr_T_14 = _r_addr_T[13]; // @[SRAM.scala:70:{49,73}]
wire _r_addr_T_15 = _r_addr_T[14]; // @[SRAM.scala:70:{49,73}]
wire _r_addr_T_16 = _r_addr_T[15]; // @[SRAM.scala:70:{49,73}]
wire _r_addr_T_17 = _r_addr_T[16]; // @[SRAM.scala:70:{49,73}]
wire _r_addr_T_18 = _r_addr_T[17]; // @[SRAM.scala:70:{49,73}]
wire _r_addr_T_19 = _r_addr_T[18]; // @[SRAM.scala:70:{49,73}]
wire _r_addr_T_20 = _r_addr_T[19]; // @[SRAM.scala:70:{49,73}]
wire _r_addr_T_21 = _r_addr_T[20]; // @[SRAM.scala:70:{49,73}]
wire _r_addr_T_22 = _r_addr_T[21]; // @[SRAM.scala:70:{49,73}]
wire _r_addr_T_23 = _r_addr_T[22]; // @[SRAM.scala:70:{49,73}]
wire _r_addr_T_24 = _r_addr_T[23]; // @[SRAM.scala:70:{49,73}]
wire _r_addr_T_25 = _r_addr_T[24]; // @[SRAM.scala:70:{49,73}]
wire _r_addr_T_26 = _r_addr_T[25]; // @[SRAM.scala:70:{49,73}]
wire [1:0] r_addr_lo_lo_lo_hi = {_r_addr_T_3, _r_addr_T_2}; // @[SRAM.scala:70:{21,73}]
wire [2:0] r_addr_lo_lo_lo = {r_addr_lo_lo_lo_hi, _r_addr_T_1}; // @[SRAM.scala:70:{21,73}]
wire [1:0] r_addr_lo_lo_hi_hi = {_r_addr_T_6, _r_addr_T_5}; // @[SRAM.scala:70:{21,73}]
wire [2:0] r_addr_lo_lo_hi = {r_addr_lo_lo_hi_hi, _r_addr_T_4}; // @[SRAM.scala:70:{21,73}]
wire [5:0] r_addr_lo_lo = {r_addr_lo_lo_hi, r_addr_lo_lo_lo}; // @[SRAM.scala:70:21]
wire [1:0] r_addr_lo_hi_lo_hi = {_r_addr_T_9, _r_addr_T_8}; // @[SRAM.scala:70:{21,73}]
wire [2:0] r_addr_lo_hi_lo = {r_addr_lo_hi_lo_hi, _r_addr_T_7}; // @[SRAM.scala:70:{21,73}]
wire [1:0] r_addr_lo_hi_hi_lo = {_r_addr_T_11, _r_addr_T_10}; // @[SRAM.scala:70:{21,73}]
wire [1:0] r_addr_lo_hi_hi_hi = {_r_addr_T_13, _r_addr_T_12}; // @[SRAM.scala:70:{21,73}]
wire [3:0] r_addr_lo_hi_hi = {r_addr_lo_hi_hi_hi, r_addr_lo_hi_hi_lo}; // @[SRAM.scala:70:21]
wire [6:0] r_addr_lo_hi = {r_addr_lo_hi_hi, r_addr_lo_hi_lo}; // @[SRAM.scala:70:21]
wire [12:0] r_addr_lo = {r_addr_lo_hi, r_addr_lo_lo}; // @[SRAM.scala:70:21]
wire [1:0] r_addr_hi_lo_lo_hi = {_r_addr_T_16, _r_addr_T_15}; // @[SRAM.scala:70:{21,73}]
wire [2:0] r_addr_hi_lo_lo = {r_addr_hi_lo_lo_hi, _r_addr_T_14}; // @[SRAM.scala:70:{21,73}]
wire [1:0] r_addr_hi_lo_hi_hi = {_r_addr_T_19, _r_addr_T_18}; // @[SRAM.scala:70:{21,73}]
wire [2:0] r_addr_hi_lo_hi = {r_addr_hi_lo_hi_hi, _r_addr_T_17}; // @[SRAM.scala:70:{21,73}]
wire [5:0] r_addr_hi_lo = {r_addr_hi_lo_hi, r_addr_hi_lo_lo}; // @[SRAM.scala:70:21]
wire [1:0] r_addr_hi_hi_lo_hi = {_r_addr_T_22, _r_addr_T_21}; // @[SRAM.scala:70:{21,73}]
wire [2:0] r_addr_hi_hi_lo = {r_addr_hi_hi_lo_hi, _r_addr_T_20}; // @[SRAM.scala:70:{21,73}]
wire [1:0] r_addr_hi_hi_hi_lo = {_r_addr_T_24, _r_addr_T_23}; // @[SRAM.scala:70:{21,73}]
wire [1:0] r_addr_hi_hi_hi_hi = {_r_addr_T_26, _r_addr_T_25}; // @[SRAM.scala:70:{21,73}]
wire [3:0] r_addr_hi_hi_hi = {r_addr_hi_hi_hi_hi, r_addr_hi_hi_hi_lo}; // @[SRAM.scala:70:21]
wire [6:0] r_addr_hi_hi = {r_addr_hi_hi_hi, r_addr_hi_hi_lo}; // @[SRAM.scala:70:21]
wire [12:0] r_addr_hi = {r_addr_hi_hi, r_addr_hi_lo}; // @[SRAM.scala:70:21]
wire [25:0] r_addr = {r_addr_hi, r_addr_lo}; // @[SRAM.scala:70:21]
wire [25:0] _rdata_WIRE = r_addr; // @[package.scala:100:58]
wire [25:0] _w_addr_T = nodeIn_aw_bits_addr[28:3]; // @[SRAM.scala:71:49]
wire _w_addr_T_1 = _w_addr_T[0]; // @[SRAM.scala:71:{49,73}]
wire _w_addr_T_2 = _w_addr_T[1]; // @[SRAM.scala:71:{49,73}]
wire _w_addr_T_3 = _w_addr_T[2]; // @[SRAM.scala:71:{49,73}]
wire _w_addr_T_4 = _w_addr_T[3]; // @[SRAM.scala:71:{49,73}]
wire _w_addr_T_5 = _w_addr_T[4]; // @[SRAM.scala:71:{49,73}]
wire _w_addr_T_6 = _w_addr_T[5]; // @[SRAM.scala:71:{49,73}]
wire _w_addr_T_7 = _w_addr_T[6]; // @[SRAM.scala:71:{49,73}]
wire _w_addr_T_8 = _w_addr_T[7]; // @[SRAM.scala:71:{49,73}]
wire _w_addr_T_9 = _w_addr_T[8]; // @[SRAM.scala:71:{49,73}]
wire _w_addr_T_10 = _w_addr_T[9]; // @[SRAM.scala:71:{49,73}]
wire _w_addr_T_11 = _w_addr_T[10]; // @[SRAM.scala:71:{49,73}]
wire _w_addr_T_12 = _w_addr_T[11]; // @[SRAM.scala:71:{49,73}]
wire _w_addr_T_13 = _w_addr_T[12]; // @[SRAM.scala:71:{49,73}]
wire _w_addr_T_14 = _w_addr_T[13]; // @[SRAM.scala:71:{49,73}]
wire _w_addr_T_15 = _w_addr_T[14]; // @[SRAM.scala:71:{49,73}]
wire _w_addr_T_16 = _w_addr_T[15]; // @[SRAM.scala:71:{49,73}]
wire _w_addr_T_17 = _w_addr_T[16]; // @[SRAM.scala:71:{49,73}]
wire _w_addr_T_18 = _w_addr_T[17]; // @[SRAM.scala:71:{49,73}]
wire _w_addr_T_19 = _w_addr_T[18]; // @[SRAM.scala:71:{49,73}]
wire _w_addr_T_20 = _w_addr_T[19]; // @[SRAM.scala:71:{49,73}]
wire _w_addr_T_21 = _w_addr_T[20]; // @[SRAM.scala:71:{49,73}]
wire _w_addr_T_22 = _w_addr_T[21]; // @[SRAM.scala:71:{49,73}]
wire _w_addr_T_23 = _w_addr_T[22]; // @[SRAM.scala:71:{49,73}]
wire _w_addr_T_24 = _w_addr_T[23]; // @[SRAM.scala:71:{49,73}]
wire _w_addr_T_25 = _w_addr_T[24]; // @[SRAM.scala:71:{49,73}]
wire _w_addr_T_26 = _w_addr_T[25]; // @[SRAM.scala:71:{49,73}]
wire [1:0] w_addr_lo_lo_lo_hi = {_w_addr_T_3, _w_addr_T_2}; // @[SRAM.scala:71:{21,73}]
wire [2:0] w_addr_lo_lo_lo = {w_addr_lo_lo_lo_hi, _w_addr_T_1}; // @[SRAM.scala:71:{21,73}]
wire [1:0] w_addr_lo_lo_hi_hi = {_w_addr_T_6, _w_addr_T_5}; // @[SRAM.scala:71:{21,73}]
wire [2:0] w_addr_lo_lo_hi = {w_addr_lo_lo_hi_hi, _w_addr_T_4}; // @[SRAM.scala:71:{21,73}]
wire [5:0] w_addr_lo_lo = {w_addr_lo_lo_hi, w_addr_lo_lo_lo}; // @[SRAM.scala:71:21]
wire [1:0] w_addr_lo_hi_lo_hi = {_w_addr_T_9, _w_addr_T_8}; // @[SRAM.scala:71:{21,73}]
wire [2:0] w_addr_lo_hi_lo = {w_addr_lo_hi_lo_hi, _w_addr_T_7}; // @[SRAM.scala:71:{21,73}]
wire [1:0] w_addr_lo_hi_hi_lo = {_w_addr_T_11, _w_addr_T_10}; // @[SRAM.scala:71:{21,73}]
wire [1:0] w_addr_lo_hi_hi_hi = {_w_addr_T_13, _w_addr_T_12}; // @[SRAM.scala:71:{21,73}]
wire [3:0] w_addr_lo_hi_hi = {w_addr_lo_hi_hi_hi, w_addr_lo_hi_hi_lo}; // @[SRAM.scala:71:21]
wire [6:0] w_addr_lo_hi = {w_addr_lo_hi_hi, w_addr_lo_hi_lo}; // @[SRAM.scala:71:21]
wire [12:0] w_addr_lo = {w_addr_lo_hi, w_addr_lo_lo}; // @[SRAM.scala:71:21]
wire [1:0] w_addr_hi_lo_lo_hi = {_w_addr_T_16, _w_addr_T_15}; // @[SRAM.scala:71:{21,73}]
wire [2:0] w_addr_hi_lo_lo = {w_addr_hi_lo_lo_hi, _w_addr_T_14}; // @[SRAM.scala:71:{21,73}]
wire [1:0] w_addr_hi_lo_hi_hi = {_w_addr_T_19, _w_addr_T_18}; // @[SRAM.scala:71:{21,73}]
wire [2:0] w_addr_hi_lo_hi = {w_addr_hi_lo_hi_hi, _w_addr_T_17}; // @[SRAM.scala:71:{21,73}]
wire [5:0] w_addr_hi_lo = {w_addr_hi_lo_hi, w_addr_hi_lo_lo}; // @[SRAM.scala:71:21]
wire [1:0] w_addr_hi_hi_lo_hi = {_w_addr_T_22, _w_addr_T_21}; // @[SRAM.scala:71:{21,73}]
wire [2:0] w_addr_hi_hi_lo = {w_addr_hi_hi_lo_hi, _w_addr_T_20}; // @[SRAM.scala:71:{21,73}]
wire [1:0] w_addr_hi_hi_hi_lo = {_w_addr_T_24, _w_addr_T_23}; // @[SRAM.scala:71:{21,73}]
wire [1:0] w_addr_hi_hi_hi_hi = {_w_addr_T_26, _w_addr_T_25}; // @[SRAM.scala:71:{21,73}]
wire [3:0] w_addr_hi_hi_hi = {w_addr_hi_hi_hi_hi, w_addr_hi_hi_hi_lo}; // @[SRAM.scala:71:21]
wire [6:0] w_addr_hi_hi = {w_addr_hi_hi_hi, w_addr_hi_hi_lo}; // @[SRAM.scala:71:21]
wire [12:0] w_addr_hi = {w_addr_hi_hi, w_addr_hi_lo}; // @[SRAM.scala:71:21]
wire [25:0] w_addr = {w_addr_hi, w_addr_lo}; // @[SRAM.scala:71:21]
wire [29:0] _r_sel0_T_1 = {1'h0, _r_sel0_T}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _r_sel0_T_2 = _r_sel0_T_1 & 30'h20000000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _r_sel0_T_3 = _r_sel0_T_2; // @[Parameters.scala:137:46]
wire r_sel0 = _r_sel0_T_3 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [29:0] _w_sel0_T_1 = {1'h0, _w_sel0_T}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _w_sel0_T_2 = _w_sel0_T_1 & 30'h20000000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _w_sel0_T_3 = _w_sel0_T_2; // @[Parameters.scala:137:46]
wire w_sel0 = _w_sel0_T_3 == 30'h0; // @[Parameters.scala:137:{46,59}]
reg w_full; // @[SRAM.scala:75:25]
assign nodeIn_b_valid = w_full; // @[SRAM.scala:75:25]
reg [3:0] w_id; // @[SRAM.scala:76:21]
assign nodeIn_b_bits_id = w_id; // @[SRAM.scala:76:21]
reg w_echo_real_last; // @[SRAM.scala:77:21]
assign nodeIn_b_bits_echo_real_last = w_echo_real_last; // @[SRAM.scala:77:21]
reg r_sel1; // @[SRAM.scala:78:25]
reg w_sel1; // @[SRAM.scala:79:25]
wire _T_3 = nodeIn_aw_ready & nodeIn_aw_valid; // @[Decoupled.scala:51:35]
wire [7:0] _wdata_T = nodeIn_w_bits_data[7:0]; // @[SRAM.scala:90:66]
assign wdata_0 = _wdata_T; // @[SRAM.scala:90:{45,66}]
wire [7:0] _wdata_T_1 = nodeIn_w_bits_data[15:8]; // @[SRAM.scala:90:66]
assign wdata_1 = _wdata_T_1; // @[SRAM.scala:90:{45,66}]
wire [7:0] _wdata_T_2 = nodeIn_w_bits_data[23:16]; // @[SRAM.scala:90:66]
assign wdata_2 = _wdata_T_2; // @[SRAM.scala:90:{45,66}]
wire [7:0] _wdata_T_3 = nodeIn_w_bits_data[31:24]; // @[SRAM.scala:90:66]
assign wdata_3 = _wdata_T_3; // @[SRAM.scala:90:{45,66}]
wire [7:0] _wdata_T_4 = nodeIn_w_bits_data[39:32]; // @[SRAM.scala:90:66]
assign wdata_4 = _wdata_T_4; // @[SRAM.scala:90:{45,66}]
wire [7:0] _wdata_T_5 = nodeIn_w_bits_data[47:40]; // @[SRAM.scala:90:66]
assign wdata_5 = _wdata_T_5; // @[SRAM.scala:90:{45,66}]
wire [7:0] _wdata_T_6 = nodeIn_w_bits_data[55:48]; // @[SRAM.scala:90:66]
assign wdata_6 = _wdata_T_6; // @[SRAM.scala:90:{45,66}]
wire [7:0] _wdata_T_7 = nodeIn_w_bits_data[63:56]; // @[SRAM.scala:90:66]
assign wdata_7 = _wdata_T_7; // @[SRAM.scala:90:{45,66}]
wire _nodeIn_aw_ready_T = ~w_full; // @[SRAM.scala:75:25, :97:50]
wire _nodeIn_aw_ready_T_1 = nodeIn_b_ready | _nodeIn_aw_ready_T; // @[SRAM.scala:97:{47,50}]
assign _nodeIn_aw_ready_T_2 = nodeIn_w_valid & _nodeIn_aw_ready_T_1; // @[SRAM.scala:97:{32,47}]
assign nodeIn_aw_ready = _nodeIn_aw_ready_T_2; // @[SRAM.scala:97:32]
wire _nodeIn_w_ready_T = ~w_full; // @[SRAM.scala:75:25, :97:50, :98:50]
wire _nodeIn_w_ready_T_1 = nodeIn_b_ready | _nodeIn_w_ready_T; // @[SRAM.scala:98:{47,50}]
assign _nodeIn_w_ready_T_2 = nodeIn_aw_valid & _nodeIn_w_ready_T_1; // @[SRAM.scala:98:{32,47}]
assign nodeIn_w_ready = _nodeIn_w_ready_T_2; // @[SRAM.scala:98:32]
assign _nodeIn_b_bits_resp_T = w_sel1 ? 2'h0 : 2'h3; // @[SRAM.scala:79:25, :101:26]
assign nodeIn_b_bits_resp = _nodeIn_b_bits_resp_T; // @[SRAM.scala:101:26]
reg r_full; // @[SRAM.scala:104:25]
assign nodeIn_r_valid = r_full; // @[SRAM.scala:104:25]
reg [3:0] r_id; // @[SRAM.scala:105:21]
assign nodeIn_r_bits_id = r_id; // @[SRAM.scala:105:21]
reg r_echo_real_last; // @[SRAM.scala:106:21]
assign nodeIn_r_bits_echo_real_last = r_echo_real_last; // @[SRAM.scala:106:21]
wire ren = nodeIn_ar_ready & nodeIn_ar_valid; // @[Decoupled.scala:51:35]
reg rdata_REG; // @[package.scala:100:91]
reg [7:0] rdata_r_0; // @[package.scala:88:63]
reg [7:0] rdata_r_1; // @[package.scala:88:63]
reg [7:0] rdata_r_2; // @[package.scala:88:63]
reg [7:0] rdata_r_3; // @[package.scala:88:63]
reg [7:0] rdata_r_4; // @[package.scala:88:63]
reg [7:0] rdata_r_5; // @[package.scala:88:63]
reg [7:0] rdata_r_6; // @[package.scala:88:63]
reg [7:0] rdata_r_7; // @[package.scala:88:63]
wire [7:0] rdata_0 = rdata_REG ? _mem_R0_data[7:0] : rdata_r_0; // @[package.scala:88:{42,63}, :100:91]
wire [7:0] rdata_1 = rdata_REG ? _mem_R0_data[15:8] : rdata_r_1; // @[package.scala:88:{42,63}, :100:91]
wire [7:0] rdata_2 = rdata_REG ? _mem_R0_data[23:16] : rdata_r_2; // @[package.scala:88:{42,63}, :100:91]
wire [7:0] rdata_3 = rdata_REG ? _mem_R0_data[31:24] : rdata_r_3; // @[package.scala:88:{42,63}, :100:91]
wire [7:0] rdata_4 = rdata_REG ? _mem_R0_data[39:32] : rdata_r_4; // @[package.scala:88:{42,63}, :100:91]
wire [7:0] rdata_5 = rdata_REG ? _mem_R0_data[47:40] : rdata_r_5; // @[package.scala:88:{42,63}, :100:91]
wire [7:0] rdata_6 = rdata_REG ? _mem_R0_data[55:48] : rdata_r_6; // @[package.scala:88:{42,63}, :100:91]
wire [7:0] rdata_7 = rdata_REG ? _mem_R0_data[63:56] : rdata_r_7; // @[package.scala:88:{42,63}, :100:91]
wire _nodeIn_ar_ready_T = ~r_full; // @[SRAM.scala:104:25, :122:34]
assign _nodeIn_ar_ready_T_1 = nodeIn_r_ready | _nodeIn_ar_ready_T; // @[SRAM.scala:122:{31,34}]
assign nodeIn_ar_ready = _nodeIn_ar_ready_T_1; // @[SRAM.scala:122:31]
assign _nodeIn_r_bits_resp_T_1 = r_sel1 ? 2'h0 : 2'h3; // @[SRAM.scala:78:25, :125:26]
assign nodeIn_r_bits_resp = _nodeIn_r_bits_resp_T_1; // @[SRAM.scala:125:26]
wire [15:0] nodeIn_r_bits_data_lo_lo = {rdata_1, rdata_0}; // @[package.scala:88:42]
wire [15:0] nodeIn_r_bits_data_lo_hi = {rdata_3, rdata_2}; // @[package.scala:88:42]
wire [31:0] nodeIn_r_bits_data_lo = {nodeIn_r_bits_data_lo_hi, nodeIn_r_bits_data_lo_lo}; // @[SRAM.scala:126:26]
wire [15:0] nodeIn_r_bits_data_hi_lo = {rdata_5, rdata_4}; // @[package.scala:88:42]
wire [15:0] nodeIn_r_bits_data_hi_hi = {rdata_7, rdata_6}; // @[package.scala:88:42]
wire [31:0] nodeIn_r_bits_data_hi = {nodeIn_r_bits_data_hi_hi, nodeIn_r_bits_data_hi_lo}; // @[SRAM.scala:126:26]
assign _nodeIn_r_bits_data_T = {nodeIn_r_bits_data_hi, nodeIn_r_bits_data_lo}; // @[SRAM.scala:126:26]
assign nodeIn_r_bits_data = _nodeIn_r_bits_data_T; // @[SRAM.scala:126:26]
always @(posedge clock) begin // @[SRAM.scala:58:9]
if (reset) begin // @[SRAM.scala:58:9]
w_full <= 1'h0; // @[SRAM.scala:75:25]
r_full <= 1'h0; // @[SRAM.scala:104:25]
end
else begin // @[SRAM.scala:58:9]
w_full <= _T_3 | ~(nodeIn_b_ready & nodeIn_b_valid) & w_full; // @[Decoupled.scala:51:35]
r_full <= ren | ~(nodeIn_r_ready & nodeIn_r_valid) & r_full; // @[Decoupled.scala:51:35]
end
if (_T_3) begin // @[Decoupled.scala:51:35]
w_id <= nodeIn_aw_bits_id; // @[SRAM.scala:76:21]
w_echo_real_last <= nodeIn_aw_bits_echo_real_last; // @[SRAM.scala:77:21]
end
r_sel1 <= r_sel0; // @[Parameters.scala:137:59]
w_sel1 <= w_sel0; // @[Parameters.scala:137:59]
if (ren) begin // @[Decoupled.scala:51:35]
r_id <= nodeIn_ar_bits_id; // @[SRAM.scala:105:21]
r_echo_real_last <= nodeIn_ar_bits_echo_real_last; // @[SRAM.scala:106:21]
end
rdata_REG <= ren; // @[Decoupled.scala:51:35]
if (rdata_REG) begin // @[package.scala:100:91]
rdata_r_0 <= _mem_R0_data[7:0]; // @[package.scala:88:63]
rdata_r_1 <= _mem_R0_data[15:8]; // @[package.scala:88:63]
rdata_r_2 <= _mem_R0_data[23:16]; // @[package.scala:88:63]
rdata_r_3 <= _mem_R0_data[31:24]; // @[package.scala:88:63]
rdata_r_4 <= _mem_R0_data[39:32]; // @[package.scala:88:63]
rdata_r_5 <= _mem_R0_data[47:40]; // @[package.scala:88:63]
rdata_r_6 <= _mem_R0_data[55:48]; // @[package.scala:88:63]
rdata_r_7 <= _mem_R0_data[63:56]; // @[package.scala:88:63]
end
always @(posedge)
mem mem ( // @[DescribedSRAM.scala:17:26]
.R0_addr (_rdata_WIRE), // @[package.scala:100:58]
.R0_en (ren), // @[Decoupled.scala:51:35]
.R0_clk (clock),
.R0_data (_mem_R0_data),
.W0_addr (w_addr), // @[SRAM.scala:71:21]
.W0_en (_T_3 & w_sel0), // @[Decoupled.scala:51:35]
.W0_clk (clock),
.W0_data ({wdata_7, wdata_6, wdata_5, wdata_4, wdata_3, wdata_2, wdata_1, wdata_0}), // @[DescribedSRAM.scala:17:26]
.W0_mask (nodeIn_w_bits_strb) // @[MixedNode.scala:551:17]
); // @[DescribedSRAM.scala:17:26]
assign auto_in_aw_ready = auto_in_aw_ready_0; // @[SRAM.scala:58:9]
assign auto_in_w_ready = auto_in_w_ready_0; // @[SRAM.scala:58:9]
assign auto_in_b_valid = auto_in_b_valid_0; // @[SRAM.scala:58:9]
assign auto_in_b_bits_id = auto_in_b_bits_id_0; // @[SRAM.scala:58:9]
assign auto_in_b_bits_resp = auto_in_b_bits_resp_0; // @[SRAM.scala:58:9]
assign auto_in_b_bits_echo_real_last = auto_in_b_bits_echo_real_last_0; // @[SRAM.scala:58:9]
assign auto_in_ar_ready = auto_in_ar_ready_0; // @[SRAM.scala:58:9]
assign auto_in_r_valid = auto_in_r_valid_0; // @[SRAM.scala:58:9]
assign auto_in_r_bits_id = auto_in_r_bits_id_0; // @[SRAM.scala:58:9]
assign auto_in_r_bits_data = auto_in_r_bits_data_0; // @[SRAM.scala:58:9]
assign auto_in_r_bits_resp = auto_in_r_bits_resp_0; // @[SRAM.scala:58:9]
assign auto_in_r_bits_echo_real_last = auto_in_r_bits_echo_real_last_0; // @[SRAM.scala:58:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module ZstdMatchFinder :
input clock : Clock
input reset : Reset
output io : { l2io : { memloader_userif : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt, size : UInt, data : UInt<256>, cmd : UInt}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>}}, flip no_memops_inflight : UInt<1>}, lit_memwriter_userif : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt, size : UInt, data : UInt<256>, cmd : UInt}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>}}, flip no_memops_inflight : UInt<1>}, seq_memwriter_userif : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt, size : UInt, data : UInt<256>, cmd : UInt}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>}}, flip no_memops_inflight : UInt<1>}}, flip src : { compress_src_info : { flip ready : UInt<1>, valid : UInt<1>, bits : { ip : UInt<64>, isize : UInt<64>}}, compress_src_info2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { ip : UInt<64>, isize : UInt<64>}}}, flip dst : { lit_dst_info : { flip ready : UInt<1>, valid : UInt<1>, bits : { op : UInt<64>, cmpflag : UInt<64>}}, seq_dst_info : { flip ready : UInt<1>, valid : UInt<1>, bits : { op : UInt<64>, cmpflag : UInt<64>}}}, buff_consumed : { lit_consumed_bytes : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, seq_consumed_bytes : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, flip MAX_OFFSET_ALLOWED : UInt<64>, flip RUNTIME_HT_NUM_ENTRIES_LOG2 : UInt<5>, flip ALGORITHM : UInt<1>}
node _T = and(io.src.compress_src_info.ready, io.src.compress_src_info.valid)
when _T :
regreset loginfo_cycles : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T = add(loginfo_cycles, UInt<1>(0h1))
node _loginfo_cycles_T_1 = tail(_loginfo_cycles_T, 1)
connect loginfo_cycles, _loginfo_cycles_T_1
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles) : printf
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
printf(clock, UInt<1>(0h1), "MATCHFINDER_SRC_INFO_FIRE\n") : printf_1
regreset loginfo_cycles_1 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_2 = add(loginfo_cycles_1, UInt<1>(0h1))
node _loginfo_cycles_T_3 = tail(_loginfo_cycles_T_2, 1)
connect loginfo_cycles_1, _loginfo_cycles_T_3
node _T_5 = asUInt(reset)
node _T_6 = eq(_T_5, UInt<1>(0h0))
when _T_6 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_1) : printf_2
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
printf(clock, UInt<1>(0h1), "addr: 0x%x, size: %d\n", io.src.compress_src_info.bits.ip, io.src.compress_src_info.bits.isize) : printf_3
node _T_9 = and(io.src.compress_src_info2.ready, io.src.compress_src_info2.valid)
when _T_9 :
regreset loginfo_cycles_2 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_4 = add(loginfo_cycles_2, UInt<1>(0h1))
node _loginfo_cycles_T_5 = tail(_loginfo_cycles_T_4, 1)
connect loginfo_cycles_2, _loginfo_cycles_T_5
node _T_10 = asUInt(reset)
node _T_11 = eq(_T_10, UInt<1>(0h0))
when _T_11 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_2) : printf_4
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
printf(clock, UInt<1>(0h1), "MATCHFINDER_SRC_INFO2_FIRE\n") : printf_5
regreset loginfo_cycles_3 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_6 = add(loginfo_cycles_3, UInt<1>(0h1))
node _loginfo_cycles_T_7 = tail(_loginfo_cycles_T_6, 1)
connect loginfo_cycles_3, _loginfo_cycles_T_7
node _T_14 = asUInt(reset)
node _T_15 = eq(_T_14, UInt<1>(0h0))
when _T_15 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_3) : printf_6
node _T_16 = asUInt(reset)
node _T_17 = eq(_T_16, UInt<1>(0h0))
when _T_17 :
printf(clock, UInt<1>(0h1), "addr: 0x%x, size: %d\n", io.src.compress_src_info2.bits.ip, io.src.compress_src_info2.bits.isize) : printf_7
node _T_18 = and(io.dst.lit_dst_info.ready, io.dst.lit_dst_info.valid)
when _T_18 :
regreset loginfo_cycles_4 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_8 = add(loginfo_cycles_4, UInt<1>(0h1))
node _loginfo_cycles_T_9 = tail(_loginfo_cycles_T_8, 1)
connect loginfo_cycles_4, _loginfo_cycles_T_9
node _T_19 = asUInt(reset)
node _T_20 = eq(_T_19, UInt<1>(0h0))
when _T_20 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_4) : printf_8
node _T_21 = asUInt(reset)
node _T_22 = eq(_T_21, UInt<1>(0h0))
when _T_22 :
printf(clock, UInt<1>(0h1), "MATCHFINDER_LIT_DST_INFO_FIRE\n") : printf_9
regreset loginfo_cycles_5 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_10 = add(loginfo_cycles_5, UInt<1>(0h1))
node _loginfo_cycles_T_11 = tail(_loginfo_cycles_T_10, 1)
connect loginfo_cycles_5, _loginfo_cycles_T_11
node _T_23 = asUInt(reset)
node _T_24 = eq(_T_23, UInt<1>(0h0))
when _T_24 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_5) : printf_10
node _T_25 = asUInt(reset)
node _T_26 = eq(_T_25, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "op: 0x%x, cmpflag: 0x%x\n", io.dst.lit_dst_info.bits.op, io.dst.lit_dst_info.bits.cmpflag) : printf_11
node _T_27 = and(io.dst.seq_dst_info.ready, io.dst.seq_dst_info.valid)
when _T_27 :
regreset loginfo_cycles_6 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_12 = add(loginfo_cycles_6, UInt<1>(0h1))
node _loginfo_cycles_T_13 = tail(_loginfo_cycles_T_12, 1)
connect loginfo_cycles_6, _loginfo_cycles_T_13
node _T_28 = asUInt(reset)
node _T_29 = eq(_T_28, UInt<1>(0h0))
when _T_29 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_6) : printf_12
node _T_30 = asUInt(reset)
node _T_31 = eq(_T_30, UInt<1>(0h0))
when _T_31 :
printf(clock, UInt<1>(0h1), "MATCHFINDER_SEQ_DST_INFO_FIRE\n") : printf_13
regreset loginfo_cycles_7 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_14 = add(loginfo_cycles_7, UInt<1>(0h1))
node _loginfo_cycles_T_15 = tail(_loginfo_cycles_T_14, 1)
connect loginfo_cycles_7, _loginfo_cycles_T_15
node _T_32 = asUInt(reset)
node _T_33 = eq(_T_32, UInt<1>(0h0))
when _T_33 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_7) : printf_14
node _T_34 = asUInt(reset)
node _T_35 = eq(_T_34, UInt<1>(0h0))
when _T_35 :
printf(clock, UInt<1>(0h1), "op: 0x%x, cmpflag: 0x%x\n", io.dst.seq_dst_info.bits.op, io.dst.seq_dst_info.bits.cmpflag) : printf_15
node _T_36 = and(io.buff_consumed.lit_consumed_bytes.ready, io.buff_consumed.lit_consumed_bytes.valid)
when _T_36 :
regreset loginfo_cycles_8 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_16 = add(loginfo_cycles_8, UInt<1>(0h1))
node _loginfo_cycles_T_17 = tail(_loginfo_cycles_T_16, 1)
connect loginfo_cycles_8, _loginfo_cycles_T_17
node _T_37 = asUInt(reset)
node _T_38 = eq(_T_37, UInt<1>(0h0))
when _T_38 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_8) : printf_16
node _T_39 = asUInt(reset)
node _T_40 = eq(_T_39, UInt<1>(0h0))
when _T_40 :
printf(clock, UInt<1>(0h1), "MATCHFINDER_LIT_CONSUMED_BYTES_FIRE\n") : printf_17
regreset loginfo_cycles_9 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_18 = add(loginfo_cycles_9, UInt<1>(0h1))
node _loginfo_cycles_T_19 = tail(_loginfo_cycles_T_18, 1)
connect loginfo_cycles_9, _loginfo_cycles_T_19
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_9) : printf_18
node _T_43 = asUInt(reset)
node _T_44 = eq(_T_43, UInt<1>(0h0))
when _T_44 :
printf(clock, UInt<1>(0h1), "consumed_bytes: %d\n", io.buff_consumed.lit_consumed_bytes.bits) : printf_19
node _T_45 = and(io.buff_consumed.seq_consumed_bytes.ready, io.buff_consumed.seq_consumed_bytes.valid)
when _T_45 :
regreset loginfo_cycles_10 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_20 = add(loginfo_cycles_10, UInt<1>(0h1))
node _loginfo_cycles_T_21 = tail(_loginfo_cycles_T_20, 1)
connect loginfo_cycles_10, _loginfo_cycles_T_21
node _T_46 = asUInt(reset)
node _T_47 = eq(_T_46, UInt<1>(0h0))
when _T_47 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_10) : printf_20
node _T_48 = asUInt(reset)
node _T_49 = eq(_T_48, UInt<1>(0h0))
when _T_49 :
printf(clock, UInt<1>(0h1), "MATCHFINDER_SEQ_CONSUMED_BYTES_FIRE\n") : printf_21
regreset loginfo_cycles_11 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_22 = add(loginfo_cycles_11, UInt<1>(0h1))
node _loginfo_cycles_T_23 = tail(_loginfo_cycles_T_22, 1)
connect loginfo_cycles_11, _loginfo_cycles_T_23
node _T_50 = asUInt(reset)
node _T_51 = eq(_T_50, UInt<1>(0h0))
when _T_51 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_11) : printf_22
node _T_52 = asUInt(reset)
node _T_53 = eq(_T_52, UInt<1>(0h0))
when _T_53 :
printf(clock, UInt<1>(0h1), "consumed_bytes: %d\n", io.buff_consumed.seq_consumed_bytes.bits) : printf_23
inst memloader of LZ77HashMatcherMemLoader
connect memloader.clock, clock
connect memloader.reset, reset
connect memloader.io.l2helperUser.no_memops_inflight, io.l2io.memloader_userif.no_memops_inflight
connect memloader.io.l2helperUser.resp, io.l2io.memloader_userif.resp
connect io.l2io.memloader_userif.req.bits, memloader.io.l2helperUser.req.bits
connect io.l2io.memloader_userif.req.valid, memloader.io.l2helperUser.req.valid
connect memloader.io.l2helperUser.req.ready, io.l2io.memloader_userif.req.ready
connect memloader.io.src_info, io.src.compress_src_info
node use_zstd = eq(io.ALGORITHM, UInt<1>(0h0))
inst lz77hashmatcher of LZ77HashMatcher
connect lz77hashmatcher.clock, clock
connect lz77hashmatcher.reset, reset
node _lz77hashmatcher_io_write_snappy_header_T = eq(use_zstd, UInt<1>(0h0))
connect lz77hashmatcher.io.write_snappy_header, _lz77hashmatcher_io_write_snappy_header_T
connect lz77hashmatcher.io.MAX_OFFSET_ALLOWED, io.MAX_OFFSET_ALLOWED
connect lz77hashmatcher.io.RUNTIME_HT_NUM_ENTRIES_LOG2, io.RUNTIME_HT_NUM_ENTRIES_LOG2
connect lz77hashmatcher.io.memloader_in, memloader.io.consumer
connect lz77hashmatcher.io.memloader_optional_hbsram_in, memloader.io.optional_hbsram_write
connect lz77hashmatcher.io.src_info, io.src.compress_src_info2
inst zstd_litlen_injector of ZstdMatchFinderLitLenInjector
connect zstd_litlen_injector.clock, clock
connect zstd_litlen_injector.reset, reset
connect zstd_litlen_injector.io.memwrites_in, lz77hashmatcher.io.memwrites_out
inst seq_memwriter of ZstdMatchFinderMemwriter
connect seq_memwriter.clock, clock
connect seq_memwriter.reset, reset
connect seq_memwriter.io.memwrites_in, zstd_litlen_injector.io.seq_memwrites_out
connect seq_memwriter.io.compress_dest_info, io.dst.seq_dst_info
node _seq_memwriter_io_force_write_T = eq(use_zstd, UInt<1>(0h0))
connect seq_memwriter.io.force_write, _seq_memwriter_io_force_write_T
connect seq_memwriter.io.l2io.no_memops_inflight, io.l2io.seq_memwriter_userif.no_memops_inflight
connect seq_memwriter.io.l2io.resp, io.l2io.seq_memwriter_userif.resp
connect io.l2io.seq_memwriter_userif.req.bits, seq_memwriter.io.l2io.req.bits
connect io.l2io.seq_memwriter_userif.req.valid, seq_memwriter.io.l2io.req.valid
connect seq_memwriter.io.l2io.req.ready, io.l2io.seq_memwriter_userif.req.ready
inst lit_memwriter of ZstdMatchFinderMemwriter_1
connect lit_memwriter.clock, clock
connect lit_memwriter.reset, reset
connect lit_memwriter.io.memwrites_in, zstd_litlen_injector.io.lit_memwrites_out
connect lit_memwriter.io.compress_dest_info, io.dst.lit_dst_info
connect lit_memwriter.io.force_write, UInt<1>(0h0)
connect lit_memwriter.io.l2io.no_memops_inflight, io.l2io.lit_memwriter_userif.no_memops_inflight
connect lit_memwriter.io.l2io.resp, io.l2io.lit_memwriter_userif.resp
connect io.l2io.lit_memwriter_userif.req.bits, lit_memwriter.io.l2io.req.bits
connect io.l2io.lit_memwriter_userif.req.valid, lit_memwriter.io.l2io.req.valid
connect lit_memwriter.io.l2io.req.ready, io.l2io.lit_memwriter_userif.req.ready
connect io.buff_consumed.lit_consumed_bytes.bits, lit_memwriter.io.written_bytes.bits
connect io.buff_consumed.lit_consumed_bytes.valid, lit_memwriter.io.written_bytes.valid
connect lit_memwriter.io.written_bytes.ready, io.buff_consumed.lit_consumed_bytes.ready
connect io.buff_consumed.seq_consumed_bytes.bits, seq_memwriter.io.written_bytes.bits
connect io.buff_consumed.seq_consumed_bytes.valid, seq_memwriter.io.written_bytes.valid
connect seq_memwriter.io.written_bytes.ready, io.buff_consumed.seq_consumed_bytes.ready | module ZstdMatchFinder( // @[ZstdMatchFinder.scala:48:7]
input clock, // @[ZstdMatchFinder.scala:48:7]
input reset, // @[ZstdMatchFinder.scala:48:7]
input io_l2io_memloader_userif_req_ready, // @[ZstdMatchFinder.scala:49:14]
output io_l2io_memloader_userif_req_valid, // @[ZstdMatchFinder.scala:49:14]
output [70:0] io_l2io_memloader_userif_req_bits_addr, // @[ZstdMatchFinder.scala:49:14]
output io_l2io_memloader_userif_resp_ready, // @[ZstdMatchFinder.scala:49:14]
input io_l2io_memloader_userif_resp_valid, // @[ZstdMatchFinder.scala:49:14]
input [255:0] io_l2io_memloader_userif_resp_bits_data, // @[ZstdMatchFinder.scala:49:14]
input io_l2io_memloader_userif_no_memops_inflight, // @[ZstdMatchFinder.scala:49:14]
input io_l2io_lit_memwriter_userif_req_ready, // @[ZstdMatchFinder.scala:49:14]
output io_l2io_lit_memwriter_userif_req_valid, // @[ZstdMatchFinder.scala:49:14]
output [63:0] io_l2io_lit_memwriter_userif_req_bits_addr, // @[ZstdMatchFinder.scala:49:14]
output [2:0] io_l2io_lit_memwriter_userif_req_bits_size, // @[ZstdMatchFinder.scala:49:14]
output [255:0] io_l2io_lit_memwriter_userif_req_bits_data, // @[ZstdMatchFinder.scala:49:14]
input io_l2io_lit_memwriter_userif_resp_valid, // @[ZstdMatchFinder.scala:49:14]
input [255:0] io_l2io_lit_memwriter_userif_resp_bits_data, // @[ZstdMatchFinder.scala:49:14]
input io_l2io_lit_memwriter_userif_no_memops_inflight, // @[ZstdMatchFinder.scala:49:14]
input io_l2io_seq_memwriter_userif_req_ready, // @[ZstdMatchFinder.scala:49:14]
output io_l2io_seq_memwriter_userif_req_valid, // @[ZstdMatchFinder.scala:49:14]
output [63:0] io_l2io_seq_memwriter_userif_req_bits_addr, // @[ZstdMatchFinder.scala:49:14]
output [2:0] io_l2io_seq_memwriter_userif_req_bits_size, // @[ZstdMatchFinder.scala:49:14]
output [255:0] io_l2io_seq_memwriter_userif_req_bits_data, // @[ZstdMatchFinder.scala:49:14]
input io_l2io_seq_memwriter_userif_resp_valid, // @[ZstdMatchFinder.scala:49:14]
input [255:0] io_l2io_seq_memwriter_userif_resp_bits_data, // @[ZstdMatchFinder.scala:49:14]
input io_l2io_seq_memwriter_userif_no_memops_inflight, // @[ZstdMatchFinder.scala:49:14]
output io_src_compress_src_info_ready, // @[ZstdMatchFinder.scala:49:14]
input io_src_compress_src_info_valid, // @[ZstdMatchFinder.scala:49:14]
input [63:0] io_src_compress_src_info_bits_ip, // @[ZstdMatchFinder.scala:49:14]
input [63:0] io_src_compress_src_info_bits_isize, // @[ZstdMatchFinder.scala:49:14]
output io_src_compress_src_info2_ready, // @[ZstdMatchFinder.scala:49:14]
input io_src_compress_src_info2_valid, // @[ZstdMatchFinder.scala:49:14]
input [63:0] io_src_compress_src_info2_bits_ip, // @[ZstdMatchFinder.scala:49:14]
input [63:0] io_src_compress_src_info2_bits_isize, // @[ZstdMatchFinder.scala:49:14]
output io_dst_lit_dst_info_ready, // @[ZstdMatchFinder.scala:49:14]
input io_dst_lit_dst_info_valid, // @[ZstdMatchFinder.scala:49:14]
input [63:0] io_dst_lit_dst_info_bits_op, // @[ZstdMatchFinder.scala:49:14]
input [63:0] io_dst_lit_dst_info_bits_cmpflag, // @[ZstdMatchFinder.scala:49:14]
output io_dst_seq_dst_info_ready, // @[ZstdMatchFinder.scala:49:14]
input io_dst_seq_dst_info_valid, // @[ZstdMatchFinder.scala:49:14]
input [63:0] io_dst_seq_dst_info_bits_op, // @[ZstdMatchFinder.scala:49:14]
input [63:0] io_dst_seq_dst_info_bits_cmpflag, // @[ZstdMatchFinder.scala:49:14]
input io_buff_consumed_lit_consumed_bytes_ready, // @[ZstdMatchFinder.scala:49:14]
output io_buff_consumed_lit_consumed_bytes_valid, // @[ZstdMatchFinder.scala:49:14]
output [63:0] io_buff_consumed_lit_consumed_bytes_bits, // @[ZstdMatchFinder.scala:49:14]
input io_buff_consumed_seq_consumed_bytes_ready, // @[ZstdMatchFinder.scala:49:14]
output io_buff_consumed_seq_consumed_bytes_valid, // @[ZstdMatchFinder.scala:49:14]
output [63:0] io_buff_consumed_seq_consumed_bytes_bits, // @[ZstdMatchFinder.scala:49:14]
input [63:0] io_MAX_OFFSET_ALLOWED, // @[ZstdMatchFinder.scala:49:14]
input [4:0] io_RUNTIME_HT_NUM_ENTRIES_LOG2, // @[ZstdMatchFinder.scala:49:14]
input io_ALGORITHM // @[ZstdMatchFinder.scala:49:14]
);
wire _lit_memwriter_io_memwrites_in_ready; // @[ZstdMatchFinder.scala:157:31]
wire _seq_memwriter_io_memwrites_in_ready; // @[ZstdMatchFinder.scala:151:31]
wire _zstd_litlen_injector_io_memwrites_in_ready; // @[ZstdMatchFinder.scala:148:38]
wire _zstd_litlen_injector_io_seq_memwrites_out_valid; // @[ZstdMatchFinder.scala:148:38]
wire [255:0] _zstd_litlen_injector_io_seq_memwrites_out_bits_data; // @[ZstdMatchFinder.scala:148:38]
wire [5:0] _zstd_litlen_injector_io_seq_memwrites_out_bits_validbytes; // @[ZstdMatchFinder.scala:148:38]
wire _zstd_litlen_injector_io_seq_memwrites_out_bits_end_of_message; // @[ZstdMatchFinder.scala:148:38]
wire _zstd_litlen_injector_io_seq_memwrites_out_bits_is_copy; // @[ZstdMatchFinder.scala:148:38]
wire _zstd_litlen_injector_io_seq_memwrites_out_bits_length_header; // @[ZstdMatchFinder.scala:148:38]
wire _zstd_litlen_injector_io_seq_memwrites_out_bits_is_dummy; // @[ZstdMatchFinder.scala:148:38]
wire _zstd_litlen_injector_io_lit_memwrites_out_valid; // @[ZstdMatchFinder.scala:148:38]
wire [255:0] _zstd_litlen_injector_io_lit_memwrites_out_bits_data; // @[ZstdMatchFinder.scala:148:38]
wire [5:0] _zstd_litlen_injector_io_lit_memwrites_out_bits_validbytes; // @[ZstdMatchFinder.scala:148:38]
wire _zstd_litlen_injector_io_lit_memwrites_out_bits_end_of_message; // @[ZstdMatchFinder.scala:148:38]
wire _zstd_litlen_injector_io_lit_memwrites_out_bits_is_copy; // @[ZstdMatchFinder.scala:148:38]
wire _zstd_litlen_injector_io_lit_memwrites_out_bits_length_header; // @[ZstdMatchFinder.scala:148:38]
wire _zstd_litlen_injector_io_lit_memwrites_out_bits_is_dummy; // @[ZstdMatchFinder.scala:148:38]
wire [5:0] _lz77hashmatcher_io_memloader_in_user_consumed_bytes; // @[ZstdMatchFinder.scala:87:31]
wire _lz77hashmatcher_io_memloader_in_output_ready; // @[ZstdMatchFinder.scala:87:31]
wire _lz77hashmatcher_io_memwrites_out_valid; // @[ZstdMatchFinder.scala:87:31]
wire [255:0] _lz77hashmatcher_io_memwrites_out_bits_data; // @[ZstdMatchFinder.scala:87:31]
wire [5:0] _lz77hashmatcher_io_memwrites_out_bits_validbytes; // @[ZstdMatchFinder.scala:87:31]
wire _lz77hashmatcher_io_memwrites_out_bits_end_of_message; // @[ZstdMatchFinder.scala:87:31]
wire _lz77hashmatcher_io_memwrites_out_bits_is_copy; // @[ZstdMatchFinder.scala:87:31]
wire _lz77hashmatcher_io_memwrites_out_bits_length_header; // @[ZstdMatchFinder.scala:87:31]
wire [5:0] _memloader_io_consumer_available_output_bytes; // @[ZstdMatchFinder.scala:81:25]
wire _memloader_io_consumer_output_valid; // @[ZstdMatchFinder.scala:81:25]
wire [255:0] _memloader_io_consumer_output_data; // @[ZstdMatchFinder.scala:81:25]
wire _memloader_io_consumer_output_last_chunk; // @[ZstdMatchFinder.scala:81:25]
wire _memloader_io_optional_hbsram_write_valid; // @[ZstdMatchFinder.scala:81:25]
wire [255:0] _memloader_io_optional_hbsram_write_bits_data; // @[ZstdMatchFinder.scala:81:25]
wire [5:0] _memloader_io_optional_hbsram_write_bits_valid_bytes; // @[ZstdMatchFinder.scala:81:25]
wire io_l2io_memloader_userif_req_ready_0 = io_l2io_memloader_userif_req_ready; // @[ZstdMatchFinder.scala:48:7]
wire io_l2io_memloader_userif_resp_valid_0 = io_l2io_memloader_userif_resp_valid; // @[ZstdMatchFinder.scala:48:7]
wire [255:0] io_l2io_memloader_userif_resp_bits_data_0 = io_l2io_memloader_userif_resp_bits_data; // @[ZstdMatchFinder.scala:48:7]
wire io_l2io_memloader_userif_no_memops_inflight_0 = io_l2io_memloader_userif_no_memops_inflight; // @[ZstdMatchFinder.scala:48:7]
wire io_l2io_lit_memwriter_userif_req_ready_0 = io_l2io_lit_memwriter_userif_req_ready; // @[ZstdMatchFinder.scala:48:7]
wire io_l2io_lit_memwriter_userif_resp_valid_0 = io_l2io_lit_memwriter_userif_resp_valid; // @[ZstdMatchFinder.scala:48:7]
wire [255:0] io_l2io_lit_memwriter_userif_resp_bits_data_0 = io_l2io_lit_memwriter_userif_resp_bits_data; // @[ZstdMatchFinder.scala:48:7]
wire io_l2io_lit_memwriter_userif_no_memops_inflight_0 = io_l2io_lit_memwriter_userif_no_memops_inflight; // @[ZstdMatchFinder.scala:48:7]
wire io_l2io_seq_memwriter_userif_req_ready_0 = io_l2io_seq_memwriter_userif_req_ready; // @[ZstdMatchFinder.scala:48:7]
wire io_l2io_seq_memwriter_userif_resp_valid_0 = io_l2io_seq_memwriter_userif_resp_valid; // @[ZstdMatchFinder.scala:48:7]
wire [255:0] io_l2io_seq_memwriter_userif_resp_bits_data_0 = io_l2io_seq_memwriter_userif_resp_bits_data; // @[ZstdMatchFinder.scala:48:7]
wire io_l2io_seq_memwriter_userif_no_memops_inflight_0 = io_l2io_seq_memwriter_userif_no_memops_inflight; // @[ZstdMatchFinder.scala:48:7]
wire io_src_compress_src_info_valid_0 = io_src_compress_src_info_valid; // @[ZstdMatchFinder.scala:48:7]
wire [63:0] io_src_compress_src_info_bits_ip_0 = io_src_compress_src_info_bits_ip; // @[ZstdMatchFinder.scala:48:7]
wire [63:0] io_src_compress_src_info_bits_isize_0 = io_src_compress_src_info_bits_isize; // @[ZstdMatchFinder.scala:48:7]
wire io_src_compress_src_info2_valid_0 = io_src_compress_src_info2_valid; // @[ZstdMatchFinder.scala:48:7]
wire [63:0] io_src_compress_src_info2_bits_ip_0 = io_src_compress_src_info2_bits_ip; // @[ZstdMatchFinder.scala:48:7]
wire [63:0] io_src_compress_src_info2_bits_isize_0 = io_src_compress_src_info2_bits_isize; // @[ZstdMatchFinder.scala:48:7]
wire io_dst_lit_dst_info_valid_0 = io_dst_lit_dst_info_valid; // @[ZstdMatchFinder.scala:48:7]
wire [63:0] io_dst_lit_dst_info_bits_op_0 = io_dst_lit_dst_info_bits_op; // @[ZstdMatchFinder.scala:48:7]
wire [63:0] io_dst_lit_dst_info_bits_cmpflag_0 = io_dst_lit_dst_info_bits_cmpflag; // @[ZstdMatchFinder.scala:48:7]
wire io_dst_seq_dst_info_valid_0 = io_dst_seq_dst_info_valid; // @[ZstdMatchFinder.scala:48:7]
wire [63:0] io_dst_seq_dst_info_bits_op_0 = io_dst_seq_dst_info_bits_op; // @[ZstdMatchFinder.scala:48:7]
wire [63:0] io_dst_seq_dst_info_bits_cmpflag_0 = io_dst_seq_dst_info_bits_cmpflag; // @[ZstdMatchFinder.scala:48:7]
wire io_buff_consumed_lit_consumed_bytes_ready_0 = io_buff_consumed_lit_consumed_bytes_ready; // @[ZstdMatchFinder.scala:48:7]
wire io_buff_consumed_seq_consumed_bytes_ready_0 = io_buff_consumed_seq_consumed_bytes_ready; // @[ZstdMatchFinder.scala:48:7]
wire [63:0] io_MAX_OFFSET_ALLOWED_0 = io_MAX_OFFSET_ALLOWED; // @[ZstdMatchFinder.scala:48:7]
wire [4:0] io_RUNTIME_HT_NUM_ENTRIES_LOG2_0 = io_RUNTIME_HT_NUM_ENTRIES_LOG2; // @[ZstdMatchFinder.scala:48:7]
wire io_ALGORITHM_0 = io_ALGORITHM; // @[ZstdMatchFinder.scala:48:7]
wire [2:0] io_l2io_memloader_userif_req_bits_size = 3'h5; // @[ZstdMatchFinder.scala:48:7]
wire [255:0] io_l2io_memloader_userif_req_bits_data = 256'h0; // @[ZstdMatchFinder.scala:48:7]
wire io_l2io_memloader_userif_req_bits_cmd = 1'h0; // @[ZstdMatchFinder.scala:48:7]
wire io_l2io_lit_memwriter_userif_req_bits_cmd = 1'h1; // @[ZstdMatchFinder.scala:48:7]
wire io_l2io_lit_memwriter_userif_resp_ready = 1'h1; // @[ZstdMatchFinder.scala:48:7]
wire io_l2io_seq_memwriter_userif_req_bits_cmd = 1'h1; // @[ZstdMatchFinder.scala:48:7]
wire io_l2io_seq_memwriter_userif_resp_ready = 1'h1; // @[ZstdMatchFinder.scala:48:7]
wire [70:0] io_l2io_memloader_userif_req_bits_addr_0; // @[ZstdMatchFinder.scala:48:7]
wire io_l2io_memloader_userif_req_valid_0; // @[ZstdMatchFinder.scala:48:7]
wire io_l2io_memloader_userif_resp_ready_0; // @[ZstdMatchFinder.scala:48:7]
wire [63:0] io_l2io_lit_memwriter_userif_req_bits_addr_0; // @[ZstdMatchFinder.scala:48:7]
wire [2:0] io_l2io_lit_memwriter_userif_req_bits_size_0; // @[ZstdMatchFinder.scala:48:7]
wire [255:0] io_l2io_lit_memwriter_userif_req_bits_data_0; // @[ZstdMatchFinder.scala:48:7]
wire io_l2io_lit_memwriter_userif_req_valid_0; // @[ZstdMatchFinder.scala:48:7]
wire [63:0] io_l2io_seq_memwriter_userif_req_bits_addr_0; // @[ZstdMatchFinder.scala:48:7]
wire [2:0] io_l2io_seq_memwriter_userif_req_bits_size_0; // @[ZstdMatchFinder.scala:48:7]
wire [255:0] io_l2io_seq_memwriter_userif_req_bits_data_0; // @[ZstdMatchFinder.scala:48:7]
wire io_l2io_seq_memwriter_userif_req_valid_0; // @[ZstdMatchFinder.scala:48:7]
wire io_src_compress_src_info_ready_0; // @[ZstdMatchFinder.scala:48:7]
wire io_src_compress_src_info2_ready_0; // @[ZstdMatchFinder.scala:48:7]
wire io_dst_lit_dst_info_ready_0; // @[ZstdMatchFinder.scala:48:7]
wire io_dst_seq_dst_info_ready_0; // @[ZstdMatchFinder.scala:48:7]
wire io_buff_consumed_lit_consumed_bytes_valid_0; // @[ZstdMatchFinder.scala:48:7]
wire [63:0] io_buff_consumed_lit_consumed_bytes_bits_0; // @[ZstdMatchFinder.scala:48:7]
wire io_buff_consumed_seq_consumed_bytes_valid_0; // @[ZstdMatchFinder.scala:48:7]
wire [63:0] io_buff_consumed_seq_consumed_bytes_bits_0; // @[ZstdMatchFinder.scala:48:7]
reg [63:0] loginfo_cycles; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_1; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_2; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_4 = {1'h0, loginfo_cycles_2} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_3; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_6 = {1'h0, loginfo_cycles_3} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_7 = _loginfo_cycles_T_6[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_4; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_8 = {1'h0, loginfo_cycles_4} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_9 = _loginfo_cycles_T_8[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_5; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_10 = {1'h0, loginfo_cycles_5} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_11 = _loginfo_cycles_T_10[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_6; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_12 = {1'h0, loginfo_cycles_6} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_13 = _loginfo_cycles_T_12[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_7; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_14 = {1'h0, loginfo_cycles_7} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_15 = _loginfo_cycles_T_14[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_8; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_16 = {1'h0, loginfo_cycles_8} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_17 = _loginfo_cycles_T_16[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_9; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_18 = {1'h0, loginfo_cycles_9} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_19 = _loginfo_cycles_T_18[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_10; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_20 = {1'h0, loginfo_cycles_10} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_21 = _loginfo_cycles_T_20[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_11; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_22 = {1'h0, loginfo_cycles_11} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_23 = _loginfo_cycles_T_22[63:0]; // @[Util.scala:19:38] |
Generate the Verilog code corresponding to this FIRRTL code module TLAtomicAutomata_cbus :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_18
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
wire initval : { state : UInt<2>}
connect initval.state, UInt<1>(0h0)
wire _cam_s_WIRE : { state : UInt<2>}[1]
connect _cam_s_WIRE[0], initval
regreset cam_s : { state : UInt<2>}[1], clock, reset, _cam_s_WIRE
reg cam_a : { bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, fifoId : UInt<1>, lut : UInt<4>}[1], clock
reg cam_d : { data : UInt<64>, denied : UInt<1>, corrupt : UInt<1>}[1], clock
node cam_free_0 = eq(cam_s[0].state, UInt<1>(0h0))
node cam_amo_0 = eq(cam_s[0].state, UInt<2>(0h2))
node _cam_abusy_T = eq(cam_s[0].state, UInt<2>(0h3))
node _cam_abusy_T_1 = eq(cam_s[0].state, UInt<2>(0h2))
node cam_abusy_0 = or(_cam_abusy_T, _cam_abusy_T_1)
node cam_dmatch_0 = neq(cam_s[0].state, UInt<1>(0h0))
node _a_canLogical_T = leq(UInt<1>(0h0), nodeIn.a.bits.size)
node _a_canLogical_T_1 = leq(nodeIn.a.bits.size, UInt<2>(0h3))
node _a_canLogical_T_2 = and(_a_canLogical_T, _a_canLogical_T_1)
node _a_canLogical_T_3 = or(UInt<1>(0h0), _a_canLogical_T_2)
node _a_canLogical_T_4 = xor(nodeIn.a.bits.address, UInt<13>(0h1000))
node _a_canLogical_T_5 = cvt(_a_canLogical_T_4)
node _a_canLogical_T_6 = and(_a_canLogical_T_5, asSInt(UInt<33>(0h9a111000)))
node _a_canLogical_T_7 = asSInt(_a_canLogical_T_6)
node _a_canLogical_T_8 = eq(_a_canLogical_T_7, asSInt(UInt<1>(0h0)))
node _a_canLogical_T_9 = xor(nodeIn.a.bits.address, UInt<29>(0h10000000))
node _a_canLogical_T_10 = cvt(_a_canLogical_T_9)
node _a_canLogical_T_11 = and(_a_canLogical_T_10, asSInt(UInt<33>(0h9a111000)))
node _a_canLogical_T_12 = asSInt(_a_canLogical_T_11)
node _a_canLogical_T_13 = eq(_a_canLogical_T_12, asSInt(UInt<1>(0h0)))
node _a_canLogical_T_14 = or(_a_canLogical_T_8, _a_canLogical_T_13)
node _a_canLogical_T_15 = and(_a_canLogical_T_3, _a_canLogical_T_14)
node _a_canLogical_T_16 = or(UInt<1>(0h0), UInt<1>(0h0))
node _a_canLogical_T_17 = xor(nodeIn.a.bits.address, UInt<1>(0h0))
node _a_canLogical_T_18 = cvt(_a_canLogical_T_17)
node _a_canLogical_T_19 = and(_a_canLogical_T_18, asSInt(UInt<33>(0h9a111000)))
node _a_canLogical_T_20 = asSInt(_a_canLogical_T_19)
node _a_canLogical_T_21 = eq(_a_canLogical_T_20, asSInt(UInt<1>(0h0)))
node _a_canLogical_T_22 = xor(nodeIn.a.bits.address, UInt<17>(0h10000))
node _a_canLogical_T_23 = cvt(_a_canLogical_T_22)
node _a_canLogical_T_24 = and(_a_canLogical_T_23, asSInt(UInt<33>(0h9a110000)))
node _a_canLogical_T_25 = asSInt(_a_canLogical_T_24)
node _a_canLogical_T_26 = eq(_a_canLogical_T_25, asSInt(UInt<1>(0h0)))
node _a_canLogical_T_27 = xor(nodeIn.a.bits.address, UInt<21>(0h100000))
node _a_canLogical_T_28 = cvt(_a_canLogical_T_27)
node _a_canLogical_T_29 = and(_a_canLogical_T_28, asSInt(UInt<33>(0h9a101000)))
node _a_canLogical_T_30 = asSInt(_a_canLogical_T_29)
node _a_canLogical_T_31 = eq(_a_canLogical_T_30, asSInt(UInt<1>(0h0)))
node _a_canLogical_T_32 = xor(nodeIn.a.bits.address, UInt<26>(0h2000000))
node _a_canLogical_T_33 = cvt(_a_canLogical_T_32)
node _a_canLogical_T_34 = and(_a_canLogical_T_33, asSInt(UInt<33>(0h9a110000)))
node _a_canLogical_T_35 = asSInt(_a_canLogical_T_34)
node _a_canLogical_T_36 = eq(_a_canLogical_T_35, asSInt(UInt<1>(0h0)))
node _a_canLogical_T_37 = xor(nodeIn.a.bits.address, UInt<28>(0h8000000))
node _a_canLogical_T_38 = cvt(_a_canLogical_T_37)
node _a_canLogical_T_39 = and(_a_canLogical_T_38, asSInt(UInt<33>(0h98000000)))
node _a_canLogical_T_40 = asSInt(_a_canLogical_T_39)
node _a_canLogical_T_41 = eq(_a_canLogical_T_40, asSInt(UInt<1>(0h0)))
node _a_canLogical_T_42 = or(_a_canLogical_T_21, _a_canLogical_T_26)
node _a_canLogical_T_43 = or(_a_canLogical_T_42, _a_canLogical_T_31)
node _a_canLogical_T_44 = or(_a_canLogical_T_43, _a_canLogical_T_36)
node _a_canLogical_T_45 = or(_a_canLogical_T_44, _a_canLogical_T_41)
node _a_canLogical_T_46 = and(_a_canLogical_T_16, _a_canLogical_T_45)
node _a_canLogical_T_47 = eq(UInt<2>(0h2), nodeIn.a.bits.size)
node _a_canLogical_T_48 = or(UInt<1>(0h0), _a_canLogical_T_47)
node _a_canLogical_T_49 = xor(nodeIn.a.bits.address, UInt<32>(0h80000000))
node _a_canLogical_T_50 = cvt(_a_canLogical_T_49)
node _a_canLogical_T_51 = and(_a_canLogical_T_50, asSInt(UInt<33>(0h9a110000)))
node _a_canLogical_T_52 = asSInt(_a_canLogical_T_51)
node _a_canLogical_T_53 = eq(_a_canLogical_T_52, asSInt(UInt<1>(0h0)))
node _a_canLogical_T_54 = and(_a_canLogical_T_48, _a_canLogical_T_53)
node _a_canLogical_T_55 = or(UInt<1>(0h0), _a_canLogical_T_15)
node _a_canLogical_T_56 = or(_a_canLogical_T_55, _a_canLogical_T_46)
node _a_canLogical_T_57 = or(_a_canLogical_T_56, _a_canLogical_T_54)
node a_canLogical = and(UInt<1>(0h1), _a_canLogical_T_57)
node _a_canArithmetic_T = leq(UInt<1>(0h0), nodeIn.a.bits.size)
node _a_canArithmetic_T_1 = leq(nodeIn.a.bits.size, UInt<2>(0h3))
node _a_canArithmetic_T_2 = and(_a_canArithmetic_T, _a_canArithmetic_T_1)
node _a_canArithmetic_T_3 = or(UInt<1>(0h0), _a_canArithmetic_T_2)
node _a_canArithmetic_T_4 = xor(nodeIn.a.bits.address, UInt<13>(0h1000))
node _a_canArithmetic_T_5 = cvt(_a_canArithmetic_T_4)
node _a_canArithmetic_T_6 = and(_a_canArithmetic_T_5, asSInt(UInt<33>(0h9a111000)))
node _a_canArithmetic_T_7 = asSInt(_a_canArithmetic_T_6)
node _a_canArithmetic_T_8 = eq(_a_canArithmetic_T_7, asSInt(UInt<1>(0h0)))
node _a_canArithmetic_T_9 = xor(nodeIn.a.bits.address, UInt<29>(0h10000000))
node _a_canArithmetic_T_10 = cvt(_a_canArithmetic_T_9)
node _a_canArithmetic_T_11 = and(_a_canArithmetic_T_10, asSInt(UInt<33>(0h9a111000)))
node _a_canArithmetic_T_12 = asSInt(_a_canArithmetic_T_11)
node _a_canArithmetic_T_13 = eq(_a_canArithmetic_T_12, asSInt(UInt<1>(0h0)))
node _a_canArithmetic_T_14 = or(_a_canArithmetic_T_8, _a_canArithmetic_T_13)
node _a_canArithmetic_T_15 = and(_a_canArithmetic_T_3, _a_canArithmetic_T_14)
node _a_canArithmetic_T_16 = or(UInt<1>(0h0), UInt<1>(0h0))
node _a_canArithmetic_T_17 = xor(nodeIn.a.bits.address, UInt<1>(0h0))
node _a_canArithmetic_T_18 = cvt(_a_canArithmetic_T_17)
node _a_canArithmetic_T_19 = and(_a_canArithmetic_T_18, asSInt(UInt<33>(0h9a111000)))
node _a_canArithmetic_T_20 = asSInt(_a_canArithmetic_T_19)
node _a_canArithmetic_T_21 = eq(_a_canArithmetic_T_20, asSInt(UInt<1>(0h0)))
node _a_canArithmetic_T_22 = xor(nodeIn.a.bits.address, UInt<17>(0h10000))
node _a_canArithmetic_T_23 = cvt(_a_canArithmetic_T_22)
node _a_canArithmetic_T_24 = and(_a_canArithmetic_T_23, asSInt(UInt<33>(0h9a110000)))
node _a_canArithmetic_T_25 = asSInt(_a_canArithmetic_T_24)
node _a_canArithmetic_T_26 = eq(_a_canArithmetic_T_25, asSInt(UInt<1>(0h0)))
node _a_canArithmetic_T_27 = xor(nodeIn.a.bits.address, UInt<21>(0h100000))
node _a_canArithmetic_T_28 = cvt(_a_canArithmetic_T_27)
node _a_canArithmetic_T_29 = and(_a_canArithmetic_T_28, asSInt(UInt<33>(0h9a101000)))
node _a_canArithmetic_T_30 = asSInt(_a_canArithmetic_T_29)
node _a_canArithmetic_T_31 = eq(_a_canArithmetic_T_30, asSInt(UInt<1>(0h0)))
node _a_canArithmetic_T_32 = xor(nodeIn.a.bits.address, UInt<26>(0h2000000))
node _a_canArithmetic_T_33 = cvt(_a_canArithmetic_T_32)
node _a_canArithmetic_T_34 = and(_a_canArithmetic_T_33, asSInt(UInt<33>(0h9a110000)))
node _a_canArithmetic_T_35 = asSInt(_a_canArithmetic_T_34)
node _a_canArithmetic_T_36 = eq(_a_canArithmetic_T_35, asSInt(UInt<1>(0h0)))
node _a_canArithmetic_T_37 = xor(nodeIn.a.bits.address, UInt<28>(0h8000000))
node _a_canArithmetic_T_38 = cvt(_a_canArithmetic_T_37)
node _a_canArithmetic_T_39 = and(_a_canArithmetic_T_38, asSInt(UInt<33>(0h98000000)))
node _a_canArithmetic_T_40 = asSInt(_a_canArithmetic_T_39)
node _a_canArithmetic_T_41 = eq(_a_canArithmetic_T_40, asSInt(UInt<1>(0h0)))
node _a_canArithmetic_T_42 = or(_a_canArithmetic_T_21, _a_canArithmetic_T_26)
node _a_canArithmetic_T_43 = or(_a_canArithmetic_T_42, _a_canArithmetic_T_31)
node _a_canArithmetic_T_44 = or(_a_canArithmetic_T_43, _a_canArithmetic_T_36)
node _a_canArithmetic_T_45 = or(_a_canArithmetic_T_44, _a_canArithmetic_T_41)
node _a_canArithmetic_T_46 = and(_a_canArithmetic_T_16, _a_canArithmetic_T_45)
node _a_canArithmetic_T_47 = eq(UInt<2>(0h2), nodeIn.a.bits.size)
node _a_canArithmetic_T_48 = or(UInt<1>(0h0), _a_canArithmetic_T_47)
node _a_canArithmetic_T_49 = xor(nodeIn.a.bits.address, UInt<32>(0h80000000))
node _a_canArithmetic_T_50 = cvt(_a_canArithmetic_T_49)
node _a_canArithmetic_T_51 = and(_a_canArithmetic_T_50, asSInt(UInt<33>(0h9a110000)))
node _a_canArithmetic_T_52 = asSInt(_a_canArithmetic_T_51)
node _a_canArithmetic_T_53 = eq(_a_canArithmetic_T_52, asSInt(UInt<1>(0h0)))
node _a_canArithmetic_T_54 = and(_a_canArithmetic_T_48, _a_canArithmetic_T_53)
node _a_canArithmetic_T_55 = or(UInt<1>(0h0), _a_canArithmetic_T_15)
node _a_canArithmetic_T_56 = or(_a_canArithmetic_T_55, _a_canArithmetic_T_46)
node _a_canArithmetic_T_57 = or(_a_canArithmetic_T_56, _a_canArithmetic_T_54)
node a_canArithmetic = and(UInt<1>(0h1), _a_canArithmetic_T_57)
node a_isLogical = eq(nodeIn.a.bits.opcode, UInt<2>(0h3))
node a_isArithmetic = eq(nodeIn.a.bits.opcode, UInt<2>(0h2))
node _a_isSupported_T = mux(a_isArithmetic, a_canArithmetic, UInt<1>(0h1))
node a_isSupported = mux(a_isLogical, a_canLogical, _a_isSupported_T)
node _a_cam_por_put_T = or(UInt<1>(0h0), cam_amo_0)
node _a_cam_sel_put_T = eq(UInt<1>(0h0), UInt<1>(0h0))
node a_cam_sel_put_0 = and(cam_amo_0, _a_cam_sel_put_T)
node _a_fifoId_T = xor(nodeIn.a.bits.address, UInt<1>(0h0))
node _a_fifoId_T_1 = cvt(_a_fifoId_T)
node _a_fifoId_T_2 = and(_a_fifoId_T_1, asSInt(UInt<1>(0h0)))
node _a_fifoId_T_3 = asSInt(_a_fifoId_T_2)
node _a_fifoId_T_4 = eq(_a_fifoId_T_3, asSInt(UInt<1>(0h0)))
node _a_cam_busy_T = eq(cam_a[0].fifoId, UInt<1>(0h0))
node a_cam_busy = and(cam_abusy_0, _a_cam_busy_T)
node _a_cam_por_free_T = or(UInt<1>(0h0), cam_free_0)
node _a_cam_sel_free_T = eq(UInt<1>(0h0), UInt<1>(0h0))
node a_cam_sel_free_0 = and(cam_free_0, _a_cam_sel_free_T)
node _indexes_T = bits(cam_a[0].bits.data, 0, 0)
node _indexes_T_1 = bits(cam_d[0].data, 0, 0)
node indexes_0 = cat(_indexes_T, _indexes_T_1)
node _indexes_T_2 = bits(cam_a[0].bits.data, 1, 1)
node _indexes_T_3 = bits(cam_d[0].data, 1, 1)
node indexes_1 = cat(_indexes_T_2, _indexes_T_3)
node _indexes_T_4 = bits(cam_a[0].bits.data, 2, 2)
node _indexes_T_5 = bits(cam_d[0].data, 2, 2)
node indexes_2 = cat(_indexes_T_4, _indexes_T_5)
node _indexes_T_6 = bits(cam_a[0].bits.data, 3, 3)
node _indexes_T_7 = bits(cam_d[0].data, 3, 3)
node indexes_3 = cat(_indexes_T_6, _indexes_T_7)
node _indexes_T_8 = bits(cam_a[0].bits.data, 4, 4)
node _indexes_T_9 = bits(cam_d[0].data, 4, 4)
node indexes_4 = cat(_indexes_T_8, _indexes_T_9)
node _indexes_T_10 = bits(cam_a[0].bits.data, 5, 5)
node _indexes_T_11 = bits(cam_d[0].data, 5, 5)
node indexes_5 = cat(_indexes_T_10, _indexes_T_11)
node _indexes_T_12 = bits(cam_a[0].bits.data, 6, 6)
node _indexes_T_13 = bits(cam_d[0].data, 6, 6)
node indexes_6 = cat(_indexes_T_12, _indexes_T_13)
node _indexes_T_14 = bits(cam_a[0].bits.data, 7, 7)
node _indexes_T_15 = bits(cam_d[0].data, 7, 7)
node indexes_7 = cat(_indexes_T_14, _indexes_T_15)
node _indexes_T_16 = bits(cam_a[0].bits.data, 8, 8)
node _indexes_T_17 = bits(cam_d[0].data, 8, 8)
node indexes_8 = cat(_indexes_T_16, _indexes_T_17)
node _indexes_T_18 = bits(cam_a[0].bits.data, 9, 9)
node _indexes_T_19 = bits(cam_d[0].data, 9, 9)
node indexes_9 = cat(_indexes_T_18, _indexes_T_19)
node _indexes_T_20 = bits(cam_a[0].bits.data, 10, 10)
node _indexes_T_21 = bits(cam_d[0].data, 10, 10)
node indexes_10 = cat(_indexes_T_20, _indexes_T_21)
node _indexes_T_22 = bits(cam_a[0].bits.data, 11, 11)
node _indexes_T_23 = bits(cam_d[0].data, 11, 11)
node indexes_11 = cat(_indexes_T_22, _indexes_T_23)
node _indexes_T_24 = bits(cam_a[0].bits.data, 12, 12)
node _indexes_T_25 = bits(cam_d[0].data, 12, 12)
node indexes_12 = cat(_indexes_T_24, _indexes_T_25)
node _indexes_T_26 = bits(cam_a[0].bits.data, 13, 13)
node _indexes_T_27 = bits(cam_d[0].data, 13, 13)
node indexes_13 = cat(_indexes_T_26, _indexes_T_27)
node _indexes_T_28 = bits(cam_a[0].bits.data, 14, 14)
node _indexes_T_29 = bits(cam_d[0].data, 14, 14)
node indexes_14 = cat(_indexes_T_28, _indexes_T_29)
node _indexes_T_30 = bits(cam_a[0].bits.data, 15, 15)
node _indexes_T_31 = bits(cam_d[0].data, 15, 15)
node indexes_15 = cat(_indexes_T_30, _indexes_T_31)
node _indexes_T_32 = bits(cam_a[0].bits.data, 16, 16)
node _indexes_T_33 = bits(cam_d[0].data, 16, 16)
node indexes_16 = cat(_indexes_T_32, _indexes_T_33)
node _indexes_T_34 = bits(cam_a[0].bits.data, 17, 17)
node _indexes_T_35 = bits(cam_d[0].data, 17, 17)
node indexes_17 = cat(_indexes_T_34, _indexes_T_35)
node _indexes_T_36 = bits(cam_a[0].bits.data, 18, 18)
node _indexes_T_37 = bits(cam_d[0].data, 18, 18)
node indexes_18 = cat(_indexes_T_36, _indexes_T_37)
node _indexes_T_38 = bits(cam_a[0].bits.data, 19, 19)
node _indexes_T_39 = bits(cam_d[0].data, 19, 19)
node indexes_19 = cat(_indexes_T_38, _indexes_T_39)
node _indexes_T_40 = bits(cam_a[0].bits.data, 20, 20)
node _indexes_T_41 = bits(cam_d[0].data, 20, 20)
node indexes_20 = cat(_indexes_T_40, _indexes_T_41)
node _indexes_T_42 = bits(cam_a[0].bits.data, 21, 21)
node _indexes_T_43 = bits(cam_d[0].data, 21, 21)
node indexes_21 = cat(_indexes_T_42, _indexes_T_43)
node _indexes_T_44 = bits(cam_a[0].bits.data, 22, 22)
node _indexes_T_45 = bits(cam_d[0].data, 22, 22)
node indexes_22 = cat(_indexes_T_44, _indexes_T_45)
node _indexes_T_46 = bits(cam_a[0].bits.data, 23, 23)
node _indexes_T_47 = bits(cam_d[0].data, 23, 23)
node indexes_23 = cat(_indexes_T_46, _indexes_T_47)
node _indexes_T_48 = bits(cam_a[0].bits.data, 24, 24)
node _indexes_T_49 = bits(cam_d[0].data, 24, 24)
node indexes_24 = cat(_indexes_T_48, _indexes_T_49)
node _indexes_T_50 = bits(cam_a[0].bits.data, 25, 25)
node _indexes_T_51 = bits(cam_d[0].data, 25, 25)
node indexes_25 = cat(_indexes_T_50, _indexes_T_51)
node _indexes_T_52 = bits(cam_a[0].bits.data, 26, 26)
node _indexes_T_53 = bits(cam_d[0].data, 26, 26)
node indexes_26 = cat(_indexes_T_52, _indexes_T_53)
node _indexes_T_54 = bits(cam_a[0].bits.data, 27, 27)
node _indexes_T_55 = bits(cam_d[0].data, 27, 27)
node indexes_27 = cat(_indexes_T_54, _indexes_T_55)
node _indexes_T_56 = bits(cam_a[0].bits.data, 28, 28)
node _indexes_T_57 = bits(cam_d[0].data, 28, 28)
node indexes_28 = cat(_indexes_T_56, _indexes_T_57)
node _indexes_T_58 = bits(cam_a[0].bits.data, 29, 29)
node _indexes_T_59 = bits(cam_d[0].data, 29, 29)
node indexes_29 = cat(_indexes_T_58, _indexes_T_59)
node _indexes_T_60 = bits(cam_a[0].bits.data, 30, 30)
node _indexes_T_61 = bits(cam_d[0].data, 30, 30)
node indexes_30 = cat(_indexes_T_60, _indexes_T_61)
node _indexes_T_62 = bits(cam_a[0].bits.data, 31, 31)
node _indexes_T_63 = bits(cam_d[0].data, 31, 31)
node indexes_31 = cat(_indexes_T_62, _indexes_T_63)
node _indexes_T_64 = bits(cam_a[0].bits.data, 32, 32)
node _indexes_T_65 = bits(cam_d[0].data, 32, 32)
node indexes_32 = cat(_indexes_T_64, _indexes_T_65)
node _indexes_T_66 = bits(cam_a[0].bits.data, 33, 33)
node _indexes_T_67 = bits(cam_d[0].data, 33, 33)
node indexes_33 = cat(_indexes_T_66, _indexes_T_67)
node _indexes_T_68 = bits(cam_a[0].bits.data, 34, 34)
node _indexes_T_69 = bits(cam_d[0].data, 34, 34)
node indexes_34 = cat(_indexes_T_68, _indexes_T_69)
node _indexes_T_70 = bits(cam_a[0].bits.data, 35, 35)
node _indexes_T_71 = bits(cam_d[0].data, 35, 35)
node indexes_35 = cat(_indexes_T_70, _indexes_T_71)
node _indexes_T_72 = bits(cam_a[0].bits.data, 36, 36)
node _indexes_T_73 = bits(cam_d[0].data, 36, 36)
node indexes_36 = cat(_indexes_T_72, _indexes_T_73)
node _indexes_T_74 = bits(cam_a[0].bits.data, 37, 37)
node _indexes_T_75 = bits(cam_d[0].data, 37, 37)
node indexes_37 = cat(_indexes_T_74, _indexes_T_75)
node _indexes_T_76 = bits(cam_a[0].bits.data, 38, 38)
node _indexes_T_77 = bits(cam_d[0].data, 38, 38)
node indexes_38 = cat(_indexes_T_76, _indexes_T_77)
node _indexes_T_78 = bits(cam_a[0].bits.data, 39, 39)
node _indexes_T_79 = bits(cam_d[0].data, 39, 39)
node indexes_39 = cat(_indexes_T_78, _indexes_T_79)
node _indexes_T_80 = bits(cam_a[0].bits.data, 40, 40)
node _indexes_T_81 = bits(cam_d[0].data, 40, 40)
node indexes_40 = cat(_indexes_T_80, _indexes_T_81)
node _indexes_T_82 = bits(cam_a[0].bits.data, 41, 41)
node _indexes_T_83 = bits(cam_d[0].data, 41, 41)
node indexes_41 = cat(_indexes_T_82, _indexes_T_83)
node _indexes_T_84 = bits(cam_a[0].bits.data, 42, 42)
node _indexes_T_85 = bits(cam_d[0].data, 42, 42)
node indexes_42 = cat(_indexes_T_84, _indexes_T_85)
node _indexes_T_86 = bits(cam_a[0].bits.data, 43, 43)
node _indexes_T_87 = bits(cam_d[0].data, 43, 43)
node indexes_43 = cat(_indexes_T_86, _indexes_T_87)
node _indexes_T_88 = bits(cam_a[0].bits.data, 44, 44)
node _indexes_T_89 = bits(cam_d[0].data, 44, 44)
node indexes_44 = cat(_indexes_T_88, _indexes_T_89)
node _indexes_T_90 = bits(cam_a[0].bits.data, 45, 45)
node _indexes_T_91 = bits(cam_d[0].data, 45, 45)
node indexes_45 = cat(_indexes_T_90, _indexes_T_91)
node _indexes_T_92 = bits(cam_a[0].bits.data, 46, 46)
node _indexes_T_93 = bits(cam_d[0].data, 46, 46)
node indexes_46 = cat(_indexes_T_92, _indexes_T_93)
node _indexes_T_94 = bits(cam_a[0].bits.data, 47, 47)
node _indexes_T_95 = bits(cam_d[0].data, 47, 47)
node indexes_47 = cat(_indexes_T_94, _indexes_T_95)
node _indexes_T_96 = bits(cam_a[0].bits.data, 48, 48)
node _indexes_T_97 = bits(cam_d[0].data, 48, 48)
node indexes_48 = cat(_indexes_T_96, _indexes_T_97)
node _indexes_T_98 = bits(cam_a[0].bits.data, 49, 49)
node _indexes_T_99 = bits(cam_d[0].data, 49, 49)
node indexes_49 = cat(_indexes_T_98, _indexes_T_99)
node _indexes_T_100 = bits(cam_a[0].bits.data, 50, 50)
node _indexes_T_101 = bits(cam_d[0].data, 50, 50)
node indexes_50 = cat(_indexes_T_100, _indexes_T_101)
node _indexes_T_102 = bits(cam_a[0].bits.data, 51, 51)
node _indexes_T_103 = bits(cam_d[0].data, 51, 51)
node indexes_51 = cat(_indexes_T_102, _indexes_T_103)
node _indexes_T_104 = bits(cam_a[0].bits.data, 52, 52)
node _indexes_T_105 = bits(cam_d[0].data, 52, 52)
node indexes_52 = cat(_indexes_T_104, _indexes_T_105)
node _indexes_T_106 = bits(cam_a[0].bits.data, 53, 53)
node _indexes_T_107 = bits(cam_d[0].data, 53, 53)
node indexes_53 = cat(_indexes_T_106, _indexes_T_107)
node _indexes_T_108 = bits(cam_a[0].bits.data, 54, 54)
node _indexes_T_109 = bits(cam_d[0].data, 54, 54)
node indexes_54 = cat(_indexes_T_108, _indexes_T_109)
node _indexes_T_110 = bits(cam_a[0].bits.data, 55, 55)
node _indexes_T_111 = bits(cam_d[0].data, 55, 55)
node indexes_55 = cat(_indexes_T_110, _indexes_T_111)
node _indexes_T_112 = bits(cam_a[0].bits.data, 56, 56)
node _indexes_T_113 = bits(cam_d[0].data, 56, 56)
node indexes_56 = cat(_indexes_T_112, _indexes_T_113)
node _indexes_T_114 = bits(cam_a[0].bits.data, 57, 57)
node _indexes_T_115 = bits(cam_d[0].data, 57, 57)
node indexes_57 = cat(_indexes_T_114, _indexes_T_115)
node _indexes_T_116 = bits(cam_a[0].bits.data, 58, 58)
node _indexes_T_117 = bits(cam_d[0].data, 58, 58)
node indexes_58 = cat(_indexes_T_116, _indexes_T_117)
node _indexes_T_118 = bits(cam_a[0].bits.data, 59, 59)
node _indexes_T_119 = bits(cam_d[0].data, 59, 59)
node indexes_59 = cat(_indexes_T_118, _indexes_T_119)
node _indexes_T_120 = bits(cam_a[0].bits.data, 60, 60)
node _indexes_T_121 = bits(cam_d[0].data, 60, 60)
node indexes_60 = cat(_indexes_T_120, _indexes_T_121)
node _indexes_T_122 = bits(cam_a[0].bits.data, 61, 61)
node _indexes_T_123 = bits(cam_d[0].data, 61, 61)
node indexes_61 = cat(_indexes_T_122, _indexes_T_123)
node _indexes_T_124 = bits(cam_a[0].bits.data, 62, 62)
node _indexes_T_125 = bits(cam_d[0].data, 62, 62)
node indexes_62 = cat(_indexes_T_124, _indexes_T_125)
node _indexes_T_126 = bits(cam_a[0].bits.data, 63, 63)
node _indexes_T_127 = bits(cam_d[0].data, 63, 63)
node indexes_63 = cat(_indexes_T_126, _indexes_T_127)
node _logic_out_T = dshr(cam_a[0].lut, indexes_0)
node _logic_out_T_1 = bits(_logic_out_T, 0, 0)
node _logic_out_T_2 = dshr(cam_a[0].lut, indexes_1)
node _logic_out_T_3 = bits(_logic_out_T_2, 0, 0)
node _logic_out_T_4 = dshr(cam_a[0].lut, indexes_2)
node _logic_out_T_5 = bits(_logic_out_T_4, 0, 0)
node _logic_out_T_6 = dshr(cam_a[0].lut, indexes_3)
node _logic_out_T_7 = bits(_logic_out_T_6, 0, 0)
node _logic_out_T_8 = dshr(cam_a[0].lut, indexes_4)
node _logic_out_T_9 = bits(_logic_out_T_8, 0, 0)
node _logic_out_T_10 = dshr(cam_a[0].lut, indexes_5)
node _logic_out_T_11 = bits(_logic_out_T_10, 0, 0)
node _logic_out_T_12 = dshr(cam_a[0].lut, indexes_6)
node _logic_out_T_13 = bits(_logic_out_T_12, 0, 0)
node _logic_out_T_14 = dshr(cam_a[0].lut, indexes_7)
node _logic_out_T_15 = bits(_logic_out_T_14, 0, 0)
node _logic_out_T_16 = dshr(cam_a[0].lut, indexes_8)
node _logic_out_T_17 = bits(_logic_out_T_16, 0, 0)
node _logic_out_T_18 = dshr(cam_a[0].lut, indexes_9)
node _logic_out_T_19 = bits(_logic_out_T_18, 0, 0)
node _logic_out_T_20 = dshr(cam_a[0].lut, indexes_10)
node _logic_out_T_21 = bits(_logic_out_T_20, 0, 0)
node _logic_out_T_22 = dshr(cam_a[0].lut, indexes_11)
node _logic_out_T_23 = bits(_logic_out_T_22, 0, 0)
node _logic_out_T_24 = dshr(cam_a[0].lut, indexes_12)
node _logic_out_T_25 = bits(_logic_out_T_24, 0, 0)
node _logic_out_T_26 = dshr(cam_a[0].lut, indexes_13)
node _logic_out_T_27 = bits(_logic_out_T_26, 0, 0)
node _logic_out_T_28 = dshr(cam_a[0].lut, indexes_14)
node _logic_out_T_29 = bits(_logic_out_T_28, 0, 0)
node _logic_out_T_30 = dshr(cam_a[0].lut, indexes_15)
node _logic_out_T_31 = bits(_logic_out_T_30, 0, 0)
node _logic_out_T_32 = dshr(cam_a[0].lut, indexes_16)
node _logic_out_T_33 = bits(_logic_out_T_32, 0, 0)
node _logic_out_T_34 = dshr(cam_a[0].lut, indexes_17)
node _logic_out_T_35 = bits(_logic_out_T_34, 0, 0)
node _logic_out_T_36 = dshr(cam_a[0].lut, indexes_18)
node _logic_out_T_37 = bits(_logic_out_T_36, 0, 0)
node _logic_out_T_38 = dshr(cam_a[0].lut, indexes_19)
node _logic_out_T_39 = bits(_logic_out_T_38, 0, 0)
node _logic_out_T_40 = dshr(cam_a[0].lut, indexes_20)
node _logic_out_T_41 = bits(_logic_out_T_40, 0, 0)
node _logic_out_T_42 = dshr(cam_a[0].lut, indexes_21)
node _logic_out_T_43 = bits(_logic_out_T_42, 0, 0)
node _logic_out_T_44 = dshr(cam_a[0].lut, indexes_22)
node _logic_out_T_45 = bits(_logic_out_T_44, 0, 0)
node _logic_out_T_46 = dshr(cam_a[0].lut, indexes_23)
node _logic_out_T_47 = bits(_logic_out_T_46, 0, 0)
node _logic_out_T_48 = dshr(cam_a[0].lut, indexes_24)
node _logic_out_T_49 = bits(_logic_out_T_48, 0, 0)
node _logic_out_T_50 = dshr(cam_a[0].lut, indexes_25)
node _logic_out_T_51 = bits(_logic_out_T_50, 0, 0)
node _logic_out_T_52 = dshr(cam_a[0].lut, indexes_26)
node _logic_out_T_53 = bits(_logic_out_T_52, 0, 0)
node _logic_out_T_54 = dshr(cam_a[0].lut, indexes_27)
node _logic_out_T_55 = bits(_logic_out_T_54, 0, 0)
node _logic_out_T_56 = dshr(cam_a[0].lut, indexes_28)
node _logic_out_T_57 = bits(_logic_out_T_56, 0, 0)
node _logic_out_T_58 = dshr(cam_a[0].lut, indexes_29)
node _logic_out_T_59 = bits(_logic_out_T_58, 0, 0)
node _logic_out_T_60 = dshr(cam_a[0].lut, indexes_30)
node _logic_out_T_61 = bits(_logic_out_T_60, 0, 0)
node _logic_out_T_62 = dshr(cam_a[0].lut, indexes_31)
node _logic_out_T_63 = bits(_logic_out_T_62, 0, 0)
node _logic_out_T_64 = dshr(cam_a[0].lut, indexes_32)
node _logic_out_T_65 = bits(_logic_out_T_64, 0, 0)
node _logic_out_T_66 = dshr(cam_a[0].lut, indexes_33)
node _logic_out_T_67 = bits(_logic_out_T_66, 0, 0)
node _logic_out_T_68 = dshr(cam_a[0].lut, indexes_34)
node _logic_out_T_69 = bits(_logic_out_T_68, 0, 0)
node _logic_out_T_70 = dshr(cam_a[0].lut, indexes_35)
node _logic_out_T_71 = bits(_logic_out_T_70, 0, 0)
node _logic_out_T_72 = dshr(cam_a[0].lut, indexes_36)
node _logic_out_T_73 = bits(_logic_out_T_72, 0, 0)
node _logic_out_T_74 = dshr(cam_a[0].lut, indexes_37)
node _logic_out_T_75 = bits(_logic_out_T_74, 0, 0)
node _logic_out_T_76 = dshr(cam_a[0].lut, indexes_38)
node _logic_out_T_77 = bits(_logic_out_T_76, 0, 0)
node _logic_out_T_78 = dshr(cam_a[0].lut, indexes_39)
node _logic_out_T_79 = bits(_logic_out_T_78, 0, 0)
node _logic_out_T_80 = dshr(cam_a[0].lut, indexes_40)
node _logic_out_T_81 = bits(_logic_out_T_80, 0, 0)
node _logic_out_T_82 = dshr(cam_a[0].lut, indexes_41)
node _logic_out_T_83 = bits(_logic_out_T_82, 0, 0)
node _logic_out_T_84 = dshr(cam_a[0].lut, indexes_42)
node _logic_out_T_85 = bits(_logic_out_T_84, 0, 0)
node _logic_out_T_86 = dshr(cam_a[0].lut, indexes_43)
node _logic_out_T_87 = bits(_logic_out_T_86, 0, 0)
node _logic_out_T_88 = dshr(cam_a[0].lut, indexes_44)
node _logic_out_T_89 = bits(_logic_out_T_88, 0, 0)
node _logic_out_T_90 = dshr(cam_a[0].lut, indexes_45)
node _logic_out_T_91 = bits(_logic_out_T_90, 0, 0)
node _logic_out_T_92 = dshr(cam_a[0].lut, indexes_46)
node _logic_out_T_93 = bits(_logic_out_T_92, 0, 0)
node _logic_out_T_94 = dshr(cam_a[0].lut, indexes_47)
node _logic_out_T_95 = bits(_logic_out_T_94, 0, 0)
node _logic_out_T_96 = dshr(cam_a[0].lut, indexes_48)
node _logic_out_T_97 = bits(_logic_out_T_96, 0, 0)
node _logic_out_T_98 = dshr(cam_a[0].lut, indexes_49)
node _logic_out_T_99 = bits(_logic_out_T_98, 0, 0)
node _logic_out_T_100 = dshr(cam_a[0].lut, indexes_50)
node _logic_out_T_101 = bits(_logic_out_T_100, 0, 0)
node _logic_out_T_102 = dshr(cam_a[0].lut, indexes_51)
node _logic_out_T_103 = bits(_logic_out_T_102, 0, 0)
node _logic_out_T_104 = dshr(cam_a[0].lut, indexes_52)
node _logic_out_T_105 = bits(_logic_out_T_104, 0, 0)
node _logic_out_T_106 = dshr(cam_a[0].lut, indexes_53)
node _logic_out_T_107 = bits(_logic_out_T_106, 0, 0)
node _logic_out_T_108 = dshr(cam_a[0].lut, indexes_54)
node _logic_out_T_109 = bits(_logic_out_T_108, 0, 0)
node _logic_out_T_110 = dshr(cam_a[0].lut, indexes_55)
node _logic_out_T_111 = bits(_logic_out_T_110, 0, 0)
node _logic_out_T_112 = dshr(cam_a[0].lut, indexes_56)
node _logic_out_T_113 = bits(_logic_out_T_112, 0, 0)
node _logic_out_T_114 = dshr(cam_a[0].lut, indexes_57)
node _logic_out_T_115 = bits(_logic_out_T_114, 0, 0)
node _logic_out_T_116 = dshr(cam_a[0].lut, indexes_58)
node _logic_out_T_117 = bits(_logic_out_T_116, 0, 0)
node _logic_out_T_118 = dshr(cam_a[0].lut, indexes_59)
node _logic_out_T_119 = bits(_logic_out_T_118, 0, 0)
node _logic_out_T_120 = dshr(cam_a[0].lut, indexes_60)
node _logic_out_T_121 = bits(_logic_out_T_120, 0, 0)
node _logic_out_T_122 = dshr(cam_a[0].lut, indexes_61)
node _logic_out_T_123 = bits(_logic_out_T_122, 0, 0)
node _logic_out_T_124 = dshr(cam_a[0].lut, indexes_62)
node _logic_out_T_125 = bits(_logic_out_T_124, 0, 0)
node _logic_out_T_126 = dshr(cam_a[0].lut, indexes_63)
node _logic_out_T_127 = bits(_logic_out_T_126, 0, 0)
node logic_out_lo_lo_lo_lo_lo = cat(_logic_out_T_3, _logic_out_T_1)
node logic_out_lo_lo_lo_lo_hi = cat(_logic_out_T_7, _logic_out_T_5)
node logic_out_lo_lo_lo_lo = cat(logic_out_lo_lo_lo_lo_hi, logic_out_lo_lo_lo_lo_lo)
node logic_out_lo_lo_lo_hi_lo = cat(_logic_out_T_11, _logic_out_T_9)
node logic_out_lo_lo_lo_hi_hi = cat(_logic_out_T_15, _logic_out_T_13)
node logic_out_lo_lo_lo_hi = cat(logic_out_lo_lo_lo_hi_hi, logic_out_lo_lo_lo_hi_lo)
node logic_out_lo_lo_lo = cat(logic_out_lo_lo_lo_hi, logic_out_lo_lo_lo_lo)
node logic_out_lo_lo_hi_lo_lo = cat(_logic_out_T_19, _logic_out_T_17)
node logic_out_lo_lo_hi_lo_hi = cat(_logic_out_T_23, _logic_out_T_21)
node logic_out_lo_lo_hi_lo = cat(logic_out_lo_lo_hi_lo_hi, logic_out_lo_lo_hi_lo_lo)
node logic_out_lo_lo_hi_hi_lo = cat(_logic_out_T_27, _logic_out_T_25)
node logic_out_lo_lo_hi_hi_hi = cat(_logic_out_T_31, _logic_out_T_29)
node logic_out_lo_lo_hi_hi = cat(logic_out_lo_lo_hi_hi_hi, logic_out_lo_lo_hi_hi_lo)
node logic_out_lo_lo_hi = cat(logic_out_lo_lo_hi_hi, logic_out_lo_lo_hi_lo)
node logic_out_lo_lo = cat(logic_out_lo_lo_hi, logic_out_lo_lo_lo)
node logic_out_lo_hi_lo_lo_lo = cat(_logic_out_T_35, _logic_out_T_33)
node logic_out_lo_hi_lo_lo_hi = cat(_logic_out_T_39, _logic_out_T_37)
node logic_out_lo_hi_lo_lo = cat(logic_out_lo_hi_lo_lo_hi, logic_out_lo_hi_lo_lo_lo)
node logic_out_lo_hi_lo_hi_lo = cat(_logic_out_T_43, _logic_out_T_41)
node logic_out_lo_hi_lo_hi_hi = cat(_logic_out_T_47, _logic_out_T_45)
node logic_out_lo_hi_lo_hi = cat(logic_out_lo_hi_lo_hi_hi, logic_out_lo_hi_lo_hi_lo)
node logic_out_lo_hi_lo = cat(logic_out_lo_hi_lo_hi, logic_out_lo_hi_lo_lo)
node logic_out_lo_hi_hi_lo_lo = cat(_logic_out_T_51, _logic_out_T_49)
node logic_out_lo_hi_hi_lo_hi = cat(_logic_out_T_55, _logic_out_T_53)
node logic_out_lo_hi_hi_lo = cat(logic_out_lo_hi_hi_lo_hi, logic_out_lo_hi_hi_lo_lo)
node logic_out_lo_hi_hi_hi_lo = cat(_logic_out_T_59, _logic_out_T_57)
node logic_out_lo_hi_hi_hi_hi = cat(_logic_out_T_63, _logic_out_T_61)
node logic_out_lo_hi_hi_hi = cat(logic_out_lo_hi_hi_hi_hi, logic_out_lo_hi_hi_hi_lo)
node logic_out_lo_hi_hi = cat(logic_out_lo_hi_hi_hi, logic_out_lo_hi_hi_lo)
node logic_out_lo_hi = cat(logic_out_lo_hi_hi, logic_out_lo_hi_lo)
node logic_out_lo = cat(logic_out_lo_hi, logic_out_lo_lo)
node logic_out_hi_lo_lo_lo_lo = cat(_logic_out_T_67, _logic_out_T_65)
node logic_out_hi_lo_lo_lo_hi = cat(_logic_out_T_71, _logic_out_T_69)
node logic_out_hi_lo_lo_lo = cat(logic_out_hi_lo_lo_lo_hi, logic_out_hi_lo_lo_lo_lo)
node logic_out_hi_lo_lo_hi_lo = cat(_logic_out_T_75, _logic_out_T_73)
node logic_out_hi_lo_lo_hi_hi = cat(_logic_out_T_79, _logic_out_T_77)
node logic_out_hi_lo_lo_hi = cat(logic_out_hi_lo_lo_hi_hi, logic_out_hi_lo_lo_hi_lo)
node logic_out_hi_lo_lo = cat(logic_out_hi_lo_lo_hi, logic_out_hi_lo_lo_lo)
node logic_out_hi_lo_hi_lo_lo = cat(_logic_out_T_83, _logic_out_T_81)
node logic_out_hi_lo_hi_lo_hi = cat(_logic_out_T_87, _logic_out_T_85)
node logic_out_hi_lo_hi_lo = cat(logic_out_hi_lo_hi_lo_hi, logic_out_hi_lo_hi_lo_lo)
node logic_out_hi_lo_hi_hi_lo = cat(_logic_out_T_91, _logic_out_T_89)
node logic_out_hi_lo_hi_hi_hi = cat(_logic_out_T_95, _logic_out_T_93)
node logic_out_hi_lo_hi_hi = cat(logic_out_hi_lo_hi_hi_hi, logic_out_hi_lo_hi_hi_lo)
node logic_out_hi_lo_hi = cat(logic_out_hi_lo_hi_hi, logic_out_hi_lo_hi_lo)
node logic_out_hi_lo = cat(logic_out_hi_lo_hi, logic_out_hi_lo_lo)
node logic_out_hi_hi_lo_lo_lo = cat(_logic_out_T_99, _logic_out_T_97)
node logic_out_hi_hi_lo_lo_hi = cat(_logic_out_T_103, _logic_out_T_101)
node logic_out_hi_hi_lo_lo = cat(logic_out_hi_hi_lo_lo_hi, logic_out_hi_hi_lo_lo_lo)
node logic_out_hi_hi_lo_hi_lo = cat(_logic_out_T_107, _logic_out_T_105)
node logic_out_hi_hi_lo_hi_hi = cat(_logic_out_T_111, _logic_out_T_109)
node logic_out_hi_hi_lo_hi = cat(logic_out_hi_hi_lo_hi_hi, logic_out_hi_hi_lo_hi_lo)
node logic_out_hi_hi_lo = cat(logic_out_hi_hi_lo_hi, logic_out_hi_hi_lo_lo)
node logic_out_hi_hi_hi_lo_lo = cat(_logic_out_T_115, _logic_out_T_113)
node logic_out_hi_hi_hi_lo_hi = cat(_logic_out_T_119, _logic_out_T_117)
node logic_out_hi_hi_hi_lo = cat(logic_out_hi_hi_hi_lo_hi, logic_out_hi_hi_hi_lo_lo)
node logic_out_hi_hi_hi_hi_lo = cat(_logic_out_T_123, _logic_out_T_121)
node logic_out_hi_hi_hi_hi_hi = cat(_logic_out_T_127, _logic_out_T_125)
node logic_out_hi_hi_hi_hi = cat(logic_out_hi_hi_hi_hi_hi, logic_out_hi_hi_hi_hi_lo)
node logic_out_hi_hi_hi = cat(logic_out_hi_hi_hi_hi, logic_out_hi_hi_hi_lo)
node logic_out_hi_hi = cat(logic_out_hi_hi_hi, logic_out_hi_hi_lo)
node logic_out_hi = cat(logic_out_hi_hi, logic_out_hi_lo)
node logic_out = cat(logic_out_hi, logic_out_lo)
node unsigned = bits(cam_a[0].bits.param, 1, 1)
node take_max = bits(cam_a[0].bits.param, 0, 0)
node adder = bits(cam_a[0].bits.param, 2, 2)
node _signSel_T = not(cam_a[0].bits.mask)
node _signSel_T_1 = shr(cam_a[0].bits.mask, 1)
node _signSel_T_2 = or(_signSel_T, _signSel_T_1)
node signSel = not(_signSel_T_2)
node _signbits_a_T = bits(cam_a[0].bits.data, 7, 7)
node _signbits_a_T_1 = bits(cam_a[0].bits.data, 15, 15)
node _signbits_a_T_2 = bits(cam_a[0].bits.data, 23, 23)
node _signbits_a_T_3 = bits(cam_a[0].bits.data, 31, 31)
node _signbits_a_T_4 = bits(cam_a[0].bits.data, 39, 39)
node _signbits_a_T_5 = bits(cam_a[0].bits.data, 47, 47)
node _signbits_a_T_6 = bits(cam_a[0].bits.data, 55, 55)
node _signbits_a_T_7 = bits(cam_a[0].bits.data, 63, 63)
node signbits_a_lo_lo = cat(_signbits_a_T_1, _signbits_a_T)
node signbits_a_lo_hi = cat(_signbits_a_T_3, _signbits_a_T_2)
node signbits_a_lo = cat(signbits_a_lo_hi, signbits_a_lo_lo)
node signbits_a_hi_lo = cat(_signbits_a_T_5, _signbits_a_T_4)
node signbits_a_hi_hi = cat(_signbits_a_T_7, _signbits_a_T_6)
node signbits_a_hi = cat(signbits_a_hi_hi, signbits_a_hi_lo)
node signbits_a = cat(signbits_a_hi, signbits_a_lo)
node _signbits_d_T = bits(cam_d[0].data, 7, 7)
node _signbits_d_T_1 = bits(cam_d[0].data, 15, 15)
node _signbits_d_T_2 = bits(cam_d[0].data, 23, 23)
node _signbits_d_T_3 = bits(cam_d[0].data, 31, 31)
node _signbits_d_T_4 = bits(cam_d[0].data, 39, 39)
node _signbits_d_T_5 = bits(cam_d[0].data, 47, 47)
node _signbits_d_T_6 = bits(cam_d[0].data, 55, 55)
node _signbits_d_T_7 = bits(cam_d[0].data, 63, 63)
node signbits_d_lo_lo = cat(_signbits_d_T_1, _signbits_d_T)
node signbits_d_lo_hi = cat(_signbits_d_T_3, _signbits_d_T_2)
node signbits_d_lo = cat(signbits_d_lo_hi, signbits_d_lo_lo)
node signbits_d_hi_lo = cat(_signbits_d_T_5, _signbits_d_T_4)
node signbits_d_hi_hi = cat(_signbits_d_T_7, _signbits_d_T_6)
node signbits_d_hi = cat(signbits_d_hi_hi, signbits_d_hi_lo)
node signbits_d = cat(signbits_d_hi, signbits_d_lo)
node _signbit_a_T = and(signbits_a, signSel)
node _signbit_a_T_1 = shl(_signbit_a_T, 1)
node signbit_a = bits(_signbit_a_T_1, 7, 0)
node _signbit_d_T = and(signbits_d, signSel)
node _signbit_d_T_1 = shl(_signbit_d_T, 1)
node signbit_d = bits(_signbit_d_T_1, 7, 0)
node _signext_a_T = shl(signbit_a, 1)
node _signext_a_T_1 = bits(_signext_a_T, 7, 0)
node _signext_a_T_2 = or(signbit_a, _signext_a_T_1)
node _signext_a_T_3 = shl(_signext_a_T_2, 2)
node _signext_a_T_4 = bits(_signext_a_T_3, 7, 0)
node _signext_a_T_5 = or(_signext_a_T_2, _signext_a_T_4)
node _signext_a_T_6 = shl(_signext_a_T_5, 4)
node _signext_a_T_7 = bits(_signext_a_T_6, 7, 0)
node _signext_a_T_8 = or(_signext_a_T_5, _signext_a_T_7)
node _signext_a_T_9 = bits(_signext_a_T_8, 7, 0)
node _signext_a_T_10 = bits(_signext_a_T_9, 0, 0)
node _signext_a_T_11 = bits(_signext_a_T_9, 1, 1)
node _signext_a_T_12 = bits(_signext_a_T_9, 2, 2)
node _signext_a_T_13 = bits(_signext_a_T_9, 3, 3)
node _signext_a_T_14 = bits(_signext_a_T_9, 4, 4)
node _signext_a_T_15 = bits(_signext_a_T_9, 5, 5)
node _signext_a_T_16 = bits(_signext_a_T_9, 6, 6)
node _signext_a_T_17 = bits(_signext_a_T_9, 7, 7)
node _signext_a_T_18 = mux(_signext_a_T_10, UInt<8>(0hff), UInt<8>(0h0))
node _signext_a_T_19 = mux(_signext_a_T_11, UInt<8>(0hff), UInt<8>(0h0))
node _signext_a_T_20 = mux(_signext_a_T_12, UInt<8>(0hff), UInt<8>(0h0))
node _signext_a_T_21 = mux(_signext_a_T_13, UInt<8>(0hff), UInt<8>(0h0))
node _signext_a_T_22 = mux(_signext_a_T_14, UInt<8>(0hff), UInt<8>(0h0))
node _signext_a_T_23 = mux(_signext_a_T_15, UInt<8>(0hff), UInt<8>(0h0))
node _signext_a_T_24 = mux(_signext_a_T_16, UInt<8>(0hff), UInt<8>(0h0))
node _signext_a_T_25 = mux(_signext_a_T_17, UInt<8>(0hff), UInt<8>(0h0))
node signext_a_lo_lo = cat(_signext_a_T_19, _signext_a_T_18)
node signext_a_lo_hi = cat(_signext_a_T_21, _signext_a_T_20)
node signext_a_lo = cat(signext_a_lo_hi, signext_a_lo_lo)
node signext_a_hi_lo = cat(_signext_a_T_23, _signext_a_T_22)
node signext_a_hi_hi = cat(_signext_a_T_25, _signext_a_T_24)
node signext_a_hi = cat(signext_a_hi_hi, signext_a_hi_lo)
node signext_a = cat(signext_a_hi, signext_a_lo)
node _signext_d_T = shl(signbit_d, 1)
node _signext_d_T_1 = bits(_signext_d_T, 7, 0)
node _signext_d_T_2 = or(signbit_d, _signext_d_T_1)
node _signext_d_T_3 = shl(_signext_d_T_2, 2)
node _signext_d_T_4 = bits(_signext_d_T_3, 7, 0)
node _signext_d_T_5 = or(_signext_d_T_2, _signext_d_T_4)
node _signext_d_T_6 = shl(_signext_d_T_5, 4)
node _signext_d_T_7 = bits(_signext_d_T_6, 7, 0)
node _signext_d_T_8 = or(_signext_d_T_5, _signext_d_T_7)
node _signext_d_T_9 = bits(_signext_d_T_8, 7, 0)
node _signext_d_T_10 = bits(_signext_d_T_9, 0, 0)
node _signext_d_T_11 = bits(_signext_d_T_9, 1, 1)
node _signext_d_T_12 = bits(_signext_d_T_9, 2, 2)
node _signext_d_T_13 = bits(_signext_d_T_9, 3, 3)
node _signext_d_T_14 = bits(_signext_d_T_9, 4, 4)
node _signext_d_T_15 = bits(_signext_d_T_9, 5, 5)
node _signext_d_T_16 = bits(_signext_d_T_9, 6, 6)
node _signext_d_T_17 = bits(_signext_d_T_9, 7, 7)
node _signext_d_T_18 = mux(_signext_d_T_10, UInt<8>(0hff), UInt<8>(0h0))
node _signext_d_T_19 = mux(_signext_d_T_11, UInt<8>(0hff), UInt<8>(0h0))
node _signext_d_T_20 = mux(_signext_d_T_12, UInt<8>(0hff), UInt<8>(0h0))
node _signext_d_T_21 = mux(_signext_d_T_13, UInt<8>(0hff), UInt<8>(0h0))
node _signext_d_T_22 = mux(_signext_d_T_14, UInt<8>(0hff), UInt<8>(0h0))
node _signext_d_T_23 = mux(_signext_d_T_15, UInt<8>(0hff), UInt<8>(0h0))
node _signext_d_T_24 = mux(_signext_d_T_16, UInt<8>(0hff), UInt<8>(0h0))
node _signext_d_T_25 = mux(_signext_d_T_17, UInt<8>(0hff), UInt<8>(0h0))
node signext_d_lo_lo = cat(_signext_d_T_19, _signext_d_T_18)
node signext_d_lo_hi = cat(_signext_d_T_21, _signext_d_T_20)
node signext_d_lo = cat(signext_d_lo_hi, signext_d_lo_lo)
node signext_d_hi_lo = cat(_signext_d_T_23, _signext_d_T_22)
node signext_d_hi_hi = cat(_signext_d_T_25, _signext_d_T_24)
node signext_d_hi = cat(signext_d_hi_hi, signext_d_hi_lo)
node signext_d = cat(signext_d_hi, signext_d_lo)
node _wide_mask_T = bits(cam_a[0].bits.mask, 0, 0)
node _wide_mask_T_1 = bits(cam_a[0].bits.mask, 1, 1)
node _wide_mask_T_2 = bits(cam_a[0].bits.mask, 2, 2)
node _wide_mask_T_3 = bits(cam_a[0].bits.mask, 3, 3)
node _wide_mask_T_4 = bits(cam_a[0].bits.mask, 4, 4)
node _wide_mask_T_5 = bits(cam_a[0].bits.mask, 5, 5)
node _wide_mask_T_6 = bits(cam_a[0].bits.mask, 6, 6)
node _wide_mask_T_7 = bits(cam_a[0].bits.mask, 7, 7)
node _wide_mask_T_8 = mux(_wide_mask_T, UInt<8>(0hff), UInt<8>(0h0))
node _wide_mask_T_9 = mux(_wide_mask_T_1, UInt<8>(0hff), UInt<8>(0h0))
node _wide_mask_T_10 = mux(_wide_mask_T_2, UInt<8>(0hff), UInt<8>(0h0))
node _wide_mask_T_11 = mux(_wide_mask_T_3, UInt<8>(0hff), UInt<8>(0h0))
node _wide_mask_T_12 = mux(_wide_mask_T_4, UInt<8>(0hff), UInt<8>(0h0))
node _wide_mask_T_13 = mux(_wide_mask_T_5, UInt<8>(0hff), UInt<8>(0h0))
node _wide_mask_T_14 = mux(_wide_mask_T_6, UInt<8>(0hff), UInt<8>(0h0))
node _wide_mask_T_15 = mux(_wide_mask_T_7, UInt<8>(0hff), UInt<8>(0h0))
node wide_mask_lo_lo = cat(_wide_mask_T_9, _wide_mask_T_8)
node wide_mask_lo_hi = cat(_wide_mask_T_11, _wide_mask_T_10)
node wide_mask_lo = cat(wide_mask_lo_hi, wide_mask_lo_lo)
node wide_mask_hi_lo = cat(_wide_mask_T_13, _wide_mask_T_12)
node wide_mask_hi_hi = cat(_wide_mask_T_15, _wide_mask_T_14)
node wide_mask_hi = cat(wide_mask_hi_hi, wide_mask_hi_lo)
node wide_mask = cat(wide_mask_hi, wide_mask_lo)
node _a_a_ext_T = and(cam_a[0].bits.data, wide_mask)
node a_a_ext = or(_a_a_ext_T, signext_a)
node _a_d_ext_T = and(cam_d[0].data, wide_mask)
node a_d_ext = or(_a_d_ext_T, signext_d)
node _a_d_inv_T = not(a_d_ext)
node a_d_inv = mux(adder, a_d_ext, _a_d_inv_T)
node _adder_out_T = add(a_a_ext, a_d_inv)
node adder_out = tail(_adder_out_T, 1)
node _a_bigger_uneq_T = bits(a_a_ext, 63, 63)
node a_bigger_uneq = eq(unsigned, _a_bigger_uneq_T)
node _a_bigger_T = bits(a_a_ext, 63, 63)
node _a_bigger_T_1 = bits(a_d_ext, 63, 63)
node _a_bigger_T_2 = eq(_a_bigger_T, _a_bigger_T_1)
node _a_bigger_T_3 = bits(adder_out, 63, 63)
node _a_bigger_T_4 = eq(_a_bigger_T_3, UInt<1>(0h0))
node a_bigger = mux(_a_bigger_T_2, _a_bigger_T_4, a_bigger_uneq)
node pick_a = eq(take_max, a_bigger)
node _arith_out_T = mux(pick_a, cam_a[0].bits.data, cam_d[0].data)
node arith_out = mux(adder, adder_out, _arith_out_T)
node _amo_data_T = bits(cam_a[0].bits.opcode, 0, 0)
node amo_data = mux(_amo_data_T, logic_out, arith_out)
wire source_i : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
node _a_allow_T = eq(a_cam_busy, UInt<1>(0h0))
node _a_allow_T_1 = or(a_isSupported, cam_free_0)
node a_allow = and(_a_allow_T, _a_allow_T_1)
node _nodeIn_a_ready_T = and(source_i.ready, a_allow)
connect nodeIn.a.ready, _nodeIn_a_ready_T
node _source_i_valid_T = and(nodeIn.a.valid, a_allow)
connect source_i.valid, _source_i_valid_T
connect source_i.bits, nodeIn.a.bits
node _T = eq(a_isSupported, UInt<1>(0h0))
when _T :
connect source_i.bits.opcode, UInt<3>(0h4)
connect source_i.bits.param, UInt<1>(0h0)
wire source_c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect source_c.valid, cam_amo_0
node _source_c_bits_T = or(cam_a[0].bits.corrupt, cam_d[0].corrupt)
node _source_c_bits_legal_T = leq(UInt<1>(0h0), cam_a[0].bits.size)
node _source_c_bits_legal_T_1 = leq(cam_a[0].bits.size, UInt<4>(0hc))
node _source_c_bits_legal_T_2 = and(_source_c_bits_legal_T, _source_c_bits_legal_T_1)
node _source_c_bits_legal_T_3 = or(UInt<1>(0h0), _source_c_bits_legal_T_2)
node _source_c_bits_legal_T_4 = xor(cam_a[0].bits.address, UInt<14>(0h3000))
node _source_c_bits_legal_T_5 = cvt(_source_c_bits_legal_T_4)
node _source_c_bits_legal_T_6 = and(_source_c_bits_legal_T_5, asSInt(UInt<33>(0h8a113000)))
node _source_c_bits_legal_T_7 = asSInt(_source_c_bits_legal_T_6)
node _source_c_bits_legal_T_8 = eq(_source_c_bits_legal_T_7, asSInt(UInt<1>(0h0)))
node _source_c_bits_legal_T_9 = and(_source_c_bits_legal_T_3, _source_c_bits_legal_T_8)
node _source_c_bits_legal_T_10 = leq(UInt<1>(0h0), cam_a[0].bits.size)
node _source_c_bits_legal_T_11 = leq(cam_a[0].bits.size, UInt<3>(0h6))
node _source_c_bits_legal_T_12 = and(_source_c_bits_legal_T_10, _source_c_bits_legal_T_11)
node _source_c_bits_legal_T_13 = or(UInt<1>(0h0), _source_c_bits_legal_T_12)
node _source_c_bits_legal_T_14 = xor(cam_a[0].bits.address, UInt<1>(0h0))
node _source_c_bits_legal_T_15 = cvt(_source_c_bits_legal_T_14)
node _source_c_bits_legal_T_16 = and(_source_c_bits_legal_T_15, asSInt(UInt<33>(0h8a112000)))
node _source_c_bits_legal_T_17 = asSInt(_source_c_bits_legal_T_16)
node _source_c_bits_legal_T_18 = eq(_source_c_bits_legal_T_17, asSInt(UInt<1>(0h0)))
node _source_c_bits_legal_T_19 = xor(cam_a[0].bits.address, UInt<21>(0h100000))
node _source_c_bits_legal_T_20 = cvt(_source_c_bits_legal_T_19)
node _source_c_bits_legal_T_21 = and(_source_c_bits_legal_T_20, asSInt(UInt<33>(0h8a103000)))
node _source_c_bits_legal_T_22 = asSInt(_source_c_bits_legal_T_21)
node _source_c_bits_legal_T_23 = eq(_source_c_bits_legal_T_22, asSInt(UInt<1>(0h0)))
node _source_c_bits_legal_T_24 = xor(cam_a[0].bits.address, UInt<26>(0h2000000))
node _source_c_bits_legal_T_25 = cvt(_source_c_bits_legal_T_24)
node _source_c_bits_legal_T_26 = and(_source_c_bits_legal_T_25, asSInt(UInt<33>(0h8a110000)))
node _source_c_bits_legal_T_27 = asSInt(_source_c_bits_legal_T_26)
node _source_c_bits_legal_T_28 = eq(_source_c_bits_legal_T_27, asSInt(UInt<1>(0h0)))
node _source_c_bits_legal_T_29 = xor(cam_a[0].bits.address, UInt<28>(0h8000000))
node _source_c_bits_legal_T_30 = cvt(_source_c_bits_legal_T_29)
node _source_c_bits_legal_T_31 = and(_source_c_bits_legal_T_30, asSInt(UInt<33>(0h88000000)))
node _source_c_bits_legal_T_32 = asSInt(_source_c_bits_legal_T_31)
node _source_c_bits_legal_T_33 = eq(_source_c_bits_legal_T_32, asSInt(UInt<1>(0h0)))
node _source_c_bits_legal_T_34 = xor(cam_a[0].bits.address, UInt<32>(0h80000000))
node _source_c_bits_legal_T_35 = cvt(_source_c_bits_legal_T_34)
node _source_c_bits_legal_T_36 = and(_source_c_bits_legal_T_35, asSInt(UInt<33>(0h8a110000)))
node _source_c_bits_legal_T_37 = asSInt(_source_c_bits_legal_T_36)
node _source_c_bits_legal_T_38 = eq(_source_c_bits_legal_T_37, asSInt(UInt<1>(0h0)))
node _source_c_bits_legal_T_39 = or(_source_c_bits_legal_T_18, _source_c_bits_legal_T_23)
node _source_c_bits_legal_T_40 = or(_source_c_bits_legal_T_39, _source_c_bits_legal_T_28)
node _source_c_bits_legal_T_41 = or(_source_c_bits_legal_T_40, _source_c_bits_legal_T_33)
node _source_c_bits_legal_T_42 = or(_source_c_bits_legal_T_41, _source_c_bits_legal_T_38)
node _source_c_bits_legal_T_43 = and(_source_c_bits_legal_T_13, _source_c_bits_legal_T_42)
node _source_c_bits_legal_T_44 = or(UInt<1>(0h0), UInt<1>(0h0))
node _source_c_bits_legal_T_45 = xor(cam_a[0].bits.address, UInt<17>(0h10000))
node _source_c_bits_legal_T_46 = cvt(_source_c_bits_legal_T_45)
node _source_c_bits_legal_T_47 = and(_source_c_bits_legal_T_46, asSInt(UInt<33>(0h8a110000)))
node _source_c_bits_legal_T_48 = asSInt(_source_c_bits_legal_T_47)
node _source_c_bits_legal_T_49 = eq(_source_c_bits_legal_T_48, asSInt(UInt<1>(0h0)))
node _source_c_bits_legal_T_50 = and(_source_c_bits_legal_T_44, _source_c_bits_legal_T_49)
node _source_c_bits_legal_T_51 = or(UInt<1>(0h0), _source_c_bits_legal_T_9)
node _source_c_bits_legal_T_52 = or(_source_c_bits_legal_T_51, _source_c_bits_legal_T_43)
node source_c_bits_legal = or(_source_c_bits_legal_T_52, _source_c_bits_legal_T_50)
wire source_c_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect source_c_bits_a.opcode, UInt<1>(0h0)
connect source_c_bits_a.param, UInt<1>(0h0)
connect source_c_bits_a.size, cam_a[0].bits.size
connect source_c_bits_a.source, cam_a[0].bits.source
connect source_c_bits_a.address, cam_a[0].bits.address
node _source_c_bits_a_mask_sizeOH_T = or(cam_a[0].bits.size, UInt<3>(0h0))
node source_c_bits_a_mask_sizeOH_shiftAmount = bits(_source_c_bits_a_mask_sizeOH_T, 1, 0)
node _source_c_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), source_c_bits_a_mask_sizeOH_shiftAmount)
node _source_c_bits_a_mask_sizeOH_T_2 = bits(_source_c_bits_a_mask_sizeOH_T_1, 2, 0)
node source_c_bits_a_mask_sizeOH = or(_source_c_bits_a_mask_sizeOH_T_2, UInt<1>(0h1))
node source_c_bits_a_mask_sub_sub_sub_0_1 = geq(cam_a[0].bits.size, UInt<2>(0h3))
node source_c_bits_a_mask_sub_sub_size = bits(source_c_bits_a_mask_sizeOH, 2, 2)
node source_c_bits_a_mask_sub_sub_bit = bits(cam_a[0].bits.address, 2, 2)
node source_c_bits_a_mask_sub_sub_nbit = eq(source_c_bits_a_mask_sub_sub_bit, UInt<1>(0h0))
node source_c_bits_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), source_c_bits_a_mask_sub_sub_nbit)
node _source_c_bits_a_mask_sub_sub_acc_T = and(source_c_bits_a_mask_sub_sub_size, source_c_bits_a_mask_sub_sub_0_2)
node source_c_bits_a_mask_sub_sub_0_1 = or(source_c_bits_a_mask_sub_sub_sub_0_1, _source_c_bits_a_mask_sub_sub_acc_T)
node source_c_bits_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), source_c_bits_a_mask_sub_sub_bit)
node _source_c_bits_a_mask_sub_sub_acc_T_1 = and(source_c_bits_a_mask_sub_sub_size, source_c_bits_a_mask_sub_sub_1_2)
node source_c_bits_a_mask_sub_sub_1_1 = or(source_c_bits_a_mask_sub_sub_sub_0_1, _source_c_bits_a_mask_sub_sub_acc_T_1)
node source_c_bits_a_mask_sub_size = bits(source_c_bits_a_mask_sizeOH, 1, 1)
node source_c_bits_a_mask_sub_bit = bits(cam_a[0].bits.address, 1, 1)
node source_c_bits_a_mask_sub_nbit = eq(source_c_bits_a_mask_sub_bit, UInt<1>(0h0))
node source_c_bits_a_mask_sub_0_2 = and(source_c_bits_a_mask_sub_sub_0_2, source_c_bits_a_mask_sub_nbit)
node _source_c_bits_a_mask_sub_acc_T = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_0_2)
node source_c_bits_a_mask_sub_0_1 = or(source_c_bits_a_mask_sub_sub_0_1, _source_c_bits_a_mask_sub_acc_T)
node source_c_bits_a_mask_sub_1_2 = and(source_c_bits_a_mask_sub_sub_0_2, source_c_bits_a_mask_sub_bit)
node _source_c_bits_a_mask_sub_acc_T_1 = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_1_2)
node source_c_bits_a_mask_sub_1_1 = or(source_c_bits_a_mask_sub_sub_0_1, _source_c_bits_a_mask_sub_acc_T_1)
node source_c_bits_a_mask_sub_2_2 = and(source_c_bits_a_mask_sub_sub_1_2, source_c_bits_a_mask_sub_nbit)
node _source_c_bits_a_mask_sub_acc_T_2 = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_2_2)
node source_c_bits_a_mask_sub_2_1 = or(source_c_bits_a_mask_sub_sub_1_1, _source_c_bits_a_mask_sub_acc_T_2)
node source_c_bits_a_mask_sub_3_2 = and(source_c_bits_a_mask_sub_sub_1_2, source_c_bits_a_mask_sub_bit)
node _source_c_bits_a_mask_sub_acc_T_3 = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_3_2)
node source_c_bits_a_mask_sub_3_1 = or(source_c_bits_a_mask_sub_sub_1_1, _source_c_bits_a_mask_sub_acc_T_3)
node source_c_bits_a_mask_size = bits(source_c_bits_a_mask_sizeOH, 0, 0)
node source_c_bits_a_mask_bit = bits(cam_a[0].bits.address, 0, 0)
node source_c_bits_a_mask_nbit = eq(source_c_bits_a_mask_bit, UInt<1>(0h0))
node source_c_bits_a_mask_eq = and(source_c_bits_a_mask_sub_0_2, source_c_bits_a_mask_nbit)
node _source_c_bits_a_mask_acc_T = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq)
node source_c_bits_a_mask_acc = or(source_c_bits_a_mask_sub_0_1, _source_c_bits_a_mask_acc_T)
node source_c_bits_a_mask_eq_1 = and(source_c_bits_a_mask_sub_0_2, source_c_bits_a_mask_bit)
node _source_c_bits_a_mask_acc_T_1 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_1)
node source_c_bits_a_mask_acc_1 = or(source_c_bits_a_mask_sub_0_1, _source_c_bits_a_mask_acc_T_1)
node source_c_bits_a_mask_eq_2 = and(source_c_bits_a_mask_sub_1_2, source_c_bits_a_mask_nbit)
node _source_c_bits_a_mask_acc_T_2 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_2)
node source_c_bits_a_mask_acc_2 = or(source_c_bits_a_mask_sub_1_1, _source_c_bits_a_mask_acc_T_2)
node source_c_bits_a_mask_eq_3 = and(source_c_bits_a_mask_sub_1_2, source_c_bits_a_mask_bit)
node _source_c_bits_a_mask_acc_T_3 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_3)
node source_c_bits_a_mask_acc_3 = or(source_c_bits_a_mask_sub_1_1, _source_c_bits_a_mask_acc_T_3)
node source_c_bits_a_mask_eq_4 = and(source_c_bits_a_mask_sub_2_2, source_c_bits_a_mask_nbit)
node _source_c_bits_a_mask_acc_T_4 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_4)
node source_c_bits_a_mask_acc_4 = or(source_c_bits_a_mask_sub_2_1, _source_c_bits_a_mask_acc_T_4)
node source_c_bits_a_mask_eq_5 = and(source_c_bits_a_mask_sub_2_2, source_c_bits_a_mask_bit)
node _source_c_bits_a_mask_acc_T_5 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_5)
node source_c_bits_a_mask_acc_5 = or(source_c_bits_a_mask_sub_2_1, _source_c_bits_a_mask_acc_T_5)
node source_c_bits_a_mask_eq_6 = and(source_c_bits_a_mask_sub_3_2, source_c_bits_a_mask_nbit)
node _source_c_bits_a_mask_acc_T_6 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_6)
node source_c_bits_a_mask_acc_6 = or(source_c_bits_a_mask_sub_3_1, _source_c_bits_a_mask_acc_T_6)
node source_c_bits_a_mask_eq_7 = and(source_c_bits_a_mask_sub_3_2, source_c_bits_a_mask_bit)
node _source_c_bits_a_mask_acc_T_7 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_7)
node source_c_bits_a_mask_acc_7 = or(source_c_bits_a_mask_sub_3_1, _source_c_bits_a_mask_acc_T_7)
node source_c_bits_a_mask_lo_lo = cat(source_c_bits_a_mask_acc_1, source_c_bits_a_mask_acc)
node source_c_bits_a_mask_lo_hi = cat(source_c_bits_a_mask_acc_3, source_c_bits_a_mask_acc_2)
node source_c_bits_a_mask_lo = cat(source_c_bits_a_mask_lo_hi, source_c_bits_a_mask_lo_lo)
node source_c_bits_a_mask_hi_lo = cat(source_c_bits_a_mask_acc_5, source_c_bits_a_mask_acc_4)
node source_c_bits_a_mask_hi_hi = cat(source_c_bits_a_mask_acc_7, source_c_bits_a_mask_acc_6)
node source_c_bits_a_mask_hi = cat(source_c_bits_a_mask_hi_hi, source_c_bits_a_mask_hi_lo)
node _source_c_bits_a_mask_T = cat(source_c_bits_a_mask_hi, source_c_bits_a_mask_lo)
connect source_c_bits_a.mask, _source_c_bits_a_mask_T
connect source_c_bits_a.data, amo_data
connect source_c_bits_a.corrupt, _source_c_bits_T
connect source_c.bits, source_c_bits_a
node _decode_T = dshl(UInt<12>(0hfff), nodeIn.a.bits.size)
node _decode_T_1 = bits(_decode_T, 11, 0)
node _decode_T_2 = not(_decode_T_1)
node decode = shr(_decode_T_2, 3)
node _opdata_T = bits(nodeIn.a.bits.opcode, 2, 2)
node opdata = eq(_opdata_T, UInt<1>(0h0))
node _T_1 = mux(opdata, decode, UInt<1>(0h0))
regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0)
node idle = eq(beatsLeft, UInt<1>(0h0))
node latch = and(idle, nodeOut.a.ready)
node _readys_T = cat(source_i.valid, source_c.valid)
node _readys_T_1 = shl(_readys_T, 1)
node _readys_T_2 = bits(_readys_T_1, 1, 0)
node _readys_T_3 = or(_readys_T, _readys_T_2)
node _readys_T_4 = bits(_readys_T_3, 1, 0)
node _readys_T_5 = shl(_readys_T_4, 1)
node _readys_T_6 = bits(_readys_T_5, 1, 0)
node _readys_T_7 = not(_readys_T_6)
node _readys_T_8 = bits(_readys_T_7, 0, 0)
node _readys_T_9 = bits(_readys_T_7, 1, 1)
wire readys : UInt<1>[2]
connect readys[0], _readys_T_8
connect readys[1], _readys_T_9
node _winner_T = and(readys[0], source_c.valid)
node _winner_T_1 = and(readys[1], source_i.valid)
wire winner : UInt<1>[2]
connect winner[0], _winner_T
connect winner[1], _winner_T_1
node prefixOR_1 = or(UInt<1>(0h0), winner[0])
node _prefixOR_T = or(prefixOR_1, winner[1])
node _T_2 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_3 = eq(winner[0], UInt<1>(0h0))
node _T_4 = or(_T_2, _T_3)
node _T_5 = eq(prefixOR_1, UInt<1>(0h0))
node _T_6 = eq(winner[1], UInt<1>(0h0))
node _T_7 = or(_T_5, _T_6)
node _T_8 = and(_T_4, _T_7)
node _T_9 = asUInt(reset)
node _T_10 = eq(_T_9, UInt<1>(0h0))
when _T_10 :
node _T_11 = eq(_T_8, UInt<1>(0h0))
when _T_11 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf
assert(clock, _T_8, UInt<1>(0h1), "") : assert
node _T_12 = or(source_c.valid, source_i.valid)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = or(winner[0], winner[1])
node _T_15 = or(_T_13, _T_14)
node _T_16 = asUInt(reset)
node _T_17 = eq(_T_16, UInt<1>(0h0))
when _T_17 :
node _T_18 = eq(_T_15, UInt<1>(0h0))
when _T_18 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1
assert(clock, _T_15, UInt<1>(0h1), "") : assert_1
node maskedBeats_0 = mux(winner[0], UInt<1>(0h0), UInt<1>(0h0))
node maskedBeats_1 = mux(winner[1], _T_1, UInt<1>(0h0))
node initBeats = or(maskedBeats_0, maskedBeats_1)
node _beatsLeft_T = and(nodeOut.a.ready, nodeOut.a.valid)
node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T)
node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1)
node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2)
connect beatsLeft, _beatsLeft_T_3
wire _state_WIRE : UInt<1>[2]
connect _state_WIRE[0], UInt<1>(0h0)
connect _state_WIRE[1], UInt<1>(0h0)
regreset state : UInt<1>[2], clock, reset, _state_WIRE
node muxState = mux(idle, winner, state)
connect state, muxState
node allowed = mux(idle, readys, state)
node _source_c_ready_T = and(nodeOut.a.ready, allowed[0])
connect source_c.ready, _source_c_ready_T
node _source_i_ready_T = and(nodeOut.a.ready, allowed[1])
connect source_i.ready, _source_i_ready_T
node _nodeOut_a_valid_T = or(source_c.valid, source_i.valid)
node _nodeOut_a_valid_T_1 = mux(state[0], source_c.valid, UInt<1>(0h0))
node _nodeOut_a_valid_T_2 = mux(state[1], source_i.valid, UInt<1>(0h0))
node _nodeOut_a_valid_T_3 = or(_nodeOut_a_valid_T_1, _nodeOut_a_valid_T_2)
wire _nodeOut_a_valid_WIRE : UInt<1>
connect _nodeOut_a_valid_WIRE, _nodeOut_a_valid_T_3
node _nodeOut_a_valid_T_4 = mux(idle, _nodeOut_a_valid_T, _nodeOut_a_valid_WIRE)
connect nodeOut.a.valid, _nodeOut_a_valid_T_4
wire _nodeOut_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
node _nodeOut_a_bits_T = mux(muxState[0], source_c.bits.corrupt, UInt<1>(0h0))
node _nodeOut_a_bits_T_1 = mux(muxState[1], source_i.bits.corrupt, UInt<1>(0h0))
node _nodeOut_a_bits_T_2 = or(_nodeOut_a_bits_T, _nodeOut_a_bits_T_1)
wire _nodeOut_a_bits_WIRE_1 : UInt<1>
connect _nodeOut_a_bits_WIRE_1, _nodeOut_a_bits_T_2
connect _nodeOut_a_bits_WIRE.corrupt, _nodeOut_a_bits_WIRE_1
node _nodeOut_a_bits_T_3 = mux(muxState[0], source_c.bits.data, UInt<1>(0h0))
node _nodeOut_a_bits_T_4 = mux(muxState[1], source_i.bits.data, UInt<1>(0h0))
node _nodeOut_a_bits_T_5 = or(_nodeOut_a_bits_T_3, _nodeOut_a_bits_T_4)
wire _nodeOut_a_bits_WIRE_2 : UInt<64>
connect _nodeOut_a_bits_WIRE_2, _nodeOut_a_bits_T_5
connect _nodeOut_a_bits_WIRE.data, _nodeOut_a_bits_WIRE_2
node _nodeOut_a_bits_T_6 = mux(muxState[0], source_c.bits.mask, UInt<1>(0h0))
node _nodeOut_a_bits_T_7 = mux(muxState[1], source_i.bits.mask, UInt<1>(0h0))
node _nodeOut_a_bits_T_8 = or(_nodeOut_a_bits_T_6, _nodeOut_a_bits_T_7)
wire _nodeOut_a_bits_WIRE_3 : UInt<8>
connect _nodeOut_a_bits_WIRE_3, _nodeOut_a_bits_T_8
connect _nodeOut_a_bits_WIRE.mask, _nodeOut_a_bits_WIRE_3
wire _nodeOut_a_bits_WIRE_4 : { }
connect _nodeOut_a_bits_WIRE.echo, _nodeOut_a_bits_WIRE_4
wire _nodeOut_a_bits_WIRE_5 : { }
connect _nodeOut_a_bits_WIRE.user, _nodeOut_a_bits_WIRE_5
node _nodeOut_a_bits_T_9 = mux(muxState[0], source_c.bits.address, UInt<1>(0h0))
node _nodeOut_a_bits_T_10 = mux(muxState[1], source_i.bits.address, UInt<1>(0h0))
node _nodeOut_a_bits_T_11 = or(_nodeOut_a_bits_T_9, _nodeOut_a_bits_T_10)
wire _nodeOut_a_bits_WIRE_6 : UInt<32>
connect _nodeOut_a_bits_WIRE_6, _nodeOut_a_bits_T_11
connect _nodeOut_a_bits_WIRE.address, _nodeOut_a_bits_WIRE_6
node _nodeOut_a_bits_T_12 = mux(muxState[0], source_c.bits.source, UInt<1>(0h0))
node _nodeOut_a_bits_T_13 = mux(muxState[1], source_i.bits.source, UInt<1>(0h0))
node _nodeOut_a_bits_T_14 = or(_nodeOut_a_bits_T_12, _nodeOut_a_bits_T_13)
wire _nodeOut_a_bits_WIRE_7 : UInt<7>
connect _nodeOut_a_bits_WIRE_7, _nodeOut_a_bits_T_14
connect _nodeOut_a_bits_WIRE.source, _nodeOut_a_bits_WIRE_7
node _nodeOut_a_bits_T_15 = mux(muxState[0], source_c.bits.size, UInt<1>(0h0))
node _nodeOut_a_bits_T_16 = mux(muxState[1], source_i.bits.size, UInt<1>(0h0))
node _nodeOut_a_bits_T_17 = or(_nodeOut_a_bits_T_15, _nodeOut_a_bits_T_16)
wire _nodeOut_a_bits_WIRE_8 : UInt<4>
connect _nodeOut_a_bits_WIRE_8, _nodeOut_a_bits_T_17
connect _nodeOut_a_bits_WIRE.size, _nodeOut_a_bits_WIRE_8
node _nodeOut_a_bits_T_18 = mux(muxState[0], source_c.bits.param, UInt<1>(0h0))
node _nodeOut_a_bits_T_19 = mux(muxState[1], source_i.bits.param, UInt<1>(0h0))
node _nodeOut_a_bits_T_20 = or(_nodeOut_a_bits_T_18, _nodeOut_a_bits_T_19)
wire _nodeOut_a_bits_WIRE_9 : UInt<3>
connect _nodeOut_a_bits_WIRE_9, _nodeOut_a_bits_T_20
connect _nodeOut_a_bits_WIRE.param, _nodeOut_a_bits_WIRE_9
node _nodeOut_a_bits_T_21 = mux(muxState[0], source_c.bits.opcode, UInt<1>(0h0))
node _nodeOut_a_bits_T_22 = mux(muxState[1], source_i.bits.opcode, UInt<1>(0h0))
node _nodeOut_a_bits_T_23 = or(_nodeOut_a_bits_T_21, _nodeOut_a_bits_T_22)
wire _nodeOut_a_bits_WIRE_10 : UInt<3>
connect _nodeOut_a_bits_WIRE_10, _nodeOut_a_bits_T_23
connect _nodeOut_a_bits_WIRE.opcode, _nodeOut_a_bits_WIRE_10
connect nodeOut.a.bits.corrupt, _nodeOut_a_bits_WIRE.corrupt
connect nodeOut.a.bits.data, _nodeOut_a_bits_WIRE.data
connect nodeOut.a.bits.mask, _nodeOut_a_bits_WIRE.mask
connect nodeOut.a.bits.address, _nodeOut_a_bits_WIRE.address
connect nodeOut.a.bits.source, _nodeOut_a_bits_WIRE.source
connect nodeOut.a.bits.size, _nodeOut_a_bits_WIRE.size
connect nodeOut.a.bits.param, _nodeOut_a_bits_WIRE.param
connect nodeOut.a.bits.opcode, _nodeOut_a_bits_WIRE.opcode
node _T_19 = and(source_i.ready, source_i.valid)
node _T_20 = eq(a_isSupported, UInt<1>(0h0))
node _T_21 = and(_T_19, _T_20)
when _T_21 :
when a_cam_sel_free_0 :
connect cam_a[0].fifoId, UInt<1>(0h0)
connect cam_a[0].bits, nodeIn.a.bits
node _cam_a_0_lut_T = bits(nodeIn.a.bits.param, 1, 0)
node _cam_a_0_lut_T_1 = eq(UInt<3>(0h1), _cam_a_0_lut_T)
node _cam_a_0_lut_T_2 = mux(_cam_a_0_lut_T_1, UInt<4>(0he), UInt<4>(0h8))
node _cam_a_0_lut_T_3 = eq(UInt<3>(0h0), _cam_a_0_lut_T)
node _cam_a_0_lut_T_4 = mux(_cam_a_0_lut_T_3, UInt<3>(0h6), _cam_a_0_lut_T_2)
node _cam_a_0_lut_T_5 = eq(UInt<3>(0h3), _cam_a_0_lut_T)
node _cam_a_0_lut_T_6 = mux(_cam_a_0_lut_T_5, UInt<4>(0hc), _cam_a_0_lut_T_4)
connect cam_a[0].lut, _cam_a_0_lut_T_6
when a_cam_sel_free_0 :
connect cam_s[0].state, UInt<2>(0h3)
node _T_22 = and(source_c.ready, source_c.valid)
when _T_22 :
when a_cam_sel_put_0 :
connect cam_s[0].state, UInt<1>(0h1)
node _d_first_T = and(nodeOut.d.ready, nodeOut.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), nodeOut.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(nodeOut.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
node d_cam_sel_raw_0 = eq(cam_a[0].bits.source, nodeIn.d.bits.source)
node d_cam_sel_match_0 = and(d_cam_sel_raw_0, cam_dmatch_0)
node d_cam_sel_0 = mux(UInt<1>(0h0), a_cam_sel_free_0, d_cam_sel_match_0)
node d_cam_sel_any = or(UInt<1>(0h0), d_cam_sel_match_0)
node d_ackd = eq(nodeOut.d.bits.opcode, UInt<1>(0h1))
node d_ack = eq(nodeOut.d.bits.opcode, UInt<1>(0h0))
node _T_23 = and(nodeOut.d.ready, nodeOut.d.valid)
node _T_24 = and(_T_23, d_first)
when _T_24 :
node _T_25 = and(d_cam_sel_0, d_ackd)
when _T_25 :
connect cam_d[0].data, nodeOut.d.bits.data
connect cam_d[0].denied, nodeOut.d.bits.denied
connect cam_d[0].corrupt, nodeOut.d.bits.corrupt
when d_cam_sel_0 :
node _cam_s_0_state_T = mux(d_ackd, UInt<2>(0h2), UInt<1>(0h0))
connect cam_s[0].state, _cam_s_0_state_T
node _d_drop_T = and(d_first, d_ackd)
node d_drop = and(_d_drop_T, d_cam_sel_any)
node _d_replace_T = and(d_first, d_ack)
node d_replace = and(_d_replace_T, d_cam_sel_match_0)
node _nodeIn_d_valid_T = eq(d_drop, UInt<1>(0h0))
node _nodeIn_d_valid_T_1 = and(nodeOut.d.valid, _nodeIn_d_valid_T)
connect nodeIn.d.valid, _nodeIn_d_valid_T_1
node _nodeOut_d_ready_T = or(nodeIn.d.ready, d_drop)
connect nodeOut.d.ready, _nodeOut_d_ready_T
connect nodeIn.d.bits.corrupt, nodeOut.d.bits.corrupt
connect nodeIn.d.bits.data, nodeOut.d.bits.data
connect nodeIn.d.bits.denied, nodeOut.d.bits.denied
connect nodeIn.d.bits.sink, nodeOut.d.bits.sink
connect nodeIn.d.bits.source, nodeOut.d.bits.source
connect nodeIn.d.bits.size, nodeOut.d.bits.size
connect nodeIn.d.bits.param, nodeOut.d.bits.param
connect nodeIn.d.bits.opcode, nodeOut.d.bits.opcode
when d_replace :
connect nodeIn.d.bits.opcode, UInt<1>(0h1)
connect nodeIn.d.bits.data, cam_d[0].data
node _nodeIn_d_bits_corrupt_T = or(cam_d[0].corrupt, nodeOut.d.bits.denied)
connect nodeIn.d.bits.corrupt, _nodeIn_d_bits_corrupt_T
node _nodeIn_d_bits_denied_T = or(cam_d[0].denied, nodeOut.d.bits.denied)
connect nodeIn.d.bits.denied, _nodeIn_d_bits_denied_T
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<7>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<7>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<7>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
connect _WIRE_9.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_10.bits.sink, UInt<1>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.valid, UInt<1>(0h0)
extmodule plusarg_reader_38 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_39 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLAtomicAutomata_cbus( // @[AtomicAutomata.scala:36:9]
input clock, // @[AtomicAutomata.scala:36:9]
input reset, // @[AtomicAutomata.scala:36:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[AtomicAutomata.scala:36:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[AtomicAutomata.scala:36:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[AtomicAutomata.scala:36:9]
wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[AtomicAutomata.scala:36:9]
wire [6:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[AtomicAutomata.scala:36:9]
wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[AtomicAutomata.scala:36:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[AtomicAutomata.scala:36:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[AtomicAutomata.scala:36:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[AtomicAutomata.scala:36:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[AtomicAutomata.scala:36:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[AtomicAutomata.scala:36:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[AtomicAutomata.scala:36:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[AtomicAutomata.scala:36:9]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[AtomicAutomata.scala:36:9]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[AtomicAutomata.scala:36:9]
wire [6:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[AtomicAutomata.scala:36:9]
wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[AtomicAutomata.scala:36:9]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[AtomicAutomata.scala:36:9]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[AtomicAutomata.scala:36:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[AtomicAutomata.scala:36:9]
wire _a_canLogical_T = 1'h1; // @[Parameters.scala:92:28]
wire _a_canArithmetic_T = 1'h1; // @[Parameters.scala:92:28]
wire _a_cam_sel_put_T = 1'h1; // @[AtomicAutomata.scala:103:83]
wire _a_fifoId_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire _a_cam_busy_T = 1'h1; // @[AtomicAutomata.scala:111:60]
wire _a_cam_sel_free_T = 1'h1; // @[AtomicAutomata.scala:116:85]
wire _source_c_bits_legal_T = 1'h1; // @[Parameters.scala:92:28]
wire _source_c_bits_legal_T_10 = 1'h1; // @[Parameters.scala:92:28]
wire _a_canLogical_T_16 = 1'h0; // @[Parameters.scala:684:29]
wire _a_canLogical_T_46 = 1'h0; // @[Parameters.scala:684:54]
wire _a_canArithmetic_T_16 = 1'h0; // @[Parameters.scala:684:29]
wire _a_canArithmetic_T_46 = 1'h0; // @[Parameters.scala:684:54]
wire _source_c_bits_legal_T_44 = 1'h0; // @[Parameters.scala:684:29]
wire _source_c_bits_legal_T_50 = 1'h0; // @[Parameters.scala:684:54]
wire maskedBeats_0 = 1'h0; // @[Arbiter.scala:82:69]
wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34]
wire [2:0] source_c_bits_opcode = 3'h0; // @[AtomicAutomata.scala:165:28]
wire [2:0] source_c_bits_param = 3'h0; // @[AtomicAutomata.scala:165:28]
wire [2:0] source_c_bits_a_opcode = 3'h0; // @[Edges.scala:480:17]
wire [2:0] source_c_bits_a_param = 3'h0; // @[Edges.scala:480:17]
wire [2:0] _nodeOut_a_bits_T_18 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_21 = 3'h0; // @[Mux.scala:30:73]
wire [32:0] _a_fifoId_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _a_fifoId_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [1:0] initval_state = 2'h0; // @[AtomicAutomata.scala:80:27]
wire [1:0] _cam_s_WIRE_0_state = 2'h0; // @[AtomicAutomata.scala:82:50]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[AtomicAutomata.scala:36:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[AtomicAutomata.scala:36:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[AtomicAutomata.scala:36:9]
wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[AtomicAutomata.scala:36:9]
wire [6:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[AtomicAutomata.scala:36:9]
wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[AtomicAutomata.scala:36:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[AtomicAutomata.scala:36:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[AtomicAutomata.scala:36:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[AtomicAutomata.scala:36:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[AtomicAutomata.scala:36:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [6:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[AtomicAutomata.scala:36:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [6:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[AtomicAutomata.scala:36:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[AtomicAutomata.scala:36:9]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[AtomicAutomata.scala:36:9]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[AtomicAutomata.scala:36:9]
wire [6:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[AtomicAutomata.scala:36:9]
wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[AtomicAutomata.scala:36:9]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[AtomicAutomata.scala:36:9]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[AtomicAutomata.scala:36:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[AtomicAutomata.scala:36:9]
wire auto_in_a_ready_0; // @[AtomicAutomata.scala:36:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[AtomicAutomata.scala:36:9]
wire [1:0] auto_in_d_bits_param_0; // @[AtomicAutomata.scala:36:9]
wire [3:0] auto_in_d_bits_size_0; // @[AtomicAutomata.scala:36:9]
wire [6:0] auto_in_d_bits_source_0; // @[AtomicAutomata.scala:36:9]
wire auto_in_d_bits_sink_0; // @[AtomicAutomata.scala:36:9]
wire auto_in_d_bits_denied_0; // @[AtomicAutomata.scala:36:9]
wire [63:0] auto_in_d_bits_data_0; // @[AtomicAutomata.scala:36:9]
wire auto_in_d_bits_corrupt_0; // @[AtomicAutomata.scala:36:9]
wire auto_in_d_valid_0; // @[AtomicAutomata.scala:36:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[AtomicAutomata.scala:36:9]
wire [2:0] auto_out_a_bits_param_0; // @[AtomicAutomata.scala:36:9]
wire [3:0] auto_out_a_bits_size_0; // @[AtomicAutomata.scala:36:9]
wire [6:0] auto_out_a_bits_source_0; // @[AtomicAutomata.scala:36:9]
wire [31:0] auto_out_a_bits_address_0; // @[AtomicAutomata.scala:36:9]
wire [7:0] auto_out_a_bits_mask_0; // @[AtomicAutomata.scala:36:9]
wire [63:0] auto_out_a_bits_data_0; // @[AtomicAutomata.scala:36:9]
wire auto_out_a_bits_corrupt_0; // @[AtomicAutomata.scala:36:9]
wire auto_out_a_valid_0; // @[AtomicAutomata.scala:36:9]
wire auto_out_d_ready_0; // @[AtomicAutomata.scala:36:9]
wire _nodeIn_a_ready_T; // @[AtomicAutomata.scala:156:38]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[AtomicAutomata.scala:36:9]
wire [3:0] source_i_bits_size = nodeIn_a_bits_size; // @[AtomicAutomata.scala:154:28]
wire [6:0] source_i_bits_source = nodeIn_a_bits_source; // @[AtomicAutomata.scala:154:28]
wire [31:0] _a_canLogical_T_17 = nodeIn_a_bits_address; // @[Parameters.scala:137:31]
wire [31:0] _a_canArithmetic_T_17 = nodeIn_a_bits_address; // @[Parameters.scala:137:31]
wire [31:0] _a_fifoId_T = nodeIn_a_bits_address; // @[Parameters.scala:137:31]
wire [31:0] source_i_bits_address = nodeIn_a_bits_address; // @[AtomicAutomata.scala:154:28]
wire [7:0] source_i_bits_mask = nodeIn_a_bits_mask; // @[AtomicAutomata.scala:154:28]
wire [63:0] source_i_bits_data = nodeIn_a_bits_data; // @[AtomicAutomata.scala:154:28]
wire source_i_bits_corrupt = nodeIn_a_bits_corrupt; // @[AtomicAutomata.scala:154:28]
wire _nodeIn_d_valid_T_1; // @[AtomicAutomata.scala:241:35]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[AtomicAutomata.scala:36:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[AtomicAutomata.scala:36:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[AtomicAutomata.scala:36:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[AtomicAutomata.scala:36:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[AtomicAutomata.scala:36:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[AtomicAutomata.scala:36:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[AtomicAutomata.scala:36:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[AtomicAutomata.scala:36:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[AtomicAutomata.scala:36:9]
wire _nodeOut_a_valid_T_4; // @[Arbiter.scala:96:24]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[AtomicAutomata.scala:36:9]
wire [2:0] _nodeOut_a_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[AtomicAutomata.scala:36:9]
wire [2:0] _nodeOut_a_bits_WIRE_param; // @[Mux.scala:30:73]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[AtomicAutomata.scala:36:9]
wire [3:0] _nodeOut_a_bits_WIRE_size; // @[Mux.scala:30:73]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[AtomicAutomata.scala:36:9]
wire [6:0] _nodeOut_a_bits_WIRE_source; // @[Mux.scala:30:73]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[AtomicAutomata.scala:36:9]
wire [31:0] _nodeOut_a_bits_WIRE_address; // @[Mux.scala:30:73]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[AtomicAutomata.scala:36:9]
wire [7:0] _nodeOut_a_bits_WIRE_mask; // @[Mux.scala:30:73]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[AtomicAutomata.scala:36:9]
wire [63:0] _nodeOut_a_bits_WIRE_data; // @[Mux.scala:30:73]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[AtomicAutomata.scala:36:9]
wire _nodeOut_a_bits_WIRE_corrupt; // @[Mux.scala:30:73]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[AtomicAutomata.scala:36:9]
wire _nodeOut_d_ready_T; // @[AtomicAutomata.scala:242:35]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[AtomicAutomata.scala:36:9]
assign nodeIn_d_bits_param = nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_size = nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_source = nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_sink = nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
reg [1:0] cam_s_0_state; // @[AtomicAutomata.scala:82:28]
reg [2:0] cam_a_0_bits_opcode; // @[AtomicAutomata.scala:83:24]
reg [2:0] cam_a_0_bits_param; // @[AtomicAutomata.scala:83:24]
reg [3:0] cam_a_0_bits_size; // @[AtomicAutomata.scala:83:24]
wire [3:0] source_c_bits_a_size = cam_a_0_bits_size; // @[Edges.scala:480:17]
wire [3:0] _source_c_bits_a_mask_sizeOH_T = cam_a_0_bits_size; // @[Misc.scala:202:34]
reg [6:0] cam_a_0_bits_source; // @[AtomicAutomata.scala:83:24]
wire [6:0] source_c_bits_a_source = cam_a_0_bits_source; // @[Edges.scala:480:17]
reg [31:0] cam_a_0_bits_address; // @[AtomicAutomata.scala:83:24]
wire [31:0] _source_c_bits_legal_T_14 = cam_a_0_bits_address; // @[AtomicAutomata.scala:83:24]
wire [31:0] source_c_bits_a_address = cam_a_0_bits_address; // @[Edges.scala:480:17]
reg [7:0] cam_a_0_bits_mask; // @[AtomicAutomata.scala:83:24]
reg [63:0] cam_a_0_bits_data; // @[AtomicAutomata.scala:83:24]
reg cam_a_0_bits_corrupt; // @[AtomicAutomata.scala:83:24]
reg [3:0] cam_a_0_lut; // @[AtomicAutomata.scala:83:24]
reg [63:0] cam_d_0_data; // @[AtomicAutomata.scala:84:24]
reg cam_d_0_denied; // @[AtomicAutomata.scala:84:24]
reg cam_d_0_corrupt; // @[AtomicAutomata.scala:84:24]
wire cam_free_0 = ~(|cam_s_0_state); // @[AtomicAutomata.scala:82:28, :86:44]
wire _a_cam_por_free_T = cam_free_0; // @[AtomicAutomata.scala:86:44, :115:58]
wire a_cam_sel_free_0 = cam_free_0; // @[AtomicAutomata.scala:86:44, :116:82]
wire _GEN = cam_s_0_state == 2'h2; // @[AtomicAutomata.scala:82:28, :87:44]
wire cam_amo_0; // @[AtomicAutomata.scala:87:44]
assign cam_amo_0 = _GEN; // @[AtomicAutomata.scala:87:44]
wire _cam_abusy_T_1; // @[AtomicAutomata.scala:88:68]
assign _cam_abusy_T_1 = _GEN; // @[AtomicAutomata.scala:87:44, :88:68]
wire _a_cam_por_put_T = cam_amo_0; // @[AtomicAutomata.scala:87:44, :102:56]
wire a_cam_sel_put_0 = cam_amo_0; // @[AtomicAutomata.scala:87:44, :103:80]
wire source_c_valid = cam_amo_0; // @[AtomicAutomata.scala:87:44, :165:28]
wire _cam_abusy_T = &cam_s_0_state; // @[AtomicAutomata.scala:82:28, :88:49]
wire cam_abusy_0 = _cam_abusy_T | _cam_abusy_T_1; // @[AtomicAutomata.scala:88:{49,57,68}]
wire a_cam_busy = cam_abusy_0; // @[AtomicAutomata.scala:88:57, :111:96]
wire cam_dmatch_0 = |cam_s_0_state; // @[AtomicAutomata.scala:82:28, :86:44, :89:49]
wire _GEN_0 = nodeIn_a_bits_size < 4'h4; // @[Parameters.scala:92:38]
wire _a_canLogical_T_1; // @[Parameters.scala:92:38]
assign _a_canLogical_T_1 = _GEN_0; // @[Parameters.scala:92:38]
wire _a_canArithmetic_T_1; // @[Parameters.scala:92:38]
assign _a_canArithmetic_T_1 = _GEN_0; // @[Parameters.scala:92:38]
wire _a_canLogical_T_2 = _a_canLogical_T_1; // @[Parameters.scala:92:{33,38}]
wire _a_canLogical_T_3 = _a_canLogical_T_2; // @[Parameters.scala:684:29]
wire [31:0] _GEN_1 = {nodeIn_a_bits_address[31:13], nodeIn_a_bits_address[12:0] ^ 13'h1000}; // @[Parameters.scala:137:31]
wire [31:0] _a_canLogical_T_4; // @[Parameters.scala:137:31]
assign _a_canLogical_T_4 = _GEN_1; // @[Parameters.scala:137:31]
wire [31:0] _a_canArithmetic_T_4; // @[Parameters.scala:137:31]
assign _a_canArithmetic_T_4 = _GEN_1; // @[Parameters.scala:137:31]
wire [32:0] _a_canLogical_T_5 = {1'h0, _a_canLogical_T_4}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_canLogical_T_6 = _a_canLogical_T_5 & 33'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_canLogical_T_7 = _a_canLogical_T_6; // @[Parameters.scala:137:46]
wire _a_canLogical_T_8 = _a_canLogical_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _GEN_2 = {nodeIn_a_bits_address[31:29], nodeIn_a_bits_address[28:0] ^ 29'h10000000}; // @[Parameters.scala:137:31]
wire [31:0] _a_canLogical_T_9; // @[Parameters.scala:137:31]
assign _a_canLogical_T_9 = _GEN_2; // @[Parameters.scala:137:31]
wire [31:0] _a_canArithmetic_T_9; // @[Parameters.scala:137:31]
assign _a_canArithmetic_T_9 = _GEN_2; // @[Parameters.scala:137:31]
wire [32:0] _a_canLogical_T_10 = {1'h0, _a_canLogical_T_9}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_canLogical_T_11 = _a_canLogical_T_10 & 33'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_canLogical_T_12 = _a_canLogical_T_11; // @[Parameters.scala:137:46]
wire _a_canLogical_T_13 = _a_canLogical_T_12 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _a_canLogical_T_14 = _a_canLogical_T_8 | _a_canLogical_T_13; // @[Parameters.scala:685:42]
wire _a_canLogical_T_15 = _a_canLogical_T_3 & _a_canLogical_T_14; // @[Parameters.scala:684:{29,54}, :685:42]
wire _a_canLogical_T_55 = _a_canLogical_T_15; // @[Parameters.scala:684:54, :686:26]
wire [32:0] _a_canLogical_T_18 = {1'h0, _a_canLogical_T_17}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_canLogical_T_19 = _a_canLogical_T_18 & 33'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_canLogical_T_20 = _a_canLogical_T_19; // @[Parameters.scala:137:46]
wire _a_canLogical_T_21 = _a_canLogical_T_20 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _GEN_3 = {nodeIn_a_bits_address[31:17], nodeIn_a_bits_address[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31]
wire [31:0] _a_canLogical_T_22; // @[Parameters.scala:137:31]
assign _a_canLogical_T_22 = _GEN_3; // @[Parameters.scala:137:31]
wire [31:0] _a_canArithmetic_T_22; // @[Parameters.scala:137:31]
assign _a_canArithmetic_T_22 = _GEN_3; // @[Parameters.scala:137:31]
wire [32:0] _a_canLogical_T_23 = {1'h0, _a_canLogical_T_22}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_canLogical_T_24 = _a_canLogical_T_23 & 33'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_canLogical_T_25 = _a_canLogical_T_24; // @[Parameters.scala:137:46]
wire _a_canLogical_T_26 = _a_canLogical_T_25 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _GEN_4 = {nodeIn_a_bits_address[31:21], nodeIn_a_bits_address[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31]
wire [31:0] _a_canLogical_T_27; // @[Parameters.scala:137:31]
assign _a_canLogical_T_27 = _GEN_4; // @[Parameters.scala:137:31]
wire [31:0] _a_canArithmetic_T_27; // @[Parameters.scala:137:31]
assign _a_canArithmetic_T_27 = _GEN_4; // @[Parameters.scala:137:31]
wire [32:0] _a_canLogical_T_28 = {1'h0, _a_canLogical_T_27}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_canLogical_T_29 = _a_canLogical_T_28 & 33'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_canLogical_T_30 = _a_canLogical_T_29; // @[Parameters.scala:137:46]
wire _a_canLogical_T_31 = _a_canLogical_T_30 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _GEN_5 = {nodeIn_a_bits_address[31:26], nodeIn_a_bits_address[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31]
wire [31:0] _a_canLogical_T_32; // @[Parameters.scala:137:31]
assign _a_canLogical_T_32 = _GEN_5; // @[Parameters.scala:137:31]
wire [31:0] _a_canArithmetic_T_32; // @[Parameters.scala:137:31]
assign _a_canArithmetic_T_32 = _GEN_5; // @[Parameters.scala:137:31]
wire [32:0] _a_canLogical_T_33 = {1'h0, _a_canLogical_T_32}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_canLogical_T_34 = _a_canLogical_T_33 & 33'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_canLogical_T_35 = _a_canLogical_T_34; // @[Parameters.scala:137:46]
wire _a_canLogical_T_36 = _a_canLogical_T_35 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _GEN_6 = {nodeIn_a_bits_address[31:28], nodeIn_a_bits_address[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31]
wire [31:0] _a_canLogical_T_37; // @[Parameters.scala:137:31]
assign _a_canLogical_T_37 = _GEN_6; // @[Parameters.scala:137:31]
wire [31:0] _a_canArithmetic_T_37; // @[Parameters.scala:137:31]
assign _a_canArithmetic_T_37 = _GEN_6; // @[Parameters.scala:137:31]
wire [32:0] _a_canLogical_T_38 = {1'h0, _a_canLogical_T_37}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_canLogical_T_39 = _a_canLogical_T_38 & 33'h98000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_canLogical_T_40 = _a_canLogical_T_39; // @[Parameters.scala:137:46]
wire _a_canLogical_T_41 = _a_canLogical_T_40 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _a_canLogical_T_42 = _a_canLogical_T_21 | _a_canLogical_T_26; // @[Parameters.scala:685:42]
wire _a_canLogical_T_43 = _a_canLogical_T_42 | _a_canLogical_T_31; // @[Parameters.scala:685:42]
wire _a_canLogical_T_44 = _a_canLogical_T_43 | _a_canLogical_T_36; // @[Parameters.scala:685:42]
wire _a_canLogical_T_45 = _a_canLogical_T_44 | _a_canLogical_T_41; // @[Parameters.scala:685:42]
wire _GEN_7 = nodeIn_a_bits_size == 4'h2; // @[Parameters.scala:91:44]
wire _a_canLogical_T_47; // @[Parameters.scala:91:44]
assign _a_canLogical_T_47 = _GEN_7; // @[Parameters.scala:91:44]
wire _a_canArithmetic_T_47; // @[Parameters.scala:91:44]
assign _a_canArithmetic_T_47 = _GEN_7; // @[Parameters.scala:91:44]
wire _a_canLogical_T_48 = _a_canLogical_T_47; // @[Parameters.scala:684:29]
wire [31:0] _GEN_8 = nodeIn_a_bits_address ^ 32'h80000000; // @[Parameters.scala:137:31]
wire [31:0] _a_canLogical_T_49; // @[Parameters.scala:137:31]
assign _a_canLogical_T_49 = _GEN_8; // @[Parameters.scala:137:31]
wire [31:0] _a_canArithmetic_T_49; // @[Parameters.scala:137:31]
assign _a_canArithmetic_T_49 = _GEN_8; // @[Parameters.scala:137:31]
wire [32:0] _a_canLogical_T_50 = {1'h0, _a_canLogical_T_49}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_canLogical_T_51 = _a_canLogical_T_50 & 33'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_canLogical_T_52 = _a_canLogical_T_51; // @[Parameters.scala:137:46]
wire _a_canLogical_T_53 = _a_canLogical_T_52 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _a_canLogical_T_54 = _a_canLogical_T_48 & _a_canLogical_T_53; // @[Parameters.scala:684:{29,54}]
wire _a_canLogical_T_56 = _a_canLogical_T_55; // @[Parameters.scala:686:26]
wire _a_canLogical_T_57 = _a_canLogical_T_56 | _a_canLogical_T_54; // @[Parameters.scala:684:54, :686:26]
wire a_canLogical = _a_canLogical_T_57; // @[Parameters.scala:686:26]
wire _a_canArithmetic_T_2 = _a_canArithmetic_T_1; // @[Parameters.scala:92:{33,38}]
wire _a_canArithmetic_T_3 = _a_canArithmetic_T_2; // @[Parameters.scala:684:29]
wire [32:0] _a_canArithmetic_T_5 = {1'h0, _a_canArithmetic_T_4}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_canArithmetic_T_6 = _a_canArithmetic_T_5 & 33'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_canArithmetic_T_7 = _a_canArithmetic_T_6; // @[Parameters.scala:137:46]
wire _a_canArithmetic_T_8 = _a_canArithmetic_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [32:0] _a_canArithmetic_T_10 = {1'h0, _a_canArithmetic_T_9}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_canArithmetic_T_11 = _a_canArithmetic_T_10 & 33'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_canArithmetic_T_12 = _a_canArithmetic_T_11; // @[Parameters.scala:137:46]
wire _a_canArithmetic_T_13 = _a_canArithmetic_T_12 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _a_canArithmetic_T_14 = _a_canArithmetic_T_8 | _a_canArithmetic_T_13; // @[Parameters.scala:685:42]
wire _a_canArithmetic_T_15 = _a_canArithmetic_T_3 & _a_canArithmetic_T_14; // @[Parameters.scala:684:{29,54}, :685:42]
wire _a_canArithmetic_T_55 = _a_canArithmetic_T_15; // @[Parameters.scala:684:54, :686:26]
wire [32:0] _a_canArithmetic_T_18 = {1'h0, _a_canArithmetic_T_17}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_canArithmetic_T_19 = _a_canArithmetic_T_18 & 33'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_canArithmetic_T_20 = _a_canArithmetic_T_19; // @[Parameters.scala:137:46]
wire _a_canArithmetic_T_21 = _a_canArithmetic_T_20 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [32:0] _a_canArithmetic_T_23 = {1'h0, _a_canArithmetic_T_22}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_canArithmetic_T_24 = _a_canArithmetic_T_23 & 33'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_canArithmetic_T_25 = _a_canArithmetic_T_24; // @[Parameters.scala:137:46]
wire _a_canArithmetic_T_26 = _a_canArithmetic_T_25 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [32:0] _a_canArithmetic_T_28 = {1'h0, _a_canArithmetic_T_27}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_canArithmetic_T_29 = _a_canArithmetic_T_28 & 33'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_canArithmetic_T_30 = _a_canArithmetic_T_29; // @[Parameters.scala:137:46]
wire _a_canArithmetic_T_31 = _a_canArithmetic_T_30 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [32:0] _a_canArithmetic_T_33 = {1'h0, _a_canArithmetic_T_32}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_canArithmetic_T_34 = _a_canArithmetic_T_33 & 33'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_canArithmetic_T_35 = _a_canArithmetic_T_34; // @[Parameters.scala:137:46]
wire _a_canArithmetic_T_36 = _a_canArithmetic_T_35 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [32:0] _a_canArithmetic_T_38 = {1'h0, _a_canArithmetic_T_37}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_canArithmetic_T_39 = _a_canArithmetic_T_38 & 33'h98000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_canArithmetic_T_40 = _a_canArithmetic_T_39; // @[Parameters.scala:137:46]
wire _a_canArithmetic_T_41 = _a_canArithmetic_T_40 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _a_canArithmetic_T_42 = _a_canArithmetic_T_21 | _a_canArithmetic_T_26; // @[Parameters.scala:685:42]
wire _a_canArithmetic_T_43 = _a_canArithmetic_T_42 | _a_canArithmetic_T_31; // @[Parameters.scala:685:42]
wire _a_canArithmetic_T_44 = _a_canArithmetic_T_43 | _a_canArithmetic_T_36; // @[Parameters.scala:685:42]
wire _a_canArithmetic_T_45 = _a_canArithmetic_T_44 | _a_canArithmetic_T_41; // @[Parameters.scala:685:42]
wire _a_canArithmetic_T_48 = _a_canArithmetic_T_47; // @[Parameters.scala:684:29]
wire [32:0] _a_canArithmetic_T_50 = {1'h0, _a_canArithmetic_T_49}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_canArithmetic_T_51 = _a_canArithmetic_T_50 & 33'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_canArithmetic_T_52 = _a_canArithmetic_T_51; // @[Parameters.scala:137:46]
wire _a_canArithmetic_T_53 = _a_canArithmetic_T_52 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _a_canArithmetic_T_54 = _a_canArithmetic_T_48 & _a_canArithmetic_T_53; // @[Parameters.scala:684:{29,54}]
wire _a_canArithmetic_T_56 = _a_canArithmetic_T_55; // @[Parameters.scala:686:26]
wire _a_canArithmetic_T_57 = _a_canArithmetic_T_56 | _a_canArithmetic_T_54; // @[Parameters.scala:684:54, :686:26]
wire a_canArithmetic = _a_canArithmetic_T_57; // @[Parameters.scala:686:26]
wire a_isLogical = nodeIn_a_bits_opcode == 3'h3; // @[AtomicAutomata.scala:96:47]
wire a_isArithmetic = nodeIn_a_bits_opcode == 3'h2; // @[AtomicAutomata.scala:97:47]
wire _a_isSupported_T = ~a_isArithmetic | a_canArithmetic; // @[AtomicAutomata.scala:95:45, :97:47, :98:63]
wire a_isSupported = a_isLogical ? a_canLogical : _a_isSupported_T; // @[AtomicAutomata.scala:94:45, :96:47, :98:{32,63}]
wire [32:0] _a_fifoId_T_1 = {1'h0, _a_fifoId_T}; // @[Parameters.scala:137:{31,41}]
wire _indexes_T = cam_a_0_bits_data[0]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_1 = cam_d_0_data[0]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_0 = {_indexes_T, _indexes_T_1}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_2 = cam_a_0_bits_data[1]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_3 = cam_d_0_data[1]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_1 = {_indexes_T_2, _indexes_T_3}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_4 = cam_a_0_bits_data[2]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_5 = cam_d_0_data[2]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_2 = {_indexes_T_4, _indexes_T_5}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_6 = cam_a_0_bits_data[3]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_7 = cam_d_0_data[3]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_3 = {_indexes_T_6, _indexes_T_7}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_8 = cam_a_0_bits_data[4]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_9 = cam_d_0_data[4]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_4 = {_indexes_T_8, _indexes_T_9}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_10 = cam_a_0_bits_data[5]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_11 = cam_d_0_data[5]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_5 = {_indexes_T_10, _indexes_T_11}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_12 = cam_a_0_bits_data[6]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_13 = cam_d_0_data[6]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_6 = {_indexes_T_12, _indexes_T_13}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_14 = cam_a_0_bits_data[7]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _signbits_a_T = cam_a_0_bits_data[7]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64]
wire _indexes_T_15 = cam_d_0_data[7]; // @[AtomicAutomata.scala:84:24, :119:73]
wire _signbits_d_T = cam_d_0_data[7]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64]
wire [1:0] indexes_7 = {_indexes_T_14, _indexes_T_15}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_16 = cam_a_0_bits_data[8]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_17 = cam_d_0_data[8]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_8 = {_indexes_T_16, _indexes_T_17}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_18 = cam_a_0_bits_data[9]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_19 = cam_d_0_data[9]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_9 = {_indexes_T_18, _indexes_T_19}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_20 = cam_a_0_bits_data[10]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_21 = cam_d_0_data[10]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_10 = {_indexes_T_20, _indexes_T_21}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_22 = cam_a_0_bits_data[11]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_23 = cam_d_0_data[11]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_11 = {_indexes_T_22, _indexes_T_23}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_24 = cam_a_0_bits_data[12]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_25 = cam_d_0_data[12]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_12 = {_indexes_T_24, _indexes_T_25}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_26 = cam_a_0_bits_data[13]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_27 = cam_d_0_data[13]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_13 = {_indexes_T_26, _indexes_T_27}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_28 = cam_a_0_bits_data[14]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_29 = cam_d_0_data[14]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_14 = {_indexes_T_28, _indexes_T_29}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_30 = cam_a_0_bits_data[15]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _signbits_a_T_1 = cam_a_0_bits_data[15]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64]
wire _indexes_T_31 = cam_d_0_data[15]; // @[AtomicAutomata.scala:84:24, :119:73]
wire _signbits_d_T_1 = cam_d_0_data[15]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64]
wire [1:0] indexes_15 = {_indexes_T_30, _indexes_T_31}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_32 = cam_a_0_bits_data[16]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_33 = cam_d_0_data[16]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_16 = {_indexes_T_32, _indexes_T_33}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_34 = cam_a_0_bits_data[17]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_35 = cam_d_0_data[17]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_17 = {_indexes_T_34, _indexes_T_35}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_36 = cam_a_0_bits_data[18]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_37 = cam_d_0_data[18]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_18 = {_indexes_T_36, _indexes_T_37}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_38 = cam_a_0_bits_data[19]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_39 = cam_d_0_data[19]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_19 = {_indexes_T_38, _indexes_T_39}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_40 = cam_a_0_bits_data[20]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_41 = cam_d_0_data[20]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_20 = {_indexes_T_40, _indexes_T_41}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_42 = cam_a_0_bits_data[21]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_43 = cam_d_0_data[21]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_21 = {_indexes_T_42, _indexes_T_43}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_44 = cam_a_0_bits_data[22]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_45 = cam_d_0_data[22]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_22 = {_indexes_T_44, _indexes_T_45}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_46 = cam_a_0_bits_data[23]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _signbits_a_T_2 = cam_a_0_bits_data[23]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64]
wire _indexes_T_47 = cam_d_0_data[23]; // @[AtomicAutomata.scala:84:24, :119:73]
wire _signbits_d_T_2 = cam_d_0_data[23]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64]
wire [1:0] indexes_23 = {_indexes_T_46, _indexes_T_47}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_48 = cam_a_0_bits_data[24]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_49 = cam_d_0_data[24]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_24 = {_indexes_T_48, _indexes_T_49}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_50 = cam_a_0_bits_data[25]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_51 = cam_d_0_data[25]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_25 = {_indexes_T_50, _indexes_T_51}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_52 = cam_a_0_bits_data[26]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_53 = cam_d_0_data[26]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_26 = {_indexes_T_52, _indexes_T_53}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_54 = cam_a_0_bits_data[27]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_55 = cam_d_0_data[27]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_27 = {_indexes_T_54, _indexes_T_55}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_56 = cam_a_0_bits_data[28]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_57 = cam_d_0_data[28]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_28 = {_indexes_T_56, _indexes_T_57}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_58 = cam_a_0_bits_data[29]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_59 = cam_d_0_data[29]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_29 = {_indexes_T_58, _indexes_T_59}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_60 = cam_a_0_bits_data[30]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_61 = cam_d_0_data[30]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_30 = {_indexes_T_60, _indexes_T_61}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_62 = cam_a_0_bits_data[31]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _signbits_a_T_3 = cam_a_0_bits_data[31]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64]
wire _indexes_T_63 = cam_d_0_data[31]; // @[AtomicAutomata.scala:84:24, :119:73]
wire _signbits_d_T_3 = cam_d_0_data[31]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64]
wire [1:0] indexes_31 = {_indexes_T_62, _indexes_T_63}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_64 = cam_a_0_bits_data[32]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_65 = cam_d_0_data[32]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_32 = {_indexes_T_64, _indexes_T_65}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_66 = cam_a_0_bits_data[33]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_67 = cam_d_0_data[33]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_33 = {_indexes_T_66, _indexes_T_67}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_68 = cam_a_0_bits_data[34]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_69 = cam_d_0_data[34]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_34 = {_indexes_T_68, _indexes_T_69}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_70 = cam_a_0_bits_data[35]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_71 = cam_d_0_data[35]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_35 = {_indexes_T_70, _indexes_T_71}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_72 = cam_a_0_bits_data[36]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_73 = cam_d_0_data[36]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_36 = {_indexes_T_72, _indexes_T_73}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_74 = cam_a_0_bits_data[37]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_75 = cam_d_0_data[37]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_37 = {_indexes_T_74, _indexes_T_75}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_76 = cam_a_0_bits_data[38]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_77 = cam_d_0_data[38]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_38 = {_indexes_T_76, _indexes_T_77}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_78 = cam_a_0_bits_data[39]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _signbits_a_T_4 = cam_a_0_bits_data[39]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64]
wire _indexes_T_79 = cam_d_0_data[39]; // @[AtomicAutomata.scala:84:24, :119:73]
wire _signbits_d_T_4 = cam_d_0_data[39]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64]
wire [1:0] indexes_39 = {_indexes_T_78, _indexes_T_79}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_80 = cam_a_0_bits_data[40]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_81 = cam_d_0_data[40]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_40 = {_indexes_T_80, _indexes_T_81}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_82 = cam_a_0_bits_data[41]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_83 = cam_d_0_data[41]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_41 = {_indexes_T_82, _indexes_T_83}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_84 = cam_a_0_bits_data[42]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_85 = cam_d_0_data[42]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_42 = {_indexes_T_84, _indexes_T_85}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_86 = cam_a_0_bits_data[43]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_87 = cam_d_0_data[43]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_43 = {_indexes_T_86, _indexes_T_87}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_88 = cam_a_0_bits_data[44]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_89 = cam_d_0_data[44]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_44 = {_indexes_T_88, _indexes_T_89}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_90 = cam_a_0_bits_data[45]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_91 = cam_d_0_data[45]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_45 = {_indexes_T_90, _indexes_T_91}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_92 = cam_a_0_bits_data[46]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_93 = cam_d_0_data[46]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_46 = {_indexes_T_92, _indexes_T_93}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_94 = cam_a_0_bits_data[47]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _signbits_a_T_5 = cam_a_0_bits_data[47]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64]
wire _indexes_T_95 = cam_d_0_data[47]; // @[AtomicAutomata.scala:84:24, :119:73]
wire _signbits_d_T_5 = cam_d_0_data[47]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64]
wire [1:0] indexes_47 = {_indexes_T_94, _indexes_T_95}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_96 = cam_a_0_bits_data[48]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_97 = cam_d_0_data[48]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_48 = {_indexes_T_96, _indexes_T_97}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_98 = cam_a_0_bits_data[49]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_99 = cam_d_0_data[49]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_49 = {_indexes_T_98, _indexes_T_99}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_100 = cam_a_0_bits_data[50]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_101 = cam_d_0_data[50]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_50 = {_indexes_T_100, _indexes_T_101}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_102 = cam_a_0_bits_data[51]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_103 = cam_d_0_data[51]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_51 = {_indexes_T_102, _indexes_T_103}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_104 = cam_a_0_bits_data[52]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_105 = cam_d_0_data[52]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_52 = {_indexes_T_104, _indexes_T_105}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_106 = cam_a_0_bits_data[53]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_107 = cam_d_0_data[53]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_53 = {_indexes_T_106, _indexes_T_107}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_108 = cam_a_0_bits_data[54]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_109 = cam_d_0_data[54]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_54 = {_indexes_T_108, _indexes_T_109}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_110 = cam_a_0_bits_data[55]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _signbits_a_T_6 = cam_a_0_bits_data[55]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64]
wire _indexes_T_111 = cam_d_0_data[55]; // @[AtomicAutomata.scala:84:24, :119:73]
wire _signbits_d_T_6 = cam_d_0_data[55]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64]
wire [1:0] indexes_55 = {_indexes_T_110, _indexes_T_111}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_112 = cam_a_0_bits_data[56]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_113 = cam_d_0_data[56]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_56 = {_indexes_T_112, _indexes_T_113}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_114 = cam_a_0_bits_data[57]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_115 = cam_d_0_data[57]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_57 = {_indexes_T_114, _indexes_T_115}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_116 = cam_a_0_bits_data[58]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_117 = cam_d_0_data[58]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_58 = {_indexes_T_116, _indexes_T_117}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_118 = cam_a_0_bits_data[59]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_119 = cam_d_0_data[59]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_59 = {_indexes_T_118, _indexes_T_119}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_120 = cam_a_0_bits_data[60]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_121 = cam_d_0_data[60]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_60 = {_indexes_T_120, _indexes_T_121}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_122 = cam_a_0_bits_data[61]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_123 = cam_d_0_data[61]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_61 = {_indexes_T_122, _indexes_T_123}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_124 = cam_a_0_bits_data[62]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_125 = cam_d_0_data[62]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_62 = {_indexes_T_124, _indexes_T_125}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_126 = cam_a_0_bits_data[63]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _signbits_a_T_7 = cam_a_0_bits_data[63]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64]
wire _indexes_T_127 = cam_d_0_data[63]; // @[AtomicAutomata.scala:84:24, :119:73]
wire _signbits_d_T_7 = cam_d_0_data[63]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64]
wire [1:0] indexes_63 = {_indexes_T_126, _indexes_T_127}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire [3:0] _logic_out_T = cam_a_0_lut >> indexes_0; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_1 = _logic_out_T[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_2 = cam_a_0_lut >> indexes_1; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_3 = _logic_out_T_2[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_4 = cam_a_0_lut >> indexes_2; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_5 = _logic_out_T_4[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_6 = cam_a_0_lut >> indexes_3; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_7 = _logic_out_T_6[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_8 = cam_a_0_lut >> indexes_4; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_9 = _logic_out_T_8[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_10 = cam_a_0_lut >> indexes_5; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_11 = _logic_out_T_10[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_12 = cam_a_0_lut >> indexes_6; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_13 = _logic_out_T_12[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_14 = cam_a_0_lut >> indexes_7; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_15 = _logic_out_T_14[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_16 = cam_a_0_lut >> indexes_8; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_17 = _logic_out_T_16[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_18 = cam_a_0_lut >> indexes_9; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_19 = _logic_out_T_18[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_20 = cam_a_0_lut >> indexes_10; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_21 = _logic_out_T_20[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_22 = cam_a_0_lut >> indexes_11; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_23 = _logic_out_T_22[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_24 = cam_a_0_lut >> indexes_12; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_25 = _logic_out_T_24[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_26 = cam_a_0_lut >> indexes_13; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_27 = _logic_out_T_26[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_28 = cam_a_0_lut >> indexes_14; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_29 = _logic_out_T_28[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_30 = cam_a_0_lut >> indexes_15; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_31 = _logic_out_T_30[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_32 = cam_a_0_lut >> indexes_16; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_33 = _logic_out_T_32[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_34 = cam_a_0_lut >> indexes_17; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_35 = _logic_out_T_34[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_36 = cam_a_0_lut >> indexes_18; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_37 = _logic_out_T_36[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_38 = cam_a_0_lut >> indexes_19; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_39 = _logic_out_T_38[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_40 = cam_a_0_lut >> indexes_20; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_41 = _logic_out_T_40[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_42 = cam_a_0_lut >> indexes_21; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_43 = _logic_out_T_42[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_44 = cam_a_0_lut >> indexes_22; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_45 = _logic_out_T_44[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_46 = cam_a_0_lut >> indexes_23; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_47 = _logic_out_T_46[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_48 = cam_a_0_lut >> indexes_24; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_49 = _logic_out_T_48[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_50 = cam_a_0_lut >> indexes_25; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_51 = _logic_out_T_50[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_52 = cam_a_0_lut >> indexes_26; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_53 = _logic_out_T_52[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_54 = cam_a_0_lut >> indexes_27; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_55 = _logic_out_T_54[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_56 = cam_a_0_lut >> indexes_28; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_57 = _logic_out_T_56[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_58 = cam_a_0_lut >> indexes_29; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_59 = _logic_out_T_58[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_60 = cam_a_0_lut >> indexes_30; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_61 = _logic_out_T_60[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_62 = cam_a_0_lut >> indexes_31; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_63 = _logic_out_T_62[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_64 = cam_a_0_lut >> indexes_32; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_65 = _logic_out_T_64[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_66 = cam_a_0_lut >> indexes_33; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_67 = _logic_out_T_66[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_68 = cam_a_0_lut >> indexes_34; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_69 = _logic_out_T_68[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_70 = cam_a_0_lut >> indexes_35; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_71 = _logic_out_T_70[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_72 = cam_a_0_lut >> indexes_36; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_73 = _logic_out_T_72[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_74 = cam_a_0_lut >> indexes_37; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_75 = _logic_out_T_74[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_76 = cam_a_0_lut >> indexes_38; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_77 = _logic_out_T_76[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_78 = cam_a_0_lut >> indexes_39; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_79 = _logic_out_T_78[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_80 = cam_a_0_lut >> indexes_40; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_81 = _logic_out_T_80[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_82 = cam_a_0_lut >> indexes_41; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_83 = _logic_out_T_82[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_84 = cam_a_0_lut >> indexes_42; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_85 = _logic_out_T_84[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_86 = cam_a_0_lut >> indexes_43; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_87 = _logic_out_T_86[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_88 = cam_a_0_lut >> indexes_44; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_89 = _logic_out_T_88[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_90 = cam_a_0_lut >> indexes_45; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_91 = _logic_out_T_90[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_92 = cam_a_0_lut >> indexes_46; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_93 = _logic_out_T_92[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_94 = cam_a_0_lut >> indexes_47; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_95 = _logic_out_T_94[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_96 = cam_a_0_lut >> indexes_48; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_97 = _logic_out_T_96[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_98 = cam_a_0_lut >> indexes_49; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_99 = _logic_out_T_98[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_100 = cam_a_0_lut >> indexes_50; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_101 = _logic_out_T_100[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_102 = cam_a_0_lut >> indexes_51; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_103 = _logic_out_T_102[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_104 = cam_a_0_lut >> indexes_52; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_105 = _logic_out_T_104[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_106 = cam_a_0_lut >> indexes_53; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_107 = _logic_out_T_106[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_108 = cam_a_0_lut >> indexes_54; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_109 = _logic_out_T_108[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_110 = cam_a_0_lut >> indexes_55; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_111 = _logic_out_T_110[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_112 = cam_a_0_lut >> indexes_56; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_113 = _logic_out_T_112[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_114 = cam_a_0_lut >> indexes_57; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_115 = _logic_out_T_114[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_116 = cam_a_0_lut >> indexes_58; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_117 = _logic_out_T_116[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_118 = cam_a_0_lut >> indexes_59; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_119 = _logic_out_T_118[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_120 = cam_a_0_lut >> indexes_60; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_121 = _logic_out_T_120[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_122 = cam_a_0_lut >> indexes_61; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_123 = _logic_out_T_122[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_124 = cam_a_0_lut >> indexes_62; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_125 = _logic_out_T_124[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_126 = cam_a_0_lut >> indexes_63; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_127 = _logic_out_T_126[0]; // @[AtomicAutomata.scala:120:57]
wire [1:0] logic_out_lo_lo_lo_lo_lo = {_logic_out_T_3, _logic_out_T_1}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_lo_lo_lo_lo_hi = {_logic_out_T_7, _logic_out_T_5}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_lo_lo_lo_lo = {logic_out_lo_lo_lo_lo_hi, logic_out_lo_lo_lo_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_lo_lo_lo_hi_lo = {_logic_out_T_11, _logic_out_T_9}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_lo_lo_lo_hi_hi = {_logic_out_T_15, _logic_out_T_13}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_lo_lo_lo_hi = {logic_out_lo_lo_lo_hi_hi, logic_out_lo_lo_lo_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [7:0] logic_out_lo_lo_lo = {logic_out_lo_lo_lo_hi, logic_out_lo_lo_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_lo_lo_hi_lo_lo = {_logic_out_T_19, _logic_out_T_17}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_lo_lo_hi_lo_hi = {_logic_out_T_23, _logic_out_T_21}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_lo_lo_hi_lo = {logic_out_lo_lo_hi_lo_hi, logic_out_lo_lo_hi_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_lo_lo_hi_hi_lo = {_logic_out_T_27, _logic_out_T_25}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_lo_lo_hi_hi_hi = {_logic_out_T_31, _logic_out_T_29}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_lo_lo_hi_hi = {logic_out_lo_lo_hi_hi_hi, logic_out_lo_lo_hi_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [7:0] logic_out_lo_lo_hi = {logic_out_lo_lo_hi_hi, logic_out_lo_lo_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [15:0] logic_out_lo_lo = {logic_out_lo_lo_hi, logic_out_lo_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_lo_hi_lo_lo_lo = {_logic_out_T_35, _logic_out_T_33}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_lo_hi_lo_lo_hi = {_logic_out_T_39, _logic_out_T_37}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_lo_hi_lo_lo = {logic_out_lo_hi_lo_lo_hi, logic_out_lo_hi_lo_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_lo_hi_lo_hi_lo = {_logic_out_T_43, _logic_out_T_41}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_lo_hi_lo_hi_hi = {_logic_out_T_47, _logic_out_T_45}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_lo_hi_lo_hi = {logic_out_lo_hi_lo_hi_hi, logic_out_lo_hi_lo_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [7:0] logic_out_lo_hi_lo = {logic_out_lo_hi_lo_hi, logic_out_lo_hi_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_lo_hi_hi_lo_lo = {_logic_out_T_51, _logic_out_T_49}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_lo_hi_hi_lo_hi = {_logic_out_T_55, _logic_out_T_53}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_lo_hi_hi_lo = {logic_out_lo_hi_hi_lo_hi, logic_out_lo_hi_hi_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_lo_hi_hi_hi_lo = {_logic_out_T_59, _logic_out_T_57}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_lo_hi_hi_hi_hi = {_logic_out_T_63, _logic_out_T_61}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_lo_hi_hi_hi = {logic_out_lo_hi_hi_hi_hi, logic_out_lo_hi_hi_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [7:0] logic_out_lo_hi_hi = {logic_out_lo_hi_hi_hi, logic_out_lo_hi_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [15:0] logic_out_lo_hi = {logic_out_lo_hi_hi, logic_out_lo_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [31:0] logic_out_lo = {logic_out_lo_hi, logic_out_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_hi_lo_lo_lo_lo = {_logic_out_T_67, _logic_out_T_65}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_hi_lo_lo_lo_hi = {_logic_out_T_71, _logic_out_T_69}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_hi_lo_lo_lo = {logic_out_hi_lo_lo_lo_hi, logic_out_hi_lo_lo_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_hi_lo_lo_hi_lo = {_logic_out_T_75, _logic_out_T_73}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_hi_lo_lo_hi_hi = {_logic_out_T_79, _logic_out_T_77}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_hi_lo_lo_hi = {logic_out_hi_lo_lo_hi_hi, logic_out_hi_lo_lo_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [7:0] logic_out_hi_lo_lo = {logic_out_hi_lo_lo_hi, logic_out_hi_lo_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_hi_lo_hi_lo_lo = {_logic_out_T_83, _logic_out_T_81}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_hi_lo_hi_lo_hi = {_logic_out_T_87, _logic_out_T_85}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_hi_lo_hi_lo = {logic_out_hi_lo_hi_lo_hi, logic_out_hi_lo_hi_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_hi_lo_hi_hi_lo = {_logic_out_T_91, _logic_out_T_89}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_hi_lo_hi_hi_hi = {_logic_out_T_95, _logic_out_T_93}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_hi_lo_hi_hi = {logic_out_hi_lo_hi_hi_hi, logic_out_hi_lo_hi_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [7:0] logic_out_hi_lo_hi = {logic_out_hi_lo_hi_hi, logic_out_hi_lo_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [15:0] logic_out_hi_lo = {logic_out_hi_lo_hi, logic_out_hi_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_hi_hi_lo_lo_lo = {_logic_out_T_99, _logic_out_T_97}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_hi_hi_lo_lo_hi = {_logic_out_T_103, _logic_out_T_101}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_hi_hi_lo_lo = {logic_out_hi_hi_lo_lo_hi, logic_out_hi_hi_lo_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_hi_hi_lo_hi_lo = {_logic_out_T_107, _logic_out_T_105}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_hi_hi_lo_hi_hi = {_logic_out_T_111, _logic_out_T_109}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_hi_hi_lo_hi = {logic_out_hi_hi_lo_hi_hi, logic_out_hi_hi_lo_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [7:0] logic_out_hi_hi_lo = {logic_out_hi_hi_lo_hi, logic_out_hi_hi_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_hi_hi_hi_lo_lo = {_logic_out_T_115, _logic_out_T_113}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_hi_hi_hi_lo_hi = {_logic_out_T_119, _logic_out_T_117}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_hi_hi_hi_lo = {logic_out_hi_hi_hi_lo_hi, logic_out_hi_hi_hi_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_hi_hi_hi_hi_lo = {_logic_out_T_123, _logic_out_T_121}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_hi_hi_hi_hi_hi = {_logic_out_T_127, _logic_out_T_125}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_hi_hi_hi_hi = {logic_out_hi_hi_hi_hi_hi, logic_out_hi_hi_hi_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [7:0] logic_out_hi_hi_hi = {logic_out_hi_hi_hi_hi, logic_out_hi_hi_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [15:0] logic_out_hi_hi = {logic_out_hi_hi_hi, logic_out_hi_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [31:0] logic_out_hi = {logic_out_hi_hi, logic_out_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [63:0] logic_out = {logic_out_hi, logic_out_lo}; // @[AtomicAutomata.scala:120:28]
wire unsigned_0 = cam_a_0_bits_param[1]; // @[AtomicAutomata.scala:83:24, :123:42]
wire take_max = cam_a_0_bits_param[0]; // @[AtomicAutomata.scala:83:24, :124:42]
wire adder = cam_a_0_bits_param[2]; // @[AtomicAutomata.scala:83:24, :125:39]
wire [7:0] _signSel_T = ~cam_a_0_bits_mask; // @[AtomicAutomata.scala:83:24, :127:25]
wire [6:0] _signSel_T_1 = cam_a_0_bits_mask[7:1]; // @[AtomicAutomata.scala:83:24, :127:39]
wire [7:0] _signSel_T_2 = {_signSel_T[7], _signSel_T[6:0] | _signSel_T_1}; // @[AtomicAutomata.scala:127:{25,31,39}]
wire [7:0] signSel = ~_signSel_T_2; // @[AtomicAutomata.scala:127:{23,31}]
wire [1:0] signbits_a_lo_lo = {_signbits_a_T_1, _signbits_a_T}; // @[AtomicAutomata.scala:128:{29,64}]
wire [1:0] signbits_a_lo_hi = {_signbits_a_T_3, _signbits_a_T_2}; // @[AtomicAutomata.scala:128:{29,64}]
wire [3:0] signbits_a_lo = {signbits_a_lo_hi, signbits_a_lo_lo}; // @[AtomicAutomata.scala:128:29]
wire [1:0] signbits_a_hi_lo = {_signbits_a_T_5, _signbits_a_T_4}; // @[AtomicAutomata.scala:128:{29,64}]
wire [1:0] signbits_a_hi_hi = {_signbits_a_T_7, _signbits_a_T_6}; // @[AtomicAutomata.scala:128:{29,64}]
wire [3:0] signbits_a_hi = {signbits_a_hi_hi, signbits_a_hi_lo}; // @[AtomicAutomata.scala:128:29]
wire [7:0] signbits_a = {signbits_a_hi, signbits_a_lo}; // @[AtomicAutomata.scala:128:29]
wire [1:0] signbits_d_lo_lo = {_signbits_d_T_1, _signbits_d_T}; // @[AtomicAutomata.scala:129:{29,64}]
wire [1:0] signbits_d_lo_hi = {_signbits_d_T_3, _signbits_d_T_2}; // @[AtomicAutomata.scala:129:{29,64}]
wire [3:0] signbits_d_lo = {signbits_d_lo_hi, signbits_d_lo_lo}; // @[AtomicAutomata.scala:129:29]
wire [1:0] signbits_d_hi_lo = {_signbits_d_T_5, _signbits_d_T_4}; // @[AtomicAutomata.scala:129:{29,64}]
wire [1:0] signbits_d_hi_hi = {_signbits_d_T_7, _signbits_d_T_6}; // @[AtomicAutomata.scala:129:{29,64}]
wire [3:0] signbits_d_hi = {signbits_d_hi_hi, signbits_d_hi_lo}; // @[AtomicAutomata.scala:129:29]
wire [7:0] signbits_d = {signbits_d_hi, signbits_d_lo}; // @[AtomicAutomata.scala:129:29]
wire [7:0] _signbit_a_T = signbits_a & signSel; // @[AtomicAutomata.scala:127:23, :128:29, :131:38]
wire [8:0] _signbit_a_T_1 = {_signbit_a_T, 1'h0}; // @[AtomicAutomata.scala:131:{38,49}]
wire [7:0] signbit_a = _signbit_a_T_1[7:0]; // @[AtomicAutomata.scala:131:{49,54}]
wire [7:0] _signbit_d_T = signbits_d & signSel; // @[AtomicAutomata.scala:127:23, :129:29, :132:38]
wire [8:0] _signbit_d_T_1 = {_signbit_d_T, 1'h0}; // @[AtomicAutomata.scala:132:{38,49}]
wire [7:0] signbit_d = _signbit_d_T_1[7:0]; // @[AtomicAutomata.scala:132:{49,54}]
wire [8:0] _signext_a_T = {signbit_a, 1'h0}; // @[package.scala:253:48]
wire [7:0] _signext_a_T_1 = _signext_a_T[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _signext_a_T_2 = signbit_a | _signext_a_T_1; // @[package.scala:253:{43,53}]
wire [9:0] _signext_a_T_3 = {_signext_a_T_2, 2'h0}; // @[package.scala:253:{43,48}]
wire [7:0] _signext_a_T_4 = _signext_a_T_3[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _signext_a_T_5 = _signext_a_T_2 | _signext_a_T_4; // @[package.scala:253:{43,53}]
wire [11:0] _signext_a_T_6 = {_signext_a_T_5, 4'h0}; // @[package.scala:253:{43,48}]
wire [7:0] _signext_a_T_7 = _signext_a_T_6[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _signext_a_T_8 = _signext_a_T_5 | _signext_a_T_7; // @[package.scala:253:{43,53}]
wire [7:0] _signext_a_T_9 = _signext_a_T_8; // @[package.scala:253:43, :254:17]
wire _signext_a_T_10 = _signext_a_T_9[0]; // @[package.scala:254:17]
wire _signext_a_T_11 = _signext_a_T_9[1]; // @[package.scala:254:17]
wire _signext_a_T_12 = _signext_a_T_9[2]; // @[package.scala:254:17]
wire _signext_a_T_13 = _signext_a_T_9[3]; // @[package.scala:254:17]
wire _signext_a_T_14 = _signext_a_T_9[4]; // @[package.scala:254:17]
wire _signext_a_T_15 = _signext_a_T_9[5]; // @[package.scala:254:17]
wire _signext_a_T_16 = _signext_a_T_9[6]; // @[package.scala:254:17]
wire _signext_a_T_17 = _signext_a_T_9[7]; // @[package.scala:254:17]
wire [7:0] _signext_a_T_18 = {8{_signext_a_T_10}}; // @[AtomicAutomata.scala:133:40]
wire [7:0] _signext_a_T_19 = {8{_signext_a_T_11}}; // @[AtomicAutomata.scala:133:40]
wire [7:0] _signext_a_T_20 = {8{_signext_a_T_12}}; // @[AtomicAutomata.scala:133:40]
wire [7:0] _signext_a_T_21 = {8{_signext_a_T_13}}; // @[AtomicAutomata.scala:133:40]
wire [7:0] _signext_a_T_22 = {8{_signext_a_T_14}}; // @[AtomicAutomata.scala:133:40]
wire [7:0] _signext_a_T_23 = {8{_signext_a_T_15}}; // @[AtomicAutomata.scala:133:40]
wire [7:0] _signext_a_T_24 = {8{_signext_a_T_16}}; // @[AtomicAutomata.scala:133:40]
wire [7:0] _signext_a_T_25 = {8{_signext_a_T_17}}; // @[AtomicAutomata.scala:133:40]
wire [15:0] signext_a_lo_lo = {_signext_a_T_19, _signext_a_T_18}; // @[AtomicAutomata.scala:133:40]
wire [15:0] signext_a_lo_hi = {_signext_a_T_21, _signext_a_T_20}; // @[AtomicAutomata.scala:133:40]
wire [31:0] signext_a_lo = {signext_a_lo_hi, signext_a_lo_lo}; // @[AtomicAutomata.scala:133:40]
wire [15:0] signext_a_hi_lo = {_signext_a_T_23, _signext_a_T_22}; // @[AtomicAutomata.scala:133:40]
wire [15:0] signext_a_hi_hi = {_signext_a_T_25, _signext_a_T_24}; // @[AtomicAutomata.scala:133:40]
wire [31:0] signext_a_hi = {signext_a_hi_hi, signext_a_hi_lo}; // @[AtomicAutomata.scala:133:40]
wire [63:0] signext_a = {signext_a_hi, signext_a_lo}; // @[AtomicAutomata.scala:133:40]
wire [8:0] _signext_d_T = {signbit_d, 1'h0}; // @[package.scala:253:48]
wire [7:0] _signext_d_T_1 = _signext_d_T[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _signext_d_T_2 = signbit_d | _signext_d_T_1; // @[package.scala:253:{43,53}]
wire [9:0] _signext_d_T_3 = {_signext_d_T_2, 2'h0}; // @[package.scala:253:{43,48}]
wire [7:0] _signext_d_T_4 = _signext_d_T_3[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _signext_d_T_5 = _signext_d_T_2 | _signext_d_T_4; // @[package.scala:253:{43,53}]
wire [11:0] _signext_d_T_6 = {_signext_d_T_5, 4'h0}; // @[package.scala:253:{43,48}]
wire [7:0] _signext_d_T_7 = _signext_d_T_6[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _signext_d_T_8 = _signext_d_T_5 | _signext_d_T_7; // @[package.scala:253:{43,53}]
wire [7:0] _signext_d_T_9 = _signext_d_T_8; // @[package.scala:253:43, :254:17]
wire _signext_d_T_10 = _signext_d_T_9[0]; // @[package.scala:254:17]
wire _signext_d_T_11 = _signext_d_T_9[1]; // @[package.scala:254:17]
wire _signext_d_T_12 = _signext_d_T_9[2]; // @[package.scala:254:17]
wire _signext_d_T_13 = _signext_d_T_9[3]; // @[package.scala:254:17]
wire _signext_d_T_14 = _signext_d_T_9[4]; // @[package.scala:254:17]
wire _signext_d_T_15 = _signext_d_T_9[5]; // @[package.scala:254:17]
wire _signext_d_T_16 = _signext_d_T_9[6]; // @[package.scala:254:17]
wire _signext_d_T_17 = _signext_d_T_9[7]; // @[package.scala:254:17]
wire [7:0] _signext_d_T_18 = {8{_signext_d_T_10}}; // @[AtomicAutomata.scala:134:40]
wire [7:0] _signext_d_T_19 = {8{_signext_d_T_11}}; // @[AtomicAutomata.scala:134:40]
wire [7:0] _signext_d_T_20 = {8{_signext_d_T_12}}; // @[AtomicAutomata.scala:134:40]
wire [7:0] _signext_d_T_21 = {8{_signext_d_T_13}}; // @[AtomicAutomata.scala:134:40]
wire [7:0] _signext_d_T_22 = {8{_signext_d_T_14}}; // @[AtomicAutomata.scala:134:40]
wire [7:0] _signext_d_T_23 = {8{_signext_d_T_15}}; // @[AtomicAutomata.scala:134:40]
wire [7:0] _signext_d_T_24 = {8{_signext_d_T_16}}; // @[AtomicAutomata.scala:134:40]
wire [7:0] _signext_d_T_25 = {8{_signext_d_T_17}}; // @[AtomicAutomata.scala:134:40]
wire [15:0] signext_d_lo_lo = {_signext_d_T_19, _signext_d_T_18}; // @[AtomicAutomata.scala:134:40]
wire [15:0] signext_d_lo_hi = {_signext_d_T_21, _signext_d_T_20}; // @[AtomicAutomata.scala:134:40]
wire [31:0] signext_d_lo = {signext_d_lo_hi, signext_d_lo_lo}; // @[AtomicAutomata.scala:134:40]
wire [15:0] signext_d_hi_lo = {_signext_d_T_23, _signext_d_T_22}; // @[AtomicAutomata.scala:134:40]
wire [15:0] signext_d_hi_hi = {_signext_d_T_25, _signext_d_T_24}; // @[AtomicAutomata.scala:134:40]
wire [31:0] signext_d_hi = {signext_d_hi_hi, signext_d_hi_lo}; // @[AtomicAutomata.scala:134:40]
wire [63:0] signext_d = {signext_d_hi, signext_d_lo}; // @[AtomicAutomata.scala:134:40]
wire _wide_mask_T = cam_a_0_bits_mask[0]; // @[AtomicAutomata.scala:83:24, :136:40]
wire _wide_mask_T_1 = cam_a_0_bits_mask[1]; // @[AtomicAutomata.scala:83:24, :136:40]
wire _wide_mask_T_2 = cam_a_0_bits_mask[2]; // @[AtomicAutomata.scala:83:24, :136:40]
wire _wide_mask_T_3 = cam_a_0_bits_mask[3]; // @[AtomicAutomata.scala:83:24, :136:40]
wire _wide_mask_T_4 = cam_a_0_bits_mask[4]; // @[AtomicAutomata.scala:83:24, :136:40]
wire _wide_mask_T_5 = cam_a_0_bits_mask[5]; // @[AtomicAutomata.scala:83:24, :136:40]
wire _wide_mask_T_6 = cam_a_0_bits_mask[6]; // @[AtomicAutomata.scala:83:24, :136:40]
wire _wide_mask_T_7 = cam_a_0_bits_mask[7]; // @[AtomicAutomata.scala:83:24, :136:40]
wire [7:0] _wide_mask_T_8 = {8{_wide_mask_T}}; // @[AtomicAutomata.scala:136:40]
wire [7:0] _wide_mask_T_9 = {8{_wide_mask_T_1}}; // @[AtomicAutomata.scala:136:40]
wire [7:0] _wide_mask_T_10 = {8{_wide_mask_T_2}}; // @[AtomicAutomata.scala:136:40]
wire [7:0] _wide_mask_T_11 = {8{_wide_mask_T_3}}; // @[AtomicAutomata.scala:136:40]
wire [7:0] _wide_mask_T_12 = {8{_wide_mask_T_4}}; // @[AtomicAutomata.scala:136:40]
wire [7:0] _wide_mask_T_13 = {8{_wide_mask_T_5}}; // @[AtomicAutomata.scala:136:40]
wire [7:0] _wide_mask_T_14 = {8{_wide_mask_T_6}}; // @[AtomicAutomata.scala:136:40]
wire [7:0] _wide_mask_T_15 = {8{_wide_mask_T_7}}; // @[AtomicAutomata.scala:136:40]
wire [15:0] wide_mask_lo_lo = {_wide_mask_T_9, _wide_mask_T_8}; // @[AtomicAutomata.scala:136:40]
wire [15:0] wide_mask_lo_hi = {_wide_mask_T_11, _wide_mask_T_10}; // @[AtomicAutomata.scala:136:40]
wire [31:0] wide_mask_lo = {wide_mask_lo_hi, wide_mask_lo_lo}; // @[AtomicAutomata.scala:136:40]
wire [15:0] wide_mask_hi_lo = {_wide_mask_T_13, _wide_mask_T_12}; // @[AtomicAutomata.scala:136:40]
wire [15:0] wide_mask_hi_hi = {_wide_mask_T_15, _wide_mask_T_14}; // @[AtomicAutomata.scala:136:40]
wire [31:0] wide_mask_hi = {wide_mask_hi_hi, wide_mask_hi_lo}; // @[AtomicAutomata.scala:136:40]
wire [63:0] wide_mask = {wide_mask_hi, wide_mask_lo}; // @[AtomicAutomata.scala:136:40]
wire [63:0] _a_a_ext_T = cam_a_0_bits_data & wide_mask; // @[AtomicAutomata.scala:83:24, :136:40, :137:28]
wire [63:0] a_a_ext = _a_a_ext_T | signext_a; // @[AtomicAutomata.scala:133:40, :137:{28,41}]
wire [63:0] _a_d_ext_T = cam_d_0_data & wide_mask; // @[AtomicAutomata.scala:84:24, :136:40, :138:28]
wire [63:0] a_d_ext = _a_d_ext_T | signext_d; // @[AtomicAutomata.scala:134:40, :138:{28,41}]
wire [63:0] _a_d_inv_T = ~a_d_ext; // @[AtomicAutomata.scala:138:41, :139:43]
wire [63:0] a_d_inv = adder ? a_d_ext : _a_d_inv_T; // @[AtomicAutomata.scala:125:39, :138:41, :139:{26,43}]
wire [64:0] _adder_out_T = {1'h0, a_a_ext} + {1'h0, a_d_inv}; // @[AtomicAutomata.scala:137:41, :139:26, :140:33]
wire [63:0] adder_out = _adder_out_T[63:0]; // @[AtomicAutomata.scala:140:33]
wire _a_bigger_uneq_T = a_a_ext[63]; // @[AtomicAutomata.scala:137:41, :142:49]
wire _a_bigger_T = a_a_ext[63]; // @[AtomicAutomata.scala:137:41, :142:49, :143:35]
wire a_bigger_uneq = unsigned_0 == _a_bigger_uneq_T; // @[AtomicAutomata.scala:123:42, :142:{38,49}]
wire _a_bigger_T_1 = a_d_ext[63]; // @[AtomicAutomata.scala:138:41, :143:50]
wire _a_bigger_T_2 = _a_bigger_T == _a_bigger_T_1; // @[AtomicAutomata.scala:143:{35,39,50}]
wire _a_bigger_T_3 = adder_out[63]; // @[AtomicAutomata.scala:140:33, :143:65]
wire _a_bigger_T_4 = ~_a_bigger_T_3; // @[AtomicAutomata.scala:143:{55,65}]
wire a_bigger = _a_bigger_T_2 ? _a_bigger_T_4 : a_bigger_uneq; // @[AtomicAutomata.scala:142:38, :143:{27,39,55}]
wire pick_a = take_max == a_bigger; // @[AtomicAutomata.scala:124:42, :143:27, :144:31]
wire [63:0] _arith_out_T = pick_a ? cam_a_0_bits_data : cam_d_0_data; // @[AtomicAutomata.scala:83:24, :84:24, :144:31, :145:50]
wire [63:0] arith_out = adder ? adder_out : _arith_out_T; // @[AtomicAutomata.scala:125:39, :140:33, :145:{28,50}]
wire _amo_data_T = cam_a_0_bits_opcode[0]; // @[AtomicAutomata.scala:83:24, :151:34]
wire [63:0] amo_data = _amo_data_T ? logic_out : arith_out; // @[AtomicAutomata.scala:120:28, :145:28, :151:{14,34}]
wire [63:0] source_c_bits_a_data = amo_data; // @[Edges.scala:480:17]
wire _source_i_ready_T; // @[Arbiter.scala:94:31]
wire _source_i_valid_T; // @[AtomicAutomata.scala:157:38]
wire [2:0] source_i_bits_opcode; // @[AtomicAutomata.scala:154:28]
wire [2:0] source_i_bits_param; // @[AtomicAutomata.scala:154:28]
wire source_i_ready; // @[AtomicAutomata.scala:154:28]
wire source_i_valid; // @[AtomicAutomata.scala:154:28]
wire _a_allow_T = ~a_cam_busy; // @[AtomicAutomata.scala:111:96, :155:23]
wire _a_allow_T_1 = a_isSupported | cam_free_0; // @[AtomicAutomata.scala:86:44, :98:32, :155:53]
wire a_allow = _a_allow_T & _a_allow_T_1; // @[AtomicAutomata.scala:155:{23,35,53}]
assign _nodeIn_a_ready_T = source_i_ready & a_allow; // @[AtomicAutomata.scala:154:28, :155:35, :156:38]
assign nodeIn_a_ready = _nodeIn_a_ready_T; // @[AtomicAutomata.scala:156:38]
assign _source_i_valid_T = nodeIn_a_valid & a_allow; // @[AtomicAutomata.scala:155:35, :157:38]
assign source_i_valid = _source_i_valid_T; // @[AtomicAutomata.scala:154:28, :157:38]
assign source_i_bits_opcode = a_isSupported ? nodeIn_a_bits_opcode : 3'h4; // @[AtomicAutomata.scala:98:32, :154:28, :158:24, :159:31, :160:32]
assign source_i_bits_param = a_isSupported ? nodeIn_a_bits_param : 3'h0; // @[AtomicAutomata.scala:98:32, :154:28, :158:24, :159:31, :161:32]
wire _source_c_ready_T; // @[Arbiter.scala:94:31]
wire [7:0] source_c_bits_a_mask; // @[Edges.scala:480:17]
wire source_c_bits_a_corrupt; // @[Edges.scala:480:17]
wire [3:0] source_c_bits_size; // @[AtomicAutomata.scala:165:28]
wire [6:0] source_c_bits_source; // @[AtomicAutomata.scala:165:28]
wire [31:0] source_c_bits_address; // @[AtomicAutomata.scala:165:28]
wire [7:0] source_c_bits_mask; // @[AtomicAutomata.scala:165:28]
wire [63:0] source_c_bits_data; // @[AtomicAutomata.scala:165:28]
wire source_c_bits_corrupt; // @[AtomicAutomata.scala:165:28]
wire source_c_ready; // @[AtomicAutomata.scala:165:28]
wire _source_c_bits_T = cam_a_0_bits_corrupt | cam_d_0_corrupt; // @[AtomicAutomata.scala:83:24, :84:24, :172:45]
assign source_c_bits_a_corrupt = _source_c_bits_T; // @[Edges.scala:480:17]
wire _source_c_bits_legal_T_1 = cam_a_0_bits_size < 4'hD; // @[AtomicAutomata.scala:83:24]
wire _source_c_bits_legal_T_2 = _source_c_bits_legal_T_1; // @[Parameters.scala:92:{33,38}]
wire _source_c_bits_legal_T_3 = _source_c_bits_legal_T_2; // @[Parameters.scala:684:29]
wire [31:0] _source_c_bits_legal_T_4 = {cam_a_0_bits_address[31:14], cam_a_0_bits_address[13:0] ^ 14'h3000}; // @[AtomicAutomata.scala:83:24]
wire [32:0] _source_c_bits_legal_T_5 = {1'h0, _source_c_bits_legal_T_4}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _source_c_bits_legal_T_6 = _source_c_bits_legal_T_5 & 33'h8A113000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _source_c_bits_legal_T_7 = _source_c_bits_legal_T_6; // @[Parameters.scala:137:46]
wire _source_c_bits_legal_T_8 = _source_c_bits_legal_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _source_c_bits_legal_T_9 = _source_c_bits_legal_T_3 & _source_c_bits_legal_T_8; // @[Parameters.scala:684:{29,54}]
wire _source_c_bits_legal_T_51 = _source_c_bits_legal_T_9; // @[Parameters.scala:684:54, :686:26]
wire _source_c_bits_legal_T_11 = cam_a_0_bits_size < 4'h7; // @[AtomicAutomata.scala:83:24]
wire _source_c_bits_legal_T_12 = _source_c_bits_legal_T_11; // @[Parameters.scala:92:{33,38}]
wire _source_c_bits_legal_T_13 = _source_c_bits_legal_T_12; // @[Parameters.scala:684:29]
wire [32:0] _source_c_bits_legal_T_15 = {1'h0, _source_c_bits_legal_T_14}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _source_c_bits_legal_T_16 = _source_c_bits_legal_T_15 & 33'h8A112000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _source_c_bits_legal_T_17 = _source_c_bits_legal_T_16; // @[Parameters.scala:137:46]
wire _source_c_bits_legal_T_18 = _source_c_bits_legal_T_17 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _source_c_bits_legal_T_19 = {cam_a_0_bits_address[31:21], cam_a_0_bits_address[20:0] ^ 21'h100000}; // @[AtomicAutomata.scala:83:24]
wire [32:0] _source_c_bits_legal_T_20 = {1'h0, _source_c_bits_legal_T_19}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _source_c_bits_legal_T_21 = _source_c_bits_legal_T_20 & 33'h8A103000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _source_c_bits_legal_T_22 = _source_c_bits_legal_T_21; // @[Parameters.scala:137:46]
wire _source_c_bits_legal_T_23 = _source_c_bits_legal_T_22 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _source_c_bits_legal_T_24 = {cam_a_0_bits_address[31:26], cam_a_0_bits_address[25:0] ^ 26'h2000000}; // @[AtomicAutomata.scala:83:24]
wire [32:0] _source_c_bits_legal_T_25 = {1'h0, _source_c_bits_legal_T_24}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _source_c_bits_legal_T_26 = _source_c_bits_legal_T_25 & 33'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _source_c_bits_legal_T_27 = _source_c_bits_legal_T_26; // @[Parameters.scala:137:46]
wire _source_c_bits_legal_T_28 = _source_c_bits_legal_T_27 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _source_c_bits_legal_T_29 = {cam_a_0_bits_address[31:28], cam_a_0_bits_address[27:0] ^ 28'h8000000}; // @[AtomicAutomata.scala:83:24]
wire [32:0] _source_c_bits_legal_T_30 = {1'h0, _source_c_bits_legal_T_29}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _source_c_bits_legal_T_31 = _source_c_bits_legal_T_30 & 33'h88000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _source_c_bits_legal_T_32 = _source_c_bits_legal_T_31; // @[Parameters.scala:137:46]
wire _source_c_bits_legal_T_33 = _source_c_bits_legal_T_32 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _source_c_bits_legal_T_34 = cam_a_0_bits_address ^ 32'h80000000; // @[AtomicAutomata.scala:83:24]
wire [32:0] _source_c_bits_legal_T_35 = {1'h0, _source_c_bits_legal_T_34}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _source_c_bits_legal_T_36 = _source_c_bits_legal_T_35 & 33'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _source_c_bits_legal_T_37 = _source_c_bits_legal_T_36; // @[Parameters.scala:137:46]
wire _source_c_bits_legal_T_38 = _source_c_bits_legal_T_37 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _source_c_bits_legal_T_39 = _source_c_bits_legal_T_18 | _source_c_bits_legal_T_23; // @[Parameters.scala:685:42]
wire _source_c_bits_legal_T_40 = _source_c_bits_legal_T_39 | _source_c_bits_legal_T_28; // @[Parameters.scala:685:42]
wire _source_c_bits_legal_T_41 = _source_c_bits_legal_T_40 | _source_c_bits_legal_T_33; // @[Parameters.scala:685:42]
wire _source_c_bits_legal_T_42 = _source_c_bits_legal_T_41 | _source_c_bits_legal_T_38; // @[Parameters.scala:685:42]
wire _source_c_bits_legal_T_43 = _source_c_bits_legal_T_13 & _source_c_bits_legal_T_42; // @[Parameters.scala:684:{29,54}, :685:42]
wire [31:0] _source_c_bits_legal_T_45 = {cam_a_0_bits_address[31:17], cam_a_0_bits_address[16:0] ^ 17'h10000}; // @[AtomicAutomata.scala:83:24]
wire [32:0] _source_c_bits_legal_T_46 = {1'h0, _source_c_bits_legal_T_45}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _source_c_bits_legal_T_47 = _source_c_bits_legal_T_46 & 33'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _source_c_bits_legal_T_48 = _source_c_bits_legal_T_47; // @[Parameters.scala:137:46]
wire _source_c_bits_legal_T_49 = _source_c_bits_legal_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _source_c_bits_legal_T_52 = _source_c_bits_legal_T_51 | _source_c_bits_legal_T_43; // @[Parameters.scala:684:54, :686:26]
wire source_c_bits_legal = _source_c_bits_legal_T_52; // @[Parameters.scala:686:26]
assign source_c_bits_size = source_c_bits_a_size; // @[Edges.scala:480:17]
assign source_c_bits_source = source_c_bits_a_source; // @[Edges.scala:480:17]
assign source_c_bits_address = source_c_bits_a_address; // @[Edges.scala:480:17]
wire [7:0] _source_c_bits_a_mask_T; // @[Misc.scala:222:10]
assign source_c_bits_mask = source_c_bits_a_mask; // @[Edges.scala:480:17]
assign source_c_bits_data = source_c_bits_a_data; // @[Edges.scala:480:17]
assign source_c_bits_corrupt = source_c_bits_a_corrupt; // @[Edges.scala:480:17]
wire [1:0] source_c_bits_a_mask_sizeOH_shiftAmount = _source_c_bits_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _source_c_bits_a_mask_sizeOH_T_1 = 4'h1 << source_c_bits_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _source_c_bits_a_mask_sizeOH_T_2 = _source_c_bits_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] source_c_bits_a_mask_sizeOH = {_source_c_bits_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire source_c_bits_a_mask_sub_sub_sub_0_1 = cam_a_0_bits_size > 4'h2; // @[Misc.scala:206:21]
wire source_c_bits_a_mask_sub_sub_size = source_c_bits_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire source_c_bits_a_mask_sub_sub_bit = cam_a_0_bits_address[2]; // @[Misc.scala:210:26]
wire source_c_bits_a_mask_sub_sub_1_2 = source_c_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire source_c_bits_a_mask_sub_sub_nbit = ~source_c_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire source_c_bits_a_mask_sub_sub_0_2 = source_c_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _source_c_bits_a_mask_sub_sub_acc_T = source_c_bits_a_mask_sub_sub_size & source_c_bits_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_sub_sub_0_1 = source_c_bits_a_mask_sub_sub_sub_0_1 | _source_c_bits_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _source_c_bits_a_mask_sub_sub_acc_T_1 = source_c_bits_a_mask_sub_sub_size & source_c_bits_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_sub_sub_1_1 = source_c_bits_a_mask_sub_sub_sub_0_1 | _source_c_bits_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire source_c_bits_a_mask_sub_size = source_c_bits_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire source_c_bits_a_mask_sub_bit = cam_a_0_bits_address[1]; // @[Misc.scala:210:26]
wire source_c_bits_a_mask_sub_nbit = ~source_c_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire source_c_bits_a_mask_sub_0_2 = source_c_bits_a_mask_sub_sub_0_2 & source_c_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _source_c_bits_a_mask_sub_acc_T = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_sub_0_1 = source_c_bits_a_mask_sub_sub_0_1 | _source_c_bits_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_sub_1_2 = source_c_bits_a_mask_sub_sub_0_2 & source_c_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _source_c_bits_a_mask_sub_acc_T_1 = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_sub_1_1 = source_c_bits_a_mask_sub_sub_0_1 | _source_c_bits_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_sub_2_2 = source_c_bits_a_mask_sub_sub_1_2 & source_c_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _source_c_bits_a_mask_sub_acc_T_2 = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_sub_2_1 = source_c_bits_a_mask_sub_sub_1_1 | _source_c_bits_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_sub_3_2 = source_c_bits_a_mask_sub_sub_1_2 & source_c_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _source_c_bits_a_mask_sub_acc_T_3 = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_sub_3_1 = source_c_bits_a_mask_sub_sub_1_1 | _source_c_bits_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_size = source_c_bits_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire source_c_bits_a_mask_bit = cam_a_0_bits_address[0]; // @[Misc.scala:210:26]
wire source_c_bits_a_mask_nbit = ~source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20]
wire source_c_bits_a_mask_eq = source_c_bits_a_mask_sub_0_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _source_c_bits_a_mask_acc_T = source_c_bits_a_mask_size & source_c_bits_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_acc = source_c_bits_a_mask_sub_0_1 | _source_c_bits_a_mask_acc_T; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_eq_1 = source_c_bits_a_mask_sub_0_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _source_c_bits_a_mask_acc_T_1 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_acc_1 = source_c_bits_a_mask_sub_0_1 | _source_c_bits_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_eq_2 = source_c_bits_a_mask_sub_1_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _source_c_bits_a_mask_acc_T_2 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_acc_2 = source_c_bits_a_mask_sub_1_1 | _source_c_bits_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_eq_3 = source_c_bits_a_mask_sub_1_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _source_c_bits_a_mask_acc_T_3 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_acc_3 = source_c_bits_a_mask_sub_1_1 | _source_c_bits_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_eq_4 = source_c_bits_a_mask_sub_2_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _source_c_bits_a_mask_acc_T_4 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_acc_4 = source_c_bits_a_mask_sub_2_1 | _source_c_bits_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_eq_5 = source_c_bits_a_mask_sub_2_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _source_c_bits_a_mask_acc_T_5 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_acc_5 = source_c_bits_a_mask_sub_2_1 | _source_c_bits_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_eq_6 = source_c_bits_a_mask_sub_3_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _source_c_bits_a_mask_acc_T_6 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_acc_6 = source_c_bits_a_mask_sub_3_1 | _source_c_bits_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_eq_7 = source_c_bits_a_mask_sub_3_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _source_c_bits_a_mask_acc_T_7 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_acc_7 = source_c_bits_a_mask_sub_3_1 | _source_c_bits_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] source_c_bits_a_mask_lo_lo = {source_c_bits_a_mask_acc_1, source_c_bits_a_mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] source_c_bits_a_mask_lo_hi = {source_c_bits_a_mask_acc_3, source_c_bits_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] source_c_bits_a_mask_lo = {source_c_bits_a_mask_lo_hi, source_c_bits_a_mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] source_c_bits_a_mask_hi_lo = {source_c_bits_a_mask_acc_5, source_c_bits_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] source_c_bits_a_mask_hi_hi = {source_c_bits_a_mask_acc_7, source_c_bits_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] source_c_bits_a_mask_hi = {source_c_bits_a_mask_hi_hi, source_c_bits_a_mask_hi_lo}; // @[Misc.scala:222:10]
assign _source_c_bits_a_mask_T = {source_c_bits_a_mask_hi, source_c_bits_a_mask_lo}; // @[Misc.scala:222:10]
assign source_c_bits_a_mask = _source_c_bits_a_mask_T; // @[Misc.scala:222:10]
wire [26:0] _decode_T = 27'hFFF << nodeIn_a_bits_size; // @[package.scala:243:71]
wire [11:0] _decode_T_1 = _decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _decode_T_2 = ~_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] decode = _decode_T_2[11:3]; // @[package.scala:243:46]
wire _opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire opdata = ~_opdata_T; // @[Edges.scala:92:{28,37}]
reg [8:0] beatsLeft; // @[Arbiter.scala:60:30]
wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch = idle & nodeOut_a_ready; // @[Arbiter.scala:61:28, :62:24]
wire [1:0] _readys_T = {source_i_valid, source_c_valid}; // @[AtomicAutomata.scala:154:28, :165:28]
wire [2:0] _readys_T_1 = {_readys_T, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_T_2 = _readys_T_1[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_T_3 = _readys_T | _readys_T_2; // @[package.scala:253:{43,53}]
wire [1:0] _readys_T_4 = _readys_T_3; // @[package.scala:253:43, :254:17]
wire [2:0] _readys_T_5 = {_readys_T_4, 1'h0}; // @[package.scala:254:17]
wire [1:0] _readys_T_6 = _readys_T_5[1:0]; // @[Arbiter.scala:16:{78,83}]
wire [1:0] _readys_T_7 = ~_readys_T_6; // @[Arbiter.scala:16:{61,83}]
wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:16:61, :68:76]
wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:16:61, :68:76]
wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}]
wire _winner_T = readys_0 & source_c_valid; // @[AtomicAutomata.scala:165:28]
wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_1 = readys_1 & source_i_valid; // @[AtomicAutomata.scala:154:28]
wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48]
wire _nodeOut_a_valid_T = source_c_valid | source_i_valid; // @[AtomicAutomata.scala:154:28, :165:28] |
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_59 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, flip out_credit_available : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<3>, sa_stall : UInt<3>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}}
inst input_buffer of InputBuffer_59
connect input_buffer.clock, clock
connect input_buffer.reset, reset
connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id
connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id
connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node
connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id
connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node
connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id
connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload
connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail
connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head
connect input_buffer.io.enq[0].valid, io.in.flit[0].valid
connect input_buffer.io.deq[0].ready, UInt<1>(0h0)
connect input_buffer.io.deq[1].ready, UInt<1>(0h0)
connect input_buffer.io.deq[2].ready, UInt<1>(0h0)
connect input_buffer.io.deq[3].ready, UInt<1>(0h0)
connect input_buffer.io.deq[4].ready, UInt<1>(0h0)
connect input_buffer.io.deq[5].ready, UInt<1>(0h0)
connect input_buffer.io.deq[6].ready, UInt<1>(0h0)
connect input_buffer.io.deq[7].ready, UInt<1>(0h0)
inst route_arbiter of Arbiter8_RouteComputerReq_59
connect route_arbiter.clock, clock
connect route_arbiter.reset, reset
connect io.router_req.bits, route_arbiter.io.out.bits
connect io.router_req.valid, route_arbiter.io.out.valid
connect route_arbiter.io.out.ready, io.router_req.ready
reg states : { g : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, fifo_deps : UInt<8>}[8], clock
node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T :
node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h8))
node _T_2 = asUInt(reset)
node _T_3 = eq(_T_2, UInt<1>(0h0))
when _T_3 :
node _T_4 = eq(_T_1, UInt<1>(0h0))
when _T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf
assert(clock, _T_1, UInt<1>(0h1), "") : assert
node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0))
node _T_6 = asUInt(reset)
node _T_7 = eq(_T_6, UInt<1>(0h0))
when _T_7 :
node _T_8 = eq(_T_5, UInt<1>(0h0))
when _T_8 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1
assert(clock, _T_5, UInt<1>(0h1), "") : assert_1
node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<5>(0h1b))
node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1))
connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[5], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[6], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[7], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[5], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[6], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[7], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[5], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[6], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[7], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[5], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[6], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[7], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow
node _route_arbiter_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h1))
connect route_arbiter.io.in[0].valid, _route_arbiter_io_in_0_valid_T
connect route_arbiter.io.in[0].bits.flow.egress_node_id, states[0].flow.egress_node_id
connect route_arbiter.io.in[0].bits.flow.egress_node, states[0].flow.egress_node
connect route_arbiter.io.in[0].bits.flow.ingress_node_id, states[0].flow.ingress_node_id
connect route_arbiter.io.in[0].bits.flow.ingress_node, states[0].flow.ingress_node
connect route_arbiter.io.in[0].bits.flow.vnet_id, states[0].flow.vnet_id
connect route_arbiter.io.in[0].bits.src_virt_id, UInt<1>(0h0)
node _T_9 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid)
when _T_9 :
connect states[0].g, UInt<3>(0h2)
node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1))
connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T
connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id
connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node
connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id
connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node
connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id
connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1)
node _T_10 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid)
when _T_10 :
connect states[1].g, UInt<3>(0h2)
node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1))
connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T
connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id
connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node
connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id
connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node
connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id
connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2)
node _T_11 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid)
when _T_11 :
connect states[2].g, UInt<3>(0h2)
node _route_arbiter_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h1))
connect route_arbiter.io.in[3].valid, _route_arbiter_io_in_3_valid_T
connect route_arbiter.io.in[3].bits.flow.egress_node_id, states[3].flow.egress_node_id
connect route_arbiter.io.in[3].bits.flow.egress_node, states[3].flow.egress_node
connect route_arbiter.io.in[3].bits.flow.ingress_node_id, states[3].flow.ingress_node_id
connect route_arbiter.io.in[3].bits.flow.ingress_node, states[3].flow.ingress_node
connect route_arbiter.io.in[3].bits.flow.vnet_id, states[3].flow.vnet_id
connect route_arbiter.io.in[3].bits.src_virt_id, UInt<2>(0h3)
node _T_12 = and(route_arbiter.io.in[3].ready, route_arbiter.io.in[3].valid)
when _T_12 :
connect states[3].g, UInt<3>(0h2)
node _route_arbiter_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h1))
connect route_arbiter.io.in[4].valid, _route_arbiter_io_in_4_valid_T
connect route_arbiter.io.in[4].bits.flow.egress_node_id, states[4].flow.egress_node_id
connect route_arbiter.io.in[4].bits.flow.egress_node, states[4].flow.egress_node
connect route_arbiter.io.in[4].bits.flow.ingress_node_id, states[4].flow.ingress_node_id
connect route_arbiter.io.in[4].bits.flow.ingress_node, states[4].flow.ingress_node
connect route_arbiter.io.in[4].bits.flow.vnet_id, states[4].flow.vnet_id
connect route_arbiter.io.in[4].bits.src_virt_id, UInt<3>(0h4)
node _T_13 = and(route_arbiter.io.in[4].ready, route_arbiter.io.in[4].valid)
when _T_13 :
connect states[4].g, UInt<3>(0h2)
node _route_arbiter_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h1))
connect route_arbiter.io.in[5].valid, _route_arbiter_io_in_5_valid_T
connect route_arbiter.io.in[5].bits.flow.egress_node_id, states[5].flow.egress_node_id
connect route_arbiter.io.in[5].bits.flow.egress_node, states[5].flow.egress_node
connect route_arbiter.io.in[5].bits.flow.ingress_node_id, states[5].flow.ingress_node_id
connect route_arbiter.io.in[5].bits.flow.ingress_node, states[5].flow.ingress_node
connect route_arbiter.io.in[5].bits.flow.vnet_id, states[5].flow.vnet_id
connect route_arbiter.io.in[5].bits.src_virt_id, UInt<3>(0h5)
node _T_14 = and(route_arbiter.io.in[5].ready, route_arbiter.io.in[5].valid)
when _T_14 :
connect states[5].g, UInt<3>(0h2)
node _route_arbiter_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h1))
connect route_arbiter.io.in[6].valid, _route_arbiter_io_in_6_valid_T
connect route_arbiter.io.in[6].bits.flow.egress_node_id, states[6].flow.egress_node_id
connect route_arbiter.io.in[6].bits.flow.egress_node, states[6].flow.egress_node
connect route_arbiter.io.in[6].bits.flow.ingress_node_id, states[6].flow.ingress_node_id
connect route_arbiter.io.in[6].bits.flow.ingress_node, states[6].flow.ingress_node
connect route_arbiter.io.in[6].bits.flow.vnet_id, states[6].flow.vnet_id
connect route_arbiter.io.in[6].bits.src_virt_id, UInt<3>(0h6)
node _T_15 = and(route_arbiter.io.in[6].ready, route_arbiter.io.in[6].valid)
when _T_15 :
connect states[6].g, UInt<3>(0h2)
node _route_arbiter_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h1))
connect route_arbiter.io.in[7].valid, _route_arbiter_io_in_7_valid_T
connect route_arbiter.io.in[7].bits.flow.egress_node_id, states[7].flow.egress_node_id
connect route_arbiter.io.in[7].bits.flow.egress_node, states[7].flow.egress_node
connect route_arbiter.io.in[7].bits.flow.ingress_node_id, states[7].flow.ingress_node_id
connect route_arbiter.io.in[7].bits.flow.ingress_node, states[7].flow.ingress_node
connect route_arbiter.io.in[7].bits.flow.vnet_id, states[7].flow.vnet_id
connect route_arbiter.io.in[7].bits.src_virt_id, UInt<3>(0h7)
node _T_16 = and(route_arbiter.io.in[7].ready, route_arbiter.io.in[7].valid)
when _T_16 :
connect states[7].g, UInt<3>(0h2)
node _T_17 = and(io.router_req.ready, io.router_req.valid)
when _T_17 :
node _T_18 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1))
node _T_19 = asUInt(reset)
node _T_20 = eq(_T_19, UInt<1>(0h0))
when _T_20 :
node _T_21 = eq(_T_18, UInt<1>(0h0))
when _T_21 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2
assert(clock, _T_18, UInt<1>(0h1), "") : assert_2
connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2)
node _T_22 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id)
when _T_22 :
connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_23 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id)
when _T_23 :
connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_24 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id)
when _T_24 :
connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[2].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_25 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id)
when _T_25 :
connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[3].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[3].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_26 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id)
when _T_26 :
connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[4].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[4].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_27 = eq(UInt<3>(0h5), io.router_req.bits.src_virt_id)
when _T_27 :
connect states[5].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[5].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[5].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[5].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_28 = eq(UInt<3>(0h6), io.router_req.bits.src_virt_id)
when _T_28 :
connect states[6].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[6].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[6].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[6].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_29 = eq(UInt<3>(0h7), io.router_req.bits.src_virt_id)
when _T_29 :
connect states[7].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[7].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[7].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[7].vc_sel.`3`, io.router_resp.vc_sel.`3`
regreset mask : UInt<8>, clock, reset, UInt<8>(0h0)
wire vcalloc_reqs : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}[8]
wire vcalloc_vals : UInt<1>[8]
node vcalloc_filter_lo_lo = cat(vcalloc_vals[1], vcalloc_vals[0])
node vcalloc_filter_lo_hi = cat(vcalloc_vals[3], vcalloc_vals[2])
node vcalloc_filter_lo = cat(vcalloc_filter_lo_hi, vcalloc_filter_lo_lo)
node vcalloc_filter_hi_lo = cat(vcalloc_vals[5], vcalloc_vals[4])
node vcalloc_filter_hi_hi = cat(vcalloc_vals[7], vcalloc_vals[6])
node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_filter_hi_lo)
node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo)
node vcalloc_filter_lo_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0])
node vcalloc_filter_lo_hi_1 = cat(vcalloc_vals[3], vcalloc_vals[2])
node vcalloc_filter_lo_1 = cat(vcalloc_filter_lo_hi_1, vcalloc_filter_lo_lo_1)
node vcalloc_filter_hi_lo_1 = cat(vcalloc_vals[5], vcalloc_vals[4])
node vcalloc_filter_hi_hi_1 = cat(vcalloc_vals[7], vcalloc_vals[6])
node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_filter_hi_lo_1)
node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1)
node _vcalloc_filter_T_2 = not(mask)
node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2)
node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3)
node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0)
node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1)
node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2)
node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3)
node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4)
node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5)
node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6)
node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7)
node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8)
node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9)
node _vcalloc_filter_T_15 = bits(_vcalloc_filter_T_4, 10, 10)
node _vcalloc_filter_T_16 = bits(_vcalloc_filter_T_4, 11, 11)
node _vcalloc_filter_T_17 = bits(_vcalloc_filter_T_4, 12, 12)
node _vcalloc_filter_T_18 = bits(_vcalloc_filter_T_4, 13, 13)
node _vcalloc_filter_T_19 = bits(_vcalloc_filter_T_4, 14, 14)
node _vcalloc_filter_T_20 = bits(_vcalloc_filter_T_4, 15, 15)
node _vcalloc_filter_T_21 = mux(_vcalloc_filter_T_20, UInt<16>(0h8000), UInt<16>(0h0))
node _vcalloc_filter_T_22 = mux(_vcalloc_filter_T_19, UInt<16>(0h4000), _vcalloc_filter_T_21)
node _vcalloc_filter_T_23 = mux(_vcalloc_filter_T_18, UInt<16>(0h2000), _vcalloc_filter_T_22)
node _vcalloc_filter_T_24 = mux(_vcalloc_filter_T_17, UInt<16>(0h1000), _vcalloc_filter_T_23)
node _vcalloc_filter_T_25 = mux(_vcalloc_filter_T_16, UInt<16>(0h800), _vcalloc_filter_T_24)
node _vcalloc_filter_T_26 = mux(_vcalloc_filter_T_15, UInt<16>(0h400), _vcalloc_filter_T_25)
node _vcalloc_filter_T_27 = mux(_vcalloc_filter_T_14, UInt<16>(0h200), _vcalloc_filter_T_26)
node _vcalloc_filter_T_28 = mux(_vcalloc_filter_T_13, UInt<16>(0h100), _vcalloc_filter_T_27)
node _vcalloc_filter_T_29 = mux(_vcalloc_filter_T_12, UInt<16>(0h80), _vcalloc_filter_T_28)
node _vcalloc_filter_T_30 = mux(_vcalloc_filter_T_11, UInt<16>(0h40), _vcalloc_filter_T_29)
node _vcalloc_filter_T_31 = mux(_vcalloc_filter_T_10, UInt<16>(0h20), _vcalloc_filter_T_30)
node _vcalloc_filter_T_32 = mux(_vcalloc_filter_T_9, UInt<16>(0h10), _vcalloc_filter_T_31)
node _vcalloc_filter_T_33 = mux(_vcalloc_filter_T_8, UInt<16>(0h8), _vcalloc_filter_T_32)
node _vcalloc_filter_T_34 = mux(_vcalloc_filter_T_7, UInt<16>(0h4), _vcalloc_filter_T_33)
node _vcalloc_filter_T_35 = mux(_vcalloc_filter_T_6, UInt<16>(0h2), _vcalloc_filter_T_34)
node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<16>(0h1), _vcalloc_filter_T_35)
node _vcalloc_sel_T = bits(vcalloc_filter, 7, 0)
node _vcalloc_sel_T_1 = shr(vcalloc_filter, 8)
node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1)
node _T_30 = and(io.router_req.ready, io.router_req.valid)
when _T_30 :
node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id)
node _mask_T_1 = sub(_mask_T, UInt<1>(0h1))
node _mask_T_2 = tail(_mask_T_1, 1)
connect mask, _mask_T_2
else :
node _T_31 = or(vcalloc_vals[0], vcalloc_vals[1])
node _T_32 = or(_T_31, vcalloc_vals[2])
node _T_33 = or(_T_32, vcalloc_vals[3])
node _T_34 = or(_T_33, vcalloc_vals[4])
node _T_35 = or(_T_34, vcalloc_vals[5])
node _T_36 = or(_T_35, vcalloc_vals[6])
node _T_37 = or(_T_36, vcalloc_vals[7])
when _T_37 :
node _mask_T_3 = not(UInt<1>(0h0))
node _mask_T_4 = not(UInt<2>(0h0))
node _mask_T_5 = not(UInt<3>(0h0))
node _mask_T_6 = not(UInt<4>(0h0))
node _mask_T_7 = not(UInt<5>(0h0))
node _mask_T_8 = not(UInt<6>(0h0))
node _mask_T_9 = not(UInt<7>(0h0))
node _mask_T_10 = not(UInt<8>(0h0))
node _mask_T_11 = bits(vcalloc_sel, 0, 0)
node _mask_T_12 = bits(vcalloc_sel, 1, 1)
node _mask_T_13 = bits(vcalloc_sel, 2, 2)
node _mask_T_14 = bits(vcalloc_sel, 3, 3)
node _mask_T_15 = bits(vcalloc_sel, 4, 4)
node _mask_T_16 = bits(vcalloc_sel, 5, 5)
node _mask_T_17 = bits(vcalloc_sel, 6, 6)
node _mask_T_18 = bits(vcalloc_sel, 7, 7)
node _mask_T_19 = mux(_mask_T_11, _mask_T_3, UInt<1>(0h0))
node _mask_T_20 = mux(_mask_T_12, _mask_T_4, UInt<1>(0h0))
node _mask_T_21 = mux(_mask_T_13, _mask_T_5, UInt<1>(0h0))
node _mask_T_22 = mux(_mask_T_14, _mask_T_6, UInt<1>(0h0))
node _mask_T_23 = mux(_mask_T_15, _mask_T_7, UInt<1>(0h0))
node _mask_T_24 = mux(_mask_T_16, _mask_T_8, UInt<1>(0h0))
node _mask_T_25 = mux(_mask_T_17, _mask_T_9, UInt<1>(0h0))
node _mask_T_26 = mux(_mask_T_18, _mask_T_10, UInt<1>(0h0))
node _mask_T_27 = or(_mask_T_19, _mask_T_20)
node _mask_T_28 = or(_mask_T_27, _mask_T_21)
node _mask_T_29 = or(_mask_T_28, _mask_T_22)
node _mask_T_30 = or(_mask_T_29, _mask_T_23)
node _mask_T_31 = or(_mask_T_30, _mask_T_24)
node _mask_T_32 = or(_mask_T_31, _mask_T_25)
node _mask_T_33 = or(_mask_T_32, _mask_T_26)
wire _mask_WIRE : UInt<8>
connect _mask_WIRE, _mask_T_33
connect mask, _mask_WIRE
node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1])
node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2])
node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3])
node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4])
node _io_vcalloc_req_valid_T_4 = or(_io_vcalloc_req_valid_T_3, vcalloc_vals[5])
node _io_vcalloc_req_valid_T_5 = or(_io_vcalloc_req_valid_T_4, vcalloc_vals[6])
node _io_vcalloc_req_valid_T_6 = or(_io_vcalloc_req_valid_T_5, vcalloc_vals[7])
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_6
node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0)
node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1)
node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2)
node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3)
node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4)
node _io_vcalloc_req_bits_T_5 = bits(vcalloc_sel, 5, 5)
node _io_vcalloc_req_bits_T_6 = bits(vcalloc_sel, 6, 6)
node _io_vcalloc_req_bits_T_7 = bits(vcalloc_sel, 7, 7)
wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}
wire _io_vcalloc_req_bits_WIRE_1 : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}
wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[8]
node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9)
node _io_vcalloc_req_bits_T_17 = or(_io_vcalloc_req_bits_T_16, _io_vcalloc_req_bits_T_10)
node _io_vcalloc_req_bits_T_18 = or(_io_vcalloc_req_bits_T_17, _io_vcalloc_req_bits_T_11)
node _io_vcalloc_req_bits_T_19 = or(_io_vcalloc_req_bits_T_18, _io_vcalloc_req_bits_T_12)
node _io_vcalloc_req_bits_T_20 = or(_io_vcalloc_req_bits_T_19, _io_vcalloc_req_bits_T_13)
node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_14)
node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_15)
wire _io_vcalloc_req_bits_WIRE_3 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_22
connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3
node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_26 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_27 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24)
node _io_vcalloc_req_bits_T_32 = or(_io_vcalloc_req_bits_T_31, _io_vcalloc_req_bits_T_25)
node _io_vcalloc_req_bits_T_33 = or(_io_vcalloc_req_bits_T_32, _io_vcalloc_req_bits_T_26)
node _io_vcalloc_req_bits_T_34 = or(_io_vcalloc_req_bits_T_33, _io_vcalloc_req_bits_T_27)
node _io_vcalloc_req_bits_T_35 = or(_io_vcalloc_req_bits_T_34, _io_vcalloc_req_bits_T_28)
node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_35, _io_vcalloc_req_bits_T_29)
node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_30)
wire _io_vcalloc_req_bits_WIRE_4 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_37
connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4
node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_41 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_42 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39)
node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_40)
node _io_vcalloc_req_bits_T_48 = or(_io_vcalloc_req_bits_T_47, _io_vcalloc_req_bits_T_41)
node _io_vcalloc_req_bits_T_49 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_42)
node _io_vcalloc_req_bits_T_50 = or(_io_vcalloc_req_bits_T_49, _io_vcalloc_req_bits_T_43)
node _io_vcalloc_req_bits_T_51 = or(_io_vcalloc_req_bits_T_50, _io_vcalloc_req_bits_T_44)
node _io_vcalloc_req_bits_T_52 = or(_io_vcalloc_req_bits_T_51, _io_vcalloc_req_bits_T_45)
wire _io_vcalloc_req_bits_WIRE_5 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_52
connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5
node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_56 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_57 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_58 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_53, _io_vcalloc_req_bits_T_54)
node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_55)
node _io_vcalloc_req_bits_T_63 = or(_io_vcalloc_req_bits_T_62, _io_vcalloc_req_bits_T_56)
node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_57)
node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_58)
node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_59)
node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_60)
wire _io_vcalloc_req_bits_WIRE_6 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_67
connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6
node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_71 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69)
node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_76, _io_vcalloc_req_bits_T_70)
node _io_vcalloc_req_bits_T_78 = or(_io_vcalloc_req_bits_T_77, _io_vcalloc_req_bits_T_71)
node _io_vcalloc_req_bits_T_79 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_72)
node _io_vcalloc_req_bits_T_80 = or(_io_vcalloc_req_bits_T_79, _io_vcalloc_req_bits_T_73)
node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_80, _io_vcalloc_req_bits_T_74)
node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_75)
wire _io_vcalloc_req_bits_WIRE_7 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_82
connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7
node _io_vcalloc_req_bits_T_83 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_84 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_85 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_91 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_84)
node _io_vcalloc_req_bits_T_92 = or(_io_vcalloc_req_bits_T_91, _io_vcalloc_req_bits_T_85)
node _io_vcalloc_req_bits_T_93 = or(_io_vcalloc_req_bits_T_92, _io_vcalloc_req_bits_T_86)
node _io_vcalloc_req_bits_T_94 = or(_io_vcalloc_req_bits_T_93, _io_vcalloc_req_bits_T_87)
node _io_vcalloc_req_bits_T_95 = or(_io_vcalloc_req_bits_T_94, _io_vcalloc_req_bits_T_88)
node _io_vcalloc_req_bits_T_96 = or(_io_vcalloc_req_bits_T_95, _io_vcalloc_req_bits_T_89)
node _io_vcalloc_req_bits_T_97 = or(_io_vcalloc_req_bits_T_96, _io_vcalloc_req_bits_T_90)
wire _io_vcalloc_req_bits_WIRE_8 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_97
connect _io_vcalloc_req_bits_WIRE_2[5], _io_vcalloc_req_bits_WIRE_8
node _io_vcalloc_req_bits_T_98 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_99 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_100 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_101 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_102 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_103 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_104 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_106 = or(_io_vcalloc_req_bits_T_98, _io_vcalloc_req_bits_T_99)
node _io_vcalloc_req_bits_T_107 = or(_io_vcalloc_req_bits_T_106, _io_vcalloc_req_bits_T_100)
node _io_vcalloc_req_bits_T_108 = or(_io_vcalloc_req_bits_T_107, _io_vcalloc_req_bits_T_101)
node _io_vcalloc_req_bits_T_109 = or(_io_vcalloc_req_bits_T_108, _io_vcalloc_req_bits_T_102)
node _io_vcalloc_req_bits_T_110 = or(_io_vcalloc_req_bits_T_109, _io_vcalloc_req_bits_T_103)
node _io_vcalloc_req_bits_T_111 = or(_io_vcalloc_req_bits_T_110, _io_vcalloc_req_bits_T_104)
node _io_vcalloc_req_bits_T_112 = or(_io_vcalloc_req_bits_T_111, _io_vcalloc_req_bits_T_105)
wire _io_vcalloc_req_bits_WIRE_9 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_112
connect _io_vcalloc_req_bits_WIRE_2[6], _io_vcalloc_req_bits_WIRE_9
node _io_vcalloc_req_bits_T_113 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_114 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_115 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_116 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_117 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_118 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_119 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_120 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_121 = or(_io_vcalloc_req_bits_T_113, _io_vcalloc_req_bits_T_114)
node _io_vcalloc_req_bits_T_122 = or(_io_vcalloc_req_bits_T_121, _io_vcalloc_req_bits_T_115)
node _io_vcalloc_req_bits_T_123 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_116)
node _io_vcalloc_req_bits_T_124 = or(_io_vcalloc_req_bits_T_123, _io_vcalloc_req_bits_T_117)
node _io_vcalloc_req_bits_T_125 = or(_io_vcalloc_req_bits_T_124, _io_vcalloc_req_bits_T_118)
node _io_vcalloc_req_bits_T_126 = or(_io_vcalloc_req_bits_T_125, _io_vcalloc_req_bits_T_119)
node _io_vcalloc_req_bits_T_127 = or(_io_vcalloc_req_bits_T_126, _io_vcalloc_req_bits_T_120)
wire _io_vcalloc_req_bits_WIRE_10 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_127
connect _io_vcalloc_req_bits_WIRE_2[7], _io_vcalloc_req_bits_WIRE_10
connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2
wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>[8]
node _io_vcalloc_req_bits_T_128 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_129 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_130 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_133 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_134 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_135 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_128, _io_vcalloc_req_bits_T_129)
node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_130)
node _io_vcalloc_req_bits_T_138 = or(_io_vcalloc_req_bits_T_137, _io_vcalloc_req_bits_T_131)
node _io_vcalloc_req_bits_T_139 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_132)
node _io_vcalloc_req_bits_T_140 = or(_io_vcalloc_req_bits_T_139, _io_vcalloc_req_bits_T_133)
node _io_vcalloc_req_bits_T_141 = or(_io_vcalloc_req_bits_T_140, _io_vcalloc_req_bits_T_134)
node _io_vcalloc_req_bits_T_142 = or(_io_vcalloc_req_bits_T_141, _io_vcalloc_req_bits_T_135)
wire _io_vcalloc_req_bits_WIRE_12 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_142
connect _io_vcalloc_req_bits_WIRE_11[0], _io_vcalloc_req_bits_WIRE_12
node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_144 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_145 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_146 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_147 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_148 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_149 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_150 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_151 = or(_io_vcalloc_req_bits_T_143, _io_vcalloc_req_bits_T_144)
node _io_vcalloc_req_bits_T_152 = or(_io_vcalloc_req_bits_T_151, _io_vcalloc_req_bits_T_145)
node _io_vcalloc_req_bits_T_153 = or(_io_vcalloc_req_bits_T_152, _io_vcalloc_req_bits_T_146)
node _io_vcalloc_req_bits_T_154 = or(_io_vcalloc_req_bits_T_153, _io_vcalloc_req_bits_T_147)
node _io_vcalloc_req_bits_T_155 = or(_io_vcalloc_req_bits_T_154, _io_vcalloc_req_bits_T_148)
node _io_vcalloc_req_bits_T_156 = or(_io_vcalloc_req_bits_T_155, _io_vcalloc_req_bits_T_149)
node _io_vcalloc_req_bits_T_157 = or(_io_vcalloc_req_bits_T_156, _io_vcalloc_req_bits_T_150)
wire _io_vcalloc_req_bits_WIRE_13 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_157
connect _io_vcalloc_req_bits_WIRE_11[1], _io_vcalloc_req_bits_WIRE_13
node _io_vcalloc_req_bits_T_158 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_159 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_160 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_161 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_162 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_163 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_164 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_165 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_166 = or(_io_vcalloc_req_bits_T_158, _io_vcalloc_req_bits_T_159)
node _io_vcalloc_req_bits_T_167 = or(_io_vcalloc_req_bits_T_166, _io_vcalloc_req_bits_T_160)
node _io_vcalloc_req_bits_T_168 = or(_io_vcalloc_req_bits_T_167, _io_vcalloc_req_bits_T_161)
node _io_vcalloc_req_bits_T_169 = or(_io_vcalloc_req_bits_T_168, _io_vcalloc_req_bits_T_162)
node _io_vcalloc_req_bits_T_170 = or(_io_vcalloc_req_bits_T_169, _io_vcalloc_req_bits_T_163)
node _io_vcalloc_req_bits_T_171 = or(_io_vcalloc_req_bits_T_170, _io_vcalloc_req_bits_T_164)
node _io_vcalloc_req_bits_T_172 = or(_io_vcalloc_req_bits_T_171, _io_vcalloc_req_bits_T_165)
wire _io_vcalloc_req_bits_WIRE_14 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_172
connect _io_vcalloc_req_bits_WIRE_11[2], _io_vcalloc_req_bits_WIRE_14
node _io_vcalloc_req_bits_T_173 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_174 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_175 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_176 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_177 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_178 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_179 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_180 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_181 = or(_io_vcalloc_req_bits_T_173, _io_vcalloc_req_bits_T_174)
node _io_vcalloc_req_bits_T_182 = or(_io_vcalloc_req_bits_T_181, _io_vcalloc_req_bits_T_175)
node _io_vcalloc_req_bits_T_183 = or(_io_vcalloc_req_bits_T_182, _io_vcalloc_req_bits_T_176)
node _io_vcalloc_req_bits_T_184 = or(_io_vcalloc_req_bits_T_183, _io_vcalloc_req_bits_T_177)
node _io_vcalloc_req_bits_T_185 = or(_io_vcalloc_req_bits_T_184, _io_vcalloc_req_bits_T_178)
node _io_vcalloc_req_bits_T_186 = or(_io_vcalloc_req_bits_T_185, _io_vcalloc_req_bits_T_179)
node _io_vcalloc_req_bits_T_187 = or(_io_vcalloc_req_bits_T_186, _io_vcalloc_req_bits_T_180)
wire _io_vcalloc_req_bits_WIRE_15 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_187
connect _io_vcalloc_req_bits_WIRE_11[3], _io_vcalloc_req_bits_WIRE_15
node _io_vcalloc_req_bits_T_188 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_189 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_190 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_191 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_192 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_193 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_194 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_195 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_196 = or(_io_vcalloc_req_bits_T_188, _io_vcalloc_req_bits_T_189)
node _io_vcalloc_req_bits_T_197 = or(_io_vcalloc_req_bits_T_196, _io_vcalloc_req_bits_T_190)
node _io_vcalloc_req_bits_T_198 = or(_io_vcalloc_req_bits_T_197, _io_vcalloc_req_bits_T_191)
node _io_vcalloc_req_bits_T_199 = or(_io_vcalloc_req_bits_T_198, _io_vcalloc_req_bits_T_192)
node _io_vcalloc_req_bits_T_200 = or(_io_vcalloc_req_bits_T_199, _io_vcalloc_req_bits_T_193)
node _io_vcalloc_req_bits_T_201 = or(_io_vcalloc_req_bits_T_200, _io_vcalloc_req_bits_T_194)
node _io_vcalloc_req_bits_T_202 = or(_io_vcalloc_req_bits_T_201, _io_vcalloc_req_bits_T_195)
wire _io_vcalloc_req_bits_WIRE_16 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_202
connect _io_vcalloc_req_bits_WIRE_11[4], _io_vcalloc_req_bits_WIRE_16
node _io_vcalloc_req_bits_T_203 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_204 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_205 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_206 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_207 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_208 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_209 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_210 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_211 = or(_io_vcalloc_req_bits_T_203, _io_vcalloc_req_bits_T_204)
node _io_vcalloc_req_bits_T_212 = or(_io_vcalloc_req_bits_T_211, _io_vcalloc_req_bits_T_205)
node _io_vcalloc_req_bits_T_213 = or(_io_vcalloc_req_bits_T_212, _io_vcalloc_req_bits_T_206)
node _io_vcalloc_req_bits_T_214 = or(_io_vcalloc_req_bits_T_213, _io_vcalloc_req_bits_T_207)
node _io_vcalloc_req_bits_T_215 = or(_io_vcalloc_req_bits_T_214, _io_vcalloc_req_bits_T_208)
node _io_vcalloc_req_bits_T_216 = or(_io_vcalloc_req_bits_T_215, _io_vcalloc_req_bits_T_209)
node _io_vcalloc_req_bits_T_217 = or(_io_vcalloc_req_bits_T_216, _io_vcalloc_req_bits_T_210)
wire _io_vcalloc_req_bits_WIRE_17 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_217
connect _io_vcalloc_req_bits_WIRE_11[5], _io_vcalloc_req_bits_WIRE_17
node _io_vcalloc_req_bits_T_218 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_219 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_220 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_221 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_222 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_223 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_224 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_225 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_226 = or(_io_vcalloc_req_bits_T_218, _io_vcalloc_req_bits_T_219)
node _io_vcalloc_req_bits_T_227 = or(_io_vcalloc_req_bits_T_226, _io_vcalloc_req_bits_T_220)
node _io_vcalloc_req_bits_T_228 = or(_io_vcalloc_req_bits_T_227, _io_vcalloc_req_bits_T_221)
node _io_vcalloc_req_bits_T_229 = or(_io_vcalloc_req_bits_T_228, _io_vcalloc_req_bits_T_222)
node _io_vcalloc_req_bits_T_230 = or(_io_vcalloc_req_bits_T_229, _io_vcalloc_req_bits_T_223)
node _io_vcalloc_req_bits_T_231 = or(_io_vcalloc_req_bits_T_230, _io_vcalloc_req_bits_T_224)
node _io_vcalloc_req_bits_T_232 = or(_io_vcalloc_req_bits_T_231, _io_vcalloc_req_bits_T_225)
wire _io_vcalloc_req_bits_WIRE_18 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_232
connect _io_vcalloc_req_bits_WIRE_11[6], _io_vcalloc_req_bits_WIRE_18
node _io_vcalloc_req_bits_T_233 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_234 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_235 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_236 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_237 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_238 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_239 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_240 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_241 = or(_io_vcalloc_req_bits_T_233, _io_vcalloc_req_bits_T_234)
node _io_vcalloc_req_bits_T_242 = or(_io_vcalloc_req_bits_T_241, _io_vcalloc_req_bits_T_235)
node _io_vcalloc_req_bits_T_243 = or(_io_vcalloc_req_bits_T_242, _io_vcalloc_req_bits_T_236)
node _io_vcalloc_req_bits_T_244 = or(_io_vcalloc_req_bits_T_243, _io_vcalloc_req_bits_T_237)
node _io_vcalloc_req_bits_T_245 = or(_io_vcalloc_req_bits_T_244, _io_vcalloc_req_bits_T_238)
node _io_vcalloc_req_bits_T_246 = or(_io_vcalloc_req_bits_T_245, _io_vcalloc_req_bits_T_239)
node _io_vcalloc_req_bits_T_247 = or(_io_vcalloc_req_bits_T_246, _io_vcalloc_req_bits_T_240)
wire _io_vcalloc_req_bits_WIRE_19 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_247
connect _io_vcalloc_req_bits_WIRE_11[7], _io_vcalloc_req_bits_WIRE_19
connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_11
wire _io_vcalloc_req_bits_WIRE_20 : UInt<1>[8]
node _io_vcalloc_req_bits_T_248 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_249 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_250 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_251 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_252 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_253 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_254 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_255 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_256 = or(_io_vcalloc_req_bits_T_248, _io_vcalloc_req_bits_T_249)
node _io_vcalloc_req_bits_T_257 = or(_io_vcalloc_req_bits_T_256, _io_vcalloc_req_bits_T_250)
node _io_vcalloc_req_bits_T_258 = or(_io_vcalloc_req_bits_T_257, _io_vcalloc_req_bits_T_251)
node _io_vcalloc_req_bits_T_259 = or(_io_vcalloc_req_bits_T_258, _io_vcalloc_req_bits_T_252)
node _io_vcalloc_req_bits_T_260 = or(_io_vcalloc_req_bits_T_259, _io_vcalloc_req_bits_T_253)
node _io_vcalloc_req_bits_T_261 = or(_io_vcalloc_req_bits_T_260, _io_vcalloc_req_bits_T_254)
node _io_vcalloc_req_bits_T_262 = or(_io_vcalloc_req_bits_T_261, _io_vcalloc_req_bits_T_255)
wire _io_vcalloc_req_bits_WIRE_21 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_262
connect _io_vcalloc_req_bits_WIRE_20[0], _io_vcalloc_req_bits_WIRE_21
node _io_vcalloc_req_bits_T_263 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_264 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_265 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_266 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_267 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_268 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_269 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_270 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_271 = or(_io_vcalloc_req_bits_T_263, _io_vcalloc_req_bits_T_264)
node _io_vcalloc_req_bits_T_272 = or(_io_vcalloc_req_bits_T_271, _io_vcalloc_req_bits_T_265)
node _io_vcalloc_req_bits_T_273 = or(_io_vcalloc_req_bits_T_272, _io_vcalloc_req_bits_T_266)
node _io_vcalloc_req_bits_T_274 = or(_io_vcalloc_req_bits_T_273, _io_vcalloc_req_bits_T_267)
node _io_vcalloc_req_bits_T_275 = or(_io_vcalloc_req_bits_T_274, _io_vcalloc_req_bits_T_268)
node _io_vcalloc_req_bits_T_276 = or(_io_vcalloc_req_bits_T_275, _io_vcalloc_req_bits_T_269)
node _io_vcalloc_req_bits_T_277 = or(_io_vcalloc_req_bits_T_276, _io_vcalloc_req_bits_T_270)
wire _io_vcalloc_req_bits_WIRE_22 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_277
connect _io_vcalloc_req_bits_WIRE_20[1], _io_vcalloc_req_bits_WIRE_22
node _io_vcalloc_req_bits_T_278 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_279 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_280 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_281 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_282 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_283 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_284 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_285 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_286 = or(_io_vcalloc_req_bits_T_278, _io_vcalloc_req_bits_T_279)
node _io_vcalloc_req_bits_T_287 = or(_io_vcalloc_req_bits_T_286, _io_vcalloc_req_bits_T_280)
node _io_vcalloc_req_bits_T_288 = or(_io_vcalloc_req_bits_T_287, _io_vcalloc_req_bits_T_281)
node _io_vcalloc_req_bits_T_289 = or(_io_vcalloc_req_bits_T_288, _io_vcalloc_req_bits_T_282)
node _io_vcalloc_req_bits_T_290 = or(_io_vcalloc_req_bits_T_289, _io_vcalloc_req_bits_T_283)
node _io_vcalloc_req_bits_T_291 = or(_io_vcalloc_req_bits_T_290, _io_vcalloc_req_bits_T_284)
node _io_vcalloc_req_bits_T_292 = or(_io_vcalloc_req_bits_T_291, _io_vcalloc_req_bits_T_285)
wire _io_vcalloc_req_bits_WIRE_23 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_23, _io_vcalloc_req_bits_T_292
connect _io_vcalloc_req_bits_WIRE_20[2], _io_vcalloc_req_bits_WIRE_23
node _io_vcalloc_req_bits_T_293 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_294 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_295 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_296 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_297 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_298 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_299 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_300 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_301 = or(_io_vcalloc_req_bits_T_293, _io_vcalloc_req_bits_T_294)
node _io_vcalloc_req_bits_T_302 = or(_io_vcalloc_req_bits_T_301, _io_vcalloc_req_bits_T_295)
node _io_vcalloc_req_bits_T_303 = or(_io_vcalloc_req_bits_T_302, _io_vcalloc_req_bits_T_296)
node _io_vcalloc_req_bits_T_304 = or(_io_vcalloc_req_bits_T_303, _io_vcalloc_req_bits_T_297)
node _io_vcalloc_req_bits_T_305 = or(_io_vcalloc_req_bits_T_304, _io_vcalloc_req_bits_T_298)
node _io_vcalloc_req_bits_T_306 = or(_io_vcalloc_req_bits_T_305, _io_vcalloc_req_bits_T_299)
node _io_vcalloc_req_bits_T_307 = or(_io_vcalloc_req_bits_T_306, _io_vcalloc_req_bits_T_300)
wire _io_vcalloc_req_bits_WIRE_24 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_24, _io_vcalloc_req_bits_T_307
connect _io_vcalloc_req_bits_WIRE_20[3], _io_vcalloc_req_bits_WIRE_24
node _io_vcalloc_req_bits_T_308 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_309 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_310 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_311 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_312 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_313 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_314 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_315 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_316 = or(_io_vcalloc_req_bits_T_308, _io_vcalloc_req_bits_T_309)
node _io_vcalloc_req_bits_T_317 = or(_io_vcalloc_req_bits_T_316, _io_vcalloc_req_bits_T_310)
node _io_vcalloc_req_bits_T_318 = or(_io_vcalloc_req_bits_T_317, _io_vcalloc_req_bits_T_311)
node _io_vcalloc_req_bits_T_319 = or(_io_vcalloc_req_bits_T_318, _io_vcalloc_req_bits_T_312)
node _io_vcalloc_req_bits_T_320 = or(_io_vcalloc_req_bits_T_319, _io_vcalloc_req_bits_T_313)
node _io_vcalloc_req_bits_T_321 = or(_io_vcalloc_req_bits_T_320, _io_vcalloc_req_bits_T_314)
node _io_vcalloc_req_bits_T_322 = or(_io_vcalloc_req_bits_T_321, _io_vcalloc_req_bits_T_315)
wire _io_vcalloc_req_bits_WIRE_25 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_25, _io_vcalloc_req_bits_T_322
connect _io_vcalloc_req_bits_WIRE_20[4], _io_vcalloc_req_bits_WIRE_25
node _io_vcalloc_req_bits_T_323 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_324 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_325 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_326 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_327 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_328 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_329 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_330 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_331 = or(_io_vcalloc_req_bits_T_323, _io_vcalloc_req_bits_T_324)
node _io_vcalloc_req_bits_T_332 = or(_io_vcalloc_req_bits_T_331, _io_vcalloc_req_bits_T_325)
node _io_vcalloc_req_bits_T_333 = or(_io_vcalloc_req_bits_T_332, _io_vcalloc_req_bits_T_326)
node _io_vcalloc_req_bits_T_334 = or(_io_vcalloc_req_bits_T_333, _io_vcalloc_req_bits_T_327)
node _io_vcalloc_req_bits_T_335 = or(_io_vcalloc_req_bits_T_334, _io_vcalloc_req_bits_T_328)
node _io_vcalloc_req_bits_T_336 = or(_io_vcalloc_req_bits_T_335, _io_vcalloc_req_bits_T_329)
node _io_vcalloc_req_bits_T_337 = or(_io_vcalloc_req_bits_T_336, _io_vcalloc_req_bits_T_330)
wire _io_vcalloc_req_bits_WIRE_26 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_26, _io_vcalloc_req_bits_T_337
connect _io_vcalloc_req_bits_WIRE_20[5], _io_vcalloc_req_bits_WIRE_26
node _io_vcalloc_req_bits_T_338 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_339 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_340 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_341 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_342 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_343 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_344 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_345 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_346 = or(_io_vcalloc_req_bits_T_338, _io_vcalloc_req_bits_T_339)
node _io_vcalloc_req_bits_T_347 = or(_io_vcalloc_req_bits_T_346, _io_vcalloc_req_bits_T_340)
node _io_vcalloc_req_bits_T_348 = or(_io_vcalloc_req_bits_T_347, _io_vcalloc_req_bits_T_341)
node _io_vcalloc_req_bits_T_349 = or(_io_vcalloc_req_bits_T_348, _io_vcalloc_req_bits_T_342)
node _io_vcalloc_req_bits_T_350 = or(_io_vcalloc_req_bits_T_349, _io_vcalloc_req_bits_T_343)
node _io_vcalloc_req_bits_T_351 = or(_io_vcalloc_req_bits_T_350, _io_vcalloc_req_bits_T_344)
node _io_vcalloc_req_bits_T_352 = or(_io_vcalloc_req_bits_T_351, _io_vcalloc_req_bits_T_345)
wire _io_vcalloc_req_bits_WIRE_27 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_27, _io_vcalloc_req_bits_T_352
connect _io_vcalloc_req_bits_WIRE_20[6], _io_vcalloc_req_bits_WIRE_27
node _io_vcalloc_req_bits_T_353 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_354 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_355 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_356 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_357 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_358 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_359 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_360 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_361 = or(_io_vcalloc_req_bits_T_353, _io_vcalloc_req_bits_T_354)
node _io_vcalloc_req_bits_T_362 = or(_io_vcalloc_req_bits_T_361, _io_vcalloc_req_bits_T_355)
node _io_vcalloc_req_bits_T_363 = or(_io_vcalloc_req_bits_T_362, _io_vcalloc_req_bits_T_356)
node _io_vcalloc_req_bits_T_364 = or(_io_vcalloc_req_bits_T_363, _io_vcalloc_req_bits_T_357)
node _io_vcalloc_req_bits_T_365 = or(_io_vcalloc_req_bits_T_364, _io_vcalloc_req_bits_T_358)
node _io_vcalloc_req_bits_T_366 = or(_io_vcalloc_req_bits_T_365, _io_vcalloc_req_bits_T_359)
node _io_vcalloc_req_bits_T_367 = or(_io_vcalloc_req_bits_T_366, _io_vcalloc_req_bits_T_360)
wire _io_vcalloc_req_bits_WIRE_28 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_28, _io_vcalloc_req_bits_T_367
connect _io_vcalloc_req_bits_WIRE_20[7], _io_vcalloc_req_bits_WIRE_28
connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_20
wire _io_vcalloc_req_bits_WIRE_29 : UInt<1>[8]
node _io_vcalloc_req_bits_T_368 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_369 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_370 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_371 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_372 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_373 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_374 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_375 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_376 = or(_io_vcalloc_req_bits_T_368, _io_vcalloc_req_bits_T_369)
node _io_vcalloc_req_bits_T_377 = or(_io_vcalloc_req_bits_T_376, _io_vcalloc_req_bits_T_370)
node _io_vcalloc_req_bits_T_378 = or(_io_vcalloc_req_bits_T_377, _io_vcalloc_req_bits_T_371)
node _io_vcalloc_req_bits_T_379 = or(_io_vcalloc_req_bits_T_378, _io_vcalloc_req_bits_T_372)
node _io_vcalloc_req_bits_T_380 = or(_io_vcalloc_req_bits_T_379, _io_vcalloc_req_bits_T_373)
node _io_vcalloc_req_bits_T_381 = or(_io_vcalloc_req_bits_T_380, _io_vcalloc_req_bits_T_374)
node _io_vcalloc_req_bits_T_382 = or(_io_vcalloc_req_bits_T_381, _io_vcalloc_req_bits_T_375)
wire _io_vcalloc_req_bits_WIRE_30 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_30, _io_vcalloc_req_bits_T_382
connect _io_vcalloc_req_bits_WIRE_29[0], _io_vcalloc_req_bits_WIRE_30
node _io_vcalloc_req_bits_T_383 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_384 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_385 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_386 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_387 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_388 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_389 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_390 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_391 = or(_io_vcalloc_req_bits_T_383, _io_vcalloc_req_bits_T_384)
node _io_vcalloc_req_bits_T_392 = or(_io_vcalloc_req_bits_T_391, _io_vcalloc_req_bits_T_385)
node _io_vcalloc_req_bits_T_393 = or(_io_vcalloc_req_bits_T_392, _io_vcalloc_req_bits_T_386)
node _io_vcalloc_req_bits_T_394 = or(_io_vcalloc_req_bits_T_393, _io_vcalloc_req_bits_T_387)
node _io_vcalloc_req_bits_T_395 = or(_io_vcalloc_req_bits_T_394, _io_vcalloc_req_bits_T_388)
node _io_vcalloc_req_bits_T_396 = or(_io_vcalloc_req_bits_T_395, _io_vcalloc_req_bits_T_389)
node _io_vcalloc_req_bits_T_397 = or(_io_vcalloc_req_bits_T_396, _io_vcalloc_req_bits_T_390)
wire _io_vcalloc_req_bits_WIRE_31 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_31, _io_vcalloc_req_bits_T_397
connect _io_vcalloc_req_bits_WIRE_29[1], _io_vcalloc_req_bits_WIRE_31
node _io_vcalloc_req_bits_T_398 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_399 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_400 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_401 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_402 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_403 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_404 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_405 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_406 = or(_io_vcalloc_req_bits_T_398, _io_vcalloc_req_bits_T_399)
node _io_vcalloc_req_bits_T_407 = or(_io_vcalloc_req_bits_T_406, _io_vcalloc_req_bits_T_400)
node _io_vcalloc_req_bits_T_408 = or(_io_vcalloc_req_bits_T_407, _io_vcalloc_req_bits_T_401)
node _io_vcalloc_req_bits_T_409 = or(_io_vcalloc_req_bits_T_408, _io_vcalloc_req_bits_T_402)
node _io_vcalloc_req_bits_T_410 = or(_io_vcalloc_req_bits_T_409, _io_vcalloc_req_bits_T_403)
node _io_vcalloc_req_bits_T_411 = or(_io_vcalloc_req_bits_T_410, _io_vcalloc_req_bits_T_404)
node _io_vcalloc_req_bits_T_412 = or(_io_vcalloc_req_bits_T_411, _io_vcalloc_req_bits_T_405)
wire _io_vcalloc_req_bits_WIRE_32 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_32, _io_vcalloc_req_bits_T_412
connect _io_vcalloc_req_bits_WIRE_29[2], _io_vcalloc_req_bits_WIRE_32
node _io_vcalloc_req_bits_T_413 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_414 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_415 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_416 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_417 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_418 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_419 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_420 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_421 = or(_io_vcalloc_req_bits_T_413, _io_vcalloc_req_bits_T_414)
node _io_vcalloc_req_bits_T_422 = or(_io_vcalloc_req_bits_T_421, _io_vcalloc_req_bits_T_415)
node _io_vcalloc_req_bits_T_423 = or(_io_vcalloc_req_bits_T_422, _io_vcalloc_req_bits_T_416)
node _io_vcalloc_req_bits_T_424 = or(_io_vcalloc_req_bits_T_423, _io_vcalloc_req_bits_T_417)
node _io_vcalloc_req_bits_T_425 = or(_io_vcalloc_req_bits_T_424, _io_vcalloc_req_bits_T_418)
node _io_vcalloc_req_bits_T_426 = or(_io_vcalloc_req_bits_T_425, _io_vcalloc_req_bits_T_419)
node _io_vcalloc_req_bits_T_427 = or(_io_vcalloc_req_bits_T_426, _io_vcalloc_req_bits_T_420)
wire _io_vcalloc_req_bits_WIRE_33 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_33, _io_vcalloc_req_bits_T_427
connect _io_vcalloc_req_bits_WIRE_29[3], _io_vcalloc_req_bits_WIRE_33
node _io_vcalloc_req_bits_T_428 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_429 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_430 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_431 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_432 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_433 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_434 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_435 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_436 = or(_io_vcalloc_req_bits_T_428, _io_vcalloc_req_bits_T_429)
node _io_vcalloc_req_bits_T_437 = or(_io_vcalloc_req_bits_T_436, _io_vcalloc_req_bits_T_430)
node _io_vcalloc_req_bits_T_438 = or(_io_vcalloc_req_bits_T_437, _io_vcalloc_req_bits_T_431)
node _io_vcalloc_req_bits_T_439 = or(_io_vcalloc_req_bits_T_438, _io_vcalloc_req_bits_T_432)
node _io_vcalloc_req_bits_T_440 = or(_io_vcalloc_req_bits_T_439, _io_vcalloc_req_bits_T_433)
node _io_vcalloc_req_bits_T_441 = or(_io_vcalloc_req_bits_T_440, _io_vcalloc_req_bits_T_434)
node _io_vcalloc_req_bits_T_442 = or(_io_vcalloc_req_bits_T_441, _io_vcalloc_req_bits_T_435)
wire _io_vcalloc_req_bits_WIRE_34 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_34, _io_vcalloc_req_bits_T_442
connect _io_vcalloc_req_bits_WIRE_29[4], _io_vcalloc_req_bits_WIRE_34
node _io_vcalloc_req_bits_T_443 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_444 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_445 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_446 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_447 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_448 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_449 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_450 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_451 = or(_io_vcalloc_req_bits_T_443, _io_vcalloc_req_bits_T_444)
node _io_vcalloc_req_bits_T_452 = or(_io_vcalloc_req_bits_T_451, _io_vcalloc_req_bits_T_445)
node _io_vcalloc_req_bits_T_453 = or(_io_vcalloc_req_bits_T_452, _io_vcalloc_req_bits_T_446)
node _io_vcalloc_req_bits_T_454 = or(_io_vcalloc_req_bits_T_453, _io_vcalloc_req_bits_T_447)
node _io_vcalloc_req_bits_T_455 = or(_io_vcalloc_req_bits_T_454, _io_vcalloc_req_bits_T_448)
node _io_vcalloc_req_bits_T_456 = or(_io_vcalloc_req_bits_T_455, _io_vcalloc_req_bits_T_449)
node _io_vcalloc_req_bits_T_457 = or(_io_vcalloc_req_bits_T_456, _io_vcalloc_req_bits_T_450)
wire _io_vcalloc_req_bits_WIRE_35 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_35, _io_vcalloc_req_bits_T_457
connect _io_vcalloc_req_bits_WIRE_29[5], _io_vcalloc_req_bits_WIRE_35
node _io_vcalloc_req_bits_T_458 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_459 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_460 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_461 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_462 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_463 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_464 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_465 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_466 = or(_io_vcalloc_req_bits_T_458, _io_vcalloc_req_bits_T_459)
node _io_vcalloc_req_bits_T_467 = or(_io_vcalloc_req_bits_T_466, _io_vcalloc_req_bits_T_460)
node _io_vcalloc_req_bits_T_468 = or(_io_vcalloc_req_bits_T_467, _io_vcalloc_req_bits_T_461)
node _io_vcalloc_req_bits_T_469 = or(_io_vcalloc_req_bits_T_468, _io_vcalloc_req_bits_T_462)
node _io_vcalloc_req_bits_T_470 = or(_io_vcalloc_req_bits_T_469, _io_vcalloc_req_bits_T_463)
node _io_vcalloc_req_bits_T_471 = or(_io_vcalloc_req_bits_T_470, _io_vcalloc_req_bits_T_464)
node _io_vcalloc_req_bits_T_472 = or(_io_vcalloc_req_bits_T_471, _io_vcalloc_req_bits_T_465)
wire _io_vcalloc_req_bits_WIRE_36 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_36, _io_vcalloc_req_bits_T_472
connect _io_vcalloc_req_bits_WIRE_29[6], _io_vcalloc_req_bits_WIRE_36
node _io_vcalloc_req_bits_T_473 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_474 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_475 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_476 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_477 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_478 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_479 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_480 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_481 = or(_io_vcalloc_req_bits_T_473, _io_vcalloc_req_bits_T_474)
node _io_vcalloc_req_bits_T_482 = or(_io_vcalloc_req_bits_T_481, _io_vcalloc_req_bits_T_475)
node _io_vcalloc_req_bits_T_483 = or(_io_vcalloc_req_bits_T_482, _io_vcalloc_req_bits_T_476)
node _io_vcalloc_req_bits_T_484 = or(_io_vcalloc_req_bits_T_483, _io_vcalloc_req_bits_T_477)
node _io_vcalloc_req_bits_T_485 = or(_io_vcalloc_req_bits_T_484, _io_vcalloc_req_bits_T_478)
node _io_vcalloc_req_bits_T_486 = or(_io_vcalloc_req_bits_T_485, _io_vcalloc_req_bits_T_479)
node _io_vcalloc_req_bits_T_487 = or(_io_vcalloc_req_bits_T_486, _io_vcalloc_req_bits_T_480)
wire _io_vcalloc_req_bits_WIRE_37 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_37, _io_vcalloc_req_bits_T_487
connect _io_vcalloc_req_bits_WIRE_29[7], _io_vcalloc_req_bits_WIRE_37
connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_29
connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1
node _io_vcalloc_req_bits_T_488 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_489 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_490 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_491 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_492 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_493 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_494 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_495 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_496 = or(_io_vcalloc_req_bits_T_488, _io_vcalloc_req_bits_T_489)
node _io_vcalloc_req_bits_T_497 = or(_io_vcalloc_req_bits_T_496, _io_vcalloc_req_bits_T_490)
node _io_vcalloc_req_bits_T_498 = or(_io_vcalloc_req_bits_T_497, _io_vcalloc_req_bits_T_491)
node _io_vcalloc_req_bits_T_499 = or(_io_vcalloc_req_bits_T_498, _io_vcalloc_req_bits_T_492)
node _io_vcalloc_req_bits_T_500 = or(_io_vcalloc_req_bits_T_499, _io_vcalloc_req_bits_T_493)
node _io_vcalloc_req_bits_T_501 = or(_io_vcalloc_req_bits_T_500, _io_vcalloc_req_bits_T_494)
node _io_vcalloc_req_bits_T_502 = or(_io_vcalloc_req_bits_T_501, _io_vcalloc_req_bits_T_495)
wire _io_vcalloc_req_bits_WIRE_38 : UInt<3>
connect _io_vcalloc_req_bits_WIRE_38, _io_vcalloc_req_bits_T_502
connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_38
wire _io_vcalloc_req_bits_WIRE_39 : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}
node _io_vcalloc_req_bits_T_503 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_504 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_505 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_506 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_507 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_508 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_509 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_510 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_511 = or(_io_vcalloc_req_bits_T_503, _io_vcalloc_req_bits_T_504)
node _io_vcalloc_req_bits_T_512 = or(_io_vcalloc_req_bits_T_511, _io_vcalloc_req_bits_T_505)
node _io_vcalloc_req_bits_T_513 = or(_io_vcalloc_req_bits_T_512, _io_vcalloc_req_bits_T_506)
node _io_vcalloc_req_bits_T_514 = or(_io_vcalloc_req_bits_T_513, _io_vcalloc_req_bits_T_507)
node _io_vcalloc_req_bits_T_515 = or(_io_vcalloc_req_bits_T_514, _io_vcalloc_req_bits_T_508)
node _io_vcalloc_req_bits_T_516 = or(_io_vcalloc_req_bits_T_515, _io_vcalloc_req_bits_T_509)
node _io_vcalloc_req_bits_T_517 = or(_io_vcalloc_req_bits_T_516, _io_vcalloc_req_bits_T_510)
wire _io_vcalloc_req_bits_WIRE_40 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_40, _io_vcalloc_req_bits_T_517
connect _io_vcalloc_req_bits_WIRE_39.egress_node_id, _io_vcalloc_req_bits_WIRE_40
node _io_vcalloc_req_bits_T_518 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_519 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_520 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_521 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_522 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_523 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_524 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_525 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_526 = or(_io_vcalloc_req_bits_T_518, _io_vcalloc_req_bits_T_519)
node _io_vcalloc_req_bits_T_527 = or(_io_vcalloc_req_bits_T_526, _io_vcalloc_req_bits_T_520)
node _io_vcalloc_req_bits_T_528 = or(_io_vcalloc_req_bits_T_527, _io_vcalloc_req_bits_T_521)
node _io_vcalloc_req_bits_T_529 = or(_io_vcalloc_req_bits_T_528, _io_vcalloc_req_bits_T_522)
node _io_vcalloc_req_bits_T_530 = or(_io_vcalloc_req_bits_T_529, _io_vcalloc_req_bits_T_523)
node _io_vcalloc_req_bits_T_531 = or(_io_vcalloc_req_bits_T_530, _io_vcalloc_req_bits_T_524)
node _io_vcalloc_req_bits_T_532 = or(_io_vcalloc_req_bits_T_531, _io_vcalloc_req_bits_T_525)
wire _io_vcalloc_req_bits_WIRE_41 : UInt<5>
connect _io_vcalloc_req_bits_WIRE_41, _io_vcalloc_req_bits_T_532
connect _io_vcalloc_req_bits_WIRE_39.egress_node, _io_vcalloc_req_bits_WIRE_41
node _io_vcalloc_req_bits_T_533 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_534 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_535 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_536 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_537 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_538 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_539 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_540 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_541 = or(_io_vcalloc_req_bits_T_533, _io_vcalloc_req_bits_T_534)
node _io_vcalloc_req_bits_T_542 = or(_io_vcalloc_req_bits_T_541, _io_vcalloc_req_bits_T_535)
node _io_vcalloc_req_bits_T_543 = or(_io_vcalloc_req_bits_T_542, _io_vcalloc_req_bits_T_536)
node _io_vcalloc_req_bits_T_544 = or(_io_vcalloc_req_bits_T_543, _io_vcalloc_req_bits_T_537)
node _io_vcalloc_req_bits_T_545 = or(_io_vcalloc_req_bits_T_544, _io_vcalloc_req_bits_T_538)
node _io_vcalloc_req_bits_T_546 = or(_io_vcalloc_req_bits_T_545, _io_vcalloc_req_bits_T_539)
node _io_vcalloc_req_bits_T_547 = or(_io_vcalloc_req_bits_T_546, _io_vcalloc_req_bits_T_540)
wire _io_vcalloc_req_bits_WIRE_42 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_42, _io_vcalloc_req_bits_T_547
connect _io_vcalloc_req_bits_WIRE_39.ingress_node_id, _io_vcalloc_req_bits_WIRE_42
node _io_vcalloc_req_bits_T_548 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_549 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_550 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_551 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_552 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_553 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_554 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_555 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_556 = or(_io_vcalloc_req_bits_T_548, _io_vcalloc_req_bits_T_549)
node _io_vcalloc_req_bits_T_557 = or(_io_vcalloc_req_bits_T_556, _io_vcalloc_req_bits_T_550)
node _io_vcalloc_req_bits_T_558 = or(_io_vcalloc_req_bits_T_557, _io_vcalloc_req_bits_T_551)
node _io_vcalloc_req_bits_T_559 = or(_io_vcalloc_req_bits_T_558, _io_vcalloc_req_bits_T_552)
node _io_vcalloc_req_bits_T_560 = or(_io_vcalloc_req_bits_T_559, _io_vcalloc_req_bits_T_553)
node _io_vcalloc_req_bits_T_561 = or(_io_vcalloc_req_bits_T_560, _io_vcalloc_req_bits_T_554)
node _io_vcalloc_req_bits_T_562 = or(_io_vcalloc_req_bits_T_561, _io_vcalloc_req_bits_T_555)
wire _io_vcalloc_req_bits_WIRE_43 : UInt<5>
connect _io_vcalloc_req_bits_WIRE_43, _io_vcalloc_req_bits_T_562
connect _io_vcalloc_req_bits_WIRE_39.ingress_node, _io_vcalloc_req_bits_WIRE_43
node _io_vcalloc_req_bits_T_563 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_564 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_565 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_566 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_567 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_568 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_569 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_570 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_571 = or(_io_vcalloc_req_bits_T_563, _io_vcalloc_req_bits_T_564)
node _io_vcalloc_req_bits_T_572 = or(_io_vcalloc_req_bits_T_571, _io_vcalloc_req_bits_T_565)
node _io_vcalloc_req_bits_T_573 = or(_io_vcalloc_req_bits_T_572, _io_vcalloc_req_bits_T_566)
node _io_vcalloc_req_bits_T_574 = or(_io_vcalloc_req_bits_T_573, _io_vcalloc_req_bits_T_567)
node _io_vcalloc_req_bits_T_575 = or(_io_vcalloc_req_bits_T_574, _io_vcalloc_req_bits_T_568)
node _io_vcalloc_req_bits_T_576 = or(_io_vcalloc_req_bits_T_575, _io_vcalloc_req_bits_T_569)
node _io_vcalloc_req_bits_T_577 = or(_io_vcalloc_req_bits_T_576, _io_vcalloc_req_bits_T_570)
wire _io_vcalloc_req_bits_WIRE_44 : UInt<3>
connect _io_vcalloc_req_bits_WIRE_44, _io_vcalloc_req_bits_T_577
connect _io_vcalloc_req_bits_WIRE_39.vnet_id, _io_vcalloc_req_bits_WIRE_44
connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_39
connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE
node _vcalloc_vals_0_T = eq(states[0].g, UInt<3>(0h2))
node _vcalloc_vals_0_T_1 = eq(states[0].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_0_T_2 = and(_vcalloc_vals_0_T, _vcalloc_vals_0_T_1)
connect vcalloc_vals[0], _vcalloc_vals_0_T_2
connect vcalloc_reqs[0].in_vc, UInt<1>(0h0)
connect vcalloc_reqs[0].vc_sel.`0`, states[0].vc_sel.`0`
connect vcalloc_reqs[0].vc_sel.`1`, states[0].vc_sel.`1`
connect vcalloc_reqs[0].vc_sel.`2`, states[0].vc_sel.`2`
connect vcalloc_reqs[0].vc_sel.`3`, states[0].vc_sel.`3`
connect vcalloc_reqs[0].flow, states[0].flow
node _T_38 = bits(vcalloc_sel, 0, 0)
node _T_39 = and(vcalloc_vals[0], _T_38)
node _T_40 = and(_T_39, io.vcalloc_req.ready)
when _T_40 :
connect states[0].g, UInt<3>(0h3)
node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2))
node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1)
connect vcalloc_vals[1], _vcalloc_vals_1_T_2
connect vcalloc_reqs[1].in_vc, UInt<1>(0h1)
connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0`
connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1`
connect vcalloc_reqs[1].vc_sel.`2`, states[1].vc_sel.`2`
connect vcalloc_reqs[1].vc_sel.`3`, states[1].vc_sel.`3`
connect vcalloc_reqs[1].flow, states[1].flow
node _T_41 = bits(vcalloc_sel, 1, 1)
node _T_42 = and(vcalloc_vals[1], _T_41)
node _T_43 = and(_T_42, io.vcalloc_req.ready)
when _T_43 :
connect states[1].g, UInt<3>(0h3)
node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2))
node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1)
connect vcalloc_vals[2], _vcalloc_vals_2_T_2
connect vcalloc_reqs[2].in_vc, UInt<2>(0h2)
connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0`
connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1`
connect vcalloc_reqs[2].vc_sel.`2`, states[2].vc_sel.`2`
connect vcalloc_reqs[2].vc_sel.`3`, states[2].vc_sel.`3`
connect vcalloc_reqs[2].flow, states[2].flow
node _T_44 = bits(vcalloc_sel, 2, 2)
node _T_45 = and(vcalloc_vals[2], _T_44)
node _T_46 = and(_T_45, io.vcalloc_req.ready)
when _T_46 :
connect states[2].g, UInt<3>(0h3)
node _vcalloc_vals_3_T = eq(states[3].g, UInt<3>(0h2))
node _vcalloc_vals_3_T_1 = eq(states[3].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_3_T_2 = and(_vcalloc_vals_3_T, _vcalloc_vals_3_T_1)
connect vcalloc_vals[3], _vcalloc_vals_3_T_2
connect vcalloc_reqs[3].in_vc, UInt<2>(0h3)
connect vcalloc_reqs[3].vc_sel.`0`, states[3].vc_sel.`0`
connect vcalloc_reqs[3].vc_sel.`1`, states[3].vc_sel.`1`
connect vcalloc_reqs[3].vc_sel.`2`, states[3].vc_sel.`2`
connect vcalloc_reqs[3].vc_sel.`3`, states[3].vc_sel.`3`
connect vcalloc_reqs[3].flow, states[3].flow
node _T_47 = bits(vcalloc_sel, 3, 3)
node _T_48 = and(vcalloc_vals[3], _T_47)
node _T_49 = and(_T_48, io.vcalloc_req.ready)
when _T_49 :
connect states[3].g, UInt<3>(0h3)
node _vcalloc_vals_4_T = eq(states[4].g, UInt<3>(0h2))
node _vcalloc_vals_4_T_1 = eq(states[4].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_4_T_2 = and(_vcalloc_vals_4_T, _vcalloc_vals_4_T_1)
connect vcalloc_vals[4], _vcalloc_vals_4_T_2
connect vcalloc_reqs[4].in_vc, UInt<3>(0h4)
connect vcalloc_reqs[4].vc_sel.`0`, states[4].vc_sel.`0`
connect vcalloc_reqs[4].vc_sel.`1`, states[4].vc_sel.`1`
connect vcalloc_reqs[4].vc_sel.`2`, states[4].vc_sel.`2`
connect vcalloc_reqs[4].vc_sel.`3`, states[4].vc_sel.`3`
connect vcalloc_reqs[4].flow, states[4].flow
node _T_50 = bits(vcalloc_sel, 4, 4)
node _T_51 = and(vcalloc_vals[4], _T_50)
node _T_52 = and(_T_51, io.vcalloc_req.ready)
when _T_52 :
connect states[4].g, UInt<3>(0h3)
node _vcalloc_vals_5_T = eq(states[5].g, UInt<3>(0h2))
node _vcalloc_vals_5_T_1 = eq(states[5].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_5_T_2 = and(_vcalloc_vals_5_T, _vcalloc_vals_5_T_1)
connect vcalloc_vals[5], _vcalloc_vals_5_T_2
connect vcalloc_reqs[5].in_vc, UInt<3>(0h5)
connect vcalloc_reqs[5].vc_sel.`0`, states[5].vc_sel.`0`
connect vcalloc_reqs[5].vc_sel.`1`, states[5].vc_sel.`1`
connect vcalloc_reqs[5].vc_sel.`2`, states[5].vc_sel.`2`
connect vcalloc_reqs[5].vc_sel.`3`, states[5].vc_sel.`3`
connect vcalloc_reqs[5].flow, states[5].flow
node _T_53 = bits(vcalloc_sel, 5, 5)
node _T_54 = and(vcalloc_vals[5], _T_53)
node _T_55 = and(_T_54, io.vcalloc_req.ready)
when _T_55 :
connect states[5].g, UInt<3>(0h3)
node _vcalloc_vals_6_T = eq(states[6].g, UInt<3>(0h2))
node _vcalloc_vals_6_T_1 = eq(states[6].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_6_T_2 = and(_vcalloc_vals_6_T, _vcalloc_vals_6_T_1)
connect vcalloc_vals[6], _vcalloc_vals_6_T_2
connect vcalloc_reqs[6].in_vc, UInt<3>(0h6)
connect vcalloc_reqs[6].vc_sel.`0`, states[6].vc_sel.`0`
connect vcalloc_reqs[6].vc_sel.`1`, states[6].vc_sel.`1`
connect vcalloc_reqs[6].vc_sel.`2`, states[6].vc_sel.`2`
connect vcalloc_reqs[6].vc_sel.`3`, states[6].vc_sel.`3`
connect vcalloc_reqs[6].flow, states[6].flow
node _T_56 = bits(vcalloc_sel, 6, 6)
node _T_57 = and(vcalloc_vals[6], _T_56)
node _T_58 = and(_T_57, io.vcalloc_req.ready)
when _T_58 :
connect states[6].g, UInt<3>(0h3)
node _vcalloc_vals_7_T = eq(states[7].g, UInt<3>(0h2))
node _vcalloc_vals_7_T_1 = eq(states[7].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_7_T_2 = and(_vcalloc_vals_7_T, _vcalloc_vals_7_T_1)
connect vcalloc_vals[7], _vcalloc_vals_7_T_2
connect vcalloc_reqs[7].in_vc, UInt<3>(0h7)
connect vcalloc_reqs[7].vc_sel.`0`, states[7].vc_sel.`0`
connect vcalloc_reqs[7].vc_sel.`1`, states[7].vc_sel.`1`
connect vcalloc_reqs[7].vc_sel.`2`, states[7].vc_sel.`2`
connect vcalloc_reqs[7].vc_sel.`3`, states[7].vc_sel.`3`
connect vcalloc_reqs[7].flow, states[7].flow
node _T_59 = bits(vcalloc_sel, 7, 7)
node _T_60 = and(vcalloc_vals[7], _T_59)
node _T_61 = and(_T_60, io.vcalloc_req.ready)
when _T_61 :
connect states[7].g, UInt<3>(0h3)
node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1])
node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0)
node _io_debug_va_stall_T_2 = add(vcalloc_vals[2], vcalloc_vals[3])
node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0)
node _io_debug_va_stall_T_4 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_3)
node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 2, 0)
node _io_debug_va_stall_T_6 = add(vcalloc_vals[4], vcalloc_vals[5])
node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 1, 0)
node _io_debug_va_stall_T_8 = add(vcalloc_vals[6], vcalloc_vals[7])
node _io_debug_va_stall_T_9 = bits(_io_debug_va_stall_T_8, 1, 0)
node _io_debug_va_stall_T_10 = add(_io_debug_va_stall_T_7, _io_debug_va_stall_T_9)
node _io_debug_va_stall_T_11 = bits(_io_debug_va_stall_T_10, 2, 0)
node _io_debug_va_stall_T_12 = add(_io_debug_va_stall_T_5, _io_debug_va_stall_T_11)
node _io_debug_va_stall_T_13 = bits(_io_debug_va_stall_T_12, 3, 0)
node _io_debug_va_stall_T_14 = sub(_io_debug_va_stall_T_13, io.vcalloc_req.ready)
node _io_debug_va_stall_T_15 = tail(_io_debug_va_stall_T_14, 1)
connect io.debug.va_stall, _io_debug_va_stall_T_15
node _T_62 = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
when _T_62 :
node _T_63 = bits(vcalloc_sel, 0, 0)
when _T_63 :
connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[0].g, UInt<3>(0h3)
node _T_64 = eq(states[0].g, UInt<3>(0h2))
node _T_65 = asUInt(reset)
node _T_66 = eq(_T_65, UInt<1>(0h0))
when _T_66 :
node _T_67 = eq(_T_64, UInt<1>(0h0))
when _T_67 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3
assert(clock, _T_64, UInt<1>(0h1), "") : assert_3
node _T_68 = bits(vcalloc_sel, 1, 1)
when _T_68 :
connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[1].g, UInt<3>(0h3)
node _T_69 = eq(states[1].g, UInt<3>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4
assert(clock, _T_69, UInt<1>(0h1), "") : assert_4
node _T_73 = bits(vcalloc_sel, 2, 2)
when _T_73 :
connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[2].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[2].g, UInt<3>(0h3)
node _T_74 = eq(states[2].g, UInt<3>(0h2))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5
assert(clock, _T_74, UInt<1>(0h1), "") : assert_5
node _T_78 = bits(vcalloc_sel, 3, 3)
when _T_78 :
connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[3].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[3].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[3].g, UInt<3>(0h3)
node _T_79 = eq(states[3].g, UInt<3>(0h2))
node _T_80 = asUInt(reset)
node _T_81 = eq(_T_80, UInt<1>(0h0))
when _T_81 :
node _T_82 = eq(_T_79, UInt<1>(0h0))
when _T_82 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6
assert(clock, _T_79, UInt<1>(0h1), "") : assert_6
node _T_83 = bits(vcalloc_sel, 4, 4)
when _T_83 :
connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[4].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[4].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[4].g, UInt<3>(0h3)
node _T_84 = eq(states[4].g, UInt<3>(0h2))
node _T_85 = asUInt(reset)
node _T_86 = eq(_T_85, UInt<1>(0h0))
when _T_86 :
node _T_87 = eq(_T_84, UInt<1>(0h0))
when _T_87 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7
assert(clock, _T_84, UInt<1>(0h1), "") : assert_7
node _T_88 = bits(vcalloc_sel, 5, 5)
when _T_88 :
connect states[5].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[5].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[5].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[5].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[5].g, UInt<3>(0h3)
node _T_89 = eq(states[5].g, UInt<3>(0h2))
node _T_90 = asUInt(reset)
node _T_91 = eq(_T_90, UInt<1>(0h0))
when _T_91 :
node _T_92 = eq(_T_89, UInt<1>(0h0))
when _T_92 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_8
assert(clock, _T_89, UInt<1>(0h1), "") : assert_8
node _T_93 = bits(vcalloc_sel, 6, 6)
when _T_93 :
connect states[6].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[6].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[6].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[6].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[6].g, UInt<3>(0h3)
node _T_94 = eq(states[6].g, UInt<3>(0h2))
node _T_95 = asUInt(reset)
node _T_96 = eq(_T_95, UInt<1>(0h0))
when _T_96 :
node _T_97 = eq(_T_94, UInt<1>(0h0))
when _T_97 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_9
assert(clock, _T_94, UInt<1>(0h1), "") : assert_9
node _T_98 = bits(vcalloc_sel, 7, 7)
when _T_98 :
connect states[7].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[7].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[7].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[7].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[7].g, UInt<3>(0h3)
node _T_99 = eq(states[7].g, UInt<3>(0h2))
node _T_100 = asUInt(reset)
node _T_101 = eq(_T_100, UInt<1>(0h0))
when _T_101 :
node _T_102 = eq(_T_99, UInt<1>(0h0))
when _T_102 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_10
assert(clock, _T_99, UInt<1>(0h1), "") : assert_10
inst salloc_arb of SwitchArbiter_151
connect salloc_arb.clock, clock
connect salloc_arb.reset, reset
node credit_available_lo_lo = cat(states[0].vc_sel.`0`[1], states[0].vc_sel.`0`[0])
node credit_available_lo_hi = cat(states[0].vc_sel.`0`[3], states[0].vc_sel.`0`[2])
node credit_available_lo = cat(credit_available_lo_hi, credit_available_lo_lo)
node credit_available_hi_lo = cat(states[0].vc_sel.`0`[5], states[0].vc_sel.`0`[4])
node credit_available_hi_hi = cat(states[0].vc_sel.`0`[7], states[0].vc_sel.`0`[6])
node credit_available_hi = cat(credit_available_hi_hi, credit_available_hi_lo)
node _credit_available_T = cat(credit_available_hi, credit_available_lo)
node credit_available_lo_lo_1 = cat(states[0].vc_sel.`1`[1], states[0].vc_sel.`1`[0])
node credit_available_lo_hi_1 = cat(states[0].vc_sel.`1`[3], states[0].vc_sel.`1`[2])
node credit_available_lo_1 = cat(credit_available_lo_hi_1, credit_available_lo_lo_1)
node credit_available_hi_lo_1 = cat(states[0].vc_sel.`1`[5], states[0].vc_sel.`1`[4])
node credit_available_hi_hi_1 = cat(states[0].vc_sel.`1`[7], states[0].vc_sel.`1`[6])
node credit_available_hi_1 = cat(credit_available_hi_hi_1, credit_available_hi_lo_1)
node _credit_available_T_1 = cat(credit_available_hi_1, credit_available_lo_1)
node credit_available_lo_lo_2 = cat(states[0].vc_sel.`2`[1], states[0].vc_sel.`2`[0])
node credit_available_lo_hi_2 = cat(states[0].vc_sel.`2`[3], states[0].vc_sel.`2`[2])
node credit_available_lo_2 = cat(credit_available_lo_hi_2, credit_available_lo_lo_2)
node credit_available_hi_lo_2 = cat(states[0].vc_sel.`2`[5], states[0].vc_sel.`2`[4])
node credit_available_hi_hi_2 = cat(states[0].vc_sel.`2`[7], states[0].vc_sel.`2`[6])
node credit_available_hi_2 = cat(credit_available_hi_hi_2, credit_available_hi_lo_2)
node _credit_available_T_2 = cat(credit_available_hi_2, credit_available_lo_2)
node credit_available_lo_lo_3 = cat(states[0].vc_sel.`3`[1], states[0].vc_sel.`3`[0])
node credit_available_lo_hi_3 = cat(states[0].vc_sel.`3`[3], states[0].vc_sel.`3`[2])
node credit_available_lo_3 = cat(credit_available_lo_hi_3, credit_available_lo_lo_3)
node credit_available_hi_lo_3 = cat(states[0].vc_sel.`3`[5], states[0].vc_sel.`3`[4])
node credit_available_hi_hi_3 = cat(states[0].vc_sel.`3`[7], states[0].vc_sel.`3`[6])
node credit_available_hi_3 = cat(credit_available_hi_hi_3, credit_available_hi_lo_3)
node _credit_available_T_3 = cat(credit_available_hi_3, credit_available_lo_3)
node credit_available_lo_4 = cat(_credit_available_T_1, _credit_available_T)
node credit_available_hi_4 = cat(_credit_available_T_3, _credit_available_T_2)
node _credit_available_T_4 = cat(credit_available_hi_4, credit_available_lo_4)
node credit_available_lo_lo_4 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_4 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_5 = cat(credit_available_lo_hi_4, credit_available_lo_lo_4)
node credit_available_hi_lo_4 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_4 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_5 = cat(credit_available_hi_hi_4, credit_available_hi_lo_4)
node _credit_available_T_5 = cat(credit_available_hi_5, credit_available_lo_5)
node credit_available_lo_lo_5 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_5 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_6 = cat(credit_available_lo_hi_5, credit_available_lo_lo_5)
node credit_available_hi_lo_5 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_5 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_6 = cat(credit_available_hi_hi_5, credit_available_hi_lo_5)
node _credit_available_T_6 = cat(credit_available_hi_6, credit_available_lo_6)
node credit_available_lo_lo_6 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_6 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_7 = cat(credit_available_lo_hi_6, credit_available_lo_lo_6)
node credit_available_hi_lo_6 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_6 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_7 = cat(credit_available_hi_hi_6, credit_available_hi_lo_6)
node _credit_available_T_7 = cat(credit_available_hi_7, credit_available_lo_7)
node credit_available_lo_lo_7 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_7 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_8 = cat(credit_available_lo_hi_7, credit_available_lo_lo_7)
node credit_available_hi_lo_7 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_7 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_8 = cat(credit_available_hi_hi_7, credit_available_hi_lo_7)
node _credit_available_T_8 = cat(credit_available_hi_8, credit_available_lo_8)
node credit_available_lo_9 = cat(_credit_available_T_6, _credit_available_T_5)
node credit_available_hi_9 = cat(_credit_available_T_8, _credit_available_T_7)
node _credit_available_T_9 = cat(credit_available_hi_9, credit_available_lo_9)
node _credit_available_T_10 = and(_credit_available_T_4, _credit_available_T_9)
node credit_available = neq(_credit_available_T_10, UInt<1>(0h0))
node _salloc_arb_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h3))
node _salloc_arb_io_in_0_valid_T_1 = and(_salloc_arb_io_in_0_valid_T, credit_available)
node _salloc_arb_io_in_0_valid_T_2 = and(_salloc_arb_io_in_0_valid_T_1, input_buffer.io.deq[0].valid)
connect salloc_arb.io.in[0].valid, _salloc_arb_io_in_0_valid_T_2
connect salloc_arb.io.in[0].bits.vc_sel.`0`[0], states[0].vc_sel.`0`[0]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[1], states[0].vc_sel.`0`[1]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[2], states[0].vc_sel.`0`[2]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[3], states[0].vc_sel.`0`[3]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[4], states[0].vc_sel.`0`[4]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[5], states[0].vc_sel.`0`[5]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[6], states[0].vc_sel.`0`[6]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[7], states[0].vc_sel.`0`[7]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[0], states[0].vc_sel.`1`[0]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[1], states[0].vc_sel.`1`[1]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[2], states[0].vc_sel.`1`[2]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[3], states[0].vc_sel.`1`[3]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[4], states[0].vc_sel.`1`[4]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[5], states[0].vc_sel.`1`[5]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[6], states[0].vc_sel.`1`[6]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[7], states[0].vc_sel.`1`[7]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[0], states[0].vc_sel.`2`[0]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[1], states[0].vc_sel.`2`[1]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[2], states[0].vc_sel.`2`[2]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[3], states[0].vc_sel.`2`[3]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[4], states[0].vc_sel.`2`[4]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[5], states[0].vc_sel.`2`[5]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[6], states[0].vc_sel.`2`[6]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[7], states[0].vc_sel.`2`[7]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[0], states[0].vc_sel.`3`[0]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[1], states[0].vc_sel.`3`[1]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[2], states[0].vc_sel.`3`[2]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[3], states[0].vc_sel.`3`[3]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[4], states[0].vc_sel.`3`[4]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[5], states[0].vc_sel.`3`[5]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[6], states[0].vc_sel.`3`[6]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[7], states[0].vc_sel.`3`[7]
connect salloc_arb.io.in[0].bits.tail, input_buffer.io.deq[0].bits.tail
node _T_103 = and(salloc_arb.io.in[0].ready, salloc_arb.io.in[0].valid)
node _T_104 = and(_T_103, input_buffer.io.deq[0].bits.tail)
when _T_104 :
connect states[0].g, UInt<3>(0h0)
connect input_buffer.io.deq[0].ready, salloc_arb.io.in[0].ready
node credit_available_lo_lo_8 = cat(states[1].vc_sel.`0`[1], states[1].vc_sel.`0`[0])
node credit_available_lo_hi_8 = cat(states[1].vc_sel.`0`[3], states[1].vc_sel.`0`[2])
node credit_available_lo_10 = cat(credit_available_lo_hi_8, credit_available_lo_lo_8)
node credit_available_hi_lo_8 = cat(states[1].vc_sel.`0`[5], states[1].vc_sel.`0`[4])
node credit_available_hi_hi_8 = cat(states[1].vc_sel.`0`[7], states[1].vc_sel.`0`[6])
node credit_available_hi_10 = cat(credit_available_hi_hi_8, credit_available_hi_lo_8)
node _credit_available_T_11 = cat(credit_available_hi_10, credit_available_lo_10)
node credit_available_lo_lo_9 = cat(states[1].vc_sel.`1`[1], states[1].vc_sel.`1`[0])
node credit_available_lo_hi_9 = cat(states[1].vc_sel.`1`[3], states[1].vc_sel.`1`[2])
node credit_available_lo_11 = cat(credit_available_lo_hi_9, credit_available_lo_lo_9)
node credit_available_hi_lo_9 = cat(states[1].vc_sel.`1`[5], states[1].vc_sel.`1`[4])
node credit_available_hi_hi_9 = cat(states[1].vc_sel.`1`[7], states[1].vc_sel.`1`[6])
node credit_available_hi_11 = cat(credit_available_hi_hi_9, credit_available_hi_lo_9)
node _credit_available_T_12 = cat(credit_available_hi_11, credit_available_lo_11)
node credit_available_lo_lo_10 = cat(states[1].vc_sel.`2`[1], states[1].vc_sel.`2`[0])
node credit_available_lo_hi_10 = cat(states[1].vc_sel.`2`[3], states[1].vc_sel.`2`[2])
node credit_available_lo_12 = cat(credit_available_lo_hi_10, credit_available_lo_lo_10)
node credit_available_hi_lo_10 = cat(states[1].vc_sel.`2`[5], states[1].vc_sel.`2`[4])
node credit_available_hi_hi_10 = cat(states[1].vc_sel.`2`[7], states[1].vc_sel.`2`[6])
node credit_available_hi_12 = cat(credit_available_hi_hi_10, credit_available_hi_lo_10)
node _credit_available_T_13 = cat(credit_available_hi_12, credit_available_lo_12)
node credit_available_lo_lo_11 = cat(states[1].vc_sel.`3`[1], states[1].vc_sel.`3`[0])
node credit_available_lo_hi_11 = cat(states[1].vc_sel.`3`[3], states[1].vc_sel.`3`[2])
node credit_available_lo_13 = cat(credit_available_lo_hi_11, credit_available_lo_lo_11)
node credit_available_hi_lo_11 = cat(states[1].vc_sel.`3`[5], states[1].vc_sel.`3`[4])
node credit_available_hi_hi_11 = cat(states[1].vc_sel.`3`[7], states[1].vc_sel.`3`[6])
node credit_available_hi_13 = cat(credit_available_hi_hi_11, credit_available_hi_lo_11)
node _credit_available_T_14 = cat(credit_available_hi_13, credit_available_lo_13)
node credit_available_lo_14 = cat(_credit_available_T_12, _credit_available_T_11)
node credit_available_hi_14 = cat(_credit_available_T_14, _credit_available_T_13)
node _credit_available_T_15 = cat(credit_available_hi_14, credit_available_lo_14)
node credit_available_lo_lo_12 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_12 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_15 = cat(credit_available_lo_hi_12, credit_available_lo_lo_12)
node credit_available_hi_lo_12 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_12 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_15 = cat(credit_available_hi_hi_12, credit_available_hi_lo_12)
node _credit_available_T_16 = cat(credit_available_hi_15, credit_available_lo_15)
node credit_available_lo_lo_13 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_13 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_16 = cat(credit_available_lo_hi_13, credit_available_lo_lo_13)
node credit_available_hi_lo_13 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_13 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_16 = cat(credit_available_hi_hi_13, credit_available_hi_lo_13)
node _credit_available_T_17 = cat(credit_available_hi_16, credit_available_lo_16)
node credit_available_lo_lo_14 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_14 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_17 = cat(credit_available_lo_hi_14, credit_available_lo_lo_14)
node credit_available_hi_lo_14 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_14 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_17 = cat(credit_available_hi_hi_14, credit_available_hi_lo_14)
node _credit_available_T_18 = cat(credit_available_hi_17, credit_available_lo_17)
node credit_available_lo_lo_15 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_15 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_18 = cat(credit_available_lo_hi_15, credit_available_lo_lo_15)
node credit_available_hi_lo_15 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_15 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_18 = cat(credit_available_hi_hi_15, credit_available_hi_lo_15)
node _credit_available_T_19 = cat(credit_available_hi_18, credit_available_lo_18)
node credit_available_lo_19 = cat(_credit_available_T_17, _credit_available_T_16)
node credit_available_hi_19 = cat(_credit_available_T_19, _credit_available_T_18)
node _credit_available_T_20 = cat(credit_available_hi_19, credit_available_lo_19)
node _credit_available_T_21 = and(_credit_available_T_15, _credit_available_T_20)
node credit_available_1 = neq(_credit_available_T_21, UInt<1>(0h0))
node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3))
node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available_1)
node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid)
connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2
connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[2], states[1].vc_sel.`0`[2]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[3], states[1].vc_sel.`0`[3]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[4], states[1].vc_sel.`0`[4]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[5], states[1].vc_sel.`0`[5]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[6], states[1].vc_sel.`0`[6]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[7], states[1].vc_sel.`0`[7]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[1], states[1].vc_sel.`1`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[2], states[1].vc_sel.`1`[2]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[3], states[1].vc_sel.`1`[3]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[4], states[1].vc_sel.`1`[4]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[5], states[1].vc_sel.`1`[5]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[6], states[1].vc_sel.`1`[6]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[7], states[1].vc_sel.`1`[7]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[0], states[1].vc_sel.`2`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[1], states[1].vc_sel.`2`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[2], states[1].vc_sel.`2`[2]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[3], states[1].vc_sel.`2`[3]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[4], states[1].vc_sel.`2`[4]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[5], states[1].vc_sel.`2`[5]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[6], states[1].vc_sel.`2`[6]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[7], states[1].vc_sel.`2`[7]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[0], states[1].vc_sel.`3`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[1], states[1].vc_sel.`3`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[2], states[1].vc_sel.`3`[2]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[3], states[1].vc_sel.`3`[3]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[4], states[1].vc_sel.`3`[4]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[5], states[1].vc_sel.`3`[5]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[6], states[1].vc_sel.`3`[6]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[7], states[1].vc_sel.`3`[7]
connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail
node _T_105 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid)
node _T_106 = and(_T_105, input_buffer.io.deq[1].bits.tail)
when _T_106 :
connect states[1].g, UInt<3>(0h0)
connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready
node credit_available_lo_lo_16 = cat(states[2].vc_sel.`0`[1], states[2].vc_sel.`0`[0])
node credit_available_lo_hi_16 = cat(states[2].vc_sel.`0`[3], states[2].vc_sel.`0`[2])
node credit_available_lo_20 = cat(credit_available_lo_hi_16, credit_available_lo_lo_16)
node credit_available_hi_lo_16 = cat(states[2].vc_sel.`0`[5], states[2].vc_sel.`0`[4])
node credit_available_hi_hi_16 = cat(states[2].vc_sel.`0`[7], states[2].vc_sel.`0`[6])
node credit_available_hi_20 = cat(credit_available_hi_hi_16, credit_available_hi_lo_16)
node _credit_available_T_22 = cat(credit_available_hi_20, credit_available_lo_20)
node credit_available_lo_lo_17 = cat(states[2].vc_sel.`1`[1], states[2].vc_sel.`1`[0])
node credit_available_lo_hi_17 = cat(states[2].vc_sel.`1`[3], states[2].vc_sel.`1`[2])
node credit_available_lo_21 = cat(credit_available_lo_hi_17, credit_available_lo_lo_17)
node credit_available_hi_lo_17 = cat(states[2].vc_sel.`1`[5], states[2].vc_sel.`1`[4])
node credit_available_hi_hi_17 = cat(states[2].vc_sel.`1`[7], states[2].vc_sel.`1`[6])
node credit_available_hi_21 = cat(credit_available_hi_hi_17, credit_available_hi_lo_17)
node _credit_available_T_23 = cat(credit_available_hi_21, credit_available_lo_21)
node credit_available_lo_lo_18 = cat(states[2].vc_sel.`2`[1], states[2].vc_sel.`2`[0])
node credit_available_lo_hi_18 = cat(states[2].vc_sel.`2`[3], states[2].vc_sel.`2`[2])
node credit_available_lo_22 = cat(credit_available_lo_hi_18, credit_available_lo_lo_18)
node credit_available_hi_lo_18 = cat(states[2].vc_sel.`2`[5], states[2].vc_sel.`2`[4])
node credit_available_hi_hi_18 = cat(states[2].vc_sel.`2`[7], states[2].vc_sel.`2`[6])
node credit_available_hi_22 = cat(credit_available_hi_hi_18, credit_available_hi_lo_18)
node _credit_available_T_24 = cat(credit_available_hi_22, credit_available_lo_22)
node credit_available_lo_lo_19 = cat(states[2].vc_sel.`3`[1], states[2].vc_sel.`3`[0])
node credit_available_lo_hi_19 = cat(states[2].vc_sel.`3`[3], states[2].vc_sel.`3`[2])
node credit_available_lo_23 = cat(credit_available_lo_hi_19, credit_available_lo_lo_19)
node credit_available_hi_lo_19 = cat(states[2].vc_sel.`3`[5], states[2].vc_sel.`3`[4])
node credit_available_hi_hi_19 = cat(states[2].vc_sel.`3`[7], states[2].vc_sel.`3`[6])
node credit_available_hi_23 = cat(credit_available_hi_hi_19, credit_available_hi_lo_19)
node _credit_available_T_25 = cat(credit_available_hi_23, credit_available_lo_23)
node credit_available_lo_24 = cat(_credit_available_T_23, _credit_available_T_22)
node credit_available_hi_24 = cat(_credit_available_T_25, _credit_available_T_24)
node _credit_available_T_26 = cat(credit_available_hi_24, credit_available_lo_24)
node credit_available_lo_lo_20 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_20 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_25 = cat(credit_available_lo_hi_20, credit_available_lo_lo_20)
node credit_available_hi_lo_20 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_20 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_25 = cat(credit_available_hi_hi_20, credit_available_hi_lo_20)
node _credit_available_T_27 = cat(credit_available_hi_25, credit_available_lo_25)
node credit_available_lo_lo_21 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_21 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_26 = cat(credit_available_lo_hi_21, credit_available_lo_lo_21)
node credit_available_hi_lo_21 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_21 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_26 = cat(credit_available_hi_hi_21, credit_available_hi_lo_21)
node _credit_available_T_28 = cat(credit_available_hi_26, credit_available_lo_26)
node credit_available_lo_lo_22 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_22 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_27 = cat(credit_available_lo_hi_22, credit_available_lo_lo_22)
node credit_available_hi_lo_22 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_22 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_27 = cat(credit_available_hi_hi_22, credit_available_hi_lo_22)
node _credit_available_T_29 = cat(credit_available_hi_27, credit_available_lo_27)
node credit_available_lo_lo_23 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_23 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_28 = cat(credit_available_lo_hi_23, credit_available_lo_lo_23)
node credit_available_hi_lo_23 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_23 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_28 = cat(credit_available_hi_hi_23, credit_available_hi_lo_23)
node _credit_available_T_30 = cat(credit_available_hi_28, credit_available_lo_28)
node credit_available_lo_29 = cat(_credit_available_T_28, _credit_available_T_27)
node credit_available_hi_29 = cat(_credit_available_T_30, _credit_available_T_29)
node _credit_available_T_31 = cat(credit_available_hi_29, credit_available_lo_29)
node _credit_available_T_32 = and(_credit_available_T_26, _credit_available_T_31)
node credit_available_2 = neq(_credit_available_T_32, UInt<1>(0h0))
node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3))
node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available_2)
node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid)
connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2
connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[3], states[2].vc_sel.`0`[3]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[4], states[2].vc_sel.`0`[4]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[5], states[2].vc_sel.`0`[5]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[6], states[2].vc_sel.`0`[6]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[7], states[2].vc_sel.`0`[7]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[1], states[2].vc_sel.`1`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[2], states[2].vc_sel.`1`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[3], states[2].vc_sel.`1`[3]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[4], states[2].vc_sel.`1`[4]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[5], states[2].vc_sel.`1`[5]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[6], states[2].vc_sel.`1`[6]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[7], states[2].vc_sel.`1`[7]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[0], states[2].vc_sel.`2`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[1], states[2].vc_sel.`2`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[2], states[2].vc_sel.`2`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[3], states[2].vc_sel.`2`[3]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[4], states[2].vc_sel.`2`[4]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[5], states[2].vc_sel.`2`[5]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[6], states[2].vc_sel.`2`[6]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[7], states[2].vc_sel.`2`[7]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[0], states[2].vc_sel.`3`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[1], states[2].vc_sel.`3`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[2], states[2].vc_sel.`3`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[3], states[2].vc_sel.`3`[3]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[4], states[2].vc_sel.`3`[4]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[5], states[2].vc_sel.`3`[5]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[6], states[2].vc_sel.`3`[6]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[7], states[2].vc_sel.`3`[7]
connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail
node _T_107 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid)
node _T_108 = and(_T_107, input_buffer.io.deq[2].bits.tail)
when _T_108 :
connect states[2].g, UInt<3>(0h0)
connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready
node credit_available_lo_lo_24 = cat(states[3].vc_sel.`0`[1], states[3].vc_sel.`0`[0])
node credit_available_lo_hi_24 = cat(states[3].vc_sel.`0`[3], states[3].vc_sel.`0`[2])
node credit_available_lo_30 = cat(credit_available_lo_hi_24, credit_available_lo_lo_24)
node credit_available_hi_lo_24 = cat(states[3].vc_sel.`0`[5], states[3].vc_sel.`0`[4])
node credit_available_hi_hi_24 = cat(states[3].vc_sel.`0`[7], states[3].vc_sel.`0`[6])
node credit_available_hi_30 = cat(credit_available_hi_hi_24, credit_available_hi_lo_24)
node _credit_available_T_33 = cat(credit_available_hi_30, credit_available_lo_30)
node credit_available_lo_lo_25 = cat(states[3].vc_sel.`1`[1], states[3].vc_sel.`1`[0])
node credit_available_lo_hi_25 = cat(states[3].vc_sel.`1`[3], states[3].vc_sel.`1`[2])
node credit_available_lo_31 = cat(credit_available_lo_hi_25, credit_available_lo_lo_25)
node credit_available_hi_lo_25 = cat(states[3].vc_sel.`1`[5], states[3].vc_sel.`1`[4])
node credit_available_hi_hi_25 = cat(states[3].vc_sel.`1`[7], states[3].vc_sel.`1`[6])
node credit_available_hi_31 = cat(credit_available_hi_hi_25, credit_available_hi_lo_25)
node _credit_available_T_34 = cat(credit_available_hi_31, credit_available_lo_31)
node credit_available_lo_lo_26 = cat(states[3].vc_sel.`2`[1], states[3].vc_sel.`2`[0])
node credit_available_lo_hi_26 = cat(states[3].vc_sel.`2`[3], states[3].vc_sel.`2`[2])
node credit_available_lo_32 = cat(credit_available_lo_hi_26, credit_available_lo_lo_26)
node credit_available_hi_lo_26 = cat(states[3].vc_sel.`2`[5], states[3].vc_sel.`2`[4])
node credit_available_hi_hi_26 = cat(states[3].vc_sel.`2`[7], states[3].vc_sel.`2`[6])
node credit_available_hi_32 = cat(credit_available_hi_hi_26, credit_available_hi_lo_26)
node _credit_available_T_35 = cat(credit_available_hi_32, credit_available_lo_32)
node credit_available_lo_lo_27 = cat(states[3].vc_sel.`3`[1], states[3].vc_sel.`3`[0])
node credit_available_lo_hi_27 = cat(states[3].vc_sel.`3`[3], states[3].vc_sel.`3`[2])
node credit_available_lo_33 = cat(credit_available_lo_hi_27, credit_available_lo_lo_27)
node credit_available_hi_lo_27 = cat(states[3].vc_sel.`3`[5], states[3].vc_sel.`3`[4])
node credit_available_hi_hi_27 = cat(states[3].vc_sel.`3`[7], states[3].vc_sel.`3`[6])
node credit_available_hi_33 = cat(credit_available_hi_hi_27, credit_available_hi_lo_27)
node _credit_available_T_36 = cat(credit_available_hi_33, credit_available_lo_33)
node credit_available_lo_34 = cat(_credit_available_T_34, _credit_available_T_33)
node credit_available_hi_34 = cat(_credit_available_T_36, _credit_available_T_35)
node _credit_available_T_37 = cat(credit_available_hi_34, credit_available_lo_34)
node credit_available_lo_lo_28 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_28 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_35 = cat(credit_available_lo_hi_28, credit_available_lo_lo_28)
node credit_available_hi_lo_28 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_28 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_35 = cat(credit_available_hi_hi_28, credit_available_hi_lo_28)
node _credit_available_T_38 = cat(credit_available_hi_35, credit_available_lo_35)
node credit_available_lo_lo_29 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_29 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_36 = cat(credit_available_lo_hi_29, credit_available_lo_lo_29)
node credit_available_hi_lo_29 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_29 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_36 = cat(credit_available_hi_hi_29, credit_available_hi_lo_29)
node _credit_available_T_39 = cat(credit_available_hi_36, credit_available_lo_36)
node credit_available_lo_lo_30 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_30 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_37 = cat(credit_available_lo_hi_30, credit_available_lo_lo_30)
node credit_available_hi_lo_30 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_30 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_37 = cat(credit_available_hi_hi_30, credit_available_hi_lo_30)
node _credit_available_T_40 = cat(credit_available_hi_37, credit_available_lo_37)
node credit_available_lo_lo_31 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_31 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_38 = cat(credit_available_lo_hi_31, credit_available_lo_lo_31)
node credit_available_hi_lo_31 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_31 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_38 = cat(credit_available_hi_hi_31, credit_available_hi_lo_31)
node _credit_available_T_41 = cat(credit_available_hi_38, credit_available_lo_38)
node credit_available_lo_39 = cat(_credit_available_T_39, _credit_available_T_38)
node credit_available_hi_39 = cat(_credit_available_T_41, _credit_available_T_40)
node _credit_available_T_42 = cat(credit_available_hi_39, credit_available_lo_39)
node _credit_available_T_43 = and(_credit_available_T_37, _credit_available_T_42)
node credit_available_3 = neq(_credit_available_T_43, UInt<1>(0h0))
node _salloc_arb_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h3))
node _salloc_arb_io_in_3_valid_T_1 = and(_salloc_arb_io_in_3_valid_T, credit_available_3)
node _salloc_arb_io_in_3_valid_T_2 = and(_salloc_arb_io_in_3_valid_T_1, input_buffer.io.deq[3].valid)
connect salloc_arb.io.in[3].valid, _salloc_arb_io_in_3_valid_T_2
connect salloc_arb.io.in[3].bits.vc_sel.`0`[0], states[3].vc_sel.`0`[0]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[1], states[3].vc_sel.`0`[1]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[2], states[3].vc_sel.`0`[2]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[3], states[3].vc_sel.`0`[3]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[4], states[3].vc_sel.`0`[4]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[5], states[3].vc_sel.`0`[5]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[6], states[3].vc_sel.`0`[6]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[7], states[3].vc_sel.`0`[7]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[0], states[3].vc_sel.`1`[0]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[1], states[3].vc_sel.`1`[1]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[2], states[3].vc_sel.`1`[2]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[3], states[3].vc_sel.`1`[3]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[4], states[3].vc_sel.`1`[4]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[5], states[3].vc_sel.`1`[5]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[6], states[3].vc_sel.`1`[6]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[7], states[3].vc_sel.`1`[7]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[0], states[3].vc_sel.`2`[0]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[1], states[3].vc_sel.`2`[1]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[2], states[3].vc_sel.`2`[2]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[3], states[3].vc_sel.`2`[3]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[4], states[3].vc_sel.`2`[4]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[5], states[3].vc_sel.`2`[5]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[6], states[3].vc_sel.`2`[6]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[7], states[3].vc_sel.`2`[7]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[0], states[3].vc_sel.`3`[0]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[1], states[3].vc_sel.`3`[1]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[2], states[3].vc_sel.`3`[2]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[3], states[3].vc_sel.`3`[3]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[4], states[3].vc_sel.`3`[4]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[5], states[3].vc_sel.`3`[5]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[6], states[3].vc_sel.`3`[6]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[7], states[3].vc_sel.`3`[7]
connect salloc_arb.io.in[3].bits.tail, input_buffer.io.deq[3].bits.tail
node _T_109 = and(salloc_arb.io.in[3].ready, salloc_arb.io.in[3].valid)
node _T_110 = and(_T_109, input_buffer.io.deq[3].bits.tail)
when _T_110 :
connect states[3].g, UInt<3>(0h0)
connect input_buffer.io.deq[3].ready, salloc_arb.io.in[3].ready
node credit_available_lo_lo_32 = cat(states[4].vc_sel.`0`[1], states[4].vc_sel.`0`[0])
node credit_available_lo_hi_32 = cat(states[4].vc_sel.`0`[3], states[4].vc_sel.`0`[2])
node credit_available_lo_40 = cat(credit_available_lo_hi_32, credit_available_lo_lo_32)
node credit_available_hi_lo_32 = cat(states[4].vc_sel.`0`[5], states[4].vc_sel.`0`[4])
node credit_available_hi_hi_32 = cat(states[4].vc_sel.`0`[7], states[4].vc_sel.`0`[6])
node credit_available_hi_40 = cat(credit_available_hi_hi_32, credit_available_hi_lo_32)
node _credit_available_T_44 = cat(credit_available_hi_40, credit_available_lo_40)
node credit_available_lo_lo_33 = cat(states[4].vc_sel.`1`[1], states[4].vc_sel.`1`[0])
node credit_available_lo_hi_33 = cat(states[4].vc_sel.`1`[3], states[4].vc_sel.`1`[2])
node credit_available_lo_41 = cat(credit_available_lo_hi_33, credit_available_lo_lo_33)
node credit_available_hi_lo_33 = cat(states[4].vc_sel.`1`[5], states[4].vc_sel.`1`[4])
node credit_available_hi_hi_33 = cat(states[4].vc_sel.`1`[7], states[4].vc_sel.`1`[6])
node credit_available_hi_41 = cat(credit_available_hi_hi_33, credit_available_hi_lo_33)
node _credit_available_T_45 = cat(credit_available_hi_41, credit_available_lo_41)
node credit_available_lo_lo_34 = cat(states[4].vc_sel.`2`[1], states[4].vc_sel.`2`[0])
node credit_available_lo_hi_34 = cat(states[4].vc_sel.`2`[3], states[4].vc_sel.`2`[2])
node credit_available_lo_42 = cat(credit_available_lo_hi_34, credit_available_lo_lo_34)
node credit_available_hi_lo_34 = cat(states[4].vc_sel.`2`[5], states[4].vc_sel.`2`[4])
node credit_available_hi_hi_34 = cat(states[4].vc_sel.`2`[7], states[4].vc_sel.`2`[6])
node credit_available_hi_42 = cat(credit_available_hi_hi_34, credit_available_hi_lo_34)
node _credit_available_T_46 = cat(credit_available_hi_42, credit_available_lo_42)
node credit_available_lo_lo_35 = cat(states[4].vc_sel.`3`[1], states[4].vc_sel.`3`[0])
node credit_available_lo_hi_35 = cat(states[4].vc_sel.`3`[3], states[4].vc_sel.`3`[2])
node credit_available_lo_43 = cat(credit_available_lo_hi_35, credit_available_lo_lo_35)
node credit_available_hi_lo_35 = cat(states[4].vc_sel.`3`[5], states[4].vc_sel.`3`[4])
node credit_available_hi_hi_35 = cat(states[4].vc_sel.`3`[7], states[4].vc_sel.`3`[6])
node credit_available_hi_43 = cat(credit_available_hi_hi_35, credit_available_hi_lo_35)
node _credit_available_T_47 = cat(credit_available_hi_43, credit_available_lo_43)
node credit_available_lo_44 = cat(_credit_available_T_45, _credit_available_T_44)
node credit_available_hi_44 = cat(_credit_available_T_47, _credit_available_T_46)
node _credit_available_T_48 = cat(credit_available_hi_44, credit_available_lo_44)
node credit_available_lo_lo_36 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_36 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_45 = cat(credit_available_lo_hi_36, credit_available_lo_lo_36)
node credit_available_hi_lo_36 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_36 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_45 = cat(credit_available_hi_hi_36, credit_available_hi_lo_36)
node _credit_available_T_49 = cat(credit_available_hi_45, credit_available_lo_45)
node credit_available_lo_lo_37 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_37 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_46 = cat(credit_available_lo_hi_37, credit_available_lo_lo_37)
node credit_available_hi_lo_37 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_37 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_46 = cat(credit_available_hi_hi_37, credit_available_hi_lo_37)
node _credit_available_T_50 = cat(credit_available_hi_46, credit_available_lo_46)
node credit_available_lo_lo_38 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_38 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_47 = cat(credit_available_lo_hi_38, credit_available_lo_lo_38)
node credit_available_hi_lo_38 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_38 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_47 = cat(credit_available_hi_hi_38, credit_available_hi_lo_38)
node _credit_available_T_51 = cat(credit_available_hi_47, credit_available_lo_47)
node credit_available_lo_lo_39 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_39 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_48 = cat(credit_available_lo_hi_39, credit_available_lo_lo_39)
node credit_available_hi_lo_39 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_39 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_48 = cat(credit_available_hi_hi_39, credit_available_hi_lo_39)
node _credit_available_T_52 = cat(credit_available_hi_48, credit_available_lo_48)
node credit_available_lo_49 = cat(_credit_available_T_50, _credit_available_T_49)
node credit_available_hi_49 = cat(_credit_available_T_52, _credit_available_T_51)
node _credit_available_T_53 = cat(credit_available_hi_49, credit_available_lo_49)
node _credit_available_T_54 = and(_credit_available_T_48, _credit_available_T_53)
node credit_available_4 = neq(_credit_available_T_54, UInt<1>(0h0))
node _salloc_arb_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h3))
node _salloc_arb_io_in_4_valid_T_1 = and(_salloc_arb_io_in_4_valid_T, credit_available_4)
node _salloc_arb_io_in_4_valid_T_2 = and(_salloc_arb_io_in_4_valid_T_1, input_buffer.io.deq[4].valid)
connect salloc_arb.io.in[4].valid, _salloc_arb_io_in_4_valid_T_2
connect salloc_arb.io.in[4].bits.vc_sel.`0`[0], states[4].vc_sel.`0`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[1], states[4].vc_sel.`0`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[2], states[4].vc_sel.`0`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[3], states[4].vc_sel.`0`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[4], states[4].vc_sel.`0`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[5], states[4].vc_sel.`0`[5]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[6], states[4].vc_sel.`0`[6]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[7], states[4].vc_sel.`0`[7]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[0], states[4].vc_sel.`1`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[1], states[4].vc_sel.`1`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[2], states[4].vc_sel.`1`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[3], states[4].vc_sel.`1`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[4], states[4].vc_sel.`1`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[5], states[4].vc_sel.`1`[5]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[6], states[4].vc_sel.`1`[6]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[7], states[4].vc_sel.`1`[7]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[0], states[4].vc_sel.`2`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[1], states[4].vc_sel.`2`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[2], states[4].vc_sel.`2`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[3], states[4].vc_sel.`2`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[4], states[4].vc_sel.`2`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[5], states[4].vc_sel.`2`[5]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[6], states[4].vc_sel.`2`[6]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[7], states[4].vc_sel.`2`[7]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[0], states[4].vc_sel.`3`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[1], states[4].vc_sel.`3`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[2], states[4].vc_sel.`3`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[3], states[4].vc_sel.`3`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[4], states[4].vc_sel.`3`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[5], states[4].vc_sel.`3`[5]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[6], states[4].vc_sel.`3`[6]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[7], states[4].vc_sel.`3`[7]
connect salloc_arb.io.in[4].bits.tail, input_buffer.io.deq[4].bits.tail
node _T_111 = and(salloc_arb.io.in[4].ready, salloc_arb.io.in[4].valid)
node _T_112 = and(_T_111, input_buffer.io.deq[4].bits.tail)
when _T_112 :
connect states[4].g, UInt<3>(0h0)
connect input_buffer.io.deq[4].ready, salloc_arb.io.in[4].ready
node credit_available_lo_lo_40 = cat(states[5].vc_sel.`0`[1], states[5].vc_sel.`0`[0])
node credit_available_lo_hi_40 = cat(states[5].vc_sel.`0`[3], states[5].vc_sel.`0`[2])
node credit_available_lo_50 = cat(credit_available_lo_hi_40, credit_available_lo_lo_40)
node credit_available_hi_lo_40 = cat(states[5].vc_sel.`0`[5], states[5].vc_sel.`0`[4])
node credit_available_hi_hi_40 = cat(states[5].vc_sel.`0`[7], states[5].vc_sel.`0`[6])
node credit_available_hi_50 = cat(credit_available_hi_hi_40, credit_available_hi_lo_40)
node _credit_available_T_55 = cat(credit_available_hi_50, credit_available_lo_50)
node credit_available_lo_lo_41 = cat(states[5].vc_sel.`1`[1], states[5].vc_sel.`1`[0])
node credit_available_lo_hi_41 = cat(states[5].vc_sel.`1`[3], states[5].vc_sel.`1`[2])
node credit_available_lo_51 = cat(credit_available_lo_hi_41, credit_available_lo_lo_41)
node credit_available_hi_lo_41 = cat(states[5].vc_sel.`1`[5], states[5].vc_sel.`1`[4])
node credit_available_hi_hi_41 = cat(states[5].vc_sel.`1`[7], states[5].vc_sel.`1`[6])
node credit_available_hi_51 = cat(credit_available_hi_hi_41, credit_available_hi_lo_41)
node _credit_available_T_56 = cat(credit_available_hi_51, credit_available_lo_51)
node credit_available_lo_lo_42 = cat(states[5].vc_sel.`2`[1], states[5].vc_sel.`2`[0])
node credit_available_lo_hi_42 = cat(states[5].vc_sel.`2`[3], states[5].vc_sel.`2`[2])
node credit_available_lo_52 = cat(credit_available_lo_hi_42, credit_available_lo_lo_42)
node credit_available_hi_lo_42 = cat(states[5].vc_sel.`2`[5], states[5].vc_sel.`2`[4])
node credit_available_hi_hi_42 = cat(states[5].vc_sel.`2`[7], states[5].vc_sel.`2`[6])
node credit_available_hi_52 = cat(credit_available_hi_hi_42, credit_available_hi_lo_42)
node _credit_available_T_57 = cat(credit_available_hi_52, credit_available_lo_52)
node credit_available_lo_lo_43 = cat(states[5].vc_sel.`3`[1], states[5].vc_sel.`3`[0])
node credit_available_lo_hi_43 = cat(states[5].vc_sel.`3`[3], states[5].vc_sel.`3`[2])
node credit_available_lo_53 = cat(credit_available_lo_hi_43, credit_available_lo_lo_43)
node credit_available_hi_lo_43 = cat(states[5].vc_sel.`3`[5], states[5].vc_sel.`3`[4])
node credit_available_hi_hi_43 = cat(states[5].vc_sel.`3`[7], states[5].vc_sel.`3`[6])
node credit_available_hi_53 = cat(credit_available_hi_hi_43, credit_available_hi_lo_43)
node _credit_available_T_58 = cat(credit_available_hi_53, credit_available_lo_53)
node credit_available_lo_54 = cat(_credit_available_T_56, _credit_available_T_55)
node credit_available_hi_54 = cat(_credit_available_T_58, _credit_available_T_57)
node _credit_available_T_59 = cat(credit_available_hi_54, credit_available_lo_54)
node credit_available_lo_lo_44 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_44 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_55 = cat(credit_available_lo_hi_44, credit_available_lo_lo_44)
node credit_available_hi_lo_44 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_44 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_55 = cat(credit_available_hi_hi_44, credit_available_hi_lo_44)
node _credit_available_T_60 = cat(credit_available_hi_55, credit_available_lo_55)
node credit_available_lo_lo_45 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_45 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_56 = cat(credit_available_lo_hi_45, credit_available_lo_lo_45)
node credit_available_hi_lo_45 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_45 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_56 = cat(credit_available_hi_hi_45, credit_available_hi_lo_45)
node _credit_available_T_61 = cat(credit_available_hi_56, credit_available_lo_56)
node credit_available_lo_lo_46 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_46 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_57 = cat(credit_available_lo_hi_46, credit_available_lo_lo_46)
node credit_available_hi_lo_46 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_46 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_57 = cat(credit_available_hi_hi_46, credit_available_hi_lo_46)
node _credit_available_T_62 = cat(credit_available_hi_57, credit_available_lo_57)
node credit_available_lo_lo_47 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_47 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_58 = cat(credit_available_lo_hi_47, credit_available_lo_lo_47)
node credit_available_hi_lo_47 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_47 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_58 = cat(credit_available_hi_hi_47, credit_available_hi_lo_47)
node _credit_available_T_63 = cat(credit_available_hi_58, credit_available_lo_58)
node credit_available_lo_59 = cat(_credit_available_T_61, _credit_available_T_60)
node credit_available_hi_59 = cat(_credit_available_T_63, _credit_available_T_62)
node _credit_available_T_64 = cat(credit_available_hi_59, credit_available_lo_59)
node _credit_available_T_65 = and(_credit_available_T_59, _credit_available_T_64)
node credit_available_5 = neq(_credit_available_T_65, UInt<1>(0h0))
node _salloc_arb_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h3))
node _salloc_arb_io_in_5_valid_T_1 = and(_salloc_arb_io_in_5_valid_T, credit_available_5)
node _salloc_arb_io_in_5_valid_T_2 = and(_salloc_arb_io_in_5_valid_T_1, input_buffer.io.deq[5].valid)
connect salloc_arb.io.in[5].valid, _salloc_arb_io_in_5_valid_T_2
connect salloc_arb.io.in[5].bits.vc_sel.`0`[0], states[5].vc_sel.`0`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[1], states[5].vc_sel.`0`[1]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[2], states[5].vc_sel.`0`[2]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[3], states[5].vc_sel.`0`[3]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[4], states[5].vc_sel.`0`[4]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[5], states[5].vc_sel.`0`[5]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[6], states[5].vc_sel.`0`[6]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[7], states[5].vc_sel.`0`[7]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[0], states[5].vc_sel.`1`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[1], states[5].vc_sel.`1`[1]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[2], states[5].vc_sel.`1`[2]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[3], states[5].vc_sel.`1`[3]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[4], states[5].vc_sel.`1`[4]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[5], states[5].vc_sel.`1`[5]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[6], states[5].vc_sel.`1`[6]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[7], states[5].vc_sel.`1`[7]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[0], states[5].vc_sel.`2`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[1], states[5].vc_sel.`2`[1]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[2], states[5].vc_sel.`2`[2]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[3], states[5].vc_sel.`2`[3]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[4], states[5].vc_sel.`2`[4]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[5], states[5].vc_sel.`2`[5]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[6], states[5].vc_sel.`2`[6]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[7], states[5].vc_sel.`2`[7]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[0], states[5].vc_sel.`3`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[1], states[5].vc_sel.`3`[1]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[2], states[5].vc_sel.`3`[2]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[3], states[5].vc_sel.`3`[3]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[4], states[5].vc_sel.`3`[4]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[5], states[5].vc_sel.`3`[5]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[6], states[5].vc_sel.`3`[6]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[7], states[5].vc_sel.`3`[7]
connect salloc_arb.io.in[5].bits.tail, input_buffer.io.deq[5].bits.tail
node _T_113 = and(salloc_arb.io.in[5].ready, salloc_arb.io.in[5].valid)
node _T_114 = and(_T_113, input_buffer.io.deq[5].bits.tail)
when _T_114 :
connect states[5].g, UInt<3>(0h0)
connect input_buffer.io.deq[5].ready, salloc_arb.io.in[5].ready
node credit_available_lo_lo_48 = cat(states[6].vc_sel.`0`[1], states[6].vc_sel.`0`[0])
node credit_available_lo_hi_48 = cat(states[6].vc_sel.`0`[3], states[6].vc_sel.`0`[2])
node credit_available_lo_60 = cat(credit_available_lo_hi_48, credit_available_lo_lo_48)
node credit_available_hi_lo_48 = cat(states[6].vc_sel.`0`[5], states[6].vc_sel.`0`[4])
node credit_available_hi_hi_48 = cat(states[6].vc_sel.`0`[7], states[6].vc_sel.`0`[6])
node credit_available_hi_60 = cat(credit_available_hi_hi_48, credit_available_hi_lo_48)
node _credit_available_T_66 = cat(credit_available_hi_60, credit_available_lo_60)
node credit_available_lo_lo_49 = cat(states[6].vc_sel.`1`[1], states[6].vc_sel.`1`[0])
node credit_available_lo_hi_49 = cat(states[6].vc_sel.`1`[3], states[6].vc_sel.`1`[2])
node credit_available_lo_61 = cat(credit_available_lo_hi_49, credit_available_lo_lo_49)
node credit_available_hi_lo_49 = cat(states[6].vc_sel.`1`[5], states[6].vc_sel.`1`[4])
node credit_available_hi_hi_49 = cat(states[6].vc_sel.`1`[7], states[6].vc_sel.`1`[6])
node credit_available_hi_61 = cat(credit_available_hi_hi_49, credit_available_hi_lo_49)
node _credit_available_T_67 = cat(credit_available_hi_61, credit_available_lo_61)
node credit_available_lo_lo_50 = cat(states[6].vc_sel.`2`[1], states[6].vc_sel.`2`[0])
node credit_available_lo_hi_50 = cat(states[6].vc_sel.`2`[3], states[6].vc_sel.`2`[2])
node credit_available_lo_62 = cat(credit_available_lo_hi_50, credit_available_lo_lo_50)
node credit_available_hi_lo_50 = cat(states[6].vc_sel.`2`[5], states[6].vc_sel.`2`[4])
node credit_available_hi_hi_50 = cat(states[6].vc_sel.`2`[7], states[6].vc_sel.`2`[6])
node credit_available_hi_62 = cat(credit_available_hi_hi_50, credit_available_hi_lo_50)
node _credit_available_T_68 = cat(credit_available_hi_62, credit_available_lo_62)
node credit_available_lo_lo_51 = cat(states[6].vc_sel.`3`[1], states[6].vc_sel.`3`[0])
node credit_available_lo_hi_51 = cat(states[6].vc_sel.`3`[3], states[6].vc_sel.`3`[2])
node credit_available_lo_63 = cat(credit_available_lo_hi_51, credit_available_lo_lo_51)
node credit_available_hi_lo_51 = cat(states[6].vc_sel.`3`[5], states[6].vc_sel.`3`[4])
node credit_available_hi_hi_51 = cat(states[6].vc_sel.`3`[7], states[6].vc_sel.`3`[6])
node credit_available_hi_63 = cat(credit_available_hi_hi_51, credit_available_hi_lo_51)
node _credit_available_T_69 = cat(credit_available_hi_63, credit_available_lo_63)
node credit_available_lo_64 = cat(_credit_available_T_67, _credit_available_T_66)
node credit_available_hi_64 = cat(_credit_available_T_69, _credit_available_T_68)
node _credit_available_T_70 = cat(credit_available_hi_64, credit_available_lo_64)
node credit_available_lo_lo_52 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_52 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_65 = cat(credit_available_lo_hi_52, credit_available_lo_lo_52)
node credit_available_hi_lo_52 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_52 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_65 = cat(credit_available_hi_hi_52, credit_available_hi_lo_52)
node _credit_available_T_71 = cat(credit_available_hi_65, credit_available_lo_65)
node credit_available_lo_lo_53 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_53 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_66 = cat(credit_available_lo_hi_53, credit_available_lo_lo_53)
node credit_available_hi_lo_53 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_53 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_66 = cat(credit_available_hi_hi_53, credit_available_hi_lo_53)
node _credit_available_T_72 = cat(credit_available_hi_66, credit_available_lo_66)
node credit_available_lo_lo_54 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_54 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_67 = cat(credit_available_lo_hi_54, credit_available_lo_lo_54)
node credit_available_hi_lo_54 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_54 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_67 = cat(credit_available_hi_hi_54, credit_available_hi_lo_54)
node _credit_available_T_73 = cat(credit_available_hi_67, credit_available_lo_67)
node credit_available_lo_lo_55 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_55 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_68 = cat(credit_available_lo_hi_55, credit_available_lo_lo_55)
node credit_available_hi_lo_55 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_55 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_68 = cat(credit_available_hi_hi_55, credit_available_hi_lo_55)
node _credit_available_T_74 = cat(credit_available_hi_68, credit_available_lo_68)
node credit_available_lo_69 = cat(_credit_available_T_72, _credit_available_T_71)
node credit_available_hi_69 = cat(_credit_available_T_74, _credit_available_T_73)
node _credit_available_T_75 = cat(credit_available_hi_69, credit_available_lo_69)
node _credit_available_T_76 = and(_credit_available_T_70, _credit_available_T_75)
node credit_available_6 = neq(_credit_available_T_76, UInt<1>(0h0))
node _salloc_arb_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h3))
node _salloc_arb_io_in_6_valid_T_1 = and(_salloc_arb_io_in_6_valid_T, credit_available_6)
node _salloc_arb_io_in_6_valid_T_2 = and(_salloc_arb_io_in_6_valid_T_1, input_buffer.io.deq[6].valid)
connect salloc_arb.io.in[6].valid, _salloc_arb_io_in_6_valid_T_2
connect salloc_arb.io.in[6].bits.vc_sel.`0`[0], states[6].vc_sel.`0`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[1], states[6].vc_sel.`0`[1]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[2], states[6].vc_sel.`0`[2]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[3], states[6].vc_sel.`0`[3]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[4], states[6].vc_sel.`0`[4]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[5], states[6].vc_sel.`0`[5]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[6], states[6].vc_sel.`0`[6]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[7], states[6].vc_sel.`0`[7]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[0], states[6].vc_sel.`1`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[1], states[6].vc_sel.`1`[1]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[2], states[6].vc_sel.`1`[2]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[3], states[6].vc_sel.`1`[3]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[4], states[6].vc_sel.`1`[4]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[5], states[6].vc_sel.`1`[5]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[6], states[6].vc_sel.`1`[6]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[7], states[6].vc_sel.`1`[7]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[0], states[6].vc_sel.`2`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[1], states[6].vc_sel.`2`[1]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[2], states[6].vc_sel.`2`[2]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[3], states[6].vc_sel.`2`[3]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[4], states[6].vc_sel.`2`[4]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[5], states[6].vc_sel.`2`[5]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[6], states[6].vc_sel.`2`[6]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[7], states[6].vc_sel.`2`[7]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[0], states[6].vc_sel.`3`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[1], states[6].vc_sel.`3`[1]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[2], states[6].vc_sel.`3`[2]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[3], states[6].vc_sel.`3`[3]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[4], states[6].vc_sel.`3`[4]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[5], states[6].vc_sel.`3`[5]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[6], states[6].vc_sel.`3`[6]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[7], states[6].vc_sel.`3`[7]
connect salloc_arb.io.in[6].bits.tail, input_buffer.io.deq[6].bits.tail
node _T_115 = and(salloc_arb.io.in[6].ready, salloc_arb.io.in[6].valid)
node _T_116 = and(_T_115, input_buffer.io.deq[6].bits.tail)
when _T_116 :
connect states[6].g, UInt<3>(0h0)
connect input_buffer.io.deq[6].ready, salloc_arb.io.in[6].ready
node credit_available_lo_lo_56 = cat(states[7].vc_sel.`0`[1], states[7].vc_sel.`0`[0])
node credit_available_lo_hi_56 = cat(states[7].vc_sel.`0`[3], states[7].vc_sel.`0`[2])
node credit_available_lo_70 = cat(credit_available_lo_hi_56, credit_available_lo_lo_56)
node credit_available_hi_lo_56 = cat(states[7].vc_sel.`0`[5], states[7].vc_sel.`0`[4])
node credit_available_hi_hi_56 = cat(states[7].vc_sel.`0`[7], states[7].vc_sel.`0`[6])
node credit_available_hi_70 = cat(credit_available_hi_hi_56, credit_available_hi_lo_56)
node _credit_available_T_77 = cat(credit_available_hi_70, credit_available_lo_70)
node credit_available_lo_lo_57 = cat(states[7].vc_sel.`1`[1], states[7].vc_sel.`1`[0])
node credit_available_lo_hi_57 = cat(states[7].vc_sel.`1`[3], states[7].vc_sel.`1`[2])
node credit_available_lo_71 = cat(credit_available_lo_hi_57, credit_available_lo_lo_57)
node credit_available_hi_lo_57 = cat(states[7].vc_sel.`1`[5], states[7].vc_sel.`1`[4])
node credit_available_hi_hi_57 = cat(states[7].vc_sel.`1`[7], states[7].vc_sel.`1`[6])
node credit_available_hi_71 = cat(credit_available_hi_hi_57, credit_available_hi_lo_57)
node _credit_available_T_78 = cat(credit_available_hi_71, credit_available_lo_71)
node credit_available_lo_lo_58 = cat(states[7].vc_sel.`2`[1], states[7].vc_sel.`2`[0])
node credit_available_lo_hi_58 = cat(states[7].vc_sel.`2`[3], states[7].vc_sel.`2`[2])
node credit_available_lo_72 = cat(credit_available_lo_hi_58, credit_available_lo_lo_58)
node credit_available_hi_lo_58 = cat(states[7].vc_sel.`2`[5], states[7].vc_sel.`2`[4])
node credit_available_hi_hi_58 = cat(states[7].vc_sel.`2`[7], states[7].vc_sel.`2`[6])
node credit_available_hi_72 = cat(credit_available_hi_hi_58, credit_available_hi_lo_58)
node _credit_available_T_79 = cat(credit_available_hi_72, credit_available_lo_72)
node credit_available_lo_lo_59 = cat(states[7].vc_sel.`3`[1], states[7].vc_sel.`3`[0])
node credit_available_lo_hi_59 = cat(states[7].vc_sel.`3`[3], states[7].vc_sel.`3`[2])
node credit_available_lo_73 = cat(credit_available_lo_hi_59, credit_available_lo_lo_59)
node credit_available_hi_lo_59 = cat(states[7].vc_sel.`3`[5], states[7].vc_sel.`3`[4])
node credit_available_hi_hi_59 = cat(states[7].vc_sel.`3`[7], states[7].vc_sel.`3`[6])
node credit_available_hi_73 = cat(credit_available_hi_hi_59, credit_available_hi_lo_59)
node _credit_available_T_80 = cat(credit_available_hi_73, credit_available_lo_73)
node credit_available_lo_74 = cat(_credit_available_T_78, _credit_available_T_77)
node credit_available_hi_74 = cat(_credit_available_T_80, _credit_available_T_79)
node _credit_available_T_81 = cat(credit_available_hi_74, credit_available_lo_74)
node credit_available_lo_lo_60 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_60 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_75 = cat(credit_available_lo_hi_60, credit_available_lo_lo_60)
node credit_available_hi_lo_60 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_60 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_75 = cat(credit_available_hi_hi_60, credit_available_hi_lo_60)
node _credit_available_T_82 = cat(credit_available_hi_75, credit_available_lo_75)
node credit_available_lo_lo_61 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_61 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_76 = cat(credit_available_lo_hi_61, credit_available_lo_lo_61)
node credit_available_hi_lo_61 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_61 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_76 = cat(credit_available_hi_hi_61, credit_available_hi_lo_61)
node _credit_available_T_83 = cat(credit_available_hi_76, credit_available_lo_76)
node credit_available_lo_lo_62 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_62 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_77 = cat(credit_available_lo_hi_62, credit_available_lo_lo_62)
node credit_available_hi_lo_62 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_62 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_77 = cat(credit_available_hi_hi_62, credit_available_hi_lo_62)
node _credit_available_T_84 = cat(credit_available_hi_77, credit_available_lo_77)
node credit_available_lo_lo_63 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_63 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_78 = cat(credit_available_lo_hi_63, credit_available_lo_lo_63)
node credit_available_hi_lo_63 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_63 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_78 = cat(credit_available_hi_hi_63, credit_available_hi_lo_63)
node _credit_available_T_85 = cat(credit_available_hi_78, credit_available_lo_78)
node credit_available_lo_79 = cat(_credit_available_T_83, _credit_available_T_82)
node credit_available_hi_79 = cat(_credit_available_T_85, _credit_available_T_84)
node _credit_available_T_86 = cat(credit_available_hi_79, credit_available_lo_79)
node _credit_available_T_87 = and(_credit_available_T_81, _credit_available_T_86)
node credit_available_7 = neq(_credit_available_T_87, UInt<1>(0h0))
node _salloc_arb_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h3))
node _salloc_arb_io_in_7_valid_T_1 = and(_salloc_arb_io_in_7_valid_T, credit_available_7)
node _salloc_arb_io_in_7_valid_T_2 = and(_salloc_arb_io_in_7_valid_T_1, input_buffer.io.deq[7].valid)
connect salloc_arb.io.in[7].valid, _salloc_arb_io_in_7_valid_T_2
connect salloc_arb.io.in[7].bits.vc_sel.`0`[0], states[7].vc_sel.`0`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[1], states[7].vc_sel.`0`[1]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[2], states[7].vc_sel.`0`[2]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[3], states[7].vc_sel.`0`[3]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[4], states[7].vc_sel.`0`[4]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[5], states[7].vc_sel.`0`[5]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[6], states[7].vc_sel.`0`[6]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[7], states[7].vc_sel.`0`[7]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[0], states[7].vc_sel.`1`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[1], states[7].vc_sel.`1`[1]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[2], states[7].vc_sel.`1`[2]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[3], states[7].vc_sel.`1`[3]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[4], states[7].vc_sel.`1`[4]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[5], states[7].vc_sel.`1`[5]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[6], states[7].vc_sel.`1`[6]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[7], states[7].vc_sel.`1`[7]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[0], states[7].vc_sel.`2`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[1], states[7].vc_sel.`2`[1]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[2], states[7].vc_sel.`2`[2]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[3], states[7].vc_sel.`2`[3]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[4], states[7].vc_sel.`2`[4]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[5], states[7].vc_sel.`2`[5]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[6], states[7].vc_sel.`2`[6]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[7], states[7].vc_sel.`2`[7]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[0], states[7].vc_sel.`3`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[1], states[7].vc_sel.`3`[1]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[2], states[7].vc_sel.`3`[2]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[3], states[7].vc_sel.`3`[3]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[4], states[7].vc_sel.`3`[4]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[5], states[7].vc_sel.`3`[5]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[6], states[7].vc_sel.`3`[6]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[7], states[7].vc_sel.`3`[7]
connect salloc_arb.io.in[7].bits.tail, input_buffer.io.deq[7].bits.tail
node _T_117 = and(salloc_arb.io.in[7].ready, salloc_arb.io.in[7].valid)
node _T_118 = and(_T_117, input_buffer.io.deq[7].bits.tail)
when _T_118 :
connect states[7].g, UInt<3>(0h0)
connect input_buffer.io.deq[7].ready, salloc_arb.io.in[7].ready
node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T)
node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2)
node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4)
node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6)
node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8)
node _io_debug_sa_stall_T_10 = eq(salloc_arb.io.in[5].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_11 = and(salloc_arb.io.in[5].valid, _io_debug_sa_stall_T_10)
node _io_debug_sa_stall_T_12 = eq(salloc_arb.io.in[6].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_13 = and(salloc_arb.io.in[6].valid, _io_debug_sa_stall_T_12)
node _io_debug_sa_stall_T_14 = eq(salloc_arb.io.in[7].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_15 = and(salloc_arb.io.in[7].valid, _io_debug_sa_stall_T_14)
node _io_debug_sa_stall_T_16 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3)
node _io_debug_sa_stall_T_17 = bits(_io_debug_sa_stall_T_16, 1, 0)
node _io_debug_sa_stall_T_18 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_7)
node _io_debug_sa_stall_T_19 = bits(_io_debug_sa_stall_T_18, 1, 0)
node _io_debug_sa_stall_T_20 = add(_io_debug_sa_stall_T_17, _io_debug_sa_stall_T_19)
node _io_debug_sa_stall_T_21 = bits(_io_debug_sa_stall_T_20, 2, 0)
node _io_debug_sa_stall_T_22 = add(_io_debug_sa_stall_T_9, _io_debug_sa_stall_T_11)
node _io_debug_sa_stall_T_23 = bits(_io_debug_sa_stall_T_22, 1, 0)
node _io_debug_sa_stall_T_24 = add(_io_debug_sa_stall_T_13, _io_debug_sa_stall_T_15)
node _io_debug_sa_stall_T_25 = bits(_io_debug_sa_stall_T_24, 1, 0)
node _io_debug_sa_stall_T_26 = add(_io_debug_sa_stall_T_23, _io_debug_sa_stall_T_25)
node _io_debug_sa_stall_T_27 = bits(_io_debug_sa_stall_T_26, 2, 0)
node _io_debug_sa_stall_T_28 = add(_io_debug_sa_stall_T_21, _io_debug_sa_stall_T_27)
node _io_debug_sa_stall_T_29 = bits(_io_debug_sa_stall_T_28, 3, 0)
connect io.debug.sa_stall, _io_debug_sa_stall_T_29
connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits
connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid
connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready
when io.block :
connect salloc_arb.io.out[0].ready, UInt<1>(0h0)
connect io.salloc_req[0].valid, UInt<1>(0h0)
reg salloc_outs : { valid : UInt<1>, vid : UInt<3>, out_vid : UInt<3>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], clock
node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.credit_return, _io_in_credit_return_T_1
node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _io_in_vc_free_T_6 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _io_in_vc_free_T_7 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _io_in_vc_free_T_8 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _io_in_vc_free_T_9 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_11 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_12 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_13 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_14 = mux(_io_in_vc_free_T_6, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_15 = mux(_io_in_vc_free_T_7, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_16 = mux(_io_in_vc_free_T_8, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_17 = or(_io_in_vc_free_T_9, _io_in_vc_free_T_10)
node _io_in_vc_free_T_18 = or(_io_in_vc_free_T_17, _io_in_vc_free_T_11)
node _io_in_vc_free_T_19 = or(_io_in_vc_free_T_18, _io_in_vc_free_T_12)
node _io_in_vc_free_T_20 = or(_io_in_vc_free_T_19, _io_in_vc_free_T_13)
node _io_in_vc_free_T_21 = or(_io_in_vc_free_T_20, _io_in_vc_free_T_14)
node _io_in_vc_free_T_22 = or(_io_in_vc_free_T_21, _io_in_vc_free_T_15)
node _io_in_vc_free_T_23 = or(_io_in_vc_free_T_22, _io_in_vc_free_T_16)
wire _io_in_vc_free_WIRE : UInt<1>
connect _io_in_vc_free_WIRE, _io_in_vc_free_T_23
node _io_in_vc_free_T_24 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE)
node _io_in_vc_free_T_25 = mux(_io_in_vc_free_T_24, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.vc_free, _io_in_vc_free_T_25
node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
connect salloc_outs[0].valid, _salloc_outs_0_valid_T
node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 7, 4)
node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 3, 0)
node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi)
node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo)
node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 3, 2)
node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 1, 0)
node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1)
node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1)
node _salloc_outs_0_vid_T_4 = bits(_salloc_outs_0_vid_T_3, 1, 1)
node _salloc_outs_0_vid_T_5 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_4)
node _salloc_outs_0_vid_T_6 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_5)
connect salloc_outs[0].vid, _salloc_outs_0_vid_T_6
node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _vc_sel_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _vc_sel_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _vc_sel_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
wire vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}
wire _vc_sel_WIRE : UInt<1>[8]
node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_10 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_11 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_12 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_13 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_14 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_15 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_16 = or(_vc_sel_T_8, _vc_sel_T_9)
node _vc_sel_T_17 = or(_vc_sel_T_16, _vc_sel_T_10)
node _vc_sel_T_18 = or(_vc_sel_T_17, _vc_sel_T_11)
node _vc_sel_T_19 = or(_vc_sel_T_18, _vc_sel_T_12)
node _vc_sel_T_20 = or(_vc_sel_T_19, _vc_sel_T_13)
node _vc_sel_T_21 = or(_vc_sel_T_20, _vc_sel_T_14)
node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_15)
wire _vc_sel_WIRE_1 : UInt<1>
connect _vc_sel_WIRE_1, _vc_sel_T_22
connect _vc_sel_WIRE[0], _vc_sel_WIRE_1
node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_26 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_27 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_28 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_29 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_30 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_31 = or(_vc_sel_T_23, _vc_sel_T_24)
node _vc_sel_T_32 = or(_vc_sel_T_31, _vc_sel_T_25)
node _vc_sel_T_33 = or(_vc_sel_T_32, _vc_sel_T_26)
node _vc_sel_T_34 = or(_vc_sel_T_33, _vc_sel_T_27)
node _vc_sel_T_35 = or(_vc_sel_T_34, _vc_sel_T_28)
node _vc_sel_T_36 = or(_vc_sel_T_35, _vc_sel_T_29)
node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_30)
wire _vc_sel_WIRE_2 : UInt<1>
connect _vc_sel_WIRE_2, _vc_sel_T_37
connect _vc_sel_WIRE[1], _vc_sel_WIRE_2
node _vc_sel_T_38 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_39 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_40 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_41 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_42 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_43 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_44 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_45 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_46 = or(_vc_sel_T_38, _vc_sel_T_39)
node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_40)
node _vc_sel_T_48 = or(_vc_sel_T_47, _vc_sel_T_41)
node _vc_sel_T_49 = or(_vc_sel_T_48, _vc_sel_T_42)
node _vc_sel_T_50 = or(_vc_sel_T_49, _vc_sel_T_43)
node _vc_sel_T_51 = or(_vc_sel_T_50, _vc_sel_T_44)
node _vc_sel_T_52 = or(_vc_sel_T_51, _vc_sel_T_45)
wire _vc_sel_WIRE_3 : UInt<1>
connect _vc_sel_WIRE_3, _vc_sel_T_52
connect _vc_sel_WIRE[2], _vc_sel_WIRE_3
node _vc_sel_T_53 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_54 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_55 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_56 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_57 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_58 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_59 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_60 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_61 = or(_vc_sel_T_53, _vc_sel_T_54)
node _vc_sel_T_62 = or(_vc_sel_T_61, _vc_sel_T_55)
node _vc_sel_T_63 = or(_vc_sel_T_62, _vc_sel_T_56)
node _vc_sel_T_64 = or(_vc_sel_T_63, _vc_sel_T_57)
node _vc_sel_T_65 = or(_vc_sel_T_64, _vc_sel_T_58)
node _vc_sel_T_66 = or(_vc_sel_T_65, _vc_sel_T_59)
node _vc_sel_T_67 = or(_vc_sel_T_66, _vc_sel_T_60)
wire _vc_sel_WIRE_4 : UInt<1>
connect _vc_sel_WIRE_4, _vc_sel_T_67
connect _vc_sel_WIRE[3], _vc_sel_WIRE_4
node _vc_sel_T_68 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_69 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_70 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_71 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_72 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_73 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_74 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_75 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_76 = or(_vc_sel_T_68, _vc_sel_T_69)
node _vc_sel_T_77 = or(_vc_sel_T_76, _vc_sel_T_70)
node _vc_sel_T_78 = or(_vc_sel_T_77, _vc_sel_T_71)
node _vc_sel_T_79 = or(_vc_sel_T_78, _vc_sel_T_72)
node _vc_sel_T_80 = or(_vc_sel_T_79, _vc_sel_T_73)
node _vc_sel_T_81 = or(_vc_sel_T_80, _vc_sel_T_74)
node _vc_sel_T_82 = or(_vc_sel_T_81, _vc_sel_T_75)
wire _vc_sel_WIRE_5 : UInt<1>
connect _vc_sel_WIRE_5, _vc_sel_T_82
connect _vc_sel_WIRE[4], _vc_sel_WIRE_5
node _vc_sel_T_83 = mux(_vc_sel_T, states[0].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_84 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_85 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_86 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_87 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_88 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_89 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_90 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_91 = or(_vc_sel_T_83, _vc_sel_T_84)
node _vc_sel_T_92 = or(_vc_sel_T_91, _vc_sel_T_85)
node _vc_sel_T_93 = or(_vc_sel_T_92, _vc_sel_T_86)
node _vc_sel_T_94 = or(_vc_sel_T_93, _vc_sel_T_87)
node _vc_sel_T_95 = or(_vc_sel_T_94, _vc_sel_T_88)
node _vc_sel_T_96 = or(_vc_sel_T_95, _vc_sel_T_89)
node _vc_sel_T_97 = or(_vc_sel_T_96, _vc_sel_T_90)
wire _vc_sel_WIRE_6 : UInt<1>
connect _vc_sel_WIRE_6, _vc_sel_T_97
connect _vc_sel_WIRE[5], _vc_sel_WIRE_6
node _vc_sel_T_98 = mux(_vc_sel_T, states[0].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_99 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_100 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_101 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_102 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_103 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_104 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_105 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_106 = or(_vc_sel_T_98, _vc_sel_T_99)
node _vc_sel_T_107 = or(_vc_sel_T_106, _vc_sel_T_100)
node _vc_sel_T_108 = or(_vc_sel_T_107, _vc_sel_T_101)
node _vc_sel_T_109 = or(_vc_sel_T_108, _vc_sel_T_102)
node _vc_sel_T_110 = or(_vc_sel_T_109, _vc_sel_T_103)
node _vc_sel_T_111 = or(_vc_sel_T_110, _vc_sel_T_104)
node _vc_sel_T_112 = or(_vc_sel_T_111, _vc_sel_T_105)
wire _vc_sel_WIRE_7 : UInt<1>
connect _vc_sel_WIRE_7, _vc_sel_T_112
connect _vc_sel_WIRE[6], _vc_sel_WIRE_7
node _vc_sel_T_113 = mux(_vc_sel_T, states[0].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_114 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_115 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_116 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_117 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_118 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_119 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_120 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_121 = or(_vc_sel_T_113, _vc_sel_T_114)
node _vc_sel_T_122 = or(_vc_sel_T_121, _vc_sel_T_115)
node _vc_sel_T_123 = or(_vc_sel_T_122, _vc_sel_T_116)
node _vc_sel_T_124 = or(_vc_sel_T_123, _vc_sel_T_117)
node _vc_sel_T_125 = or(_vc_sel_T_124, _vc_sel_T_118)
node _vc_sel_T_126 = or(_vc_sel_T_125, _vc_sel_T_119)
node _vc_sel_T_127 = or(_vc_sel_T_126, _vc_sel_T_120)
wire _vc_sel_WIRE_8 : UInt<1>
connect _vc_sel_WIRE_8, _vc_sel_T_127
connect _vc_sel_WIRE[7], _vc_sel_WIRE_8
connect vc_sel.`0`, _vc_sel_WIRE
wire _vc_sel_WIRE_9 : UInt<1>[8]
node _vc_sel_T_128 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_129 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_130 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_131 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_132 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_133 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_134 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_135 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_136 = or(_vc_sel_T_128, _vc_sel_T_129)
node _vc_sel_T_137 = or(_vc_sel_T_136, _vc_sel_T_130)
node _vc_sel_T_138 = or(_vc_sel_T_137, _vc_sel_T_131)
node _vc_sel_T_139 = or(_vc_sel_T_138, _vc_sel_T_132)
node _vc_sel_T_140 = or(_vc_sel_T_139, _vc_sel_T_133)
node _vc_sel_T_141 = or(_vc_sel_T_140, _vc_sel_T_134)
node _vc_sel_T_142 = or(_vc_sel_T_141, _vc_sel_T_135)
wire _vc_sel_WIRE_10 : UInt<1>
connect _vc_sel_WIRE_10, _vc_sel_T_142
connect _vc_sel_WIRE_9[0], _vc_sel_WIRE_10
node _vc_sel_T_143 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_144 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_145 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_146 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_147 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_148 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_149 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_150 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_151 = or(_vc_sel_T_143, _vc_sel_T_144)
node _vc_sel_T_152 = or(_vc_sel_T_151, _vc_sel_T_145)
node _vc_sel_T_153 = or(_vc_sel_T_152, _vc_sel_T_146)
node _vc_sel_T_154 = or(_vc_sel_T_153, _vc_sel_T_147)
node _vc_sel_T_155 = or(_vc_sel_T_154, _vc_sel_T_148)
node _vc_sel_T_156 = or(_vc_sel_T_155, _vc_sel_T_149)
node _vc_sel_T_157 = or(_vc_sel_T_156, _vc_sel_T_150)
wire _vc_sel_WIRE_11 : UInt<1>
connect _vc_sel_WIRE_11, _vc_sel_T_157
connect _vc_sel_WIRE_9[1], _vc_sel_WIRE_11
node _vc_sel_T_158 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_159 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_160 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_161 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_162 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_163 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_164 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_165 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_166 = or(_vc_sel_T_158, _vc_sel_T_159)
node _vc_sel_T_167 = or(_vc_sel_T_166, _vc_sel_T_160)
node _vc_sel_T_168 = or(_vc_sel_T_167, _vc_sel_T_161)
node _vc_sel_T_169 = or(_vc_sel_T_168, _vc_sel_T_162)
node _vc_sel_T_170 = or(_vc_sel_T_169, _vc_sel_T_163)
node _vc_sel_T_171 = or(_vc_sel_T_170, _vc_sel_T_164)
node _vc_sel_T_172 = or(_vc_sel_T_171, _vc_sel_T_165)
wire _vc_sel_WIRE_12 : UInt<1>
connect _vc_sel_WIRE_12, _vc_sel_T_172
connect _vc_sel_WIRE_9[2], _vc_sel_WIRE_12
node _vc_sel_T_173 = mux(_vc_sel_T, states[0].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_174 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_175 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_176 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_177 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_178 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_179 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_180 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_181 = or(_vc_sel_T_173, _vc_sel_T_174)
node _vc_sel_T_182 = or(_vc_sel_T_181, _vc_sel_T_175)
node _vc_sel_T_183 = or(_vc_sel_T_182, _vc_sel_T_176)
node _vc_sel_T_184 = or(_vc_sel_T_183, _vc_sel_T_177)
node _vc_sel_T_185 = or(_vc_sel_T_184, _vc_sel_T_178)
node _vc_sel_T_186 = or(_vc_sel_T_185, _vc_sel_T_179)
node _vc_sel_T_187 = or(_vc_sel_T_186, _vc_sel_T_180)
wire _vc_sel_WIRE_13 : UInt<1>
connect _vc_sel_WIRE_13, _vc_sel_T_187
connect _vc_sel_WIRE_9[3], _vc_sel_WIRE_13
node _vc_sel_T_188 = mux(_vc_sel_T, states[0].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_189 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_190 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_191 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_192 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_193 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_194 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_195 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_196 = or(_vc_sel_T_188, _vc_sel_T_189)
node _vc_sel_T_197 = or(_vc_sel_T_196, _vc_sel_T_190)
node _vc_sel_T_198 = or(_vc_sel_T_197, _vc_sel_T_191)
node _vc_sel_T_199 = or(_vc_sel_T_198, _vc_sel_T_192)
node _vc_sel_T_200 = or(_vc_sel_T_199, _vc_sel_T_193)
node _vc_sel_T_201 = or(_vc_sel_T_200, _vc_sel_T_194)
node _vc_sel_T_202 = or(_vc_sel_T_201, _vc_sel_T_195)
wire _vc_sel_WIRE_14 : UInt<1>
connect _vc_sel_WIRE_14, _vc_sel_T_202
connect _vc_sel_WIRE_9[4], _vc_sel_WIRE_14
node _vc_sel_T_203 = mux(_vc_sel_T, states[0].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_204 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_205 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_206 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_207 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_208 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_209 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_210 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_211 = or(_vc_sel_T_203, _vc_sel_T_204)
node _vc_sel_T_212 = or(_vc_sel_T_211, _vc_sel_T_205)
node _vc_sel_T_213 = or(_vc_sel_T_212, _vc_sel_T_206)
node _vc_sel_T_214 = or(_vc_sel_T_213, _vc_sel_T_207)
node _vc_sel_T_215 = or(_vc_sel_T_214, _vc_sel_T_208)
node _vc_sel_T_216 = or(_vc_sel_T_215, _vc_sel_T_209)
node _vc_sel_T_217 = or(_vc_sel_T_216, _vc_sel_T_210)
wire _vc_sel_WIRE_15 : UInt<1>
connect _vc_sel_WIRE_15, _vc_sel_T_217
connect _vc_sel_WIRE_9[5], _vc_sel_WIRE_15
node _vc_sel_T_218 = mux(_vc_sel_T, states[0].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_219 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_220 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_221 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_222 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_223 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_224 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_225 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_226 = or(_vc_sel_T_218, _vc_sel_T_219)
node _vc_sel_T_227 = or(_vc_sel_T_226, _vc_sel_T_220)
node _vc_sel_T_228 = or(_vc_sel_T_227, _vc_sel_T_221)
node _vc_sel_T_229 = or(_vc_sel_T_228, _vc_sel_T_222)
node _vc_sel_T_230 = or(_vc_sel_T_229, _vc_sel_T_223)
node _vc_sel_T_231 = or(_vc_sel_T_230, _vc_sel_T_224)
node _vc_sel_T_232 = or(_vc_sel_T_231, _vc_sel_T_225)
wire _vc_sel_WIRE_16 : UInt<1>
connect _vc_sel_WIRE_16, _vc_sel_T_232
connect _vc_sel_WIRE_9[6], _vc_sel_WIRE_16
node _vc_sel_T_233 = mux(_vc_sel_T, states[0].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_234 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_235 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_236 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_237 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_238 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_239 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_240 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_241 = or(_vc_sel_T_233, _vc_sel_T_234)
node _vc_sel_T_242 = or(_vc_sel_T_241, _vc_sel_T_235)
node _vc_sel_T_243 = or(_vc_sel_T_242, _vc_sel_T_236)
node _vc_sel_T_244 = or(_vc_sel_T_243, _vc_sel_T_237)
node _vc_sel_T_245 = or(_vc_sel_T_244, _vc_sel_T_238)
node _vc_sel_T_246 = or(_vc_sel_T_245, _vc_sel_T_239)
node _vc_sel_T_247 = or(_vc_sel_T_246, _vc_sel_T_240)
wire _vc_sel_WIRE_17 : UInt<1>
connect _vc_sel_WIRE_17, _vc_sel_T_247
connect _vc_sel_WIRE_9[7], _vc_sel_WIRE_17
connect vc_sel.`1`, _vc_sel_WIRE_9
wire _vc_sel_WIRE_18 : UInt<1>[8]
node _vc_sel_T_248 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_249 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_250 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_251 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_252 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_253 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_254 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_255 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_256 = or(_vc_sel_T_248, _vc_sel_T_249)
node _vc_sel_T_257 = or(_vc_sel_T_256, _vc_sel_T_250)
node _vc_sel_T_258 = or(_vc_sel_T_257, _vc_sel_T_251)
node _vc_sel_T_259 = or(_vc_sel_T_258, _vc_sel_T_252)
node _vc_sel_T_260 = or(_vc_sel_T_259, _vc_sel_T_253)
node _vc_sel_T_261 = or(_vc_sel_T_260, _vc_sel_T_254)
node _vc_sel_T_262 = or(_vc_sel_T_261, _vc_sel_T_255)
wire _vc_sel_WIRE_19 : UInt<1>
connect _vc_sel_WIRE_19, _vc_sel_T_262
connect _vc_sel_WIRE_18[0], _vc_sel_WIRE_19
node _vc_sel_T_263 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_264 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_265 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_266 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_267 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_268 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_269 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_270 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_271 = or(_vc_sel_T_263, _vc_sel_T_264)
node _vc_sel_T_272 = or(_vc_sel_T_271, _vc_sel_T_265)
node _vc_sel_T_273 = or(_vc_sel_T_272, _vc_sel_T_266)
node _vc_sel_T_274 = or(_vc_sel_T_273, _vc_sel_T_267)
node _vc_sel_T_275 = or(_vc_sel_T_274, _vc_sel_T_268)
node _vc_sel_T_276 = or(_vc_sel_T_275, _vc_sel_T_269)
node _vc_sel_T_277 = or(_vc_sel_T_276, _vc_sel_T_270)
wire _vc_sel_WIRE_20 : UInt<1>
connect _vc_sel_WIRE_20, _vc_sel_T_277
connect _vc_sel_WIRE_18[1], _vc_sel_WIRE_20
node _vc_sel_T_278 = mux(_vc_sel_T, states[0].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_279 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_280 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_281 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_282 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_283 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_284 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_285 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_286 = or(_vc_sel_T_278, _vc_sel_T_279)
node _vc_sel_T_287 = or(_vc_sel_T_286, _vc_sel_T_280)
node _vc_sel_T_288 = or(_vc_sel_T_287, _vc_sel_T_281)
node _vc_sel_T_289 = or(_vc_sel_T_288, _vc_sel_T_282)
node _vc_sel_T_290 = or(_vc_sel_T_289, _vc_sel_T_283)
node _vc_sel_T_291 = or(_vc_sel_T_290, _vc_sel_T_284)
node _vc_sel_T_292 = or(_vc_sel_T_291, _vc_sel_T_285)
wire _vc_sel_WIRE_21 : UInt<1>
connect _vc_sel_WIRE_21, _vc_sel_T_292
connect _vc_sel_WIRE_18[2], _vc_sel_WIRE_21
node _vc_sel_T_293 = mux(_vc_sel_T, states[0].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_294 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_295 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_296 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_297 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_298 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_299 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_300 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_301 = or(_vc_sel_T_293, _vc_sel_T_294)
node _vc_sel_T_302 = or(_vc_sel_T_301, _vc_sel_T_295)
node _vc_sel_T_303 = or(_vc_sel_T_302, _vc_sel_T_296)
node _vc_sel_T_304 = or(_vc_sel_T_303, _vc_sel_T_297)
node _vc_sel_T_305 = or(_vc_sel_T_304, _vc_sel_T_298)
node _vc_sel_T_306 = or(_vc_sel_T_305, _vc_sel_T_299)
node _vc_sel_T_307 = or(_vc_sel_T_306, _vc_sel_T_300)
wire _vc_sel_WIRE_22 : UInt<1>
connect _vc_sel_WIRE_22, _vc_sel_T_307
connect _vc_sel_WIRE_18[3], _vc_sel_WIRE_22
node _vc_sel_T_308 = mux(_vc_sel_T, states[0].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_309 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_310 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_311 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_312 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_313 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_314 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_315 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_316 = or(_vc_sel_T_308, _vc_sel_T_309)
node _vc_sel_T_317 = or(_vc_sel_T_316, _vc_sel_T_310)
node _vc_sel_T_318 = or(_vc_sel_T_317, _vc_sel_T_311)
node _vc_sel_T_319 = or(_vc_sel_T_318, _vc_sel_T_312)
node _vc_sel_T_320 = or(_vc_sel_T_319, _vc_sel_T_313)
node _vc_sel_T_321 = or(_vc_sel_T_320, _vc_sel_T_314)
node _vc_sel_T_322 = or(_vc_sel_T_321, _vc_sel_T_315)
wire _vc_sel_WIRE_23 : UInt<1>
connect _vc_sel_WIRE_23, _vc_sel_T_322
connect _vc_sel_WIRE_18[4], _vc_sel_WIRE_23
node _vc_sel_T_323 = mux(_vc_sel_T, states[0].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_324 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_325 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_326 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_327 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_328 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_329 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_330 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_331 = or(_vc_sel_T_323, _vc_sel_T_324)
node _vc_sel_T_332 = or(_vc_sel_T_331, _vc_sel_T_325)
node _vc_sel_T_333 = or(_vc_sel_T_332, _vc_sel_T_326)
node _vc_sel_T_334 = or(_vc_sel_T_333, _vc_sel_T_327)
node _vc_sel_T_335 = or(_vc_sel_T_334, _vc_sel_T_328)
node _vc_sel_T_336 = or(_vc_sel_T_335, _vc_sel_T_329)
node _vc_sel_T_337 = or(_vc_sel_T_336, _vc_sel_T_330)
wire _vc_sel_WIRE_24 : UInt<1>
connect _vc_sel_WIRE_24, _vc_sel_T_337
connect _vc_sel_WIRE_18[5], _vc_sel_WIRE_24
node _vc_sel_T_338 = mux(_vc_sel_T, states[0].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_339 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_340 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_341 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_342 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_343 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_344 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_345 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_346 = or(_vc_sel_T_338, _vc_sel_T_339)
node _vc_sel_T_347 = or(_vc_sel_T_346, _vc_sel_T_340)
node _vc_sel_T_348 = or(_vc_sel_T_347, _vc_sel_T_341)
node _vc_sel_T_349 = or(_vc_sel_T_348, _vc_sel_T_342)
node _vc_sel_T_350 = or(_vc_sel_T_349, _vc_sel_T_343)
node _vc_sel_T_351 = or(_vc_sel_T_350, _vc_sel_T_344)
node _vc_sel_T_352 = or(_vc_sel_T_351, _vc_sel_T_345)
wire _vc_sel_WIRE_25 : UInt<1>
connect _vc_sel_WIRE_25, _vc_sel_T_352
connect _vc_sel_WIRE_18[6], _vc_sel_WIRE_25
node _vc_sel_T_353 = mux(_vc_sel_T, states[0].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_354 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_355 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_356 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_357 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_358 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_359 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_360 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_361 = or(_vc_sel_T_353, _vc_sel_T_354)
node _vc_sel_T_362 = or(_vc_sel_T_361, _vc_sel_T_355)
node _vc_sel_T_363 = or(_vc_sel_T_362, _vc_sel_T_356)
node _vc_sel_T_364 = or(_vc_sel_T_363, _vc_sel_T_357)
node _vc_sel_T_365 = or(_vc_sel_T_364, _vc_sel_T_358)
node _vc_sel_T_366 = or(_vc_sel_T_365, _vc_sel_T_359)
node _vc_sel_T_367 = or(_vc_sel_T_366, _vc_sel_T_360)
wire _vc_sel_WIRE_26 : UInt<1>
connect _vc_sel_WIRE_26, _vc_sel_T_367
connect _vc_sel_WIRE_18[7], _vc_sel_WIRE_26
connect vc_sel.`2`, _vc_sel_WIRE_18
wire _vc_sel_WIRE_27 : UInt<1>[8]
node _vc_sel_T_368 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_369 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_370 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_371 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_372 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_373 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_374 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_375 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_376 = or(_vc_sel_T_368, _vc_sel_T_369)
node _vc_sel_T_377 = or(_vc_sel_T_376, _vc_sel_T_370)
node _vc_sel_T_378 = or(_vc_sel_T_377, _vc_sel_T_371)
node _vc_sel_T_379 = or(_vc_sel_T_378, _vc_sel_T_372)
node _vc_sel_T_380 = or(_vc_sel_T_379, _vc_sel_T_373)
node _vc_sel_T_381 = or(_vc_sel_T_380, _vc_sel_T_374)
node _vc_sel_T_382 = or(_vc_sel_T_381, _vc_sel_T_375)
wire _vc_sel_WIRE_28 : UInt<1>
connect _vc_sel_WIRE_28, _vc_sel_T_382
connect _vc_sel_WIRE_27[0], _vc_sel_WIRE_28
node _vc_sel_T_383 = mux(_vc_sel_T, states[0].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_384 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_385 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_386 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_387 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_388 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_389 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_390 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_391 = or(_vc_sel_T_383, _vc_sel_T_384)
node _vc_sel_T_392 = or(_vc_sel_T_391, _vc_sel_T_385)
node _vc_sel_T_393 = or(_vc_sel_T_392, _vc_sel_T_386)
node _vc_sel_T_394 = or(_vc_sel_T_393, _vc_sel_T_387)
node _vc_sel_T_395 = or(_vc_sel_T_394, _vc_sel_T_388)
node _vc_sel_T_396 = or(_vc_sel_T_395, _vc_sel_T_389)
node _vc_sel_T_397 = or(_vc_sel_T_396, _vc_sel_T_390)
wire _vc_sel_WIRE_29 : UInt<1>
connect _vc_sel_WIRE_29, _vc_sel_T_397
connect _vc_sel_WIRE_27[1], _vc_sel_WIRE_29
node _vc_sel_T_398 = mux(_vc_sel_T, states[0].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_399 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_400 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_401 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_402 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_403 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_404 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_405 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_406 = or(_vc_sel_T_398, _vc_sel_T_399)
node _vc_sel_T_407 = or(_vc_sel_T_406, _vc_sel_T_400)
node _vc_sel_T_408 = or(_vc_sel_T_407, _vc_sel_T_401)
node _vc_sel_T_409 = or(_vc_sel_T_408, _vc_sel_T_402)
node _vc_sel_T_410 = or(_vc_sel_T_409, _vc_sel_T_403)
node _vc_sel_T_411 = or(_vc_sel_T_410, _vc_sel_T_404)
node _vc_sel_T_412 = or(_vc_sel_T_411, _vc_sel_T_405)
wire _vc_sel_WIRE_30 : UInt<1>
connect _vc_sel_WIRE_30, _vc_sel_T_412
connect _vc_sel_WIRE_27[2], _vc_sel_WIRE_30
node _vc_sel_T_413 = mux(_vc_sel_T, states[0].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_414 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_415 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_416 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_417 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_418 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_419 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_420 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_421 = or(_vc_sel_T_413, _vc_sel_T_414)
node _vc_sel_T_422 = or(_vc_sel_T_421, _vc_sel_T_415)
node _vc_sel_T_423 = or(_vc_sel_T_422, _vc_sel_T_416)
node _vc_sel_T_424 = or(_vc_sel_T_423, _vc_sel_T_417)
node _vc_sel_T_425 = or(_vc_sel_T_424, _vc_sel_T_418)
node _vc_sel_T_426 = or(_vc_sel_T_425, _vc_sel_T_419)
node _vc_sel_T_427 = or(_vc_sel_T_426, _vc_sel_T_420)
wire _vc_sel_WIRE_31 : UInt<1>
connect _vc_sel_WIRE_31, _vc_sel_T_427
connect _vc_sel_WIRE_27[3], _vc_sel_WIRE_31
node _vc_sel_T_428 = mux(_vc_sel_T, states[0].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_429 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_430 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_431 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_432 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_433 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_434 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_435 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_436 = or(_vc_sel_T_428, _vc_sel_T_429)
node _vc_sel_T_437 = or(_vc_sel_T_436, _vc_sel_T_430)
node _vc_sel_T_438 = or(_vc_sel_T_437, _vc_sel_T_431)
node _vc_sel_T_439 = or(_vc_sel_T_438, _vc_sel_T_432)
node _vc_sel_T_440 = or(_vc_sel_T_439, _vc_sel_T_433)
node _vc_sel_T_441 = or(_vc_sel_T_440, _vc_sel_T_434)
node _vc_sel_T_442 = or(_vc_sel_T_441, _vc_sel_T_435)
wire _vc_sel_WIRE_32 : UInt<1>
connect _vc_sel_WIRE_32, _vc_sel_T_442
connect _vc_sel_WIRE_27[4], _vc_sel_WIRE_32
node _vc_sel_T_443 = mux(_vc_sel_T, states[0].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_444 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_445 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_446 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_447 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_448 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_449 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_450 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_451 = or(_vc_sel_T_443, _vc_sel_T_444)
node _vc_sel_T_452 = or(_vc_sel_T_451, _vc_sel_T_445)
node _vc_sel_T_453 = or(_vc_sel_T_452, _vc_sel_T_446)
node _vc_sel_T_454 = or(_vc_sel_T_453, _vc_sel_T_447)
node _vc_sel_T_455 = or(_vc_sel_T_454, _vc_sel_T_448)
node _vc_sel_T_456 = or(_vc_sel_T_455, _vc_sel_T_449)
node _vc_sel_T_457 = or(_vc_sel_T_456, _vc_sel_T_450)
wire _vc_sel_WIRE_33 : UInt<1>
connect _vc_sel_WIRE_33, _vc_sel_T_457
connect _vc_sel_WIRE_27[5], _vc_sel_WIRE_33
node _vc_sel_T_458 = mux(_vc_sel_T, states[0].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_459 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_460 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_461 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_462 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_463 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_464 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_465 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_466 = or(_vc_sel_T_458, _vc_sel_T_459)
node _vc_sel_T_467 = or(_vc_sel_T_466, _vc_sel_T_460)
node _vc_sel_T_468 = or(_vc_sel_T_467, _vc_sel_T_461)
node _vc_sel_T_469 = or(_vc_sel_T_468, _vc_sel_T_462)
node _vc_sel_T_470 = or(_vc_sel_T_469, _vc_sel_T_463)
node _vc_sel_T_471 = or(_vc_sel_T_470, _vc_sel_T_464)
node _vc_sel_T_472 = or(_vc_sel_T_471, _vc_sel_T_465)
wire _vc_sel_WIRE_34 : UInt<1>
connect _vc_sel_WIRE_34, _vc_sel_T_472
connect _vc_sel_WIRE_27[6], _vc_sel_WIRE_34
node _vc_sel_T_473 = mux(_vc_sel_T, states[0].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_474 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_475 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_476 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_477 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_478 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_479 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_480 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_481 = or(_vc_sel_T_473, _vc_sel_T_474)
node _vc_sel_T_482 = or(_vc_sel_T_481, _vc_sel_T_475)
node _vc_sel_T_483 = or(_vc_sel_T_482, _vc_sel_T_476)
node _vc_sel_T_484 = or(_vc_sel_T_483, _vc_sel_T_477)
node _vc_sel_T_485 = or(_vc_sel_T_484, _vc_sel_T_478)
node _vc_sel_T_486 = or(_vc_sel_T_485, _vc_sel_T_479)
node _vc_sel_T_487 = or(_vc_sel_T_486, _vc_sel_T_480)
wire _vc_sel_WIRE_35 : UInt<1>
connect _vc_sel_WIRE_35, _vc_sel_T_487
connect _vc_sel_WIRE_27[7], _vc_sel_WIRE_35
connect vc_sel.`3`, _vc_sel_WIRE_27
node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1])
node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2])
node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3])
node _channel_oh_T_3 = or(_channel_oh_T_2, vc_sel.`0`[4])
node _channel_oh_T_4 = or(_channel_oh_T_3, vc_sel.`0`[5])
node _channel_oh_T_5 = or(_channel_oh_T_4, vc_sel.`0`[6])
node channel_oh_0 = or(_channel_oh_T_5, vc_sel.`0`[7])
node _channel_oh_T_6 = or(vc_sel.`1`[0], vc_sel.`1`[1])
node _channel_oh_T_7 = or(_channel_oh_T_6, vc_sel.`1`[2])
node _channel_oh_T_8 = or(_channel_oh_T_7, vc_sel.`1`[3])
node _channel_oh_T_9 = or(_channel_oh_T_8, vc_sel.`1`[4])
node _channel_oh_T_10 = or(_channel_oh_T_9, vc_sel.`1`[5])
node _channel_oh_T_11 = or(_channel_oh_T_10, vc_sel.`1`[6])
node channel_oh_1 = or(_channel_oh_T_11, vc_sel.`1`[7])
node _channel_oh_T_12 = or(vc_sel.`2`[0], vc_sel.`2`[1])
node _channel_oh_T_13 = or(_channel_oh_T_12, vc_sel.`2`[2])
node _channel_oh_T_14 = or(_channel_oh_T_13, vc_sel.`2`[3])
node _channel_oh_T_15 = or(_channel_oh_T_14, vc_sel.`2`[4])
node _channel_oh_T_16 = or(_channel_oh_T_15, vc_sel.`2`[5])
node _channel_oh_T_17 = or(_channel_oh_T_16, vc_sel.`2`[6])
node channel_oh_2 = or(_channel_oh_T_17, vc_sel.`2`[7])
node _channel_oh_T_18 = or(vc_sel.`3`[0], vc_sel.`3`[1])
node _channel_oh_T_19 = or(_channel_oh_T_18, vc_sel.`3`[2])
node _channel_oh_T_20 = or(_channel_oh_T_19, vc_sel.`3`[3])
node _channel_oh_T_21 = or(_channel_oh_T_20, vc_sel.`3`[4])
node _channel_oh_T_22 = or(_channel_oh_T_21, vc_sel.`3`[5])
node _channel_oh_T_23 = or(_channel_oh_T_22, vc_sel.`3`[6])
node channel_oh_3 = or(_channel_oh_T_23, vc_sel.`3`[7])
node virt_channel_lo_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0])
node virt_channel_lo_hi = cat(vc_sel.`0`[3], vc_sel.`0`[2])
node virt_channel_lo = cat(virt_channel_lo_hi, virt_channel_lo_lo)
node virt_channel_hi_lo = cat(vc_sel.`0`[5], vc_sel.`0`[4])
node virt_channel_hi_hi = cat(vc_sel.`0`[7], vc_sel.`0`[6])
node virt_channel_hi = cat(virt_channel_hi_hi, virt_channel_hi_lo)
node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo)
node virt_channel_hi_1 = bits(_virt_channel_T, 7, 4)
node virt_channel_lo_1 = bits(_virt_channel_T, 3, 0)
node _virt_channel_T_1 = orr(virt_channel_hi_1)
node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1)
node virt_channel_hi_2 = bits(_virt_channel_T_2, 3, 2)
node virt_channel_lo_2 = bits(_virt_channel_T_2, 1, 0)
node _virt_channel_T_3 = orr(virt_channel_hi_2)
node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2)
node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1)
node _virt_channel_T_6 = cat(_virt_channel_T_3, _virt_channel_T_5)
node _virt_channel_T_7 = cat(_virt_channel_T_1, _virt_channel_T_6)
node virt_channel_lo_lo_1 = cat(vc_sel.`1`[1], vc_sel.`1`[0])
node virt_channel_lo_hi_1 = cat(vc_sel.`1`[3], vc_sel.`1`[2])
node virt_channel_lo_3 = cat(virt_channel_lo_hi_1, virt_channel_lo_lo_1)
node virt_channel_hi_lo_1 = cat(vc_sel.`1`[5], vc_sel.`1`[4])
node virt_channel_hi_hi_1 = cat(vc_sel.`1`[7], vc_sel.`1`[6])
node virt_channel_hi_3 = cat(virt_channel_hi_hi_1, virt_channel_hi_lo_1)
node _virt_channel_T_8 = cat(virt_channel_hi_3, virt_channel_lo_3)
node virt_channel_hi_4 = bits(_virt_channel_T_8, 7, 4)
node virt_channel_lo_4 = bits(_virt_channel_T_8, 3, 0)
node _virt_channel_T_9 = orr(virt_channel_hi_4)
node _virt_channel_T_10 = or(virt_channel_hi_4, virt_channel_lo_4)
node virt_channel_hi_5 = bits(_virt_channel_T_10, 3, 2)
node virt_channel_lo_5 = bits(_virt_channel_T_10, 1, 0)
node _virt_channel_T_11 = orr(virt_channel_hi_5)
node _virt_channel_T_12 = or(virt_channel_hi_5, virt_channel_lo_5)
node _virt_channel_T_13 = bits(_virt_channel_T_12, 1, 1)
node _virt_channel_T_14 = cat(_virt_channel_T_11, _virt_channel_T_13)
node _virt_channel_T_15 = cat(_virt_channel_T_9, _virt_channel_T_14)
node virt_channel_lo_lo_2 = cat(vc_sel.`2`[1], vc_sel.`2`[0])
node virt_channel_lo_hi_2 = cat(vc_sel.`2`[3], vc_sel.`2`[2])
node virt_channel_lo_6 = cat(virt_channel_lo_hi_2, virt_channel_lo_lo_2)
node virt_channel_hi_lo_2 = cat(vc_sel.`2`[5], vc_sel.`2`[4])
node virt_channel_hi_hi_2 = cat(vc_sel.`2`[7], vc_sel.`2`[6])
node virt_channel_hi_6 = cat(virt_channel_hi_hi_2, virt_channel_hi_lo_2)
node _virt_channel_T_16 = cat(virt_channel_hi_6, virt_channel_lo_6)
node virt_channel_hi_7 = bits(_virt_channel_T_16, 7, 4)
node virt_channel_lo_7 = bits(_virt_channel_T_16, 3, 0)
node _virt_channel_T_17 = orr(virt_channel_hi_7)
node _virt_channel_T_18 = or(virt_channel_hi_7, virt_channel_lo_7)
node virt_channel_hi_8 = bits(_virt_channel_T_18, 3, 2)
node virt_channel_lo_8 = bits(_virt_channel_T_18, 1, 0)
node _virt_channel_T_19 = orr(virt_channel_hi_8)
node _virt_channel_T_20 = or(virt_channel_hi_8, virt_channel_lo_8)
node _virt_channel_T_21 = bits(_virt_channel_T_20, 1, 1)
node _virt_channel_T_22 = cat(_virt_channel_T_19, _virt_channel_T_21)
node _virt_channel_T_23 = cat(_virt_channel_T_17, _virt_channel_T_22)
node virt_channel_lo_lo_3 = cat(vc_sel.`3`[1], vc_sel.`3`[0])
node virt_channel_lo_hi_3 = cat(vc_sel.`3`[3], vc_sel.`3`[2])
node virt_channel_lo_9 = cat(virt_channel_lo_hi_3, virt_channel_lo_lo_3)
node virt_channel_hi_lo_3 = cat(vc_sel.`3`[5], vc_sel.`3`[4])
node virt_channel_hi_hi_3 = cat(vc_sel.`3`[7], vc_sel.`3`[6])
node virt_channel_hi_9 = cat(virt_channel_hi_hi_3, virt_channel_hi_lo_3)
node _virt_channel_T_24 = cat(virt_channel_hi_9, virt_channel_lo_9)
node virt_channel_hi_10 = bits(_virt_channel_T_24, 7, 4)
node virt_channel_lo_10 = bits(_virt_channel_T_24, 3, 0)
node _virt_channel_T_25 = orr(virt_channel_hi_10)
node _virt_channel_T_26 = or(virt_channel_hi_10, virt_channel_lo_10)
node virt_channel_hi_11 = bits(_virt_channel_T_26, 3, 2)
node virt_channel_lo_11 = bits(_virt_channel_T_26, 1, 0)
node _virt_channel_T_27 = orr(virt_channel_hi_11)
node _virt_channel_T_28 = or(virt_channel_hi_11, virt_channel_lo_11)
node _virt_channel_T_29 = bits(_virt_channel_T_28, 1, 1)
node _virt_channel_T_30 = cat(_virt_channel_T_27, _virt_channel_T_29)
node _virt_channel_T_31 = cat(_virt_channel_T_25, _virt_channel_T_30)
node _virt_channel_T_32 = mux(channel_oh_0, _virt_channel_T_7, UInt<1>(0h0))
node _virt_channel_T_33 = mux(channel_oh_1, _virt_channel_T_15, UInt<1>(0h0))
node _virt_channel_T_34 = mux(channel_oh_2, _virt_channel_T_23, UInt<1>(0h0))
node _virt_channel_T_35 = mux(channel_oh_3, _virt_channel_T_31, UInt<1>(0h0))
node _virt_channel_T_36 = or(_virt_channel_T_32, _virt_channel_T_33)
node _virt_channel_T_37 = or(_virt_channel_T_36, _virt_channel_T_34)
node _virt_channel_T_38 = or(_virt_channel_T_37, _virt_channel_T_35)
wire virt_channel : UInt<3>
connect virt_channel, _virt_channel_T_38
node _T_119 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
when _T_119 :
connect salloc_outs[0].out_vid, virt_channel
node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_payload_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_payload_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_payload_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _salloc_outs_0_flit_payload_T_8 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_9 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_10 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_11 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_12 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_13 = mux(_salloc_outs_0_flit_payload_T_5, input_buffer.io.deq[5].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_14 = mux(_salloc_outs_0_flit_payload_T_6, input_buffer.io.deq[6].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_15 = mux(_salloc_outs_0_flit_payload_T_7, input_buffer.io.deq[7].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_16 = or(_salloc_outs_0_flit_payload_T_8, _salloc_outs_0_flit_payload_T_9)
node _salloc_outs_0_flit_payload_T_17 = or(_salloc_outs_0_flit_payload_T_16, _salloc_outs_0_flit_payload_T_10)
node _salloc_outs_0_flit_payload_T_18 = or(_salloc_outs_0_flit_payload_T_17, _salloc_outs_0_flit_payload_T_11)
node _salloc_outs_0_flit_payload_T_19 = or(_salloc_outs_0_flit_payload_T_18, _salloc_outs_0_flit_payload_T_12)
node _salloc_outs_0_flit_payload_T_20 = or(_salloc_outs_0_flit_payload_T_19, _salloc_outs_0_flit_payload_T_13)
node _salloc_outs_0_flit_payload_T_21 = or(_salloc_outs_0_flit_payload_T_20, _salloc_outs_0_flit_payload_T_14)
node _salloc_outs_0_flit_payload_T_22 = or(_salloc_outs_0_flit_payload_T_21, _salloc_outs_0_flit_payload_T_15)
wire _salloc_outs_0_flit_payload_WIRE : UInt<73>
connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_22
connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE
node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_head_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_head_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_head_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _salloc_outs_0_flit_head_T_8 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_9 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_10 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_11 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_12 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_13 = mux(_salloc_outs_0_flit_head_T_5, input_buffer.io.deq[5].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_14 = mux(_salloc_outs_0_flit_head_T_6, input_buffer.io.deq[6].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_15 = mux(_salloc_outs_0_flit_head_T_7, input_buffer.io.deq[7].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_16 = or(_salloc_outs_0_flit_head_T_8, _salloc_outs_0_flit_head_T_9)
node _salloc_outs_0_flit_head_T_17 = or(_salloc_outs_0_flit_head_T_16, _salloc_outs_0_flit_head_T_10)
node _salloc_outs_0_flit_head_T_18 = or(_salloc_outs_0_flit_head_T_17, _salloc_outs_0_flit_head_T_11)
node _salloc_outs_0_flit_head_T_19 = or(_salloc_outs_0_flit_head_T_18, _salloc_outs_0_flit_head_T_12)
node _salloc_outs_0_flit_head_T_20 = or(_salloc_outs_0_flit_head_T_19, _salloc_outs_0_flit_head_T_13)
node _salloc_outs_0_flit_head_T_21 = or(_salloc_outs_0_flit_head_T_20, _salloc_outs_0_flit_head_T_14)
node _salloc_outs_0_flit_head_T_22 = or(_salloc_outs_0_flit_head_T_21, _salloc_outs_0_flit_head_T_15)
wire _salloc_outs_0_flit_head_WIRE : UInt<1>
connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_22
connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE
node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_tail_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_tail_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_tail_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _salloc_outs_0_flit_tail_T_8 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_9 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_10 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_11 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_12 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_13 = mux(_salloc_outs_0_flit_tail_T_5, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_14 = mux(_salloc_outs_0_flit_tail_T_6, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_15 = mux(_salloc_outs_0_flit_tail_T_7, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_16 = or(_salloc_outs_0_flit_tail_T_8, _salloc_outs_0_flit_tail_T_9)
node _salloc_outs_0_flit_tail_T_17 = or(_salloc_outs_0_flit_tail_T_16, _salloc_outs_0_flit_tail_T_10)
node _salloc_outs_0_flit_tail_T_18 = or(_salloc_outs_0_flit_tail_T_17, _salloc_outs_0_flit_tail_T_11)
node _salloc_outs_0_flit_tail_T_19 = or(_salloc_outs_0_flit_tail_T_18, _salloc_outs_0_flit_tail_T_12)
node _salloc_outs_0_flit_tail_T_20 = or(_salloc_outs_0_flit_tail_T_19, _salloc_outs_0_flit_tail_T_13)
node _salloc_outs_0_flit_tail_T_21 = or(_salloc_outs_0_flit_tail_T_20, _salloc_outs_0_flit_tail_T_14)
node _salloc_outs_0_flit_tail_T_22 = or(_salloc_outs_0_flit_tail_T_21, _salloc_outs_0_flit_tail_T_15)
wire _salloc_outs_0_flit_tail_WIRE : UInt<1>
connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_22
connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE
node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_flow_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_flow_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_flow_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}
node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9)
node _salloc_outs_0_flit_flow_T_17 = or(_salloc_outs_0_flit_flow_T_16, _salloc_outs_0_flit_flow_T_10)
node _salloc_outs_0_flit_flow_T_18 = or(_salloc_outs_0_flit_flow_T_17, _salloc_outs_0_flit_flow_T_11)
node _salloc_outs_0_flit_flow_T_19 = or(_salloc_outs_0_flit_flow_T_18, _salloc_outs_0_flit_flow_T_12)
node _salloc_outs_0_flit_flow_T_20 = or(_salloc_outs_0_flit_flow_T_19, _salloc_outs_0_flit_flow_T_13)
node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_20, _salloc_outs_0_flit_flow_T_14)
node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_15)
wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_22
connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1
node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_26 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_27 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_28 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_29 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_30 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_31 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24)
node _salloc_outs_0_flit_flow_T_32 = or(_salloc_outs_0_flit_flow_T_31, _salloc_outs_0_flit_flow_T_25)
node _salloc_outs_0_flit_flow_T_33 = or(_salloc_outs_0_flit_flow_T_32, _salloc_outs_0_flit_flow_T_26)
node _salloc_outs_0_flit_flow_T_34 = or(_salloc_outs_0_flit_flow_T_33, _salloc_outs_0_flit_flow_T_27)
node _salloc_outs_0_flit_flow_T_35 = or(_salloc_outs_0_flit_flow_T_34, _salloc_outs_0_flit_flow_T_28)
node _salloc_outs_0_flit_flow_T_36 = or(_salloc_outs_0_flit_flow_T_35, _salloc_outs_0_flit_flow_T_29)
node _salloc_outs_0_flit_flow_T_37 = or(_salloc_outs_0_flit_flow_T_36, _salloc_outs_0_flit_flow_T_30)
wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<5>
connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_37
connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2
node _salloc_outs_0_flit_flow_T_38 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_39 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_40 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_41 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_42 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_43 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_44 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_45 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_38, _salloc_outs_0_flit_flow_T_39)
node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_40)
node _salloc_outs_0_flit_flow_T_48 = or(_salloc_outs_0_flit_flow_T_47, _salloc_outs_0_flit_flow_T_41)
node _salloc_outs_0_flit_flow_T_49 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_42)
node _salloc_outs_0_flit_flow_T_50 = or(_salloc_outs_0_flit_flow_T_49, _salloc_outs_0_flit_flow_T_43)
node _salloc_outs_0_flit_flow_T_51 = or(_salloc_outs_0_flit_flow_T_50, _salloc_outs_0_flit_flow_T_44)
node _salloc_outs_0_flit_flow_T_52 = or(_salloc_outs_0_flit_flow_T_51, _salloc_outs_0_flit_flow_T_45)
wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_52
connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3
node _salloc_outs_0_flit_flow_T_53 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_54 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_55 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_56 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_57 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_58 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_59 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_60 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_61 = or(_salloc_outs_0_flit_flow_T_53, _salloc_outs_0_flit_flow_T_54)
node _salloc_outs_0_flit_flow_T_62 = or(_salloc_outs_0_flit_flow_T_61, _salloc_outs_0_flit_flow_T_55)
node _salloc_outs_0_flit_flow_T_63 = or(_salloc_outs_0_flit_flow_T_62, _salloc_outs_0_flit_flow_T_56)
node _salloc_outs_0_flit_flow_T_64 = or(_salloc_outs_0_flit_flow_T_63, _salloc_outs_0_flit_flow_T_57)
node _salloc_outs_0_flit_flow_T_65 = or(_salloc_outs_0_flit_flow_T_64, _salloc_outs_0_flit_flow_T_58)
node _salloc_outs_0_flit_flow_T_66 = or(_salloc_outs_0_flit_flow_T_65, _salloc_outs_0_flit_flow_T_59)
node _salloc_outs_0_flit_flow_T_67 = or(_salloc_outs_0_flit_flow_T_66, _salloc_outs_0_flit_flow_T_60)
wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<5>
connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_67
connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4
node _salloc_outs_0_flit_flow_T_68 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_69 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_70 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_71 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_72 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_73 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_74 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_75 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_76 = or(_salloc_outs_0_flit_flow_T_68, _salloc_outs_0_flit_flow_T_69)
node _salloc_outs_0_flit_flow_T_77 = or(_salloc_outs_0_flit_flow_T_76, _salloc_outs_0_flit_flow_T_70)
node _salloc_outs_0_flit_flow_T_78 = or(_salloc_outs_0_flit_flow_T_77, _salloc_outs_0_flit_flow_T_71)
node _salloc_outs_0_flit_flow_T_79 = or(_salloc_outs_0_flit_flow_T_78, _salloc_outs_0_flit_flow_T_72)
node _salloc_outs_0_flit_flow_T_80 = or(_salloc_outs_0_flit_flow_T_79, _salloc_outs_0_flit_flow_T_73)
node _salloc_outs_0_flit_flow_T_81 = or(_salloc_outs_0_flit_flow_T_80, _salloc_outs_0_flit_flow_T_74)
node _salloc_outs_0_flit_flow_T_82 = or(_salloc_outs_0_flit_flow_T_81, _salloc_outs_0_flit_flow_T_75)
wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<3>
connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_82
connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5
connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE
else :
invalidate salloc_outs[0].out_vid
invalidate salloc_outs[0].flit.virt_channel_id
invalidate salloc_outs[0].flit.flow.egress_node_id
invalidate salloc_outs[0].flit.flow.egress_node
invalidate salloc_outs[0].flit.flow.ingress_node_id
invalidate salloc_outs[0].flit.flow.ingress_node
invalidate salloc_outs[0].flit.flow.vnet_id
invalidate salloc_outs[0].flit.payload
invalidate salloc_outs[0].flit.tail
invalidate salloc_outs[0].flit.head
invalidate salloc_outs[0].flit.virt_channel_id
connect io.out[0].valid, salloc_outs[0].valid
connect io.out[0].bits.flit, salloc_outs[0].flit
connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid
connect states[0].vc_sel.`0`[0], UInt<1>(0h0)
connect states[0].vc_sel.`0`[1], UInt<1>(0h0)
connect states[0].vc_sel.`0`[2], UInt<1>(0h0)
connect states[0].vc_sel.`0`[3], UInt<1>(0h0)
connect states[0].vc_sel.`0`[4], UInt<1>(0h0)
connect states[0].vc_sel.`0`[5], UInt<1>(0h0)
connect states[0].vc_sel.`0`[6], UInt<1>(0h0)
connect states[0].vc_sel.`0`[7], UInt<1>(0h0)
connect states[0].vc_sel.`1`[0], UInt<1>(0h0)
connect states[0].vc_sel.`3`[0], UInt<1>(0h0)
connect states[0].vc_sel.`3`[1], UInt<1>(0h0)
connect states[0].vc_sel.`3`[2], UInt<1>(0h0)
connect states[0].vc_sel.`3`[3], UInt<1>(0h0)
connect states[0].vc_sel.`3`[4], UInt<1>(0h0)
connect states[0].vc_sel.`3`[5], UInt<1>(0h0)
connect states[0].vc_sel.`3`[6], UInt<1>(0h0)
connect states[0].vc_sel.`3`[7], UInt<1>(0h0)
connect states[1].vc_sel.`0`[0], UInt<1>(0h0)
connect states[1].vc_sel.`0`[1], UInt<1>(0h0)
connect states[1].vc_sel.`0`[2], UInt<1>(0h0)
connect states[1].vc_sel.`0`[3], UInt<1>(0h0)
connect states[1].vc_sel.`0`[4], UInt<1>(0h0)
connect states[1].vc_sel.`0`[5], UInt<1>(0h0)
connect states[1].vc_sel.`0`[6], UInt<1>(0h0)
connect states[1].vc_sel.`0`[7], UInt<1>(0h0)
connect states[1].vc_sel.`1`[0], UInt<1>(0h0)
connect states[1].vc_sel.`3`[0], UInt<1>(0h0)
connect states[1].vc_sel.`3`[1], UInt<1>(0h0)
connect states[1].vc_sel.`3`[2], UInt<1>(0h0)
connect states[1].vc_sel.`3`[3], UInt<1>(0h0)
connect states[1].vc_sel.`3`[4], UInt<1>(0h0)
connect states[1].vc_sel.`3`[5], UInt<1>(0h0)
connect states[1].vc_sel.`3`[6], UInt<1>(0h0)
connect states[1].vc_sel.`3`[7], UInt<1>(0h0)
connect states[2].vc_sel.`0`[0], UInt<1>(0h0)
connect states[2].vc_sel.`0`[1], UInt<1>(0h0)
connect states[2].vc_sel.`0`[2], UInt<1>(0h0)
connect states[2].vc_sel.`0`[3], UInt<1>(0h0)
connect states[2].vc_sel.`0`[4], UInt<1>(0h0)
connect states[2].vc_sel.`0`[5], UInt<1>(0h0)
connect states[2].vc_sel.`0`[6], UInt<1>(0h0)
connect states[2].vc_sel.`0`[7], UInt<1>(0h0)
connect states[2].vc_sel.`1`[0], UInt<1>(0h0)
connect states[2].vc_sel.`3`[0], UInt<1>(0h0)
connect states[2].vc_sel.`3`[1], UInt<1>(0h0)
connect states[2].vc_sel.`3`[2], UInt<1>(0h0)
connect states[2].vc_sel.`3`[3], UInt<1>(0h0)
connect states[2].vc_sel.`3`[4], UInt<1>(0h0)
connect states[2].vc_sel.`3`[5], UInt<1>(0h0)
connect states[2].vc_sel.`3`[6], UInt<1>(0h0)
connect states[2].vc_sel.`3`[7], UInt<1>(0h0)
connect states[3].vc_sel.`0`[0], UInt<1>(0h0)
connect states[3].vc_sel.`0`[1], UInt<1>(0h0)
connect states[3].vc_sel.`0`[2], UInt<1>(0h0)
connect states[3].vc_sel.`0`[3], UInt<1>(0h0)
connect states[3].vc_sel.`0`[4], UInt<1>(0h0)
connect states[3].vc_sel.`0`[5], UInt<1>(0h0)
connect states[3].vc_sel.`0`[6], UInt<1>(0h0)
connect states[3].vc_sel.`0`[7], UInt<1>(0h0)
connect states[3].vc_sel.`1`[0], UInt<1>(0h0)
connect states[3].vc_sel.`3`[0], UInt<1>(0h0)
connect states[3].vc_sel.`3`[1], UInt<1>(0h0)
connect states[3].vc_sel.`3`[2], UInt<1>(0h0)
connect states[3].vc_sel.`3`[3], UInt<1>(0h0)
connect states[3].vc_sel.`3`[4], UInt<1>(0h0)
connect states[3].vc_sel.`3`[5], UInt<1>(0h0)
connect states[3].vc_sel.`3`[6], UInt<1>(0h0)
connect states[3].vc_sel.`3`[7], UInt<1>(0h0)
connect states[4].vc_sel.`0`[0], UInt<1>(0h0)
connect states[4].vc_sel.`0`[1], UInt<1>(0h0)
connect states[4].vc_sel.`0`[2], UInt<1>(0h0)
connect states[4].vc_sel.`0`[3], UInt<1>(0h0)
connect states[4].vc_sel.`0`[4], UInt<1>(0h0)
connect states[4].vc_sel.`0`[5], UInt<1>(0h0)
connect states[4].vc_sel.`0`[6], UInt<1>(0h0)
connect states[4].vc_sel.`0`[7], UInt<1>(0h0)
connect states[4].vc_sel.`1`[0], UInt<1>(0h0)
connect states[4].vc_sel.`3`[0], UInt<1>(0h0)
connect states[4].vc_sel.`3`[1], UInt<1>(0h0)
connect states[4].vc_sel.`3`[2], UInt<1>(0h0)
connect states[4].vc_sel.`3`[3], UInt<1>(0h0)
connect states[4].vc_sel.`3`[4], UInt<1>(0h0)
connect states[4].vc_sel.`3`[5], UInt<1>(0h0)
connect states[4].vc_sel.`3`[6], UInt<1>(0h0)
connect states[4].vc_sel.`3`[7], UInt<1>(0h0)
connect states[5].vc_sel.`0`[0], UInt<1>(0h0)
connect states[5].vc_sel.`0`[1], UInt<1>(0h0)
connect states[5].vc_sel.`0`[2], UInt<1>(0h0)
connect states[5].vc_sel.`0`[3], UInt<1>(0h0)
connect states[5].vc_sel.`0`[4], UInt<1>(0h0)
connect states[5].vc_sel.`0`[5], UInt<1>(0h0)
connect states[5].vc_sel.`0`[6], UInt<1>(0h0)
connect states[5].vc_sel.`0`[7], UInt<1>(0h0)
connect states[5].vc_sel.`1`[0], UInt<1>(0h0)
connect states[5].vc_sel.`3`[0], UInt<1>(0h0)
connect states[5].vc_sel.`3`[1], UInt<1>(0h0)
connect states[5].vc_sel.`3`[2], UInt<1>(0h0)
connect states[5].vc_sel.`3`[3], UInt<1>(0h0)
connect states[5].vc_sel.`3`[4], UInt<1>(0h0)
connect states[5].vc_sel.`3`[5], UInt<1>(0h0)
connect states[5].vc_sel.`3`[6], UInt<1>(0h0)
connect states[5].vc_sel.`3`[7], UInt<1>(0h0)
connect states[6].vc_sel.`0`[0], UInt<1>(0h0)
connect states[6].vc_sel.`0`[1], UInt<1>(0h0)
connect states[6].vc_sel.`0`[2], UInt<1>(0h0)
connect states[6].vc_sel.`0`[3], UInt<1>(0h0)
connect states[6].vc_sel.`0`[4], UInt<1>(0h0)
connect states[6].vc_sel.`0`[5], UInt<1>(0h0)
connect states[6].vc_sel.`0`[6], UInt<1>(0h0)
connect states[6].vc_sel.`0`[7], UInt<1>(0h0)
connect states[6].vc_sel.`1`[0], UInt<1>(0h0)
connect states[6].vc_sel.`3`[0], UInt<1>(0h0)
connect states[6].vc_sel.`3`[1], UInt<1>(0h0)
connect states[6].vc_sel.`3`[2], UInt<1>(0h0)
connect states[6].vc_sel.`3`[3], UInt<1>(0h0)
connect states[6].vc_sel.`3`[4], UInt<1>(0h0)
connect states[6].vc_sel.`3`[5], UInt<1>(0h0)
connect states[6].vc_sel.`3`[6], UInt<1>(0h0)
connect states[6].vc_sel.`3`[7], UInt<1>(0h0)
connect states[7].vc_sel.`0`[0], UInt<1>(0h0)
connect states[7].vc_sel.`0`[1], UInt<1>(0h0)
connect states[7].vc_sel.`0`[2], UInt<1>(0h0)
connect states[7].vc_sel.`0`[3], UInt<1>(0h0)
connect states[7].vc_sel.`0`[4], UInt<1>(0h0)
connect states[7].vc_sel.`0`[5], UInt<1>(0h0)
connect states[7].vc_sel.`0`[6], UInt<1>(0h0)
connect states[7].vc_sel.`0`[7], UInt<1>(0h0)
connect states[7].vc_sel.`1`[0], UInt<1>(0h0)
connect states[7].vc_sel.`3`[0], UInt<1>(0h0)
connect states[7].vc_sel.`3`[1], UInt<1>(0h0)
connect states[7].vc_sel.`3`[2], UInt<1>(0h0)
connect states[7].vc_sel.`3`[3], UInt<1>(0h0)
connect states[7].vc_sel.`3`[4], UInt<1>(0h0)
connect states[7].vc_sel.`3`[5], UInt<1>(0h0)
connect states[7].vc_sel.`3`[6], UInt<1>(0h0)
connect states[7].vc_sel.`3`[7], UInt<1>(0h0)
node _T_120 = asUInt(reset)
when _T_120 :
connect states[0].g, UInt<3>(0h0)
connect states[1].g, UInt<3>(0h0)
connect states[2].g, UInt<3>(0h0)
connect states[3].g, UInt<3>(0h0)
connect states[4].g, UInt<3>(0h0)
connect states[5].g, UInt<3>(0h0)
connect states[6].g, UInt<3>(0h0)
connect states[7].g, UInt<3>(0h0) | module InputUnit_59( // @[InputUnit.scala:158:7]
input clock, // @[InputUnit.scala:158:7]
input reset, // @[InputUnit.scala:158:7]
output [2:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14]
output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
output [4:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [4:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_2, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_3, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_4, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_5, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_6, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_7, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_2, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_3, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_4, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_5, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_6, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_7, // @[InputUnit.scala:170:14]
input io_vcalloc_req_ready, // @[InputUnit.scala:170:14]
output io_vcalloc_req_valid, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_2, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_3, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_4, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_5, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_6, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_7, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_2, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_3, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_4, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_5, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_6, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_7, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_2, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_3, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_4, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_5, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_6, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_7, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_2, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_3, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_4, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_5, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_6, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_7, // @[InputUnit.scala:170:14]
input io_salloc_req_0_ready, // @[InputUnit.scala:170:14]
output io_salloc_req_0_valid, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14]
output io_out_0_valid, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14]
output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14]
output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14]
output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14]
output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14]
input io_in_flit_0_valid, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14]
input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14]
output [7:0] io_in_credit_return, // @[InputUnit.scala:170:14]
output [7:0] io_in_vc_free // @[InputUnit.scala:170:14]
);
wire vcalloc_vals_7; // @[InputUnit.scala:266:32]
wire vcalloc_vals_6; // @[InputUnit.scala:266:32]
wire vcalloc_vals_5; // @[InputUnit.scala:266:32]
wire vcalloc_vals_4; // @[InputUnit.scala:266:32]
wire vcalloc_vals_3; // @[InputUnit.scala:266:32]
wire vcalloc_vals_2; // @[InputUnit.scala:266:32]
wire vcalloc_vals_1; // @[InputUnit.scala:266:32]
wire vcalloc_vals_0; // @[InputUnit.scala:266:32]
wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_6_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_7_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26]
wire [7:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26]
wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_6_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_7_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29]
wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29]
wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28]
reg [2:0] states_0_g; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_1_2; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg [2:0] states_0_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_1_g; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_1_2; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg [2:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_2_g; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_2; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg [2:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_3_g; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_2; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg [2:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_4_g; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_2; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_5_g; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_2; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg [2:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_6_g; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_2; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg [2:0] states_6_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_6_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_6_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_6_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_6_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_7_g; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_2; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg [2:0] states_7_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_7_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_7_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_7_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_7_flow_egress_node_id; // @[InputUnit.scala:192:19]
wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30]
wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_6_valid = states_6_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_7_valid = states_7_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
reg [7:0] mask; // @[InputUnit.scala:250:21]
wire [7:0] _vcalloc_filter_T_3 = {vcalloc_vals_7, vcalloc_vals_6, vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, vcalloc_vals_2, vcalloc_vals_1, vcalloc_vals_0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32]
wire [15:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 16'h1 : _vcalloc_filter_T_3[1] ? 16'h2 : _vcalloc_filter_T_3[2] ? 16'h4 : _vcalloc_filter_T_3[3] ? 16'h8 : _vcalloc_filter_T_3[4] ? 16'h10 : _vcalloc_filter_T_3[5] ? 16'h20 : _vcalloc_filter_T_3[6] ? 16'h40 : _vcalloc_filter_T_3[7] ? 16'h80 : vcalloc_vals_0 ? 16'h100 : vcalloc_vals_1 ? 16'h200 : vcalloc_vals_2 ? 16'h400 : vcalloc_vals_3 ? 16'h800 : vcalloc_vals_4 ? 16'h1000 : vcalloc_vals_5 ? 16'h2000 : vcalloc_vals_6 ? 16'h4000 : {vcalloc_vals_7, 15'h0}; // @[OneHot.scala:85:71]
wire [7:0] vcalloc_sel = vcalloc_filter[7:0] | vcalloc_filter[15:8]; // @[Mux.scala:50:70]
wire io_vcalloc_req_valid_0 = vcalloc_vals_0 | vcalloc_vals_1 | vcalloc_vals_2 | vcalloc_vals_3 | vcalloc_vals_4 | vcalloc_vals_5 | vcalloc_vals_6 | vcalloc_vals_7; // @[package.scala:81:59]
assign vcalloc_vals_0 = states_0_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_2 = states_2_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_6 = states_6_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_7 = states_7_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
wire _GEN_1 = _GEN_0 & vcalloc_sel[0]; // @[Mux.scala:32:36]
wire _GEN_2 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36]
wire _GEN_3 = _GEN_0 & vcalloc_sel[2]; // @[Mux.scala:32:36]
wire _GEN_4 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36]
wire _GEN_5 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36]
wire _GEN_6 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36]
wire _GEN_7 = _GEN_0 & vcalloc_sel[6]; // @[Mux.scala:32:36]
wire _GEN_8 = _GEN_0 & vcalloc_sel[7]; // @[Mux.scala:32:36] |
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_212 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>}
node _io_out_d_T = mul(io.in_a, io.in_b)
node _io_out_d_T_1 = add(_io_out_d_T, io.in_c)
node _io_out_d_T_2 = tail(_io_out_d_T_1, 1)
node _io_out_d_T_3 = asSInt(_io_out_d_T_2)
connect io.out_d, _io_out_d_T_3 | module MacUnit_212( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [19:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54]
assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_4 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0))
node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1))
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3))
node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4))
node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6))
node _roundMagUp_T = and(roundingMode_min, io.in.sign)
node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0))
node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1)
node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2)
node adjustedSig = shl(io.in.sig, 0)
node doShiftSigDown1 = bits(adjustedSig, 26, 26)
wire common_expOut : UInt<9>
wire common_fractOut : UInt<23>
wire common_overflow : UInt<1>
wire common_totalUnderflow : UInt<1>
wire common_underflow : UInt<1>
wire common_inexact : UInt<1>
node _roundMask_T = bits(io.in.sExp, 8, 0)
node _roundMask_T_1 = not(_roundMask_T)
node roundMask_msb = bits(_roundMask_T_1, 8, 8)
node roundMask_lsbs = bits(_roundMask_T_1, 7, 0)
node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7)
node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0)
node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6)
node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0)
node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2)
node _roundMask_T_2 = bits(roundMask_shift, 63, 42)
node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0)
node _roundMask_T_4 = shl(UInt<8>(0hff), 8)
node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4)
node _roundMask_T_6 = shr(_roundMask_T_3, 8)
node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5)
node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0)
node _roundMask_T_9 = shl(_roundMask_T_8, 8)
node _roundMask_T_10 = not(_roundMask_T_5)
node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10)
node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11)
node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0)
node _roundMask_T_14 = shl(_roundMask_T_13, 4)
node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14)
node _roundMask_T_16 = shr(_roundMask_T_12, 4)
node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15)
node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0)
node _roundMask_T_19 = shl(_roundMask_T_18, 4)
node _roundMask_T_20 = not(_roundMask_T_15)
node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20)
node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21)
node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0)
node _roundMask_T_24 = shl(_roundMask_T_23, 2)
node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24)
node _roundMask_T_26 = shr(_roundMask_T_22, 2)
node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25)
node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0)
node _roundMask_T_29 = shl(_roundMask_T_28, 2)
node _roundMask_T_30 = not(_roundMask_T_25)
node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30)
node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31)
node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0)
node _roundMask_T_34 = shl(_roundMask_T_33, 1)
node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34)
node _roundMask_T_36 = shr(_roundMask_T_32, 1)
node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35)
node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0)
node _roundMask_T_39 = shl(_roundMask_T_38, 1)
node _roundMask_T_40 = not(_roundMask_T_35)
node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40)
node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41)
node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16)
node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0)
node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0)
node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0)
node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1)
node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47)
node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2)
node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0)
node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1)
node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51)
node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52)
node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4)
node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0)
node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1)
node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56)
node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57)
node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58)
node _roundMask_T_60 = not(_roundMask_T_59)
node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60)
node _roundMask_T_62 = not(_roundMask_T_61)
node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7))
node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6)
node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0)
node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3)
node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0)
node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0)
node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0)
node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1)
node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67)
node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2)
node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69)
node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0))
node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71)
node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0))
node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1)
node roundMask = cat(_roundMask_T_74, UInt<2>(0h3))
node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask)
node shiftedRoundMask = shr(_shiftedRoundMask_T, 1)
node _roundPosMask_T = not(shiftedRoundMask)
node roundPosMask = and(_roundPosMask_T, roundMask)
node _roundPosBit_T = and(adjustedSig, roundPosMask)
node roundPosBit = orr(_roundPosBit_T)
node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask)
node anyRoundExtra = orr(_anyRoundExtra_T)
node anyRound = or(roundPosBit, anyRoundExtra)
node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit)
node _roundIncr_T_2 = and(roundMagUp, anyRound)
node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2)
node _roundedSig_T = or(adjustedSig, roundMask)
node _roundedSig_T_1 = shr(_roundedSig_T, 2)
node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1))
node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit)
node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0))
node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4)
node _roundedSig_T_6 = shr(roundMask, 1)
node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0))
node _roundedSig_T_8 = not(_roundedSig_T_7)
node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8)
node _roundedSig_T_10 = not(roundMask)
node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10)
node _roundedSig_T_12 = shr(_roundedSig_T_11, 2)
node _roundedSig_T_13 = and(roundingMode_odd, anyRound)
node _roundedSig_T_14 = shr(roundPosMask, 1)
node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0))
node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15)
node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16)
node _sRoundedExp_T = shr(roundedSig, 24)
node _sRoundedExp_T_1 = cvt(_sRoundedExp_T)
node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1)
node _common_expOut_T = bits(sRoundedExp, 8, 0)
connect common_expOut, _common_expOut_T
node _common_fractOut_T = bits(roundedSig, 23, 1)
node _common_fractOut_T_1 = bits(roundedSig, 22, 0)
node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1)
connect common_fractOut, _common_fractOut_T_2
node _common_overflow_T = shr(sRoundedExp, 7)
node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3)))
connect common_overflow, _common_overflow_T_1
node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b)))
connect common_totalUnderflow, _common_totalUnderflow_T
node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2)
node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1)
node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1)
node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2)
node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T)
node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0)
node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2)
node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3)
node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit)
node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound)
node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2)
node _roundCarry_T = bits(roundedSig, 25, 25)
node _roundCarry_T_1 = bits(roundedSig, 24, 24)
node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1)
node _common_underflow_T = shr(io.in.sExp, 8)
node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0)))
node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1)
node _common_underflow_T_3 = bits(roundMask, 3, 3)
node _common_underflow_T_4 = bits(roundMask, 2, 2)
node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4)
node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5)
node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1))
node _common_underflow_T_8 = bits(roundMask, 4, 4)
node _common_underflow_T_9 = bits(roundMask, 3, 3)
node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9)
node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0))
node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11)
node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry)
node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit)
node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr)
node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0))
node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16)
node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17)
connect common_underflow, _common_underflow_T_18
node _common_inexact_T = or(common_totalUnderflow, anyRound)
connect common_inexact, _common_inexact_T
node isNaNOut = or(io.invalidExc, io.in.isNaN)
node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf)
node _commonCase_T = eq(isNaNOut, UInt<1>(0h0))
node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0))
node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1)
node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0))
node commonCase = and(_commonCase_T_2, _commonCase_T_3)
node overflow = and(commonCase, common_overflow)
node underflow = and(commonCase, common_underflow)
node _inexact_T = and(commonCase, common_inexact)
node inexact = or(overflow, _inexact_T)
node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp)
node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow)
node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd)
node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1)
node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0))
node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T)
node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp)
node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T)
node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign)
node _expOut_T = or(io.in.isZero, common_totalUnderflow)
node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0))
node _expOut_T_2 = not(_expOut_T_1)
node _expOut_T_3 = and(common_expOut, _expOut_T_2)
node _expOut_T_4 = not(UInt<9>(0h6b))
node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0))
node _expOut_T_6 = not(_expOut_T_5)
node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6)
node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0))
node _expOut_T_9 = not(_expOut_T_8)
node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9)
node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0))
node _expOut_T_12 = not(_expOut_T_11)
node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12)
node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0))
node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14)
node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0))
node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16)
node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0))
node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18)
node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0))
node expOut = or(_expOut_T_19, _expOut_T_20)
node _fractOut_T = or(isNaNOut, io.in.isZero)
node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow)
node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0))
node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut)
node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0))
node fractOut = or(_fractOut_T_3, _fractOut_T_4)
node _io_out_T = cat(signOut, expOut)
node _io_out_T_1 = cat(_io_out_T, fractOut)
connect io.out, _io_out_T_1
node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc)
node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow)
node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact)
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_4( // @[RoundAnyRawFNToRecFN.scala:48:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_detectTininess, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_detectTininess_0 = io_detectTininess; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20]
wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49]
wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22]
wire _common_underflow_T_7 = io_detectTininess_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :222:49]
wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33]
wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53]
wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53]
wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53]
wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53]
wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53]
wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53]
wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27]
wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66]
wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}]
wire roundMagUp = _roundMagUp_T | _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}]
wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57]
wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37]
wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31]
wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16]
wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31]
wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50]
wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31]
wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40]
wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49]
wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37]
wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21]
wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25]
wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26]
wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26]
wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26]
wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26]
wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26]
wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26]
wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26]
wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56]
wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22]
wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22]
wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22]
wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20]
wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20]
wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20]
wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20]
wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20]
wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20]
wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20]
wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20]
wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20]
wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20]
wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}]
wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}]
wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17]
wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56]
wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22]
wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22]
wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20]
wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20]
wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22]
wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20]
wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20]
wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58]
wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24]
wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24]
wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}]
wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41]
wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}]
wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28]
wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}]
wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40]
wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}]
wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42]
wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}]
wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36]
wire _GEN = roundingMode_near_even | roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38]
wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38]
assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38]
wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38]
assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38]
wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32]
assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32]
wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}]
wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29]
wire roundIncr = _roundIncr_T_1 | _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29]
wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32]
wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}]
wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}]
wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49]
wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30]
wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30]
wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35]
wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35]
wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}]
wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21]
wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32]
wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}]
wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}]
wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42]
wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67]
wire [25:0] _roundedSig_T_15 = _roundedSig_T_13 ? _roundedSig_T_14 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:{24,42,67}]
wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} | _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24]
wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47]
wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54]
wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}]
wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}]
assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37]
assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37]
wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27]
wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27]
assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27]
assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16]
wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30]
assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}]
assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50]
assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31]
assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31]
wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45]
wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44]
wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61]
wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}]
wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}]
wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63]
wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}]
wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}]
wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}]
wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29]
wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 | _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29]
wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27]
wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27]
wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27]
wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49]
wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}]
wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}]
wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57]
wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49]
wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71]
wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}]
wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30]
wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49]
wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49]
wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}]
wire _common_underflow_T_12 = _common_underflow_T_7 & _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:{49,77}, :223:34]
wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38]
wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45]
wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}]
wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60]
wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27]
assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76]
assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40]
assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49]
assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49]
wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34]
wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22]
wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36]
wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}]
wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64]
wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}]
wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32]
wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32]
wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43]
wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}]
wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}]
wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20]
wire _pegMinNonzeroMagOut_T_1 = roundMagUp | roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60]
wire pegMinNonzeroMagOut = _pegMinNonzeroMagOut_T & _pegMinNonzeroMagOut_T_1; // @[RoundAnyRawFNToRecFN.scala:245:{20,45,60}]
wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42]
wire pegMaxFiniteMagOut = overflow & _pegMaxFiniteMagOut_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :246:{39,42}]
wire _notNaN_isInfOut_T = overflow & overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:238:32, :243:60, :248:45]
wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}]
wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22]
wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32]
wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}]
wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}]
wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14]
wire [8:0] _expOut_T_5 = pegMinNonzeroMagOut ? 9'h194 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :257:18]
wire [8:0] _expOut_T_6 = ~_expOut_T_5; // @[RoundAnyRawFNToRecFN.scala:257:{14,18}]
wire [8:0] _expOut_T_7 = _expOut_T_3 & _expOut_T_6; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17, :257:14]
wire [8:0] _expOut_T_8 = {1'h0, pegMaxFiniteMagOut, 7'h0}; // @[RoundAnyRawFNToRecFN.scala:246:39, :261:18]
wire [8:0] _expOut_T_9 = ~_expOut_T_8; // @[RoundAnyRawFNToRecFN.scala:261:{14,18}]
wire [8:0] _expOut_T_10 = _expOut_T_7 & _expOut_T_9; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17, :261:14]
wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18]
wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}]
wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14]
wire [8:0] _expOut_T_14 = pegMinNonzeroMagOut ? 9'h6B : 9'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :269:16]
wire [8:0] _expOut_T_15 = _expOut_T_13 | _expOut_T_14; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18, :269:16]
wire [8:0] _expOut_T_16 = pegMaxFiniteMagOut ? 9'h17F : 9'h0; // @[RoundAnyRawFNToRecFN.scala:246:39, :273:16]
wire [8:0] _expOut_T_17 = _expOut_T_15 | _expOut_T_16; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15, :273:16]
wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16]
wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16]
wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16]
wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16]
wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22]
wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}]
wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16]
wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16]
wire [22:0] _fractOut_T_4 = {23{pegMaxFiniteMagOut}}; // @[RoundAnyRawFNToRecFN.scala:246:39, :284:13]
wire [22:0] fractOut = _fractOut_T_3 | _fractOut_T_4; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11, :284:13]
wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23]
assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}]
assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33]
wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23]
wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}]
wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}]
assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IssueUnitCollapsing_3 :
input clock : Clock
input reset : Reset
output io : { flip dis_uops : { flip ready : UInt<1>, valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}[2], iss_uops : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}[2], flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}}[4], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<2>, flip fu_types : UInt<1>[10][2], flip brupdate : { b1 : { resolve_mask : UInt<12>, mispredict_mask : UInt<12>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip flush_pipeline : UInt<1>, flip squash_grant : UInt<1>, flip tsc_reg : UInt<64>}
wire _WIRE : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
wire _WIRE_1 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect _WIRE, io.dis_uops[0].bits
connect _WIRE.iw_issued, UInt<1>(0h0)
connect _WIRE.iw_issued_partial_agen, UInt<1>(0h0)
connect _WIRE.iw_issued_partial_dgen, UInt<1>(0h0)
connect _WIRE.iw_p1_bypass_hint, UInt<1>(0h0)
connect _WIRE.iw_p2_bypass_hint, UInt<1>(0h0)
connect _WIRE.iw_p3_bypass_hint, UInt<1>(0h0)
node prs1_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, io.dis_uops[0].bits.prs1)
node prs1_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, io.dis_uops[0].bits.prs1)
node prs1_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, io.dis_uops[0].bits.prs1)
node prs1_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, io.dis_uops[0].bits.prs1)
node prs2_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, io.dis_uops[0].bits.prs2)
node prs2_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, io.dis_uops[0].bits.prs2)
node prs2_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, io.dis_uops[0].bits.prs2)
node prs2_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, io.dis_uops[0].bits.prs2)
node prs3_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, io.dis_uops[0].bits.prs3)
node prs3_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, io.dis_uops[0].bits.prs3)
node prs3_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, io.dis_uops[0].bits.prs3)
node prs3_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, io.dis_uops[0].bits.prs3)
node prs1_wakeups_0 = and(io.wakeup_ports[0].valid, prs1_matches_0)
node prs1_wakeups_1 = and(io.wakeup_ports[1].valid, prs1_matches_1)
node prs1_wakeups_2 = and(io.wakeup_ports[2].valid, prs1_matches_2)
node prs1_wakeups_3 = and(io.wakeup_ports[3].valid, prs1_matches_3)
node prs2_wakeups_0 = and(io.wakeup_ports[0].valid, prs2_matches_0)
node prs2_wakeups_1 = and(io.wakeup_ports[1].valid, prs2_matches_1)
node prs2_wakeups_2 = and(io.wakeup_ports[2].valid, prs2_matches_2)
node prs2_wakeups_3 = and(io.wakeup_ports[3].valid, prs2_matches_3)
node prs3_wakeups_0 = and(io.wakeup_ports[0].valid, prs3_matches_0)
node prs3_wakeups_1 = and(io.wakeup_ports[1].valid, prs3_matches_1)
node prs3_wakeups_2 = and(io.wakeup_ports[2].valid, prs3_matches_2)
node prs3_wakeups_3 = and(io.wakeup_ports[3].valid, prs3_matches_3)
node prs1_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0)
node prs1_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1)
node prs1_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs1_matches_2)
node prs1_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs1_matches_3)
node prs2_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0)
node prs2_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1)
node prs2_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs2_matches_2)
node prs2_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs2_matches_3)
node _T = or(prs1_wakeups_0, prs1_wakeups_1)
node _T_1 = or(_T, prs1_wakeups_2)
node _T_2 = or(_T_1, prs1_wakeups_3)
when _T_2 :
connect _WIRE.prs1_busy, UInt<1>(0h0)
node _T_3 = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0))
node _T_4 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0))
node _T_5 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0))
node _T_6 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0))
node _T_7 = or(_T_3, _T_4)
node _T_8 = or(_T_7, _T_5)
node _T_9 = or(_T_8, _T_6)
wire _WIRE_2 : UInt<2>
connect _WIRE_2, _T_9
connect _WIRE.iw_p1_speculative_child, _WIRE_2
node _T_10 = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _T_11 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _T_12 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _T_13 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _T_14 = or(_T_10, _T_11)
node _T_15 = or(_T_14, _T_12)
node _T_16 = or(_T_15, _T_13)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_16
connect _WIRE.iw_p1_bypass_hint, _WIRE_3
node _T_17 = or(prs1_rebusys_0, prs1_rebusys_1)
node _T_18 = or(_T_17, prs1_rebusys_2)
node _T_19 = or(_T_18, prs1_rebusys_3)
node _T_20 = and(io.child_rebusys, io.dis_uops[0].bits.iw_p1_speculative_child)
node _T_21 = neq(_T_20, UInt<1>(0h0))
node _T_22 = or(_T_19, _T_21)
when _T_22 :
node _T_23 = eq(io.dis_uops[0].bits.lrs1_rtype, UInt<2>(0h0))
connect _WIRE.prs1_busy, _T_23
node _T_24 = or(prs2_wakeups_0, prs2_wakeups_1)
node _T_25 = or(_T_24, prs2_wakeups_2)
node _T_26 = or(_T_25, prs2_wakeups_3)
when _T_26 :
connect _WIRE.prs2_busy, UInt<1>(0h0)
node _T_27 = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0))
node _T_28 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0))
node _T_29 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0))
node _T_30 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0))
node _T_31 = or(_T_27, _T_28)
node _T_32 = or(_T_31, _T_29)
node _T_33 = or(_T_32, _T_30)
wire _WIRE_4 : UInt<2>
connect _WIRE_4, _T_33
connect _WIRE.iw_p2_speculative_child, _WIRE_4
node _T_34 = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _T_35 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _T_36 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _T_37 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _T_38 = or(_T_34, _T_35)
node _T_39 = or(_T_38, _T_36)
node _T_40 = or(_T_39, _T_37)
wire _WIRE_5 : UInt<1>
connect _WIRE_5, _T_40
connect _WIRE.iw_p2_bypass_hint, _WIRE_5
node _T_41 = or(prs2_rebusys_0, prs2_rebusys_1)
node _T_42 = or(_T_41, prs2_rebusys_2)
node _T_43 = or(_T_42, prs2_rebusys_3)
node _T_44 = and(io.child_rebusys, io.dis_uops[0].bits.iw_p2_speculative_child)
node _T_45 = neq(_T_44, UInt<1>(0h0))
node _T_46 = or(_T_43, _T_45)
when _T_46 :
node _T_47 = eq(io.dis_uops[0].bits.lrs2_rtype, UInt<2>(0h0))
connect _WIRE.prs2_busy, _T_47
node _T_48 = or(prs3_wakeups_0, prs3_wakeups_1)
node _T_49 = or(_T_48, prs3_wakeups_2)
node _T_50 = or(_T_49, prs3_wakeups_3)
when _T_50 :
connect _WIRE.prs3_busy, UInt<1>(0h0)
node _T_51 = mux(prs3_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _T_52 = mux(prs3_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _T_53 = mux(prs3_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _T_54 = mux(prs3_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _T_55 = or(_T_51, _T_52)
node _T_56 = or(_T_55, _T_53)
node _T_57 = or(_T_56, _T_54)
wire _WIRE_6 : UInt<1>
connect _WIRE_6, _T_57
connect _WIRE.iw_p3_bypass_hint, _WIRE_6
node _T_58 = eq(io.pred_wakeup_port.bits, io.dis_uops[0].bits.ppred)
node _T_59 = and(io.pred_wakeup_port.valid, _T_58)
when _T_59 :
connect _WIRE.ppred_busy, UInt<1>(0h0)
connect _WIRE_1, io.dis_uops[1].bits
connect _WIRE_1.iw_issued, UInt<1>(0h0)
connect _WIRE_1.iw_issued_partial_agen, UInt<1>(0h0)
connect _WIRE_1.iw_issued_partial_dgen, UInt<1>(0h0)
connect _WIRE_1.iw_p1_bypass_hint, UInt<1>(0h0)
connect _WIRE_1.iw_p2_bypass_hint, UInt<1>(0h0)
connect _WIRE_1.iw_p3_bypass_hint, UInt<1>(0h0)
node prs1_matches_0_1 = eq(io.wakeup_ports[0].bits.uop.pdst, io.dis_uops[1].bits.prs1)
node prs1_matches_1_1 = eq(io.wakeup_ports[1].bits.uop.pdst, io.dis_uops[1].bits.prs1)
node prs1_matches_2_1 = eq(io.wakeup_ports[2].bits.uop.pdst, io.dis_uops[1].bits.prs1)
node prs1_matches_3_1 = eq(io.wakeup_ports[3].bits.uop.pdst, io.dis_uops[1].bits.prs1)
node prs2_matches_0_1 = eq(io.wakeup_ports[0].bits.uop.pdst, io.dis_uops[1].bits.prs2)
node prs2_matches_1_1 = eq(io.wakeup_ports[1].bits.uop.pdst, io.dis_uops[1].bits.prs2)
node prs2_matches_2_1 = eq(io.wakeup_ports[2].bits.uop.pdst, io.dis_uops[1].bits.prs2)
node prs2_matches_3_1 = eq(io.wakeup_ports[3].bits.uop.pdst, io.dis_uops[1].bits.prs2)
node prs3_matches_0_1 = eq(io.wakeup_ports[0].bits.uop.pdst, io.dis_uops[1].bits.prs3)
node prs3_matches_1_1 = eq(io.wakeup_ports[1].bits.uop.pdst, io.dis_uops[1].bits.prs3)
node prs3_matches_2_1 = eq(io.wakeup_ports[2].bits.uop.pdst, io.dis_uops[1].bits.prs3)
node prs3_matches_3_1 = eq(io.wakeup_ports[3].bits.uop.pdst, io.dis_uops[1].bits.prs3)
node prs1_wakeups_0_1 = and(io.wakeup_ports[0].valid, prs1_matches_0_1)
node prs1_wakeups_1_1 = and(io.wakeup_ports[1].valid, prs1_matches_1_1)
node prs1_wakeups_2_1 = and(io.wakeup_ports[2].valid, prs1_matches_2_1)
node prs1_wakeups_3_1 = and(io.wakeup_ports[3].valid, prs1_matches_3_1)
node prs2_wakeups_0_1 = and(io.wakeup_ports[0].valid, prs2_matches_0_1)
node prs2_wakeups_1_1 = and(io.wakeup_ports[1].valid, prs2_matches_1_1)
node prs2_wakeups_2_1 = and(io.wakeup_ports[2].valid, prs2_matches_2_1)
node prs2_wakeups_3_1 = and(io.wakeup_ports[3].valid, prs2_matches_3_1)
node prs3_wakeups_0_1 = and(io.wakeup_ports[0].valid, prs3_matches_0_1)
node prs3_wakeups_1_1 = and(io.wakeup_ports[1].valid, prs3_matches_1_1)
node prs3_wakeups_2_1 = and(io.wakeup_ports[2].valid, prs3_matches_2_1)
node prs3_wakeups_3_1 = and(io.wakeup_ports[3].valid, prs3_matches_3_1)
node prs1_rebusys_0_1 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0_1)
node prs1_rebusys_1_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1_1)
node prs1_rebusys_2_1 = and(io.wakeup_ports[2].bits.rebusy, prs1_matches_2_1)
node prs1_rebusys_3_1 = and(io.wakeup_ports[3].bits.rebusy, prs1_matches_3_1)
node prs2_rebusys_0_1 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0_1)
node prs2_rebusys_1_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1_1)
node prs2_rebusys_2_1 = and(io.wakeup_ports[2].bits.rebusy, prs2_matches_2_1)
node prs2_rebusys_3_1 = and(io.wakeup_ports[3].bits.rebusy, prs2_matches_3_1)
node _T_60 = or(prs1_wakeups_0_1, prs1_wakeups_1_1)
node _T_61 = or(_T_60, prs1_wakeups_2_1)
node _T_62 = or(_T_61, prs1_wakeups_3_1)
when _T_62 :
connect _WIRE_1.prs1_busy, UInt<1>(0h0)
node _T_63 = mux(prs1_wakeups_0_1, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0))
node _T_64 = mux(prs1_wakeups_1_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0))
node _T_65 = mux(prs1_wakeups_2_1, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0))
node _T_66 = mux(prs1_wakeups_3_1, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0))
node _T_67 = or(_T_63, _T_64)
node _T_68 = or(_T_67, _T_65)
node _T_69 = or(_T_68, _T_66)
wire _WIRE_7 : UInt<2>
connect _WIRE_7, _T_69
connect _WIRE_1.iw_p1_speculative_child, _WIRE_7
node _T_70 = mux(prs1_wakeups_0_1, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _T_71 = mux(prs1_wakeups_1_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _T_72 = mux(prs1_wakeups_2_1, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _T_73 = mux(prs1_wakeups_3_1, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _T_74 = or(_T_70, _T_71)
node _T_75 = or(_T_74, _T_72)
node _T_76 = or(_T_75, _T_73)
wire _WIRE_8 : UInt<1>
connect _WIRE_8, _T_76
connect _WIRE_1.iw_p1_bypass_hint, _WIRE_8
node _T_77 = or(prs1_rebusys_0_1, prs1_rebusys_1_1)
node _T_78 = or(_T_77, prs1_rebusys_2_1)
node _T_79 = or(_T_78, prs1_rebusys_3_1)
node _T_80 = and(io.child_rebusys, io.dis_uops[1].bits.iw_p1_speculative_child)
node _T_81 = neq(_T_80, UInt<1>(0h0))
node _T_82 = or(_T_79, _T_81)
when _T_82 :
node _T_83 = eq(io.dis_uops[1].bits.lrs1_rtype, UInt<2>(0h0))
connect _WIRE_1.prs1_busy, _T_83
node _T_84 = or(prs2_wakeups_0_1, prs2_wakeups_1_1)
node _T_85 = or(_T_84, prs2_wakeups_2_1)
node _T_86 = or(_T_85, prs2_wakeups_3_1)
when _T_86 :
connect _WIRE_1.prs2_busy, UInt<1>(0h0)
node _T_87 = mux(prs2_wakeups_0_1, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0))
node _T_88 = mux(prs2_wakeups_1_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0))
node _T_89 = mux(prs2_wakeups_2_1, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0))
node _T_90 = mux(prs2_wakeups_3_1, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0))
node _T_91 = or(_T_87, _T_88)
node _T_92 = or(_T_91, _T_89)
node _T_93 = or(_T_92, _T_90)
wire _WIRE_9 : UInt<2>
connect _WIRE_9, _T_93
connect _WIRE_1.iw_p2_speculative_child, _WIRE_9
node _T_94 = mux(prs2_wakeups_0_1, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _T_95 = mux(prs2_wakeups_1_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _T_96 = mux(prs2_wakeups_2_1, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _T_97 = mux(prs2_wakeups_3_1, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _T_98 = or(_T_94, _T_95)
node _T_99 = or(_T_98, _T_96)
node _T_100 = or(_T_99, _T_97)
wire _WIRE_10 : UInt<1>
connect _WIRE_10, _T_100
connect _WIRE_1.iw_p2_bypass_hint, _WIRE_10
node _T_101 = or(prs2_rebusys_0_1, prs2_rebusys_1_1)
node _T_102 = or(_T_101, prs2_rebusys_2_1)
node _T_103 = or(_T_102, prs2_rebusys_3_1)
node _T_104 = and(io.child_rebusys, io.dis_uops[1].bits.iw_p2_speculative_child)
node _T_105 = neq(_T_104, UInt<1>(0h0))
node _T_106 = or(_T_103, _T_105)
when _T_106 :
node _T_107 = eq(io.dis_uops[1].bits.lrs2_rtype, UInt<2>(0h0))
connect _WIRE_1.prs2_busy, _T_107
node _T_108 = or(prs3_wakeups_0_1, prs3_wakeups_1_1)
node _T_109 = or(_T_108, prs3_wakeups_2_1)
node _T_110 = or(_T_109, prs3_wakeups_3_1)
when _T_110 :
connect _WIRE_1.prs3_busy, UInt<1>(0h0)
node _T_111 = mux(prs3_wakeups_0_1, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _T_112 = mux(prs3_wakeups_1_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _T_113 = mux(prs3_wakeups_2_1, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _T_114 = mux(prs3_wakeups_3_1, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _T_115 = or(_T_111, _T_112)
node _T_116 = or(_T_115, _T_113)
node _T_117 = or(_T_116, _T_114)
wire _WIRE_11 : UInt<1>
connect _WIRE_11, _T_117
connect _WIRE_1.iw_p3_bypass_hint, _WIRE_11
node _T_118 = eq(io.pred_wakeup_port.bits, io.dis_uops[1].bits.ppred)
node _T_119 = and(io.pred_wakeup_port.valid, _T_118)
when _T_119 :
connect _WIRE_1.ppred_busy, UInt<1>(0h0)
inst slots_0 of IssueSlot_36
connect slots_0.clock, clock
connect slots_0.reset, reset
inst slots_1 of IssueSlot_37
connect slots_1.clock, clock
connect slots_1.reset, reset
inst slots_2 of IssueSlot_38
connect slots_2.clock, clock
connect slots_2.reset, reset
inst slots_3 of IssueSlot_39
connect slots_3.clock, clock
connect slots_3.reset, reset
inst slots_4 of IssueSlot_40
connect slots_4.clock, clock
connect slots_4.reset, reset
inst slots_5 of IssueSlot_41
connect slots_5.clock, clock
connect slots_5.reset, reset
inst slots_6 of IssueSlot_42
connect slots_6.clock, clock
connect slots_6.reset, reset
inst slots_7 of IssueSlot_43
connect slots_7.clock, clock
connect slots_7.reset, reset
inst slots_8 of IssueSlot_44
connect slots_8.clock, clock
connect slots_8.reset, reset
inst slots_9 of IssueSlot_45
connect slots_9.clock, clock
connect slots_9.reset, reset
inst slots_10 of IssueSlot_46
connect slots_10.clock, clock
connect slots_10.reset, reset
inst slots_11 of IssueSlot_47
connect slots_11.clock, clock
connect slots_11.reset, reset
inst slots_12 of IssueSlot_48
connect slots_12.clock, clock
connect slots_12.reset, reset
inst slots_13 of IssueSlot_49
connect slots_13.clock, clock
connect slots_13.reset, reset
inst slots_14 of IssueSlot_50
connect slots_14.clock, clock
connect slots_14.reset, reset
inst slots_15 of IssueSlot_51
connect slots_15.clock, clock
connect slots_15.reset, reset
inst slots_16 of IssueSlot_52
connect slots_16.clock, clock
connect slots_16.reset, reset
inst slots_17 of IssueSlot_53
connect slots_17.clock, clock
connect slots_17.reset, reset
inst slots_18 of IssueSlot_54
connect slots_18.clock, clock
connect slots_18.reset, reset
inst slots_19 of IssueSlot_55
connect slots_19.clock, clock
connect slots_19.reset, reset
wire issue_slots : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, flip grant : UInt<1>, iss_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip in_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip brupdate : { b1 : { resolve_mask : UInt<12>, mispredict_mask : UInt<12>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip kill : UInt<1>, flip clear : UInt<1>, flip squash_grant : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}}[4], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<2>}[20]
connect slots_0.io.child_rebusys, issue_slots[0].child_rebusys
connect slots_0.io.pred_wakeup_port.bits, issue_slots[0].pred_wakeup_port.bits
connect slots_0.io.pred_wakeup_port.valid, issue_slots[0].pred_wakeup_port.valid
connect slots_0.io.wakeup_ports[0].bits.rebusy, issue_slots[0].wakeup_ports[0].bits.rebusy
connect slots_0.io.wakeup_ports[0].bits.speculative_mask, issue_slots[0].wakeup_ports[0].bits.speculative_mask
connect slots_0.io.wakeup_ports[0].bits.bypassable, issue_slots[0].wakeup_ports[0].bits.bypassable
connect slots_0.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[0].wakeup_ports[0].bits.uop.debug_tsrc
connect slots_0.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[0].wakeup_ports[0].bits.uop.debug_fsrc
connect slots_0.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[0].wakeup_ports[0].bits.uop.bp_xcpt_if
connect slots_0.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[0].wakeup_ports[0].bits.uop.bp_debug_if
connect slots_0.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[0].wakeup_ports[0].bits.uop.xcpt_ma_if
connect slots_0.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[0].wakeup_ports[0].bits.uop.xcpt_ae_if
connect slots_0.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[0].wakeup_ports[0].bits.uop.xcpt_pf_if
connect slots_0.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[0].wakeup_ports[0].bits.uop.fp_typ
connect slots_0.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[0].wakeup_ports[0].bits.uop.fp_rm
connect slots_0.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[0].wakeup_ports[0].bits.uop.fp_val
connect slots_0.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[0].wakeup_ports[0].bits.uop.fcn_op
connect slots_0.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[0].wakeup_ports[0].bits.uop.fcn_dw
connect slots_0.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[0].wakeup_ports[0].bits.uop.frs3_en
connect slots_0.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[0].wakeup_ports[0].bits.uop.lrs2_rtype
connect slots_0.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[0].wakeup_ports[0].bits.uop.lrs1_rtype
connect slots_0.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[0].wakeup_ports[0].bits.uop.dst_rtype
connect slots_0.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[0].wakeup_ports[0].bits.uop.lrs3
connect slots_0.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[0].wakeup_ports[0].bits.uop.lrs2
connect slots_0.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[0].wakeup_ports[0].bits.uop.lrs1
connect slots_0.io.wakeup_ports[0].bits.uop.ldst, issue_slots[0].wakeup_ports[0].bits.uop.ldst
connect slots_0.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[0].wakeup_ports[0].bits.uop.ldst_is_rs1
connect slots_0.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[0].wakeup_ports[0].bits.uop.csr_cmd
connect slots_0.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[0].wakeup_ports[0].bits.uop.flush_on_commit
connect slots_0.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[0].wakeup_ports[0].bits.uop.is_unique
connect slots_0.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[0].wakeup_ports[0].bits.uop.uses_stq
connect slots_0.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[0].wakeup_ports[0].bits.uop.uses_ldq
connect slots_0.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[0].wakeup_ports[0].bits.uop.mem_signed
connect slots_0.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[0].wakeup_ports[0].bits.uop.mem_size
connect slots_0.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[0].wakeup_ports[0].bits.uop.mem_cmd
connect slots_0.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[0].wakeup_ports[0].bits.uop.exc_cause
connect slots_0.io.wakeup_ports[0].bits.uop.exception, issue_slots[0].wakeup_ports[0].bits.uop.exception
connect slots_0.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[0].wakeup_ports[0].bits.uop.stale_pdst
connect slots_0.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[0].wakeup_ports[0].bits.uop.ppred_busy
connect slots_0.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[0].wakeup_ports[0].bits.uop.prs3_busy
connect slots_0.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[0].wakeup_ports[0].bits.uop.prs2_busy
connect slots_0.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[0].wakeup_ports[0].bits.uop.prs1_busy
connect slots_0.io.wakeup_ports[0].bits.uop.ppred, issue_slots[0].wakeup_ports[0].bits.uop.ppred
connect slots_0.io.wakeup_ports[0].bits.uop.prs3, issue_slots[0].wakeup_ports[0].bits.uop.prs3
connect slots_0.io.wakeup_ports[0].bits.uop.prs2, issue_slots[0].wakeup_ports[0].bits.uop.prs2
connect slots_0.io.wakeup_ports[0].bits.uop.prs1, issue_slots[0].wakeup_ports[0].bits.uop.prs1
connect slots_0.io.wakeup_ports[0].bits.uop.pdst, issue_slots[0].wakeup_ports[0].bits.uop.pdst
connect slots_0.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[0].wakeup_ports[0].bits.uop.rxq_idx
connect slots_0.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[0].wakeup_ports[0].bits.uop.stq_idx
connect slots_0.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[0].wakeup_ports[0].bits.uop.ldq_idx
connect slots_0.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[0].wakeup_ports[0].bits.uop.rob_idx
connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.vec
connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.wflags
connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.sqrt
connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.div
connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.fma
connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe
connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.toint
connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.fromint
connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut
connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn
connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.swap23
connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.swap12
connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.ren3
connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.ren2
connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.ren1
connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.wen
connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.ldst
connect slots_0.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[0].wakeup_ports[0].bits.uop.op2_sel
connect slots_0.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[0].wakeup_ports[0].bits.uop.op1_sel
connect slots_0.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[0].wakeup_ports[0].bits.uop.imm_packed
connect slots_0.io.wakeup_ports[0].bits.uop.pimm, issue_slots[0].wakeup_ports[0].bits.uop.pimm
connect slots_0.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[0].wakeup_ports[0].bits.uop.imm_sel
connect slots_0.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[0].wakeup_ports[0].bits.uop.imm_rename
connect slots_0.io.wakeup_ports[0].bits.uop.taken, issue_slots[0].wakeup_ports[0].bits.uop.taken
connect slots_0.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[0].wakeup_ports[0].bits.uop.pc_lob
connect slots_0.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[0].wakeup_ports[0].bits.uop.edge_inst
connect slots_0.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[0].wakeup_ports[0].bits.uop.ftq_idx
connect slots_0.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[0].wakeup_ports[0].bits.uop.is_mov
connect slots_0.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[0].wakeup_ports[0].bits.uop.is_rocc
connect slots_0.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[0].wakeup_ports[0].bits.uop.is_sys_pc2epc
connect slots_0.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[0].wakeup_ports[0].bits.uop.is_eret
connect slots_0.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[0].wakeup_ports[0].bits.uop.is_amo
connect slots_0.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[0].wakeup_ports[0].bits.uop.is_sfence
connect slots_0.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[0].wakeup_ports[0].bits.uop.is_fencei
connect slots_0.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[0].wakeup_ports[0].bits.uop.is_fence
connect slots_0.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[0].wakeup_ports[0].bits.uop.is_sfb
connect slots_0.io.wakeup_ports[0].bits.uop.br_type, issue_slots[0].wakeup_ports[0].bits.uop.br_type
connect slots_0.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[0].wakeup_ports[0].bits.uop.br_tag
connect slots_0.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[0].wakeup_ports[0].bits.uop.br_mask
connect slots_0.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[0].wakeup_ports[0].bits.uop.dis_col_sel
connect slots_0.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[0].wakeup_ports[0].bits.uop.iw_p3_bypass_hint
connect slots_0.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[0].wakeup_ports[0].bits.uop.iw_p2_bypass_hint
connect slots_0.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[0].wakeup_ports[0].bits.uop.iw_p1_bypass_hint
connect slots_0.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[0].wakeup_ports[0].bits.uop.iw_p2_speculative_child
connect slots_0.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[0].wakeup_ports[0].bits.uop.iw_p1_speculative_child
connect slots_0.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[0].wakeup_ports[0].bits.uop.iw_issued_partial_dgen
connect slots_0.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[0].wakeup_ports[0].bits.uop.iw_issued_partial_agen
connect slots_0.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[0].wakeup_ports[0].bits.uop.iw_issued
connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[0]
connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[1]
connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[2]
connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[3]
connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[4]
connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[5]
connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[6]
connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[7]
connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[8]
connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[9]
connect slots_0.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[0].wakeup_ports[0].bits.uop.iq_type[0]
connect slots_0.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[0].wakeup_ports[0].bits.uop.iq_type[1]
connect slots_0.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[0].wakeup_ports[0].bits.uop.iq_type[2]
connect slots_0.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[0].wakeup_ports[0].bits.uop.iq_type[3]
connect slots_0.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[0].wakeup_ports[0].bits.uop.debug_pc
connect slots_0.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[0].wakeup_ports[0].bits.uop.is_rvc
connect slots_0.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[0].wakeup_ports[0].bits.uop.debug_inst
connect slots_0.io.wakeup_ports[0].bits.uop.inst, issue_slots[0].wakeup_ports[0].bits.uop.inst
connect slots_0.io.wakeup_ports[0].valid, issue_slots[0].wakeup_ports[0].valid
connect slots_0.io.wakeup_ports[1].bits.rebusy, issue_slots[0].wakeup_ports[1].bits.rebusy
connect slots_0.io.wakeup_ports[1].bits.speculative_mask, issue_slots[0].wakeup_ports[1].bits.speculative_mask
connect slots_0.io.wakeup_ports[1].bits.bypassable, issue_slots[0].wakeup_ports[1].bits.bypassable
connect slots_0.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[0].wakeup_ports[1].bits.uop.debug_tsrc
connect slots_0.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[0].wakeup_ports[1].bits.uop.debug_fsrc
connect slots_0.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[0].wakeup_ports[1].bits.uop.bp_xcpt_if
connect slots_0.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[0].wakeup_ports[1].bits.uop.bp_debug_if
connect slots_0.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[0].wakeup_ports[1].bits.uop.xcpt_ma_if
connect slots_0.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[0].wakeup_ports[1].bits.uop.xcpt_ae_if
connect slots_0.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[0].wakeup_ports[1].bits.uop.xcpt_pf_if
connect slots_0.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[0].wakeup_ports[1].bits.uop.fp_typ
connect slots_0.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[0].wakeup_ports[1].bits.uop.fp_rm
connect slots_0.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[0].wakeup_ports[1].bits.uop.fp_val
connect slots_0.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[0].wakeup_ports[1].bits.uop.fcn_op
connect slots_0.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[0].wakeup_ports[1].bits.uop.fcn_dw
connect slots_0.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[0].wakeup_ports[1].bits.uop.frs3_en
connect slots_0.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[0].wakeup_ports[1].bits.uop.lrs2_rtype
connect slots_0.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[0].wakeup_ports[1].bits.uop.lrs1_rtype
connect slots_0.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[0].wakeup_ports[1].bits.uop.dst_rtype
connect slots_0.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[0].wakeup_ports[1].bits.uop.lrs3
connect slots_0.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[0].wakeup_ports[1].bits.uop.lrs2
connect slots_0.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[0].wakeup_ports[1].bits.uop.lrs1
connect slots_0.io.wakeup_ports[1].bits.uop.ldst, issue_slots[0].wakeup_ports[1].bits.uop.ldst
connect slots_0.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[0].wakeup_ports[1].bits.uop.ldst_is_rs1
connect slots_0.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[0].wakeup_ports[1].bits.uop.csr_cmd
connect slots_0.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[0].wakeup_ports[1].bits.uop.flush_on_commit
connect slots_0.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[0].wakeup_ports[1].bits.uop.is_unique
connect slots_0.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[0].wakeup_ports[1].bits.uop.uses_stq
connect slots_0.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[0].wakeup_ports[1].bits.uop.uses_ldq
connect slots_0.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[0].wakeup_ports[1].bits.uop.mem_signed
connect slots_0.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[0].wakeup_ports[1].bits.uop.mem_size
connect slots_0.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[0].wakeup_ports[1].bits.uop.mem_cmd
connect slots_0.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[0].wakeup_ports[1].bits.uop.exc_cause
connect slots_0.io.wakeup_ports[1].bits.uop.exception, issue_slots[0].wakeup_ports[1].bits.uop.exception
connect slots_0.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[0].wakeup_ports[1].bits.uop.stale_pdst
connect slots_0.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[0].wakeup_ports[1].bits.uop.ppred_busy
connect slots_0.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[0].wakeup_ports[1].bits.uop.prs3_busy
connect slots_0.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[0].wakeup_ports[1].bits.uop.prs2_busy
connect slots_0.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[0].wakeup_ports[1].bits.uop.prs1_busy
connect slots_0.io.wakeup_ports[1].bits.uop.ppred, issue_slots[0].wakeup_ports[1].bits.uop.ppred
connect slots_0.io.wakeup_ports[1].bits.uop.prs3, issue_slots[0].wakeup_ports[1].bits.uop.prs3
connect slots_0.io.wakeup_ports[1].bits.uop.prs2, issue_slots[0].wakeup_ports[1].bits.uop.prs2
connect slots_0.io.wakeup_ports[1].bits.uop.prs1, issue_slots[0].wakeup_ports[1].bits.uop.prs1
connect slots_0.io.wakeup_ports[1].bits.uop.pdst, issue_slots[0].wakeup_ports[1].bits.uop.pdst
connect slots_0.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[0].wakeup_ports[1].bits.uop.rxq_idx
connect slots_0.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[0].wakeup_ports[1].bits.uop.stq_idx
connect slots_0.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[0].wakeup_ports[1].bits.uop.ldq_idx
connect slots_0.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[0].wakeup_ports[1].bits.uop.rob_idx
connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.vec
connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.wflags
connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.sqrt
connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.div
connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.fma
connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe
connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.toint
connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.fromint
connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut
connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn
connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.swap23
connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.swap12
connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.ren3
connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.ren2
connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.ren1
connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.wen
connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.ldst
connect slots_0.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[0].wakeup_ports[1].bits.uop.op2_sel
connect slots_0.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[0].wakeup_ports[1].bits.uop.op1_sel
connect slots_0.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[0].wakeup_ports[1].bits.uop.imm_packed
connect slots_0.io.wakeup_ports[1].bits.uop.pimm, issue_slots[0].wakeup_ports[1].bits.uop.pimm
connect slots_0.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[0].wakeup_ports[1].bits.uop.imm_sel
connect slots_0.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[0].wakeup_ports[1].bits.uop.imm_rename
connect slots_0.io.wakeup_ports[1].bits.uop.taken, issue_slots[0].wakeup_ports[1].bits.uop.taken
connect slots_0.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[0].wakeup_ports[1].bits.uop.pc_lob
connect slots_0.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[0].wakeup_ports[1].bits.uop.edge_inst
connect slots_0.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[0].wakeup_ports[1].bits.uop.ftq_idx
connect slots_0.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[0].wakeup_ports[1].bits.uop.is_mov
connect slots_0.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[0].wakeup_ports[1].bits.uop.is_rocc
connect slots_0.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[0].wakeup_ports[1].bits.uop.is_sys_pc2epc
connect slots_0.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[0].wakeup_ports[1].bits.uop.is_eret
connect slots_0.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[0].wakeup_ports[1].bits.uop.is_amo
connect slots_0.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[0].wakeup_ports[1].bits.uop.is_sfence
connect slots_0.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[0].wakeup_ports[1].bits.uop.is_fencei
connect slots_0.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[0].wakeup_ports[1].bits.uop.is_fence
connect slots_0.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[0].wakeup_ports[1].bits.uop.is_sfb
connect slots_0.io.wakeup_ports[1].bits.uop.br_type, issue_slots[0].wakeup_ports[1].bits.uop.br_type
connect slots_0.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[0].wakeup_ports[1].bits.uop.br_tag
connect slots_0.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[0].wakeup_ports[1].bits.uop.br_mask
connect slots_0.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[0].wakeup_ports[1].bits.uop.dis_col_sel
connect slots_0.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[0].wakeup_ports[1].bits.uop.iw_p3_bypass_hint
connect slots_0.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[0].wakeup_ports[1].bits.uop.iw_p2_bypass_hint
connect slots_0.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[0].wakeup_ports[1].bits.uop.iw_p1_bypass_hint
connect slots_0.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[0].wakeup_ports[1].bits.uop.iw_p2_speculative_child
connect slots_0.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[0].wakeup_ports[1].bits.uop.iw_p1_speculative_child
connect slots_0.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[0].wakeup_ports[1].bits.uop.iw_issued_partial_dgen
connect slots_0.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[0].wakeup_ports[1].bits.uop.iw_issued_partial_agen
connect slots_0.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[0].wakeup_ports[1].bits.uop.iw_issued
connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[0]
connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[1]
connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[2]
connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[3]
connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[4]
connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[5]
connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[6]
connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[7]
connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[8]
connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[9]
connect slots_0.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[0].wakeup_ports[1].bits.uop.iq_type[0]
connect slots_0.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[0].wakeup_ports[1].bits.uop.iq_type[1]
connect slots_0.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[0].wakeup_ports[1].bits.uop.iq_type[2]
connect slots_0.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[0].wakeup_ports[1].bits.uop.iq_type[3]
connect slots_0.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[0].wakeup_ports[1].bits.uop.debug_pc
connect slots_0.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[0].wakeup_ports[1].bits.uop.is_rvc
connect slots_0.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[0].wakeup_ports[1].bits.uop.debug_inst
connect slots_0.io.wakeup_ports[1].bits.uop.inst, issue_slots[0].wakeup_ports[1].bits.uop.inst
connect slots_0.io.wakeup_ports[1].valid, issue_slots[0].wakeup_ports[1].valid
connect slots_0.io.wakeup_ports[2].bits.rebusy, issue_slots[0].wakeup_ports[2].bits.rebusy
connect slots_0.io.wakeup_ports[2].bits.speculative_mask, issue_slots[0].wakeup_ports[2].bits.speculative_mask
connect slots_0.io.wakeup_ports[2].bits.bypassable, issue_slots[0].wakeup_ports[2].bits.bypassable
connect slots_0.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[0].wakeup_ports[2].bits.uop.debug_tsrc
connect slots_0.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[0].wakeup_ports[2].bits.uop.debug_fsrc
connect slots_0.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[0].wakeup_ports[2].bits.uop.bp_xcpt_if
connect slots_0.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[0].wakeup_ports[2].bits.uop.bp_debug_if
connect slots_0.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[0].wakeup_ports[2].bits.uop.xcpt_ma_if
connect slots_0.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[0].wakeup_ports[2].bits.uop.xcpt_ae_if
connect slots_0.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[0].wakeup_ports[2].bits.uop.xcpt_pf_if
connect slots_0.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[0].wakeup_ports[2].bits.uop.fp_typ
connect slots_0.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[0].wakeup_ports[2].bits.uop.fp_rm
connect slots_0.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[0].wakeup_ports[2].bits.uop.fp_val
connect slots_0.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[0].wakeup_ports[2].bits.uop.fcn_op
connect slots_0.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[0].wakeup_ports[2].bits.uop.fcn_dw
connect slots_0.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[0].wakeup_ports[2].bits.uop.frs3_en
connect slots_0.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[0].wakeup_ports[2].bits.uop.lrs2_rtype
connect slots_0.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[0].wakeup_ports[2].bits.uop.lrs1_rtype
connect slots_0.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[0].wakeup_ports[2].bits.uop.dst_rtype
connect slots_0.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[0].wakeup_ports[2].bits.uop.lrs3
connect slots_0.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[0].wakeup_ports[2].bits.uop.lrs2
connect slots_0.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[0].wakeup_ports[2].bits.uop.lrs1
connect slots_0.io.wakeup_ports[2].bits.uop.ldst, issue_slots[0].wakeup_ports[2].bits.uop.ldst
connect slots_0.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[0].wakeup_ports[2].bits.uop.ldst_is_rs1
connect slots_0.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[0].wakeup_ports[2].bits.uop.csr_cmd
connect slots_0.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[0].wakeup_ports[2].bits.uop.flush_on_commit
connect slots_0.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[0].wakeup_ports[2].bits.uop.is_unique
connect slots_0.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[0].wakeup_ports[2].bits.uop.uses_stq
connect slots_0.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[0].wakeup_ports[2].bits.uop.uses_ldq
connect slots_0.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[0].wakeup_ports[2].bits.uop.mem_signed
connect slots_0.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[0].wakeup_ports[2].bits.uop.mem_size
connect slots_0.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[0].wakeup_ports[2].bits.uop.mem_cmd
connect slots_0.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[0].wakeup_ports[2].bits.uop.exc_cause
connect slots_0.io.wakeup_ports[2].bits.uop.exception, issue_slots[0].wakeup_ports[2].bits.uop.exception
connect slots_0.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[0].wakeup_ports[2].bits.uop.stale_pdst
connect slots_0.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[0].wakeup_ports[2].bits.uop.ppred_busy
connect slots_0.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[0].wakeup_ports[2].bits.uop.prs3_busy
connect slots_0.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[0].wakeup_ports[2].bits.uop.prs2_busy
connect slots_0.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[0].wakeup_ports[2].bits.uop.prs1_busy
connect slots_0.io.wakeup_ports[2].bits.uop.ppred, issue_slots[0].wakeup_ports[2].bits.uop.ppred
connect slots_0.io.wakeup_ports[2].bits.uop.prs3, issue_slots[0].wakeup_ports[2].bits.uop.prs3
connect slots_0.io.wakeup_ports[2].bits.uop.prs2, issue_slots[0].wakeup_ports[2].bits.uop.prs2
connect slots_0.io.wakeup_ports[2].bits.uop.prs1, issue_slots[0].wakeup_ports[2].bits.uop.prs1
connect slots_0.io.wakeup_ports[2].bits.uop.pdst, issue_slots[0].wakeup_ports[2].bits.uop.pdst
connect slots_0.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[0].wakeup_ports[2].bits.uop.rxq_idx
connect slots_0.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[0].wakeup_ports[2].bits.uop.stq_idx
connect slots_0.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[0].wakeup_ports[2].bits.uop.ldq_idx
connect slots_0.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[0].wakeup_ports[2].bits.uop.rob_idx
connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.vec
connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.wflags
connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.sqrt
connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.div
connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.fma
connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe
connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.toint
connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.fromint
connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut
connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn
connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.swap23
connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.swap12
connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.ren3
connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.ren2
connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.ren1
connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.wen
connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.ldst
connect slots_0.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[0].wakeup_ports[2].bits.uop.op2_sel
connect slots_0.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[0].wakeup_ports[2].bits.uop.op1_sel
connect slots_0.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[0].wakeup_ports[2].bits.uop.imm_packed
connect slots_0.io.wakeup_ports[2].bits.uop.pimm, issue_slots[0].wakeup_ports[2].bits.uop.pimm
connect slots_0.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[0].wakeup_ports[2].bits.uop.imm_sel
connect slots_0.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[0].wakeup_ports[2].bits.uop.imm_rename
connect slots_0.io.wakeup_ports[2].bits.uop.taken, issue_slots[0].wakeup_ports[2].bits.uop.taken
connect slots_0.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[0].wakeup_ports[2].bits.uop.pc_lob
connect slots_0.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[0].wakeup_ports[2].bits.uop.edge_inst
connect slots_0.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[0].wakeup_ports[2].bits.uop.ftq_idx
connect slots_0.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[0].wakeup_ports[2].bits.uop.is_mov
connect slots_0.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[0].wakeup_ports[2].bits.uop.is_rocc
connect slots_0.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[0].wakeup_ports[2].bits.uop.is_sys_pc2epc
connect slots_0.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[0].wakeup_ports[2].bits.uop.is_eret
connect slots_0.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[0].wakeup_ports[2].bits.uop.is_amo
connect slots_0.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[0].wakeup_ports[2].bits.uop.is_sfence
connect slots_0.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[0].wakeup_ports[2].bits.uop.is_fencei
connect slots_0.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[0].wakeup_ports[2].bits.uop.is_fence
connect slots_0.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[0].wakeup_ports[2].bits.uop.is_sfb
connect slots_0.io.wakeup_ports[2].bits.uop.br_type, issue_slots[0].wakeup_ports[2].bits.uop.br_type
connect slots_0.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[0].wakeup_ports[2].bits.uop.br_tag
connect slots_0.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[0].wakeup_ports[2].bits.uop.br_mask
connect slots_0.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[0].wakeup_ports[2].bits.uop.dis_col_sel
connect slots_0.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[0].wakeup_ports[2].bits.uop.iw_p3_bypass_hint
connect slots_0.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[0].wakeup_ports[2].bits.uop.iw_p2_bypass_hint
connect slots_0.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[0].wakeup_ports[2].bits.uop.iw_p1_bypass_hint
connect slots_0.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[0].wakeup_ports[2].bits.uop.iw_p2_speculative_child
connect slots_0.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[0].wakeup_ports[2].bits.uop.iw_p1_speculative_child
connect slots_0.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[0].wakeup_ports[2].bits.uop.iw_issued_partial_dgen
connect slots_0.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[0].wakeup_ports[2].bits.uop.iw_issued_partial_agen
connect slots_0.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[0].wakeup_ports[2].bits.uop.iw_issued
connect slots_0.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[0].wakeup_ports[2].bits.uop.fu_code[0]
connect slots_0.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[0].wakeup_ports[2].bits.uop.fu_code[1]
connect slots_0.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[0].wakeup_ports[2].bits.uop.fu_code[2]
connect slots_0.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[0].wakeup_ports[2].bits.uop.fu_code[3]
connect slots_0.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[0].wakeup_ports[2].bits.uop.fu_code[4]
connect slots_0.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[0].wakeup_ports[2].bits.uop.fu_code[5]
connect slots_0.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[0].wakeup_ports[2].bits.uop.fu_code[6]
connect slots_0.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[0].wakeup_ports[2].bits.uop.fu_code[7]
connect slots_0.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[0].wakeup_ports[2].bits.uop.fu_code[8]
connect slots_0.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[0].wakeup_ports[2].bits.uop.fu_code[9]
connect slots_0.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[0].wakeup_ports[2].bits.uop.iq_type[0]
connect slots_0.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[0].wakeup_ports[2].bits.uop.iq_type[1]
connect slots_0.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[0].wakeup_ports[2].bits.uop.iq_type[2]
connect slots_0.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[0].wakeup_ports[2].bits.uop.iq_type[3]
connect slots_0.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[0].wakeup_ports[2].bits.uop.debug_pc
connect slots_0.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[0].wakeup_ports[2].bits.uop.is_rvc
connect slots_0.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[0].wakeup_ports[2].bits.uop.debug_inst
connect slots_0.io.wakeup_ports[2].bits.uop.inst, issue_slots[0].wakeup_ports[2].bits.uop.inst
connect slots_0.io.wakeup_ports[2].valid, issue_slots[0].wakeup_ports[2].valid
connect slots_0.io.wakeup_ports[3].bits.rebusy, issue_slots[0].wakeup_ports[3].bits.rebusy
connect slots_0.io.wakeup_ports[3].bits.speculative_mask, issue_slots[0].wakeup_ports[3].bits.speculative_mask
connect slots_0.io.wakeup_ports[3].bits.bypassable, issue_slots[0].wakeup_ports[3].bits.bypassable
connect slots_0.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[0].wakeup_ports[3].bits.uop.debug_tsrc
connect slots_0.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[0].wakeup_ports[3].bits.uop.debug_fsrc
connect slots_0.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[0].wakeup_ports[3].bits.uop.bp_xcpt_if
connect slots_0.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[0].wakeup_ports[3].bits.uop.bp_debug_if
connect slots_0.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[0].wakeup_ports[3].bits.uop.xcpt_ma_if
connect slots_0.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[0].wakeup_ports[3].bits.uop.xcpt_ae_if
connect slots_0.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[0].wakeup_ports[3].bits.uop.xcpt_pf_if
connect slots_0.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[0].wakeup_ports[3].bits.uop.fp_typ
connect slots_0.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[0].wakeup_ports[3].bits.uop.fp_rm
connect slots_0.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[0].wakeup_ports[3].bits.uop.fp_val
connect slots_0.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[0].wakeup_ports[3].bits.uop.fcn_op
connect slots_0.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[0].wakeup_ports[3].bits.uop.fcn_dw
connect slots_0.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[0].wakeup_ports[3].bits.uop.frs3_en
connect slots_0.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[0].wakeup_ports[3].bits.uop.lrs2_rtype
connect slots_0.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[0].wakeup_ports[3].bits.uop.lrs1_rtype
connect slots_0.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[0].wakeup_ports[3].bits.uop.dst_rtype
connect slots_0.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[0].wakeup_ports[3].bits.uop.lrs3
connect slots_0.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[0].wakeup_ports[3].bits.uop.lrs2
connect slots_0.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[0].wakeup_ports[3].bits.uop.lrs1
connect slots_0.io.wakeup_ports[3].bits.uop.ldst, issue_slots[0].wakeup_ports[3].bits.uop.ldst
connect slots_0.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[0].wakeup_ports[3].bits.uop.ldst_is_rs1
connect slots_0.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[0].wakeup_ports[3].bits.uop.csr_cmd
connect slots_0.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[0].wakeup_ports[3].bits.uop.flush_on_commit
connect slots_0.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[0].wakeup_ports[3].bits.uop.is_unique
connect slots_0.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[0].wakeup_ports[3].bits.uop.uses_stq
connect slots_0.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[0].wakeup_ports[3].bits.uop.uses_ldq
connect slots_0.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[0].wakeup_ports[3].bits.uop.mem_signed
connect slots_0.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[0].wakeup_ports[3].bits.uop.mem_size
connect slots_0.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[0].wakeup_ports[3].bits.uop.mem_cmd
connect slots_0.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[0].wakeup_ports[3].bits.uop.exc_cause
connect slots_0.io.wakeup_ports[3].bits.uop.exception, issue_slots[0].wakeup_ports[3].bits.uop.exception
connect slots_0.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[0].wakeup_ports[3].bits.uop.stale_pdst
connect slots_0.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[0].wakeup_ports[3].bits.uop.ppred_busy
connect slots_0.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[0].wakeup_ports[3].bits.uop.prs3_busy
connect slots_0.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[0].wakeup_ports[3].bits.uop.prs2_busy
connect slots_0.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[0].wakeup_ports[3].bits.uop.prs1_busy
connect slots_0.io.wakeup_ports[3].bits.uop.ppred, issue_slots[0].wakeup_ports[3].bits.uop.ppred
connect slots_0.io.wakeup_ports[3].bits.uop.prs3, issue_slots[0].wakeup_ports[3].bits.uop.prs3
connect slots_0.io.wakeup_ports[3].bits.uop.prs2, issue_slots[0].wakeup_ports[3].bits.uop.prs2
connect slots_0.io.wakeup_ports[3].bits.uop.prs1, issue_slots[0].wakeup_ports[3].bits.uop.prs1
connect slots_0.io.wakeup_ports[3].bits.uop.pdst, issue_slots[0].wakeup_ports[3].bits.uop.pdst
connect slots_0.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[0].wakeup_ports[3].bits.uop.rxq_idx
connect slots_0.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[0].wakeup_ports[3].bits.uop.stq_idx
connect slots_0.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[0].wakeup_ports[3].bits.uop.ldq_idx
connect slots_0.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[0].wakeup_ports[3].bits.uop.rob_idx
connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.vec
connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.wflags
connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.sqrt
connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.div
connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.fma
connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe
connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.toint
connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.fromint
connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut
connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn
connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.swap23
connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.swap12
connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.ren3
connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.ren2
connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.ren1
connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.wen
connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.ldst
connect slots_0.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[0].wakeup_ports[3].bits.uop.op2_sel
connect slots_0.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[0].wakeup_ports[3].bits.uop.op1_sel
connect slots_0.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[0].wakeup_ports[3].bits.uop.imm_packed
connect slots_0.io.wakeup_ports[3].bits.uop.pimm, issue_slots[0].wakeup_ports[3].bits.uop.pimm
connect slots_0.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[0].wakeup_ports[3].bits.uop.imm_sel
connect slots_0.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[0].wakeup_ports[3].bits.uop.imm_rename
connect slots_0.io.wakeup_ports[3].bits.uop.taken, issue_slots[0].wakeup_ports[3].bits.uop.taken
connect slots_0.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[0].wakeup_ports[3].bits.uop.pc_lob
connect slots_0.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[0].wakeup_ports[3].bits.uop.edge_inst
connect slots_0.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[0].wakeup_ports[3].bits.uop.ftq_idx
connect slots_0.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[0].wakeup_ports[3].bits.uop.is_mov
connect slots_0.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[0].wakeup_ports[3].bits.uop.is_rocc
connect slots_0.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[0].wakeup_ports[3].bits.uop.is_sys_pc2epc
connect slots_0.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[0].wakeup_ports[3].bits.uop.is_eret
connect slots_0.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[0].wakeup_ports[3].bits.uop.is_amo
connect slots_0.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[0].wakeup_ports[3].bits.uop.is_sfence
connect slots_0.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[0].wakeup_ports[3].bits.uop.is_fencei
connect slots_0.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[0].wakeup_ports[3].bits.uop.is_fence
connect slots_0.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[0].wakeup_ports[3].bits.uop.is_sfb
connect slots_0.io.wakeup_ports[3].bits.uop.br_type, issue_slots[0].wakeup_ports[3].bits.uop.br_type
connect slots_0.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[0].wakeup_ports[3].bits.uop.br_tag
connect slots_0.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[0].wakeup_ports[3].bits.uop.br_mask
connect slots_0.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[0].wakeup_ports[3].bits.uop.dis_col_sel
connect slots_0.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[0].wakeup_ports[3].bits.uop.iw_p3_bypass_hint
connect slots_0.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[0].wakeup_ports[3].bits.uop.iw_p2_bypass_hint
connect slots_0.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[0].wakeup_ports[3].bits.uop.iw_p1_bypass_hint
connect slots_0.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[0].wakeup_ports[3].bits.uop.iw_p2_speculative_child
connect slots_0.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[0].wakeup_ports[3].bits.uop.iw_p1_speculative_child
connect slots_0.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[0].wakeup_ports[3].bits.uop.iw_issued_partial_dgen
connect slots_0.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[0].wakeup_ports[3].bits.uop.iw_issued_partial_agen
connect slots_0.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[0].wakeup_ports[3].bits.uop.iw_issued
connect slots_0.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[0].wakeup_ports[3].bits.uop.fu_code[0]
connect slots_0.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[0].wakeup_ports[3].bits.uop.fu_code[1]
connect slots_0.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[0].wakeup_ports[3].bits.uop.fu_code[2]
connect slots_0.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[0].wakeup_ports[3].bits.uop.fu_code[3]
connect slots_0.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[0].wakeup_ports[3].bits.uop.fu_code[4]
connect slots_0.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[0].wakeup_ports[3].bits.uop.fu_code[5]
connect slots_0.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[0].wakeup_ports[3].bits.uop.fu_code[6]
connect slots_0.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[0].wakeup_ports[3].bits.uop.fu_code[7]
connect slots_0.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[0].wakeup_ports[3].bits.uop.fu_code[8]
connect slots_0.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[0].wakeup_ports[3].bits.uop.fu_code[9]
connect slots_0.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[0].wakeup_ports[3].bits.uop.iq_type[0]
connect slots_0.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[0].wakeup_ports[3].bits.uop.iq_type[1]
connect slots_0.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[0].wakeup_ports[3].bits.uop.iq_type[2]
connect slots_0.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[0].wakeup_ports[3].bits.uop.iq_type[3]
connect slots_0.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[0].wakeup_ports[3].bits.uop.debug_pc
connect slots_0.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[0].wakeup_ports[3].bits.uop.is_rvc
connect slots_0.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[0].wakeup_ports[3].bits.uop.debug_inst
connect slots_0.io.wakeup_ports[3].bits.uop.inst, issue_slots[0].wakeup_ports[3].bits.uop.inst
connect slots_0.io.wakeup_ports[3].valid, issue_slots[0].wakeup_ports[3].valid
connect slots_0.io.squash_grant, issue_slots[0].squash_grant
connect slots_0.io.clear, issue_slots[0].clear
connect slots_0.io.kill, issue_slots[0].kill
connect slots_0.io.brupdate.b2.target_offset, issue_slots[0].brupdate.b2.target_offset
connect slots_0.io.brupdate.b2.jalr_target, issue_slots[0].brupdate.b2.jalr_target
connect slots_0.io.brupdate.b2.pc_sel, issue_slots[0].brupdate.b2.pc_sel
connect slots_0.io.brupdate.b2.cfi_type, issue_slots[0].brupdate.b2.cfi_type
connect slots_0.io.brupdate.b2.taken, issue_slots[0].brupdate.b2.taken
connect slots_0.io.brupdate.b2.mispredict, issue_slots[0].brupdate.b2.mispredict
connect slots_0.io.brupdate.b2.uop.debug_tsrc, issue_slots[0].brupdate.b2.uop.debug_tsrc
connect slots_0.io.brupdate.b2.uop.debug_fsrc, issue_slots[0].brupdate.b2.uop.debug_fsrc
connect slots_0.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[0].brupdate.b2.uop.bp_xcpt_if
connect slots_0.io.brupdate.b2.uop.bp_debug_if, issue_slots[0].brupdate.b2.uop.bp_debug_if
connect slots_0.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[0].brupdate.b2.uop.xcpt_ma_if
connect slots_0.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[0].brupdate.b2.uop.xcpt_ae_if
connect slots_0.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[0].brupdate.b2.uop.xcpt_pf_if
connect slots_0.io.brupdate.b2.uop.fp_typ, issue_slots[0].brupdate.b2.uop.fp_typ
connect slots_0.io.brupdate.b2.uop.fp_rm, issue_slots[0].brupdate.b2.uop.fp_rm
connect slots_0.io.brupdate.b2.uop.fp_val, issue_slots[0].brupdate.b2.uop.fp_val
connect slots_0.io.brupdate.b2.uop.fcn_op, issue_slots[0].brupdate.b2.uop.fcn_op
connect slots_0.io.brupdate.b2.uop.fcn_dw, issue_slots[0].brupdate.b2.uop.fcn_dw
connect slots_0.io.brupdate.b2.uop.frs3_en, issue_slots[0].brupdate.b2.uop.frs3_en
connect slots_0.io.brupdate.b2.uop.lrs2_rtype, issue_slots[0].brupdate.b2.uop.lrs2_rtype
connect slots_0.io.brupdate.b2.uop.lrs1_rtype, issue_slots[0].brupdate.b2.uop.lrs1_rtype
connect slots_0.io.brupdate.b2.uop.dst_rtype, issue_slots[0].brupdate.b2.uop.dst_rtype
connect slots_0.io.brupdate.b2.uop.lrs3, issue_slots[0].brupdate.b2.uop.lrs3
connect slots_0.io.brupdate.b2.uop.lrs2, issue_slots[0].brupdate.b2.uop.lrs2
connect slots_0.io.brupdate.b2.uop.lrs1, issue_slots[0].brupdate.b2.uop.lrs1
connect slots_0.io.brupdate.b2.uop.ldst, issue_slots[0].brupdate.b2.uop.ldst
connect slots_0.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[0].brupdate.b2.uop.ldst_is_rs1
connect slots_0.io.brupdate.b2.uop.csr_cmd, issue_slots[0].brupdate.b2.uop.csr_cmd
connect slots_0.io.brupdate.b2.uop.flush_on_commit, issue_slots[0].brupdate.b2.uop.flush_on_commit
connect slots_0.io.brupdate.b2.uop.is_unique, issue_slots[0].brupdate.b2.uop.is_unique
connect slots_0.io.brupdate.b2.uop.uses_stq, issue_slots[0].brupdate.b2.uop.uses_stq
connect slots_0.io.brupdate.b2.uop.uses_ldq, issue_slots[0].brupdate.b2.uop.uses_ldq
connect slots_0.io.brupdate.b2.uop.mem_signed, issue_slots[0].brupdate.b2.uop.mem_signed
connect slots_0.io.brupdate.b2.uop.mem_size, issue_slots[0].brupdate.b2.uop.mem_size
connect slots_0.io.brupdate.b2.uop.mem_cmd, issue_slots[0].brupdate.b2.uop.mem_cmd
connect slots_0.io.brupdate.b2.uop.exc_cause, issue_slots[0].brupdate.b2.uop.exc_cause
connect slots_0.io.brupdate.b2.uop.exception, issue_slots[0].brupdate.b2.uop.exception
connect slots_0.io.brupdate.b2.uop.stale_pdst, issue_slots[0].brupdate.b2.uop.stale_pdst
connect slots_0.io.brupdate.b2.uop.ppred_busy, issue_slots[0].brupdate.b2.uop.ppred_busy
connect slots_0.io.brupdate.b2.uop.prs3_busy, issue_slots[0].brupdate.b2.uop.prs3_busy
connect slots_0.io.brupdate.b2.uop.prs2_busy, issue_slots[0].brupdate.b2.uop.prs2_busy
connect slots_0.io.brupdate.b2.uop.prs1_busy, issue_slots[0].brupdate.b2.uop.prs1_busy
connect slots_0.io.brupdate.b2.uop.ppred, issue_slots[0].brupdate.b2.uop.ppred
connect slots_0.io.brupdate.b2.uop.prs3, issue_slots[0].brupdate.b2.uop.prs3
connect slots_0.io.brupdate.b2.uop.prs2, issue_slots[0].brupdate.b2.uop.prs2
connect slots_0.io.brupdate.b2.uop.prs1, issue_slots[0].brupdate.b2.uop.prs1
connect slots_0.io.brupdate.b2.uop.pdst, issue_slots[0].brupdate.b2.uop.pdst
connect slots_0.io.brupdate.b2.uop.rxq_idx, issue_slots[0].brupdate.b2.uop.rxq_idx
connect slots_0.io.brupdate.b2.uop.stq_idx, issue_slots[0].brupdate.b2.uop.stq_idx
connect slots_0.io.brupdate.b2.uop.ldq_idx, issue_slots[0].brupdate.b2.uop.ldq_idx
connect slots_0.io.brupdate.b2.uop.rob_idx, issue_slots[0].brupdate.b2.uop.rob_idx
connect slots_0.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[0].brupdate.b2.uop.fp_ctrl.vec
connect slots_0.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[0].brupdate.b2.uop.fp_ctrl.wflags
connect slots_0.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[0].brupdate.b2.uop.fp_ctrl.sqrt
connect slots_0.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[0].brupdate.b2.uop.fp_ctrl.div
connect slots_0.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[0].brupdate.b2.uop.fp_ctrl.fma
connect slots_0.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[0].brupdate.b2.uop.fp_ctrl.fastpipe
connect slots_0.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[0].brupdate.b2.uop.fp_ctrl.toint
connect slots_0.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[0].brupdate.b2.uop.fp_ctrl.fromint
connect slots_0.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[0].brupdate.b2.uop.fp_ctrl.typeTagOut
connect slots_0.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[0].brupdate.b2.uop.fp_ctrl.typeTagIn
connect slots_0.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[0].brupdate.b2.uop.fp_ctrl.swap23
connect slots_0.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[0].brupdate.b2.uop.fp_ctrl.swap12
connect slots_0.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[0].brupdate.b2.uop.fp_ctrl.ren3
connect slots_0.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[0].brupdate.b2.uop.fp_ctrl.ren2
connect slots_0.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[0].brupdate.b2.uop.fp_ctrl.ren1
connect slots_0.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[0].brupdate.b2.uop.fp_ctrl.wen
connect slots_0.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[0].brupdate.b2.uop.fp_ctrl.ldst
connect slots_0.io.brupdate.b2.uop.op2_sel, issue_slots[0].brupdate.b2.uop.op2_sel
connect slots_0.io.brupdate.b2.uop.op1_sel, issue_slots[0].brupdate.b2.uop.op1_sel
connect slots_0.io.brupdate.b2.uop.imm_packed, issue_slots[0].brupdate.b2.uop.imm_packed
connect slots_0.io.brupdate.b2.uop.pimm, issue_slots[0].brupdate.b2.uop.pimm
connect slots_0.io.brupdate.b2.uop.imm_sel, issue_slots[0].brupdate.b2.uop.imm_sel
connect slots_0.io.brupdate.b2.uop.imm_rename, issue_slots[0].brupdate.b2.uop.imm_rename
connect slots_0.io.brupdate.b2.uop.taken, issue_slots[0].brupdate.b2.uop.taken
connect slots_0.io.brupdate.b2.uop.pc_lob, issue_slots[0].brupdate.b2.uop.pc_lob
connect slots_0.io.brupdate.b2.uop.edge_inst, issue_slots[0].brupdate.b2.uop.edge_inst
connect slots_0.io.brupdate.b2.uop.ftq_idx, issue_slots[0].brupdate.b2.uop.ftq_idx
connect slots_0.io.brupdate.b2.uop.is_mov, issue_slots[0].brupdate.b2.uop.is_mov
connect slots_0.io.brupdate.b2.uop.is_rocc, issue_slots[0].brupdate.b2.uop.is_rocc
connect slots_0.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[0].brupdate.b2.uop.is_sys_pc2epc
connect slots_0.io.brupdate.b2.uop.is_eret, issue_slots[0].brupdate.b2.uop.is_eret
connect slots_0.io.brupdate.b2.uop.is_amo, issue_slots[0].brupdate.b2.uop.is_amo
connect slots_0.io.brupdate.b2.uop.is_sfence, issue_slots[0].brupdate.b2.uop.is_sfence
connect slots_0.io.brupdate.b2.uop.is_fencei, issue_slots[0].brupdate.b2.uop.is_fencei
connect slots_0.io.brupdate.b2.uop.is_fence, issue_slots[0].brupdate.b2.uop.is_fence
connect slots_0.io.brupdate.b2.uop.is_sfb, issue_slots[0].brupdate.b2.uop.is_sfb
connect slots_0.io.brupdate.b2.uop.br_type, issue_slots[0].brupdate.b2.uop.br_type
connect slots_0.io.brupdate.b2.uop.br_tag, issue_slots[0].brupdate.b2.uop.br_tag
connect slots_0.io.brupdate.b2.uop.br_mask, issue_slots[0].brupdate.b2.uop.br_mask
connect slots_0.io.brupdate.b2.uop.dis_col_sel, issue_slots[0].brupdate.b2.uop.dis_col_sel
connect slots_0.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[0].brupdate.b2.uop.iw_p3_bypass_hint
connect slots_0.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[0].brupdate.b2.uop.iw_p2_bypass_hint
connect slots_0.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[0].brupdate.b2.uop.iw_p1_bypass_hint
connect slots_0.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[0].brupdate.b2.uop.iw_p2_speculative_child
connect slots_0.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[0].brupdate.b2.uop.iw_p1_speculative_child
connect slots_0.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[0].brupdate.b2.uop.iw_issued_partial_dgen
connect slots_0.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[0].brupdate.b2.uop.iw_issued_partial_agen
connect slots_0.io.brupdate.b2.uop.iw_issued, issue_slots[0].brupdate.b2.uop.iw_issued
connect slots_0.io.brupdate.b2.uop.fu_code[0], issue_slots[0].brupdate.b2.uop.fu_code[0]
connect slots_0.io.brupdate.b2.uop.fu_code[1], issue_slots[0].brupdate.b2.uop.fu_code[1]
connect slots_0.io.brupdate.b2.uop.fu_code[2], issue_slots[0].brupdate.b2.uop.fu_code[2]
connect slots_0.io.brupdate.b2.uop.fu_code[3], issue_slots[0].brupdate.b2.uop.fu_code[3]
connect slots_0.io.brupdate.b2.uop.fu_code[4], issue_slots[0].brupdate.b2.uop.fu_code[4]
connect slots_0.io.brupdate.b2.uop.fu_code[5], issue_slots[0].brupdate.b2.uop.fu_code[5]
connect slots_0.io.brupdate.b2.uop.fu_code[6], issue_slots[0].brupdate.b2.uop.fu_code[6]
connect slots_0.io.brupdate.b2.uop.fu_code[7], issue_slots[0].brupdate.b2.uop.fu_code[7]
connect slots_0.io.brupdate.b2.uop.fu_code[8], issue_slots[0].brupdate.b2.uop.fu_code[8]
connect slots_0.io.brupdate.b2.uop.fu_code[9], issue_slots[0].brupdate.b2.uop.fu_code[9]
connect slots_0.io.brupdate.b2.uop.iq_type[0], issue_slots[0].brupdate.b2.uop.iq_type[0]
connect slots_0.io.brupdate.b2.uop.iq_type[1], issue_slots[0].brupdate.b2.uop.iq_type[1]
connect slots_0.io.brupdate.b2.uop.iq_type[2], issue_slots[0].brupdate.b2.uop.iq_type[2]
connect slots_0.io.brupdate.b2.uop.iq_type[3], issue_slots[0].brupdate.b2.uop.iq_type[3]
connect slots_0.io.brupdate.b2.uop.debug_pc, issue_slots[0].brupdate.b2.uop.debug_pc
connect slots_0.io.brupdate.b2.uop.is_rvc, issue_slots[0].brupdate.b2.uop.is_rvc
connect slots_0.io.brupdate.b2.uop.debug_inst, issue_slots[0].brupdate.b2.uop.debug_inst
connect slots_0.io.brupdate.b2.uop.inst, issue_slots[0].brupdate.b2.uop.inst
connect slots_0.io.brupdate.b1.mispredict_mask, issue_slots[0].brupdate.b1.mispredict_mask
connect slots_0.io.brupdate.b1.resolve_mask, issue_slots[0].brupdate.b1.resolve_mask
connect issue_slots[0].out_uop.debug_tsrc, slots_0.io.out_uop.debug_tsrc
connect issue_slots[0].out_uop.debug_fsrc, slots_0.io.out_uop.debug_fsrc
connect issue_slots[0].out_uop.bp_xcpt_if, slots_0.io.out_uop.bp_xcpt_if
connect issue_slots[0].out_uop.bp_debug_if, slots_0.io.out_uop.bp_debug_if
connect issue_slots[0].out_uop.xcpt_ma_if, slots_0.io.out_uop.xcpt_ma_if
connect issue_slots[0].out_uop.xcpt_ae_if, slots_0.io.out_uop.xcpt_ae_if
connect issue_slots[0].out_uop.xcpt_pf_if, slots_0.io.out_uop.xcpt_pf_if
connect issue_slots[0].out_uop.fp_typ, slots_0.io.out_uop.fp_typ
connect issue_slots[0].out_uop.fp_rm, slots_0.io.out_uop.fp_rm
connect issue_slots[0].out_uop.fp_val, slots_0.io.out_uop.fp_val
connect issue_slots[0].out_uop.fcn_op, slots_0.io.out_uop.fcn_op
connect issue_slots[0].out_uop.fcn_dw, slots_0.io.out_uop.fcn_dw
connect issue_slots[0].out_uop.frs3_en, slots_0.io.out_uop.frs3_en
connect issue_slots[0].out_uop.lrs2_rtype, slots_0.io.out_uop.lrs2_rtype
connect issue_slots[0].out_uop.lrs1_rtype, slots_0.io.out_uop.lrs1_rtype
connect issue_slots[0].out_uop.dst_rtype, slots_0.io.out_uop.dst_rtype
connect issue_slots[0].out_uop.lrs3, slots_0.io.out_uop.lrs3
connect issue_slots[0].out_uop.lrs2, slots_0.io.out_uop.lrs2
connect issue_slots[0].out_uop.lrs1, slots_0.io.out_uop.lrs1
connect issue_slots[0].out_uop.ldst, slots_0.io.out_uop.ldst
connect issue_slots[0].out_uop.ldst_is_rs1, slots_0.io.out_uop.ldst_is_rs1
connect issue_slots[0].out_uop.csr_cmd, slots_0.io.out_uop.csr_cmd
connect issue_slots[0].out_uop.flush_on_commit, slots_0.io.out_uop.flush_on_commit
connect issue_slots[0].out_uop.is_unique, slots_0.io.out_uop.is_unique
connect issue_slots[0].out_uop.uses_stq, slots_0.io.out_uop.uses_stq
connect issue_slots[0].out_uop.uses_ldq, slots_0.io.out_uop.uses_ldq
connect issue_slots[0].out_uop.mem_signed, slots_0.io.out_uop.mem_signed
connect issue_slots[0].out_uop.mem_size, slots_0.io.out_uop.mem_size
connect issue_slots[0].out_uop.mem_cmd, slots_0.io.out_uop.mem_cmd
connect issue_slots[0].out_uop.exc_cause, slots_0.io.out_uop.exc_cause
connect issue_slots[0].out_uop.exception, slots_0.io.out_uop.exception
connect issue_slots[0].out_uop.stale_pdst, slots_0.io.out_uop.stale_pdst
connect issue_slots[0].out_uop.ppred_busy, slots_0.io.out_uop.ppred_busy
connect issue_slots[0].out_uop.prs3_busy, slots_0.io.out_uop.prs3_busy
connect issue_slots[0].out_uop.prs2_busy, slots_0.io.out_uop.prs2_busy
connect issue_slots[0].out_uop.prs1_busy, slots_0.io.out_uop.prs1_busy
connect issue_slots[0].out_uop.ppred, slots_0.io.out_uop.ppred
connect issue_slots[0].out_uop.prs3, slots_0.io.out_uop.prs3
connect issue_slots[0].out_uop.prs2, slots_0.io.out_uop.prs2
connect issue_slots[0].out_uop.prs1, slots_0.io.out_uop.prs1
connect issue_slots[0].out_uop.pdst, slots_0.io.out_uop.pdst
connect issue_slots[0].out_uop.rxq_idx, slots_0.io.out_uop.rxq_idx
connect issue_slots[0].out_uop.stq_idx, slots_0.io.out_uop.stq_idx
connect issue_slots[0].out_uop.ldq_idx, slots_0.io.out_uop.ldq_idx
connect issue_slots[0].out_uop.rob_idx, slots_0.io.out_uop.rob_idx
connect issue_slots[0].out_uop.fp_ctrl.vec, slots_0.io.out_uop.fp_ctrl.vec
connect issue_slots[0].out_uop.fp_ctrl.wflags, slots_0.io.out_uop.fp_ctrl.wflags
connect issue_slots[0].out_uop.fp_ctrl.sqrt, slots_0.io.out_uop.fp_ctrl.sqrt
connect issue_slots[0].out_uop.fp_ctrl.div, slots_0.io.out_uop.fp_ctrl.div
connect issue_slots[0].out_uop.fp_ctrl.fma, slots_0.io.out_uop.fp_ctrl.fma
connect issue_slots[0].out_uop.fp_ctrl.fastpipe, slots_0.io.out_uop.fp_ctrl.fastpipe
connect issue_slots[0].out_uop.fp_ctrl.toint, slots_0.io.out_uop.fp_ctrl.toint
connect issue_slots[0].out_uop.fp_ctrl.fromint, slots_0.io.out_uop.fp_ctrl.fromint
connect issue_slots[0].out_uop.fp_ctrl.typeTagOut, slots_0.io.out_uop.fp_ctrl.typeTagOut
connect issue_slots[0].out_uop.fp_ctrl.typeTagIn, slots_0.io.out_uop.fp_ctrl.typeTagIn
connect issue_slots[0].out_uop.fp_ctrl.swap23, slots_0.io.out_uop.fp_ctrl.swap23
connect issue_slots[0].out_uop.fp_ctrl.swap12, slots_0.io.out_uop.fp_ctrl.swap12
connect issue_slots[0].out_uop.fp_ctrl.ren3, slots_0.io.out_uop.fp_ctrl.ren3
connect issue_slots[0].out_uop.fp_ctrl.ren2, slots_0.io.out_uop.fp_ctrl.ren2
connect issue_slots[0].out_uop.fp_ctrl.ren1, slots_0.io.out_uop.fp_ctrl.ren1
connect issue_slots[0].out_uop.fp_ctrl.wen, slots_0.io.out_uop.fp_ctrl.wen
connect issue_slots[0].out_uop.fp_ctrl.ldst, slots_0.io.out_uop.fp_ctrl.ldst
connect issue_slots[0].out_uop.op2_sel, slots_0.io.out_uop.op2_sel
connect issue_slots[0].out_uop.op1_sel, slots_0.io.out_uop.op1_sel
connect issue_slots[0].out_uop.imm_packed, slots_0.io.out_uop.imm_packed
connect issue_slots[0].out_uop.pimm, slots_0.io.out_uop.pimm
connect issue_slots[0].out_uop.imm_sel, slots_0.io.out_uop.imm_sel
connect issue_slots[0].out_uop.imm_rename, slots_0.io.out_uop.imm_rename
connect issue_slots[0].out_uop.taken, slots_0.io.out_uop.taken
connect issue_slots[0].out_uop.pc_lob, slots_0.io.out_uop.pc_lob
connect issue_slots[0].out_uop.edge_inst, slots_0.io.out_uop.edge_inst
connect issue_slots[0].out_uop.ftq_idx, slots_0.io.out_uop.ftq_idx
connect issue_slots[0].out_uop.is_mov, slots_0.io.out_uop.is_mov
connect issue_slots[0].out_uop.is_rocc, slots_0.io.out_uop.is_rocc
connect issue_slots[0].out_uop.is_sys_pc2epc, slots_0.io.out_uop.is_sys_pc2epc
connect issue_slots[0].out_uop.is_eret, slots_0.io.out_uop.is_eret
connect issue_slots[0].out_uop.is_amo, slots_0.io.out_uop.is_amo
connect issue_slots[0].out_uop.is_sfence, slots_0.io.out_uop.is_sfence
connect issue_slots[0].out_uop.is_fencei, slots_0.io.out_uop.is_fencei
connect issue_slots[0].out_uop.is_fence, slots_0.io.out_uop.is_fence
connect issue_slots[0].out_uop.is_sfb, slots_0.io.out_uop.is_sfb
connect issue_slots[0].out_uop.br_type, slots_0.io.out_uop.br_type
connect issue_slots[0].out_uop.br_tag, slots_0.io.out_uop.br_tag
connect issue_slots[0].out_uop.br_mask, slots_0.io.out_uop.br_mask
connect issue_slots[0].out_uop.dis_col_sel, slots_0.io.out_uop.dis_col_sel
connect issue_slots[0].out_uop.iw_p3_bypass_hint, slots_0.io.out_uop.iw_p3_bypass_hint
connect issue_slots[0].out_uop.iw_p2_bypass_hint, slots_0.io.out_uop.iw_p2_bypass_hint
connect issue_slots[0].out_uop.iw_p1_bypass_hint, slots_0.io.out_uop.iw_p1_bypass_hint
connect issue_slots[0].out_uop.iw_p2_speculative_child, slots_0.io.out_uop.iw_p2_speculative_child
connect issue_slots[0].out_uop.iw_p1_speculative_child, slots_0.io.out_uop.iw_p1_speculative_child
connect issue_slots[0].out_uop.iw_issued_partial_dgen, slots_0.io.out_uop.iw_issued_partial_dgen
connect issue_slots[0].out_uop.iw_issued_partial_agen, slots_0.io.out_uop.iw_issued_partial_agen
connect issue_slots[0].out_uop.iw_issued, slots_0.io.out_uop.iw_issued
connect issue_slots[0].out_uop.fu_code[0], slots_0.io.out_uop.fu_code[0]
connect issue_slots[0].out_uop.fu_code[1], slots_0.io.out_uop.fu_code[1]
connect issue_slots[0].out_uop.fu_code[2], slots_0.io.out_uop.fu_code[2]
connect issue_slots[0].out_uop.fu_code[3], slots_0.io.out_uop.fu_code[3]
connect issue_slots[0].out_uop.fu_code[4], slots_0.io.out_uop.fu_code[4]
connect issue_slots[0].out_uop.fu_code[5], slots_0.io.out_uop.fu_code[5]
connect issue_slots[0].out_uop.fu_code[6], slots_0.io.out_uop.fu_code[6]
connect issue_slots[0].out_uop.fu_code[7], slots_0.io.out_uop.fu_code[7]
connect issue_slots[0].out_uop.fu_code[8], slots_0.io.out_uop.fu_code[8]
connect issue_slots[0].out_uop.fu_code[9], slots_0.io.out_uop.fu_code[9]
connect issue_slots[0].out_uop.iq_type[0], slots_0.io.out_uop.iq_type[0]
connect issue_slots[0].out_uop.iq_type[1], slots_0.io.out_uop.iq_type[1]
connect issue_slots[0].out_uop.iq_type[2], slots_0.io.out_uop.iq_type[2]
connect issue_slots[0].out_uop.iq_type[3], slots_0.io.out_uop.iq_type[3]
connect issue_slots[0].out_uop.debug_pc, slots_0.io.out_uop.debug_pc
connect issue_slots[0].out_uop.is_rvc, slots_0.io.out_uop.is_rvc
connect issue_slots[0].out_uop.debug_inst, slots_0.io.out_uop.debug_inst
connect issue_slots[0].out_uop.inst, slots_0.io.out_uop.inst
connect slots_0.io.in_uop.bits.debug_tsrc, issue_slots[0].in_uop.bits.debug_tsrc
connect slots_0.io.in_uop.bits.debug_fsrc, issue_slots[0].in_uop.bits.debug_fsrc
connect slots_0.io.in_uop.bits.bp_xcpt_if, issue_slots[0].in_uop.bits.bp_xcpt_if
connect slots_0.io.in_uop.bits.bp_debug_if, issue_slots[0].in_uop.bits.bp_debug_if
connect slots_0.io.in_uop.bits.xcpt_ma_if, issue_slots[0].in_uop.bits.xcpt_ma_if
connect slots_0.io.in_uop.bits.xcpt_ae_if, issue_slots[0].in_uop.bits.xcpt_ae_if
connect slots_0.io.in_uop.bits.xcpt_pf_if, issue_slots[0].in_uop.bits.xcpt_pf_if
connect slots_0.io.in_uop.bits.fp_typ, issue_slots[0].in_uop.bits.fp_typ
connect slots_0.io.in_uop.bits.fp_rm, issue_slots[0].in_uop.bits.fp_rm
connect slots_0.io.in_uop.bits.fp_val, issue_slots[0].in_uop.bits.fp_val
connect slots_0.io.in_uop.bits.fcn_op, issue_slots[0].in_uop.bits.fcn_op
connect slots_0.io.in_uop.bits.fcn_dw, issue_slots[0].in_uop.bits.fcn_dw
connect slots_0.io.in_uop.bits.frs3_en, issue_slots[0].in_uop.bits.frs3_en
connect slots_0.io.in_uop.bits.lrs2_rtype, issue_slots[0].in_uop.bits.lrs2_rtype
connect slots_0.io.in_uop.bits.lrs1_rtype, issue_slots[0].in_uop.bits.lrs1_rtype
connect slots_0.io.in_uop.bits.dst_rtype, issue_slots[0].in_uop.bits.dst_rtype
connect slots_0.io.in_uop.bits.lrs3, issue_slots[0].in_uop.bits.lrs3
connect slots_0.io.in_uop.bits.lrs2, issue_slots[0].in_uop.bits.lrs2
connect slots_0.io.in_uop.bits.lrs1, issue_slots[0].in_uop.bits.lrs1
connect slots_0.io.in_uop.bits.ldst, issue_slots[0].in_uop.bits.ldst
connect slots_0.io.in_uop.bits.ldst_is_rs1, issue_slots[0].in_uop.bits.ldst_is_rs1
connect slots_0.io.in_uop.bits.csr_cmd, issue_slots[0].in_uop.bits.csr_cmd
connect slots_0.io.in_uop.bits.flush_on_commit, issue_slots[0].in_uop.bits.flush_on_commit
connect slots_0.io.in_uop.bits.is_unique, issue_slots[0].in_uop.bits.is_unique
connect slots_0.io.in_uop.bits.uses_stq, issue_slots[0].in_uop.bits.uses_stq
connect slots_0.io.in_uop.bits.uses_ldq, issue_slots[0].in_uop.bits.uses_ldq
connect slots_0.io.in_uop.bits.mem_signed, issue_slots[0].in_uop.bits.mem_signed
connect slots_0.io.in_uop.bits.mem_size, issue_slots[0].in_uop.bits.mem_size
connect slots_0.io.in_uop.bits.mem_cmd, issue_slots[0].in_uop.bits.mem_cmd
connect slots_0.io.in_uop.bits.exc_cause, issue_slots[0].in_uop.bits.exc_cause
connect slots_0.io.in_uop.bits.exception, issue_slots[0].in_uop.bits.exception
connect slots_0.io.in_uop.bits.stale_pdst, issue_slots[0].in_uop.bits.stale_pdst
connect slots_0.io.in_uop.bits.ppred_busy, issue_slots[0].in_uop.bits.ppred_busy
connect slots_0.io.in_uop.bits.prs3_busy, issue_slots[0].in_uop.bits.prs3_busy
connect slots_0.io.in_uop.bits.prs2_busy, issue_slots[0].in_uop.bits.prs2_busy
connect slots_0.io.in_uop.bits.prs1_busy, issue_slots[0].in_uop.bits.prs1_busy
connect slots_0.io.in_uop.bits.ppred, issue_slots[0].in_uop.bits.ppred
connect slots_0.io.in_uop.bits.prs3, issue_slots[0].in_uop.bits.prs3
connect slots_0.io.in_uop.bits.prs2, issue_slots[0].in_uop.bits.prs2
connect slots_0.io.in_uop.bits.prs1, issue_slots[0].in_uop.bits.prs1
connect slots_0.io.in_uop.bits.pdst, issue_slots[0].in_uop.bits.pdst
connect slots_0.io.in_uop.bits.rxq_idx, issue_slots[0].in_uop.bits.rxq_idx
connect slots_0.io.in_uop.bits.stq_idx, issue_slots[0].in_uop.bits.stq_idx
connect slots_0.io.in_uop.bits.ldq_idx, issue_slots[0].in_uop.bits.ldq_idx
connect slots_0.io.in_uop.bits.rob_idx, issue_slots[0].in_uop.bits.rob_idx
connect slots_0.io.in_uop.bits.fp_ctrl.vec, issue_slots[0].in_uop.bits.fp_ctrl.vec
connect slots_0.io.in_uop.bits.fp_ctrl.wflags, issue_slots[0].in_uop.bits.fp_ctrl.wflags
connect slots_0.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[0].in_uop.bits.fp_ctrl.sqrt
connect slots_0.io.in_uop.bits.fp_ctrl.div, issue_slots[0].in_uop.bits.fp_ctrl.div
connect slots_0.io.in_uop.bits.fp_ctrl.fma, issue_slots[0].in_uop.bits.fp_ctrl.fma
connect slots_0.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[0].in_uop.bits.fp_ctrl.fastpipe
connect slots_0.io.in_uop.bits.fp_ctrl.toint, issue_slots[0].in_uop.bits.fp_ctrl.toint
connect slots_0.io.in_uop.bits.fp_ctrl.fromint, issue_slots[0].in_uop.bits.fp_ctrl.fromint
connect slots_0.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[0].in_uop.bits.fp_ctrl.typeTagOut
connect slots_0.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[0].in_uop.bits.fp_ctrl.typeTagIn
connect slots_0.io.in_uop.bits.fp_ctrl.swap23, issue_slots[0].in_uop.bits.fp_ctrl.swap23
connect slots_0.io.in_uop.bits.fp_ctrl.swap12, issue_slots[0].in_uop.bits.fp_ctrl.swap12
connect slots_0.io.in_uop.bits.fp_ctrl.ren3, issue_slots[0].in_uop.bits.fp_ctrl.ren3
connect slots_0.io.in_uop.bits.fp_ctrl.ren2, issue_slots[0].in_uop.bits.fp_ctrl.ren2
connect slots_0.io.in_uop.bits.fp_ctrl.ren1, issue_slots[0].in_uop.bits.fp_ctrl.ren1
connect slots_0.io.in_uop.bits.fp_ctrl.wen, issue_slots[0].in_uop.bits.fp_ctrl.wen
connect slots_0.io.in_uop.bits.fp_ctrl.ldst, issue_slots[0].in_uop.bits.fp_ctrl.ldst
connect slots_0.io.in_uop.bits.op2_sel, issue_slots[0].in_uop.bits.op2_sel
connect slots_0.io.in_uop.bits.op1_sel, issue_slots[0].in_uop.bits.op1_sel
connect slots_0.io.in_uop.bits.imm_packed, issue_slots[0].in_uop.bits.imm_packed
connect slots_0.io.in_uop.bits.pimm, issue_slots[0].in_uop.bits.pimm
connect slots_0.io.in_uop.bits.imm_sel, issue_slots[0].in_uop.bits.imm_sel
connect slots_0.io.in_uop.bits.imm_rename, issue_slots[0].in_uop.bits.imm_rename
connect slots_0.io.in_uop.bits.taken, issue_slots[0].in_uop.bits.taken
connect slots_0.io.in_uop.bits.pc_lob, issue_slots[0].in_uop.bits.pc_lob
connect slots_0.io.in_uop.bits.edge_inst, issue_slots[0].in_uop.bits.edge_inst
connect slots_0.io.in_uop.bits.ftq_idx, issue_slots[0].in_uop.bits.ftq_idx
connect slots_0.io.in_uop.bits.is_mov, issue_slots[0].in_uop.bits.is_mov
connect slots_0.io.in_uop.bits.is_rocc, issue_slots[0].in_uop.bits.is_rocc
connect slots_0.io.in_uop.bits.is_sys_pc2epc, issue_slots[0].in_uop.bits.is_sys_pc2epc
connect slots_0.io.in_uop.bits.is_eret, issue_slots[0].in_uop.bits.is_eret
connect slots_0.io.in_uop.bits.is_amo, issue_slots[0].in_uop.bits.is_amo
connect slots_0.io.in_uop.bits.is_sfence, issue_slots[0].in_uop.bits.is_sfence
connect slots_0.io.in_uop.bits.is_fencei, issue_slots[0].in_uop.bits.is_fencei
connect slots_0.io.in_uop.bits.is_fence, issue_slots[0].in_uop.bits.is_fence
connect slots_0.io.in_uop.bits.is_sfb, issue_slots[0].in_uop.bits.is_sfb
connect slots_0.io.in_uop.bits.br_type, issue_slots[0].in_uop.bits.br_type
connect slots_0.io.in_uop.bits.br_tag, issue_slots[0].in_uop.bits.br_tag
connect slots_0.io.in_uop.bits.br_mask, issue_slots[0].in_uop.bits.br_mask
connect slots_0.io.in_uop.bits.dis_col_sel, issue_slots[0].in_uop.bits.dis_col_sel
connect slots_0.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[0].in_uop.bits.iw_p3_bypass_hint
connect slots_0.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[0].in_uop.bits.iw_p2_bypass_hint
connect slots_0.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[0].in_uop.bits.iw_p1_bypass_hint
connect slots_0.io.in_uop.bits.iw_p2_speculative_child, issue_slots[0].in_uop.bits.iw_p2_speculative_child
connect slots_0.io.in_uop.bits.iw_p1_speculative_child, issue_slots[0].in_uop.bits.iw_p1_speculative_child
connect slots_0.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[0].in_uop.bits.iw_issued_partial_dgen
connect slots_0.io.in_uop.bits.iw_issued_partial_agen, issue_slots[0].in_uop.bits.iw_issued_partial_agen
connect slots_0.io.in_uop.bits.iw_issued, issue_slots[0].in_uop.bits.iw_issued
connect slots_0.io.in_uop.bits.fu_code[0], issue_slots[0].in_uop.bits.fu_code[0]
connect slots_0.io.in_uop.bits.fu_code[1], issue_slots[0].in_uop.bits.fu_code[1]
connect slots_0.io.in_uop.bits.fu_code[2], issue_slots[0].in_uop.bits.fu_code[2]
connect slots_0.io.in_uop.bits.fu_code[3], issue_slots[0].in_uop.bits.fu_code[3]
connect slots_0.io.in_uop.bits.fu_code[4], issue_slots[0].in_uop.bits.fu_code[4]
connect slots_0.io.in_uop.bits.fu_code[5], issue_slots[0].in_uop.bits.fu_code[5]
connect slots_0.io.in_uop.bits.fu_code[6], issue_slots[0].in_uop.bits.fu_code[6]
connect slots_0.io.in_uop.bits.fu_code[7], issue_slots[0].in_uop.bits.fu_code[7]
connect slots_0.io.in_uop.bits.fu_code[8], issue_slots[0].in_uop.bits.fu_code[8]
connect slots_0.io.in_uop.bits.fu_code[9], issue_slots[0].in_uop.bits.fu_code[9]
connect slots_0.io.in_uop.bits.iq_type[0], issue_slots[0].in_uop.bits.iq_type[0]
connect slots_0.io.in_uop.bits.iq_type[1], issue_slots[0].in_uop.bits.iq_type[1]
connect slots_0.io.in_uop.bits.iq_type[2], issue_slots[0].in_uop.bits.iq_type[2]
connect slots_0.io.in_uop.bits.iq_type[3], issue_slots[0].in_uop.bits.iq_type[3]
connect slots_0.io.in_uop.bits.debug_pc, issue_slots[0].in_uop.bits.debug_pc
connect slots_0.io.in_uop.bits.is_rvc, issue_slots[0].in_uop.bits.is_rvc
connect slots_0.io.in_uop.bits.debug_inst, issue_slots[0].in_uop.bits.debug_inst
connect slots_0.io.in_uop.bits.inst, issue_slots[0].in_uop.bits.inst
connect slots_0.io.in_uop.valid, issue_slots[0].in_uop.valid
connect issue_slots[0].iss_uop.debug_tsrc, slots_0.io.iss_uop.debug_tsrc
connect issue_slots[0].iss_uop.debug_fsrc, slots_0.io.iss_uop.debug_fsrc
connect issue_slots[0].iss_uop.bp_xcpt_if, slots_0.io.iss_uop.bp_xcpt_if
connect issue_slots[0].iss_uop.bp_debug_if, slots_0.io.iss_uop.bp_debug_if
connect issue_slots[0].iss_uop.xcpt_ma_if, slots_0.io.iss_uop.xcpt_ma_if
connect issue_slots[0].iss_uop.xcpt_ae_if, slots_0.io.iss_uop.xcpt_ae_if
connect issue_slots[0].iss_uop.xcpt_pf_if, slots_0.io.iss_uop.xcpt_pf_if
connect issue_slots[0].iss_uop.fp_typ, slots_0.io.iss_uop.fp_typ
connect issue_slots[0].iss_uop.fp_rm, slots_0.io.iss_uop.fp_rm
connect issue_slots[0].iss_uop.fp_val, slots_0.io.iss_uop.fp_val
connect issue_slots[0].iss_uop.fcn_op, slots_0.io.iss_uop.fcn_op
connect issue_slots[0].iss_uop.fcn_dw, slots_0.io.iss_uop.fcn_dw
connect issue_slots[0].iss_uop.frs3_en, slots_0.io.iss_uop.frs3_en
connect issue_slots[0].iss_uop.lrs2_rtype, slots_0.io.iss_uop.lrs2_rtype
connect issue_slots[0].iss_uop.lrs1_rtype, slots_0.io.iss_uop.lrs1_rtype
connect issue_slots[0].iss_uop.dst_rtype, slots_0.io.iss_uop.dst_rtype
connect issue_slots[0].iss_uop.lrs3, slots_0.io.iss_uop.lrs3
connect issue_slots[0].iss_uop.lrs2, slots_0.io.iss_uop.lrs2
connect issue_slots[0].iss_uop.lrs1, slots_0.io.iss_uop.lrs1
connect issue_slots[0].iss_uop.ldst, slots_0.io.iss_uop.ldst
connect issue_slots[0].iss_uop.ldst_is_rs1, slots_0.io.iss_uop.ldst_is_rs1
connect issue_slots[0].iss_uop.csr_cmd, slots_0.io.iss_uop.csr_cmd
connect issue_slots[0].iss_uop.flush_on_commit, slots_0.io.iss_uop.flush_on_commit
connect issue_slots[0].iss_uop.is_unique, slots_0.io.iss_uop.is_unique
connect issue_slots[0].iss_uop.uses_stq, slots_0.io.iss_uop.uses_stq
connect issue_slots[0].iss_uop.uses_ldq, slots_0.io.iss_uop.uses_ldq
connect issue_slots[0].iss_uop.mem_signed, slots_0.io.iss_uop.mem_signed
connect issue_slots[0].iss_uop.mem_size, slots_0.io.iss_uop.mem_size
connect issue_slots[0].iss_uop.mem_cmd, slots_0.io.iss_uop.mem_cmd
connect issue_slots[0].iss_uop.exc_cause, slots_0.io.iss_uop.exc_cause
connect issue_slots[0].iss_uop.exception, slots_0.io.iss_uop.exception
connect issue_slots[0].iss_uop.stale_pdst, slots_0.io.iss_uop.stale_pdst
connect issue_slots[0].iss_uop.ppred_busy, slots_0.io.iss_uop.ppred_busy
connect issue_slots[0].iss_uop.prs3_busy, slots_0.io.iss_uop.prs3_busy
connect issue_slots[0].iss_uop.prs2_busy, slots_0.io.iss_uop.prs2_busy
connect issue_slots[0].iss_uop.prs1_busy, slots_0.io.iss_uop.prs1_busy
connect issue_slots[0].iss_uop.ppred, slots_0.io.iss_uop.ppred
connect issue_slots[0].iss_uop.prs3, slots_0.io.iss_uop.prs3
connect issue_slots[0].iss_uop.prs2, slots_0.io.iss_uop.prs2
connect issue_slots[0].iss_uop.prs1, slots_0.io.iss_uop.prs1
connect issue_slots[0].iss_uop.pdst, slots_0.io.iss_uop.pdst
connect issue_slots[0].iss_uop.rxq_idx, slots_0.io.iss_uop.rxq_idx
connect issue_slots[0].iss_uop.stq_idx, slots_0.io.iss_uop.stq_idx
connect issue_slots[0].iss_uop.ldq_idx, slots_0.io.iss_uop.ldq_idx
connect issue_slots[0].iss_uop.rob_idx, slots_0.io.iss_uop.rob_idx
connect issue_slots[0].iss_uop.fp_ctrl.vec, slots_0.io.iss_uop.fp_ctrl.vec
connect issue_slots[0].iss_uop.fp_ctrl.wflags, slots_0.io.iss_uop.fp_ctrl.wflags
connect issue_slots[0].iss_uop.fp_ctrl.sqrt, slots_0.io.iss_uop.fp_ctrl.sqrt
connect issue_slots[0].iss_uop.fp_ctrl.div, slots_0.io.iss_uop.fp_ctrl.div
connect issue_slots[0].iss_uop.fp_ctrl.fma, slots_0.io.iss_uop.fp_ctrl.fma
connect issue_slots[0].iss_uop.fp_ctrl.fastpipe, slots_0.io.iss_uop.fp_ctrl.fastpipe
connect issue_slots[0].iss_uop.fp_ctrl.toint, slots_0.io.iss_uop.fp_ctrl.toint
connect issue_slots[0].iss_uop.fp_ctrl.fromint, slots_0.io.iss_uop.fp_ctrl.fromint
connect issue_slots[0].iss_uop.fp_ctrl.typeTagOut, slots_0.io.iss_uop.fp_ctrl.typeTagOut
connect issue_slots[0].iss_uop.fp_ctrl.typeTagIn, slots_0.io.iss_uop.fp_ctrl.typeTagIn
connect issue_slots[0].iss_uop.fp_ctrl.swap23, slots_0.io.iss_uop.fp_ctrl.swap23
connect issue_slots[0].iss_uop.fp_ctrl.swap12, slots_0.io.iss_uop.fp_ctrl.swap12
connect issue_slots[0].iss_uop.fp_ctrl.ren3, slots_0.io.iss_uop.fp_ctrl.ren3
connect issue_slots[0].iss_uop.fp_ctrl.ren2, slots_0.io.iss_uop.fp_ctrl.ren2
connect issue_slots[0].iss_uop.fp_ctrl.ren1, slots_0.io.iss_uop.fp_ctrl.ren1
connect issue_slots[0].iss_uop.fp_ctrl.wen, slots_0.io.iss_uop.fp_ctrl.wen
connect issue_slots[0].iss_uop.fp_ctrl.ldst, slots_0.io.iss_uop.fp_ctrl.ldst
connect issue_slots[0].iss_uop.op2_sel, slots_0.io.iss_uop.op2_sel
connect issue_slots[0].iss_uop.op1_sel, slots_0.io.iss_uop.op1_sel
connect issue_slots[0].iss_uop.imm_packed, slots_0.io.iss_uop.imm_packed
connect issue_slots[0].iss_uop.pimm, slots_0.io.iss_uop.pimm
connect issue_slots[0].iss_uop.imm_sel, slots_0.io.iss_uop.imm_sel
connect issue_slots[0].iss_uop.imm_rename, slots_0.io.iss_uop.imm_rename
connect issue_slots[0].iss_uop.taken, slots_0.io.iss_uop.taken
connect issue_slots[0].iss_uop.pc_lob, slots_0.io.iss_uop.pc_lob
connect issue_slots[0].iss_uop.edge_inst, slots_0.io.iss_uop.edge_inst
connect issue_slots[0].iss_uop.ftq_idx, slots_0.io.iss_uop.ftq_idx
connect issue_slots[0].iss_uop.is_mov, slots_0.io.iss_uop.is_mov
connect issue_slots[0].iss_uop.is_rocc, slots_0.io.iss_uop.is_rocc
connect issue_slots[0].iss_uop.is_sys_pc2epc, slots_0.io.iss_uop.is_sys_pc2epc
connect issue_slots[0].iss_uop.is_eret, slots_0.io.iss_uop.is_eret
connect issue_slots[0].iss_uop.is_amo, slots_0.io.iss_uop.is_amo
connect issue_slots[0].iss_uop.is_sfence, slots_0.io.iss_uop.is_sfence
connect issue_slots[0].iss_uop.is_fencei, slots_0.io.iss_uop.is_fencei
connect issue_slots[0].iss_uop.is_fence, slots_0.io.iss_uop.is_fence
connect issue_slots[0].iss_uop.is_sfb, slots_0.io.iss_uop.is_sfb
connect issue_slots[0].iss_uop.br_type, slots_0.io.iss_uop.br_type
connect issue_slots[0].iss_uop.br_tag, slots_0.io.iss_uop.br_tag
connect issue_slots[0].iss_uop.br_mask, slots_0.io.iss_uop.br_mask
connect issue_slots[0].iss_uop.dis_col_sel, slots_0.io.iss_uop.dis_col_sel
connect issue_slots[0].iss_uop.iw_p3_bypass_hint, slots_0.io.iss_uop.iw_p3_bypass_hint
connect issue_slots[0].iss_uop.iw_p2_bypass_hint, slots_0.io.iss_uop.iw_p2_bypass_hint
connect issue_slots[0].iss_uop.iw_p1_bypass_hint, slots_0.io.iss_uop.iw_p1_bypass_hint
connect issue_slots[0].iss_uop.iw_p2_speculative_child, slots_0.io.iss_uop.iw_p2_speculative_child
connect issue_slots[0].iss_uop.iw_p1_speculative_child, slots_0.io.iss_uop.iw_p1_speculative_child
connect issue_slots[0].iss_uop.iw_issued_partial_dgen, slots_0.io.iss_uop.iw_issued_partial_dgen
connect issue_slots[0].iss_uop.iw_issued_partial_agen, slots_0.io.iss_uop.iw_issued_partial_agen
connect issue_slots[0].iss_uop.iw_issued, slots_0.io.iss_uop.iw_issued
connect issue_slots[0].iss_uop.fu_code[0], slots_0.io.iss_uop.fu_code[0]
connect issue_slots[0].iss_uop.fu_code[1], slots_0.io.iss_uop.fu_code[1]
connect issue_slots[0].iss_uop.fu_code[2], slots_0.io.iss_uop.fu_code[2]
connect issue_slots[0].iss_uop.fu_code[3], slots_0.io.iss_uop.fu_code[3]
connect issue_slots[0].iss_uop.fu_code[4], slots_0.io.iss_uop.fu_code[4]
connect issue_slots[0].iss_uop.fu_code[5], slots_0.io.iss_uop.fu_code[5]
connect issue_slots[0].iss_uop.fu_code[6], slots_0.io.iss_uop.fu_code[6]
connect issue_slots[0].iss_uop.fu_code[7], slots_0.io.iss_uop.fu_code[7]
connect issue_slots[0].iss_uop.fu_code[8], slots_0.io.iss_uop.fu_code[8]
connect issue_slots[0].iss_uop.fu_code[9], slots_0.io.iss_uop.fu_code[9]
connect issue_slots[0].iss_uop.iq_type[0], slots_0.io.iss_uop.iq_type[0]
connect issue_slots[0].iss_uop.iq_type[1], slots_0.io.iss_uop.iq_type[1]
connect issue_slots[0].iss_uop.iq_type[2], slots_0.io.iss_uop.iq_type[2]
connect issue_slots[0].iss_uop.iq_type[3], slots_0.io.iss_uop.iq_type[3]
connect issue_slots[0].iss_uop.debug_pc, slots_0.io.iss_uop.debug_pc
connect issue_slots[0].iss_uop.is_rvc, slots_0.io.iss_uop.is_rvc
connect issue_slots[0].iss_uop.debug_inst, slots_0.io.iss_uop.debug_inst
connect issue_slots[0].iss_uop.inst, slots_0.io.iss_uop.inst
connect slots_0.io.grant, issue_slots[0].grant
connect issue_slots[0].request, slots_0.io.request
connect issue_slots[0].will_be_valid, slots_0.io.will_be_valid
connect issue_slots[0].valid, slots_0.io.valid
connect slots_1.io.child_rebusys, issue_slots[1].child_rebusys
connect slots_1.io.pred_wakeup_port.bits, issue_slots[1].pred_wakeup_port.bits
connect slots_1.io.pred_wakeup_port.valid, issue_slots[1].pred_wakeup_port.valid
connect slots_1.io.wakeup_ports[0].bits.rebusy, issue_slots[1].wakeup_ports[0].bits.rebusy
connect slots_1.io.wakeup_ports[0].bits.speculative_mask, issue_slots[1].wakeup_ports[0].bits.speculative_mask
connect slots_1.io.wakeup_ports[0].bits.bypassable, issue_slots[1].wakeup_ports[0].bits.bypassable
connect slots_1.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[1].wakeup_ports[0].bits.uop.debug_tsrc
connect slots_1.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[1].wakeup_ports[0].bits.uop.debug_fsrc
connect slots_1.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[1].wakeup_ports[0].bits.uop.bp_xcpt_if
connect slots_1.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[1].wakeup_ports[0].bits.uop.bp_debug_if
connect slots_1.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[1].wakeup_ports[0].bits.uop.xcpt_ma_if
connect slots_1.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[1].wakeup_ports[0].bits.uop.xcpt_ae_if
connect slots_1.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[1].wakeup_ports[0].bits.uop.xcpt_pf_if
connect slots_1.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[1].wakeup_ports[0].bits.uop.fp_typ
connect slots_1.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[1].wakeup_ports[0].bits.uop.fp_rm
connect slots_1.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[1].wakeup_ports[0].bits.uop.fp_val
connect slots_1.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[1].wakeup_ports[0].bits.uop.fcn_op
connect slots_1.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[1].wakeup_ports[0].bits.uop.fcn_dw
connect slots_1.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[1].wakeup_ports[0].bits.uop.frs3_en
connect slots_1.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[1].wakeup_ports[0].bits.uop.lrs2_rtype
connect slots_1.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[1].wakeup_ports[0].bits.uop.lrs1_rtype
connect slots_1.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[1].wakeup_ports[0].bits.uop.dst_rtype
connect slots_1.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[1].wakeup_ports[0].bits.uop.lrs3
connect slots_1.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[1].wakeup_ports[0].bits.uop.lrs2
connect slots_1.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[1].wakeup_ports[0].bits.uop.lrs1
connect slots_1.io.wakeup_ports[0].bits.uop.ldst, issue_slots[1].wakeup_ports[0].bits.uop.ldst
connect slots_1.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[1].wakeup_ports[0].bits.uop.ldst_is_rs1
connect slots_1.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[1].wakeup_ports[0].bits.uop.csr_cmd
connect slots_1.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[1].wakeup_ports[0].bits.uop.flush_on_commit
connect slots_1.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[1].wakeup_ports[0].bits.uop.is_unique
connect slots_1.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[1].wakeup_ports[0].bits.uop.uses_stq
connect slots_1.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[1].wakeup_ports[0].bits.uop.uses_ldq
connect slots_1.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[1].wakeup_ports[0].bits.uop.mem_signed
connect slots_1.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[1].wakeup_ports[0].bits.uop.mem_size
connect slots_1.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[1].wakeup_ports[0].bits.uop.mem_cmd
connect slots_1.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[1].wakeup_ports[0].bits.uop.exc_cause
connect slots_1.io.wakeup_ports[0].bits.uop.exception, issue_slots[1].wakeup_ports[0].bits.uop.exception
connect slots_1.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[1].wakeup_ports[0].bits.uop.stale_pdst
connect slots_1.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[1].wakeup_ports[0].bits.uop.ppred_busy
connect slots_1.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[1].wakeup_ports[0].bits.uop.prs3_busy
connect slots_1.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[1].wakeup_ports[0].bits.uop.prs2_busy
connect slots_1.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[1].wakeup_ports[0].bits.uop.prs1_busy
connect slots_1.io.wakeup_ports[0].bits.uop.ppred, issue_slots[1].wakeup_ports[0].bits.uop.ppred
connect slots_1.io.wakeup_ports[0].bits.uop.prs3, issue_slots[1].wakeup_ports[0].bits.uop.prs3
connect slots_1.io.wakeup_ports[0].bits.uop.prs2, issue_slots[1].wakeup_ports[0].bits.uop.prs2
connect slots_1.io.wakeup_ports[0].bits.uop.prs1, issue_slots[1].wakeup_ports[0].bits.uop.prs1
connect slots_1.io.wakeup_ports[0].bits.uop.pdst, issue_slots[1].wakeup_ports[0].bits.uop.pdst
connect slots_1.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[1].wakeup_ports[0].bits.uop.rxq_idx
connect slots_1.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[1].wakeup_ports[0].bits.uop.stq_idx
connect slots_1.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[1].wakeup_ports[0].bits.uop.ldq_idx
connect slots_1.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[1].wakeup_ports[0].bits.uop.rob_idx
connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.vec
connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.wflags
connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.sqrt
connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.div
connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.fma
connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe
connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.toint
connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.fromint
connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut
connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn
connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.swap23
connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.swap12
connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.ren3
connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.ren2
connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.ren1
connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.wen
connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.ldst
connect slots_1.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[1].wakeup_ports[0].bits.uop.op2_sel
connect slots_1.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[1].wakeup_ports[0].bits.uop.op1_sel
connect slots_1.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[1].wakeup_ports[0].bits.uop.imm_packed
connect slots_1.io.wakeup_ports[0].bits.uop.pimm, issue_slots[1].wakeup_ports[0].bits.uop.pimm
connect slots_1.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[1].wakeup_ports[0].bits.uop.imm_sel
connect slots_1.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[1].wakeup_ports[0].bits.uop.imm_rename
connect slots_1.io.wakeup_ports[0].bits.uop.taken, issue_slots[1].wakeup_ports[0].bits.uop.taken
connect slots_1.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[1].wakeup_ports[0].bits.uop.pc_lob
connect slots_1.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[1].wakeup_ports[0].bits.uop.edge_inst
connect slots_1.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[1].wakeup_ports[0].bits.uop.ftq_idx
connect slots_1.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[1].wakeup_ports[0].bits.uop.is_mov
connect slots_1.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[1].wakeup_ports[0].bits.uop.is_rocc
connect slots_1.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[1].wakeup_ports[0].bits.uop.is_sys_pc2epc
connect slots_1.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[1].wakeup_ports[0].bits.uop.is_eret
connect slots_1.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[1].wakeup_ports[0].bits.uop.is_amo
connect slots_1.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[1].wakeup_ports[0].bits.uop.is_sfence
connect slots_1.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[1].wakeup_ports[0].bits.uop.is_fencei
connect slots_1.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[1].wakeup_ports[0].bits.uop.is_fence
connect slots_1.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[1].wakeup_ports[0].bits.uop.is_sfb
connect slots_1.io.wakeup_ports[0].bits.uop.br_type, issue_slots[1].wakeup_ports[0].bits.uop.br_type
connect slots_1.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[1].wakeup_ports[0].bits.uop.br_tag
connect slots_1.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[1].wakeup_ports[0].bits.uop.br_mask
connect slots_1.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[1].wakeup_ports[0].bits.uop.dis_col_sel
connect slots_1.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[1].wakeup_ports[0].bits.uop.iw_p3_bypass_hint
connect slots_1.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[1].wakeup_ports[0].bits.uop.iw_p2_bypass_hint
connect slots_1.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[1].wakeup_ports[0].bits.uop.iw_p1_bypass_hint
connect slots_1.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[1].wakeup_ports[0].bits.uop.iw_p2_speculative_child
connect slots_1.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[1].wakeup_ports[0].bits.uop.iw_p1_speculative_child
connect slots_1.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[1].wakeup_ports[0].bits.uop.iw_issued_partial_dgen
connect slots_1.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[1].wakeup_ports[0].bits.uop.iw_issued_partial_agen
connect slots_1.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[1].wakeup_ports[0].bits.uop.iw_issued
connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[0]
connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[1]
connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[2]
connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[3]
connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[4]
connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[5]
connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[6]
connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[7]
connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[8]
connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[9]
connect slots_1.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[1].wakeup_ports[0].bits.uop.iq_type[0]
connect slots_1.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[1].wakeup_ports[0].bits.uop.iq_type[1]
connect slots_1.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[1].wakeup_ports[0].bits.uop.iq_type[2]
connect slots_1.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[1].wakeup_ports[0].bits.uop.iq_type[3]
connect slots_1.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[1].wakeup_ports[0].bits.uop.debug_pc
connect slots_1.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[1].wakeup_ports[0].bits.uop.is_rvc
connect slots_1.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[1].wakeup_ports[0].bits.uop.debug_inst
connect slots_1.io.wakeup_ports[0].bits.uop.inst, issue_slots[1].wakeup_ports[0].bits.uop.inst
connect slots_1.io.wakeup_ports[0].valid, issue_slots[1].wakeup_ports[0].valid
connect slots_1.io.wakeup_ports[1].bits.rebusy, issue_slots[1].wakeup_ports[1].bits.rebusy
connect slots_1.io.wakeup_ports[1].bits.speculative_mask, issue_slots[1].wakeup_ports[1].bits.speculative_mask
connect slots_1.io.wakeup_ports[1].bits.bypassable, issue_slots[1].wakeup_ports[1].bits.bypassable
connect slots_1.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[1].wakeup_ports[1].bits.uop.debug_tsrc
connect slots_1.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[1].wakeup_ports[1].bits.uop.debug_fsrc
connect slots_1.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[1].wakeup_ports[1].bits.uop.bp_xcpt_if
connect slots_1.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[1].wakeup_ports[1].bits.uop.bp_debug_if
connect slots_1.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[1].wakeup_ports[1].bits.uop.xcpt_ma_if
connect slots_1.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[1].wakeup_ports[1].bits.uop.xcpt_ae_if
connect slots_1.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[1].wakeup_ports[1].bits.uop.xcpt_pf_if
connect slots_1.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[1].wakeup_ports[1].bits.uop.fp_typ
connect slots_1.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[1].wakeup_ports[1].bits.uop.fp_rm
connect slots_1.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[1].wakeup_ports[1].bits.uop.fp_val
connect slots_1.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[1].wakeup_ports[1].bits.uop.fcn_op
connect slots_1.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[1].wakeup_ports[1].bits.uop.fcn_dw
connect slots_1.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[1].wakeup_ports[1].bits.uop.frs3_en
connect slots_1.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[1].wakeup_ports[1].bits.uop.lrs2_rtype
connect slots_1.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[1].wakeup_ports[1].bits.uop.lrs1_rtype
connect slots_1.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[1].wakeup_ports[1].bits.uop.dst_rtype
connect slots_1.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[1].wakeup_ports[1].bits.uop.lrs3
connect slots_1.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[1].wakeup_ports[1].bits.uop.lrs2
connect slots_1.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[1].wakeup_ports[1].bits.uop.lrs1
connect slots_1.io.wakeup_ports[1].bits.uop.ldst, issue_slots[1].wakeup_ports[1].bits.uop.ldst
connect slots_1.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[1].wakeup_ports[1].bits.uop.ldst_is_rs1
connect slots_1.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[1].wakeup_ports[1].bits.uop.csr_cmd
connect slots_1.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[1].wakeup_ports[1].bits.uop.flush_on_commit
connect slots_1.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[1].wakeup_ports[1].bits.uop.is_unique
connect slots_1.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[1].wakeup_ports[1].bits.uop.uses_stq
connect slots_1.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[1].wakeup_ports[1].bits.uop.uses_ldq
connect slots_1.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[1].wakeup_ports[1].bits.uop.mem_signed
connect slots_1.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[1].wakeup_ports[1].bits.uop.mem_size
connect slots_1.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[1].wakeup_ports[1].bits.uop.mem_cmd
connect slots_1.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[1].wakeup_ports[1].bits.uop.exc_cause
connect slots_1.io.wakeup_ports[1].bits.uop.exception, issue_slots[1].wakeup_ports[1].bits.uop.exception
connect slots_1.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[1].wakeup_ports[1].bits.uop.stale_pdst
connect slots_1.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[1].wakeup_ports[1].bits.uop.ppred_busy
connect slots_1.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[1].wakeup_ports[1].bits.uop.prs3_busy
connect slots_1.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[1].wakeup_ports[1].bits.uop.prs2_busy
connect slots_1.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[1].wakeup_ports[1].bits.uop.prs1_busy
connect slots_1.io.wakeup_ports[1].bits.uop.ppred, issue_slots[1].wakeup_ports[1].bits.uop.ppred
connect slots_1.io.wakeup_ports[1].bits.uop.prs3, issue_slots[1].wakeup_ports[1].bits.uop.prs3
connect slots_1.io.wakeup_ports[1].bits.uop.prs2, issue_slots[1].wakeup_ports[1].bits.uop.prs2
connect slots_1.io.wakeup_ports[1].bits.uop.prs1, issue_slots[1].wakeup_ports[1].bits.uop.prs1
connect slots_1.io.wakeup_ports[1].bits.uop.pdst, issue_slots[1].wakeup_ports[1].bits.uop.pdst
connect slots_1.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[1].wakeup_ports[1].bits.uop.rxq_idx
connect slots_1.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[1].wakeup_ports[1].bits.uop.stq_idx
connect slots_1.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[1].wakeup_ports[1].bits.uop.ldq_idx
connect slots_1.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[1].wakeup_ports[1].bits.uop.rob_idx
connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.vec
connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.wflags
connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.sqrt
connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.div
connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.fma
connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe
connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.toint
connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.fromint
connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut
connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn
connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.swap23
connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.swap12
connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.ren3
connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.ren2
connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.ren1
connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.wen
connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.ldst
connect slots_1.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[1].wakeup_ports[1].bits.uop.op2_sel
connect slots_1.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[1].wakeup_ports[1].bits.uop.op1_sel
connect slots_1.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[1].wakeup_ports[1].bits.uop.imm_packed
connect slots_1.io.wakeup_ports[1].bits.uop.pimm, issue_slots[1].wakeup_ports[1].bits.uop.pimm
connect slots_1.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[1].wakeup_ports[1].bits.uop.imm_sel
connect slots_1.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[1].wakeup_ports[1].bits.uop.imm_rename
connect slots_1.io.wakeup_ports[1].bits.uop.taken, issue_slots[1].wakeup_ports[1].bits.uop.taken
connect slots_1.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[1].wakeup_ports[1].bits.uop.pc_lob
connect slots_1.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[1].wakeup_ports[1].bits.uop.edge_inst
connect slots_1.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[1].wakeup_ports[1].bits.uop.ftq_idx
connect slots_1.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[1].wakeup_ports[1].bits.uop.is_mov
connect slots_1.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[1].wakeup_ports[1].bits.uop.is_rocc
connect slots_1.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[1].wakeup_ports[1].bits.uop.is_sys_pc2epc
connect slots_1.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[1].wakeup_ports[1].bits.uop.is_eret
connect slots_1.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[1].wakeup_ports[1].bits.uop.is_amo
connect slots_1.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[1].wakeup_ports[1].bits.uop.is_sfence
connect slots_1.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[1].wakeup_ports[1].bits.uop.is_fencei
connect slots_1.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[1].wakeup_ports[1].bits.uop.is_fence
connect slots_1.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[1].wakeup_ports[1].bits.uop.is_sfb
connect slots_1.io.wakeup_ports[1].bits.uop.br_type, issue_slots[1].wakeup_ports[1].bits.uop.br_type
connect slots_1.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[1].wakeup_ports[1].bits.uop.br_tag
connect slots_1.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[1].wakeup_ports[1].bits.uop.br_mask
connect slots_1.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[1].wakeup_ports[1].bits.uop.dis_col_sel
connect slots_1.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[1].wakeup_ports[1].bits.uop.iw_p3_bypass_hint
connect slots_1.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[1].wakeup_ports[1].bits.uop.iw_p2_bypass_hint
connect slots_1.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[1].wakeup_ports[1].bits.uop.iw_p1_bypass_hint
connect slots_1.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[1].wakeup_ports[1].bits.uop.iw_p2_speculative_child
connect slots_1.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[1].wakeup_ports[1].bits.uop.iw_p1_speculative_child
connect slots_1.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[1].wakeup_ports[1].bits.uop.iw_issued_partial_dgen
connect slots_1.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[1].wakeup_ports[1].bits.uop.iw_issued_partial_agen
connect slots_1.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[1].wakeup_ports[1].bits.uop.iw_issued
connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[0]
connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[1]
connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[2]
connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[3]
connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[4]
connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[5]
connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[6]
connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[7]
connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[8]
connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[9]
connect slots_1.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[1].wakeup_ports[1].bits.uop.iq_type[0]
connect slots_1.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[1].wakeup_ports[1].bits.uop.iq_type[1]
connect slots_1.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[1].wakeup_ports[1].bits.uop.iq_type[2]
connect slots_1.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[1].wakeup_ports[1].bits.uop.iq_type[3]
connect slots_1.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[1].wakeup_ports[1].bits.uop.debug_pc
connect slots_1.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[1].wakeup_ports[1].bits.uop.is_rvc
connect slots_1.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[1].wakeup_ports[1].bits.uop.debug_inst
connect slots_1.io.wakeup_ports[1].bits.uop.inst, issue_slots[1].wakeup_ports[1].bits.uop.inst
connect slots_1.io.wakeup_ports[1].valid, issue_slots[1].wakeup_ports[1].valid
connect slots_1.io.wakeup_ports[2].bits.rebusy, issue_slots[1].wakeup_ports[2].bits.rebusy
connect slots_1.io.wakeup_ports[2].bits.speculative_mask, issue_slots[1].wakeup_ports[2].bits.speculative_mask
connect slots_1.io.wakeup_ports[2].bits.bypassable, issue_slots[1].wakeup_ports[2].bits.bypassable
connect slots_1.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[1].wakeup_ports[2].bits.uop.debug_tsrc
connect slots_1.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[1].wakeup_ports[2].bits.uop.debug_fsrc
connect slots_1.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[1].wakeup_ports[2].bits.uop.bp_xcpt_if
connect slots_1.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[1].wakeup_ports[2].bits.uop.bp_debug_if
connect slots_1.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[1].wakeup_ports[2].bits.uop.xcpt_ma_if
connect slots_1.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[1].wakeup_ports[2].bits.uop.xcpt_ae_if
connect slots_1.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[1].wakeup_ports[2].bits.uop.xcpt_pf_if
connect slots_1.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[1].wakeup_ports[2].bits.uop.fp_typ
connect slots_1.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[1].wakeup_ports[2].bits.uop.fp_rm
connect slots_1.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[1].wakeup_ports[2].bits.uop.fp_val
connect slots_1.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[1].wakeup_ports[2].bits.uop.fcn_op
connect slots_1.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[1].wakeup_ports[2].bits.uop.fcn_dw
connect slots_1.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[1].wakeup_ports[2].bits.uop.frs3_en
connect slots_1.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[1].wakeup_ports[2].bits.uop.lrs2_rtype
connect slots_1.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[1].wakeup_ports[2].bits.uop.lrs1_rtype
connect slots_1.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[1].wakeup_ports[2].bits.uop.dst_rtype
connect slots_1.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[1].wakeup_ports[2].bits.uop.lrs3
connect slots_1.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[1].wakeup_ports[2].bits.uop.lrs2
connect slots_1.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[1].wakeup_ports[2].bits.uop.lrs1
connect slots_1.io.wakeup_ports[2].bits.uop.ldst, issue_slots[1].wakeup_ports[2].bits.uop.ldst
connect slots_1.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[1].wakeup_ports[2].bits.uop.ldst_is_rs1
connect slots_1.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[1].wakeup_ports[2].bits.uop.csr_cmd
connect slots_1.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[1].wakeup_ports[2].bits.uop.flush_on_commit
connect slots_1.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[1].wakeup_ports[2].bits.uop.is_unique
connect slots_1.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[1].wakeup_ports[2].bits.uop.uses_stq
connect slots_1.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[1].wakeup_ports[2].bits.uop.uses_ldq
connect slots_1.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[1].wakeup_ports[2].bits.uop.mem_signed
connect slots_1.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[1].wakeup_ports[2].bits.uop.mem_size
connect slots_1.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[1].wakeup_ports[2].bits.uop.mem_cmd
connect slots_1.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[1].wakeup_ports[2].bits.uop.exc_cause
connect slots_1.io.wakeup_ports[2].bits.uop.exception, issue_slots[1].wakeup_ports[2].bits.uop.exception
connect slots_1.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[1].wakeup_ports[2].bits.uop.stale_pdst
connect slots_1.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[1].wakeup_ports[2].bits.uop.ppred_busy
connect slots_1.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[1].wakeup_ports[2].bits.uop.prs3_busy
connect slots_1.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[1].wakeup_ports[2].bits.uop.prs2_busy
connect slots_1.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[1].wakeup_ports[2].bits.uop.prs1_busy
connect slots_1.io.wakeup_ports[2].bits.uop.ppred, issue_slots[1].wakeup_ports[2].bits.uop.ppred
connect slots_1.io.wakeup_ports[2].bits.uop.prs3, issue_slots[1].wakeup_ports[2].bits.uop.prs3
connect slots_1.io.wakeup_ports[2].bits.uop.prs2, issue_slots[1].wakeup_ports[2].bits.uop.prs2
connect slots_1.io.wakeup_ports[2].bits.uop.prs1, issue_slots[1].wakeup_ports[2].bits.uop.prs1
connect slots_1.io.wakeup_ports[2].bits.uop.pdst, issue_slots[1].wakeup_ports[2].bits.uop.pdst
connect slots_1.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[1].wakeup_ports[2].bits.uop.rxq_idx
connect slots_1.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[1].wakeup_ports[2].bits.uop.stq_idx
connect slots_1.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[1].wakeup_ports[2].bits.uop.ldq_idx
connect slots_1.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[1].wakeup_ports[2].bits.uop.rob_idx
connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.vec
connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.wflags
connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.sqrt
connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.div
connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.fma
connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe
connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.toint
connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.fromint
connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut
connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn
connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.swap23
connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.swap12
connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.ren3
connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.ren2
connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.ren1
connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.wen
connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.ldst
connect slots_1.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[1].wakeup_ports[2].bits.uop.op2_sel
connect slots_1.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[1].wakeup_ports[2].bits.uop.op1_sel
connect slots_1.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[1].wakeup_ports[2].bits.uop.imm_packed
connect slots_1.io.wakeup_ports[2].bits.uop.pimm, issue_slots[1].wakeup_ports[2].bits.uop.pimm
connect slots_1.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[1].wakeup_ports[2].bits.uop.imm_sel
connect slots_1.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[1].wakeup_ports[2].bits.uop.imm_rename
connect slots_1.io.wakeup_ports[2].bits.uop.taken, issue_slots[1].wakeup_ports[2].bits.uop.taken
connect slots_1.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[1].wakeup_ports[2].bits.uop.pc_lob
connect slots_1.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[1].wakeup_ports[2].bits.uop.edge_inst
connect slots_1.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[1].wakeup_ports[2].bits.uop.ftq_idx
connect slots_1.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[1].wakeup_ports[2].bits.uop.is_mov
connect slots_1.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[1].wakeup_ports[2].bits.uop.is_rocc
connect slots_1.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[1].wakeup_ports[2].bits.uop.is_sys_pc2epc
connect slots_1.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[1].wakeup_ports[2].bits.uop.is_eret
connect slots_1.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[1].wakeup_ports[2].bits.uop.is_amo
connect slots_1.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[1].wakeup_ports[2].bits.uop.is_sfence
connect slots_1.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[1].wakeup_ports[2].bits.uop.is_fencei
connect slots_1.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[1].wakeup_ports[2].bits.uop.is_fence
connect slots_1.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[1].wakeup_ports[2].bits.uop.is_sfb
connect slots_1.io.wakeup_ports[2].bits.uop.br_type, issue_slots[1].wakeup_ports[2].bits.uop.br_type
connect slots_1.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[1].wakeup_ports[2].bits.uop.br_tag
connect slots_1.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[1].wakeup_ports[2].bits.uop.br_mask
connect slots_1.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[1].wakeup_ports[2].bits.uop.dis_col_sel
connect slots_1.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[1].wakeup_ports[2].bits.uop.iw_p3_bypass_hint
connect slots_1.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[1].wakeup_ports[2].bits.uop.iw_p2_bypass_hint
connect slots_1.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[1].wakeup_ports[2].bits.uop.iw_p1_bypass_hint
connect slots_1.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[1].wakeup_ports[2].bits.uop.iw_p2_speculative_child
connect slots_1.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[1].wakeup_ports[2].bits.uop.iw_p1_speculative_child
connect slots_1.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[1].wakeup_ports[2].bits.uop.iw_issued_partial_dgen
connect slots_1.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[1].wakeup_ports[2].bits.uop.iw_issued_partial_agen
connect slots_1.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[1].wakeup_ports[2].bits.uop.iw_issued
connect slots_1.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[1].wakeup_ports[2].bits.uop.fu_code[0]
connect slots_1.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[1].wakeup_ports[2].bits.uop.fu_code[1]
connect slots_1.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[1].wakeup_ports[2].bits.uop.fu_code[2]
connect slots_1.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[1].wakeup_ports[2].bits.uop.fu_code[3]
connect slots_1.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[1].wakeup_ports[2].bits.uop.fu_code[4]
connect slots_1.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[1].wakeup_ports[2].bits.uop.fu_code[5]
connect slots_1.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[1].wakeup_ports[2].bits.uop.fu_code[6]
connect slots_1.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[1].wakeup_ports[2].bits.uop.fu_code[7]
connect slots_1.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[1].wakeup_ports[2].bits.uop.fu_code[8]
connect slots_1.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[1].wakeup_ports[2].bits.uop.fu_code[9]
connect slots_1.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[1].wakeup_ports[2].bits.uop.iq_type[0]
connect slots_1.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[1].wakeup_ports[2].bits.uop.iq_type[1]
connect slots_1.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[1].wakeup_ports[2].bits.uop.iq_type[2]
connect slots_1.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[1].wakeup_ports[2].bits.uop.iq_type[3]
connect slots_1.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[1].wakeup_ports[2].bits.uop.debug_pc
connect slots_1.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[1].wakeup_ports[2].bits.uop.is_rvc
connect slots_1.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[1].wakeup_ports[2].bits.uop.debug_inst
connect slots_1.io.wakeup_ports[2].bits.uop.inst, issue_slots[1].wakeup_ports[2].bits.uop.inst
connect slots_1.io.wakeup_ports[2].valid, issue_slots[1].wakeup_ports[2].valid
connect slots_1.io.wakeup_ports[3].bits.rebusy, issue_slots[1].wakeup_ports[3].bits.rebusy
connect slots_1.io.wakeup_ports[3].bits.speculative_mask, issue_slots[1].wakeup_ports[3].bits.speculative_mask
connect slots_1.io.wakeup_ports[3].bits.bypassable, issue_slots[1].wakeup_ports[3].bits.bypassable
connect slots_1.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[1].wakeup_ports[3].bits.uop.debug_tsrc
connect slots_1.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[1].wakeup_ports[3].bits.uop.debug_fsrc
connect slots_1.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[1].wakeup_ports[3].bits.uop.bp_xcpt_if
connect slots_1.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[1].wakeup_ports[3].bits.uop.bp_debug_if
connect slots_1.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[1].wakeup_ports[3].bits.uop.xcpt_ma_if
connect slots_1.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[1].wakeup_ports[3].bits.uop.xcpt_ae_if
connect slots_1.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[1].wakeup_ports[3].bits.uop.xcpt_pf_if
connect slots_1.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[1].wakeup_ports[3].bits.uop.fp_typ
connect slots_1.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[1].wakeup_ports[3].bits.uop.fp_rm
connect slots_1.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[1].wakeup_ports[3].bits.uop.fp_val
connect slots_1.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[1].wakeup_ports[3].bits.uop.fcn_op
connect slots_1.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[1].wakeup_ports[3].bits.uop.fcn_dw
connect slots_1.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[1].wakeup_ports[3].bits.uop.frs3_en
connect slots_1.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[1].wakeup_ports[3].bits.uop.lrs2_rtype
connect slots_1.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[1].wakeup_ports[3].bits.uop.lrs1_rtype
connect slots_1.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[1].wakeup_ports[3].bits.uop.dst_rtype
connect slots_1.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[1].wakeup_ports[3].bits.uop.lrs3
connect slots_1.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[1].wakeup_ports[3].bits.uop.lrs2
connect slots_1.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[1].wakeup_ports[3].bits.uop.lrs1
connect slots_1.io.wakeup_ports[3].bits.uop.ldst, issue_slots[1].wakeup_ports[3].bits.uop.ldst
connect slots_1.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[1].wakeup_ports[3].bits.uop.ldst_is_rs1
connect slots_1.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[1].wakeup_ports[3].bits.uop.csr_cmd
connect slots_1.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[1].wakeup_ports[3].bits.uop.flush_on_commit
connect slots_1.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[1].wakeup_ports[3].bits.uop.is_unique
connect slots_1.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[1].wakeup_ports[3].bits.uop.uses_stq
connect slots_1.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[1].wakeup_ports[3].bits.uop.uses_ldq
connect slots_1.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[1].wakeup_ports[3].bits.uop.mem_signed
connect slots_1.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[1].wakeup_ports[3].bits.uop.mem_size
connect slots_1.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[1].wakeup_ports[3].bits.uop.mem_cmd
connect slots_1.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[1].wakeup_ports[3].bits.uop.exc_cause
connect slots_1.io.wakeup_ports[3].bits.uop.exception, issue_slots[1].wakeup_ports[3].bits.uop.exception
connect slots_1.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[1].wakeup_ports[3].bits.uop.stale_pdst
connect slots_1.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[1].wakeup_ports[3].bits.uop.ppred_busy
connect slots_1.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[1].wakeup_ports[3].bits.uop.prs3_busy
connect slots_1.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[1].wakeup_ports[3].bits.uop.prs2_busy
connect slots_1.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[1].wakeup_ports[3].bits.uop.prs1_busy
connect slots_1.io.wakeup_ports[3].bits.uop.ppred, issue_slots[1].wakeup_ports[3].bits.uop.ppred
connect slots_1.io.wakeup_ports[3].bits.uop.prs3, issue_slots[1].wakeup_ports[3].bits.uop.prs3
connect slots_1.io.wakeup_ports[3].bits.uop.prs2, issue_slots[1].wakeup_ports[3].bits.uop.prs2
connect slots_1.io.wakeup_ports[3].bits.uop.prs1, issue_slots[1].wakeup_ports[3].bits.uop.prs1
connect slots_1.io.wakeup_ports[3].bits.uop.pdst, issue_slots[1].wakeup_ports[3].bits.uop.pdst
connect slots_1.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[1].wakeup_ports[3].bits.uop.rxq_idx
connect slots_1.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[1].wakeup_ports[3].bits.uop.stq_idx
connect slots_1.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[1].wakeup_ports[3].bits.uop.ldq_idx
connect slots_1.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[1].wakeup_ports[3].bits.uop.rob_idx
connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.vec
connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.wflags
connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.sqrt
connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.div
connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.fma
connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe
connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.toint
connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.fromint
connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut
connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn
connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.swap23
connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.swap12
connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.ren3
connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.ren2
connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.ren1
connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.wen
connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.ldst
connect slots_1.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[1].wakeup_ports[3].bits.uop.op2_sel
connect slots_1.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[1].wakeup_ports[3].bits.uop.op1_sel
connect slots_1.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[1].wakeup_ports[3].bits.uop.imm_packed
connect slots_1.io.wakeup_ports[3].bits.uop.pimm, issue_slots[1].wakeup_ports[3].bits.uop.pimm
connect slots_1.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[1].wakeup_ports[3].bits.uop.imm_sel
connect slots_1.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[1].wakeup_ports[3].bits.uop.imm_rename
connect slots_1.io.wakeup_ports[3].bits.uop.taken, issue_slots[1].wakeup_ports[3].bits.uop.taken
connect slots_1.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[1].wakeup_ports[3].bits.uop.pc_lob
connect slots_1.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[1].wakeup_ports[3].bits.uop.edge_inst
connect slots_1.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[1].wakeup_ports[3].bits.uop.ftq_idx
connect slots_1.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[1].wakeup_ports[3].bits.uop.is_mov
connect slots_1.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[1].wakeup_ports[3].bits.uop.is_rocc
connect slots_1.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[1].wakeup_ports[3].bits.uop.is_sys_pc2epc
connect slots_1.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[1].wakeup_ports[3].bits.uop.is_eret
connect slots_1.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[1].wakeup_ports[3].bits.uop.is_amo
connect slots_1.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[1].wakeup_ports[3].bits.uop.is_sfence
connect slots_1.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[1].wakeup_ports[3].bits.uop.is_fencei
connect slots_1.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[1].wakeup_ports[3].bits.uop.is_fence
connect slots_1.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[1].wakeup_ports[3].bits.uop.is_sfb
connect slots_1.io.wakeup_ports[3].bits.uop.br_type, issue_slots[1].wakeup_ports[3].bits.uop.br_type
connect slots_1.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[1].wakeup_ports[3].bits.uop.br_tag
connect slots_1.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[1].wakeup_ports[3].bits.uop.br_mask
connect slots_1.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[1].wakeup_ports[3].bits.uop.dis_col_sel
connect slots_1.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[1].wakeup_ports[3].bits.uop.iw_p3_bypass_hint
connect slots_1.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[1].wakeup_ports[3].bits.uop.iw_p2_bypass_hint
connect slots_1.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[1].wakeup_ports[3].bits.uop.iw_p1_bypass_hint
connect slots_1.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[1].wakeup_ports[3].bits.uop.iw_p2_speculative_child
connect slots_1.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[1].wakeup_ports[3].bits.uop.iw_p1_speculative_child
connect slots_1.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[1].wakeup_ports[3].bits.uop.iw_issued_partial_dgen
connect slots_1.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[1].wakeup_ports[3].bits.uop.iw_issued_partial_agen
connect slots_1.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[1].wakeup_ports[3].bits.uop.iw_issued
connect slots_1.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[1].wakeup_ports[3].bits.uop.fu_code[0]
connect slots_1.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[1].wakeup_ports[3].bits.uop.fu_code[1]
connect slots_1.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[1].wakeup_ports[3].bits.uop.fu_code[2]
connect slots_1.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[1].wakeup_ports[3].bits.uop.fu_code[3]
connect slots_1.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[1].wakeup_ports[3].bits.uop.fu_code[4]
connect slots_1.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[1].wakeup_ports[3].bits.uop.fu_code[5]
connect slots_1.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[1].wakeup_ports[3].bits.uop.fu_code[6]
connect slots_1.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[1].wakeup_ports[3].bits.uop.fu_code[7]
connect slots_1.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[1].wakeup_ports[3].bits.uop.fu_code[8]
connect slots_1.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[1].wakeup_ports[3].bits.uop.fu_code[9]
connect slots_1.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[1].wakeup_ports[3].bits.uop.iq_type[0]
connect slots_1.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[1].wakeup_ports[3].bits.uop.iq_type[1]
connect slots_1.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[1].wakeup_ports[3].bits.uop.iq_type[2]
connect slots_1.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[1].wakeup_ports[3].bits.uop.iq_type[3]
connect slots_1.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[1].wakeup_ports[3].bits.uop.debug_pc
connect slots_1.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[1].wakeup_ports[3].bits.uop.is_rvc
connect slots_1.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[1].wakeup_ports[3].bits.uop.debug_inst
connect slots_1.io.wakeup_ports[3].bits.uop.inst, issue_slots[1].wakeup_ports[3].bits.uop.inst
connect slots_1.io.wakeup_ports[3].valid, issue_slots[1].wakeup_ports[3].valid
connect slots_1.io.squash_grant, issue_slots[1].squash_grant
connect slots_1.io.clear, issue_slots[1].clear
connect slots_1.io.kill, issue_slots[1].kill
connect slots_1.io.brupdate.b2.target_offset, issue_slots[1].brupdate.b2.target_offset
connect slots_1.io.brupdate.b2.jalr_target, issue_slots[1].brupdate.b2.jalr_target
connect slots_1.io.brupdate.b2.pc_sel, issue_slots[1].brupdate.b2.pc_sel
connect slots_1.io.brupdate.b2.cfi_type, issue_slots[1].brupdate.b2.cfi_type
connect slots_1.io.brupdate.b2.taken, issue_slots[1].brupdate.b2.taken
connect slots_1.io.brupdate.b2.mispredict, issue_slots[1].brupdate.b2.mispredict
connect slots_1.io.brupdate.b2.uop.debug_tsrc, issue_slots[1].brupdate.b2.uop.debug_tsrc
connect slots_1.io.brupdate.b2.uop.debug_fsrc, issue_slots[1].brupdate.b2.uop.debug_fsrc
connect slots_1.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[1].brupdate.b2.uop.bp_xcpt_if
connect slots_1.io.brupdate.b2.uop.bp_debug_if, issue_slots[1].brupdate.b2.uop.bp_debug_if
connect slots_1.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[1].brupdate.b2.uop.xcpt_ma_if
connect slots_1.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[1].brupdate.b2.uop.xcpt_ae_if
connect slots_1.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[1].brupdate.b2.uop.xcpt_pf_if
connect slots_1.io.brupdate.b2.uop.fp_typ, issue_slots[1].brupdate.b2.uop.fp_typ
connect slots_1.io.brupdate.b2.uop.fp_rm, issue_slots[1].brupdate.b2.uop.fp_rm
connect slots_1.io.brupdate.b2.uop.fp_val, issue_slots[1].brupdate.b2.uop.fp_val
connect slots_1.io.brupdate.b2.uop.fcn_op, issue_slots[1].brupdate.b2.uop.fcn_op
connect slots_1.io.brupdate.b2.uop.fcn_dw, issue_slots[1].brupdate.b2.uop.fcn_dw
connect slots_1.io.brupdate.b2.uop.frs3_en, issue_slots[1].brupdate.b2.uop.frs3_en
connect slots_1.io.brupdate.b2.uop.lrs2_rtype, issue_slots[1].brupdate.b2.uop.lrs2_rtype
connect slots_1.io.brupdate.b2.uop.lrs1_rtype, issue_slots[1].brupdate.b2.uop.lrs1_rtype
connect slots_1.io.brupdate.b2.uop.dst_rtype, issue_slots[1].brupdate.b2.uop.dst_rtype
connect slots_1.io.brupdate.b2.uop.lrs3, issue_slots[1].brupdate.b2.uop.lrs3
connect slots_1.io.brupdate.b2.uop.lrs2, issue_slots[1].brupdate.b2.uop.lrs2
connect slots_1.io.brupdate.b2.uop.lrs1, issue_slots[1].brupdate.b2.uop.lrs1
connect slots_1.io.brupdate.b2.uop.ldst, issue_slots[1].brupdate.b2.uop.ldst
connect slots_1.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[1].brupdate.b2.uop.ldst_is_rs1
connect slots_1.io.brupdate.b2.uop.csr_cmd, issue_slots[1].brupdate.b2.uop.csr_cmd
connect slots_1.io.brupdate.b2.uop.flush_on_commit, issue_slots[1].brupdate.b2.uop.flush_on_commit
connect slots_1.io.brupdate.b2.uop.is_unique, issue_slots[1].brupdate.b2.uop.is_unique
connect slots_1.io.brupdate.b2.uop.uses_stq, issue_slots[1].brupdate.b2.uop.uses_stq
connect slots_1.io.brupdate.b2.uop.uses_ldq, issue_slots[1].brupdate.b2.uop.uses_ldq
connect slots_1.io.brupdate.b2.uop.mem_signed, issue_slots[1].brupdate.b2.uop.mem_signed
connect slots_1.io.brupdate.b2.uop.mem_size, issue_slots[1].brupdate.b2.uop.mem_size
connect slots_1.io.brupdate.b2.uop.mem_cmd, issue_slots[1].brupdate.b2.uop.mem_cmd
connect slots_1.io.brupdate.b2.uop.exc_cause, issue_slots[1].brupdate.b2.uop.exc_cause
connect slots_1.io.brupdate.b2.uop.exception, issue_slots[1].brupdate.b2.uop.exception
connect slots_1.io.brupdate.b2.uop.stale_pdst, issue_slots[1].brupdate.b2.uop.stale_pdst
connect slots_1.io.brupdate.b2.uop.ppred_busy, issue_slots[1].brupdate.b2.uop.ppred_busy
connect slots_1.io.brupdate.b2.uop.prs3_busy, issue_slots[1].brupdate.b2.uop.prs3_busy
connect slots_1.io.brupdate.b2.uop.prs2_busy, issue_slots[1].brupdate.b2.uop.prs2_busy
connect slots_1.io.brupdate.b2.uop.prs1_busy, issue_slots[1].brupdate.b2.uop.prs1_busy
connect slots_1.io.brupdate.b2.uop.ppred, issue_slots[1].brupdate.b2.uop.ppred
connect slots_1.io.brupdate.b2.uop.prs3, issue_slots[1].brupdate.b2.uop.prs3
connect slots_1.io.brupdate.b2.uop.prs2, issue_slots[1].brupdate.b2.uop.prs2
connect slots_1.io.brupdate.b2.uop.prs1, issue_slots[1].brupdate.b2.uop.prs1
connect slots_1.io.brupdate.b2.uop.pdst, issue_slots[1].brupdate.b2.uop.pdst
connect slots_1.io.brupdate.b2.uop.rxq_idx, issue_slots[1].brupdate.b2.uop.rxq_idx
connect slots_1.io.brupdate.b2.uop.stq_idx, issue_slots[1].brupdate.b2.uop.stq_idx
connect slots_1.io.brupdate.b2.uop.ldq_idx, issue_slots[1].brupdate.b2.uop.ldq_idx
connect slots_1.io.brupdate.b2.uop.rob_idx, issue_slots[1].brupdate.b2.uop.rob_idx
connect slots_1.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[1].brupdate.b2.uop.fp_ctrl.vec
connect slots_1.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[1].brupdate.b2.uop.fp_ctrl.wflags
connect slots_1.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[1].brupdate.b2.uop.fp_ctrl.sqrt
connect slots_1.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[1].brupdate.b2.uop.fp_ctrl.div
connect slots_1.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[1].brupdate.b2.uop.fp_ctrl.fma
connect slots_1.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[1].brupdate.b2.uop.fp_ctrl.fastpipe
connect slots_1.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[1].brupdate.b2.uop.fp_ctrl.toint
connect slots_1.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[1].brupdate.b2.uop.fp_ctrl.fromint
connect slots_1.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[1].brupdate.b2.uop.fp_ctrl.typeTagOut
connect slots_1.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[1].brupdate.b2.uop.fp_ctrl.typeTagIn
connect slots_1.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[1].brupdate.b2.uop.fp_ctrl.swap23
connect slots_1.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[1].brupdate.b2.uop.fp_ctrl.swap12
connect slots_1.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[1].brupdate.b2.uop.fp_ctrl.ren3
connect slots_1.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[1].brupdate.b2.uop.fp_ctrl.ren2
connect slots_1.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[1].brupdate.b2.uop.fp_ctrl.ren1
connect slots_1.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[1].brupdate.b2.uop.fp_ctrl.wen
connect slots_1.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[1].brupdate.b2.uop.fp_ctrl.ldst
connect slots_1.io.brupdate.b2.uop.op2_sel, issue_slots[1].brupdate.b2.uop.op2_sel
connect slots_1.io.brupdate.b2.uop.op1_sel, issue_slots[1].brupdate.b2.uop.op1_sel
connect slots_1.io.brupdate.b2.uop.imm_packed, issue_slots[1].brupdate.b2.uop.imm_packed
connect slots_1.io.brupdate.b2.uop.pimm, issue_slots[1].brupdate.b2.uop.pimm
connect slots_1.io.brupdate.b2.uop.imm_sel, issue_slots[1].brupdate.b2.uop.imm_sel
connect slots_1.io.brupdate.b2.uop.imm_rename, issue_slots[1].brupdate.b2.uop.imm_rename
connect slots_1.io.brupdate.b2.uop.taken, issue_slots[1].brupdate.b2.uop.taken
connect slots_1.io.brupdate.b2.uop.pc_lob, issue_slots[1].brupdate.b2.uop.pc_lob
connect slots_1.io.brupdate.b2.uop.edge_inst, issue_slots[1].brupdate.b2.uop.edge_inst
connect slots_1.io.brupdate.b2.uop.ftq_idx, issue_slots[1].brupdate.b2.uop.ftq_idx
connect slots_1.io.brupdate.b2.uop.is_mov, issue_slots[1].brupdate.b2.uop.is_mov
connect slots_1.io.brupdate.b2.uop.is_rocc, issue_slots[1].brupdate.b2.uop.is_rocc
connect slots_1.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[1].brupdate.b2.uop.is_sys_pc2epc
connect slots_1.io.brupdate.b2.uop.is_eret, issue_slots[1].brupdate.b2.uop.is_eret
connect slots_1.io.brupdate.b2.uop.is_amo, issue_slots[1].brupdate.b2.uop.is_amo
connect slots_1.io.brupdate.b2.uop.is_sfence, issue_slots[1].brupdate.b2.uop.is_sfence
connect slots_1.io.brupdate.b2.uop.is_fencei, issue_slots[1].brupdate.b2.uop.is_fencei
connect slots_1.io.brupdate.b2.uop.is_fence, issue_slots[1].brupdate.b2.uop.is_fence
connect slots_1.io.brupdate.b2.uop.is_sfb, issue_slots[1].brupdate.b2.uop.is_sfb
connect slots_1.io.brupdate.b2.uop.br_type, issue_slots[1].brupdate.b2.uop.br_type
connect slots_1.io.brupdate.b2.uop.br_tag, issue_slots[1].brupdate.b2.uop.br_tag
connect slots_1.io.brupdate.b2.uop.br_mask, issue_slots[1].brupdate.b2.uop.br_mask
connect slots_1.io.brupdate.b2.uop.dis_col_sel, issue_slots[1].brupdate.b2.uop.dis_col_sel
connect slots_1.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[1].brupdate.b2.uop.iw_p3_bypass_hint
connect slots_1.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[1].brupdate.b2.uop.iw_p2_bypass_hint
connect slots_1.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[1].brupdate.b2.uop.iw_p1_bypass_hint
connect slots_1.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[1].brupdate.b2.uop.iw_p2_speculative_child
connect slots_1.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[1].brupdate.b2.uop.iw_p1_speculative_child
connect slots_1.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[1].brupdate.b2.uop.iw_issued_partial_dgen
connect slots_1.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[1].brupdate.b2.uop.iw_issued_partial_agen
connect slots_1.io.brupdate.b2.uop.iw_issued, issue_slots[1].brupdate.b2.uop.iw_issued
connect slots_1.io.brupdate.b2.uop.fu_code[0], issue_slots[1].brupdate.b2.uop.fu_code[0]
connect slots_1.io.brupdate.b2.uop.fu_code[1], issue_slots[1].brupdate.b2.uop.fu_code[1]
connect slots_1.io.brupdate.b2.uop.fu_code[2], issue_slots[1].brupdate.b2.uop.fu_code[2]
connect slots_1.io.brupdate.b2.uop.fu_code[3], issue_slots[1].brupdate.b2.uop.fu_code[3]
connect slots_1.io.brupdate.b2.uop.fu_code[4], issue_slots[1].brupdate.b2.uop.fu_code[4]
connect slots_1.io.brupdate.b2.uop.fu_code[5], issue_slots[1].brupdate.b2.uop.fu_code[5]
connect slots_1.io.brupdate.b2.uop.fu_code[6], issue_slots[1].brupdate.b2.uop.fu_code[6]
connect slots_1.io.brupdate.b2.uop.fu_code[7], issue_slots[1].brupdate.b2.uop.fu_code[7]
connect slots_1.io.brupdate.b2.uop.fu_code[8], issue_slots[1].brupdate.b2.uop.fu_code[8]
connect slots_1.io.brupdate.b2.uop.fu_code[9], issue_slots[1].brupdate.b2.uop.fu_code[9]
connect slots_1.io.brupdate.b2.uop.iq_type[0], issue_slots[1].brupdate.b2.uop.iq_type[0]
connect slots_1.io.brupdate.b2.uop.iq_type[1], issue_slots[1].brupdate.b2.uop.iq_type[1]
connect slots_1.io.brupdate.b2.uop.iq_type[2], issue_slots[1].brupdate.b2.uop.iq_type[2]
connect slots_1.io.brupdate.b2.uop.iq_type[3], issue_slots[1].brupdate.b2.uop.iq_type[3]
connect slots_1.io.brupdate.b2.uop.debug_pc, issue_slots[1].brupdate.b2.uop.debug_pc
connect slots_1.io.brupdate.b2.uop.is_rvc, issue_slots[1].brupdate.b2.uop.is_rvc
connect slots_1.io.brupdate.b2.uop.debug_inst, issue_slots[1].brupdate.b2.uop.debug_inst
connect slots_1.io.brupdate.b2.uop.inst, issue_slots[1].brupdate.b2.uop.inst
connect slots_1.io.brupdate.b1.mispredict_mask, issue_slots[1].brupdate.b1.mispredict_mask
connect slots_1.io.brupdate.b1.resolve_mask, issue_slots[1].brupdate.b1.resolve_mask
connect issue_slots[1].out_uop.debug_tsrc, slots_1.io.out_uop.debug_tsrc
connect issue_slots[1].out_uop.debug_fsrc, slots_1.io.out_uop.debug_fsrc
connect issue_slots[1].out_uop.bp_xcpt_if, slots_1.io.out_uop.bp_xcpt_if
connect issue_slots[1].out_uop.bp_debug_if, slots_1.io.out_uop.bp_debug_if
connect issue_slots[1].out_uop.xcpt_ma_if, slots_1.io.out_uop.xcpt_ma_if
connect issue_slots[1].out_uop.xcpt_ae_if, slots_1.io.out_uop.xcpt_ae_if
connect issue_slots[1].out_uop.xcpt_pf_if, slots_1.io.out_uop.xcpt_pf_if
connect issue_slots[1].out_uop.fp_typ, slots_1.io.out_uop.fp_typ
connect issue_slots[1].out_uop.fp_rm, slots_1.io.out_uop.fp_rm
connect issue_slots[1].out_uop.fp_val, slots_1.io.out_uop.fp_val
connect issue_slots[1].out_uop.fcn_op, slots_1.io.out_uop.fcn_op
connect issue_slots[1].out_uop.fcn_dw, slots_1.io.out_uop.fcn_dw
connect issue_slots[1].out_uop.frs3_en, slots_1.io.out_uop.frs3_en
connect issue_slots[1].out_uop.lrs2_rtype, slots_1.io.out_uop.lrs2_rtype
connect issue_slots[1].out_uop.lrs1_rtype, slots_1.io.out_uop.lrs1_rtype
connect issue_slots[1].out_uop.dst_rtype, slots_1.io.out_uop.dst_rtype
connect issue_slots[1].out_uop.lrs3, slots_1.io.out_uop.lrs3
connect issue_slots[1].out_uop.lrs2, slots_1.io.out_uop.lrs2
connect issue_slots[1].out_uop.lrs1, slots_1.io.out_uop.lrs1
connect issue_slots[1].out_uop.ldst, slots_1.io.out_uop.ldst
connect issue_slots[1].out_uop.ldst_is_rs1, slots_1.io.out_uop.ldst_is_rs1
connect issue_slots[1].out_uop.csr_cmd, slots_1.io.out_uop.csr_cmd
connect issue_slots[1].out_uop.flush_on_commit, slots_1.io.out_uop.flush_on_commit
connect issue_slots[1].out_uop.is_unique, slots_1.io.out_uop.is_unique
connect issue_slots[1].out_uop.uses_stq, slots_1.io.out_uop.uses_stq
connect issue_slots[1].out_uop.uses_ldq, slots_1.io.out_uop.uses_ldq
connect issue_slots[1].out_uop.mem_signed, slots_1.io.out_uop.mem_signed
connect issue_slots[1].out_uop.mem_size, slots_1.io.out_uop.mem_size
connect issue_slots[1].out_uop.mem_cmd, slots_1.io.out_uop.mem_cmd
connect issue_slots[1].out_uop.exc_cause, slots_1.io.out_uop.exc_cause
connect issue_slots[1].out_uop.exception, slots_1.io.out_uop.exception
connect issue_slots[1].out_uop.stale_pdst, slots_1.io.out_uop.stale_pdst
connect issue_slots[1].out_uop.ppred_busy, slots_1.io.out_uop.ppred_busy
connect issue_slots[1].out_uop.prs3_busy, slots_1.io.out_uop.prs3_busy
connect issue_slots[1].out_uop.prs2_busy, slots_1.io.out_uop.prs2_busy
connect issue_slots[1].out_uop.prs1_busy, slots_1.io.out_uop.prs1_busy
connect issue_slots[1].out_uop.ppred, slots_1.io.out_uop.ppred
connect issue_slots[1].out_uop.prs3, slots_1.io.out_uop.prs3
connect issue_slots[1].out_uop.prs2, slots_1.io.out_uop.prs2
connect issue_slots[1].out_uop.prs1, slots_1.io.out_uop.prs1
connect issue_slots[1].out_uop.pdst, slots_1.io.out_uop.pdst
connect issue_slots[1].out_uop.rxq_idx, slots_1.io.out_uop.rxq_idx
connect issue_slots[1].out_uop.stq_idx, slots_1.io.out_uop.stq_idx
connect issue_slots[1].out_uop.ldq_idx, slots_1.io.out_uop.ldq_idx
connect issue_slots[1].out_uop.rob_idx, slots_1.io.out_uop.rob_idx
connect issue_slots[1].out_uop.fp_ctrl.vec, slots_1.io.out_uop.fp_ctrl.vec
connect issue_slots[1].out_uop.fp_ctrl.wflags, slots_1.io.out_uop.fp_ctrl.wflags
connect issue_slots[1].out_uop.fp_ctrl.sqrt, slots_1.io.out_uop.fp_ctrl.sqrt
connect issue_slots[1].out_uop.fp_ctrl.div, slots_1.io.out_uop.fp_ctrl.div
connect issue_slots[1].out_uop.fp_ctrl.fma, slots_1.io.out_uop.fp_ctrl.fma
connect issue_slots[1].out_uop.fp_ctrl.fastpipe, slots_1.io.out_uop.fp_ctrl.fastpipe
connect issue_slots[1].out_uop.fp_ctrl.toint, slots_1.io.out_uop.fp_ctrl.toint
connect issue_slots[1].out_uop.fp_ctrl.fromint, slots_1.io.out_uop.fp_ctrl.fromint
connect issue_slots[1].out_uop.fp_ctrl.typeTagOut, slots_1.io.out_uop.fp_ctrl.typeTagOut
connect issue_slots[1].out_uop.fp_ctrl.typeTagIn, slots_1.io.out_uop.fp_ctrl.typeTagIn
connect issue_slots[1].out_uop.fp_ctrl.swap23, slots_1.io.out_uop.fp_ctrl.swap23
connect issue_slots[1].out_uop.fp_ctrl.swap12, slots_1.io.out_uop.fp_ctrl.swap12
connect issue_slots[1].out_uop.fp_ctrl.ren3, slots_1.io.out_uop.fp_ctrl.ren3
connect issue_slots[1].out_uop.fp_ctrl.ren2, slots_1.io.out_uop.fp_ctrl.ren2
connect issue_slots[1].out_uop.fp_ctrl.ren1, slots_1.io.out_uop.fp_ctrl.ren1
connect issue_slots[1].out_uop.fp_ctrl.wen, slots_1.io.out_uop.fp_ctrl.wen
connect issue_slots[1].out_uop.fp_ctrl.ldst, slots_1.io.out_uop.fp_ctrl.ldst
connect issue_slots[1].out_uop.op2_sel, slots_1.io.out_uop.op2_sel
connect issue_slots[1].out_uop.op1_sel, slots_1.io.out_uop.op1_sel
connect issue_slots[1].out_uop.imm_packed, slots_1.io.out_uop.imm_packed
connect issue_slots[1].out_uop.pimm, slots_1.io.out_uop.pimm
connect issue_slots[1].out_uop.imm_sel, slots_1.io.out_uop.imm_sel
connect issue_slots[1].out_uop.imm_rename, slots_1.io.out_uop.imm_rename
connect issue_slots[1].out_uop.taken, slots_1.io.out_uop.taken
connect issue_slots[1].out_uop.pc_lob, slots_1.io.out_uop.pc_lob
connect issue_slots[1].out_uop.edge_inst, slots_1.io.out_uop.edge_inst
connect issue_slots[1].out_uop.ftq_idx, slots_1.io.out_uop.ftq_idx
connect issue_slots[1].out_uop.is_mov, slots_1.io.out_uop.is_mov
connect issue_slots[1].out_uop.is_rocc, slots_1.io.out_uop.is_rocc
connect issue_slots[1].out_uop.is_sys_pc2epc, slots_1.io.out_uop.is_sys_pc2epc
connect issue_slots[1].out_uop.is_eret, slots_1.io.out_uop.is_eret
connect issue_slots[1].out_uop.is_amo, slots_1.io.out_uop.is_amo
connect issue_slots[1].out_uop.is_sfence, slots_1.io.out_uop.is_sfence
connect issue_slots[1].out_uop.is_fencei, slots_1.io.out_uop.is_fencei
connect issue_slots[1].out_uop.is_fence, slots_1.io.out_uop.is_fence
connect issue_slots[1].out_uop.is_sfb, slots_1.io.out_uop.is_sfb
connect issue_slots[1].out_uop.br_type, slots_1.io.out_uop.br_type
connect issue_slots[1].out_uop.br_tag, slots_1.io.out_uop.br_tag
connect issue_slots[1].out_uop.br_mask, slots_1.io.out_uop.br_mask
connect issue_slots[1].out_uop.dis_col_sel, slots_1.io.out_uop.dis_col_sel
connect issue_slots[1].out_uop.iw_p3_bypass_hint, slots_1.io.out_uop.iw_p3_bypass_hint
connect issue_slots[1].out_uop.iw_p2_bypass_hint, slots_1.io.out_uop.iw_p2_bypass_hint
connect issue_slots[1].out_uop.iw_p1_bypass_hint, slots_1.io.out_uop.iw_p1_bypass_hint
connect issue_slots[1].out_uop.iw_p2_speculative_child, slots_1.io.out_uop.iw_p2_speculative_child
connect issue_slots[1].out_uop.iw_p1_speculative_child, slots_1.io.out_uop.iw_p1_speculative_child
connect issue_slots[1].out_uop.iw_issued_partial_dgen, slots_1.io.out_uop.iw_issued_partial_dgen
connect issue_slots[1].out_uop.iw_issued_partial_agen, slots_1.io.out_uop.iw_issued_partial_agen
connect issue_slots[1].out_uop.iw_issued, slots_1.io.out_uop.iw_issued
connect issue_slots[1].out_uop.fu_code[0], slots_1.io.out_uop.fu_code[0]
connect issue_slots[1].out_uop.fu_code[1], slots_1.io.out_uop.fu_code[1]
connect issue_slots[1].out_uop.fu_code[2], slots_1.io.out_uop.fu_code[2]
connect issue_slots[1].out_uop.fu_code[3], slots_1.io.out_uop.fu_code[3]
connect issue_slots[1].out_uop.fu_code[4], slots_1.io.out_uop.fu_code[4]
connect issue_slots[1].out_uop.fu_code[5], slots_1.io.out_uop.fu_code[5]
connect issue_slots[1].out_uop.fu_code[6], slots_1.io.out_uop.fu_code[6]
connect issue_slots[1].out_uop.fu_code[7], slots_1.io.out_uop.fu_code[7]
connect issue_slots[1].out_uop.fu_code[8], slots_1.io.out_uop.fu_code[8]
connect issue_slots[1].out_uop.fu_code[9], slots_1.io.out_uop.fu_code[9]
connect issue_slots[1].out_uop.iq_type[0], slots_1.io.out_uop.iq_type[0]
connect issue_slots[1].out_uop.iq_type[1], slots_1.io.out_uop.iq_type[1]
connect issue_slots[1].out_uop.iq_type[2], slots_1.io.out_uop.iq_type[2]
connect issue_slots[1].out_uop.iq_type[3], slots_1.io.out_uop.iq_type[3]
connect issue_slots[1].out_uop.debug_pc, slots_1.io.out_uop.debug_pc
connect issue_slots[1].out_uop.is_rvc, slots_1.io.out_uop.is_rvc
connect issue_slots[1].out_uop.debug_inst, slots_1.io.out_uop.debug_inst
connect issue_slots[1].out_uop.inst, slots_1.io.out_uop.inst
connect slots_1.io.in_uop.bits.debug_tsrc, issue_slots[1].in_uop.bits.debug_tsrc
connect slots_1.io.in_uop.bits.debug_fsrc, issue_slots[1].in_uop.bits.debug_fsrc
connect slots_1.io.in_uop.bits.bp_xcpt_if, issue_slots[1].in_uop.bits.bp_xcpt_if
connect slots_1.io.in_uop.bits.bp_debug_if, issue_slots[1].in_uop.bits.bp_debug_if
connect slots_1.io.in_uop.bits.xcpt_ma_if, issue_slots[1].in_uop.bits.xcpt_ma_if
connect slots_1.io.in_uop.bits.xcpt_ae_if, issue_slots[1].in_uop.bits.xcpt_ae_if
connect slots_1.io.in_uop.bits.xcpt_pf_if, issue_slots[1].in_uop.bits.xcpt_pf_if
connect slots_1.io.in_uop.bits.fp_typ, issue_slots[1].in_uop.bits.fp_typ
connect slots_1.io.in_uop.bits.fp_rm, issue_slots[1].in_uop.bits.fp_rm
connect slots_1.io.in_uop.bits.fp_val, issue_slots[1].in_uop.bits.fp_val
connect slots_1.io.in_uop.bits.fcn_op, issue_slots[1].in_uop.bits.fcn_op
connect slots_1.io.in_uop.bits.fcn_dw, issue_slots[1].in_uop.bits.fcn_dw
connect slots_1.io.in_uop.bits.frs3_en, issue_slots[1].in_uop.bits.frs3_en
connect slots_1.io.in_uop.bits.lrs2_rtype, issue_slots[1].in_uop.bits.lrs2_rtype
connect slots_1.io.in_uop.bits.lrs1_rtype, issue_slots[1].in_uop.bits.lrs1_rtype
connect slots_1.io.in_uop.bits.dst_rtype, issue_slots[1].in_uop.bits.dst_rtype
connect slots_1.io.in_uop.bits.lrs3, issue_slots[1].in_uop.bits.lrs3
connect slots_1.io.in_uop.bits.lrs2, issue_slots[1].in_uop.bits.lrs2
connect slots_1.io.in_uop.bits.lrs1, issue_slots[1].in_uop.bits.lrs1
connect slots_1.io.in_uop.bits.ldst, issue_slots[1].in_uop.bits.ldst
connect slots_1.io.in_uop.bits.ldst_is_rs1, issue_slots[1].in_uop.bits.ldst_is_rs1
connect slots_1.io.in_uop.bits.csr_cmd, issue_slots[1].in_uop.bits.csr_cmd
connect slots_1.io.in_uop.bits.flush_on_commit, issue_slots[1].in_uop.bits.flush_on_commit
connect slots_1.io.in_uop.bits.is_unique, issue_slots[1].in_uop.bits.is_unique
connect slots_1.io.in_uop.bits.uses_stq, issue_slots[1].in_uop.bits.uses_stq
connect slots_1.io.in_uop.bits.uses_ldq, issue_slots[1].in_uop.bits.uses_ldq
connect slots_1.io.in_uop.bits.mem_signed, issue_slots[1].in_uop.bits.mem_signed
connect slots_1.io.in_uop.bits.mem_size, issue_slots[1].in_uop.bits.mem_size
connect slots_1.io.in_uop.bits.mem_cmd, issue_slots[1].in_uop.bits.mem_cmd
connect slots_1.io.in_uop.bits.exc_cause, issue_slots[1].in_uop.bits.exc_cause
connect slots_1.io.in_uop.bits.exception, issue_slots[1].in_uop.bits.exception
connect slots_1.io.in_uop.bits.stale_pdst, issue_slots[1].in_uop.bits.stale_pdst
connect slots_1.io.in_uop.bits.ppred_busy, issue_slots[1].in_uop.bits.ppred_busy
connect slots_1.io.in_uop.bits.prs3_busy, issue_slots[1].in_uop.bits.prs3_busy
connect slots_1.io.in_uop.bits.prs2_busy, issue_slots[1].in_uop.bits.prs2_busy
connect slots_1.io.in_uop.bits.prs1_busy, issue_slots[1].in_uop.bits.prs1_busy
connect slots_1.io.in_uop.bits.ppred, issue_slots[1].in_uop.bits.ppred
connect slots_1.io.in_uop.bits.prs3, issue_slots[1].in_uop.bits.prs3
connect slots_1.io.in_uop.bits.prs2, issue_slots[1].in_uop.bits.prs2
connect slots_1.io.in_uop.bits.prs1, issue_slots[1].in_uop.bits.prs1
connect slots_1.io.in_uop.bits.pdst, issue_slots[1].in_uop.bits.pdst
connect slots_1.io.in_uop.bits.rxq_idx, issue_slots[1].in_uop.bits.rxq_idx
connect slots_1.io.in_uop.bits.stq_idx, issue_slots[1].in_uop.bits.stq_idx
connect slots_1.io.in_uop.bits.ldq_idx, issue_slots[1].in_uop.bits.ldq_idx
connect slots_1.io.in_uop.bits.rob_idx, issue_slots[1].in_uop.bits.rob_idx
connect slots_1.io.in_uop.bits.fp_ctrl.vec, issue_slots[1].in_uop.bits.fp_ctrl.vec
connect slots_1.io.in_uop.bits.fp_ctrl.wflags, issue_slots[1].in_uop.bits.fp_ctrl.wflags
connect slots_1.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[1].in_uop.bits.fp_ctrl.sqrt
connect slots_1.io.in_uop.bits.fp_ctrl.div, issue_slots[1].in_uop.bits.fp_ctrl.div
connect slots_1.io.in_uop.bits.fp_ctrl.fma, issue_slots[1].in_uop.bits.fp_ctrl.fma
connect slots_1.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[1].in_uop.bits.fp_ctrl.fastpipe
connect slots_1.io.in_uop.bits.fp_ctrl.toint, issue_slots[1].in_uop.bits.fp_ctrl.toint
connect slots_1.io.in_uop.bits.fp_ctrl.fromint, issue_slots[1].in_uop.bits.fp_ctrl.fromint
connect slots_1.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[1].in_uop.bits.fp_ctrl.typeTagOut
connect slots_1.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[1].in_uop.bits.fp_ctrl.typeTagIn
connect slots_1.io.in_uop.bits.fp_ctrl.swap23, issue_slots[1].in_uop.bits.fp_ctrl.swap23
connect slots_1.io.in_uop.bits.fp_ctrl.swap12, issue_slots[1].in_uop.bits.fp_ctrl.swap12
connect slots_1.io.in_uop.bits.fp_ctrl.ren3, issue_slots[1].in_uop.bits.fp_ctrl.ren3
connect slots_1.io.in_uop.bits.fp_ctrl.ren2, issue_slots[1].in_uop.bits.fp_ctrl.ren2
connect slots_1.io.in_uop.bits.fp_ctrl.ren1, issue_slots[1].in_uop.bits.fp_ctrl.ren1
connect slots_1.io.in_uop.bits.fp_ctrl.wen, issue_slots[1].in_uop.bits.fp_ctrl.wen
connect slots_1.io.in_uop.bits.fp_ctrl.ldst, issue_slots[1].in_uop.bits.fp_ctrl.ldst
connect slots_1.io.in_uop.bits.op2_sel, issue_slots[1].in_uop.bits.op2_sel
connect slots_1.io.in_uop.bits.op1_sel, issue_slots[1].in_uop.bits.op1_sel
connect slots_1.io.in_uop.bits.imm_packed, issue_slots[1].in_uop.bits.imm_packed
connect slots_1.io.in_uop.bits.pimm, issue_slots[1].in_uop.bits.pimm
connect slots_1.io.in_uop.bits.imm_sel, issue_slots[1].in_uop.bits.imm_sel
connect slots_1.io.in_uop.bits.imm_rename, issue_slots[1].in_uop.bits.imm_rename
connect slots_1.io.in_uop.bits.taken, issue_slots[1].in_uop.bits.taken
connect slots_1.io.in_uop.bits.pc_lob, issue_slots[1].in_uop.bits.pc_lob
connect slots_1.io.in_uop.bits.edge_inst, issue_slots[1].in_uop.bits.edge_inst
connect slots_1.io.in_uop.bits.ftq_idx, issue_slots[1].in_uop.bits.ftq_idx
connect slots_1.io.in_uop.bits.is_mov, issue_slots[1].in_uop.bits.is_mov
connect slots_1.io.in_uop.bits.is_rocc, issue_slots[1].in_uop.bits.is_rocc
connect slots_1.io.in_uop.bits.is_sys_pc2epc, issue_slots[1].in_uop.bits.is_sys_pc2epc
connect slots_1.io.in_uop.bits.is_eret, issue_slots[1].in_uop.bits.is_eret
connect slots_1.io.in_uop.bits.is_amo, issue_slots[1].in_uop.bits.is_amo
connect slots_1.io.in_uop.bits.is_sfence, issue_slots[1].in_uop.bits.is_sfence
connect slots_1.io.in_uop.bits.is_fencei, issue_slots[1].in_uop.bits.is_fencei
connect slots_1.io.in_uop.bits.is_fence, issue_slots[1].in_uop.bits.is_fence
connect slots_1.io.in_uop.bits.is_sfb, issue_slots[1].in_uop.bits.is_sfb
connect slots_1.io.in_uop.bits.br_type, issue_slots[1].in_uop.bits.br_type
connect slots_1.io.in_uop.bits.br_tag, issue_slots[1].in_uop.bits.br_tag
connect slots_1.io.in_uop.bits.br_mask, issue_slots[1].in_uop.bits.br_mask
connect slots_1.io.in_uop.bits.dis_col_sel, issue_slots[1].in_uop.bits.dis_col_sel
connect slots_1.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[1].in_uop.bits.iw_p3_bypass_hint
connect slots_1.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[1].in_uop.bits.iw_p2_bypass_hint
connect slots_1.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[1].in_uop.bits.iw_p1_bypass_hint
connect slots_1.io.in_uop.bits.iw_p2_speculative_child, issue_slots[1].in_uop.bits.iw_p2_speculative_child
connect slots_1.io.in_uop.bits.iw_p1_speculative_child, issue_slots[1].in_uop.bits.iw_p1_speculative_child
connect slots_1.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[1].in_uop.bits.iw_issued_partial_dgen
connect slots_1.io.in_uop.bits.iw_issued_partial_agen, issue_slots[1].in_uop.bits.iw_issued_partial_agen
connect slots_1.io.in_uop.bits.iw_issued, issue_slots[1].in_uop.bits.iw_issued
connect slots_1.io.in_uop.bits.fu_code[0], issue_slots[1].in_uop.bits.fu_code[0]
connect slots_1.io.in_uop.bits.fu_code[1], issue_slots[1].in_uop.bits.fu_code[1]
connect slots_1.io.in_uop.bits.fu_code[2], issue_slots[1].in_uop.bits.fu_code[2]
connect slots_1.io.in_uop.bits.fu_code[3], issue_slots[1].in_uop.bits.fu_code[3]
connect slots_1.io.in_uop.bits.fu_code[4], issue_slots[1].in_uop.bits.fu_code[4]
connect slots_1.io.in_uop.bits.fu_code[5], issue_slots[1].in_uop.bits.fu_code[5]
connect slots_1.io.in_uop.bits.fu_code[6], issue_slots[1].in_uop.bits.fu_code[6]
connect slots_1.io.in_uop.bits.fu_code[7], issue_slots[1].in_uop.bits.fu_code[7]
connect slots_1.io.in_uop.bits.fu_code[8], issue_slots[1].in_uop.bits.fu_code[8]
connect slots_1.io.in_uop.bits.fu_code[9], issue_slots[1].in_uop.bits.fu_code[9]
connect slots_1.io.in_uop.bits.iq_type[0], issue_slots[1].in_uop.bits.iq_type[0]
connect slots_1.io.in_uop.bits.iq_type[1], issue_slots[1].in_uop.bits.iq_type[1]
connect slots_1.io.in_uop.bits.iq_type[2], issue_slots[1].in_uop.bits.iq_type[2]
connect slots_1.io.in_uop.bits.iq_type[3], issue_slots[1].in_uop.bits.iq_type[3]
connect slots_1.io.in_uop.bits.debug_pc, issue_slots[1].in_uop.bits.debug_pc
connect slots_1.io.in_uop.bits.is_rvc, issue_slots[1].in_uop.bits.is_rvc
connect slots_1.io.in_uop.bits.debug_inst, issue_slots[1].in_uop.bits.debug_inst
connect slots_1.io.in_uop.bits.inst, issue_slots[1].in_uop.bits.inst
connect slots_1.io.in_uop.valid, issue_slots[1].in_uop.valid
connect issue_slots[1].iss_uop.debug_tsrc, slots_1.io.iss_uop.debug_tsrc
connect issue_slots[1].iss_uop.debug_fsrc, slots_1.io.iss_uop.debug_fsrc
connect issue_slots[1].iss_uop.bp_xcpt_if, slots_1.io.iss_uop.bp_xcpt_if
connect issue_slots[1].iss_uop.bp_debug_if, slots_1.io.iss_uop.bp_debug_if
connect issue_slots[1].iss_uop.xcpt_ma_if, slots_1.io.iss_uop.xcpt_ma_if
connect issue_slots[1].iss_uop.xcpt_ae_if, slots_1.io.iss_uop.xcpt_ae_if
connect issue_slots[1].iss_uop.xcpt_pf_if, slots_1.io.iss_uop.xcpt_pf_if
connect issue_slots[1].iss_uop.fp_typ, slots_1.io.iss_uop.fp_typ
connect issue_slots[1].iss_uop.fp_rm, slots_1.io.iss_uop.fp_rm
connect issue_slots[1].iss_uop.fp_val, slots_1.io.iss_uop.fp_val
connect issue_slots[1].iss_uop.fcn_op, slots_1.io.iss_uop.fcn_op
connect issue_slots[1].iss_uop.fcn_dw, slots_1.io.iss_uop.fcn_dw
connect issue_slots[1].iss_uop.frs3_en, slots_1.io.iss_uop.frs3_en
connect issue_slots[1].iss_uop.lrs2_rtype, slots_1.io.iss_uop.lrs2_rtype
connect issue_slots[1].iss_uop.lrs1_rtype, slots_1.io.iss_uop.lrs1_rtype
connect issue_slots[1].iss_uop.dst_rtype, slots_1.io.iss_uop.dst_rtype
connect issue_slots[1].iss_uop.lrs3, slots_1.io.iss_uop.lrs3
connect issue_slots[1].iss_uop.lrs2, slots_1.io.iss_uop.lrs2
connect issue_slots[1].iss_uop.lrs1, slots_1.io.iss_uop.lrs1
connect issue_slots[1].iss_uop.ldst, slots_1.io.iss_uop.ldst
connect issue_slots[1].iss_uop.ldst_is_rs1, slots_1.io.iss_uop.ldst_is_rs1
connect issue_slots[1].iss_uop.csr_cmd, slots_1.io.iss_uop.csr_cmd
connect issue_slots[1].iss_uop.flush_on_commit, slots_1.io.iss_uop.flush_on_commit
connect issue_slots[1].iss_uop.is_unique, slots_1.io.iss_uop.is_unique
connect issue_slots[1].iss_uop.uses_stq, slots_1.io.iss_uop.uses_stq
connect issue_slots[1].iss_uop.uses_ldq, slots_1.io.iss_uop.uses_ldq
connect issue_slots[1].iss_uop.mem_signed, slots_1.io.iss_uop.mem_signed
connect issue_slots[1].iss_uop.mem_size, slots_1.io.iss_uop.mem_size
connect issue_slots[1].iss_uop.mem_cmd, slots_1.io.iss_uop.mem_cmd
connect issue_slots[1].iss_uop.exc_cause, slots_1.io.iss_uop.exc_cause
connect issue_slots[1].iss_uop.exception, slots_1.io.iss_uop.exception
connect issue_slots[1].iss_uop.stale_pdst, slots_1.io.iss_uop.stale_pdst
connect issue_slots[1].iss_uop.ppred_busy, slots_1.io.iss_uop.ppred_busy
connect issue_slots[1].iss_uop.prs3_busy, slots_1.io.iss_uop.prs3_busy
connect issue_slots[1].iss_uop.prs2_busy, slots_1.io.iss_uop.prs2_busy
connect issue_slots[1].iss_uop.prs1_busy, slots_1.io.iss_uop.prs1_busy
connect issue_slots[1].iss_uop.ppred, slots_1.io.iss_uop.ppred
connect issue_slots[1].iss_uop.prs3, slots_1.io.iss_uop.prs3
connect issue_slots[1].iss_uop.prs2, slots_1.io.iss_uop.prs2
connect issue_slots[1].iss_uop.prs1, slots_1.io.iss_uop.prs1
connect issue_slots[1].iss_uop.pdst, slots_1.io.iss_uop.pdst
connect issue_slots[1].iss_uop.rxq_idx, slots_1.io.iss_uop.rxq_idx
connect issue_slots[1].iss_uop.stq_idx, slots_1.io.iss_uop.stq_idx
connect issue_slots[1].iss_uop.ldq_idx, slots_1.io.iss_uop.ldq_idx
connect issue_slots[1].iss_uop.rob_idx, slots_1.io.iss_uop.rob_idx
connect issue_slots[1].iss_uop.fp_ctrl.vec, slots_1.io.iss_uop.fp_ctrl.vec
connect issue_slots[1].iss_uop.fp_ctrl.wflags, slots_1.io.iss_uop.fp_ctrl.wflags
connect issue_slots[1].iss_uop.fp_ctrl.sqrt, slots_1.io.iss_uop.fp_ctrl.sqrt
connect issue_slots[1].iss_uop.fp_ctrl.div, slots_1.io.iss_uop.fp_ctrl.div
connect issue_slots[1].iss_uop.fp_ctrl.fma, slots_1.io.iss_uop.fp_ctrl.fma
connect issue_slots[1].iss_uop.fp_ctrl.fastpipe, slots_1.io.iss_uop.fp_ctrl.fastpipe
connect issue_slots[1].iss_uop.fp_ctrl.toint, slots_1.io.iss_uop.fp_ctrl.toint
connect issue_slots[1].iss_uop.fp_ctrl.fromint, slots_1.io.iss_uop.fp_ctrl.fromint
connect issue_slots[1].iss_uop.fp_ctrl.typeTagOut, slots_1.io.iss_uop.fp_ctrl.typeTagOut
connect issue_slots[1].iss_uop.fp_ctrl.typeTagIn, slots_1.io.iss_uop.fp_ctrl.typeTagIn
connect issue_slots[1].iss_uop.fp_ctrl.swap23, slots_1.io.iss_uop.fp_ctrl.swap23
connect issue_slots[1].iss_uop.fp_ctrl.swap12, slots_1.io.iss_uop.fp_ctrl.swap12
connect issue_slots[1].iss_uop.fp_ctrl.ren3, slots_1.io.iss_uop.fp_ctrl.ren3
connect issue_slots[1].iss_uop.fp_ctrl.ren2, slots_1.io.iss_uop.fp_ctrl.ren2
connect issue_slots[1].iss_uop.fp_ctrl.ren1, slots_1.io.iss_uop.fp_ctrl.ren1
connect issue_slots[1].iss_uop.fp_ctrl.wen, slots_1.io.iss_uop.fp_ctrl.wen
connect issue_slots[1].iss_uop.fp_ctrl.ldst, slots_1.io.iss_uop.fp_ctrl.ldst
connect issue_slots[1].iss_uop.op2_sel, slots_1.io.iss_uop.op2_sel
connect issue_slots[1].iss_uop.op1_sel, slots_1.io.iss_uop.op1_sel
connect issue_slots[1].iss_uop.imm_packed, slots_1.io.iss_uop.imm_packed
connect issue_slots[1].iss_uop.pimm, slots_1.io.iss_uop.pimm
connect issue_slots[1].iss_uop.imm_sel, slots_1.io.iss_uop.imm_sel
connect issue_slots[1].iss_uop.imm_rename, slots_1.io.iss_uop.imm_rename
connect issue_slots[1].iss_uop.taken, slots_1.io.iss_uop.taken
connect issue_slots[1].iss_uop.pc_lob, slots_1.io.iss_uop.pc_lob
connect issue_slots[1].iss_uop.edge_inst, slots_1.io.iss_uop.edge_inst
connect issue_slots[1].iss_uop.ftq_idx, slots_1.io.iss_uop.ftq_idx
connect issue_slots[1].iss_uop.is_mov, slots_1.io.iss_uop.is_mov
connect issue_slots[1].iss_uop.is_rocc, slots_1.io.iss_uop.is_rocc
connect issue_slots[1].iss_uop.is_sys_pc2epc, slots_1.io.iss_uop.is_sys_pc2epc
connect issue_slots[1].iss_uop.is_eret, slots_1.io.iss_uop.is_eret
connect issue_slots[1].iss_uop.is_amo, slots_1.io.iss_uop.is_amo
connect issue_slots[1].iss_uop.is_sfence, slots_1.io.iss_uop.is_sfence
connect issue_slots[1].iss_uop.is_fencei, slots_1.io.iss_uop.is_fencei
connect issue_slots[1].iss_uop.is_fence, slots_1.io.iss_uop.is_fence
connect issue_slots[1].iss_uop.is_sfb, slots_1.io.iss_uop.is_sfb
connect issue_slots[1].iss_uop.br_type, slots_1.io.iss_uop.br_type
connect issue_slots[1].iss_uop.br_tag, slots_1.io.iss_uop.br_tag
connect issue_slots[1].iss_uop.br_mask, slots_1.io.iss_uop.br_mask
connect issue_slots[1].iss_uop.dis_col_sel, slots_1.io.iss_uop.dis_col_sel
connect issue_slots[1].iss_uop.iw_p3_bypass_hint, slots_1.io.iss_uop.iw_p3_bypass_hint
connect issue_slots[1].iss_uop.iw_p2_bypass_hint, slots_1.io.iss_uop.iw_p2_bypass_hint
connect issue_slots[1].iss_uop.iw_p1_bypass_hint, slots_1.io.iss_uop.iw_p1_bypass_hint
connect issue_slots[1].iss_uop.iw_p2_speculative_child, slots_1.io.iss_uop.iw_p2_speculative_child
connect issue_slots[1].iss_uop.iw_p1_speculative_child, slots_1.io.iss_uop.iw_p1_speculative_child
connect issue_slots[1].iss_uop.iw_issued_partial_dgen, slots_1.io.iss_uop.iw_issued_partial_dgen
connect issue_slots[1].iss_uop.iw_issued_partial_agen, slots_1.io.iss_uop.iw_issued_partial_agen
connect issue_slots[1].iss_uop.iw_issued, slots_1.io.iss_uop.iw_issued
connect issue_slots[1].iss_uop.fu_code[0], slots_1.io.iss_uop.fu_code[0]
connect issue_slots[1].iss_uop.fu_code[1], slots_1.io.iss_uop.fu_code[1]
connect issue_slots[1].iss_uop.fu_code[2], slots_1.io.iss_uop.fu_code[2]
connect issue_slots[1].iss_uop.fu_code[3], slots_1.io.iss_uop.fu_code[3]
connect issue_slots[1].iss_uop.fu_code[4], slots_1.io.iss_uop.fu_code[4]
connect issue_slots[1].iss_uop.fu_code[5], slots_1.io.iss_uop.fu_code[5]
connect issue_slots[1].iss_uop.fu_code[6], slots_1.io.iss_uop.fu_code[6]
connect issue_slots[1].iss_uop.fu_code[7], slots_1.io.iss_uop.fu_code[7]
connect issue_slots[1].iss_uop.fu_code[8], slots_1.io.iss_uop.fu_code[8]
connect issue_slots[1].iss_uop.fu_code[9], slots_1.io.iss_uop.fu_code[9]
connect issue_slots[1].iss_uop.iq_type[0], slots_1.io.iss_uop.iq_type[0]
connect issue_slots[1].iss_uop.iq_type[1], slots_1.io.iss_uop.iq_type[1]
connect issue_slots[1].iss_uop.iq_type[2], slots_1.io.iss_uop.iq_type[2]
connect issue_slots[1].iss_uop.iq_type[3], slots_1.io.iss_uop.iq_type[3]
connect issue_slots[1].iss_uop.debug_pc, slots_1.io.iss_uop.debug_pc
connect issue_slots[1].iss_uop.is_rvc, slots_1.io.iss_uop.is_rvc
connect issue_slots[1].iss_uop.debug_inst, slots_1.io.iss_uop.debug_inst
connect issue_slots[1].iss_uop.inst, slots_1.io.iss_uop.inst
connect slots_1.io.grant, issue_slots[1].grant
connect issue_slots[1].request, slots_1.io.request
connect issue_slots[1].will_be_valid, slots_1.io.will_be_valid
connect issue_slots[1].valid, slots_1.io.valid
connect slots_2.io.child_rebusys, issue_slots[2].child_rebusys
connect slots_2.io.pred_wakeup_port.bits, issue_slots[2].pred_wakeup_port.bits
connect slots_2.io.pred_wakeup_port.valid, issue_slots[2].pred_wakeup_port.valid
connect slots_2.io.wakeup_ports[0].bits.rebusy, issue_slots[2].wakeup_ports[0].bits.rebusy
connect slots_2.io.wakeup_ports[0].bits.speculative_mask, issue_slots[2].wakeup_ports[0].bits.speculative_mask
connect slots_2.io.wakeup_ports[0].bits.bypassable, issue_slots[2].wakeup_ports[0].bits.bypassable
connect slots_2.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[2].wakeup_ports[0].bits.uop.debug_tsrc
connect slots_2.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[2].wakeup_ports[0].bits.uop.debug_fsrc
connect slots_2.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[2].wakeup_ports[0].bits.uop.bp_xcpt_if
connect slots_2.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[2].wakeup_ports[0].bits.uop.bp_debug_if
connect slots_2.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[2].wakeup_ports[0].bits.uop.xcpt_ma_if
connect slots_2.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[2].wakeup_ports[0].bits.uop.xcpt_ae_if
connect slots_2.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[2].wakeup_ports[0].bits.uop.xcpt_pf_if
connect slots_2.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[2].wakeup_ports[0].bits.uop.fp_typ
connect slots_2.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[2].wakeup_ports[0].bits.uop.fp_rm
connect slots_2.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[2].wakeup_ports[0].bits.uop.fp_val
connect slots_2.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[2].wakeup_ports[0].bits.uop.fcn_op
connect slots_2.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[2].wakeup_ports[0].bits.uop.fcn_dw
connect slots_2.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[2].wakeup_ports[0].bits.uop.frs3_en
connect slots_2.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[2].wakeup_ports[0].bits.uop.lrs2_rtype
connect slots_2.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[2].wakeup_ports[0].bits.uop.lrs1_rtype
connect slots_2.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[2].wakeup_ports[0].bits.uop.dst_rtype
connect slots_2.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[2].wakeup_ports[0].bits.uop.lrs3
connect slots_2.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[2].wakeup_ports[0].bits.uop.lrs2
connect slots_2.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[2].wakeup_ports[0].bits.uop.lrs1
connect slots_2.io.wakeup_ports[0].bits.uop.ldst, issue_slots[2].wakeup_ports[0].bits.uop.ldst
connect slots_2.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[2].wakeup_ports[0].bits.uop.ldst_is_rs1
connect slots_2.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[2].wakeup_ports[0].bits.uop.csr_cmd
connect slots_2.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[2].wakeup_ports[0].bits.uop.flush_on_commit
connect slots_2.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[2].wakeup_ports[0].bits.uop.is_unique
connect slots_2.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[2].wakeup_ports[0].bits.uop.uses_stq
connect slots_2.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[2].wakeup_ports[0].bits.uop.uses_ldq
connect slots_2.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[2].wakeup_ports[0].bits.uop.mem_signed
connect slots_2.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[2].wakeup_ports[0].bits.uop.mem_size
connect slots_2.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[2].wakeup_ports[0].bits.uop.mem_cmd
connect slots_2.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[2].wakeup_ports[0].bits.uop.exc_cause
connect slots_2.io.wakeup_ports[0].bits.uop.exception, issue_slots[2].wakeup_ports[0].bits.uop.exception
connect slots_2.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[2].wakeup_ports[0].bits.uop.stale_pdst
connect slots_2.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[2].wakeup_ports[0].bits.uop.ppred_busy
connect slots_2.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[2].wakeup_ports[0].bits.uop.prs3_busy
connect slots_2.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[2].wakeup_ports[0].bits.uop.prs2_busy
connect slots_2.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[2].wakeup_ports[0].bits.uop.prs1_busy
connect slots_2.io.wakeup_ports[0].bits.uop.ppred, issue_slots[2].wakeup_ports[0].bits.uop.ppred
connect slots_2.io.wakeup_ports[0].bits.uop.prs3, issue_slots[2].wakeup_ports[0].bits.uop.prs3
connect slots_2.io.wakeup_ports[0].bits.uop.prs2, issue_slots[2].wakeup_ports[0].bits.uop.prs2
connect slots_2.io.wakeup_ports[0].bits.uop.prs1, issue_slots[2].wakeup_ports[0].bits.uop.prs1
connect slots_2.io.wakeup_ports[0].bits.uop.pdst, issue_slots[2].wakeup_ports[0].bits.uop.pdst
connect slots_2.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[2].wakeup_ports[0].bits.uop.rxq_idx
connect slots_2.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[2].wakeup_ports[0].bits.uop.stq_idx
connect slots_2.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[2].wakeup_ports[0].bits.uop.ldq_idx
connect slots_2.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[2].wakeup_ports[0].bits.uop.rob_idx
connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.vec
connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.wflags
connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.sqrt
connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.div
connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.fma
connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe
connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.toint
connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.fromint
connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut
connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn
connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.swap23
connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.swap12
connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.ren3
connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.ren2
connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.ren1
connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.wen
connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.ldst
connect slots_2.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[2].wakeup_ports[0].bits.uop.op2_sel
connect slots_2.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[2].wakeup_ports[0].bits.uop.op1_sel
connect slots_2.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[2].wakeup_ports[0].bits.uop.imm_packed
connect slots_2.io.wakeup_ports[0].bits.uop.pimm, issue_slots[2].wakeup_ports[0].bits.uop.pimm
connect slots_2.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[2].wakeup_ports[0].bits.uop.imm_sel
connect slots_2.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[2].wakeup_ports[0].bits.uop.imm_rename
connect slots_2.io.wakeup_ports[0].bits.uop.taken, issue_slots[2].wakeup_ports[0].bits.uop.taken
connect slots_2.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[2].wakeup_ports[0].bits.uop.pc_lob
connect slots_2.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[2].wakeup_ports[0].bits.uop.edge_inst
connect slots_2.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[2].wakeup_ports[0].bits.uop.ftq_idx
connect slots_2.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[2].wakeup_ports[0].bits.uop.is_mov
connect slots_2.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[2].wakeup_ports[0].bits.uop.is_rocc
connect slots_2.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[2].wakeup_ports[0].bits.uop.is_sys_pc2epc
connect slots_2.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[2].wakeup_ports[0].bits.uop.is_eret
connect slots_2.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[2].wakeup_ports[0].bits.uop.is_amo
connect slots_2.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[2].wakeup_ports[0].bits.uop.is_sfence
connect slots_2.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[2].wakeup_ports[0].bits.uop.is_fencei
connect slots_2.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[2].wakeup_ports[0].bits.uop.is_fence
connect slots_2.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[2].wakeup_ports[0].bits.uop.is_sfb
connect slots_2.io.wakeup_ports[0].bits.uop.br_type, issue_slots[2].wakeup_ports[0].bits.uop.br_type
connect slots_2.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[2].wakeup_ports[0].bits.uop.br_tag
connect slots_2.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[2].wakeup_ports[0].bits.uop.br_mask
connect slots_2.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[2].wakeup_ports[0].bits.uop.dis_col_sel
connect slots_2.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[2].wakeup_ports[0].bits.uop.iw_p3_bypass_hint
connect slots_2.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[2].wakeup_ports[0].bits.uop.iw_p2_bypass_hint
connect slots_2.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[2].wakeup_ports[0].bits.uop.iw_p1_bypass_hint
connect slots_2.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[2].wakeup_ports[0].bits.uop.iw_p2_speculative_child
connect slots_2.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[2].wakeup_ports[0].bits.uop.iw_p1_speculative_child
connect slots_2.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[2].wakeup_ports[0].bits.uop.iw_issued_partial_dgen
connect slots_2.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[2].wakeup_ports[0].bits.uop.iw_issued_partial_agen
connect slots_2.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[2].wakeup_ports[0].bits.uop.iw_issued
connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[0]
connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[1]
connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[2]
connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[3]
connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[4]
connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[5]
connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[6]
connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[7]
connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[8]
connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[9]
connect slots_2.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[2].wakeup_ports[0].bits.uop.iq_type[0]
connect slots_2.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[2].wakeup_ports[0].bits.uop.iq_type[1]
connect slots_2.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[2].wakeup_ports[0].bits.uop.iq_type[2]
connect slots_2.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[2].wakeup_ports[0].bits.uop.iq_type[3]
connect slots_2.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[2].wakeup_ports[0].bits.uop.debug_pc
connect slots_2.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[2].wakeup_ports[0].bits.uop.is_rvc
connect slots_2.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[2].wakeup_ports[0].bits.uop.debug_inst
connect slots_2.io.wakeup_ports[0].bits.uop.inst, issue_slots[2].wakeup_ports[0].bits.uop.inst
connect slots_2.io.wakeup_ports[0].valid, issue_slots[2].wakeup_ports[0].valid
connect slots_2.io.wakeup_ports[1].bits.rebusy, issue_slots[2].wakeup_ports[1].bits.rebusy
connect slots_2.io.wakeup_ports[1].bits.speculative_mask, issue_slots[2].wakeup_ports[1].bits.speculative_mask
connect slots_2.io.wakeup_ports[1].bits.bypassable, issue_slots[2].wakeup_ports[1].bits.bypassable
connect slots_2.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[2].wakeup_ports[1].bits.uop.debug_tsrc
connect slots_2.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[2].wakeup_ports[1].bits.uop.debug_fsrc
connect slots_2.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[2].wakeup_ports[1].bits.uop.bp_xcpt_if
connect slots_2.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[2].wakeup_ports[1].bits.uop.bp_debug_if
connect slots_2.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[2].wakeup_ports[1].bits.uop.xcpt_ma_if
connect slots_2.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[2].wakeup_ports[1].bits.uop.xcpt_ae_if
connect slots_2.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[2].wakeup_ports[1].bits.uop.xcpt_pf_if
connect slots_2.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[2].wakeup_ports[1].bits.uop.fp_typ
connect slots_2.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[2].wakeup_ports[1].bits.uop.fp_rm
connect slots_2.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[2].wakeup_ports[1].bits.uop.fp_val
connect slots_2.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[2].wakeup_ports[1].bits.uop.fcn_op
connect slots_2.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[2].wakeup_ports[1].bits.uop.fcn_dw
connect slots_2.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[2].wakeup_ports[1].bits.uop.frs3_en
connect slots_2.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[2].wakeup_ports[1].bits.uop.lrs2_rtype
connect slots_2.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[2].wakeup_ports[1].bits.uop.lrs1_rtype
connect slots_2.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[2].wakeup_ports[1].bits.uop.dst_rtype
connect slots_2.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[2].wakeup_ports[1].bits.uop.lrs3
connect slots_2.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[2].wakeup_ports[1].bits.uop.lrs2
connect slots_2.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[2].wakeup_ports[1].bits.uop.lrs1
connect slots_2.io.wakeup_ports[1].bits.uop.ldst, issue_slots[2].wakeup_ports[1].bits.uop.ldst
connect slots_2.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[2].wakeup_ports[1].bits.uop.ldst_is_rs1
connect slots_2.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[2].wakeup_ports[1].bits.uop.csr_cmd
connect slots_2.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[2].wakeup_ports[1].bits.uop.flush_on_commit
connect slots_2.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[2].wakeup_ports[1].bits.uop.is_unique
connect slots_2.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[2].wakeup_ports[1].bits.uop.uses_stq
connect slots_2.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[2].wakeup_ports[1].bits.uop.uses_ldq
connect slots_2.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[2].wakeup_ports[1].bits.uop.mem_signed
connect slots_2.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[2].wakeup_ports[1].bits.uop.mem_size
connect slots_2.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[2].wakeup_ports[1].bits.uop.mem_cmd
connect slots_2.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[2].wakeup_ports[1].bits.uop.exc_cause
connect slots_2.io.wakeup_ports[1].bits.uop.exception, issue_slots[2].wakeup_ports[1].bits.uop.exception
connect slots_2.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[2].wakeup_ports[1].bits.uop.stale_pdst
connect slots_2.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[2].wakeup_ports[1].bits.uop.ppred_busy
connect slots_2.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[2].wakeup_ports[1].bits.uop.prs3_busy
connect slots_2.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[2].wakeup_ports[1].bits.uop.prs2_busy
connect slots_2.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[2].wakeup_ports[1].bits.uop.prs1_busy
connect slots_2.io.wakeup_ports[1].bits.uop.ppred, issue_slots[2].wakeup_ports[1].bits.uop.ppred
connect slots_2.io.wakeup_ports[1].bits.uop.prs3, issue_slots[2].wakeup_ports[1].bits.uop.prs3
connect slots_2.io.wakeup_ports[1].bits.uop.prs2, issue_slots[2].wakeup_ports[1].bits.uop.prs2
connect slots_2.io.wakeup_ports[1].bits.uop.prs1, issue_slots[2].wakeup_ports[1].bits.uop.prs1
connect slots_2.io.wakeup_ports[1].bits.uop.pdst, issue_slots[2].wakeup_ports[1].bits.uop.pdst
connect slots_2.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[2].wakeup_ports[1].bits.uop.rxq_idx
connect slots_2.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[2].wakeup_ports[1].bits.uop.stq_idx
connect slots_2.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[2].wakeup_ports[1].bits.uop.ldq_idx
connect slots_2.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[2].wakeup_ports[1].bits.uop.rob_idx
connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.vec
connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.wflags
connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.sqrt
connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.div
connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.fma
connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe
connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.toint
connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.fromint
connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut
connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn
connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.swap23
connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.swap12
connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.ren3
connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.ren2
connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.ren1
connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.wen
connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.ldst
connect slots_2.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[2].wakeup_ports[1].bits.uop.op2_sel
connect slots_2.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[2].wakeup_ports[1].bits.uop.op1_sel
connect slots_2.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[2].wakeup_ports[1].bits.uop.imm_packed
connect slots_2.io.wakeup_ports[1].bits.uop.pimm, issue_slots[2].wakeup_ports[1].bits.uop.pimm
connect slots_2.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[2].wakeup_ports[1].bits.uop.imm_sel
connect slots_2.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[2].wakeup_ports[1].bits.uop.imm_rename
connect slots_2.io.wakeup_ports[1].bits.uop.taken, issue_slots[2].wakeup_ports[1].bits.uop.taken
connect slots_2.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[2].wakeup_ports[1].bits.uop.pc_lob
connect slots_2.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[2].wakeup_ports[1].bits.uop.edge_inst
connect slots_2.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[2].wakeup_ports[1].bits.uop.ftq_idx
connect slots_2.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[2].wakeup_ports[1].bits.uop.is_mov
connect slots_2.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[2].wakeup_ports[1].bits.uop.is_rocc
connect slots_2.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[2].wakeup_ports[1].bits.uop.is_sys_pc2epc
connect slots_2.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[2].wakeup_ports[1].bits.uop.is_eret
connect slots_2.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[2].wakeup_ports[1].bits.uop.is_amo
connect slots_2.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[2].wakeup_ports[1].bits.uop.is_sfence
connect slots_2.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[2].wakeup_ports[1].bits.uop.is_fencei
connect slots_2.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[2].wakeup_ports[1].bits.uop.is_fence
connect slots_2.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[2].wakeup_ports[1].bits.uop.is_sfb
connect slots_2.io.wakeup_ports[1].bits.uop.br_type, issue_slots[2].wakeup_ports[1].bits.uop.br_type
connect slots_2.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[2].wakeup_ports[1].bits.uop.br_tag
connect slots_2.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[2].wakeup_ports[1].bits.uop.br_mask
connect slots_2.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[2].wakeup_ports[1].bits.uop.dis_col_sel
connect slots_2.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[2].wakeup_ports[1].bits.uop.iw_p3_bypass_hint
connect slots_2.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[2].wakeup_ports[1].bits.uop.iw_p2_bypass_hint
connect slots_2.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[2].wakeup_ports[1].bits.uop.iw_p1_bypass_hint
connect slots_2.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[2].wakeup_ports[1].bits.uop.iw_p2_speculative_child
connect slots_2.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[2].wakeup_ports[1].bits.uop.iw_p1_speculative_child
connect slots_2.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[2].wakeup_ports[1].bits.uop.iw_issued_partial_dgen
connect slots_2.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[2].wakeup_ports[1].bits.uop.iw_issued_partial_agen
connect slots_2.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[2].wakeup_ports[1].bits.uop.iw_issued
connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[0]
connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[1]
connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[2]
connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[3]
connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[4]
connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[5]
connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[6]
connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[7]
connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[8]
connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[9]
connect slots_2.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[2].wakeup_ports[1].bits.uop.iq_type[0]
connect slots_2.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[2].wakeup_ports[1].bits.uop.iq_type[1]
connect slots_2.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[2].wakeup_ports[1].bits.uop.iq_type[2]
connect slots_2.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[2].wakeup_ports[1].bits.uop.iq_type[3]
connect slots_2.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[2].wakeup_ports[1].bits.uop.debug_pc
connect slots_2.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[2].wakeup_ports[1].bits.uop.is_rvc
connect slots_2.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[2].wakeup_ports[1].bits.uop.debug_inst
connect slots_2.io.wakeup_ports[1].bits.uop.inst, issue_slots[2].wakeup_ports[1].bits.uop.inst
connect slots_2.io.wakeup_ports[1].valid, issue_slots[2].wakeup_ports[1].valid
connect slots_2.io.wakeup_ports[2].bits.rebusy, issue_slots[2].wakeup_ports[2].bits.rebusy
connect slots_2.io.wakeup_ports[2].bits.speculative_mask, issue_slots[2].wakeup_ports[2].bits.speculative_mask
connect slots_2.io.wakeup_ports[2].bits.bypassable, issue_slots[2].wakeup_ports[2].bits.bypassable
connect slots_2.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[2].wakeup_ports[2].bits.uop.debug_tsrc
connect slots_2.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[2].wakeup_ports[2].bits.uop.debug_fsrc
connect slots_2.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[2].wakeup_ports[2].bits.uop.bp_xcpt_if
connect slots_2.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[2].wakeup_ports[2].bits.uop.bp_debug_if
connect slots_2.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[2].wakeup_ports[2].bits.uop.xcpt_ma_if
connect slots_2.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[2].wakeup_ports[2].bits.uop.xcpt_ae_if
connect slots_2.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[2].wakeup_ports[2].bits.uop.xcpt_pf_if
connect slots_2.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[2].wakeup_ports[2].bits.uop.fp_typ
connect slots_2.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[2].wakeup_ports[2].bits.uop.fp_rm
connect slots_2.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[2].wakeup_ports[2].bits.uop.fp_val
connect slots_2.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[2].wakeup_ports[2].bits.uop.fcn_op
connect slots_2.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[2].wakeup_ports[2].bits.uop.fcn_dw
connect slots_2.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[2].wakeup_ports[2].bits.uop.frs3_en
connect slots_2.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[2].wakeup_ports[2].bits.uop.lrs2_rtype
connect slots_2.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[2].wakeup_ports[2].bits.uop.lrs1_rtype
connect slots_2.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[2].wakeup_ports[2].bits.uop.dst_rtype
connect slots_2.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[2].wakeup_ports[2].bits.uop.lrs3
connect slots_2.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[2].wakeup_ports[2].bits.uop.lrs2
connect slots_2.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[2].wakeup_ports[2].bits.uop.lrs1
connect slots_2.io.wakeup_ports[2].bits.uop.ldst, issue_slots[2].wakeup_ports[2].bits.uop.ldst
connect slots_2.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[2].wakeup_ports[2].bits.uop.ldst_is_rs1
connect slots_2.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[2].wakeup_ports[2].bits.uop.csr_cmd
connect slots_2.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[2].wakeup_ports[2].bits.uop.flush_on_commit
connect slots_2.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[2].wakeup_ports[2].bits.uop.is_unique
connect slots_2.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[2].wakeup_ports[2].bits.uop.uses_stq
connect slots_2.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[2].wakeup_ports[2].bits.uop.uses_ldq
connect slots_2.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[2].wakeup_ports[2].bits.uop.mem_signed
connect slots_2.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[2].wakeup_ports[2].bits.uop.mem_size
connect slots_2.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[2].wakeup_ports[2].bits.uop.mem_cmd
connect slots_2.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[2].wakeup_ports[2].bits.uop.exc_cause
connect slots_2.io.wakeup_ports[2].bits.uop.exception, issue_slots[2].wakeup_ports[2].bits.uop.exception
connect slots_2.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[2].wakeup_ports[2].bits.uop.stale_pdst
connect slots_2.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[2].wakeup_ports[2].bits.uop.ppred_busy
connect slots_2.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[2].wakeup_ports[2].bits.uop.prs3_busy
connect slots_2.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[2].wakeup_ports[2].bits.uop.prs2_busy
connect slots_2.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[2].wakeup_ports[2].bits.uop.prs1_busy
connect slots_2.io.wakeup_ports[2].bits.uop.ppred, issue_slots[2].wakeup_ports[2].bits.uop.ppred
connect slots_2.io.wakeup_ports[2].bits.uop.prs3, issue_slots[2].wakeup_ports[2].bits.uop.prs3
connect slots_2.io.wakeup_ports[2].bits.uop.prs2, issue_slots[2].wakeup_ports[2].bits.uop.prs2
connect slots_2.io.wakeup_ports[2].bits.uop.prs1, issue_slots[2].wakeup_ports[2].bits.uop.prs1
connect slots_2.io.wakeup_ports[2].bits.uop.pdst, issue_slots[2].wakeup_ports[2].bits.uop.pdst
connect slots_2.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[2].wakeup_ports[2].bits.uop.rxq_idx
connect slots_2.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[2].wakeup_ports[2].bits.uop.stq_idx
connect slots_2.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[2].wakeup_ports[2].bits.uop.ldq_idx
connect slots_2.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[2].wakeup_ports[2].bits.uop.rob_idx
connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.vec
connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.wflags
connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.sqrt
connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.div
connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.fma
connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe
connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.toint
connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.fromint
connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut
connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn
connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.swap23
connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.swap12
connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.ren3
connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.ren2
connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.ren1
connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.wen
connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.ldst
connect slots_2.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[2].wakeup_ports[2].bits.uop.op2_sel
connect slots_2.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[2].wakeup_ports[2].bits.uop.op1_sel
connect slots_2.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[2].wakeup_ports[2].bits.uop.imm_packed
connect slots_2.io.wakeup_ports[2].bits.uop.pimm, issue_slots[2].wakeup_ports[2].bits.uop.pimm
connect slots_2.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[2].wakeup_ports[2].bits.uop.imm_sel
connect slots_2.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[2].wakeup_ports[2].bits.uop.imm_rename
connect slots_2.io.wakeup_ports[2].bits.uop.taken, issue_slots[2].wakeup_ports[2].bits.uop.taken
connect slots_2.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[2].wakeup_ports[2].bits.uop.pc_lob
connect slots_2.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[2].wakeup_ports[2].bits.uop.edge_inst
connect slots_2.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[2].wakeup_ports[2].bits.uop.ftq_idx
connect slots_2.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[2].wakeup_ports[2].bits.uop.is_mov
connect slots_2.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[2].wakeup_ports[2].bits.uop.is_rocc
connect slots_2.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[2].wakeup_ports[2].bits.uop.is_sys_pc2epc
connect slots_2.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[2].wakeup_ports[2].bits.uop.is_eret
connect slots_2.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[2].wakeup_ports[2].bits.uop.is_amo
connect slots_2.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[2].wakeup_ports[2].bits.uop.is_sfence
connect slots_2.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[2].wakeup_ports[2].bits.uop.is_fencei
connect slots_2.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[2].wakeup_ports[2].bits.uop.is_fence
connect slots_2.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[2].wakeup_ports[2].bits.uop.is_sfb
connect slots_2.io.wakeup_ports[2].bits.uop.br_type, issue_slots[2].wakeup_ports[2].bits.uop.br_type
connect slots_2.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[2].wakeup_ports[2].bits.uop.br_tag
connect slots_2.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[2].wakeup_ports[2].bits.uop.br_mask
connect slots_2.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[2].wakeup_ports[2].bits.uop.dis_col_sel
connect slots_2.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[2].wakeup_ports[2].bits.uop.iw_p3_bypass_hint
connect slots_2.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[2].wakeup_ports[2].bits.uop.iw_p2_bypass_hint
connect slots_2.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[2].wakeup_ports[2].bits.uop.iw_p1_bypass_hint
connect slots_2.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[2].wakeup_ports[2].bits.uop.iw_p2_speculative_child
connect slots_2.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[2].wakeup_ports[2].bits.uop.iw_p1_speculative_child
connect slots_2.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[2].wakeup_ports[2].bits.uop.iw_issued_partial_dgen
connect slots_2.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[2].wakeup_ports[2].bits.uop.iw_issued_partial_agen
connect slots_2.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[2].wakeup_ports[2].bits.uop.iw_issued
connect slots_2.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[2].wakeup_ports[2].bits.uop.fu_code[0]
connect slots_2.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[2].wakeup_ports[2].bits.uop.fu_code[1]
connect slots_2.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[2].wakeup_ports[2].bits.uop.fu_code[2]
connect slots_2.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[2].wakeup_ports[2].bits.uop.fu_code[3]
connect slots_2.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[2].wakeup_ports[2].bits.uop.fu_code[4]
connect slots_2.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[2].wakeup_ports[2].bits.uop.fu_code[5]
connect slots_2.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[2].wakeup_ports[2].bits.uop.fu_code[6]
connect slots_2.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[2].wakeup_ports[2].bits.uop.fu_code[7]
connect slots_2.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[2].wakeup_ports[2].bits.uop.fu_code[8]
connect slots_2.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[2].wakeup_ports[2].bits.uop.fu_code[9]
connect slots_2.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[2].wakeup_ports[2].bits.uop.iq_type[0]
connect slots_2.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[2].wakeup_ports[2].bits.uop.iq_type[1]
connect slots_2.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[2].wakeup_ports[2].bits.uop.iq_type[2]
connect slots_2.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[2].wakeup_ports[2].bits.uop.iq_type[3]
connect slots_2.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[2].wakeup_ports[2].bits.uop.debug_pc
connect slots_2.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[2].wakeup_ports[2].bits.uop.is_rvc
connect slots_2.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[2].wakeup_ports[2].bits.uop.debug_inst
connect slots_2.io.wakeup_ports[2].bits.uop.inst, issue_slots[2].wakeup_ports[2].bits.uop.inst
connect slots_2.io.wakeup_ports[2].valid, issue_slots[2].wakeup_ports[2].valid
connect slots_2.io.wakeup_ports[3].bits.rebusy, issue_slots[2].wakeup_ports[3].bits.rebusy
connect slots_2.io.wakeup_ports[3].bits.speculative_mask, issue_slots[2].wakeup_ports[3].bits.speculative_mask
connect slots_2.io.wakeup_ports[3].bits.bypassable, issue_slots[2].wakeup_ports[3].bits.bypassable
connect slots_2.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[2].wakeup_ports[3].bits.uop.debug_tsrc
connect slots_2.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[2].wakeup_ports[3].bits.uop.debug_fsrc
connect slots_2.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[2].wakeup_ports[3].bits.uop.bp_xcpt_if
connect slots_2.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[2].wakeup_ports[3].bits.uop.bp_debug_if
connect slots_2.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[2].wakeup_ports[3].bits.uop.xcpt_ma_if
connect slots_2.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[2].wakeup_ports[3].bits.uop.xcpt_ae_if
connect slots_2.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[2].wakeup_ports[3].bits.uop.xcpt_pf_if
connect slots_2.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[2].wakeup_ports[3].bits.uop.fp_typ
connect slots_2.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[2].wakeup_ports[3].bits.uop.fp_rm
connect slots_2.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[2].wakeup_ports[3].bits.uop.fp_val
connect slots_2.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[2].wakeup_ports[3].bits.uop.fcn_op
connect slots_2.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[2].wakeup_ports[3].bits.uop.fcn_dw
connect slots_2.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[2].wakeup_ports[3].bits.uop.frs3_en
connect slots_2.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[2].wakeup_ports[3].bits.uop.lrs2_rtype
connect slots_2.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[2].wakeup_ports[3].bits.uop.lrs1_rtype
connect slots_2.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[2].wakeup_ports[3].bits.uop.dst_rtype
connect slots_2.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[2].wakeup_ports[3].bits.uop.lrs3
connect slots_2.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[2].wakeup_ports[3].bits.uop.lrs2
connect slots_2.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[2].wakeup_ports[3].bits.uop.lrs1
connect slots_2.io.wakeup_ports[3].bits.uop.ldst, issue_slots[2].wakeup_ports[3].bits.uop.ldst
connect slots_2.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[2].wakeup_ports[3].bits.uop.ldst_is_rs1
connect slots_2.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[2].wakeup_ports[3].bits.uop.csr_cmd
connect slots_2.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[2].wakeup_ports[3].bits.uop.flush_on_commit
connect slots_2.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[2].wakeup_ports[3].bits.uop.is_unique
connect slots_2.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[2].wakeup_ports[3].bits.uop.uses_stq
connect slots_2.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[2].wakeup_ports[3].bits.uop.uses_ldq
connect slots_2.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[2].wakeup_ports[3].bits.uop.mem_signed
connect slots_2.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[2].wakeup_ports[3].bits.uop.mem_size
connect slots_2.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[2].wakeup_ports[3].bits.uop.mem_cmd
connect slots_2.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[2].wakeup_ports[3].bits.uop.exc_cause
connect slots_2.io.wakeup_ports[3].bits.uop.exception, issue_slots[2].wakeup_ports[3].bits.uop.exception
connect slots_2.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[2].wakeup_ports[3].bits.uop.stale_pdst
connect slots_2.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[2].wakeup_ports[3].bits.uop.ppred_busy
connect slots_2.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[2].wakeup_ports[3].bits.uop.prs3_busy
connect slots_2.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[2].wakeup_ports[3].bits.uop.prs2_busy
connect slots_2.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[2].wakeup_ports[3].bits.uop.prs1_busy
connect slots_2.io.wakeup_ports[3].bits.uop.ppred, issue_slots[2].wakeup_ports[3].bits.uop.ppred
connect slots_2.io.wakeup_ports[3].bits.uop.prs3, issue_slots[2].wakeup_ports[3].bits.uop.prs3
connect slots_2.io.wakeup_ports[3].bits.uop.prs2, issue_slots[2].wakeup_ports[3].bits.uop.prs2
connect slots_2.io.wakeup_ports[3].bits.uop.prs1, issue_slots[2].wakeup_ports[3].bits.uop.prs1
connect slots_2.io.wakeup_ports[3].bits.uop.pdst, issue_slots[2].wakeup_ports[3].bits.uop.pdst
connect slots_2.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[2].wakeup_ports[3].bits.uop.rxq_idx
connect slots_2.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[2].wakeup_ports[3].bits.uop.stq_idx
connect slots_2.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[2].wakeup_ports[3].bits.uop.ldq_idx
connect slots_2.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[2].wakeup_ports[3].bits.uop.rob_idx
connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.vec
connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.wflags
connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.sqrt
connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.div
connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.fma
connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe
connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.toint
connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.fromint
connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut
connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn
connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.swap23
connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.swap12
connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.ren3
connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.ren2
connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.ren1
connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.wen
connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.ldst
connect slots_2.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[2].wakeup_ports[3].bits.uop.op2_sel
connect slots_2.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[2].wakeup_ports[3].bits.uop.op1_sel
connect slots_2.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[2].wakeup_ports[3].bits.uop.imm_packed
connect slots_2.io.wakeup_ports[3].bits.uop.pimm, issue_slots[2].wakeup_ports[3].bits.uop.pimm
connect slots_2.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[2].wakeup_ports[3].bits.uop.imm_sel
connect slots_2.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[2].wakeup_ports[3].bits.uop.imm_rename
connect slots_2.io.wakeup_ports[3].bits.uop.taken, issue_slots[2].wakeup_ports[3].bits.uop.taken
connect slots_2.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[2].wakeup_ports[3].bits.uop.pc_lob
connect slots_2.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[2].wakeup_ports[3].bits.uop.edge_inst
connect slots_2.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[2].wakeup_ports[3].bits.uop.ftq_idx
connect slots_2.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[2].wakeup_ports[3].bits.uop.is_mov
connect slots_2.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[2].wakeup_ports[3].bits.uop.is_rocc
connect slots_2.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[2].wakeup_ports[3].bits.uop.is_sys_pc2epc
connect slots_2.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[2].wakeup_ports[3].bits.uop.is_eret
connect slots_2.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[2].wakeup_ports[3].bits.uop.is_amo
connect slots_2.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[2].wakeup_ports[3].bits.uop.is_sfence
connect slots_2.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[2].wakeup_ports[3].bits.uop.is_fencei
connect slots_2.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[2].wakeup_ports[3].bits.uop.is_fence
connect slots_2.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[2].wakeup_ports[3].bits.uop.is_sfb
connect slots_2.io.wakeup_ports[3].bits.uop.br_type, issue_slots[2].wakeup_ports[3].bits.uop.br_type
connect slots_2.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[2].wakeup_ports[3].bits.uop.br_tag
connect slots_2.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[2].wakeup_ports[3].bits.uop.br_mask
connect slots_2.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[2].wakeup_ports[3].bits.uop.dis_col_sel
connect slots_2.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[2].wakeup_ports[3].bits.uop.iw_p3_bypass_hint
connect slots_2.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[2].wakeup_ports[3].bits.uop.iw_p2_bypass_hint
connect slots_2.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[2].wakeup_ports[3].bits.uop.iw_p1_bypass_hint
connect slots_2.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[2].wakeup_ports[3].bits.uop.iw_p2_speculative_child
connect slots_2.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[2].wakeup_ports[3].bits.uop.iw_p1_speculative_child
connect slots_2.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[2].wakeup_ports[3].bits.uop.iw_issued_partial_dgen
connect slots_2.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[2].wakeup_ports[3].bits.uop.iw_issued_partial_agen
connect slots_2.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[2].wakeup_ports[3].bits.uop.iw_issued
connect slots_2.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[2].wakeup_ports[3].bits.uop.fu_code[0]
connect slots_2.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[2].wakeup_ports[3].bits.uop.fu_code[1]
connect slots_2.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[2].wakeup_ports[3].bits.uop.fu_code[2]
connect slots_2.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[2].wakeup_ports[3].bits.uop.fu_code[3]
connect slots_2.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[2].wakeup_ports[3].bits.uop.fu_code[4]
connect slots_2.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[2].wakeup_ports[3].bits.uop.fu_code[5]
connect slots_2.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[2].wakeup_ports[3].bits.uop.fu_code[6]
connect slots_2.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[2].wakeup_ports[3].bits.uop.fu_code[7]
connect slots_2.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[2].wakeup_ports[3].bits.uop.fu_code[8]
connect slots_2.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[2].wakeup_ports[3].bits.uop.fu_code[9]
connect slots_2.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[2].wakeup_ports[3].bits.uop.iq_type[0]
connect slots_2.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[2].wakeup_ports[3].bits.uop.iq_type[1]
connect slots_2.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[2].wakeup_ports[3].bits.uop.iq_type[2]
connect slots_2.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[2].wakeup_ports[3].bits.uop.iq_type[3]
connect slots_2.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[2].wakeup_ports[3].bits.uop.debug_pc
connect slots_2.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[2].wakeup_ports[3].bits.uop.is_rvc
connect slots_2.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[2].wakeup_ports[3].bits.uop.debug_inst
connect slots_2.io.wakeup_ports[3].bits.uop.inst, issue_slots[2].wakeup_ports[3].bits.uop.inst
connect slots_2.io.wakeup_ports[3].valid, issue_slots[2].wakeup_ports[3].valid
connect slots_2.io.squash_grant, issue_slots[2].squash_grant
connect slots_2.io.clear, issue_slots[2].clear
connect slots_2.io.kill, issue_slots[2].kill
connect slots_2.io.brupdate.b2.target_offset, issue_slots[2].brupdate.b2.target_offset
connect slots_2.io.brupdate.b2.jalr_target, issue_slots[2].brupdate.b2.jalr_target
connect slots_2.io.brupdate.b2.pc_sel, issue_slots[2].brupdate.b2.pc_sel
connect slots_2.io.brupdate.b2.cfi_type, issue_slots[2].brupdate.b2.cfi_type
connect slots_2.io.brupdate.b2.taken, issue_slots[2].brupdate.b2.taken
connect slots_2.io.brupdate.b2.mispredict, issue_slots[2].brupdate.b2.mispredict
connect slots_2.io.brupdate.b2.uop.debug_tsrc, issue_slots[2].brupdate.b2.uop.debug_tsrc
connect slots_2.io.brupdate.b2.uop.debug_fsrc, issue_slots[2].brupdate.b2.uop.debug_fsrc
connect slots_2.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[2].brupdate.b2.uop.bp_xcpt_if
connect slots_2.io.brupdate.b2.uop.bp_debug_if, issue_slots[2].brupdate.b2.uop.bp_debug_if
connect slots_2.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[2].brupdate.b2.uop.xcpt_ma_if
connect slots_2.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[2].brupdate.b2.uop.xcpt_ae_if
connect slots_2.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[2].brupdate.b2.uop.xcpt_pf_if
connect slots_2.io.brupdate.b2.uop.fp_typ, issue_slots[2].brupdate.b2.uop.fp_typ
connect slots_2.io.brupdate.b2.uop.fp_rm, issue_slots[2].brupdate.b2.uop.fp_rm
connect slots_2.io.brupdate.b2.uop.fp_val, issue_slots[2].brupdate.b2.uop.fp_val
connect slots_2.io.brupdate.b2.uop.fcn_op, issue_slots[2].brupdate.b2.uop.fcn_op
connect slots_2.io.brupdate.b2.uop.fcn_dw, issue_slots[2].brupdate.b2.uop.fcn_dw
connect slots_2.io.brupdate.b2.uop.frs3_en, issue_slots[2].brupdate.b2.uop.frs3_en
connect slots_2.io.brupdate.b2.uop.lrs2_rtype, issue_slots[2].brupdate.b2.uop.lrs2_rtype
connect slots_2.io.brupdate.b2.uop.lrs1_rtype, issue_slots[2].brupdate.b2.uop.lrs1_rtype
connect slots_2.io.brupdate.b2.uop.dst_rtype, issue_slots[2].brupdate.b2.uop.dst_rtype
connect slots_2.io.brupdate.b2.uop.lrs3, issue_slots[2].brupdate.b2.uop.lrs3
connect slots_2.io.brupdate.b2.uop.lrs2, issue_slots[2].brupdate.b2.uop.lrs2
connect slots_2.io.brupdate.b2.uop.lrs1, issue_slots[2].brupdate.b2.uop.lrs1
connect slots_2.io.brupdate.b2.uop.ldst, issue_slots[2].brupdate.b2.uop.ldst
connect slots_2.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[2].brupdate.b2.uop.ldst_is_rs1
connect slots_2.io.brupdate.b2.uop.csr_cmd, issue_slots[2].brupdate.b2.uop.csr_cmd
connect slots_2.io.brupdate.b2.uop.flush_on_commit, issue_slots[2].brupdate.b2.uop.flush_on_commit
connect slots_2.io.brupdate.b2.uop.is_unique, issue_slots[2].brupdate.b2.uop.is_unique
connect slots_2.io.brupdate.b2.uop.uses_stq, issue_slots[2].brupdate.b2.uop.uses_stq
connect slots_2.io.brupdate.b2.uop.uses_ldq, issue_slots[2].brupdate.b2.uop.uses_ldq
connect slots_2.io.brupdate.b2.uop.mem_signed, issue_slots[2].brupdate.b2.uop.mem_signed
connect slots_2.io.brupdate.b2.uop.mem_size, issue_slots[2].brupdate.b2.uop.mem_size
connect slots_2.io.brupdate.b2.uop.mem_cmd, issue_slots[2].brupdate.b2.uop.mem_cmd
connect slots_2.io.brupdate.b2.uop.exc_cause, issue_slots[2].brupdate.b2.uop.exc_cause
connect slots_2.io.brupdate.b2.uop.exception, issue_slots[2].brupdate.b2.uop.exception
connect slots_2.io.brupdate.b2.uop.stale_pdst, issue_slots[2].brupdate.b2.uop.stale_pdst
connect slots_2.io.brupdate.b2.uop.ppred_busy, issue_slots[2].brupdate.b2.uop.ppred_busy
connect slots_2.io.brupdate.b2.uop.prs3_busy, issue_slots[2].brupdate.b2.uop.prs3_busy
connect slots_2.io.brupdate.b2.uop.prs2_busy, issue_slots[2].brupdate.b2.uop.prs2_busy
connect slots_2.io.brupdate.b2.uop.prs1_busy, issue_slots[2].brupdate.b2.uop.prs1_busy
connect slots_2.io.brupdate.b2.uop.ppred, issue_slots[2].brupdate.b2.uop.ppred
connect slots_2.io.brupdate.b2.uop.prs3, issue_slots[2].brupdate.b2.uop.prs3
connect slots_2.io.brupdate.b2.uop.prs2, issue_slots[2].brupdate.b2.uop.prs2
connect slots_2.io.brupdate.b2.uop.prs1, issue_slots[2].brupdate.b2.uop.prs1
connect slots_2.io.brupdate.b2.uop.pdst, issue_slots[2].brupdate.b2.uop.pdst
connect slots_2.io.brupdate.b2.uop.rxq_idx, issue_slots[2].brupdate.b2.uop.rxq_idx
connect slots_2.io.brupdate.b2.uop.stq_idx, issue_slots[2].brupdate.b2.uop.stq_idx
connect slots_2.io.brupdate.b2.uop.ldq_idx, issue_slots[2].brupdate.b2.uop.ldq_idx
connect slots_2.io.brupdate.b2.uop.rob_idx, issue_slots[2].brupdate.b2.uop.rob_idx
connect slots_2.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[2].brupdate.b2.uop.fp_ctrl.vec
connect slots_2.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[2].brupdate.b2.uop.fp_ctrl.wflags
connect slots_2.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[2].brupdate.b2.uop.fp_ctrl.sqrt
connect slots_2.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[2].brupdate.b2.uop.fp_ctrl.div
connect slots_2.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[2].brupdate.b2.uop.fp_ctrl.fma
connect slots_2.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[2].brupdate.b2.uop.fp_ctrl.fastpipe
connect slots_2.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[2].brupdate.b2.uop.fp_ctrl.toint
connect slots_2.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[2].brupdate.b2.uop.fp_ctrl.fromint
connect slots_2.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[2].brupdate.b2.uop.fp_ctrl.typeTagOut
connect slots_2.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[2].brupdate.b2.uop.fp_ctrl.typeTagIn
connect slots_2.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[2].brupdate.b2.uop.fp_ctrl.swap23
connect slots_2.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[2].brupdate.b2.uop.fp_ctrl.swap12
connect slots_2.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[2].brupdate.b2.uop.fp_ctrl.ren3
connect slots_2.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[2].brupdate.b2.uop.fp_ctrl.ren2
connect slots_2.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[2].brupdate.b2.uop.fp_ctrl.ren1
connect slots_2.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[2].brupdate.b2.uop.fp_ctrl.wen
connect slots_2.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[2].brupdate.b2.uop.fp_ctrl.ldst
connect slots_2.io.brupdate.b2.uop.op2_sel, issue_slots[2].brupdate.b2.uop.op2_sel
connect slots_2.io.brupdate.b2.uop.op1_sel, issue_slots[2].brupdate.b2.uop.op1_sel
connect slots_2.io.brupdate.b2.uop.imm_packed, issue_slots[2].brupdate.b2.uop.imm_packed
connect slots_2.io.brupdate.b2.uop.pimm, issue_slots[2].brupdate.b2.uop.pimm
connect slots_2.io.brupdate.b2.uop.imm_sel, issue_slots[2].brupdate.b2.uop.imm_sel
connect slots_2.io.brupdate.b2.uop.imm_rename, issue_slots[2].brupdate.b2.uop.imm_rename
connect slots_2.io.brupdate.b2.uop.taken, issue_slots[2].brupdate.b2.uop.taken
connect slots_2.io.brupdate.b2.uop.pc_lob, issue_slots[2].brupdate.b2.uop.pc_lob
connect slots_2.io.brupdate.b2.uop.edge_inst, issue_slots[2].brupdate.b2.uop.edge_inst
connect slots_2.io.brupdate.b2.uop.ftq_idx, issue_slots[2].brupdate.b2.uop.ftq_idx
connect slots_2.io.brupdate.b2.uop.is_mov, issue_slots[2].brupdate.b2.uop.is_mov
connect slots_2.io.brupdate.b2.uop.is_rocc, issue_slots[2].brupdate.b2.uop.is_rocc
connect slots_2.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[2].brupdate.b2.uop.is_sys_pc2epc
connect slots_2.io.brupdate.b2.uop.is_eret, issue_slots[2].brupdate.b2.uop.is_eret
connect slots_2.io.brupdate.b2.uop.is_amo, issue_slots[2].brupdate.b2.uop.is_amo
connect slots_2.io.brupdate.b2.uop.is_sfence, issue_slots[2].brupdate.b2.uop.is_sfence
connect slots_2.io.brupdate.b2.uop.is_fencei, issue_slots[2].brupdate.b2.uop.is_fencei
connect slots_2.io.brupdate.b2.uop.is_fence, issue_slots[2].brupdate.b2.uop.is_fence
connect slots_2.io.brupdate.b2.uop.is_sfb, issue_slots[2].brupdate.b2.uop.is_sfb
connect slots_2.io.brupdate.b2.uop.br_type, issue_slots[2].brupdate.b2.uop.br_type
connect slots_2.io.brupdate.b2.uop.br_tag, issue_slots[2].brupdate.b2.uop.br_tag
connect slots_2.io.brupdate.b2.uop.br_mask, issue_slots[2].brupdate.b2.uop.br_mask
connect slots_2.io.brupdate.b2.uop.dis_col_sel, issue_slots[2].brupdate.b2.uop.dis_col_sel
connect slots_2.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[2].brupdate.b2.uop.iw_p3_bypass_hint
connect slots_2.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[2].brupdate.b2.uop.iw_p2_bypass_hint
connect slots_2.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[2].brupdate.b2.uop.iw_p1_bypass_hint
connect slots_2.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[2].brupdate.b2.uop.iw_p2_speculative_child
connect slots_2.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[2].brupdate.b2.uop.iw_p1_speculative_child
connect slots_2.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[2].brupdate.b2.uop.iw_issued_partial_dgen
connect slots_2.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[2].brupdate.b2.uop.iw_issued_partial_agen
connect slots_2.io.brupdate.b2.uop.iw_issued, issue_slots[2].brupdate.b2.uop.iw_issued
connect slots_2.io.brupdate.b2.uop.fu_code[0], issue_slots[2].brupdate.b2.uop.fu_code[0]
connect slots_2.io.brupdate.b2.uop.fu_code[1], issue_slots[2].brupdate.b2.uop.fu_code[1]
connect slots_2.io.brupdate.b2.uop.fu_code[2], issue_slots[2].brupdate.b2.uop.fu_code[2]
connect slots_2.io.brupdate.b2.uop.fu_code[3], issue_slots[2].brupdate.b2.uop.fu_code[3]
connect slots_2.io.brupdate.b2.uop.fu_code[4], issue_slots[2].brupdate.b2.uop.fu_code[4]
connect slots_2.io.brupdate.b2.uop.fu_code[5], issue_slots[2].brupdate.b2.uop.fu_code[5]
connect slots_2.io.brupdate.b2.uop.fu_code[6], issue_slots[2].brupdate.b2.uop.fu_code[6]
connect slots_2.io.brupdate.b2.uop.fu_code[7], issue_slots[2].brupdate.b2.uop.fu_code[7]
connect slots_2.io.brupdate.b2.uop.fu_code[8], issue_slots[2].brupdate.b2.uop.fu_code[8]
connect slots_2.io.brupdate.b2.uop.fu_code[9], issue_slots[2].brupdate.b2.uop.fu_code[9]
connect slots_2.io.brupdate.b2.uop.iq_type[0], issue_slots[2].brupdate.b2.uop.iq_type[0]
connect slots_2.io.brupdate.b2.uop.iq_type[1], issue_slots[2].brupdate.b2.uop.iq_type[1]
connect slots_2.io.brupdate.b2.uop.iq_type[2], issue_slots[2].brupdate.b2.uop.iq_type[2]
connect slots_2.io.brupdate.b2.uop.iq_type[3], issue_slots[2].brupdate.b2.uop.iq_type[3]
connect slots_2.io.brupdate.b2.uop.debug_pc, issue_slots[2].brupdate.b2.uop.debug_pc
connect slots_2.io.brupdate.b2.uop.is_rvc, issue_slots[2].brupdate.b2.uop.is_rvc
connect slots_2.io.brupdate.b2.uop.debug_inst, issue_slots[2].brupdate.b2.uop.debug_inst
connect slots_2.io.brupdate.b2.uop.inst, issue_slots[2].brupdate.b2.uop.inst
connect slots_2.io.brupdate.b1.mispredict_mask, issue_slots[2].brupdate.b1.mispredict_mask
connect slots_2.io.brupdate.b1.resolve_mask, issue_slots[2].brupdate.b1.resolve_mask
connect issue_slots[2].out_uop.debug_tsrc, slots_2.io.out_uop.debug_tsrc
connect issue_slots[2].out_uop.debug_fsrc, slots_2.io.out_uop.debug_fsrc
connect issue_slots[2].out_uop.bp_xcpt_if, slots_2.io.out_uop.bp_xcpt_if
connect issue_slots[2].out_uop.bp_debug_if, slots_2.io.out_uop.bp_debug_if
connect issue_slots[2].out_uop.xcpt_ma_if, slots_2.io.out_uop.xcpt_ma_if
connect issue_slots[2].out_uop.xcpt_ae_if, slots_2.io.out_uop.xcpt_ae_if
connect issue_slots[2].out_uop.xcpt_pf_if, slots_2.io.out_uop.xcpt_pf_if
connect issue_slots[2].out_uop.fp_typ, slots_2.io.out_uop.fp_typ
connect issue_slots[2].out_uop.fp_rm, slots_2.io.out_uop.fp_rm
connect issue_slots[2].out_uop.fp_val, slots_2.io.out_uop.fp_val
connect issue_slots[2].out_uop.fcn_op, slots_2.io.out_uop.fcn_op
connect issue_slots[2].out_uop.fcn_dw, slots_2.io.out_uop.fcn_dw
connect issue_slots[2].out_uop.frs3_en, slots_2.io.out_uop.frs3_en
connect issue_slots[2].out_uop.lrs2_rtype, slots_2.io.out_uop.lrs2_rtype
connect issue_slots[2].out_uop.lrs1_rtype, slots_2.io.out_uop.lrs1_rtype
connect issue_slots[2].out_uop.dst_rtype, slots_2.io.out_uop.dst_rtype
connect issue_slots[2].out_uop.lrs3, slots_2.io.out_uop.lrs3
connect issue_slots[2].out_uop.lrs2, slots_2.io.out_uop.lrs2
connect issue_slots[2].out_uop.lrs1, slots_2.io.out_uop.lrs1
connect issue_slots[2].out_uop.ldst, slots_2.io.out_uop.ldst
connect issue_slots[2].out_uop.ldst_is_rs1, slots_2.io.out_uop.ldst_is_rs1
connect issue_slots[2].out_uop.csr_cmd, slots_2.io.out_uop.csr_cmd
connect issue_slots[2].out_uop.flush_on_commit, slots_2.io.out_uop.flush_on_commit
connect issue_slots[2].out_uop.is_unique, slots_2.io.out_uop.is_unique
connect issue_slots[2].out_uop.uses_stq, slots_2.io.out_uop.uses_stq
connect issue_slots[2].out_uop.uses_ldq, slots_2.io.out_uop.uses_ldq
connect issue_slots[2].out_uop.mem_signed, slots_2.io.out_uop.mem_signed
connect issue_slots[2].out_uop.mem_size, slots_2.io.out_uop.mem_size
connect issue_slots[2].out_uop.mem_cmd, slots_2.io.out_uop.mem_cmd
connect issue_slots[2].out_uop.exc_cause, slots_2.io.out_uop.exc_cause
connect issue_slots[2].out_uop.exception, slots_2.io.out_uop.exception
connect issue_slots[2].out_uop.stale_pdst, slots_2.io.out_uop.stale_pdst
connect issue_slots[2].out_uop.ppred_busy, slots_2.io.out_uop.ppred_busy
connect issue_slots[2].out_uop.prs3_busy, slots_2.io.out_uop.prs3_busy
connect issue_slots[2].out_uop.prs2_busy, slots_2.io.out_uop.prs2_busy
connect issue_slots[2].out_uop.prs1_busy, slots_2.io.out_uop.prs1_busy
connect issue_slots[2].out_uop.ppred, slots_2.io.out_uop.ppred
connect issue_slots[2].out_uop.prs3, slots_2.io.out_uop.prs3
connect issue_slots[2].out_uop.prs2, slots_2.io.out_uop.prs2
connect issue_slots[2].out_uop.prs1, slots_2.io.out_uop.prs1
connect issue_slots[2].out_uop.pdst, slots_2.io.out_uop.pdst
connect issue_slots[2].out_uop.rxq_idx, slots_2.io.out_uop.rxq_idx
connect issue_slots[2].out_uop.stq_idx, slots_2.io.out_uop.stq_idx
connect issue_slots[2].out_uop.ldq_idx, slots_2.io.out_uop.ldq_idx
connect issue_slots[2].out_uop.rob_idx, slots_2.io.out_uop.rob_idx
connect issue_slots[2].out_uop.fp_ctrl.vec, slots_2.io.out_uop.fp_ctrl.vec
connect issue_slots[2].out_uop.fp_ctrl.wflags, slots_2.io.out_uop.fp_ctrl.wflags
connect issue_slots[2].out_uop.fp_ctrl.sqrt, slots_2.io.out_uop.fp_ctrl.sqrt
connect issue_slots[2].out_uop.fp_ctrl.div, slots_2.io.out_uop.fp_ctrl.div
connect issue_slots[2].out_uop.fp_ctrl.fma, slots_2.io.out_uop.fp_ctrl.fma
connect issue_slots[2].out_uop.fp_ctrl.fastpipe, slots_2.io.out_uop.fp_ctrl.fastpipe
connect issue_slots[2].out_uop.fp_ctrl.toint, slots_2.io.out_uop.fp_ctrl.toint
connect issue_slots[2].out_uop.fp_ctrl.fromint, slots_2.io.out_uop.fp_ctrl.fromint
connect issue_slots[2].out_uop.fp_ctrl.typeTagOut, slots_2.io.out_uop.fp_ctrl.typeTagOut
connect issue_slots[2].out_uop.fp_ctrl.typeTagIn, slots_2.io.out_uop.fp_ctrl.typeTagIn
connect issue_slots[2].out_uop.fp_ctrl.swap23, slots_2.io.out_uop.fp_ctrl.swap23
connect issue_slots[2].out_uop.fp_ctrl.swap12, slots_2.io.out_uop.fp_ctrl.swap12
connect issue_slots[2].out_uop.fp_ctrl.ren3, slots_2.io.out_uop.fp_ctrl.ren3
connect issue_slots[2].out_uop.fp_ctrl.ren2, slots_2.io.out_uop.fp_ctrl.ren2
connect issue_slots[2].out_uop.fp_ctrl.ren1, slots_2.io.out_uop.fp_ctrl.ren1
connect issue_slots[2].out_uop.fp_ctrl.wen, slots_2.io.out_uop.fp_ctrl.wen
connect issue_slots[2].out_uop.fp_ctrl.ldst, slots_2.io.out_uop.fp_ctrl.ldst
connect issue_slots[2].out_uop.op2_sel, slots_2.io.out_uop.op2_sel
connect issue_slots[2].out_uop.op1_sel, slots_2.io.out_uop.op1_sel
connect issue_slots[2].out_uop.imm_packed, slots_2.io.out_uop.imm_packed
connect issue_slots[2].out_uop.pimm, slots_2.io.out_uop.pimm
connect issue_slots[2].out_uop.imm_sel, slots_2.io.out_uop.imm_sel
connect issue_slots[2].out_uop.imm_rename, slots_2.io.out_uop.imm_rename
connect issue_slots[2].out_uop.taken, slots_2.io.out_uop.taken
connect issue_slots[2].out_uop.pc_lob, slots_2.io.out_uop.pc_lob
connect issue_slots[2].out_uop.edge_inst, slots_2.io.out_uop.edge_inst
connect issue_slots[2].out_uop.ftq_idx, slots_2.io.out_uop.ftq_idx
connect issue_slots[2].out_uop.is_mov, slots_2.io.out_uop.is_mov
connect issue_slots[2].out_uop.is_rocc, slots_2.io.out_uop.is_rocc
connect issue_slots[2].out_uop.is_sys_pc2epc, slots_2.io.out_uop.is_sys_pc2epc
connect issue_slots[2].out_uop.is_eret, slots_2.io.out_uop.is_eret
connect issue_slots[2].out_uop.is_amo, slots_2.io.out_uop.is_amo
connect issue_slots[2].out_uop.is_sfence, slots_2.io.out_uop.is_sfence
connect issue_slots[2].out_uop.is_fencei, slots_2.io.out_uop.is_fencei
connect issue_slots[2].out_uop.is_fence, slots_2.io.out_uop.is_fence
connect issue_slots[2].out_uop.is_sfb, slots_2.io.out_uop.is_sfb
connect issue_slots[2].out_uop.br_type, slots_2.io.out_uop.br_type
connect issue_slots[2].out_uop.br_tag, slots_2.io.out_uop.br_tag
connect issue_slots[2].out_uop.br_mask, slots_2.io.out_uop.br_mask
connect issue_slots[2].out_uop.dis_col_sel, slots_2.io.out_uop.dis_col_sel
connect issue_slots[2].out_uop.iw_p3_bypass_hint, slots_2.io.out_uop.iw_p3_bypass_hint
connect issue_slots[2].out_uop.iw_p2_bypass_hint, slots_2.io.out_uop.iw_p2_bypass_hint
connect issue_slots[2].out_uop.iw_p1_bypass_hint, slots_2.io.out_uop.iw_p1_bypass_hint
connect issue_slots[2].out_uop.iw_p2_speculative_child, slots_2.io.out_uop.iw_p2_speculative_child
connect issue_slots[2].out_uop.iw_p1_speculative_child, slots_2.io.out_uop.iw_p1_speculative_child
connect issue_slots[2].out_uop.iw_issued_partial_dgen, slots_2.io.out_uop.iw_issued_partial_dgen
connect issue_slots[2].out_uop.iw_issued_partial_agen, slots_2.io.out_uop.iw_issued_partial_agen
connect issue_slots[2].out_uop.iw_issued, slots_2.io.out_uop.iw_issued
connect issue_slots[2].out_uop.fu_code[0], slots_2.io.out_uop.fu_code[0]
connect issue_slots[2].out_uop.fu_code[1], slots_2.io.out_uop.fu_code[1]
connect issue_slots[2].out_uop.fu_code[2], slots_2.io.out_uop.fu_code[2]
connect issue_slots[2].out_uop.fu_code[3], slots_2.io.out_uop.fu_code[3]
connect issue_slots[2].out_uop.fu_code[4], slots_2.io.out_uop.fu_code[4]
connect issue_slots[2].out_uop.fu_code[5], slots_2.io.out_uop.fu_code[5]
connect issue_slots[2].out_uop.fu_code[6], slots_2.io.out_uop.fu_code[6]
connect issue_slots[2].out_uop.fu_code[7], slots_2.io.out_uop.fu_code[7]
connect issue_slots[2].out_uop.fu_code[8], slots_2.io.out_uop.fu_code[8]
connect issue_slots[2].out_uop.fu_code[9], slots_2.io.out_uop.fu_code[9]
connect issue_slots[2].out_uop.iq_type[0], slots_2.io.out_uop.iq_type[0]
connect issue_slots[2].out_uop.iq_type[1], slots_2.io.out_uop.iq_type[1]
connect issue_slots[2].out_uop.iq_type[2], slots_2.io.out_uop.iq_type[2]
connect issue_slots[2].out_uop.iq_type[3], slots_2.io.out_uop.iq_type[3]
connect issue_slots[2].out_uop.debug_pc, slots_2.io.out_uop.debug_pc
connect issue_slots[2].out_uop.is_rvc, slots_2.io.out_uop.is_rvc
connect issue_slots[2].out_uop.debug_inst, slots_2.io.out_uop.debug_inst
connect issue_slots[2].out_uop.inst, slots_2.io.out_uop.inst
connect slots_2.io.in_uop.bits.debug_tsrc, issue_slots[2].in_uop.bits.debug_tsrc
connect slots_2.io.in_uop.bits.debug_fsrc, issue_slots[2].in_uop.bits.debug_fsrc
connect slots_2.io.in_uop.bits.bp_xcpt_if, issue_slots[2].in_uop.bits.bp_xcpt_if
connect slots_2.io.in_uop.bits.bp_debug_if, issue_slots[2].in_uop.bits.bp_debug_if
connect slots_2.io.in_uop.bits.xcpt_ma_if, issue_slots[2].in_uop.bits.xcpt_ma_if
connect slots_2.io.in_uop.bits.xcpt_ae_if, issue_slots[2].in_uop.bits.xcpt_ae_if
connect slots_2.io.in_uop.bits.xcpt_pf_if, issue_slots[2].in_uop.bits.xcpt_pf_if
connect slots_2.io.in_uop.bits.fp_typ, issue_slots[2].in_uop.bits.fp_typ
connect slots_2.io.in_uop.bits.fp_rm, issue_slots[2].in_uop.bits.fp_rm
connect slots_2.io.in_uop.bits.fp_val, issue_slots[2].in_uop.bits.fp_val
connect slots_2.io.in_uop.bits.fcn_op, issue_slots[2].in_uop.bits.fcn_op
connect slots_2.io.in_uop.bits.fcn_dw, issue_slots[2].in_uop.bits.fcn_dw
connect slots_2.io.in_uop.bits.frs3_en, issue_slots[2].in_uop.bits.frs3_en
connect slots_2.io.in_uop.bits.lrs2_rtype, issue_slots[2].in_uop.bits.lrs2_rtype
connect slots_2.io.in_uop.bits.lrs1_rtype, issue_slots[2].in_uop.bits.lrs1_rtype
connect slots_2.io.in_uop.bits.dst_rtype, issue_slots[2].in_uop.bits.dst_rtype
connect slots_2.io.in_uop.bits.lrs3, issue_slots[2].in_uop.bits.lrs3
connect slots_2.io.in_uop.bits.lrs2, issue_slots[2].in_uop.bits.lrs2
connect slots_2.io.in_uop.bits.lrs1, issue_slots[2].in_uop.bits.lrs1
connect slots_2.io.in_uop.bits.ldst, issue_slots[2].in_uop.bits.ldst
connect slots_2.io.in_uop.bits.ldst_is_rs1, issue_slots[2].in_uop.bits.ldst_is_rs1
connect slots_2.io.in_uop.bits.csr_cmd, issue_slots[2].in_uop.bits.csr_cmd
connect slots_2.io.in_uop.bits.flush_on_commit, issue_slots[2].in_uop.bits.flush_on_commit
connect slots_2.io.in_uop.bits.is_unique, issue_slots[2].in_uop.bits.is_unique
connect slots_2.io.in_uop.bits.uses_stq, issue_slots[2].in_uop.bits.uses_stq
connect slots_2.io.in_uop.bits.uses_ldq, issue_slots[2].in_uop.bits.uses_ldq
connect slots_2.io.in_uop.bits.mem_signed, issue_slots[2].in_uop.bits.mem_signed
connect slots_2.io.in_uop.bits.mem_size, issue_slots[2].in_uop.bits.mem_size
connect slots_2.io.in_uop.bits.mem_cmd, issue_slots[2].in_uop.bits.mem_cmd
connect slots_2.io.in_uop.bits.exc_cause, issue_slots[2].in_uop.bits.exc_cause
connect slots_2.io.in_uop.bits.exception, issue_slots[2].in_uop.bits.exception
connect slots_2.io.in_uop.bits.stale_pdst, issue_slots[2].in_uop.bits.stale_pdst
connect slots_2.io.in_uop.bits.ppred_busy, issue_slots[2].in_uop.bits.ppred_busy
connect slots_2.io.in_uop.bits.prs3_busy, issue_slots[2].in_uop.bits.prs3_busy
connect slots_2.io.in_uop.bits.prs2_busy, issue_slots[2].in_uop.bits.prs2_busy
connect slots_2.io.in_uop.bits.prs1_busy, issue_slots[2].in_uop.bits.prs1_busy
connect slots_2.io.in_uop.bits.ppred, issue_slots[2].in_uop.bits.ppred
connect slots_2.io.in_uop.bits.prs3, issue_slots[2].in_uop.bits.prs3
connect slots_2.io.in_uop.bits.prs2, issue_slots[2].in_uop.bits.prs2
connect slots_2.io.in_uop.bits.prs1, issue_slots[2].in_uop.bits.prs1
connect slots_2.io.in_uop.bits.pdst, issue_slots[2].in_uop.bits.pdst
connect slots_2.io.in_uop.bits.rxq_idx, issue_slots[2].in_uop.bits.rxq_idx
connect slots_2.io.in_uop.bits.stq_idx, issue_slots[2].in_uop.bits.stq_idx
connect slots_2.io.in_uop.bits.ldq_idx, issue_slots[2].in_uop.bits.ldq_idx
connect slots_2.io.in_uop.bits.rob_idx, issue_slots[2].in_uop.bits.rob_idx
connect slots_2.io.in_uop.bits.fp_ctrl.vec, issue_slots[2].in_uop.bits.fp_ctrl.vec
connect slots_2.io.in_uop.bits.fp_ctrl.wflags, issue_slots[2].in_uop.bits.fp_ctrl.wflags
connect slots_2.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[2].in_uop.bits.fp_ctrl.sqrt
connect slots_2.io.in_uop.bits.fp_ctrl.div, issue_slots[2].in_uop.bits.fp_ctrl.div
connect slots_2.io.in_uop.bits.fp_ctrl.fma, issue_slots[2].in_uop.bits.fp_ctrl.fma
connect slots_2.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[2].in_uop.bits.fp_ctrl.fastpipe
connect slots_2.io.in_uop.bits.fp_ctrl.toint, issue_slots[2].in_uop.bits.fp_ctrl.toint
connect slots_2.io.in_uop.bits.fp_ctrl.fromint, issue_slots[2].in_uop.bits.fp_ctrl.fromint
connect slots_2.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[2].in_uop.bits.fp_ctrl.typeTagOut
connect slots_2.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[2].in_uop.bits.fp_ctrl.typeTagIn
connect slots_2.io.in_uop.bits.fp_ctrl.swap23, issue_slots[2].in_uop.bits.fp_ctrl.swap23
connect slots_2.io.in_uop.bits.fp_ctrl.swap12, issue_slots[2].in_uop.bits.fp_ctrl.swap12
connect slots_2.io.in_uop.bits.fp_ctrl.ren3, issue_slots[2].in_uop.bits.fp_ctrl.ren3
connect slots_2.io.in_uop.bits.fp_ctrl.ren2, issue_slots[2].in_uop.bits.fp_ctrl.ren2
connect slots_2.io.in_uop.bits.fp_ctrl.ren1, issue_slots[2].in_uop.bits.fp_ctrl.ren1
connect slots_2.io.in_uop.bits.fp_ctrl.wen, issue_slots[2].in_uop.bits.fp_ctrl.wen
connect slots_2.io.in_uop.bits.fp_ctrl.ldst, issue_slots[2].in_uop.bits.fp_ctrl.ldst
connect slots_2.io.in_uop.bits.op2_sel, issue_slots[2].in_uop.bits.op2_sel
connect slots_2.io.in_uop.bits.op1_sel, issue_slots[2].in_uop.bits.op1_sel
connect slots_2.io.in_uop.bits.imm_packed, issue_slots[2].in_uop.bits.imm_packed
connect slots_2.io.in_uop.bits.pimm, issue_slots[2].in_uop.bits.pimm
connect slots_2.io.in_uop.bits.imm_sel, issue_slots[2].in_uop.bits.imm_sel
connect slots_2.io.in_uop.bits.imm_rename, issue_slots[2].in_uop.bits.imm_rename
connect slots_2.io.in_uop.bits.taken, issue_slots[2].in_uop.bits.taken
connect slots_2.io.in_uop.bits.pc_lob, issue_slots[2].in_uop.bits.pc_lob
connect slots_2.io.in_uop.bits.edge_inst, issue_slots[2].in_uop.bits.edge_inst
connect slots_2.io.in_uop.bits.ftq_idx, issue_slots[2].in_uop.bits.ftq_idx
connect slots_2.io.in_uop.bits.is_mov, issue_slots[2].in_uop.bits.is_mov
connect slots_2.io.in_uop.bits.is_rocc, issue_slots[2].in_uop.bits.is_rocc
connect slots_2.io.in_uop.bits.is_sys_pc2epc, issue_slots[2].in_uop.bits.is_sys_pc2epc
connect slots_2.io.in_uop.bits.is_eret, issue_slots[2].in_uop.bits.is_eret
connect slots_2.io.in_uop.bits.is_amo, issue_slots[2].in_uop.bits.is_amo
connect slots_2.io.in_uop.bits.is_sfence, issue_slots[2].in_uop.bits.is_sfence
connect slots_2.io.in_uop.bits.is_fencei, issue_slots[2].in_uop.bits.is_fencei
connect slots_2.io.in_uop.bits.is_fence, issue_slots[2].in_uop.bits.is_fence
connect slots_2.io.in_uop.bits.is_sfb, issue_slots[2].in_uop.bits.is_sfb
connect slots_2.io.in_uop.bits.br_type, issue_slots[2].in_uop.bits.br_type
connect slots_2.io.in_uop.bits.br_tag, issue_slots[2].in_uop.bits.br_tag
connect slots_2.io.in_uop.bits.br_mask, issue_slots[2].in_uop.bits.br_mask
connect slots_2.io.in_uop.bits.dis_col_sel, issue_slots[2].in_uop.bits.dis_col_sel
connect slots_2.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[2].in_uop.bits.iw_p3_bypass_hint
connect slots_2.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[2].in_uop.bits.iw_p2_bypass_hint
connect slots_2.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[2].in_uop.bits.iw_p1_bypass_hint
connect slots_2.io.in_uop.bits.iw_p2_speculative_child, issue_slots[2].in_uop.bits.iw_p2_speculative_child
connect slots_2.io.in_uop.bits.iw_p1_speculative_child, issue_slots[2].in_uop.bits.iw_p1_speculative_child
connect slots_2.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[2].in_uop.bits.iw_issued_partial_dgen
connect slots_2.io.in_uop.bits.iw_issued_partial_agen, issue_slots[2].in_uop.bits.iw_issued_partial_agen
connect slots_2.io.in_uop.bits.iw_issued, issue_slots[2].in_uop.bits.iw_issued
connect slots_2.io.in_uop.bits.fu_code[0], issue_slots[2].in_uop.bits.fu_code[0]
connect slots_2.io.in_uop.bits.fu_code[1], issue_slots[2].in_uop.bits.fu_code[1]
connect slots_2.io.in_uop.bits.fu_code[2], issue_slots[2].in_uop.bits.fu_code[2]
connect slots_2.io.in_uop.bits.fu_code[3], issue_slots[2].in_uop.bits.fu_code[3]
connect slots_2.io.in_uop.bits.fu_code[4], issue_slots[2].in_uop.bits.fu_code[4]
connect slots_2.io.in_uop.bits.fu_code[5], issue_slots[2].in_uop.bits.fu_code[5]
connect slots_2.io.in_uop.bits.fu_code[6], issue_slots[2].in_uop.bits.fu_code[6]
connect slots_2.io.in_uop.bits.fu_code[7], issue_slots[2].in_uop.bits.fu_code[7]
connect slots_2.io.in_uop.bits.fu_code[8], issue_slots[2].in_uop.bits.fu_code[8]
connect slots_2.io.in_uop.bits.fu_code[9], issue_slots[2].in_uop.bits.fu_code[9]
connect slots_2.io.in_uop.bits.iq_type[0], issue_slots[2].in_uop.bits.iq_type[0]
connect slots_2.io.in_uop.bits.iq_type[1], issue_slots[2].in_uop.bits.iq_type[1]
connect slots_2.io.in_uop.bits.iq_type[2], issue_slots[2].in_uop.bits.iq_type[2]
connect slots_2.io.in_uop.bits.iq_type[3], issue_slots[2].in_uop.bits.iq_type[3]
connect slots_2.io.in_uop.bits.debug_pc, issue_slots[2].in_uop.bits.debug_pc
connect slots_2.io.in_uop.bits.is_rvc, issue_slots[2].in_uop.bits.is_rvc
connect slots_2.io.in_uop.bits.debug_inst, issue_slots[2].in_uop.bits.debug_inst
connect slots_2.io.in_uop.bits.inst, issue_slots[2].in_uop.bits.inst
connect slots_2.io.in_uop.valid, issue_slots[2].in_uop.valid
connect issue_slots[2].iss_uop.debug_tsrc, slots_2.io.iss_uop.debug_tsrc
connect issue_slots[2].iss_uop.debug_fsrc, slots_2.io.iss_uop.debug_fsrc
connect issue_slots[2].iss_uop.bp_xcpt_if, slots_2.io.iss_uop.bp_xcpt_if
connect issue_slots[2].iss_uop.bp_debug_if, slots_2.io.iss_uop.bp_debug_if
connect issue_slots[2].iss_uop.xcpt_ma_if, slots_2.io.iss_uop.xcpt_ma_if
connect issue_slots[2].iss_uop.xcpt_ae_if, slots_2.io.iss_uop.xcpt_ae_if
connect issue_slots[2].iss_uop.xcpt_pf_if, slots_2.io.iss_uop.xcpt_pf_if
connect issue_slots[2].iss_uop.fp_typ, slots_2.io.iss_uop.fp_typ
connect issue_slots[2].iss_uop.fp_rm, slots_2.io.iss_uop.fp_rm
connect issue_slots[2].iss_uop.fp_val, slots_2.io.iss_uop.fp_val
connect issue_slots[2].iss_uop.fcn_op, slots_2.io.iss_uop.fcn_op
connect issue_slots[2].iss_uop.fcn_dw, slots_2.io.iss_uop.fcn_dw
connect issue_slots[2].iss_uop.frs3_en, slots_2.io.iss_uop.frs3_en
connect issue_slots[2].iss_uop.lrs2_rtype, slots_2.io.iss_uop.lrs2_rtype
connect issue_slots[2].iss_uop.lrs1_rtype, slots_2.io.iss_uop.lrs1_rtype
connect issue_slots[2].iss_uop.dst_rtype, slots_2.io.iss_uop.dst_rtype
connect issue_slots[2].iss_uop.lrs3, slots_2.io.iss_uop.lrs3
connect issue_slots[2].iss_uop.lrs2, slots_2.io.iss_uop.lrs2
connect issue_slots[2].iss_uop.lrs1, slots_2.io.iss_uop.lrs1
connect issue_slots[2].iss_uop.ldst, slots_2.io.iss_uop.ldst
connect issue_slots[2].iss_uop.ldst_is_rs1, slots_2.io.iss_uop.ldst_is_rs1
connect issue_slots[2].iss_uop.csr_cmd, slots_2.io.iss_uop.csr_cmd
connect issue_slots[2].iss_uop.flush_on_commit, slots_2.io.iss_uop.flush_on_commit
connect issue_slots[2].iss_uop.is_unique, slots_2.io.iss_uop.is_unique
connect issue_slots[2].iss_uop.uses_stq, slots_2.io.iss_uop.uses_stq
connect issue_slots[2].iss_uop.uses_ldq, slots_2.io.iss_uop.uses_ldq
connect issue_slots[2].iss_uop.mem_signed, slots_2.io.iss_uop.mem_signed
connect issue_slots[2].iss_uop.mem_size, slots_2.io.iss_uop.mem_size
connect issue_slots[2].iss_uop.mem_cmd, slots_2.io.iss_uop.mem_cmd
connect issue_slots[2].iss_uop.exc_cause, slots_2.io.iss_uop.exc_cause
connect issue_slots[2].iss_uop.exception, slots_2.io.iss_uop.exception
connect issue_slots[2].iss_uop.stale_pdst, slots_2.io.iss_uop.stale_pdst
connect issue_slots[2].iss_uop.ppred_busy, slots_2.io.iss_uop.ppred_busy
connect issue_slots[2].iss_uop.prs3_busy, slots_2.io.iss_uop.prs3_busy
connect issue_slots[2].iss_uop.prs2_busy, slots_2.io.iss_uop.prs2_busy
connect issue_slots[2].iss_uop.prs1_busy, slots_2.io.iss_uop.prs1_busy
connect issue_slots[2].iss_uop.ppred, slots_2.io.iss_uop.ppred
connect issue_slots[2].iss_uop.prs3, slots_2.io.iss_uop.prs3
connect issue_slots[2].iss_uop.prs2, slots_2.io.iss_uop.prs2
connect issue_slots[2].iss_uop.prs1, slots_2.io.iss_uop.prs1
connect issue_slots[2].iss_uop.pdst, slots_2.io.iss_uop.pdst
connect issue_slots[2].iss_uop.rxq_idx, slots_2.io.iss_uop.rxq_idx
connect issue_slots[2].iss_uop.stq_idx, slots_2.io.iss_uop.stq_idx
connect issue_slots[2].iss_uop.ldq_idx, slots_2.io.iss_uop.ldq_idx
connect issue_slots[2].iss_uop.rob_idx, slots_2.io.iss_uop.rob_idx
connect issue_slots[2].iss_uop.fp_ctrl.vec, slots_2.io.iss_uop.fp_ctrl.vec
connect issue_slots[2].iss_uop.fp_ctrl.wflags, slots_2.io.iss_uop.fp_ctrl.wflags
connect issue_slots[2].iss_uop.fp_ctrl.sqrt, slots_2.io.iss_uop.fp_ctrl.sqrt
connect issue_slots[2].iss_uop.fp_ctrl.div, slots_2.io.iss_uop.fp_ctrl.div
connect issue_slots[2].iss_uop.fp_ctrl.fma, slots_2.io.iss_uop.fp_ctrl.fma
connect issue_slots[2].iss_uop.fp_ctrl.fastpipe, slots_2.io.iss_uop.fp_ctrl.fastpipe
connect issue_slots[2].iss_uop.fp_ctrl.toint, slots_2.io.iss_uop.fp_ctrl.toint
connect issue_slots[2].iss_uop.fp_ctrl.fromint, slots_2.io.iss_uop.fp_ctrl.fromint
connect issue_slots[2].iss_uop.fp_ctrl.typeTagOut, slots_2.io.iss_uop.fp_ctrl.typeTagOut
connect issue_slots[2].iss_uop.fp_ctrl.typeTagIn, slots_2.io.iss_uop.fp_ctrl.typeTagIn
connect issue_slots[2].iss_uop.fp_ctrl.swap23, slots_2.io.iss_uop.fp_ctrl.swap23
connect issue_slots[2].iss_uop.fp_ctrl.swap12, slots_2.io.iss_uop.fp_ctrl.swap12
connect issue_slots[2].iss_uop.fp_ctrl.ren3, slots_2.io.iss_uop.fp_ctrl.ren3
connect issue_slots[2].iss_uop.fp_ctrl.ren2, slots_2.io.iss_uop.fp_ctrl.ren2
connect issue_slots[2].iss_uop.fp_ctrl.ren1, slots_2.io.iss_uop.fp_ctrl.ren1
connect issue_slots[2].iss_uop.fp_ctrl.wen, slots_2.io.iss_uop.fp_ctrl.wen
connect issue_slots[2].iss_uop.fp_ctrl.ldst, slots_2.io.iss_uop.fp_ctrl.ldst
connect issue_slots[2].iss_uop.op2_sel, slots_2.io.iss_uop.op2_sel
connect issue_slots[2].iss_uop.op1_sel, slots_2.io.iss_uop.op1_sel
connect issue_slots[2].iss_uop.imm_packed, slots_2.io.iss_uop.imm_packed
connect issue_slots[2].iss_uop.pimm, slots_2.io.iss_uop.pimm
connect issue_slots[2].iss_uop.imm_sel, slots_2.io.iss_uop.imm_sel
connect issue_slots[2].iss_uop.imm_rename, slots_2.io.iss_uop.imm_rename
connect issue_slots[2].iss_uop.taken, slots_2.io.iss_uop.taken
connect issue_slots[2].iss_uop.pc_lob, slots_2.io.iss_uop.pc_lob
connect issue_slots[2].iss_uop.edge_inst, slots_2.io.iss_uop.edge_inst
connect issue_slots[2].iss_uop.ftq_idx, slots_2.io.iss_uop.ftq_idx
connect issue_slots[2].iss_uop.is_mov, slots_2.io.iss_uop.is_mov
connect issue_slots[2].iss_uop.is_rocc, slots_2.io.iss_uop.is_rocc
connect issue_slots[2].iss_uop.is_sys_pc2epc, slots_2.io.iss_uop.is_sys_pc2epc
connect issue_slots[2].iss_uop.is_eret, slots_2.io.iss_uop.is_eret
connect issue_slots[2].iss_uop.is_amo, slots_2.io.iss_uop.is_amo
connect issue_slots[2].iss_uop.is_sfence, slots_2.io.iss_uop.is_sfence
connect issue_slots[2].iss_uop.is_fencei, slots_2.io.iss_uop.is_fencei
connect issue_slots[2].iss_uop.is_fence, slots_2.io.iss_uop.is_fence
connect issue_slots[2].iss_uop.is_sfb, slots_2.io.iss_uop.is_sfb
connect issue_slots[2].iss_uop.br_type, slots_2.io.iss_uop.br_type
connect issue_slots[2].iss_uop.br_tag, slots_2.io.iss_uop.br_tag
connect issue_slots[2].iss_uop.br_mask, slots_2.io.iss_uop.br_mask
connect issue_slots[2].iss_uop.dis_col_sel, slots_2.io.iss_uop.dis_col_sel
connect issue_slots[2].iss_uop.iw_p3_bypass_hint, slots_2.io.iss_uop.iw_p3_bypass_hint
connect issue_slots[2].iss_uop.iw_p2_bypass_hint, slots_2.io.iss_uop.iw_p2_bypass_hint
connect issue_slots[2].iss_uop.iw_p1_bypass_hint, slots_2.io.iss_uop.iw_p1_bypass_hint
connect issue_slots[2].iss_uop.iw_p2_speculative_child, slots_2.io.iss_uop.iw_p2_speculative_child
connect issue_slots[2].iss_uop.iw_p1_speculative_child, slots_2.io.iss_uop.iw_p1_speculative_child
connect issue_slots[2].iss_uop.iw_issued_partial_dgen, slots_2.io.iss_uop.iw_issued_partial_dgen
connect issue_slots[2].iss_uop.iw_issued_partial_agen, slots_2.io.iss_uop.iw_issued_partial_agen
connect issue_slots[2].iss_uop.iw_issued, slots_2.io.iss_uop.iw_issued
connect issue_slots[2].iss_uop.fu_code[0], slots_2.io.iss_uop.fu_code[0]
connect issue_slots[2].iss_uop.fu_code[1], slots_2.io.iss_uop.fu_code[1]
connect issue_slots[2].iss_uop.fu_code[2], slots_2.io.iss_uop.fu_code[2]
connect issue_slots[2].iss_uop.fu_code[3], slots_2.io.iss_uop.fu_code[3]
connect issue_slots[2].iss_uop.fu_code[4], slots_2.io.iss_uop.fu_code[4]
connect issue_slots[2].iss_uop.fu_code[5], slots_2.io.iss_uop.fu_code[5]
connect issue_slots[2].iss_uop.fu_code[6], slots_2.io.iss_uop.fu_code[6]
connect issue_slots[2].iss_uop.fu_code[7], slots_2.io.iss_uop.fu_code[7]
connect issue_slots[2].iss_uop.fu_code[8], slots_2.io.iss_uop.fu_code[8]
connect issue_slots[2].iss_uop.fu_code[9], slots_2.io.iss_uop.fu_code[9]
connect issue_slots[2].iss_uop.iq_type[0], slots_2.io.iss_uop.iq_type[0]
connect issue_slots[2].iss_uop.iq_type[1], slots_2.io.iss_uop.iq_type[1]
connect issue_slots[2].iss_uop.iq_type[2], slots_2.io.iss_uop.iq_type[2]
connect issue_slots[2].iss_uop.iq_type[3], slots_2.io.iss_uop.iq_type[3]
connect issue_slots[2].iss_uop.debug_pc, slots_2.io.iss_uop.debug_pc
connect issue_slots[2].iss_uop.is_rvc, slots_2.io.iss_uop.is_rvc
connect issue_slots[2].iss_uop.debug_inst, slots_2.io.iss_uop.debug_inst
connect issue_slots[2].iss_uop.inst, slots_2.io.iss_uop.inst
connect slots_2.io.grant, issue_slots[2].grant
connect issue_slots[2].request, slots_2.io.request
connect issue_slots[2].will_be_valid, slots_2.io.will_be_valid
connect issue_slots[2].valid, slots_2.io.valid
connect slots_3.io.child_rebusys, issue_slots[3].child_rebusys
connect slots_3.io.pred_wakeup_port.bits, issue_slots[3].pred_wakeup_port.bits
connect slots_3.io.pred_wakeup_port.valid, issue_slots[3].pred_wakeup_port.valid
connect slots_3.io.wakeup_ports[0].bits.rebusy, issue_slots[3].wakeup_ports[0].bits.rebusy
connect slots_3.io.wakeup_ports[0].bits.speculative_mask, issue_slots[3].wakeup_ports[0].bits.speculative_mask
connect slots_3.io.wakeup_ports[0].bits.bypassable, issue_slots[3].wakeup_ports[0].bits.bypassable
connect slots_3.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[3].wakeup_ports[0].bits.uop.debug_tsrc
connect slots_3.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[3].wakeup_ports[0].bits.uop.debug_fsrc
connect slots_3.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[3].wakeup_ports[0].bits.uop.bp_xcpt_if
connect slots_3.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[3].wakeup_ports[0].bits.uop.bp_debug_if
connect slots_3.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[3].wakeup_ports[0].bits.uop.xcpt_ma_if
connect slots_3.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[3].wakeup_ports[0].bits.uop.xcpt_ae_if
connect slots_3.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[3].wakeup_ports[0].bits.uop.xcpt_pf_if
connect slots_3.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[3].wakeup_ports[0].bits.uop.fp_typ
connect slots_3.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[3].wakeup_ports[0].bits.uop.fp_rm
connect slots_3.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[3].wakeup_ports[0].bits.uop.fp_val
connect slots_3.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[3].wakeup_ports[0].bits.uop.fcn_op
connect slots_3.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[3].wakeup_ports[0].bits.uop.fcn_dw
connect slots_3.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[3].wakeup_ports[0].bits.uop.frs3_en
connect slots_3.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[3].wakeup_ports[0].bits.uop.lrs2_rtype
connect slots_3.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[3].wakeup_ports[0].bits.uop.lrs1_rtype
connect slots_3.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[3].wakeup_ports[0].bits.uop.dst_rtype
connect slots_3.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[3].wakeup_ports[0].bits.uop.lrs3
connect slots_3.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[3].wakeup_ports[0].bits.uop.lrs2
connect slots_3.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[3].wakeup_ports[0].bits.uop.lrs1
connect slots_3.io.wakeup_ports[0].bits.uop.ldst, issue_slots[3].wakeup_ports[0].bits.uop.ldst
connect slots_3.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[3].wakeup_ports[0].bits.uop.ldst_is_rs1
connect slots_3.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[3].wakeup_ports[0].bits.uop.csr_cmd
connect slots_3.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[3].wakeup_ports[0].bits.uop.flush_on_commit
connect slots_3.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[3].wakeup_ports[0].bits.uop.is_unique
connect slots_3.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[3].wakeup_ports[0].bits.uop.uses_stq
connect slots_3.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[3].wakeup_ports[0].bits.uop.uses_ldq
connect slots_3.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[3].wakeup_ports[0].bits.uop.mem_signed
connect slots_3.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[3].wakeup_ports[0].bits.uop.mem_size
connect slots_3.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[3].wakeup_ports[0].bits.uop.mem_cmd
connect slots_3.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[3].wakeup_ports[0].bits.uop.exc_cause
connect slots_3.io.wakeup_ports[0].bits.uop.exception, issue_slots[3].wakeup_ports[0].bits.uop.exception
connect slots_3.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[3].wakeup_ports[0].bits.uop.stale_pdst
connect slots_3.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[3].wakeup_ports[0].bits.uop.ppred_busy
connect slots_3.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[3].wakeup_ports[0].bits.uop.prs3_busy
connect slots_3.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[3].wakeup_ports[0].bits.uop.prs2_busy
connect slots_3.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[3].wakeup_ports[0].bits.uop.prs1_busy
connect slots_3.io.wakeup_ports[0].bits.uop.ppred, issue_slots[3].wakeup_ports[0].bits.uop.ppred
connect slots_3.io.wakeup_ports[0].bits.uop.prs3, issue_slots[3].wakeup_ports[0].bits.uop.prs3
connect slots_3.io.wakeup_ports[0].bits.uop.prs2, issue_slots[3].wakeup_ports[0].bits.uop.prs2
connect slots_3.io.wakeup_ports[0].bits.uop.prs1, issue_slots[3].wakeup_ports[0].bits.uop.prs1
connect slots_3.io.wakeup_ports[0].bits.uop.pdst, issue_slots[3].wakeup_ports[0].bits.uop.pdst
connect slots_3.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[3].wakeup_ports[0].bits.uop.rxq_idx
connect slots_3.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[3].wakeup_ports[0].bits.uop.stq_idx
connect slots_3.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[3].wakeup_ports[0].bits.uop.ldq_idx
connect slots_3.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[3].wakeup_ports[0].bits.uop.rob_idx
connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.vec
connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.wflags
connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.sqrt
connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.div
connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.fma
connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe
connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.toint
connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.fromint
connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut
connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn
connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.swap23
connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.swap12
connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.ren3
connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.ren2
connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.ren1
connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.wen
connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.ldst
connect slots_3.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[3].wakeup_ports[0].bits.uop.op2_sel
connect slots_3.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[3].wakeup_ports[0].bits.uop.op1_sel
connect slots_3.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[3].wakeup_ports[0].bits.uop.imm_packed
connect slots_3.io.wakeup_ports[0].bits.uop.pimm, issue_slots[3].wakeup_ports[0].bits.uop.pimm
connect slots_3.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[3].wakeup_ports[0].bits.uop.imm_sel
connect slots_3.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[3].wakeup_ports[0].bits.uop.imm_rename
connect slots_3.io.wakeup_ports[0].bits.uop.taken, issue_slots[3].wakeup_ports[0].bits.uop.taken
connect slots_3.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[3].wakeup_ports[0].bits.uop.pc_lob
connect slots_3.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[3].wakeup_ports[0].bits.uop.edge_inst
connect slots_3.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[3].wakeup_ports[0].bits.uop.ftq_idx
connect slots_3.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[3].wakeup_ports[0].bits.uop.is_mov
connect slots_3.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[3].wakeup_ports[0].bits.uop.is_rocc
connect slots_3.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[3].wakeup_ports[0].bits.uop.is_sys_pc2epc
connect slots_3.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[3].wakeup_ports[0].bits.uop.is_eret
connect slots_3.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[3].wakeup_ports[0].bits.uop.is_amo
connect slots_3.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[3].wakeup_ports[0].bits.uop.is_sfence
connect slots_3.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[3].wakeup_ports[0].bits.uop.is_fencei
connect slots_3.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[3].wakeup_ports[0].bits.uop.is_fence
connect slots_3.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[3].wakeup_ports[0].bits.uop.is_sfb
connect slots_3.io.wakeup_ports[0].bits.uop.br_type, issue_slots[3].wakeup_ports[0].bits.uop.br_type
connect slots_3.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[3].wakeup_ports[0].bits.uop.br_tag
connect slots_3.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[3].wakeup_ports[0].bits.uop.br_mask
connect slots_3.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[3].wakeup_ports[0].bits.uop.dis_col_sel
connect slots_3.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[3].wakeup_ports[0].bits.uop.iw_p3_bypass_hint
connect slots_3.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[3].wakeup_ports[0].bits.uop.iw_p2_bypass_hint
connect slots_3.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[3].wakeup_ports[0].bits.uop.iw_p1_bypass_hint
connect slots_3.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[3].wakeup_ports[0].bits.uop.iw_p2_speculative_child
connect slots_3.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[3].wakeup_ports[0].bits.uop.iw_p1_speculative_child
connect slots_3.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[3].wakeup_ports[0].bits.uop.iw_issued_partial_dgen
connect slots_3.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[3].wakeup_ports[0].bits.uop.iw_issued_partial_agen
connect slots_3.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[3].wakeup_ports[0].bits.uop.iw_issued
connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[0]
connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[1]
connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[2]
connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[3]
connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[4]
connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[5]
connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[6]
connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[7]
connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[8]
connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[9]
connect slots_3.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[3].wakeup_ports[0].bits.uop.iq_type[0]
connect slots_3.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[3].wakeup_ports[0].bits.uop.iq_type[1]
connect slots_3.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[3].wakeup_ports[0].bits.uop.iq_type[2]
connect slots_3.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[3].wakeup_ports[0].bits.uop.iq_type[3]
connect slots_3.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[3].wakeup_ports[0].bits.uop.debug_pc
connect slots_3.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[3].wakeup_ports[0].bits.uop.is_rvc
connect slots_3.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[3].wakeup_ports[0].bits.uop.debug_inst
connect slots_3.io.wakeup_ports[0].bits.uop.inst, issue_slots[3].wakeup_ports[0].bits.uop.inst
connect slots_3.io.wakeup_ports[0].valid, issue_slots[3].wakeup_ports[0].valid
connect slots_3.io.wakeup_ports[1].bits.rebusy, issue_slots[3].wakeup_ports[1].bits.rebusy
connect slots_3.io.wakeup_ports[1].bits.speculative_mask, issue_slots[3].wakeup_ports[1].bits.speculative_mask
connect slots_3.io.wakeup_ports[1].bits.bypassable, issue_slots[3].wakeup_ports[1].bits.bypassable
connect slots_3.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[3].wakeup_ports[1].bits.uop.debug_tsrc
connect slots_3.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[3].wakeup_ports[1].bits.uop.debug_fsrc
connect slots_3.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[3].wakeup_ports[1].bits.uop.bp_xcpt_if
connect slots_3.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[3].wakeup_ports[1].bits.uop.bp_debug_if
connect slots_3.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[3].wakeup_ports[1].bits.uop.xcpt_ma_if
connect slots_3.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[3].wakeup_ports[1].bits.uop.xcpt_ae_if
connect slots_3.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[3].wakeup_ports[1].bits.uop.xcpt_pf_if
connect slots_3.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[3].wakeup_ports[1].bits.uop.fp_typ
connect slots_3.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[3].wakeup_ports[1].bits.uop.fp_rm
connect slots_3.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[3].wakeup_ports[1].bits.uop.fp_val
connect slots_3.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[3].wakeup_ports[1].bits.uop.fcn_op
connect slots_3.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[3].wakeup_ports[1].bits.uop.fcn_dw
connect slots_3.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[3].wakeup_ports[1].bits.uop.frs3_en
connect slots_3.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[3].wakeup_ports[1].bits.uop.lrs2_rtype
connect slots_3.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[3].wakeup_ports[1].bits.uop.lrs1_rtype
connect slots_3.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[3].wakeup_ports[1].bits.uop.dst_rtype
connect slots_3.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[3].wakeup_ports[1].bits.uop.lrs3
connect slots_3.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[3].wakeup_ports[1].bits.uop.lrs2
connect slots_3.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[3].wakeup_ports[1].bits.uop.lrs1
connect slots_3.io.wakeup_ports[1].bits.uop.ldst, issue_slots[3].wakeup_ports[1].bits.uop.ldst
connect slots_3.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[3].wakeup_ports[1].bits.uop.ldst_is_rs1
connect slots_3.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[3].wakeup_ports[1].bits.uop.csr_cmd
connect slots_3.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[3].wakeup_ports[1].bits.uop.flush_on_commit
connect slots_3.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[3].wakeup_ports[1].bits.uop.is_unique
connect slots_3.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[3].wakeup_ports[1].bits.uop.uses_stq
connect slots_3.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[3].wakeup_ports[1].bits.uop.uses_ldq
connect slots_3.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[3].wakeup_ports[1].bits.uop.mem_signed
connect slots_3.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[3].wakeup_ports[1].bits.uop.mem_size
connect slots_3.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[3].wakeup_ports[1].bits.uop.mem_cmd
connect slots_3.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[3].wakeup_ports[1].bits.uop.exc_cause
connect slots_3.io.wakeup_ports[1].bits.uop.exception, issue_slots[3].wakeup_ports[1].bits.uop.exception
connect slots_3.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[3].wakeup_ports[1].bits.uop.stale_pdst
connect slots_3.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[3].wakeup_ports[1].bits.uop.ppred_busy
connect slots_3.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[3].wakeup_ports[1].bits.uop.prs3_busy
connect slots_3.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[3].wakeup_ports[1].bits.uop.prs2_busy
connect slots_3.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[3].wakeup_ports[1].bits.uop.prs1_busy
connect slots_3.io.wakeup_ports[1].bits.uop.ppred, issue_slots[3].wakeup_ports[1].bits.uop.ppred
connect slots_3.io.wakeup_ports[1].bits.uop.prs3, issue_slots[3].wakeup_ports[1].bits.uop.prs3
connect slots_3.io.wakeup_ports[1].bits.uop.prs2, issue_slots[3].wakeup_ports[1].bits.uop.prs2
connect slots_3.io.wakeup_ports[1].bits.uop.prs1, issue_slots[3].wakeup_ports[1].bits.uop.prs1
connect slots_3.io.wakeup_ports[1].bits.uop.pdst, issue_slots[3].wakeup_ports[1].bits.uop.pdst
connect slots_3.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[3].wakeup_ports[1].bits.uop.rxq_idx
connect slots_3.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[3].wakeup_ports[1].bits.uop.stq_idx
connect slots_3.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[3].wakeup_ports[1].bits.uop.ldq_idx
connect slots_3.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[3].wakeup_ports[1].bits.uop.rob_idx
connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.vec
connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.wflags
connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.sqrt
connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.div
connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.fma
connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe
connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.toint
connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.fromint
connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut
connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn
connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.swap23
connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.swap12
connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.ren3
connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.ren2
connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.ren1
connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.wen
connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.ldst
connect slots_3.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[3].wakeup_ports[1].bits.uop.op2_sel
connect slots_3.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[3].wakeup_ports[1].bits.uop.op1_sel
connect slots_3.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[3].wakeup_ports[1].bits.uop.imm_packed
connect slots_3.io.wakeup_ports[1].bits.uop.pimm, issue_slots[3].wakeup_ports[1].bits.uop.pimm
connect slots_3.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[3].wakeup_ports[1].bits.uop.imm_sel
connect slots_3.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[3].wakeup_ports[1].bits.uop.imm_rename
connect slots_3.io.wakeup_ports[1].bits.uop.taken, issue_slots[3].wakeup_ports[1].bits.uop.taken
connect slots_3.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[3].wakeup_ports[1].bits.uop.pc_lob
connect slots_3.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[3].wakeup_ports[1].bits.uop.edge_inst
connect slots_3.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[3].wakeup_ports[1].bits.uop.ftq_idx
connect slots_3.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[3].wakeup_ports[1].bits.uop.is_mov
connect slots_3.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[3].wakeup_ports[1].bits.uop.is_rocc
connect slots_3.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[3].wakeup_ports[1].bits.uop.is_sys_pc2epc
connect slots_3.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[3].wakeup_ports[1].bits.uop.is_eret
connect slots_3.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[3].wakeup_ports[1].bits.uop.is_amo
connect slots_3.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[3].wakeup_ports[1].bits.uop.is_sfence
connect slots_3.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[3].wakeup_ports[1].bits.uop.is_fencei
connect slots_3.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[3].wakeup_ports[1].bits.uop.is_fence
connect slots_3.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[3].wakeup_ports[1].bits.uop.is_sfb
connect slots_3.io.wakeup_ports[1].bits.uop.br_type, issue_slots[3].wakeup_ports[1].bits.uop.br_type
connect slots_3.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[3].wakeup_ports[1].bits.uop.br_tag
connect slots_3.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[3].wakeup_ports[1].bits.uop.br_mask
connect slots_3.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[3].wakeup_ports[1].bits.uop.dis_col_sel
connect slots_3.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[3].wakeup_ports[1].bits.uop.iw_p3_bypass_hint
connect slots_3.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[3].wakeup_ports[1].bits.uop.iw_p2_bypass_hint
connect slots_3.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[3].wakeup_ports[1].bits.uop.iw_p1_bypass_hint
connect slots_3.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[3].wakeup_ports[1].bits.uop.iw_p2_speculative_child
connect slots_3.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[3].wakeup_ports[1].bits.uop.iw_p1_speculative_child
connect slots_3.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[3].wakeup_ports[1].bits.uop.iw_issued_partial_dgen
connect slots_3.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[3].wakeup_ports[1].bits.uop.iw_issued_partial_agen
connect slots_3.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[3].wakeup_ports[1].bits.uop.iw_issued
connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[0]
connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[1]
connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[2]
connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[3]
connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[4]
connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[5]
connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[6]
connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[7]
connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[8]
connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[9]
connect slots_3.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[3].wakeup_ports[1].bits.uop.iq_type[0]
connect slots_3.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[3].wakeup_ports[1].bits.uop.iq_type[1]
connect slots_3.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[3].wakeup_ports[1].bits.uop.iq_type[2]
connect slots_3.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[3].wakeup_ports[1].bits.uop.iq_type[3]
connect slots_3.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[3].wakeup_ports[1].bits.uop.debug_pc
connect slots_3.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[3].wakeup_ports[1].bits.uop.is_rvc
connect slots_3.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[3].wakeup_ports[1].bits.uop.debug_inst
connect slots_3.io.wakeup_ports[1].bits.uop.inst, issue_slots[3].wakeup_ports[1].bits.uop.inst
connect slots_3.io.wakeup_ports[1].valid, issue_slots[3].wakeup_ports[1].valid
connect slots_3.io.wakeup_ports[2].bits.rebusy, issue_slots[3].wakeup_ports[2].bits.rebusy
connect slots_3.io.wakeup_ports[2].bits.speculative_mask, issue_slots[3].wakeup_ports[2].bits.speculative_mask
connect slots_3.io.wakeup_ports[2].bits.bypassable, issue_slots[3].wakeup_ports[2].bits.bypassable
connect slots_3.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[3].wakeup_ports[2].bits.uop.debug_tsrc
connect slots_3.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[3].wakeup_ports[2].bits.uop.debug_fsrc
connect slots_3.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[3].wakeup_ports[2].bits.uop.bp_xcpt_if
connect slots_3.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[3].wakeup_ports[2].bits.uop.bp_debug_if
connect slots_3.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[3].wakeup_ports[2].bits.uop.xcpt_ma_if
connect slots_3.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[3].wakeup_ports[2].bits.uop.xcpt_ae_if
connect slots_3.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[3].wakeup_ports[2].bits.uop.xcpt_pf_if
connect slots_3.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[3].wakeup_ports[2].bits.uop.fp_typ
connect slots_3.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[3].wakeup_ports[2].bits.uop.fp_rm
connect slots_3.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[3].wakeup_ports[2].bits.uop.fp_val
connect slots_3.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[3].wakeup_ports[2].bits.uop.fcn_op
connect slots_3.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[3].wakeup_ports[2].bits.uop.fcn_dw
connect slots_3.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[3].wakeup_ports[2].bits.uop.frs3_en
connect slots_3.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[3].wakeup_ports[2].bits.uop.lrs2_rtype
connect slots_3.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[3].wakeup_ports[2].bits.uop.lrs1_rtype
connect slots_3.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[3].wakeup_ports[2].bits.uop.dst_rtype
connect slots_3.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[3].wakeup_ports[2].bits.uop.lrs3
connect slots_3.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[3].wakeup_ports[2].bits.uop.lrs2
connect slots_3.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[3].wakeup_ports[2].bits.uop.lrs1
connect slots_3.io.wakeup_ports[2].bits.uop.ldst, issue_slots[3].wakeup_ports[2].bits.uop.ldst
connect slots_3.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[3].wakeup_ports[2].bits.uop.ldst_is_rs1
connect slots_3.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[3].wakeup_ports[2].bits.uop.csr_cmd
connect slots_3.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[3].wakeup_ports[2].bits.uop.flush_on_commit
connect slots_3.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[3].wakeup_ports[2].bits.uop.is_unique
connect slots_3.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[3].wakeup_ports[2].bits.uop.uses_stq
connect slots_3.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[3].wakeup_ports[2].bits.uop.uses_ldq
connect slots_3.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[3].wakeup_ports[2].bits.uop.mem_signed
connect slots_3.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[3].wakeup_ports[2].bits.uop.mem_size
connect slots_3.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[3].wakeup_ports[2].bits.uop.mem_cmd
connect slots_3.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[3].wakeup_ports[2].bits.uop.exc_cause
connect slots_3.io.wakeup_ports[2].bits.uop.exception, issue_slots[3].wakeup_ports[2].bits.uop.exception
connect slots_3.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[3].wakeup_ports[2].bits.uop.stale_pdst
connect slots_3.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[3].wakeup_ports[2].bits.uop.ppred_busy
connect slots_3.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[3].wakeup_ports[2].bits.uop.prs3_busy
connect slots_3.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[3].wakeup_ports[2].bits.uop.prs2_busy
connect slots_3.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[3].wakeup_ports[2].bits.uop.prs1_busy
connect slots_3.io.wakeup_ports[2].bits.uop.ppred, issue_slots[3].wakeup_ports[2].bits.uop.ppred
connect slots_3.io.wakeup_ports[2].bits.uop.prs3, issue_slots[3].wakeup_ports[2].bits.uop.prs3
connect slots_3.io.wakeup_ports[2].bits.uop.prs2, issue_slots[3].wakeup_ports[2].bits.uop.prs2
connect slots_3.io.wakeup_ports[2].bits.uop.prs1, issue_slots[3].wakeup_ports[2].bits.uop.prs1
connect slots_3.io.wakeup_ports[2].bits.uop.pdst, issue_slots[3].wakeup_ports[2].bits.uop.pdst
connect slots_3.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[3].wakeup_ports[2].bits.uop.rxq_idx
connect slots_3.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[3].wakeup_ports[2].bits.uop.stq_idx
connect slots_3.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[3].wakeup_ports[2].bits.uop.ldq_idx
connect slots_3.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[3].wakeup_ports[2].bits.uop.rob_idx
connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.vec
connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.wflags
connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.sqrt
connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.div
connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.fma
connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe
connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.toint
connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.fromint
connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut
connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn
connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.swap23
connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.swap12
connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.ren3
connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.ren2
connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.ren1
connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.wen
connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.ldst
connect slots_3.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[3].wakeup_ports[2].bits.uop.op2_sel
connect slots_3.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[3].wakeup_ports[2].bits.uop.op1_sel
connect slots_3.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[3].wakeup_ports[2].bits.uop.imm_packed
connect slots_3.io.wakeup_ports[2].bits.uop.pimm, issue_slots[3].wakeup_ports[2].bits.uop.pimm
connect slots_3.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[3].wakeup_ports[2].bits.uop.imm_sel
connect slots_3.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[3].wakeup_ports[2].bits.uop.imm_rename
connect slots_3.io.wakeup_ports[2].bits.uop.taken, issue_slots[3].wakeup_ports[2].bits.uop.taken
connect slots_3.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[3].wakeup_ports[2].bits.uop.pc_lob
connect slots_3.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[3].wakeup_ports[2].bits.uop.edge_inst
connect slots_3.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[3].wakeup_ports[2].bits.uop.ftq_idx
connect slots_3.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[3].wakeup_ports[2].bits.uop.is_mov
connect slots_3.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[3].wakeup_ports[2].bits.uop.is_rocc
connect slots_3.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[3].wakeup_ports[2].bits.uop.is_sys_pc2epc
connect slots_3.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[3].wakeup_ports[2].bits.uop.is_eret
connect slots_3.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[3].wakeup_ports[2].bits.uop.is_amo
connect slots_3.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[3].wakeup_ports[2].bits.uop.is_sfence
connect slots_3.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[3].wakeup_ports[2].bits.uop.is_fencei
connect slots_3.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[3].wakeup_ports[2].bits.uop.is_fence
connect slots_3.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[3].wakeup_ports[2].bits.uop.is_sfb
connect slots_3.io.wakeup_ports[2].bits.uop.br_type, issue_slots[3].wakeup_ports[2].bits.uop.br_type
connect slots_3.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[3].wakeup_ports[2].bits.uop.br_tag
connect slots_3.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[3].wakeup_ports[2].bits.uop.br_mask
connect slots_3.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[3].wakeup_ports[2].bits.uop.dis_col_sel
connect slots_3.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[3].wakeup_ports[2].bits.uop.iw_p3_bypass_hint
connect slots_3.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[3].wakeup_ports[2].bits.uop.iw_p2_bypass_hint
connect slots_3.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[3].wakeup_ports[2].bits.uop.iw_p1_bypass_hint
connect slots_3.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[3].wakeup_ports[2].bits.uop.iw_p2_speculative_child
connect slots_3.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[3].wakeup_ports[2].bits.uop.iw_p1_speculative_child
connect slots_3.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[3].wakeup_ports[2].bits.uop.iw_issued_partial_dgen
connect slots_3.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[3].wakeup_ports[2].bits.uop.iw_issued_partial_agen
connect slots_3.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[3].wakeup_ports[2].bits.uop.iw_issued
connect slots_3.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[3].wakeup_ports[2].bits.uop.fu_code[0]
connect slots_3.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[3].wakeup_ports[2].bits.uop.fu_code[1]
connect slots_3.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[3].wakeup_ports[2].bits.uop.fu_code[2]
connect slots_3.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[3].wakeup_ports[2].bits.uop.fu_code[3]
connect slots_3.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[3].wakeup_ports[2].bits.uop.fu_code[4]
connect slots_3.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[3].wakeup_ports[2].bits.uop.fu_code[5]
connect slots_3.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[3].wakeup_ports[2].bits.uop.fu_code[6]
connect slots_3.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[3].wakeup_ports[2].bits.uop.fu_code[7]
connect slots_3.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[3].wakeup_ports[2].bits.uop.fu_code[8]
connect slots_3.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[3].wakeup_ports[2].bits.uop.fu_code[9]
connect slots_3.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[3].wakeup_ports[2].bits.uop.iq_type[0]
connect slots_3.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[3].wakeup_ports[2].bits.uop.iq_type[1]
connect slots_3.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[3].wakeup_ports[2].bits.uop.iq_type[2]
connect slots_3.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[3].wakeup_ports[2].bits.uop.iq_type[3]
connect slots_3.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[3].wakeup_ports[2].bits.uop.debug_pc
connect slots_3.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[3].wakeup_ports[2].bits.uop.is_rvc
connect slots_3.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[3].wakeup_ports[2].bits.uop.debug_inst
connect slots_3.io.wakeup_ports[2].bits.uop.inst, issue_slots[3].wakeup_ports[2].bits.uop.inst
connect slots_3.io.wakeup_ports[2].valid, issue_slots[3].wakeup_ports[2].valid
connect slots_3.io.wakeup_ports[3].bits.rebusy, issue_slots[3].wakeup_ports[3].bits.rebusy
connect slots_3.io.wakeup_ports[3].bits.speculative_mask, issue_slots[3].wakeup_ports[3].bits.speculative_mask
connect slots_3.io.wakeup_ports[3].bits.bypassable, issue_slots[3].wakeup_ports[3].bits.bypassable
connect slots_3.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[3].wakeup_ports[3].bits.uop.debug_tsrc
connect slots_3.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[3].wakeup_ports[3].bits.uop.debug_fsrc
connect slots_3.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[3].wakeup_ports[3].bits.uop.bp_xcpt_if
connect slots_3.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[3].wakeup_ports[3].bits.uop.bp_debug_if
connect slots_3.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[3].wakeup_ports[3].bits.uop.xcpt_ma_if
connect slots_3.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[3].wakeup_ports[3].bits.uop.xcpt_ae_if
connect slots_3.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[3].wakeup_ports[3].bits.uop.xcpt_pf_if
connect slots_3.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[3].wakeup_ports[3].bits.uop.fp_typ
connect slots_3.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[3].wakeup_ports[3].bits.uop.fp_rm
connect slots_3.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[3].wakeup_ports[3].bits.uop.fp_val
connect slots_3.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[3].wakeup_ports[3].bits.uop.fcn_op
connect slots_3.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[3].wakeup_ports[3].bits.uop.fcn_dw
connect slots_3.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[3].wakeup_ports[3].bits.uop.frs3_en
connect slots_3.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[3].wakeup_ports[3].bits.uop.lrs2_rtype
connect slots_3.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[3].wakeup_ports[3].bits.uop.lrs1_rtype
connect slots_3.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[3].wakeup_ports[3].bits.uop.dst_rtype
connect slots_3.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[3].wakeup_ports[3].bits.uop.lrs3
connect slots_3.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[3].wakeup_ports[3].bits.uop.lrs2
connect slots_3.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[3].wakeup_ports[3].bits.uop.lrs1
connect slots_3.io.wakeup_ports[3].bits.uop.ldst, issue_slots[3].wakeup_ports[3].bits.uop.ldst
connect slots_3.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[3].wakeup_ports[3].bits.uop.ldst_is_rs1
connect slots_3.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[3].wakeup_ports[3].bits.uop.csr_cmd
connect slots_3.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[3].wakeup_ports[3].bits.uop.flush_on_commit
connect slots_3.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[3].wakeup_ports[3].bits.uop.is_unique
connect slots_3.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[3].wakeup_ports[3].bits.uop.uses_stq
connect slots_3.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[3].wakeup_ports[3].bits.uop.uses_ldq
connect slots_3.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[3].wakeup_ports[3].bits.uop.mem_signed
connect slots_3.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[3].wakeup_ports[3].bits.uop.mem_size
connect slots_3.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[3].wakeup_ports[3].bits.uop.mem_cmd
connect slots_3.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[3].wakeup_ports[3].bits.uop.exc_cause
connect slots_3.io.wakeup_ports[3].bits.uop.exception, issue_slots[3].wakeup_ports[3].bits.uop.exception
connect slots_3.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[3].wakeup_ports[3].bits.uop.stale_pdst
connect slots_3.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[3].wakeup_ports[3].bits.uop.ppred_busy
connect slots_3.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[3].wakeup_ports[3].bits.uop.prs3_busy
connect slots_3.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[3].wakeup_ports[3].bits.uop.prs2_busy
connect slots_3.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[3].wakeup_ports[3].bits.uop.prs1_busy
connect slots_3.io.wakeup_ports[3].bits.uop.ppred, issue_slots[3].wakeup_ports[3].bits.uop.ppred
connect slots_3.io.wakeup_ports[3].bits.uop.prs3, issue_slots[3].wakeup_ports[3].bits.uop.prs3
connect slots_3.io.wakeup_ports[3].bits.uop.prs2, issue_slots[3].wakeup_ports[3].bits.uop.prs2
connect slots_3.io.wakeup_ports[3].bits.uop.prs1, issue_slots[3].wakeup_ports[3].bits.uop.prs1
connect slots_3.io.wakeup_ports[3].bits.uop.pdst, issue_slots[3].wakeup_ports[3].bits.uop.pdst
connect slots_3.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[3].wakeup_ports[3].bits.uop.rxq_idx
connect slots_3.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[3].wakeup_ports[3].bits.uop.stq_idx
connect slots_3.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[3].wakeup_ports[3].bits.uop.ldq_idx
connect slots_3.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[3].wakeup_ports[3].bits.uop.rob_idx
connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.vec
connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.wflags
connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.sqrt
connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.div
connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.fma
connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe
connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.toint
connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.fromint
connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut
connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn
connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.swap23
connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.swap12
connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.ren3
connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.ren2
connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.ren1
connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.wen
connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.ldst
connect slots_3.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[3].wakeup_ports[3].bits.uop.op2_sel
connect slots_3.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[3].wakeup_ports[3].bits.uop.op1_sel
connect slots_3.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[3].wakeup_ports[3].bits.uop.imm_packed
connect slots_3.io.wakeup_ports[3].bits.uop.pimm, issue_slots[3].wakeup_ports[3].bits.uop.pimm
connect slots_3.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[3].wakeup_ports[3].bits.uop.imm_sel
connect slots_3.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[3].wakeup_ports[3].bits.uop.imm_rename
connect slots_3.io.wakeup_ports[3].bits.uop.taken, issue_slots[3].wakeup_ports[3].bits.uop.taken
connect slots_3.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[3].wakeup_ports[3].bits.uop.pc_lob
connect slots_3.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[3].wakeup_ports[3].bits.uop.edge_inst
connect slots_3.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[3].wakeup_ports[3].bits.uop.ftq_idx
connect slots_3.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[3].wakeup_ports[3].bits.uop.is_mov
connect slots_3.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[3].wakeup_ports[3].bits.uop.is_rocc
connect slots_3.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[3].wakeup_ports[3].bits.uop.is_sys_pc2epc
connect slots_3.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[3].wakeup_ports[3].bits.uop.is_eret
connect slots_3.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[3].wakeup_ports[3].bits.uop.is_amo
connect slots_3.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[3].wakeup_ports[3].bits.uop.is_sfence
connect slots_3.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[3].wakeup_ports[3].bits.uop.is_fencei
connect slots_3.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[3].wakeup_ports[3].bits.uop.is_fence
connect slots_3.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[3].wakeup_ports[3].bits.uop.is_sfb
connect slots_3.io.wakeup_ports[3].bits.uop.br_type, issue_slots[3].wakeup_ports[3].bits.uop.br_type
connect slots_3.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[3].wakeup_ports[3].bits.uop.br_tag
connect slots_3.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[3].wakeup_ports[3].bits.uop.br_mask
connect slots_3.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[3].wakeup_ports[3].bits.uop.dis_col_sel
connect slots_3.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[3].wakeup_ports[3].bits.uop.iw_p3_bypass_hint
connect slots_3.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[3].wakeup_ports[3].bits.uop.iw_p2_bypass_hint
connect slots_3.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[3].wakeup_ports[3].bits.uop.iw_p1_bypass_hint
connect slots_3.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[3].wakeup_ports[3].bits.uop.iw_p2_speculative_child
connect slots_3.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[3].wakeup_ports[3].bits.uop.iw_p1_speculative_child
connect slots_3.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[3].wakeup_ports[3].bits.uop.iw_issued_partial_dgen
connect slots_3.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[3].wakeup_ports[3].bits.uop.iw_issued_partial_agen
connect slots_3.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[3].wakeup_ports[3].bits.uop.iw_issued
connect slots_3.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[3].wakeup_ports[3].bits.uop.fu_code[0]
connect slots_3.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[3].wakeup_ports[3].bits.uop.fu_code[1]
connect slots_3.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[3].wakeup_ports[3].bits.uop.fu_code[2]
connect slots_3.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[3].wakeup_ports[3].bits.uop.fu_code[3]
connect slots_3.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[3].wakeup_ports[3].bits.uop.fu_code[4]
connect slots_3.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[3].wakeup_ports[3].bits.uop.fu_code[5]
connect slots_3.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[3].wakeup_ports[3].bits.uop.fu_code[6]
connect slots_3.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[3].wakeup_ports[3].bits.uop.fu_code[7]
connect slots_3.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[3].wakeup_ports[3].bits.uop.fu_code[8]
connect slots_3.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[3].wakeup_ports[3].bits.uop.fu_code[9]
connect slots_3.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[3].wakeup_ports[3].bits.uop.iq_type[0]
connect slots_3.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[3].wakeup_ports[3].bits.uop.iq_type[1]
connect slots_3.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[3].wakeup_ports[3].bits.uop.iq_type[2]
connect slots_3.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[3].wakeup_ports[3].bits.uop.iq_type[3]
connect slots_3.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[3].wakeup_ports[3].bits.uop.debug_pc
connect slots_3.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[3].wakeup_ports[3].bits.uop.is_rvc
connect slots_3.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[3].wakeup_ports[3].bits.uop.debug_inst
connect slots_3.io.wakeup_ports[3].bits.uop.inst, issue_slots[3].wakeup_ports[3].bits.uop.inst
connect slots_3.io.wakeup_ports[3].valid, issue_slots[3].wakeup_ports[3].valid
connect slots_3.io.squash_grant, issue_slots[3].squash_grant
connect slots_3.io.clear, issue_slots[3].clear
connect slots_3.io.kill, issue_slots[3].kill
connect slots_3.io.brupdate.b2.target_offset, issue_slots[3].brupdate.b2.target_offset
connect slots_3.io.brupdate.b2.jalr_target, issue_slots[3].brupdate.b2.jalr_target
connect slots_3.io.brupdate.b2.pc_sel, issue_slots[3].brupdate.b2.pc_sel
connect slots_3.io.brupdate.b2.cfi_type, issue_slots[3].brupdate.b2.cfi_type
connect slots_3.io.brupdate.b2.taken, issue_slots[3].brupdate.b2.taken
connect slots_3.io.brupdate.b2.mispredict, issue_slots[3].brupdate.b2.mispredict
connect slots_3.io.brupdate.b2.uop.debug_tsrc, issue_slots[3].brupdate.b2.uop.debug_tsrc
connect slots_3.io.brupdate.b2.uop.debug_fsrc, issue_slots[3].brupdate.b2.uop.debug_fsrc
connect slots_3.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[3].brupdate.b2.uop.bp_xcpt_if
connect slots_3.io.brupdate.b2.uop.bp_debug_if, issue_slots[3].brupdate.b2.uop.bp_debug_if
connect slots_3.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[3].brupdate.b2.uop.xcpt_ma_if
connect slots_3.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[3].brupdate.b2.uop.xcpt_ae_if
connect slots_3.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[3].brupdate.b2.uop.xcpt_pf_if
connect slots_3.io.brupdate.b2.uop.fp_typ, issue_slots[3].brupdate.b2.uop.fp_typ
connect slots_3.io.brupdate.b2.uop.fp_rm, issue_slots[3].brupdate.b2.uop.fp_rm
connect slots_3.io.brupdate.b2.uop.fp_val, issue_slots[3].brupdate.b2.uop.fp_val
connect slots_3.io.brupdate.b2.uop.fcn_op, issue_slots[3].brupdate.b2.uop.fcn_op
connect slots_3.io.brupdate.b2.uop.fcn_dw, issue_slots[3].brupdate.b2.uop.fcn_dw
connect slots_3.io.brupdate.b2.uop.frs3_en, issue_slots[3].brupdate.b2.uop.frs3_en
connect slots_3.io.brupdate.b2.uop.lrs2_rtype, issue_slots[3].brupdate.b2.uop.lrs2_rtype
connect slots_3.io.brupdate.b2.uop.lrs1_rtype, issue_slots[3].brupdate.b2.uop.lrs1_rtype
connect slots_3.io.brupdate.b2.uop.dst_rtype, issue_slots[3].brupdate.b2.uop.dst_rtype
connect slots_3.io.brupdate.b2.uop.lrs3, issue_slots[3].brupdate.b2.uop.lrs3
connect slots_3.io.brupdate.b2.uop.lrs2, issue_slots[3].brupdate.b2.uop.lrs2
connect slots_3.io.brupdate.b2.uop.lrs1, issue_slots[3].brupdate.b2.uop.lrs1
connect slots_3.io.brupdate.b2.uop.ldst, issue_slots[3].brupdate.b2.uop.ldst
connect slots_3.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[3].brupdate.b2.uop.ldst_is_rs1
connect slots_3.io.brupdate.b2.uop.csr_cmd, issue_slots[3].brupdate.b2.uop.csr_cmd
connect slots_3.io.brupdate.b2.uop.flush_on_commit, issue_slots[3].brupdate.b2.uop.flush_on_commit
connect slots_3.io.brupdate.b2.uop.is_unique, issue_slots[3].brupdate.b2.uop.is_unique
connect slots_3.io.brupdate.b2.uop.uses_stq, issue_slots[3].brupdate.b2.uop.uses_stq
connect slots_3.io.brupdate.b2.uop.uses_ldq, issue_slots[3].brupdate.b2.uop.uses_ldq
connect slots_3.io.brupdate.b2.uop.mem_signed, issue_slots[3].brupdate.b2.uop.mem_signed
connect slots_3.io.brupdate.b2.uop.mem_size, issue_slots[3].brupdate.b2.uop.mem_size
connect slots_3.io.brupdate.b2.uop.mem_cmd, issue_slots[3].brupdate.b2.uop.mem_cmd
connect slots_3.io.brupdate.b2.uop.exc_cause, issue_slots[3].brupdate.b2.uop.exc_cause
connect slots_3.io.brupdate.b2.uop.exception, issue_slots[3].brupdate.b2.uop.exception
connect slots_3.io.brupdate.b2.uop.stale_pdst, issue_slots[3].brupdate.b2.uop.stale_pdst
connect slots_3.io.brupdate.b2.uop.ppred_busy, issue_slots[3].brupdate.b2.uop.ppred_busy
connect slots_3.io.brupdate.b2.uop.prs3_busy, issue_slots[3].brupdate.b2.uop.prs3_busy
connect slots_3.io.brupdate.b2.uop.prs2_busy, issue_slots[3].brupdate.b2.uop.prs2_busy
connect slots_3.io.brupdate.b2.uop.prs1_busy, issue_slots[3].brupdate.b2.uop.prs1_busy
connect slots_3.io.brupdate.b2.uop.ppred, issue_slots[3].brupdate.b2.uop.ppred
connect slots_3.io.brupdate.b2.uop.prs3, issue_slots[3].brupdate.b2.uop.prs3
connect slots_3.io.brupdate.b2.uop.prs2, issue_slots[3].brupdate.b2.uop.prs2
connect slots_3.io.brupdate.b2.uop.prs1, issue_slots[3].brupdate.b2.uop.prs1
connect slots_3.io.brupdate.b2.uop.pdst, issue_slots[3].brupdate.b2.uop.pdst
connect slots_3.io.brupdate.b2.uop.rxq_idx, issue_slots[3].brupdate.b2.uop.rxq_idx
connect slots_3.io.brupdate.b2.uop.stq_idx, issue_slots[3].brupdate.b2.uop.stq_idx
connect slots_3.io.brupdate.b2.uop.ldq_idx, issue_slots[3].brupdate.b2.uop.ldq_idx
connect slots_3.io.brupdate.b2.uop.rob_idx, issue_slots[3].brupdate.b2.uop.rob_idx
connect slots_3.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[3].brupdate.b2.uop.fp_ctrl.vec
connect slots_3.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[3].brupdate.b2.uop.fp_ctrl.wflags
connect slots_3.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[3].brupdate.b2.uop.fp_ctrl.sqrt
connect slots_3.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[3].brupdate.b2.uop.fp_ctrl.div
connect slots_3.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[3].brupdate.b2.uop.fp_ctrl.fma
connect slots_3.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[3].brupdate.b2.uop.fp_ctrl.fastpipe
connect slots_3.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[3].brupdate.b2.uop.fp_ctrl.toint
connect slots_3.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[3].brupdate.b2.uop.fp_ctrl.fromint
connect slots_3.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[3].brupdate.b2.uop.fp_ctrl.typeTagOut
connect slots_3.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[3].brupdate.b2.uop.fp_ctrl.typeTagIn
connect slots_3.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[3].brupdate.b2.uop.fp_ctrl.swap23
connect slots_3.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[3].brupdate.b2.uop.fp_ctrl.swap12
connect slots_3.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[3].brupdate.b2.uop.fp_ctrl.ren3
connect slots_3.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[3].brupdate.b2.uop.fp_ctrl.ren2
connect slots_3.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[3].brupdate.b2.uop.fp_ctrl.ren1
connect slots_3.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[3].brupdate.b2.uop.fp_ctrl.wen
connect slots_3.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[3].brupdate.b2.uop.fp_ctrl.ldst
connect slots_3.io.brupdate.b2.uop.op2_sel, issue_slots[3].brupdate.b2.uop.op2_sel
connect slots_3.io.brupdate.b2.uop.op1_sel, issue_slots[3].brupdate.b2.uop.op1_sel
connect slots_3.io.brupdate.b2.uop.imm_packed, issue_slots[3].brupdate.b2.uop.imm_packed
connect slots_3.io.brupdate.b2.uop.pimm, issue_slots[3].brupdate.b2.uop.pimm
connect slots_3.io.brupdate.b2.uop.imm_sel, issue_slots[3].brupdate.b2.uop.imm_sel
connect slots_3.io.brupdate.b2.uop.imm_rename, issue_slots[3].brupdate.b2.uop.imm_rename
connect slots_3.io.brupdate.b2.uop.taken, issue_slots[3].brupdate.b2.uop.taken
connect slots_3.io.brupdate.b2.uop.pc_lob, issue_slots[3].brupdate.b2.uop.pc_lob
connect slots_3.io.brupdate.b2.uop.edge_inst, issue_slots[3].brupdate.b2.uop.edge_inst
connect slots_3.io.brupdate.b2.uop.ftq_idx, issue_slots[3].brupdate.b2.uop.ftq_idx
connect slots_3.io.brupdate.b2.uop.is_mov, issue_slots[3].brupdate.b2.uop.is_mov
connect slots_3.io.brupdate.b2.uop.is_rocc, issue_slots[3].brupdate.b2.uop.is_rocc
connect slots_3.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[3].brupdate.b2.uop.is_sys_pc2epc
connect slots_3.io.brupdate.b2.uop.is_eret, issue_slots[3].brupdate.b2.uop.is_eret
connect slots_3.io.brupdate.b2.uop.is_amo, issue_slots[3].brupdate.b2.uop.is_amo
connect slots_3.io.brupdate.b2.uop.is_sfence, issue_slots[3].brupdate.b2.uop.is_sfence
connect slots_3.io.brupdate.b2.uop.is_fencei, issue_slots[3].brupdate.b2.uop.is_fencei
connect slots_3.io.brupdate.b2.uop.is_fence, issue_slots[3].brupdate.b2.uop.is_fence
connect slots_3.io.brupdate.b2.uop.is_sfb, issue_slots[3].brupdate.b2.uop.is_sfb
connect slots_3.io.brupdate.b2.uop.br_type, issue_slots[3].brupdate.b2.uop.br_type
connect slots_3.io.brupdate.b2.uop.br_tag, issue_slots[3].brupdate.b2.uop.br_tag
connect slots_3.io.brupdate.b2.uop.br_mask, issue_slots[3].brupdate.b2.uop.br_mask
connect slots_3.io.brupdate.b2.uop.dis_col_sel, issue_slots[3].brupdate.b2.uop.dis_col_sel
connect slots_3.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[3].brupdate.b2.uop.iw_p3_bypass_hint
connect slots_3.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[3].brupdate.b2.uop.iw_p2_bypass_hint
connect slots_3.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[3].brupdate.b2.uop.iw_p1_bypass_hint
connect slots_3.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[3].brupdate.b2.uop.iw_p2_speculative_child
connect slots_3.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[3].brupdate.b2.uop.iw_p1_speculative_child
connect slots_3.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[3].brupdate.b2.uop.iw_issued_partial_dgen
connect slots_3.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[3].brupdate.b2.uop.iw_issued_partial_agen
connect slots_3.io.brupdate.b2.uop.iw_issued, issue_slots[3].brupdate.b2.uop.iw_issued
connect slots_3.io.brupdate.b2.uop.fu_code[0], issue_slots[3].brupdate.b2.uop.fu_code[0]
connect slots_3.io.brupdate.b2.uop.fu_code[1], issue_slots[3].brupdate.b2.uop.fu_code[1]
connect slots_3.io.brupdate.b2.uop.fu_code[2], issue_slots[3].brupdate.b2.uop.fu_code[2]
connect slots_3.io.brupdate.b2.uop.fu_code[3], issue_slots[3].brupdate.b2.uop.fu_code[3]
connect slots_3.io.brupdate.b2.uop.fu_code[4], issue_slots[3].brupdate.b2.uop.fu_code[4]
connect slots_3.io.brupdate.b2.uop.fu_code[5], issue_slots[3].brupdate.b2.uop.fu_code[5]
connect slots_3.io.brupdate.b2.uop.fu_code[6], issue_slots[3].brupdate.b2.uop.fu_code[6]
connect slots_3.io.brupdate.b2.uop.fu_code[7], issue_slots[3].brupdate.b2.uop.fu_code[7]
connect slots_3.io.brupdate.b2.uop.fu_code[8], issue_slots[3].brupdate.b2.uop.fu_code[8]
connect slots_3.io.brupdate.b2.uop.fu_code[9], issue_slots[3].brupdate.b2.uop.fu_code[9]
connect slots_3.io.brupdate.b2.uop.iq_type[0], issue_slots[3].brupdate.b2.uop.iq_type[0]
connect slots_3.io.brupdate.b2.uop.iq_type[1], issue_slots[3].brupdate.b2.uop.iq_type[1]
connect slots_3.io.brupdate.b2.uop.iq_type[2], issue_slots[3].brupdate.b2.uop.iq_type[2]
connect slots_3.io.brupdate.b2.uop.iq_type[3], issue_slots[3].brupdate.b2.uop.iq_type[3]
connect slots_3.io.brupdate.b2.uop.debug_pc, issue_slots[3].brupdate.b2.uop.debug_pc
connect slots_3.io.brupdate.b2.uop.is_rvc, issue_slots[3].brupdate.b2.uop.is_rvc
connect slots_3.io.brupdate.b2.uop.debug_inst, issue_slots[3].brupdate.b2.uop.debug_inst
connect slots_3.io.brupdate.b2.uop.inst, issue_slots[3].brupdate.b2.uop.inst
connect slots_3.io.brupdate.b1.mispredict_mask, issue_slots[3].brupdate.b1.mispredict_mask
connect slots_3.io.brupdate.b1.resolve_mask, issue_slots[3].brupdate.b1.resolve_mask
connect issue_slots[3].out_uop.debug_tsrc, slots_3.io.out_uop.debug_tsrc
connect issue_slots[3].out_uop.debug_fsrc, slots_3.io.out_uop.debug_fsrc
connect issue_slots[3].out_uop.bp_xcpt_if, slots_3.io.out_uop.bp_xcpt_if
connect issue_slots[3].out_uop.bp_debug_if, slots_3.io.out_uop.bp_debug_if
connect issue_slots[3].out_uop.xcpt_ma_if, slots_3.io.out_uop.xcpt_ma_if
connect issue_slots[3].out_uop.xcpt_ae_if, slots_3.io.out_uop.xcpt_ae_if
connect issue_slots[3].out_uop.xcpt_pf_if, slots_3.io.out_uop.xcpt_pf_if
connect issue_slots[3].out_uop.fp_typ, slots_3.io.out_uop.fp_typ
connect issue_slots[3].out_uop.fp_rm, slots_3.io.out_uop.fp_rm
connect issue_slots[3].out_uop.fp_val, slots_3.io.out_uop.fp_val
connect issue_slots[3].out_uop.fcn_op, slots_3.io.out_uop.fcn_op
connect issue_slots[3].out_uop.fcn_dw, slots_3.io.out_uop.fcn_dw
connect issue_slots[3].out_uop.frs3_en, slots_3.io.out_uop.frs3_en
connect issue_slots[3].out_uop.lrs2_rtype, slots_3.io.out_uop.lrs2_rtype
connect issue_slots[3].out_uop.lrs1_rtype, slots_3.io.out_uop.lrs1_rtype
connect issue_slots[3].out_uop.dst_rtype, slots_3.io.out_uop.dst_rtype
connect issue_slots[3].out_uop.lrs3, slots_3.io.out_uop.lrs3
connect issue_slots[3].out_uop.lrs2, slots_3.io.out_uop.lrs2
connect issue_slots[3].out_uop.lrs1, slots_3.io.out_uop.lrs1
connect issue_slots[3].out_uop.ldst, slots_3.io.out_uop.ldst
connect issue_slots[3].out_uop.ldst_is_rs1, slots_3.io.out_uop.ldst_is_rs1
connect issue_slots[3].out_uop.csr_cmd, slots_3.io.out_uop.csr_cmd
connect issue_slots[3].out_uop.flush_on_commit, slots_3.io.out_uop.flush_on_commit
connect issue_slots[3].out_uop.is_unique, slots_3.io.out_uop.is_unique
connect issue_slots[3].out_uop.uses_stq, slots_3.io.out_uop.uses_stq
connect issue_slots[3].out_uop.uses_ldq, slots_3.io.out_uop.uses_ldq
connect issue_slots[3].out_uop.mem_signed, slots_3.io.out_uop.mem_signed
connect issue_slots[3].out_uop.mem_size, slots_3.io.out_uop.mem_size
connect issue_slots[3].out_uop.mem_cmd, slots_3.io.out_uop.mem_cmd
connect issue_slots[3].out_uop.exc_cause, slots_3.io.out_uop.exc_cause
connect issue_slots[3].out_uop.exception, slots_3.io.out_uop.exception
connect issue_slots[3].out_uop.stale_pdst, slots_3.io.out_uop.stale_pdst
connect issue_slots[3].out_uop.ppred_busy, slots_3.io.out_uop.ppred_busy
connect issue_slots[3].out_uop.prs3_busy, slots_3.io.out_uop.prs3_busy
connect issue_slots[3].out_uop.prs2_busy, slots_3.io.out_uop.prs2_busy
connect issue_slots[3].out_uop.prs1_busy, slots_3.io.out_uop.prs1_busy
connect issue_slots[3].out_uop.ppred, slots_3.io.out_uop.ppred
connect issue_slots[3].out_uop.prs3, slots_3.io.out_uop.prs3
connect issue_slots[3].out_uop.prs2, slots_3.io.out_uop.prs2
connect issue_slots[3].out_uop.prs1, slots_3.io.out_uop.prs1
connect issue_slots[3].out_uop.pdst, slots_3.io.out_uop.pdst
connect issue_slots[3].out_uop.rxq_idx, slots_3.io.out_uop.rxq_idx
connect issue_slots[3].out_uop.stq_idx, slots_3.io.out_uop.stq_idx
connect issue_slots[3].out_uop.ldq_idx, slots_3.io.out_uop.ldq_idx
connect issue_slots[3].out_uop.rob_idx, slots_3.io.out_uop.rob_idx
connect issue_slots[3].out_uop.fp_ctrl.vec, slots_3.io.out_uop.fp_ctrl.vec
connect issue_slots[3].out_uop.fp_ctrl.wflags, slots_3.io.out_uop.fp_ctrl.wflags
connect issue_slots[3].out_uop.fp_ctrl.sqrt, slots_3.io.out_uop.fp_ctrl.sqrt
connect issue_slots[3].out_uop.fp_ctrl.div, slots_3.io.out_uop.fp_ctrl.div
connect issue_slots[3].out_uop.fp_ctrl.fma, slots_3.io.out_uop.fp_ctrl.fma
connect issue_slots[3].out_uop.fp_ctrl.fastpipe, slots_3.io.out_uop.fp_ctrl.fastpipe
connect issue_slots[3].out_uop.fp_ctrl.toint, slots_3.io.out_uop.fp_ctrl.toint
connect issue_slots[3].out_uop.fp_ctrl.fromint, slots_3.io.out_uop.fp_ctrl.fromint
connect issue_slots[3].out_uop.fp_ctrl.typeTagOut, slots_3.io.out_uop.fp_ctrl.typeTagOut
connect issue_slots[3].out_uop.fp_ctrl.typeTagIn, slots_3.io.out_uop.fp_ctrl.typeTagIn
connect issue_slots[3].out_uop.fp_ctrl.swap23, slots_3.io.out_uop.fp_ctrl.swap23
connect issue_slots[3].out_uop.fp_ctrl.swap12, slots_3.io.out_uop.fp_ctrl.swap12
connect issue_slots[3].out_uop.fp_ctrl.ren3, slots_3.io.out_uop.fp_ctrl.ren3
connect issue_slots[3].out_uop.fp_ctrl.ren2, slots_3.io.out_uop.fp_ctrl.ren2
connect issue_slots[3].out_uop.fp_ctrl.ren1, slots_3.io.out_uop.fp_ctrl.ren1
connect issue_slots[3].out_uop.fp_ctrl.wen, slots_3.io.out_uop.fp_ctrl.wen
connect issue_slots[3].out_uop.fp_ctrl.ldst, slots_3.io.out_uop.fp_ctrl.ldst
connect issue_slots[3].out_uop.op2_sel, slots_3.io.out_uop.op2_sel
connect issue_slots[3].out_uop.op1_sel, slots_3.io.out_uop.op1_sel
connect issue_slots[3].out_uop.imm_packed, slots_3.io.out_uop.imm_packed
connect issue_slots[3].out_uop.pimm, slots_3.io.out_uop.pimm
connect issue_slots[3].out_uop.imm_sel, slots_3.io.out_uop.imm_sel
connect issue_slots[3].out_uop.imm_rename, slots_3.io.out_uop.imm_rename
connect issue_slots[3].out_uop.taken, slots_3.io.out_uop.taken
connect issue_slots[3].out_uop.pc_lob, slots_3.io.out_uop.pc_lob
connect issue_slots[3].out_uop.edge_inst, slots_3.io.out_uop.edge_inst
connect issue_slots[3].out_uop.ftq_idx, slots_3.io.out_uop.ftq_idx
connect issue_slots[3].out_uop.is_mov, slots_3.io.out_uop.is_mov
connect issue_slots[3].out_uop.is_rocc, slots_3.io.out_uop.is_rocc
connect issue_slots[3].out_uop.is_sys_pc2epc, slots_3.io.out_uop.is_sys_pc2epc
connect issue_slots[3].out_uop.is_eret, slots_3.io.out_uop.is_eret
connect issue_slots[3].out_uop.is_amo, slots_3.io.out_uop.is_amo
connect issue_slots[3].out_uop.is_sfence, slots_3.io.out_uop.is_sfence
connect issue_slots[3].out_uop.is_fencei, slots_3.io.out_uop.is_fencei
connect issue_slots[3].out_uop.is_fence, slots_3.io.out_uop.is_fence
connect issue_slots[3].out_uop.is_sfb, slots_3.io.out_uop.is_sfb
connect issue_slots[3].out_uop.br_type, slots_3.io.out_uop.br_type
connect issue_slots[3].out_uop.br_tag, slots_3.io.out_uop.br_tag
connect issue_slots[3].out_uop.br_mask, slots_3.io.out_uop.br_mask
connect issue_slots[3].out_uop.dis_col_sel, slots_3.io.out_uop.dis_col_sel
connect issue_slots[3].out_uop.iw_p3_bypass_hint, slots_3.io.out_uop.iw_p3_bypass_hint
connect issue_slots[3].out_uop.iw_p2_bypass_hint, slots_3.io.out_uop.iw_p2_bypass_hint
connect issue_slots[3].out_uop.iw_p1_bypass_hint, slots_3.io.out_uop.iw_p1_bypass_hint
connect issue_slots[3].out_uop.iw_p2_speculative_child, slots_3.io.out_uop.iw_p2_speculative_child
connect issue_slots[3].out_uop.iw_p1_speculative_child, slots_3.io.out_uop.iw_p1_speculative_child
connect issue_slots[3].out_uop.iw_issued_partial_dgen, slots_3.io.out_uop.iw_issued_partial_dgen
connect issue_slots[3].out_uop.iw_issued_partial_agen, slots_3.io.out_uop.iw_issued_partial_agen
connect issue_slots[3].out_uop.iw_issued, slots_3.io.out_uop.iw_issued
connect issue_slots[3].out_uop.fu_code[0], slots_3.io.out_uop.fu_code[0]
connect issue_slots[3].out_uop.fu_code[1], slots_3.io.out_uop.fu_code[1]
connect issue_slots[3].out_uop.fu_code[2], slots_3.io.out_uop.fu_code[2]
connect issue_slots[3].out_uop.fu_code[3], slots_3.io.out_uop.fu_code[3]
connect issue_slots[3].out_uop.fu_code[4], slots_3.io.out_uop.fu_code[4]
connect issue_slots[3].out_uop.fu_code[5], slots_3.io.out_uop.fu_code[5]
connect issue_slots[3].out_uop.fu_code[6], slots_3.io.out_uop.fu_code[6]
connect issue_slots[3].out_uop.fu_code[7], slots_3.io.out_uop.fu_code[7]
connect issue_slots[3].out_uop.fu_code[8], slots_3.io.out_uop.fu_code[8]
connect issue_slots[3].out_uop.fu_code[9], slots_3.io.out_uop.fu_code[9]
connect issue_slots[3].out_uop.iq_type[0], slots_3.io.out_uop.iq_type[0]
connect issue_slots[3].out_uop.iq_type[1], slots_3.io.out_uop.iq_type[1]
connect issue_slots[3].out_uop.iq_type[2], slots_3.io.out_uop.iq_type[2]
connect issue_slots[3].out_uop.iq_type[3], slots_3.io.out_uop.iq_type[3]
connect issue_slots[3].out_uop.debug_pc, slots_3.io.out_uop.debug_pc
connect issue_slots[3].out_uop.is_rvc, slots_3.io.out_uop.is_rvc
connect issue_slots[3].out_uop.debug_inst, slots_3.io.out_uop.debug_inst
connect issue_slots[3].out_uop.inst, slots_3.io.out_uop.inst
connect slots_3.io.in_uop.bits.debug_tsrc, issue_slots[3].in_uop.bits.debug_tsrc
connect slots_3.io.in_uop.bits.debug_fsrc, issue_slots[3].in_uop.bits.debug_fsrc
connect slots_3.io.in_uop.bits.bp_xcpt_if, issue_slots[3].in_uop.bits.bp_xcpt_if
connect slots_3.io.in_uop.bits.bp_debug_if, issue_slots[3].in_uop.bits.bp_debug_if
connect slots_3.io.in_uop.bits.xcpt_ma_if, issue_slots[3].in_uop.bits.xcpt_ma_if
connect slots_3.io.in_uop.bits.xcpt_ae_if, issue_slots[3].in_uop.bits.xcpt_ae_if
connect slots_3.io.in_uop.bits.xcpt_pf_if, issue_slots[3].in_uop.bits.xcpt_pf_if
connect slots_3.io.in_uop.bits.fp_typ, issue_slots[3].in_uop.bits.fp_typ
connect slots_3.io.in_uop.bits.fp_rm, issue_slots[3].in_uop.bits.fp_rm
connect slots_3.io.in_uop.bits.fp_val, issue_slots[3].in_uop.bits.fp_val
connect slots_3.io.in_uop.bits.fcn_op, issue_slots[3].in_uop.bits.fcn_op
connect slots_3.io.in_uop.bits.fcn_dw, issue_slots[3].in_uop.bits.fcn_dw
connect slots_3.io.in_uop.bits.frs3_en, issue_slots[3].in_uop.bits.frs3_en
connect slots_3.io.in_uop.bits.lrs2_rtype, issue_slots[3].in_uop.bits.lrs2_rtype
connect slots_3.io.in_uop.bits.lrs1_rtype, issue_slots[3].in_uop.bits.lrs1_rtype
connect slots_3.io.in_uop.bits.dst_rtype, issue_slots[3].in_uop.bits.dst_rtype
connect slots_3.io.in_uop.bits.lrs3, issue_slots[3].in_uop.bits.lrs3
connect slots_3.io.in_uop.bits.lrs2, issue_slots[3].in_uop.bits.lrs2
connect slots_3.io.in_uop.bits.lrs1, issue_slots[3].in_uop.bits.lrs1
connect slots_3.io.in_uop.bits.ldst, issue_slots[3].in_uop.bits.ldst
connect slots_3.io.in_uop.bits.ldst_is_rs1, issue_slots[3].in_uop.bits.ldst_is_rs1
connect slots_3.io.in_uop.bits.csr_cmd, issue_slots[3].in_uop.bits.csr_cmd
connect slots_3.io.in_uop.bits.flush_on_commit, issue_slots[3].in_uop.bits.flush_on_commit
connect slots_3.io.in_uop.bits.is_unique, issue_slots[3].in_uop.bits.is_unique
connect slots_3.io.in_uop.bits.uses_stq, issue_slots[3].in_uop.bits.uses_stq
connect slots_3.io.in_uop.bits.uses_ldq, issue_slots[3].in_uop.bits.uses_ldq
connect slots_3.io.in_uop.bits.mem_signed, issue_slots[3].in_uop.bits.mem_signed
connect slots_3.io.in_uop.bits.mem_size, issue_slots[3].in_uop.bits.mem_size
connect slots_3.io.in_uop.bits.mem_cmd, issue_slots[3].in_uop.bits.mem_cmd
connect slots_3.io.in_uop.bits.exc_cause, issue_slots[3].in_uop.bits.exc_cause
connect slots_3.io.in_uop.bits.exception, issue_slots[3].in_uop.bits.exception
connect slots_3.io.in_uop.bits.stale_pdst, issue_slots[3].in_uop.bits.stale_pdst
connect slots_3.io.in_uop.bits.ppred_busy, issue_slots[3].in_uop.bits.ppred_busy
connect slots_3.io.in_uop.bits.prs3_busy, issue_slots[3].in_uop.bits.prs3_busy
connect slots_3.io.in_uop.bits.prs2_busy, issue_slots[3].in_uop.bits.prs2_busy
connect slots_3.io.in_uop.bits.prs1_busy, issue_slots[3].in_uop.bits.prs1_busy
connect slots_3.io.in_uop.bits.ppred, issue_slots[3].in_uop.bits.ppred
connect slots_3.io.in_uop.bits.prs3, issue_slots[3].in_uop.bits.prs3
connect slots_3.io.in_uop.bits.prs2, issue_slots[3].in_uop.bits.prs2
connect slots_3.io.in_uop.bits.prs1, issue_slots[3].in_uop.bits.prs1
connect slots_3.io.in_uop.bits.pdst, issue_slots[3].in_uop.bits.pdst
connect slots_3.io.in_uop.bits.rxq_idx, issue_slots[3].in_uop.bits.rxq_idx
connect slots_3.io.in_uop.bits.stq_idx, issue_slots[3].in_uop.bits.stq_idx
connect slots_3.io.in_uop.bits.ldq_idx, issue_slots[3].in_uop.bits.ldq_idx
connect slots_3.io.in_uop.bits.rob_idx, issue_slots[3].in_uop.bits.rob_idx
connect slots_3.io.in_uop.bits.fp_ctrl.vec, issue_slots[3].in_uop.bits.fp_ctrl.vec
connect slots_3.io.in_uop.bits.fp_ctrl.wflags, issue_slots[3].in_uop.bits.fp_ctrl.wflags
connect slots_3.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[3].in_uop.bits.fp_ctrl.sqrt
connect slots_3.io.in_uop.bits.fp_ctrl.div, issue_slots[3].in_uop.bits.fp_ctrl.div
connect slots_3.io.in_uop.bits.fp_ctrl.fma, issue_slots[3].in_uop.bits.fp_ctrl.fma
connect slots_3.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[3].in_uop.bits.fp_ctrl.fastpipe
connect slots_3.io.in_uop.bits.fp_ctrl.toint, issue_slots[3].in_uop.bits.fp_ctrl.toint
connect slots_3.io.in_uop.bits.fp_ctrl.fromint, issue_slots[3].in_uop.bits.fp_ctrl.fromint
connect slots_3.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[3].in_uop.bits.fp_ctrl.typeTagOut
connect slots_3.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[3].in_uop.bits.fp_ctrl.typeTagIn
connect slots_3.io.in_uop.bits.fp_ctrl.swap23, issue_slots[3].in_uop.bits.fp_ctrl.swap23
connect slots_3.io.in_uop.bits.fp_ctrl.swap12, issue_slots[3].in_uop.bits.fp_ctrl.swap12
connect slots_3.io.in_uop.bits.fp_ctrl.ren3, issue_slots[3].in_uop.bits.fp_ctrl.ren3
connect slots_3.io.in_uop.bits.fp_ctrl.ren2, issue_slots[3].in_uop.bits.fp_ctrl.ren2
connect slots_3.io.in_uop.bits.fp_ctrl.ren1, issue_slots[3].in_uop.bits.fp_ctrl.ren1
connect slots_3.io.in_uop.bits.fp_ctrl.wen, issue_slots[3].in_uop.bits.fp_ctrl.wen
connect slots_3.io.in_uop.bits.fp_ctrl.ldst, issue_slots[3].in_uop.bits.fp_ctrl.ldst
connect slots_3.io.in_uop.bits.op2_sel, issue_slots[3].in_uop.bits.op2_sel
connect slots_3.io.in_uop.bits.op1_sel, issue_slots[3].in_uop.bits.op1_sel
connect slots_3.io.in_uop.bits.imm_packed, issue_slots[3].in_uop.bits.imm_packed
connect slots_3.io.in_uop.bits.pimm, issue_slots[3].in_uop.bits.pimm
connect slots_3.io.in_uop.bits.imm_sel, issue_slots[3].in_uop.bits.imm_sel
connect slots_3.io.in_uop.bits.imm_rename, issue_slots[3].in_uop.bits.imm_rename
connect slots_3.io.in_uop.bits.taken, issue_slots[3].in_uop.bits.taken
connect slots_3.io.in_uop.bits.pc_lob, issue_slots[3].in_uop.bits.pc_lob
connect slots_3.io.in_uop.bits.edge_inst, issue_slots[3].in_uop.bits.edge_inst
connect slots_3.io.in_uop.bits.ftq_idx, issue_slots[3].in_uop.bits.ftq_idx
connect slots_3.io.in_uop.bits.is_mov, issue_slots[3].in_uop.bits.is_mov
connect slots_3.io.in_uop.bits.is_rocc, issue_slots[3].in_uop.bits.is_rocc
connect slots_3.io.in_uop.bits.is_sys_pc2epc, issue_slots[3].in_uop.bits.is_sys_pc2epc
connect slots_3.io.in_uop.bits.is_eret, issue_slots[3].in_uop.bits.is_eret
connect slots_3.io.in_uop.bits.is_amo, issue_slots[3].in_uop.bits.is_amo
connect slots_3.io.in_uop.bits.is_sfence, issue_slots[3].in_uop.bits.is_sfence
connect slots_3.io.in_uop.bits.is_fencei, issue_slots[3].in_uop.bits.is_fencei
connect slots_3.io.in_uop.bits.is_fence, issue_slots[3].in_uop.bits.is_fence
connect slots_3.io.in_uop.bits.is_sfb, issue_slots[3].in_uop.bits.is_sfb
connect slots_3.io.in_uop.bits.br_type, issue_slots[3].in_uop.bits.br_type
connect slots_3.io.in_uop.bits.br_tag, issue_slots[3].in_uop.bits.br_tag
connect slots_3.io.in_uop.bits.br_mask, issue_slots[3].in_uop.bits.br_mask
connect slots_3.io.in_uop.bits.dis_col_sel, issue_slots[3].in_uop.bits.dis_col_sel
connect slots_3.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[3].in_uop.bits.iw_p3_bypass_hint
connect slots_3.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[3].in_uop.bits.iw_p2_bypass_hint
connect slots_3.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[3].in_uop.bits.iw_p1_bypass_hint
connect slots_3.io.in_uop.bits.iw_p2_speculative_child, issue_slots[3].in_uop.bits.iw_p2_speculative_child
connect slots_3.io.in_uop.bits.iw_p1_speculative_child, issue_slots[3].in_uop.bits.iw_p1_speculative_child
connect slots_3.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[3].in_uop.bits.iw_issued_partial_dgen
connect slots_3.io.in_uop.bits.iw_issued_partial_agen, issue_slots[3].in_uop.bits.iw_issued_partial_agen
connect slots_3.io.in_uop.bits.iw_issued, issue_slots[3].in_uop.bits.iw_issued
connect slots_3.io.in_uop.bits.fu_code[0], issue_slots[3].in_uop.bits.fu_code[0]
connect slots_3.io.in_uop.bits.fu_code[1], issue_slots[3].in_uop.bits.fu_code[1]
connect slots_3.io.in_uop.bits.fu_code[2], issue_slots[3].in_uop.bits.fu_code[2]
connect slots_3.io.in_uop.bits.fu_code[3], issue_slots[3].in_uop.bits.fu_code[3]
connect slots_3.io.in_uop.bits.fu_code[4], issue_slots[3].in_uop.bits.fu_code[4]
connect slots_3.io.in_uop.bits.fu_code[5], issue_slots[3].in_uop.bits.fu_code[5]
connect slots_3.io.in_uop.bits.fu_code[6], issue_slots[3].in_uop.bits.fu_code[6]
connect slots_3.io.in_uop.bits.fu_code[7], issue_slots[3].in_uop.bits.fu_code[7]
connect slots_3.io.in_uop.bits.fu_code[8], issue_slots[3].in_uop.bits.fu_code[8]
connect slots_3.io.in_uop.bits.fu_code[9], issue_slots[3].in_uop.bits.fu_code[9]
connect slots_3.io.in_uop.bits.iq_type[0], issue_slots[3].in_uop.bits.iq_type[0]
connect slots_3.io.in_uop.bits.iq_type[1], issue_slots[3].in_uop.bits.iq_type[1]
connect slots_3.io.in_uop.bits.iq_type[2], issue_slots[3].in_uop.bits.iq_type[2]
connect slots_3.io.in_uop.bits.iq_type[3], issue_slots[3].in_uop.bits.iq_type[3]
connect slots_3.io.in_uop.bits.debug_pc, issue_slots[3].in_uop.bits.debug_pc
connect slots_3.io.in_uop.bits.is_rvc, issue_slots[3].in_uop.bits.is_rvc
connect slots_3.io.in_uop.bits.debug_inst, issue_slots[3].in_uop.bits.debug_inst
connect slots_3.io.in_uop.bits.inst, issue_slots[3].in_uop.bits.inst
connect slots_3.io.in_uop.valid, issue_slots[3].in_uop.valid
connect issue_slots[3].iss_uop.debug_tsrc, slots_3.io.iss_uop.debug_tsrc
connect issue_slots[3].iss_uop.debug_fsrc, slots_3.io.iss_uop.debug_fsrc
connect issue_slots[3].iss_uop.bp_xcpt_if, slots_3.io.iss_uop.bp_xcpt_if
connect issue_slots[3].iss_uop.bp_debug_if, slots_3.io.iss_uop.bp_debug_if
connect issue_slots[3].iss_uop.xcpt_ma_if, slots_3.io.iss_uop.xcpt_ma_if
connect issue_slots[3].iss_uop.xcpt_ae_if, slots_3.io.iss_uop.xcpt_ae_if
connect issue_slots[3].iss_uop.xcpt_pf_if, slots_3.io.iss_uop.xcpt_pf_if
connect issue_slots[3].iss_uop.fp_typ, slots_3.io.iss_uop.fp_typ
connect issue_slots[3].iss_uop.fp_rm, slots_3.io.iss_uop.fp_rm
connect issue_slots[3].iss_uop.fp_val, slots_3.io.iss_uop.fp_val
connect issue_slots[3].iss_uop.fcn_op, slots_3.io.iss_uop.fcn_op
connect issue_slots[3].iss_uop.fcn_dw, slots_3.io.iss_uop.fcn_dw
connect issue_slots[3].iss_uop.frs3_en, slots_3.io.iss_uop.frs3_en
connect issue_slots[3].iss_uop.lrs2_rtype, slots_3.io.iss_uop.lrs2_rtype
connect issue_slots[3].iss_uop.lrs1_rtype, slots_3.io.iss_uop.lrs1_rtype
connect issue_slots[3].iss_uop.dst_rtype, slots_3.io.iss_uop.dst_rtype
connect issue_slots[3].iss_uop.lrs3, slots_3.io.iss_uop.lrs3
connect issue_slots[3].iss_uop.lrs2, slots_3.io.iss_uop.lrs2
connect issue_slots[3].iss_uop.lrs1, slots_3.io.iss_uop.lrs1
connect issue_slots[3].iss_uop.ldst, slots_3.io.iss_uop.ldst
connect issue_slots[3].iss_uop.ldst_is_rs1, slots_3.io.iss_uop.ldst_is_rs1
connect issue_slots[3].iss_uop.csr_cmd, slots_3.io.iss_uop.csr_cmd
connect issue_slots[3].iss_uop.flush_on_commit, slots_3.io.iss_uop.flush_on_commit
connect issue_slots[3].iss_uop.is_unique, slots_3.io.iss_uop.is_unique
connect issue_slots[3].iss_uop.uses_stq, slots_3.io.iss_uop.uses_stq
connect issue_slots[3].iss_uop.uses_ldq, slots_3.io.iss_uop.uses_ldq
connect issue_slots[3].iss_uop.mem_signed, slots_3.io.iss_uop.mem_signed
connect issue_slots[3].iss_uop.mem_size, slots_3.io.iss_uop.mem_size
connect issue_slots[3].iss_uop.mem_cmd, slots_3.io.iss_uop.mem_cmd
connect issue_slots[3].iss_uop.exc_cause, slots_3.io.iss_uop.exc_cause
connect issue_slots[3].iss_uop.exception, slots_3.io.iss_uop.exception
connect issue_slots[3].iss_uop.stale_pdst, slots_3.io.iss_uop.stale_pdst
connect issue_slots[3].iss_uop.ppred_busy, slots_3.io.iss_uop.ppred_busy
connect issue_slots[3].iss_uop.prs3_busy, slots_3.io.iss_uop.prs3_busy
connect issue_slots[3].iss_uop.prs2_busy, slots_3.io.iss_uop.prs2_busy
connect issue_slots[3].iss_uop.prs1_busy, slots_3.io.iss_uop.prs1_busy
connect issue_slots[3].iss_uop.ppred, slots_3.io.iss_uop.ppred
connect issue_slots[3].iss_uop.prs3, slots_3.io.iss_uop.prs3
connect issue_slots[3].iss_uop.prs2, slots_3.io.iss_uop.prs2
connect issue_slots[3].iss_uop.prs1, slots_3.io.iss_uop.prs1
connect issue_slots[3].iss_uop.pdst, slots_3.io.iss_uop.pdst
connect issue_slots[3].iss_uop.rxq_idx, slots_3.io.iss_uop.rxq_idx
connect issue_slots[3].iss_uop.stq_idx, slots_3.io.iss_uop.stq_idx
connect issue_slots[3].iss_uop.ldq_idx, slots_3.io.iss_uop.ldq_idx
connect issue_slots[3].iss_uop.rob_idx, slots_3.io.iss_uop.rob_idx
connect issue_slots[3].iss_uop.fp_ctrl.vec, slots_3.io.iss_uop.fp_ctrl.vec
connect issue_slots[3].iss_uop.fp_ctrl.wflags, slots_3.io.iss_uop.fp_ctrl.wflags
connect issue_slots[3].iss_uop.fp_ctrl.sqrt, slots_3.io.iss_uop.fp_ctrl.sqrt
connect issue_slots[3].iss_uop.fp_ctrl.div, slots_3.io.iss_uop.fp_ctrl.div
connect issue_slots[3].iss_uop.fp_ctrl.fma, slots_3.io.iss_uop.fp_ctrl.fma
connect issue_slots[3].iss_uop.fp_ctrl.fastpipe, slots_3.io.iss_uop.fp_ctrl.fastpipe
connect issue_slots[3].iss_uop.fp_ctrl.toint, slots_3.io.iss_uop.fp_ctrl.toint
connect issue_slots[3].iss_uop.fp_ctrl.fromint, slots_3.io.iss_uop.fp_ctrl.fromint
connect issue_slots[3].iss_uop.fp_ctrl.typeTagOut, slots_3.io.iss_uop.fp_ctrl.typeTagOut
connect issue_slots[3].iss_uop.fp_ctrl.typeTagIn, slots_3.io.iss_uop.fp_ctrl.typeTagIn
connect issue_slots[3].iss_uop.fp_ctrl.swap23, slots_3.io.iss_uop.fp_ctrl.swap23
connect issue_slots[3].iss_uop.fp_ctrl.swap12, slots_3.io.iss_uop.fp_ctrl.swap12
connect issue_slots[3].iss_uop.fp_ctrl.ren3, slots_3.io.iss_uop.fp_ctrl.ren3
connect issue_slots[3].iss_uop.fp_ctrl.ren2, slots_3.io.iss_uop.fp_ctrl.ren2
connect issue_slots[3].iss_uop.fp_ctrl.ren1, slots_3.io.iss_uop.fp_ctrl.ren1
connect issue_slots[3].iss_uop.fp_ctrl.wen, slots_3.io.iss_uop.fp_ctrl.wen
connect issue_slots[3].iss_uop.fp_ctrl.ldst, slots_3.io.iss_uop.fp_ctrl.ldst
connect issue_slots[3].iss_uop.op2_sel, slots_3.io.iss_uop.op2_sel
connect issue_slots[3].iss_uop.op1_sel, slots_3.io.iss_uop.op1_sel
connect issue_slots[3].iss_uop.imm_packed, slots_3.io.iss_uop.imm_packed
connect issue_slots[3].iss_uop.pimm, slots_3.io.iss_uop.pimm
connect issue_slots[3].iss_uop.imm_sel, slots_3.io.iss_uop.imm_sel
connect issue_slots[3].iss_uop.imm_rename, slots_3.io.iss_uop.imm_rename
connect issue_slots[3].iss_uop.taken, slots_3.io.iss_uop.taken
connect issue_slots[3].iss_uop.pc_lob, slots_3.io.iss_uop.pc_lob
connect issue_slots[3].iss_uop.edge_inst, slots_3.io.iss_uop.edge_inst
connect issue_slots[3].iss_uop.ftq_idx, slots_3.io.iss_uop.ftq_idx
connect issue_slots[3].iss_uop.is_mov, slots_3.io.iss_uop.is_mov
connect issue_slots[3].iss_uop.is_rocc, slots_3.io.iss_uop.is_rocc
connect issue_slots[3].iss_uop.is_sys_pc2epc, slots_3.io.iss_uop.is_sys_pc2epc
connect issue_slots[3].iss_uop.is_eret, slots_3.io.iss_uop.is_eret
connect issue_slots[3].iss_uop.is_amo, slots_3.io.iss_uop.is_amo
connect issue_slots[3].iss_uop.is_sfence, slots_3.io.iss_uop.is_sfence
connect issue_slots[3].iss_uop.is_fencei, slots_3.io.iss_uop.is_fencei
connect issue_slots[3].iss_uop.is_fence, slots_3.io.iss_uop.is_fence
connect issue_slots[3].iss_uop.is_sfb, slots_3.io.iss_uop.is_sfb
connect issue_slots[3].iss_uop.br_type, slots_3.io.iss_uop.br_type
connect issue_slots[3].iss_uop.br_tag, slots_3.io.iss_uop.br_tag
connect issue_slots[3].iss_uop.br_mask, slots_3.io.iss_uop.br_mask
connect issue_slots[3].iss_uop.dis_col_sel, slots_3.io.iss_uop.dis_col_sel
connect issue_slots[3].iss_uop.iw_p3_bypass_hint, slots_3.io.iss_uop.iw_p3_bypass_hint
connect issue_slots[3].iss_uop.iw_p2_bypass_hint, slots_3.io.iss_uop.iw_p2_bypass_hint
connect issue_slots[3].iss_uop.iw_p1_bypass_hint, slots_3.io.iss_uop.iw_p1_bypass_hint
connect issue_slots[3].iss_uop.iw_p2_speculative_child, slots_3.io.iss_uop.iw_p2_speculative_child
connect issue_slots[3].iss_uop.iw_p1_speculative_child, slots_3.io.iss_uop.iw_p1_speculative_child
connect issue_slots[3].iss_uop.iw_issued_partial_dgen, slots_3.io.iss_uop.iw_issued_partial_dgen
connect issue_slots[3].iss_uop.iw_issued_partial_agen, slots_3.io.iss_uop.iw_issued_partial_agen
connect issue_slots[3].iss_uop.iw_issued, slots_3.io.iss_uop.iw_issued
connect issue_slots[3].iss_uop.fu_code[0], slots_3.io.iss_uop.fu_code[0]
connect issue_slots[3].iss_uop.fu_code[1], slots_3.io.iss_uop.fu_code[1]
connect issue_slots[3].iss_uop.fu_code[2], slots_3.io.iss_uop.fu_code[2]
connect issue_slots[3].iss_uop.fu_code[3], slots_3.io.iss_uop.fu_code[3]
connect issue_slots[3].iss_uop.fu_code[4], slots_3.io.iss_uop.fu_code[4]
connect issue_slots[3].iss_uop.fu_code[5], slots_3.io.iss_uop.fu_code[5]
connect issue_slots[3].iss_uop.fu_code[6], slots_3.io.iss_uop.fu_code[6]
connect issue_slots[3].iss_uop.fu_code[7], slots_3.io.iss_uop.fu_code[7]
connect issue_slots[3].iss_uop.fu_code[8], slots_3.io.iss_uop.fu_code[8]
connect issue_slots[3].iss_uop.fu_code[9], slots_3.io.iss_uop.fu_code[9]
connect issue_slots[3].iss_uop.iq_type[0], slots_3.io.iss_uop.iq_type[0]
connect issue_slots[3].iss_uop.iq_type[1], slots_3.io.iss_uop.iq_type[1]
connect issue_slots[3].iss_uop.iq_type[2], slots_3.io.iss_uop.iq_type[2]
connect issue_slots[3].iss_uop.iq_type[3], slots_3.io.iss_uop.iq_type[3]
connect issue_slots[3].iss_uop.debug_pc, slots_3.io.iss_uop.debug_pc
connect issue_slots[3].iss_uop.is_rvc, slots_3.io.iss_uop.is_rvc
connect issue_slots[3].iss_uop.debug_inst, slots_3.io.iss_uop.debug_inst
connect issue_slots[3].iss_uop.inst, slots_3.io.iss_uop.inst
connect slots_3.io.grant, issue_slots[3].grant
connect issue_slots[3].request, slots_3.io.request
connect issue_slots[3].will_be_valid, slots_3.io.will_be_valid
connect issue_slots[3].valid, slots_3.io.valid
connect slots_4.io.child_rebusys, issue_slots[4].child_rebusys
connect slots_4.io.pred_wakeup_port.bits, issue_slots[4].pred_wakeup_port.bits
connect slots_4.io.pred_wakeup_port.valid, issue_slots[4].pred_wakeup_port.valid
connect slots_4.io.wakeup_ports[0].bits.rebusy, issue_slots[4].wakeup_ports[0].bits.rebusy
connect slots_4.io.wakeup_ports[0].bits.speculative_mask, issue_slots[4].wakeup_ports[0].bits.speculative_mask
connect slots_4.io.wakeup_ports[0].bits.bypassable, issue_slots[4].wakeup_ports[0].bits.bypassable
connect slots_4.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[4].wakeup_ports[0].bits.uop.debug_tsrc
connect slots_4.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[4].wakeup_ports[0].bits.uop.debug_fsrc
connect slots_4.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[4].wakeup_ports[0].bits.uop.bp_xcpt_if
connect slots_4.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[4].wakeup_ports[0].bits.uop.bp_debug_if
connect slots_4.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[4].wakeup_ports[0].bits.uop.xcpt_ma_if
connect slots_4.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[4].wakeup_ports[0].bits.uop.xcpt_ae_if
connect slots_4.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[4].wakeup_ports[0].bits.uop.xcpt_pf_if
connect slots_4.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[4].wakeup_ports[0].bits.uop.fp_typ
connect slots_4.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[4].wakeup_ports[0].bits.uop.fp_rm
connect slots_4.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[4].wakeup_ports[0].bits.uop.fp_val
connect slots_4.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[4].wakeup_ports[0].bits.uop.fcn_op
connect slots_4.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[4].wakeup_ports[0].bits.uop.fcn_dw
connect slots_4.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[4].wakeup_ports[0].bits.uop.frs3_en
connect slots_4.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[4].wakeup_ports[0].bits.uop.lrs2_rtype
connect slots_4.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[4].wakeup_ports[0].bits.uop.lrs1_rtype
connect slots_4.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[4].wakeup_ports[0].bits.uop.dst_rtype
connect slots_4.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[4].wakeup_ports[0].bits.uop.lrs3
connect slots_4.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[4].wakeup_ports[0].bits.uop.lrs2
connect slots_4.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[4].wakeup_ports[0].bits.uop.lrs1
connect slots_4.io.wakeup_ports[0].bits.uop.ldst, issue_slots[4].wakeup_ports[0].bits.uop.ldst
connect slots_4.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[4].wakeup_ports[0].bits.uop.ldst_is_rs1
connect slots_4.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[4].wakeup_ports[0].bits.uop.csr_cmd
connect slots_4.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[4].wakeup_ports[0].bits.uop.flush_on_commit
connect slots_4.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[4].wakeup_ports[0].bits.uop.is_unique
connect slots_4.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[4].wakeup_ports[0].bits.uop.uses_stq
connect slots_4.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[4].wakeup_ports[0].bits.uop.uses_ldq
connect slots_4.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[4].wakeup_ports[0].bits.uop.mem_signed
connect slots_4.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[4].wakeup_ports[0].bits.uop.mem_size
connect slots_4.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[4].wakeup_ports[0].bits.uop.mem_cmd
connect slots_4.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[4].wakeup_ports[0].bits.uop.exc_cause
connect slots_4.io.wakeup_ports[0].bits.uop.exception, issue_slots[4].wakeup_ports[0].bits.uop.exception
connect slots_4.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[4].wakeup_ports[0].bits.uop.stale_pdst
connect slots_4.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[4].wakeup_ports[0].bits.uop.ppred_busy
connect slots_4.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[4].wakeup_ports[0].bits.uop.prs3_busy
connect slots_4.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[4].wakeup_ports[0].bits.uop.prs2_busy
connect slots_4.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[4].wakeup_ports[0].bits.uop.prs1_busy
connect slots_4.io.wakeup_ports[0].bits.uop.ppred, issue_slots[4].wakeup_ports[0].bits.uop.ppred
connect slots_4.io.wakeup_ports[0].bits.uop.prs3, issue_slots[4].wakeup_ports[0].bits.uop.prs3
connect slots_4.io.wakeup_ports[0].bits.uop.prs2, issue_slots[4].wakeup_ports[0].bits.uop.prs2
connect slots_4.io.wakeup_ports[0].bits.uop.prs1, issue_slots[4].wakeup_ports[0].bits.uop.prs1
connect slots_4.io.wakeup_ports[0].bits.uop.pdst, issue_slots[4].wakeup_ports[0].bits.uop.pdst
connect slots_4.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[4].wakeup_ports[0].bits.uop.rxq_idx
connect slots_4.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[4].wakeup_ports[0].bits.uop.stq_idx
connect slots_4.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[4].wakeup_ports[0].bits.uop.ldq_idx
connect slots_4.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[4].wakeup_ports[0].bits.uop.rob_idx
connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.vec
connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.wflags
connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.sqrt
connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.div
connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.fma
connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe
connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.toint
connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.fromint
connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut
connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn
connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.swap23
connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.swap12
connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.ren3
connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.ren2
connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.ren1
connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.wen
connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.ldst
connect slots_4.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[4].wakeup_ports[0].bits.uop.op2_sel
connect slots_4.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[4].wakeup_ports[0].bits.uop.op1_sel
connect slots_4.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[4].wakeup_ports[0].bits.uop.imm_packed
connect slots_4.io.wakeup_ports[0].bits.uop.pimm, issue_slots[4].wakeup_ports[0].bits.uop.pimm
connect slots_4.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[4].wakeup_ports[0].bits.uop.imm_sel
connect slots_4.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[4].wakeup_ports[0].bits.uop.imm_rename
connect slots_4.io.wakeup_ports[0].bits.uop.taken, issue_slots[4].wakeup_ports[0].bits.uop.taken
connect slots_4.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[4].wakeup_ports[0].bits.uop.pc_lob
connect slots_4.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[4].wakeup_ports[0].bits.uop.edge_inst
connect slots_4.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[4].wakeup_ports[0].bits.uop.ftq_idx
connect slots_4.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[4].wakeup_ports[0].bits.uop.is_mov
connect slots_4.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[4].wakeup_ports[0].bits.uop.is_rocc
connect slots_4.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[4].wakeup_ports[0].bits.uop.is_sys_pc2epc
connect slots_4.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[4].wakeup_ports[0].bits.uop.is_eret
connect slots_4.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[4].wakeup_ports[0].bits.uop.is_amo
connect slots_4.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[4].wakeup_ports[0].bits.uop.is_sfence
connect slots_4.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[4].wakeup_ports[0].bits.uop.is_fencei
connect slots_4.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[4].wakeup_ports[0].bits.uop.is_fence
connect slots_4.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[4].wakeup_ports[0].bits.uop.is_sfb
connect slots_4.io.wakeup_ports[0].bits.uop.br_type, issue_slots[4].wakeup_ports[0].bits.uop.br_type
connect slots_4.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[4].wakeup_ports[0].bits.uop.br_tag
connect slots_4.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[4].wakeup_ports[0].bits.uop.br_mask
connect slots_4.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[4].wakeup_ports[0].bits.uop.dis_col_sel
connect slots_4.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[4].wakeup_ports[0].bits.uop.iw_p3_bypass_hint
connect slots_4.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[4].wakeup_ports[0].bits.uop.iw_p2_bypass_hint
connect slots_4.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[4].wakeup_ports[0].bits.uop.iw_p1_bypass_hint
connect slots_4.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[4].wakeup_ports[0].bits.uop.iw_p2_speculative_child
connect slots_4.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[4].wakeup_ports[0].bits.uop.iw_p1_speculative_child
connect slots_4.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[4].wakeup_ports[0].bits.uop.iw_issued_partial_dgen
connect slots_4.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[4].wakeup_ports[0].bits.uop.iw_issued_partial_agen
connect slots_4.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[4].wakeup_ports[0].bits.uop.iw_issued
connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[0]
connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[1]
connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[2]
connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[3]
connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[4]
connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[5]
connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[6]
connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[7]
connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[8]
connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[9]
connect slots_4.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[4].wakeup_ports[0].bits.uop.iq_type[0]
connect slots_4.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[4].wakeup_ports[0].bits.uop.iq_type[1]
connect slots_4.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[4].wakeup_ports[0].bits.uop.iq_type[2]
connect slots_4.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[4].wakeup_ports[0].bits.uop.iq_type[3]
connect slots_4.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[4].wakeup_ports[0].bits.uop.debug_pc
connect slots_4.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[4].wakeup_ports[0].bits.uop.is_rvc
connect slots_4.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[4].wakeup_ports[0].bits.uop.debug_inst
connect slots_4.io.wakeup_ports[0].bits.uop.inst, issue_slots[4].wakeup_ports[0].bits.uop.inst
connect slots_4.io.wakeup_ports[0].valid, issue_slots[4].wakeup_ports[0].valid
connect slots_4.io.wakeup_ports[1].bits.rebusy, issue_slots[4].wakeup_ports[1].bits.rebusy
connect slots_4.io.wakeup_ports[1].bits.speculative_mask, issue_slots[4].wakeup_ports[1].bits.speculative_mask
connect slots_4.io.wakeup_ports[1].bits.bypassable, issue_slots[4].wakeup_ports[1].bits.bypassable
connect slots_4.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[4].wakeup_ports[1].bits.uop.debug_tsrc
connect slots_4.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[4].wakeup_ports[1].bits.uop.debug_fsrc
connect slots_4.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[4].wakeup_ports[1].bits.uop.bp_xcpt_if
connect slots_4.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[4].wakeup_ports[1].bits.uop.bp_debug_if
connect slots_4.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[4].wakeup_ports[1].bits.uop.xcpt_ma_if
connect slots_4.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[4].wakeup_ports[1].bits.uop.xcpt_ae_if
connect slots_4.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[4].wakeup_ports[1].bits.uop.xcpt_pf_if
connect slots_4.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[4].wakeup_ports[1].bits.uop.fp_typ
connect slots_4.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[4].wakeup_ports[1].bits.uop.fp_rm
connect slots_4.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[4].wakeup_ports[1].bits.uop.fp_val
connect slots_4.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[4].wakeup_ports[1].bits.uop.fcn_op
connect slots_4.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[4].wakeup_ports[1].bits.uop.fcn_dw
connect slots_4.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[4].wakeup_ports[1].bits.uop.frs3_en
connect slots_4.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[4].wakeup_ports[1].bits.uop.lrs2_rtype
connect slots_4.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[4].wakeup_ports[1].bits.uop.lrs1_rtype
connect slots_4.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[4].wakeup_ports[1].bits.uop.dst_rtype
connect slots_4.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[4].wakeup_ports[1].bits.uop.lrs3
connect slots_4.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[4].wakeup_ports[1].bits.uop.lrs2
connect slots_4.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[4].wakeup_ports[1].bits.uop.lrs1
connect slots_4.io.wakeup_ports[1].bits.uop.ldst, issue_slots[4].wakeup_ports[1].bits.uop.ldst
connect slots_4.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[4].wakeup_ports[1].bits.uop.ldst_is_rs1
connect slots_4.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[4].wakeup_ports[1].bits.uop.csr_cmd
connect slots_4.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[4].wakeup_ports[1].bits.uop.flush_on_commit
connect slots_4.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[4].wakeup_ports[1].bits.uop.is_unique
connect slots_4.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[4].wakeup_ports[1].bits.uop.uses_stq
connect slots_4.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[4].wakeup_ports[1].bits.uop.uses_ldq
connect slots_4.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[4].wakeup_ports[1].bits.uop.mem_signed
connect slots_4.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[4].wakeup_ports[1].bits.uop.mem_size
connect slots_4.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[4].wakeup_ports[1].bits.uop.mem_cmd
connect slots_4.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[4].wakeup_ports[1].bits.uop.exc_cause
connect slots_4.io.wakeup_ports[1].bits.uop.exception, issue_slots[4].wakeup_ports[1].bits.uop.exception
connect slots_4.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[4].wakeup_ports[1].bits.uop.stale_pdst
connect slots_4.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[4].wakeup_ports[1].bits.uop.ppred_busy
connect slots_4.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[4].wakeup_ports[1].bits.uop.prs3_busy
connect slots_4.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[4].wakeup_ports[1].bits.uop.prs2_busy
connect slots_4.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[4].wakeup_ports[1].bits.uop.prs1_busy
connect slots_4.io.wakeup_ports[1].bits.uop.ppred, issue_slots[4].wakeup_ports[1].bits.uop.ppred
connect slots_4.io.wakeup_ports[1].bits.uop.prs3, issue_slots[4].wakeup_ports[1].bits.uop.prs3
connect slots_4.io.wakeup_ports[1].bits.uop.prs2, issue_slots[4].wakeup_ports[1].bits.uop.prs2
connect slots_4.io.wakeup_ports[1].bits.uop.prs1, issue_slots[4].wakeup_ports[1].bits.uop.prs1
connect slots_4.io.wakeup_ports[1].bits.uop.pdst, issue_slots[4].wakeup_ports[1].bits.uop.pdst
connect slots_4.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[4].wakeup_ports[1].bits.uop.rxq_idx
connect slots_4.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[4].wakeup_ports[1].bits.uop.stq_idx
connect slots_4.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[4].wakeup_ports[1].bits.uop.ldq_idx
connect slots_4.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[4].wakeup_ports[1].bits.uop.rob_idx
connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.vec
connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.wflags
connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.sqrt
connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.div
connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.fma
connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe
connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.toint
connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.fromint
connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut
connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn
connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.swap23
connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.swap12
connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.ren3
connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.ren2
connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.ren1
connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.wen
connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.ldst
connect slots_4.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[4].wakeup_ports[1].bits.uop.op2_sel
connect slots_4.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[4].wakeup_ports[1].bits.uop.op1_sel
connect slots_4.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[4].wakeup_ports[1].bits.uop.imm_packed
connect slots_4.io.wakeup_ports[1].bits.uop.pimm, issue_slots[4].wakeup_ports[1].bits.uop.pimm
connect slots_4.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[4].wakeup_ports[1].bits.uop.imm_sel
connect slots_4.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[4].wakeup_ports[1].bits.uop.imm_rename
connect slots_4.io.wakeup_ports[1].bits.uop.taken, issue_slots[4].wakeup_ports[1].bits.uop.taken
connect slots_4.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[4].wakeup_ports[1].bits.uop.pc_lob
connect slots_4.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[4].wakeup_ports[1].bits.uop.edge_inst
connect slots_4.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[4].wakeup_ports[1].bits.uop.ftq_idx
connect slots_4.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[4].wakeup_ports[1].bits.uop.is_mov
connect slots_4.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[4].wakeup_ports[1].bits.uop.is_rocc
connect slots_4.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[4].wakeup_ports[1].bits.uop.is_sys_pc2epc
connect slots_4.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[4].wakeup_ports[1].bits.uop.is_eret
connect slots_4.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[4].wakeup_ports[1].bits.uop.is_amo
connect slots_4.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[4].wakeup_ports[1].bits.uop.is_sfence
connect slots_4.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[4].wakeup_ports[1].bits.uop.is_fencei
connect slots_4.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[4].wakeup_ports[1].bits.uop.is_fence
connect slots_4.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[4].wakeup_ports[1].bits.uop.is_sfb
connect slots_4.io.wakeup_ports[1].bits.uop.br_type, issue_slots[4].wakeup_ports[1].bits.uop.br_type
connect slots_4.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[4].wakeup_ports[1].bits.uop.br_tag
connect slots_4.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[4].wakeup_ports[1].bits.uop.br_mask
connect slots_4.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[4].wakeup_ports[1].bits.uop.dis_col_sel
connect slots_4.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[4].wakeup_ports[1].bits.uop.iw_p3_bypass_hint
connect slots_4.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[4].wakeup_ports[1].bits.uop.iw_p2_bypass_hint
connect slots_4.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[4].wakeup_ports[1].bits.uop.iw_p1_bypass_hint
connect slots_4.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[4].wakeup_ports[1].bits.uop.iw_p2_speculative_child
connect slots_4.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[4].wakeup_ports[1].bits.uop.iw_p1_speculative_child
connect slots_4.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[4].wakeup_ports[1].bits.uop.iw_issued_partial_dgen
connect slots_4.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[4].wakeup_ports[1].bits.uop.iw_issued_partial_agen
connect slots_4.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[4].wakeup_ports[1].bits.uop.iw_issued
connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[0]
connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[1]
connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[2]
connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[3]
connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[4]
connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[5]
connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[6]
connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[7]
connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[8]
connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[9]
connect slots_4.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[4].wakeup_ports[1].bits.uop.iq_type[0]
connect slots_4.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[4].wakeup_ports[1].bits.uop.iq_type[1]
connect slots_4.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[4].wakeup_ports[1].bits.uop.iq_type[2]
connect slots_4.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[4].wakeup_ports[1].bits.uop.iq_type[3]
connect slots_4.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[4].wakeup_ports[1].bits.uop.debug_pc
connect slots_4.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[4].wakeup_ports[1].bits.uop.is_rvc
connect slots_4.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[4].wakeup_ports[1].bits.uop.debug_inst
connect slots_4.io.wakeup_ports[1].bits.uop.inst, issue_slots[4].wakeup_ports[1].bits.uop.inst
connect slots_4.io.wakeup_ports[1].valid, issue_slots[4].wakeup_ports[1].valid
connect slots_4.io.wakeup_ports[2].bits.rebusy, issue_slots[4].wakeup_ports[2].bits.rebusy
connect slots_4.io.wakeup_ports[2].bits.speculative_mask, issue_slots[4].wakeup_ports[2].bits.speculative_mask
connect slots_4.io.wakeup_ports[2].bits.bypassable, issue_slots[4].wakeup_ports[2].bits.bypassable
connect slots_4.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[4].wakeup_ports[2].bits.uop.debug_tsrc
connect slots_4.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[4].wakeup_ports[2].bits.uop.debug_fsrc
connect slots_4.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[4].wakeup_ports[2].bits.uop.bp_xcpt_if
connect slots_4.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[4].wakeup_ports[2].bits.uop.bp_debug_if
connect slots_4.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[4].wakeup_ports[2].bits.uop.xcpt_ma_if
connect slots_4.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[4].wakeup_ports[2].bits.uop.xcpt_ae_if
connect slots_4.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[4].wakeup_ports[2].bits.uop.xcpt_pf_if
connect slots_4.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[4].wakeup_ports[2].bits.uop.fp_typ
connect slots_4.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[4].wakeup_ports[2].bits.uop.fp_rm
connect slots_4.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[4].wakeup_ports[2].bits.uop.fp_val
connect slots_4.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[4].wakeup_ports[2].bits.uop.fcn_op
connect slots_4.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[4].wakeup_ports[2].bits.uop.fcn_dw
connect slots_4.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[4].wakeup_ports[2].bits.uop.frs3_en
connect slots_4.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[4].wakeup_ports[2].bits.uop.lrs2_rtype
connect slots_4.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[4].wakeup_ports[2].bits.uop.lrs1_rtype
connect slots_4.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[4].wakeup_ports[2].bits.uop.dst_rtype
connect slots_4.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[4].wakeup_ports[2].bits.uop.lrs3
connect slots_4.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[4].wakeup_ports[2].bits.uop.lrs2
connect slots_4.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[4].wakeup_ports[2].bits.uop.lrs1
connect slots_4.io.wakeup_ports[2].bits.uop.ldst, issue_slots[4].wakeup_ports[2].bits.uop.ldst
connect slots_4.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[4].wakeup_ports[2].bits.uop.ldst_is_rs1
connect slots_4.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[4].wakeup_ports[2].bits.uop.csr_cmd
connect slots_4.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[4].wakeup_ports[2].bits.uop.flush_on_commit
connect slots_4.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[4].wakeup_ports[2].bits.uop.is_unique
connect slots_4.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[4].wakeup_ports[2].bits.uop.uses_stq
connect slots_4.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[4].wakeup_ports[2].bits.uop.uses_ldq
connect slots_4.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[4].wakeup_ports[2].bits.uop.mem_signed
connect slots_4.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[4].wakeup_ports[2].bits.uop.mem_size
connect slots_4.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[4].wakeup_ports[2].bits.uop.mem_cmd
connect slots_4.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[4].wakeup_ports[2].bits.uop.exc_cause
connect slots_4.io.wakeup_ports[2].bits.uop.exception, issue_slots[4].wakeup_ports[2].bits.uop.exception
connect slots_4.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[4].wakeup_ports[2].bits.uop.stale_pdst
connect slots_4.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[4].wakeup_ports[2].bits.uop.ppred_busy
connect slots_4.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[4].wakeup_ports[2].bits.uop.prs3_busy
connect slots_4.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[4].wakeup_ports[2].bits.uop.prs2_busy
connect slots_4.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[4].wakeup_ports[2].bits.uop.prs1_busy
connect slots_4.io.wakeup_ports[2].bits.uop.ppred, issue_slots[4].wakeup_ports[2].bits.uop.ppred
connect slots_4.io.wakeup_ports[2].bits.uop.prs3, issue_slots[4].wakeup_ports[2].bits.uop.prs3
connect slots_4.io.wakeup_ports[2].bits.uop.prs2, issue_slots[4].wakeup_ports[2].bits.uop.prs2
connect slots_4.io.wakeup_ports[2].bits.uop.prs1, issue_slots[4].wakeup_ports[2].bits.uop.prs1
connect slots_4.io.wakeup_ports[2].bits.uop.pdst, issue_slots[4].wakeup_ports[2].bits.uop.pdst
connect slots_4.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[4].wakeup_ports[2].bits.uop.rxq_idx
connect slots_4.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[4].wakeup_ports[2].bits.uop.stq_idx
connect slots_4.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[4].wakeup_ports[2].bits.uop.ldq_idx
connect slots_4.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[4].wakeup_ports[2].bits.uop.rob_idx
connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.vec
connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.wflags
connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.sqrt
connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.div
connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.fma
connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe
connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.toint
connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.fromint
connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut
connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn
connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.swap23
connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.swap12
connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.ren3
connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.ren2
connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.ren1
connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.wen
connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.ldst
connect slots_4.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[4].wakeup_ports[2].bits.uop.op2_sel
connect slots_4.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[4].wakeup_ports[2].bits.uop.op1_sel
connect slots_4.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[4].wakeup_ports[2].bits.uop.imm_packed
connect slots_4.io.wakeup_ports[2].bits.uop.pimm, issue_slots[4].wakeup_ports[2].bits.uop.pimm
connect slots_4.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[4].wakeup_ports[2].bits.uop.imm_sel
connect slots_4.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[4].wakeup_ports[2].bits.uop.imm_rename
connect slots_4.io.wakeup_ports[2].bits.uop.taken, issue_slots[4].wakeup_ports[2].bits.uop.taken
connect slots_4.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[4].wakeup_ports[2].bits.uop.pc_lob
connect slots_4.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[4].wakeup_ports[2].bits.uop.edge_inst
connect slots_4.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[4].wakeup_ports[2].bits.uop.ftq_idx
connect slots_4.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[4].wakeup_ports[2].bits.uop.is_mov
connect slots_4.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[4].wakeup_ports[2].bits.uop.is_rocc
connect slots_4.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[4].wakeup_ports[2].bits.uop.is_sys_pc2epc
connect slots_4.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[4].wakeup_ports[2].bits.uop.is_eret
connect slots_4.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[4].wakeup_ports[2].bits.uop.is_amo
connect slots_4.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[4].wakeup_ports[2].bits.uop.is_sfence
connect slots_4.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[4].wakeup_ports[2].bits.uop.is_fencei
connect slots_4.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[4].wakeup_ports[2].bits.uop.is_fence
connect slots_4.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[4].wakeup_ports[2].bits.uop.is_sfb
connect slots_4.io.wakeup_ports[2].bits.uop.br_type, issue_slots[4].wakeup_ports[2].bits.uop.br_type
connect slots_4.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[4].wakeup_ports[2].bits.uop.br_tag
connect slots_4.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[4].wakeup_ports[2].bits.uop.br_mask
connect slots_4.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[4].wakeup_ports[2].bits.uop.dis_col_sel
connect slots_4.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[4].wakeup_ports[2].bits.uop.iw_p3_bypass_hint
connect slots_4.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[4].wakeup_ports[2].bits.uop.iw_p2_bypass_hint
connect slots_4.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[4].wakeup_ports[2].bits.uop.iw_p1_bypass_hint
connect slots_4.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[4].wakeup_ports[2].bits.uop.iw_p2_speculative_child
connect slots_4.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[4].wakeup_ports[2].bits.uop.iw_p1_speculative_child
connect slots_4.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[4].wakeup_ports[2].bits.uop.iw_issued_partial_dgen
connect slots_4.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[4].wakeup_ports[2].bits.uop.iw_issued_partial_agen
connect slots_4.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[4].wakeup_ports[2].bits.uop.iw_issued
connect slots_4.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[4].wakeup_ports[2].bits.uop.fu_code[0]
connect slots_4.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[4].wakeup_ports[2].bits.uop.fu_code[1]
connect slots_4.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[4].wakeup_ports[2].bits.uop.fu_code[2]
connect slots_4.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[4].wakeup_ports[2].bits.uop.fu_code[3]
connect slots_4.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[4].wakeup_ports[2].bits.uop.fu_code[4]
connect slots_4.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[4].wakeup_ports[2].bits.uop.fu_code[5]
connect slots_4.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[4].wakeup_ports[2].bits.uop.fu_code[6]
connect slots_4.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[4].wakeup_ports[2].bits.uop.fu_code[7]
connect slots_4.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[4].wakeup_ports[2].bits.uop.fu_code[8]
connect slots_4.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[4].wakeup_ports[2].bits.uop.fu_code[9]
connect slots_4.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[4].wakeup_ports[2].bits.uop.iq_type[0]
connect slots_4.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[4].wakeup_ports[2].bits.uop.iq_type[1]
connect slots_4.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[4].wakeup_ports[2].bits.uop.iq_type[2]
connect slots_4.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[4].wakeup_ports[2].bits.uop.iq_type[3]
connect slots_4.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[4].wakeup_ports[2].bits.uop.debug_pc
connect slots_4.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[4].wakeup_ports[2].bits.uop.is_rvc
connect slots_4.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[4].wakeup_ports[2].bits.uop.debug_inst
connect slots_4.io.wakeup_ports[2].bits.uop.inst, issue_slots[4].wakeup_ports[2].bits.uop.inst
connect slots_4.io.wakeup_ports[2].valid, issue_slots[4].wakeup_ports[2].valid
connect slots_4.io.wakeup_ports[3].bits.rebusy, issue_slots[4].wakeup_ports[3].bits.rebusy
connect slots_4.io.wakeup_ports[3].bits.speculative_mask, issue_slots[4].wakeup_ports[3].bits.speculative_mask
connect slots_4.io.wakeup_ports[3].bits.bypassable, issue_slots[4].wakeup_ports[3].bits.bypassable
connect slots_4.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[4].wakeup_ports[3].bits.uop.debug_tsrc
connect slots_4.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[4].wakeup_ports[3].bits.uop.debug_fsrc
connect slots_4.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[4].wakeup_ports[3].bits.uop.bp_xcpt_if
connect slots_4.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[4].wakeup_ports[3].bits.uop.bp_debug_if
connect slots_4.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[4].wakeup_ports[3].bits.uop.xcpt_ma_if
connect slots_4.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[4].wakeup_ports[3].bits.uop.xcpt_ae_if
connect slots_4.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[4].wakeup_ports[3].bits.uop.xcpt_pf_if
connect slots_4.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[4].wakeup_ports[3].bits.uop.fp_typ
connect slots_4.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[4].wakeup_ports[3].bits.uop.fp_rm
connect slots_4.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[4].wakeup_ports[3].bits.uop.fp_val
connect slots_4.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[4].wakeup_ports[3].bits.uop.fcn_op
connect slots_4.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[4].wakeup_ports[3].bits.uop.fcn_dw
connect slots_4.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[4].wakeup_ports[3].bits.uop.frs3_en
connect slots_4.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[4].wakeup_ports[3].bits.uop.lrs2_rtype
connect slots_4.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[4].wakeup_ports[3].bits.uop.lrs1_rtype
connect slots_4.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[4].wakeup_ports[3].bits.uop.dst_rtype
connect slots_4.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[4].wakeup_ports[3].bits.uop.lrs3
connect slots_4.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[4].wakeup_ports[3].bits.uop.lrs2
connect slots_4.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[4].wakeup_ports[3].bits.uop.lrs1
connect slots_4.io.wakeup_ports[3].bits.uop.ldst, issue_slots[4].wakeup_ports[3].bits.uop.ldst
connect slots_4.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[4].wakeup_ports[3].bits.uop.ldst_is_rs1
connect slots_4.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[4].wakeup_ports[3].bits.uop.csr_cmd
connect slots_4.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[4].wakeup_ports[3].bits.uop.flush_on_commit
connect slots_4.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[4].wakeup_ports[3].bits.uop.is_unique
connect slots_4.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[4].wakeup_ports[3].bits.uop.uses_stq
connect slots_4.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[4].wakeup_ports[3].bits.uop.uses_ldq
connect slots_4.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[4].wakeup_ports[3].bits.uop.mem_signed
connect slots_4.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[4].wakeup_ports[3].bits.uop.mem_size
connect slots_4.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[4].wakeup_ports[3].bits.uop.mem_cmd
connect slots_4.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[4].wakeup_ports[3].bits.uop.exc_cause
connect slots_4.io.wakeup_ports[3].bits.uop.exception, issue_slots[4].wakeup_ports[3].bits.uop.exception
connect slots_4.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[4].wakeup_ports[3].bits.uop.stale_pdst
connect slots_4.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[4].wakeup_ports[3].bits.uop.ppred_busy
connect slots_4.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[4].wakeup_ports[3].bits.uop.prs3_busy
connect slots_4.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[4].wakeup_ports[3].bits.uop.prs2_busy
connect slots_4.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[4].wakeup_ports[3].bits.uop.prs1_busy
connect slots_4.io.wakeup_ports[3].bits.uop.ppred, issue_slots[4].wakeup_ports[3].bits.uop.ppred
connect slots_4.io.wakeup_ports[3].bits.uop.prs3, issue_slots[4].wakeup_ports[3].bits.uop.prs3
connect slots_4.io.wakeup_ports[3].bits.uop.prs2, issue_slots[4].wakeup_ports[3].bits.uop.prs2
connect slots_4.io.wakeup_ports[3].bits.uop.prs1, issue_slots[4].wakeup_ports[3].bits.uop.prs1
connect slots_4.io.wakeup_ports[3].bits.uop.pdst, issue_slots[4].wakeup_ports[3].bits.uop.pdst
connect slots_4.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[4].wakeup_ports[3].bits.uop.rxq_idx
connect slots_4.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[4].wakeup_ports[3].bits.uop.stq_idx
connect slots_4.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[4].wakeup_ports[3].bits.uop.ldq_idx
connect slots_4.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[4].wakeup_ports[3].bits.uop.rob_idx
connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.vec
connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.wflags
connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.sqrt
connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.div
connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.fma
connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe
connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.toint
connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.fromint
connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut
connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn
connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.swap23
connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.swap12
connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.ren3
connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.ren2
connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.ren1
connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.wen
connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.ldst
connect slots_4.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[4].wakeup_ports[3].bits.uop.op2_sel
connect slots_4.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[4].wakeup_ports[3].bits.uop.op1_sel
connect slots_4.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[4].wakeup_ports[3].bits.uop.imm_packed
connect slots_4.io.wakeup_ports[3].bits.uop.pimm, issue_slots[4].wakeup_ports[3].bits.uop.pimm
connect slots_4.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[4].wakeup_ports[3].bits.uop.imm_sel
connect slots_4.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[4].wakeup_ports[3].bits.uop.imm_rename
connect slots_4.io.wakeup_ports[3].bits.uop.taken, issue_slots[4].wakeup_ports[3].bits.uop.taken
connect slots_4.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[4].wakeup_ports[3].bits.uop.pc_lob
connect slots_4.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[4].wakeup_ports[3].bits.uop.edge_inst
connect slots_4.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[4].wakeup_ports[3].bits.uop.ftq_idx
connect slots_4.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[4].wakeup_ports[3].bits.uop.is_mov
connect slots_4.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[4].wakeup_ports[3].bits.uop.is_rocc
connect slots_4.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[4].wakeup_ports[3].bits.uop.is_sys_pc2epc
connect slots_4.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[4].wakeup_ports[3].bits.uop.is_eret
connect slots_4.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[4].wakeup_ports[3].bits.uop.is_amo
connect slots_4.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[4].wakeup_ports[3].bits.uop.is_sfence
connect slots_4.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[4].wakeup_ports[3].bits.uop.is_fencei
connect slots_4.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[4].wakeup_ports[3].bits.uop.is_fence
connect slots_4.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[4].wakeup_ports[3].bits.uop.is_sfb
connect slots_4.io.wakeup_ports[3].bits.uop.br_type, issue_slots[4].wakeup_ports[3].bits.uop.br_type
connect slots_4.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[4].wakeup_ports[3].bits.uop.br_tag
connect slots_4.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[4].wakeup_ports[3].bits.uop.br_mask
connect slots_4.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[4].wakeup_ports[3].bits.uop.dis_col_sel
connect slots_4.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[4].wakeup_ports[3].bits.uop.iw_p3_bypass_hint
connect slots_4.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[4].wakeup_ports[3].bits.uop.iw_p2_bypass_hint
connect slots_4.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[4].wakeup_ports[3].bits.uop.iw_p1_bypass_hint
connect slots_4.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[4].wakeup_ports[3].bits.uop.iw_p2_speculative_child
connect slots_4.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[4].wakeup_ports[3].bits.uop.iw_p1_speculative_child
connect slots_4.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[4].wakeup_ports[3].bits.uop.iw_issued_partial_dgen
connect slots_4.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[4].wakeup_ports[3].bits.uop.iw_issued_partial_agen
connect slots_4.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[4].wakeup_ports[3].bits.uop.iw_issued
connect slots_4.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[4].wakeup_ports[3].bits.uop.fu_code[0]
connect slots_4.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[4].wakeup_ports[3].bits.uop.fu_code[1]
connect slots_4.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[4].wakeup_ports[3].bits.uop.fu_code[2]
connect slots_4.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[4].wakeup_ports[3].bits.uop.fu_code[3]
connect slots_4.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[4].wakeup_ports[3].bits.uop.fu_code[4]
connect slots_4.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[4].wakeup_ports[3].bits.uop.fu_code[5]
connect slots_4.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[4].wakeup_ports[3].bits.uop.fu_code[6]
connect slots_4.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[4].wakeup_ports[3].bits.uop.fu_code[7]
connect slots_4.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[4].wakeup_ports[3].bits.uop.fu_code[8]
connect slots_4.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[4].wakeup_ports[3].bits.uop.fu_code[9]
connect slots_4.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[4].wakeup_ports[3].bits.uop.iq_type[0]
connect slots_4.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[4].wakeup_ports[3].bits.uop.iq_type[1]
connect slots_4.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[4].wakeup_ports[3].bits.uop.iq_type[2]
connect slots_4.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[4].wakeup_ports[3].bits.uop.iq_type[3]
connect slots_4.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[4].wakeup_ports[3].bits.uop.debug_pc
connect slots_4.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[4].wakeup_ports[3].bits.uop.is_rvc
connect slots_4.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[4].wakeup_ports[3].bits.uop.debug_inst
connect slots_4.io.wakeup_ports[3].bits.uop.inst, issue_slots[4].wakeup_ports[3].bits.uop.inst
connect slots_4.io.wakeup_ports[3].valid, issue_slots[4].wakeup_ports[3].valid
connect slots_4.io.squash_grant, issue_slots[4].squash_grant
connect slots_4.io.clear, issue_slots[4].clear
connect slots_4.io.kill, issue_slots[4].kill
connect slots_4.io.brupdate.b2.target_offset, issue_slots[4].brupdate.b2.target_offset
connect slots_4.io.brupdate.b2.jalr_target, issue_slots[4].brupdate.b2.jalr_target
connect slots_4.io.brupdate.b2.pc_sel, issue_slots[4].brupdate.b2.pc_sel
connect slots_4.io.brupdate.b2.cfi_type, issue_slots[4].brupdate.b2.cfi_type
connect slots_4.io.brupdate.b2.taken, issue_slots[4].brupdate.b2.taken
connect slots_4.io.brupdate.b2.mispredict, issue_slots[4].brupdate.b2.mispredict
connect slots_4.io.brupdate.b2.uop.debug_tsrc, issue_slots[4].brupdate.b2.uop.debug_tsrc
connect slots_4.io.brupdate.b2.uop.debug_fsrc, issue_slots[4].brupdate.b2.uop.debug_fsrc
connect slots_4.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[4].brupdate.b2.uop.bp_xcpt_if
connect slots_4.io.brupdate.b2.uop.bp_debug_if, issue_slots[4].brupdate.b2.uop.bp_debug_if
connect slots_4.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[4].brupdate.b2.uop.xcpt_ma_if
connect slots_4.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[4].brupdate.b2.uop.xcpt_ae_if
connect slots_4.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[4].brupdate.b2.uop.xcpt_pf_if
connect slots_4.io.brupdate.b2.uop.fp_typ, issue_slots[4].brupdate.b2.uop.fp_typ
connect slots_4.io.brupdate.b2.uop.fp_rm, issue_slots[4].brupdate.b2.uop.fp_rm
connect slots_4.io.brupdate.b2.uop.fp_val, issue_slots[4].brupdate.b2.uop.fp_val
connect slots_4.io.brupdate.b2.uop.fcn_op, issue_slots[4].brupdate.b2.uop.fcn_op
connect slots_4.io.brupdate.b2.uop.fcn_dw, issue_slots[4].brupdate.b2.uop.fcn_dw
connect slots_4.io.brupdate.b2.uop.frs3_en, issue_slots[4].brupdate.b2.uop.frs3_en
connect slots_4.io.brupdate.b2.uop.lrs2_rtype, issue_slots[4].brupdate.b2.uop.lrs2_rtype
connect slots_4.io.brupdate.b2.uop.lrs1_rtype, issue_slots[4].brupdate.b2.uop.lrs1_rtype
connect slots_4.io.brupdate.b2.uop.dst_rtype, issue_slots[4].brupdate.b2.uop.dst_rtype
connect slots_4.io.brupdate.b2.uop.lrs3, issue_slots[4].brupdate.b2.uop.lrs3
connect slots_4.io.brupdate.b2.uop.lrs2, issue_slots[4].brupdate.b2.uop.lrs2
connect slots_4.io.brupdate.b2.uop.lrs1, issue_slots[4].brupdate.b2.uop.lrs1
connect slots_4.io.brupdate.b2.uop.ldst, issue_slots[4].brupdate.b2.uop.ldst
connect slots_4.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[4].brupdate.b2.uop.ldst_is_rs1
connect slots_4.io.brupdate.b2.uop.csr_cmd, issue_slots[4].brupdate.b2.uop.csr_cmd
connect slots_4.io.brupdate.b2.uop.flush_on_commit, issue_slots[4].brupdate.b2.uop.flush_on_commit
connect slots_4.io.brupdate.b2.uop.is_unique, issue_slots[4].brupdate.b2.uop.is_unique
connect slots_4.io.brupdate.b2.uop.uses_stq, issue_slots[4].brupdate.b2.uop.uses_stq
connect slots_4.io.brupdate.b2.uop.uses_ldq, issue_slots[4].brupdate.b2.uop.uses_ldq
connect slots_4.io.brupdate.b2.uop.mem_signed, issue_slots[4].brupdate.b2.uop.mem_signed
connect slots_4.io.brupdate.b2.uop.mem_size, issue_slots[4].brupdate.b2.uop.mem_size
connect slots_4.io.brupdate.b2.uop.mem_cmd, issue_slots[4].brupdate.b2.uop.mem_cmd
connect slots_4.io.brupdate.b2.uop.exc_cause, issue_slots[4].brupdate.b2.uop.exc_cause
connect slots_4.io.brupdate.b2.uop.exception, issue_slots[4].brupdate.b2.uop.exception
connect slots_4.io.brupdate.b2.uop.stale_pdst, issue_slots[4].brupdate.b2.uop.stale_pdst
connect slots_4.io.brupdate.b2.uop.ppred_busy, issue_slots[4].brupdate.b2.uop.ppred_busy
connect slots_4.io.brupdate.b2.uop.prs3_busy, issue_slots[4].brupdate.b2.uop.prs3_busy
connect slots_4.io.brupdate.b2.uop.prs2_busy, issue_slots[4].brupdate.b2.uop.prs2_busy
connect slots_4.io.brupdate.b2.uop.prs1_busy, issue_slots[4].brupdate.b2.uop.prs1_busy
connect slots_4.io.brupdate.b2.uop.ppred, issue_slots[4].brupdate.b2.uop.ppred
connect slots_4.io.brupdate.b2.uop.prs3, issue_slots[4].brupdate.b2.uop.prs3
connect slots_4.io.brupdate.b2.uop.prs2, issue_slots[4].brupdate.b2.uop.prs2
connect slots_4.io.brupdate.b2.uop.prs1, issue_slots[4].brupdate.b2.uop.prs1
connect slots_4.io.brupdate.b2.uop.pdst, issue_slots[4].brupdate.b2.uop.pdst
connect slots_4.io.brupdate.b2.uop.rxq_idx, issue_slots[4].brupdate.b2.uop.rxq_idx
connect slots_4.io.brupdate.b2.uop.stq_idx, issue_slots[4].brupdate.b2.uop.stq_idx
connect slots_4.io.brupdate.b2.uop.ldq_idx, issue_slots[4].brupdate.b2.uop.ldq_idx
connect slots_4.io.brupdate.b2.uop.rob_idx, issue_slots[4].brupdate.b2.uop.rob_idx
connect slots_4.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[4].brupdate.b2.uop.fp_ctrl.vec
connect slots_4.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[4].brupdate.b2.uop.fp_ctrl.wflags
connect slots_4.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[4].brupdate.b2.uop.fp_ctrl.sqrt
connect slots_4.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[4].brupdate.b2.uop.fp_ctrl.div
connect slots_4.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[4].brupdate.b2.uop.fp_ctrl.fma
connect slots_4.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[4].brupdate.b2.uop.fp_ctrl.fastpipe
connect slots_4.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[4].brupdate.b2.uop.fp_ctrl.toint
connect slots_4.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[4].brupdate.b2.uop.fp_ctrl.fromint
connect slots_4.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[4].brupdate.b2.uop.fp_ctrl.typeTagOut
connect slots_4.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[4].brupdate.b2.uop.fp_ctrl.typeTagIn
connect slots_4.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[4].brupdate.b2.uop.fp_ctrl.swap23
connect slots_4.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[4].brupdate.b2.uop.fp_ctrl.swap12
connect slots_4.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[4].brupdate.b2.uop.fp_ctrl.ren3
connect slots_4.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[4].brupdate.b2.uop.fp_ctrl.ren2
connect slots_4.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[4].brupdate.b2.uop.fp_ctrl.ren1
connect slots_4.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[4].brupdate.b2.uop.fp_ctrl.wen
connect slots_4.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[4].brupdate.b2.uop.fp_ctrl.ldst
connect slots_4.io.brupdate.b2.uop.op2_sel, issue_slots[4].brupdate.b2.uop.op2_sel
connect slots_4.io.brupdate.b2.uop.op1_sel, issue_slots[4].brupdate.b2.uop.op1_sel
connect slots_4.io.brupdate.b2.uop.imm_packed, issue_slots[4].brupdate.b2.uop.imm_packed
connect slots_4.io.brupdate.b2.uop.pimm, issue_slots[4].brupdate.b2.uop.pimm
connect slots_4.io.brupdate.b2.uop.imm_sel, issue_slots[4].brupdate.b2.uop.imm_sel
connect slots_4.io.brupdate.b2.uop.imm_rename, issue_slots[4].brupdate.b2.uop.imm_rename
connect slots_4.io.brupdate.b2.uop.taken, issue_slots[4].brupdate.b2.uop.taken
connect slots_4.io.brupdate.b2.uop.pc_lob, issue_slots[4].brupdate.b2.uop.pc_lob
connect slots_4.io.brupdate.b2.uop.edge_inst, issue_slots[4].brupdate.b2.uop.edge_inst
connect slots_4.io.brupdate.b2.uop.ftq_idx, issue_slots[4].brupdate.b2.uop.ftq_idx
connect slots_4.io.brupdate.b2.uop.is_mov, issue_slots[4].brupdate.b2.uop.is_mov
connect slots_4.io.brupdate.b2.uop.is_rocc, issue_slots[4].brupdate.b2.uop.is_rocc
connect slots_4.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[4].brupdate.b2.uop.is_sys_pc2epc
connect slots_4.io.brupdate.b2.uop.is_eret, issue_slots[4].brupdate.b2.uop.is_eret
connect slots_4.io.brupdate.b2.uop.is_amo, issue_slots[4].brupdate.b2.uop.is_amo
connect slots_4.io.brupdate.b2.uop.is_sfence, issue_slots[4].brupdate.b2.uop.is_sfence
connect slots_4.io.brupdate.b2.uop.is_fencei, issue_slots[4].brupdate.b2.uop.is_fencei
connect slots_4.io.brupdate.b2.uop.is_fence, issue_slots[4].brupdate.b2.uop.is_fence
connect slots_4.io.brupdate.b2.uop.is_sfb, issue_slots[4].brupdate.b2.uop.is_sfb
connect slots_4.io.brupdate.b2.uop.br_type, issue_slots[4].brupdate.b2.uop.br_type
connect slots_4.io.brupdate.b2.uop.br_tag, issue_slots[4].brupdate.b2.uop.br_tag
connect slots_4.io.brupdate.b2.uop.br_mask, issue_slots[4].brupdate.b2.uop.br_mask
connect slots_4.io.brupdate.b2.uop.dis_col_sel, issue_slots[4].brupdate.b2.uop.dis_col_sel
connect slots_4.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[4].brupdate.b2.uop.iw_p3_bypass_hint
connect slots_4.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[4].brupdate.b2.uop.iw_p2_bypass_hint
connect slots_4.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[4].brupdate.b2.uop.iw_p1_bypass_hint
connect slots_4.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[4].brupdate.b2.uop.iw_p2_speculative_child
connect slots_4.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[4].brupdate.b2.uop.iw_p1_speculative_child
connect slots_4.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[4].brupdate.b2.uop.iw_issued_partial_dgen
connect slots_4.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[4].brupdate.b2.uop.iw_issued_partial_agen
connect slots_4.io.brupdate.b2.uop.iw_issued, issue_slots[4].brupdate.b2.uop.iw_issued
connect slots_4.io.brupdate.b2.uop.fu_code[0], issue_slots[4].brupdate.b2.uop.fu_code[0]
connect slots_4.io.brupdate.b2.uop.fu_code[1], issue_slots[4].brupdate.b2.uop.fu_code[1]
connect slots_4.io.brupdate.b2.uop.fu_code[2], issue_slots[4].brupdate.b2.uop.fu_code[2]
connect slots_4.io.brupdate.b2.uop.fu_code[3], issue_slots[4].brupdate.b2.uop.fu_code[3]
connect slots_4.io.brupdate.b2.uop.fu_code[4], issue_slots[4].brupdate.b2.uop.fu_code[4]
connect slots_4.io.brupdate.b2.uop.fu_code[5], issue_slots[4].brupdate.b2.uop.fu_code[5]
connect slots_4.io.brupdate.b2.uop.fu_code[6], issue_slots[4].brupdate.b2.uop.fu_code[6]
connect slots_4.io.brupdate.b2.uop.fu_code[7], issue_slots[4].brupdate.b2.uop.fu_code[7]
connect slots_4.io.brupdate.b2.uop.fu_code[8], issue_slots[4].brupdate.b2.uop.fu_code[8]
connect slots_4.io.brupdate.b2.uop.fu_code[9], issue_slots[4].brupdate.b2.uop.fu_code[9]
connect slots_4.io.brupdate.b2.uop.iq_type[0], issue_slots[4].brupdate.b2.uop.iq_type[0]
connect slots_4.io.brupdate.b2.uop.iq_type[1], issue_slots[4].brupdate.b2.uop.iq_type[1]
connect slots_4.io.brupdate.b2.uop.iq_type[2], issue_slots[4].brupdate.b2.uop.iq_type[2]
connect slots_4.io.brupdate.b2.uop.iq_type[3], issue_slots[4].brupdate.b2.uop.iq_type[3]
connect slots_4.io.brupdate.b2.uop.debug_pc, issue_slots[4].brupdate.b2.uop.debug_pc
connect slots_4.io.brupdate.b2.uop.is_rvc, issue_slots[4].brupdate.b2.uop.is_rvc
connect slots_4.io.brupdate.b2.uop.debug_inst, issue_slots[4].brupdate.b2.uop.debug_inst
connect slots_4.io.brupdate.b2.uop.inst, issue_slots[4].brupdate.b2.uop.inst
connect slots_4.io.brupdate.b1.mispredict_mask, issue_slots[4].brupdate.b1.mispredict_mask
connect slots_4.io.brupdate.b1.resolve_mask, issue_slots[4].brupdate.b1.resolve_mask
connect issue_slots[4].out_uop.debug_tsrc, slots_4.io.out_uop.debug_tsrc
connect issue_slots[4].out_uop.debug_fsrc, slots_4.io.out_uop.debug_fsrc
connect issue_slots[4].out_uop.bp_xcpt_if, slots_4.io.out_uop.bp_xcpt_if
connect issue_slots[4].out_uop.bp_debug_if, slots_4.io.out_uop.bp_debug_if
connect issue_slots[4].out_uop.xcpt_ma_if, slots_4.io.out_uop.xcpt_ma_if
connect issue_slots[4].out_uop.xcpt_ae_if, slots_4.io.out_uop.xcpt_ae_if
connect issue_slots[4].out_uop.xcpt_pf_if, slots_4.io.out_uop.xcpt_pf_if
connect issue_slots[4].out_uop.fp_typ, slots_4.io.out_uop.fp_typ
connect issue_slots[4].out_uop.fp_rm, slots_4.io.out_uop.fp_rm
connect issue_slots[4].out_uop.fp_val, slots_4.io.out_uop.fp_val
connect issue_slots[4].out_uop.fcn_op, slots_4.io.out_uop.fcn_op
connect issue_slots[4].out_uop.fcn_dw, slots_4.io.out_uop.fcn_dw
connect issue_slots[4].out_uop.frs3_en, slots_4.io.out_uop.frs3_en
connect issue_slots[4].out_uop.lrs2_rtype, slots_4.io.out_uop.lrs2_rtype
connect issue_slots[4].out_uop.lrs1_rtype, slots_4.io.out_uop.lrs1_rtype
connect issue_slots[4].out_uop.dst_rtype, slots_4.io.out_uop.dst_rtype
connect issue_slots[4].out_uop.lrs3, slots_4.io.out_uop.lrs3
connect issue_slots[4].out_uop.lrs2, slots_4.io.out_uop.lrs2
connect issue_slots[4].out_uop.lrs1, slots_4.io.out_uop.lrs1
connect issue_slots[4].out_uop.ldst, slots_4.io.out_uop.ldst
connect issue_slots[4].out_uop.ldst_is_rs1, slots_4.io.out_uop.ldst_is_rs1
connect issue_slots[4].out_uop.csr_cmd, slots_4.io.out_uop.csr_cmd
connect issue_slots[4].out_uop.flush_on_commit, slots_4.io.out_uop.flush_on_commit
connect issue_slots[4].out_uop.is_unique, slots_4.io.out_uop.is_unique
connect issue_slots[4].out_uop.uses_stq, slots_4.io.out_uop.uses_stq
connect issue_slots[4].out_uop.uses_ldq, slots_4.io.out_uop.uses_ldq
connect issue_slots[4].out_uop.mem_signed, slots_4.io.out_uop.mem_signed
connect issue_slots[4].out_uop.mem_size, slots_4.io.out_uop.mem_size
connect issue_slots[4].out_uop.mem_cmd, slots_4.io.out_uop.mem_cmd
connect issue_slots[4].out_uop.exc_cause, slots_4.io.out_uop.exc_cause
connect issue_slots[4].out_uop.exception, slots_4.io.out_uop.exception
connect issue_slots[4].out_uop.stale_pdst, slots_4.io.out_uop.stale_pdst
connect issue_slots[4].out_uop.ppred_busy, slots_4.io.out_uop.ppred_busy
connect issue_slots[4].out_uop.prs3_busy, slots_4.io.out_uop.prs3_busy
connect issue_slots[4].out_uop.prs2_busy, slots_4.io.out_uop.prs2_busy
connect issue_slots[4].out_uop.prs1_busy, slots_4.io.out_uop.prs1_busy
connect issue_slots[4].out_uop.ppred, slots_4.io.out_uop.ppred
connect issue_slots[4].out_uop.prs3, slots_4.io.out_uop.prs3
connect issue_slots[4].out_uop.prs2, slots_4.io.out_uop.prs2
connect issue_slots[4].out_uop.prs1, slots_4.io.out_uop.prs1
connect issue_slots[4].out_uop.pdst, slots_4.io.out_uop.pdst
connect issue_slots[4].out_uop.rxq_idx, slots_4.io.out_uop.rxq_idx
connect issue_slots[4].out_uop.stq_idx, slots_4.io.out_uop.stq_idx
connect issue_slots[4].out_uop.ldq_idx, slots_4.io.out_uop.ldq_idx
connect issue_slots[4].out_uop.rob_idx, slots_4.io.out_uop.rob_idx
connect issue_slots[4].out_uop.fp_ctrl.vec, slots_4.io.out_uop.fp_ctrl.vec
connect issue_slots[4].out_uop.fp_ctrl.wflags, slots_4.io.out_uop.fp_ctrl.wflags
connect issue_slots[4].out_uop.fp_ctrl.sqrt, slots_4.io.out_uop.fp_ctrl.sqrt
connect issue_slots[4].out_uop.fp_ctrl.div, slots_4.io.out_uop.fp_ctrl.div
connect issue_slots[4].out_uop.fp_ctrl.fma, slots_4.io.out_uop.fp_ctrl.fma
connect issue_slots[4].out_uop.fp_ctrl.fastpipe, slots_4.io.out_uop.fp_ctrl.fastpipe
connect issue_slots[4].out_uop.fp_ctrl.toint, slots_4.io.out_uop.fp_ctrl.toint
connect issue_slots[4].out_uop.fp_ctrl.fromint, slots_4.io.out_uop.fp_ctrl.fromint
connect issue_slots[4].out_uop.fp_ctrl.typeTagOut, slots_4.io.out_uop.fp_ctrl.typeTagOut
connect issue_slots[4].out_uop.fp_ctrl.typeTagIn, slots_4.io.out_uop.fp_ctrl.typeTagIn
connect issue_slots[4].out_uop.fp_ctrl.swap23, slots_4.io.out_uop.fp_ctrl.swap23
connect issue_slots[4].out_uop.fp_ctrl.swap12, slots_4.io.out_uop.fp_ctrl.swap12
connect issue_slots[4].out_uop.fp_ctrl.ren3, slots_4.io.out_uop.fp_ctrl.ren3
connect issue_slots[4].out_uop.fp_ctrl.ren2, slots_4.io.out_uop.fp_ctrl.ren2
connect issue_slots[4].out_uop.fp_ctrl.ren1, slots_4.io.out_uop.fp_ctrl.ren1
connect issue_slots[4].out_uop.fp_ctrl.wen, slots_4.io.out_uop.fp_ctrl.wen
connect issue_slots[4].out_uop.fp_ctrl.ldst, slots_4.io.out_uop.fp_ctrl.ldst
connect issue_slots[4].out_uop.op2_sel, slots_4.io.out_uop.op2_sel
connect issue_slots[4].out_uop.op1_sel, slots_4.io.out_uop.op1_sel
connect issue_slots[4].out_uop.imm_packed, slots_4.io.out_uop.imm_packed
connect issue_slots[4].out_uop.pimm, slots_4.io.out_uop.pimm
connect issue_slots[4].out_uop.imm_sel, slots_4.io.out_uop.imm_sel
connect issue_slots[4].out_uop.imm_rename, slots_4.io.out_uop.imm_rename
connect issue_slots[4].out_uop.taken, slots_4.io.out_uop.taken
connect issue_slots[4].out_uop.pc_lob, slots_4.io.out_uop.pc_lob
connect issue_slots[4].out_uop.edge_inst, slots_4.io.out_uop.edge_inst
connect issue_slots[4].out_uop.ftq_idx, slots_4.io.out_uop.ftq_idx
connect issue_slots[4].out_uop.is_mov, slots_4.io.out_uop.is_mov
connect issue_slots[4].out_uop.is_rocc, slots_4.io.out_uop.is_rocc
connect issue_slots[4].out_uop.is_sys_pc2epc, slots_4.io.out_uop.is_sys_pc2epc
connect issue_slots[4].out_uop.is_eret, slots_4.io.out_uop.is_eret
connect issue_slots[4].out_uop.is_amo, slots_4.io.out_uop.is_amo
connect issue_slots[4].out_uop.is_sfence, slots_4.io.out_uop.is_sfence
connect issue_slots[4].out_uop.is_fencei, slots_4.io.out_uop.is_fencei
connect issue_slots[4].out_uop.is_fence, slots_4.io.out_uop.is_fence
connect issue_slots[4].out_uop.is_sfb, slots_4.io.out_uop.is_sfb
connect issue_slots[4].out_uop.br_type, slots_4.io.out_uop.br_type
connect issue_slots[4].out_uop.br_tag, slots_4.io.out_uop.br_tag
connect issue_slots[4].out_uop.br_mask, slots_4.io.out_uop.br_mask
connect issue_slots[4].out_uop.dis_col_sel, slots_4.io.out_uop.dis_col_sel
connect issue_slots[4].out_uop.iw_p3_bypass_hint, slots_4.io.out_uop.iw_p3_bypass_hint
connect issue_slots[4].out_uop.iw_p2_bypass_hint, slots_4.io.out_uop.iw_p2_bypass_hint
connect issue_slots[4].out_uop.iw_p1_bypass_hint, slots_4.io.out_uop.iw_p1_bypass_hint
connect issue_slots[4].out_uop.iw_p2_speculative_child, slots_4.io.out_uop.iw_p2_speculative_child
connect issue_slots[4].out_uop.iw_p1_speculative_child, slots_4.io.out_uop.iw_p1_speculative_child
connect issue_slots[4].out_uop.iw_issued_partial_dgen, slots_4.io.out_uop.iw_issued_partial_dgen
connect issue_slots[4].out_uop.iw_issued_partial_agen, slots_4.io.out_uop.iw_issued_partial_agen
connect issue_slots[4].out_uop.iw_issued, slots_4.io.out_uop.iw_issued
connect issue_slots[4].out_uop.fu_code[0], slots_4.io.out_uop.fu_code[0]
connect issue_slots[4].out_uop.fu_code[1], slots_4.io.out_uop.fu_code[1]
connect issue_slots[4].out_uop.fu_code[2], slots_4.io.out_uop.fu_code[2]
connect issue_slots[4].out_uop.fu_code[3], slots_4.io.out_uop.fu_code[3]
connect issue_slots[4].out_uop.fu_code[4], slots_4.io.out_uop.fu_code[4]
connect issue_slots[4].out_uop.fu_code[5], slots_4.io.out_uop.fu_code[5]
connect issue_slots[4].out_uop.fu_code[6], slots_4.io.out_uop.fu_code[6]
connect issue_slots[4].out_uop.fu_code[7], slots_4.io.out_uop.fu_code[7]
connect issue_slots[4].out_uop.fu_code[8], slots_4.io.out_uop.fu_code[8]
connect issue_slots[4].out_uop.fu_code[9], slots_4.io.out_uop.fu_code[9]
connect issue_slots[4].out_uop.iq_type[0], slots_4.io.out_uop.iq_type[0]
connect issue_slots[4].out_uop.iq_type[1], slots_4.io.out_uop.iq_type[1]
connect issue_slots[4].out_uop.iq_type[2], slots_4.io.out_uop.iq_type[2]
connect issue_slots[4].out_uop.iq_type[3], slots_4.io.out_uop.iq_type[3]
connect issue_slots[4].out_uop.debug_pc, slots_4.io.out_uop.debug_pc
connect issue_slots[4].out_uop.is_rvc, slots_4.io.out_uop.is_rvc
connect issue_slots[4].out_uop.debug_inst, slots_4.io.out_uop.debug_inst
connect issue_slots[4].out_uop.inst, slots_4.io.out_uop.inst
connect slots_4.io.in_uop.bits.debug_tsrc, issue_slots[4].in_uop.bits.debug_tsrc
connect slots_4.io.in_uop.bits.debug_fsrc, issue_slots[4].in_uop.bits.debug_fsrc
connect slots_4.io.in_uop.bits.bp_xcpt_if, issue_slots[4].in_uop.bits.bp_xcpt_if
connect slots_4.io.in_uop.bits.bp_debug_if, issue_slots[4].in_uop.bits.bp_debug_if
connect slots_4.io.in_uop.bits.xcpt_ma_if, issue_slots[4].in_uop.bits.xcpt_ma_if
connect slots_4.io.in_uop.bits.xcpt_ae_if, issue_slots[4].in_uop.bits.xcpt_ae_if
connect slots_4.io.in_uop.bits.xcpt_pf_if, issue_slots[4].in_uop.bits.xcpt_pf_if
connect slots_4.io.in_uop.bits.fp_typ, issue_slots[4].in_uop.bits.fp_typ
connect slots_4.io.in_uop.bits.fp_rm, issue_slots[4].in_uop.bits.fp_rm
connect slots_4.io.in_uop.bits.fp_val, issue_slots[4].in_uop.bits.fp_val
connect slots_4.io.in_uop.bits.fcn_op, issue_slots[4].in_uop.bits.fcn_op
connect slots_4.io.in_uop.bits.fcn_dw, issue_slots[4].in_uop.bits.fcn_dw
connect slots_4.io.in_uop.bits.frs3_en, issue_slots[4].in_uop.bits.frs3_en
connect slots_4.io.in_uop.bits.lrs2_rtype, issue_slots[4].in_uop.bits.lrs2_rtype
connect slots_4.io.in_uop.bits.lrs1_rtype, issue_slots[4].in_uop.bits.lrs1_rtype
connect slots_4.io.in_uop.bits.dst_rtype, issue_slots[4].in_uop.bits.dst_rtype
connect slots_4.io.in_uop.bits.lrs3, issue_slots[4].in_uop.bits.lrs3
connect slots_4.io.in_uop.bits.lrs2, issue_slots[4].in_uop.bits.lrs2
connect slots_4.io.in_uop.bits.lrs1, issue_slots[4].in_uop.bits.lrs1
connect slots_4.io.in_uop.bits.ldst, issue_slots[4].in_uop.bits.ldst
connect slots_4.io.in_uop.bits.ldst_is_rs1, issue_slots[4].in_uop.bits.ldst_is_rs1
connect slots_4.io.in_uop.bits.csr_cmd, issue_slots[4].in_uop.bits.csr_cmd
connect slots_4.io.in_uop.bits.flush_on_commit, issue_slots[4].in_uop.bits.flush_on_commit
connect slots_4.io.in_uop.bits.is_unique, issue_slots[4].in_uop.bits.is_unique
connect slots_4.io.in_uop.bits.uses_stq, issue_slots[4].in_uop.bits.uses_stq
connect slots_4.io.in_uop.bits.uses_ldq, issue_slots[4].in_uop.bits.uses_ldq
connect slots_4.io.in_uop.bits.mem_signed, issue_slots[4].in_uop.bits.mem_signed
connect slots_4.io.in_uop.bits.mem_size, issue_slots[4].in_uop.bits.mem_size
connect slots_4.io.in_uop.bits.mem_cmd, issue_slots[4].in_uop.bits.mem_cmd
connect slots_4.io.in_uop.bits.exc_cause, issue_slots[4].in_uop.bits.exc_cause
connect slots_4.io.in_uop.bits.exception, issue_slots[4].in_uop.bits.exception
connect slots_4.io.in_uop.bits.stale_pdst, issue_slots[4].in_uop.bits.stale_pdst
connect slots_4.io.in_uop.bits.ppred_busy, issue_slots[4].in_uop.bits.ppred_busy
connect slots_4.io.in_uop.bits.prs3_busy, issue_slots[4].in_uop.bits.prs3_busy
connect slots_4.io.in_uop.bits.prs2_busy, issue_slots[4].in_uop.bits.prs2_busy
connect slots_4.io.in_uop.bits.prs1_busy, issue_slots[4].in_uop.bits.prs1_busy
connect slots_4.io.in_uop.bits.ppred, issue_slots[4].in_uop.bits.ppred
connect slots_4.io.in_uop.bits.prs3, issue_slots[4].in_uop.bits.prs3
connect slots_4.io.in_uop.bits.prs2, issue_slots[4].in_uop.bits.prs2
connect slots_4.io.in_uop.bits.prs1, issue_slots[4].in_uop.bits.prs1
connect slots_4.io.in_uop.bits.pdst, issue_slots[4].in_uop.bits.pdst
connect slots_4.io.in_uop.bits.rxq_idx, issue_slots[4].in_uop.bits.rxq_idx
connect slots_4.io.in_uop.bits.stq_idx, issue_slots[4].in_uop.bits.stq_idx
connect slots_4.io.in_uop.bits.ldq_idx, issue_slots[4].in_uop.bits.ldq_idx
connect slots_4.io.in_uop.bits.rob_idx, issue_slots[4].in_uop.bits.rob_idx
connect slots_4.io.in_uop.bits.fp_ctrl.vec, issue_slots[4].in_uop.bits.fp_ctrl.vec
connect slots_4.io.in_uop.bits.fp_ctrl.wflags, issue_slots[4].in_uop.bits.fp_ctrl.wflags
connect slots_4.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[4].in_uop.bits.fp_ctrl.sqrt
connect slots_4.io.in_uop.bits.fp_ctrl.div, issue_slots[4].in_uop.bits.fp_ctrl.div
connect slots_4.io.in_uop.bits.fp_ctrl.fma, issue_slots[4].in_uop.bits.fp_ctrl.fma
connect slots_4.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[4].in_uop.bits.fp_ctrl.fastpipe
connect slots_4.io.in_uop.bits.fp_ctrl.toint, issue_slots[4].in_uop.bits.fp_ctrl.toint
connect slots_4.io.in_uop.bits.fp_ctrl.fromint, issue_slots[4].in_uop.bits.fp_ctrl.fromint
connect slots_4.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[4].in_uop.bits.fp_ctrl.typeTagOut
connect slots_4.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[4].in_uop.bits.fp_ctrl.typeTagIn
connect slots_4.io.in_uop.bits.fp_ctrl.swap23, issue_slots[4].in_uop.bits.fp_ctrl.swap23
connect slots_4.io.in_uop.bits.fp_ctrl.swap12, issue_slots[4].in_uop.bits.fp_ctrl.swap12
connect slots_4.io.in_uop.bits.fp_ctrl.ren3, issue_slots[4].in_uop.bits.fp_ctrl.ren3
connect slots_4.io.in_uop.bits.fp_ctrl.ren2, issue_slots[4].in_uop.bits.fp_ctrl.ren2
connect slots_4.io.in_uop.bits.fp_ctrl.ren1, issue_slots[4].in_uop.bits.fp_ctrl.ren1
connect slots_4.io.in_uop.bits.fp_ctrl.wen, issue_slots[4].in_uop.bits.fp_ctrl.wen
connect slots_4.io.in_uop.bits.fp_ctrl.ldst, issue_slots[4].in_uop.bits.fp_ctrl.ldst
connect slots_4.io.in_uop.bits.op2_sel, issue_slots[4].in_uop.bits.op2_sel
connect slots_4.io.in_uop.bits.op1_sel, issue_slots[4].in_uop.bits.op1_sel
connect slots_4.io.in_uop.bits.imm_packed, issue_slots[4].in_uop.bits.imm_packed
connect slots_4.io.in_uop.bits.pimm, issue_slots[4].in_uop.bits.pimm
connect slots_4.io.in_uop.bits.imm_sel, issue_slots[4].in_uop.bits.imm_sel
connect slots_4.io.in_uop.bits.imm_rename, issue_slots[4].in_uop.bits.imm_rename
connect slots_4.io.in_uop.bits.taken, issue_slots[4].in_uop.bits.taken
connect slots_4.io.in_uop.bits.pc_lob, issue_slots[4].in_uop.bits.pc_lob
connect slots_4.io.in_uop.bits.edge_inst, issue_slots[4].in_uop.bits.edge_inst
connect slots_4.io.in_uop.bits.ftq_idx, issue_slots[4].in_uop.bits.ftq_idx
connect slots_4.io.in_uop.bits.is_mov, issue_slots[4].in_uop.bits.is_mov
connect slots_4.io.in_uop.bits.is_rocc, issue_slots[4].in_uop.bits.is_rocc
connect slots_4.io.in_uop.bits.is_sys_pc2epc, issue_slots[4].in_uop.bits.is_sys_pc2epc
connect slots_4.io.in_uop.bits.is_eret, issue_slots[4].in_uop.bits.is_eret
connect slots_4.io.in_uop.bits.is_amo, issue_slots[4].in_uop.bits.is_amo
connect slots_4.io.in_uop.bits.is_sfence, issue_slots[4].in_uop.bits.is_sfence
connect slots_4.io.in_uop.bits.is_fencei, issue_slots[4].in_uop.bits.is_fencei
connect slots_4.io.in_uop.bits.is_fence, issue_slots[4].in_uop.bits.is_fence
connect slots_4.io.in_uop.bits.is_sfb, issue_slots[4].in_uop.bits.is_sfb
connect slots_4.io.in_uop.bits.br_type, issue_slots[4].in_uop.bits.br_type
connect slots_4.io.in_uop.bits.br_tag, issue_slots[4].in_uop.bits.br_tag
connect slots_4.io.in_uop.bits.br_mask, issue_slots[4].in_uop.bits.br_mask
connect slots_4.io.in_uop.bits.dis_col_sel, issue_slots[4].in_uop.bits.dis_col_sel
connect slots_4.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[4].in_uop.bits.iw_p3_bypass_hint
connect slots_4.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[4].in_uop.bits.iw_p2_bypass_hint
connect slots_4.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[4].in_uop.bits.iw_p1_bypass_hint
connect slots_4.io.in_uop.bits.iw_p2_speculative_child, issue_slots[4].in_uop.bits.iw_p2_speculative_child
connect slots_4.io.in_uop.bits.iw_p1_speculative_child, issue_slots[4].in_uop.bits.iw_p1_speculative_child
connect slots_4.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[4].in_uop.bits.iw_issued_partial_dgen
connect slots_4.io.in_uop.bits.iw_issued_partial_agen, issue_slots[4].in_uop.bits.iw_issued_partial_agen
connect slots_4.io.in_uop.bits.iw_issued, issue_slots[4].in_uop.bits.iw_issued
connect slots_4.io.in_uop.bits.fu_code[0], issue_slots[4].in_uop.bits.fu_code[0]
connect slots_4.io.in_uop.bits.fu_code[1], issue_slots[4].in_uop.bits.fu_code[1]
connect slots_4.io.in_uop.bits.fu_code[2], issue_slots[4].in_uop.bits.fu_code[2]
connect slots_4.io.in_uop.bits.fu_code[3], issue_slots[4].in_uop.bits.fu_code[3]
connect slots_4.io.in_uop.bits.fu_code[4], issue_slots[4].in_uop.bits.fu_code[4]
connect slots_4.io.in_uop.bits.fu_code[5], issue_slots[4].in_uop.bits.fu_code[5]
connect slots_4.io.in_uop.bits.fu_code[6], issue_slots[4].in_uop.bits.fu_code[6]
connect slots_4.io.in_uop.bits.fu_code[7], issue_slots[4].in_uop.bits.fu_code[7]
connect slots_4.io.in_uop.bits.fu_code[8], issue_slots[4].in_uop.bits.fu_code[8]
connect slots_4.io.in_uop.bits.fu_code[9], issue_slots[4].in_uop.bits.fu_code[9]
connect slots_4.io.in_uop.bits.iq_type[0], issue_slots[4].in_uop.bits.iq_type[0]
connect slots_4.io.in_uop.bits.iq_type[1], issue_slots[4].in_uop.bits.iq_type[1]
connect slots_4.io.in_uop.bits.iq_type[2], issue_slots[4].in_uop.bits.iq_type[2]
connect slots_4.io.in_uop.bits.iq_type[3], issue_slots[4].in_uop.bits.iq_type[3]
connect slots_4.io.in_uop.bits.debug_pc, issue_slots[4].in_uop.bits.debug_pc
connect slots_4.io.in_uop.bits.is_rvc, issue_slots[4].in_uop.bits.is_rvc
connect slots_4.io.in_uop.bits.debug_inst, issue_slots[4].in_uop.bits.debug_inst
connect slots_4.io.in_uop.bits.inst, issue_slots[4].in_uop.bits.inst
connect slots_4.io.in_uop.valid, issue_slots[4].in_uop.valid
connect issue_slots[4].iss_uop.debug_tsrc, slots_4.io.iss_uop.debug_tsrc
connect issue_slots[4].iss_uop.debug_fsrc, slots_4.io.iss_uop.debug_fsrc
connect issue_slots[4].iss_uop.bp_xcpt_if, slots_4.io.iss_uop.bp_xcpt_if
connect issue_slots[4].iss_uop.bp_debug_if, slots_4.io.iss_uop.bp_debug_if
connect issue_slots[4].iss_uop.xcpt_ma_if, slots_4.io.iss_uop.xcpt_ma_if
connect issue_slots[4].iss_uop.xcpt_ae_if, slots_4.io.iss_uop.xcpt_ae_if
connect issue_slots[4].iss_uop.xcpt_pf_if, slots_4.io.iss_uop.xcpt_pf_if
connect issue_slots[4].iss_uop.fp_typ, slots_4.io.iss_uop.fp_typ
connect issue_slots[4].iss_uop.fp_rm, slots_4.io.iss_uop.fp_rm
connect issue_slots[4].iss_uop.fp_val, slots_4.io.iss_uop.fp_val
connect issue_slots[4].iss_uop.fcn_op, slots_4.io.iss_uop.fcn_op
connect issue_slots[4].iss_uop.fcn_dw, slots_4.io.iss_uop.fcn_dw
connect issue_slots[4].iss_uop.frs3_en, slots_4.io.iss_uop.frs3_en
connect issue_slots[4].iss_uop.lrs2_rtype, slots_4.io.iss_uop.lrs2_rtype
connect issue_slots[4].iss_uop.lrs1_rtype, slots_4.io.iss_uop.lrs1_rtype
connect issue_slots[4].iss_uop.dst_rtype, slots_4.io.iss_uop.dst_rtype
connect issue_slots[4].iss_uop.lrs3, slots_4.io.iss_uop.lrs3
connect issue_slots[4].iss_uop.lrs2, slots_4.io.iss_uop.lrs2
connect issue_slots[4].iss_uop.lrs1, slots_4.io.iss_uop.lrs1
connect issue_slots[4].iss_uop.ldst, slots_4.io.iss_uop.ldst
connect issue_slots[4].iss_uop.ldst_is_rs1, slots_4.io.iss_uop.ldst_is_rs1
connect issue_slots[4].iss_uop.csr_cmd, slots_4.io.iss_uop.csr_cmd
connect issue_slots[4].iss_uop.flush_on_commit, slots_4.io.iss_uop.flush_on_commit
connect issue_slots[4].iss_uop.is_unique, slots_4.io.iss_uop.is_unique
connect issue_slots[4].iss_uop.uses_stq, slots_4.io.iss_uop.uses_stq
connect issue_slots[4].iss_uop.uses_ldq, slots_4.io.iss_uop.uses_ldq
connect issue_slots[4].iss_uop.mem_signed, slots_4.io.iss_uop.mem_signed
connect issue_slots[4].iss_uop.mem_size, slots_4.io.iss_uop.mem_size
connect issue_slots[4].iss_uop.mem_cmd, slots_4.io.iss_uop.mem_cmd
connect issue_slots[4].iss_uop.exc_cause, slots_4.io.iss_uop.exc_cause
connect issue_slots[4].iss_uop.exception, slots_4.io.iss_uop.exception
connect issue_slots[4].iss_uop.stale_pdst, slots_4.io.iss_uop.stale_pdst
connect issue_slots[4].iss_uop.ppred_busy, slots_4.io.iss_uop.ppred_busy
connect issue_slots[4].iss_uop.prs3_busy, slots_4.io.iss_uop.prs3_busy
connect issue_slots[4].iss_uop.prs2_busy, slots_4.io.iss_uop.prs2_busy
connect issue_slots[4].iss_uop.prs1_busy, slots_4.io.iss_uop.prs1_busy
connect issue_slots[4].iss_uop.ppred, slots_4.io.iss_uop.ppred
connect issue_slots[4].iss_uop.prs3, slots_4.io.iss_uop.prs3
connect issue_slots[4].iss_uop.prs2, slots_4.io.iss_uop.prs2
connect issue_slots[4].iss_uop.prs1, slots_4.io.iss_uop.prs1
connect issue_slots[4].iss_uop.pdst, slots_4.io.iss_uop.pdst
connect issue_slots[4].iss_uop.rxq_idx, slots_4.io.iss_uop.rxq_idx
connect issue_slots[4].iss_uop.stq_idx, slots_4.io.iss_uop.stq_idx
connect issue_slots[4].iss_uop.ldq_idx, slots_4.io.iss_uop.ldq_idx
connect issue_slots[4].iss_uop.rob_idx, slots_4.io.iss_uop.rob_idx
connect issue_slots[4].iss_uop.fp_ctrl.vec, slots_4.io.iss_uop.fp_ctrl.vec
connect issue_slots[4].iss_uop.fp_ctrl.wflags, slots_4.io.iss_uop.fp_ctrl.wflags
connect issue_slots[4].iss_uop.fp_ctrl.sqrt, slots_4.io.iss_uop.fp_ctrl.sqrt
connect issue_slots[4].iss_uop.fp_ctrl.div, slots_4.io.iss_uop.fp_ctrl.div
connect issue_slots[4].iss_uop.fp_ctrl.fma, slots_4.io.iss_uop.fp_ctrl.fma
connect issue_slots[4].iss_uop.fp_ctrl.fastpipe, slots_4.io.iss_uop.fp_ctrl.fastpipe
connect issue_slots[4].iss_uop.fp_ctrl.toint, slots_4.io.iss_uop.fp_ctrl.toint
connect issue_slots[4].iss_uop.fp_ctrl.fromint, slots_4.io.iss_uop.fp_ctrl.fromint
connect issue_slots[4].iss_uop.fp_ctrl.typeTagOut, slots_4.io.iss_uop.fp_ctrl.typeTagOut
connect issue_slots[4].iss_uop.fp_ctrl.typeTagIn, slots_4.io.iss_uop.fp_ctrl.typeTagIn
connect issue_slots[4].iss_uop.fp_ctrl.swap23, slots_4.io.iss_uop.fp_ctrl.swap23
connect issue_slots[4].iss_uop.fp_ctrl.swap12, slots_4.io.iss_uop.fp_ctrl.swap12
connect issue_slots[4].iss_uop.fp_ctrl.ren3, slots_4.io.iss_uop.fp_ctrl.ren3
connect issue_slots[4].iss_uop.fp_ctrl.ren2, slots_4.io.iss_uop.fp_ctrl.ren2
connect issue_slots[4].iss_uop.fp_ctrl.ren1, slots_4.io.iss_uop.fp_ctrl.ren1
connect issue_slots[4].iss_uop.fp_ctrl.wen, slots_4.io.iss_uop.fp_ctrl.wen
connect issue_slots[4].iss_uop.fp_ctrl.ldst, slots_4.io.iss_uop.fp_ctrl.ldst
connect issue_slots[4].iss_uop.op2_sel, slots_4.io.iss_uop.op2_sel
connect issue_slots[4].iss_uop.op1_sel, slots_4.io.iss_uop.op1_sel
connect issue_slots[4].iss_uop.imm_packed, slots_4.io.iss_uop.imm_packed
connect issue_slots[4].iss_uop.pimm, slots_4.io.iss_uop.pimm
connect issue_slots[4].iss_uop.imm_sel, slots_4.io.iss_uop.imm_sel
connect issue_slots[4].iss_uop.imm_rename, slots_4.io.iss_uop.imm_rename
connect issue_slots[4].iss_uop.taken, slots_4.io.iss_uop.taken
connect issue_slots[4].iss_uop.pc_lob, slots_4.io.iss_uop.pc_lob
connect issue_slots[4].iss_uop.edge_inst, slots_4.io.iss_uop.edge_inst
connect issue_slots[4].iss_uop.ftq_idx, slots_4.io.iss_uop.ftq_idx
connect issue_slots[4].iss_uop.is_mov, slots_4.io.iss_uop.is_mov
connect issue_slots[4].iss_uop.is_rocc, slots_4.io.iss_uop.is_rocc
connect issue_slots[4].iss_uop.is_sys_pc2epc, slots_4.io.iss_uop.is_sys_pc2epc
connect issue_slots[4].iss_uop.is_eret, slots_4.io.iss_uop.is_eret
connect issue_slots[4].iss_uop.is_amo, slots_4.io.iss_uop.is_amo
connect issue_slots[4].iss_uop.is_sfence, slots_4.io.iss_uop.is_sfence
connect issue_slots[4].iss_uop.is_fencei, slots_4.io.iss_uop.is_fencei
connect issue_slots[4].iss_uop.is_fence, slots_4.io.iss_uop.is_fence
connect issue_slots[4].iss_uop.is_sfb, slots_4.io.iss_uop.is_sfb
connect issue_slots[4].iss_uop.br_type, slots_4.io.iss_uop.br_type
connect issue_slots[4].iss_uop.br_tag, slots_4.io.iss_uop.br_tag
connect issue_slots[4].iss_uop.br_mask, slots_4.io.iss_uop.br_mask
connect issue_slots[4].iss_uop.dis_col_sel, slots_4.io.iss_uop.dis_col_sel
connect issue_slots[4].iss_uop.iw_p3_bypass_hint, slots_4.io.iss_uop.iw_p3_bypass_hint
connect issue_slots[4].iss_uop.iw_p2_bypass_hint, slots_4.io.iss_uop.iw_p2_bypass_hint
connect issue_slots[4].iss_uop.iw_p1_bypass_hint, slots_4.io.iss_uop.iw_p1_bypass_hint
connect issue_slots[4].iss_uop.iw_p2_speculative_child, slots_4.io.iss_uop.iw_p2_speculative_child
connect issue_slots[4].iss_uop.iw_p1_speculative_child, slots_4.io.iss_uop.iw_p1_speculative_child
connect issue_slots[4].iss_uop.iw_issued_partial_dgen, slots_4.io.iss_uop.iw_issued_partial_dgen
connect issue_slots[4].iss_uop.iw_issued_partial_agen, slots_4.io.iss_uop.iw_issued_partial_agen
connect issue_slots[4].iss_uop.iw_issued, slots_4.io.iss_uop.iw_issued
connect issue_slots[4].iss_uop.fu_code[0], slots_4.io.iss_uop.fu_code[0]
connect issue_slots[4].iss_uop.fu_code[1], slots_4.io.iss_uop.fu_code[1]
connect issue_slots[4].iss_uop.fu_code[2], slots_4.io.iss_uop.fu_code[2]
connect issue_slots[4].iss_uop.fu_code[3], slots_4.io.iss_uop.fu_code[3]
connect issue_slots[4].iss_uop.fu_code[4], slots_4.io.iss_uop.fu_code[4]
connect issue_slots[4].iss_uop.fu_code[5], slots_4.io.iss_uop.fu_code[5]
connect issue_slots[4].iss_uop.fu_code[6], slots_4.io.iss_uop.fu_code[6]
connect issue_slots[4].iss_uop.fu_code[7], slots_4.io.iss_uop.fu_code[7]
connect issue_slots[4].iss_uop.fu_code[8], slots_4.io.iss_uop.fu_code[8]
connect issue_slots[4].iss_uop.fu_code[9], slots_4.io.iss_uop.fu_code[9]
connect issue_slots[4].iss_uop.iq_type[0], slots_4.io.iss_uop.iq_type[0]
connect issue_slots[4].iss_uop.iq_type[1], slots_4.io.iss_uop.iq_type[1]
connect issue_slots[4].iss_uop.iq_type[2], slots_4.io.iss_uop.iq_type[2]
connect issue_slots[4].iss_uop.iq_type[3], slots_4.io.iss_uop.iq_type[3]
connect issue_slots[4].iss_uop.debug_pc, slots_4.io.iss_uop.debug_pc
connect issue_slots[4].iss_uop.is_rvc, slots_4.io.iss_uop.is_rvc
connect issue_slots[4].iss_uop.debug_inst, slots_4.io.iss_uop.debug_inst
connect issue_slots[4].iss_uop.inst, slots_4.io.iss_uop.inst
connect slots_4.io.grant, issue_slots[4].grant
connect issue_slots[4].request, slots_4.io.request
connect issue_slots[4].will_be_valid, slots_4.io.will_be_valid
connect issue_slots[4].valid, slots_4.io.valid
connect slots_5.io.child_rebusys, issue_slots[5].child_rebusys
connect slots_5.io.pred_wakeup_port.bits, issue_slots[5].pred_wakeup_port.bits
connect slots_5.io.pred_wakeup_port.valid, issue_slots[5].pred_wakeup_port.valid
connect slots_5.io.wakeup_ports[0].bits.rebusy, issue_slots[5].wakeup_ports[0].bits.rebusy
connect slots_5.io.wakeup_ports[0].bits.speculative_mask, issue_slots[5].wakeup_ports[0].bits.speculative_mask
connect slots_5.io.wakeup_ports[0].bits.bypassable, issue_slots[5].wakeup_ports[0].bits.bypassable
connect slots_5.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[5].wakeup_ports[0].bits.uop.debug_tsrc
connect slots_5.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[5].wakeup_ports[0].bits.uop.debug_fsrc
connect slots_5.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[5].wakeup_ports[0].bits.uop.bp_xcpt_if
connect slots_5.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[5].wakeup_ports[0].bits.uop.bp_debug_if
connect slots_5.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[5].wakeup_ports[0].bits.uop.xcpt_ma_if
connect slots_5.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[5].wakeup_ports[0].bits.uop.xcpt_ae_if
connect slots_5.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[5].wakeup_ports[0].bits.uop.xcpt_pf_if
connect slots_5.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[5].wakeup_ports[0].bits.uop.fp_typ
connect slots_5.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[5].wakeup_ports[0].bits.uop.fp_rm
connect slots_5.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[5].wakeup_ports[0].bits.uop.fp_val
connect slots_5.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[5].wakeup_ports[0].bits.uop.fcn_op
connect slots_5.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[5].wakeup_ports[0].bits.uop.fcn_dw
connect slots_5.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[5].wakeup_ports[0].bits.uop.frs3_en
connect slots_5.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[5].wakeup_ports[0].bits.uop.lrs2_rtype
connect slots_5.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[5].wakeup_ports[0].bits.uop.lrs1_rtype
connect slots_5.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[5].wakeup_ports[0].bits.uop.dst_rtype
connect slots_5.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[5].wakeup_ports[0].bits.uop.lrs3
connect slots_5.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[5].wakeup_ports[0].bits.uop.lrs2
connect slots_5.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[5].wakeup_ports[0].bits.uop.lrs1
connect slots_5.io.wakeup_ports[0].bits.uop.ldst, issue_slots[5].wakeup_ports[0].bits.uop.ldst
connect slots_5.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[5].wakeup_ports[0].bits.uop.ldst_is_rs1
connect slots_5.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[5].wakeup_ports[0].bits.uop.csr_cmd
connect slots_5.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[5].wakeup_ports[0].bits.uop.flush_on_commit
connect slots_5.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[5].wakeup_ports[0].bits.uop.is_unique
connect slots_5.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[5].wakeup_ports[0].bits.uop.uses_stq
connect slots_5.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[5].wakeup_ports[0].bits.uop.uses_ldq
connect slots_5.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[5].wakeup_ports[0].bits.uop.mem_signed
connect slots_5.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[5].wakeup_ports[0].bits.uop.mem_size
connect slots_5.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[5].wakeup_ports[0].bits.uop.mem_cmd
connect slots_5.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[5].wakeup_ports[0].bits.uop.exc_cause
connect slots_5.io.wakeup_ports[0].bits.uop.exception, issue_slots[5].wakeup_ports[0].bits.uop.exception
connect slots_5.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[5].wakeup_ports[0].bits.uop.stale_pdst
connect slots_5.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[5].wakeup_ports[0].bits.uop.ppred_busy
connect slots_5.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[5].wakeup_ports[0].bits.uop.prs3_busy
connect slots_5.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[5].wakeup_ports[0].bits.uop.prs2_busy
connect slots_5.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[5].wakeup_ports[0].bits.uop.prs1_busy
connect slots_5.io.wakeup_ports[0].bits.uop.ppred, issue_slots[5].wakeup_ports[0].bits.uop.ppred
connect slots_5.io.wakeup_ports[0].bits.uop.prs3, issue_slots[5].wakeup_ports[0].bits.uop.prs3
connect slots_5.io.wakeup_ports[0].bits.uop.prs2, issue_slots[5].wakeup_ports[0].bits.uop.prs2
connect slots_5.io.wakeup_ports[0].bits.uop.prs1, issue_slots[5].wakeup_ports[0].bits.uop.prs1
connect slots_5.io.wakeup_ports[0].bits.uop.pdst, issue_slots[5].wakeup_ports[0].bits.uop.pdst
connect slots_5.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[5].wakeup_ports[0].bits.uop.rxq_idx
connect slots_5.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[5].wakeup_ports[0].bits.uop.stq_idx
connect slots_5.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[5].wakeup_ports[0].bits.uop.ldq_idx
connect slots_5.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[5].wakeup_ports[0].bits.uop.rob_idx
connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.vec
connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.wflags
connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.sqrt
connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.div
connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.fma
connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe
connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.toint
connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.fromint
connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut
connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn
connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.swap23
connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.swap12
connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.ren3
connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.ren2
connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.ren1
connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.wen
connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.ldst
connect slots_5.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[5].wakeup_ports[0].bits.uop.op2_sel
connect slots_5.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[5].wakeup_ports[0].bits.uop.op1_sel
connect slots_5.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[5].wakeup_ports[0].bits.uop.imm_packed
connect slots_5.io.wakeup_ports[0].bits.uop.pimm, issue_slots[5].wakeup_ports[0].bits.uop.pimm
connect slots_5.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[5].wakeup_ports[0].bits.uop.imm_sel
connect slots_5.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[5].wakeup_ports[0].bits.uop.imm_rename
connect slots_5.io.wakeup_ports[0].bits.uop.taken, issue_slots[5].wakeup_ports[0].bits.uop.taken
connect slots_5.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[5].wakeup_ports[0].bits.uop.pc_lob
connect slots_5.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[5].wakeup_ports[0].bits.uop.edge_inst
connect slots_5.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[5].wakeup_ports[0].bits.uop.ftq_idx
connect slots_5.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[5].wakeup_ports[0].bits.uop.is_mov
connect slots_5.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[5].wakeup_ports[0].bits.uop.is_rocc
connect slots_5.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[5].wakeup_ports[0].bits.uop.is_sys_pc2epc
connect slots_5.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[5].wakeup_ports[0].bits.uop.is_eret
connect slots_5.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[5].wakeup_ports[0].bits.uop.is_amo
connect slots_5.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[5].wakeup_ports[0].bits.uop.is_sfence
connect slots_5.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[5].wakeup_ports[0].bits.uop.is_fencei
connect slots_5.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[5].wakeup_ports[0].bits.uop.is_fence
connect slots_5.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[5].wakeup_ports[0].bits.uop.is_sfb
connect slots_5.io.wakeup_ports[0].bits.uop.br_type, issue_slots[5].wakeup_ports[0].bits.uop.br_type
connect slots_5.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[5].wakeup_ports[0].bits.uop.br_tag
connect slots_5.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[5].wakeup_ports[0].bits.uop.br_mask
connect slots_5.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[5].wakeup_ports[0].bits.uop.dis_col_sel
connect slots_5.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[5].wakeup_ports[0].bits.uop.iw_p3_bypass_hint
connect slots_5.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[5].wakeup_ports[0].bits.uop.iw_p2_bypass_hint
connect slots_5.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[5].wakeup_ports[0].bits.uop.iw_p1_bypass_hint
connect slots_5.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[5].wakeup_ports[0].bits.uop.iw_p2_speculative_child
connect slots_5.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[5].wakeup_ports[0].bits.uop.iw_p1_speculative_child
connect slots_5.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[5].wakeup_ports[0].bits.uop.iw_issued_partial_dgen
connect slots_5.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[5].wakeup_ports[0].bits.uop.iw_issued_partial_agen
connect slots_5.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[5].wakeup_ports[0].bits.uop.iw_issued
connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[0]
connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[1]
connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[2]
connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[3]
connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[4]
connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[5]
connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[6]
connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[7]
connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[8]
connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[9]
connect slots_5.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[5].wakeup_ports[0].bits.uop.iq_type[0]
connect slots_5.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[5].wakeup_ports[0].bits.uop.iq_type[1]
connect slots_5.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[5].wakeup_ports[0].bits.uop.iq_type[2]
connect slots_5.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[5].wakeup_ports[0].bits.uop.iq_type[3]
connect slots_5.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[5].wakeup_ports[0].bits.uop.debug_pc
connect slots_5.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[5].wakeup_ports[0].bits.uop.is_rvc
connect slots_5.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[5].wakeup_ports[0].bits.uop.debug_inst
connect slots_5.io.wakeup_ports[0].bits.uop.inst, issue_slots[5].wakeup_ports[0].bits.uop.inst
connect slots_5.io.wakeup_ports[0].valid, issue_slots[5].wakeup_ports[0].valid
connect slots_5.io.wakeup_ports[1].bits.rebusy, issue_slots[5].wakeup_ports[1].bits.rebusy
connect slots_5.io.wakeup_ports[1].bits.speculative_mask, issue_slots[5].wakeup_ports[1].bits.speculative_mask
connect slots_5.io.wakeup_ports[1].bits.bypassable, issue_slots[5].wakeup_ports[1].bits.bypassable
connect slots_5.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[5].wakeup_ports[1].bits.uop.debug_tsrc
connect slots_5.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[5].wakeup_ports[1].bits.uop.debug_fsrc
connect slots_5.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[5].wakeup_ports[1].bits.uop.bp_xcpt_if
connect slots_5.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[5].wakeup_ports[1].bits.uop.bp_debug_if
connect slots_5.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[5].wakeup_ports[1].bits.uop.xcpt_ma_if
connect slots_5.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[5].wakeup_ports[1].bits.uop.xcpt_ae_if
connect slots_5.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[5].wakeup_ports[1].bits.uop.xcpt_pf_if
connect slots_5.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[5].wakeup_ports[1].bits.uop.fp_typ
connect slots_5.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[5].wakeup_ports[1].bits.uop.fp_rm
connect slots_5.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[5].wakeup_ports[1].bits.uop.fp_val
connect slots_5.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[5].wakeup_ports[1].bits.uop.fcn_op
connect slots_5.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[5].wakeup_ports[1].bits.uop.fcn_dw
connect slots_5.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[5].wakeup_ports[1].bits.uop.frs3_en
connect slots_5.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[5].wakeup_ports[1].bits.uop.lrs2_rtype
connect slots_5.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[5].wakeup_ports[1].bits.uop.lrs1_rtype
connect slots_5.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[5].wakeup_ports[1].bits.uop.dst_rtype
connect slots_5.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[5].wakeup_ports[1].bits.uop.lrs3
connect slots_5.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[5].wakeup_ports[1].bits.uop.lrs2
connect slots_5.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[5].wakeup_ports[1].bits.uop.lrs1
connect slots_5.io.wakeup_ports[1].bits.uop.ldst, issue_slots[5].wakeup_ports[1].bits.uop.ldst
connect slots_5.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[5].wakeup_ports[1].bits.uop.ldst_is_rs1
connect slots_5.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[5].wakeup_ports[1].bits.uop.csr_cmd
connect slots_5.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[5].wakeup_ports[1].bits.uop.flush_on_commit
connect slots_5.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[5].wakeup_ports[1].bits.uop.is_unique
connect slots_5.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[5].wakeup_ports[1].bits.uop.uses_stq
connect slots_5.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[5].wakeup_ports[1].bits.uop.uses_ldq
connect slots_5.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[5].wakeup_ports[1].bits.uop.mem_signed
connect slots_5.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[5].wakeup_ports[1].bits.uop.mem_size
connect slots_5.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[5].wakeup_ports[1].bits.uop.mem_cmd
connect slots_5.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[5].wakeup_ports[1].bits.uop.exc_cause
connect slots_5.io.wakeup_ports[1].bits.uop.exception, issue_slots[5].wakeup_ports[1].bits.uop.exception
connect slots_5.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[5].wakeup_ports[1].bits.uop.stale_pdst
connect slots_5.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[5].wakeup_ports[1].bits.uop.ppred_busy
connect slots_5.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[5].wakeup_ports[1].bits.uop.prs3_busy
connect slots_5.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[5].wakeup_ports[1].bits.uop.prs2_busy
connect slots_5.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[5].wakeup_ports[1].bits.uop.prs1_busy
connect slots_5.io.wakeup_ports[1].bits.uop.ppred, issue_slots[5].wakeup_ports[1].bits.uop.ppred
connect slots_5.io.wakeup_ports[1].bits.uop.prs3, issue_slots[5].wakeup_ports[1].bits.uop.prs3
connect slots_5.io.wakeup_ports[1].bits.uop.prs2, issue_slots[5].wakeup_ports[1].bits.uop.prs2
connect slots_5.io.wakeup_ports[1].bits.uop.prs1, issue_slots[5].wakeup_ports[1].bits.uop.prs1
connect slots_5.io.wakeup_ports[1].bits.uop.pdst, issue_slots[5].wakeup_ports[1].bits.uop.pdst
connect slots_5.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[5].wakeup_ports[1].bits.uop.rxq_idx
connect slots_5.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[5].wakeup_ports[1].bits.uop.stq_idx
connect slots_5.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[5].wakeup_ports[1].bits.uop.ldq_idx
connect slots_5.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[5].wakeup_ports[1].bits.uop.rob_idx
connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.vec
connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.wflags
connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.sqrt
connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.div
connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.fma
connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe
connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.toint
connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.fromint
connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut
connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn
connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.swap23
connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.swap12
connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.ren3
connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.ren2
connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.ren1
connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.wen
connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.ldst
connect slots_5.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[5].wakeup_ports[1].bits.uop.op2_sel
connect slots_5.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[5].wakeup_ports[1].bits.uop.op1_sel
connect slots_5.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[5].wakeup_ports[1].bits.uop.imm_packed
connect slots_5.io.wakeup_ports[1].bits.uop.pimm, issue_slots[5].wakeup_ports[1].bits.uop.pimm
connect slots_5.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[5].wakeup_ports[1].bits.uop.imm_sel
connect slots_5.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[5].wakeup_ports[1].bits.uop.imm_rename
connect slots_5.io.wakeup_ports[1].bits.uop.taken, issue_slots[5].wakeup_ports[1].bits.uop.taken
connect slots_5.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[5].wakeup_ports[1].bits.uop.pc_lob
connect slots_5.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[5].wakeup_ports[1].bits.uop.edge_inst
connect slots_5.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[5].wakeup_ports[1].bits.uop.ftq_idx
connect slots_5.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[5].wakeup_ports[1].bits.uop.is_mov
connect slots_5.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[5].wakeup_ports[1].bits.uop.is_rocc
connect slots_5.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[5].wakeup_ports[1].bits.uop.is_sys_pc2epc
connect slots_5.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[5].wakeup_ports[1].bits.uop.is_eret
connect slots_5.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[5].wakeup_ports[1].bits.uop.is_amo
connect slots_5.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[5].wakeup_ports[1].bits.uop.is_sfence
connect slots_5.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[5].wakeup_ports[1].bits.uop.is_fencei
connect slots_5.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[5].wakeup_ports[1].bits.uop.is_fence
connect slots_5.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[5].wakeup_ports[1].bits.uop.is_sfb
connect slots_5.io.wakeup_ports[1].bits.uop.br_type, issue_slots[5].wakeup_ports[1].bits.uop.br_type
connect slots_5.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[5].wakeup_ports[1].bits.uop.br_tag
connect slots_5.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[5].wakeup_ports[1].bits.uop.br_mask
connect slots_5.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[5].wakeup_ports[1].bits.uop.dis_col_sel
connect slots_5.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[5].wakeup_ports[1].bits.uop.iw_p3_bypass_hint
connect slots_5.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[5].wakeup_ports[1].bits.uop.iw_p2_bypass_hint
connect slots_5.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[5].wakeup_ports[1].bits.uop.iw_p1_bypass_hint
connect slots_5.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[5].wakeup_ports[1].bits.uop.iw_p2_speculative_child
connect slots_5.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[5].wakeup_ports[1].bits.uop.iw_p1_speculative_child
connect slots_5.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[5].wakeup_ports[1].bits.uop.iw_issued_partial_dgen
connect slots_5.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[5].wakeup_ports[1].bits.uop.iw_issued_partial_agen
connect slots_5.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[5].wakeup_ports[1].bits.uop.iw_issued
connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[0]
connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[1]
connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[2]
connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[3]
connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[4]
connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[5]
connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[6]
connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[7]
connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[8]
connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[9]
connect slots_5.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[5].wakeup_ports[1].bits.uop.iq_type[0]
connect slots_5.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[5].wakeup_ports[1].bits.uop.iq_type[1]
connect slots_5.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[5].wakeup_ports[1].bits.uop.iq_type[2]
connect slots_5.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[5].wakeup_ports[1].bits.uop.iq_type[3]
connect slots_5.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[5].wakeup_ports[1].bits.uop.debug_pc
connect slots_5.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[5].wakeup_ports[1].bits.uop.is_rvc
connect slots_5.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[5].wakeup_ports[1].bits.uop.debug_inst
connect slots_5.io.wakeup_ports[1].bits.uop.inst, issue_slots[5].wakeup_ports[1].bits.uop.inst
connect slots_5.io.wakeup_ports[1].valid, issue_slots[5].wakeup_ports[1].valid
connect slots_5.io.wakeup_ports[2].bits.rebusy, issue_slots[5].wakeup_ports[2].bits.rebusy
connect slots_5.io.wakeup_ports[2].bits.speculative_mask, issue_slots[5].wakeup_ports[2].bits.speculative_mask
connect slots_5.io.wakeup_ports[2].bits.bypassable, issue_slots[5].wakeup_ports[2].bits.bypassable
connect slots_5.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[5].wakeup_ports[2].bits.uop.debug_tsrc
connect slots_5.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[5].wakeup_ports[2].bits.uop.debug_fsrc
connect slots_5.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[5].wakeup_ports[2].bits.uop.bp_xcpt_if
connect slots_5.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[5].wakeup_ports[2].bits.uop.bp_debug_if
connect slots_5.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[5].wakeup_ports[2].bits.uop.xcpt_ma_if
connect slots_5.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[5].wakeup_ports[2].bits.uop.xcpt_ae_if
connect slots_5.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[5].wakeup_ports[2].bits.uop.xcpt_pf_if
connect slots_5.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[5].wakeup_ports[2].bits.uop.fp_typ
connect slots_5.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[5].wakeup_ports[2].bits.uop.fp_rm
connect slots_5.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[5].wakeup_ports[2].bits.uop.fp_val
connect slots_5.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[5].wakeup_ports[2].bits.uop.fcn_op
connect slots_5.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[5].wakeup_ports[2].bits.uop.fcn_dw
connect slots_5.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[5].wakeup_ports[2].bits.uop.frs3_en
connect slots_5.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[5].wakeup_ports[2].bits.uop.lrs2_rtype
connect slots_5.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[5].wakeup_ports[2].bits.uop.lrs1_rtype
connect slots_5.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[5].wakeup_ports[2].bits.uop.dst_rtype
connect slots_5.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[5].wakeup_ports[2].bits.uop.lrs3
connect slots_5.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[5].wakeup_ports[2].bits.uop.lrs2
connect slots_5.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[5].wakeup_ports[2].bits.uop.lrs1
connect slots_5.io.wakeup_ports[2].bits.uop.ldst, issue_slots[5].wakeup_ports[2].bits.uop.ldst
connect slots_5.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[5].wakeup_ports[2].bits.uop.ldst_is_rs1
connect slots_5.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[5].wakeup_ports[2].bits.uop.csr_cmd
connect slots_5.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[5].wakeup_ports[2].bits.uop.flush_on_commit
connect slots_5.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[5].wakeup_ports[2].bits.uop.is_unique
connect slots_5.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[5].wakeup_ports[2].bits.uop.uses_stq
connect slots_5.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[5].wakeup_ports[2].bits.uop.uses_ldq
connect slots_5.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[5].wakeup_ports[2].bits.uop.mem_signed
connect slots_5.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[5].wakeup_ports[2].bits.uop.mem_size
connect slots_5.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[5].wakeup_ports[2].bits.uop.mem_cmd
connect slots_5.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[5].wakeup_ports[2].bits.uop.exc_cause
connect slots_5.io.wakeup_ports[2].bits.uop.exception, issue_slots[5].wakeup_ports[2].bits.uop.exception
connect slots_5.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[5].wakeup_ports[2].bits.uop.stale_pdst
connect slots_5.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[5].wakeup_ports[2].bits.uop.ppred_busy
connect slots_5.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[5].wakeup_ports[2].bits.uop.prs3_busy
connect slots_5.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[5].wakeup_ports[2].bits.uop.prs2_busy
connect slots_5.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[5].wakeup_ports[2].bits.uop.prs1_busy
connect slots_5.io.wakeup_ports[2].bits.uop.ppred, issue_slots[5].wakeup_ports[2].bits.uop.ppred
connect slots_5.io.wakeup_ports[2].bits.uop.prs3, issue_slots[5].wakeup_ports[2].bits.uop.prs3
connect slots_5.io.wakeup_ports[2].bits.uop.prs2, issue_slots[5].wakeup_ports[2].bits.uop.prs2
connect slots_5.io.wakeup_ports[2].bits.uop.prs1, issue_slots[5].wakeup_ports[2].bits.uop.prs1
connect slots_5.io.wakeup_ports[2].bits.uop.pdst, issue_slots[5].wakeup_ports[2].bits.uop.pdst
connect slots_5.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[5].wakeup_ports[2].bits.uop.rxq_idx
connect slots_5.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[5].wakeup_ports[2].bits.uop.stq_idx
connect slots_5.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[5].wakeup_ports[2].bits.uop.ldq_idx
connect slots_5.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[5].wakeup_ports[2].bits.uop.rob_idx
connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.vec
connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.wflags
connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.sqrt
connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.div
connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.fma
connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe
connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.toint
connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.fromint
connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut
connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn
connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.swap23
connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.swap12
connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.ren3
connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.ren2
connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.ren1
connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.wen
connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.ldst
connect slots_5.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[5].wakeup_ports[2].bits.uop.op2_sel
connect slots_5.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[5].wakeup_ports[2].bits.uop.op1_sel
connect slots_5.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[5].wakeup_ports[2].bits.uop.imm_packed
connect slots_5.io.wakeup_ports[2].bits.uop.pimm, issue_slots[5].wakeup_ports[2].bits.uop.pimm
connect slots_5.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[5].wakeup_ports[2].bits.uop.imm_sel
connect slots_5.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[5].wakeup_ports[2].bits.uop.imm_rename
connect slots_5.io.wakeup_ports[2].bits.uop.taken, issue_slots[5].wakeup_ports[2].bits.uop.taken
connect slots_5.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[5].wakeup_ports[2].bits.uop.pc_lob
connect slots_5.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[5].wakeup_ports[2].bits.uop.edge_inst
connect slots_5.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[5].wakeup_ports[2].bits.uop.ftq_idx
connect slots_5.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[5].wakeup_ports[2].bits.uop.is_mov
connect slots_5.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[5].wakeup_ports[2].bits.uop.is_rocc
connect slots_5.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[5].wakeup_ports[2].bits.uop.is_sys_pc2epc
connect slots_5.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[5].wakeup_ports[2].bits.uop.is_eret
connect slots_5.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[5].wakeup_ports[2].bits.uop.is_amo
connect slots_5.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[5].wakeup_ports[2].bits.uop.is_sfence
connect slots_5.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[5].wakeup_ports[2].bits.uop.is_fencei
connect slots_5.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[5].wakeup_ports[2].bits.uop.is_fence
connect slots_5.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[5].wakeup_ports[2].bits.uop.is_sfb
connect slots_5.io.wakeup_ports[2].bits.uop.br_type, issue_slots[5].wakeup_ports[2].bits.uop.br_type
connect slots_5.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[5].wakeup_ports[2].bits.uop.br_tag
connect slots_5.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[5].wakeup_ports[2].bits.uop.br_mask
connect slots_5.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[5].wakeup_ports[2].bits.uop.dis_col_sel
connect slots_5.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[5].wakeup_ports[2].bits.uop.iw_p3_bypass_hint
connect slots_5.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[5].wakeup_ports[2].bits.uop.iw_p2_bypass_hint
connect slots_5.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[5].wakeup_ports[2].bits.uop.iw_p1_bypass_hint
connect slots_5.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[5].wakeup_ports[2].bits.uop.iw_p2_speculative_child
connect slots_5.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[5].wakeup_ports[2].bits.uop.iw_p1_speculative_child
connect slots_5.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[5].wakeup_ports[2].bits.uop.iw_issued_partial_dgen
connect slots_5.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[5].wakeup_ports[2].bits.uop.iw_issued_partial_agen
connect slots_5.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[5].wakeup_ports[2].bits.uop.iw_issued
connect slots_5.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[5].wakeup_ports[2].bits.uop.fu_code[0]
connect slots_5.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[5].wakeup_ports[2].bits.uop.fu_code[1]
connect slots_5.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[5].wakeup_ports[2].bits.uop.fu_code[2]
connect slots_5.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[5].wakeup_ports[2].bits.uop.fu_code[3]
connect slots_5.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[5].wakeup_ports[2].bits.uop.fu_code[4]
connect slots_5.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[5].wakeup_ports[2].bits.uop.fu_code[5]
connect slots_5.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[5].wakeup_ports[2].bits.uop.fu_code[6]
connect slots_5.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[5].wakeup_ports[2].bits.uop.fu_code[7]
connect slots_5.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[5].wakeup_ports[2].bits.uop.fu_code[8]
connect slots_5.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[5].wakeup_ports[2].bits.uop.fu_code[9]
connect slots_5.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[5].wakeup_ports[2].bits.uop.iq_type[0]
connect slots_5.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[5].wakeup_ports[2].bits.uop.iq_type[1]
connect slots_5.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[5].wakeup_ports[2].bits.uop.iq_type[2]
connect slots_5.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[5].wakeup_ports[2].bits.uop.iq_type[3]
connect slots_5.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[5].wakeup_ports[2].bits.uop.debug_pc
connect slots_5.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[5].wakeup_ports[2].bits.uop.is_rvc
connect slots_5.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[5].wakeup_ports[2].bits.uop.debug_inst
connect slots_5.io.wakeup_ports[2].bits.uop.inst, issue_slots[5].wakeup_ports[2].bits.uop.inst
connect slots_5.io.wakeup_ports[2].valid, issue_slots[5].wakeup_ports[2].valid
connect slots_5.io.wakeup_ports[3].bits.rebusy, issue_slots[5].wakeup_ports[3].bits.rebusy
connect slots_5.io.wakeup_ports[3].bits.speculative_mask, issue_slots[5].wakeup_ports[3].bits.speculative_mask
connect slots_5.io.wakeup_ports[3].bits.bypassable, issue_slots[5].wakeup_ports[3].bits.bypassable
connect slots_5.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[5].wakeup_ports[3].bits.uop.debug_tsrc
connect slots_5.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[5].wakeup_ports[3].bits.uop.debug_fsrc
connect slots_5.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[5].wakeup_ports[3].bits.uop.bp_xcpt_if
connect slots_5.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[5].wakeup_ports[3].bits.uop.bp_debug_if
connect slots_5.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[5].wakeup_ports[3].bits.uop.xcpt_ma_if
connect slots_5.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[5].wakeup_ports[3].bits.uop.xcpt_ae_if
connect slots_5.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[5].wakeup_ports[3].bits.uop.xcpt_pf_if
connect slots_5.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[5].wakeup_ports[3].bits.uop.fp_typ
connect slots_5.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[5].wakeup_ports[3].bits.uop.fp_rm
connect slots_5.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[5].wakeup_ports[3].bits.uop.fp_val
connect slots_5.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[5].wakeup_ports[3].bits.uop.fcn_op
connect slots_5.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[5].wakeup_ports[3].bits.uop.fcn_dw
connect slots_5.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[5].wakeup_ports[3].bits.uop.frs3_en
connect slots_5.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[5].wakeup_ports[3].bits.uop.lrs2_rtype
connect slots_5.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[5].wakeup_ports[3].bits.uop.lrs1_rtype
connect slots_5.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[5].wakeup_ports[3].bits.uop.dst_rtype
connect slots_5.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[5].wakeup_ports[3].bits.uop.lrs3
connect slots_5.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[5].wakeup_ports[3].bits.uop.lrs2
connect slots_5.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[5].wakeup_ports[3].bits.uop.lrs1
connect slots_5.io.wakeup_ports[3].bits.uop.ldst, issue_slots[5].wakeup_ports[3].bits.uop.ldst
connect slots_5.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[5].wakeup_ports[3].bits.uop.ldst_is_rs1
connect slots_5.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[5].wakeup_ports[3].bits.uop.csr_cmd
connect slots_5.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[5].wakeup_ports[3].bits.uop.flush_on_commit
connect slots_5.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[5].wakeup_ports[3].bits.uop.is_unique
connect slots_5.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[5].wakeup_ports[3].bits.uop.uses_stq
connect slots_5.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[5].wakeup_ports[3].bits.uop.uses_ldq
connect slots_5.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[5].wakeup_ports[3].bits.uop.mem_signed
connect slots_5.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[5].wakeup_ports[3].bits.uop.mem_size
connect slots_5.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[5].wakeup_ports[3].bits.uop.mem_cmd
connect slots_5.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[5].wakeup_ports[3].bits.uop.exc_cause
connect slots_5.io.wakeup_ports[3].bits.uop.exception, issue_slots[5].wakeup_ports[3].bits.uop.exception
connect slots_5.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[5].wakeup_ports[3].bits.uop.stale_pdst
connect slots_5.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[5].wakeup_ports[3].bits.uop.ppred_busy
connect slots_5.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[5].wakeup_ports[3].bits.uop.prs3_busy
connect slots_5.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[5].wakeup_ports[3].bits.uop.prs2_busy
connect slots_5.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[5].wakeup_ports[3].bits.uop.prs1_busy
connect slots_5.io.wakeup_ports[3].bits.uop.ppred, issue_slots[5].wakeup_ports[3].bits.uop.ppred
connect slots_5.io.wakeup_ports[3].bits.uop.prs3, issue_slots[5].wakeup_ports[3].bits.uop.prs3
connect slots_5.io.wakeup_ports[3].bits.uop.prs2, issue_slots[5].wakeup_ports[3].bits.uop.prs2
connect slots_5.io.wakeup_ports[3].bits.uop.prs1, issue_slots[5].wakeup_ports[3].bits.uop.prs1
connect slots_5.io.wakeup_ports[3].bits.uop.pdst, issue_slots[5].wakeup_ports[3].bits.uop.pdst
connect slots_5.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[5].wakeup_ports[3].bits.uop.rxq_idx
connect slots_5.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[5].wakeup_ports[3].bits.uop.stq_idx
connect slots_5.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[5].wakeup_ports[3].bits.uop.ldq_idx
connect slots_5.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[5].wakeup_ports[3].bits.uop.rob_idx
connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.vec
connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.wflags
connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.sqrt
connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.div
connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.fma
connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe
connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.toint
connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.fromint
connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut
connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn
connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.swap23
connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.swap12
connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.ren3
connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.ren2
connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.ren1
connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.wen
connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.ldst
connect slots_5.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[5].wakeup_ports[3].bits.uop.op2_sel
connect slots_5.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[5].wakeup_ports[3].bits.uop.op1_sel
connect slots_5.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[5].wakeup_ports[3].bits.uop.imm_packed
connect slots_5.io.wakeup_ports[3].bits.uop.pimm, issue_slots[5].wakeup_ports[3].bits.uop.pimm
connect slots_5.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[5].wakeup_ports[3].bits.uop.imm_sel
connect slots_5.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[5].wakeup_ports[3].bits.uop.imm_rename
connect slots_5.io.wakeup_ports[3].bits.uop.taken, issue_slots[5].wakeup_ports[3].bits.uop.taken
connect slots_5.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[5].wakeup_ports[3].bits.uop.pc_lob
connect slots_5.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[5].wakeup_ports[3].bits.uop.edge_inst
connect slots_5.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[5].wakeup_ports[3].bits.uop.ftq_idx
connect slots_5.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[5].wakeup_ports[3].bits.uop.is_mov
connect slots_5.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[5].wakeup_ports[3].bits.uop.is_rocc
connect slots_5.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[5].wakeup_ports[3].bits.uop.is_sys_pc2epc
connect slots_5.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[5].wakeup_ports[3].bits.uop.is_eret
connect slots_5.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[5].wakeup_ports[3].bits.uop.is_amo
connect slots_5.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[5].wakeup_ports[3].bits.uop.is_sfence
connect slots_5.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[5].wakeup_ports[3].bits.uop.is_fencei
connect slots_5.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[5].wakeup_ports[3].bits.uop.is_fence
connect slots_5.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[5].wakeup_ports[3].bits.uop.is_sfb
connect slots_5.io.wakeup_ports[3].bits.uop.br_type, issue_slots[5].wakeup_ports[3].bits.uop.br_type
connect slots_5.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[5].wakeup_ports[3].bits.uop.br_tag
connect slots_5.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[5].wakeup_ports[3].bits.uop.br_mask
connect slots_5.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[5].wakeup_ports[3].bits.uop.dis_col_sel
connect slots_5.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[5].wakeup_ports[3].bits.uop.iw_p3_bypass_hint
connect slots_5.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[5].wakeup_ports[3].bits.uop.iw_p2_bypass_hint
connect slots_5.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[5].wakeup_ports[3].bits.uop.iw_p1_bypass_hint
connect slots_5.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[5].wakeup_ports[3].bits.uop.iw_p2_speculative_child
connect slots_5.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[5].wakeup_ports[3].bits.uop.iw_p1_speculative_child
connect slots_5.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[5].wakeup_ports[3].bits.uop.iw_issued_partial_dgen
connect slots_5.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[5].wakeup_ports[3].bits.uop.iw_issued_partial_agen
connect slots_5.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[5].wakeup_ports[3].bits.uop.iw_issued
connect slots_5.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[5].wakeup_ports[3].bits.uop.fu_code[0]
connect slots_5.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[5].wakeup_ports[3].bits.uop.fu_code[1]
connect slots_5.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[5].wakeup_ports[3].bits.uop.fu_code[2]
connect slots_5.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[5].wakeup_ports[3].bits.uop.fu_code[3]
connect slots_5.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[5].wakeup_ports[3].bits.uop.fu_code[4]
connect slots_5.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[5].wakeup_ports[3].bits.uop.fu_code[5]
connect slots_5.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[5].wakeup_ports[3].bits.uop.fu_code[6]
connect slots_5.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[5].wakeup_ports[3].bits.uop.fu_code[7]
connect slots_5.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[5].wakeup_ports[3].bits.uop.fu_code[8]
connect slots_5.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[5].wakeup_ports[3].bits.uop.fu_code[9]
connect slots_5.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[5].wakeup_ports[3].bits.uop.iq_type[0]
connect slots_5.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[5].wakeup_ports[3].bits.uop.iq_type[1]
connect slots_5.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[5].wakeup_ports[3].bits.uop.iq_type[2]
connect slots_5.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[5].wakeup_ports[3].bits.uop.iq_type[3]
connect slots_5.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[5].wakeup_ports[3].bits.uop.debug_pc
connect slots_5.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[5].wakeup_ports[3].bits.uop.is_rvc
connect slots_5.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[5].wakeup_ports[3].bits.uop.debug_inst
connect slots_5.io.wakeup_ports[3].bits.uop.inst, issue_slots[5].wakeup_ports[3].bits.uop.inst
connect slots_5.io.wakeup_ports[3].valid, issue_slots[5].wakeup_ports[3].valid
connect slots_5.io.squash_grant, issue_slots[5].squash_grant
connect slots_5.io.clear, issue_slots[5].clear
connect slots_5.io.kill, issue_slots[5].kill
connect slots_5.io.brupdate.b2.target_offset, issue_slots[5].brupdate.b2.target_offset
connect slots_5.io.brupdate.b2.jalr_target, issue_slots[5].brupdate.b2.jalr_target
connect slots_5.io.brupdate.b2.pc_sel, issue_slots[5].brupdate.b2.pc_sel
connect slots_5.io.brupdate.b2.cfi_type, issue_slots[5].brupdate.b2.cfi_type
connect slots_5.io.brupdate.b2.taken, issue_slots[5].brupdate.b2.taken
connect slots_5.io.brupdate.b2.mispredict, issue_slots[5].brupdate.b2.mispredict
connect slots_5.io.brupdate.b2.uop.debug_tsrc, issue_slots[5].brupdate.b2.uop.debug_tsrc
connect slots_5.io.brupdate.b2.uop.debug_fsrc, issue_slots[5].brupdate.b2.uop.debug_fsrc
connect slots_5.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[5].brupdate.b2.uop.bp_xcpt_if
connect slots_5.io.brupdate.b2.uop.bp_debug_if, issue_slots[5].brupdate.b2.uop.bp_debug_if
connect slots_5.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[5].brupdate.b2.uop.xcpt_ma_if
connect slots_5.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[5].brupdate.b2.uop.xcpt_ae_if
connect slots_5.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[5].brupdate.b2.uop.xcpt_pf_if
connect slots_5.io.brupdate.b2.uop.fp_typ, issue_slots[5].brupdate.b2.uop.fp_typ
connect slots_5.io.brupdate.b2.uop.fp_rm, issue_slots[5].brupdate.b2.uop.fp_rm
connect slots_5.io.brupdate.b2.uop.fp_val, issue_slots[5].brupdate.b2.uop.fp_val
connect slots_5.io.brupdate.b2.uop.fcn_op, issue_slots[5].brupdate.b2.uop.fcn_op
connect slots_5.io.brupdate.b2.uop.fcn_dw, issue_slots[5].brupdate.b2.uop.fcn_dw
connect slots_5.io.brupdate.b2.uop.frs3_en, issue_slots[5].brupdate.b2.uop.frs3_en
connect slots_5.io.brupdate.b2.uop.lrs2_rtype, issue_slots[5].brupdate.b2.uop.lrs2_rtype
connect slots_5.io.brupdate.b2.uop.lrs1_rtype, issue_slots[5].brupdate.b2.uop.lrs1_rtype
connect slots_5.io.brupdate.b2.uop.dst_rtype, issue_slots[5].brupdate.b2.uop.dst_rtype
connect slots_5.io.brupdate.b2.uop.lrs3, issue_slots[5].brupdate.b2.uop.lrs3
connect slots_5.io.brupdate.b2.uop.lrs2, issue_slots[5].brupdate.b2.uop.lrs2
connect slots_5.io.brupdate.b2.uop.lrs1, issue_slots[5].brupdate.b2.uop.lrs1
connect slots_5.io.brupdate.b2.uop.ldst, issue_slots[5].brupdate.b2.uop.ldst
connect slots_5.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[5].brupdate.b2.uop.ldst_is_rs1
connect slots_5.io.brupdate.b2.uop.csr_cmd, issue_slots[5].brupdate.b2.uop.csr_cmd
connect slots_5.io.brupdate.b2.uop.flush_on_commit, issue_slots[5].brupdate.b2.uop.flush_on_commit
connect slots_5.io.brupdate.b2.uop.is_unique, issue_slots[5].brupdate.b2.uop.is_unique
connect slots_5.io.brupdate.b2.uop.uses_stq, issue_slots[5].brupdate.b2.uop.uses_stq
connect slots_5.io.brupdate.b2.uop.uses_ldq, issue_slots[5].brupdate.b2.uop.uses_ldq
connect slots_5.io.brupdate.b2.uop.mem_signed, issue_slots[5].brupdate.b2.uop.mem_signed
connect slots_5.io.brupdate.b2.uop.mem_size, issue_slots[5].brupdate.b2.uop.mem_size
connect slots_5.io.brupdate.b2.uop.mem_cmd, issue_slots[5].brupdate.b2.uop.mem_cmd
connect slots_5.io.brupdate.b2.uop.exc_cause, issue_slots[5].brupdate.b2.uop.exc_cause
connect slots_5.io.brupdate.b2.uop.exception, issue_slots[5].brupdate.b2.uop.exception
connect slots_5.io.brupdate.b2.uop.stale_pdst, issue_slots[5].brupdate.b2.uop.stale_pdst
connect slots_5.io.brupdate.b2.uop.ppred_busy, issue_slots[5].brupdate.b2.uop.ppred_busy
connect slots_5.io.brupdate.b2.uop.prs3_busy, issue_slots[5].brupdate.b2.uop.prs3_busy
connect slots_5.io.brupdate.b2.uop.prs2_busy, issue_slots[5].brupdate.b2.uop.prs2_busy
connect slots_5.io.brupdate.b2.uop.prs1_busy, issue_slots[5].brupdate.b2.uop.prs1_busy
connect slots_5.io.brupdate.b2.uop.ppred, issue_slots[5].brupdate.b2.uop.ppred
connect slots_5.io.brupdate.b2.uop.prs3, issue_slots[5].brupdate.b2.uop.prs3
connect slots_5.io.brupdate.b2.uop.prs2, issue_slots[5].brupdate.b2.uop.prs2
connect slots_5.io.brupdate.b2.uop.prs1, issue_slots[5].brupdate.b2.uop.prs1
connect slots_5.io.brupdate.b2.uop.pdst, issue_slots[5].brupdate.b2.uop.pdst
connect slots_5.io.brupdate.b2.uop.rxq_idx, issue_slots[5].brupdate.b2.uop.rxq_idx
connect slots_5.io.brupdate.b2.uop.stq_idx, issue_slots[5].brupdate.b2.uop.stq_idx
connect slots_5.io.brupdate.b2.uop.ldq_idx, issue_slots[5].brupdate.b2.uop.ldq_idx
connect slots_5.io.brupdate.b2.uop.rob_idx, issue_slots[5].brupdate.b2.uop.rob_idx
connect slots_5.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[5].brupdate.b2.uop.fp_ctrl.vec
connect slots_5.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[5].brupdate.b2.uop.fp_ctrl.wflags
connect slots_5.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[5].brupdate.b2.uop.fp_ctrl.sqrt
connect slots_5.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[5].brupdate.b2.uop.fp_ctrl.div
connect slots_5.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[5].brupdate.b2.uop.fp_ctrl.fma
connect slots_5.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[5].brupdate.b2.uop.fp_ctrl.fastpipe
connect slots_5.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[5].brupdate.b2.uop.fp_ctrl.toint
connect slots_5.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[5].brupdate.b2.uop.fp_ctrl.fromint
connect slots_5.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[5].brupdate.b2.uop.fp_ctrl.typeTagOut
connect slots_5.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[5].brupdate.b2.uop.fp_ctrl.typeTagIn
connect slots_5.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[5].brupdate.b2.uop.fp_ctrl.swap23
connect slots_5.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[5].brupdate.b2.uop.fp_ctrl.swap12
connect slots_5.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[5].brupdate.b2.uop.fp_ctrl.ren3
connect slots_5.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[5].brupdate.b2.uop.fp_ctrl.ren2
connect slots_5.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[5].brupdate.b2.uop.fp_ctrl.ren1
connect slots_5.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[5].brupdate.b2.uop.fp_ctrl.wen
connect slots_5.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[5].brupdate.b2.uop.fp_ctrl.ldst
connect slots_5.io.brupdate.b2.uop.op2_sel, issue_slots[5].brupdate.b2.uop.op2_sel
connect slots_5.io.brupdate.b2.uop.op1_sel, issue_slots[5].brupdate.b2.uop.op1_sel
connect slots_5.io.brupdate.b2.uop.imm_packed, issue_slots[5].brupdate.b2.uop.imm_packed
connect slots_5.io.brupdate.b2.uop.pimm, issue_slots[5].brupdate.b2.uop.pimm
connect slots_5.io.brupdate.b2.uop.imm_sel, issue_slots[5].brupdate.b2.uop.imm_sel
connect slots_5.io.brupdate.b2.uop.imm_rename, issue_slots[5].brupdate.b2.uop.imm_rename
connect slots_5.io.brupdate.b2.uop.taken, issue_slots[5].brupdate.b2.uop.taken
connect slots_5.io.brupdate.b2.uop.pc_lob, issue_slots[5].brupdate.b2.uop.pc_lob
connect slots_5.io.brupdate.b2.uop.edge_inst, issue_slots[5].brupdate.b2.uop.edge_inst
connect slots_5.io.brupdate.b2.uop.ftq_idx, issue_slots[5].brupdate.b2.uop.ftq_idx
connect slots_5.io.brupdate.b2.uop.is_mov, issue_slots[5].brupdate.b2.uop.is_mov
connect slots_5.io.brupdate.b2.uop.is_rocc, issue_slots[5].brupdate.b2.uop.is_rocc
connect slots_5.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[5].brupdate.b2.uop.is_sys_pc2epc
connect slots_5.io.brupdate.b2.uop.is_eret, issue_slots[5].brupdate.b2.uop.is_eret
connect slots_5.io.brupdate.b2.uop.is_amo, issue_slots[5].brupdate.b2.uop.is_amo
connect slots_5.io.brupdate.b2.uop.is_sfence, issue_slots[5].brupdate.b2.uop.is_sfence
connect slots_5.io.brupdate.b2.uop.is_fencei, issue_slots[5].brupdate.b2.uop.is_fencei
connect slots_5.io.brupdate.b2.uop.is_fence, issue_slots[5].brupdate.b2.uop.is_fence
connect slots_5.io.brupdate.b2.uop.is_sfb, issue_slots[5].brupdate.b2.uop.is_sfb
connect slots_5.io.brupdate.b2.uop.br_type, issue_slots[5].brupdate.b2.uop.br_type
connect slots_5.io.brupdate.b2.uop.br_tag, issue_slots[5].brupdate.b2.uop.br_tag
connect slots_5.io.brupdate.b2.uop.br_mask, issue_slots[5].brupdate.b2.uop.br_mask
connect slots_5.io.brupdate.b2.uop.dis_col_sel, issue_slots[5].brupdate.b2.uop.dis_col_sel
connect slots_5.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[5].brupdate.b2.uop.iw_p3_bypass_hint
connect slots_5.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[5].brupdate.b2.uop.iw_p2_bypass_hint
connect slots_5.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[5].brupdate.b2.uop.iw_p1_bypass_hint
connect slots_5.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[5].brupdate.b2.uop.iw_p2_speculative_child
connect slots_5.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[5].brupdate.b2.uop.iw_p1_speculative_child
connect slots_5.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[5].brupdate.b2.uop.iw_issued_partial_dgen
connect slots_5.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[5].brupdate.b2.uop.iw_issued_partial_agen
connect slots_5.io.brupdate.b2.uop.iw_issued, issue_slots[5].brupdate.b2.uop.iw_issued
connect slots_5.io.brupdate.b2.uop.fu_code[0], issue_slots[5].brupdate.b2.uop.fu_code[0]
connect slots_5.io.brupdate.b2.uop.fu_code[1], issue_slots[5].brupdate.b2.uop.fu_code[1]
connect slots_5.io.brupdate.b2.uop.fu_code[2], issue_slots[5].brupdate.b2.uop.fu_code[2]
connect slots_5.io.brupdate.b2.uop.fu_code[3], issue_slots[5].brupdate.b2.uop.fu_code[3]
connect slots_5.io.brupdate.b2.uop.fu_code[4], issue_slots[5].brupdate.b2.uop.fu_code[4]
connect slots_5.io.brupdate.b2.uop.fu_code[5], issue_slots[5].brupdate.b2.uop.fu_code[5]
connect slots_5.io.brupdate.b2.uop.fu_code[6], issue_slots[5].brupdate.b2.uop.fu_code[6]
connect slots_5.io.brupdate.b2.uop.fu_code[7], issue_slots[5].brupdate.b2.uop.fu_code[7]
connect slots_5.io.brupdate.b2.uop.fu_code[8], issue_slots[5].brupdate.b2.uop.fu_code[8]
connect slots_5.io.brupdate.b2.uop.fu_code[9], issue_slots[5].brupdate.b2.uop.fu_code[9]
connect slots_5.io.brupdate.b2.uop.iq_type[0], issue_slots[5].brupdate.b2.uop.iq_type[0]
connect slots_5.io.brupdate.b2.uop.iq_type[1], issue_slots[5].brupdate.b2.uop.iq_type[1]
connect slots_5.io.brupdate.b2.uop.iq_type[2], issue_slots[5].brupdate.b2.uop.iq_type[2]
connect slots_5.io.brupdate.b2.uop.iq_type[3], issue_slots[5].brupdate.b2.uop.iq_type[3]
connect slots_5.io.brupdate.b2.uop.debug_pc, issue_slots[5].brupdate.b2.uop.debug_pc
connect slots_5.io.brupdate.b2.uop.is_rvc, issue_slots[5].brupdate.b2.uop.is_rvc
connect slots_5.io.brupdate.b2.uop.debug_inst, issue_slots[5].brupdate.b2.uop.debug_inst
connect slots_5.io.brupdate.b2.uop.inst, issue_slots[5].brupdate.b2.uop.inst
connect slots_5.io.brupdate.b1.mispredict_mask, issue_slots[5].brupdate.b1.mispredict_mask
connect slots_5.io.brupdate.b1.resolve_mask, issue_slots[5].brupdate.b1.resolve_mask
connect issue_slots[5].out_uop.debug_tsrc, slots_5.io.out_uop.debug_tsrc
connect issue_slots[5].out_uop.debug_fsrc, slots_5.io.out_uop.debug_fsrc
connect issue_slots[5].out_uop.bp_xcpt_if, slots_5.io.out_uop.bp_xcpt_if
connect issue_slots[5].out_uop.bp_debug_if, slots_5.io.out_uop.bp_debug_if
connect issue_slots[5].out_uop.xcpt_ma_if, slots_5.io.out_uop.xcpt_ma_if
connect issue_slots[5].out_uop.xcpt_ae_if, slots_5.io.out_uop.xcpt_ae_if
connect issue_slots[5].out_uop.xcpt_pf_if, slots_5.io.out_uop.xcpt_pf_if
connect issue_slots[5].out_uop.fp_typ, slots_5.io.out_uop.fp_typ
connect issue_slots[5].out_uop.fp_rm, slots_5.io.out_uop.fp_rm
connect issue_slots[5].out_uop.fp_val, slots_5.io.out_uop.fp_val
connect issue_slots[5].out_uop.fcn_op, slots_5.io.out_uop.fcn_op
connect issue_slots[5].out_uop.fcn_dw, slots_5.io.out_uop.fcn_dw
connect issue_slots[5].out_uop.frs3_en, slots_5.io.out_uop.frs3_en
connect issue_slots[5].out_uop.lrs2_rtype, slots_5.io.out_uop.lrs2_rtype
connect issue_slots[5].out_uop.lrs1_rtype, slots_5.io.out_uop.lrs1_rtype
connect issue_slots[5].out_uop.dst_rtype, slots_5.io.out_uop.dst_rtype
connect issue_slots[5].out_uop.lrs3, slots_5.io.out_uop.lrs3
connect issue_slots[5].out_uop.lrs2, slots_5.io.out_uop.lrs2
connect issue_slots[5].out_uop.lrs1, slots_5.io.out_uop.lrs1
connect issue_slots[5].out_uop.ldst, slots_5.io.out_uop.ldst
connect issue_slots[5].out_uop.ldst_is_rs1, slots_5.io.out_uop.ldst_is_rs1
connect issue_slots[5].out_uop.csr_cmd, slots_5.io.out_uop.csr_cmd
connect issue_slots[5].out_uop.flush_on_commit, slots_5.io.out_uop.flush_on_commit
connect issue_slots[5].out_uop.is_unique, slots_5.io.out_uop.is_unique
connect issue_slots[5].out_uop.uses_stq, slots_5.io.out_uop.uses_stq
connect issue_slots[5].out_uop.uses_ldq, slots_5.io.out_uop.uses_ldq
connect issue_slots[5].out_uop.mem_signed, slots_5.io.out_uop.mem_signed
connect issue_slots[5].out_uop.mem_size, slots_5.io.out_uop.mem_size
connect issue_slots[5].out_uop.mem_cmd, slots_5.io.out_uop.mem_cmd
connect issue_slots[5].out_uop.exc_cause, slots_5.io.out_uop.exc_cause
connect issue_slots[5].out_uop.exception, slots_5.io.out_uop.exception
connect issue_slots[5].out_uop.stale_pdst, slots_5.io.out_uop.stale_pdst
connect issue_slots[5].out_uop.ppred_busy, slots_5.io.out_uop.ppred_busy
connect issue_slots[5].out_uop.prs3_busy, slots_5.io.out_uop.prs3_busy
connect issue_slots[5].out_uop.prs2_busy, slots_5.io.out_uop.prs2_busy
connect issue_slots[5].out_uop.prs1_busy, slots_5.io.out_uop.prs1_busy
connect issue_slots[5].out_uop.ppred, slots_5.io.out_uop.ppred
connect issue_slots[5].out_uop.prs3, slots_5.io.out_uop.prs3
connect issue_slots[5].out_uop.prs2, slots_5.io.out_uop.prs2
connect issue_slots[5].out_uop.prs1, slots_5.io.out_uop.prs1
connect issue_slots[5].out_uop.pdst, slots_5.io.out_uop.pdst
connect issue_slots[5].out_uop.rxq_idx, slots_5.io.out_uop.rxq_idx
connect issue_slots[5].out_uop.stq_idx, slots_5.io.out_uop.stq_idx
connect issue_slots[5].out_uop.ldq_idx, slots_5.io.out_uop.ldq_idx
connect issue_slots[5].out_uop.rob_idx, slots_5.io.out_uop.rob_idx
connect issue_slots[5].out_uop.fp_ctrl.vec, slots_5.io.out_uop.fp_ctrl.vec
connect issue_slots[5].out_uop.fp_ctrl.wflags, slots_5.io.out_uop.fp_ctrl.wflags
connect issue_slots[5].out_uop.fp_ctrl.sqrt, slots_5.io.out_uop.fp_ctrl.sqrt
connect issue_slots[5].out_uop.fp_ctrl.div, slots_5.io.out_uop.fp_ctrl.div
connect issue_slots[5].out_uop.fp_ctrl.fma, slots_5.io.out_uop.fp_ctrl.fma
connect issue_slots[5].out_uop.fp_ctrl.fastpipe, slots_5.io.out_uop.fp_ctrl.fastpipe
connect issue_slots[5].out_uop.fp_ctrl.toint, slots_5.io.out_uop.fp_ctrl.toint
connect issue_slots[5].out_uop.fp_ctrl.fromint, slots_5.io.out_uop.fp_ctrl.fromint
connect issue_slots[5].out_uop.fp_ctrl.typeTagOut, slots_5.io.out_uop.fp_ctrl.typeTagOut
connect issue_slots[5].out_uop.fp_ctrl.typeTagIn, slots_5.io.out_uop.fp_ctrl.typeTagIn
connect issue_slots[5].out_uop.fp_ctrl.swap23, slots_5.io.out_uop.fp_ctrl.swap23
connect issue_slots[5].out_uop.fp_ctrl.swap12, slots_5.io.out_uop.fp_ctrl.swap12
connect issue_slots[5].out_uop.fp_ctrl.ren3, slots_5.io.out_uop.fp_ctrl.ren3
connect issue_slots[5].out_uop.fp_ctrl.ren2, slots_5.io.out_uop.fp_ctrl.ren2
connect issue_slots[5].out_uop.fp_ctrl.ren1, slots_5.io.out_uop.fp_ctrl.ren1
connect issue_slots[5].out_uop.fp_ctrl.wen, slots_5.io.out_uop.fp_ctrl.wen
connect issue_slots[5].out_uop.fp_ctrl.ldst, slots_5.io.out_uop.fp_ctrl.ldst
connect issue_slots[5].out_uop.op2_sel, slots_5.io.out_uop.op2_sel
connect issue_slots[5].out_uop.op1_sel, slots_5.io.out_uop.op1_sel
connect issue_slots[5].out_uop.imm_packed, slots_5.io.out_uop.imm_packed
connect issue_slots[5].out_uop.pimm, slots_5.io.out_uop.pimm
connect issue_slots[5].out_uop.imm_sel, slots_5.io.out_uop.imm_sel
connect issue_slots[5].out_uop.imm_rename, slots_5.io.out_uop.imm_rename
connect issue_slots[5].out_uop.taken, slots_5.io.out_uop.taken
connect issue_slots[5].out_uop.pc_lob, slots_5.io.out_uop.pc_lob
connect issue_slots[5].out_uop.edge_inst, slots_5.io.out_uop.edge_inst
connect issue_slots[5].out_uop.ftq_idx, slots_5.io.out_uop.ftq_idx
connect issue_slots[5].out_uop.is_mov, slots_5.io.out_uop.is_mov
connect issue_slots[5].out_uop.is_rocc, slots_5.io.out_uop.is_rocc
connect issue_slots[5].out_uop.is_sys_pc2epc, slots_5.io.out_uop.is_sys_pc2epc
connect issue_slots[5].out_uop.is_eret, slots_5.io.out_uop.is_eret
connect issue_slots[5].out_uop.is_amo, slots_5.io.out_uop.is_amo
connect issue_slots[5].out_uop.is_sfence, slots_5.io.out_uop.is_sfence
connect issue_slots[5].out_uop.is_fencei, slots_5.io.out_uop.is_fencei
connect issue_slots[5].out_uop.is_fence, slots_5.io.out_uop.is_fence
connect issue_slots[5].out_uop.is_sfb, slots_5.io.out_uop.is_sfb
connect issue_slots[5].out_uop.br_type, slots_5.io.out_uop.br_type
connect issue_slots[5].out_uop.br_tag, slots_5.io.out_uop.br_tag
connect issue_slots[5].out_uop.br_mask, slots_5.io.out_uop.br_mask
connect issue_slots[5].out_uop.dis_col_sel, slots_5.io.out_uop.dis_col_sel
connect issue_slots[5].out_uop.iw_p3_bypass_hint, slots_5.io.out_uop.iw_p3_bypass_hint
connect issue_slots[5].out_uop.iw_p2_bypass_hint, slots_5.io.out_uop.iw_p2_bypass_hint
connect issue_slots[5].out_uop.iw_p1_bypass_hint, slots_5.io.out_uop.iw_p1_bypass_hint
connect issue_slots[5].out_uop.iw_p2_speculative_child, slots_5.io.out_uop.iw_p2_speculative_child
connect issue_slots[5].out_uop.iw_p1_speculative_child, slots_5.io.out_uop.iw_p1_speculative_child
connect issue_slots[5].out_uop.iw_issued_partial_dgen, slots_5.io.out_uop.iw_issued_partial_dgen
connect issue_slots[5].out_uop.iw_issued_partial_agen, slots_5.io.out_uop.iw_issued_partial_agen
connect issue_slots[5].out_uop.iw_issued, slots_5.io.out_uop.iw_issued
connect issue_slots[5].out_uop.fu_code[0], slots_5.io.out_uop.fu_code[0]
connect issue_slots[5].out_uop.fu_code[1], slots_5.io.out_uop.fu_code[1]
connect issue_slots[5].out_uop.fu_code[2], slots_5.io.out_uop.fu_code[2]
connect issue_slots[5].out_uop.fu_code[3], slots_5.io.out_uop.fu_code[3]
connect issue_slots[5].out_uop.fu_code[4], slots_5.io.out_uop.fu_code[4]
connect issue_slots[5].out_uop.fu_code[5], slots_5.io.out_uop.fu_code[5]
connect issue_slots[5].out_uop.fu_code[6], slots_5.io.out_uop.fu_code[6]
connect issue_slots[5].out_uop.fu_code[7], slots_5.io.out_uop.fu_code[7]
connect issue_slots[5].out_uop.fu_code[8], slots_5.io.out_uop.fu_code[8]
connect issue_slots[5].out_uop.fu_code[9], slots_5.io.out_uop.fu_code[9]
connect issue_slots[5].out_uop.iq_type[0], slots_5.io.out_uop.iq_type[0]
connect issue_slots[5].out_uop.iq_type[1], slots_5.io.out_uop.iq_type[1]
connect issue_slots[5].out_uop.iq_type[2], slots_5.io.out_uop.iq_type[2]
connect issue_slots[5].out_uop.iq_type[3], slots_5.io.out_uop.iq_type[3]
connect issue_slots[5].out_uop.debug_pc, slots_5.io.out_uop.debug_pc
connect issue_slots[5].out_uop.is_rvc, slots_5.io.out_uop.is_rvc
connect issue_slots[5].out_uop.debug_inst, slots_5.io.out_uop.debug_inst
connect issue_slots[5].out_uop.inst, slots_5.io.out_uop.inst
connect slots_5.io.in_uop.bits.debug_tsrc, issue_slots[5].in_uop.bits.debug_tsrc
connect slots_5.io.in_uop.bits.debug_fsrc, issue_slots[5].in_uop.bits.debug_fsrc
connect slots_5.io.in_uop.bits.bp_xcpt_if, issue_slots[5].in_uop.bits.bp_xcpt_if
connect slots_5.io.in_uop.bits.bp_debug_if, issue_slots[5].in_uop.bits.bp_debug_if
connect slots_5.io.in_uop.bits.xcpt_ma_if, issue_slots[5].in_uop.bits.xcpt_ma_if
connect slots_5.io.in_uop.bits.xcpt_ae_if, issue_slots[5].in_uop.bits.xcpt_ae_if
connect slots_5.io.in_uop.bits.xcpt_pf_if, issue_slots[5].in_uop.bits.xcpt_pf_if
connect slots_5.io.in_uop.bits.fp_typ, issue_slots[5].in_uop.bits.fp_typ
connect slots_5.io.in_uop.bits.fp_rm, issue_slots[5].in_uop.bits.fp_rm
connect slots_5.io.in_uop.bits.fp_val, issue_slots[5].in_uop.bits.fp_val
connect slots_5.io.in_uop.bits.fcn_op, issue_slots[5].in_uop.bits.fcn_op
connect slots_5.io.in_uop.bits.fcn_dw, issue_slots[5].in_uop.bits.fcn_dw
connect slots_5.io.in_uop.bits.frs3_en, issue_slots[5].in_uop.bits.frs3_en
connect slots_5.io.in_uop.bits.lrs2_rtype, issue_slots[5].in_uop.bits.lrs2_rtype
connect slots_5.io.in_uop.bits.lrs1_rtype, issue_slots[5].in_uop.bits.lrs1_rtype
connect slots_5.io.in_uop.bits.dst_rtype, issue_slots[5].in_uop.bits.dst_rtype
connect slots_5.io.in_uop.bits.lrs3, issue_slots[5].in_uop.bits.lrs3
connect slots_5.io.in_uop.bits.lrs2, issue_slots[5].in_uop.bits.lrs2
connect slots_5.io.in_uop.bits.lrs1, issue_slots[5].in_uop.bits.lrs1
connect slots_5.io.in_uop.bits.ldst, issue_slots[5].in_uop.bits.ldst
connect slots_5.io.in_uop.bits.ldst_is_rs1, issue_slots[5].in_uop.bits.ldst_is_rs1
connect slots_5.io.in_uop.bits.csr_cmd, issue_slots[5].in_uop.bits.csr_cmd
connect slots_5.io.in_uop.bits.flush_on_commit, issue_slots[5].in_uop.bits.flush_on_commit
connect slots_5.io.in_uop.bits.is_unique, issue_slots[5].in_uop.bits.is_unique
connect slots_5.io.in_uop.bits.uses_stq, issue_slots[5].in_uop.bits.uses_stq
connect slots_5.io.in_uop.bits.uses_ldq, issue_slots[5].in_uop.bits.uses_ldq
connect slots_5.io.in_uop.bits.mem_signed, issue_slots[5].in_uop.bits.mem_signed
connect slots_5.io.in_uop.bits.mem_size, issue_slots[5].in_uop.bits.mem_size
connect slots_5.io.in_uop.bits.mem_cmd, issue_slots[5].in_uop.bits.mem_cmd
connect slots_5.io.in_uop.bits.exc_cause, issue_slots[5].in_uop.bits.exc_cause
connect slots_5.io.in_uop.bits.exception, issue_slots[5].in_uop.bits.exception
connect slots_5.io.in_uop.bits.stale_pdst, issue_slots[5].in_uop.bits.stale_pdst
connect slots_5.io.in_uop.bits.ppred_busy, issue_slots[5].in_uop.bits.ppred_busy
connect slots_5.io.in_uop.bits.prs3_busy, issue_slots[5].in_uop.bits.prs3_busy
connect slots_5.io.in_uop.bits.prs2_busy, issue_slots[5].in_uop.bits.prs2_busy
connect slots_5.io.in_uop.bits.prs1_busy, issue_slots[5].in_uop.bits.prs1_busy
connect slots_5.io.in_uop.bits.ppred, issue_slots[5].in_uop.bits.ppred
connect slots_5.io.in_uop.bits.prs3, issue_slots[5].in_uop.bits.prs3
connect slots_5.io.in_uop.bits.prs2, issue_slots[5].in_uop.bits.prs2
connect slots_5.io.in_uop.bits.prs1, issue_slots[5].in_uop.bits.prs1
connect slots_5.io.in_uop.bits.pdst, issue_slots[5].in_uop.bits.pdst
connect slots_5.io.in_uop.bits.rxq_idx, issue_slots[5].in_uop.bits.rxq_idx
connect slots_5.io.in_uop.bits.stq_idx, issue_slots[5].in_uop.bits.stq_idx
connect slots_5.io.in_uop.bits.ldq_idx, issue_slots[5].in_uop.bits.ldq_idx
connect slots_5.io.in_uop.bits.rob_idx, issue_slots[5].in_uop.bits.rob_idx
connect slots_5.io.in_uop.bits.fp_ctrl.vec, issue_slots[5].in_uop.bits.fp_ctrl.vec
connect slots_5.io.in_uop.bits.fp_ctrl.wflags, issue_slots[5].in_uop.bits.fp_ctrl.wflags
connect slots_5.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[5].in_uop.bits.fp_ctrl.sqrt
connect slots_5.io.in_uop.bits.fp_ctrl.div, issue_slots[5].in_uop.bits.fp_ctrl.div
connect slots_5.io.in_uop.bits.fp_ctrl.fma, issue_slots[5].in_uop.bits.fp_ctrl.fma
connect slots_5.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[5].in_uop.bits.fp_ctrl.fastpipe
connect slots_5.io.in_uop.bits.fp_ctrl.toint, issue_slots[5].in_uop.bits.fp_ctrl.toint
connect slots_5.io.in_uop.bits.fp_ctrl.fromint, issue_slots[5].in_uop.bits.fp_ctrl.fromint
connect slots_5.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[5].in_uop.bits.fp_ctrl.typeTagOut
connect slots_5.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[5].in_uop.bits.fp_ctrl.typeTagIn
connect slots_5.io.in_uop.bits.fp_ctrl.swap23, issue_slots[5].in_uop.bits.fp_ctrl.swap23
connect slots_5.io.in_uop.bits.fp_ctrl.swap12, issue_slots[5].in_uop.bits.fp_ctrl.swap12
connect slots_5.io.in_uop.bits.fp_ctrl.ren3, issue_slots[5].in_uop.bits.fp_ctrl.ren3
connect slots_5.io.in_uop.bits.fp_ctrl.ren2, issue_slots[5].in_uop.bits.fp_ctrl.ren2
connect slots_5.io.in_uop.bits.fp_ctrl.ren1, issue_slots[5].in_uop.bits.fp_ctrl.ren1
connect slots_5.io.in_uop.bits.fp_ctrl.wen, issue_slots[5].in_uop.bits.fp_ctrl.wen
connect slots_5.io.in_uop.bits.fp_ctrl.ldst, issue_slots[5].in_uop.bits.fp_ctrl.ldst
connect slots_5.io.in_uop.bits.op2_sel, issue_slots[5].in_uop.bits.op2_sel
connect slots_5.io.in_uop.bits.op1_sel, issue_slots[5].in_uop.bits.op1_sel
connect slots_5.io.in_uop.bits.imm_packed, issue_slots[5].in_uop.bits.imm_packed
connect slots_5.io.in_uop.bits.pimm, issue_slots[5].in_uop.bits.pimm
connect slots_5.io.in_uop.bits.imm_sel, issue_slots[5].in_uop.bits.imm_sel
connect slots_5.io.in_uop.bits.imm_rename, issue_slots[5].in_uop.bits.imm_rename
connect slots_5.io.in_uop.bits.taken, issue_slots[5].in_uop.bits.taken
connect slots_5.io.in_uop.bits.pc_lob, issue_slots[5].in_uop.bits.pc_lob
connect slots_5.io.in_uop.bits.edge_inst, issue_slots[5].in_uop.bits.edge_inst
connect slots_5.io.in_uop.bits.ftq_idx, issue_slots[5].in_uop.bits.ftq_idx
connect slots_5.io.in_uop.bits.is_mov, issue_slots[5].in_uop.bits.is_mov
connect slots_5.io.in_uop.bits.is_rocc, issue_slots[5].in_uop.bits.is_rocc
connect slots_5.io.in_uop.bits.is_sys_pc2epc, issue_slots[5].in_uop.bits.is_sys_pc2epc
connect slots_5.io.in_uop.bits.is_eret, issue_slots[5].in_uop.bits.is_eret
connect slots_5.io.in_uop.bits.is_amo, issue_slots[5].in_uop.bits.is_amo
connect slots_5.io.in_uop.bits.is_sfence, issue_slots[5].in_uop.bits.is_sfence
connect slots_5.io.in_uop.bits.is_fencei, issue_slots[5].in_uop.bits.is_fencei
connect slots_5.io.in_uop.bits.is_fence, issue_slots[5].in_uop.bits.is_fence
connect slots_5.io.in_uop.bits.is_sfb, issue_slots[5].in_uop.bits.is_sfb
connect slots_5.io.in_uop.bits.br_type, issue_slots[5].in_uop.bits.br_type
connect slots_5.io.in_uop.bits.br_tag, issue_slots[5].in_uop.bits.br_tag
connect slots_5.io.in_uop.bits.br_mask, issue_slots[5].in_uop.bits.br_mask
connect slots_5.io.in_uop.bits.dis_col_sel, issue_slots[5].in_uop.bits.dis_col_sel
connect slots_5.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[5].in_uop.bits.iw_p3_bypass_hint
connect slots_5.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[5].in_uop.bits.iw_p2_bypass_hint
connect slots_5.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[5].in_uop.bits.iw_p1_bypass_hint
connect slots_5.io.in_uop.bits.iw_p2_speculative_child, issue_slots[5].in_uop.bits.iw_p2_speculative_child
connect slots_5.io.in_uop.bits.iw_p1_speculative_child, issue_slots[5].in_uop.bits.iw_p1_speculative_child
connect slots_5.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[5].in_uop.bits.iw_issued_partial_dgen
connect slots_5.io.in_uop.bits.iw_issued_partial_agen, issue_slots[5].in_uop.bits.iw_issued_partial_agen
connect slots_5.io.in_uop.bits.iw_issued, issue_slots[5].in_uop.bits.iw_issued
connect slots_5.io.in_uop.bits.fu_code[0], issue_slots[5].in_uop.bits.fu_code[0]
connect slots_5.io.in_uop.bits.fu_code[1], issue_slots[5].in_uop.bits.fu_code[1]
connect slots_5.io.in_uop.bits.fu_code[2], issue_slots[5].in_uop.bits.fu_code[2]
connect slots_5.io.in_uop.bits.fu_code[3], issue_slots[5].in_uop.bits.fu_code[3]
connect slots_5.io.in_uop.bits.fu_code[4], issue_slots[5].in_uop.bits.fu_code[4]
connect slots_5.io.in_uop.bits.fu_code[5], issue_slots[5].in_uop.bits.fu_code[5]
connect slots_5.io.in_uop.bits.fu_code[6], issue_slots[5].in_uop.bits.fu_code[6]
connect slots_5.io.in_uop.bits.fu_code[7], issue_slots[5].in_uop.bits.fu_code[7]
connect slots_5.io.in_uop.bits.fu_code[8], issue_slots[5].in_uop.bits.fu_code[8]
connect slots_5.io.in_uop.bits.fu_code[9], issue_slots[5].in_uop.bits.fu_code[9]
connect slots_5.io.in_uop.bits.iq_type[0], issue_slots[5].in_uop.bits.iq_type[0]
connect slots_5.io.in_uop.bits.iq_type[1], issue_slots[5].in_uop.bits.iq_type[1]
connect slots_5.io.in_uop.bits.iq_type[2], issue_slots[5].in_uop.bits.iq_type[2]
connect slots_5.io.in_uop.bits.iq_type[3], issue_slots[5].in_uop.bits.iq_type[3]
connect slots_5.io.in_uop.bits.debug_pc, issue_slots[5].in_uop.bits.debug_pc
connect slots_5.io.in_uop.bits.is_rvc, issue_slots[5].in_uop.bits.is_rvc
connect slots_5.io.in_uop.bits.debug_inst, issue_slots[5].in_uop.bits.debug_inst
connect slots_5.io.in_uop.bits.inst, issue_slots[5].in_uop.bits.inst
connect slots_5.io.in_uop.valid, issue_slots[5].in_uop.valid
connect issue_slots[5].iss_uop.debug_tsrc, slots_5.io.iss_uop.debug_tsrc
connect issue_slots[5].iss_uop.debug_fsrc, slots_5.io.iss_uop.debug_fsrc
connect issue_slots[5].iss_uop.bp_xcpt_if, slots_5.io.iss_uop.bp_xcpt_if
connect issue_slots[5].iss_uop.bp_debug_if, slots_5.io.iss_uop.bp_debug_if
connect issue_slots[5].iss_uop.xcpt_ma_if, slots_5.io.iss_uop.xcpt_ma_if
connect issue_slots[5].iss_uop.xcpt_ae_if, slots_5.io.iss_uop.xcpt_ae_if
connect issue_slots[5].iss_uop.xcpt_pf_if, slots_5.io.iss_uop.xcpt_pf_if
connect issue_slots[5].iss_uop.fp_typ, slots_5.io.iss_uop.fp_typ
connect issue_slots[5].iss_uop.fp_rm, slots_5.io.iss_uop.fp_rm
connect issue_slots[5].iss_uop.fp_val, slots_5.io.iss_uop.fp_val
connect issue_slots[5].iss_uop.fcn_op, slots_5.io.iss_uop.fcn_op
connect issue_slots[5].iss_uop.fcn_dw, slots_5.io.iss_uop.fcn_dw
connect issue_slots[5].iss_uop.frs3_en, slots_5.io.iss_uop.frs3_en
connect issue_slots[5].iss_uop.lrs2_rtype, slots_5.io.iss_uop.lrs2_rtype
connect issue_slots[5].iss_uop.lrs1_rtype, slots_5.io.iss_uop.lrs1_rtype
connect issue_slots[5].iss_uop.dst_rtype, slots_5.io.iss_uop.dst_rtype
connect issue_slots[5].iss_uop.lrs3, slots_5.io.iss_uop.lrs3
connect issue_slots[5].iss_uop.lrs2, slots_5.io.iss_uop.lrs2
connect issue_slots[5].iss_uop.lrs1, slots_5.io.iss_uop.lrs1
connect issue_slots[5].iss_uop.ldst, slots_5.io.iss_uop.ldst
connect issue_slots[5].iss_uop.ldst_is_rs1, slots_5.io.iss_uop.ldst_is_rs1
connect issue_slots[5].iss_uop.csr_cmd, slots_5.io.iss_uop.csr_cmd
connect issue_slots[5].iss_uop.flush_on_commit, slots_5.io.iss_uop.flush_on_commit
connect issue_slots[5].iss_uop.is_unique, slots_5.io.iss_uop.is_unique
connect issue_slots[5].iss_uop.uses_stq, slots_5.io.iss_uop.uses_stq
connect issue_slots[5].iss_uop.uses_ldq, slots_5.io.iss_uop.uses_ldq
connect issue_slots[5].iss_uop.mem_signed, slots_5.io.iss_uop.mem_signed
connect issue_slots[5].iss_uop.mem_size, slots_5.io.iss_uop.mem_size
connect issue_slots[5].iss_uop.mem_cmd, slots_5.io.iss_uop.mem_cmd
connect issue_slots[5].iss_uop.exc_cause, slots_5.io.iss_uop.exc_cause
connect issue_slots[5].iss_uop.exception, slots_5.io.iss_uop.exception
connect issue_slots[5].iss_uop.stale_pdst, slots_5.io.iss_uop.stale_pdst
connect issue_slots[5].iss_uop.ppred_busy, slots_5.io.iss_uop.ppred_busy
connect issue_slots[5].iss_uop.prs3_busy, slots_5.io.iss_uop.prs3_busy
connect issue_slots[5].iss_uop.prs2_busy, slots_5.io.iss_uop.prs2_busy
connect issue_slots[5].iss_uop.prs1_busy, slots_5.io.iss_uop.prs1_busy
connect issue_slots[5].iss_uop.ppred, slots_5.io.iss_uop.ppred
connect issue_slots[5].iss_uop.prs3, slots_5.io.iss_uop.prs3
connect issue_slots[5].iss_uop.prs2, slots_5.io.iss_uop.prs2
connect issue_slots[5].iss_uop.prs1, slots_5.io.iss_uop.prs1
connect issue_slots[5].iss_uop.pdst, slots_5.io.iss_uop.pdst
connect issue_slots[5].iss_uop.rxq_idx, slots_5.io.iss_uop.rxq_idx
connect issue_slots[5].iss_uop.stq_idx, slots_5.io.iss_uop.stq_idx
connect issue_slots[5].iss_uop.ldq_idx, slots_5.io.iss_uop.ldq_idx
connect issue_slots[5].iss_uop.rob_idx, slots_5.io.iss_uop.rob_idx
connect issue_slots[5].iss_uop.fp_ctrl.vec, slots_5.io.iss_uop.fp_ctrl.vec
connect issue_slots[5].iss_uop.fp_ctrl.wflags, slots_5.io.iss_uop.fp_ctrl.wflags
connect issue_slots[5].iss_uop.fp_ctrl.sqrt, slots_5.io.iss_uop.fp_ctrl.sqrt
connect issue_slots[5].iss_uop.fp_ctrl.div, slots_5.io.iss_uop.fp_ctrl.div
connect issue_slots[5].iss_uop.fp_ctrl.fma, slots_5.io.iss_uop.fp_ctrl.fma
connect issue_slots[5].iss_uop.fp_ctrl.fastpipe, slots_5.io.iss_uop.fp_ctrl.fastpipe
connect issue_slots[5].iss_uop.fp_ctrl.toint, slots_5.io.iss_uop.fp_ctrl.toint
connect issue_slots[5].iss_uop.fp_ctrl.fromint, slots_5.io.iss_uop.fp_ctrl.fromint
connect issue_slots[5].iss_uop.fp_ctrl.typeTagOut, slots_5.io.iss_uop.fp_ctrl.typeTagOut
connect issue_slots[5].iss_uop.fp_ctrl.typeTagIn, slots_5.io.iss_uop.fp_ctrl.typeTagIn
connect issue_slots[5].iss_uop.fp_ctrl.swap23, slots_5.io.iss_uop.fp_ctrl.swap23
connect issue_slots[5].iss_uop.fp_ctrl.swap12, slots_5.io.iss_uop.fp_ctrl.swap12
connect issue_slots[5].iss_uop.fp_ctrl.ren3, slots_5.io.iss_uop.fp_ctrl.ren3
connect issue_slots[5].iss_uop.fp_ctrl.ren2, slots_5.io.iss_uop.fp_ctrl.ren2
connect issue_slots[5].iss_uop.fp_ctrl.ren1, slots_5.io.iss_uop.fp_ctrl.ren1
connect issue_slots[5].iss_uop.fp_ctrl.wen, slots_5.io.iss_uop.fp_ctrl.wen
connect issue_slots[5].iss_uop.fp_ctrl.ldst, slots_5.io.iss_uop.fp_ctrl.ldst
connect issue_slots[5].iss_uop.op2_sel, slots_5.io.iss_uop.op2_sel
connect issue_slots[5].iss_uop.op1_sel, slots_5.io.iss_uop.op1_sel
connect issue_slots[5].iss_uop.imm_packed, slots_5.io.iss_uop.imm_packed
connect issue_slots[5].iss_uop.pimm, slots_5.io.iss_uop.pimm
connect issue_slots[5].iss_uop.imm_sel, slots_5.io.iss_uop.imm_sel
connect issue_slots[5].iss_uop.imm_rename, slots_5.io.iss_uop.imm_rename
connect issue_slots[5].iss_uop.taken, slots_5.io.iss_uop.taken
connect issue_slots[5].iss_uop.pc_lob, slots_5.io.iss_uop.pc_lob
connect issue_slots[5].iss_uop.edge_inst, slots_5.io.iss_uop.edge_inst
connect issue_slots[5].iss_uop.ftq_idx, slots_5.io.iss_uop.ftq_idx
connect issue_slots[5].iss_uop.is_mov, slots_5.io.iss_uop.is_mov
connect issue_slots[5].iss_uop.is_rocc, slots_5.io.iss_uop.is_rocc
connect issue_slots[5].iss_uop.is_sys_pc2epc, slots_5.io.iss_uop.is_sys_pc2epc
connect issue_slots[5].iss_uop.is_eret, slots_5.io.iss_uop.is_eret
connect issue_slots[5].iss_uop.is_amo, slots_5.io.iss_uop.is_amo
connect issue_slots[5].iss_uop.is_sfence, slots_5.io.iss_uop.is_sfence
connect issue_slots[5].iss_uop.is_fencei, slots_5.io.iss_uop.is_fencei
connect issue_slots[5].iss_uop.is_fence, slots_5.io.iss_uop.is_fence
connect issue_slots[5].iss_uop.is_sfb, slots_5.io.iss_uop.is_sfb
connect issue_slots[5].iss_uop.br_type, slots_5.io.iss_uop.br_type
connect issue_slots[5].iss_uop.br_tag, slots_5.io.iss_uop.br_tag
connect issue_slots[5].iss_uop.br_mask, slots_5.io.iss_uop.br_mask
connect issue_slots[5].iss_uop.dis_col_sel, slots_5.io.iss_uop.dis_col_sel
connect issue_slots[5].iss_uop.iw_p3_bypass_hint, slots_5.io.iss_uop.iw_p3_bypass_hint
connect issue_slots[5].iss_uop.iw_p2_bypass_hint, slots_5.io.iss_uop.iw_p2_bypass_hint
connect issue_slots[5].iss_uop.iw_p1_bypass_hint, slots_5.io.iss_uop.iw_p1_bypass_hint
connect issue_slots[5].iss_uop.iw_p2_speculative_child, slots_5.io.iss_uop.iw_p2_speculative_child
connect issue_slots[5].iss_uop.iw_p1_speculative_child, slots_5.io.iss_uop.iw_p1_speculative_child
connect issue_slots[5].iss_uop.iw_issued_partial_dgen, slots_5.io.iss_uop.iw_issued_partial_dgen
connect issue_slots[5].iss_uop.iw_issued_partial_agen, slots_5.io.iss_uop.iw_issued_partial_agen
connect issue_slots[5].iss_uop.iw_issued, slots_5.io.iss_uop.iw_issued
connect issue_slots[5].iss_uop.fu_code[0], slots_5.io.iss_uop.fu_code[0]
connect issue_slots[5].iss_uop.fu_code[1], slots_5.io.iss_uop.fu_code[1]
connect issue_slots[5].iss_uop.fu_code[2], slots_5.io.iss_uop.fu_code[2]
connect issue_slots[5].iss_uop.fu_code[3], slots_5.io.iss_uop.fu_code[3]
connect issue_slots[5].iss_uop.fu_code[4], slots_5.io.iss_uop.fu_code[4]
connect issue_slots[5].iss_uop.fu_code[5], slots_5.io.iss_uop.fu_code[5]
connect issue_slots[5].iss_uop.fu_code[6], slots_5.io.iss_uop.fu_code[6]
connect issue_slots[5].iss_uop.fu_code[7], slots_5.io.iss_uop.fu_code[7]
connect issue_slots[5].iss_uop.fu_code[8], slots_5.io.iss_uop.fu_code[8]
connect issue_slots[5].iss_uop.fu_code[9], slots_5.io.iss_uop.fu_code[9]
connect issue_slots[5].iss_uop.iq_type[0], slots_5.io.iss_uop.iq_type[0]
connect issue_slots[5].iss_uop.iq_type[1], slots_5.io.iss_uop.iq_type[1]
connect issue_slots[5].iss_uop.iq_type[2], slots_5.io.iss_uop.iq_type[2]
connect issue_slots[5].iss_uop.iq_type[3], slots_5.io.iss_uop.iq_type[3]
connect issue_slots[5].iss_uop.debug_pc, slots_5.io.iss_uop.debug_pc
connect issue_slots[5].iss_uop.is_rvc, slots_5.io.iss_uop.is_rvc
connect issue_slots[5].iss_uop.debug_inst, slots_5.io.iss_uop.debug_inst
connect issue_slots[5].iss_uop.inst, slots_5.io.iss_uop.inst
connect slots_5.io.grant, issue_slots[5].grant
connect issue_slots[5].request, slots_5.io.request
connect issue_slots[5].will_be_valid, slots_5.io.will_be_valid
connect issue_slots[5].valid, slots_5.io.valid
connect slots_6.io.child_rebusys, issue_slots[6].child_rebusys
connect slots_6.io.pred_wakeup_port.bits, issue_slots[6].pred_wakeup_port.bits
connect slots_6.io.pred_wakeup_port.valid, issue_slots[6].pred_wakeup_port.valid
connect slots_6.io.wakeup_ports[0].bits.rebusy, issue_slots[6].wakeup_ports[0].bits.rebusy
connect slots_6.io.wakeup_ports[0].bits.speculative_mask, issue_slots[6].wakeup_ports[0].bits.speculative_mask
connect slots_6.io.wakeup_ports[0].bits.bypassable, issue_slots[6].wakeup_ports[0].bits.bypassable
connect slots_6.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[6].wakeup_ports[0].bits.uop.debug_tsrc
connect slots_6.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[6].wakeup_ports[0].bits.uop.debug_fsrc
connect slots_6.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[6].wakeup_ports[0].bits.uop.bp_xcpt_if
connect slots_6.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[6].wakeup_ports[0].bits.uop.bp_debug_if
connect slots_6.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[6].wakeup_ports[0].bits.uop.xcpt_ma_if
connect slots_6.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[6].wakeup_ports[0].bits.uop.xcpt_ae_if
connect slots_6.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[6].wakeup_ports[0].bits.uop.xcpt_pf_if
connect slots_6.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[6].wakeup_ports[0].bits.uop.fp_typ
connect slots_6.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[6].wakeup_ports[0].bits.uop.fp_rm
connect slots_6.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[6].wakeup_ports[0].bits.uop.fp_val
connect slots_6.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[6].wakeup_ports[0].bits.uop.fcn_op
connect slots_6.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[6].wakeup_ports[0].bits.uop.fcn_dw
connect slots_6.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[6].wakeup_ports[0].bits.uop.frs3_en
connect slots_6.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[6].wakeup_ports[0].bits.uop.lrs2_rtype
connect slots_6.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[6].wakeup_ports[0].bits.uop.lrs1_rtype
connect slots_6.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[6].wakeup_ports[0].bits.uop.dst_rtype
connect slots_6.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[6].wakeup_ports[0].bits.uop.lrs3
connect slots_6.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[6].wakeup_ports[0].bits.uop.lrs2
connect slots_6.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[6].wakeup_ports[0].bits.uop.lrs1
connect slots_6.io.wakeup_ports[0].bits.uop.ldst, issue_slots[6].wakeup_ports[0].bits.uop.ldst
connect slots_6.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[6].wakeup_ports[0].bits.uop.ldst_is_rs1
connect slots_6.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[6].wakeup_ports[0].bits.uop.csr_cmd
connect slots_6.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[6].wakeup_ports[0].bits.uop.flush_on_commit
connect slots_6.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[6].wakeup_ports[0].bits.uop.is_unique
connect slots_6.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[6].wakeup_ports[0].bits.uop.uses_stq
connect slots_6.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[6].wakeup_ports[0].bits.uop.uses_ldq
connect slots_6.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[6].wakeup_ports[0].bits.uop.mem_signed
connect slots_6.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[6].wakeup_ports[0].bits.uop.mem_size
connect slots_6.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[6].wakeup_ports[0].bits.uop.mem_cmd
connect slots_6.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[6].wakeup_ports[0].bits.uop.exc_cause
connect slots_6.io.wakeup_ports[0].bits.uop.exception, issue_slots[6].wakeup_ports[0].bits.uop.exception
connect slots_6.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[6].wakeup_ports[0].bits.uop.stale_pdst
connect slots_6.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[6].wakeup_ports[0].bits.uop.ppred_busy
connect slots_6.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[6].wakeup_ports[0].bits.uop.prs3_busy
connect slots_6.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[6].wakeup_ports[0].bits.uop.prs2_busy
connect slots_6.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[6].wakeup_ports[0].bits.uop.prs1_busy
connect slots_6.io.wakeup_ports[0].bits.uop.ppred, issue_slots[6].wakeup_ports[0].bits.uop.ppred
connect slots_6.io.wakeup_ports[0].bits.uop.prs3, issue_slots[6].wakeup_ports[0].bits.uop.prs3
connect slots_6.io.wakeup_ports[0].bits.uop.prs2, issue_slots[6].wakeup_ports[0].bits.uop.prs2
connect slots_6.io.wakeup_ports[0].bits.uop.prs1, issue_slots[6].wakeup_ports[0].bits.uop.prs1
connect slots_6.io.wakeup_ports[0].bits.uop.pdst, issue_slots[6].wakeup_ports[0].bits.uop.pdst
connect slots_6.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[6].wakeup_ports[0].bits.uop.rxq_idx
connect slots_6.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[6].wakeup_ports[0].bits.uop.stq_idx
connect slots_6.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[6].wakeup_ports[0].bits.uop.ldq_idx
connect slots_6.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[6].wakeup_ports[0].bits.uop.rob_idx
connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.vec
connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.wflags
connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.sqrt
connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.div
connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.fma
connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe
connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.toint
connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.fromint
connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut
connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn
connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.swap23
connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.swap12
connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.ren3
connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.ren2
connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.ren1
connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.wen
connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.ldst
connect slots_6.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[6].wakeup_ports[0].bits.uop.op2_sel
connect slots_6.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[6].wakeup_ports[0].bits.uop.op1_sel
connect slots_6.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[6].wakeup_ports[0].bits.uop.imm_packed
connect slots_6.io.wakeup_ports[0].bits.uop.pimm, issue_slots[6].wakeup_ports[0].bits.uop.pimm
connect slots_6.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[6].wakeup_ports[0].bits.uop.imm_sel
connect slots_6.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[6].wakeup_ports[0].bits.uop.imm_rename
connect slots_6.io.wakeup_ports[0].bits.uop.taken, issue_slots[6].wakeup_ports[0].bits.uop.taken
connect slots_6.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[6].wakeup_ports[0].bits.uop.pc_lob
connect slots_6.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[6].wakeup_ports[0].bits.uop.edge_inst
connect slots_6.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[6].wakeup_ports[0].bits.uop.ftq_idx
connect slots_6.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[6].wakeup_ports[0].bits.uop.is_mov
connect slots_6.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[6].wakeup_ports[0].bits.uop.is_rocc
connect slots_6.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[6].wakeup_ports[0].bits.uop.is_sys_pc2epc
connect slots_6.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[6].wakeup_ports[0].bits.uop.is_eret
connect slots_6.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[6].wakeup_ports[0].bits.uop.is_amo
connect slots_6.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[6].wakeup_ports[0].bits.uop.is_sfence
connect slots_6.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[6].wakeup_ports[0].bits.uop.is_fencei
connect slots_6.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[6].wakeup_ports[0].bits.uop.is_fence
connect slots_6.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[6].wakeup_ports[0].bits.uop.is_sfb
connect slots_6.io.wakeup_ports[0].bits.uop.br_type, issue_slots[6].wakeup_ports[0].bits.uop.br_type
connect slots_6.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[6].wakeup_ports[0].bits.uop.br_tag
connect slots_6.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[6].wakeup_ports[0].bits.uop.br_mask
connect slots_6.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[6].wakeup_ports[0].bits.uop.dis_col_sel
connect slots_6.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[6].wakeup_ports[0].bits.uop.iw_p3_bypass_hint
connect slots_6.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[6].wakeup_ports[0].bits.uop.iw_p2_bypass_hint
connect slots_6.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[6].wakeup_ports[0].bits.uop.iw_p1_bypass_hint
connect slots_6.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[6].wakeup_ports[0].bits.uop.iw_p2_speculative_child
connect slots_6.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[6].wakeup_ports[0].bits.uop.iw_p1_speculative_child
connect slots_6.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[6].wakeup_ports[0].bits.uop.iw_issued_partial_dgen
connect slots_6.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[6].wakeup_ports[0].bits.uop.iw_issued_partial_agen
connect slots_6.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[6].wakeup_ports[0].bits.uop.iw_issued
connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[0]
connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[1]
connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[2]
connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[3]
connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[4]
connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[5]
connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[6]
connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[7]
connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[8]
connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[9]
connect slots_6.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[6].wakeup_ports[0].bits.uop.iq_type[0]
connect slots_6.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[6].wakeup_ports[0].bits.uop.iq_type[1]
connect slots_6.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[6].wakeup_ports[0].bits.uop.iq_type[2]
connect slots_6.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[6].wakeup_ports[0].bits.uop.iq_type[3]
connect slots_6.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[6].wakeup_ports[0].bits.uop.debug_pc
connect slots_6.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[6].wakeup_ports[0].bits.uop.is_rvc
connect slots_6.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[6].wakeup_ports[0].bits.uop.debug_inst
connect slots_6.io.wakeup_ports[0].bits.uop.inst, issue_slots[6].wakeup_ports[0].bits.uop.inst
connect slots_6.io.wakeup_ports[0].valid, issue_slots[6].wakeup_ports[0].valid
connect slots_6.io.wakeup_ports[1].bits.rebusy, issue_slots[6].wakeup_ports[1].bits.rebusy
connect slots_6.io.wakeup_ports[1].bits.speculative_mask, issue_slots[6].wakeup_ports[1].bits.speculative_mask
connect slots_6.io.wakeup_ports[1].bits.bypassable, issue_slots[6].wakeup_ports[1].bits.bypassable
connect slots_6.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[6].wakeup_ports[1].bits.uop.debug_tsrc
connect slots_6.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[6].wakeup_ports[1].bits.uop.debug_fsrc
connect slots_6.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[6].wakeup_ports[1].bits.uop.bp_xcpt_if
connect slots_6.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[6].wakeup_ports[1].bits.uop.bp_debug_if
connect slots_6.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[6].wakeup_ports[1].bits.uop.xcpt_ma_if
connect slots_6.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[6].wakeup_ports[1].bits.uop.xcpt_ae_if
connect slots_6.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[6].wakeup_ports[1].bits.uop.xcpt_pf_if
connect slots_6.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[6].wakeup_ports[1].bits.uop.fp_typ
connect slots_6.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[6].wakeup_ports[1].bits.uop.fp_rm
connect slots_6.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[6].wakeup_ports[1].bits.uop.fp_val
connect slots_6.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[6].wakeup_ports[1].bits.uop.fcn_op
connect slots_6.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[6].wakeup_ports[1].bits.uop.fcn_dw
connect slots_6.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[6].wakeup_ports[1].bits.uop.frs3_en
connect slots_6.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[6].wakeup_ports[1].bits.uop.lrs2_rtype
connect slots_6.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[6].wakeup_ports[1].bits.uop.lrs1_rtype
connect slots_6.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[6].wakeup_ports[1].bits.uop.dst_rtype
connect slots_6.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[6].wakeup_ports[1].bits.uop.lrs3
connect slots_6.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[6].wakeup_ports[1].bits.uop.lrs2
connect slots_6.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[6].wakeup_ports[1].bits.uop.lrs1
connect slots_6.io.wakeup_ports[1].bits.uop.ldst, issue_slots[6].wakeup_ports[1].bits.uop.ldst
connect slots_6.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[6].wakeup_ports[1].bits.uop.ldst_is_rs1
connect slots_6.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[6].wakeup_ports[1].bits.uop.csr_cmd
connect slots_6.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[6].wakeup_ports[1].bits.uop.flush_on_commit
connect slots_6.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[6].wakeup_ports[1].bits.uop.is_unique
connect slots_6.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[6].wakeup_ports[1].bits.uop.uses_stq
connect slots_6.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[6].wakeup_ports[1].bits.uop.uses_ldq
connect slots_6.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[6].wakeup_ports[1].bits.uop.mem_signed
connect slots_6.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[6].wakeup_ports[1].bits.uop.mem_size
connect slots_6.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[6].wakeup_ports[1].bits.uop.mem_cmd
connect slots_6.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[6].wakeup_ports[1].bits.uop.exc_cause
connect slots_6.io.wakeup_ports[1].bits.uop.exception, issue_slots[6].wakeup_ports[1].bits.uop.exception
connect slots_6.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[6].wakeup_ports[1].bits.uop.stale_pdst
connect slots_6.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[6].wakeup_ports[1].bits.uop.ppred_busy
connect slots_6.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[6].wakeup_ports[1].bits.uop.prs3_busy
connect slots_6.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[6].wakeup_ports[1].bits.uop.prs2_busy
connect slots_6.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[6].wakeup_ports[1].bits.uop.prs1_busy
connect slots_6.io.wakeup_ports[1].bits.uop.ppred, issue_slots[6].wakeup_ports[1].bits.uop.ppred
connect slots_6.io.wakeup_ports[1].bits.uop.prs3, issue_slots[6].wakeup_ports[1].bits.uop.prs3
connect slots_6.io.wakeup_ports[1].bits.uop.prs2, issue_slots[6].wakeup_ports[1].bits.uop.prs2
connect slots_6.io.wakeup_ports[1].bits.uop.prs1, issue_slots[6].wakeup_ports[1].bits.uop.prs1
connect slots_6.io.wakeup_ports[1].bits.uop.pdst, issue_slots[6].wakeup_ports[1].bits.uop.pdst
connect slots_6.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[6].wakeup_ports[1].bits.uop.rxq_idx
connect slots_6.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[6].wakeup_ports[1].bits.uop.stq_idx
connect slots_6.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[6].wakeup_ports[1].bits.uop.ldq_idx
connect slots_6.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[6].wakeup_ports[1].bits.uop.rob_idx
connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.vec
connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.wflags
connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.sqrt
connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.div
connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.fma
connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe
connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.toint
connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.fromint
connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut
connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn
connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.swap23
connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.swap12
connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.ren3
connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.ren2
connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.ren1
connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.wen
connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.ldst
connect slots_6.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[6].wakeup_ports[1].bits.uop.op2_sel
connect slots_6.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[6].wakeup_ports[1].bits.uop.op1_sel
connect slots_6.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[6].wakeup_ports[1].bits.uop.imm_packed
connect slots_6.io.wakeup_ports[1].bits.uop.pimm, issue_slots[6].wakeup_ports[1].bits.uop.pimm
connect slots_6.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[6].wakeup_ports[1].bits.uop.imm_sel
connect slots_6.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[6].wakeup_ports[1].bits.uop.imm_rename
connect slots_6.io.wakeup_ports[1].bits.uop.taken, issue_slots[6].wakeup_ports[1].bits.uop.taken
connect slots_6.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[6].wakeup_ports[1].bits.uop.pc_lob
connect slots_6.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[6].wakeup_ports[1].bits.uop.edge_inst
connect slots_6.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[6].wakeup_ports[1].bits.uop.ftq_idx
connect slots_6.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[6].wakeup_ports[1].bits.uop.is_mov
connect slots_6.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[6].wakeup_ports[1].bits.uop.is_rocc
connect slots_6.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[6].wakeup_ports[1].bits.uop.is_sys_pc2epc
connect slots_6.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[6].wakeup_ports[1].bits.uop.is_eret
connect slots_6.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[6].wakeup_ports[1].bits.uop.is_amo
connect slots_6.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[6].wakeup_ports[1].bits.uop.is_sfence
connect slots_6.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[6].wakeup_ports[1].bits.uop.is_fencei
connect slots_6.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[6].wakeup_ports[1].bits.uop.is_fence
connect slots_6.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[6].wakeup_ports[1].bits.uop.is_sfb
connect slots_6.io.wakeup_ports[1].bits.uop.br_type, issue_slots[6].wakeup_ports[1].bits.uop.br_type
connect slots_6.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[6].wakeup_ports[1].bits.uop.br_tag
connect slots_6.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[6].wakeup_ports[1].bits.uop.br_mask
connect slots_6.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[6].wakeup_ports[1].bits.uop.dis_col_sel
connect slots_6.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[6].wakeup_ports[1].bits.uop.iw_p3_bypass_hint
connect slots_6.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[6].wakeup_ports[1].bits.uop.iw_p2_bypass_hint
connect slots_6.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[6].wakeup_ports[1].bits.uop.iw_p1_bypass_hint
connect slots_6.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[6].wakeup_ports[1].bits.uop.iw_p2_speculative_child
connect slots_6.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[6].wakeup_ports[1].bits.uop.iw_p1_speculative_child
connect slots_6.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[6].wakeup_ports[1].bits.uop.iw_issued_partial_dgen
connect slots_6.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[6].wakeup_ports[1].bits.uop.iw_issued_partial_agen
connect slots_6.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[6].wakeup_ports[1].bits.uop.iw_issued
connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[0]
connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[1]
connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[2]
connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[3]
connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[4]
connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[5]
connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[6]
connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[7]
connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[8]
connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[9]
connect slots_6.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[6].wakeup_ports[1].bits.uop.iq_type[0]
connect slots_6.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[6].wakeup_ports[1].bits.uop.iq_type[1]
connect slots_6.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[6].wakeup_ports[1].bits.uop.iq_type[2]
connect slots_6.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[6].wakeup_ports[1].bits.uop.iq_type[3]
connect slots_6.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[6].wakeup_ports[1].bits.uop.debug_pc
connect slots_6.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[6].wakeup_ports[1].bits.uop.is_rvc
connect slots_6.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[6].wakeup_ports[1].bits.uop.debug_inst
connect slots_6.io.wakeup_ports[1].bits.uop.inst, issue_slots[6].wakeup_ports[1].bits.uop.inst
connect slots_6.io.wakeup_ports[1].valid, issue_slots[6].wakeup_ports[1].valid
connect slots_6.io.wakeup_ports[2].bits.rebusy, issue_slots[6].wakeup_ports[2].bits.rebusy
connect slots_6.io.wakeup_ports[2].bits.speculative_mask, issue_slots[6].wakeup_ports[2].bits.speculative_mask
connect slots_6.io.wakeup_ports[2].bits.bypassable, issue_slots[6].wakeup_ports[2].bits.bypassable
connect slots_6.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[6].wakeup_ports[2].bits.uop.debug_tsrc
connect slots_6.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[6].wakeup_ports[2].bits.uop.debug_fsrc
connect slots_6.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[6].wakeup_ports[2].bits.uop.bp_xcpt_if
connect slots_6.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[6].wakeup_ports[2].bits.uop.bp_debug_if
connect slots_6.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[6].wakeup_ports[2].bits.uop.xcpt_ma_if
connect slots_6.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[6].wakeup_ports[2].bits.uop.xcpt_ae_if
connect slots_6.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[6].wakeup_ports[2].bits.uop.xcpt_pf_if
connect slots_6.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[6].wakeup_ports[2].bits.uop.fp_typ
connect slots_6.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[6].wakeup_ports[2].bits.uop.fp_rm
connect slots_6.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[6].wakeup_ports[2].bits.uop.fp_val
connect slots_6.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[6].wakeup_ports[2].bits.uop.fcn_op
connect slots_6.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[6].wakeup_ports[2].bits.uop.fcn_dw
connect slots_6.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[6].wakeup_ports[2].bits.uop.frs3_en
connect slots_6.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[6].wakeup_ports[2].bits.uop.lrs2_rtype
connect slots_6.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[6].wakeup_ports[2].bits.uop.lrs1_rtype
connect slots_6.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[6].wakeup_ports[2].bits.uop.dst_rtype
connect slots_6.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[6].wakeup_ports[2].bits.uop.lrs3
connect slots_6.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[6].wakeup_ports[2].bits.uop.lrs2
connect slots_6.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[6].wakeup_ports[2].bits.uop.lrs1
connect slots_6.io.wakeup_ports[2].bits.uop.ldst, issue_slots[6].wakeup_ports[2].bits.uop.ldst
connect slots_6.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[6].wakeup_ports[2].bits.uop.ldst_is_rs1
connect slots_6.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[6].wakeup_ports[2].bits.uop.csr_cmd
connect slots_6.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[6].wakeup_ports[2].bits.uop.flush_on_commit
connect slots_6.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[6].wakeup_ports[2].bits.uop.is_unique
connect slots_6.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[6].wakeup_ports[2].bits.uop.uses_stq
connect slots_6.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[6].wakeup_ports[2].bits.uop.uses_ldq
connect slots_6.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[6].wakeup_ports[2].bits.uop.mem_signed
connect slots_6.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[6].wakeup_ports[2].bits.uop.mem_size
connect slots_6.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[6].wakeup_ports[2].bits.uop.mem_cmd
connect slots_6.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[6].wakeup_ports[2].bits.uop.exc_cause
connect slots_6.io.wakeup_ports[2].bits.uop.exception, issue_slots[6].wakeup_ports[2].bits.uop.exception
connect slots_6.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[6].wakeup_ports[2].bits.uop.stale_pdst
connect slots_6.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[6].wakeup_ports[2].bits.uop.ppred_busy
connect slots_6.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[6].wakeup_ports[2].bits.uop.prs3_busy
connect slots_6.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[6].wakeup_ports[2].bits.uop.prs2_busy
connect slots_6.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[6].wakeup_ports[2].bits.uop.prs1_busy
connect slots_6.io.wakeup_ports[2].bits.uop.ppred, issue_slots[6].wakeup_ports[2].bits.uop.ppred
connect slots_6.io.wakeup_ports[2].bits.uop.prs3, issue_slots[6].wakeup_ports[2].bits.uop.prs3
connect slots_6.io.wakeup_ports[2].bits.uop.prs2, issue_slots[6].wakeup_ports[2].bits.uop.prs2
connect slots_6.io.wakeup_ports[2].bits.uop.prs1, issue_slots[6].wakeup_ports[2].bits.uop.prs1
connect slots_6.io.wakeup_ports[2].bits.uop.pdst, issue_slots[6].wakeup_ports[2].bits.uop.pdst
connect slots_6.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[6].wakeup_ports[2].bits.uop.rxq_idx
connect slots_6.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[6].wakeup_ports[2].bits.uop.stq_idx
connect slots_6.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[6].wakeup_ports[2].bits.uop.ldq_idx
connect slots_6.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[6].wakeup_ports[2].bits.uop.rob_idx
connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.vec
connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.wflags
connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.sqrt
connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.div
connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.fma
connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe
connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.toint
connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.fromint
connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut
connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn
connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.swap23
connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.swap12
connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.ren3
connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.ren2
connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.ren1
connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.wen
connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.ldst
connect slots_6.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[6].wakeup_ports[2].bits.uop.op2_sel
connect slots_6.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[6].wakeup_ports[2].bits.uop.op1_sel
connect slots_6.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[6].wakeup_ports[2].bits.uop.imm_packed
connect slots_6.io.wakeup_ports[2].bits.uop.pimm, issue_slots[6].wakeup_ports[2].bits.uop.pimm
connect slots_6.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[6].wakeup_ports[2].bits.uop.imm_sel
connect slots_6.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[6].wakeup_ports[2].bits.uop.imm_rename
connect slots_6.io.wakeup_ports[2].bits.uop.taken, issue_slots[6].wakeup_ports[2].bits.uop.taken
connect slots_6.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[6].wakeup_ports[2].bits.uop.pc_lob
connect slots_6.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[6].wakeup_ports[2].bits.uop.edge_inst
connect slots_6.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[6].wakeup_ports[2].bits.uop.ftq_idx
connect slots_6.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[6].wakeup_ports[2].bits.uop.is_mov
connect slots_6.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[6].wakeup_ports[2].bits.uop.is_rocc
connect slots_6.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[6].wakeup_ports[2].bits.uop.is_sys_pc2epc
connect slots_6.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[6].wakeup_ports[2].bits.uop.is_eret
connect slots_6.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[6].wakeup_ports[2].bits.uop.is_amo
connect slots_6.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[6].wakeup_ports[2].bits.uop.is_sfence
connect slots_6.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[6].wakeup_ports[2].bits.uop.is_fencei
connect slots_6.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[6].wakeup_ports[2].bits.uop.is_fence
connect slots_6.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[6].wakeup_ports[2].bits.uop.is_sfb
connect slots_6.io.wakeup_ports[2].bits.uop.br_type, issue_slots[6].wakeup_ports[2].bits.uop.br_type
connect slots_6.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[6].wakeup_ports[2].bits.uop.br_tag
connect slots_6.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[6].wakeup_ports[2].bits.uop.br_mask
connect slots_6.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[6].wakeup_ports[2].bits.uop.dis_col_sel
connect slots_6.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[6].wakeup_ports[2].bits.uop.iw_p3_bypass_hint
connect slots_6.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[6].wakeup_ports[2].bits.uop.iw_p2_bypass_hint
connect slots_6.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[6].wakeup_ports[2].bits.uop.iw_p1_bypass_hint
connect slots_6.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[6].wakeup_ports[2].bits.uop.iw_p2_speculative_child
connect slots_6.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[6].wakeup_ports[2].bits.uop.iw_p1_speculative_child
connect slots_6.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[6].wakeup_ports[2].bits.uop.iw_issued_partial_dgen
connect slots_6.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[6].wakeup_ports[2].bits.uop.iw_issued_partial_agen
connect slots_6.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[6].wakeup_ports[2].bits.uop.iw_issued
connect slots_6.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[6].wakeup_ports[2].bits.uop.fu_code[0]
connect slots_6.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[6].wakeup_ports[2].bits.uop.fu_code[1]
connect slots_6.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[6].wakeup_ports[2].bits.uop.fu_code[2]
connect slots_6.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[6].wakeup_ports[2].bits.uop.fu_code[3]
connect slots_6.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[6].wakeup_ports[2].bits.uop.fu_code[4]
connect slots_6.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[6].wakeup_ports[2].bits.uop.fu_code[5]
connect slots_6.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[6].wakeup_ports[2].bits.uop.fu_code[6]
connect slots_6.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[6].wakeup_ports[2].bits.uop.fu_code[7]
connect slots_6.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[6].wakeup_ports[2].bits.uop.fu_code[8]
connect slots_6.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[6].wakeup_ports[2].bits.uop.fu_code[9]
connect slots_6.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[6].wakeup_ports[2].bits.uop.iq_type[0]
connect slots_6.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[6].wakeup_ports[2].bits.uop.iq_type[1]
connect slots_6.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[6].wakeup_ports[2].bits.uop.iq_type[2]
connect slots_6.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[6].wakeup_ports[2].bits.uop.iq_type[3]
connect slots_6.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[6].wakeup_ports[2].bits.uop.debug_pc
connect slots_6.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[6].wakeup_ports[2].bits.uop.is_rvc
connect slots_6.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[6].wakeup_ports[2].bits.uop.debug_inst
connect slots_6.io.wakeup_ports[2].bits.uop.inst, issue_slots[6].wakeup_ports[2].bits.uop.inst
connect slots_6.io.wakeup_ports[2].valid, issue_slots[6].wakeup_ports[2].valid
connect slots_6.io.wakeup_ports[3].bits.rebusy, issue_slots[6].wakeup_ports[3].bits.rebusy
connect slots_6.io.wakeup_ports[3].bits.speculative_mask, issue_slots[6].wakeup_ports[3].bits.speculative_mask
connect slots_6.io.wakeup_ports[3].bits.bypassable, issue_slots[6].wakeup_ports[3].bits.bypassable
connect slots_6.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[6].wakeup_ports[3].bits.uop.debug_tsrc
connect slots_6.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[6].wakeup_ports[3].bits.uop.debug_fsrc
connect slots_6.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[6].wakeup_ports[3].bits.uop.bp_xcpt_if
connect slots_6.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[6].wakeup_ports[3].bits.uop.bp_debug_if
connect slots_6.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[6].wakeup_ports[3].bits.uop.xcpt_ma_if
connect slots_6.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[6].wakeup_ports[3].bits.uop.xcpt_ae_if
connect slots_6.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[6].wakeup_ports[3].bits.uop.xcpt_pf_if
connect slots_6.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[6].wakeup_ports[3].bits.uop.fp_typ
connect slots_6.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[6].wakeup_ports[3].bits.uop.fp_rm
connect slots_6.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[6].wakeup_ports[3].bits.uop.fp_val
connect slots_6.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[6].wakeup_ports[3].bits.uop.fcn_op
connect slots_6.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[6].wakeup_ports[3].bits.uop.fcn_dw
connect slots_6.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[6].wakeup_ports[3].bits.uop.frs3_en
connect slots_6.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[6].wakeup_ports[3].bits.uop.lrs2_rtype
connect slots_6.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[6].wakeup_ports[3].bits.uop.lrs1_rtype
connect slots_6.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[6].wakeup_ports[3].bits.uop.dst_rtype
connect slots_6.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[6].wakeup_ports[3].bits.uop.lrs3
connect slots_6.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[6].wakeup_ports[3].bits.uop.lrs2
connect slots_6.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[6].wakeup_ports[3].bits.uop.lrs1
connect slots_6.io.wakeup_ports[3].bits.uop.ldst, issue_slots[6].wakeup_ports[3].bits.uop.ldst
connect slots_6.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[6].wakeup_ports[3].bits.uop.ldst_is_rs1
connect slots_6.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[6].wakeup_ports[3].bits.uop.csr_cmd
connect slots_6.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[6].wakeup_ports[3].bits.uop.flush_on_commit
connect slots_6.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[6].wakeup_ports[3].bits.uop.is_unique
connect slots_6.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[6].wakeup_ports[3].bits.uop.uses_stq
connect slots_6.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[6].wakeup_ports[3].bits.uop.uses_ldq
connect slots_6.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[6].wakeup_ports[3].bits.uop.mem_signed
connect slots_6.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[6].wakeup_ports[3].bits.uop.mem_size
connect slots_6.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[6].wakeup_ports[3].bits.uop.mem_cmd
connect slots_6.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[6].wakeup_ports[3].bits.uop.exc_cause
connect slots_6.io.wakeup_ports[3].bits.uop.exception, issue_slots[6].wakeup_ports[3].bits.uop.exception
connect slots_6.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[6].wakeup_ports[3].bits.uop.stale_pdst
connect slots_6.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[6].wakeup_ports[3].bits.uop.ppred_busy
connect slots_6.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[6].wakeup_ports[3].bits.uop.prs3_busy
connect slots_6.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[6].wakeup_ports[3].bits.uop.prs2_busy
connect slots_6.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[6].wakeup_ports[3].bits.uop.prs1_busy
connect slots_6.io.wakeup_ports[3].bits.uop.ppred, issue_slots[6].wakeup_ports[3].bits.uop.ppred
connect slots_6.io.wakeup_ports[3].bits.uop.prs3, issue_slots[6].wakeup_ports[3].bits.uop.prs3
connect slots_6.io.wakeup_ports[3].bits.uop.prs2, issue_slots[6].wakeup_ports[3].bits.uop.prs2
connect slots_6.io.wakeup_ports[3].bits.uop.prs1, issue_slots[6].wakeup_ports[3].bits.uop.prs1
connect slots_6.io.wakeup_ports[3].bits.uop.pdst, issue_slots[6].wakeup_ports[3].bits.uop.pdst
connect slots_6.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[6].wakeup_ports[3].bits.uop.rxq_idx
connect slots_6.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[6].wakeup_ports[3].bits.uop.stq_idx
connect slots_6.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[6].wakeup_ports[3].bits.uop.ldq_idx
connect slots_6.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[6].wakeup_ports[3].bits.uop.rob_idx
connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.vec
connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.wflags
connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.sqrt
connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.div
connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.fma
connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe
connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.toint
connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.fromint
connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut
connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn
connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.swap23
connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.swap12
connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.ren3
connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.ren2
connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.ren1
connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.wen
connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.ldst
connect slots_6.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[6].wakeup_ports[3].bits.uop.op2_sel
connect slots_6.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[6].wakeup_ports[3].bits.uop.op1_sel
connect slots_6.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[6].wakeup_ports[3].bits.uop.imm_packed
connect slots_6.io.wakeup_ports[3].bits.uop.pimm, issue_slots[6].wakeup_ports[3].bits.uop.pimm
connect slots_6.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[6].wakeup_ports[3].bits.uop.imm_sel
connect slots_6.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[6].wakeup_ports[3].bits.uop.imm_rename
connect slots_6.io.wakeup_ports[3].bits.uop.taken, issue_slots[6].wakeup_ports[3].bits.uop.taken
connect slots_6.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[6].wakeup_ports[3].bits.uop.pc_lob
connect slots_6.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[6].wakeup_ports[3].bits.uop.edge_inst
connect slots_6.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[6].wakeup_ports[3].bits.uop.ftq_idx
connect slots_6.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[6].wakeup_ports[3].bits.uop.is_mov
connect slots_6.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[6].wakeup_ports[3].bits.uop.is_rocc
connect slots_6.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[6].wakeup_ports[3].bits.uop.is_sys_pc2epc
connect slots_6.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[6].wakeup_ports[3].bits.uop.is_eret
connect slots_6.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[6].wakeup_ports[3].bits.uop.is_amo
connect slots_6.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[6].wakeup_ports[3].bits.uop.is_sfence
connect slots_6.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[6].wakeup_ports[3].bits.uop.is_fencei
connect slots_6.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[6].wakeup_ports[3].bits.uop.is_fence
connect slots_6.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[6].wakeup_ports[3].bits.uop.is_sfb
connect slots_6.io.wakeup_ports[3].bits.uop.br_type, issue_slots[6].wakeup_ports[3].bits.uop.br_type
connect slots_6.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[6].wakeup_ports[3].bits.uop.br_tag
connect slots_6.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[6].wakeup_ports[3].bits.uop.br_mask
connect slots_6.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[6].wakeup_ports[3].bits.uop.dis_col_sel
connect slots_6.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[6].wakeup_ports[3].bits.uop.iw_p3_bypass_hint
connect slots_6.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[6].wakeup_ports[3].bits.uop.iw_p2_bypass_hint
connect slots_6.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[6].wakeup_ports[3].bits.uop.iw_p1_bypass_hint
connect slots_6.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[6].wakeup_ports[3].bits.uop.iw_p2_speculative_child
connect slots_6.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[6].wakeup_ports[3].bits.uop.iw_p1_speculative_child
connect slots_6.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[6].wakeup_ports[3].bits.uop.iw_issued_partial_dgen
connect slots_6.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[6].wakeup_ports[3].bits.uop.iw_issued_partial_agen
connect slots_6.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[6].wakeup_ports[3].bits.uop.iw_issued
connect slots_6.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[6].wakeup_ports[3].bits.uop.fu_code[0]
connect slots_6.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[6].wakeup_ports[3].bits.uop.fu_code[1]
connect slots_6.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[6].wakeup_ports[3].bits.uop.fu_code[2]
connect slots_6.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[6].wakeup_ports[3].bits.uop.fu_code[3]
connect slots_6.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[6].wakeup_ports[3].bits.uop.fu_code[4]
connect slots_6.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[6].wakeup_ports[3].bits.uop.fu_code[5]
connect slots_6.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[6].wakeup_ports[3].bits.uop.fu_code[6]
connect slots_6.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[6].wakeup_ports[3].bits.uop.fu_code[7]
connect slots_6.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[6].wakeup_ports[3].bits.uop.fu_code[8]
connect slots_6.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[6].wakeup_ports[3].bits.uop.fu_code[9]
connect slots_6.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[6].wakeup_ports[3].bits.uop.iq_type[0]
connect slots_6.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[6].wakeup_ports[3].bits.uop.iq_type[1]
connect slots_6.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[6].wakeup_ports[3].bits.uop.iq_type[2]
connect slots_6.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[6].wakeup_ports[3].bits.uop.iq_type[3]
connect slots_6.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[6].wakeup_ports[3].bits.uop.debug_pc
connect slots_6.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[6].wakeup_ports[3].bits.uop.is_rvc
connect slots_6.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[6].wakeup_ports[3].bits.uop.debug_inst
connect slots_6.io.wakeup_ports[3].bits.uop.inst, issue_slots[6].wakeup_ports[3].bits.uop.inst
connect slots_6.io.wakeup_ports[3].valid, issue_slots[6].wakeup_ports[3].valid
connect slots_6.io.squash_grant, issue_slots[6].squash_grant
connect slots_6.io.clear, issue_slots[6].clear
connect slots_6.io.kill, issue_slots[6].kill
connect slots_6.io.brupdate.b2.target_offset, issue_slots[6].brupdate.b2.target_offset
connect slots_6.io.brupdate.b2.jalr_target, issue_slots[6].brupdate.b2.jalr_target
connect slots_6.io.brupdate.b2.pc_sel, issue_slots[6].brupdate.b2.pc_sel
connect slots_6.io.brupdate.b2.cfi_type, issue_slots[6].brupdate.b2.cfi_type
connect slots_6.io.brupdate.b2.taken, issue_slots[6].brupdate.b2.taken
connect slots_6.io.brupdate.b2.mispredict, issue_slots[6].brupdate.b2.mispredict
connect slots_6.io.brupdate.b2.uop.debug_tsrc, issue_slots[6].brupdate.b2.uop.debug_tsrc
connect slots_6.io.brupdate.b2.uop.debug_fsrc, issue_slots[6].brupdate.b2.uop.debug_fsrc
connect slots_6.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[6].brupdate.b2.uop.bp_xcpt_if
connect slots_6.io.brupdate.b2.uop.bp_debug_if, issue_slots[6].brupdate.b2.uop.bp_debug_if
connect slots_6.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[6].brupdate.b2.uop.xcpt_ma_if
connect slots_6.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[6].brupdate.b2.uop.xcpt_ae_if
connect slots_6.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[6].brupdate.b2.uop.xcpt_pf_if
connect slots_6.io.brupdate.b2.uop.fp_typ, issue_slots[6].brupdate.b2.uop.fp_typ
connect slots_6.io.brupdate.b2.uop.fp_rm, issue_slots[6].brupdate.b2.uop.fp_rm
connect slots_6.io.brupdate.b2.uop.fp_val, issue_slots[6].brupdate.b2.uop.fp_val
connect slots_6.io.brupdate.b2.uop.fcn_op, issue_slots[6].brupdate.b2.uop.fcn_op
connect slots_6.io.brupdate.b2.uop.fcn_dw, issue_slots[6].brupdate.b2.uop.fcn_dw
connect slots_6.io.brupdate.b2.uop.frs3_en, issue_slots[6].brupdate.b2.uop.frs3_en
connect slots_6.io.brupdate.b2.uop.lrs2_rtype, issue_slots[6].brupdate.b2.uop.lrs2_rtype
connect slots_6.io.brupdate.b2.uop.lrs1_rtype, issue_slots[6].brupdate.b2.uop.lrs1_rtype
connect slots_6.io.brupdate.b2.uop.dst_rtype, issue_slots[6].brupdate.b2.uop.dst_rtype
connect slots_6.io.brupdate.b2.uop.lrs3, issue_slots[6].brupdate.b2.uop.lrs3
connect slots_6.io.brupdate.b2.uop.lrs2, issue_slots[6].brupdate.b2.uop.lrs2
connect slots_6.io.brupdate.b2.uop.lrs1, issue_slots[6].brupdate.b2.uop.lrs1
connect slots_6.io.brupdate.b2.uop.ldst, issue_slots[6].brupdate.b2.uop.ldst
connect slots_6.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[6].brupdate.b2.uop.ldst_is_rs1
connect slots_6.io.brupdate.b2.uop.csr_cmd, issue_slots[6].brupdate.b2.uop.csr_cmd
connect slots_6.io.brupdate.b2.uop.flush_on_commit, issue_slots[6].brupdate.b2.uop.flush_on_commit
connect slots_6.io.brupdate.b2.uop.is_unique, issue_slots[6].brupdate.b2.uop.is_unique
connect slots_6.io.brupdate.b2.uop.uses_stq, issue_slots[6].brupdate.b2.uop.uses_stq
connect slots_6.io.brupdate.b2.uop.uses_ldq, issue_slots[6].brupdate.b2.uop.uses_ldq
connect slots_6.io.brupdate.b2.uop.mem_signed, issue_slots[6].brupdate.b2.uop.mem_signed
connect slots_6.io.brupdate.b2.uop.mem_size, issue_slots[6].brupdate.b2.uop.mem_size
connect slots_6.io.brupdate.b2.uop.mem_cmd, issue_slots[6].brupdate.b2.uop.mem_cmd
connect slots_6.io.brupdate.b2.uop.exc_cause, issue_slots[6].brupdate.b2.uop.exc_cause
connect slots_6.io.brupdate.b2.uop.exception, issue_slots[6].brupdate.b2.uop.exception
connect slots_6.io.brupdate.b2.uop.stale_pdst, issue_slots[6].brupdate.b2.uop.stale_pdst
connect slots_6.io.brupdate.b2.uop.ppred_busy, issue_slots[6].brupdate.b2.uop.ppred_busy
connect slots_6.io.brupdate.b2.uop.prs3_busy, issue_slots[6].brupdate.b2.uop.prs3_busy
connect slots_6.io.brupdate.b2.uop.prs2_busy, issue_slots[6].brupdate.b2.uop.prs2_busy
connect slots_6.io.brupdate.b2.uop.prs1_busy, issue_slots[6].brupdate.b2.uop.prs1_busy
connect slots_6.io.brupdate.b2.uop.ppred, issue_slots[6].brupdate.b2.uop.ppred
connect slots_6.io.brupdate.b2.uop.prs3, issue_slots[6].brupdate.b2.uop.prs3
connect slots_6.io.brupdate.b2.uop.prs2, issue_slots[6].brupdate.b2.uop.prs2
connect slots_6.io.brupdate.b2.uop.prs1, issue_slots[6].brupdate.b2.uop.prs1
connect slots_6.io.brupdate.b2.uop.pdst, issue_slots[6].brupdate.b2.uop.pdst
connect slots_6.io.brupdate.b2.uop.rxq_idx, issue_slots[6].brupdate.b2.uop.rxq_idx
connect slots_6.io.brupdate.b2.uop.stq_idx, issue_slots[6].brupdate.b2.uop.stq_idx
connect slots_6.io.brupdate.b2.uop.ldq_idx, issue_slots[6].brupdate.b2.uop.ldq_idx
connect slots_6.io.brupdate.b2.uop.rob_idx, issue_slots[6].brupdate.b2.uop.rob_idx
connect slots_6.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[6].brupdate.b2.uop.fp_ctrl.vec
connect slots_6.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[6].brupdate.b2.uop.fp_ctrl.wflags
connect slots_6.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[6].brupdate.b2.uop.fp_ctrl.sqrt
connect slots_6.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[6].brupdate.b2.uop.fp_ctrl.div
connect slots_6.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[6].brupdate.b2.uop.fp_ctrl.fma
connect slots_6.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[6].brupdate.b2.uop.fp_ctrl.fastpipe
connect slots_6.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[6].brupdate.b2.uop.fp_ctrl.toint
connect slots_6.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[6].brupdate.b2.uop.fp_ctrl.fromint
connect slots_6.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[6].brupdate.b2.uop.fp_ctrl.typeTagOut
connect slots_6.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[6].brupdate.b2.uop.fp_ctrl.typeTagIn
connect slots_6.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[6].brupdate.b2.uop.fp_ctrl.swap23
connect slots_6.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[6].brupdate.b2.uop.fp_ctrl.swap12
connect slots_6.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[6].brupdate.b2.uop.fp_ctrl.ren3
connect slots_6.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[6].brupdate.b2.uop.fp_ctrl.ren2
connect slots_6.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[6].brupdate.b2.uop.fp_ctrl.ren1
connect slots_6.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[6].brupdate.b2.uop.fp_ctrl.wen
connect slots_6.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[6].brupdate.b2.uop.fp_ctrl.ldst
connect slots_6.io.brupdate.b2.uop.op2_sel, issue_slots[6].brupdate.b2.uop.op2_sel
connect slots_6.io.brupdate.b2.uop.op1_sel, issue_slots[6].brupdate.b2.uop.op1_sel
connect slots_6.io.brupdate.b2.uop.imm_packed, issue_slots[6].brupdate.b2.uop.imm_packed
connect slots_6.io.brupdate.b2.uop.pimm, issue_slots[6].brupdate.b2.uop.pimm
connect slots_6.io.brupdate.b2.uop.imm_sel, issue_slots[6].brupdate.b2.uop.imm_sel
connect slots_6.io.brupdate.b2.uop.imm_rename, issue_slots[6].brupdate.b2.uop.imm_rename
connect slots_6.io.brupdate.b2.uop.taken, issue_slots[6].brupdate.b2.uop.taken
connect slots_6.io.brupdate.b2.uop.pc_lob, issue_slots[6].brupdate.b2.uop.pc_lob
connect slots_6.io.brupdate.b2.uop.edge_inst, issue_slots[6].brupdate.b2.uop.edge_inst
connect slots_6.io.brupdate.b2.uop.ftq_idx, issue_slots[6].brupdate.b2.uop.ftq_idx
connect slots_6.io.brupdate.b2.uop.is_mov, issue_slots[6].brupdate.b2.uop.is_mov
connect slots_6.io.brupdate.b2.uop.is_rocc, issue_slots[6].brupdate.b2.uop.is_rocc
connect slots_6.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[6].brupdate.b2.uop.is_sys_pc2epc
connect slots_6.io.brupdate.b2.uop.is_eret, issue_slots[6].brupdate.b2.uop.is_eret
connect slots_6.io.brupdate.b2.uop.is_amo, issue_slots[6].brupdate.b2.uop.is_amo
connect slots_6.io.brupdate.b2.uop.is_sfence, issue_slots[6].brupdate.b2.uop.is_sfence
connect slots_6.io.brupdate.b2.uop.is_fencei, issue_slots[6].brupdate.b2.uop.is_fencei
connect slots_6.io.brupdate.b2.uop.is_fence, issue_slots[6].brupdate.b2.uop.is_fence
connect slots_6.io.brupdate.b2.uop.is_sfb, issue_slots[6].brupdate.b2.uop.is_sfb
connect slots_6.io.brupdate.b2.uop.br_type, issue_slots[6].brupdate.b2.uop.br_type
connect slots_6.io.brupdate.b2.uop.br_tag, issue_slots[6].brupdate.b2.uop.br_tag
connect slots_6.io.brupdate.b2.uop.br_mask, issue_slots[6].brupdate.b2.uop.br_mask
connect slots_6.io.brupdate.b2.uop.dis_col_sel, issue_slots[6].brupdate.b2.uop.dis_col_sel
connect slots_6.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[6].brupdate.b2.uop.iw_p3_bypass_hint
connect slots_6.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[6].brupdate.b2.uop.iw_p2_bypass_hint
connect slots_6.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[6].brupdate.b2.uop.iw_p1_bypass_hint
connect slots_6.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[6].brupdate.b2.uop.iw_p2_speculative_child
connect slots_6.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[6].brupdate.b2.uop.iw_p1_speculative_child
connect slots_6.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[6].brupdate.b2.uop.iw_issued_partial_dgen
connect slots_6.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[6].brupdate.b2.uop.iw_issued_partial_agen
connect slots_6.io.brupdate.b2.uop.iw_issued, issue_slots[6].brupdate.b2.uop.iw_issued
connect slots_6.io.brupdate.b2.uop.fu_code[0], issue_slots[6].brupdate.b2.uop.fu_code[0]
connect slots_6.io.brupdate.b2.uop.fu_code[1], issue_slots[6].brupdate.b2.uop.fu_code[1]
connect slots_6.io.brupdate.b2.uop.fu_code[2], issue_slots[6].brupdate.b2.uop.fu_code[2]
connect slots_6.io.brupdate.b2.uop.fu_code[3], issue_slots[6].brupdate.b2.uop.fu_code[3]
connect slots_6.io.brupdate.b2.uop.fu_code[4], issue_slots[6].brupdate.b2.uop.fu_code[4]
connect slots_6.io.brupdate.b2.uop.fu_code[5], issue_slots[6].brupdate.b2.uop.fu_code[5]
connect slots_6.io.brupdate.b2.uop.fu_code[6], issue_slots[6].brupdate.b2.uop.fu_code[6]
connect slots_6.io.brupdate.b2.uop.fu_code[7], issue_slots[6].brupdate.b2.uop.fu_code[7]
connect slots_6.io.brupdate.b2.uop.fu_code[8], issue_slots[6].brupdate.b2.uop.fu_code[8]
connect slots_6.io.brupdate.b2.uop.fu_code[9], issue_slots[6].brupdate.b2.uop.fu_code[9]
connect slots_6.io.brupdate.b2.uop.iq_type[0], issue_slots[6].brupdate.b2.uop.iq_type[0]
connect slots_6.io.brupdate.b2.uop.iq_type[1], issue_slots[6].brupdate.b2.uop.iq_type[1]
connect slots_6.io.brupdate.b2.uop.iq_type[2], issue_slots[6].brupdate.b2.uop.iq_type[2]
connect slots_6.io.brupdate.b2.uop.iq_type[3], issue_slots[6].brupdate.b2.uop.iq_type[3]
connect slots_6.io.brupdate.b2.uop.debug_pc, issue_slots[6].brupdate.b2.uop.debug_pc
connect slots_6.io.brupdate.b2.uop.is_rvc, issue_slots[6].brupdate.b2.uop.is_rvc
connect slots_6.io.brupdate.b2.uop.debug_inst, issue_slots[6].brupdate.b2.uop.debug_inst
connect slots_6.io.brupdate.b2.uop.inst, issue_slots[6].brupdate.b2.uop.inst
connect slots_6.io.brupdate.b1.mispredict_mask, issue_slots[6].brupdate.b1.mispredict_mask
connect slots_6.io.brupdate.b1.resolve_mask, issue_slots[6].brupdate.b1.resolve_mask
connect issue_slots[6].out_uop.debug_tsrc, slots_6.io.out_uop.debug_tsrc
connect issue_slots[6].out_uop.debug_fsrc, slots_6.io.out_uop.debug_fsrc
connect issue_slots[6].out_uop.bp_xcpt_if, slots_6.io.out_uop.bp_xcpt_if
connect issue_slots[6].out_uop.bp_debug_if, slots_6.io.out_uop.bp_debug_if
connect issue_slots[6].out_uop.xcpt_ma_if, slots_6.io.out_uop.xcpt_ma_if
connect issue_slots[6].out_uop.xcpt_ae_if, slots_6.io.out_uop.xcpt_ae_if
connect issue_slots[6].out_uop.xcpt_pf_if, slots_6.io.out_uop.xcpt_pf_if
connect issue_slots[6].out_uop.fp_typ, slots_6.io.out_uop.fp_typ
connect issue_slots[6].out_uop.fp_rm, slots_6.io.out_uop.fp_rm
connect issue_slots[6].out_uop.fp_val, slots_6.io.out_uop.fp_val
connect issue_slots[6].out_uop.fcn_op, slots_6.io.out_uop.fcn_op
connect issue_slots[6].out_uop.fcn_dw, slots_6.io.out_uop.fcn_dw
connect issue_slots[6].out_uop.frs3_en, slots_6.io.out_uop.frs3_en
connect issue_slots[6].out_uop.lrs2_rtype, slots_6.io.out_uop.lrs2_rtype
connect issue_slots[6].out_uop.lrs1_rtype, slots_6.io.out_uop.lrs1_rtype
connect issue_slots[6].out_uop.dst_rtype, slots_6.io.out_uop.dst_rtype
connect issue_slots[6].out_uop.lrs3, slots_6.io.out_uop.lrs3
connect issue_slots[6].out_uop.lrs2, slots_6.io.out_uop.lrs2
connect issue_slots[6].out_uop.lrs1, slots_6.io.out_uop.lrs1
connect issue_slots[6].out_uop.ldst, slots_6.io.out_uop.ldst
connect issue_slots[6].out_uop.ldst_is_rs1, slots_6.io.out_uop.ldst_is_rs1
connect issue_slots[6].out_uop.csr_cmd, slots_6.io.out_uop.csr_cmd
connect issue_slots[6].out_uop.flush_on_commit, slots_6.io.out_uop.flush_on_commit
connect issue_slots[6].out_uop.is_unique, slots_6.io.out_uop.is_unique
connect issue_slots[6].out_uop.uses_stq, slots_6.io.out_uop.uses_stq
connect issue_slots[6].out_uop.uses_ldq, slots_6.io.out_uop.uses_ldq
connect issue_slots[6].out_uop.mem_signed, slots_6.io.out_uop.mem_signed
connect issue_slots[6].out_uop.mem_size, slots_6.io.out_uop.mem_size
connect issue_slots[6].out_uop.mem_cmd, slots_6.io.out_uop.mem_cmd
connect issue_slots[6].out_uop.exc_cause, slots_6.io.out_uop.exc_cause
connect issue_slots[6].out_uop.exception, slots_6.io.out_uop.exception
connect issue_slots[6].out_uop.stale_pdst, slots_6.io.out_uop.stale_pdst
connect issue_slots[6].out_uop.ppred_busy, slots_6.io.out_uop.ppred_busy
connect issue_slots[6].out_uop.prs3_busy, slots_6.io.out_uop.prs3_busy
connect issue_slots[6].out_uop.prs2_busy, slots_6.io.out_uop.prs2_busy
connect issue_slots[6].out_uop.prs1_busy, slots_6.io.out_uop.prs1_busy
connect issue_slots[6].out_uop.ppred, slots_6.io.out_uop.ppred
connect issue_slots[6].out_uop.prs3, slots_6.io.out_uop.prs3
connect issue_slots[6].out_uop.prs2, slots_6.io.out_uop.prs2
connect issue_slots[6].out_uop.prs1, slots_6.io.out_uop.prs1
connect issue_slots[6].out_uop.pdst, slots_6.io.out_uop.pdst
connect issue_slots[6].out_uop.rxq_idx, slots_6.io.out_uop.rxq_idx
connect issue_slots[6].out_uop.stq_idx, slots_6.io.out_uop.stq_idx
connect issue_slots[6].out_uop.ldq_idx, slots_6.io.out_uop.ldq_idx
connect issue_slots[6].out_uop.rob_idx, slots_6.io.out_uop.rob_idx
connect issue_slots[6].out_uop.fp_ctrl.vec, slots_6.io.out_uop.fp_ctrl.vec
connect issue_slots[6].out_uop.fp_ctrl.wflags, slots_6.io.out_uop.fp_ctrl.wflags
connect issue_slots[6].out_uop.fp_ctrl.sqrt, slots_6.io.out_uop.fp_ctrl.sqrt
connect issue_slots[6].out_uop.fp_ctrl.div, slots_6.io.out_uop.fp_ctrl.div
connect issue_slots[6].out_uop.fp_ctrl.fma, slots_6.io.out_uop.fp_ctrl.fma
connect issue_slots[6].out_uop.fp_ctrl.fastpipe, slots_6.io.out_uop.fp_ctrl.fastpipe
connect issue_slots[6].out_uop.fp_ctrl.toint, slots_6.io.out_uop.fp_ctrl.toint
connect issue_slots[6].out_uop.fp_ctrl.fromint, slots_6.io.out_uop.fp_ctrl.fromint
connect issue_slots[6].out_uop.fp_ctrl.typeTagOut, slots_6.io.out_uop.fp_ctrl.typeTagOut
connect issue_slots[6].out_uop.fp_ctrl.typeTagIn, slots_6.io.out_uop.fp_ctrl.typeTagIn
connect issue_slots[6].out_uop.fp_ctrl.swap23, slots_6.io.out_uop.fp_ctrl.swap23
connect issue_slots[6].out_uop.fp_ctrl.swap12, slots_6.io.out_uop.fp_ctrl.swap12
connect issue_slots[6].out_uop.fp_ctrl.ren3, slots_6.io.out_uop.fp_ctrl.ren3
connect issue_slots[6].out_uop.fp_ctrl.ren2, slots_6.io.out_uop.fp_ctrl.ren2
connect issue_slots[6].out_uop.fp_ctrl.ren1, slots_6.io.out_uop.fp_ctrl.ren1
connect issue_slots[6].out_uop.fp_ctrl.wen, slots_6.io.out_uop.fp_ctrl.wen
connect issue_slots[6].out_uop.fp_ctrl.ldst, slots_6.io.out_uop.fp_ctrl.ldst
connect issue_slots[6].out_uop.op2_sel, slots_6.io.out_uop.op2_sel
connect issue_slots[6].out_uop.op1_sel, slots_6.io.out_uop.op1_sel
connect issue_slots[6].out_uop.imm_packed, slots_6.io.out_uop.imm_packed
connect issue_slots[6].out_uop.pimm, slots_6.io.out_uop.pimm
connect issue_slots[6].out_uop.imm_sel, slots_6.io.out_uop.imm_sel
connect issue_slots[6].out_uop.imm_rename, slots_6.io.out_uop.imm_rename
connect issue_slots[6].out_uop.taken, slots_6.io.out_uop.taken
connect issue_slots[6].out_uop.pc_lob, slots_6.io.out_uop.pc_lob
connect issue_slots[6].out_uop.edge_inst, slots_6.io.out_uop.edge_inst
connect issue_slots[6].out_uop.ftq_idx, slots_6.io.out_uop.ftq_idx
connect issue_slots[6].out_uop.is_mov, slots_6.io.out_uop.is_mov
connect issue_slots[6].out_uop.is_rocc, slots_6.io.out_uop.is_rocc
connect issue_slots[6].out_uop.is_sys_pc2epc, slots_6.io.out_uop.is_sys_pc2epc
connect issue_slots[6].out_uop.is_eret, slots_6.io.out_uop.is_eret
connect issue_slots[6].out_uop.is_amo, slots_6.io.out_uop.is_amo
connect issue_slots[6].out_uop.is_sfence, slots_6.io.out_uop.is_sfence
connect issue_slots[6].out_uop.is_fencei, slots_6.io.out_uop.is_fencei
connect issue_slots[6].out_uop.is_fence, slots_6.io.out_uop.is_fence
connect issue_slots[6].out_uop.is_sfb, slots_6.io.out_uop.is_sfb
connect issue_slots[6].out_uop.br_type, slots_6.io.out_uop.br_type
connect issue_slots[6].out_uop.br_tag, slots_6.io.out_uop.br_tag
connect issue_slots[6].out_uop.br_mask, slots_6.io.out_uop.br_mask
connect issue_slots[6].out_uop.dis_col_sel, slots_6.io.out_uop.dis_col_sel
connect issue_slots[6].out_uop.iw_p3_bypass_hint, slots_6.io.out_uop.iw_p3_bypass_hint
connect issue_slots[6].out_uop.iw_p2_bypass_hint, slots_6.io.out_uop.iw_p2_bypass_hint
connect issue_slots[6].out_uop.iw_p1_bypass_hint, slots_6.io.out_uop.iw_p1_bypass_hint
connect issue_slots[6].out_uop.iw_p2_speculative_child, slots_6.io.out_uop.iw_p2_speculative_child
connect issue_slots[6].out_uop.iw_p1_speculative_child, slots_6.io.out_uop.iw_p1_speculative_child
connect issue_slots[6].out_uop.iw_issued_partial_dgen, slots_6.io.out_uop.iw_issued_partial_dgen
connect issue_slots[6].out_uop.iw_issued_partial_agen, slots_6.io.out_uop.iw_issued_partial_agen
connect issue_slots[6].out_uop.iw_issued, slots_6.io.out_uop.iw_issued
connect issue_slots[6].out_uop.fu_code[0], slots_6.io.out_uop.fu_code[0]
connect issue_slots[6].out_uop.fu_code[1], slots_6.io.out_uop.fu_code[1]
connect issue_slots[6].out_uop.fu_code[2], slots_6.io.out_uop.fu_code[2]
connect issue_slots[6].out_uop.fu_code[3], slots_6.io.out_uop.fu_code[3]
connect issue_slots[6].out_uop.fu_code[4], slots_6.io.out_uop.fu_code[4]
connect issue_slots[6].out_uop.fu_code[5], slots_6.io.out_uop.fu_code[5]
connect issue_slots[6].out_uop.fu_code[6], slots_6.io.out_uop.fu_code[6]
connect issue_slots[6].out_uop.fu_code[7], slots_6.io.out_uop.fu_code[7]
connect issue_slots[6].out_uop.fu_code[8], slots_6.io.out_uop.fu_code[8]
connect issue_slots[6].out_uop.fu_code[9], slots_6.io.out_uop.fu_code[9]
connect issue_slots[6].out_uop.iq_type[0], slots_6.io.out_uop.iq_type[0]
connect issue_slots[6].out_uop.iq_type[1], slots_6.io.out_uop.iq_type[1]
connect issue_slots[6].out_uop.iq_type[2], slots_6.io.out_uop.iq_type[2]
connect issue_slots[6].out_uop.iq_type[3], slots_6.io.out_uop.iq_type[3]
connect issue_slots[6].out_uop.debug_pc, slots_6.io.out_uop.debug_pc
connect issue_slots[6].out_uop.is_rvc, slots_6.io.out_uop.is_rvc
connect issue_slots[6].out_uop.debug_inst, slots_6.io.out_uop.debug_inst
connect issue_slots[6].out_uop.inst, slots_6.io.out_uop.inst
connect slots_6.io.in_uop.bits.debug_tsrc, issue_slots[6].in_uop.bits.debug_tsrc
connect slots_6.io.in_uop.bits.debug_fsrc, issue_slots[6].in_uop.bits.debug_fsrc
connect slots_6.io.in_uop.bits.bp_xcpt_if, issue_slots[6].in_uop.bits.bp_xcpt_if
connect slots_6.io.in_uop.bits.bp_debug_if, issue_slots[6].in_uop.bits.bp_debug_if
connect slots_6.io.in_uop.bits.xcpt_ma_if, issue_slots[6].in_uop.bits.xcpt_ma_if
connect slots_6.io.in_uop.bits.xcpt_ae_if, issue_slots[6].in_uop.bits.xcpt_ae_if
connect slots_6.io.in_uop.bits.xcpt_pf_if, issue_slots[6].in_uop.bits.xcpt_pf_if
connect slots_6.io.in_uop.bits.fp_typ, issue_slots[6].in_uop.bits.fp_typ
connect slots_6.io.in_uop.bits.fp_rm, issue_slots[6].in_uop.bits.fp_rm
connect slots_6.io.in_uop.bits.fp_val, issue_slots[6].in_uop.bits.fp_val
connect slots_6.io.in_uop.bits.fcn_op, issue_slots[6].in_uop.bits.fcn_op
connect slots_6.io.in_uop.bits.fcn_dw, issue_slots[6].in_uop.bits.fcn_dw
connect slots_6.io.in_uop.bits.frs3_en, issue_slots[6].in_uop.bits.frs3_en
connect slots_6.io.in_uop.bits.lrs2_rtype, issue_slots[6].in_uop.bits.lrs2_rtype
connect slots_6.io.in_uop.bits.lrs1_rtype, issue_slots[6].in_uop.bits.lrs1_rtype
connect slots_6.io.in_uop.bits.dst_rtype, issue_slots[6].in_uop.bits.dst_rtype
connect slots_6.io.in_uop.bits.lrs3, issue_slots[6].in_uop.bits.lrs3
connect slots_6.io.in_uop.bits.lrs2, issue_slots[6].in_uop.bits.lrs2
connect slots_6.io.in_uop.bits.lrs1, issue_slots[6].in_uop.bits.lrs1
connect slots_6.io.in_uop.bits.ldst, issue_slots[6].in_uop.bits.ldst
connect slots_6.io.in_uop.bits.ldst_is_rs1, issue_slots[6].in_uop.bits.ldst_is_rs1
connect slots_6.io.in_uop.bits.csr_cmd, issue_slots[6].in_uop.bits.csr_cmd
connect slots_6.io.in_uop.bits.flush_on_commit, issue_slots[6].in_uop.bits.flush_on_commit
connect slots_6.io.in_uop.bits.is_unique, issue_slots[6].in_uop.bits.is_unique
connect slots_6.io.in_uop.bits.uses_stq, issue_slots[6].in_uop.bits.uses_stq
connect slots_6.io.in_uop.bits.uses_ldq, issue_slots[6].in_uop.bits.uses_ldq
connect slots_6.io.in_uop.bits.mem_signed, issue_slots[6].in_uop.bits.mem_signed
connect slots_6.io.in_uop.bits.mem_size, issue_slots[6].in_uop.bits.mem_size
connect slots_6.io.in_uop.bits.mem_cmd, issue_slots[6].in_uop.bits.mem_cmd
connect slots_6.io.in_uop.bits.exc_cause, issue_slots[6].in_uop.bits.exc_cause
connect slots_6.io.in_uop.bits.exception, issue_slots[6].in_uop.bits.exception
connect slots_6.io.in_uop.bits.stale_pdst, issue_slots[6].in_uop.bits.stale_pdst
connect slots_6.io.in_uop.bits.ppred_busy, issue_slots[6].in_uop.bits.ppred_busy
connect slots_6.io.in_uop.bits.prs3_busy, issue_slots[6].in_uop.bits.prs3_busy
connect slots_6.io.in_uop.bits.prs2_busy, issue_slots[6].in_uop.bits.prs2_busy
connect slots_6.io.in_uop.bits.prs1_busy, issue_slots[6].in_uop.bits.prs1_busy
connect slots_6.io.in_uop.bits.ppred, issue_slots[6].in_uop.bits.ppred
connect slots_6.io.in_uop.bits.prs3, issue_slots[6].in_uop.bits.prs3
connect slots_6.io.in_uop.bits.prs2, issue_slots[6].in_uop.bits.prs2
connect slots_6.io.in_uop.bits.prs1, issue_slots[6].in_uop.bits.prs1
connect slots_6.io.in_uop.bits.pdst, issue_slots[6].in_uop.bits.pdst
connect slots_6.io.in_uop.bits.rxq_idx, issue_slots[6].in_uop.bits.rxq_idx
connect slots_6.io.in_uop.bits.stq_idx, issue_slots[6].in_uop.bits.stq_idx
connect slots_6.io.in_uop.bits.ldq_idx, issue_slots[6].in_uop.bits.ldq_idx
connect slots_6.io.in_uop.bits.rob_idx, issue_slots[6].in_uop.bits.rob_idx
connect slots_6.io.in_uop.bits.fp_ctrl.vec, issue_slots[6].in_uop.bits.fp_ctrl.vec
connect slots_6.io.in_uop.bits.fp_ctrl.wflags, issue_slots[6].in_uop.bits.fp_ctrl.wflags
connect slots_6.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[6].in_uop.bits.fp_ctrl.sqrt
connect slots_6.io.in_uop.bits.fp_ctrl.div, issue_slots[6].in_uop.bits.fp_ctrl.div
connect slots_6.io.in_uop.bits.fp_ctrl.fma, issue_slots[6].in_uop.bits.fp_ctrl.fma
connect slots_6.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[6].in_uop.bits.fp_ctrl.fastpipe
connect slots_6.io.in_uop.bits.fp_ctrl.toint, issue_slots[6].in_uop.bits.fp_ctrl.toint
connect slots_6.io.in_uop.bits.fp_ctrl.fromint, issue_slots[6].in_uop.bits.fp_ctrl.fromint
connect slots_6.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[6].in_uop.bits.fp_ctrl.typeTagOut
connect slots_6.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[6].in_uop.bits.fp_ctrl.typeTagIn
connect slots_6.io.in_uop.bits.fp_ctrl.swap23, issue_slots[6].in_uop.bits.fp_ctrl.swap23
connect slots_6.io.in_uop.bits.fp_ctrl.swap12, issue_slots[6].in_uop.bits.fp_ctrl.swap12
connect slots_6.io.in_uop.bits.fp_ctrl.ren3, issue_slots[6].in_uop.bits.fp_ctrl.ren3
connect slots_6.io.in_uop.bits.fp_ctrl.ren2, issue_slots[6].in_uop.bits.fp_ctrl.ren2
connect slots_6.io.in_uop.bits.fp_ctrl.ren1, issue_slots[6].in_uop.bits.fp_ctrl.ren1
connect slots_6.io.in_uop.bits.fp_ctrl.wen, issue_slots[6].in_uop.bits.fp_ctrl.wen
connect slots_6.io.in_uop.bits.fp_ctrl.ldst, issue_slots[6].in_uop.bits.fp_ctrl.ldst
connect slots_6.io.in_uop.bits.op2_sel, issue_slots[6].in_uop.bits.op2_sel
connect slots_6.io.in_uop.bits.op1_sel, issue_slots[6].in_uop.bits.op1_sel
connect slots_6.io.in_uop.bits.imm_packed, issue_slots[6].in_uop.bits.imm_packed
connect slots_6.io.in_uop.bits.pimm, issue_slots[6].in_uop.bits.pimm
connect slots_6.io.in_uop.bits.imm_sel, issue_slots[6].in_uop.bits.imm_sel
connect slots_6.io.in_uop.bits.imm_rename, issue_slots[6].in_uop.bits.imm_rename
connect slots_6.io.in_uop.bits.taken, issue_slots[6].in_uop.bits.taken
connect slots_6.io.in_uop.bits.pc_lob, issue_slots[6].in_uop.bits.pc_lob
connect slots_6.io.in_uop.bits.edge_inst, issue_slots[6].in_uop.bits.edge_inst
connect slots_6.io.in_uop.bits.ftq_idx, issue_slots[6].in_uop.bits.ftq_idx
connect slots_6.io.in_uop.bits.is_mov, issue_slots[6].in_uop.bits.is_mov
connect slots_6.io.in_uop.bits.is_rocc, issue_slots[6].in_uop.bits.is_rocc
connect slots_6.io.in_uop.bits.is_sys_pc2epc, issue_slots[6].in_uop.bits.is_sys_pc2epc
connect slots_6.io.in_uop.bits.is_eret, issue_slots[6].in_uop.bits.is_eret
connect slots_6.io.in_uop.bits.is_amo, issue_slots[6].in_uop.bits.is_amo
connect slots_6.io.in_uop.bits.is_sfence, issue_slots[6].in_uop.bits.is_sfence
connect slots_6.io.in_uop.bits.is_fencei, issue_slots[6].in_uop.bits.is_fencei
connect slots_6.io.in_uop.bits.is_fence, issue_slots[6].in_uop.bits.is_fence
connect slots_6.io.in_uop.bits.is_sfb, issue_slots[6].in_uop.bits.is_sfb
connect slots_6.io.in_uop.bits.br_type, issue_slots[6].in_uop.bits.br_type
connect slots_6.io.in_uop.bits.br_tag, issue_slots[6].in_uop.bits.br_tag
connect slots_6.io.in_uop.bits.br_mask, issue_slots[6].in_uop.bits.br_mask
connect slots_6.io.in_uop.bits.dis_col_sel, issue_slots[6].in_uop.bits.dis_col_sel
connect slots_6.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[6].in_uop.bits.iw_p3_bypass_hint
connect slots_6.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[6].in_uop.bits.iw_p2_bypass_hint
connect slots_6.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[6].in_uop.bits.iw_p1_bypass_hint
connect slots_6.io.in_uop.bits.iw_p2_speculative_child, issue_slots[6].in_uop.bits.iw_p2_speculative_child
connect slots_6.io.in_uop.bits.iw_p1_speculative_child, issue_slots[6].in_uop.bits.iw_p1_speculative_child
connect slots_6.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[6].in_uop.bits.iw_issued_partial_dgen
connect slots_6.io.in_uop.bits.iw_issued_partial_agen, issue_slots[6].in_uop.bits.iw_issued_partial_agen
connect slots_6.io.in_uop.bits.iw_issued, issue_slots[6].in_uop.bits.iw_issued
connect slots_6.io.in_uop.bits.fu_code[0], issue_slots[6].in_uop.bits.fu_code[0]
connect slots_6.io.in_uop.bits.fu_code[1], issue_slots[6].in_uop.bits.fu_code[1]
connect slots_6.io.in_uop.bits.fu_code[2], issue_slots[6].in_uop.bits.fu_code[2]
connect slots_6.io.in_uop.bits.fu_code[3], issue_slots[6].in_uop.bits.fu_code[3]
connect slots_6.io.in_uop.bits.fu_code[4], issue_slots[6].in_uop.bits.fu_code[4]
connect slots_6.io.in_uop.bits.fu_code[5], issue_slots[6].in_uop.bits.fu_code[5]
connect slots_6.io.in_uop.bits.fu_code[6], issue_slots[6].in_uop.bits.fu_code[6]
connect slots_6.io.in_uop.bits.fu_code[7], issue_slots[6].in_uop.bits.fu_code[7]
connect slots_6.io.in_uop.bits.fu_code[8], issue_slots[6].in_uop.bits.fu_code[8]
connect slots_6.io.in_uop.bits.fu_code[9], issue_slots[6].in_uop.bits.fu_code[9]
connect slots_6.io.in_uop.bits.iq_type[0], issue_slots[6].in_uop.bits.iq_type[0]
connect slots_6.io.in_uop.bits.iq_type[1], issue_slots[6].in_uop.bits.iq_type[1]
connect slots_6.io.in_uop.bits.iq_type[2], issue_slots[6].in_uop.bits.iq_type[2]
connect slots_6.io.in_uop.bits.iq_type[3], issue_slots[6].in_uop.bits.iq_type[3]
connect slots_6.io.in_uop.bits.debug_pc, issue_slots[6].in_uop.bits.debug_pc
connect slots_6.io.in_uop.bits.is_rvc, issue_slots[6].in_uop.bits.is_rvc
connect slots_6.io.in_uop.bits.debug_inst, issue_slots[6].in_uop.bits.debug_inst
connect slots_6.io.in_uop.bits.inst, issue_slots[6].in_uop.bits.inst
connect slots_6.io.in_uop.valid, issue_slots[6].in_uop.valid
connect issue_slots[6].iss_uop.debug_tsrc, slots_6.io.iss_uop.debug_tsrc
connect issue_slots[6].iss_uop.debug_fsrc, slots_6.io.iss_uop.debug_fsrc
connect issue_slots[6].iss_uop.bp_xcpt_if, slots_6.io.iss_uop.bp_xcpt_if
connect issue_slots[6].iss_uop.bp_debug_if, slots_6.io.iss_uop.bp_debug_if
connect issue_slots[6].iss_uop.xcpt_ma_if, slots_6.io.iss_uop.xcpt_ma_if
connect issue_slots[6].iss_uop.xcpt_ae_if, slots_6.io.iss_uop.xcpt_ae_if
connect issue_slots[6].iss_uop.xcpt_pf_if, slots_6.io.iss_uop.xcpt_pf_if
connect issue_slots[6].iss_uop.fp_typ, slots_6.io.iss_uop.fp_typ
connect issue_slots[6].iss_uop.fp_rm, slots_6.io.iss_uop.fp_rm
connect issue_slots[6].iss_uop.fp_val, slots_6.io.iss_uop.fp_val
connect issue_slots[6].iss_uop.fcn_op, slots_6.io.iss_uop.fcn_op
connect issue_slots[6].iss_uop.fcn_dw, slots_6.io.iss_uop.fcn_dw
connect issue_slots[6].iss_uop.frs3_en, slots_6.io.iss_uop.frs3_en
connect issue_slots[6].iss_uop.lrs2_rtype, slots_6.io.iss_uop.lrs2_rtype
connect issue_slots[6].iss_uop.lrs1_rtype, slots_6.io.iss_uop.lrs1_rtype
connect issue_slots[6].iss_uop.dst_rtype, slots_6.io.iss_uop.dst_rtype
connect issue_slots[6].iss_uop.lrs3, slots_6.io.iss_uop.lrs3
connect issue_slots[6].iss_uop.lrs2, slots_6.io.iss_uop.lrs2
connect issue_slots[6].iss_uop.lrs1, slots_6.io.iss_uop.lrs1
connect issue_slots[6].iss_uop.ldst, slots_6.io.iss_uop.ldst
connect issue_slots[6].iss_uop.ldst_is_rs1, slots_6.io.iss_uop.ldst_is_rs1
connect issue_slots[6].iss_uop.csr_cmd, slots_6.io.iss_uop.csr_cmd
connect issue_slots[6].iss_uop.flush_on_commit, slots_6.io.iss_uop.flush_on_commit
connect issue_slots[6].iss_uop.is_unique, slots_6.io.iss_uop.is_unique
connect issue_slots[6].iss_uop.uses_stq, slots_6.io.iss_uop.uses_stq
connect issue_slots[6].iss_uop.uses_ldq, slots_6.io.iss_uop.uses_ldq
connect issue_slots[6].iss_uop.mem_signed, slots_6.io.iss_uop.mem_signed
connect issue_slots[6].iss_uop.mem_size, slots_6.io.iss_uop.mem_size
connect issue_slots[6].iss_uop.mem_cmd, slots_6.io.iss_uop.mem_cmd
connect issue_slots[6].iss_uop.exc_cause, slots_6.io.iss_uop.exc_cause
connect issue_slots[6].iss_uop.exception, slots_6.io.iss_uop.exception
connect issue_slots[6].iss_uop.stale_pdst, slots_6.io.iss_uop.stale_pdst
connect issue_slots[6].iss_uop.ppred_busy, slots_6.io.iss_uop.ppred_busy
connect issue_slots[6].iss_uop.prs3_busy, slots_6.io.iss_uop.prs3_busy
connect issue_slots[6].iss_uop.prs2_busy, slots_6.io.iss_uop.prs2_busy
connect issue_slots[6].iss_uop.prs1_busy, slots_6.io.iss_uop.prs1_busy
connect issue_slots[6].iss_uop.ppred, slots_6.io.iss_uop.ppred
connect issue_slots[6].iss_uop.prs3, slots_6.io.iss_uop.prs3
connect issue_slots[6].iss_uop.prs2, slots_6.io.iss_uop.prs2
connect issue_slots[6].iss_uop.prs1, slots_6.io.iss_uop.prs1
connect issue_slots[6].iss_uop.pdst, slots_6.io.iss_uop.pdst
connect issue_slots[6].iss_uop.rxq_idx, slots_6.io.iss_uop.rxq_idx
connect issue_slots[6].iss_uop.stq_idx, slots_6.io.iss_uop.stq_idx
connect issue_slots[6].iss_uop.ldq_idx, slots_6.io.iss_uop.ldq_idx
connect issue_slots[6].iss_uop.rob_idx, slots_6.io.iss_uop.rob_idx
connect issue_slots[6].iss_uop.fp_ctrl.vec, slots_6.io.iss_uop.fp_ctrl.vec
connect issue_slots[6].iss_uop.fp_ctrl.wflags, slots_6.io.iss_uop.fp_ctrl.wflags
connect issue_slots[6].iss_uop.fp_ctrl.sqrt, slots_6.io.iss_uop.fp_ctrl.sqrt
connect issue_slots[6].iss_uop.fp_ctrl.div, slots_6.io.iss_uop.fp_ctrl.div
connect issue_slots[6].iss_uop.fp_ctrl.fma, slots_6.io.iss_uop.fp_ctrl.fma
connect issue_slots[6].iss_uop.fp_ctrl.fastpipe, slots_6.io.iss_uop.fp_ctrl.fastpipe
connect issue_slots[6].iss_uop.fp_ctrl.toint, slots_6.io.iss_uop.fp_ctrl.toint
connect issue_slots[6].iss_uop.fp_ctrl.fromint, slots_6.io.iss_uop.fp_ctrl.fromint
connect issue_slots[6].iss_uop.fp_ctrl.typeTagOut, slots_6.io.iss_uop.fp_ctrl.typeTagOut
connect issue_slots[6].iss_uop.fp_ctrl.typeTagIn, slots_6.io.iss_uop.fp_ctrl.typeTagIn
connect issue_slots[6].iss_uop.fp_ctrl.swap23, slots_6.io.iss_uop.fp_ctrl.swap23
connect issue_slots[6].iss_uop.fp_ctrl.swap12, slots_6.io.iss_uop.fp_ctrl.swap12
connect issue_slots[6].iss_uop.fp_ctrl.ren3, slots_6.io.iss_uop.fp_ctrl.ren3
connect issue_slots[6].iss_uop.fp_ctrl.ren2, slots_6.io.iss_uop.fp_ctrl.ren2
connect issue_slots[6].iss_uop.fp_ctrl.ren1, slots_6.io.iss_uop.fp_ctrl.ren1
connect issue_slots[6].iss_uop.fp_ctrl.wen, slots_6.io.iss_uop.fp_ctrl.wen
connect issue_slots[6].iss_uop.fp_ctrl.ldst, slots_6.io.iss_uop.fp_ctrl.ldst
connect issue_slots[6].iss_uop.op2_sel, slots_6.io.iss_uop.op2_sel
connect issue_slots[6].iss_uop.op1_sel, slots_6.io.iss_uop.op1_sel
connect issue_slots[6].iss_uop.imm_packed, slots_6.io.iss_uop.imm_packed
connect issue_slots[6].iss_uop.pimm, slots_6.io.iss_uop.pimm
connect issue_slots[6].iss_uop.imm_sel, slots_6.io.iss_uop.imm_sel
connect issue_slots[6].iss_uop.imm_rename, slots_6.io.iss_uop.imm_rename
connect issue_slots[6].iss_uop.taken, slots_6.io.iss_uop.taken
connect issue_slots[6].iss_uop.pc_lob, slots_6.io.iss_uop.pc_lob
connect issue_slots[6].iss_uop.edge_inst, slots_6.io.iss_uop.edge_inst
connect issue_slots[6].iss_uop.ftq_idx, slots_6.io.iss_uop.ftq_idx
connect issue_slots[6].iss_uop.is_mov, slots_6.io.iss_uop.is_mov
connect issue_slots[6].iss_uop.is_rocc, slots_6.io.iss_uop.is_rocc
connect issue_slots[6].iss_uop.is_sys_pc2epc, slots_6.io.iss_uop.is_sys_pc2epc
connect issue_slots[6].iss_uop.is_eret, slots_6.io.iss_uop.is_eret
connect issue_slots[6].iss_uop.is_amo, slots_6.io.iss_uop.is_amo
connect issue_slots[6].iss_uop.is_sfence, slots_6.io.iss_uop.is_sfence
connect issue_slots[6].iss_uop.is_fencei, slots_6.io.iss_uop.is_fencei
connect issue_slots[6].iss_uop.is_fence, slots_6.io.iss_uop.is_fence
connect issue_slots[6].iss_uop.is_sfb, slots_6.io.iss_uop.is_sfb
connect issue_slots[6].iss_uop.br_type, slots_6.io.iss_uop.br_type
connect issue_slots[6].iss_uop.br_tag, slots_6.io.iss_uop.br_tag
connect issue_slots[6].iss_uop.br_mask, slots_6.io.iss_uop.br_mask
connect issue_slots[6].iss_uop.dis_col_sel, slots_6.io.iss_uop.dis_col_sel
connect issue_slots[6].iss_uop.iw_p3_bypass_hint, slots_6.io.iss_uop.iw_p3_bypass_hint
connect issue_slots[6].iss_uop.iw_p2_bypass_hint, slots_6.io.iss_uop.iw_p2_bypass_hint
connect issue_slots[6].iss_uop.iw_p1_bypass_hint, slots_6.io.iss_uop.iw_p1_bypass_hint
connect issue_slots[6].iss_uop.iw_p2_speculative_child, slots_6.io.iss_uop.iw_p2_speculative_child
connect issue_slots[6].iss_uop.iw_p1_speculative_child, slots_6.io.iss_uop.iw_p1_speculative_child
connect issue_slots[6].iss_uop.iw_issued_partial_dgen, slots_6.io.iss_uop.iw_issued_partial_dgen
connect issue_slots[6].iss_uop.iw_issued_partial_agen, slots_6.io.iss_uop.iw_issued_partial_agen
connect issue_slots[6].iss_uop.iw_issued, slots_6.io.iss_uop.iw_issued
connect issue_slots[6].iss_uop.fu_code[0], slots_6.io.iss_uop.fu_code[0]
connect issue_slots[6].iss_uop.fu_code[1], slots_6.io.iss_uop.fu_code[1]
connect issue_slots[6].iss_uop.fu_code[2], slots_6.io.iss_uop.fu_code[2]
connect issue_slots[6].iss_uop.fu_code[3], slots_6.io.iss_uop.fu_code[3]
connect issue_slots[6].iss_uop.fu_code[4], slots_6.io.iss_uop.fu_code[4]
connect issue_slots[6].iss_uop.fu_code[5], slots_6.io.iss_uop.fu_code[5]
connect issue_slots[6].iss_uop.fu_code[6], slots_6.io.iss_uop.fu_code[6]
connect issue_slots[6].iss_uop.fu_code[7], slots_6.io.iss_uop.fu_code[7]
connect issue_slots[6].iss_uop.fu_code[8], slots_6.io.iss_uop.fu_code[8]
connect issue_slots[6].iss_uop.fu_code[9], slots_6.io.iss_uop.fu_code[9]
connect issue_slots[6].iss_uop.iq_type[0], slots_6.io.iss_uop.iq_type[0]
connect issue_slots[6].iss_uop.iq_type[1], slots_6.io.iss_uop.iq_type[1]
connect issue_slots[6].iss_uop.iq_type[2], slots_6.io.iss_uop.iq_type[2]
connect issue_slots[6].iss_uop.iq_type[3], slots_6.io.iss_uop.iq_type[3]
connect issue_slots[6].iss_uop.debug_pc, slots_6.io.iss_uop.debug_pc
connect issue_slots[6].iss_uop.is_rvc, slots_6.io.iss_uop.is_rvc
connect issue_slots[6].iss_uop.debug_inst, slots_6.io.iss_uop.debug_inst
connect issue_slots[6].iss_uop.inst, slots_6.io.iss_uop.inst
connect slots_6.io.grant, issue_slots[6].grant
connect issue_slots[6].request, slots_6.io.request
connect issue_slots[6].will_be_valid, slots_6.io.will_be_valid
connect issue_slots[6].valid, slots_6.io.valid
connect slots_7.io.child_rebusys, issue_slots[7].child_rebusys
connect slots_7.io.pred_wakeup_port.bits, issue_slots[7].pred_wakeup_port.bits
connect slots_7.io.pred_wakeup_port.valid, issue_slots[7].pred_wakeup_port.valid
connect slots_7.io.wakeup_ports[0].bits.rebusy, issue_slots[7].wakeup_ports[0].bits.rebusy
connect slots_7.io.wakeup_ports[0].bits.speculative_mask, issue_slots[7].wakeup_ports[0].bits.speculative_mask
connect slots_7.io.wakeup_ports[0].bits.bypassable, issue_slots[7].wakeup_ports[0].bits.bypassable
connect slots_7.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[7].wakeup_ports[0].bits.uop.debug_tsrc
connect slots_7.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[7].wakeup_ports[0].bits.uop.debug_fsrc
connect slots_7.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[7].wakeup_ports[0].bits.uop.bp_xcpt_if
connect slots_7.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[7].wakeup_ports[0].bits.uop.bp_debug_if
connect slots_7.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[7].wakeup_ports[0].bits.uop.xcpt_ma_if
connect slots_7.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[7].wakeup_ports[0].bits.uop.xcpt_ae_if
connect slots_7.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[7].wakeup_ports[0].bits.uop.xcpt_pf_if
connect slots_7.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[7].wakeup_ports[0].bits.uop.fp_typ
connect slots_7.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[7].wakeup_ports[0].bits.uop.fp_rm
connect slots_7.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[7].wakeup_ports[0].bits.uop.fp_val
connect slots_7.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[7].wakeup_ports[0].bits.uop.fcn_op
connect slots_7.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[7].wakeup_ports[0].bits.uop.fcn_dw
connect slots_7.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[7].wakeup_ports[0].bits.uop.frs3_en
connect slots_7.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[7].wakeup_ports[0].bits.uop.lrs2_rtype
connect slots_7.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[7].wakeup_ports[0].bits.uop.lrs1_rtype
connect slots_7.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[7].wakeup_ports[0].bits.uop.dst_rtype
connect slots_7.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[7].wakeup_ports[0].bits.uop.lrs3
connect slots_7.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[7].wakeup_ports[0].bits.uop.lrs2
connect slots_7.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[7].wakeup_ports[0].bits.uop.lrs1
connect slots_7.io.wakeup_ports[0].bits.uop.ldst, issue_slots[7].wakeup_ports[0].bits.uop.ldst
connect slots_7.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[7].wakeup_ports[0].bits.uop.ldst_is_rs1
connect slots_7.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[7].wakeup_ports[0].bits.uop.csr_cmd
connect slots_7.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[7].wakeup_ports[0].bits.uop.flush_on_commit
connect slots_7.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[7].wakeup_ports[0].bits.uop.is_unique
connect slots_7.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[7].wakeup_ports[0].bits.uop.uses_stq
connect slots_7.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[7].wakeup_ports[0].bits.uop.uses_ldq
connect slots_7.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[7].wakeup_ports[0].bits.uop.mem_signed
connect slots_7.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[7].wakeup_ports[0].bits.uop.mem_size
connect slots_7.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[7].wakeup_ports[0].bits.uop.mem_cmd
connect slots_7.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[7].wakeup_ports[0].bits.uop.exc_cause
connect slots_7.io.wakeup_ports[0].bits.uop.exception, issue_slots[7].wakeup_ports[0].bits.uop.exception
connect slots_7.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[7].wakeup_ports[0].bits.uop.stale_pdst
connect slots_7.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[7].wakeup_ports[0].bits.uop.ppred_busy
connect slots_7.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[7].wakeup_ports[0].bits.uop.prs3_busy
connect slots_7.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[7].wakeup_ports[0].bits.uop.prs2_busy
connect slots_7.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[7].wakeup_ports[0].bits.uop.prs1_busy
connect slots_7.io.wakeup_ports[0].bits.uop.ppred, issue_slots[7].wakeup_ports[0].bits.uop.ppred
connect slots_7.io.wakeup_ports[0].bits.uop.prs3, issue_slots[7].wakeup_ports[0].bits.uop.prs3
connect slots_7.io.wakeup_ports[0].bits.uop.prs2, issue_slots[7].wakeup_ports[0].bits.uop.prs2
connect slots_7.io.wakeup_ports[0].bits.uop.prs1, issue_slots[7].wakeup_ports[0].bits.uop.prs1
connect slots_7.io.wakeup_ports[0].bits.uop.pdst, issue_slots[7].wakeup_ports[0].bits.uop.pdst
connect slots_7.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[7].wakeup_ports[0].bits.uop.rxq_idx
connect slots_7.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[7].wakeup_ports[0].bits.uop.stq_idx
connect slots_7.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[7].wakeup_ports[0].bits.uop.ldq_idx
connect slots_7.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[7].wakeup_ports[0].bits.uop.rob_idx
connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.vec
connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.wflags
connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.sqrt
connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.div
connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.fma
connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe
connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.toint
connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.fromint
connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut
connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn
connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.swap23
connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.swap12
connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.ren3
connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.ren2
connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.ren1
connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.wen
connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.ldst
connect slots_7.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[7].wakeup_ports[0].bits.uop.op2_sel
connect slots_7.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[7].wakeup_ports[0].bits.uop.op1_sel
connect slots_7.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[7].wakeup_ports[0].bits.uop.imm_packed
connect slots_7.io.wakeup_ports[0].bits.uop.pimm, issue_slots[7].wakeup_ports[0].bits.uop.pimm
connect slots_7.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[7].wakeup_ports[0].bits.uop.imm_sel
connect slots_7.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[7].wakeup_ports[0].bits.uop.imm_rename
connect slots_7.io.wakeup_ports[0].bits.uop.taken, issue_slots[7].wakeup_ports[0].bits.uop.taken
connect slots_7.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[7].wakeup_ports[0].bits.uop.pc_lob
connect slots_7.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[7].wakeup_ports[0].bits.uop.edge_inst
connect slots_7.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[7].wakeup_ports[0].bits.uop.ftq_idx
connect slots_7.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[7].wakeup_ports[0].bits.uop.is_mov
connect slots_7.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[7].wakeup_ports[0].bits.uop.is_rocc
connect slots_7.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[7].wakeup_ports[0].bits.uop.is_sys_pc2epc
connect slots_7.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[7].wakeup_ports[0].bits.uop.is_eret
connect slots_7.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[7].wakeup_ports[0].bits.uop.is_amo
connect slots_7.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[7].wakeup_ports[0].bits.uop.is_sfence
connect slots_7.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[7].wakeup_ports[0].bits.uop.is_fencei
connect slots_7.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[7].wakeup_ports[0].bits.uop.is_fence
connect slots_7.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[7].wakeup_ports[0].bits.uop.is_sfb
connect slots_7.io.wakeup_ports[0].bits.uop.br_type, issue_slots[7].wakeup_ports[0].bits.uop.br_type
connect slots_7.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[7].wakeup_ports[0].bits.uop.br_tag
connect slots_7.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[7].wakeup_ports[0].bits.uop.br_mask
connect slots_7.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[7].wakeup_ports[0].bits.uop.dis_col_sel
connect slots_7.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[7].wakeup_ports[0].bits.uop.iw_p3_bypass_hint
connect slots_7.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[7].wakeup_ports[0].bits.uop.iw_p2_bypass_hint
connect slots_7.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[7].wakeup_ports[0].bits.uop.iw_p1_bypass_hint
connect slots_7.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[7].wakeup_ports[0].bits.uop.iw_p2_speculative_child
connect slots_7.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[7].wakeup_ports[0].bits.uop.iw_p1_speculative_child
connect slots_7.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[7].wakeup_ports[0].bits.uop.iw_issued_partial_dgen
connect slots_7.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[7].wakeup_ports[0].bits.uop.iw_issued_partial_agen
connect slots_7.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[7].wakeup_ports[0].bits.uop.iw_issued
connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[0]
connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[1]
connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[2]
connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[3]
connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[4]
connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[5]
connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[6]
connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[7]
connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[8]
connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[9]
connect slots_7.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[7].wakeup_ports[0].bits.uop.iq_type[0]
connect slots_7.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[7].wakeup_ports[0].bits.uop.iq_type[1]
connect slots_7.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[7].wakeup_ports[0].bits.uop.iq_type[2]
connect slots_7.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[7].wakeup_ports[0].bits.uop.iq_type[3]
connect slots_7.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[7].wakeup_ports[0].bits.uop.debug_pc
connect slots_7.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[7].wakeup_ports[0].bits.uop.is_rvc
connect slots_7.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[7].wakeup_ports[0].bits.uop.debug_inst
connect slots_7.io.wakeup_ports[0].bits.uop.inst, issue_slots[7].wakeup_ports[0].bits.uop.inst
connect slots_7.io.wakeup_ports[0].valid, issue_slots[7].wakeup_ports[0].valid
connect slots_7.io.wakeup_ports[1].bits.rebusy, issue_slots[7].wakeup_ports[1].bits.rebusy
connect slots_7.io.wakeup_ports[1].bits.speculative_mask, issue_slots[7].wakeup_ports[1].bits.speculative_mask
connect slots_7.io.wakeup_ports[1].bits.bypassable, issue_slots[7].wakeup_ports[1].bits.bypassable
connect slots_7.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[7].wakeup_ports[1].bits.uop.debug_tsrc
connect slots_7.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[7].wakeup_ports[1].bits.uop.debug_fsrc
connect slots_7.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[7].wakeup_ports[1].bits.uop.bp_xcpt_if
connect slots_7.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[7].wakeup_ports[1].bits.uop.bp_debug_if
connect slots_7.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[7].wakeup_ports[1].bits.uop.xcpt_ma_if
connect slots_7.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[7].wakeup_ports[1].bits.uop.xcpt_ae_if
connect slots_7.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[7].wakeup_ports[1].bits.uop.xcpt_pf_if
connect slots_7.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[7].wakeup_ports[1].bits.uop.fp_typ
connect slots_7.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[7].wakeup_ports[1].bits.uop.fp_rm
connect slots_7.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[7].wakeup_ports[1].bits.uop.fp_val
connect slots_7.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[7].wakeup_ports[1].bits.uop.fcn_op
connect slots_7.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[7].wakeup_ports[1].bits.uop.fcn_dw
connect slots_7.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[7].wakeup_ports[1].bits.uop.frs3_en
connect slots_7.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[7].wakeup_ports[1].bits.uop.lrs2_rtype
connect slots_7.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[7].wakeup_ports[1].bits.uop.lrs1_rtype
connect slots_7.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[7].wakeup_ports[1].bits.uop.dst_rtype
connect slots_7.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[7].wakeup_ports[1].bits.uop.lrs3
connect slots_7.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[7].wakeup_ports[1].bits.uop.lrs2
connect slots_7.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[7].wakeup_ports[1].bits.uop.lrs1
connect slots_7.io.wakeup_ports[1].bits.uop.ldst, issue_slots[7].wakeup_ports[1].bits.uop.ldst
connect slots_7.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[7].wakeup_ports[1].bits.uop.ldst_is_rs1
connect slots_7.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[7].wakeup_ports[1].bits.uop.csr_cmd
connect slots_7.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[7].wakeup_ports[1].bits.uop.flush_on_commit
connect slots_7.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[7].wakeup_ports[1].bits.uop.is_unique
connect slots_7.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[7].wakeup_ports[1].bits.uop.uses_stq
connect slots_7.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[7].wakeup_ports[1].bits.uop.uses_ldq
connect slots_7.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[7].wakeup_ports[1].bits.uop.mem_signed
connect slots_7.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[7].wakeup_ports[1].bits.uop.mem_size
connect slots_7.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[7].wakeup_ports[1].bits.uop.mem_cmd
connect slots_7.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[7].wakeup_ports[1].bits.uop.exc_cause
connect slots_7.io.wakeup_ports[1].bits.uop.exception, issue_slots[7].wakeup_ports[1].bits.uop.exception
connect slots_7.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[7].wakeup_ports[1].bits.uop.stale_pdst
connect slots_7.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[7].wakeup_ports[1].bits.uop.ppred_busy
connect slots_7.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[7].wakeup_ports[1].bits.uop.prs3_busy
connect slots_7.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[7].wakeup_ports[1].bits.uop.prs2_busy
connect slots_7.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[7].wakeup_ports[1].bits.uop.prs1_busy
connect slots_7.io.wakeup_ports[1].bits.uop.ppred, issue_slots[7].wakeup_ports[1].bits.uop.ppred
connect slots_7.io.wakeup_ports[1].bits.uop.prs3, issue_slots[7].wakeup_ports[1].bits.uop.prs3
connect slots_7.io.wakeup_ports[1].bits.uop.prs2, issue_slots[7].wakeup_ports[1].bits.uop.prs2
connect slots_7.io.wakeup_ports[1].bits.uop.prs1, issue_slots[7].wakeup_ports[1].bits.uop.prs1
connect slots_7.io.wakeup_ports[1].bits.uop.pdst, issue_slots[7].wakeup_ports[1].bits.uop.pdst
connect slots_7.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[7].wakeup_ports[1].bits.uop.rxq_idx
connect slots_7.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[7].wakeup_ports[1].bits.uop.stq_idx
connect slots_7.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[7].wakeup_ports[1].bits.uop.ldq_idx
connect slots_7.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[7].wakeup_ports[1].bits.uop.rob_idx
connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.vec
connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.wflags
connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.sqrt
connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.div
connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.fma
connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe
connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.toint
connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.fromint
connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut
connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn
connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.swap23
connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.swap12
connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.ren3
connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.ren2
connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.ren1
connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.wen
connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.ldst
connect slots_7.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[7].wakeup_ports[1].bits.uop.op2_sel
connect slots_7.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[7].wakeup_ports[1].bits.uop.op1_sel
connect slots_7.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[7].wakeup_ports[1].bits.uop.imm_packed
connect slots_7.io.wakeup_ports[1].bits.uop.pimm, issue_slots[7].wakeup_ports[1].bits.uop.pimm
connect slots_7.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[7].wakeup_ports[1].bits.uop.imm_sel
connect slots_7.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[7].wakeup_ports[1].bits.uop.imm_rename
connect slots_7.io.wakeup_ports[1].bits.uop.taken, issue_slots[7].wakeup_ports[1].bits.uop.taken
connect slots_7.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[7].wakeup_ports[1].bits.uop.pc_lob
connect slots_7.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[7].wakeup_ports[1].bits.uop.edge_inst
connect slots_7.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[7].wakeup_ports[1].bits.uop.ftq_idx
connect slots_7.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[7].wakeup_ports[1].bits.uop.is_mov
connect slots_7.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[7].wakeup_ports[1].bits.uop.is_rocc
connect slots_7.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[7].wakeup_ports[1].bits.uop.is_sys_pc2epc
connect slots_7.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[7].wakeup_ports[1].bits.uop.is_eret
connect slots_7.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[7].wakeup_ports[1].bits.uop.is_amo
connect slots_7.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[7].wakeup_ports[1].bits.uop.is_sfence
connect slots_7.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[7].wakeup_ports[1].bits.uop.is_fencei
connect slots_7.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[7].wakeup_ports[1].bits.uop.is_fence
connect slots_7.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[7].wakeup_ports[1].bits.uop.is_sfb
connect slots_7.io.wakeup_ports[1].bits.uop.br_type, issue_slots[7].wakeup_ports[1].bits.uop.br_type
connect slots_7.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[7].wakeup_ports[1].bits.uop.br_tag
connect slots_7.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[7].wakeup_ports[1].bits.uop.br_mask
connect slots_7.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[7].wakeup_ports[1].bits.uop.dis_col_sel
connect slots_7.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[7].wakeup_ports[1].bits.uop.iw_p3_bypass_hint
connect slots_7.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[7].wakeup_ports[1].bits.uop.iw_p2_bypass_hint
connect slots_7.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[7].wakeup_ports[1].bits.uop.iw_p1_bypass_hint
connect slots_7.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[7].wakeup_ports[1].bits.uop.iw_p2_speculative_child
connect slots_7.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[7].wakeup_ports[1].bits.uop.iw_p1_speculative_child
connect slots_7.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[7].wakeup_ports[1].bits.uop.iw_issued_partial_dgen
connect slots_7.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[7].wakeup_ports[1].bits.uop.iw_issued_partial_agen
connect slots_7.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[7].wakeup_ports[1].bits.uop.iw_issued
connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[0]
connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[1]
connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[2]
connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[3]
connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[4]
connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[5]
connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[6]
connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[7]
connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[8]
connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[9]
connect slots_7.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[7].wakeup_ports[1].bits.uop.iq_type[0]
connect slots_7.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[7].wakeup_ports[1].bits.uop.iq_type[1]
connect slots_7.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[7].wakeup_ports[1].bits.uop.iq_type[2]
connect slots_7.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[7].wakeup_ports[1].bits.uop.iq_type[3]
connect slots_7.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[7].wakeup_ports[1].bits.uop.debug_pc
connect slots_7.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[7].wakeup_ports[1].bits.uop.is_rvc
connect slots_7.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[7].wakeup_ports[1].bits.uop.debug_inst
connect slots_7.io.wakeup_ports[1].bits.uop.inst, issue_slots[7].wakeup_ports[1].bits.uop.inst
connect slots_7.io.wakeup_ports[1].valid, issue_slots[7].wakeup_ports[1].valid
connect slots_7.io.wakeup_ports[2].bits.rebusy, issue_slots[7].wakeup_ports[2].bits.rebusy
connect slots_7.io.wakeup_ports[2].bits.speculative_mask, issue_slots[7].wakeup_ports[2].bits.speculative_mask
connect slots_7.io.wakeup_ports[2].bits.bypassable, issue_slots[7].wakeup_ports[2].bits.bypassable
connect slots_7.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[7].wakeup_ports[2].bits.uop.debug_tsrc
connect slots_7.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[7].wakeup_ports[2].bits.uop.debug_fsrc
connect slots_7.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[7].wakeup_ports[2].bits.uop.bp_xcpt_if
connect slots_7.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[7].wakeup_ports[2].bits.uop.bp_debug_if
connect slots_7.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[7].wakeup_ports[2].bits.uop.xcpt_ma_if
connect slots_7.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[7].wakeup_ports[2].bits.uop.xcpt_ae_if
connect slots_7.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[7].wakeup_ports[2].bits.uop.xcpt_pf_if
connect slots_7.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[7].wakeup_ports[2].bits.uop.fp_typ
connect slots_7.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[7].wakeup_ports[2].bits.uop.fp_rm
connect slots_7.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[7].wakeup_ports[2].bits.uop.fp_val
connect slots_7.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[7].wakeup_ports[2].bits.uop.fcn_op
connect slots_7.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[7].wakeup_ports[2].bits.uop.fcn_dw
connect slots_7.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[7].wakeup_ports[2].bits.uop.frs3_en
connect slots_7.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[7].wakeup_ports[2].bits.uop.lrs2_rtype
connect slots_7.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[7].wakeup_ports[2].bits.uop.lrs1_rtype
connect slots_7.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[7].wakeup_ports[2].bits.uop.dst_rtype
connect slots_7.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[7].wakeup_ports[2].bits.uop.lrs3
connect slots_7.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[7].wakeup_ports[2].bits.uop.lrs2
connect slots_7.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[7].wakeup_ports[2].bits.uop.lrs1
connect slots_7.io.wakeup_ports[2].bits.uop.ldst, issue_slots[7].wakeup_ports[2].bits.uop.ldst
connect slots_7.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[7].wakeup_ports[2].bits.uop.ldst_is_rs1
connect slots_7.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[7].wakeup_ports[2].bits.uop.csr_cmd
connect slots_7.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[7].wakeup_ports[2].bits.uop.flush_on_commit
connect slots_7.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[7].wakeup_ports[2].bits.uop.is_unique
connect slots_7.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[7].wakeup_ports[2].bits.uop.uses_stq
connect slots_7.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[7].wakeup_ports[2].bits.uop.uses_ldq
connect slots_7.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[7].wakeup_ports[2].bits.uop.mem_signed
connect slots_7.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[7].wakeup_ports[2].bits.uop.mem_size
connect slots_7.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[7].wakeup_ports[2].bits.uop.mem_cmd
connect slots_7.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[7].wakeup_ports[2].bits.uop.exc_cause
connect slots_7.io.wakeup_ports[2].bits.uop.exception, issue_slots[7].wakeup_ports[2].bits.uop.exception
connect slots_7.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[7].wakeup_ports[2].bits.uop.stale_pdst
connect slots_7.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[7].wakeup_ports[2].bits.uop.ppred_busy
connect slots_7.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[7].wakeup_ports[2].bits.uop.prs3_busy
connect slots_7.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[7].wakeup_ports[2].bits.uop.prs2_busy
connect slots_7.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[7].wakeup_ports[2].bits.uop.prs1_busy
connect slots_7.io.wakeup_ports[2].bits.uop.ppred, issue_slots[7].wakeup_ports[2].bits.uop.ppred
connect slots_7.io.wakeup_ports[2].bits.uop.prs3, issue_slots[7].wakeup_ports[2].bits.uop.prs3
connect slots_7.io.wakeup_ports[2].bits.uop.prs2, issue_slots[7].wakeup_ports[2].bits.uop.prs2
connect slots_7.io.wakeup_ports[2].bits.uop.prs1, issue_slots[7].wakeup_ports[2].bits.uop.prs1
connect slots_7.io.wakeup_ports[2].bits.uop.pdst, issue_slots[7].wakeup_ports[2].bits.uop.pdst
connect slots_7.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[7].wakeup_ports[2].bits.uop.rxq_idx
connect slots_7.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[7].wakeup_ports[2].bits.uop.stq_idx
connect slots_7.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[7].wakeup_ports[2].bits.uop.ldq_idx
connect slots_7.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[7].wakeup_ports[2].bits.uop.rob_idx
connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.vec
connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.wflags
connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.sqrt
connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.div
connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.fma
connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe
connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.toint
connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.fromint
connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut
connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn
connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.swap23
connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.swap12
connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.ren3
connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.ren2
connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.ren1
connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.wen
connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.ldst
connect slots_7.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[7].wakeup_ports[2].bits.uop.op2_sel
connect slots_7.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[7].wakeup_ports[2].bits.uop.op1_sel
connect slots_7.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[7].wakeup_ports[2].bits.uop.imm_packed
connect slots_7.io.wakeup_ports[2].bits.uop.pimm, issue_slots[7].wakeup_ports[2].bits.uop.pimm
connect slots_7.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[7].wakeup_ports[2].bits.uop.imm_sel
connect slots_7.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[7].wakeup_ports[2].bits.uop.imm_rename
connect slots_7.io.wakeup_ports[2].bits.uop.taken, issue_slots[7].wakeup_ports[2].bits.uop.taken
connect slots_7.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[7].wakeup_ports[2].bits.uop.pc_lob
connect slots_7.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[7].wakeup_ports[2].bits.uop.edge_inst
connect slots_7.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[7].wakeup_ports[2].bits.uop.ftq_idx
connect slots_7.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[7].wakeup_ports[2].bits.uop.is_mov
connect slots_7.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[7].wakeup_ports[2].bits.uop.is_rocc
connect slots_7.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[7].wakeup_ports[2].bits.uop.is_sys_pc2epc
connect slots_7.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[7].wakeup_ports[2].bits.uop.is_eret
connect slots_7.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[7].wakeup_ports[2].bits.uop.is_amo
connect slots_7.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[7].wakeup_ports[2].bits.uop.is_sfence
connect slots_7.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[7].wakeup_ports[2].bits.uop.is_fencei
connect slots_7.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[7].wakeup_ports[2].bits.uop.is_fence
connect slots_7.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[7].wakeup_ports[2].bits.uop.is_sfb
connect slots_7.io.wakeup_ports[2].bits.uop.br_type, issue_slots[7].wakeup_ports[2].bits.uop.br_type
connect slots_7.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[7].wakeup_ports[2].bits.uop.br_tag
connect slots_7.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[7].wakeup_ports[2].bits.uop.br_mask
connect slots_7.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[7].wakeup_ports[2].bits.uop.dis_col_sel
connect slots_7.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[7].wakeup_ports[2].bits.uop.iw_p3_bypass_hint
connect slots_7.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[7].wakeup_ports[2].bits.uop.iw_p2_bypass_hint
connect slots_7.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[7].wakeup_ports[2].bits.uop.iw_p1_bypass_hint
connect slots_7.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[7].wakeup_ports[2].bits.uop.iw_p2_speculative_child
connect slots_7.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[7].wakeup_ports[2].bits.uop.iw_p1_speculative_child
connect slots_7.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[7].wakeup_ports[2].bits.uop.iw_issued_partial_dgen
connect slots_7.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[7].wakeup_ports[2].bits.uop.iw_issued_partial_agen
connect slots_7.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[7].wakeup_ports[2].bits.uop.iw_issued
connect slots_7.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[7].wakeup_ports[2].bits.uop.fu_code[0]
connect slots_7.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[7].wakeup_ports[2].bits.uop.fu_code[1]
connect slots_7.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[7].wakeup_ports[2].bits.uop.fu_code[2]
connect slots_7.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[7].wakeup_ports[2].bits.uop.fu_code[3]
connect slots_7.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[7].wakeup_ports[2].bits.uop.fu_code[4]
connect slots_7.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[7].wakeup_ports[2].bits.uop.fu_code[5]
connect slots_7.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[7].wakeup_ports[2].bits.uop.fu_code[6]
connect slots_7.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[7].wakeup_ports[2].bits.uop.fu_code[7]
connect slots_7.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[7].wakeup_ports[2].bits.uop.fu_code[8]
connect slots_7.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[7].wakeup_ports[2].bits.uop.fu_code[9]
connect slots_7.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[7].wakeup_ports[2].bits.uop.iq_type[0]
connect slots_7.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[7].wakeup_ports[2].bits.uop.iq_type[1]
connect slots_7.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[7].wakeup_ports[2].bits.uop.iq_type[2]
connect slots_7.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[7].wakeup_ports[2].bits.uop.iq_type[3]
connect slots_7.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[7].wakeup_ports[2].bits.uop.debug_pc
connect slots_7.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[7].wakeup_ports[2].bits.uop.is_rvc
connect slots_7.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[7].wakeup_ports[2].bits.uop.debug_inst
connect slots_7.io.wakeup_ports[2].bits.uop.inst, issue_slots[7].wakeup_ports[2].bits.uop.inst
connect slots_7.io.wakeup_ports[2].valid, issue_slots[7].wakeup_ports[2].valid
connect slots_7.io.wakeup_ports[3].bits.rebusy, issue_slots[7].wakeup_ports[3].bits.rebusy
connect slots_7.io.wakeup_ports[3].bits.speculative_mask, issue_slots[7].wakeup_ports[3].bits.speculative_mask
connect slots_7.io.wakeup_ports[3].bits.bypassable, issue_slots[7].wakeup_ports[3].bits.bypassable
connect slots_7.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[7].wakeup_ports[3].bits.uop.debug_tsrc
connect slots_7.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[7].wakeup_ports[3].bits.uop.debug_fsrc
connect slots_7.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[7].wakeup_ports[3].bits.uop.bp_xcpt_if
connect slots_7.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[7].wakeup_ports[3].bits.uop.bp_debug_if
connect slots_7.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[7].wakeup_ports[3].bits.uop.xcpt_ma_if
connect slots_7.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[7].wakeup_ports[3].bits.uop.xcpt_ae_if
connect slots_7.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[7].wakeup_ports[3].bits.uop.xcpt_pf_if
connect slots_7.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[7].wakeup_ports[3].bits.uop.fp_typ
connect slots_7.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[7].wakeup_ports[3].bits.uop.fp_rm
connect slots_7.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[7].wakeup_ports[3].bits.uop.fp_val
connect slots_7.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[7].wakeup_ports[3].bits.uop.fcn_op
connect slots_7.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[7].wakeup_ports[3].bits.uop.fcn_dw
connect slots_7.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[7].wakeup_ports[3].bits.uop.frs3_en
connect slots_7.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[7].wakeup_ports[3].bits.uop.lrs2_rtype
connect slots_7.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[7].wakeup_ports[3].bits.uop.lrs1_rtype
connect slots_7.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[7].wakeup_ports[3].bits.uop.dst_rtype
connect slots_7.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[7].wakeup_ports[3].bits.uop.lrs3
connect slots_7.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[7].wakeup_ports[3].bits.uop.lrs2
connect slots_7.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[7].wakeup_ports[3].bits.uop.lrs1
connect slots_7.io.wakeup_ports[3].bits.uop.ldst, issue_slots[7].wakeup_ports[3].bits.uop.ldst
connect slots_7.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[7].wakeup_ports[3].bits.uop.ldst_is_rs1
connect slots_7.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[7].wakeup_ports[3].bits.uop.csr_cmd
connect slots_7.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[7].wakeup_ports[3].bits.uop.flush_on_commit
connect slots_7.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[7].wakeup_ports[3].bits.uop.is_unique
connect slots_7.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[7].wakeup_ports[3].bits.uop.uses_stq
connect slots_7.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[7].wakeup_ports[3].bits.uop.uses_ldq
connect slots_7.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[7].wakeup_ports[3].bits.uop.mem_signed
connect slots_7.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[7].wakeup_ports[3].bits.uop.mem_size
connect slots_7.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[7].wakeup_ports[3].bits.uop.mem_cmd
connect slots_7.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[7].wakeup_ports[3].bits.uop.exc_cause
connect slots_7.io.wakeup_ports[3].bits.uop.exception, issue_slots[7].wakeup_ports[3].bits.uop.exception
connect slots_7.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[7].wakeup_ports[3].bits.uop.stale_pdst
connect slots_7.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[7].wakeup_ports[3].bits.uop.ppred_busy
connect slots_7.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[7].wakeup_ports[3].bits.uop.prs3_busy
connect slots_7.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[7].wakeup_ports[3].bits.uop.prs2_busy
connect slots_7.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[7].wakeup_ports[3].bits.uop.prs1_busy
connect slots_7.io.wakeup_ports[3].bits.uop.ppred, issue_slots[7].wakeup_ports[3].bits.uop.ppred
connect slots_7.io.wakeup_ports[3].bits.uop.prs3, issue_slots[7].wakeup_ports[3].bits.uop.prs3
connect slots_7.io.wakeup_ports[3].bits.uop.prs2, issue_slots[7].wakeup_ports[3].bits.uop.prs2
connect slots_7.io.wakeup_ports[3].bits.uop.prs1, issue_slots[7].wakeup_ports[3].bits.uop.prs1
connect slots_7.io.wakeup_ports[3].bits.uop.pdst, issue_slots[7].wakeup_ports[3].bits.uop.pdst
connect slots_7.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[7].wakeup_ports[3].bits.uop.rxq_idx
connect slots_7.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[7].wakeup_ports[3].bits.uop.stq_idx
connect slots_7.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[7].wakeup_ports[3].bits.uop.ldq_idx
connect slots_7.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[7].wakeup_ports[3].bits.uop.rob_idx
connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.vec
connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.wflags
connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.sqrt
connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.div
connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.fma
connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe
connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.toint
connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.fromint
connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut
connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn
connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.swap23
connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.swap12
connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.ren3
connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.ren2
connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.ren1
connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.wen
connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.ldst
connect slots_7.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[7].wakeup_ports[3].bits.uop.op2_sel
connect slots_7.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[7].wakeup_ports[3].bits.uop.op1_sel
connect slots_7.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[7].wakeup_ports[3].bits.uop.imm_packed
connect slots_7.io.wakeup_ports[3].bits.uop.pimm, issue_slots[7].wakeup_ports[3].bits.uop.pimm
connect slots_7.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[7].wakeup_ports[3].bits.uop.imm_sel
connect slots_7.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[7].wakeup_ports[3].bits.uop.imm_rename
connect slots_7.io.wakeup_ports[3].bits.uop.taken, issue_slots[7].wakeup_ports[3].bits.uop.taken
connect slots_7.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[7].wakeup_ports[3].bits.uop.pc_lob
connect slots_7.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[7].wakeup_ports[3].bits.uop.edge_inst
connect slots_7.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[7].wakeup_ports[3].bits.uop.ftq_idx
connect slots_7.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[7].wakeup_ports[3].bits.uop.is_mov
connect slots_7.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[7].wakeup_ports[3].bits.uop.is_rocc
connect slots_7.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[7].wakeup_ports[3].bits.uop.is_sys_pc2epc
connect slots_7.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[7].wakeup_ports[3].bits.uop.is_eret
connect slots_7.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[7].wakeup_ports[3].bits.uop.is_amo
connect slots_7.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[7].wakeup_ports[3].bits.uop.is_sfence
connect slots_7.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[7].wakeup_ports[3].bits.uop.is_fencei
connect slots_7.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[7].wakeup_ports[3].bits.uop.is_fence
connect slots_7.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[7].wakeup_ports[3].bits.uop.is_sfb
connect slots_7.io.wakeup_ports[3].bits.uop.br_type, issue_slots[7].wakeup_ports[3].bits.uop.br_type
connect slots_7.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[7].wakeup_ports[3].bits.uop.br_tag
connect slots_7.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[7].wakeup_ports[3].bits.uop.br_mask
connect slots_7.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[7].wakeup_ports[3].bits.uop.dis_col_sel
connect slots_7.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[7].wakeup_ports[3].bits.uop.iw_p3_bypass_hint
connect slots_7.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[7].wakeup_ports[3].bits.uop.iw_p2_bypass_hint
connect slots_7.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[7].wakeup_ports[3].bits.uop.iw_p1_bypass_hint
connect slots_7.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[7].wakeup_ports[3].bits.uop.iw_p2_speculative_child
connect slots_7.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[7].wakeup_ports[3].bits.uop.iw_p1_speculative_child
connect slots_7.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[7].wakeup_ports[3].bits.uop.iw_issued_partial_dgen
connect slots_7.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[7].wakeup_ports[3].bits.uop.iw_issued_partial_agen
connect slots_7.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[7].wakeup_ports[3].bits.uop.iw_issued
connect slots_7.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[7].wakeup_ports[3].bits.uop.fu_code[0]
connect slots_7.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[7].wakeup_ports[3].bits.uop.fu_code[1]
connect slots_7.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[7].wakeup_ports[3].bits.uop.fu_code[2]
connect slots_7.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[7].wakeup_ports[3].bits.uop.fu_code[3]
connect slots_7.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[7].wakeup_ports[3].bits.uop.fu_code[4]
connect slots_7.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[7].wakeup_ports[3].bits.uop.fu_code[5]
connect slots_7.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[7].wakeup_ports[3].bits.uop.fu_code[6]
connect slots_7.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[7].wakeup_ports[3].bits.uop.fu_code[7]
connect slots_7.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[7].wakeup_ports[3].bits.uop.fu_code[8]
connect slots_7.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[7].wakeup_ports[3].bits.uop.fu_code[9]
connect slots_7.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[7].wakeup_ports[3].bits.uop.iq_type[0]
connect slots_7.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[7].wakeup_ports[3].bits.uop.iq_type[1]
connect slots_7.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[7].wakeup_ports[3].bits.uop.iq_type[2]
connect slots_7.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[7].wakeup_ports[3].bits.uop.iq_type[3]
connect slots_7.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[7].wakeup_ports[3].bits.uop.debug_pc
connect slots_7.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[7].wakeup_ports[3].bits.uop.is_rvc
connect slots_7.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[7].wakeup_ports[3].bits.uop.debug_inst
connect slots_7.io.wakeup_ports[3].bits.uop.inst, issue_slots[7].wakeup_ports[3].bits.uop.inst
connect slots_7.io.wakeup_ports[3].valid, issue_slots[7].wakeup_ports[3].valid
connect slots_7.io.squash_grant, issue_slots[7].squash_grant
connect slots_7.io.clear, issue_slots[7].clear
connect slots_7.io.kill, issue_slots[7].kill
connect slots_7.io.brupdate.b2.target_offset, issue_slots[7].brupdate.b2.target_offset
connect slots_7.io.brupdate.b2.jalr_target, issue_slots[7].brupdate.b2.jalr_target
connect slots_7.io.brupdate.b2.pc_sel, issue_slots[7].brupdate.b2.pc_sel
connect slots_7.io.brupdate.b2.cfi_type, issue_slots[7].brupdate.b2.cfi_type
connect slots_7.io.brupdate.b2.taken, issue_slots[7].brupdate.b2.taken
connect slots_7.io.brupdate.b2.mispredict, issue_slots[7].brupdate.b2.mispredict
connect slots_7.io.brupdate.b2.uop.debug_tsrc, issue_slots[7].brupdate.b2.uop.debug_tsrc
connect slots_7.io.brupdate.b2.uop.debug_fsrc, issue_slots[7].brupdate.b2.uop.debug_fsrc
connect slots_7.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[7].brupdate.b2.uop.bp_xcpt_if
connect slots_7.io.brupdate.b2.uop.bp_debug_if, issue_slots[7].brupdate.b2.uop.bp_debug_if
connect slots_7.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[7].brupdate.b2.uop.xcpt_ma_if
connect slots_7.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[7].brupdate.b2.uop.xcpt_ae_if
connect slots_7.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[7].brupdate.b2.uop.xcpt_pf_if
connect slots_7.io.brupdate.b2.uop.fp_typ, issue_slots[7].brupdate.b2.uop.fp_typ
connect slots_7.io.brupdate.b2.uop.fp_rm, issue_slots[7].brupdate.b2.uop.fp_rm
connect slots_7.io.brupdate.b2.uop.fp_val, issue_slots[7].brupdate.b2.uop.fp_val
connect slots_7.io.brupdate.b2.uop.fcn_op, issue_slots[7].brupdate.b2.uop.fcn_op
connect slots_7.io.brupdate.b2.uop.fcn_dw, issue_slots[7].brupdate.b2.uop.fcn_dw
connect slots_7.io.brupdate.b2.uop.frs3_en, issue_slots[7].brupdate.b2.uop.frs3_en
connect slots_7.io.brupdate.b2.uop.lrs2_rtype, issue_slots[7].brupdate.b2.uop.lrs2_rtype
connect slots_7.io.brupdate.b2.uop.lrs1_rtype, issue_slots[7].brupdate.b2.uop.lrs1_rtype
connect slots_7.io.brupdate.b2.uop.dst_rtype, issue_slots[7].brupdate.b2.uop.dst_rtype
connect slots_7.io.brupdate.b2.uop.lrs3, issue_slots[7].brupdate.b2.uop.lrs3
connect slots_7.io.brupdate.b2.uop.lrs2, issue_slots[7].brupdate.b2.uop.lrs2
connect slots_7.io.brupdate.b2.uop.lrs1, issue_slots[7].brupdate.b2.uop.lrs1
connect slots_7.io.brupdate.b2.uop.ldst, issue_slots[7].brupdate.b2.uop.ldst
connect slots_7.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[7].brupdate.b2.uop.ldst_is_rs1
connect slots_7.io.brupdate.b2.uop.csr_cmd, issue_slots[7].brupdate.b2.uop.csr_cmd
connect slots_7.io.brupdate.b2.uop.flush_on_commit, issue_slots[7].brupdate.b2.uop.flush_on_commit
connect slots_7.io.brupdate.b2.uop.is_unique, issue_slots[7].brupdate.b2.uop.is_unique
connect slots_7.io.brupdate.b2.uop.uses_stq, issue_slots[7].brupdate.b2.uop.uses_stq
connect slots_7.io.brupdate.b2.uop.uses_ldq, issue_slots[7].brupdate.b2.uop.uses_ldq
connect slots_7.io.brupdate.b2.uop.mem_signed, issue_slots[7].brupdate.b2.uop.mem_signed
connect slots_7.io.brupdate.b2.uop.mem_size, issue_slots[7].brupdate.b2.uop.mem_size
connect slots_7.io.brupdate.b2.uop.mem_cmd, issue_slots[7].brupdate.b2.uop.mem_cmd
connect slots_7.io.brupdate.b2.uop.exc_cause, issue_slots[7].brupdate.b2.uop.exc_cause
connect slots_7.io.brupdate.b2.uop.exception, issue_slots[7].brupdate.b2.uop.exception
connect slots_7.io.brupdate.b2.uop.stale_pdst, issue_slots[7].brupdate.b2.uop.stale_pdst
connect slots_7.io.brupdate.b2.uop.ppred_busy, issue_slots[7].brupdate.b2.uop.ppred_busy
connect slots_7.io.brupdate.b2.uop.prs3_busy, issue_slots[7].brupdate.b2.uop.prs3_busy
connect slots_7.io.brupdate.b2.uop.prs2_busy, issue_slots[7].brupdate.b2.uop.prs2_busy
connect slots_7.io.brupdate.b2.uop.prs1_busy, issue_slots[7].brupdate.b2.uop.prs1_busy
connect slots_7.io.brupdate.b2.uop.ppred, issue_slots[7].brupdate.b2.uop.ppred
connect slots_7.io.brupdate.b2.uop.prs3, issue_slots[7].brupdate.b2.uop.prs3
connect slots_7.io.brupdate.b2.uop.prs2, issue_slots[7].brupdate.b2.uop.prs2
connect slots_7.io.brupdate.b2.uop.prs1, issue_slots[7].brupdate.b2.uop.prs1
connect slots_7.io.brupdate.b2.uop.pdst, issue_slots[7].brupdate.b2.uop.pdst
connect slots_7.io.brupdate.b2.uop.rxq_idx, issue_slots[7].brupdate.b2.uop.rxq_idx
connect slots_7.io.brupdate.b2.uop.stq_idx, issue_slots[7].brupdate.b2.uop.stq_idx
connect slots_7.io.brupdate.b2.uop.ldq_idx, issue_slots[7].brupdate.b2.uop.ldq_idx
connect slots_7.io.brupdate.b2.uop.rob_idx, issue_slots[7].brupdate.b2.uop.rob_idx
connect slots_7.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[7].brupdate.b2.uop.fp_ctrl.vec
connect slots_7.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[7].brupdate.b2.uop.fp_ctrl.wflags
connect slots_7.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[7].brupdate.b2.uop.fp_ctrl.sqrt
connect slots_7.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[7].brupdate.b2.uop.fp_ctrl.div
connect slots_7.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[7].brupdate.b2.uop.fp_ctrl.fma
connect slots_7.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[7].brupdate.b2.uop.fp_ctrl.fastpipe
connect slots_7.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[7].brupdate.b2.uop.fp_ctrl.toint
connect slots_7.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[7].brupdate.b2.uop.fp_ctrl.fromint
connect slots_7.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[7].brupdate.b2.uop.fp_ctrl.typeTagOut
connect slots_7.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[7].brupdate.b2.uop.fp_ctrl.typeTagIn
connect slots_7.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[7].brupdate.b2.uop.fp_ctrl.swap23
connect slots_7.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[7].brupdate.b2.uop.fp_ctrl.swap12
connect slots_7.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[7].brupdate.b2.uop.fp_ctrl.ren3
connect slots_7.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[7].brupdate.b2.uop.fp_ctrl.ren2
connect slots_7.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[7].brupdate.b2.uop.fp_ctrl.ren1
connect slots_7.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[7].brupdate.b2.uop.fp_ctrl.wen
connect slots_7.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[7].brupdate.b2.uop.fp_ctrl.ldst
connect slots_7.io.brupdate.b2.uop.op2_sel, issue_slots[7].brupdate.b2.uop.op2_sel
connect slots_7.io.brupdate.b2.uop.op1_sel, issue_slots[7].brupdate.b2.uop.op1_sel
connect slots_7.io.brupdate.b2.uop.imm_packed, issue_slots[7].brupdate.b2.uop.imm_packed
connect slots_7.io.brupdate.b2.uop.pimm, issue_slots[7].brupdate.b2.uop.pimm
connect slots_7.io.brupdate.b2.uop.imm_sel, issue_slots[7].brupdate.b2.uop.imm_sel
connect slots_7.io.brupdate.b2.uop.imm_rename, issue_slots[7].brupdate.b2.uop.imm_rename
connect slots_7.io.brupdate.b2.uop.taken, issue_slots[7].brupdate.b2.uop.taken
connect slots_7.io.brupdate.b2.uop.pc_lob, issue_slots[7].brupdate.b2.uop.pc_lob
connect slots_7.io.brupdate.b2.uop.edge_inst, issue_slots[7].brupdate.b2.uop.edge_inst
connect slots_7.io.brupdate.b2.uop.ftq_idx, issue_slots[7].brupdate.b2.uop.ftq_idx
connect slots_7.io.brupdate.b2.uop.is_mov, issue_slots[7].brupdate.b2.uop.is_mov
connect slots_7.io.brupdate.b2.uop.is_rocc, issue_slots[7].brupdate.b2.uop.is_rocc
connect slots_7.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[7].brupdate.b2.uop.is_sys_pc2epc
connect slots_7.io.brupdate.b2.uop.is_eret, issue_slots[7].brupdate.b2.uop.is_eret
connect slots_7.io.brupdate.b2.uop.is_amo, issue_slots[7].brupdate.b2.uop.is_amo
connect slots_7.io.brupdate.b2.uop.is_sfence, issue_slots[7].brupdate.b2.uop.is_sfence
connect slots_7.io.brupdate.b2.uop.is_fencei, issue_slots[7].brupdate.b2.uop.is_fencei
connect slots_7.io.brupdate.b2.uop.is_fence, issue_slots[7].brupdate.b2.uop.is_fence
connect slots_7.io.brupdate.b2.uop.is_sfb, issue_slots[7].brupdate.b2.uop.is_sfb
connect slots_7.io.brupdate.b2.uop.br_type, issue_slots[7].brupdate.b2.uop.br_type
connect slots_7.io.brupdate.b2.uop.br_tag, issue_slots[7].brupdate.b2.uop.br_tag
connect slots_7.io.brupdate.b2.uop.br_mask, issue_slots[7].brupdate.b2.uop.br_mask
connect slots_7.io.brupdate.b2.uop.dis_col_sel, issue_slots[7].brupdate.b2.uop.dis_col_sel
connect slots_7.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[7].brupdate.b2.uop.iw_p3_bypass_hint
connect slots_7.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[7].brupdate.b2.uop.iw_p2_bypass_hint
connect slots_7.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[7].brupdate.b2.uop.iw_p1_bypass_hint
connect slots_7.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[7].brupdate.b2.uop.iw_p2_speculative_child
connect slots_7.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[7].brupdate.b2.uop.iw_p1_speculative_child
connect slots_7.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[7].brupdate.b2.uop.iw_issued_partial_dgen
connect slots_7.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[7].brupdate.b2.uop.iw_issued_partial_agen
connect slots_7.io.brupdate.b2.uop.iw_issued, issue_slots[7].brupdate.b2.uop.iw_issued
connect slots_7.io.brupdate.b2.uop.fu_code[0], issue_slots[7].brupdate.b2.uop.fu_code[0]
connect slots_7.io.brupdate.b2.uop.fu_code[1], issue_slots[7].brupdate.b2.uop.fu_code[1]
connect slots_7.io.brupdate.b2.uop.fu_code[2], issue_slots[7].brupdate.b2.uop.fu_code[2]
connect slots_7.io.brupdate.b2.uop.fu_code[3], issue_slots[7].brupdate.b2.uop.fu_code[3]
connect slots_7.io.brupdate.b2.uop.fu_code[4], issue_slots[7].brupdate.b2.uop.fu_code[4]
connect slots_7.io.brupdate.b2.uop.fu_code[5], issue_slots[7].brupdate.b2.uop.fu_code[5]
connect slots_7.io.brupdate.b2.uop.fu_code[6], issue_slots[7].brupdate.b2.uop.fu_code[6]
connect slots_7.io.brupdate.b2.uop.fu_code[7], issue_slots[7].brupdate.b2.uop.fu_code[7]
connect slots_7.io.brupdate.b2.uop.fu_code[8], issue_slots[7].brupdate.b2.uop.fu_code[8]
connect slots_7.io.brupdate.b2.uop.fu_code[9], issue_slots[7].brupdate.b2.uop.fu_code[9]
connect slots_7.io.brupdate.b2.uop.iq_type[0], issue_slots[7].brupdate.b2.uop.iq_type[0]
connect slots_7.io.brupdate.b2.uop.iq_type[1], issue_slots[7].brupdate.b2.uop.iq_type[1]
connect slots_7.io.brupdate.b2.uop.iq_type[2], issue_slots[7].brupdate.b2.uop.iq_type[2]
connect slots_7.io.brupdate.b2.uop.iq_type[3], issue_slots[7].brupdate.b2.uop.iq_type[3]
connect slots_7.io.brupdate.b2.uop.debug_pc, issue_slots[7].brupdate.b2.uop.debug_pc
connect slots_7.io.brupdate.b2.uop.is_rvc, issue_slots[7].brupdate.b2.uop.is_rvc
connect slots_7.io.brupdate.b2.uop.debug_inst, issue_slots[7].brupdate.b2.uop.debug_inst
connect slots_7.io.brupdate.b2.uop.inst, issue_slots[7].brupdate.b2.uop.inst
connect slots_7.io.brupdate.b1.mispredict_mask, issue_slots[7].brupdate.b1.mispredict_mask
connect slots_7.io.brupdate.b1.resolve_mask, issue_slots[7].brupdate.b1.resolve_mask
connect issue_slots[7].out_uop.debug_tsrc, slots_7.io.out_uop.debug_tsrc
connect issue_slots[7].out_uop.debug_fsrc, slots_7.io.out_uop.debug_fsrc
connect issue_slots[7].out_uop.bp_xcpt_if, slots_7.io.out_uop.bp_xcpt_if
connect issue_slots[7].out_uop.bp_debug_if, slots_7.io.out_uop.bp_debug_if
connect issue_slots[7].out_uop.xcpt_ma_if, slots_7.io.out_uop.xcpt_ma_if
connect issue_slots[7].out_uop.xcpt_ae_if, slots_7.io.out_uop.xcpt_ae_if
connect issue_slots[7].out_uop.xcpt_pf_if, slots_7.io.out_uop.xcpt_pf_if
connect issue_slots[7].out_uop.fp_typ, slots_7.io.out_uop.fp_typ
connect issue_slots[7].out_uop.fp_rm, slots_7.io.out_uop.fp_rm
connect issue_slots[7].out_uop.fp_val, slots_7.io.out_uop.fp_val
connect issue_slots[7].out_uop.fcn_op, slots_7.io.out_uop.fcn_op
connect issue_slots[7].out_uop.fcn_dw, slots_7.io.out_uop.fcn_dw
connect issue_slots[7].out_uop.frs3_en, slots_7.io.out_uop.frs3_en
connect issue_slots[7].out_uop.lrs2_rtype, slots_7.io.out_uop.lrs2_rtype
connect issue_slots[7].out_uop.lrs1_rtype, slots_7.io.out_uop.lrs1_rtype
connect issue_slots[7].out_uop.dst_rtype, slots_7.io.out_uop.dst_rtype
connect issue_slots[7].out_uop.lrs3, slots_7.io.out_uop.lrs3
connect issue_slots[7].out_uop.lrs2, slots_7.io.out_uop.lrs2
connect issue_slots[7].out_uop.lrs1, slots_7.io.out_uop.lrs1
connect issue_slots[7].out_uop.ldst, slots_7.io.out_uop.ldst
connect issue_slots[7].out_uop.ldst_is_rs1, slots_7.io.out_uop.ldst_is_rs1
connect issue_slots[7].out_uop.csr_cmd, slots_7.io.out_uop.csr_cmd
connect issue_slots[7].out_uop.flush_on_commit, slots_7.io.out_uop.flush_on_commit
connect issue_slots[7].out_uop.is_unique, slots_7.io.out_uop.is_unique
connect issue_slots[7].out_uop.uses_stq, slots_7.io.out_uop.uses_stq
connect issue_slots[7].out_uop.uses_ldq, slots_7.io.out_uop.uses_ldq
connect issue_slots[7].out_uop.mem_signed, slots_7.io.out_uop.mem_signed
connect issue_slots[7].out_uop.mem_size, slots_7.io.out_uop.mem_size
connect issue_slots[7].out_uop.mem_cmd, slots_7.io.out_uop.mem_cmd
connect issue_slots[7].out_uop.exc_cause, slots_7.io.out_uop.exc_cause
connect issue_slots[7].out_uop.exception, slots_7.io.out_uop.exception
connect issue_slots[7].out_uop.stale_pdst, slots_7.io.out_uop.stale_pdst
connect issue_slots[7].out_uop.ppred_busy, slots_7.io.out_uop.ppred_busy
connect issue_slots[7].out_uop.prs3_busy, slots_7.io.out_uop.prs3_busy
connect issue_slots[7].out_uop.prs2_busy, slots_7.io.out_uop.prs2_busy
connect issue_slots[7].out_uop.prs1_busy, slots_7.io.out_uop.prs1_busy
connect issue_slots[7].out_uop.ppred, slots_7.io.out_uop.ppred
connect issue_slots[7].out_uop.prs3, slots_7.io.out_uop.prs3
connect issue_slots[7].out_uop.prs2, slots_7.io.out_uop.prs2
connect issue_slots[7].out_uop.prs1, slots_7.io.out_uop.prs1
connect issue_slots[7].out_uop.pdst, slots_7.io.out_uop.pdst
connect issue_slots[7].out_uop.rxq_idx, slots_7.io.out_uop.rxq_idx
connect issue_slots[7].out_uop.stq_idx, slots_7.io.out_uop.stq_idx
connect issue_slots[7].out_uop.ldq_idx, slots_7.io.out_uop.ldq_idx
connect issue_slots[7].out_uop.rob_idx, slots_7.io.out_uop.rob_idx
connect issue_slots[7].out_uop.fp_ctrl.vec, slots_7.io.out_uop.fp_ctrl.vec
connect issue_slots[7].out_uop.fp_ctrl.wflags, slots_7.io.out_uop.fp_ctrl.wflags
connect issue_slots[7].out_uop.fp_ctrl.sqrt, slots_7.io.out_uop.fp_ctrl.sqrt
connect issue_slots[7].out_uop.fp_ctrl.div, slots_7.io.out_uop.fp_ctrl.div
connect issue_slots[7].out_uop.fp_ctrl.fma, slots_7.io.out_uop.fp_ctrl.fma
connect issue_slots[7].out_uop.fp_ctrl.fastpipe, slots_7.io.out_uop.fp_ctrl.fastpipe
connect issue_slots[7].out_uop.fp_ctrl.toint, slots_7.io.out_uop.fp_ctrl.toint
connect issue_slots[7].out_uop.fp_ctrl.fromint, slots_7.io.out_uop.fp_ctrl.fromint
connect issue_slots[7].out_uop.fp_ctrl.typeTagOut, slots_7.io.out_uop.fp_ctrl.typeTagOut
connect issue_slots[7].out_uop.fp_ctrl.typeTagIn, slots_7.io.out_uop.fp_ctrl.typeTagIn
connect issue_slots[7].out_uop.fp_ctrl.swap23, slots_7.io.out_uop.fp_ctrl.swap23
connect issue_slots[7].out_uop.fp_ctrl.swap12, slots_7.io.out_uop.fp_ctrl.swap12
connect issue_slots[7].out_uop.fp_ctrl.ren3, slots_7.io.out_uop.fp_ctrl.ren3
connect issue_slots[7].out_uop.fp_ctrl.ren2, slots_7.io.out_uop.fp_ctrl.ren2
connect issue_slots[7].out_uop.fp_ctrl.ren1, slots_7.io.out_uop.fp_ctrl.ren1
connect issue_slots[7].out_uop.fp_ctrl.wen, slots_7.io.out_uop.fp_ctrl.wen
connect issue_slots[7].out_uop.fp_ctrl.ldst, slots_7.io.out_uop.fp_ctrl.ldst
connect issue_slots[7].out_uop.op2_sel, slots_7.io.out_uop.op2_sel
connect issue_slots[7].out_uop.op1_sel, slots_7.io.out_uop.op1_sel
connect issue_slots[7].out_uop.imm_packed, slots_7.io.out_uop.imm_packed
connect issue_slots[7].out_uop.pimm, slots_7.io.out_uop.pimm
connect issue_slots[7].out_uop.imm_sel, slots_7.io.out_uop.imm_sel
connect issue_slots[7].out_uop.imm_rename, slots_7.io.out_uop.imm_rename
connect issue_slots[7].out_uop.taken, slots_7.io.out_uop.taken
connect issue_slots[7].out_uop.pc_lob, slots_7.io.out_uop.pc_lob
connect issue_slots[7].out_uop.edge_inst, slots_7.io.out_uop.edge_inst
connect issue_slots[7].out_uop.ftq_idx, slots_7.io.out_uop.ftq_idx
connect issue_slots[7].out_uop.is_mov, slots_7.io.out_uop.is_mov
connect issue_slots[7].out_uop.is_rocc, slots_7.io.out_uop.is_rocc
connect issue_slots[7].out_uop.is_sys_pc2epc, slots_7.io.out_uop.is_sys_pc2epc
connect issue_slots[7].out_uop.is_eret, slots_7.io.out_uop.is_eret
connect issue_slots[7].out_uop.is_amo, slots_7.io.out_uop.is_amo
connect issue_slots[7].out_uop.is_sfence, slots_7.io.out_uop.is_sfence
connect issue_slots[7].out_uop.is_fencei, slots_7.io.out_uop.is_fencei
connect issue_slots[7].out_uop.is_fence, slots_7.io.out_uop.is_fence
connect issue_slots[7].out_uop.is_sfb, slots_7.io.out_uop.is_sfb
connect issue_slots[7].out_uop.br_type, slots_7.io.out_uop.br_type
connect issue_slots[7].out_uop.br_tag, slots_7.io.out_uop.br_tag
connect issue_slots[7].out_uop.br_mask, slots_7.io.out_uop.br_mask
connect issue_slots[7].out_uop.dis_col_sel, slots_7.io.out_uop.dis_col_sel
connect issue_slots[7].out_uop.iw_p3_bypass_hint, slots_7.io.out_uop.iw_p3_bypass_hint
connect issue_slots[7].out_uop.iw_p2_bypass_hint, slots_7.io.out_uop.iw_p2_bypass_hint
connect issue_slots[7].out_uop.iw_p1_bypass_hint, slots_7.io.out_uop.iw_p1_bypass_hint
connect issue_slots[7].out_uop.iw_p2_speculative_child, slots_7.io.out_uop.iw_p2_speculative_child
connect issue_slots[7].out_uop.iw_p1_speculative_child, slots_7.io.out_uop.iw_p1_speculative_child
connect issue_slots[7].out_uop.iw_issued_partial_dgen, slots_7.io.out_uop.iw_issued_partial_dgen
connect issue_slots[7].out_uop.iw_issued_partial_agen, slots_7.io.out_uop.iw_issued_partial_agen
connect issue_slots[7].out_uop.iw_issued, slots_7.io.out_uop.iw_issued
connect issue_slots[7].out_uop.fu_code[0], slots_7.io.out_uop.fu_code[0]
connect issue_slots[7].out_uop.fu_code[1], slots_7.io.out_uop.fu_code[1]
connect issue_slots[7].out_uop.fu_code[2], slots_7.io.out_uop.fu_code[2]
connect issue_slots[7].out_uop.fu_code[3], slots_7.io.out_uop.fu_code[3]
connect issue_slots[7].out_uop.fu_code[4], slots_7.io.out_uop.fu_code[4]
connect issue_slots[7].out_uop.fu_code[5], slots_7.io.out_uop.fu_code[5]
connect issue_slots[7].out_uop.fu_code[6], slots_7.io.out_uop.fu_code[6]
connect issue_slots[7].out_uop.fu_code[7], slots_7.io.out_uop.fu_code[7]
connect issue_slots[7].out_uop.fu_code[8], slots_7.io.out_uop.fu_code[8]
connect issue_slots[7].out_uop.fu_code[9], slots_7.io.out_uop.fu_code[9]
connect issue_slots[7].out_uop.iq_type[0], slots_7.io.out_uop.iq_type[0]
connect issue_slots[7].out_uop.iq_type[1], slots_7.io.out_uop.iq_type[1]
connect issue_slots[7].out_uop.iq_type[2], slots_7.io.out_uop.iq_type[2]
connect issue_slots[7].out_uop.iq_type[3], slots_7.io.out_uop.iq_type[3]
connect issue_slots[7].out_uop.debug_pc, slots_7.io.out_uop.debug_pc
connect issue_slots[7].out_uop.is_rvc, slots_7.io.out_uop.is_rvc
connect issue_slots[7].out_uop.debug_inst, slots_7.io.out_uop.debug_inst
connect issue_slots[7].out_uop.inst, slots_7.io.out_uop.inst
connect slots_7.io.in_uop.bits.debug_tsrc, issue_slots[7].in_uop.bits.debug_tsrc
connect slots_7.io.in_uop.bits.debug_fsrc, issue_slots[7].in_uop.bits.debug_fsrc
connect slots_7.io.in_uop.bits.bp_xcpt_if, issue_slots[7].in_uop.bits.bp_xcpt_if
connect slots_7.io.in_uop.bits.bp_debug_if, issue_slots[7].in_uop.bits.bp_debug_if
connect slots_7.io.in_uop.bits.xcpt_ma_if, issue_slots[7].in_uop.bits.xcpt_ma_if
connect slots_7.io.in_uop.bits.xcpt_ae_if, issue_slots[7].in_uop.bits.xcpt_ae_if
connect slots_7.io.in_uop.bits.xcpt_pf_if, issue_slots[7].in_uop.bits.xcpt_pf_if
connect slots_7.io.in_uop.bits.fp_typ, issue_slots[7].in_uop.bits.fp_typ
connect slots_7.io.in_uop.bits.fp_rm, issue_slots[7].in_uop.bits.fp_rm
connect slots_7.io.in_uop.bits.fp_val, issue_slots[7].in_uop.bits.fp_val
connect slots_7.io.in_uop.bits.fcn_op, issue_slots[7].in_uop.bits.fcn_op
connect slots_7.io.in_uop.bits.fcn_dw, issue_slots[7].in_uop.bits.fcn_dw
connect slots_7.io.in_uop.bits.frs3_en, issue_slots[7].in_uop.bits.frs3_en
connect slots_7.io.in_uop.bits.lrs2_rtype, issue_slots[7].in_uop.bits.lrs2_rtype
connect slots_7.io.in_uop.bits.lrs1_rtype, issue_slots[7].in_uop.bits.lrs1_rtype
connect slots_7.io.in_uop.bits.dst_rtype, issue_slots[7].in_uop.bits.dst_rtype
connect slots_7.io.in_uop.bits.lrs3, issue_slots[7].in_uop.bits.lrs3
connect slots_7.io.in_uop.bits.lrs2, issue_slots[7].in_uop.bits.lrs2
connect slots_7.io.in_uop.bits.lrs1, issue_slots[7].in_uop.bits.lrs1
connect slots_7.io.in_uop.bits.ldst, issue_slots[7].in_uop.bits.ldst
connect slots_7.io.in_uop.bits.ldst_is_rs1, issue_slots[7].in_uop.bits.ldst_is_rs1
connect slots_7.io.in_uop.bits.csr_cmd, issue_slots[7].in_uop.bits.csr_cmd
connect slots_7.io.in_uop.bits.flush_on_commit, issue_slots[7].in_uop.bits.flush_on_commit
connect slots_7.io.in_uop.bits.is_unique, issue_slots[7].in_uop.bits.is_unique
connect slots_7.io.in_uop.bits.uses_stq, issue_slots[7].in_uop.bits.uses_stq
connect slots_7.io.in_uop.bits.uses_ldq, issue_slots[7].in_uop.bits.uses_ldq
connect slots_7.io.in_uop.bits.mem_signed, issue_slots[7].in_uop.bits.mem_signed
connect slots_7.io.in_uop.bits.mem_size, issue_slots[7].in_uop.bits.mem_size
connect slots_7.io.in_uop.bits.mem_cmd, issue_slots[7].in_uop.bits.mem_cmd
connect slots_7.io.in_uop.bits.exc_cause, issue_slots[7].in_uop.bits.exc_cause
connect slots_7.io.in_uop.bits.exception, issue_slots[7].in_uop.bits.exception
connect slots_7.io.in_uop.bits.stale_pdst, issue_slots[7].in_uop.bits.stale_pdst
connect slots_7.io.in_uop.bits.ppred_busy, issue_slots[7].in_uop.bits.ppred_busy
connect slots_7.io.in_uop.bits.prs3_busy, issue_slots[7].in_uop.bits.prs3_busy
connect slots_7.io.in_uop.bits.prs2_busy, issue_slots[7].in_uop.bits.prs2_busy
connect slots_7.io.in_uop.bits.prs1_busy, issue_slots[7].in_uop.bits.prs1_busy
connect slots_7.io.in_uop.bits.ppred, issue_slots[7].in_uop.bits.ppred
connect slots_7.io.in_uop.bits.prs3, issue_slots[7].in_uop.bits.prs3
connect slots_7.io.in_uop.bits.prs2, issue_slots[7].in_uop.bits.prs2
connect slots_7.io.in_uop.bits.prs1, issue_slots[7].in_uop.bits.prs1
connect slots_7.io.in_uop.bits.pdst, issue_slots[7].in_uop.bits.pdst
connect slots_7.io.in_uop.bits.rxq_idx, issue_slots[7].in_uop.bits.rxq_idx
connect slots_7.io.in_uop.bits.stq_idx, issue_slots[7].in_uop.bits.stq_idx
connect slots_7.io.in_uop.bits.ldq_idx, issue_slots[7].in_uop.bits.ldq_idx
connect slots_7.io.in_uop.bits.rob_idx, issue_slots[7].in_uop.bits.rob_idx
connect slots_7.io.in_uop.bits.fp_ctrl.vec, issue_slots[7].in_uop.bits.fp_ctrl.vec
connect slots_7.io.in_uop.bits.fp_ctrl.wflags, issue_slots[7].in_uop.bits.fp_ctrl.wflags
connect slots_7.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[7].in_uop.bits.fp_ctrl.sqrt
connect slots_7.io.in_uop.bits.fp_ctrl.div, issue_slots[7].in_uop.bits.fp_ctrl.div
connect slots_7.io.in_uop.bits.fp_ctrl.fma, issue_slots[7].in_uop.bits.fp_ctrl.fma
connect slots_7.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[7].in_uop.bits.fp_ctrl.fastpipe
connect slots_7.io.in_uop.bits.fp_ctrl.toint, issue_slots[7].in_uop.bits.fp_ctrl.toint
connect slots_7.io.in_uop.bits.fp_ctrl.fromint, issue_slots[7].in_uop.bits.fp_ctrl.fromint
connect slots_7.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[7].in_uop.bits.fp_ctrl.typeTagOut
connect slots_7.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[7].in_uop.bits.fp_ctrl.typeTagIn
connect slots_7.io.in_uop.bits.fp_ctrl.swap23, issue_slots[7].in_uop.bits.fp_ctrl.swap23
connect slots_7.io.in_uop.bits.fp_ctrl.swap12, issue_slots[7].in_uop.bits.fp_ctrl.swap12
connect slots_7.io.in_uop.bits.fp_ctrl.ren3, issue_slots[7].in_uop.bits.fp_ctrl.ren3
connect slots_7.io.in_uop.bits.fp_ctrl.ren2, issue_slots[7].in_uop.bits.fp_ctrl.ren2
connect slots_7.io.in_uop.bits.fp_ctrl.ren1, issue_slots[7].in_uop.bits.fp_ctrl.ren1
connect slots_7.io.in_uop.bits.fp_ctrl.wen, issue_slots[7].in_uop.bits.fp_ctrl.wen
connect slots_7.io.in_uop.bits.fp_ctrl.ldst, issue_slots[7].in_uop.bits.fp_ctrl.ldst
connect slots_7.io.in_uop.bits.op2_sel, issue_slots[7].in_uop.bits.op2_sel
connect slots_7.io.in_uop.bits.op1_sel, issue_slots[7].in_uop.bits.op1_sel
connect slots_7.io.in_uop.bits.imm_packed, issue_slots[7].in_uop.bits.imm_packed
connect slots_7.io.in_uop.bits.pimm, issue_slots[7].in_uop.bits.pimm
connect slots_7.io.in_uop.bits.imm_sel, issue_slots[7].in_uop.bits.imm_sel
connect slots_7.io.in_uop.bits.imm_rename, issue_slots[7].in_uop.bits.imm_rename
connect slots_7.io.in_uop.bits.taken, issue_slots[7].in_uop.bits.taken
connect slots_7.io.in_uop.bits.pc_lob, issue_slots[7].in_uop.bits.pc_lob
connect slots_7.io.in_uop.bits.edge_inst, issue_slots[7].in_uop.bits.edge_inst
connect slots_7.io.in_uop.bits.ftq_idx, issue_slots[7].in_uop.bits.ftq_idx
connect slots_7.io.in_uop.bits.is_mov, issue_slots[7].in_uop.bits.is_mov
connect slots_7.io.in_uop.bits.is_rocc, issue_slots[7].in_uop.bits.is_rocc
connect slots_7.io.in_uop.bits.is_sys_pc2epc, issue_slots[7].in_uop.bits.is_sys_pc2epc
connect slots_7.io.in_uop.bits.is_eret, issue_slots[7].in_uop.bits.is_eret
connect slots_7.io.in_uop.bits.is_amo, issue_slots[7].in_uop.bits.is_amo
connect slots_7.io.in_uop.bits.is_sfence, issue_slots[7].in_uop.bits.is_sfence
connect slots_7.io.in_uop.bits.is_fencei, issue_slots[7].in_uop.bits.is_fencei
connect slots_7.io.in_uop.bits.is_fence, issue_slots[7].in_uop.bits.is_fence
connect slots_7.io.in_uop.bits.is_sfb, issue_slots[7].in_uop.bits.is_sfb
connect slots_7.io.in_uop.bits.br_type, issue_slots[7].in_uop.bits.br_type
connect slots_7.io.in_uop.bits.br_tag, issue_slots[7].in_uop.bits.br_tag
connect slots_7.io.in_uop.bits.br_mask, issue_slots[7].in_uop.bits.br_mask
connect slots_7.io.in_uop.bits.dis_col_sel, issue_slots[7].in_uop.bits.dis_col_sel
connect slots_7.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[7].in_uop.bits.iw_p3_bypass_hint
connect slots_7.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[7].in_uop.bits.iw_p2_bypass_hint
connect slots_7.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[7].in_uop.bits.iw_p1_bypass_hint
connect slots_7.io.in_uop.bits.iw_p2_speculative_child, issue_slots[7].in_uop.bits.iw_p2_speculative_child
connect slots_7.io.in_uop.bits.iw_p1_speculative_child, issue_slots[7].in_uop.bits.iw_p1_speculative_child
connect slots_7.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[7].in_uop.bits.iw_issued_partial_dgen
connect slots_7.io.in_uop.bits.iw_issued_partial_agen, issue_slots[7].in_uop.bits.iw_issued_partial_agen
connect slots_7.io.in_uop.bits.iw_issued, issue_slots[7].in_uop.bits.iw_issued
connect slots_7.io.in_uop.bits.fu_code[0], issue_slots[7].in_uop.bits.fu_code[0]
connect slots_7.io.in_uop.bits.fu_code[1], issue_slots[7].in_uop.bits.fu_code[1]
connect slots_7.io.in_uop.bits.fu_code[2], issue_slots[7].in_uop.bits.fu_code[2]
connect slots_7.io.in_uop.bits.fu_code[3], issue_slots[7].in_uop.bits.fu_code[3]
connect slots_7.io.in_uop.bits.fu_code[4], issue_slots[7].in_uop.bits.fu_code[4]
connect slots_7.io.in_uop.bits.fu_code[5], issue_slots[7].in_uop.bits.fu_code[5]
connect slots_7.io.in_uop.bits.fu_code[6], issue_slots[7].in_uop.bits.fu_code[6]
connect slots_7.io.in_uop.bits.fu_code[7], issue_slots[7].in_uop.bits.fu_code[7]
connect slots_7.io.in_uop.bits.fu_code[8], issue_slots[7].in_uop.bits.fu_code[8]
connect slots_7.io.in_uop.bits.fu_code[9], issue_slots[7].in_uop.bits.fu_code[9]
connect slots_7.io.in_uop.bits.iq_type[0], issue_slots[7].in_uop.bits.iq_type[0]
connect slots_7.io.in_uop.bits.iq_type[1], issue_slots[7].in_uop.bits.iq_type[1]
connect slots_7.io.in_uop.bits.iq_type[2], issue_slots[7].in_uop.bits.iq_type[2]
connect slots_7.io.in_uop.bits.iq_type[3], issue_slots[7].in_uop.bits.iq_type[3]
connect slots_7.io.in_uop.bits.debug_pc, issue_slots[7].in_uop.bits.debug_pc
connect slots_7.io.in_uop.bits.is_rvc, issue_slots[7].in_uop.bits.is_rvc
connect slots_7.io.in_uop.bits.debug_inst, issue_slots[7].in_uop.bits.debug_inst
connect slots_7.io.in_uop.bits.inst, issue_slots[7].in_uop.bits.inst
connect slots_7.io.in_uop.valid, issue_slots[7].in_uop.valid
connect issue_slots[7].iss_uop.debug_tsrc, slots_7.io.iss_uop.debug_tsrc
connect issue_slots[7].iss_uop.debug_fsrc, slots_7.io.iss_uop.debug_fsrc
connect issue_slots[7].iss_uop.bp_xcpt_if, slots_7.io.iss_uop.bp_xcpt_if
connect issue_slots[7].iss_uop.bp_debug_if, slots_7.io.iss_uop.bp_debug_if
connect issue_slots[7].iss_uop.xcpt_ma_if, slots_7.io.iss_uop.xcpt_ma_if
connect issue_slots[7].iss_uop.xcpt_ae_if, slots_7.io.iss_uop.xcpt_ae_if
connect issue_slots[7].iss_uop.xcpt_pf_if, slots_7.io.iss_uop.xcpt_pf_if
connect issue_slots[7].iss_uop.fp_typ, slots_7.io.iss_uop.fp_typ
connect issue_slots[7].iss_uop.fp_rm, slots_7.io.iss_uop.fp_rm
connect issue_slots[7].iss_uop.fp_val, slots_7.io.iss_uop.fp_val
connect issue_slots[7].iss_uop.fcn_op, slots_7.io.iss_uop.fcn_op
connect issue_slots[7].iss_uop.fcn_dw, slots_7.io.iss_uop.fcn_dw
connect issue_slots[7].iss_uop.frs3_en, slots_7.io.iss_uop.frs3_en
connect issue_slots[7].iss_uop.lrs2_rtype, slots_7.io.iss_uop.lrs2_rtype
connect issue_slots[7].iss_uop.lrs1_rtype, slots_7.io.iss_uop.lrs1_rtype
connect issue_slots[7].iss_uop.dst_rtype, slots_7.io.iss_uop.dst_rtype
connect issue_slots[7].iss_uop.lrs3, slots_7.io.iss_uop.lrs3
connect issue_slots[7].iss_uop.lrs2, slots_7.io.iss_uop.lrs2
connect issue_slots[7].iss_uop.lrs1, slots_7.io.iss_uop.lrs1
connect issue_slots[7].iss_uop.ldst, slots_7.io.iss_uop.ldst
connect issue_slots[7].iss_uop.ldst_is_rs1, slots_7.io.iss_uop.ldst_is_rs1
connect issue_slots[7].iss_uop.csr_cmd, slots_7.io.iss_uop.csr_cmd
connect issue_slots[7].iss_uop.flush_on_commit, slots_7.io.iss_uop.flush_on_commit
connect issue_slots[7].iss_uop.is_unique, slots_7.io.iss_uop.is_unique
connect issue_slots[7].iss_uop.uses_stq, slots_7.io.iss_uop.uses_stq
connect issue_slots[7].iss_uop.uses_ldq, slots_7.io.iss_uop.uses_ldq
connect issue_slots[7].iss_uop.mem_signed, slots_7.io.iss_uop.mem_signed
connect issue_slots[7].iss_uop.mem_size, slots_7.io.iss_uop.mem_size
connect issue_slots[7].iss_uop.mem_cmd, slots_7.io.iss_uop.mem_cmd
connect issue_slots[7].iss_uop.exc_cause, slots_7.io.iss_uop.exc_cause
connect issue_slots[7].iss_uop.exception, slots_7.io.iss_uop.exception
connect issue_slots[7].iss_uop.stale_pdst, slots_7.io.iss_uop.stale_pdst
connect issue_slots[7].iss_uop.ppred_busy, slots_7.io.iss_uop.ppred_busy
connect issue_slots[7].iss_uop.prs3_busy, slots_7.io.iss_uop.prs3_busy
connect issue_slots[7].iss_uop.prs2_busy, slots_7.io.iss_uop.prs2_busy
connect issue_slots[7].iss_uop.prs1_busy, slots_7.io.iss_uop.prs1_busy
connect issue_slots[7].iss_uop.ppred, slots_7.io.iss_uop.ppred
connect issue_slots[7].iss_uop.prs3, slots_7.io.iss_uop.prs3
connect issue_slots[7].iss_uop.prs2, slots_7.io.iss_uop.prs2
connect issue_slots[7].iss_uop.prs1, slots_7.io.iss_uop.prs1
connect issue_slots[7].iss_uop.pdst, slots_7.io.iss_uop.pdst
connect issue_slots[7].iss_uop.rxq_idx, slots_7.io.iss_uop.rxq_idx
connect issue_slots[7].iss_uop.stq_idx, slots_7.io.iss_uop.stq_idx
connect issue_slots[7].iss_uop.ldq_idx, slots_7.io.iss_uop.ldq_idx
connect issue_slots[7].iss_uop.rob_idx, slots_7.io.iss_uop.rob_idx
connect issue_slots[7].iss_uop.fp_ctrl.vec, slots_7.io.iss_uop.fp_ctrl.vec
connect issue_slots[7].iss_uop.fp_ctrl.wflags, slots_7.io.iss_uop.fp_ctrl.wflags
connect issue_slots[7].iss_uop.fp_ctrl.sqrt, slots_7.io.iss_uop.fp_ctrl.sqrt
connect issue_slots[7].iss_uop.fp_ctrl.div, slots_7.io.iss_uop.fp_ctrl.div
connect issue_slots[7].iss_uop.fp_ctrl.fma, slots_7.io.iss_uop.fp_ctrl.fma
connect issue_slots[7].iss_uop.fp_ctrl.fastpipe, slots_7.io.iss_uop.fp_ctrl.fastpipe
connect issue_slots[7].iss_uop.fp_ctrl.toint, slots_7.io.iss_uop.fp_ctrl.toint
connect issue_slots[7].iss_uop.fp_ctrl.fromint, slots_7.io.iss_uop.fp_ctrl.fromint
connect issue_slots[7].iss_uop.fp_ctrl.typeTagOut, slots_7.io.iss_uop.fp_ctrl.typeTagOut
connect issue_slots[7].iss_uop.fp_ctrl.typeTagIn, slots_7.io.iss_uop.fp_ctrl.typeTagIn
connect issue_slots[7].iss_uop.fp_ctrl.swap23, slots_7.io.iss_uop.fp_ctrl.swap23
connect issue_slots[7].iss_uop.fp_ctrl.swap12, slots_7.io.iss_uop.fp_ctrl.swap12
connect issue_slots[7].iss_uop.fp_ctrl.ren3, slots_7.io.iss_uop.fp_ctrl.ren3
connect issue_slots[7].iss_uop.fp_ctrl.ren2, slots_7.io.iss_uop.fp_ctrl.ren2
connect issue_slots[7].iss_uop.fp_ctrl.ren1, slots_7.io.iss_uop.fp_ctrl.ren1
connect issue_slots[7].iss_uop.fp_ctrl.wen, slots_7.io.iss_uop.fp_ctrl.wen
connect issue_slots[7].iss_uop.fp_ctrl.ldst, slots_7.io.iss_uop.fp_ctrl.ldst
connect issue_slots[7].iss_uop.op2_sel, slots_7.io.iss_uop.op2_sel
connect issue_slots[7].iss_uop.op1_sel, slots_7.io.iss_uop.op1_sel
connect issue_slots[7].iss_uop.imm_packed, slots_7.io.iss_uop.imm_packed
connect issue_slots[7].iss_uop.pimm, slots_7.io.iss_uop.pimm
connect issue_slots[7].iss_uop.imm_sel, slots_7.io.iss_uop.imm_sel
connect issue_slots[7].iss_uop.imm_rename, slots_7.io.iss_uop.imm_rename
connect issue_slots[7].iss_uop.taken, slots_7.io.iss_uop.taken
connect issue_slots[7].iss_uop.pc_lob, slots_7.io.iss_uop.pc_lob
connect issue_slots[7].iss_uop.edge_inst, slots_7.io.iss_uop.edge_inst
connect issue_slots[7].iss_uop.ftq_idx, slots_7.io.iss_uop.ftq_idx
connect issue_slots[7].iss_uop.is_mov, slots_7.io.iss_uop.is_mov
connect issue_slots[7].iss_uop.is_rocc, slots_7.io.iss_uop.is_rocc
connect issue_slots[7].iss_uop.is_sys_pc2epc, slots_7.io.iss_uop.is_sys_pc2epc
connect issue_slots[7].iss_uop.is_eret, slots_7.io.iss_uop.is_eret
connect issue_slots[7].iss_uop.is_amo, slots_7.io.iss_uop.is_amo
connect issue_slots[7].iss_uop.is_sfence, slots_7.io.iss_uop.is_sfence
connect issue_slots[7].iss_uop.is_fencei, slots_7.io.iss_uop.is_fencei
connect issue_slots[7].iss_uop.is_fence, slots_7.io.iss_uop.is_fence
connect issue_slots[7].iss_uop.is_sfb, slots_7.io.iss_uop.is_sfb
connect issue_slots[7].iss_uop.br_type, slots_7.io.iss_uop.br_type
connect issue_slots[7].iss_uop.br_tag, slots_7.io.iss_uop.br_tag
connect issue_slots[7].iss_uop.br_mask, slots_7.io.iss_uop.br_mask
connect issue_slots[7].iss_uop.dis_col_sel, slots_7.io.iss_uop.dis_col_sel
connect issue_slots[7].iss_uop.iw_p3_bypass_hint, slots_7.io.iss_uop.iw_p3_bypass_hint
connect issue_slots[7].iss_uop.iw_p2_bypass_hint, slots_7.io.iss_uop.iw_p2_bypass_hint
connect issue_slots[7].iss_uop.iw_p1_bypass_hint, slots_7.io.iss_uop.iw_p1_bypass_hint
connect issue_slots[7].iss_uop.iw_p2_speculative_child, slots_7.io.iss_uop.iw_p2_speculative_child
connect issue_slots[7].iss_uop.iw_p1_speculative_child, slots_7.io.iss_uop.iw_p1_speculative_child
connect issue_slots[7].iss_uop.iw_issued_partial_dgen, slots_7.io.iss_uop.iw_issued_partial_dgen
connect issue_slots[7].iss_uop.iw_issued_partial_agen, slots_7.io.iss_uop.iw_issued_partial_agen
connect issue_slots[7].iss_uop.iw_issued, slots_7.io.iss_uop.iw_issued
connect issue_slots[7].iss_uop.fu_code[0], slots_7.io.iss_uop.fu_code[0]
connect issue_slots[7].iss_uop.fu_code[1], slots_7.io.iss_uop.fu_code[1]
connect issue_slots[7].iss_uop.fu_code[2], slots_7.io.iss_uop.fu_code[2]
connect issue_slots[7].iss_uop.fu_code[3], slots_7.io.iss_uop.fu_code[3]
connect issue_slots[7].iss_uop.fu_code[4], slots_7.io.iss_uop.fu_code[4]
connect issue_slots[7].iss_uop.fu_code[5], slots_7.io.iss_uop.fu_code[5]
connect issue_slots[7].iss_uop.fu_code[6], slots_7.io.iss_uop.fu_code[6]
connect issue_slots[7].iss_uop.fu_code[7], slots_7.io.iss_uop.fu_code[7]
connect issue_slots[7].iss_uop.fu_code[8], slots_7.io.iss_uop.fu_code[8]
connect issue_slots[7].iss_uop.fu_code[9], slots_7.io.iss_uop.fu_code[9]
connect issue_slots[7].iss_uop.iq_type[0], slots_7.io.iss_uop.iq_type[0]
connect issue_slots[7].iss_uop.iq_type[1], slots_7.io.iss_uop.iq_type[1]
connect issue_slots[7].iss_uop.iq_type[2], slots_7.io.iss_uop.iq_type[2]
connect issue_slots[7].iss_uop.iq_type[3], slots_7.io.iss_uop.iq_type[3]
connect issue_slots[7].iss_uop.debug_pc, slots_7.io.iss_uop.debug_pc
connect issue_slots[7].iss_uop.is_rvc, slots_7.io.iss_uop.is_rvc
connect issue_slots[7].iss_uop.debug_inst, slots_7.io.iss_uop.debug_inst
connect issue_slots[7].iss_uop.inst, slots_7.io.iss_uop.inst
connect slots_7.io.grant, issue_slots[7].grant
connect issue_slots[7].request, slots_7.io.request
connect issue_slots[7].will_be_valid, slots_7.io.will_be_valid
connect issue_slots[7].valid, slots_7.io.valid
connect slots_8.io.child_rebusys, issue_slots[8].child_rebusys
connect slots_8.io.pred_wakeup_port.bits, issue_slots[8].pred_wakeup_port.bits
connect slots_8.io.pred_wakeup_port.valid, issue_slots[8].pred_wakeup_port.valid
connect slots_8.io.wakeup_ports[0].bits.rebusy, issue_slots[8].wakeup_ports[0].bits.rebusy
connect slots_8.io.wakeup_ports[0].bits.speculative_mask, issue_slots[8].wakeup_ports[0].bits.speculative_mask
connect slots_8.io.wakeup_ports[0].bits.bypassable, issue_slots[8].wakeup_ports[0].bits.bypassable
connect slots_8.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[8].wakeup_ports[0].bits.uop.debug_tsrc
connect slots_8.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[8].wakeup_ports[0].bits.uop.debug_fsrc
connect slots_8.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[8].wakeup_ports[0].bits.uop.bp_xcpt_if
connect slots_8.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[8].wakeup_ports[0].bits.uop.bp_debug_if
connect slots_8.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[8].wakeup_ports[0].bits.uop.xcpt_ma_if
connect slots_8.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[8].wakeup_ports[0].bits.uop.xcpt_ae_if
connect slots_8.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[8].wakeup_ports[0].bits.uop.xcpt_pf_if
connect slots_8.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[8].wakeup_ports[0].bits.uop.fp_typ
connect slots_8.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[8].wakeup_ports[0].bits.uop.fp_rm
connect slots_8.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[8].wakeup_ports[0].bits.uop.fp_val
connect slots_8.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[8].wakeup_ports[0].bits.uop.fcn_op
connect slots_8.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[8].wakeup_ports[0].bits.uop.fcn_dw
connect slots_8.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[8].wakeup_ports[0].bits.uop.frs3_en
connect slots_8.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[8].wakeup_ports[0].bits.uop.lrs2_rtype
connect slots_8.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[8].wakeup_ports[0].bits.uop.lrs1_rtype
connect slots_8.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[8].wakeup_ports[0].bits.uop.dst_rtype
connect slots_8.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[8].wakeup_ports[0].bits.uop.lrs3
connect slots_8.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[8].wakeup_ports[0].bits.uop.lrs2
connect slots_8.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[8].wakeup_ports[0].bits.uop.lrs1
connect slots_8.io.wakeup_ports[0].bits.uop.ldst, issue_slots[8].wakeup_ports[0].bits.uop.ldst
connect slots_8.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[8].wakeup_ports[0].bits.uop.ldst_is_rs1
connect slots_8.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[8].wakeup_ports[0].bits.uop.csr_cmd
connect slots_8.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[8].wakeup_ports[0].bits.uop.flush_on_commit
connect slots_8.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[8].wakeup_ports[0].bits.uop.is_unique
connect slots_8.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[8].wakeup_ports[0].bits.uop.uses_stq
connect slots_8.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[8].wakeup_ports[0].bits.uop.uses_ldq
connect slots_8.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[8].wakeup_ports[0].bits.uop.mem_signed
connect slots_8.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[8].wakeup_ports[0].bits.uop.mem_size
connect slots_8.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[8].wakeup_ports[0].bits.uop.mem_cmd
connect slots_8.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[8].wakeup_ports[0].bits.uop.exc_cause
connect slots_8.io.wakeup_ports[0].bits.uop.exception, issue_slots[8].wakeup_ports[0].bits.uop.exception
connect slots_8.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[8].wakeup_ports[0].bits.uop.stale_pdst
connect slots_8.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[8].wakeup_ports[0].bits.uop.ppred_busy
connect slots_8.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[8].wakeup_ports[0].bits.uop.prs3_busy
connect slots_8.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[8].wakeup_ports[0].bits.uop.prs2_busy
connect slots_8.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[8].wakeup_ports[0].bits.uop.prs1_busy
connect slots_8.io.wakeup_ports[0].bits.uop.ppred, issue_slots[8].wakeup_ports[0].bits.uop.ppred
connect slots_8.io.wakeup_ports[0].bits.uop.prs3, issue_slots[8].wakeup_ports[0].bits.uop.prs3
connect slots_8.io.wakeup_ports[0].bits.uop.prs2, issue_slots[8].wakeup_ports[0].bits.uop.prs2
connect slots_8.io.wakeup_ports[0].bits.uop.prs1, issue_slots[8].wakeup_ports[0].bits.uop.prs1
connect slots_8.io.wakeup_ports[0].bits.uop.pdst, issue_slots[8].wakeup_ports[0].bits.uop.pdst
connect slots_8.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[8].wakeup_ports[0].bits.uop.rxq_idx
connect slots_8.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[8].wakeup_ports[0].bits.uop.stq_idx
connect slots_8.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[8].wakeup_ports[0].bits.uop.ldq_idx
connect slots_8.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[8].wakeup_ports[0].bits.uop.rob_idx
connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.vec
connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.wflags
connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.sqrt
connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.div
connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.fma
connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe
connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.toint
connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.fromint
connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut
connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn
connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.swap23
connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.swap12
connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.ren3
connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.ren2
connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.ren1
connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.wen
connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.ldst
connect slots_8.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[8].wakeup_ports[0].bits.uop.op2_sel
connect slots_8.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[8].wakeup_ports[0].bits.uop.op1_sel
connect slots_8.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[8].wakeup_ports[0].bits.uop.imm_packed
connect slots_8.io.wakeup_ports[0].bits.uop.pimm, issue_slots[8].wakeup_ports[0].bits.uop.pimm
connect slots_8.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[8].wakeup_ports[0].bits.uop.imm_sel
connect slots_8.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[8].wakeup_ports[0].bits.uop.imm_rename
connect slots_8.io.wakeup_ports[0].bits.uop.taken, issue_slots[8].wakeup_ports[0].bits.uop.taken
connect slots_8.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[8].wakeup_ports[0].bits.uop.pc_lob
connect slots_8.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[8].wakeup_ports[0].bits.uop.edge_inst
connect slots_8.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[8].wakeup_ports[0].bits.uop.ftq_idx
connect slots_8.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[8].wakeup_ports[0].bits.uop.is_mov
connect slots_8.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[8].wakeup_ports[0].bits.uop.is_rocc
connect slots_8.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[8].wakeup_ports[0].bits.uop.is_sys_pc2epc
connect slots_8.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[8].wakeup_ports[0].bits.uop.is_eret
connect slots_8.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[8].wakeup_ports[0].bits.uop.is_amo
connect slots_8.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[8].wakeup_ports[0].bits.uop.is_sfence
connect slots_8.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[8].wakeup_ports[0].bits.uop.is_fencei
connect slots_8.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[8].wakeup_ports[0].bits.uop.is_fence
connect slots_8.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[8].wakeup_ports[0].bits.uop.is_sfb
connect slots_8.io.wakeup_ports[0].bits.uop.br_type, issue_slots[8].wakeup_ports[0].bits.uop.br_type
connect slots_8.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[8].wakeup_ports[0].bits.uop.br_tag
connect slots_8.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[8].wakeup_ports[0].bits.uop.br_mask
connect slots_8.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[8].wakeup_ports[0].bits.uop.dis_col_sel
connect slots_8.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[8].wakeup_ports[0].bits.uop.iw_p3_bypass_hint
connect slots_8.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[8].wakeup_ports[0].bits.uop.iw_p2_bypass_hint
connect slots_8.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[8].wakeup_ports[0].bits.uop.iw_p1_bypass_hint
connect slots_8.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[8].wakeup_ports[0].bits.uop.iw_p2_speculative_child
connect slots_8.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[8].wakeup_ports[0].bits.uop.iw_p1_speculative_child
connect slots_8.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[8].wakeup_ports[0].bits.uop.iw_issued_partial_dgen
connect slots_8.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[8].wakeup_ports[0].bits.uop.iw_issued_partial_agen
connect slots_8.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[8].wakeup_ports[0].bits.uop.iw_issued
connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[0]
connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[1]
connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[2]
connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[3]
connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[4]
connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[5]
connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[6]
connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[7]
connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[8]
connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[9]
connect slots_8.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[8].wakeup_ports[0].bits.uop.iq_type[0]
connect slots_8.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[8].wakeup_ports[0].bits.uop.iq_type[1]
connect slots_8.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[8].wakeup_ports[0].bits.uop.iq_type[2]
connect slots_8.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[8].wakeup_ports[0].bits.uop.iq_type[3]
connect slots_8.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[8].wakeup_ports[0].bits.uop.debug_pc
connect slots_8.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[8].wakeup_ports[0].bits.uop.is_rvc
connect slots_8.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[8].wakeup_ports[0].bits.uop.debug_inst
connect slots_8.io.wakeup_ports[0].bits.uop.inst, issue_slots[8].wakeup_ports[0].bits.uop.inst
connect slots_8.io.wakeup_ports[0].valid, issue_slots[8].wakeup_ports[0].valid
connect slots_8.io.wakeup_ports[1].bits.rebusy, issue_slots[8].wakeup_ports[1].bits.rebusy
connect slots_8.io.wakeup_ports[1].bits.speculative_mask, issue_slots[8].wakeup_ports[1].bits.speculative_mask
connect slots_8.io.wakeup_ports[1].bits.bypassable, issue_slots[8].wakeup_ports[1].bits.bypassable
connect slots_8.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[8].wakeup_ports[1].bits.uop.debug_tsrc
connect slots_8.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[8].wakeup_ports[1].bits.uop.debug_fsrc
connect slots_8.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[8].wakeup_ports[1].bits.uop.bp_xcpt_if
connect slots_8.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[8].wakeup_ports[1].bits.uop.bp_debug_if
connect slots_8.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[8].wakeup_ports[1].bits.uop.xcpt_ma_if
connect slots_8.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[8].wakeup_ports[1].bits.uop.xcpt_ae_if
connect slots_8.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[8].wakeup_ports[1].bits.uop.xcpt_pf_if
connect slots_8.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[8].wakeup_ports[1].bits.uop.fp_typ
connect slots_8.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[8].wakeup_ports[1].bits.uop.fp_rm
connect slots_8.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[8].wakeup_ports[1].bits.uop.fp_val
connect slots_8.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[8].wakeup_ports[1].bits.uop.fcn_op
connect slots_8.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[8].wakeup_ports[1].bits.uop.fcn_dw
connect slots_8.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[8].wakeup_ports[1].bits.uop.frs3_en
connect slots_8.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[8].wakeup_ports[1].bits.uop.lrs2_rtype
connect slots_8.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[8].wakeup_ports[1].bits.uop.lrs1_rtype
connect slots_8.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[8].wakeup_ports[1].bits.uop.dst_rtype
connect slots_8.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[8].wakeup_ports[1].bits.uop.lrs3
connect slots_8.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[8].wakeup_ports[1].bits.uop.lrs2
connect slots_8.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[8].wakeup_ports[1].bits.uop.lrs1
connect slots_8.io.wakeup_ports[1].bits.uop.ldst, issue_slots[8].wakeup_ports[1].bits.uop.ldst
connect slots_8.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[8].wakeup_ports[1].bits.uop.ldst_is_rs1
connect slots_8.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[8].wakeup_ports[1].bits.uop.csr_cmd
connect slots_8.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[8].wakeup_ports[1].bits.uop.flush_on_commit
connect slots_8.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[8].wakeup_ports[1].bits.uop.is_unique
connect slots_8.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[8].wakeup_ports[1].bits.uop.uses_stq
connect slots_8.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[8].wakeup_ports[1].bits.uop.uses_ldq
connect slots_8.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[8].wakeup_ports[1].bits.uop.mem_signed
connect slots_8.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[8].wakeup_ports[1].bits.uop.mem_size
connect slots_8.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[8].wakeup_ports[1].bits.uop.mem_cmd
connect slots_8.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[8].wakeup_ports[1].bits.uop.exc_cause
connect slots_8.io.wakeup_ports[1].bits.uop.exception, issue_slots[8].wakeup_ports[1].bits.uop.exception
connect slots_8.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[8].wakeup_ports[1].bits.uop.stale_pdst
connect slots_8.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[8].wakeup_ports[1].bits.uop.ppred_busy
connect slots_8.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[8].wakeup_ports[1].bits.uop.prs3_busy
connect slots_8.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[8].wakeup_ports[1].bits.uop.prs2_busy
connect slots_8.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[8].wakeup_ports[1].bits.uop.prs1_busy
connect slots_8.io.wakeup_ports[1].bits.uop.ppred, issue_slots[8].wakeup_ports[1].bits.uop.ppred
connect slots_8.io.wakeup_ports[1].bits.uop.prs3, issue_slots[8].wakeup_ports[1].bits.uop.prs3
connect slots_8.io.wakeup_ports[1].bits.uop.prs2, issue_slots[8].wakeup_ports[1].bits.uop.prs2
connect slots_8.io.wakeup_ports[1].bits.uop.prs1, issue_slots[8].wakeup_ports[1].bits.uop.prs1
connect slots_8.io.wakeup_ports[1].bits.uop.pdst, issue_slots[8].wakeup_ports[1].bits.uop.pdst
connect slots_8.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[8].wakeup_ports[1].bits.uop.rxq_idx
connect slots_8.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[8].wakeup_ports[1].bits.uop.stq_idx
connect slots_8.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[8].wakeup_ports[1].bits.uop.ldq_idx
connect slots_8.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[8].wakeup_ports[1].bits.uop.rob_idx
connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.vec
connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.wflags
connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.sqrt
connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.div
connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.fma
connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe
connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.toint
connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.fromint
connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut
connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn
connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.swap23
connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.swap12
connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.ren3
connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.ren2
connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.ren1
connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.wen
connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.ldst
connect slots_8.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[8].wakeup_ports[1].bits.uop.op2_sel
connect slots_8.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[8].wakeup_ports[1].bits.uop.op1_sel
connect slots_8.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[8].wakeup_ports[1].bits.uop.imm_packed
connect slots_8.io.wakeup_ports[1].bits.uop.pimm, issue_slots[8].wakeup_ports[1].bits.uop.pimm
connect slots_8.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[8].wakeup_ports[1].bits.uop.imm_sel
connect slots_8.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[8].wakeup_ports[1].bits.uop.imm_rename
connect slots_8.io.wakeup_ports[1].bits.uop.taken, issue_slots[8].wakeup_ports[1].bits.uop.taken
connect slots_8.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[8].wakeup_ports[1].bits.uop.pc_lob
connect slots_8.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[8].wakeup_ports[1].bits.uop.edge_inst
connect slots_8.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[8].wakeup_ports[1].bits.uop.ftq_idx
connect slots_8.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[8].wakeup_ports[1].bits.uop.is_mov
connect slots_8.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[8].wakeup_ports[1].bits.uop.is_rocc
connect slots_8.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[8].wakeup_ports[1].bits.uop.is_sys_pc2epc
connect slots_8.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[8].wakeup_ports[1].bits.uop.is_eret
connect slots_8.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[8].wakeup_ports[1].bits.uop.is_amo
connect slots_8.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[8].wakeup_ports[1].bits.uop.is_sfence
connect slots_8.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[8].wakeup_ports[1].bits.uop.is_fencei
connect slots_8.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[8].wakeup_ports[1].bits.uop.is_fence
connect slots_8.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[8].wakeup_ports[1].bits.uop.is_sfb
connect slots_8.io.wakeup_ports[1].bits.uop.br_type, issue_slots[8].wakeup_ports[1].bits.uop.br_type
connect slots_8.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[8].wakeup_ports[1].bits.uop.br_tag
connect slots_8.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[8].wakeup_ports[1].bits.uop.br_mask
connect slots_8.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[8].wakeup_ports[1].bits.uop.dis_col_sel
connect slots_8.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[8].wakeup_ports[1].bits.uop.iw_p3_bypass_hint
connect slots_8.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[8].wakeup_ports[1].bits.uop.iw_p2_bypass_hint
connect slots_8.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[8].wakeup_ports[1].bits.uop.iw_p1_bypass_hint
connect slots_8.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[8].wakeup_ports[1].bits.uop.iw_p2_speculative_child
connect slots_8.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[8].wakeup_ports[1].bits.uop.iw_p1_speculative_child
connect slots_8.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[8].wakeup_ports[1].bits.uop.iw_issued_partial_dgen
connect slots_8.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[8].wakeup_ports[1].bits.uop.iw_issued_partial_agen
connect slots_8.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[8].wakeup_ports[1].bits.uop.iw_issued
connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[0]
connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[1]
connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[2]
connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[3]
connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[4]
connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[5]
connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[6]
connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[7]
connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[8]
connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[9]
connect slots_8.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[8].wakeup_ports[1].bits.uop.iq_type[0]
connect slots_8.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[8].wakeup_ports[1].bits.uop.iq_type[1]
connect slots_8.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[8].wakeup_ports[1].bits.uop.iq_type[2]
connect slots_8.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[8].wakeup_ports[1].bits.uop.iq_type[3]
connect slots_8.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[8].wakeup_ports[1].bits.uop.debug_pc
connect slots_8.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[8].wakeup_ports[1].bits.uop.is_rvc
connect slots_8.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[8].wakeup_ports[1].bits.uop.debug_inst
connect slots_8.io.wakeup_ports[1].bits.uop.inst, issue_slots[8].wakeup_ports[1].bits.uop.inst
connect slots_8.io.wakeup_ports[1].valid, issue_slots[8].wakeup_ports[1].valid
connect slots_8.io.wakeup_ports[2].bits.rebusy, issue_slots[8].wakeup_ports[2].bits.rebusy
connect slots_8.io.wakeup_ports[2].bits.speculative_mask, issue_slots[8].wakeup_ports[2].bits.speculative_mask
connect slots_8.io.wakeup_ports[2].bits.bypassable, issue_slots[8].wakeup_ports[2].bits.bypassable
connect slots_8.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[8].wakeup_ports[2].bits.uop.debug_tsrc
connect slots_8.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[8].wakeup_ports[2].bits.uop.debug_fsrc
connect slots_8.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[8].wakeup_ports[2].bits.uop.bp_xcpt_if
connect slots_8.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[8].wakeup_ports[2].bits.uop.bp_debug_if
connect slots_8.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[8].wakeup_ports[2].bits.uop.xcpt_ma_if
connect slots_8.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[8].wakeup_ports[2].bits.uop.xcpt_ae_if
connect slots_8.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[8].wakeup_ports[2].bits.uop.xcpt_pf_if
connect slots_8.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[8].wakeup_ports[2].bits.uop.fp_typ
connect slots_8.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[8].wakeup_ports[2].bits.uop.fp_rm
connect slots_8.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[8].wakeup_ports[2].bits.uop.fp_val
connect slots_8.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[8].wakeup_ports[2].bits.uop.fcn_op
connect slots_8.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[8].wakeup_ports[2].bits.uop.fcn_dw
connect slots_8.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[8].wakeup_ports[2].bits.uop.frs3_en
connect slots_8.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[8].wakeup_ports[2].bits.uop.lrs2_rtype
connect slots_8.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[8].wakeup_ports[2].bits.uop.lrs1_rtype
connect slots_8.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[8].wakeup_ports[2].bits.uop.dst_rtype
connect slots_8.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[8].wakeup_ports[2].bits.uop.lrs3
connect slots_8.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[8].wakeup_ports[2].bits.uop.lrs2
connect slots_8.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[8].wakeup_ports[2].bits.uop.lrs1
connect slots_8.io.wakeup_ports[2].bits.uop.ldst, issue_slots[8].wakeup_ports[2].bits.uop.ldst
connect slots_8.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[8].wakeup_ports[2].bits.uop.ldst_is_rs1
connect slots_8.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[8].wakeup_ports[2].bits.uop.csr_cmd
connect slots_8.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[8].wakeup_ports[2].bits.uop.flush_on_commit
connect slots_8.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[8].wakeup_ports[2].bits.uop.is_unique
connect slots_8.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[8].wakeup_ports[2].bits.uop.uses_stq
connect slots_8.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[8].wakeup_ports[2].bits.uop.uses_ldq
connect slots_8.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[8].wakeup_ports[2].bits.uop.mem_signed
connect slots_8.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[8].wakeup_ports[2].bits.uop.mem_size
connect slots_8.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[8].wakeup_ports[2].bits.uop.mem_cmd
connect slots_8.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[8].wakeup_ports[2].bits.uop.exc_cause
connect slots_8.io.wakeup_ports[2].bits.uop.exception, issue_slots[8].wakeup_ports[2].bits.uop.exception
connect slots_8.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[8].wakeup_ports[2].bits.uop.stale_pdst
connect slots_8.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[8].wakeup_ports[2].bits.uop.ppred_busy
connect slots_8.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[8].wakeup_ports[2].bits.uop.prs3_busy
connect slots_8.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[8].wakeup_ports[2].bits.uop.prs2_busy
connect slots_8.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[8].wakeup_ports[2].bits.uop.prs1_busy
connect slots_8.io.wakeup_ports[2].bits.uop.ppred, issue_slots[8].wakeup_ports[2].bits.uop.ppred
connect slots_8.io.wakeup_ports[2].bits.uop.prs3, issue_slots[8].wakeup_ports[2].bits.uop.prs3
connect slots_8.io.wakeup_ports[2].bits.uop.prs2, issue_slots[8].wakeup_ports[2].bits.uop.prs2
connect slots_8.io.wakeup_ports[2].bits.uop.prs1, issue_slots[8].wakeup_ports[2].bits.uop.prs1
connect slots_8.io.wakeup_ports[2].bits.uop.pdst, issue_slots[8].wakeup_ports[2].bits.uop.pdst
connect slots_8.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[8].wakeup_ports[2].bits.uop.rxq_idx
connect slots_8.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[8].wakeup_ports[2].bits.uop.stq_idx
connect slots_8.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[8].wakeup_ports[2].bits.uop.ldq_idx
connect slots_8.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[8].wakeup_ports[2].bits.uop.rob_idx
connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.vec
connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.wflags
connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.sqrt
connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.div
connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.fma
connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe
connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.toint
connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.fromint
connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut
connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn
connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.swap23
connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.swap12
connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.ren3
connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.ren2
connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.ren1
connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.wen
connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.ldst
connect slots_8.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[8].wakeup_ports[2].bits.uop.op2_sel
connect slots_8.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[8].wakeup_ports[2].bits.uop.op1_sel
connect slots_8.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[8].wakeup_ports[2].bits.uop.imm_packed
connect slots_8.io.wakeup_ports[2].bits.uop.pimm, issue_slots[8].wakeup_ports[2].bits.uop.pimm
connect slots_8.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[8].wakeup_ports[2].bits.uop.imm_sel
connect slots_8.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[8].wakeup_ports[2].bits.uop.imm_rename
connect slots_8.io.wakeup_ports[2].bits.uop.taken, issue_slots[8].wakeup_ports[2].bits.uop.taken
connect slots_8.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[8].wakeup_ports[2].bits.uop.pc_lob
connect slots_8.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[8].wakeup_ports[2].bits.uop.edge_inst
connect slots_8.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[8].wakeup_ports[2].bits.uop.ftq_idx
connect slots_8.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[8].wakeup_ports[2].bits.uop.is_mov
connect slots_8.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[8].wakeup_ports[2].bits.uop.is_rocc
connect slots_8.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[8].wakeup_ports[2].bits.uop.is_sys_pc2epc
connect slots_8.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[8].wakeup_ports[2].bits.uop.is_eret
connect slots_8.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[8].wakeup_ports[2].bits.uop.is_amo
connect slots_8.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[8].wakeup_ports[2].bits.uop.is_sfence
connect slots_8.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[8].wakeup_ports[2].bits.uop.is_fencei
connect slots_8.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[8].wakeup_ports[2].bits.uop.is_fence
connect slots_8.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[8].wakeup_ports[2].bits.uop.is_sfb
connect slots_8.io.wakeup_ports[2].bits.uop.br_type, issue_slots[8].wakeup_ports[2].bits.uop.br_type
connect slots_8.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[8].wakeup_ports[2].bits.uop.br_tag
connect slots_8.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[8].wakeup_ports[2].bits.uop.br_mask
connect slots_8.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[8].wakeup_ports[2].bits.uop.dis_col_sel
connect slots_8.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[8].wakeup_ports[2].bits.uop.iw_p3_bypass_hint
connect slots_8.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[8].wakeup_ports[2].bits.uop.iw_p2_bypass_hint
connect slots_8.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[8].wakeup_ports[2].bits.uop.iw_p1_bypass_hint
connect slots_8.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[8].wakeup_ports[2].bits.uop.iw_p2_speculative_child
connect slots_8.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[8].wakeup_ports[2].bits.uop.iw_p1_speculative_child
connect slots_8.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[8].wakeup_ports[2].bits.uop.iw_issued_partial_dgen
connect slots_8.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[8].wakeup_ports[2].bits.uop.iw_issued_partial_agen
connect slots_8.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[8].wakeup_ports[2].bits.uop.iw_issued
connect slots_8.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[8].wakeup_ports[2].bits.uop.fu_code[0]
connect slots_8.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[8].wakeup_ports[2].bits.uop.fu_code[1]
connect slots_8.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[8].wakeup_ports[2].bits.uop.fu_code[2]
connect slots_8.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[8].wakeup_ports[2].bits.uop.fu_code[3]
connect slots_8.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[8].wakeup_ports[2].bits.uop.fu_code[4]
connect slots_8.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[8].wakeup_ports[2].bits.uop.fu_code[5]
connect slots_8.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[8].wakeup_ports[2].bits.uop.fu_code[6]
connect slots_8.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[8].wakeup_ports[2].bits.uop.fu_code[7]
connect slots_8.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[8].wakeup_ports[2].bits.uop.fu_code[8]
connect slots_8.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[8].wakeup_ports[2].bits.uop.fu_code[9]
connect slots_8.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[8].wakeup_ports[2].bits.uop.iq_type[0]
connect slots_8.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[8].wakeup_ports[2].bits.uop.iq_type[1]
connect slots_8.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[8].wakeup_ports[2].bits.uop.iq_type[2]
connect slots_8.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[8].wakeup_ports[2].bits.uop.iq_type[3]
connect slots_8.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[8].wakeup_ports[2].bits.uop.debug_pc
connect slots_8.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[8].wakeup_ports[2].bits.uop.is_rvc
connect slots_8.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[8].wakeup_ports[2].bits.uop.debug_inst
connect slots_8.io.wakeup_ports[2].bits.uop.inst, issue_slots[8].wakeup_ports[2].bits.uop.inst
connect slots_8.io.wakeup_ports[2].valid, issue_slots[8].wakeup_ports[2].valid
connect slots_8.io.wakeup_ports[3].bits.rebusy, issue_slots[8].wakeup_ports[3].bits.rebusy
connect slots_8.io.wakeup_ports[3].bits.speculative_mask, issue_slots[8].wakeup_ports[3].bits.speculative_mask
connect slots_8.io.wakeup_ports[3].bits.bypassable, issue_slots[8].wakeup_ports[3].bits.bypassable
connect slots_8.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[8].wakeup_ports[3].bits.uop.debug_tsrc
connect slots_8.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[8].wakeup_ports[3].bits.uop.debug_fsrc
connect slots_8.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[8].wakeup_ports[3].bits.uop.bp_xcpt_if
connect slots_8.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[8].wakeup_ports[3].bits.uop.bp_debug_if
connect slots_8.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[8].wakeup_ports[3].bits.uop.xcpt_ma_if
connect slots_8.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[8].wakeup_ports[3].bits.uop.xcpt_ae_if
connect slots_8.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[8].wakeup_ports[3].bits.uop.xcpt_pf_if
connect slots_8.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[8].wakeup_ports[3].bits.uop.fp_typ
connect slots_8.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[8].wakeup_ports[3].bits.uop.fp_rm
connect slots_8.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[8].wakeup_ports[3].bits.uop.fp_val
connect slots_8.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[8].wakeup_ports[3].bits.uop.fcn_op
connect slots_8.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[8].wakeup_ports[3].bits.uop.fcn_dw
connect slots_8.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[8].wakeup_ports[3].bits.uop.frs3_en
connect slots_8.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[8].wakeup_ports[3].bits.uop.lrs2_rtype
connect slots_8.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[8].wakeup_ports[3].bits.uop.lrs1_rtype
connect slots_8.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[8].wakeup_ports[3].bits.uop.dst_rtype
connect slots_8.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[8].wakeup_ports[3].bits.uop.lrs3
connect slots_8.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[8].wakeup_ports[3].bits.uop.lrs2
connect slots_8.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[8].wakeup_ports[3].bits.uop.lrs1
connect slots_8.io.wakeup_ports[3].bits.uop.ldst, issue_slots[8].wakeup_ports[3].bits.uop.ldst
connect slots_8.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[8].wakeup_ports[3].bits.uop.ldst_is_rs1
connect slots_8.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[8].wakeup_ports[3].bits.uop.csr_cmd
connect slots_8.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[8].wakeup_ports[3].bits.uop.flush_on_commit
connect slots_8.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[8].wakeup_ports[3].bits.uop.is_unique
connect slots_8.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[8].wakeup_ports[3].bits.uop.uses_stq
connect slots_8.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[8].wakeup_ports[3].bits.uop.uses_ldq
connect slots_8.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[8].wakeup_ports[3].bits.uop.mem_signed
connect slots_8.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[8].wakeup_ports[3].bits.uop.mem_size
connect slots_8.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[8].wakeup_ports[3].bits.uop.mem_cmd
connect slots_8.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[8].wakeup_ports[3].bits.uop.exc_cause
connect slots_8.io.wakeup_ports[3].bits.uop.exception, issue_slots[8].wakeup_ports[3].bits.uop.exception
connect slots_8.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[8].wakeup_ports[3].bits.uop.stale_pdst
connect slots_8.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[8].wakeup_ports[3].bits.uop.ppred_busy
connect slots_8.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[8].wakeup_ports[3].bits.uop.prs3_busy
connect slots_8.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[8].wakeup_ports[3].bits.uop.prs2_busy
connect slots_8.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[8].wakeup_ports[3].bits.uop.prs1_busy
connect slots_8.io.wakeup_ports[3].bits.uop.ppred, issue_slots[8].wakeup_ports[3].bits.uop.ppred
connect slots_8.io.wakeup_ports[3].bits.uop.prs3, issue_slots[8].wakeup_ports[3].bits.uop.prs3
connect slots_8.io.wakeup_ports[3].bits.uop.prs2, issue_slots[8].wakeup_ports[3].bits.uop.prs2
connect slots_8.io.wakeup_ports[3].bits.uop.prs1, issue_slots[8].wakeup_ports[3].bits.uop.prs1
connect slots_8.io.wakeup_ports[3].bits.uop.pdst, issue_slots[8].wakeup_ports[3].bits.uop.pdst
connect slots_8.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[8].wakeup_ports[3].bits.uop.rxq_idx
connect slots_8.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[8].wakeup_ports[3].bits.uop.stq_idx
connect slots_8.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[8].wakeup_ports[3].bits.uop.ldq_idx
connect slots_8.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[8].wakeup_ports[3].bits.uop.rob_idx
connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.vec
connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.wflags
connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.sqrt
connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.div
connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.fma
connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe
connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.toint
connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.fromint
connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut
connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn
connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.swap23
connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.swap12
connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.ren3
connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.ren2
connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.ren1
connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.wen
connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.ldst
connect slots_8.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[8].wakeup_ports[3].bits.uop.op2_sel
connect slots_8.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[8].wakeup_ports[3].bits.uop.op1_sel
connect slots_8.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[8].wakeup_ports[3].bits.uop.imm_packed
connect slots_8.io.wakeup_ports[3].bits.uop.pimm, issue_slots[8].wakeup_ports[3].bits.uop.pimm
connect slots_8.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[8].wakeup_ports[3].bits.uop.imm_sel
connect slots_8.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[8].wakeup_ports[3].bits.uop.imm_rename
connect slots_8.io.wakeup_ports[3].bits.uop.taken, issue_slots[8].wakeup_ports[3].bits.uop.taken
connect slots_8.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[8].wakeup_ports[3].bits.uop.pc_lob
connect slots_8.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[8].wakeup_ports[3].bits.uop.edge_inst
connect slots_8.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[8].wakeup_ports[3].bits.uop.ftq_idx
connect slots_8.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[8].wakeup_ports[3].bits.uop.is_mov
connect slots_8.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[8].wakeup_ports[3].bits.uop.is_rocc
connect slots_8.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[8].wakeup_ports[3].bits.uop.is_sys_pc2epc
connect slots_8.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[8].wakeup_ports[3].bits.uop.is_eret
connect slots_8.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[8].wakeup_ports[3].bits.uop.is_amo
connect slots_8.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[8].wakeup_ports[3].bits.uop.is_sfence
connect slots_8.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[8].wakeup_ports[3].bits.uop.is_fencei
connect slots_8.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[8].wakeup_ports[3].bits.uop.is_fence
connect slots_8.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[8].wakeup_ports[3].bits.uop.is_sfb
connect slots_8.io.wakeup_ports[3].bits.uop.br_type, issue_slots[8].wakeup_ports[3].bits.uop.br_type
connect slots_8.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[8].wakeup_ports[3].bits.uop.br_tag
connect slots_8.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[8].wakeup_ports[3].bits.uop.br_mask
connect slots_8.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[8].wakeup_ports[3].bits.uop.dis_col_sel
connect slots_8.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[8].wakeup_ports[3].bits.uop.iw_p3_bypass_hint
connect slots_8.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[8].wakeup_ports[3].bits.uop.iw_p2_bypass_hint
connect slots_8.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[8].wakeup_ports[3].bits.uop.iw_p1_bypass_hint
connect slots_8.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[8].wakeup_ports[3].bits.uop.iw_p2_speculative_child
connect slots_8.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[8].wakeup_ports[3].bits.uop.iw_p1_speculative_child
connect slots_8.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[8].wakeup_ports[3].bits.uop.iw_issued_partial_dgen
connect slots_8.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[8].wakeup_ports[3].bits.uop.iw_issued_partial_agen
connect slots_8.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[8].wakeup_ports[3].bits.uop.iw_issued
connect slots_8.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[8].wakeup_ports[3].bits.uop.fu_code[0]
connect slots_8.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[8].wakeup_ports[3].bits.uop.fu_code[1]
connect slots_8.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[8].wakeup_ports[3].bits.uop.fu_code[2]
connect slots_8.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[8].wakeup_ports[3].bits.uop.fu_code[3]
connect slots_8.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[8].wakeup_ports[3].bits.uop.fu_code[4]
connect slots_8.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[8].wakeup_ports[3].bits.uop.fu_code[5]
connect slots_8.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[8].wakeup_ports[3].bits.uop.fu_code[6]
connect slots_8.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[8].wakeup_ports[3].bits.uop.fu_code[7]
connect slots_8.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[8].wakeup_ports[3].bits.uop.fu_code[8]
connect slots_8.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[8].wakeup_ports[3].bits.uop.fu_code[9]
connect slots_8.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[8].wakeup_ports[3].bits.uop.iq_type[0]
connect slots_8.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[8].wakeup_ports[3].bits.uop.iq_type[1]
connect slots_8.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[8].wakeup_ports[3].bits.uop.iq_type[2]
connect slots_8.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[8].wakeup_ports[3].bits.uop.iq_type[3]
connect slots_8.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[8].wakeup_ports[3].bits.uop.debug_pc
connect slots_8.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[8].wakeup_ports[3].bits.uop.is_rvc
connect slots_8.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[8].wakeup_ports[3].bits.uop.debug_inst
connect slots_8.io.wakeup_ports[3].bits.uop.inst, issue_slots[8].wakeup_ports[3].bits.uop.inst
connect slots_8.io.wakeup_ports[3].valid, issue_slots[8].wakeup_ports[3].valid
connect slots_8.io.squash_grant, issue_slots[8].squash_grant
connect slots_8.io.clear, issue_slots[8].clear
connect slots_8.io.kill, issue_slots[8].kill
connect slots_8.io.brupdate.b2.target_offset, issue_slots[8].brupdate.b2.target_offset
connect slots_8.io.brupdate.b2.jalr_target, issue_slots[8].brupdate.b2.jalr_target
connect slots_8.io.brupdate.b2.pc_sel, issue_slots[8].brupdate.b2.pc_sel
connect slots_8.io.brupdate.b2.cfi_type, issue_slots[8].brupdate.b2.cfi_type
connect slots_8.io.brupdate.b2.taken, issue_slots[8].brupdate.b2.taken
connect slots_8.io.brupdate.b2.mispredict, issue_slots[8].brupdate.b2.mispredict
connect slots_8.io.brupdate.b2.uop.debug_tsrc, issue_slots[8].brupdate.b2.uop.debug_tsrc
connect slots_8.io.brupdate.b2.uop.debug_fsrc, issue_slots[8].brupdate.b2.uop.debug_fsrc
connect slots_8.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[8].brupdate.b2.uop.bp_xcpt_if
connect slots_8.io.brupdate.b2.uop.bp_debug_if, issue_slots[8].brupdate.b2.uop.bp_debug_if
connect slots_8.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[8].brupdate.b2.uop.xcpt_ma_if
connect slots_8.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[8].brupdate.b2.uop.xcpt_ae_if
connect slots_8.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[8].brupdate.b2.uop.xcpt_pf_if
connect slots_8.io.brupdate.b2.uop.fp_typ, issue_slots[8].brupdate.b2.uop.fp_typ
connect slots_8.io.brupdate.b2.uop.fp_rm, issue_slots[8].brupdate.b2.uop.fp_rm
connect slots_8.io.brupdate.b2.uop.fp_val, issue_slots[8].brupdate.b2.uop.fp_val
connect slots_8.io.brupdate.b2.uop.fcn_op, issue_slots[8].brupdate.b2.uop.fcn_op
connect slots_8.io.brupdate.b2.uop.fcn_dw, issue_slots[8].brupdate.b2.uop.fcn_dw
connect slots_8.io.brupdate.b2.uop.frs3_en, issue_slots[8].brupdate.b2.uop.frs3_en
connect slots_8.io.brupdate.b2.uop.lrs2_rtype, issue_slots[8].brupdate.b2.uop.lrs2_rtype
connect slots_8.io.brupdate.b2.uop.lrs1_rtype, issue_slots[8].brupdate.b2.uop.lrs1_rtype
connect slots_8.io.brupdate.b2.uop.dst_rtype, issue_slots[8].brupdate.b2.uop.dst_rtype
connect slots_8.io.brupdate.b2.uop.lrs3, issue_slots[8].brupdate.b2.uop.lrs3
connect slots_8.io.brupdate.b2.uop.lrs2, issue_slots[8].brupdate.b2.uop.lrs2
connect slots_8.io.brupdate.b2.uop.lrs1, issue_slots[8].brupdate.b2.uop.lrs1
connect slots_8.io.brupdate.b2.uop.ldst, issue_slots[8].brupdate.b2.uop.ldst
connect slots_8.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[8].brupdate.b2.uop.ldst_is_rs1
connect slots_8.io.brupdate.b2.uop.csr_cmd, issue_slots[8].brupdate.b2.uop.csr_cmd
connect slots_8.io.brupdate.b2.uop.flush_on_commit, issue_slots[8].brupdate.b2.uop.flush_on_commit
connect slots_8.io.brupdate.b2.uop.is_unique, issue_slots[8].brupdate.b2.uop.is_unique
connect slots_8.io.brupdate.b2.uop.uses_stq, issue_slots[8].brupdate.b2.uop.uses_stq
connect slots_8.io.brupdate.b2.uop.uses_ldq, issue_slots[8].brupdate.b2.uop.uses_ldq
connect slots_8.io.brupdate.b2.uop.mem_signed, issue_slots[8].brupdate.b2.uop.mem_signed
connect slots_8.io.brupdate.b2.uop.mem_size, issue_slots[8].brupdate.b2.uop.mem_size
connect slots_8.io.brupdate.b2.uop.mem_cmd, issue_slots[8].brupdate.b2.uop.mem_cmd
connect slots_8.io.brupdate.b2.uop.exc_cause, issue_slots[8].brupdate.b2.uop.exc_cause
connect slots_8.io.brupdate.b2.uop.exception, issue_slots[8].brupdate.b2.uop.exception
connect slots_8.io.brupdate.b2.uop.stale_pdst, issue_slots[8].brupdate.b2.uop.stale_pdst
connect slots_8.io.brupdate.b2.uop.ppred_busy, issue_slots[8].brupdate.b2.uop.ppred_busy
connect slots_8.io.brupdate.b2.uop.prs3_busy, issue_slots[8].brupdate.b2.uop.prs3_busy
connect slots_8.io.brupdate.b2.uop.prs2_busy, issue_slots[8].brupdate.b2.uop.prs2_busy
connect slots_8.io.brupdate.b2.uop.prs1_busy, issue_slots[8].brupdate.b2.uop.prs1_busy
connect slots_8.io.brupdate.b2.uop.ppred, issue_slots[8].brupdate.b2.uop.ppred
connect slots_8.io.brupdate.b2.uop.prs3, issue_slots[8].brupdate.b2.uop.prs3
connect slots_8.io.brupdate.b2.uop.prs2, issue_slots[8].brupdate.b2.uop.prs2
connect slots_8.io.brupdate.b2.uop.prs1, issue_slots[8].brupdate.b2.uop.prs1
connect slots_8.io.brupdate.b2.uop.pdst, issue_slots[8].brupdate.b2.uop.pdst
connect slots_8.io.brupdate.b2.uop.rxq_idx, issue_slots[8].brupdate.b2.uop.rxq_idx
connect slots_8.io.brupdate.b2.uop.stq_idx, issue_slots[8].brupdate.b2.uop.stq_idx
connect slots_8.io.brupdate.b2.uop.ldq_idx, issue_slots[8].brupdate.b2.uop.ldq_idx
connect slots_8.io.brupdate.b2.uop.rob_idx, issue_slots[8].brupdate.b2.uop.rob_idx
connect slots_8.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[8].brupdate.b2.uop.fp_ctrl.vec
connect slots_8.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[8].brupdate.b2.uop.fp_ctrl.wflags
connect slots_8.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[8].brupdate.b2.uop.fp_ctrl.sqrt
connect slots_8.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[8].brupdate.b2.uop.fp_ctrl.div
connect slots_8.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[8].brupdate.b2.uop.fp_ctrl.fma
connect slots_8.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[8].brupdate.b2.uop.fp_ctrl.fastpipe
connect slots_8.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[8].brupdate.b2.uop.fp_ctrl.toint
connect slots_8.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[8].brupdate.b2.uop.fp_ctrl.fromint
connect slots_8.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[8].brupdate.b2.uop.fp_ctrl.typeTagOut
connect slots_8.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[8].brupdate.b2.uop.fp_ctrl.typeTagIn
connect slots_8.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[8].brupdate.b2.uop.fp_ctrl.swap23
connect slots_8.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[8].brupdate.b2.uop.fp_ctrl.swap12
connect slots_8.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[8].brupdate.b2.uop.fp_ctrl.ren3
connect slots_8.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[8].brupdate.b2.uop.fp_ctrl.ren2
connect slots_8.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[8].brupdate.b2.uop.fp_ctrl.ren1
connect slots_8.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[8].brupdate.b2.uop.fp_ctrl.wen
connect slots_8.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[8].brupdate.b2.uop.fp_ctrl.ldst
connect slots_8.io.brupdate.b2.uop.op2_sel, issue_slots[8].brupdate.b2.uop.op2_sel
connect slots_8.io.brupdate.b2.uop.op1_sel, issue_slots[8].brupdate.b2.uop.op1_sel
connect slots_8.io.brupdate.b2.uop.imm_packed, issue_slots[8].brupdate.b2.uop.imm_packed
connect slots_8.io.brupdate.b2.uop.pimm, issue_slots[8].brupdate.b2.uop.pimm
connect slots_8.io.brupdate.b2.uop.imm_sel, issue_slots[8].brupdate.b2.uop.imm_sel
connect slots_8.io.brupdate.b2.uop.imm_rename, issue_slots[8].brupdate.b2.uop.imm_rename
connect slots_8.io.brupdate.b2.uop.taken, issue_slots[8].brupdate.b2.uop.taken
connect slots_8.io.brupdate.b2.uop.pc_lob, issue_slots[8].brupdate.b2.uop.pc_lob
connect slots_8.io.brupdate.b2.uop.edge_inst, issue_slots[8].brupdate.b2.uop.edge_inst
connect slots_8.io.brupdate.b2.uop.ftq_idx, issue_slots[8].brupdate.b2.uop.ftq_idx
connect slots_8.io.brupdate.b2.uop.is_mov, issue_slots[8].brupdate.b2.uop.is_mov
connect slots_8.io.brupdate.b2.uop.is_rocc, issue_slots[8].brupdate.b2.uop.is_rocc
connect slots_8.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[8].brupdate.b2.uop.is_sys_pc2epc
connect slots_8.io.brupdate.b2.uop.is_eret, issue_slots[8].brupdate.b2.uop.is_eret
connect slots_8.io.brupdate.b2.uop.is_amo, issue_slots[8].brupdate.b2.uop.is_amo
connect slots_8.io.brupdate.b2.uop.is_sfence, issue_slots[8].brupdate.b2.uop.is_sfence
connect slots_8.io.brupdate.b2.uop.is_fencei, issue_slots[8].brupdate.b2.uop.is_fencei
connect slots_8.io.brupdate.b2.uop.is_fence, issue_slots[8].brupdate.b2.uop.is_fence
connect slots_8.io.brupdate.b2.uop.is_sfb, issue_slots[8].brupdate.b2.uop.is_sfb
connect slots_8.io.brupdate.b2.uop.br_type, issue_slots[8].brupdate.b2.uop.br_type
connect slots_8.io.brupdate.b2.uop.br_tag, issue_slots[8].brupdate.b2.uop.br_tag
connect slots_8.io.brupdate.b2.uop.br_mask, issue_slots[8].brupdate.b2.uop.br_mask
connect slots_8.io.brupdate.b2.uop.dis_col_sel, issue_slots[8].brupdate.b2.uop.dis_col_sel
connect slots_8.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[8].brupdate.b2.uop.iw_p3_bypass_hint
connect slots_8.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[8].brupdate.b2.uop.iw_p2_bypass_hint
connect slots_8.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[8].brupdate.b2.uop.iw_p1_bypass_hint
connect slots_8.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[8].brupdate.b2.uop.iw_p2_speculative_child
connect slots_8.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[8].brupdate.b2.uop.iw_p1_speculative_child
connect slots_8.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[8].brupdate.b2.uop.iw_issued_partial_dgen
connect slots_8.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[8].brupdate.b2.uop.iw_issued_partial_agen
connect slots_8.io.brupdate.b2.uop.iw_issued, issue_slots[8].brupdate.b2.uop.iw_issued
connect slots_8.io.brupdate.b2.uop.fu_code[0], issue_slots[8].brupdate.b2.uop.fu_code[0]
connect slots_8.io.brupdate.b2.uop.fu_code[1], issue_slots[8].brupdate.b2.uop.fu_code[1]
connect slots_8.io.brupdate.b2.uop.fu_code[2], issue_slots[8].brupdate.b2.uop.fu_code[2]
connect slots_8.io.brupdate.b2.uop.fu_code[3], issue_slots[8].brupdate.b2.uop.fu_code[3]
connect slots_8.io.brupdate.b2.uop.fu_code[4], issue_slots[8].brupdate.b2.uop.fu_code[4]
connect slots_8.io.brupdate.b2.uop.fu_code[5], issue_slots[8].brupdate.b2.uop.fu_code[5]
connect slots_8.io.brupdate.b2.uop.fu_code[6], issue_slots[8].brupdate.b2.uop.fu_code[6]
connect slots_8.io.brupdate.b2.uop.fu_code[7], issue_slots[8].brupdate.b2.uop.fu_code[7]
connect slots_8.io.brupdate.b2.uop.fu_code[8], issue_slots[8].brupdate.b2.uop.fu_code[8]
connect slots_8.io.brupdate.b2.uop.fu_code[9], issue_slots[8].brupdate.b2.uop.fu_code[9]
connect slots_8.io.brupdate.b2.uop.iq_type[0], issue_slots[8].brupdate.b2.uop.iq_type[0]
connect slots_8.io.brupdate.b2.uop.iq_type[1], issue_slots[8].brupdate.b2.uop.iq_type[1]
connect slots_8.io.brupdate.b2.uop.iq_type[2], issue_slots[8].brupdate.b2.uop.iq_type[2]
connect slots_8.io.brupdate.b2.uop.iq_type[3], issue_slots[8].brupdate.b2.uop.iq_type[3]
connect slots_8.io.brupdate.b2.uop.debug_pc, issue_slots[8].brupdate.b2.uop.debug_pc
connect slots_8.io.brupdate.b2.uop.is_rvc, issue_slots[8].brupdate.b2.uop.is_rvc
connect slots_8.io.brupdate.b2.uop.debug_inst, issue_slots[8].brupdate.b2.uop.debug_inst
connect slots_8.io.brupdate.b2.uop.inst, issue_slots[8].brupdate.b2.uop.inst
connect slots_8.io.brupdate.b1.mispredict_mask, issue_slots[8].brupdate.b1.mispredict_mask
connect slots_8.io.brupdate.b1.resolve_mask, issue_slots[8].brupdate.b1.resolve_mask
connect issue_slots[8].out_uop.debug_tsrc, slots_8.io.out_uop.debug_tsrc
connect issue_slots[8].out_uop.debug_fsrc, slots_8.io.out_uop.debug_fsrc
connect issue_slots[8].out_uop.bp_xcpt_if, slots_8.io.out_uop.bp_xcpt_if
connect issue_slots[8].out_uop.bp_debug_if, slots_8.io.out_uop.bp_debug_if
connect issue_slots[8].out_uop.xcpt_ma_if, slots_8.io.out_uop.xcpt_ma_if
connect issue_slots[8].out_uop.xcpt_ae_if, slots_8.io.out_uop.xcpt_ae_if
connect issue_slots[8].out_uop.xcpt_pf_if, slots_8.io.out_uop.xcpt_pf_if
connect issue_slots[8].out_uop.fp_typ, slots_8.io.out_uop.fp_typ
connect issue_slots[8].out_uop.fp_rm, slots_8.io.out_uop.fp_rm
connect issue_slots[8].out_uop.fp_val, slots_8.io.out_uop.fp_val
connect issue_slots[8].out_uop.fcn_op, slots_8.io.out_uop.fcn_op
connect issue_slots[8].out_uop.fcn_dw, slots_8.io.out_uop.fcn_dw
connect issue_slots[8].out_uop.frs3_en, slots_8.io.out_uop.frs3_en
connect issue_slots[8].out_uop.lrs2_rtype, slots_8.io.out_uop.lrs2_rtype
connect issue_slots[8].out_uop.lrs1_rtype, slots_8.io.out_uop.lrs1_rtype
connect issue_slots[8].out_uop.dst_rtype, slots_8.io.out_uop.dst_rtype
connect issue_slots[8].out_uop.lrs3, slots_8.io.out_uop.lrs3
connect issue_slots[8].out_uop.lrs2, slots_8.io.out_uop.lrs2
connect issue_slots[8].out_uop.lrs1, slots_8.io.out_uop.lrs1
connect issue_slots[8].out_uop.ldst, slots_8.io.out_uop.ldst
connect issue_slots[8].out_uop.ldst_is_rs1, slots_8.io.out_uop.ldst_is_rs1
connect issue_slots[8].out_uop.csr_cmd, slots_8.io.out_uop.csr_cmd
connect issue_slots[8].out_uop.flush_on_commit, slots_8.io.out_uop.flush_on_commit
connect issue_slots[8].out_uop.is_unique, slots_8.io.out_uop.is_unique
connect issue_slots[8].out_uop.uses_stq, slots_8.io.out_uop.uses_stq
connect issue_slots[8].out_uop.uses_ldq, slots_8.io.out_uop.uses_ldq
connect issue_slots[8].out_uop.mem_signed, slots_8.io.out_uop.mem_signed
connect issue_slots[8].out_uop.mem_size, slots_8.io.out_uop.mem_size
connect issue_slots[8].out_uop.mem_cmd, slots_8.io.out_uop.mem_cmd
connect issue_slots[8].out_uop.exc_cause, slots_8.io.out_uop.exc_cause
connect issue_slots[8].out_uop.exception, slots_8.io.out_uop.exception
connect issue_slots[8].out_uop.stale_pdst, slots_8.io.out_uop.stale_pdst
connect issue_slots[8].out_uop.ppred_busy, slots_8.io.out_uop.ppred_busy
connect issue_slots[8].out_uop.prs3_busy, slots_8.io.out_uop.prs3_busy
connect issue_slots[8].out_uop.prs2_busy, slots_8.io.out_uop.prs2_busy
connect issue_slots[8].out_uop.prs1_busy, slots_8.io.out_uop.prs1_busy
connect issue_slots[8].out_uop.ppred, slots_8.io.out_uop.ppred
connect issue_slots[8].out_uop.prs3, slots_8.io.out_uop.prs3
connect issue_slots[8].out_uop.prs2, slots_8.io.out_uop.prs2
connect issue_slots[8].out_uop.prs1, slots_8.io.out_uop.prs1
connect issue_slots[8].out_uop.pdst, slots_8.io.out_uop.pdst
connect issue_slots[8].out_uop.rxq_idx, slots_8.io.out_uop.rxq_idx
connect issue_slots[8].out_uop.stq_idx, slots_8.io.out_uop.stq_idx
connect issue_slots[8].out_uop.ldq_idx, slots_8.io.out_uop.ldq_idx
connect issue_slots[8].out_uop.rob_idx, slots_8.io.out_uop.rob_idx
connect issue_slots[8].out_uop.fp_ctrl.vec, slots_8.io.out_uop.fp_ctrl.vec
connect issue_slots[8].out_uop.fp_ctrl.wflags, slots_8.io.out_uop.fp_ctrl.wflags
connect issue_slots[8].out_uop.fp_ctrl.sqrt, slots_8.io.out_uop.fp_ctrl.sqrt
connect issue_slots[8].out_uop.fp_ctrl.div, slots_8.io.out_uop.fp_ctrl.div
connect issue_slots[8].out_uop.fp_ctrl.fma, slots_8.io.out_uop.fp_ctrl.fma
connect issue_slots[8].out_uop.fp_ctrl.fastpipe, slots_8.io.out_uop.fp_ctrl.fastpipe
connect issue_slots[8].out_uop.fp_ctrl.toint, slots_8.io.out_uop.fp_ctrl.toint
connect issue_slots[8].out_uop.fp_ctrl.fromint, slots_8.io.out_uop.fp_ctrl.fromint
connect issue_slots[8].out_uop.fp_ctrl.typeTagOut, slots_8.io.out_uop.fp_ctrl.typeTagOut
connect issue_slots[8].out_uop.fp_ctrl.typeTagIn, slots_8.io.out_uop.fp_ctrl.typeTagIn
connect issue_slots[8].out_uop.fp_ctrl.swap23, slots_8.io.out_uop.fp_ctrl.swap23
connect issue_slots[8].out_uop.fp_ctrl.swap12, slots_8.io.out_uop.fp_ctrl.swap12
connect issue_slots[8].out_uop.fp_ctrl.ren3, slots_8.io.out_uop.fp_ctrl.ren3
connect issue_slots[8].out_uop.fp_ctrl.ren2, slots_8.io.out_uop.fp_ctrl.ren2
connect issue_slots[8].out_uop.fp_ctrl.ren1, slots_8.io.out_uop.fp_ctrl.ren1
connect issue_slots[8].out_uop.fp_ctrl.wen, slots_8.io.out_uop.fp_ctrl.wen
connect issue_slots[8].out_uop.fp_ctrl.ldst, slots_8.io.out_uop.fp_ctrl.ldst
connect issue_slots[8].out_uop.op2_sel, slots_8.io.out_uop.op2_sel
connect issue_slots[8].out_uop.op1_sel, slots_8.io.out_uop.op1_sel
connect issue_slots[8].out_uop.imm_packed, slots_8.io.out_uop.imm_packed
connect issue_slots[8].out_uop.pimm, slots_8.io.out_uop.pimm
connect issue_slots[8].out_uop.imm_sel, slots_8.io.out_uop.imm_sel
connect issue_slots[8].out_uop.imm_rename, slots_8.io.out_uop.imm_rename
connect issue_slots[8].out_uop.taken, slots_8.io.out_uop.taken
connect issue_slots[8].out_uop.pc_lob, slots_8.io.out_uop.pc_lob
connect issue_slots[8].out_uop.edge_inst, slots_8.io.out_uop.edge_inst
connect issue_slots[8].out_uop.ftq_idx, slots_8.io.out_uop.ftq_idx
connect issue_slots[8].out_uop.is_mov, slots_8.io.out_uop.is_mov
connect issue_slots[8].out_uop.is_rocc, slots_8.io.out_uop.is_rocc
connect issue_slots[8].out_uop.is_sys_pc2epc, slots_8.io.out_uop.is_sys_pc2epc
connect issue_slots[8].out_uop.is_eret, slots_8.io.out_uop.is_eret
connect issue_slots[8].out_uop.is_amo, slots_8.io.out_uop.is_amo
connect issue_slots[8].out_uop.is_sfence, slots_8.io.out_uop.is_sfence
connect issue_slots[8].out_uop.is_fencei, slots_8.io.out_uop.is_fencei
connect issue_slots[8].out_uop.is_fence, slots_8.io.out_uop.is_fence
connect issue_slots[8].out_uop.is_sfb, slots_8.io.out_uop.is_sfb
connect issue_slots[8].out_uop.br_type, slots_8.io.out_uop.br_type
connect issue_slots[8].out_uop.br_tag, slots_8.io.out_uop.br_tag
connect issue_slots[8].out_uop.br_mask, slots_8.io.out_uop.br_mask
connect issue_slots[8].out_uop.dis_col_sel, slots_8.io.out_uop.dis_col_sel
connect issue_slots[8].out_uop.iw_p3_bypass_hint, slots_8.io.out_uop.iw_p3_bypass_hint
connect issue_slots[8].out_uop.iw_p2_bypass_hint, slots_8.io.out_uop.iw_p2_bypass_hint
connect issue_slots[8].out_uop.iw_p1_bypass_hint, slots_8.io.out_uop.iw_p1_bypass_hint
connect issue_slots[8].out_uop.iw_p2_speculative_child, slots_8.io.out_uop.iw_p2_speculative_child
connect issue_slots[8].out_uop.iw_p1_speculative_child, slots_8.io.out_uop.iw_p1_speculative_child
connect issue_slots[8].out_uop.iw_issued_partial_dgen, slots_8.io.out_uop.iw_issued_partial_dgen
connect issue_slots[8].out_uop.iw_issued_partial_agen, slots_8.io.out_uop.iw_issued_partial_agen
connect issue_slots[8].out_uop.iw_issued, slots_8.io.out_uop.iw_issued
connect issue_slots[8].out_uop.fu_code[0], slots_8.io.out_uop.fu_code[0]
connect issue_slots[8].out_uop.fu_code[1], slots_8.io.out_uop.fu_code[1]
connect issue_slots[8].out_uop.fu_code[2], slots_8.io.out_uop.fu_code[2]
connect issue_slots[8].out_uop.fu_code[3], slots_8.io.out_uop.fu_code[3]
connect issue_slots[8].out_uop.fu_code[4], slots_8.io.out_uop.fu_code[4]
connect issue_slots[8].out_uop.fu_code[5], slots_8.io.out_uop.fu_code[5]
connect issue_slots[8].out_uop.fu_code[6], slots_8.io.out_uop.fu_code[6]
connect issue_slots[8].out_uop.fu_code[7], slots_8.io.out_uop.fu_code[7]
connect issue_slots[8].out_uop.fu_code[8], slots_8.io.out_uop.fu_code[8]
connect issue_slots[8].out_uop.fu_code[9], slots_8.io.out_uop.fu_code[9]
connect issue_slots[8].out_uop.iq_type[0], slots_8.io.out_uop.iq_type[0]
connect issue_slots[8].out_uop.iq_type[1], slots_8.io.out_uop.iq_type[1]
connect issue_slots[8].out_uop.iq_type[2], slots_8.io.out_uop.iq_type[2]
connect issue_slots[8].out_uop.iq_type[3], slots_8.io.out_uop.iq_type[3]
connect issue_slots[8].out_uop.debug_pc, slots_8.io.out_uop.debug_pc
connect issue_slots[8].out_uop.is_rvc, slots_8.io.out_uop.is_rvc
connect issue_slots[8].out_uop.debug_inst, slots_8.io.out_uop.debug_inst
connect issue_slots[8].out_uop.inst, slots_8.io.out_uop.inst
connect slots_8.io.in_uop.bits.debug_tsrc, issue_slots[8].in_uop.bits.debug_tsrc
connect slots_8.io.in_uop.bits.debug_fsrc, issue_slots[8].in_uop.bits.debug_fsrc
connect slots_8.io.in_uop.bits.bp_xcpt_if, issue_slots[8].in_uop.bits.bp_xcpt_if
connect slots_8.io.in_uop.bits.bp_debug_if, issue_slots[8].in_uop.bits.bp_debug_if
connect slots_8.io.in_uop.bits.xcpt_ma_if, issue_slots[8].in_uop.bits.xcpt_ma_if
connect slots_8.io.in_uop.bits.xcpt_ae_if, issue_slots[8].in_uop.bits.xcpt_ae_if
connect slots_8.io.in_uop.bits.xcpt_pf_if, issue_slots[8].in_uop.bits.xcpt_pf_if
connect slots_8.io.in_uop.bits.fp_typ, issue_slots[8].in_uop.bits.fp_typ
connect slots_8.io.in_uop.bits.fp_rm, issue_slots[8].in_uop.bits.fp_rm
connect slots_8.io.in_uop.bits.fp_val, issue_slots[8].in_uop.bits.fp_val
connect slots_8.io.in_uop.bits.fcn_op, issue_slots[8].in_uop.bits.fcn_op
connect slots_8.io.in_uop.bits.fcn_dw, issue_slots[8].in_uop.bits.fcn_dw
connect slots_8.io.in_uop.bits.frs3_en, issue_slots[8].in_uop.bits.frs3_en
connect slots_8.io.in_uop.bits.lrs2_rtype, issue_slots[8].in_uop.bits.lrs2_rtype
connect slots_8.io.in_uop.bits.lrs1_rtype, issue_slots[8].in_uop.bits.lrs1_rtype
connect slots_8.io.in_uop.bits.dst_rtype, issue_slots[8].in_uop.bits.dst_rtype
connect slots_8.io.in_uop.bits.lrs3, issue_slots[8].in_uop.bits.lrs3
connect slots_8.io.in_uop.bits.lrs2, issue_slots[8].in_uop.bits.lrs2
connect slots_8.io.in_uop.bits.lrs1, issue_slots[8].in_uop.bits.lrs1
connect slots_8.io.in_uop.bits.ldst, issue_slots[8].in_uop.bits.ldst
connect slots_8.io.in_uop.bits.ldst_is_rs1, issue_slots[8].in_uop.bits.ldst_is_rs1
connect slots_8.io.in_uop.bits.csr_cmd, issue_slots[8].in_uop.bits.csr_cmd
connect slots_8.io.in_uop.bits.flush_on_commit, issue_slots[8].in_uop.bits.flush_on_commit
connect slots_8.io.in_uop.bits.is_unique, issue_slots[8].in_uop.bits.is_unique
connect slots_8.io.in_uop.bits.uses_stq, issue_slots[8].in_uop.bits.uses_stq
connect slots_8.io.in_uop.bits.uses_ldq, issue_slots[8].in_uop.bits.uses_ldq
connect slots_8.io.in_uop.bits.mem_signed, issue_slots[8].in_uop.bits.mem_signed
connect slots_8.io.in_uop.bits.mem_size, issue_slots[8].in_uop.bits.mem_size
connect slots_8.io.in_uop.bits.mem_cmd, issue_slots[8].in_uop.bits.mem_cmd
connect slots_8.io.in_uop.bits.exc_cause, issue_slots[8].in_uop.bits.exc_cause
connect slots_8.io.in_uop.bits.exception, issue_slots[8].in_uop.bits.exception
connect slots_8.io.in_uop.bits.stale_pdst, issue_slots[8].in_uop.bits.stale_pdst
connect slots_8.io.in_uop.bits.ppred_busy, issue_slots[8].in_uop.bits.ppred_busy
connect slots_8.io.in_uop.bits.prs3_busy, issue_slots[8].in_uop.bits.prs3_busy
connect slots_8.io.in_uop.bits.prs2_busy, issue_slots[8].in_uop.bits.prs2_busy
connect slots_8.io.in_uop.bits.prs1_busy, issue_slots[8].in_uop.bits.prs1_busy
connect slots_8.io.in_uop.bits.ppred, issue_slots[8].in_uop.bits.ppred
connect slots_8.io.in_uop.bits.prs3, issue_slots[8].in_uop.bits.prs3
connect slots_8.io.in_uop.bits.prs2, issue_slots[8].in_uop.bits.prs2
connect slots_8.io.in_uop.bits.prs1, issue_slots[8].in_uop.bits.prs1
connect slots_8.io.in_uop.bits.pdst, issue_slots[8].in_uop.bits.pdst
connect slots_8.io.in_uop.bits.rxq_idx, issue_slots[8].in_uop.bits.rxq_idx
connect slots_8.io.in_uop.bits.stq_idx, issue_slots[8].in_uop.bits.stq_idx
connect slots_8.io.in_uop.bits.ldq_idx, issue_slots[8].in_uop.bits.ldq_idx
connect slots_8.io.in_uop.bits.rob_idx, issue_slots[8].in_uop.bits.rob_idx
connect slots_8.io.in_uop.bits.fp_ctrl.vec, issue_slots[8].in_uop.bits.fp_ctrl.vec
connect slots_8.io.in_uop.bits.fp_ctrl.wflags, issue_slots[8].in_uop.bits.fp_ctrl.wflags
connect slots_8.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[8].in_uop.bits.fp_ctrl.sqrt
connect slots_8.io.in_uop.bits.fp_ctrl.div, issue_slots[8].in_uop.bits.fp_ctrl.div
connect slots_8.io.in_uop.bits.fp_ctrl.fma, issue_slots[8].in_uop.bits.fp_ctrl.fma
connect slots_8.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[8].in_uop.bits.fp_ctrl.fastpipe
connect slots_8.io.in_uop.bits.fp_ctrl.toint, issue_slots[8].in_uop.bits.fp_ctrl.toint
connect slots_8.io.in_uop.bits.fp_ctrl.fromint, issue_slots[8].in_uop.bits.fp_ctrl.fromint
connect slots_8.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[8].in_uop.bits.fp_ctrl.typeTagOut
connect slots_8.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[8].in_uop.bits.fp_ctrl.typeTagIn
connect slots_8.io.in_uop.bits.fp_ctrl.swap23, issue_slots[8].in_uop.bits.fp_ctrl.swap23
connect slots_8.io.in_uop.bits.fp_ctrl.swap12, issue_slots[8].in_uop.bits.fp_ctrl.swap12
connect slots_8.io.in_uop.bits.fp_ctrl.ren3, issue_slots[8].in_uop.bits.fp_ctrl.ren3
connect slots_8.io.in_uop.bits.fp_ctrl.ren2, issue_slots[8].in_uop.bits.fp_ctrl.ren2
connect slots_8.io.in_uop.bits.fp_ctrl.ren1, issue_slots[8].in_uop.bits.fp_ctrl.ren1
connect slots_8.io.in_uop.bits.fp_ctrl.wen, issue_slots[8].in_uop.bits.fp_ctrl.wen
connect slots_8.io.in_uop.bits.fp_ctrl.ldst, issue_slots[8].in_uop.bits.fp_ctrl.ldst
connect slots_8.io.in_uop.bits.op2_sel, issue_slots[8].in_uop.bits.op2_sel
connect slots_8.io.in_uop.bits.op1_sel, issue_slots[8].in_uop.bits.op1_sel
connect slots_8.io.in_uop.bits.imm_packed, issue_slots[8].in_uop.bits.imm_packed
connect slots_8.io.in_uop.bits.pimm, issue_slots[8].in_uop.bits.pimm
connect slots_8.io.in_uop.bits.imm_sel, issue_slots[8].in_uop.bits.imm_sel
connect slots_8.io.in_uop.bits.imm_rename, issue_slots[8].in_uop.bits.imm_rename
connect slots_8.io.in_uop.bits.taken, issue_slots[8].in_uop.bits.taken
connect slots_8.io.in_uop.bits.pc_lob, issue_slots[8].in_uop.bits.pc_lob
connect slots_8.io.in_uop.bits.edge_inst, issue_slots[8].in_uop.bits.edge_inst
connect slots_8.io.in_uop.bits.ftq_idx, issue_slots[8].in_uop.bits.ftq_idx
connect slots_8.io.in_uop.bits.is_mov, issue_slots[8].in_uop.bits.is_mov
connect slots_8.io.in_uop.bits.is_rocc, issue_slots[8].in_uop.bits.is_rocc
connect slots_8.io.in_uop.bits.is_sys_pc2epc, issue_slots[8].in_uop.bits.is_sys_pc2epc
connect slots_8.io.in_uop.bits.is_eret, issue_slots[8].in_uop.bits.is_eret
connect slots_8.io.in_uop.bits.is_amo, issue_slots[8].in_uop.bits.is_amo
connect slots_8.io.in_uop.bits.is_sfence, issue_slots[8].in_uop.bits.is_sfence
connect slots_8.io.in_uop.bits.is_fencei, issue_slots[8].in_uop.bits.is_fencei
connect slots_8.io.in_uop.bits.is_fence, issue_slots[8].in_uop.bits.is_fence
connect slots_8.io.in_uop.bits.is_sfb, issue_slots[8].in_uop.bits.is_sfb
connect slots_8.io.in_uop.bits.br_type, issue_slots[8].in_uop.bits.br_type
connect slots_8.io.in_uop.bits.br_tag, issue_slots[8].in_uop.bits.br_tag
connect slots_8.io.in_uop.bits.br_mask, issue_slots[8].in_uop.bits.br_mask
connect slots_8.io.in_uop.bits.dis_col_sel, issue_slots[8].in_uop.bits.dis_col_sel
connect slots_8.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[8].in_uop.bits.iw_p3_bypass_hint
connect slots_8.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[8].in_uop.bits.iw_p2_bypass_hint
connect slots_8.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[8].in_uop.bits.iw_p1_bypass_hint
connect slots_8.io.in_uop.bits.iw_p2_speculative_child, issue_slots[8].in_uop.bits.iw_p2_speculative_child
connect slots_8.io.in_uop.bits.iw_p1_speculative_child, issue_slots[8].in_uop.bits.iw_p1_speculative_child
connect slots_8.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[8].in_uop.bits.iw_issued_partial_dgen
connect slots_8.io.in_uop.bits.iw_issued_partial_agen, issue_slots[8].in_uop.bits.iw_issued_partial_agen
connect slots_8.io.in_uop.bits.iw_issued, issue_slots[8].in_uop.bits.iw_issued
connect slots_8.io.in_uop.bits.fu_code[0], issue_slots[8].in_uop.bits.fu_code[0]
connect slots_8.io.in_uop.bits.fu_code[1], issue_slots[8].in_uop.bits.fu_code[1]
connect slots_8.io.in_uop.bits.fu_code[2], issue_slots[8].in_uop.bits.fu_code[2]
connect slots_8.io.in_uop.bits.fu_code[3], issue_slots[8].in_uop.bits.fu_code[3]
connect slots_8.io.in_uop.bits.fu_code[4], issue_slots[8].in_uop.bits.fu_code[4]
connect slots_8.io.in_uop.bits.fu_code[5], issue_slots[8].in_uop.bits.fu_code[5]
connect slots_8.io.in_uop.bits.fu_code[6], issue_slots[8].in_uop.bits.fu_code[6]
connect slots_8.io.in_uop.bits.fu_code[7], issue_slots[8].in_uop.bits.fu_code[7]
connect slots_8.io.in_uop.bits.fu_code[8], issue_slots[8].in_uop.bits.fu_code[8]
connect slots_8.io.in_uop.bits.fu_code[9], issue_slots[8].in_uop.bits.fu_code[9]
connect slots_8.io.in_uop.bits.iq_type[0], issue_slots[8].in_uop.bits.iq_type[0]
connect slots_8.io.in_uop.bits.iq_type[1], issue_slots[8].in_uop.bits.iq_type[1]
connect slots_8.io.in_uop.bits.iq_type[2], issue_slots[8].in_uop.bits.iq_type[2]
connect slots_8.io.in_uop.bits.iq_type[3], issue_slots[8].in_uop.bits.iq_type[3]
connect slots_8.io.in_uop.bits.debug_pc, issue_slots[8].in_uop.bits.debug_pc
connect slots_8.io.in_uop.bits.is_rvc, issue_slots[8].in_uop.bits.is_rvc
connect slots_8.io.in_uop.bits.debug_inst, issue_slots[8].in_uop.bits.debug_inst
connect slots_8.io.in_uop.bits.inst, issue_slots[8].in_uop.bits.inst
connect slots_8.io.in_uop.valid, issue_slots[8].in_uop.valid
connect issue_slots[8].iss_uop.debug_tsrc, slots_8.io.iss_uop.debug_tsrc
connect issue_slots[8].iss_uop.debug_fsrc, slots_8.io.iss_uop.debug_fsrc
connect issue_slots[8].iss_uop.bp_xcpt_if, slots_8.io.iss_uop.bp_xcpt_if
connect issue_slots[8].iss_uop.bp_debug_if, slots_8.io.iss_uop.bp_debug_if
connect issue_slots[8].iss_uop.xcpt_ma_if, slots_8.io.iss_uop.xcpt_ma_if
connect issue_slots[8].iss_uop.xcpt_ae_if, slots_8.io.iss_uop.xcpt_ae_if
connect issue_slots[8].iss_uop.xcpt_pf_if, slots_8.io.iss_uop.xcpt_pf_if
connect issue_slots[8].iss_uop.fp_typ, slots_8.io.iss_uop.fp_typ
connect issue_slots[8].iss_uop.fp_rm, slots_8.io.iss_uop.fp_rm
connect issue_slots[8].iss_uop.fp_val, slots_8.io.iss_uop.fp_val
connect issue_slots[8].iss_uop.fcn_op, slots_8.io.iss_uop.fcn_op
connect issue_slots[8].iss_uop.fcn_dw, slots_8.io.iss_uop.fcn_dw
connect issue_slots[8].iss_uop.frs3_en, slots_8.io.iss_uop.frs3_en
connect issue_slots[8].iss_uop.lrs2_rtype, slots_8.io.iss_uop.lrs2_rtype
connect issue_slots[8].iss_uop.lrs1_rtype, slots_8.io.iss_uop.lrs1_rtype
connect issue_slots[8].iss_uop.dst_rtype, slots_8.io.iss_uop.dst_rtype
connect issue_slots[8].iss_uop.lrs3, slots_8.io.iss_uop.lrs3
connect issue_slots[8].iss_uop.lrs2, slots_8.io.iss_uop.lrs2
connect issue_slots[8].iss_uop.lrs1, slots_8.io.iss_uop.lrs1
connect issue_slots[8].iss_uop.ldst, slots_8.io.iss_uop.ldst
connect issue_slots[8].iss_uop.ldst_is_rs1, slots_8.io.iss_uop.ldst_is_rs1
connect issue_slots[8].iss_uop.csr_cmd, slots_8.io.iss_uop.csr_cmd
connect issue_slots[8].iss_uop.flush_on_commit, slots_8.io.iss_uop.flush_on_commit
connect issue_slots[8].iss_uop.is_unique, slots_8.io.iss_uop.is_unique
connect issue_slots[8].iss_uop.uses_stq, slots_8.io.iss_uop.uses_stq
connect issue_slots[8].iss_uop.uses_ldq, slots_8.io.iss_uop.uses_ldq
connect issue_slots[8].iss_uop.mem_signed, slots_8.io.iss_uop.mem_signed
connect issue_slots[8].iss_uop.mem_size, slots_8.io.iss_uop.mem_size
connect issue_slots[8].iss_uop.mem_cmd, slots_8.io.iss_uop.mem_cmd
connect issue_slots[8].iss_uop.exc_cause, slots_8.io.iss_uop.exc_cause
connect issue_slots[8].iss_uop.exception, slots_8.io.iss_uop.exception
connect issue_slots[8].iss_uop.stale_pdst, slots_8.io.iss_uop.stale_pdst
connect issue_slots[8].iss_uop.ppred_busy, slots_8.io.iss_uop.ppred_busy
connect issue_slots[8].iss_uop.prs3_busy, slots_8.io.iss_uop.prs3_busy
connect issue_slots[8].iss_uop.prs2_busy, slots_8.io.iss_uop.prs2_busy
connect issue_slots[8].iss_uop.prs1_busy, slots_8.io.iss_uop.prs1_busy
connect issue_slots[8].iss_uop.ppred, slots_8.io.iss_uop.ppred
connect issue_slots[8].iss_uop.prs3, slots_8.io.iss_uop.prs3
connect issue_slots[8].iss_uop.prs2, slots_8.io.iss_uop.prs2
connect issue_slots[8].iss_uop.prs1, slots_8.io.iss_uop.prs1
connect issue_slots[8].iss_uop.pdst, slots_8.io.iss_uop.pdst
connect issue_slots[8].iss_uop.rxq_idx, slots_8.io.iss_uop.rxq_idx
connect issue_slots[8].iss_uop.stq_idx, slots_8.io.iss_uop.stq_idx
connect issue_slots[8].iss_uop.ldq_idx, slots_8.io.iss_uop.ldq_idx
connect issue_slots[8].iss_uop.rob_idx, slots_8.io.iss_uop.rob_idx
connect issue_slots[8].iss_uop.fp_ctrl.vec, slots_8.io.iss_uop.fp_ctrl.vec
connect issue_slots[8].iss_uop.fp_ctrl.wflags, slots_8.io.iss_uop.fp_ctrl.wflags
connect issue_slots[8].iss_uop.fp_ctrl.sqrt, slots_8.io.iss_uop.fp_ctrl.sqrt
connect issue_slots[8].iss_uop.fp_ctrl.div, slots_8.io.iss_uop.fp_ctrl.div
connect issue_slots[8].iss_uop.fp_ctrl.fma, slots_8.io.iss_uop.fp_ctrl.fma
connect issue_slots[8].iss_uop.fp_ctrl.fastpipe, slots_8.io.iss_uop.fp_ctrl.fastpipe
connect issue_slots[8].iss_uop.fp_ctrl.toint, slots_8.io.iss_uop.fp_ctrl.toint
connect issue_slots[8].iss_uop.fp_ctrl.fromint, slots_8.io.iss_uop.fp_ctrl.fromint
connect issue_slots[8].iss_uop.fp_ctrl.typeTagOut, slots_8.io.iss_uop.fp_ctrl.typeTagOut
connect issue_slots[8].iss_uop.fp_ctrl.typeTagIn, slots_8.io.iss_uop.fp_ctrl.typeTagIn
connect issue_slots[8].iss_uop.fp_ctrl.swap23, slots_8.io.iss_uop.fp_ctrl.swap23
connect issue_slots[8].iss_uop.fp_ctrl.swap12, slots_8.io.iss_uop.fp_ctrl.swap12
connect issue_slots[8].iss_uop.fp_ctrl.ren3, slots_8.io.iss_uop.fp_ctrl.ren3
connect issue_slots[8].iss_uop.fp_ctrl.ren2, slots_8.io.iss_uop.fp_ctrl.ren2
connect issue_slots[8].iss_uop.fp_ctrl.ren1, slots_8.io.iss_uop.fp_ctrl.ren1
connect issue_slots[8].iss_uop.fp_ctrl.wen, slots_8.io.iss_uop.fp_ctrl.wen
connect issue_slots[8].iss_uop.fp_ctrl.ldst, slots_8.io.iss_uop.fp_ctrl.ldst
connect issue_slots[8].iss_uop.op2_sel, slots_8.io.iss_uop.op2_sel
connect issue_slots[8].iss_uop.op1_sel, slots_8.io.iss_uop.op1_sel
connect issue_slots[8].iss_uop.imm_packed, slots_8.io.iss_uop.imm_packed
connect issue_slots[8].iss_uop.pimm, slots_8.io.iss_uop.pimm
connect issue_slots[8].iss_uop.imm_sel, slots_8.io.iss_uop.imm_sel
connect issue_slots[8].iss_uop.imm_rename, slots_8.io.iss_uop.imm_rename
connect issue_slots[8].iss_uop.taken, slots_8.io.iss_uop.taken
connect issue_slots[8].iss_uop.pc_lob, slots_8.io.iss_uop.pc_lob
connect issue_slots[8].iss_uop.edge_inst, slots_8.io.iss_uop.edge_inst
connect issue_slots[8].iss_uop.ftq_idx, slots_8.io.iss_uop.ftq_idx
connect issue_slots[8].iss_uop.is_mov, slots_8.io.iss_uop.is_mov
connect issue_slots[8].iss_uop.is_rocc, slots_8.io.iss_uop.is_rocc
connect issue_slots[8].iss_uop.is_sys_pc2epc, slots_8.io.iss_uop.is_sys_pc2epc
connect issue_slots[8].iss_uop.is_eret, slots_8.io.iss_uop.is_eret
connect issue_slots[8].iss_uop.is_amo, slots_8.io.iss_uop.is_amo
connect issue_slots[8].iss_uop.is_sfence, slots_8.io.iss_uop.is_sfence
connect issue_slots[8].iss_uop.is_fencei, slots_8.io.iss_uop.is_fencei
connect issue_slots[8].iss_uop.is_fence, slots_8.io.iss_uop.is_fence
connect issue_slots[8].iss_uop.is_sfb, slots_8.io.iss_uop.is_sfb
connect issue_slots[8].iss_uop.br_type, slots_8.io.iss_uop.br_type
connect issue_slots[8].iss_uop.br_tag, slots_8.io.iss_uop.br_tag
connect issue_slots[8].iss_uop.br_mask, slots_8.io.iss_uop.br_mask
connect issue_slots[8].iss_uop.dis_col_sel, slots_8.io.iss_uop.dis_col_sel
connect issue_slots[8].iss_uop.iw_p3_bypass_hint, slots_8.io.iss_uop.iw_p3_bypass_hint
connect issue_slots[8].iss_uop.iw_p2_bypass_hint, slots_8.io.iss_uop.iw_p2_bypass_hint
connect issue_slots[8].iss_uop.iw_p1_bypass_hint, slots_8.io.iss_uop.iw_p1_bypass_hint
connect issue_slots[8].iss_uop.iw_p2_speculative_child, slots_8.io.iss_uop.iw_p2_speculative_child
connect issue_slots[8].iss_uop.iw_p1_speculative_child, slots_8.io.iss_uop.iw_p1_speculative_child
connect issue_slots[8].iss_uop.iw_issued_partial_dgen, slots_8.io.iss_uop.iw_issued_partial_dgen
connect issue_slots[8].iss_uop.iw_issued_partial_agen, slots_8.io.iss_uop.iw_issued_partial_agen
connect issue_slots[8].iss_uop.iw_issued, slots_8.io.iss_uop.iw_issued
connect issue_slots[8].iss_uop.fu_code[0], slots_8.io.iss_uop.fu_code[0]
connect issue_slots[8].iss_uop.fu_code[1], slots_8.io.iss_uop.fu_code[1]
connect issue_slots[8].iss_uop.fu_code[2], slots_8.io.iss_uop.fu_code[2]
connect issue_slots[8].iss_uop.fu_code[3], slots_8.io.iss_uop.fu_code[3]
connect issue_slots[8].iss_uop.fu_code[4], slots_8.io.iss_uop.fu_code[4]
connect issue_slots[8].iss_uop.fu_code[5], slots_8.io.iss_uop.fu_code[5]
connect issue_slots[8].iss_uop.fu_code[6], slots_8.io.iss_uop.fu_code[6]
connect issue_slots[8].iss_uop.fu_code[7], slots_8.io.iss_uop.fu_code[7]
connect issue_slots[8].iss_uop.fu_code[8], slots_8.io.iss_uop.fu_code[8]
connect issue_slots[8].iss_uop.fu_code[9], slots_8.io.iss_uop.fu_code[9]
connect issue_slots[8].iss_uop.iq_type[0], slots_8.io.iss_uop.iq_type[0]
connect issue_slots[8].iss_uop.iq_type[1], slots_8.io.iss_uop.iq_type[1]
connect issue_slots[8].iss_uop.iq_type[2], slots_8.io.iss_uop.iq_type[2]
connect issue_slots[8].iss_uop.iq_type[3], slots_8.io.iss_uop.iq_type[3]
connect issue_slots[8].iss_uop.debug_pc, slots_8.io.iss_uop.debug_pc
connect issue_slots[8].iss_uop.is_rvc, slots_8.io.iss_uop.is_rvc
connect issue_slots[8].iss_uop.debug_inst, slots_8.io.iss_uop.debug_inst
connect issue_slots[8].iss_uop.inst, slots_8.io.iss_uop.inst
connect slots_8.io.grant, issue_slots[8].grant
connect issue_slots[8].request, slots_8.io.request
connect issue_slots[8].will_be_valid, slots_8.io.will_be_valid
connect issue_slots[8].valid, slots_8.io.valid
connect slots_9.io.child_rebusys, issue_slots[9].child_rebusys
connect slots_9.io.pred_wakeup_port.bits, issue_slots[9].pred_wakeup_port.bits
connect slots_9.io.pred_wakeup_port.valid, issue_slots[9].pred_wakeup_port.valid
connect slots_9.io.wakeup_ports[0].bits.rebusy, issue_slots[9].wakeup_ports[0].bits.rebusy
connect slots_9.io.wakeup_ports[0].bits.speculative_mask, issue_slots[9].wakeup_ports[0].bits.speculative_mask
connect slots_9.io.wakeup_ports[0].bits.bypassable, issue_slots[9].wakeup_ports[0].bits.bypassable
connect slots_9.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[9].wakeup_ports[0].bits.uop.debug_tsrc
connect slots_9.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[9].wakeup_ports[0].bits.uop.debug_fsrc
connect slots_9.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[9].wakeup_ports[0].bits.uop.bp_xcpt_if
connect slots_9.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[9].wakeup_ports[0].bits.uop.bp_debug_if
connect slots_9.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[9].wakeup_ports[0].bits.uop.xcpt_ma_if
connect slots_9.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[9].wakeup_ports[0].bits.uop.xcpt_ae_if
connect slots_9.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[9].wakeup_ports[0].bits.uop.xcpt_pf_if
connect slots_9.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[9].wakeup_ports[0].bits.uop.fp_typ
connect slots_9.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[9].wakeup_ports[0].bits.uop.fp_rm
connect slots_9.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[9].wakeup_ports[0].bits.uop.fp_val
connect slots_9.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[9].wakeup_ports[0].bits.uop.fcn_op
connect slots_9.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[9].wakeup_ports[0].bits.uop.fcn_dw
connect slots_9.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[9].wakeup_ports[0].bits.uop.frs3_en
connect slots_9.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[9].wakeup_ports[0].bits.uop.lrs2_rtype
connect slots_9.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[9].wakeup_ports[0].bits.uop.lrs1_rtype
connect slots_9.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[9].wakeup_ports[0].bits.uop.dst_rtype
connect slots_9.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[9].wakeup_ports[0].bits.uop.lrs3
connect slots_9.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[9].wakeup_ports[0].bits.uop.lrs2
connect slots_9.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[9].wakeup_ports[0].bits.uop.lrs1
connect slots_9.io.wakeup_ports[0].bits.uop.ldst, issue_slots[9].wakeup_ports[0].bits.uop.ldst
connect slots_9.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[9].wakeup_ports[0].bits.uop.ldst_is_rs1
connect slots_9.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[9].wakeup_ports[0].bits.uop.csr_cmd
connect slots_9.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[9].wakeup_ports[0].bits.uop.flush_on_commit
connect slots_9.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[9].wakeup_ports[0].bits.uop.is_unique
connect slots_9.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[9].wakeup_ports[0].bits.uop.uses_stq
connect slots_9.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[9].wakeup_ports[0].bits.uop.uses_ldq
connect slots_9.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[9].wakeup_ports[0].bits.uop.mem_signed
connect slots_9.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[9].wakeup_ports[0].bits.uop.mem_size
connect slots_9.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[9].wakeup_ports[0].bits.uop.mem_cmd
connect slots_9.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[9].wakeup_ports[0].bits.uop.exc_cause
connect slots_9.io.wakeup_ports[0].bits.uop.exception, issue_slots[9].wakeup_ports[0].bits.uop.exception
connect slots_9.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[9].wakeup_ports[0].bits.uop.stale_pdst
connect slots_9.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[9].wakeup_ports[0].bits.uop.ppred_busy
connect slots_9.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[9].wakeup_ports[0].bits.uop.prs3_busy
connect slots_9.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[9].wakeup_ports[0].bits.uop.prs2_busy
connect slots_9.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[9].wakeup_ports[0].bits.uop.prs1_busy
connect slots_9.io.wakeup_ports[0].bits.uop.ppred, issue_slots[9].wakeup_ports[0].bits.uop.ppred
connect slots_9.io.wakeup_ports[0].bits.uop.prs3, issue_slots[9].wakeup_ports[0].bits.uop.prs3
connect slots_9.io.wakeup_ports[0].bits.uop.prs2, issue_slots[9].wakeup_ports[0].bits.uop.prs2
connect slots_9.io.wakeup_ports[0].bits.uop.prs1, issue_slots[9].wakeup_ports[0].bits.uop.prs1
connect slots_9.io.wakeup_ports[0].bits.uop.pdst, issue_slots[9].wakeup_ports[0].bits.uop.pdst
connect slots_9.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[9].wakeup_ports[0].bits.uop.rxq_idx
connect slots_9.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[9].wakeup_ports[0].bits.uop.stq_idx
connect slots_9.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[9].wakeup_ports[0].bits.uop.ldq_idx
connect slots_9.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[9].wakeup_ports[0].bits.uop.rob_idx
connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.vec
connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.wflags
connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.sqrt
connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.div
connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.fma
connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe
connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.toint
connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.fromint
connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut
connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn
connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.swap23
connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.swap12
connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.ren3
connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.ren2
connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.ren1
connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.wen
connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.ldst
connect slots_9.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[9].wakeup_ports[0].bits.uop.op2_sel
connect slots_9.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[9].wakeup_ports[0].bits.uop.op1_sel
connect slots_9.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[9].wakeup_ports[0].bits.uop.imm_packed
connect slots_9.io.wakeup_ports[0].bits.uop.pimm, issue_slots[9].wakeup_ports[0].bits.uop.pimm
connect slots_9.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[9].wakeup_ports[0].bits.uop.imm_sel
connect slots_9.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[9].wakeup_ports[0].bits.uop.imm_rename
connect slots_9.io.wakeup_ports[0].bits.uop.taken, issue_slots[9].wakeup_ports[0].bits.uop.taken
connect slots_9.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[9].wakeup_ports[0].bits.uop.pc_lob
connect slots_9.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[9].wakeup_ports[0].bits.uop.edge_inst
connect slots_9.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[9].wakeup_ports[0].bits.uop.ftq_idx
connect slots_9.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[9].wakeup_ports[0].bits.uop.is_mov
connect slots_9.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[9].wakeup_ports[0].bits.uop.is_rocc
connect slots_9.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[9].wakeup_ports[0].bits.uop.is_sys_pc2epc
connect slots_9.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[9].wakeup_ports[0].bits.uop.is_eret
connect slots_9.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[9].wakeup_ports[0].bits.uop.is_amo
connect slots_9.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[9].wakeup_ports[0].bits.uop.is_sfence
connect slots_9.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[9].wakeup_ports[0].bits.uop.is_fencei
connect slots_9.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[9].wakeup_ports[0].bits.uop.is_fence
connect slots_9.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[9].wakeup_ports[0].bits.uop.is_sfb
connect slots_9.io.wakeup_ports[0].bits.uop.br_type, issue_slots[9].wakeup_ports[0].bits.uop.br_type
connect slots_9.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[9].wakeup_ports[0].bits.uop.br_tag
connect slots_9.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[9].wakeup_ports[0].bits.uop.br_mask
connect slots_9.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[9].wakeup_ports[0].bits.uop.dis_col_sel
connect slots_9.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[9].wakeup_ports[0].bits.uop.iw_p3_bypass_hint
connect slots_9.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[9].wakeup_ports[0].bits.uop.iw_p2_bypass_hint
connect slots_9.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[9].wakeup_ports[0].bits.uop.iw_p1_bypass_hint
connect slots_9.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[9].wakeup_ports[0].bits.uop.iw_p2_speculative_child
connect slots_9.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[9].wakeup_ports[0].bits.uop.iw_p1_speculative_child
connect slots_9.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[9].wakeup_ports[0].bits.uop.iw_issued_partial_dgen
connect slots_9.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[9].wakeup_ports[0].bits.uop.iw_issued_partial_agen
connect slots_9.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[9].wakeup_ports[0].bits.uop.iw_issued
connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[0]
connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[1]
connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[2]
connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[3]
connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[4]
connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[5]
connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[6]
connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[7]
connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[8]
connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[9]
connect slots_9.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[9].wakeup_ports[0].bits.uop.iq_type[0]
connect slots_9.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[9].wakeup_ports[0].bits.uop.iq_type[1]
connect slots_9.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[9].wakeup_ports[0].bits.uop.iq_type[2]
connect slots_9.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[9].wakeup_ports[0].bits.uop.iq_type[3]
connect slots_9.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[9].wakeup_ports[0].bits.uop.debug_pc
connect slots_9.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[9].wakeup_ports[0].bits.uop.is_rvc
connect slots_9.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[9].wakeup_ports[0].bits.uop.debug_inst
connect slots_9.io.wakeup_ports[0].bits.uop.inst, issue_slots[9].wakeup_ports[0].bits.uop.inst
connect slots_9.io.wakeup_ports[0].valid, issue_slots[9].wakeup_ports[0].valid
connect slots_9.io.wakeup_ports[1].bits.rebusy, issue_slots[9].wakeup_ports[1].bits.rebusy
connect slots_9.io.wakeup_ports[1].bits.speculative_mask, issue_slots[9].wakeup_ports[1].bits.speculative_mask
connect slots_9.io.wakeup_ports[1].bits.bypassable, issue_slots[9].wakeup_ports[1].bits.bypassable
connect slots_9.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[9].wakeup_ports[1].bits.uop.debug_tsrc
connect slots_9.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[9].wakeup_ports[1].bits.uop.debug_fsrc
connect slots_9.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[9].wakeup_ports[1].bits.uop.bp_xcpt_if
connect slots_9.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[9].wakeup_ports[1].bits.uop.bp_debug_if
connect slots_9.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[9].wakeup_ports[1].bits.uop.xcpt_ma_if
connect slots_9.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[9].wakeup_ports[1].bits.uop.xcpt_ae_if
connect slots_9.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[9].wakeup_ports[1].bits.uop.xcpt_pf_if
connect slots_9.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[9].wakeup_ports[1].bits.uop.fp_typ
connect slots_9.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[9].wakeup_ports[1].bits.uop.fp_rm
connect slots_9.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[9].wakeup_ports[1].bits.uop.fp_val
connect slots_9.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[9].wakeup_ports[1].bits.uop.fcn_op
connect slots_9.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[9].wakeup_ports[1].bits.uop.fcn_dw
connect slots_9.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[9].wakeup_ports[1].bits.uop.frs3_en
connect slots_9.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[9].wakeup_ports[1].bits.uop.lrs2_rtype
connect slots_9.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[9].wakeup_ports[1].bits.uop.lrs1_rtype
connect slots_9.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[9].wakeup_ports[1].bits.uop.dst_rtype
connect slots_9.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[9].wakeup_ports[1].bits.uop.lrs3
connect slots_9.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[9].wakeup_ports[1].bits.uop.lrs2
connect slots_9.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[9].wakeup_ports[1].bits.uop.lrs1
connect slots_9.io.wakeup_ports[1].bits.uop.ldst, issue_slots[9].wakeup_ports[1].bits.uop.ldst
connect slots_9.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[9].wakeup_ports[1].bits.uop.ldst_is_rs1
connect slots_9.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[9].wakeup_ports[1].bits.uop.csr_cmd
connect slots_9.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[9].wakeup_ports[1].bits.uop.flush_on_commit
connect slots_9.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[9].wakeup_ports[1].bits.uop.is_unique
connect slots_9.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[9].wakeup_ports[1].bits.uop.uses_stq
connect slots_9.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[9].wakeup_ports[1].bits.uop.uses_ldq
connect slots_9.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[9].wakeup_ports[1].bits.uop.mem_signed
connect slots_9.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[9].wakeup_ports[1].bits.uop.mem_size
connect slots_9.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[9].wakeup_ports[1].bits.uop.mem_cmd
connect slots_9.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[9].wakeup_ports[1].bits.uop.exc_cause
connect slots_9.io.wakeup_ports[1].bits.uop.exception, issue_slots[9].wakeup_ports[1].bits.uop.exception
connect slots_9.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[9].wakeup_ports[1].bits.uop.stale_pdst
connect slots_9.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[9].wakeup_ports[1].bits.uop.ppred_busy
connect slots_9.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[9].wakeup_ports[1].bits.uop.prs3_busy
connect slots_9.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[9].wakeup_ports[1].bits.uop.prs2_busy
connect slots_9.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[9].wakeup_ports[1].bits.uop.prs1_busy
connect slots_9.io.wakeup_ports[1].bits.uop.ppred, issue_slots[9].wakeup_ports[1].bits.uop.ppred
connect slots_9.io.wakeup_ports[1].bits.uop.prs3, issue_slots[9].wakeup_ports[1].bits.uop.prs3
connect slots_9.io.wakeup_ports[1].bits.uop.prs2, issue_slots[9].wakeup_ports[1].bits.uop.prs2
connect slots_9.io.wakeup_ports[1].bits.uop.prs1, issue_slots[9].wakeup_ports[1].bits.uop.prs1
connect slots_9.io.wakeup_ports[1].bits.uop.pdst, issue_slots[9].wakeup_ports[1].bits.uop.pdst
connect slots_9.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[9].wakeup_ports[1].bits.uop.rxq_idx
connect slots_9.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[9].wakeup_ports[1].bits.uop.stq_idx
connect slots_9.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[9].wakeup_ports[1].bits.uop.ldq_idx
connect slots_9.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[9].wakeup_ports[1].bits.uop.rob_idx
connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.vec
connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.wflags
connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.sqrt
connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.div
connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.fma
connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe
connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.toint
connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.fromint
connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut
connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn
connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.swap23
connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.swap12
connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.ren3
connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.ren2
connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.ren1
connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.wen
connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.ldst
connect slots_9.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[9].wakeup_ports[1].bits.uop.op2_sel
connect slots_9.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[9].wakeup_ports[1].bits.uop.op1_sel
connect slots_9.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[9].wakeup_ports[1].bits.uop.imm_packed
connect slots_9.io.wakeup_ports[1].bits.uop.pimm, issue_slots[9].wakeup_ports[1].bits.uop.pimm
connect slots_9.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[9].wakeup_ports[1].bits.uop.imm_sel
connect slots_9.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[9].wakeup_ports[1].bits.uop.imm_rename
connect slots_9.io.wakeup_ports[1].bits.uop.taken, issue_slots[9].wakeup_ports[1].bits.uop.taken
connect slots_9.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[9].wakeup_ports[1].bits.uop.pc_lob
connect slots_9.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[9].wakeup_ports[1].bits.uop.edge_inst
connect slots_9.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[9].wakeup_ports[1].bits.uop.ftq_idx
connect slots_9.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[9].wakeup_ports[1].bits.uop.is_mov
connect slots_9.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[9].wakeup_ports[1].bits.uop.is_rocc
connect slots_9.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[9].wakeup_ports[1].bits.uop.is_sys_pc2epc
connect slots_9.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[9].wakeup_ports[1].bits.uop.is_eret
connect slots_9.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[9].wakeup_ports[1].bits.uop.is_amo
connect slots_9.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[9].wakeup_ports[1].bits.uop.is_sfence
connect slots_9.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[9].wakeup_ports[1].bits.uop.is_fencei
connect slots_9.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[9].wakeup_ports[1].bits.uop.is_fence
connect slots_9.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[9].wakeup_ports[1].bits.uop.is_sfb
connect slots_9.io.wakeup_ports[1].bits.uop.br_type, issue_slots[9].wakeup_ports[1].bits.uop.br_type
connect slots_9.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[9].wakeup_ports[1].bits.uop.br_tag
connect slots_9.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[9].wakeup_ports[1].bits.uop.br_mask
connect slots_9.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[9].wakeup_ports[1].bits.uop.dis_col_sel
connect slots_9.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[9].wakeup_ports[1].bits.uop.iw_p3_bypass_hint
connect slots_9.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[9].wakeup_ports[1].bits.uop.iw_p2_bypass_hint
connect slots_9.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[9].wakeup_ports[1].bits.uop.iw_p1_bypass_hint
connect slots_9.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[9].wakeup_ports[1].bits.uop.iw_p2_speculative_child
connect slots_9.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[9].wakeup_ports[1].bits.uop.iw_p1_speculative_child
connect slots_9.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[9].wakeup_ports[1].bits.uop.iw_issued_partial_dgen
connect slots_9.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[9].wakeup_ports[1].bits.uop.iw_issued_partial_agen
connect slots_9.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[9].wakeup_ports[1].bits.uop.iw_issued
connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[0]
connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[1]
connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[2]
connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[3]
connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[4]
connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[5]
connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[6]
connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[7]
connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[8]
connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[9]
connect slots_9.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[9].wakeup_ports[1].bits.uop.iq_type[0]
connect slots_9.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[9].wakeup_ports[1].bits.uop.iq_type[1]
connect slots_9.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[9].wakeup_ports[1].bits.uop.iq_type[2]
connect slots_9.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[9].wakeup_ports[1].bits.uop.iq_type[3]
connect slots_9.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[9].wakeup_ports[1].bits.uop.debug_pc
connect slots_9.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[9].wakeup_ports[1].bits.uop.is_rvc
connect slots_9.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[9].wakeup_ports[1].bits.uop.debug_inst
connect slots_9.io.wakeup_ports[1].bits.uop.inst, issue_slots[9].wakeup_ports[1].bits.uop.inst
connect slots_9.io.wakeup_ports[1].valid, issue_slots[9].wakeup_ports[1].valid
connect slots_9.io.wakeup_ports[2].bits.rebusy, issue_slots[9].wakeup_ports[2].bits.rebusy
connect slots_9.io.wakeup_ports[2].bits.speculative_mask, issue_slots[9].wakeup_ports[2].bits.speculative_mask
connect slots_9.io.wakeup_ports[2].bits.bypassable, issue_slots[9].wakeup_ports[2].bits.bypassable
connect slots_9.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[9].wakeup_ports[2].bits.uop.debug_tsrc
connect slots_9.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[9].wakeup_ports[2].bits.uop.debug_fsrc
connect slots_9.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[9].wakeup_ports[2].bits.uop.bp_xcpt_if
connect slots_9.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[9].wakeup_ports[2].bits.uop.bp_debug_if
connect slots_9.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[9].wakeup_ports[2].bits.uop.xcpt_ma_if
connect slots_9.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[9].wakeup_ports[2].bits.uop.xcpt_ae_if
connect slots_9.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[9].wakeup_ports[2].bits.uop.xcpt_pf_if
connect slots_9.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[9].wakeup_ports[2].bits.uop.fp_typ
connect slots_9.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[9].wakeup_ports[2].bits.uop.fp_rm
connect slots_9.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[9].wakeup_ports[2].bits.uop.fp_val
connect slots_9.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[9].wakeup_ports[2].bits.uop.fcn_op
connect slots_9.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[9].wakeup_ports[2].bits.uop.fcn_dw
connect slots_9.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[9].wakeup_ports[2].bits.uop.frs3_en
connect slots_9.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[9].wakeup_ports[2].bits.uop.lrs2_rtype
connect slots_9.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[9].wakeup_ports[2].bits.uop.lrs1_rtype
connect slots_9.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[9].wakeup_ports[2].bits.uop.dst_rtype
connect slots_9.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[9].wakeup_ports[2].bits.uop.lrs3
connect slots_9.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[9].wakeup_ports[2].bits.uop.lrs2
connect slots_9.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[9].wakeup_ports[2].bits.uop.lrs1
connect slots_9.io.wakeup_ports[2].bits.uop.ldst, issue_slots[9].wakeup_ports[2].bits.uop.ldst
connect slots_9.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[9].wakeup_ports[2].bits.uop.ldst_is_rs1
connect slots_9.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[9].wakeup_ports[2].bits.uop.csr_cmd
connect slots_9.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[9].wakeup_ports[2].bits.uop.flush_on_commit
connect slots_9.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[9].wakeup_ports[2].bits.uop.is_unique
connect slots_9.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[9].wakeup_ports[2].bits.uop.uses_stq
connect slots_9.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[9].wakeup_ports[2].bits.uop.uses_ldq
connect slots_9.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[9].wakeup_ports[2].bits.uop.mem_signed
connect slots_9.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[9].wakeup_ports[2].bits.uop.mem_size
connect slots_9.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[9].wakeup_ports[2].bits.uop.mem_cmd
connect slots_9.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[9].wakeup_ports[2].bits.uop.exc_cause
connect slots_9.io.wakeup_ports[2].bits.uop.exception, issue_slots[9].wakeup_ports[2].bits.uop.exception
connect slots_9.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[9].wakeup_ports[2].bits.uop.stale_pdst
connect slots_9.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[9].wakeup_ports[2].bits.uop.ppred_busy
connect slots_9.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[9].wakeup_ports[2].bits.uop.prs3_busy
connect slots_9.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[9].wakeup_ports[2].bits.uop.prs2_busy
connect slots_9.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[9].wakeup_ports[2].bits.uop.prs1_busy
connect slots_9.io.wakeup_ports[2].bits.uop.ppred, issue_slots[9].wakeup_ports[2].bits.uop.ppred
connect slots_9.io.wakeup_ports[2].bits.uop.prs3, issue_slots[9].wakeup_ports[2].bits.uop.prs3
connect slots_9.io.wakeup_ports[2].bits.uop.prs2, issue_slots[9].wakeup_ports[2].bits.uop.prs2
connect slots_9.io.wakeup_ports[2].bits.uop.prs1, issue_slots[9].wakeup_ports[2].bits.uop.prs1
connect slots_9.io.wakeup_ports[2].bits.uop.pdst, issue_slots[9].wakeup_ports[2].bits.uop.pdst
connect slots_9.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[9].wakeup_ports[2].bits.uop.rxq_idx
connect slots_9.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[9].wakeup_ports[2].bits.uop.stq_idx
connect slots_9.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[9].wakeup_ports[2].bits.uop.ldq_idx
connect slots_9.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[9].wakeup_ports[2].bits.uop.rob_idx
connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.vec
connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.wflags
connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.sqrt
connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.div
connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.fma
connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe
connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.toint
connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.fromint
connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut
connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn
connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.swap23
connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.swap12
connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.ren3
connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.ren2
connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.ren1
connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.wen
connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.ldst
connect slots_9.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[9].wakeup_ports[2].bits.uop.op2_sel
connect slots_9.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[9].wakeup_ports[2].bits.uop.op1_sel
connect slots_9.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[9].wakeup_ports[2].bits.uop.imm_packed
connect slots_9.io.wakeup_ports[2].bits.uop.pimm, issue_slots[9].wakeup_ports[2].bits.uop.pimm
connect slots_9.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[9].wakeup_ports[2].bits.uop.imm_sel
connect slots_9.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[9].wakeup_ports[2].bits.uop.imm_rename
connect slots_9.io.wakeup_ports[2].bits.uop.taken, issue_slots[9].wakeup_ports[2].bits.uop.taken
connect slots_9.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[9].wakeup_ports[2].bits.uop.pc_lob
connect slots_9.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[9].wakeup_ports[2].bits.uop.edge_inst
connect slots_9.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[9].wakeup_ports[2].bits.uop.ftq_idx
connect slots_9.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[9].wakeup_ports[2].bits.uop.is_mov
connect slots_9.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[9].wakeup_ports[2].bits.uop.is_rocc
connect slots_9.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[9].wakeup_ports[2].bits.uop.is_sys_pc2epc
connect slots_9.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[9].wakeup_ports[2].bits.uop.is_eret
connect slots_9.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[9].wakeup_ports[2].bits.uop.is_amo
connect slots_9.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[9].wakeup_ports[2].bits.uop.is_sfence
connect slots_9.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[9].wakeup_ports[2].bits.uop.is_fencei
connect slots_9.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[9].wakeup_ports[2].bits.uop.is_fence
connect slots_9.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[9].wakeup_ports[2].bits.uop.is_sfb
connect slots_9.io.wakeup_ports[2].bits.uop.br_type, issue_slots[9].wakeup_ports[2].bits.uop.br_type
connect slots_9.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[9].wakeup_ports[2].bits.uop.br_tag
connect slots_9.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[9].wakeup_ports[2].bits.uop.br_mask
connect slots_9.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[9].wakeup_ports[2].bits.uop.dis_col_sel
connect slots_9.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[9].wakeup_ports[2].bits.uop.iw_p3_bypass_hint
connect slots_9.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[9].wakeup_ports[2].bits.uop.iw_p2_bypass_hint
connect slots_9.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[9].wakeup_ports[2].bits.uop.iw_p1_bypass_hint
connect slots_9.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[9].wakeup_ports[2].bits.uop.iw_p2_speculative_child
connect slots_9.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[9].wakeup_ports[2].bits.uop.iw_p1_speculative_child
connect slots_9.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[9].wakeup_ports[2].bits.uop.iw_issued_partial_dgen
connect slots_9.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[9].wakeup_ports[2].bits.uop.iw_issued_partial_agen
connect slots_9.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[9].wakeup_ports[2].bits.uop.iw_issued
connect slots_9.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[9].wakeup_ports[2].bits.uop.fu_code[0]
connect slots_9.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[9].wakeup_ports[2].bits.uop.fu_code[1]
connect slots_9.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[9].wakeup_ports[2].bits.uop.fu_code[2]
connect slots_9.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[9].wakeup_ports[2].bits.uop.fu_code[3]
connect slots_9.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[9].wakeup_ports[2].bits.uop.fu_code[4]
connect slots_9.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[9].wakeup_ports[2].bits.uop.fu_code[5]
connect slots_9.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[9].wakeup_ports[2].bits.uop.fu_code[6]
connect slots_9.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[9].wakeup_ports[2].bits.uop.fu_code[7]
connect slots_9.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[9].wakeup_ports[2].bits.uop.fu_code[8]
connect slots_9.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[9].wakeup_ports[2].bits.uop.fu_code[9]
connect slots_9.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[9].wakeup_ports[2].bits.uop.iq_type[0]
connect slots_9.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[9].wakeup_ports[2].bits.uop.iq_type[1]
connect slots_9.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[9].wakeup_ports[2].bits.uop.iq_type[2]
connect slots_9.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[9].wakeup_ports[2].bits.uop.iq_type[3]
connect slots_9.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[9].wakeup_ports[2].bits.uop.debug_pc
connect slots_9.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[9].wakeup_ports[2].bits.uop.is_rvc
connect slots_9.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[9].wakeup_ports[2].bits.uop.debug_inst
connect slots_9.io.wakeup_ports[2].bits.uop.inst, issue_slots[9].wakeup_ports[2].bits.uop.inst
connect slots_9.io.wakeup_ports[2].valid, issue_slots[9].wakeup_ports[2].valid
connect slots_9.io.wakeup_ports[3].bits.rebusy, issue_slots[9].wakeup_ports[3].bits.rebusy
connect slots_9.io.wakeup_ports[3].bits.speculative_mask, issue_slots[9].wakeup_ports[3].bits.speculative_mask
connect slots_9.io.wakeup_ports[3].bits.bypassable, issue_slots[9].wakeup_ports[3].bits.bypassable
connect slots_9.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[9].wakeup_ports[3].bits.uop.debug_tsrc
connect slots_9.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[9].wakeup_ports[3].bits.uop.debug_fsrc
connect slots_9.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[9].wakeup_ports[3].bits.uop.bp_xcpt_if
connect slots_9.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[9].wakeup_ports[3].bits.uop.bp_debug_if
connect slots_9.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[9].wakeup_ports[3].bits.uop.xcpt_ma_if
connect slots_9.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[9].wakeup_ports[3].bits.uop.xcpt_ae_if
connect slots_9.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[9].wakeup_ports[3].bits.uop.xcpt_pf_if
connect slots_9.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[9].wakeup_ports[3].bits.uop.fp_typ
connect slots_9.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[9].wakeup_ports[3].bits.uop.fp_rm
connect slots_9.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[9].wakeup_ports[3].bits.uop.fp_val
connect slots_9.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[9].wakeup_ports[3].bits.uop.fcn_op
connect slots_9.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[9].wakeup_ports[3].bits.uop.fcn_dw
connect slots_9.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[9].wakeup_ports[3].bits.uop.frs3_en
connect slots_9.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[9].wakeup_ports[3].bits.uop.lrs2_rtype
connect slots_9.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[9].wakeup_ports[3].bits.uop.lrs1_rtype
connect slots_9.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[9].wakeup_ports[3].bits.uop.dst_rtype
connect slots_9.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[9].wakeup_ports[3].bits.uop.lrs3
connect slots_9.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[9].wakeup_ports[3].bits.uop.lrs2
connect slots_9.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[9].wakeup_ports[3].bits.uop.lrs1
connect slots_9.io.wakeup_ports[3].bits.uop.ldst, issue_slots[9].wakeup_ports[3].bits.uop.ldst
connect slots_9.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[9].wakeup_ports[3].bits.uop.ldst_is_rs1
connect slots_9.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[9].wakeup_ports[3].bits.uop.csr_cmd
connect slots_9.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[9].wakeup_ports[3].bits.uop.flush_on_commit
connect slots_9.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[9].wakeup_ports[3].bits.uop.is_unique
connect slots_9.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[9].wakeup_ports[3].bits.uop.uses_stq
connect slots_9.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[9].wakeup_ports[3].bits.uop.uses_ldq
connect slots_9.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[9].wakeup_ports[3].bits.uop.mem_signed
connect slots_9.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[9].wakeup_ports[3].bits.uop.mem_size
connect slots_9.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[9].wakeup_ports[3].bits.uop.mem_cmd
connect slots_9.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[9].wakeup_ports[3].bits.uop.exc_cause
connect slots_9.io.wakeup_ports[3].bits.uop.exception, issue_slots[9].wakeup_ports[3].bits.uop.exception
connect slots_9.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[9].wakeup_ports[3].bits.uop.stale_pdst
connect slots_9.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[9].wakeup_ports[3].bits.uop.ppred_busy
connect slots_9.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[9].wakeup_ports[3].bits.uop.prs3_busy
connect slots_9.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[9].wakeup_ports[3].bits.uop.prs2_busy
connect slots_9.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[9].wakeup_ports[3].bits.uop.prs1_busy
connect slots_9.io.wakeup_ports[3].bits.uop.ppred, issue_slots[9].wakeup_ports[3].bits.uop.ppred
connect slots_9.io.wakeup_ports[3].bits.uop.prs3, issue_slots[9].wakeup_ports[3].bits.uop.prs3
connect slots_9.io.wakeup_ports[3].bits.uop.prs2, issue_slots[9].wakeup_ports[3].bits.uop.prs2
connect slots_9.io.wakeup_ports[3].bits.uop.prs1, issue_slots[9].wakeup_ports[3].bits.uop.prs1
connect slots_9.io.wakeup_ports[3].bits.uop.pdst, issue_slots[9].wakeup_ports[3].bits.uop.pdst
connect slots_9.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[9].wakeup_ports[3].bits.uop.rxq_idx
connect slots_9.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[9].wakeup_ports[3].bits.uop.stq_idx
connect slots_9.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[9].wakeup_ports[3].bits.uop.ldq_idx
connect slots_9.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[9].wakeup_ports[3].bits.uop.rob_idx
connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.vec
connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.wflags
connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.sqrt
connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.div
connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.fma
connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe
connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.toint
connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.fromint
connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut
connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn
connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.swap23
connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.swap12
connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.ren3
connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.ren2
connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.ren1
connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.wen
connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.ldst
connect slots_9.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[9].wakeup_ports[3].bits.uop.op2_sel
connect slots_9.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[9].wakeup_ports[3].bits.uop.op1_sel
connect slots_9.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[9].wakeup_ports[3].bits.uop.imm_packed
connect slots_9.io.wakeup_ports[3].bits.uop.pimm, issue_slots[9].wakeup_ports[3].bits.uop.pimm
connect slots_9.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[9].wakeup_ports[3].bits.uop.imm_sel
connect slots_9.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[9].wakeup_ports[3].bits.uop.imm_rename
connect slots_9.io.wakeup_ports[3].bits.uop.taken, issue_slots[9].wakeup_ports[3].bits.uop.taken
connect slots_9.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[9].wakeup_ports[3].bits.uop.pc_lob
connect slots_9.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[9].wakeup_ports[3].bits.uop.edge_inst
connect slots_9.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[9].wakeup_ports[3].bits.uop.ftq_idx
connect slots_9.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[9].wakeup_ports[3].bits.uop.is_mov
connect slots_9.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[9].wakeup_ports[3].bits.uop.is_rocc
connect slots_9.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[9].wakeup_ports[3].bits.uop.is_sys_pc2epc
connect slots_9.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[9].wakeup_ports[3].bits.uop.is_eret
connect slots_9.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[9].wakeup_ports[3].bits.uop.is_amo
connect slots_9.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[9].wakeup_ports[3].bits.uop.is_sfence
connect slots_9.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[9].wakeup_ports[3].bits.uop.is_fencei
connect slots_9.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[9].wakeup_ports[3].bits.uop.is_fence
connect slots_9.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[9].wakeup_ports[3].bits.uop.is_sfb
connect slots_9.io.wakeup_ports[3].bits.uop.br_type, issue_slots[9].wakeup_ports[3].bits.uop.br_type
connect slots_9.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[9].wakeup_ports[3].bits.uop.br_tag
connect slots_9.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[9].wakeup_ports[3].bits.uop.br_mask
connect slots_9.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[9].wakeup_ports[3].bits.uop.dis_col_sel
connect slots_9.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[9].wakeup_ports[3].bits.uop.iw_p3_bypass_hint
connect slots_9.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[9].wakeup_ports[3].bits.uop.iw_p2_bypass_hint
connect slots_9.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[9].wakeup_ports[3].bits.uop.iw_p1_bypass_hint
connect slots_9.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[9].wakeup_ports[3].bits.uop.iw_p2_speculative_child
connect slots_9.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[9].wakeup_ports[3].bits.uop.iw_p1_speculative_child
connect slots_9.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[9].wakeup_ports[3].bits.uop.iw_issued_partial_dgen
connect slots_9.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[9].wakeup_ports[3].bits.uop.iw_issued_partial_agen
connect slots_9.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[9].wakeup_ports[3].bits.uop.iw_issued
connect slots_9.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[9].wakeup_ports[3].bits.uop.fu_code[0]
connect slots_9.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[9].wakeup_ports[3].bits.uop.fu_code[1]
connect slots_9.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[9].wakeup_ports[3].bits.uop.fu_code[2]
connect slots_9.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[9].wakeup_ports[3].bits.uop.fu_code[3]
connect slots_9.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[9].wakeup_ports[3].bits.uop.fu_code[4]
connect slots_9.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[9].wakeup_ports[3].bits.uop.fu_code[5]
connect slots_9.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[9].wakeup_ports[3].bits.uop.fu_code[6]
connect slots_9.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[9].wakeup_ports[3].bits.uop.fu_code[7]
connect slots_9.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[9].wakeup_ports[3].bits.uop.fu_code[8]
connect slots_9.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[9].wakeup_ports[3].bits.uop.fu_code[9]
connect slots_9.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[9].wakeup_ports[3].bits.uop.iq_type[0]
connect slots_9.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[9].wakeup_ports[3].bits.uop.iq_type[1]
connect slots_9.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[9].wakeup_ports[3].bits.uop.iq_type[2]
connect slots_9.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[9].wakeup_ports[3].bits.uop.iq_type[3]
connect slots_9.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[9].wakeup_ports[3].bits.uop.debug_pc
connect slots_9.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[9].wakeup_ports[3].bits.uop.is_rvc
connect slots_9.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[9].wakeup_ports[3].bits.uop.debug_inst
connect slots_9.io.wakeup_ports[3].bits.uop.inst, issue_slots[9].wakeup_ports[3].bits.uop.inst
connect slots_9.io.wakeup_ports[3].valid, issue_slots[9].wakeup_ports[3].valid
connect slots_9.io.squash_grant, issue_slots[9].squash_grant
connect slots_9.io.clear, issue_slots[9].clear
connect slots_9.io.kill, issue_slots[9].kill
connect slots_9.io.brupdate.b2.target_offset, issue_slots[9].brupdate.b2.target_offset
connect slots_9.io.brupdate.b2.jalr_target, issue_slots[9].brupdate.b2.jalr_target
connect slots_9.io.brupdate.b2.pc_sel, issue_slots[9].brupdate.b2.pc_sel
connect slots_9.io.brupdate.b2.cfi_type, issue_slots[9].brupdate.b2.cfi_type
connect slots_9.io.brupdate.b2.taken, issue_slots[9].brupdate.b2.taken
connect slots_9.io.brupdate.b2.mispredict, issue_slots[9].brupdate.b2.mispredict
connect slots_9.io.brupdate.b2.uop.debug_tsrc, issue_slots[9].brupdate.b2.uop.debug_tsrc
connect slots_9.io.brupdate.b2.uop.debug_fsrc, issue_slots[9].brupdate.b2.uop.debug_fsrc
connect slots_9.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[9].brupdate.b2.uop.bp_xcpt_if
connect slots_9.io.brupdate.b2.uop.bp_debug_if, issue_slots[9].brupdate.b2.uop.bp_debug_if
connect slots_9.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[9].brupdate.b2.uop.xcpt_ma_if
connect slots_9.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[9].brupdate.b2.uop.xcpt_ae_if
connect slots_9.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[9].brupdate.b2.uop.xcpt_pf_if
connect slots_9.io.brupdate.b2.uop.fp_typ, issue_slots[9].brupdate.b2.uop.fp_typ
connect slots_9.io.brupdate.b2.uop.fp_rm, issue_slots[9].brupdate.b2.uop.fp_rm
connect slots_9.io.brupdate.b2.uop.fp_val, issue_slots[9].brupdate.b2.uop.fp_val
connect slots_9.io.brupdate.b2.uop.fcn_op, issue_slots[9].brupdate.b2.uop.fcn_op
connect slots_9.io.brupdate.b2.uop.fcn_dw, issue_slots[9].brupdate.b2.uop.fcn_dw
connect slots_9.io.brupdate.b2.uop.frs3_en, issue_slots[9].brupdate.b2.uop.frs3_en
connect slots_9.io.brupdate.b2.uop.lrs2_rtype, issue_slots[9].brupdate.b2.uop.lrs2_rtype
connect slots_9.io.brupdate.b2.uop.lrs1_rtype, issue_slots[9].brupdate.b2.uop.lrs1_rtype
connect slots_9.io.brupdate.b2.uop.dst_rtype, issue_slots[9].brupdate.b2.uop.dst_rtype
connect slots_9.io.brupdate.b2.uop.lrs3, issue_slots[9].brupdate.b2.uop.lrs3
connect slots_9.io.brupdate.b2.uop.lrs2, issue_slots[9].brupdate.b2.uop.lrs2
connect slots_9.io.brupdate.b2.uop.lrs1, issue_slots[9].brupdate.b2.uop.lrs1
connect slots_9.io.brupdate.b2.uop.ldst, issue_slots[9].brupdate.b2.uop.ldst
connect slots_9.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[9].brupdate.b2.uop.ldst_is_rs1
connect slots_9.io.brupdate.b2.uop.csr_cmd, issue_slots[9].brupdate.b2.uop.csr_cmd
connect slots_9.io.brupdate.b2.uop.flush_on_commit, issue_slots[9].brupdate.b2.uop.flush_on_commit
connect slots_9.io.brupdate.b2.uop.is_unique, issue_slots[9].brupdate.b2.uop.is_unique
connect slots_9.io.brupdate.b2.uop.uses_stq, issue_slots[9].brupdate.b2.uop.uses_stq
connect slots_9.io.brupdate.b2.uop.uses_ldq, issue_slots[9].brupdate.b2.uop.uses_ldq
connect slots_9.io.brupdate.b2.uop.mem_signed, issue_slots[9].brupdate.b2.uop.mem_signed
connect slots_9.io.brupdate.b2.uop.mem_size, issue_slots[9].brupdate.b2.uop.mem_size
connect slots_9.io.brupdate.b2.uop.mem_cmd, issue_slots[9].brupdate.b2.uop.mem_cmd
connect slots_9.io.brupdate.b2.uop.exc_cause, issue_slots[9].brupdate.b2.uop.exc_cause
connect slots_9.io.brupdate.b2.uop.exception, issue_slots[9].brupdate.b2.uop.exception
connect slots_9.io.brupdate.b2.uop.stale_pdst, issue_slots[9].brupdate.b2.uop.stale_pdst
connect slots_9.io.brupdate.b2.uop.ppred_busy, issue_slots[9].brupdate.b2.uop.ppred_busy
connect slots_9.io.brupdate.b2.uop.prs3_busy, issue_slots[9].brupdate.b2.uop.prs3_busy
connect slots_9.io.brupdate.b2.uop.prs2_busy, issue_slots[9].brupdate.b2.uop.prs2_busy
connect slots_9.io.brupdate.b2.uop.prs1_busy, issue_slots[9].brupdate.b2.uop.prs1_busy
connect slots_9.io.brupdate.b2.uop.ppred, issue_slots[9].brupdate.b2.uop.ppred
connect slots_9.io.brupdate.b2.uop.prs3, issue_slots[9].brupdate.b2.uop.prs3
connect slots_9.io.brupdate.b2.uop.prs2, issue_slots[9].brupdate.b2.uop.prs2
connect slots_9.io.brupdate.b2.uop.prs1, issue_slots[9].brupdate.b2.uop.prs1
connect slots_9.io.brupdate.b2.uop.pdst, issue_slots[9].brupdate.b2.uop.pdst
connect slots_9.io.brupdate.b2.uop.rxq_idx, issue_slots[9].brupdate.b2.uop.rxq_idx
connect slots_9.io.brupdate.b2.uop.stq_idx, issue_slots[9].brupdate.b2.uop.stq_idx
connect slots_9.io.brupdate.b2.uop.ldq_idx, issue_slots[9].brupdate.b2.uop.ldq_idx
connect slots_9.io.brupdate.b2.uop.rob_idx, issue_slots[9].brupdate.b2.uop.rob_idx
connect slots_9.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[9].brupdate.b2.uop.fp_ctrl.vec
connect slots_9.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[9].brupdate.b2.uop.fp_ctrl.wflags
connect slots_9.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[9].brupdate.b2.uop.fp_ctrl.sqrt
connect slots_9.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[9].brupdate.b2.uop.fp_ctrl.div
connect slots_9.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[9].brupdate.b2.uop.fp_ctrl.fma
connect slots_9.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[9].brupdate.b2.uop.fp_ctrl.fastpipe
connect slots_9.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[9].brupdate.b2.uop.fp_ctrl.toint
connect slots_9.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[9].brupdate.b2.uop.fp_ctrl.fromint
connect slots_9.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[9].brupdate.b2.uop.fp_ctrl.typeTagOut
connect slots_9.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[9].brupdate.b2.uop.fp_ctrl.typeTagIn
connect slots_9.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[9].brupdate.b2.uop.fp_ctrl.swap23
connect slots_9.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[9].brupdate.b2.uop.fp_ctrl.swap12
connect slots_9.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[9].brupdate.b2.uop.fp_ctrl.ren3
connect slots_9.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[9].brupdate.b2.uop.fp_ctrl.ren2
connect slots_9.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[9].brupdate.b2.uop.fp_ctrl.ren1
connect slots_9.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[9].brupdate.b2.uop.fp_ctrl.wen
connect slots_9.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[9].brupdate.b2.uop.fp_ctrl.ldst
connect slots_9.io.brupdate.b2.uop.op2_sel, issue_slots[9].brupdate.b2.uop.op2_sel
connect slots_9.io.brupdate.b2.uop.op1_sel, issue_slots[9].brupdate.b2.uop.op1_sel
connect slots_9.io.brupdate.b2.uop.imm_packed, issue_slots[9].brupdate.b2.uop.imm_packed
connect slots_9.io.brupdate.b2.uop.pimm, issue_slots[9].brupdate.b2.uop.pimm
connect slots_9.io.brupdate.b2.uop.imm_sel, issue_slots[9].brupdate.b2.uop.imm_sel
connect slots_9.io.brupdate.b2.uop.imm_rename, issue_slots[9].brupdate.b2.uop.imm_rename
connect slots_9.io.brupdate.b2.uop.taken, issue_slots[9].brupdate.b2.uop.taken
connect slots_9.io.brupdate.b2.uop.pc_lob, issue_slots[9].brupdate.b2.uop.pc_lob
connect slots_9.io.brupdate.b2.uop.edge_inst, issue_slots[9].brupdate.b2.uop.edge_inst
connect slots_9.io.brupdate.b2.uop.ftq_idx, issue_slots[9].brupdate.b2.uop.ftq_idx
connect slots_9.io.brupdate.b2.uop.is_mov, issue_slots[9].brupdate.b2.uop.is_mov
connect slots_9.io.brupdate.b2.uop.is_rocc, issue_slots[9].brupdate.b2.uop.is_rocc
connect slots_9.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[9].brupdate.b2.uop.is_sys_pc2epc
connect slots_9.io.brupdate.b2.uop.is_eret, issue_slots[9].brupdate.b2.uop.is_eret
connect slots_9.io.brupdate.b2.uop.is_amo, issue_slots[9].brupdate.b2.uop.is_amo
connect slots_9.io.brupdate.b2.uop.is_sfence, issue_slots[9].brupdate.b2.uop.is_sfence
connect slots_9.io.brupdate.b2.uop.is_fencei, issue_slots[9].brupdate.b2.uop.is_fencei
connect slots_9.io.brupdate.b2.uop.is_fence, issue_slots[9].brupdate.b2.uop.is_fence
connect slots_9.io.brupdate.b2.uop.is_sfb, issue_slots[9].brupdate.b2.uop.is_sfb
connect slots_9.io.brupdate.b2.uop.br_type, issue_slots[9].brupdate.b2.uop.br_type
connect slots_9.io.brupdate.b2.uop.br_tag, issue_slots[9].brupdate.b2.uop.br_tag
connect slots_9.io.brupdate.b2.uop.br_mask, issue_slots[9].brupdate.b2.uop.br_mask
connect slots_9.io.brupdate.b2.uop.dis_col_sel, issue_slots[9].brupdate.b2.uop.dis_col_sel
connect slots_9.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[9].brupdate.b2.uop.iw_p3_bypass_hint
connect slots_9.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[9].brupdate.b2.uop.iw_p2_bypass_hint
connect slots_9.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[9].brupdate.b2.uop.iw_p1_bypass_hint
connect slots_9.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[9].brupdate.b2.uop.iw_p2_speculative_child
connect slots_9.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[9].brupdate.b2.uop.iw_p1_speculative_child
connect slots_9.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[9].brupdate.b2.uop.iw_issued_partial_dgen
connect slots_9.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[9].brupdate.b2.uop.iw_issued_partial_agen
connect slots_9.io.brupdate.b2.uop.iw_issued, issue_slots[9].brupdate.b2.uop.iw_issued
connect slots_9.io.brupdate.b2.uop.fu_code[0], issue_slots[9].brupdate.b2.uop.fu_code[0]
connect slots_9.io.brupdate.b2.uop.fu_code[1], issue_slots[9].brupdate.b2.uop.fu_code[1]
connect slots_9.io.brupdate.b2.uop.fu_code[2], issue_slots[9].brupdate.b2.uop.fu_code[2]
connect slots_9.io.brupdate.b2.uop.fu_code[3], issue_slots[9].brupdate.b2.uop.fu_code[3]
connect slots_9.io.brupdate.b2.uop.fu_code[4], issue_slots[9].brupdate.b2.uop.fu_code[4]
connect slots_9.io.brupdate.b2.uop.fu_code[5], issue_slots[9].brupdate.b2.uop.fu_code[5]
connect slots_9.io.brupdate.b2.uop.fu_code[6], issue_slots[9].brupdate.b2.uop.fu_code[6]
connect slots_9.io.brupdate.b2.uop.fu_code[7], issue_slots[9].brupdate.b2.uop.fu_code[7]
connect slots_9.io.brupdate.b2.uop.fu_code[8], issue_slots[9].brupdate.b2.uop.fu_code[8]
connect slots_9.io.brupdate.b2.uop.fu_code[9], issue_slots[9].brupdate.b2.uop.fu_code[9]
connect slots_9.io.brupdate.b2.uop.iq_type[0], issue_slots[9].brupdate.b2.uop.iq_type[0]
connect slots_9.io.brupdate.b2.uop.iq_type[1], issue_slots[9].brupdate.b2.uop.iq_type[1]
connect slots_9.io.brupdate.b2.uop.iq_type[2], issue_slots[9].brupdate.b2.uop.iq_type[2]
connect slots_9.io.brupdate.b2.uop.iq_type[3], issue_slots[9].brupdate.b2.uop.iq_type[3]
connect slots_9.io.brupdate.b2.uop.debug_pc, issue_slots[9].brupdate.b2.uop.debug_pc
connect slots_9.io.brupdate.b2.uop.is_rvc, issue_slots[9].brupdate.b2.uop.is_rvc
connect slots_9.io.brupdate.b2.uop.debug_inst, issue_slots[9].brupdate.b2.uop.debug_inst
connect slots_9.io.brupdate.b2.uop.inst, issue_slots[9].brupdate.b2.uop.inst
connect slots_9.io.brupdate.b1.mispredict_mask, issue_slots[9].brupdate.b1.mispredict_mask
connect slots_9.io.brupdate.b1.resolve_mask, issue_slots[9].brupdate.b1.resolve_mask
connect issue_slots[9].out_uop.debug_tsrc, slots_9.io.out_uop.debug_tsrc
connect issue_slots[9].out_uop.debug_fsrc, slots_9.io.out_uop.debug_fsrc
connect issue_slots[9].out_uop.bp_xcpt_if, slots_9.io.out_uop.bp_xcpt_if
connect issue_slots[9].out_uop.bp_debug_if, slots_9.io.out_uop.bp_debug_if
connect issue_slots[9].out_uop.xcpt_ma_if, slots_9.io.out_uop.xcpt_ma_if
connect issue_slots[9].out_uop.xcpt_ae_if, slots_9.io.out_uop.xcpt_ae_if
connect issue_slots[9].out_uop.xcpt_pf_if, slots_9.io.out_uop.xcpt_pf_if
connect issue_slots[9].out_uop.fp_typ, slots_9.io.out_uop.fp_typ
connect issue_slots[9].out_uop.fp_rm, slots_9.io.out_uop.fp_rm
connect issue_slots[9].out_uop.fp_val, slots_9.io.out_uop.fp_val
connect issue_slots[9].out_uop.fcn_op, slots_9.io.out_uop.fcn_op
connect issue_slots[9].out_uop.fcn_dw, slots_9.io.out_uop.fcn_dw
connect issue_slots[9].out_uop.frs3_en, slots_9.io.out_uop.frs3_en
connect issue_slots[9].out_uop.lrs2_rtype, slots_9.io.out_uop.lrs2_rtype
connect issue_slots[9].out_uop.lrs1_rtype, slots_9.io.out_uop.lrs1_rtype
connect issue_slots[9].out_uop.dst_rtype, slots_9.io.out_uop.dst_rtype
connect issue_slots[9].out_uop.lrs3, slots_9.io.out_uop.lrs3
connect issue_slots[9].out_uop.lrs2, slots_9.io.out_uop.lrs2
connect issue_slots[9].out_uop.lrs1, slots_9.io.out_uop.lrs1
connect issue_slots[9].out_uop.ldst, slots_9.io.out_uop.ldst
connect issue_slots[9].out_uop.ldst_is_rs1, slots_9.io.out_uop.ldst_is_rs1
connect issue_slots[9].out_uop.csr_cmd, slots_9.io.out_uop.csr_cmd
connect issue_slots[9].out_uop.flush_on_commit, slots_9.io.out_uop.flush_on_commit
connect issue_slots[9].out_uop.is_unique, slots_9.io.out_uop.is_unique
connect issue_slots[9].out_uop.uses_stq, slots_9.io.out_uop.uses_stq
connect issue_slots[9].out_uop.uses_ldq, slots_9.io.out_uop.uses_ldq
connect issue_slots[9].out_uop.mem_signed, slots_9.io.out_uop.mem_signed
connect issue_slots[9].out_uop.mem_size, slots_9.io.out_uop.mem_size
connect issue_slots[9].out_uop.mem_cmd, slots_9.io.out_uop.mem_cmd
connect issue_slots[9].out_uop.exc_cause, slots_9.io.out_uop.exc_cause
connect issue_slots[9].out_uop.exception, slots_9.io.out_uop.exception
connect issue_slots[9].out_uop.stale_pdst, slots_9.io.out_uop.stale_pdst
connect issue_slots[9].out_uop.ppred_busy, slots_9.io.out_uop.ppred_busy
connect issue_slots[9].out_uop.prs3_busy, slots_9.io.out_uop.prs3_busy
connect issue_slots[9].out_uop.prs2_busy, slots_9.io.out_uop.prs2_busy
connect issue_slots[9].out_uop.prs1_busy, slots_9.io.out_uop.prs1_busy
connect issue_slots[9].out_uop.ppred, slots_9.io.out_uop.ppred
connect issue_slots[9].out_uop.prs3, slots_9.io.out_uop.prs3
connect issue_slots[9].out_uop.prs2, slots_9.io.out_uop.prs2
connect issue_slots[9].out_uop.prs1, slots_9.io.out_uop.prs1
connect issue_slots[9].out_uop.pdst, slots_9.io.out_uop.pdst
connect issue_slots[9].out_uop.rxq_idx, slots_9.io.out_uop.rxq_idx
connect issue_slots[9].out_uop.stq_idx, slots_9.io.out_uop.stq_idx
connect issue_slots[9].out_uop.ldq_idx, slots_9.io.out_uop.ldq_idx
connect issue_slots[9].out_uop.rob_idx, slots_9.io.out_uop.rob_idx
connect issue_slots[9].out_uop.fp_ctrl.vec, slots_9.io.out_uop.fp_ctrl.vec
connect issue_slots[9].out_uop.fp_ctrl.wflags, slots_9.io.out_uop.fp_ctrl.wflags
connect issue_slots[9].out_uop.fp_ctrl.sqrt, slots_9.io.out_uop.fp_ctrl.sqrt
connect issue_slots[9].out_uop.fp_ctrl.div, slots_9.io.out_uop.fp_ctrl.div
connect issue_slots[9].out_uop.fp_ctrl.fma, slots_9.io.out_uop.fp_ctrl.fma
connect issue_slots[9].out_uop.fp_ctrl.fastpipe, slots_9.io.out_uop.fp_ctrl.fastpipe
connect issue_slots[9].out_uop.fp_ctrl.toint, slots_9.io.out_uop.fp_ctrl.toint
connect issue_slots[9].out_uop.fp_ctrl.fromint, slots_9.io.out_uop.fp_ctrl.fromint
connect issue_slots[9].out_uop.fp_ctrl.typeTagOut, slots_9.io.out_uop.fp_ctrl.typeTagOut
connect issue_slots[9].out_uop.fp_ctrl.typeTagIn, slots_9.io.out_uop.fp_ctrl.typeTagIn
connect issue_slots[9].out_uop.fp_ctrl.swap23, slots_9.io.out_uop.fp_ctrl.swap23
connect issue_slots[9].out_uop.fp_ctrl.swap12, slots_9.io.out_uop.fp_ctrl.swap12
connect issue_slots[9].out_uop.fp_ctrl.ren3, slots_9.io.out_uop.fp_ctrl.ren3
connect issue_slots[9].out_uop.fp_ctrl.ren2, slots_9.io.out_uop.fp_ctrl.ren2
connect issue_slots[9].out_uop.fp_ctrl.ren1, slots_9.io.out_uop.fp_ctrl.ren1
connect issue_slots[9].out_uop.fp_ctrl.wen, slots_9.io.out_uop.fp_ctrl.wen
connect issue_slots[9].out_uop.fp_ctrl.ldst, slots_9.io.out_uop.fp_ctrl.ldst
connect issue_slots[9].out_uop.op2_sel, slots_9.io.out_uop.op2_sel
connect issue_slots[9].out_uop.op1_sel, slots_9.io.out_uop.op1_sel
connect issue_slots[9].out_uop.imm_packed, slots_9.io.out_uop.imm_packed
connect issue_slots[9].out_uop.pimm, slots_9.io.out_uop.pimm
connect issue_slots[9].out_uop.imm_sel, slots_9.io.out_uop.imm_sel
connect issue_slots[9].out_uop.imm_rename, slots_9.io.out_uop.imm_rename
connect issue_slots[9].out_uop.taken, slots_9.io.out_uop.taken
connect issue_slots[9].out_uop.pc_lob, slots_9.io.out_uop.pc_lob
connect issue_slots[9].out_uop.edge_inst, slots_9.io.out_uop.edge_inst
connect issue_slots[9].out_uop.ftq_idx, slots_9.io.out_uop.ftq_idx
connect issue_slots[9].out_uop.is_mov, slots_9.io.out_uop.is_mov
connect issue_slots[9].out_uop.is_rocc, slots_9.io.out_uop.is_rocc
connect issue_slots[9].out_uop.is_sys_pc2epc, slots_9.io.out_uop.is_sys_pc2epc
connect issue_slots[9].out_uop.is_eret, slots_9.io.out_uop.is_eret
connect issue_slots[9].out_uop.is_amo, slots_9.io.out_uop.is_amo
connect issue_slots[9].out_uop.is_sfence, slots_9.io.out_uop.is_sfence
connect issue_slots[9].out_uop.is_fencei, slots_9.io.out_uop.is_fencei
connect issue_slots[9].out_uop.is_fence, slots_9.io.out_uop.is_fence
connect issue_slots[9].out_uop.is_sfb, slots_9.io.out_uop.is_sfb
connect issue_slots[9].out_uop.br_type, slots_9.io.out_uop.br_type
connect issue_slots[9].out_uop.br_tag, slots_9.io.out_uop.br_tag
connect issue_slots[9].out_uop.br_mask, slots_9.io.out_uop.br_mask
connect issue_slots[9].out_uop.dis_col_sel, slots_9.io.out_uop.dis_col_sel
connect issue_slots[9].out_uop.iw_p3_bypass_hint, slots_9.io.out_uop.iw_p3_bypass_hint
connect issue_slots[9].out_uop.iw_p2_bypass_hint, slots_9.io.out_uop.iw_p2_bypass_hint
connect issue_slots[9].out_uop.iw_p1_bypass_hint, slots_9.io.out_uop.iw_p1_bypass_hint
connect issue_slots[9].out_uop.iw_p2_speculative_child, slots_9.io.out_uop.iw_p2_speculative_child
connect issue_slots[9].out_uop.iw_p1_speculative_child, slots_9.io.out_uop.iw_p1_speculative_child
connect issue_slots[9].out_uop.iw_issued_partial_dgen, slots_9.io.out_uop.iw_issued_partial_dgen
connect issue_slots[9].out_uop.iw_issued_partial_agen, slots_9.io.out_uop.iw_issued_partial_agen
connect issue_slots[9].out_uop.iw_issued, slots_9.io.out_uop.iw_issued
connect issue_slots[9].out_uop.fu_code[0], slots_9.io.out_uop.fu_code[0]
connect issue_slots[9].out_uop.fu_code[1], slots_9.io.out_uop.fu_code[1]
connect issue_slots[9].out_uop.fu_code[2], slots_9.io.out_uop.fu_code[2]
connect issue_slots[9].out_uop.fu_code[3], slots_9.io.out_uop.fu_code[3]
connect issue_slots[9].out_uop.fu_code[4], slots_9.io.out_uop.fu_code[4]
connect issue_slots[9].out_uop.fu_code[5], slots_9.io.out_uop.fu_code[5]
connect issue_slots[9].out_uop.fu_code[6], slots_9.io.out_uop.fu_code[6]
connect issue_slots[9].out_uop.fu_code[7], slots_9.io.out_uop.fu_code[7]
connect issue_slots[9].out_uop.fu_code[8], slots_9.io.out_uop.fu_code[8]
connect issue_slots[9].out_uop.fu_code[9], slots_9.io.out_uop.fu_code[9]
connect issue_slots[9].out_uop.iq_type[0], slots_9.io.out_uop.iq_type[0]
connect issue_slots[9].out_uop.iq_type[1], slots_9.io.out_uop.iq_type[1]
connect issue_slots[9].out_uop.iq_type[2], slots_9.io.out_uop.iq_type[2]
connect issue_slots[9].out_uop.iq_type[3], slots_9.io.out_uop.iq_type[3]
connect issue_slots[9].out_uop.debug_pc, slots_9.io.out_uop.debug_pc
connect issue_slots[9].out_uop.is_rvc, slots_9.io.out_uop.is_rvc
connect issue_slots[9].out_uop.debug_inst, slots_9.io.out_uop.debug_inst
connect issue_slots[9].out_uop.inst, slots_9.io.out_uop.inst
connect slots_9.io.in_uop.bits.debug_tsrc, issue_slots[9].in_uop.bits.debug_tsrc
connect slots_9.io.in_uop.bits.debug_fsrc, issue_slots[9].in_uop.bits.debug_fsrc
connect slots_9.io.in_uop.bits.bp_xcpt_if, issue_slots[9].in_uop.bits.bp_xcpt_if
connect slots_9.io.in_uop.bits.bp_debug_if, issue_slots[9].in_uop.bits.bp_debug_if
connect slots_9.io.in_uop.bits.xcpt_ma_if, issue_slots[9].in_uop.bits.xcpt_ma_if
connect slots_9.io.in_uop.bits.xcpt_ae_if, issue_slots[9].in_uop.bits.xcpt_ae_if
connect slots_9.io.in_uop.bits.xcpt_pf_if, issue_slots[9].in_uop.bits.xcpt_pf_if
connect slots_9.io.in_uop.bits.fp_typ, issue_slots[9].in_uop.bits.fp_typ
connect slots_9.io.in_uop.bits.fp_rm, issue_slots[9].in_uop.bits.fp_rm
connect slots_9.io.in_uop.bits.fp_val, issue_slots[9].in_uop.bits.fp_val
connect slots_9.io.in_uop.bits.fcn_op, issue_slots[9].in_uop.bits.fcn_op
connect slots_9.io.in_uop.bits.fcn_dw, issue_slots[9].in_uop.bits.fcn_dw
connect slots_9.io.in_uop.bits.frs3_en, issue_slots[9].in_uop.bits.frs3_en
connect slots_9.io.in_uop.bits.lrs2_rtype, issue_slots[9].in_uop.bits.lrs2_rtype
connect slots_9.io.in_uop.bits.lrs1_rtype, issue_slots[9].in_uop.bits.lrs1_rtype
connect slots_9.io.in_uop.bits.dst_rtype, issue_slots[9].in_uop.bits.dst_rtype
connect slots_9.io.in_uop.bits.lrs3, issue_slots[9].in_uop.bits.lrs3
connect slots_9.io.in_uop.bits.lrs2, issue_slots[9].in_uop.bits.lrs2
connect slots_9.io.in_uop.bits.lrs1, issue_slots[9].in_uop.bits.lrs1
connect slots_9.io.in_uop.bits.ldst, issue_slots[9].in_uop.bits.ldst
connect slots_9.io.in_uop.bits.ldst_is_rs1, issue_slots[9].in_uop.bits.ldst_is_rs1
connect slots_9.io.in_uop.bits.csr_cmd, issue_slots[9].in_uop.bits.csr_cmd
connect slots_9.io.in_uop.bits.flush_on_commit, issue_slots[9].in_uop.bits.flush_on_commit
connect slots_9.io.in_uop.bits.is_unique, issue_slots[9].in_uop.bits.is_unique
connect slots_9.io.in_uop.bits.uses_stq, issue_slots[9].in_uop.bits.uses_stq
connect slots_9.io.in_uop.bits.uses_ldq, issue_slots[9].in_uop.bits.uses_ldq
connect slots_9.io.in_uop.bits.mem_signed, issue_slots[9].in_uop.bits.mem_signed
connect slots_9.io.in_uop.bits.mem_size, issue_slots[9].in_uop.bits.mem_size
connect slots_9.io.in_uop.bits.mem_cmd, issue_slots[9].in_uop.bits.mem_cmd
connect slots_9.io.in_uop.bits.exc_cause, issue_slots[9].in_uop.bits.exc_cause
connect slots_9.io.in_uop.bits.exception, issue_slots[9].in_uop.bits.exception
connect slots_9.io.in_uop.bits.stale_pdst, issue_slots[9].in_uop.bits.stale_pdst
connect slots_9.io.in_uop.bits.ppred_busy, issue_slots[9].in_uop.bits.ppred_busy
connect slots_9.io.in_uop.bits.prs3_busy, issue_slots[9].in_uop.bits.prs3_busy
connect slots_9.io.in_uop.bits.prs2_busy, issue_slots[9].in_uop.bits.prs2_busy
connect slots_9.io.in_uop.bits.prs1_busy, issue_slots[9].in_uop.bits.prs1_busy
connect slots_9.io.in_uop.bits.ppred, issue_slots[9].in_uop.bits.ppred
connect slots_9.io.in_uop.bits.prs3, issue_slots[9].in_uop.bits.prs3
connect slots_9.io.in_uop.bits.prs2, issue_slots[9].in_uop.bits.prs2
connect slots_9.io.in_uop.bits.prs1, issue_slots[9].in_uop.bits.prs1
connect slots_9.io.in_uop.bits.pdst, issue_slots[9].in_uop.bits.pdst
connect slots_9.io.in_uop.bits.rxq_idx, issue_slots[9].in_uop.bits.rxq_idx
connect slots_9.io.in_uop.bits.stq_idx, issue_slots[9].in_uop.bits.stq_idx
connect slots_9.io.in_uop.bits.ldq_idx, issue_slots[9].in_uop.bits.ldq_idx
connect slots_9.io.in_uop.bits.rob_idx, issue_slots[9].in_uop.bits.rob_idx
connect slots_9.io.in_uop.bits.fp_ctrl.vec, issue_slots[9].in_uop.bits.fp_ctrl.vec
connect slots_9.io.in_uop.bits.fp_ctrl.wflags, issue_slots[9].in_uop.bits.fp_ctrl.wflags
connect slots_9.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[9].in_uop.bits.fp_ctrl.sqrt
connect slots_9.io.in_uop.bits.fp_ctrl.div, issue_slots[9].in_uop.bits.fp_ctrl.div
connect slots_9.io.in_uop.bits.fp_ctrl.fma, issue_slots[9].in_uop.bits.fp_ctrl.fma
connect slots_9.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[9].in_uop.bits.fp_ctrl.fastpipe
connect slots_9.io.in_uop.bits.fp_ctrl.toint, issue_slots[9].in_uop.bits.fp_ctrl.toint
connect slots_9.io.in_uop.bits.fp_ctrl.fromint, issue_slots[9].in_uop.bits.fp_ctrl.fromint
connect slots_9.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[9].in_uop.bits.fp_ctrl.typeTagOut
connect slots_9.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[9].in_uop.bits.fp_ctrl.typeTagIn
connect slots_9.io.in_uop.bits.fp_ctrl.swap23, issue_slots[9].in_uop.bits.fp_ctrl.swap23
connect slots_9.io.in_uop.bits.fp_ctrl.swap12, issue_slots[9].in_uop.bits.fp_ctrl.swap12
connect slots_9.io.in_uop.bits.fp_ctrl.ren3, issue_slots[9].in_uop.bits.fp_ctrl.ren3
connect slots_9.io.in_uop.bits.fp_ctrl.ren2, issue_slots[9].in_uop.bits.fp_ctrl.ren2
connect slots_9.io.in_uop.bits.fp_ctrl.ren1, issue_slots[9].in_uop.bits.fp_ctrl.ren1
connect slots_9.io.in_uop.bits.fp_ctrl.wen, issue_slots[9].in_uop.bits.fp_ctrl.wen
connect slots_9.io.in_uop.bits.fp_ctrl.ldst, issue_slots[9].in_uop.bits.fp_ctrl.ldst
connect slots_9.io.in_uop.bits.op2_sel, issue_slots[9].in_uop.bits.op2_sel
connect slots_9.io.in_uop.bits.op1_sel, issue_slots[9].in_uop.bits.op1_sel
connect slots_9.io.in_uop.bits.imm_packed, issue_slots[9].in_uop.bits.imm_packed
connect slots_9.io.in_uop.bits.pimm, issue_slots[9].in_uop.bits.pimm
connect slots_9.io.in_uop.bits.imm_sel, issue_slots[9].in_uop.bits.imm_sel
connect slots_9.io.in_uop.bits.imm_rename, issue_slots[9].in_uop.bits.imm_rename
connect slots_9.io.in_uop.bits.taken, issue_slots[9].in_uop.bits.taken
connect slots_9.io.in_uop.bits.pc_lob, issue_slots[9].in_uop.bits.pc_lob
connect slots_9.io.in_uop.bits.edge_inst, issue_slots[9].in_uop.bits.edge_inst
connect slots_9.io.in_uop.bits.ftq_idx, issue_slots[9].in_uop.bits.ftq_idx
connect slots_9.io.in_uop.bits.is_mov, issue_slots[9].in_uop.bits.is_mov
connect slots_9.io.in_uop.bits.is_rocc, issue_slots[9].in_uop.bits.is_rocc
connect slots_9.io.in_uop.bits.is_sys_pc2epc, issue_slots[9].in_uop.bits.is_sys_pc2epc
connect slots_9.io.in_uop.bits.is_eret, issue_slots[9].in_uop.bits.is_eret
connect slots_9.io.in_uop.bits.is_amo, issue_slots[9].in_uop.bits.is_amo
connect slots_9.io.in_uop.bits.is_sfence, issue_slots[9].in_uop.bits.is_sfence
connect slots_9.io.in_uop.bits.is_fencei, issue_slots[9].in_uop.bits.is_fencei
connect slots_9.io.in_uop.bits.is_fence, issue_slots[9].in_uop.bits.is_fence
connect slots_9.io.in_uop.bits.is_sfb, issue_slots[9].in_uop.bits.is_sfb
connect slots_9.io.in_uop.bits.br_type, issue_slots[9].in_uop.bits.br_type
connect slots_9.io.in_uop.bits.br_tag, issue_slots[9].in_uop.bits.br_tag
connect slots_9.io.in_uop.bits.br_mask, issue_slots[9].in_uop.bits.br_mask
connect slots_9.io.in_uop.bits.dis_col_sel, issue_slots[9].in_uop.bits.dis_col_sel
connect slots_9.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[9].in_uop.bits.iw_p3_bypass_hint
connect slots_9.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[9].in_uop.bits.iw_p2_bypass_hint
connect slots_9.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[9].in_uop.bits.iw_p1_bypass_hint
connect slots_9.io.in_uop.bits.iw_p2_speculative_child, issue_slots[9].in_uop.bits.iw_p2_speculative_child
connect slots_9.io.in_uop.bits.iw_p1_speculative_child, issue_slots[9].in_uop.bits.iw_p1_speculative_child
connect slots_9.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[9].in_uop.bits.iw_issued_partial_dgen
connect slots_9.io.in_uop.bits.iw_issued_partial_agen, issue_slots[9].in_uop.bits.iw_issued_partial_agen
connect slots_9.io.in_uop.bits.iw_issued, issue_slots[9].in_uop.bits.iw_issued
connect slots_9.io.in_uop.bits.fu_code[0], issue_slots[9].in_uop.bits.fu_code[0]
connect slots_9.io.in_uop.bits.fu_code[1], issue_slots[9].in_uop.bits.fu_code[1]
connect slots_9.io.in_uop.bits.fu_code[2], issue_slots[9].in_uop.bits.fu_code[2]
connect slots_9.io.in_uop.bits.fu_code[3], issue_slots[9].in_uop.bits.fu_code[3]
connect slots_9.io.in_uop.bits.fu_code[4], issue_slots[9].in_uop.bits.fu_code[4]
connect slots_9.io.in_uop.bits.fu_code[5], issue_slots[9].in_uop.bits.fu_code[5]
connect slots_9.io.in_uop.bits.fu_code[6], issue_slots[9].in_uop.bits.fu_code[6]
connect slots_9.io.in_uop.bits.fu_code[7], issue_slots[9].in_uop.bits.fu_code[7]
connect slots_9.io.in_uop.bits.fu_code[8], issue_slots[9].in_uop.bits.fu_code[8]
connect slots_9.io.in_uop.bits.fu_code[9], issue_slots[9].in_uop.bits.fu_code[9]
connect slots_9.io.in_uop.bits.iq_type[0], issue_slots[9].in_uop.bits.iq_type[0]
connect slots_9.io.in_uop.bits.iq_type[1], issue_slots[9].in_uop.bits.iq_type[1]
connect slots_9.io.in_uop.bits.iq_type[2], issue_slots[9].in_uop.bits.iq_type[2]
connect slots_9.io.in_uop.bits.iq_type[3], issue_slots[9].in_uop.bits.iq_type[3]
connect slots_9.io.in_uop.bits.debug_pc, issue_slots[9].in_uop.bits.debug_pc
connect slots_9.io.in_uop.bits.is_rvc, issue_slots[9].in_uop.bits.is_rvc
connect slots_9.io.in_uop.bits.debug_inst, issue_slots[9].in_uop.bits.debug_inst
connect slots_9.io.in_uop.bits.inst, issue_slots[9].in_uop.bits.inst
connect slots_9.io.in_uop.valid, issue_slots[9].in_uop.valid
connect issue_slots[9].iss_uop.debug_tsrc, slots_9.io.iss_uop.debug_tsrc
connect issue_slots[9].iss_uop.debug_fsrc, slots_9.io.iss_uop.debug_fsrc
connect issue_slots[9].iss_uop.bp_xcpt_if, slots_9.io.iss_uop.bp_xcpt_if
connect issue_slots[9].iss_uop.bp_debug_if, slots_9.io.iss_uop.bp_debug_if
connect issue_slots[9].iss_uop.xcpt_ma_if, slots_9.io.iss_uop.xcpt_ma_if
connect issue_slots[9].iss_uop.xcpt_ae_if, slots_9.io.iss_uop.xcpt_ae_if
connect issue_slots[9].iss_uop.xcpt_pf_if, slots_9.io.iss_uop.xcpt_pf_if
connect issue_slots[9].iss_uop.fp_typ, slots_9.io.iss_uop.fp_typ
connect issue_slots[9].iss_uop.fp_rm, slots_9.io.iss_uop.fp_rm
connect issue_slots[9].iss_uop.fp_val, slots_9.io.iss_uop.fp_val
connect issue_slots[9].iss_uop.fcn_op, slots_9.io.iss_uop.fcn_op
connect issue_slots[9].iss_uop.fcn_dw, slots_9.io.iss_uop.fcn_dw
connect issue_slots[9].iss_uop.frs3_en, slots_9.io.iss_uop.frs3_en
connect issue_slots[9].iss_uop.lrs2_rtype, slots_9.io.iss_uop.lrs2_rtype
connect issue_slots[9].iss_uop.lrs1_rtype, slots_9.io.iss_uop.lrs1_rtype
connect issue_slots[9].iss_uop.dst_rtype, slots_9.io.iss_uop.dst_rtype
connect issue_slots[9].iss_uop.lrs3, slots_9.io.iss_uop.lrs3
connect issue_slots[9].iss_uop.lrs2, slots_9.io.iss_uop.lrs2
connect issue_slots[9].iss_uop.lrs1, slots_9.io.iss_uop.lrs1
connect issue_slots[9].iss_uop.ldst, slots_9.io.iss_uop.ldst
connect issue_slots[9].iss_uop.ldst_is_rs1, slots_9.io.iss_uop.ldst_is_rs1
connect issue_slots[9].iss_uop.csr_cmd, slots_9.io.iss_uop.csr_cmd
connect issue_slots[9].iss_uop.flush_on_commit, slots_9.io.iss_uop.flush_on_commit
connect issue_slots[9].iss_uop.is_unique, slots_9.io.iss_uop.is_unique
connect issue_slots[9].iss_uop.uses_stq, slots_9.io.iss_uop.uses_stq
connect issue_slots[9].iss_uop.uses_ldq, slots_9.io.iss_uop.uses_ldq
connect issue_slots[9].iss_uop.mem_signed, slots_9.io.iss_uop.mem_signed
connect issue_slots[9].iss_uop.mem_size, slots_9.io.iss_uop.mem_size
connect issue_slots[9].iss_uop.mem_cmd, slots_9.io.iss_uop.mem_cmd
connect issue_slots[9].iss_uop.exc_cause, slots_9.io.iss_uop.exc_cause
connect issue_slots[9].iss_uop.exception, slots_9.io.iss_uop.exception
connect issue_slots[9].iss_uop.stale_pdst, slots_9.io.iss_uop.stale_pdst
connect issue_slots[9].iss_uop.ppred_busy, slots_9.io.iss_uop.ppred_busy
connect issue_slots[9].iss_uop.prs3_busy, slots_9.io.iss_uop.prs3_busy
connect issue_slots[9].iss_uop.prs2_busy, slots_9.io.iss_uop.prs2_busy
connect issue_slots[9].iss_uop.prs1_busy, slots_9.io.iss_uop.prs1_busy
connect issue_slots[9].iss_uop.ppred, slots_9.io.iss_uop.ppred
connect issue_slots[9].iss_uop.prs3, slots_9.io.iss_uop.prs3
connect issue_slots[9].iss_uop.prs2, slots_9.io.iss_uop.prs2
connect issue_slots[9].iss_uop.prs1, slots_9.io.iss_uop.prs1
connect issue_slots[9].iss_uop.pdst, slots_9.io.iss_uop.pdst
connect issue_slots[9].iss_uop.rxq_idx, slots_9.io.iss_uop.rxq_idx
connect issue_slots[9].iss_uop.stq_idx, slots_9.io.iss_uop.stq_idx
connect issue_slots[9].iss_uop.ldq_idx, slots_9.io.iss_uop.ldq_idx
connect issue_slots[9].iss_uop.rob_idx, slots_9.io.iss_uop.rob_idx
connect issue_slots[9].iss_uop.fp_ctrl.vec, slots_9.io.iss_uop.fp_ctrl.vec
connect issue_slots[9].iss_uop.fp_ctrl.wflags, slots_9.io.iss_uop.fp_ctrl.wflags
connect issue_slots[9].iss_uop.fp_ctrl.sqrt, slots_9.io.iss_uop.fp_ctrl.sqrt
connect issue_slots[9].iss_uop.fp_ctrl.div, slots_9.io.iss_uop.fp_ctrl.div
connect issue_slots[9].iss_uop.fp_ctrl.fma, slots_9.io.iss_uop.fp_ctrl.fma
connect issue_slots[9].iss_uop.fp_ctrl.fastpipe, slots_9.io.iss_uop.fp_ctrl.fastpipe
connect issue_slots[9].iss_uop.fp_ctrl.toint, slots_9.io.iss_uop.fp_ctrl.toint
connect issue_slots[9].iss_uop.fp_ctrl.fromint, slots_9.io.iss_uop.fp_ctrl.fromint
connect issue_slots[9].iss_uop.fp_ctrl.typeTagOut, slots_9.io.iss_uop.fp_ctrl.typeTagOut
connect issue_slots[9].iss_uop.fp_ctrl.typeTagIn, slots_9.io.iss_uop.fp_ctrl.typeTagIn
connect issue_slots[9].iss_uop.fp_ctrl.swap23, slots_9.io.iss_uop.fp_ctrl.swap23
connect issue_slots[9].iss_uop.fp_ctrl.swap12, slots_9.io.iss_uop.fp_ctrl.swap12
connect issue_slots[9].iss_uop.fp_ctrl.ren3, slots_9.io.iss_uop.fp_ctrl.ren3
connect issue_slots[9].iss_uop.fp_ctrl.ren2, slots_9.io.iss_uop.fp_ctrl.ren2
connect issue_slots[9].iss_uop.fp_ctrl.ren1, slots_9.io.iss_uop.fp_ctrl.ren1
connect issue_slots[9].iss_uop.fp_ctrl.wen, slots_9.io.iss_uop.fp_ctrl.wen
connect issue_slots[9].iss_uop.fp_ctrl.ldst, slots_9.io.iss_uop.fp_ctrl.ldst
connect issue_slots[9].iss_uop.op2_sel, slots_9.io.iss_uop.op2_sel
connect issue_slots[9].iss_uop.op1_sel, slots_9.io.iss_uop.op1_sel
connect issue_slots[9].iss_uop.imm_packed, slots_9.io.iss_uop.imm_packed
connect issue_slots[9].iss_uop.pimm, slots_9.io.iss_uop.pimm
connect issue_slots[9].iss_uop.imm_sel, slots_9.io.iss_uop.imm_sel
connect issue_slots[9].iss_uop.imm_rename, slots_9.io.iss_uop.imm_rename
connect issue_slots[9].iss_uop.taken, slots_9.io.iss_uop.taken
connect issue_slots[9].iss_uop.pc_lob, slots_9.io.iss_uop.pc_lob
connect issue_slots[9].iss_uop.edge_inst, slots_9.io.iss_uop.edge_inst
connect issue_slots[9].iss_uop.ftq_idx, slots_9.io.iss_uop.ftq_idx
connect issue_slots[9].iss_uop.is_mov, slots_9.io.iss_uop.is_mov
connect issue_slots[9].iss_uop.is_rocc, slots_9.io.iss_uop.is_rocc
connect issue_slots[9].iss_uop.is_sys_pc2epc, slots_9.io.iss_uop.is_sys_pc2epc
connect issue_slots[9].iss_uop.is_eret, slots_9.io.iss_uop.is_eret
connect issue_slots[9].iss_uop.is_amo, slots_9.io.iss_uop.is_amo
connect issue_slots[9].iss_uop.is_sfence, slots_9.io.iss_uop.is_sfence
connect issue_slots[9].iss_uop.is_fencei, slots_9.io.iss_uop.is_fencei
connect issue_slots[9].iss_uop.is_fence, slots_9.io.iss_uop.is_fence
connect issue_slots[9].iss_uop.is_sfb, slots_9.io.iss_uop.is_sfb
connect issue_slots[9].iss_uop.br_type, slots_9.io.iss_uop.br_type
connect issue_slots[9].iss_uop.br_tag, slots_9.io.iss_uop.br_tag
connect issue_slots[9].iss_uop.br_mask, slots_9.io.iss_uop.br_mask
connect issue_slots[9].iss_uop.dis_col_sel, slots_9.io.iss_uop.dis_col_sel
connect issue_slots[9].iss_uop.iw_p3_bypass_hint, slots_9.io.iss_uop.iw_p3_bypass_hint
connect issue_slots[9].iss_uop.iw_p2_bypass_hint, slots_9.io.iss_uop.iw_p2_bypass_hint
connect issue_slots[9].iss_uop.iw_p1_bypass_hint, slots_9.io.iss_uop.iw_p1_bypass_hint
connect issue_slots[9].iss_uop.iw_p2_speculative_child, slots_9.io.iss_uop.iw_p2_speculative_child
connect issue_slots[9].iss_uop.iw_p1_speculative_child, slots_9.io.iss_uop.iw_p1_speculative_child
connect issue_slots[9].iss_uop.iw_issued_partial_dgen, slots_9.io.iss_uop.iw_issued_partial_dgen
connect issue_slots[9].iss_uop.iw_issued_partial_agen, slots_9.io.iss_uop.iw_issued_partial_agen
connect issue_slots[9].iss_uop.iw_issued, slots_9.io.iss_uop.iw_issued
connect issue_slots[9].iss_uop.fu_code[0], slots_9.io.iss_uop.fu_code[0]
connect issue_slots[9].iss_uop.fu_code[1], slots_9.io.iss_uop.fu_code[1]
connect issue_slots[9].iss_uop.fu_code[2], slots_9.io.iss_uop.fu_code[2]
connect issue_slots[9].iss_uop.fu_code[3], slots_9.io.iss_uop.fu_code[3]
connect issue_slots[9].iss_uop.fu_code[4], slots_9.io.iss_uop.fu_code[4]
connect issue_slots[9].iss_uop.fu_code[5], slots_9.io.iss_uop.fu_code[5]
connect issue_slots[9].iss_uop.fu_code[6], slots_9.io.iss_uop.fu_code[6]
connect issue_slots[9].iss_uop.fu_code[7], slots_9.io.iss_uop.fu_code[7]
connect issue_slots[9].iss_uop.fu_code[8], slots_9.io.iss_uop.fu_code[8]
connect issue_slots[9].iss_uop.fu_code[9], slots_9.io.iss_uop.fu_code[9]
connect issue_slots[9].iss_uop.iq_type[0], slots_9.io.iss_uop.iq_type[0]
connect issue_slots[9].iss_uop.iq_type[1], slots_9.io.iss_uop.iq_type[1]
connect issue_slots[9].iss_uop.iq_type[2], slots_9.io.iss_uop.iq_type[2]
connect issue_slots[9].iss_uop.iq_type[3], slots_9.io.iss_uop.iq_type[3]
connect issue_slots[9].iss_uop.debug_pc, slots_9.io.iss_uop.debug_pc
connect issue_slots[9].iss_uop.is_rvc, slots_9.io.iss_uop.is_rvc
connect issue_slots[9].iss_uop.debug_inst, slots_9.io.iss_uop.debug_inst
connect issue_slots[9].iss_uop.inst, slots_9.io.iss_uop.inst
connect slots_9.io.grant, issue_slots[9].grant
connect issue_slots[9].request, slots_9.io.request
connect issue_slots[9].will_be_valid, slots_9.io.will_be_valid
connect issue_slots[9].valid, slots_9.io.valid
connect slots_10.io.child_rebusys, issue_slots[10].child_rebusys
connect slots_10.io.pred_wakeup_port.bits, issue_slots[10].pred_wakeup_port.bits
connect slots_10.io.pred_wakeup_port.valid, issue_slots[10].pred_wakeup_port.valid
connect slots_10.io.wakeup_ports[0].bits.rebusy, issue_slots[10].wakeup_ports[0].bits.rebusy
connect slots_10.io.wakeup_ports[0].bits.speculative_mask, issue_slots[10].wakeup_ports[0].bits.speculative_mask
connect slots_10.io.wakeup_ports[0].bits.bypassable, issue_slots[10].wakeup_ports[0].bits.bypassable
connect slots_10.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[10].wakeup_ports[0].bits.uop.debug_tsrc
connect slots_10.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[10].wakeup_ports[0].bits.uop.debug_fsrc
connect slots_10.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[10].wakeup_ports[0].bits.uop.bp_xcpt_if
connect slots_10.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[10].wakeup_ports[0].bits.uop.bp_debug_if
connect slots_10.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[10].wakeup_ports[0].bits.uop.xcpt_ma_if
connect slots_10.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[10].wakeup_ports[0].bits.uop.xcpt_ae_if
connect slots_10.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[10].wakeup_ports[0].bits.uop.xcpt_pf_if
connect slots_10.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[10].wakeup_ports[0].bits.uop.fp_typ
connect slots_10.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[10].wakeup_ports[0].bits.uop.fp_rm
connect slots_10.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[10].wakeup_ports[0].bits.uop.fp_val
connect slots_10.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[10].wakeup_ports[0].bits.uop.fcn_op
connect slots_10.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[10].wakeup_ports[0].bits.uop.fcn_dw
connect slots_10.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[10].wakeup_ports[0].bits.uop.frs3_en
connect slots_10.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[10].wakeup_ports[0].bits.uop.lrs2_rtype
connect slots_10.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[10].wakeup_ports[0].bits.uop.lrs1_rtype
connect slots_10.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[10].wakeup_ports[0].bits.uop.dst_rtype
connect slots_10.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[10].wakeup_ports[0].bits.uop.lrs3
connect slots_10.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[10].wakeup_ports[0].bits.uop.lrs2
connect slots_10.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[10].wakeup_ports[0].bits.uop.lrs1
connect slots_10.io.wakeup_ports[0].bits.uop.ldst, issue_slots[10].wakeup_ports[0].bits.uop.ldst
connect slots_10.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[10].wakeup_ports[0].bits.uop.ldst_is_rs1
connect slots_10.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[10].wakeup_ports[0].bits.uop.csr_cmd
connect slots_10.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[10].wakeup_ports[0].bits.uop.flush_on_commit
connect slots_10.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[10].wakeup_ports[0].bits.uop.is_unique
connect slots_10.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[10].wakeup_ports[0].bits.uop.uses_stq
connect slots_10.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[10].wakeup_ports[0].bits.uop.uses_ldq
connect slots_10.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[10].wakeup_ports[0].bits.uop.mem_signed
connect slots_10.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[10].wakeup_ports[0].bits.uop.mem_size
connect slots_10.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[10].wakeup_ports[0].bits.uop.mem_cmd
connect slots_10.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[10].wakeup_ports[0].bits.uop.exc_cause
connect slots_10.io.wakeup_ports[0].bits.uop.exception, issue_slots[10].wakeup_ports[0].bits.uop.exception
connect slots_10.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[10].wakeup_ports[0].bits.uop.stale_pdst
connect slots_10.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[10].wakeup_ports[0].bits.uop.ppred_busy
connect slots_10.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[10].wakeup_ports[0].bits.uop.prs3_busy
connect slots_10.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[10].wakeup_ports[0].bits.uop.prs2_busy
connect slots_10.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[10].wakeup_ports[0].bits.uop.prs1_busy
connect slots_10.io.wakeup_ports[0].bits.uop.ppred, issue_slots[10].wakeup_ports[0].bits.uop.ppred
connect slots_10.io.wakeup_ports[0].bits.uop.prs3, issue_slots[10].wakeup_ports[0].bits.uop.prs3
connect slots_10.io.wakeup_ports[0].bits.uop.prs2, issue_slots[10].wakeup_ports[0].bits.uop.prs2
connect slots_10.io.wakeup_ports[0].bits.uop.prs1, issue_slots[10].wakeup_ports[0].bits.uop.prs1
connect slots_10.io.wakeup_ports[0].bits.uop.pdst, issue_slots[10].wakeup_ports[0].bits.uop.pdst
connect slots_10.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[10].wakeup_ports[0].bits.uop.rxq_idx
connect slots_10.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[10].wakeup_ports[0].bits.uop.stq_idx
connect slots_10.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[10].wakeup_ports[0].bits.uop.ldq_idx
connect slots_10.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[10].wakeup_ports[0].bits.uop.rob_idx
connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.vec
connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.wflags
connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.sqrt
connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.div
connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.fma
connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe
connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.toint
connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.fromint
connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut
connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn
connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.swap23
connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.swap12
connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.ren3
connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.ren2
connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.ren1
connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.wen
connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.ldst
connect slots_10.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[10].wakeup_ports[0].bits.uop.op2_sel
connect slots_10.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[10].wakeup_ports[0].bits.uop.op1_sel
connect slots_10.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[10].wakeup_ports[0].bits.uop.imm_packed
connect slots_10.io.wakeup_ports[0].bits.uop.pimm, issue_slots[10].wakeup_ports[0].bits.uop.pimm
connect slots_10.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[10].wakeup_ports[0].bits.uop.imm_sel
connect slots_10.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[10].wakeup_ports[0].bits.uop.imm_rename
connect slots_10.io.wakeup_ports[0].bits.uop.taken, issue_slots[10].wakeup_ports[0].bits.uop.taken
connect slots_10.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[10].wakeup_ports[0].bits.uop.pc_lob
connect slots_10.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[10].wakeup_ports[0].bits.uop.edge_inst
connect slots_10.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[10].wakeup_ports[0].bits.uop.ftq_idx
connect slots_10.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[10].wakeup_ports[0].bits.uop.is_mov
connect slots_10.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[10].wakeup_ports[0].bits.uop.is_rocc
connect slots_10.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[10].wakeup_ports[0].bits.uop.is_sys_pc2epc
connect slots_10.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[10].wakeup_ports[0].bits.uop.is_eret
connect slots_10.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[10].wakeup_ports[0].bits.uop.is_amo
connect slots_10.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[10].wakeup_ports[0].bits.uop.is_sfence
connect slots_10.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[10].wakeup_ports[0].bits.uop.is_fencei
connect slots_10.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[10].wakeup_ports[0].bits.uop.is_fence
connect slots_10.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[10].wakeup_ports[0].bits.uop.is_sfb
connect slots_10.io.wakeup_ports[0].bits.uop.br_type, issue_slots[10].wakeup_ports[0].bits.uop.br_type
connect slots_10.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[10].wakeup_ports[0].bits.uop.br_tag
connect slots_10.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[10].wakeup_ports[0].bits.uop.br_mask
connect slots_10.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[10].wakeup_ports[0].bits.uop.dis_col_sel
connect slots_10.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[10].wakeup_ports[0].bits.uop.iw_p3_bypass_hint
connect slots_10.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[10].wakeup_ports[0].bits.uop.iw_p2_bypass_hint
connect slots_10.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[10].wakeup_ports[0].bits.uop.iw_p1_bypass_hint
connect slots_10.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[10].wakeup_ports[0].bits.uop.iw_p2_speculative_child
connect slots_10.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[10].wakeup_ports[0].bits.uop.iw_p1_speculative_child
connect slots_10.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[10].wakeup_ports[0].bits.uop.iw_issued_partial_dgen
connect slots_10.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[10].wakeup_ports[0].bits.uop.iw_issued_partial_agen
connect slots_10.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[10].wakeup_ports[0].bits.uop.iw_issued
connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[0]
connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[1]
connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[2]
connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[3]
connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[4]
connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[5]
connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[6]
connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[7]
connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[8]
connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[9]
connect slots_10.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[10].wakeup_ports[0].bits.uop.iq_type[0]
connect slots_10.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[10].wakeup_ports[0].bits.uop.iq_type[1]
connect slots_10.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[10].wakeup_ports[0].bits.uop.iq_type[2]
connect slots_10.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[10].wakeup_ports[0].bits.uop.iq_type[3]
connect slots_10.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[10].wakeup_ports[0].bits.uop.debug_pc
connect slots_10.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[10].wakeup_ports[0].bits.uop.is_rvc
connect slots_10.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[10].wakeup_ports[0].bits.uop.debug_inst
connect slots_10.io.wakeup_ports[0].bits.uop.inst, issue_slots[10].wakeup_ports[0].bits.uop.inst
connect slots_10.io.wakeup_ports[0].valid, issue_slots[10].wakeup_ports[0].valid
connect slots_10.io.wakeup_ports[1].bits.rebusy, issue_slots[10].wakeup_ports[1].bits.rebusy
connect slots_10.io.wakeup_ports[1].bits.speculative_mask, issue_slots[10].wakeup_ports[1].bits.speculative_mask
connect slots_10.io.wakeup_ports[1].bits.bypassable, issue_slots[10].wakeup_ports[1].bits.bypassable
connect slots_10.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[10].wakeup_ports[1].bits.uop.debug_tsrc
connect slots_10.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[10].wakeup_ports[1].bits.uop.debug_fsrc
connect slots_10.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[10].wakeup_ports[1].bits.uop.bp_xcpt_if
connect slots_10.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[10].wakeup_ports[1].bits.uop.bp_debug_if
connect slots_10.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[10].wakeup_ports[1].bits.uop.xcpt_ma_if
connect slots_10.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[10].wakeup_ports[1].bits.uop.xcpt_ae_if
connect slots_10.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[10].wakeup_ports[1].bits.uop.xcpt_pf_if
connect slots_10.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[10].wakeup_ports[1].bits.uop.fp_typ
connect slots_10.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[10].wakeup_ports[1].bits.uop.fp_rm
connect slots_10.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[10].wakeup_ports[1].bits.uop.fp_val
connect slots_10.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[10].wakeup_ports[1].bits.uop.fcn_op
connect slots_10.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[10].wakeup_ports[1].bits.uop.fcn_dw
connect slots_10.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[10].wakeup_ports[1].bits.uop.frs3_en
connect slots_10.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[10].wakeup_ports[1].bits.uop.lrs2_rtype
connect slots_10.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[10].wakeup_ports[1].bits.uop.lrs1_rtype
connect slots_10.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[10].wakeup_ports[1].bits.uop.dst_rtype
connect slots_10.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[10].wakeup_ports[1].bits.uop.lrs3
connect slots_10.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[10].wakeup_ports[1].bits.uop.lrs2
connect slots_10.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[10].wakeup_ports[1].bits.uop.lrs1
connect slots_10.io.wakeup_ports[1].bits.uop.ldst, issue_slots[10].wakeup_ports[1].bits.uop.ldst
connect slots_10.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[10].wakeup_ports[1].bits.uop.ldst_is_rs1
connect slots_10.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[10].wakeup_ports[1].bits.uop.csr_cmd
connect slots_10.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[10].wakeup_ports[1].bits.uop.flush_on_commit
connect slots_10.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[10].wakeup_ports[1].bits.uop.is_unique
connect slots_10.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[10].wakeup_ports[1].bits.uop.uses_stq
connect slots_10.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[10].wakeup_ports[1].bits.uop.uses_ldq
connect slots_10.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[10].wakeup_ports[1].bits.uop.mem_signed
connect slots_10.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[10].wakeup_ports[1].bits.uop.mem_size
connect slots_10.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[10].wakeup_ports[1].bits.uop.mem_cmd
connect slots_10.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[10].wakeup_ports[1].bits.uop.exc_cause
connect slots_10.io.wakeup_ports[1].bits.uop.exception, issue_slots[10].wakeup_ports[1].bits.uop.exception
connect slots_10.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[10].wakeup_ports[1].bits.uop.stale_pdst
connect slots_10.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[10].wakeup_ports[1].bits.uop.ppred_busy
connect slots_10.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[10].wakeup_ports[1].bits.uop.prs3_busy
connect slots_10.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[10].wakeup_ports[1].bits.uop.prs2_busy
connect slots_10.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[10].wakeup_ports[1].bits.uop.prs1_busy
connect slots_10.io.wakeup_ports[1].bits.uop.ppred, issue_slots[10].wakeup_ports[1].bits.uop.ppred
connect slots_10.io.wakeup_ports[1].bits.uop.prs3, issue_slots[10].wakeup_ports[1].bits.uop.prs3
connect slots_10.io.wakeup_ports[1].bits.uop.prs2, issue_slots[10].wakeup_ports[1].bits.uop.prs2
connect slots_10.io.wakeup_ports[1].bits.uop.prs1, issue_slots[10].wakeup_ports[1].bits.uop.prs1
connect slots_10.io.wakeup_ports[1].bits.uop.pdst, issue_slots[10].wakeup_ports[1].bits.uop.pdst
connect slots_10.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[10].wakeup_ports[1].bits.uop.rxq_idx
connect slots_10.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[10].wakeup_ports[1].bits.uop.stq_idx
connect slots_10.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[10].wakeup_ports[1].bits.uop.ldq_idx
connect slots_10.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[10].wakeup_ports[1].bits.uop.rob_idx
connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.vec
connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.wflags
connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.sqrt
connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.div
connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.fma
connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe
connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.toint
connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.fromint
connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut
connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn
connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.swap23
connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.swap12
connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.ren3
connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.ren2
connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.ren1
connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.wen
connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.ldst
connect slots_10.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[10].wakeup_ports[1].bits.uop.op2_sel
connect slots_10.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[10].wakeup_ports[1].bits.uop.op1_sel
connect slots_10.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[10].wakeup_ports[1].bits.uop.imm_packed
connect slots_10.io.wakeup_ports[1].bits.uop.pimm, issue_slots[10].wakeup_ports[1].bits.uop.pimm
connect slots_10.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[10].wakeup_ports[1].bits.uop.imm_sel
connect slots_10.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[10].wakeup_ports[1].bits.uop.imm_rename
connect slots_10.io.wakeup_ports[1].bits.uop.taken, issue_slots[10].wakeup_ports[1].bits.uop.taken
connect slots_10.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[10].wakeup_ports[1].bits.uop.pc_lob
connect slots_10.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[10].wakeup_ports[1].bits.uop.edge_inst
connect slots_10.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[10].wakeup_ports[1].bits.uop.ftq_idx
connect slots_10.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[10].wakeup_ports[1].bits.uop.is_mov
connect slots_10.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[10].wakeup_ports[1].bits.uop.is_rocc
connect slots_10.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[10].wakeup_ports[1].bits.uop.is_sys_pc2epc
connect slots_10.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[10].wakeup_ports[1].bits.uop.is_eret
connect slots_10.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[10].wakeup_ports[1].bits.uop.is_amo
connect slots_10.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[10].wakeup_ports[1].bits.uop.is_sfence
connect slots_10.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[10].wakeup_ports[1].bits.uop.is_fencei
connect slots_10.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[10].wakeup_ports[1].bits.uop.is_fence
connect slots_10.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[10].wakeup_ports[1].bits.uop.is_sfb
connect slots_10.io.wakeup_ports[1].bits.uop.br_type, issue_slots[10].wakeup_ports[1].bits.uop.br_type
connect slots_10.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[10].wakeup_ports[1].bits.uop.br_tag
connect slots_10.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[10].wakeup_ports[1].bits.uop.br_mask
connect slots_10.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[10].wakeup_ports[1].bits.uop.dis_col_sel
connect slots_10.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[10].wakeup_ports[1].bits.uop.iw_p3_bypass_hint
connect slots_10.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[10].wakeup_ports[1].bits.uop.iw_p2_bypass_hint
connect slots_10.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[10].wakeup_ports[1].bits.uop.iw_p1_bypass_hint
connect slots_10.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[10].wakeup_ports[1].bits.uop.iw_p2_speculative_child
connect slots_10.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[10].wakeup_ports[1].bits.uop.iw_p1_speculative_child
connect slots_10.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[10].wakeup_ports[1].bits.uop.iw_issued_partial_dgen
connect slots_10.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[10].wakeup_ports[1].bits.uop.iw_issued_partial_agen
connect slots_10.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[10].wakeup_ports[1].bits.uop.iw_issued
connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[0]
connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[1]
connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[2]
connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[3]
connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[4]
connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[5]
connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[6]
connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[7]
connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[8]
connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[9]
connect slots_10.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[10].wakeup_ports[1].bits.uop.iq_type[0]
connect slots_10.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[10].wakeup_ports[1].bits.uop.iq_type[1]
connect slots_10.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[10].wakeup_ports[1].bits.uop.iq_type[2]
connect slots_10.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[10].wakeup_ports[1].bits.uop.iq_type[3]
connect slots_10.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[10].wakeup_ports[1].bits.uop.debug_pc
connect slots_10.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[10].wakeup_ports[1].bits.uop.is_rvc
connect slots_10.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[10].wakeup_ports[1].bits.uop.debug_inst
connect slots_10.io.wakeup_ports[1].bits.uop.inst, issue_slots[10].wakeup_ports[1].bits.uop.inst
connect slots_10.io.wakeup_ports[1].valid, issue_slots[10].wakeup_ports[1].valid
connect slots_10.io.wakeup_ports[2].bits.rebusy, issue_slots[10].wakeup_ports[2].bits.rebusy
connect slots_10.io.wakeup_ports[2].bits.speculative_mask, issue_slots[10].wakeup_ports[2].bits.speculative_mask
connect slots_10.io.wakeup_ports[2].bits.bypassable, issue_slots[10].wakeup_ports[2].bits.bypassable
connect slots_10.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[10].wakeup_ports[2].bits.uop.debug_tsrc
connect slots_10.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[10].wakeup_ports[2].bits.uop.debug_fsrc
connect slots_10.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[10].wakeup_ports[2].bits.uop.bp_xcpt_if
connect slots_10.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[10].wakeup_ports[2].bits.uop.bp_debug_if
connect slots_10.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[10].wakeup_ports[2].bits.uop.xcpt_ma_if
connect slots_10.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[10].wakeup_ports[2].bits.uop.xcpt_ae_if
connect slots_10.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[10].wakeup_ports[2].bits.uop.xcpt_pf_if
connect slots_10.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[10].wakeup_ports[2].bits.uop.fp_typ
connect slots_10.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[10].wakeup_ports[2].bits.uop.fp_rm
connect slots_10.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[10].wakeup_ports[2].bits.uop.fp_val
connect slots_10.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[10].wakeup_ports[2].bits.uop.fcn_op
connect slots_10.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[10].wakeup_ports[2].bits.uop.fcn_dw
connect slots_10.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[10].wakeup_ports[2].bits.uop.frs3_en
connect slots_10.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[10].wakeup_ports[2].bits.uop.lrs2_rtype
connect slots_10.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[10].wakeup_ports[2].bits.uop.lrs1_rtype
connect slots_10.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[10].wakeup_ports[2].bits.uop.dst_rtype
connect slots_10.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[10].wakeup_ports[2].bits.uop.lrs3
connect slots_10.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[10].wakeup_ports[2].bits.uop.lrs2
connect slots_10.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[10].wakeup_ports[2].bits.uop.lrs1
connect slots_10.io.wakeup_ports[2].bits.uop.ldst, issue_slots[10].wakeup_ports[2].bits.uop.ldst
connect slots_10.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[10].wakeup_ports[2].bits.uop.ldst_is_rs1
connect slots_10.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[10].wakeup_ports[2].bits.uop.csr_cmd
connect slots_10.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[10].wakeup_ports[2].bits.uop.flush_on_commit
connect slots_10.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[10].wakeup_ports[2].bits.uop.is_unique
connect slots_10.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[10].wakeup_ports[2].bits.uop.uses_stq
connect slots_10.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[10].wakeup_ports[2].bits.uop.uses_ldq
connect slots_10.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[10].wakeup_ports[2].bits.uop.mem_signed
connect slots_10.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[10].wakeup_ports[2].bits.uop.mem_size
connect slots_10.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[10].wakeup_ports[2].bits.uop.mem_cmd
connect slots_10.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[10].wakeup_ports[2].bits.uop.exc_cause
connect slots_10.io.wakeup_ports[2].bits.uop.exception, issue_slots[10].wakeup_ports[2].bits.uop.exception
connect slots_10.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[10].wakeup_ports[2].bits.uop.stale_pdst
connect slots_10.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[10].wakeup_ports[2].bits.uop.ppred_busy
connect slots_10.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[10].wakeup_ports[2].bits.uop.prs3_busy
connect slots_10.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[10].wakeup_ports[2].bits.uop.prs2_busy
connect slots_10.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[10].wakeup_ports[2].bits.uop.prs1_busy
connect slots_10.io.wakeup_ports[2].bits.uop.ppred, issue_slots[10].wakeup_ports[2].bits.uop.ppred
connect slots_10.io.wakeup_ports[2].bits.uop.prs3, issue_slots[10].wakeup_ports[2].bits.uop.prs3
connect slots_10.io.wakeup_ports[2].bits.uop.prs2, issue_slots[10].wakeup_ports[2].bits.uop.prs2
connect slots_10.io.wakeup_ports[2].bits.uop.prs1, issue_slots[10].wakeup_ports[2].bits.uop.prs1
connect slots_10.io.wakeup_ports[2].bits.uop.pdst, issue_slots[10].wakeup_ports[2].bits.uop.pdst
connect slots_10.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[10].wakeup_ports[2].bits.uop.rxq_idx
connect slots_10.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[10].wakeup_ports[2].bits.uop.stq_idx
connect slots_10.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[10].wakeup_ports[2].bits.uop.ldq_idx
connect slots_10.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[10].wakeup_ports[2].bits.uop.rob_idx
connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.vec
connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.wflags
connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.sqrt
connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.div
connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.fma
connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe
connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.toint
connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.fromint
connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut
connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn
connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.swap23
connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.swap12
connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.ren3
connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.ren2
connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.ren1
connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.wen
connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.ldst
connect slots_10.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[10].wakeup_ports[2].bits.uop.op2_sel
connect slots_10.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[10].wakeup_ports[2].bits.uop.op1_sel
connect slots_10.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[10].wakeup_ports[2].bits.uop.imm_packed
connect slots_10.io.wakeup_ports[2].bits.uop.pimm, issue_slots[10].wakeup_ports[2].bits.uop.pimm
connect slots_10.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[10].wakeup_ports[2].bits.uop.imm_sel
connect slots_10.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[10].wakeup_ports[2].bits.uop.imm_rename
connect slots_10.io.wakeup_ports[2].bits.uop.taken, issue_slots[10].wakeup_ports[2].bits.uop.taken
connect slots_10.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[10].wakeup_ports[2].bits.uop.pc_lob
connect slots_10.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[10].wakeup_ports[2].bits.uop.edge_inst
connect slots_10.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[10].wakeup_ports[2].bits.uop.ftq_idx
connect slots_10.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[10].wakeup_ports[2].bits.uop.is_mov
connect slots_10.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[10].wakeup_ports[2].bits.uop.is_rocc
connect slots_10.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[10].wakeup_ports[2].bits.uop.is_sys_pc2epc
connect slots_10.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[10].wakeup_ports[2].bits.uop.is_eret
connect slots_10.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[10].wakeup_ports[2].bits.uop.is_amo
connect slots_10.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[10].wakeup_ports[2].bits.uop.is_sfence
connect slots_10.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[10].wakeup_ports[2].bits.uop.is_fencei
connect slots_10.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[10].wakeup_ports[2].bits.uop.is_fence
connect slots_10.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[10].wakeup_ports[2].bits.uop.is_sfb
connect slots_10.io.wakeup_ports[2].bits.uop.br_type, issue_slots[10].wakeup_ports[2].bits.uop.br_type
connect slots_10.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[10].wakeup_ports[2].bits.uop.br_tag
connect slots_10.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[10].wakeup_ports[2].bits.uop.br_mask
connect slots_10.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[10].wakeup_ports[2].bits.uop.dis_col_sel
connect slots_10.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[10].wakeup_ports[2].bits.uop.iw_p3_bypass_hint
connect slots_10.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[10].wakeup_ports[2].bits.uop.iw_p2_bypass_hint
connect slots_10.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[10].wakeup_ports[2].bits.uop.iw_p1_bypass_hint
connect slots_10.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[10].wakeup_ports[2].bits.uop.iw_p2_speculative_child
connect slots_10.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[10].wakeup_ports[2].bits.uop.iw_p1_speculative_child
connect slots_10.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[10].wakeup_ports[2].bits.uop.iw_issued_partial_dgen
connect slots_10.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[10].wakeup_ports[2].bits.uop.iw_issued_partial_agen
connect slots_10.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[10].wakeup_ports[2].bits.uop.iw_issued
connect slots_10.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[10].wakeup_ports[2].bits.uop.fu_code[0]
connect slots_10.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[10].wakeup_ports[2].bits.uop.fu_code[1]
connect slots_10.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[10].wakeup_ports[2].bits.uop.fu_code[2]
connect slots_10.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[10].wakeup_ports[2].bits.uop.fu_code[3]
connect slots_10.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[10].wakeup_ports[2].bits.uop.fu_code[4]
connect slots_10.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[10].wakeup_ports[2].bits.uop.fu_code[5]
connect slots_10.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[10].wakeup_ports[2].bits.uop.fu_code[6]
connect slots_10.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[10].wakeup_ports[2].bits.uop.fu_code[7]
connect slots_10.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[10].wakeup_ports[2].bits.uop.fu_code[8]
connect slots_10.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[10].wakeup_ports[2].bits.uop.fu_code[9]
connect slots_10.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[10].wakeup_ports[2].bits.uop.iq_type[0]
connect slots_10.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[10].wakeup_ports[2].bits.uop.iq_type[1]
connect slots_10.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[10].wakeup_ports[2].bits.uop.iq_type[2]
connect slots_10.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[10].wakeup_ports[2].bits.uop.iq_type[3]
connect slots_10.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[10].wakeup_ports[2].bits.uop.debug_pc
connect slots_10.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[10].wakeup_ports[2].bits.uop.is_rvc
connect slots_10.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[10].wakeup_ports[2].bits.uop.debug_inst
connect slots_10.io.wakeup_ports[2].bits.uop.inst, issue_slots[10].wakeup_ports[2].bits.uop.inst
connect slots_10.io.wakeup_ports[2].valid, issue_slots[10].wakeup_ports[2].valid
connect slots_10.io.wakeup_ports[3].bits.rebusy, issue_slots[10].wakeup_ports[3].bits.rebusy
connect slots_10.io.wakeup_ports[3].bits.speculative_mask, issue_slots[10].wakeup_ports[3].bits.speculative_mask
connect slots_10.io.wakeup_ports[3].bits.bypassable, issue_slots[10].wakeup_ports[3].bits.bypassable
connect slots_10.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[10].wakeup_ports[3].bits.uop.debug_tsrc
connect slots_10.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[10].wakeup_ports[3].bits.uop.debug_fsrc
connect slots_10.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[10].wakeup_ports[3].bits.uop.bp_xcpt_if
connect slots_10.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[10].wakeup_ports[3].bits.uop.bp_debug_if
connect slots_10.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[10].wakeup_ports[3].bits.uop.xcpt_ma_if
connect slots_10.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[10].wakeup_ports[3].bits.uop.xcpt_ae_if
connect slots_10.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[10].wakeup_ports[3].bits.uop.xcpt_pf_if
connect slots_10.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[10].wakeup_ports[3].bits.uop.fp_typ
connect slots_10.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[10].wakeup_ports[3].bits.uop.fp_rm
connect slots_10.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[10].wakeup_ports[3].bits.uop.fp_val
connect slots_10.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[10].wakeup_ports[3].bits.uop.fcn_op
connect slots_10.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[10].wakeup_ports[3].bits.uop.fcn_dw
connect slots_10.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[10].wakeup_ports[3].bits.uop.frs3_en
connect slots_10.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[10].wakeup_ports[3].bits.uop.lrs2_rtype
connect slots_10.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[10].wakeup_ports[3].bits.uop.lrs1_rtype
connect slots_10.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[10].wakeup_ports[3].bits.uop.dst_rtype
connect slots_10.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[10].wakeup_ports[3].bits.uop.lrs3
connect slots_10.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[10].wakeup_ports[3].bits.uop.lrs2
connect slots_10.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[10].wakeup_ports[3].bits.uop.lrs1
connect slots_10.io.wakeup_ports[3].bits.uop.ldst, issue_slots[10].wakeup_ports[3].bits.uop.ldst
connect slots_10.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[10].wakeup_ports[3].bits.uop.ldst_is_rs1
connect slots_10.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[10].wakeup_ports[3].bits.uop.csr_cmd
connect slots_10.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[10].wakeup_ports[3].bits.uop.flush_on_commit
connect slots_10.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[10].wakeup_ports[3].bits.uop.is_unique
connect slots_10.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[10].wakeup_ports[3].bits.uop.uses_stq
connect slots_10.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[10].wakeup_ports[3].bits.uop.uses_ldq
connect slots_10.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[10].wakeup_ports[3].bits.uop.mem_signed
connect slots_10.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[10].wakeup_ports[3].bits.uop.mem_size
connect slots_10.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[10].wakeup_ports[3].bits.uop.mem_cmd
connect slots_10.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[10].wakeup_ports[3].bits.uop.exc_cause
connect slots_10.io.wakeup_ports[3].bits.uop.exception, issue_slots[10].wakeup_ports[3].bits.uop.exception
connect slots_10.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[10].wakeup_ports[3].bits.uop.stale_pdst
connect slots_10.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[10].wakeup_ports[3].bits.uop.ppred_busy
connect slots_10.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[10].wakeup_ports[3].bits.uop.prs3_busy
connect slots_10.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[10].wakeup_ports[3].bits.uop.prs2_busy
connect slots_10.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[10].wakeup_ports[3].bits.uop.prs1_busy
connect slots_10.io.wakeup_ports[3].bits.uop.ppred, issue_slots[10].wakeup_ports[3].bits.uop.ppred
connect slots_10.io.wakeup_ports[3].bits.uop.prs3, issue_slots[10].wakeup_ports[3].bits.uop.prs3
connect slots_10.io.wakeup_ports[3].bits.uop.prs2, issue_slots[10].wakeup_ports[3].bits.uop.prs2
connect slots_10.io.wakeup_ports[3].bits.uop.prs1, issue_slots[10].wakeup_ports[3].bits.uop.prs1
connect slots_10.io.wakeup_ports[3].bits.uop.pdst, issue_slots[10].wakeup_ports[3].bits.uop.pdst
connect slots_10.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[10].wakeup_ports[3].bits.uop.rxq_idx
connect slots_10.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[10].wakeup_ports[3].bits.uop.stq_idx
connect slots_10.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[10].wakeup_ports[3].bits.uop.ldq_idx
connect slots_10.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[10].wakeup_ports[3].bits.uop.rob_idx
connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.vec
connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.wflags
connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.sqrt
connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.div
connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.fma
connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe
connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.toint
connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.fromint
connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut
connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn
connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.swap23
connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.swap12
connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.ren3
connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.ren2
connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.ren1
connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.wen
connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.ldst
connect slots_10.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[10].wakeup_ports[3].bits.uop.op2_sel
connect slots_10.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[10].wakeup_ports[3].bits.uop.op1_sel
connect slots_10.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[10].wakeup_ports[3].bits.uop.imm_packed
connect slots_10.io.wakeup_ports[3].bits.uop.pimm, issue_slots[10].wakeup_ports[3].bits.uop.pimm
connect slots_10.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[10].wakeup_ports[3].bits.uop.imm_sel
connect slots_10.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[10].wakeup_ports[3].bits.uop.imm_rename
connect slots_10.io.wakeup_ports[3].bits.uop.taken, issue_slots[10].wakeup_ports[3].bits.uop.taken
connect slots_10.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[10].wakeup_ports[3].bits.uop.pc_lob
connect slots_10.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[10].wakeup_ports[3].bits.uop.edge_inst
connect slots_10.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[10].wakeup_ports[3].bits.uop.ftq_idx
connect slots_10.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[10].wakeup_ports[3].bits.uop.is_mov
connect slots_10.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[10].wakeup_ports[3].bits.uop.is_rocc
connect slots_10.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[10].wakeup_ports[3].bits.uop.is_sys_pc2epc
connect slots_10.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[10].wakeup_ports[3].bits.uop.is_eret
connect slots_10.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[10].wakeup_ports[3].bits.uop.is_amo
connect slots_10.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[10].wakeup_ports[3].bits.uop.is_sfence
connect slots_10.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[10].wakeup_ports[3].bits.uop.is_fencei
connect slots_10.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[10].wakeup_ports[3].bits.uop.is_fence
connect slots_10.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[10].wakeup_ports[3].bits.uop.is_sfb
connect slots_10.io.wakeup_ports[3].bits.uop.br_type, issue_slots[10].wakeup_ports[3].bits.uop.br_type
connect slots_10.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[10].wakeup_ports[3].bits.uop.br_tag
connect slots_10.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[10].wakeup_ports[3].bits.uop.br_mask
connect slots_10.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[10].wakeup_ports[3].bits.uop.dis_col_sel
connect slots_10.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[10].wakeup_ports[3].bits.uop.iw_p3_bypass_hint
connect slots_10.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[10].wakeup_ports[3].bits.uop.iw_p2_bypass_hint
connect slots_10.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[10].wakeup_ports[3].bits.uop.iw_p1_bypass_hint
connect slots_10.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[10].wakeup_ports[3].bits.uop.iw_p2_speculative_child
connect slots_10.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[10].wakeup_ports[3].bits.uop.iw_p1_speculative_child
connect slots_10.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[10].wakeup_ports[3].bits.uop.iw_issued_partial_dgen
connect slots_10.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[10].wakeup_ports[3].bits.uop.iw_issued_partial_agen
connect slots_10.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[10].wakeup_ports[3].bits.uop.iw_issued
connect slots_10.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[10].wakeup_ports[3].bits.uop.fu_code[0]
connect slots_10.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[10].wakeup_ports[3].bits.uop.fu_code[1]
connect slots_10.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[10].wakeup_ports[3].bits.uop.fu_code[2]
connect slots_10.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[10].wakeup_ports[3].bits.uop.fu_code[3]
connect slots_10.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[10].wakeup_ports[3].bits.uop.fu_code[4]
connect slots_10.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[10].wakeup_ports[3].bits.uop.fu_code[5]
connect slots_10.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[10].wakeup_ports[3].bits.uop.fu_code[6]
connect slots_10.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[10].wakeup_ports[3].bits.uop.fu_code[7]
connect slots_10.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[10].wakeup_ports[3].bits.uop.fu_code[8]
connect slots_10.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[10].wakeup_ports[3].bits.uop.fu_code[9]
connect slots_10.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[10].wakeup_ports[3].bits.uop.iq_type[0]
connect slots_10.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[10].wakeup_ports[3].bits.uop.iq_type[1]
connect slots_10.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[10].wakeup_ports[3].bits.uop.iq_type[2]
connect slots_10.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[10].wakeup_ports[3].bits.uop.iq_type[3]
connect slots_10.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[10].wakeup_ports[3].bits.uop.debug_pc
connect slots_10.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[10].wakeup_ports[3].bits.uop.is_rvc
connect slots_10.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[10].wakeup_ports[3].bits.uop.debug_inst
connect slots_10.io.wakeup_ports[3].bits.uop.inst, issue_slots[10].wakeup_ports[3].bits.uop.inst
connect slots_10.io.wakeup_ports[3].valid, issue_slots[10].wakeup_ports[3].valid
connect slots_10.io.squash_grant, issue_slots[10].squash_grant
connect slots_10.io.clear, issue_slots[10].clear
connect slots_10.io.kill, issue_slots[10].kill
connect slots_10.io.brupdate.b2.target_offset, issue_slots[10].brupdate.b2.target_offset
connect slots_10.io.brupdate.b2.jalr_target, issue_slots[10].brupdate.b2.jalr_target
connect slots_10.io.brupdate.b2.pc_sel, issue_slots[10].brupdate.b2.pc_sel
connect slots_10.io.brupdate.b2.cfi_type, issue_slots[10].brupdate.b2.cfi_type
connect slots_10.io.brupdate.b2.taken, issue_slots[10].brupdate.b2.taken
connect slots_10.io.brupdate.b2.mispredict, issue_slots[10].brupdate.b2.mispredict
connect slots_10.io.brupdate.b2.uop.debug_tsrc, issue_slots[10].brupdate.b2.uop.debug_tsrc
connect slots_10.io.brupdate.b2.uop.debug_fsrc, issue_slots[10].brupdate.b2.uop.debug_fsrc
connect slots_10.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[10].brupdate.b2.uop.bp_xcpt_if
connect slots_10.io.brupdate.b2.uop.bp_debug_if, issue_slots[10].brupdate.b2.uop.bp_debug_if
connect slots_10.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[10].brupdate.b2.uop.xcpt_ma_if
connect slots_10.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[10].brupdate.b2.uop.xcpt_ae_if
connect slots_10.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[10].brupdate.b2.uop.xcpt_pf_if
connect slots_10.io.brupdate.b2.uop.fp_typ, issue_slots[10].brupdate.b2.uop.fp_typ
connect slots_10.io.brupdate.b2.uop.fp_rm, issue_slots[10].brupdate.b2.uop.fp_rm
connect slots_10.io.brupdate.b2.uop.fp_val, issue_slots[10].brupdate.b2.uop.fp_val
connect slots_10.io.brupdate.b2.uop.fcn_op, issue_slots[10].brupdate.b2.uop.fcn_op
connect slots_10.io.brupdate.b2.uop.fcn_dw, issue_slots[10].brupdate.b2.uop.fcn_dw
connect slots_10.io.brupdate.b2.uop.frs3_en, issue_slots[10].brupdate.b2.uop.frs3_en
connect slots_10.io.brupdate.b2.uop.lrs2_rtype, issue_slots[10].brupdate.b2.uop.lrs2_rtype
connect slots_10.io.brupdate.b2.uop.lrs1_rtype, issue_slots[10].brupdate.b2.uop.lrs1_rtype
connect slots_10.io.brupdate.b2.uop.dst_rtype, issue_slots[10].brupdate.b2.uop.dst_rtype
connect slots_10.io.brupdate.b2.uop.lrs3, issue_slots[10].brupdate.b2.uop.lrs3
connect slots_10.io.brupdate.b2.uop.lrs2, issue_slots[10].brupdate.b2.uop.lrs2
connect slots_10.io.brupdate.b2.uop.lrs1, issue_slots[10].brupdate.b2.uop.lrs1
connect slots_10.io.brupdate.b2.uop.ldst, issue_slots[10].brupdate.b2.uop.ldst
connect slots_10.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[10].brupdate.b2.uop.ldst_is_rs1
connect slots_10.io.brupdate.b2.uop.csr_cmd, issue_slots[10].brupdate.b2.uop.csr_cmd
connect slots_10.io.brupdate.b2.uop.flush_on_commit, issue_slots[10].brupdate.b2.uop.flush_on_commit
connect slots_10.io.brupdate.b2.uop.is_unique, issue_slots[10].brupdate.b2.uop.is_unique
connect slots_10.io.brupdate.b2.uop.uses_stq, issue_slots[10].brupdate.b2.uop.uses_stq
connect slots_10.io.brupdate.b2.uop.uses_ldq, issue_slots[10].brupdate.b2.uop.uses_ldq
connect slots_10.io.brupdate.b2.uop.mem_signed, issue_slots[10].brupdate.b2.uop.mem_signed
connect slots_10.io.brupdate.b2.uop.mem_size, issue_slots[10].brupdate.b2.uop.mem_size
connect slots_10.io.brupdate.b2.uop.mem_cmd, issue_slots[10].brupdate.b2.uop.mem_cmd
connect slots_10.io.brupdate.b2.uop.exc_cause, issue_slots[10].brupdate.b2.uop.exc_cause
connect slots_10.io.brupdate.b2.uop.exception, issue_slots[10].brupdate.b2.uop.exception
connect slots_10.io.brupdate.b2.uop.stale_pdst, issue_slots[10].brupdate.b2.uop.stale_pdst
connect slots_10.io.brupdate.b2.uop.ppred_busy, issue_slots[10].brupdate.b2.uop.ppred_busy
connect slots_10.io.brupdate.b2.uop.prs3_busy, issue_slots[10].brupdate.b2.uop.prs3_busy
connect slots_10.io.brupdate.b2.uop.prs2_busy, issue_slots[10].brupdate.b2.uop.prs2_busy
connect slots_10.io.brupdate.b2.uop.prs1_busy, issue_slots[10].brupdate.b2.uop.prs1_busy
connect slots_10.io.brupdate.b2.uop.ppred, issue_slots[10].brupdate.b2.uop.ppred
connect slots_10.io.brupdate.b2.uop.prs3, issue_slots[10].brupdate.b2.uop.prs3
connect slots_10.io.brupdate.b2.uop.prs2, issue_slots[10].brupdate.b2.uop.prs2
connect slots_10.io.brupdate.b2.uop.prs1, issue_slots[10].brupdate.b2.uop.prs1
connect slots_10.io.brupdate.b2.uop.pdst, issue_slots[10].brupdate.b2.uop.pdst
connect slots_10.io.brupdate.b2.uop.rxq_idx, issue_slots[10].brupdate.b2.uop.rxq_idx
connect slots_10.io.brupdate.b2.uop.stq_idx, issue_slots[10].brupdate.b2.uop.stq_idx
connect slots_10.io.brupdate.b2.uop.ldq_idx, issue_slots[10].brupdate.b2.uop.ldq_idx
connect slots_10.io.brupdate.b2.uop.rob_idx, issue_slots[10].brupdate.b2.uop.rob_idx
connect slots_10.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[10].brupdate.b2.uop.fp_ctrl.vec
connect slots_10.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[10].brupdate.b2.uop.fp_ctrl.wflags
connect slots_10.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[10].brupdate.b2.uop.fp_ctrl.sqrt
connect slots_10.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[10].brupdate.b2.uop.fp_ctrl.div
connect slots_10.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[10].brupdate.b2.uop.fp_ctrl.fma
connect slots_10.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[10].brupdate.b2.uop.fp_ctrl.fastpipe
connect slots_10.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[10].brupdate.b2.uop.fp_ctrl.toint
connect slots_10.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[10].brupdate.b2.uop.fp_ctrl.fromint
connect slots_10.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[10].brupdate.b2.uop.fp_ctrl.typeTagOut
connect slots_10.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[10].brupdate.b2.uop.fp_ctrl.typeTagIn
connect slots_10.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[10].brupdate.b2.uop.fp_ctrl.swap23
connect slots_10.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[10].brupdate.b2.uop.fp_ctrl.swap12
connect slots_10.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[10].brupdate.b2.uop.fp_ctrl.ren3
connect slots_10.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[10].brupdate.b2.uop.fp_ctrl.ren2
connect slots_10.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[10].brupdate.b2.uop.fp_ctrl.ren1
connect slots_10.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[10].brupdate.b2.uop.fp_ctrl.wen
connect slots_10.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[10].brupdate.b2.uop.fp_ctrl.ldst
connect slots_10.io.brupdate.b2.uop.op2_sel, issue_slots[10].brupdate.b2.uop.op2_sel
connect slots_10.io.brupdate.b2.uop.op1_sel, issue_slots[10].brupdate.b2.uop.op1_sel
connect slots_10.io.brupdate.b2.uop.imm_packed, issue_slots[10].brupdate.b2.uop.imm_packed
connect slots_10.io.brupdate.b2.uop.pimm, issue_slots[10].brupdate.b2.uop.pimm
connect slots_10.io.brupdate.b2.uop.imm_sel, issue_slots[10].brupdate.b2.uop.imm_sel
connect slots_10.io.brupdate.b2.uop.imm_rename, issue_slots[10].brupdate.b2.uop.imm_rename
connect slots_10.io.brupdate.b2.uop.taken, issue_slots[10].brupdate.b2.uop.taken
connect slots_10.io.brupdate.b2.uop.pc_lob, issue_slots[10].brupdate.b2.uop.pc_lob
connect slots_10.io.brupdate.b2.uop.edge_inst, issue_slots[10].brupdate.b2.uop.edge_inst
connect slots_10.io.brupdate.b2.uop.ftq_idx, issue_slots[10].brupdate.b2.uop.ftq_idx
connect slots_10.io.brupdate.b2.uop.is_mov, issue_slots[10].brupdate.b2.uop.is_mov
connect slots_10.io.brupdate.b2.uop.is_rocc, issue_slots[10].brupdate.b2.uop.is_rocc
connect slots_10.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[10].brupdate.b2.uop.is_sys_pc2epc
connect slots_10.io.brupdate.b2.uop.is_eret, issue_slots[10].brupdate.b2.uop.is_eret
connect slots_10.io.brupdate.b2.uop.is_amo, issue_slots[10].brupdate.b2.uop.is_amo
connect slots_10.io.brupdate.b2.uop.is_sfence, issue_slots[10].brupdate.b2.uop.is_sfence
connect slots_10.io.brupdate.b2.uop.is_fencei, issue_slots[10].brupdate.b2.uop.is_fencei
connect slots_10.io.brupdate.b2.uop.is_fence, issue_slots[10].brupdate.b2.uop.is_fence
connect slots_10.io.brupdate.b2.uop.is_sfb, issue_slots[10].brupdate.b2.uop.is_sfb
connect slots_10.io.brupdate.b2.uop.br_type, issue_slots[10].brupdate.b2.uop.br_type
connect slots_10.io.brupdate.b2.uop.br_tag, issue_slots[10].brupdate.b2.uop.br_tag
connect slots_10.io.brupdate.b2.uop.br_mask, issue_slots[10].brupdate.b2.uop.br_mask
connect slots_10.io.brupdate.b2.uop.dis_col_sel, issue_slots[10].brupdate.b2.uop.dis_col_sel
connect slots_10.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[10].brupdate.b2.uop.iw_p3_bypass_hint
connect slots_10.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[10].brupdate.b2.uop.iw_p2_bypass_hint
connect slots_10.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[10].brupdate.b2.uop.iw_p1_bypass_hint
connect slots_10.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[10].brupdate.b2.uop.iw_p2_speculative_child
connect slots_10.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[10].brupdate.b2.uop.iw_p1_speculative_child
connect slots_10.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[10].brupdate.b2.uop.iw_issued_partial_dgen
connect slots_10.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[10].brupdate.b2.uop.iw_issued_partial_agen
connect slots_10.io.brupdate.b2.uop.iw_issued, issue_slots[10].brupdate.b2.uop.iw_issued
connect slots_10.io.brupdate.b2.uop.fu_code[0], issue_slots[10].brupdate.b2.uop.fu_code[0]
connect slots_10.io.brupdate.b2.uop.fu_code[1], issue_slots[10].brupdate.b2.uop.fu_code[1]
connect slots_10.io.brupdate.b2.uop.fu_code[2], issue_slots[10].brupdate.b2.uop.fu_code[2]
connect slots_10.io.brupdate.b2.uop.fu_code[3], issue_slots[10].brupdate.b2.uop.fu_code[3]
connect slots_10.io.brupdate.b2.uop.fu_code[4], issue_slots[10].brupdate.b2.uop.fu_code[4]
connect slots_10.io.brupdate.b2.uop.fu_code[5], issue_slots[10].brupdate.b2.uop.fu_code[5]
connect slots_10.io.brupdate.b2.uop.fu_code[6], issue_slots[10].brupdate.b2.uop.fu_code[6]
connect slots_10.io.brupdate.b2.uop.fu_code[7], issue_slots[10].brupdate.b2.uop.fu_code[7]
connect slots_10.io.brupdate.b2.uop.fu_code[8], issue_slots[10].brupdate.b2.uop.fu_code[8]
connect slots_10.io.brupdate.b2.uop.fu_code[9], issue_slots[10].brupdate.b2.uop.fu_code[9]
connect slots_10.io.brupdate.b2.uop.iq_type[0], issue_slots[10].brupdate.b2.uop.iq_type[0]
connect slots_10.io.brupdate.b2.uop.iq_type[1], issue_slots[10].brupdate.b2.uop.iq_type[1]
connect slots_10.io.brupdate.b2.uop.iq_type[2], issue_slots[10].brupdate.b2.uop.iq_type[2]
connect slots_10.io.brupdate.b2.uop.iq_type[3], issue_slots[10].brupdate.b2.uop.iq_type[3]
connect slots_10.io.brupdate.b2.uop.debug_pc, issue_slots[10].brupdate.b2.uop.debug_pc
connect slots_10.io.brupdate.b2.uop.is_rvc, issue_slots[10].brupdate.b2.uop.is_rvc
connect slots_10.io.brupdate.b2.uop.debug_inst, issue_slots[10].brupdate.b2.uop.debug_inst
connect slots_10.io.brupdate.b2.uop.inst, issue_slots[10].brupdate.b2.uop.inst
connect slots_10.io.brupdate.b1.mispredict_mask, issue_slots[10].brupdate.b1.mispredict_mask
connect slots_10.io.brupdate.b1.resolve_mask, issue_slots[10].brupdate.b1.resolve_mask
connect issue_slots[10].out_uop.debug_tsrc, slots_10.io.out_uop.debug_tsrc
connect issue_slots[10].out_uop.debug_fsrc, slots_10.io.out_uop.debug_fsrc
connect issue_slots[10].out_uop.bp_xcpt_if, slots_10.io.out_uop.bp_xcpt_if
connect issue_slots[10].out_uop.bp_debug_if, slots_10.io.out_uop.bp_debug_if
connect issue_slots[10].out_uop.xcpt_ma_if, slots_10.io.out_uop.xcpt_ma_if
connect issue_slots[10].out_uop.xcpt_ae_if, slots_10.io.out_uop.xcpt_ae_if
connect issue_slots[10].out_uop.xcpt_pf_if, slots_10.io.out_uop.xcpt_pf_if
connect issue_slots[10].out_uop.fp_typ, slots_10.io.out_uop.fp_typ
connect issue_slots[10].out_uop.fp_rm, slots_10.io.out_uop.fp_rm
connect issue_slots[10].out_uop.fp_val, slots_10.io.out_uop.fp_val
connect issue_slots[10].out_uop.fcn_op, slots_10.io.out_uop.fcn_op
connect issue_slots[10].out_uop.fcn_dw, slots_10.io.out_uop.fcn_dw
connect issue_slots[10].out_uop.frs3_en, slots_10.io.out_uop.frs3_en
connect issue_slots[10].out_uop.lrs2_rtype, slots_10.io.out_uop.lrs2_rtype
connect issue_slots[10].out_uop.lrs1_rtype, slots_10.io.out_uop.lrs1_rtype
connect issue_slots[10].out_uop.dst_rtype, slots_10.io.out_uop.dst_rtype
connect issue_slots[10].out_uop.lrs3, slots_10.io.out_uop.lrs3
connect issue_slots[10].out_uop.lrs2, slots_10.io.out_uop.lrs2
connect issue_slots[10].out_uop.lrs1, slots_10.io.out_uop.lrs1
connect issue_slots[10].out_uop.ldst, slots_10.io.out_uop.ldst
connect issue_slots[10].out_uop.ldst_is_rs1, slots_10.io.out_uop.ldst_is_rs1
connect issue_slots[10].out_uop.csr_cmd, slots_10.io.out_uop.csr_cmd
connect issue_slots[10].out_uop.flush_on_commit, slots_10.io.out_uop.flush_on_commit
connect issue_slots[10].out_uop.is_unique, slots_10.io.out_uop.is_unique
connect issue_slots[10].out_uop.uses_stq, slots_10.io.out_uop.uses_stq
connect issue_slots[10].out_uop.uses_ldq, slots_10.io.out_uop.uses_ldq
connect issue_slots[10].out_uop.mem_signed, slots_10.io.out_uop.mem_signed
connect issue_slots[10].out_uop.mem_size, slots_10.io.out_uop.mem_size
connect issue_slots[10].out_uop.mem_cmd, slots_10.io.out_uop.mem_cmd
connect issue_slots[10].out_uop.exc_cause, slots_10.io.out_uop.exc_cause
connect issue_slots[10].out_uop.exception, slots_10.io.out_uop.exception
connect issue_slots[10].out_uop.stale_pdst, slots_10.io.out_uop.stale_pdst
connect issue_slots[10].out_uop.ppred_busy, slots_10.io.out_uop.ppred_busy
connect issue_slots[10].out_uop.prs3_busy, slots_10.io.out_uop.prs3_busy
connect issue_slots[10].out_uop.prs2_busy, slots_10.io.out_uop.prs2_busy
connect issue_slots[10].out_uop.prs1_busy, slots_10.io.out_uop.prs1_busy
connect issue_slots[10].out_uop.ppred, slots_10.io.out_uop.ppred
connect issue_slots[10].out_uop.prs3, slots_10.io.out_uop.prs3
connect issue_slots[10].out_uop.prs2, slots_10.io.out_uop.prs2
connect issue_slots[10].out_uop.prs1, slots_10.io.out_uop.prs1
connect issue_slots[10].out_uop.pdst, slots_10.io.out_uop.pdst
connect issue_slots[10].out_uop.rxq_idx, slots_10.io.out_uop.rxq_idx
connect issue_slots[10].out_uop.stq_idx, slots_10.io.out_uop.stq_idx
connect issue_slots[10].out_uop.ldq_idx, slots_10.io.out_uop.ldq_idx
connect issue_slots[10].out_uop.rob_idx, slots_10.io.out_uop.rob_idx
connect issue_slots[10].out_uop.fp_ctrl.vec, slots_10.io.out_uop.fp_ctrl.vec
connect issue_slots[10].out_uop.fp_ctrl.wflags, slots_10.io.out_uop.fp_ctrl.wflags
connect issue_slots[10].out_uop.fp_ctrl.sqrt, slots_10.io.out_uop.fp_ctrl.sqrt
connect issue_slots[10].out_uop.fp_ctrl.div, slots_10.io.out_uop.fp_ctrl.div
connect issue_slots[10].out_uop.fp_ctrl.fma, slots_10.io.out_uop.fp_ctrl.fma
connect issue_slots[10].out_uop.fp_ctrl.fastpipe, slots_10.io.out_uop.fp_ctrl.fastpipe
connect issue_slots[10].out_uop.fp_ctrl.toint, slots_10.io.out_uop.fp_ctrl.toint
connect issue_slots[10].out_uop.fp_ctrl.fromint, slots_10.io.out_uop.fp_ctrl.fromint
connect issue_slots[10].out_uop.fp_ctrl.typeTagOut, slots_10.io.out_uop.fp_ctrl.typeTagOut
connect issue_slots[10].out_uop.fp_ctrl.typeTagIn, slots_10.io.out_uop.fp_ctrl.typeTagIn
connect issue_slots[10].out_uop.fp_ctrl.swap23, slots_10.io.out_uop.fp_ctrl.swap23
connect issue_slots[10].out_uop.fp_ctrl.swap12, slots_10.io.out_uop.fp_ctrl.swap12
connect issue_slots[10].out_uop.fp_ctrl.ren3, slots_10.io.out_uop.fp_ctrl.ren3
connect issue_slots[10].out_uop.fp_ctrl.ren2, slots_10.io.out_uop.fp_ctrl.ren2
connect issue_slots[10].out_uop.fp_ctrl.ren1, slots_10.io.out_uop.fp_ctrl.ren1
connect issue_slots[10].out_uop.fp_ctrl.wen, slots_10.io.out_uop.fp_ctrl.wen
connect issue_slots[10].out_uop.fp_ctrl.ldst, slots_10.io.out_uop.fp_ctrl.ldst
connect issue_slots[10].out_uop.op2_sel, slots_10.io.out_uop.op2_sel
connect issue_slots[10].out_uop.op1_sel, slots_10.io.out_uop.op1_sel
connect issue_slots[10].out_uop.imm_packed, slots_10.io.out_uop.imm_packed
connect issue_slots[10].out_uop.pimm, slots_10.io.out_uop.pimm
connect issue_slots[10].out_uop.imm_sel, slots_10.io.out_uop.imm_sel
connect issue_slots[10].out_uop.imm_rename, slots_10.io.out_uop.imm_rename
connect issue_slots[10].out_uop.taken, slots_10.io.out_uop.taken
connect issue_slots[10].out_uop.pc_lob, slots_10.io.out_uop.pc_lob
connect issue_slots[10].out_uop.edge_inst, slots_10.io.out_uop.edge_inst
connect issue_slots[10].out_uop.ftq_idx, slots_10.io.out_uop.ftq_idx
connect issue_slots[10].out_uop.is_mov, slots_10.io.out_uop.is_mov
connect issue_slots[10].out_uop.is_rocc, slots_10.io.out_uop.is_rocc
connect issue_slots[10].out_uop.is_sys_pc2epc, slots_10.io.out_uop.is_sys_pc2epc
connect issue_slots[10].out_uop.is_eret, slots_10.io.out_uop.is_eret
connect issue_slots[10].out_uop.is_amo, slots_10.io.out_uop.is_amo
connect issue_slots[10].out_uop.is_sfence, slots_10.io.out_uop.is_sfence
connect issue_slots[10].out_uop.is_fencei, slots_10.io.out_uop.is_fencei
connect issue_slots[10].out_uop.is_fence, slots_10.io.out_uop.is_fence
connect issue_slots[10].out_uop.is_sfb, slots_10.io.out_uop.is_sfb
connect issue_slots[10].out_uop.br_type, slots_10.io.out_uop.br_type
connect issue_slots[10].out_uop.br_tag, slots_10.io.out_uop.br_tag
connect issue_slots[10].out_uop.br_mask, slots_10.io.out_uop.br_mask
connect issue_slots[10].out_uop.dis_col_sel, slots_10.io.out_uop.dis_col_sel
connect issue_slots[10].out_uop.iw_p3_bypass_hint, slots_10.io.out_uop.iw_p3_bypass_hint
connect issue_slots[10].out_uop.iw_p2_bypass_hint, slots_10.io.out_uop.iw_p2_bypass_hint
connect issue_slots[10].out_uop.iw_p1_bypass_hint, slots_10.io.out_uop.iw_p1_bypass_hint
connect issue_slots[10].out_uop.iw_p2_speculative_child, slots_10.io.out_uop.iw_p2_speculative_child
connect issue_slots[10].out_uop.iw_p1_speculative_child, slots_10.io.out_uop.iw_p1_speculative_child
connect issue_slots[10].out_uop.iw_issued_partial_dgen, slots_10.io.out_uop.iw_issued_partial_dgen
connect issue_slots[10].out_uop.iw_issued_partial_agen, slots_10.io.out_uop.iw_issued_partial_agen
connect issue_slots[10].out_uop.iw_issued, slots_10.io.out_uop.iw_issued
connect issue_slots[10].out_uop.fu_code[0], slots_10.io.out_uop.fu_code[0]
connect issue_slots[10].out_uop.fu_code[1], slots_10.io.out_uop.fu_code[1]
connect issue_slots[10].out_uop.fu_code[2], slots_10.io.out_uop.fu_code[2]
connect issue_slots[10].out_uop.fu_code[3], slots_10.io.out_uop.fu_code[3]
connect issue_slots[10].out_uop.fu_code[4], slots_10.io.out_uop.fu_code[4]
connect issue_slots[10].out_uop.fu_code[5], slots_10.io.out_uop.fu_code[5]
connect issue_slots[10].out_uop.fu_code[6], slots_10.io.out_uop.fu_code[6]
connect issue_slots[10].out_uop.fu_code[7], slots_10.io.out_uop.fu_code[7]
connect issue_slots[10].out_uop.fu_code[8], slots_10.io.out_uop.fu_code[8]
connect issue_slots[10].out_uop.fu_code[9], slots_10.io.out_uop.fu_code[9]
connect issue_slots[10].out_uop.iq_type[0], slots_10.io.out_uop.iq_type[0]
connect issue_slots[10].out_uop.iq_type[1], slots_10.io.out_uop.iq_type[1]
connect issue_slots[10].out_uop.iq_type[2], slots_10.io.out_uop.iq_type[2]
connect issue_slots[10].out_uop.iq_type[3], slots_10.io.out_uop.iq_type[3]
connect issue_slots[10].out_uop.debug_pc, slots_10.io.out_uop.debug_pc
connect issue_slots[10].out_uop.is_rvc, slots_10.io.out_uop.is_rvc
connect issue_slots[10].out_uop.debug_inst, slots_10.io.out_uop.debug_inst
connect issue_slots[10].out_uop.inst, slots_10.io.out_uop.inst
connect slots_10.io.in_uop.bits.debug_tsrc, issue_slots[10].in_uop.bits.debug_tsrc
connect slots_10.io.in_uop.bits.debug_fsrc, issue_slots[10].in_uop.bits.debug_fsrc
connect slots_10.io.in_uop.bits.bp_xcpt_if, issue_slots[10].in_uop.bits.bp_xcpt_if
connect slots_10.io.in_uop.bits.bp_debug_if, issue_slots[10].in_uop.bits.bp_debug_if
connect slots_10.io.in_uop.bits.xcpt_ma_if, issue_slots[10].in_uop.bits.xcpt_ma_if
connect slots_10.io.in_uop.bits.xcpt_ae_if, issue_slots[10].in_uop.bits.xcpt_ae_if
connect slots_10.io.in_uop.bits.xcpt_pf_if, issue_slots[10].in_uop.bits.xcpt_pf_if
connect slots_10.io.in_uop.bits.fp_typ, issue_slots[10].in_uop.bits.fp_typ
connect slots_10.io.in_uop.bits.fp_rm, issue_slots[10].in_uop.bits.fp_rm
connect slots_10.io.in_uop.bits.fp_val, issue_slots[10].in_uop.bits.fp_val
connect slots_10.io.in_uop.bits.fcn_op, issue_slots[10].in_uop.bits.fcn_op
connect slots_10.io.in_uop.bits.fcn_dw, issue_slots[10].in_uop.bits.fcn_dw
connect slots_10.io.in_uop.bits.frs3_en, issue_slots[10].in_uop.bits.frs3_en
connect slots_10.io.in_uop.bits.lrs2_rtype, issue_slots[10].in_uop.bits.lrs2_rtype
connect slots_10.io.in_uop.bits.lrs1_rtype, issue_slots[10].in_uop.bits.lrs1_rtype
connect slots_10.io.in_uop.bits.dst_rtype, issue_slots[10].in_uop.bits.dst_rtype
connect slots_10.io.in_uop.bits.lrs3, issue_slots[10].in_uop.bits.lrs3
connect slots_10.io.in_uop.bits.lrs2, issue_slots[10].in_uop.bits.lrs2
connect slots_10.io.in_uop.bits.lrs1, issue_slots[10].in_uop.bits.lrs1
connect slots_10.io.in_uop.bits.ldst, issue_slots[10].in_uop.bits.ldst
connect slots_10.io.in_uop.bits.ldst_is_rs1, issue_slots[10].in_uop.bits.ldst_is_rs1
connect slots_10.io.in_uop.bits.csr_cmd, issue_slots[10].in_uop.bits.csr_cmd
connect slots_10.io.in_uop.bits.flush_on_commit, issue_slots[10].in_uop.bits.flush_on_commit
connect slots_10.io.in_uop.bits.is_unique, issue_slots[10].in_uop.bits.is_unique
connect slots_10.io.in_uop.bits.uses_stq, issue_slots[10].in_uop.bits.uses_stq
connect slots_10.io.in_uop.bits.uses_ldq, issue_slots[10].in_uop.bits.uses_ldq
connect slots_10.io.in_uop.bits.mem_signed, issue_slots[10].in_uop.bits.mem_signed
connect slots_10.io.in_uop.bits.mem_size, issue_slots[10].in_uop.bits.mem_size
connect slots_10.io.in_uop.bits.mem_cmd, issue_slots[10].in_uop.bits.mem_cmd
connect slots_10.io.in_uop.bits.exc_cause, issue_slots[10].in_uop.bits.exc_cause
connect slots_10.io.in_uop.bits.exception, issue_slots[10].in_uop.bits.exception
connect slots_10.io.in_uop.bits.stale_pdst, issue_slots[10].in_uop.bits.stale_pdst
connect slots_10.io.in_uop.bits.ppred_busy, issue_slots[10].in_uop.bits.ppred_busy
connect slots_10.io.in_uop.bits.prs3_busy, issue_slots[10].in_uop.bits.prs3_busy
connect slots_10.io.in_uop.bits.prs2_busy, issue_slots[10].in_uop.bits.prs2_busy
connect slots_10.io.in_uop.bits.prs1_busy, issue_slots[10].in_uop.bits.prs1_busy
connect slots_10.io.in_uop.bits.ppred, issue_slots[10].in_uop.bits.ppred
connect slots_10.io.in_uop.bits.prs3, issue_slots[10].in_uop.bits.prs3
connect slots_10.io.in_uop.bits.prs2, issue_slots[10].in_uop.bits.prs2
connect slots_10.io.in_uop.bits.prs1, issue_slots[10].in_uop.bits.prs1
connect slots_10.io.in_uop.bits.pdst, issue_slots[10].in_uop.bits.pdst
connect slots_10.io.in_uop.bits.rxq_idx, issue_slots[10].in_uop.bits.rxq_idx
connect slots_10.io.in_uop.bits.stq_idx, issue_slots[10].in_uop.bits.stq_idx
connect slots_10.io.in_uop.bits.ldq_idx, issue_slots[10].in_uop.bits.ldq_idx
connect slots_10.io.in_uop.bits.rob_idx, issue_slots[10].in_uop.bits.rob_idx
connect slots_10.io.in_uop.bits.fp_ctrl.vec, issue_slots[10].in_uop.bits.fp_ctrl.vec
connect slots_10.io.in_uop.bits.fp_ctrl.wflags, issue_slots[10].in_uop.bits.fp_ctrl.wflags
connect slots_10.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[10].in_uop.bits.fp_ctrl.sqrt
connect slots_10.io.in_uop.bits.fp_ctrl.div, issue_slots[10].in_uop.bits.fp_ctrl.div
connect slots_10.io.in_uop.bits.fp_ctrl.fma, issue_slots[10].in_uop.bits.fp_ctrl.fma
connect slots_10.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[10].in_uop.bits.fp_ctrl.fastpipe
connect slots_10.io.in_uop.bits.fp_ctrl.toint, issue_slots[10].in_uop.bits.fp_ctrl.toint
connect slots_10.io.in_uop.bits.fp_ctrl.fromint, issue_slots[10].in_uop.bits.fp_ctrl.fromint
connect slots_10.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[10].in_uop.bits.fp_ctrl.typeTagOut
connect slots_10.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[10].in_uop.bits.fp_ctrl.typeTagIn
connect slots_10.io.in_uop.bits.fp_ctrl.swap23, issue_slots[10].in_uop.bits.fp_ctrl.swap23
connect slots_10.io.in_uop.bits.fp_ctrl.swap12, issue_slots[10].in_uop.bits.fp_ctrl.swap12
connect slots_10.io.in_uop.bits.fp_ctrl.ren3, issue_slots[10].in_uop.bits.fp_ctrl.ren3
connect slots_10.io.in_uop.bits.fp_ctrl.ren2, issue_slots[10].in_uop.bits.fp_ctrl.ren2
connect slots_10.io.in_uop.bits.fp_ctrl.ren1, issue_slots[10].in_uop.bits.fp_ctrl.ren1
connect slots_10.io.in_uop.bits.fp_ctrl.wen, issue_slots[10].in_uop.bits.fp_ctrl.wen
connect slots_10.io.in_uop.bits.fp_ctrl.ldst, issue_slots[10].in_uop.bits.fp_ctrl.ldst
connect slots_10.io.in_uop.bits.op2_sel, issue_slots[10].in_uop.bits.op2_sel
connect slots_10.io.in_uop.bits.op1_sel, issue_slots[10].in_uop.bits.op1_sel
connect slots_10.io.in_uop.bits.imm_packed, issue_slots[10].in_uop.bits.imm_packed
connect slots_10.io.in_uop.bits.pimm, issue_slots[10].in_uop.bits.pimm
connect slots_10.io.in_uop.bits.imm_sel, issue_slots[10].in_uop.bits.imm_sel
connect slots_10.io.in_uop.bits.imm_rename, issue_slots[10].in_uop.bits.imm_rename
connect slots_10.io.in_uop.bits.taken, issue_slots[10].in_uop.bits.taken
connect slots_10.io.in_uop.bits.pc_lob, issue_slots[10].in_uop.bits.pc_lob
connect slots_10.io.in_uop.bits.edge_inst, issue_slots[10].in_uop.bits.edge_inst
connect slots_10.io.in_uop.bits.ftq_idx, issue_slots[10].in_uop.bits.ftq_idx
connect slots_10.io.in_uop.bits.is_mov, issue_slots[10].in_uop.bits.is_mov
connect slots_10.io.in_uop.bits.is_rocc, issue_slots[10].in_uop.bits.is_rocc
connect slots_10.io.in_uop.bits.is_sys_pc2epc, issue_slots[10].in_uop.bits.is_sys_pc2epc
connect slots_10.io.in_uop.bits.is_eret, issue_slots[10].in_uop.bits.is_eret
connect slots_10.io.in_uop.bits.is_amo, issue_slots[10].in_uop.bits.is_amo
connect slots_10.io.in_uop.bits.is_sfence, issue_slots[10].in_uop.bits.is_sfence
connect slots_10.io.in_uop.bits.is_fencei, issue_slots[10].in_uop.bits.is_fencei
connect slots_10.io.in_uop.bits.is_fence, issue_slots[10].in_uop.bits.is_fence
connect slots_10.io.in_uop.bits.is_sfb, issue_slots[10].in_uop.bits.is_sfb
connect slots_10.io.in_uop.bits.br_type, issue_slots[10].in_uop.bits.br_type
connect slots_10.io.in_uop.bits.br_tag, issue_slots[10].in_uop.bits.br_tag
connect slots_10.io.in_uop.bits.br_mask, issue_slots[10].in_uop.bits.br_mask
connect slots_10.io.in_uop.bits.dis_col_sel, issue_slots[10].in_uop.bits.dis_col_sel
connect slots_10.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[10].in_uop.bits.iw_p3_bypass_hint
connect slots_10.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[10].in_uop.bits.iw_p2_bypass_hint
connect slots_10.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[10].in_uop.bits.iw_p1_bypass_hint
connect slots_10.io.in_uop.bits.iw_p2_speculative_child, issue_slots[10].in_uop.bits.iw_p2_speculative_child
connect slots_10.io.in_uop.bits.iw_p1_speculative_child, issue_slots[10].in_uop.bits.iw_p1_speculative_child
connect slots_10.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[10].in_uop.bits.iw_issued_partial_dgen
connect slots_10.io.in_uop.bits.iw_issued_partial_agen, issue_slots[10].in_uop.bits.iw_issued_partial_agen
connect slots_10.io.in_uop.bits.iw_issued, issue_slots[10].in_uop.bits.iw_issued
connect slots_10.io.in_uop.bits.fu_code[0], issue_slots[10].in_uop.bits.fu_code[0]
connect slots_10.io.in_uop.bits.fu_code[1], issue_slots[10].in_uop.bits.fu_code[1]
connect slots_10.io.in_uop.bits.fu_code[2], issue_slots[10].in_uop.bits.fu_code[2]
connect slots_10.io.in_uop.bits.fu_code[3], issue_slots[10].in_uop.bits.fu_code[3]
connect slots_10.io.in_uop.bits.fu_code[4], issue_slots[10].in_uop.bits.fu_code[4]
connect slots_10.io.in_uop.bits.fu_code[5], issue_slots[10].in_uop.bits.fu_code[5]
connect slots_10.io.in_uop.bits.fu_code[6], issue_slots[10].in_uop.bits.fu_code[6]
connect slots_10.io.in_uop.bits.fu_code[7], issue_slots[10].in_uop.bits.fu_code[7]
connect slots_10.io.in_uop.bits.fu_code[8], issue_slots[10].in_uop.bits.fu_code[8]
connect slots_10.io.in_uop.bits.fu_code[9], issue_slots[10].in_uop.bits.fu_code[9]
connect slots_10.io.in_uop.bits.iq_type[0], issue_slots[10].in_uop.bits.iq_type[0]
connect slots_10.io.in_uop.bits.iq_type[1], issue_slots[10].in_uop.bits.iq_type[1]
connect slots_10.io.in_uop.bits.iq_type[2], issue_slots[10].in_uop.bits.iq_type[2]
connect slots_10.io.in_uop.bits.iq_type[3], issue_slots[10].in_uop.bits.iq_type[3]
connect slots_10.io.in_uop.bits.debug_pc, issue_slots[10].in_uop.bits.debug_pc
connect slots_10.io.in_uop.bits.is_rvc, issue_slots[10].in_uop.bits.is_rvc
connect slots_10.io.in_uop.bits.debug_inst, issue_slots[10].in_uop.bits.debug_inst
connect slots_10.io.in_uop.bits.inst, issue_slots[10].in_uop.bits.inst
connect slots_10.io.in_uop.valid, issue_slots[10].in_uop.valid
connect issue_slots[10].iss_uop.debug_tsrc, slots_10.io.iss_uop.debug_tsrc
connect issue_slots[10].iss_uop.debug_fsrc, slots_10.io.iss_uop.debug_fsrc
connect issue_slots[10].iss_uop.bp_xcpt_if, slots_10.io.iss_uop.bp_xcpt_if
connect issue_slots[10].iss_uop.bp_debug_if, slots_10.io.iss_uop.bp_debug_if
connect issue_slots[10].iss_uop.xcpt_ma_if, slots_10.io.iss_uop.xcpt_ma_if
connect issue_slots[10].iss_uop.xcpt_ae_if, slots_10.io.iss_uop.xcpt_ae_if
connect issue_slots[10].iss_uop.xcpt_pf_if, slots_10.io.iss_uop.xcpt_pf_if
connect issue_slots[10].iss_uop.fp_typ, slots_10.io.iss_uop.fp_typ
connect issue_slots[10].iss_uop.fp_rm, slots_10.io.iss_uop.fp_rm
connect issue_slots[10].iss_uop.fp_val, slots_10.io.iss_uop.fp_val
connect issue_slots[10].iss_uop.fcn_op, slots_10.io.iss_uop.fcn_op
connect issue_slots[10].iss_uop.fcn_dw, slots_10.io.iss_uop.fcn_dw
connect issue_slots[10].iss_uop.frs3_en, slots_10.io.iss_uop.frs3_en
connect issue_slots[10].iss_uop.lrs2_rtype, slots_10.io.iss_uop.lrs2_rtype
connect issue_slots[10].iss_uop.lrs1_rtype, slots_10.io.iss_uop.lrs1_rtype
connect issue_slots[10].iss_uop.dst_rtype, slots_10.io.iss_uop.dst_rtype
connect issue_slots[10].iss_uop.lrs3, slots_10.io.iss_uop.lrs3
connect issue_slots[10].iss_uop.lrs2, slots_10.io.iss_uop.lrs2
connect issue_slots[10].iss_uop.lrs1, slots_10.io.iss_uop.lrs1
connect issue_slots[10].iss_uop.ldst, slots_10.io.iss_uop.ldst
connect issue_slots[10].iss_uop.ldst_is_rs1, slots_10.io.iss_uop.ldst_is_rs1
connect issue_slots[10].iss_uop.csr_cmd, slots_10.io.iss_uop.csr_cmd
connect issue_slots[10].iss_uop.flush_on_commit, slots_10.io.iss_uop.flush_on_commit
connect issue_slots[10].iss_uop.is_unique, slots_10.io.iss_uop.is_unique
connect issue_slots[10].iss_uop.uses_stq, slots_10.io.iss_uop.uses_stq
connect issue_slots[10].iss_uop.uses_ldq, slots_10.io.iss_uop.uses_ldq
connect issue_slots[10].iss_uop.mem_signed, slots_10.io.iss_uop.mem_signed
connect issue_slots[10].iss_uop.mem_size, slots_10.io.iss_uop.mem_size
connect issue_slots[10].iss_uop.mem_cmd, slots_10.io.iss_uop.mem_cmd
connect issue_slots[10].iss_uop.exc_cause, slots_10.io.iss_uop.exc_cause
connect issue_slots[10].iss_uop.exception, slots_10.io.iss_uop.exception
connect issue_slots[10].iss_uop.stale_pdst, slots_10.io.iss_uop.stale_pdst
connect issue_slots[10].iss_uop.ppred_busy, slots_10.io.iss_uop.ppred_busy
connect issue_slots[10].iss_uop.prs3_busy, slots_10.io.iss_uop.prs3_busy
connect issue_slots[10].iss_uop.prs2_busy, slots_10.io.iss_uop.prs2_busy
connect issue_slots[10].iss_uop.prs1_busy, slots_10.io.iss_uop.prs1_busy
connect issue_slots[10].iss_uop.ppred, slots_10.io.iss_uop.ppred
connect issue_slots[10].iss_uop.prs3, slots_10.io.iss_uop.prs3
connect issue_slots[10].iss_uop.prs2, slots_10.io.iss_uop.prs2
connect issue_slots[10].iss_uop.prs1, slots_10.io.iss_uop.prs1
connect issue_slots[10].iss_uop.pdst, slots_10.io.iss_uop.pdst
connect issue_slots[10].iss_uop.rxq_idx, slots_10.io.iss_uop.rxq_idx
connect issue_slots[10].iss_uop.stq_idx, slots_10.io.iss_uop.stq_idx
connect issue_slots[10].iss_uop.ldq_idx, slots_10.io.iss_uop.ldq_idx
connect issue_slots[10].iss_uop.rob_idx, slots_10.io.iss_uop.rob_idx
connect issue_slots[10].iss_uop.fp_ctrl.vec, slots_10.io.iss_uop.fp_ctrl.vec
connect issue_slots[10].iss_uop.fp_ctrl.wflags, slots_10.io.iss_uop.fp_ctrl.wflags
connect issue_slots[10].iss_uop.fp_ctrl.sqrt, slots_10.io.iss_uop.fp_ctrl.sqrt
connect issue_slots[10].iss_uop.fp_ctrl.div, slots_10.io.iss_uop.fp_ctrl.div
connect issue_slots[10].iss_uop.fp_ctrl.fma, slots_10.io.iss_uop.fp_ctrl.fma
connect issue_slots[10].iss_uop.fp_ctrl.fastpipe, slots_10.io.iss_uop.fp_ctrl.fastpipe
connect issue_slots[10].iss_uop.fp_ctrl.toint, slots_10.io.iss_uop.fp_ctrl.toint
connect issue_slots[10].iss_uop.fp_ctrl.fromint, slots_10.io.iss_uop.fp_ctrl.fromint
connect issue_slots[10].iss_uop.fp_ctrl.typeTagOut, slots_10.io.iss_uop.fp_ctrl.typeTagOut
connect issue_slots[10].iss_uop.fp_ctrl.typeTagIn, slots_10.io.iss_uop.fp_ctrl.typeTagIn
connect issue_slots[10].iss_uop.fp_ctrl.swap23, slots_10.io.iss_uop.fp_ctrl.swap23
connect issue_slots[10].iss_uop.fp_ctrl.swap12, slots_10.io.iss_uop.fp_ctrl.swap12
connect issue_slots[10].iss_uop.fp_ctrl.ren3, slots_10.io.iss_uop.fp_ctrl.ren3
connect issue_slots[10].iss_uop.fp_ctrl.ren2, slots_10.io.iss_uop.fp_ctrl.ren2
connect issue_slots[10].iss_uop.fp_ctrl.ren1, slots_10.io.iss_uop.fp_ctrl.ren1
connect issue_slots[10].iss_uop.fp_ctrl.wen, slots_10.io.iss_uop.fp_ctrl.wen
connect issue_slots[10].iss_uop.fp_ctrl.ldst, slots_10.io.iss_uop.fp_ctrl.ldst
connect issue_slots[10].iss_uop.op2_sel, slots_10.io.iss_uop.op2_sel
connect issue_slots[10].iss_uop.op1_sel, slots_10.io.iss_uop.op1_sel
connect issue_slots[10].iss_uop.imm_packed, slots_10.io.iss_uop.imm_packed
connect issue_slots[10].iss_uop.pimm, slots_10.io.iss_uop.pimm
connect issue_slots[10].iss_uop.imm_sel, slots_10.io.iss_uop.imm_sel
connect issue_slots[10].iss_uop.imm_rename, slots_10.io.iss_uop.imm_rename
connect issue_slots[10].iss_uop.taken, slots_10.io.iss_uop.taken
connect issue_slots[10].iss_uop.pc_lob, slots_10.io.iss_uop.pc_lob
connect issue_slots[10].iss_uop.edge_inst, slots_10.io.iss_uop.edge_inst
connect issue_slots[10].iss_uop.ftq_idx, slots_10.io.iss_uop.ftq_idx
connect issue_slots[10].iss_uop.is_mov, slots_10.io.iss_uop.is_mov
connect issue_slots[10].iss_uop.is_rocc, slots_10.io.iss_uop.is_rocc
connect issue_slots[10].iss_uop.is_sys_pc2epc, slots_10.io.iss_uop.is_sys_pc2epc
connect issue_slots[10].iss_uop.is_eret, slots_10.io.iss_uop.is_eret
connect issue_slots[10].iss_uop.is_amo, slots_10.io.iss_uop.is_amo
connect issue_slots[10].iss_uop.is_sfence, slots_10.io.iss_uop.is_sfence
connect issue_slots[10].iss_uop.is_fencei, slots_10.io.iss_uop.is_fencei
connect issue_slots[10].iss_uop.is_fence, slots_10.io.iss_uop.is_fence
connect issue_slots[10].iss_uop.is_sfb, slots_10.io.iss_uop.is_sfb
connect issue_slots[10].iss_uop.br_type, slots_10.io.iss_uop.br_type
connect issue_slots[10].iss_uop.br_tag, slots_10.io.iss_uop.br_tag
connect issue_slots[10].iss_uop.br_mask, slots_10.io.iss_uop.br_mask
connect issue_slots[10].iss_uop.dis_col_sel, slots_10.io.iss_uop.dis_col_sel
connect issue_slots[10].iss_uop.iw_p3_bypass_hint, slots_10.io.iss_uop.iw_p3_bypass_hint
connect issue_slots[10].iss_uop.iw_p2_bypass_hint, slots_10.io.iss_uop.iw_p2_bypass_hint
connect issue_slots[10].iss_uop.iw_p1_bypass_hint, slots_10.io.iss_uop.iw_p1_bypass_hint
connect issue_slots[10].iss_uop.iw_p2_speculative_child, slots_10.io.iss_uop.iw_p2_speculative_child
connect issue_slots[10].iss_uop.iw_p1_speculative_child, slots_10.io.iss_uop.iw_p1_speculative_child
connect issue_slots[10].iss_uop.iw_issued_partial_dgen, slots_10.io.iss_uop.iw_issued_partial_dgen
connect issue_slots[10].iss_uop.iw_issued_partial_agen, slots_10.io.iss_uop.iw_issued_partial_agen
connect issue_slots[10].iss_uop.iw_issued, slots_10.io.iss_uop.iw_issued
connect issue_slots[10].iss_uop.fu_code[0], slots_10.io.iss_uop.fu_code[0]
connect issue_slots[10].iss_uop.fu_code[1], slots_10.io.iss_uop.fu_code[1]
connect issue_slots[10].iss_uop.fu_code[2], slots_10.io.iss_uop.fu_code[2]
connect issue_slots[10].iss_uop.fu_code[3], slots_10.io.iss_uop.fu_code[3]
connect issue_slots[10].iss_uop.fu_code[4], slots_10.io.iss_uop.fu_code[4]
connect issue_slots[10].iss_uop.fu_code[5], slots_10.io.iss_uop.fu_code[5]
connect issue_slots[10].iss_uop.fu_code[6], slots_10.io.iss_uop.fu_code[6]
connect issue_slots[10].iss_uop.fu_code[7], slots_10.io.iss_uop.fu_code[7]
connect issue_slots[10].iss_uop.fu_code[8], slots_10.io.iss_uop.fu_code[8]
connect issue_slots[10].iss_uop.fu_code[9], slots_10.io.iss_uop.fu_code[9]
connect issue_slots[10].iss_uop.iq_type[0], slots_10.io.iss_uop.iq_type[0]
connect issue_slots[10].iss_uop.iq_type[1], slots_10.io.iss_uop.iq_type[1]
connect issue_slots[10].iss_uop.iq_type[2], slots_10.io.iss_uop.iq_type[2]
connect issue_slots[10].iss_uop.iq_type[3], slots_10.io.iss_uop.iq_type[3]
connect issue_slots[10].iss_uop.debug_pc, slots_10.io.iss_uop.debug_pc
connect issue_slots[10].iss_uop.is_rvc, slots_10.io.iss_uop.is_rvc
connect issue_slots[10].iss_uop.debug_inst, slots_10.io.iss_uop.debug_inst
connect issue_slots[10].iss_uop.inst, slots_10.io.iss_uop.inst
connect slots_10.io.grant, issue_slots[10].grant
connect issue_slots[10].request, slots_10.io.request
connect issue_slots[10].will_be_valid, slots_10.io.will_be_valid
connect issue_slots[10].valid, slots_10.io.valid
connect slots_11.io.child_rebusys, issue_slots[11].child_rebusys
connect slots_11.io.pred_wakeup_port.bits, issue_slots[11].pred_wakeup_port.bits
connect slots_11.io.pred_wakeup_port.valid, issue_slots[11].pred_wakeup_port.valid
connect slots_11.io.wakeup_ports[0].bits.rebusy, issue_slots[11].wakeup_ports[0].bits.rebusy
connect slots_11.io.wakeup_ports[0].bits.speculative_mask, issue_slots[11].wakeup_ports[0].bits.speculative_mask
connect slots_11.io.wakeup_ports[0].bits.bypassable, issue_slots[11].wakeup_ports[0].bits.bypassable
connect slots_11.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[11].wakeup_ports[0].bits.uop.debug_tsrc
connect slots_11.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[11].wakeup_ports[0].bits.uop.debug_fsrc
connect slots_11.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[11].wakeup_ports[0].bits.uop.bp_xcpt_if
connect slots_11.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[11].wakeup_ports[0].bits.uop.bp_debug_if
connect slots_11.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[11].wakeup_ports[0].bits.uop.xcpt_ma_if
connect slots_11.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[11].wakeup_ports[0].bits.uop.xcpt_ae_if
connect slots_11.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[11].wakeup_ports[0].bits.uop.xcpt_pf_if
connect slots_11.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[11].wakeup_ports[0].bits.uop.fp_typ
connect slots_11.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[11].wakeup_ports[0].bits.uop.fp_rm
connect slots_11.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[11].wakeup_ports[0].bits.uop.fp_val
connect slots_11.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[11].wakeup_ports[0].bits.uop.fcn_op
connect slots_11.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[11].wakeup_ports[0].bits.uop.fcn_dw
connect slots_11.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[11].wakeup_ports[0].bits.uop.frs3_en
connect slots_11.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[11].wakeup_ports[0].bits.uop.lrs2_rtype
connect slots_11.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[11].wakeup_ports[0].bits.uop.lrs1_rtype
connect slots_11.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[11].wakeup_ports[0].bits.uop.dst_rtype
connect slots_11.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[11].wakeup_ports[0].bits.uop.lrs3
connect slots_11.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[11].wakeup_ports[0].bits.uop.lrs2
connect slots_11.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[11].wakeup_ports[0].bits.uop.lrs1
connect slots_11.io.wakeup_ports[0].bits.uop.ldst, issue_slots[11].wakeup_ports[0].bits.uop.ldst
connect slots_11.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[11].wakeup_ports[0].bits.uop.ldst_is_rs1
connect slots_11.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[11].wakeup_ports[0].bits.uop.csr_cmd
connect slots_11.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[11].wakeup_ports[0].bits.uop.flush_on_commit
connect slots_11.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[11].wakeup_ports[0].bits.uop.is_unique
connect slots_11.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[11].wakeup_ports[0].bits.uop.uses_stq
connect slots_11.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[11].wakeup_ports[0].bits.uop.uses_ldq
connect slots_11.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[11].wakeup_ports[0].bits.uop.mem_signed
connect slots_11.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[11].wakeup_ports[0].bits.uop.mem_size
connect slots_11.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[11].wakeup_ports[0].bits.uop.mem_cmd
connect slots_11.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[11].wakeup_ports[0].bits.uop.exc_cause
connect slots_11.io.wakeup_ports[0].bits.uop.exception, issue_slots[11].wakeup_ports[0].bits.uop.exception
connect slots_11.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[11].wakeup_ports[0].bits.uop.stale_pdst
connect slots_11.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[11].wakeup_ports[0].bits.uop.ppred_busy
connect slots_11.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[11].wakeup_ports[0].bits.uop.prs3_busy
connect slots_11.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[11].wakeup_ports[0].bits.uop.prs2_busy
connect slots_11.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[11].wakeup_ports[0].bits.uop.prs1_busy
connect slots_11.io.wakeup_ports[0].bits.uop.ppred, issue_slots[11].wakeup_ports[0].bits.uop.ppred
connect slots_11.io.wakeup_ports[0].bits.uop.prs3, issue_slots[11].wakeup_ports[0].bits.uop.prs3
connect slots_11.io.wakeup_ports[0].bits.uop.prs2, issue_slots[11].wakeup_ports[0].bits.uop.prs2
connect slots_11.io.wakeup_ports[0].bits.uop.prs1, issue_slots[11].wakeup_ports[0].bits.uop.prs1
connect slots_11.io.wakeup_ports[0].bits.uop.pdst, issue_slots[11].wakeup_ports[0].bits.uop.pdst
connect slots_11.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[11].wakeup_ports[0].bits.uop.rxq_idx
connect slots_11.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[11].wakeup_ports[0].bits.uop.stq_idx
connect slots_11.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[11].wakeup_ports[0].bits.uop.ldq_idx
connect slots_11.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[11].wakeup_ports[0].bits.uop.rob_idx
connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.vec
connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.wflags
connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.sqrt
connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.div
connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.fma
connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe
connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.toint
connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.fromint
connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut
connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn
connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.swap23
connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.swap12
connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.ren3
connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.ren2
connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.ren1
connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.wen
connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.ldst
connect slots_11.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[11].wakeup_ports[0].bits.uop.op2_sel
connect slots_11.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[11].wakeup_ports[0].bits.uop.op1_sel
connect slots_11.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[11].wakeup_ports[0].bits.uop.imm_packed
connect slots_11.io.wakeup_ports[0].bits.uop.pimm, issue_slots[11].wakeup_ports[0].bits.uop.pimm
connect slots_11.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[11].wakeup_ports[0].bits.uop.imm_sel
connect slots_11.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[11].wakeup_ports[0].bits.uop.imm_rename
connect slots_11.io.wakeup_ports[0].bits.uop.taken, issue_slots[11].wakeup_ports[0].bits.uop.taken
connect slots_11.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[11].wakeup_ports[0].bits.uop.pc_lob
connect slots_11.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[11].wakeup_ports[0].bits.uop.edge_inst
connect slots_11.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[11].wakeup_ports[0].bits.uop.ftq_idx
connect slots_11.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[11].wakeup_ports[0].bits.uop.is_mov
connect slots_11.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[11].wakeup_ports[0].bits.uop.is_rocc
connect slots_11.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[11].wakeup_ports[0].bits.uop.is_sys_pc2epc
connect slots_11.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[11].wakeup_ports[0].bits.uop.is_eret
connect slots_11.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[11].wakeup_ports[0].bits.uop.is_amo
connect slots_11.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[11].wakeup_ports[0].bits.uop.is_sfence
connect slots_11.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[11].wakeup_ports[0].bits.uop.is_fencei
connect slots_11.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[11].wakeup_ports[0].bits.uop.is_fence
connect slots_11.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[11].wakeup_ports[0].bits.uop.is_sfb
connect slots_11.io.wakeup_ports[0].bits.uop.br_type, issue_slots[11].wakeup_ports[0].bits.uop.br_type
connect slots_11.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[11].wakeup_ports[0].bits.uop.br_tag
connect slots_11.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[11].wakeup_ports[0].bits.uop.br_mask
connect slots_11.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[11].wakeup_ports[0].bits.uop.dis_col_sel
connect slots_11.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[11].wakeup_ports[0].bits.uop.iw_p3_bypass_hint
connect slots_11.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[11].wakeup_ports[0].bits.uop.iw_p2_bypass_hint
connect slots_11.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[11].wakeup_ports[0].bits.uop.iw_p1_bypass_hint
connect slots_11.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[11].wakeup_ports[0].bits.uop.iw_p2_speculative_child
connect slots_11.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[11].wakeup_ports[0].bits.uop.iw_p1_speculative_child
connect slots_11.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[11].wakeup_ports[0].bits.uop.iw_issued_partial_dgen
connect slots_11.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[11].wakeup_ports[0].bits.uop.iw_issued_partial_agen
connect slots_11.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[11].wakeup_ports[0].bits.uop.iw_issued
connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[0]
connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[1]
connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[2]
connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[3]
connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[4]
connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[5]
connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[6]
connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[7]
connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[8]
connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[9]
connect slots_11.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[11].wakeup_ports[0].bits.uop.iq_type[0]
connect slots_11.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[11].wakeup_ports[0].bits.uop.iq_type[1]
connect slots_11.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[11].wakeup_ports[0].bits.uop.iq_type[2]
connect slots_11.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[11].wakeup_ports[0].bits.uop.iq_type[3]
connect slots_11.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[11].wakeup_ports[0].bits.uop.debug_pc
connect slots_11.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[11].wakeup_ports[0].bits.uop.is_rvc
connect slots_11.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[11].wakeup_ports[0].bits.uop.debug_inst
connect slots_11.io.wakeup_ports[0].bits.uop.inst, issue_slots[11].wakeup_ports[0].bits.uop.inst
connect slots_11.io.wakeup_ports[0].valid, issue_slots[11].wakeup_ports[0].valid
connect slots_11.io.wakeup_ports[1].bits.rebusy, issue_slots[11].wakeup_ports[1].bits.rebusy
connect slots_11.io.wakeup_ports[1].bits.speculative_mask, issue_slots[11].wakeup_ports[1].bits.speculative_mask
connect slots_11.io.wakeup_ports[1].bits.bypassable, issue_slots[11].wakeup_ports[1].bits.bypassable
connect slots_11.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[11].wakeup_ports[1].bits.uop.debug_tsrc
connect slots_11.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[11].wakeup_ports[1].bits.uop.debug_fsrc
connect slots_11.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[11].wakeup_ports[1].bits.uop.bp_xcpt_if
connect slots_11.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[11].wakeup_ports[1].bits.uop.bp_debug_if
connect slots_11.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[11].wakeup_ports[1].bits.uop.xcpt_ma_if
connect slots_11.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[11].wakeup_ports[1].bits.uop.xcpt_ae_if
connect slots_11.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[11].wakeup_ports[1].bits.uop.xcpt_pf_if
connect slots_11.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[11].wakeup_ports[1].bits.uop.fp_typ
connect slots_11.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[11].wakeup_ports[1].bits.uop.fp_rm
connect slots_11.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[11].wakeup_ports[1].bits.uop.fp_val
connect slots_11.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[11].wakeup_ports[1].bits.uop.fcn_op
connect slots_11.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[11].wakeup_ports[1].bits.uop.fcn_dw
connect slots_11.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[11].wakeup_ports[1].bits.uop.frs3_en
connect slots_11.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[11].wakeup_ports[1].bits.uop.lrs2_rtype
connect slots_11.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[11].wakeup_ports[1].bits.uop.lrs1_rtype
connect slots_11.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[11].wakeup_ports[1].bits.uop.dst_rtype
connect slots_11.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[11].wakeup_ports[1].bits.uop.lrs3
connect slots_11.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[11].wakeup_ports[1].bits.uop.lrs2
connect slots_11.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[11].wakeup_ports[1].bits.uop.lrs1
connect slots_11.io.wakeup_ports[1].bits.uop.ldst, issue_slots[11].wakeup_ports[1].bits.uop.ldst
connect slots_11.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[11].wakeup_ports[1].bits.uop.ldst_is_rs1
connect slots_11.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[11].wakeup_ports[1].bits.uop.csr_cmd
connect slots_11.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[11].wakeup_ports[1].bits.uop.flush_on_commit
connect slots_11.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[11].wakeup_ports[1].bits.uop.is_unique
connect slots_11.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[11].wakeup_ports[1].bits.uop.uses_stq
connect slots_11.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[11].wakeup_ports[1].bits.uop.uses_ldq
connect slots_11.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[11].wakeup_ports[1].bits.uop.mem_signed
connect slots_11.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[11].wakeup_ports[1].bits.uop.mem_size
connect slots_11.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[11].wakeup_ports[1].bits.uop.mem_cmd
connect slots_11.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[11].wakeup_ports[1].bits.uop.exc_cause
connect slots_11.io.wakeup_ports[1].bits.uop.exception, issue_slots[11].wakeup_ports[1].bits.uop.exception
connect slots_11.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[11].wakeup_ports[1].bits.uop.stale_pdst
connect slots_11.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[11].wakeup_ports[1].bits.uop.ppred_busy
connect slots_11.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[11].wakeup_ports[1].bits.uop.prs3_busy
connect slots_11.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[11].wakeup_ports[1].bits.uop.prs2_busy
connect slots_11.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[11].wakeup_ports[1].bits.uop.prs1_busy
connect slots_11.io.wakeup_ports[1].bits.uop.ppred, issue_slots[11].wakeup_ports[1].bits.uop.ppred
connect slots_11.io.wakeup_ports[1].bits.uop.prs3, issue_slots[11].wakeup_ports[1].bits.uop.prs3
connect slots_11.io.wakeup_ports[1].bits.uop.prs2, issue_slots[11].wakeup_ports[1].bits.uop.prs2
connect slots_11.io.wakeup_ports[1].bits.uop.prs1, issue_slots[11].wakeup_ports[1].bits.uop.prs1
connect slots_11.io.wakeup_ports[1].bits.uop.pdst, issue_slots[11].wakeup_ports[1].bits.uop.pdst
connect slots_11.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[11].wakeup_ports[1].bits.uop.rxq_idx
connect slots_11.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[11].wakeup_ports[1].bits.uop.stq_idx
connect slots_11.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[11].wakeup_ports[1].bits.uop.ldq_idx
connect slots_11.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[11].wakeup_ports[1].bits.uop.rob_idx
connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.vec
connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.wflags
connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.sqrt
connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.div
connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.fma
connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe
connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.toint
connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.fromint
connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut
connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn
connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.swap23
connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.swap12
connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.ren3
connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.ren2
connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.ren1
connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.wen
connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.ldst
connect slots_11.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[11].wakeup_ports[1].bits.uop.op2_sel
connect slots_11.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[11].wakeup_ports[1].bits.uop.op1_sel
connect slots_11.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[11].wakeup_ports[1].bits.uop.imm_packed
connect slots_11.io.wakeup_ports[1].bits.uop.pimm, issue_slots[11].wakeup_ports[1].bits.uop.pimm
connect slots_11.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[11].wakeup_ports[1].bits.uop.imm_sel
connect slots_11.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[11].wakeup_ports[1].bits.uop.imm_rename
connect slots_11.io.wakeup_ports[1].bits.uop.taken, issue_slots[11].wakeup_ports[1].bits.uop.taken
connect slots_11.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[11].wakeup_ports[1].bits.uop.pc_lob
connect slots_11.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[11].wakeup_ports[1].bits.uop.edge_inst
connect slots_11.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[11].wakeup_ports[1].bits.uop.ftq_idx
connect slots_11.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[11].wakeup_ports[1].bits.uop.is_mov
connect slots_11.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[11].wakeup_ports[1].bits.uop.is_rocc
connect slots_11.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[11].wakeup_ports[1].bits.uop.is_sys_pc2epc
connect slots_11.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[11].wakeup_ports[1].bits.uop.is_eret
connect slots_11.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[11].wakeup_ports[1].bits.uop.is_amo
connect slots_11.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[11].wakeup_ports[1].bits.uop.is_sfence
connect slots_11.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[11].wakeup_ports[1].bits.uop.is_fencei
connect slots_11.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[11].wakeup_ports[1].bits.uop.is_fence
connect slots_11.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[11].wakeup_ports[1].bits.uop.is_sfb
connect slots_11.io.wakeup_ports[1].bits.uop.br_type, issue_slots[11].wakeup_ports[1].bits.uop.br_type
connect slots_11.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[11].wakeup_ports[1].bits.uop.br_tag
connect slots_11.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[11].wakeup_ports[1].bits.uop.br_mask
connect slots_11.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[11].wakeup_ports[1].bits.uop.dis_col_sel
connect slots_11.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[11].wakeup_ports[1].bits.uop.iw_p3_bypass_hint
connect slots_11.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[11].wakeup_ports[1].bits.uop.iw_p2_bypass_hint
connect slots_11.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[11].wakeup_ports[1].bits.uop.iw_p1_bypass_hint
connect slots_11.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[11].wakeup_ports[1].bits.uop.iw_p2_speculative_child
connect slots_11.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[11].wakeup_ports[1].bits.uop.iw_p1_speculative_child
connect slots_11.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[11].wakeup_ports[1].bits.uop.iw_issued_partial_dgen
connect slots_11.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[11].wakeup_ports[1].bits.uop.iw_issued_partial_agen
connect slots_11.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[11].wakeup_ports[1].bits.uop.iw_issued
connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[0]
connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[1]
connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[2]
connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[3]
connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[4]
connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[5]
connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[6]
connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[7]
connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[8]
connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[9]
connect slots_11.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[11].wakeup_ports[1].bits.uop.iq_type[0]
connect slots_11.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[11].wakeup_ports[1].bits.uop.iq_type[1]
connect slots_11.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[11].wakeup_ports[1].bits.uop.iq_type[2]
connect slots_11.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[11].wakeup_ports[1].bits.uop.iq_type[3]
connect slots_11.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[11].wakeup_ports[1].bits.uop.debug_pc
connect slots_11.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[11].wakeup_ports[1].bits.uop.is_rvc
connect slots_11.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[11].wakeup_ports[1].bits.uop.debug_inst
connect slots_11.io.wakeup_ports[1].bits.uop.inst, issue_slots[11].wakeup_ports[1].bits.uop.inst
connect slots_11.io.wakeup_ports[1].valid, issue_slots[11].wakeup_ports[1].valid
connect slots_11.io.wakeup_ports[2].bits.rebusy, issue_slots[11].wakeup_ports[2].bits.rebusy
connect slots_11.io.wakeup_ports[2].bits.speculative_mask, issue_slots[11].wakeup_ports[2].bits.speculative_mask
connect slots_11.io.wakeup_ports[2].bits.bypassable, issue_slots[11].wakeup_ports[2].bits.bypassable
connect slots_11.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[11].wakeup_ports[2].bits.uop.debug_tsrc
connect slots_11.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[11].wakeup_ports[2].bits.uop.debug_fsrc
connect slots_11.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[11].wakeup_ports[2].bits.uop.bp_xcpt_if
connect slots_11.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[11].wakeup_ports[2].bits.uop.bp_debug_if
connect slots_11.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[11].wakeup_ports[2].bits.uop.xcpt_ma_if
connect slots_11.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[11].wakeup_ports[2].bits.uop.xcpt_ae_if
connect slots_11.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[11].wakeup_ports[2].bits.uop.xcpt_pf_if
connect slots_11.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[11].wakeup_ports[2].bits.uop.fp_typ
connect slots_11.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[11].wakeup_ports[2].bits.uop.fp_rm
connect slots_11.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[11].wakeup_ports[2].bits.uop.fp_val
connect slots_11.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[11].wakeup_ports[2].bits.uop.fcn_op
connect slots_11.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[11].wakeup_ports[2].bits.uop.fcn_dw
connect slots_11.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[11].wakeup_ports[2].bits.uop.frs3_en
connect slots_11.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[11].wakeup_ports[2].bits.uop.lrs2_rtype
connect slots_11.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[11].wakeup_ports[2].bits.uop.lrs1_rtype
connect slots_11.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[11].wakeup_ports[2].bits.uop.dst_rtype
connect slots_11.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[11].wakeup_ports[2].bits.uop.lrs3
connect slots_11.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[11].wakeup_ports[2].bits.uop.lrs2
connect slots_11.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[11].wakeup_ports[2].bits.uop.lrs1
connect slots_11.io.wakeup_ports[2].bits.uop.ldst, issue_slots[11].wakeup_ports[2].bits.uop.ldst
connect slots_11.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[11].wakeup_ports[2].bits.uop.ldst_is_rs1
connect slots_11.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[11].wakeup_ports[2].bits.uop.csr_cmd
connect slots_11.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[11].wakeup_ports[2].bits.uop.flush_on_commit
connect slots_11.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[11].wakeup_ports[2].bits.uop.is_unique
connect slots_11.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[11].wakeup_ports[2].bits.uop.uses_stq
connect slots_11.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[11].wakeup_ports[2].bits.uop.uses_ldq
connect slots_11.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[11].wakeup_ports[2].bits.uop.mem_signed
connect slots_11.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[11].wakeup_ports[2].bits.uop.mem_size
connect slots_11.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[11].wakeup_ports[2].bits.uop.mem_cmd
connect slots_11.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[11].wakeup_ports[2].bits.uop.exc_cause
connect slots_11.io.wakeup_ports[2].bits.uop.exception, issue_slots[11].wakeup_ports[2].bits.uop.exception
connect slots_11.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[11].wakeup_ports[2].bits.uop.stale_pdst
connect slots_11.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[11].wakeup_ports[2].bits.uop.ppred_busy
connect slots_11.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[11].wakeup_ports[2].bits.uop.prs3_busy
connect slots_11.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[11].wakeup_ports[2].bits.uop.prs2_busy
connect slots_11.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[11].wakeup_ports[2].bits.uop.prs1_busy
connect slots_11.io.wakeup_ports[2].bits.uop.ppred, issue_slots[11].wakeup_ports[2].bits.uop.ppred
connect slots_11.io.wakeup_ports[2].bits.uop.prs3, issue_slots[11].wakeup_ports[2].bits.uop.prs3
connect slots_11.io.wakeup_ports[2].bits.uop.prs2, issue_slots[11].wakeup_ports[2].bits.uop.prs2
connect slots_11.io.wakeup_ports[2].bits.uop.prs1, issue_slots[11].wakeup_ports[2].bits.uop.prs1
connect slots_11.io.wakeup_ports[2].bits.uop.pdst, issue_slots[11].wakeup_ports[2].bits.uop.pdst
connect slots_11.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[11].wakeup_ports[2].bits.uop.rxq_idx
connect slots_11.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[11].wakeup_ports[2].bits.uop.stq_idx
connect slots_11.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[11].wakeup_ports[2].bits.uop.ldq_idx
connect slots_11.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[11].wakeup_ports[2].bits.uop.rob_idx
connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.vec
connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.wflags
connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.sqrt
connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.div
connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.fma
connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe
connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.toint
connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.fromint
connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut
connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn
connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.swap23
connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.swap12
connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.ren3
connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.ren2
connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.ren1
connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.wen
connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.ldst
connect slots_11.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[11].wakeup_ports[2].bits.uop.op2_sel
connect slots_11.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[11].wakeup_ports[2].bits.uop.op1_sel
connect slots_11.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[11].wakeup_ports[2].bits.uop.imm_packed
connect slots_11.io.wakeup_ports[2].bits.uop.pimm, issue_slots[11].wakeup_ports[2].bits.uop.pimm
connect slots_11.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[11].wakeup_ports[2].bits.uop.imm_sel
connect slots_11.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[11].wakeup_ports[2].bits.uop.imm_rename
connect slots_11.io.wakeup_ports[2].bits.uop.taken, issue_slots[11].wakeup_ports[2].bits.uop.taken
connect slots_11.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[11].wakeup_ports[2].bits.uop.pc_lob
connect slots_11.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[11].wakeup_ports[2].bits.uop.edge_inst
connect slots_11.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[11].wakeup_ports[2].bits.uop.ftq_idx
connect slots_11.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[11].wakeup_ports[2].bits.uop.is_mov
connect slots_11.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[11].wakeup_ports[2].bits.uop.is_rocc
connect slots_11.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[11].wakeup_ports[2].bits.uop.is_sys_pc2epc
connect slots_11.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[11].wakeup_ports[2].bits.uop.is_eret
connect slots_11.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[11].wakeup_ports[2].bits.uop.is_amo
connect slots_11.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[11].wakeup_ports[2].bits.uop.is_sfence
connect slots_11.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[11].wakeup_ports[2].bits.uop.is_fencei
connect slots_11.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[11].wakeup_ports[2].bits.uop.is_fence
connect slots_11.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[11].wakeup_ports[2].bits.uop.is_sfb
connect slots_11.io.wakeup_ports[2].bits.uop.br_type, issue_slots[11].wakeup_ports[2].bits.uop.br_type
connect slots_11.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[11].wakeup_ports[2].bits.uop.br_tag
connect slots_11.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[11].wakeup_ports[2].bits.uop.br_mask
connect slots_11.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[11].wakeup_ports[2].bits.uop.dis_col_sel
connect slots_11.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[11].wakeup_ports[2].bits.uop.iw_p3_bypass_hint
connect slots_11.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[11].wakeup_ports[2].bits.uop.iw_p2_bypass_hint
connect slots_11.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[11].wakeup_ports[2].bits.uop.iw_p1_bypass_hint
connect slots_11.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[11].wakeup_ports[2].bits.uop.iw_p2_speculative_child
connect slots_11.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[11].wakeup_ports[2].bits.uop.iw_p1_speculative_child
connect slots_11.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[11].wakeup_ports[2].bits.uop.iw_issued_partial_dgen
connect slots_11.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[11].wakeup_ports[2].bits.uop.iw_issued_partial_agen
connect slots_11.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[11].wakeup_ports[2].bits.uop.iw_issued
connect slots_11.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[11].wakeup_ports[2].bits.uop.fu_code[0]
connect slots_11.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[11].wakeup_ports[2].bits.uop.fu_code[1]
connect slots_11.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[11].wakeup_ports[2].bits.uop.fu_code[2]
connect slots_11.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[11].wakeup_ports[2].bits.uop.fu_code[3]
connect slots_11.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[11].wakeup_ports[2].bits.uop.fu_code[4]
connect slots_11.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[11].wakeup_ports[2].bits.uop.fu_code[5]
connect slots_11.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[11].wakeup_ports[2].bits.uop.fu_code[6]
connect slots_11.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[11].wakeup_ports[2].bits.uop.fu_code[7]
connect slots_11.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[11].wakeup_ports[2].bits.uop.fu_code[8]
connect slots_11.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[11].wakeup_ports[2].bits.uop.fu_code[9]
connect slots_11.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[11].wakeup_ports[2].bits.uop.iq_type[0]
connect slots_11.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[11].wakeup_ports[2].bits.uop.iq_type[1]
connect slots_11.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[11].wakeup_ports[2].bits.uop.iq_type[2]
connect slots_11.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[11].wakeup_ports[2].bits.uop.iq_type[3]
connect slots_11.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[11].wakeup_ports[2].bits.uop.debug_pc
connect slots_11.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[11].wakeup_ports[2].bits.uop.is_rvc
connect slots_11.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[11].wakeup_ports[2].bits.uop.debug_inst
connect slots_11.io.wakeup_ports[2].bits.uop.inst, issue_slots[11].wakeup_ports[2].bits.uop.inst
connect slots_11.io.wakeup_ports[2].valid, issue_slots[11].wakeup_ports[2].valid
connect slots_11.io.wakeup_ports[3].bits.rebusy, issue_slots[11].wakeup_ports[3].bits.rebusy
connect slots_11.io.wakeup_ports[3].bits.speculative_mask, issue_slots[11].wakeup_ports[3].bits.speculative_mask
connect slots_11.io.wakeup_ports[3].bits.bypassable, issue_slots[11].wakeup_ports[3].bits.bypassable
connect slots_11.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[11].wakeup_ports[3].bits.uop.debug_tsrc
connect slots_11.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[11].wakeup_ports[3].bits.uop.debug_fsrc
connect slots_11.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[11].wakeup_ports[3].bits.uop.bp_xcpt_if
connect slots_11.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[11].wakeup_ports[3].bits.uop.bp_debug_if
connect slots_11.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[11].wakeup_ports[3].bits.uop.xcpt_ma_if
connect slots_11.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[11].wakeup_ports[3].bits.uop.xcpt_ae_if
connect slots_11.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[11].wakeup_ports[3].bits.uop.xcpt_pf_if
connect slots_11.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[11].wakeup_ports[3].bits.uop.fp_typ
connect slots_11.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[11].wakeup_ports[3].bits.uop.fp_rm
connect slots_11.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[11].wakeup_ports[3].bits.uop.fp_val
connect slots_11.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[11].wakeup_ports[3].bits.uop.fcn_op
connect slots_11.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[11].wakeup_ports[3].bits.uop.fcn_dw
connect slots_11.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[11].wakeup_ports[3].bits.uop.frs3_en
connect slots_11.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[11].wakeup_ports[3].bits.uop.lrs2_rtype
connect slots_11.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[11].wakeup_ports[3].bits.uop.lrs1_rtype
connect slots_11.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[11].wakeup_ports[3].bits.uop.dst_rtype
connect slots_11.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[11].wakeup_ports[3].bits.uop.lrs3
connect slots_11.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[11].wakeup_ports[3].bits.uop.lrs2
connect slots_11.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[11].wakeup_ports[3].bits.uop.lrs1
connect slots_11.io.wakeup_ports[3].bits.uop.ldst, issue_slots[11].wakeup_ports[3].bits.uop.ldst
connect slots_11.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[11].wakeup_ports[3].bits.uop.ldst_is_rs1
connect slots_11.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[11].wakeup_ports[3].bits.uop.csr_cmd
connect slots_11.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[11].wakeup_ports[3].bits.uop.flush_on_commit
connect slots_11.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[11].wakeup_ports[3].bits.uop.is_unique
connect slots_11.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[11].wakeup_ports[3].bits.uop.uses_stq
connect slots_11.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[11].wakeup_ports[3].bits.uop.uses_ldq
connect slots_11.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[11].wakeup_ports[3].bits.uop.mem_signed
connect slots_11.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[11].wakeup_ports[3].bits.uop.mem_size
connect slots_11.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[11].wakeup_ports[3].bits.uop.mem_cmd
connect slots_11.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[11].wakeup_ports[3].bits.uop.exc_cause
connect slots_11.io.wakeup_ports[3].bits.uop.exception, issue_slots[11].wakeup_ports[3].bits.uop.exception
connect slots_11.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[11].wakeup_ports[3].bits.uop.stale_pdst
connect slots_11.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[11].wakeup_ports[3].bits.uop.ppred_busy
connect slots_11.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[11].wakeup_ports[3].bits.uop.prs3_busy
connect slots_11.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[11].wakeup_ports[3].bits.uop.prs2_busy
connect slots_11.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[11].wakeup_ports[3].bits.uop.prs1_busy
connect slots_11.io.wakeup_ports[3].bits.uop.ppred, issue_slots[11].wakeup_ports[3].bits.uop.ppred
connect slots_11.io.wakeup_ports[3].bits.uop.prs3, issue_slots[11].wakeup_ports[3].bits.uop.prs3
connect slots_11.io.wakeup_ports[3].bits.uop.prs2, issue_slots[11].wakeup_ports[3].bits.uop.prs2
connect slots_11.io.wakeup_ports[3].bits.uop.prs1, issue_slots[11].wakeup_ports[3].bits.uop.prs1
connect slots_11.io.wakeup_ports[3].bits.uop.pdst, issue_slots[11].wakeup_ports[3].bits.uop.pdst
connect slots_11.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[11].wakeup_ports[3].bits.uop.rxq_idx
connect slots_11.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[11].wakeup_ports[3].bits.uop.stq_idx
connect slots_11.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[11].wakeup_ports[3].bits.uop.ldq_idx
connect slots_11.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[11].wakeup_ports[3].bits.uop.rob_idx
connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.vec
connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.wflags
connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.sqrt
connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.div
connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.fma
connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe
connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.toint
connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.fromint
connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut
connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn
connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.swap23
connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.swap12
connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.ren3
connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.ren2
connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.ren1
connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.wen
connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.ldst
connect slots_11.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[11].wakeup_ports[3].bits.uop.op2_sel
connect slots_11.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[11].wakeup_ports[3].bits.uop.op1_sel
connect slots_11.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[11].wakeup_ports[3].bits.uop.imm_packed
connect slots_11.io.wakeup_ports[3].bits.uop.pimm, issue_slots[11].wakeup_ports[3].bits.uop.pimm
connect slots_11.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[11].wakeup_ports[3].bits.uop.imm_sel
connect slots_11.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[11].wakeup_ports[3].bits.uop.imm_rename
connect slots_11.io.wakeup_ports[3].bits.uop.taken, issue_slots[11].wakeup_ports[3].bits.uop.taken
connect slots_11.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[11].wakeup_ports[3].bits.uop.pc_lob
connect slots_11.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[11].wakeup_ports[3].bits.uop.edge_inst
connect slots_11.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[11].wakeup_ports[3].bits.uop.ftq_idx
connect slots_11.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[11].wakeup_ports[3].bits.uop.is_mov
connect slots_11.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[11].wakeup_ports[3].bits.uop.is_rocc
connect slots_11.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[11].wakeup_ports[3].bits.uop.is_sys_pc2epc
connect slots_11.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[11].wakeup_ports[3].bits.uop.is_eret
connect slots_11.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[11].wakeup_ports[3].bits.uop.is_amo
connect slots_11.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[11].wakeup_ports[3].bits.uop.is_sfence
connect slots_11.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[11].wakeup_ports[3].bits.uop.is_fencei
connect slots_11.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[11].wakeup_ports[3].bits.uop.is_fence
connect slots_11.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[11].wakeup_ports[3].bits.uop.is_sfb
connect slots_11.io.wakeup_ports[3].bits.uop.br_type, issue_slots[11].wakeup_ports[3].bits.uop.br_type
connect slots_11.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[11].wakeup_ports[3].bits.uop.br_tag
connect slots_11.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[11].wakeup_ports[3].bits.uop.br_mask
connect slots_11.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[11].wakeup_ports[3].bits.uop.dis_col_sel
connect slots_11.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[11].wakeup_ports[3].bits.uop.iw_p3_bypass_hint
connect slots_11.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[11].wakeup_ports[3].bits.uop.iw_p2_bypass_hint
connect slots_11.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[11].wakeup_ports[3].bits.uop.iw_p1_bypass_hint
connect slots_11.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[11].wakeup_ports[3].bits.uop.iw_p2_speculative_child
connect slots_11.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[11].wakeup_ports[3].bits.uop.iw_p1_speculative_child
connect slots_11.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[11].wakeup_ports[3].bits.uop.iw_issued_partial_dgen
connect slots_11.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[11].wakeup_ports[3].bits.uop.iw_issued_partial_agen
connect slots_11.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[11].wakeup_ports[3].bits.uop.iw_issued
connect slots_11.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[11].wakeup_ports[3].bits.uop.fu_code[0]
connect slots_11.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[11].wakeup_ports[3].bits.uop.fu_code[1]
connect slots_11.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[11].wakeup_ports[3].bits.uop.fu_code[2]
connect slots_11.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[11].wakeup_ports[3].bits.uop.fu_code[3]
connect slots_11.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[11].wakeup_ports[3].bits.uop.fu_code[4]
connect slots_11.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[11].wakeup_ports[3].bits.uop.fu_code[5]
connect slots_11.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[11].wakeup_ports[3].bits.uop.fu_code[6]
connect slots_11.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[11].wakeup_ports[3].bits.uop.fu_code[7]
connect slots_11.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[11].wakeup_ports[3].bits.uop.fu_code[8]
connect slots_11.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[11].wakeup_ports[3].bits.uop.fu_code[9]
connect slots_11.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[11].wakeup_ports[3].bits.uop.iq_type[0]
connect slots_11.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[11].wakeup_ports[3].bits.uop.iq_type[1]
connect slots_11.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[11].wakeup_ports[3].bits.uop.iq_type[2]
connect slots_11.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[11].wakeup_ports[3].bits.uop.iq_type[3]
connect slots_11.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[11].wakeup_ports[3].bits.uop.debug_pc
connect slots_11.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[11].wakeup_ports[3].bits.uop.is_rvc
connect slots_11.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[11].wakeup_ports[3].bits.uop.debug_inst
connect slots_11.io.wakeup_ports[3].bits.uop.inst, issue_slots[11].wakeup_ports[3].bits.uop.inst
connect slots_11.io.wakeup_ports[3].valid, issue_slots[11].wakeup_ports[3].valid
connect slots_11.io.squash_grant, issue_slots[11].squash_grant
connect slots_11.io.clear, issue_slots[11].clear
connect slots_11.io.kill, issue_slots[11].kill
connect slots_11.io.brupdate.b2.target_offset, issue_slots[11].brupdate.b2.target_offset
connect slots_11.io.brupdate.b2.jalr_target, issue_slots[11].brupdate.b2.jalr_target
connect slots_11.io.brupdate.b2.pc_sel, issue_slots[11].brupdate.b2.pc_sel
connect slots_11.io.brupdate.b2.cfi_type, issue_slots[11].brupdate.b2.cfi_type
connect slots_11.io.brupdate.b2.taken, issue_slots[11].brupdate.b2.taken
connect slots_11.io.brupdate.b2.mispredict, issue_slots[11].brupdate.b2.mispredict
connect slots_11.io.brupdate.b2.uop.debug_tsrc, issue_slots[11].brupdate.b2.uop.debug_tsrc
connect slots_11.io.brupdate.b2.uop.debug_fsrc, issue_slots[11].brupdate.b2.uop.debug_fsrc
connect slots_11.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[11].brupdate.b2.uop.bp_xcpt_if
connect slots_11.io.brupdate.b2.uop.bp_debug_if, issue_slots[11].brupdate.b2.uop.bp_debug_if
connect slots_11.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[11].brupdate.b2.uop.xcpt_ma_if
connect slots_11.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[11].brupdate.b2.uop.xcpt_ae_if
connect slots_11.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[11].brupdate.b2.uop.xcpt_pf_if
connect slots_11.io.brupdate.b2.uop.fp_typ, issue_slots[11].brupdate.b2.uop.fp_typ
connect slots_11.io.brupdate.b2.uop.fp_rm, issue_slots[11].brupdate.b2.uop.fp_rm
connect slots_11.io.brupdate.b2.uop.fp_val, issue_slots[11].brupdate.b2.uop.fp_val
connect slots_11.io.brupdate.b2.uop.fcn_op, issue_slots[11].brupdate.b2.uop.fcn_op
connect slots_11.io.brupdate.b2.uop.fcn_dw, issue_slots[11].brupdate.b2.uop.fcn_dw
connect slots_11.io.brupdate.b2.uop.frs3_en, issue_slots[11].brupdate.b2.uop.frs3_en
connect slots_11.io.brupdate.b2.uop.lrs2_rtype, issue_slots[11].brupdate.b2.uop.lrs2_rtype
connect slots_11.io.brupdate.b2.uop.lrs1_rtype, issue_slots[11].brupdate.b2.uop.lrs1_rtype
connect slots_11.io.brupdate.b2.uop.dst_rtype, issue_slots[11].brupdate.b2.uop.dst_rtype
connect slots_11.io.brupdate.b2.uop.lrs3, issue_slots[11].brupdate.b2.uop.lrs3
connect slots_11.io.brupdate.b2.uop.lrs2, issue_slots[11].brupdate.b2.uop.lrs2
connect slots_11.io.brupdate.b2.uop.lrs1, issue_slots[11].brupdate.b2.uop.lrs1
connect slots_11.io.brupdate.b2.uop.ldst, issue_slots[11].brupdate.b2.uop.ldst
connect slots_11.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[11].brupdate.b2.uop.ldst_is_rs1
connect slots_11.io.brupdate.b2.uop.csr_cmd, issue_slots[11].brupdate.b2.uop.csr_cmd
connect slots_11.io.brupdate.b2.uop.flush_on_commit, issue_slots[11].brupdate.b2.uop.flush_on_commit
connect slots_11.io.brupdate.b2.uop.is_unique, issue_slots[11].brupdate.b2.uop.is_unique
connect slots_11.io.brupdate.b2.uop.uses_stq, issue_slots[11].brupdate.b2.uop.uses_stq
connect slots_11.io.brupdate.b2.uop.uses_ldq, issue_slots[11].brupdate.b2.uop.uses_ldq
connect slots_11.io.brupdate.b2.uop.mem_signed, issue_slots[11].brupdate.b2.uop.mem_signed
connect slots_11.io.brupdate.b2.uop.mem_size, issue_slots[11].brupdate.b2.uop.mem_size
connect slots_11.io.brupdate.b2.uop.mem_cmd, issue_slots[11].brupdate.b2.uop.mem_cmd
connect slots_11.io.brupdate.b2.uop.exc_cause, issue_slots[11].brupdate.b2.uop.exc_cause
connect slots_11.io.brupdate.b2.uop.exception, issue_slots[11].brupdate.b2.uop.exception
connect slots_11.io.brupdate.b2.uop.stale_pdst, issue_slots[11].brupdate.b2.uop.stale_pdst
connect slots_11.io.brupdate.b2.uop.ppred_busy, issue_slots[11].brupdate.b2.uop.ppred_busy
connect slots_11.io.brupdate.b2.uop.prs3_busy, issue_slots[11].brupdate.b2.uop.prs3_busy
connect slots_11.io.brupdate.b2.uop.prs2_busy, issue_slots[11].brupdate.b2.uop.prs2_busy
connect slots_11.io.brupdate.b2.uop.prs1_busy, issue_slots[11].brupdate.b2.uop.prs1_busy
connect slots_11.io.brupdate.b2.uop.ppred, issue_slots[11].brupdate.b2.uop.ppred
connect slots_11.io.brupdate.b2.uop.prs3, issue_slots[11].brupdate.b2.uop.prs3
connect slots_11.io.brupdate.b2.uop.prs2, issue_slots[11].brupdate.b2.uop.prs2
connect slots_11.io.brupdate.b2.uop.prs1, issue_slots[11].brupdate.b2.uop.prs1
connect slots_11.io.brupdate.b2.uop.pdst, issue_slots[11].brupdate.b2.uop.pdst
connect slots_11.io.brupdate.b2.uop.rxq_idx, issue_slots[11].brupdate.b2.uop.rxq_idx
connect slots_11.io.brupdate.b2.uop.stq_idx, issue_slots[11].brupdate.b2.uop.stq_idx
connect slots_11.io.brupdate.b2.uop.ldq_idx, issue_slots[11].brupdate.b2.uop.ldq_idx
connect slots_11.io.brupdate.b2.uop.rob_idx, issue_slots[11].brupdate.b2.uop.rob_idx
connect slots_11.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[11].brupdate.b2.uop.fp_ctrl.vec
connect slots_11.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[11].brupdate.b2.uop.fp_ctrl.wflags
connect slots_11.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[11].brupdate.b2.uop.fp_ctrl.sqrt
connect slots_11.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[11].brupdate.b2.uop.fp_ctrl.div
connect slots_11.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[11].brupdate.b2.uop.fp_ctrl.fma
connect slots_11.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[11].brupdate.b2.uop.fp_ctrl.fastpipe
connect slots_11.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[11].brupdate.b2.uop.fp_ctrl.toint
connect slots_11.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[11].brupdate.b2.uop.fp_ctrl.fromint
connect slots_11.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[11].brupdate.b2.uop.fp_ctrl.typeTagOut
connect slots_11.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[11].brupdate.b2.uop.fp_ctrl.typeTagIn
connect slots_11.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[11].brupdate.b2.uop.fp_ctrl.swap23
connect slots_11.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[11].brupdate.b2.uop.fp_ctrl.swap12
connect slots_11.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[11].brupdate.b2.uop.fp_ctrl.ren3
connect slots_11.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[11].brupdate.b2.uop.fp_ctrl.ren2
connect slots_11.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[11].brupdate.b2.uop.fp_ctrl.ren1
connect slots_11.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[11].brupdate.b2.uop.fp_ctrl.wen
connect slots_11.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[11].brupdate.b2.uop.fp_ctrl.ldst
connect slots_11.io.brupdate.b2.uop.op2_sel, issue_slots[11].brupdate.b2.uop.op2_sel
connect slots_11.io.brupdate.b2.uop.op1_sel, issue_slots[11].brupdate.b2.uop.op1_sel
connect slots_11.io.brupdate.b2.uop.imm_packed, issue_slots[11].brupdate.b2.uop.imm_packed
connect slots_11.io.brupdate.b2.uop.pimm, issue_slots[11].brupdate.b2.uop.pimm
connect slots_11.io.brupdate.b2.uop.imm_sel, issue_slots[11].brupdate.b2.uop.imm_sel
connect slots_11.io.brupdate.b2.uop.imm_rename, issue_slots[11].brupdate.b2.uop.imm_rename
connect slots_11.io.brupdate.b2.uop.taken, issue_slots[11].brupdate.b2.uop.taken
connect slots_11.io.brupdate.b2.uop.pc_lob, issue_slots[11].brupdate.b2.uop.pc_lob
connect slots_11.io.brupdate.b2.uop.edge_inst, issue_slots[11].brupdate.b2.uop.edge_inst
connect slots_11.io.brupdate.b2.uop.ftq_idx, issue_slots[11].brupdate.b2.uop.ftq_idx
connect slots_11.io.brupdate.b2.uop.is_mov, issue_slots[11].brupdate.b2.uop.is_mov
connect slots_11.io.brupdate.b2.uop.is_rocc, issue_slots[11].brupdate.b2.uop.is_rocc
connect slots_11.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[11].brupdate.b2.uop.is_sys_pc2epc
connect slots_11.io.brupdate.b2.uop.is_eret, issue_slots[11].brupdate.b2.uop.is_eret
connect slots_11.io.brupdate.b2.uop.is_amo, issue_slots[11].brupdate.b2.uop.is_amo
connect slots_11.io.brupdate.b2.uop.is_sfence, issue_slots[11].brupdate.b2.uop.is_sfence
connect slots_11.io.brupdate.b2.uop.is_fencei, issue_slots[11].brupdate.b2.uop.is_fencei
connect slots_11.io.brupdate.b2.uop.is_fence, issue_slots[11].brupdate.b2.uop.is_fence
connect slots_11.io.brupdate.b2.uop.is_sfb, issue_slots[11].brupdate.b2.uop.is_sfb
connect slots_11.io.brupdate.b2.uop.br_type, issue_slots[11].brupdate.b2.uop.br_type
connect slots_11.io.brupdate.b2.uop.br_tag, issue_slots[11].brupdate.b2.uop.br_tag
connect slots_11.io.brupdate.b2.uop.br_mask, issue_slots[11].brupdate.b2.uop.br_mask
connect slots_11.io.brupdate.b2.uop.dis_col_sel, issue_slots[11].brupdate.b2.uop.dis_col_sel
connect slots_11.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[11].brupdate.b2.uop.iw_p3_bypass_hint
connect slots_11.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[11].brupdate.b2.uop.iw_p2_bypass_hint
connect slots_11.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[11].brupdate.b2.uop.iw_p1_bypass_hint
connect slots_11.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[11].brupdate.b2.uop.iw_p2_speculative_child
connect slots_11.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[11].brupdate.b2.uop.iw_p1_speculative_child
connect slots_11.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[11].brupdate.b2.uop.iw_issued_partial_dgen
connect slots_11.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[11].brupdate.b2.uop.iw_issued_partial_agen
connect slots_11.io.brupdate.b2.uop.iw_issued, issue_slots[11].brupdate.b2.uop.iw_issued
connect slots_11.io.brupdate.b2.uop.fu_code[0], issue_slots[11].brupdate.b2.uop.fu_code[0]
connect slots_11.io.brupdate.b2.uop.fu_code[1], issue_slots[11].brupdate.b2.uop.fu_code[1]
connect slots_11.io.brupdate.b2.uop.fu_code[2], issue_slots[11].brupdate.b2.uop.fu_code[2]
connect slots_11.io.brupdate.b2.uop.fu_code[3], issue_slots[11].brupdate.b2.uop.fu_code[3]
connect slots_11.io.brupdate.b2.uop.fu_code[4], issue_slots[11].brupdate.b2.uop.fu_code[4]
connect slots_11.io.brupdate.b2.uop.fu_code[5], issue_slots[11].brupdate.b2.uop.fu_code[5]
connect slots_11.io.brupdate.b2.uop.fu_code[6], issue_slots[11].brupdate.b2.uop.fu_code[6]
connect slots_11.io.brupdate.b2.uop.fu_code[7], issue_slots[11].brupdate.b2.uop.fu_code[7]
connect slots_11.io.brupdate.b2.uop.fu_code[8], issue_slots[11].brupdate.b2.uop.fu_code[8]
connect slots_11.io.brupdate.b2.uop.fu_code[9], issue_slots[11].brupdate.b2.uop.fu_code[9]
connect slots_11.io.brupdate.b2.uop.iq_type[0], issue_slots[11].brupdate.b2.uop.iq_type[0]
connect slots_11.io.brupdate.b2.uop.iq_type[1], issue_slots[11].brupdate.b2.uop.iq_type[1]
connect slots_11.io.brupdate.b2.uop.iq_type[2], issue_slots[11].brupdate.b2.uop.iq_type[2]
connect slots_11.io.brupdate.b2.uop.iq_type[3], issue_slots[11].brupdate.b2.uop.iq_type[3]
connect slots_11.io.brupdate.b2.uop.debug_pc, issue_slots[11].brupdate.b2.uop.debug_pc
connect slots_11.io.brupdate.b2.uop.is_rvc, issue_slots[11].brupdate.b2.uop.is_rvc
connect slots_11.io.brupdate.b2.uop.debug_inst, issue_slots[11].brupdate.b2.uop.debug_inst
connect slots_11.io.brupdate.b2.uop.inst, issue_slots[11].brupdate.b2.uop.inst
connect slots_11.io.brupdate.b1.mispredict_mask, issue_slots[11].brupdate.b1.mispredict_mask
connect slots_11.io.brupdate.b1.resolve_mask, issue_slots[11].brupdate.b1.resolve_mask
connect issue_slots[11].out_uop.debug_tsrc, slots_11.io.out_uop.debug_tsrc
connect issue_slots[11].out_uop.debug_fsrc, slots_11.io.out_uop.debug_fsrc
connect issue_slots[11].out_uop.bp_xcpt_if, slots_11.io.out_uop.bp_xcpt_if
connect issue_slots[11].out_uop.bp_debug_if, slots_11.io.out_uop.bp_debug_if
connect issue_slots[11].out_uop.xcpt_ma_if, slots_11.io.out_uop.xcpt_ma_if
connect issue_slots[11].out_uop.xcpt_ae_if, slots_11.io.out_uop.xcpt_ae_if
connect issue_slots[11].out_uop.xcpt_pf_if, slots_11.io.out_uop.xcpt_pf_if
connect issue_slots[11].out_uop.fp_typ, slots_11.io.out_uop.fp_typ
connect issue_slots[11].out_uop.fp_rm, slots_11.io.out_uop.fp_rm
connect issue_slots[11].out_uop.fp_val, slots_11.io.out_uop.fp_val
connect issue_slots[11].out_uop.fcn_op, slots_11.io.out_uop.fcn_op
connect issue_slots[11].out_uop.fcn_dw, slots_11.io.out_uop.fcn_dw
connect issue_slots[11].out_uop.frs3_en, slots_11.io.out_uop.frs3_en
connect issue_slots[11].out_uop.lrs2_rtype, slots_11.io.out_uop.lrs2_rtype
connect issue_slots[11].out_uop.lrs1_rtype, slots_11.io.out_uop.lrs1_rtype
connect issue_slots[11].out_uop.dst_rtype, slots_11.io.out_uop.dst_rtype
connect issue_slots[11].out_uop.lrs3, slots_11.io.out_uop.lrs3
connect issue_slots[11].out_uop.lrs2, slots_11.io.out_uop.lrs2
connect issue_slots[11].out_uop.lrs1, slots_11.io.out_uop.lrs1
connect issue_slots[11].out_uop.ldst, slots_11.io.out_uop.ldst
connect issue_slots[11].out_uop.ldst_is_rs1, slots_11.io.out_uop.ldst_is_rs1
connect issue_slots[11].out_uop.csr_cmd, slots_11.io.out_uop.csr_cmd
connect issue_slots[11].out_uop.flush_on_commit, slots_11.io.out_uop.flush_on_commit
connect issue_slots[11].out_uop.is_unique, slots_11.io.out_uop.is_unique
connect issue_slots[11].out_uop.uses_stq, slots_11.io.out_uop.uses_stq
connect issue_slots[11].out_uop.uses_ldq, slots_11.io.out_uop.uses_ldq
connect issue_slots[11].out_uop.mem_signed, slots_11.io.out_uop.mem_signed
connect issue_slots[11].out_uop.mem_size, slots_11.io.out_uop.mem_size
connect issue_slots[11].out_uop.mem_cmd, slots_11.io.out_uop.mem_cmd
connect issue_slots[11].out_uop.exc_cause, slots_11.io.out_uop.exc_cause
connect issue_slots[11].out_uop.exception, slots_11.io.out_uop.exception
connect issue_slots[11].out_uop.stale_pdst, slots_11.io.out_uop.stale_pdst
connect issue_slots[11].out_uop.ppred_busy, slots_11.io.out_uop.ppred_busy
connect issue_slots[11].out_uop.prs3_busy, slots_11.io.out_uop.prs3_busy
connect issue_slots[11].out_uop.prs2_busy, slots_11.io.out_uop.prs2_busy
connect issue_slots[11].out_uop.prs1_busy, slots_11.io.out_uop.prs1_busy
connect issue_slots[11].out_uop.ppred, slots_11.io.out_uop.ppred
connect issue_slots[11].out_uop.prs3, slots_11.io.out_uop.prs3
connect issue_slots[11].out_uop.prs2, slots_11.io.out_uop.prs2
connect issue_slots[11].out_uop.prs1, slots_11.io.out_uop.prs1
connect issue_slots[11].out_uop.pdst, slots_11.io.out_uop.pdst
connect issue_slots[11].out_uop.rxq_idx, slots_11.io.out_uop.rxq_idx
connect issue_slots[11].out_uop.stq_idx, slots_11.io.out_uop.stq_idx
connect issue_slots[11].out_uop.ldq_idx, slots_11.io.out_uop.ldq_idx
connect issue_slots[11].out_uop.rob_idx, slots_11.io.out_uop.rob_idx
connect issue_slots[11].out_uop.fp_ctrl.vec, slots_11.io.out_uop.fp_ctrl.vec
connect issue_slots[11].out_uop.fp_ctrl.wflags, slots_11.io.out_uop.fp_ctrl.wflags
connect issue_slots[11].out_uop.fp_ctrl.sqrt, slots_11.io.out_uop.fp_ctrl.sqrt
connect issue_slots[11].out_uop.fp_ctrl.div, slots_11.io.out_uop.fp_ctrl.div
connect issue_slots[11].out_uop.fp_ctrl.fma, slots_11.io.out_uop.fp_ctrl.fma
connect issue_slots[11].out_uop.fp_ctrl.fastpipe, slots_11.io.out_uop.fp_ctrl.fastpipe
connect issue_slots[11].out_uop.fp_ctrl.toint, slots_11.io.out_uop.fp_ctrl.toint
connect issue_slots[11].out_uop.fp_ctrl.fromint, slots_11.io.out_uop.fp_ctrl.fromint
connect issue_slots[11].out_uop.fp_ctrl.typeTagOut, slots_11.io.out_uop.fp_ctrl.typeTagOut
connect issue_slots[11].out_uop.fp_ctrl.typeTagIn, slots_11.io.out_uop.fp_ctrl.typeTagIn
connect issue_slots[11].out_uop.fp_ctrl.swap23, slots_11.io.out_uop.fp_ctrl.swap23
connect issue_slots[11].out_uop.fp_ctrl.swap12, slots_11.io.out_uop.fp_ctrl.swap12
connect issue_slots[11].out_uop.fp_ctrl.ren3, slots_11.io.out_uop.fp_ctrl.ren3
connect issue_slots[11].out_uop.fp_ctrl.ren2, slots_11.io.out_uop.fp_ctrl.ren2
connect issue_slots[11].out_uop.fp_ctrl.ren1, slots_11.io.out_uop.fp_ctrl.ren1
connect issue_slots[11].out_uop.fp_ctrl.wen, slots_11.io.out_uop.fp_ctrl.wen
connect issue_slots[11].out_uop.fp_ctrl.ldst, slots_11.io.out_uop.fp_ctrl.ldst
connect issue_slots[11].out_uop.op2_sel, slots_11.io.out_uop.op2_sel
connect issue_slots[11].out_uop.op1_sel, slots_11.io.out_uop.op1_sel
connect issue_slots[11].out_uop.imm_packed, slots_11.io.out_uop.imm_packed
connect issue_slots[11].out_uop.pimm, slots_11.io.out_uop.pimm
connect issue_slots[11].out_uop.imm_sel, slots_11.io.out_uop.imm_sel
connect issue_slots[11].out_uop.imm_rename, slots_11.io.out_uop.imm_rename
connect issue_slots[11].out_uop.taken, slots_11.io.out_uop.taken
connect issue_slots[11].out_uop.pc_lob, slots_11.io.out_uop.pc_lob
connect issue_slots[11].out_uop.edge_inst, slots_11.io.out_uop.edge_inst
connect issue_slots[11].out_uop.ftq_idx, slots_11.io.out_uop.ftq_idx
connect issue_slots[11].out_uop.is_mov, slots_11.io.out_uop.is_mov
connect issue_slots[11].out_uop.is_rocc, slots_11.io.out_uop.is_rocc
connect issue_slots[11].out_uop.is_sys_pc2epc, slots_11.io.out_uop.is_sys_pc2epc
connect issue_slots[11].out_uop.is_eret, slots_11.io.out_uop.is_eret
connect issue_slots[11].out_uop.is_amo, slots_11.io.out_uop.is_amo
connect issue_slots[11].out_uop.is_sfence, slots_11.io.out_uop.is_sfence
connect issue_slots[11].out_uop.is_fencei, slots_11.io.out_uop.is_fencei
connect issue_slots[11].out_uop.is_fence, slots_11.io.out_uop.is_fence
connect issue_slots[11].out_uop.is_sfb, slots_11.io.out_uop.is_sfb
connect issue_slots[11].out_uop.br_type, slots_11.io.out_uop.br_type
connect issue_slots[11].out_uop.br_tag, slots_11.io.out_uop.br_tag
connect issue_slots[11].out_uop.br_mask, slots_11.io.out_uop.br_mask
connect issue_slots[11].out_uop.dis_col_sel, slots_11.io.out_uop.dis_col_sel
connect issue_slots[11].out_uop.iw_p3_bypass_hint, slots_11.io.out_uop.iw_p3_bypass_hint
connect issue_slots[11].out_uop.iw_p2_bypass_hint, slots_11.io.out_uop.iw_p2_bypass_hint
connect issue_slots[11].out_uop.iw_p1_bypass_hint, slots_11.io.out_uop.iw_p1_bypass_hint
connect issue_slots[11].out_uop.iw_p2_speculative_child, slots_11.io.out_uop.iw_p2_speculative_child
connect issue_slots[11].out_uop.iw_p1_speculative_child, slots_11.io.out_uop.iw_p1_speculative_child
connect issue_slots[11].out_uop.iw_issued_partial_dgen, slots_11.io.out_uop.iw_issued_partial_dgen
connect issue_slots[11].out_uop.iw_issued_partial_agen, slots_11.io.out_uop.iw_issued_partial_agen
connect issue_slots[11].out_uop.iw_issued, slots_11.io.out_uop.iw_issued
connect issue_slots[11].out_uop.fu_code[0], slots_11.io.out_uop.fu_code[0]
connect issue_slots[11].out_uop.fu_code[1], slots_11.io.out_uop.fu_code[1]
connect issue_slots[11].out_uop.fu_code[2], slots_11.io.out_uop.fu_code[2]
connect issue_slots[11].out_uop.fu_code[3], slots_11.io.out_uop.fu_code[3]
connect issue_slots[11].out_uop.fu_code[4], slots_11.io.out_uop.fu_code[4]
connect issue_slots[11].out_uop.fu_code[5], slots_11.io.out_uop.fu_code[5]
connect issue_slots[11].out_uop.fu_code[6], slots_11.io.out_uop.fu_code[6]
connect issue_slots[11].out_uop.fu_code[7], slots_11.io.out_uop.fu_code[7]
connect issue_slots[11].out_uop.fu_code[8], slots_11.io.out_uop.fu_code[8]
connect issue_slots[11].out_uop.fu_code[9], slots_11.io.out_uop.fu_code[9]
connect issue_slots[11].out_uop.iq_type[0], slots_11.io.out_uop.iq_type[0]
connect issue_slots[11].out_uop.iq_type[1], slots_11.io.out_uop.iq_type[1]
connect issue_slots[11].out_uop.iq_type[2], slots_11.io.out_uop.iq_type[2]
connect issue_slots[11].out_uop.iq_type[3], slots_11.io.out_uop.iq_type[3]
connect issue_slots[11].out_uop.debug_pc, slots_11.io.out_uop.debug_pc
connect issue_slots[11].out_uop.is_rvc, slots_11.io.out_uop.is_rvc
connect issue_slots[11].out_uop.debug_inst, slots_11.io.out_uop.debug_inst
connect issue_slots[11].out_uop.inst, slots_11.io.out_uop.inst
connect slots_11.io.in_uop.bits.debug_tsrc, issue_slots[11].in_uop.bits.debug_tsrc
connect slots_11.io.in_uop.bits.debug_fsrc, issue_slots[11].in_uop.bits.debug_fsrc
connect slots_11.io.in_uop.bits.bp_xcpt_if, issue_slots[11].in_uop.bits.bp_xcpt_if
connect slots_11.io.in_uop.bits.bp_debug_if, issue_slots[11].in_uop.bits.bp_debug_if
connect slots_11.io.in_uop.bits.xcpt_ma_if, issue_slots[11].in_uop.bits.xcpt_ma_if
connect slots_11.io.in_uop.bits.xcpt_ae_if, issue_slots[11].in_uop.bits.xcpt_ae_if
connect slots_11.io.in_uop.bits.xcpt_pf_if, issue_slots[11].in_uop.bits.xcpt_pf_if
connect slots_11.io.in_uop.bits.fp_typ, issue_slots[11].in_uop.bits.fp_typ
connect slots_11.io.in_uop.bits.fp_rm, issue_slots[11].in_uop.bits.fp_rm
connect slots_11.io.in_uop.bits.fp_val, issue_slots[11].in_uop.bits.fp_val
connect slots_11.io.in_uop.bits.fcn_op, issue_slots[11].in_uop.bits.fcn_op
connect slots_11.io.in_uop.bits.fcn_dw, issue_slots[11].in_uop.bits.fcn_dw
connect slots_11.io.in_uop.bits.frs3_en, issue_slots[11].in_uop.bits.frs3_en
connect slots_11.io.in_uop.bits.lrs2_rtype, issue_slots[11].in_uop.bits.lrs2_rtype
connect slots_11.io.in_uop.bits.lrs1_rtype, issue_slots[11].in_uop.bits.lrs1_rtype
connect slots_11.io.in_uop.bits.dst_rtype, issue_slots[11].in_uop.bits.dst_rtype
connect slots_11.io.in_uop.bits.lrs3, issue_slots[11].in_uop.bits.lrs3
connect slots_11.io.in_uop.bits.lrs2, issue_slots[11].in_uop.bits.lrs2
connect slots_11.io.in_uop.bits.lrs1, issue_slots[11].in_uop.bits.lrs1
connect slots_11.io.in_uop.bits.ldst, issue_slots[11].in_uop.bits.ldst
connect slots_11.io.in_uop.bits.ldst_is_rs1, issue_slots[11].in_uop.bits.ldst_is_rs1
connect slots_11.io.in_uop.bits.csr_cmd, issue_slots[11].in_uop.bits.csr_cmd
connect slots_11.io.in_uop.bits.flush_on_commit, issue_slots[11].in_uop.bits.flush_on_commit
connect slots_11.io.in_uop.bits.is_unique, issue_slots[11].in_uop.bits.is_unique
connect slots_11.io.in_uop.bits.uses_stq, issue_slots[11].in_uop.bits.uses_stq
connect slots_11.io.in_uop.bits.uses_ldq, issue_slots[11].in_uop.bits.uses_ldq
connect slots_11.io.in_uop.bits.mem_signed, issue_slots[11].in_uop.bits.mem_signed
connect slots_11.io.in_uop.bits.mem_size, issue_slots[11].in_uop.bits.mem_size
connect slots_11.io.in_uop.bits.mem_cmd, issue_slots[11].in_uop.bits.mem_cmd
connect slots_11.io.in_uop.bits.exc_cause, issue_slots[11].in_uop.bits.exc_cause
connect slots_11.io.in_uop.bits.exception, issue_slots[11].in_uop.bits.exception
connect slots_11.io.in_uop.bits.stale_pdst, issue_slots[11].in_uop.bits.stale_pdst
connect slots_11.io.in_uop.bits.ppred_busy, issue_slots[11].in_uop.bits.ppred_busy
connect slots_11.io.in_uop.bits.prs3_busy, issue_slots[11].in_uop.bits.prs3_busy
connect slots_11.io.in_uop.bits.prs2_busy, issue_slots[11].in_uop.bits.prs2_busy
connect slots_11.io.in_uop.bits.prs1_busy, issue_slots[11].in_uop.bits.prs1_busy
connect slots_11.io.in_uop.bits.ppred, issue_slots[11].in_uop.bits.ppred
connect slots_11.io.in_uop.bits.prs3, issue_slots[11].in_uop.bits.prs3
connect slots_11.io.in_uop.bits.prs2, issue_slots[11].in_uop.bits.prs2
connect slots_11.io.in_uop.bits.prs1, issue_slots[11].in_uop.bits.prs1
connect slots_11.io.in_uop.bits.pdst, issue_slots[11].in_uop.bits.pdst
connect slots_11.io.in_uop.bits.rxq_idx, issue_slots[11].in_uop.bits.rxq_idx
connect slots_11.io.in_uop.bits.stq_idx, issue_slots[11].in_uop.bits.stq_idx
connect slots_11.io.in_uop.bits.ldq_idx, issue_slots[11].in_uop.bits.ldq_idx
connect slots_11.io.in_uop.bits.rob_idx, issue_slots[11].in_uop.bits.rob_idx
connect slots_11.io.in_uop.bits.fp_ctrl.vec, issue_slots[11].in_uop.bits.fp_ctrl.vec
connect slots_11.io.in_uop.bits.fp_ctrl.wflags, issue_slots[11].in_uop.bits.fp_ctrl.wflags
connect slots_11.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[11].in_uop.bits.fp_ctrl.sqrt
connect slots_11.io.in_uop.bits.fp_ctrl.div, issue_slots[11].in_uop.bits.fp_ctrl.div
connect slots_11.io.in_uop.bits.fp_ctrl.fma, issue_slots[11].in_uop.bits.fp_ctrl.fma
connect slots_11.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[11].in_uop.bits.fp_ctrl.fastpipe
connect slots_11.io.in_uop.bits.fp_ctrl.toint, issue_slots[11].in_uop.bits.fp_ctrl.toint
connect slots_11.io.in_uop.bits.fp_ctrl.fromint, issue_slots[11].in_uop.bits.fp_ctrl.fromint
connect slots_11.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[11].in_uop.bits.fp_ctrl.typeTagOut
connect slots_11.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[11].in_uop.bits.fp_ctrl.typeTagIn
connect slots_11.io.in_uop.bits.fp_ctrl.swap23, issue_slots[11].in_uop.bits.fp_ctrl.swap23
connect slots_11.io.in_uop.bits.fp_ctrl.swap12, issue_slots[11].in_uop.bits.fp_ctrl.swap12
connect slots_11.io.in_uop.bits.fp_ctrl.ren3, issue_slots[11].in_uop.bits.fp_ctrl.ren3
connect slots_11.io.in_uop.bits.fp_ctrl.ren2, issue_slots[11].in_uop.bits.fp_ctrl.ren2
connect slots_11.io.in_uop.bits.fp_ctrl.ren1, issue_slots[11].in_uop.bits.fp_ctrl.ren1
connect slots_11.io.in_uop.bits.fp_ctrl.wen, issue_slots[11].in_uop.bits.fp_ctrl.wen
connect slots_11.io.in_uop.bits.fp_ctrl.ldst, issue_slots[11].in_uop.bits.fp_ctrl.ldst
connect slots_11.io.in_uop.bits.op2_sel, issue_slots[11].in_uop.bits.op2_sel
connect slots_11.io.in_uop.bits.op1_sel, issue_slots[11].in_uop.bits.op1_sel
connect slots_11.io.in_uop.bits.imm_packed, issue_slots[11].in_uop.bits.imm_packed
connect slots_11.io.in_uop.bits.pimm, issue_slots[11].in_uop.bits.pimm
connect slots_11.io.in_uop.bits.imm_sel, issue_slots[11].in_uop.bits.imm_sel
connect slots_11.io.in_uop.bits.imm_rename, issue_slots[11].in_uop.bits.imm_rename
connect slots_11.io.in_uop.bits.taken, issue_slots[11].in_uop.bits.taken
connect slots_11.io.in_uop.bits.pc_lob, issue_slots[11].in_uop.bits.pc_lob
connect slots_11.io.in_uop.bits.edge_inst, issue_slots[11].in_uop.bits.edge_inst
connect slots_11.io.in_uop.bits.ftq_idx, issue_slots[11].in_uop.bits.ftq_idx
connect slots_11.io.in_uop.bits.is_mov, issue_slots[11].in_uop.bits.is_mov
connect slots_11.io.in_uop.bits.is_rocc, issue_slots[11].in_uop.bits.is_rocc
connect slots_11.io.in_uop.bits.is_sys_pc2epc, issue_slots[11].in_uop.bits.is_sys_pc2epc
connect slots_11.io.in_uop.bits.is_eret, issue_slots[11].in_uop.bits.is_eret
connect slots_11.io.in_uop.bits.is_amo, issue_slots[11].in_uop.bits.is_amo
connect slots_11.io.in_uop.bits.is_sfence, issue_slots[11].in_uop.bits.is_sfence
connect slots_11.io.in_uop.bits.is_fencei, issue_slots[11].in_uop.bits.is_fencei
connect slots_11.io.in_uop.bits.is_fence, issue_slots[11].in_uop.bits.is_fence
connect slots_11.io.in_uop.bits.is_sfb, issue_slots[11].in_uop.bits.is_sfb
connect slots_11.io.in_uop.bits.br_type, issue_slots[11].in_uop.bits.br_type
connect slots_11.io.in_uop.bits.br_tag, issue_slots[11].in_uop.bits.br_tag
connect slots_11.io.in_uop.bits.br_mask, issue_slots[11].in_uop.bits.br_mask
connect slots_11.io.in_uop.bits.dis_col_sel, issue_slots[11].in_uop.bits.dis_col_sel
connect slots_11.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[11].in_uop.bits.iw_p3_bypass_hint
connect slots_11.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[11].in_uop.bits.iw_p2_bypass_hint
connect slots_11.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[11].in_uop.bits.iw_p1_bypass_hint
connect slots_11.io.in_uop.bits.iw_p2_speculative_child, issue_slots[11].in_uop.bits.iw_p2_speculative_child
connect slots_11.io.in_uop.bits.iw_p1_speculative_child, issue_slots[11].in_uop.bits.iw_p1_speculative_child
connect slots_11.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[11].in_uop.bits.iw_issued_partial_dgen
connect slots_11.io.in_uop.bits.iw_issued_partial_agen, issue_slots[11].in_uop.bits.iw_issued_partial_agen
connect slots_11.io.in_uop.bits.iw_issued, issue_slots[11].in_uop.bits.iw_issued
connect slots_11.io.in_uop.bits.fu_code[0], issue_slots[11].in_uop.bits.fu_code[0]
connect slots_11.io.in_uop.bits.fu_code[1], issue_slots[11].in_uop.bits.fu_code[1]
connect slots_11.io.in_uop.bits.fu_code[2], issue_slots[11].in_uop.bits.fu_code[2]
connect slots_11.io.in_uop.bits.fu_code[3], issue_slots[11].in_uop.bits.fu_code[3]
connect slots_11.io.in_uop.bits.fu_code[4], issue_slots[11].in_uop.bits.fu_code[4]
connect slots_11.io.in_uop.bits.fu_code[5], issue_slots[11].in_uop.bits.fu_code[5]
connect slots_11.io.in_uop.bits.fu_code[6], issue_slots[11].in_uop.bits.fu_code[6]
connect slots_11.io.in_uop.bits.fu_code[7], issue_slots[11].in_uop.bits.fu_code[7]
connect slots_11.io.in_uop.bits.fu_code[8], issue_slots[11].in_uop.bits.fu_code[8]
connect slots_11.io.in_uop.bits.fu_code[9], issue_slots[11].in_uop.bits.fu_code[9]
connect slots_11.io.in_uop.bits.iq_type[0], issue_slots[11].in_uop.bits.iq_type[0]
connect slots_11.io.in_uop.bits.iq_type[1], issue_slots[11].in_uop.bits.iq_type[1]
connect slots_11.io.in_uop.bits.iq_type[2], issue_slots[11].in_uop.bits.iq_type[2]
connect slots_11.io.in_uop.bits.iq_type[3], issue_slots[11].in_uop.bits.iq_type[3]
connect slots_11.io.in_uop.bits.debug_pc, issue_slots[11].in_uop.bits.debug_pc
connect slots_11.io.in_uop.bits.is_rvc, issue_slots[11].in_uop.bits.is_rvc
connect slots_11.io.in_uop.bits.debug_inst, issue_slots[11].in_uop.bits.debug_inst
connect slots_11.io.in_uop.bits.inst, issue_slots[11].in_uop.bits.inst
connect slots_11.io.in_uop.valid, issue_slots[11].in_uop.valid
connect issue_slots[11].iss_uop.debug_tsrc, slots_11.io.iss_uop.debug_tsrc
connect issue_slots[11].iss_uop.debug_fsrc, slots_11.io.iss_uop.debug_fsrc
connect issue_slots[11].iss_uop.bp_xcpt_if, slots_11.io.iss_uop.bp_xcpt_if
connect issue_slots[11].iss_uop.bp_debug_if, slots_11.io.iss_uop.bp_debug_if
connect issue_slots[11].iss_uop.xcpt_ma_if, slots_11.io.iss_uop.xcpt_ma_if
connect issue_slots[11].iss_uop.xcpt_ae_if, slots_11.io.iss_uop.xcpt_ae_if
connect issue_slots[11].iss_uop.xcpt_pf_if, slots_11.io.iss_uop.xcpt_pf_if
connect issue_slots[11].iss_uop.fp_typ, slots_11.io.iss_uop.fp_typ
connect issue_slots[11].iss_uop.fp_rm, slots_11.io.iss_uop.fp_rm
connect issue_slots[11].iss_uop.fp_val, slots_11.io.iss_uop.fp_val
connect issue_slots[11].iss_uop.fcn_op, slots_11.io.iss_uop.fcn_op
connect issue_slots[11].iss_uop.fcn_dw, slots_11.io.iss_uop.fcn_dw
connect issue_slots[11].iss_uop.frs3_en, slots_11.io.iss_uop.frs3_en
connect issue_slots[11].iss_uop.lrs2_rtype, slots_11.io.iss_uop.lrs2_rtype
connect issue_slots[11].iss_uop.lrs1_rtype, slots_11.io.iss_uop.lrs1_rtype
connect issue_slots[11].iss_uop.dst_rtype, slots_11.io.iss_uop.dst_rtype
connect issue_slots[11].iss_uop.lrs3, slots_11.io.iss_uop.lrs3
connect issue_slots[11].iss_uop.lrs2, slots_11.io.iss_uop.lrs2
connect issue_slots[11].iss_uop.lrs1, slots_11.io.iss_uop.lrs1
connect issue_slots[11].iss_uop.ldst, slots_11.io.iss_uop.ldst
connect issue_slots[11].iss_uop.ldst_is_rs1, slots_11.io.iss_uop.ldst_is_rs1
connect issue_slots[11].iss_uop.csr_cmd, slots_11.io.iss_uop.csr_cmd
connect issue_slots[11].iss_uop.flush_on_commit, slots_11.io.iss_uop.flush_on_commit
connect issue_slots[11].iss_uop.is_unique, slots_11.io.iss_uop.is_unique
connect issue_slots[11].iss_uop.uses_stq, slots_11.io.iss_uop.uses_stq
connect issue_slots[11].iss_uop.uses_ldq, slots_11.io.iss_uop.uses_ldq
connect issue_slots[11].iss_uop.mem_signed, slots_11.io.iss_uop.mem_signed
connect issue_slots[11].iss_uop.mem_size, slots_11.io.iss_uop.mem_size
connect issue_slots[11].iss_uop.mem_cmd, slots_11.io.iss_uop.mem_cmd
connect issue_slots[11].iss_uop.exc_cause, slots_11.io.iss_uop.exc_cause
connect issue_slots[11].iss_uop.exception, slots_11.io.iss_uop.exception
connect issue_slots[11].iss_uop.stale_pdst, slots_11.io.iss_uop.stale_pdst
connect issue_slots[11].iss_uop.ppred_busy, slots_11.io.iss_uop.ppred_busy
connect issue_slots[11].iss_uop.prs3_busy, slots_11.io.iss_uop.prs3_busy
connect issue_slots[11].iss_uop.prs2_busy, slots_11.io.iss_uop.prs2_busy
connect issue_slots[11].iss_uop.prs1_busy, slots_11.io.iss_uop.prs1_busy
connect issue_slots[11].iss_uop.ppred, slots_11.io.iss_uop.ppred
connect issue_slots[11].iss_uop.prs3, slots_11.io.iss_uop.prs3
connect issue_slots[11].iss_uop.prs2, slots_11.io.iss_uop.prs2
connect issue_slots[11].iss_uop.prs1, slots_11.io.iss_uop.prs1
connect issue_slots[11].iss_uop.pdst, slots_11.io.iss_uop.pdst
connect issue_slots[11].iss_uop.rxq_idx, slots_11.io.iss_uop.rxq_idx
connect issue_slots[11].iss_uop.stq_idx, slots_11.io.iss_uop.stq_idx
connect issue_slots[11].iss_uop.ldq_idx, slots_11.io.iss_uop.ldq_idx
connect issue_slots[11].iss_uop.rob_idx, slots_11.io.iss_uop.rob_idx
connect issue_slots[11].iss_uop.fp_ctrl.vec, slots_11.io.iss_uop.fp_ctrl.vec
connect issue_slots[11].iss_uop.fp_ctrl.wflags, slots_11.io.iss_uop.fp_ctrl.wflags
connect issue_slots[11].iss_uop.fp_ctrl.sqrt, slots_11.io.iss_uop.fp_ctrl.sqrt
connect issue_slots[11].iss_uop.fp_ctrl.div, slots_11.io.iss_uop.fp_ctrl.div
connect issue_slots[11].iss_uop.fp_ctrl.fma, slots_11.io.iss_uop.fp_ctrl.fma
connect issue_slots[11].iss_uop.fp_ctrl.fastpipe, slots_11.io.iss_uop.fp_ctrl.fastpipe
connect issue_slots[11].iss_uop.fp_ctrl.toint, slots_11.io.iss_uop.fp_ctrl.toint
connect issue_slots[11].iss_uop.fp_ctrl.fromint, slots_11.io.iss_uop.fp_ctrl.fromint
connect issue_slots[11].iss_uop.fp_ctrl.typeTagOut, slots_11.io.iss_uop.fp_ctrl.typeTagOut
connect issue_slots[11].iss_uop.fp_ctrl.typeTagIn, slots_11.io.iss_uop.fp_ctrl.typeTagIn
connect issue_slots[11].iss_uop.fp_ctrl.swap23, slots_11.io.iss_uop.fp_ctrl.swap23
connect issue_slots[11].iss_uop.fp_ctrl.swap12, slots_11.io.iss_uop.fp_ctrl.swap12
connect issue_slots[11].iss_uop.fp_ctrl.ren3, slots_11.io.iss_uop.fp_ctrl.ren3
connect issue_slots[11].iss_uop.fp_ctrl.ren2, slots_11.io.iss_uop.fp_ctrl.ren2
connect issue_slots[11].iss_uop.fp_ctrl.ren1, slots_11.io.iss_uop.fp_ctrl.ren1
connect issue_slots[11].iss_uop.fp_ctrl.wen, slots_11.io.iss_uop.fp_ctrl.wen
connect issue_slots[11].iss_uop.fp_ctrl.ldst, slots_11.io.iss_uop.fp_ctrl.ldst
connect issue_slots[11].iss_uop.op2_sel, slots_11.io.iss_uop.op2_sel
connect issue_slots[11].iss_uop.op1_sel, slots_11.io.iss_uop.op1_sel
connect issue_slots[11].iss_uop.imm_packed, slots_11.io.iss_uop.imm_packed
connect issue_slots[11].iss_uop.pimm, slots_11.io.iss_uop.pimm
connect issue_slots[11].iss_uop.imm_sel, slots_11.io.iss_uop.imm_sel
connect issue_slots[11].iss_uop.imm_rename, slots_11.io.iss_uop.imm_rename
connect issue_slots[11].iss_uop.taken, slots_11.io.iss_uop.taken
connect issue_slots[11].iss_uop.pc_lob, slots_11.io.iss_uop.pc_lob
connect issue_slots[11].iss_uop.edge_inst, slots_11.io.iss_uop.edge_inst
connect issue_slots[11].iss_uop.ftq_idx, slots_11.io.iss_uop.ftq_idx
connect issue_slots[11].iss_uop.is_mov, slots_11.io.iss_uop.is_mov
connect issue_slots[11].iss_uop.is_rocc, slots_11.io.iss_uop.is_rocc
connect issue_slots[11].iss_uop.is_sys_pc2epc, slots_11.io.iss_uop.is_sys_pc2epc
connect issue_slots[11].iss_uop.is_eret, slots_11.io.iss_uop.is_eret
connect issue_slots[11].iss_uop.is_amo, slots_11.io.iss_uop.is_amo
connect issue_slots[11].iss_uop.is_sfence, slots_11.io.iss_uop.is_sfence
connect issue_slots[11].iss_uop.is_fencei, slots_11.io.iss_uop.is_fencei
connect issue_slots[11].iss_uop.is_fence, slots_11.io.iss_uop.is_fence
connect issue_slots[11].iss_uop.is_sfb, slots_11.io.iss_uop.is_sfb
connect issue_slots[11].iss_uop.br_type, slots_11.io.iss_uop.br_type
connect issue_slots[11].iss_uop.br_tag, slots_11.io.iss_uop.br_tag
connect issue_slots[11].iss_uop.br_mask, slots_11.io.iss_uop.br_mask
connect issue_slots[11].iss_uop.dis_col_sel, slots_11.io.iss_uop.dis_col_sel
connect issue_slots[11].iss_uop.iw_p3_bypass_hint, slots_11.io.iss_uop.iw_p3_bypass_hint
connect issue_slots[11].iss_uop.iw_p2_bypass_hint, slots_11.io.iss_uop.iw_p2_bypass_hint
connect issue_slots[11].iss_uop.iw_p1_bypass_hint, slots_11.io.iss_uop.iw_p1_bypass_hint
connect issue_slots[11].iss_uop.iw_p2_speculative_child, slots_11.io.iss_uop.iw_p2_speculative_child
connect issue_slots[11].iss_uop.iw_p1_speculative_child, slots_11.io.iss_uop.iw_p1_speculative_child
connect issue_slots[11].iss_uop.iw_issued_partial_dgen, slots_11.io.iss_uop.iw_issued_partial_dgen
connect issue_slots[11].iss_uop.iw_issued_partial_agen, slots_11.io.iss_uop.iw_issued_partial_agen
connect issue_slots[11].iss_uop.iw_issued, slots_11.io.iss_uop.iw_issued
connect issue_slots[11].iss_uop.fu_code[0], slots_11.io.iss_uop.fu_code[0]
connect issue_slots[11].iss_uop.fu_code[1], slots_11.io.iss_uop.fu_code[1]
connect issue_slots[11].iss_uop.fu_code[2], slots_11.io.iss_uop.fu_code[2]
connect issue_slots[11].iss_uop.fu_code[3], slots_11.io.iss_uop.fu_code[3]
connect issue_slots[11].iss_uop.fu_code[4], slots_11.io.iss_uop.fu_code[4]
connect issue_slots[11].iss_uop.fu_code[5], slots_11.io.iss_uop.fu_code[5]
connect issue_slots[11].iss_uop.fu_code[6], slots_11.io.iss_uop.fu_code[6]
connect issue_slots[11].iss_uop.fu_code[7], slots_11.io.iss_uop.fu_code[7]
connect issue_slots[11].iss_uop.fu_code[8], slots_11.io.iss_uop.fu_code[8]
connect issue_slots[11].iss_uop.fu_code[9], slots_11.io.iss_uop.fu_code[9]
connect issue_slots[11].iss_uop.iq_type[0], slots_11.io.iss_uop.iq_type[0]
connect issue_slots[11].iss_uop.iq_type[1], slots_11.io.iss_uop.iq_type[1]
connect issue_slots[11].iss_uop.iq_type[2], slots_11.io.iss_uop.iq_type[2]
connect issue_slots[11].iss_uop.iq_type[3], slots_11.io.iss_uop.iq_type[3]
connect issue_slots[11].iss_uop.debug_pc, slots_11.io.iss_uop.debug_pc
connect issue_slots[11].iss_uop.is_rvc, slots_11.io.iss_uop.is_rvc
connect issue_slots[11].iss_uop.debug_inst, slots_11.io.iss_uop.debug_inst
connect issue_slots[11].iss_uop.inst, slots_11.io.iss_uop.inst
connect slots_11.io.grant, issue_slots[11].grant
connect issue_slots[11].request, slots_11.io.request
connect issue_slots[11].will_be_valid, slots_11.io.will_be_valid
connect issue_slots[11].valid, slots_11.io.valid
connect slots_12.io.child_rebusys, issue_slots[12].child_rebusys
connect slots_12.io.pred_wakeup_port.bits, issue_slots[12].pred_wakeup_port.bits
connect slots_12.io.pred_wakeup_port.valid, issue_slots[12].pred_wakeup_port.valid
connect slots_12.io.wakeup_ports[0].bits.rebusy, issue_slots[12].wakeup_ports[0].bits.rebusy
connect slots_12.io.wakeup_ports[0].bits.speculative_mask, issue_slots[12].wakeup_ports[0].bits.speculative_mask
connect slots_12.io.wakeup_ports[0].bits.bypassable, issue_slots[12].wakeup_ports[0].bits.bypassable
connect slots_12.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[12].wakeup_ports[0].bits.uop.debug_tsrc
connect slots_12.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[12].wakeup_ports[0].bits.uop.debug_fsrc
connect slots_12.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[12].wakeup_ports[0].bits.uop.bp_xcpt_if
connect slots_12.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[12].wakeup_ports[0].bits.uop.bp_debug_if
connect slots_12.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[12].wakeup_ports[0].bits.uop.xcpt_ma_if
connect slots_12.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[12].wakeup_ports[0].bits.uop.xcpt_ae_if
connect slots_12.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[12].wakeup_ports[0].bits.uop.xcpt_pf_if
connect slots_12.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[12].wakeup_ports[0].bits.uop.fp_typ
connect slots_12.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[12].wakeup_ports[0].bits.uop.fp_rm
connect slots_12.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[12].wakeup_ports[0].bits.uop.fp_val
connect slots_12.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[12].wakeup_ports[0].bits.uop.fcn_op
connect slots_12.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[12].wakeup_ports[0].bits.uop.fcn_dw
connect slots_12.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[12].wakeup_ports[0].bits.uop.frs3_en
connect slots_12.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[12].wakeup_ports[0].bits.uop.lrs2_rtype
connect slots_12.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[12].wakeup_ports[0].bits.uop.lrs1_rtype
connect slots_12.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[12].wakeup_ports[0].bits.uop.dst_rtype
connect slots_12.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[12].wakeup_ports[0].bits.uop.lrs3
connect slots_12.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[12].wakeup_ports[0].bits.uop.lrs2
connect slots_12.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[12].wakeup_ports[0].bits.uop.lrs1
connect slots_12.io.wakeup_ports[0].bits.uop.ldst, issue_slots[12].wakeup_ports[0].bits.uop.ldst
connect slots_12.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[12].wakeup_ports[0].bits.uop.ldst_is_rs1
connect slots_12.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[12].wakeup_ports[0].bits.uop.csr_cmd
connect slots_12.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[12].wakeup_ports[0].bits.uop.flush_on_commit
connect slots_12.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[12].wakeup_ports[0].bits.uop.is_unique
connect slots_12.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[12].wakeup_ports[0].bits.uop.uses_stq
connect slots_12.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[12].wakeup_ports[0].bits.uop.uses_ldq
connect slots_12.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[12].wakeup_ports[0].bits.uop.mem_signed
connect slots_12.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[12].wakeup_ports[0].bits.uop.mem_size
connect slots_12.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[12].wakeup_ports[0].bits.uop.mem_cmd
connect slots_12.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[12].wakeup_ports[0].bits.uop.exc_cause
connect slots_12.io.wakeup_ports[0].bits.uop.exception, issue_slots[12].wakeup_ports[0].bits.uop.exception
connect slots_12.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[12].wakeup_ports[0].bits.uop.stale_pdst
connect slots_12.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[12].wakeup_ports[0].bits.uop.ppred_busy
connect slots_12.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[12].wakeup_ports[0].bits.uop.prs3_busy
connect slots_12.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[12].wakeup_ports[0].bits.uop.prs2_busy
connect slots_12.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[12].wakeup_ports[0].bits.uop.prs1_busy
connect slots_12.io.wakeup_ports[0].bits.uop.ppred, issue_slots[12].wakeup_ports[0].bits.uop.ppred
connect slots_12.io.wakeup_ports[0].bits.uop.prs3, issue_slots[12].wakeup_ports[0].bits.uop.prs3
connect slots_12.io.wakeup_ports[0].bits.uop.prs2, issue_slots[12].wakeup_ports[0].bits.uop.prs2
connect slots_12.io.wakeup_ports[0].bits.uop.prs1, issue_slots[12].wakeup_ports[0].bits.uop.prs1
connect slots_12.io.wakeup_ports[0].bits.uop.pdst, issue_slots[12].wakeup_ports[0].bits.uop.pdst
connect slots_12.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[12].wakeup_ports[0].bits.uop.rxq_idx
connect slots_12.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[12].wakeup_ports[0].bits.uop.stq_idx
connect slots_12.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[12].wakeup_ports[0].bits.uop.ldq_idx
connect slots_12.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[12].wakeup_ports[0].bits.uop.rob_idx
connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.vec
connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.wflags
connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.sqrt
connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.div
connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.fma
connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe
connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.toint
connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.fromint
connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut
connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn
connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.swap23
connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.swap12
connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.ren3
connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.ren2
connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.ren1
connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.wen
connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.ldst
connect slots_12.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[12].wakeup_ports[0].bits.uop.op2_sel
connect slots_12.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[12].wakeup_ports[0].bits.uop.op1_sel
connect slots_12.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[12].wakeup_ports[0].bits.uop.imm_packed
connect slots_12.io.wakeup_ports[0].bits.uop.pimm, issue_slots[12].wakeup_ports[0].bits.uop.pimm
connect slots_12.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[12].wakeup_ports[0].bits.uop.imm_sel
connect slots_12.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[12].wakeup_ports[0].bits.uop.imm_rename
connect slots_12.io.wakeup_ports[0].bits.uop.taken, issue_slots[12].wakeup_ports[0].bits.uop.taken
connect slots_12.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[12].wakeup_ports[0].bits.uop.pc_lob
connect slots_12.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[12].wakeup_ports[0].bits.uop.edge_inst
connect slots_12.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[12].wakeup_ports[0].bits.uop.ftq_idx
connect slots_12.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[12].wakeup_ports[0].bits.uop.is_mov
connect slots_12.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[12].wakeup_ports[0].bits.uop.is_rocc
connect slots_12.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[12].wakeup_ports[0].bits.uop.is_sys_pc2epc
connect slots_12.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[12].wakeup_ports[0].bits.uop.is_eret
connect slots_12.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[12].wakeup_ports[0].bits.uop.is_amo
connect slots_12.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[12].wakeup_ports[0].bits.uop.is_sfence
connect slots_12.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[12].wakeup_ports[0].bits.uop.is_fencei
connect slots_12.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[12].wakeup_ports[0].bits.uop.is_fence
connect slots_12.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[12].wakeup_ports[0].bits.uop.is_sfb
connect slots_12.io.wakeup_ports[0].bits.uop.br_type, issue_slots[12].wakeup_ports[0].bits.uop.br_type
connect slots_12.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[12].wakeup_ports[0].bits.uop.br_tag
connect slots_12.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[12].wakeup_ports[0].bits.uop.br_mask
connect slots_12.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[12].wakeup_ports[0].bits.uop.dis_col_sel
connect slots_12.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[12].wakeup_ports[0].bits.uop.iw_p3_bypass_hint
connect slots_12.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[12].wakeup_ports[0].bits.uop.iw_p2_bypass_hint
connect slots_12.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[12].wakeup_ports[0].bits.uop.iw_p1_bypass_hint
connect slots_12.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[12].wakeup_ports[0].bits.uop.iw_p2_speculative_child
connect slots_12.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[12].wakeup_ports[0].bits.uop.iw_p1_speculative_child
connect slots_12.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[12].wakeup_ports[0].bits.uop.iw_issued_partial_dgen
connect slots_12.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[12].wakeup_ports[0].bits.uop.iw_issued_partial_agen
connect slots_12.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[12].wakeup_ports[0].bits.uop.iw_issued
connect slots_12.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[12].wakeup_ports[0].bits.uop.fu_code[0]
connect slots_12.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[12].wakeup_ports[0].bits.uop.fu_code[1]
connect slots_12.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[12].wakeup_ports[0].bits.uop.fu_code[2]
connect slots_12.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[12].wakeup_ports[0].bits.uop.fu_code[3]
connect slots_12.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[12].wakeup_ports[0].bits.uop.fu_code[4]
connect slots_12.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[12].wakeup_ports[0].bits.uop.fu_code[5]
connect slots_12.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[12].wakeup_ports[0].bits.uop.fu_code[6]
connect slots_12.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[12].wakeup_ports[0].bits.uop.fu_code[7]
connect slots_12.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[12].wakeup_ports[0].bits.uop.fu_code[8]
connect slots_12.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[12].wakeup_ports[0].bits.uop.fu_code[9]
connect slots_12.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[12].wakeup_ports[0].bits.uop.iq_type[0]
connect slots_12.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[12].wakeup_ports[0].bits.uop.iq_type[1]
connect slots_12.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[12].wakeup_ports[0].bits.uop.iq_type[2]
connect slots_12.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[12].wakeup_ports[0].bits.uop.iq_type[3]
connect slots_12.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[12].wakeup_ports[0].bits.uop.debug_pc
connect slots_12.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[12].wakeup_ports[0].bits.uop.is_rvc
connect slots_12.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[12].wakeup_ports[0].bits.uop.debug_inst
connect slots_12.io.wakeup_ports[0].bits.uop.inst, issue_slots[12].wakeup_ports[0].bits.uop.inst
connect slots_12.io.wakeup_ports[0].valid, issue_slots[12].wakeup_ports[0].valid
connect slots_12.io.wakeup_ports[1].bits.rebusy, issue_slots[12].wakeup_ports[1].bits.rebusy
connect slots_12.io.wakeup_ports[1].bits.speculative_mask, issue_slots[12].wakeup_ports[1].bits.speculative_mask
connect slots_12.io.wakeup_ports[1].bits.bypassable, issue_slots[12].wakeup_ports[1].bits.bypassable
connect slots_12.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[12].wakeup_ports[1].bits.uop.debug_tsrc
connect slots_12.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[12].wakeup_ports[1].bits.uop.debug_fsrc
connect slots_12.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[12].wakeup_ports[1].bits.uop.bp_xcpt_if
connect slots_12.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[12].wakeup_ports[1].bits.uop.bp_debug_if
connect slots_12.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[12].wakeup_ports[1].bits.uop.xcpt_ma_if
connect slots_12.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[12].wakeup_ports[1].bits.uop.xcpt_ae_if
connect slots_12.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[12].wakeup_ports[1].bits.uop.xcpt_pf_if
connect slots_12.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[12].wakeup_ports[1].bits.uop.fp_typ
connect slots_12.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[12].wakeup_ports[1].bits.uop.fp_rm
connect slots_12.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[12].wakeup_ports[1].bits.uop.fp_val
connect slots_12.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[12].wakeup_ports[1].bits.uop.fcn_op
connect slots_12.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[12].wakeup_ports[1].bits.uop.fcn_dw
connect slots_12.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[12].wakeup_ports[1].bits.uop.frs3_en
connect slots_12.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[12].wakeup_ports[1].bits.uop.lrs2_rtype
connect slots_12.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[12].wakeup_ports[1].bits.uop.lrs1_rtype
connect slots_12.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[12].wakeup_ports[1].bits.uop.dst_rtype
connect slots_12.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[12].wakeup_ports[1].bits.uop.lrs3
connect slots_12.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[12].wakeup_ports[1].bits.uop.lrs2
connect slots_12.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[12].wakeup_ports[1].bits.uop.lrs1
connect slots_12.io.wakeup_ports[1].bits.uop.ldst, issue_slots[12].wakeup_ports[1].bits.uop.ldst
connect slots_12.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[12].wakeup_ports[1].bits.uop.ldst_is_rs1
connect slots_12.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[12].wakeup_ports[1].bits.uop.csr_cmd
connect slots_12.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[12].wakeup_ports[1].bits.uop.flush_on_commit
connect slots_12.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[12].wakeup_ports[1].bits.uop.is_unique
connect slots_12.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[12].wakeup_ports[1].bits.uop.uses_stq
connect slots_12.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[12].wakeup_ports[1].bits.uop.uses_ldq
connect slots_12.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[12].wakeup_ports[1].bits.uop.mem_signed
connect slots_12.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[12].wakeup_ports[1].bits.uop.mem_size
connect slots_12.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[12].wakeup_ports[1].bits.uop.mem_cmd
connect slots_12.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[12].wakeup_ports[1].bits.uop.exc_cause
connect slots_12.io.wakeup_ports[1].bits.uop.exception, issue_slots[12].wakeup_ports[1].bits.uop.exception
connect slots_12.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[12].wakeup_ports[1].bits.uop.stale_pdst
connect slots_12.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[12].wakeup_ports[1].bits.uop.ppred_busy
connect slots_12.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[12].wakeup_ports[1].bits.uop.prs3_busy
connect slots_12.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[12].wakeup_ports[1].bits.uop.prs2_busy
connect slots_12.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[12].wakeup_ports[1].bits.uop.prs1_busy
connect slots_12.io.wakeup_ports[1].bits.uop.ppred, issue_slots[12].wakeup_ports[1].bits.uop.ppred
connect slots_12.io.wakeup_ports[1].bits.uop.prs3, issue_slots[12].wakeup_ports[1].bits.uop.prs3
connect slots_12.io.wakeup_ports[1].bits.uop.prs2, issue_slots[12].wakeup_ports[1].bits.uop.prs2
connect slots_12.io.wakeup_ports[1].bits.uop.prs1, issue_slots[12].wakeup_ports[1].bits.uop.prs1
connect slots_12.io.wakeup_ports[1].bits.uop.pdst, issue_slots[12].wakeup_ports[1].bits.uop.pdst
connect slots_12.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[12].wakeup_ports[1].bits.uop.rxq_idx
connect slots_12.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[12].wakeup_ports[1].bits.uop.stq_idx
connect slots_12.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[12].wakeup_ports[1].bits.uop.ldq_idx
connect slots_12.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[12].wakeup_ports[1].bits.uop.rob_idx
connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.vec
connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.wflags
connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.sqrt
connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.div
connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.fma
connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe
connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.toint
connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.fromint
connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut
connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn
connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.swap23
connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.swap12
connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.ren3
connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.ren2
connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.ren1
connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.wen
connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.ldst
connect slots_12.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[12].wakeup_ports[1].bits.uop.op2_sel
connect slots_12.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[12].wakeup_ports[1].bits.uop.op1_sel
connect slots_12.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[12].wakeup_ports[1].bits.uop.imm_packed
connect slots_12.io.wakeup_ports[1].bits.uop.pimm, issue_slots[12].wakeup_ports[1].bits.uop.pimm
connect slots_12.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[12].wakeup_ports[1].bits.uop.imm_sel
connect slots_12.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[12].wakeup_ports[1].bits.uop.imm_rename
connect slots_12.io.wakeup_ports[1].bits.uop.taken, issue_slots[12].wakeup_ports[1].bits.uop.taken
connect slots_12.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[12].wakeup_ports[1].bits.uop.pc_lob
connect slots_12.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[12].wakeup_ports[1].bits.uop.edge_inst
connect slots_12.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[12].wakeup_ports[1].bits.uop.ftq_idx
connect slots_12.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[12].wakeup_ports[1].bits.uop.is_mov
connect slots_12.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[12].wakeup_ports[1].bits.uop.is_rocc
connect slots_12.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[12].wakeup_ports[1].bits.uop.is_sys_pc2epc
connect slots_12.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[12].wakeup_ports[1].bits.uop.is_eret
connect slots_12.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[12].wakeup_ports[1].bits.uop.is_amo
connect slots_12.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[12].wakeup_ports[1].bits.uop.is_sfence
connect slots_12.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[12].wakeup_ports[1].bits.uop.is_fencei
connect slots_12.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[12].wakeup_ports[1].bits.uop.is_fence
connect slots_12.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[12].wakeup_ports[1].bits.uop.is_sfb
connect slots_12.io.wakeup_ports[1].bits.uop.br_type, issue_slots[12].wakeup_ports[1].bits.uop.br_type
connect slots_12.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[12].wakeup_ports[1].bits.uop.br_tag
connect slots_12.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[12].wakeup_ports[1].bits.uop.br_mask
connect slots_12.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[12].wakeup_ports[1].bits.uop.dis_col_sel
connect slots_12.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[12].wakeup_ports[1].bits.uop.iw_p3_bypass_hint
connect slots_12.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[12].wakeup_ports[1].bits.uop.iw_p2_bypass_hint
connect slots_12.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[12].wakeup_ports[1].bits.uop.iw_p1_bypass_hint
connect slots_12.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[12].wakeup_ports[1].bits.uop.iw_p2_speculative_child
connect slots_12.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[12].wakeup_ports[1].bits.uop.iw_p1_speculative_child
connect slots_12.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[12].wakeup_ports[1].bits.uop.iw_issued_partial_dgen
connect slots_12.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[12].wakeup_ports[1].bits.uop.iw_issued_partial_agen
connect slots_12.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[12].wakeup_ports[1].bits.uop.iw_issued
connect slots_12.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[12].wakeup_ports[1].bits.uop.fu_code[0]
connect slots_12.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[12].wakeup_ports[1].bits.uop.fu_code[1]
connect slots_12.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[12].wakeup_ports[1].bits.uop.fu_code[2]
connect slots_12.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[12].wakeup_ports[1].bits.uop.fu_code[3]
connect slots_12.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[12].wakeup_ports[1].bits.uop.fu_code[4]
connect slots_12.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[12].wakeup_ports[1].bits.uop.fu_code[5]
connect slots_12.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[12].wakeup_ports[1].bits.uop.fu_code[6]
connect slots_12.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[12].wakeup_ports[1].bits.uop.fu_code[7]
connect slots_12.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[12].wakeup_ports[1].bits.uop.fu_code[8]
connect slots_12.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[12].wakeup_ports[1].bits.uop.fu_code[9]
connect slots_12.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[12].wakeup_ports[1].bits.uop.iq_type[0]
connect slots_12.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[12].wakeup_ports[1].bits.uop.iq_type[1]
connect slots_12.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[12].wakeup_ports[1].bits.uop.iq_type[2]
connect slots_12.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[12].wakeup_ports[1].bits.uop.iq_type[3]
connect slots_12.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[12].wakeup_ports[1].bits.uop.debug_pc
connect slots_12.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[12].wakeup_ports[1].bits.uop.is_rvc
connect slots_12.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[12].wakeup_ports[1].bits.uop.debug_inst
connect slots_12.io.wakeup_ports[1].bits.uop.inst, issue_slots[12].wakeup_ports[1].bits.uop.inst
connect slots_12.io.wakeup_ports[1].valid, issue_slots[12].wakeup_ports[1].valid
connect slots_12.io.wakeup_ports[2].bits.rebusy, issue_slots[12].wakeup_ports[2].bits.rebusy
connect slots_12.io.wakeup_ports[2].bits.speculative_mask, issue_slots[12].wakeup_ports[2].bits.speculative_mask
connect slots_12.io.wakeup_ports[2].bits.bypassable, issue_slots[12].wakeup_ports[2].bits.bypassable
connect slots_12.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[12].wakeup_ports[2].bits.uop.debug_tsrc
connect slots_12.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[12].wakeup_ports[2].bits.uop.debug_fsrc
connect slots_12.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[12].wakeup_ports[2].bits.uop.bp_xcpt_if
connect slots_12.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[12].wakeup_ports[2].bits.uop.bp_debug_if
connect slots_12.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[12].wakeup_ports[2].bits.uop.xcpt_ma_if
connect slots_12.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[12].wakeup_ports[2].bits.uop.xcpt_ae_if
connect slots_12.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[12].wakeup_ports[2].bits.uop.xcpt_pf_if
connect slots_12.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[12].wakeup_ports[2].bits.uop.fp_typ
connect slots_12.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[12].wakeup_ports[2].bits.uop.fp_rm
connect slots_12.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[12].wakeup_ports[2].bits.uop.fp_val
connect slots_12.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[12].wakeup_ports[2].bits.uop.fcn_op
connect slots_12.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[12].wakeup_ports[2].bits.uop.fcn_dw
connect slots_12.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[12].wakeup_ports[2].bits.uop.frs3_en
connect slots_12.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[12].wakeup_ports[2].bits.uop.lrs2_rtype
connect slots_12.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[12].wakeup_ports[2].bits.uop.lrs1_rtype
connect slots_12.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[12].wakeup_ports[2].bits.uop.dst_rtype
connect slots_12.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[12].wakeup_ports[2].bits.uop.lrs3
connect slots_12.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[12].wakeup_ports[2].bits.uop.lrs2
connect slots_12.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[12].wakeup_ports[2].bits.uop.lrs1
connect slots_12.io.wakeup_ports[2].bits.uop.ldst, issue_slots[12].wakeup_ports[2].bits.uop.ldst
connect slots_12.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[12].wakeup_ports[2].bits.uop.ldst_is_rs1
connect slots_12.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[12].wakeup_ports[2].bits.uop.csr_cmd
connect slots_12.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[12].wakeup_ports[2].bits.uop.flush_on_commit
connect slots_12.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[12].wakeup_ports[2].bits.uop.is_unique
connect slots_12.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[12].wakeup_ports[2].bits.uop.uses_stq
connect slots_12.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[12].wakeup_ports[2].bits.uop.uses_ldq
connect slots_12.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[12].wakeup_ports[2].bits.uop.mem_signed
connect slots_12.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[12].wakeup_ports[2].bits.uop.mem_size
connect slots_12.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[12].wakeup_ports[2].bits.uop.mem_cmd
connect slots_12.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[12].wakeup_ports[2].bits.uop.exc_cause
connect slots_12.io.wakeup_ports[2].bits.uop.exception, issue_slots[12].wakeup_ports[2].bits.uop.exception
connect slots_12.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[12].wakeup_ports[2].bits.uop.stale_pdst
connect slots_12.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[12].wakeup_ports[2].bits.uop.ppred_busy
connect slots_12.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[12].wakeup_ports[2].bits.uop.prs3_busy
connect slots_12.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[12].wakeup_ports[2].bits.uop.prs2_busy
connect slots_12.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[12].wakeup_ports[2].bits.uop.prs1_busy
connect slots_12.io.wakeup_ports[2].bits.uop.ppred, issue_slots[12].wakeup_ports[2].bits.uop.ppred
connect slots_12.io.wakeup_ports[2].bits.uop.prs3, issue_slots[12].wakeup_ports[2].bits.uop.prs3
connect slots_12.io.wakeup_ports[2].bits.uop.prs2, issue_slots[12].wakeup_ports[2].bits.uop.prs2
connect slots_12.io.wakeup_ports[2].bits.uop.prs1, issue_slots[12].wakeup_ports[2].bits.uop.prs1
connect slots_12.io.wakeup_ports[2].bits.uop.pdst, issue_slots[12].wakeup_ports[2].bits.uop.pdst
connect slots_12.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[12].wakeup_ports[2].bits.uop.rxq_idx
connect slots_12.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[12].wakeup_ports[2].bits.uop.stq_idx
connect slots_12.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[12].wakeup_ports[2].bits.uop.ldq_idx
connect slots_12.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[12].wakeup_ports[2].bits.uop.rob_idx
connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.vec
connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.wflags
connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.sqrt
connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.div
connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.fma
connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe
connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.toint
connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.fromint
connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut
connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn
connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.swap23
connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.swap12
connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.ren3
connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.ren2
connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.ren1
connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.wen
connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.ldst
connect slots_12.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[12].wakeup_ports[2].bits.uop.op2_sel
connect slots_12.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[12].wakeup_ports[2].bits.uop.op1_sel
connect slots_12.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[12].wakeup_ports[2].bits.uop.imm_packed
connect slots_12.io.wakeup_ports[2].bits.uop.pimm, issue_slots[12].wakeup_ports[2].bits.uop.pimm
connect slots_12.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[12].wakeup_ports[2].bits.uop.imm_sel
connect slots_12.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[12].wakeup_ports[2].bits.uop.imm_rename
connect slots_12.io.wakeup_ports[2].bits.uop.taken, issue_slots[12].wakeup_ports[2].bits.uop.taken
connect slots_12.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[12].wakeup_ports[2].bits.uop.pc_lob
connect slots_12.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[12].wakeup_ports[2].bits.uop.edge_inst
connect slots_12.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[12].wakeup_ports[2].bits.uop.ftq_idx
connect slots_12.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[12].wakeup_ports[2].bits.uop.is_mov
connect slots_12.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[12].wakeup_ports[2].bits.uop.is_rocc
connect slots_12.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[12].wakeup_ports[2].bits.uop.is_sys_pc2epc
connect slots_12.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[12].wakeup_ports[2].bits.uop.is_eret
connect slots_12.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[12].wakeup_ports[2].bits.uop.is_amo
connect slots_12.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[12].wakeup_ports[2].bits.uop.is_sfence
connect slots_12.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[12].wakeup_ports[2].bits.uop.is_fencei
connect slots_12.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[12].wakeup_ports[2].bits.uop.is_fence
connect slots_12.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[12].wakeup_ports[2].bits.uop.is_sfb
connect slots_12.io.wakeup_ports[2].bits.uop.br_type, issue_slots[12].wakeup_ports[2].bits.uop.br_type
connect slots_12.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[12].wakeup_ports[2].bits.uop.br_tag
connect slots_12.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[12].wakeup_ports[2].bits.uop.br_mask
connect slots_12.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[12].wakeup_ports[2].bits.uop.dis_col_sel
connect slots_12.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[12].wakeup_ports[2].bits.uop.iw_p3_bypass_hint
connect slots_12.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[12].wakeup_ports[2].bits.uop.iw_p2_bypass_hint
connect slots_12.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[12].wakeup_ports[2].bits.uop.iw_p1_bypass_hint
connect slots_12.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[12].wakeup_ports[2].bits.uop.iw_p2_speculative_child
connect slots_12.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[12].wakeup_ports[2].bits.uop.iw_p1_speculative_child
connect slots_12.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[12].wakeup_ports[2].bits.uop.iw_issued_partial_dgen
connect slots_12.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[12].wakeup_ports[2].bits.uop.iw_issued_partial_agen
connect slots_12.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[12].wakeup_ports[2].bits.uop.iw_issued
connect slots_12.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[12].wakeup_ports[2].bits.uop.fu_code[0]
connect slots_12.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[12].wakeup_ports[2].bits.uop.fu_code[1]
connect slots_12.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[12].wakeup_ports[2].bits.uop.fu_code[2]
connect slots_12.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[12].wakeup_ports[2].bits.uop.fu_code[3]
connect slots_12.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[12].wakeup_ports[2].bits.uop.fu_code[4]
connect slots_12.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[12].wakeup_ports[2].bits.uop.fu_code[5]
connect slots_12.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[12].wakeup_ports[2].bits.uop.fu_code[6]
connect slots_12.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[12].wakeup_ports[2].bits.uop.fu_code[7]
connect slots_12.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[12].wakeup_ports[2].bits.uop.fu_code[8]
connect slots_12.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[12].wakeup_ports[2].bits.uop.fu_code[9]
connect slots_12.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[12].wakeup_ports[2].bits.uop.iq_type[0]
connect slots_12.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[12].wakeup_ports[2].bits.uop.iq_type[1]
connect slots_12.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[12].wakeup_ports[2].bits.uop.iq_type[2]
connect slots_12.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[12].wakeup_ports[2].bits.uop.iq_type[3]
connect slots_12.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[12].wakeup_ports[2].bits.uop.debug_pc
connect slots_12.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[12].wakeup_ports[2].bits.uop.is_rvc
connect slots_12.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[12].wakeup_ports[2].bits.uop.debug_inst
connect slots_12.io.wakeup_ports[2].bits.uop.inst, issue_slots[12].wakeup_ports[2].bits.uop.inst
connect slots_12.io.wakeup_ports[2].valid, issue_slots[12].wakeup_ports[2].valid
connect slots_12.io.wakeup_ports[3].bits.rebusy, issue_slots[12].wakeup_ports[3].bits.rebusy
connect slots_12.io.wakeup_ports[3].bits.speculative_mask, issue_slots[12].wakeup_ports[3].bits.speculative_mask
connect slots_12.io.wakeup_ports[3].bits.bypassable, issue_slots[12].wakeup_ports[3].bits.bypassable
connect slots_12.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[12].wakeup_ports[3].bits.uop.debug_tsrc
connect slots_12.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[12].wakeup_ports[3].bits.uop.debug_fsrc
connect slots_12.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[12].wakeup_ports[3].bits.uop.bp_xcpt_if
connect slots_12.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[12].wakeup_ports[3].bits.uop.bp_debug_if
connect slots_12.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[12].wakeup_ports[3].bits.uop.xcpt_ma_if
connect slots_12.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[12].wakeup_ports[3].bits.uop.xcpt_ae_if
connect slots_12.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[12].wakeup_ports[3].bits.uop.xcpt_pf_if
connect slots_12.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[12].wakeup_ports[3].bits.uop.fp_typ
connect slots_12.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[12].wakeup_ports[3].bits.uop.fp_rm
connect slots_12.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[12].wakeup_ports[3].bits.uop.fp_val
connect slots_12.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[12].wakeup_ports[3].bits.uop.fcn_op
connect slots_12.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[12].wakeup_ports[3].bits.uop.fcn_dw
connect slots_12.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[12].wakeup_ports[3].bits.uop.frs3_en
connect slots_12.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[12].wakeup_ports[3].bits.uop.lrs2_rtype
connect slots_12.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[12].wakeup_ports[3].bits.uop.lrs1_rtype
connect slots_12.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[12].wakeup_ports[3].bits.uop.dst_rtype
connect slots_12.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[12].wakeup_ports[3].bits.uop.lrs3
connect slots_12.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[12].wakeup_ports[3].bits.uop.lrs2
connect slots_12.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[12].wakeup_ports[3].bits.uop.lrs1
connect slots_12.io.wakeup_ports[3].bits.uop.ldst, issue_slots[12].wakeup_ports[3].bits.uop.ldst
connect slots_12.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[12].wakeup_ports[3].bits.uop.ldst_is_rs1
connect slots_12.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[12].wakeup_ports[3].bits.uop.csr_cmd
connect slots_12.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[12].wakeup_ports[3].bits.uop.flush_on_commit
connect slots_12.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[12].wakeup_ports[3].bits.uop.is_unique
connect slots_12.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[12].wakeup_ports[3].bits.uop.uses_stq
connect slots_12.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[12].wakeup_ports[3].bits.uop.uses_ldq
connect slots_12.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[12].wakeup_ports[3].bits.uop.mem_signed
connect slots_12.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[12].wakeup_ports[3].bits.uop.mem_size
connect slots_12.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[12].wakeup_ports[3].bits.uop.mem_cmd
connect slots_12.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[12].wakeup_ports[3].bits.uop.exc_cause
connect slots_12.io.wakeup_ports[3].bits.uop.exception, issue_slots[12].wakeup_ports[3].bits.uop.exception
connect slots_12.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[12].wakeup_ports[3].bits.uop.stale_pdst
connect slots_12.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[12].wakeup_ports[3].bits.uop.ppred_busy
connect slots_12.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[12].wakeup_ports[3].bits.uop.prs3_busy
connect slots_12.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[12].wakeup_ports[3].bits.uop.prs2_busy
connect slots_12.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[12].wakeup_ports[3].bits.uop.prs1_busy
connect slots_12.io.wakeup_ports[3].bits.uop.ppred, issue_slots[12].wakeup_ports[3].bits.uop.ppred
connect slots_12.io.wakeup_ports[3].bits.uop.prs3, issue_slots[12].wakeup_ports[3].bits.uop.prs3
connect slots_12.io.wakeup_ports[3].bits.uop.prs2, issue_slots[12].wakeup_ports[3].bits.uop.prs2
connect slots_12.io.wakeup_ports[3].bits.uop.prs1, issue_slots[12].wakeup_ports[3].bits.uop.prs1
connect slots_12.io.wakeup_ports[3].bits.uop.pdst, issue_slots[12].wakeup_ports[3].bits.uop.pdst
connect slots_12.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[12].wakeup_ports[3].bits.uop.rxq_idx
connect slots_12.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[12].wakeup_ports[3].bits.uop.stq_idx
connect slots_12.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[12].wakeup_ports[3].bits.uop.ldq_idx
connect slots_12.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[12].wakeup_ports[3].bits.uop.rob_idx
connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.vec
connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.wflags
connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.sqrt
connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.div
connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.fma
connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe
connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.toint
connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.fromint
connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut
connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn
connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.swap23
connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.swap12
connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.ren3
connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.ren2
connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.ren1
connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.wen
connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.ldst
connect slots_12.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[12].wakeup_ports[3].bits.uop.op2_sel
connect slots_12.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[12].wakeup_ports[3].bits.uop.op1_sel
connect slots_12.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[12].wakeup_ports[3].bits.uop.imm_packed
connect slots_12.io.wakeup_ports[3].bits.uop.pimm, issue_slots[12].wakeup_ports[3].bits.uop.pimm
connect slots_12.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[12].wakeup_ports[3].bits.uop.imm_sel
connect slots_12.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[12].wakeup_ports[3].bits.uop.imm_rename
connect slots_12.io.wakeup_ports[3].bits.uop.taken, issue_slots[12].wakeup_ports[3].bits.uop.taken
connect slots_12.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[12].wakeup_ports[3].bits.uop.pc_lob
connect slots_12.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[12].wakeup_ports[3].bits.uop.edge_inst
connect slots_12.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[12].wakeup_ports[3].bits.uop.ftq_idx
connect slots_12.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[12].wakeup_ports[3].bits.uop.is_mov
connect slots_12.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[12].wakeup_ports[3].bits.uop.is_rocc
connect slots_12.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[12].wakeup_ports[3].bits.uop.is_sys_pc2epc
connect slots_12.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[12].wakeup_ports[3].bits.uop.is_eret
connect slots_12.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[12].wakeup_ports[3].bits.uop.is_amo
connect slots_12.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[12].wakeup_ports[3].bits.uop.is_sfence
connect slots_12.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[12].wakeup_ports[3].bits.uop.is_fencei
connect slots_12.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[12].wakeup_ports[3].bits.uop.is_fence
connect slots_12.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[12].wakeup_ports[3].bits.uop.is_sfb
connect slots_12.io.wakeup_ports[3].bits.uop.br_type, issue_slots[12].wakeup_ports[3].bits.uop.br_type
connect slots_12.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[12].wakeup_ports[3].bits.uop.br_tag
connect slots_12.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[12].wakeup_ports[3].bits.uop.br_mask
connect slots_12.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[12].wakeup_ports[3].bits.uop.dis_col_sel
connect slots_12.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[12].wakeup_ports[3].bits.uop.iw_p3_bypass_hint
connect slots_12.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[12].wakeup_ports[3].bits.uop.iw_p2_bypass_hint
connect slots_12.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[12].wakeup_ports[3].bits.uop.iw_p1_bypass_hint
connect slots_12.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[12].wakeup_ports[3].bits.uop.iw_p2_speculative_child
connect slots_12.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[12].wakeup_ports[3].bits.uop.iw_p1_speculative_child
connect slots_12.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[12].wakeup_ports[3].bits.uop.iw_issued_partial_dgen
connect slots_12.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[12].wakeup_ports[3].bits.uop.iw_issued_partial_agen
connect slots_12.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[12].wakeup_ports[3].bits.uop.iw_issued
connect slots_12.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[12].wakeup_ports[3].bits.uop.fu_code[0]
connect slots_12.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[12].wakeup_ports[3].bits.uop.fu_code[1]
connect slots_12.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[12].wakeup_ports[3].bits.uop.fu_code[2]
connect slots_12.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[12].wakeup_ports[3].bits.uop.fu_code[3]
connect slots_12.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[12].wakeup_ports[3].bits.uop.fu_code[4]
connect slots_12.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[12].wakeup_ports[3].bits.uop.fu_code[5]
connect slots_12.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[12].wakeup_ports[3].bits.uop.fu_code[6]
connect slots_12.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[12].wakeup_ports[3].bits.uop.fu_code[7]
connect slots_12.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[12].wakeup_ports[3].bits.uop.fu_code[8]
connect slots_12.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[12].wakeup_ports[3].bits.uop.fu_code[9]
connect slots_12.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[12].wakeup_ports[3].bits.uop.iq_type[0]
connect slots_12.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[12].wakeup_ports[3].bits.uop.iq_type[1]
connect slots_12.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[12].wakeup_ports[3].bits.uop.iq_type[2]
connect slots_12.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[12].wakeup_ports[3].bits.uop.iq_type[3]
connect slots_12.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[12].wakeup_ports[3].bits.uop.debug_pc
connect slots_12.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[12].wakeup_ports[3].bits.uop.is_rvc
connect slots_12.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[12].wakeup_ports[3].bits.uop.debug_inst
connect slots_12.io.wakeup_ports[3].bits.uop.inst, issue_slots[12].wakeup_ports[3].bits.uop.inst
connect slots_12.io.wakeup_ports[3].valid, issue_slots[12].wakeup_ports[3].valid
connect slots_12.io.squash_grant, issue_slots[12].squash_grant
connect slots_12.io.clear, issue_slots[12].clear
connect slots_12.io.kill, issue_slots[12].kill
connect slots_12.io.brupdate.b2.target_offset, issue_slots[12].brupdate.b2.target_offset
connect slots_12.io.brupdate.b2.jalr_target, issue_slots[12].brupdate.b2.jalr_target
connect slots_12.io.brupdate.b2.pc_sel, issue_slots[12].brupdate.b2.pc_sel
connect slots_12.io.brupdate.b2.cfi_type, issue_slots[12].brupdate.b2.cfi_type
connect slots_12.io.brupdate.b2.taken, issue_slots[12].brupdate.b2.taken
connect slots_12.io.brupdate.b2.mispredict, issue_slots[12].brupdate.b2.mispredict
connect slots_12.io.brupdate.b2.uop.debug_tsrc, issue_slots[12].brupdate.b2.uop.debug_tsrc
connect slots_12.io.brupdate.b2.uop.debug_fsrc, issue_slots[12].brupdate.b2.uop.debug_fsrc
connect slots_12.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[12].brupdate.b2.uop.bp_xcpt_if
connect slots_12.io.brupdate.b2.uop.bp_debug_if, issue_slots[12].brupdate.b2.uop.bp_debug_if
connect slots_12.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[12].brupdate.b2.uop.xcpt_ma_if
connect slots_12.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[12].brupdate.b2.uop.xcpt_ae_if
connect slots_12.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[12].brupdate.b2.uop.xcpt_pf_if
connect slots_12.io.brupdate.b2.uop.fp_typ, issue_slots[12].brupdate.b2.uop.fp_typ
connect slots_12.io.brupdate.b2.uop.fp_rm, issue_slots[12].brupdate.b2.uop.fp_rm
connect slots_12.io.brupdate.b2.uop.fp_val, issue_slots[12].brupdate.b2.uop.fp_val
connect slots_12.io.brupdate.b2.uop.fcn_op, issue_slots[12].brupdate.b2.uop.fcn_op
connect slots_12.io.brupdate.b2.uop.fcn_dw, issue_slots[12].brupdate.b2.uop.fcn_dw
connect slots_12.io.brupdate.b2.uop.frs3_en, issue_slots[12].brupdate.b2.uop.frs3_en
connect slots_12.io.brupdate.b2.uop.lrs2_rtype, issue_slots[12].brupdate.b2.uop.lrs2_rtype
connect slots_12.io.brupdate.b2.uop.lrs1_rtype, issue_slots[12].brupdate.b2.uop.lrs1_rtype
connect slots_12.io.brupdate.b2.uop.dst_rtype, issue_slots[12].brupdate.b2.uop.dst_rtype
connect slots_12.io.brupdate.b2.uop.lrs3, issue_slots[12].brupdate.b2.uop.lrs3
connect slots_12.io.brupdate.b2.uop.lrs2, issue_slots[12].brupdate.b2.uop.lrs2
connect slots_12.io.brupdate.b2.uop.lrs1, issue_slots[12].brupdate.b2.uop.lrs1
connect slots_12.io.brupdate.b2.uop.ldst, issue_slots[12].brupdate.b2.uop.ldst
connect slots_12.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[12].brupdate.b2.uop.ldst_is_rs1
connect slots_12.io.brupdate.b2.uop.csr_cmd, issue_slots[12].brupdate.b2.uop.csr_cmd
connect slots_12.io.brupdate.b2.uop.flush_on_commit, issue_slots[12].brupdate.b2.uop.flush_on_commit
connect slots_12.io.brupdate.b2.uop.is_unique, issue_slots[12].brupdate.b2.uop.is_unique
connect slots_12.io.brupdate.b2.uop.uses_stq, issue_slots[12].brupdate.b2.uop.uses_stq
connect slots_12.io.brupdate.b2.uop.uses_ldq, issue_slots[12].brupdate.b2.uop.uses_ldq
connect slots_12.io.brupdate.b2.uop.mem_signed, issue_slots[12].brupdate.b2.uop.mem_signed
connect slots_12.io.brupdate.b2.uop.mem_size, issue_slots[12].brupdate.b2.uop.mem_size
connect slots_12.io.brupdate.b2.uop.mem_cmd, issue_slots[12].brupdate.b2.uop.mem_cmd
connect slots_12.io.brupdate.b2.uop.exc_cause, issue_slots[12].brupdate.b2.uop.exc_cause
connect slots_12.io.brupdate.b2.uop.exception, issue_slots[12].brupdate.b2.uop.exception
connect slots_12.io.brupdate.b2.uop.stale_pdst, issue_slots[12].brupdate.b2.uop.stale_pdst
connect slots_12.io.brupdate.b2.uop.ppred_busy, issue_slots[12].brupdate.b2.uop.ppred_busy
connect slots_12.io.brupdate.b2.uop.prs3_busy, issue_slots[12].brupdate.b2.uop.prs3_busy
connect slots_12.io.brupdate.b2.uop.prs2_busy, issue_slots[12].brupdate.b2.uop.prs2_busy
connect slots_12.io.brupdate.b2.uop.prs1_busy, issue_slots[12].brupdate.b2.uop.prs1_busy
connect slots_12.io.brupdate.b2.uop.ppred, issue_slots[12].brupdate.b2.uop.ppred
connect slots_12.io.brupdate.b2.uop.prs3, issue_slots[12].brupdate.b2.uop.prs3
connect slots_12.io.brupdate.b2.uop.prs2, issue_slots[12].brupdate.b2.uop.prs2
connect slots_12.io.brupdate.b2.uop.prs1, issue_slots[12].brupdate.b2.uop.prs1
connect slots_12.io.brupdate.b2.uop.pdst, issue_slots[12].brupdate.b2.uop.pdst
connect slots_12.io.brupdate.b2.uop.rxq_idx, issue_slots[12].brupdate.b2.uop.rxq_idx
connect slots_12.io.brupdate.b2.uop.stq_idx, issue_slots[12].brupdate.b2.uop.stq_idx
connect slots_12.io.brupdate.b2.uop.ldq_idx, issue_slots[12].brupdate.b2.uop.ldq_idx
connect slots_12.io.brupdate.b2.uop.rob_idx, issue_slots[12].brupdate.b2.uop.rob_idx
connect slots_12.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[12].brupdate.b2.uop.fp_ctrl.vec
connect slots_12.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[12].brupdate.b2.uop.fp_ctrl.wflags
connect slots_12.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[12].brupdate.b2.uop.fp_ctrl.sqrt
connect slots_12.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[12].brupdate.b2.uop.fp_ctrl.div
connect slots_12.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[12].brupdate.b2.uop.fp_ctrl.fma
connect slots_12.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[12].brupdate.b2.uop.fp_ctrl.fastpipe
connect slots_12.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[12].brupdate.b2.uop.fp_ctrl.toint
connect slots_12.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[12].brupdate.b2.uop.fp_ctrl.fromint
connect slots_12.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[12].brupdate.b2.uop.fp_ctrl.typeTagOut
connect slots_12.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[12].brupdate.b2.uop.fp_ctrl.typeTagIn
connect slots_12.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[12].brupdate.b2.uop.fp_ctrl.swap23
connect slots_12.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[12].brupdate.b2.uop.fp_ctrl.swap12
connect slots_12.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[12].brupdate.b2.uop.fp_ctrl.ren3
connect slots_12.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[12].brupdate.b2.uop.fp_ctrl.ren2
connect slots_12.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[12].brupdate.b2.uop.fp_ctrl.ren1
connect slots_12.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[12].brupdate.b2.uop.fp_ctrl.wen
connect slots_12.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[12].brupdate.b2.uop.fp_ctrl.ldst
connect slots_12.io.brupdate.b2.uop.op2_sel, issue_slots[12].brupdate.b2.uop.op2_sel
connect slots_12.io.brupdate.b2.uop.op1_sel, issue_slots[12].brupdate.b2.uop.op1_sel
connect slots_12.io.brupdate.b2.uop.imm_packed, issue_slots[12].brupdate.b2.uop.imm_packed
connect slots_12.io.brupdate.b2.uop.pimm, issue_slots[12].brupdate.b2.uop.pimm
connect slots_12.io.brupdate.b2.uop.imm_sel, issue_slots[12].brupdate.b2.uop.imm_sel
connect slots_12.io.brupdate.b2.uop.imm_rename, issue_slots[12].brupdate.b2.uop.imm_rename
connect slots_12.io.brupdate.b2.uop.taken, issue_slots[12].brupdate.b2.uop.taken
connect slots_12.io.brupdate.b2.uop.pc_lob, issue_slots[12].brupdate.b2.uop.pc_lob
connect slots_12.io.brupdate.b2.uop.edge_inst, issue_slots[12].brupdate.b2.uop.edge_inst
connect slots_12.io.brupdate.b2.uop.ftq_idx, issue_slots[12].brupdate.b2.uop.ftq_idx
connect slots_12.io.brupdate.b2.uop.is_mov, issue_slots[12].brupdate.b2.uop.is_mov
connect slots_12.io.brupdate.b2.uop.is_rocc, issue_slots[12].brupdate.b2.uop.is_rocc
connect slots_12.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[12].brupdate.b2.uop.is_sys_pc2epc
connect slots_12.io.brupdate.b2.uop.is_eret, issue_slots[12].brupdate.b2.uop.is_eret
connect slots_12.io.brupdate.b2.uop.is_amo, issue_slots[12].brupdate.b2.uop.is_amo
connect slots_12.io.brupdate.b2.uop.is_sfence, issue_slots[12].brupdate.b2.uop.is_sfence
connect slots_12.io.brupdate.b2.uop.is_fencei, issue_slots[12].brupdate.b2.uop.is_fencei
connect slots_12.io.brupdate.b2.uop.is_fence, issue_slots[12].brupdate.b2.uop.is_fence
connect slots_12.io.brupdate.b2.uop.is_sfb, issue_slots[12].brupdate.b2.uop.is_sfb
connect slots_12.io.brupdate.b2.uop.br_type, issue_slots[12].brupdate.b2.uop.br_type
connect slots_12.io.brupdate.b2.uop.br_tag, issue_slots[12].brupdate.b2.uop.br_tag
connect slots_12.io.brupdate.b2.uop.br_mask, issue_slots[12].brupdate.b2.uop.br_mask
connect slots_12.io.brupdate.b2.uop.dis_col_sel, issue_slots[12].brupdate.b2.uop.dis_col_sel
connect slots_12.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[12].brupdate.b2.uop.iw_p3_bypass_hint
connect slots_12.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[12].brupdate.b2.uop.iw_p2_bypass_hint
connect slots_12.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[12].brupdate.b2.uop.iw_p1_bypass_hint
connect slots_12.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[12].brupdate.b2.uop.iw_p2_speculative_child
connect slots_12.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[12].brupdate.b2.uop.iw_p1_speculative_child
connect slots_12.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[12].brupdate.b2.uop.iw_issued_partial_dgen
connect slots_12.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[12].brupdate.b2.uop.iw_issued_partial_agen
connect slots_12.io.brupdate.b2.uop.iw_issued, issue_slots[12].brupdate.b2.uop.iw_issued
connect slots_12.io.brupdate.b2.uop.fu_code[0], issue_slots[12].brupdate.b2.uop.fu_code[0]
connect slots_12.io.brupdate.b2.uop.fu_code[1], issue_slots[12].brupdate.b2.uop.fu_code[1]
connect slots_12.io.brupdate.b2.uop.fu_code[2], issue_slots[12].brupdate.b2.uop.fu_code[2]
connect slots_12.io.brupdate.b2.uop.fu_code[3], issue_slots[12].brupdate.b2.uop.fu_code[3]
connect slots_12.io.brupdate.b2.uop.fu_code[4], issue_slots[12].brupdate.b2.uop.fu_code[4]
connect slots_12.io.brupdate.b2.uop.fu_code[5], issue_slots[12].brupdate.b2.uop.fu_code[5]
connect slots_12.io.brupdate.b2.uop.fu_code[6], issue_slots[12].brupdate.b2.uop.fu_code[6]
connect slots_12.io.brupdate.b2.uop.fu_code[7], issue_slots[12].brupdate.b2.uop.fu_code[7]
connect slots_12.io.brupdate.b2.uop.fu_code[8], issue_slots[12].brupdate.b2.uop.fu_code[8]
connect slots_12.io.brupdate.b2.uop.fu_code[9], issue_slots[12].brupdate.b2.uop.fu_code[9]
connect slots_12.io.brupdate.b2.uop.iq_type[0], issue_slots[12].brupdate.b2.uop.iq_type[0]
connect slots_12.io.brupdate.b2.uop.iq_type[1], issue_slots[12].brupdate.b2.uop.iq_type[1]
connect slots_12.io.brupdate.b2.uop.iq_type[2], issue_slots[12].brupdate.b2.uop.iq_type[2]
connect slots_12.io.brupdate.b2.uop.iq_type[3], issue_slots[12].brupdate.b2.uop.iq_type[3]
connect slots_12.io.brupdate.b2.uop.debug_pc, issue_slots[12].brupdate.b2.uop.debug_pc
connect slots_12.io.brupdate.b2.uop.is_rvc, issue_slots[12].brupdate.b2.uop.is_rvc
connect slots_12.io.brupdate.b2.uop.debug_inst, issue_slots[12].brupdate.b2.uop.debug_inst
connect slots_12.io.brupdate.b2.uop.inst, issue_slots[12].brupdate.b2.uop.inst
connect slots_12.io.brupdate.b1.mispredict_mask, issue_slots[12].brupdate.b1.mispredict_mask
connect slots_12.io.brupdate.b1.resolve_mask, issue_slots[12].brupdate.b1.resolve_mask
connect issue_slots[12].out_uop.debug_tsrc, slots_12.io.out_uop.debug_tsrc
connect issue_slots[12].out_uop.debug_fsrc, slots_12.io.out_uop.debug_fsrc
connect issue_slots[12].out_uop.bp_xcpt_if, slots_12.io.out_uop.bp_xcpt_if
connect issue_slots[12].out_uop.bp_debug_if, slots_12.io.out_uop.bp_debug_if
connect issue_slots[12].out_uop.xcpt_ma_if, slots_12.io.out_uop.xcpt_ma_if
connect issue_slots[12].out_uop.xcpt_ae_if, slots_12.io.out_uop.xcpt_ae_if
connect issue_slots[12].out_uop.xcpt_pf_if, slots_12.io.out_uop.xcpt_pf_if
connect issue_slots[12].out_uop.fp_typ, slots_12.io.out_uop.fp_typ
connect issue_slots[12].out_uop.fp_rm, slots_12.io.out_uop.fp_rm
connect issue_slots[12].out_uop.fp_val, slots_12.io.out_uop.fp_val
connect issue_slots[12].out_uop.fcn_op, slots_12.io.out_uop.fcn_op
connect issue_slots[12].out_uop.fcn_dw, slots_12.io.out_uop.fcn_dw
connect issue_slots[12].out_uop.frs3_en, slots_12.io.out_uop.frs3_en
connect issue_slots[12].out_uop.lrs2_rtype, slots_12.io.out_uop.lrs2_rtype
connect issue_slots[12].out_uop.lrs1_rtype, slots_12.io.out_uop.lrs1_rtype
connect issue_slots[12].out_uop.dst_rtype, slots_12.io.out_uop.dst_rtype
connect issue_slots[12].out_uop.lrs3, slots_12.io.out_uop.lrs3
connect issue_slots[12].out_uop.lrs2, slots_12.io.out_uop.lrs2
connect issue_slots[12].out_uop.lrs1, slots_12.io.out_uop.lrs1
connect issue_slots[12].out_uop.ldst, slots_12.io.out_uop.ldst
connect issue_slots[12].out_uop.ldst_is_rs1, slots_12.io.out_uop.ldst_is_rs1
connect issue_slots[12].out_uop.csr_cmd, slots_12.io.out_uop.csr_cmd
connect issue_slots[12].out_uop.flush_on_commit, slots_12.io.out_uop.flush_on_commit
connect issue_slots[12].out_uop.is_unique, slots_12.io.out_uop.is_unique
connect issue_slots[12].out_uop.uses_stq, slots_12.io.out_uop.uses_stq
connect issue_slots[12].out_uop.uses_ldq, slots_12.io.out_uop.uses_ldq
connect issue_slots[12].out_uop.mem_signed, slots_12.io.out_uop.mem_signed
connect issue_slots[12].out_uop.mem_size, slots_12.io.out_uop.mem_size
connect issue_slots[12].out_uop.mem_cmd, slots_12.io.out_uop.mem_cmd
connect issue_slots[12].out_uop.exc_cause, slots_12.io.out_uop.exc_cause
connect issue_slots[12].out_uop.exception, slots_12.io.out_uop.exception
connect issue_slots[12].out_uop.stale_pdst, slots_12.io.out_uop.stale_pdst
connect issue_slots[12].out_uop.ppred_busy, slots_12.io.out_uop.ppred_busy
connect issue_slots[12].out_uop.prs3_busy, slots_12.io.out_uop.prs3_busy
connect issue_slots[12].out_uop.prs2_busy, slots_12.io.out_uop.prs2_busy
connect issue_slots[12].out_uop.prs1_busy, slots_12.io.out_uop.prs1_busy
connect issue_slots[12].out_uop.ppred, slots_12.io.out_uop.ppred
connect issue_slots[12].out_uop.prs3, slots_12.io.out_uop.prs3
connect issue_slots[12].out_uop.prs2, slots_12.io.out_uop.prs2
connect issue_slots[12].out_uop.prs1, slots_12.io.out_uop.prs1
connect issue_slots[12].out_uop.pdst, slots_12.io.out_uop.pdst
connect issue_slots[12].out_uop.rxq_idx, slots_12.io.out_uop.rxq_idx
connect issue_slots[12].out_uop.stq_idx, slots_12.io.out_uop.stq_idx
connect issue_slots[12].out_uop.ldq_idx, slots_12.io.out_uop.ldq_idx
connect issue_slots[12].out_uop.rob_idx, slots_12.io.out_uop.rob_idx
connect issue_slots[12].out_uop.fp_ctrl.vec, slots_12.io.out_uop.fp_ctrl.vec
connect issue_slots[12].out_uop.fp_ctrl.wflags, slots_12.io.out_uop.fp_ctrl.wflags
connect issue_slots[12].out_uop.fp_ctrl.sqrt, slots_12.io.out_uop.fp_ctrl.sqrt
connect issue_slots[12].out_uop.fp_ctrl.div, slots_12.io.out_uop.fp_ctrl.div
connect issue_slots[12].out_uop.fp_ctrl.fma, slots_12.io.out_uop.fp_ctrl.fma
connect issue_slots[12].out_uop.fp_ctrl.fastpipe, slots_12.io.out_uop.fp_ctrl.fastpipe
connect issue_slots[12].out_uop.fp_ctrl.toint, slots_12.io.out_uop.fp_ctrl.toint
connect issue_slots[12].out_uop.fp_ctrl.fromint, slots_12.io.out_uop.fp_ctrl.fromint
connect issue_slots[12].out_uop.fp_ctrl.typeTagOut, slots_12.io.out_uop.fp_ctrl.typeTagOut
connect issue_slots[12].out_uop.fp_ctrl.typeTagIn, slots_12.io.out_uop.fp_ctrl.typeTagIn
connect issue_slots[12].out_uop.fp_ctrl.swap23, slots_12.io.out_uop.fp_ctrl.swap23
connect issue_slots[12].out_uop.fp_ctrl.swap12, slots_12.io.out_uop.fp_ctrl.swap12
connect issue_slots[12].out_uop.fp_ctrl.ren3, slots_12.io.out_uop.fp_ctrl.ren3
connect issue_slots[12].out_uop.fp_ctrl.ren2, slots_12.io.out_uop.fp_ctrl.ren2
connect issue_slots[12].out_uop.fp_ctrl.ren1, slots_12.io.out_uop.fp_ctrl.ren1
connect issue_slots[12].out_uop.fp_ctrl.wen, slots_12.io.out_uop.fp_ctrl.wen
connect issue_slots[12].out_uop.fp_ctrl.ldst, slots_12.io.out_uop.fp_ctrl.ldst
connect issue_slots[12].out_uop.op2_sel, slots_12.io.out_uop.op2_sel
connect issue_slots[12].out_uop.op1_sel, slots_12.io.out_uop.op1_sel
connect issue_slots[12].out_uop.imm_packed, slots_12.io.out_uop.imm_packed
connect issue_slots[12].out_uop.pimm, slots_12.io.out_uop.pimm
connect issue_slots[12].out_uop.imm_sel, slots_12.io.out_uop.imm_sel
connect issue_slots[12].out_uop.imm_rename, slots_12.io.out_uop.imm_rename
connect issue_slots[12].out_uop.taken, slots_12.io.out_uop.taken
connect issue_slots[12].out_uop.pc_lob, slots_12.io.out_uop.pc_lob
connect issue_slots[12].out_uop.edge_inst, slots_12.io.out_uop.edge_inst
connect issue_slots[12].out_uop.ftq_idx, slots_12.io.out_uop.ftq_idx
connect issue_slots[12].out_uop.is_mov, slots_12.io.out_uop.is_mov
connect issue_slots[12].out_uop.is_rocc, slots_12.io.out_uop.is_rocc
connect issue_slots[12].out_uop.is_sys_pc2epc, slots_12.io.out_uop.is_sys_pc2epc
connect issue_slots[12].out_uop.is_eret, slots_12.io.out_uop.is_eret
connect issue_slots[12].out_uop.is_amo, slots_12.io.out_uop.is_amo
connect issue_slots[12].out_uop.is_sfence, slots_12.io.out_uop.is_sfence
connect issue_slots[12].out_uop.is_fencei, slots_12.io.out_uop.is_fencei
connect issue_slots[12].out_uop.is_fence, slots_12.io.out_uop.is_fence
connect issue_slots[12].out_uop.is_sfb, slots_12.io.out_uop.is_sfb
connect issue_slots[12].out_uop.br_type, slots_12.io.out_uop.br_type
connect issue_slots[12].out_uop.br_tag, slots_12.io.out_uop.br_tag
connect issue_slots[12].out_uop.br_mask, slots_12.io.out_uop.br_mask
connect issue_slots[12].out_uop.dis_col_sel, slots_12.io.out_uop.dis_col_sel
connect issue_slots[12].out_uop.iw_p3_bypass_hint, slots_12.io.out_uop.iw_p3_bypass_hint
connect issue_slots[12].out_uop.iw_p2_bypass_hint, slots_12.io.out_uop.iw_p2_bypass_hint
connect issue_slots[12].out_uop.iw_p1_bypass_hint, slots_12.io.out_uop.iw_p1_bypass_hint
connect issue_slots[12].out_uop.iw_p2_speculative_child, slots_12.io.out_uop.iw_p2_speculative_child
connect issue_slots[12].out_uop.iw_p1_speculative_child, slots_12.io.out_uop.iw_p1_speculative_child
connect issue_slots[12].out_uop.iw_issued_partial_dgen, slots_12.io.out_uop.iw_issued_partial_dgen
connect issue_slots[12].out_uop.iw_issued_partial_agen, slots_12.io.out_uop.iw_issued_partial_agen
connect issue_slots[12].out_uop.iw_issued, slots_12.io.out_uop.iw_issued
connect issue_slots[12].out_uop.fu_code[0], slots_12.io.out_uop.fu_code[0]
connect issue_slots[12].out_uop.fu_code[1], slots_12.io.out_uop.fu_code[1]
connect issue_slots[12].out_uop.fu_code[2], slots_12.io.out_uop.fu_code[2]
connect issue_slots[12].out_uop.fu_code[3], slots_12.io.out_uop.fu_code[3]
connect issue_slots[12].out_uop.fu_code[4], slots_12.io.out_uop.fu_code[4]
connect issue_slots[12].out_uop.fu_code[5], slots_12.io.out_uop.fu_code[5]
connect issue_slots[12].out_uop.fu_code[6], slots_12.io.out_uop.fu_code[6]
connect issue_slots[12].out_uop.fu_code[7], slots_12.io.out_uop.fu_code[7]
connect issue_slots[12].out_uop.fu_code[8], slots_12.io.out_uop.fu_code[8]
connect issue_slots[12].out_uop.fu_code[9], slots_12.io.out_uop.fu_code[9]
connect issue_slots[12].out_uop.iq_type[0], slots_12.io.out_uop.iq_type[0]
connect issue_slots[12].out_uop.iq_type[1], slots_12.io.out_uop.iq_type[1]
connect issue_slots[12].out_uop.iq_type[2], slots_12.io.out_uop.iq_type[2]
connect issue_slots[12].out_uop.iq_type[3], slots_12.io.out_uop.iq_type[3]
connect issue_slots[12].out_uop.debug_pc, slots_12.io.out_uop.debug_pc
connect issue_slots[12].out_uop.is_rvc, slots_12.io.out_uop.is_rvc
connect issue_slots[12].out_uop.debug_inst, slots_12.io.out_uop.debug_inst
connect issue_slots[12].out_uop.inst, slots_12.io.out_uop.inst
connect slots_12.io.in_uop.bits.debug_tsrc, issue_slots[12].in_uop.bits.debug_tsrc
connect slots_12.io.in_uop.bits.debug_fsrc, issue_slots[12].in_uop.bits.debug_fsrc
connect slots_12.io.in_uop.bits.bp_xcpt_if, issue_slots[12].in_uop.bits.bp_xcpt_if
connect slots_12.io.in_uop.bits.bp_debug_if, issue_slots[12].in_uop.bits.bp_debug_if
connect slots_12.io.in_uop.bits.xcpt_ma_if, issue_slots[12].in_uop.bits.xcpt_ma_if
connect slots_12.io.in_uop.bits.xcpt_ae_if, issue_slots[12].in_uop.bits.xcpt_ae_if
connect slots_12.io.in_uop.bits.xcpt_pf_if, issue_slots[12].in_uop.bits.xcpt_pf_if
connect slots_12.io.in_uop.bits.fp_typ, issue_slots[12].in_uop.bits.fp_typ
connect slots_12.io.in_uop.bits.fp_rm, issue_slots[12].in_uop.bits.fp_rm
connect slots_12.io.in_uop.bits.fp_val, issue_slots[12].in_uop.bits.fp_val
connect slots_12.io.in_uop.bits.fcn_op, issue_slots[12].in_uop.bits.fcn_op
connect slots_12.io.in_uop.bits.fcn_dw, issue_slots[12].in_uop.bits.fcn_dw
connect slots_12.io.in_uop.bits.frs3_en, issue_slots[12].in_uop.bits.frs3_en
connect slots_12.io.in_uop.bits.lrs2_rtype, issue_slots[12].in_uop.bits.lrs2_rtype
connect slots_12.io.in_uop.bits.lrs1_rtype, issue_slots[12].in_uop.bits.lrs1_rtype
connect slots_12.io.in_uop.bits.dst_rtype, issue_slots[12].in_uop.bits.dst_rtype
connect slots_12.io.in_uop.bits.lrs3, issue_slots[12].in_uop.bits.lrs3
connect slots_12.io.in_uop.bits.lrs2, issue_slots[12].in_uop.bits.lrs2
connect slots_12.io.in_uop.bits.lrs1, issue_slots[12].in_uop.bits.lrs1
connect slots_12.io.in_uop.bits.ldst, issue_slots[12].in_uop.bits.ldst
connect slots_12.io.in_uop.bits.ldst_is_rs1, issue_slots[12].in_uop.bits.ldst_is_rs1
connect slots_12.io.in_uop.bits.csr_cmd, issue_slots[12].in_uop.bits.csr_cmd
connect slots_12.io.in_uop.bits.flush_on_commit, issue_slots[12].in_uop.bits.flush_on_commit
connect slots_12.io.in_uop.bits.is_unique, issue_slots[12].in_uop.bits.is_unique
connect slots_12.io.in_uop.bits.uses_stq, issue_slots[12].in_uop.bits.uses_stq
connect slots_12.io.in_uop.bits.uses_ldq, issue_slots[12].in_uop.bits.uses_ldq
connect slots_12.io.in_uop.bits.mem_signed, issue_slots[12].in_uop.bits.mem_signed
connect slots_12.io.in_uop.bits.mem_size, issue_slots[12].in_uop.bits.mem_size
connect slots_12.io.in_uop.bits.mem_cmd, issue_slots[12].in_uop.bits.mem_cmd
connect slots_12.io.in_uop.bits.exc_cause, issue_slots[12].in_uop.bits.exc_cause
connect slots_12.io.in_uop.bits.exception, issue_slots[12].in_uop.bits.exception
connect slots_12.io.in_uop.bits.stale_pdst, issue_slots[12].in_uop.bits.stale_pdst
connect slots_12.io.in_uop.bits.ppred_busy, issue_slots[12].in_uop.bits.ppred_busy
connect slots_12.io.in_uop.bits.prs3_busy, issue_slots[12].in_uop.bits.prs3_busy
connect slots_12.io.in_uop.bits.prs2_busy, issue_slots[12].in_uop.bits.prs2_busy
connect slots_12.io.in_uop.bits.prs1_busy, issue_slots[12].in_uop.bits.prs1_busy
connect slots_12.io.in_uop.bits.ppred, issue_slots[12].in_uop.bits.ppred
connect slots_12.io.in_uop.bits.prs3, issue_slots[12].in_uop.bits.prs3
connect slots_12.io.in_uop.bits.prs2, issue_slots[12].in_uop.bits.prs2
connect slots_12.io.in_uop.bits.prs1, issue_slots[12].in_uop.bits.prs1
connect slots_12.io.in_uop.bits.pdst, issue_slots[12].in_uop.bits.pdst
connect slots_12.io.in_uop.bits.rxq_idx, issue_slots[12].in_uop.bits.rxq_idx
connect slots_12.io.in_uop.bits.stq_idx, issue_slots[12].in_uop.bits.stq_idx
connect slots_12.io.in_uop.bits.ldq_idx, issue_slots[12].in_uop.bits.ldq_idx
connect slots_12.io.in_uop.bits.rob_idx, issue_slots[12].in_uop.bits.rob_idx
connect slots_12.io.in_uop.bits.fp_ctrl.vec, issue_slots[12].in_uop.bits.fp_ctrl.vec
connect slots_12.io.in_uop.bits.fp_ctrl.wflags, issue_slots[12].in_uop.bits.fp_ctrl.wflags
connect slots_12.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[12].in_uop.bits.fp_ctrl.sqrt
connect slots_12.io.in_uop.bits.fp_ctrl.div, issue_slots[12].in_uop.bits.fp_ctrl.div
connect slots_12.io.in_uop.bits.fp_ctrl.fma, issue_slots[12].in_uop.bits.fp_ctrl.fma
connect slots_12.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[12].in_uop.bits.fp_ctrl.fastpipe
connect slots_12.io.in_uop.bits.fp_ctrl.toint, issue_slots[12].in_uop.bits.fp_ctrl.toint
connect slots_12.io.in_uop.bits.fp_ctrl.fromint, issue_slots[12].in_uop.bits.fp_ctrl.fromint
connect slots_12.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[12].in_uop.bits.fp_ctrl.typeTagOut
connect slots_12.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[12].in_uop.bits.fp_ctrl.typeTagIn
connect slots_12.io.in_uop.bits.fp_ctrl.swap23, issue_slots[12].in_uop.bits.fp_ctrl.swap23
connect slots_12.io.in_uop.bits.fp_ctrl.swap12, issue_slots[12].in_uop.bits.fp_ctrl.swap12
connect slots_12.io.in_uop.bits.fp_ctrl.ren3, issue_slots[12].in_uop.bits.fp_ctrl.ren3
connect slots_12.io.in_uop.bits.fp_ctrl.ren2, issue_slots[12].in_uop.bits.fp_ctrl.ren2
connect slots_12.io.in_uop.bits.fp_ctrl.ren1, issue_slots[12].in_uop.bits.fp_ctrl.ren1
connect slots_12.io.in_uop.bits.fp_ctrl.wen, issue_slots[12].in_uop.bits.fp_ctrl.wen
connect slots_12.io.in_uop.bits.fp_ctrl.ldst, issue_slots[12].in_uop.bits.fp_ctrl.ldst
connect slots_12.io.in_uop.bits.op2_sel, issue_slots[12].in_uop.bits.op2_sel
connect slots_12.io.in_uop.bits.op1_sel, issue_slots[12].in_uop.bits.op1_sel
connect slots_12.io.in_uop.bits.imm_packed, issue_slots[12].in_uop.bits.imm_packed
connect slots_12.io.in_uop.bits.pimm, issue_slots[12].in_uop.bits.pimm
connect slots_12.io.in_uop.bits.imm_sel, issue_slots[12].in_uop.bits.imm_sel
connect slots_12.io.in_uop.bits.imm_rename, issue_slots[12].in_uop.bits.imm_rename
connect slots_12.io.in_uop.bits.taken, issue_slots[12].in_uop.bits.taken
connect slots_12.io.in_uop.bits.pc_lob, issue_slots[12].in_uop.bits.pc_lob
connect slots_12.io.in_uop.bits.edge_inst, issue_slots[12].in_uop.bits.edge_inst
connect slots_12.io.in_uop.bits.ftq_idx, issue_slots[12].in_uop.bits.ftq_idx
connect slots_12.io.in_uop.bits.is_mov, issue_slots[12].in_uop.bits.is_mov
connect slots_12.io.in_uop.bits.is_rocc, issue_slots[12].in_uop.bits.is_rocc
connect slots_12.io.in_uop.bits.is_sys_pc2epc, issue_slots[12].in_uop.bits.is_sys_pc2epc
connect slots_12.io.in_uop.bits.is_eret, issue_slots[12].in_uop.bits.is_eret
connect slots_12.io.in_uop.bits.is_amo, issue_slots[12].in_uop.bits.is_amo
connect slots_12.io.in_uop.bits.is_sfence, issue_slots[12].in_uop.bits.is_sfence
connect slots_12.io.in_uop.bits.is_fencei, issue_slots[12].in_uop.bits.is_fencei
connect slots_12.io.in_uop.bits.is_fence, issue_slots[12].in_uop.bits.is_fence
connect slots_12.io.in_uop.bits.is_sfb, issue_slots[12].in_uop.bits.is_sfb
connect slots_12.io.in_uop.bits.br_type, issue_slots[12].in_uop.bits.br_type
connect slots_12.io.in_uop.bits.br_tag, issue_slots[12].in_uop.bits.br_tag
connect slots_12.io.in_uop.bits.br_mask, issue_slots[12].in_uop.bits.br_mask
connect slots_12.io.in_uop.bits.dis_col_sel, issue_slots[12].in_uop.bits.dis_col_sel
connect slots_12.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[12].in_uop.bits.iw_p3_bypass_hint
connect slots_12.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[12].in_uop.bits.iw_p2_bypass_hint
connect slots_12.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[12].in_uop.bits.iw_p1_bypass_hint
connect slots_12.io.in_uop.bits.iw_p2_speculative_child, issue_slots[12].in_uop.bits.iw_p2_speculative_child
connect slots_12.io.in_uop.bits.iw_p1_speculative_child, issue_slots[12].in_uop.bits.iw_p1_speculative_child
connect slots_12.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[12].in_uop.bits.iw_issued_partial_dgen
connect slots_12.io.in_uop.bits.iw_issued_partial_agen, issue_slots[12].in_uop.bits.iw_issued_partial_agen
connect slots_12.io.in_uop.bits.iw_issued, issue_slots[12].in_uop.bits.iw_issued
connect slots_12.io.in_uop.bits.fu_code[0], issue_slots[12].in_uop.bits.fu_code[0]
connect slots_12.io.in_uop.bits.fu_code[1], issue_slots[12].in_uop.bits.fu_code[1]
connect slots_12.io.in_uop.bits.fu_code[2], issue_slots[12].in_uop.bits.fu_code[2]
connect slots_12.io.in_uop.bits.fu_code[3], issue_slots[12].in_uop.bits.fu_code[3]
connect slots_12.io.in_uop.bits.fu_code[4], issue_slots[12].in_uop.bits.fu_code[4]
connect slots_12.io.in_uop.bits.fu_code[5], issue_slots[12].in_uop.bits.fu_code[5]
connect slots_12.io.in_uop.bits.fu_code[6], issue_slots[12].in_uop.bits.fu_code[6]
connect slots_12.io.in_uop.bits.fu_code[7], issue_slots[12].in_uop.bits.fu_code[7]
connect slots_12.io.in_uop.bits.fu_code[8], issue_slots[12].in_uop.bits.fu_code[8]
connect slots_12.io.in_uop.bits.fu_code[9], issue_slots[12].in_uop.bits.fu_code[9]
connect slots_12.io.in_uop.bits.iq_type[0], issue_slots[12].in_uop.bits.iq_type[0]
connect slots_12.io.in_uop.bits.iq_type[1], issue_slots[12].in_uop.bits.iq_type[1]
connect slots_12.io.in_uop.bits.iq_type[2], issue_slots[12].in_uop.bits.iq_type[2]
connect slots_12.io.in_uop.bits.iq_type[3], issue_slots[12].in_uop.bits.iq_type[3]
connect slots_12.io.in_uop.bits.debug_pc, issue_slots[12].in_uop.bits.debug_pc
connect slots_12.io.in_uop.bits.is_rvc, issue_slots[12].in_uop.bits.is_rvc
connect slots_12.io.in_uop.bits.debug_inst, issue_slots[12].in_uop.bits.debug_inst
connect slots_12.io.in_uop.bits.inst, issue_slots[12].in_uop.bits.inst
connect slots_12.io.in_uop.valid, issue_slots[12].in_uop.valid
connect issue_slots[12].iss_uop.debug_tsrc, slots_12.io.iss_uop.debug_tsrc
connect issue_slots[12].iss_uop.debug_fsrc, slots_12.io.iss_uop.debug_fsrc
connect issue_slots[12].iss_uop.bp_xcpt_if, slots_12.io.iss_uop.bp_xcpt_if
connect issue_slots[12].iss_uop.bp_debug_if, slots_12.io.iss_uop.bp_debug_if
connect issue_slots[12].iss_uop.xcpt_ma_if, slots_12.io.iss_uop.xcpt_ma_if
connect issue_slots[12].iss_uop.xcpt_ae_if, slots_12.io.iss_uop.xcpt_ae_if
connect issue_slots[12].iss_uop.xcpt_pf_if, slots_12.io.iss_uop.xcpt_pf_if
connect issue_slots[12].iss_uop.fp_typ, slots_12.io.iss_uop.fp_typ
connect issue_slots[12].iss_uop.fp_rm, slots_12.io.iss_uop.fp_rm
connect issue_slots[12].iss_uop.fp_val, slots_12.io.iss_uop.fp_val
connect issue_slots[12].iss_uop.fcn_op, slots_12.io.iss_uop.fcn_op
connect issue_slots[12].iss_uop.fcn_dw, slots_12.io.iss_uop.fcn_dw
connect issue_slots[12].iss_uop.frs3_en, slots_12.io.iss_uop.frs3_en
connect issue_slots[12].iss_uop.lrs2_rtype, slots_12.io.iss_uop.lrs2_rtype
connect issue_slots[12].iss_uop.lrs1_rtype, slots_12.io.iss_uop.lrs1_rtype
connect issue_slots[12].iss_uop.dst_rtype, slots_12.io.iss_uop.dst_rtype
connect issue_slots[12].iss_uop.lrs3, slots_12.io.iss_uop.lrs3
connect issue_slots[12].iss_uop.lrs2, slots_12.io.iss_uop.lrs2
connect issue_slots[12].iss_uop.lrs1, slots_12.io.iss_uop.lrs1
connect issue_slots[12].iss_uop.ldst, slots_12.io.iss_uop.ldst
connect issue_slots[12].iss_uop.ldst_is_rs1, slots_12.io.iss_uop.ldst_is_rs1
connect issue_slots[12].iss_uop.csr_cmd, slots_12.io.iss_uop.csr_cmd
connect issue_slots[12].iss_uop.flush_on_commit, slots_12.io.iss_uop.flush_on_commit
connect issue_slots[12].iss_uop.is_unique, slots_12.io.iss_uop.is_unique
connect issue_slots[12].iss_uop.uses_stq, slots_12.io.iss_uop.uses_stq
connect issue_slots[12].iss_uop.uses_ldq, slots_12.io.iss_uop.uses_ldq
connect issue_slots[12].iss_uop.mem_signed, slots_12.io.iss_uop.mem_signed
connect issue_slots[12].iss_uop.mem_size, slots_12.io.iss_uop.mem_size
connect issue_slots[12].iss_uop.mem_cmd, slots_12.io.iss_uop.mem_cmd
connect issue_slots[12].iss_uop.exc_cause, slots_12.io.iss_uop.exc_cause
connect issue_slots[12].iss_uop.exception, slots_12.io.iss_uop.exception
connect issue_slots[12].iss_uop.stale_pdst, slots_12.io.iss_uop.stale_pdst
connect issue_slots[12].iss_uop.ppred_busy, slots_12.io.iss_uop.ppred_busy
connect issue_slots[12].iss_uop.prs3_busy, slots_12.io.iss_uop.prs3_busy
connect issue_slots[12].iss_uop.prs2_busy, slots_12.io.iss_uop.prs2_busy
connect issue_slots[12].iss_uop.prs1_busy, slots_12.io.iss_uop.prs1_busy
connect issue_slots[12].iss_uop.ppred, slots_12.io.iss_uop.ppred
connect issue_slots[12].iss_uop.prs3, slots_12.io.iss_uop.prs3
connect issue_slots[12].iss_uop.prs2, slots_12.io.iss_uop.prs2
connect issue_slots[12].iss_uop.prs1, slots_12.io.iss_uop.prs1
connect issue_slots[12].iss_uop.pdst, slots_12.io.iss_uop.pdst
connect issue_slots[12].iss_uop.rxq_idx, slots_12.io.iss_uop.rxq_idx
connect issue_slots[12].iss_uop.stq_idx, slots_12.io.iss_uop.stq_idx
connect issue_slots[12].iss_uop.ldq_idx, slots_12.io.iss_uop.ldq_idx
connect issue_slots[12].iss_uop.rob_idx, slots_12.io.iss_uop.rob_idx
connect issue_slots[12].iss_uop.fp_ctrl.vec, slots_12.io.iss_uop.fp_ctrl.vec
connect issue_slots[12].iss_uop.fp_ctrl.wflags, slots_12.io.iss_uop.fp_ctrl.wflags
connect issue_slots[12].iss_uop.fp_ctrl.sqrt, slots_12.io.iss_uop.fp_ctrl.sqrt
connect issue_slots[12].iss_uop.fp_ctrl.div, slots_12.io.iss_uop.fp_ctrl.div
connect issue_slots[12].iss_uop.fp_ctrl.fma, slots_12.io.iss_uop.fp_ctrl.fma
connect issue_slots[12].iss_uop.fp_ctrl.fastpipe, slots_12.io.iss_uop.fp_ctrl.fastpipe
connect issue_slots[12].iss_uop.fp_ctrl.toint, slots_12.io.iss_uop.fp_ctrl.toint
connect issue_slots[12].iss_uop.fp_ctrl.fromint, slots_12.io.iss_uop.fp_ctrl.fromint
connect issue_slots[12].iss_uop.fp_ctrl.typeTagOut, slots_12.io.iss_uop.fp_ctrl.typeTagOut
connect issue_slots[12].iss_uop.fp_ctrl.typeTagIn, slots_12.io.iss_uop.fp_ctrl.typeTagIn
connect issue_slots[12].iss_uop.fp_ctrl.swap23, slots_12.io.iss_uop.fp_ctrl.swap23
connect issue_slots[12].iss_uop.fp_ctrl.swap12, slots_12.io.iss_uop.fp_ctrl.swap12
connect issue_slots[12].iss_uop.fp_ctrl.ren3, slots_12.io.iss_uop.fp_ctrl.ren3
connect issue_slots[12].iss_uop.fp_ctrl.ren2, slots_12.io.iss_uop.fp_ctrl.ren2
connect issue_slots[12].iss_uop.fp_ctrl.ren1, slots_12.io.iss_uop.fp_ctrl.ren1
connect issue_slots[12].iss_uop.fp_ctrl.wen, slots_12.io.iss_uop.fp_ctrl.wen
connect issue_slots[12].iss_uop.fp_ctrl.ldst, slots_12.io.iss_uop.fp_ctrl.ldst
connect issue_slots[12].iss_uop.op2_sel, slots_12.io.iss_uop.op2_sel
connect issue_slots[12].iss_uop.op1_sel, slots_12.io.iss_uop.op1_sel
connect issue_slots[12].iss_uop.imm_packed, slots_12.io.iss_uop.imm_packed
connect issue_slots[12].iss_uop.pimm, slots_12.io.iss_uop.pimm
connect issue_slots[12].iss_uop.imm_sel, slots_12.io.iss_uop.imm_sel
connect issue_slots[12].iss_uop.imm_rename, slots_12.io.iss_uop.imm_rename
connect issue_slots[12].iss_uop.taken, slots_12.io.iss_uop.taken
connect issue_slots[12].iss_uop.pc_lob, slots_12.io.iss_uop.pc_lob
connect issue_slots[12].iss_uop.edge_inst, slots_12.io.iss_uop.edge_inst
connect issue_slots[12].iss_uop.ftq_idx, slots_12.io.iss_uop.ftq_idx
connect issue_slots[12].iss_uop.is_mov, slots_12.io.iss_uop.is_mov
connect issue_slots[12].iss_uop.is_rocc, slots_12.io.iss_uop.is_rocc
connect issue_slots[12].iss_uop.is_sys_pc2epc, slots_12.io.iss_uop.is_sys_pc2epc
connect issue_slots[12].iss_uop.is_eret, slots_12.io.iss_uop.is_eret
connect issue_slots[12].iss_uop.is_amo, slots_12.io.iss_uop.is_amo
connect issue_slots[12].iss_uop.is_sfence, slots_12.io.iss_uop.is_sfence
connect issue_slots[12].iss_uop.is_fencei, slots_12.io.iss_uop.is_fencei
connect issue_slots[12].iss_uop.is_fence, slots_12.io.iss_uop.is_fence
connect issue_slots[12].iss_uop.is_sfb, slots_12.io.iss_uop.is_sfb
connect issue_slots[12].iss_uop.br_type, slots_12.io.iss_uop.br_type
connect issue_slots[12].iss_uop.br_tag, slots_12.io.iss_uop.br_tag
connect issue_slots[12].iss_uop.br_mask, slots_12.io.iss_uop.br_mask
connect issue_slots[12].iss_uop.dis_col_sel, slots_12.io.iss_uop.dis_col_sel
connect issue_slots[12].iss_uop.iw_p3_bypass_hint, slots_12.io.iss_uop.iw_p3_bypass_hint
connect issue_slots[12].iss_uop.iw_p2_bypass_hint, slots_12.io.iss_uop.iw_p2_bypass_hint
connect issue_slots[12].iss_uop.iw_p1_bypass_hint, slots_12.io.iss_uop.iw_p1_bypass_hint
connect issue_slots[12].iss_uop.iw_p2_speculative_child, slots_12.io.iss_uop.iw_p2_speculative_child
connect issue_slots[12].iss_uop.iw_p1_speculative_child, slots_12.io.iss_uop.iw_p1_speculative_child
connect issue_slots[12].iss_uop.iw_issued_partial_dgen, slots_12.io.iss_uop.iw_issued_partial_dgen
connect issue_slots[12].iss_uop.iw_issued_partial_agen, slots_12.io.iss_uop.iw_issued_partial_agen
connect issue_slots[12].iss_uop.iw_issued, slots_12.io.iss_uop.iw_issued
connect issue_slots[12].iss_uop.fu_code[0], slots_12.io.iss_uop.fu_code[0]
connect issue_slots[12].iss_uop.fu_code[1], slots_12.io.iss_uop.fu_code[1]
connect issue_slots[12].iss_uop.fu_code[2], slots_12.io.iss_uop.fu_code[2]
connect issue_slots[12].iss_uop.fu_code[3], slots_12.io.iss_uop.fu_code[3]
connect issue_slots[12].iss_uop.fu_code[4], slots_12.io.iss_uop.fu_code[4]
connect issue_slots[12].iss_uop.fu_code[5], slots_12.io.iss_uop.fu_code[5]
connect issue_slots[12].iss_uop.fu_code[6], slots_12.io.iss_uop.fu_code[6]
connect issue_slots[12].iss_uop.fu_code[7], slots_12.io.iss_uop.fu_code[7]
connect issue_slots[12].iss_uop.fu_code[8], slots_12.io.iss_uop.fu_code[8]
connect issue_slots[12].iss_uop.fu_code[9], slots_12.io.iss_uop.fu_code[9]
connect issue_slots[12].iss_uop.iq_type[0], slots_12.io.iss_uop.iq_type[0]
connect issue_slots[12].iss_uop.iq_type[1], slots_12.io.iss_uop.iq_type[1]
connect issue_slots[12].iss_uop.iq_type[2], slots_12.io.iss_uop.iq_type[2]
connect issue_slots[12].iss_uop.iq_type[3], slots_12.io.iss_uop.iq_type[3]
connect issue_slots[12].iss_uop.debug_pc, slots_12.io.iss_uop.debug_pc
connect issue_slots[12].iss_uop.is_rvc, slots_12.io.iss_uop.is_rvc
connect issue_slots[12].iss_uop.debug_inst, slots_12.io.iss_uop.debug_inst
connect issue_slots[12].iss_uop.inst, slots_12.io.iss_uop.inst
connect slots_12.io.grant, issue_slots[12].grant
connect issue_slots[12].request, slots_12.io.request
connect issue_slots[12].will_be_valid, slots_12.io.will_be_valid
connect issue_slots[12].valid, slots_12.io.valid
connect slots_13.io.child_rebusys, issue_slots[13].child_rebusys
connect slots_13.io.pred_wakeup_port.bits, issue_slots[13].pred_wakeup_port.bits
connect slots_13.io.pred_wakeup_port.valid, issue_slots[13].pred_wakeup_port.valid
connect slots_13.io.wakeup_ports[0].bits.rebusy, issue_slots[13].wakeup_ports[0].bits.rebusy
connect slots_13.io.wakeup_ports[0].bits.speculative_mask, issue_slots[13].wakeup_ports[0].bits.speculative_mask
connect slots_13.io.wakeup_ports[0].bits.bypassable, issue_slots[13].wakeup_ports[0].bits.bypassable
connect slots_13.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[13].wakeup_ports[0].bits.uop.debug_tsrc
connect slots_13.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[13].wakeup_ports[0].bits.uop.debug_fsrc
connect slots_13.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[13].wakeup_ports[0].bits.uop.bp_xcpt_if
connect slots_13.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[13].wakeup_ports[0].bits.uop.bp_debug_if
connect slots_13.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[13].wakeup_ports[0].bits.uop.xcpt_ma_if
connect slots_13.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[13].wakeup_ports[0].bits.uop.xcpt_ae_if
connect slots_13.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[13].wakeup_ports[0].bits.uop.xcpt_pf_if
connect slots_13.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[13].wakeup_ports[0].bits.uop.fp_typ
connect slots_13.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[13].wakeup_ports[0].bits.uop.fp_rm
connect slots_13.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[13].wakeup_ports[0].bits.uop.fp_val
connect slots_13.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[13].wakeup_ports[0].bits.uop.fcn_op
connect slots_13.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[13].wakeup_ports[0].bits.uop.fcn_dw
connect slots_13.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[13].wakeup_ports[0].bits.uop.frs3_en
connect slots_13.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[13].wakeup_ports[0].bits.uop.lrs2_rtype
connect slots_13.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[13].wakeup_ports[0].bits.uop.lrs1_rtype
connect slots_13.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[13].wakeup_ports[0].bits.uop.dst_rtype
connect slots_13.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[13].wakeup_ports[0].bits.uop.lrs3
connect slots_13.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[13].wakeup_ports[0].bits.uop.lrs2
connect slots_13.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[13].wakeup_ports[0].bits.uop.lrs1
connect slots_13.io.wakeup_ports[0].bits.uop.ldst, issue_slots[13].wakeup_ports[0].bits.uop.ldst
connect slots_13.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[13].wakeup_ports[0].bits.uop.ldst_is_rs1
connect slots_13.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[13].wakeup_ports[0].bits.uop.csr_cmd
connect slots_13.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[13].wakeup_ports[0].bits.uop.flush_on_commit
connect slots_13.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[13].wakeup_ports[0].bits.uop.is_unique
connect slots_13.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[13].wakeup_ports[0].bits.uop.uses_stq
connect slots_13.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[13].wakeup_ports[0].bits.uop.uses_ldq
connect slots_13.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[13].wakeup_ports[0].bits.uop.mem_signed
connect slots_13.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[13].wakeup_ports[0].bits.uop.mem_size
connect slots_13.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[13].wakeup_ports[0].bits.uop.mem_cmd
connect slots_13.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[13].wakeup_ports[0].bits.uop.exc_cause
connect slots_13.io.wakeup_ports[0].bits.uop.exception, issue_slots[13].wakeup_ports[0].bits.uop.exception
connect slots_13.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[13].wakeup_ports[0].bits.uop.stale_pdst
connect slots_13.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[13].wakeup_ports[0].bits.uop.ppred_busy
connect slots_13.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[13].wakeup_ports[0].bits.uop.prs3_busy
connect slots_13.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[13].wakeup_ports[0].bits.uop.prs2_busy
connect slots_13.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[13].wakeup_ports[0].bits.uop.prs1_busy
connect slots_13.io.wakeup_ports[0].bits.uop.ppred, issue_slots[13].wakeup_ports[0].bits.uop.ppred
connect slots_13.io.wakeup_ports[0].bits.uop.prs3, issue_slots[13].wakeup_ports[0].bits.uop.prs3
connect slots_13.io.wakeup_ports[0].bits.uop.prs2, issue_slots[13].wakeup_ports[0].bits.uop.prs2
connect slots_13.io.wakeup_ports[0].bits.uop.prs1, issue_slots[13].wakeup_ports[0].bits.uop.prs1
connect slots_13.io.wakeup_ports[0].bits.uop.pdst, issue_slots[13].wakeup_ports[0].bits.uop.pdst
connect slots_13.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[13].wakeup_ports[0].bits.uop.rxq_idx
connect slots_13.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[13].wakeup_ports[0].bits.uop.stq_idx
connect slots_13.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[13].wakeup_ports[0].bits.uop.ldq_idx
connect slots_13.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[13].wakeup_ports[0].bits.uop.rob_idx
connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.vec
connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.wflags
connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.sqrt
connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.div
connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.fma
connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe
connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.toint
connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.fromint
connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut
connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn
connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.swap23
connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.swap12
connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.ren3
connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.ren2
connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.ren1
connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.wen
connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.ldst
connect slots_13.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[13].wakeup_ports[0].bits.uop.op2_sel
connect slots_13.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[13].wakeup_ports[0].bits.uop.op1_sel
connect slots_13.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[13].wakeup_ports[0].bits.uop.imm_packed
connect slots_13.io.wakeup_ports[0].bits.uop.pimm, issue_slots[13].wakeup_ports[0].bits.uop.pimm
connect slots_13.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[13].wakeup_ports[0].bits.uop.imm_sel
connect slots_13.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[13].wakeup_ports[0].bits.uop.imm_rename
connect slots_13.io.wakeup_ports[0].bits.uop.taken, issue_slots[13].wakeup_ports[0].bits.uop.taken
connect slots_13.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[13].wakeup_ports[0].bits.uop.pc_lob
connect slots_13.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[13].wakeup_ports[0].bits.uop.edge_inst
connect slots_13.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[13].wakeup_ports[0].bits.uop.ftq_idx
connect slots_13.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[13].wakeup_ports[0].bits.uop.is_mov
connect slots_13.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[13].wakeup_ports[0].bits.uop.is_rocc
connect slots_13.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[13].wakeup_ports[0].bits.uop.is_sys_pc2epc
connect slots_13.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[13].wakeup_ports[0].bits.uop.is_eret
connect slots_13.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[13].wakeup_ports[0].bits.uop.is_amo
connect slots_13.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[13].wakeup_ports[0].bits.uop.is_sfence
connect slots_13.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[13].wakeup_ports[0].bits.uop.is_fencei
connect slots_13.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[13].wakeup_ports[0].bits.uop.is_fence
connect slots_13.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[13].wakeup_ports[0].bits.uop.is_sfb
connect slots_13.io.wakeup_ports[0].bits.uop.br_type, issue_slots[13].wakeup_ports[0].bits.uop.br_type
connect slots_13.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[13].wakeup_ports[0].bits.uop.br_tag
connect slots_13.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[13].wakeup_ports[0].bits.uop.br_mask
connect slots_13.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[13].wakeup_ports[0].bits.uop.dis_col_sel
connect slots_13.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[13].wakeup_ports[0].bits.uop.iw_p3_bypass_hint
connect slots_13.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[13].wakeup_ports[0].bits.uop.iw_p2_bypass_hint
connect slots_13.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[13].wakeup_ports[0].bits.uop.iw_p1_bypass_hint
connect slots_13.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[13].wakeup_ports[0].bits.uop.iw_p2_speculative_child
connect slots_13.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[13].wakeup_ports[0].bits.uop.iw_p1_speculative_child
connect slots_13.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[13].wakeup_ports[0].bits.uop.iw_issued_partial_dgen
connect slots_13.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[13].wakeup_ports[0].bits.uop.iw_issued_partial_agen
connect slots_13.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[13].wakeup_ports[0].bits.uop.iw_issued
connect slots_13.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[13].wakeup_ports[0].bits.uop.fu_code[0]
connect slots_13.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[13].wakeup_ports[0].bits.uop.fu_code[1]
connect slots_13.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[13].wakeup_ports[0].bits.uop.fu_code[2]
connect slots_13.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[13].wakeup_ports[0].bits.uop.fu_code[3]
connect slots_13.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[13].wakeup_ports[0].bits.uop.fu_code[4]
connect slots_13.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[13].wakeup_ports[0].bits.uop.fu_code[5]
connect slots_13.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[13].wakeup_ports[0].bits.uop.fu_code[6]
connect slots_13.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[13].wakeup_ports[0].bits.uop.fu_code[7]
connect slots_13.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[13].wakeup_ports[0].bits.uop.fu_code[8]
connect slots_13.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[13].wakeup_ports[0].bits.uop.fu_code[9]
connect slots_13.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[13].wakeup_ports[0].bits.uop.iq_type[0]
connect slots_13.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[13].wakeup_ports[0].bits.uop.iq_type[1]
connect slots_13.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[13].wakeup_ports[0].bits.uop.iq_type[2]
connect slots_13.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[13].wakeup_ports[0].bits.uop.iq_type[3]
connect slots_13.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[13].wakeup_ports[0].bits.uop.debug_pc
connect slots_13.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[13].wakeup_ports[0].bits.uop.is_rvc
connect slots_13.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[13].wakeup_ports[0].bits.uop.debug_inst
connect slots_13.io.wakeup_ports[0].bits.uop.inst, issue_slots[13].wakeup_ports[0].bits.uop.inst
connect slots_13.io.wakeup_ports[0].valid, issue_slots[13].wakeup_ports[0].valid
connect slots_13.io.wakeup_ports[1].bits.rebusy, issue_slots[13].wakeup_ports[1].bits.rebusy
connect slots_13.io.wakeup_ports[1].bits.speculative_mask, issue_slots[13].wakeup_ports[1].bits.speculative_mask
connect slots_13.io.wakeup_ports[1].bits.bypassable, issue_slots[13].wakeup_ports[1].bits.bypassable
connect slots_13.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[13].wakeup_ports[1].bits.uop.debug_tsrc
connect slots_13.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[13].wakeup_ports[1].bits.uop.debug_fsrc
connect slots_13.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[13].wakeup_ports[1].bits.uop.bp_xcpt_if
connect slots_13.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[13].wakeup_ports[1].bits.uop.bp_debug_if
connect slots_13.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[13].wakeup_ports[1].bits.uop.xcpt_ma_if
connect slots_13.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[13].wakeup_ports[1].bits.uop.xcpt_ae_if
connect slots_13.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[13].wakeup_ports[1].bits.uop.xcpt_pf_if
connect slots_13.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[13].wakeup_ports[1].bits.uop.fp_typ
connect slots_13.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[13].wakeup_ports[1].bits.uop.fp_rm
connect slots_13.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[13].wakeup_ports[1].bits.uop.fp_val
connect slots_13.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[13].wakeup_ports[1].bits.uop.fcn_op
connect slots_13.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[13].wakeup_ports[1].bits.uop.fcn_dw
connect slots_13.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[13].wakeup_ports[1].bits.uop.frs3_en
connect slots_13.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[13].wakeup_ports[1].bits.uop.lrs2_rtype
connect slots_13.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[13].wakeup_ports[1].bits.uop.lrs1_rtype
connect slots_13.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[13].wakeup_ports[1].bits.uop.dst_rtype
connect slots_13.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[13].wakeup_ports[1].bits.uop.lrs3
connect slots_13.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[13].wakeup_ports[1].bits.uop.lrs2
connect slots_13.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[13].wakeup_ports[1].bits.uop.lrs1
connect slots_13.io.wakeup_ports[1].bits.uop.ldst, issue_slots[13].wakeup_ports[1].bits.uop.ldst
connect slots_13.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[13].wakeup_ports[1].bits.uop.ldst_is_rs1
connect slots_13.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[13].wakeup_ports[1].bits.uop.csr_cmd
connect slots_13.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[13].wakeup_ports[1].bits.uop.flush_on_commit
connect slots_13.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[13].wakeup_ports[1].bits.uop.is_unique
connect slots_13.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[13].wakeup_ports[1].bits.uop.uses_stq
connect slots_13.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[13].wakeup_ports[1].bits.uop.uses_ldq
connect slots_13.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[13].wakeup_ports[1].bits.uop.mem_signed
connect slots_13.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[13].wakeup_ports[1].bits.uop.mem_size
connect slots_13.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[13].wakeup_ports[1].bits.uop.mem_cmd
connect slots_13.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[13].wakeup_ports[1].bits.uop.exc_cause
connect slots_13.io.wakeup_ports[1].bits.uop.exception, issue_slots[13].wakeup_ports[1].bits.uop.exception
connect slots_13.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[13].wakeup_ports[1].bits.uop.stale_pdst
connect slots_13.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[13].wakeup_ports[1].bits.uop.ppred_busy
connect slots_13.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[13].wakeup_ports[1].bits.uop.prs3_busy
connect slots_13.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[13].wakeup_ports[1].bits.uop.prs2_busy
connect slots_13.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[13].wakeup_ports[1].bits.uop.prs1_busy
connect slots_13.io.wakeup_ports[1].bits.uop.ppred, issue_slots[13].wakeup_ports[1].bits.uop.ppred
connect slots_13.io.wakeup_ports[1].bits.uop.prs3, issue_slots[13].wakeup_ports[1].bits.uop.prs3
connect slots_13.io.wakeup_ports[1].bits.uop.prs2, issue_slots[13].wakeup_ports[1].bits.uop.prs2
connect slots_13.io.wakeup_ports[1].bits.uop.prs1, issue_slots[13].wakeup_ports[1].bits.uop.prs1
connect slots_13.io.wakeup_ports[1].bits.uop.pdst, issue_slots[13].wakeup_ports[1].bits.uop.pdst
connect slots_13.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[13].wakeup_ports[1].bits.uop.rxq_idx
connect slots_13.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[13].wakeup_ports[1].bits.uop.stq_idx
connect slots_13.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[13].wakeup_ports[1].bits.uop.ldq_idx
connect slots_13.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[13].wakeup_ports[1].bits.uop.rob_idx
connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.vec
connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.wflags
connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.sqrt
connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.div
connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.fma
connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe
connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.toint
connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.fromint
connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut
connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn
connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.swap23
connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.swap12
connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.ren3
connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.ren2
connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.ren1
connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.wen
connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.ldst
connect slots_13.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[13].wakeup_ports[1].bits.uop.op2_sel
connect slots_13.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[13].wakeup_ports[1].bits.uop.op1_sel
connect slots_13.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[13].wakeup_ports[1].bits.uop.imm_packed
connect slots_13.io.wakeup_ports[1].bits.uop.pimm, issue_slots[13].wakeup_ports[1].bits.uop.pimm
connect slots_13.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[13].wakeup_ports[1].bits.uop.imm_sel
connect slots_13.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[13].wakeup_ports[1].bits.uop.imm_rename
connect slots_13.io.wakeup_ports[1].bits.uop.taken, issue_slots[13].wakeup_ports[1].bits.uop.taken
connect slots_13.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[13].wakeup_ports[1].bits.uop.pc_lob
connect slots_13.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[13].wakeup_ports[1].bits.uop.edge_inst
connect slots_13.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[13].wakeup_ports[1].bits.uop.ftq_idx
connect slots_13.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[13].wakeup_ports[1].bits.uop.is_mov
connect slots_13.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[13].wakeup_ports[1].bits.uop.is_rocc
connect slots_13.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[13].wakeup_ports[1].bits.uop.is_sys_pc2epc
connect slots_13.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[13].wakeup_ports[1].bits.uop.is_eret
connect slots_13.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[13].wakeup_ports[1].bits.uop.is_amo
connect slots_13.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[13].wakeup_ports[1].bits.uop.is_sfence
connect slots_13.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[13].wakeup_ports[1].bits.uop.is_fencei
connect slots_13.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[13].wakeup_ports[1].bits.uop.is_fence
connect slots_13.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[13].wakeup_ports[1].bits.uop.is_sfb
connect slots_13.io.wakeup_ports[1].bits.uop.br_type, issue_slots[13].wakeup_ports[1].bits.uop.br_type
connect slots_13.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[13].wakeup_ports[1].bits.uop.br_tag
connect slots_13.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[13].wakeup_ports[1].bits.uop.br_mask
connect slots_13.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[13].wakeup_ports[1].bits.uop.dis_col_sel
connect slots_13.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[13].wakeup_ports[1].bits.uop.iw_p3_bypass_hint
connect slots_13.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[13].wakeup_ports[1].bits.uop.iw_p2_bypass_hint
connect slots_13.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[13].wakeup_ports[1].bits.uop.iw_p1_bypass_hint
connect slots_13.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[13].wakeup_ports[1].bits.uop.iw_p2_speculative_child
connect slots_13.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[13].wakeup_ports[1].bits.uop.iw_p1_speculative_child
connect slots_13.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[13].wakeup_ports[1].bits.uop.iw_issued_partial_dgen
connect slots_13.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[13].wakeup_ports[1].bits.uop.iw_issued_partial_agen
connect slots_13.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[13].wakeup_ports[1].bits.uop.iw_issued
connect slots_13.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[13].wakeup_ports[1].bits.uop.fu_code[0]
connect slots_13.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[13].wakeup_ports[1].bits.uop.fu_code[1]
connect slots_13.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[13].wakeup_ports[1].bits.uop.fu_code[2]
connect slots_13.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[13].wakeup_ports[1].bits.uop.fu_code[3]
connect slots_13.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[13].wakeup_ports[1].bits.uop.fu_code[4]
connect slots_13.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[13].wakeup_ports[1].bits.uop.fu_code[5]
connect slots_13.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[13].wakeup_ports[1].bits.uop.fu_code[6]
connect slots_13.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[13].wakeup_ports[1].bits.uop.fu_code[7]
connect slots_13.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[13].wakeup_ports[1].bits.uop.fu_code[8]
connect slots_13.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[13].wakeup_ports[1].bits.uop.fu_code[9]
connect slots_13.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[13].wakeup_ports[1].bits.uop.iq_type[0]
connect slots_13.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[13].wakeup_ports[1].bits.uop.iq_type[1]
connect slots_13.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[13].wakeup_ports[1].bits.uop.iq_type[2]
connect slots_13.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[13].wakeup_ports[1].bits.uop.iq_type[3]
connect slots_13.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[13].wakeup_ports[1].bits.uop.debug_pc
connect slots_13.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[13].wakeup_ports[1].bits.uop.is_rvc
connect slots_13.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[13].wakeup_ports[1].bits.uop.debug_inst
connect slots_13.io.wakeup_ports[1].bits.uop.inst, issue_slots[13].wakeup_ports[1].bits.uop.inst
connect slots_13.io.wakeup_ports[1].valid, issue_slots[13].wakeup_ports[1].valid
connect slots_13.io.wakeup_ports[2].bits.rebusy, issue_slots[13].wakeup_ports[2].bits.rebusy
connect slots_13.io.wakeup_ports[2].bits.speculative_mask, issue_slots[13].wakeup_ports[2].bits.speculative_mask
connect slots_13.io.wakeup_ports[2].bits.bypassable, issue_slots[13].wakeup_ports[2].bits.bypassable
connect slots_13.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[13].wakeup_ports[2].bits.uop.debug_tsrc
connect slots_13.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[13].wakeup_ports[2].bits.uop.debug_fsrc
connect slots_13.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[13].wakeup_ports[2].bits.uop.bp_xcpt_if
connect slots_13.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[13].wakeup_ports[2].bits.uop.bp_debug_if
connect slots_13.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[13].wakeup_ports[2].bits.uop.xcpt_ma_if
connect slots_13.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[13].wakeup_ports[2].bits.uop.xcpt_ae_if
connect slots_13.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[13].wakeup_ports[2].bits.uop.xcpt_pf_if
connect slots_13.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[13].wakeup_ports[2].bits.uop.fp_typ
connect slots_13.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[13].wakeup_ports[2].bits.uop.fp_rm
connect slots_13.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[13].wakeup_ports[2].bits.uop.fp_val
connect slots_13.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[13].wakeup_ports[2].bits.uop.fcn_op
connect slots_13.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[13].wakeup_ports[2].bits.uop.fcn_dw
connect slots_13.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[13].wakeup_ports[2].bits.uop.frs3_en
connect slots_13.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[13].wakeup_ports[2].bits.uop.lrs2_rtype
connect slots_13.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[13].wakeup_ports[2].bits.uop.lrs1_rtype
connect slots_13.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[13].wakeup_ports[2].bits.uop.dst_rtype
connect slots_13.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[13].wakeup_ports[2].bits.uop.lrs3
connect slots_13.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[13].wakeup_ports[2].bits.uop.lrs2
connect slots_13.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[13].wakeup_ports[2].bits.uop.lrs1
connect slots_13.io.wakeup_ports[2].bits.uop.ldst, issue_slots[13].wakeup_ports[2].bits.uop.ldst
connect slots_13.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[13].wakeup_ports[2].bits.uop.ldst_is_rs1
connect slots_13.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[13].wakeup_ports[2].bits.uop.csr_cmd
connect slots_13.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[13].wakeup_ports[2].bits.uop.flush_on_commit
connect slots_13.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[13].wakeup_ports[2].bits.uop.is_unique
connect slots_13.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[13].wakeup_ports[2].bits.uop.uses_stq
connect slots_13.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[13].wakeup_ports[2].bits.uop.uses_ldq
connect slots_13.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[13].wakeup_ports[2].bits.uop.mem_signed
connect slots_13.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[13].wakeup_ports[2].bits.uop.mem_size
connect slots_13.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[13].wakeup_ports[2].bits.uop.mem_cmd
connect slots_13.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[13].wakeup_ports[2].bits.uop.exc_cause
connect slots_13.io.wakeup_ports[2].bits.uop.exception, issue_slots[13].wakeup_ports[2].bits.uop.exception
connect slots_13.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[13].wakeup_ports[2].bits.uop.stale_pdst
connect slots_13.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[13].wakeup_ports[2].bits.uop.ppred_busy
connect slots_13.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[13].wakeup_ports[2].bits.uop.prs3_busy
connect slots_13.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[13].wakeup_ports[2].bits.uop.prs2_busy
connect slots_13.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[13].wakeup_ports[2].bits.uop.prs1_busy
connect slots_13.io.wakeup_ports[2].bits.uop.ppred, issue_slots[13].wakeup_ports[2].bits.uop.ppred
connect slots_13.io.wakeup_ports[2].bits.uop.prs3, issue_slots[13].wakeup_ports[2].bits.uop.prs3
connect slots_13.io.wakeup_ports[2].bits.uop.prs2, issue_slots[13].wakeup_ports[2].bits.uop.prs2
connect slots_13.io.wakeup_ports[2].bits.uop.prs1, issue_slots[13].wakeup_ports[2].bits.uop.prs1
connect slots_13.io.wakeup_ports[2].bits.uop.pdst, issue_slots[13].wakeup_ports[2].bits.uop.pdst
connect slots_13.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[13].wakeup_ports[2].bits.uop.rxq_idx
connect slots_13.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[13].wakeup_ports[2].bits.uop.stq_idx
connect slots_13.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[13].wakeup_ports[2].bits.uop.ldq_idx
connect slots_13.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[13].wakeup_ports[2].bits.uop.rob_idx
connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.vec
connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.wflags
connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.sqrt
connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.div
connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.fma
connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe
connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.toint
connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.fromint
connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut
connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn
connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.swap23
connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.swap12
connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.ren3
connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.ren2
connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.ren1
connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.wen
connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.ldst
connect slots_13.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[13].wakeup_ports[2].bits.uop.op2_sel
connect slots_13.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[13].wakeup_ports[2].bits.uop.op1_sel
connect slots_13.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[13].wakeup_ports[2].bits.uop.imm_packed
connect slots_13.io.wakeup_ports[2].bits.uop.pimm, issue_slots[13].wakeup_ports[2].bits.uop.pimm
connect slots_13.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[13].wakeup_ports[2].bits.uop.imm_sel
connect slots_13.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[13].wakeup_ports[2].bits.uop.imm_rename
connect slots_13.io.wakeup_ports[2].bits.uop.taken, issue_slots[13].wakeup_ports[2].bits.uop.taken
connect slots_13.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[13].wakeup_ports[2].bits.uop.pc_lob
connect slots_13.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[13].wakeup_ports[2].bits.uop.edge_inst
connect slots_13.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[13].wakeup_ports[2].bits.uop.ftq_idx
connect slots_13.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[13].wakeup_ports[2].bits.uop.is_mov
connect slots_13.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[13].wakeup_ports[2].bits.uop.is_rocc
connect slots_13.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[13].wakeup_ports[2].bits.uop.is_sys_pc2epc
connect slots_13.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[13].wakeup_ports[2].bits.uop.is_eret
connect slots_13.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[13].wakeup_ports[2].bits.uop.is_amo
connect slots_13.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[13].wakeup_ports[2].bits.uop.is_sfence
connect slots_13.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[13].wakeup_ports[2].bits.uop.is_fencei
connect slots_13.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[13].wakeup_ports[2].bits.uop.is_fence
connect slots_13.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[13].wakeup_ports[2].bits.uop.is_sfb
connect slots_13.io.wakeup_ports[2].bits.uop.br_type, issue_slots[13].wakeup_ports[2].bits.uop.br_type
connect slots_13.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[13].wakeup_ports[2].bits.uop.br_tag
connect slots_13.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[13].wakeup_ports[2].bits.uop.br_mask
connect slots_13.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[13].wakeup_ports[2].bits.uop.dis_col_sel
connect slots_13.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[13].wakeup_ports[2].bits.uop.iw_p3_bypass_hint
connect slots_13.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[13].wakeup_ports[2].bits.uop.iw_p2_bypass_hint
connect slots_13.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[13].wakeup_ports[2].bits.uop.iw_p1_bypass_hint
connect slots_13.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[13].wakeup_ports[2].bits.uop.iw_p2_speculative_child
connect slots_13.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[13].wakeup_ports[2].bits.uop.iw_p1_speculative_child
connect slots_13.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[13].wakeup_ports[2].bits.uop.iw_issued_partial_dgen
connect slots_13.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[13].wakeup_ports[2].bits.uop.iw_issued_partial_agen
connect slots_13.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[13].wakeup_ports[2].bits.uop.iw_issued
connect slots_13.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[13].wakeup_ports[2].bits.uop.fu_code[0]
connect slots_13.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[13].wakeup_ports[2].bits.uop.fu_code[1]
connect slots_13.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[13].wakeup_ports[2].bits.uop.fu_code[2]
connect slots_13.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[13].wakeup_ports[2].bits.uop.fu_code[3]
connect slots_13.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[13].wakeup_ports[2].bits.uop.fu_code[4]
connect slots_13.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[13].wakeup_ports[2].bits.uop.fu_code[5]
connect slots_13.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[13].wakeup_ports[2].bits.uop.fu_code[6]
connect slots_13.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[13].wakeup_ports[2].bits.uop.fu_code[7]
connect slots_13.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[13].wakeup_ports[2].bits.uop.fu_code[8]
connect slots_13.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[13].wakeup_ports[2].bits.uop.fu_code[9]
connect slots_13.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[13].wakeup_ports[2].bits.uop.iq_type[0]
connect slots_13.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[13].wakeup_ports[2].bits.uop.iq_type[1]
connect slots_13.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[13].wakeup_ports[2].bits.uop.iq_type[2]
connect slots_13.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[13].wakeup_ports[2].bits.uop.iq_type[3]
connect slots_13.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[13].wakeup_ports[2].bits.uop.debug_pc
connect slots_13.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[13].wakeup_ports[2].bits.uop.is_rvc
connect slots_13.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[13].wakeup_ports[2].bits.uop.debug_inst
connect slots_13.io.wakeup_ports[2].bits.uop.inst, issue_slots[13].wakeup_ports[2].bits.uop.inst
connect slots_13.io.wakeup_ports[2].valid, issue_slots[13].wakeup_ports[2].valid
connect slots_13.io.wakeup_ports[3].bits.rebusy, issue_slots[13].wakeup_ports[3].bits.rebusy
connect slots_13.io.wakeup_ports[3].bits.speculative_mask, issue_slots[13].wakeup_ports[3].bits.speculative_mask
connect slots_13.io.wakeup_ports[3].bits.bypassable, issue_slots[13].wakeup_ports[3].bits.bypassable
connect slots_13.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[13].wakeup_ports[3].bits.uop.debug_tsrc
connect slots_13.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[13].wakeup_ports[3].bits.uop.debug_fsrc
connect slots_13.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[13].wakeup_ports[3].bits.uop.bp_xcpt_if
connect slots_13.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[13].wakeup_ports[3].bits.uop.bp_debug_if
connect slots_13.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[13].wakeup_ports[3].bits.uop.xcpt_ma_if
connect slots_13.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[13].wakeup_ports[3].bits.uop.xcpt_ae_if
connect slots_13.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[13].wakeup_ports[3].bits.uop.xcpt_pf_if
connect slots_13.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[13].wakeup_ports[3].bits.uop.fp_typ
connect slots_13.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[13].wakeup_ports[3].bits.uop.fp_rm
connect slots_13.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[13].wakeup_ports[3].bits.uop.fp_val
connect slots_13.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[13].wakeup_ports[3].bits.uop.fcn_op
connect slots_13.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[13].wakeup_ports[3].bits.uop.fcn_dw
connect slots_13.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[13].wakeup_ports[3].bits.uop.frs3_en
connect slots_13.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[13].wakeup_ports[3].bits.uop.lrs2_rtype
connect slots_13.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[13].wakeup_ports[3].bits.uop.lrs1_rtype
connect slots_13.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[13].wakeup_ports[3].bits.uop.dst_rtype
connect slots_13.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[13].wakeup_ports[3].bits.uop.lrs3
connect slots_13.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[13].wakeup_ports[3].bits.uop.lrs2
connect slots_13.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[13].wakeup_ports[3].bits.uop.lrs1
connect slots_13.io.wakeup_ports[3].bits.uop.ldst, issue_slots[13].wakeup_ports[3].bits.uop.ldst
connect slots_13.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[13].wakeup_ports[3].bits.uop.ldst_is_rs1
connect slots_13.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[13].wakeup_ports[3].bits.uop.csr_cmd
connect slots_13.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[13].wakeup_ports[3].bits.uop.flush_on_commit
connect slots_13.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[13].wakeup_ports[3].bits.uop.is_unique
connect slots_13.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[13].wakeup_ports[3].bits.uop.uses_stq
connect slots_13.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[13].wakeup_ports[3].bits.uop.uses_ldq
connect slots_13.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[13].wakeup_ports[3].bits.uop.mem_signed
connect slots_13.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[13].wakeup_ports[3].bits.uop.mem_size
connect slots_13.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[13].wakeup_ports[3].bits.uop.mem_cmd
connect slots_13.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[13].wakeup_ports[3].bits.uop.exc_cause
connect slots_13.io.wakeup_ports[3].bits.uop.exception, issue_slots[13].wakeup_ports[3].bits.uop.exception
connect slots_13.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[13].wakeup_ports[3].bits.uop.stale_pdst
connect slots_13.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[13].wakeup_ports[3].bits.uop.ppred_busy
connect slots_13.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[13].wakeup_ports[3].bits.uop.prs3_busy
connect slots_13.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[13].wakeup_ports[3].bits.uop.prs2_busy
connect slots_13.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[13].wakeup_ports[3].bits.uop.prs1_busy
connect slots_13.io.wakeup_ports[3].bits.uop.ppred, issue_slots[13].wakeup_ports[3].bits.uop.ppred
connect slots_13.io.wakeup_ports[3].bits.uop.prs3, issue_slots[13].wakeup_ports[3].bits.uop.prs3
connect slots_13.io.wakeup_ports[3].bits.uop.prs2, issue_slots[13].wakeup_ports[3].bits.uop.prs2
connect slots_13.io.wakeup_ports[3].bits.uop.prs1, issue_slots[13].wakeup_ports[3].bits.uop.prs1
connect slots_13.io.wakeup_ports[3].bits.uop.pdst, issue_slots[13].wakeup_ports[3].bits.uop.pdst
connect slots_13.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[13].wakeup_ports[3].bits.uop.rxq_idx
connect slots_13.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[13].wakeup_ports[3].bits.uop.stq_idx
connect slots_13.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[13].wakeup_ports[3].bits.uop.ldq_idx
connect slots_13.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[13].wakeup_ports[3].bits.uop.rob_idx
connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.vec
connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.wflags
connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.sqrt
connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.div
connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.fma
connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe
connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.toint
connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.fromint
connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut
connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn
connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.swap23
connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.swap12
connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.ren3
connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.ren2
connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.ren1
connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.wen
connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.ldst
connect slots_13.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[13].wakeup_ports[3].bits.uop.op2_sel
connect slots_13.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[13].wakeup_ports[3].bits.uop.op1_sel
connect slots_13.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[13].wakeup_ports[3].bits.uop.imm_packed
connect slots_13.io.wakeup_ports[3].bits.uop.pimm, issue_slots[13].wakeup_ports[3].bits.uop.pimm
connect slots_13.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[13].wakeup_ports[3].bits.uop.imm_sel
connect slots_13.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[13].wakeup_ports[3].bits.uop.imm_rename
connect slots_13.io.wakeup_ports[3].bits.uop.taken, issue_slots[13].wakeup_ports[3].bits.uop.taken
connect slots_13.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[13].wakeup_ports[3].bits.uop.pc_lob
connect slots_13.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[13].wakeup_ports[3].bits.uop.edge_inst
connect slots_13.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[13].wakeup_ports[3].bits.uop.ftq_idx
connect slots_13.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[13].wakeup_ports[3].bits.uop.is_mov
connect slots_13.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[13].wakeup_ports[3].bits.uop.is_rocc
connect slots_13.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[13].wakeup_ports[3].bits.uop.is_sys_pc2epc
connect slots_13.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[13].wakeup_ports[3].bits.uop.is_eret
connect slots_13.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[13].wakeup_ports[3].bits.uop.is_amo
connect slots_13.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[13].wakeup_ports[3].bits.uop.is_sfence
connect slots_13.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[13].wakeup_ports[3].bits.uop.is_fencei
connect slots_13.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[13].wakeup_ports[3].bits.uop.is_fence
connect slots_13.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[13].wakeup_ports[3].bits.uop.is_sfb
connect slots_13.io.wakeup_ports[3].bits.uop.br_type, issue_slots[13].wakeup_ports[3].bits.uop.br_type
connect slots_13.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[13].wakeup_ports[3].bits.uop.br_tag
connect slots_13.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[13].wakeup_ports[3].bits.uop.br_mask
connect slots_13.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[13].wakeup_ports[3].bits.uop.dis_col_sel
connect slots_13.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[13].wakeup_ports[3].bits.uop.iw_p3_bypass_hint
connect slots_13.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[13].wakeup_ports[3].bits.uop.iw_p2_bypass_hint
connect slots_13.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[13].wakeup_ports[3].bits.uop.iw_p1_bypass_hint
connect slots_13.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[13].wakeup_ports[3].bits.uop.iw_p2_speculative_child
connect slots_13.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[13].wakeup_ports[3].bits.uop.iw_p1_speculative_child
connect slots_13.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[13].wakeup_ports[3].bits.uop.iw_issued_partial_dgen
connect slots_13.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[13].wakeup_ports[3].bits.uop.iw_issued_partial_agen
connect slots_13.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[13].wakeup_ports[3].bits.uop.iw_issued
connect slots_13.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[13].wakeup_ports[3].bits.uop.fu_code[0]
connect slots_13.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[13].wakeup_ports[3].bits.uop.fu_code[1]
connect slots_13.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[13].wakeup_ports[3].bits.uop.fu_code[2]
connect slots_13.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[13].wakeup_ports[3].bits.uop.fu_code[3]
connect slots_13.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[13].wakeup_ports[3].bits.uop.fu_code[4]
connect slots_13.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[13].wakeup_ports[3].bits.uop.fu_code[5]
connect slots_13.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[13].wakeup_ports[3].bits.uop.fu_code[6]
connect slots_13.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[13].wakeup_ports[3].bits.uop.fu_code[7]
connect slots_13.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[13].wakeup_ports[3].bits.uop.fu_code[8]
connect slots_13.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[13].wakeup_ports[3].bits.uop.fu_code[9]
connect slots_13.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[13].wakeup_ports[3].bits.uop.iq_type[0]
connect slots_13.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[13].wakeup_ports[3].bits.uop.iq_type[1]
connect slots_13.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[13].wakeup_ports[3].bits.uop.iq_type[2]
connect slots_13.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[13].wakeup_ports[3].bits.uop.iq_type[3]
connect slots_13.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[13].wakeup_ports[3].bits.uop.debug_pc
connect slots_13.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[13].wakeup_ports[3].bits.uop.is_rvc
connect slots_13.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[13].wakeup_ports[3].bits.uop.debug_inst
connect slots_13.io.wakeup_ports[3].bits.uop.inst, issue_slots[13].wakeup_ports[3].bits.uop.inst
connect slots_13.io.wakeup_ports[3].valid, issue_slots[13].wakeup_ports[3].valid
connect slots_13.io.squash_grant, issue_slots[13].squash_grant
connect slots_13.io.clear, issue_slots[13].clear
connect slots_13.io.kill, issue_slots[13].kill
connect slots_13.io.brupdate.b2.target_offset, issue_slots[13].brupdate.b2.target_offset
connect slots_13.io.brupdate.b2.jalr_target, issue_slots[13].brupdate.b2.jalr_target
connect slots_13.io.brupdate.b2.pc_sel, issue_slots[13].brupdate.b2.pc_sel
connect slots_13.io.brupdate.b2.cfi_type, issue_slots[13].brupdate.b2.cfi_type
connect slots_13.io.brupdate.b2.taken, issue_slots[13].brupdate.b2.taken
connect slots_13.io.brupdate.b2.mispredict, issue_slots[13].brupdate.b2.mispredict
connect slots_13.io.brupdate.b2.uop.debug_tsrc, issue_slots[13].brupdate.b2.uop.debug_tsrc
connect slots_13.io.brupdate.b2.uop.debug_fsrc, issue_slots[13].brupdate.b2.uop.debug_fsrc
connect slots_13.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[13].brupdate.b2.uop.bp_xcpt_if
connect slots_13.io.brupdate.b2.uop.bp_debug_if, issue_slots[13].brupdate.b2.uop.bp_debug_if
connect slots_13.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[13].brupdate.b2.uop.xcpt_ma_if
connect slots_13.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[13].brupdate.b2.uop.xcpt_ae_if
connect slots_13.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[13].brupdate.b2.uop.xcpt_pf_if
connect slots_13.io.brupdate.b2.uop.fp_typ, issue_slots[13].brupdate.b2.uop.fp_typ
connect slots_13.io.brupdate.b2.uop.fp_rm, issue_slots[13].brupdate.b2.uop.fp_rm
connect slots_13.io.brupdate.b2.uop.fp_val, issue_slots[13].brupdate.b2.uop.fp_val
connect slots_13.io.brupdate.b2.uop.fcn_op, issue_slots[13].brupdate.b2.uop.fcn_op
connect slots_13.io.brupdate.b2.uop.fcn_dw, issue_slots[13].brupdate.b2.uop.fcn_dw
connect slots_13.io.brupdate.b2.uop.frs3_en, issue_slots[13].brupdate.b2.uop.frs3_en
connect slots_13.io.brupdate.b2.uop.lrs2_rtype, issue_slots[13].brupdate.b2.uop.lrs2_rtype
connect slots_13.io.brupdate.b2.uop.lrs1_rtype, issue_slots[13].brupdate.b2.uop.lrs1_rtype
connect slots_13.io.brupdate.b2.uop.dst_rtype, issue_slots[13].brupdate.b2.uop.dst_rtype
connect slots_13.io.brupdate.b2.uop.lrs3, issue_slots[13].brupdate.b2.uop.lrs3
connect slots_13.io.brupdate.b2.uop.lrs2, issue_slots[13].brupdate.b2.uop.lrs2
connect slots_13.io.brupdate.b2.uop.lrs1, issue_slots[13].brupdate.b2.uop.lrs1
connect slots_13.io.brupdate.b2.uop.ldst, issue_slots[13].brupdate.b2.uop.ldst
connect slots_13.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[13].brupdate.b2.uop.ldst_is_rs1
connect slots_13.io.brupdate.b2.uop.csr_cmd, issue_slots[13].brupdate.b2.uop.csr_cmd
connect slots_13.io.brupdate.b2.uop.flush_on_commit, issue_slots[13].brupdate.b2.uop.flush_on_commit
connect slots_13.io.brupdate.b2.uop.is_unique, issue_slots[13].brupdate.b2.uop.is_unique
connect slots_13.io.brupdate.b2.uop.uses_stq, issue_slots[13].brupdate.b2.uop.uses_stq
connect slots_13.io.brupdate.b2.uop.uses_ldq, issue_slots[13].brupdate.b2.uop.uses_ldq
connect slots_13.io.brupdate.b2.uop.mem_signed, issue_slots[13].brupdate.b2.uop.mem_signed
connect slots_13.io.brupdate.b2.uop.mem_size, issue_slots[13].brupdate.b2.uop.mem_size
connect slots_13.io.brupdate.b2.uop.mem_cmd, issue_slots[13].brupdate.b2.uop.mem_cmd
connect slots_13.io.brupdate.b2.uop.exc_cause, issue_slots[13].brupdate.b2.uop.exc_cause
connect slots_13.io.brupdate.b2.uop.exception, issue_slots[13].brupdate.b2.uop.exception
connect slots_13.io.brupdate.b2.uop.stale_pdst, issue_slots[13].brupdate.b2.uop.stale_pdst
connect slots_13.io.brupdate.b2.uop.ppred_busy, issue_slots[13].brupdate.b2.uop.ppred_busy
connect slots_13.io.brupdate.b2.uop.prs3_busy, issue_slots[13].brupdate.b2.uop.prs3_busy
connect slots_13.io.brupdate.b2.uop.prs2_busy, issue_slots[13].brupdate.b2.uop.prs2_busy
connect slots_13.io.brupdate.b2.uop.prs1_busy, issue_slots[13].brupdate.b2.uop.prs1_busy
connect slots_13.io.brupdate.b2.uop.ppred, issue_slots[13].brupdate.b2.uop.ppred
connect slots_13.io.brupdate.b2.uop.prs3, issue_slots[13].brupdate.b2.uop.prs3
connect slots_13.io.brupdate.b2.uop.prs2, issue_slots[13].brupdate.b2.uop.prs2
connect slots_13.io.brupdate.b2.uop.prs1, issue_slots[13].brupdate.b2.uop.prs1
connect slots_13.io.brupdate.b2.uop.pdst, issue_slots[13].brupdate.b2.uop.pdst
connect slots_13.io.brupdate.b2.uop.rxq_idx, issue_slots[13].brupdate.b2.uop.rxq_idx
connect slots_13.io.brupdate.b2.uop.stq_idx, issue_slots[13].brupdate.b2.uop.stq_idx
connect slots_13.io.brupdate.b2.uop.ldq_idx, issue_slots[13].brupdate.b2.uop.ldq_idx
connect slots_13.io.brupdate.b2.uop.rob_idx, issue_slots[13].brupdate.b2.uop.rob_idx
connect slots_13.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[13].brupdate.b2.uop.fp_ctrl.vec
connect slots_13.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[13].brupdate.b2.uop.fp_ctrl.wflags
connect slots_13.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[13].brupdate.b2.uop.fp_ctrl.sqrt
connect slots_13.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[13].brupdate.b2.uop.fp_ctrl.div
connect slots_13.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[13].brupdate.b2.uop.fp_ctrl.fma
connect slots_13.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[13].brupdate.b2.uop.fp_ctrl.fastpipe
connect slots_13.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[13].brupdate.b2.uop.fp_ctrl.toint
connect slots_13.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[13].brupdate.b2.uop.fp_ctrl.fromint
connect slots_13.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[13].brupdate.b2.uop.fp_ctrl.typeTagOut
connect slots_13.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[13].brupdate.b2.uop.fp_ctrl.typeTagIn
connect slots_13.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[13].brupdate.b2.uop.fp_ctrl.swap23
connect slots_13.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[13].brupdate.b2.uop.fp_ctrl.swap12
connect slots_13.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[13].brupdate.b2.uop.fp_ctrl.ren3
connect slots_13.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[13].brupdate.b2.uop.fp_ctrl.ren2
connect slots_13.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[13].brupdate.b2.uop.fp_ctrl.ren1
connect slots_13.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[13].brupdate.b2.uop.fp_ctrl.wen
connect slots_13.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[13].brupdate.b2.uop.fp_ctrl.ldst
connect slots_13.io.brupdate.b2.uop.op2_sel, issue_slots[13].brupdate.b2.uop.op2_sel
connect slots_13.io.brupdate.b2.uop.op1_sel, issue_slots[13].brupdate.b2.uop.op1_sel
connect slots_13.io.brupdate.b2.uop.imm_packed, issue_slots[13].brupdate.b2.uop.imm_packed
connect slots_13.io.brupdate.b2.uop.pimm, issue_slots[13].brupdate.b2.uop.pimm
connect slots_13.io.brupdate.b2.uop.imm_sel, issue_slots[13].brupdate.b2.uop.imm_sel
connect slots_13.io.brupdate.b2.uop.imm_rename, issue_slots[13].brupdate.b2.uop.imm_rename
connect slots_13.io.brupdate.b2.uop.taken, issue_slots[13].brupdate.b2.uop.taken
connect slots_13.io.brupdate.b2.uop.pc_lob, issue_slots[13].brupdate.b2.uop.pc_lob
connect slots_13.io.brupdate.b2.uop.edge_inst, issue_slots[13].brupdate.b2.uop.edge_inst
connect slots_13.io.brupdate.b2.uop.ftq_idx, issue_slots[13].brupdate.b2.uop.ftq_idx
connect slots_13.io.brupdate.b2.uop.is_mov, issue_slots[13].brupdate.b2.uop.is_mov
connect slots_13.io.brupdate.b2.uop.is_rocc, issue_slots[13].brupdate.b2.uop.is_rocc
connect slots_13.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[13].brupdate.b2.uop.is_sys_pc2epc
connect slots_13.io.brupdate.b2.uop.is_eret, issue_slots[13].brupdate.b2.uop.is_eret
connect slots_13.io.brupdate.b2.uop.is_amo, issue_slots[13].brupdate.b2.uop.is_amo
connect slots_13.io.brupdate.b2.uop.is_sfence, issue_slots[13].brupdate.b2.uop.is_sfence
connect slots_13.io.brupdate.b2.uop.is_fencei, issue_slots[13].brupdate.b2.uop.is_fencei
connect slots_13.io.brupdate.b2.uop.is_fence, issue_slots[13].brupdate.b2.uop.is_fence
connect slots_13.io.brupdate.b2.uop.is_sfb, issue_slots[13].brupdate.b2.uop.is_sfb
connect slots_13.io.brupdate.b2.uop.br_type, issue_slots[13].brupdate.b2.uop.br_type
connect slots_13.io.brupdate.b2.uop.br_tag, issue_slots[13].brupdate.b2.uop.br_tag
connect slots_13.io.brupdate.b2.uop.br_mask, issue_slots[13].brupdate.b2.uop.br_mask
connect slots_13.io.brupdate.b2.uop.dis_col_sel, issue_slots[13].brupdate.b2.uop.dis_col_sel
connect slots_13.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[13].brupdate.b2.uop.iw_p3_bypass_hint
connect slots_13.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[13].brupdate.b2.uop.iw_p2_bypass_hint
connect slots_13.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[13].brupdate.b2.uop.iw_p1_bypass_hint
connect slots_13.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[13].brupdate.b2.uop.iw_p2_speculative_child
connect slots_13.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[13].brupdate.b2.uop.iw_p1_speculative_child
connect slots_13.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[13].brupdate.b2.uop.iw_issued_partial_dgen
connect slots_13.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[13].brupdate.b2.uop.iw_issued_partial_agen
connect slots_13.io.brupdate.b2.uop.iw_issued, issue_slots[13].brupdate.b2.uop.iw_issued
connect slots_13.io.brupdate.b2.uop.fu_code[0], issue_slots[13].brupdate.b2.uop.fu_code[0]
connect slots_13.io.brupdate.b2.uop.fu_code[1], issue_slots[13].brupdate.b2.uop.fu_code[1]
connect slots_13.io.brupdate.b2.uop.fu_code[2], issue_slots[13].brupdate.b2.uop.fu_code[2]
connect slots_13.io.brupdate.b2.uop.fu_code[3], issue_slots[13].brupdate.b2.uop.fu_code[3]
connect slots_13.io.brupdate.b2.uop.fu_code[4], issue_slots[13].brupdate.b2.uop.fu_code[4]
connect slots_13.io.brupdate.b2.uop.fu_code[5], issue_slots[13].brupdate.b2.uop.fu_code[5]
connect slots_13.io.brupdate.b2.uop.fu_code[6], issue_slots[13].brupdate.b2.uop.fu_code[6]
connect slots_13.io.brupdate.b2.uop.fu_code[7], issue_slots[13].brupdate.b2.uop.fu_code[7]
connect slots_13.io.brupdate.b2.uop.fu_code[8], issue_slots[13].brupdate.b2.uop.fu_code[8]
connect slots_13.io.brupdate.b2.uop.fu_code[9], issue_slots[13].brupdate.b2.uop.fu_code[9]
connect slots_13.io.brupdate.b2.uop.iq_type[0], issue_slots[13].brupdate.b2.uop.iq_type[0]
connect slots_13.io.brupdate.b2.uop.iq_type[1], issue_slots[13].brupdate.b2.uop.iq_type[1]
connect slots_13.io.brupdate.b2.uop.iq_type[2], issue_slots[13].brupdate.b2.uop.iq_type[2]
connect slots_13.io.brupdate.b2.uop.iq_type[3], issue_slots[13].brupdate.b2.uop.iq_type[3]
connect slots_13.io.brupdate.b2.uop.debug_pc, issue_slots[13].brupdate.b2.uop.debug_pc
connect slots_13.io.brupdate.b2.uop.is_rvc, issue_slots[13].brupdate.b2.uop.is_rvc
connect slots_13.io.brupdate.b2.uop.debug_inst, issue_slots[13].brupdate.b2.uop.debug_inst
connect slots_13.io.brupdate.b2.uop.inst, issue_slots[13].brupdate.b2.uop.inst
connect slots_13.io.brupdate.b1.mispredict_mask, issue_slots[13].brupdate.b1.mispredict_mask
connect slots_13.io.brupdate.b1.resolve_mask, issue_slots[13].brupdate.b1.resolve_mask
connect issue_slots[13].out_uop.debug_tsrc, slots_13.io.out_uop.debug_tsrc
connect issue_slots[13].out_uop.debug_fsrc, slots_13.io.out_uop.debug_fsrc
connect issue_slots[13].out_uop.bp_xcpt_if, slots_13.io.out_uop.bp_xcpt_if
connect issue_slots[13].out_uop.bp_debug_if, slots_13.io.out_uop.bp_debug_if
connect issue_slots[13].out_uop.xcpt_ma_if, slots_13.io.out_uop.xcpt_ma_if
connect issue_slots[13].out_uop.xcpt_ae_if, slots_13.io.out_uop.xcpt_ae_if
connect issue_slots[13].out_uop.xcpt_pf_if, slots_13.io.out_uop.xcpt_pf_if
connect issue_slots[13].out_uop.fp_typ, slots_13.io.out_uop.fp_typ
connect issue_slots[13].out_uop.fp_rm, slots_13.io.out_uop.fp_rm
connect issue_slots[13].out_uop.fp_val, slots_13.io.out_uop.fp_val
connect issue_slots[13].out_uop.fcn_op, slots_13.io.out_uop.fcn_op
connect issue_slots[13].out_uop.fcn_dw, slots_13.io.out_uop.fcn_dw
connect issue_slots[13].out_uop.frs3_en, slots_13.io.out_uop.frs3_en
connect issue_slots[13].out_uop.lrs2_rtype, slots_13.io.out_uop.lrs2_rtype
connect issue_slots[13].out_uop.lrs1_rtype, slots_13.io.out_uop.lrs1_rtype
connect issue_slots[13].out_uop.dst_rtype, slots_13.io.out_uop.dst_rtype
connect issue_slots[13].out_uop.lrs3, slots_13.io.out_uop.lrs3
connect issue_slots[13].out_uop.lrs2, slots_13.io.out_uop.lrs2
connect issue_slots[13].out_uop.lrs1, slots_13.io.out_uop.lrs1
connect issue_slots[13].out_uop.ldst, slots_13.io.out_uop.ldst
connect issue_slots[13].out_uop.ldst_is_rs1, slots_13.io.out_uop.ldst_is_rs1
connect issue_slots[13].out_uop.csr_cmd, slots_13.io.out_uop.csr_cmd
connect issue_slots[13].out_uop.flush_on_commit, slots_13.io.out_uop.flush_on_commit
connect issue_slots[13].out_uop.is_unique, slots_13.io.out_uop.is_unique
connect issue_slots[13].out_uop.uses_stq, slots_13.io.out_uop.uses_stq
connect issue_slots[13].out_uop.uses_ldq, slots_13.io.out_uop.uses_ldq
connect issue_slots[13].out_uop.mem_signed, slots_13.io.out_uop.mem_signed
connect issue_slots[13].out_uop.mem_size, slots_13.io.out_uop.mem_size
connect issue_slots[13].out_uop.mem_cmd, slots_13.io.out_uop.mem_cmd
connect issue_slots[13].out_uop.exc_cause, slots_13.io.out_uop.exc_cause
connect issue_slots[13].out_uop.exception, slots_13.io.out_uop.exception
connect issue_slots[13].out_uop.stale_pdst, slots_13.io.out_uop.stale_pdst
connect issue_slots[13].out_uop.ppred_busy, slots_13.io.out_uop.ppred_busy
connect issue_slots[13].out_uop.prs3_busy, slots_13.io.out_uop.prs3_busy
connect issue_slots[13].out_uop.prs2_busy, slots_13.io.out_uop.prs2_busy
connect issue_slots[13].out_uop.prs1_busy, slots_13.io.out_uop.prs1_busy
connect issue_slots[13].out_uop.ppred, slots_13.io.out_uop.ppred
connect issue_slots[13].out_uop.prs3, slots_13.io.out_uop.prs3
connect issue_slots[13].out_uop.prs2, slots_13.io.out_uop.prs2
connect issue_slots[13].out_uop.prs1, slots_13.io.out_uop.prs1
connect issue_slots[13].out_uop.pdst, slots_13.io.out_uop.pdst
connect issue_slots[13].out_uop.rxq_idx, slots_13.io.out_uop.rxq_idx
connect issue_slots[13].out_uop.stq_idx, slots_13.io.out_uop.stq_idx
connect issue_slots[13].out_uop.ldq_idx, slots_13.io.out_uop.ldq_idx
connect issue_slots[13].out_uop.rob_idx, slots_13.io.out_uop.rob_idx
connect issue_slots[13].out_uop.fp_ctrl.vec, slots_13.io.out_uop.fp_ctrl.vec
connect issue_slots[13].out_uop.fp_ctrl.wflags, slots_13.io.out_uop.fp_ctrl.wflags
connect issue_slots[13].out_uop.fp_ctrl.sqrt, slots_13.io.out_uop.fp_ctrl.sqrt
connect issue_slots[13].out_uop.fp_ctrl.div, slots_13.io.out_uop.fp_ctrl.div
connect issue_slots[13].out_uop.fp_ctrl.fma, slots_13.io.out_uop.fp_ctrl.fma
connect issue_slots[13].out_uop.fp_ctrl.fastpipe, slots_13.io.out_uop.fp_ctrl.fastpipe
connect issue_slots[13].out_uop.fp_ctrl.toint, slots_13.io.out_uop.fp_ctrl.toint
connect issue_slots[13].out_uop.fp_ctrl.fromint, slots_13.io.out_uop.fp_ctrl.fromint
connect issue_slots[13].out_uop.fp_ctrl.typeTagOut, slots_13.io.out_uop.fp_ctrl.typeTagOut
connect issue_slots[13].out_uop.fp_ctrl.typeTagIn, slots_13.io.out_uop.fp_ctrl.typeTagIn
connect issue_slots[13].out_uop.fp_ctrl.swap23, slots_13.io.out_uop.fp_ctrl.swap23
connect issue_slots[13].out_uop.fp_ctrl.swap12, slots_13.io.out_uop.fp_ctrl.swap12
connect issue_slots[13].out_uop.fp_ctrl.ren3, slots_13.io.out_uop.fp_ctrl.ren3
connect issue_slots[13].out_uop.fp_ctrl.ren2, slots_13.io.out_uop.fp_ctrl.ren2
connect issue_slots[13].out_uop.fp_ctrl.ren1, slots_13.io.out_uop.fp_ctrl.ren1
connect issue_slots[13].out_uop.fp_ctrl.wen, slots_13.io.out_uop.fp_ctrl.wen
connect issue_slots[13].out_uop.fp_ctrl.ldst, slots_13.io.out_uop.fp_ctrl.ldst
connect issue_slots[13].out_uop.op2_sel, slots_13.io.out_uop.op2_sel
connect issue_slots[13].out_uop.op1_sel, slots_13.io.out_uop.op1_sel
connect issue_slots[13].out_uop.imm_packed, slots_13.io.out_uop.imm_packed
connect issue_slots[13].out_uop.pimm, slots_13.io.out_uop.pimm
connect issue_slots[13].out_uop.imm_sel, slots_13.io.out_uop.imm_sel
connect issue_slots[13].out_uop.imm_rename, slots_13.io.out_uop.imm_rename
connect issue_slots[13].out_uop.taken, slots_13.io.out_uop.taken
connect issue_slots[13].out_uop.pc_lob, slots_13.io.out_uop.pc_lob
connect issue_slots[13].out_uop.edge_inst, slots_13.io.out_uop.edge_inst
connect issue_slots[13].out_uop.ftq_idx, slots_13.io.out_uop.ftq_idx
connect issue_slots[13].out_uop.is_mov, slots_13.io.out_uop.is_mov
connect issue_slots[13].out_uop.is_rocc, slots_13.io.out_uop.is_rocc
connect issue_slots[13].out_uop.is_sys_pc2epc, slots_13.io.out_uop.is_sys_pc2epc
connect issue_slots[13].out_uop.is_eret, slots_13.io.out_uop.is_eret
connect issue_slots[13].out_uop.is_amo, slots_13.io.out_uop.is_amo
connect issue_slots[13].out_uop.is_sfence, slots_13.io.out_uop.is_sfence
connect issue_slots[13].out_uop.is_fencei, slots_13.io.out_uop.is_fencei
connect issue_slots[13].out_uop.is_fence, slots_13.io.out_uop.is_fence
connect issue_slots[13].out_uop.is_sfb, slots_13.io.out_uop.is_sfb
connect issue_slots[13].out_uop.br_type, slots_13.io.out_uop.br_type
connect issue_slots[13].out_uop.br_tag, slots_13.io.out_uop.br_tag
connect issue_slots[13].out_uop.br_mask, slots_13.io.out_uop.br_mask
connect issue_slots[13].out_uop.dis_col_sel, slots_13.io.out_uop.dis_col_sel
connect issue_slots[13].out_uop.iw_p3_bypass_hint, slots_13.io.out_uop.iw_p3_bypass_hint
connect issue_slots[13].out_uop.iw_p2_bypass_hint, slots_13.io.out_uop.iw_p2_bypass_hint
connect issue_slots[13].out_uop.iw_p1_bypass_hint, slots_13.io.out_uop.iw_p1_bypass_hint
connect issue_slots[13].out_uop.iw_p2_speculative_child, slots_13.io.out_uop.iw_p2_speculative_child
connect issue_slots[13].out_uop.iw_p1_speculative_child, slots_13.io.out_uop.iw_p1_speculative_child
connect issue_slots[13].out_uop.iw_issued_partial_dgen, slots_13.io.out_uop.iw_issued_partial_dgen
connect issue_slots[13].out_uop.iw_issued_partial_agen, slots_13.io.out_uop.iw_issued_partial_agen
connect issue_slots[13].out_uop.iw_issued, slots_13.io.out_uop.iw_issued
connect issue_slots[13].out_uop.fu_code[0], slots_13.io.out_uop.fu_code[0]
connect issue_slots[13].out_uop.fu_code[1], slots_13.io.out_uop.fu_code[1]
connect issue_slots[13].out_uop.fu_code[2], slots_13.io.out_uop.fu_code[2]
connect issue_slots[13].out_uop.fu_code[3], slots_13.io.out_uop.fu_code[3]
connect issue_slots[13].out_uop.fu_code[4], slots_13.io.out_uop.fu_code[4]
connect issue_slots[13].out_uop.fu_code[5], slots_13.io.out_uop.fu_code[5]
connect issue_slots[13].out_uop.fu_code[6], slots_13.io.out_uop.fu_code[6]
connect issue_slots[13].out_uop.fu_code[7], slots_13.io.out_uop.fu_code[7]
connect issue_slots[13].out_uop.fu_code[8], slots_13.io.out_uop.fu_code[8]
connect issue_slots[13].out_uop.fu_code[9], slots_13.io.out_uop.fu_code[9]
connect issue_slots[13].out_uop.iq_type[0], slots_13.io.out_uop.iq_type[0]
connect issue_slots[13].out_uop.iq_type[1], slots_13.io.out_uop.iq_type[1]
connect issue_slots[13].out_uop.iq_type[2], slots_13.io.out_uop.iq_type[2]
connect issue_slots[13].out_uop.iq_type[3], slots_13.io.out_uop.iq_type[3]
connect issue_slots[13].out_uop.debug_pc, slots_13.io.out_uop.debug_pc
connect issue_slots[13].out_uop.is_rvc, slots_13.io.out_uop.is_rvc
connect issue_slots[13].out_uop.debug_inst, slots_13.io.out_uop.debug_inst
connect issue_slots[13].out_uop.inst, slots_13.io.out_uop.inst
connect slots_13.io.in_uop.bits.debug_tsrc, issue_slots[13].in_uop.bits.debug_tsrc
connect slots_13.io.in_uop.bits.debug_fsrc, issue_slots[13].in_uop.bits.debug_fsrc
connect slots_13.io.in_uop.bits.bp_xcpt_if, issue_slots[13].in_uop.bits.bp_xcpt_if
connect slots_13.io.in_uop.bits.bp_debug_if, issue_slots[13].in_uop.bits.bp_debug_if
connect slots_13.io.in_uop.bits.xcpt_ma_if, issue_slots[13].in_uop.bits.xcpt_ma_if
connect slots_13.io.in_uop.bits.xcpt_ae_if, issue_slots[13].in_uop.bits.xcpt_ae_if
connect slots_13.io.in_uop.bits.xcpt_pf_if, issue_slots[13].in_uop.bits.xcpt_pf_if
connect slots_13.io.in_uop.bits.fp_typ, issue_slots[13].in_uop.bits.fp_typ
connect slots_13.io.in_uop.bits.fp_rm, issue_slots[13].in_uop.bits.fp_rm
connect slots_13.io.in_uop.bits.fp_val, issue_slots[13].in_uop.bits.fp_val
connect slots_13.io.in_uop.bits.fcn_op, issue_slots[13].in_uop.bits.fcn_op
connect slots_13.io.in_uop.bits.fcn_dw, issue_slots[13].in_uop.bits.fcn_dw
connect slots_13.io.in_uop.bits.frs3_en, issue_slots[13].in_uop.bits.frs3_en
connect slots_13.io.in_uop.bits.lrs2_rtype, issue_slots[13].in_uop.bits.lrs2_rtype
connect slots_13.io.in_uop.bits.lrs1_rtype, issue_slots[13].in_uop.bits.lrs1_rtype
connect slots_13.io.in_uop.bits.dst_rtype, issue_slots[13].in_uop.bits.dst_rtype
connect slots_13.io.in_uop.bits.lrs3, issue_slots[13].in_uop.bits.lrs3
connect slots_13.io.in_uop.bits.lrs2, issue_slots[13].in_uop.bits.lrs2
connect slots_13.io.in_uop.bits.lrs1, issue_slots[13].in_uop.bits.lrs1
connect slots_13.io.in_uop.bits.ldst, issue_slots[13].in_uop.bits.ldst
connect slots_13.io.in_uop.bits.ldst_is_rs1, issue_slots[13].in_uop.bits.ldst_is_rs1
connect slots_13.io.in_uop.bits.csr_cmd, issue_slots[13].in_uop.bits.csr_cmd
connect slots_13.io.in_uop.bits.flush_on_commit, issue_slots[13].in_uop.bits.flush_on_commit
connect slots_13.io.in_uop.bits.is_unique, issue_slots[13].in_uop.bits.is_unique
connect slots_13.io.in_uop.bits.uses_stq, issue_slots[13].in_uop.bits.uses_stq
connect slots_13.io.in_uop.bits.uses_ldq, issue_slots[13].in_uop.bits.uses_ldq
connect slots_13.io.in_uop.bits.mem_signed, issue_slots[13].in_uop.bits.mem_signed
connect slots_13.io.in_uop.bits.mem_size, issue_slots[13].in_uop.bits.mem_size
connect slots_13.io.in_uop.bits.mem_cmd, issue_slots[13].in_uop.bits.mem_cmd
connect slots_13.io.in_uop.bits.exc_cause, issue_slots[13].in_uop.bits.exc_cause
connect slots_13.io.in_uop.bits.exception, issue_slots[13].in_uop.bits.exception
connect slots_13.io.in_uop.bits.stale_pdst, issue_slots[13].in_uop.bits.stale_pdst
connect slots_13.io.in_uop.bits.ppred_busy, issue_slots[13].in_uop.bits.ppred_busy
connect slots_13.io.in_uop.bits.prs3_busy, issue_slots[13].in_uop.bits.prs3_busy
connect slots_13.io.in_uop.bits.prs2_busy, issue_slots[13].in_uop.bits.prs2_busy
connect slots_13.io.in_uop.bits.prs1_busy, issue_slots[13].in_uop.bits.prs1_busy
connect slots_13.io.in_uop.bits.ppred, issue_slots[13].in_uop.bits.ppred
connect slots_13.io.in_uop.bits.prs3, issue_slots[13].in_uop.bits.prs3
connect slots_13.io.in_uop.bits.prs2, issue_slots[13].in_uop.bits.prs2
connect slots_13.io.in_uop.bits.prs1, issue_slots[13].in_uop.bits.prs1
connect slots_13.io.in_uop.bits.pdst, issue_slots[13].in_uop.bits.pdst
connect slots_13.io.in_uop.bits.rxq_idx, issue_slots[13].in_uop.bits.rxq_idx
connect slots_13.io.in_uop.bits.stq_idx, issue_slots[13].in_uop.bits.stq_idx
connect slots_13.io.in_uop.bits.ldq_idx, issue_slots[13].in_uop.bits.ldq_idx
connect slots_13.io.in_uop.bits.rob_idx, issue_slots[13].in_uop.bits.rob_idx
connect slots_13.io.in_uop.bits.fp_ctrl.vec, issue_slots[13].in_uop.bits.fp_ctrl.vec
connect slots_13.io.in_uop.bits.fp_ctrl.wflags, issue_slots[13].in_uop.bits.fp_ctrl.wflags
connect slots_13.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[13].in_uop.bits.fp_ctrl.sqrt
connect slots_13.io.in_uop.bits.fp_ctrl.div, issue_slots[13].in_uop.bits.fp_ctrl.div
connect slots_13.io.in_uop.bits.fp_ctrl.fma, issue_slots[13].in_uop.bits.fp_ctrl.fma
connect slots_13.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[13].in_uop.bits.fp_ctrl.fastpipe
connect slots_13.io.in_uop.bits.fp_ctrl.toint, issue_slots[13].in_uop.bits.fp_ctrl.toint
connect slots_13.io.in_uop.bits.fp_ctrl.fromint, issue_slots[13].in_uop.bits.fp_ctrl.fromint
connect slots_13.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[13].in_uop.bits.fp_ctrl.typeTagOut
connect slots_13.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[13].in_uop.bits.fp_ctrl.typeTagIn
connect slots_13.io.in_uop.bits.fp_ctrl.swap23, issue_slots[13].in_uop.bits.fp_ctrl.swap23
connect slots_13.io.in_uop.bits.fp_ctrl.swap12, issue_slots[13].in_uop.bits.fp_ctrl.swap12
connect slots_13.io.in_uop.bits.fp_ctrl.ren3, issue_slots[13].in_uop.bits.fp_ctrl.ren3
connect slots_13.io.in_uop.bits.fp_ctrl.ren2, issue_slots[13].in_uop.bits.fp_ctrl.ren2
connect slots_13.io.in_uop.bits.fp_ctrl.ren1, issue_slots[13].in_uop.bits.fp_ctrl.ren1
connect slots_13.io.in_uop.bits.fp_ctrl.wen, issue_slots[13].in_uop.bits.fp_ctrl.wen
connect slots_13.io.in_uop.bits.fp_ctrl.ldst, issue_slots[13].in_uop.bits.fp_ctrl.ldst
connect slots_13.io.in_uop.bits.op2_sel, issue_slots[13].in_uop.bits.op2_sel
connect slots_13.io.in_uop.bits.op1_sel, issue_slots[13].in_uop.bits.op1_sel
connect slots_13.io.in_uop.bits.imm_packed, issue_slots[13].in_uop.bits.imm_packed
connect slots_13.io.in_uop.bits.pimm, issue_slots[13].in_uop.bits.pimm
connect slots_13.io.in_uop.bits.imm_sel, issue_slots[13].in_uop.bits.imm_sel
connect slots_13.io.in_uop.bits.imm_rename, issue_slots[13].in_uop.bits.imm_rename
connect slots_13.io.in_uop.bits.taken, issue_slots[13].in_uop.bits.taken
connect slots_13.io.in_uop.bits.pc_lob, issue_slots[13].in_uop.bits.pc_lob
connect slots_13.io.in_uop.bits.edge_inst, issue_slots[13].in_uop.bits.edge_inst
connect slots_13.io.in_uop.bits.ftq_idx, issue_slots[13].in_uop.bits.ftq_idx
connect slots_13.io.in_uop.bits.is_mov, issue_slots[13].in_uop.bits.is_mov
connect slots_13.io.in_uop.bits.is_rocc, issue_slots[13].in_uop.bits.is_rocc
connect slots_13.io.in_uop.bits.is_sys_pc2epc, issue_slots[13].in_uop.bits.is_sys_pc2epc
connect slots_13.io.in_uop.bits.is_eret, issue_slots[13].in_uop.bits.is_eret
connect slots_13.io.in_uop.bits.is_amo, issue_slots[13].in_uop.bits.is_amo
connect slots_13.io.in_uop.bits.is_sfence, issue_slots[13].in_uop.bits.is_sfence
connect slots_13.io.in_uop.bits.is_fencei, issue_slots[13].in_uop.bits.is_fencei
connect slots_13.io.in_uop.bits.is_fence, issue_slots[13].in_uop.bits.is_fence
connect slots_13.io.in_uop.bits.is_sfb, issue_slots[13].in_uop.bits.is_sfb
connect slots_13.io.in_uop.bits.br_type, issue_slots[13].in_uop.bits.br_type
connect slots_13.io.in_uop.bits.br_tag, issue_slots[13].in_uop.bits.br_tag
connect slots_13.io.in_uop.bits.br_mask, issue_slots[13].in_uop.bits.br_mask
connect slots_13.io.in_uop.bits.dis_col_sel, issue_slots[13].in_uop.bits.dis_col_sel
connect slots_13.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[13].in_uop.bits.iw_p3_bypass_hint
connect slots_13.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[13].in_uop.bits.iw_p2_bypass_hint
connect slots_13.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[13].in_uop.bits.iw_p1_bypass_hint
connect slots_13.io.in_uop.bits.iw_p2_speculative_child, issue_slots[13].in_uop.bits.iw_p2_speculative_child
connect slots_13.io.in_uop.bits.iw_p1_speculative_child, issue_slots[13].in_uop.bits.iw_p1_speculative_child
connect slots_13.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[13].in_uop.bits.iw_issued_partial_dgen
connect slots_13.io.in_uop.bits.iw_issued_partial_agen, issue_slots[13].in_uop.bits.iw_issued_partial_agen
connect slots_13.io.in_uop.bits.iw_issued, issue_slots[13].in_uop.bits.iw_issued
connect slots_13.io.in_uop.bits.fu_code[0], issue_slots[13].in_uop.bits.fu_code[0]
connect slots_13.io.in_uop.bits.fu_code[1], issue_slots[13].in_uop.bits.fu_code[1]
connect slots_13.io.in_uop.bits.fu_code[2], issue_slots[13].in_uop.bits.fu_code[2]
connect slots_13.io.in_uop.bits.fu_code[3], issue_slots[13].in_uop.bits.fu_code[3]
connect slots_13.io.in_uop.bits.fu_code[4], issue_slots[13].in_uop.bits.fu_code[4]
connect slots_13.io.in_uop.bits.fu_code[5], issue_slots[13].in_uop.bits.fu_code[5]
connect slots_13.io.in_uop.bits.fu_code[6], issue_slots[13].in_uop.bits.fu_code[6]
connect slots_13.io.in_uop.bits.fu_code[7], issue_slots[13].in_uop.bits.fu_code[7]
connect slots_13.io.in_uop.bits.fu_code[8], issue_slots[13].in_uop.bits.fu_code[8]
connect slots_13.io.in_uop.bits.fu_code[9], issue_slots[13].in_uop.bits.fu_code[9]
connect slots_13.io.in_uop.bits.iq_type[0], issue_slots[13].in_uop.bits.iq_type[0]
connect slots_13.io.in_uop.bits.iq_type[1], issue_slots[13].in_uop.bits.iq_type[1]
connect slots_13.io.in_uop.bits.iq_type[2], issue_slots[13].in_uop.bits.iq_type[2]
connect slots_13.io.in_uop.bits.iq_type[3], issue_slots[13].in_uop.bits.iq_type[3]
connect slots_13.io.in_uop.bits.debug_pc, issue_slots[13].in_uop.bits.debug_pc
connect slots_13.io.in_uop.bits.is_rvc, issue_slots[13].in_uop.bits.is_rvc
connect slots_13.io.in_uop.bits.debug_inst, issue_slots[13].in_uop.bits.debug_inst
connect slots_13.io.in_uop.bits.inst, issue_slots[13].in_uop.bits.inst
connect slots_13.io.in_uop.valid, issue_slots[13].in_uop.valid
connect issue_slots[13].iss_uop.debug_tsrc, slots_13.io.iss_uop.debug_tsrc
connect issue_slots[13].iss_uop.debug_fsrc, slots_13.io.iss_uop.debug_fsrc
connect issue_slots[13].iss_uop.bp_xcpt_if, slots_13.io.iss_uop.bp_xcpt_if
connect issue_slots[13].iss_uop.bp_debug_if, slots_13.io.iss_uop.bp_debug_if
connect issue_slots[13].iss_uop.xcpt_ma_if, slots_13.io.iss_uop.xcpt_ma_if
connect issue_slots[13].iss_uop.xcpt_ae_if, slots_13.io.iss_uop.xcpt_ae_if
connect issue_slots[13].iss_uop.xcpt_pf_if, slots_13.io.iss_uop.xcpt_pf_if
connect issue_slots[13].iss_uop.fp_typ, slots_13.io.iss_uop.fp_typ
connect issue_slots[13].iss_uop.fp_rm, slots_13.io.iss_uop.fp_rm
connect issue_slots[13].iss_uop.fp_val, slots_13.io.iss_uop.fp_val
connect issue_slots[13].iss_uop.fcn_op, slots_13.io.iss_uop.fcn_op
connect issue_slots[13].iss_uop.fcn_dw, slots_13.io.iss_uop.fcn_dw
connect issue_slots[13].iss_uop.frs3_en, slots_13.io.iss_uop.frs3_en
connect issue_slots[13].iss_uop.lrs2_rtype, slots_13.io.iss_uop.lrs2_rtype
connect issue_slots[13].iss_uop.lrs1_rtype, slots_13.io.iss_uop.lrs1_rtype
connect issue_slots[13].iss_uop.dst_rtype, slots_13.io.iss_uop.dst_rtype
connect issue_slots[13].iss_uop.lrs3, slots_13.io.iss_uop.lrs3
connect issue_slots[13].iss_uop.lrs2, slots_13.io.iss_uop.lrs2
connect issue_slots[13].iss_uop.lrs1, slots_13.io.iss_uop.lrs1
connect issue_slots[13].iss_uop.ldst, slots_13.io.iss_uop.ldst
connect issue_slots[13].iss_uop.ldst_is_rs1, slots_13.io.iss_uop.ldst_is_rs1
connect issue_slots[13].iss_uop.csr_cmd, slots_13.io.iss_uop.csr_cmd
connect issue_slots[13].iss_uop.flush_on_commit, slots_13.io.iss_uop.flush_on_commit
connect issue_slots[13].iss_uop.is_unique, slots_13.io.iss_uop.is_unique
connect issue_slots[13].iss_uop.uses_stq, slots_13.io.iss_uop.uses_stq
connect issue_slots[13].iss_uop.uses_ldq, slots_13.io.iss_uop.uses_ldq
connect issue_slots[13].iss_uop.mem_signed, slots_13.io.iss_uop.mem_signed
connect issue_slots[13].iss_uop.mem_size, slots_13.io.iss_uop.mem_size
connect issue_slots[13].iss_uop.mem_cmd, slots_13.io.iss_uop.mem_cmd
connect issue_slots[13].iss_uop.exc_cause, slots_13.io.iss_uop.exc_cause
connect issue_slots[13].iss_uop.exception, slots_13.io.iss_uop.exception
connect issue_slots[13].iss_uop.stale_pdst, slots_13.io.iss_uop.stale_pdst
connect issue_slots[13].iss_uop.ppred_busy, slots_13.io.iss_uop.ppred_busy
connect issue_slots[13].iss_uop.prs3_busy, slots_13.io.iss_uop.prs3_busy
connect issue_slots[13].iss_uop.prs2_busy, slots_13.io.iss_uop.prs2_busy
connect issue_slots[13].iss_uop.prs1_busy, slots_13.io.iss_uop.prs1_busy
connect issue_slots[13].iss_uop.ppred, slots_13.io.iss_uop.ppred
connect issue_slots[13].iss_uop.prs3, slots_13.io.iss_uop.prs3
connect issue_slots[13].iss_uop.prs2, slots_13.io.iss_uop.prs2
connect issue_slots[13].iss_uop.prs1, slots_13.io.iss_uop.prs1
connect issue_slots[13].iss_uop.pdst, slots_13.io.iss_uop.pdst
connect issue_slots[13].iss_uop.rxq_idx, slots_13.io.iss_uop.rxq_idx
connect issue_slots[13].iss_uop.stq_idx, slots_13.io.iss_uop.stq_idx
connect issue_slots[13].iss_uop.ldq_idx, slots_13.io.iss_uop.ldq_idx
connect issue_slots[13].iss_uop.rob_idx, slots_13.io.iss_uop.rob_idx
connect issue_slots[13].iss_uop.fp_ctrl.vec, slots_13.io.iss_uop.fp_ctrl.vec
connect issue_slots[13].iss_uop.fp_ctrl.wflags, slots_13.io.iss_uop.fp_ctrl.wflags
connect issue_slots[13].iss_uop.fp_ctrl.sqrt, slots_13.io.iss_uop.fp_ctrl.sqrt
connect issue_slots[13].iss_uop.fp_ctrl.div, slots_13.io.iss_uop.fp_ctrl.div
connect issue_slots[13].iss_uop.fp_ctrl.fma, slots_13.io.iss_uop.fp_ctrl.fma
connect issue_slots[13].iss_uop.fp_ctrl.fastpipe, slots_13.io.iss_uop.fp_ctrl.fastpipe
connect issue_slots[13].iss_uop.fp_ctrl.toint, slots_13.io.iss_uop.fp_ctrl.toint
connect issue_slots[13].iss_uop.fp_ctrl.fromint, slots_13.io.iss_uop.fp_ctrl.fromint
connect issue_slots[13].iss_uop.fp_ctrl.typeTagOut, slots_13.io.iss_uop.fp_ctrl.typeTagOut
connect issue_slots[13].iss_uop.fp_ctrl.typeTagIn, slots_13.io.iss_uop.fp_ctrl.typeTagIn
connect issue_slots[13].iss_uop.fp_ctrl.swap23, slots_13.io.iss_uop.fp_ctrl.swap23
connect issue_slots[13].iss_uop.fp_ctrl.swap12, slots_13.io.iss_uop.fp_ctrl.swap12
connect issue_slots[13].iss_uop.fp_ctrl.ren3, slots_13.io.iss_uop.fp_ctrl.ren3
connect issue_slots[13].iss_uop.fp_ctrl.ren2, slots_13.io.iss_uop.fp_ctrl.ren2
connect issue_slots[13].iss_uop.fp_ctrl.ren1, slots_13.io.iss_uop.fp_ctrl.ren1
connect issue_slots[13].iss_uop.fp_ctrl.wen, slots_13.io.iss_uop.fp_ctrl.wen
connect issue_slots[13].iss_uop.fp_ctrl.ldst, slots_13.io.iss_uop.fp_ctrl.ldst
connect issue_slots[13].iss_uop.op2_sel, slots_13.io.iss_uop.op2_sel
connect issue_slots[13].iss_uop.op1_sel, slots_13.io.iss_uop.op1_sel
connect issue_slots[13].iss_uop.imm_packed, slots_13.io.iss_uop.imm_packed
connect issue_slots[13].iss_uop.pimm, slots_13.io.iss_uop.pimm
connect issue_slots[13].iss_uop.imm_sel, slots_13.io.iss_uop.imm_sel
connect issue_slots[13].iss_uop.imm_rename, slots_13.io.iss_uop.imm_rename
connect issue_slots[13].iss_uop.taken, slots_13.io.iss_uop.taken
connect issue_slots[13].iss_uop.pc_lob, slots_13.io.iss_uop.pc_lob
connect issue_slots[13].iss_uop.edge_inst, slots_13.io.iss_uop.edge_inst
connect issue_slots[13].iss_uop.ftq_idx, slots_13.io.iss_uop.ftq_idx
connect issue_slots[13].iss_uop.is_mov, slots_13.io.iss_uop.is_mov
connect issue_slots[13].iss_uop.is_rocc, slots_13.io.iss_uop.is_rocc
connect issue_slots[13].iss_uop.is_sys_pc2epc, slots_13.io.iss_uop.is_sys_pc2epc
connect issue_slots[13].iss_uop.is_eret, slots_13.io.iss_uop.is_eret
connect issue_slots[13].iss_uop.is_amo, slots_13.io.iss_uop.is_amo
connect issue_slots[13].iss_uop.is_sfence, slots_13.io.iss_uop.is_sfence
connect issue_slots[13].iss_uop.is_fencei, slots_13.io.iss_uop.is_fencei
connect issue_slots[13].iss_uop.is_fence, slots_13.io.iss_uop.is_fence
connect issue_slots[13].iss_uop.is_sfb, slots_13.io.iss_uop.is_sfb
connect issue_slots[13].iss_uop.br_type, slots_13.io.iss_uop.br_type
connect issue_slots[13].iss_uop.br_tag, slots_13.io.iss_uop.br_tag
connect issue_slots[13].iss_uop.br_mask, slots_13.io.iss_uop.br_mask
connect issue_slots[13].iss_uop.dis_col_sel, slots_13.io.iss_uop.dis_col_sel
connect issue_slots[13].iss_uop.iw_p3_bypass_hint, slots_13.io.iss_uop.iw_p3_bypass_hint
connect issue_slots[13].iss_uop.iw_p2_bypass_hint, slots_13.io.iss_uop.iw_p2_bypass_hint
connect issue_slots[13].iss_uop.iw_p1_bypass_hint, slots_13.io.iss_uop.iw_p1_bypass_hint
connect issue_slots[13].iss_uop.iw_p2_speculative_child, slots_13.io.iss_uop.iw_p2_speculative_child
connect issue_slots[13].iss_uop.iw_p1_speculative_child, slots_13.io.iss_uop.iw_p1_speculative_child
connect issue_slots[13].iss_uop.iw_issued_partial_dgen, slots_13.io.iss_uop.iw_issued_partial_dgen
connect issue_slots[13].iss_uop.iw_issued_partial_agen, slots_13.io.iss_uop.iw_issued_partial_agen
connect issue_slots[13].iss_uop.iw_issued, slots_13.io.iss_uop.iw_issued
connect issue_slots[13].iss_uop.fu_code[0], slots_13.io.iss_uop.fu_code[0]
connect issue_slots[13].iss_uop.fu_code[1], slots_13.io.iss_uop.fu_code[1]
connect issue_slots[13].iss_uop.fu_code[2], slots_13.io.iss_uop.fu_code[2]
connect issue_slots[13].iss_uop.fu_code[3], slots_13.io.iss_uop.fu_code[3]
connect issue_slots[13].iss_uop.fu_code[4], slots_13.io.iss_uop.fu_code[4]
connect issue_slots[13].iss_uop.fu_code[5], slots_13.io.iss_uop.fu_code[5]
connect issue_slots[13].iss_uop.fu_code[6], slots_13.io.iss_uop.fu_code[6]
connect issue_slots[13].iss_uop.fu_code[7], slots_13.io.iss_uop.fu_code[7]
connect issue_slots[13].iss_uop.fu_code[8], slots_13.io.iss_uop.fu_code[8]
connect issue_slots[13].iss_uop.fu_code[9], slots_13.io.iss_uop.fu_code[9]
connect issue_slots[13].iss_uop.iq_type[0], slots_13.io.iss_uop.iq_type[0]
connect issue_slots[13].iss_uop.iq_type[1], slots_13.io.iss_uop.iq_type[1]
connect issue_slots[13].iss_uop.iq_type[2], slots_13.io.iss_uop.iq_type[2]
connect issue_slots[13].iss_uop.iq_type[3], slots_13.io.iss_uop.iq_type[3]
connect issue_slots[13].iss_uop.debug_pc, slots_13.io.iss_uop.debug_pc
connect issue_slots[13].iss_uop.is_rvc, slots_13.io.iss_uop.is_rvc
connect issue_slots[13].iss_uop.debug_inst, slots_13.io.iss_uop.debug_inst
connect issue_slots[13].iss_uop.inst, slots_13.io.iss_uop.inst
connect slots_13.io.grant, issue_slots[13].grant
connect issue_slots[13].request, slots_13.io.request
connect issue_slots[13].will_be_valid, slots_13.io.will_be_valid
connect issue_slots[13].valid, slots_13.io.valid
connect slots_14.io.child_rebusys, issue_slots[14].child_rebusys
connect slots_14.io.pred_wakeup_port.bits, issue_slots[14].pred_wakeup_port.bits
connect slots_14.io.pred_wakeup_port.valid, issue_slots[14].pred_wakeup_port.valid
connect slots_14.io.wakeup_ports[0].bits.rebusy, issue_slots[14].wakeup_ports[0].bits.rebusy
connect slots_14.io.wakeup_ports[0].bits.speculative_mask, issue_slots[14].wakeup_ports[0].bits.speculative_mask
connect slots_14.io.wakeup_ports[0].bits.bypassable, issue_slots[14].wakeup_ports[0].bits.bypassable
connect slots_14.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[14].wakeup_ports[0].bits.uop.debug_tsrc
connect slots_14.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[14].wakeup_ports[0].bits.uop.debug_fsrc
connect slots_14.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[14].wakeup_ports[0].bits.uop.bp_xcpt_if
connect slots_14.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[14].wakeup_ports[0].bits.uop.bp_debug_if
connect slots_14.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[14].wakeup_ports[0].bits.uop.xcpt_ma_if
connect slots_14.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[14].wakeup_ports[0].bits.uop.xcpt_ae_if
connect slots_14.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[14].wakeup_ports[0].bits.uop.xcpt_pf_if
connect slots_14.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[14].wakeup_ports[0].bits.uop.fp_typ
connect slots_14.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[14].wakeup_ports[0].bits.uop.fp_rm
connect slots_14.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[14].wakeup_ports[0].bits.uop.fp_val
connect slots_14.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[14].wakeup_ports[0].bits.uop.fcn_op
connect slots_14.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[14].wakeup_ports[0].bits.uop.fcn_dw
connect slots_14.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[14].wakeup_ports[0].bits.uop.frs3_en
connect slots_14.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[14].wakeup_ports[0].bits.uop.lrs2_rtype
connect slots_14.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[14].wakeup_ports[0].bits.uop.lrs1_rtype
connect slots_14.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[14].wakeup_ports[0].bits.uop.dst_rtype
connect slots_14.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[14].wakeup_ports[0].bits.uop.lrs3
connect slots_14.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[14].wakeup_ports[0].bits.uop.lrs2
connect slots_14.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[14].wakeup_ports[0].bits.uop.lrs1
connect slots_14.io.wakeup_ports[0].bits.uop.ldst, issue_slots[14].wakeup_ports[0].bits.uop.ldst
connect slots_14.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[14].wakeup_ports[0].bits.uop.ldst_is_rs1
connect slots_14.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[14].wakeup_ports[0].bits.uop.csr_cmd
connect slots_14.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[14].wakeup_ports[0].bits.uop.flush_on_commit
connect slots_14.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[14].wakeup_ports[0].bits.uop.is_unique
connect slots_14.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[14].wakeup_ports[0].bits.uop.uses_stq
connect slots_14.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[14].wakeup_ports[0].bits.uop.uses_ldq
connect slots_14.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[14].wakeup_ports[0].bits.uop.mem_signed
connect slots_14.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[14].wakeup_ports[0].bits.uop.mem_size
connect slots_14.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[14].wakeup_ports[0].bits.uop.mem_cmd
connect slots_14.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[14].wakeup_ports[0].bits.uop.exc_cause
connect slots_14.io.wakeup_ports[0].bits.uop.exception, issue_slots[14].wakeup_ports[0].bits.uop.exception
connect slots_14.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[14].wakeup_ports[0].bits.uop.stale_pdst
connect slots_14.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[14].wakeup_ports[0].bits.uop.ppred_busy
connect slots_14.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[14].wakeup_ports[0].bits.uop.prs3_busy
connect slots_14.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[14].wakeup_ports[0].bits.uop.prs2_busy
connect slots_14.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[14].wakeup_ports[0].bits.uop.prs1_busy
connect slots_14.io.wakeup_ports[0].bits.uop.ppred, issue_slots[14].wakeup_ports[0].bits.uop.ppred
connect slots_14.io.wakeup_ports[0].bits.uop.prs3, issue_slots[14].wakeup_ports[0].bits.uop.prs3
connect slots_14.io.wakeup_ports[0].bits.uop.prs2, issue_slots[14].wakeup_ports[0].bits.uop.prs2
connect slots_14.io.wakeup_ports[0].bits.uop.prs1, issue_slots[14].wakeup_ports[0].bits.uop.prs1
connect slots_14.io.wakeup_ports[0].bits.uop.pdst, issue_slots[14].wakeup_ports[0].bits.uop.pdst
connect slots_14.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[14].wakeup_ports[0].bits.uop.rxq_idx
connect slots_14.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[14].wakeup_ports[0].bits.uop.stq_idx
connect slots_14.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[14].wakeup_ports[0].bits.uop.ldq_idx
connect slots_14.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[14].wakeup_ports[0].bits.uop.rob_idx
connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.vec
connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.wflags
connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.sqrt
connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.div
connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.fma
connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe
connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.toint
connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.fromint
connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut
connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn
connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.swap23
connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.swap12
connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.ren3
connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.ren2
connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.ren1
connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.wen
connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.ldst
connect slots_14.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[14].wakeup_ports[0].bits.uop.op2_sel
connect slots_14.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[14].wakeup_ports[0].bits.uop.op1_sel
connect slots_14.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[14].wakeup_ports[0].bits.uop.imm_packed
connect slots_14.io.wakeup_ports[0].bits.uop.pimm, issue_slots[14].wakeup_ports[0].bits.uop.pimm
connect slots_14.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[14].wakeup_ports[0].bits.uop.imm_sel
connect slots_14.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[14].wakeup_ports[0].bits.uop.imm_rename
connect slots_14.io.wakeup_ports[0].bits.uop.taken, issue_slots[14].wakeup_ports[0].bits.uop.taken
connect slots_14.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[14].wakeup_ports[0].bits.uop.pc_lob
connect slots_14.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[14].wakeup_ports[0].bits.uop.edge_inst
connect slots_14.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[14].wakeup_ports[0].bits.uop.ftq_idx
connect slots_14.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[14].wakeup_ports[0].bits.uop.is_mov
connect slots_14.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[14].wakeup_ports[0].bits.uop.is_rocc
connect slots_14.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[14].wakeup_ports[0].bits.uop.is_sys_pc2epc
connect slots_14.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[14].wakeup_ports[0].bits.uop.is_eret
connect slots_14.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[14].wakeup_ports[0].bits.uop.is_amo
connect slots_14.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[14].wakeup_ports[0].bits.uop.is_sfence
connect slots_14.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[14].wakeup_ports[0].bits.uop.is_fencei
connect slots_14.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[14].wakeup_ports[0].bits.uop.is_fence
connect slots_14.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[14].wakeup_ports[0].bits.uop.is_sfb
connect slots_14.io.wakeup_ports[0].bits.uop.br_type, issue_slots[14].wakeup_ports[0].bits.uop.br_type
connect slots_14.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[14].wakeup_ports[0].bits.uop.br_tag
connect slots_14.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[14].wakeup_ports[0].bits.uop.br_mask
connect slots_14.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[14].wakeup_ports[0].bits.uop.dis_col_sel
connect slots_14.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[14].wakeup_ports[0].bits.uop.iw_p3_bypass_hint
connect slots_14.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[14].wakeup_ports[0].bits.uop.iw_p2_bypass_hint
connect slots_14.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[14].wakeup_ports[0].bits.uop.iw_p1_bypass_hint
connect slots_14.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[14].wakeup_ports[0].bits.uop.iw_p2_speculative_child
connect slots_14.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[14].wakeup_ports[0].bits.uop.iw_p1_speculative_child
connect slots_14.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[14].wakeup_ports[0].bits.uop.iw_issued_partial_dgen
connect slots_14.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[14].wakeup_ports[0].bits.uop.iw_issued_partial_agen
connect slots_14.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[14].wakeup_ports[0].bits.uop.iw_issued
connect slots_14.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[14].wakeup_ports[0].bits.uop.fu_code[0]
connect slots_14.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[14].wakeup_ports[0].bits.uop.fu_code[1]
connect slots_14.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[14].wakeup_ports[0].bits.uop.fu_code[2]
connect slots_14.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[14].wakeup_ports[0].bits.uop.fu_code[3]
connect slots_14.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[14].wakeup_ports[0].bits.uop.fu_code[4]
connect slots_14.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[14].wakeup_ports[0].bits.uop.fu_code[5]
connect slots_14.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[14].wakeup_ports[0].bits.uop.fu_code[6]
connect slots_14.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[14].wakeup_ports[0].bits.uop.fu_code[7]
connect slots_14.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[14].wakeup_ports[0].bits.uop.fu_code[8]
connect slots_14.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[14].wakeup_ports[0].bits.uop.fu_code[9]
connect slots_14.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[14].wakeup_ports[0].bits.uop.iq_type[0]
connect slots_14.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[14].wakeup_ports[0].bits.uop.iq_type[1]
connect slots_14.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[14].wakeup_ports[0].bits.uop.iq_type[2]
connect slots_14.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[14].wakeup_ports[0].bits.uop.iq_type[3]
connect slots_14.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[14].wakeup_ports[0].bits.uop.debug_pc
connect slots_14.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[14].wakeup_ports[0].bits.uop.is_rvc
connect slots_14.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[14].wakeup_ports[0].bits.uop.debug_inst
connect slots_14.io.wakeup_ports[0].bits.uop.inst, issue_slots[14].wakeup_ports[0].bits.uop.inst
connect slots_14.io.wakeup_ports[0].valid, issue_slots[14].wakeup_ports[0].valid
connect slots_14.io.wakeup_ports[1].bits.rebusy, issue_slots[14].wakeup_ports[1].bits.rebusy
connect slots_14.io.wakeup_ports[1].bits.speculative_mask, issue_slots[14].wakeup_ports[1].bits.speculative_mask
connect slots_14.io.wakeup_ports[1].bits.bypassable, issue_slots[14].wakeup_ports[1].bits.bypassable
connect slots_14.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[14].wakeup_ports[1].bits.uop.debug_tsrc
connect slots_14.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[14].wakeup_ports[1].bits.uop.debug_fsrc
connect slots_14.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[14].wakeup_ports[1].bits.uop.bp_xcpt_if
connect slots_14.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[14].wakeup_ports[1].bits.uop.bp_debug_if
connect slots_14.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[14].wakeup_ports[1].bits.uop.xcpt_ma_if
connect slots_14.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[14].wakeup_ports[1].bits.uop.xcpt_ae_if
connect slots_14.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[14].wakeup_ports[1].bits.uop.xcpt_pf_if
connect slots_14.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[14].wakeup_ports[1].bits.uop.fp_typ
connect slots_14.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[14].wakeup_ports[1].bits.uop.fp_rm
connect slots_14.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[14].wakeup_ports[1].bits.uop.fp_val
connect slots_14.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[14].wakeup_ports[1].bits.uop.fcn_op
connect slots_14.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[14].wakeup_ports[1].bits.uop.fcn_dw
connect slots_14.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[14].wakeup_ports[1].bits.uop.frs3_en
connect slots_14.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[14].wakeup_ports[1].bits.uop.lrs2_rtype
connect slots_14.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[14].wakeup_ports[1].bits.uop.lrs1_rtype
connect slots_14.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[14].wakeup_ports[1].bits.uop.dst_rtype
connect slots_14.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[14].wakeup_ports[1].bits.uop.lrs3
connect slots_14.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[14].wakeup_ports[1].bits.uop.lrs2
connect slots_14.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[14].wakeup_ports[1].bits.uop.lrs1
connect slots_14.io.wakeup_ports[1].bits.uop.ldst, issue_slots[14].wakeup_ports[1].bits.uop.ldst
connect slots_14.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[14].wakeup_ports[1].bits.uop.ldst_is_rs1
connect slots_14.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[14].wakeup_ports[1].bits.uop.csr_cmd
connect slots_14.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[14].wakeup_ports[1].bits.uop.flush_on_commit
connect slots_14.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[14].wakeup_ports[1].bits.uop.is_unique
connect slots_14.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[14].wakeup_ports[1].bits.uop.uses_stq
connect slots_14.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[14].wakeup_ports[1].bits.uop.uses_ldq
connect slots_14.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[14].wakeup_ports[1].bits.uop.mem_signed
connect slots_14.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[14].wakeup_ports[1].bits.uop.mem_size
connect slots_14.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[14].wakeup_ports[1].bits.uop.mem_cmd
connect slots_14.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[14].wakeup_ports[1].bits.uop.exc_cause
connect slots_14.io.wakeup_ports[1].bits.uop.exception, issue_slots[14].wakeup_ports[1].bits.uop.exception
connect slots_14.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[14].wakeup_ports[1].bits.uop.stale_pdst
connect slots_14.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[14].wakeup_ports[1].bits.uop.ppred_busy
connect slots_14.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[14].wakeup_ports[1].bits.uop.prs3_busy
connect slots_14.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[14].wakeup_ports[1].bits.uop.prs2_busy
connect slots_14.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[14].wakeup_ports[1].bits.uop.prs1_busy
connect slots_14.io.wakeup_ports[1].bits.uop.ppred, issue_slots[14].wakeup_ports[1].bits.uop.ppred
connect slots_14.io.wakeup_ports[1].bits.uop.prs3, issue_slots[14].wakeup_ports[1].bits.uop.prs3
connect slots_14.io.wakeup_ports[1].bits.uop.prs2, issue_slots[14].wakeup_ports[1].bits.uop.prs2
connect slots_14.io.wakeup_ports[1].bits.uop.prs1, issue_slots[14].wakeup_ports[1].bits.uop.prs1
connect slots_14.io.wakeup_ports[1].bits.uop.pdst, issue_slots[14].wakeup_ports[1].bits.uop.pdst
connect slots_14.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[14].wakeup_ports[1].bits.uop.rxq_idx
connect slots_14.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[14].wakeup_ports[1].bits.uop.stq_idx
connect slots_14.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[14].wakeup_ports[1].bits.uop.ldq_idx
connect slots_14.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[14].wakeup_ports[1].bits.uop.rob_idx
connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.vec
connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.wflags
connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.sqrt
connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.div
connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.fma
connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe
connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.toint
connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.fromint
connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut
connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn
connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.swap23
connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.swap12
connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.ren3
connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.ren2
connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.ren1
connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.wen
connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.ldst
connect slots_14.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[14].wakeup_ports[1].bits.uop.op2_sel
connect slots_14.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[14].wakeup_ports[1].bits.uop.op1_sel
connect slots_14.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[14].wakeup_ports[1].bits.uop.imm_packed
connect slots_14.io.wakeup_ports[1].bits.uop.pimm, issue_slots[14].wakeup_ports[1].bits.uop.pimm
connect slots_14.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[14].wakeup_ports[1].bits.uop.imm_sel
connect slots_14.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[14].wakeup_ports[1].bits.uop.imm_rename
connect slots_14.io.wakeup_ports[1].bits.uop.taken, issue_slots[14].wakeup_ports[1].bits.uop.taken
connect slots_14.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[14].wakeup_ports[1].bits.uop.pc_lob
connect slots_14.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[14].wakeup_ports[1].bits.uop.edge_inst
connect slots_14.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[14].wakeup_ports[1].bits.uop.ftq_idx
connect slots_14.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[14].wakeup_ports[1].bits.uop.is_mov
connect slots_14.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[14].wakeup_ports[1].bits.uop.is_rocc
connect slots_14.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[14].wakeup_ports[1].bits.uop.is_sys_pc2epc
connect slots_14.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[14].wakeup_ports[1].bits.uop.is_eret
connect slots_14.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[14].wakeup_ports[1].bits.uop.is_amo
connect slots_14.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[14].wakeup_ports[1].bits.uop.is_sfence
connect slots_14.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[14].wakeup_ports[1].bits.uop.is_fencei
connect slots_14.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[14].wakeup_ports[1].bits.uop.is_fence
connect slots_14.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[14].wakeup_ports[1].bits.uop.is_sfb
connect slots_14.io.wakeup_ports[1].bits.uop.br_type, issue_slots[14].wakeup_ports[1].bits.uop.br_type
connect slots_14.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[14].wakeup_ports[1].bits.uop.br_tag
connect slots_14.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[14].wakeup_ports[1].bits.uop.br_mask
connect slots_14.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[14].wakeup_ports[1].bits.uop.dis_col_sel
connect slots_14.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[14].wakeup_ports[1].bits.uop.iw_p3_bypass_hint
connect slots_14.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[14].wakeup_ports[1].bits.uop.iw_p2_bypass_hint
connect slots_14.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[14].wakeup_ports[1].bits.uop.iw_p1_bypass_hint
connect slots_14.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[14].wakeup_ports[1].bits.uop.iw_p2_speculative_child
connect slots_14.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[14].wakeup_ports[1].bits.uop.iw_p1_speculative_child
connect slots_14.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[14].wakeup_ports[1].bits.uop.iw_issued_partial_dgen
connect slots_14.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[14].wakeup_ports[1].bits.uop.iw_issued_partial_agen
connect slots_14.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[14].wakeup_ports[1].bits.uop.iw_issued
connect slots_14.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[14].wakeup_ports[1].bits.uop.fu_code[0]
connect slots_14.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[14].wakeup_ports[1].bits.uop.fu_code[1]
connect slots_14.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[14].wakeup_ports[1].bits.uop.fu_code[2]
connect slots_14.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[14].wakeup_ports[1].bits.uop.fu_code[3]
connect slots_14.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[14].wakeup_ports[1].bits.uop.fu_code[4]
connect slots_14.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[14].wakeup_ports[1].bits.uop.fu_code[5]
connect slots_14.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[14].wakeup_ports[1].bits.uop.fu_code[6]
connect slots_14.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[14].wakeup_ports[1].bits.uop.fu_code[7]
connect slots_14.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[14].wakeup_ports[1].bits.uop.fu_code[8]
connect slots_14.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[14].wakeup_ports[1].bits.uop.fu_code[9]
connect slots_14.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[14].wakeup_ports[1].bits.uop.iq_type[0]
connect slots_14.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[14].wakeup_ports[1].bits.uop.iq_type[1]
connect slots_14.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[14].wakeup_ports[1].bits.uop.iq_type[2]
connect slots_14.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[14].wakeup_ports[1].bits.uop.iq_type[3]
connect slots_14.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[14].wakeup_ports[1].bits.uop.debug_pc
connect slots_14.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[14].wakeup_ports[1].bits.uop.is_rvc
connect slots_14.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[14].wakeup_ports[1].bits.uop.debug_inst
connect slots_14.io.wakeup_ports[1].bits.uop.inst, issue_slots[14].wakeup_ports[1].bits.uop.inst
connect slots_14.io.wakeup_ports[1].valid, issue_slots[14].wakeup_ports[1].valid
connect slots_14.io.wakeup_ports[2].bits.rebusy, issue_slots[14].wakeup_ports[2].bits.rebusy
connect slots_14.io.wakeup_ports[2].bits.speculative_mask, issue_slots[14].wakeup_ports[2].bits.speculative_mask
connect slots_14.io.wakeup_ports[2].bits.bypassable, issue_slots[14].wakeup_ports[2].bits.bypassable
connect slots_14.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[14].wakeup_ports[2].bits.uop.debug_tsrc
connect slots_14.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[14].wakeup_ports[2].bits.uop.debug_fsrc
connect slots_14.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[14].wakeup_ports[2].bits.uop.bp_xcpt_if
connect slots_14.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[14].wakeup_ports[2].bits.uop.bp_debug_if
connect slots_14.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[14].wakeup_ports[2].bits.uop.xcpt_ma_if
connect slots_14.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[14].wakeup_ports[2].bits.uop.xcpt_ae_if
connect slots_14.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[14].wakeup_ports[2].bits.uop.xcpt_pf_if
connect slots_14.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[14].wakeup_ports[2].bits.uop.fp_typ
connect slots_14.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[14].wakeup_ports[2].bits.uop.fp_rm
connect slots_14.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[14].wakeup_ports[2].bits.uop.fp_val
connect slots_14.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[14].wakeup_ports[2].bits.uop.fcn_op
connect slots_14.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[14].wakeup_ports[2].bits.uop.fcn_dw
connect slots_14.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[14].wakeup_ports[2].bits.uop.frs3_en
connect slots_14.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[14].wakeup_ports[2].bits.uop.lrs2_rtype
connect slots_14.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[14].wakeup_ports[2].bits.uop.lrs1_rtype
connect slots_14.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[14].wakeup_ports[2].bits.uop.dst_rtype
connect slots_14.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[14].wakeup_ports[2].bits.uop.lrs3
connect slots_14.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[14].wakeup_ports[2].bits.uop.lrs2
connect slots_14.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[14].wakeup_ports[2].bits.uop.lrs1
connect slots_14.io.wakeup_ports[2].bits.uop.ldst, issue_slots[14].wakeup_ports[2].bits.uop.ldst
connect slots_14.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[14].wakeup_ports[2].bits.uop.ldst_is_rs1
connect slots_14.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[14].wakeup_ports[2].bits.uop.csr_cmd
connect slots_14.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[14].wakeup_ports[2].bits.uop.flush_on_commit
connect slots_14.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[14].wakeup_ports[2].bits.uop.is_unique
connect slots_14.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[14].wakeup_ports[2].bits.uop.uses_stq
connect slots_14.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[14].wakeup_ports[2].bits.uop.uses_ldq
connect slots_14.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[14].wakeup_ports[2].bits.uop.mem_signed
connect slots_14.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[14].wakeup_ports[2].bits.uop.mem_size
connect slots_14.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[14].wakeup_ports[2].bits.uop.mem_cmd
connect slots_14.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[14].wakeup_ports[2].bits.uop.exc_cause
connect slots_14.io.wakeup_ports[2].bits.uop.exception, issue_slots[14].wakeup_ports[2].bits.uop.exception
connect slots_14.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[14].wakeup_ports[2].bits.uop.stale_pdst
connect slots_14.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[14].wakeup_ports[2].bits.uop.ppred_busy
connect slots_14.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[14].wakeup_ports[2].bits.uop.prs3_busy
connect slots_14.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[14].wakeup_ports[2].bits.uop.prs2_busy
connect slots_14.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[14].wakeup_ports[2].bits.uop.prs1_busy
connect slots_14.io.wakeup_ports[2].bits.uop.ppred, issue_slots[14].wakeup_ports[2].bits.uop.ppred
connect slots_14.io.wakeup_ports[2].bits.uop.prs3, issue_slots[14].wakeup_ports[2].bits.uop.prs3
connect slots_14.io.wakeup_ports[2].bits.uop.prs2, issue_slots[14].wakeup_ports[2].bits.uop.prs2
connect slots_14.io.wakeup_ports[2].bits.uop.prs1, issue_slots[14].wakeup_ports[2].bits.uop.prs1
connect slots_14.io.wakeup_ports[2].bits.uop.pdst, issue_slots[14].wakeup_ports[2].bits.uop.pdst
connect slots_14.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[14].wakeup_ports[2].bits.uop.rxq_idx
connect slots_14.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[14].wakeup_ports[2].bits.uop.stq_idx
connect slots_14.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[14].wakeup_ports[2].bits.uop.ldq_idx
connect slots_14.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[14].wakeup_ports[2].bits.uop.rob_idx
connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.vec
connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.wflags
connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.sqrt
connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.div
connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.fma
connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe
connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.toint
connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.fromint
connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut
connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn
connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.swap23
connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.swap12
connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.ren3
connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.ren2
connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.ren1
connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.wen
connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.ldst
connect slots_14.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[14].wakeup_ports[2].bits.uop.op2_sel
connect slots_14.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[14].wakeup_ports[2].bits.uop.op1_sel
connect slots_14.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[14].wakeup_ports[2].bits.uop.imm_packed
connect slots_14.io.wakeup_ports[2].bits.uop.pimm, issue_slots[14].wakeup_ports[2].bits.uop.pimm
connect slots_14.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[14].wakeup_ports[2].bits.uop.imm_sel
connect slots_14.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[14].wakeup_ports[2].bits.uop.imm_rename
connect slots_14.io.wakeup_ports[2].bits.uop.taken, issue_slots[14].wakeup_ports[2].bits.uop.taken
connect slots_14.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[14].wakeup_ports[2].bits.uop.pc_lob
connect slots_14.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[14].wakeup_ports[2].bits.uop.edge_inst
connect slots_14.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[14].wakeup_ports[2].bits.uop.ftq_idx
connect slots_14.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[14].wakeup_ports[2].bits.uop.is_mov
connect slots_14.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[14].wakeup_ports[2].bits.uop.is_rocc
connect slots_14.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[14].wakeup_ports[2].bits.uop.is_sys_pc2epc
connect slots_14.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[14].wakeup_ports[2].bits.uop.is_eret
connect slots_14.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[14].wakeup_ports[2].bits.uop.is_amo
connect slots_14.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[14].wakeup_ports[2].bits.uop.is_sfence
connect slots_14.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[14].wakeup_ports[2].bits.uop.is_fencei
connect slots_14.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[14].wakeup_ports[2].bits.uop.is_fence
connect slots_14.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[14].wakeup_ports[2].bits.uop.is_sfb
connect slots_14.io.wakeup_ports[2].bits.uop.br_type, issue_slots[14].wakeup_ports[2].bits.uop.br_type
connect slots_14.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[14].wakeup_ports[2].bits.uop.br_tag
connect slots_14.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[14].wakeup_ports[2].bits.uop.br_mask
connect slots_14.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[14].wakeup_ports[2].bits.uop.dis_col_sel
connect slots_14.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[14].wakeup_ports[2].bits.uop.iw_p3_bypass_hint
connect slots_14.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[14].wakeup_ports[2].bits.uop.iw_p2_bypass_hint
connect slots_14.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[14].wakeup_ports[2].bits.uop.iw_p1_bypass_hint
connect slots_14.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[14].wakeup_ports[2].bits.uop.iw_p2_speculative_child
connect slots_14.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[14].wakeup_ports[2].bits.uop.iw_p1_speculative_child
connect slots_14.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[14].wakeup_ports[2].bits.uop.iw_issued_partial_dgen
connect slots_14.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[14].wakeup_ports[2].bits.uop.iw_issued_partial_agen
connect slots_14.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[14].wakeup_ports[2].bits.uop.iw_issued
connect slots_14.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[14].wakeup_ports[2].bits.uop.fu_code[0]
connect slots_14.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[14].wakeup_ports[2].bits.uop.fu_code[1]
connect slots_14.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[14].wakeup_ports[2].bits.uop.fu_code[2]
connect slots_14.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[14].wakeup_ports[2].bits.uop.fu_code[3]
connect slots_14.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[14].wakeup_ports[2].bits.uop.fu_code[4]
connect slots_14.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[14].wakeup_ports[2].bits.uop.fu_code[5]
connect slots_14.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[14].wakeup_ports[2].bits.uop.fu_code[6]
connect slots_14.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[14].wakeup_ports[2].bits.uop.fu_code[7]
connect slots_14.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[14].wakeup_ports[2].bits.uop.fu_code[8]
connect slots_14.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[14].wakeup_ports[2].bits.uop.fu_code[9]
connect slots_14.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[14].wakeup_ports[2].bits.uop.iq_type[0]
connect slots_14.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[14].wakeup_ports[2].bits.uop.iq_type[1]
connect slots_14.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[14].wakeup_ports[2].bits.uop.iq_type[2]
connect slots_14.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[14].wakeup_ports[2].bits.uop.iq_type[3]
connect slots_14.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[14].wakeup_ports[2].bits.uop.debug_pc
connect slots_14.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[14].wakeup_ports[2].bits.uop.is_rvc
connect slots_14.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[14].wakeup_ports[2].bits.uop.debug_inst
connect slots_14.io.wakeup_ports[2].bits.uop.inst, issue_slots[14].wakeup_ports[2].bits.uop.inst
connect slots_14.io.wakeup_ports[2].valid, issue_slots[14].wakeup_ports[2].valid
connect slots_14.io.wakeup_ports[3].bits.rebusy, issue_slots[14].wakeup_ports[3].bits.rebusy
connect slots_14.io.wakeup_ports[3].bits.speculative_mask, issue_slots[14].wakeup_ports[3].bits.speculative_mask
connect slots_14.io.wakeup_ports[3].bits.bypassable, issue_slots[14].wakeup_ports[3].bits.bypassable
connect slots_14.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[14].wakeup_ports[3].bits.uop.debug_tsrc
connect slots_14.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[14].wakeup_ports[3].bits.uop.debug_fsrc
connect slots_14.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[14].wakeup_ports[3].bits.uop.bp_xcpt_if
connect slots_14.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[14].wakeup_ports[3].bits.uop.bp_debug_if
connect slots_14.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[14].wakeup_ports[3].bits.uop.xcpt_ma_if
connect slots_14.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[14].wakeup_ports[3].bits.uop.xcpt_ae_if
connect slots_14.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[14].wakeup_ports[3].bits.uop.xcpt_pf_if
connect slots_14.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[14].wakeup_ports[3].bits.uop.fp_typ
connect slots_14.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[14].wakeup_ports[3].bits.uop.fp_rm
connect slots_14.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[14].wakeup_ports[3].bits.uop.fp_val
connect slots_14.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[14].wakeup_ports[3].bits.uop.fcn_op
connect slots_14.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[14].wakeup_ports[3].bits.uop.fcn_dw
connect slots_14.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[14].wakeup_ports[3].bits.uop.frs3_en
connect slots_14.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[14].wakeup_ports[3].bits.uop.lrs2_rtype
connect slots_14.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[14].wakeup_ports[3].bits.uop.lrs1_rtype
connect slots_14.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[14].wakeup_ports[3].bits.uop.dst_rtype
connect slots_14.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[14].wakeup_ports[3].bits.uop.lrs3
connect slots_14.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[14].wakeup_ports[3].bits.uop.lrs2
connect slots_14.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[14].wakeup_ports[3].bits.uop.lrs1
connect slots_14.io.wakeup_ports[3].bits.uop.ldst, issue_slots[14].wakeup_ports[3].bits.uop.ldst
connect slots_14.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[14].wakeup_ports[3].bits.uop.ldst_is_rs1
connect slots_14.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[14].wakeup_ports[3].bits.uop.csr_cmd
connect slots_14.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[14].wakeup_ports[3].bits.uop.flush_on_commit
connect slots_14.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[14].wakeup_ports[3].bits.uop.is_unique
connect slots_14.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[14].wakeup_ports[3].bits.uop.uses_stq
connect slots_14.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[14].wakeup_ports[3].bits.uop.uses_ldq
connect slots_14.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[14].wakeup_ports[3].bits.uop.mem_signed
connect slots_14.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[14].wakeup_ports[3].bits.uop.mem_size
connect slots_14.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[14].wakeup_ports[3].bits.uop.mem_cmd
connect slots_14.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[14].wakeup_ports[3].bits.uop.exc_cause
connect slots_14.io.wakeup_ports[3].bits.uop.exception, issue_slots[14].wakeup_ports[3].bits.uop.exception
connect slots_14.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[14].wakeup_ports[3].bits.uop.stale_pdst
connect slots_14.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[14].wakeup_ports[3].bits.uop.ppred_busy
connect slots_14.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[14].wakeup_ports[3].bits.uop.prs3_busy
connect slots_14.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[14].wakeup_ports[3].bits.uop.prs2_busy
connect slots_14.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[14].wakeup_ports[3].bits.uop.prs1_busy
connect slots_14.io.wakeup_ports[3].bits.uop.ppred, issue_slots[14].wakeup_ports[3].bits.uop.ppred
connect slots_14.io.wakeup_ports[3].bits.uop.prs3, issue_slots[14].wakeup_ports[3].bits.uop.prs3
connect slots_14.io.wakeup_ports[3].bits.uop.prs2, issue_slots[14].wakeup_ports[3].bits.uop.prs2
connect slots_14.io.wakeup_ports[3].bits.uop.prs1, issue_slots[14].wakeup_ports[3].bits.uop.prs1
connect slots_14.io.wakeup_ports[3].bits.uop.pdst, issue_slots[14].wakeup_ports[3].bits.uop.pdst
connect slots_14.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[14].wakeup_ports[3].bits.uop.rxq_idx
connect slots_14.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[14].wakeup_ports[3].bits.uop.stq_idx
connect slots_14.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[14].wakeup_ports[3].bits.uop.ldq_idx
connect slots_14.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[14].wakeup_ports[3].bits.uop.rob_idx
connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.vec
connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.wflags
connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.sqrt
connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.div
connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.fma
connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe
connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.toint
connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.fromint
connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut
connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn
connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.swap23
connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.swap12
connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.ren3
connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.ren2
connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.ren1
connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.wen
connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.ldst
connect slots_14.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[14].wakeup_ports[3].bits.uop.op2_sel
connect slots_14.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[14].wakeup_ports[3].bits.uop.op1_sel
connect slots_14.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[14].wakeup_ports[3].bits.uop.imm_packed
connect slots_14.io.wakeup_ports[3].bits.uop.pimm, issue_slots[14].wakeup_ports[3].bits.uop.pimm
connect slots_14.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[14].wakeup_ports[3].bits.uop.imm_sel
connect slots_14.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[14].wakeup_ports[3].bits.uop.imm_rename
connect slots_14.io.wakeup_ports[3].bits.uop.taken, issue_slots[14].wakeup_ports[3].bits.uop.taken
connect slots_14.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[14].wakeup_ports[3].bits.uop.pc_lob
connect slots_14.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[14].wakeup_ports[3].bits.uop.edge_inst
connect slots_14.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[14].wakeup_ports[3].bits.uop.ftq_idx
connect slots_14.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[14].wakeup_ports[3].bits.uop.is_mov
connect slots_14.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[14].wakeup_ports[3].bits.uop.is_rocc
connect slots_14.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[14].wakeup_ports[3].bits.uop.is_sys_pc2epc
connect slots_14.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[14].wakeup_ports[3].bits.uop.is_eret
connect slots_14.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[14].wakeup_ports[3].bits.uop.is_amo
connect slots_14.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[14].wakeup_ports[3].bits.uop.is_sfence
connect slots_14.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[14].wakeup_ports[3].bits.uop.is_fencei
connect slots_14.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[14].wakeup_ports[3].bits.uop.is_fence
connect slots_14.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[14].wakeup_ports[3].bits.uop.is_sfb
connect slots_14.io.wakeup_ports[3].bits.uop.br_type, issue_slots[14].wakeup_ports[3].bits.uop.br_type
connect slots_14.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[14].wakeup_ports[3].bits.uop.br_tag
connect slots_14.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[14].wakeup_ports[3].bits.uop.br_mask
connect slots_14.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[14].wakeup_ports[3].bits.uop.dis_col_sel
connect slots_14.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[14].wakeup_ports[3].bits.uop.iw_p3_bypass_hint
connect slots_14.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[14].wakeup_ports[3].bits.uop.iw_p2_bypass_hint
connect slots_14.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[14].wakeup_ports[3].bits.uop.iw_p1_bypass_hint
connect slots_14.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[14].wakeup_ports[3].bits.uop.iw_p2_speculative_child
connect slots_14.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[14].wakeup_ports[3].bits.uop.iw_p1_speculative_child
connect slots_14.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[14].wakeup_ports[3].bits.uop.iw_issued_partial_dgen
connect slots_14.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[14].wakeup_ports[3].bits.uop.iw_issued_partial_agen
connect slots_14.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[14].wakeup_ports[3].bits.uop.iw_issued
connect slots_14.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[14].wakeup_ports[3].bits.uop.fu_code[0]
connect slots_14.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[14].wakeup_ports[3].bits.uop.fu_code[1]
connect slots_14.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[14].wakeup_ports[3].bits.uop.fu_code[2]
connect slots_14.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[14].wakeup_ports[3].bits.uop.fu_code[3]
connect slots_14.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[14].wakeup_ports[3].bits.uop.fu_code[4]
connect slots_14.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[14].wakeup_ports[3].bits.uop.fu_code[5]
connect slots_14.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[14].wakeup_ports[3].bits.uop.fu_code[6]
connect slots_14.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[14].wakeup_ports[3].bits.uop.fu_code[7]
connect slots_14.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[14].wakeup_ports[3].bits.uop.fu_code[8]
connect slots_14.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[14].wakeup_ports[3].bits.uop.fu_code[9]
connect slots_14.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[14].wakeup_ports[3].bits.uop.iq_type[0]
connect slots_14.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[14].wakeup_ports[3].bits.uop.iq_type[1]
connect slots_14.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[14].wakeup_ports[3].bits.uop.iq_type[2]
connect slots_14.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[14].wakeup_ports[3].bits.uop.iq_type[3]
connect slots_14.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[14].wakeup_ports[3].bits.uop.debug_pc
connect slots_14.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[14].wakeup_ports[3].bits.uop.is_rvc
connect slots_14.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[14].wakeup_ports[3].bits.uop.debug_inst
connect slots_14.io.wakeup_ports[3].bits.uop.inst, issue_slots[14].wakeup_ports[3].bits.uop.inst
connect slots_14.io.wakeup_ports[3].valid, issue_slots[14].wakeup_ports[3].valid
connect slots_14.io.squash_grant, issue_slots[14].squash_grant
connect slots_14.io.clear, issue_slots[14].clear
connect slots_14.io.kill, issue_slots[14].kill
connect slots_14.io.brupdate.b2.target_offset, issue_slots[14].brupdate.b2.target_offset
connect slots_14.io.brupdate.b2.jalr_target, issue_slots[14].brupdate.b2.jalr_target
connect slots_14.io.brupdate.b2.pc_sel, issue_slots[14].brupdate.b2.pc_sel
connect slots_14.io.brupdate.b2.cfi_type, issue_slots[14].brupdate.b2.cfi_type
connect slots_14.io.brupdate.b2.taken, issue_slots[14].brupdate.b2.taken
connect slots_14.io.brupdate.b2.mispredict, issue_slots[14].brupdate.b2.mispredict
connect slots_14.io.brupdate.b2.uop.debug_tsrc, issue_slots[14].brupdate.b2.uop.debug_tsrc
connect slots_14.io.brupdate.b2.uop.debug_fsrc, issue_slots[14].brupdate.b2.uop.debug_fsrc
connect slots_14.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[14].brupdate.b2.uop.bp_xcpt_if
connect slots_14.io.brupdate.b2.uop.bp_debug_if, issue_slots[14].brupdate.b2.uop.bp_debug_if
connect slots_14.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[14].brupdate.b2.uop.xcpt_ma_if
connect slots_14.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[14].brupdate.b2.uop.xcpt_ae_if
connect slots_14.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[14].brupdate.b2.uop.xcpt_pf_if
connect slots_14.io.brupdate.b2.uop.fp_typ, issue_slots[14].brupdate.b2.uop.fp_typ
connect slots_14.io.brupdate.b2.uop.fp_rm, issue_slots[14].brupdate.b2.uop.fp_rm
connect slots_14.io.brupdate.b2.uop.fp_val, issue_slots[14].brupdate.b2.uop.fp_val
connect slots_14.io.brupdate.b2.uop.fcn_op, issue_slots[14].brupdate.b2.uop.fcn_op
connect slots_14.io.brupdate.b2.uop.fcn_dw, issue_slots[14].brupdate.b2.uop.fcn_dw
connect slots_14.io.brupdate.b2.uop.frs3_en, issue_slots[14].brupdate.b2.uop.frs3_en
connect slots_14.io.brupdate.b2.uop.lrs2_rtype, issue_slots[14].brupdate.b2.uop.lrs2_rtype
connect slots_14.io.brupdate.b2.uop.lrs1_rtype, issue_slots[14].brupdate.b2.uop.lrs1_rtype
connect slots_14.io.brupdate.b2.uop.dst_rtype, issue_slots[14].brupdate.b2.uop.dst_rtype
connect slots_14.io.brupdate.b2.uop.lrs3, issue_slots[14].brupdate.b2.uop.lrs3
connect slots_14.io.brupdate.b2.uop.lrs2, issue_slots[14].brupdate.b2.uop.lrs2
connect slots_14.io.brupdate.b2.uop.lrs1, issue_slots[14].brupdate.b2.uop.lrs1
connect slots_14.io.brupdate.b2.uop.ldst, issue_slots[14].brupdate.b2.uop.ldst
connect slots_14.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[14].brupdate.b2.uop.ldst_is_rs1
connect slots_14.io.brupdate.b2.uop.csr_cmd, issue_slots[14].brupdate.b2.uop.csr_cmd
connect slots_14.io.brupdate.b2.uop.flush_on_commit, issue_slots[14].brupdate.b2.uop.flush_on_commit
connect slots_14.io.brupdate.b2.uop.is_unique, issue_slots[14].brupdate.b2.uop.is_unique
connect slots_14.io.brupdate.b2.uop.uses_stq, issue_slots[14].brupdate.b2.uop.uses_stq
connect slots_14.io.brupdate.b2.uop.uses_ldq, issue_slots[14].brupdate.b2.uop.uses_ldq
connect slots_14.io.brupdate.b2.uop.mem_signed, issue_slots[14].brupdate.b2.uop.mem_signed
connect slots_14.io.brupdate.b2.uop.mem_size, issue_slots[14].brupdate.b2.uop.mem_size
connect slots_14.io.brupdate.b2.uop.mem_cmd, issue_slots[14].brupdate.b2.uop.mem_cmd
connect slots_14.io.brupdate.b2.uop.exc_cause, issue_slots[14].brupdate.b2.uop.exc_cause
connect slots_14.io.brupdate.b2.uop.exception, issue_slots[14].brupdate.b2.uop.exception
connect slots_14.io.brupdate.b2.uop.stale_pdst, issue_slots[14].brupdate.b2.uop.stale_pdst
connect slots_14.io.brupdate.b2.uop.ppred_busy, issue_slots[14].brupdate.b2.uop.ppred_busy
connect slots_14.io.brupdate.b2.uop.prs3_busy, issue_slots[14].brupdate.b2.uop.prs3_busy
connect slots_14.io.brupdate.b2.uop.prs2_busy, issue_slots[14].brupdate.b2.uop.prs2_busy
connect slots_14.io.brupdate.b2.uop.prs1_busy, issue_slots[14].brupdate.b2.uop.prs1_busy
connect slots_14.io.brupdate.b2.uop.ppred, issue_slots[14].brupdate.b2.uop.ppred
connect slots_14.io.brupdate.b2.uop.prs3, issue_slots[14].brupdate.b2.uop.prs3
connect slots_14.io.brupdate.b2.uop.prs2, issue_slots[14].brupdate.b2.uop.prs2
connect slots_14.io.brupdate.b2.uop.prs1, issue_slots[14].brupdate.b2.uop.prs1
connect slots_14.io.brupdate.b2.uop.pdst, issue_slots[14].brupdate.b2.uop.pdst
connect slots_14.io.brupdate.b2.uop.rxq_idx, issue_slots[14].brupdate.b2.uop.rxq_idx
connect slots_14.io.brupdate.b2.uop.stq_idx, issue_slots[14].brupdate.b2.uop.stq_idx
connect slots_14.io.brupdate.b2.uop.ldq_idx, issue_slots[14].brupdate.b2.uop.ldq_idx
connect slots_14.io.brupdate.b2.uop.rob_idx, issue_slots[14].brupdate.b2.uop.rob_idx
connect slots_14.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[14].brupdate.b2.uop.fp_ctrl.vec
connect slots_14.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[14].brupdate.b2.uop.fp_ctrl.wflags
connect slots_14.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[14].brupdate.b2.uop.fp_ctrl.sqrt
connect slots_14.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[14].brupdate.b2.uop.fp_ctrl.div
connect slots_14.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[14].brupdate.b2.uop.fp_ctrl.fma
connect slots_14.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[14].brupdate.b2.uop.fp_ctrl.fastpipe
connect slots_14.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[14].brupdate.b2.uop.fp_ctrl.toint
connect slots_14.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[14].brupdate.b2.uop.fp_ctrl.fromint
connect slots_14.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[14].brupdate.b2.uop.fp_ctrl.typeTagOut
connect slots_14.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[14].brupdate.b2.uop.fp_ctrl.typeTagIn
connect slots_14.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[14].brupdate.b2.uop.fp_ctrl.swap23
connect slots_14.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[14].brupdate.b2.uop.fp_ctrl.swap12
connect slots_14.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[14].brupdate.b2.uop.fp_ctrl.ren3
connect slots_14.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[14].brupdate.b2.uop.fp_ctrl.ren2
connect slots_14.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[14].brupdate.b2.uop.fp_ctrl.ren1
connect slots_14.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[14].brupdate.b2.uop.fp_ctrl.wen
connect slots_14.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[14].brupdate.b2.uop.fp_ctrl.ldst
connect slots_14.io.brupdate.b2.uop.op2_sel, issue_slots[14].brupdate.b2.uop.op2_sel
connect slots_14.io.brupdate.b2.uop.op1_sel, issue_slots[14].brupdate.b2.uop.op1_sel
connect slots_14.io.brupdate.b2.uop.imm_packed, issue_slots[14].brupdate.b2.uop.imm_packed
connect slots_14.io.brupdate.b2.uop.pimm, issue_slots[14].brupdate.b2.uop.pimm
connect slots_14.io.brupdate.b2.uop.imm_sel, issue_slots[14].brupdate.b2.uop.imm_sel
connect slots_14.io.brupdate.b2.uop.imm_rename, issue_slots[14].brupdate.b2.uop.imm_rename
connect slots_14.io.brupdate.b2.uop.taken, issue_slots[14].brupdate.b2.uop.taken
connect slots_14.io.brupdate.b2.uop.pc_lob, issue_slots[14].brupdate.b2.uop.pc_lob
connect slots_14.io.brupdate.b2.uop.edge_inst, issue_slots[14].brupdate.b2.uop.edge_inst
connect slots_14.io.brupdate.b2.uop.ftq_idx, issue_slots[14].brupdate.b2.uop.ftq_idx
connect slots_14.io.brupdate.b2.uop.is_mov, issue_slots[14].brupdate.b2.uop.is_mov
connect slots_14.io.brupdate.b2.uop.is_rocc, issue_slots[14].brupdate.b2.uop.is_rocc
connect slots_14.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[14].brupdate.b2.uop.is_sys_pc2epc
connect slots_14.io.brupdate.b2.uop.is_eret, issue_slots[14].brupdate.b2.uop.is_eret
connect slots_14.io.brupdate.b2.uop.is_amo, issue_slots[14].brupdate.b2.uop.is_amo
connect slots_14.io.brupdate.b2.uop.is_sfence, issue_slots[14].brupdate.b2.uop.is_sfence
connect slots_14.io.brupdate.b2.uop.is_fencei, issue_slots[14].brupdate.b2.uop.is_fencei
connect slots_14.io.brupdate.b2.uop.is_fence, issue_slots[14].brupdate.b2.uop.is_fence
connect slots_14.io.brupdate.b2.uop.is_sfb, issue_slots[14].brupdate.b2.uop.is_sfb
connect slots_14.io.brupdate.b2.uop.br_type, issue_slots[14].brupdate.b2.uop.br_type
connect slots_14.io.brupdate.b2.uop.br_tag, issue_slots[14].brupdate.b2.uop.br_tag
connect slots_14.io.brupdate.b2.uop.br_mask, issue_slots[14].brupdate.b2.uop.br_mask
connect slots_14.io.brupdate.b2.uop.dis_col_sel, issue_slots[14].brupdate.b2.uop.dis_col_sel
connect slots_14.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[14].brupdate.b2.uop.iw_p3_bypass_hint
connect slots_14.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[14].brupdate.b2.uop.iw_p2_bypass_hint
connect slots_14.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[14].brupdate.b2.uop.iw_p1_bypass_hint
connect slots_14.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[14].brupdate.b2.uop.iw_p2_speculative_child
connect slots_14.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[14].brupdate.b2.uop.iw_p1_speculative_child
connect slots_14.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[14].brupdate.b2.uop.iw_issued_partial_dgen
connect slots_14.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[14].brupdate.b2.uop.iw_issued_partial_agen
connect slots_14.io.brupdate.b2.uop.iw_issued, issue_slots[14].brupdate.b2.uop.iw_issued
connect slots_14.io.brupdate.b2.uop.fu_code[0], issue_slots[14].brupdate.b2.uop.fu_code[0]
connect slots_14.io.brupdate.b2.uop.fu_code[1], issue_slots[14].brupdate.b2.uop.fu_code[1]
connect slots_14.io.brupdate.b2.uop.fu_code[2], issue_slots[14].brupdate.b2.uop.fu_code[2]
connect slots_14.io.brupdate.b2.uop.fu_code[3], issue_slots[14].brupdate.b2.uop.fu_code[3]
connect slots_14.io.brupdate.b2.uop.fu_code[4], issue_slots[14].brupdate.b2.uop.fu_code[4]
connect slots_14.io.brupdate.b2.uop.fu_code[5], issue_slots[14].brupdate.b2.uop.fu_code[5]
connect slots_14.io.brupdate.b2.uop.fu_code[6], issue_slots[14].brupdate.b2.uop.fu_code[6]
connect slots_14.io.brupdate.b2.uop.fu_code[7], issue_slots[14].brupdate.b2.uop.fu_code[7]
connect slots_14.io.brupdate.b2.uop.fu_code[8], issue_slots[14].brupdate.b2.uop.fu_code[8]
connect slots_14.io.brupdate.b2.uop.fu_code[9], issue_slots[14].brupdate.b2.uop.fu_code[9]
connect slots_14.io.brupdate.b2.uop.iq_type[0], issue_slots[14].brupdate.b2.uop.iq_type[0]
connect slots_14.io.brupdate.b2.uop.iq_type[1], issue_slots[14].brupdate.b2.uop.iq_type[1]
connect slots_14.io.brupdate.b2.uop.iq_type[2], issue_slots[14].brupdate.b2.uop.iq_type[2]
connect slots_14.io.brupdate.b2.uop.iq_type[3], issue_slots[14].brupdate.b2.uop.iq_type[3]
connect slots_14.io.brupdate.b2.uop.debug_pc, issue_slots[14].brupdate.b2.uop.debug_pc
connect slots_14.io.brupdate.b2.uop.is_rvc, issue_slots[14].brupdate.b2.uop.is_rvc
connect slots_14.io.brupdate.b2.uop.debug_inst, issue_slots[14].brupdate.b2.uop.debug_inst
connect slots_14.io.brupdate.b2.uop.inst, issue_slots[14].brupdate.b2.uop.inst
connect slots_14.io.brupdate.b1.mispredict_mask, issue_slots[14].brupdate.b1.mispredict_mask
connect slots_14.io.brupdate.b1.resolve_mask, issue_slots[14].brupdate.b1.resolve_mask
connect issue_slots[14].out_uop.debug_tsrc, slots_14.io.out_uop.debug_tsrc
connect issue_slots[14].out_uop.debug_fsrc, slots_14.io.out_uop.debug_fsrc
connect issue_slots[14].out_uop.bp_xcpt_if, slots_14.io.out_uop.bp_xcpt_if
connect issue_slots[14].out_uop.bp_debug_if, slots_14.io.out_uop.bp_debug_if
connect issue_slots[14].out_uop.xcpt_ma_if, slots_14.io.out_uop.xcpt_ma_if
connect issue_slots[14].out_uop.xcpt_ae_if, slots_14.io.out_uop.xcpt_ae_if
connect issue_slots[14].out_uop.xcpt_pf_if, slots_14.io.out_uop.xcpt_pf_if
connect issue_slots[14].out_uop.fp_typ, slots_14.io.out_uop.fp_typ
connect issue_slots[14].out_uop.fp_rm, slots_14.io.out_uop.fp_rm
connect issue_slots[14].out_uop.fp_val, slots_14.io.out_uop.fp_val
connect issue_slots[14].out_uop.fcn_op, slots_14.io.out_uop.fcn_op
connect issue_slots[14].out_uop.fcn_dw, slots_14.io.out_uop.fcn_dw
connect issue_slots[14].out_uop.frs3_en, slots_14.io.out_uop.frs3_en
connect issue_slots[14].out_uop.lrs2_rtype, slots_14.io.out_uop.lrs2_rtype
connect issue_slots[14].out_uop.lrs1_rtype, slots_14.io.out_uop.lrs1_rtype
connect issue_slots[14].out_uop.dst_rtype, slots_14.io.out_uop.dst_rtype
connect issue_slots[14].out_uop.lrs3, slots_14.io.out_uop.lrs3
connect issue_slots[14].out_uop.lrs2, slots_14.io.out_uop.lrs2
connect issue_slots[14].out_uop.lrs1, slots_14.io.out_uop.lrs1
connect issue_slots[14].out_uop.ldst, slots_14.io.out_uop.ldst
connect issue_slots[14].out_uop.ldst_is_rs1, slots_14.io.out_uop.ldst_is_rs1
connect issue_slots[14].out_uop.csr_cmd, slots_14.io.out_uop.csr_cmd
connect issue_slots[14].out_uop.flush_on_commit, slots_14.io.out_uop.flush_on_commit
connect issue_slots[14].out_uop.is_unique, slots_14.io.out_uop.is_unique
connect issue_slots[14].out_uop.uses_stq, slots_14.io.out_uop.uses_stq
connect issue_slots[14].out_uop.uses_ldq, slots_14.io.out_uop.uses_ldq
connect issue_slots[14].out_uop.mem_signed, slots_14.io.out_uop.mem_signed
connect issue_slots[14].out_uop.mem_size, slots_14.io.out_uop.mem_size
connect issue_slots[14].out_uop.mem_cmd, slots_14.io.out_uop.mem_cmd
connect issue_slots[14].out_uop.exc_cause, slots_14.io.out_uop.exc_cause
connect issue_slots[14].out_uop.exception, slots_14.io.out_uop.exception
connect issue_slots[14].out_uop.stale_pdst, slots_14.io.out_uop.stale_pdst
connect issue_slots[14].out_uop.ppred_busy, slots_14.io.out_uop.ppred_busy
connect issue_slots[14].out_uop.prs3_busy, slots_14.io.out_uop.prs3_busy
connect issue_slots[14].out_uop.prs2_busy, slots_14.io.out_uop.prs2_busy
connect issue_slots[14].out_uop.prs1_busy, slots_14.io.out_uop.prs1_busy
connect issue_slots[14].out_uop.ppred, slots_14.io.out_uop.ppred
connect issue_slots[14].out_uop.prs3, slots_14.io.out_uop.prs3
connect issue_slots[14].out_uop.prs2, slots_14.io.out_uop.prs2
connect issue_slots[14].out_uop.prs1, slots_14.io.out_uop.prs1
connect issue_slots[14].out_uop.pdst, slots_14.io.out_uop.pdst
connect issue_slots[14].out_uop.rxq_idx, slots_14.io.out_uop.rxq_idx
connect issue_slots[14].out_uop.stq_idx, slots_14.io.out_uop.stq_idx
connect issue_slots[14].out_uop.ldq_idx, slots_14.io.out_uop.ldq_idx
connect issue_slots[14].out_uop.rob_idx, slots_14.io.out_uop.rob_idx
connect issue_slots[14].out_uop.fp_ctrl.vec, slots_14.io.out_uop.fp_ctrl.vec
connect issue_slots[14].out_uop.fp_ctrl.wflags, slots_14.io.out_uop.fp_ctrl.wflags
connect issue_slots[14].out_uop.fp_ctrl.sqrt, slots_14.io.out_uop.fp_ctrl.sqrt
connect issue_slots[14].out_uop.fp_ctrl.div, slots_14.io.out_uop.fp_ctrl.div
connect issue_slots[14].out_uop.fp_ctrl.fma, slots_14.io.out_uop.fp_ctrl.fma
connect issue_slots[14].out_uop.fp_ctrl.fastpipe, slots_14.io.out_uop.fp_ctrl.fastpipe
connect issue_slots[14].out_uop.fp_ctrl.toint, slots_14.io.out_uop.fp_ctrl.toint
connect issue_slots[14].out_uop.fp_ctrl.fromint, slots_14.io.out_uop.fp_ctrl.fromint
connect issue_slots[14].out_uop.fp_ctrl.typeTagOut, slots_14.io.out_uop.fp_ctrl.typeTagOut
connect issue_slots[14].out_uop.fp_ctrl.typeTagIn, slots_14.io.out_uop.fp_ctrl.typeTagIn
connect issue_slots[14].out_uop.fp_ctrl.swap23, slots_14.io.out_uop.fp_ctrl.swap23
connect issue_slots[14].out_uop.fp_ctrl.swap12, slots_14.io.out_uop.fp_ctrl.swap12
connect issue_slots[14].out_uop.fp_ctrl.ren3, slots_14.io.out_uop.fp_ctrl.ren3
connect issue_slots[14].out_uop.fp_ctrl.ren2, slots_14.io.out_uop.fp_ctrl.ren2
connect issue_slots[14].out_uop.fp_ctrl.ren1, slots_14.io.out_uop.fp_ctrl.ren1
connect issue_slots[14].out_uop.fp_ctrl.wen, slots_14.io.out_uop.fp_ctrl.wen
connect issue_slots[14].out_uop.fp_ctrl.ldst, slots_14.io.out_uop.fp_ctrl.ldst
connect issue_slots[14].out_uop.op2_sel, slots_14.io.out_uop.op2_sel
connect issue_slots[14].out_uop.op1_sel, slots_14.io.out_uop.op1_sel
connect issue_slots[14].out_uop.imm_packed, slots_14.io.out_uop.imm_packed
connect issue_slots[14].out_uop.pimm, slots_14.io.out_uop.pimm
connect issue_slots[14].out_uop.imm_sel, slots_14.io.out_uop.imm_sel
connect issue_slots[14].out_uop.imm_rename, slots_14.io.out_uop.imm_rename
connect issue_slots[14].out_uop.taken, slots_14.io.out_uop.taken
connect issue_slots[14].out_uop.pc_lob, slots_14.io.out_uop.pc_lob
connect issue_slots[14].out_uop.edge_inst, slots_14.io.out_uop.edge_inst
connect issue_slots[14].out_uop.ftq_idx, slots_14.io.out_uop.ftq_idx
connect issue_slots[14].out_uop.is_mov, slots_14.io.out_uop.is_mov
connect issue_slots[14].out_uop.is_rocc, slots_14.io.out_uop.is_rocc
connect issue_slots[14].out_uop.is_sys_pc2epc, slots_14.io.out_uop.is_sys_pc2epc
connect issue_slots[14].out_uop.is_eret, slots_14.io.out_uop.is_eret
connect issue_slots[14].out_uop.is_amo, slots_14.io.out_uop.is_amo
connect issue_slots[14].out_uop.is_sfence, slots_14.io.out_uop.is_sfence
connect issue_slots[14].out_uop.is_fencei, slots_14.io.out_uop.is_fencei
connect issue_slots[14].out_uop.is_fence, slots_14.io.out_uop.is_fence
connect issue_slots[14].out_uop.is_sfb, slots_14.io.out_uop.is_sfb
connect issue_slots[14].out_uop.br_type, slots_14.io.out_uop.br_type
connect issue_slots[14].out_uop.br_tag, slots_14.io.out_uop.br_tag
connect issue_slots[14].out_uop.br_mask, slots_14.io.out_uop.br_mask
connect issue_slots[14].out_uop.dis_col_sel, slots_14.io.out_uop.dis_col_sel
connect issue_slots[14].out_uop.iw_p3_bypass_hint, slots_14.io.out_uop.iw_p3_bypass_hint
connect issue_slots[14].out_uop.iw_p2_bypass_hint, slots_14.io.out_uop.iw_p2_bypass_hint
connect issue_slots[14].out_uop.iw_p1_bypass_hint, slots_14.io.out_uop.iw_p1_bypass_hint
connect issue_slots[14].out_uop.iw_p2_speculative_child, slots_14.io.out_uop.iw_p2_speculative_child
connect issue_slots[14].out_uop.iw_p1_speculative_child, slots_14.io.out_uop.iw_p1_speculative_child
connect issue_slots[14].out_uop.iw_issued_partial_dgen, slots_14.io.out_uop.iw_issued_partial_dgen
connect issue_slots[14].out_uop.iw_issued_partial_agen, slots_14.io.out_uop.iw_issued_partial_agen
connect issue_slots[14].out_uop.iw_issued, slots_14.io.out_uop.iw_issued
connect issue_slots[14].out_uop.fu_code[0], slots_14.io.out_uop.fu_code[0]
connect issue_slots[14].out_uop.fu_code[1], slots_14.io.out_uop.fu_code[1]
connect issue_slots[14].out_uop.fu_code[2], slots_14.io.out_uop.fu_code[2]
connect issue_slots[14].out_uop.fu_code[3], slots_14.io.out_uop.fu_code[3]
connect issue_slots[14].out_uop.fu_code[4], slots_14.io.out_uop.fu_code[4]
connect issue_slots[14].out_uop.fu_code[5], slots_14.io.out_uop.fu_code[5]
connect issue_slots[14].out_uop.fu_code[6], slots_14.io.out_uop.fu_code[6]
connect issue_slots[14].out_uop.fu_code[7], slots_14.io.out_uop.fu_code[7]
connect issue_slots[14].out_uop.fu_code[8], slots_14.io.out_uop.fu_code[8]
connect issue_slots[14].out_uop.fu_code[9], slots_14.io.out_uop.fu_code[9]
connect issue_slots[14].out_uop.iq_type[0], slots_14.io.out_uop.iq_type[0]
connect issue_slots[14].out_uop.iq_type[1], slots_14.io.out_uop.iq_type[1]
connect issue_slots[14].out_uop.iq_type[2], slots_14.io.out_uop.iq_type[2]
connect issue_slots[14].out_uop.iq_type[3], slots_14.io.out_uop.iq_type[3]
connect issue_slots[14].out_uop.debug_pc, slots_14.io.out_uop.debug_pc
connect issue_slots[14].out_uop.is_rvc, slots_14.io.out_uop.is_rvc
connect issue_slots[14].out_uop.debug_inst, slots_14.io.out_uop.debug_inst
connect issue_slots[14].out_uop.inst, slots_14.io.out_uop.inst
connect slots_14.io.in_uop.bits.debug_tsrc, issue_slots[14].in_uop.bits.debug_tsrc
connect slots_14.io.in_uop.bits.debug_fsrc, issue_slots[14].in_uop.bits.debug_fsrc
connect slots_14.io.in_uop.bits.bp_xcpt_if, issue_slots[14].in_uop.bits.bp_xcpt_if
connect slots_14.io.in_uop.bits.bp_debug_if, issue_slots[14].in_uop.bits.bp_debug_if
connect slots_14.io.in_uop.bits.xcpt_ma_if, issue_slots[14].in_uop.bits.xcpt_ma_if
connect slots_14.io.in_uop.bits.xcpt_ae_if, issue_slots[14].in_uop.bits.xcpt_ae_if
connect slots_14.io.in_uop.bits.xcpt_pf_if, issue_slots[14].in_uop.bits.xcpt_pf_if
connect slots_14.io.in_uop.bits.fp_typ, issue_slots[14].in_uop.bits.fp_typ
connect slots_14.io.in_uop.bits.fp_rm, issue_slots[14].in_uop.bits.fp_rm
connect slots_14.io.in_uop.bits.fp_val, issue_slots[14].in_uop.bits.fp_val
connect slots_14.io.in_uop.bits.fcn_op, issue_slots[14].in_uop.bits.fcn_op
connect slots_14.io.in_uop.bits.fcn_dw, issue_slots[14].in_uop.bits.fcn_dw
connect slots_14.io.in_uop.bits.frs3_en, issue_slots[14].in_uop.bits.frs3_en
connect slots_14.io.in_uop.bits.lrs2_rtype, issue_slots[14].in_uop.bits.lrs2_rtype
connect slots_14.io.in_uop.bits.lrs1_rtype, issue_slots[14].in_uop.bits.lrs1_rtype
connect slots_14.io.in_uop.bits.dst_rtype, issue_slots[14].in_uop.bits.dst_rtype
connect slots_14.io.in_uop.bits.lrs3, issue_slots[14].in_uop.bits.lrs3
connect slots_14.io.in_uop.bits.lrs2, issue_slots[14].in_uop.bits.lrs2
connect slots_14.io.in_uop.bits.lrs1, issue_slots[14].in_uop.bits.lrs1
connect slots_14.io.in_uop.bits.ldst, issue_slots[14].in_uop.bits.ldst
connect slots_14.io.in_uop.bits.ldst_is_rs1, issue_slots[14].in_uop.bits.ldst_is_rs1
connect slots_14.io.in_uop.bits.csr_cmd, issue_slots[14].in_uop.bits.csr_cmd
connect slots_14.io.in_uop.bits.flush_on_commit, issue_slots[14].in_uop.bits.flush_on_commit
connect slots_14.io.in_uop.bits.is_unique, issue_slots[14].in_uop.bits.is_unique
connect slots_14.io.in_uop.bits.uses_stq, issue_slots[14].in_uop.bits.uses_stq
connect slots_14.io.in_uop.bits.uses_ldq, issue_slots[14].in_uop.bits.uses_ldq
connect slots_14.io.in_uop.bits.mem_signed, issue_slots[14].in_uop.bits.mem_signed
connect slots_14.io.in_uop.bits.mem_size, issue_slots[14].in_uop.bits.mem_size
connect slots_14.io.in_uop.bits.mem_cmd, issue_slots[14].in_uop.bits.mem_cmd
connect slots_14.io.in_uop.bits.exc_cause, issue_slots[14].in_uop.bits.exc_cause
connect slots_14.io.in_uop.bits.exception, issue_slots[14].in_uop.bits.exception
connect slots_14.io.in_uop.bits.stale_pdst, issue_slots[14].in_uop.bits.stale_pdst
connect slots_14.io.in_uop.bits.ppred_busy, issue_slots[14].in_uop.bits.ppred_busy
connect slots_14.io.in_uop.bits.prs3_busy, issue_slots[14].in_uop.bits.prs3_busy
connect slots_14.io.in_uop.bits.prs2_busy, issue_slots[14].in_uop.bits.prs2_busy
connect slots_14.io.in_uop.bits.prs1_busy, issue_slots[14].in_uop.bits.prs1_busy
connect slots_14.io.in_uop.bits.ppred, issue_slots[14].in_uop.bits.ppred
connect slots_14.io.in_uop.bits.prs3, issue_slots[14].in_uop.bits.prs3
connect slots_14.io.in_uop.bits.prs2, issue_slots[14].in_uop.bits.prs2
connect slots_14.io.in_uop.bits.prs1, issue_slots[14].in_uop.bits.prs1
connect slots_14.io.in_uop.bits.pdst, issue_slots[14].in_uop.bits.pdst
connect slots_14.io.in_uop.bits.rxq_idx, issue_slots[14].in_uop.bits.rxq_idx
connect slots_14.io.in_uop.bits.stq_idx, issue_slots[14].in_uop.bits.stq_idx
connect slots_14.io.in_uop.bits.ldq_idx, issue_slots[14].in_uop.bits.ldq_idx
connect slots_14.io.in_uop.bits.rob_idx, issue_slots[14].in_uop.bits.rob_idx
connect slots_14.io.in_uop.bits.fp_ctrl.vec, issue_slots[14].in_uop.bits.fp_ctrl.vec
connect slots_14.io.in_uop.bits.fp_ctrl.wflags, issue_slots[14].in_uop.bits.fp_ctrl.wflags
connect slots_14.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[14].in_uop.bits.fp_ctrl.sqrt
connect slots_14.io.in_uop.bits.fp_ctrl.div, issue_slots[14].in_uop.bits.fp_ctrl.div
connect slots_14.io.in_uop.bits.fp_ctrl.fma, issue_slots[14].in_uop.bits.fp_ctrl.fma
connect slots_14.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[14].in_uop.bits.fp_ctrl.fastpipe
connect slots_14.io.in_uop.bits.fp_ctrl.toint, issue_slots[14].in_uop.bits.fp_ctrl.toint
connect slots_14.io.in_uop.bits.fp_ctrl.fromint, issue_slots[14].in_uop.bits.fp_ctrl.fromint
connect slots_14.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[14].in_uop.bits.fp_ctrl.typeTagOut
connect slots_14.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[14].in_uop.bits.fp_ctrl.typeTagIn
connect slots_14.io.in_uop.bits.fp_ctrl.swap23, issue_slots[14].in_uop.bits.fp_ctrl.swap23
connect slots_14.io.in_uop.bits.fp_ctrl.swap12, issue_slots[14].in_uop.bits.fp_ctrl.swap12
connect slots_14.io.in_uop.bits.fp_ctrl.ren3, issue_slots[14].in_uop.bits.fp_ctrl.ren3
connect slots_14.io.in_uop.bits.fp_ctrl.ren2, issue_slots[14].in_uop.bits.fp_ctrl.ren2
connect slots_14.io.in_uop.bits.fp_ctrl.ren1, issue_slots[14].in_uop.bits.fp_ctrl.ren1
connect slots_14.io.in_uop.bits.fp_ctrl.wen, issue_slots[14].in_uop.bits.fp_ctrl.wen
connect slots_14.io.in_uop.bits.fp_ctrl.ldst, issue_slots[14].in_uop.bits.fp_ctrl.ldst
connect slots_14.io.in_uop.bits.op2_sel, issue_slots[14].in_uop.bits.op2_sel
connect slots_14.io.in_uop.bits.op1_sel, issue_slots[14].in_uop.bits.op1_sel
connect slots_14.io.in_uop.bits.imm_packed, issue_slots[14].in_uop.bits.imm_packed
connect slots_14.io.in_uop.bits.pimm, issue_slots[14].in_uop.bits.pimm
connect slots_14.io.in_uop.bits.imm_sel, issue_slots[14].in_uop.bits.imm_sel
connect slots_14.io.in_uop.bits.imm_rename, issue_slots[14].in_uop.bits.imm_rename
connect slots_14.io.in_uop.bits.taken, issue_slots[14].in_uop.bits.taken
connect slots_14.io.in_uop.bits.pc_lob, issue_slots[14].in_uop.bits.pc_lob
connect slots_14.io.in_uop.bits.edge_inst, issue_slots[14].in_uop.bits.edge_inst
connect slots_14.io.in_uop.bits.ftq_idx, issue_slots[14].in_uop.bits.ftq_idx
connect slots_14.io.in_uop.bits.is_mov, issue_slots[14].in_uop.bits.is_mov
connect slots_14.io.in_uop.bits.is_rocc, issue_slots[14].in_uop.bits.is_rocc
connect slots_14.io.in_uop.bits.is_sys_pc2epc, issue_slots[14].in_uop.bits.is_sys_pc2epc
connect slots_14.io.in_uop.bits.is_eret, issue_slots[14].in_uop.bits.is_eret
connect slots_14.io.in_uop.bits.is_amo, issue_slots[14].in_uop.bits.is_amo
connect slots_14.io.in_uop.bits.is_sfence, issue_slots[14].in_uop.bits.is_sfence
connect slots_14.io.in_uop.bits.is_fencei, issue_slots[14].in_uop.bits.is_fencei
connect slots_14.io.in_uop.bits.is_fence, issue_slots[14].in_uop.bits.is_fence
connect slots_14.io.in_uop.bits.is_sfb, issue_slots[14].in_uop.bits.is_sfb
connect slots_14.io.in_uop.bits.br_type, issue_slots[14].in_uop.bits.br_type
connect slots_14.io.in_uop.bits.br_tag, issue_slots[14].in_uop.bits.br_tag
connect slots_14.io.in_uop.bits.br_mask, issue_slots[14].in_uop.bits.br_mask
connect slots_14.io.in_uop.bits.dis_col_sel, issue_slots[14].in_uop.bits.dis_col_sel
connect slots_14.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[14].in_uop.bits.iw_p3_bypass_hint
connect slots_14.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[14].in_uop.bits.iw_p2_bypass_hint
connect slots_14.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[14].in_uop.bits.iw_p1_bypass_hint
connect slots_14.io.in_uop.bits.iw_p2_speculative_child, issue_slots[14].in_uop.bits.iw_p2_speculative_child
connect slots_14.io.in_uop.bits.iw_p1_speculative_child, issue_slots[14].in_uop.bits.iw_p1_speculative_child
connect slots_14.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[14].in_uop.bits.iw_issued_partial_dgen
connect slots_14.io.in_uop.bits.iw_issued_partial_agen, issue_slots[14].in_uop.bits.iw_issued_partial_agen
connect slots_14.io.in_uop.bits.iw_issued, issue_slots[14].in_uop.bits.iw_issued
connect slots_14.io.in_uop.bits.fu_code[0], issue_slots[14].in_uop.bits.fu_code[0]
connect slots_14.io.in_uop.bits.fu_code[1], issue_slots[14].in_uop.bits.fu_code[1]
connect slots_14.io.in_uop.bits.fu_code[2], issue_slots[14].in_uop.bits.fu_code[2]
connect slots_14.io.in_uop.bits.fu_code[3], issue_slots[14].in_uop.bits.fu_code[3]
connect slots_14.io.in_uop.bits.fu_code[4], issue_slots[14].in_uop.bits.fu_code[4]
connect slots_14.io.in_uop.bits.fu_code[5], issue_slots[14].in_uop.bits.fu_code[5]
connect slots_14.io.in_uop.bits.fu_code[6], issue_slots[14].in_uop.bits.fu_code[6]
connect slots_14.io.in_uop.bits.fu_code[7], issue_slots[14].in_uop.bits.fu_code[7]
connect slots_14.io.in_uop.bits.fu_code[8], issue_slots[14].in_uop.bits.fu_code[8]
connect slots_14.io.in_uop.bits.fu_code[9], issue_slots[14].in_uop.bits.fu_code[9]
connect slots_14.io.in_uop.bits.iq_type[0], issue_slots[14].in_uop.bits.iq_type[0]
connect slots_14.io.in_uop.bits.iq_type[1], issue_slots[14].in_uop.bits.iq_type[1]
connect slots_14.io.in_uop.bits.iq_type[2], issue_slots[14].in_uop.bits.iq_type[2]
connect slots_14.io.in_uop.bits.iq_type[3], issue_slots[14].in_uop.bits.iq_type[3]
connect slots_14.io.in_uop.bits.debug_pc, issue_slots[14].in_uop.bits.debug_pc
connect slots_14.io.in_uop.bits.is_rvc, issue_slots[14].in_uop.bits.is_rvc
connect slots_14.io.in_uop.bits.debug_inst, issue_slots[14].in_uop.bits.debug_inst
connect slots_14.io.in_uop.bits.inst, issue_slots[14].in_uop.bits.inst
connect slots_14.io.in_uop.valid, issue_slots[14].in_uop.valid
connect issue_slots[14].iss_uop.debug_tsrc, slots_14.io.iss_uop.debug_tsrc
connect issue_slots[14].iss_uop.debug_fsrc, slots_14.io.iss_uop.debug_fsrc
connect issue_slots[14].iss_uop.bp_xcpt_if, slots_14.io.iss_uop.bp_xcpt_if
connect issue_slots[14].iss_uop.bp_debug_if, slots_14.io.iss_uop.bp_debug_if
connect issue_slots[14].iss_uop.xcpt_ma_if, slots_14.io.iss_uop.xcpt_ma_if
connect issue_slots[14].iss_uop.xcpt_ae_if, slots_14.io.iss_uop.xcpt_ae_if
connect issue_slots[14].iss_uop.xcpt_pf_if, slots_14.io.iss_uop.xcpt_pf_if
connect issue_slots[14].iss_uop.fp_typ, slots_14.io.iss_uop.fp_typ
connect issue_slots[14].iss_uop.fp_rm, slots_14.io.iss_uop.fp_rm
connect issue_slots[14].iss_uop.fp_val, slots_14.io.iss_uop.fp_val
connect issue_slots[14].iss_uop.fcn_op, slots_14.io.iss_uop.fcn_op
connect issue_slots[14].iss_uop.fcn_dw, slots_14.io.iss_uop.fcn_dw
connect issue_slots[14].iss_uop.frs3_en, slots_14.io.iss_uop.frs3_en
connect issue_slots[14].iss_uop.lrs2_rtype, slots_14.io.iss_uop.lrs2_rtype
connect issue_slots[14].iss_uop.lrs1_rtype, slots_14.io.iss_uop.lrs1_rtype
connect issue_slots[14].iss_uop.dst_rtype, slots_14.io.iss_uop.dst_rtype
connect issue_slots[14].iss_uop.lrs3, slots_14.io.iss_uop.lrs3
connect issue_slots[14].iss_uop.lrs2, slots_14.io.iss_uop.lrs2
connect issue_slots[14].iss_uop.lrs1, slots_14.io.iss_uop.lrs1
connect issue_slots[14].iss_uop.ldst, slots_14.io.iss_uop.ldst
connect issue_slots[14].iss_uop.ldst_is_rs1, slots_14.io.iss_uop.ldst_is_rs1
connect issue_slots[14].iss_uop.csr_cmd, slots_14.io.iss_uop.csr_cmd
connect issue_slots[14].iss_uop.flush_on_commit, slots_14.io.iss_uop.flush_on_commit
connect issue_slots[14].iss_uop.is_unique, slots_14.io.iss_uop.is_unique
connect issue_slots[14].iss_uop.uses_stq, slots_14.io.iss_uop.uses_stq
connect issue_slots[14].iss_uop.uses_ldq, slots_14.io.iss_uop.uses_ldq
connect issue_slots[14].iss_uop.mem_signed, slots_14.io.iss_uop.mem_signed
connect issue_slots[14].iss_uop.mem_size, slots_14.io.iss_uop.mem_size
connect issue_slots[14].iss_uop.mem_cmd, slots_14.io.iss_uop.mem_cmd
connect issue_slots[14].iss_uop.exc_cause, slots_14.io.iss_uop.exc_cause
connect issue_slots[14].iss_uop.exception, slots_14.io.iss_uop.exception
connect issue_slots[14].iss_uop.stale_pdst, slots_14.io.iss_uop.stale_pdst
connect issue_slots[14].iss_uop.ppred_busy, slots_14.io.iss_uop.ppred_busy
connect issue_slots[14].iss_uop.prs3_busy, slots_14.io.iss_uop.prs3_busy
connect issue_slots[14].iss_uop.prs2_busy, slots_14.io.iss_uop.prs2_busy
connect issue_slots[14].iss_uop.prs1_busy, slots_14.io.iss_uop.prs1_busy
connect issue_slots[14].iss_uop.ppred, slots_14.io.iss_uop.ppred
connect issue_slots[14].iss_uop.prs3, slots_14.io.iss_uop.prs3
connect issue_slots[14].iss_uop.prs2, slots_14.io.iss_uop.prs2
connect issue_slots[14].iss_uop.prs1, slots_14.io.iss_uop.prs1
connect issue_slots[14].iss_uop.pdst, slots_14.io.iss_uop.pdst
connect issue_slots[14].iss_uop.rxq_idx, slots_14.io.iss_uop.rxq_idx
connect issue_slots[14].iss_uop.stq_idx, slots_14.io.iss_uop.stq_idx
connect issue_slots[14].iss_uop.ldq_idx, slots_14.io.iss_uop.ldq_idx
connect issue_slots[14].iss_uop.rob_idx, slots_14.io.iss_uop.rob_idx
connect issue_slots[14].iss_uop.fp_ctrl.vec, slots_14.io.iss_uop.fp_ctrl.vec
connect issue_slots[14].iss_uop.fp_ctrl.wflags, slots_14.io.iss_uop.fp_ctrl.wflags
connect issue_slots[14].iss_uop.fp_ctrl.sqrt, slots_14.io.iss_uop.fp_ctrl.sqrt
connect issue_slots[14].iss_uop.fp_ctrl.div, slots_14.io.iss_uop.fp_ctrl.div
connect issue_slots[14].iss_uop.fp_ctrl.fma, slots_14.io.iss_uop.fp_ctrl.fma
connect issue_slots[14].iss_uop.fp_ctrl.fastpipe, slots_14.io.iss_uop.fp_ctrl.fastpipe
connect issue_slots[14].iss_uop.fp_ctrl.toint, slots_14.io.iss_uop.fp_ctrl.toint
connect issue_slots[14].iss_uop.fp_ctrl.fromint, slots_14.io.iss_uop.fp_ctrl.fromint
connect issue_slots[14].iss_uop.fp_ctrl.typeTagOut, slots_14.io.iss_uop.fp_ctrl.typeTagOut
connect issue_slots[14].iss_uop.fp_ctrl.typeTagIn, slots_14.io.iss_uop.fp_ctrl.typeTagIn
connect issue_slots[14].iss_uop.fp_ctrl.swap23, slots_14.io.iss_uop.fp_ctrl.swap23
connect issue_slots[14].iss_uop.fp_ctrl.swap12, slots_14.io.iss_uop.fp_ctrl.swap12
connect issue_slots[14].iss_uop.fp_ctrl.ren3, slots_14.io.iss_uop.fp_ctrl.ren3
connect issue_slots[14].iss_uop.fp_ctrl.ren2, slots_14.io.iss_uop.fp_ctrl.ren2
connect issue_slots[14].iss_uop.fp_ctrl.ren1, slots_14.io.iss_uop.fp_ctrl.ren1
connect issue_slots[14].iss_uop.fp_ctrl.wen, slots_14.io.iss_uop.fp_ctrl.wen
connect issue_slots[14].iss_uop.fp_ctrl.ldst, slots_14.io.iss_uop.fp_ctrl.ldst
connect issue_slots[14].iss_uop.op2_sel, slots_14.io.iss_uop.op2_sel
connect issue_slots[14].iss_uop.op1_sel, slots_14.io.iss_uop.op1_sel
connect issue_slots[14].iss_uop.imm_packed, slots_14.io.iss_uop.imm_packed
connect issue_slots[14].iss_uop.pimm, slots_14.io.iss_uop.pimm
connect issue_slots[14].iss_uop.imm_sel, slots_14.io.iss_uop.imm_sel
connect issue_slots[14].iss_uop.imm_rename, slots_14.io.iss_uop.imm_rename
connect issue_slots[14].iss_uop.taken, slots_14.io.iss_uop.taken
connect issue_slots[14].iss_uop.pc_lob, slots_14.io.iss_uop.pc_lob
connect issue_slots[14].iss_uop.edge_inst, slots_14.io.iss_uop.edge_inst
connect issue_slots[14].iss_uop.ftq_idx, slots_14.io.iss_uop.ftq_idx
connect issue_slots[14].iss_uop.is_mov, slots_14.io.iss_uop.is_mov
connect issue_slots[14].iss_uop.is_rocc, slots_14.io.iss_uop.is_rocc
connect issue_slots[14].iss_uop.is_sys_pc2epc, slots_14.io.iss_uop.is_sys_pc2epc
connect issue_slots[14].iss_uop.is_eret, slots_14.io.iss_uop.is_eret
connect issue_slots[14].iss_uop.is_amo, slots_14.io.iss_uop.is_amo
connect issue_slots[14].iss_uop.is_sfence, slots_14.io.iss_uop.is_sfence
connect issue_slots[14].iss_uop.is_fencei, slots_14.io.iss_uop.is_fencei
connect issue_slots[14].iss_uop.is_fence, slots_14.io.iss_uop.is_fence
connect issue_slots[14].iss_uop.is_sfb, slots_14.io.iss_uop.is_sfb
connect issue_slots[14].iss_uop.br_type, slots_14.io.iss_uop.br_type
connect issue_slots[14].iss_uop.br_tag, slots_14.io.iss_uop.br_tag
connect issue_slots[14].iss_uop.br_mask, slots_14.io.iss_uop.br_mask
connect issue_slots[14].iss_uop.dis_col_sel, slots_14.io.iss_uop.dis_col_sel
connect issue_slots[14].iss_uop.iw_p3_bypass_hint, slots_14.io.iss_uop.iw_p3_bypass_hint
connect issue_slots[14].iss_uop.iw_p2_bypass_hint, slots_14.io.iss_uop.iw_p2_bypass_hint
connect issue_slots[14].iss_uop.iw_p1_bypass_hint, slots_14.io.iss_uop.iw_p1_bypass_hint
connect issue_slots[14].iss_uop.iw_p2_speculative_child, slots_14.io.iss_uop.iw_p2_speculative_child
connect issue_slots[14].iss_uop.iw_p1_speculative_child, slots_14.io.iss_uop.iw_p1_speculative_child
connect issue_slots[14].iss_uop.iw_issued_partial_dgen, slots_14.io.iss_uop.iw_issued_partial_dgen
connect issue_slots[14].iss_uop.iw_issued_partial_agen, slots_14.io.iss_uop.iw_issued_partial_agen
connect issue_slots[14].iss_uop.iw_issued, slots_14.io.iss_uop.iw_issued
connect issue_slots[14].iss_uop.fu_code[0], slots_14.io.iss_uop.fu_code[0]
connect issue_slots[14].iss_uop.fu_code[1], slots_14.io.iss_uop.fu_code[1]
connect issue_slots[14].iss_uop.fu_code[2], slots_14.io.iss_uop.fu_code[2]
connect issue_slots[14].iss_uop.fu_code[3], slots_14.io.iss_uop.fu_code[3]
connect issue_slots[14].iss_uop.fu_code[4], slots_14.io.iss_uop.fu_code[4]
connect issue_slots[14].iss_uop.fu_code[5], slots_14.io.iss_uop.fu_code[5]
connect issue_slots[14].iss_uop.fu_code[6], slots_14.io.iss_uop.fu_code[6]
connect issue_slots[14].iss_uop.fu_code[7], slots_14.io.iss_uop.fu_code[7]
connect issue_slots[14].iss_uop.fu_code[8], slots_14.io.iss_uop.fu_code[8]
connect issue_slots[14].iss_uop.fu_code[9], slots_14.io.iss_uop.fu_code[9]
connect issue_slots[14].iss_uop.iq_type[0], slots_14.io.iss_uop.iq_type[0]
connect issue_slots[14].iss_uop.iq_type[1], slots_14.io.iss_uop.iq_type[1]
connect issue_slots[14].iss_uop.iq_type[2], slots_14.io.iss_uop.iq_type[2]
connect issue_slots[14].iss_uop.iq_type[3], slots_14.io.iss_uop.iq_type[3]
connect issue_slots[14].iss_uop.debug_pc, slots_14.io.iss_uop.debug_pc
connect issue_slots[14].iss_uop.is_rvc, slots_14.io.iss_uop.is_rvc
connect issue_slots[14].iss_uop.debug_inst, slots_14.io.iss_uop.debug_inst
connect issue_slots[14].iss_uop.inst, slots_14.io.iss_uop.inst
connect slots_14.io.grant, issue_slots[14].grant
connect issue_slots[14].request, slots_14.io.request
connect issue_slots[14].will_be_valid, slots_14.io.will_be_valid
connect issue_slots[14].valid, slots_14.io.valid
connect slots_15.io.child_rebusys, issue_slots[15].child_rebusys
connect slots_15.io.pred_wakeup_port.bits, issue_slots[15].pred_wakeup_port.bits
connect slots_15.io.pred_wakeup_port.valid, issue_slots[15].pred_wakeup_port.valid
connect slots_15.io.wakeup_ports[0].bits.rebusy, issue_slots[15].wakeup_ports[0].bits.rebusy
connect slots_15.io.wakeup_ports[0].bits.speculative_mask, issue_slots[15].wakeup_ports[0].bits.speculative_mask
connect slots_15.io.wakeup_ports[0].bits.bypassable, issue_slots[15].wakeup_ports[0].bits.bypassable
connect slots_15.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[15].wakeup_ports[0].bits.uop.debug_tsrc
connect slots_15.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[15].wakeup_ports[0].bits.uop.debug_fsrc
connect slots_15.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[15].wakeup_ports[0].bits.uop.bp_xcpt_if
connect slots_15.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[15].wakeup_ports[0].bits.uop.bp_debug_if
connect slots_15.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[15].wakeup_ports[0].bits.uop.xcpt_ma_if
connect slots_15.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[15].wakeup_ports[0].bits.uop.xcpt_ae_if
connect slots_15.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[15].wakeup_ports[0].bits.uop.xcpt_pf_if
connect slots_15.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[15].wakeup_ports[0].bits.uop.fp_typ
connect slots_15.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[15].wakeup_ports[0].bits.uop.fp_rm
connect slots_15.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[15].wakeup_ports[0].bits.uop.fp_val
connect slots_15.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[15].wakeup_ports[0].bits.uop.fcn_op
connect slots_15.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[15].wakeup_ports[0].bits.uop.fcn_dw
connect slots_15.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[15].wakeup_ports[0].bits.uop.frs3_en
connect slots_15.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[15].wakeup_ports[0].bits.uop.lrs2_rtype
connect slots_15.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[15].wakeup_ports[0].bits.uop.lrs1_rtype
connect slots_15.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[15].wakeup_ports[0].bits.uop.dst_rtype
connect slots_15.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[15].wakeup_ports[0].bits.uop.lrs3
connect slots_15.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[15].wakeup_ports[0].bits.uop.lrs2
connect slots_15.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[15].wakeup_ports[0].bits.uop.lrs1
connect slots_15.io.wakeup_ports[0].bits.uop.ldst, issue_slots[15].wakeup_ports[0].bits.uop.ldst
connect slots_15.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[15].wakeup_ports[0].bits.uop.ldst_is_rs1
connect slots_15.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[15].wakeup_ports[0].bits.uop.csr_cmd
connect slots_15.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[15].wakeup_ports[0].bits.uop.flush_on_commit
connect slots_15.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[15].wakeup_ports[0].bits.uop.is_unique
connect slots_15.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[15].wakeup_ports[0].bits.uop.uses_stq
connect slots_15.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[15].wakeup_ports[0].bits.uop.uses_ldq
connect slots_15.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[15].wakeup_ports[0].bits.uop.mem_signed
connect slots_15.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[15].wakeup_ports[0].bits.uop.mem_size
connect slots_15.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[15].wakeup_ports[0].bits.uop.mem_cmd
connect slots_15.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[15].wakeup_ports[0].bits.uop.exc_cause
connect slots_15.io.wakeup_ports[0].bits.uop.exception, issue_slots[15].wakeup_ports[0].bits.uop.exception
connect slots_15.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[15].wakeup_ports[0].bits.uop.stale_pdst
connect slots_15.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[15].wakeup_ports[0].bits.uop.ppred_busy
connect slots_15.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[15].wakeup_ports[0].bits.uop.prs3_busy
connect slots_15.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[15].wakeup_ports[0].bits.uop.prs2_busy
connect slots_15.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[15].wakeup_ports[0].bits.uop.prs1_busy
connect slots_15.io.wakeup_ports[0].bits.uop.ppred, issue_slots[15].wakeup_ports[0].bits.uop.ppred
connect slots_15.io.wakeup_ports[0].bits.uop.prs3, issue_slots[15].wakeup_ports[0].bits.uop.prs3
connect slots_15.io.wakeup_ports[0].bits.uop.prs2, issue_slots[15].wakeup_ports[0].bits.uop.prs2
connect slots_15.io.wakeup_ports[0].bits.uop.prs1, issue_slots[15].wakeup_ports[0].bits.uop.prs1
connect slots_15.io.wakeup_ports[0].bits.uop.pdst, issue_slots[15].wakeup_ports[0].bits.uop.pdst
connect slots_15.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[15].wakeup_ports[0].bits.uop.rxq_idx
connect slots_15.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[15].wakeup_ports[0].bits.uop.stq_idx
connect slots_15.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[15].wakeup_ports[0].bits.uop.ldq_idx
connect slots_15.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[15].wakeup_ports[0].bits.uop.rob_idx
connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.vec
connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.wflags
connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.sqrt
connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.div
connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.fma
connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe
connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.toint
connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.fromint
connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut
connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn
connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.swap23
connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.swap12
connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.ren3
connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.ren2
connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.ren1
connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.wen
connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.ldst
connect slots_15.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[15].wakeup_ports[0].bits.uop.op2_sel
connect slots_15.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[15].wakeup_ports[0].bits.uop.op1_sel
connect slots_15.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[15].wakeup_ports[0].bits.uop.imm_packed
connect slots_15.io.wakeup_ports[0].bits.uop.pimm, issue_slots[15].wakeup_ports[0].bits.uop.pimm
connect slots_15.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[15].wakeup_ports[0].bits.uop.imm_sel
connect slots_15.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[15].wakeup_ports[0].bits.uop.imm_rename
connect slots_15.io.wakeup_ports[0].bits.uop.taken, issue_slots[15].wakeup_ports[0].bits.uop.taken
connect slots_15.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[15].wakeup_ports[0].bits.uop.pc_lob
connect slots_15.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[15].wakeup_ports[0].bits.uop.edge_inst
connect slots_15.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[15].wakeup_ports[0].bits.uop.ftq_idx
connect slots_15.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[15].wakeup_ports[0].bits.uop.is_mov
connect slots_15.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[15].wakeup_ports[0].bits.uop.is_rocc
connect slots_15.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[15].wakeup_ports[0].bits.uop.is_sys_pc2epc
connect slots_15.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[15].wakeup_ports[0].bits.uop.is_eret
connect slots_15.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[15].wakeup_ports[0].bits.uop.is_amo
connect slots_15.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[15].wakeup_ports[0].bits.uop.is_sfence
connect slots_15.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[15].wakeup_ports[0].bits.uop.is_fencei
connect slots_15.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[15].wakeup_ports[0].bits.uop.is_fence
connect slots_15.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[15].wakeup_ports[0].bits.uop.is_sfb
connect slots_15.io.wakeup_ports[0].bits.uop.br_type, issue_slots[15].wakeup_ports[0].bits.uop.br_type
connect slots_15.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[15].wakeup_ports[0].bits.uop.br_tag
connect slots_15.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[15].wakeup_ports[0].bits.uop.br_mask
connect slots_15.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[15].wakeup_ports[0].bits.uop.dis_col_sel
connect slots_15.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[15].wakeup_ports[0].bits.uop.iw_p3_bypass_hint
connect slots_15.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[15].wakeup_ports[0].bits.uop.iw_p2_bypass_hint
connect slots_15.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[15].wakeup_ports[0].bits.uop.iw_p1_bypass_hint
connect slots_15.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[15].wakeup_ports[0].bits.uop.iw_p2_speculative_child
connect slots_15.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[15].wakeup_ports[0].bits.uop.iw_p1_speculative_child
connect slots_15.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[15].wakeup_ports[0].bits.uop.iw_issued_partial_dgen
connect slots_15.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[15].wakeup_ports[0].bits.uop.iw_issued_partial_agen
connect slots_15.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[15].wakeup_ports[0].bits.uop.iw_issued
connect slots_15.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[15].wakeup_ports[0].bits.uop.fu_code[0]
connect slots_15.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[15].wakeup_ports[0].bits.uop.fu_code[1]
connect slots_15.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[15].wakeup_ports[0].bits.uop.fu_code[2]
connect slots_15.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[15].wakeup_ports[0].bits.uop.fu_code[3]
connect slots_15.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[15].wakeup_ports[0].bits.uop.fu_code[4]
connect slots_15.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[15].wakeup_ports[0].bits.uop.fu_code[5]
connect slots_15.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[15].wakeup_ports[0].bits.uop.fu_code[6]
connect slots_15.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[15].wakeup_ports[0].bits.uop.fu_code[7]
connect slots_15.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[15].wakeup_ports[0].bits.uop.fu_code[8]
connect slots_15.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[15].wakeup_ports[0].bits.uop.fu_code[9]
connect slots_15.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[15].wakeup_ports[0].bits.uop.iq_type[0]
connect slots_15.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[15].wakeup_ports[0].bits.uop.iq_type[1]
connect slots_15.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[15].wakeup_ports[0].bits.uop.iq_type[2]
connect slots_15.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[15].wakeup_ports[0].bits.uop.iq_type[3]
connect slots_15.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[15].wakeup_ports[0].bits.uop.debug_pc
connect slots_15.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[15].wakeup_ports[0].bits.uop.is_rvc
connect slots_15.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[15].wakeup_ports[0].bits.uop.debug_inst
connect slots_15.io.wakeup_ports[0].bits.uop.inst, issue_slots[15].wakeup_ports[0].bits.uop.inst
connect slots_15.io.wakeup_ports[0].valid, issue_slots[15].wakeup_ports[0].valid
connect slots_15.io.wakeup_ports[1].bits.rebusy, issue_slots[15].wakeup_ports[1].bits.rebusy
connect slots_15.io.wakeup_ports[1].bits.speculative_mask, issue_slots[15].wakeup_ports[1].bits.speculative_mask
connect slots_15.io.wakeup_ports[1].bits.bypassable, issue_slots[15].wakeup_ports[1].bits.bypassable
connect slots_15.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[15].wakeup_ports[1].bits.uop.debug_tsrc
connect slots_15.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[15].wakeup_ports[1].bits.uop.debug_fsrc
connect slots_15.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[15].wakeup_ports[1].bits.uop.bp_xcpt_if
connect slots_15.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[15].wakeup_ports[1].bits.uop.bp_debug_if
connect slots_15.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[15].wakeup_ports[1].bits.uop.xcpt_ma_if
connect slots_15.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[15].wakeup_ports[1].bits.uop.xcpt_ae_if
connect slots_15.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[15].wakeup_ports[1].bits.uop.xcpt_pf_if
connect slots_15.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[15].wakeup_ports[1].bits.uop.fp_typ
connect slots_15.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[15].wakeup_ports[1].bits.uop.fp_rm
connect slots_15.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[15].wakeup_ports[1].bits.uop.fp_val
connect slots_15.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[15].wakeup_ports[1].bits.uop.fcn_op
connect slots_15.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[15].wakeup_ports[1].bits.uop.fcn_dw
connect slots_15.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[15].wakeup_ports[1].bits.uop.frs3_en
connect slots_15.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[15].wakeup_ports[1].bits.uop.lrs2_rtype
connect slots_15.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[15].wakeup_ports[1].bits.uop.lrs1_rtype
connect slots_15.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[15].wakeup_ports[1].bits.uop.dst_rtype
connect slots_15.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[15].wakeup_ports[1].bits.uop.lrs3
connect slots_15.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[15].wakeup_ports[1].bits.uop.lrs2
connect slots_15.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[15].wakeup_ports[1].bits.uop.lrs1
connect slots_15.io.wakeup_ports[1].bits.uop.ldst, issue_slots[15].wakeup_ports[1].bits.uop.ldst
connect slots_15.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[15].wakeup_ports[1].bits.uop.ldst_is_rs1
connect slots_15.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[15].wakeup_ports[1].bits.uop.csr_cmd
connect slots_15.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[15].wakeup_ports[1].bits.uop.flush_on_commit
connect slots_15.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[15].wakeup_ports[1].bits.uop.is_unique
connect slots_15.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[15].wakeup_ports[1].bits.uop.uses_stq
connect slots_15.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[15].wakeup_ports[1].bits.uop.uses_ldq
connect slots_15.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[15].wakeup_ports[1].bits.uop.mem_signed
connect slots_15.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[15].wakeup_ports[1].bits.uop.mem_size
connect slots_15.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[15].wakeup_ports[1].bits.uop.mem_cmd
connect slots_15.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[15].wakeup_ports[1].bits.uop.exc_cause
connect slots_15.io.wakeup_ports[1].bits.uop.exception, issue_slots[15].wakeup_ports[1].bits.uop.exception
connect slots_15.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[15].wakeup_ports[1].bits.uop.stale_pdst
connect slots_15.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[15].wakeup_ports[1].bits.uop.ppred_busy
connect slots_15.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[15].wakeup_ports[1].bits.uop.prs3_busy
connect slots_15.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[15].wakeup_ports[1].bits.uop.prs2_busy
connect slots_15.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[15].wakeup_ports[1].bits.uop.prs1_busy
connect slots_15.io.wakeup_ports[1].bits.uop.ppred, issue_slots[15].wakeup_ports[1].bits.uop.ppred
connect slots_15.io.wakeup_ports[1].bits.uop.prs3, issue_slots[15].wakeup_ports[1].bits.uop.prs3
connect slots_15.io.wakeup_ports[1].bits.uop.prs2, issue_slots[15].wakeup_ports[1].bits.uop.prs2
connect slots_15.io.wakeup_ports[1].bits.uop.prs1, issue_slots[15].wakeup_ports[1].bits.uop.prs1
connect slots_15.io.wakeup_ports[1].bits.uop.pdst, issue_slots[15].wakeup_ports[1].bits.uop.pdst
connect slots_15.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[15].wakeup_ports[1].bits.uop.rxq_idx
connect slots_15.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[15].wakeup_ports[1].bits.uop.stq_idx
connect slots_15.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[15].wakeup_ports[1].bits.uop.ldq_idx
connect slots_15.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[15].wakeup_ports[1].bits.uop.rob_idx
connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.vec
connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.wflags
connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.sqrt
connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.div
connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.fma
connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe
connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.toint
connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.fromint
connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut
connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn
connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.swap23
connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.swap12
connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.ren3
connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.ren2
connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.ren1
connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.wen
connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.ldst
connect slots_15.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[15].wakeup_ports[1].bits.uop.op2_sel
connect slots_15.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[15].wakeup_ports[1].bits.uop.op1_sel
connect slots_15.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[15].wakeup_ports[1].bits.uop.imm_packed
connect slots_15.io.wakeup_ports[1].bits.uop.pimm, issue_slots[15].wakeup_ports[1].bits.uop.pimm
connect slots_15.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[15].wakeup_ports[1].bits.uop.imm_sel
connect slots_15.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[15].wakeup_ports[1].bits.uop.imm_rename
connect slots_15.io.wakeup_ports[1].bits.uop.taken, issue_slots[15].wakeup_ports[1].bits.uop.taken
connect slots_15.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[15].wakeup_ports[1].bits.uop.pc_lob
connect slots_15.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[15].wakeup_ports[1].bits.uop.edge_inst
connect slots_15.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[15].wakeup_ports[1].bits.uop.ftq_idx
connect slots_15.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[15].wakeup_ports[1].bits.uop.is_mov
connect slots_15.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[15].wakeup_ports[1].bits.uop.is_rocc
connect slots_15.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[15].wakeup_ports[1].bits.uop.is_sys_pc2epc
connect slots_15.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[15].wakeup_ports[1].bits.uop.is_eret
connect slots_15.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[15].wakeup_ports[1].bits.uop.is_amo
connect slots_15.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[15].wakeup_ports[1].bits.uop.is_sfence
connect slots_15.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[15].wakeup_ports[1].bits.uop.is_fencei
connect slots_15.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[15].wakeup_ports[1].bits.uop.is_fence
connect slots_15.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[15].wakeup_ports[1].bits.uop.is_sfb
connect slots_15.io.wakeup_ports[1].bits.uop.br_type, issue_slots[15].wakeup_ports[1].bits.uop.br_type
connect slots_15.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[15].wakeup_ports[1].bits.uop.br_tag
connect slots_15.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[15].wakeup_ports[1].bits.uop.br_mask
connect slots_15.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[15].wakeup_ports[1].bits.uop.dis_col_sel
connect slots_15.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[15].wakeup_ports[1].bits.uop.iw_p3_bypass_hint
connect slots_15.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[15].wakeup_ports[1].bits.uop.iw_p2_bypass_hint
connect slots_15.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[15].wakeup_ports[1].bits.uop.iw_p1_bypass_hint
connect slots_15.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[15].wakeup_ports[1].bits.uop.iw_p2_speculative_child
connect slots_15.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[15].wakeup_ports[1].bits.uop.iw_p1_speculative_child
connect slots_15.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[15].wakeup_ports[1].bits.uop.iw_issued_partial_dgen
connect slots_15.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[15].wakeup_ports[1].bits.uop.iw_issued_partial_agen
connect slots_15.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[15].wakeup_ports[1].bits.uop.iw_issued
connect slots_15.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[15].wakeup_ports[1].bits.uop.fu_code[0]
connect slots_15.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[15].wakeup_ports[1].bits.uop.fu_code[1]
connect slots_15.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[15].wakeup_ports[1].bits.uop.fu_code[2]
connect slots_15.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[15].wakeup_ports[1].bits.uop.fu_code[3]
connect slots_15.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[15].wakeup_ports[1].bits.uop.fu_code[4]
connect slots_15.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[15].wakeup_ports[1].bits.uop.fu_code[5]
connect slots_15.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[15].wakeup_ports[1].bits.uop.fu_code[6]
connect slots_15.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[15].wakeup_ports[1].bits.uop.fu_code[7]
connect slots_15.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[15].wakeup_ports[1].bits.uop.fu_code[8]
connect slots_15.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[15].wakeup_ports[1].bits.uop.fu_code[9]
connect slots_15.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[15].wakeup_ports[1].bits.uop.iq_type[0]
connect slots_15.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[15].wakeup_ports[1].bits.uop.iq_type[1]
connect slots_15.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[15].wakeup_ports[1].bits.uop.iq_type[2]
connect slots_15.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[15].wakeup_ports[1].bits.uop.iq_type[3]
connect slots_15.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[15].wakeup_ports[1].bits.uop.debug_pc
connect slots_15.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[15].wakeup_ports[1].bits.uop.is_rvc
connect slots_15.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[15].wakeup_ports[1].bits.uop.debug_inst
connect slots_15.io.wakeup_ports[1].bits.uop.inst, issue_slots[15].wakeup_ports[1].bits.uop.inst
connect slots_15.io.wakeup_ports[1].valid, issue_slots[15].wakeup_ports[1].valid
connect slots_15.io.wakeup_ports[2].bits.rebusy, issue_slots[15].wakeup_ports[2].bits.rebusy
connect slots_15.io.wakeup_ports[2].bits.speculative_mask, issue_slots[15].wakeup_ports[2].bits.speculative_mask
connect slots_15.io.wakeup_ports[2].bits.bypassable, issue_slots[15].wakeup_ports[2].bits.bypassable
connect slots_15.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[15].wakeup_ports[2].bits.uop.debug_tsrc
connect slots_15.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[15].wakeup_ports[2].bits.uop.debug_fsrc
connect slots_15.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[15].wakeup_ports[2].bits.uop.bp_xcpt_if
connect slots_15.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[15].wakeup_ports[2].bits.uop.bp_debug_if
connect slots_15.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[15].wakeup_ports[2].bits.uop.xcpt_ma_if
connect slots_15.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[15].wakeup_ports[2].bits.uop.xcpt_ae_if
connect slots_15.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[15].wakeup_ports[2].bits.uop.xcpt_pf_if
connect slots_15.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[15].wakeup_ports[2].bits.uop.fp_typ
connect slots_15.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[15].wakeup_ports[2].bits.uop.fp_rm
connect slots_15.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[15].wakeup_ports[2].bits.uop.fp_val
connect slots_15.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[15].wakeup_ports[2].bits.uop.fcn_op
connect slots_15.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[15].wakeup_ports[2].bits.uop.fcn_dw
connect slots_15.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[15].wakeup_ports[2].bits.uop.frs3_en
connect slots_15.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[15].wakeup_ports[2].bits.uop.lrs2_rtype
connect slots_15.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[15].wakeup_ports[2].bits.uop.lrs1_rtype
connect slots_15.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[15].wakeup_ports[2].bits.uop.dst_rtype
connect slots_15.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[15].wakeup_ports[2].bits.uop.lrs3
connect slots_15.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[15].wakeup_ports[2].bits.uop.lrs2
connect slots_15.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[15].wakeup_ports[2].bits.uop.lrs1
connect slots_15.io.wakeup_ports[2].bits.uop.ldst, issue_slots[15].wakeup_ports[2].bits.uop.ldst
connect slots_15.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[15].wakeup_ports[2].bits.uop.ldst_is_rs1
connect slots_15.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[15].wakeup_ports[2].bits.uop.csr_cmd
connect slots_15.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[15].wakeup_ports[2].bits.uop.flush_on_commit
connect slots_15.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[15].wakeup_ports[2].bits.uop.is_unique
connect slots_15.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[15].wakeup_ports[2].bits.uop.uses_stq
connect slots_15.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[15].wakeup_ports[2].bits.uop.uses_ldq
connect slots_15.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[15].wakeup_ports[2].bits.uop.mem_signed
connect slots_15.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[15].wakeup_ports[2].bits.uop.mem_size
connect slots_15.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[15].wakeup_ports[2].bits.uop.mem_cmd
connect slots_15.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[15].wakeup_ports[2].bits.uop.exc_cause
connect slots_15.io.wakeup_ports[2].bits.uop.exception, issue_slots[15].wakeup_ports[2].bits.uop.exception
connect slots_15.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[15].wakeup_ports[2].bits.uop.stale_pdst
connect slots_15.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[15].wakeup_ports[2].bits.uop.ppred_busy
connect slots_15.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[15].wakeup_ports[2].bits.uop.prs3_busy
connect slots_15.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[15].wakeup_ports[2].bits.uop.prs2_busy
connect slots_15.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[15].wakeup_ports[2].bits.uop.prs1_busy
connect slots_15.io.wakeup_ports[2].bits.uop.ppred, issue_slots[15].wakeup_ports[2].bits.uop.ppred
connect slots_15.io.wakeup_ports[2].bits.uop.prs3, issue_slots[15].wakeup_ports[2].bits.uop.prs3
connect slots_15.io.wakeup_ports[2].bits.uop.prs2, issue_slots[15].wakeup_ports[2].bits.uop.prs2
connect slots_15.io.wakeup_ports[2].bits.uop.prs1, issue_slots[15].wakeup_ports[2].bits.uop.prs1
connect slots_15.io.wakeup_ports[2].bits.uop.pdst, issue_slots[15].wakeup_ports[2].bits.uop.pdst
connect slots_15.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[15].wakeup_ports[2].bits.uop.rxq_idx
connect slots_15.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[15].wakeup_ports[2].bits.uop.stq_idx
connect slots_15.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[15].wakeup_ports[2].bits.uop.ldq_idx
connect slots_15.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[15].wakeup_ports[2].bits.uop.rob_idx
connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.vec
connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.wflags
connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.sqrt
connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.div
connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.fma
connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe
connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.toint
connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.fromint
connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut
connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn
connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.swap23
connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.swap12
connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.ren3
connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.ren2
connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.ren1
connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.wen
connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.ldst
connect slots_15.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[15].wakeup_ports[2].bits.uop.op2_sel
connect slots_15.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[15].wakeup_ports[2].bits.uop.op1_sel
connect slots_15.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[15].wakeup_ports[2].bits.uop.imm_packed
connect slots_15.io.wakeup_ports[2].bits.uop.pimm, issue_slots[15].wakeup_ports[2].bits.uop.pimm
connect slots_15.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[15].wakeup_ports[2].bits.uop.imm_sel
connect slots_15.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[15].wakeup_ports[2].bits.uop.imm_rename
connect slots_15.io.wakeup_ports[2].bits.uop.taken, issue_slots[15].wakeup_ports[2].bits.uop.taken
connect slots_15.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[15].wakeup_ports[2].bits.uop.pc_lob
connect slots_15.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[15].wakeup_ports[2].bits.uop.edge_inst
connect slots_15.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[15].wakeup_ports[2].bits.uop.ftq_idx
connect slots_15.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[15].wakeup_ports[2].bits.uop.is_mov
connect slots_15.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[15].wakeup_ports[2].bits.uop.is_rocc
connect slots_15.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[15].wakeup_ports[2].bits.uop.is_sys_pc2epc
connect slots_15.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[15].wakeup_ports[2].bits.uop.is_eret
connect slots_15.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[15].wakeup_ports[2].bits.uop.is_amo
connect slots_15.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[15].wakeup_ports[2].bits.uop.is_sfence
connect slots_15.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[15].wakeup_ports[2].bits.uop.is_fencei
connect slots_15.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[15].wakeup_ports[2].bits.uop.is_fence
connect slots_15.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[15].wakeup_ports[2].bits.uop.is_sfb
connect slots_15.io.wakeup_ports[2].bits.uop.br_type, issue_slots[15].wakeup_ports[2].bits.uop.br_type
connect slots_15.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[15].wakeup_ports[2].bits.uop.br_tag
connect slots_15.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[15].wakeup_ports[2].bits.uop.br_mask
connect slots_15.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[15].wakeup_ports[2].bits.uop.dis_col_sel
connect slots_15.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[15].wakeup_ports[2].bits.uop.iw_p3_bypass_hint
connect slots_15.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[15].wakeup_ports[2].bits.uop.iw_p2_bypass_hint
connect slots_15.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[15].wakeup_ports[2].bits.uop.iw_p1_bypass_hint
connect slots_15.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[15].wakeup_ports[2].bits.uop.iw_p2_speculative_child
connect slots_15.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[15].wakeup_ports[2].bits.uop.iw_p1_speculative_child
connect slots_15.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[15].wakeup_ports[2].bits.uop.iw_issued_partial_dgen
connect slots_15.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[15].wakeup_ports[2].bits.uop.iw_issued_partial_agen
connect slots_15.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[15].wakeup_ports[2].bits.uop.iw_issued
connect slots_15.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[15].wakeup_ports[2].bits.uop.fu_code[0]
connect slots_15.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[15].wakeup_ports[2].bits.uop.fu_code[1]
connect slots_15.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[15].wakeup_ports[2].bits.uop.fu_code[2]
connect slots_15.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[15].wakeup_ports[2].bits.uop.fu_code[3]
connect slots_15.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[15].wakeup_ports[2].bits.uop.fu_code[4]
connect slots_15.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[15].wakeup_ports[2].bits.uop.fu_code[5]
connect slots_15.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[15].wakeup_ports[2].bits.uop.fu_code[6]
connect slots_15.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[15].wakeup_ports[2].bits.uop.fu_code[7]
connect slots_15.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[15].wakeup_ports[2].bits.uop.fu_code[8]
connect slots_15.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[15].wakeup_ports[2].bits.uop.fu_code[9]
connect slots_15.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[15].wakeup_ports[2].bits.uop.iq_type[0]
connect slots_15.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[15].wakeup_ports[2].bits.uop.iq_type[1]
connect slots_15.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[15].wakeup_ports[2].bits.uop.iq_type[2]
connect slots_15.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[15].wakeup_ports[2].bits.uop.iq_type[3]
connect slots_15.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[15].wakeup_ports[2].bits.uop.debug_pc
connect slots_15.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[15].wakeup_ports[2].bits.uop.is_rvc
connect slots_15.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[15].wakeup_ports[2].bits.uop.debug_inst
connect slots_15.io.wakeup_ports[2].bits.uop.inst, issue_slots[15].wakeup_ports[2].bits.uop.inst
connect slots_15.io.wakeup_ports[2].valid, issue_slots[15].wakeup_ports[2].valid
connect slots_15.io.wakeup_ports[3].bits.rebusy, issue_slots[15].wakeup_ports[3].bits.rebusy
connect slots_15.io.wakeup_ports[3].bits.speculative_mask, issue_slots[15].wakeup_ports[3].bits.speculative_mask
connect slots_15.io.wakeup_ports[3].bits.bypassable, issue_slots[15].wakeup_ports[3].bits.bypassable
connect slots_15.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[15].wakeup_ports[3].bits.uop.debug_tsrc
connect slots_15.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[15].wakeup_ports[3].bits.uop.debug_fsrc
connect slots_15.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[15].wakeup_ports[3].bits.uop.bp_xcpt_if
connect slots_15.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[15].wakeup_ports[3].bits.uop.bp_debug_if
connect slots_15.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[15].wakeup_ports[3].bits.uop.xcpt_ma_if
connect slots_15.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[15].wakeup_ports[3].bits.uop.xcpt_ae_if
connect slots_15.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[15].wakeup_ports[3].bits.uop.xcpt_pf_if
connect slots_15.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[15].wakeup_ports[3].bits.uop.fp_typ
connect slots_15.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[15].wakeup_ports[3].bits.uop.fp_rm
connect slots_15.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[15].wakeup_ports[3].bits.uop.fp_val
connect slots_15.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[15].wakeup_ports[3].bits.uop.fcn_op
connect slots_15.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[15].wakeup_ports[3].bits.uop.fcn_dw
connect slots_15.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[15].wakeup_ports[3].bits.uop.frs3_en
connect slots_15.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[15].wakeup_ports[3].bits.uop.lrs2_rtype
connect slots_15.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[15].wakeup_ports[3].bits.uop.lrs1_rtype
connect slots_15.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[15].wakeup_ports[3].bits.uop.dst_rtype
connect slots_15.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[15].wakeup_ports[3].bits.uop.lrs3
connect slots_15.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[15].wakeup_ports[3].bits.uop.lrs2
connect slots_15.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[15].wakeup_ports[3].bits.uop.lrs1
connect slots_15.io.wakeup_ports[3].bits.uop.ldst, issue_slots[15].wakeup_ports[3].bits.uop.ldst
connect slots_15.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[15].wakeup_ports[3].bits.uop.ldst_is_rs1
connect slots_15.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[15].wakeup_ports[3].bits.uop.csr_cmd
connect slots_15.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[15].wakeup_ports[3].bits.uop.flush_on_commit
connect slots_15.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[15].wakeup_ports[3].bits.uop.is_unique
connect slots_15.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[15].wakeup_ports[3].bits.uop.uses_stq
connect slots_15.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[15].wakeup_ports[3].bits.uop.uses_ldq
connect slots_15.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[15].wakeup_ports[3].bits.uop.mem_signed
connect slots_15.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[15].wakeup_ports[3].bits.uop.mem_size
connect slots_15.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[15].wakeup_ports[3].bits.uop.mem_cmd
connect slots_15.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[15].wakeup_ports[3].bits.uop.exc_cause
connect slots_15.io.wakeup_ports[3].bits.uop.exception, issue_slots[15].wakeup_ports[3].bits.uop.exception
connect slots_15.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[15].wakeup_ports[3].bits.uop.stale_pdst
connect slots_15.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[15].wakeup_ports[3].bits.uop.ppred_busy
connect slots_15.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[15].wakeup_ports[3].bits.uop.prs3_busy
connect slots_15.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[15].wakeup_ports[3].bits.uop.prs2_busy
connect slots_15.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[15].wakeup_ports[3].bits.uop.prs1_busy
connect slots_15.io.wakeup_ports[3].bits.uop.ppred, issue_slots[15].wakeup_ports[3].bits.uop.ppred
connect slots_15.io.wakeup_ports[3].bits.uop.prs3, issue_slots[15].wakeup_ports[3].bits.uop.prs3
connect slots_15.io.wakeup_ports[3].bits.uop.prs2, issue_slots[15].wakeup_ports[3].bits.uop.prs2
connect slots_15.io.wakeup_ports[3].bits.uop.prs1, issue_slots[15].wakeup_ports[3].bits.uop.prs1
connect slots_15.io.wakeup_ports[3].bits.uop.pdst, issue_slots[15].wakeup_ports[3].bits.uop.pdst
connect slots_15.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[15].wakeup_ports[3].bits.uop.rxq_idx
connect slots_15.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[15].wakeup_ports[3].bits.uop.stq_idx
connect slots_15.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[15].wakeup_ports[3].bits.uop.ldq_idx
connect slots_15.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[15].wakeup_ports[3].bits.uop.rob_idx
connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.vec
connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.wflags
connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.sqrt
connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.div
connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.fma
connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe
connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.toint
connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.fromint
connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut
connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn
connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.swap23
connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.swap12
connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.ren3
connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.ren2
connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.ren1
connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.wen
connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.ldst
connect slots_15.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[15].wakeup_ports[3].bits.uop.op2_sel
connect slots_15.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[15].wakeup_ports[3].bits.uop.op1_sel
connect slots_15.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[15].wakeup_ports[3].bits.uop.imm_packed
connect slots_15.io.wakeup_ports[3].bits.uop.pimm, issue_slots[15].wakeup_ports[3].bits.uop.pimm
connect slots_15.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[15].wakeup_ports[3].bits.uop.imm_sel
connect slots_15.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[15].wakeup_ports[3].bits.uop.imm_rename
connect slots_15.io.wakeup_ports[3].bits.uop.taken, issue_slots[15].wakeup_ports[3].bits.uop.taken
connect slots_15.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[15].wakeup_ports[3].bits.uop.pc_lob
connect slots_15.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[15].wakeup_ports[3].bits.uop.edge_inst
connect slots_15.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[15].wakeup_ports[3].bits.uop.ftq_idx
connect slots_15.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[15].wakeup_ports[3].bits.uop.is_mov
connect slots_15.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[15].wakeup_ports[3].bits.uop.is_rocc
connect slots_15.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[15].wakeup_ports[3].bits.uop.is_sys_pc2epc
connect slots_15.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[15].wakeup_ports[3].bits.uop.is_eret
connect slots_15.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[15].wakeup_ports[3].bits.uop.is_amo
connect slots_15.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[15].wakeup_ports[3].bits.uop.is_sfence
connect slots_15.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[15].wakeup_ports[3].bits.uop.is_fencei
connect slots_15.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[15].wakeup_ports[3].bits.uop.is_fence
connect slots_15.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[15].wakeup_ports[3].bits.uop.is_sfb
connect slots_15.io.wakeup_ports[3].bits.uop.br_type, issue_slots[15].wakeup_ports[3].bits.uop.br_type
connect slots_15.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[15].wakeup_ports[3].bits.uop.br_tag
connect slots_15.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[15].wakeup_ports[3].bits.uop.br_mask
connect slots_15.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[15].wakeup_ports[3].bits.uop.dis_col_sel
connect slots_15.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[15].wakeup_ports[3].bits.uop.iw_p3_bypass_hint
connect slots_15.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[15].wakeup_ports[3].bits.uop.iw_p2_bypass_hint
connect slots_15.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[15].wakeup_ports[3].bits.uop.iw_p1_bypass_hint
connect slots_15.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[15].wakeup_ports[3].bits.uop.iw_p2_speculative_child
connect slots_15.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[15].wakeup_ports[3].bits.uop.iw_p1_speculative_child
connect slots_15.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[15].wakeup_ports[3].bits.uop.iw_issued_partial_dgen
connect slots_15.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[15].wakeup_ports[3].bits.uop.iw_issued_partial_agen
connect slots_15.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[15].wakeup_ports[3].bits.uop.iw_issued
connect slots_15.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[15].wakeup_ports[3].bits.uop.fu_code[0]
connect slots_15.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[15].wakeup_ports[3].bits.uop.fu_code[1]
connect slots_15.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[15].wakeup_ports[3].bits.uop.fu_code[2]
connect slots_15.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[15].wakeup_ports[3].bits.uop.fu_code[3]
connect slots_15.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[15].wakeup_ports[3].bits.uop.fu_code[4]
connect slots_15.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[15].wakeup_ports[3].bits.uop.fu_code[5]
connect slots_15.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[15].wakeup_ports[3].bits.uop.fu_code[6]
connect slots_15.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[15].wakeup_ports[3].bits.uop.fu_code[7]
connect slots_15.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[15].wakeup_ports[3].bits.uop.fu_code[8]
connect slots_15.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[15].wakeup_ports[3].bits.uop.fu_code[9]
connect slots_15.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[15].wakeup_ports[3].bits.uop.iq_type[0]
connect slots_15.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[15].wakeup_ports[3].bits.uop.iq_type[1]
connect slots_15.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[15].wakeup_ports[3].bits.uop.iq_type[2]
connect slots_15.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[15].wakeup_ports[3].bits.uop.iq_type[3]
connect slots_15.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[15].wakeup_ports[3].bits.uop.debug_pc
connect slots_15.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[15].wakeup_ports[3].bits.uop.is_rvc
connect slots_15.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[15].wakeup_ports[3].bits.uop.debug_inst
connect slots_15.io.wakeup_ports[3].bits.uop.inst, issue_slots[15].wakeup_ports[3].bits.uop.inst
connect slots_15.io.wakeup_ports[3].valid, issue_slots[15].wakeup_ports[3].valid
connect slots_15.io.squash_grant, issue_slots[15].squash_grant
connect slots_15.io.clear, issue_slots[15].clear
connect slots_15.io.kill, issue_slots[15].kill
connect slots_15.io.brupdate.b2.target_offset, issue_slots[15].brupdate.b2.target_offset
connect slots_15.io.brupdate.b2.jalr_target, issue_slots[15].brupdate.b2.jalr_target
connect slots_15.io.brupdate.b2.pc_sel, issue_slots[15].brupdate.b2.pc_sel
connect slots_15.io.brupdate.b2.cfi_type, issue_slots[15].brupdate.b2.cfi_type
connect slots_15.io.brupdate.b2.taken, issue_slots[15].brupdate.b2.taken
connect slots_15.io.brupdate.b2.mispredict, issue_slots[15].brupdate.b2.mispredict
connect slots_15.io.brupdate.b2.uop.debug_tsrc, issue_slots[15].brupdate.b2.uop.debug_tsrc
connect slots_15.io.brupdate.b2.uop.debug_fsrc, issue_slots[15].brupdate.b2.uop.debug_fsrc
connect slots_15.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[15].brupdate.b2.uop.bp_xcpt_if
connect slots_15.io.brupdate.b2.uop.bp_debug_if, issue_slots[15].brupdate.b2.uop.bp_debug_if
connect slots_15.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[15].brupdate.b2.uop.xcpt_ma_if
connect slots_15.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[15].brupdate.b2.uop.xcpt_ae_if
connect slots_15.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[15].brupdate.b2.uop.xcpt_pf_if
connect slots_15.io.brupdate.b2.uop.fp_typ, issue_slots[15].brupdate.b2.uop.fp_typ
connect slots_15.io.brupdate.b2.uop.fp_rm, issue_slots[15].brupdate.b2.uop.fp_rm
connect slots_15.io.brupdate.b2.uop.fp_val, issue_slots[15].brupdate.b2.uop.fp_val
connect slots_15.io.brupdate.b2.uop.fcn_op, issue_slots[15].brupdate.b2.uop.fcn_op
connect slots_15.io.brupdate.b2.uop.fcn_dw, issue_slots[15].brupdate.b2.uop.fcn_dw
connect slots_15.io.brupdate.b2.uop.frs3_en, issue_slots[15].brupdate.b2.uop.frs3_en
connect slots_15.io.brupdate.b2.uop.lrs2_rtype, issue_slots[15].brupdate.b2.uop.lrs2_rtype
connect slots_15.io.brupdate.b2.uop.lrs1_rtype, issue_slots[15].brupdate.b2.uop.lrs1_rtype
connect slots_15.io.brupdate.b2.uop.dst_rtype, issue_slots[15].brupdate.b2.uop.dst_rtype
connect slots_15.io.brupdate.b2.uop.lrs3, issue_slots[15].brupdate.b2.uop.lrs3
connect slots_15.io.brupdate.b2.uop.lrs2, issue_slots[15].brupdate.b2.uop.lrs2
connect slots_15.io.brupdate.b2.uop.lrs1, issue_slots[15].brupdate.b2.uop.lrs1
connect slots_15.io.brupdate.b2.uop.ldst, issue_slots[15].brupdate.b2.uop.ldst
connect slots_15.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[15].brupdate.b2.uop.ldst_is_rs1
connect slots_15.io.brupdate.b2.uop.csr_cmd, issue_slots[15].brupdate.b2.uop.csr_cmd
connect slots_15.io.brupdate.b2.uop.flush_on_commit, issue_slots[15].brupdate.b2.uop.flush_on_commit
connect slots_15.io.brupdate.b2.uop.is_unique, issue_slots[15].brupdate.b2.uop.is_unique
connect slots_15.io.brupdate.b2.uop.uses_stq, issue_slots[15].brupdate.b2.uop.uses_stq
connect slots_15.io.brupdate.b2.uop.uses_ldq, issue_slots[15].brupdate.b2.uop.uses_ldq
connect slots_15.io.brupdate.b2.uop.mem_signed, issue_slots[15].brupdate.b2.uop.mem_signed
connect slots_15.io.brupdate.b2.uop.mem_size, issue_slots[15].brupdate.b2.uop.mem_size
connect slots_15.io.brupdate.b2.uop.mem_cmd, issue_slots[15].brupdate.b2.uop.mem_cmd
connect slots_15.io.brupdate.b2.uop.exc_cause, issue_slots[15].brupdate.b2.uop.exc_cause
connect slots_15.io.brupdate.b2.uop.exception, issue_slots[15].brupdate.b2.uop.exception
connect slots_15.io.brupdate.b2.uop.stale_pdst, issue_slots[15].brupdate.b2.uop.stale_pdst
connect slots_15.io.brupdate.b2.uop.ppred_busy, issue_slots[15].brupdate.b2.uop.ppred_busy
connect slots_15.io.brupdate.b2.uop.prs3_busy, issue_slots[15].brupdate.b2.uop.prs3_busy
connect slots_15.io.brupdate.b2.uop.prs2_busy, issue_slots[15].brupdate.b2.uop.prs2_busy
connect slots_15.io.brupdate.b2.uop.prs1_busy, issue_slots[15].brupdate.b2.uop.prs1_busy
connect slots_15.io.brupdate.b2.uop.ppred, issue_slots[15].brupdate.b2.uop.ppred
connect slots_15.io.brupdate.b2.uop.prs3, issue_slots[15].brupdate.b2.uop.prs3
connect slots_15.io.brupdate.b2.uop.prs2, issue_slots[15].brupdate.b2.uop.prs2
connect slots_15.io.brupdate.b2.uop.prs1, issue_slots[15].brupdate.b2.uop.prs1
connect slots_15.io.brupdate.b2.uop.pdst, issue_slots[15].brupdate.b2.uop.pdst
connect slots_15.io.brupdate.b2.uop.rxq_idx, issue_slots[15].brupdate.b2.uop.rxq_idx
connect slots_15.io.brupdate.b2.uop.stq_idx, issue_slots[15].brupdate.b2.uop.stq_idx
connect slots_15.io.brupdate.b2.uop.ldq_idx, issue_slots[15].brupdate.b2.uop.ldq_idx
connect slots_15.io.brupdate.b2.uop.rob_idx, issue_slots[15].brupdate.b2.uop.rob_idx
connect slots_15.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[15].brupdate.b2.uop.fp_ctrl.vec
connect slots_15.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[15].brupdate.b2.uop.fp_ctrl.wflags
connect slots_15.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[15].brupdate.b2.uop.fp_ctrl.sqrt
connect slots_15.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[15].brupdate.b2.uop.fp_ctrl.div
connect slots_15.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[15].brupdate.b2.uop.fp_ctrl.fma
connect slots_15.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[15].brupdate.b2.uop.fp_ctrl.fastpipe
connect slots_15.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[15].brupdate.b2.uop.fp_ctrl.toint
connect slots_15.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[15].brupdate.b2.uop.fp_ctrl.fromint
connect slots_15.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[15].brupdate.b2.uop.fp_ctrl.typeTagOut
connect slots_15.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[15].brupdate.b2.uop.fp_ctrl.typeTagIn
connect slots_15.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[15].brupdate.b2.uop.fp_ctrl.swap23
connect slots_15.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[15].brupdate.b2.uop.fp_ctrl.swap12
connect slots_15.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[15].brupdate.b2.uop.fp_ctrl.ren3
connect slots_15.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[15].brupdate.b2.uop.fp_ctrl.ren2
connect slots_15.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[15].brupdate.b2.uop.fp_ctrl.ren1
connect slots_15.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[15].brupdate.b2.uop.fp_ctrl.wen
connect slots_15.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[15].brupdate.b2.uop.fp_ctrl.ldst
connect slots_15.io.brupdate.b2.uop.op2_sel, issue_slots[15].brupdate.b2.uop.op2_sel
connect slots_15.io.brupdate.b2.uop.op1_sel, issue_slots[15].brupdate.b2.uop.op1_sel
connect slots_15.io.brupdate.b2.uop.imm_packed, issue_slots[15].brupdate.b2.uop.imm_packed
connect slots_15.io.brupdate.b2.uop.pimm, issue_slots[15].brupdate.b2.uop.pimm
connect slots_15.io.brupdate.b2.uop.imm_sel, issue_slots[15].brupdate.b2.uop.imm_sel
connect slots_15.io.brupdate.b2.uop.imm_rename, issue_slots[15].brupdate.b2.uop.imm_rename
connect slots_15.io.brupdate.b2.uop.taken, issue_slots[15].brupdate.b2.uop.taken
connect slots_15.io.brupdate.b2.uop.pc_lob, issue_slots[15].brupdate.b2.uop.pc_lob
connect slots_15.io.brupdate.b2.uop.edge_inst, issue_slots[15].brupdate.b2.uop.edge_inst
connect slots_15.io.brupdate.b2.uop.ftq_idx, issue_slots[15].brupdate.b2.uop.ftq_idx
connect slots_15.io.brupdate.b2.uop.is_mov, issue_slots[15].brupdate.b2.uop.is_mov
connect slots_15.io.brupdate.b2.uop.is_rocc, issue_slots[15].brupdate.b2.uop.is_rocc
connect slots_15.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[15].brupdate.b2.uop.is_sys_pc2epc
connect slots_15.io.brupdate.b2.uop.is_eret, issue_slots[15].brupdate.b2.uop.is_eret
connect slots_15.io.brupdate.b2.uop.is_amo, issue_slots[15].brupdate.b2.uop.is_amo
connect slots_15.io.brupdate.b2.uop.is_sfence, issue_slots[15].brupdate.b2.uop.is_sfence
connect slots_15.io.brupdate.b2.uop.is_fencei, issue_slots[15].brupdate.b2.uop.is_fencei
connect slots_15.io.brupdate.b2.uop.is_fence, issue_slots[15].brupdate.b2.uop.is_fence
connect slots_15.io.brupdate.b2.uop.is_sfb, issue_slots[15].brupdate.b2.uop.is_sfb
connect slots_15.io.brupdate.b2.uop.br_type, issue_slots[15].brupdate.b2.uop.br_type
connect slots_15.io.brupdate.b2.uop.br_tag, issue_slots[15].brupdate.b2.uop.br_tag
connect slots_15.io.brupdate.b2.uop.br_mask, issue_slots[15].brupdate.b2.uop.br_mask
connect slots_15.io.brupdate.b2.uop.dis_col_sel, issue_slots[15].brupdate.b2.uop.dis_col_sel
connect slots_15.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[15].brupdate.b2.uop.iw_p3_bypass_hint
connect slots_15.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[15].brupdate.b2.uop.iw_p2_bypass_hint
connect slots_15.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[15].brupdate.b2.uop.iw_p1_bypass_hint
connect slots_15.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[15].brupdate.b2.uop.iw_p2_speculative_child
connect slots_15.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[15].brupdate.b2.uop.iw_p1_speculative_child
connect slots_15.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[15].brupdate.b2.uop.iw_issued_partial_dgen
connect slots_15.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[15].brupdate.b2.uop.iw_issued_partial_agen
connect slots_15.io.brupdate.b2.uop.iw_issued, issue_slots[15].brupdate.b2.uop.iw_issued
connect slots_15.io.brupdate.b2.uop.fu_code[0], issue_slots[15].brupdate.b2.uop.fu_code[0]
connect slots_15.io.brupdate.b2.uop.fu_code[1], issue_slots[15].brupdate.b2.uop.fu_code[1]
connect slots_15.io.brupdate.b2.uop.fu_code[2], issue_slots[15].brupdate.b2.uop.fu_code[2]
connect slots_15.io.brupdate.b2.uop.fu_code[3], issue_slots[15].brupdate.b2.uop.fu_code[3]
connect slots_15.io.brupdate.b2.uop.fu_code[4], issue_slots[15].brupdate.b2.uop.fu_code[4]
connect slots_15.io.brupdate.b2.uop.fu_code[5], issue_slots[15].brupdate.b2.uop.fu_code[5]
connect slots_15.io.brupdate.b2.uop.fu_code[6], issue_slots[15].brupdate.b2.uop.fu_code[6]
connect slots_15.io.brupdate.b2.uop.fu_code[7], issue_slots[15].brupdate.b2.uop.fu_code[7]
connect slots_15.io.brupdate.b2.uop.fu_code[8], issue_slots[15].brupdate.b2.uop.fu_code[8]
connect slots_15.io.brupdate.b2.uop.fu_code[9], issue_slots[15].brupdate.b2.uop.fu_code[9]
connect slots_15.io.brupdate.b2.uop.iq_type[0], issue_slots[15].brupdate.b2.uop.iq_type[0]
connect slots_15.io.brupdate.b2.uop.iq_type[1], issue_slots[15].brupdate.b2.uop.iq_type[1]
connect slots_15.io.brupdate.b2.uop.iq_type[2], issue_slots[15].brupdate.b2.uop.iq_type[2]
connect slots_15.io.brupdate.b2.uop.iq_type[3], issue_slots[15].brupdate.b2.uop.iq_type[3]
connect slots_15.io.brupdate.b2.uop.debug_pc, issue_slots[15].brupdate.b2.uop.debug_pc
connect slots_15.io.brupdate.b2.uop.is_rvc, issue_slots[15].brupdate.b2.uop.is_rvc
connect slots_15.io.brupdate.b2.uop.debug_inst, issue_slots[15].brupdate.b2.uop.debug_inst
connect slots_15.io.brupdate.b2.uop.inst, issue_slots[15].brupdate.b2.uop.inst
connect slots_15.io.brupdate.b1.mispredict_mask, issue_slots[15].brupdate.b1.mispredict_mask
connect slots_15.io.brupdate.b1.resolve_mask, issue_slots[15].brupdate.b1.resolve_mask
connect issue_slots[15].out_uop.debug_tsrc, slots_15.io.out_uop.debug_tsrc
connect issue_slots[15].out_uop.debug_fsrc, slots_15.io.out_uop.debug_fsrc
connect issue_slots[15].out_uop.bp_xcpt_if, slots_15.io.out_uop.bp_xcpt_if
connect issue_slots[15].out_uop.bp_debug_if, slots_15.io.out_uop.bp_debug_if
connect issue_slots[15].out_uop.xcpt_ma_if, slots_15.io.out_uop.xcpt_ma_if
connect issue_slots[15].out_uop.xcpt_ae_if, slots_15.io.out_uop.xcpt_ae_if
connect issue_slots[15].out_uop.xcpt_pf_if, slots_15.io.out_uop.xcpt_pf_if
connect issue_slots[15].out_uop.fp_typ, slots_15.io.out_uop.fp_typ
connect issue_slots[15].out_uop.fp_rm, slots_15.io.out_uop.fp_rm
connect issue_slots[15].out_uop.fp_val, slots_15.io.out_uop.fp_val
connect issue_slots[15].out_uop.fcn_op, slots_15.io.out_uop.fcn_op
connect issue_slots[15].out_uop.fcn_dw, slots_15.io.out_uop.fcn_dw
connect issue_slots[15].out_uop.frs3_en, slots_15.io.out_uop.frs3_en
connect issue_slots[15].out_uop.lrs2_rtype, slots_15.io.out_uop.lrs2_rtype
connect issue_slots[15].out_uop.lrs1_rtype, slots_15.io.out_uop.lrs1_rtype
connect issue_slots[15].out_uop.dst_rtype, slots_15.io.out_uop.dst_rtype
connect issue_slots[15].out_uop.lrs3, slots_15.io.out_uop.lrs3
connect issue_slots[15].out_uop.lrs2, slots_15.io.out_uop.lrs2
connect issue_slots[15].out_uop.lrs1, slots_15.io.out_uop.lrs1
connect issue_slots[15].out_uop.ldst, slots_15.io.out_uop.ldst
connect issue_slots[15].out_uop.ldst_is_rs1, slots_15.io.out_uop.ldst_is_rs1
connect issue_slots[15].out_uop.csr_cmd, slots_15.io.out_uop.csr_cmd
connect issue_slots[15].out_uop.flush_on_commit, slots_15.io.out_uop.flush_on_commit
connect issue_slots[15].out_uop.is_unique, slots_15.io.out_uop.is_unique
connect issue_slots[15].out_uop.uses_stq, slots_15.io.out_uop.uses_stq
connect issue_slots[15].out_uop.uses_ldq, slots_15.io.out_uop.uses_ldq
connect issue_slots[15].out_uop.mem_signed, slots_15.io.out_uop.mem_signed
connect issue_slots[15].out_uop.mem_size, slots_15.io.out_uop.mem_size
connect issue_slots[15].out_uop.mem_cmd, slots_15.io.out_uop.mem_cmd
connect issue_slots[15].out_uop.exc_cause, slots_15.io.out_uop.exc_cause
connect issue_slots[15].out_uop.exception, slots_15.io.out_uop.exception
connect issue_slots[15].out_uop.stale_pdst, slots_15.io.out_uop.stale_pdst
connect issue_slots[15].out_uop.ppred_busy, slots_15.io.out_uop.ppred_busy
connect issue_slots[15].out_uop.prs3_busy, slots_15.io.out_uop.prs3_busy
connect issue_slots[15].out_uop.prs2_busy, slots_15.io.out_uop.prs2_busy
connect issue_slots[15].out_uop.prs1_busy, slots_15.io.out_uop.prs1_busy
connect issue_slots[15].out_uop.ppred, slots_15.io.out_uop.ppred
connect issue_slots[15].out_uop.prs3, slots_15.io.out_uop.prs3
connect issue_slots[15].out_uop.prs2, slots_15.io.out_uop.prs2
connect issue_slots[15].out_uop.prs1, slots_15.io.out_uop.prs1
connect issue_slots[15].out_uop.pdst, slots_15.io.out_uop.pdst
connect issue_slots[15].out_uop.rxq_idx, slots_15.io.out_uop.rxq_idx
connect issue_slots[15].out_uop.stq_idx, slots_15.io.out_uop.stq_idx
connect issue_slots[15].out_uop.ldq_idx, slots_15.io.out_uop.ldq_idx
connect issue_slots[15].out_uop.rob_idx, slots_15.io.out_uop.rob_idx
connect issue_slots[15].out_uop.fp_ctrl.vec, slots_15.io.out_uop.fp_ctrl.vec
connect issue_slots[15].out_uop.fp_ctrl.wflags, slots_15.io.out_uop.fp_ctrl.wflags
connect issue_slots[15].out_uop.fp_ctrl.sqrt, slots_15.io.out_uop.fp_ctrl.sqrt
connect issue_slots[15].out_uop.fp_ctrl.div, slots_15.io.out_uop.fp_ctrl.div
connect issue_slots[15].out_uop.fp_ctrl.fma, slots_15.io.out_uop.fp_ctrl.fma
connect issue_slots[15].out_uop.fp_ctrl.fastpipe, slots_15.io.out_uop.fp_ctrl.fastpipe
connect issue_slots[15].out_uop.fp_ctrl.toint, slots_15.io.out_uop.fp_ctrl.toint
connect issue_slots[15].out_uop.fp_ctrl.fromint, slots_15.io.out_uop.fp_ctrl.fromint
connect issue_slots[15].out_uop.fp_ctrl.typeTagOut, slots_15.io.out_uop.fp_ctrl.typeTagOut
connect issue_slots[15].out_uop.fp_ctrl.typeTagIn, slots_15.io.out_uop.fp_ctrl.typeTagIn
connect issue_slots[15].out_uop.fp_ctrl.swap23, slots_15.io.out_uop.fp_ctrl.swap23
connect issue_slots[15].out_uop.fp_ctrl.swap12, slots_15.io.out_uop.fp_ctrl.swap12
connect issue_slots[15].out_uop.fp_ctrl.ren3, slots_15.io.out_uop.fp_ctrl.ren3
connect issue_slots[15].out_uop.fp_ctrl.ren2, slots_15.io.out_uop.fp_ctrl.ren2
connect issue_slots[15].out_uop.fp_ctrl.ren1, slots_15.io.out_uop.fp_ctrl.ren1
connect issue_slots[15].out_uop.fp_ctrl.wen, slots_15.io.out_uop.fp_ctrl.wen
connect issue_slots[15].out_uop.fp_ctrl.ldst, slots_15.io.out_uop.fp_ctrl.ldst
connect issue_slots[15].out_uop.op2_sel, slots_15.io.out_uop.op2_sel
connect issue_slots[15].out_uop.op1_sel, slots_15.io.out_uop.op1_sel
connect issue_slots[15].out_uop.imm_packed, slots_15.io.out_uop.imm_packed
connect issue_slots[15].out_uop.pimm, slots_15.io.out_uop.pimm
connect issue_slots[15].out_uop.imm_sel, slots_15.io.out_uop.imm_sel
connect issue_slots[15].out_uop.imm_rename, slots_15.io.out_uop.imm_rename
connect issue_slots[15].out_uop.taken, slots_15.io.out_uop.taken
connect issue_slots[15].out_uop.pc_lob, slots_15.io.out_uop.pc_lob
connect issue_slots[15].out_uop.edge_inst, slots_15.io.out_uop.edge_inst
connect issue_slots[15].out_uop.ftq_idx, slots_15.io.out_uop.ftq_idx
connect issue_slots[15].out_uop.is_mov, slots_15.io.out_uop.is_mov
connect issue_slots[15].out_uop.is_rocc, slots_15.io.out_uop.is_rocc
connect issue_slots[15].out_uop.is_sys_pc2epc, slots_15.io.out_uop.is_sys_pc2epc
connect issue_slots[15].out_uop.is_eret, slots_15.io.out_uop.is_eret
connect issue_slots[15].out_uop.is_amo, slots_15.io.out_uop.is_amo
connect issue_slots[15].out_uop.is_sfence, slots_15.io.out_uop.is_sfence
connect issue_slots[15].out_uop.is_fencei, slots_15.io.out_uop.is_fencei
connect issue_slots[15].out_uop.is_fence, slots_15.io.out_uop.is_fence
connect issue_slots[15].out_uop.is_sfb, slots_15.io.out_uop.is_sfb
connect issue_slots[15].out_uop.br_type, slots_15.io.out_uop.br_type
connect issue_slots[15].out_uop.br_tag, slots_15.io.out_uop.br_tag
connect issue_slots[15].out_uop.br_mask, slots_15.io.out_uop.br_mask
connect issue_slots[15].out_uop.dis_col_sel, slots_15.io.out_uop.dis_col_sel
connect issue_slots[15].out_uop.iw_p3_bypass_hint, slots_15.io.out_uop.iw_p3_bypass_hint
connect issue_slots[15].out_uop.iw_p2_bypass_hint, slots_15.io.out_uop.iw_p2_bypass_hint
connect issue_slots[15].out_uop.iw_p1_bypass_hint, slots_15.io.out_uop.iw_p1_bypass_hint
connect issue_slots[15].out_uop.iw_p2_speculative_child, slots_15.io.out_uop.iw_p2_speculative_child
connect issue_slots[15].out_uop.iw_p1_speculative_child, slots_15.io.out_uop.iw_p1_speculative_child
connect issue_slots[15].out_uop.iw_issued_partial_dgen, slots_15.io.out_uop.iw_issued_partial_dgen
connect issue_slots[15].out_uop.iw_issued_partial_agen, slots_15.io.out_uop.iw_issued_partial_agen
connect issue_slots[15].out_uop.iw_issued, slots_15.io.out_uop.iw_issued
connect issue_slots[15].out_uop.fu_code[0], slots_15.io.out_uop.fu_code[0]
connect issue_slots[15].out_uop.fu_code[1], slots_15.io.out_uop.fu_code[1]
connect issue_slots[15].out_uop.fu_code[2], slots_15.io.out_uop.fu_code[2]
connect issue_slots[15].out_uop.fu_code[3], slots_15.io.out_uop.fu_code[3]
connect issue_slots[15].out_uop.fu_code[4], slots_15.io.out_uop.fu_code[4]
connect issue_slots[15].out_uop.fu_code[5], slots_15.io.out_uop.fu_code[5]
connect issue_slots[15].out_uop.fu_code[6], slots_15.io.out_uop.fu_code[6]
connect issue_slots[15].out_uop.fu_code[7], slots_15.io.out_uop.fu_code[7]
connect issue_slots[15].out_uop.fu_code[8], slots_15.io.out_uop.fu_code[8]
connect issue_slots[15].out_uop.fu_code[9], slots_15.io.out_uop.fu_code[9]
connect issue_slots[15].out_uop.iq_type[0], slots_15.io.out_uop.iq_type[0]
connect issue_slots[15].out_uop.iq_type[1], slots_15.io.out_uop.iq_type[1]
connect issue_slots[15].out_uop.iq_type[2], slots_15.io.out_uop.iq_type[2]
connect issue_slots[15].out_uop.iq_type[3], slots_15.io.out_uop.iq_type[3]
connect issue_slots[15].out_uop.debug_pc, slots_15.io.out_uop.debug_pc
connect issue_slots[15].out_uop.is_rvc, slots_15.io.out_uop.is_rvc
connect issue_slots[15].out_uop.debug_inst, slots_15.io.out_uop.debug_inst
connect issue_slots[15].out_uop.inst, slots_15.io.out_uop.inst
connect slots_15.io.in_uop.bits.debug_tsrc, issue_slots[15].in_uop.bits.debug_tsrc
connect slots_15.io.in_uop.bits.debug_fsrc, issue_slots[15].in_uop.bits.debug_fsrc
connect slots_15.io.in_uop.bits.bp_xcpt_if, issue_slots[15].in_uop.bits.bp_xcpt_if
connect slots_15.io.in_uop.bits.bp_debug_if, issue_slots[15].in_uop.bits.bp_debug_if
connect slots_15.io.in_uop.bits.xcpt_ma_if, issue_slots[15].in_uop.bits.xcpt_ma_if
connect slots_15.io.in_uop.bits.xcpt_ae_if, issue_slots[15].in_uop.bits.xcpt_ae_if
connect slots_15.io.in_uop.bits.xcpt_pf_if, issue_slots[15].in_uop.bits.xcpt_pf_if
connect slots_15.io.in_uop.bits.fp_typ, issue_slots[15].in_uop.bits.fp_typ
connect slots_15.io.in_uop.bits.fp_rm, issue_slots[15].in_uop.bits.fp_rm
connect slots_15.io.in_uop.bits.fp_val, issue_slots[15].in_uop.bits.fp_val
connect slots_15.io.in_uop.bits.fcn_op, issue_slots[15].in_uop.bits.fcn_op
connect slots_15.io.in_uop.bits.fcn_dw, issue_slots[15].in_uop.bits.fcn_dw
connect slots_15.io.in_uop.bits.frs3_en, issue_slots[15].in_uop.bits.frs3_en
connect slots_15.io.in_uop.bits.lrs2_rtype, issue_slots[15].in_uop.bits.lrs2_rtype
connect slots_15.io.in_uop.bits.lrs1_rtype, issue_slots[15].in_uop.bits.lrs1_rtype
connect slots_15.io.in_uop.bits.dst_rtype, issue_slots[15].in_uop.bits.dst_rtype
connect slots_15.io.in_uop.bits.lrs3, issue_slots[15].in_uop.bits.lrs3
connect slots_15.io.in_uop.bits.lrs2, issue_slots[15].in_uop.bits.lrs2
connect slots_15.io.in_uop.bits.lrs1, issue_slots[15].in_uop.bits.lrs1
connect slots_15.io.in_uop.bits.ldst, issue_slots[15].in_uop.bits.ldst
connect slots_15.io.in_uop.bits.ldst_is_rs1, issue_slots[15].in_uop.bits.ldst_is_rs1
connect slots_15.io.in_uop.bits.csr_cmd, issue_slots[15].in_uop.bits.csr_cmd
connect slots_15.io.in_uop.bits.flush_on_commit, issue_slots[15].in_uop.bits.flush_on_commit
connect slots_15.io.in_uop.bits.is_unique, issue_slots[15].in_uop.bits.is_unique
connect slots_15.io.in_uop.bits.uses_stq, issue_slots[15].in_uop.bits.uses_stq
connect slots_15.io.in_uop.bits.uses_ldq, issue_slots[15].in_uop.bits.uses_ldq
connect slots_15.io.in_uop.bits.mem_signed, issue_slots[15].in_uop.bits.mem_signed
connect slots_15.io.in_uop.bits.mem_size, issue_slots[15].in_uop.bits.mem_size
connect slots_15.io.in_uop.bits.mem_cmd, issue_slots[15].in_uop.bits.mem_cmd
connect slots_15.io.in_uop.bits.exc_cause, issue_slots[15].in_uop.bits.exc_cause
connect slots_15.io.in_uop.bits.exception, issue_slots[15].in_uop.bits.exception
connect slots_15.io.in_uop.bits.stale_pdst, issue_slots[15].in_uop.bits.stale_pdst
connect slots_15.io.in_uop.bits.ppred_busy, issue_slots[15].in_uop.bits.ppred_busy
connect slots_15.io.in_uop.bits.prs3_busy, issue_slots[15].in_uop.bits.prs3_busy
connect slots_15.io.in_uop.bits.prs2_busy, issue_slots[15].in_uop.bits.prs2_busy
connect slots_15.io.in_uop.bits.prs1_busy, issue_slots[15].in_uop.bits.prs1_busy
connect slots_15.io.in_uop.bits.ppred, issue_slots[15].in_uop.bits.ppred
connect slots_15.io.in_uop.bits.prs3, issue_slots[15].in_uop.bits.prs3
connect slots_15.io.in_uop.bits.prs2, issue_slots[15].in_uop.bits.prs2
connect slots_15.io.in_uop.bits.prs1, issue_slots[15].in_uop.bits.prs1
connect slots_15.io.in_uop.bits.pdst, issue_slots[15].in_uop.bits.pdst
connect slots_15.io.in_uop.bits.rxq_idx, issue_slots[15].in_uop.bits.rxq_idx
connect slots_15.io.in_uop.bits.stq_idx, issue_slots[15].in_uop.bits.stq_idx
connect slots_15.io.in_uop.bits.ldq_idx, issue_slots[15].in_uop.bits.ldq_idx
connect slots_15.io.in_uop.bits.rob_idx, issue_slots[15].in_uop.bits.rob_idx
connect slots_15.io.in_uop.bits.fp_ctrl.vec, issue_slots[15].in_uop.bits.fp_ctrl.vec
connect slots_15.io.in_uop.bits.fp_ctrl.wflags, issue_slots[15].in_uop.bits.fp_ctrl.wflags
connect slots_15.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[15].in_uop.bits.fp_ctrl.sqrt
connect slots_15.io.in_uop.bits.fp_ctrl.div, issue_slots[15].in_uop.bits.fp_ctrl.div
connect slots_15.io.in_uop.bits.fp_ctrl.fma, issue_slots[15].in_uop.bits.fp_ctrl.fma
connect slots_15.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[15].in_uop.bits.fp_ctrl.fastpipe
connect slots_15.io.in_uop.bits.fp_ctrl.toint, issue_slots[15].in_uop.bits.fp_ctrl.toint
connect slots_15.io.in_uop.bits.fp_ctrl.fromint, issue_slots[15].in_uop.bits.fp_ctrl.fromint
connect slots_15.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[15].in_uop.bits.fp_ctrl.typeTagOut
connect slots_15.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[15].in_uop.bits.fp_ctrl.typeTagIn
connect slots_15.io.in_uop.bits.fp_ctrl.swap23, issue_slots[15].in_uop.bits.fp_ctrl.swap23
connect slots_15.io.in_uop.bits.fp_ctrl.swap12, issue_slots[15].in_uop.bits.fp_ctrl.swap12
connect slots_15.io.in_uop.bits.fp_ctrl.ren3, issue_slots[15].in_uop.bits.fp_ctrl.ren3
connect slots_15.io.in_uop.bits.fp_ctrl.ren2, issue_slots[15].in_uop.bits.fp_ctrl.ren2
connect slots_15.io.in_uop.bits.fp_ctrl.ren1, issue_slots[15].in_uop.bits.fp_ctrl.ren1
connect slots_15.io.in_uop.bits.fp_ctrl.wen, issue_slots[15].in_uop.bits.fp_ctrl.wen
connect slots_15.io.in_uop.bits.fp_ctrl.ldst, issue_slots[15].in_uop.bits.fp_ctrl.ldst
connect slots_15.io.in_uop.bits.op2_sel, issue_slots[15].in_uop.bits.op2_sel
connect slots_15.io.in_uop.bits.op1_sel, issue_slots[15].in_uop.bits.op1_sel
connect slots_15.io.in_uop.bits.imm_packed, issue_slots[15].in_uop.bits.imm_packed
connect slots_15.io.in_uop.bits.pimm, issue_slots[15].in_uop.bits.pimm
connect slots_15.io.in_uop.bits.imm_sel, issue_slots[15].in_uop.bits.imm_sel
connect slots_15.io.in_uop.bits.imm_rename, issue_slots[15].in_uop.bits.imm_rename
connect slots_15.io.in_uop.bits.taken, issue_slots[15].in_uop.bits.taken
connect slots_15.io.in_uop.bits.pc_lob, issue_slots[15].in_uop.bits.pc_lob
connect slots_15.io.in_uop.bits.edge_inst, issue_slots[15].in_uop.bits.edge_inst
connect slots_15.io.in_uop.bits.ftq_idx, issue_slots[15].in_uop.bits.ftq_idx
connect slots_15.io.in_uop.bits.is_mov, issue_slots[15].in_uop.bits.is_mov
connect slots_15.io.in_uop.bits.is_rocc, issue_slots[15].in_uop.bits.is_rocc
connect slots_15.io.in_uop.bits.is_sys_pc2epc, issue_slots[15].in_uop.bits.is_sys_pc2epc
connect slots_15.io.in_uop.bits.is_eret, issue_slots[15].in_uop.bits.is_eret
connect slots_15.io.in_uop.bits.is_amo, issue_slots[15].in_uop.bits.is_amo
connect slots_15.io.in_uop.bits.is_sfence, issue_slots[15].in_uop.bits.is_sfence
connect slots_15.io.in_uop.bits.is_fencei, issue_slots[15].in_uop.bits.is_fencei
connect slots_15.io.in_uop.bits.is_fence, issue_slots[15].in_uop.bits.is_fence
connect slots_15.io.in_uop.bits.is_sfb, issue_slots[15].in_uop.bits.is_sfb
connect slots_15.io.in_uop.bits.br_type, issue_slots[15].in_uop.bits.br_type
connect slots_15.io.in_uop.bits.br_tag, issue_slots[15].in_uop.bits.br_tag
connect slots_15.io.in_uop.bits.br_mask, issue_slots[15].in_uop.bits.br_mask
connect slots_15.io.in_uop.bits.dis_col_sel, issue_slots[15].in_uop.bits.dis_col_sel
connect slots_15.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[15].in_uop.bits.iw_p3_bypass_hint
connect slots_15.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[15].in_uop.bits.iw_p2_bypass_hint
connect slots_15.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[15].in_uop.bits.iw_p1_bypass_hint
connect slots_15.io.in_uop.bits.iw_p2_speculative_child, issue_slots[15].in_uop.bits.iw_p2_speculative_child
connect slots_15.io.in_uop.bits.iw_p1_speculative_child, issue_slots[15].in_uop.bits.iw_p1_speculative_child
connect slots_15.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[15].in_uop.bits.iw_issued_partial_dgen
connect slots_15.io.in_uop.bits.iw_issued_partial_agen, issue_slots[15].in_uop.bits.iw_issued_partial_agen
connect slots_15.io.in_uop.bits.iw_issued, issue_slots[15].in_uop.bits.iw_issued
connect slots_15.io.in_uop.bits.fu_code[0], issue_slots[15].in_uop.bits.fu_code[0]
connect slots_15.io.in_uop.bits.fu_code[1], issue_slots[15].in_uop.bits.fu_code[1]
connect slots_15.io.in_uop.bits.fu_code[2], issue_slots[15].in_uop.bits.fu_code[2]
connect slots_15.io.in_uop.bits.fu_code[3], issue_slots[15].in_uop.bits.fu_code[3]
connect slots_15.io.in_uop.bits.fu_code[4], issue_slots[15].in_uop.bits.fu_code[4]
connect slots_15.io.in_uop.bits.fu_code[5], issue_slots[15].in_uop.bits.fu_code[5]
connect slots_15.io.in_uop.bits.fu_code[6], issue_slots[15].in_uop.bits.fu_code[6]
connect slots_15.io.in_uop.bits.fu_code[7], issue_slots[15].in_uop.bits.fu_code[7]
connect slots_15.io.in_uop.bits.fu_code[8], issue_slots[15].in_uop.bits.fu_code[8]
connect slots_15.io.in_uop.bits.fu_code[9], issue_slots[15].in_uop.bits.fu_code[9]
connect slots_15.io.in_uop.bits.iq_type[0], issue_slots[15].in_uop.bits.iq_type[0]
connect slots_15.io.in_uop.bits.iq_type[1], issue_slots[15].in_uop.bits.iq_type[1]
connect slots_15.io.in_uop.bits.iq_type[2], issue_slots[15].in_uop.bits.iq_type[2]
connect slots_15.io.in_uop.bits.iq_type[3], issue_slots[15].in_uop.bits.iq_type[3]
connect slots_15.io.in_uop.bits.debug_pc, issue_slots[15].in_uop.bits.debug_pc
connect slots_15.io.in_uop.bits.is_rvc, issue_slots[15].in_uop.bits.is_rvc
connect slots_15.io.in_uop.bits.debug_inst, issue_slots[15].in_uop.bits.debug_inst
connect slots_15.io.in_uop.bits.inst, issue_slots[15].in_uop.bits.inst
connect slots_15.io.in_uop.valid, issue_slots[15].in_uop.valid
connect issue_slots[15].iss_uop.debug_tsrc, slots_15.io.iss_uop.debug_tsrc
connect issue_slots[15].iss_uop.debug_fsrc, slots_15.io.iss_uop.debug_fsrc
connect issue_slots[15].iss_uop.bp_xcpt_if, slots_15.io.iss_uop.bp_xcpt_if
connect issue_slots[15].iss_uop.bp_debug_if, slots_15.io.iss_uop.bp_debug_if
connect issue_slots[15].iss_uop.xcpt_ma_if, slots_15.io.iss_uop.xcpt_ma_if
connect issue_slots[15].iss_uop.xcpt_ae_if, slots_15.io.iss_uop.xcpt_ae_if
connect issue_slots[15].iss_uop.xcpt_pf_if, slots_15.io.iss_uop.xcpt_pf_if
connect issue_slots[15].iss_uop.fp_typ, slots_15.io.iss_uop.fp_typ
connect issue_slots[15].iss_uop.fp_rm, slots_15.io.iss_uop.fp_rm
connect issue_slots[15].iss_uop.fp_val, slots_15.io.iss_uop.fp_val
connect issue_slots[15].iss_uop.fcn_op, slots_15.io.iss_uop.fcn_op
connect issue_slots[15].iss_uop.fcn_dw, slots_15.io.iss_uop.fcn_dw
connect issue_slots[15].iss_uop.frs3_en, slots_15.io.iss_uop.frs3_en
connect issue_slots[15].iss_uop.lrs2_rtype, slots_15.io.iss_uop.lrs2_rtype
connect issue_slots[15].iss_uop.lrs1_rtype, slots_15.io.iss_uop.lrs1_rtype
connect issue_slots[15].iss_uop.dst_rtype, slots_15.io.iss_uop.dst_rtype
connect issue_slots[15].iss_uop.lrs3, slots_15.io.iss_uop.lrs3
connect issue_slots[15].iss_uop.lrs2, slots_15.io.iss_uop.lrs2
connect issue_slots[15].iss_uop.lrs1, slots_15.io.iss_uop.lrs1
connect issue_slots[15].iss_uop.ldst, slots_15.io.iss_uop.ldst
connect issue_slots[15].iss_uop.ldst_is_rs1, slots_15.io.iss_uop.ldst_is_rs1
connect issue_slots[15].iss_uop.csr_cmd, slots_15.io.iss_uop.csr_cmd
connect issue_slots[15].iss_uop.flush_on_commit, slots_15.io.iss_uop.flush_on_commit
connect issue_slots[15].iss_uop.is_unique, slots_15.io.iss_uop.is_unique
connect issue_slots[15].iss_uop.uses_stq, slots_15.io.iss_uop.uses_stq
connect issue_slots[15].iss_uop.uses_ldq, slots_15.io.iss_uop.uses_ldq
connect issue_slots[15].iss_uop.mem_signed, slots_15.io.iss_uop.mem_signed
connect issue_slots[15].iss_uop.mem_size, slots_15.io.iss_uop.mem_size
connect issue_slots[15].iss_uop.mem_cmd, slots_15.io.iss_uop.mem_cmd
connect issue_slots[15].iss_uop.exc_cause, slots_15.io.iss_uop.exc_cause
connect issue_slots[15].iss_uop.exception, slots_15.io.iss_uop.exception
connect issue_slots[15].iss_uop.stale_pdst, slots_15.io.iss_uop.stale_pdst
connect issue_slots[15].iss_uop.ppred_busy, slots_15.io.iss_uop.ppred_busy
connect issue_slots[15].iss_uop.prs3_busy, slots_15.io.iss_uop.prs3_busy
connect issue_slots[15].iss_uop.prs2_busy, slots_15.io.iss_uop.prs2_busy
connect issue_slots[15].iss_uop.prs1_busy, slots_15.io.iss_uop.prs1_busy
connect issue_slots[15].iss_uop.ppred, slots_15.io.iss_uop.ppred
connect issue_slots[15].iss_uop.prs3, slots_15.io.iss_uop.prs3
connect issue_slots[15].iss_uop.prs2, slots_15.io.iss_uop.prs2
connect issue_slots[15].iss_uop.prs1, slots_15.io.iss_uop.prs1
connect issue_slots[15].iss_uop.pdst, slots_15.io.iss_uop.pdst
connect issue_slots[15].iss_uop.rxq_idx, slots_15.io.iss_uop.rxq_idx
connect issue_slots[15].iss_uop.stq_idx, slots_15.io.iss_uop.stq_idx
connect issue_slots[15].iss_uop.ldq_idx, slots_15.io.iss_uop.ldq_idx
connect issue_slots[15].iss_uop.rob_idx, slots_15.io.iss_uop.rob_idx
connect issue_slots[15].iss_uop.fp_ctrl.vec, slots_15.io.iss_uop.fp_ctrl.vec
connect issue_slots[15].iss_uop.fp_ctrl.wflags, slots_15.io.iss_uop.fp_ctrl.wflags
connect issue_slots[15].iss_uop.fp_ctrl.sqrt, slots_15.io.iss_uop.fp_ctrl.sqrt
connect issue_slots[15].iss_uop.fp_ctrl.div, slots_15.io.iss_uop.fp_ctrl.div
connect issue_slots[15].iss_uop.fp_ctrl.fma, slots_15.io.iss_uop.fp_ctrl.fma
connect issue_slots[15].iss_uop.fp_ctrl.fastpipe, slots_15.io.iss_uop.fp_ctrl.fastpipe
connect issue_slots[15].iss_uop.fp_ctrl.toint, slots_15.io.iss_uop.fp_ctrl.toint
connect issue_slots[15].iss_uop.fp_ctrl.fromint, slots_15.io.iss_uop.fp_ctrl.fromint
connect issue_slots[15].iss_uop.fp_ctrl.typeTagOut, slots_15.io.iss_uop.fp_ctrl.typeTagOut
connect issue_slots[15].iss_uop.fp_ctrl.typeTagIn, slots_15.io.iss_uop.fp_ctrl.typeTagIn
connect issue_slots[15].iss_uop.fp_ctrl.swap23, slots_15.io.iss_uop.fp_ctrl.swap23
connect issue_slots[15].iss_uop.fp_ctrl.swap12, slots_15.io.iss_uop.fp_ctrl.swap12
connect issue_slots[15].iss_uop.fp_ctrl.ren3, slots_15.io.iss_uop.fp_ctrl.ren3
connect issue_slots[15].iss_uop.fp_ctrl.ren2, slots_15.io.iss_uop.fp_ctrl.ren2
connect issue_slots[15].iss_uop.fp_ctrl.ren1, slots_15.io.iss_uop.fp_ctrl.ren1
connect issue_slots[15].iss_uop.fp_ctrl.wen, slots_15.io.iss_uop.fp_ctrl.wen
connect issue_slots[15].iss_uop.fp_ctrl.ldst, slots_15.io.iss_uop.fp_ctrl.ldst
connect issue_slots[15].iss_uop.op2_sel, slots_15.io.iss_uop.op2_sel
connect issue_slots[15].iss_uop.op1_sel, slots_15.io.iss_uop.op1_sel
connect issue_slots[15].iss_uop.imm_packed, slots_15.io.iss_uop.imm_packed
connect issue_slots[15].iss_uop.pimm, slots_15.io.iss_uop.pimm
connect issue_slots[15].iss_uop.imm_sel, slots_15.io.iss_uop.imm_sel
connect issue_slots[15].iss_uop.imm_rename, slots_15.io.iss_uop.imm_rename
connect issue_slots[15].iss_uop.taken, slots_15.io.iss_uop.taken
connect issue_slots[15].iss_uop.pc_lob, slots_15.io.iss_uop.pc_lob
connect issue_slots[15].iss_uop.edge_inst, slots_15.io.iss_uop.edge_inst
connect issue_slots[15].iss_uop.ftq_idx, slots_15.io.iss_uop.ftq_idx
connect issue_slots[15].iss_uop.is_mov, slots_15.io.iss_uop.is_mov
connect issue_slots[15].iss_uop.is_rocc, slots_15.io.iss_uop.is_rocc
connect issue_slots[15].iss_uop.is_sys_pc2epc, slots_15.io.iss_uop.is_sys_pc2epc
connect issue_slots[15].iss_uop.is_eret, slots_15.io.iss_uop.is_eret
connect issue_slots[15].iss_uop.is_amo, slots_15.io.iss_uop.is_amo
connect issue_slots[15].iss_uop.is_sfence, slots_15.io.iss_uop.is_sfence
connect issue_slots[15].iss_uop.is_fencei, slots_15.io.iss_uop.is_fencei
connect issue_slots[15].iss_uop.is_fence, slots_15.io.iss_uop.is_fence
connect issue_slots[15].iss_uop.is_sfb, slots_15.io.iss_uop.is_sfb
connect issue_slots[15].iss_uop.br_type, slots_15.io.iss_uop.br_type
connect issue_slots[15].iss_uop.br_tag, slots_15.io.iss_uop.br_tag
connect issue_slots[15].iss_uop.br_mask, slots_15.io.iss_uop.br_mask
connect issue_slots[15].iss_uop.dis_col_sel, slots_15.io.iss_uop.dis_col_sel
connect issue_slots[15].iss_uop.iw_p3_bypass_hint, slots_15.io.iss_uop.iw_p3_bypass_hint
connect issue_slots[15].iss_uop.iw_p2_bypass_hint, slots_15.io.iss_uop.iw_p2_bypass_hint
connect issue_slots[15].iss_uop.iw_p1_bypass_hint, slots_15.io.iss_uop.iw_p1_bypass_hint
connect issue_slots[15].iss_uop.iw_p2_speculative_child, slots_15.io.iss_uop.iw_p2_speculative_child
connect issue_slots[15].iss_uop.iw_p1_speculative_child, slots_15.io.iss_uop.iw_p1_speculative_child
connect issue_slots[15].iss_uop.iw_issued_partial_dgen, slots_15.io.iss_uop.iw_issued_partial_dgen
connect issue_slots[15].iss_uop.iw_issued_partial_agen, slots_15.io.iss_uop.iw_issued_partial_agen
connect issue_slots[15].iss_uop.iw_issued, slots_15.io.iss_uop.iw_issued
connect issue_slots[15].iss_uop.fu_code[0], slots_15.io.iss_uop.fu_code[0]
connect issue_slots[15].iss_uop.fu_code[1], slots_15.io.iss_uop.fu_code[1]
connect issue_slots[15].iss_uop.fu_code[2], slots_15.io.iss_uop.fu_code[2]
connect issue_slots[15].iss_uop.fu_code[3], slots_15.io.iss_uop.fu_code[3]
connect issue_slots[15].iss_uop.fu_code[4], slots_15.io.iss_uop.fu_code[4]
connect issue_slots[15].iss_uop.fu_code[5], slots_15.io.iss_uop.fu_code[5]
connect issue_slots[15].iss_uop.fu_code[6], slots_15.io.iss_uop.fu_code[6]
connect issue_slots[15].iss_uop.fu_code[7], slots_15.io.iss_uop.fu_code[7]
connect issue_slots[15].iss_uop.fu_code[8], slots_15.io.iss_uop.fu_code[8]
connect issue_slots[15].iss_uop.fu_code[9], slots_15.io.iss_uop.fu_code[9]
connect issue_slots[15].iss_uop.iq_type[0], slots_15.io.iss_uop.iq_type[0]
connect issue_slots[15].iss_uop.iq_type[1], slots_15.io.iss_uop.iq_type[1]
connect issue_slots[15].iss_uop.iq_type[2], slots_15.io.iss_uop.iq_type[2]
connect issue_slots[15].iss_uop.iq_type[3], slots_15.io.iss_uop.iq_type[3]
connect issue_slots[15].iss_uop.debug_pc, slots_15.io.iss_uop.debug_pc
connect issue_slots[15].iss_uop.is_rvc, slots_15.io.iss_uop.is_rvc
connect issue_slots[15].iss_uop.debug_inst, slots_15.io.iss_uop.debug_inst
connect issue_slots[15].iss_uop.inst, slots_15.io.iss_uop.inst
connect slots_15.io.grant, issue_slots[15].grant
connect issue_slots[15].request, slots_15.io.request
connect issue_slots[15].will_be_valid, slots_15.io.will_be_valid
connect issue_slots[15].valid, slots_15.io.valid
connect slots_16.io.child_rebusys, issue_slots[16].child_rebusys
connect slots_16.io.pred_wakeup_port.bits, issue_slots[16].pred_wakeup_port.bits
connect slots_16.io.pred_wakeup_port.valid, issue_slots[16].pred_wakeup_port.valid
connect slots_16.io.wakeup_ports[0].bits.rebusy, issue_slots[16].wakeup_ports[0].bits.rebusy
connect slots_16.io.wakeup_ports[0].bits.speculative_mask, issue_slots[16].wakeup_ports[0].bits.speculative_mask
connect slots_16.io.wakeup_ports[0].bits.bypassable, issue_slots[16].wakeup_ports[0].bits.bypassable
connect slots_16.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[16].wakeup_ports[0].bits.uop.debug_tsrc
connect slots_16.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[16].wakeup_ports[0].bits.uop.debug_fsrc
connect slots_16.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[16].wakeup_ports[0].bits.uop.bp_xcpt_if
connect slots_16.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[16].wakeup_ports[0].bits.uop.bp_debug_if
connect slots_16.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[16].wakeup_ports[0].bits.uop.xcpt_ma_if
connect slots_16.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[16].wakeup_ports[0].bits.uop.xcpt_ae_if
connect slots_16.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[16].wakeup_ports[0].bits.uop.xcpt_pf_if
connect slots_16.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[16].wakeup_ports[0].bits.uop.fp_typ
connect slots_16.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[16].wakeup_ports[0].bits.uop.fp_rm
connect slots_16.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[16].wakeup_ports[0].bits.uop.fp_val
connect slots_16.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[16].wakeup_ports[0].bits.uop.fcn_op
connect slots_16.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[16].wakeup_ports[0].bits.uop.fcn_dw
connect slots_16.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[16].wakeup_ports[0].bits.uop.frs3_en
connect slots_16.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[16].wakeup_ports[0].bits.uop.lrs2_rtype
connect slots_16.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[16].wakeup_ports[0].bits.uop.lrs1_rtype
connect slots_16.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[16].wakeup_ports[0].bits.uop.dst_rtype
connect slots_16.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[16].wakeup_ports[0].bits.uop.lrs3
connect slots_16.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[16].wakeup_ports[0].bits.uop.lrs2
connect slots_16.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[16].wakeup_ports[0].bits.uop.lrs1
connect slots_16.io.wakeup_ports[0].bits.uop.ldst, issue_slots[16].wakeup_ports[0].bits.uop.ldst
connect slots_16.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[16].wakeup_ports[0].bits.uop.ldst_is_rs1
connect slots_16.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[16].wakeup_ports[0].bits.uop.csr_cmd
connect slots_16.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[16].wakeup_ports[0].bits.uop.flush_on_commit
connect slots_16.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[16].wakeup_ports[0].bits.uop.is_unique
connect slots_16.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[16].wakeup_ports[0].bits.uop.uses_stq
connect slots_16.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[16].wakeup_ports[0].bits.uop.uses_ldq
connect slots_16.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[16].wakeup_ports[0].bits.uop.mem_signed
connect slots_16.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[16].wakeup_ports[0].bits.uop.mem_size
connect slots_16.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[16].wakeup_ports[0].bits.uop.mem_cmd
connect slots_16.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[16].wakeup_ports[0].bits.uop.exc_cause
connect slots_16.io.wakeup_ports[0].bits.uop.exception, issue_slots[16].wakeup_ports[0].bits.uop.exception
connect slots_16.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[16].wakeup_ports[0].bits.uop.stale_pdst
connect slots_16.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[16].wakeup_ports[0].bits.uop.ppred_busy
connect slots_16.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[16].wakeup_ports[0].bits.uop.prs3_busy
connect slots_16.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[16].wakeup_ports[0].bits.uop.prs2_busy
connect slots_16.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[16].wakeup_ports[0].bits.uop.prs1_busy
connect slots_16.io.wakeup_ports[0].bits.uop.ppred, issue_slots[16].wakeup_ports[0].bits.uop.ppred
connect slots_16.io.wakeup_ports[0].bits.uop.prs3, issue_slots[16].wakeup_ports[0].bits.uop.prs3
connect slots_16.io.wakeup_ports[0].bits.uop.prs2, issue_slots[16].wakeup_ports[0].bits.uop.prs2
connect slots_16.io.wakeup_ports[0].bits.uop.prs1, issue_slots[16].wakeup_ports[0].bits.uop.prs1
connect slots_16.io.wakeup_ports[0].bits.uop.pdst, issue_slots[16].wakeup_ports[0].bits.uop.pdst
connect slots_16.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[16].wakeup_ports[0].bits.uop.rxq_idx
connect slots_16.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[16].wakeup_ports[0].bits.uop.stq_idx
connect slots_16.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[16].wakeup_ports[0].bits.uop.ldq_idx
connect slots_16.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[16].wakeup_ports[0].bits.uop.rob_idx
connect slots_16.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.vec
connect slots_16.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.wflags
connect slots_16.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.sqrt
connect slots_16.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.div
connect slots_16.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.fma
connect slots_16.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe
connect slots_16.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.toint
connect slots_16.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.fromint
connect slots_16.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut
connect slots_16.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn
connect slots_16.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.swap23
connect slots_16.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.swap12
connect slots_16.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.ren3
connect slots_16.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.ren2
connect slots_16.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.ren1
connect slots_16.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.wen
connect slots_16.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.ldst
connect slots_16.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[16].wakeup_ports[0].bits.uop.op2_sel
connect slots_16.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[16].wakeup_ports[0].bits.uop.op1_sel
connect slots_16.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[16].wakeup_ports[0].bits.uop.imm_packed
connect slots_16.io.wakeup_ports[0].bits.uop.pimm, issue_slots[16].wakeup_ports[0].bits.uop.pimm
connect slots_16.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[16].wakeup_ports[0].bits.uop.imm_sel
connect slots_16.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[16].wakeup_ports[0].bits.uop.imm_rename
connect slots_16.io.wakeup_ports[0].bits.uop.taken, issue_slots[16].wakeup_ports[0].bits.uop.taken
connect slots_16.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[16].wakeup_ports[0].bits.uop.pc_lob
connect slots_16.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[16].wakeup_ports[0].bits.uop.edge_inst
connect slots_16.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[16].wakeup_ports[0].bits.uop.ftq_idx
connect slots_16.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[16].wakeup_ports[0].bits.uop.is_mov
connect slots_16.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[16].wakeup_ports[0].bits.uop.is_rocc
connect slots_16.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[16].wakeup_ports[0].bits.uop.is_sys_pc2epc
connect slots_16.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[16].wakeup_ports[0].bits.uop.is_eret
connect slots_16.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[16].wakeup_ports[0].bits.uop.is_amo
connect slots_16.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[16].wakeup_ports[0].bits.uop.is_sfence
connect slots_16.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[16].wakeup_ports[0].bits.uop.is_fencei
connect slots_16.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[16].wakeup_ports[0].bits.uop.is_fence
connect slots_16.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[16].wakeup_ports[0].bits.uop.is_sfb
connect slots_16.io.wakeup_ports[0].bits.uop.br_type, issue_slots[16].wakeup_ports[0].bits.uop.br_type
connect slots_16.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[16].wakeup_ports[0].bits.uop.br_tag
connect slots_16.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[16].wakeup_ports[0].bits.uop.br_mask
connect slots_16.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[16].wakeup_ports[0].bits.uop.dis_col_sel
connect slots_16.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[16].wakeup_ports[0].bits.uop.iw_p3_bypass_hint
connect slots_16.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[16].wakeup_ports[0].bits.uop.iw_p2_bypass_hint
connect slots_16.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[16].wakeup_ports[0].bits.uop.iw_p1_bypass_hint
connect slots_16.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[16].wakeup_ports[0].bits.uop.iw_p2_speculative_child
connect slots_16.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[16].wakeup_ports[0].bits.uop.iw_p1_speculative_child
connect slots_16.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[16].wakeup_ports[0].bits.uop.iw_issued_partial_dgen
connect slots_16.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[16].wakeup_ports[0].bits.uop.iw_issued_partial_agen
connect slots_16.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[16].wakeup_ports[0].bits.uop.iw_issued
connect slots_16.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[16].wakeup_ports[0].bits.uop.fu_code[0]
connect slots_16.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[16].wakeup_ports[0].bits.uop.fu_code[1]
connect slots_16.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[16].wakeup_ports[0].bits.uop.fu_code[2]
connect slots_16.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[16].wakeup_ports[0].bits.uop.fu_code[3]
connect slots_16.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[16].wakeup_ports[0].bits.uop.fu_code[4]
connect slots_16.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[16].wakeup_ports[0].bits.uop.fu_code[5]
connect slots_16.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[16].wakeup_ports[0].bits.uop.fu_code[6]
connect slots_16.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[16].wakeup_ports[0].bits.uop.fu_code[7]
connect slots_16.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[16].wakeup_ports[0].bits.uop.fu_code[8]
connect slots_16.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[16].wakeup_ports[0].bits.uop.fu_code[9]
connect slots_16.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[16].wakeup_ports[0].bits.uop.iq_type[0]
connect slots_16.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[16].wakeup_ports[0].bits.uop.iq_type[1]
connect slots_16.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[16].wakeup_ports[0].bits.uop.iq_type[2]
connect slots_16.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[16].wakeup_ports[0].bits.uop.iq_type[3]
connect slots_16.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[16].wakeup_ports[0].bits.uop.debug_pc
connect slots_16.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[16].wakeup_ports[0].bits.uop.is_rvc
connect slots_16.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[16].wakeup_ports[0].bits.uop.debug_inst
connect slots_16.io.wakeup_ports[0].bits.uop.inst, issue_slots[16].wakeup_ports[0].bits.uop.inst
connect slots_16.io.wakeup_ports[0].valid, issue_slots[16].wakeup_ports[0].valid
connect slots_16.io.wakeup_ports[1].bits.rebusy, issue_slots[16].wakeup_ports[1].bits.rebusy
connect slots_16.io.wakeup_ports[1].bits.speculative_mask, issue_slots[16].wakeup_ports[1].bits.speculative_mask
connect slots_16.io.wakeup_ports[1].bits.bypassable, issue_slots[16].wakeup_ports[1].bits.bypassable
connect slots_16.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[16].wakeup_ports[1].bits.uop.debug_tsrc
connect slots_16.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[16].wakeup_ports[1].bits.uop.debug_fsrc
connect slots_16.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[16].wakeup_ports[1].bits.uop.bp_xcpt_if
connect slots_16.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[16].wakeup_ports[1].bits.uop.bp_debug_if
connect slots_16.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[16].wakeup_ports[1].bits.uop.xcpt_ma_if
connect slots_16.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[16].wakeup_ports[1].bits.uop.xcpt_ae_if
connect slots_16.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[16].wakeup_ports[1].bits.uop.xcpt_pf_if
connect slots_16.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[16].wakeup_ports[1].bits.uop.fp_typ
connect slots_16.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[16].wakeup_ports[1].bits.uop.fp_rm
connect slots_16.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[16].wakeup_ports[1].bits.uop.fp_val
connect slots_16.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[16].wakeup_ports[1].bits.uop.fcn_op
connect slots_16.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[16].wakeup_ports[1].bits.uop.fcn_dw
connect slots_16.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[16].wakeup_ports[1].bits.uop.frs3_en
connect slots_16.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[16].wakeup_ports[1].bits.uop.lrs2_rtype
connect slots_16.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[16].wakeup_ports[1].bits.uop.lrs1_rtype
connect slots_16.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[16].wakeup_ports[1].bits.uop.dst_rtype
connect slots_16.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[16].wakeup_ports[1].bits.uop.lrs3
connect slots_16.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[16].wakeup_ports[1].bits.uop.lrs2
connect slots_16.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[16].wakeup_ports[1].bits.uop.lrs1
connect slots_16.io.wakeup_ports[1].bits.uop.ldst, issue_slots[16].wakeup_ports[1].bits.uop.ldst
connect slots_16.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[16].wakeup_ports[1].bits.uop.ldst_is_rs1
connect slots_16.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[16].wakeup_ports[1].bits.uop.csr_cmd
connect slots_16.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[16].wakeup_ports[1].bits.uop.flush_on_commit
connect slots_16.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[16].wakeup_ports[1].bits.uop.is_unique
connect slots_16.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[16].wakeup_ports[1].bits.uop.uses_stq
connect slots_16.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[16].wakeup_ports[1].bits.uop.uses_ldq
connect slots_16.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[16].wakeup_ports[1].bits.uop.mem_signed
connect slots_16.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[16].wakeup_ports[1].bits.uop.mem_size
connect slots_16.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[16].wakeup_ports[1].bits.uop.mem_cmd
connect slots_16.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[16].wakeup_ports[1].bits.uop.exc_cause
connect slots_16.io.wakeup_ports[1].bits.uop.exception, issue_slots[16].wakeup_ports[1].bits.uop.exception
connect slots_16.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[16].wakeup_ports[1].bits.uop.stale_pdst
connect slots_16.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[16].wakeup_ports[1].bits.uop.ppred_busy
connect slots_16.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[16].wakeup_ports[1].bits.uop.prs3_busy
connect slots_16.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[16].wakeup_ports[1].bits.uop.prs2_busy
connect slots_16.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[16].wakeup_ports[1].bits.uop.prs1_busy
connect slots_16.io.wakeup_ports[1].bits.uop.ppred, issue_slots[16].wakeup_ports[1].bits.uop.ppred
connect slots_16.io.wakeup_ports[1].bits.uop.prs3, issue_slots[16].wakeup_ports[1].bits.uop.prs3
connect slots_16.io.wakeup_ports[1].bits.uop.prs2, issue_slots[16].wakeup_ports[1].bits.uop.prs2
connect slots_16.io.wakeup_ports[1].bits.uop.prs1, issue_slots[16].wakeup_ports[1].bits.uop.prs1
connect slots_16.io.wakeup_ports[1].bits.uop.pdst, issue_slots[16].wakeup_ports[1].bits.uop.pdst
connect slots_16.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[16].wakeup_ports[1].bits.uop.rxq_idx
connect slots_16.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[16].wakeup_ports[1].bits.uop.stq_idx
connect slots_16.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[16].wakeup_ports[1].bits.uop.ldq_idx
connect slots_16.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[16].wakeup_ports[1].bits.uop.rob_idx
connect slots_16.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.vec
connect slots_16.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.wflags
connect slots_16.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.sqrt
connect slots_16.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.div
connect slots_16.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.fma
connect slots_16.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe
connect slots_16.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.toint
connect slots_16.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.fromint
connect slots_16.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut
connect slots_16.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn
connect slots_16.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.swap23
connect slots_16.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.swap12
connect slots_16.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.ren3
connect slots_16.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.ren2
connect slots_16.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.ren1
connect slots_16.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.wen
connect slots_16.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.ldst
connect slots_16.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[16].wakeup_ports[1].bits.uop.op2_sel
connect slots_16.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[16].wakeup_ports[1].bits.uop.op1_sel
connect slots_16.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[16].wakeup_ports[1].bits.uop.imm_packed
connect slots_16.io.wakeup_ports[1].bits.uop.pimm, issue_slots[16].wakeup_ports[1].bits.uop.pimm
connect slots_16.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[16].wakeup_ports[1].bits.uop.imm_sel
connect slots_16.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[16].wakeup_ports[1].bits.uop.imm_rename
connect slots_16.io.wakeup_ports[1].bits.uop.taken, issue_slots[16].wakeup_ports[1].bits.uop.taken
connect slots_16.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[16].wakeup_ports[1].bits.uop.pc_lob
connect slots_16.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[16].wakeup_ports[1].bits.uop.edge_inst
connect slots_16.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[16].wakeup_ports[1].bits.uop.ftq_idx
connect slots_16.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[16].wakeup_ports[1].bits.uop.is_mov
connect slots_16.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[16].wakeup_ports[1].bits.uop.is_rocc
connect slots_16.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[16].wakeup_ports[1].bits.uop.is_sys_pc2epc
connect slots_16.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[16].wakeup_ports[1].bits.uop.is_eret
connect slots_16.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[16].wakeup_ports[1].bits.uop.is_amo
connect slots_16.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[16].wakeup_ports[1].bits.uop.is_sfence
connect slots_16.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[16].wakeup_ports[1].bits.uop.is_fencei
connect slots_16.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[16].wakeup_ports[1].bits.uop.is_fence
connect slots_16.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[16].wakeup_ports[1].bits.uop.is_sfb
connect slots_16.io.wakeup_ports[1].bits.uop.br_type, issue_slots[16].wakeup_ports[1].bits.uop.br_type
connect slots_16.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[16].wakeup_ports[1].bits.uop.br_tag
connect slots_16.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[16].wakeup_ports[1].bits.uop.br_mask
connect slots_16.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[16].wakeup_ports[1].bits.uop.dis_col_sel
connect slots_16.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[16].wakeup_ports[1].bits.uop.iw_p3_bypass_hint
connect slots_16.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[16].wakeup_ports[1].bits.uop.iw_p2_bypass_hint
connect slots_16.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[16].wakeup_ports[1].bits.uop.iw_p1_bypass_hint
connect slots_16.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[16].wakeup_ports[1].bits.uop.iw_p2_speculative_child
connect slots_16.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[16].wakeup_ports[1].bits.uop.iw_p1_speculative_child
connect slots_16.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[16].wakeup_ports[1].bits.uop.iw_issued_partial_dgen
connect slots_16.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[16].wakeup_ports[1].bits.uop.iw_issued_partial_agen
connect slots_16.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[16].wakeup_ports[1].bits.uop.iw_issued
connect slots_16.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[16].wakeup_ports[1].bits.uop.fu_code[0]
connect slots_16.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[16].wakeup_ports[1].bits.uop.fu_code[1]
connect slots_16.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[16].wakeup_ports[1].bits.uop.fu_code[2]
connect slots_16.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[16].wakeup_ports[1].bits.uop.fu_code[3]
connect slots_16.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[16].wakeup_ports[1].bits.uop.fu_code[4]
connect slots_16.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[16].wakeup_ports[1].bits.uop.fu_code[5]
connect slots_16.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[16].wakeup_ports[1].bits.uop.fu_code[6]
connect slots_16.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[16].wakeup_ports[1].bits.uop.fu_code[7]
connect slots_16.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[16].wakeup_ports[1].bits.uop.fu_code[8]
connect slots_16.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[16].wakeup_ports[1].bits.uop.fu_code[9]
connect slots_16.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[16].wakeup_ports[1].bits.uop.iq_type[0]
connect slots_16.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[16].wakeup_ports[1].bits.uop.iq_type[1]
connect slots_16.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[16].wakeup_ports[1].bits.uop.iq_type[2]
connect slots_16.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[16].wakeup_ports[1].bits.uop.iq_type[3]
connect slots_16.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[16].wakeup_ports[1].bits.uop.debug_pc
connect slots_16.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[16].wakeup_ports[1].bits.uop.is_rvc
connect slots_16.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[16].wakeup_ports[1].bits.uop.debug_inst
connect slots_16.io.wakeup_ports[1].bits.uop.inst, issue_slots[16].wakeup_ports[1].bits.uop.inst
connect slots_16.io.wakeup_ports[1].valid, issue_slots[16].wakeup_ports[1].valid
connect slots_16.io.wakeup_ports[2].bits.rebusy, issue_slots[16].wakeup_ports[2].bits.rebusy
connect slots_16.io.wakeup_ports[2].bits.speculative_mask, issue_slots[16].wakeup_ports[2].bits.speculative_mask
connect slots_16.io.wakeup_ports[2].bits.bypassable, issue_slots[16].wakeup_ports[2].bits.bypassable
connect slots_16.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[16].wakeup_ports[2].bits.uop.debug_tsrc
connect slots_16.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[16].wakeup_ports[2].bits.uop.debug_fsrc
connect slots_16.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[16].wakeup_ports[2].bits.uop.bp_xcpt_if
connect slots_16.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[16].wakeup_ports[2].bits.uop.bp_debug_if
connect slots_16.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[16].wakeup_ports[2].bits.uop.xcpt_ma_if
connect slots_16.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[16].wakeup_ports[2].bits.uop.xcpt_ae_if
connect slots_16.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[16].wakeup_ports[2].bits.uop.xcpt_pf_if
connect slots_16.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[16].wakeup_ports[2].bits.uop.fp_typ
connect slots_16.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[16].wakeup_ports[2].bits.uop.fp_rm
connect slots_16.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[16].wakeup_ports[2].bits.uop.fp_val
connect slots_16.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[16].wakeup_ports[2].bits.uop.fcn_op
connect slots_16.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[16].wakeup_ports[2].bits.uop.fcn_dw
connect slots_16.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[16].wakeup_ports[2].bits.uop.frs3_en
connect slots_16.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[16].wakeup_ports[2].bits.uop.lrs2_rtype
connect slots_16.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[16].wakeup_ports[2].bits.uop.lrs1_rtype
connect slots_16.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[16].wakeup_ports[2].bits.uop.dst_rtype
connect slots_16.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[16].wakeup_ports[2].bits.uop.lrs3
connect slots_16.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[16].wakeup_ports[2].bits.uop.lrs2
connect slots_16.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[16].wakeup_ports[2].bits.uop.lrs1
connect slots_16.io.wakeup_ports[2].bits.uop.ldst, issue_slots[16].wakeup_ports[2].bits.uop.ldst
connect slots_16.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[16].wakeup_ports[2].bits.uop.ldst_is_rs1
connect slots_16.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[16].wakeup_ports[2].bits.uop.csr_cmd
connect slots_16.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[16].wakeup_ports[2].bits.uop.flush_on_commit
connect slots_16.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[16].wakeup_ports[2].bits.uop.is_unique
connect slots_16.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[16].wakeup_ports[2].bits.uop.uses_stq
connect slots_16.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[16].wakeup_ports[2].bits.uop.uses_ldq
connect slots_16.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[16].wakeup_ports[2].bits.uop.mem_signed
connect slots_16.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[16].wakeup_ports[2].bits.uop.mem_size
connect slots_16.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[16].wakeup_ports[2].bits.uop.mem_cmd
connect slots_16.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[16].wakeup_ports[2].bits.uop.exc_cause
connect slots_16.io.wakeup_ports[2].bits.uop.exception, issue_slots[16].wakeup_ports[2].bits.uop.exception
connect slots_16.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[16].wakeup_ports[2].bits.uop.stale_pdst
connect slots_16.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[16].wakeup_ports[2].bits.uop.ppred_busy
connect slots_16.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[16].wakeup_ports[2].bits.uop.prs3_busy
connect slots_16.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[16].wakeup_ports[2].bits.uop.prs2_busy
connect slots_16.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[16].wakeup_ports[2].bits.uop.prs1_busy
connect slots_16.io.wakeup_ports[2].bits.uop.ppred, issue_slots[16].wakeup_ports[2].bits.uop.ppred
connect slots_16.io.wakeup_ports[2].bits.uop.prs3, issue_slots[16].wakeup_ports[2].bits.uop.prs3
connect slots_16.io.wakeup_ports[2].bits.uop.prs2, issue_slots[16].wakeup_ports[2].bits.uop.prs2
connect slots_16.io.wakeup_ports[2].bits.uop.prs1, issue_slots[16].wakeup_ports[2].bits.uop.prs1
connect slots_16.io.wakeup_ports[2].bits.uop.pdst, issue_slots[16].wakeup_ports[2].bits.uop.pdst
connect slots_16.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[16].wakeup_ports[2].bits.uop.rxq_idx
connect slots_16.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[16].wakeup_ports[2].bits.uop.stq_idx
connect slots_16.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[16].wakeup_ports[2].bits.uop.ldq_idx
connect slots_16.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[16].wakeup_ports[2].bits.uop.rob_idx
connect slots_16.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.vec
connect slots_16.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.wflags
connect slots_16.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.sqrt
connect slots_16.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.div
connect slots_16.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.fma
connect slots_16.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe
connect slots_16.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.toint
connect slots_16.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.fromint
connect slots_16.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut
connect slots_16.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn
connect slots_16.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.swap23
connect slots_16.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.swap12
connect slots_16.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.ren3
connect slots_16.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.ren2
connect slots_16.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.ren1
connect slots_16.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.wen
connect slots_16.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.ldst
connect slots_16.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[16].wakeup_ports[2].bits.uop.op2_sel
connect slots_16.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[16].wakeup_ports[2].bits.uop.op1_sel
connect slots_16.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[16].wakeup_ports[2].bits.uop.imm_packed
connect slots_16.io.wakeup_ports[2].bits.uop.pimm, issue_slots[16].wakeup_ports[2].bits.uop.pimm
connect slots_16.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[16].wakeup_ports[2].bits.uop.imm_sel
connect slots_16.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[16].wakeup_ports[2].bits.uop.imm_rename
connect slots_16.io.wakeup_ports[2].bits.uop.taken, issue_slots[16].wakeup_ports[2].bits.uop.taken
connect slots_16.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[16].wakeup_ports[2].bits.uop.pc_lob
connect slots_16.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[16].wakeup_ports[2].bits.uop.edge_inst
connect slots_16.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[16].wakeup_ports[2].bits.uop.ftq_idx
connect slots_16.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[16].wakeup_ports[2].bits.uop.is_mov
connect slots_16.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[16].wakeup_ports[2].bits.uop.is_rocc
connect slots_16.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[16].wakeup_ports[2].bits.uop.is_sys_pc2epc
connect slots_16.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[16].wakeup_ports[2].bits.uop.is_eret
connect slots_16.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[16].wakeup_ports[2].bits.uop.is_amo
connect slots_16.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[16].wakeup_ports[2].bits.uop.is_sfence
connect slots_16.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[16].wakeup_ports[2].bits.uop.is_fencei
connect slots_16.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[16].wakeup_ports[2].bits.uop.is_fence
connect slots_16.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[16].wakeup_ports[2].bits.uop.is_sfb
connect slots_16.io.wakeup_ports[2].bits.uop.br_type, issue_slots[16].wakeup_ports[2].bits.uop.br_type
connect slots_16.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[16].wakeup_ports[2].bits.uop.br_tag
connect slots_16.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[16].wakeup_ports[2].bits.uop.br_mask
connect slots_16.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[16].wakeup_ports[2].bits.uop.dis_col_sel
connect slots_16.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[16].wakeup_ports[2].bits.uop.iw_p3_bypass_hint
connect slots_16.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[16].wakeup_ports[2].bits.uop.iw_p2_bypass_hint
connect slots_16.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[16].wakeup_ports[2].bits.uop.iw_p1_bypass_hint
connect slots_16.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[16].wakeup_ports[2].bits.uop.iw_p2_speculative_child
connect slots_16.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[16].wakeup_ports[2].bits.uop.iw_p1_speculative_child
connect slots_16.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[16].wakeup_ports[2].bits.uop.iw_issued_partial_dgen
connect slots_16.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[16].wakeup_ports[2].bits.uop.iw_issued_partial_agen
connect slots_16.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[16].wakeup_ports[2].bits.uop.iw_issued
connect slots_16.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[16].wakeup_ports[2].bits.uop.fu_code[0]
connect slots_16.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[16].wakeup_ports[2].bits.uop.fu_code[1]
connect slots_16.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[16].wakeup_ports[2].bits.uop.fu_code[2]
connect slots_16.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[16].wakeup_ports[2].bits.uop.fu_code[3]
connect slots_16.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[16].wakeup_ports[2].bits.uop.fu_code[4]
connect slots_16.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[16].wakeup_ports[2].bits.uop.fu_code[5]
connect slots_16.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[16].wakeup_ports[2].bits.uop.fu_code[6]
connect slots_16.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[16].wakeup_ports[2].bits.uop.fu_code[7]
connect slots_16.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[16].wakeup_ports[2].bits.uop.fu_code[8]
connect slots_16.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[16].wakeup_ports[2].bits.uop.fu_code[9]
connect slots_16.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[16].wakeup_ports[2].bits.uop.iq_type[0]
connect slots_16.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[16].wakeup_ports[2].bits.uop.iq_type[1]
connect slots_16.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[16].wakeup_ports[2].bits.uop.iq_type[2]
connect slots_16.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[16].wakeup_ports[2].bits.uop.iq_type[3]
connect slots_16.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[16].wakeup_ports[2].bits.uop.debug_pc
connect slots_16.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[16].wakeup_ports[2].bits.uop.is_rvc
connect slots_16.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[16].wakeup_ports[2].bits.uop.debug_inst
connect slots_16.io.wakeup_ports[2].bits.uop.inst, issue_slots[16].wakeup_ports[2].bits.uop.inst
connect slots_16.io.wakeup_ports[2].valid, issue_slots[16].wakeup_ports[2].valid
connect slots_16.io.wakeup_ports[3].bits.rebusy, issue_slots[16].wakeup_ports[3].bits.rebusy
connect slots_16.io.wakeup_ports[3].bits.speculative_mask, issue_slots[16].wakeup_ports[3].bits.speculative_mask
connect slots_16.io.wakeup_ports[3].bits.bypassable, issue_slots[16].wakeup_ports[3].bits.bypassable
connect slots_16.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[16].wakeup_ports[3].bits.uop.debug_tsrc
connect slots_16.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[16].wakeup_ports[3].bits.uop.debug_fsrc
connect slots_16.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[16].wakeup_ports[3].bits.uop.bp_xcpt_if
connect slots_16.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[16].wakeup_ports[3].bits.uop.bp_debug_if
connect slots_16.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[16].wakeup_ports[3].bits.uop.xcpt_ma_if
connect slots_16.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[16].wakeup_ports[3].bits.uop.xcpt_ae_if
connect slots_16.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[16].wakeup_ports[3].bits.uop.xcpt_pf_if
connect slots_16.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[16].wakeup_ports[3].bits.uop.fp_typ
connect slots_16.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[16].wakeup_ports[3].bits.uop.fp_rm
connect slots_16.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[16].wakeup_ports[3].bits.uop.fp_val
connect slots_16.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[16].wakeup_ports[3].bits.uop.fcn_op
connect slots_16.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[16].wakeup_ports[3].bits.uop.fcn_dw
connect slots_16.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[16].wakeup_ports[3].bits.uop.frs3_en
connect slots_16.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[16].wakeup_ports[3].bits.uop.lrs2_rtype
connect slots_16.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[16].wakeup_ports[3].bits.uop.lrs1_rtype
connect slots_16.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[16].wakeup_ports[3].bits.uop.dst_rtype
connect slots_16.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[16].wakeup_ports[3].bits.uop.lrs3
connect slots_16.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[16].wakeup_ports[3].bits.uop.lrs2
connect slots_16.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[16].wakeup_ports[3].bits.uop.lrs1
connect slots_16.io.wakeup_ports[3].bits.uop.ldst, issue_slots[16].wakeup_ports[3].bits.uop.ldst
connect slots_16.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[16].wakeup_ports[3].bits.uop.ldst_is_rs1
connect slots_16.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[16].wakeup_ports[3].bits.uop.csr_cmd
connect slots_16.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[16].wakeup_ports[3].bits.uop.flush_on_commit
connect slots_16.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[16].wakeup_ports[3].bits.uop.is_unique
connect slots_16.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[16].wakeup_ports[3].bits.uop.uses_stq
connect slots_16.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[16].wakeup_ports[3].bits.uop.uses_ldq
connect slots_16.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[16].wakeup_ports[3].bits.uop.mem_signed
connect slots_16.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[16].wakeup_ports[3].bits.uop.mem_size
connect slots_16.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[16].wakeup_ports[3].bits.uop.mem_cmd
connect slots_16.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[16].wakeup_ports[3].bits.uop.exc_cause
connect slots_16.io.wakeup_ports[3].bits.uop.exception, issue_slots[16].wakeup_ports[3].bits.uop.exception
connect slots_16.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[16].wakeup_ports[3].bits.uop.stale_pdst
connect slots_16.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[16].wakeup_ports[3].bits.uop.ppred_busy
connect slots_16.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[16].wakeup_ports[3].bits.uop.prs3_busy
connect slots_16.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[16].wakeup_ports[3].bits.uop.prs2_busy
connect slots_16.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[16].wakeup_ports[3].bits.uop.prs1_busy
connect slots_16.io.wakeup_ports[3].bits.uop.ppred, issue_slots[16].wakeup_ports[3].bits.uop.ppred
connect slots_16.io.wakeup_ports[3].bits.uop.prs3, issue_slots[16].wakeup_ports[3].bits.uop.prs3
connect slots_16.io.wakeup_ports[3].bits.uop.prs2, issue_slots[16].wakeup_ports[3].bits.uop.prs2
connect slots_16.io.wakeup_ports[3].bits.uop.prs1, issue_slots[16].wakeup_ports[3].bits.uop.prs1
connect slots_16.io.wakeup_ports[3].bits.uop.pdst, issue_slots[16].wakeup_ports[3].bits.uop.pdst
connect slots_16.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[16].wakeup_ports[3].bits.uop.rxq_idx
connect slots_16.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[16].wakeup_ports[3].bits.uop.stq_idx
connect slots_16.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[16].wakeup_ports[3].bits.uop.ldq_idx
connect slots_16.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[16].wakeup_ports[3].bits.uop.rob_idx
connect slots_16.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.vec
connect slots_16.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.wflags
connect slots_16.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.sqrt
connect slots_16.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.div
connect slots_16.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.fma
connect slots_16.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe
connect slots_16.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.toint
connect slots_16.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.fromint
connect slots_16.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut
connect slots_16.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn
connect slots_16.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.swap23
connect slots_16.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.swap12
connect slots_16.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.ren3
connect slots_16.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.ren2
connect slots_16.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.ren1
connect slots_16.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.wen
connect slots_16.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.ldst
connect slots_16.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[16].wakeup_ports[3].bits.uop.op2_sel
connect slots_16.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[16].wakeup_ports[3].bits.uop.op1_sel
connect slots_16.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[16].wakeup_ports[3].bits.uop.imm_packed
connect slots_16.io.wakeup_ports[3].bits.uop.pimm, issue_slots[16].wakeup_ports[3].bits.uop.pimm
connect slots_16.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[16].wakeup_ports[3].bits.uop.imm_sel
connect slots_16.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[16].wakeup_ports[3].bits.uop.imm_rename
connect slots_16.io.wakeup_ports[3].bits.uop.taken, issue_slots[16].wakeup_ports[3].bits.uop.taken
connect slots_16.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[16].wakeup_ports[3].bits.uop.pc_lob
connect slots_16.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[16].wakeup_ports[3].bits.uop.edge_inst
connect slots_16.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[16].wakeup_ports[3].bits.uop.ftq_idx
connect slots_16.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[16].wakeup_ports[3].bits.uop.is_mov
connect slots_16.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[16].wakeup_ports[3].bits.uop.is_rocc
connect slots_16.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[16].wakeup_ports[3].bits.uop.is_sys_pc2epc
connect slots_16.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[16].wakeup_ports[3].bits.uop.is_eret
connect slots_16.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[16].wakeup_ports[3].bits.uop.is_amo
connect slots_16.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[16].wakeup_ports[3].bits.uop.is_sfence
connect slots_16.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[16].wakeup_ports[3].bits.uop.is_fencei
connect slots_16.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[16].wakeup_ports[3].bits.uop.is_fence
connect slots_16.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[16].wakeup_ports[3].bits.uop.is_sfb
connect slots_16.io.wakeup_ports[3].bits.uop.br_type, issue_slots[16].wakeup_ports[3].bits.uop.br_type
connect slots_16.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[16].wakeup_ports[3].bits.uop.br_tag
connect slots_16.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[16].wakeup_ports[3].bits.uop.br_mask
connect slots_16.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[16].wakeup_ports[3].bits.uop.dis_col_sel
connect slots_16.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[16].wakeup_ports[3].bits.uop.iw_p3_bypass_hint
connect slots_16.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[16].wakeup_ports[3].bits.uop.iw_p2_bypass_hint
connect slots_16.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[16].wakeup_ports[3].bits.uop.iw_p1_bypass_hint
connect slots_16.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[16].wakeup_ports[3].bits.uop.iw_p2_speculative_child
connect slots_16.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[16].wakeup_ports[3].bits.uop.iw_p1_speculative_child
connect slots_16.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[16].wakeup_ports[3].bits.uop.iw_issued_partial_dgen
connect slots_16.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[16].wakeup_ports[3].bits.uop.iw_issued_partial_agen
connect slots_16.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[16].wakeup_ports[3].bits.uop.iw_issued
connect slots_16.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[16].wakeup_ports[3].bits.uop.fu_code[0]
connect slots_16.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[16].wakeup_ports[3].bits.uop.fu_code[1]
connect slots_16.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[16].wakeup_ports[3].bits.uop.fu_code[2]
connect slots_16.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[16].wakeup_ports[3].bits.uop.fu_code[3]
connect slots_16.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[16].wakeup_ports[3].bits.uop.fu_code[4]
connect slots_16.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[16].wakeup_ports[3].bits.uop.fu_code[5]
connect slots_16.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[16].wakeup_ports[3].bits.uop.fu_code[6]
connect slots_16.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[16].wakeup_ports[3].bits.uop.fu_code[7]
connect slots_16.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[16].wakeup_ports[3].bits.uop.fu_code[8]
connect slots_16.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[16].wakeup_ports[3].bits.uop.fu_code[9]
connect slots_16.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[16].wakeup_ports[3].bits.uop.iq_type[0]
connect slots_16.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[16].wakeup_ports[3].bits.uop.iq_type[1]
connect slots_16.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[16].wakeup_ports[3].bits.uop.iq_type[2]
connect slots_16.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[16].wakeup_ports[3].bits.uop.iq_type[3]
connect slots_16.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[16].wakeup_ports[3].bits.uop.debug_pc
connect slots_16.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[16].wakeup_ports[3].bits.uop.is_rvc
connect slots_16.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[16].wakeup_ports[3].bits.uop.debug_inst
connect slots_16.io.wakeup_ports[3].bits.uop.inst, issue_slots[16].wakeup_ports[3].bits.uop.inst
connect slots_16.io.wakeup_ports[3].valid, issue_slots[16].wakeup_ports[3].valid
connect slots_16.io.squash_grant, issue_slots[16].squash_grant
connect slots_16.io.clear, issue_slots[16].clear
connect slots_16.io.kill, issue_slots[16].kill
connect slots_16.io.brupdate.b2.target_offset, issue_slots[16].brupdate.b2.target_offset
connect slots_16.io.brupdate.b2.jalr_target, issue_slots[16].brupdate.b2.jalr_target
connect slots_16.io.brupdate.b2.pc_sel, issue_slots[16].brupdate.b2.pc_sel
connect slots_16.io.brupdate.b2.cfi_type, issue_slots[16].brupdate.b2.cfi_type
connect slots_16.io.brupdate.b2.taken, issue_slots[16].brupdate.b2.taken
connect slots_16.io.brupdate.b2.mispredict, issue_slots[16].brupdate.b2.mispredict
connect slots_16.io.brupdate.b2.uop.debug_tsrc, issue_slots[16].brupdate.b2.uop.debug_tsrc
connect slots_16.io.brupdate.b2.uop.debug_fsrc, issue_slots[16].brupdate.b2.uop.debug_fsrc
connect slots_16.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[16].brupdate.b2.uop.bp_xcpt_if
connect slots_16.io.brupdate.b2.uop.bp_debug_if, issue_slots[16].brupdate.b2.uop.bp_debug_if
connect slots_16.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[16].brupdate.b2.uop.xcpt_ma_if
connect slots_16.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[16].brupdate.b2.uop.xcpt_ae_if
connect slots_16.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[16].brupdate.b2.uop.xcpt_pf_if
connect slots_16.io.brupdate.b2.uop.fp_typ, issue_slots[16].brupdate.b2.uop.fp_typ
connect slots_16.io.brupdate.b2.uop.fp_rm, issue_slots[16].brupdate.b2.uop.fp_rm
connect slots_16.io.brupdate.b2.uop.fp_val, issue_slots[16].brupdate.b2.uop.fp_val
connect slots_16.io.brupdate.b2.uop.fcn_op, issue_slots[16].brupdate.b2.uop.fcn_op
connect slots_16.io.brupdate.b2.uop.fcn_dw, issue_slots[16].brupdate.b2.uop.fcn_dw
connect slots_16.io.brupdate.b2.uop.frs3_en, issue_slots[16].brupdate.b2.uop.frs3_en
connect slots_16.io.brupdate.b2.uop.lrs2_rtype, issue_slots[16].brupdate.b2.uop.lrs2_rtype
connect slots_16.io.brupdate.b2.uop.lrs1_rtype, issue_slots[16].brupdate.b2.uop.lrs1_rtype
connect slots_16.io.brupdate.b2.uop.dst_rtype, issue_slots[16].brupdate.b2.uop.dst_rtype
connect slots_16.io.brupdate.b2.uop.lrs3, issue_slots[16].brupdate.b2.uop.lrs3
connect slots_16.io.brupdate.b2.uop.lrs2, issue_slots[16].brupdate.b2.uop.lrs2
connect slots_16.io.brupdate.b2.uop.lrs1, issue_slots[16].brupdate.b2.uop.lrs1
connect slots_16.io.brupdate.b2.uop.ldst, issue_slots[16].brupdate.b2.uop.ldst
connect slots_16.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[16].brupdate.b2.uop.ldst_is_rs1
connect slots_16.io.brupdate.b2.uop.csr_cmd, issue_slots[16].brupdate.b2.uop.csr_cmd
connect slots_16.io.brupdate.b2.uop.flush_on_commit, issue_slots[16].brupdate.b2.uop.flush_on_commit
connect slots_16.io.brupdate.b2.uop.is_unique, issue_slots[16].brupdate.b2.uop.is_unique
connect slots_16.io.brupdate.b2.uop.uses_stq, issue_slots[16].brupdate.b2.uop.uses_stq
connect slots_16.io.brupdate.b2.uop.uses_ldq, issue_slots[16].brupdate.b2.uop.uses_ldq
connect slots_16.io.brupdate.b2.uop.mem_signed, issue_slots[16].brupdate.b2.uop.mem_signed
connect slots_16.io.brupdate.b2.uop.mem_size, issue_slots[16].brupdate.b2.uop.mem_size
connect slots_16.io.brupdate.b2.uop.mem_cmd, issue_slots[16].brupdate.b2.uop.mem_cmd
connect slots_16.io.brupdate.b2.uop.exc_cause, issue_slots[16].brupdate.b2.uop.exc_cause
connect slots_16.io.brupdate.b2.uop.exception, issue_slots[16].brupdate.b2.uop.exception
connect slots_16.io.brupdate.b2.uop.stale_pdst, issue_slots[16].brupdate.b2.uop.stale_pdst
connect slots_16.io.brupdate.b2.uop.ppred_busy, issue_slots[16].brupdate.b2.uop.ppred_busy
connect slots_16.io.brupdate.b2.uop.prs3_busy, issue_slots[16].brupdate.b2.uop.prs3_busy
connect slots_16.io.brupdate.b2.uop.prs2_busy, issue_slots[16].brupdate.b2.uop.prs2_busy
connect slots_16.io.brupdate.b2.uop.prs1_busy, issue_slots[16].brupdate.b2.uop.prs1_busy
connect slots_16.io.brupdate.b2.uop.ppred, issue_slots[16].brupdate.b2.uop.ppred
connect slots_16.io.brupdate.b2.uop.prs3, issue_slots[16].brupdate.b2.uop.prs3
connect slots_16.io.brupdate.b2.uop.prs2, issue_slots[16].brupdate.b2.uop.prs2
connect slots_16.io.brupdate.b2.uop.prs1, issue_slots[16].brupdate.b2.uop.prs1
connect slots_16.io.brupdate.b2.uop.pdst, issue_slots[16].brupdate.b2.uop.pdst
connect slots_16.io.brupdate.b2.uop.rxq_idx, issue_slots[16].brupdate.b2.uop.rxq_idx
connect slots_16.io.brupdate.b2.uop.stq_idx, issue_slots[16].brupdate.b2.uop.stq_idx
connect slots_16.io.brupdate.b2.uop.ldq_idx, issue_slots[16].brupdate.b2.uop.ldq_idx
connect slots_16.io.brupdate.b2.uop.rob_idx, issue_slots[16].brupdate.b2.uop.rob_idx
connect slots_16.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[16].brupdate.b2.uop.fp_ctrl.vec
connect slots_16.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[16].brupdate.b2.uop.fp_ctrl.wflags
connect slots_16.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[16].brupdate.b2.uop.fp_ctrl.sqrt
connect slots_16.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[16].brupdate.b2.uop.fp_ctrl.div
connect slots_16.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[16].brupdate.b2.uop.fp_ctrl.fma
connect slots_16.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[16].brupdate.b2.uop.fp_ctrl.fastpipe
connect slots_16.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[16].brupdate.b2.uop.fp_ctrl.toint
connect slots_16.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[16].brupdate.b2.uop.fp_ctrl.fromint
connect slots_16.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[16].brupdate.b2.uop.fp_ctrl.typeTagOut
connect slots_16.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[16].brupdate.b2.uop.fp_ctrl.typeTagIn
connect slots_16.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[16].brupdate.b2.uop.fp_ctrl.swap23
connect slots_16.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[16].brupdate.b2.uop.fp_ctrl.swap12
connect slots_16.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[16].brupdate.b2.uop.fp_ctrl.ren3
connect slots_16.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[16].brupdate.b2.uop.fp_ctrl.ren2
connect slots_16.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[16].brupdate.b2.uop.fp_ctrl.ren1
connect slots_16.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[16].brupdate.b2.uop.fp_ctrl.wen
connect slots_16.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[16].brupdate.b2.uop.fp_ctrl.ldst
connect slots_16.io.brupdate.b2.uop.op2_sel, issue_slots[16].brupdate.b2.uop.op2_sel
connect slots_16.io.brupdate.b2.uop.op1_sel, issue_slots[16].brupdate.b2.uop.op1_sel
connect slots_16.io.brupdate.b2.uop.imm_packed, issue_slots[16].brupdate.b2.uop.imm_packed
connect slots_16.io.brupdate.b2.uop.pimm, issue_slots[16].brupdate.b2.uop.pimm
connect slots_16.io.brupdate.b2.uop.imm_sel, issue_slots[16].brupdate.b2.uop.imm_sel
connect slots_16.io.brupdate.b2.uop.imm_rename, issue_slots[16].brupdate.b2.uop.imm_rename
connect slots_16.io.brupdate.b2.uop.taken, issue_slots[16].brupdate.b2.uop.taken
connect slots_16.io.brupdate.b2.uop.pc_lob, issue_slots[16].brupdate.b2.uop.pc_lob
connect slots_16.io.brupdate.b2.uop.edge_inst, issue_slots[16].brupdate.b2.uop.edge_inst
connect slots_16.io.brupdate.b2.uop.ftq_idx, issue_slots[16].brupdate.b2.uop.ftq_idx
connect slots_16.io.brupdate.b2.uop.is_mov, issue_slots[16].brupdate.b2.uop.is_mov
connect slots_16.io.brupdate.b2.uop.is_rocc, issue_slots[16].brupdate.b2.uop.is_rocc
connect slots_16.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[16].brupdate.b2.uop.is_sys_pc2epc
connect slots_16.io.brupdate.b2.uop.is_eret, issue_slots[16].brupdate.b2.uop.is_eret
connect slots_16.io.brupdate.b2.uop.is_amo, issue_slots[16].brupdate.b2.uop.is_amo
connect slots_16.io.brupdate.b2.uop.is_sfence, issue_slots[16].brupdate.b2.uop.is_sfence
connect slots_16.io.brupdate.b2.uop.is_fencei, issue_slots[16].brupdate.b2.uop.is_fencei
connect slots_16.io.brupdate.b2.uop.is_fence, issue_slots[16].brupdate.b2.uop.is_fence
connect slots_16.io.brupdate.b2.uop.is_sfb, issue_slots[16].brupdate.b2.uop.is_sfb
connect slots_16.io.brupdate.b2.uop.br_type, issue_slots[16].brupdate.b2.uop.br_type
connect slots_16.io.brupdate.b2.uop.br_tag, issue_slots[16].brupdate.b2.uop.br_tag
connect slots_16.io.brupdate.b2.uop.br_mask, issue_slots[16].brupdate.b2.uop.br_mask
connect slots_16.io.brupdate.b2.uop.dis_col_sel, issue_slots[16].brupdate.b2.uop.dis_col_sel
connect slots_16.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[16].brupdate.b2.uop.iw_p3_bypass_hint
connect slots_16.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[16].brupdate.b2.uop.iw_p2_bypass_hint
connect slots_16.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[16].brupdate.b2.uop.iw_p1_bypass_hint
connect slots_16.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[16].brupdate.b2.uop.iw_p2_speculative_child
connect slots_16.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[16].brupdate.b2.uop.iw_p1_speculative_child
connect slots_16.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[16].brupdate.b2.uop.iw_issued_partial_dgen
connect slots_16.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[16].brupdate.b2.uop.iw_issued_partial_agen
connect slots_16.io.brupdate.b2.uop.iw_issued, issue_slots[16].brupdate.b2.uop.iw_issued
connect slots_16.io.brupdate.b2.uop.fu_code[0], issue_slots[16].brupdate.b2.uop.fu_code[0]
connect slots_16.io.brupdate.b2.uop.fu_code[1], issue_slots[16].brupdate.b2.uop.fu_code[1]
connect slots_16.io.brupdate.b2.uop.fu_code[2], issue_slots[16].brupdate.b2.uop.fu_code[2]
connect slots_16.io.brupdate.b2.uop.fu_code[3], issue_slots[16].brupdate.b2.uop.fu_code[3]
connect slots_16.io.brupdate.b2.uop.fu_code[4], issue_slots[16].brupdate.b2.uop.fu_code[4]
connect slots_16.io.brupdate.b2.uop.fu_code[5], issue_slots[16].brupdate.b2.uop.fu_code[5]
connect slots_16.io.brupdate.b2.uop.fu_code[6], issue_slots[16].brupdate.b2.uop.fu_code[6]
connect slots_16.io.brupdate.b2.uop.fu_code[7], issue_slots[16].brupdate.b2.uop.fu_code[7]
connect slots_16.io.brupdate.b2.uop.fu_code[8], issue_slots[16].brupdate.b2.uop.fu_code[8]
connect slots_16.io.brupdate.b2.uop.fu_code[9], issue_slots[16].brupdate.b2.uop.fu_code[9]
connect slots_16.io.brupdate.b2.uop.iq_type[0], issue_slots[16].brupdate.b2.uop.iq_type[0]
connect slots_16.io.brupdate.b2.uop.iq_type[1], issue_slots[16].brupdate.b2.uop.iq_type[1]
connect slots_16.io.brupdate.b2.uop.iq_type[2], issue_slots[16].brupdate.b2.uop.iq_type[2]
connect slots_16.io.brupdate.b2.uop.iq_type[3], issue_slots[16].brupdate.b2.uop.iq_type[3]
connect slots_16.io.brupdate.b2.uop.debug_pc, issue_slots[16].brupdate.b2.uop.debug_pc
connect slots_16.io.brupdate.b2.uop.is_rvc, issue_slots[16].brupdate.b2.uop.is_rvc
connect slots_16.io.brupdate.b2.uop.debug_inst, issue_slots[16].brupdate.b2.uop.debug_inst
connect slots_16.io.brupdate.b2.uop.inst, issue_slots[16].brupdate.b2.uop.inst
connect slots_16.io.brupdate.b1.mispredict_mask, issue_slots[16].brupdate.b1.mispredict_mask
connect slots_16.io.brupdate.b1.resolve_mask, issue_slots[16].brupdate.b1.resolve_mask
connect issue_slots[16].out_uop.debug_tsrc, slots_16.io.out_uop.debug_tsrc
connect issue_slots[16].out_uop.debug_fsrc, slots_16.io.out_uop.debug_fsrc
connect issue_slots[16].out_uop.bp_xcpt_if, slots_16.io.out_uop.bp_xcpt_if
connect issue_slots[16].out_uop.bp_debug_if, slots_16.io.out_uop.bp_debug_if
connect issue_slots[16].out_uop.xcpt_ma_if, slots_16.io.out_uop.xcpt_ma_if
connect issue_slots[16].out_uop.xcpt_ae_if, slots_16.io.out_uop.xcpt_ae_if
connect issue_slots[16].out_uop.xcpt_pf_if, slots_16.io.out_uop.xcpt_pf_if
connect issue_slots[16].out_uop.fp_typ, slots_16.io.out_uop.fp_typ
connect issue_slots[16].out_uop.fp_rm, slots_16.io.out_uop.fp_rm
connect issue_slots[16].out_uop.fp_val, slots_16.io.out_uop.fp_val
connect issue_slots[16].out_uop.fcn_op, slots_16.io.out_uop.fcn_op
connect issue_slots[16].out_uop.fcn_dw, slots_16.io.out_uop.fcn_dw
connect issue_slots[16].out_uop.frs3_en, slots_16.io.out_uop.frs3_en
connect issue_slots[16].out_uop.lrs2_rtype, slots_16.io.out_uop.lrs2_rtype
connect issue_slots[16].out_uop.lrs1_rtype, slots_16.io.out_uop.lrs1_rtype
connect issue_slots[16].out_uop.dst_rtype, slots_16.io.out_uop.dst_rtype
connect issue_slots[16].out_uop.lrs3, slots_16.io.out_uop.lrs3
connect issue_slots[16].out_uop.lrs2, slots_16.io.out_uop.lrs2
connect issue_slots[16].out_uop.lrs1, slots_16.io.out_uop.lrs1
connect issue_slots[16].out_uop.ldst, slots_16.io.out_uop.ldst
connect issue_slots[16].out_uop.ldst_is_rs1, slots_16.io.out_uop.ldst_is_rs1
connect issue_slots[16].out_uop.csr_cmd, slots_16.io.out_uop.csr_cmd
connect issue_slots[16].out_uop.flush_on_commit, slots_16.io.out_uop.flush_on_commit
connect issue_slots[16].out_uop.is_unique, slots_16.io.out_uop.is_unique
connect issue_slots[16].out_uop.uses_stq, slots_16.io.out_uop.uses_stq
connect issue_slots[16].out_uop.uses_ldq, slots_16.io.out_uop.uses_ldq
connect issue_slots[16].out_uop.mem_signed, slots_16.io.out_uop.mem_signed
connect issue_slots[16].out_uop.mem_size, slots_16.io.out_uop.mem_size
connect issue_slots[16].out_uop.mem_cmd, slots_16.io.out_uop.mem_cmd
connect issue_slots[16].out_uop.exc_cause, slots_16.io.out_uop.exc_cause
connect issue_slots[16].out_uop.exception, slots_16.io.out_uop.exception
connect issue_slots[16].out_uop.stale_pdst, slots_16.io.out_uop.stale_pdst
connect issue_slots[16].out_uop.ppred_busy, slots_16.io.out_uop.ppred_busy
connect issue_slots[16].out_uop.prs3_busy, slots_16.io.out_uop.prs3_busy
connect issue_slots[16].out_uop.prs2_busy, slots_16.io.out_uop.prs2_busy
connect issue_slots[16].out_uop.prs1_busy, slots_16.io.out_uop.prs1_busy
connect issue_slots[16].out_uop.ppred, slots_16.io.out_uop.ppred
connect issue_slots[16].out_uop.prs3, slots_16.io.out_uop.prs3
connect issue_slots[16].out_uop.prs2, slots_16.io.out_uop.prs2
connect issue_slots[16].out_uop.prs1, slots_16.io.out_uop.prs1
connect issue_slots[16].out_uop.pdst, slots_16.io.out_uop.pdst
connect issue_slots[16].out_uop.rxq_idx, slots_16.io.out_uop.rxq_idx
connect issue_slots[16].out_uop.stq_idx, slots_16.io.out_uop.stq_idx
connect issue_slots[16].out_uop.ldq_idx, slots_16.io.out_uop.ldq_idx
connect issue_slots[16].out_uop.rob_idx, slots_16.io.out_uop.rob_idx
connect issue_slots[16].out_uop.fp_ctrl.vec, slots_16.io.out_uop.fp_ctrl.vec
connect issue_slots[16].out_uop.fp_ctrl.wflags, slots_16.io.out_uop.fp_ctrl.wflags
connect issue_slots[16].out_uop.fp_ctrl.sqrt, slots_16.io.out_uop.fp_ctrl.sqrt
connect issue_slots[16].out_uop.fp_ctrl.div, slots_16.io.out_uop.fp_ctrl.div
connect issue_slots[16].out_uop.fp_ctrl.fma, slots_16.io.out_uop.fp_ctrl.fma
connect issue_slots[16].out_uop.fp_ctrl.fastpipe, slots_16.io.out_uop.fp_ctrl.fastpipe
connect issue_slots[16].out_uop.fp_ctrl.toint, slots_16.io.out_uop.fp_ctrl.toint
connect issue_slots[16].out_uop.fp_ctrl.fromint, slots_16.io.out_uop.fp_ctrl.fromint
connect issue_slots[16].out_uop.fp_ctrl.typeTagOut, slots_16.io.out_uop.fp_ctrl.typeTagOut
connect issue_slots[16].out_uop.fp_ctrl.typeTagIn, slots_16.io.out_uop.fp_ctrl.typeTagIn
connect issue_slots[16].out_uop.fp_ctrl.swap23, slots_16.io.out_uop.fp_ctrl.swap23
connect issue_slots[16].out_uop.fp_ctrl.swap12, slots_16.io.out_uop.fp_ctrl.swap12
connect issue_slots[16].out_uop.fp_ctrl.ren3, slots_16.io.out_uop.fp_ctrl.ren3
connect issue_slots[16].out_uop.fp_ctrl.ren2, slots_16.io.out_uop.fp_ctrl.ren2
connect issue_slots[16].out_uop.fp_ctrl.ren1, slots_16.io.out_uop.fp_ctrl.ren1
connect issue_slots[16].out_uop.fp_ctrl.wen, slots_16.io.out_uop.fp_ctrl.wen
connect issue_slots[16].out_uop.fp_ctrl.ldst, slots_16.io.out_uop.fp_ctrl.ldst
connect issue_slots[16].out_uop.op2_sel, slots_16.io.out_uop.op2_sel
connect issue_slots[16].out_uop.op1_sel, slots_16.io.out_uop.op1_sel
connect issue_slots[16].out_uop.imm_packed, slots_16.io.out_uop.imm_packed
connect issue_slots[16].out_uop.pimm, slots_16.io.out_uop.pimm
connect issue_slots[16].out_uop.imm_sel, slots_16.io.out_uop.imm_sel
connect issue_slots[16].out_uop.imm_rename, slots_16.io.out_uop.imm_rename
connect issue_slots[16].out_uop.taken, slots_16.io.out_uop.taken
connect issue_slots[16].out_uop.pc_lob, slots_16.io.out_uop.pc_lob
connect issue_slots[16].out_uop.edge_inst, slots_16.io.out_uop.edge_inst
connect issue_slots[16].out_uop.ftq_idx, slots_16.io.out_uop.ftq_idx
connect issue_slots[16].out_uop.is_mov, slots_16.io.out_uop.is_mov
connect issue_slots[16].out_uop.is_rocc, slots_16.io.out_uop.is_rocc
connect issue_slots[16].out_uop.is_sys_pc2epc, slots_16.io.out_uop.is_sys_pc2epc
connect issue_slots[16].out_uop.is_eret, slots_16.io.out_uop.is_eret
connect issue_slots[16].out_uop.is_amo, slots_16.io.out_uop.is_amo
connect issue_slots[16].out_uop.is_sfence, slots_16.io.out_uop.is_sfence
connect issue_slots[16].out_uop.is_fencei, slots_16.io.out_uop.is_fencei
connect issue_slots[16].out_uop.is_fence, slots_16.io.out_uop.is_fence
connect issue_slots[16].out_uop.is_sfb, slots_16.io.out_uop.is_sfb
connect issue_slots[16].out_uop.br_type, slots_16.io.out_uop.br_type
connect issue_slots[16].out_uop.br_tag, slots_16.io.out_uop.br_tag
connect issue_slots[16].out_uop.br_mask, slots_16.io.out_uop.br_mask
connect issue_slots[16].out_uop.dis_col_sel, slots_16.io.out_uop.dis_col_sel
connect issue_slots[16].out_uop.iw_p3_bypass_hint, slots_16.io.out_uop.iw_p3_bypass_hint
connect issue_slots[16].out_uop.iw_p2_bypass_hint, slots_16.io.out_uop.iw_p2_bypass_hint
connect issue_slots[16].out_uop.iw_p1_bypass_hint, slots_16.io.out_uop.iw_p1_bypass_hint
connect issue_slots[16].out_uop.iw_p2_speculative_child, slots_16.io.out_uop.iw_p2_speculative_child
connect issue_slots[16].out_uop.iw_p1_speculative_child, slots_16.io.out_uop.iw_p1_speculative_child
connect issue_slots[16].out_uop.iw_issued_partial_dgen, slots_16.io.out_uop.iw_issued_partial_dgen
connect issue_slots[16].out_uop.iw_issued_partial_agen, slots_16.io.out_uop.iw_issued_partial_agen
connect issue_slots[16].out_uop.iw_issued, slots_16.io.out_uop.iw_issued
connect issue_slots[16].out_uop.fu_code[0], slots_16.io.out_uop.fu_code[0]
connect issue_slots[16].out_uop.fu_code[1], slots_16.io.out_uop.fu_code[1]
connect issue_slots[16].out_uop.fu_code[2], slots_16.io.out_uop.fu_code[2]
connect issue_slots[16].out_uop.fu_code[3], slots_16.io.out_uop.fu_code[3]
connect issue_slots[16].out_uop.fu_code[4], slots_16.io.out_uop.fu_code[4]
connect issue_slots[16].out_uop.fu_code[5], slots_16.io.out_uop.fu_code[5]
connect issue_slots[16].out_uop.fu_code[6], slots_16.io.out_uop.fu_code[6]
connect issue_slots[16].out_uop.fu_code[7], slots_16.io.out_uop.fu_code[7]
connect issue_slots[16].out_uop.fu_code[8], slots_16.io.out_uop.fu_code[8]
connect issue_slots[16].out_uop.fu_code[9], slots_16.io.out_uop.fu_code[9]
connect issue_slots[16].out_uop.iq_type[0], slots_16.io.out_uop.iq_type[0]
connect issue_slots[16].out_uop.iq_type[1], slots_16.io.out_uop.iq_type[1]
connect issue_slots[16].out_uop.iq_type[2], slots_16.io.out_uop.iq_type[2]
connect issue_slots[16].out_uop.iq_type[3], slots_16.io.out_uop.iq_type[3]
connect issue_slots[16].out_uop.debug_pc, slots_16.io.out_uop.debug_pc
connect issue_slots[16].out_uop.is_rvc, slots_16.io.out_uop.is_rvc
connect issue_slots[16].out_uop.debug_inst, slots_16.io.out_uop.debug_inst
connect issue_slots[16].out_uop.inst, slots_16.io.out_uop.inst
connect slots_16.io.in_uop.bits.debug_tsrc, issue_slots[16].in_uop.bits.debug_tsrc
connect slots_16.io.in_uop.bits.debug_fsrc, issue_slots[16].in_uop.bits.debug_fsrc
connect slots_16.io.in_uop.bits.bp_xcpt_if, issue_slots[16].in_uop.bits.bp_xcpt_if
connect slots_16.io.in_uop.bits.bp_debug_if, issue_slots[16].in_uop.bits.bp_debug_if
connect slots_16.io.in_uop.bits.xcpt_ma_if, issue_slots[16].in_uop.bits.xcpt_ma_if
connect slots_16.io.in_uop.bits.xcpt_ae_if, issue_slots[16].in_uop.bits.xcpt_ae_if
connect slots_16.io.in_uop.bits.xcpt_pf_if, issue_slots[16].in_uop.bits.xcpt_pf_if
connect slots_16.io.in_uop.bits.fp_typ, issue_slots[16].in_uop.bits.fp_typ
connect slots_16.io.in_uop.bits.fp_rm, issue_slots[16].in_uop.bits.fp_rm
connect slots_16.io.in_uop.bits.fp_val, issue_slots[16].in_uop.bits.fp_val
connect slots_16.io.in_uop.bits.fcn_op, issue_slots[16].in_uop.bits.fcn_op
connect slots_16.io.in_uop.bits.fcn_dw, issue_slots[16].in_uop.bits.fcn_dw
connect slots_16.io.in_uop.bits.frs3_en, issue_slots[16].in_uop.bits.frs3_en
connect slots_16.io.in_uop.bits.lrs2_rtype, issue_slots[16].in_uop.bits.lrs2_rtype
connect slots_16.io.in_uop.bits.lrs1_rtype, issue_slots[16].in_uop.bits.lrs1_rtype
connect slots_16.io.in_uop.bits.dst_rtype, issue_slots[16].in_uop.bits.dst_rtype
connect slots_16.io.in_uop.bits.lrs3, issue_slots[16].in_uop.bits.lrs3
connect slots_16.io.in_uop.bits.lrs2, issue_slots[16].in_uop.bits.lrs2
connect slots_16.io.in_uop.bits.lrs1, issue_slots[16].in_uop.bits.lrs1
connect slots_16.io.in_uop.bits.ldst, issue_slots[16].in_uop.bits.ldst
connect slots_16.io.in_uop.bits.ldst_is_rs1, issue_slots[16].in_uop.bits.ldst_is_rs1
connect slots_16.io.in_uop.bits.csr_cmd, issue_slots[16].in_uop.bits.csr_cmd
connect slots_16.io.in_uop.bits.flush_on_commit, issue_slots[16].in_uop.bits.flush_on_commit
connect slots_16.io.in_uop.bits.is_unique, issue_slots[16].in_uop.bits.is_unique
connect slots_16.io.in_uop.bits.uses_stq, issue_slots[16].in_uop.bits.uses_stq
connect slots_16.io.in_uop.bits.uses_ldq, issue_slots[16].in_uop.bits.uses_ldq
connect slots_16.io.in_uop.bits.mem_signed, issue_slots[16].in_uop.bits.mem_signed
connect slots_16.io.in_uop.bits.mem_size, issue_slots[16].in_uop.bits.mem_size
connect slots_16.io.in_uop.bits.mem_cmd, issue_slots[16].in_uop.bits.mem_cmd
connect slots_16.io.in_uop.bits.exc_cause, issue_slots[16].in_uop.bits.exc_cause
connect slots_16.io.in_uop.bits.exception, issue_slots[16].in_uop.bits.exception
connect slots_16.io.in_uop.bits.stale_pdst, issue_slots[16].in_uop.bits.stale_pdst
connect slots_16.io.in_uop.bits.ppred_busy, issue_slots[16].in_uop.bits.ppred_busy
connect slots_16.io.in_uop.bits.prs3_busy, issue_slots[16].in_uop.bits.prs3_busy
connect slots_16.io.in_uop.bits.prs2_busy, issue_slots[16].in_uop.bits.prs2_busy
connect slots_16.io.in_uop.bits.prs1_busy, issue_slots[16].in_uop.bits.prs1_busy
connect slots_16.io.in_uop.bits.ppred, issue_slots[16].in_uop.bits.ppred
connect slots_16.io.in_uop.bits.prs3, issue_slots[16].in_uop.bits.prs3
connect slots_16.io.in_uop.bits.prs2, issue_slots[16].in_uop.bits.prs2
connect slots_16.io.in_uop.bits.prs1, issue_slots[16].in_uop.bits.prs1
connect slots_16.io.in_uop.bits.pdst, issue_slots[16].in_uop.bits.pdst
connect slots_16.io.in_uop.bits.rxq_idx, issue_slots[16].in_uop.bits.rxq_idx
connect slots_16.io.in_uop.bits.stq_idx, issue_slots[16].in_uop.bits.stq_idx
connect slots_16.io.in_uop.bits.ldq_idx, issue_slots[16].in_uop.bits.ldq_idx
connect slots_16.io.in_uop.bits.rob_idx, issue_slots[16].in_uop.bits.rob_idx
connect slots_16.io.in_uop.bits.fp_ctrl.vec, issue_slots[16].in_uop.bits.fp_ctrl.vec
connect slots_16.io.in_uop.bits.fp_ctrl.wflags, issue_slots[16].in_uop.bits.fp_ctrl.wflags
connect slots_16.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[16].in_uop.bits.fp_ctrl.sqrt
connect slots_16.io.in_uop.bits.fp_ctrl.div, issue_slots[16].in_uop.bits.fp_ctrl.div
connect slots_16.io.in_uop.bits.fp_ctrl.fma, issue_slots[16].in_uop.bits.fp_ctrl.fma
connect slots_16.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[16].in_uop.bits.fp_ctrl.fastpipe
connect slots_16.io.in_uop.bits.fp_ctrl.toint, issue_slots[16].in_uop.bits.fp_ctrl.toint
connect slots_16.io.in_uop.bits.fp_ctrl.fromint, issue_slots[16].in_uop.bits.fp_ctrl.fromint
connect slots_16.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[16].in_uop.bits.fp_ctrl.typeTagOut
connect slots_16.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[16].in_uop.bits.fp_ctrl.typeTagIn
connect slots_16.io.in_uop.bits.fp_ctrl.swap23, issue_slots[16].in_uop.bits.fp_ctrl.swap23
connect slots_16.io.in_uop.bits.fp_ctrl.swap12, issue_slots[16].in_uop.bits.fp_ctrl.swap12
connect slots_16.io.in_uop.bits.fp_ctrl.ren3, issue_slots[16].in_uop.bits.fp_ctrl.ren3
connect slots_16.io.in_uop.bits.fp_ctrl.ren2, issue_slots[16].in_uop.bits.fp_ctrl.ren2
connect slots_16.io.in_uop.bits.fp_ctrl.ren1, issue_slots[16].in_uop.bits.fp_ctrl.ren1
connect slots_16.io.in_uop.bits.fp_ctrl.wen, issue_slots[16].in_uop.bits.fp_ctrl.wen
connect slots_16.io.in_uop.bits.fp_ctrl.ldst, issue_slots[16].in_uop.bits.fp_ctrl.ldst
connect slots_16.io.in_uop.bits.op2_sel, issue_slots[16].in_uop.bits.op2_sel
connect slots_16.io.in_uop.bits.op1_sel, issue_slots[16].in_uop.bits.op1_sel
connect slots_16.io.in_uop.bits.imm_packed, issue_slots[16].in_uop.bits.imm_packed
connect slots_16.io.in_uop.bits.pimm, issue_slots[16].in_uop.bits.pimm
connect slots_16.io.in_uop.bits.imm_sel, issue_slots[16].in_uop.bits.imm_sel
connect slots_16.io.in_uop.bits.imm_rename, issue_slots[16].in_uop.bits.imm_rename
connect slots_16.io.in_uop.bits.taken, issue_slots[16].in_uop.bits.taken
connect slots_16.io.in_uop.bits.pc_lob, issue_slots[16].in_uop.bits.pc_lob
connect slots_16.io.in_uop.bits.edge_inst, issue_slots[16].in_uop.bits.edge_inst
connect slots_16.io.in_uop.bits.ftq_idx, issue_slots[16].in_uop.bits.ftq_idx
connect slots_16.io.in_uop.bits.is_mov, issue_slots[16].in_uop.bits.is_mov
connect slots_16.io.in_uop.bits.is_rocc, issue_slots[16].in_uop.bits.is_rocc
connect slots_16.io.in_uop.bits.is_sys_pc2epc, issue_slots[16].in_uop.bits.is_sys_pc2epc
connect slots_16.io.in_uop.bits.is_eret, issue_slots[16].in_uop.bits.is_eret
connect slots_16.io.in_uop.bits.is_amo, issue_slots[16].in_uop.bits.is_amo
connect slots_16.io.in_uop.bits.is_sfence, issue_slots[16].in_uop.bits.is_sfence
connect slots_16.io.in_uop.bits.is_fencei, issue_slots[16].in_uop.bits.is_fencei
connect slots_16.io.in_uop.bits.is_fence, issue_slots[16].in_uop.bits.is_fence
connect slots_16.io.in_uop.bits.is_sfb, issue_slots[16].in_uop.bits.is_sfb
connect slots_16.io.in_uop.bits.br_type, issue_slots[16].in_uop.bits.br_type
connect slots_16.io.in_uop.bits.br_tag, issue_slots[16].in_uop.bits.br_tag
connect slots_16.io.in_uop.bits.br_mask, issue_slots[16].in_uop.bits.br_mask
connect slots_16.io.in_uop.bits.dis_col_sel, issue_slots[16].in_uop.bits.dis_col_sel
connect slots_16.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[16].in_uop.bits.iw_p3_bypass_hint
connect slots_16.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[16].in_uop.bits.iw_p2_bypass_hint
connect slots_16.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[16].in_uop.bits.iw_p1_bypass_hint
connect slots_16.io.in_uop.bits.iw_p2_speculative_child, issue_slots[16].in_uop.bits.iw_p2_speculative_child
connect slots_16.io.in_uop.bits.iw_p1_speculative_child, issue_slots[16].in_uop.bits.iw_p1_speculative_child
connect slots_16.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[16].in_uop.bits.iw_issued_partial_dgen
connect slots_16.io.in_uop.bits.iw_issued_partial_agen, issue_slots[16].in_uop.bits.iw_issued_partial_agen
connect slots_16.io.in_uop.bits.iw_issued, issue_slots[16].in_uop.bits.iw_issued
connect slots_16.io.in_uop.bits.fu_code[0], issue_slots[16].in_uop.bits.fu_code[0]
connect slots_16.io.in_uop.bits.fu_code[1], issue_slots[16].in_uop.bits.fu_code[1]
connect slots_16.io.in_uop.bits.fu_code[2], issue_slots[16].in_uop.bits.fu_code[2]
connect slots_16.io.in_uop.bits.fu_code[3], issue_slots[16].in_uop.bits.fu_code[3]
connect slots_16.io.in_uop.bits.fu_code[4], issue_slots[16].in_uop.bits.fu_code[4]
connect slots_16.io.in_uop.bits.fu_code[5], issue_slots[16].in_uop.bits.fu_code[5]
connect slots_16.io.in_uop.bits.fu_code[6], issue_slots[16].in_uop.bits.fu_code[6]
connect slots_16.io.in_uop.bits.fu_code[7], issue_slots[16].in_uop.bits.fu_code[7]
connect slots_16.io.in_uop.bits.fu_code[8], issue_slots[16].in_uop.bits.fu_code[8]
connect slots_16.io.in_uop.bits.fu_code[9], issue_slots[16].in_uop.bits.fu_code[9]
connect slots_16.io.in_uop.bits.iq_type[0], issue_slots[16].in_uop.bits.iq_type[0]
connect slots_16.io.in_uop.bits.iq_type[1], issue_slots[16].in_uop.bits.iq_type[1]
connect slots_16.io.in_uop.bits.iq_type[2], issue_slots[16].in_uop.bits.iq_type[2]
connect slots_16.io.in_uop.bits.iq_type[3], issue_slots[16].in_uop.bits.iq_type[3]
connect slots_16.io.in_uop.bits.debug_pc, issue_slots[16].in_uop.bits.debug_pc
connect slots_16.io.in_uop.bits.is_rvc, issue_slots[16].in_uop.bits.is_rvc
connect slots_16.io.in_uop.bits.debug_inst, issue_slots[16].in_uop.bits.debug_inst
connect slots_16.io.in_uop.bits.inst, issue_slots[16].in_uop.bits.inst
connect slots_16.io.in_uop.valid, issue_slots[16].in_uop.valid
connect issue_slots[16].iss_uop.debug_tsrc, slots_16.io.iss_uop.debug_tsrc
connect issue_slots[16].iss_uop.debug_fsrc, slots_16.io.iss_uop.debug_fsrc
connect issue_slots[16].iss_uop.bp_xcpt_if, slots_16.io.iss_uop.bp_xcpt_if
connect issue_slots[16].iss_uop.bp_debug_if, slots_16.io.iss_uop.bp_debug_if
connect issue_slots[16].iss_uop.xcpt_ma_if, slots_16.io.iss_uop.xcpt_ma_if
connect issue_slots[16].iss_uop.xcpt_ae_if, slots_16.io.iss_uop.xcpt_ae_if
connect issue_slots[16].iss_uop.xcpt_pf_if, slots_16.io.iss_uop.xcpt_pf_if
connect issue_slots[16].iss_uop.fp_typ, slots_16.io.iss_uop.fp_typ
connect issue_slots[16].iss_uop.fp_rm, slots_16.io.iss_uop.fp_rm
connect issue_slots[16].iss_uop.fp_val, slots_16.io.iss_uop.fp_val
connect issue_slots[16].iss_uop.fcn_op, slots_16.io.iss_uop.fcn_op
connect issue_slots[16].iss_uop.fcn_dw, slots_16.io.iss_uop.fcn_dw
connect issue_slots[16].iss_uop.frs3_en, slots_16.io.iss_uop.frs3_en
connect issue_slots[16].iss_uop.lrs2_rtype, slots_16.io.iss_uop.lrs2_rtype
connect issue_slots[16].iss_uop.lrs1_rtype, slots_16.io.iss_uop.lrs1_rtype
connect issue_slots[16].iss_uop.dst_rtype, slots_16.io.iss_uop.dst_rtype
connect issue_slots[16].iss_uop.lrs3, slots_16.io.iss_uop.lrs3
connect issue_slots[16].iss_uop.lrs2, slots_16.io.iss_uop.lrs2
connect issue_slots[16].iss_uop.lrs1, slots_16.io.iss_uop.lrs1
connect issue_slots[16].iss_uop.ldst, slots_16.io.iss_uop.ldst
connect issue_slots[16].iss_uop.ldst_is_rs1, slots_16.io.iss_uop.ldst_is_rs1
connect issue_slots[16].iss_uop.csr_cmd, slots_16.io.iss_uop.csr_cmd
connect issue_slots[16].iss_uop.flush_on_commit, slots_16.io.iss_uop.flush_on_commit
connect issue_slots[16].iss_uop.is_unique, slots_16.io.iss_uop.is_unique
connect issue_slots[16].iss_uop.uses_stq, slots_16.io.iss_uop.uses_stq
connect issue_slots[16].iss_uop.uses_ldq, slots_16.io.iss_uop.uses_ldq
connect issue_slots[16].iss_uop.mem_signed, slots_16.io.iss_uop.mem_signed
connect issue_slots[16].iss_uop.mem_size, slots_16.io.iss_uop.mem_size
connect issue_slots[16].iss_uop.mem_cmd, slots_16.io.iss_uop.mem_cmd
connect issue_slots[16].iss_uop.exc_cause, slots_16.io.iss_uop.exc_cause
connect issue_slots[16].iss_uop.exception, slots_16.io.iss_uop.exception
connect issue_slots[16].iss_uop.stale_pdst, slots_16.io.iss_uop.stale_pdst
connect issue_slots[16].iss_uop.ppred_busy, slots_16.io.iss_uop.ppred_busy
connect issue_slots[16].iss_uop.prs3_busy, slots_16.io.iss_uop.prs3_busy
connect issue_slots[16].iss_uop.prs2_busy, slots_16.io.iss_uop.prs2_busy
connect issue_slots[16].iss_uop.prs1_busy, slots_16.io.iss_uop.prs1_busy
connect issue_slots[16].iss_uop.ppred, slots_16.io.iss_uop.ppred
connect issue_slots[16].iss_uop.prs3, slots_16.io.iss_uop.prs3
connect issue_slots[16].iss_uop.prs2, slots_16.io.iss_uop.prs2
connect issue_slots[16].iss_uop.prs1, slots_16.io.iss_uop.prs1
connect issue_slots[16].iss_uop.pdst, slots_16.io.iss_uop.pdst
connect issue_slots[16].iss_uop.rxq_idx, slots_16.io.iss_uop.rxq_idx
connect issue_slots[16].iss_uop.stq_idx, slots_16.io.iss_uop.stq_idx
connect issue_slots[16].iss_uop.ldq_idx, slots_16.io.iss_uop.ldq_idx
connect issue_slots[16].iss_uop.rob_idx, slots_16.io.iss_uop.rob_idx
connect issue_slots[16].iss_uop.fp_ctrl.vec, slots_16.io.iss_uop.fp_ctrl.vec
connect issue_slots[16].iss_uop.fp_ctrl.wflags, slots_16.io.iss_uop.fp_ctrl.wflags
connect issue_slots[16].iss_uop.fp_ctrl.sqrt, slots_16.io.iss_uop.fp_ctrl.sqrt
connect issue_slots[16].iss_uop.fp_ctrl.div, slots_16.io.iss_uop.fp_ctrl.div
connect issue_slots[16].iss_uop.fp_ctrl.fma, slots_16.io.iss_uop.fp_ctrl.fma
connect issue_slots[16].iss_uop.fp_ctrl.fastpipe, slots_16.io.iss_uop.fp_ctrl.fastpipe
connect issue_slots[16].iss_uop.fp_ctrl.toint, slots_16.io.iss_uop.fp_ctrl.toint
connect issue_slots[16].iss_uop.fp_ctrl.fromint, slots_16.io.iss_uop.fp_ctrl.fromint
connect issue_slots[16].iss_uop.fp_ctrl.typeTagOut, slots_16.io.iss_uop.fp_ctrl.typeTagOut
connect issue_slots[16].iss_uop.fp_ctrl.typeTagIn, slots_16.io.iss_uop.fp_ctrl.typeTagIn
connect issue_slots[16].iss_uop.fp_ctrl.swap23, slots_16.io.iss_uop.fp_ctrl.swap23
connect issue_slots[16].iss_uop.fp_ctrl.swap12, slots_16.io.iss_uop.fp_ctrl.swap12
connect issue_slots[16].iss_uop.fp_ctrl.ren3, slots_16.io.iss_uop.fp_ctrl.ren3
connect issue_slots[16].iss_uop.fp_ctrl.ren2, slots_16.io.iss_uop.fp_ctrl.ren2
connect issue_slots[16].iss_uop.fp_ctrl.ren1, slots_16.io.iss_uop.fp_ctrl.ren1
connect issue_slots[16].iss_uop.fp_ctrl.wen, slots_16.io.iss_uop.fp_ctrl.wen
connect issue_slots[16].iss_uop.fp_ctrl.ldst, slots_16.io.iss_uop.fp_ctrl.ldst
connect issue_slots[16].iss_uop.op2_sel, slots_16.io.iss_uop.op2_sel
connect issue_slots[16].iss_uop.op1_sel, slots_16.io.iss_uop.op1_sel
connect issue_slots[16].iss_uop.imm_packed, slots_16.io.iss_uop.imm_packed
connect issue_slots[16].iss_uop.pimm, slots_16.io.iss_uop.pimm
connect issue_slots[16].iss_uop.imm_sel, slots_16.io.iss_uop.imm_sel
connect issue_slots[16].iss_uop.imm_rename, slots_16.io.iss_uop.imm_rename
connect issue_slots[16].iss_uop.taken, slots_16.io.iss_uop.taken
connect issue_slots[16].iss_uop.pc_lob, slots_16.io.iss_uop.pc_lob
connect issue_slots[16].iss_uop.edge_inst, slots_16.io.iss_uop.edge_inst
connect issue_slots[16].iss_uop.ftq_idx, slots_16.io.iss_uop.ftq_idx
connect issue_slots[16].iss_uop.is_mov, slots_16.io.iss_uop.is_mov
connect issue_slots[16].iss_uop.is_rocc, slots_16.io.iss_uop.is_rocc
connect issue_slots[16].iss_uop.is_sys_pc2epc, slots_16.io.iss_uop.is_sys_pc2epc
connect issue_slots[16].iss_uop.is_eret, slots_16.io.iss_uop.is_eret
connect issue_slots[16].iss_uop.is_amo, slots_16.io.iss_uop.is_amo
connect issue_slots[16].iss_uop.is_sfence, slots_16.io.iss_uop.is_sfence
connect issue_slots[16].iss_uop.is_fencei, slots_16.io.iss_uop.is_fencei
connect issue_slots[16].iss_uop.is_fence, slots_16.io.iss_uop.is_fence
connect issue_slots[16].iss_uop.is_sfb, slots_16.io.iss_uop.is_sfb
connect issue_slots[16].iss_uop.br_type, slots_16.io.iss_uop.br_type
connect issue_slots[16].iss_uop.br_tag, slots_16.io.iss_uop.br_tag
connect issue_slots[16].iss_uop.br_mask, slots_16.io.iss_uop.br_mask
connect issue_slots[16].iss_uop.dis_col_sel, slots_16.io.iss_uop.dis_col_sel
connect issue_slots[16].iss_uop.iw_p3_bypass_hint, slots_16.io.iss_uop.iw_p3_bypass_hint
connect issue_slots[16].iss_uop.iw_p2_bypass_hint, slots_16.io.iss_uop.iw_p2_bypass_hint
connect issue_slots[16].iss_uop.iw_p1_bypass_hint, slots_16.io.iss_uop.iw_p1_bypass_hint
connect issue_slots[16].iss_uop.iw_p2_speculative_child, slots_16.io.iss_uop.iw_p2_speculative_child
connect issue_slots[16].iss_uop.iw_p1_speculative_child, slots_16.io.iss_uop.iw_p1_speculative_child
connect issue_slots[16].iss_uop.iw_issued_partial_dgen, slots_16.io.iss_uop.iw_issued_partial_dgen
connect issue_slots[16].iss_uop.iw_issued_partial_agen, slots_16.io.iss_uop.iw_issued_partial_agen
connect issue_slots[16].iss_uop.iw_issued, slots_16.io.iss_uop.iw_issued
connect issue_slots[16].iss_uop.fu_code[0], slots_16.io.iss_uop.fu_code[0]
connect issue_slots[16].iss_uop.fu_code[1], slots_16.io.iss_uop.fu_code[1]
connect issue_slots[16].iss_uop.fu_code[2], slots_16.io.iss_uop.fu_code[2]
connect issue_slots[16].iss_uop.fu_code[3], slots_16.io.iss_uop.fu_code[3]
connect issue_slots[16].iss_uop.fu_code[4], slots_16.io.iss_uop.fu_code[4]
connect issue_slots[16].iss_uop.fu_code[5], slots_16.io.iss_uop.fu_code[5]
connect issue_slots[16].iss_uop.fu_code[6], slots_16.io.iss_uop.fu_code[6]
connect issue_slots[16].iss_uop.fu_code[7], slots_16.io.iss_uop.fu_code[7]
connect issue_slots[16].iss_uop.fu_code[8], slots_16.io.iss_uop.fu_code[8]
connect issue_slots[16].iss_uop.fu_code[9], slots_16.io.iss_uop.fu_code[9]
connect issue_slots[16].iss_uop.iq_type[0], slots_16.io.iss_uop.iq_type[0]
connect issue_slots[16].iss_uop.iq_type[1], slots_16.io.iss_uop.iq_type[1]
connect issue_slots[16].iss_uop.iq_type[2], slots_16.io.iss_uop.iq_type[2]
connect issue_slots[16].iss_uop.iq_type[3], slots_16.io.iss_uop.iq_type[3]
connect issue_slots[16].iss_uop.debug_pc, slots_16.io.iss_uop.debug_pc
connect issue_slots[16].iss_uop.is_rvc, slots_16.io.iss_uop.is_rvc
connect issue_slots[16].iss_uop.debug_inst, slots_16.io.iss_uop.debug_inst
connect issue_slots[16].iss_uop.inst, slots_16.io.iss_uop.inst
connect slots_16.io.grant, issue_slots[16].grant
connect issue_slots[16].request, slots_16.io.request
connect issue_slots[16].will_be_valid, slots_16.io.will_be_valid
connect issue_slots[16].valid, slots_16.io.valid
connect slots_17.io.child_rebusys, issue_slots[17].child_rebusys
connect slots_17.io.pred_wakeup_port.bits, issue_slots[17].pred_wakeup_port.bits
connect slots_17.io.pred_wakeup_port.valid, issue_slots[17].pred_wakeup_port.valid
connect slots_17.io.wakeup_ports[0].bits.rebusy, issue_slots[17].wakeup_ports[0].bits.rebusy
connect slots_17.io.wakeup_ports[0].bits.speculative_mask, issue_slots[17].wakeup_ports[0].bits.speculative_mask
connect slots_17.io.wakeup_ports[0].bits.bypassable, issue_slots[17].wakeup_ports[0].bits.bypassable
connect slots_17.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[17].wakeup_ports[0].bits.uop.debug_tsrc
connect slots_17.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[17].wakeup_ports[0].bits.uop.debug_fsrc
connect slots_17.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[17].wakeup_ports[0].bits.uop.bp_xcpt_if
connect slots_17.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[17].wakeup_ports[0].bits.uop.bp_debug_if
connect slots_17.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[17].wakeup_ports[0].bits.uop.xcpt_ma_if
connect slots_17.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[17].wakeup_ports[0].bits.uop.xcpt_ae_if
connect slots_17.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[17].wakeup_ports[0].bits.uop.xcpt_pf_if
connect slots_17.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[17].wakeup_ports[0].bits.uop.fp_typ
connect slots_17.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[17].wakeup_ports[0].bits.uop.fp_rm
connect slots_17.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[17].wakeup_ports[0].bits.uop.fp_val
connect slots_17.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[17].wakeup_ports[0].bits.uop.fcn_op
connect slots_17.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[17].wakeup_ports[0].bits.uop.fcn_dw
connect slots_17.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[17].wakeup_ports[0].bits.uop.frs3_en
connect slots_17.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[17].wakeup_ports[0].bits.uop.lrs2_rtype
connect slots_17.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[17].wakeup_ports[0].bits.uop.lrs1_rtype
connect slots_17.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[17].wakeup_ports[0].bits.uop.dst_rtype
connect slots_17.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[17].wakeup_ports[0].bits.uop.lrs3
connect slots_17.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[17].wakeup_ports[0].bits.uop.lrs2
connect slots_17.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[17].wakeup_ports[0].bits.uop.lrs1
connect slots_17.io.wakeup_ports[0].bits.uop.ldst, issue_slots[17].wakeup_ports[0].bits.uop.ldst
connect slots_17.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[17].wakeup_ports[0].bits.uop.ldst_is_rs1
connect slots_17.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[17].wakeup_ports[0].bits.uop.csr_cmd
connect slots_17.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[17].wakeup_ports[0].bits.uop.flush_on_commit
connect slots_17.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[17].wakeup_ports[0].bits.uop.is_unique
connect slots_17.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[17].wakeup_ports[0].bits.uop.uses_stq
connect slots_17.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[17].wakeup_ports[0].bits.uop.uses_ldq
connect slots_17.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[17].wakeup_ports[0].bits.uop.mem_signed
connect slots_17.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[17].wakeup_ports[0].bits.uop.mem_size
connect slots_17.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[17].wakeup_ports[0].bits.uop.mem_cmd
connect slots_17.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[17].wakeup_ports[0].bits.uop.exc_cause
connect slots_17.io.wakeup_ports[0].bits.uop.exception, issue_slots[17].wakeup_ports[0].bits.uop.exception
connect slots_17.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[17].wakeup_ports[0].bits.uop.stale_pdst
connect slots_17.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[17].wakeup_ports[0].bits.uop.ppred_busy
connect slots_17.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[17].wakeup_ports[0].bits.uop.prs3_busy
connect slots_17.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[17].wakeup_ports[0].bits.uop.prs2_busy
connect slots_17.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[17].wakeup_ports[0].bits.uop.prs1_busy
connect slots_17.io.wakeup_ports[0].bits.uop.ppred, issue_slots[17].wakeup_ports[0].bits.uop.ppred
connect slots_17.io.wakeup_ports[0].bits.uop.prs3, issue_slots[17].wakeup_ports[0].bits.uop.prs3
connect slots_17.io.wakeup_ports[0].bits.uop.prs2, issue_slots[17].wakeup_ports[0].bits.uop.prs2
connect slots_17.io.wakeup_ports[0].bits.uop.prs1, issue_slots[17].wakeup_ports[0].bits.uop.prs1
connect slots_17.io.wakeup_ports[0].bits.uop.pdst, issue_slots[17].wakeup_ports[0].bits.uop.pdst
connect slots_17.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[17].wakeup_ports[0].bits.uop.rxq_idx
connect slots_17.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[17].wakeup_ports[0].bits.uop.stq_idx
connect slots_17.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[17].wakeup_ports[0].bits.uop.ldq_idx
connect slots_17.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[17].wakeup_ports[0].bits.uop.rob_idx
connect slots_17.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.vec
connect slots_17.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.wflags
connect slots_17.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.sqrt
connect slots_17.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.div
connect slots_17.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.fma
connect slots_17.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe
connect slots_17.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.toint
connect slots_17.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.fromint
connect slots_17.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut
connect slots_17.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn
connect slots_17.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.swap23
connect slots_17.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.swap12
connect slots_17.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.ren3
connect slots_17.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.ren2
connect slots_17.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.ren1
connect slots_17.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.wen
connect slots_17.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.ldst
connect slots_17.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[17].wakeup_ports[0].bits.uop.op2_sel
connect slots_17.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[17].wakeup_ports[0].bits.uop.op1_sel
connect slots_17.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[17].wakeup_ports[0].bits.uop.imm_packed
connect slots_17.io.wakeup_ports[0].bits.uop.pimm, issue_slots[17].wakeup_ports[0].bits.uop.pimm
connect slots_17.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[17].wakeup_ports[0].bits.uop.imm_sel
connect slots_17.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[17].wakeup_ports[0].bits.uop.imm_rename
connect slots_17.io.wakeup_ports[0].bits.uop.taken, issue_slots[17].wakeup_ports[0].bits.uop.taken
connect slots_17.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[17].wakeup_ports[0].bits.uop.pc_lob
connect slots_17.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[17].wakeup_ports[0].bits.uop.edge_inst
connect slots_17.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[17].wakeup_ports[0].bits.uop.ftq_idx
connect slots_17.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[17].wakeup_ports[0].bits.uop.is_mov
connect slots_17.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[17].wakeup_ports[0].bits.uop.is_rocc
connect slots_17.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[17].wakeup_ports[0].bits.uop.is_sys_pc2epc
connect slots_17.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[17].wakeup_ports[0].bits.uop.is_eret
connect slots_17.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[17].wakeup_ports[0].bits.uop.is_amo
connect slots_17.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[17].wakeup_ports[0].bits.uop.is_sfence
connect slots_17.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[17].wakeup_ports[0].bits.uop.is_fencei
connect slots_17.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[17].wakeup_ports[0].bits.uop.is_fence
connect slots_17.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[17].wakeup_ports[0].bits.uop.is_sfb
connect slots_17.io.wakeup_ports[0].bits.uop.br_type, issue_slots[17].wakeup_ports[0].bits.uop.br_type
connect slots_17.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[17].wakeup_ports[0].bits.uop.br_tag
connect slots_17.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[17].wakeup_ports[0].bits.uop.br_mask
connect slots_17.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[17].wakeup_ports[0].bits.uop.dis_col_sel
connect slots_17.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[17].wakeup_ports[0].bits.uop.iw_p3_bypass_hint
connect slots_17.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[17].wakeup_ports[0].bits.uop.iw_p2_bypass_hint
connect slots_17.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[17].wakeup_ports[0].bits.uop.iw_p1_bypass_hint
connect slots_17.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[17].wakeup_ports[0].bits.uop.iw_p2_speculative_child
connect slots_17.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[17].wakeup_ports[0].bits.uop.iw_p1_speculative_child
connect slots_17.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[17].wakeup_ports[0].bits.uop.iw_issued_partial_dgen
connect slots_17.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[17].wakeup_ports[0].bits.uop.iw_issued_partial_agen
connect slots_17.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[17].wakeup_ports[0].bits.uop.iw_issued
connect slots_17.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[17].wakeup_ports[0].bits.uop.fu_code[0]
connect slots_17.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[17].wakeup_ports[0].bits.uop.fu_code[1]
connect slots_17.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[17].wakeup_ports[0].bits.uop.fu_code[2]
connect slots_17.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[17].wakeup_ports[0].bits.uop.fu_code[3]
connect slots_17.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[17].wakeup_ports[0].bits.uop.fu_code[4]
connect slots_17.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[17].wakeup_ports[0].bits.uop.fu_code[5]
connect slots_17.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[17].wakeup_ports[0].bits.uop.fu_code[6]
connect slots_17.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[17].wakeup_ports[0].bits.uop.fu_code[7]
connect slots_17.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[17].wakeup_ports[0].bits.uop.fu_code[8]
connect slots_17.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[17].wakeup_ports[0].bits.uop.fu_code[9]
connect slots_17.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[17].wakeup_ports[0].bits.uop.iq_type[0]
connect slots_17.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[17].wakeup_ports[0].bits.uop.iq_type[1]
connect slots_17.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[17].wakeup_ports[0].bits.uop.iq_type[2]
connect slots_17.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[17].wakeup_ports[0].bits.uop.iq_type[3]
connect slots_17.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[17].wakeup_ports[0].bits.uop.debug_pc
connect slots_17.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[17].wakeup_ports[0].bits.uop.is_rvc
connect slots_17.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[17].wakeup_ports[0].bits.uop.debug_inst
connect slots_17.io.wakeup_ports[0].bits.uop.inst, issue_slots[17].wakeup_ports[0].bits.uop.inst
connect slots_17.io.wakeup_ports[0].valid, issue_slots[17].wakeup_ports[0].valid
connect slots_17.io.wakeup_ports[1].bits.rebusy, issue_slots[17].wakeup_ports[1].bits.rebusy
connect slots_17.io.wakeup_ports[1].bits.speculative_mask, issue_slots[17].wakeup_ports[1].bits.speculative_mask
connect slots_17.io.wakeup_ports[1].bits.bypassable, issue_slots[17].wakeup_ports[1].bits.bypassable
connect slots_17.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[17].wakeup_ports[1].bits.uop.debug_tsrc
connect slots_17.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[17].wakeup_ports[1].bits.uop.debug_fsrc
connect slots_17.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[17].wakeup_ports[1].bits.uop.bp_xcpt_if
connect slots_17.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[17].wakeup_ports[1].bits.uop.bp_debug_if
connect slots_17.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[17].wakeup_ports[1].bits.uop.xcpt_ma_if
connect slots_17.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[17].wakeup_ports[1].bits.uop.xcpt_ae_if
connect slots_17.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[17].wakeup_ports[1].bits.uop.xcpt_pf_if
connect slots_17.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[17].wakeup_ports[1].bits.uop.fp_typ
connect slots_17.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[17].wakeup_ports[1].bits.uop.fp_rm
connect slots_17.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[17].wakeup_ports[1].bits.uop.fp_val
connect slots_17.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[17].wakeup_ports[1].bits.uop.fcn_op
connect slots_17.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[17].wakeup_ports[1].bits.uop.fcn_dw
connect slots_17.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[17].wakeup_ports[1].bits.uop.frs3_en
connect slots_17.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[17].wakeup_ports[1].bits.uop.lrs2_rtype
connect slots_17.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[17].wakeup_ports[1].bits.uop.lrs1_rtype
connect slots_17.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[17].wakeup_ports[1].bits.uop.dst_rtype
connect slots_17.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[17].wakeup_ports[1].bits.uop.lrs3
connect slots_17.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[17].wakeup_ports[1].bits.uop.lrs2
connect slots_17.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[17].wakeup_ports[1].bits.uop.lrs1
connect slots_17.io.wakeup_ports[1].bits.uop.ldst, issue_slots[17].wakeup_ports[1].bits.uop.ldst
connect slots_17.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[17].wakeup_ports[1].bits.uop.ldst_is_rs1
connect slots_17.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[17].wakeup_ports[1].bits.uop.csr_cmd
connect slots_17.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[17].wakeup_ports[1].bits.uop.flush_on_commit
connect slots_17.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[17].wakeup_ports[1].bits.uop.is_unique
connect slots_17.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[17].wakeup_ports[1].bits.uop.uses_stq
connect slots_17.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[17].wakeup_ports[1].bits.uop.uses_ldq
connect slots_17.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[17].wakeup_ports[1].bits.uop.mem_signed
connect slots_17.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[17].wakeup_ports[1].bits.uop.mem_size
connect slots_17.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[17].wakeup_ports[1].bits.uop.mem_cmd
connect slots_17.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[17].wakeup_ports[1].bits.uop.exc_cause
connect slots_17.io.wakeup_ports[1].bits.uop.exception, issue_slots[17].wakeup_ports[1].bits.uop.exception
connect slots_17.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[17].wakeup_ports[1].bits.uop.stale_pdst
connect slots_17.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[17].wakeup_ports[1].bits.uop.ppred_busy
connect slots_17.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[17].wakeup_ports[1].bits.uop.prs3_busy
connect slots_17.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[17].wakeup_ports[1].bits.uop.prs2_busy
connect slots_17.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[17].wakeup_ports[1].bits.uop.prs1_busy
connect slots_17.io.wakeup_ports[1].bits.uop.ppred, issue_slots[17].wakeup_ports[1].bits.uop.ppred
connect slots_17.io.wakeup_ports[1].bits.uop.prs3, issue_slots[17].wakeup_ports[1].bits.uop.prs3
connect slots_17.io.wakeup_ports[1].bits.uop.prs2, issue_slots[17].wakeup_ports[1].bits.uop.prs2
connect slots_17.io.wakeup_ports[1].bits.uop.prs1, issue_slots[17].wakeup_ports[1].bits.uop.prs1
connect slots_17.io.wakeup_ports[1].bits.uop.pdst, issue_slots[17].wakeup_ports[1].bits.uop.pdst
connect slots_17.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[17].wakeup_ports[1].bits.uop.rxq_idx
connect slots_17.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[17].wakeup_ports[1].bits.uop.stq_idx
connect slots_17.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[17].wakeup_ports[1].bits.uop.ldq_idx
connect slots_17.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[17].wakeup_ports[1].bits.uop.rob_idx
connect slots_17.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.vec
connect slots_17.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.wflags
connect slots_17.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.sqrt
connect slots_17.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.div
connect slots_17.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.fma
connect slots_17.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe
connect slots_17.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.toint
connect slots_17.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.fromint
connect slots_17.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut
connect slots_17.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn
connect slots_17.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.swap23
connect slots_17.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.swap12
connect slots_17.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.ren3
connect slots_17.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.ren2
connect slots_17.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.ren1
connect slots_17.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.wen
connect slots_17.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.ldst
connect slots_17.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[17].wakeup_ports[1].bits.uop.op2_sel
connect slots_17.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[17].wakeup_ports[1].bits.uop.op1_sel
connect slots_17.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[17].wakeup_ports[1].bits.uop.imm_packed
connect slots_17.io.wakeup_ports[1].bits.uop.pimm, issue_slots[17].wakeup_ports[1].bits.uop.pimm
connect slots_17.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[17].wakeup_ports[1].bits.uop.imm_sel
connect slots_17.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[17].wakeup_ports[1].bits.uop.imm_rename
connect slots_17.io.wakeup_ports[1].bits.uop.taken, issue_slots[17].wakeup_ports[1].bits.uop.taken
connect slots_17.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[17].wakeup_ports[1].bits.uop.pc_lob
connect slots_17.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[17].wakeup_ports[1].bits.uop.edge_inst
connect slots_17.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[17].wakeup_ports[1].bits.uop.ftq_idx
connect slots_17.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[17].wakeup_ports[1].bits.uop.is_mov
connect slots_17.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[17].wakeup_ports[1].bits.uop.is_rocc
connect slots_17.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[17].wakeup_ports[1].bits.uop.is_sys_pc2epc
connect slots_17.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[17].wakeup_ports[1].bits.uop.is_eret
connect slots_17.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[17].wakeup_ports[1].bits.uop.is_amo
connect slots_17.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[17].wakeup_ports[1].bits.uop.is_sfence
connect slots_17.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[17].wakeup_ports[1].bits.uop.is_fencei
connect slots_17.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[17].wakeup_ports[1].bits.uop.is_fence
connect slots_17.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[17].wakeup_ports[1].bits.uop.is_sfb
connect slots_17.io.wakeup_ports[1].bits.uop.br_type, issue_slots[17].wakeup_ports[1].bits.uop.br_type
connect slots_17.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[17].wakeup_ports[1].bits.uop.br_tag
connect slots_17.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[17].wakeup_ports[1].bits.uop.br_mask
connect slots_17.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[17].wakeup_ports[1].bits.uop.dis_col_sel
connect slots_17.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[17].wakeup_ports[1].bits.uop.iw_p3_bypass_hint
connect slots_17.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[17].wakeup_ports[1].bits.uop.iw_p2_bypass_hint
connect slots_17.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[17].wakeup_ports[1].bits.uop.iw_p1_bypass_hint
connect slots_17.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[17].wakeup_ports[1].bits.uop.iw_p2_speculative_child
connect slots_17.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[17].wakeup_ports[1].bits.uop.iw_p1_speculative_child
connect slots_17.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[17].wakeup_ports[1].bits.uop.iw_issued_partial_dgen
connect slots_17.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[17].wakeup_ports[1].bits.uop.iw_issued_partial_agen
connect slots_17.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[17].wakeup_ports[1].bits.uop.iw_issued
connect slots_17.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[17].wakeup_ports[1].bits.uop.fu_code[0]
connect slots_17.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[17].wakeup_ports[1].bits.uop.fu_code[1]
connect slots_17.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[17].wakeup_ports[1].bits.uop.fu_code[2]
connect slots_17.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[17].wakeup_ports[1].bits.uop.fu_code[3]
connect slots_17.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[17].wakeup_ports[1].bits.uop.fu_code[4]
connect slots_17.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[17].wakeup_ports[1].bits.uop.fu_code[5]
connect slots_17.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[17].wakeup_ports[1].bits.uop.fu_code[6]
connect slots_17.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[17].wakeup_ports[1].bits.uop.fu_code[7]
connect slots_17.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[17].wakeup_ports[1].bits.uop.fu_code[8]
connect slots_17.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[17].wakeup_ports[1].bits.uop.fu_code[9]
connect slots_17.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[17].wakeup_ports[1].bits.uop.iq_type[0]
connect slots_17.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[17].wakeup_ports[1].bits.uop.iq_type[1]
connect slots_17.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[17].wakeup_ports[1].bits.uop.iq_type[2]
connect slots_17.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[17].wakeup_ports[1].bits.uop.iq_type[3]
connect slots_17.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[17].wakeup_ports[1].bits.uop.debug_pc
connect slots_17.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[17].wakeup_ports[1].bits.uop.is_rvc
connect slots_17.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[17].wakeup_ports[1].bits.uop.debug_inst
connect slots_17.io.wakeup_ports[1].bits.uop.inst, issue_slots[17].wakeup_ports[1].bits.uop.inst
connect slots_17.io.wakeup_ports[1].valid, issue_slots[17].wakeup_ports[1].valid
connect slots_17.io.wakeup_ports[2].bits.rebusy, issue_slots[17].wakeup_ports[2].bits.rebusy
connect slots_17.io.wakeup_ports[2].bits.speculative_mask, issue_slots[17].wakeup_ports[2].bits.speculative_mask
connect slots_17.io.wakeup_ports[2].bits.bypassable, issue_slots[17].wakeup_ports[2].bits.bypassable
connect slots_17.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[17].wakeup_ports[2].bits.uop.debug_tsrc
connect slots_17.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[17].wakeup_ports[2].bits.uop.debug_fsrc
connect slots_17.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[17].wakeup_ports[2].bits.uop.bp_xcpt_if
connect slots_17.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[17].wakeup_ports[2].bits.uop.bp_debug_if
connect slots_17.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[17].wakeup_ports[2].bits.uop.xcpt_ma_if
connect slots_17.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[17].wakeup_ports[2].bits.uop.xcpt_ae_if
connect slots_17.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[17].wakeup_ports[2].bits.uop.xcpt_pf_if
connect slots_17.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[17].wakeup_ports[2].bits.uop.fp_typ
connect slots_17.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[17].wakeup_ports[2].bits.uop.fp_rm
connect slots_17.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[17].wakeup_ports[2].bits.uop.fp_val
connect slots_17.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[17].wakeup_ports[2].bits.uop.fcn_op
connect slots_17.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[17].wakeup_ports[2].bits.uop.fcn_dw
connect slots_17.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[17].wakeup_ports[2].bits.uop.frs3_en
connect slots_17.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[17].wakeup_ports[2].bits.uop.lrs2_rtype
connect slots_17.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[17].wakeup_ports[2].bits.uop.lrs1_rtype
connect slots_17.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[17].wakeup_ports[2].bits.uop.dst_rtype
connect slots_17.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[17].wakeup_ports[2].bits.uop.lrs3
connect slots_17.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[17].wakeup_ports[2].bits.uop.lrs2
connect slots_17.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[17].wakeup_ports[2].bits.uop.lrs1
connect slots_17.io.wakeup_ports[2].bits.uop.ldst, issue_slots[17].wakeup_ports[2].bits.uop.ldst
connect slots_17.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[17].wakeup_ports[2].bits.uop.ldst_is_rs1
connect slots_17.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[17].wakeup_ports[2].bits.uop.csr_cmd
connect slots_17.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[17].wakeup_ports[2].bits.uop.flush_on_commit
connect slots_17.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[17].wakeup_ports[2].bits.uop.is_unique
connect slots_17.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[17].wakeup_ports[2].bits.uop.uses_stq
connect slots_17.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[17].wakeup_ports[2].bits.uop.uses_ldq
connect slots_17.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[17].wakeup_ports[2].bits.uop.mem_signed
connect slots_17.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[17].wakeup_ports[2].bits.uop.mem_size
connect slots_17.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[17].wakeup_ports[2].bits.uop.mem_cmd
connect slots_17.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[17].wakeup_ports[2].bits.uop.exc_cause
connect slots_17.io.wakeup_ports[2].bits.uop.exception, issue_slots[17].wakeup_ports[2].bits.uop.exception
connect slots_17.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[17].wakeup_ports[2].bits.uop.stale_pdst
connect slots_17.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[17].wakeup_ports[2].bits.uop.ppred_busy
connect slots_17.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[17].wakeup_ports[2].bits.uop.prs3_busy
connect slots_17.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[17].wakeup_ports[2].bits.uop.prs2_busy
connect slots_17.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[17].wakeup_ports[2].bits.uop.prs1_busy
connect slots_17.io.wakeup_ports[2].bits.uop.ppred, issue_slots[17].wakeup_ports[2].bits.uop.ppred
connect slots_17.io.wakeup_ports[2].bits.uop.prs3, issue_slots[17].wakeup_ports[2].bits.uop.prs3
connect slots_17.io.wakeup_ports[2].bits.uop.prs2, issue_slots[17].wakeup_ports[2].bits.uop.prs2
connect slots_17.io.wakeup_ports[2].bits.uop.prs1, issue_slots[17].wakeup_ports[2].bits.uop.prs1
connect slots_17.io.wakeup_ports[2].bits.uop.pdst, issue_slots[17].wakeup_ports[2].bits.uop.pdst
connect slots_17.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[17].wakeup_ports[2].bits.uop.rxq_idx
connect slots_17.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[17].wakeup_ports[2].bits.uop.stq_idx
connect slots_17.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[17].wakeup_ports[2].bits.uop.ldq_idx
connect slots_17.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[17].wakeup_ports[2].bits.uop.rob_idx
connect slots_17.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.vec
connect slots_17.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.wflags
connect slots_17.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.sqrt
connect slots_17.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.div
connect slots_17.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.fma
connect slots_17.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe
connect slots_17.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.toint
connect slots_17.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.fromint
connect slots_17.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut
connect slots_17.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn
connect slots_17.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.swap23
connect slots_17.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.swap12
connect slots_17.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.ren3
connect slots_17.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.ren2
connect slots_17.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.ren1
connect slots_17.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.wen
connect slots_17.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.ldst
connect slots_17.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[17].wakeup_ports[2].bits.uop.op2_sel
connect slots_17.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[17].wakeup_ports[2].bits.uop.op1_sel
connect slots_17.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[17].wakeup_ports[2].bits.uop.imm_packed
connect slots_17.io.wakeup_ports[2].bits.uop.pimm, issue_slots[17].wakeup_ports[2].bits.uop.pimm
connect slots_17.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[17].wakeup_ports[2].bits.uop.imm_sel
connect slots_17.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[17].wakeup_ports[2].bits.uop.imm_rename
connect slots_17.io.wakeup_ports[2].bits.uop.taken, issue_slots[17].wakeup_ports[2].bits.uop.taken
connect slots_17.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[17].wakeup_ports[2].bits.uop.pc_lob
connect slots_17.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[17].wakeup_ports[2].bits.uop.edge_inst
connect slots_17.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[17].wakeup_ports[2].bits.uop.ftq_idx
connect slots_17.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[17].wakeup_ports[2].bits.uop.is_mov
connect slots_17.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[17].wakeup_ports[2].bits.uop.is_rocc
connect slots_17.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[17].wakeup_ports[2].bits.uop.is_sys_pc2epc
connect slots_17.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[17].wakeup_ports[2].bits.uop.is_eret
connect slots_17.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[17].wakeup_ports[2].bits.uop.is_amo
connect slots_17.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[17].wakeup_ports[2].bits.uop.is_sfence
connect slots_17.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[17].wakeup_ports[2].bits.uop.is_fencei
connect slots_17.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[17].wakeup_ports[2].bits.uop.is_fence
connect slots_17.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[17].wakeup_ports[2].bits.uop.is_sfb
connect slots_17.io.wakeup_ports[2].bits.uop.br_type, issue_slots[17].wakeup_ports[2].bits.uop.br_type
connect slots_17.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[17].wakeup_ports[2].bits.uop.br_tag
connect slots_17.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[17].wakeup_ports[2].bits.uop.br_mask
connect slots_17.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[17].wakeup_ports[2].bits.uop.dis_col_sel
connect slots_17.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[17].wakeup_ports[2].bits.uop.iw_p3_bypass_hint
connect slots_17.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[17].wakeup_ports[2].bits.uop.iw_p2_bypass_hint
connect slots_17.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[17].wakeup_ports[2].bits.uop.iw_p1_bypass_hint
connect slots_17.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[17].wakeup_ports[2].bits.uop.iw_p2_speculative_child
connect slots_17.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[17].wakeup_ports[2].bits.uop.iw_p1_speculative_child
connect slots_17.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[17].wakeup_ports[2].bits.uop.iw_issued_partial_dgen
connect slots_17.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[17].wakeup_ports[2].bits.uop.iw_issued_partial_agen
connect slots_17.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[17].wakeup_ports[2].bits.uop.iw_issued
connect slots_17.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[17].wakeup_ports[2].bits.uop.fu_code[0]
connect slots_17.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[17].wakeup_ports[2].bits.uop.fu_code[1]
connect slots_17.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[17].wakeup_ports[2].bits.uop.fu_code[2]
connect slots_17.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[17].wakeup_ports[2].bits.uop.fu_code[3]
connect slots_17.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[17].wakeup_ports[2].bits.uop.fu_code[4]
connect slots_17.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[17].wakeup_ports[2].bits.uop.fu_code[5]
connect slots_17.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[17].wakeup_ports[2].bits.uop.fu_code[6]
connect slots_17.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[17].wakeup_ports[2].bits.uop.fu_code[7]
connect slots_17.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[17].wakeup_ports[2].bits.uop.fu_code[8]
connect slots_17.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[17].wakeup_ports[2].bits.uop.fu_code[9]
connect slots_17.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[17].wakeup_ports[2].bits.uop.iq_type[0]
connect slots_17.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[17].wakeup_ports[2].bits.uop.iq_type[1]
connect slots_17.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[17].wakeup_ports[2].bits.uop.iq_type[2]
connect slots_17.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[17].wakeup_ports[2].bits.uop.iq_type[3]
connect slots_17.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[17].wakeup_ports[2].bits.uop.debug_pc
connect slots_17.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[17].wakeup_ports[2].bits.uop.is_rvc
connect slots_17.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[17].wakeup_ports[2].bits.uop.debug_inst
connect slots_17.io.wakeup_ports[2].bits.uop.inst, issue_slots[17].wakeup_ports[2].bits.uop.inst
connect slots_17.io.wakeup_ports[2].valid, issue_slots[17].wakeup_ports[2].valid
connect slots_17.io.wakeup_ports[3].bits.rebusy, issue_slots[17].wakeup_ports[3].bits.rebusy
connect slots_17.io.wakeup_ports[3].bits.speculative_mask, issue_slots[17].wakeup_ports[3].bits.speculative_mask
connect slots_17.io.wakeup_ports[3].bits.bypassable, issue_slots[17].wakeup_ports[3].bits.bypassable
connect slots_17.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[17].wakeup_ports[3].bits.uop.debug_tsrc
connect slots_17.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[17].wakeup_ports[3].bits.uop.debug_fsrc
connect slots_17.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[17].wakeup_ports[3].bits.uop.bp_xcpt_if
connect slots_17.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[17].wakeup_ports[3].bits.uop.bp_debug_if
connect slots_17.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[17].wakeup_ports[3].bits.uop.xcpt_ma_if
connect slots_17.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[17].wakeup_ports[3].bits.uop.xcpt_ae_if
connect slots_17.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[17].wakeup_ports[3].bits.uop.xcpt_pf_if
connect slots_17.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[17].wakeup_ports[3].bits.uop.fp_typ
connect slots_17.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[17].wakeup_ports[3].bits.uop.fp_rm
connect slots_17.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[17].wakeup_ports[3].bits.uop.fp_val
connect slots_17.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[17].wakeup_ports[3].bits.uop.fcn_op
connect slots_17.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[17].wakeup_ports[3].bits.uop.fcn_dw
connect slots_17.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[17].wakeup_ports[3].bits.uop.frs3_en
connect slots_17.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[17].wakeup_ports[3].bits.uop.lrs2_rtype
connect slots_17.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[17].wakeup_ports[3].bits.uop.lrs1_rtype
connect slots_17.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[17].wakeup_ports[3].bits.uop.dst_rtype
connect slots_17.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[17].wakeup_ports[3].bits.uop.lrs3
connect slots_17.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[17].wakeup_ports[3].bits.uop.lrs2
connect slots_17.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[17].wakeup_ports[3].bits.uop.lrs1
connect slots_17.io.wakeup_ports[3].bits.uop.ldst, issue_slots[17].wakeup_ports[3].bits.uop.ldst
connect slots_17.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[17].wakeup_ports[3].bits.uop.ldst_is_rs1
connect slots_17.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[17].wakeup_ports[3].bits.uop.csr_cmd
connect slots_17.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[17].wakeup_ports[3].bits.uop.flush_on_commit
connect slots_17.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[17].wakeup_ports[3].bits.uop.is_unique
connect slots_17.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[17].wakeup_ports[3].bits.uop.uses_stq
connect slots_17.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[17].wakeup_ports[3].bits.uop.uses_ldq
connect slots_17.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[17].wakeup_ports[3].bits.uop.mem_signed
connect slots_17.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[17].wakeup_ports[3].bits.uop.mem_size
connect slots_17.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[17].wakeup_ports[3].bits.uop.mem_cmd
connect slots_17.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[17].wakeup_ports[3].bits.uop.exc_cause
connect slots_17.io.wakeup_ports[3].bits.uop.exception, issue_slots[17].wakeup_ports[3].bits.uop.exception
connect slots_17.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[17].wakeup_ports[3].bits.uop.stale_pdst
connect slots_17.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[17].wakeup_ports[3].bits.uop.ppred_busy
connect slots_17.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[17].wakeup_ports[3].bits.uop.prs3_busy
connect slots_17.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[17].wakeup_ports[3].bits.uop.prs2_busy
connect slots_17.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[17].wakeup_ports[3].bits.uop.prs1_busy
connect slots_17.io.wakeup_ports[3].bits.uop.ppred, issue_slots[17].wakeup_ports[3].bits.uop.ppred
connect slots_17.io.wakeup_ports[3].bits.uop.prs3, issue_slots[17].wakeup_ports[3].bits.uop.prs3
connect slots_17.io.wakeup_ports[3].bits.uop.prs2, issue_slots[17].wakeup_ports[3].bits.uop.prs2
connect slots_17.io.wakeup_ports[3].bits.uop.prs1, issue_slots[17].wakeup_ports[3].bits.uop.prs1
connect slots_17.io.wakeup_ports[3].bits.uop.pdst, issue_slots[17].wakeup_ports[3].bits.uop.pdst
connect slots_17.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[17].wakeup_ports[3].bits.uop.rxq_idx
connect slots_17.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[17].wakeup_ports[3].bits.uop.stq_idx
connect slots_17.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[17].wakeup_ports[3].bits.uop.ldq_idx
connect slots_17.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[17].wakeup_ports[3].bits.uop.rob_idx
connect slots_17.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.vec
connect slots_17.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.wflags
connect slots_17.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.sqrt
connect slots_17.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.div
connect slots_17.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.fma
connect slots_17.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe
connect slots_17.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.toint
connect slots_17.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.fromint
connect slots_17.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut
connect slots_17.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn
connect slots_17.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.swap23
connect slots_17.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.swap12
connect slots_17.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.ren3
connect slots_17.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.ren2
connect slots_17.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.ren1
connect slots_17.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.wen
connect slots_17.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.ldst
connect slots_17.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[17].wakeup_ports[3].bits.uop.op2_sel
connect slots_17.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[17].wakeup_ports[3].bits.uop.op1_sel
connect slots_17.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[17].wakeup_ports[3].bits.uop.imm_packed
connect slots_17.io.wakeup_ports[3].bits.uop.pimm, issue_slots[17].wakeup_ports[3].bits.uop.pimm
connect slots_17.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[17].wakeup_ports[3].bits.uop.imm_sel
connect slots_17.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[17].wakeup_ports[3].bits.uop.imm_rename
connect slots_17.io.wakeup_ports[3].bits.uop.taken, issue_slots[17].wakeup_ports[3].bits.uop.taken
connect slots_17.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[17].wakeup_ports[3].bits.uop.pc_lob
connect slots_17.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[17].wakeup_ports[3].bits.uop.edge_inst
connect slots_17.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[17].wakeup_ports[3].bits.uop.ftq_idx
connect slots_17.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[17].wakeup_ports[3].bits.uop.is_mov
connect slots_17.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[17].wakeup_ports[3].bits.uop.is_rocc
connect slots_17.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[17].wakeup_ports[3].bits.uop.is_sys_pc2epc
connect slots_17.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[17].wakeup_ports[3].bits.uop.is_eret
connect slots_17.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[17].wakeup_ports[3].bits.uop.is_amo
connect slots_17.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[17].wakeup_ports[3].bits.uop.is_sfence
connect slots_17.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[17].wakeup_ports[3].bits.uop.is_fencei
connect slots_17.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[17].wakeup_ports[3].bits.uop.is_fence
connect slots_17.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[17].wakeup_ports[3].bits.uop.is_sfb
connect slots_17.io.wakeup_ports[3].bits.uop.br_type, issue_slots[17].wakeup_ports[3].bits.uop.br_type
connect slots_17.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[17].wakeup_ports[3].bits.uop.br_tag
connect slots_17.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[17].wakeup_ports[3].bits.uop.br_mask
connect slots_17.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[17].wakeup_ports[3].bits.uop.dis_col_sel
connect slots_17.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[17].wakeup_ports[3].bits.uop.iw_p3_bypass_hint
connect slots_17.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[17].wakeup_ports[3].bits.uop.iw_p2_bypass_hint
connect slots_17.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[17].wakeup_ports[3].bits.uop.iw_p1_bypass_hint
connect slots_17.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[17].wakeup_ports[3].bits.uop.iw_p2_speculative_child
connect slots_17.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[17].wakeup_ports[3].bits.uop.iw_p1_speculative_child
connect slots_17.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[17].wakeup_ports[3].bits.uop.iw_issued_partial_dgen
connect slots_17.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[17].wakeup_ports[3].bits.uop.iw_issued_partial_agen
connect slots_17.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[17].wakeup_ports[3].bits.uop.iw_issued
connect slots_17.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[17].wakeup_ports[3].bits.uop.fu_code[0]
connect slots_17.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[17].wakeup_ports[3].bits.uop.fu_code[1]
connect slots_17.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[17].wakeup_ports[3].bits.uop.fu_code[2]
connect slots_17.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[17].wakeup_ports[3].bits.uop.fu_code[3]
connect slots_17.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[17].wakeup_ports[3].bits.uop.fu_code[4]
connect slots_17.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[17].wakeup_ports[3].bits.uop.fu_code[5]
connect slots_17.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[17].wakeup_ports[3].bits.uop.fu_code[6]
connect slots_17.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[17].wakeup_ports[3].bits.uop.fu_code[7]
connect slots_17.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[17].wakeup_ports[3].bits.uop.fu_code[8]
connect slots_17.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[17].wakeup_ports[3].bits.uop.fu_code[9]
connect slots_17.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[17].wakeup_ports[3].bits.uop.iq_type[0]
connect slots_17.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[17].wakeup_ports[3].bits.uop.iq_type[1]
connect slots_17.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[17].wakeup_ports[3].bits.uop.iq_type[2]
connect slots_17.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[17].wakeup_ports[3].bits.uop.iq_type[3]
connect slots_17.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[17].wakeup_ports[3].bits.uop.debug_pc
connect slots_17.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[17].wakeup_ports[3].bits.uop.is_rvc
connect slots_17.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[17].wakeup_ports[3].bits.uop.debug_inst
connect slots_17.io.wakeup_ports[3].bits.uop.inst, issue_slots[17].wakeup_ports[3].bits.uop.inst
connect slots_17.io.wakeup_ports[3].valid, issue_slots[17].wakeup_ports[3].valid
connect slots_17.io.squash_grant, issue_slots[17].squash_grant
connect slots_17.io.clear, issue_slots[17].clear
connect slots_17.io.kill, issue_slots[17].kill
connect slots_17.io.brupdate.b2.target_offset, issue_slots[17].brupdate.b2.target_offset
connect slots_17.io.brupdate.b2.jalr_target, issue_slots[17].brupdate.b2.jalr_target
connect slots_17.io.brupdate.b2.pc_sel, issue_slots[17].brupdate.b2.pc_sel
connect slots_17.io.brupdate.b2.cfi_type, issue_slots[17].brupdate.b2.cfi_type
connect slots_17.io.brupdate.b2.taken, issue_slots[17].brupdate.b2.taken
connect slots_17.io.brupdate.b2.mispredict, issue_slots[17].brupdate.b2.mispredict
connect slots_17.io.brupdate.b2.uop.debug_tsrc, issue_slots[17].brupdate.b2.uop.debug_tsrc
connect slots_17.io.brupdate.b2.uop.debug_fsrc, issue_slots[17].brupdate.b2.uop.debug_fsrc
connect slots_17.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[17].brupdate.b2.uop.bp_xcpt_if
connect slots_17.io.brupdate.b2.uop.bp_debug_if, issue_slots[17].brupdate.b2.uop.bp_debug_if
connect slots_17.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[17].brupdate.b2.uop.xcpt_ma_if
connect slots_17.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[17].brupdate.b2.uop.xcpt_ae_if
connect slots_17.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[17].brupdate.b2.uop.xcpt_pf_if
connect slots_17.io.brupdate.b2.uop.fp_typ, issue_slots[17].brupdate.b2.uop.fp_typ
connect slots_17.io.brupdate.b2.uop.fp_rm, issue_slots[17].brupdate.b2.uop.fp_rm
connect slots_17.io.brupdate.b2.uop.fp_val, issue_slots[17].brupdate.b2.uop.fp_val
connect slots_17.io.brupdate.b2.uop.fcn_op, issue_slots[17].brupdate.b2.uop.fcn_op
connect slots_17.io.brupdate.b2.uop.fcn_dw, issue_slots[17].brupdate.b2.uop.fcn_dw
connect slots_17.io.brupdate.b2.uop.frs3_en, issue_slots[17].brupdate.b2.uop.frs3_en
connect slots_17.io.brupdate.b2.uop.lrs2_rtype, issue_slots[17].brupdate.b2.uop.lrs2_rtype
connect slots_17.io.brupdate.b2.uop.lrs1_rtype, issue_slots[17].brupdate.b2.uop.lrs1_rtype
connect slots_17.io.brupdate.b2.uop.dst_rtype, issue_slots[17].brupdate.b2.uop.dst_rtype
connect slots_17.io.brupdate.b2.uop.lrs3, issue_slots[17].brupdate.b2.uop.lrs3
connect slots_17.io.brupdate.b2.uop.lrs2, issue_slots[17].brupdate.b2.uop.lrs2
connect slots_17.io.brupdate.b2.uop.lrs1, issue_slots[17].brupdate.b2.uop.lrs1
connect slots_17.io.brupdate.b2.uop.ldst, issue_slots[17].brupdate.b2.uop.ldst
connect slots_17.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[17].brupdate.b2.uop.ldst_is_rs1
connect slots_17.io.brupdate.b2.uop.csr_cmd, issue_slots[17].brupdate.b2.uop.csr_cmd
connect slots_17.io.brupdate.b2.uop.flush_on_commit, issue_slots[17].brupdate.b2.uop.flush_on_commit
connect slots_17.io.brupdate.b2.uop.is_unique, issue_slots[17].brupdate.b2.uop.is_unique
connect slots_17.io.brupdate.b2.uop.uses_stq, issue_slots[17].brupdate.b2.uop.uses_stq
connect slots_17.io.brupdate.b2.uop.uses_ldq, issue_slots[17].brupdate.b2.uop.uses_ldq
connect slots_17.io.brupdate.b2.uop.mem_signed, issue_slots[17].brupdate.b2.uop.mem_signed
connect slots_17.io.brupdate.b2.uop.mem_size, issue_slots[17].brupdate.b2.uop.mem_size
connect slots_17.io.brupdate.b2.uop.mem_cmd, issue_slots[17].brupdate.b2.uop.mem_cmd
connect slots_17.io.brupdate.b2.uop.exc_cause, issue_slots[17].brupdate.b2.uop.exc_cause
connect slots_17.io.brupdate.b2.uop.exception, issue_slots[17].brupdate.b2.uop.exception
connect slots_17.io.brupdate.b2.uop.stale_pdst, issue_slots[17].brupdate.b2.uop.stale_pdst
connect slots_17.io.brupdate.b2.uop.ppred_busy, issue_slots[17].brupdate.b2.uop.ppred_busy
connect slots_17.io.brupdate.b2.uop.prs3_busy, issue_slots[17].brupdate.b2.uop.prs3_busy
connect slots_17.io.brupdate.b2.uop.prs2_busy, issue_slots[17].brupdate.b2.uop.prs2_busy
connect slots_17.io.brupdate.b2.uop.prs1_busy, issue_slots[17].brupdate.b2.uop.prs1_busy
connect slots_17.io.brupdate.b2.uop.ppred, issue_slots[17].brupdate.b2.uop.ppred
connect slots_17.io.brupdate.b2.uop.prs3, issue_slots[17].brupdate.b2.uop.prs3
connect slots_17.io.brupdate.b2.uop.prs2, issue_slots[17].brupdate.b2.uop.prs2
connect slots_17.io.brupdate.b2.uop.prs1, issue_slots[17].brupdate.b2.uop.prs1
connect slots_17.io.brupdate.b2.uop.pdst, issue_slots[17].brupdate.b2.uop.pdst
connect slots_17.io.brupdate.b2.uop.rxq_idx, issue_slots[17].brupdate.b2.uop.rxq_idx
connect slots_17.io.brupdate.b2.uop.stq_idx, issue_slots[17].brupdate.b2.uop.stq_idx
connect slots_17.io.brupdate.b2.uop.ldq_idx, issue_slots[17].brupdate.b2.uop.ldq_idx
connect slots_17.io.brupdate.b2.uop.rob_idx, issue_slots[17].brupdate.b2.uop.rob_idx
connect slots_17.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[17].brupdate.b2.uop.fp_ctrl.vec
connect slots_17.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[17].brupdate.b2.uop.fp_ctrl.wflags
connect slots_17.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[17].brupdate.b2.uop.fp_ctrl.sqrt
connect slots_17.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[17].brupdate.b2.uop.fp_ctrl.div
connect slots_17.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[17].brupdate.b2.uop.fp_ctrl.fma
connect slots_17.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[17].brupdate.b2.uop.fp_ctrl.fastpipe
connect slots_17.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[17].brupdate.b2.uop.fp_ctrl.toint
connect slots_17.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[17].brupdate.b2.uop.fp_ctrl.fromint
connect slots_17.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[17].brupdate.b2.uop.fp_ctrl.typeTagOut
connect slots_17.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[17].brupdate.b2.uop.fp_ctrl.typeTagIn
connect slots_17.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[17].brupdate.b2.uop.fp_ctrl.swap23
connect slots_17.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[17].brupdate.b2.uop.fp_ctrl.swap12
connect slots_17.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[17].brupdate.b2.uop.fp_ctrl.ren3
connect slots_17.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[17].brupdate.b2.uop.fp_ctrl.ren2
connect slots_17.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[17].brupdate.b2.uop.fp_ctrl.ren1
connect slots_17.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[17].brupdate.b2.uop.fp_ctrl.wen
connect slots_17.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[17].brupdate.b2.uop.fp_ctrl.ldst
connect slots_17.io.brupdate.b2.uop.op2_sel, issue_slots[17].brupdate.b2.uop.op2_sel
connect slots_17.io.brupdate.b2.uop.op1_sel, issue_slots[17].brupdate.b2.uop.op1_sel
connect slots_17.io.brupdate.b2.uop.imm_packed, issue_slots[17].brupdate.b2.uop.imm_packed
connect slots_17.io.brupdate.b2.uop.pimm, issue_slots[17].brupdate.b2.uop.pimm
connect slots_17.io.brupdate.b2.uop.imm_sel, issue_slots[17].brupdate.b2.uop.imm_sel
connect slots_17.io.brupdate.b2.uop.imm_rename, issue_slots[17].brupdate.b2.uop.imm_rename
connect slots_17.io.brupdate.b2.uop.taken, issue_slots[17].brupdate.b2.uop.taken
connect slots_17.io.brupdate.b2.uop.pc_lob, issue_slots[17].brupdate.b2.uop.pc_lob
connect slots_17.io.brupdate.b2.uop.edge_inst, issue_slots[17].brupdate.b2.uop.edge_inst
connect slots_17.io.brupdate.b2.uop.ftq_idx, issue_slots[17].brupdate.b2.uop.ftq_idx
connect slots_17.io.brupdate.b2.uop.is_mov, issue_slots[17].brupdate.b2.uop.is_mov
connect slots_17.io.brupdate.b2.uop.is_rocc, issue_slots[17].brupdate.b2.uop.is_rocc
connect slots_17.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[17].brupdate.b2.uop.is_sys_pc2epc
connect slots_17.io.brupdate.b2.uop.is_eret, issue_slots[17].brupdate.b2.uop.is_eret
connect slots_17.io.brupdate.b2.uop.is_amo, issue_slots[17].brupdate.b2.uop.is_amo
connect slots_17.io.brupdate.b2.uop.is_sfence, issue_slots[17].brupdate.b2.uop.is_sfence
connect slots_17.io.brupdate.b2.uop.is_fencei, issue_slots[17].brupdate.b2.uop.is_fencei
connect slots_17.io.brupdate.b2.uop.is_fence, issue_slots[17].brupdate.b2.uop.is_fence
connect slots_17.io.brupdate.b2.uop.is_sfb, issue_slots[17].brupdate.b2.uop.is_sfb
connect slots_17.io.brupdate.b2.uop.br_type, issue_slots[17].brupdate.b2.uop.br_type
connect slots_17.io.brupdate.b2.uop.br_tag, issue_slots[17].brupdate.b2.uop.br_tag
connect slots_17.io.brupdate.b2.uop.br_mask, issue_slots[17].brupdate.b2.uop.br_mask
connect slots_17.io.brupdate.b2.uop.dis_col_sel, issue_slots[17].brupdate.b2.uop.dis_col_sel
connect slots_17.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[17].brupdate.b2.uop.iw_p3_bypass_hint
connect slots_17.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[17].brupdate.b2.uop.iw_p2_bypass_hint
connect slots_17.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[17].brupdate.b2.uop.iw_p1_bypass_hint
connect slots_17.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[17].brupdate.b2.uop.iw_p2_speculative_child
connect slots_17.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[17].brupdate.b2.uop.iw_p1_speculative_child
connect slots_17.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[17].brupdate.b2.uop.iw_issued_partial_dgen
connect slots_17.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[17].brupdate.b2.uop.iw_issued_partial_agen
connect slots_17.io.brupdate.b2.uop.iw_issued, issue_slots[17].brupdate.b2.uop.iw_issued
connect slots_17.io.brupdate.b2.uop.fu_code[0], issue_slots[17].brupdate.b2.uop.fu_code[0]
connect slots_17.io.brupdate.b2.uop.fu_code[1], issue_slots[17].brupdate.b2.uop.fu_code[1]
connect slots_17.io.brupdate.b2.uop.fu_code[2], issue_slots[17].brupdate.b2.uop.fu_code[2]
connect slots_17.io.brupdate.b2.uop.fu_code[3], issue_slots[17].brupdate.b2.uop.fu_code[3]
connect slots_17.io.brupdate.b2.uop.fu_code[4], issue_slots[17].brupdate.b2.uop.fu_code[4]
connect slots_17.io.brupdate.b2.uop.fu_code[5], issue_slots[17].brupdate.b2.uop.fu_code[5]
connect slots_17.io.brupdate.b2.uop.fu_code[6], issue_slots[17].brupdate.b2.uop.fu_code[6]
connect slots_17.io.brupdate.b2.uop.fu_code[7], issue_slots[17].brupdate.b2.uop.fu_code[7]
connect slots_17.io.brupdate.b2.uop.fu_code[8], issue_slots[17].brupdate.b2.uop.fu_code[8]
connect slots_17.io.brupdate.b2.uop.fu_code[9], issue_slots[17].brupdate.b2.uop.fu_code[9]
connect slots_17.io.brupdate.b2.uop.iq_type[0], issue_slots[17].brupdate.b2.uop.iq_type[0]
connect slots_17.io.brupdate.b2.uop.iq_type[1], issue_slots[17].brupdate.b2.uop.iq_type[1]
connect slots_17.io.brupdate.b2.uop.iq_type[2], issue_slots[17].brupdate.b2.uop.iq_type[2]
connect slots_17.io.brupdate.b2.uop.iq_type[3], issue_slots[17].brupdate.b2.uop.iq_type[3]
connect slots_17.io.brupdate.b2.uop.debug_pc, issue_slots[17].brupdate.b2.uop.debug_pc
connect slots_17.io.brupdate.b2.uop.is_rvc, issue_slots[17].brupdate.b2.uop.is_rvc
connect slots_17.io.brupdate.b2.uop.debug_inst, issue_slots[17].brupdate.b2.uop.debug_inst
connect slots_17.io.brupdate.b2.uop.inst, issue_slots[17].brupdate.b2.uop.inst
connect slots_17.io.brupdate.b1.mispredict_mask, issue_slots[17].brupdate.b1.mispredict_mask
connect slots_17.io.brupdate.b1.resolve_mask, issue_slots[17].brupdate.b1.resolve_mask
connect issue_slots[17].out_uop.debug_tsrc, slots_17.io.out_uop.debug_tsrc
connect issue_slots[17].out_uop.debug_fsrc, slots_17.io.out_uop.debug_fsrc
connect issue_slots[17].out_uop.bp_xcpt_if, slots_17.io.out_uop.bp_xcpt_if
connect issue_slots[17].out_uop.bp_debug_if, slots_17.io.out_uop.bp_debug_if
connect issue_slots[17].out_uop.xcpt_ma_if, slots_17.io.out_uop.xcpt_ma_if
connect issue_slots[17].out_uop.xcpt_ae_if, slots_17.io.out_uop.xcpt_ae_if
connect issue_slots[17].out_uop.xcpt_pf_if, slots_17.io.out_uop.xcpt_pf_if
connect issue_slots[17].out_uop.fp_typ, slots_17.io.out_uop.fp_typ
connect issue_slots[17].out_uop.fp_rm, slots_17.io.out_uop.fp_rm
connect issue_slots[17].out_uop.fp_val, slots_17.io.out_uop.fp_val
connect issue_slots[17].out_uop.fcn_op, slots_17.io.out_uop.fcn_op
connect issue_slots[17].out_uop.fcn_dw, slots_17.io.out_uop.fcn_dw
connect issue_slots[17].out_uop.frs3_en, slots_17.io.out_uop.frs3_en
connect issue_slots[17].out_uop.lrs2_rtype, slots_17.io.out_uop.lrs2_rtype
connect issue_slots[17].out_uop.lrs1_rtype, slots_17.io.out_uop.lrs1_rtype
connect issue_slots[17].out_uop.dst_rtype, slots_17.io.out_uop.dst_rtype
connect issue_slots[17].out_uop.lrs3, slots_17.io.out_uop.lrs3
connect issue_slots[17].out_uop.lrs2, slots_17.io.out_uop.lrs2
connect issue_slots[17].out_uop.lrs1, slots_17.io.out_uop.lrs1
connect issue_slots[17].out_uop.ldst, slots_17.io.out_uop.ldst
connect issue_slots[17].out_uop.ldst_is_rs1, slots_17.io.out_uop.ldst_is_rs1
connect issue_slots[17].out_uop.csr_cmd, slots_17.io.out_uop.csr_cmd
connect issue_slots[17].out_uop.flush_on_commit, slots_17.io.out_uop.flush_on_commit
connect issue_slots[17].out_uop.is_unique, slots_17.io.out_uop.is_unique
connect issue_slots[17].out_uop.uses_stq, slots_17.io.out_uop.uses_stq
connect issue_slots[17].out_uop.uses_ldq, slots_17.io.out_uop.uses_ldq
connect issue_slots[17].out_uop.mem_signed, slots_17.io.out_uop.mem_signed
connect issue_slots[17].out_uop.mem_size, slots_17.io.out_uop.mem_size
connect issue_slots[17].out_uop.mem_cmd, slots_17.io.out_uop.mem_cmd
connect issue_slots[17].out_uop.exc_cause, slots_17.io.out_uop.exc_cause
connect issue_slots[17].out_uop.exception, slots_17.io.out_uop.exception
connect issue_slots[17].out_uop.stale_pdst, slots_17.io.out_uop.stale_pdst
connect issue_slots[17].out_uop.ppred_busy, slots_17.io.out_uop.ppred_busy
connect issue_slots[17].out_uop.prs3_busy, slots_17.io.out_uop.prs3_busy
connect issue_slots[17].out_uop.prs2_busy, slots_17.io.out_uop.prs2_busy
connect issue_slots[17].out_uop.prs1_busy, slots_17.io.out_uop.prs1_busy
connect issue_slots[17].out_uop.ppred, slots_17.io.out_uop.ppred
connect issue_slots[17].out_uop.prs3, slots_17.io.out_uop.prs3
connect issue_slots[17].out_uop.prs2, slots_17.io.out_uop.prs2
connect issue_slots[17].out_uop.prs1, slots_17.io.out_uop.prs1
connect issue_slots[17].out_uop.pdst, slots_17.io.out_uop.pdst
connect issue_slots[17].out_uop.rxq_idx, slots_17.io.out_uop.rxq_idx
connect issue_slots[17].out_uop.stq_idx, slots_17.io.out_uop.stq_idx
connect issue_slots[17].out_uop.ldq_idx, slots_17.io.out_uop.ldq_idx
connect issue_slots[17].out_uop.rob_idx, slots_17.io.out_uop.rob_idx
connect issue_slots[17].out_uop.fp_ctrl.vec, slots_17.io.out_uop.fp_ctrl.vec
connect issue_slots[17].out_uop.fp_ctrl.wflags, slots_17.io.out_uop.fp_ctrl.wflags
connect issue_slots[17].out_uop.fp_ctrl.sqrt, slots_17.io.out_uop.fp_ctrl.sqrt
connect issue_slots[17].out_uop.fp_ctrl.div, slots_17.io.out_uop.fp_ctrl.div
connect issue_slots[17].out_uop.fp_ctrl.fma, slots_17.io.out_uop.fp_ctrl.fma
connect issue_slots[17].out_uop.fp_ctrl.fastpipe, slots_17.io.out_uop.fp_ctrl.fastpipe
connect issue_slots[17].out_uop.fp_ctrl.toint, slots_17.io.out_uop.fp_ctrl.toint
connect issue_slots[17].out_uop.fp_ctrl.fromint, slots_17.io.out_uop.fp_ctrl.fromint
connect issue_slots[17].out_uop.fp_ctrl.typeTagOut, slots_17.io.out_uop.fp_ctrl.typeTagOut
connect issue_slots[17].out_uop.fp_ctrl.typeTagIn, slots_17.io.out_uop.fp_ctrl.typeTagIn
connect issue_slots[17].out_uop.fp_ctrl.swap23, slots_17.io.out_uop.fp_ctrl.swap23
connect issue_slots[17].out_uop.fp_ctrl.swap12, slots_17.io.out_uop.fp_ctrl.swap12
connect issue_slots[17].out_uop.fp_ctrl.ren3, slots_17.io.out_uop.fp_ctrl.ren3
connect issue_slots[17].out_uop.fp_ctrl.ren2, slots_17.io.out_uop.fp_ctrl.ren2
connect issue_slots[17].out_uop.fp_ctrl.ren1, slots_17.io.out_uop.fp_ctrl.ren1
connect issue_slots[17].out_uop.fp_ctrl.wen, slots_17.io.out_uop.fp_ctrl.wen
connect issue_slots[17].out_uop.fp_ctrl.ldst, slots_17.io.out_uop.fp_ctrl.ldst
connect issue_slots[17].out_uop.op2_sel, slots_17.io.out_uop.op2_sel
connect issue_slots[17].out_uop.op1_sel, slots_17.io.out_uop.op1_sel
connect issue_slots[17].out_uop.imm_packed, slots_17.io.out_uop.imm_packed
connect issue_slots[17].out_uop.pimm, slots_17.io.out_uop.pimm
connect issue_slots[17].out_uop.imm_sel, slots_17.io.out_uop.imm_sel
connect issue_slots[17].out_uop.imm_rename, slots_17.io.out_uop.imm_rename
connect issue_slots[17].out_uop.taken, slots_17.io.out_uop.taken
connect issue_slots[17].out_uop.pc_lob, slots_17.io.out_uop.pc_lob
connect issue_slots[17].out_uop.edge_inst, slots_17.io.out_uop.edge_inst
connect issue_slots[17].out_uop.ftq_idx, slots_17.io.out_uop.ftq_idx
connect issue_slots[17].out_uop.is_mov, slots_17.io.out_uop.is_mov
connect issue_slots[17].out_uop.is_rocc, slots_17.io.out_uop.is_rocc
connect issue_slots[17].out_uop.is_sys_pc2epc, slots_17.io.out_uop.is_sys_pc2epc
connect issue_slots[17].out_uop.is_eret, slots_17.io.out_uop.is_eret
connect issue_slots[17].out_uop.is_amo, slots_17.io.out_uop.is_amo
connect issue_slots[17].out_uop.is_sfence, slots_17.io.out_uop.is_sfence
connect issue_slots[17].out_uop.is_fencei, slots_17.io.out_uop.is_fencei
connect issue_slots[17].out_uop.is_fence, slots_17.io.out_uop.is_fence
connect issue_slots[17].out_uop.is_sfb, slots_17.io.out_uop.is_sfb
connect issue_slots[17].out_uop.br_type, slots_17.io.out_uop.br_type
connect issue_slots[17].out_uop.br_tag, slots_17.io.out_uop.br_tag
connect issue_slots[17].out_uop.br_mask, slots_17.io.out_uop.br_mask
connect issue_slots[17].out_uop.dis_col_sel, slots_17.io.out_uop.dis_col_sel
connect issue_slots[17].out_uop.iw_p3_bypass_hint, slots_17.io.out_uop.iw_p3_bypass_hint
connect issue_slots[17].out_uop.iw_p2_bypass_hint, slots_17.io.out_uop.iw_p2_bypass_hint
connect issue_slots[17].out_uop.iw_p1_bypass_hint, slots_17.io.out_uop.iw_p1_bypass_hint
connect issue_slots[17].out_uop.iw_p2_speculative_child, slots_17.io.out_uop.iw_p2_speculative_child
connect issue_slots[17].out_uop.iw_p1_speculative_child, slots_17.io.out_uop.iw_p1_speculative_child
connect issue_slots[17].out_uop.iw_issued_partial_dgen, slots_17.io.out_uop.iw_issued_partial_dgen
connect issue_slots[17].out_uop.iw_issued_partial_agen, slots_17.io.out_uop.iw_issued_partial_agen
connect issue_slots[17].out_uop.iw_issued, slots_17.io.out_uop.iw_issued
connect issue_slots[17].out_uop.fu_code[0], slots_17.io.out_uop.fu_code[0]
connect issue_slots[17].out_uop.fu_code[1], slots_17.io.out_uop.fu_code[1]
connect issue_slots[17].out_uop.fu_code[2], slots_17.io.out_uop.fu_code[2]
connect issue_slots[17].out_uop.fu_code[3], slots_17.io.out_uop.fu_code[3]
connect issue_slots[17].out_uop.fu_code[4], slots_17.io.out_uop.fu_code[4]
connect issue_slots[17].out_uop.fu_code[5], slots_17.io.out_uop.fu_code[5]
connect issue_slots[17].out_uop.fu_code[6], slots_17.io.out_uop.fu_code[6]
connect issue_slots[17].out_uop.fu_code[7], slots_17.io.out_uop.fu_code[7]
connect issue_slots[17].out_uop.fu_code[8], slots_17.io.out_uop.fu_code[8]
connect issue_slots[17].out_uop.fu_code[9], slots_17.io.out_uop.fu_code[9]
connect issue_slots[17].out_uop.iq_type[0], slots_17.io.out_uop.iq_type[0]
connect issue_slots[17].out_uop.iq_type[1], slots_17.io.out_uop.iq_type[1]
connect issue_slots[17].out_uop.iq_type[2], slots_17.io.out_uop.iq_type[2]
connect issue_slots[17].out_uop.iq_type[3], slots_17.io.out_uop.iq_type[3]
connect issue_slots[17].out_uop.debug_pc, slots_17.io.out_uop.debug_pc
connect issue_slots[17].out_uop.is_rvc, slots_17.io.out_uop.is_rvc
connect issue_slots[17].out_uop.debug_inst, slots_17.io.out_uop.debug_inst
connect issue_slots[17].out_uop.inst, slots_17.io.out_uop.inst
connect slots_17.io.in_uop.bits.debug_tsrc, issue_slots[17].in_uop.bits.debug_tsrc
connect slots_17.io.in_uop.bits.debug_fsrc, issue_slots[17].in_uop.bits.debug_fsrc
connect slots_17.io.in_uop.bits.bp_xcpt_if, issue_slots[17].in_uop.bits.bp_xcpt_if
connect slots_17.io.in_uop.bits.bp_debug_if, issue_slots[17].in_uop.bits.bp_debug_if
connect slots_17.io.in_uop.bits.xcpt_ma_if, issue_slots[17].in_uop.bits.xcpt_ma_if
connect slots_17.io.in_uop.bits.xcpt_ae_if, issue_slots[17].in_uop.bits.xcpt_ae_if
connect slots_17.io.in_uop.bits.xcpt_pf_if, issue_slots[17].in_uop.bits.xcpt_pf_if
connect slots_17.io.in_uop.bits.fp_typ, issue_slots[17].in_uop.bits.fp_typ
connect slots_17.io.in_uop.bits.fp_rm, issue_slots[17].in_uop.bits.fp_rm
connect slots_17.io.in_uop.bits.fp_val, issue_slots[17].in_uop.bits.fp_val
connect slots_17.io.in_uop.bits.fcn_op, issue_slots[17].in_uop.bits.fcn_op
connect slots_17.io.in_uop.bits.fcn_dw, issue_slots[17].in_uop.bits.fcn_dw
connect slots_17.io.in_uop.bits.frs3_en, issue_slots[17].in_uop.bits.frs3_en
connect slots_17.io.in_uop.bits.lrs2_rtype, issue_slots[17].in_uop.bits.lrs2_rtype
connect slots_17.io.in_uop.bits.lrs1_rtype, issue_slots[17].in_uop.bits.lrs1_rtype
connect slots_17.io.in_uop.bits.dst_rtype, issue_slots[17].in_uop.bits.dst_rtype
connect slots_17.io.in_uop.bits.lrs3, issue_slots[17].in_uop.bits.lrs3
connect slots_17.io.in_uop.bits.lrs2, issue_slots[17].in_uop.bits.lrs2
connect slots_17.io.in_uop.bits.lrs1, issue_slots[17].in_uop.bits.lrs1
connect slots_17.io.in_uop.bits.ldst, issue_slots[17].in_uop.bits.ldst
connect slots_17.io.in_uop.bits.ldst_is_rs1, issue_slots[17].in_uop.bits.ldst_is_rs1
connect slots_17.io.in_uop.bits.csr_cmd, issue_slots[17].in_uop.bits.csr_cmd
connect slots_17.io.in_uop.bits.flush_on_commit, issue_slots[17].in_uop.bits.flush_on_commit
connect slots_17.io.in_uop.bits.is_unique, issue_slots[17].in_uop.bits.is_unique
connect slots_17.io.in_uop.bits.uses_stq, issue_slots[17].in_uop.bits.uses_stq
connect slots_17.io.in_uop.bits.uses_ldq, issue_slots[17].in_uop.bits.uses_ldq
connect slots_17.io.in_uop.bits.mem_signed, issue_slots[17].in_uop.bits.mem_signed
connect slots_17.io.in_uop.bits.mem_size, issue_slots[17].in_uop.bits.mem_size
connect slots_17.io.in_uop.bits.mem_cmd, issue_slots[17].in_uop.bits.mem_cmd
connect slots_17.io.in_uop.bits.exc_cause, issue_slots[17].in_uop.bits.exc_cause
connect slots_17.io.in_uop.bits.exception, issue_slots[17].in_uop.bits.exception
connect slots_17.io.in_uop.bits.stale_pdst, issue_slots[17].in_uop.bits.stale_pdst
connect slots_17.io.in_uop.bits.ppred_busy, issue_slots[17].in_uop.bits.ppred_busy
connect slots_17.io.in_uop.bits.prs3_busy, issue_slots[17].in_uop.bits.prs3_busy
connect slots_17.io.in_uop.bits.prs2_busy, issue_slots[17].in_uop.bits.prs2_busy
connect slots_17.io.in_uop.bits.prs1_busy, issue_slots[17].in_uop.bits.prs1_busy
connect slots_17.io.in_uop.bits.ppred, issue_slots[17].in_uop.bits.ppred
connect slots_17.io.in_uop.bits.prs3, issue_slots[17].in_uop.bits.prs3
connect slots_17.io.in_uop.bits.prs2, issue_slots[17].in_uop.bits.prs2
connect slots_17.io.in_uop.bits.prs1, issue_slots[17].in_uop.bits.prs1
connect slots_17.io.in_uop.bits.pdst, issue_slots[17].in_uop.bits.pdst
connect slots_17.io.in_uop.bits.rxq_idx, issue_slots[17].in_uop.bits.rxq_idx
connect slots_17.io.in_uop.bits.stq_idx, issue_slots[17].in_uop.bits.stq_idx
connect slots_17.io.in_uop.bits.ldq_idx, issue_slots[17].in_uop.bits.ldq_idx
connect slots_17.io.in_uop.bits.rob_idx, issue_slots[17].in_uop.bits.rob_idx
connect slots_17.io.in_uop.bits.fp_ctrl.vec, issue_slots[17].in_uop.bits.fp_ctrl.vec
connect slots_17.io.in_uop.bits.fp_ctrl.wflags, issue_slots[17].in_uop.bits.fp_ctrl.wflags
connect slots_17.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[17].in_uop.bits.fp_ctrl.sqrt
connect slots_17.io.in_uop.bits.fp_ctrl.div, issue_slots[17].in_uop.bits.fp_ctrl.div
connect slots_17.io.in_uop.bits.fp_ctrl.fma, issue_slots[17].in_uop.bits.fp_ctrl.fma
connect slots_17.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[17].in_uop.bits.fp_ctrl.fastpipe
connect slots_17.io.in_uop.bits.fp_ctrl.toint, issue_slots[17].in_uop.bits.fp_ctrl.toint
connect slots_17.io.in_uop.bits.fp_ctrl.fromint, issue_slots[17].in_uop.bits.fp_ctrl.fromint
connect slots_17.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[17].in_uop.bits.fp_ctrl.typeTagOut
connect slots_17.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[17].in_uop.bits.fp_ctrl.typeTagIn
connect slots_17.io.in_uop.bits.fp_ctrl.swap23, issue_slots[17].in_uop.bits.fp_ctrl.swap23
connect slots_17.io.in_uop.bits.fp_ctrl.swap12, issue_slots[17].in_uop.bits.fp_ctrl.swap12
connect slots_17.io.in_uop.bits.fp_ctrl.ren3, issue_slots[17].in_uop.bits.fp_ctrl.ren3
connect slots_17.io.in_uop.bits.fp_ctrl.ren2, issue_slots[17].in_uop.bits.fp_ctrl.ren2
connect slots_17.io.in_uop.bits.fp_ctrl.ren1, issue_slots[17].in_uop.bits.fp_ctrl.ren1
connect slots_17.io.in_uop.bits.fp_ctrl.wen, issue_slots[17].in_uop.bits.fp_ctrl.wen
connect slots_17.io.in_uop.bits.fp_ctrl.ldst, issue_slots[17].in_uop.bits.fp_ctrl.ldst
connect slots_17.io.in_uop.bits.op2_sel, issue_slots[17].in_uop.bits.op2_sel
connect slots_17.io.in_uop.bits.op1_sel, issue_slots[17].in_uop.bits.op1_sel
connect slots_17.io.in_uop.bits.imm_packed, issue_slots[17].in_uop.bits.imm_packed
connect slots_17.io.in_uop.bits.pimm, issue_slots[17].in_uop.bits.pimm
connect slots_17.io.in_uop.bits.imm_sel, issue_slots[17].in_uop.bits.imm_sel
connect slots_17.io.in_uop.bits.imm_rename, issue_slots[17].in_uop.bits.imm_rename
connect slots_17.io.in_uop.bits.taken, issue_slots[17].in_uop.bits.taken
connect slots_17.io.in_uop.bits.pc_lob, issue_slots[17].in_uop.bits.pc_lob
connect slots_17.io.in_uop.bits.edge_inst, issue_slots[17].in_uop.bits.edge_inst
connect slots_17.io.in_uop.bits.ftq_idx, issue_slots[17].in_uop.bits.ftq_idx
connect slots_17.io.in_uop.bits.is_mov, issue_slots[17].in_uop.bits.is_mov
connect slots_17.io.in_uop.bits.is_rocc, issue_slots[17].in_uop.bits.is_rocc
connect slots_17.io.in_uop.bits.is_sys_pc2epc, issue_slots[17].in_uop.bits.is_sys_pc2epc
connect slots_17.io.in_uop.bits.is_eret, issue_slots[17].in_uop.bits.is_eret
connect slots_17.io.in_uop.bits.is_amo, issue_slots[17].in_uop.bits.is_amo
connect slots_17.io.in_uop.bits.is_sfence, issue_slots[17].in_uop.bits.is_sfence
connect slots_17.io.in_uop.bits.is_fencei, issue_slots[17].in_uop.bits.is_fencei
connect slots_17.io.in_uop.bits.is_fence, issue_slots[17].in_uop.bits.is_fence
connect slots_17.io.in_uop.bits.is_sfb, issue_slots[17].in_uop.bits.is_sfb
connect slots_17.io.in_uop.bits.br_type, issue_slots[17].in_uop.bits.br_type
connect slots_17.io.in_uop.bits.br_tag, issue_slots[17].in_uop.bits.br_tag
connect slots_17.io.in_uop.bits.br_mask, issue_slots[17].in_uop.bits.br_mask
connect slots_17.io.in_uop.bits.dis_col_sel, issue_slots[17].in_uop.bits.dis_col_sel
connect slots_17.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[17].in_uop.bits.iw_p3_bypass_hint
connect slots_17.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[17].in_uop.bits.iw_p2_bypass_hint
connect slots_17.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[17].in_uop.bits.iw_p1_bypass_hint
connect slots_17.io.in_uop.bits.iw_p2_speculative_child, issue_slots[17].in_uop.bits.iw_p2_speculative_child
connect slots_17.io.in_uop.bits.iw_p1_speculative_child, issue_slots[17].in_uop.bits.iw_p1_speculative_child
connect slots_17.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[17].in_uop.bits.iw_issued_partial_dgen
connect slots_17.io.in_uop.bits.iw_issued_partial_agen, issue_slots[17].in_uop.bits.iw_issued_partial_agen
connect slots_17.io.in_uop.bits.iw_issued, issue_slots[17].in_uop.bits.iw_issued
connect slots_17.io.in_uop.bits.fu_code[0], issue_slots[17].in_uop.bits.fu_code[0]
connect slots_17.io.in_uop.bits.fu_code[1], issue_slots[17].in_uop.bits.fu_code[1]
connect slots_17.io.in_uop.bits.fu_code[2], issue_slots[17].in_uop.bits.fu_code[2]
connect slots_17.io.in_uop.bits.fu_code[3], issue_slots[17].in_uop.bits.fu_code[3]
connect slots_17.io.in_uop.bits.fu_code[4], issue_slots[17].in_uop.bits.fu_code[4]
connect slots_17.io.in_uop.bits.fu_code[5], issue_slots[17].in_uop.bits.fu_code[5]
connect slots_17.io.in_uop.bits.fu_code[6], issue_slots[17].in_uop.bits.fu_code[6]
connect slots_17.io.in_uop.bits.fu_code[7], issue_slots[17].in_uop.bits.fu_code[7]
connect slots_17.io.in_uop.bits.fu_code[8], issue_slots[17].in_uop.bits.fu_code[8]
connect slots_17.io.in_uop.bits.fu_code[9], issue_slots[17].in_uop.bits.fu_code[9]
connect slots_17.io.in_uop.bits.iq_type[0], issue_slots[17].in_uop.bits.iq_type[0]
connect slots_17.io.in_uop.bits.iq_type[1], issue_slots[17].in_uop.bits.iq_type[1]
connect slots_17.io.in_uop.bits.iq_type[2], issue_slots[17].in_uop.bits.iq_type[2]
connect slots_17.io.in_uop.bits.iq_type[3], issue_slots[17].in_uop.bits.iq_type[3]
connect slots_17.io.in_uop.bits.debug_pc, issue_slots[17].in_uop.bits.debug_pc
connect slots_17.io.in_uop.bits.is_rvc, issue_slots[17].in_uop.bits.is_rvc
connect slots_17.io.in_uop.bits.debug_inst, issue_slots[17].in_uop.bits.debug_inst
connect slots_17.io.in_uop.bits.inst, issue_slots[17].in_uop.bits.inst
connect slots_17.io.in_uop.valid, issue_slots[17].in_uop.valid
connect issue_slots[17].iss_uop.debug_tsrc, slots_17.io.iss_uop.debug_tsrc
connect issue_slots[17].iss_uop.debug_fsrc, slots_17.io.iss_uop.debug_fsrc
connect issue_slots[17].iss_uop.bp_xcpt_if, slots_17.io.iss_uop.bp_xcpt_if
connect issue_slots[17].iss_uop.bp_debug_if, slots_17.io.iss_uop.bp_debug_if
connect issue_slots[17].iss_uop.xcpt_ma_if, slots_17.io.iss_uop.xcpt_ma_if
connect issue_slots[17].iss_uop.xcpt_ae_if, slots_17.io.iss_uop.xcpt_ae_if
connect issue_slots[17].iss_uop.xcpt_pf_if, slots_17.io.iss_uop.xcpt_pf_if
connect issue_slots[17].iss_uop.fp_typ, slots_17.io.iss_uop.fp_typ
connect issue_slots[17].iss_uop.fp_rm, slots_17.io.iss_uop.fp_rm
connect issue_slots[17].iss_uop.fp_val, slots_17.io.iss_uop.fp_val
connect issue_slots[17].iss_uop.fcn_op, slots_17.io.iss_uop.fcn_op
connect issue_slots[17].iss_uop.fcn_dw, slots_17.io.iss_uop.fcn_dw
connect issue_slots[17].iss_uop.frs3_en, slots_17.io.iss_uop.frs3_en
connect issue_slots[17].iss_uop.lrs2_rtype, slots_17.io.iss_uop.lrs2_rtype
connect issue_slots[17].iss_uop.lrs1_rtype, slots_17.io.iss_uop.lrs1_rtype
connect issue_slots[17].iss_uop.dst_rtype, slots_17.io.iss_uop.dst_rtype
connect issue_slots[17].iss_uop.lrs3, slots_17.io.iss_uop.lrs3
connect issue_slots[17].iss_uop.lrs2, slots_17.io.iss_uop.lrs2
connect issue_slots[17].iss_uop.lrs1, slots_17.io.iss_uop.lrs1
connect issue_slots[17].iss_uop.ldst, slots_17.io.iss_uop.ldst
connect issue_slots[17].iss_uop.ldst_is_rs1, slots_17.io.iss_uop.ldst_is_rs1
connect issue_slots[17].iss_uop.csr_cmd, slots_17.io.iss_uop.csr_cmd
connect issue_slots[17].iss_uop.flush_on_commit, slots_17.io.iss_uop.flush_on_commit
connect issue_slots[17].iss_uop.is_unique, slots_17.io.iss_uop.is_unique
connect issue_slots[17].iss_uop.uses_stq, slots_17.io.iss_uop.uses_stq
connect issue_slots[17].iss_uop.uses_ldq, slots_17.io.iss_uop.uses_ldq
connect issue_slots[17].iss_uop.mem_signed, slots_17.io.iss_uop.mem_signed
connect issue_slots[17].iss_uop.mem_size, slots_17.io.iss_uop.mem_size
connect issue_slots[17].iss_uop.mem_cmd, slots_17.io.iss_uop.mem_cmd
connect issue_slots[17].iss_uop.exc_cause, slots_17.io.iss_uop.exc_cause
connect issue_slots[17].iss_uop.exception, slots_17.io.iss_uop.exception
connect issue_slots[17].iss_uop.stale_pdst, slots_17.io.iss_uop.stale_pdst
connect issue_slots[17].iss_uop.ppred_busy, slots_17.io.iss_uop.ppred_busy
connect issue_slots[17].iss_uop.prs3_busy, slots_17.io.iss_uop.prs3_busy
connect issue_slots[17].iss_uop.prs2_busy, slots_17.io.iss_uop.prs2_busy
connect issue_slots[17].iss_uop.prs1_busy, slots_17.io.iss_uop.prs1_busy
connect issue_slots[17].iss_uop.ppred, slots_17.io.iss_uop.ppred
connect issue_slots[17].iss_uop.prs3, slots_17.io.iss_uop.prs3
connect issue_slots[17].iss_uop.prs2, slots_17.io.iss_uop.prs2
connect issue_slots[17].iss_uop.prs1, slots_17.io.iss_uop.prs1
connect issue_slots[17].iss_uop.pdst, slots_17.io.iss_uop.pdst
connect issue_slots[17].iss_uop.rxq_idx, slots_17.io.iss_uop.rxq_idx
connect issue_slots[17].iss_uop.stq_idx, slots_17.io.iss_uop.stq_idx
connect issue_slots[17].iss_uop.ldq_idx, slots_17.io.iss_uop.ldq_idx
connect issue_slots[17].iss_uop.rob_idx, slots_17.io.iss_uop.rob_idx
connect issue_slots[17].iss_uop.fp_ctrl.vec, slots_17.io.iss_uop.fp_ctrl.vec
connect issue_slots[17].iss_uop.fp_ctrl.wflags, slots_17.io.iss_uop.fp_ctrl.wflags
connect issue_slots[17].iss_uop.fp_ctrl.sqrt, slots_17.io.iss_uop.fp_ctrl.sqrt
connect issue_slots[17].iss_uop.fp_ctrl.div, slots_17.io.iss_uop.fp_ctrl.div
connect issue_slots[17].iss_uop.fp_ctrl.fma, slots_17.io.iss_uop.fp_ctrl.fma
connect issue_slots[17].iss_uop.fp_ctrl.fastpipe, slots_17.io.iss_uop.fp_ctrl.fastpipe
connect issue_slots[17].iss_uop.fp_ctrl.toint, slots_17.io.iss_uop.fp_ctrl.toint
connect issue_slots[17].iss_uop.fp_ctrl.fromint, slots_17.io.iss_uop.fp_ctrl.fromint
connect issue_slots[17].iss_uop.fp_ctrl.typeTagOut, slots_17.io.iss_uop.fp_ctrl.typeTagOut
connect issue_slots[17].iss_uop.fp_ctrl.typeTagIn, slots_17.io.iss_uop.fp_ctrl.typeTagIn
connect issue_slots[17].iss_uop.fp_ctrl.swap23, slots_17.io.iss_uop.fp_ctrl.swap23
connect issue_slots[17].iss_uop.fp_ctrl.swap12, slots_17.io.iss_uop.fp_ctrl.swap12
connect issue_slots[17].iss_uop.fp_ctrl.ren3, slots_17.io.iss_uop.fp_ctrl.ren3
connect issue_slots[17].iss_uop.fp_ctrl.ren2, slots_17.io.iss_uop.fp_ctrl.ren2
connect issue_slots[17].iss_uop.fp_ctrl.ren1, slots_17.io.iss_uop.fp_ctrl.ren1
connect issue_slots[17].iss_uop.fp_ctrl.wen, slots_17.io.iss_uop.fp_ctrl.wen
connect issue_slots[17].iss_uop.fp_ctrl.ldst, slots_17.io.iss_uop.fp_ctrl.ldst
connect issue_slots[17].iss_uop.op2_sel, slots_17.io.iss_uop.op2_sel
connect issue_slots[17].iss_uop.op1_sel, slots_17.io.iss_uop.op1_sel
connect issue_slots[17].iss_uop.imm_packed, slots_17.io.iss_uop.imm_packed
connect issue_slots[17].iss_uop.pimm, slots_17.io.iss_uop.pimm
connect issue_slots[17].iss_uop.imm_sel, slots_17.io.iss_uop.imm_sel
connect issue_slots[17].iss_uop.imm_rename, slots_17.io.iss_uop.imm_rename
connect issue_slots[17].iss_uop.taken, slots_17.io.iss_uop.taken
connect issue_slots[17].iss_uop.pc_lob, slots_17.io.iss_uop.pc_lob
connect issue_slots[17].iss_uop.edge_inst, slots_17.io.iss_uop.edge_inst
connect issue_slots[17].iss_uop.ftq_idx, slots_17.io.iss_uop.ftq_idx
connect issue_slots[17].iss_uop.is_mov, slots_17.io.iss_uop.is_mov
connect issue_slots[17].iss_uop.is_rocc, slots_17.io.iss_uop.is_rocc
connect issue_slots[17].iss_uop.is_sys_pc2epc, slots_17.io.iss_uop.is_sys_pc2epc
connect issue_slots[17].iss_uop.is_eret, slots_17.io.iss_uop.is_eret
connect issue_slots[17].iss_uop.is_amo, slots_17.io.iss_uop.is_amo
connect issue_slots[17].iss_uop.is_sfence, slots_17.io.iss_uop.is_sfence
connect issue_slots[17].iss_uop.is_fencei, slots_17.io.iss_uop.is_fencei
connect issue_slots[17].iss_uop.is_fence, slots_17.io.iss_uop.is_fence
connect issue_slots[17].iss_uop.is_sfb, slots_17.io.iss_uop.is_sfb
connect issue_slots[17].iss_uop.br_type, slots_17.io.iss_uop.br_type
connect issue_slots[17].iss_uop.br_tag, slots_17.io.iss_uop.br_tag
connect issue_slots[17].iss_uop.br_mask, slots_17.io.iss_uop.br_mask
connect issue_slots[17].iss_uop.dis_col_sel, slots_17.io.iss_uop.dis_col_sel
connect issue_slots[17].iss_uop.iw_p3_bypass_hint, slots_17.io.iss_uop.iw_p3_bypass_hint
connect issue_slots[17].iss_uop.iw_p2_bypass_hint, slots_17.io.iss_uop.iw_p2_bypass_hint
connect issue_slots[17].iss_uop.iw_p1_bypass_hint, slots_17.io.iss_uop.iw_p1_bypass_hint
connect issue_slots[17].iss_uop.iw_p2_speculative_child, slots_17.io.iss_uop.iw_p2_speculative_child
connect issue_slots[17].iss_uop.iw_p1_speculative_child, slots_17.io.iss_uop.iw_p1_speculative_child
connect issue_slots[17].iss_uop.iw_issued_partial_dgen, slots_17.io.iss_uop.iw_issued_partial_dgen
connect issue_slots[17].iss_uop.iw_issued_partial_agen, slots_17.io.iss_uop.iw_issued_partial_agen
connect issue_slots[17].iss_uop.iw_issued, slots_17.io.iss_uop.iw_issued
connect issue_slots[17].iss_uop.fu_code[0], slots_17.io.iss_uop.fu_code[0]
connect issue_slots[17].iss_uop.fu_code[1], slots_17.io.iss_uop.fu_code[1]
connect issue_slots[17].iss_uop.fu_code[2], slots_17.io.iss_uop.fu_code[2]
connect issue_slots[17].iss_uop.fu_code[3], slots_17.io.iss_uop.fu_code[3]
connect issue_slots[17].iss_uop.fu_code[4], slots_17.io.iss_uop.fu_code[4]
connect issue_slots[17].iss_uop.fu_code[5], slots_17.io.iss_uop.fu_code[5]
connect issue_slots[17].iss_uop.fu_code[6], slots_17.io.iss_uop.fu_code[6]
connect issue_slots[17].iss_uop.fu_code[7], slots_17.io.iss_uop.fu_code[7]
connect issue_slots[17].iss_uop.fu_code[8], slots_17.io.iss_uop.fu_code[8]
connect issue_slots[17].iss_uop.fu_code[9], slots_17.io.iss_uop.fu_code[9]
connect issue_slots[17].iss_uop.iq_type[0], slots_17.io.iss_uop.iq_type[0]
connect issue_slots[17].iss_uop.iq_type[1], slots_17.io.iss_uop.iq_type[1]
connect issue_slots[17].iss_uop.iq_type[2], slots_17.io.iss_uop.iq_type[2]
connect issue_slots[17].iss_uop.iq_type[3], slots_17.io.iss_uop.iq_type[3]
connect issue_slots[17].iss_uop.debug_pc, slots_17.io.iss_uop.debug_pc
connect issue_slots[17].iss_uop.is_rvc, slots_17.io.iss_uop.is_rvc
connect issue_slots[17].iss_uop.debug_inst, slots_17.io.iss_uop.debug_inst
connect issue_slots[17].iss_uop.inst, slots_17.io.iss_uop.inst
connect slots_17.io.grant, issue_slots[17].grant
connect issue_slots[17].request, slots_17.io.request
connect issue_slots[17].will_be_valid, slots_17.io.will_be_valid
connect issue_slots[17].valid, slots_17.io.valid
connect slots_18.io.child_rebusys, issue_slots[18].child_rebusys
connect slots_18.io.pred_wakeup_port.bits, issue_slots[18].pred_wakeup_port.bits
connect slots_18.io.pred_wakeup_port.valid, issue_slots[18].pred_wakeup_port.valid
connect slots_18.io.wakeup_ports[0].bits.rebusy, issue_slots[18].wakeup_ports[0].bits.rebusy
connect slots_18.io.wakeup_ports[0].bits.speculative_mask, issue_slots[18].wakeup_ports[0].bits.speculative_mask
connect slots_18.io.wakeup_ports[0].bits.bypassable, issue_slots[18].wakeup_ports[0].bits.bypassable
connect slots_18.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[18].wakeup_ports[0].bits.uop.debug_tsrc
connect slots_18.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[18].wakeup_ports[0].bits.uop.debug_fsrc
connect slots_18.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[18].wakeup_ports[0].bits.uop.bp_xcpt_if
connect slots_18.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[18].wakeup_ports[0].bits.uop.bp_debug_if
connect slots_18.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[18].wakeup_ports[0].bits.uop.xcpt_ma_if
connect slots_18.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[18].wakeup_ports[0].bits.uop.xcpt_ae_if
connect slots_18.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[18].wakeup_ports[0].bits.uop.xcpt_pf_if
connect slots_18.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[18].wakeup_ports[0].bits.uop.fp_typ
connect slots_18.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[18].wakeup_ports[0].bits.uop.fp_rm
connect slots_18.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[18].wakeup_ports[0].bits.uop.fp_val
connect slots_18.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[18].wakeup_ports[0].bits.uop.fcn_op
connect slots_18.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[18].wakeup_ports[0].bits.uop.fcn_dw
connect slots_18.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[18].wakeup_ports[0].bits.uop.frs3_en
connect slots_18.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[18].wakeup_ports[0].bits.uop.lrs2_rtype
connect slots_18.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[18].wakeup_ports[0].bits.uop.lrs1_rtype
connect slots_18.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[18].wakeup_ports[0].bits.uop.dst_rtype
connect slots_18.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[18].wakeup_ports[0].bits.uop.lrs3
connect slots_18.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[18].wakeup_ports[0].bits.uop.lrs2
connect slots_18.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[18].wakeup_ports[0].bits.uop.lrs1
connect slots_18.io.wakeup_ports[0].bits.uop.ldst, issue_slots[18].wakeup_ports[0].bits.uop.ldst
connect slots_18.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[18].wakeup_ports[0].bits.uop.ldst_is_rs1
connect slots_18.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[18].wakeup_ports[0].bits.uop.csr_cmd
connect slots_18.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[18].wakeup_ports[0].bits.uop.flush_on_commit
connect slots_18.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[18].wakeup_ports[0].bits.uop.is_unique
connect slots_18.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[18].wakeup_ports[0].bits.uop.uses_stq
connect slots_18.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[18].wakeup_ports[0].bits.uop.uses_ldq
connect slots_18.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[18].wakeup_ports[0].bits.uop.mem_signed
connect slots_18.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[18].wakeup_ports[0].bits.uop.mem_size
connect slots_18.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[18].wakeup_ports[0].bits.uop.mem_cmd
connect slots_18.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[18].wakeup_ports[0].bits.uop.exc_cause
connect slots_18.io.wakeup_ports[0].bits.uop.exception, issue_slots[18].wakeup_ports[0].bits.uop.exception
connect slots_18.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[18].wakeup_ports[0].bits.uop.stale_pdst
connect slots_18.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[18].wakeup_ports[0].bits.uop.ppred_busy
connect slots_18.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[18].wakeup_ports[0].bits.uop.prs3_busy
connect slots_18.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[18].wakeup_ports[0].bits.uop.prs2_busy
connect slots_18.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[18].wakeup_ports[0].bits.uop.prs1_busy
connect slots_18.io.wakeup_ports[0].bits.uop.ppred, issue_slots[18].wakeup_ports[0].bits.uop.ppred
connect slots_18.io.wakeup_ports[0].bits.uop.prs3, issue_slots[18].wakeup_ports[0].bits.uop.prs3
connect slots_18.io.wakeup_ports[0].bits.uop.prs2, issue_slots[18].wakeup_ports[0].bits.uop.prs2
connect slots_18.io.wakeup_ports[0].bits.uop.prs1, issue_slots[18].wakeup_ports[0].bits.uop.prs1
connect slots_18.io.wakeup_ports[0].bits.uop.pdst, issue_slots[18].wakeup_ports[0].bits.uop.pdst
connect slots_18.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[18].wakeup_ports[0].bits.uop.rxq_idx
connect slots_18.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[18].wakeup_ports[0].bits.uop.stq_idx
connect slots_18.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[18].wakeup_ports[0].bits.uop.ldq_idx
connect slots_18.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[18].wakeup_ports[0].bits.uop.rob_idx
connect slots_18.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.vec
connect slots_18.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.wflags
connect slots_18.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.sqrt
connect slots_18.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.div
connect slots_18.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.fma
connect slots_18.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe
connect slots_18.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.toint
connect slots_18.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.fromint
connect slots_18.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut
connect slots_18.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn
connect slots_18.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.swap23
connect slots_18.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.swap12
connect slots_18.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.ren3
connect slots_18.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.ren2
connect slots_18.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.ren1
connect slots_18.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.wen
connect slots_18.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.ldst
connect slots_18.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[18].wakeup_ports[0].bits.uop.op2_sel
connect slots_18.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[18].wakeup_ports[0].bits.uop.op1_sel
connect slots_18.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[18].wakeup_ports[0].bits.uop.imm_packed
connect slots_18.io.wakeup_ports[0].bits.uop.pimm, issue_slots[18].wakeup_ports[0].bits.uop.pimm
connect slots_18.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[18].wakeup_ports[0].bits.uop.imm_sel
connect slots_18.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[18].wakeup_ports[0].bits.uop.imm_rename
connect slots_18.io.wakeup_ports[0].bits.uop.taken, issue_slots[18].wakeup_ports[0].bits.uop.taken
connect slots_18.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[18].wakeup_ports[0].bits.uop.pc_lob
connect slots_18.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[18].wakeup_ports[0].bits.uop.edge_inst
connect slots_18.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[18].wakeup_ports[0].bits.uop.ftq_idx
connect slots_18.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[18].wakeup_ports[0].bits.uop.is_mov
connect slots_18.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[18].wakeup_ports[0].bits.uop.is_rocc
connect slots_18.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[18].wakeup_ports[0].bits.uop.is_sys_pc2epc
connect slots_18.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[18].wakeup_ports[0].bits.uop.is_eret
connect slots_18.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[18].wakeup_ports[0].bits.uop.is_amo
connect slots_18.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[18].wakeup_ports[0].bits.uop.is_sfence
connect slots_18.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[18].wakeup_ports[0].bits.uop.is_fencei
connect slots_18.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[18].wakeup_ports[0].bits.uop.is_fence
connect slots_18.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[18].wakeup_ports[0].bits.uop.is_sfb
connect slots_18.io.wakeup_ports[0].bits.uop.br_type, issue_slots[18].wakeup_ports[0].bits.uop.br_type
connect slots_18.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[18].wakeup_ports[0].bits.uop.br_tag
connect slots_18.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[18].wakeup_ports[0].bits.uop.br_mask
connect slots_18.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[18].wakeup_ports[0].bits.uop.dis_col_sel
connect slots_18.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[18].wakeup_ports[0].bits.uop.iw_p3_bypass_hint
connect slots_18.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[18].wakeup_ports[0].bits.uop.iw_p2_bypass_hint
connect slots_18.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[18].wakeup_ports[0].bits.uop.iw_p1_bypass_hint
connect slots_18.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[18].wakeup_ports[0].bits.uop.iw_p2_speculative_child
connect slots_18.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[18].wakeup_ports[0].bits.uop.iw_p1_speculative_child
connect slots_18.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[18].wakeup_ports[0].bits.uop.iw_issued_partial_dgen
connect slots_18.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[18].wakeup_ports[0].bits.uop.iw_issued_partial_agen
connect slots_18.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[18].wakeup_ports[0].bits.uop.iw_issued
connect slots_18.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[18].wakeup_ports[0].bits.uop.fu_code[0]
connect slots_18.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[18].wakeup_ports[0].bits.uop.fu_code[1]
connect slots_18.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[18].wakeup_ports[0].bits.uop.fu_code[2]
connect slots_18.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[18].wakeup_ports[0].bits.uop.fu_code[3]
connect slots_18.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[18].wakeup_ports[0].bits.uop.fu_code[4]
connect slots_18.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[18].wakeup_ports[0].bits.uop.fu_code[5]
connect slots_18.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[18].wakeup_ports[0].bits.uop.fu_code[6]
connect slots_18.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[18].wakeup_ports[0].bits.uop.fu_code[7]
connect slots_18.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[18].wakeup_ports[0].bits.uop.fu_code[8]
connect slots_18.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[18].wakeup_ports[0].bits.uop.fu_code[9]
connect slots_18.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[18].wakeup_ports[0].bits.uop.iq_type[0]
connect slots_18.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[18].wakeup_ports[0].bits.uop.iq_type[1]
connect slots_18.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[18].wakeup_ports[0].bits.uop.iq_type[2]
connect slots_18.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[18].wakeup_ports[0].bits.uop.iq_type[3]
connect slots_18.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[18].wakeup_ports[0].bits.uop.debug_pc
connect slots_18.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[18].wakeup_ports[0].bits.uop.is_rvc
connect slots_18.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[18].wakeup_ports[0].bits.uop.debug_inst
connect slots_18.io.wakeup_ports[0].bits.uop.inst, issue_slots[18].wakeup_ports[0].bits.uop.inst
connect slots_18.io.wakeup_ports[0].valid, issue_slots[18].wakeup_ports[0].valid
connect slots_18.io.wakeup_ports[1].bits.rebusy, issue_slots[18].wakeup_ports[1].bits.rebusy
connect slots_18.io.wakeup_ports[1].bits.speculative_mask, issue_slots[18].wakeup_ports[1].bits.speculative_mask
connect slots_18.io.wakeup_ports[1].bits.bypassable, issue_slots[18].wakeup_ports[1].bits.bypassable
connect slots_18.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[18].wakeup_ports[1].bits.uop.debug_tsrc
connect slots_18.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[18].wakeup_ports[1].bits.uop.debug_fsrc
connect slots_18.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[18].wakeup_ports[1].bits.uop.bp_xcpt_if
connect slots_18.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[18].wakeup_ports[1].bits.uop.bp_debug_if
connect slots_18.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[18].wakeup_ports[1].bits.uop.xcpt_ma_if
connect slots_18.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[18].wakeup_ports[1].bits.uop.xcpt_ae_if
connect slots_18.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[18].wakeup_ports[1].bits.uop.xcpt_pf_if
connect slots_18.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[18].wakeup_ports[1].bits.uop.fp_typ
connect slots_18.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[18].wakeup_ports[1].bits.uop.fp_rm
connect slots_18.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[18].wakeup_ports[1].bits.uop.fp_val
connect slots_18.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[18].wakeup_ports[1].bits.uop.fcn_op
connect slots_18.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[18].wakeup_ports[1].bits.uop.fcn_dw
connect slots_18.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[18].wakeup_ports[1].bits.uop.frs3_en
connect slots_18.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[18].wakeup_ports[1].bits.uop.lrs2_rtype
connect slots_18.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[18].wakeup_ports[1].bits.uop.lrs1_rtype
connect slots_18.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[18].wakeup_ports[1].bits.uop.dst_rtype
connect slots_18.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[18].wakeup_ports[1].bits.uop.lrs3
connect slots_18.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[18].wakeup_ports[1].bits.uop.lrs2
connect slots_18.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[18].wakeup_ports[1].bits.uop.lrs1
connect slots_18.io.wakeup_ports[1].bits.uop.ldst, issue_slots[18].wakeup_ports[1].bits.uop.ldst
connect slots_18.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[18].wakeup_ports[1].bits.uop.ldst_is_rs1
connect slots_18.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[18].wakeup_ports[1].bits.uop.csr_cmd
connect slots_18.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[18].wakeup_ports[1].bits.uop.flush_on_commit
connect slots_18.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[18].wakeup_ports[1].bits.uop.is_unique
connect slots_18.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[18].wakeup_ports[1].bits.uop.uses_stq
connect slots_18.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[18].wakeup_ports[1].bits.uop.uses_ldq
connect slots_18.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[18].wakeup_ports[1].bits.uop.mem_signed
connect slots_18.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[18].wakeup_ports[1].bits.uop.mem_size
connect slots_18.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[18].wakeup_ports[1].bits.uop.mem_cmd
connect slots_18.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[18].wakeup_ports[1].bits.uop.exc_cause
connect slots_18.io.wakeup_ports[1].bits.uop.exception, issue_slots[18].wakeup_ports[1].bits.uop.exception
connect slots_18.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[18].wakeup_ports[1].bits.uop.stale_pdst
connect slots_18.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[18].wakeup_ports[1].bits.uop.ppred_busy
connect slots_18.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[18].wakeup_ports[1].bits.uop.prs3_busy
connect slots_18.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[18].wakeup_ports[1].bits.uop.prs2_busy
connect slots_18.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[18].wakeup_ports[1].bits.uop.prs1_busy
connect slots_18.io.wakeup_ports[1].bits.uop.ppred, issue_slots[18].wakeup_ports[1].bits.uop.ppred
connect slots_18.io.wakeup_ports[1].bits.uop.prs3, issue_slots[18].wakeup_ports[1].bits.uop.prs3
connect slots_18.io.wakeup_ports[1].bits.uop.prs2, issue_slots[18].wakeup_ports[1].bits.uop.prs2
connect slots_18.io.wakeup_ports[1].bits.uop.prs1, issue_slots[18].wakeup_ports[1].bits.uop.prs1
connect slots_18.io.wakeup_ports[1].bits.uop.pdst, issue_slots[18].wakeup_ports[1].bits.uop.pdst
connect slots_18.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[18].wakeup_ports[1].bits.uop.rxq_idx
connect slots_18.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[18].wakeup_ports[1].bits.uop.stq_idx
connect slots_18.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[18].wakeup_ports[1].bits.uop.ldq_idx
connect slots_18.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[18].wakeup_ports[1].bits.uop.rob_idx
connect slots_18.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.vec
connect slots_18.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.wflags
connect slots_18.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.sqrt
connect slots_18.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.div
connect slots_18.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.fma
connect slots_18.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe
connect slots_18.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.toint
connect slots_18.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.fromint
connect slots_18.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut
connect slots_18.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn
connect slots_18.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.swap23
connect slots_18.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.swap12
connect slots_18.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.ren3
connect slots_18.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.ren2
connect slots_18.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.ren1
connect slots_18.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.wen
connect slots_18.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.ldst
connect slots_18.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[18].wakeup_ports[1].bits.uop.op2_sel
connect slots_18.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[18].wakeup_ports[1].bits.uop.op1_sel
connect slots_18.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[18].wakeup_ports[1].bits.uop.imm_packed
connect slots_18.io.wakeup_ports[1].bits.uop.pimm, issue_slots[18].wakeup_ports[1].bits.uop.pimm
connect slots_18.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[18].wakeup_ports[1].bits.uop.imm_sel
connect slots_18.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[18].wakeup_ports[1].bits.uop.imm_rename
connect slots_18.io.wakeup_ports[1].bits.uop.taken, issue_slots[18].wakeup_ports[1].bits.uop.taken
connect slots_18.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[18].wakeup_ports[1].bits.uop.pc_lob
connect slots_18.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[18].wakeup_ports[1].bits.uop.edge_inst
connect slots_18.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[18].wakeup_ports[1].bits.uop.ftq_idx
connect slots_18.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[18].wakeup_ports[1].bits.uop.is_mov
connect slots_18.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[18].wakeup_ports[1].bits.uop.is_rocc
connect slots_18.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[18].wakeup_ports[1].bits.uop.is_sys_pc2epc
connect slots_18.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[18].wakeup_ports[1].bits.uop.is_eret
connect slots_18.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[18].wakeup_ports[1].bits.uop.is_amo
connect slots_18.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[18].wakeup_ports[1].bits.uop.is_sfence
connect slots_18.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[18].wakeup_ports[1].bits.uop.is_fencei
connect slots_18.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[18].wakeup_ports[1].bits.uop.is_fence
connect slots_18.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[18].wakeup_ports[1].bits.uop.is_sfb
connect slots_18.io.wakeup_ports[1].bits.uop.br_type, issue_slots[18].wakeup_ports[1].bits.uop.br_type
connect slots_18.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[18].wakeup_ports[1].bits.uop.br_tag
connect slots_18.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[18].wakeup_ports[1].bits.uop.br_mask
connect slots_18.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[18].wakeup_ports[1].bits.uop.dis_col_sel
connect slots_18.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[18].wakeup_ports[1].bits.uop.iw_p3_bypass_hint
connect slots_18.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[18].wakeup_ports[1].bits.uop.iw_p2_bypass_hint
connect slots_18.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[18].wakeup_ports[1].bits.uop.iw_p1_bypass_hint
connect slots_18.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[18].wakeup_ports[1].bits.uop.iw_p2_speculative_child
connect slots_18.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[18].wakeup_ports[1].bits.uop.iw_p1_speculative_child
connect slots_18.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[18].wakeup_ports[1].bits.uop.iw_issued_partial_dgen
connect slots_18.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[18].wakeup_ports[1].bits.uop.iw_issued_partial_agen
connect slots_18.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[18].wakeup_ports[1].bits.uop.iw_issued
connect slots_18.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[18].wakeup_ports[1].bits.uop.fu_code[0]
connect slots_18.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[18].wakeup_ports[1].bits.uop.fu_code[1]
connect slots_18.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[18].wakeup_ports[1].bits.uop.fu_code[2]
connect slots_18.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[18].wakeup_ports[1].bits.uop.fu_code[3]
connect slots_18.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[18].wakeup_ports[1].bits.uop.fu_code[4]
connect slots_18.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[18].wakeup_ports[1].bits.uop.fu_code[5]
connect slots_18.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[18].wakeup_ports[1].bits.uop.fu_code[6]
connect slots_18.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[18].wakeup_ports[1].bits.uop.fu_code[7]
connect slots_18.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[18].wakeup_ports[1].bits.uop.fu_code[8]
connect slots_18.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[18].wakeup_ports[1].bits.uop.fu_code[9]
connect slots_18.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[18].wakeup_ports[1].bits.uop.iq_type[0]
connect slots_18.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[18].wakeup_ports[1].bits.uop.iq_type[1]
connect slots_18.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[18].wakeup_ports[1].bits.uop.iq_type[2]
connect slots_18.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[18].wakeup_ports[1].bits.uop.iq_type[3]
connect slots_18.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[18].wakeup_ports[1].bits.uop.debug_pc
connect slots_18.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[18].wakeup_ports[1].bits.uop.is_rvc
connect slots_18.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[18].wakeup_ports[1].bits.uop.debug_inst
connect slots_18.io.wakeup_ports[1].bits.uop.inst, issue_slots[18].wakeup_ports[1].bits.uop.inst
connect slots_18.io.wakeup_ports[1].valid, issue_slots[18].wakeup_ports[1].valid
connect slots_18.io.wakeup_ports[2].bits.rebusy, issue_slots[18].wakeup_ports[2].bits.rebusy
connect slots_18.io.wakeup_ports[2].bits.speculative_mask, issue_slots[18].wakeup_ports[2].bits.speculative_mask
connect slots_18.io.wakeup_ports[2].bits.bypassable, issue_slots[18].wakeup_ports[2].bits.bypassable
connect slots_18.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[18].wakeup_ports[2].bits.uop.debug_tsrc
connect slots_18.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[18].wakeup_ports[2].bits.uop.debug_fsrc
connect slots_18.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[18].wakeup_ports[2].bits.uop.bp_xcpt_if
connect slots_18.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[18].wakeup_ports[2].bits.uop.bp_debug_if
connect slots_18.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[18].wakeup_ports[2].bits.uop.xcpt_ma_if
connect slots_18.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[18].wakeup_ports[2].bits.uop.xcpt_ae_if
connect slots_18.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[18].wakeup_ports[2].bits.uop.xcpt_pf_if
connect slots_18.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[18].wakeup_ports[2].bits.uop.fp_typ
connect slots_18.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[18].wakeup_ports[2].bits.uop.fp_rm
connect slots_18.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[18].wakeup_ports[2].bits.uop.fp_val
connect slots_18.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[18].wakeup_ports[2].bits.uop.fcn_op
connect slots_18.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[18].wakeup_ports[2].bits.uop.fcn_dw
connect slots_18.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[18].wakeup_ports[2].bits.uop.frs3_en
connect slots_18.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[18].wakeup_ports[2].bits.uop.lrs2_rtype
connect slots_18.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[18].wakeup_ports[2].bits.uop.lrs1_rtype
connect slots_18.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[18].wakeup_ports[2].bits.uop.dst_rtype
connect slots_18.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[18].wakeup_ports[2].bits.uop.lrs3
connect slots_18.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[18].wakeup_ports[2].bits.uop.lrs2
connect slots_18.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[18].wakeup_ports[2].bits.uop.lrs1
connect slots_18.io.wakeup_ports[2].bits.uop.ldst, issue_slots[18].wakeup_ports[2].bits.uop.ldst
connect slots_18.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[18].wakeup_ports[2].bits.uop.ldst_is_rs1
connect slots_18.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[18].wakeup_ports[2].bits.uop.csr_cmd
connect slots_18.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[18].wakeup_ports[2].bits.uop.flush_on_commit
connect slots_18.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[18].wakeup_ports[2].bits.uop.is_unique
connect slots_18.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[18].wakeup_ports[2].bits.uop.uses_stq
connect slots_18.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[18].wakeup_ports[2].bits.uop.uses_ldq
connect slots_18.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[18].wakeup_ports[2].bits.uop.mem_signed
connect slots_18.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[18].wakeup_ports[2].bits.uop.mem_size
connect slots_18.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[18].wakeup_ports[2].bits.uop.mem_cmd
connect slots_18.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[18].wakeup_ports[2].bits.uop.exc_cause
connect slots_18.io.wakeup_ports[2].bits.uop.exception, issue_slots[18].wakeup_ports[2].bits.uop.exception
connect slots_18.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[18].wakeup_ports[2].bits.uop.stale_pdst
connect slots_18.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[18].wakeup_ports[2].bits.uop.ppred_busy
connect slots_18.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[18].wakeup_ports[2].bits.uop.prs3_busy
connect slots_18.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[18].wakeup_ports[2].bits.uop.prs2_busy
connect slots_18.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[18].wakeup_ports[2].bits.uop.prs1_busy
connect slots_18.io.wakeup_ports[2].bits.uop.ppred, issue_slots[18].wakeup_ports[2].bits.uop.ppred
connect slots_18.io.wakeup_ports[2].bits.uop.prs3, issue_slots[18].wakeup_ports[2].bits.uop.prs3
connect slots_18.io.wakeup_ports[2].bits.uop.prs2, issue_slots[18].wakeup_ports[2].bits.uop.prs2
connect slots_18.io.wakeup_ports[2].bits.uop.prs1, issue_slots[18].wakeup_ports[2].bits.uop.prs1
connect slots_18.io.wakeup_ports[2].bits.uop.pdst, issue_slots[18].wakeup_ports[2].bits.uop.pdst
connect slots_18.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[18].wakeup_ports[2].bits.uop.rxq_idx
connect slots_18.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[18].wakeup_ports[2].bits.uop.stq_idx
connect slots_18.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[18].wakeup_ports[2].bits.uop.ldq_idx
connect slots_18.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[18].wakeup_ports[2].bits.uop.rob_idx
connect slots_18.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.vec
connect slots_18.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.wflags
connect slots_18.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.sqrt
connect slots_18.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.div
connect slots_18.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.fma
connect slots_18.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe
connect slots_18.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.toint
connect slots_18.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.fromint
connect slots_18.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut
connect slots_18.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn
connect slots_18.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.swap23
connect slots_18.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.swap12
connect slots_18.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.ren3
connect slots_18.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.ren2
connect slots_18.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.ren1
connect slots_18.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.wen
connect slots_18.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.ldst
connect slots_18.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[18].wakeup_ports[2].bits.uop.op2_sel
connect slots_18.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[18].wakeup_ports[2].bits.uop.op1_sel
connect slots_18.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[18].wakeup_ports[2].bits.uop.imm_packed
connect slots_18.io.wakeup_ports[2].bits.uop.pimm, issue_slots[18].wakeup_ports[2].bits.uop.pimm
connect slots_18.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[18].wakeup_ports[2].bits.uop.imm_sel
connect slots_18.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[18].wakeup_ports[2].bits.uop.imm_rename
connect slots_18.io.wakeup_ports[2].bits.uop.taken, issue_slots[18].wakeup_ports[2].bits.uop.taken
connect slots_18.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[18].wakeup_ports[2].bits.uop.pc_lob
connect slots_18.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[18].wakeup_ports[2].bits.uop.edge_inst
connect slots_18.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[18].wakeup_ports[2].bits.uop.ftq_idx
connect slots_18.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[18].wakeup_ports[2].bits.uop.is_mov
connect slots_18.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[18].wakeup_ports[2].bits.uop.is_rocc
connect slots_18.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[18].wakeup_ports[2].bits.uop.is_sys_pc2epc
connect slots_18.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[18].wakeup_ports[2].bits.uop.is_eret
connect slots_18.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[18].wakeup_ports[2].bits.uop.is_amo
connect slots_18.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[18].wakeup_ports[2].bits.uop.is_sfence
connect slots_18.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[18].wakeup_ports[2].bits.uop.is_fencei
connect slots_18.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[18].wakeup_ports[2].bits.uop.is_fence
connect slots_18.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[18].wakeup_ports[2].bits.uop.is_sfb
connect slots_18.io.wakeup_ports[2].bits.uop.br_type, issue_slots[18].wakeup_ports[2].bits.uop.br_type
connect slots_18.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[18].wakeup_ports[2].bits.uop.br_tag
connect slots_18.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[18].wakeup_ports[2].bits.uop.br_mask
connect slots_18.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[18].wakeup_ports[2].bits.uop.dis_col_sel
connect slots_18.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[18].wakeup_ports[2].bits.uop.iw_p3_bypass_hint
connect slots_18.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[18].wakeup_ports[2].bits.uop.iw_p2_bypass_hint
connect slots_18.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[18].wakeup_ports[2].bits.uop.iw_p1_bypass_hint
connect slots_18.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[18].wakeup_ports[2].bits.uop.iw_p2_speculative_child
connect slots_18.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[18].wakeup_ports[2].bits.uop.iw_p1_speculative_child
connect slots_18.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[18].wakeup_ports[2].bits.uop.iw_issued_partial_dgen
connect slots_18.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[18].wakeup_ports[2].bits.uop.iw_issued_partial_agen
connect slots_18.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[18].wakeup_ports[2].bits.uop.iw_issued
connect slots_18.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[18].wakeup_ports[2].bits.uop.fu_code[0]
connect slots_18.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[18].wakeup_ports[2].bits.uop.fu_code[1]
connect slots_18.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[18].wakeup_ports[2].bits.uop.fu_code[2]
connect slots_18.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[18].wakeup_ports[2].bits.uop.fu_code[3]
connect slots_18.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[18].wakeup_ports[2].bits.uop.fu_code[4]
connect slots_18.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[18].wakeup_ports[2].bits.uop.fu_code[5]
connect slots_18.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[18].wakeup_ports[2].bits.uop.fu_code[6]
connect slots_18.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[18].wakeup_ports[2].bits.uop.fu_code[7]
connect slots_18.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[18].wakeup_ports[2].bits.uop.fu_code[8]
connect slots_18.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[18].wakeup_ports[2].bits.uop.fu_code[9]
connect slots_18.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[18].wakeup_ports[2].bits.uop.iq_type[0]
connect slots_18.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[18].wakeup_ports[2].bits.uop.iq_type[1]
connect slots_18.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[18].wakeup_ports[2].bits.uop.iq_type[2]
connect slots_18.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[18].wakeup_ports[2].bits.uop.iq_type[3]
connect slots_18.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[18].wakeup_ports[2].bits.uop.debug_pc
connect slots_18.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[18].wakeup_ports[2].bits.uop.is_rvc
connect slots_18.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[18].wakeup_ports[2].bits.uop.debug_inst
connect slots_18.io.wakeup_ports[2].bits.uop.inst, issue_slots[18].wakeup_ports[2].bits.uop.inst
connect slots_18.io.wakeup_ports[2].valid, issue_slots[18].wakeup_ports[2].valid
connect slots_18.io.wakeup_ports[3].bits.rebusy, issue_slots[18].wakeup_ports[3].bits.rebusy
connect slots_18.io.wakeup_ports[3].bits.speculative_mask, issue_slots[18].wakeup_ports[3].bits.speculative_mask
connect slots_18.io.wakeup_ports[3].bits.bypassable, issue_slots[18].wakeup_ports[3].bits.bypassable
connect slots_18.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[18].wakeup_ports[3].bits.uop.debug_tsrc
connect slots_18.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[18].wakeup_ports[3].bits.uop.debug_fsrc
connect slots_18.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[18].wakeup_ports[3].bits.uop.bp_xcpt_if
connect slots_18.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[18].wakeup_ports[3].bits.uop.bp_debug_if
connect slots_18.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[18].wakeup_ports[3].bits.uop.xcpt_ma_if
connect slots_18.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[18].wakeup_ports[3].bits.uop.xcpt_ae_if
connect slots_18.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[18].wakeup_ports[3].bits.uop.xcpt_pf_if
connect slots_18.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[18].wakeup_ports[3].bits.uop.fp_typ
connect slots_18.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[18].wakeup_ports[3].bits.uop.fp_rm
connect slots_18.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[18].wakeup_ports[3].bits.uop.fp_val
connect slots_18.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[18].wakeup_ports[3].bits.uop.fcn_op
connect slots_18.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[18].wakeup_ports[3].bits.uop.fcn_dw
connect slots_18.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[18].wakeup_ports[3].bits.uop.frs3_en
connect slots_18.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[18].wakeup_ports[3].bits.uop.lrs2_rtype
connect slots_18.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[18].wakeup_ports[3].bits.uop.lrs1_rtype
connect slots_18.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[18].wakeup_ports[3].bits.uop.dst_rtype
connect slots_18.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[18].wakeup_ports[3].bits.uop.lrs3
connect slots_18.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[18].wakeup_ports[3].bits.uop.lrs2
connect slots_18.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[18].wakeup_ports[3].bits.uop.lrs1
connect slots_18.io.wakeup_ports[3].bits.uop.ldst, issue_slots[18].wakeup_ports[3].bits.uop.ldst
connect slots_18.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[18].wakeup_ports[3].bits.uop.ldst_is_rs1
connect slots_18.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[18].wakeup_ports[3].bits.uop.csr_cmd
connect slots_18.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[18].wakeup_ports[3].bits.uop.flush_on_commit
connect slots_18.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[18].wakeup_ports[3].bits.uop.is_unique
connect slots_18.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[18].wakeup_ports[3].bits.uop.uses_stq
connect slots_18.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[18].wakeup_ports[3].bits.uop.uses_ldq
connect slots_18.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[18].wakeup_ports[3].bits.uop.mem_signed
connect slots_18.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[18].wakeup_ports[3].bits.uop.mem_size
connect slots_18.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[18].wakeup_ports[3].bits.uop.mem_cmd
connect slots_18.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[18].wakeup_ports[3].bits.uop.exc_cause
connect slots_18.io.wakeup_ports[3].bits.uop.exception, issue_slots[18].wakeup_ports[3].bits.uop.exception
connect slots_18.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[18].wakeup_ports[3].bits.uop.stale_pdst
connect slots_18.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[18].wakeup_ports[3].bits.uop.ppred_busy
connect slots_18.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[18].wakeup_ports[3].bits.uop.prs3_busy
connect slots_18.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[18].wakeup_ports[3].bits.uop.prs2_busy
connect slots_18.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[18].wakeup_ports[3].bits.uop.prs1_busy
connect slots_18.io.wakeup_ports[3].bits.uop.ppred, issue_slots[18].wakeup_ports[3].bits.uop.ppred
connect slots_18.io.wakeup_ports[3].bits.uop.prs3, issue_slots[18].wakeup_ports[3].bits.uop.prs3
connect slots_18.io.wakeup_ports[3].bits.uop.prs2, issue_slots[18].wakeup_ports[3].bits.uop.prs2
connect slots_18.io.wakeup_ports[3].bits.uop.prs1, issue_slots[18].wakeup_ports[3].bits.uop.prs1
connect slots_18.io.wakeup_ports[3].bits.uop.pdst, issue_slots[18].wakeup_ports[3].bits.uop.pdst
connect slots_18.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[18].wakeup_ports[3].bits.uop.rxq_idx
connect slots_18.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[18].wakeup_ports[3].bits.uop.stq_idx
connect slots_18.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[18].wakeup_ports[3].bits.uop.ldq_idx
connect slots_18.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[18].wakeup_ports[3].bits.uop.rob_idx
connect slots_18.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.vec
connect slots_18.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.wflags
connect slots_18.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.sqrt
connect slots_18.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.div
connect slots_18.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.fma
connect slots_18.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe
connect slots_18.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.toint
connect slots_18.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.fromint
connect slots_18.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut
connect slots_18.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn
connect slots_18.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.swap23
connect slots_18.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.swap12
connect slots_18.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.ren3
connect slots_18.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.ren2
connect slots_18.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.ren1
connect slots_18.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.wen
connect slots_18.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.ldst
connect slots_18.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[18].wakeup_ports[3].bits.uop.op2_sel
connect slots_18.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[18].wakeup_ports[3].bits.uop.op1_sel
connect slots_18.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[18].wakeup_ports[3].bits.uop.imm_packed
connect slots_18.io.wakeup_ports[3].bits.uop.pimm, issue_slots[18].wakeup_ports[3].bits.uop.pimm
connect slots_18.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[18].wakeup_ports[3].bits.uop.imm_sel
connect slots_18.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[18].wakeup_ports[3].bits.uop.imm_rename
connect slots_18.io.wakeup_ports[3].bits.uop.taken, issue_slots[18].wakeup_ports[3].bits.uop.taken
connect slots_18.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[18].wakeup_ports[3].bits.uop.pc_lob
connect slots_18.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[18].wakeup_ports[3].bits.uop.edge_inst
connect slots_18.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[18].wakeup_ports[3].bits.uop.ftq_idx
connect slots_18.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[18].wakeup_ports[3].bits.uop.is_mov
connect slots_18.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[18].wakeup_ports[3].bits.uop.is_rocc
connect slots_18.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[18].wakeup_ports[3].bits.uop.is_sys_pc2epc
connect slots_18.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[18].wakeup_ports[3].bits.uop.is_eret
connect slots_18.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[18].wakeup_ports[3].bits.uop.is_amo
connect slots_18.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[18].wakeup_ports[3].bits.uop.is_sfence
connect slots_18.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[18].wakeup_ports[3].bits.uop.is_fencei
connect slots_18.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[18].wakeup_ports[3].bits.uop.is_fence
connect slots_18.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[18].wakeup_ports[3].bits.uop.is_sfb
connect slots_18.io.wakeup_ports[3].bits.uop.br_type, issue_slots[18].wakeup_ports[3].bits.uop.br_type
connect slots_18.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[18].wakeup_ports[3].bits.uop.br_tag
connect slots_18.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[18].wakeup_ports[3].bits.uop.br_mask
connect slots_18.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[18].wakeup_ports[3].bits.uop.dis_col_sel
connect slots_18.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[18].wakeup_ports[3].bits.uop.iw_p3_bypass_hint
connect slots_18.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[18].wakeup_ports[3].bits.uop.iw_p2_bypass_hint
connect slots_18.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[18].wakeup_ports[3].bits.uop.iw_p1_bypass_hint
connect slots_18.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[18].wakeup_ports[3].bits.uop.iw_p2_speculative_child
connect slots_18.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[18].wakeup_ports[3].bits.uop.iw_p1_speculative_child
connect slots_18.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[18].wakeup_ports[3].bits.uop.iw_issued_partial_dgen
connect slots_18.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[18].wakeup_ports[3].bits.uop.iw_issued_partial_agen
connect slots_18.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[18].wakeup_ports[3].bits.uop.iw_issued
connect slots_18.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[18].wakeup_ports[3].bits.uop.fu_code[0]
connect slots_18.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[18].wakeup_ports[3].bits.uop.fu_code[1]
connect slots_18.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[18].wakeup_ports[3].bits.uop.fu_code[2]
connect slots_18.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[18].wakeup_ports[3].bits.uop.fu_code[3]
connect slots_18.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[18].wakeup_ports[3].bits.uop.fu_code[4]
connect slots_18.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[18].wakeup_ports[3].bits.uop.fu_code[5]
connect slots_18.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[18].wakeup_ports[3].bits.uop.fu_code[6]
connect slots_18.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[18].wakeup_ports[3].bits.uop.fu_code[7]
connect slots_18.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[18].wakeup_ports[3].bits.uop.fu_code[8]
connect slots_18.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[18].wakeup_ports[3].bits.uop.fu_code[9]
connect slots_18.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[18].wakeup_ports[3].bits.uop.iq_type[0]
connect slots_18.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[18].wakeup_ports[3].bits.uop.iq_type[1]
connect slots_18.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[18].wakeup_ports[3].bits.uop.iq_type[2]
connect slots_18.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[18].wakeup_ports[3].bits.uop.iq_type[3]
connect slots_18.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[18].wakeup_ports[3].bits.uop.debug_pc
connect slots_18.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[18].wakeup_ports[3].bits.uop.is_rvc
connect slots_18.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[18].wakeup_ports[3].bits.uop.debug_inst
connect slots_18.io.wakeup_ports[3].bits.uop.inst, issue_slots[18].wakeup_ports[3].bits.uop.inst
connect slots_18.io.wakeup_ports[3].valid, issue_slots[18].wakeup_ports[3].valid
connect slots_18.io.squash_grant, issue_slots[18].squash_grant
connect slots_18.io.clear, issue_slots[18].clear
connect slots_18.io.kill, issue_slots[18].kill
connect slots_18.io.brupdate.b2.target_offset, issue_slots[18].brupdate.b2.target_offset
connect slots_18.io.brupdate.b2.jalr_target, issue_slots[18].brupdate.b2.jalr_target
connect slots_18.io.brupdate.b2.pc_sel, issue_slots[18].brupdate.b2.pc_sel
connect slots_18.io.brupdate.b2.cfi_type, issue_slots[18].brupdate.b2.cfi_type
connect slots_18.io.brupdate.b2.taken, issue_slots[18].brupdate.b2.taken
connect slots_18.io.brupdate.b2.mispredict, issue_slots[18].brupdate.b2.mispredict
connect slots_18.io.brupdate.b2.uop.debug_tsrc, issue_slots[18].brupdate.b2.uop.debug_tsrc
connect slots_18.io.brupdate.b2.uop.debug_fsrc, issue_slots[18].brupdate.b2.uop.debug_fsrc
connect slots_18.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[18].brupdate.b2.uop.bp_xcpt_if
connect slots_18.io.brupdate.b2.uop.bp_debug_if, issue_slots[18].brupdate.b2.uop.bp_debug_if
connect slots_18.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[18].brupdate.b2.uop.xcpt_ma_if
connect slots_18.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[18].brupdate.b2.uop.xcpt_ae_if
connect slots_18.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[18].brupdate.b2.uop.xcpt_pf_if
connect slots_18.io.brupdate.b2.uop.fp_typ, issue_slots[18].brupdate.b2.uop.fp_typ
connect slots_18.io.brupdate.b2.uop.fp_rm, issue_slots[18].brupdate.b2.uop.fp_rm
connect slots_18.io.brupdate.b2.uop.fp_val, issue_slots[18].brupdate.b2.uop.fp_val
connect slots_18.io.brupdate.b2.uop.fcn_op, issue_slots[18].brupdate.b2.uop.fcn_op
connect slots_18.io.brupdate.b2.uop.fcn_dw, issue_slots[18].brupdate.b2.uop.fcn_dw
connect slots_18.io.brupdate.b2.uop.frs3_en, issue_slots[18].brupdate.b2.uop.frs3_en
connect slots_18.io.brupdate.b2.uop.lrs2_rtype, issue_slots[18].brupdate.b2.uop.lrs2_rtype
connect slots_18.io.brupdate.b2.uop.lrs1_rtype, issue_slots[18].brupdate.b2.uop.lrs1_rtype
connect slots_18.io.brupdate.b2.uop.dst_rtype, issue_slots[18].brupdate.b2.uop.dst_rtype
connect slots_18.io.brupdate.b2.uop.lrs3, issue_slots[18].brupdate.b2.uop.lrs3
connect slots_18.io.brupdate.b2.uop.lrs2, issue_slots[18].brupdate.b2.uop.lrs2
connect slots_18.io.brupdate.b2.uop.lrs1, issue_slots[18].brupdate.b2.uop.lrs1
connect slots_18.io.brupdate.b2.uop.ldst, issue_slots[18].brupdate.b2.uop.ldst
connect slots_18.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[18].brupdate.b2.uop.ldst_is_rs1
connect slots_18.io.brupdate.b2.uop.csr_cmd, issue_slots[18].brupdate.b2.uop.csr_cmd
connect slots_18.io.brupdate.b2.uop.flush_on_commit, issue_slots[18].brupdate.b2.uop.flush_on_commit
connect slots_18.io.brupdate.b2.uop.is_unique, issue_slots[18].brupdate.b2.uop.is_unique
connect slots_18.io.brupdate.b2.uop.uses_stq, issue_slots[18].brupdate.b2.uop.uses_stq
connect slots_18.io.brupdate.b2.uop.uses_ldq, issue_slots[18].brupdate.b2.uop.uses_ldq
connect slots_18.io.brupdate.b2.uop.mem_signed, issue_slots[18].brupdate.b2.uop.mem_signed
connect slots_18.io.brupdate.b2.uop.mem_size, issue_slots[18].brupdate.b2.uop.mem_size
connect slots_18.io.brupdate.b2.uop.mem_cmd, issue_slots[18].brupdate.b2.uop.mem_cmd
connect slots_18.io.brupdate.b2.uop.exc_cause, issue_slots[18].brupdate.b2.uop.exc_cause
connect slots_18.io.brupdate.b2.uop.exception, issue_slots[18].brupdate.b2.uop.exception
connect slots_18.io.brupdate.b2.uop.stale_pdst, issue_slots[18].brupdate.b2.uop.stale_pdst
connect slots_18.io.brupdate.b2.uop.ppred_busy, issue_slots[18].brupdate.b2.uop.ppred_busy
connect slots_18.io.brupdate.b2.uop.prs3_busy, issue_slots[18].brupdate.b2.uop.prs3_busy
connect slots_18.io.brupdate.b2.uop.prs2_busy, issue_slots[18].brupdate.b2.uop.prs2_busy
connect slots_18.io.brupdate.b2.uop.prs1_busy, issue_slots[18].brupdate.b2.uop.prs1_busy
connect slots_18.io.brupdate.b2.uop.ppred, issue_slots[18].brupdate.b2.uop.ppred
connect slots_18.io.brupdate.b2.uop.prs3, issue_slots[18].brupdate.b2.uop.prs3
connect slots_18.io.brupdate.b2.uop.prs2, issue_slots[18].brupdate.b2.uop.prs2
connect slots_18.io.brupdate.b2.uop.prs1, issue_slots[18].brupdate.b2.uop.prs1
connect slots_18.io.brupdate.b2.uop.pdst, issue_slots[18].brupdate.b2.uop.pdst
connect slots_18.io.brupdate.b2.uop.rxq_idx, issue_slots[18].brupdate.b2.uop.rxq_idx
connect slots_18.io.brupdate.b2.uop.stq_idx, issue_slots[18].brupdate.b2.uop.stq_idx
connect slots_18.io.brupdate.b2.uop.ldq_idx, issue_slots[18].brupdate.b2.uop.ldq_idx
connect slots_18.io.brupdate.b2.uop.rob_idx, issue_slots[18].brupdate.b2.uop.rob_idx
connect slots_18.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[18].brupdate.b2.uop.fp_ctrl.vec
connect slots_18.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[18].brupdate.b2.uop.fp_ctrl.wflags
connect slots_18.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[18].brupdate.b2.uop.fp_ctrl.sqrt
connect slots_18.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[18].brupdate.b2.uop.fp_ctrl.div
connect slots_18.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[18].brupdate.b2.uop.fp_ctrl.fma
connect slots_18.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[18].brupdate.b2.uop.fp_ctrl.fastpipe
connect slots_18.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[18].brupdate.b2.uop.fp_ctrl.toint
connect slots_18.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[18].brupdate.b2.uop.fp_ctrl.fromint
connect slots_18.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[18].brupdate.b2.uop.fp_ctrl.typeTagOut
connect slots_18.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[18].brupdate.b2.uop.fp_ctrl.typeTagIn
connect slots_18.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[18].brupdate.b2.uop.fp_ctrl.swap23
connect slots_18.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[18].brupdate.b2.uop.fp_ctrl.swap12
connect slots_18.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[18].brupdate.b2.uop.fp_ctrl.ren3
connect slots_18.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[18].brupdate.b2.uop.fp_ctrl.ren2
connect slots_18.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[18].brupdate.b2.uop.fp_ctrl.ren1
connect slots_18.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[18].brupdate.b2.uop.fp_ctrl.wen
connect slots_18.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[18].brupdate.b2.uop.fp_ctrl.ldst
connect slots_18.io.brupdate.b2.uop.op2_sel, issue_slots[18].brupdate.b2.uop.op2_sel
connect slots_18.io.brupdate.b2.uop.op1_sel, issue_slots[18].brupdate.b2.uop.op1_sel
connect slots_18.io.brupdate.b2.uop.imm_packed, issue_slots[18].brupdate.b2.uop.imm_packed
connect slots_18.io.brupdate.b2.uop.pimm, issue_slots[18].brupdate.b2.uop.pimm
connect slots_18.io.brupdate.b2.uop.imm_sel, issue_slots[18].brupdate.b2.uop.imm_sel
connect slots_18.io.brupdate.b2.uop.imm_rename, issue_slots[18].brupdate.b2.uop.imm_rename
connect slots_18.io.brupdate.b2.uop.taken, issue_slots[18].brupdate.b2.uop.taken
connect slots_18.io.brupdate.b2.uop.pc_lob, issue_slots[18].brupdate.b2.uop.pc_lob
connect slots_18.io.brupdate.b2.uop.edge_inst, issue_slots[18].brupdate.b2.uop.edge_inst
connect slots_18.io.brupdate.b2.uop.ftq_idx, issue_slots[18].brupdate.b2.uop.ftq_idx
connect slots_18.io.brupdate.b2.uop.is_mov, issue_slots[18].brupdate.b2.uop.is_mov
connect slots_18.io.brupdate.b2.uop.is_rocc, issue_slots[18].brupdate.b2.uop.is_rocc
connect slots_18.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[18].brupdate.b2.uop.is_sys_pc2epc
connect slots_18.io.brupdate.b2.uop.is_eret, issue_slots[18].brupdate.b2.uop.is_eret
connect slots_18.io.brupdate.b2.uop.is_amo, issue_slots[18].brupdate.b2.uop.is_amo
connect slots_18.io.brupdate.b2.uop.is_sfence, issue_slots[18].brupdate.b2.uop.is_sfence
connect slots_18.io.brupdate.b2.uop.is_fencei, issue_slots[18].brupdate.b2.uop.is_fencei
connect slots_18.io.brupdate.b2.uop.is_fence, issue_slots[18].brupdate.b2.uop.is_fence
connect slots_18.io.brupdate.b2.uop.is_sfb, issue_slots[18].brupdate.b2.uop.is_sfb
connect slots_18.io.brupdate.b2.uop.br_type, issue_slots[18].brupdate.b2.uop.br_type
connect slots_18.io.brupdate.b2.uop.br_tag, issue_slots[18].brupdate.b2.uop.br_tag
connect slots_18.io.brupdate.b2.uop.br_mask, issue_slots[18].brupdate.b2.uop.br_mask
connect slots_18.io.brupdate.b2.uop.dis_col_sel, issue_slots[18].brupdate.b2.uop.dis_col_sel
connect slots_18.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[18].brupdate.b2.uop.iw_p3_bypass_hint
connect slots_18.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[18].brupdate.b2.uop.iw_p2_bypass_hint
connect slots_18.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[18].brupdate.b2.uop.iw_p1_bypass_hint
connect slots_18.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[18].brupdate.b2.uop.iw_p2_speculative_child
connect slots_18.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[18].brupdate.b2.uop.iw_p1_speculative_child
connect slots_18.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[18].brupdate.b2.uop.iw_issued_partial_dgen
connect slots_18.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[18].brupdate.b2.uop.iw_issued_partial_agen
connect slots_18.io.brupdate.b2.uop.iw_issued, issue_slots[18].brupdate.b2.uop.iw_issued
connect slots_18.io.brupdate.b2.uop.fu_code[0], issue_slots[18].brupdate.b2.uop.fu_code[0]
connect slots_18.io.brupdate.b2.uop.fu_code[1], issue_slots[18].brupdate.b2.uop.fu_code[1]
connect slots_18.io.brupdate.b2.uop.fu_code[2], issue_slots[18].brupdate.b2.uop.fu_code[2]
connect slots_18.io.brupdate.b2.uop.fu_code[3], issue_slots[18].brupdate.b2.uop.fu_code[3]
connect slots_18.io.brupdate.b2.uop.fu_code[4], issue_slots[18].brupdate.b2.uop.fu_code[4]
connect slots_18.io.brupdate.b2.uop.fu_code[5], issue_slots[18].brupdate.b2.uop.fu_code[5]
connect slots_18.io.brupdate.b2.uop.fu_code[6], issue_slots[18].brupdate.b2.uop.fu_code[6]
connect slots_18.io.brupdate.b2.uop.fu_code[7], issue_slots[18].brupdate.b2.uop.fu_code[7]
connect slots_18.io.brupdate.b2.uop.fu_code[8], issue_slots[18].brupdate.b2.uop.fu_code[8]
connect slots_18.io.brupdate.b2.uop.fu_code[9], issue_slots[18].brupdate.b2.uop.fu_code[9]
connect slots_18.io.brupdate.b2.uop.iq_type[0], issue_slots[18].brupdate.b2.uop.iq_type[0]
connect slots_18.io.brupdate.b2.uop.iq_type[1], issue_slots[18].brupdate.b2.uop.iq_type[1]
connect slots_18.io.brupdate.b2.uop.iq_type[2], issue_slots[18].brupdate.b2.uop.iq_type[2]
connect slots_18.io.brupdate.b2.uop.iq_type[3], issue_slots[18].brupdate.b2.uop.iq_type[3]
connect slots_18.io.brupdate.b2.uop.debug_pc, issue_slots[18].brupdate.b2.uop.debug_pc
connect slots_18.io.brupdate.b2.uop.is_rvc, issue_slots[18].brupdate.b2.uop.is_rvc
connect slots_18.io.brupdate.b2.uop.debug_inst, issue_slots[18].brupdate.b2.uop.debug_inst
connect slots_18.io.brupdate.b2.uop.inst, issue_slots[18].brupdate.b2.uop.inst
connect slots_18.io.brupdate.b1.mispredict_mask, issue_slots[18].brupdate.b1.mispredict_mask
connect slots_18.io.brupdate.b1.resolve_mask, issue_slots[18].brupdate.b1.resolve_mask
connect issue_slots[18].out_uop.debug_tsrc, slots_18.io.out_uop.debug_tsrc
connect issue_slots[18].out_uop.debug_fsrc, slots_18.io.out_uop.debug_fsrc
connect issue_slots[18].out_uop.bp_xcpt_if, slots_18.io.out_uop.bp_xcpt_if
connect issue_slots[18].out_uop.bp_debug_if, slots_18.io.out_uop.bp_debug_if
connect issue_slots[18].out_uop.xcpt_ma_if, slots_18.io.out_uop.xcpt_ma_if
connect issue_slots[18].out_uop.xcpt_ae_if, slots_18.io.out_uop.xcpt_ae_if
connect issue_slots[18].out_uop.xcpt_pf_if, slots_18.io.out_uop.xcpt_pf_if
connect issue_slots[18].out_uop.fp_typ, slots_18.io.out_uop.fp_typ
connect issue_slots[18].out_uop.fp_rm, slots_18.io.out_uop.fp_rm
connect issue_slots[18].out_uop.fp_val, slots_18.io.out_uop.fp_val
connect issue_slots[18].out_uop.fcn_op, slots_18.io.out_uop.fcn_op
connect issue_slots[18].out_uop.fcn_dw, slots_18.io.out_uop.fcn_dw
connect issue_slots[18].out_uop.frs3_en, slots_18.io.out_uop.frs3_en
connect issue_slots[18].out_uop.lrs2_rtype, slots_18.io.out_uop.lrs2_rtype
connect issue_slots[18].out_uop.lrs1_rtype, slots_18.io.out_uop.lrs1_rtype
connect issue_slots[18].out_uop.dst_rtype, slots_18.io.out_uop.dst_rtype
connect issue_slots[18].out_uop.lrs3, slots_18.io.out_uop.lrs3
connect issue_slots[18].out_uop.lrs2, slots_18.io.out_uop.lrs2
connect issue_slots[18].out_uop.lrs1, slots_18.io.out_uop.lrs1
connect issue_slots[18].out_uop.ldst, slots_18.io.out_uop.ldst
connect issue_slots[18].out_uop.ldst_is_rs1, slots_18.io.out_uop.ldst_is_rs1
connect issue_slots[18].out_uop.csr_cmd, slots_18.io.out_uop.csr_cmd
connect issue_slots[18].out_uop.flush_on_commit, slots_18.io.out_uop.flush_on_commit
connect issue_slots[18].out_uop.is_unique, slots_18.io.out_uop.is_unique
connect issue_slots[18].out_uop.uses_stq, slots_18.io.out_uop.uses_stq
connect issue_slots[18].out_uop.uses_ldq, slots_18.io.out_uop.uses_ldq
connect issue_slots[18].out_uop.mem_signed, slots_18.io.out_uop.mem_signed
connect issue_slots[18].out_uop.mem_size, slots_18.io.out_uop.mem_size
connect issue_slots[18].out_uop.mem_cmd, slots_18.io.out_uop.mem_cmd
connect issue_slots[18].out_uop.exc_cause, slots_18.io.out_uop.exc_cause
connect issue_slots[18].out_uop.exception, slots_18.io.out_uop.exception
connect issue_slots[18].out_uop.stale_pdst, slots_18.io.out_uop.stale_pdst
connect issue_slots[18].out_uop.ppred_busy, slots_18.io.out_uop.ppred_busy
connect issue_slots[18].out_uop.prs3_busy, slots_18.io.out_uop.prs3_busy
connect issue_slots[18].out_uop.prs2_busy, slots_18.io.out_uop.prs2_busy
connect issue_slots[18].out_uop.prs1_busy, slots_18.io.out_uop.prs1_busy
connect issue_slots[18].out_uop.ppred, slots_18.io.out_uop.ppred
connect issue_slots[18].out_uop.prs3, slots_18.io.out_uop.prs3
connect issue_slots[18].out_uop.prs2, slots_18.io.out_uop.prs2
connect issue_slots[18].out_uop.prs1, slots_18.io.out_uop.prs1
connect issue_slots[18].out_uop.pdst, slots_18.io.out_uop.pdst
connect issue_slots[18].out_uop.rxq_idx, slots_18.io.out_uop.rxq_idx
connect issue_slots[18].out_uop.stq_idx, slots_18.io.out_uop.stq_idx
connect issue_slots[18].out_uop.ldq_idx, slots_18.io.out_uop.ldq_idx
connect issue_slots[18].out_uop.rob_idx, slots_18.io.out_uop.rob_idx
connect issue_slots[18].out_uop.fp_ctrl.vec, slots_18.io.out_uop.fp_ctrl.vec
connect issue_slots[18].out_uop.fp_ctrl.wflags, slots_18.io.out_uop.fp_ctrl.wflags
connect issue_slots[18].out_uop.fp_ctrl.sqrt, slots_18.io.out_uop.fp_ctrl.sqrt
connect issue_slots[18].out_uop.fp_ctrl.div, slots_18.io.out_uop.fp_ctrl.div
connect issue_slots[18].out_uop.fp_ctrl.fma, slots_18.io.out_uop.fp_ctrl.fma
connect issue_slots[18].out_uop.fp_ctrl.fastpipe, slots_18.io.out_uop.fp_ctrl.fastpipe
connect issue_slots[18].out_uop.fp_ctrl.toint, slots_18.io.out_uop.fp_ctrl.toint
connect issue_slots[18].out_uop.fp_ctrl.fromint, slots_18.io.out_uop.fp_ctrl.fromint
connect issue_slots[18].out_uop.fp_ctrl.typeTagOut, slots_18.io.out_uop.fp_ctrl.typeTagOut
connect issue_slots[18].out_uop.fp_ctrl.typeTagIn, slots_18.io.out_uop.fp_ctrl.typeTagIn
connect issue_slots[18].out_uop.fp_ctrl.swap23, slots_18.io.out_uop.fp_ctrl.swap23
connect issue_slots[18].out_uop.fp_ctrl.swap12, slots_18.io.out_uop.fp_ctrl.swap12
connect issue_slots[18].out_uop.fp_ctrl.ren3, slots_18.io.out_uop.fp_ctrl.ren3
connect issue_slots[18].out_uop.fp_ctrl.ren2, slots_18.io.out_uop.fp_ctrl.ren2
connect issue_slots[18].out_uop.fp_ctrl.ren1, slots_18.io.out_uop.fp_ctrl.ren1
connect issue_slots[18].out_uop.fp_ctrl.wen, slots_18.io.out_uop.fp_ctrl.wen
connect issue_slots[18].out_uop.fp_ctrl.ldst, slots_18.io.out_uop.fp_ctrl.ldst
connect issue_slots[18].out_uop.op2_sel, slots_18.io.out_uop.op2_sel
connect issue_slots[18].out_uop.op1_sel, slots_18.io.out_uop.op1_sel
connect issue_slots[18].out_uop.imm_packed, slots_18.io.out_uop.imm_packed
connect issue_slots[18].out_uop.pimm, slots_18.io.out_uop.pimm
connect issue_slots[18].out_uop.imm_sel, slots_18.io.out_uop.imm_sel
connect issue_slots[18].out_uop.imm_rename, slots_18.io.out_uop.imm_rename
connect issue_slots[18].out_uop.taken, slots_18.io.out_uop.taken
connect issue_slots[18].out_uop.pc_lob, slots_18.io.out_uop.pc_lob
connect issue_slots[18].out_uop.edge_inst, slots_18.io.out_uop.edge_inst
connect issue_slots[18].out_uop.ftq_idx, slots_18.io.out_uop.ftq_idx
connect issue_slots[18].out_uop.is_mov, slots_18.io.out_uop.is_mov
connect issue_slots[18].out_uop.is_rocc, slots_18.io.out_uop.is_rocc
connect issue_slots[18].out_uop.is_sys_pc2epc, slots_18.io.out_uop.is_sys_pc2epc
connect issue_slots[18].out_uop.is_eret, slots_18.io.out_uop.is_eret
connect issue_slots[18].out_uop.is_amo, slots_18.io.out_uop.is_amo
connect issue_slots[18].out_uop.is_sfence, slots_18.io.out_uop.is_sfence
connect issue_slots[18].out_uop.is_fencei, slots_18.io.out_uop.is_fencei
connect issue_slots[18].out_uop.is_fence, slots_18.io.out_uop.is_fence
connect issue_slots[18].out_uop.is_sfb, slots_18.io.out_uop.is_sfb
connect issue_slots[18].out_uop.br_type, slots_18.io.out_uop.br_type
connect issue_slots[18].out_uop.br_tag, slots_18.io.out_uop.br_tag
connect issue_slots[18].out_uop.br_mask, slots_18.io.out_uop.br_mask
connect issue_slots[18].out_uop.dis_col_sel, slots_18.io.out_uop.dis_col_sel
connect issue_slots[18].out_uop.iw_p3_bypass_hint, slots_18.io.out_uop.iw_p3_bypass_hint
connect issue_slots[18].out_uop.iw_p2_bypass_hint, slots_18.io.out_uop.iw_p2_bypass_hint
connect issue_slots[18].out_uop.iw_p1_bypass_hint, slots_18.io.out_uop.iw_p1_bypass_hint
connect issue_slots[18].out_uop.iw_p2_speculative_child, slots_18.io.out_uop.iw_p2_speculative_child
connect issue_slots[18].out_uop.iw_p1_speculative_child, slots_18.io.out_uop.iw_p1_speculative_child
connect issue_slots[18].out_uop.iw_issued_partial_dgen, slots_18.io.out_uop.iw_issued_partial_dgen
connect issue_slots[18].out_uop.iw_issued_partial_agen, slots_18.io.out_uop.iw_issued_partial_agen
connect issue_slots[18].out_uop.iw_issued, slots_18.io.out_uop.iw_issued
connect issue_slots[18].out_uop.fu_code[0], slots_18.io.out_uop.fu_code[0]
connect issue_slots[18].out_uop.fu_code[1], slots_18.io.out_uop.fu_code[1]
connect issue_slots[18].out_uop.fu_code[2], slots_18.io.out_uop.fu_code[2]
connect issue_slots[18].out_uop.fu_code[3], slots_18.io.out_uop.fu_code[3]
connect issue_slots[18].out_uop.fu_code[4], slots_18.io.out_uop.fu_code[4]
connect issue_slots[18].out_uop.fu_code[5], slots_18.io.out_uop.fu_code[5]
connect issue_slots[18].out_uop.fu_code[6], slots_18.io.out_uop.fu_code[6]
connect issue_slots[18].out_uop.fu_code[7], slots_18.io.out_uop.fu_code[7]
connect issue_slots[18].out_uop.fu_code[8], slots_18.io.out_uop.fu_code[8]
connect issue_slots[18].out_uop.fu_code[9], slots_18.io.out_uop.fu_code[9]
connect issue_slots[18].out_uop.iq_type[0], slots_18.io.out_uop.iq_type[0]
connect issue_slots[18].out_uop.iq_type[1], slots_18.io.out_uop.iq_type[1]
connect issue_slots[18].out_uop.iq_type[2], slots_18.io.out_uop.iq_type[2]
connect issue_slots[18].out_uop.iq_type[3], slots_18.io.out_uop.iq_type[3]
connect issue_slots[18].out_uop.debug_pc, slots_18.io.out_uop.debug_pc
connect issue_slots[18].out_uop.is_rvc, slots_18.io.out_uop.is_rvc
connect issue_slots[18].out_uop.debug_inst, slots_18.io.out_uop.debug_inst
connect issue_slots[18].out_uop.inst, slots_18.io.out_uop.inst
connect slots_18.io.in_uop.bits.debug_tsrc, issue_slots[18].in_uop.bits.debug_tsrc
connect slots_18.io.in_uop.bits.debug_fsrc, issue_slots[18].in_uop.bits.debug_fsrc
connect slots_18.io.in_uop.bits.bp_xcpt_if, issue_slots[18].in_uop.bits.bp_xcpt_if
connect slots_18.io.in_uop.bits.bp_debug_if, issue_slots[18].in_uop.bits.bp_debug_if
connect slots_18.io.in_uop.bits.xcpt_ma_if, issue_slots[18].in_uop.bits.xcpt_ma_if
connect slots_18.io.in_uop.bits.xcpt_ae_if, issue_slots[18].in_uop.bits.xcpt_ae_if
connect slots_18.io.in_uop.bits.xcpt_pf_if, issue_slots[18].in_uop.bits.xcpt_pf_if
connect slots_18.io.in_uop.bits.fp_typ, issue_slots[18].in_uop.bits.fp_typ
connect slots_18.io.in_uop.bits.fp_rm, issue_slots[18].in_uop.bits.fp_rm
connect slots_18.io.in_uop.bits.fp_val, issue_slots[18].in_uop.bits.fp_val
connect slots_18.io.in_uop.bits.fcn_op, issue_slots[18].in_uop.bits.fcn_op
connect slots_18.io.in_uop.bits.fcn_dw, issue_slots[18].in_uop.bits.fcn_dw
connect slots_18.io.in_uop.bits.frs3_en, issue_slots[18].in_uop.bits.frs3_en
connect slots_18.io.in_uop.bits.lrs2_rtype, issue_slots[18].in_uop.bits.lrs2_rtype
connect slots_18.io.in_uop.bits.lrs1_rtype, issue_slots[18].in_uop.bits.lrs1_rtype
connect slots_18.io.in_uop.bits.dst_rtype, issue_slots[18].in_uop.bits.dst_rtype
connect slots_18.io.in_uop.bits.lrs3, issue_slots[18].in_uop.bits.lrs3
connect slots_18.io.in_uop.bits.lrs2, issue_slots[18].in_uop.bits.lrs2
connect slots_18.io.in_uop.bits.lrs1, issue_slots[18].in_uop.bits.lrs1
connect slots_18.io.in_uop.bits.ldst, issue_slots[18].in_uop.bits.ldst
connect slots_18.io.in_uop.bits.ldst_is_rs1, issue_slots[18].in_uop.bits.ldst_is_rs1
connect slots_18.io.in_uop.bits.csr_cmd, issue_slots[18].in_uop.bits.csr_cmd
connect slots_18.io.in_uop.bits.flush_on_commit, issue_slots[18].in_uop.bits.flush_on_commit
connect slots_18.io.in_uop.bits.is_unique, issue_slots[18].in_uop.bits.is_unique
connect slots_18.io.in_uop.bits.uses_stq, issue_slots[18].in_uop.bits.uses_stq
connect slots_18.io.in_uop.bits.uses_ldq, issue_slots[18].in_uop.bits.uses_ldq
connect slots_18.io.in_uop.bits.mem_signed, issue_slots[18].in_uop.bits.mem_signed
connect slots_18.io.in_uop.bits.mem_size, issue_slots[18].in_uop.bits.mem_size
connect slots_18.io.in_uop.bits.mem_cmd, issue_slots[18].in_uop.bits.mem_cmd
connect slots_18.io.in_uop.bits.exc_cause, issue_slots[18].in_uop.bits.exc_cause
connect slots_18.io.in_uop.bits.exception, issue_slots[18].in_uop.bits.exception
connect slots_18.io.in_uop.bits.stale_pdst, issue_slots[18].in_uop.bits.stale_pdst
connect slots_18.io.in_uop.bits.ppred_busy, issue_slots[18].in_uop.bits.ppred_busy
connect slots_18.io.in_uop.bits.prs3_busy, issue_slots[18].in_uop.bits.prs3_busy
connect slots_18.io.in_uop.bits.prs2_busy, issue_slots[18].in_uop.bits.prs2_busy
connect slots_18.io.in_uop.bits.prs1_busy, issue_slots[18].in_uop.bits.prs1_busy
connect slots_18.io.in_uop.bits.ppred, issue_slots[18].in_uop.bits.ppred
connect slots_18.io.in_uop.bits.prs3, issue_slots[18].in_uop.bits.prs3
connect slots_18.io.in_uop.bits.prs2, issue_slots[18].in_uop.bits.prs2
connect slots_18.io.in_uop.bits.prs1, issue_slots[18].in_uop.bits.prs1
connect slots_18.io.in_uop.bits.pdst, issue_slots[18].in_uop.bits.pdst
connect slots_18.io.in_uop.bits.rxq_idx, issue_slots[18].in_uop.bits.rxq_idx
connect slots_18.io.in_uop.bits.stq_idx, issue_slots[18].in_uop.bits.stq_idx
connect slots_18.io.in_uop.bits.ldq_idx, issue_slots[18].in_uop.bits.ldq_idx
connect slots_18.io.in_uop.bits.rob_idx, issue_slots[18].in_uop.bits.rob_idx
connect slots_18.io.in_uop.bits.fp_ctrl.vec, issue_slots[18].in_uop.bits.fp_ctrl.vec
connect slots_18.io.in_uop.bits.fp_ctrl.wflags, issue_slots[18].in_uop.bits.fp_ctrl.wflags
connect slots_18.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[18].in_uop.bits.fp_ctrl.sqrt
connect slots_18.io.in_uop.bits.fp_ctrl.div, issue_slots[18].in_uop.bits.fp_ctrl.div
connect slots_18.io.in_uop.bits.fp_ctrl.fma, issue_slots[18].in_uop.bits.fp_ctrl.fma
connect slots_18.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[18].in_uop.bits.fp_ctrl.fastpipe
connect slots_18.io.in_uop.bits.fp_ctrl.toint, issue_slots[18].in_uop.bits.fp_ctrl.toint
connect slots_18.io.in_uop.bits.fp_ctrl.fromint, issue_slots[18].in_uop.bits.fp_ctrl.fromint
connect slots_18.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[18].in_uop.bits.fp_ctrl.typeTagOut
connect slots_18.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[18].in_uop.bits.fp_ctrl.typeTagIn
connect slots_18.io.in_uop.bits.fp_ctrl.swap23, issue_slots[18].in_uop.bits.fp_ctrl.swap23
connect slots_18.io.in_uop.bits.fp_ctrl.swap12, issue_slots[18].in_uop.bits.fp_ctrl.swap12
connect slots_18.io.in_uop.bits.fp_ctrl.ren3, issue_slots[18].in_uop.bits.fp_ctrl.ren3
connect slots_18.io.in_uop.bits.fp_ctrl.ren2, issue_slots[18].in_uop.bits.fp_ctrl.ren2
connect slots_18.io.in_uop.bits.fp_ctrl.ren1, issue_slots[18].in_uop.bits.fp_ctrl.ren1
connect slots_18.io.in_uop.bits.fp_ctrl.wen, issue_slots[18].in_uop.bits.fp_ctrl.wen
connect slots_18.io.in_uop.bits.fp_ctrl.ldst, issue_slots[18].in_uop.bits.fp_ctrl.ldst
connect slots_18.io.in_uop.bits.op2_sel, issue_slots[18].in_uop.bits.op2_sel
connect slots_18.io.in_uop.bits.op1_sel, issue_slots[18].in_uop.bits.op1_sel
connect slots_18.io.in_uop.bits.imm_packed, issue_slots[18].in_uop.bits.imm_packed
connect slots_18.io.in_uop.bits.pimm, issue_slots[18].in_uop.bits.pimm
connect slots_18.io.in_uop.bits.imm_sel, issue_slots[18].in_uop.bits.imm_sel
connect slots_18.io.in_uop.bits.imm_rename, issue_slots[18].in_uop.bits.imm_rename
connect slots_18.io.in_uop.bits.taken, issue_slots[18].in_uop.bits.taken
connect slots_18.io.in_uop.bits.pc_lob, issue_slots[18].in_uop.bits.pc_lob
connect slots_18.io.in_uop.bits.edge_inst, issue_slots[18].in_uop.bits.edge_inst
connect slots_18.io.in_uop.bits.ftq_idx, issue_slots[18].in_uop.bits.ftq_idx
connect slots_18.io.in_uop.bits.is_mov, issue_slots[18].in_uop.bits.is_mov
connect slots_18.io.in_uop.bits.is_rocc, issue_slots[18].in_uop.bits.is_rocc
connect slots_18.io.in_uop.bits.is_sys_pc2epc, issue_slots[18].in_uop.bits.is_sys_pc2epc
connect slots_18.io.in_uop.bits.is_eret, issue_slots[18].in_uop.bits.is_eret
connect slots_18.io.in_uop.bits.is_amo, issue_slots[18].in_uop.bits.is_amo
connect slots_18.io.in_uop.bits.is_sfence, issue_slots[18].in_uop.bits.is_sfence
connect slots_18.io.in_uop.bits.is_fencei, issue_slots[18].in_uop.bits.is_fencei
connect slots_18.io.in_uop.bits.is_fence, issue_slots[18].in_uop.bits.is_fence
connect slots_18.io.in_uop.bits.is_sfb, issue_slots[18].in_uop.bits.is_sfb
connect slots_18.io.in_uop.bits.br_type, issue_slots[18].in_uop.bits.br_type
connect slots_18.io.in_uop.bits.br_tag, issue_slots[18].in_uop.bits.br_tag
connect slots_18.io.in_uop.bits.br_mask, issue_slots[18].in_uop.bits.br_mask
connect slots_18.io.in_uop.bits.dis_col_sel, issue_slots[18].in_uop.bits.dis_col_sel
connect slots_18.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[18].in_uop.bits.iw_p3_bypass_hint
connect slots_18.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[18].in_uop.bits.iw_p2_bypass_hint
connect slots_18.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[18].in_uop.bits.iw_p1_bypass_hint
connect slots_18.io.in_uop.bits.iw_p2_speculative_child, issue_slots[18].in_uop.bits.iw_p2_speculative_child
connect slots_18.io.in_uop.bits.iw_p1_speculative_child, issue_slots[18].in_uop.bits.iw_p1_speculative_child
connect slots_18.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[18].in_uop.bits.iw_issued_partial_dgen
connect slots_18.io.in_uop.bits.iw_issued_partial_agen, issue_slots[18].in_uop.bits.iw_issued_partial_agen
connect slots_18.io.in_uop.bits.iw_issued, issue_slots[18].in_uop.bits.iw_issued
connect slots_18.io.in_uop.bits.fu_code[0], issue_slots[18].in_uop.bits.fu_code[0]
connect slots_18.io.in_uop.bits.fu_code[1], issue_slots[18].in_uop.bits.fu_code[1]
connect slots_18.io.in_uop.bits.fu_code[2], issue_slots[18].in_uop.bits.fu_code[2]
connect slots_18.io.in_uop.bits.fu_code[3], issue_slots[18].in_uop.bits.fu_code[3]
connect slots_18.io.in_uop.bits.fu_code[4], issue_slots[18].in_uop.bits.fu_code[4]
connect slots_18.io.in_uop.bits.fu_code[5], issue_slots[18].in_uop.bits.fu_code[5]
connect slots_18.io.in_uop.bits.fu_code[6], issue_slots[18].in_uop.bits.fu_code[6]
connect slots_18.io.in_uop.bits.fu_code[7], issue_slots[18].in_uop.bits.fu_code[7]
connect slots_18.io.in_uop.bits.fu_code[8], issue_slots[18].in_uop.bits.fu_code[8]
connect slots_18.io.in_uop.bits.fu_code[9], issue_slots[18].in_uop.bits.fu_code[9]
connect slots_18.io.in_uop.bits.iq_type[0], issue_slots[18].in_uop.bits.iq_type[0]
connect slots_18.io.in_uop.bits.iq_type[1], issue_slots[18].in_uop.bits.iq_type[1]
connect slots_18.io.in_uop.bits.iq_type[2], issue_slots[18].in_uop.bits.iq_type[2]
connect slots_18.io.in_uop.bits.iq_type[3], issue_slots[18].in_uop.bits.iq_type[3]
connect slots_18.io.in_uop.bits.debug_pc, issue_slots[18].in_uop.bits.debug_pc
connect slots_18.io.in_uop.bits.is_rvc, issue_slots[18].in_uop.bits.is_rvc
connect slots_18.io.in_uop.bits.debug_inst, issue_slots[18].in_uop.bits.debug_inst
connect slots_18.io.in_uop.bits.inst, issue_slots[18].in_uop.bits.inst
connect slots_18.io.in_uop.valid, issue_slots[18].in_uop.valid
connect issue_slots[18].iss_uop.debug_tsrc, slots_18.io.iss_uop.debug_tsrc
connect issue_slots[18].iss_uop.debug_fsrc, slots_18.io.iss_uop.debug_fsrc
connect issue_slots[18].iss_uop.bp_xcpt_if, slots_18.io.iss_uop.bp_xcpt_if
connect issue_slots[18].iss_uop.bp_debug_if, slots_18.io.iss_uop.bp_debug_if
connect issue_slots[18].iss_uop.xcpt_ma_if, slots_18.io.iss_uop.xcpt_ma_if
connect issue_slots[18].iss_uop.xcpt_ae_if, slots_18.io.iss_uop.xcpt_ae_if
connect issue_slots[18].iss_uop.xcpt_pf_if, slots_18.io.iss_uop.xcpt_pf_if
connect issue_slots[18].iss_uop.fp_typ, slots_18.io.iss_uop.fp_typ
connect issue_slots[18].iss_uop.fp_rm, slots_18.io.iss_uop.fp_rm
connect issue_slots[18].iss_uop.fp_val, slots_18.io.iss_uop.fp_val
connect issue_slots[18].iss_uop.fcn_op, slots_18.io.iss_uop.fcn_op
connect issue_slots[18].iss_uop.fcn_dw, slots_18.io.iss_uop.fcn_dw
connect issue_slots[18].iss_uop.frs3_en, slots_18.io.iss_uop.frs3_en
connect issue_slots[18].iss_uop.lrs2_rtype, slots_18.io.iss_uop.lrs2_rtype
connect issue_slots[18].iss_uop.lrs1_rtype, slots_18.io.iss_uop.lrs1_rtype
connect issue_slots[18].iss_uop.dst_rtype, slots_18.io.iss_uop.dst_rtype
connect issue_slots[18].iss_uop.lrs3, slots_18.io.iss_uop.lrs3
connect issue_slots[18].iss_uop.lrs2, slots_18.io.iss_uop.lrs2
connect issue_slots[18].iss_uop.lrs1, slots_18.io.iss_uop.lrs1
connect issue_slots[18].iss_uop.ldst, slots_18.io.iss_uop.ldst
connect issue_slots[18].iss_uop.ldst_is_rs1, slots_18.io.iss_uop.ldst_is_rs1
connect issue_slots[18].iss_uop.csr_cmd, slots_18.io.iss_uop.csr_cmd
connect issue_slots[18].iss_uop.flush_on_commit, slots_18.io.iss_uop.flush_on_commit
connect issue_slots[18].iss_uop.is_unique, slots_18.io.iss_uop.is_unique
connect issue_slots[18].iss_uop.uses_stq, slots_18.io.iss_uop.uses_stq
connect issue_slots[18].iss_uop.uses_ldq, slots_18.io.iss_uop.uses_ldq
connect issue_slots[18].iss_uop.mem_signed, slots_18.io.iss_uop.mem_signed
connect issue_slots[18].iss_uop.mem_size, slots_18.io.iss_uop.mem_size
connect issue_slots[18].iss_uop.mem_cmd, slots_18.io.iss_uop.mem_cmd
connect issue_slots[18].iss_uop.exc_cause, slots_18.io.iss_uop.exc_cause
connect issue_slots[18].iss_uop.exception, slots_18.io.iss_uop.exception
connect issue_slots[18].iss_uop.stale_pdst, slots_18.io.iss_uop.stale_pdst
connect issue_slots[18].iss_uop.ppred_busy, slots_18.io.iss_uop.ppred_busy
connect issue_slots[18].iss_uop.prs3_busy, slots_18.io.iss_uop.prs3_busy
connect issue_slots[18].iss_uop.prs2_busy, slots_18.io.iss_uop.prs2_busy
connect issue_slots[18].iss_uop.prs1_busy, slots_18.io.iss_uop.prs1_busy
connect issue_slots[18].iss_uop.ppred, slots_18.io.iss_uop.ppred
connect issue_slots[18].iss_uop.prs3, slots_18.io.iss_uop.prs3
connect issue_slots[18].iss_uop.prs2, slots_18.io.iss_uop.prs2
connect issue_slots[18].iss_uop.prs1, slots_18.io.iss_uop.prs1
connect issue_slots[18].iss_uop.pdst, slots_18.io.iss_uop.pdst
connect issue_slots[18].iss_uop.rxq_idx, slots_18.io.iss_uop.rxq_idx
connect issue_slots[18].iss_uop.stq_idx, slots_18.io.iss_uop.stq_idx
connect issue_slots[18].iss_uop.ldq_idx, slots_18.io.iss_uop.ldq_idx
connect issue_slots[18].iss_uop.rob_idx, slots_18.io.iss_uop.rob_idx
connect issue_slots[18].iss_uop.fp_ctrl.vec, slots_18.io.iss_uop.fp_ctrl.vec
connect issue_slots[18].iss_uop.fp_ctrl.wflags, slots_18.io.iss_uop.fp_ctrl.wflags
connect issue_slots[18].iss_uop.fp_ctrl.sqrt, slots_18.io.iss_uop.fp_ctrl.sqrt
connect issue_slots[18].iss_uop.fp_ctrl.div, slots_18.io.iss_uop.fp_ctrl.div
connect issue_slots[18].iss_uop.fp_ctrl.fma, slots_18.io.iss_uop.fp_ctrl.fma
connect issue_slots[18].iss_uop.fp_ctrl.fastpipe, slots_18.io.iss_uop.fp_ctrl.fastpipe
connect issue_slots[18].iss_uop.fp_ctrl.toint, slots_18.io.iss_uop.fp_ctrl.toint
connect issue_slots[18].iss_uop.fp_ctrl.fromint, slots_18.io.iss_uop.fp_ctrl.fromint
connect issue_slots[18].iss_uop.fp_ctrl.typeTagOut, slots_18.io.iss_uop.fp_ctrl.typeTagOut
connect issue_slots[18].iss_uop.fp_ctrl.typeTagIn, slots_18.io.iss_uop.fp_ctrl.typeTagIn
connect issue_slots[18].iss_uop.fp_ctrl.swap23, slots_18.io.iss_uop.fp_ctrl.swap23
connect issue_slots[18].iss_uop.fp_ctrl.swap12, slots_18.io.iss_uop.fp_ctrl.swap12
connect issue_slots[18].iss_uop.fp_ctrl.ren3, slots_18.io.iss_uop.fp_ctrl.ren3
connect issue_slots[18].iss_uop.fp_ctrl.ren2, slots_18.io.iss_uop.fp_ctrl.ren2
connect issue_slots[18].iss_uop.fp_ctrl.ren1, slots_18.io.iss_uop.fp_ctrl.ren1
connect issue_slots[18].iss_uop.fp_ctrl.wen, slots_18.io.iss_uop.fp_ctrl.wen
connect issue_slots[18].iss_uop.fp_ctrl.ldst, slots_18.io.iss_uop.fp_ctrl.ldst
connect issue_slots[18].iss_uop.op2_sel, slots_18.io.iss_uop.op2_sel
connect issue_slots[18].iss_uop.op1_sel, slots_18.io.iss_uop.op1_sel
connect issue_slots[18].iss_uop.imm_packed, slots_18.io.iss_uop.imm_packed
connect issue_slots[18].iss_uop.pimm, slots_18.io.iss_uop.pimm
connect issue_slots[18].iss_uop.imm_sel, slots_18.io.iss_uop.imm_sel
connect issue_slots[18].iss_uop.imm_rename, slots_18.io.iss_uop.imm_rename
connect issue_slots[18].iss_uop.taken, slots_18.io.iss_uop.taken
connect issue_slots[18].iss_uop.pc_lob, slots_18.io.iss_uop.pc_lob
connect issue_slots[18].iss_uop.edge_inst, slots_18.io.iss_uop.edge_inst
connect issue_slots[18].iss_uop.ftq_idx, slots_18.io.iss_uop.ftq_idx
connect issue_slots[18].iss_uop.is_mov, slots_18.io.iss_uop.is_mov
connect issue_slots[18].iss_uop.is_rocc, slots_18.io.iss_uop.is_rocc
connect issue_slots[18].iss_uop.is_sys_pc2epc, slots_18.io.iss_uop.is_sys_pc2epc
connect issue_slots[18].iss_uop.is_eret, slots_18.io.iss_uop.is_eret
connect issue_slots[18].iss_uop.is_amo, slots_18.io.iss_uop.is_amo
connect issue_slots[18].iss_uop.is_sfence, slots_18.io.iss_uop.is_sfence
connect issue_slots[18].iss_uop.is_fencei, slots_18.io.iss_uop.is_fencei
connect issue_slots[18].iss_uop.is_fence, slots_18.io.iss_uop.is_fence
connect issue_slots[18].iss_uop.is_sfb, slots_18.io.iss_uop.is_sfb
connect issue_slots[18].iss_uop.br_type, slots_18.io.iss_uop.br_type
connect issue_slots[18].iss_uop.br_tag, slots_18.io.iss_uop.br_tag
connect issue_slots[18].iss_uop.br_mask, slots_18.io.iss_uop.br_mask
connect issue_slots[18].iss_uop.dis_col_sel, slots_18.io.iss_uop.dis_col_sel
connect issue_slots[18].iss_uop.iw_p3_bypass_hint, slots_18.io.iss_uop.iw_p3_bypass_hint
connect issue_slots[18].iss_uop.iw_p2_bypass_hint, slots_18.io.iss_uop.iw_p2_bypass_hint
connect issue_slots[18].iss_uop.iw_p1_bypass_hint, slots_18.io.iss_uop.iw_p1_bypass_hint
connect issue_slots[18].iss_uop.iw_p2_speculative_child, slots_18.io.iss_uop.iw_p2_speculative_child
connect issue_slots[18].iss_uop.iw_p1_speculative_child, slots_18.io.iss_uop.iw_p1_speculative_child
connect issue_slots[18].iss_uop.iw_issued_partial_dgen, slots_18.io.iss_uop.iw_issued_partial_dgen
connect issue_slots[18].iss_uop.iw_issued_partial_agen, slots_18.io.iss_uop.iw_issued_partial_agen
connect issue_slots[18].iss_uop.iw_issued, slots_18.io.iss_uop.iw_issued
connect issue_slots[18].iss_uop.fu_code[0], slots_18.io.iss_uop.fu_code[0]
connect issue_slots[18].iss_uop.fu_code[1], slots_18.io.iss_uop.fu_code[1]
connect issue_slots[18].iss_uop.fu_code[2], slots_18.io.iss_uop.fu_code[2]
connect issue_slots[18].iss_uop.fu_code[3], slots_18.io.iss_uop.fu_code[3]
connect issue_slots[18].iss_uop.fu_code[4], slots_18.io.iss_uop.fu_code[4]
connect issue_slots[18].iss_uop.fu_code[5], slots_18.io.iss_uop.fu_code[5]
connect issue_slots[18].iss_uop.fu_code[6], slots_18.io.iss_uop.fu_code[6]
connect issue_slots[18].iss_uop.fu_code[7], slots_18.io.iss_uop.fu_code[7]
connect issue_slots[18].iss_uop.fu_code[8], slots_18.io.iss_uop.fu_code[8]
connect issue_slots[18].iss_uop.fu_code[9], slots_18.io.iss_uop.fu_code[9]
connect issue_slots[18].iss_uop.iq_type[0], slots_18.io.iss_uop.iq_type[0]
connect issue_slots[18].iss_uop.iq_type[1], slots_18.io.iss_uop.iq_type[1]
connect issue_slots[18].iss_uop.iq_type[2], slots_18.io.iss_uop.iq_type[2]
connect issue_slots[18].iss_uop.iq_type[3], slots_18.io.iss_uop.iq_type[3]
connect issue_slots[18].iss_uop.debug_pc, slots_18.io.iss_uop.debug_pc
connect issue_slots[18].iss_uop.is_rvc, slots_18.io.iss_uop.is_rvc
connect issue_slots[18].iss_uop.debug_inst, slots_18.io.iss_uop.debug_inst
connect issue_slots[18].iss_uop.inst, slots_18.io.iss_uop.inst
connect slots_18.io.grant, issue_slots[18].grant
connect issue_slots[18].request, slots_18.io.request
connect issue_slots[18].will_be_valid, slots_18.io.will_be_valid
connect issue_slots[18].valid, slots_18.io.valid
connect slots_19.io.child_rebusys, issue_slots[19].child_rebusys
connect slots_19.io.pred_wakeup_port.bits, issue_slots[19].pred_wakeup_port.bits
connect slots_19.io.pred_wakeup_port.valid, issue_slots[19].pred_wakeup_port.valid
connect slots_19.io.wakeup_ports[0].bits.rebusy, issue_slots[19].wakeup_ports[0].bits.rebusy
connect slots_19.io.wakeup_ports[0].bits.speculative_mask, issue_slots[19].wakeup_ports[0].bits.speculative_mask
connect slots_19.io.wakeup_ports[0].bits.bypassable, issue_slots[19].wakeup_ports[0].bits.bypassable
connect slots_19.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[19].wakeup_ports[0].bits.uop.debug_tsrc
connect slots_19.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[19].wakeup_ports[0].bits.uop.debug_fsrc
connect slots_19.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[19].wakeup_ports[0].bits.uop.bp_xcpt_if
connect slots_19.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[19].wakeup_ports[0].bits.uop.bp_debug_if
connect slots_19.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[19].wakeup_ports[0].bits.uop.xcpt_ma_if
connect slots_19.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[19].wakeup_ports[0].bits.uop.xcpt_ae_if
connect slots_19.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[19].wakeup_ports[0].bits.uop.xcpt_pf_if
connect slots_19.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[19].wakeup_ports[0].bits.uop.fp_typ
connect slots_19.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[19].wakeup_ports[0].bits.uop.fp_rm
connect slots_19.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[19].wakeup_ports[0].bits.uop.fp_val
connect slots_19.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[19].wakeup_ports[0].bits.uop.fcn_op
connect slots_19.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[19].wakeup_ports[0].bits.uop.fcn_dw
connect slots_19.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[19].wakeup_ports[0].bits.uop.frs3_en
connect slots_19.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[19].wakeup_ports[0].bits.uop.lrs2_rtype
connect slots_19.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[19].wakeup_ports[0].bits.uop.lrs1_rtype
connect slots_19.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[19].wakeup_ports[0].bits.uop.dst_rtype
connect slots_19.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[19].wakeup_ports[0].bits.uop.lrs3
connect slots_19.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[19].wakeup_ports[0].bits.uop.lrs2
connect slots_19.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[19].wakeup_ports[0].bits.uop.lrs1
connect slots_19.io.wakeup_ports[0].bits.uop.ldst, issue_slots[19].wakeup_ports[0].bits.uop.ldst
connect slots_19.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[19].wakeup_ports[0].bits.uop.ldst_is_rs1
connect slots_19.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[19].wakeup_ports[0].bits.uop.csr_cmd
connect slots_19.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[19].wakeup_ports[0].bits.uop.flush_on_commit
connect slots_19.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[19].wakeup_ports[0].bits.uop.is_unique
connect slots_19.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[19].wakeup_ports[0].bits.uop.uses_stq
connect slots_19.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[19].wakeup_ports[0].bits.uop.uses_ldq
connect slots_19.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[19].wakeup_ports[0].bits.uop.mem_signed
connect slots_19.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[19].wakeup_ports[0].bits.uop.mem_size
connect slots_19.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[19].wakeup_ports[0].bits.uop.mem_cmd
connect slots_19.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[19].wakeup_ports[0].bits.uop.exc_cause
connect slots_19.io.wakeup_ports[0].bits.uop.exception, issue_slots[19].wakeup_ports[0].bits.uop.exception
connect slots_19.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[19].wakeup_ports[0].bits.uop.stale_pdst
connect slots_19.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[19].wakeup_ports[0].bits.uop.ppred_busy
connect slots_19.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[19].wakeup_ports[0].bits.uop.prs3_busy
connect slots_19.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[19].wakeup_ports[0].bits.uop.prs2_busy
connect slots_19.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[19].wakeup_ports[0].bits.uop.prs1_busy
connect slots_19.io.wakeup_ports[0].bits.uop.ppred, issue_slots[19].wakeup_ports[0].bits.uop.ppred
connect slots_19.io.wakeup_ports[0].bits.uop.prs3, issue_slots[19].wakeup_ports[0].bits.uop.prs3
connect slots_19.io.wakeup_ports[0].bits.uop.prs2, issue_slots[19].wakeup_ports[0].bits.uop.prs2
connect slots_19.io.wakeup_ports[0].bits.uop.prs1, issue_slots[19].wakeup_ports[0].bits.uop.prs1
connect slots_19.io.wakeup_ports[0].bits.uop.pdst, issue_slots[19].wakeup_ports[0].bits.uop.pdst
connect slots_19.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[19].wakeup_ports[0].bits.uop.rxq_idx
connect slots_19.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[19].wakeup_ports[0].bits.uop.stq_idx
connect slots_19.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[19].wakeup_ports[0].bits.uop.ldq_idx
connect slots_19.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[19].wakeup_ports[0].bits.uop.rob_idx
connect slots_19.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.vec
connect slots_19.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.wflags
connect slots_19.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.sqrt
connect slots_19.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.div
connect slots_19.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.fma
connect slots_19.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe
connect slots_19.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.toint
connect slots_19.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.fromint
connect slots_19.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut
connect slots_19.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn
connect slots_19.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.swap23
connect slots_19.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.swap12
connect slots_19.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.ren3
connect slots_19.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.ren2
connect slots_19.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.ren1
connect slots_19.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.wen
connect slots_19.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.ldst
connect slots_19.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[19].wakeup_ports[0].bits.uop.op2_sel
connect slots_19.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[19].wakeup_ports[0].bits.uop.op1_sel
connect slots_19.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[19].wakeup_ports[0].bits.uop.imm_packed
connect slots_19.io.wakeup_ports[0].bits.uop.pimm, issue_slots[19].wakeup_ports[0].bits.uop.pimm
connect slots_19.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[19].wakeup_ports[0].bits.uop.imm_sel
connect slots_19.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[19].wakeup_ports[0].bits.uop.imm_rename
connect slots_19.io.wakeup_ports[0].bits.uop.taken, issue_slots[19].wakeup_ports[0].bits.uop.taken
connect slots_19.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[19].wakeup_ports[0].bits.uop.pc_lob
connect slots_19.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[19].wakeup_ports[0].bits.uop.edge_inst
connect slots_19.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[19].wakeup_ports[0].bits.uop.ftq_idx
connect slots_19.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[19].wakeup_ports[0].bits.uop.is_mov
connect slots_19.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[19].wakeup_ports[0].bits.uop.is_rocc
connect slots_19.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[19].wakeup_ports[0].bits.uop.is_sys_pc2epc
connect slots_19.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[19].wakeup_ports[0].bits.uop.is_eret
connect slots_19.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[19].wakeup_ports[0].bits.uop.is_amo
connect slots_19.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[19].wakeup_ports[0].bits.uop.is_sfence
connect slots_19.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[19].wakeup_ports[0].bits.uop.is_fencei
connect slots_19.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[19].wakeup_ports[0].bits.uop.is_fence
connect slots_19.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[19].wakeup_ports[0].bits.uop.is_sfb
connect slots_19.io.wakeup_ports[0].bits.uop.br_type, issue_slots[19].wakeup_ports[0].bits.uop.br_type
connect slots_19.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[19].wakeup_ports[0].bits.uop.br_tag
connect slots_19.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[19].wakeup_ports[0].bits.uop.br_mask
connect slots_19.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[19].wakeup_ports[0].bits.uop.dis_col_sel
connect slots_19.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[19].wakeup_ports[0].bits.uop.iw_p3_bypass_hint
connect slots_19.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[19].wakeup_ports[0].bits.uop.iw_p2_bypass_hint
connect slots_19.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[19].wakeup_ports[0].bits.uop.iw_p1_bypass_hint
connect slots_19.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[19].wakeup_ports[0].bits.uop.iw_p2_speculative_child
connect slots_19.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[19].wakeup_ports[0].bits.uop.iw_p1_speculative_child
connect slots_19.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[19].wakeup_ports[0].bits.uop.iw_issued_partial_dgen
connect slots_19.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[19].wakeup_ports[0].bits.uop.iw_issued_partial_agen
connect slots_19.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[19].wakeup_ports[0].bits.uop.iw_issued
connect slots_19.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[19].wakeup_ports[0].bits.uop.fu_code[0]
connect slots_19.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[19].wakeup_ports[0].bits.uop.fu_code[1]
connect slots_19.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[19].wakeup_ports[0].bits.uop.fu_code[2]
connect slots_19.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[19].wakeup_ports[0].bits.uop.fu_code[3]
connect slots_19.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[19].wakeup_ports[0].bits.uop.fu_code[4]
connect slots_19.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[19].wakeup_ports[0].bits.uop.fu_code[5]
connect slots_19.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[19].wakeup_ports[0].bits.uop.fu_code[6]
connect slots_19.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[19].wakeup_ports[0].bits.uop.fu_code[7]
connect slots_19.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[19].wakeup_ports[0].bits.uop.fu_code[8]
connect slots_19.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[19].wakeup_ports[0].bits.uop.fu_code[9]
connect slots_19.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[19].wakeup_ports[0].bits.uop.iq_type[0]
connect slots_19.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[19].wakeup_ports[0].bits.uop.iq_type[1]
connect slots_19.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[19].wakeup_ports[0].bits.uop.iq_type[2]
connect slots_19.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[19].wakeup_ports[0].bits.uop.iq_type[3]
connect slots_19.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[19].wakeup_ports[0].bits.uop.debug_pc
connect slots_19.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[19].wakeup_ports[0].bits.uop.is_rvc
connect slots_19.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[19].wakeup_ports[0].bits.uop.debug_inst
connect slots_19.io.wakeup_ports[0].bits.uop.inst, issue_slots[19].wakeup_ports[0].bits.uop.inst
connect slots_19.io.wakeup_ports[0].valid, issue_slots[19].wakeup_ports[0].valid
connect slots_19.io.wakeup_ports[1].bits.rebusy, issue_slots[19].wakeup_ports[1].bits.rebusy
connect slots_19.io.wakeup_ports[1].bits.speculative_mask, issue_slots[19].wakeup_ports[1].bits.speculative_mask
connect slots_19.io.wakeup_ports[1].bits.bypassable, issue_slots[19].wakeup_ports[1].bits.bypassable
connect slots_19.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[19].wakeup_ports[1].bits.uop.debug_tsrc
connect slots_19.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[19].wakeup_ports[1].bits.uop.debug_fsrc
connect slots_19.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[19].wakeup_ports[1].bits.uop.bp_xcpt_if
connect slots_19.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[19].wakeup_ports[1].bits.uop.bp_debug_if
connect slots_19.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[19].wakeup_ports[1].bits.uop.xcpt_ma_if
connect slots_19.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[19].wakeup_ports[1].bits.uop.xcpt_ae_if
connect slots_19.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[19].wakeup_ports[1].bits.uop.xcpt_pf_if
connect slots_19.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[19].wakeup_ports[1].bits.uop.fp_typ
connect slots_19.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[19].wakeup_ports[1].bits.uop.fp_rm
connect slots_19.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[19].wakeup_ports[1].bits.uop.fp_val
connect slots_19.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[19].wakeup_ports[1].bits.uop.fcn_op
connect slots_19.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[19].wakeup_ports[1].bits.uop.fcn_dw
connect slots_19.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[19].wakeup_ports[1].bits.uop.frs3_en
connect slots_19.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[19].wakeup_ports[1].bits.uop.lrs2_rtype
connect slots_19.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[19].wakeup_ports[1].bits.uop.lrs1_rtype
connect slots_19.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[19].wakeup_ports[1].bits.uop.dst_rtype
connect slots_19.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[19].wakeup_ports[1].bits.uop.lrs3
connect slots_19.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[19].wakeup_ports[1].bits.uop.lrs2
connect slots_19.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[19].wakeup_ports[1].bits.uop.lrs1
connect slots_19.io.wakeup_ports[1].bits.uop.ldst, issue_slots[19].wakeup_ports[1].bits.uop.ldst
connect slots_19.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[19].wakeup_ports[1].bits.uop.ldst_is_rs1
connect slots_19.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[19].wakeup_ports[1].bits.uop.csr_cmd
connect slots_19.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[19].wakeup_ports[1].bits.uop.flush_on_commit
connect slots_19.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[19].wakeup_ports[1].bits.uop.is_unique
connect slots_19.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[19].wakeup_ports[1].bits.uop.uses_stq
connect slots_19.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[19].wakeup_ports[1].bits.uop.uses_ldq
connect slots_19.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[19].wakeup_ports[1].bits.uop.mem_signed
connect slots_19.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[19].wakeup_ports[1].bits.uop.mem_size
connect slots_19.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[19].wakeup_ports[1].bits.uop.mem_cmd
connect slots_19.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[19].wakeup_ports[1].bits.uop.exc_cause
connect slots_19.io.wakeup_ports[1].bits.uop.exception, issue_slots[19].wakeup_ports[1].bits.uop.exception
connect slots_19.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[19].wakeup_ports[1].bits.uop.stale_pdst
connect slots_19.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[19].wakeup_ports[1].bits.uop.ppred_busy
connect slots_19.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[19].wakeup_ports[1].bits.uop.prs3_busy
connect slots_19.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[19].wakeup_ports[1].bits.uop.prs2_busy
connect slots_19.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[19].wakeup_ports[1].bits.uop.prs1_busy
connect slots_19.io.wakeup_ports[1].bits.uop.ppred, issue_slots[19].wakeup_ports[1].bits.uop.ppred
connect slots_19.io.wakeup_ports[1].bits.uop.prs3, issue_slots[19].wakeup_ports[1].bits.uop.prs3
connect slots_19.io.wakeup_ports[1].bits.uop.prs2, issue_slots[19].wakeup_ports[1].bits.uop.prs2
connect slots_19.io.wakeup_ports[1].bits.uop.prs1, issue_slots[19].wakeup_ports[1].bits.uop.prs1
connect slots_19.io.wakeup_ports[1].bits.uop.pdst, issue_slots[19].wakeup_ports[1].bits.uop.pdst
connect slots_19.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[19].wakeup_ports[1].bits.uop.rxq_idx
connect slots_19.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[19].wakeup_ports[1].bits.uop.stq_idx
connect slots_19.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[19].wakeup_ports[1].bits.uop.ldq_idx
connect slots_19.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[19].wakeup_ports[1].bits.uop.rob_idx
connect slots_19.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.vec
connect slots_19.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.wflags
connect slots_19.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.sqrt
connect slots_19.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.div
connect slots_19.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.fma
connect slots_19.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe
connect slots_19.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.toint
connect slots_19.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.fromint
connect slots_19.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut
connect slots_19.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn
connect slots_19.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.swap23
connect slots_19.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.swap12
connect slots_19.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.ren3
connect slots_19.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.ren2
connect slots_19.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.ren1
connect slots_19.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.wen
connect slots_19.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.ldst
connect slots_19.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[19].wakeup_ports[1].bits.uop.op2_sel
connect slots_19.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[19].wakeup_ports[1].bits.uop.op1_sel
connect slots_19.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[19].wakeup_ports[1].bits.uop.imm_packed
connect slots_19.io.wakeup_ports[1].bits.uop.pimm, issue_slots[19].wakeup_ports[1].bits.uop.pimm
connect slots_19.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[19].wakeup_ports[1].bits.uop.imm_sel
connect slots_19.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[19].wakeup_ports[1].bits.uop.imm_rename
connect slots_19.io.wakeup_ports[1].bits.uop.taken, issue_slots[19].wakeup_ports[1].bits.uop.taken
connect slots_19.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[19].wakeup_ports[1].bits.uop.pc_lob
connect slots_19.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[19].wakeup_ports[1].bits.uop.edge_inst
connect slots_19.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[19].wakeup_ports[1].bits.uop.ftq_idx
connect slots_19.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[19].wakeup_ports[1].bits.uop.is_mov
connect slots_19.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[19].wakeup_ports[1].bits.uop.is_rocc
connect slots_19.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[19].wakeup_ports[1].bits.uop.is_sys_pc2epc
connect slots_19.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[19].wakeup_ports[1].bits.uop.is_eret
connect slots_19.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[19].wakeup_ports[1].bits.uop.is_amo
connect slots_19.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[19].wakeup_ports[1].bits.uop.is_sfence
connect slots_19.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[19].wakeup_ports[1].bits.uop.is_fencei
connect slots_19.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[19].wakeup_ports[1].bits.uop.is_fence
connect slots_19.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[19].wakeup_ports[1].bits.uop.is_sfb
connect slots_19.io.wakeup_ports[1].bits.uop.br_type, issue_slots[19].wakeup_ports[1].bits.uop.br_type
connect slots_19.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[19].wakeup_ports[1].bits.uop.br_tag
connect slots_19.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[19].wakeup_ports[1].bits.uop.br_mask
connect slots_19.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[19].wakeup_ports[1].bits.uop.dis_col_sel
connect slots_19.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[19].wakeup_ports[1].bits.uop.iw_p3_bypass_hint
connect slots_19.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[19].wakeup_ports[1].bits.uop.iw_p2_bypass_hint
connect slots_19.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[19].wakeup_ports[1].bits.uop.iw_p1_bypass_hint
connect slots_19.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[19].wakeup_ports[1].bits.uop.iw_p2_speculative_child
connect slots_19.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[19].wakeup_ports[1].bits.uop.iw_p1_speculative_child
connect slots_19.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[19].wakeup_ports[1].bits.uop.iw_issued_partial_dgen
connect slots_19.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[19].wakeup_ports[1].bits.uop.iw_issued_partial_agen
connect slots_19.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[19].wakeup_ports[1].bits.uop.iw_issued
connect slots_19.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[19].wakeup_ports[1].bits.uop.fu_code[0]
connect slots_19.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[19].wakeup_ports[1].bits.uop.fu_code[1]
connect slots_19.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[19].wakeup_ports[1].bits.uop.fu_code[2]
connect slots_19.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[19].wakeup_ports[1].bits.uop.fu_code[3]
connect slots_19.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[19].wakeup_ports[1].bits.uop.fu_code[4]
connect slots_19.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[19].wakeup_ports[1].bits.uop.fu_code[5]
connect slots_19.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[19].wakeup_ports[1].bits.uop.fu_code[6]
connect slots_19.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[19].wakeup_ports[1].bits.uop.fu_code[7]
connect slots_19.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[19].wakeup_ports[1].bits.uop.fu_code[8]
connect slots_19.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[19].wakeup_ports[1].bits.uop.fu_code[9]
connect slots_19.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[19].wakeup_ports[1].bits.uop.iq_type[0]
connect slots_19.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[19].wakeup_ports[1].bits.uop.iq_type[1]
connect slots_19.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[19].wakeup_ports[1].bits.uop.iq_type[2]
connect slots_19.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[19].wakeup_ports[1].bits.uop.iq_type[3]
connect slots_19.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[19].wakeup_ports[1].bits.uop.debug_pc
connect slots_19.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[19].wakeup_ports[1].bits.uop.is_rvc
connect slots_19.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[19].wakeup_ports[1].bits.uop.debug_inst
connect slots_19.io.wakeup_ports[1].bits.uop.inst, issue_slots[19].wakeup_ports[1].bits.uop.inst
connect slots_19.io.wakeup_ports[1].valid, issue_slots[19].wakeup_ports[1].valid
connect slots_19.io.wakeup_ports[2].bits.rebusy, issue_slots[19].wakeup_ports[2].bits.rebusy
connect slots_19.io.wakeup_ports[2].bits.speculative_mask, issue_slots[19].wakeup_ports[2].bits.speculative_mask
connect slots_19.io.wakeup_ports[2].bits.bypassable, issue_slots[19].wakeup_ports[2].bits.bypassable
connect slots_19.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[19].wakeup_ports[2].bits.uop.debug_tsrc
connect slots_19.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[19].wakeup_ports[2].bits.uop.debug_fsrc
connect slots_19.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[19].wakeup_ports[2].bits.uop.bp_xcpt_if
connect slots_19.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[19].wakeup_ports[2].bits.uop.bp_debug_if
connect slots_19.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[19].wakeup_ports[2].bits.uop.xcpt_ma_if
connect slots_19.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[19].wakeup_ports[2].bits.uop.xcpt_ae_if
connect slots_19.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[19].wakeup_ports[2].bits.uop.xcpt_pf_if
connect slots_19.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[19].wakeup_ports[2].bits.uop.fp_typ
connect slots_19.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[19].wakeup_ports[2].bits.uop.fp_rm
connect slots_19.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[19].wakeup_ports[2].bits.uop.fp_val
connect slots_19.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[19].wakeup_ports[2].bits.uop.fcn_op
connect slots_19.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[19].wakeup_ports[2].bits.uop.fcn_dw
connect slots_19.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[19].wakeup_ports[2].bits.uop.frs3_en
connect slots_19.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[19].wakeup_ports[2].bits.uop.lrs2_rtype
connect slots_19.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[19].wakeup_ports[2].bits.uop.lrs1_rtype
connect slots_19.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[19].wakeup_ports[2].bits.uop.dst_rtype
connect slots_19.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[19].wakeup_ports[2].bits.uop.lrs3
connect slots_19.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[19].wakeup_ports[2].bits.uop.lrs2
connect slots_19.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[19].wakeup_ports[2].bits.uop.lrs1
connect slots_19.io.wakeup_ports[2].bits.uop.ldst, issue_slots[19].wakeup_ports[2].bits.uop.ldst
connect slots_19.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[19].wakeup_ports[2].bits.uop.ldst_is_rs1
connect slots_19.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[19].wakeup_ports[2].bits.uop.csr_cmd
connect slots_19.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[19].wakeup_ports[2].bits.uop.flush_on_commit
connect slots_19.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[19].wakeup_ports[2].bits.uop.is_unique
connect slots_19.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[19].wakeup_ports[2].bits.uop.uses_stq
connect slots_19.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[19].wakeup_ports[2].bits.uop.uses_ldq
connect slots_19.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[19].wakeup_ports[2].bits.uop.mem_signed
connect slots_19.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[19].wakeup_ports[2].bits.uop.mem_size
connect slots_19.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[19].wakeup_ports[2].bits.uop.mem_cmd
connect slots_19.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[19].wakeup_ports[2].bits.uop.exc_cause
connect slots_19.io.wakeup_ports[2].bits.uop.exception, issue_slots[19].wakeup_ports[2].bits.uop.exception
connect slots_19.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[19].wakeup_ports[2].bits.uop.stale_pdst
connect slots_19.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[19].wakeup_ports[2].bits.uop.ppred_busy
connect slots_19.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[19].wakeup_ports[2].bits.uop.prs3_busy
connect slots_19.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[19].wakeup_ports[2].bits.uop.prs2_busy
connect slots_19.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[19].wakeup_ports[2].bits.uop.prs1_busy
connect slots_19.io.wakeup_ports[2].bits.uop.ppred, issue_slots[19].wakeup_ports[2].bits.uop.ppred
connect slots_19.io.wakeup_ports[2].bits.uop.prs3, issue_slots[19].wakeup_ports[2].bits.uop.prs3
connect slots_19.io.wakeup_ports[2].bits.uop.prs2, issue_slots[19].wakeup_ports[2].bits.uop.prs2
connect slots_19.io.wakeup_ports[2].bits.uop.prs1, issue_slots[19].wakeup_ports[2].bits.uop.prs1
connect slots_19.io.wakeup_ports[2].bits.uop.pdst, issue_slots[19].wakeup_ports[2].bits.uop.pdst
connect slots_19.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[19].wakeup_ports[2].bits.uop.rxq_idx
connect slots_19.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[19].wakeup_ports[2].bits.uop.stq_idx
connect slots_19.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[19].wakeup_ports[2].bits.uop.ldq_idx
connect slots_19.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[19].wakeup_ports[2].bits.uop.rob_idx
connect slots_19.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.vec
connect slots_19.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.wflags
connect slots_19.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.sqrt
connect slots_19.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.div
connect slots_19.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.fma
connect slots_19.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe
connect slots_19.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.toint
connect slots_19.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.fromint
connect slots_19.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut
connect slots_19.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn
connect slots_19.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.swap23
connect slots_19.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.swap12
connect slots_19.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.ren3
connect slots_19.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.ren2
connect slots_19.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.ren1
connect slots_19.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.wen
connect slots_19.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.ldst
connect slots_19.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[19].wakeup_ports[2].bits.uop.op2_sel
connect slots_19.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[19].wakeup_ports[2].bits.uop.op1_sel
connect slots_19.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[19].wakeup_ports[2].bits.uop.imm_packed
connect slots_19.io.wakeup_ports[2].bits.uop.pimm, issue_slots[19].wakeup_ports[2].bits.uop.pimm
connect slots_19.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[19].wakeup_ports[2].bits.uop.imm_sel
connect slots_19.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[19].wakeup_ports[2].bits.uop.imm_rename
connect slots_19.io.wakeup_ports[2].bits.uop.taken, issue_slots[19].wakeup_ports[2].bits.uop.taken
connect slots_19.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[19].wakeup_ports[2].bits.uop.pc_lob
connect slots_19.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[19].wakeup_ports[2].bits.uop.edge_inst
connect slots_19.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[19].wakeup_ports[2].bits.uop.ftq_idx
connect slots_19.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[19].wakeup_ports[2].bits.uop.is_mov
connect slots_19.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[19].wakeup_ports[2].bits.uop.is_rocc
connect slots_19.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[19].wakeup_ports[2].bits.uop.is_sys_pc2epc
connect slots_19.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[19].wakeup_ports[2].bits.uop.is_eret
connect slots_19.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[19].wakeup_ports[2].bits.uop.is_amo
connect slots_19.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[19].wakeup_ports[2].bits.uop.is_sfence
connect slots_19.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[19].wakeup_ports[2].bits.uop.is_fencei
connect slots_19.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[19].wakeup_ports[2].bits.uop.is_fence
connect slots_19.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[19].wakeup_ports[2].bits.uop.is_sfb
connect slots_19.io.wakeup_ports[2].bits.uop.br_type, issue_slots[19].wakeup_ports[2].bits.uop.br_type
connect slots_19.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[19].wakeup_ports[2].bits.uop.br_tag
connect slots_19.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[19].wakeup_ports[2].bits.uop.br_mask
connect slots_19.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[19].wakeup_ports[2].bits.uop.dis_col_sel
connect slots_19.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[19].wakeup_ports[2].bits.uop.iw_p3_bypass_hint
connect slots_19.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[19].wakeup_ports[2].bits.uop.iw_p2_bypass_hint
connect slots_19.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[19].wakeup_ports[2].bits.uop.iw_p1_bypass_hint
connect slots_19.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[19].wakeup_ports[2].bits.uop.iw_p2_speculative_child
connect slots_19.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[19].wakeup_ports[2].bits.uop.iw_p1_speculative_child
connect slots_19.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[19].wakeup_ports[2].bits.uop.iw_issued_partial_dgen
connect slots_19.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[19].wakeup_ports[2].bits.uop.iw_issued_partial_agen
connect slots_19.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[19].wakeup_ports[2].bits.uop.iw_issued
connect slots_19.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[19].wakeup_ports[2].bits.uop.fu_code[0]
connect slots_19.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[19].wakeup_ports[2].bits.uop.fu_code[1]
connect slots_19.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[19].wakeup_ports[2].bits.uop.fu_code[2]
connect slots_19.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[19].wakeup_ports[2].bits.uop.fu_code[3]
connect slots_19.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[19].wakeup_ports[2].bits.uop.fu_code[4]
connect slots_19.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[19].wakeup_ports[2].bits.uop.fu_code[5]
connect slots_19.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[19].wakeup_ports[2].bits.uop.fu_code[6]
connect slots_19.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[19].wakeup_ports[2].bits.uop.fu_code[7]
connect slots_19.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[19].wakeup_ports[2].bits.uop.fu_code[8]
connect slots_19.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[19].wakeup_ports[2].bits.uop.fu_code[9]
connect slots_19.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[19].wakeup_ports[2].bits.uop.iq_type[0]
connect slots_19.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[19].wakeup_ports[2].bits.uop.iq_type[1]
connect slots_19.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[19].wakeup_ports[2].bits.uop.iq_type[2]
connect slots_19.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[19].wakeup_ports[2].bits.uop.iq_type[3]
connect slots_19.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[19].wakeup_ports[2].bits.uop.debug_pc
connect slots_19.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[19].wakeup_ports[2].bits.uop.is_rvc
connect slots_19.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[19].wakeup_ports[2].bits.uop.debug_inst
connect slots_19.io.wakeup_ports[2].bits.uop.inst, issue_slots[19].wakeup_ports[2].bits.uop.inst
connect slots_19.io.wakeup_ports[2].valid, issue_slots[19].wakeup_ports[2].valid
connect slots_19.io.wakeup_ports[3].bits.rebusy, issue_slots[19].wakeup_ports[3].bits.rebusy
connect slots_19.io.wakeup_ports[3].bits.speculative_mask, issue_slots[19].wakeup_ports[3].bits.speculative_mask
connect slots_19.io.wakeup_ports[3].bits.bypassable, issue_slots[19].wakeup_ports[3].bits.bypassable
connect slots_19.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[19].wakeup_ports[3].bits.uop.debug_tsrc
connect slots_19.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[19].wakeup_ports[3].bits.uop.debug_fsrc
connect slots_19.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[19].wakeup_ports[3].bits.uop.bp_xcpt_if
connect slots_19.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[19].wakeup_ports[3].bits.uop.bp_debug_if
connect slots_19.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[19].wakeup_ports[3].bits.uop.xcpt_ma_if
connect slots_19.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[19].wakeup_ports[3].bits.uop.xcpt_ae_if
connect slots_19.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[19].wakeup_ports[3].bits.uop.xcpt_pf_if
connect slots_19.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[19].wakeup_ports[3].bits.uop.fp_typ
connect slots_19.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[19].wakeup_ports[3].bits.uop.fp_rm
connect slots_19.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[19].wakeup_ports[3].bits.uop.fp_val
connect slots_19.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[19].wakeup_ports[3].bits.uop.fcn_op
connect slots_19.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[19].wakeup_ports[3].bits.uop.fcn_dw
connect slots_19.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[19].wakeup_ports[3].bits.uop.frs3_en
connect slots_19.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[19].wakeup_ports[3].bits.uop.lrs2_rtype
connect slots_19.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[19].wakeup_ports[3].bits.uop.lrs1_rtype
connect slots_19.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[19].wakeup_ports[3].bits.uop.dst_rtype
connect slots_19.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[19].wakeup_ports[3].bits.uop.lrs3
connect slots_19.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[19].wakeup_ports[3].bits.uop.lrs2
connect slots_19.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[19].wakeup_ports[3].bits.uop.lrs1
connect slots_19.io.wakeup_ports[3].bits.uop.ldst, issue_slots[19].wakeup_ports[3].bits.uop.ldst
connect slots_19.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[19].wakeup_ports[3].bits.uop.ldst_is_rs1
connect slots_19.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[19].wakeup_ports[3].bits.uop.csr_cmd
connect slots_19.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[19].wakeup_ports[3].bits.uop.flush_on_commit
connect slots_19.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[19].wakeup_ports[3].bits.uop.is_unique
connect slots_19.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[19].wakeup_ports[3].bits.uop.uses_stq
connect slots_19.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[19].wakeup_ports[3].bits.uop.uses_ldq
connect slots_19.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[19].wakeup_ports[3].bits.uop.mem_signed
connect slots_19.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[19].wakeup_ports[3].bits.uop.mem_size
connect slots_19.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[19].wakeup_ports[3].bits.uop.mem_cmd
connect slots_19.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[19].wakeup_ports[3].bits.uop.exc_cause
connect slots_19.io.wakeup_ports[3].bits.uop.exception, issue_slots[19].wakeup_ports[3].bits.uop.exception
connect slots_19.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[19].wakeup_ports[3].bits.uop.stale_pdst
connect slots_19.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[19].wakeup_ports[3].bits.uop.ppred_busy
connect slots_19.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[19].wakeup_ports[3].bits.uop.prs3_busy
connect slots_19.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[19].wakeup_ports[3].bits.uop.prs2_busy
connect slots_19.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[19].wakeup_ports[3].bits.uop.prs1_busy
connect slots_19.io.wakeup_ports[3].bits.uop.ppred, issue_slots[19].wakeup_ports[3].bits.uop.ppred
connect slots_19.io.wakeup_ports[3].bits.uop.prs3, issue_slots[19].wakeup_ports[3].bits.uop.prs3
connect slots_19.io.wakeup_ports[3].bits.uop.prs2, issue_slots[19].wakeup_ports[3].bits.uop.prs2
connect slots_19.io.wakeup_ports[3].bits.uop.prs1, issue_slots[19].wakeup_ports[3].bits.uop.prs1
connect slots_19.io.wakeup_ports[3].bits.uop.pdst, issue_slots[19].wakeup_ports[3].bits.uop.pdst
connect slots_19.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[19].wakeup_ports[3].bits.uop.rxq_idx
connect slots_19.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[19].wakeup_ports[3].bits.uop.stq_idx
connect slots_19.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[19].wakeup_ports[3].bits.uop.ldq_idx
connect slots_19.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[19].wakeup_ports[3].bits.uop.rob_idx
connect slots_19.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.vec
connect slots_19.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.wflags
connect slots_19.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.sqrt
connect slots_19.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.div
connect slots_19.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.fma
connect slots_19.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe
connect slots_19.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.toint
connect slots_19.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.fromint
connect slots_19.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut
connect slots_19.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn
connect slots_19.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.swap23
connect slots_19.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.swap12
connect slots_19.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.ren3
connect slots_19.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.ren2
connect slots_19.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.ren1
connect slots_19.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.wen
connect slots_19.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.ldst
connect slots_19.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[19].wakeup_ports[3].bits.uop.op2_sel
connect slots_19.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[19].wakeup_ports[3].bits.uop.op1_sel
connect slots_19.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[19].wakeup_ports[3].bits.uop.imm_packed
connect slots_19.io.wakeup_ports[3].bits.uop.pimm, issue_slots[19].wakeup_ports[3].bits.uop.pimm
connect slots_19.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[19].wakeup_ports[3].bits.uop.imm_sel
connect slots_19.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[19].wakeup_ports[3].bits.uop.imm_rename
connect slots_19.io.wakeup_ports[3].bits.uop.taken, issue_slots[19].wakeup_ports[3].bits.uop.taken
connect slots_19.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[19].wakeup_ports[3].bits.uop.pc_lob
connect slots_19.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[19].wakeup_ports[3].bits.uop.edge_inst
connect slots_19.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[19].wakeup_ports[3].bits.uop.ftq_idx
connect slots_19.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[19].wakeup_ports[3].bits.uop.is_mov
connect slots_19.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[19].wakeup_ports[3].bits.uop.is_rocc
connect slots_19.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[19].wakeup_ports[3].bits.uop.is_sys_pc2epc
connect slots_19.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[19].wakeup_ports[3].bits.uop.is_eret
connect slots_19.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[19].wakeup_ports[3].bits.uop.is_amo
connect slots_19.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[19].wakeup_ports[3].bits.uop.is_sfence
connect slots_19.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[19].wakeup_ports[3].bits.uop.is_fencei
connect slots_19.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[19].wakeup_ports[3].bits.uop.is_fence
connect slots_19.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[19].wakeup_ports[3].bits.uop.is_sfb
connect slots_19.io.wakeup_ports[3].bits.uop.br_type, issue_slots[19].wakeup_ports[3].bits.uop.br_type
connect slots_19.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[19].wakeup_ports[3].bits.uop.br_tag
connect slots_19.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[19].wakeup_ports[3].bits.uop.br_mask
connect slots_19.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[19].wakeup_ports[3].bits.uop.dis_col_sel
connect slots_19.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[19].wakeup_ports[3].bits.uop.iw_p3_bypass_hint
connect slots_19.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[19].wakeup_ports[3].bits.uop.iw_p2_bypass_hint
connect slots_19.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[19].wakeup_ports[3].bits.uop.iw_p1_bypass_hint
connect slots_19.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[19].wakeup_ports[3].bits.uop.iw_p2_speculative_child
connect slots_19.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[19].wakeup_ports[3].bits.uop.iw_p1_speculative_child
connect slots_19.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[19].wakeup_ports[3].bits.uop.iw_issued_partial_dgen
connect slots_19.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[19].wakeup_ports[3].bits.uop.iw_issued_partial_agen
connect slots_19.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[19].wakeup_ports[3].bits.uop.iw_issued
connect slots_19.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[19].wakeup_ports[3].bits.uop.fu_code[0]
connect slots_19.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[19].wakeup_ports[3].bits.uop.fu_code[1]
connect slots_19.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[19].wakeup_ports[3].bits.uop.fu_code[2]
connect slots_19.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[19].wakeup_ports[3].bits.uop.fu_code[3]
connect slots_19.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[19].wakeup_ports[3].bits.uop.fu_code[4]
connect slots_19.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[19].wakeup_ports[3].bits.uop.fu_code[5]
connect slots_19.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[19].wakeup_ports[3].bits.uop.fu_code[6]
connect slots_19.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[19].wakeup_ports[3].bits.uop.fu_code[7]
connect slots_19.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[19].wakeup_ports[3].bits.uop.fu_code[8]
connect slots_19.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[19].wakeup_ports[3].bits.uop.fu_code[9]
connect slots_19.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[19].wakeup_ports[3].bits.uop.iq_type[0]
connect slots_19.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[19].wakeup_ports[3].bits.uop.iq_type[1]
connect slots_19.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[19].wakeup_ports[3].bits.uop.iq_type[2]
connect slots_19.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[19].wakeup_ports[3].bits.uop.iq_type[3]
connect slots_19.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[19].wakeup_ports[3].bits.uop.debug_pc
connect slots_19.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[19].wakeup_ports[3].bits.uop.is_rvc
connect slots_19.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[19].wakeup_ports[3].bits.uop.debug_inst
connect slots_19.io.wakeup_ports[3].bits.uop.inst, issue_slots[19].wakeup_ports[3].bits.uop.inst
connect slots_19.io.wakeup_ports[3].valid, issue_slots[19].wakeup_ports[3].valid
connect slots_19.io.squash_grant, issue_slots[19].squash_grant
connect slots_19.io.clear, issue_slots[19].clear
connect slots_19.io.kill, issue_slots[19].kill
connect slots_19.io.brupdate.b2.target_offset, issue_slots[19].brupdate.b2.target_offset
connect slots_19.io.brupdate.b2.jalr_target, issue_slots[19].brupdate.b2.jalr_target
connect slots_19.io.brupdate.b2.pc_sel, issue_slots[19].brupdate.b2.pc_sel
connect slots_19.io.brupdate.b2.cfi_type, issue_slots[19].brupdate.b2.cfi_type
connect slots_19.io.brupdate.b2.taken, issue_slots[19].brupdate.b2.taken
connect slots_19.io.brupdate.b2.mispredict, issue_slots[19].brupdate.b2.mispredict
connect slots_19.io.brupdate.b2.uop.debug_tsrc, issue_slots[19].brupdate.b2.uop.debug_tsrc
connect slots_19.io.brupdate.b2.uop.debug_fsrc, issue_slots[19].brupdate.b2.uop.debug_fsrc
connect slots_19.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[19].brupdate.b2.uop.bp_xcpt_if
connect slots_19.io.brupdate.b2.uop.bp_debug_if, issue_slots[19].brupdate.b2.uop.bp_debug_if
connect slots_19.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[19].brupdate.b2.uop.xcpt_ma_if
connect slots_19.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[19].brupdate.b2.uop.xcpt_ae_if
connect slots_19.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[19].brupdate.b2.uop.xcpt_pf_if
connect slots_19.io.brupdate.b2.uop.fp_typ, issue_slots[19].brupdate.b2.uop.fp_typ
connect slots_19.io.brupdate.b2.uop.fp_rm, issue_slots[19].brupdate.b2.uop.fp_rm
connect slots_19.io.brupdate.b2.uop.fp_val, issue_slots[19].brupdate.b2.uop.fp_val
connect slots_19.io.brupdate.b2.uop.fcn_op, issue_slots[19].brupdate.b2.uop.fcn_op
connect slots_19.io.brupdate.b2.uop.fcn_dw, issue_slots[19].brupdate.b2.uop.fcn_dw
connect slots_19.io.brupdate.b2.uop.frs3_en, issue_slots[19].brupdate.b2.uop.frs3_en
connect slots_19.io.brupdate.b2.uop.lrs2_rtype, issue_slots[19].brupdate.b2.uop.lrs2_rtype
connect slots_19.io.brupdate.b2.uop.lrs1_rtype, issue_slots[19].brupdate.b2.uop.lrs1_rtype
connect slots_19.io.brupdate.b2.uop.dst_rtype, issue_slots[19].brupdate.b2.uop.dst_rtype
connect slots_19.io.brupdate.b2.uop.lrs3, issue_slots[19].brupdate.b2.uop.lrs3
connect slots_19.io.brupdate.b2.uop.lrs2, issue_slots[19].brupdate.b2.uop.lrs2
connect slots_19.io.brupdate.b2.uop.lrs1, issue_slots[19].brupdate.b2.uop.lrs1
connect slots_19.io.brupdate.b2.uop.ldst, issue_slots[19].brupdate.b2.uop.ldst
connect slots_19.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[19].brupdate.b2.uop.ldst_is_rs1
connect slots_19.io.brupdate.b2.uop.csr_cmd, issue_slots[19].brupdate.b2.uop.csr_cmd
connect slots_19.io.brupdate.b2.uop.flush_on_commit, issue_slots[19].brupdate.b2.uop.flush_on_commit
connect slots_19.io.brupdate.b2.uop.is_unique, issue_slots[19].brupdate.b2.uop.is_unique
connect slots_19.io.brupdate.b2.uop.uses_stq, issue_slots[19].brupdate.b2.uop.uses_stq
connect slots_19.io.brupdate.b2.uop.uses_ldq, issue_slots[19].brupdate.b2.uop.uses_ldq
connect slots_19.io.brupdate.b2.uop.mem_signed, issue_slots[19].brupdate.b2.uop.mem_signed
connect slots_19.io.brupdate.b2.uop.mem_size, issue_slots[19].brupdate.b2.uop.mem_size
connect slots_19.io.brupdate.b2.uop.mem_cmd, issue_slots[19].brupdate.b2.uop.mem_cmd
connect slots_19.io.brupdate.b2.uop.exc_cause, issue_slots[19].brupdate.b2.uop.exc_cause
connect slots_19.io.brupdate.b2.uop.exception, issue_slots[19].brupdate.b2.uop.exception
connect slots_19.io.brupdate.b2.uop.stale_pdst, issue_slots[19].brupdate.b2.uop.stale_pdst
connect slots_19.io.brupdate.b2.uop.ppred_busy, issue_slots[19].brupdate.b2.uop.ppred_busy
connect slots_19.io.brupdate.b2.uop.prs3_busy, issue_slots[19].brupdate.b2.uop.prs3_busy
connect slots_19.io.brupdate.b2.uop.prs2_busy, issue_slots[19].brupdate.b2.uop.prs2_busy
connect slots_19.io.brupdate.b2.uop.prs1_busy, issue_slots[19].brupdate.b2.uop.prs1_busy
connect slots_19.io.brupdate.b2.uop.ppred, issue_slots[19].brupdate.b2.uop.ppred
connect slots_19.io.brupdate.b2.uop.prs3, issue_slots[19].brupdate.b2.uop.prs3
connect slots_19.io.brupdate.b2.uop.prs2, issue_slots[19].brupdate.b2.uop.prs2
connect slots_19.io.brupdate.b2.uop.prs1, issue_slots[19].brupdate.b2.uop.prs1
connect slots_19.io.brupdate.b2.uop.pdst, issue_slots[19].brupdate.b2.uop.pdst
connect slots_19.io.brupdate.b2.uop.rxq_idx, issue_slots[19].brupdate.b2.uop.rxq_idx
connect slots_19.io.brupdate.b2.uop.stq_idx, issue_slots[19].brupdate.b2.uop.stq_idx
connect slots_19.io.brupdate.b2.uop.ldq_idx, issue_slots[19].brupdate.b2.uop.ldq_idx
connect slots_19.io.brupdate.b2.uop.rob_idx, issue_slots[19].brupdate.b2.uop.rob_idx
connect slots_19.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[19].brupdate.b2.uop.fp_ctrl.vec
connect slots_19.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[19].brupdate.b2.uop.fp_ctrl.wflags
connect slots_19.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[19].brupdate.b2.uop.fp_ctrl.sqrt
connect slots_19.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[19].brupdate.b2.uop.fp_ctrl.div
connect slots_19.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[19].brupdate.b2.uop.fp_ctrl.fma
connect slots_19.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[19].brupdate.b2.uop.fp_ctrl.fastpipe
connect slots_19.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[19].brupdate.b2.uop.fp_ctrl.toint
connect slots_19.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[19].brupdate.b2.uop.fp_ctrl.fromint
connect slots_19.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[19].brupdate.b2.uop.fp_ctrl.typeTagOut
connect slots_19.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[19].brupdate.b2.uop.fp_ctrl.typeTagIn
connect slots_19.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[19].brupdate.b2.uop.fp_ctrl.swap23
connect slots_19.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[19].brupdate.b2.uop.fp_ctrl.swap12
connect slots_19.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[19].brupdate.b2.uop.fp_ctrl.ren3
connect slots_19.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[19].brupdate.b2.uop.fp_ctrl.ren2
connect slots_19.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[19].brupdate.b2.uop.fp_ctrl.ren1
connect slots_19.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[19].brupdate.b2.uop.fp_ctrl.wen
connect slots_19.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[19].brupdate.b2.uop.fp_ctrl.ldst
connect slots_19.io.brupdate.b2.uop.op2_sel, issue_slots[19].brupdate.b2.uop.op2_sel
connect slots_19.io.brupdate.b2.uop.op1_sel, issue_slots[19].brupdate.b2.uop.op1_sel
connect slots_19.io.brupdate.b2.uop.imm_packed, issue_slots[19].brupdate.b2.uop.imm_packed
connect slots_19.io.brupdate.b2.uop.pimm, issue_slots[19].brupdate.b2.uop.pimm
connect slots_19.io.brupdate.b2.uop.imm_sel, issue_slots[19].brupdate.b2.uop.imm_sel
connect slots_19.io.brupdate.b2.uop.imm_rename, issue_slots[19].brupdate.b2.uop.imm_rename
connect slots_19.io.brupdate.b2.uop.taken, issue_slots[19].brupdate.b2.uop.taken
connect slots_19.io.brupdate.b2.uop.pc_lob, issue_slots[19].brupdate.b2.uop.pc_lob
connect slots_19.io.brupdate.b2.uop.edge_inst, issue_slots[19].brupdate.b2.uop.edge_inst
connect slots_19.io.brupdate.b2.uop.ftq_idx, issue_slots[19].brupdate.b2.uop.ftq_idx
connect slots_19.io.brupdate.b2.uop.is_mov, issue_slots[19].brupdate.b2.uop.is_mov
connect slots_19.io.brupdate.b2.uop.is_rocc, issue_slots[19].brupdate.b2.uop.is_rocc
connect slots_19.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[19].brupdate.b2.uop.is_sys_pc2epc
connect slots_19.io.brupdate.b2.uop.is_eret, issue_slots[19].brupdate.b2.uop.is_eret
connect slots_19.io.brupdate.b2.uop.is_amo, issue_slots[19].brupdate.b2.uop.is_amo
connect slots_19.io.brupdate.b2.uop.is_sfence, issue_slots[19].brupdate.b2.uop.is_sfence
connect slots_19.io.brupdate.b2.uop.is_fencei, issue_slots[19].brupdate.b2.uop.is_fencei
connect slots_19.io.brupdate.b2.uop.is_fence, issue_slots[19].brupdate.b2.uop.is_fence
connect slots_19.io.brupdate.b2.uop.is_sfb, issue_slots[19].brupdate.b2.uop.is_sfb
connect slots_19.io.brupdate.b2.uop.br_type, issue_slots[19].brupdate.b2.uop.br_type
connect slots_19.io.brupdate.b2.uop.br_tag, issue_slots[19].brupdate.b2.uop.br_tag
connect slots_19.io.brupdate.b2.uop.br_mask, issue_slots[19].brupdate.b2.uop.br_mask
connect slots_19.io.brupdate.b2.uop.dis_col_sel, issue_slots[19].brupdate.b2.uop.dis_col_sel
connect slots_19.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[19].brupdate.b2.uop.iw_p3_bypass_hint
connect slots_19.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[19].brupdate.b2.uop.iw_p2_bypass_hint
connect slots_19.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[19].brupdate.b2.uop.iw_p1_bypass_hint
connect slots_19.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[19].brupdate.b2.uop.iw_p2_speculative_child
connect slots_19.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[19].brupdate.b2.uop.iw_p1_speculative_child
connect slots_19.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[19].brupdate.b2.uop.iw_issued_partial_dgen
connect slots_19.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[19].brupdate.b2.uop.iw_issued_partial_agen
connect slots_19.io.brupdate.b2.uop.iw_issued, issue_slots[19].brupdate.b2.uop.iw_issued
connect slots_19.io.brupdate.b2.uop.fu_code[0], issue_slots[19].brupdate.b2.uop.fu_code[0]
connect slots_19.io.brupdate.b2.uop.fu_code[1], issue_slots[19].brupdate.b2.uop.fu_code[1]
connect slots_19.io.brupdate.b2.uop.fu_code[2], issue_slots[19].brupdate.b2.uop.fu_code[2]
connect slots_19.io.brupdate.b2.uop.fu_code[3], issue_slots[19].brupdate.b2.uop.fu_code[3]
connect slots_19.io.brupdate.b2.uop.fu_code[4], issue_slots[19].brupdate.b2.uop.fu_code[4]
connect slots_19.io.brupdate.b2.uop.fu_code[5], issue_slots[19].brupdate.b2.uop.fu_code[5]
connect slots_19.io.brupdate.b2.uop.fu_code[6], issue_slots[19].brupdate.b2.uop.fu_code[6]
connect slots_19.io.brupdate.b2.uop.fu_code[7], issue_slots[19].brupdate.b2.uop.fu_code[7]
connect slots_19.io.brupdate.b2.uop.fu_code[8], issue_slots[19].brupdate.b2.uop.fu_code[8]
connect slots_19.io.brupdate.b2.uop.fu_code[9], issue_slots[19].brupdate.b2.uop.fu_code[9]
connect slots_19.io.brupdate.b2.uop.iq_type[0], issue_slots[19].brupdate.b2.uop.iq_type[0]
connect slots_19.io.brupdate.b2.uop.iq_type[1], issue_slots[19].brupdate.b2.uop.iq_type[1]
connect slots_19.io.brupdate.b2.uop.iq_type[2], issue_slots[19].brupdate.b2.uop.iq_type[2]
connect slots_19.io.brupdate.b2.uop.iq_type[3], issue_slots[19].brupdate.b2.uop.iq_type[3]
connect slots_19.io.brupdate.b2.uop.debug_pc, issue_slots[19].brupdate.b2.uop.debug_pc
connect slots_19.io.brupdate.b2.uop.is_rvc, issue_slots[19].brupdate.b2.uop.is_rvc
connect slots_19.io.brupdate.b2.uop.debug_inst, issue_slots[19].brupdate.b2.uop.debug_inst
connect slots_19.io.brupdate.b2.uop.inst, issue_slots[19].brupdate.b2.uop.inst
connect slots_19.io.brupdate.b1.mispredict_mask, issue_slots[19].brupdate.b1.mispredict_mask
connect slots_19.io.brupdate.b1.resolve_mask, issue_slots[19].brupdate.b1.resolve_mask
connect issue_slots[19].out_uop.debug_tsrc, slots_19.io.out_uop.debug_tsrc
connect issue_slots[19].out_uop.debug_fsrc, slots_19.io.out_uop.debug_fsrc
connect issue_slots[19].out_uop.bp_xcpt_if, slots_19.io.out_uop.bp_xcpt_if
connect issue_slots[19].out_uop.bp_debug_if, slots_19.io.out_uop.bp_debug_if
connect issue_slots[19].out_uop.xcpt_ma_if, slots_19.io.out_uop.xcpt_ma_if
connect issue_slots[19].out_uop.xcpt_ae_if, slots_19.io.out_uop.xcpt_ae_if
connect issue_slots[19].out_uop.xcpt_pf_if, slots_19.io.out_uop.xcpt_pf_if
connect issue_slots[19].out_uop.fp_typ, slots_19.io.out_uop.fp_typ
connect issue_slots[19].out_uop.fp_rm, slots_19.io.out_uop.fp_rm
connect issue_slots[19].out_uop.fp_val, slots_19.io.out_uop.fp_val
connect issue_slots[19].out_uop.fcn_op, slots_19.io.out_uop.fcn_op
connect issue_slots[19].out_uop.fcn_dw, slots_19.io.out_uop.fcn_dw
connect issue_slots[19].out_uop.frs3_en, slots_19.io.out_uop.frs3_en
connect issue_slots[19].out_uop.lrs2_rtype, slots_19.io.out_uop.lrs2_rtype
connect issue_slots[19].out_uop.lrs1_rtype, slots_19.io.out_uop.lrs1_rtype
connect issue_slots[19].out_uop.dst_rtype, slots_19.io.out_uop.dst_rtype
connect issue_slots[19].out_uop.lrs3, slots_19.io.out_uop.lrs3
connect issue_slots[19].out_uop.lrs2, slots_19.io.out_uop.lrs2
connect issue_slots[19].out_uop.lrs1, slots_19.io.out_uop.lrs1
connect issue_slots[19].out_uop.ldst, slots_19.io.out_uop.ldst
connect issue_slots[19].out_uop.ldst_is_rs1, slots_19.io.out_uop.ldst_is_rs1
connect issue_slots[19].out_uop.csr_cmd, slots_19.io.out_uop.csr_cmd
connect issue_slots[19].out_uop.flush_on_commit, slots_19.io.out_uop.flush_on_commit
connect issue_slots[19].out_uop.is_unique, slots_19.io.out_uop.is_unique
connect issue_slots[19].out_uop.uses_stq, slots_19.io.out_uop.uses_stq
connect issue_slots[19].out_uop.uses_ldq, slots_19.io.out_uop.uses_ldq
connect issue_slots[19].out_uop.mem_signed, slots_19.io.out_uop.mem_signed
connect issue_slots[19].out_uop.mem_size, slots_19.io.out_uop.mem_size
connect issue_slots[19].out_uop.mem_cmd, slots_19.io.out_uop.mem_cmd
connect issue_slots[19].out_uop.exc_cause, slots_19.io.out_uop.exc_cause
connect issue_slots[19].out_uop.exception, slots_19.io.out_uop.exception
connect issue_slots[19].out_uop.stale_pdst, slots_19.io.out_uop.stale_pdst
connect issue_slots[19].out_uop.ppred_busy, slots_19.io.out_uop.ppred_busy
connect issue_slots[19].out_uop.prs3_busy, slots_19.io.out_uop.prs3_busy
connect issue_slots[19].out_uop.prs2_busy, slots_19.io.out_uop.prs2_busy
connect issue_slots[19].out_uop.prs1_busy, slots_19.io.out_uop.prs1_busy
connect issue_slots[19].out_uop.ppred, slots_19.io.out_uop.ppred
connect issue_slots[19].out_uop.prs3, slots_19.io.out_uop.prs3
connect issue_slots[19].out_uop.prs2, slots_19.io.out_uop.prs2
connect issue_slots[19].out_uop.prs1, slots_19.io.out_uop.prs1
connect issue_slots[19].out_uop.pdst, slots_19.io.out_uop.pdst
connect issue_slots[19].out_uop.rxq_idx, slots_19.io.out_uop.rxq_idx
connect issue_slots[19].out_uop.stq_idx, slots_19.io.out_uop.stq_idx
connect issue_slots[19].out_uop.ldq_idx, slots_19.io.out_uop.ldq_idx
connect issue_slots[19].out_uop.rob_idx, slots_19.io.out_uop.rob_idx
connect issue_slots[19].out_uop.fp_ctrl.vec, slots_19.io.out_uop.fp_ctrl.vec
connect issue_slots[19].out_uop.fp_ctrl.wflags, slots_19.io.out_uop.fp_ctrl.wflags
connect issue_slots[19].out_uop.fp_ctrl.sqrt, slots_19.io.out_uop.fp_ctrl.sqrt
connect issue_slots[19].out_uop.fp_ctrl.div, slots_19.io.out_uop.fp_ctrl.div
connect issue_slots[19].out_uop.fp_ctrl.fma, slots_19.io.out_uop.fp_ctrl.fma
connect issue_slots[19].out_uop.fp_ctrl.fastpipe, slots_19.io.out_uop.fp_ctrl.fastpipe
connect issue_slots[19].out_uop.fp_ctrl.toint, slots_19.io.out_uop.fp_ctrl.toint
connect issue_slots[19].out_uop.fp_ctrl.fromint, slots_19.io.out_uop.fp_ctrl.fromint
connect issue_slots[19].out_uop.fp_ctrl.typeTagOut, slots_19.io.out_uop.fp_ctrl.typeTagOut
connect issue_slots[19].out_uop.fp_ctrl.typeTagIn, slots_19.io.out_uop.fp_ctrl.typeTagIn
connect issue_slots[19].out_uop.fp_ctrl.swap23, slots_19.io.out_uop.fp_ctrl.swap23
connect issue_slots[19].out_uop.fp_ctrl.swap12, slots_19.io.out_uop.fp_ctrl.swap12
connect issue_slots[19].out_uop.fp_ctrl.ren3, slots_19.io.out_uop.fp_ctrl.ren3
connect issue_slots[19].out_uop.fp_ctrl.ren2, slots_19.io.out_uop.fp_ctrl.ren2
connect issue_slots[19].out_uop.fp_ctrl.ren1, slots_19.io.out_uop.fp_ctrl.ren1
connect issue_slots[19].out_uop.fp_ctrl.wen, slots_19.io.out_uop.fp_ctrl.wen
connect issue_slots[19].out_uop.fp_ctrl.ldst, slots_19.io.out_uop.fp_ctrl.ldst
connect issue_slots[19].out_uop.op2_sel, slots_19.io.out_uop.op2_sel
connect issue_slots[19].out_uop.op1_sel, slots_19.io.out_uop.op1_sel
connect issue_slots[19].out_uop.imm_packed, slots_19.io.out_uop.imm_packed
connect issue_slots[19].out_uop.pimm, slots_19.io.out_uop.pimm
connect issue_slots[19].out_uop.imm_sel, slots_19.io.out_uop.imm_sel
connect issue_slots[19].out_uop.imm_rename, slots_19.io.out_uop.imm_rename
connect issue_slots[19].out_uop.taken, slots_19.io.out_uop.taken
connect issue_slots[19].out_uop.pc_lob, slots_19.io.out_uop.pc_lob
connect issue_slots[19].out_uop.edge_inst, slots_19.io.out_uop.edge_inst
connect issue_slots[19].out_uop.ftq_idx, slots_19.io.out_uop.ftq_idx
connect issue_slots[19].out_uop.is_mov, slots_19.io.out_uop.is_mov
connect issue_slots[19].out_uop.is_rocc, slots_19.io.out_uop.is_rocc
connect issue_slots[19].out_uop.is_sys_pc2epc, slots_19.io.out_uop.is_sys_pc2epc
connect issue_slots[19].out_uop.is_eret, slots_19.io.out_uop.is_eret
connect issue_slots[19].out_uop.is_amo, slots_19.io.out_uop.is_amo
connect issue_slots[19].out_uop.is_sfence, slots_19.io.out_uop.is_sfence
connect issue_slots[19].out_uop.is_fencei, slots_19.io.out_uop.is_fencei
connect issue_slots[19].out_uop.is_fence, slots_19.io.out_uop.is_fence
connect issue_slots[19].out_uop.is_sfb, slots_19.io.out_uop.is_sfb
connect issue_slots[19].out_uop.br_type, slots_19.io.out_uop.br_type
connect issue_slots[19].out_uop.br_tag, slots_19.io.out_uop.br_tag
connect issue_slots[19].out_uop.br_mask, slots_19.io.out_uop.br_mask
connect issue_slots[19].out_uop.dis_col_sel, slots_19.io.out_uop.dis_col_sel
connect issue_slots[19].out_uop.iw_p3_bypass_hint, slots_19.io.out_uop.iw_p3_bypass_hint
connect issue_slots[19].out_uop.iw_p2_bypass_hint, slots_19.io.out_uop.iw_p2_bypass_hint
connect issue_slots[19].out_uop.iw_p1_bypass_hint, slots_19.io.out_uop.iw_p1_bypass_hint
connect issue_slots[19].out_uop.iw_p2_speculative_child, slots_19.io.out_uop.iw_p2_speculative_child
connect issue_slots[19].out_uop.iw_p1_speculative_child, slots_19.io.out_uop.iw_p1_speculative_child
connect issue_slots[19].out_uop.iw_issued_partial_dgen, slots_19.io.out_uop.iw_issued_partial_dgen
connect issue_slots[19].out_uop.iw_issued_partial_agen, slots_19.io.out_uop.iw_issued_partial_agen
connect issue_slots[19].out_uop.iw_issued, slots_19.io.out_uop.iw_issued
connect issue_slots[19].out_uop.fu_code[0], slots_19.io.out_uop.fu_code[0]
connect issue_slots[19].out_uop.fu_code[1], slots_19.io.out_uop.fu_code[1]
connect issue_slots[19].out_uop.fu_code[2], slots_19.io.out_uop.fu_code[2]
connect issue_slots[19].out_uop.fu_code[3], slots_19.io.out_uop.fu_code[3]
connect issue_slots[19].out_uop.fu_code[4], slots_19.io.out_uop.fu_code[4]
connect issue_slots[19].out_uop.fu_code[5], slots_19.io.out_uop.fu_code[5]
connect issue_slots[19].out_uop.fu_code[6], slots_19.io.out_uop.fu_code[6]
connect issue_slots[19].out_uop.fu_code[7], slots_19.io.out_uop.fu_code[7]
connect issue_slots[19].out_uop.fu_code[8], slots_19.io.out_uop.fu_code[8]
connect issue_slots[19].out_uop.fu_code[9], slots_19.io.out_uop.fu_code[9]
connect issue_slots[19].out_uop.iq_type[0], slots_19.io.out_uop.iq_type[0]
connect issue_slots[19].out_uop.iq_type[1], slots_19.io.out_uop.iq_type[1]
connect issue_slots[19].out_uop.iq_type[2], slots_19.io.out_uop.iq_type[2]
connect issue_slots[19].out_uop.iq_type[3], slots_19.io.out_uop.iq_type[3]
connect issue_slots[19].out_uop.debug_pc, slots_19.io.out_uop.debug_pc
connect issue_slots[19].out_uop.is_rvc, slots_19.io.out_uop.is_rvc
connect issue_slots[19].out_uop.debug_inst, slots_19.io.out_uop.debug_inst
connect issue_slots[19].out_uop.inst, slots_19.io.out_uop.inst
connect slots_19.io.in_uop.bits.debug_tsrc, issue_slots[19].in_uop.bits.debug_tsrc
connect slots_19.io.in_uop.bits.debug_fsrc, issue_slots[19].in_uop.bits.debug_fsrc
connect slots_19.io.in_uop.bits.bp_xcpt_if, issue_slots[19].in_uop.bits.bp_xcpt_if
connect slots_19.io.in_uop.bits.bp_debug_if, issue_slots[19].in_uop.bits.bp_debug_if
connect slots_19.io.in_uop.bits.xcpt_ma_if, issue_slots[19].in_uop.bits.xcpt_ma_if
connect slots_19.io.in_uop.bits.xcpt_ae_if, issue_slots[19].in_uop.bits.xcpt_ae_if
connect slots_19.io.in_uop.bits.xcpt_pf_if, issue_slots[19].in_uop.bits.xcpt_pf_if
connect slots_19.io.in_uop.bits.fp_typ, issue_slots[19].in_uop.bits.fp_typ
connect slots_19.io.in_uop.bits.fp_rm, issue_slots[19].in_uop.bits.fp_rm
connect slots_19.io.in_uop.bits.fp_val, issue_slots[19].in_uop.bits.fp_val
connect slots_19.io.in_uop.bits.fcn_op, issue_slots[19].in_uop.bits.fcn_op
connect slots_19.io.in_uop.bits.fcn_dw, issue_slots[19].in_uop.bits.fcn_dw
connect slots_19.io.in_uop.bits.frs3_en, issue_slots[19].in_uop.bits.frs3_en
connect slots_19.io.in_uop.bits.lrs2_rtype, issue_slots[19].in_uop.bits.lrs2_rtype
connect slots_19.io.in_uop.bits.lrs1_rtype, issue_slots[19].in_uop.bits.lrs1_rtype
connect slots_19.io.in_uop.bits.dst_rtype, issue_slots[19].in_uop.bits.dst_rtype
connect slots_19.io.in_uop.bits.lrs3, issue_slots[19].in_uop.bits.lrs3
connect slots_19.io.in_uop.bits.lrs2, issue_slots[19].in_uop.bits.lrs2
connect slots_19.io.in_uop.bits.lrs1, issue_slots[19].in_uop.bits.lrs1
connect slots_19.io.in_uop.bits.ldst, issue_slots[19].in_uop.bits.ldst
connect slots_19.io.in_uop.bits.ldst_is_rs1, issue_slots[19].in_uop.bits.ldst_is_rs1
connect slots_19.io.in_uop.bits.csr_cmd, issue_slots[19].in_uop.bits.csr_cmd
connect slots_19.io.in_uop.bits.flush_on_commit, issue_slots[19].in_uop.bits.flush_on_commit
connect slots_19.io.in_uop.bits.is_unique, issue_slots[19].in_uop.bits.is_unique
connect slots_19.io.in_uop.bits.uses_stq, issue_slots[19].in_uop.bits.uses_stq
connect slots_19.io.in_uop.bits.uses_ldq, issue_slots[19].in_uop.bits.uses_ldq
connect slots_19.io.in_uop.bits.mem_signed, issue_slots[19].in_uop.bits.mem_signed
connect slots_19.io.in_uop.bits.mem_size, issue_slots[19].in_uop.bits.mem_size
connect slots_19.io.in_uop.bits.mem_cmd, issue_slots[19].in_uop.bits.mem_cmd
connect slots_19.io.in_uop.bits.exc_cause, issue_slots[19].in_uop.bits.exc_cause
connect slots_19.io.in_uop.bits.exception, issue_slots[19].in_uop.bits.exception
connect slots_19.io.in_uop.bits.stale_pdst, issue_slots[19].in_uop.bits.stale_pdst
connect slots_19.io.in_uop.bits.ppred_busy, issue_slots[19].in_uop.bits.ppred_busy
connect slots_19.io.in_uop.bits.prs3_busy, issue_slots[19].in_uop.bits.prs3_busy
connect slots_19.io.in_uop.bits.prs2_busy, issue_slots[19].in_uop.bits.prs2_busy
connect slots_19.io.in_uop.bits.prs1_busy, issue_slots[19].in_uop.bits.prs1_busy
connect slots_19.io.in_uop.bits.ppred, issue_slots[19].in_uop.bits.ppred
connect slots_19.io.in_uop.bits.prs3, issue_slots[19].in_uop.bits.prs3
connect slots_19.io.in_uop.bits.prs2, issue_slots[19].in_uop.bits.prs2
connect slots_19.io.in_uop.bits.prs1, issue_slots[19].in_uop.bits.prs1
connect slots_19.io.in_uop.bits.pdst, issue_slots[19].in_uop.bits.pdst
connect slots_19.io.in_uop.bits.rxq_idx, issue_slots[19].in_uop.bits.rxq_idx
connect slots_19.io.in_uop.bits.stq_idx, issue_slots[19].in_uop.bits.stq_idx
connect slots_19.io.in_uop.bits.ldq_idx, issue_slots[19].in_uop.bits.ldq_idx
connect slots_19.io.in_uop.bits.rob_idx, issue_slots[19].in_uop.bits.rob_idx
connect slots_19.io.in_uop.bits.fp_ctrl.vec, issue_slots[19].in_uop.bits.fp_ctrl.vec
connect slots_19.io.in_uop.bits.fp_ctrl.wflags, issue_slots[19].in_uop.bits.fp_ctrl.wflags
connect slots_19.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[19].in_uop.bits.fp_ctrl.sqrt
connect slots_19.io.in_uop.bits.fp_ctrl.div, issue_slots[19].in_uop.bits.fp_ctrl.div
connect slots_19.io.in_uop.bits.fp_ctrl.fma, issue_slots[19].in_uop.bits.fp_ctrl.fma
connect slots_19.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[19].in_uop.bits.fp_ctrl.fastpipe
connect slots_19.io.in_uop.bits.fp_ctrl.toint, issue_slots[19].in_uop.bits.fp_ctrl.toint
connect slots_19.io.in_uop.bits.fp_ctrl.fromint, issue_slots[19].in_uop.bits.fp_ctrl.fromint
connect slots_19.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[19].in_uop.bits.fp_ctrl.typeTagOut
connect slots_19.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[19].in_uop.bits.fp_ctrl.typeTagIn
connect slots_19.io.in_uop.bits.fp_ctrl.swap23, issue_slots[19].in_uop.bits.fp_ctrl.swap23
connect slots_19.io.in_uop.bits.fp_ctrl.swap12, issue_slots[19].in_uop.bits.fp_ctrl.swap12
connect slots_19.io.in_uop.bits.fp_ctrl.ren3, issue_slots[19].in_uop.bits.fp_ctrl.ren3
connect slots_19.io.in_uop.bits.fp_ctrl.ren2, issue_slots[19].in_uop.bits.fp_ctrl.ren2
connect slots_19.io.in_uop.bits.fp_ctrl.ren1, issue_slots[19].in_uop.bits.fp_ctrl.ren1
connect slots_19.io.in_uop.bits.fp_ctrl.wen, issue_slots[19].in_uop.bits.fp_ctrl.wen
connect slots_19.io.in_uop.bits.fp_ctrl.ldst, issue_slots[19].in_uop.bits.fp_ctrl.ldst
connect slots_19.io.in_uop.bits.op2_sel, issue_slots[19].in_uop.bits.op2_sel
connect slots_19.io.in_uop.bits.op1_sel, issue_slots[19].in_uop.bits.op1_sel
connect slots_19.io.in_uop.bits.imm_packed, issue_slots[19].in_uop.bits.imm_packed
connect slots_19.io.in_uop.bits.pimm, issue_slots[19].in_uop.bits.pimm
connect slots_19.io.in_uop.bits.imm_sel, issue_slots[19].in_uop.bits.imm_sel
connect slots_19.io.in_uop.bits.imm_rename, issue_slots[19].in_uop.bits.imm_rename
connect slots_19.io.in_uop.bits.taken, issue_slots[19].in_uop.bits.taken
connect slots_19.io.in_uop.bits.pc_lob, issue_slots[19].in_uop.bits.pc_lob
connect slots_19.io.in_uop.bits.edge_inst, issue_slots[19].in_uop.bits.edge_inst
connect slots_19.io.in_uop.bits.ftq_idx, issue_slots[19].in_uop.bits.ftq_idx
connect slots_19.io.in_uop.bits.is_mov, issue_slots[19].in_uop.bits.is_mov
connect slots_19.io.in_uop.bits.is_rocc, issue_slots[19].in_uop.bits.is_rocc
connect slots_19.io.in_uop.bits.is_sys_pc2epc, issue_slots[19].in_uop.bits.is_sys_pc2epc
connect slots_19.io.in_uop.bits.is_eret, issue_slots[19].in_uop.bits.is_eret
connect slots_19.io.in_uop.bits.is_amo, issue_slots[19].in_uop.bits.is_amo
connect slots_19.io.in_uop.bits.is_sfence, issue_slots[19].in_uop.bits.is_sfence
connect slots_19.io.in_uop.bits.is_fencei, issue_slots[19].in_uop.bits.is_fencei
connect slots_19.io.in_uop.bits.is_fence, issue_slots[19].in_uop.bits.is_fence
connect slots_19.io.in_uop.bits.is_sfb, issue_slots[19].in_uop.bits.is_sfb
connect slots_19.io.in_uop.bits.br_type, issue_slots[19].in_uop.bits.br_type
connect slots_19.io.in_uop.bits.br_tag, issue_slots[19].in_uop.bits.br_tag
connect slots_19.io.in_uop.bits.br_mask, issue_slots[19].in_uop.bits.br_mask
connect slots_19.io.in_uop.bits.dis_col_sel, issue_slots[19].in_uop.bits.dis_col_sel
connect slots_19.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[19].in_uop.bits.iw_p3_bypass_hint
connect slots_19.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[19].in_uop.bits.iw_p2_bypass_hint
connect slots_19.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[19].in_uop.bits.iw_p1_bypass_hint
connect slots_19.io.in_uop.bits.iw_p2_speculative_child, issue_slots[19].in_uop.bits.iw_p2_speculative_child
connect slots_19.io.in_uop.bits.iw_p1_speculative_child, issue_slots[19].in_uop.bits.iw_p1_speculative_child
connect slots_19.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[19].in_uop.bits.iw_issued_partial_dgen
connect slots_19.io.in_uop.bits.iw_issued_partial_agen, issue_slots[19].in_uop.bits.iw_issued_partial_agen
connect slots_19.io.in_uop.bits.iw_issued, issue_slots[19].in_uop.bits.iw_issued
connect slots_19.io.in_uop.bits.fu_code[0], issue_slots[19].in_uop.bits.fu_code[0]
connect slots_19.io.in_uop.bits.fu_code[1], issue_slots[19].in_uop.bits.fu_code[1]
connect slots_19.io.in_uop.bits.fu_code[2], issue_slots[19].in_uop.bits.fu_code[2]
connect slots_19.io.in_uop.bits.fu_code[3], issue_slots[19].in_uop.bits.fu_code[3]
connect slots_19.io.in_uop.bits.fu_code[4], issue_slots[19].in_uop.bits.fu_code[4]
connect slots_19.io.in_uop.bits.fu_code[5], issue_slots[19].in_uop.bits.fu_code[5]
connect slots_19.io.in_uop.bits.fu_code[6], issue_slots[19].in_uop.bits.fu_code[6]
connect slots_19.io.in_uop.bits.fu_code[7], issue_slots[19].in_uop.bits.fu_code[7]
connect slots_19.io.in_uop.bits.fu_code[8], issue_slots[19].in_uop.bits.fu_code[8]
connect slots_19.io.in_uop.bits.fu_code[9], issue_slots[19].in_uop.bits.fu_code[9]
connect slots_19.io.in_uop.bits.iq_type[0], issue_slots[19].in_uop.bits.iq_type[0]
connect slots_19.io.in_uop.bits.iq_type[1], issue_slots[19].in_uop.bits.iq_type[1]
connect slots_19.io.in_uop.bits.iq_type[2], issue_slots[19].in_uop.bits.iq_type[2]
connect slots_19.io.in_uop.bits.iq_type[3], issue_slots[19].in_uop.bits.iq_type[3]
connect slots_19.io.in_uop.bits.debug_pc, issue_slots[19].in_uop.bits.debug_pc
connect slots_19.io.in_uop.bits.is_rvc, issue_slots[19].in_uop.bits.is_rvc
connect slots_19.io.in_uop.bits.debug_inst, issue_slots[19].in_uop.bits.debug_inst
connect slots_19.io.in_uop.bits.inst, issue_slots[19].in_uop.bits.inst
connect slots_19.io.in_uop.valid, issue_slots[19].in_uop.valid
connect issue_slots[19].iss_uop.debug_tsrc, slots_19.io.iss_uop.debug_tsrc
connect issue_slots[19].iss_uop.debug_fsrc, slots_19.io.iss_uop.debug_fsrc
connect issue_slots[19].iss_uop.bp_xcpt_if, slots_19.io.iss_uop.bp_xcpt_if
connect issue_slots[19].iss_uop.bp_debug_if, slots_19.io.iss_uop.bp_debug_if
connect issue_slots[19].iss_uop.xcpt_ma_if, slots_19.io.iss_uop.xcpt_ma_if
connect issue_slots[19].iss_uop.xcpt_ae_if, slots_19.io.iss_uop.xcpt_ae_if
connect issue_slots[19].iss_uop.xcpt_pf_if, slots_19.io.iss_uop.xcpt_pf_if
connect issue_slots[19].iss_uop.fp_typ, slots_19.io.iss_uop.fp_typ
connect issue_slots[19].iss_uop.fp_rm, slots_19.io.iss_uop.fp_rm
connect issue_slots[19].iss_uop.fp_val, slots_19.io.iss_uop.fp_val
connect issue_slots[19].iss_uop.fcn_op, slots_19.io.iss_uop.fcn_op
connect issue_slots[19].iss_uop.fcn_dw, slots_19.io.iss_uop.fcn_dw
connect issue_slots[19].iss_uop.frs3_en, slots_19.io.iss_uop.frs3_en
connect issue_slots[19].iss_uop.lrs2_rtype, slots_19.io.iss_uop.lrs2_rtype
connect issue_slots[19].iss_uop.lrs1_rtype, slots_19.io.iss_uop.lrs1_rtype
connect issue_slots[19].iss_uop.dst_rtype, slots_19.io.iss_uop.dst_rtype
connect issue_slots[19].iss_uop.lrs3, slots_19.io.iss_uop.lrs3
connect issue_slots[19].iss_uop.lrs2, slots_19.io.iss_uop.lrs2
connect issue_slots[19].iss_uop.lrs1, slots_19.io.iss_uop.lrs1
connect issue_slots[19].iss_uop.ldst, slots_19.io.iss_uop.ldst
connect issue_slots[19].iss_uop.ldst_is_rs1, slots_19.io.iss_uop.ldst_is_rs1
connect issue_slots[19].iss_uop.csr_cmd, slots_19.io.iss_uop.csr_cmd
connect issue_slots[19].iss_uop.flush_on_commit, slots_19.io.iss_uop.flush_on_commit
connect issue_slots[19].iss_uop.is_unique, slots_19.io.iss_uop.is_unique
connect issue_slots[19].iss_uop.uses_stq, slots_19.io.iss_uop.uses_stq
connect issue_slots[19].iss_uop.uses_ldq, slots_19.io.iss_uop.uses_ldq
connect issue_slots[19].iss_uop.mem_signed, slots_19.io.iss_uop.mem_signed
connect issue_slots[19].iss_uop.mem_size, slots_19.io.iss_uop.mem_size
connect issue_slots[19].iss_uop.mem_cmd, slots_19.io.iss_uop.mem_cmd
connect issue_slots[19].iss_uop.exc_cause, slots_19.io.iss_uop.exc_cause
connect issue_slots[19].iss_uop.exception, slots_19.io.iss_uop.exception
connect issue_slots[19].iss_uop.stale_pdst, slots_19.io.iss_uop.stale_pdst
connect issue_slots[19].iss_uop.ppred_busy, slots_19.io.iss_uop.ppred_busy
connect issue_slots[19].iss_uop.prs3_busy, slots_19.io.iss_uop.prs3_busy
connect issue_slots[19].iss_uop.prs2_busy, slots_19.io.iss_uop.prs2_busy
connect issue_slots[19].iss_uop.prs1_busy, slots_19.io.iss_uop.prs1_busy
connect issue_slots[19].iss_uop.ppred, slots_19.io.iss_uop.ppred
connect issue_slots[19].iss_uop.prs3, slots_19.io.iss_uop.prs3
connect issue_slots[19].iss_uop.prs2, slots_19.io.iss_uop.prs2
connect issue_slots[19].iss_uop.prs1, slots_19.io.iss_uop.prs1
connect issue_slots[19].iss_uop.pdst, slots_19.io.iss_uop.pdst
connect issue_slots[19].iss_uop.rxq_idx, slots_19.io.iss_uop.rxq_idx
connect issue_slots[19].iss_uop.stq_idx, slots_19.io.iss_uop.stq_idx
connect issue_slots[19].iss_uop.ldq_idx, slots_19.io.iss_uop.ldq_idx
connect issue_slots[19].iss_uop.rob_idx, slots_19.io.iss_uop.rob_idx
connect issue_slots[19].iss_uop.fp_ctrl.vec, slots_19.io.iss_uop.fp_ctrl.vec
connect issue_slots[19].iss_uop.fp_ctrl.wflags, slots_19.io.iss_uop.fp_ctrl.wflags
connect issue_slots[19].iss_uop.fp_ctrl.sqrt, slots_19.io.iss_uop.fp_ctrl.sqrt
connect issue_slots[19].iss_uop.fp_ctrl.div, slots_19.io.iss_uop.fp_ctrl.div
connect issue_slots[19].iss_uop.fp_ctrl.fma, slots_19.io.iss_uop.fp_ctrl.fma
connect issue_slots[19].iss_uop.fp_ctrl.fastpipe, slots_19.io.iss_uop.fp_ctrl.fastpipe
connect issue_slots[19].iss_uop.fp_ctrl.toint, slots_19.io.iss_uop.fp_ctrl.toint
connect issue_slots[19].iss_uop.fp_ctrl.fromint, slots_19.io.iss_uop.fp_ctrl.fromint
connect issue_slots[19].iss_uop.fp_ctrl.typeTagOut, slots_19.io.iss_uop.fp_ctrl.typeTagOut
connect issue_slots[19].iss_uop.fp_ctrl.typeTagIn, slots_19.io.iss_uop.fp_ctrl.typeTagIn
connect issue_slots[19].iss_uop.fp_ctrl.swap23, slots_19.io.iss_uop.fp_ctrl.swap23
connect issue_slots[19].iss_uop.fp_ctrl.swap12, slots_19.io.iss_uop.fp_ctrl.swap12
connect issue_slots[19].iss_uop.fp_ctrl.ren3, slots_19.io.iss_uop.fp_ctrl.ren3
connect issue_slots[19].iss_uop.fp_ctrl.ren2, slots_19.io.iss_uop.fp_ctrl.ren2
connect issue_slots[19].iss_uop.fp_ctrl.ren1, slots_19.io.iss_uop.fp_ctrl.ren1
connect issue_slots[19].iss_uop.fp_ctrl.wen, slots_19.io.iss_uop.fp_ctrl.wen
connect issue_slots[19].iss_uop.fp_ctrl.ldst, slots_19.io.iss_uop.fp_ctrl.ldst
connect issue_slots[19].iss_uop.op2_sel, slots_19.io.iss_uop.op2_sel
connect issue_slots[19].iss_uop.op1_sel, slots_19.io.iss_uop.op1_sel
connect issue_slots[19].iss_uop.imm_packed, slots_19.io.iss_uop.imm_packed
connect issue_slots[19].iss_uop.pimm, slots_19.io.iss_uop.pimm
connect issue_slots[19].iss_uop.imm_sel, slots_19.io.iss_uop.imm_sel
connect issue_slots[19].iss_uop.imm_rename, slots_19.io.iss_uop.imm_rename
connect issue_slots[19].iss_uop.taken, slots_19.io.iss_uop.taken
connect issue_slots[19].iss_uop.pc_lob, slots_19.io.iss_uop.pc_lob
connect issue_slots[19].iss_uop.edge_inst, slots_19.io.iss_uop.edge_inst
connect issue_slots[19].iss_uop.ftq_idx, slots_19.io.iss_uop.ftq_idx
connect issue_slots[19].iss_uop.is_mov, slots_19.io.iss_uop.is_mov
connect issue_slots[19].iss_uop.is_rocc, slots_19.io.iss_uop.is_rocc
connect issue_slots[19].iss_uop.is_sys_pc2epc, slots_19.io.iss_uop.is_sys_pc2epc
connect issue_slots[19].iss_uop.is_eret, slots_19.io.iss_uop.is_eret
connect issue_slots[19].iss_uop.is_amo, slots_19.io.iss_uop.is_amo
connect issue_slots[19].iss_uop.is_sfence, slots_19.io.iss_uop.is_sfence
connect issue_slots[19].iss_uop.is_fencei, slots_19.io.iss_uop.is_fencei
connect issue_slots[19].iss_uop.is_fence, slots_19.io.iss_uop.is_fence
connect issue_slots[19].iss_uop.is_sfb, slots_19.io.iss_uop.is_sfb
connect issue_slots[19].iss_uop.br_type, slots_19.io.iss_uop.br_type
connect issue_slots[19].iss_uop.br_tag, slots_19.io.iss_uop.br_tag
connect issue_slots[19].iss_uop.br_mask, slots_19.io.iss_uop.br_mask
connect issue_slots[19].iss_uop.dis_col_sel, slots_19.io.iss_uop.dis_col_sel
connect issue_slots[19].iss_uop.iw_p3_bypass_hint, slots_19.io.iss_uop.iw_p3_bypass_hint
connect issue_slots[19].iss_uop.iw_p2_bypass_hint, slots_19.io.iss_uop.iw_p2_bypass_hint
connect issue_slots[19].iss_uop.iw_p1_bypass_hint, slots_19.io.iss_uop.iw_p1_bypass_hint
connect issue_slots[19].iss_uop.iw_p2_speculative_child, slots_19.io.iss_uop.iw_p2_speculative_child
connect issue_slots[19].iss_uop.iw_p1_speculative_child, slots_19.io.iss_uop.iw_p1_speculative_child
connect issue_slots[19].iss_uop.iw_issued_partial_dgen, slots_19.io.iss_uop.iw_issued_partial_dgen
connect issue_slots[19].iss_uop.iw_issued_partial_agen, slots_19.io.iss_uop.iw_issued_partial_agen
connect issue_slots[19].iss_uop.iw_issued, slots_19.io.iss_uop.iw_issued
connect issue_slots[19].iss_uop.fu_code[0], slots_19.io.iss_uop.fu_code[0]
connect issue_slots[19].iss_uop.fu_code[1], slots_19.io.iss_uop.fu_code[1]
connect issue_slots[19].iss_uop.fu_code[2], slots_19.io.iss_uop.fu_code[2]
connect issue_slots[19].iss_uop.fu_code[3], slots_19.io.iss_uop.fu_code[3]
connect issue_slots[19].iss_uop.fu_code[4], slots_19.io.iss_uop.fu_code[4]
connect issue_slots[19].iss_uop.fu_code[5], slots_19.io.iss_uop.fu_code[5]
connect issue_slots[19].iss_uop.fu_code[6], slots_19.io.iss_uop.fu_code[6]
connect issue_slots[19].iss_uop.fu_code[7], slots_19.io.iss_uop.fu_code[7]
connect issue_slots[19].iss_uop.fu_code[8], slots_19.io.iss_uop.fu_code[8]
connect issue_slots[19].iss_uop.fu_code[9], slots_19.io.iss_uop.fu_code[9]
connect issue_slots[19].iss_uop.iq_type[0], slots_19.io.iss_uop.iq_type[0]
connect issue_slots[19].iss_uop.iq_type[1], slots_19.io.iss_uop.iq_type[1]
connect issue_slots[19].iss_uop.iq_type[2], slots_19.io.iss_uop.iq_type[2]
connect issue_slots[19].iss_uop.iq_type[3], slots_19.io.iss_uop.iq_type[3]
connect issue_slots[19].iss_uop.debug_pc, slots_19.io.iss_uop.debug_pc
connect issue_slots[19].iss_uop.is_rvc, slots_19.io.iss_uop.is_rvc
connect issue_slots[19].iss_uop.debug_inst, slots_19.io.iss_uop.debug_inst
connect issue_slots[19].iss_uop.inst, slots_19.io.iss_uop.inst
connect slots_19.io.grant, issue_slots[19].grant
connect issue_slots[19].request, slots_19.io.request
connect issue_slots[19].will_be_valid, slots_19.io.will_be_valid
connect issue_slots[19].valid, slots_19.io.valid
connect issue_slots[0].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy
connect issue_slots[0].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask
connect issue_slots[0].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable
connect issue_slots[0].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc
connect issue_slots[0].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc
connect issue_slots[0].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if
connect issue_slots[0].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if
connect issue_slots[0].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if
connect issue_slots[0].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if
connect issue_slots[0].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if
connect issue_slots[0].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ
connect issue_slots[0].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm
connect issue_slots[0].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val
connect issue_slots[0].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op
connect issue_slots[0].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw
connect issue_slots[0].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en
connect issue_slots[0].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype
connect issue_slots[0].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype
connect issue_slots[0].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype
connect issue_slots[0].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3
connect issue_slots[0].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2
connect issue_slots[0].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1
connect issue_slots[0].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst
connect issue_slots[0].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1
connect issue_slots[0].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd
connect issue_slots[0].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit
connect issue_slots[0].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique
connect issue_slots[0].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq
connect issue_slots[0].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq
connect issue_slots[0].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed
connect issue_slots[0].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size
connect issue_slots[0].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd
connect issue_slots[0].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause
connect issue_slots[0].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception
connect issue_slots[0].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst
connect issue_slots[0].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy
connect issue_slots[0].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy
connect issue_slots[0].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy
connect issue_slots[0].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy
connect issue_slots[0].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred
connect issue_slots[0].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3
connect issue_slots[0].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2
connect issue_slots[0].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1
connect issue_slots[0].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst
connect issue_slots[0].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx
connect issue_slots[0].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx
connect issue_slots[0].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx
connect issue_slots[0].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx
connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec
connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags
connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt
connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div
connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma
connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe
connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint
connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint
connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23
connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12
connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3
connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2
connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1
connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen
connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst
connect issue_slots[0].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel
connect issue_slots[0].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel
connect issue_slots[0].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed
connect issue_slots[0].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm
connect issue_slots[0].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel
connect issue_slots[0].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename
connect issue_slots[0].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken
connect issue_slots[0].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob
connect issue_slots[0].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst
connect issue_slots[0].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx
connect issue_slots[0].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov
connect issue_slots[0].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc
connect issue_slots[0].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc
connect issue_slots[0].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret
connect issue_slots[0].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo
connect issue_slots[0].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence
connect issue_slots[0].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei
connect issue_slots[0].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence
connect issue_slots[0].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb
connect issue_slots[0].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type
connect issue_slots[0].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag
connect issue_slots[0].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask
connect issue_slots[0].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel
connect issue_slots[0].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint
connect issue_slots[0].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint
connect issue_slots[0].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint
connect issue_slots[0].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child
connect issue_slots[0].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child
connect issue_slots[0].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen
connect issue_slots[0].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen
connect issue_slots[0].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued
connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0]
connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1]
connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2]
connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3]
connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4]
connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5]
connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6]
connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7]
connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8]
connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9]
connect issue_slots[0].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0]
connect issue_slots[0].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1]
connect issue_slots[0].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2]
connect issue_slots[0].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3]
connect issue_slots[0].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc
connect issue_slots[0].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc
connect issue_slots[0].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst
connect issue_slots[0].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst
connect issue_slots[0].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[0].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy
connect issue_slots[0].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask
connect issue_slots[0].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable
connect issue_slots[0].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc
connect issue_slots[0].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc
connect issue_slots[0].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if
connect issue_slots[0].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if
connect issue_slots[0].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if
connect issue_slots[0].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if
connect issue_slots[0].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if
connect issue_slots[0].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ
connect issue_slots[0].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm
connect issue_slots[0].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val
connect issue_slots[0].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op
connect issue_slots[0].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw
connect issue_slots[0].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en
connect issue_slots[0].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype
connect issue_slots[0].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype
connect issue_slots[0].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype
connect issue_slots[0].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3
connect issue_slots[0].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2
connect issue_slots[0].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1
connect issue_slots[0].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst
connect issue_slots[0].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1
connect issue_slots[0].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd
connect issue_slots[0].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit
connect issue_slots[0].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique
connect issue_slots[0].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq
connect issue_slots[0].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq
connect issue_slots[0].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed
connect issue_slots[0].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size
connect issue_slots[0].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd
connect issue_slots[0].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause
connect issue_slots[0].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception
connect issue_slots[0].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst
connect issue_slots[0].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy
connect issue_slots[0].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy
connect issue_slots[0].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy
connect issue_slots[0].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy
connect issue_slots[0].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred
connect issue_slots[0].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3
connect issue_slots[0].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2
connect issue_slots[0].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1
connect issue_slots[0].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst
connect issue_slots[0].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx
connect issue_slots[0].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx
connect issue_slots[0].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx
connect issue_slots[0].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx
connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec
connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags
connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt
connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div
connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma
connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe
connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint
connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint
connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23
connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12
connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3
connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2
connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1
connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen
connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst
connect issue_slots[0].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel
connect issue_slots[0].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel
connect issue_slots[0].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed
connect issue_slots[0].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm
connect issue_slots[0].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel
connect issue_slots[0].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename
connect issue_slots[0].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken
connect issue_slots[0].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob
connect issue_slots[0].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst
connect issue_slots[0].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx
connect issue_slots[0].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov
connect issue_slots[0].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc
connect issue_slots[0].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc
connect issue_slots[0].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret
connect issue_slots[0].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo
connect issue_slots[0].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence
connect issue_slots[0].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei
connect issue_slots[0].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence
connect issue_slots[0].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb
connect issue_slots[0].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type
connect issue_slots[0].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag
connect issue_slots[0].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask
connect issue_slots[0].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel
connect issue_slots[0].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint
connect issue_slots[0].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint
connect issue_slots[0].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint
connect issue_slots[0].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child
connect issue_slots[0].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child
connect issue_slots[0].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen
connect issue_slots[0].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen
connect issue_slots[0].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued
connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0]
connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1]
connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2]
connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3]
connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4]
connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5]
connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6]
connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7]
connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8]
connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9]
connect issue_slots[0].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0]
connect issue_slots[0].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1]
connect issue_slots[0].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2]
connect issue_slots[0].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3]
connect issue_slots[0].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc
connect issue_slots[0].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc
connect issue_slots[0].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst
connect issue_slots[0].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst
connect issue_slots[0].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[0].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy
connect issue_slots[0].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask
connect issue_slots[0].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable
connect issue_slots[0].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc
connect issue_slots[0].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc
connect issue_slots[0].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if
connect issue_slots[0].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if
connect issue_slots[0].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if
connect issue_slots[0].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if
connect issue_slots[0].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if
connect issue_slots[0].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ
connect issue_slots[0].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm
connect issue_slots[0].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val
connect issue_slots[0].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op
connect issue_slots[0].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw
connect issue_slots[0].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en
connect issue_slots[0].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype
connect issue_slots[0].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype
connect issue_slots[0].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype
connect issue_slots[0].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3
connect issue_slots[0].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2
connect issue_slots[0].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1
connect issue_slots[0].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst
connect issue_slots[0].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1
connect issue_slots[0].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd
connect issue_slots[0].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit
connect issue_slots[0].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique
connect issue_slots[0].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq
connect issue_slots[0].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq
connect issue_slots[0].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed
connect issue_slots[0].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size
connect issue_slots[0].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd
connect issue_slots[0].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause
connect issue_slots[0].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception
connect issue_slots[0].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst
connect issue_slots[0].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy
connect issue_slots[0].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy
connect issue_slots[0].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy
connect issue_slots[0].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy
connect issue_slots[0].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred
connect issue_slots[0].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3
connect issue_slots[0].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2
connect issue_slots[0].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1
connect issue_slots[0].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst
connect issue_slots[0].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx
connect issue_slots[0].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx
connect issue_slots[0].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx
connect issue_slots[0].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx
connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec
connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags
connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt
connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div
connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma
connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe
connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint
connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint
connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23
connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12
connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3
connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2
connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1
connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen
connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst
connect issue_slots[0].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel
connect issue_slots[0].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel
connect issue_slots[0].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed
connect issue_slots[0].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm
connect issue_slots[0].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel
connect issue_slots[0].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename
connect issue_slots[0].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken
connect issue_slots[0].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob
connect issue_slots[0].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst
connect issue_slots[0].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx
connect issue_slots[0].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov
connect issue_slots[0].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc
connect issue_slots[0].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc
connect issue_slots[0].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret
connect issue_slots[0].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo
connect issue_slots[0].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence
connect issue_slots[0].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei
connect issue_slots[0].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence
connect issue_slots[0].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb
connect issue_slots[0].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type
connect issue_slots[0].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag
connect issue_slots[0].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask
connect issue_slots[0].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel
connect issue_slots[0].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint
connect issue_slots[0].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint
connect issue_slots[0].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint
connect issue_slots[0].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child
connect issue_slots[0].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child
connect issue_slots[0].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen
connect issue_slots[0].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen
connect issue_slots[0].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued
connect issue_slots[0].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0]
connect issue_slots[0].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1]
connect issue_slots[0].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2]
connect issue_slots[0].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3]
connect issue_slots[0].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4]
connect issue_slots[0].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5]
connect issue_slots[0].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6]
connect issue_slots[0].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7]
connect issue_slots[0].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8]
connect issue_slots[0].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9]
connect issue_slots[0].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0]
connect issue_slots[0].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1]
connect issue_slots[0].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2]
connect issue_slots[0].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3]
connect issue_slots[0].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc
connect issue_slots[0].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc
connect issue_slots[0].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst
connect issue_slots[0].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst
connect issue_slots[0].wakeup_ports[2].valid, io.wakeup_ports[2].valid
connect issue_slots[0].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy
connect issue_slots[0].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask
connect issue_slots[0].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable
connect issue_slots[0].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc
connect issue_slots[0].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc
connect issue_slots[0].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if
connect issue_slots[0].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if
connect issue_slots[0].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if
connect issue_slots[0].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if
connect issue_slots[0].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if
connect issue_slots[0].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ
connect issue_slots[0].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm
connect issue_slots[0].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val
connect issue_slots[0].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op
connect issue_slots[0].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw
connect issue_slots[0].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en
connect issue_slots[0].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype
connect issue_slots[0].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype
connect issue_slots[0].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype
connect issue_slots[0].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3
connect issue_slots[0].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2
connect issue_slots[0].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1
connect issue_slots[0].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst
connect issue_slots[0].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1
connect issue_slots[0].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd
connect issue_slots[0].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit
connect issue_slots[0].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique
connect issue_slots[0].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq
connect issue_slots[0].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq
connect issue_slots[0].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed
connect issue_slots[0].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size
connect issue_slots[0].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd
connect issue_slots[0].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause
connect issue_slots[0].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception
connect issue_slots[0].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst
connect issue_slots[0].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy
connect issue_slots[0].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy
connect issue_slots[0].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy
connect issue_slots[0].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy
connect issue_slots[0].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred
connect issue_slots[0].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3
connect issue_slots[0].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2
connect issue_slots[0].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1
connect issue_slots[0].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst
connect issue_slots[0].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx
connect issue_slots[0].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx
connect issue_slots[0].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx
connect issue_slots[0].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx
connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec
connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags
connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt
connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div
connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma
connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe
connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint
connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint
connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23
connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12
connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3
connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2
connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1
connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen
connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst
connect issue_slots[0].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel
connect issue_slots[0].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel
connect issue_slots[0].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed
connect issue_slots[0].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm
connect issue_slots[0].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel
connect issue_slots[0].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename
connect issue_slots[0].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken
connect issue_slots[0].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob
connect issue_slots[0].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst
connect issue_slots[0].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx
connect issue_slots[0].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov
connect issue_slots[0].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc
connect issue_slots[0].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc
connect issue_slots[0].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret
connect issue_slots[0].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo
connect issue_slots[0].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence
connect issue_slots[0].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei
connect issue_slots[0].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence
connect issue_slots[0].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb
connect issue_slots[0].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type
connect issue_slots[0].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag
connect issue_slots[0].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask
connect issue_slots[0].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel
connect issue_slots[0].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint
connect issue_slots[0].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint
connect issue_slots[0].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint
connect issue_slots[0].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child
connect issue_slots[0].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child
connect issue_slots[0].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen
connect issue_slots[0].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen
connect issue_slots[0].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued
connect issue_slots[0].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0]
connect issue_slots[0].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1]
connect issue_slots[0].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2]
connect issue_slots[0].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3]
connect issue_slots[0].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4]
connect issue_slots[0].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5]
connect issue_slots[0].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6]
connect issue_slots[0].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7]
connect issue_slots[0].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8]
connect issue_slots[0].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9]
connect issue_slots[0].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0]
connect issue_slots[0].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1]
connect issue_slots[0].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2]
connect issue_slots[0].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3]
connect issue_slots[0].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc
connect issue_slots[0].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc
connect issue_slots[0].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst
connect issue_slots[0].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst
connect issue_slots[0].wakeup_ports[3].valid, io.wakeup_ports[3].valid
connect issue_slots[0].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[0].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[0].child_rebusys, io.child_rebusys
connect issue_slots[0].squash_grant, io.squash_grant
connect issue_slots[0].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[0].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[0].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[0].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[0].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[0].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[0].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[0].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[0].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[0].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[0].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[0].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[0].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[0].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ
connect issue_slots[0].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm
connect issue_slots[0].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[0].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op
connect issue_slots[0].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw
connect issue_slots[0].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[0].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[0].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[0].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[0].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[0].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[0].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[0].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[0].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[0].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd
connect issue_slots[0].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[0].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[0].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[0].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[0].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[0].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[0].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[0].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[0].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[0].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[0].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[0].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[0].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[0].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[0].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[0].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[0].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[0].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[0].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[0].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[0].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[0].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[0].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[0].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec
connect issue_slots[0].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags
connect issue_slots[0].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt
connect issue_slots[0].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div
connect issue_slots[0].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma
connect issue_slots[0].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe
connect issue_slots[0].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint
connect issue_slots[0].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint
connect issue_slots[0].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut
connect issue_slots[0].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn
connect issue_slots[0].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23
connect issue_slots[0].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12
connect issue_slots[0].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3
connect issue_slots[0].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2
connect issue_slots[0].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1
connect issue_slots[0].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen
connect issue_slots[0].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst
connect issue_slots[0].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel
connect issue_slots[0].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel
connect issue_slots[0].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[0].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm
connect issue_slots[0].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel
connect issue_slots[0].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename
connect issue_slots[0].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[0].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[0].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[0].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[0].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov
connect issue_slots[0].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc
connect issue_slots[0].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[0].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret
connect issue_slots[0].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[0].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence
connect issue_slots[0].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[0].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[0].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[0].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type
connect issue_slots[0].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[0].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[0].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel
connect issue_slots[0].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint
connect issue_slots[0].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint
connect issue_slots[0].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint
connect issue_slots[0].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child
connect issue_slots[0].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child
connect issue_slots[0].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen
connect issue_slots[0].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen
connect issue_slots[0].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued
connect issue_slots[0].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0]
connect issue_slots[0].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1]
connect issue_slots[0].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2]
connect issue_slots[0].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3]
connect issue_slots[0].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4]
connect issue_slots[0].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5]
connect issue_slots[0].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6]
connect issue_slots[0].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7]
connect issue_slots[0].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8]
connect issue_slots[0].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9]
connect issue_slots[0].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0]
connect issue_slots[0].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1]
connect issue_slots[0].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2]
connect issue_slots[0].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3]
connect issue_slots[0].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[0].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[0].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[0].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[0].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[0].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[0].kill, io.flush_pipeline
connect issue_slots[1].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy
connect issue_slots[1].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask
connect issue_slots[1].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable
connect issue_slots[1].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc
connect issue_slots[1].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc
connect issue_slots[1].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if
connect issue_slots[1].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if
connect issue_slots[1].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if
connect issue_slots[1].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if
connect issue_slots[1].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if
connect issue_slots[1].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ
connect issue_slots[1].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm
connect issue_slots[1].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val
connect issue_slots[1].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op
connect issue_slots[1].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw
connect issue_slots[1].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en
connect issue_slots[1].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype
connect issue_slots[1].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype
connect issue_slots[1].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype
connect issue_slots[1].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3
connect issue_slots[1].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2
connect issue_slots[1].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1
connect issue_slots[1].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst
connect issue_slots[1].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1
connect issue_slots[1].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd
connect issue_slots[1].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit
connect issue_slots[1].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique
connect issue_slots[1].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq
connect issue_slots[1].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq
connect issue_slots[1].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed
connect issue_slots[1].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size
connect issue_slots[1].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd
connect issue_slots[1].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause
connect issue_slots[1].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception
connect issue_slots[1].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst
connect issue_slots[1].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy
connect issue_slots[1].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy
connect issue_slots[1].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy
connect issue_slots[1].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy
connect issue_slots[1].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred
connect issue_slots[1].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3
connect issue_slots[1].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2
connect issue_slots[1].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1
connect issue_slots[1].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst
connect issue_slots[1].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx
connect issue_slots[1].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx
connect issue_slots[1].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx
connect issue_slots[1].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx
connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec
connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags
connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt
connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div
connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma
connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe
connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint
connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint
connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23
connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12
connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3
connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2
connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1
connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen
connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst
connect issue_slots[1].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel
connect issue_slots[1].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel
connect issue_slots[1].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed
connect issue_slots[1].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm
connect issue_slots[1].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel
connect issue_slots[1].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename
connect issue_slots[1].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken
connect issue_slots[1].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob
connect issue_slots[1].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst
connect issue_slots[1].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx
connect issue_slots[1].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov
connect issue_slots[1].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc
connect issue_slots[1].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc
connect issue_slots[1].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret
connect issue_slots[1].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo
connect issue_slots[1].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence
connect issue_slots[1].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei
connect issue_slots[1].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence
connect issue_slots[1].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb
connect issue_slots[1].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type
connect issue_slots[1].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag
connect issue_slots[1].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask
connect issue_slots[1].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel
connect issue_slots[1].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint
connect issue_slots[1].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint
connect issue_slots[1].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint
connect issue_slots[1].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child
connect issue_slots[1].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child
connect issue_slots[1].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen
connect issue_slots[1].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen
connect issue_slots[1].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued
connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0]
connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1]
connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2]
connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3]
connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4]
connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5]
connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6]
connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7]
connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8]
connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9]
connect issue_slots[1].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0]
connect issue_slots[1].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1]
connect issue_slots[1].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2]
connect issue_slots[1].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3]
connect issue_slots[1].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc
connect issue_slots[1].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc
connect issue_slots[1].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst
connect issue_slots[1].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst
connect issue_slots[1].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[1].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy
connect issue_slots[1].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask
connect issue_slots[1].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable
connect issue_slots[1].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc
connect issue_slots[1].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc
connect issue_slots[1].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if
connect issue_slots[1].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if
connect issue_slots[1].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if
connect issue_slots[1].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if
connect issue_slots[1].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if
connect issue_slots[1].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ
connect issue_slots[1].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm
connect issue_slots[1].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val
connect issue_slots[1].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op
connect issue_slots[1].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw
connect issue_slots[1].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en
connect issue_slots[1].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype
connect issue_slots[1].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype
connect issue_slots[1].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype
connect issue_slots[1].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3
connect issue_slots[1].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2
connect issue_slots[1].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1
connect issue_slots[1].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst
connect issue_slots[1].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1
connect issue_slots[1].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd
connect issue_slots[1].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit
connect issue_slots[1].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique
connect issue_slots[1].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq
connect issue_slots[1].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq
connect issue_slots[1].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed
connect issue_slots[1].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size
connect issue_slots[1].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd
connect issue_slots[1].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause
connect issue_slots[1].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception
connect issue_slots[1].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst
connect issue_slots[1].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy
connect issue_slots[1].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy
connect issue_slots[1].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy
connect issue_slots[1].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy
connect issue_slots[1].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred
connect issue_slots[1].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3
connect issue_slots[1].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2
connect issue_slots[1].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1
connect issue_slots[1].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst
connect issue_slots[1].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx
connect issue_slots[1].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx
connect issue_slots[1].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx
connect issue_slots[1].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx
connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec
connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags
connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt
connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div
connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma
connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe
connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint
connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint
connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23
connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12
connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3
connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2
connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1
connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen
connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst
connect issue_slots[1].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel
connect issue_slots[1].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel
connect issue_slots[1].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed
connect issue_slots[1].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm
connect issue_slots[1].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel
connect issue_slots[1].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename
connect issue_slots[1].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken
connect issue_slots[1].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob
connect issue_slots[1].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst
connect issue_slots[1].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx
connect issue_slots[1].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov
connect issue_slots[1].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc
connect issue_slots[1].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc
connect issue_slots[1].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret
connect issue_slots[1].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo
connect issue_slots[1].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence
connect issue_slots[1].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei
connect issue_slots[1].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence
connect issue_slots[1].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb
connect issue_slots[1].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type
connect issue_slots[1].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag
connect issue_slots[1].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask
connect issue_slots[1].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel
connect issue_slots[1].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint
connect issue_slots[1].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint
connect issue_slots[1].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint
connect issue_slots[1].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child
connect issue_slots[1].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child
connect issue_slots[1].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen
connect issue_slots[1].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen
connect issue_slots[1].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued
connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0]
connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1]
connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2]
connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3]
connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4]
connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5]
connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6]
connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7]
connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8]
connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9]
connect issue_slots[1].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0]
connect issue_slots[1].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1]
connect issue_slots[1].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2]
connect issue_slots[1].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3]
connect issue_slots[1].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc
connect issue_slots[1].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc
connect issue_slots[1].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst
connect issue_slots[1].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst
connect issue_slots[1].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[1].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy
connect issue_slots[1].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask
connect issue_slots[1].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable
connect issue_slots[1].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc
connect issue_slots[1].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc
connect issue_slots[1].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if
connect issue_slots[1].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if
connect issue_slots[1].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if
connect issue_slots[1].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if
connect issue_slots[1].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if
connect issue_slots[1].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ
connect issue_slots[1].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm
connect issue_slots[1].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val
connect issue_slots[1].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op
connect issue_slots[1].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw
connect issue_slots[1].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en
connect issue_slots[1].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype
connect issue_slots[1].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype
connect issue_slots[1].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype
connect issue_slots[1].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3
connect issue_slots[1].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2
connect issue_slots[1].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1
connect issue_slots[1].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst
connect issue_slots[1].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1
connect issue_slots[1].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd
connect issue_slots[1].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit
connect issue_slots[1].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique
connect issue_slots[1].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq
connect issue_slots[1].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq
connect issue_slots[1].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed
connect issue_slots[1].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size
connect issue_slots[1].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd
connect issue_slots[1].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause
connect issue_slots[1].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception
connect issue_slots[1].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst
connect issue_slots[1].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy
connect issue_slots[1].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy
connect issue_slots[1].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy
connect issue_slots[1].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy
connect issue_slots[1].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred
connect issue_slots[1].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3
connect issue_slots[1].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2
connect issue_slots[1].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1
connect issue_slots[1].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst
connect issue_slots[1].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx
connect issue_slots[1].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx
connect issue_slots[1].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx
connect issue_slots[1].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx
connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec
connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags
connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt
connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div
connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma
connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe
connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint
connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint
connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23
connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12
connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3
connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2
connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1
connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen
connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst
connect issue_slots[1].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel
connect issue_slots[1].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel
connect issue_slots[1].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed
connect issue_slots[1].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm
connect issue_slots[1].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel
connect issue_slots[1].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename
connect issue_slots[1].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken
connect issue_slots[1].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob
connect issue_slots[1].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst
connect issue_slots[1].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx
connect issue_slots[1].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov
connect issue_slots[1].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc
connect issue_slots[1].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc
connect issue_slots[1].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret
connect issue_slots[1].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo
connect issue_slots[1].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence
connect issue_slots[1].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei
connect issue_slots[1].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence
connect issue_slots[1].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb
connect issue_slots[1].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type
connect issue_slots[1].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag
connect issue_slots[1].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask
connect issue_slots[1].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel
connect issue_slots[1].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint
connect issue_slots[1].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint
connect issue_slots[1].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint
connect issue_slots[1].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child
connect issue_slots[1].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child
connect issue_slots[1].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen
connect issue_slots[1].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen
connect issue_slots[1].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued
connect issue_slots[1].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0]
connect issue_slots[1].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1]
connect issue_slots[1].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2]
connect issue_slots[1].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3]
connect issue_slots[1].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4]
connect issue_slots[1].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5]
connect issue_slots[1].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6]
connect issue_slots[1].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7]
connect issue_slots[1].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8]
connect issue_slots[1].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9]
connect issue_slots[1].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0]
connect issue_slots[1].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1]
connect issue_slots[1].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2]
connect issue_slots[1].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3]
connect issue_slots[1].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc
connect issue_slots[1].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc
connect issue_slots[1].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst
connect issue_slots[1].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst
connect issue_slots[1].wakeup_ports[2].valid, io.wakeup_ports[2].valid
connect issue_slots[1].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy
connect issue_slots[1].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask
connect issue_slots[1].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable
connect issue_slots[1].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc
connect issue_slots[1].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc
connect issue_slots[1].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if
connect issue_slots[1].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if
connect issue_slots[1].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if
connect issue_slots[1].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if
connect issue_slots[1].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if
connect issue_slots[1].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ
connect issue_slots[1].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm
connect issue_slots[1].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val
connect issue_slots[1].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op
connect issue_slots[1].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw
connect issue_slots[1].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en
connect issue_slots[1].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype
connect issue_slots[1].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype
connect issue_slots[1].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype
connect issue_slots[1].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3
connect issue_slots[1].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2
connect issue_slots[1].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1
connect issue_slots[1].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst
connect issue_slots[1].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1
connect issue_slots[1].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd
connect issue_slots[1].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit
connect issue_slots[1].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique
connect issue_slots[1].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq
connect issue_slots[1].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq
connect issue_slots[1].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed
connect issue_slots[1].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size
connect issue_slots[1].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd
connect issue_slots[1].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause
connect issue_slots[1].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception
connect issue_slots[1].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst
connect issue_slots[1].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy
connect issue_slots[1].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy
connect issue_slots[1].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy
connect issue_slots[1].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy
connect issue_slots[1].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred
connect issue_slots[1].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3
connect issue_slots[1].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2
connect issue_slots[1].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1
connect issue_slots[1].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst
connect issue_slots[1].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx
connect issue_slots[1].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx
connect issue_slots[1].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx
connect issue_slots[1].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx
connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec
connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags
connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt
connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div
connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma
connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe
connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint
connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint
connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23
connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12
connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3
connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2
connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1
connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen
connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst
connect issue_slots[1].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel
connect issue_slots[1].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel
connect issue_slots[1].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed
connect issue_slots[1].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm
connect issue_slots[1].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel
connect issue_slots[1].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename
connect issue_slots[1].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken
connect issue_slots[1].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob
connect issue_slots[1].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst
connect issue_slots[1].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx
connect issue_slots[1].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov
connect issue_slots[1].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc
connect issue_slots[1].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc
connect issue_slots[1].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret
connect issue_slots[1].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo
connect issue_slots[1].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence
connect issue_slots[1].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei
connect issue_slots[1].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence
connect issue_slots[1].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb
connect issue_slots[1].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type
connect issue_slots[1].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag
connect issue_slots[1].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask
connect issue_slots[1].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel
connect issue_slots[1].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint
connect issue_slots[1].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint
connect issue_slots[1].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint
connect issue_slots[1].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child
connect issue_slots[1].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child
connect issue_slots[1].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen
connect issue_slots[1].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen
connect issue_slots[1].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued
connect issue_slots[1].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0]
connect issue_slots[1].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1]
connect issue_slots[1].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2]
connect issue_slots[1].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3]
connect issue_slots[1].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4]
connect issue_slots[1].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5]
connect issue_slots[1].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6]
connect issue_slots[1].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7]
connect issue_slots[1].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8]
connect issue_slots[1].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9]
connect issue_slots[1].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0]
connect issue_slots[1].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1]
connect issue_slots[1].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2]
connect issue_slots[1].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3]
connect issue_slots[1].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc
connect issue_slots[1].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc
connect issue_slots[1].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst
connect issue_slots[1].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst
connect issue_slots[1].wakeup_ports[3].valid, io.wakeup_ports[3].valid
connect issue_slots[1].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[1].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[1].child_rebusys, io.child_rebusys
connect issue_slots[1].squash_grant, io.squash_grant
connect issue_slots[1].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[1].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[1].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[1].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[1].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[1].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[1].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[1].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[1].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[1].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[1].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[1].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[1].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[1].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ
connect issue_slots[1].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm
connect issue_slots[1].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[1].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op
connect issue_slots[1].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw
connect issue_slots[1].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[1].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[1].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[1].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[1].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[1].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[1].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[1].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[1].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[1].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd
connect issue_slots[1].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[1].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[1].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[1].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[1].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[1].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[1].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[1].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[1].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[1].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[1].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[1].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[1].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[1].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[1].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[1].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[1].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[1].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[1].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[1].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[1].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[1].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[1].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[1].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec
connect issue_slots[1].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags
connect issue_slots[1].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt
connect issue_slots[1].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div
connect issue_slots[1].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma
connect issue_slots[1].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe
connect issue_slots[1].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint
connect issue_slots[1].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint
connect issue_slots[1].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut
connect issue_slots[1].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn
connect issue_slots[1].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23
connect issue_slots[1].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12
connect issue_slots[1].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3
connect issue_slots[1].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2
connect issue_slots[1].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1
connect issue_slots[1].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen
connect issue_slots[1].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst
connect issue_slots[1].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel
connect issue_slots[1].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel
connect issue_slots[1].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[1].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm
connect issue_slots[1].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel
connect issue_slots[1].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename
connect issue_slots[1].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[1].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[1].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[1].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[1].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov
connect issue_slots[1].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc
connect issue_slots[1].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[1].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret
connect issue_slots[1].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[1].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence
connect issue_slots[1].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[1].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[1].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[1].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type
connect issue_slots[1].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[1].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[1].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel
connect issue_slots[1].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint
connect issue_slots[1].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint
connect issue_slots[1].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint
connect issue_slots[1].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child
connect issue_slots[1].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child
connect issue_slots[1].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen
connect issue_slots[1].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen
connect issue_slots[1].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued
connect issue_slots[1].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0]
connect issue_slots[1].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1]
connect issue_slots[1].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2]
connect issue_slots[1].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3]
connect issue_slots[1].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4]
connect issue_slots[1].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5]
connect issue_slots[1].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6]
connect issue_slots[1].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7]
connect issue_slots[1].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8]
connect issue_slots[1].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9]
connect issue_slots[1].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0]
connect issue_slots[1].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1]
connect issue_slots[1].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2]
connect issue_slots[1].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3]
connect issue_slots[1].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[1].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[1].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[1].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[1].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[1].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[1].kill, io.flush_pipeline
connect issue_slots[2].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy
connect issue_slots[2].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask
connect issue_slots[2].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable
connect issue_slots[2].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc
connect issue_slots[2].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc
connect issue_slots[2].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if
connect issue_slots[2].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if
connect issue_slots[2].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if
connect issue_slots[2].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if
connect issue_slots[2].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if
connect issue_slots[2].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ
connect issue_slots[2].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm
connect issue_slots[2].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val
connect issue_slots[2].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op
connect issue_slots[2].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw
connect issue_slots[2].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en
connect issue_slots[2].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype
connect issue_slots[2].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype
connect issue_slots[2].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype
connect issue_slots[2].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3
connect issue_slots[2].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2
connect issue_slots[2].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1
connect issue_slots[2].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst
connect issue_slots[2].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1
connect issue_slots[2].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd
connect issue_slots[2].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit
connect issue_slots[2].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique
connect issue_slots[2].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq
connect issue_slots[2].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq
connect issue_slots[2].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed
connect issue_slots[2].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size
connect issue_slots[2].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd
connect issue_slots[2].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause
connect issue_slots[2].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception
connect issue_slots[2].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst
connect issue_slots[2].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy
connect issue_slots[2].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy
connect issue_slots[2].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy
connect issue_slots[2].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy
connect issue_slots[2].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred
connect issue_slots[2].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3
connect issue_slots[2].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2
connect issue_slots[2].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1
connect issue_slots[2].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst
connect issue_slots[2].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx
connect issue_slots[2].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx
connect issue_slots[2].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx
connect issue_slots[2].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx
connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec
connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags
connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt
connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div
connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma
connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe
connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint
connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint
connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23
connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12
connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3
connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2
connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1
connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen
connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst
connect issue_slots[2].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel
connect issue_slots[2].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel
connect issue_slots[2].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed
connect issue_slots[2].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm
connect issue_slots[2].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel
connect issue_slots[2].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename
connect issue_slots[2].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken
connect issue_slots[2].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob
connect issue_slots[2].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst
connect issue_slots[2].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx
connect issue_slots[2].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov
connect issue_slots[2].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc
connect issue_slots[2].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc
connect issue_slots[2].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret
connect issue_slots[2].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo
connect issue_slots[2].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence
connect issue_slots[2].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei
connect issue_slots[2].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence
connect issue_slots[2].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb
connect issue_slots[2].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type
connect issue_slots[2].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag
connect issue_slots[2].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask
connect issue_slots[2].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel
connect issue_slots[2].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint
connect issue_slots[2].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint
connect issue_slots[2].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint
connect issue_slots[2].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child
connect issue_slots[2].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child
connect issue_slots[2].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen
connect issue_slots[2].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen
connect issue_slots[2].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued
connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0]
connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1]
connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2]
connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3]
connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4]
connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5]
connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6]
connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7]
connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8]
connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9]
connect issue_slots[2].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0]
connect issue_slots[2].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1]
connect issue_slots[2].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2]
connect issue_slots[2].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3]
connect issue_slots[2].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc
connect issue_slots[2].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc
connect issue_slots[2].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst
connect issue_slots[2].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst
connect issue_slots[2].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[2].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy
connect issue_slots[2].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask
connect issue_slots[2].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable
connect issue_slots[2].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc
connect issue_slots[2].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc
connect issue_slots[2].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if
connect issue_slots[2].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if
connect issue_slots[2].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if
connect issue_slots[2].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if
connect issue_slots[2].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if
connect issue_slots[2].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ
connect issue_slots[2].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm
connect issue_slots[2].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val
connect issue_slots[2].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op
connect issue_slots[2].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw
connect issue_slots[2].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en
connect issue_slots[2].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype
connect issue_slots[2].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype
connect issue_slots[2].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype
connect issue_slots[2].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3
connect issue_slots[2].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2
connect issue_slots[2].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1
connect issue_slots[2].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst
connect issue_slots[2].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1
connect issue_slots[2].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd
connect issue_slots[2].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit
connect issue_slots[2].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique
connect issue_slots[2].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq
connect issue_slots[2].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq
connect issue_slots[2].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed
connect issue_slots[2].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size
connect issue_slots[2].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd
connect issue_slots[2].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause
connect issue_slots[2].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception
connect issue_slots[2].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst
connect issue_slots[2].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy
connect issue_slots[2].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy
connect issue_slots[2].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy
connect issue_slots[2].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy
connect issue_slots[2].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred
connect issue_slots[2].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3
connect issue_slots[2].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2
connect issue_slots[2].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1
connect issue_slots[2].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst
connect issue_slots[2].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx
connect issue_slots[2].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx
connect issue_slots[2].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx
connect issue_slots[2].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx
connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec
connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags
connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt
connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div
connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma
connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe
connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint
connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint
connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23
connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12
connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3
connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2
connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1
connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen
connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst
connect issue_slots[2].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel
connect issue_slots[2].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel
connect issue_slots[2].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed
connect issue_slots[2].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm
connect issue_slots[2].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel
connect issue_slots[2].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename
connect issue_slots[2].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken
connect issue_slots[2].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob
connect issue_slots[2].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst
connect issue_slots[2].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx
connect issue_slots[2].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov
connect issue_slots[2].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc
connect issue_slots[2].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc
connect issue_slots[2].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret
connect issue_slots[2].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo
connect issue_slots[2].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence
connect issue_slots[2].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei
connect issue_slots[2].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence
connect issue_slots[2].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb
connect issue_slots[2].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type
connect issue_slots[2].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag
connect issue_slots[2].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask
connect issue_slots[2].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel
connect issue_slots[2].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint
connect issue_slots[2].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint
connect issue_slots[2].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint
connect issue_slots[2].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child
connect issue_slots[2].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child
connect issue_slots[2].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen
connect issue_slots[2].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen
connect issue_slots[2].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued
connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0]
connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1]
connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2]
connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3]
connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4]
connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5]
connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6]
connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7]
connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8]
connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9]
connect issue_slots[2].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0]
connect issue_slots[2].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1]
connect issue_slots[2].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2]
connect issue_slots[2].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3]
connect issue_slots[2].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc
connect issue_slots[2].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc
connect issue_slots[2].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst
connect issue_slots[2].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst
connect issue_slots[2].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[2].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy
connect issue_slots[2].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask
connect issue_slots[2].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable
connect issue_slots[2].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc
connect issue_slots[2].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc
connect issue_slots[2].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if
connect issue_slots[2].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if
connect issue_slots[2].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if
connect issue_slots[2].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if
connect issue_slots[2].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if
connect issue_slots[2].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ
connect issue_slots[2].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm
connect issue_slots[2].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val
connect issue_slots[2].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op
connect issue_slots[2].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw
connect issue_slots[2].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en
connect issue_slots[2].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype
connect issue_slots[2].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype
connect issue_slots[2].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype
connect issue_slots[2].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3
connect issue_slots[2].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2
connect issue_slots[2].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1
connect issue_slots[2].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst
connect issue_slots[2].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1
connect issue_slots[2].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd
connect issue_slots[2].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit
connect issue_slots[2].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique
connect issue_slots[2].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq
connect issue_slots[2].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq
connect issue_slots[2].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed
connect issue_slots[2].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size
connect issue_slots[2].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd
connect issue_slots[2].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause
connect issue_slots[2].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception
connect issue_slots[2].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst
connect issue_slots[2].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy
connect issue_slots[2].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy
connect issue_slots[2].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy
connect issue_slots[2].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy
connect issue_slots[2].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred
connect issue_slots[2].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3
connect issue_slots[2].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2
connect issue_slots[2].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1
connect issue_slots[2].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst
connect issue_slots[2].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx
connect issue_slots[2].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx
connect issue_slots[2].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx
connect issue_slots[2].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx
connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec
connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags
connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt
connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div
connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma
connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe
connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint
connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint
connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23
connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12
connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3
connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2
connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1
connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen
connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst
connect issue_slots[2].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel
connect issue_slots[2].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel
connect issue_slots[2].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed
connect issue_slots[2].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm
connect issue_slots[2].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel
connect issue_slots[2].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename
connect issue_slots[2].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken
connect issue_slots[2].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob
connect issue_slots[2].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst
connect issue_slots[2].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx
connect issue_slots[2].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov
connect issue_slots[2].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc
connect issue_slots[2].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc
connect issue_slots[2].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret
connect issue_slots[2].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo
connect issue_slots[2].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence
connect issue_slots[2].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei
connect issue_slots[2].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence
connect issue_slots[2].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb
connect issue_slots[2].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type
connect issue_slots[2].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag
connect issue_slots[2].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask
connect issue_slots[2].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel
connect issue_slots[2].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint
connect issue_slots[2].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint
connect issue_slots[2].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint
connect issue_slots[2].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child
connect issue_slots[2].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child
connect issue_slots[2].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen
connect issue_slots[2].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen
connect issue_slots[2].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued
connect issue_slots[2].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0]
connect issue_slots[2].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1]
connect issue_slots[2].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2]
connect issue_slots[2].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3]
connect issue_slots[2].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4]
connect issue_slots[2].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5]
connect issue_slots[2].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6]
connect issue_slots[2].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7]
connect issue_slots[2].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8]
connect issue_slots[2].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9]
connect issue_slots[2].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0]
connect issue_slots[2].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1]
connect issue_slots[2].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2]
connect issue_slots[2].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3]
connect issue_slots[2].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc
connect issue_slots[2].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc
connect issue_slots[2].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst
connect issue_slots[2].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst
connect issue_slots[2].wakeup_ports[2].valid, io.wakeup_ports[2].valid
connect issue_slots[2].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy
connect issue_slots[2].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask
connect issue_slots[2].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable
connect issue_slots[2].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc
connect issue_slots[2].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc
connect issue_slots[2].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if
connect issue_slots[2].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if
connect issue_slots[2].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if
connect issue_slots[2].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if
connect issue_slots[2].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if
connect issue_slots[2].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ
connect issue_slots[2].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm
connect issue_slots[2].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val
connect issue_slots[2].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op
connect issue_slots[2].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw
connect issue_slots[2].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en
connect issue_slots[2].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype
connect issue_slots[2].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype
connect issue_slots[2].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype
connect issue_slots[2].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3
connect issue_slots[2].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2
connect issue_slots[2].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1
connect issue_slots[2].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst
connect issue_slots[2].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1
connect issue_slots[2].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd
connect issue_slots[2].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit
connect issue_slots[2].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique
connect issue_slots[2].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq
connect issue_slots[2].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq
connect issue_slots[2].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed
connect issue_slots[2].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size
connect issue_slots[2].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd
connect issue_slots[2].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause
connect issue_slots[2].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception
connect issue_slots[2].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst
connect issue_slots[2].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy
connect issue_slots[2].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy
connect issue_slots[2].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy
connect issue_slots[2].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy
connect issue_slots[2].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred
connect issue_slots[2].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3
connect issue_slots[2].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2
connect issue_slots[2].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1
connect issue_slots[2].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst
connect issue_slots[2].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx
connect issue_slots[2].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx
connect issue_slots[2].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx
connect issue_slots[2].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx
connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec
connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags
connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt
connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div
connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma
connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe
connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint
connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint
connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23
connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12
connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3
connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2
connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1
connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen
connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst
connect issue_slots[2].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel
connect issue_slots[2].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel
connect issue_slots[2].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed
connect issue_slots[2].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm
connect issue_slots[2].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel
connect issue_slots[2].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename
connect issue_slots[2].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken
connect issue_slots[2].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob
connect issue_slots[2].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst
connect issue_slots[2].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx
connect issue_slots[2].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov
connect issue_slots[2].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc
connect issue_slots[2].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc
connect issue_slots[2].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret
connect issue_slots[2].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo
connect issue_slots[2].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence
connect issue_slots[2].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei
connect issue_slots[2].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence
connect issue_slots[2].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb
connect issue_slots[2].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type
connect issue_slots[2].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag
connect issue_slots[2].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask
connect issue_slots[2].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel
connect issue_slots[2].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint
connect issue_slots[2].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint
connect issue_slots[2].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint
connect issue_slots[2].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child
connect issue_slots[2].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child
connect issue_slots[2].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen
connect issue_slots[2].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen
connect issue_slots[2].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued
connect issue_slots[2].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0]
connect issue_slots[2].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1]
connect issue_slots[2].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2]
connect issue_slots[2].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3]
connect issue_slots[2].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4]
connect issue_slots[2].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5]
connect issue_slots[2].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6]
connect issue_slots[2].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7]
connect issue_slots[2].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8]
connect issue_slots[2].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9]
connect issue_slots[2].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0]
connect issue_slots[2].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1]
connect issue_slots[2].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2]
connect issue_slots[2].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3]
connect issue_slots[2].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc
connect issue_slots[2].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc
connect issue_slots[2].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst
connect issue_slots[2].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst
connect issue_slots[2].wakeup_ports[3].valid, io.wakeup_ports[3].valid
connect issue_slots[2].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[2].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[2].child_rebusys, io.child_rebusys
connect issue_slots[2].squash_grant, io.squash_grant
connect issue_slots[2].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[2].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[2].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[2].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[2].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[2].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[2].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[2].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[2].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[2].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[2].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[2].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[2].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[2].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ
connect issue_slots[2].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm
connect issue_slots[2].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[2].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op
connect issue_slots[2].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw
connect issue_slots[2].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[2].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[2].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[2].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[2].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[2].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[2].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[2].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[2].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[2].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd
connect issue_slots[2].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[2].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[2].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[2].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[2].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[2].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[2].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[2].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[2].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[2].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[2].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[2].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[2].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[2].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[2].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[2].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[2].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[2].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[2].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[2].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[2].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[2].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[2].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[2].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec
connect issue_slots[2].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags
connect issue_slots[2].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt
connect issue_slots[2].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div
connect issue_slots[2].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma
connect issue_slots[2].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe
connect issue_slots[2].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint
connect issue_slots[2].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint
connect issue_slots[2].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut
connect issue_slots[2].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn
connect issue_slots[2].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23
connect issue_slots[2].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12
connect issue_slots[2].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3
connect issue_slots[2].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2
connect issue_slots[2].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1
connect issue_slots[2].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen
connect issue_slots[2].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst
connect issue_slots[2].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel
connect issue_slots[2].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel
connect issue_slots[2].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[2].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm
connect issue_slots[2].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel
connect issue_slots[2].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename
connect issue_slots[2].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[2].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[2].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[2].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[2].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov
connect issue_slots[2].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc
connect issue_slots[2].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[2].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret
connect issue_slots[2].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[2].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence
connect issue_slots[2].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[2].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[2].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[2].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type
connect issue_slots[2].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[2].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[2].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel
connect issue_slots[2].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint
connect issue_slots[2].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint
connect issue_slots[2].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint
connect issue_slots[2].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child
connect issue_slots[2].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child
connect issue_slots[2].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen
connect issue_slots[2].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen
connect issue_slots[2].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued
connect issue_slots[2].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0]
connect issue_slots[2].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1]
connect issue_slots[2].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2]
connect issue_slots[2].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3]
connect issue_slots[2].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4]
connect issue_slots[2].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5]
connect issue_slots[2].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6]
connect issue_slots[2].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7]
connect issue_slots[2].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8]
connect issue_slots[2].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9]
connect issue_slots[2].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0]
connect issue_slots[2].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1]
connect issue_slots[2].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2]
connect issue_slots[2].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3]
connect issue_slots[2].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[2].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[2].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[2].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[2].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[2].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[2].kill, io.flush_pipeline
connect issue_slots[3].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy
connect issue_slots[3].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask
connect issue_slots[3].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable
connect issue_slots[3].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc
connect issue_slots[3].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc
connect issue_slots[3].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if
connect issue_slots[3].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if
connect issue_slots[3].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if
connect issue_slots[3].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if
connect issue_slots[3].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if
connect issue_slots[3].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ
connect issue_slots[3].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm
connect issue_slots[3].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val
connect issue_slots[3].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op
connect issue_slots[3].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw
connect issue_slots[3].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en
connect issue_slots[3].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype
connect issue_slots[3].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype
connect issue_slots[3].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype
connect issue_slots[3].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3
connect issue_slots[3].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2
connect issue_slots[3].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1
connect issue_slots[3].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst
connect issue_slots[3].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1
connect issue_slots[3].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd
connect issue_slots[3].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit
connect issue_slots[3].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique
connect issue_slots[3].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq
connect issue_slots[3].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq
connect issue_slots[3].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed
connect issue_slots[3].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size
connect issue_slots[3].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd
connect issue_slots[3].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause
connect issue_slots[3].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception
connect issue_slots[3].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst
connect issue_slots[3].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy
connect issue_slots[3].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy
connect issue_slots[3].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy
connect issue_slots[3].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy
connect issue_slots[3].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred
connect issue_slots[3].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3
connect issue_slots[3].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2
connect issue_slots[3].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1
connect issue_slots[3].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst
connect issue_slots[3].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx
connect issue_slots[3].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx
connect issue_slots[3].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx
connect issue_slots[3].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx
connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec
connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags
connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt
connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div
connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma
connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe
connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint
connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint
connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23
connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12
connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3
connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2
connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1
connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen
connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst
connect issue_slots[3].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel
connect issue_slots[3].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel
connect issue_slots[3].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed
connect issue_slots[3].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm
connect issue_slots[3].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel
connect issue_slots[3].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename
connect issue_slots[3].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken
connect issue_slots[3].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob
connect issue_slots[3].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst
connect issue_slots[3].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx
connect issue_slots[3].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov
connect issue_slots[3].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc
connect issue_slots[3].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc
connect issue_slots[3].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret
connect issue_slots[3].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo
connect issue_slots[3].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence
connect issue_slots[3].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei
connect issue_slots[3].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence
connect issue_slots[3].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb
connect issue_slots[3].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type
connect issue_slots[3].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag
connect issue_slots[3].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask
connect issue_slots[3].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel
connect issue_slots[3].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint
connect issue_slots[3].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint
connect issue_slots[3].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint
connect issue_slots[3].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child
connect issue_slots[3].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child
connect issue_slots[3].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen
connect issue_slots[3].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen
connect issue_slots[3].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued
connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0]
connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1]
connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2]
connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3]
connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4]
connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5]
connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6]
connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7]
connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8]
connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9]
connect issue_slots[3].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0]
connect issue_slots[3].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1]
connect issue_slots[3].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2]
connect issue_slots[3].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3]
connect issue_slots[3].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc
connect issue_slots[3].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc
connect issue_slots[3].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst
connect issue_slots[3].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst
connect issue_slots[3].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[3].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy
connect issue_slots[3].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask
connect issue_slots[3].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable
connect issue_slots[3].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc
connect issue_slots[3].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc
connect issue_slots[3].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if
connect issue_slots[3].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if
connect issue_slots[3].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if
connect issue_slots[3].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if
connect issue_slots[3].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if
connect issue_slots[3].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ
connect issue_slots[3].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm
connect issue_slots[3].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val
connect issue_slots[3].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op
connect issue_slots[3].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw
connect issue_slots[3].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en
connect issue_slots[3].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype
connect issue_slots[3].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype
connect issue_slots[3].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype
connect issue_slots[3].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3
connect issue_slots[3].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2
connect issue_slots[3].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1
connect issue_slots[3].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst
connect issue_slots[3].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1
connect issue_slots[3].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd
connect issue_slots[3].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit
connect issue_slots[3].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique
connect issue_slots[3].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq
connect issue_slots[3].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq
connect issue_slots[3].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed
connect issue_slots[3].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size
connect issue_slots[3].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd
connect issue_slots[3].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause
connect issue_slots[3].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception
connect issue_slots[3].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst
connect issue_slots[3].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy
connect issue_slots[3].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy
connect issue_slots[3].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy
connect issue_slots[3].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy
connect issue_slots[3].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred
connect issue_slots[3].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3
connect issue_slots[3].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2
connect issue_slots[3].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1
connect issue_slots[3].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst
connect issue_slots[3].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx
connect issue_slots[3].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx
connect issue_slots[3].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx
connect issue_slots[3].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx
connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec
connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags
connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt
connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div
connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma
connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe
connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint
connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint
connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23
connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12
connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3
connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2
connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1
connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen
connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst
connect issue_slots[3].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel
connect issue_slots[3].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel
connect issue_slots[3].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed
connect issue_slots[3].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm
connect issue_slots[3].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel
connect issue_slots[3].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename
connect issue_slots[3].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken
connect issue_slots[3].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob
connect issue_slots[3].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst
connect issue_slots[3].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx
connect issue_slots[3].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov
connect issue_slots[3].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc
connect issue_slots[3].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc
connect issue_slots[3].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret
connect issue_slots[3].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo
connect issue_slots[3].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence
connect issue_slots[3].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei
connect issue_slots[3].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence
connect issue_slots[3].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb
connect issue_slots[3].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type
connect issue_slots[3].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag
connect issue_slots[3].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask
connect issue_slots[3].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel
connect issue_slots[3].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint
connect issue_slots[3].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint
connect issue_slots[3].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint
connect issue_slots[3].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child
connect issue_slots[3].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child
connect issue_slots[3].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen
connect issue_slots[3].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen
connect issue_slots[3].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued
connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0]
connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1]
connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2]
connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3]
connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4]
connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5]
connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6]
connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7]
connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8]
connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9]
connect issue_slots[3].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0]
connect issue_slots[3].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1]
connect issue_slots[3].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2]
connect issue_slots[3].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3]
connect issue_slots[3].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc
connect issue_slots[3].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc
connect issue_slots[3].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst
connect issue_slots[3].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst
connect issue_slots[3].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[3].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy
connect issue_slots[3].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask
connect issue_slots[3].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable
connect issue_slots[3].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc
connect issue_slots[3].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc
connect issue_slots[3].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if
connect issue_slots[3].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if
connect issue_slots[3].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if
connect issue_slots[3].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if
connect issue_slots[3].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if
connect issue_slots[3].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ
connect issue_slots[3].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm
connect issue_slots[3].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val
connect issue_slots[3].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op
connect issue_slots[3].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw
connect issue_slots[3].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en
connect issue_slots[3].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype
connect issue_slots[3].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype
connect issue_slots[3].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype
connect issue_slots[3].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3
connect issue_slots[3].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2
connect issue_slots[3].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1
connect issue_slots[3].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst
connect issue_slots[3].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1
connect issue_slots[3].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd
connect issue_slots[3].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit
connect issue_slots[3].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique
connect issue_slots[3].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq
connect issue_slots[3].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq
connect issue_slots[3].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed
connect issue_slots[3].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size
connect issue_slots[3].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd
connect issue_slots[3].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause
connect issue_slots[3].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception
connect issue_slots[3].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst
connect issue_slots[3].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy
connect issue_slots[3].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy
connect issue_slots[3].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy
connect issue_slots[3].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy
connect issue_slots[3].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred
connect issue_slots[3].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3
connect issue_slots[3].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2
connect issue_slots[3].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1
connect issue_slots[3].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst
connect issue_slots[3].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx
connect issue_slots[3].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx
connect issue_slots[3].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx
connect issue_slots[3].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx
connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec
connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags
connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt
connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div
connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma
connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe
connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint
connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint
connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23
connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12
connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3
connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2
connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1
connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen
connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst
connect issue_slots[3].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel
connect issue_slots[3].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel
connect issue_slots[3].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed
connect issue_slots[3].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm
connect issue_slots[3].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel
connect issue_slots[3].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename
connect issue_slots[3].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken
connect issue_slots[3].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob
connect issue_slots[3].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst
connect issue_slots[3].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx
connect issue_slots[3].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov
connect issue_slots[3].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc
connect issue_slots[3].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc
connect issue_slots[3].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret
connect issue_slots[3].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo
connect issue_slots[3].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence
connect issue_slots[3].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei
connect issue_slots[3].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence
connect issue_slots[3].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb
connect issue_slots[3].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type
connect issue_slots[3].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag
connect issue_slots[3].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask
connect issue_slots[3].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel
connect issue_slots[3].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint
connect issue_slots[3].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint
connect issue_slots[3].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint
connect issue_slots[3].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child
connect issue_slots[3].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child
connect issue_slots[3].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen
connect issue_slots[3].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen
connect issue_slots[3].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued
connect issue_slots[3].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0]
connect issue_slots[3].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1]
connect issue_slots[3].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2]
connect issue_slots[3].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3]
connect issue_slots[3].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4]
connect issue_slots[3].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5]
connect issue_slots[3].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6]
connect issue_slots[3].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7]
connect issue_slots[3].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8]
connect issue_slots[3].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9]
connect issue_slots[3].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0]
connect issue_slots[3].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1]
connect issue_slots[3].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2]
connect issue_slots[3].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3]
connect issue_slots[3].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc
connect issue_slots[3].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc
connect issue_slots[3].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst
connect issue_slots[3].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst
connect issue_slots[3].wakeup_ports[2].valid, io.wakeup_ports[2].valid
connect issue_slots[3].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy
connect issue_slots[3].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask
connect issue_slots[3].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable
connect issue_slots[3].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc
connect issue_slots[3].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc
connect issue_slots[3].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if
connect issue_slots[3].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if
connect issue_slots[3].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if
connect issue_slots[3].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if
connect issue_slots[3].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if
connect issue_slots[3].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ
connect issue_slots[3].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm
connect issue_slots[3].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val
connect issue_slots[3].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op
connect issue_slots[3].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw
connect issue_slots[3].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en
connect issue_slots[3].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype
connect issue_slots[3].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype
connect issue_slots[3].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype
connect issue_slots[3].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3
connect issue_slots[3].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2
connect issue_slots[3].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1
connect issue_slots[3].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst
connect issue_slots[3].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1
connect issue_slots[3].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd
connect issue_slots[3].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit
connect issue_slots[3].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique
connect issue_slots[3].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq
connect issue_slots[3].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq
connect issue_slots[3].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed
connect issue_slots[3].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size
connect issue_slots[3].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd
connect issue_slots[3].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause
connect issue_slots[3].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception
connect issue_slots[3].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst
connect issue_slots[3].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy
connect issue_slots[3].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy
connect issue_slots[3].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy
connect issue_slots[3].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy
connect issue_slots[3].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred
connect issue_slots[3].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3
connect issue_slots[3].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2
connect issue_slots[3].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1
connect issue_slots[3].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst
connect issue_slots[3].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx
connect issue_slots[3].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx
connect issue_slots[3].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx
connect issue_slots[3].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx
connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec
connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags
connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt
connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div
connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma
connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe
connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint
connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint
connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23
connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12
connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3
connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2
connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1
connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen
connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst
connect issue_slots[3].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel
connect issue_slots[3].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel
connect issue_slots[3].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed
connect issue_slots[3].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm
connect issue_slots[3].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel
connect issue_slots[3].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename
connect issue_slots[3].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken
connect issue_slots[3].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob
connect issue_slots[3].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst
connect issue_slots[3].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx
connect issue_slots[3].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov
connect issue_slots[3].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc
connect issue_slots[3].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc
connect issue_slots[3].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret
connect issue_slots[3].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo
connect issue_slots[3].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence
connect issue_slots[3].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei
connect issue_slots[3].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence
connect issue_slots[3].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb
connect issue_slots[3].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type
connect issue_slots[3].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag
connect issue_slots[3].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask
connect issue_slots[3].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel
connect issue_slots[3].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint
connect issue_slots[3].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint
connect issue_slots[3].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint
connect issue_slots[3].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child
connect issue_slots[3].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child
connect issue_slots[3].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen
connect issue_slots[3].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen
connect issue_slots[3].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued
connect issue_slots[3].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0]
connect issue_slots[3].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1]
connect issue_slots[3].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2]
connect issue_slots[3].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3]
connect issue_slots[3].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4]
connect issue_slots[3].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5]
connect issue_slots[3].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6]
connect issue_slots[3].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7]
connect issue_slots[3].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8]
connect issue_slots[3].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9]
connect issue_slots[3].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0]
connect issue_slots[3].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1]
connect issue_slots[3].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2]
connect issue_slots[3].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3]
connect issue_slots[3].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc
connect issue_slots[3].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc
connect issue_slots[3].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst
connect issue_slots[3].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst
connect issue_slots[3].wakeup_ports[3].valid, io.wakeup_ports[3].valid
connect issue_slots[3].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[3].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[3].child_rebusys, io.child_rebusys
connect issue_slots[3].squash_grant, io.squash_grant
connect issue_slots[3].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[3].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[3].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[3].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[3].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[3].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[3].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[3].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[3].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[3].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[3].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[3].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[3].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[3].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ
connect issue_slots[3].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm
connect issue_slots[3].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[3].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op
connect issue_slots[3].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw
connect issue_slots[3].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[3].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[3].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[3].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[3].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[3].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[3].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[3].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[3].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[3].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd
connect issue_slots[3].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[3].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[3].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[3].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[3].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[3].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[3].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[3].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[3].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[3].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[3].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[3].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[3].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[3].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[3].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[3].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[3].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[3].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[3].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[3].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[3].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[3].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[3].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[3].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec
connect issue_slots[3].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags
connect issue_slots[3].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt
connect issue_slots[3].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div
connect issue_slots[3].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma
connect issue_slots[3].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe
connect issue_slots[3].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint
connect issue_slots[3].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint
connect issue_slots[3].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut
connect issue_slots[3].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn
connect issue_slots[3].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23
connect issue_slots[3].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12
connect issue_slots[3].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3
connect issue_slots[3].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2
connect issue_slots[3].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1
connect issue_slots[3].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen
connect issue_slots[3].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst
connect issue_slots[3].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel
connect issue_slots[3].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel
connect issue_slots[3].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[3].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm
connect issue_slots[3].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel
connect issue_slots[3].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename
connect issue_slots[3].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[3].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[3].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[3].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[3].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov
connect issue_slots[3].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc
connect issue_slots[3].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[3].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret
connect issue_slots[3].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[3].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence
connect issue_slots[3].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[3].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[3].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[3].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type
connect issue_slots[3].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[3].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[3].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel
connect issue_slots[3].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint
connect issue_slots[3].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint
connect issue_slots[3].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint
connect issue_slots[3].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child
connect issue_slots[3].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child
connect issue_slots[3].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen
connect issue_slots[3].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen
connect issue_slots[3].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued
connect issue_slots[3].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0]
connect issue_slots[3].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1]
connect issue_slots[3].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2]
connect issue_slots[3].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3]
connect issue_slots[3].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4]
connect issue_slots[3].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5]
connect issue_slots[3].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6]
connect issue_slots[3].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7]
connect issue_slots[3].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8]
connect issue_slots[3].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9]
connect issue_slots[3].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0]
connect issue_slots[3].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1]
connect issue_slots[3].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2]
connect issue_slots[3].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3]
connect issue_slots[3].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[3].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[3].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[3].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[3].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[3].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[3].kill, io.flush_pipeline
connect issue_slots[4].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy
connect issue_slots[4].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask
connect issue_slots[4].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable
connect issue_slots[4].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc
connect issue_slots[4].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc
connect issue_slots[4].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if
connect issue_slots[4].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if
connect issue_slots[4].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if
connect issue_slots[4].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if
connect issue_slots[4].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if
connect issue_slots[4].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ
connect issue_slots[4].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm
connect issue_slots[4].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val
connect issue_slots[4].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op
connect issue_slots[4].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw
connect issue_slots[4].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en
connect issue_slots[4].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype
connect issue_slots[4].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype
connect issue_slots[4].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype
connect issue_slots[4].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3
connect issue_slots[4].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2
connect issue_slots[4].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1
connect issue_slots[4].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst
connect issue_slots[4].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1
connect issue_slots[4].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd
connect issue_slots[4].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit
connect issue_slots[4].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique
connect issue_slots[4].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq
connect issue_slots[4].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq
connect issue_slots[4].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed
connect issue_slots[4].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size
connect issue_slots[4].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd
connect issue_slots[4].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause
connect issue_slots[4].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception
connect issue_slots[4].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst
connect issue_slots[4].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy
connect issue_slots[4].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy
connect issue_slots[4].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy
connect issue_slots[4].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy
connect issue_slots[4].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred
connect issue_slots[4].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3
connect issue_slots[4].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2
connect issue_slots[4].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1
connect issue_slots[4].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst
connect issue_slots[4].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx
connect issue_slots[4].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx
connect issue_slots[4].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx
connect issue_slots[4].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx
connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec
connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags
connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt
connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div
connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma
connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe
connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint
connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint
connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23
connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12
connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3
connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2
connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1
connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen
connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst
connect issue_slots[4].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel
connect issue_slots[4].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel
connect issue_slots[4].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed
connect issue_slots[4].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm
connect issue_slots[4].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel
connect issue_slots[4].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename
connect issue_slots[4].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken
connect issue_slots[4].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob
connect issue_slots[4].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst
connect issue_slots[4].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx
connect issue_slots[4].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov
connect issue_slots[4].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc
connect issue_slots[4].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc
connect issue_slots[4].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret
connect issue_slots[4].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo
connect issue_slots[4].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence
connect issue_slots[4].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei
connect issue_slots[4].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence
connect issue_slots[4].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb
connect issue_slots[4].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type
connect issue_slots[4].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag
connect issue_slots[4].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask
connect issue_slots[4].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel
connect issue_slots[4].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint
connect issue_slots[4].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint
connect issue_slots[4].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint
connect issue_slots[4].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child
connect issue_slots[4].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child
connect issue_slots[4].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen
connect issue_slots[4].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen
connect issue_slots[4].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued
connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0]
connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1]
connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2]
connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3]
connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4]
connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5]
connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6]
connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7]
connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8]
connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9]
connect issue_slots[4].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0]
connect issue_slots[4].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1]
connect issue_slots[4].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2]
connect issue_slots[4].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3]
connect issue_slots[4].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc
connect issue_slots[4].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc
connect issue_slots[4].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst
connect issue_slots[4].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst
connect issue_slots[4].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[4].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy
connect issue_slots[4].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask
connect issue_slots[4].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable
connect issue_slots[4].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc
connect issue_slots[4].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc
connect issue_slots[4].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if
connect issue_slots[4].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if
connect issue_slots[4].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if
connect issue_slots[4].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if
connect issue_slots[4].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if
connect issue_slots[4].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ
connect issue_slots[4].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm
connect issue_slots[4].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val
connect issue_slots[4].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op
connect issue_slots[4].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw
connect issue_slots[4].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en
connect issue_slots[4].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype
connect issue_slots[4].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype
connect issue_slots[4].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype
connect issue_slots[4].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3
connect issue_slots[4].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2
connect issue_slots[4].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1
connect issue_slots[4].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst
connect issue_slots[4].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1
connect issue_slots[4].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd
connect issue_slots[4].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit
connect issue_slots[4].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique
connect issue_slots[4].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq
connect issue_slots[4].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq
connect issue_slots[4].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed
connect issue_slots[4].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size
connect issue_slots[4].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd
connect issue_slots[4].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause
connect issue_slots[4].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception
connect issue_slots[4].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst
connect issue_slots[4].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy
connect issue_slots[4].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy
connect issue_slots[4].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy
connect issue_slots[4].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy
connect issue_slots[4].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred
connect issue_slots[4].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3
connect issue_slots[4].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2
connect issue_slots[4].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1
connect issue_slots[4].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst
connect issue_slots[4].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx
connect issue_slots[4].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx
connect issue_slots[4].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx
connect issue_slots[4].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx
connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec
connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags
connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt
connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div
connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma
connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe
connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint
connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint
connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23
connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12
connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3
connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2
connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1
connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen
connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst
connect issue_slots[4].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel
connect issue_slots[4].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel
connect issue_slots[4].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed
connect issue_slots[4].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm
connect issue_slots[4].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel
connect issue_slots[4].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename
connect issue_slots[4].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken
connect issue_slots[4].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob
connect issue_slots[4].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst
connect issue_slots[4].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx
connect issue_slots[4].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov
connect issue_slots[4].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc
connect issue_slots[4].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc
connect issue_slots[4].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret
connect issue_slots[4].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo
connect issue_slots[4].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence
connect issue_slots[4].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei
connect issue_slots[4].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence
connect issue_slots[4].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb
connect issue_slots[4].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type
connect issue_slots[4].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag
connect issue_slots[4].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask
connect issue_slots[4].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel
connect issue_slots[4].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint
connect issue_slots[4].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint
connect issue_slots[4].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint
connect issue_slots[4].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child
connect issue_slots[4].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child
connect issue_slots[4].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen
connect issue_slots[4].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen
connect issue_slots[4].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued
connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0]
connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1]
connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2]
connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3]
connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4]
connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5]
connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6]
connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7]
connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8]
connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9]
connect issue_slots[4].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0]
connect issue_slots[4].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1]
connect issue_slots[4].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2]
connect issue_slots[4].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3]
connect issue_slots[4].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc
connect issue_slots[4].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc
connect issue_slots[4].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst
connect issue_slots[4].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst
connect issue_slots[4].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[4].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy
connect issue_slots[4].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask
connect issue_slots[4].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable
connect issue_slots[4].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc
connect issue_slots[4].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc
connect issue_slots[4].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if
connect issue_slots[4].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if
connect issue_slots[4].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if
connect issue_slots[4].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if
connect issue_slots[4].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if
connect issue_slots[4].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ
connect issue_slots[4].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm
connect issue_slots[4].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val
connect issue_slots[4].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op
connect issue_slots[4].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw
connect issue_slots[4].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en
connect issue_slots[4].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype
connect issue_slots[4].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype
connect issue_slots[4].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype
connect issue_slots[4].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3
connect issue_slots[4].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2
connect issue_slots[4].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1
connect issue_slots[4].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst
connect issue_slots[4].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1
connect issue_slots[4].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd
connect issue_slots[4].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit
connect issue_slots[4].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique
connect issue_slots[4].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq
connect issue_slots[4].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq
connect issue_slots[4].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed
connect issue_slots[4].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size
connect issue_slots[4].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd
connect issue_slots[4].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause
connect issue_slots[4].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception
connect issue_slots[4].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst
connect issue_slots[4].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy
connect issue_slots[4].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy
connect issue_slots[4].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy
connect issue_slots[4].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy
connect issue_slots[4].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred
connect issue_slots[4].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3
connect issue_slots[4].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2
connect issue_slots[4].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1
connect issue_slots[4].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst
connect issue_slots[4].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx
connect issue_slots[4].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx
connect issue_slots[4].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx
connect issue_slots[4].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx
connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec
connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags
connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt
connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div
connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma
connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe
connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint
connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint
connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23
connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12
connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3
connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2
connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1
connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen
connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst
connect issue_slots[4].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel
connect issue_slots[4].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel
connect issue_slots[4].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed
connect issue_slots[4].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm
connect issue_slots[4].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel
connect issue_slots[4].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename
connect issue_slots[4].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken
connect issue_slots[4].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob
connect issue_slots[4].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst
connect issue_slots[4].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx
connect issue_slots[4].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov
connect issue_slots[4].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc
connect issue_slots[4].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc
connect issue_slots[4].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret
connect issue_slots[4].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo
connect issue_slots[4].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence
connect issue_slots[4].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei
connect issue_slots[4].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence
connect issue_slots[4].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb
connect issue_slots[4].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type
connect issue_slots[4].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag
connect issue_slots[4].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask
connect issue_slots[4].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel
connect issue_slots[4].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint
connect issue_slots[4].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint
connect issue_slots[4].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint
connect issue_slots[4].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child
connect issue_slots[4].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child
connect issue_slots[4].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen
connect issue_slots[4].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen
connect issue_slots[4].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued
connect issue_slots[4].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0]
connect issue_slots[4].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1]
connect issue_slots[4].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2]
connect issue_slots[4].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3]
connect issue_slots[4].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4]
connect issue_slots[4].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5]
connect issue_slots[4].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6]
connect issue_slots[4].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7]
connect issue_slots[4].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8]
connect issue_slots[4].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9]
connect issue_slots[4].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0]
connect issue_slots[4].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1]
connect issue_slots[4].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2]
connect issue_slots[4].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3]
connect issue_slots[4].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc
connect issue_slots[4].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc
connect issue_slots[4].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst
connect issue_slots[4].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst
connect issue_slots[4].wakeup_ports[2].valid, io.wakeup_ports[2].valid
connect issue_slots[4].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy
connect issue_slots[4].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask
connect issue_slots[4].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable
connect issue_slots[4].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc
connect issue_slots[4].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc
connect issue_slots[4].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if
connect issue_slots[4].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if
connect issue_slots[4].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if
connect issue_slots[4].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if
connect issue_slots[4].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if
connect issue_slots[4].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ
connect issue_slots[4].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm
connect issue_slots[4].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val
connect issue_slots[4].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op
connect issue_slots[4].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw
connect issue_slots[4].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en
connect issue_slots[4].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype
connect issue_slots[4].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype
connect issue_slots[4].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype
connect issue_slots[4].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3
connect issue_slots[4].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2
connect issue_slots[4].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1
connect issue_slots[4].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst
connect issue_slots[4].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1
connect issue_slots[4].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd
connect issue_slots[4].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit
connect issue_slots[4].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique
connect issue_slots[4].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq
connect issue_slots[4].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq
connect issue_slots[4].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed
connect issue_slots[4].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size
connect issue_slots[4].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd
connect issue_slots[4].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause
connect issue_slots[4].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception
connect issue_slots[4].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst
connect issue_slots[4].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy
connect issue_slots[4].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy
connect issue_slots[4].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy
connect issue_slots[4].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy
connect issue_slots[4].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred
connect issue_slots[4].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3
connect issue_slots[4].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2
connect issue_slots[4].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1
connect issue_slots[4].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst
connect issue_slots[4].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx
connect issue_slots[4].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx
connect issue_slots[4].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx
connect issue_slots[4].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx
connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec
connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags
connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt
connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div
connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma
connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe
connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint
connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint
connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23
connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12
connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3
connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2
connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1
connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen
connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst
connect issue_slots[4].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel
connect issue_slots[4].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel
connect issue_slots[4].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed
connect issue_slots[4].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm
connect issue_slots[4].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel
connect issue_slots[4].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename
connect issue_slots[4].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken
connect issue_slots[4].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob
connect issue_slots[4].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst
connect issue_slots[4].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx
connect issue_slots[4].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov
connect issue_slots[4].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc
connect issue_slots[4].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc
connect issue_slots[4].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret
connect issue_slots[4].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo
connect issue_slots[4].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence
connect issue_slots[4].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei
connect issue_slots[4].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence
connect issue_slots[4].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb
connect issue_slots[4].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type
connect issue_slots[4].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag
connect issue_slots[4].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask
connect issue_slots[4].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel
connect issue_slots[4].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint
connect issue_slots[4].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint
connect issue_slots[4].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint
connect issue_slots[4].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child
connect issue_slots[4].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child
connect issue_slots[4].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen
connect issue_slots[4].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen
connect issue_slots[4].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued
connect issue_slots[4].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0]
connect issue_slots[4].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1]
connect issue_slots[4].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2]
connect issue_slots[4].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3]
connect issue_slots[4].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4]
connect issue_slots[4].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5]
connect issue_slots[4].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6]
connect issue_slots[4].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7]
connect issue_slots[4].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8]
connect issue_slots[4].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9]
connect issue_slots[4].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0]
connect issue_slots[4].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1]
connect issue_slots[4].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2]
connect issue_slots[4].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3]
connect issue_slots[4].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc
connect issue_slots[4].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc
connect issue_slots[4].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst
connect issue_slots[4].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst
connect issue_slots[4].wakeup_ports[3].valid, io.wakeup_ports[3].valid
connect issue_slots[4].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[4].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[4].child_rebusys, io.child_rebusys
connect issue_slots[4].squash_grant, io.squash_grant
connect issue_slots[4].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[4].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[4].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[4].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[4].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[4].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[4].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[4].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[4].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[4].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[4].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[4].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[4].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[4].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ
connect issue_slots[4].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm
connect issue_slots[4].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[4].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op
connect issue_slots[4].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw
connect issue_slots[4].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[4].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[4].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[4].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[4].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[4].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[4].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[4].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[4].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[4].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd
connect issue_slots[4].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[4].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[4].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[4].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[4].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[4].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[4].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[4].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[4].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[4].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[4].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[4].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[4].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[4].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[4].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[4].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[4].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[4].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[4].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[4].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[4].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[4].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[4].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[4].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec
connect issue_slots[4].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags
connect issue_slots[4].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt
connect issue_slots[4].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div
connect issue_slots[4].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma
connect issue_slots[4].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe
connect issue_slots[4].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint
connect issue_slots[4].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint
connect issue_slots[4].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut
connect issue_slots[4].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn
connect issue_slots[4].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23
connect issue_slots[4].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12
connect issue_slots[4].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3
connect issue_slots[4].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2
connect issue_slots[4].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1
connect issue_slots[4].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen
connect issue_slots[4].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst
connect issue_slots[4].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel
connect issue_slots[4].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel
connect issue_slots[4].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[4].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm
connect issue_slots[4].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel
connect issue_slots[4].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename
connect issue_slots[4].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[4].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[4].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[4].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[4].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov
connect issue_slots[4].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc
connect issue_slots[4].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[4].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret
connect issue_slots[4].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[4].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence
connect issue_slots[4].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[4].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[4].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[4].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type
connect issue_slots[4].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[4].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[4].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel
connect issue_slots[4].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint
connect issue_slots[4].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint
connect issue_slots[4].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint
connect issue_slots[4].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child
connect issue_slots[4].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child
connect issue_slots[4].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen
connect issue_slots[4].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen
connect issue_slots[4].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued
connect issue_slots[4].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0]
connect issue_slots[4].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1]
connect issue_slots[4].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2]
connect issue_slots[4].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3]
connect issue_slots[4].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4]
connect issue_slots[4].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5]
connect issue_slots[4].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6]
connect issue_slots[4].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7]
connect issue_slots[4].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8]
connect issue_slots[4].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9]
connect issue_slots[4].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0]
connect issue_slots[4].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1]
connect issue_slots[4].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2]
connect issue_slots[4].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3]
connect issue_slots[4].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[4].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[4].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[4].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[4].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[4].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[4].kill, io.flush_pipeline
connect issue_slots[5].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy
connect issue_slots[5].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask
connect issue_slots[5].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable
connect issue_slots[5].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc
connect issue_slots[5].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc
connect issue_slots[5].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if
connect issue_slots[5].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if
connect issue_slots[5].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if
connect issue_slots[5].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if
connect issue_slots[5].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if
connect issue_slots[5].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ
connect issue_slots[5].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm
connect issue_slots[5].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val
connect issue_slots[5].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op
connect issue_slots[5].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw
connect issue_slots[5].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en
connect issue_slots[5].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype
connect issue_slots[5].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype
connect issue_slots[5].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype
connect issue_slots[5].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3
connect issue_slots[5].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2
connect issue_slots[5].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1
connect issue_slots[5].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst
connect issue_slots[5].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1
connect issue_slots[5].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd
connect issue_slots[5].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit
connect issue_slots[5].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique
connect issue_slots[5].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq
connect issue_slots[5].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq
connect issue_slots[5].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed
connect issue_slots[5].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size
connect issue_slots[5].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd
connect issue_slots[5].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause
connect issue_slots[5].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception
connect issue_slots[5].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst
connect issue_slots[5].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy
connect issue_slots[5].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy
connect issue_slots[5].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy
connect issue_slots[5].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy
connect issue_slots[5].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred
connect issue_slots[5].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3
connect issue_slots[5].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2
connect issue_slots[5].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1
connect issue_slots[5].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst
connect issue_slots[5].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx
connect issue_slots[5].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx
connect issue_slots[5].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx
connect issue_slots[5].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx
connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec
connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags
connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt
connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div
connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma
connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe
connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint
connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint
connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23
connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12
connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3
connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2
connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1
connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen
connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst
connect issue_slots[5].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel
connect issue_slots[5].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel
connect issue_slots[5].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed
connect issue_slots[5].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm
connect issue_slots[5].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel
connect issue_slots[5].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename
connect issue_slots[5].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken
connect issue_slots[5].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob
connect issue_slots[5].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst
connect issue_slots[5].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx
connect issue_slots[5].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov
connect issue_slots[5].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc
connect issue_slots[5].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc
connect issue_slots[5].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret
connect issue_slots[5].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo
connect issue_slots[5].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence
connect issue_slots[5].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei
connect issue_slots[5].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence
connect issue_slots[5].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb
connect issue_slots[5].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type
connect issue_slots[5].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag
connect issue_slots[5].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask
connect issue_slots[5].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel
connect issue_slots[5].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint
connect issue_slots[5].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint
connect issue_slots[5].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint
connect issue_slots[5].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child
connect issue_slots[5].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child
connect issue_slots[5].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen
connect issue_slots[5].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen
connect issue_slots[5].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued
connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0]
connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1]
connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2]
connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3]
connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4]
connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5]
connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6]
connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7]
connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8]
connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9]
connect issue_slots[5].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0]
connect issue_slots[5].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1]
connect issue_slots[5].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2]
connect issue_slots[5].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3]
connect issue_slots[5].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc
connect issue_slots[5].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc
connect issue_slots[5].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst
connect issue_slots[5].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst
connect issue_slots[5].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[5].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy
connect issue_slots[5].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask
connect issue_slots[5].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable
connect issue_slots[5].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc
connect issue_slots[5].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc
connect issue_slots[5].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if
connect issue_slots[5].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if
connect issue_slots[5].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if
connect issue_slots[5].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if
connect issue_slots[5].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if
connect issue_slots[5].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ
connect issue_slots[5].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm
connect issue_slots[5].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val
connect issue_slots[5].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op
connect issue_slots[5].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw
connect issue_slots[5].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en
connect issue_slots[5].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype
connect issue_slots[5].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype
connect issue_slots[5].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype
connect issue_slots[5].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3
connect issue_slots[5].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2
connect issue_slots[5].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1
connect issue_slots[5].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst
connect issue_slots[5].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1
connect issue_slots[5].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd
connect issue_slots[5].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit
connect issue_slots[5].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique
connect issue_slots[5].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq
connect issue_slots[5].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq
connect issue_slots[5].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed
connect issue_slots[5].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size
connect issue_slots[5].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd
connect issue_slots[5].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause
connect issue_slots[5].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception
connect issue_slots[5].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst
connect issue_slots[5].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy
connect issue_slots[5].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy
connect issue_slots[5].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy
connect issue_slots[5].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy
connect issue_slots[5].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred
connect issue_slots[5].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3
connect issue_slots[5].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2
connect issue_slots[5].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1
connect issue_slots[5].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst
connect issue_slots[5].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx
connect issue_slots[5].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx
connect issue_slots[5].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx
connect issue_slots[5].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx
connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec
connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags
connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt
connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div
connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma
connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe
connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint
connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint
connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23
connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12
connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3
connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2
connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1
connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen
connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst
connect issue_slots[5].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel
connect issue_slots[5].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel
connect issue_slots[5].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed
connect issue_slots[5].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm
connect issue_slots[5].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel
connect issue_slots[5].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename
connect issue_slots[5].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken
connect issue_slots[5].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob
connect issue_slots[5].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst
connect issue_slots[5].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx
connect issue_slots[5].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov
connect issue_slots[5].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc
connect issue_slots[5].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc
connect issue_slots[5].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret
connect issue_slots[5].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo
connect issue_slots[5].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence
connect issue_slots[5].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei
connect issue_slots[5].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence
connect issue_slots[5].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb
connect issue_slots[5].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type
connect issue_slots[5].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag
connect issue_slots[5].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask
connect issue_slots[5].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel
connect issue_slots[5].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint
connect issue_slots[5].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint
connect issue_slots[5].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint
connect issue_slots[5].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child
connect issue_slots[5].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child
connect issue_slots[5].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen
connect issue_slots[5].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen
connect issue_slots[5].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued
connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0]
connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1]
connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2]
connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3]
connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4]
connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5]
connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6]
connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7]
connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8]
connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9]
connect issue_slots[5].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0]
connect issue_slots[5].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1]
connect issue_slots[5].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2]
connect issue_slots[5].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3]
connect issue_slots[5].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc
connect issue_slots[5].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc
connect issue_slots[5].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst
connect issue_slots[5].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst
connect issue_slots[5].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[5].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy
connect issue_slots[5].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask
connect issue_slots[5].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable
connect issue_slots[5].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc
connect issue_slots[5].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc
connect issue_slots[5].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if
connect issue_slots[5].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if
connect issue_slots[5].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if
connect issue_slots[5].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if
connect issue_slots[5].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if
connect issue_slots[5].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ
connect issue_slots[5].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm
connect issue_slots[5].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val
connect issue_slots[5].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op
connect issue_slots[5].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw
connect issue_slots[5].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en
connect issue_slots[5].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype
connect issue_slots[5].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype
connect issue_slots[5].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype
connect issue_slots[5].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3
connect issue_slots[5].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2
connect issue_slots[5].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1
connect issue_slots[5].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst
connect issue_slots[5].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1
connect issue_slots[5].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd
connect issue_slots[5].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit
connect issue_slots[5].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique
connect issue_slots[5].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq
connect issue_slots[5].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq
connect issue_slots[5].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed
connect issue_slots[5].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size
connect issue_slots[5].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd
connect issue_slots[5].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause
connect issue_slots[5].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception
connect issue_slots[5].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst
connect issue_slots[5].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy
connect issue_slots[5].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy
connect issue_slots[5].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy
connect issue_slots[5].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy
connect issue_slots[5].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred
connect issue_slots[5].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3
connect issue_slots[5].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2
connect issue_slots[5].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1
connect issue_slots[5].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst
connect issue_slots[5].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx
connect issue_slots[5].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx
connect issue_slots[5].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx
connect issue_slots[5].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx
connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec
connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags
connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt
connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div
connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma
connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe
connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint
connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint
connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23
connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12
connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3
connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2
connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1
connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen
connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst
connect issue_slots[5].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel
connect issue_slots[5].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel
connect issue_slots[5].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed
connect issue_slots[5].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm
connect issue_slots[5].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel
connect issue_slots[5].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename
connect issue_slots[5].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken
connect issue_slots[5].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob
connect issue_slots[5].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst
connect issue_slots[5].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx
connect issue_slots[5].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov
connect issue_slots[5].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc
connect issue_slots[5].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc
connect issue_slots[5].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret
connect issue_slots[5].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo
connect issue_slots[5].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence
connect issue_slots[5].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei
connect issue_slots[5].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence
connect issue_slots[5].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb
connect issue_slots[5].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type
connect issue_slots[5].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag
connect issue_slots[5].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask
connect issue_slots[5].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel
connect issue_slots[5].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint
connect issue_slots[5].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint
connect issue_slots[5].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint
connect issue_slots[5].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child
connect issue_slots[5].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child
connect issue_slots[5].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen
connect issue_slots[5].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen
connect issue_slots[5].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued
connect issue_slots[5].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0]
connect issue_slots[5].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1]
connect issue_slots[5].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2]
connect issue_slots[5].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3]
connect issue_slots[5].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4]
connect issue_slots[5].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5]
connect issue_slots[5].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6]
connect issue_slots[5].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7]
connect issue_slots[5].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8]
connect issue_slots[5].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9]
connect issue_slots[5].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0]
connect issue_slots[5].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1]
connect issue_slots[5].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2]
connect issue_slots[5].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3]
connect issue_slots[5].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc
connect issue_slots[5].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc
connect issue_slots[5].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst
connect issue_slots[5].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst
connect issue_slots[5].wakeup_ports[2].valid, io.wakeup_ports[2].valid
connect issue_slots[5].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy
connect issue_slots[5].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask
connect issue_slots[5].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable
connect issue_slots[5].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc
connect issue_slots[5].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc
connect issue_slots[5].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if
connect issue_slots[5].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if
connect issue_slots[5].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if
connect issue_slots[5].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if
connect issue_slots[5].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if
connect issue_slots[5].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ
connect issue_slots[5].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm
connect issue_slots[5].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val
connect issue_slots[5].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op
connect issue_slots[5].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw
connect issue_slots[5].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en
connect issue_slots[5].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype
connect issue_slots[5].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype
connect issue_slots[5].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype
connect issue_slots[5].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3
connect issue_slots[5].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2
connect issue_slots[5].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1
connect issue_slots[5].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst
connect issue_slots[5].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1
connect issue_slots[5].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd
connect issue_slots[5].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit
connect issue_slots[5].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique
connect issue_slots[5].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq
connect issue_slots[5].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq
connect issue_slots[5].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed
connect issue_slots[5].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size
connect issue_slots[5].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd
connect issue_slots[5].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause
connect issue_slots[5].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception
connect issue_slots[5].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst
connect issue_slots[5].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy
connect issue_slots[5].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy
connect issue_slots[5].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy
connect issue_slots[5].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy
connect issue_slots[5].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred
connect issue_slots[5].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3
connect issue_slots[5].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2
connect issue_slots[5].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1
connect issue_slots[5].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst
connect issue_slots[5].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx
connect issue_slots[5].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx
connect issue_slots[5].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx
connect issue_slots[5].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx
connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec
connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags
connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt
connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div
connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma
connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe
connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint
connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint
connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23
connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12
connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3
connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2
connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1
connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen
connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst
connect issue_slots[5].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel
connect issue_slots[5].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel
connect issue_slots[5].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed
connect issue_slots[5].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm
connect issue_slots[5].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel
connect issue_slots[5].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename
connect issue_slots[5].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken
connect issue_slots[5].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob
connect issue_slots[5].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst
connect issue_slots[5].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx
connect issue_slots[5].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov
connect issue_slots[5].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc
connect issue_slots[5].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc
connect issue_slots[5].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret
connect issue_slots[5].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo
connect issue_slots[5].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence
connect issue_slots[5].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei
connect issue_slots[5].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence
connect issue_slots[5].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb
connect issue_slots[5].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type
connect issue_slots[5].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag
connect issue_slots[5].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask
connect issue_slots[5].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel
connect issue_slots[5].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint
connect issue_slots[5].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint
connect issue_slots[5].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint
connect issue_slots[5].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child
connect issue_slots[5].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child
connect issue_slots[5].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen
connect issue_slots[5].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen
connect issue_slots[5].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued
connect issue_slots[5].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0]
connect issue_slots[5].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1]
connect issue_slots[5].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2]
connect issue_slots[5].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3]
connect issue_slots[5].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4]
connect issue_slots[5].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5]
connect issue_slots[5].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6]
connect issue_slots[5].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7]
connect issue_slots[5].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8]
connect issue_slots[5].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9]
connect issue_slots[5].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0]
connect issue_slots[5].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1]
connect issue_slots[5].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2]
connect issue_slots[5].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3]
connect issue_slots[5].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc
connect issue_slots[5].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc
connect issue_slots[5].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst
connect issue_slots[5].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst
connect issue_slots[5].wakeup_ports[3].valid, io.wakeup_ports[3].valid
connect issue_slots[5].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[5].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[5].child_rebusys, io.child_rebusys
connect issue_slots[5].squash_grant, io.squash_grant
connect issue_slots[5].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[5].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[5].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[5].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[5].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[5].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[5].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[5].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[5].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[5].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[5].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[5].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[5].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[5].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ
connect issue_slots[5].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm
connect issue_slots[5].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[5].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op
connect issue_slots[5].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw
connect issue_slots[5].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[5].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[5].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[5].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[5].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[5].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[5].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[5].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[5].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[5].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd
connect issue_slots[5].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[5].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[5].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[5].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[5].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[5].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[5].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[5].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[5].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[5].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[5].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[5].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[5].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[5].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[5].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[5].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[5].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[5].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[5].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[5].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[5].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[5].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[5].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[5].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec
connect issue_slots[5].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags
connect issue_slots[5].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt
connect issue_slots[5].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div
connect issue_slots[5].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma
connect issue_slots[5].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe
connect issue_slots[5].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint
connect issue_slots[5].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint
connect issue_slots[5].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut
connect issue_slots[5].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn
connect issue_slots[5].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23
connect issue_slots[5].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12
connect issue_slots[5].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3
connect issue_slots[5].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2
connect issue_slots[5].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1
connect issue_slots[5].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen
connect issue_slots[5].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst
connect issue_slots[5].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel
connect issue_slots[5].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel
connect issue_slots[5].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[5].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm
connect issue_slots[5].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel
connect issue_slots[5].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename
connect issue_slots[5].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[5].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[5].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[5].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[5].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov
connect issue_slots[5].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc
connect issue_slots[5].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[5].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret
connect issue_slots[5].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[5].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence
connect issue_slots[5].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[5].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[5].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[5].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type
connect issue_slots[5].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[5].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[5].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel
connect issue_slots[5].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint
connect issue_slots[5].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint
connect issue_slots[5].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint
connect issue_slots[5].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child
connect issue_slots[5].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child
connect issue_slots[5].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen
connect issue_slots[5].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen
connect issue_slots[5].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued
connect issue_slots[5].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0]
connect issue_slots[5].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1]
connect issue_slots[5].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2]
connect issue_slots[5].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3]
connect issue_slots[5].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4]
connect issue_slots[5].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5]
connect issue_slots[5].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6]
connect issue_slots[5].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7]
connect issue_slots[5].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8]
connect issue_slots[5].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9]
connect issue_slots[5].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0]
connect issue_slots[5].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1]
connect issue_slots[5].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2]
connect issue_slots[5].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3]
connect issue_slots[5].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[5].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[5].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[5].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[5].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[5].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[5].kill, io.flush_pipeline
connect issue_slots[6].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy
connect issue_slots[6].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask
connect issue_slots[6].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable
connect issue_slots[6].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc
connect issue_slots[6].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc
connect issue_slots[6].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if
connect issue_slots[6].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if
connect issue_slots[6].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if
connect issue_slots[6].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if
connect issue_slots[6].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if
connect issue_slots[6].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ
connect issue_slots[6].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm
connect issue_slots[6].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val
connect issue_slots[6].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op
connect issue_slots[6].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw
connect issue_slots[6].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en
connect issue_slots[6].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype
connect issue_slots[6].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype
connect issue_slots[6].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype
connect issue_slots[6].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3
connect issue_slots[6].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2
connect issue_slots[6].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1
connect issue_slots[6].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst
connect issue_slots[6].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1
connect issue_slots[6].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd
connect issue_slots[6].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit
connect issue_slots[6].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique
connect issue_slots[6].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq
connect issue_slots[6].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq
connect issue_slots[6].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed
connect issue_slots[6].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size
connect issue_slots[6].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd
connect issue_slots[6].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause
connect issue_slots[6].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception
connect issue_slots[6].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst
connect issue_slots[6].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy
connect issue_slots[6].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy
connect issue_slots[6].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy
connect issue_slots[6].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy
connect issue_slots[6].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred
connect issue_slots[6].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3
connect issue_slots[6].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2
connect issue_slots[6].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1
connect issue_slots[6].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst
connect issue_slots[6].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx
connect issue_slots[6].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx
connect issue_slots[6].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx
connect issue_slots[6].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx
connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec
connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags
connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt
connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div
connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma
connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe
connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint
connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint
connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23
connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12
connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3
connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2
connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1
connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen
connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst
connect issue_slots[6].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel
connect issue_slots[6].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel
connect issue_slots[6].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed
connect issue_slots[6].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm
connect issue_slots[6].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel
connect issue_slots[6].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename
connect issue_slots[6].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken
connect issue_slots[6].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob
connect issue_slots[6].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst
connect issue_slots[6].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx
connect issue_slots[6].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov
connect issue_slots[6].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc
connect issue_slots[6].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc
connect issue_slots[6].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret
connect issue_slots[6].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo
connect issue_slots[6].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence
connect issue_slots[6].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei
connect issue_slots[6].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence
connect issue_slots[6].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb
connect issue_slots[6].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type
connect issue_slots[6].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag
connect issue_slots[6].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask
connect issue_slots[6].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel
connect issue_slots[6].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint
connect issue_slots[6].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint
connect issue_slots[6].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint
connect issue_slots[6].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child
connect issue_slots[6].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child
connect issue_slots[6].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen
connect issue_slots[6].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen
connect issue_slots[6].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued
connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0]
connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1]
connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2]
connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3]
connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4]
connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5]
connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6]
connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7]
connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8]
connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9]
connect issue_slots[6].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0]
connect issue_slots[6].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1]
connect issue_slots[6].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2]
connect issue_slots[6].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3]
connect issue_slots[6].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc
connect issue_slots[6].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc
connect issue_slots[6].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst
connect issue_slots[6].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst
connect issue_slots[6].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[6].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy
connect issue_slots[6].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask
connect issue_slots[6].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable
connect issue_slots[6].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc
connect issue_slots[6].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc
connect issue_slots[6].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if
connect issue_slots[6].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if
connect issue_slots[6].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if
connect issue_slots[6].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if
connect issue_slots[6].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if
connect issue_slots[6].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ
connect issue_slots[6].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm
connect issue_slots[6].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val
connect issue_slots[6].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op
connect issue_slots[6].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw
connect issue_slots[6].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en
connect issue_slots[6].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype
connect issue_slots[6].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype
connect issue_slots[6].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype
connect issue_slots[6].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3
connect issue_slots[6].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2
connect issue_slots[6].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1
connect issue_slots[6].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst
connect issue_slots[6].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1
connect issue_slots[6].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd
connect issue_slots[6].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit
connect issue_slots[6].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique
connect issue_slots[6].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq
connect issue_slots[6].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq
connect issue_slots[6].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed
connect issue_slots[6].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size
connect issue_slots[6].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd
connect issue_slots[6].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause
connect issue_slots[6].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception
connect issue_slots[6].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst
connect issue_slots[6].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy
connect issue_slots[6].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy
connect issue_slots[6].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy
connect issue_slots[6].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy
connect issue_slots[6].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred
connect issue_slots[6].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3
connect issue_slots[6].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2
connect issue_slots[6].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1
connect issue_slots[6].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst
connect issue_slots[6].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx
connect issue_slots[6].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx
connect issue_slots[6].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx
connect issue_slots[6].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx
connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec
connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags
connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt
connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div
connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma
connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe
connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint
connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint
connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23
connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12
connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3
connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2
connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1
connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen
connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst
connect issue_slots[6].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel
connect issue_slots[6].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel
connect issue_slots[6].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed
connect issue_slots[6].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm
connect issue_slots[6].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel
connect issue_slots[6].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename
connect issue_slots[6].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken
connect issue_slots[6].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob
connect issue_slots[6].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst
connect issue_slots[6].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx
connect issue_slots[6].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov
connect issue_slots[6].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc
connect issue_slots[6].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc
connect issue_slots[6].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret
connect issue_slots[6].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo
connect issue_slots[6].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence
connect issue_slots[6].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei
connect issue_slots[6].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence
connect issue_slots[6].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb
connect issue_slots[6].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type
connect issue_slots[6].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag
connect issue_slots[6].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask
connect issue_slots[6].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel
connect issue_slots[6].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint
connect issue_slots[6].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint
connect issue_slots[6].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint
connect issue_slots[6].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child
connect issue_slots[6].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child
connect issue_slots[6].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen
connect issue_slots[6].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen
connect issue_slots[6].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued
connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0]
connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1]
connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2]
connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3]
connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4]
connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5]
connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6]
connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7]
connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8]
connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9]
connect issue_slots[6].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0]
connect issue_slots[6].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1]
connect issue_slots[6].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2]
connect issue_slots[6].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3]
connect issue_slots[6].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc
connect issue_slots[6].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc
connect issue_slots[6].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst
connect issue_slots[6].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst
connect issue_slots[6].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[6].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy
connect issue_slots[6].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask
connect issue_slots[6].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable
connect issue_slots[6].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc
connect issue_slots[6].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc
connect issue_slots[6].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if
connect issue_slots[6].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if
connect issue_slots[6].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if
connect issue_slots[6].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if
connect issue_slots[6].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if
connect issue_slots[6].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ
connect issue_slots[6].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm
connect issue_slots[6].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val
connect issue_slots[6].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op
connect issue_slots[6].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw
connect issue_slots[6].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en
connect issue_slots[6].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype
connect issue_slots[6].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype
connect issue_slots[6].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype
connect issue_slots[6].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3
connect issue_slots[6].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2
connect issue_slots[6].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1
connect issue_slots[6].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst
connect issue_slots[6].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1
connect issue_slots[6].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd
connect issue_slots[6].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit
connect issue_slots[6].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique
connect issue_slots[6].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq
connect issue_slots[6].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq
connect issue_slots[6].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed
connect issue_slots[6].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size
connect issue_slots[6].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd
connect issue_slots[6].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause
connect issue_slots[6].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception
connect issue_slots[6].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst
connect issue_slots[6].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy
connect issue_slots[6].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy
connect issue_slots[6].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy
connect issue_slots[6].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy
connect issue_slots[6].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred
connect issue_slots[6].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3
connect issue_slots[6].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2
connect issue_slots[6].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1
connect issue_slots[6].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst
connect issue_slots[6].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx
connect issue_slots[6].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx
connect issue_slots[6].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx
connect issue_slots[6].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx
connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec
connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags
connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt
connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div
connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma
connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe
connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint
connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint
connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23
connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12
connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3
connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2
connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1
connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen
connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst
connect issue_slots[6].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel
connect issue_slots[6].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel
connect issue_slots[6].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed
connect issue_slots[6].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm
connect issue_slots[6].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel
connect issue_slots[6].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename
connect issue_slots[6].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken
connect issue_slots[6].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob
connect issue_slots[6].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst
connect issue_slots[6].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx
connect issue_slots[6].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov
connect issue_slots[6].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc
connect issue_slots[6].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc
connect issue_slots[6].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret
connect issue_slots[6].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo
connect issue_slots[6].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence
connect issue_slots[6].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei
connect issue_slots[6].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence
connect issue_slots[6].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb
connect issue_slots[6].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type
connect issue_slots[6].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag
connect issue_slots[6].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask
connect issue_slots[6].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel
connect issue_slots[6].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint
connect issue_slots[6].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint
connect issue_slots[6].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint
connect issue_slots[6].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child
connect issue_slots[6].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child
connect issue_slots[6].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen
connect issue_slots[6].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen
connect issue_slots[6].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued
connect issue_slots[6].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0]
connect issue_slots[6].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1]
connect issue_slots[6].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2]
connect issue_slots[6].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3]
connect issue_slots[6].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4]
connect issue_slots[6].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5]
connect issue_slots[6].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6]
connect issue_slots[6].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7]
connect issue_slots[6].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8]
connect issue_slots[6].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9]
connect issue_slots[6].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0]
connect issue_slots[6].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1]
connect issue_slots[6].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2]
connect issue_slots[6].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3]
connect issue_slots[6].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc
connect issue_slots[6].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc
connect issue_slots[6].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst
connect issue_slots[6].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst
connect issue_slots[6].wakeup_ports[2].valid, io.wakeup_ports[2].valid
connect issue_slots[6].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy
connect issue_slots[6].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask
connect issue_slots[6].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable
connect issue_slots[6].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc
connect issue_slots[6].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc
connect issue_slots[6].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if
connect issue_slots[6].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if
connect issue_slots[6].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if
connect issue_slots[6].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if
connect issue_slots[6].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if
connect issue_slots[6].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ
connect issue_slots[6].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm
connect issue_slots[6].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val
connect issue_slots[6].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op
connect issue_slots[6].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw
connect issue_slots[6].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en
connect issue_slots[6].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype
connect issue_slots[6].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype
connect issue_slots[6].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype
connect issue_slots[6].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3
connect issue_slots[6].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2
connect issue_slots[6].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1
connect issue_slots[6].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst
connect issue_slots[6].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1
connect issue_slots[6].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd
connect issue_slots[6].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit
connect issue_slots[6].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique
connect issue_slots[6].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq
connect issue_slots[6].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq
connect issue_slots[6].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed
connect issue_slots[6].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size
connect issue_slots[6].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd
connect issue_slots[6].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause
connect issue_slots[6].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception
connect issue_slots[6].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst
connect issue_slots[6].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy
connect issue_slots[6].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy
connect issue_slots[6].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy
connect issue_slots[6].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy
connect issue_slots[6].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred
connect issue_slots[6].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3
connect issue_slots[6].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2
connect issue_slots[6].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1
connect issue_slots[6].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst
connect issue_slots[6].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx
connect issue_slots[6].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx
connect issue_slots[6].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx
connect issue_slots[6].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx
connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec
connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags
connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt
connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div
connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma
connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe
connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint
connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint
connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23
connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12
connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3
connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2
connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1
connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen
connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst
connect issue_slots[6].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel
connect issue_slots[6].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel
connect issue_slots[6].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed
connect issue_slots[6].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm
connect issue_slots[6].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel
connect issue_slots[6].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename
connect issue_slots[6].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken
connect issue_slots[6].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob
connect issue_slots[6].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst
connect issue_slots[6].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx
connect issue_slots[6].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov
connect issue_slots[6].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc
connect issue_slots[6].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc
connect issue_slots[6].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret
connect issue_slots[6].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo
connect issue_slots[6].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence
connect issue_slots[6].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei
connect issue_slots[6].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence
connect issue_slots[6].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb
connect issue_slots[6].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type
connect issue_slots[6].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag
connect issue_slots[6].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask
connect issue_slots[6].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel
connect issue_slots[6].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint
connect issue_slots[6].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint
connect issue_slots[6].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint
connect issue_slots[6].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child
connect issue_slots[6].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child
connect issue_slots[6].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen
connect issue_slots[6].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen
connect issue_slots[6].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued
connect issue_slots[6].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0]
connect issue_slots[6].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1]
connect issue_slots[6].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2]
connect issue_slots[6].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3]
connect issue_slots[6].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4]
connect issue_slots[6].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5]
connect issue_slots[6].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6]
connect issue_slots[6].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7]
connect issue_slots[6].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8]
connect issue_slots[6].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9]
connect issue_slots[6].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0]
connect issue_slots[6].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1]
connect issue_slots[6].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2]
connect issue_slots[6].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3]
connect issue_slots[6].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc
connect issue_slots[6].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc
connect issue_slots[6].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst
connect issue_slots[6].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst
connect issue_slots[6].wakeup_ports[3].valid, io.wakeup_ports[3].valid
connect issue_slots[6].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[6].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[6].child_rebusys, io.child_rebusys
connect issue_slots[6].squash_grant, io.squash_grant
connect issue_slots[6].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[6].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[6].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[6].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[6].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[6].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[6].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[6].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[6].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[6].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[6].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[6].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[6].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[6].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ
connect issue_slots[6].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm
connect issue_slots[6].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[6].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op
connect issue_slots[6].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw
connect issue_slots[6].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[6].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[6].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[6].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[6].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[6].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[6].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[6].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[6].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[6].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd
connect issue_slots[6].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[6].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[6].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[6].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[6].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[6].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[6].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[6].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[6].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[6].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[6].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[6].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[6].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[6].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[6].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[6].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[6].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[6].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[6].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[6].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[6].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[6].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[6].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[6].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec
connect issue_slots[6].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags
connect issue_slots[6].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt
connect issue_slots[6].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div
connect issue_slots[6].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma
connect issue_slots[6].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe
connect issue_slots[6].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint
connect issue_slots[6].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint
connect issue_slots[6].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut
connect issue_slots[6].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn
connect issue_slots[6].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23
connect issue_slots[6].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12
connect issue_slots[6].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3
connect issue_slots[6].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2
connect issue_slots[6].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1
connect issue_slots[6].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen
connect issue_slots[6].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst
connect issue_slots[6].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel
connect issue_slots[6].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel
connect issue_slots[6].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[6].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm
connect issue_slots[6].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel
connect issue_slots[6].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename
connect issue_slots[6].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[6].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[6].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[6].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[6].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov
connect issue_slots[6].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc
connect issue_slots[6].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[6].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret
connect issue_slots[6].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[6].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence
connect issue_slots[6].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[6].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[6].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[6].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type
connect issue_slots[6].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[6].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[6].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel
connect issue_slots[6].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint
connect issue_slots[6].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint
connect issue_slots[6].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint
connect issue_slots[6].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child
connect issue_slots[6].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child
connect issue_slots[6].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen
connect issue_slots[6].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen
connect issue_slots[6].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued
connect issue_slots[6].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0]
connect issue_slots[6].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1]
connect issue_slots[6].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2]
connect issue_slots[6].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3]
connect issue_slots[6].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4]
connect issue_slots[6].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5]
connect issue_slots[6].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6]
connect issue_slots[6].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7]
connect issue_slots[6].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8]
connect issue_slots[6].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9]
connect issue_slots[6].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0]
connect issue_slots[6].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1]
connect issue_slots[6].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2]
connect issue_slots[6].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3]
connect issue_slots[6].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[6].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[6].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[6].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[6].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[6].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[6].kill, io.flush_pipeline
connect issue_slots[7].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy
connect issue_slots[7].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask
connect issue_slots[7].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable
connect issue_slots[7].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc
connect issue_slots[7].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc
connect issue_slots[7].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if
connect issue_slots[7].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if
connect issue_slots[7].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if
connect issue_slots[7].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if
connect issue_slots[7].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if
connect issue_slots[7].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ
connect issue_slots[7].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm
connect issue_slots[7].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val
connect issue_slots[7].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op
connect issue_slots[7].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw
connect issue_slots[7].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en
connect issue_slots[7].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype
connect issue_slots[7].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype
connect issue_slots[7].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype
connect issue_slots[7].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3
connect issue_slots[7].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2
connect issue_slots[7].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1
connect issue_slots[7].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst
connect issue_slots[7].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1
connect issue_slots[7].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd
connect issue_slots[7].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit
connect issue_slots[7].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique
connect issue_slots[7].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq
connect issue_slots[7].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq
connect issue_slots[7].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed
connect issue_slots[7].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size
connect issue_slots[7].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd
connect issue_slots[7].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause
connect issue_slots[7].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception
connect issue_slots[7].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst
connect issue_slots[7].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy
connect issue_slots[7].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy
connect issue_slots[7].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy
connect issue_slots[7].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy
connect issue_slots[7].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred
connect issue_slots[7].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3
connect issue_slots[7].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2
connect issue_slots[7].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1
connect issue_slots[7].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst
connect issue_slots[7].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx
connect issue_slots[7].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx
connect issue_slots[7].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx
connect issue_slots[7].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx
connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec
connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags
connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt
connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div
connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma
connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe
connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint
connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint
connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23
connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12
connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3
connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2
connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1
connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen
connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst
connect issue_slots[7].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel
connect issue_slots[7].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel
connect issue_slots[7].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed
connect issue_slots[7].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm
connect issue_slots[7].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel
connect issue_slots[7].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename
connect issue_slots[7].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken
connect issue_slots[7].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob
connect issue_slots[7].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst
connect issue_slots[7].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx
connect issue_slots[7].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov
connect issue_slots[7].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc
connect issue_slots[7].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc
connect issue_slots[7].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret
connect issue_slots[7].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo
connect issue_slots[7].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence
connect issue_slots[7].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei
connect issue_slots[7].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence
connect issue_slots[7].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb
connect issue_slots[7].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type
connect issue_slots[7].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag
connect issue_slots[7].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask
connect issue_slots[7].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel
connect issue_slots[7].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint
connect issue_slots[7].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint
connect issue_slots[7].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint
connect issue_slots[7].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child
connect issue_slots[7].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child
connect issue_slots[7].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen
connect issue_slots[7].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen
connect issue_slots[7].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued
connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0]
connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1]
connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2]
connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3]
connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4]
connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5]
connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6]
connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7]
connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8]
connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9]
connect issue_slots[7].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0]
connect issue_slots[7].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1]
connect issue_slots[7].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2]
connect issue_slots[7].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3]
connect issue_slots[7].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc
connect issue_slots[7].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc
connect issue_slots[7].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst
connect issue_slots[7].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst
connect issue_slots[7].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[7].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy
connect issue_slots[7].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask
connect issue_slots[7].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable
connect issue_slots[7].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc
connect issue_slots[7].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc
connect issue_slots[7].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if
connect issue_slots[7].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if
connect issue_slots[7].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if
connect issue_slots[7].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if
connect issue_slots[7].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if
connect issue_slots[7].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ
connect issue_slots[7].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm
connect issue_slots[7].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val
connect issue_slots[7].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op
connect issue_slots[7].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw
connect issue_slots[7].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en
connect issue_slots[7].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype
connect issue_slots[7].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype
connect issue_slots[7].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype
connect issue_slots[7].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3
connect issue_slots[7].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2
connect issue_slots[7].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1
connect issue_slots[7].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst
connect issue_slots[7].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1
connect issue_slots[7].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd
connect issue_slots[7].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit
connect issue_slots[7].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique
connect issue_slots[7].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq
connect issue_slots[7].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq
connect issue_slots[7].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed
connect issue_slots[7].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size
connect issue_slots[7].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd
connect issue_slots[7].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause
connect issue_slots[7].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception
connect issue_slots[7].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst
connect issue_slots[7].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy
connect issue_slots[7].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy
connect issue_slots[7].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy
connect issue_slots[7].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy
connect issue_slots[7].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred
connect issue_slots[7].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3
connect issue_slots[7].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2
connect issue_slots[7].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1
connect issue_slots[7].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst
connect issue_slots[7].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx
connect issue_slots[7].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx
connect issue_slots[7].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx
connect issue_slots[7].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx
connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec
connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags
connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt
connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div
connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma
connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe
connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint
connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint
connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23
connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12
connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3
connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2
connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1
connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen
connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst
connect issue_slots[7].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel
connect issue_slots[7].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel
connect issue_slots[7].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed
connect issue_slots[7].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm
connect issue_slots[7].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel
connect issue_slots[7].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename
connect issue_slots[7].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken
connect issue_slots[7].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob
connect issue_slots[7].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst
connect issue_slots[7].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx
connect issue_slots[7].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov
connect issue_slots[7].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc
connect issue_slots[7].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc
connect issue_slots[7].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret
connect issue_slots[7].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo
connect issue_slots[7].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence
connect issue_slots[7].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei
connect issue_slots[7].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence
connect issue_slots[7].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb
connect issue_slots[7].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type
connect issue_slots[7].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag
connect issue_slots[7].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask
connect issue_slots[7].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel
connect issue_slots[7].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint
connect issue_slots[7].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint
connect issue_slots[7].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint
connect issue_slots[7].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child
connect issue_slots[7].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child
connect issue_slots[7].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen
connect issue_slots[7].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen
connect issue_slots[7].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued
connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0]
connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1]
connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2]
connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3]
connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4]
connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5]
connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6]
connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7]
connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8]
connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9]
connect issue_slots[7].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0]
connect issue_slots[7].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1]
connect issue_slots[7].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2]
connect issue_slots[7].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3]
connect issue_slots[7].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc
connect issue_slots[7].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc
connect issue_slots[7].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst
connect issue_slots[7].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst
connect issue_slots[7].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[7].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy
connect issue_slots[7].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask
connect issue_slots[7].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable
connect issue_slots[7].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc
connect issue_slots[7].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc
connect issue_slots[7].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if
connect issue_slots[7].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if
connect issue_slots[7].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if
connect issue_slots[7].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if
connect issue_slots[7].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if
connect issue_slots[7].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ
connect issue_slots[7].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm
connect issue_slots[7].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val
connect issue_slots[7].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op
connect issue_slots[7].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw
connect issue_slots[7].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en
connect issue_slots[7].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype
connect issue_slots[7].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype
connect issue_slots[7].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype
connect issue_slots[7].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3
connect issue_slots[7].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2
connect issue_slots[7].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1
connect issue_slots[7].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst
connect issue_slots[7].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1
connect issue_slots[7].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd
connect issue_slots[7].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit
connect issue_slots[7].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique
connect issue_slots[7].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq
connect issue_slots[7].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq
connect issue_slots[7].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed
connect issue_slots[7].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size
connect issue_slots[7].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd
connect issue_slots[7].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause
connect issue_slots[7].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception
connect issue_slots[7].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst
connect issue_slots[7].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy
connect issue_slots[7].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy
connect issue_slots[7].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy
connect issue_slots[7].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy
connect issue_slots[7].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred
connect issue_slots[7].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3
connect issue_slots[7].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2
connect issue_slots[7].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1
connect issue_slots[7].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst
connect issue_slots[7].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx
connect issue_slots[7].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx
connect issue_slots[7].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx
connect issue_slots[7].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx
connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec
connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags
connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt
connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div
connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma
connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe
connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint
connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint
connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23
connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12
connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3
connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2
connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1
connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen
connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst
connect issue_slots[7].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel
connect issue_slots[7].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel
connect issue_slots[7].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed
connect issue_slots[7].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm
connect issue_slots[7].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel
connect issue_slots[7].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename
connect issue_slots[7].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken
connect issue_slots[7].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob
connect issue_slots[7].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst
connect issue_slots[7].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx
connect issue_slots[7].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov
connect issue_slots[7].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc
connect issue_slots[7].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc
connect issue_slots[7].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret
connect issue_slots[7].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo
connect issue_slots[7].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence
connect issue_slots[7].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei
connect issue_slots[7].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence
connect issue_slots[7].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb
connect issue_slots[7].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type
connect issue_slots[7].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag
connect issue_slots[7].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask
connect issue_slots[7].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel
connect issue_slots[7].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint
connect issue_slots[7].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint
connect issue_slots[7].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint
connect issue_slots[7].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child
connect issue_slots[7].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child
connect issue_slots[7].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen
connect issue_slots[7].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen
connect issue_slots[7].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued
connect issue_slots[7].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0]
connect issue_slots[7].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1]
connect issue_slots[7].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2]
connect issue_slots[7].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3]
connect issue_slots[7].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4]
connect issue_slots[7].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5]
connect issue_slots[7].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6]
connect issue_slots[7].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7]
connect issue_slots[7].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8]
connect issue_slots[7].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9]
connect issue_slots[7].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0]
connect issue_slots[7].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1]
connect issue_slots[7].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2]
connect issue_slots[7].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3]
connect issue_slots[7].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc
connect issue_slots[7].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc
connect issue_slots[7].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst
connect issue_slots[7].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst
connect issue_slots[7].wakeup_ports[2].valid, io.wakeup_ports[2].valid
connect issue_slots[7].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy
connect issue_slots[7].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask
connect issue_slots[7].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable
connect issue_slots[7].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc
connect issue_slots[7].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc
connect issue_slots[7].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if
connect issue_slots[7].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if
connect issue_slots[7].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if
connect issue_slots[7].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if
connect issue_slots[7].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if
connect issue_slots[7].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ
connect issue_slots[7].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm
connect issue_slots[7].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val
connect issue_slots[7].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op
connect issue_slots[7].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw
connect issue_slots[7].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en
connect issue_slots[7].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype
connect issue_slots[7].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype
connect issue_slots[7].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype
connect issue_slots[7].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3
connect issue_slots[7].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2
connect issue_slots[7].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1
connect issue_slots[7].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst
connect issue_slots[7].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1
connect issue_slots[7].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd
connect issue_slots[7].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit
connect issue_slots[7].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique
connect issue_slots[7].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq
connect issue_slots[7].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq
connect issue_slots[7].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed
connect issue_slots[7].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size
connect issue_slots[7].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd
connect issue_slots[7].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause
connect issue_slots[7].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception
connect issue_slots[7].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst
connect issue_slots[7].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy
connect issue_slots[7].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy
connect issue_slots[7].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy
connect issue_slots[7].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy
connect issue_slots[7].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred
connect issue_slots[7].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3
connect issue_slots[7].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2
connect issue_slots[7].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1
connect issue_slots[7].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst
connect issue_slots[7].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx
connect issue_slots[7].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx
connect issue_slots[7].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx
connect issue_slots[7].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx
connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec
connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags
connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt
connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div
connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma
connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe
connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint
connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint
connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23
connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12
connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3
connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2
connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1
connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen
connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst
connect issue_slots[7].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel
connect issue_slots[7].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel
connect issue_slots[7].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed
connect issue_slots[7].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm
connect issue_slots[7].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel
connect issue_slots[7].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename
connect issue_slots[7].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken
connect issue_slots[7].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob
connect issue_slots[7].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst
connect issue_slots[7].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx
connect issue_slots[7].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov
connect issue_slots[7].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc
connect issue_slots[7].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc
connect issue_slots[7].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret
connect issue_slots[7].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo
connect issue_slots[7].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence
connect issue_slots[7].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei
connect issue_slots[7].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence
connect issue_slots[7].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb
connect issue_slots[7].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type
connect issue_slots[7].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag
connect issue_slots[7].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask
connect issue_slots[7].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel
connect issue_slots[7].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint
connect issue_slots[7].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint
connect issue_slots[7].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint
connect issue_slots[7].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child
connect issue_slots[7].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child
connect issue_slots[7].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen
connect issue_slots[7].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen
connect issue_slots[7].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued
connect issue_slots[7].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0]
connect issue_slots[7].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1]
connect issue_slots[7].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2]
connect issue_slots[7].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3]
connect issue_slots[7].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4]
connect issue_slots[7].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5]
connect issue_slots[7].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6]
connect issue_slots[7].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7]
connect issue_slots[7].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8]
connect issue_slots[7].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9]
connect issue_slots[7].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0]
connect issue_slots[7].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1]
connect issue_slots[7].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2]
connect issue_slots[7].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3]
connect issue_slots[7].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc
connect issue_slots[7].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc
connect issue_slots[7].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst
connect issue_slots[7].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst
connect issue_slots[7].wakeup_ports[3].valid, io.wakeup_ports[3].valid
connect issue_slots[7].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[7].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[7].child_rebusys, io.child_rebusys
connect issue_slots[7].squash_grant, io.squash_grant
connect issue_slots[7].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[7].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[7].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[7].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[7].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[7].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[7].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[7].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[7].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[7].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[7].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[7].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[7].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[7].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ
connect issue_slots[7].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm
connect issue_slots[7].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[7].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op
connect issue_slots[7].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw
connect issue_slots[7].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[7].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[7].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[7].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[7].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[7].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[7].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[7].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[7].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[7].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd
connect issue_slots[7].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[7].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[7].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[7].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[7].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[7].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[7].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[7].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[7].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[7].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[7].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[7].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[7].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[7].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[7].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[7].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[7].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[7].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[7].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[7].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[7].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[7].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[7].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[7].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec
connect issue_slots[7].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags
connect issue_slots[7].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt
connect issue_slots[7].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div
connect issue_slots[7].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma
connect issue_slots[7].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe
connect issue_slots[7].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint
connect issue_slots[7].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint
connect issue_slots[7].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut
connect issue_slots[7].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn
connect issue_slots[7].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23
connect issue_slots[7].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12
connect issue_slots[7].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3
connect issue_slots[7].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2
connect issue_slots[7].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1
connect issue_slots[7].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen
connect issue_slots[7].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst
connect issue_slots[7].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel
connect issue_slots[7].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel
connect issue_slots[7].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[7].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm
connect issue_slots[7].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel
connect issue_slots[7].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename
connect issue_slots[7].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[7].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[7].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[7].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[7].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov
connect issue_slots[7].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc
connect issue_slots[7].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[7].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret
connect issue_slots[7].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[7].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence
connect issue_slots[7].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[7].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[7].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[7].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type
connect issue_slots[7].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[7].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[7].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel
connect issue_slots[7].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint
connect issue_slots[7].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint
connect issue_slots[7].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint
connect issue_slots[7].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child
connect issue_slots[7].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child
connect issue_slots[7].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen
connect issue_slots[7].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen
connect issue_slots[7].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued
connect issue_slots[7].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0]
connect issue_slots[7].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1]
connect issue_slots[7].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2]
connect issue_slots[7].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3]
connect issue_slots[7].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4]
connect issue_slots[7].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5]
connect issue_slots[7].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6]
connect issue_slots[7].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7]
connect issue_slots[7].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8]
connect issue_slots[7].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9]
connect issue_slots[7].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0]
connect issue_slots[7].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1]
connect issue_slots[7].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2]
connect issue_slots[7].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3]
connect issue_slots[7].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[7].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[7].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[7].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[7].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[7].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[7].kill, io.flush_pipeline
connect issue_slots[8].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy
connect issue_slots[8].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask
connect issue_slots[8].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable
connect issue_slots[8].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc
connect issue_slots[8].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc
connect issue_slots[8].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if
connect issue_slots[8].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if
connect issue_slots[8].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if
connect issue_slots[8].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if
connect issue_slots[8].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if
connect issue_slots[8].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ
connect issue_slots[8].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm
connect issue_slots[8].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val
connect issue_slots[8].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op
connect issue_slots[8].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw
connect issue_slots[8].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en
connect issue_slots[8].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype
connect issue_slots[8].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype
connect issue_slots[8].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype
connect issue_slots[8].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3
connect issue_slots[8].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2
connect issue_slots[8].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1
connect issue_slots[8].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst
connect issue_slots[8].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1
connect issue_slots[8].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd
connect issue_slots[8].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit
connect issue_slots[8].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique
connect issue_slots[8].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq
connect issue_slots[8].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq
connect issue_slots[8].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed
connect issue_slots[8].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size
connect issue_slots[8].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd
connect issue_slots[8].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause
connect issue_slots[8].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception
connect issue_slots[8].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst
connect issue_slots[8].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy
connect issue_slots[8].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy
connect issue_slots[8].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy
connect issue_slots[8].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy
connect issue_slots[8].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred
connect issue_slots[8].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3
connect issue_slots[8].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2
connect issue_slots[8].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1
connect issue_slots[8].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst
connect issue_slots[8].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx
connect issue_slots[8].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx
connect issue_slots[8].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx
connect issue_slots[8].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx
connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec
connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags
connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt
connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div
connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma
connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe
connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint
connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint
connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23
connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12
connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3
connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2
connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1
connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen
connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst
connect issue_slots[8].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel
connect issue_slots[8].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel
connect issue_slots[8].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed
connect issue_slots[8].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm
connect issue_slots[8].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel
connect issue_slots[8].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename
connect issue_slots[8].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken
connect issue_slots[8].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob
connect issue_slots[8].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst
connect issue_slots[8].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx
connect issue_slots[8].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov
connect issue_slots[8].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc
connect issue_slots[8].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc
connect issue_slots[8].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret
connect issue_slots[8].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo
connect issue_slots[8].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence
connect issue_slots[8].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei
connect issue_slots[8].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence
connect issue_slots[8].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb
connect issue_slots[8].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type
connect issue_slots[8].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag
connect issue_slots[8].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask
connect issue_slots[8].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel
connect issue_slots[8].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint
connect issue_slots[8].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint
connect issue_slots[8].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint
connect issue_slots[8].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child
connect issue_slots[8].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child
connect issue_slots[8].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen
connect issue_slots[8].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen
connect issue_slots[8].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued
connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0]
connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1]
connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2]
connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3]
connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4]
connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5]
connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6]
connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7]
connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8]
connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9]
connect issue_slots[8].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0]
connect issue_slots[8].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1]
connect issue_slots[8].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2]
connect issue_slots[8].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3]
connect issue_slots[8].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc
connect issue_slots[8].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc
connect issue_slots[8].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst
connect issue_slots[8].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst
connect issue_slots[8].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[8].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy
connect issue_slots[8].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask
connect issue_slots[8].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable
connect issue_slots[8].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc
connect issue_slots[8].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc
connect issue_slots[8].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if
connect issue_slots[8].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if
connect issue_slots[8].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if
connect issue_slots[8].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if
connect issue_slots[8].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if
connect issue_slots[8].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ
connect issue_slots[8].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm
connect issue_slots[8].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val
connect issue_slots[8].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op
connect issue_slots[8].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw
connect issue_slots[8].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en
connect issue_slots[8].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype
connect issue_slots[8].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype
connect issue_slots[8].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype
connect issue_slots[8].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3
connect issue_slots[8].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2
connect issue_slots[8].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1
connect issue_slots[8].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst
connect issue_slots[8].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1
connect issue_slots[8].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd
connect issue_slots[8].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit
connect issue_slots[8].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique
connect issue_slots[8].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq
connect issue_slots[8].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq
connect issue_slots[8].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed
connect issue_slots[8].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size
connect issue_slots[8].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd
connect issue_slots[8].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause
connect issue_slots[8].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception
connect issue_slots[8].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst
connect issue_slots[8].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy
connect issue_slots[8].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy
connect issue_slots[8].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy
connect issue_slots[8].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy
connect issue_slots[8].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred
connect issue_slots[8].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3
connect issue_slots[8].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2
connect issue_slots[8].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1
connect issue_slots[8].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst
connect issue_slots[8].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx
connect issue_slots[8].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx
connect issue_slots[8].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx
connect issue_slots[8].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx
connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec
connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags
connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt
connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div
connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma
connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe
connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint
connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint
connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23
connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12
connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3
connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2
connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1
connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen
connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst
connect issue_slots[8].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel
connect issue_slots[8].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel
connect issue_slots[8].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed
connect issue_slots[8].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm
connect issue_slots[8].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel
connect issue_slots[8].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename
connect issue_slots[8].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken
connect issue_slots[8].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob
connect issue_slots[8].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst
connect issue_slots[8].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx
connect issue_slots[8].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov
connect issue_slots[8].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc
connect issue_slots[8].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc
connect issue_slots[8].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret
connect issue_slots[8].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo
connect issue_slots[8].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence
connect issue_slots[8].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei
connect issue_slots[8].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence
connect issue_slots[8].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb
connect issue_slots[8].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type
connect issue_slots[8].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag
connect issue_slots[8].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask
connect issue_slots[8].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel
connect issue_slots[8].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint
connect issue_slots[8].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint
connect issue_slots[8].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint
connect issue_slots[8].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child
connect issue_slots[8].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child
connect issue_slots[8].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen
connect issue_slots[8].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen
connect issue_slots[8].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued
connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0]
connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1]
connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2]
connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3]
connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4]
connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5]
connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6]
connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7]
connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8]
connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9]
connect issue_slots[8].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0]
connect issue_slots[8].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1]
connect issue_slots[8].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2]
connect issue_slots[8].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3]
connect issue_slots[8].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc
connect issue_slots[8].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc
connect issue_slots[8].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst
connect issue_slots[8].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst
connect issue_slots[8].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[8].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy
connect issue_slots[8].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask
connect issue_slots[8].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable
connect issue_slots[8].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc
connect issue_slots[8].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc
connect issue_slots[8].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if
connect issue_slots[8].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if
connect issue_slots[8].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if
connect issue_slots[8].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if
connect issue_slots[8].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if
connect issue_slots[8].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ
connect issue_slots[8].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm
connect issue_slots[8].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val
connect issue_slots[8].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op
connect issue_slots[8].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw
connect issue_slots[8].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en
connect issue_slots[8].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype
connect issue_slots[8].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype
connect issue_slots[8].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype
connect issue_slots[8].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3
connect issue_slots[8].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2
connect issue_slots[8].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1
connect issue_slots[8].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst
connect issue_slots[8].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1
connect issue_slots[8].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd
connect issue_slots[8].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit
connect issue_slots[8].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique
connect issue_slots[8].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq
connect issue_slots[8].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq
connect issue_slots[8].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed
connect issue_slots[8].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size
connect issue_slots[8].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd
connect issue_slots[8].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause
connect issue_slots[8].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception
connect issue_slots[8].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst
connect issue_slots[8].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy
connect issue_slots[8].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy
connect issue_slots[8].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy
connect issue_slots[8].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy
connect issue_slots[8].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred
connect issue_slots[8].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3
connect issue_slots[8].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2
connect issue_slots[8].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1
connect issue_slots[8].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst
connect issue_slots[8].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx
connect issue_slots[8].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx
connect issue_slots[8].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx
connect issue_slots[8].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx
connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec
connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags
connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt
connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div
connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma
connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe
connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint
connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint
connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23
connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12
connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3
connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2
connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1
connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen
connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst
connect issue_slots[8].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel
connect issue_slots[8].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel
connect issue_slots[8].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed
connect issue_slots[8].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm
connect issue_slots[8].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel
connect issue_slots[8].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename
connect issue_slots[8].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken
connect issue_slots[8].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob
connect issue_slots[8].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst
connect issue_slots[8].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx
connect issue_slots[8].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov
connect issue_slots[8].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc
connect issue_slots[8].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc
connect issue_slots[8].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret
connect issue_slots[8].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo
connect issue_slots[8].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence
connect issue_slots[8].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei
connect issue_slots[8].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence
connect issue_slots[8].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb
connect issue_slots[8].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type
connect issue_slots[8].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag
connect issue_slots[8].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask
connect issue_slots[8].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel
connect issue_slots[8].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint
connect issue_slots[8].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint
connect issue_slots[8].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint
connect issue_slots[8].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child
connect issue_slots[8].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child
connect issue_slots[8].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen
connect issue_slots[8].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen
connect issue_slots[8].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued
connect issue_slots[8].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0]
connect issue_slots[8].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1]
connect issue_slots[8].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2]
connect issue_slots[8].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3]
connect issue_slots[8].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4]
connect issue_slots[8].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5]
connect issue_slots[8].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6]
connect issue_slots[8].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7]
connect issue_slots[8].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8]
connect issue_slots[8].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9]
connect issue_slots[8].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0]
connect issue_slots[8].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1]
connect issue_slots[8].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2]
connect issue_slots[8].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3]
connect issue_slots[8].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc
connect issue_slots[8].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc
connect issue_slots[8].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst
connect issue_slots[8].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst
connect issue_slots[8].wakeup_ports[2].valid, io.wakeup_ports[2].valid
connect issue_slots[8].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy
connect issue_slots[8].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask
connect issue_slots[8].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable
connect issue_slots[8].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc
connect issue_slots[8].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc
connect issue_slots[8].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if
connect issue_slots[8].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if
connect issue_slots[8].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if
connect issue_slots[8].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if
connect issue_slots[8].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if
connect issue_slots[8].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ
connect issue_slots[8].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm
connect issue_slots[8].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val
connect issue_slots[8].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op
connect issue_slots[8].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw
connect issue_slots[8].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en
connect issue_slots[8].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype
connect issue_slots[8].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype
connect issue_slots[8].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype
connect issue_slots[8].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3
connect issue_slots[8].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2
connect issue_slots[8].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1
connect issue_slots[8].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst
connect issue_slots[8].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1
connect issue_slots[8].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd
connect issue_slots[8].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit
connect issue_slots[8].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique
connect issue_slots[8].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq
connect issue_slots[8].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq
connect issue_slots[8].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed
connect issue_slots[8].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size
connect issue_slots[8].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd
connect issue_slots[8].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause
connect issue_slots[8].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception
connect issue_slots[8].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst
connect issue_slots[8].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy
connect issue_slots[8].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy
connect issue_slots[8].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy
connect issue_slots[8].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy
connect issue_slots[8].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred
connect issue_slots[8].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3
connect issue_slots[8].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2
connect issue_slots[8].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1
connect issue_slots[8].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst
connect issue_slots[8].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx
connect issue_slots[8].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx
connect issue_slots[8].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx
connect issue_slots[8].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx
connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec
connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags
connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt
connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div
connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma
connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe
connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint
connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint
connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23
connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12
connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3
connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2
connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1
connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen
connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst
connect issue_slots[8].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel
connect issue_slots[8].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel
connect issue_slots[8].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed
connect issue_slots[8].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm
connect issue_slots[8].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel
connect issue_slots[8].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename
connect issue_slots[8].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken
connect issue_slots[8].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob
connect issue_slots[8].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst
connect issue_slots[8].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx
connect issue_slots[8].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov
connect issue_slots[8].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc
connect issue_slots[8].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc
connect issue_slots[8].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret
connect issue_slots[8].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo
connect issue_slots[8].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence
connect issue_slots[8].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei
connect issue_slots[8].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence
connect issue_slots[8].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb
connect issue_slots[8].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type
connect issue_slots[8].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag
connect issue_slots[8].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask
connect issue_slots[8].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel
connect issue_slots[8].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint
connect issue_slots[8].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint
connect issue_slots[8].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint
connect issue_slots[8].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child
connect issue_slots[8].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child
connect issue_slots[8].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen
connect issue_slots[8].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen
connect issue_slots[8].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued
connect issue_slots[8].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0]
connect issue_slots[8].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1]
connect issue_slots[8].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2]
connect issue_slots[8].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3]
connect issue_slots[8].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4]
connect issue_slots[8].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5]
connect issue_slots[8].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6]
connect issue_slots[8].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7]
connect issue_slots[8].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8]
connect issue_slots[8].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9]
connect issue_slots[8].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0]
connect issue_slots[8].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1]
connect issue_slots[8].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2]
connect issue_slots[8].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3]
connect issue_slots[8].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc
connect issue_slots[8].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc
connect issue_slots[8].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst
connect issue_slots[8].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst
connect issue_slots[8].wakeup_ports[3].valid, io.wakeup_ports[3].valid
connect issue_slots[8].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[8].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[8].child_rebusys, io.child_rebusys
connect issue_slots[8].squash_grant, io.squash_grant
connect issue_slots[8].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[8].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[8].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[8].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[8].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[8].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[8].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[8].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[8].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[8].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[8].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[8].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[8].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[8].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ
connect issue_slots[8].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm
connect issue_slots[8].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[8].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op
connect issue_slots[8].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw
connect issue_slots[8].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[8].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[8].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[8].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[8].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[8].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[8].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[8].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[8].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[8].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd
connect issue_slots[8].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[8].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[8].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[8].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[8].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[8].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[8].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[8].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[8].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[8].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[8].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[8].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[8].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[8].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[8].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[8].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[8].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[8].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[8].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[8].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[8].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[8].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[8].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[8].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec
connect issue_slots[8].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags
connect issue_slots[8].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt
connect issue_slots[8].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div
connect issue_slots[8].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma
connect issue_slots[8].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe
connect issue_slots[8].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint
connect issue_slots[8].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint
connect issue_slots[8].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut
connect issue_slots[8].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn
connect issue_slots[8].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23
connect issue_slots[8].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12
connect issue_slots[8].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3
connect issue_slots[8].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2
connect issue_slots[8].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1
connect issue_slots[8].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen
connect issue_slots[8].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst
connect issue_slots[8].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel
connect issue_slots[8].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel
connect issue_slots[8].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[8].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm
connect issue_slots[8].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel
connect issue_slots[8].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename
connect issue_slots[8].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[8].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[8].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[8].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[8].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov
connect issue_slots[8].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc
connect issue_slots[8].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[8].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret
connect issue_slots[8].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[8].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence
connect issue_slots[8].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[8].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[8].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[8].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type
connect issue_slots[8].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[8].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[8].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel
connect issue_slots[8].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint
connect issue_slots[8].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint
connect issue_slots[8].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint
connect issue_slots[8].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child
connect issue_slots[8].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child
connect issue_slots[8].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen
connect issue_slots[8].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen
connect issue_slots[8].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued
connect issue_slots[8].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0]
connect issue_slots[8].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1]
connect issue_slots[8].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2]
connect issue_slots[8].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3]
connect issue_slots[8].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4]
connect issue_slots[8].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5]
connect issue_slots[8].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6]
connect issue_slots[8].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7]
connect issue_slots[8].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8]
connect issue_slots[8].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9]
connect issue_slots[8].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0]
connect issue_slots[8].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1]
connect issue_slots[8].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2]
connect issue_slots[8].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3]
connect issue_slots[8].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[8].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[8].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[8].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[8].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[8].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[8].kill, io.flush_pipeline
connect issue_slots[9].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy
connect issue_slots[9].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask
connect issue_slots[9].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable
connect issue_slots[9].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc
connect issue_slots[9].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc
connect issue_slots[9].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if
connect issue_slots[9].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if
connect issue_slots[9].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if
connect issue_slots[9].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if
connect issue_slots[9].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if
connect issue_slots[9].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ
connect issue_slots[9].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm
connect issue_slots[9].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val
connect issue_slots[9].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op
connect issue_slots[9].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw
connect issue_slots[9].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en
connect issue_slots[9].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype
connect issue_slots[9].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype
connect issue_slots[9].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype
connect issue_slots[9].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3
connect issue_slots[9].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2
connect issue_slots[9].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1
connect issue_slots[9].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst
connect issue_slots[9].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1
connect issue_slots[9].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd
connect issue_slots[9].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit
connect issue_slots[9].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique
connect issue_slots[9].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq
connect issue_slots[9].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq
connect issue_slots[9].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed
connect issue_slots[9].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size
connect issue_slots[9].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd
connect issue_slots[9].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause
connect issue_slots[9].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception
connect issue_slots[9].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst
connect issue_slots[9].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy
connect issue_slots[9].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy
connect issue_slots[9].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy
connect issue_slots[9].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy
connect issue_slots[9].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred
connect issue_slots[9].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3
connect issue_slots[9].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2
connect issue_slots[9].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1
connect issue_slots[9].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst
connect issue_slots[9].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx
connect issue_slots[9].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx
connect issue_slots[9].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx
connect issue_slots[9].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx
connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec
connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags
connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt
connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div
connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma
connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe
connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint
connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint
connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23
connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12
connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3
connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2
connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1
connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen
connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst
connect issue_slots[9].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel
connect issue_slots[9].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel
connect issue_slots[9].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed
connect issue_slots[9].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm
connect issue_slots[9].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel
connect issue_slots[9].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename
connect issue_slots[9].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken
connect issue_slots[9].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob
connect issue_slots[9].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst
connect issue_slots[9].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx
connect issue_slots[9].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov
connect issue_slots[9].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc
connect issue_slots[9].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc
connect issue_slots[9].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret
connect issue_slots[9].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo
connect issue_slots[9].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence
connect issue_slots[9].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei
connect issue_slots[9].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence
connect issue_slots[9].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb
connect issue_slots[9].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type
connect issue_slots[9].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag
connect issue_slots[9].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask
connect issue_slots[9].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel
connect issue_slots[9].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint
connect issue_slots[9].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint
connect issue_slots[9].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint
connect issue_slots[9].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child
connect issue_slots[9].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child
connect issue_slots[9].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen
connect issue_slots[9].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen
connect issue_slots[9].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued
connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0]
connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1]
connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2]
connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3]
connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4]
connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5]
connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6]
connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7]
connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8]
connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9]
connect issue_slots[9].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0]
connect issue_slots[9].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1]
connect issue_slots[9].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2]
connect issue_slots[9].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3]
connect issue_slots[9].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc
connect issue_slots[9].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc
connect issue_slots[9].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst
connect issue_slots[9].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst
connect issue_slots[9].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[9].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy
connect issue_slots[9].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask
connect issue_slots[9].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable
connect issue_slots[9].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc
connect issue_slots[9].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc
connect issue_slots[9].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if
connect issue_slots[9].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if
connect issue_slots[9].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if
connect issue_slots[9].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if
connect issue_slots[9].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if
connect issue_slots[9].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ
connect issue_slots[9].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm
connect issue_slots[9].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val
connect issue_slots[9].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op
connect issue_slots[9].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw
connect issue_slots[9].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en
connect issue_slots[9].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype
connect issue_slots[9].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype
connect issue_slots[9].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype
connect issue_slots[9].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3
connect issue_slots[9].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2
connect issue_slots[9].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1
connect issue_slots[9].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst
connect issue_slots[9].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1
connect issue_slots[9].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd
connect issue_slots[9].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit
connect issue_slots[9].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique
connect issue_slots[9].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq
connect issue_slots[9].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq
connect issue_slots[9].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed
connect issue_slots[9].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size
connect issue_slots[9].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd
connect issue_slots[9].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause
connect issue_slots[9].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception
connect issue_slots[9].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst
connect issue_slots[9].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy
connect issue_slots[9].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy
connect issue_slots[9].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy
connect issue_slots[9].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy
connect issue_slots[9].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred
connect issue_slots[9].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3
connect issue_slots[9].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2
connect issue_slots[9].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1
connect issue_slots[9].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst
connect issue_slots[9].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx
connect issue_slots[9].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx
connect issue_slots[9].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx
connect issue_slots[9].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx
connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec
connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags
connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt
connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div
connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma
connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe
connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint
connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint
connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23
connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12
connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3
connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2
connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1
connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen
connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst
connect issue_slots[9].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel
connect issue_slots[9].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel
connect issue_slots[9].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed
connect issue_slots[9].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm
connect issue_slots[9].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel
connect issue_slots[9].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename
connect issue_slots[9].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken
connect issue_slots[9].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob
connect issue_slots[9].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst
connect issue_slots[9].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx
connect issue_slots[9].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov
connect issue_slots[9].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc
connect issue_slots[9].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc
connect issue_slots[9].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret
connect issue_slots[9].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo
connect issue_slots[9].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence
connect issue_slots[9].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei
connect issue_slots[9].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence
connect issue_slots[9].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb
connect issue_slots[9].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type
connect issue_slots[9].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag
connect issue_slots[9].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask
connect issue_slots[9].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel
connect issue_slots[9].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint
connect issue_slots[9].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint
connect issue_slots[9].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint
connect issue_slots[9].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child
connect issue_slots[9].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child
connect issue_slots[9].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen
connect issue_slots[9].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen
connect issue_slots[9].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued
connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0]
connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1]
connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2]
connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3]
connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4]
connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5]
connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6]
connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7]
connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8]
connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9]
connect issue_slots[9].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0]
connect issue_slots[9].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1]
connect issue_slots[9].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2]
connect issue_slots[9].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3]
connect issue_slots[9].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc
connect issue_slots[9].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc
connect issue_slots[9].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst
connect issue_slots[9].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst
connect issue_slots[9].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[9].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy
connect issue_slots[9].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask
connect issue_slots[9].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable
connect issue_slots[9].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc
connect issue_slots[9].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc
connect issue_slots[9].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if
connect issue_slots[9].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if
connect issue_slots[9].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if
connect issue_slots[9].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if
connect issue_slots[9].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if
connect issue_slots[9].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ
connect issue_slots[9].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm
connect issue_slots[9].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val
connect issue_slots[9].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op
connect issue_slots[9].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw
connect issue_slots[9].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en
connect issue_slots[9].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype
connect issue_slots[9].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype
connect issue_slots[9].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype
connect issue_slots[9].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3
connect issue_slots[9].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2
connect issue_slots[9].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1
connect issue_slots[9].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst
connect issue_slots[9].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1
connect issue_slots[9].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd
connect issue_slots[9].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit
connect issue_slots[9].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique
connect issue_slots[9].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq
connect issue_slots[9].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq
connect issue_slots[9].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed
connect issue_slots[9].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size
connect issue_slots[9].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd
connect issue_slots[9].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause
connect issue_slots[9].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception
connect issue_slots[9].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst
connect issue_slots[9].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy
connect issue_slots[9].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy
connect issue_slots[9].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy
connect issue_slots[9].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy
connect issue_slots[9].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred
connect issue_slots[9].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3
connect issue_slots[9].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2
connect issue_slots[9].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1
connect issue_slots[9].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst
connect issue_slots[9].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx
connect issue_slots[9].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx
connect issue_slots[9].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx
connect issue_slots[9].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx
connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec
connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags
connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt
connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div
connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma
connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe
connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint
connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint
connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23
connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12
connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3
connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2
connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1
connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen
connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst
connect issue_slots[9].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel
connect issue_slots[9].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel
connect issue_slots[9].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed
connect issue_slots[9].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm
connect issue_slots[9].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel
connect issue_slots[9].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename
connect issue_slots[9].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken
connect issue_slots[9].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob
connect issue_slots[9].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst
connect issue_slots[9].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx
connect issue_slots[9].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov
connect issue_slots[9].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc
connect issue_slots[9].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc
connect issue_slots[9].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret
connect issue_slots[9].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo
connect issue_slots[9].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence
connect issue_slots[9].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei
connect issue_slots[9].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence
connect issue_slots[9].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb
connect issue_slots[9].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type
connect issue_slots[9].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag
connect issue_slots[9].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask
connect issue_slots[9].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel
connect issue_slots[9].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint
connect issue_slots[9].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint
connect issue_slots[9].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint
connect issue_slots[9].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child
connect issue_slots[9].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child
connect issue_slots[9].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen
connect issue_slots[9].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen
connect issue_slots[9].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued
connect issue_slots[9].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0]
connect issue_slots[9].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1]
connect issue_slots[9].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2]
connect issue_slots[9].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3]
connect issue_slots[9].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4]
connect issue_slots[9].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5]
connect issue_slots[9].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6]
connect issue_slots[9].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7]
connect issue_slots[9].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8]
connect issue_slots[9].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9]
connect issue_slots[9].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0]
connect issue_slots[9].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1]
connect issue_slots[9].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2]
connect issue_slots[9].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3]
connect issue_slots[9].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc
connect issue_slots[9].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc
connect issue_slots[9].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst
connect issue_slots[9].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst
connect issue_slots[9].wakeup_ports[2].valid, io.wakeup_ports[2].valid
connect issue_slots[9].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy
connect issue_slots[9].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask
connect issue_slots[9].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable
connect issue_slots[9].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc
connect issue_slots[9].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc
connect issue_slots[9].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if
connect issue_slots[9].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if
connect issue_slots[9].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if
connect issue_slots[9].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if
connect issue_slots[9].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if
connect issue_slots[9].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ
connect issue_slots[9].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm
connect issue_slots[9].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val
connect issue_slots[9].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op
connect issue_slots[9].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw
connect issue_slots[9].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en
connect issue_slots[9].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype
connect issue_slots[9].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype
connect issue_slots[9].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype
connect issue_slots[9].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3
connect issue_slots[9].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2
connect issue_slots[9].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1
connect issue_slots[9].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst
connect issue_slots[9].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1
connect issue_slots[9].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd
connect issue_slots[9].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit
connect issue_slots[9].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique
connect issue_slots[9].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq
connect issue_slots[9].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq
connect issue_slots[9].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed
connect issue_slots[9].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size
connect issue_slots[9].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd
connect issue_slots[9].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause
connect issue_slots[9].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception
connect issue_slots[9].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst
connect issue_slots[9].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy
connect issue_slots[9].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy
connect issue_slots[9].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy
connect issue_slots[9].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy
connect issue_slots[9].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred
connect issue_slots[9].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3
connect issue_slots[9].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2
connect issue_slots[9].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1
connect issue_slots[9].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst
connect issue_slots[9].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx
connect issue_slots[9].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx
connect issue_slots[9].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx
connect issue_slots[9].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx
connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec
connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags
connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt
connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div
connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma
connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe
connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint
connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint
connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23
connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12
connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3
connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2
connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1
connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen
connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst
connect issue_slots[9].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel
connect issue_slots[9].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel
connect issue_slots[9].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed
connect issue_slots[9].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm
connect issue_slots[9].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel
connect issue_slots[9].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename
connect issue_slots[9].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken
connect issue_slots[9].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob
connect issue_slots[9].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst
connect issue_slots[9].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx
connect issue_slots[9].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov
connect issue_slots[9].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc
connect issue_slots[9].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc
connect issue_slots[9].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret
connect issue_slots[9].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo
connect issue_slots[9].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence
connect issue_slots[9].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei
connect issue_slots[9].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence
connect issue_slots[9].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb
connect issue_slots[9].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type
connect issue_slots[9].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag
connect issue_slots[9].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask
connect issue_slots[9].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel
connect issue_slots[9].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint
connect issue_slots[9].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint
connect issue_slots[9].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint
connect issue_slots[9].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child
connect issue_slots[9].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child
connect issue_slots[9].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen
connect issue_slots[9].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen
connect issue_slots[9].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued
connect issue_slots[9].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0]
connect issue_slots[9].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1]
connect issue_slots[9].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2]
connect issue_slots[9].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3]
connect issue_slots[9].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4]
connect issue_slots[9].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5]
connect issue_slots[9].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6]
connect issue_slots[9].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7]
connect issue_slots[9].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8]
connect issue_slots[9].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9]
connect issue_slots[9].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0]
connect issue_slots[9].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1]
connect issue_slots[9].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2]
connect issue_slots[9].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3]
connect issue_slots[9].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc
connect issue_slots[9].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc
connect issue_slots[9].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst
connect issue_slots[9].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst
connect issue_slots[9].wakeup_ports[3].valid, io.wakeup_ports[3].valid
connect issue_slots[9].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[9].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[9].child_rebusys, io.child_rebusys
connect issue_slots[9].squash_grant, io.squash_grant
connect issue_slots[9].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[9].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[9].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[9].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[9].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[9].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[9].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[9].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[9].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[9].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[9].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[9].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[9].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[9].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ
connect issue_slots[9].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm
connect issue_slots[9].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[9].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op
connect issue_slots[9].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw
connect issue_slots[9].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[9].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[9].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[9].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[9].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[9].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[9].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[9].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[9].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[9].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd
connect issue_slots[9].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[9].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[9].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[9].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[9].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[9].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[9].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[9].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[9].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[9].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[9].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[9].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[9].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[9].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[9].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[9].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[9].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[9].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[9].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[9].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[9].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[9].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[9].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[9].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec
connect issue_slots[9].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags
connect issue_slots[9].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt
connect issue_slots[9].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div
connect issue_slots[9].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma
connect issue_slots[9].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe
connect issue_slots[9].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint
connect issue_slots[9].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint
connect issue_slots[9].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut
connect issue_slots[9].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn
connect issue_slots[9].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23
connect issue_slots[9].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12
connect issue_slots[9].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3
connect issue_slots[9].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2
connect issue_slots[9].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1
connect issue_slots[9].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen
connect issue_slots[9].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst
connect issue_slots[9].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel
connect issue_slots[9].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel
connect issue_slots[9].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[9].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm
connect issue_slots[9].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel
connect issue_slots[9].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename
connect issue_slots[9].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[9].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[9].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[9].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[9].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov
connect issue_slots[9].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc
connect issue_slots[9].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[9].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret
connect issue_slots[9].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[9].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence
connect issue_slots[9].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[9].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[9].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[9].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type
connect issue_slots[9].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[9].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[9].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel
connect issue_slots[9].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint
connect issue_slots[9].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint
connect issue_slots[9].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint
connect issue_slots[9].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child
connect issue_slots[9].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child
connect issue_slots[9].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen
connect issue_slots[9].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen
connect issue_slots[9].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued
connect issue_slots[9].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0]
connect issue_slots[9].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1]
connect issue_slots[9].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2]
connect issue_slots[9].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3]
connect issue_slots[9].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4]
connect issue_slots[9].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5]
connect issue_slots[9].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6]
connect issue_slots[9].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7]
connect issue_slots[9].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8]
connect issue_slots[9].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9]
connect issue_slots[9].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0]
connect issue_slots[9].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1]
connect issue_slots[9].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2]
connect issue_slots[9].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3]
connect issue_slots[9].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[9].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[9].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[9].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[9].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[9].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[9].kill, io.flush_pipeline
connect issue_slots[10].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy
connect issue_slots[10].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask
connect issue_slots[10].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable
connect issue_slots[10].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc
connect issue_slots[10].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc
connect issue_slots[10].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if
connect issue_slots[10].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if
connect issue_slots[10].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if
connect issue_slots[10].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if
connect issue_slots[10].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if
connect issue_slots[10].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ
connect issue_slots[10].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm
connect issue_slots[10].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val
connect issue_slots[10].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op
connect issue_slots[10].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw
connect issue_slots[10].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en
connect issue_slots[10].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype
connect issue_slots[10].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype
connect issue_slots[10].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype
connect issue_slots[10].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3
connect issue_slots[10].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2
connect issue_slots[10].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1
connect issue_slots[10].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst
connect issue_slots[10].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1
connect issue_slots[10].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd
connect issue_slots[10].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit
connect issue_slots[10].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique
connect issue_slots[10].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq
connect issue_slots[10].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq
connect issue_slots[10].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed
connect issue_slots[10].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size
connect issue_slots[10].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd
connect issue_slots[10].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause
connect issue_slots[10].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception
connect issue_slots[10].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst
connect issue_slots[10].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy
connect issue_slots[10].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy
connect issue_slots[10].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy
connect issue_slots[10].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy
connect issue_slots[10].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred
connect issue_slots[10].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3
connect issue_slots[10].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2
connect issue_slots[10].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1
connect issue_slots[10].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst
connect issue_slots[10].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx
connect issue_slots[10].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx
connect issue_slots[10].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx
connect issue_slots[10].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx
connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec
connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags
connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt
connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div
connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma
connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe
connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint
connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint
connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23
connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12
connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3
connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2
connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1
connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen
connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst
connect issue_slots[10].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel
connect issue_slots[10].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel
connect issue_slots[10].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed
connect issue_slots[10].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm
connect issue_slots[10].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel
connect issue_slots[10].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename
connect issue_slots[10].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken
connect issue_slots[10].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob
connect issue_slots[10].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst
connect issue_slots[10].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx
connect issue_slots[10].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov
connect issue_slots[10].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc
connect issue_slots[10].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc
connect issue_slots[10].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret
connect issue_slots[10].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo
connect issue_slots[10].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence
connect issue_slots[10].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei
connect issue_slots[10].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence
connect issue_slots[10].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb
connect issue_slots[10].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type
connect issue_slots[10].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag
connect issue_slots[10].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask
connect issue_slots[10].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel
connect issue_slots[10].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint
connect issue_slots[10].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint
connect issue_slots[10].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint
connect issue_slots[10].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child
connect issue_slots[10].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child
connect issue_slots[10].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen
connect issue_slots[10].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen
connect issue_slots[10].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued
connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0]
connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1]
connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2]
connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3]
connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4]
connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5]
connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6]
connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7]
connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8]
connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9]
connect issue_slots[10].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0]
connect issue_slots[10].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1]
connect issue_slots[10].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2]
connect issue_slots[10].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3]
connect issue_slots[10].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc
connect issue_slots[10].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc
connect issue_slots[10].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst
connect issue_slots[10].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst
connect issue_slots[10].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[10].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy
connect issue_slots[10].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask
connect issue_slots[10].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable
connect issue_slots[10].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc
connect issue_slots[10].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc
connect issue_slots[10].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if
connect issue_slots[10].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if
connect issue_slots[10].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if
connect issue_slots[10].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if
connect issue_slots[10].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if
connect issue_slots[10].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ
connect issue_slots[10].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm
connect issue_slots[10].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val
connect issue_slots[10].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op
connect issue_slots[10].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw
connect issue_slots[10].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en
connect issue_slots[10].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype
connect issue_slots[10].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype
connect issue_slots[10].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype
connect issue_slots[10].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3
connect issue_slots[10].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2
connect issue_slots[10].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1
connect issue_slots[10].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst
connect issue_slots[10].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1
connect issue_slots[10].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd
connect issue_slots[10].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit
connect issue_slots[10].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique
connect issue_slots[10].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq
connect issue_slots[10].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq
connect issue_slots[10].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed
connect issue_slots[10].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size
connect issue_slots[10].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd
connect issue_slots[10].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause
connect issue_slots[10].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception
connect issue_slots[10].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst
connect issue_slots[10].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy
connect issue_slots[10].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy
connect issue_slots[10].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy
connect issue_slots[10].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy
connect issue_slots[10].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred
connect issue_slots[10].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3
connect issue_slots[10].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2
connect issue_slots[10].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1
connect issue_slots[10].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst
connect issue_slots[10].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx
connect issue_slots[10].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx
connect issue_slots[10].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx
connect issue_slots[10].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx
connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec
connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags
connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt
connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div
connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma
connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe
connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint
connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint
connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23
connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12
connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3
connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2
connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1
connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen
connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst
connect issue_slots[10].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel
connect issue_slots[10].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel
connect issue_slots[10].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed
connect issue_slots[10].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm
connect issue_slots[10].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel
connect issue_slots[10].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename
connect issue_slots[10].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken
connect issue_slots[10].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob
connect issue_slots[10].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst
connect issue_slots[10].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx
connect issue_slots[10].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov
connect issue_slots[10].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc
connect issue_slots[10].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc
connect issue_slots[10].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret
connect issue_slots[10].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo
connect issue_slots[10].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence
connect issue_slots[10].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei
connect issue_slots[10].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence
connect issue_slots[10].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb
connect issue_slots[10].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type
connect issue_slots[10].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag
connect issue_slots[10].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask
connect issue_slots[10].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel
connect issue_slots[10].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint
connect issue_slots[10].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint
connect issue_slots[10].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint
connect issue_slots[10].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child
connect issue_slots[10].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child
connect issue_slots[10].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen
connect issue_slots[10].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen
connect issue_slots[10].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued
connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0]
connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1]
connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2]
connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3]
connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4]
connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5]
connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6]
connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7]
connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8]
connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9]
connect issue_slots[10].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0]
connect issue_slots[10].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1]
connect issue_slots[10].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2]
connect issue_slots[10].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3]
connect issue_slots[10].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc
connect issue_slots[10].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc
connect issue_slots[10].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst
connect issue_slots[10].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst
connect issue_slots[10].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[10].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy
connect issue_slots[10].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask
connect issue_slots[10].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable
connect issue_slots[10].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc
connect issue_slots[10].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc
connect issue_slots[10].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if
connect issue_slots[10].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if
connect issue_slots[10].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if
connect issue_slots[10].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if
connect issue_slots[10].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if
connect issue_slots[10].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ
connect issue_slots[10].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm
connect issue_slots[10].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val
connect issue_slots[10].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op
connect issue_slots[10].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw
connect issue_slots[10].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en
connect issue_slots[10].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype
connect issue_slots[10].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype
connect issue_slots[10].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype
connect issue_slots[10].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3
connect issue_slots[10].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2
connect issue_slots[10].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1
connect issue_slots[10].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst
connect issue_slots[10].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1
connect issue_slots[10].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd
connect issue_slots[10].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit
connect issue_slots[10].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique
connect issue_slots[10].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq
connect issue_slots[10].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq
connect issue_slots[10].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed
connect issue_slots[10].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size
connect issue_slots[10].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd
connect issue_slots[10].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause
connect issue_slots[10].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception
connect issue_slots[10].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst
connect issue_slots[10].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy
connect issue_slots[10].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy
connect issue_slots[10].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy
connect issue_slots[10].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy
connect issue_slots[10].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred
connect issue_slots[10].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3
connect issue_slots[10].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2
connect issue_slots[10].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1
connect issue_slots[10].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst
connect issue_slots[10].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx
connect issue_slots[10].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx
connect issue_slots[10].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx
connect issue_slots[10].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx
connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec
connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags
connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt
connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div
connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma
connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe
connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint
connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint
connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23
connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12
connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3
connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2
connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1
connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen
connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst
connect issue_slots[10].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel
connect issue_slots[10].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel
connect issue_slots[10].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed
connect issue_slots[10].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm
connect issue_slots[10].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel
connect issue_slots[10].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename
connect issue_slots[10].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken
connect issue_slots[10].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob
connect issue_slots[10].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst
connect issue_slots[10].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx
connect issue_slots[10].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov
connect issue_slots[10].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc
connect issue_slots[10].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc
connect issue_slots[10].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret
connect issue_slots[10].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo
connect issue_slots[10].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence
connect issue_slots[10].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei
connect issue_slots[10].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence
connect issue_slots[10].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb
connect issue_slots[10].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type
connect issue_slots[10].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag
connect issue_slots[10].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask
connect issue_slots[10].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel
connect issue_slots[10].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint
connect issue_slots[10].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint
connect issue_slots[10].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint
connect issue_slots[10].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child
connect issue_slots[10].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child
connect issue_slots[10].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen
connect issue_slots[10].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen
connect issue_slots[10].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued
connect issue_slots[10].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0]
connect issue_slots[10].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1]
connect issue_slots[10].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2]
connect issue_slots[10].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3]
connect issue_slots[10].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4]
connect issue_slots[10].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5]
connect issue_slots[10].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6]
connect issue_slots[10].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7]
connect issue_slots[10].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8]
connect issue_slots[10].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9]
connect issue_slots[10].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0]
connect issue_slots[10].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1]
connect issue_slots[10].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2]
connect issue_slots[10].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3]
connect issue_slots[10].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc
connect issue_slots[10].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc
connect issue_slots[10].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst
connect issue_slots[10].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst
connect issue_slots[10].wakeup_ports[2].valid, io.wakeup_ports[2].valid
connect issue_slots[10].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy
connect issue_slots[10].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask
connect issue_slots[10].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable
connect issue_slots[10].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc
connect issue_slots[10].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc
connect issue_slots[10].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if
connect issue_slots[10].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if
connect issue_slots[10].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if
connect issue_slots[10].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if
connect issue_slots[10].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if
connect issue_slots[10].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ
connect issue_slots[10].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm
connect issue_slots[10].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val
connect issue_slots[10].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op
connect issue_slots[10].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw
connect issue_slots[10].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en
connect issue_slots[10].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype
connect issue_slots[10].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype
connect issue_slots[10].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype
connect issue_slots[10].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3
connect issue_slots[10].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2
connect issue_slots[10].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1
connect issue_slots[10].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst
connect issue_slots[10].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1
connect issue_slots[10].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd
connect issue_slots[10].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit
connect issue_slots[10].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique
connect issue_slots[10].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq
connect issue_slots[10].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq
connect issue_slots[10].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed
connect issue_slots[10].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size
connect issue_slots[10].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd
connect issue_slots[10].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause
connect issue_slots[10].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception
connect issue_slots[10].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst
connect issue_slots[10].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy
connect issue_slots[10].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy
connect issue_slots[10].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy
connect issue_slots[10].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy
connect issue_slots[10].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred
connect issue_slots[10].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3
connect issue_slots[10].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2
connect issue_slots[10].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1
connect issue_slots[10].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst
connect issue_slots[10].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx
connect issue_slots[10].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx
connect issue_slots[10].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx
connect issue_slots[10].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx
connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec
connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags
connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt
connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div
connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma
connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe
connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint
connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint
connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23
connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12
connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3
connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2
connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1
connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen
connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst
connect issue_slots[10].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel
connect issue_slots[10].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel
connect issue_slots[10].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed
connect issue_slots[10].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm
connect issue_slots[10].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel
connect issue_slots[10].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename
connect issue_slots[10].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken
connect issue_slots[10].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob
connect issue_slots[10].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst
connect issue_slots[10].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx
connect issue_slots[10].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov
connect issue_slots[10].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc
connect issue_slots[10].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc
connect issue_slots[10].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret
connect issue_slots[10].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo
connect issue_slots[10].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence
connect issue_slots[10].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei
connect issue_slots[10].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence
connect issue_slots[10].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb
connect issue_slots[10].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type
connect issue_slots[10].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag
connect issue_slots[10].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask
connect issue_slots[10].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel
connect issue_slots[10].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint
connect issue_slots[10].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint
connect issue_slots[10].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint
connect issue_slots[10].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child
connect issue_slots[10].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child
connect issue_slots[10].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen
connect issue_slots[10].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen
connect issue_slots[10].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued
connect issue_slots[10].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0]
connect issue_slots[10].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1]
connect issue_slots[10].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2]
connect issue_slots[10].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3]
connect issue_slots[10].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4]
connect issue_slots[10].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5]
connect issue_slots[10].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6]
connect issue_slots[10].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7]
connect issue_slots[10].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8]
connect issue_slots[10].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9]
connect issue_slots[10].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0]
connect issue_slots[10].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1]
connect issue_slots[10].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2]
connect issue_slots[10].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3]
connect issue_slots[10].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc
connect issue_slots[10].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc
connect issue_slots[10].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst
connect issue_slots[10].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst
connect issue_slots[10].wakeup_ports[3].valid, io.wakeup_ports[3].valid
connect issue_slots[10].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[10].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[10].child_rebusys, io.child_rebusys
connect issue_slots[10].squash_grant, io.squash_grant
connect issue_slots[10].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[10].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[10].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[10].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[10].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[10].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[10].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[10].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[10].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[10].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[10].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[10].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[10].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[10].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ
connect issue_slots[10].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm
connect issue_slots[10].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[10].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op
connect issue_slots[10].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw
connect issue_slots[10].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[10].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[10].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[10].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[10].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[10].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[10].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[10].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[10].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[10].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd
connect issue_slots[10].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[10].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[10].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[10].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[10].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[10].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[10].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[10].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[10].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[10].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[10].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[10].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[10].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[10].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[10].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[10].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[10].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[10].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[10].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[10].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[10].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[10].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[10].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[10].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec
connect issue_slots[10].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags
connect issue_slots[10].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt
connect issue_slots[10].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div
connect issue_slots[10].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma
connect issue_slots[10].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe
connect issue_slots[10].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint
connect issue_slots[10].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint
connect issue_slots[10].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut
connect issue_slots[10].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn
connect issue_slots[10].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23
connect issue_slots[10].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12
connect issue_slots[10].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3
connect issue_slots[10].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2
connect issue_slots[10].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1
connect issue_slots[10].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen
connect issue_slots[10].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst
connect issue_slots[10].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel
connect issue_slots[10].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel
connect issue_slots[10].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[10].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm
connect issue_slots[10].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel
connect issue_slots[10].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename
connect issue_slots[10].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[10].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[10].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[10].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[10].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov
connect issue_slots[10].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc
connect issue_slots[10].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[10].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret
connect issue_slots[10].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[10].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence
connect issue_slots[10].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[10].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[10].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[10].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type
connect issue_slots[10].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[10].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[10].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel
connect issue_slots[10].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint
connect issue_slots[10].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint
connect issue_slots[10].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint
connect issue_slots[10].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child
connect issue_slots[10].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child
connect issue_slots[10].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen
connect issue_slots[10].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen
connect issue_slots[10].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued
connect issue_slots[10].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0]
connect issue_slots[10].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1]
connect issue_slots[10].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2]
connect issue_slots[10].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3]
connect issue_slots[10].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4]
connect issue_slots[10].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5]
connect issue_slots[10].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6]
connect issue_slots[10].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7]
connect issue_slots[10].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8]
connect issue_slots[10].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9]
connect issue_slots[10].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0]
connect issue_slots[10].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1]
connect issue_slots[10].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2]
connect issue_slots[10].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3]
connect issue_slots[10].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[10].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[10].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[10].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[10].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[10].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[10].kill, io.flush_pipeline
connect issue_slots[11].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy
connect issue_slots[11].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask
connect issue_slots[11].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable
connect issue_slots[11].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc
connect issue_slots[11].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc
connect issue_slots[11].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if
connect issue_slots[11].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if
connect issue_slots[11].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if
connect issue_slots[11].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if
connect issue_slots[11].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if
connect issue_slots[11].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ
connect issue_slots[11].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm
connect issue_slots[11].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val
connect issue_slots[11].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op
connect issue_slots[11].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw
connect issue_slots[11].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en
connect issue_slots[11].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype
connect issue_slots[11].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype
connect issue_slots[11].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype
connect issue_slots[11].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3
connect issue_slots[11].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2
connect issue_slots[11].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1
connect issue_slots[11].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst
connect issue_slots[11].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1
connect issue_slots[11].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd
connect issue_slots[11].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit
connect issue_slots[11].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique
connect issue_slots[11].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq
connect issue_slots[11].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq
connect issue_slots[11].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed
connect issue_slots[11].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size
connect issue_slots[11].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd
connect issue_slots[11].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause
connect issue_slots[11].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception
connect issue_slots[11].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst
connect issue_slots[11].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy
connect issue_slots[11].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy
connect issue_slots[11].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy
connect issue_slots[11].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy
connect issue_slots[11].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred
connect issue_slots[11].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3
connect issue_slots[11].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2
connect issue_slots[11].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1
connect issue_slots[11].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst
connect issue_slots[11].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx
connect issue_slots[11].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx
connect issue_slots[11].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx
connect issue_slots[11].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx
connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec
connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags
connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt
connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div
connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma
connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe
connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint
connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint
connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23
connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12
connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3
connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2
connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1
connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen
connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst
connect issue_slots[11].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel
connect issue_slots[11].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel
connect issue_slots[11].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed
connect issue_slots[11].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm
connect issue_slots[11].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel
connect issue_slots[11].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename
connect issue_slots[11].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken
connect issue_slots[11].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob
connect issue_slots[11].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst
connect issue_slots[11].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx
connect issue_slots[11].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov
connect issue_slots[11].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc
connect issue_slots[11].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc
connect issue_slots[11].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret
connect issue_slots[11].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo
connect issue_slots[11].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence
connect issue_slots[11].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei
connect issue_slots[11].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence
connect issue_slots[11].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb
connect issue_slots[11].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type
connect issue_slots[11].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag
connect issue_slots[11].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask
connect issue_slots[11].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel
connect issue_slots[11].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint
connect issue_slots[11].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint
connect issue_slots[11].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint
connect issue_slots[11].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child
connect issue_slots[11].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child
connect issue_slots[11].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen
connect issue_slots[11].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen
connect issue_slots[11].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued
connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0]
connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1]
connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2]
connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3]
connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4]
connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5]
connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6]
connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7]
connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8]
connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9]
connect issue_slots[11].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0]
connect issue_slots[11].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1]
connect issue_slots[11].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2]
connect issue_slots[11].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3]
connect issue_slots[11].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc
connect issue_slots[11].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc
connect issue_slots[11].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst
connect issue_slots[11].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst
connect issue_slots[11].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[11].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy
connect issue_slots[11].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask
connect issue_slots[11].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable
connect issue_slots[11].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc
connect issue_slots[11].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc
connect issue_slots[11].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if
connect issue_slots[11].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if
connect issue_slots[11].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if
connect issue_slots[11].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if
connect issue_slots[11].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if
connect issue_slots[11].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ
connect issue_slots[11].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm
connect issue_slots[11].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val
connect issue_slots[11].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op
connect issue_slots[11].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw
connect issue_slots[11].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en
connect issue_slots[11].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype
connect issue_slots[11].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype
connect issue_slots[11].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype
connect issue_slots[11].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3
connect issue_slots[11].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2
connect issue_slots[11].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1
connect issue_slots[11].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst
connect issue_slots[11].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1
connect issue_slots[11].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd
connect issue_slots[11].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit
connect issue_slots[11].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique
connect issue_slots[11].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq
connect issue_slots[11].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq
connect issue_slots[11].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed
connect issue_slots[11].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size
connect issue_slots[11].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd
connect issue_slots[11].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause
connect issue_slots[11].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception
connect issue_slots[11].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst
connect issue_slots[11].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy
connect issue_slots[11].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy
connect issue_slots[11].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy
connect issue_slots[11].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy
connect issue_slots[11].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred
connect issue_slots[11].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3
connect issue_slots[11].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2
connect issue_slots[11].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1
connect issue_slots[11].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst
connect issue_slots[11].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx
connect issue_slots[11].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx
connect issue_slots[11].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx
connect issue_slots[11].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx
connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec
connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags
connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt
connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div
connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma
connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe
connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint
connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint
connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23
connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12
connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3
connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2
connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1
connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen
connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst
connect issue_slots[11].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel
connect issue_slots[11].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel
connect issue_slots[11].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed
connect issue_slots[11].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm
connect issue_slots[11].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel
connect issue_slots[11].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename
connect issue_slots[11].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken
connect issue_slots[11].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob
connect issue_slots[11].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst
connect issue_slots[11].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx
connect issue_slots[11].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov
connect issue_slots[11].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc
connect issue_slots[11].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc
connect issue_slots[11].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret
connect issue_slots[11].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo
connect issue_slots[11].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence
connect issue_slots[11].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei
connect issue_slots[11].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence
connect issue_slots[11].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb
connect issue_slots[11].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type
connect issue_slots[11].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag
connect issue_slots[11].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask
connect issue_slots[11].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel
connect issue_slots[11].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint
connect issue_slots[11].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint
connect issue_slots[11].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint
connect issue_slots[11].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child
connect issue_slots[11].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child
connect issue_slots[11].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen
connect issue_slots[11].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen
connect issue_slots[11].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued
connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0]
connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1]
connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2]
connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3]
connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4]
connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5]
connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6]
connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7]
connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8]
connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9]
connect issue_slots[11].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0]
connect issue_slots[11].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1]
connect issue_slots[11].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2]
connect issue_slots[11].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3]
connect issue_slots[11].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc
connect issue_slots[11].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc
connect issue_slots[11].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst
connect issue_slots[11].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst
connect issue_slots[11].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[11].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy
connect issue_slots[11].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask
connect issue_slots[11].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable
connect issue_slots[11].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc
connect issue_slots[11].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc
connect issue_slots[11].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if
connect issue_slots[11].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if
connect issue_slots[11].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if
connect issue_slots[11].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if
connect issue_slots[11].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if
connect issue_slots[11].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ
connect issue_slots[11].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm
connect issue_slots[11].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val
connect issue_slots[11].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op
connect issue_slots[11].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw
connect issue_slots[11].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en
connect issue_slots[11].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype
connect issue_slots[11].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype
connect issue_slots[11].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype
connect issue_slots[11].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3
connect issue_slots[11].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2
connect issue_slots[11].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1
connect issue_slots[11].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst
connect issue_slots[11].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1
connect issue_slots[11].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd
connect issue_slots[11].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit
connect issue_slots[11].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique
connect issue_slots[11].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq
connect issue_slots[11].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq
connect issue_slots[11].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed
connect issue_slots[11].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size
connect issue_slots[11].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd
connect issue_slots[11].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause
connect issue_slots[11].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception
connect issue_slots[11].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst
connect issue_slots[11].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy
connect issue_slots[11].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy
connect issue_slots[11].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy
connect issue_slots[11].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy
connect issue_slots[11].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred
connect issue_slots[11].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3
connect issue_slots[11].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2
connect issue_slots[11].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1
connect issue_slots[11].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst
connect issue_slots[11].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx
connect issue_slots[11].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx
connect issue_slots[11].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx
connect issue_slots[11].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx
connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec
connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags
connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt
connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div
connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma
connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe
connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint
connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint
connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23
connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12
connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3
connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2
connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1
connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen
connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst
connect issue_slots[11].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel
connect issue_slots[11].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel
connect issue_slots[11].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed
connect issue_slots[11].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm
connect issue_slots[11].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel
connect issue_slots[11].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename
connect issue_slots[11].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken
connect issue_slots[11].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob
connect issue_slots[11].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst
connect issue_slots[11].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx
connect issue_slots[11].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov
connect issue_slots[11].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc
connect issue_slots[11].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc
connect issue_slots[11].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret
connect issue_slots[11].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo
connect issue_slots[11].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence
connect issue_slots[11].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei
connect issue_slots[11].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence
connect issue_slots[11].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb
connect issue_slots[11].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type
connect issue_slots[11].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag
connect issue_slots[11].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask
connect issue_slots[11].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel
connect issue_slots[11].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint
connect issue_slots[11].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint
connect issue_slots[11].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint
connect issue_slots[11].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child
connect issue_slots[11].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child
connect issue_slots[11].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen
connect issue_slots[11].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen
connect issue_slots[11].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued
connect issue_slots[11].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0]
connect issue_slots[11].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1]
connect issue_slots[11].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2]
connect issue_slots[11].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3]
connect issue_slots[11].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4]
connect issue_slots[11].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5]
connect issue_slots[11].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6]
connect issue_slots[11].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7]
connect issue_slots[11].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8]
connect issue_slots[11].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9]
connect issue_slots[11].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0]
connect issue_slots[11].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1]
connect issue_slots[11].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2]
connect issue_slots[11].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3]
connect issue_slots[11].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc
connect issue_slots[11].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc
connect issue_slots[11].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst
connect issue_slots[11].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst
connect issue_slots[11].wakeup_ports[2].valid, io.wakeup_ports[2].valid
connect issue_slots[11].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy
connect issue_slots[11].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask
connect issue_slots[11].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable
connect issue_slots[11].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc
connect issue_slots[11].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc
connect issue_slots[11].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if
connect issue_slots[11].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if
connect issue_slots[11].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if
connect issue_slots[11].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if
connect issue_slots[11].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if
connect issue_slots[11].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ
connect issue_slots[11].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm
connect issue_slots[11].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val
connect issue_slots[11].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op
connect issue_slots[11].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw
connect issue_slots[11].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en
connect issue_slots[11].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype
connect issue_slots[11].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype
connect issue_slots[11].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype
connect issue_slots[11].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3
connect issue_slots[11].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2
connect issue_slots[11].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1
connect issue_slots[11].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst
connect issue_slots[11].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1
connect issue_slots[11].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd
connect issue_slots[11].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit
connect issue_slots[11].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique
connect issue_slots[11].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq
connect issue_slots[11].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq
connect issue_slots[11].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed
connect issue_slots[11].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size
connect issue_slots[11].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd
connect issue_slots[11].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause
connect issue_slots[11].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception
connect issue_slots[11].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst
connect issue_slots[11].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy
connect issue_slots[11].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy
connect issue_slots[11].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy
connect issue_slots[11].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy
connect issue_slots[11].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred
connect issue_slots[11].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3
connect issue_slots[11].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2
connect issue_slots[11].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1
connect issue_slots[11].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst
connect issue_slots[11].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx
connect issue_slots[11].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx
connect issue_slots[11].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx
connect issue_slots[11].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx
connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec
connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags
connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt
connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div
connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma
connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe
connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint
connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint
connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23
connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12
connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3
connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2
connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1
connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen
connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst
connect issue_slots[11].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel
connect issue_slots[11].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel
connect issue_slots[11].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed
connect issue_slots[11].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm
connect issue_slots[11].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel
connect issue_slots[11].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename
connect issue_slots[11].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken
connect issue_slots[11].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob
connect issue_slots[11].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst
connect issue_slots[11].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx
connect issue_slots[11].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov
connect issue_slots[11].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc
connect issue_slots[11].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc
connect issue_slots[11].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret
connect issue_slots[11].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo
connect issue_slots[11].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence
connect issue_slots[11].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei
connect issue_slots[11].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence
connect issue_slots[11].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb
connect issue_slots[11].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type
connect issue_slots[11].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag
connect issue_slots[11].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask
connect issue_slots[11].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel
connect issue_slots[11].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint
connect issue_slots[11].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint
connect issue_slots[11].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint
connect issue_slots[11].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child
connect issue_slots[11].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child
connect issue_slots[11].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen
connect issue_slots[11].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen
connect issue_slots[11].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued
connect issue_slots[11].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0]
connect issue_slots[11].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1]
connect issue_slots[11].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2]
connect issue_slots[11].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3]
connect issue_slots[11].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4]
connect issue_slots[11].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5]
connect issue_slots[11].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6]
connect issue_slots[11].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7]
connect issue_slots[11].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8]
connect issue_slots[11].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9]
connect issue_slots[11].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0]
connect issue_slots[11].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1]
connect issue_slots[11].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2]
connect issue_slots[11].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3]
connect issue_slots[11].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc
connect issue_slots[11].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc
connect issue_slots[11].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst
connect issue_slots[11].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst
connect issue_slots[11].wakeup_ports[3].valid, io.wakeup_ports[3].valid
connect issue_slots[11].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[11].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[11].child_rebusys, io.child_rebusys
connect issue_slots[11].squash_grant, io.squash_grant
connect issue_slots[11].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[11].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[11].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[11].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[11].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[11].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[11].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[11].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[11].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[11].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[11].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[11].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[11].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[11].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ
connect issue_slots[11].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm
connect issue_slots[11].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[11].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op
connect issue_slots[11].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw
connect issue_slots[11].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[11].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[11].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[11].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[11].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[11].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[11].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[11].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[11].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[11].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd
connect issue_slots[11].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[11].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[11].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[11].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[11].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[11].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[11].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[11].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[11].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[11].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[11].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[11].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[11].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[11].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[11].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[11].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[11].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[11].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[11].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[11].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[11].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[11].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[11].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[11].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec
connect issue_slots[11].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags
connect issue_slots[11].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt
connect issue_slots[11].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div
connect issue_slots[11].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma
connect issue_slots[11].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe
connect issue_slots[11].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint
connect issue_slots[11].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint
connect issue_slots[11].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut
connect issue_slots[11].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn
connect issue_slots[11].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23
connect issue_slots[11].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12
connect issue_slots[11].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3
connect issue_slots[11].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2
connect issue_slots[11].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1
connect issue_slots[11].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen
connect issue_slots[11].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst
connect issue_slots[11].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel
connect issue_slots[11].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel
connect issue_slots[11].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[11].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm
connect issue_slots[11].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel
connect issue_slots[11].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename
connect issue_slots[11].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[11].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[11].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[11].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[11].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov
connect issue_slots[11].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc
connect issue_slots[11].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[11].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret
connect issue_slots[11].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[11].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence
connect issue_slots[11].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[11].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[11].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[11].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type
connect issue_slots[11].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[11].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[11].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel
connect issue_slots[11].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint
connect issue_slots[11].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint
connect issue_slots[11].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint
connect issue_slots[11].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child
connect issue_slots[11].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child
connect issue_slots[11].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen
connect issue_slots[11].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen
connect issue_slots[11].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued
connect issue_slots[11].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0]
connect issue_slots[11].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1]
connect issue_slots[11].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2]
connect issue_slots[11].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3]
connect issue_slots[11].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4]
connect issue_slots[11].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5]
connect issue_slots[11].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6]
connect issue_slots[11].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7]
connect issue_slots[11].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8]
connect issue_slots[11].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9]
connect issue_slots[11].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0]
connect issue_slots[11].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1]
connect issue_slots[11].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2]
connect issue_slots[11].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3]
connect issue_slots[11].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[11].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[11].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[11].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[11].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[11].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[11].kill, io.flush_pipeline
connect issue_slots[12].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy
connect issue_slots[12].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask
connect issue_slots[12].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable
connect issue_slots[12].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc
connect issue_slots[12].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc
connect issue_slots[12].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if
connect issue_slots[12].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if
connect issue_slots[12].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if
connect issue_slots[12].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if
connect issue_slots[12].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if
connect issue_slots[12].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ
connect issue_slots[12].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm
connect issue_slots[12].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val
connect issue_slots[12].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op
connect issue_slots[12].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw
connect issue_slots[12].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en
connect issue_slots[12].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype
connect issue_slots[12].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype
connect issue_slots[12].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype
connect issue_slots[12].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3
connect issue_slots[12].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2
connect issue_slots[12].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1
connect issue_slots[12].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst
connect issue_slots[12].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1
connect issue_slots[12].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd
connect issue_slots[12].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit
connect issue_slots[12].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique
connect issue_slots[12].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq
connect issue_slots[12].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq
connect issue_slots[12].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed
connect issue_slots[12].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size
connect issue_slots[12].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd
connect issue_slots[12].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause
connect issue_slots[12].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception
connect issue_slots[12].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst
connect issue_slots[12].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy
connect issue_slots[12].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy
connect issue_slots[12].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy
connect issue_slots[12].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy
connect issue_slots[12].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred
connect issue_slots[12].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3
connect issue_slots[12].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2
connect issue_slots[12].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1
connect issue_slots[12].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst
connect issue_slots[12].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx
connect issue_slots[12].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx
connect issue_slots[12].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx
connect issue_slots[12].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx
connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec
connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags
connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt
connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div
connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma
connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe
connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint
connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint
connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23
connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12
connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3
connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2
connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1
connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen
connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst
connect issue_slots[12].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel
connect issue_slots[12].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel
connect issue_slots[12].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed
connect issue_slots[12].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm
connect issue_slots[12].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel
connect issue_slots[12].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename
connect issue_slots[12].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken
connect issue_slots[12].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob
connect issue_slots[12].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst
connect issue_slots[12].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx
connect issue_slots[12].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov
connect issue_slots[12].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc
connect issue_slots[12].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc
connect issue_slots[12].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret
connect issue_slots[12].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo
connect issue_slots[12].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence
connect issue_slots[12].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei
connect issue_slots[12].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence
connect issue_slots[12].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb
connect issue_slots[12].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type
connect issue_slots[12].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag
connect issue_slots[12].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask
connect issue_slots[12].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel
connect issue_slots[12].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint
connect issue_slots[12].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint
connect issue_slots[12].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint
connect issue_slots[12].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child
connect issue_slots[12].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child
connect issue_slots[12].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen
connect issue_slots[12].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen
connect issue_slots[12].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued
connect issue_slots[12].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0]
connect issue_slots[12].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1]
connect issue_slots[12].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2]
connect issue_slots[12].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3]
connect issue_slots[12].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4]
connect issue_slots[12].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5]
connect issue_slots[12].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6]
connect issue_slots[12].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7]
connect issue_slots[12].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8]
connect issue_slots[12].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9]
connect issue_slots[12].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0]
connect issue_slots[12].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1]
connect issue_slots[12].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2]
connect issue_slots[12].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3]
connect issue_slots[12].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc
connect issue_slots[12].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc
connect issue_slots[12].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst
connect issue_slots[12].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst
connect issue_slots[12].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[12].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy
connect issue_slots[12].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask
connect issue_slots[12].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable
connect issue_slots[12].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc
connect issue_slots[12].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc
connect issue_slots[12].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if
connect issue_slots[12].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if
connect issue_slots[12].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if
connect issue_slots[12].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if
connect issue_slots[12].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if
connect issue_slots[12].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ
connect issue_slots[12].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm
connect issue_slots[12].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val
connect issue_slots[12].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op
connect issue_slots[12].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw
connect issue_slots[12].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en
connect issue_slots[12].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype
connect issue_slots[12].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype
connect issue_slots[12].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype
connect issue_slots[12].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3
connect issue_slots[12].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2
connect issue_slots[12].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1
connect issue_slots[12].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst
connect issue_slots[12].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1
connect issue_slots[12].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd
connect issue_slots[12].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit
connect issue_slots[12].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique
connect issue_slots[12].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq
connect issue_slots[12].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq
connect issue_slots[12].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed
connect issue_slots[12].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size
connect issue_slots[12].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd
connect issue_slots[12].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause
connect issue_slots[12].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception
connect issue_slots[12].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst
connect issue_slots[12].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy
connect issue_slots[12].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy
connect issue_slots[12].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy
connect issue_slots[12].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy
connect issue_slots[12].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred
connect issue_slots[12].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3
connect issue_slots[12].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2
connect issue_slots[12].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1
connect issue_slots[12].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst
connect issue_slots[12].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx
connect issue_slots[12].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx
connect issue_slots[12].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx
connect issue_slots[12].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx
connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec
connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags
connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt
connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div
connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma
connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe
connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint
connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint
connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23
connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12
connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3
connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2
connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1
connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen
connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst
connect issue_slots[12].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel
connect issue_slots[12].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel
connect issue_slots[12].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed
connect issue_slots[12].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm
connect issue_slots[12].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel
connect issue_slots[12].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename
connect issue_slots[12].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken
connect issue_slots[12].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob
connect issue_slots[12].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst
connect issue_slots[12].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx
connect issue_slots[12].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov
connect issue_slots[12].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc
connect issue_slots[12].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc
connect issue_slots[12].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret
connect issue_slots[12].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo
connect issue_slots[12].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence
connect issue_slots[12].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei
connect issue_slots[12].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence
connect issue_slots[12].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb
connect issue_slots[12].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type
connect issue_slots[12].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag
connect issue_slots[12].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask
connect issue_slots[12].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel
connect issue_slots[12].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint
connect issue_slots[12].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint
connect issue_slots[12].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint
connect issue_slots[12].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child
connect issue_slots[12].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child
connect issue_slots[12].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen
connect issue_slots[12].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen
connect issue_slots[12].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued
connect issue_slots[12].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0]
connect issue_slots[12].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1]
connect issue_slots[12].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2]
connect issue_slots[12].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3]
connect issue_slots[12].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4]
connect issue_slots[12].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5]
connect issue_slots[12].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6]
connect issue_slots[12].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7]
connect issue_slots[12].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8]
connect issue_slots[12].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9]
connect issue_slots[12].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0]
connect issue_slots[12].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1]
connect issue_slots[12].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2]
connect issue_slots[12].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3]
connect issue_slots[12].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc
connect issue_slots[12].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc
connect issue_slots[12].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst
connect issue_slots[12].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst
connect issue_slots[12].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[12].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy
connect issue_slots[12].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask
connect issue_slots[12].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable
connect issue_slots[12].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc
connect issue_slots[12].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc
connect issue_slots[12].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if
connect issue_slots[12].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if
connect issue_slots[12].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if
connect issue_slots[12].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if
connect issue_slots[12].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if
connect issue_slots[12].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ
connect issue_slots[12].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm
connect issue_slots[12].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val
connect issue_slots[12].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op
connect issue_slots[12].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw
connect issue_slots[12].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en
connect issue_slots[12].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype
connect issue_slots[12].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype
connect issue_slots[12].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype
connect issue_slots[12].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3
connect issue_slots[12].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2
connect issue_slots[12].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1
connect issue_slots[12].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst
connect issue_slots[12].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1
connect issue_slots[12].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd
connect issue_slots[12].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit
connect issue_slots[12].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique
connect issue_slots[12].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq
connect issue_slots[12].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq
connect issue_slots[12].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed
connect issue_slots[12].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size
connect issue_slots[12].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd
connect issue_slots[12].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause
connect issue_slots[12].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception
connect issue_slots[12].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst
connect issue_slots[12].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy
connect issue_slots[12].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy
connect issue_slots[12].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy
connect issue_slots[12].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy
connect issue_slots[12].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred
connect issue_slots[12].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3
connect issue_slots[12].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2
connect issue_slots[12].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1
connect issue_slots[12].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst
connect issue_slots[12].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx
connect issue_slots[12].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx
connect issue_slots[12].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx
connect issue_slots[12].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx
connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec
connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags
connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt
connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div
connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma
connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe
connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint
connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint
connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23
connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12
connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3
connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2
connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1
connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen
connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst
connect issue_slots[12].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel
connect issue_slots[12].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel
connect issue_slots[12].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed
connect issue_slots[12].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm
connect issue_slots[12].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel
connect issue_slots[12].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename
connect issue_slots[12].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken
connect issue_slots[12].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob
connect issue_slots[12].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst
connect issue_slots[12].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx
connect issue_slots[12].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov
connect issue_slots[12].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc
connect issue_slots[12].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc
connect issue_slots[12].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret
connect issue_slots[12].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo
connect issue_slots[12].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence
connect issue_slots[12].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei
connect issue_slots[12].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence
connect issue_slots[12].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb
connect issue_slots[12].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type
connect issue_slots[12].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag
connect issue_slots[12].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask
connect issue_slots[12].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel
connect issue_slots[12].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint
connect issue_slots[12].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint
connect issue_slots[12].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint
connect issue_slots[12].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child
connect issue_slots[12].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child
connect issue_slots[12].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen
connect issue_slots[12].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen
connect issue_slots[12].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued
connect issue_slots[12].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0]
connect issue_slots[12].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1]
connect issue_slots[12].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2]
connect issue_slots[12].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3]
connect issue_slots[12].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4]
connect issue_slots[12].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5]
connect issue_slots[12].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6]
connect issue_slots[12].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7]
connect issue_slots[12].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8]
connect issue_slots[12].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9]
connect issue_slots[12].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0]
connect issue_slots[12].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1]
connect issue_slots[12].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2]
connect issue_slots[12].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3]
connect issue_slots[12].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc
connect issue_slots[12].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc
connect issue_slots[12].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst
connect issue_slots[12].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst
connect issue_slots[12].wakeup_ports[2].valid, io.wakeup_ports[2].valid
connect issue_slots[12].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy
connect issue_slots[12].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask
connect issue_slots[12].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable
connect issue_slots[12].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc
connect issue_slots[12].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc
connect issue_slots[12].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if
connect issue_slots[12].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if
connect issue_slots[12].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if
connect issue_slots[12].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if
connect issue_slots[12].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if
connect issue_slots[12].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ
connect issue_slots[12].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm
connect issue_slots[12].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val
connect issue_slots[12].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op
connect issue_slots[12].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw
connect issue_slots[12].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en
connect issue_slots[12].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype
connect issue_slots[12].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype
connect issue_slots[12].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype
connect issue_slots[12].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3
connect issue_slots[12].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2
connect issue_slots[12].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1
connect issue_slots[12].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst
connect issue_slots[12].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1
connect issue_slots[12].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd
connect issue_slots[12].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit
connect issue_slots[12].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique
connect issue_slots[12].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq
connect issue_slots[12].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq
connect issue_slots[12].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed
connect issue_slots[12].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size
connect issue_slots[12].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd
connect issue_slots[12].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause
connect issue_slots[12].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception
connect issue_slots[12].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst
connect issue_slots[12].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy
connect issue_slots[12].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy
connect issue_slots[12].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy
connect issue_slots[12].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy
connect issue_slots[12].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred
connect issue_slots[12].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3
connect issue_slots[12].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2
connect issue_slots[12].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1
connect issue_slots[12].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst
connect issue_slots[12].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx
connect issue_slots[12].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx
connect issue_slots[12].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx
connect issue_slots[12].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx
connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec
connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags
connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt
connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div
connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma
connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe
connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint
connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint
connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23
connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12
connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3
connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2
connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1
connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen
connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst
connect issue_slots[12].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel
connect issue_slots[12].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel
connect issue_slots[12].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed
connect issue_slots[12].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm
connect issue_slots[12].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel
connect issue_slots[12].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename
connect issue_slots[12].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken
connect issue_slots[12].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob
connect issue_slots[12].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst
connect issue_slots[12].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx
connect issue_slots[12].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov
connect issue_slots[12].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc
connect issue_slots[12].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc
connect issue_slots[12].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret
connect issue_slots[12].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo
connect issue_slots[12].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence
connect issue_slots[12].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei
connect issue_slots[12].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence
connect issue_slots[12].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb
connect issue_slots[12].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type
connect issue_slots[12].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag
connect issue_slots[12].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask
connect issue_slots[12].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel
connect issue_slots[12].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint
connect issue_slots[12].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint
connect issue_slots[12].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint
connect issue_slots[12].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child
connect issue_slots[12].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child
connect issue_slots[12].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen
connect issue_slots[12].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen
connect issue_slots[12].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued
connect issue_slots[12].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0]
connect issue_slots[12].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1]
connect issue_slots[12].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2]
connect issue_slots[12].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3]
connect issue_slots[12].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4]
connect issue_slots[12].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5]
connect issue_slots[12].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6]
connect issue_slots[12].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7]
connect issue_slots[12].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8]
connect issue_slots[12].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9]
connect issue_slots[12].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0]
connect issue_slots[12].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1]
connect issue_slots[12].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2]
connect issue_slots[12].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3]
connect issue_slots[12].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc
connect issue_slots[12].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc
connect issue_slots[12].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst
connect issue_slots[12].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst
connect issue_slots[12].wakeup_ports[3].valid, io.wakeup_ports[3].valid
connect issue_slots[12].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[12].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[12].child_rebusys, io.child_rebusys
connect issue_slots[12].squash_grant, io.squash_grant
connect issue_slots[12].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[12].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[12].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[12].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[12].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[12].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[12].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[12].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[12].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[12].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[12].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[12].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[12].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[12].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ
connect issue_slots[12].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm
connect issue_slots[12].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[12].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op
connect issue_slots[12].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw
connect issue_slots[12].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[12].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[12].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[12].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[12].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[12].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[12].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[12].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[12].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[12].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd
connect issue_slots[12].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[12].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[12].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[12].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[12].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[12].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[12].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[12].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[12].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[12].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[12].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[12].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[12].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[12].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[12].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[12].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[12].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[12].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[12].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[12].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[12].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[12].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[12].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[12].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec
connect issue_slots[12].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags
connect issue_slots[12].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt
connect issue_slots[12].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div
connect issue_slots[12].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma
connect issue_slots[12].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe
connect issue_slots[12].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint
connect issue_slots[12].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint
connect issue_slots[12].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut
connect issue_slots[12].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn
connect issue_slots[12].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23
connect issue_slots[12].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12
connect issue_slots[12].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3
connect issue_slots[12].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2
connect issue_slots[12].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1
connect issue_slots[12].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen
connect issue_slots[12].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst
connect issue_slots[12].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel
connect issue_slots[12].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel
connect issue_slots[12].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[12].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm
connect issue_slots[12].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel
connect issue_slots[12].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename
connect issue_slots[12].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[12].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[12].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[12].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[12].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov
connect issue_slots[12].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc
connect issue_slots[12].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[12].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret
connect issue_slots[12].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[12].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence
connect issue_slots[12].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[12].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[12].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[12].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type
connect issue_slots[12].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[12].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[12].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel
connect issue_slots[12].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint
connect issue_slots[12].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint
connect issue_slots[12].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint
connect issue_slots[12].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child
connect issue_slots[12].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child
connect issue_slots[12].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen
connect issue_slots[12].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen
connect issue_slots[12].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued
connect issue_slots[12].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0]
connect issue_slots[12].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1]
connect issue_slots[12].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2]
connect issue_slots[12].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3]
connect issue_slots[12].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4]
connect issue_slots[12].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5]
connect issue_slots[12].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6]
connect issue_slots[12].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7]
connect issue_slots[12].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8]
connect issue_slots[12].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9]
connect issue_slots[12].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0]
connect issue_slots[12].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1]
connect issue_slots[12].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2]
connect issue_slots[12].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3]
connect issue_slots[12].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[12].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[12].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[12].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[12].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[12].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[12].kill, io.flush_pipeline
connect issue_slots[13].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy
connect issue_slots[13].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask
connect issue_slots[13].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable
connect issue_slots[13].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc
connect issue_slots[13].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc
connect issue_slots[13].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if
connect issue_slots[13].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if
connect issue_slots[13].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if
connect issue_slots[13].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if
connect issue_slots[13].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if
connect issue_slots[13].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ
connect issue_slots[13].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm
connect issue_slots[13].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val
connect issue_slots[13].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op
connect issue_slots[13].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw
connect issue_slots[13].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en
connect issue_slots[13].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype
connect issue_slots[13].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype
connect issue_slots[13].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype
connect issue_slots[13].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3
connect issue_slots[13].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2
connect issue_slots[13].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1
connect issue_slots[13].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst
connect issue_slots[13].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1
connect issue_slots[13].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd
connect issue_slots[13].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit
connect issue_slots[13].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique
connect issue_slots[13].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq
connect issue_slots[13].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq
connect issue_slots[13].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed
connect issue_slots[13].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size
connect issue_slots[13].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd
connect issue_slots[13].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause
connect issue_slots[13].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception
connect issue_slots[13].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst
connect issue_slots[13].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy
connect issue_slots[13].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy
connect issue_slots[13].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy
connect issue_slots[13].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy
connect issue_slots[13].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred
connect issue_slots[13].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3
connect issue_slots[13].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2
connect issue_slots[13].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1
connect issue_slots[13].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst
connect issue_slots[13].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx
connect issue_slots[13].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx
connect issue_slots[13].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx
connect issue_slots[13].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx
connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec
connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags
connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt
connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div
connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma
connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe
connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint
connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint
connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23
connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12
connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3
connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2
connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1
connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen
connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst
connect issue_slots[13].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel
connect issue_slots[13].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel
connect issue_slots[13].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed
connect issue_slots[13].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm
connect issue_slots[13].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel
connect issue_slots[13].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename
connect issue_slots[13].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken
connect issue_slots[13].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob
connect issue_slots[13].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst
connect issue_slots[13].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx
connect issue_slots[13].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov
connect issue_slots[13].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc
connect issue_slots[13].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc
connect issue_slots[13].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret
connect issue_slots[13].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo
connect issue_slots[13].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence
connect issue_slots[13].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei
connect issue_slots[13].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence
connect issue_slots[13].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb
connect issue_slots[13].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type
connect issue_slots[13].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag
connect issue_slots[13].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask
connect issue_slots[13].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel
connect issue_slots[13].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint
connect issue_slots[13].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint
connect issue_slots[13].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint
connect issue_slots[13].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child
connect issue_slots[13].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child
connect issue_slots[13].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen
connect issue_slots[13].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen
connect issue_slots[13].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued
connect issue_slots[13].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0]
connect issue_slots[13].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1]
connect issue_slots[13].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2]
connect issue_slots[13].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3]
connect issue_slots[13].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4]
connect issue_slots[13].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5]
connect issue_slots[13].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6]
connect issue_slots[13].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7]
connect issue_slots[13].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8]
connect issue_slots[13].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9]
connect issue_slots[13].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0]
connect issue_slots[13].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1]
connect issue_slots[13].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2]
connect issue_slots[13].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3]
connect issue_slots[13].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc
connect issue_slots[13].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc
connect issue_slots[13].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst
connect issue_slots[13].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst
connect issue_slots[13].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[13].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy
connect issue_slots[13].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask
connect issue_slots[13].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable
connect issue_slots[13].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc
connect issue_slots[13].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc
connect issue_slots[13].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if
connect issue_slots[13].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if
connect issue_slots[13].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if
connect issue_slots[13].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if
connect issue_slots[13].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if
connect issue_slots[13].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ
connect issue_slots[13].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm
connect issue_slots[13].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val
connect issue_slots[13].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op
connect issue_slots[13].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw
connect issue_slots[13].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en
connect issue_slots[13].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype
connect issue_slots[13].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype
connect issue_slots[13].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype
connect issue_slots[13].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3
connect issue_slots[13].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2
connect issue_slots[13].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1
connect issue_slots[13].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst
connect issue_slots[13].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1
connect issue_slots[13].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd
connect issue_slots[13].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit
connect issue_slots[13].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique
connect issue_slots[13].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq
connect issue_slots[13].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq
connect issue_slots[13].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed
connect issue_slots[13].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size
connect issue_slots[13].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd
connect issue_slots[13].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause
connect issue_slots[13].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception
connect issue_slots[13].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst
connect issue_slots[13].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy
connect issue_slots[13].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy
connect issue_slots[13].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy
connect issue_slots[13].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy
connect issue_slots[13].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred
connect issue_slots[13].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3
connect issue_slots[13].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2
connect issue_slots[13].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1
connect issue_slots[13].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst
connect issue_slots[13].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx
connect issue_slots[13].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx
connect issue_slots[13].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx
connect issue_slots[13].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx
connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec
connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags
connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt
connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div
connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma
connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe
connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint
connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint
connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23
connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12
connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3
connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2
connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1
connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen
connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst
connect issue_slots[13].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel
connect issue_slots[13].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel
connect issue_slots[13].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed
connect issue_slots[13].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm
connect issue_slots[13].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel
connect issue_slots[13].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename
connect issue_slots[13].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken
connect issue_slots[13].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob
connect issue_slots[13].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst
connect issue_slots[13].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx
connect issue_slots[13].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov
connect issue_slots[13].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc
connect issue_slots[13].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc
connect issue_slots[13].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret
connect issue_slots[13].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo
connect issue_slots[13].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence
connect issue_slots[13].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei
connect issue_slots[13].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence
connect issue_slots[13].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb
connect issue_slots[13].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type
connect issue_slots[13].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag
connect issue_slots[13].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask
connect issue_slots[13].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel
connect issue_slots[13].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint
connect issue_slots[13].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint
connect issue_slots[13].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint
connect issue_slots[13].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child
connect issue_slots[13].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child
connect issue_slots[13].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen
connect issue_slots[13].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen
connect issue_slots[13].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued
connect issue_slots[13].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0]
connect issue_slots[13].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1]
connect issue_slots[13].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2]
connect issue_slots[13].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3]
connect issue_slots[13].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4]
connect issue_slots[13].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5]
connect issue_slots[13].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6]
connect issue_slots[13].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7]
connect issue_slots[13].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8]
connect issue_slots[13].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9]
connect issue_slots[13].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0]
connect issue_slots[13].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1]
connect issue_slots[13].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2]
connect issue_slots[13].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3]
connect issue_slots[13].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc
connect issue_slots[13].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc
connect issue_slots[13].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst
connect issue_slots[13].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst
connect issue_slots[13].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[13].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy
connect issue_slots[13].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask
connect issue_slots[13].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable
connect issue_slots[13].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc
connect issue_slots[13].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc
connect issue_slots[13].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if
connect issue_slots[13].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if
connect issue_slots[13].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if
connect issue_slots[13].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if
connect issue_slots[13].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if
connect issue_slots[13].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ
connect issue_slots[13].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm
connect issue_slots[13].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val
connect issue_slots[13].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op
connect issue_slots[13].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw
connect issue_slots[13].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en
connect issue_slots[13].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype
connect issue_slots[13].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype
connect issue_slots[13].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype
connect issue_slots[13].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3
connect issue_slots[13].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2
connect issue_slots[13].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1
connect issue_slots[13].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst
connect issue_slots[13].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1
connect issue_slots[13].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd
connect issue_slots[13].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit
connect issue_slots[13].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique
connect issue_slots[13].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq
connect issue_slots[13].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq
connect issue_slots[13].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed
connect issue_slots[13].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size
connect issue_slots[13].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd
connect issue_slots[13].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause
connect issue_slots[13].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception
connect issue_slots[13].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst
connect issue_slots[13].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy
connect issue_slots[13].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy
connect issue_slots[13].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy
connect issue_slots[13].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy
connect issue_slots[13].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred
connect issue_slots[13].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3
connect issue_slots[13].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2
connect issue_slots[13].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1
connect issue_slots[13].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst
connect issue_slots[13].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx
connect issue_slots[13].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx
connect issue_slots[13].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx
connect issue_slots[13].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx
connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec
connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags
connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt
connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div
connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma
connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe
connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint
connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint
connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23
connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12
connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3
connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2
connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1
connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen
connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst
connect issue_slots[13].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel
connect issue_slots[13].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel
connect issue_slots[13].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed
connect issue_slots[13].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm
connect issue_slots[13].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel
connect issue_slots[13].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename
connect issue_slots[13].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken
connect issue_slots[13].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob
connect issue_slots[13].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst
connect issue_slots[13].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx
connect issue_slots[13].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov
connect issue_slots[13].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc
connect issue_slots[13].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc
connect issue_slots[13].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret
connect issue_slots[13].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo
connect issue_slots[13].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence
connect issue_slots[13].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei
connect issue_slots[13].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence
connect issue_slots[13].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb
connect issue_slots[13].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type
connect issue_slots[13].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag
connect issue_slots[13].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask
connect issue_slots[13].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel
connect issue_slots[13].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint
connect issue_slots[13].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint
connect issue_slots[13].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint
connect issue_slots[13].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child
connect issue_slots[13].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child
connect issue_slots[13].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen
connect issue_slots[13].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen
connect issue_slots[13].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued
connect issue_slots[13].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0]
connect issue_slots[13].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1]
connect issue_slots[13].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2]
connect issue_slots[13].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3]
connect issue_slots[13].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4]
connect issue_slots[13].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5]
connect issue_slots[13].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6]
connect issue_slots[13].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7]
connect issue_slots[13].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8]
connect issue_slots[13].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9]
connect issue_slots[13].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0]
connect issue_slots[13].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1]
connect issue_slots[13].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2]
connect issue_slots[13].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3]
connect issue_slots[13].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc
connect issue_slots[13].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc
connect issue_slots[13].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst
connect issue_slots[13].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst
connect issue_slots[13].wakeup_ports[2].valid, io.wakeup_ports[2].valid
connect issue_slots[13].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy
connect issue_slots[13].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask
connect issue_slots[13].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable
connect issue_slots[13].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc
connect issue_slots[13].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc
connect issue_slots[13].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if
connect issue_slots[13].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if
connect issue_slots[13].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if
connect issue_slots[13].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if
connect issue_slots[13].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if
connect issue_slots[13].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ
connect issue_slots[13].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm
connect issue_slots[13].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val
connect issue_slots[13].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op
connect issue_slots[13].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw
connect issue_slots[13].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en
connect issue_slots[13].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype
connect issue_slots[13].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype
connect issue_slots[13].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype
connect issue_slots[13].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3
connect issue_slots[13].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2
connect issue_slots[13].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1
connect issue_slots[13].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst
connect issue_slots[13].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1
connect issue_slots[13].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd
connect issue_slots[13].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit
connect issue_slots[13].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique
connect issue_slots[13].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq
connect issue_slots[13].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq
connect issue_slots[13].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed
connect issue_slots[13].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size
connect issue_slots[13].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd
connect issue_slots[13].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause
connect issue_slots[13].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception
connect issue_slots[13].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst
connect issue_slots[13].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy
connect issue_slots[13].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy
connect issue_slots[13].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy
connect issue_slots[13].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy
connect issue_slots[13].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred
connect issue_slots[13].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3
connect issue_slots[13].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2
connect issue_slots[13].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1
connect issue_slots[13].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst
connect issue_slots[13].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx
connect issue_slots[13].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx
connect issue_slots[13].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx
connect issue_slots[13].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx
connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec
connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags
connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt
connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div
connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma
connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe
connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint
connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint
connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23
connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12
connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3
connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2
connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1
connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen
connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst
connect issue_slots[13].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel
connect issue_slots[13].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel
connect issue_slots[13].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed
connect issue_slots[13].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm
connect issue_slots[13].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel
connect issue_slots[13].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename
connect issue_slots[13].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken
connect issue_slots[13].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob
connect issue_slots[13].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst
connect issue_slots[13].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx
connect issue_slots[13].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov
connect issue_slots[13].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc
connect issue_slots[13].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc
connect issue_slots[13].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret
connect issue_slots[13].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo
connect issue_slots[13].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence
connect issue_slots[13].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei
connect issue_slots[13].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence
connect issue_slots[13].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb
connect issue_slots[13].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type
connect issue_slots[13].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag
connect issue_slots[13].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask
connect issue_slots[13].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel
connect issue_slots[13].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint
connect issue_slots[13].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint
connect issue_slots[13].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint
connect issue_slots[13].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child
connect issue_slots[13].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child
connect issue_slots[13].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen
connect issue_slots[13].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen
connect issue_slots[13].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued
connect issue_slots[13].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0]
connect issue_slots[13].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1]
connect issue_slots[13].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2]
connect issue_slots[13].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3]
connect issue_slots[13].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4]
connect issue_slots[13].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5]
connect issue_slots[13].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6]
connect issue_slots[13].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7]
connect issue_slots[13].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8]
connect issue_slots[13].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9]
connect issue_slots[13].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0]
connect issue_slots[13].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1]
connect issue_slots[13].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2]
connect issue_slots[13].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3]
connect issue_slots[13].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc
connect issue_slots[13].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc
connect issue_slots[13].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst
connect issue_slots[13].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst
connect issue_slots[13].wakeup_ports[3].valid, io.wakeup_ports[3].valid
connect issue_slots[13].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[13].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[13].child_rebusys, io.child_rebusys
connect issue_slots[13].squash_grant, io.squash_grant
connect issue_slots[13].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[13].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[13].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[13].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[13].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[13].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[13].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[13].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[13].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[13].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[13].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[13].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[13].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[13].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ
connect issue_slots[13].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm
connect issue_slots[13].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[13].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op
connect issue_slots[13].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw
connect issue_slots[13].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[13].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[13].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[13].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[13].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[13].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[13].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[13].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[13].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[13].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd
connect issue_slots[13].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[13].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[13].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[13].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[13].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[13].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[13].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[13].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[13].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[13].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[13].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[13].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[13].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[13].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[13].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[13].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[13].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[13].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[13].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[13].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[13].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[13].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[13].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[13].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec
connect issue_slots[13].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags
connect issue_slots[13].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt
connect issue_slots[13].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div
connect issue_slots[13].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma
connect issue_slots[13].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe
connect issue_slots[13].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint
connect issue_slots[13].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint
connect issue_slots[13].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut
connect issue_slots[13].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn
connect issue_slots[13].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23
connect issue_slots[13].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12
connect issue_slots[13].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3
connect issue_slots[13].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2
connect issue_slots[13].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1
connect issue_slots[13].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen
connect issue_slots[13].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst
connect issue_slots[13].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel
connect issue_slots[13].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel
connect issue_slots[13].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[13].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm
connect issue_slots[13].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel
connect issue_slots[13].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename
connect issue_slots[13].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[13].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[13].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[13].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[13].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov
connect issue_slots[13].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc
connect issue_slots[13].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[13].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret
connect issue_slots[13].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[13].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence
connect issue_slots[13].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[13].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[13].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[13].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type
connect issue_slots[13].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[13].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[13].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel
connect issue_slots[13].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint
connect issue_slots[13].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint
connect issue_slots[13].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint
connect issue_slots[13].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child
connect issue_slots[13].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child
connect issue_slots[13].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen
connect issue_slots[13].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen
connect issue_slots[13].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued
connect issue_slots[13].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0]
connect issue_slots[13].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1]
connect issue_slots[13].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2]
connect issue_slots[13].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3]
connect issue_slots[13].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4]
connect issue_slots[13].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5]
connect issue_slots[13].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6]
connect issue_slots[13].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7]
connect issue_slots[13].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8]
connect issue_slots[13].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9]
connect issue_slots[13].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0]
connect issue_slots[13].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1]
connect issue_slots[13].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2]
connect issue_slots[13].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3]
connect issue_slots[13].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[13].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[13].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[13].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[13].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[13].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[13].kill, io.flush_pipeline
connect issue_slots[14].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy
connect issue_slots[14].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask
connect issue_slots[14].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable
connect issue_slots[14].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc
connect issue_slots[14].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc
connect issue_slots[14].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if
connect issue_slots[14].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if
connect issue_slots[14].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if
connect issue_slots[14].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if
connect issue_slots[14].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if
connect issue_slots[14].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ
connect issue_slots[14].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm
connect issue_slots[14].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val
connect issue_slots[14].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op
connect issue_slots[14].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw
connect issue_slots[14].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en
connect issue_slots[14].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype
connect issue_slots[14].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype
connect issue_slots[14].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype
connect issue_slots[14].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3
connect issue_slots[14].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2
connect issue_slots[14].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1
connect issue_slots[14].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst
connect issue_slots[14].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1
connect issue_slots[14].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd
connect issue_slots[14].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit
connect issue_slots[14].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique
connect issue_slots[14].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq
connect issue_slots[14].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq
connect issue_slots[14].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed
connect issue_slots[14].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size
connect issue_slots[14].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd
connect issue_slots[14].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause
connect issue_slots[14].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception
connect issue_slots[14].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst
connect issue_slots[14].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy
connect issue_slots[14].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy
connect issue_slots[14].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy
connect issue_slots[14].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy
connect issue_slots[14].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred
connect issue_slots[14].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3
connect issue_slots[14].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2
connect issue_slots[14].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1
connect issue_slots[14].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst
connect issue_slots[14].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx
connect issue_slots[14].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx
connect issue_slots[14].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx
connect issue_slots[14].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx
connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec
connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags
connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt
connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div
connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma
connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe
connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint
connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint
connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23
connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12
connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3
connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2
connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1
connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen
connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst
connect issue_slots[14].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel
connect issue_slots[14].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel
connect issue_slots[14].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed
connect issue_slots[14].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm
connect issue_slots[14].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel
connect issue_slots[14].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename
connect issue_slots[14].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken
connect issue_slots[14].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob
connect issue_slots[14].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst
connect issue_slots[14].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx
connect issue_slots[14].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov
connect issue_slots[14].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc
connect issue_slots[14].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc
connect issue_slots[14].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret
connect issue_slots[14].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo
connect issue_slots[14].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence
connect issue_slots[14].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei
connect issue_slots[14].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence
connect issue_slots[14].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb
connect issue_slots[14].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type
connect issue_slots[14].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag
connect issue_slots[14].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask
connect issue_slots[14].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel
connect issue_slots[14].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint
connect issue_slots[14].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint
connect issue_slots[14].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint
connect issue_slots[14].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child
connect issue_slots[14].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child
connect issue_slots[14].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen
connect issue_slots[14].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen
connect issue_slots[14].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued
connect issue_slots[14].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0]
connect issue_slots[14].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1]
connect issue_slots[14].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2]
connect issue_slots[14].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3]
connect issue_slots[14].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4]
connect issue_slots[14].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5]
connect issue_slots[14].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6]
connect issue_slots[14].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7]
connect issue_slots[14].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8]
connect issue_slots[14].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9]
connect issue_slots[14].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0]
connect issue_slots[14].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1]
connect issue_slots[14].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2]
connect issue_slots[14].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3]
connect issue_slots[14].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc
connect issue_slots[14].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc
connect issue_slots[14].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst
connect issue_slots[14].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst
connect issue_slots[14].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[14].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy
connect issue_slots[14].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask
connect issue_slots[14].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable
connect issue_slots[14].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc
connect issue_slots[14].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc
connect issue_slots[14].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if
connect issue_slots[14].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if
connect issue_slots[14].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if
connect issue_slots[14].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if
connect issue_slots[14].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if
connect issue_slots[14].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ
connect issue_slots[14].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm
connect issue_slots[14].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val
connect issue_slots[14].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op
connect issue_slots[14].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw
connect issue_slots[14].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en
connect issue_slots[14].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype
connect issue_slots[14].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype
connect issue_slots[14].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype
connect issue_slots[14].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3
connect issue_slots[14].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2
connect issue_slots[14].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1
connect issue_slots[14].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst
connect issue_slots[14].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1
connect issue_slots[14].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd
connect issue_slots[14].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit
connect issue_slots[14].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique
connect issue_slots[14].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq
connect issue_slots[14].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq
connect issue_slots[14].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed
connect issue_slots[14].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size
connect issue_slots[14].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd
connect issue_slots[14].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause
connect issue_slots[14].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception
connect issue_slots[14].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst
connect issue_slots[14].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy
connect issue_slots[14].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy
connect issue_slots[14].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy
connect issue_slots[14].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy
connect issue_slots[14].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred
connect issue_slots[14].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3
connect issue_slots[14].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2
connect issue_slots[14].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1
connect issue_slots[14].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst
connect issue_slots[14].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx
connect issue_slots[14].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx
connect issue_slots[14].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx
connect issue_slots[14].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx
connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec
connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags
connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt
connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div
connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma
connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe
connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint
connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint
connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23
connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12
connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3
connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2
connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1
connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen
connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst
connect issue_slots[14].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel
connect issue_slots[14].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel
connect issue_slots[14].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed
connect issue_slots[14].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm
connect issue_slots[14].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel
connect issue_slots[14].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename
connect issue_slots[14].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken
connect issue_slots[14].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob
connect issue_slots[14].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst
connect issue_slots[14].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx
connect issue_slots[14].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov
connect issue_slots[14].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc
connect issue_slots[14].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc
connect issue_slots[14].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret
connect issue_slots[14].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo
connect issue_slots[14].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence
connect issue_slots[14].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei
connect issue_slots[14].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence
connect issue_slots[14].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb
connect issue_slots[14].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type
connect issue_slots[14].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag
connect issue_slots[14].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask
connect issue_slots[14].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel
connect issue_slots[14].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint
connect issue_slots[14].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint
connect issue_slots[14].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint
connect issue_slots[14].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child
connect issue_slots[14].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child
connect issue_slots[14].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen
connect issue_slots[14].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen
connect issue_slots[14].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued
connect issue_slots[14].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0]
connect issue_slots[14].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1]
connect issue_slots[14].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2]
connect issue_slots[14].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3]
connect issue_slots[14].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4]
connect issue_slots[14].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5]
connect issue_slots[14].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6]
connect issue_slots[14].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7]
connect issue_slots[14].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8]
connect issue_slots[14].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9]
connect issue_slots[14].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0]
connect issue_slots[14].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1]
connect issue_slots[14].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2]
connect issue_slots[14].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3]
connect issue_slots[14].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc
connect issue_slots[14].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc
connect issue_slots[14].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst
connect issue_slots[14].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst
connect issue_slots[14].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[14].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy
connect issue_slots[14].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask
connect issue_slots[14].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable
connect issue_slots[14].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc
connect issue_slots[14].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc
connect issue_slots[14].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if
connect issue_slots[14].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if
connect issue_slots[14].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if
connect issue_slots[14].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if
connect issue_slots[14].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if
connect issue_slots[14].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ
connect issue_slots[14].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm
connect issue_slots[14].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val
connect issue_slots[14].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op
connect issue_slots[14].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw
connect issue_slots[14].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en
connect issue_slots[14].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype
connect issue_slots[14].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype
connect issue_slots[14].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype
connect issue_slots[14].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3
connect issue_slots[14].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2
connect issue_slots[14].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1
connect issue_slots[14].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst
connect issue_slots[14].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1
connect issue_slots[14].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd
connect issue_slots[14].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit
connect issue_slots[14].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique
connect issue_slots[14].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq
connect issue_slots[14].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq
connect issue_slots[14].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed
connect issue_slots[14].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size
connect issue_slots[14].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd
connect issue_slots[14].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause
connect issue_slots[14].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception
connect issue_slots[14].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst
connect issue_slots[14].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy
connect issue_slots[14].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy
connect issue_slots[14].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy
connect issue_slots[14].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy
connect issue_slots[14].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred
connect issue_slots[14].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3
connect issue_slots[14].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2
connect issue_slots[14].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1
connect issue_slots[14].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst
connect issue_slots[14].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx
connect issue_slots[14].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx
connect issue_slots[14].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx
connect issue_slots[14].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx
connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec
connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags
connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt
connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div
connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma
connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe
connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint
connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint
connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23
connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12
connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3
connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2
connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1
connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen
connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst
connect issue_slots[14].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel
connect issue_slots[14].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel
connect issue_slots[14].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed
connect issue_slots[14].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm
connect issue_slots[14].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel
connect issue_slots[14].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename
connect issue_slots[14].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken
connect issue_slots[14].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob
connect issue_slots[14].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst
connect issue_slots[14].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx
connect issue_slots[14].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov
connect issue_slots[14].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc
connect issue_slots[14].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc
connect issue_slots[14].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret
connect issue_slots[14].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo
connect issue_slots[14].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence
connect issue_slots[14].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei
connect issue_slots[14].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence
connect issue_slots[14].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb
connect issue_slots[14].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type
connect issue_slots[14].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag
connect issue_slots[14].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask
connect issue_slots[14].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel
connect issue_slots[14].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint
connect issue_slots[14].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint
connect issue_slots[14].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint
connect issue_slots[14].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child
connect issue_slots[14].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child
connect issue_slots[14].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen
connect issue_slots[14].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen
connect issue_slots[14].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued
connect issue_slots[14].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0]
connect issue_slots[14].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1]
connect issue_slots[14].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2]
connect issue_slots[14].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3]
connect issue_slots[14].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4]
connect issue_slots[14].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5]
connect issue_slots[14].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6]
connect issue_slots[14].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7]
connect issue_slots[14].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8]
connect issue_slots[14].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9]
connect issue_slots[14].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0]
connect issue_slots[14].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1]
connect issue_slots[14].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2]
connect issue_slots[14].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3]
connect issue_slots[14].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc
connect issue_slots[14].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc
connect issue_slots[14].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst
connect issue_slots[14].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst
connect issue_slots[14].wakeup_ports[2].valid, io.wakeup_ports[2].valid
connect issue_slots[14].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy
connect issue_slots[14].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask
connect issue_slots[14].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable
connect issue_slots[14].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc
connect issue_slots[14].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc
connect issue_slots[14].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if
connect issue_slots[14].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if
connect issue_slots[14].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if
connect issue_slots[14].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if
connect issue_slots[14].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if
connect issue_slots[14].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ
connect issue_slots[14].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm
connect issue_slots[14].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val
connect issue_slots[14].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op
connect issue_slots[14].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw
connect issue_slots[14].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en
connect issue_slots[14].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype
connect issue_slots[14].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype
connect issue_slots[14].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype
connect issue_slots[14].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3
connect issue_slots[14].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2
connect issue_slots[14].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1
connect issue_slots[14].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst
connect issue_slots[14].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1
connect issue_slots[14].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd
connect issue_slots[14].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit
connect issue_slots[14].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique
connect issue_slots[14].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq
connect issue_slots[14].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq
connect issue_slots[14].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed
connect issue_slots[14].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size
connect issue_slots[14].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd
connect issue_slots[14].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause
connect issue_slots[14].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception
connect issue_slots[14].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst
connect issue_slots[14].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy
connect issue_slots[14].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy
connect issue_slots[14].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy
connect issue_slots[14].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy
connect issue_slots[14].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred
connect issue_slots[14].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3
connect issue_slots[14].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2
connect issue_slots[14].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1
connect issue_slots[14].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst
connect issue_slots[14].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx
connect issue_slots[14].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx
connect issue_slots[14].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx
connect issue_slots[14].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx
connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec
connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags
connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt
connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div
connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma
connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe
connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint
connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint
connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23
connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12
connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3
connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2
connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1
connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen
connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst
connect issue_slots[14].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel
connect issue_slots[14].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel
connect issue_slots[14].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed
connect issue_slots[14].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm
connect issue_slots[14].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel
connect issue_slots[14].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename
connect issue_slots[14].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken
connect issue_slots[14].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob
connect issue_slots[14].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst
connect issue_slots[14].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx
connect issue_slots[14].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov
connect issue_slots[14].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc
connect issue_slots[14].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc
connect issue_slots[14].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret
connect issue_slots[14].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo
connect issue_slots[14].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence
connect issue_slots[14].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei
connect issue_slots[14].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence
connect issue_slots[14].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb
connect issue_slots[14].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type
connect issue_slots[14].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag
connect issue_slots[14].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask
connect issue_slots[14].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel
connect issue_slots[14].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint
connect issue_slots[14].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint
connect issue_slots[14].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint
connect issue_slots[14].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child
connect issue_slots[14].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child
connect issue_slots[14].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen
connect issue_slots[14].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen
connect issue_slots[14].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued
connect issue_slots[14].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0]
connect issue_slots[14].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1]
connect issue_slots[14].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2]
connect issue_slots[14].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3]
connect issue_slots[14].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4]
connect issue_slots[14].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5]
connect issue_slots[14].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6]
connect issue_slots[14].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7]
connect issue_slots[14].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8]
connect issue_slots[14].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9]
connect issue_slots[14].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0]
connect issue_slots[14].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1]
connect issue_slots[14].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2]
connect issue_slots[14].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3]
connect issue_slots[14].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc
connect issue_slots[14].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc
connect issue_slots[14].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst
connect issue_slots[14].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst
connect issue_slots[14].wakeup_ports[3].valid, io.wakeup_ports[3].valid
connect issue_slots[14].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[14].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[14].child_rebusys, io.child_rebusys
connect issue_slots[14].squash_grant, io.squash_grant
connect issue_slots[14].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[14].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[14].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[14].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[14].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[14].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[14].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[14].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[14].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[14].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[14].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[14].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[14].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[14].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ
connect issue_slots[14].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm
connect issue_slots[14].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[14].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op
connect issue_slots[14].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw
connect issue_slots[14].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[14].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[14].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[14].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[14].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[14].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[14].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[14].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[14].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[14].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd
connect issue_slots[14].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[14].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[14].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[14].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[14].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[14].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[14].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[14].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[14].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[14].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[14].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[14].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[14].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[14].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[14].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[14].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[14].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[14].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[14].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[14].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[14].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[14].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[14].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[14].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec
connect issue_slots[14].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags
connect issue_slots[14].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt
connect issue_slots[14].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div
connect issue_slots[14].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma
connect issue_slots[14].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe
connect issue_slots[14].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint
connect issue_slots[14].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint
connect issue_slots[14].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut
connect issue_slots[14].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn
connect issue_slots[14].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23
connect issue_slots[14].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12
connect issue_slots[14].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3
connect issue_slots[14].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2
connect issue_slots[14].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1
connect issue_slots[14].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen
connect issue_slots[14].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst
connect issue_slots[14].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel
connect issue_slots[14].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel
connect issue_slots[14].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[14].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm
connect issue_slots[14].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel
connect issue_slots[14].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename
connect issue_slots[14].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[14].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[14].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[14].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[14].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov
connect issue_slots[14].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc
connect issue_slots[14].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[14].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret
connect issue_slots[14].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[14].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence
connect issue_slots[14].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[14].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[14].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[14].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type
connect issue_slots[14].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[14].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[14].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel
connect issue_slots[14].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint
connect issue_slots[14].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint
connect issue_slots[14].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint
connect issue_slots[14].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child
connect issue_slots[14].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child
connect issue_slots[14].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen
connect issue_slots[14].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen
connect issue_slots[14].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued
connect issue_slots[14].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0]
connect issue_slots[14].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1]
connect issue_slots[14].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2]
connect issue_slots[14].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3]
connect issue_slots[14].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4]
connect issue_slots[14].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5]
connect issue_slots[14].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6]
connect issue_slots[14].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7]
connect issue_slots[14].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8]
connect issue_slots[14].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9]
connect issue_slots[14].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0]
connect issue_slots[14].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1]
connect issue_slots[14].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2]
connect issue_slots[14].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3]
connect issue_slots[14].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[14].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[14].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[14].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[14].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[14].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[14].kill, io.flush_pipeline
connect issue_slots[15].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy
connect issue_slots[15].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask
connect issue_slots[15].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable
connect issue_slots[15].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc
connect issue_slots[15].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc
connect issue_slots[15].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if
connect issue_slots[15].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if
connect issue_slots[15].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if
connect issue_slots[15].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if
connect issue_slots[15].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if
connect issue_slots[15].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ
connect issue_slots[15].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm
connect issue_slots[15].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val
connect issue_slots[15].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op
connect issue_slots[15].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw
connect issue_slots[15].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en
connect issue_slots[15].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype
connect issue_slots[15].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype
connect issue_slots[15].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype
connect issue_slots[15].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3
connect issue_slots[15].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2
connect issue_slots[15].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1
connect issue_slots[15].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst
connect issue_slots[15].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1
connect issue_slots[15].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd
connect issue_slots[15].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit
connect issue_slots[15].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique
connect issue_slots[15].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq
connect issue_slots[15].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq
connect issue_slots[15].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed
connect issue_slots[15].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size
connect issue_slots[15].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd
connect issue_slots[15].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause
connect issue_slots[15].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception
connect issue_slots[15].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst
connect issue_slots[15].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy
connect issue_slots[15].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy
connect issue_slots[15].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy
connect issue_slots[15].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy
connect issue_slots[15].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred
connect issue_slots[15].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3
connect issue_slots[15].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2
connect issue_slots[15].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1
connect issue_slots[15].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst
connect issue_slots[15].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx
connect issue_slots[15].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx
connect issue_slots[15].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx
connect issue_slots[15].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx
connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec
connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags
connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt
connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div
connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma
connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe
connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint
connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint
connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23
connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12
connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3
connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2
connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1
connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen
connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst
connect issue_slots[15].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel
connect issue_slots[15].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel
connect issue_slots[15].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed
connect issue_slots[15].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm
connect issue_slots[15].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel
connect issue_slots[15].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename
connect issue_slots[15].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken
connect issue_slots[15].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob
connect issue_slots[15].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst
connect issue_slots[15].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx
connect issue_slots[15].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov
connect issue_slots[15].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc
connect issue_slots[15].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc
connect issue_slots[15].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret
connect issue_slots[15].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo
connect issue_slots[15].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence
connect issue_slots[15].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei
connect issue_slots[15].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence
connect issue_slots[15].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb
connect issue_slots[15].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type
connect issue_slots[15].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag
connect issue_slots[15].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask
connect issue_slots[15].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel
connect issue_slots[15].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint
connect issue_slots[15].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint
connect issue_slots[15].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint
connect issue_slots[15].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child
connect issue_slots[15].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child
connect issue_slots[15].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen
connect issue_slots[15].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen
connect issue_slots[15].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued
connect issue_slots[15].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0]
connect issue_slots[15].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1]
connect issue_slots[15].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2]
connect issue_slots[15].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3]
connect issue_slots[15].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4]
connect issue_slots[15].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5]
connect issue_slots[15].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6]
connect issue_slots[15].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7]
connect issue_slots[15].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8]
connect issue_slots[15].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9]
connect issue_slots[15].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0]
connect issue_slots[15].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1]
connect issue_slots[15].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2]
connect issue_slots[15].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3]
connect issue_slots[15].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc
connect issue_slots[15].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc
connect issue_slots[15].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst
connect issue_slots[15].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst
connect issue_slots[15].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[15].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy
connect issue_slots[15].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask
connect issue_slots[15].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable
connect issue_slots[15].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc
connect issue_slots[15].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc
connect issue_slots[15].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if
connect issue_slots[15].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if
connect issue_slots[15].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if
connect issue_slots[15].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if
connect issue_slots[15].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if
connect issue_slots[15].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ
connect issue_slots[15].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm
connect issue_slots[15].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val
connect issue_slots[15].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op
connect issue_slots[15].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw
connect issue_slots[15].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en
connect issue_slots[15].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype
connect issue_slots[15].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype
connect issue_slots[15].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype
connect issue_slots[15].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3
connect issue_slots[15].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2
connect issue_slots[15].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1
connect issue_slots[15].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst
connect issue_slots[15].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1
connect issue_slots[15].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd
connect issue_slots[15].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit
connect issue_slots[15].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique
connect issue_slots[15].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq
connect issue_slots[15].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq
connect issue_slots[15].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed
connect issue_slots[15].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size
connect issue_slots[15].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd
connect issue_slots[15].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause
connect issue_slots[15].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception
connect issue_slots[15].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst
connect issue_slots[15].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy
connect issue_slots[15].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy
connect issue_slots[15].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy
connect issue_slots[15].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy
connect issue_slots[15].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred
connect issue_slots[15].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3
connect issue_slots[15].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2
connect issue_slots[15].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1
connect issue_slots[15].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst
connect issue_slots[15].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx
connect issue_slots[15].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx
connect issue_slots[15].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx
connect issue_slots[15].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx
connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec
connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags
connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt
connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div
connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma
connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe
connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint
connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint
connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23
connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12
connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3
connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2
connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1
connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen
connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst
connect issue_slots[15].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel
connect issue_slots[15].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel
connect issue_slots[15].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed
connect issue_slots[15].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm
connect issue_slots[15].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel
connect issue_slots[15].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename
connect issue_slots[15].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken
connect issue_slots[15].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob
connect issue_slots[15].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst
connect issue_slots[15].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx
connect issue_slots[15].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov
connect issue_slots[15].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc
connect issue_slots[15].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc
connect issue_slots[15].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret
connect issue_slots[15].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo
connect issue_slots[15].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence
connect issue_slots[15].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei
connect issue_slots[15].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence
connect issue_slots[15].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb
connect issue_slots[15].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type
connect issue_slots[15].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag
connect issue_slots[15].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask
connect issue_slots[15].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel
connect issue_slots[15].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint
connect issue_slots[15].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint
connect issue_slots[15].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint
connect issue_slots[15].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child
connect issue_slots[15].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child
connect issue_slots[15].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen
connect issue_slots[15].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen
connect issue_slots[15].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued
connect issue_slots[15].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0]
connect issue_slots[15].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1]
connect issue_slots[15].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2]
connect issue_slots[15].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3]
connect issue_slots[15].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4]
connect issue_slots[15].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5]
connect issue_slots[15].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6]
connect issue_slots[15].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7]
connect issue_slots[15].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8]
connect issue_slots[15].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9]
connect issue_slots[15].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0]
connect issue_slots[15].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1]
connect issue_slots[15].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2]
connect issue_slots[15].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3]
connect issue_slots[15].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc
connect issue_slots[15].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc
connect issue_slots[15].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst
connect issue_slots[15].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst
connect issue_slots[15].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[15].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy
connect issue_slots[15].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask
connect issue_slots[15].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable
connect issue_slots[15].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc
connect issue_slots[15].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc
connect issue_slots[15].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if
connect issue_slots[15].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if
connect issue_slots[15].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if
connect issue_slots[15].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if
connect issue_slots[15].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if
connect issue_slots[15].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ
connect issue_slots[15].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm
connect issue_slots[15].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val
connect issue_slots[15].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op
connect issue_slots[15].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw
connect issue_slots[15].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en
connect issue_slots[15].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype
connect issue_slots[15].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype
connect issue_slots[15].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype
connect issue_slots[15].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3
connect issue_slots[15].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2
connect issue_slots[15].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1
connect issue_slots[15].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst
connect issue_slots[15].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1
connect issue_slots[15].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd
connect issue_slots[15].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit
connect issue_slots[15].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique
connect issue_slots[15].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq
connect issue_slots[15].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq
connect issue_slots[15].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed
connect issue_slots[15].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size
connect issue_slots[15].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd
connect issue_slots[15].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause
connect issue_slots[15].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception
connect issue_slots[15].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst
connect issue_slots[15].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy
connect issue_slots[15].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy
connect issue_slots[15].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy
connect issue_slots[15].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy
connect issue_slots[15].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred
connect issue_slots[15].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3
connect issue_slots[15].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2
connect issue_slots[15].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1
connect issue_slots[15].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst
connect issue_slots[15].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx
connect issue_slots[15].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx
connect issue_slots[15].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx
connect issue_slots[15].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx
connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec
connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags
connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt
connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div
connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma
connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe
connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint
connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint
connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23
connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12
connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3
connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2
connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1
connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen
connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst
connect issue_slots[15].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel
connect issue_slots[15].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel
connect issue_slots[15].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed
connect issue_slots[15].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm
connect issue_slots[15].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel
connect issue_slots[15].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename
connect issue_slots[15].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken
connect issue_slots[15].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob
connect issue_slots[15].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst
connect issue_slots[15].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx
connect issue_slots[15].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov
connect issue_slots[15].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc
connect issue_slots[15].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc
connect issue_slots[15].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret
connect issue_slots[15].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo
connect issue_slots[15].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence
connect issue_slots[15].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei
connect issue_slots[15].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence
connect issue_slots[15].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb
connect issue_slots[15].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type
connect issue_slots[15].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag
connect issue_slots[15].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask
connect issue_slots[15].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel
connect issue_slots[15].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint
connect issue_slots[15].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint
connect issue_slots[15].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint
connect issue_slots[15].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child
connect issue_slots[15].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child
connect issue_slots[15].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen
connect issue_slots[15].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen
connect issue_slots[15].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued
connect issue_slots[15].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0]
connect issue_slots[15].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1]
connect issue_slots[15].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2]
connect issue_slots[15].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3]
connect issue_slots[15].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4]
connect issue_slots[15].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5]
connect issue_slots[15].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6]
connect issue_slots[15].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7]
connect issue_slots[15].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8]
connect issue_slots[15].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9]
connect issue_slots[15].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0]
connect issue_slots[15].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1]
connect issue_slots[15].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2]
connect issue_slots[15].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3]
connect issue_slots[15].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc
connect issue_slots[15].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc
connect issue_slots[15].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst
connect issue_slots[15].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst
connect issue_slots[15].wakeup_ports[2].valid, io.wakeup_ports[2].valid
connect issue_slots[15].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy
connect issue_slots[15].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask
connect issue_slots[15].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable
connect issue_slots[15].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc
connect issue_slots[15].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc
connect issue_slots[15].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if
connect issue_slots[15].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if
connect issue_slots[15].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if
connect issue_slots[15].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if
connect issue_slots[15].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if
connect issue_slots[15].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ
connect issue_slots[15].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm
connect issue_slots[15].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val
connect issue_slots[15].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op
connect issue_slots[15].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw
connect issue_slots[15].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en
connect issue_slots[15].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype
connect issue_slots[15].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype
connect issue_slots[15].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype
connect issue_slots[15].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3
connect issue_slots[15].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2
connect issue_slots[15].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1
connect issue_slots[15].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst
connect issue_slots[15].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1
connect issue_slots[15].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd
connect issue_slots[15].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit
connect issue_slots[15].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique
connect issue_slots[15].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq
connect issue_slots[15].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq
connect issue_slots[15].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed
connect issue_slots[15].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size
connect issue_slots[15].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd
connect issue_slots[15].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause
connect issue_slots[15].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception
connect issue_slots[15].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst
connect issue_slots[15].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy
connect issue_slots[15].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy
connect issue_slots[15].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy
connect issue_slots[15].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy
connect issue_slots[15].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred
connect issue_slots[15].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3
connect issue_slots[15].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2
connect issue_slots[15].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1
connect issue_slots[15].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst
connect issue_slots[15].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx
connect issue_slots[15].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx
connect issue_slots[15].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx
connect issue_slots[15].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx
connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec
connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags
connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt
connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div
connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma
connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe
connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint
connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint
connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23
connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12
connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3
connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2
connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1
connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen
connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst
connect issue_slots[15].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel
connect issue_slots[15].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel
connect issue_slots[15].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed
connect issue_slots[15].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm
connect issue_slots[15].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel
connect issue_slots[15].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename
connect issue_slots[15].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken
connect issue_slots[15].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob
connect issue_slots[15].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst
connect issue_slots[15].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx
connect issue_slots[15].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov
connect issue_slots[15].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc
connect issue_slots[15].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc
connect issue_slots[15].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret
connect issue_slots[15].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo
connect issue_slots[15].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence
connect issue_slots[15].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei
connect issue_slots[15].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence
connect issue_slots[15].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb
connect issue_slots[15].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type
connect issue_slots[15].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag
connect issue_slots[15].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask
connect issue_slots[15].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel
connect issue_slots[15].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint
connect issue_slots[15].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint
connect issue_slots[15].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint
connect issue_slots[15].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child
connect issue_slots[15].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child
connect issue_slots[15].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen
connect issue_slots[15].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen
connect issue_slots[15].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued
connect issue_slots[15].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0]
connect issue_slots[15].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1]
connect issue_slots[15].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2]
connect issue_slots[15].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3]
connect issue_slots[15].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4]
connect issue_slots[15].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5]
connect issue_slots[15].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6]
connect issue_slots[15].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7]
connect issue_slots[15].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8]
connect issue_slots[15].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9]
connect issue_slots[15].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0]
connect issue_slots[15].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1]
connect issue_slots[15].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2]
connect issue_slots[15].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3]
connect issue_slots[15].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc
connect issue_slots[15].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc
connect issue_slots[15].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst
connect issue_slots[15].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst
connect issue_slots[15].wakeup_ports[3].valid, io.wakeup_ports[3].valid
connect issue_slots[15].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[15].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[15].child_rebusys, io.child_rebusys
connect issue_slots[15].squash_grant, io.squash_grant
connect issue_slots[15].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[15].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[15].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[15].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[15].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[15].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[15].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[15].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[15].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[15].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[15].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[15].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[15].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[15].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ
connect issue_slots[15].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm
connect issue_slots[15].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[15].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op
connect issue_slots[15].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw
connect issue_slots[15].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[15].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[15].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[15].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[15].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[15].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[15].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[15].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[15].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[15].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd
connect issue_slots[15].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[15].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[15].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[15].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[15].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[15].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[15].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[15].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[15].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[15].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[15].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[15].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[15].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[15].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[15].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[15].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[15].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[15].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[15].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[15].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[15].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[15].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[15].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[15].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec
connect issue_slots[15].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags
connect issue_slots[15].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt
connect issue_slots[15].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div
connect issue_slots[15].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma
connect issue_slots[15].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe
connect issue_slots[15].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint
connect issue_slots[15].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint
connect issue_slots[15].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut
connect issue_slots[15].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn
connect issue_slots[15].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23
connect issue_slots[15].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12
connect issue_slots[15].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3
connect issue_slots[15].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2
connect issue_slots[15].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1
connect issue_slots[15].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen
connect issue_slots[15].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst
connect issue_slots[15].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel
connect issue_slots[15].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel
connect issue_slots[15].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[15].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm
connect issue_slots[15].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel
connect issue_slots[15].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename
connect issue_slots[15].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[15].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[15].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[15].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[15].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov
connect issue_slots[15].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc
connect issue_slots[15].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[15].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret
connect issue_slots[15].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[15].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence
connect issue_slots[15].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[15].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[15].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[15].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type
connect issue_slots[15].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[15].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[15].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel
connect issue_slots[15].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint
connect issue_slots[15].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint
connect issue_slots[15].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint
connect issue_slots[15].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child
connect issue_slots[15].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child
connect issue_slots[15].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen
connect issue_slots[15].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen
connect issue_slots[15].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued
connect issue_slots[15].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0]
connect issue_slots[15].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1]
connect issue_slots[15].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2]
connect issue_slots[15].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3]
connect issue_slots[15].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4]
connect issue_slots[15].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5]
connect issue_slots[15].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6]
connect issue_slots[15].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7]
connect issue_slots[15].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8]
connect issue_slots[15].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9]
connect issue_slots[15].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0]
connect issue_slots[15].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1]
connect issue_slots[15].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2]
connect issue_slots[15].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3]
connect issue_slots[15].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[15].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[15].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[15].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[15].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[15].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[15].kill, io.flush_pipeline
connect issue_slots[16].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy
connect issue_slots[16].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask
connect issue_slots[16].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable
connect issue_slots[16].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc
connect issue_slots[16].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc
connect issue_slots[16].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if
connect issue_slots[16].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if
connect issue_slots[16].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if
connect issue_slots[16].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if
connect issue_slots[16].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if
connect issue_slots[16].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ
connect issue_slots[16].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm
connect issue_slots[16].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val
connect issue_slots[16].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op
connect issue_slots[16].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw
connect issue_slots[16].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en
connect issue_slots[16].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype
connect issue_slots[16].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype
connect issue_slots[16].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype
connect issue_slots[16].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3
connect issue_slots[16].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2
connect issue_slots[16].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1
connect issue_slots[16].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst
connect issue_slots[16].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1
connect issue_slots[16].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd
connect issue_slots[16].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit
connect issue_slots[16].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique
connect issue_slots[16].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq
connect issue_slots[16].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq
connect issue_slots[16].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed
connect issue_slots[16].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size
connect issue_slots[16].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd
connect issue_slots[16].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause
connect issue_slots[16].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception
connect issue_slots[16].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst
connect issue_slots[16].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy
connect issue_slots[16].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy
connect issue_slots[16].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy
connect issue_slots[16].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy
connect issue_slots[16].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred
connect issue_slots[16].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3
connect issue_slots[16].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2
connect issue_slots[16].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1
connect issue_slots[16].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst
connect issue_slots[16].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx
connect issue_slots[16].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx
connect issue_slots[16].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx
connect issue_slots[16].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx
connect issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec
connect issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags
connect issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt
connect issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div
connect issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma
connect issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe
connect issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint
connect issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint
connect issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23
connect issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12
connect issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3
connect issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2
connect issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1
connect issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen
connect issue_slots[16].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst
connect issue_slots[16].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel
connect issue_slots[16].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel
connect issue_slots[16].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed
connect issue_slots[16].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm
connect issue_slots[16].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel
connect issue_slots[16].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename
connect issue_slots[16].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken
connect issue_slots[16].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob
connect issue_slots[16].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst
connect issue_slots[16].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx
connect issue_slots[16].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov
connect issue_slots[16].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc
connect issue_slots[16].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc
connect issue_slots[16].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret
connect issue_slots[16].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo
connect issue_slots[16].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence
connect issue_slots[16].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei
connect issue_slots[16].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence
connect issue_slots[16].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb
connect issue_slots[16].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type
connect issue_slots[16].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag
connect issue_slots[16].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask
connect issue_slots[16].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel
connect issue_slots[16].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint
connect issue_slots[16].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint
connect issue_slots[16].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint
connect issue_slots[16].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child
connect issue_slots[16].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child
connect issue_slots[16].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen
connect issue_slots[16].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen
connect issue_slots[16].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued
connect issue_slots[16].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0]
connect issue_slots[16].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1]
connect issue_slots[16].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2]
connect issue_slots[16].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3]
connect issue_slots[16].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4]
connect issue_slots[16].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5]
connect issue_slots[16].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6]
connect issue_slots[16].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7]
connect issue_slots[16].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8]
connect issue_slots[16].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9]
connect issue_slots[16].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0]
connect issue_slots[16].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1]
connect issue_slots[16].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2]
connect issue_slots[16].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3]
connect issue_slots[16].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc
connect issue_slots[16].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc
connect issue_slots[16].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst
connect issue_slots[16].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst
connect issue_slots[16].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[16].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy
connect issue_slots[16].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask
connect issue_slots[16].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable
connect issue_slots[16].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc
connect issue_slots[16].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc
connect issue_slots[16].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if
connect issue_slots[16].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if
connect issue_slots[16].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if
connect issue_slots[16].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if
connect issue_slots[16].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if
connect issue_slots[16].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ
connect issue_slots[16].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm
connect issue_slots[16].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val
connect issue_slots[16].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op
connect issue_slots[16].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw
connect issue_slots[16].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en
connect issue_slots[16].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype
connect issue_slots[16].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype
connect issue_slots[16].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype
connect issue_slots[16].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3
connect issue_slots[16].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2
connect issue_slots[16].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1
connect issue_slots[16].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst
connect issue_slots[16].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1
connect issue_slots[16].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd
connect issue_slots[16].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit
connect issue_slots[16].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique
connect issue_slots[16].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq
connect issue_slots[16].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq
connect issue_slots[16].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed
connect issue_slots[16].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size
connect issue_slots[16].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd
connect issue_slots[16].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause
connect issue_slots[16].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception
connect issue_slots[16].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst
connect issue_slots[16].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy
connect issue_slots[16].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy
connect issue_slots[16].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy
connect issue_slots[16].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy
connect issue_slots[16].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred
connect issue_slots[16].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3
connect issue_slots[16].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2
connect issue_slots[16].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1
connect issue_slots[16].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst
connect issue_slots[16].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx
connect issue_slots[16].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx
connect issue_slots[16].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx
connect issue_slots[16].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx
connect issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec
connect issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags
connect issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt
connect issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div
connect issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma
connect issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe
connect issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint
connect issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint
connect issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23
connect issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12
connect issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3
connect issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2
connect issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1
connect issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen
connect issue_slots[16].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst
connect issue_slots[16].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel
connect issue_slots[16].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel
connect issue_slots[16].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed
connect issue_slots[16].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm
connect issue_slots[16].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel
connect issue_slots[16].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename
connect issue_slots[16].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken
connect issue_slots[16].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob
connect issue_slots[16].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst
connect issue_slots[16].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx
connect issue_slots[16].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov
connect issue_slots[16].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc
connect issue_slots[16].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc
connect issue_slots[16].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret
connect issue_slots[16].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo
connect issue_slots[16].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence
connect issue_slots[16].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei
connect issue_slots[16].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence
connect issue_slots[16].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb
connect issue_slots[16].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type
connect issue_slots[16].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag
connect issue_slots[16].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask
connect issue_slots[16].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel
connect issue_slots[16].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint
connect issue_slots[16].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint
connect issue_slots[16].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint
connect issue_slots[16].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child
connect issue_slots[16].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child
connect issue_slots[16].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen
connect issue_slots[16].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen
connect issue_slots[16].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued
connect issue_slots[16].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0]
connect issue_slots[16].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1]
connect issue_slots[16].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2]
connect issue_slots[16].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3]
connect issue_slots[16].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4]
connect issue_slots[16].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5]
connect issue_slots[16].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6]
connect issue_slots[16].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7]
connect issue_slots[16].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8]
connect issue_slots[16].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9]
connect issue_slots[16].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0]
connect issue_slots[16].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1]
connect issue_slots[16].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2]
connect issue_slots[16].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3]
connect issue_slots[16].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc
connect issue_slots[16].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc
connect issue_slots[16].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst
connect issue_slots[16].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst
connect issue_slots[16].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[16].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy
connect issue_slots[16].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask
connect issue_slots[16].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable
connect issue_slots[16].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc
connect issue_slots[16].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc
connect issue_slots[16].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if
connect issue_slots[16].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if
connect issue_slots[16].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if
connect issue_slots[16].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if
connect issue_slots[16].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if
connect issue_slots[16].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ
connect issue_slots[16].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm
connect issue_slots[16].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val
connect issue_slots[16].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op
connect issue_slots[16].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw
connect issue_slots[16].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en
connect issue_slots[16].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype
connect issue_slots[16].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype
connect issue_slots[16].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype
connect issue_slots[16].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3
connect issue_slots[16].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2
connect issue_slots[16].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1
connect issue_slots[16].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst
connect issue_slots[16].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1
connect issue_slots[16].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd
connect issue_slots[16].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit
connect issue_slots[16].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique
connect issue_slots[16].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq
connect issue_slots[16].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq
connect issue_slots[16].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed
connect issue_slots[16].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size
connect issue_slots[16].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd
connect issue_slots[16].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause
connect issue_slots[16].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception
connect issue_slots[16].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst
connect issue_slots[16].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy
connect issue_slots[16].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy
connect issue_slots[16].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy
connect issue_slots[16].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy
connect issue_slots[16].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred
connect issue_slots[16].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3
connect issue_slots[16].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2
connect issue_slots[16].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1
connect issue_slots[16].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst
connect issue_slots[16].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx
connect issue_slots[16].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx
connect issue_slots[16].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx
connect issue_slots[16].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx
connect issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec
connect issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags
connect issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt
connect issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div
connect issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma
connect issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe
connect issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint
connect issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint
connect issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23
connect issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12
connect issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3
connect issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2
connect issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1
connect issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen
connect issue_slots[16].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst
connect issue_slots[16].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel
connect issue_slots[16].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel
connect issue_slots[16].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed
connect issue_slots[16].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm
connect issue_slots[16].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel
connect issue_slots[16].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename
connect issue_slots[16].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken
connect issue_slots[16].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob
connect issue_slots[16].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst
connect issue_slots[16].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx
connect issue_slots[16].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov
connect issue_slots[16].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc
connect issue_slots[16].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc
connect issue_slots[16].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret
connect issue_slots[16].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo
connect issue_slots[16].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence
connect issue_slots[16].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei
connect issue_slots[16].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence
connect issue_slots[16].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb
connect issue_slots[16].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type
connect issue_slots[16].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag
connect issue_slots[16].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask
connect issue_slots[16].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel
connect issue_slots[16].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint
connect issue_slots[16].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint
connect issue_slots[16].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint
connect issue_slots[16].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child
connect issue_slots[16].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child
connect issue_slots[16].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen
connect issue_slots[16].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen
connect issue_slots[16].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued
connect issue_slots[16].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0]
connect issue_slots[16].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1]
connect issue_slots[16].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2]
connect issue_slots[16].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3]
connect issue_slots[16].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4]
connect issue_slots[16].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5]
connect issue_slots[16].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6]
connect issue_slots[16].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7]
connect issue_slots[16].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8]
connect issue_slots[16].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9]
connect issue_slots[16].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0]
connect issue_slots[16].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1]
connect issue_slots[16].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2]
connect issue_slots[16].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3]
connect issue_slots[16].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc
connect issue_slots[16].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc
connect issue_slots[16].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst
connect issue_slots[16].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst
connect issue_slots[16].wakeup_ports[2].valid, io.wakeup_ports[2].valid
connect issue_slots[16].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy
connect issue_slots[16].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask
connect issue_slots[16].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable
connect issue_slots[16].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc
connect issue_slots[16].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc
connect issue_slots[16].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if
connect issue_slots[16].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if
connect issue_slots[16].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if
connect issue_slots[16].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if
connect issue_slots[16].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if
connect issue_slots[16].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ
connect issue_slots[16].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm
connect issue_slots[16].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val
connect issue_slots[16].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op
connect issue_slots[16].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw
connect issue_slots[16].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en
connect issue_slots[16].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype
connect issue_slots[16].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype
connect issue_slots[16].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype
connect issue_slots[16].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3
connect issue_slots[16].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2
connect issue_slots[16].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1
connect issue_slots[16].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst
connect issue_slots[16].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1
connect issue_slots[16].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd
connect issue_slots[16].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit
connect issue_slots[16].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique
connect issue_slots[16].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq
connect issue_slots[16].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq
connect issue_slots[16].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed
connect issue_slots[16].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size
connect issue_slots[16].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd
connect issue_slots[16].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause
connect issue_slots[16].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception
connect issue_slots[16].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst
connect issue_slots[16].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy
connect issue_slots[16].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy
connect issue_slots[16].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy
connect issue_slots[16].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy
connect issue_slots[16].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred
connect issue_slots[16].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3
connect issue_slots[16].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2
connect issue_slots[16].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1
connect issue_slots[16].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst
connect issue_slots[16].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx
connect issue_slots[16].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx
connect issue_slots[16].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx
connect issue_slots[16].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx
connect issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec
connect issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags
connect issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt
connect issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div
connect issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma
connect issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe
connect issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint
connect issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint
connect issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23
connect issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12
connect issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3
connect issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2
connect issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1
connect issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen
connect issue_slots[16].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst
connect issue_slots[16].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel
connect issue_slots[16].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel
connect issue_slots[16].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed
connect issue_slots[16].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm
connect issue_slots[16].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel
connect issue_slots[16].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename
connect issue_slots[16].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken
connect issue_slots[16].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob
connect issue_slots[16].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst
connect issue_slots[16].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx
connect issue_slots[16].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov
connect issue_slots[16].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc
connect issue_slots[16].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc
connect issue_slots[16].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret
connect issue_slots[16].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo
connect issue_slots[16].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence
connect issue_slots[16].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei
connect issue_slots[16].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence
connect issue_slots[16].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb
connect issue_slots[16].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type
connect issue_slots[16].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag
connect issue_slots[16].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask
connect issue_slots[16].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel
connect issue_slots[16].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint
connect issue_slots[16].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint
connect issue_slots[16].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint
connect issue_slots[16].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child
connect issue_slots[16].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child
connect issue_slots[16].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen
connect issue_slots[16].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen
connect issue_slots[16].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued
connect issue_slots[16].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0]
connect issue_slots[16].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1]
connect issue_slots[16].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2]
connect issue_slots[16].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3]
connect issue_slots[16].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4]
connect issue_slots[16].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5]
connect issue_slots[16].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6]
connect issue_slots[16].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7]
connect issue_slots[16].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8]
connect issue_slots[16].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9]
connect issue_slots[16].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0]
connect issue_slots[16].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1]
connect issue_slots[16].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2]
connect issue_slots[16].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3]
connect issue_slots[16].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc
connect issue_slots[16].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc
connect issue_slots[16].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst
connect issue_slots[16].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst
connect issue_slots[16].wakeup_ports[3].valid, io.wakeup_ports[3].valid
connect issue_slots[16].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[16].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[16].child_rebusys, io.child_rebusys
connect issue_slots[16].squash_grant, io.squash_grant
connect issue_slots[16].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[16].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[16].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[16].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[16].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[16].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[16].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[16].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[16].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[16].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[16].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[16].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[16].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[16].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ
connect issue_slots[16].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm
connect issue_slots[16].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[16].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op
connect issue_slots[16].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw
connect issue_slots[16].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[16].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[16].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[16].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[16].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[16].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[16].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[16].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[16].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[16].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd
connect issue_slots[16].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[16].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[16].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[16].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[16].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[16].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[16].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[16].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[16].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[16].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[16].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[16].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[16].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[16].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[16].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[16].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[16].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[16].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[16].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[16].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[16].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[16].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[16].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[16].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec
connect issue_slots[16].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags
connect issue_slots[16].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt
connect issue_slots[16].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div
connect issue_slots[16].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma
connect issue_slots[16].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe
connect issue_slots[16].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint
connect issue_slots[16].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint
connect issue_slots[16].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut
connect issue_slots[16].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn
connect issue_slots[16].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23
connect issue_slots[16].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12
connect issue_slots[16].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3
connect issue_slots[16].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2
connect issue_slots[16].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1
connect issue_slots[16].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen
connect issue_slots[16].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst
connect issue_slots[16].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel
connect issue_slots[16].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel
connect issue_slots[16].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[16].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm
connect issue_slots[16].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel
connect issue_slots[16].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename
connect issue_slots[16].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[16].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[16].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[16].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[16].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov
connect issue_slots[16].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc
connect issue_slots[16].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[16].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret
connect issue_slots[16].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[16].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence
connect issue_slots[16].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[16].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[16].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[16].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type
connect issue_slots[16].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[16].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[16].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel
connect issue_slots[16].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint
connect issue_slots[16].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint
connect issue_slots[16].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint
connect issue_slots[16].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child
connect issue_slots[16].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child
connect issue_slots[16].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen
connect issue_slots[16].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen
connect issue_slots[16].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued
connect issue_slots[16].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0]
connect issue_slots[16].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1]
connect issue_slots[16].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2]
connect issue_slots[16].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3]
connect issue_slots[16].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4]
connect issue_slots[16].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5]
connect issue_slots[16].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6]
connect issue_slots[16].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7]
connect issue_slots[16].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8]
connect issue_slots[16].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9]
connect issue_slots[16].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0]
connect issue_slots[16].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1]
connect issue_slots[16].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2]
connect issue_slots[16].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3]
connect issue_slots[16].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[16].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[16].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[16].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[16].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[16].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[16].kill, io.flush_pipeline
connect issue_slots[17].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy
connect issue_slots[17].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask
connect issue_slots[17].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable
connect issue_slots[17].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc
connect issue_slots[17].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc
connect issue_slots[17].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if
connect issue_slots[17].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if
connect issue_slots[17].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if
connect issue_slots[17].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if
connect issue_slots[17].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if
connect issue_slots[17].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ
connect issue_slots[17].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm
connect issue_slots[17].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val
connect issue_slots[17].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op
connect issue_slots[17].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw
connect issue_slots[17].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en
connect issue_slots[17].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype
connect issue_slots[17].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype
connect issue_slots[17].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype
connect issue_slots[17].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3
connect issue_slots[17].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2
connect issue_slots[17].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1
connect issue_slots[17].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst
connect issue_slots[17].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1
connect issue_slots[17].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd
connect issue_slots[17].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit
connect issue_slots[17].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique
connect issue_slots[17].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq
connect issue_slots[17].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq
connect issue_slots[17].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed
connect issue_slots[17].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size
connect issue_slots[17].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd
connect issue_slots[17].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause
connect issue_slots[17].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception
connect issue_slots[17].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst
connect issue_slots[17].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy
connect issue_slots[17].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy
connect issue_slots[17].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy
connect issue_slots[17].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy
connect issue_slots[17].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred
connect issue_slots[17].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3
connect issue_slots[17].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2
connect issue_slots[17].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1
connect issue_slots[17].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst
connect issue_slots[17].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx
connect issue_slots[17].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx
connect issue_slots[17].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx
connect issue_slots[17].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx
connect issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec
connect issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags
connect issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt
connect issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div
connect issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma
connect issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe
connect issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint
connect issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint
connect issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23
connect issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12
connect issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3
connect issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2
connect issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1
connect issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen
connect issue_slots[17].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst
connect issue_slots[17].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel
connect issue_slots[17].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel
connect issue_slots[17].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed
connect issue_slots[17].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm
connect issue_slots[17].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel
connect issue_slots[17].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename
connect issue_slots[17].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken
connect issue_slots[17].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob
connect issue_slots[17].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst
connect issue_slots[17].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx
connect issue_slots[17].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov
connect issue_slots[17].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc
connect issue_slots[17].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc
connect issue_slots[17].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret
connect issue_slots[17].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo
connect issue_slots[17].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence
connect issue_slots[17].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei
connect issue_slots[17].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence
connect issue_slots[17].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb
connect issue_slots[17].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type
connect issue_slots[17].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag
connect issue_slots[17].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask
connect issue_slots[17].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel
connect issue_slots[17].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint
connect issue_slots[17].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint
connect issue_slots[17].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint
connect issue_slots[17].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child
connect issue_slots[17].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child
connect issue_slots[17].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen
connect issue_slots[17].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen
connect issue_slots[17].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued
connect issue_slots[17].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0]
connect issue_slots[17].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1]
connect issue_slots[17].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2]
connect issue_slots[17].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3]
connect issue_slots[17].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4]
connect issue_slots[17].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5]
connect issue_slots[17].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6]
connect issue_slots[17].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7]
connect issue_slots[17].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8]
connect issue_slots[17].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9]
connect issue_slots[17].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0]
connect issue_slots[17].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1]
connect issue_slots[17].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2]
connect issue_slots[17].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3]
connect issue_slots[17].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc
connect issue_slots[17].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc
connect issue_slots[17].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst
connect issue_slots[17].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst
connect issue_slots[17].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[17].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy
connect issue_slots[17].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask
connect issue_slots[17].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable
connect issue_slots[17].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc
connect issue_slots[17].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc
connect issue_slots[17].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if
connect issue_slots[17].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if
connect issue_slots[17].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if
connect issue_slots[17].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if
connect issue_slots[17].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if
connect issue_slots[17].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ
connect issue_slots[17].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm
connect issue_slots[17].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val
connect issue_slots[17].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op
connect issue_slots[17].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw
connect issue_slots[17].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en
connect issue_slots[17].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype
connect issue_slots[17].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype
connect issue_slots[17].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype
connect issue_slots[17].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3
connect issue_slots[17].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2
connect issue_slots[17].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1
connect issue_slots[17].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst
connect issue_slots[17].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1
connect issue_slots[17].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd
connect issue_slots[17].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit
connect issue_slots[17].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique
connect issue_slots[17].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq
connect issue_slots[17].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq
connect issue_slots[17].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed
connect issue_slots[17].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size
connect issue_slots[17].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd
connect issue_slots[17].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause
connect issue_slots[17].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception
connect issue_slots[17].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst
connect issue_slots[17].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy
connect issue_slots[17].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy
connect issue_slots[17].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy
connect issue_slots[17].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy
connect issue_slots[17].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred
connect issue_slots[17].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3
connect issue_slots[17].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2
connect issue_slots[17].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1
connect issue_slots[17].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst
connect issue_slots[17].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx
connect issue_slots[17].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx
connect issue_slots[17].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx
connect issue_slots[17].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx
connect issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec
connect issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags
connect issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt
connect issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div
connect issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma
connect issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe
connect issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint
connect issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint
connect issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23
connect issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12
connect issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3
connect issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2
connect issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1
connect issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen
connect issue_slots[17].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst
connect issue_slots[17].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel
connect issue_slots[17].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel
connect issue_slots[17].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed
connect issue_slots[17].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm
connect issue_slots[17].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel
connect issue_slots[17].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename
connect issue_slots[17].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken
connect issue_slots[17].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob
connect issue_slots[17].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst
connect issue_slots[17].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx
connect issue_slots[17].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov
connect issue_slots[17].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc
connect issue_slots[17].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc
connect issue_slots[17].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret
connect issue_slots[17].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo
connect issue_slots[17].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence
connect issue_slots[17].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei
connect issue_slots[17].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence
connect issue_slots[17].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb
connect issue_slots[17].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type
connect issue_slots[17].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag
connect issue_slots[17].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask
connect issue_slots[17].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel
connect issue_slots[17].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint
connect issue_slots[17].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint
connect issue_slots[17].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint
connect issue_slots[17].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child
connect issue_slots[17].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child
connect issue_slots[17].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen
connect issue_slots[17].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen
connect issue_slots[17].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued
connect issue_slots[17].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0]
connect issue_slots[17].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1]
connect issue_slots[17].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2]
connect issue_slots[17].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3]
connect issue_slots[17].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4]
connect issue_slots[17].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5]
connect issue_slots[17].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6]
connect issue_slots[17].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7]
connect issue_slots[17].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8]
connect issue_slots[17].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9]
connect issue_slots[17].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0]
connect issue_slots[17].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1]
connect issue_slots[17].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2]
connect issue_slots[17].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3]
connect issue_slots[17].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc
connect issue_slots[17].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc
connect issue_slots[17].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst
connect issue_slots[17].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst
connect issue_slots[17].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[17].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy
connect issue_slots[17].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask
connect issue_slots[17].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable
connect issue_slots[17].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc
connect issue_slots[17].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc
connect issue_slots[17].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if
connect issue_slots[17].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if
connect issue_slots[17].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if
connect issue_slots[17].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if
connect issue_slots[17].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if
connect issue_slots[17].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ
connect issue_slots[17].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm
connect issue_slots[17].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val
connect issue_slots[17].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op
connect issue_slots[17].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw
connect issue_slots[17].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en
connect issue_slots[17].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype
connect issue_slots[17].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype
connect issue_slots[17].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype
connect issue_slots[17].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3
connect issue_slots[17].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2
connect issue_slots[17].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1
connect issue_slots[17].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst
connect issue_slots[17].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1
connect issue_slots[17].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd
connect issue_slots[17].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit
connect issue_slots[17].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique
connect issue_slots[17].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq
connect issue_slots[17].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq
connect issue_slots[17].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed
connect issue_slots[17].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size
connect issue_slots[17].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd
connect issue_slots[17].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause
connect issue_slots[17].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception
connect issue_slots[17].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst
connect issue_slots[17].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy
connect issue_slots[17].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy
connect issue_slots[17].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy
connect issue_slots[17].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy
connect issue_slots[17].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred
connect issue_slots[17].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3
connect issue_slots[17].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2
connect issue_slots[17].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1
connect issue_slots[17].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst
connect issue_slots[17].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx
connect issue_slots[17].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx
connect issue_slots[17].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx
connect issue_slots[17].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx
connect issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec
connect issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags
connect issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt
connect issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div
connect issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma
connect issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe
connect issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint
connect issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint
connect issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23
connect issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12
connect issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3
connect issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2
connect issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1
connect issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen
connect issue_slots[17].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst
connect issue_slots[17].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel
connect issue_slots[17].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel
connect issue_slots[17].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed
connect issue_slots[17].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm
connect issue_slots[17].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel
connect issue_slots[17].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename
connect issue_slots[17].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken
connect issue_slots[17].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob
connect issue_slots[17].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst
connect issue_slots[17].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx
connect issue_slots[17].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov
connect issue_slots[17].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc
connect issue_slots[17].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc
connect issue_slots[17].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret
connect issue_slots[17].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo
connect issue_slots[17].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence
connect issue_slots[17].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei
connect issue_slots[17].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence
connect issue_slots[17].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb
connect issue_slots[17].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type
connect issue_slots[17].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag
connect issue_slots[17].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask
connect issue_slots[17].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel
connect issue_slots[17].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint
connect issue_slots[17].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint
connect issue_slots[17].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint
connect issue_slots[17].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child
connect issue_slots[17].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child
connect issue_slots[17].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen
connect issue_slots[17].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen
connect issue_slots[17].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued
connect issue_slots[17].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0]
connect issue_slots[17].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1]
connect issue_slots[17].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2]
connect issue_slots[17].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3]
connect issue_slots[17].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4]
connect issue_slots[17].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5]
connect issue_slots[17].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6]
connect issue_slots[17].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7]
connect issue_slots[17].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8]
connect issue_slots[17].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9]
connect issue_slots[17].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0]
connect issue_slots[17].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1]
connect issue_slots[17].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2]
connect issue_slots[17].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3]
connect issue_slots[17].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc
connect issue_slots[17].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc
connect issue_slots[17].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst
connect issue_slots[17].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst
connect issue_slots[17].wakeup_ports[2].valid, io.wakeup_ports[2].valid
connect issue_slots[17].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy
connect issue_slots[17].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask
connect issue_slots[17].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable
connect issue_slots[17].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc
connect issue_slots[17].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc
connect issue_slots[17].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if
connect issue_slots[17].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if
connect issue_slots[17].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if
connect issue_slots[17].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if
connect issue_slots[17].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if
connect issue_slots[17].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ
connect issue_slots[17].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm
connect issue_slots[17].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val
connect issue_slots[17].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op
connect issue_slots[17].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw
connect issue_slots[17].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en
connect issue_slots[17].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype
connect issue_slots[17].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype
connect issue_slots[17].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype
connect issue_slots[17].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3
connect issue_slots[17].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2
connect issue_slots[17].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1
connect issue_slots[17].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst
connect issue_slots[17].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1
connect issue_slots[17].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd
connect issue_slots[17].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit
connect issue_slots[17].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique
connect issue_slots[17].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq
connect issue_slots[17].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq
connect issue_slots[17].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed
connect issue_slots[17].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size
connect issue_slots[17].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd
connect issue_slots[17].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause
connect issue_slots[17].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception
connect issue_slots[17].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst
connect issue_slots[17].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy
connect issue_slots[17].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy
connect issue_slots[17].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy
connect issue_slots[17].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy
connect issue_slots[17].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred
connect issue_slots[17].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3
connect issue_slots[17].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2
connect issue_slots[17].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1
connect issue_slots[17].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst
connect issue_slots[17].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx
connect issue_slots[17].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx
connect issue_slots[17].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx
connect issue_slots[17].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx
connect issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec
connect issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags
connect issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt
connect issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div
connect issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma
connect issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe
connect issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint
connect issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint
connect issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23
connect issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12
connect issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3
connect issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2
connect issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1
connect issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen
connect issue_slots[17].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst
connect issue_slots[17].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel
connect issue_slots[17].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel
connect issue_slots[17].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed
connect issue_slots[17].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm
connect issue_slots[17].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel
connect issue_slots[17].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename
connect issue_slots[17].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken
connect issue_slots[17].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob
connect issue_slots[17].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst
connect issue_slots[17].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx
connect issue_slots[17].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov
connect issue_slots[17].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc
connect issue_slots[17].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc
connect issue_slots[17].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret
connect issue_slots[17].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo
connect issue_slots[17].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence
connect issue_slots[17].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei
connect issue_slots[17].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence
connect issue_slots[17].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb
connect issue_slots[17].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type
connect issue_slots[17].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag
connect issue_slots[17].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask
connect issue_slots[17].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel
connect issue_slots[17].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint
connect issue_slots[17].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint
connect issue_slots[17].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint
connect issue_slots[17].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child
connect issue_slots[17].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child
connect issue_slots[17].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen
connect issue_slots[17].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen
connect issue_slots[17].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued
connect issue_slots[17].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0]
connect issue_slots[17].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1]
connect issue_slots[17].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2]
connect issue_slots[17].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3]
connect issue_slots[17].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4]
connect issue_slots[17].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5]
connect issue_slots[17].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6]
connect issue_slots[17].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7]
connect issue_slots[17].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8]
connect issue_slots[17].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9]
connect issue_slots[17].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0]
connect issue_slots[17].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1]
connect issue_slots[17].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2]
connect issue_slots[17].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3]
connect issue_slots[17].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc
connect issue_slots[17].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc
connect issue_slots[17].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst
connect issue_slots[17].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst
connect issue_slots[17].wakeup_ports[3].valid, io.wakeup_ports[3].valid
connect issue_slots[17].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[17].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[17].child_rebusys, io.child_rebusys
connect issue_slots[17].squash_grant, io.squash_grant
connect issue_slots[17].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[17].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[17].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[17].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[17].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[17].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[17].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[17].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[17].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[17].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[17].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[17].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[17].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[17].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ
connect issue_slots[17].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm
connect issue_slots[17].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[17].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op
connect issue_slots[17].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw
connect issue_slots[17].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[17].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[17].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[17].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[17].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[17].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[17].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[17].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[17].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[17].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd
connect issue_slots[17].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[17].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[17].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[17].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[17].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[17].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[17].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[17].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[17].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[17].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[17].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[17].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[17].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[17].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[17].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[17].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[17].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[17].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[17].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[17].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[17].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[17].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[17].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[17].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec
connect issue_slots[17].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags
connect issue_slots[17].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt
connect issue_slots[17].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div
connect issue_slots[17].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma
connect issue_slots[17].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe
connect issue_slots[17].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint
connect issue_slots[17].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint
connect issue_slots[17].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut
connect issue_slots[17].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn
connect issue_slots[17].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23
connect issue_slots[17].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12
connect issue_slots[17].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3
connect issue_slots[17].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2
connect issue_slots[17].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1
connect issue_slots[17].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen
connect issue_slots[17].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst
connect issue_slots[17].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel
connect issue_slots[17].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel
connect issue_slots[17].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[17].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm
connect issue_slots[17].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel
connect issue_slots[17].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename
connect issue_slots[17].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[17].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[17].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[17].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[17].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov
connect issue_slots[17].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc
connect issue_slots[17].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[17].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret
connect issue_slots[17].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[17].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence
connect issue_slots[17].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[17].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[17].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[17].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type
connect issue_slots[17].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[17].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[17].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel
connect issue_slots[17].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint
connect issue_slots[17].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint
connect issue_slots[17].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint
connect issue_slots[17].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child
connect issue_slots[17].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child
connect issue_slots[17].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen
connect issue_slots[17].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen
connect issue_slots[17].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued
connect issue_slots[17].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0]
connect issue_slots[17].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1]
connect issue_slots[17].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2]
connect issue_slots[17].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3]
connect issue_slots[17].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4]
connect issue_slots[17].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5]
connect issue_slots[17].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6]
connect issue_slots[17].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7]
connect issue_slots[17].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8]
connect issue_slots[17].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9]
connect issue_slots[17].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0]
connect issue_slots[17].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1]
connect issue_slots[17].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2]
connect issue_slots[17].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3]
connect issue_slots[17].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[17].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[17].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[17].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[17].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[17].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[17].kill, io.flush_pipeline
connect issue_slots[18].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy
connect issue_slots[18].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask
connect issue_slots[18].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable
connect issue_slots[18].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc
connect issue_slots[18].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc
connect issue_slots[18].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if
connect issue_slots[18].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if
connect issue_slots[18].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if
connect issue_slots[18].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if
connect issue_slots[18].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if
connect issue_slots[18].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ
connect issue_slots[18].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm
connect issue_slots[18].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val
connect issue_slots[18].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op
connect issue_slots[18].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw
connect issue_slots[18].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en
connect issue_slots[18].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype
connect issue_slots[18].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype
connect issue_slots[18].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype
connect issue_slots[18].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3
connect issue_slots[18].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2
connect issue_slots[18].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1
connect issue_slots[18].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst
connect issue_slots[18].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1
connect issue_slots[18].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd
connect issue_slots[18].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit
connect issue_slots[18].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique
connect issue_slots[18].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq
connect issue_slots[18].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq
connect issue_slots[18].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed
connect issue_slots[18].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size
connect issue_slots[18].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd
connect issue_slots[18].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause
connect issue_slots[18].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception
connect issue_slots[18].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst
connect issue_slots[18].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy
connect issue_slots[18].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy
connect issue_slots[18].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy
connect issue_slots[18].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy
connect issue_slots[18].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred
connect issue_slots[18].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3
connect issue_slots[18].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2
connect issue_slots[18].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1
connect issue_slots[18].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst
connect issue_slots[18].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx
connect issue_slots[18].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx
connect issue_slots[18].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx
connect issue_slots[18].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx
connect issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec
connect issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags
connect issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt
connect issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div
connect issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma
connect issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe
connect issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint
connect issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint
connect issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23
connect issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12
connect issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3
connect issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2
connect issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1
connect issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen
connect issue_slots[18].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst
connect issue_slots[18].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel
connect issue_slots[18].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel
connect issue_slots[18].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed
connect issue_slots[18].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm
connect issue_slots[18].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel
connect issue_slots[18].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename
connect issue_slots[18].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken
connect issue_slots[18].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob
connect issue_slots[18].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst
connect issue_slots[18].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx
connect issue_slots[18].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov
connect issue_slots[18].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc
connect issue_slots[18].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc
connect issue_slots[18].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret
connect issue_slots[18].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo
connect issue_slots[18].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence
connect issue_slots[18].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei
connect issue_slots[18].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence
connect issue_slots[18].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb
connect issue_slots[18].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type
connect issue_slots[18].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag
connect issue_slots[18].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask
connect issue_slots[18].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel
connect issue_slots[18].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint
connect issue_slots[18].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint
connect issue_slots[18].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint
connect issue_slots[18].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child
connect issue_slots[18].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child
connect issue_slots[18].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen
connect issue_slots[18].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen
connect issue_slots[18].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued
connect issue_slots[18].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0]
connect issue_slots[18].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1]
connect issue_slots[18].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2]
connect issue_slots[18].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3]
connect issue_slots[18].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4]
connect issue_slots[18].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5]
connect issue_slots[18].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6]
connect issue_slots[18].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7]
connect issue_slots[18].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8]
connect issue_slots[18].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9]
connect issue_slots[18].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0]
connect issue_slots[18].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1]
connect issue_slots[18].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2]
connect issue_slots[18].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3]
connect issue_slots[18].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc
connect issue_slots[18].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc
connect issue_slots[18].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst
connect issue_slots[18].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst
connect issue_slots[18].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[18].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy
connect issue_slots[18].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask
connect issue_slots[18].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable
connect issue_slots[18].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc
connect issue_slots[18].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc
connect issue_slots[18].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if
connect issue_slots[18].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if
connect issue_slots[18].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if
connect issue_slots[18].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if
connect issue_slots[18].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if
connect issue_slots[18].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ
connect issue_slots[18].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm
connect issue_slots[18].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val
connect issue_slots[18].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op
connect issue_slots[18].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw
connect issue_slots[18].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en
connect issue_slots[18].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype
connect issue_slots[18].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype
connect issue_slots[18].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype
connect issue_slots[18].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3
connect issue_slots[18].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2
connect issue_slots[18].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1
connect issue_slots[18].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst
connect issue_slots[18].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1
connect issue_slots[18].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd
connect issue_slots[18].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit
connect issue_slots[18].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique
connect issue_slots[18].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq
connect issue_slots[18].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq
connect issue_slots[18].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed
connect issue_slots[18].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size
connect issue_slots[18].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd
connect issue_slots[18].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause
connect issue_slots[18].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception
connect issue_slots[18].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst
connect issue_slots[18].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy
connect issue_slots[18].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy
connect issue_slots[18].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy
connect issue_slots[18].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy
connect issue_slots[18].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred
connect issue_slots[18].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3
connect issue_slots[18].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2
connect issue_slots[18].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1
connect issue_slots[18].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst
connect issue_slots[18].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx
connect issue_slots[18].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx
connect issue_slots[18].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx
connect issue_slots[18].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx
connect issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec
connect issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags
connect issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt
connect issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div
connect issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma
connect issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe
connect issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint
connect issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint
connect issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23
connect issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12
connect issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3
connect issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2
connect issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1
connect issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen
connect issue_slots[18].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst
connect issue_slots[18].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel
connect issue_slots[18].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel
connect issue_slots[18].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed
connect issue_slots[18].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm
connect issue_slots[18].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel
connect issue_slots[18].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename
connect issue_slots[18].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken
connect issue_slots[18].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob
connect issue_slots[18].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst
connect issue_slots[18].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx
connect issue_slots[18].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov
connect issue_slots[18].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc
connect issue_slots[18].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc
connect issue_slots[18].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret
connect issue_slots[18].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo
connect issue_slots[18].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence
connect issue_slots[18].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei
connect issue_slots[18].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence
connect issue_slots[18].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb
connect issue_slots[18].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type
connect issue_slots[18].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag
connect issue_slots[18].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask
connect issue_slots[18].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel
connect issue_slots[18].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint
connect issue_slots[18].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint
connect issue_slots[18].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint
connect issue_slots[18].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child
connect issue_slots[18].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child
connect issue_slots[18].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen
connect issue_slots[18].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen
connect issue_slots[18].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued
connect issue_slots[18].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0]
connect issue_slots[18].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1]
connect issue_slots[18].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2]
connect issue_slots[18].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3]
connect issue_slots[18].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4]
connect issue_slots[18].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5]
connect issue_slots[18].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6]
connect issue_slots[18].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7]
connect issue_slots[18].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8]
connect issue_slots[18].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9]
connect issue_slots[18].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0]
connect issue_slots[18].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1]
connect issue_slots[18].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2]
connect issue_slots[18].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3]
connect issue_slots[18].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc
connect issue_slots[18].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc
connect issue_slots[18].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst
connect issue_slots[18].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst
connect issue_slots[18].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[18].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy
connect issue_slots[18].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask
connect issue_slots[18].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable
connect issue_slots[18].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc
connect issue_slots[18].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc
connect issue_slots[18].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if
connect issue_slots[18].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if
connect issue_slots[18].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if
connect issue_slots[18].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if
connect issue_slots[18].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if
connect issue_slots[18].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ
connect issue_slots[18].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm
connect issue_slots[18].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val
connect issue_slots[18].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op
connect issue_slots[18].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw
connect issue_slots[18].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en
connect issue_slots[18].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype
connect issue_slots[18].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype
connect issue_slots[18].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype
connect issue_slots[18].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3
connect issue_slots[18].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2
connect issue_slots[18].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1
connect issue_slots[18].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst
connect issue_slots[18].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1
connect issue_slots[18].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd
connect issue_slots[18].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit
connect issue_slots[18].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique
connect issue_slots[18].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq
connect issue_slots[18].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq
connect issue_slots[18].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed
connect issue_slots[18].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size
connect issue_slots[18].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd
connect issue_slots[18].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause
connect issue_slots[18].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception
connect issue_slots[18].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst
connect issue_slots[18].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy
connect issue_slots[18].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy
connect issue_slots[18].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy
connect issue_slots[18].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy
connect issue_slots[18].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred
connect issue_slots[18].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3
connect issue_slots[18].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2
connect issue_slots[18].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1
connect issue_slots[18].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst
connect issue_slots[18].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx
connect issue_slots[18].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx
connect issue_slots[18].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx
connect issue_slots[18].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx
connect issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec
connect issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags
connect issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt
connect issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div
connect issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma
connect issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe
connect issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint
connect issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint
connect issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23
connect issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12
connect issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3
connect issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2
connect issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1
connect issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen
connect issue_slots[18].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst
connect issue_slots[18].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel
connect issue_slots[18].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel
connect issue_slots[18].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed
connect issue_slots[18].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm
connect issue_slots[18].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel
connect issue_slots[18].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename
connect issue_slots[18].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken
connect issue_slots[18].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob
connect issue_slots[18].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst
connect issue_slots[18].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx
connect issue_slots[18].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov
connect issue_slots[18].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc
connect issue_slots[18].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc
connect issue_slots[18].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret
connect issue_slots[18].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo
connect issue_slots[18].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence
connect issue_slots[18].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei
connect issue_slots[18].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence
connect issue_slots[18].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb
connect issue_slots[18].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type
connect issue_slots[18].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag
connect issue_slots[18].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask
connect issue_slots[18].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel
connect issue_slots[18].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint
connect issue_slots[18].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint
connect issue_slots[18].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint
connect issue_slots[18].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child
connect issue_slots[18].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child
connect issue_slots[18].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen
connect issue_slots[18].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen
connect issue_slots[18].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued
connect issue_slots[18].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0]
connect issue_slots[18].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1]
connect issue_slots[18].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2]
connect issue_slots[18].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3]
connect issue_slots[18].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4]
connect issue_slots[18].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5]
connect issue_slots[18].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6]
connect issue_slots[18].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7]
connect issue_slots[18].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8]
connect issue_slots[18].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9]
connect issue_slots[18].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0]
connect issue_slots[18].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1]
connect issue_slots[18].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2]
connect issue_slots[18].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3]
connect issue_slots[18].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc
connect issue_slots[18].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc
connect issue_slots[18].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst
connect issue_slots[18].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst
connect issue_slots[18].wakeup_ports[2].valid, io.wakeup_ports[2].valid
connect issue_slots[18].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy
connect issue_slots[18].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask
connect issue_slots[18].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable
connect issue_slots[18].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc
connect issue_slots[18].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc
connect issue_slots[18].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if
connect issue_slots[18].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if
connect issue_slots[18].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if
connect issue_slots[18].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if
connect issue_slots[18].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if
connect issue_slots[18].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ
connect issue_slots[18].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm
connect issue_slots[18].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val
connect issue_slots[18].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op
connect issue_slots[18].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw
connect issue_slots[18].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en
connect issue_slots[18].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype
connect issue_slots[18].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype
connect issue_slots[18].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype
connect issue_slots[18].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3
connect issue_slots[18].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2
connect issue_slots[18].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1
connect issue_slots[18].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst
connect issue_slots[18].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1
connect issue_slots[18].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd
connect issue_slots[18].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit
connect issue_slots[18].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique
connect issue_slots[18].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq
connect issue_slots[18].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq
connect issue_slots[18].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed
connect issue_slots[18].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size
connect issue_slots[18].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd
connect issue_slots[18].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause
connect issue_slots[18].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception
connect issue_slots[18].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst
connect issue_slots[18].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy
connect issue_slots[18].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy
connect issue_slots[18].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy
connect issue_slots[18].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy
connect issue_slots[18].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred
connect issue_slots[18].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3
connect issue_slots[18].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2
connect issue_slots[18].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1
connect issue_slots[18].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst
connect issue_slots[18].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx
connect issue_slots[18].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx
connect issue_slots[18].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx
connect issue_slots[18].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx
connect issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec
connect issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags
connect issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt
connect issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div
connect issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma
connect issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe
connect issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint
connect issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint
connect issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23
connect issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12
connect issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3
connect issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2
connect issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1
connect issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen
connect issue_slots[18].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst
connect issue_slots[18].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel
connect issue_slots[18].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel
connect issue_slots[18].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed
connect issue_slots[18].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm
connect issue_slots[18].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel
connect issue_slots[18].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename
connect issue_slots[18].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken
connect issue_slots[18].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob
connect issue_slots[18].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst
connect issue_slots[18].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx
connect issue_slots[18].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov
connect issue_slots[18].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc
connect issue_slots[18].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc
connect issue_slots[18].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret
connect issue_slots[18].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo
connect issue_slots[18].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence
connect issue_slots[18].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei
connect issue_slots[18].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence
connect issue_slots[18].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb
connect issue_slots[18].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type
connect issue_slots[18].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag
connect issue_slots[18].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask
connect issue_slots[18].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel
connect issue_slots[18].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint
connect issue_slots[18].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint
connect issue_slots[18].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint
connect issue_slots[18].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child
connect issue_slots[18].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child
connect issue_slots[18].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen
connect issue_slots[18].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen
connect issue_slots[18].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued
connect issue_slots[18].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0]
connect issue_slots[18].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1]
connect issue_slots[18].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2]
connect issue_slots[18].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3]
connect issue_slots[18].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4]
connect issue_slots[18].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5]
connect issue_slots[18].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6]
connect issue_slots[18].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7]
connect issue_slots[18].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8]
connect issue_slots[18].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9]
connect issue_slots[18].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0]
connect issue_slots[18].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1]
connect issue_slots[18].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2]
connect issue_slots[18].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3]
connect issue_slots[18].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc
connect issue_slots[18].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc
connect issue_slots[18].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst
connect issue_slots[18].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst
connect issue_slots[18].wakeup_ports[3].valid, io.wakeup_ports[3].valid
connect issue_slots[18].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[18].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[18].child_rebusys, io.child_rebusys
connect issue_slots[18].squash_grant, io.squash_grant
connect issue_slots[18].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[18].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[18].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[18].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[18].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[18].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[18].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[18].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[18].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[18].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[18].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[18].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[18].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[18].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ
connect issue_slots[18].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm
connect issue_slots[18].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[18].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op
connect issue_slots[18].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw
connect issue_slots[18].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[18].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[18].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[18].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[18].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[18].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[18].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[18].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[18].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[18].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd
connect issue_slots[18].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[18].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[18].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[18].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[18].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[18].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[18].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[18].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[18].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[18].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[18].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[18].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[18].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[18].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[18].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[18].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[18].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[18].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[18].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[18].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[18].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[18].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[18].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[18].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec
connect issue_slots[18].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags
connect issue_slots[18].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt
connect issue_slots[18].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div
connect issue_slots[18].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma
connect issue_slots[18].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe
connect issue_slots[18].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint
connect issue_slots[18].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint
connect issue_slots[18].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut
connect issue_slots[18].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn
connect issue_slots[18].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23
connect issue_slots[18].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12
connect issue_slots[18].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3
connect issue_slots[18].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2
connect issue_slots[18].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1
connect issue_slots[18].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen
connect issue_slots[18].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst
connect issue_slots[18].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel
connect issue_slots[18].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel
connect issue_slots[18].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[18].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm
connect issue_slots[18].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel
connect issue_slots[18].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename
connect issue_slots[18].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[18].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[18].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[18].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[18].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov
connect issue_slots[18].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc
connect issue_slots[18].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[18].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret
connect issue_slots[18].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[18].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence
connect issue_slots[18].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[18].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[18].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[18].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type
connect issue_slots[18].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[18].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[18].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel
connect issue_slots[18].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint
connect issue_slots[18].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint
connect issue_slots[18].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint
connect issue_slots[18].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child
connect issue_slots[18].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child
connect issue_slots[18].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen
connect issue_slots[18].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen
connect issue_slots[18].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued
connect issue_slots[18].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0]
connect issue_slots[18].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1]
connect issue_slots[18].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2]
connect issue_slots[18].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3]
connect issue_slots[18].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4]
connect issue_slots[18].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5]
connect issue_slots[18].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6]
connect issue_slots[18].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7]
connect issue_slots[18].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8]
connect issue_slots[18].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9]
connect issue_slots[18].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0]
connect issue_slots[18].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1]
connect issue_slots[18].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2]
connect issue_slots[18].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3]
connect issue_slots[18].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[18].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[18].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[18].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[18].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[18].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[18].kill, io.flush_pipeline
connect issue_slots[19].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy
connect issue_slots[19].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask
connect issue_slots[19].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable
connect issue_slots[19].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc
connect issue_slots[19].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc
connect issue_slots[19].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if
connect issue_slots[19].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if
connect issue_slots[19].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if
connect issue_slots[19].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if
connect issue_slots[19].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if
connect issue_slots[19].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ
connect issue_slots[19].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm
connect issue_slots[19].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val
connect issue_slots[19].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op
connect issue_slots[19].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw
connect issue_slots[19].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en
connect issue_slots[19].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype
connect issue_slots[19].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype
connect issue_slots[19].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype
connect issue_slots[19].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3
connect issue_slots[19].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2
connect issue_slots[19].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1
connect issue_slots[19].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst
connect issue_slots[19].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1
connect issue_slots[19].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd
connect issue_slots[19].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit
connect issue_slots[19].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique
connect issue_slots[19].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq
connect issue_slots[19].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq
connect issue_slots[19].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed
connect issue_slots[19].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size
connect issue_slots[19].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd
connect issue_slots[19].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause
connect issue_slots[19].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception
connect issue_slots[19].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst
connect issue_slots[19].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy
connect issue_slots[19].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy
connect issue_slots[19].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy
connect issue_slots[19].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy
connect issue_slots[19].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred
connect issue_slots[19].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3
connect issue_slots[19].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2
connect issue_slots[19].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1
connect issue_slots[19].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst
connect issue_slots[19].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx
connect issue_slots[19].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx
connect issue_slots[19].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx
connect issue_slots[19].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx
connect issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec
connect issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags
connect issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt
connect issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div
connect issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma
connect issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe
connect issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint
connect issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint
connect issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23
connect issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12
connect issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3
connect issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2
connect issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1
connect issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen
connect issue_slots[19].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst
connect issue_slots[19].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel
connect issue_slots[19].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel
connect issue_slots[19].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed
connect issue_slots[19].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm
connect issue_slots[19].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel
connect issue_slots[19].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename
connect issue_slots[19].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken
connect issue_slots[19].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob
connect issue_slots[19].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst
connect issue_slots[19].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx
connect issue_slots[19].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov
connect issue_slots[19].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc
connect issue_slots[19].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc
connect issue_slots[19].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret
connect issue_slots[19].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo
connect issue_slots[19].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence
connect issue_slots[19].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei
connect issue_slots[19].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence
connect issue_slots[19].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb
connect issue_slots[19].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type
connect issue_slots[19].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag
connect issue_slots[19].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask
connect issue_slots[19].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel
connect issue_slots[19].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint
connect issue_slots[19].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint
connect issue_slots[19].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint
connect issue_slots[19].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child
connect issue_slots[19].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child
connect issue_slots[19].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen
connect issue_slots[19].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen
connect issue_slots[19].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued
connect issue_slots[19].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0]
connect issue_slots[19].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1]
connect issue_slots[19].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2]
connect issue_slots[19].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3]
connect issue_slots[19].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4]
connect issue_slots[19].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5]
connect issue_slots[19].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6]
connect issue_slots[19].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7]
connect issue_slots[19].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8]
connect issue_slots[19].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9]
connect issue_slots[19].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0]
connect issue_slots[19].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1]
connect issue_slots[19].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2]
connect issue_slots[19].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3]
connect issue_slots[19].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc
connect issue_slots[19].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc
connect issue_slots[19].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst
connect issue_slots[19].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst
connect issue_slots[19].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[19].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy
connect issue_slots[19].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask
connect issue_slots[19].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable
connect issue_slots[19].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc
connect issue_slots[19].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc
connect issue_slots[19].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if
connect issue_slots[19].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if
connect issue_slots[19].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if
connect issue_slots[19].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if
connect issue_slots[19].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if
connect issue_slots[19].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ
connect issue_slots[19].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm
connect issue_slots[19].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val
connect issue_slots[19].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op
connect issue_slots[19].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw
connect issue_slots[19].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en
connect issue_slots[19].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype
connect issue_slots[19].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype
connect issue_slots[19].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype
connect issue_slots[19].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3
connect issue_slots[19].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2
connect issue_slots[19].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1
connect issue_slots[19].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst
connect issue_slots[19].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1
connect issue_slots[19].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd
connect issue_slots[19].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit
connect issue_slots[19].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique
connect issue_slots[19].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq
connect issue_slots[19].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq
connect issue_slots[19].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed
connect issue_slots[19].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size
connect issue_slots[19].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd
connect issue_slots[19].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause
connect issue_slots[19].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception
connect issue_slots[19].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst
connect issue_slots[19].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy
connect issue_slots[19].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy
connect issue_slots[19].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy
connect issue_slots[19].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy
connect issue_slots[19].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred
connect issue_slots[19].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3
connect issue_slots[19].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2
connect issue_slots[19].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1
connect issue_slots[19].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst
connect issue_slots[19].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx
connect issue_slots[19].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx
connect issue_slots[19].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx
connect issue_slots[19].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx
connect issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec
connect issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags
connect issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt
connect issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div
connect issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma
connect issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe
connect issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint
connect issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint
connect issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23
connect issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12
connect issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3
connect issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2
connect issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1
connect issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen
connect issue_slots[19].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst
connect issue_slots[19].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel
connect issue_slots[19].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel
connect issue_slots[19].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed
connect issue_slots[19].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm
connect issue_slots[19].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel
connect issue_slots[19].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename
connect issue_slots[19].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken
connect issue_slots[19].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob
connect issue_slots[19].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst
connect issue_slots[19].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx
connect issue_slots[19].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov
connect issue_slots[19].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc
connect issue_slots[19].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc
connect issue_slots[19].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret
connect issue_slots[19].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo
connect issue_slots[19].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence
connect issue_slots[19].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei
connect issue_slots[19].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence
connect issue_slots[19].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb
connect issue_slots[19].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type
connect issue_slots[19].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag
connect issue_slots[19].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask
connect issue_slots[19].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel
connect issue_slots[19].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint
connect issue_slots[19].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint
connect issue_slots[19].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint
connect issue_slots[19].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child
connect issue_slots[19].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child
connect issue_slots[19].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen
connect issue_slots[19].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen
connect issue_slots[19].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued
connect issue_slots[19].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0]
connect issue_slots[19].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1]
connect issue_slots[19].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2]
connect issue_slots[19].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3]
connect issue_slots[19].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4]
connect issue_slots[19].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5]
connect issue_slots[19].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6]
connect issue_slots[19].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7]
connect issue_slots[19].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8]
connect issue_slots[19].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9]
connect issue_slots[19].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0]
connect issue_slots[19].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1]
connect issue_slots[19].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2]
connect issue_slots[19].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3]
connect issue_slots[19].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc
connect issue_slots[19].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc
connect issue_slots[19].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst
connect issue_slots[19].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst
connect issue_slots[19].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[19].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy
connect issue_slots[19].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask
connect issue_slots[19].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable
connect issue_slots[19].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc
connect issue_slots[19].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc
connect issue_slots[19].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if
connect issue_slots[19].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if
connect issue_slots[19].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if
connect issue_slots[19].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if
connect issue_slots[19].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if
connect issue_slots[19].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ
connect issue_slots[19].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm
connect issue_slots[19].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val
connect issue_slots[19].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op
connect issue_slots[19].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw
connect issue_slots[19].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en
connect issue_slots[19].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype
connect issue_slots[19].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype
connect issue_slots[19].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype
connect issue_slots[19].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3
connect issue_slots[19].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2
connect issue_slots[19].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1
connect issue_slots[19].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst
connect issue_slots[19].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1
connect issue_slots[19].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd
connect issue_slots[19].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit
connect issue_slots[19].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique
connect issue_slots[19].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq
connect issue_slots[19].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq
connect issue_slots[19].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed
connect issue_slots[19].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size
connect issue_slots[19].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd
connect issue_slots[19].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause
connect issue_slots[19].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception
connect issue_slots[19].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst
connect issue_slots[19].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy
connect issue_slots[19].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy
connect issue_slots[19].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy
connect issue_slots[19].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy
connect issue_slots[19].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred
connect issue_slots[19].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3
connect issue_slots[19].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2
connect issue_slots[19].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1
connect issue_slots[19].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst
connect issue_slots[19].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx
connect issue_slots[19].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx
connect issue_slots[19].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx
connect issue_slots[19].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx
connect issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec
connect issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags
connect issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt
connect issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div
connect issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma
connect issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe
connect issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint
connect issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint
connect issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23
connect issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12
connect issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3
connect issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2
connect issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1
connect issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen
connect issue_slots[19].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst
connect issue_slots[19].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel
connect issue_slots[19].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel
connect issue_slots[19].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed
connect issue_slots[19].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm
connect issue_slots[19].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel
connect issue_slots[19].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename
connect issue_slots[19].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken
connect issue_slots[19].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob
connect issue_slots[19].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst
connect issue_slots[19].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx
connect issue_slots[19].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov
connect issue_slots[19].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc
connect issue_slots[19].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc
connect issue_slots[19].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret
connect issue_slots[19].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo
connect issue_slots[19].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence
connect issue_slots[19].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei
connect issue_slots[19].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence
connect issue_slots[19].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb
connect issue_slots[19].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type
connect issue_slots[19].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag
connect issue_slots[19].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask
connect issue_slots[19].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel
connect issue_slots[19].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint
connect issue_slots[19].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint
connect issue_slots[19].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint
connect issue_slots[19].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child
connect issue_slots[19].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child
connect issue_slots[19].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen
connect issue_slots[19].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen
connect issue_slots[19].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued
connect issue_slots[19].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0]
connect issue_slots[19].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1]
connect issue_slots[19].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2]
connect issue_slots[19].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3]
connect issue_slots[19].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4]
connect issue_slots[19].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5]
connect issue_slots[19].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6]
connect issue_slots[19].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7]
connect issue_slots[19].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8]
connect issue_slots[19].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9]
connect issue_slots[19].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0]
connect issue_slots[19].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1]
connect issue_slots[19].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2]
connect issue_slots[19].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3]
connect issue_slots[19].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc
connect issue_slots[19].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc
connect issue_slots[19].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst
connect issue_slots[19].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst
connect issue_slots[19].wakeup_ports[2].valid, io.wakeup_ports[2].valid
connect issue_slots[19].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy
connect issue_slots[19].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask
connect issue_slots[19].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable
connect issue_slots[19].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc
connect issue_slots[19].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc
connect issue_slots[19].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if
connect issue_slots[19].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if
connect issue_slots[19].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if
connect issue_slots[19].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if
connect issue_slots[19].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if
connect issue_slots[19].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ
connect issue_slots[19].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm
connect issue_slots[19].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val
connect issue_slots[19].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op
connect issue_slots[19].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw
connect issue_slots[19].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en
connect issue_slots[19].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype
connect issue_slots[19].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype
connect issue_slots[19].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype
connect issue_slots[19].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3
connect issue_slots[19].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2
connect issue_slots[19].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1
connect issue_slots[19].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst
connect issue_slots[19].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1
connect issue_slots[19].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd
connect issue_slots[19].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit
connect issue_slots[19].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique
connect issue_slots[19].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq
connect issue_slots[19].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq
connect issue_slots[19].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed
connect issue_slots[19].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size
connect issue_slots[19].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd
connect issue_slots[19].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause
connect issue_slots[19].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception
connect issue_slots[19].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst
connect issue_slots[19].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy
connect issue_slots[19].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy
connect issue_slots[19].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy
connect issue_slots[19].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy
connect issue_slots[19].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred
connect issue_slots[19].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3
connect issue_slots[19].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2
connect issue_slots[19].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1
connect issue_slots[19].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst
connect issue_slots[19].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx
connect issue_slots[19].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx
connect issue_slots[19].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx
connect issue_slots[19].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx
connect issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec
connect issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags
connect issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt
connect issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div
connect issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma
connect issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe
connect issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint
connect issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint
connect issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut
connect issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn
connect issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23
connect issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12
connect issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3
connect issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2
connect issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1
connect issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen
connect issue_slots[19].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst
connect issue_slots[19].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel
connect issue_slots[19].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel
connect issue_slots[19].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed
connect issue_slots[19].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm
connect issue_slots[19].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel
connect issue_slots[19].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename
connect issue_slots[19].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken
connect issue_slots[19].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob
connect issue_slots[19].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst
connect issue_slots[19].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx
connect issue_slots[19].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov
connect issue_slots[19].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc
connect issue_slots[19].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc
connect issue_slots[19].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret
connect issue_slots[19].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo
connect issue_slots[19].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence
connect issue_slots[19].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei
connect issue_slots[19].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence
connect issue_slots[19].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb
connect issue_slots[19].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type
connect issue_slots[19].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag
connect issue_slots[19].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask
connect issue_slots[19].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel
connect issue_slots[19].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint
connect issue_slots[19].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint
connect issue_slots[19].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint
connect issue_slots[19].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child
connect issue_slots[19].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child
connect issue_slots[19].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen
connect issue_slots[19].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen
connect issue_slots[19].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued
connect issue_slots[19].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0]
connect issue_slots[19].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1]
connect issue_slots[19].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2]
connect issue_slots[19].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3]
connect issue_slots[19].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4]
connect issue_slots[19].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5]
connect issue_slots[19].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6]
connect issue_slots[19].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7]
connect issue_slots[19].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8]
connect issue_slots[19].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9]
connect issue_slots[19].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0]
connect issue_slots[19].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1]
connect issue_slots[19].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2]
connect issue_slots[19].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3]
connect issue_slots[19].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc
connect issue_slots[19].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc
connect issue_slots[19].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst
connect issue_slots[19].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst
connect issue_slots[19].wakeup_ports[3].valid, io.wakeup_ports[3].valid
connect issue_slots[19].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[19].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[19].child_rebusys, io.child_rebusys
connect issue_slots[19].squash_grant, io.squash_grant
connect issue_slots[19].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[19].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[19].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[19].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[19].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[19].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[19].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[19].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[19].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[19].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[19].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[19].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[19].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[19].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ
connect issue_slots[19].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm
connect issue_slots[19].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[19].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op
connect issue_slots[19].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw
connect issue_slots[19].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[19].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[19].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[19].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[19].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[19].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[19].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[19].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[19].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[19].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd
connect issue_slots[19].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[19].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[19].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[19].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[19].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[19].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[19].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[19].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[19].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[19].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[19].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[19].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[19].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[19].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[19].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[19].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[19].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[19].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[19].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[19].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[19].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[19].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[19].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[19].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec
connect issue_slots[19].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags
connect issue_slots[19].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt
connect issue_slots[19].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div
connect issue_slots[19].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma
connect issue_slots[19].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe
connect issue_slots[19].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint
connect issue_slots[19].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint
connect issue_slots[19].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut
connect issue_slots[19].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn
connect issue_slots[19].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23
connect issue_slots[19].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12
connect issue_slots[19].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3
connect issue_slots[19].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2
connect issue_slots[19].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1
connect issue_slots[19].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen
connect issue_slots[19].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst
connect issue_slots[19].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel
connect issue_slots[19].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel
connect issue_slots[19].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[19].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm
connect issue_slots[19].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel
connect issue_slots[19].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename
connect issue_slots[19].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[19].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[19].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[19].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[19].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov
connect issue_slots[19].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc
connect issue_slots[19].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[19].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret
connect issue_slots[19].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[19].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence
connect issue_slots[19].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[19].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[19].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[19].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type
connect issue_slots[19].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[19].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[19].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel
connect issue_slots[19].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint
connect issue_slots[19].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint
connect issue_slots[19].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint
connect issue_slots[19].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child
connect issue_slots[19].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child
connect issue_slots[19].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen
connect issue_slots[19].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen
connect issue_slots[19].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued
connect issue_slots[19].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0]
connect issue_slots[19].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1]
connect issue_slots[19].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2]
connect issue_slots[19].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3]
connect issue_slots[19].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4]
connect issue_slots[19].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5]
connect issue_slots[19].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6]
connect issue_slots[19].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7]
connect issue_slots[19].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8]
connect issue_slots[19].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9]
connect issue_slots[19].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0]
connect issue_slots[19].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1]
connect issue_slots[19].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2]
connect issue_slots[19].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3]
connect issue_slots[19].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[19].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[19].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[19].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[19].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[19].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[19].kill, io.flush_pipeline
connect io.iss_uops[0].valid, UInt<1>(0h0)
connect io.iss_uops[1].valid, UInt<1>(0h0)
node _T_120 = add(issue_slots[0].grant, issue_slots[1].grant)
node _T_121 = bits(_T_120, 1, 0)
node _T_122 = add(issue_slots[3].grant, issue_slots[4].grant)
node _T_123 = bits(_T_122, 1, 0)
node _T_124 = add(issue_slots[2].grant, _T_123)
node _T_125 = bits(_T_124, 1, 0)
node _T_126 = add(_T_121, _T_125)
node _T_127 = bits(_T_126, 2, 0)
node _T_128 = add(issue_slots[5].grant, issue_slots[6].grant)
node _T_129 = bits(_T_128, 1, 0)
node _T_130 = add(issue_slots[8].grant, issue_slots[9].grant)
node _T_131 = bits(_T_130, 1, 0)
node _T_132 = add(issue_slots[7].grant, _T_131)
node _T_133 = bits(_T_132, 1, 0)
node _T_134 = add(_T_129, _T_133)
node _T_135 = bits(_T_134, 2, 0)
node _T_136 = add(_T_127, _T_135)
node _T_137 = bits(_T_136, 3, 0)
node _T_138 = add(issue_slots[10].grant, issue_slots[11].grant)
node _T_139 = bits(_T_138, 1, 0)
node _T_140 = add(issue_slots[13].grant, issue_slots[14].grant)
node _T_141 = bits(_T_140, 1, 0)
node _T_142 = add(issue_slots[12].grant, _T_141)
node _T_143 = bits(_T_142, 1, 0)
node _T_144 = add(_T_139, _T_143)
node _T_145 = bits(_T_144, 2, 0)
node _T_146 = add(issue_slots[15].grant, issue_slots[16].grant)
node _T_147 = bits(_T_146, 1, 0)
node _T_148 = add(issue_slots[18].grant, issue_slots[19].grant)
node _T_149 = bits(_T_148, 1, 0)
node _T_150 = add(issue_slots[17].grant, _T_149)
node _T_151 = bits(_T_150, 1, 0)
node _T_152 = add(_T_147, _T_151)
node _T_153 = bits(_T_152, 2, 0)
node _T_154 = add(_T_145, _T_153)
node _T_155 = bits(_T_154, 3, 0)
node _T_156 = add(_T_137, _T_155)
node _T_157 = bits(_T_156, 4, 0)
node _T_158 = leq(_T_157, UInt<2>(0h2))
node _T_159 = asUInt(reset)
node _T_160 = eq(_T_159, UInt<1>(0h0))
when _T_160 :
node _T_161 = eq(_T_158, UInt<1>(0h0))
when _T_161 :
printf(clock, UInt<1>(0h1), "Assertion failed: [issue] window giving out too many grants.\n at issue-unit-age-ordered.scala:141 assert (PopCount(issue_slots.map(s => s.grant)) <= issueWidth.U, \"[issue] window giving out too many grants.\")\n") : printf
assert(clock, _T_158, UInt<1>(0h1), "") : assert
node vacants_0 = eq(issue_slots[0].valid, UInt<1>(0h0))
node vacants_1 = eq(issue_slots[1].valid, UInt<1>(0h0))
node vacants_2 = eq(issue_slots[2].valid, UInt<1>(0h0))
node vacants_3 = eq(issue_slots[3].valid, UInt<1>(0h0))
node vacants_4 = eq(issue_slots[4].valid, UInt<1>(0h0))
node vacants_5 = eq(issue_slots[5].valid, UInt<1>(0h0))
node vacants_6 = eq(issue_slots[6].valid, UInt<1>(0h0))
node vacants_7 = eq(issue_slots[7].valid, UInt<1>(0h0))
node vacants_8 = eq(issue_slots[8].valid, UInt<1>(0h0))
node vacants_9 = eq(issue_slots[9].valid, UInt<1>(0h0))
node vacants_10 = eq(issue_slots[10].valid, UInt<1>(0h0))
node vacants_11 = eq(issue_slots[11].valid, UInt<1>(0h0))
node vacants_12 = eq(issue_slots[12].valid, UInt<1>(0h0))
node vacants_13 = eq(issue_slots[13].valid, UInt<1>(0h0))
node vacants_14 = eq(issue_slots[14].valid, UInt<1>(0h0))
node vacants_15 = eq(issue_slots[15].valid, UInt<1>(0h0))
node vacants_16 = eq(issue_slots[16].valid, UInt<1>(0h0))
node vacants_17 = eq(issue_slots[17].valid, UInt<1>(0h0))
node vacants_18 = eq(issue_slots[18].valid, UInt<1>(0h0))
node vacants_19 = eq(issue_slots[19].valid, UInt<1>(0h0))
node vacants_20 = eq(io.dis_uops[0].valid, UInt<1>(0h0))
node vacants_21 = eq(io.dis_uops[1].valid, UInt<1>(0h0))
wire shamts_oh : UInt<2>[22]
connect shamts_oh[0], UInt<1>(0h0)
wire shamts_oh_1_next : UInt<2>
connect shamts_oh_1_next, shamts_oh[0]
node _shamts_oh_1_T = eq(shamts_oh[0], UInt<1>(0h0))
node _shamts_oh_1_T_1 = and(_shamts_oh_1_T, vacants_0)
when _shamts_oh_1_T_1 :
connect shamts_oh_1_next, UInt<1>(0h1)
else :
node _shamts_oh_1_T_2 = bits(shamts_oh[0], 1, 1)
node _shamts_oh_1_T_3 = eq(_shamts_oh_1_T_2, UInt<1>(0h0))
node _shamts_oh_1_T_4 = and(_shamts_oh_1_T_3, vacants_0)
when _shamts_oh_1_T_4 :
node _shamts_oh_1_next_T = dshl(shamts_oh[0], UInt<1>(0h1))
connect shamts_oh_1_next, _shamts_oh_1_next_T
connect shamts_oh[1], shamts_oh_1_next
wire shamts_oh_2_next : UInt<2>
connect shamts_oh_2_next, shamts_oh[1]
node _shamts_oh_2_T = eq(shamts_oh[1], UInt<1>(0h0))
node _shamts_oh_2_T_1 = and(_shamts_oh_2_T, vacants_1)
when _shamts_oh_2_T_1 :
connect shamts_oh_2_next, UInt<1>(0h1)
else :
node _shamts_oh_2_T_2 = bits(shamts_oh[1], 1, 1)
node _shamts_oh_2_T_3 = eq(_shamts_oh_2_T_2, UInt<1>(0h0))
node _shamts_oh_2_T_4 = and(_shamts_oh_2_T_3, vacants_1)
when _shamts_oh_2_T_4 :
node _shamts_oh_2_next_T = dshl(shamts_oh[1], UInt<1>(0h1))
connect shamts_oh_2_next, _shamts_oh_2_next_T
connect shamts_oh[2], shamts_oh_2_next
wire shamts_oh_3_next : UInt<2>
connect shamts_oh_3_next, shamts_oh[2]
node _shamts_oh_3_T = eq(shamts_oh[2], UInt<1>(0h0))
node _shamts_oh_3_T_1 = and(_shamts_oh_3_T, vacants_2)
when _shamts_oh_3_T_1 :
connect shamts_oh_3_next, UInt<1>(0h1)
else :
node _shamts_oh_3_T_2 = bits(shamts_oh[2], 1, 1)
node _shamts_oh_3_T_3 = eq(_shamts_oh_3_T_2, UInt<1>(0h0))
node _shamts_oh_3_T_4 = and(_shamts_oh_3_T_3, vacants_2)
when _shamts_oh_3_T_4 :
node _shamts_oh_3_next_T = dshl(shamts_oh[2], UInt<1>(0h1))
connect shamts_oh_3_next, _shamts_oh_3_next_T
connect shamts_oh[3], shamts_oh_3_next
wire shamts_oh_4_next : UInt<2>
connect shamts_oh_4_next, shamts_oh[3]
node _shamts_oh_4_T = eq(shamts_oh[3], UInt<1>(0h0))
node _shamts_oh_4_T_1 = and(_shamts_oh_4_T, vacants_3)
when _shamts_oh_4_T_1 :
connect shamts_oh_4_next, UInt<1>(0h1)
else :
node _shamts_oh_4_T_2 = bits(shamts_oh[3], 1, 1)
node _shamts_oh_4_T_3 = eq(_shamts_oh_4_T_2, UInt<1>(0h0))
node _shamts_oh_4_T_4 = and(_shamts_oh_4_T_3, vacants_3)
when _shamts_oh_4_T_4 :
node _shamts_oh_4_next_T = dshl(shamts_oh[3], UInt<1>(0h1))
connect shamts_oh_4_next, _shamts_oh_4_next_T
connect shamts_oh[4], shamts_oh_4_next
wire shamts_oh_5_next : UInt<2>
connect shamts_oh_5_next, shamts_oh[4]
node _shamts_oh_5_T = eq(shamts_oh[4], UInt<1>(0h0))
node _shamts_oh_5_T_1 = and(_shamts_oh_5_T, vacants_4)
when _shamts_oh_5_T_1 :
connect shamts_oh_5_next, UInt<1>(0h1)
else :
node _shamts_oh_5_T_2 = bits(shamts_oh[4], 1, 1)
node _shamts_oh_5_T_3 = eq(_shamts_oh_5_T_2, UInt<1>(0h0))
node _shamts_oh_5_T_4 = and(_shamts_oh_5_T_3, vacants_4)
when _shamts_oh_5_T_4 :
node _shamts_oh_5_next_T = dshl(shamts_oh[4], UInt<1>(0h1))
connect shamts_oh_5_next, _shamts_oh_5_next_T
connect shamts_oh[5], shamts_oh_5_next
wire shamts_oh_6_next : UInt<2>
connect shamts_oh_6_next, shamts_oh[5]
node _shamts_oh_6_T = eq(shamts_oh[5], UInt<1>(0h0))
node _shamts_oh_6_T_1 = and(_shamts_oh_6_T, vacants_5)
when _shamts_oh_6_T_1 :
connect shamts_oh_6_next, UInt<1>(0h1)
else :
node _shamts_oh_6_T_2 = bits(shamts_oh[5], 1, 1)
node _shamts_oh_6_T_3 = eq(_shamts_oh_6_T_2, UInt<1>(0h0))
node _shamts_oh_6_T_4 = and(_shamts_oh_6_T_3, vacants_5)
when _shamts_oh_6_T_4 :
node _shamts_oh_6_next_T = dshl(shamts_oh[5], UInt<1>(0h1))
connect shamts_oh_6_next, _shamts_oh_6_next_T
connect shamts_oh[6], shamts_oh_6_next
wire shamts_oh_7_next : UInt<2>
connect shamts_oh_7_next, shamts_oh[6]
node _shamts_oh_7_T = eq(shamts_oh[6], UInt<1>(0h0))
node _shamts_oh_7_T_1 = and(_shamts_oh_7_T, vacants_6)
when _shamts_oh_7_T_1 :
connect shamts_oh_7_next, UInt<1>(0h1)
else :
node _shamts_oh_7_T_2 = bits(shamts_oh[6], 1, 1)
node _shamts_oh_7_T_3 = eq(_shamts_oh_7_T_2, UInt<1>(0h0))
node _shamts_oh_7_T_4 = and(_shamts_oh_7_T_3, vacants_6)
when _shamts_oh_7_T_4 :
node _shamts_oh_7_next_T = dshl(shamts_oh[6], UInt<1>(0h1))
connect shamts_oh_7_next, _shamts_oh_7_next_T
connect shamts_oh[7], shamts_oh_7_next
wire shamts_oh_8_next : UInt<2>
connect shamts_oh_8_next, shamts_oh[7]
node _shamts_oh_8_T = eq(shamts_oh[7], UInt<1>(0h0))
node _shamts_oh_8_T_1 = and(_shamts_oh_8_T, vacants_7)
when _shamts_oh_8_T_1 :
connect shamts_oh_8_next, UInt<1>(0h1)
else :
node _shamts_oh_8_T_2 = bits(shamts_oh[7], 1, 1)
node _shamts_oh_8_T_3 = eq(_shamts_oh_8_T_2, UInt<1>(0h0))
node _shamts_oh_8_T_4 = and(_shamts_oh_8_T_3, vacants_7)
when _shamts_oh_8_T_4 :
node _shamts_oh_8_next_T = dshl(shamts_oh[7], UInt<1>(0h1))
connect shamts_oh_8_next, _shamts_oh_8_next_T
connect shamts_oh[8], shamts_oh_8_next
wire shamts_oh_9_next : UInt<2>
connect shamts_oh_9_next, shamts_oh[8]
node _shamts_oh_9_T = eq(shamts_oh[8], UInt<1>(0h0))
node _shamts_oh_9_T_1 = and(_shamts_oh_9_T, vacants_8)
when _shamts_oh_9_T_1 :
connect shamts_oh_9_next, UInt<1>(0h1)
else :
node _shamts_oh_9_T_2 = bits(shamts_oh[8], 1, 1)
node _shamts_oh_9_T_3 = eq(_shamts_oh_9_T_2, UInt<1>(0h0))
node _shamts_oh_9_T_4 = and(_shamts_oh_9_T_3, vacants_8)
when _shamts_oh_9_T_4 :
node _shamts_oh_9_next_T = dshl(shamts_oh[8], UInt<1>(0h1))
connect shamts_oh_9_next, _shamts_oh_9_next_T
connect shamts_oh[9], shamts_oh_9_next
wire shamts_oh_10_next : UInt<2>
connect shamts_oh_10_next, shamts_oh[9]
node _shamts_oh_10_T = eq(shamts_oh[9], UInt<1>(0h0))
node _shamts_oh_10_T_1 = and(_shamts_oh_10_T, vacants_9)
when _shamts_oh_10_T_1 :
connect shamts_oh_10_next, UInt<1>(0h1)
else :
node _shamts_oh_10_T_2 = bits(shamts_oh[9], 1, 1)
node _shamts_oh_10_T_3 = eq(_shamts_oh_10_T_2, UInt<1>(0h0))
node _shamts_oh_10_T_4 = and(_shamts_oh_10_T_3, vacants_9)
when _shamts_oh_10_T_4 :
node _shamts_oh_10_next_T = dshl(shamts_oh[9], UInt<1>(0h1))
connect shamts_oh_10_next, _shamts_oh_10_next_T
connect shamts_oh[10], shamts_oh_10_next
wire shamts_oh_11_next : UInt<2>
connect shamts_oh_11_next, shamts_oh[10]
node _shamts_oh_11_T = eq(shamts_oh[10], UInt<1>(0h0))
node _shamts_oh_11_T_1 = and(_shamts_oh_11_T, vacants_10)
when _shamts_oh_11_T_1 :
connect shamts_oh_11_next, UInt<1>(0h1)
else :
node _shamts_oh_11_T_2 = bits(shamts_oh[10], 1, 1)
node _shamts_oh_11_T_3 = eq(_shamts_oh_11_T_2, UInt<1>(0h0))
node _shamts_oh_11_T_4 = and(_shamts_oh_11_T_3, vacants_10)
when _shamts_oh_11_T_4 :
node _shamts_oh_11_next_T = dshl(shamts_oh[10], UInt<1>(0h1))
connect shamts_oh_11_next, _shamts_oh_11_next_T
connect shamts_oh[11], shamts_oh_11_next
wire shamts_oh_12_next : UInt<2>
connect shamts_oh_12_next, shamts_oh[11]
node _shamts_oh_12_T = eq(shamts_oh[11], UInt<1>(0h0))
node _shamts_oh_12_T_1 = and(_shamts_oh_12_T, vacants_11)
when _shamts_oh_12_T_1 :
connect shamts_oh_12_next, UInt<1>(0h1)
else :
node _shamts_oh_12_T_2 = bits(shamts_oh[11], 1, 1)
node _shamts_oh_12_T_3 = eq(_shamts_oh_12_T_2, UInt<1>(0h0))
node _shamts_oh_12_T_4 = and(_shamts_oh_12_T_3, vacants_11)
when _shamts_oh_12_T_4 :
node _shamts_oh_12_next_T = dshl(shamts_oh[11], UInt<1>(0h1))
connect shamts_oh_12_next, _shamts_oh_12_next_T
connect shamts_oh[12], shamts_oh_12_next
wire shamts_oh_13_next : UInt<2>
connect shamts_oh_13_next, shamts_oh[12]
node _shamts_oh_13_T = eq(shamts_oh[12], UInt<1>(0h0))
node _shamts_oh_13_T_1 = and(_shamts_oh_13_T, vacants_12)
when _shamts_oh_13_T_1 :
connect shamts_oh_13_next, UInt<1>(0h1)
else :
node _shamts_oh_13_T_2 = bits(shamts_oh[12], 1, 1)
node _shamts_oh_13_T_3 = eq(_shamts_oh_13_T_2, UInt<1>(0h0))
node _shamts_oh_13_T_4 = and(_shamts_oh_13_T_3, vacants_12)
when _shamts_oh_13_T_4 :
node _shamts_oh_13_next_T = dshl(shamts_oh[12], UInt<1>(0h1))
connect shamts_oh_13_next, _shamts_oh_13_next_T
connect shamts_oh[13], shamts_oh_13_next
wire shamts_oh_14_next : UInt<2>
connect shamts_oh_14_next, shamts_oh[13]
node _shamts_oh_14_T = eq(shamts_oh[13], UInt<1>(0h0))
node _shamts_oh_14_T_1 = and(_shamts_oh_14_T, vacants_13)
when _shamts_oh_14_T_1 :
connect shamts_oh_14_next, UInt<1>(0h1)
else :
node _shamts_oh_14_T_2 = bits(shamts_oh[13], 1, 1)
node _shamts_oh_14_T_3 = eq(_shamts_oh_14_T_2, UInt<1>(0h0))
node _shamts_oh_14_T_4 = and(_shamts_oh_14_T_3, vacants_13)
when _shamts_oh_14_T_4 :
node _shamts_oh_14_next_T = dshl(shamts_oh[13], UInt<1>(0h1))
connect shamts_oh_14_next, _shamts_oh_14_next_T
connect shamts_oh[14], shamts_oh_14_next
wire shamts_oh_15_next : UInt<2>
connect shamts_oh_15_next, shamts_oh[14]
node _shamts_oh_15_T = eq(shamts_oh[14], UInt<1>(0h0))
node _shamts_oh_15_T_1 = and(_shamts_oh_15_T, vacants_14)
when _shamts_oh_15_T_1 :
connect shamts_oh_15_next, UInt<1>(0h1)
else :
node _shamts_oh_15_T_2 = bits(shamts_oh[14], 1, 1)
node _shamts_oh_15_T_3 = eq(_shamts_oh_15_T_2, UInt<1>(0h0))
node _shamts_oh_15_T_4 = and(_shamts_oh_15_T_3, vacants_14)
when _shamts_oh_15_T_4 :
node _shamts_oh_15_next_T = dshl(shamts_oh[14], UInt<1>(0h1))
connect shamts_oh_15_next, _shamts_oh_15_next_T
connect shamts_oh[15], shamts_oh_15_next
wire shamts_oh_16_next : UInt<2>
connect shamts_oh_16_next, shamts_oh[15]
node _shamts_oh_16_T = eq(shamts_oh[15], UInt<1>(0h0))
node _shamts_oh_16_T_1 = and(_shamts_oh_16_T, vacants_15)
when _shamts_oh_16_T_1 :
connect shamts_oh_16_next, UInt<1>(0h1)
else :
node _shamts_oh_16_T_2 = bits(shamts_oh[15], 1, 1)
node _shamts_oh_16_T_3 = eq(_shamts_oh_16_T_2, UInt<1>(0h0))
node _shamts_oh_16_T_4 = and(_shamts_oh_16_T_3, vacants_15)
when _shamts_oh_16_T_4 :
node _shamts_oh_16_next_T = dshl(shamts_oh[15], UInt<1>(0h1))
connect shamts_oh_16_next, _shamts_oh_16_next_T
connect shamts_oh[16], shamts_oh_16_next
wire shamts_oh_17_next : UInt<2>
connect shamts_oh_17_next, shamts_oh[16]
node _shamts_oh_17_T = eq(shamts_oh[16], UInt<1>(0h0))
node _shamts_oh_17_T_1 = and(_shamts_oh_17_T, vacants_16)
when _shamts_oh_17_T_1 :
connect shamts_oh_17_next, UInt<1>(0h1)
else :
node _shamts_oh_17_T_2 = bits(shamts_oh[16], 1, 1)
node _shamts_oh_17_T_3 = eq(_shamts_oh_17_T_2, UInt<1>(0h0))
node _shamts_oh_17_T_4 = and(_shamts_oh_17_T_3, vacants_16)
when _shamts_oh_17_T_4 :
node _shamts_oh_17_next_T = dshl(shamts_oh[16], UInt<1>(0h1))
connect shamts_oh_17_next, _shamts_oh_17_next_T
connect shamts_oh[17], shamts_oh_17_next
wire shamts_oh_18_next : UInt<2>
connect shamts_oh_18_next, shamts_oh[17]
node _shamts_oh_18_T = eq(shamts_oh[17], UInt<1>(0h0))
node _shamts_oh_18_T_1 = and(_shamts_oh_18_T, vacants_17)
when _shamts_oh_18_T_1 :
connect shamts_oh_18_next, UInt<1>(0h1)
else :
node _shamts_oh_18_T_2 = bits(shamts_oh[17], 1, 1)
node _shamts_oh_18_T_3 = eq(_shamts_oh_18_T_2, UInt<1>(0h0))
node _shamts_oh_18_T_4 = and(_shamts_oh_18_T_3, vacants_17)
when _shamts_oh_18_T_4 :
node _shamts_oh_18_next_T = dshl(shamts_oh[17], UInt<1>(0h1))
connect shamts_oh_18_next, _shamts_oh_18_next_T
connect shamts_oh[18], shamts_oh_18_next
wire shamts_oh_19_next : UInt<2>
connect shamts_oh_19_next, shamts_oh[18]
node _shamts_oh_19_T = eq(shamts_oh[18], UInt<1>(0h0))
node _shamts_oh_19_T_1 = and(_shamts_oh_19_T, vacants_18)
when _shamts_oh_19_T_1 :
connect shamts_oh_19_next, UInt<1>(0h1)
else :
node _shamts_oh_19_T_2 = bits(shamts_oh[18], 1, 1)
node _shamts_oh_19_T_3 = eq(_shamts_oh_19_T_2, UInt<1>(0h0))
node _shamts_oh_19_T_4 = and(_shamts_oh_19_T_3, vacants_18)
when _shamts_oh_19_T_4 :
node _shamts_oh_19_next_T = dshl(shamts_oh[18], UInt<1>(0h1))
connect shamts_oh_19_next, _shamts_oh_19_next_T
connect shamts_oh[19], shamts_oh_19_next
wire shamts_oh_20_next : UInt<2>
connect shamts_oh_20_next, shamts_oh[19]
node _shamts_oh_20_T = eq(shamts_oh[19], UInt<1>(0h0))
node _shamts_oh_20_T_1 = and(_shamts_oh_20_T, vacants_19)
when _shamts_oh_20_T_1 :
connect shamts_oh_20_next, UInt<1>(0h1)
else :
node _shamts_oh_20_T_2 = bits(shamts_oh[19], 1, 1)
node _shamts_oh_20_T_3 = eq(_shamts_oh_20_T_2, UInt<1>(0h0))
node _shamts_oh_20_T_4 = and(_shamts_oh_20_T_3, vacants_19)
when _shamts_oh_20_T_4 :
node _shamts_oh_20_next_T = dshl(shamts_oh[19], UInt<1>(0h1))
connect shamts_oh_20_next, _shamts_oh_20_next_T
connect shamts_oh[20], shamts_oh_20_next
wire shamts_oh_21_next : UInt<2>
connect shamts_oh_21_next, shamts_oh[20]
node _shamts_oh_21_T = eq(shamts_oh[20], UInt<1>(0h0))
node _shamts_oh_21_T_1 = and(_shamts_oh_21_T, vacants_20)
when _shamts_oh_21_T_1 :
connect shamts_oh_21_next, UInt<1>(0h1)
else :
node _shamts_oh_21_T_2 = bits(shamts_oh[20], 1, 1)
node _shamts_oh_21_T_3 = eq(_shamts_oh_21_T_2, UInt<1>(0h0))
node _shamts_oh_21_T_4 = and(_shamts_oh_21_T_3, vacants_20)
when _shamts_oh_21_T_4 :
node _shamts_oh_21_next_T = dshl(shamts_oh[20], UInt<1>(0h1))
connect shamts_oh_21_next, _shamts_oh_21_next_T
connect shamts_oh[21], shamts_oh_21_next
node _will_be_valid_T = eq(_WIRE.exception, UInt<1>(0h0))
node _will_be_valid_T_1 = and(io.dis_uops[0].valid, _will_be_valid_T)
node _will_be_valid_T_2 = eq(_WIRE.is_fence, UInt<1>(0h0))
node _will_be_valid_T_3 = and(_will_be_valid_T_1, _will_be_valid_T_2)
node _will_be_valid_T_4 = eq(_WIRE.is_fencei, UInt<1>(0h0))
node will_be_valid_20 = and(_will_be_valid_T_3, _will_be_valid_T_4)
node _will_be_valid_T_5 = eq(_WIRE_1.exception, UInt<1>(0h0))
node _will_be_valid_T_6 = and(io.dis_uops[1].valid, _will_be_valid_T_5)
node _will_be_valid_T_7 = eq(_WIRE_1.is_fence, UInt<1>(0h0))
node _will_be_valid_T_8 = and(_will_be_valid_T_6, _will_be_valid_T_7)
node _will_be_valid_T_9 = eq(_WIRE_1.is_fencei, UInt<1>(0h0))
node will_be_valid_21 = and(_will_be_valid_T_8, _will_be_valid_T_9)
connect issue_slots[0].in_uop.valid, UInt<1>(0h0)
connect issue_slots[0].in_uop.bits.debug_tsrc, issue_slots[1].out_uop.debug_tsrc
connect issue_slots[0].in_uop.bits.debug_fsrc, issue_slots[1].out_uop.debug_fsrc
connect issue_slots[0].in_uop.bits.bp_xcpt_if, issue_slots[1].out_uop.bp_xcpt_if
connect issue_slots[0].in_uop.bits.bp_debug_if, issue_slots[1].out_uop.bp_debug_if
connect issue_slots[0].in_uop.bits.xcpt_ma_if, issue_slots[1].out_uop.xcpt_ma_if
connect issue_slots[0].in_uop.bits.xcpt_ae_if, issue_slots[1].out_uop.xcpt_ae_if
connect issue_slots[0].in_uop.bits.xcpt_pf_if, issue_slots[1].out_uop.xcpt_pf_if
connect issue_slots[0].in_uop.bits.fp_typ, issue_slots[1].out_uop.fp_typ
connect issue_slots[0].in_uop.bits.fp_rm, issue_slots[1].out_uop.fp_rm
connect issue_slots[0].in_uop.bits.fp_val, issue_slots[1].out_uop.fp_val
connect issue_slots[0].in_uop.bits.fcn_op, issue_slots[1].out_uop.fcn_op
connect issue_slots[0].in_uop.bits.fcn_dw, issue_slots[1].out_uop.fcn_dw
connect issue_slots[0].in_uop.bits.frs3_en, issue_slots[1].out_uop.frs3_en
connect issue_slots[0].in_uop.bits.lrs2_rtype, issue_slots[1].out_uop.lrs2_rtype
connect issue_slots[0].in_uop.bits.lrs1_rtype, issue_slots[1].out_uop.lrs1_rtype
connect issue_slots[0].in_uop.bits.dst_rtype, issue_slots[1].out_uop.dst_rtype
connect issue_slots[0].in_uop.bits.lrs3, issue_slots[1].out_uop.lrs3
connect issue_slots[0].in_uop.bits.lrs2, issue_slots[1].out_uop.lrs2
connect issue_slots[0].in_uop.bits.lrs1, issue_slots[1].out_uop.lrs1
connect issue_slots[0].in_uop.bits.ldst, issue_slots[1].out_uop.ldst
connect issue_slots[0].in_uop.bits.ldst_is_rs1, issue_slots[1].out_uop.ldst_is_rs1
connect issue_slots[0].in_uop.bits.csr_cmd, issue_slots[1].out_uop.csr_cmd
connect issue_slots[0].in_uop.bits.flush_on_commit, issue_slots[1].out_uop.flush_on_commit
connect issue_slots[0].in_uop.bits.is_unique, issue_slots[1].out_uop.is_unique
connect issue_slots[0].in_uop.bits.uses_stq, issue_slots[1].out_uop.uses_stq
connect issue_slots[0].in_uop.bits.uses_ldq, issue_slots[1].out_uop.uses_ldq
connect issue_slots[0].in_uop.bits.mem_signed, issue_slots[1].out_uop.mem_signed
connect issue_slots[0].in_uop.bits.mem_size, issue_slots[1].out_uop.mem_size
connect issue_slots[0].in_uop.bits.mem_cmd, issue_slots[1].out_uop.mem_cmd
connect issue_slots[0].in_uop.bits.exc_cause, issue_slots[1].out_uop.exc_cause
connect issue_slots[0].in_uop.bits.exception, issue_slots[1].out_uop.exception
connect issue_slots[0].in_uop.bits.stale_pdst, issue_slots[1].out_uop.stale_pdst
connect issue_slots[0].in_uop.bits.ppred_busy, issue_slots[1].out_uop.ppred_busy
connect issue_slots[0].in_uop.bits.prs3_busy, issue_slots[1].out_uop.prs3_busy
connect issue_slots[0].in_uop.bits.prs2_busy, issue_slots[1].out_uop.prs2_busy
connect issue_slots[0].in_uop.bits.prs1_busy, issue_slots[1].out_uop.prs1_busy
connect issue_slots[0].in_uop.bits.ppred, issue_slots[1].out_uop.ppred
connect issue_slots[0].in_uop.bits.prs3, issue_slots[1].out_uop.prs3
connect issue_slots[0].in_uop.bits.prs2, issue_slots[1].out_uop.prs2
connect issue_slots[0].in_uop.bits.prs1, issue_slots[1].out_uop.prs1
connect issue_slots[0].in_uop.bits.pdst, issue_slots[1].out_uop.pdst
connect issue_slots[0].in_uop.bits.rxq_idx, issue_slots[1].out_uop.rxq_idx
connect issue_slots[0].in_uop.bits.stq_idx, issue_slots[1].out_uop.stq_idx
connect issue_slots[0].in_uop.bits.ldq_idx, issue_slots[1].out_uop.ldq_idx
connect issue_slots[0].in_uop.bits.rob_idx, issue_slots[1].out_uop.rob_idx
connect issue_slots[0].in_uop.bits.fp_ctrl.vec, issue_slots[1].out_uop.fp_ctrl.vec
connect issue_slots[0].in_uop.bits.fp_ctrl.wflags, issue_slots[1].out_uop.fp_ctrl.wflags
connect issue_slots[0].in_uop.bits.fp_ctrl.sqrt, issue_slots[1].out_uop.fp_ctrl.sqrt
connect issue_slots[0].in_uop.bits.fp_ctrl.div, issue_slots[1].out_uop.fp_ctrl.div
connect issue_slots[0].in_uop.bits.fp_ctrl.fma, issue_slots[1].out_uop.fp_ctrl.fma
connect issue_slots[0].in_uop.bits.fp_ctrl.fastpipe, issue_slots[1].out_uop.fp_ctrl.fastpipe
connect issue_slots[0].in_uop.bits.fp_ctrl.toint, issue_slots[1].out_uop.fp_ctrl.toint
connect issue_slots[0].in_uop.bits.fp_ctrl.fromint, issue_slots[1].out_uop.fp_ctrl.fromint
connect issue_slots[0].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[1].out_uop.fp_ctrl.typeTagOut
connect issue_slots[0].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[1].out_uop.fp_ctrl.typeTagIn
connect issue_slots[0].in_uop.bits.fp_ctrl.swap23, issue_slots[1].out_uop.fp_ctrl.swap23
connect issue_slots[0].in_uop.bits.fp_ctrl.swap12, issue_slots[1].out_uop.fp_ctrl.swap12
connect issue_slots[0].in_uop.bits.fp_ctrl.ren3, issue_slots[1].out_uop.fp_ctrl.ren3
connect issue_slots[0].in_uop.bits.fp_ctrl.ren2, issue_slots[1].out_uop.fp_ctrl.ren2
connect issue_slots[0].in_uop.bits.fp_ctrl.ren1, issue_slots[1].out_uop.fp_ctrl.ren1
connect issue_slots[0].in_uop.bits.fp_ctrl.wen, issue_slots[1].out_uop.fp_ctrl.wen
connect issue_slots[0].in_uop.bits.fp_ctrl.ldst, issue_slots[1].out_uop.fp_ctrl.ldst
connect issue_slots[0].in_uop.bits.op2_sel, issue_slots[1].out_uop.op2_sel
connect issue_slots[0].in_uop.bits.op1_sel, issue_slots[1].out_uop.op1_sel
connect issue_slots[0].in_uop.bits.imm_packed, issue_slots[1].out_uop.imm_packed
connect issue_slots[0].in_uop.bits.pimm, issue_slots[1].out_uop.pimm
connect issue_slots[0].in_uop.bits.imm_sel, issue_slots[1].out_uop.imm_sel
connect issue_slots[0].in_uop.bits.imm_rename, issue_slots[1].out_uop.imm_rename
connect issue_slots[0].in_uop.bits.taken, issue_slots[1].out_uop.taken
connect issue_slots[0].in_uop.bits.pc_lob, issue_slots[1].out_uop.pc_lob
connect issue_slots[0].in_uop.bits.edge_inst, issue_slots[1].out_uop.edge_inst
connect issue_slots[0].in_uop.bits.ftq_idx, issue_slots[1].out_uop.ftq_idx
connect issue_slots[0].in_uop.bits.is_mov, issue_slots[1].out_uop.is_mov
connect issue_slots[0].in_uop.bits.is_rocc, issue_slots[1].out_uop.is_rocc
connect issue_slots[0].in_uop.bits.is_sys_pc2epc, issue_slots[1].out_uop.is_sys_pc2epc
connect issue_slots[0].in_uop.bits.is_eret, issue_slots[1].out_uop.is_eret
connect issue_slots[0].in_uop.bits.is_amo, issue_slots[1].out_uop.is_amo
connect issue_slots[0].in_uop.bits.is_sfence, issue_slots[1].out_uop.is_sfence
connect issue_slots[0].in_uop.bits.is_fencei, issue_slots[1].out_uop.is_fencei
connect issue_slots[0].in_uop.bits.is_fence, issue_slots[1].out_uop.is_fence
connect issue_slots[0].in_uop.bits.is_sfb, issue_slots[1].out_uop.is_sfb
connect issue_slots[0].in_uop.bits.br_type, issue_slots[1].out_uop.br_type
connect issue_slots[0].in_uop.bits.br_tag, issue_slots[1].out_uop.br_tag
connect issue_slots[0].in_uop.bits.br_mask, issue_slots[1].out_uop.br_mask
connect issue_slots[0].in_uop.bits.dis_col_sel, issue_slots[1].out_uop.dis_col_sel
connect issue_slots[0].in_uop.bits.iw_p3_bypass_hint, issue_slots[1].out_uop.iw_p3_bypass_hint
connect issue_slots[0].in_uop.bits.iw_p2_bypass_hint, issue_slots[1].out_uop.iw_p2_bypass_hint
connect issue_slots[0].in_uop.bits.iw_p1_bypass_hint, issue_slots[1].out_uop.iw_p1_bypass_hint
connect issue_slots[0].in_uop.bits.iw_p2_speculative_child, issue_slots[1].out_uop.iw_p2_speculative_child
connect issue_slots[0].in_uop.bits.iw_p1_speculative_child, issue_slots[1].out_uop.iw_p1_speculative_child
connect issue_slots[0].in_uop.bits.iw_issued_partial_dgen, issue_slots[1].out_uop.iw_issued_partial_dgen
connect issue_slots[0].in_uop.bits.iw_issued_partial_agen, issue_slots[1].out_uop.iw_issued_partial_agen
connect issue_slots[0].in_uop.bits.iw_issued, issue_slots[1].out_uop.iw_issued
connect issue_slots[0].in_uop.bits.fu_code[0], issue_slots[1].out_uop.fu_code[0]
connect issue_slots[0].in_uop.bits.fu_code[1], issue_slots[1].out_uop.fu_code[1]
connect issue_slots[0].in_uop.bits.fu_code[2], issue_slots[1].out_uop.fu_code[2]
connect issue_slots[0].in_uop.bits.fu_code[3], issue_slots[1].out_uop.fu_code[3]
connect issue_slots[0].in_uop.bits.fu_code[4], issue_slots[1].out_uop.fu_code[4]
connect issue_slots[0].in_uop.bits.fu_code[5], issue_slots[1].out_uop.fu_code[5]
connect issue_slots[0].in_uop.bits.fu_code[6], issue_slots[1].out_uop.fu_code[6]
connect issue_slots[0].in_uop.bits.fu_code[7], issue_slots[1].out_uop.fu_code[7]
connect issue_slots[0].in_uop.bits.fu_code[8], issue_slots[1].out_uop.fu_code[8]
connect issue_slots[0].in_uop.bits.fu_code[9], issue_slots[1].out_uop.fu_code[9]
connect issue_slots[0].in_uop.bits.iq_type[0], issue_slots[1].out_uop.iq_type[0]
connect issue_slots[0].in_uop.bits.iq_type[1], issue_slots[1].out_uop.iq_type[1]
connect issue_slots[0].in_uop.bits.iq_type[2], issue_slots[1].out_uop.iq_type[2]
connect issue_slots[0].in_uop.bits.iq_type[3], issue_slots[1].out_uop.iq_type[3]
connect issue_slots[0].in_uop.bits.debug_pc, issue_slots[1].out_uop.debug_pc
connect issue_slots[0].in_uop.bits.is_rvc, issue_slots[1].out_uop.is_rvc
connect issue_slots[0].in_uop.bits.debug_inst, issue_slots[1].out_uop.debug_inst
connect issue_slots[0].in_uop.bits.inst, issue_slots[1].out_uop.inst
node _T_162 = eq(shamts_oh[1], UInt<1>(0h1))
when _T_162 :
connect issue_slots[0].in_uop.valid, issue_slots[1].will_be_valid
connect issue_slots[0].in_uop.bits.debug_tsrc, issue_slots[1].out_uop.debug_tsrc
connect issue_slots[0].in_uop.bits.debug_fsrc, issue_slots[1].out_uop.debug_fsrc
connect issue_slots[0].in_uop.bits.bp_xcpt_if, issue_slots[1].out_uop.bp_xcpt_if
connect issue_slots[0].in_uop.bits.bp_debug_if, issue_slots[1].out_uop.bp_debug_if
connect issue_slots[0].in_uop.bits.xcpt_ma_if, issue_slots[1].out_uop.xcpt_ma_if
connect issue_slots[0].in_uop.bits.xcpt_ae_if, issue_slots[1].out_uop.xcpt_ae_if
connect issue_slots[0].in_uop.bits.xcpt_pf_if, issue_slots[1].out_uop.xcpt_pf_if
connect issue_slots[0].in_uop.bits.fp_typ, issue_slots[1].out_uop.fp_typ
connect issue_slots[0].in_uop.bits.fp_rm, issue_slots[1].out_uop.fp_rm
connect issue_slots[0].in_uop.bits.fp_val, issue_slots[1].out_uop.fp_val
connect issue_slots[0].in_uop.bits.fcn_op, issue_slots[1].out_uop.fcn_op
connect issue_slots[0].in_uop.bits.fcn_dw, issue_slots[1].out_uop.fcn_dw
connect issue_slots[0].in_uop.bits.frs3_en, issue_slots[1].out_uop.frs3_en
connect issue_slots[0].in_uop.bits.lrs2_rtype, issue_slots[1].out_uop.lrs2_rtype
connect issue_slots[0].in_uop.bits.lrs1_rtype, issue_slots[1].out_uop.lrs1_rtype
connect issue_slots[0].in_uop.bits.dst_rtype, issue_slots[1].out_uop.dst_rtype
connect issue_slots[0].in_uop.bits.lrs3, issue_slots[1].out_uop.lrs3
connect issue_slots[0].in_uop.bits.lrs2, issue_slots[1].out_uop.lrs2
connect issue_slots[0].in_uop.bits.lrs1, issue_slots[1].out_uop.lrs1
connect issue_slots[0].in_uop.bits.ldst, issue_slots[1].out_uop.ldst
connect issue_slots[0].in_uop.bits.ldst_is_rs1, issue_slots[1].out_uop.ldst_is_rs1
connect issue_slots[0].in_uop.bits.csr_cmd, issue_slots[1].out_uop.csr_cmd
connect issue_slots[0].in_uop.bits.flush_on_commit, issue_slots[1].out_uop.flush_on_commit
connect issue_slots[0].in_uop.bits.is_unique, issue_slots[1].out_uop.is_unique
connect issue_slots[0].in_uop.bits.uses_stq, issue_slots[1].out_uop.uses_stq
connect issue_slots[0].in_uop.bits.uses_ldq, issue_slots[1].out_uop.uses_ldq
connect issue_slots[0].in_uop.bits.mem_signed, issue_slots[1].out_uop.mem_signed
connect issue_slots[0].in_uop.bits.mem_size, issue_slots[1].out_uop.mem_size
connect issue_slots[0].in_uop.bits.mem_cmd, issue_slots[1].out_uop.mem_cmd
connect issue_slots[0].in_uop.bits.exc_cause, issue_slots[1].out_uop.exc_cause
connect issue_slots[0].in_uop.bits.exception, issue_slots[1].out_uop.exception
connect issue_slots[0].in_uop.bits.stale_pdst, issue_slots[1].out_uop.stale_pdst
connect issue_slots[0].in_uop.bits.ppred_busy, issue_slots[1].out_uop.ppred_busy
connect issue_slots[0].in_uop.bits.prs3_busy, issue_slots[1].out_uop.prs3_busy
connect issue_slots[0].in_uop.bits.prs2_busy, issue_slots[1].out_uop.prs2_busy
connect issue_slots[0].in_uop.bits.prs1_busy, issue_slots[1].out_uop.prs1_busy
connect issue_slots[0].in_uop.bits.ppred, issue_slots[1].out_uop.ppred
connect issue_slots[0].in_uop.bits.prs3, issue_slots[1].out_uop.prs3
connect issue_slots[0].in_uop.bits.prs2, issue_slots[1].out_uop.prs2
connect issue_slots[0].in_uop.bits.prs1, issue_slots[1].out_uop.prs1
connect issue_slots[0].in_uop.bits.pdst, issue_slots[1].out_uop.pdst
connect issue_slots[0].in_uop.bits.rxq_idx, issue_slots[1].out_uop.rxq_idx
connect issue_slots[0].in_uop.bits.stq_idx, issue_slots[1].out_uop.stq_idx
connect issue_slots[0].in_uop.bits.ldq_idx, issue_slots[1].out_uop.ldq_idx
connect issue_slots[0].in_uop.bits.rob_idx, issue_slots[1].out_uop.rob_idx
connect issue_slots[0].in_uop.bits.fp_ctrl.vec, issue_slots[1].out_uop.fp_ctrl.vec
connect issue_slots[0].in_uop.bits.fp_ctrl.wflags, issue_slots[1].out_uop.fp_ctrl.wflags
connect issue_slots[0].in_uop.bits.fp_ctrl.sqrt, issue_slots[1].out_uop.fp_ctrl.sqrt
connect issue_slots[0].in_uop.bits.fp_ctrl.div, issue_slots[1].out_uop.fp_ctrl.div
connect issue_slots[0].in_uop.bits.fp_ctrl.fma, issue_slots[1].out_uop.fp_ctrl.fma
connect issue_slots[0].in_uop.bits.fp_ctrl.fastpipe, issue_slots[1].out_uop.fp_ctrl.fastpipe
connect issue_slots[0].in_uop.bits.fp_ctrl.toint, issue_slots[1].out_uop.fp_ctrl.toint
connect issue_slots[0].in_uop.bits.fp_ctrl.fromint, issue_slots[1].out_uop.fp_ctrl.fromint
connect issue_slots[0].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[1].out_uop.fp_ctrl.typeTagOut
connect issue_slots[0].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[1].out_uop.fp_ctrl.typeTagIn
connect issue_slots[0].in_uop.bits.fp_ctrl.swap23, issue_slots[1].out_uop.fp_ctrl.swap23
connect issue_slots[0].in_uop.bits.fp_ctrl.swap12, issue_slots[1].out_uop.fp_ctrl.swap12
connect issue_slots[0].in_uop.bits.fp_ctrl.ren3, issue_slots[1].out_uop.fp_ctrl.ren3
connect issue_slots[0].in_uop.bits.fp_ctrl.ren2, issue_slots[1].out_uop.fp_ctrl.ren2
connect issue_slots[0].in_uop.bits.fp_ctrl.ren1, issue_slots[1].out_uop.fp_ctrl.ren1
connect issue_slots[0].in_uop.bits.fp_ctrl.wen, issue_slots[1].out_uop.fp_ctrl.wen
connect issue_slots[0].in_uop.bits.fp_ctrl.ldst, issue_slots[1].out_uop.fp_ctrl.ldst
connect issue_slots[0].in_uop.bits.op2_sel, issue_slots[1].out_uop.op2_sel
connect issue_slots[0].in_uop.bits.op1_sel, issue_slots[1].out_uop.op1_sel
connect issue_slots[0].in_uop.bits.imm_packed, issue_slots[1].out_uop.imm_packed
connect issue_slots[0].in_uop.bits.pimm, issue_slots[1].out_uop.pimm
connect issue_slots[0].in_uop.bits.imm_sel, issue_slots[1].out_uop.imm_sel
connect issue_slots[0].in_uop.bits.imm_rename, issue_slots[1].out_uop.imm_rename
connect issue_slots[0].in_uop.bits.taken, issue_slots[1].out_uop.taken
connect issue_slots[0].in_uop.bits.pc_lob, issue_slots[1].out_uop.pc_lob
connect issue_slots[0].in_uop.bits.edge_inst, issue_slots[1].out_uop.edge_inst
connect issue_slots[0].in_uop.bits.ftq_idx, issue_slots[1].out_uop.ftq_idx
connect issue_slots[0].in_uop.bits.is_mov, issue_slots[1].out_uop.is_mov
connect issue_slots[0].in_uop.bits.is_rocc, issue_slots[1].out_uop.is_rocc
connect issue_slots[0].in_uop.bits.is_sys_pc2epc, issue_slots[1].out_uop.is_sys_pc2epc
connect issue_slots[0].in_uop.bits.is_eret, issue_slots[1].out_uop.is_eret
connect issue_slots[0].in_uop.bits.is_amo, issue_slots[1].out_uop.is_amo
connect issue_slots[0].in_uop.bits.is_sfence, issue_slots[1].out_uop.is_sfence
connect issue_slots[0].in_uop.bits.is_fencei, issue_slots[1].out_uop.is_fencei
connect issue_slots[0].in_uop.bits.is_fence, issue_slots[1].out_uop.is_fence
connect issue_slots[0].in_uop.bits.is_sfb, issue_slots[1].out_uop.is_sfb
connect issue_slots[0].in_uop.bits.br_type, issue_slots[1].out_uop.br_type
connect issue_slots[0].in_uop.bits.br_tag, issue_slots[1].out_uop.br_tag
connect issue_slots[0].in_uop.bits.br_mask, issue_slots[1].out_uop.br_mask
connect issue_slots[0].in_uop.bits.dis_col_sel, issue_slots[1].out_uop.dis_col_sel
connect issue_slots[0].in_uop.bits.iw_p3_bypass_hint, issue_slots[1].out_uop.iw_p3_bypass_hint
connect issue_slots[0].in_uop.bits.iw_p2_bypass_hint, issue_slots[1].out_uop.iw_p2_bypass_hint
connect issue_slots[0].in_uop.bits.iw_p1_bypass_hint, issue_slots[1].out_uop.iw_p1_bypass_hint
connect issue_slots[0].in_uop.bits.iw_p2_speculative_child, issue_slots[1].out_uop.iw_p2_speculative_child
connect issue_slots[0].in_uop.bits.iw_p1_speculative_child, issue_slots[1].out_uop.iw_p1_speculative_child
connect issue_slots[0].in_uop.bits.iw_issued_partial_dgen, issue_slots[1].out_uop.iw_issued_partial_dgen
connect issue_slots[0].in_uop.bits.iw_issued_partial_agen, issue_slots[1].out_uop.iw_issued_partial_agen
connect issue_slots[0].in_uop.bits.iw_issued, issue_slots[1].out_uop.iw_issued
connect issue_slots[0].in_uop.bits.fu_code[0], issue_slots[1].out_uop.fu_code[0]
connect issue_slots[0].in_uop.bits.fu_code[1], issue_slots[1].out_uop.fu_code[1]
connect issue_slots[0].in_uop.bits.fu_code[2], issue_slots[1].out_uop.fu_code[2]
connect issue_slots[0].in_uop.bits.fu_code[3], issue_slots[1].out_uop.fu_code[3]
connect issue_slots[0].in_uop.bits.fu_code[4], issue_slots[1].out_uop.fu_code[4]
connect issue_slots[0].in_uop.bits.fu_code[5], issue_slots[1].out_uop.fu_code[5]
connect issue_slots[0].in_uop.bits.fu_code[6], issue_slots[1].out_uop.fu_code[6]
connect issue_slots[0].in_uop.bits.fu_code[7], issue_slots[1].out_uop.fu_code[7]
connect issue_slots[0].in_uop.bits.fu_code[8], issue_slots[1].out_uop.fu_code[8]
connect issue_slots[0].in_uop.bits.fu_code[9], issue_slots[1].out_uop.fu_code[9]
connect issue_slots[0].in_uop.bits.iq_type[0], issue_slots[1].out_uop.iq_type[0]
connect issue_slots[0].in_uop.bits.iq_type[1], issue_slots[1].out_uop.iq_type[1]
connect issue_slots[0].in_uop.bits.iq_type[2], issue_slots[1].out_uop.iq_type[2]
connect issue_slots[0].in_uop.bits.iq_type[3], issue_slots[1].out_uop.iq_type[3]
connect issue_slots[0].in_uop.bits.debug_pc, issue_slots[1].out_uop.debug_pc
connect issue_slots[0].in_uop.bits.is_rvc, issue_slots[1].out_uop.is_rvc
connect issue_slots[0].in_uop.bits.debug_inst, issue_slots[1].out_uop.debug_inst
connect issue_slots[0].in_uop.bits.inst, issue_slots[1].out_uop.inst
node _T_163 = eq(shamts_oh[2], UInt<2>(0h2))
when _T_163 :
connect issue_slots[0].in_uop.valid, issue_slots[2].will_be_valid
connect issue_slots[0].in_uop.bits.debug_tsrc, issue_slots[2].out_uop.debug_tsrc
connect issue_slots[0].in_uop.bits.debug_fsrc, issue_slots[2].out_uop.debug_fsrc
connect issue_slots[0].in_uop.bits.bp_xcpt_if, issue_slots[2].out_uop.bp_xcpt_if
connect issue_slots[0].in_uop.bits.bp_debug_if, issue_slots[2].out_uop.bp_debug_if
connect issue_slots[0].in_uop.bits.xcpt_ma_if, issue_slots[2].out_uop.xcpt_ma_if
connect issue_slots[0].in_uop.bits.xcpt_ae_if, issue_slots[2].out_uop.xcpt_ae_if
connect issue_slots[0].in_uop.bits.xcpt_pf_if, issue_slots[2].out_uop.xcpt_pf_if
connect issue_slots[0].in_uop.bits.fp_typ, issue_slots[2].out_uop.fp_typ
connect issue_slots[0].in_uop.bits.fp_rm, issue_slots[2].out_uop.fp_rm
connect issue_slots[0].in_uop.bits.fp_val, issue_slots[2].out_uop.fp_val
connect issue_slots[0].in_uop.bits.fcn_op, issue_slots[2].out_uop.fcn_op
connect issue_slots[0].in_uop.bits.fcn_dw, issue_slots[2].out_uop.fcn_dw
connect issue_slots[0].in_uop.bits.frs3_en, issue_slots[2].out_uop.frs3_en
connect issue_slots[0].in_uop.bits.lrs2_rtype, issue_slots[2].out_uop.lrs2_rtype
connect issue_slots[0].in_uop.bits.lrs1_rtype, issue_slots[2].out_uop.lrs1_rtype
connect issue_slots[0].in_uop.bits.dst_rtype, issue_slots[2].out_uop.dst_rtype
connect issue_slots[0].in_uop.bits.lrs3, issue_slots[2].out_uop.lrs3
connect issue_slots[0].in_uop.bits.lrs2, issue_slots[2].out_uop.lrs2
connect issue_slots[0].in_uop.bits.lrs1, issue_slots[2].out_uop.lrs1
connect issue_slots[0].in_uop.bits.ldst, issue_slots[2].out_uop.ldst
connect issue_slots[0].in_uop.bits.ldst_is_rs1, issue_slots[2].out_uop.ldst_is_rs1
connect issue_slots[0].in_uop.bits.csr_cmd, issue_slots[2].out_uop.csr_cmd
connect issue_slots[0].in_uop.bits.flush_on_commit, issue_slots[2].out_uop.flush_on_commit
connect issue_slots[0].in_uop.bits.is_unique, issue_slots[2].out_uop.is_unique
connect issue_slots[0].in_uop.bits.uses_stq, issue_slots[2].out_uop.uses_stq
connect issue_slots[0].in_uop.bits.uses_ldq, issue_slots[2].out_uop.uses_ldq
connect issue_slots[0].in_uop.bits.mem_signed, issue_slots[2].out_uop.mem_signed
connect issue_slots[0].in_uop.bits.mem_size, issue_slots[2].out_uop.mem_size
connect issue_slots[0].in_uop.bits.mem_cmd, issue_slots[2].out_uop.mem_cmd
connect issue_slots[0].in_uop.bits.exc_cause, issue_slots[2].out_uop.exc_cause
connect issue_slots[0].in_uop.bits.exception, issue_slots[2].out_uop.exception
connect issue_slots[0].in_uop.bits.stale_pdst, issue_slots[2].out_uop.stale_pdst
connect issue_slots[0].in_uop.bits.ppred_busy, issue_slots[2].out_uop.ppred_busy
connect issue_slots[0].in_uop.bits.prs3_busy, issue_slots[2].out_uop.prs3_busy
connect issue_slots[0].in_uop.bits.prs2_busy, issue_slots[2].out_uop.prs2_busy
connect issue_slots[0].in_uop.bits.prs1_busy, issue_slots[2].out_uop.prs1_busy
connect issue_slots[0].in_uop.bits.ppred, issue_slots[2].out_uop.ppred
connect issue_slots[0].in_uop.bits.prs3, issue_slots[2].out_uop.prs3
connect issue_slots[0].in_uop.bits.prs2, issue_slots[2].out_uop.prs2
connect issue_slots[0].in_uop.bits.prs1, issue_slots[2].out_uop.prs1
connect issue_slots[0].in_uop.bits.pdst, issue_slots[2].out_uop.pdst
connect issue_slots[0].in_uop.bits.rxq_idx, issue_slots[2].out_uop.rxq_idx
connect issue_slots[0].in_uop.bits.stq_idx, issue_slots[2].out_uop.stq_idx
connect issue_slots[0].in_uop.bits.ldq_idx, issue_slots[2].out_uop.ldq_idx
connect issue_slots[0].in_uop.bits.rob_idx, issue_slots[2].out_uop.rob_idx
connect issue_slots[0].in_uop.bits.fp_ctrl.vec, issue_slots[2].out_uop.fp_ctrl.vec
connect issue_slots[0].in_uop.bits.fp_ctrl.wflags, issue_slots[2].out_uop.fp_ctrl.wflags
connect issue_slots[0].in_uop.bits.fp_ctrl.sqrt, issue_slots[2].out_uop.fp_ctrl.sqrt
connect issue_slots[0].in_uop.bits.fp_ctrl.div, issue_slots[2].out_uop.fp_ctrl.div
connect issue_slots[0].in_uop.bits.fp_ctrl.fma, issue_slots[2].out_uop.fp_ctrl.fma
connect issue_slots[0].in_uop.bits.fp_ctrl.fastpipe, issue_slots[2].out_uop.fp_ctrl.fastpipe
connect issue_slots[0].in_uop.bits.fp_ctrl.toint, issue_slots[2].out_uop.fp_ctrl.toint
connect issue_slots[0].in_uop.bits.fp_ctrl.fromint, issue_slots[2].out_uop.fp_ctrl.fromint
connect issue_slots[0].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[2].out_uop.fp_ctrl.typeTagOut
connect issue_slots[0].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[2].out_uop.fp_ctrl.typeTagIn
connect issue_slots[0].in_uop.bits.fp_ctrl.swap23, issue_slots[2].out_uop.fp_ctrl.swap23
connect issue_slots[0].in_uop.bits.fp_ctrl.swap12, issue_slots[2].out_uop.fp_ctrl.swap12
connect issue_slots[0].in_uop.bits.fp_ctrl.ren3, issue_slots[2].out_uop.fp_ctrl.ren3
connect issue_slots[0].in_uop.bits.fp_ctrl.ren2, issue_slots[2].out_uop.fp_ctrl.ren2
connect issue_slots[0].in_uop.bits.fp_ctrl.ren1, issue_slots[2].out_uop.fp_ctrl.ren1
connect issue_slots[0].in_uop.bits.fp_ctrl.wen, issue_slots[2].out_uop.fp_ctrl.wen
connect issue_slots[0].in_uop.bits.fp_ctrl.ldst, issue_slots[2].out_uop.fp_ctrl.ldst
connect issue_slots[0].in_uop.bits.op2_sel, issue_slots[2].out_uop.op2_sel
connect issue_slots[0].in_uop.bits.op1_sel, issue_slots[2].out_uop.op1_sel
connect issue_slots[0].in_uop.bits.imm_packed, issue_slots[2].out_uop.imm_packed
connect issue_slots[0].in_uop.bits.pimm, issue_slots[2].out_uop.pimm
connect issue_slots[0].in_uop.bits.imm_sel, issue_slots[2].out_uop.imm_sel
connect issue_slots[0].in_uop.bits.imm_rename, issue_slots[2].out_uop.imm_rename
connect issue_slots[0].in_uop.bits.taken, issue_slots[2].out_uop.taken
connect issue_slots[0].in_uop.bits.pc_lob, issue_slots[2].out_uop.pc_lob
connect issue_slots[0].in_uop.bits.edge_inst, issue_slots[2].out_uop.edge_inst
connect issue_slots[0].in_uop.bits.ftq_idx, issue_slots[2].out_uop.ftq_idx
connect issue_slots[0].in_uop.bits.is_mov, issue_slots[2].out_uop.is_mov
connect issue_slots[0].in_uop.bits.is_rocc, issue_slots[2].out_uop.is_rocc
connect issue_slots[0].in_uop.bits.is_sys_pc2epc, issue_slots[2].out_uop.is_sys_pc2epc
connect issue_slots[0].in_uop.bits.is_eret, issue_slots[2].out_uop.is_eret
connect issue_slots[0].in_uop.bits.is_amo, issue_slots[2].out_uop.is_amo
connect issue_slots[0].in_uop.bits.is_sfence, issue_slots[2].out_uop.is_sfence
connect issue_slots[0].in_uop.bits.is_fencei, issue_slots[2].out_uop.is_fencei
connect issue_slots[0].in_uop.bits.is_fence, issue_slots[2].out_uop.is_fence
connect issue_slots[0].in_uop.bits.is_sfb, issue_slots[2].out_uop.is_sfb
connect issue_slots[0].in_uop.bits.br_type, issue_slots[2].out_uop.br_type
connect issue_slots[0].in_uop.bits.br_tag, issue_slots[2].out_uop.br_tag
connect issue_slots[0].in_uop.bits.br_mask, issue_slots[2].out_uop.br_mask
connect issue_slots[0].in_uop.bits.dis_col_sel, issue_slots[2].out_uop.dis_col_sel
connect issue_slots[0].in_uop.bits.iw_p3_bypass_hint, issue_slots[2].out_uop.iw_p3_bypass_hint
connect issue_slots[0].in_uop.bits.iw_p2_bypass_hint, issue_slots[2].out_uop.iw_p2_bypass_hint
connect issue_slots[0].in_uop.bits.iw_p1_bypass_hint, issue_slots[2].out_uop.iw_p1_bypass_hint
connect issue_slots[0].in_uop.bits.iw_p2_speculative_child, issue_slots[2].out_uop.iw_p2_speculative_child
connect issue_slots[0].in_uop.bits.iw_p1_speculative_child, issue_slots[2].out_uop.iw_p1_speculative_child
connect issue_slots[0].in_uop.bits.iw_issued_partial_dgen, issue_slots[2].out_uop.iw_issued_partial_dgen
connect issue_slots[0].in_uop.bits.iw_issued_partial_agen, issue_slots[2].out_uop.iw_issued_partial_agen
connect issue_slots[0].in_uop.bits.iw_issued, issue_slots[2].out_uop.iw_issued
connect issue_slots[0].in_uop.bits.fu_code[0], issue_slots[2].out_uop.fu_code[0]
connect issue_slots[0].in_uop.bits.fu_code[1], issue_slots[2].out_uop.fu_code[1]
connect issue_slots[0].in_uop.bits.fu_code[2], issue_slots[2].out_uop.fu_code[2]
connect issue_slots[0].in_uop.bits.fu_code[3], issue_slots[2].out_uop.fu_code[3]
connect issue_slots[0].in_uop.bits.fu_code[4], issue_slots[2].out_uop.fu_code[4]
connect issue_slots[0].in_uop.bits.fu_code[5], issue_slots[2].out_uop.fu_code[5]
connect issue_slots[0].in_uop.bits.fu_code[6], issue_slots[2].out_uop.fu_code[6]
connect issue_slots[0].in_uop.bits.fu_code[7], issue_slots[2].out_uop.fu_code[7]
connect issue_slots[0].in_uop.bits.fu_code[8], issue_slots[2].out_uop.fu_code[8]
connect issue_slots[0].in_uop.bits.fu_code[9], issue_slots[2].out_uop.fu_code[9]
connect issue_slots[0].in_uop.bits.iq_type[0], issue_slots[2].out_uop.iq_type[0]
connect issue_slots[0].in_uop.bits.iq_type[1], issue_slots[2].out_uop.iq_type[1]
connect issue_slots[0].in_uop.bits.iq_type[2], issue_slots[2].out_uop.iq_type[2]
connect issue_slots[0].in_uop.bits.iq_type[3], issue_slots[2].out_uop.iq_type[3]
connect issue_slots[0].in_uop.bits.debug_pc, issue_slots[2].out_uop.debug_pc
connect issue_slots[0].in_uop.bits.is_rvc, issue_slots[2].out_uop.is_rvc
connect issue_slots[0].in_uop.bits.debug_inst, issue_slots[2].out_uop.debug_inst
connect issue_slots[0].in_uop.bits.inst, issue_slots[2].out_uop.inst
node _issue_slots_0_clear_T = neq(shamts_oh[0], UInt<1>(0h0))
connect issue_slots[0].clear, _issue_slots_0_clear_T
connect issue_slots[1].in_uop.valid, UInt<1>(0h0)
connect issue_slots[1].in_uop.bits.debug_tsrc, issue_slots[2].out_uop.debug_tsrc
connect issue_slots[1].in_uop.bits.debug_fsrc, issue_slots[2].out_uop.debug_fsrc
connect issue_slots[1].in_uop.bits.bp_xcpt_if, issue_slots[2].out_uop.bp_xcpt_if
connect issue_slots[1].in_uop.bits.bp_debug_if, issue_slots[2].out_uop.bp_debug_if
connect issue_slots[1].in_uop.bits.xcpt_ma_if, issue_slots[2].out_uop.xcpt_ma_if
connect issue_slots[1].in_uop.bits.xcpt_ae_if, issue_slots[2].out_uop.xcpt_ae_if
connect issue_slots[1].in_uop.bits.xcpt_pf_if, issue_slots[2].out_uop.xcpt_pf_if
connect issue_slots[1].in_uop.bits.fp_typ, issue_slots[2].out_uop.fp_typ
connect issue_slots[1].in_uop.bits.fp_rm, issue_slots[2].out_uop.fp_rm
connect issue_slots[1].in_uop.bits.fp_val, issue_slots[2].out_uop.fp_val
connect issue_slots[1].in_uop.bits.fcn_op, issue_slots[2].out_uop.fcn_op
connect issue_slots[1].in_uop.bits.fcn_dw, issue_slots[2].out_uop.fcn_dw
connect issue_slots[1].in_uop.bits.frs3_en, issue_slots[2].out_uop.frs3_en
connect issue_slots[1].in_uop.bits.lrs2_rtype, issue_slots[2].out_uop.lrs2_rtype
connect issue_slots[1].in_uop.bits.lrs1_rtype, issue_slots[2].out_uop.lrs1_rtype
connect issue_slots[1].in_uop.bits.dst_rtype, issue_slots[2].out_uop.dst_rtype
connect issue_slots[1].in_uop.bits.lrs3, issue_slots[2].out_uop.lrs3
connect issue_slots[1].in_uop.bits.lrs2, issue_slots[2].out_uop.lrs2
connect issue_slots[1].in_uop.bits.lrs1, issue_slots[2].out_uop.lrs1
connect issue_slots[1].in_uop.bits.ldst, issue_slots[2].out_uop.ldst
connect issue_slots[1].in_uop.bits.ldst_is_rs1, issue_slots[2].out_uop.ldst_is_rs1
connect issue_slots[1].in_uop.bits.csr_cmd, issue_slots[2].out_uop.csr_cmd
connect issue_slots[1].in_uop.bits.flush_on_commit, issue_slots[2].out_uop.flush_on_commit
connect issue_slots[1].in_uop.bits.is_unique, issue_slots[2].out_uop.is_unique
connect issue_slots[1].in_uop.bits.uses_stq, issue_slots[2].out_uop.uses_stq
connect issue_slots[1].in_uop.bits.uses_ldq, issue_slots[2].out_uop.uses_ldq
connect issue_slots[1].in_uop.bits.mem_signed, issue_slots[2].out_uop.mem_signed
connect issue_slots[1].in_uop.bits.mem_size, issue_slots[2].out_uop.mem_size
connect issue_slots[1].in_uop.bits.mem_cmd, issue_slots[2].out_uop.mem_cmd
connect issue_slots[1].in_uop.bits.exc_cause, issue_slots[2].out_uop.exc_cause
connect issue_slots[1].in_uop.bits.exception, issue_slots[2].out_uop.exception
connect issue_slots[1].in_uop.bits.stale_pdst, issue_slots[2].out_uop.stale_pdst
connect issue_slots[1].in_uop.bits.ppred_busy, issue_slots[2].out_uop.ppred_busy
connect issue_slots[1].in_uop.bits.prs3_busy, issue_slots[2].out_uop.prs3_busy
connect issue_slots[1].in_uop.bits.prs2_busy, issue_slots[2].out_uop.prs2_busy
connect issue_slots[1].in_uop.bits.prs1_busy, issue_slots[2].out_uop.prs1_busy
connect issue_slots[1].in_uop.bits.ppred, issue_slots[2].out_uop.ppred
connect issue_slots[1].in_uop.bits.prs3, issue_slots[2].out_uop.prs3
connect issue_slots[1].in_uop.bits.prs2, issue_slots[2].out_uop.prs2
connect issue_slots[1].in_uop.bits.prs1, issue_slots[2].out_uop.prs1
connect issue_slots[1].in_uop.bits.pdst, issue_slots[2].out_uop.pdst
connect issue_slots[1].in_uop.bits.rxq_idx, issue_slots[2].out_uop.rxq_idx
connect issue_slots[1].in_uop.bits.stq_idx, issue_slots[2].out_uop.stq_idx
connect issue_slots[1].in_uop.bits.ldq_idx, issue_slots[2].out_uop.ldq_idx
connect issue_slots[1].in_uop.bits.rob_idx, issue_slots[2].out_uop.rob_idx
connect issue_slots[1].in_uop.bits.fp_ctrl.vec, issue_slots[2].out_uop.fp_ctrl.vec
connect issue_slots[1].in_uop.bits.fp_ctrl.wflags, issue_slots[2].out_uop.fp_ctrl.wflags
connect issue_slots[1].in_uop.bits.fp_ctrl.sqrt, issue_slots[2].out_uop.fp_ctrl.sqrt
connect issue_slots[1].in_uop.bits.fp_ctrl.div, issue_slots[2].out_uop.fp_ctrl.div
connect issue_slots[1].in_uop.bits.fp_ctrl.fma, issue_slots[2].out_uop.fp_ctrl.fma
connect issue_slots[1].in_uop.bits.fp_ctrl.fastpipe, issue_slots[2].out_uop.fp_ctrl.fastpipe
connect issue_slots[1].in_uop.bits.fp_ctrl.toint, issue_slots[2].out_uop.fp_ctrl.toint
connect issue_slots[1].in_uop.bits.fp_ctrl.fromint, issue_slots[2].out_uop.fp_ctrl.fromint
connect issue_slots[1].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[2].out_uop.fp_ctrl.typeTagOut
connect issue_slots[1].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[2].out_uop.fp_ctrl.typeTagIn
connect issue_slots[1].in_uop.bits.fp_ctrl.swap23, issue_slots[2].out_uop.fp_ctrl.swap23
connect issue_slots[1].in_uop.bits.fp_ctrl.swap12, issue_slots[2].out_uop.fp_ctrl.swap12
connect issue_slots[1].in_uop.bits.fp_ctrl.ren3, issue_slots[2].out_uop.fp_ctrl.ren3
connect issue_slots[1].in_uop.bits.fp_ctrl.ren2, issue_slots[2].out_uop.fp_ctrl.ren2
connect issue_slots[1].in_uop.bits.fp_ctrl.ren1, issue_slots[2].out_uop.fp_ctrl.ren1
connect issue_slots[1].in_uop.bits.fp_ctrl.wen, issue_slots[2].out_uop.fp_ctrl.wen
connect issue_slots[1].in_uop.bits.fp_ctrl.ldst, issue_slots[2].out_uop.fp_ctrl.ldst
connect issue_slots[1].in_uop.bits.op2_sel, issue_slots[2].out_uop.op2_sel
connect issue_slots[1].in_uop.bits.op1_sel, issue_slots[2].out_uop.op1_sel
connect issue_slots[1].in_uop.bits.imm_packed, issue_slots[2].out_uop.imm_packed
connect issue_slots[1].in_uop.bits.pimm, issue_slots[2].out_uop.pimm
connect issue_slots[1].in_uop.bits.imm_sel, issue_slots[2].out_uop.imm_sel
connect issue_slots[1].in_uop.bits.imm_rename, issue_slots[2].out_uop.imm_rename
connect issue_slots[1].in_uop.bits.taken, issue_slots[2].out_uop.taken
connect issue_slots[1].in_uop.bits.pc_lob, issue_slots[2].out_uop.pc_lob
connect issue_slots[1].in_uop.bits.edge_inst, issue_slots[2].out_uop.edge_inst
connect issue_slots[1].in_uop.bits.ftq_idx, issue_slots[2].out_uop.ftq_idx
connect issue_slots[1].in_uop.bits.is_mov, issue_slots[2].out_uop.is_mov
connect issue_slots[1].in_uop.bits.is_rocc, issue_slots[2].out_uop.is_rocc
connect issue_slots[1].in_uop.bits.is_sys_pc2epc, issue_slots[2].out_uop.is_sys_pc2epc
connect issue_slots[1].in_uop.bits.is_eret, issue_slots[2].out_uop.is_eret
connect issue_slots[1].in_uop.bits.is_amo, issue_slots[2].out_uop.is_amo
connect issue_slots[1].in_uop.bits.is_sfence, issue_slots[2].out_uop.is_sfence
connect issue_slots[1].in_uop.bits.is_fencei, issue_slots[2].out_uop.is_fencei
connect issue_slots[1].in_uop.bits.is_fence, issue_slots[2].out_uop.is_fence
connect issue_slots[1].in_uop.bits.is_sfb, issue_slots[2].out_uop.is_sfb
connect issue_slots[1].in_uop.bits.br_type, issue_slots[2].out_uop.br_type
connect issue_slots[1].in_uop.bits.br_tag, issue_slots[2].out_uop.br_tag
connect issue_slots[1].in_uop.bits.br_mask, issue_slots[2].out_uop.br_mask
connect issue_slots[1].in_uop.bits.dis_col_sel, issue_slots[2].out_uop.dis_col_sel
connect issue_slots[1].in_uop.bits.iw_p3_bypass_hint, issue_slots[2].out_uop.iw_p3_bypass_hint
connect issue_slots[1].in_uop.bits.iw_p2_bypass_hint, issue_slots[2].out_uop.iw_p2_bypass_hint
connect issue_slots[1].in_uop.bits.iw_p1_bypass_hint, issue_slots[2].out_uop.iw_p1_bypass_hint
connect issue_slots[1].in_uop.bits.iw_p2_speculative_child, issue_slots[2].out_uop.iw_p2_speculative_child
connect issue_slots[1].in_uop.bits.iw_p1_speculative_child, issue_slots[2].out_uop.iw_p1_speculative_child
connect issue_slots[1].in_uop.bits.iw_issued_partial_dgen, issue_slots[2].out_uop.iw_issued_partial_dgen
connect issue_slots[1].in_uop.bits.iw_issued_partial_agen, issue_slots[2].out_uop.iw_issued_partial_agen
connect issue_slots[1].in_uop.bits.iw_issued, issue_slots[2].out_uop.iw_issued
connect issue_slots[1].in_uop.bits.fu_code[0], issue_slots[2].out_uop.fu_code[0]
connect issue_slots[1].in_uop.bits.fu_code[1], issue_slots[2].out_uop.fu_code[1]
connect issue_slots[1].in_uop.bits.fu_code[2], issue_slots[2].out_uop.fu_code[2]
connect issue_slots[1].in_uop.bits.fu_code[3], issue_slots[2].out_uop.fu_code[3]
connect issue_slots[1].in_uop.bits.fu_code[4], issue_slots[2].out_uop.fu_code[4]
connect issue_slots[1].in_uop.bits.fu_code[5], issue_slots[2].out_uop.fu_code[5]
connect issue_slots[1].in_uop.bits.fu_code[6], issue_slots[2].out_uop.fu_code[6]
connect issue_slots[1].in_uop.bits.fu_code[7], issue_slots[2].out_uop.fu_code[7]
connect issue_slots[1].in_uop.bits.fu_code[8], issue_slots[2].out_uop.fu_code[8]
connect issue_slots[1].in_uop.bits.fu_code[9], issue_slots[2].out_uop.fu_code[9]
connect issue_slots[1].in_uop.bits.iq_type[0], issue_slots[2].out_uop.iq_type[0]
connect issue_slots[1].in_uop.bits.iq_type[1], issue_slots[2].out_uop.iq_type[1]
connect issue_slots[1].in_uop.bits.iq_type[2], issue_slots[2].out_uop.iq_type[2]
connect issue_slots[1].in_uop.bits.iq_type[3], issue_slots[2].out_uop.iq_type[3]
connect issue_slots[1].in_uop.bits.debug_pc, issue_slots[2].out_uop.debug_pc
connect issue_slots[1].in_uop.bits.is_rvc, issue_slots[2].out_uop.is_rvc
connect issue_slots[1].in_uop.bits.debug_inst, issue_slots[2].out_uop.debug_inst
connect issue_slots[1].in_uop.bits.inst, issue_slots[2].out_uop.inst
node _T_164 = eq(shamts_oh[2], UInt<1>(0h1))
when _T_164 :
connect issue_slots[1].in_uop.valid, issue_slots[2].will_be_valid
connect issue_slots[1].in_uop.bits.debug_tsrc, issue_slots[2].out_uop.debug_tsrc
connect issue_slots[1].in_uop.bits.debug_fsrc, issue_slots[2].out_uop.debug_fsrc
connect issue_slots[1].in_uop.bits.bp_xcpt_if, issue_slots[2].out_uop.bp_xcpt_if
connect issue_slots[1].in_uop.bits.bp_debug_if, issue_slots[2].out_uop.bp_debug_if
connect issue_slots[1].in_uop.bits.xcpt_ma_if, issue_slots[2].out_uop.xcpt_ma_if
connect issue_slots[1].in_uop.bits.xcpt_ae_if, issue_slots[2].out_uop.xcpt_ae_if
connect issue_slots[1].in_uop.bits.xcpt_pf_if, issue_slots[2].out_uop.xcpt_pf_if
connect issue_slots[1].in_uop.bits.fp_typ, issue_slots[2].out_uop.fp_typ
connect issue_slots[1].in_uop.bits.fp_rm, issue_slots[2].out_uop.fp_rm
connect issue_slots[1].in_uop.bits.fp_val, issue_slots[2].out_uop.fp_val
connect issue_slots[1].in_uop.bits.fcn_op, issue_slots[2].out_uop.fcn_op
connect issue_slots[1].in_uop.bits.fcn_dw, issue_slots[2].out_uop.fcn_dw
connect issue_slots[1].in_uop.bits.frs3_en, issue_slots[2].out_uop.frs3_en
connect issue_slots[1].in_uop.bits.lrs2_rtype, issue_slots[2].out_uop.lrs2_rtype
connect issue_slots[1].in_uop.bits.lrs1_rtype, issue_slots[2].out_uop.lrs1_rtype
connect issue_slots[1].in_uop.bits.dst_rtype, issue_slots[2].out_uop.dst_rtype
connect issue_slots[1].in_uop.bits.lrs3, issue_slots[2].out_uop.lrs3
connect issue_slots[1].in_uop.bits.lrs2, issue_slots[2].out_uop.lrs2
connect issue_slots[1].in_uop.bits.lrs1, issue_slots[2].out_uop.lrs1
connect issue_slots[1].in_uop.bits.ldst, issue_slots[2].out_uop.ldst
connect issue_slots[1].in_uop.bits.ldst_is_rs1, issue_slots[2].out_uop.ldst_is_rs1
connect issue_slots[1].in_uop.bits.csr_cmd, issue_slots[2].out_uop.csr_cmd
connect issue_slots[1].in_uop.bits.flush_on_commit, issue_slots[2].out_uop.flush_on_commit
connect issue_slots[1].in_uop.bits.is_unique, issue_slots[2].out_uop.is_unique
connect issue_slots[1].in_uop.bits.uses_stq, issue_slots[2].out_uop.uses_stq
connect issue_slots[1].in_uop.bits.uses_ldq, issue_slots[2].out_uop.uses_ldq
connect issue_slots[1].in_uop.bits.mem_signed, issue_slots[2].out_uop.mem_signed
connect issue_slots[1].in_uop.bits.mem_size, issue_slots[2].out_uop.mem_size
connect issue_slots[1].in_uop.bits.mem_cmd, issue_slots[2].out_uop.mem_cmd
connect issue_slots[1].in_uop.bits.exc_cause, issue_slots[2].out_uop.exc_cause
connect issue_slots[1].in_uop.bits.exception, issue_slots[2].out_uop.exception
connect issue_slots[1].in_uop.bits.stale_pdst, issue_slots[2].out_uop.stale_pdst
connect issue_slots[1].in_uop.bits.ppred_busy, issue_slots[2].out_uop.ppred_busy
connect issue_slots[1].in_uop.bits.prs3_busy, issue_slots[2].out_uop.prs3_busy
connect issue_slots[1].in_uop.bits.prs2_busy, issue_slots[2].out_uop.prs2_busy
connect issue_slots[1].in_uop.bits.prs1_busy, issue_slots[2].out_uop.prs1_busy
connect issue_slots[1].in_uop.bits.ppred, issue_slots[2].out_uop.ppred
connect issue_slots[1].in_uop.bits.prs3, issue_slots[2].out_uop.prs3
connect issue_slots[1].in_uop.bits.prs2, issue_slots[2].out_uop.prs2
connect issue_slots[1].in_uop.bits.prs1, issue_slots[2].out_uop.prs1
connect issue_slots[1].in_uop.bits.pdst, issue_slots[2].out_uop.pdst
connect issue_slots[1].in_uop.bits.rxq_idx, issue_slots[2].out_uop.rxq_idx
connect issue_slots[1].in_uop.bits.stq_idx, issue_slots[2].out_uop.stq_idx
connect issue_slots[1].in_uop.bits.ldq_idx, issue_slots[2].out_uop.ldq_idx
connect issue_slots[1].in_uop.bits.rob_idx, issue_slots[2].out_uop.rob_idx
connect issue_slots[1].in_uop.bits.fp_ctrl.vec, issue_slots[2].out_uop.fp_ctrl.vec
connect issue_slots[1].in_uop.bits.fp_ctrl.wflags, issue_slots[2].out_uop.fp_ctrl.wflags
connect issue_slots[1].in_uop.bits.fp_ctrl.sqrt, issue_slots[2].out_uop.fp_ctrl.sqrt
connect issue_slots[1].in_uop.bits.fp_ctrl.div, issue_slots[2].out_uop.fp_ctrl.div
connect issue_slots[1].in_uop.bits.fp_ctrl.fma, issue_slots[2].out_uop.fp_ctrl.fma
connect issue_slots[1].in_uop.bits.fp_ctrl.fastpipe, issue_slots[2].out_uop.fp_ctrl.fastpipe
connect issue_slots[1].in_uop.bits.fp_ctrl.toint, issue_slots[2].out_uop.fp_ctrl.toint
connect issue_slots[1].in_uop.bits.fp_ctrl.fromint, issue_slots[2].out_uop.fp_ctrl.fromint
connect issue_slots[1].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[2].out_uop.fp_ctrl.typeTagOut
connect issue_slots[1].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[2].out_uop.fp_ctrl.typeTagIn
connect issue_slots[1].in_uop.bits.fp_ctrl.swap23, issue_slots[2].out_uop.fp_ctrl.swap23
connect issue_slots[1].in_uop.bits.fp_ctrl.swap12, issue_slots[2].out_uop.fp_ctrl.swap12
connect issue_slots[1].in_uop.bits.fp_ctrl.ren3, issue_slots[2].out_uop.fp_ctrl.ren3
connect issue_slots[1].in_uop.bits.fp_ctrl.ren2, issue_slots[2].out_uop.fp_ctrl.ren2
connect issue_slots[1].in_uop.bits.fp_ctrl.ren1, issue_slots[2].out_uop.fp_ctrl.ren1
connect issue_slots[1].in_uop.bits.fp_ctrl.wen, issue_slots[2].out_uop.fp_ctrl.wen
connect issue_slots[1].in_uop.bits.fp_ctrl.ldst, issue_slots[2].out_uop.fp_ctrl.ldst
connect issue_slots[1].in_uop.bits.op2_sel, issue_slots[2].out_uop.op2_sel
connect issue_slots[1].in_uop.bits.op1_sel, issue_slots[2].out_uop.op1_sel
connect issue_slots[1].in_uop.bits.imm_packed, issue_slots[2].out_uop.imm_packed
connect issue_slots[1].in_uop.bits.pimm, issue_slots[2].out_uop.pimm
connect issue_slots[1].in_uop.bits.imm_sel, issue_slots[2].out_uop.imm_sel
connect issue_slots[1].in_uop.bits.imm_rename, issue_slots[2].out_uop.imm_rename
connect issue_slots[1].in_uop.bits.taken, issue_slots[2].out_uop.taken
connect issue_slots[1].in_uop.bits.pc_lob, issue_slots[2].out_uop.pc_lob
connect issue_slots[1].in_uop.bits.edge_inst, issue_slots[2].out_uop.edge_inst
connect issue_slots[1].in_uop.bits.ftq_idx, issue_slots[2].out_uop.ftq_idx
connect issue_slots[1].in_uop.bits.is_mov, issue_slots[2].out_uop.is_mov
connect issue_slots[1].in_uop.bits.is_rocc, issue_slots[2].out_uop.is_rocc
connect issue_slots[1].in_uop.bits.is_sys_pc2epc, issue_slots[2].out_uop.is_sys_pc2epc
connect issue_slots[1].in_uop.bits.is_eret, issue_slots[2].out_uop.is_eret
connect issue_slots[1].in_uop.bits.is_amo, issue_slots[2].out_uop.is_amo
connect issue_slots[1].in_uop.bits.is_sfence, issue_slots[2].out_uop.is_sfence
connect issue_slots[1].in_uop.bits.is_fencei, issue_slots[2].out_uop.is_fencei
connect issue_slots[1].in_uop.bits.is_fence, issue_slots[2].out_uop.is_fence
connect issue_slots[1].in_uop.bits.is_sfb, issue_slots[2].out_uop.is_sfb
connect issue_slots[1].in_uop.bits.br_type, issue_slots[2].out_uop.br_type
connect issue_slots[1].in_uop.bits.br_tag, issue_slots[2].out_uop.br_tag
connect issue_slots[1].in_uop.bits.br_mask, issue_slots[2].out_uop.br_mask
connect issue_slots[1].in_uop.bits.dis_col_sel, issue_slots[2].out_uop.dis_col_sel
connect issue_slots[1].in_uop.bits.iw_p3_bypass_hint, issue_slots[2].out_uop.iw_p3_bypass_hint
connect issue_slots[1].in_uop.bits.iw_p2_bypass_hint, issue_slots[2].out_uop.iw_p2_bypass_hint
connect issue_slots[1].in_uop.bits.iw_p1_bypass_hint, issue_slots[2].out_uop.iw_p1_bypass_hint
connect issue_slots[1].in_uop.bits.iw_p2_speculative_child, issue_slots[2].out_uop.iw_p2_speculative_child
connect issue_slots[1].in_uop.bits.iw_p1_speculative_child, issue_slots[2].out_uop.iw_p1_speculative_child
connect issue_slots[1].in_uop.bits.iw_issued_partial_dgen, issue_slots[2].out_uop.iw_issued_partial_dgen
connect issue_slots[1].in_uop.bits.iw_issued_partial_agen, issue_slots[2].out_uop.iw_issued_partial_agen
connect issue_slots[1].in_uop.bits.iw_issued, issue_slots[2].out_uop.iw_issued
connect issue_slots[1].in_uop.bits.fu_code[0], issue_slots[2].out_uop.fu_code[0]
connect issue_slots[1].in_uop.bits.fu_code[1], issue_slots[2].out_uop.fu_code[1]
connect issue_slots[1].in_uop.bits.fu_code[2], issue_slots[2].out_uop.fu_code[2]
connect issue_slots[1].in_uop.bits.fu_code[3], issue_slots[2].out_uop.fu_code[3]
connect issue_slots[1].in_uop.bits.fu_code[4], issue_slots[2].out_uop.fu_code[4]
connect issue_slots[1].in_uop.bits.fu_code[5], issue_slots[2].out_uop.fu_code[5]
connect issue_slots[1].in_uop.bits.fu_code[6], issue_slots[2].out_uop.fu_code[6]
connect issue_slots[1].in_uop.bits.fu_code[7], issue_slots[2].out_uop.fu_code[7]
connect issue_slots[1].in_uop.bits.fu_code[8], issue_slots[2].out_uop.fu_code[8]
connect issue_slots[1].in_uop.bits.fu_code[9], issue_slots[2].out_uop.fu_code[9]
connect issue_slots[1].in_uop.bits.iq_type[0], issue_slots[2].out_uop.iq_type[0]
connect issue_slots[1].in_uop.bits.iq_type[1], issue_slots[2].out_uop.iq_type[1]
connect issue_slots[1].in_uop.bits.iq_type[2], issue_slots[2].out_uop.iq_type[2]
connect issue_slots[1].in_uop.bits.iq_type[3], issue_slots[2].out_uop.iq_type[3]
connect issue_slots[1].in_uop.bits.debug_pc, issue_slots[2].out_uop.debug_pc
connect issue_slots[1].in_uop.bits.is_rvc, issue_slots[2].out_uop.is_rvc
connect issue_slots[1].in_uop.bits.debug_inst, issue_slots[2].out_uop.debug_inst
connect issue_slots[1].in_uop.bits.inst, issue_slots[2].out_uop.inst
node _T_165 = eq(shamts_oh[3], UInt<2>(0h2))
when _T_165 :
connect issue_slots[1].in_uop.valid, issue_slots[3].will_be_valid
connect issue_slots[1].in_uop.bits.debug_tsrc, issue_slots[3].out_uop.debug_tsrc
connect issue_slots[1].in_uop.bits.debug_fsrc, issue_slots[3].out_uop.debug_fsrc
connect issue_slots[1].in_uop.bits.bp_xcpt_if, issue_slots[3].out_uop.bp_xcpt_if
connect issue_slots[1].in_uop.bits.bp_debug_if, issue_slots[3].out_uop.bp_debug_if
connect issue_slots[1].in_uop.bits.xcpt_ma_if, issue_slots[3].out_uop.xcpt_ma_if
connect issue_slots[1].in_uop.bits.xcpt_ae_if, issue_slots[3].out_uop.xcpt_ae_if
connect issue_slots[1].in_uop.bits.xcpt_pf_if, issue_slots[3].out_uop.xcpt_pf_if
connect issue_slots[1].in_uop.bits.fp_typ, issue_slots[3].out_uop.fp_typ
connect issue_slots[1].in_uop.bits.fp_rm, issue_slots[3].out_uop.fp_rm
connect issue_slots[1].in_uop.bits.fp_val, issue_slots[3].out_uop.fp_val
connect issue_slots[1].in_uop.bits.fcn_op, issue_slots[3].out_uop.fcn_op
connect issue_slots[1].in_uop.bits.fcn_dw, issue_slots[3].out_uop.fcn_dw
connect issue_slots[1].in_uop.bits.frs3_en, issue_slots[3].out_uop.frs3_en
connect issue_slots[1].in_uop.bits.lrs2_rtype, issue_slots[3].out_uop.lrs2_rtype
connect issue_slots[1].in_uop.bits.lrs1_rtype, issue_slots[3].out_uop.lrs1_rtype
connect issue_slots[1].in_uop.bits.dst_rtype, issue_slots[3].out_uop.dst_rtype
connect issue_slots[1].in_uop.bits.lrs3, issue_slots[3].out_uop.lrs3
connect issue_slots[1].in_uop.bits.lrs2, issue_slots[3].out_uop.lrs2
connect issue_slots[1].in_uop.bits.lrs1, issue_slots[3].out_uop.lrs1
connect issue_slots[1].in_uop.bits.ldst, issue_slots[3].out_uop.ldst
connect issue_slots[1].in_uop.bits.ldst_is_rs1, issue_slots[3].out_uop.ldst_is_rs1
connect issue_slots[1].in_uop.bits.csr_cmd, issue_slots[3].out_uop.csr_cmd
connect issue_slots[1].in_uop.bits.flush_on_commit, issue_slots[3].out_uop.flush_on_commit
connect issue_slots[1].in_uop.bits.is_unique, issue_slots[3].out_uop.is_unique
connect issue_slots[1].in_uop.bits.uses_stq, issue_slots[3].out_uop.uses_stq
connect issue_slots[1].in_uop.bits.uses_ldq, issue_slots[3].out_uop.uses_ldq
connect issue_slots[1].in_uop.bits.mem_signed, issue_slots[3].out_uop.mem_signed
connect issue_slots[1].in_uop.bits.mem_size, issue_slots[3].out_uop.mem_size
connect issue_slots[1].in_uop.bits.mem_cmd, issue_slots[3].out_uop.mem_cmd
connect issue_slots[1].in_uop.bits.exc_cause, issue_slots[3].out_uop.exc_cause
connect issue_slots[1].in_uop.bits.exception, issue_slots[3].out_uop.exception
connect issue_slots[1].in_uop.bits.stale_pdst, issue_slots[3].out_uop.stale_pdst
connect issue_slots[1].in_uop.bits.ppred_busy, issue_slots[3].out_uop.ppred_busy
connect issue_slots[1].in_uop.bits.prs3_busy, issue_slots[3].out_uop.prs3_busy
connect issue_slots[1].in_uop.bits.prs2_busy, issue_slots[3].out_uop.prs2_busy
connect issue_slots[1].in_uop.bits.prs1_busy, issue_slots[3].out_uop.prs1_busy
connect issue_slots[1].in_uop.bits.ppred, issue_slots[3].out_uop.ppred
connect issue_slots[1].in_uop.bits.prs3, issue_slots[3].out_uop.prs3
connect issue_slots[1].in_uop.bits.prs2, issue_slots[3].out_uop.prs2
connect issue_slots[1].in_uop.bits.prs1, issue_slots[3].out_uop.prs1
connect issue_slots[1].in_uop.bits.pdst, issue_slots[3].out_uop.pdst
connect issue_slots[1].in_uop.bits.rxq_idx, issue_slots[3].out_uop.rxq_idx
connect issue_slots[1].in_uop.bits.stq_idx, issue_slots[3].out_uop.stq_idx
connect issue_slots[1].in_uop.bits.ldq_idx, issue_slots[3].out_uop.ldq_idx
connect issue_slots[1].in_uop.bits.rob_idx, issue_slots[3].out_uop.rob_idx
connect issue_slots[1].in_uop.bits.fp_ctrl.vec, issue_slots[3].out_uop.fp_ctrl.vec
connect issue_slots[1].in_uop.bits.fp_ctrl.wflags, issue_slots[3].out_uop.fp_ctrl.wflags
connect issue_slots[1].in_uop.bits.fp_ctrl.sqrt, issue_slots[3].out_uop.fp_ctrl.sqrt
connect issue_slots[1].in_uop.bits.fp_ctrl.div, issue_slots[3].out_uop.fp_ctrl.div
connect issue_slots[1].in_uop.bits.fp_ctrl.fma, issue_slots[3].out_uop.fp_ctrl.fma
connect issue_slots[1].in_uop.bits.fp_ctrl.fastpipe, issue_slots[3].out_uop.fp_ctrl.fastpipe
connect issue_slots[1].in_uop.bits.fp_ctrl.toint, issue_slots[3].out_uop.fp_ctrl.toint
connect issue_slots[1].in_uop.bits.fp_ctrl.fromint, issue_slots[3].out_uop.fp_ctrl.fromint
connect issue_slots[1].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[3].out_uop.fp_ctrl.typeTagOut
connect issue_slots[1].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[3].out_uop.fp_ctrl.typeTagIn
connect issue_slots[1].in_uop.bits.fp_ctrl.swap23, issue_slots[3].out_uop.fp_ctrl.swap23
connect issue_slots[1].in_uop.bits.fp_ctrl.swap12, issue_slots[3].out_uop.fp_ctrl.swap12
connect issue_slots[1].in_uop.bits.fp_ctrl.ren3, issue_slots[3].out_uop.fp_ctrl.ren3
connect issue_slots[1].in_uop.bits.fp_ctrl.ren2, issue_slots[3].out_uop.fp_ctrl.ren2
connect issue_slots[1].in_uop.bits.fp_ctrl.ren1, issue_slots[3].out_uop.fp_ctrl.ren1
connect issue_slots[1].in_uop.bits.fp_ctrl.wen, issue_slots[3].out_uop.fp_ctrl.wen
connect issue_slots[1].in_uop.bits.fp_ctrl.ldst, issue_slots[3].out_uop.fp_ctrl.ldst
connect issue_slots[1].in_uop.bits.op2_sel, issue_slots[3].out_uop.op2_sel
connect issue_slots[1].in_uop.bits.op1_sel, issue_slots[3].out_uop.op1_sel
connect issue_slots[1].in_uop.bits.imm_packed, issue_slots[3].out_uop.imm_packed
connect issue_slots[1].in_uop.bits.pimm, issue_slots[3].out_uop.pimm
connect issue_slots[1].in_uop.bits.imm_sel, issue_slots[3].out_uop.imm_sel
connect issue_slots[1].in_uop.bits.imm_rename, issue_slots[3].out_uop.imm_rename
connect issue_slots[1].in_uop.bits.taken, issue_slots[3].out_uop.taken
connect issue_slots[1].in_uop.bits.pc_lob, issue_slots[3].out_uop.pc_lob
connect issue_slots[1].in_uop.bits.edge_inst, issue_slots[3].out_uop.edge_inst
connect issue_slots[1].in_uop.bits.ftq_idx, issue_slots[3].out_uop.ftq_idx
connect issue_slots[1].in_uop.bits.is_mov, issue_slots[3].out_uop.is_mov
connect issue_slots[1].in_uop.bits.is_rocc, issue_slots[3].out_uop.is_rocc
connect issue_slots[1].in_uop.bits.is_sys_pc2epc, issue_slots[3].out_uop.is_sys_pc2epc
connect issue_slots[1].in_uop.bits.is_eret, issue_slots[3].out_uop.is_eret
connect issue_slots[1].in_uop.bits.is_amo, issue_slots[3].out_uop.is_amo
connect issue_slots[1].in_uop.bits.is_sfence, issue_slots[3].out_uop.is_sfence
connect issue_slots[1].in_uop.bits.is_fencei, issue_slots[3].out_uop.is_fencei
connect issue_slots[1].in_uop.bits.is_fence, issue_slots[3].out_uop.is_fence
connect issue_slots[1].in_uop.bits.is_sfb, issue_slots[3].out_uop.is_sfb
connect issue_slots[1].in_uop.bits.br_type, issue_slots[3].out_uop.br_type
connect issue_slots[1].in_uop.bits.br_tag, issue_slots[3].out_uop.br_tag
connect issue_slots[1].in_uop.bits.br_mask, issue_slots[3].out_uop.br_mask
connect issue_slots[1].in_uop.bits.dis_col_sel, issue_slots[3].out_uop.dis_col_sel
connect issue_slots[1].in_uop.bits.iw_p3_bypass_hint, issue_slots[3].out_uop.iw_p3_bypass_hint
connect issue_slots[1].in_uop.bits.iw_p2_bypass_hint, issue_slots[3].out_uop.iw_p2_bypass_hint
connect issue_slots[1].in_uop.bits.iw_p1_bypass_hint, issue_slots[3].out_uop.iw_p1_bypass_hint
connect issue_slots[1].in_uop.bits.iw_p2_speculative_child, issue_slots[3].out_uop.iw_p2_speculative_child
connect issue_slots[1].in_uop.bits.iw_p1_speculative_child, issue_slots[3].out_uop.iw_p1_speculative_child
connect issue_slots[1].in_uop.bits.iw_issued_partial_dgen, issue_slots[3].out_uop.iw_issued_partial_dgen
connect issue_slots[1].in_uop.bits.iw_issued_partial_agen, issue_slots[3].out_uop.iw_issued_partial_agen
connect issue_slots[1].in_uop.bits.iw_issued, issue_slots[3].out_uop.iw_issued
connect issue_slots[1].in_uop.bits.fu_code[0], issue_slots[3].out_uop.fu_code[0]
connect issue_slots[1].in_uop.bits.fu_code[1], issue_slots[3].out_uop.fu_code[1]
connect issue_slots[1].in_uop.bits.fu_code[2], issue_slots[3].out_uop.fu_code[2]
connect issue_slots[1].in_uop.bits.fu_code[3], issue_slots[3].out_uop.fu_code[3]
connect issue_slots[1].in_uop.bits.fu_code[4], issue_slots[3].out_uop.fu_code[4]
connect issue_slots[1].in_uop.bits.fu_code[5], issue_slots[3].out_uop.fu_code[5]
connect issue_slots[1].in_uop.bits.fu_code[6], issue_slots[3].out_uop.fu_code[6]
connect issue_slots[1].in_uop.bits.fu_code[7], issue_slots[3].out_uop.fu_code[7]
connect issue_slots[1].in_uop.bits.fu_code[8], issue_slots[3].out_uop.fu_code[8]
connect issue_slots[1].in_uop.bits.fu_code[9], issue_slots[3].out_uop.fu_code[9]
connect issue_slots[1].in_uop.bits.iq_type[0], issue_slots[3].out_uop.iq_type[0]
connect issue_slots[1].in_uop.bits.iq_type[1], issue_slots[3].out_uop.iq_type[1]
connect issue_slots[1].in_uop.bits.iq_type[2], issue_slots[3].out_uop.iq_type[2]
connect issue_slots[1].in_uop.bits.iq_type[3], issue_slots[3].out_uop.iq_type[3]
connect issue_slots[1].in_uop.bits.debug_pc, issue_slots[3].out_uop.debug_pc
connect issue_slots[1].in_uop.bits.is_rvc, issue_slots[3].out_uop.is_rvc
connect issue_slots[1].in_uop.bits.debug_inst, issue_slots[3].out_uop.debug_inst
connect issue_slots[1].in_uop.bits.inst, issue_slots[3].out_uop.inst
node _issue_slots_1_clear_T = neq(shamts_oh[1], UInt<1>(0h0))
connect issue_slots[1].clear, _issue_slots_1_clear_T
connect issue_slots[2].in_uop.valid, UInt<1>(0h0)
connect issue_slots[2].in_uop.bits.debug_tsrc, issue_slots[3].out_uop.debug_tsrc
connect issue_slots[2].in_uop.bits.debug_fsrc, issue_slots[3].out_uop.debug_fsrc
connect issue_slots[2].in_uop.bits.bp_xcpt_if, issue_slots[3].out_uop.bp_xcpt_if
connect issue_slots[2].in_uop.bits.bp_debug_if, issue_slots[3].out_uop.bp_debug_if
connect issue_slots[2].in_uop.bits.xcpt_ma_if, issue_slots[3].out_uop.xcpt_ma_if
connect issue_slots[2].in_uop.bits.xcpt_ae_if, issue_slots[3].out_uop.xcpt_ae_if
connect issue_slots[2].in_uop.bits.xcpt_pf_if, issue_slots[3].out_uop.xcpt_pf_if
connect issue_slots[2].in_uop.bits.fp_typ, issue_slots[3].out_uop.fp_typ
connect issue_slots[2].in_uop.bits.fp_rm, issue_slots[3].out_uop.fp_rm
connect issue_slots[2].in_uop.bits.fp_val, issue_slots[3].out_uop.fp_val
connect issue_slots[2].in_uop.bits.fcn_op, issue_slots[3].out_uop.fcn_op
connect issue_slots[2].in_uop.bits.fcn_dw, issue_slots[3].out_uop.fcn_dw
connect issue_slots[2].in_uop.bits.frs3_en, issue_slots[3].out_uop.frs3_en
connect issue_slots[2].in_uop.bits.lrs2_rtype, issue_slots[3].out_uop.lrs2_rtype
connect issue_slots[2].in_uop.bits.lrs1_rtype, issue_slots[3].out_uop.lrs1_rtype
connect issue_slots[2].in_uop.bits.dst_rtype, issue_slots[3].out_uop.dst_rtype
connect issue_slots[2].in_uop.bits.lrs3, issue_slots[3].out_uop.lrs3
connect issue_slots[2].in_uop.bits.lrs2, issue_slots[3].out_uop.lrs2
connect issue_slots[2].in_uop.bits.lrs1, issue_slots[3].out_uop.lrs1
connect issue_slots[2].in_uop.bits.ldst, issue_slots[3].out_uop.ldst
connect issue_slots[2].in_uop.bits.ldst_is_rs1, issue_slots[3].out_uop.ldst_is_rs1
connect issue_slots[2].in_uop.bits.csr_cmd, issue_slots[3].out_uop.csr_cmd
connect issue_slots[2].in_uop.bits.flush_on_commit, issue_slots[3].out_uop.flush_on_commit
connect issue_slots[2].in_uop.bits.is_unique, issue_slots[3].out_uop.is_unique
connect issue_slots[2].in_uop.bits.uses_stq, issue_slots[3].out_uop.uses_stq
connect issue_slots[2].in_uop.bits.uses_ldq, issue_slots[3].out_uop.uses_ldq
connect issue_slots[2].in_uop.bits.mem_signed, issue_slots[3].out_uop.mem_signed
connect issue_slots[2].in_uop.bits.mem_size, issue_slots[3].out_uop.mem_size
connect issue_slots[2].in_uop.bits.mem_cmd, issue_slots[3].out_uop.mem_cmd
connect issue_slots[2].in_uop.bits.exc_cause, issue_slots[3].out_uop.exc_cause
connect issue_slots[2].in_uop.bits.exception, issue_slots[3].out_uop.exception
connect issue_slots[2].in_uop.bits.stale_pdst, issue_slots[3].out_uop.stale_pdst
connect issue_slots[2].in_uop.bits.ppred_busy, issue_slots[3].out_uop.ppred_busy
connect issue_slots[2].in_uop.bits.prs3_busy, issue_slots[3].out_uop.prs3_busy
connect issue_slots[2].in_uop.bits.prs2_busy, issue_slots[3].out_uop.prs2_busy
connect issue_slots[2].in_uop.bits.prs1_busy, issue_slots[3].out_uop.prs1_busy
connect issue_slots[2].in_uop.bits.ppred, issue_slots[3].out_uop.ppred
connect issue_slots[2].in_uop.bits.prs3, issue_slots[3].out_uop.prs3
connect issue_slots[2].in_uop.bits.prs2, issue_slots[3].out_uop.prs2
connect issue_slots[2].in_uop.bits.prs1, issue_slots[3].out_uop.prs1
connect issue_slots[2].in_uop.bits.pdst, issue_slots[3].out_uop.pdst
connect issue_slots[2].in_uop.bits.rxq_idx, issue_slots[3].out_uop.rxq_idx
connect issue_slots[2].in_uop.bits.stq_idx, issue_slots[3].out_uop.stq_idx
connect issue_slots[2].in_uop.bits.ldq_idx, issue_slots[3].out_uop.ldq_idx
connect issue_slots[2].in_uop.bits.rob_idx, issue_slots[3].out_uop.rob_idx
connect issue_slots[2].in_uop.bits.fp_ctrl.vec, issue_slots[3].out_uop.fp_ctrl.vec
connect issue_slots[2].in_uop.bits.fp_ctrl.wflags, issue_slots[3].out_uop.fp_ctrl.wflags
connect issue_slots[2].in_uop.bits.fp_ctrl.sqrt, issue_slots[3].out_uop.fp_ctrl.sqrt
connect issue_slots[2].in_uop.bits.fp_ctrl.div, issue_slots[3].out_uop.fp_ctrl.div
connect issue_slots[2].in_uop.bits.fp_ctrl.fma, issue_slots[3].out_uop.fp_ctrl.fma
connect issue_slots[2].in_uop.bits.fp_ctrl.fastpipe, issue_slots[3].out_uop.fp_ctrl.fastpipe
connect issue_slots[2].in_uop.bits.fp_ctrl.toint, issue_slots[3].out_uop.fp_ctrl.toint
connect issue_slots[2].in_uop.bits.fp_ctrl.fromint, issue_slots[3].out_uop.fp_ctrl.fromint
connect issue_slots[2].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[3].out_uop.fp_ctrl.typeTagOut
connect issue_slots[2].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[3].out_uop.fp_ctrl.typeTagIn
connect issue_slots[2].in_uop.bits.fp_ctrl.swap23, issue_slots[3].out_uop.fp_ctrl.swap23
connect issue_slots[2].in_uop.bits.fp_ctrl.swap12, issue_slots[3].out_uop.fp_ctrl.swap12
connect issue_slots[2].in_uop.bits.fp_ctrl.ren3, issue_slots[3].out_uop.fp_ctrl.ren3
connect issue_slots[2].in_uop.bits.fp_ctrl.ren2, issue_slots[3].out_uop.fp_ctrl.ren2
connect issue_slots[2].in_uop.bits.fp_ctrl.ren1, issue_slots[3].out_uop.fp_ctrl.ren1
connect issue_slots[2].in_uop.bits.fp_ctrl.wen, issue_slots[3].out_uop.fp_ctrl.wen
connect issue_slots[2].in_uop.bits.fp_ctrl.ldst, issue_slots[3].out_uop.fp_ctrl.ldst
connect issue_slots[2].in_uop.bits.op2_sel, issue_slots[3].out_uop.op2_sel
connect issue_slots[2].in_uop.bits.op1_sel, issue_slots[3].out_uop.op1_sel
connect issue_slots[2].in_uop.bits.imm_packed, issue_slots[3].out_uop.imm_packed
connect issue_slots[2].in_uop.bits.pimm, issue_slots[3].out_uop.pimm
connect issue_slots[2].in_uop.bits.imm_sel, issue_slots[3].out_uop.imm_sel
connect issue_slots[2].in_uop.bits.imm_rename, issue_slots[3].out_uop.imm_rename
connect issue_slots[2].in_uop.bits.taken, issue_slots[3].out_uop.taken
connect issue_slots[2].in_uop.bits.pc_lob, issue_slots[3].out_uop.pc_lob
connect issue_slots[2].in_uop.bits.edge_inst, issue_slots[3].out_uop.edge_inst
connect issue_slots[2].in_uop.bits.ftq_idx, issue_slots[3].out_uop.ftq_idx
connect issue_slots[2].in_uop.bits.is_mov, issue_slots[3].out_uop.is_mov
connect issue_slots[2].in_uop.bits.is_rocc, issue_slots[3].out_uop.is_rocc
connect issue_slots[2].in_uop.bits.is_sys_pc2epc, issue_slots[3].out_uop.is_sys_pc2epc
connect issue_slots[2].in_uop.bits.is_eret, issue_slots[3].out_uop.is_eret
connect issue_slots[2].in_uop.bits.is_amo, issue_slots[3].out_uop.is_amo
connect issue_slots[2].in_uop.bits.is_sfence, issue_slots[3].out_uop.is_sfence
connect issue_slots[2].in_uop.bits.is_fencei, issue_slots[3].out_uop.is_fencei
connect issue_slots[2].in_uop.bits.is_fence, issue_slots[3].out_uop.is_fence
connect issue_slots[2].in_uop.bits.is_sfb, issue_slots[3].out_uop.is_sfb
connect issue_slots[2].in_uop.bits.br_type, issue_slots[3].out_uop.br_type
connect issue_slots[2].in_uop.bits.br_tag, issue_slots[3].out_uop.br_tag
connect issue_slots[2].in_uop.bits.br_mask, issue_slots[3].out_uop.br_mask
connect issue_slots[2].in_uop.bits.dis_col_sel, issue_slots[3].out_uop.dis_col_sel
connect issue_slots[2].in_uop.bits.iw_p3_bypass_hint, issue_slots[3].out_uop.iw_p3_bypass_hint
connect issue_slots[2].in_uop.bits.iw_p2_bypass_hint, issue_slots[3].out_uop.iw_p2_bypass_hint
connect issue_slots[2].in_uop.bits.iw_p1_bypass_hint, issue_slots[3].out_uop.iw_p1_bypass_hint
connect issue_slots[2].in_uop.bits.iw_p2_speculative_child, issue_slots[3].out_uop.iw_p2_speculative_child
connect issue_slots[2].in_uop.bits.iw_p1_speculative_child, issue_slots[3].out_uop.iw_p1_speculative_child
connect issue_slots[2].in_uop.bits.iw_issued_partial_dgen, issue_slots[3].out_uop.iw_issued_partial_dgen
connect issue_slots[2].in_uop.bits.iw_issued_partial_agen, issue_slots[3].out_uop.iw_issued_partial_agen
connect issue_slots[2].in_uop.bits.iw_issued, issue_slots[3].out_uop.iw_issued
connect issue_slots[2].in_uop.bits.fu_code[0], issue_slots[3].out_uop.fu_code[0]
connect issue_slots[2].in_uop.bits.fu_code[1], issue_slots[3].out_uop.fu_code[1]
connect issue_slots[2].in_uop.bits.fu_code[2], issue_slots[3].out_uop.fu_code[2]
connect issue_slots[2].in_uop.bits.fu_code[3], issue_slots[3].out_uop.fu_code[3]
connect issue_slots[2].in_uop.bits.fu_code[4], issue_slots[3].out_uop.fu_code[4]
connect issue_slots[2].in_uop.bits.fu_code[5], issue_slots[3].out_uop.fu_code[5]
connect issue_slots[2].in_uop.bits.fu_code[6], issue_slots[3].out_uop.fu_code[6]
connect issue_slots[2].in_uop.bits.fu_code[7], issue_slots[3].out_uop.fu_code[7]
connect issue_slots[2].in_uop.bits.fu_code[8], issue_slots[3].out_uop.fu_code[8]
connect issue_slots[2].in_uop.bits.fu_code[9], issue_slots[3].out_uop.fu_code[9]
connect issue_slots[2].in_uop.bits.iq_type[0], issue_slots[3].out_uop.iq_type[0]
connect issue_slots[2].in_uop.bits.iq_type[1], issue_slots[3].out_uop.iq_type[1]
connect issue_slots[2].in_uop.bits.iq_type[2], issue_slots[3].out_uop.iq_type[2]
connect issue_slots[2].in_uop.bits.iq_type[3], issue_slots[3].out_uop.iq_type[3]
connect issue_slots[2].in_uop.bits.debug_pc, issue_slots[3].out_uop.debug_pc
connect issue_slots[2].in_uop.bits.is_rvc, issue_slots[3].out_uop.is_rvc
connect issue_slots[2].in_uop.bits.debug_inst, issue_slots[3].out_uop.debug_inst
connect issue_slots[2].in_uop.bits.inst, issue_slots[3].out_uop.inst
node _T_166 = eq(shamts_oh[3], UInt<1>(0h1))
when _T_166 :
connect issue_slots[2].in_uop.valid, issue_slots[3].will_be_valid
connect issue_slots[2].in_uop.bits.debug_tsrc, issue_slots[3].out_uop.debug_tsrc
connect issue_slots[2].in_uop.bits.debug_fsrc, issue_slots[3].out_uop.debug_fsrc
connect issue_slots[2].in_uop.bits.bp_xcpt_if, issue_slots[3].out_uop.bp_xcpt_if
connect issue_slots[2].in_uop.bits.bp_debug_if, issue_slots[3].out_uop.bp_debug_if
connect issue_slots[2].in_uop.bits.xcpt_ma_if, issue_slots[3].out_uop.xcpt_ma_if
connect issue_slots[2].in_uop.bits.xcpt_ae_if, issue_slots[3].out_uop.xcpt_ae_if
connect issue_slots[2].in_uop.bits.xcpt_pf_if, issue_slots[3].out_uop.xcpt_pf_if
connect issue_slots[2].in_uop.bits.fp_typ, issue_slots[3].out_uop.fp_typ
connect issue_slots[2].in_uop.bits.fp_rm, issue_slots[3].out_uop.fp_rm
connect issue_slots[2].in_uop.bits.fp_val, issue_slots[3].out_uop.fp_val
connect issue_slots[2].in_uop.bits.fcn_op, issue_slots[3].out_uop.fcn_op
connect issue_slots[2].in_uop.bits.fcn_dw, issue_slots[3].out_uop.fcn_dw
connect issue_slots[2].in_uop.bits.frs3_en, issue_slots[3].out_uop.frs3_en
connect issue_slots[2].in_uop.bits.lrs2_rtype, issue_slots[3].out_uop.lrs2_rtype
connect issue_slots[2].in_uop.bits.lrs1_rtype, issue_slots[3].out_uop.lrs1_rtype
connect issue_slots[2].in_uop.bits.dst_rtype, issue_slots[3].out_uop.dst_rtype
connect issue_slots[2].in_uop.bits.lrs3, issue_slots[3].out_uop.lrs3
connect issue_slots[2].in_uop.bits.lrs2, issue_slots[3].out_uop.lrs2
connect issue_slots[2].in_uop.bits.lrs1, issue_slots[3].out_uop.lrs1
connect issue_slots[2].in_uop.bits.ldst, issue_slots[3].out_uop.ldst
connect issue_slots[2].in_uop.bits.ldst_is_rs1, issue_slots[3].out_uop.ldst_is_rs1
connect issue_slots[2].in_uop.bits.csr_cmd, issue_slots[3].out_uop.csr_cmd
connect issue_slots[2].in_uop.bits.flush_on_commit, issue_slots[3].out_uop.flush_on_commit
connect issue_slots[2].in_uop.bits.is_unique, issue_slots[3].out_uop.is_unique
connect issue_slots[2].in_uop.bits.uses_stq, issue_slots[3].out_uop.uses_stq
connect issue_slots[2].in_uop.bits.uses_ldq, issue_slots[3].out_uop.uses_ldq
connect issue_slots[2].in_uop.bits.mem_signed, issue_slots[3].out_uop.mem_signed
connect issue_slots[2].in_uop.bits.mem_size, issue_slots[3].out_uop.mem_size
connect issue_slots[2].in_uop.bits.mem_cmd, issue_slots[3].out_uop.mem_cmd
connect issue_slots[2].in_uop.bits.exc_cause, issue_slots[3].out_uop.exc_cause
connect issue_slots[2].in_uop.bits.exception, issue_slots[3].out_uop.exception
connect issue_slots[2].in_uop.bits.stale_pdst, issue_slots[3].out_uop.stale_pdst
connect issue_slots[2].in_uop.bits.ppred_busy, issue_slots[3].out_uop.ppred_busy
connect issue_slots[2].in_uop.bits.prs3_busy, issue_slots[3].out_uop.prs3_busy
connect issue_slots[2].in_uop.bits.prs2_busy, issue_slots[3].out_uop.prs2_busy
connect issue_slots[2].in_uop.bits.prs1_busy, issue_slots[3].out_uop.prs1_busy
connect issue_slots[2].in_uop.bits.ppred, issue_slots[3].out_uop.ppred
connect issue_slots[2].in_uop.bits.prs3, issue_slots[3].out_uop.prs3
connect issue_slots[2].in_uop.bits.prs2, issue_slots[3].out_uop.prs2
connect issue_slots[2].in_uop.bits.prs1, issue_slots[3].out_uop.prs1
connect issue_slots[2].in_uop.bits.pdst, issue_slots[3].out_uop.pdst
connect issue_slots[2].in_uop.bits.rxq_idx, issue_slots[3].out_uop.rxq_idx
connect issue_slots[2].in_uop.bits.stq_idx, issue_slots[3].out_uop.stq_idx
connect issue_slots[2].in_uop.bits.ldq_idx, issue_slots[3].out_uop.ldq_idx
connect issue_slots[2].in_uop.bits.rob_idx, issue_slots[3].out_uop.rob_idx
connect issue_slots[2].in_uop.bits.fp_ctrl.vec, issue_slots[3].out_uop.fp_ctrl.vec
connect issue_slots[2].in_uop.bits.fp_ctrl.wflags, issue_slots[3].out_uop.fp_ctrl.wflags
connect issue_slots[2].in_uop.bits.fp_ctrl.sqrt, issue_slots[3].out_uop.fp_ctrl.sqrt
connect issue_slots[2].in_uop.bits.fp_ctrl.div, issue_slots[3].out_uop.fp_ctrl.div
connect issue_slots[2].in_uop.bits.fp_ctrl.fma, issue_slots[3].out_uop.fp_ctrl.fma
connect issue_slots[2].in_uop.bits.fp_ctrl.fastpipe, issue_slots[3].out_uop.fp_ctrl.fastpipe
connect issue_slots[2].in_uop.bits.fp_ctrl.toint, issue_slots[3].out_uop.fp_ctrl.toint
connect issue_slots[2].in_uop.bits.fp_ctrl.fromint, issue_slots[3].out_uop.fp_ctrl.fromint
connect issue_slots[2].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[3].out_uop.fp_ctrl.typeTagOut
connect issue_slots[2].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[3].out_uop.fp_ctrl.typeTagIn
connect issue_slots[2].in_uop.bits.fp_ctrl.swap23, issue_slots[3].out_uop.fp_ctrl.swap23
connect issue_slots[2].in_uop.bits.fp_ctrl.swap12, issue_slots[3].out_uop.fp_ctrl.swap12
connect issue_slots[2].in_uop.bits.fp_ctrl.ren3, issue_slots[3].out_uop.fp_ctrl.ren3
connect issue_slots[2].in_uop.bits.fp_ctrl.ren2, issue_slots[3].out_uop.fp_ctrl.ren2
connect issue_slots[2].in_uop.bits.fp_ctrl.ren1, issue_slots[3].out_uop.fp_ctrl.ren1
connect issue_slots[2].in_uop.bits.fp_ctrl.wen, issue_slots[3].out_uop.fp_ctrl.wen
connect issue_slots[2].in_uop.bits.fp_ctrl.ldst, issue_slots[3].out_uop.fp_ctrl.ldst
connect issue_slots[2].in_uop.bits.op2_sel, issue_slots[3].out_uop.op2_sel
connect issue_slots[2].in_uop.bits.op1_sel, issue_slots[3].out_uop.op1_sel
connect issue_slots[2].in_uop.bits.imm_packed, issue_slots[3].out_uop.imm_packed
connect issue_slots[2].in_uop.bits.pimm, issue_slots[3].out_uop.pimm
connect issue_slots[2].in_uop.bits.imm_sel, issue_slots[3].out_uop.imm_sel
connect issue_slots[2].in_uop.bits.imm_rename, issue_slots[3].out_uop.imm_rename
connect issue_slots[2].in_uop.bits.taken, issue_slots[3].out_uop.taken
connect issue_slots[2].in_uop.bits.pc_lob, issue_slots[3].out_uop.pc_lob
connect issue_slots[2].in_uop.bits.edge_inst, issue_slots[3].out_uop.edge_inst
connect issue_slots[2].in_uop.bits.ftq_idx, issue_slots[3].out_uop.ftq_idx
connect issue_slots[2].in_uop.bits.is_mov, issue_slots[3].out_uop.is_mov
connect issue_slots[2].in_uop.bits.is_rocc, issue_slots[3].out_uop.is_rocc
connect issue_slots[2].in_uop.bits.is_sys_pc2epc, issue_slots[3].out_uop.is_sys_pc2epc
connect issue_slots[2].in_uop.bits.is_eret, issue_slots[3].out_uop.is_eret
connect issue_slots[2].in_uop.bits.is_amo, issue_slots[3].out_uop.is_amo
connect issue_slots[2].in_uop.bits.is_sfence, issue_slots[3].out_uop.is_sfence
connect issue_slots[2].in_uop.bits.is_fencei, issue_slots[3].out_uop.is_fencei
connect issue_slots[2].in_uop.bits.is_fence, issue_slots[3].out_uop.is_fence
connect issue_slots[2].in_uop.bits.is_sfb, issue_slots[3].out_uop.is_sfb
connect issue_slots[2].in_uop.bits.br_type, issue_slots[3].out_uop.br_type
connect issue_slots[2].in_uop.bits.br_tag, issue_slots[3].out_uop.br_tag
connect issue_slots[2].in_uop.bits.br_mask, issue_slots[3].out_uop.br_mask
connect issue_slots[2].in_uop.bits.dis_col_sel, issue_slots[3].out_uop.dis_col_sel
connect issue_slots[2].in_uop.bits.iw_p3_bypass_hint, issue_slots[3].out_uop.iw_p3_bypass_hint
connect issue_slots[2].in_uop.bits.iw_p2_bypass_hint, issue_slots[3].out_uop.iw_p2_bypass_hint
connect issue_slots[2].in_uop.bits.iw_p1_bypass_hint, issue_slots[3].out_uop.iw_p1_bypass_hint
connect issue_slots[2].in_uop.bits.iw_p2_speculative_child, issue_slots[3].out_uop.iw_p2_speculative_child
connect issue_slots[2].in_uop.bits.iw_p1_speculative_child, issue_slots[3].out_uop.iw_p1_speculative_child
connect issue_slots[2].in_uop.bits.iw_issued_partial_dgen, issue_slots[3].out_uop.iw_issued_partial_dgen
connect issue_slots[2].in_uop.bits.iw_issued_partial_agen, issue_slots[3].out_uop.iw_issued_partial_agen
connect issue_slots[2].in_uop.bits.iw_issued, issue_slots[3].out_uop.iw_issued
connect issue_slots[2].in_uop.bits.fu_code[0], issue_slots[3].out_uop.fu_code[0]
connect issue_slots[2].in_uop.bits.fu_code[1], issue_slots[3].out_uop.fu_code[1]
connect issue_slots[2].in_uop.bits.fu_code[2], issue_slots[3].out_uop.fu_code[2]
connect issue_slots[2].in_uop.bits.fu_code[3], issue_slots[3].out_uop.fu_code[3]
connect issue_slots[2].in_uop.bits.fu_code[4], issue_slots[3].out_uop.fu_code[4]
connect issue_slots[2].in_uop.bits.fu_code[5], issue_slots[3].out_uop.fu_code[5]
connect issue_slots[2].in_uop.bits.fu_code[6], issue_slots[3].out_uop.fu_code[6]
connect issue_slots[2].in_uop.bits.fu_code[7], issue_slots[3].out_uop.fu_code[7]
connect issue_slots[2].in_uop.bits.fu_code[8], issue_slots[3].out_uop.fu_code[8]
connect issue_slots[2].in_uop.bits.fu_code[9], issue_slots[3].out_uop.fu_code[9]
connect issue_slots[2].in_uop.bits.iq_type[0], issue_slots[3].out_uop.iq_type[0]
connect issue_slots[2].in_uop.bits.iq_type[1], issue_slots[3].out_uop.iq_type[1]
connect issue_slots[2].in_uop.bits.iq_type[2], issue_slots[3].out_uop.iq_type[2]
connect issue_slots[2].in_uop.bits.iq_type[3], issue_slots[3].out_uop.iq_type[3]
connect issue_slots[2].in_uop.bits.debug_pc, issue_slots[3].out_uop.debug_pc
connect issue_slots[2].in_uop.bits.is_rvc, issue_slots[3].out_uop.is_rvc
connect issue_slots[2].in_uop.bits.debug_inst, issue_slots[3].out_uop.debug_inst
connect issue_slots[2].in_uop.bits.inst, issue_slots[3].out_uop.inst
node _T_167 = eq(shamts_oh[4], UInt<2>(0h2))
when _T_167 :
connect issue_slots[2].in_uop.valid, issue_slots[4].will_be_valid
connect issue_slots[2].in_uop.bits.debug_tsrc, issue_slots[4].out_uop.debug_tsrc
connect issue_slots[2].in_uop.bits.debug_fsrc, issue_slots[4].out_uop.debug_fsrc
connect issue_slots[2].in_uop.bits.bp_xcpt_if, issue_slots[4].out_uop.bp_xcpt_if
connect issue_slots[2].in_uop.bits.bp_debug_if, issue_slots[4].out_uop.bp_debug_if
connect issue_slots[2].in_uop.bits.xcpt_ma_if, issue_slots[4].out_uop.xcpt_ma_if
connect issue_slots[2].in_uop.bits.xcpt_ae_if, issue_slots[4].out_uop.xcpt_ae_if
connect issue_slots[2].in_uop.bits.xcpt_pf_if, issue_slots[4].out_uop.xcpt_pf_if
connect issue_slots[2].in_uop.bits.fp_typ, issue_slots[4].out_uop.fp_typ
connect issue_slots[2].in_uop.bits.fp_rm, issue_slots[4].out_uop.fp_rm
connect issue_slots[2].in_uop.bits.fp_val, issue_slots[4].out_uop.fp_val
connect issue_slots[2].in_uop.bits.fcn_op, issue_slots[4].out_uop.fcn_op
connect issue_slots[2].in_uop.bits.fcn_dw, issue_slots[4].out_uop.fcn_dw
connect issue_slots[2].in_uop.bits.frs3_en, issue_slots[4].out_uop.frs3_en
connect issue_slots[2].in_uop.bits.lrs2_rtype, issue_slots[4].out_uop.lrs2_rtype
connect issue_slots[2].in_uop.bits.lrs1_rtype, issue_slots[4].out_uop.lrs1_rtype
connect issue_slots[2].in_uop.bits.dst_rtype, issue_slots[4].out_uop.dst_rtype
connect issue_slots[2].in_uop.bits.lrs3, issue_slots[4].out_uop.lrs3
connect issue_slots[2].in_uop.bits.lrs2, issue_slots[4].out_uop.lrs2
connect issue_slots[2].in_uop.bits.lrs1, issue_slots[4].out_uop.lrs1
connect issue_slots[2].in_uop.bits.ldst, issue_slots[4].out_uop.ldst
connect issue_slots[2].in_uop.bits.ldst_is_rs1, issue_slots[4].out_uop.ldst_is_rs1
connect issue_slots[2].in_uop.bits.csr_cmd, issue_slots[4].out_uop.csr_cmd
connect issue_slots[2].in_uop.bits.flush_on_commit, issue_slots[4].out_uop.flush_on_commit
connect issue_slots[2].in_uop.bits.is_unique, issue_slots[4].out_uop.is_unique
connect issue_slots[2].in_uop.bits.uses_stq, issue_slots[4].out_uop.uses_stq
connect issue_slots[2].in_uop.bits.uses_ldq, issue_slots[4].out_uop.uses_ldq
connect issue_slots[2].in_uop.bits.mem_signed, issue_slots[4].out_uop.mem_signed
connect issue_slots[2].in_uop.bits.mem_size, issue_slots[4].out_uop.mem_size
connect issue_slots[2].in_uop.bits.mem_cmd, issue_slots[4].out_uop.mem_cmd
connect issue_slots[2].in_uop.bits.exc_cause, issue_slots[4].out_uop.exc_cause
connect issue_slots[2].in_uop.bits.exception, issue_slots[4].out_uop.exception
connect issue_slots[2].in_uop.bits.stale_pdst, issue_slots[4].out_uop.stale_pdst
connect issue_slots[2].in_uop.bits.ppred_busy, issue_slots[4].out_uop.ppred_busy
connect issue_slots[2].in_uop.bits.prs3_busy, issue_slots[4].out_uop.prs3_busy
connect issue_slots[2].in_uop.bits.prs2_busy, issue_slots[4].out_uop.prs2_busy
connect issue_slots[2].in_uop.bits.prs1_busy, issue_slots[4].out_uop.prs1_busy
connect issue_slots[2].in_uop.bits.ppred, issue_slots[4].out_uop.ppred
connect issue_slots[2].in_uop.bits.prs3, issue_slots[4].out_uop.prs3
connect issue_slots[2].in_uop.bits.prs2, issue_slots[4].out_uop.prs2
connect issue_slots[2].in_uop.bits.prs1, issue_slots[4].out_uop.prs1
connect issue_slots[2].in_uop.bits.pdst, issue_slots[4].out_uop.pdst
connect issue_slots[2].in_uop.bits.rxq_idx, issue_slots[4].out_uop.rxq_idx
connect issue_slots[2].in_uop.bits.stq_idx, issue_slots[4].out_uop.stq_idx
connect issue_slots[2].in_uop.bits.ldq_idx, issue_slots[4].out_uop.ldq_idx
connect issue_slots[2].in_uop.bits.rob_idx, issue_slots[4].out_uop.rob_idx
connect issue_slots[2].in_uop.bits.fp_ctrl.vec, issue_slots[4].out_uop.fp_ctrl.vec
connect issue_slots[2].in_uop.bits.fp_ctrl.wflags, issue_slots[4].out_uop.fp_ctrl.wflags
connect issue_slots[2].in_uop.bits.fp_ctrl.sqrt, issue_slots[4].out_uop.fp_ctrl.sqrt
connect issue_slots[2].in_uop.bits.fp_ctrl.div, issue_slots[4].out_uop.fp_ctrl.div
connect issue_slots[2].in_uop.bits.fp_ctrl.fma, issue_slots[4].out_uop.fp_ctrl.fma
connect issue_slots[2].in_uop.bits.fp_ctrl.fastpipe, issue_slots[4].out_uop.fp_ctrl.fastpipe
connect issue_slots[2].in_uop.bits.fp_ctrl.toint, issue_slots[4].out_uop.fp_ctrl.toint
connect issue_slots[2].in_uop.bits.fp_ctrl.fromint, issue_slots[4].out_uop.fp_ctrl.fromint
connect issue_slots[2].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[4].out_uop.fp_ctrl.typeTagOut
connect issue_slots[2].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[4].out_uop.fp_ctrl.typeTagIn
connect issue_slots[2].in_uop.bits.fp_ctrl.swap23, issue_slots[4].out_uop.fp_ctrl.swap23
connect issue_slots[2].in_uop.bits.fp_ctrl.swap12, issue_slots[4].out_uop.fp_ctrl.swap12
connect issue_slots[2].in_uop.bits.fp_ctrl.ren3, issue_slots[4].out_uop.fp_ctrl.ren3
connect issue_slots[2].in_uop.bits.fp_ctrl.ren2, issue_slots[4].out_uop.fp_ctrl.ren2
connect issue_slots[2].in_uop.bits.fp_ctrl.ren1, issue_slots[4].out_uop.fp_ctrl.ren1
connect issue_slots[2].in_uop.bits.fp_ctrl.wen, issue_slots[4].out_uop.fp_ctrl.wen
connect issue_slots[2].in_uop.bits.fp_ctrl.ldst, issue_slots[4].out_uop.fp_ctrl.ldst
connect issue_slots[2].in_uop.bits.op2_sel, issue_slots[4].out_uop.op2_sel
connect issue_slots[2].in_uop.bits.op1_sel, issue_slots[4].out_uop.op1_sel
connect issue_slots[2].in_uop.bits.imm_packed, issue_slots[4].out_uop.imm_packed
connect issue_slots[2].in_uop.bits.pimm, issue_slots[4].out_uop.pimm
connect issue_slots[2].in_uop.bits.imm_sel, issue_slots[4].out_uop.imm_sel
connect issue_slots[2].in_uop.bits.imm_rename, issue_slots[4].out_uop.imm_rename
connect issue_slots[2].in_uop.bits.taken, issue_slots[4].out_uop.taken
connect issue_slots[2].in_uop.bits.pc_lob, issue_slots[4].out_uop.pc_lob
connect issue_slots[2].in_uop.bits.edge_inst, issue_slots[4].out_uop.edge_inst
connect issue_slots[2].in_uop.bits.ftq_idx, issue_slots[4].out_uop.ftq_idx
connect issue_slots[2].in_uop.bits.is_mov, issue_slots[4].out_uop.is_mov
connect issue_slots[2].in_uop.bits.is_rocc, issue_slots[4].out_uop.is_rocc
connect issue_slots[2].in_uop.bits.is_sys_pc2epc, issue_slots[4].out_uop.is_sys_pc2epc
connect issue_slots[2].in_uop.bits.is_eret, issue_slots[4].out_uop.is_eret
connect issue_slots[2].in_uop.bits.is_amo, issue_slots[4].out_uop.is_amo
connect issue_slots[2].in_uop.bits.is_sfence, issue_slots[4].out_uop.is_sfence
connect issue_slots[2].in_uop.bits.is_fencei, issue_slots[4].out_uop.is_fencei
connect issue_slots[2].in_uop.bits.is_fence, issue_slots[4].out_uop.is_fence
connect issue_slots[2].in_uop.bits.is_sfb, issue_slots[4].out_uop.is_sfb
connect issue_slots[2].in_uop.bits.br_type, issue_slots[4].out_uop.br_type
connect issue_slots[2].in_uop.bits.br_tag, issue_slots[4].out_uop.br_tag
connect issue_slots[2].in_uop.bits.br_mask, issue_slots[4].out_uop.br_mask
connect issue_slots[2].in_uop.bits.dis_col_sel, issue_slots[4].out_uop.dis_col_sel
connect issue_slots[2].in_uop.bits.iw_p3_bypass_hint, issue_slots[4].out_uop.iw_p3_bypass_hint
connect issue_slots[2].in_uop.bits.iw_p2_bypass_hint, issue_slots[4].out_uop.iw_p2_bypass_hint
connect issue_slots[2].in_uop.bits.iw_p1_bypass_hint, issue_slots[4].out_uop.iw_p1_bypass_hint
connect issue_slots[2].in_uop.bits.iw_p2_speculative_child, issue_slots[4].out_uop.iw_p2_speculative_child
connect issue_slots[2].in_uop.bits.iw_p1_speculative_child, issue_slots[4].out_uop.iw_p1_speculative_child
connect issue_slots[2].in_uop.bits.iw_issued_partial_dgen, issue_slots[4].out_uop.iw_issued_partial_dgen
connect issue_slots[2].in_uop.bits.iw_issued_partial_agen, issue_slots[4].out_uop.iw_issued_partial_agen
connect issue_slots[2].in_uop.bits.iw_issued, issue_slots[4].out_uop.iw_issued
connect issue_slots[2].in_uop.bits.fu_code[0], issue_slots[4].out_uop.fu_code[0]
connect issue_slots[2].in_uop.bits.fu_code[1], issue_slots[4].out_uop.fu_code[1]
connect issue_slots[2].in_uop.bits.fu_code[2], issue_slots[4].out_uop.fu_code[2]
connect issue_slots[2].in_uop.bits.fu_code[3], issue_slots[4].out_uop.fu_code[3]
connect issue_slots[2].in_uop.bits.fu_code[4], issue_slots[4].out_uop.fu_code[4]
connect issue_slots[2].in_uop.bits.fu_code[5], issue_slots[4].out_uop.fu_code[5]
connect issue_slots[2].in_uop.bits.fu_code[6], issue_slots[4].out_uop.fu_code[6]
connect issue_slots[2].in_uop.bits.fu_code[7], issue_slots[4].out_uop.fu_code[7]
connect issue_slots[2].in_uop.bits.fu_code[8], issue_slots[4].out_uop.fu_code[8]
connect issue_slots[2].in_uop.bits.fu_code[9], issue_slots[4].out_uop.fu_code[9]
connect issue_slots[2].in_uop.bits.iq_type[0], issue_slots[4].out_uop.iq_type[0]
connect issue_slots[2].in_uop.bits.iq_type[1], issue_slots[4].out_uop.iq_type[1]
connect issue_slots[2].in_uop.bits.iq_type[2], issue_slots[4].out_uop.iq_type[2]
connect issue_slots[2].in_uop.bits.iq_type[3], issue_slots[4].out_uop.iq_type[3]
connect issue_slots[2].in_uop.bits.debug_pc, issue_slots[4].out_uop.debug_pc
connect issue_slots[2].in_uop.bits.is_rvc, issue_slots[4].out_uop.is_rvc
connect issue_slots[2].in_uop.bits.debug_inst, issue_slots[4].out_uop.debug_inst
connect issue_slots[2].in_uop.bits.inst, issue_slots[4].out_uop.inst
node _issue_slots_2_clear_T = neq(shamts_oh[2], UInt<1>(0h0))
connect issue_slots[2].clear, _issue_slots_2_clear_T
connect issue_slots[3].in_uop.valid, UInt<1>(0h0)
connect issue_slots[3].in_uop.bits.debug_tsrc, issue_slots[4].out_uop.debug_tsrc
connect issue_slots[3].in_uop.bits.debug_fsrc, issue_slots[4].out_uop.debug_fsrc
connect issue_slots[3].in_uop.bits.bp_xcpt_if, issue_slots[4].out_uop.bp_xcpt_if
connect issue_slots[3].in_uop.bits.bp_debug_if, issue_slots[4].out_uop.bp_debug_if
connect issue_slots[3].in_uop.bits.xcpt_ma_if, issue_slots[4].out_uop.xcpt_ma_if
connect issue_slots[3].in_uop.bits.xcpt_ae_if, issue_slots[4].out_uop.xcpt_ae_if
connect issue_slots[3].in_uop.bits.xcpt_pf_if, issue_slots[4].out_uop.xcpt_pf_if
connect issue_slots[3].in_uop.bits.fp_typ, issue_slots[4].out_uop.fp_typ
connect issue_slots[3].in_uop.bits.fp_rm, issue_slots[4].out_uop.fp_rm
connect issue_slots[3].in_uop.bits.fp_val, issue_slots[4].out_uop.fp_val
connect issue_slots[3].in_uop.bits.fcn_op, issue_slots[4].out_uop.fcn_op
connect issue_slots[3].in_uop.bits.fcn_dw, issue_slots[4].out_uop.fcn_dw
connect issue_slots[3].in_uop.bits.frs3_en, issue_slots[4].out_uop.frs3_en
connect issue_slots[3].in_uop.bits.lrs2_rtype, issue_slots[4].out_uop.lrs2_rtype
connect issue_slots[3].in_uop.bits.lrs1_rtype, issue_slots[4].out_uop.lrs1_rtype
connect issue_slots[3].in_uop.bits.dst_rtype, issue_slots[4].out_uop.dst_rtype
connect issue_slots[3].in_uop.bits.lrs3, issue_slots[4].out_uop.lrs3
connect issue_slots[3].in_uop.bits.lrs2, issue_slots[4].out_uop.lrs2
connect issue_slots[3].in_uop.bits.lrs1, issue_slots[4].out_uop.lrs1
connect issue_slots[3].in_uop.bits.ldst, issue_slots[4].out_uop.ldst
connect issue_slots[3].in_uop.bits.ldst_is_rs1, issue_slots[4].out_uop.ldst_is_rs1
connect issue_slots[3].in_uop.bits.csr_cmd, issue_slots[4].out_uop.csr_cmd
connect issue_slots[3].in_uop.bits.flush_on_commit, issue_slots[4].out_uop.flush_on_commit
connect issue_slots[3].in_uop.bits.is_unique, issue_slots[4].out_uop.is_unique
connect issue_slots[3].in_uop.bits.uses_stq, issue_slots[4].out_uop.uses_stq
connect issue_slots[3].in_uop.bits.uses_ldq, issue_slots[4].out_uop.uses_ldq
connect issue_slots[3].in_uop.bits.mem_signed, issue_slots[4].out_uop.mem_signed
connect issue_slots[3].in_uop.bits.mem_size, issue_slots[4].out_uop.mem_size
connect issue_slots[3].in_uop.bits.mem_cmd, issue_slots[4].out_uop.mem_cmd
connect issue_slots[3].in_uop.bits.exc_cause, issue_slots[4].out_uop.exc_cause
connect issue_slots[3].in_uop.bits.exception, issue_slots[4].out_uop.exception
connect issue_slots[3].in_uop.bits.stale_pdst, issue_slots[4].out_uop.stale_pdst
connect issue_slots[3].in_uop.bits.ppred_busy, issue_slots[4].out_uop.ppred_busy
connect issue_slots[3].in_uop.bits.prs3_busy, issue_slots[4].out_uop.prs3_busy
connect issue_slots[3].in_uop.bits.prs2_busy, issue_slots[4].out_uop.prs2_busy
connect issue_slots[3].in_uop.bits.prs1_busy, issue_slots[4].out_uop.prs1_busy
connect issue_slots[3].in_uop.bits.ppred, issue_slots[4].out_uop.ppred
connect issue_slots[3].in_uop.bits.prs3, issue_slots[4].out_uop.prs3
connect issue_slots[3].in_uop.bits.prs2, issue_slots[4].out_uop.prs2
connect issue_slots[3].in_uop.bits.prs1, issue_slots[4].out_uop.prs1
connect issue_slots[3].in_uop.bits.pdst, issue_slots[4].out_uop.pdst
connect issue_slots[3].in_uop.bits.rxq_idx, issue_slots[4].out_uop.rxq_idx
connect issue_slots[3].in_uop.bits.stq_idx, issue_slots[4].out_uop.stq_idx
connect issue_slots[3].in_uop.bits.ldq_idx, issue_slots[4].out_uop.ldq_idx
connect issue_slots[3].in_uop.bits.rob_idx, issue_slots[4].out_uop.rob_idx
connect issue_slots[3].in_uop.bits.fp_ctrl.vec, issue_slots[4].out_uop.fp_ctrl.vec
connect issue_slots[3].in_uop.bits.fp_ctrl.wflags, issue_slots[4].out_uop.fp_ctrl.wflags
connect issue_slots[3].in_uop.bits.fp_ctrl.sqrt, issue_slots[4].out_uop.fp_ctrl.sqrt
connect issue_slots[3].in_uop.bits.fp_ctrl.div, issue_slots[4].out_uop.fp_ctrl.div
connect issue_slots[3].in_uop.bits.fp_ctrl.fma, issue_slots[4].out_uop.fp_ctrl.fma
connect issue_slots[3].in_uop.bits.fp_ctrl.fastpipe, issue_slots[4].out_uop.fp_ctrl.fastpipe
connect issue_slots[3].in_uop.bits.fp_ctrl.toint, issue_slots[4].out_uop.fp_ctrl.toint
connect issue_slots[3].in_uop.bits.fp_ctrl.fromint, issue_slots[4].out_uop.fp_ctrl.fromint
connect issue_slots[3].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[4].out_uop.fp_ctrl.typeTagOut
connect issue_slots[3].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[4].out_uop.fp_ctrl.typeTagIn
connect issue_slots[3].in_uop.bits.fp_ctrl.swap23, issue_slots[4].out_uop.fp_ctrl.swap23
connect issue_slots[3].in_uop.bits.fp_ctrl.swap12, issue_slots[4].out_uop.fp_ctrl.swap12
connect issue_slots[3].in_uop.bits.fp_ctrl.ren3, issue_slots[4].out_uop.fp_ctrl.ren3
connect issue_slots[3].in_uop.bits.fp_ctrl.ren2, issue_slots[4].out_uop.fp_ctrl.ren2
connect issue_slots[3].in_uop.bits.fp_ctrl.ren1, issue_slots[4].out_uop.fp_ctrl.ren1
connect issue_slots[3].in_uop.bits.fp_ctrl.wen, issue_slots[4].out_uop.fp_ctrl.wen
connect issue_slots[3].in_uop.bits.fp_ctrl.ldst, issue_slots[4].out_uop.fp_ctrl.ldst
connect issue_slots[3].in_uop.bits.op2_sel, issue_slots[4].out_uop.op2_sel
connect issue_slots[3].in_uop.bits.op1_sel, issue_slots[4].out_uop.op1_sel
connect issue_slots[3].in_uop.bits.imm_packed, issue_slots[4].out_uop.imm_packed
connect issue_slots[3].in_uop.bits.pimm, issue_slots[4].out_uop.pimm
connect issue_slots[3].in_uop.bits.imm_sel, issue_slots[4].out_uop.imm_sel
connect issue_slots[3].in_uop.bits.imm_rename, issue_slots[4].out_uop.imm_rename
connect issue_slots[3].in_uop.bits.taken, issue_slots[4].out_uop.taken
connect issue_slots[3].in_uop.bits.pc_lob, issue_slots[4].out_uop.pc_lob
connect issue_slots[3].in_uop.bits.edge_inst, issue_slots[4].out_uop.edge_inst
connect issue_slots[3].in_uop.bits.ftq_idx, issue_slots[4].out_uop.ftq_idx
connect issue_slots[3].in_uop.bits.is_mov, issue_slots[4].out_uop.is_mov
connect issue_slots[3].in_uop.bits.is_rocc, issue_slots[4].out_uop.is_rocc
connect issue_slots[3].in_uop.bits.is_sys_pc2epc, issue_slots[4].out_uop.is_sys_pc2epc
connect issue_slots[3].in_uop.bits.is_eret, issue_slots[4].out_uop.is_eret
connect issue_slots[3].in_uop.bits.is_amo, issue_slots[4].out_uop.is_amo
connect issue_slots[3].in_uop.bits.is_sfence, issue_slots[4].out_uop.is_sfence
connect issue_slots[3].in_uop.bits.is_fencei, issue_slots[4].out_uop.is_fencei
connect issue_slots[3].in_uop.bits.is_fence, issue_slots[4].out_uop.is_fence
connect issue_slots[3].in_uop.bits.is_sfb, issue_slots[4].out_uop.is_sfb
connect issue_slots[3].in_uop.bits.br_type, issue_slots[4].out_uop.br_type
connect issue_slots[3].in_uop.bits.br_tag, issue_slots[4].out_uop.br_tag
connect issue_slots[3].in_uop.bits.br_mask, issue_slots[4].out_uop.br_mask
connect issue_slots[3].in_uop.bits.dis_col_sel, issue_slots[4].out_uop.dis_col_sel
connect issue_slots[3].in_uop.bits.iw_p3_bypass_hint, issue_slots[4].out_uop.iw_p3_bypass_hint
connect issue_slots[3].in_uop.bits.iw_p2_bypass_hint, issue_slots[4].out_uop.iw_p2_bypass_hint
connect issue_slots[3].in_uop.bits.iw_p1_bypass_hint, issue_slots[4].out_uop.iw_p1_bypass_hint
connect issue_slots[3].in_uop.bits.iw_p2_speculative_child, issue_slots[4].out_uop.iw_p2_speculative_child
connect issue_slots[3].in_uop.bits.iw_p1_speculative_child, issue_slots[4].out_uop.iw_p1_speculative_child
connect issue_slots[3].in_uop.bits.iw_issued_partial_dgen, issue_slots[4].out_uop.iw_issued_partial_dgen
connect issue_slots[3].in_uop.bits.iw_issued_partial_agen, issue_slots[4].out_uop.iw_issued_partial_agen
connect issue_slots[3].in_uop.bits.iw_issued, issue_slots[4].out_uop.iw_issued
connect issue_slots[3].in_uop.bits.fu_code[0], issue_slots[4].out_uop.fu_code[0]
connect issue_slots[3].in_uop.bits.fu_code[1], issue_slots[4].out_uop.fu_code[1]
connect issue_slots[3].in_uop.bits.fu_code[2], issue_slots[4].out_uop.fu_code[2]
connect issue_slots[3].in_uop.bits.fu_code[3], issue_slots[4].out_uop.fu_code[3]
connect issue_slots[3].in_uop.bits.fu_code[4], issue_slots[4].out_uop.fu_code[4]
connect issue_slots[3].in_uop.bits.fu_code[5], issue_slots[4].out_uop.fu_code[5]
connect issue_slots[3].in_uop.bits.fu_code[6], issue_slots[4].out_uop.fu_code[6]
connect issue_slots[3].in_uop.bits.fu_code[7], issue_slots[4].out_uop.fu_code[7]
connect issue_slots[3].in_uop.bits.fu_code[8], issue_slots[4].out_uop.fu_code[8]
connect issue_slots[3].in_uop.bits.fu_code[9], issue_slots[4].out_uop.fu_code[9]
connect issue_slots[3].in_uop.bits.iq_type[0], issue_slots[4].out_uop.iq_type[0]
connect issue_slots[3].in_uop.bits.iq_type[1], issue_slots[4].out_uop.iq_type[1]
connect issue_slots[3].in_uop.bits.iq_type[2], issue_slots[4].out_uop.iq_type[2]
connect issue_slots[3].in_uop.bits.iq_type[3], issue_slots[4].out_uop.iq_type[3]
connect issue_slots[3].in_uop.bits.debug_pc, issue_slots[4].out_uop.debug_pc
connect issue_slots[3].in_uop.bits.is_rvc, issue_slots[4].out_uop.is_rvc
connect issue_slots[3].in_uop.bits.debug_inst, issue_slots[4].out_uop.debug_inst
connect issue_slots[3].in_uop.bits.inst, issue_slots[4].out_uop.inst
node _T_168 = eq(shamts_oh[4], UInt<1>(0h1))
when _T_168 :
connect issue_slots[3].in_uop.valid, issue_slots[4].will_be_valid
connect issue_slots[3].in_uop.bits.debug_tsrc, issue_slots[4].out_uop.debug_tsrc
connect issue_slots[3].in_uop.bits.debug_fsrc, issue_slots[4].out_uop.debug_fsrc
connect issue_slots[3].in_uop.bits.bp_xcpt_if, issue_slots[4].out_uop.bp_xcpt_if
connect issue_slots[3].in_uop.bits.bp_debug_if, issue_slots[4].out_uop.bp_debug_if
connect issue_slots[3].in_uop.bits.xcpt_ma_if, issue_slots[4].out_uop.xcpt_ma_if
connect issue_slots[3].in_uop.bits.xcpt_ae_if, issue_slots[4].out_uop.xcpt_ae_if
connect issue_slots[3].in_uop.bits.xcpt_pf_if, issue_slots[4].out_uop.xcpt_pf_if
connect issue_slots[3].in_uop.bits.fp_typ, issue_slots[4].out_uop.fp_typ
connect issue_slots[3].in_uop.bits.fp_rm, issue_slots[4].out_uop.fp_rm
connect issue_slots[3].in_uop.bits.fp_val, issue_slots[4].out_uop.fp_val
connect issue_slots[3].in_uop.bits.fcn_op, issue_slots[4].out_uop.fcn_op
connect issue_slots[3].in_uop.bits.fcn_dw, issue_slots[4].out_uop.fcn_dw
connect issue_slots[3].in_uop.bits.frs3_en, issue_slots[4].out_uop.frs3_en
connect issue_slots[3].in_uop.bits.lrs2_rtype, issue_slots[4].out_uop.lrs2_rtype
connect issue_slots[3].in_uop.bits.lrs1_rtype, issue_slots[4].out_uop.lrs1_rtype
connect issue_slots[3].in_uop.bits.dst_rtype, issue_slots[4].out_uop.dst_rtype
connect issue_slots[3].in_uop.bits.lrs3, issue_slots[4].out_uop.lrs3
connect issue_slots[3].in_uop.bits.lrs2, issue_slots[4].out_uop.lrs2
connect issue_slots[3].in_uop.bits.lrs1, issue_slots[4].out_uop.lrs1
connect issue_slots[3].in_uop.bits.ldst, issue_slots[4].out_uop.ldst
connect issue_slots[3].in_uop.bits.ldst_is_rs1, issue_slots[4].out_uop.ldst_is_rs1
connect issue_slots[3].in_uop.bits.csr_cmd, issue_slots[4].out_uop.csr_cmd
connect issue_slots[3].in_uop.bits.flush_on_commit, issue_slots[4].out_uop.flush_on_commit
connect issue_slots[3].in_uop.bits.is_unique, issue_slots[4].out_uop.is_unique
connect issue_slots[3].in_uop.bits.uses_stq, issue_slots[4].out_uop.uses_stq
connect issue_slots[3].in_uop.bits.uses_ldq, issue_slots[4].out_uop.uses_ldq
connect issue_slots[3].in_uop.bits.mem_signed, issue_slots[4].out_uop.mem_signed
connect issue_slots[3].in_uop.bits.mem_size, issue_slots[4].out_uop.mem_size
connect issue_slots[3].in_uop.bits.mem_cmd, issue_slots[4].out_uop.mem_cmd
connect issue_slots[3].in_uop.bits.exc_cause, issue_slots[4].out_uop.exc_cause
connect issue_slots[3].in_uop.bits.exception, issue_slots[4].out_uop.exception
connect issue_slots[3].in_uop.bits.stale_pdst, issue_slots[4].out_uop.stale_pdst
connect issue_slots[3].in_uop.bits.ppred_busy, issue_slots[4].out_uop.ppred_busy
connect issue_slots[3].in_uop.bits.prs3_busy, issue_slots[4].out_uop.prs3_busy
connect issue_slots[3].in_uop.bits.prs2_busy, issue_slots[4].out_uop.prs2_busy
connect issue_slots[3].in_uop.bits.prs1_busy, issue_slots[4].out_uop.prs1_busy
connect issue_slots[3].in_uop.bits.ppred, issue_slots[4].out_uop.ppred
connect issue_slots[3].in_uop.bits.prs3, issue_slots[4].out_uop.prs3
connect issue_slots[3].in_uop.bits.prs2, issue_slots[4].out_uop.prs2
connect issue_slots[3].in_uop.bits.prs1, issue_slots[4].out_uop.prs1
connect issue_slots[3].in_uop.bits.pdst, issue_slots[4].out_uop.pdst
connect issue_slots[3].in_uop.bits.rxq_idx, issue_slots[4].out_uop.rxq_idx
connect issue_slots[3].in_uop.bits.stq_idx, issue_slots[4].out_uop.stq_idx
connect issue_slots[3].in_uop.bits.ldq_idx, issue_slots[4].out_uop.ldq_idx
connect issue_slots[3].in_uop.bits.rob_idx, issue_slots[4].out_uop.rob_idx
connect issue_slots[3].in_uop.bits.fp_ctrl.vec, issue_slots[4].out_uop.fp_ctrl.vec
connect issue_slots[3].in_uop.bits.fp_ctrl.wflags, issue_slots[4].out_uop.fp_ctrl.wflags
connect issue_slots[3].in_uop.bits.fp_ctrl.sqrt, issue_slots[4].out_uop.fp_ctrl.sqrt
connect issue_slots[3].in_uop.bits.fp_ctrl.div, issue_slots[4].out_uop.fp_ctrl.div
connect issue_slots[3].in_uop.bits.fp_ctrl.fma, issue_slots[4].out_uop.fp_ctrl.fma
connect issue_slots[3].in_uop.bits.fp_ctrl.fastpipe, issue_slots[4].out_uop.fp_ctrl.fastpipe
connect issue_slots[3].in_uop.bits.fp_ctrl.toint, issue_slots[4].out_uop.fp_ctrl.toint
connect issue_slots[3].in_uop.bits.fp_ctrl.fromint, issue_slots[4].out_uop.fp_ctrl.fromint
connect issue_slots[3].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[4].out_uop.fp_ctrl.typeTagOut
connect issue_slots[3].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[4].out_uop.fp_ctrl.typeTagIn
connect issue_slots[3].in_uop.bits.fp_ctrl.swap23, issue_slots[4].out_uop.fp_ctrl.swap23
connect issue_slots[3].in_uop.bits.fp_ctrl.swap12, issue_slots[4].out_uop.fp_ctrl.swap12
connect issue_slots[3].in_uop.bits.fp_ctrl.ren3, issue_slots[4].out_uop.fp_ctrl.ren3
connect issue_slots[3].in_uop.bits.fp_ctrl.ren2, issue_slots[4].out_uop.fp_ctrl.ren2
connect issue_slots[3].in_uop.bits.fp_ctrl.ren1, issue_slots[4].out_uop.fp_ctrl.ren1
connect issue_slots[3].in_uop.bits.fp_ctrl.wen, issue_slots[4].out_uop.fp_ctrl.wen
connect issue_slots[3].in_uop.bits.fp_ctrl.ldst, issue_slots[4].out_uop.fp_ctrl.ldst
connect issue_slots[3].in_uop.bits.op2_sel, issue_slots[4].out_uop.op2_sel
connect issue_slots[3].in_uop.bits.op1_sel, issue_slots[4].out_uop.op1_sel
connect issue_slots[3].in_uop.bits.imm_packed, issue_slots[4].out_uop.imm_packed
connect issue_slots[3].in_uop.bits.pimm, issue_slots[4].out_uop.pimm
connect issue_slots[3].in_uop.bits.imm_sel, issue_slots[4].out_uop.imm_sel
connect issue_slots[3].in_uop.bits.imm_rename, issue_slots[4].out_uop.imm_rename
connect issue_slots[3].in_uop.bits.taken, issue_slots[4].out_uop.taken
connect issue_slots[3].in_uop.bits.pc_lob, issue_slots[4].out_uop.pc_lob
connect issue_slots[3].in_uop.bits.edge_inst, issue_slots[4].out_uop.edge_inst
connect issue_slots[3].in_uop.bits.ftq_idx, issue_slots[4].out_uop.ftq_idx
connect issue_slots[3].in_uop.bits.is_mov, issue_slots[4].out_uop.is_mov
connect issue_slots[3].in_uop.bits.is_rocc, issue_slots[4].out_uop.is_rocc
connect issue_slots[3].in_uop.bits.is_sys_pc2epc, issue_slots[4].out_uop.is_sys_pc2epc
connect issue_slots[3].in_uop.bits.is_eret, issue_slots[4].out_uop.is_eret
connect issue_slots[3].in_uop.bits.is_amo, issue_slots[4].out_uop.is_amo
connect issue_slots[3].in_uop.bits.is_sfence, issue_slots[4].out_uop.is_sfence
connect issue_slots[3].in_uop.bits.is_fencei, issue_slots[4].out_uop.is_fencei
connect issue_slots[3].in_uop.bits.is_fence, issue_slots[4].out_uop.is_fence
connect issue_slots[3].in_uop.bits.is_sfb, issue_slots[4].out_uop.is_sfb
connect issue_slots[3].in_uop.bits.br_type, issue_slots[4].out_uop.br_type
connect issue_slots[3].in_uop.bits.br_tag, issue_slots[4].out_uop.br_tag
connect issue_slots[3].in_uop.bits.br_mask, issue_slots[4].out_uop.br_mask
connect issue_slots[3].in_uop.bits.dis_col_sel, issue_slots[4].out_uop.dis_col_sel
connect issue_slots[3].in_uop.bits.iw_p3_bypass_hint, issue_slots[4].out_uop.iw_p3_bypass_hint
connect issue_slots[3].in_uop.bits.iw_p2_bypass_hint, issue_slots[4].out_uop.iw_p2_bypass_hint
connect issue_slots[3].in_uop.bits.iw_p1_bypass_hint, issue_slots[4].out_uop.iw_p1_bypass_hint
connect issue_slots[3].in_uop.bits.iw_p2_speculative_child, issue_slots[4].out_uop.iw_p2_speculative_child
connect issue_slots[3].in_uop.bits.iw_p1_speculative_child, issue_slots[4].out_uop.iw_p1_speculative_child
connect issue_slots[3].in_uop.bits.iw_issued_partial_dgen, issue_slots[4].out_uop.iw_issued_partial_dgen
connect issue_slots[3].in_uop.bits.iw_issued_partial_agen, issue_slots[4].out_uop.iw_issued_partial_agen
connect issue_slots[3].in_uop.bits.iw_issued, issue_slots[4].out_uop.iw_issued
connect issue_slots[3].in_uop.bits.fu_code[0], issue_slots[4].out_uop.fu_code[0]
connect issue_slots[3].in_uop.bits.fu_code[1], issue_slots[4].out_uop.fu_code[1]
connect issue_slots[3].in_uop.bits.fu_code[2], issue_slots[4].out_uop.fu_code[2]
connect issue_slots[3].in_uop.bits.fu_code[3], issue_slots[4].out_uop.fu_code[3]
connect issue_slots[3].in_uop.bits.fu_code[4], issue_slots[4].out_uop.fu_code[4]
connect issue_slots[3].in_uop.bits.fu_code[5], issue_slots[4].out_uop.fu_code[5]
connect issue_slots[3].in_uop.bits.fu_code[6], issue_slots[4].out_uop.fu_code[6]
connect issue_slots[3].in_uop.bits.fu_code[7], issue_slots[4].out_uop.fu_code[7]
connect issue_slots[3].in_uop.bits.fu_code[8], issue_slots[4].out_uop.fu_code[8]
connect issue_slots[3].in_uop.bits.fu_code[9], issue_slots[4].out_uop.fu_code[9]
connect issue_slots[3].in_uop.bits.iq_type[0], issue_slots[4].out_uop.iq_type[0]
connect issue_slots[3].in_uop.bits.iq_type[1], issue_slots[4].out_uop.iq_type[1]
connect issue_slots[3].in_uop.bits.iq_type[2], issue_slots[4].out_uop.iq_type[2]
connect issue_slots[3].in_uop.bits.iq_type[3], issue_slots[4].out_uop.iq_type[3]
connect issue_slots[3].in_uop.bits.debug_pc, issue_slots[4].out_uop.debug_pc
connect issue_slots[3].in_uop.bits.is_rvc, issue_slots[4].out_uop.is_rvc
connect issue_slots[3].in_uop.bits.debug_inst, issue_slots[4].out_uop.debug_inst
connect issue_slots[3].in_uop.bits.inst, issue_slots[4].out_uop.inst
node _T_169 = eq(shamts_oh[5], UInt<2>(0h2))
when _T_169 :
connect issue_slots[3].in_uop.valid, issue_slots[5].will_be_valid
connect issue_slots[3].in_uop.bits.debug_tsrc, issue_slots[5].out_uop.debug_tsrc
connect issue_slots[3].in_uop.bits.debug_fsrc, issue_slots[5].out_uop.debug_fsrc
connect issue_slots[3].in_uop.bits.bp_xcpt_if, issue_slots[5].out_uop.bp_xcpt_if
connect issue_slots[3].in_uop.bits.bp_debug_if, issue_slots[5].out_uop.bp_debug_if
connect issue_slots[3].in_uop.bits.xcpt_ma_if, issue_slots[5].out_uop.xcpt_ma_if
connect issue_slots[3].in_uop.bits.xcpt_ae_if, issue_slots[5].out_uop.xcpt_ae_if
connect issue_slots[3].in_uop.bits.xcpt_pf_if, issue_slots[5].out_uop.xcpt_pf_if
connect issue_slots[3].in_uop.bits.fp_typ, issue_slots[5].out_uop.fp_typ
connect issue_slots[3].in_uop.bits.fp_rm, issue_slots[5].out_uop.fp_rm
connect issue_slots[3].in_uop.bits.fp_val, issue_slots[5].out_uop.fp_val
connect issue_slots[3].in_uop.bits.fcn_op, issue_slots[5].out_uop.fcn_op
connect issue_slots[3].in_uop.bits.fcn_dw, issue_slots[5].out_uop.fcn_dw
connect issue_slots[3].in_uop.bits.frs3_en, issue_slots[5].out_uop.frs3_en
connect issue_slots[3].in_uop.bits.lrs2_rtype, issue_slots[5].out_uop.lrs2_rtype
connect issue_slots[3].in_uop.bits.lrs1_rtype, issue_slots[5].out_uop.lrs1_rtype
connect issue_slots[3].in_uop.bits.dst_rtype, issue_slots[5].out_uop.dst_rtype
connect issue_slots[3].in_uop.bits.lrs3, issue_slots[5].out_uop.lrs3
connect issue_slots[3].in_uop.bits.lrs2, issue_slots[5].out_uop.lrs2
connect issue_slots[3].in_uop.bits.lrs1, issue_slots[5].out_uop.lrs1
connect issue_slots[3].in_uop.bits.ldst, issue_slots[5].out_uop.ldst
connect issue_slots[3].in_uop.bits.ldst_is_rs1, issue_slots[5].out_uop.ldst_is_rs1
connect issue_slots[3].in_uop.bits.csr_cmd, issue_slots[5].out_uop.csr_cmd
connect issue_slots[3].in_uop.bits.flush_on_commit, issue_slots[5].out_uop.flush_on_commit
connect issue_slots[3].in_uop.bits.is_unique, issue_slots[5].out_uop.is_unique
connect issue_slots[3].in_uop.bits.uses_stq, issue_slots[5].out_uop.uses_stq
connect issue_slots[3].in_uop.bits.uses_ldq, issue_slots[5].out_uop.uses_ldq
connect issue_slots[3].in_uop.bits.mem_signed, issue_slots[5].out_uop.mem_signed
connect issue_slots[3].in_uop.bits.mem_size, issue_slots[5].out_uop.mem_size
connect issue_slots[3].in_uop.bits.mem_cmd, issue_slots[5].out_uop.mem_cmd
connect issue_slots[3].in_uop.bits.exc_cause, issue_slots[5].out_uop.exc_cause
connect issue_slots[3].in_uop.bits.exception, issue_slots[5].out_uop.exception
connect issue_slots[3].in_uop.bits.stale_pdst, issue_slots[5].out_uop.stale_pdst
connect issue_slots[3].in_uop.bits.ppred_busy, issue_slots[5].out_uop.ppred_busy
connect issue_slots[3].in_uop.bits.prs3_busy, issue_slots[5].out_uop.prs3_busy
connect issue_slots[3].in_uop.bits.prs2_busy, issue_slots[5].out_uop.prs2_busy
connect issue_slots[3].in_uop.bits.prs1_busy, issue_slots[5].out_uop.prs1_busy
connect issue_slots[3].in_uop.bits.ppred, issue_slots[5].out_uop.ppred
connect issue_slots[3].in_uop.bits.prs3, issue_slots[5].out_uop.prs3
connect issue_slots[3].in_uop.bits.prs2, issue_slots[5].out_uop.prs2
connect issue_slots[3].in_uop.bits.prs1, issue_slots[5].out_uop.prs1
connect issue_slots[3].in_uop.bits.pdst, issue_slots[5].out_uop.pdst
connect issue_slots[3].in_uop.bits.rxq_idx, issue_slots[5].out_uop.rxq_idx
connect issue_slots[3].in_uop.bits.stq_idx, issue_slots[5].out_uop.stq_idx
connect issue_slots[3].in_uop.bits.ldq_idx, issue_slots[5].out_uop.ldq_idx
connect issue_slots[3].in_uop.bits.rob_idx, issue_slots[5].out_uop.rob_idx
connect issue_slots[3].in_uop.bits.fp_ctrl.vec, issue_slots[5].out_uop.fp_ctrl.vec
connect issue_slots[3].in_uop.bits.fp_ctrl.wflags, issue_slots[5].out_uop.fp_ctrl.wflags
connect issue_slots[3].in_uop.bits.fp_ctrl.sqrt, issue_slots[5].out_uop.fp_ctrl.sqrt
connect issue_slots[3].in_uop.bits.fp_ctrl.div, issue_slots[5].out_uop.fp_ctrl.div
connect issue_slots[3].in_uop.bits.fp_ctrl.fma, issue_slots[5].out_uop.fp_ctrl.fma
connect issue_slots[3].in_uop.bits.fp_ctrl.fastpipe, issue_slots[5].out_uop.fp_ctrl.fastpipe
connect issue_slots[3].in_uop.bits.fp_ctrl.toint, issue_slots[5].out_uop.fp_ctrl.toint
connect issue_slots[3].in_uop.bits.fp_ctrl.fromint, issue_slots[5].out_uop.fp_ctrl.fromint
connect issue_slots[3].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[5].out_uop.fp_ctrl.typeTagOut
connect issue_slots[3].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[5].out_uop.fp_ctrl.typeTagIn
connect issue_slots[3].in_uop.bits.fp_ctrl.swap23, issue_slots[5].out_uop.fp_ctrl.swap23
connect issue_slots[3].in_uop.bits.fp_ctrl.swap12, issue_slots[5].out_uop.fp_ctrl.swap12
connect issue_slots[3].in_uop.bits.fp_ctrl.ren3, issue_slots[5].out_uop.fp_ctrl.ren3
connect issue_slots[3].in_uop.bits.fp_ctrl.ren2, issue_slots[5].out_uop.fp_ctrl.ren2
connect issue_slots[3].in_uop.bits.fp_ctrl.ren1, issue_slots[5].out_uop.fp_ctrl.ren1
connect issue_slots[3].in_uop.bits.fp_ctrl.wen, issue_slots[5].out_uop.fp_ctrl.wen
connect issue_slots[3].in_uop.bits.fp_ctrl.ldst, issue_slots[5].out_uop.fp_ctrl.ldst
connect issue_slots[3].in_uop.bits.op2_sel, issue_slots[5].out_uop.op2_sel
connect issue_slots[3].in_uop.bits.op1_sel, issue_slots[5].out_uop.op1_sel
connect issue_slots[3].in_uop.bits.imm_packed, issue_slots[5].out_uop.imm_packed
connect issue_slots[3].in_uop.bits.pimm, issue_slots[5].out_uop.pimm
connect issue_slots[3].in_uop.bits.imm_sel, issue_slots[5].out_uop.imm_sel
connect issue_slots[3].in_uop.bits.imm_rename, issue_slots[5].out_uop.imm_rename
connect issue_slots[3].in_uop.bits.taken, issue_slots[5].out_uop.taken
connect issue_slots[3].in_uop.bits.pc_lob, issue_slots[5].out_uop.pc_lob
connect issue_slots[3].in_uop.bits.edge_inst, issue_slots[5].out_uop.edge_inst
connect issue_slots[3].in_uop.bits.ftq_idx, issue_slots[5].out_uop.ftq_idx
connect issue_slots[3].in_uop.bits.is_mov, issue_slots[5].out_uop.is_mov
connect issue_slots[3].in_uop.bits.is_rocc, issue_slots[5].out_uop.is_rocc
connect issue_slots[3].in_uop.bits.is_sys_pc2epc, issue_slots[5].out_uop.is_sys_pc2epc
connect issue_slots[3].in_uop.bits.is_eret, issue_slots[5].out_uop.is_eret
connect issue_slots[3].in_uop.bits.is_amo, issue_slots[5].out_uop.is_amo
connect issue_slots[3].in_uop.bits.is_sfence, issue_slots[5].out_uop.is_sfence
connect issue_slots[3].in_uop.bits.is_fencei, issue_slots[5].out_uop.is_fencei
connect issue_slots[3].in_uop.bits.is_fence, issue_slots[5].out_uop.is_fence
connect issue_slots[3].in_uop.bits.is_sfb, issue_slots[5].out_uop.is_sfb
connect issue_slots[3].in_uop.bits.br_type, issue_slots[5].out_uop.br_type
connect issue_slots[3].in_uop.bits.br_tag, issue_slots[5].out_uop.br_tag
connect issue_slots[3].in_uop.bits.br_mask, issue_slots[5].out_uop.br_mask
connect issue_slots[3].in_uop.bits.dis_col_sel, issue_slots[5].out_uop.dis_col_sel
connect issue_slots[3].in_uop.bits.iw_p3_bypass_hint, issue_slots[5].out_uop.iw_p3_bypass_hint
connect issue_slots[3].in_uop.bits.iw_p2_bypass_hint, issue_slots[5].out_uop.iw_p2_bypass_hint
connect issue_slots[3].in_uop.bits.iw_p1_bypass_hint, issue_slots[5].out_uop.iw_p1_bypass_hint
connect issue_slots[3].in_uop.bits.iw_p2_speculative_child, issue_slots[5].out_uop.iw_p2_speculative_child
connect issue_slots[3].in_uop.bits.iw_p1_speculative_child, issue_slots[5].out_uop.iw_p1_speculative_child
connect issue_slots[3].in_uop.bits.iw_issued_partial_dgen, issue_slots[5].out_uop.iw_issued_partial_dgen
connect issue_slots[3].in_uop.bits.iw_issued_partial_agen, issue_slots[5].out_uop.iw_issued_partial_agen
connect issue_slots[3].in_uop.bits.iw_issued, issue_slots[5].out_uop.iw_issued
connect issue_slots[3].in_uop.bits.fu_code[0], issue_slots[5].out_uop.fu_code[0]
connect issue_slots[3].in_uop.bits.fu_code[1], issue_slots[5].out_uop.fu_code[1]
connect issue_slots[3].in_uop.bits.fu_code[2], issue_slots[5].out_uop.fu_code[2]
connect issue_slots[3].in_uop.bits.fu_code[3], issue_slots[5].out_uop.fu_code[3]
connect issue_slots[3].in_uop.bits.fu_code[4], issue_slots[5].out_uop.fu_code[4]
connect issue_slots[3].in_uop.bits.fu_code[5], issue_slots[5].out_uop.fu_code[5]
connect issue_slots[3].in_uop.bits.fu_code[6], issue_slots[5].out_uop.fu_code[6]
connect issue_slots[3].in_uop.bits.fu_code[7], issue_slots[5].out_uop.fu_code[7]
connect issue_slots[3].in_uop.bits.fu_code[8], issue_slots[5].out_uop.fu_code[8]
connect issue_slots[3].in_uop.bits.fu_code[9], issue_slots[5].out_uop.fu_code[9]
connect issue_slots[3].in_uop.bits.iq_type[0], issue_slots[5].out_uop.iq_type[0]
connect issue_slots[3].in_uop.bits.iq_type[1], issue_slots[5].out_uop.iq_type[1]
connect issue_slots[3].in_uop.bits.iq_type[2], issue_slots[5].out_uop.iq_type[2]
connect issue_slots[3].in_uop.bits.iq_type[3], issue_slots[5].out_uop.iq_type[3]
connect issue_slots[3].in_uop.bits.debug_pc, issue_slots[5].out_uop.debug_pc
connect issue_slots[3].in_uop.bits.is_rvc, issue_slots[5].out_uop.is_rvc
connect issue_slots[3].in_uop.bits.debug_inst, issue_slots[5].out_uop.debug_inst
connect issue_slots[3].in_uop.bits.inst, issue_slots[5].out_uop.inst
node _issue_slots_3_clear_T = neq(shamts_oh[3], UInt<1>(0h0))
connect issue_slots[3].clear, _issue_slots_3_clear_T
connect issue_slots[4].in_uop.valid, UInt<1>(0h0)
connect issue_slots[4].in_uop.bits.debug_tsrc, issue_slots[5].out_uop.debug_tsrc
connect issue_slots[4].in_uop.bits.debug_fsrc, issue_slots[5].out_uop.debug_fsrc
connect issue_slots[4].in_uop.bits.bp_xcpt_if, issue_slots[5].out_uop.bp_xcpt_if
connect issue_slots[4].in_uop.bits.bp_debug_if, issue_slots[5].out_uop.bp_debug_if
connect issue_slots[4].in_uop.bits.xcpt_ma_if, issue_slots[5].out_uop.xcpt_ma_if
connect issue_slots[4].in_uop.bits.xcpt_ae_if, issue_slots[5].out_uop.xcpt_ae_if
connect issue_slots[4].in_uop.bits.xcpt_pf_if, issue_slots[5].out_uop.xcpt_pf_if
connect issue_slots[4].in_uop.bits.fp_typ, issue_slots[5].out_uop.fp_typ
connect issue_slots[4].in_uop.bits.fp_rm, issue_slots[5].out_uop.fp_rm
connect issue_slots[4].in_uop.bits.fp_val, issue_slots[5].out_uop.fp_val
connect issue_slots[4].in_uop.bits.fcn_op, issue_slots[5].out_uop.fcn_op
connect issue_slots[4].in_uop.bits.fcn_dw, issue_slots[5].out_uop.fcn_dw
connect issue_slots[4].in_uop.bits.frs3_en, issue_slots[5].out_uop.frs3_en
connect issue_slots[4].in_uop.bits.lrs2_rtype, issue_slots[5].out_uop.lrs2_rtype
connect issue_slots[4].in_uop.bits.lrs1_rtype, issue_slots[5].out_uop.lrs1_rtype
connect issue_slots[4].in_uop.bits.dst_rtype, issue_slots[5].out_uop.dst_rtype
connect issue_slots[4].in_uop.bits.lrs3, issue_slots[5].out_uop.lrs3
connect issue_slots[4].in_uop.bits.lrs2, issue_slots[5].out_uop.lrs2
connect issue_slots[4].in_uop.bits.lrs1, issue_slots[5].out_uop.lrs1
connect issue_slots[4].in_uop.bits.ldst, issue_slots[5].out_uop.ldst
connect issue_slots[4].in_uop.bits.ldst_is_rs1, issue_slots[5].out_uop.ldst_is_rs1
connect issue_slots[4].in_uop.bits.csr_cmd, issue_slots[5].out_uop.csr_cmd
connect issue_slots[4].in_uop.bits.flush_on_commit, issue_slots[5].out_uop.flush_on_commit
connect issue_slots[4].in_uop.bits.is_unique, issue_slots[5].out_uop.is_unique
connect issue_slots[4].in_uop.bits.uses_stq, issue_slots[5].out_uop.uses_stq
connect issue_slots[4].in_uop.bits.uses_ldq, issue_slots[5].out_uop.uses_ldq
connect issue_slots[4].in_uop.bits.mem_signed, issue_slots[5].out_uop.mem_signed
connect issue_slots[4].in_uop.bits.mem_size, issue_slots[5].out_uop.mem_size
connect issue_slots[4].in_uop.bits.mem_cmd, issue_slots[5].out_uop.mem_cmd
connect issue_slots[4].in_uop.bits.exc_cause, issue_slots[5].out_uop.exc_cause
connect issue_slots[4].in_uop.bits.exception, issue_slots[5].out_uop.exception
connect issue_slots[4].in_uop.bits.stale_pdst, issue_slots[5].out_uop.stale_pdst
connect issue_slots[4].in_uop.bits.ppred_busy, issue_slots[5].out_uop.ppred_busy
connect issue_slots[4].in_uop.bits.prs3_busy, issue_slots[5].out_uop.prs3_busy
connect issue_slots[4].in_uop.bits.prs2_busy, issue_slots[5].out_uop.prs2_busy
connect issue_slots[4].in_uop.bits.prs1_busy, issue_slots[5].out_uop.prs1_busy
connect issue_slots[4].in_uop.bits.ppred, issue_slots[5].out_uop.ppred
connect issue_slots[4].in_uop.bits.prs3, issue_slots[5].out_uop.prs3
connect issue_slots[4].in_uop.bits.prs2, issue_slots[5].out_uop.prs2
connect issue_slots[4].in_uop.bits.prs1, issue_slots[5].out_uop.prs1
connect issue_slots[4].in_uop.bits.pdst, issue_slots[5].out_uop.pdst
connect issue_slots[4].in_uop.bits.rxq_idx, issue_slots[5].out_uop.rxq_idx
connect issue_slots[4].in_uop.bits.stq_idx, issue_slots[5].out_uop.stq_idx
connect issue_slots[4].in_uop.bits.ldq_idx, issue_slots[5].out_uop.ldq_idx
connect issue_slots[4].in_uop.bits.rob_idx, issue_slots[5].out_uop.rob_idx
connect issue_slots[4].in_uop.bits.fp_ctrl.vec, issue_slots[5].out_uop.fp_ctrl.vec
connect issue_slots[4].in_uop.bits.fp_ctrl.wflags, issue_slots[5].out_uop.fp_ctrl.wflags
connect issue_slots[4].in_uop.bits.fp_ctrl.sqrt, issue_slots[5].out_uop.fp_ctrl.sqrt
connect issue_slots[4].in_uop.bits.fp_ctrl.div, issue_slots[5].out_uop.fp_ctrl.div
connect issue_slots[4].in_uop.bits.fp_ctrl.fma, issue_slots[5].out_uop.fp_ctrl.fma
connect issue_slots[4].in_uop.bits.fp_ctrl.fastpipe, issue_slots[5].out_uop.fp_ctrl.fastpipe
connect issue_slots[4].in_uop.bits.fp_ctrl.toint, issue_slots[5].out_uop.fp_ctrl.toint
connect issue_slots[4].in_uop.bits.fp_ctrl.fromint, issue_slots[5].out_uop.fp_ctrl.fromint
connect issue_slots[4].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[5].out_uop.fp_ctrl.typeTagOut
connect issue_slots[4].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[5].out_uop.fp_ctrl.typeTagIn
connect issue_slots[4].in_uop.bits.fp_ctrl.swap23, issue_slots[5].out_uop.fp_ctrl.swap23
connect issue_slots[4].in_uop.bits.fp_ctrl.swap12, issue_slots[5].out_uop.fp_ctrl.swap12
connect issue_slots[4].in_uop.bits.fp_ctrl.ren3, issue_slots[5].out_uop.fp_ctrl.ren3
connect issue_slots[4].in_uop.bits.fp_ctrl.ren2, issue_slots[5].out_uop.fp_ctrl.ren2
connect issue_slots[4].in_uop.bits.fp_ctrl.ren1, issue_slots[5].out_uop.fp_ctrl.ren1
connect issue_slots[4].in_uop.bits.fp_ctrl.wen, issue_slots[5].out_uop.fp_ctrl.wen
connect issue_slots[4].in_uop.bits.fp_ctrl.ldst, issue_slots[5].out_uop.fp_ctrl.ldst
connect issue_slots[4].in_uop.bits.op2_sel, issue_slots[5].out_uop.op2_sel
connect issue_slots[4].in_uop.bits.op1_sel, issue_slots[5].out_uop.op1_sel
connect issue_slots[4].in_uop.bits.imm_packed, issue_slots[5].out_uop.imm_packed
connect issue_slots[4].in_uop.bits.pimm, issue_slots[5].out_uop.pimm
connect issue_slots[4].in_uop.bits.imm_sel, issue_slots[5].out_uop.imm_sel
connect issue_slots[4].in_uop.bits.imm_rename, issue_slots[5].out_uop.imm_rename
connect issue_slots[4].in_uop.bits.taken, issue_slots[5].out_uop.taken
connect issue_slots[4].in_uop.bits.pc_lob, issue_slots[5].out_uop.pc_lob
connect issue_slots[4].in_uop.bits.edge_inst, issue_slots[5].out_uop.edge_inst
connect issue_slots[4].in_uop.bits.ftq_idx, issue_slots[5].out_uop.ftq_idx
connect issue_slots[4].in_uop.bits.is_mov, issue_slots[5].out_uop.is_mov
connect issue_slots[4].in_uop.bits.is_rocc, issue_slots[5].out_uop.is_rocc
connect issue_slots[4].in_uop.bits.is_sys_pc2epc, issue_slots[5].out_uop.is_sys_pc2epc
connect issue_slots[4].in_uop.bits.is_eret, issue_slots[5].out_uop.is_eret
connect issue_slots[4].in_uop.bits.is_amo, issue_slots[5].out_uop.is_amo
connect issue_slots[4].in_uop.bits.is_sfence, issue_slots[5].out_uop.is_sfence
connect issue_slots[4].in_uop.bits.is_fencei, issue_slots[5].out_uop.is_fencei
connect issue_slots[4].in_uop.bits.is_fence, issue_slots[5].out_uop.is_fence
connect issue_slots[4].in_uop.bits.is_sfb, issue_slots[5].out_uop.is_sfb
connect issue_slots[4].in_uop.bits.br_type, issue_slots[5].out_uop.br_type
connect issue_slots[4].in_uop.bits.br_tag, issue_slots[5].out_uop.br_tag
connect issue_slots[4].in_uop.bits.br_mask, issue_slots[5].out_uop.br_mask
connect issue_slots[4].in_uop.bits.dis_col_sel, issue_slots[5].out_uop.dis_col_sel
connect issue_slots[4].in_uop.bits.iw_p3_bypass_hint, issue_slots[5].out_uop.iw_p3_bypass_hint
connect issue_slots[4].in_uop.bits.iw_p2_bypass_hint, issue_slots[5].out_uop.iw_p2_bypass_hint
connect issue_slots[4].in_uop.bits.iw_p1_bypass_hint, issue_slots[5].out_uop.iw_p1_bypass_hint
connect issue_slots[4].in_uop.bits.iw_p2_speculative_child, issue_slots[5].out_uop.iw_p2_speculative_child
connect issue_slots[4].in_uop.bits.iw_p1_speculative_child, issue_slots[5].out_uop.iw_p1_speculative_child
connect issue_slots[4].in_uop.bits.iw_issued_partial_dgen, issue_slots[5].out_uop.iw_issued_partial_dgen
connect issue_slots[4].in_uop.bits.iw_issued_partial_agen, issue_slots[5].out_uop.iw_issued_partial_agen
connect issue_slots[4].in_uop.bits.iw_issued, issue_slots[5].out_uop.iw_issued
connect issue_slots[4].in_uop.bits.fu_code[0], issue_slots[5].out_uop.fu_code[0]
connect issue_slots[4].in_uop.bits.fu_code[1], issue_slots[5].out_uop.fu_code[1]
connect issue_slots[4].in_uop.bits.fu_code[2], issue_slots[5].out_uop.fu_code[2]
connect issue_slots[4].in_uop.bits.fu_code[3], issue_slots[5].out_uop.fu_code[3]
connect issue_slots[4].in_uop.bits.fu_code[4], issue_slots[5].out_uop.fu_code[4]
connect issue_slots[4].in_uop.bits.fu_code[5], issue_slots[5].out_uop.fu_code[5]
connect issue_slots[4].in_uop.bits.fu_code[6], issue_slots[5].out_uop.fu_code[6]
connect issue_slots[4].in_uop.bits.fu_code[7], issue_slots[5].out_uop.fu_code[7]
connect issue_slots[4].in_uop.bits.fu_code[8], issue_slots[5].out_uop.fu_code[8]
connect issue_slots[4].in_uop.bits.fu_code[9], issue_slots[5].out_uop.fu_code[9]
connect issue_slots[4].in_uop.bits.iq_type[0], issue_slots[5].out_uop.iq_type[0]
connect issue_slots[4].in_uop.bits.iq_type[1], issue_slots[5].out_uop.iq_type[1]
connect issue_slots[4].in_uop.bits.iq_type[2], issue_slots[5].out_uop.iq_type[2]
connect issue_slots[4].in_uop.bits.iq_type[3], issue_slots[5].out_uop.iq_type[3]
connect issue_slots[4].in_uop.bits.debug_pc, issue_slots[5].out_uop.debug_pc
connect issue_slots[4].in_uop.bits.is_rvc, issue_slots[5].out_uop.is_rvc
connect issue_slots[4].in_uop.bits.debug_inst, issue_slots[5].out_uop.debug_inst
connect issue_slots[4].in_uop.bits.inst, issue_slots[5].out_uop.inst
node _T_170 = eq(shamts_oh[5], UInt<1>(0h1))
when _T_170 :
connect issue_slots[4].in_uop.valid, issue_slots[5].will_be_valid
connect issue_slots[4].in_uop.bits.debug_tsrc, issue_slots[5].out_uop.debug_tsrc
connect issue_slots[4].in_uop.bits.debug_fsrc, issue_slots[5].out_uop.debug_fsrc
connect issue_slots[4].in_uop.bits.bp_xcpt_if, issue_slots[5].out_uop.bp_xcpt_if
connect issue_slots[4].in_uop.bits.bp_debug_if, issue_slots[5].out_uop.bp_debug_if
connect issue_slots[4].in_uop.bits.xcpt_ma_if, issue_slots[5].out_uop.xcpt_ma_if
connect issue_slots[4].in_uop.bits.xcpt_ae_if, issue_slots[5].out_uop.xcpt_ae_if
connect issue_slots[4].in_uop.bits.xcpt_pf_if, issue_slots[5].out_uop.xcpt_pf_if
connect issue_slots[4].in_uop.bits.fp_typ, issue_slots[5].out_uop.fp_typ
connect issue_slots[4].in_uop.bits.fp_rm, issue_slots[5].out_uop.fp_rm
connect issue_slots[4].in_uop.bits.fp_val, issue_slots[5].out_uop.fp_val
connect issue_slots[4].in_uop.bits.fcn_op, issue_slots[5].out_uop.fcn_op
connect issue_slots[4].in_uop.bits.fcn_dw, issue_slots[5].out_uop.fcn_dw
connect issue_slots[4].in_uop.bits.frs3_en, issue_slots[5].out_uop.frs3_en
connect issue_slots[4].in_uop.bits.lrs2_rtype, issue_slots[5].out_uop.lrs2_rtype
connect issue_slots[4].in_uop.bits.lrs1_rtype, issue_slots[5].out_uop.lrs1_rtype
connect issue_slots[4].in_uop.bits.dst_rtype, issue_slots[5].out_uop.dst_rtype
connect issue_slots[4].in_uop.bits.lrs3, issue_slots[5].out_uop.lrs3
connect issue_slots[4].in_uop.bits.lrs2, issue_slots[5].out_uop.lrs2
connect issue_slots[4].in_uop.bits.lrs1, issue_slots[5].out_uop.lrs1
connect issue_slots[4].in_uop.bits.ldst, issue_slots[5].out_uop.ldst
connect issue_slots[4].in_uop.bits.ldst_is_rs1, issue_slots[5].out_uop.ldst_is_rs1
connect issue_slots[4].in_uop.bits.csr_cmd, issue_slots[5].out_uop.csr_cmd
connect issue_slots[4].in_uop.bits.flush_on_commit, issue_slots[5].out_uop.flush_on_commit
connect issue_slots[4].in_uop.bits.is_unique, issue_slots[5].out_uop.is_unique
connect issue_slots[4].in_uop.bits.uses_stq, issue_slots[5].out_uop.uses_stq
connect issue_slots[4].in_uop.bits.uses_ldq, issue_slots[5].out_uop.uses_ldq
connect issue_slots[4].in_uop.bits.mem_signed, issue_slots[5].out_uop.mem_signed
connect issue_slots[4].in_uop.bits.mem_size, issue_slots[5].out_uop.mem_size
connect issue_slots[4].in_uop.bits.mem_cmd, issue_slots[5].out_uop.mem_cmd
connect issue_slots[4].in_uop.bits.exc_cause, issue_slots[5].out_uop.exc_cause
connect issue_slots[4].in_uop.bits.exception, issue_slots[5].out_uop.exception
connect issue_slots[4].in_uop.bits.stale_pdst, issue_slots[5].out_uop.stale_pdst
connect issue_slots[4].in_uop.bits.ppred_busy, issue_slots[5].out_uop.ppred_busy
connect issue_slots[4].in_uop.bits.prs3_busy, issue_slots[5].out_uop.prs3_busy
connect issue_slots[4].in_uop.bits.prs2_busy, issue_slots[5].out_uop.prs2_busy
connect issue_slots[4].in_uop.bits.prs1_busy, issue_slots[5].out_uop.prs1_busy
connect issue_slots[4].in_uop.bits.ppred, issue_slots[5].out_uop.ppred
connect issue_slots[4].in_uop.bits.prs3, issue_slots[5].out_uop.prs3
connect issue_slots[4].in_uop.bits.prs2, issue_slots[5].out_uop.prs2
connect issue_slots[4].in_uop.bits.prs1, issue_slots[5].out_uop.prs1
connect issue_slots[4].in_uop.bits.pdst, issue_slots[5].out_uop.pdst
connect issue_slots[4].in_uop.bits.rxq_idx, issue_slots[5].out_uop.rxq_idx
connect issue_slots[4].in_uop.bits.stq_idx, issue_slots[5].out_uop.stq_idx
connect issue_slots[4].in_uop.bits.ldq_idx, issue_slots[5].out_uop.ldq_idx
connect issue_slots[4].in_uop.bits.rob_idx, issue_slots[5].out_uop.rob_idx
connect issue_slots[4].in_uop.bits.fp_ctrl.vec, issue_slots[5].out_uop.fp_ctrl.vec
connect issue_slots[4].in_uop.bits.fp_ctrl.wflags, issue_slots[5].out_uop.fp_ctrl.wflags
connect issue_slots[4].in_uop.bits.fp_ctrl.sqrt, issue_slots[5].out_uop.fp_ctrl.sqrt
connect issue_slots[4].in_uop.bits.fp_ctrl.div, issue_slots[5].out_uop.fp_ctrl.div
connect issue_slots[4].in_uop.bits.fp_ctrl.fma, issue_slots[5].out_uop.fp_ctrl.fma
connect issue_slots[4].in_uop.bits.fp_ctrl.fastpipe, issue_slots[5].out_uop.fp_ctrl.fastpipe
connect issue_slots[4].in_uop.bits.fp_ctrl.toint, issue_slots[5].out_uop.fp_ctrl.toint
connect issue_slots[4].in_uop.bits.fp_ctrl.fromint, issue_slots[5].out_uop.fp_ctrl.fromint
connect issue_slots[4].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[5].out_uop.fp_ctrl.typeTagOut
connect issue_slots[4].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[5].out_uop.fp_ctrl.typeTagIn
connect issue_slots[4].in_uop.bits.fp_ctrl.swap23, issue_slots[5].out_uop.fp_ctrl.swap23
connect issue_slots[4].in_uop.bits.fp_ctrl.swap12, issue_slots[5].out_uop.fp_ctrl.swap12
connect issue_slots[4].in_uop.bits.fp_ctrl.ren3, issue_slots[5].out_uop.fp_ctrl.ren3
connect issue_slots[4].in_uop.bits.fp_ctrl.ren2, issue_slots[5].out_uop.fp_ctrl.ren2
connect issue_slots[4].in_uop.bits.fp_ctrl.ren1, issue_slots[5].out_uop.fp_ctrl.ren1
connect issue_slots[4].in_uop.bits.fp_ctrl.wen, issue_slots[5].out_uop.fp_ctrl.wen
connect issue_slots[4].in_uop.bits.fp_ctrl.ldst, issue_slots[5].out_uop.fp_ctrl.ldst
connect issue_slots[4].in_uop.bits.op2_sel, issue_slots[5].out_uop.op2_sel
connect issue_slots[4].in_uop.bits.op1_sel, issue_slots[5].out_uop.op1_sel
connect issue_slots[4].in_uop.bits.imm_packed, issue_slots[5].out_uop.imm_packed
connect issue_slots[4].in_uop.bits.pimm, issue_slots[5].out_uop.pimm
connect issue_slots[4].in_uop.bits.imm_sel, issue_slots[5].out_uop.imm_sel
connect issue_slots[4].in_uop.bits.imm_rename, issue_slots[5].out_uop.imm_rename
connect issue_slots[4].in_uop.bits.taken, issue_slots[5].out_uop.taken
connect issue_slots[4].in_uop.bits.pc_lob, issue_slots[5].out_uop.pc_lob
connect issue_slots[4].in_uop.bits.edge_inst, issue_slots[5].out_uop.edge_inst
connect issue_slots[4].in_uop.bits.ftq_idx, issue_slots[5].out_uop.ftq_idx
connect issue_slots[4].in_uop.bits.is_mov, issue_slots[5].out_uop.is_mov
connect issue_slots[4].in_uop.bits.is_rocc, issue_slots[5].out_uop.is_rocc
connect issue_slots[4].in_uop.bits.is_sys_pc2epc, issue_slots[5].out_uop.is_sys_pc2epc
connect issue_slots[4].in_uop.bits.is_eret, issue_slots[5].out_uop.is_eret
connect issue_slots[4].in_uop.bits.is_amo, issue_slots[5].out_uop.is_amo
connect issue_slots[4].in_uop.bits.is_sfence, issue_slots[5].out_uop.is_sfence
connect issue_slots[4].in_uop.bits.is_fencei, issue_slots[5].out_uop.is_fencei
connect issue_slots[4].in_uop.bits.is_fence, issue_slots[5].out_uop.is_fence
connect issue_slots[4].in_uop.bits.is_sfb, issue_slots[5].out_uop.is_sfb
connect issue_slots[4].in_uop.bits.br_type, issue_slots[5].out_uop.br_type
connect issue_slots[4].in_uop.bits.br_tag, issue_slots[5].out_uop.br_tag
connect issue_slots[4].in_uop.bits.br_mask, issue_slots[5].out_uop.br_mask
connect issue_slots[4].in_uop.bits.dis_col_sel, issue_slots[5].out_uop.dis_col_sel
connect issue_slots[4].in_uop.bits.iw_p3_bypass_hint, issue_slots[5].out_uop.iw_p3_bypass_hint
connect issue_slots[4].in_uop.bits.iw_p2_bypass_hint, issue_slots[5].out_uop.iw_p2_bypass_hint
connect issue_slots[4].in_uop.bits.iw_p1_bypass_hint, issue_slots[5].out_uop.iw_p1_bypass_hint
connect issue_slots[4].in_uop.bits.iw_p2_speculative_child, issue_slots[5].out_uop.iw_p2_speculative_child
connect issue_slots[4].in_uop.bits.iw_p1_speculative_child, issue_slots[5].out_uop.iw_p1_speculative_child
connect issue_slots[4].in_uop.bits.iw_issued_partial_dgen, issue_slots[5].out_uop.iw_issued_partial_dgen
connect issue_slots[4].in_uop.bits.iw_issued_partial_agen, issue_slots[5].out_uop.iw_issued_partial_agen
connect issue_slots[4].in_uop.bits.iw_issued, issue_slots[5].out_uop.iw_issued
connect issue_slots[4].in_uop.bits.fu_code[0], issue_slots[5].out_uop.fu_code[0]
connect issue_slots[4].in_uop.bits.fu_code[1], issue_slots[5].out_uop.fu_code[1]
connect issue_slots[4].in_uop.bits.fu_code[2], issue_slots[5].out_uop.fu_code[2]
connect issue_slots[4].in_uop.bits.fu_code[3], issue_slots[5].out_uop.fu_code[3]
connect issue_slots[4].in_uop.bits.fu_code[4], issue_slots[5].out_uop.fu_code[4]
connect issue_slots[4].in_uop.bits.fu_code[5], issue_slots[5].out_uop.fu_code[5]
connect issue_slots[4].in_uop.bits.fu_code[6], issue_slots[5].out_uop.fu_code[6]
connect issue_slots[4].in_uop.bits.fu_code[7], issue_slots[5].out_uop.fu_code[7]
connect issue_slots[4].in_uop.bits.fu_code[8], issue_slots[5].out_uop.fu_code[8]
connect issue_slots[4].in_uop.bits.fu_code[9], issue_slots[5].out_uop.fu_code[9]
connect issue_slots[4].in_uop.bits.iq_type[0], issue_slots[5].out_uop.iq_type[0]
connect issue_slots[4].in_uop.bits.iq_type[1], issue_slots[5].out_uop.iq_type[1]
connect issue_slots[4].in_uop.bits.iq_type[2], issue_slots[5].out_uop.iq_type[2]
connect issue_slots[4].in_uop.bits.iq_type[3], issue_slots[5].out_uop.iq_type[3]
connect issue_slots[4].in_uop.bits.debug_pc, issue_slots[5].out_uop.debug_pc
connect issue_slots[4].in_uop.bits.is_rvc, issue_slots[5].out_uop.is_rvc
connect issue_slots[4].in_uop.bits.debug_inst, issue_slots[5].out_uop.debug_inst
connect issue_slots[4].in_uop.bits.inst, issue_slots[5].out_uop.inst
node _T_171 = eq(shamts_oh[6], UInt<2>(0h2))
when _T_171 :
connect issue_slots[4].in_uop.valid, issue_slots[6].will_be_valid
connect issue_slots[4].in_uop.bits.debug_tsrc, issue_slots[6].out_uop.debug_tsrc
connect issue_slots[4].in_uop.bits.debug_fsrc, issue_slots[6].out_uop.debug_fsrc
connect issue_slots[4].in_uop.bits.bp_xcpt_if, issue_slots[6].out_uop.bp_xcpt_if
connect issue_slots[4].in_uop.bits.bp_debug_if, issue_slots[6].out_uop.bp_debug_if
connect issue_slots[4].in_uop.bits.xcpt_ma_if, issue_slots[6].out_uop.xcpt_ma_if
connect issue_slots[4].in_uop.bits.xcpt_ae_if, issue_slots[6].out_uop.xcpt_ae_if
connect issue_slots[4].in_uop.bits.xcpt_pf_if, issue_slots[6].out_uop.xcpt_pf_if
connect issue_slots[4].in_uop.bits.fp_typ, issue_slots[6].out_uop.fp_typ
connect issue_slots[4].in_uop.bits.fp_rm, issue_slots[6].out_uop.fp_rm
connect issue_slots[4].in_uop.bits.fp_val, issue_slots[6].out_uop.fp_val
connect issue_slots[4].in_uop.bits.fcn_op, issue_slots[6].out_uop.fcn_op
connect issue_slots[4].in_uop.bits.fcn_dw, issue_slots[6].out_uop.fcn_dw
connect issue_slots[4].in_uop.bits.frs3_en, issue_slots[6].out_uop.frs3_en
connect issue_slots[4].in_uop.bits.lrs2_rtype, issue_slots[6].out_uop.lrs2_rtype
connect issue_slots[4].in_uop.bits.lrs1_rtype, issue_slots[6].out_uop.lrs1_rtype
connect issue_slots[4].in_uop.bits.dst_rtype, issue_slots[6].out_uop.dst_rtype
connect issue_slots[4].in_uop.bits.lrs3, issue_slots[6].out_uop.lrs3
connect issue_slots[4].in_uop.bits.lrs2, issue_slots[6].out_uop.lrs2
connect issue_slots[4].in_uop.bits.lrs1, issue_slots[6].out_uop.lrs1
connect issue_slots[4].in_uop.bits.ldst, issue_slots[6].out_uop.ldst
connect issue_slots[4].in_uop.bits.ldst_is_rs1, issue_slots[6].out_uop.ldst_is_rs1
connect issue_slots[4].in_uop.bits.csr_cmd, issue_slots[6].out_uop.csr_cmd
connect issue_slots[4].in_uop.bits.flush_on_commit, issue_slots[6].out_uop.flush_on_commit
connect issue_slots[4].in_uop.bits.is_unique, issue_slots[6].out_uop.is_unique
connect issue_slots[4].in_uop.bits.uses_stq, issue_slots[6].out_uop.uses_stq
connect issue_slots[4].in_uop.bits.uses_ldq, issue_slots[6].out_uop.uses_ldq
connect issue_slots[4].in_uop.bits.mem_signed, issue_slots[6].out_uop.mem_signed
connect issue_slots[4].in_uop.bits.mem_size, issue_slots[6].out_uop.mem_size
connect issue_slots[4].in_uop.bits.mem_cmd, issue_slots[6].out_uop.mem_cmd
connect issue_slots[4].in_uop.bits.exc_cause, issue_slots[6].out_uop.exc_cause
connect issue_slots[4].in_uop.bits.exception, issue_slots[6].out_uop.exception
connect issue_slots[4].in_uop.bits.stale_pdst, issue_slots[6].out_uop.stale_pdst
connect issue_slots[4].in_uop.bits.ppred_busy, issue_slots[6].out_uop.ppred_busy
connect issue_slots[4].in_uop.bits.prs3_busy, issue_slots[6].out_uop.prs3_busy
connect issue_slots[4].in_uop.bits.prs2_busy, issue_slots[6].out_uop.prs2_busy
connect issue_slots[4].in_uop.bits.prs1_busy, issue_slots[6].out_uop.prs1_busy
connect issue_slots[4].in_uop.bits.ppred, issue_slots[6].out_uop.ppred
connect issue_slots[4].in_uop.bits.prs3, issue_slots[6].out_uop.prs3
connect issue_slots[4].in_uop.bits.prs2, issue_slots[6].out_uop.prs2
connect issue_slots[4].in_uop.bits.prs1, issue_slots[6].out_uop.prs1
connect issue_slots[4].in_uop.bits.pdst, issue_slots[6].out_uop.pdst
connect issue_slots[4].in_uop.bits.rxq_idx, issue_slots[6].out_uop.rxq_idx
connect issue_slots[4].in_uop.bits.stq_idx, issue_slots[6].out_uop.stq_idx
connect issue_slots[4].in_uop.bits.ldq_idx, issue_slots[6].out_uop.ldq_idx
connect issue_slots[4].in_uop.bits.rob_idx, issue_slots[6].out_uop.rob_idx
connect issue_slots[4].in_uop.bits.fp_ctrl.vec, issue_slots[6].out_uop.fp_ctrl.vec
connect issue_slots[4].in_uop.bits.fp_ctrl.wflags, issue_slots[6].out_uop.fp_ctrl.wflags
connect issue_slots[4].in_uop.bits.fp_ctrl.sqrt, issue_slots[6].out_uop.fp_ctrl.sqrt
connect issue_slots[4].in_uop.bits.fp_ctrl.div, issue_slots[6].out_uop.fp_ctrl.div
connect issue_slots[4].in_uop.bits.fp_ctrl.fma, issue_slots[6].out_uop.fp_ctrl.fma
connect issue_slots[4].in_uop.bits.fp_ctrl.fastpipe, issue_slots[6].out_uop.fp_ctrl.fastpipe
connect issue_slots[4].in_uop.bits.fp_ctrl.toint, issue_slots[6].out_uop.fp_ctrl.toint
connect issue_slots[4].in_uop.bits.fp_ctrl.fromint, issue_slots[6].out_uop.fp_ctrl.fromint
connect issue_slots[4].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[6].out_uop.fp_ctrl.typeTagOut
connect issue_slots[4].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[6].out_uop.fp_ctrl.typeTagIn
connect issue_slots[4].in_uop.bits.fp_ctrl.swap23, issue_slots[6].out_uop.fp_ctrl.swap23
connect issue_slots[4].in_uop.bits.fp_ctrl.swap12, issue_slots[6].out_uop.fp_ctrl.swap12
connect issue_slots[4].in_uop.bits.fp_ctrl.ren3, issue_slots[6].out_uop.fp_ctrl.ren3
connect issue_slots[4].in_uop.bits.fp_ctrl.ren2, issue_slots[6].out_uop.fp_ctrl.ren2
connect issue_slots[4].in_uop.bits.fp_ctrl.ren1, issue_slots[6].out_uop.fp_ctrl.ren1
connect issue_slots[4].in_uop.bits.fp_ctrl.wen, issue_slots[6].out_uop.fp_ctrl.wen
connect issue_slots[4].in_uop.bits.fp_ctrl.ldst, issue_slots[6].out_uop.fp_ctrl.ldst
connect issue_slots[4].in_uop.bits.op2_sel, issue_slots[6].out_uop.op2_sel
connect issue_slots[4].in_uop.bits.op1_sel, issue_slots[6].out_uop.op1_sel
connect issue_slots[4].in_uop.bits.imm_packed, issue_slots[6].out_uop.imm_packed
connect issue_slots[4].in_uop.bits.pimm, issue_slots[6].out_uop.pimm
connect issue_slots[4].in_uop.bits.imm_sel, issue_slots[6].out_uop.imm_sel
connect issue_slots[4].in_uop.bits.imm_rename, issue_slots[6].out_uop.imm_rename
connect issue_slots[4].in_uop.bits.taken, issue_slots[6].out_uop.taken
connect issue_slots[4].in_uop.bits.pc_lob, issue_slots[6].out_uop.pc_lob
connect issue_slots[4].in_uop.bits.edge_inst, issue_slots[6].out_uop.edge_inst
connect issue_slots[4].in_uop.bits.ftq_idx, issue_slots[6].out_uop.ftq_idx
connect issue_slots[4].in_uop.bits.is_mov, issue_slots[6].out_uop.is_mov
connect issue_slots[4].in_uop.bits.is_rocc, issue_slots[6].out_uop.is_rocc
connect issue_slots[4].in_uop.bits.is_sys_pc2epc, issue_slots[6].out_uop.is_sys_pc2epc
connect issue_slots[4].in_uop.bits.is_eret, issue_slots[6].out_uop.is_eret
connect issue_slots[4].in_uop.bits.is_amo, issue_slots[6].out_uop.is_amo
connect issue_slots[4].in_uop.bits.is_sfence, issue_slots[6].out_uop.is_sfence
connect issue_slots[4].in_uop.bits.is_fencei, issue_slots[6].out_uop.is_fencei
connect issue_slots[4].in_uop.bits.is_fence, issue_slots[6].out_uop.is_fence
connect issue_slots[4].in_uop.bits.is_sfb, issue_slots[6].out_uop.is_sfb
connect issue_slots[4].in_uop.bits.br_type, issue_slots[6].out_uop.br_type
connect issue_slots[4].in_uop.bits.br_tag, issue_slots[6].out_uop.br_tag
connect issue_slots[4].in_uop.bits.br_mask, issue_slots[6].out_uop.br_mask
connect issue_slots[4].in_uop.bits.dis_col_sel, issue_slots[6].out_uop.dis_col_sel
connect issue_slots[4].in_uop.bits.iw_p3_bypass_hint, issue_slots[6].out_uop.iw_p3_bypass_hint
connect issue_slots[4].in_uop.bits.iw_p2_bypass_hint, issue_slots[6].out_uop.iw_p2_bypass_hint
connect issue_slots[4].in_uop.bits.iw_p1_bypass_hint, issue_slots[6].out_uop.iw_p1_bypass_hint
connect issue_slots[4].in_uop.bits.iw_p2_speculative_child, issue_slots[6].out_uop.iw_p2_speculative_child
connect issue_slots[4].in_uop.bits.iw_p1_speculative_child, issue_slots[6].out_uop.iw_p1_speculative_child
connect issue_slots[4].in_uop.bits.iw_issued_partial_dgen, issue_slots[6].out_uop.iw_issued_partial_dgen
connect issue_slots[4].in_uop.bits.iw_issued_partial_agen, issue_slots[6].out_uop.iw_issued_partial_agen
connect issue_slots[4].in_uop.bits.iw_issued, issue_slots[6].out_uop.iw_issued
connect issue_slots[4].in_uop.bits.fu_code[0], issue_slots[6].out_uop.fu_code[0]
connect issue_slots[4].in_uop.bits.fu_code[1], issue_slots[6].out_uop.fu_code[1]
connect issue_slots[4].in_uop.bits.fu_code[2], issue_slots[6].out_uop.fu_code[2]
connect issue_slots[4].in_uop.bits.fu_code[3], issue_slots[6].out_uop.fu_code[3]
connect issue_slots[4].in_uop.bits.fu_code[4], issue_slots[6].out_uop.fu_code[4]
connect issue_slots[4].in_uop.bits.fu_code[5], issue_slots[6].out_uop.fu_code[5]
connect issue_slots[4].in_uop.bits.fu_code[6], issue_slots[6].out_uop.fu_code[6]
connect issue_slots[4].in_uop.bits.fu_code[7], issue_slots[6].out_uop.fu_code[7]
connect issue_slots[4].in_uop.bits.fu_code[8], issue_slots[6].out_uop.fu_code[8]
connect issue_slots[4].in_uop.bits.fu_code[9], issue_slots[6].out_uop.fu_code[9]
connect issue_slots[4].in_uop.bits.iq_type[0], issue_slots[6].out_uop.iq_type[0]
connect issue_slots[4].in_uop.bits.iq_type[1], issue_slots[6].out_uop.iq_type[1]
connect issue_slots[4].in_uop.bits.iq_type[2], issue_slots[6].out_uop.iq_type[2]
connect issue_slots[4].in_uop.bits.iq_type[3], issue_slots[6].out_uop.iq_type[3]
connect issue_slots[4].in_uop.bits.debug_pc, issue_slots[6].out_uop.debug_pc
connect issue_slots[4].in_uop.bits.is_rvc, issue_slots[6].out_uop.is_rvc
connect issue_slots[4].in_uop.bits.debug_inst, issue_slots[6].out_uop.debug_inst
connect issue_slots[4].in_uop.bits.inst, issue_slots[6].out_uop.inst
node _issue_slots_4_clear_T = neq(shamts_oh[4], UInt<1>(0h0))
connect issue_slots[4].clear, _issue_slots_4_clear_T
connect issue_slots[5].in_uop.valid, UInt<1>(0h0)
connect issue_slots[5].in_uop.bits.debug_tsrc, issue_slots[6].out_uop.debug_tsrc
connect issue_slots[5].in_uop.bits.debug_fsrc, issue_slots[6].out_uop.debug_fsrc
connect issue_slots[5].in_uop.bits.bp_xcpt_if, issue_slots[6].out_uop.bp_xcpt_if
connect issue_slots[5].in_uop.bits.bp_debug_if, issue_slots[6].out_uop.bp_debug_if
connect issue_slots[5].in_uop.bits.xcpt_ma_if, issue_slots[6].out_uop.xcpt_ma_if
connect issue_slots[5].in_uop.bits.xcpt_ae_if, issue_slots[6].out_uop.xcpt_ae_if
connect issue_slots[5].in_uop.bits.xcpt_pf_if, issue_slots[6].out_uop.xcpt_pf_if
connect issue_slots[5].in_uop.bits.fp_typ, issue_slots[6].out_uop.fp_typ
connect issue_slots[5].in_uop.bits.fp_rm, issue_slots[6].out_uop.fp_rm
connect issue_slots[5].in_uop.bits.fp_val, issue_slots[6].out_uop.fp_val
connect issue_slots[5].in_uop.bits.fcn_op, issue_slots[6].out_uop.fcn_op
connect issue_slots[5].in_uop.bits.fcn_dw, issue_slots[6].out_uop.fcn_dw
connect issue_slots[5].in_uop.bits.frs3_en, issue_slots[6].out_uop.frs3_en
connect issue_slots[5].in_uop.bits.lrs2_rtype, issue_slots[6].out_uop.lrs2_rtype
connect issue_slots[5].in_uop.bits.lrs1_rtype, issue_slots[6].out_uop.lrs1_rtype
connect issue_slots[5].in_uop.bits.dst_rtype, issue_slots[6].out_uop.dst_rtype
connect issue_slots[5].in_uop.bits.lrs3, issue_slots[6].out_uop.lrs3
connect issue_slots[5].in_uop.bits.lrs2, issue_slots[6].out_uop.lrs2
connect issue_slots[5].in_uop.bits.lrs1, issue_slots[6].out_uop.lrs1
connect issue_slots[5].in_uop.bits.ldst, issue_slots[6].out_uop.ldst
connect issue_slots[5].in_uop.bits.ldst_is_rs1, issue_slots[6].out_uop.ldst_is_rs1
connect issue_slots[5].in_uop.bits.csr_cmd, issue_slots[6].out_uop.csr_cmd
connect issue_slots[5].in_uop.bits.flush_on_commit, issue_slots[6].out_uop.flush_on_commit
connect issue_slots[5].in_uop.bits.is_unique, issue_slots[6].out_uop.is_unique
connect issue_slots[5].in_uop.bits.uses_stq, issue_slots[6].out_uop.uses_stq
connect issue_slots[5].in_uop.bits.uses_ldq, issue_slots[6].out_uop.uses_ldq
connect issue_slots[5].in_uop.bits.mem_signed, issue_slots[6].out_uop.mem_signed
connect issue_slots[5].in_uop.bits.mem_size, issue_slots[6].out_uop.mem_size
connect issue_slots[5].in_uop.bits.mem_cmd, issue_slots[6].out_uop.mem_cmd
connect issue_slots[5].in_uop.bits.exc_cause, issue_slots[6].out_uop.exc_cause
connect issue_slots[5].in_uop.bits.exception, issue_slots[6].out_uop.exception
connect issue_slots[5].in_uop.bits.stale_pdst, issue_slots[6].out_uop.stale_pdst
connect issue_slots[5].in_uop.bits.ppred_busy, issue_slots[6].out_uop.ppred_busy
connect issue_slots[5].in_uop.bits.prs3_busy, issue_slots[6].out_uop.prs3_busy
connect issue_slots[5].in_uop.bits.prs2_busy, issue_slots[6].out_uop.prs2_busy
connect issue_slots[5].in_uop.bits.prs1_busy, issue_slots[6].out_uop.prs1_busy
connect issue_slots[5].in_uop.bits.ppred, issue_slots[6].out_uop.ppred
connect issue_slots[5].in_uop.bits.prs3, issue_slots[6].out_uop.prs3
connect issue_slots[5].in_uop.bits.prs2, issue_slots[6].out_uop.prs2
connect issue_slots[5].in_uop.bits.prs1, issue_slots[6].out_uop.prs1
connect issue_slots[5].in_uop.bits.pdst, issue_slots[6].out_uop.pdst
connect issue_slots[5].in_uop.bits.rxq_idx, issue_slots[6].out_uop.rxq_idx
connect issue_slots[5].in_uop.bits.stq_idx, issue_slots[6].out_uop.stq_idx
connect issue_slots[5].in_uop.bits.ldq_idx, issue_slots[6].out_uop.ldq_idx
connect issue_slots[5].in_uop.bits.rob_idx, issue_slots[6].out_uop.rob_idx
connect issue_slots[5].in_uop.bits.fp_ctrl.vec, issue_slots[6].out_uop.fp_ctrl.vec
connect issue_slots[5].in_uop.bits.fp_ctrl.wflags, issue_slots[6].out_uop.fp_ctrl.wflags
connect issue_slots[5].in_uop.bits.fp_ctrl.sqrt, issue_slots[6].out_uop.fp_ctrl.sqrt
connect issue_slots[5].in_uop.bits.fp_ctrl.div, issue_slots[6].out_uop.fp_ctrl.div
connect issue_slots[5].in_uop.bits.fp_ctrl.fma, issue_slots[6].out_uop.fp_ctrl.fma
connect issue_slots[5].in_uop.bits.fp_ctrl.fastpipe, issue_slots[6].out_uop.fp_ctrl.fastpipe
connect issue_slots[5].in_uop.bits.fp_ctrl.toint, issue_slots[6].out_uop.fp_ctrl.toint
connect issue_slots[5].in_uop.bits.fp_ctrl.fromint, issue_slots[6].out_uop.fp_ctrl.fromint
connect issue_slots[5].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[6].out_uop.fp_ctrl.typeTagOut
connect issue_slots[5].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[6].out_uop.fp_ctrl.typeTagIn
connect issue_slots[5].in_uop.bits.fp_ctrl.swap23, issue_slots[6].out_uop.fp_ctrl.swap23
connect issue_slots[5].in_uop.bits.fp_ctrl.swap12, issue_slots[6].out_uop.fp_ctrl.swap12
connect issue_slots[5].in_uop.bits.fp_ctrl.ren3, issue_slots[6].out_uop.fp_ctrl.ren3
connect issue_slots[5].in_uop.bits.fp_ctrl.ren2, issue_slots[6].out_uop.fp_ctrl.ren2
connect issue_slots[5].in_uop.bits.fp_ctrl.ren1, issue_slots[6].out_uop.fp_ctrl.ren1
connect issue_slots[5].in_uop.bits.fp_ctrl.wen, issue_slots[6].out_uop.fp_ctrl.wen
connect issue_slots[5].in_uop.bits.fp_ctrl.ldst, issue_slots[6].out_uop.fp_ctrl.ldst
connect issue_slots[5].in_uop.bits.op2_sel, issue_slots[6].out_uop.op2_sel
connect issue_slots[5].in_uop.bits.op1_sel, issue_slots[6].out_uop.op1_sel
connect issue_slots[5].in_uop.bits.imm_packed, issue_slots[6].out_uop.imm_packed
connect issue_slots[5].in_uop.bits.pimm, issue_slots[6].out_uop.pimm
connect issue_slots[5].in_uop.bits.imm_sel, issue_slots[6].out_uop.imm_sel
connect issue_slots[5].in_uop.bits.imm_rename, issue_slots[6].out_uop.imm_rename
connect issue_slots[5].in_uop.bits.taken, issue_slots[6].out_uop.taken
connect issue_slots[5].in_uop.bits.pc_lob, issue_slots[6].out_uop.pc_lob
connect issue_slots[5].in_uop.bits.edge_inst, issue_slots[6].out_uop.edge_inst
connect issue_slots[5].in_uop.bits.ftq_idx, issue_slots[6].out_uop.ftq_idx
connect issue_slots[5].in_uop.bits.is_mov, issue_slots[6].out_uop.is_mov
connect issue_slots[5].in_uop.bits.is_rocc, issue_slots[6].out_uop.is_rocc
connect issue_slots[5].in_uop.bits.is_sys_pc2epc, issue_slots[6].out_uop.is_sys_pc2epc
connect issue_slots[5].in_uop.bits.is_eret, issue_slots[6].out_uop.is_eret
connect issue_slots[5].in_uop.bits.is_amo, issue_slots[6].out_uop.is_amo
connect issue_slots[5].in_uop.bits.is_sfence, issue_slots[6].out_uop.is_sfence
connect issue_slots[5].in_uop.bits.is_fencei, issue_slots[6].out_uop.is_fencei
connect issue_slots[5].in_uop.bits.is_fence, issue_slots[6].out_uop.is_fence
connect issue_slots[5].in_uop.bits.is_sfb, issue_slots[6].out_uop.is_sfb
connect issue_slots[5].in_uop.bits.br_type, issue_slots[6].out_uop.br_type
connect issue_slots[5].in_uop.bits.br_tag, issue_slots[6].out_uop.br_tag
connect issue_slots[5].in_uop.bits.br_mask, issue_slots[6].out_uop.br_mask
connect issue_slots[5].in_uop.bits.dis_col_sel, issue_slots[6].out_uop.dis_col_sel
connect issue_slots[5].in_uop.bits.iw_p3_bypass_hint, issue_slots[6].out_uop.iw_p3_bypass_hint
connect issue_slots[5].in_uop.bits.iw_p2_bypass_hint, issue_slots[6].out_uop.iw_p2_bypass_hint
connect issue_slots[5].in_uop.bits.iw_p1_bypass_hint, issue_slots[6].out_uop.iw_p1_bypass_hint
connect issue_slots[5].in_uop.bits.iw_p2_speculative_child, issue_slots[6].out_uop.iw_p2_speculative_child
connect issue_slots[5].in_uop.bits.iw_p1_speculative_child, issue_slots[6].out_uop.iw_p1_speculative_child
connect issue_slots[5].in_uop.bits.iw_issued_partial_dgen, issue_slots[6].out_uop.iw_issued_partial_dgen
connect issue_slots[5].in_uop.bits.iw_issued_partial_agen, issue_slots[6].out_uop.iw_issued_partial_agen
connect issue_slots[5].in_uop.bits.iw_issued, issue_slots[6].out_uop.iw_issued
connect issue_slots[5].in_uop.bits.fu_code[0], issue_slots[6].out_uop.fu_code[0]
connect issue_slots[5].in_uop.bits.fu_code[1], issue_slots[6].out_uop.fu_code[1]
connect issue_slots[5].in_uop.bits.fu_code[2], issue_slots[6].out_uop.fu_code[2]
connect issue_slots[5].in_uop.bits.fu_code[3], issue_slots[6].out_uop.fu_code[3]
connect issue_slots[5].in_uop.bits.fu_code[4], issue_slots[6].out_uop.fu_code[4]
connect issue_slots[5].in_uop.bits.fu_code[5], issue_slots[6].out_uop.fu_code[5]
connect issue_slots[5].in_uop.bits.fu_code[6], issue_slots[6].out_uop.fu_code[6]
connect issue_slots[5].in_uop.bits.fu_code[7], issue_slots[6].out_uop.fu_code[7]
connect issue_slots[5].in_uop.bits.fu_code[8], issue_slots[6].out_uop.fu_code[8]
connect issue_slots[5].in_uop.bits.fu_code[9], issue_slots[6].out_uop.fu_code[9]
connect issue_slots[5].in_uop.bits.iq_type[0], issue_slots[6].out_uop.iq_type[0]
connect issue_slots[5].in_uop.bits.iq_type[1], issue_slots[6].out_uop.iq_type[1]
connect issue_slots[5].in_uop.bits.iq_type[2], issue_slots[6].out_uop.iq_type[2]
connect issue_slots[5].in_uop.bits.iq_type[3], issue_slots[6].out_uop.iq_type[3]
connect issue_slots[5].in_uop.bits.debug_pc, issue_slots[6].out_uop.debug_pc
connect issue_slots[5].in_uop.bits.is_rvc, issue_slots[6].out_uop.is_rvc
connect issue_slots[5].in_uop.bits.debug_inst, issue_slots[6].out_uop.debug_inst
connect issue_slots[5].in_uop.bits.inst, issue_slots[6].out_uop.inst
node _T_172 = eq(shamts_oh[6], UInt<1>(0h1))
when _T_172 :
connect issue_slots[5].in_uop.valid, issue_slots[6].will_be_valid
connect issue_slots[5].in_uop.bits.debug_tsrc, issue_slots[6].out_uop.debug_tsrc
connect issue_slots[5].in_uop.bits.debug_fsrc, issue_slots[6].out_uop.debug_fsrc
connect issue_slots[5].in_uop.bits.bp_xcpt_if, issue_slots[6].out_uop.bp_xcpt_if
connect issue_slots[5].in_uop.bits.bp_debug_if, issue_slots[6].out_uop.bp_debug_if
connect issue_slots[5].in_uop.bits.xcpt_ma_if, issue_slots[6].out_uop.xcpt_ma_if
connect issue_slots[5].in_uop.bits.xcpt_ae_if, issue_slots[6].out_uop.xcpt_ae_if
connect issue_slots[5].in_uop.bits.xcpt_pf_if, issue_slots[6].out_uop.xcpt_pf_if
connect issue_slots[5].in_uop.bits.fp_typ, issue_slots[6].out_uop.fp_typ
connect issue_slots[5].in_uop.bits.fp_rm, issue_slots[6].out_uop.fp_rm
connect issue_slots[5].in_uop.bits.fp_val, issue_slots[6].out_uop.fp_val
connect issue_slots[5].in_uop.bits.fcn_op, issue_slots[6].out_uop.fcn_op
connect issue_slots[5].in_uop.bits.fcn_dw, issue_slots[6].out_uop.fcn_dw
connect issue_slots[5].in_uop.bits.frs3_en, issue_slots[6].out_uop.frs3_en
connect issue_slots[5].in_uop.bits.lrs2_rtype, issue_slots[6].out_uop.lrs2_rtype
connect issue_slots[5].in_uop.bits.lrs1_rtype, issue_slots[6].out_uop.lrs1_rtype
connect issue_slots[5].in_uop.bits.dst_rtype, issue_slots[6].out_uop.dst_rtype
connect issue_slots[5].in_uop.bits.lrs3, issue_slots[6].out_uop.lrs3
connect issue_slots[5].in_uop.bits.lrs2, issue_slots[6].out_uop.lrs2
connect issue_slots[5].in_uop.bits.lrs1, issue_slots[6].out_uop.lrs1
connect issue_slots[5].in_uop.bits.ldst, issue_slots[6].out_uop.ldst
connect issue_slots[5].in_uop.bits.ldst_is_rs1, issue_slots[6].out_uop.ldst_is_rs1
connect issue_slots[5].in_uop.bits.csr_cmd, issue_slots[6].out_uop.csr_cmd
connect issue_slots[5].in_uop.bits.flush_on_commit, issue_slots[6].out_uop.flush_on_commit
connect issue_slots[5].in_uop.bits.is_unique, issue_slots[6].out_uop.is_unique
connect issue_slots[5].in_uop.bits.uses_stq, issue_slots[6].out_uop.uses_stq
connect issue_slots[5].in_uop.bits.uses_ldq, issue_slots[6].out_uop.uses_ldq
connect issue_slots[5].in_uop.bits.mem_signed, issue_slots[6].out_uop.mem_signed
connect issue_slots[5].in_uop.bits.mem_size, issue_slots[6].out_uop.mem_size
connect issue_slots[5].in_uop.bits.mem_cmd, issue_slots[6].out_uop.mem_cmd
connect issue_slots[5].in_uop.bits.exc_cause, issue_slots[6].out_uop.exc_cause
connect issue_slots[5].in_uop.bits.exception, issue_slots[6].out_uop.exception
connect issue_slots[5].in_uop.bits.stale_pdst, issue_slots[6].out_uop.stale_pdst
connect issue_slots[5].in_uop.bits.ppred_busy, issue_slots[6].out_uop.ppred_busy
connect issue_slots[5].in_uop.bits.prs3_busy, issue_slots[6].out_uop.prs3_busy
connect issue_slots[5].in_uop.bits.prs2_busy, issue_slots[6].out_uop.prs2_busy
connect issue_slots[5].in_uop.bits.prs1_busy, issue_slots[6].out_uop.prs1_busy
connect issue_slots[5].in_uop.bits.ppred, issue_slots[6].out_uop.ppred
connect issue_slots[5].in_uop.bits.prs3, issue_slots[6].out_uop.prs3
connect issue_slots[5].in_uop.bits.prs2, issue_slots[6].out_uop.prs2
connect issue_slots[5].in_uop.bits.prs1, issue_slots[6].out_uop.prs1
connect issue_slots[5].in_uop.bits.pdst, issue_slots[6].out_uop.pdst
connect issue_slots[5].in_uop.bits.rxq_idx, issue_slots[6].out_uop.rxq_idx
connect issue_slots[5].in_uop.bits.stq_idx, issue_slots[6].out_uop.stq_idx
connect issue_slots[5].in_uop.bits.ldq_idx, issue_slots[6].out_uop.ldq_idx
connect issue_slots[5].in_uop.bits.rob_idx, issue_slots[6].out_uop.rob_idx
connect issue_slots[5].in_uop.bits.fp_ctrl.vec, issue_slots[6].out_uop.fp_ctrl.vec
connect issue_slots[5].in_uop.bits.fp_ctrl.wflags, issue_slots[6].out_uop.fp_ctrl.wflags
connect issue_slots[5].in_uop.bits.fp_ctrl.sqrt, issue_slots[6].out_uop.fp_ctrl.sqrt
connect issue_slots[5].in_uop.bits.fp_ctrl.div, issue_slots[6].out_uop.fp_ctrl.div
connect issue_slots[5].in_uop.bits.fp_ctrl.fma, issue_slots[6].out_uop.fp_ctrl.fma
connect issue_slots[5].in_uop.bits.fp_ctrl.fastpipe, issue_slots[6].out_uop.fp_ctrl.fastpipe
connect issue_slots[5].in_uop.bits.fp_ctrl.toint, issue_slots[6].out_uop.fp_ctrl.toint
connect issue_slots[5].in_uop.bits.fp_ctrl.fromint, issue_slots[6].out_uop.fp_ctrl.fromint
connect issue_slots[5].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[6].out_uop.fp_ctrl.typeTagOut
connect issue_slots[5].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[6].out_uop.fp_ctrl.typeTagIn
connect issue_slots[5].in_uop.bits.fp_ctrl.swap23, issue_slots[6].out_uop.fp_ctrl.swap23
connect issue_slots[5].in_uop.bits.fp_ctrl.swap12, issue_slots[6].out_uop.fp_ctrl.swap12
connect issue_slots[5].in_uop.bits.fp_ctrl.ren3, issue_slots[6].out_uop.fp_ctrl.ren3
connect issue_slots[5].in_uop.bits.fp_ctrl.ren2, issue_slots[6].out_uop.fp_ctrl.ren2
connect issue_slots[5].in_uop.bits.fp_ctrl.ren1, issue_slots[6].out_uop.fp_ctrl.ren1
connect issue_slots[5].in_uop.bits.fp_ctrl.wen, issue_slots[6].out_uop.fp_ctrl.wen
connect issue_slots[5].in_uop.bits.fp_ctrl.ldst, issue_slots[6].out_uop.fp_ctrl.ldst
connect issue_slots[5].in_uop.bits.op2_sel, issue_slots[6].out_uop.op2_sel
connect issue_slots[5].in_uop.bits.op1_sel, issue_slots[6].out_uop.op1_sel
connect issue_slots[5].in_uop.bits.imm_packed, issue_slots[6].out_uop.imm_packed
connect issue_slots[5].in_uop.bits.pimm, issue_slots[6].out_uop.pimm
connect issue_slots[5].in_uop.bits.imm_sel, issue_slots[6].out_uop.imm_sel
connect issue_slots[5].in_uop.bits.imm_rename, issue_slots[6].out_uop.imm_rename
connect issue_slots[5].in_uop.bits.taken, issue_slots[6].out_uop.taken
connect issue_slots[5].in_uop.bits.pc_lob, issue_slots[6].out_uop.pc_lob
connect issue_slots[5].in_uop.bits.edge_inst, issue_slots[6].out_uop.edge_inst
connect issue_slots[5].in_uop.bits.ftq_idx, issue_slots[6].out_uop.ftq_idx
connect issue_slots[5].in_uop.bits.is_mov, issue_slots[6].out_uop.is_mov
connect issue_slots[5].in_uop.bits.is_rocc, issue_slots[6].out_uop.is_rocc
connect issue_slots[5].in_uop.bits.is_sys_pc2epc, issue_slots[6].out_uop.is_sys_pc2epc
connect issue_slots[5].in_uop.bits.is_eret, issue_slots[6].out_uop.is_eret
connect issue_slots[5].in_uop.bits.is_amo, issue_slots[6].out_uop.is_amo
connect issue_slots[5].in_uop.bits.is_sfence, issue_slots[6].out_uop.is_sfence
connect issue_slots[5].in_uop.bits.is_fencei, issue_slots[6].out_uop.is_fencei
connect issue_slots[5].in_uop.bits.is_fence, issue_slots[6].out_uop.is_fence
connect issue_slots[5].in_uop.bits.is_sfb, issue_slots[6].out_uop.is_sfb
connect issue_slots[5].in_uop.bits.br_type, issue_slots[6].out_uop.br_type
connect issue_slots[5].in_uop.bits.br_tag, issue_slots[6].out_uop.br_tag
connect issue_slots[5].in_uop.bits.br_mask, issue_slots[6].out_uop.br_mask
connect issue_slots[5].in_uop.bits.dis_col_sel, issue_slots[6].out_uop.dis_col_sel
connect issue_slots[5].in_uop.bits.iw_p3_bypass_hint, issue_slots[6].out_uop.iw_p3_bypass_hint
connect issue_slots[5].in_uop.bits.iw_p2_bypass_hint, issue_slots[6].out_uop.iw_p2_bypass_hint
connect issue_slots[5].in_uop.bits.iw_p1_bypass_hint, issue_slots[6].out_uop.iw_p1_bypass_hint
connect issue_slots[5].in_uop.bits.iw_p2_speculative_child, issue_slots[6].out_uop.iw_p2_speculative_child
connect issue_slots[5].in_uop.bits.iw_p1_speculative_child, issue_slots[6].out_uop.iw_p1_speculative_child
connect issue_slots[5].in_uop.bits.iw_issued_partial_dgen, issue_slots[6].out_uop.iw_issued_partial_dgen
connect issue_slots[5].in_uop.bits.iw_issued_partial_agen, issue_slots[6].out_uop.iw_issued_partial_agen
connect issue_slots[5].in_uop.bits.iw_issued, issue_slots[6].out_uop.iw_issued
connect issue_slots[5].in_uop.bits.fu_code[0], issue_slots[6].out_uop.fu_code[0]
connect issue_slots[5].in_uop.bits.fu_code[1], issue_slots[6].out_uop.fu_code[1]
connect issue_slots[5].in_uop.bits.fu_code[2], issue_slots[6].out_uop.fu_code[2]
connect issue_slots[5].in_uop.bits.fu_code[3], issue_slots[6].out_uop.fu_code[3]
connect issue_slots[5].in_uop.bits.fu_code[4], issue_slots[6].out_uop.fu_code[4]
connect issue_slots[5].in_uop.bits.fu_code[5], issue_slots[6].out_uop.fu_code[5]
connect issue_slots[5].in_uop.bits.fu_code[6], issue_slots[6].out_uop.fu_code[6]
connect issue_slots[5].in_uop.bits.fu_code[7], issue_slots[6].out_uop.fu_code[7]
connect issue_slots[5].in_uop.bits.fu_code[8], issue_slots[6].out_uop.fu_code[8]
connect issue_slots[5].in_uop.bits.fu_code[9], issue_slots[6].out_uop.fu_code[9]
connect issue_slots[5].in_uop.bits.iq_type[0], issue_slots[6].out_uop.iq_type[0]
connect issue_slots[5].in_uop.bits.iq_type[1], issue_slots[6].out_uop.iq_type[1]
connect issue_slots[5].in_uop.bits.iq_type[2], issue_slots[6].out_uop.iq_type[2]
connect issue_slots[5].in_uop.bits.iq_type[3], issue_slots[6].out_uop.iq_type[3]
connect issue_slots[5].in_uop.bits.debug_pc, issue_slots[6].out_uop.debug_pc
connect issue_slots[5].in_uop.bits.is_rvc, issue_slots[6].out_uop.is_rvc
connect issue_slots[5].in_uop.bits.debug_inst, issue_slots[6].out_uop.debug_inst
connect issue_slots[5].in_uop.bits.inst, issue_slots[6].out_uop.inst
node _T_173 = eq(shamts_oh[7], UInt<2>(0h2))
when _T_173 :
connect issue_slots[5].in_uop.valid, issue_slots[7].will_be_valid
connect issue_slots[5].in_uop.bits.debug_tsrc, issue_slots[7].out_uop.debug_tsrc
connect issue_slots[5].in_uop.bits.debug_fsrc, issue_slots[7].out_uop.debug_fsrc
connect issue_slots[5].in_uop.bits.bp_xcpt_if, issue_slots[7].out_uop.bp_xcpt_if
connect issue_slots[5].in_uop.bits.bp_debug_if, issue_slots[7].out_uop.bp_debug_if
connect issue_slots[5].in_uop.bits.xcpt_ma_if, issue_slots[7].out_uop.xcpt_ma_if
connect issue_slots[5].in_uop.bits.xcpt_ae_if, issue_slots[7].out_uop.xcpt_ae_if
connect issue_slots[5].in_uop.bits.xcpt_pf_if, issue_slots[7].out_uop.xcpt_pf_if
connect issue_slots[5].in_uop.bits.fp_typ, issue_slots[7].out_uop.fp_typ
connect issue_slots[5].in_uop.bits.fp_rm, issue_slots[7].out_uop.fp_rm
connect issue_slots[5].in_uop.bits.fp_val, issue_slots[7].out_uop.fp_val
connect issue_slots[5].in_uop.bits.fcn_op, issue_slots[7].out_uop.fcn_op
connect issue_slots[5].in_uop.bits.fcn_dw, issue_slots[7].out_uop.fcn_dw
connect issue_slots[5].in_uop.bits.frs3_en, issue_slots[7].out_uop.frs3_en
connect issue_slots[5].in_uop.bits.lrs2_rtype, issue_slots[7].out_uop.lrs2_rtype
connect issue_slots[5].in_uop.bits.lrs1_rtype, issue_slots[7].out_uop.lrs1_rtype
connect issue_slots[5].in_uop.bits.dst_rtype, issue_slots[7].out_uop.dst_rtype
connect issue_slots[5].in_uop.bits.lrs3, issue_slots[7].out_uop.lrs3
connect issue_slots[5].in_uop.bits.lrs2, issue_slots[7].out_uop.lrs2
connect issue_slots[5].in_uop.bits.lrs1, issue_slots[7].out_uop.lrs1
connect issue_slots[5].in_uop.bits.ldst, issue_slots[7].out_uop.ldst
connect issue_slots[5].in_uop.bits.ldst_is_rs1, issue_slots[7].out_uop.ldst_is_rs1
connect issue_slots[5].in_uop.bits.csr_cmd, issue_slots[7].out_uop.csr_cmd
connect issue_slots[5].in_uop.bits.flush_on_commit, issue_slots[7].out_uop.flush_on_commit
connect issue_slots[5].in_uop.bits.is_unique, issue_slots[7].out_uop.is_unique
connect issue_slots[5].in_uop.bits.uses_stq, issue_slots[7].out_uop.uses_stq
connect issue_slots[5].in_uop.bits.uses_ldq, issue_slots[7].out_uop.uses_ldq
connect issue_slots[5].in_uop.bits.mem_signed, issue_slots[7].out_uop.mem_signed
connect issue_slots[5].in_uop.bits.mem_size, issue_slots[7].out_uop.mem_size
connect issue_slots[5].in_uop.bits.mem_cmd, issue_slots[7].out_uop.mem_cmd
connect issue_slots[5].in_uop.bits.exc_cause, issue_slots[7].out_uop.exc_cause
connect issue_slots[5].in_uop.bits.exception, issue_slots[7].out_uop.exception
connect issue_slots[5].in_uop.bits.stale_pdst, issue_slots[7].out_uop.stale_pdst
connect issue_slots[5].in_uop.bits.ppred_busy, issue_slots[7].out_uop.ppred_busy
connect issue_slots[5].in_uop.bits.prs3_busy, issue_slots[7].out_uop.prs3_busy
connect issue_slots[5].in_uop.bits.prs2_busy, issue_slots[7].out_uop.prs2_busy
connect issue_slots[5].in_uop.bits.prs1_busy, issue_slots[7].out_uop.prs1_busy
connect issue_slots[5].in_uop.bits.ppred, issue_slots[7].out_uop.ppred
connect issue_slots[5].in_uop.bits.prs3, issue_slots[7].out_uop.prs3
connect issue_slots[5].in_uop.bits.prs2, issue_slots[7].out_uop.prs2
connect issue_slots[5].in_uop.bits.prs1, issue_slots[7].out_uop.prs1
connect issue_slots[5].in_uop.bits.pdst, issue_slots[7].out_uop.pdst
connect issue_slots[5].in_uop.bits.rxq_idx, issue_slots[7].out_uop.rxq_idx
connect issue_slots[5].in_uop.bits.stq_idx, issue_slots[7].out_uop.stq_idx
connect issue_slots[5].in_uop.bits.ldq_idx, issue_slots[7].out_uop.ldq_idx
connect issue_slots[5].in_uop.bits.rob_idx, issue_slots[7].out_uop.rob_idx
connect issue_slots[5].in_uop.bits.fp_ctrl.vec, issue_slots[7].out_uop.fp_ctrl.vec
connect issue_slots[5].in_uop.bits.fp_ctrl.wflags, issue_slots[7].out_uop.fp_ctrl.wflags
connect issue_slots[5].in_uop.bits.fp_ctrl.sqrt, issue_slots[7].out_uop.fp_ctrl.sqrt
connect issue_slots[5].in_uop.bits.fp_ctrl.div, issue_slots[7].out_uop.fp_ctrl.div
connect issue_slots[5].in_uop.bits.fp_ctrl.fma, issue_slots[7].out_uop.fp_ctrl.fma
connect issue_slots[5].in_uop.bits.fp_ctrl.fastpipe, issue_slots[7].out_uop.fp_ctrl.fastpipe
connect issue_slots[5].in_uop.bits.fp_ctrl.toint, issue_slots[7].out_uop.fp_ctrl.toint
connect issue_slots[5].in_uop.bits.fp_ctrl.fromint, issue_slots[7].out_uop.fp_ctrl.fromint
connect issue_slots[5].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[7].out_uop.fp_ctrl.typeTagOut
connect issue_slots[5].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[7].out_uop.fp_ctrl.typeTagIn
connect issue_slots[5].in_uop.bits.fp_ctrl.swap23, issue_slots[7].out_uop.fp_ctrl.swap23
connect issue_slots[5].in_uop.bits.fp_ctrl.swap12, issue_slots[7].out_uop.fp_ctrl.swap12
connect issue_slots[5].in_uop.bits.fp_ctrl.ren3, issue_slots[7].out_uop.fp_ctrl.ren3
connect issue_slots[5].in_uop.bits.fp_ctrl.ren2, issue_slots[7].out_uop.fp_ctrl.ren2
connect issue_slots[5].in_uop.bits.fp_ctrl.ren1, issue_slots[7].out_uop.fp_ctrl.ren1
connect issue_slots[5].in_uop.bits.fp_ctrl.wen, issue_slots[7].out_uop.fp_ctrl.wen
connect issue_slots[5].in_uop.bits.fp_ctrl.ldst, issue_slots[7].out_uop.fp_ctrl.ldst
connect issue_slots[5].in_uop.bits.op2_sel, issue_slots[7].out_uop.op2_sel
connect issue_slots[5].in_uop.bits.op1_sel, issue_slots[7].out_uop.op1_sel
connect issue_slots[5].in_uop.bits.imm_packed, issue_slots[7].out_uop.imm_packed
connect issue_slots[5].in_uop.bits.pimm, issue_slots[7].out_uop.pimm
connect issue_slots[5].in_uop.bits.imm_sel, issue_slots[7].out_uop.imm_sel
connect issue_slots[5].in_uop.bits.imm_rename, issue_slots[7].out_uop.imm_rename
connect issue_slots[5].in_uop.bits.taken, issue_slots[7].out_uop.taken
connect issue_slots[5].in_uop.bits.pc_lob, issue_slots[7].out_uop.pc_lob
connect issue_slots[5].in_uop.bits.edge_inst, issue_slots[7].out_uop.edge_inst
connect issue_slots[5].in_uop.bits.ftq_idx, issue_slots[7].out_uop.ftq_idx
connect issue_slots[5].in_uop.bits.is_mov, issue_slots[7].out_uop.is_mov
connect issue_slots[5].in_uop.bits.is_rocc, issue_slots[7].out_uop.is_rocc
connect issue_slots[5].in_uop.bits.is_sys_pc2epc, issue_slots[7].out_uop.is_sys_pc2epc
connect issue_slots[5].in_uop.bits.is_eret, issue_slots[7].out_uop.is_eret
connect issue_slots[5].in_uop.bits.is_amo, issue_slots[7].out_uop.is_amo
connect issue_slots[5].in_uop.bits.is_sfence, issue_slots[7].out_uop.is_sfence
connect issue_slots[5].in_uop.bits.is_fencei, issue_slots[7].out_uop.is_fencei
connect issue_slots[5].in_uop.bits.is_fence, issue_slots[7].out_uop.is_fence
connect issue_slots[5].in_uop.bits.is_sfb, issue_slots[7].out_uop.is_sfb
connect issue_slots[5].in_uop.bits.br_type, issue_slots[7].out_uop.br_type
connect issue_slots[5].in_uop.bits.br_tag, issue_slots[7].out_uop.br_tag
connect issue_slots[5].in_uop.bits.br_mask, issue_slots[7].out_uop.br_mask
connect issue_slots[5].in_uop.bits.dis_col_sel, issue_slots[7].out_uop.dis_col_sel
connect issue_slots[5].in_uop.bits.iw_p3_bypass_hint, issue_slots[7].out_uop.iw_p3_bypass_hint
connect issue_slots[5].in_uop.bits.iw_p2_bypass_hint, issue_slots[7].out_uop.iw_p2_bypass_hint
connect issue_slots[5].in_uop.bits.iw_p1_bypass_hint, issue_slots[7].out_uop.iw_p1_bypass_hint
connect issue_slots[5].in_uop.bits.iw_p2_speculative_child, issue_slots[7].out_uop.iw_p2_speculative_child
connect issue_slots[5].in_uop.bits.iw_p1_speculative_child, issue_slots[7].out_uop.iw_p1_speculative_child
connect issue_slots[5].in_uop.bits.iw_issued_partial_dgen, issue_slots[7].out_uop.iw_issued_partial_dgen
connect issue_slots[5].in_uop.bits.iw_issued_partial_agen, issue_slots[7].out_uop.iw_issued_partial_agen
connect issue_slots[5].in_uop.bits.iw_issued, issue_slots[7].out_uop.iw_issued
connect issue_slots[5].in_uop.bits.fu_code[0], issue_slots[7].out_uop.fu_code[0]
connect issue_slots[5].in_uop.bits.fu_code[1], issue_slots[7].out_uop.fu_code[1]
connect issue_slots[5].in_uop.bits.fu_code[2], issue_slots[7].out_uop.fu_code[2]
connect issue_slots[5].in_uop.bits.fu_code[3], issue_slots[7].out_uop.fu_code[3]
connect issue_slots[5].in_uop.bits.fu_code[4], issue_slots[7].out_uop.fu_code[4]
connect issue_slots[5].in_uop.bits.fu_code[5], issue_slots[7].out_uop.fu_code[5]
connect issue_slots[5].in_uop.bits.fu_code[6], issue_slots[7].out_uop.fu_code[6]
connect issue_slots[5].in_uop.bits.fu_code[7], issue_slots[7].out_uop.fu_code[7]
connect issue_slots[5].in_uop.bits.fu_code[8], issue_slots[7].out_uop.fu_code[8]
connect issue_slots[5].in_uop.bits.fu_code[9], issue_slots[7].out_uop.fu_code[9]
connect issue_slots[5].in_uop.bits.iq_type[0], issue_slots[7].out_uop.iq_type[0]
connect issue_slots[5].in_uop.bits.iq_type[1], issue_slots[7].out_uop.iq_type[1]
connect issue_slots[5].in_uop.bits.iq_type[2], issue_slots[7].out_uop.iq_type[2]
connect issue_slots[5].in_uop.bits.iq_type[3], issue_slots[7].out_uop.iq_type[3]
connect issue_slots[5].in_uop.bits.debug_pc, issue_slots[7].out_uop.debug_pc
connect issue_slots[5].in_uop.bits.is_rvc, issue_slots[7].out_uop.is_rvc
connect issue_slots[5].in_uop.bits.debug_inst, issue_slots[7].out_uop.debug_inst
connect issue_slots[5].in_uop.bits.inst, issue_slots[7].out_uop.inst
node _issue_slots_5_clear_T = neq(shamts_oh[5], UInt<1>(0h0))
connect issue_slots[5].clear, _issue_slots_5_clear_T
connect issue_slots[6].in_uop.valid, UInt<1>(0h0)
connect issue_slots[6].in_uop.bits.debug_tsrc, issue_slots[7].out_uop.debug_tsrc
connect issue_slots[6].in_uop.bits.debug_fsrc, issue_slots[7].out_uop.debug_fsrc
connect issue_slots[6].in_uop.bits.bp_xcpt_if, issue_slots[7].out_uop.bp_xcpt_if
connect issue_slots[6].in_uop.bits.bp_debug_if, issue_slots[7].out_uop.bp_debug_if
connect issue_slots[6].in_uop.bits.xcpt_ma_if, issue_slots[7].out_uop.xcpt_ma_if
connect issue_slots[6].in_uop.bits.xcpt_ae_if, issue_slots[7].out_uop.xcpt_ae_if
connect issue_slots[6].in_uop.bits.xcpt_pf_if, issue_slots[7].out_uop.xcpt_pf_if
connect issue_slots[6].in_uop.bits.fp_typ, issue_slots[7].out_uop.fp_typ
connect issue_slots[6].in_uop.bits.fp_rm, issue_slots[7].out_uop.fp_rm
connect issue_slots[6].in_uop.bits.fp_val, issue_slots[7].out_uop.fp_val
connect issue_slots[6].in_uop.bits.fcn_op, issue_slots[7].out_uop.fcn_op
connect issue_slots[6].in_uop.bits.fcn_dw, issue_slots[7].out_uop.fcn_dw
connect issue_slots[6].in_uop.bits.frs3_en, issue_slots[7].out_uop.frs3_en
connect issue_slots[6].in_uop.bits.lrs2_rtype, issue_slots[7].out_uop.lrs2_rtype
connect issue_slots[6].in_uop.bits.lrs1_rtype, issue_slots[7].out_uop.lrs1_rtype
connect issue_slots[6].in_uop.bits.dst_rtype, issue_slots[7].out_uop.dst_rtype
connect issue_slots[6].in_uop.bits.lrs3, issue_slots[7].out_uop.lrs3
connect issue_slots[6].in_uop.bits.lrs2, issue_slots[7].out_uop.lrs2
connect issue_slots[6].in_uop.bits.lrs1, issue_slots[7].out_uop.lrs1
connect issue_slots[6].in_uop.bits.ldst, issue_slots[7].out_uop.ldst
connect issue_slots[6].in_uop.bits.ldst_is_rs1, issue_slots[7].out_uop.ldst_is_rs1
connect issue_slots[6].in_uop.bits.csr_cmd, issue_slots[7].out_uop.csr_cmd
connect issue_slots[6].in_uop.bits.flush_on_commit, issue_slots[7].out_uop.flush_on_commit
connect issue_slots[6].in_uop.bits.is_unique, issue_slots[7].out_uop.is_unique
connect issue_slots[6].in_uop.bits.uses_stq, issue_slots[7].out_uop.uses_stq
connect issue_slots[6].in_uop.bits.uses_ldq, issue_slots[7].out_uop.uses_ldq
connect issue_slots[6].in_uop.bits.mem_signed, issue_slots[7].out_uop.mem_signed
connect issue_slots[6].in_uop.bits.mem_size, issue_slots[7].out_uop.mem_size
connect issue_slots[6].in_uop.bits.mem_cmd, issue_slots[7].out_uop.mem_cmd
connect issue_slots[6].in_uop.bits.exc_cause, issue_slots[7].out_uop.exc_cause
connect issue_slots[6].in_uop.bits.exception, issue_slots[7].out_uop.exception
connect issue_slots[6].in_uop.bits.stale_pdst, issue_slots[7].out_uop.stale_pdst
connect issue_slots[6].in_uop.bits.ppred_busy, issue_slots[7].out_uop.ppred_busy
connect issue_slots[6].in_uop.bits.prs3_busy, issue_slots[7].out_uop.prs3_busy
connect issue_slots[6].in_uop.bits.prs2_busy, issue_slots[7].out_uop.prs2_busy
connect issue_slots[6].in_uop.bits.prs1_busy, issue_slots[7].out_uop.prs1_busy
connect issue_slots[6].in_uop.bits.ppred, issue_slots[7].out_uop.ppred
connect issue_slots[6].in_uop.bits.prs3, issue_slots[7].out_uop.prs3
connect issue_slots[6].in_uop.bits.prs2, issue_slots[7].out_uop.prs2
connect issue_slots[6].in_uop.bits.prs1, issue_slots[7].out_uop.prs1
connect issue_slots[6].in_uop.bits.pdst, issue_slots[7].out_uop.pdst
connect issue_slots[6].in_uop.bits.rxq_idx, issue_slots[7].out_uop.rxq_idx
connect issue_slots[6].in_uop.bits.stq_idx, issue_slots[7].out_uop.stq_idx
connect issue_slots[6].in_uop.bits.ldq_idx, issue_slots[7].out_uop.ldq_idx
connect issue_slots[6].in_uop.bits.rob_idx, issue_slots[7].out_uop.rob_idx
connect issue_slots[6].in_uop.bits.fp_ctrl.vec, issue_slots[7].out_uop.fp_ctrl.vec
connect issue_slots[6].in_uop.bits.fp_ctrl.wflags, issue_slots[7].out_uop.fp_ctrl.wflags
connect issue_slots[6].in_uop.bits.fp_ctrl.sqrt, issue_slots[7].out_uop.fp_ctrl.sqrt
connect issue_slots[6].in_uop.bits.fp_ctrl.div, issue_slots[7].out_uop.fp_ctrl.div
connect issue_slots[6].in_uop.bits.fp_ctrl.fma, issue_slots[7].out_uop.fp_ctrl.fma
connect issue_slots[6].in_uop.bits.fp_ctrl.fastpipe, issue_slots[7].out_uop.fp_ctrl.fastpipe
connect issue_slots[6].in_uop.bits.fp_ctrl.toint, issue_slots[7].out_uop.fp_ctrl.toint
connect issue_slots[6].in_uop.bits.fp_ctrl.fromint, issue_slots[7].out_uop.fp_ctrl.fromint
connect issue_slots[6].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[7].out_uop.fp_ctrl.typeTagOut
connect issue_slots[6].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[7].out_uop.fp_ctrl.typeTagIn
connect issue_slots[6].in_uop.bits.fp_ctrl.swap23, issue_slots[7].out_uop.fp_ctrl.swap23
connect issue_slots[6].in_uop.bits.fp_ctrl.swap12, issue_slots[7].out_uop.fp_ctrl.swap12
connect issue_slots[6].in_uop.bits.fp_ctrl.ren3, issue_slots[7].out_uop.fp_ctrl.ren3
connect issue_slots[6].in_uop.bits.fp_ctrl.ren2, issue_slots[7].out_uop.fp_ctrl.ren2
connect issue_slots[6].in_uop.bits.fp_ctrl.ren1, issue_slots[7].out_uop.fp_ctrl.ren1
connect issue_slots[6].in_uop.bits.fp_ctrl.wen, issue_slots[7].out_uop.fp_ctrl.wen
connect issue_slots[6].in_uop.bits.fp_ctrl.ldst, issue_slots[7].out_uop.fp_ctrl.ldst
connect issue_slots[6].in_uop.bits.op2_sel, issue_slots[7].out_uop.op2_sel
connect issue_slots[6].in_uop.bits.op1_sel, issue_slots[7].out_uop.op1_sel
connect issue_slots[6].in_uop.bits.imm_packed, issue_slots[7].out_uop.imm_packed
connect issue_slots[6].in_uop.bits.pimm, issue_slots[7].out_uop.pimm
connect issue_slots[6].in_uop.bits.imm_sel, issue_slots[7].out_uop.imm_sel
connect issue_slots[6].in_uop.bits.imm_rename, issue_slots[7].out_uop.imm_rename
connect issue_slots[6].in_uop.bits.taken, issue_slots[7].out_uop.taken
connect issue_slots[6].in_uop.bits.pc_lob, issue_slots[7].out_uop.pc_lob
connect issue_slots[6].in_uop.bits.edge_inst, issue_slots[7].out_uop.edge_inst
connect issue_slots[6].in_uop.bits.ftq_idx, issue_slots[7].out_uop.ftq_idx
connect issue_slots[6].in_uop.bits.is_mov, issue_slots[7].out_uop.is_mov
connect issue_slots[6].in_uop.bits.is_rocc, issue_slots[7].out_uop.is_rocc
connect issue_slots[6].in_uop.bits.is_sys_pc2epc, issue_slots[7].out_uop.is_sys_pc2epc
connect issue_slots[6].in_uop.bits.is_eret, issue_slots[7].out_uop.is_eret
connect issue_slots[6].in_uop.bits.is_amo, issue_slots[7].out_uop.is_amo
connect issue_slots[6].in_uop.bits.is_sfence, issue_slots[7].out_uop.is_sfence
connect issue_slots[6].in_uop.bits.is_fencei, issue_slots[7].out_uop.is_fencei
connect issue_slots[6].in_uop.bits.is_fence, issue_slots[7].out_uop.is_fence
connect issue_slots[6].in_uop.bits.is_sfb, issue_slots[7].out_uop.is_sfb
connect issue_slots[6].in_uop.bits.br_type, issue_slots[7].out_uop.br_type
connect issue_slots[6].in_uop.bits.br_tag, issue_slots[7].out_uop.br_tag
connect issue_slots[6].in_uop.bits.br_mask, issue_slots[7].out_uop.br_mask
connect issue_slots[6].in_uop.bits.dis_col_sel, issue_slots[7].out_uop.dis_col_sel
connect issue_slots[6].in_uop.bits.iw_p3_bypass_hint, issue_slots[7].out_uop.iw_p3_bypass_hint
connect issue_slots[6].in_uop.bits.iw_p2_bypass_hint, issue_slots[7].out_uop.iw_p2_bypass_hint
connect issue_slots[6].in_uop.bits.iw_p1_bypass_hint, issue_slots[7].out_uop.iw_p1_bypass_hint
connect issue_slots[6].in_uop.bits.iw_p2_speculative_child, issue_slots[7].out_uop.iw_p2_speculative_child
connect issue_slots[6].in_uop.bits.iw_p1_speculative_child, issue_slots[7].out_uop.iw_p1_speculative_child
connect issue_slots[6].in_uop.bits.iw_issued_partial_dgen, issue_slots[7].out_uop.iw_issued_partial_dgen
connect issue_slots[6].in_uop.bits.iw_issued_partial_agen, issue_slots[7].out_uop.iw_issued_partial_agen
connect issue_slots[6].in_uop.bits.iw_issued, issue_slots[7].out_uop.iw_issued
connect issue_slots[6].in_uop.bits.fu_code[0], issue_slots[7].out_uop.fu_code[0]
connect issue_slots[6].in_uop.bits.fu_code[1], issue_slots[7].out_uop.fu_code[1]
connect issue_slots[6].in_uop.bits.fu_code[2], issue_slots[7].out_uop.fu_code[2]
connect issue_slots[6].in_uop.bits.fu_code[3], issue_slots[7].out_uop.fu_code[3]
connect issue_slots[6].in_uop.bits.fu_code[4], issue_slots[7].out_uop.fu_code[4]
connect issue_slots[6].in_uop.bits.fu_code[5], issue_slots[7].out_uop.fu_code[5]
connect issue_slots[6].in_uop.bits.fu_code[6], issue_slots[7].out_uop.fu_code[6]
connect issue_slots[6].in_uop.bits.fu_code[7], issue_slots[7].out_uop.fu_code[7]
connect issue_slots[6].in_uop.bits.fu_code[8], issue_slots[7].out_uop.fu_code[8]
connect issue_slots[6].in_uop.bits.fu_code[9], issue_slots[7].out_uop.fu_code[9]
connect issue_slots[6].in_uop.bits.iq_type[0], issue_slots[7].out_uop.iq_type[0]
connect issue_slots[6].in_uop.bits.iq_type[1], issue_slots[7].out_uop.iq_type[1]
connect issue_slots[6].in_uop.bits.iq_type[2], issue_slots[7].out_uop.iq_type[2]
connect issue_slots[6].in_uop.bits.iq_type[3], issue_slots[7].out_uop.iq_type[3]
connect issue_slots[6].in_uop.bits.debug_pc, issue_slots[7].out_uop.debug_pc
connect issue_slots[6].in_uop.bits.is_rvc, issue_slots[7].out_uop.is_rvc
connect issue_slots[6].in_uop.bits.debug_inst, issue_slots[7].out_uop.debug_inst
connect issue_slots[6].in_uop.bits.inst, issue_slots[7].out_uop.inst
node _T_174 = eq(shamts_oh[7], UInt<1>(0h1))
when _T_174 :
connect issue_slots[6].in_uop.valid, issue_slots[7].will_be_valid
connect issue_slots[6].in_uop.bits.debug_tsrc, issue_slots[7].out_uop.debug_tsrc
connect issue_slots[6].in_uop.bits.debug_fsrc, issue_slots[7].out_uop.debug_fsrc
connect issue_slots[6].in_uop.bits.bp_xcpt_if, issue_slots[7].out_uop.bp_xcpt_if
connect issue_slots[6].in_uop.bits.bp_debug_if, issue_slots[7].out_uop.bp_debug_if
connect issue_slots[6].in_uop.bits.xcpt_ma_if, issue_slots[7].out_uop.xcpt_ma_if
connect issue_slots[6].in_uop.bits.xcpt_ae_if, issue_slots[7].out_uop.xcpt_ae_if
connect issue_slots[6].in_uop.bits.xcpt_pf_if, issue_slots[7].out_uop.xcpt_pf_if
connect issue_slots[6].in_uop.bits.fp_typ, issue_slots[7].out_uop.fp_typ
connect issue_slots[6].in_uop.bits.fp_rm, issue_slots[7].out_uop.fp_rm
connect issue_slots[6].in_uop.bits.fp_val, issue_slots[7].out_uop.fp_val
connect issue_slots[6].in_uop.bits.fcn_op, issue_slots[7].out_uop.fcn_op
connect issue_slots[6].in_uop.bits.fcn_dw, issue_slots[7].out_uop.fcn_dw
connect issue_slots[6].in_uop.bits.frs3_en, issue_slots[7].out_uop.frs3_en
connect issue_slots[6].in_uop.bits.lrs2_rtype, issue_slots[7].out_uop.lrs2_rtype
connect issue_slots[6].in_uop.bits.lrs1_rtype, issue_slots[7].out_uop.lrs1_rtype
connect issue_slots[6].in_uop.bits.dst_rtype, issue_slots[7].out_uop.dst_rtype
connect issue_slots[6].in_uop.bits.lrs3, issue_slots[7].out_uop.lrs3
connect issue_slots[6].in_uop.bits.lrs2, issue_slots[7].out_uop.lrs2
connect issue_slots[6].in_uop.bits.lrs1, issue_slots[7].out_uop.lrs1
connect issue_slots[6].in_uop.bits.ldst, issue_slots[7].out_uop.ldst
connect issue_slots[6].in_uop.bits.ldst_is_rs1, issue_slots[7].out_uop.ldst_is_rs1
connect issue_slots[6].in_uop.bits.csr_cmd, issue_slots[7].out_uop.csr_cmd
connect issue_slots[6].in_uop.bits.flush_on_commit, issue_slots[7].out_uop.flush_on_commit
connect issue_slots[6].in_uop.bits.is_unique, issue_slots[7].out_uop.is_unique
connect issue_slots[6].in_uop.bits.uses_stq, issue_slots[7].out_uop.uses_stq
connect issue_slots[6].in_uop.bits.uses_ldq, issue_slots[7].out_uop.uses_ldq
connect issue_slots[6].in_uop.bits.mem_signed, issue_slots[7].out_uop.mem_signed
connect issue_slots[6].in_uop.bits.mem_size, issue_slots[7].out_uop.mem_size
connect issue_slots[6].in_uop.bits.mem_cmd, issue_slots[7].out_uop.mem_cmd
connect issue_slots[6].in_uop.bits.exc_cause, issue_slots[7].out_uop.exc_cause
connect issue_slots[6].in_uop.bits.exception, issue_slots[7].out_uop.exception
connect issue_slots[6].in_uop.bits.stale_pdst, issue_slots[7].out_uop.stale_pdst
connect issue_slots[6].in_uop.bits.ppred_busy, issue_slots[7].out_uop.ppred_busy
connect issue_slots[6].in_uop.bits.prs3_busy, issue_slots[7].out_uop.prs3_busy
connect issue_slots[6].in_uop.bits.prs2_busy, issue_slots[7].out_uop.prs2_busy
connect issue_slots[6].in_uop.bits.prs1_busy, issue_slots[7].out_uop.prs1_busy
connect issue_slots[6].in_uop.bits.ppred, issue_slots[7].out_uop.ppred
connect issue_slots[6].in_uop.bits.prs3, issue_slots[7].out_uop.prs3
connect issue_slots[6].in_uop.bits.prs2, issue_slots[7].out_uop.prs2
connect issue_slots[6].in_uop.bits.prs1, issue_slots[7].out_uop.prs1
connect issue_slots[6].in_uop.bits.pdst, issue_slots[7].out_uop.pdst
connect issue_slots[6].in_uop.bits.rxq_idx, issue_slots[7].out_uop.rxq_idx
connect issue_slots[6].in_uop.bits.stq_idx, issue_slots[7].out_uop.stq_idx
connect issue_slots[6].in_uop.bits.ldq_idx, issue_slots[7].out_uop.ldq_idx
connect issue_slots[6].in_uop.bits.rob_idx, issue_slots[7].out_uop.rob_idx
connect issue_slots[6].in_uop.bits.fp_ctrl.vec, issue_slots[7].out_uop.fp_ctrl.vec
connect issue_slots[6].in_uop.bits.fp_ctrl.wflags, issue_slots[7].out_uop.fp_ctrl.wflags
connect issue_slots[6].in_uop.bits.fp_ctrl.sqrt, issue_slots[7].out_uop.fp_ctrl.sqrt
connect issue_slots[6].in_uop.bits.fp_ctrl.div, issue_slots[7].out_uop.fp_ctrl.div
connect issue_slots[6].in_uop.bits.fp_ctrl.fma, issue_slots[7].out_uop.fp_ctrl.fma
connect issue_slots[6].in_uop.bits.fp_ctrl.fastpipe, issue_slots[7].out_uop.fp_ctrl.fastpipe
connect issue_slots[6].in_uop.bits.fp_ctrl.toint, issue_slots[7].out_uop.fp_ctrl.toint
connect issue_slots[6].in_uop.bits.fp_ctrl.fromint, issue_slots[7].out_uop.fp_ctrl.fromint
connect issue_slots[6].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[7].out_uop.fp_ctrl.typeTagOut
connect issue_slots[6].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[7].out_uop.fp_ctrl.typeTagIn
connect issue_slots[6].in_uop.bits.fp_ctrl.swap23, issue_slots[7].out_uop.fp_ctrl.swap23
connect issue_slots[6].in_uop.bits.fp_ctrl.swap12, issue_slots[7].out_uop.fp_ctrl.swap12
connect issue_slots[6].in_uop.bits.fp_ctrl.ren3, issue_slots[7].out_uop.fp_ctrl.ren3
connect issue_slots[6].in_uop.bits.fp_ctrl.ren2, issue_slots[7].out_uop.fp_ctrl.ren2
connect issue_slots[6].in_uop.bits.fp_ctrl.ren1, issue_slots[7].out_uop.fp_ctrl.ren1
connect issue_slots[6].in_uop.bits.fp_ctrl.wen, issue_slots[7].out_uop.fp_ctrl.wen
connect issue_slots[6].in_uop.bits.fp_ctrl.ldst, issue_slots[7].out_uop.fp_ctrl.ldst
connect issue_slots[6].in_uop.bits.op2_sel, issue_slots[7].out_uop.op2_sel
connect issue_slots[6].in_uop.bits.op1_sel, issue_slots[7].out_uop.op1_sel
connect issue_slots[6].in_uop.bits.imm_packed, issue_slots[7].out_uop.imm_packed
connect issue_slots[6].in_uop.bits.pimm, issue_slots[7].out_uop.pimm
connect issue_slots[6].in_uop.bits.imm_sel, issue_slots[7].out_uop.imm_sel
connect issue_slots[6].in_uop.bits.imm_rename, issue_slots[7].out_uop.imm_rename
connect issue_slots[6].in_uop.bits.taken, issue_slots[7].out_uop.taken
connect issue_slots[6].in_uop.bits.pc_lob, issue_slots[7].out_uop.pc_lob
connect issue_slots[6].in_uop.bits.edge_inst, issue_slots[7].out_uop.edge_inst
connect issue_slots[6].in_uop.bits.ftq_idx, issue_slots[7].out_uop.ftq_idx
connect issue_slots[6].in_uop.bits.is_mov, issue_slots[7].out_uop.is_mov
connect issue_slots[6].in_uop.bits.is_rocc, issue_slots[7].out_uop.is_rocc
connect issue_slots[6].in_uop.bits.is_sys_pc2epc, issue_slots[7].out_uop.is_sys_pc2epc
connect issue_slots[6].in_uop.bits.is_eret, issue_slots[7].out_uop.is_eret
connect issue_slots[6].in_uop.bits.is_amo, issue_slots[7].out_uop.is_amo
connect issue_slots[6].in_uop.bits.is_sfence, issue_slots[7].out_uop.is_sfence
connect issue_slots[6].in_uop.bits.is_fencei, issue_slots[7].out_uop.is_fencei
connect issue_slots[6].in_uop.bits.is_fence, issue_slots[7].out_uop.is_fence
connect issue_slots[6].in_uop.bits.is_sfb, issue_slots[7].out_uop.is_sfb
connect issue_slots[6].in_uop.bits.br_type, issue_slots[7].out_uop.br_type
connect issue_slots[6].in_uop.bits.br_tag, issue_slots[7].out_uop.br_tag
connect issue_slots[6].in_uop.bits.br_mask, issue_slots[7].out_uop.br_mask
connect issue_slots[6].in_uop.bits.dis_col_sel, issue_slots[7].out_uop.dis_col_sel
connect issue_slots[6].in_uop.bits.iw_p3_bypass_hint, issue_slots[7].out_uop.iw_p3_bypass_hint
connect issue_slots[6].in_uop.bits.iw_p2_bypass_hint, issue_slots[7].out_uop.iw_p2_bypass_hint
connect issue_slots[6].in_uop.bits.iw_p1_bypass_hint, issue_slots[7].out_uop.iw_p1_bypass_hint
connect issue_slots[6].in_uop.bits.iw_p2_speculative_child, issue_slots[7].out_uop.iw_p2_speculative_child
connect issue_slots[6].in_uop.bits.iw_p1_speculative_child, issue_slots[7].out_uop.iw_p1_speculative_child
connect issue_slots[6].in_uop.bits.iw_issued_partial_dgen, issue_slots[7].out_uop.iw_issued_partial_dgen
connect issue_slots[6].in_uop.bits.iw_issued_partial_agen, issue_slots[7].out_uop.iw_issued_partial_agen
connect issue_slots[6].in_uop.bits.iw_issued, issue_slots[7].out_uop.iw_issued
connect issue_slots[6].in_uop.bits.fu_code[0], issue_slots[7].out_uop.fu_code[0]
connect issue_slots[6].in_uop.bits.fu_code[1], issue_slots[7].out_uop.fu_code[1]
connect issue_slots[6].in_uop.bits.fu_code[2], issue_slots[7].out_uop.fu_code[2]
connect issue_slots[6].in_uop.bits.fu_code[3], issue_slots[7].out_uop.fu_code[3]
connect issue_slots[6].in_uop.bits.fu_code[4], issue_slots[7].out_uop.fu_code[4]
connect issue_slots[6].in_uop.bits.fu_code[5], issue_slots[7].out_uop.fu_code[5]
connect issue_slots[6].in_uop.bits.fu_code[6], issue_slots[7].out_uop.fu_code[6]
connect issue_slots[6].in_uop.bits.fu_code[7], issue_slots[7].out_uop.fu_code[7]
connect issue_slots[6].in_uop.bits.fu_code[8], issue_slots[7].out_uop.fu_code[8]
connect issue_slots[6].in_uop.bits.fu_code[9], issue_slots[7].out_uop.fu_code[9]
connect issue_slots[6].in_uop.bits.iq_type[0], issue_slots[7].out_uop.iq_type[0]
connect issue_slots[6].in_uop.bits.iq_type[1], issue_slots[7].out_uop.iq_type[1]
connect issue_slots[6].in_uop.bits.iq_type[2], issue_slots[7].out_uop.iq_type[2]
connect issue_slots[6].in_uop.bits.iq_type[3], issue_slots[7].out_uop.iq_type[3]
connect issue_slots[6].in_uop.bits.debug_pc, issue_slots[7].out_uop.debug_pc
connect issue_slots[6].in_uop.bits.is_rvc, issue_slots[7].out_uop.is_rvc
connect issue_slots[6].in_uop.bits.debug_inst, issue_slots[7].out_uop.debug_inst
connect issue_slots[6].in_uop.bits.inst, issue_slots[7].out_uop.inst
node _T_175 = eq(shamts_oh[8], UInt<2>(0h2))
when _T_175 :
connect issue_slots[6].in_uop.valid, issue_slots[8].will_be_valid
connect issue_slots[6].in_uop.bits.debug_tsrc, issue_slots[8].out_uop.debug_tsrc
connect issue_slots[6].in_uop.bits.debug_fsrc, issue_slots[8].out_uop.debug_fsrc
connect issue_slots[6].in_uop.bits.bp_xcpt_if, issue_slots[8].out_uop.bp_xcpt_if
connect issue_slots[6].in_uop.bits.bp_debug_if, issue_slots[8].out_uop.bp_debug_if
connect issue_slots[6].in_uop.bits.xcpt_ma_if, issue_slots[8].out_uop.xcpt_ma_if
connect issue_slots[6].in_uop.bits.xcpt_ae_if, issue_slots[8].out_uop.xcpt_ae_if
connect issue_slots[6].in_uop.bits.xcpt_pf_if, issue_slots[8].out_uop.xcpt_pf_if
connect issue_slots[6].in_uop.bits.fp_typ, issue_slots[8].out_uop.fp_typ
connect issue_slots[6].in_uop.bits.fp_rm, issue_slots[8].out_uop.fp_rm
connect issue_slots[6].in_uop.bits.fp_val, issue_slots[8].out_uop.fp_val
connect issue_slots[6].in_uop.bits.fcn_op, issue_slots[8].out_uop.fcn_op
connect issue_slots[6].in_uop.bits.fcn_dw, issue_slots[8].out_uop.fcn_dw
connect issue_slots[6].in_uop.bits.frs3_en, issue_slots[8].out_uop.frs3_en
connect issue_slots[6].in_uop.bits.lrs2_rtype, issue_slots[8].out_uop.lrs2_rtype
connect issue_slots[6].in_uop.bits.lrs1_rtype, issue_slots[8].out_uop.lrs1_rtype
connect issue_slots[6].in_uop.bits.dst_rtype, issue_slots[8].out_uop.dst_rtype
connect issue_slots[6].in_uop.bits.lrs3, issue_slots[8].out_uop.lrs3
connect issue_slots[6].in_uop.bits.lrs2, issue_slots[8].out_uop.lrs2
connect issue_slots[6].in_uop.bits.lrs1, issue_slots[8].out_uop.lrs1
connect issue_slots[6].in_uop.bits.ldst, issue_slots[8].out_uop.ldst
connect issue_slots[6].in_uop.bits.ldst_is_rs1, issue_slots[8].out_uop.ldst_is_rs1
connect issue_slots[6].in_uop.bits.csr_cmd, issue_slots[8].out_uop.csr_cmd
connect issue_slots[6].in_uop.bits.flush_on_commit, issue_slots[8].out_uop.flush_on_commit
connect issue_slots[6].in_uop.bits.is_unique, issue_slots[8].out_uop.is_unique
connect issue_slots[6].in_uop.bits.uses_stq, issue_slots[8].out_uop.uses_stq
connect issue_slots[6].in_uop.bits.uses_ldq, issue_slots[8].out_uop.uses_ldq
connect issue_slots[6].in_uop.bits.mem_signed, issue_slots[8].out_uop.mem_signed
connect issue_slots[6].in_uop.bits.mem_size, issue_slots[8].out_uop.mem_size
connect issue_slots[6].in_uop.bits.mem_cmd, issue_slots[8].out_uop.mem_cmd
connect issue_slots[6].in_uop.bits.exc_cause, issue_slots[8].out_uop.exc_cause
connect issue_slots[6].in_uop.bits.exception, issue_slots[8].out_uop.exception
connect issue_slots[6].in_uop.bits.stale_pdst, issue_slots[8].out_uop.stale_pdst
connect issue_slots[6].in_uop.bits.ppred_busy, issue_slots[8].out_uop.ppred_busy
connect issue_slots[6].in_uop.bits.prs3_busy, issue_slots[8].out_uop.prs3_busy
connect issue_slots[6].in_uop.bits.prs2_busy, issue_slots[8].out_uop.prs2_busy
connect issue_slots[6].in_uop.bits.prs1_busy, issue_slots[8].out_uop.prs1_busy
connect issue_slots[6].in_uop.bits.ppred, issue_slots[8].out_uop.ppred
connect issue_slots[6].in_uop.bits.prs3, issue_slots[8].out_uop.prs3
connect issue_slots[6].in_uop.bits.prs2, issue_slots[8].out_uop.prs2
connect issue_slots[6].in_uop.bits.prs1, issue_slots[8].out_uop.prs1
connect issue_slots[6].in_uop.bits.pdst, issue_slots[8].out_uop.pdst
connect issue_slots[6].in_uop.bits.rxq_idx, issue_slots[8].out_uop.rxq_idx
connect issue_slots[6].in_uop.bits.stq_idx, issue_slots[8].out_uop.stq_idx
connect issue_slots[6].in_uop.bits.ldq_idx, issue_slots[8].out_uop.ldq_idx
connect issue_slots[6].in_uop.bits.rob_idx, issue_slots[8].out_uop.rob_idx
connect issue_slots[6].in_uop.bits.fp_ctrl.vec, issue_slots[8].out_uop.fp_ctrl.vec
connect issue_slots[6].in_uop.bits.fp_ctrl.wflags, issue_slots[8].out_uop.fp_ctrl.wflags
connect issue_slots[6].in_uop.bits.fp_ctrl.sqrt, issue_slots[8].out_uop.fp_ctrl.sqrt
connect issue_slots[6].in_uop.bits.fp_ctrl.div, issue_slots[8].out_uop.fp_ctrl.div
connect issue_slots[6].in_uop.bits.fp_ctrl.fma, issue_slots[8].out_uop.fp_ctrl.fma
connect issue_slots[6].in_uop.bits.fp_ctrl.fastpipe, issue_slots[8].out_uop.fp_ctrl.fastpipe
connect issue_slots[6].in_uop.bits.fp_ctrl.toint, issue_slots[8].out_uop.fp_ctrl.toint
connect issue_slots[6].in_uop.bits.fp_ctrl.fromint, issue_slots[8].out_uop.fp_ctrl.fromint
connect issue_slots[6].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[8].out_uop.fp_ctrl.typeTagOut
connect issue_slots[6].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[8].out_uop.fp_ctrl.typeTagIn
connect issue_slots[6].in_uop.bits.fp_ctrl.swap23, issue_slots[8].out_uop.fp_ctrl.swap23
connect issue_slots[6].in_uop.bits.fp_ctrl.swap12, issue_slots[8].out_uop.fp_ctrl.swap12
connect issue_slots[6].in_uop.bits.fp_ctrl.ren3, issue_slots[8].out_uop.fp_ctrl.ren3
connect issue_slots[6].in_uop.bits.fp_ctrl.ren2, issue_slots[8].out_uop.fp_ctrl.ren2
connect issue_slots[6].in_uop.bits.fp_ctrl.ren1, issue_slots[8].out_uop.fp_ctrl.ren1
connect issue_slots[6].in_uop.bits.fp_ctrl.wen, issue_slots[8].out_uop.fp_ctrl.wen
connect issue_slots[6].in_uop.bits.fp_ctrl.ldst, issue_slots[8].out_uop.fp_ctrl.ldst
connect issue_slots[6].in_uop.bits.op2_sel, issue_slots[8].out_uop.op2_sel
connect issue_slots[6].in_uop.bits.op1_sel, issue_slots[8].out_uop.op1_sel
connect issue_slots[6].in_uop.bits.imm_packed, issue_slots[8].out_uop.imm_packed
connect issue_slots[6].in_uop.bits.pimm, issue_slots[8].out_uop.pimm
connect issue_slots[6].in_uop.bits.imm_sel, issue_slots[8].out_uop.imm_sel
connect issue_slots[6].in_uop.bits.imm_rename, issue_slots[8].out_uop.imm_rename
connect issue_slots[6].in_uop.bits.taken, issue_slots[8].out_uop.taken
connect issue_slots[6].in_uop.bits.pc_lob, issue_slots[8].out_uop.pc_lob
connect issue_slots[6].in_uop.bits.edge_inst, issue_slots[8].out_uop.edge_inst
connect issue_slots[6].in_uop.bits.ftq_idx, issue_slots[8].out_uop.ftq_idx
connect issue_slots[6].in_uop.bits.is_mov, issue_slots[8].out_uop.is_mov
connect issue_slots[6].in_uop.bits.is_rocc, issue_slots[8].out_uop.is_rocc
connect issue_slots[6].in_uop.bits.is_sys_pc2epc, issue_slots[8].out_uop.is_sys_pc2epc
connect issue_slots[6].in_uop.bits.is_eret, issue_slots[8].out_uop.is_eret
connect issue_slots[6].in_uop.bits.is_amo, issue_slots[8].out_uop.is_amo
connect issue_slots[6].in_uop.bits.is_sfence, issue_slots[8].out_uop.is_sfence
connect issue_slots[6].in_uop.bits.is_fencei, issue_slots[8].out_uop.is_fencei
connect issue_slots[6].in_uop.bits.is_fence, issue_slots[8].out_uop.is_fence
connect issue_slots[6].in_uop.bits.is_sfb, issue_slots[8].out_uop.is_sfb
connect issue_slots[6].in_uop.bits.br_type, issue_slots[8].out_uop.br_type
connect issue_slots[6].in_uop.bits.br_tag, issue_slots[8].out_uop.br_tag
connect issue_slots[6].in_uop.bits.br_mask, issue_slots[8].out_uop.br_mask
connect issue_slots[6].in_uop.bits.dis_col_sel, issue_slots[8].out_uop.dis_col_sel
connect issue_slots[6].in_uop.bits.iw_p3_bypass_hint, issue_slots[8].out_uop.iw_p3_bypass_hint
connect issue_slots[6].in_uop.bits.iw_p2_bypass_hint, issue_slots[8].out_uop.iw_p2_bypass_hint
connect issue_slots[6].in_uop.bits.iw_p1_bypass_hint, issue_slots[8].out_uop.iw_p1_bypass_hint
connect issue_slots[6].in_uop.bits.iw_p2_speculative_child, issue_slots[8].out_uop.iw_p2_speculative_child
connect issue_slots[6].in_uop.bits.iw_p1_speculative_child, issue_slots[8].out_uop.iw_p1_speculative_child
connect issue_slots[6].in_uop.bits.iw_issued_partial_dgen, issue_slots[8].out_uop.iw_issued_partial_dgen
connect issue_slots[6].in_uop.bits.iw_issued_partial_agen, issue_slots[8].out_uop.iw_issued_partial_agen
connect issue_slots[6].in_uop.bits.iw_issued, issue_slots[8].out_uop.iw_issued
connect issue_slots[6].in_uop.bits.fu_code[0], issue_slots[8].out_uop.fu_code[0]
connect issue_slots[6].in_uop.bits.fu_code[1], issue_slots[8].out_uop.fu_code[1]
connect issue_slots[6].in_uop.bits.fu_code[2], issue_slots[8].out_uop.fu_code[2]
connect issue_slots[6].in_uop.bits.fu_code[3], issue_slots[8].out_uop.fu_code[3]
connect issue_slots[6].in_uop.bits.fu_code[4], issue_slots[8].out_uop.fu_code[4]
connect issue_slots[6].in_uop.bits.fu_code[5], issue_slots[8].out_uop.fu_code[5]
connect issue_slots[6].in_uop.bits.fu_code[6], issue_slots[8].out_uop.fu_code[6]
connect issue_slots[6].in_uop.bits.fu_code[7], issue_slots[8].out_uop.fu_code[7]
connect issue_slots[6].in_uop.bits.fu_code[8], issue_slots[8].out_uop.fu_code[8]
connect issue_slots[6].in_uop.bits.fu_code[9], issue_slots[8].out_uop.fu_code[9]
connect issue_slots[6].in_uop.bits.iq_type[0], issue_slots[8].out_uop.iq_type[0]
connect issue_slots[6].in_uop.bits.iq_type[1], issue_slots[8].out_uop.iq_type[1]
connect issue_slots[6].in_uop.bits.iq_type[2], issue_slots[8].out_uop.iq_type[2]
connect issue_slots[6].in_uop.bits.iq_type[3], issue_slots[8].out_uop.iq_type[3]
connect issue_slots[6].in_uop.bits.debug_pc, issue_slots[8].out_uop.debug_pc
connect issue_slots[6].in_uop.bits.is_rvc, issue_slots[8].out_uop.is_rvc
connect issue_slots[6].in_uop.bits.debug_inst, issue_slots[8].out_uop.debug_inst
connect issue_slots[6].in_uop.bits.inst, issue_slots[8].out_uop.inst
node _issue_slots_6_clear_T = neq(shamts_oh[6], UInt<1>(0h0))
connect issue_slots[6].clear, _issue_slots_6_clear_T
connect issue_slots[7].in_uop.valid, UInt<1>(0h0)
connect issue_slots[7].in_uop.bits.debug_tsrc, issue_slots[8].out_uop.debug_tsrc
connect issue_slots[7].in_uop.bits.debug_fsrc, issue_slots[8].out_uop.debug_fsrc
connect issue_slots[7].in_uop.bits.bp_xcpt_if, issue_slots[8].out_uop.bp_xcpt_if
connect issue_slots[7].in_uop.bits.bp_debug_if, issue_slots[8].out_uop.bp_debug_if
connect issue_slots[7].in_uop.bits.xcpt_ma_if, issue_slots[8].out_uop.xcpt_ma_if
connect issue_slots[7].in_uop.bits.xcpt_ae_if, issue_slots[8].out_uop.xcpt_ae_if
connect issue_slots[7].in_uop.bits.xcpt_pf_if, issue_slots[8].out_uop.xcpt_pf_if
connect issue_slots[7].in_uop.bits.fp_typ, issue_slots[8].out_uop.fp_typ
connect issue_slots[7].in_uop.bits.fp_rm, issue_slots[8].out_uop.fp_rm
connect issue_slots[7].in_uop.bits.fp_val, issue_slots[8].out_uop.fp_val
connect issue_slots[7].in_uop.bits.fcn_op, issue_slots[8].out_uop.fcn_op
connect issue_slots[7].in_uop.bits.fcn_dw, issue_slots[8].out_uop.fcn_dw
connect issue_slots[7].in_uop.bits.frs3_en, issue_slots[8].out_uop.frs3_en
connect issue_slots[7].in_uop.bits.lrs2_rtype, issue_slots[8].out_uop.lrs2_rtype
connect issue_slots[7].in_uop.bits.lrs1_rtype, issue_slots[8].out_uop.lrs1_rtype
connect issue_slots[7].in_uop.bits.dst_rtype, issue_slots[8].out_uop.dst_rtype
connect issue_slots[7].in_uop.bits.lrs3, issue_slots[8].out_uop.lrs3
connect issue_slots[7].in_uop.bits.lrs2, issue_slots[8].out_uop.lrs2
connect issue_slots[7].in_uop.bits.lrs1, issue_slots[8].out_uop.lrs1
connect issue_slots[7].in_uop.bits.ldst, issue_slots[8].out_uop.ldst
connect issue_slots[7].in_uop.bits.ldst_is_rs1, issue_slots[8].out_uop.ldst_is_rs1
connect issue_slots[7].in_uop.bits.csr_cmd, issue_slots[8].out_uop.csr_cmd
connect issue_slots[7].in_uop.bits.flush_on_commit, issue_slots[8].out_uop.flush_on_commit
connect issue_slots[7].in_uop.bits.is_unique, issue_slots[8].out_uop.is_unique
connect issue_slots[7].in_uop.bits.uses_stq, issue_slots[8].out_uop.uses_stq
connect issue_slots[7].in_uop.bits.uses_ldq, issue_slots[8].out_uop.uses_ldq
connect issue_slots[7].in_uop.bits.mem_signed, issue_slots[8].out_uop.mem_signed
connect issue_slots[7].in_uop.bits.mem_size, issue_slots[8].out_uop.mem_size
connect issue_slots[7].in_uop.bits.mem_cmd, issue_slots[8].out_uop.mem_cmd
connect issue_slots[7].in_uop.bits.exc_cause, issue_slots[8].out_uop.exc_cause
connect issue_slots[7].in_uop.bits.exception, issue_slots[8].out_uop.exception
connect issue_slots[7].in_uop.bits.stale_pdst, issue_slots[8].out_uop.stale_pdst
connect issue_slots[7].in_uop.bits.ppred_busy, issue_slots[8].out_uop.ppred_busy
connect issue_slots[7].in_uop.bits.prs3_busy, issue_slots[8].out_uop.prs3_busy
connect issue_slots[7].in_uop.bits.prs2_busy, issue_slots[8].out_uop.prs2_busy
connect issue_slots[7].in_uop.bits.prs1_busy, issue_slots[8].out_uop.prs1_busy
connect issue_slots[7].in_uop.bits.ppred, issue_slots[8].out_uop.ppred
connect issue_slots[7].in_uop.bits.prs3, issue_slots[8].out_uop.prs3
connect issue_slots[7].in_uop.bits.prs2, issue_slots[8].out_uop.prs2
connect issue_slots[7].in_uop.bits.prs1, issue_slots[8].out_uop.prs1
connect issue_slots[7].in_uop.bits.pdst, issue_slots[8].out_uop.pdst
connect issue_slots[7].in_uop.bits.rxq_idx, issue_slots[8].out_uop.rxq_idx
connect issue_slots[7].in_uop.bits.stq_idx, issue_slots[8].out_uop.stq_idx
connect issue_slots[7].in_uop.bits.ldq_idx, issue_slots[8].out_uop.ldq_idx
connect issue_slots[7].in_uop.bits.rob_idx, issue_slots[8].out_uop.rob_idx
connect issue_slots[7].in_uop.bits.fp_ctrl.vec, issue_slots[8].out_uop.fp_ctrl.vec
connect issue_slots[7].in_uop.bits.fp_ctrl.wflags, issue_slots[8].out_uop.fp_ctrl.wflags
connect issue_slots[7].in_uop.bits.fp_ctrl.sqrt, issue_slots[8].out_uop.fp_ctrl.sqrt
connect issue_slots[7].in_uop.bits.fp_ctrl.div, issue_slots[8].out_uop.fp_ctrl.div
connect issue_slots[7].in_uop.bits.fp_ctrl.fma, issue_slots[8].out_uop.fp_ctrl.fma
connect issue_slots[7].in_uop.bits.fp_ctrl.fastpipe, issue_slots[8].out_uop.fp_ctrl.fastpipe
connect issue_slots[7].in_uop.bits.fp_ctrl.toint, issue_slots[8].out_uop.fp_ctrl.toint
connect issue_slots[7].in_uop.bits.fp_ctrl.fromint, issue_slots[8].out_uop.fp_ctrl.fromint
connect issue_slots[7].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[8].out_uop.fp_ctrl.typeTagOut
connect issue_slots[7].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[8].out_uop.fp_ctrl.typeTagIn
connect issue_slots[7].in_uop.bits.fp_ctrl.swap23, issue_slots[8].out_uop.fp_ctrl.swap23
connect issue_slots[7].in_uop.bits.fp_ctrl.swap12, issue_slots[8].out_uop.fp_ctrl.swap12
connect issue_slots[7].in_uop.bits.fp_ctrl.ren3, issue_slots[8].out_uop.fp_ctrl.ren3
connect issue_slots[7].in_uop.bits.fp_ctrl.ren2, issue_slots[8].out_uop.fp_ctrl.ren2
connect issue_slots[7].in_uop.bits.fp_ctrl.ren1, issue_slots[8].out_uop.fp_ctrl.ren1
connect issue_slots[7].in_uop.bits.fp_ctrl.wen, issue_slots[8].out_uop.fp_ctrl.wen
connect issue_slots[7].in_uop.bits.fp_ctrl.ldst, issue_slots[8].out_uop.fp_ctrl.ldst
connect issue_slots[7].in_uop.bits.op2_sel, issue_slots[8].out_uop.op2_sel
connect issue_slots[7].in_uop.bits.op1_sel, issue_slots[8].out_uop.op1_sel
connect issue_slots[7].in_uop.bits.imm_packed, issue_slots[8].out_uop.imm_packed
connect issue_slots[7].in_uop.bits.pimm, issue_slots[8].out_uop.pimm
connect issue_slots[7].in_uop.bits.imm_sel, issue_slots[8].out_uop.imm_sel
connect issue_slots[7].in_uop.bits.imm_rename, issue_slots[8].out_uop.imm_rename
connect issue_slots[7].in_uop.bits.taken, issue_slots[8].out_uop.taken
connect issue_slots[7].in_uop.bits.pc_lob, issue_slots[8].out_uop.pc_lob
connect issue_slots[7].in_uop.bits.edge_inst, issue_slots[8].out_uop.edge_inst
connect issue_slots[7].in_uop.bits.ftq_idx, issue_slots[8].out_uop.ftq_idx
connect issue_slots[7].in_uop.bits.is_mov, issue_slots[8].out_uop.is_mov
connect issue_slots[7].in_uop.bits.is_rocc, issue_slots[8].out_uop.is_rocc
connect issue_slots[7].in_uop.bits.is_sys_pc2epc, issue_slots[8].out_uop.is_sys_pc2epc
connect issue_slots[7].in_uop.bits.is_eret, issue_slots[8].out_uop.is_eret
connect issue_slots[7].in_uop.bits.is_amo, issue_slots[8].out_uop.is_amo
connect issue_slots[7].in_uop.bits.is_sfence, issue_slots[8].out_uop.is_sfence
connect issue_slots[7].in_uop.bits.is_fencei, issue_slots[8].out_uop.is_fencei
connect issue_slots[7].in_uop.bits.is_fence, issue_slots[8].out_uop.is_fence
connect issue_slots[7].in_uop.bits.is_sfb, issue_slots[8].out_uop.is_sfb
connect issue_slots[7].in_uop.bits.br_type, issue_slots[8].out_uop.br_type
connect issue_slots[7].in_uop.bits.br_tag, issue_slots[8].out_uop.br_tag
connect issue_slots[7].in_uop.bits.br_mask, issue_slots[8].out_uop.br_mask
connect issue_slots[7].in_uop.bits.dis_col_sel, issue_slots[8].out_uop.dis_col_sel
connect issue_slots[7].in_uop.bits.iw_p3_bypass_hint, issue_slots[8].out_uop.iw_p3_bypass_hint
connect issue_slots[7].in_uop.bits.iw_p2_bypass_hint, issue_slots[8].out_uop.iw_p2_bypass_hint
connect issue_slots[7].in_uop.bits.iw_p1_bypass_hint, issue_slots[8].out_uop.iw_p1_bypass_hint
connect issue_slots[7].in_uop.bits.iw_p2_speculative_child, issue_slots[8].out_uop.iw_p2_speculative_child
connect issue_slots[7].in_uop.bits.iw_p1_speculative_child, issue_slots[8].out_uop.iw_p1_speculative_child
connect issue_slots[7].in_uop.bits.iw_issued_partial_dgen, issue_slots[8].out_uop.iw_issued_partial_dgen
connect issue_slots[7].in_uop.bits.iw_issued_partial_agen, issue_slots[8].out_uop.iw_issued_partial_agen
connect issue_slots[7].in_uop.bits.iw_issued, issue_slots[8].out_uop.iw_issued
connect issue_slots[7].in_uop.bits.fu_code[0], issue_slots[8].out_uop.fu_code[0]
connect issue_slots[7].in_uop.bits.fu_code[1], issue_slots[8].out_uop.fu_code[1]
connect issue_slots[7].in_uop.bits.fu_code[2], issue_slots[8].out_uop.fu_code[2]
connect issue_slots[7].in_uop.bits.fu_code[3], issue_slots[8].out_uop.fu_code[3]
connect issue_slots[7].in_uop.bits.fu_code[4], issue_slots[8].out_uop.fu_code[4]
connect issue_slots[7].in_uop.bits.fu_code[5], issue_slots[8].out_uop.fu_code[5]
connect issue_slots[7].in_uop.bits.fu_code[6], issue_slots[8].out_uop.fu_code[6]
connect issue_slots[7].in_uop.bits.fu_code[7], issue_slots[8].out_uop.fu_code[7]
connect issue_slots[7].in_uop.bits.fu_code[8], issue_slots[8].out_uop.fu_code[8]
connect issue_slots[7].in_uop.bits.fu_code[9], issue_slots[8].out_uop.fu_code[9]
connect issue_slots[7].in_uop.bits.iq_type[0], issue_slots[8].out_uop.iq_type[0]
connect issue_slots[7].in_uop.bits.iq_type[1], issue_slots[8].out_uop.iq_type[1]
connect issue_slots[7].in_uop.bits.iq_type[2], issue_slots[8].out_uop.iq_type[2]
connect issue_slots[7].in_uop.bits.iq_type[3], issue_slots[8].out_uop.iq_type[3]
connect issue_slots[7].in_uop.bits.debug_pc, issue_slots[8].out_uop.debug_pc
connect issue_slots[7].in_uop.bits.is_rvc, issue_slots[8].out_uop.is_rvc
connect issue_slots[7].in_uop.bits.debug_inst, issue_slots[8].out_uop.debug_inst
connect issue_slots[7].in_uop.bits.inst, issue_slots[8].out_uop.inst
node _T_176 = eq(shamts_oh[8], UInt<1>(0h1))
when _T_176 :
connect issue_slots[7].in_uop.valid, issue_slots[8].will_be_valid
connect issue_slots[7].in_uop.bits.debug_tsrc, issue_slots[8].out_uop.debug_tsrc
connect issue_slots[7].in_uop.bits.debug_fsrc, issue_slots[8].out_uop.debug_fsrc
connect issue_slots[7].in_uop.bits.bp_xcpt_if, issue_slots[8].out_uop.bp_xcpt_if
connect issue_slots[7].in_uop.bits.bp_debug_if, issue_slots[8].out_uop.bp_debug_if
connect issue_slots[7].in_uop.bits.xcpt_ma_if, issue_slots[8].out_uop.xcpt_ma_if
connect issue_slots[7].in_uop.bits.xcpt_ae_if, issue_slots[8].out_uop.xcpt_ae_if
connect issue_slots[7].in_uop.bits.xcpt_pf_if, issue_slots[8].out_uop.xcpt_pf_if
connect issue_slots[7].in_uop.bits.fp_typ, issue_slots[8].out_uop.fp_typ
connect issue_slots[7].in_uop.bits.fp_rm, issue_slots[8].out_uop.fp_rm
connect issue_slots[7].in_uop.bits.fp_val, issue_slots[8].out_uop.fp_val
connect issue_slots[7].in_uop.bits.fcn_op, issue_slots[8].out_uop.fcn_op
connect issue_slots[7].in_uop.bits.fcn_dw, issue_slots[8].out_uop.fcn_dw
connect issue_slots[7].in_uop.bits.frs3_en, issue_slots[8].out_uop.frs3_en
connect issue_slots[7].in_uop.bits.lrs2_rtype, issue_slots[8].out_uop.lrs2_rtype
connect issue_slots[7].in_uop.bits.lrs1_rtype, issue_slots[8].out_uop.lrs1_rtype
connect issue_slots[7].in_uop.bits.dst_rtype, issue_slots[8].out_uop.dst_rtype
connect issue_slots[7].in_uop.bits.lrs3, issue_slots[8].out_uop.lrs3
connect issue_slots[7].in_uop.bits.lrs2, issue_slots[8].out_uop.lrs2
connect issue_slots[7].in_uop.bits.lrs1, issue_slots[8].out_uop.lrs1
connect issue_slots[7].in_uop.bits.ldst, issue_slots[8].out_uop.ldst
connect issue_slots[7].in_uop.bits.ldst_is_rs1, issue_slots[8].out_uop.ldst_is_rs1
connect issue_slots[7].in_uop.bits.csr_cmd, issue_slots[8].out_uop.csr_cmd
connect issue_slots[7].in_uop.bits.flush_on_commit, issue_slots[8].out_uop.flush_on_commit
connect issue_slots[7].in_uop.bits.is_unique, issue_slots[8].out_uop.is_unique
connect issue_slots[7].in_uop.bits.uses_stq, issue_slots[8].out_uop.uses_stq
connect issue_slots[7].in_uop.bits.uses_ldq, issue_slots[8].out_uop.uses_ldq
connect issue_slots[7].in_uop.bits.mem_signed, issue_slots[8].out_uop.mem_signed
connect issue_slots[7].in_uop.bits.mem_size, issue_slots[8].out_uop.mem_size
connect issue_slots[7].in_uop.bits.mem_cmd, issue_slots[8].out_uop.mem_cmd
connect issue_slots[7].in_uop.bits.exc_cause, issue_slots[8].out_uop.exc_cause
connect issue_slots[7].in_uop.bits.exception, issue_slots[8].out_uop.exception
connect issue_slots[7].in_uop.bits.stale_pdst, issue_slots[8].out_uop.stale_pdst
connect issue_slots[7].in_uop.bits.ppred_busy, issue_slots[8].out_uop.ppred_busy
connect issue_slots[7].in_uop.bits.prs3_busy, issue_slots[8].out_uop.prs3_busy
connect issue_slots[7].in_uop.bits.prs2_busy, issue_slots[8].out_uop.prs2_busy
connect issue_slots[7].in_uop.bits.prs1_busy, issue_slots[8].out_uop.prs1_busy
connect issue_slots[7].in_uop.bits.ppred, issue_slots[8].out_uop.ppred
connect issue_slots[7].in_uop.bits.prs3, issue_slots[8].out_uop.prs3
connect issue_slots[7].in_uop.bits.prs2, issue_slots[8].out_uop.prs2
connect issue_slots[7].in_uop.bits.prs1, issue_slots[8].out_uop.prs1
connect issue_slots[7].in_uop.bits.pdst, issue_slots[8].out_uop.pdst
connect issue_slots[7].in_uop.bits.rxq_idx, issue_slots[8].out_uop.rxq_idx
connect issue_slots[7].in_uop.bits.stq_idx, issue_slots[8].out_uop.stq_idx
connect issue_slots[7].in_uop.bits.ldq_idx, issue_slots[8].out_uop.ldq_idx
connect issue_slots[7].in_uop.bits.rob_idx, issue_slots[8].out_uop.rob_idx
connect issue_slots[7].in_uop.bits.fp_ctrl.vec, issue_slots[8].out_uop.fp_ctrl.vec
connect issue_slots[7].in_uop.bits.fp_ctrl.wflags, issue_slots[8].out_uop.fp_ctrl.wflags
connect issue_slots[7].in_uop.bits.fp_ctrl.sqrt, issue_slots[8].out_uop.fp_ctrl.sqrt
connect issue_slots[7].in_uop.bits.fp_ctrl.div, issue_slots[8].out_uop.fp_ctrl.div
connect issue_slots[7].in_uop.bits.fp_ctrl.fma, issue_slots[8].out_uop.fp_ctrl.fma
connect issue_slots[7].in_uop.bits.fp_ctrl.fastpipe, issue_slots[8].out_uop.fp_ctrl.fastpipe
connect issue_slots[7].in_uop.bits.fp_ctrl.toint, issue_slots[8].out_uop.fp_ctrl.toint
connect issue_slots[7].in_uop.bits.fp_ctrl.fromint, issue_slots[8].out_uop.fp_ctrl.fromint
connect issue_slots[7].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[8].out_uop.fp_ctrl.typeTagOut
connect issue_slots[7].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[8].out_uop.fp_ctrl.typeTagIn
connect issue_slots[7].in_uop.bits.fp_ctrl.swap23, issue_slots[8].out_uop.fp_ctrl.swap23
connect issue_slots[7].in_uop.bits.fp_ctrl.swap12, issue_slots[8].out_uop.fp_ctrl.swap12
connect issue_slots[7].in_uop.bits.fp_ctrl.ren3, issue_slots[8].out_uop.fp_ctrl.ren3
connect issue_slots[7].in_uop.bits.fp_ctrl.ren2, issue_slots[8].out_uop.fp_ctrl.ren2
connect issue_slots[7].in_uop.bits.fp_ctrl.ren1, issue_slots[8].out_uop.fp_ctrl.ren1
connect issue_slots[7].in_uop.bits.fp_ctrl.wen, issue_slots[8].out_uop.fp_ctrl.wen
connect issue_slots[7].in_uop.bits.fp_ctrl.ldst, issue_slots[8].out_uop.fp_ctrl.ldst
connect issue_slots[7].in_uop.bits.op2_sel, issue_slots[8].out_uop.op2_sel
connect issue_slots[7].in_uop.bits.op1_sel, issue_slots[8].out_uop.op1_sel
connect issue_slots[7].in_uop.bits.imm_packed, issue_slots[8].out_uop.imm_packed
connect issue_slots[7].in_uop.bits.pimm, issue_slots[8].out_uop.pimm
connect issue_slots[7].in_uop.bits.imm_sel, issue_slots[8].out_uop.imm_sel
connect issue_slots[7].in_uop.bits.imm_rename, issue_slots[8].out_uop.imm_rename
connect issue_slots[7].in_uop.bits.taken, issue_slots[8].out_uop.taken
connect issue_slots[7].in_uop.bits.pc_lob, issue_slots[8].out_uop.pc_lob
connect issue_slots[7].in_uop.bits.edge_inst, issue_slots[8].out_uop.edge_inst
connect issue_slots[7].in_uop.bits.ftq_idx, issue_slots[8].out_uop.ftq_idx
connect issue_slots[7].in_uop.bits.is_mov, issue_slots[8].out_uop.is_mov
connect issue_slots[7].in_uop.bits.is_rocc, issue_slots[8].out_uop.is_rocc
connect issue_slots[7].in_uop.bits.is_sys_pc2epc, issue_slots[8].out_uop.is_sys_pc2epc
connect issue_slots[7].in_uop.bits.is_eret, issue_slots[8].out_uop.is_eret
connect issue_slots[7].in_uop.bits.is_amo, issue_slots[8].out_uop.is_amo
connect issue_slots[7].in_uop.bits.is_sfence, issue_slots[8].out_uop.is_sfence
connect issue_slots[7].in_uop.bits.is_fencei, issue_slots[8].out_uop.is_fencei
connect issue_slots[7].in_uop.bits.is_fence, issue_slots[8].out_uop.is_fence
connect issue_slots[7].in_uop.bits.is_sfb, issue_slots[8].out_uop.is_sfb
connect issue_slots[7].in_uop.bits.br_type, issue_slots[8].out_uop.br_type
connect issue_slots[7].in_uop.bits.br_tag, issue_slots[8].out_uop.br_tag
connect issue_slots[7].in_uop.bits.br_mask, issue_slots[8].out_uop.br_mask
connect issue_slots[7].in_uop.bits.dis_col_sel, issue_slots[8].out_uop.dis_col_sel
connect issue_slots[7].in_uop.bits.iw_p3_bypass_hint, issue_slots[8].out_uop.iw_p3_bypass_hint
connect issue_slots[7].in_uop.bits.iw_p2_bypass_hint, issue_slots[8].out_uop.iw_p2_bypass_hint
connect issue_slots[7].in_uop.bits.iw_p1_bypass_hint, issue_slots[8].out_uop.iw_p1_bypass_hint
connect issue_slots[7].in_uop.bits.iw_p2_speculative_child, issue_slots[8].out_uop.iw_p2_speculative_child
connect issue_slots[7].in_uop.bits.iw_p1_speculative_child, issue_slots[8].out_uop.iw_p1_speculative_child
connect issue_slots[7].in_uop.bits.iw_issued_partial_dgen, issue_slots[8].out_uop.iw_issued_partial_dgen
connect issue_slots[7].in_uop.bits.iw_issued_partial_agen, issue_slots[8].out_uop.iw_issued_partial_agen
connect issue_slots[7].in_uop.bits.iw_issued, issue_slots[8].out_uop.iw_issued
connect issue_slots[7].in_uop.bits.fu_code[0], issue_slots[8].out_uop.fu_code[0]
connect issue_slots[7].in_uop.bits.fu_code[1], issue_slots[8].out_uop.fu_code[1]
connect issue_slots[7].in_uop.bits.fu_code[2], issue_slots[8].out_uop.fu_code[2]
connect issue_slots[7].in_uop.bits.fu_code[3], issue_slots[8].out_uop.fu_code[3]
connect issue_slots[7].in_uop.bits.fu_code[4], issue_slots[8].out_uop.fu_code[4]
connect issue_slots[7].in_uop.bits.fu_code[5], issue_slots[8].out_uop.fu_code[5]
connect issue_slots[7].in_uop.bits.fu_code[6], issue_slots[8].out_uop.fu_code[6]
connect issue_slots[7].in_uop.bits.fu_code[7], issue_slots[8].out_uop.fu_code[7]
connect issue_slots[7].in_uop.bits.fu_code[8], issue_slots[8].out_uop.fu_code[8]
connect issue_slots[7].in_uop.bits.fu_code[9], issue_slots[8].out_uop.fu_code[9]
connect issue_slots[7].in_uop.bits.iq_type[0], issue_slots[8].out_uop.iq_type[0]
connect issue_slots[7].in_uop.bits.iq_type[1], issue_slots[8].out_uop.iq_type[1]
connect issue_slots[7].in_uop.bits.iq_type[2], issue_slots[8].out_uop.iq_type[2]
connect issue_slots[7].in_uop.bits.iq_type[3], issue_slots[8].out_uop.iq_type[3]
connect issue_slots[7].in_uop.bits.debug_pc, issue_slots[8].out_uop.debug_pc
connect issue_slots[7].in_uop.bits.is_rvc, issue_slots[8].out_uop.is_rvc
connect issue_slots[7].in_uop.bits.debug_inst, issue_slots[8].out_uop.debug_inst
connect issue_slots[7].in_uop.bits.inst, issue_slots[8].out_uop.inst
node _T_177 = eq(shamts_oh[9], UInt<2>(0h2))
when _T_177 :
connect issue_slots[7].in_uop.valid, issue_slots[9].will_be_valid
connect issue_slots[7].in_uop.bits.debug_tsrc, issue_slots[9].out_uop.debug_tsrc
connect issue_slots[7].in_uop.bits.debug_fsrc, issue_slots[9].out_uop.debug_fsrc
connect issue_slots[7].in_uop.bits.bp_xcpt_if, issue_slots[9].out_uop.bp_xcpt_if
connect issue_slots[7].in_uop.bits.bp_debug_if, issue_slots[9].out_uop.bp_debug_if
connect issue_slots[7].in_uop.bits.xcpt_ma_if, issue_slots[9].out_uop.xcpt_ma_if
connect issue_slots[7].in_uop.bits.xcpt_ae_if, issue_slots[9].out_uop.xcpt_ae_if
connect issue_slots[7].in_uop.bits.xcpt_pf_if, issue_slots[9].out_uop.xcpt_pf_if
connect issue_slots[7].in_uop.bits.fp_typ, issue_slots[9].out_uop.fp_typ
connect issue_slots[7].in_uop.bits.fp_rm, issue_slots[9].out_uop.fp_rm
connect issue_slots[7].in_uop.bits.fp_val, issue_slots[9].out_uop.fp_val
connect issue_slots[7].in_uop.bits.fcn_op, issue_slots[9].out_uop.fcn_op
connect issue_slots[7].in_uop.bits.fcn_dw, issue_slots[9].out_uop.fcn_dw
connect issue_slots[7].in_uop.bits.frs3_en, issue_slots[9].out_uop.frs3_en
connect issue_slots[7].in_uop.bits.lrs2_rtype, issue_slots[9].out_uop.lrs2_rtype
connect issue_slots[7].in_uop.bits.lrs1_rtype, issue_slots[9].out_uop.lrs1_rtype
connect issue_slots[7].in_uop.bits.dst_rtype, issue_slots[9].out_uop.dst_rtype
connect issue_slots[7].in_uop.bits.lrs3, issue_slots[9].out_uop.lrs3
connect issue_slots[7].in_uop.bits.lrs2, issue_slots[9].out_uop.lrs2
connect issue_slots[7].in_uop.bits.lrs1, issue_slots[9].out_uop.lrs1
connect issue_slots[7].in_uop.bits.ldst, issue_slots[9].out_uop.ldst
connect issue_slots[7].in_uop.bits.ldst_is_rs1, issue_slots[9].out_uop.ldst_is_rs1
connect issue_slots[7].in_uop.bits.csr_cmd, issue_slots[9].out_uop.csr_cmd
connect issue_slots[7].in_uop.bits.flush_on_commit, issue_slots[9].out_uop.flush_on_commit
connect issue_slots[7].in_uop.bits.is_unique, issue_slots[9].out_uop.is_unique
connect issue_slots[7].in_uop.bits.uses_stq, issue_slots[9].out_uop.uses_stq
connect issue_slots[7].in_uop.bits.uses_ldq, issue_slots[9].out_uop.uses_ldq
connect issue_slots[7].in_uop.bits.mem_signed, issue_slots[9].out_uop.mem_signed
connect issue_slots[7].in_uop.bits.mem_size, issue_slots[9].out_uop.mem_size
connect issue_slots[7].in_uop.bits.mem_cmd, issue_slots[9].out_uop.mem_cmd
connect issue_slots[7].in_uop.bits.exc_cause, issue_slots[9].out_uop.exc_cause
connect issue_slots[7].in_uop.bits.exception, issue_slots[9].out_uop.exception
connect issue_slots[7].in_uop.bits.stale_pdst, issue_slots[9].out_uop.stale_pdst
connect issue_slots[7].in_uop.bits.ppred_busy, issue_slots[9].out_uop.ppred_busy
connect issue_slots[7].in_uop.bits.prs3_busy, issue_slots[9].out_uop.prs3_busy
connect issue_slots[7].in_uop.bits.prs2_busy, issue_slots[9].out_uop.prs2_busy
connect issue_slots[7].in_uop.bits.prs1_busy, issue_slots[9].out_uop.prs1_busy
connect issue_slots[7].in_uop.bits.ppred, issue_slots[9].out_uop.ppred
connect issue_slots[7].in_uop.bits.prs3, issue_slots[9].out_uop.prs3
connect issue_slots[7].in_uop.bits.prs2, issue_slots[9].out_uop.prs2
connect issue_slots[7].in_uop.bits.prs1, issue_slots[9].out_uop.prs1
connect issue_slots[7].in_uop.bits.pdst, issue_slots[9].out_uop.pdst
connect issue_slots[7].in_uop.bits.rxq_idx, issue_slots[9].out_uop.rxq_idx
connect issue_slots[7].in_uop.bits.stq_idx, issue_slots[9].out_uop.stq_idx
connect issue_slots[7].in_uop.bits.ldq_idx, issue_slots[9].out_uop.ldq_idx
connect issue_slots[7].in_uop.bits.rob_idx, issue_slots[9].out_uop.rob_idx
connect issue_slots[7].in_uop.bits.fp_ctrl.vec, issue_slots[9].out_uop.fp_ctrl.vec
connect issue_slots[7].in_uop.bits.fp_ctrl.wflags, issue_slots[9].out_uop.fp_ctrl.wflags
connect issue_slots[7].in_uop.bits.fp_ctrl.sqrt, issue_slots[9].out_uop.fp_ctrl.sqrt
connect issue_slots[7].in_uop.bits.fp_ctrl.div, issue_slots[9].out_uop.fp_ctrl.div
connect issue_slots[7].in_uop.bits.fp_ctrl.fma, issue_slots[9].out_uop.fp_ctrl.fma
connect issue_slots[7].in_uop.bits.fp_ctrl.fastpipe, issue_slots[9].out_uop.fp_ctrl.fastpipe
connect issue_slots[7].in_uop.bits.fp_ctrl.toint, issue_slots[9].out_uop.fp_ctrl.toint
connect issue_slots[7].in_uop.bits.fp_ctrl.fromint, issue_slots[9].out_uop.fp_ctrl.fromint
connect issue_slots[7].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[9].out_uop.fp_ctrl.typeTagOut
connect issue_slots[7].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[9].out_uop.fp_ctrl.typeTagIn
connect issue_slots[7].in_uop.bits.fp_ctrl.swap23, issue_slots[9].out_uop.fp_ctrl.swap23
connect issue_slots[7].in_uop.bits.fp_ctrl.swap12, issue_slots[9].out_uop.fp_ctrl.swap12
connect issue_slots[7].in_uop.bits.fp_ctrl.ren3, issue_slots[9].out_uop.fp_ctrl.ren3
connect issue_slots[7].in_uop.bits.fp_ctrl.ren2, issue_slots[9].out_uop.fp_ctrl.ren2
connect issue_slots[7].in_uop.bits.fp_ctrl.ren1, issue_slots[9].out_uop.fp_ctrl.ren1
connect issue_slots[7].in_uop.bits.fp_ctrl.wen, issue_slots[9].out_uop.fp_ctrl.wen
connect issue_slots[7].in_uop.bits.fp_ctrl.ldst, issue_slots[9].out_uop.fp_ctrl.ldst
connect issue_slots[7].in_uop.bits.op2_sel, issue_slots[9].out_uop.op2_sel
connect issue_slots[7].in_uop.bits.op1_sel, issue_slots[9].out_uop.op1_sel
connect issue_slots[7].in_uop.bits.imm_packed, issue_slots[9].out_uop.imm_packed
connect issue_slots[7].in_uop.bits.pimm, issue_slots[9].out_uop.pimm
connect issue_slots[7].in_uop.bits.imm_sel, issue_slots[9].out_uop.imm_sel
connect issue_slots[7].in_uop.bits.imm_rename, issue_slots[9].out_uop.imm_rename
connect issue_slots[7].in_uop.bits.taken, issue_slots[9].out_uop.taken
connect issue_slots[7].in_uop.bits.pc_lob, issue_slots[9].out_uop.pc_lob
connect issue_slots[7].in_uop.bits.edge_inst, issue_slots[9].out_uop.edge_inst
connect issue_slots[7].in_uop.bits.ftq_idx, issue_slots[9].out_uop.ftq_idx
connect issue_slots[7].in_uop.bits.is_mov, issue_slots[9].out_uop.is_mov
connect issue_slots[7].in_uop.bits.is_rocc, issue_slots[9].out_uop.is_rocc
connect issue_slots[7].in_uop.bits.is_sys_pc2epc, issue_slots[9].out_uop.is_sys_pc2epc
connect issue_slots[7].in_uop.bits.is_eret, issue_slots[9].out_uop.is_eret
connect issue_slots[7].in_uop.bits.is_amo, issue_slots[9].out_uop.is_amo
connect issue_slots[7].in_uop.bits.is_sfence, issue_slots[9].out_uop.is_sfence
connect issue_slots[7].in_uop.bits.is_fencei, issue_slots[9].out_uop.is_fencei
connect issue_slots[7].in_uop.bits.is_fence, issue_slots[9].out_uop.is_fence
connect issue_slots[7].in_uop.bits.is_sfb, issue_slots[9].out_uop.is_sfb
connect issue_slots[7].in_uop.bits.br_type, issue_slots[9].out_uop.br_type
connect issue_slots[7].in_uop.bits.br_tag, issue_slots[9].out_uop.br_tag
connect issue_slots[7].in_uop.bits.br_mask, issue_slots[9].out_uop.br_mask
connect issue_slots[7].in_uop.bits.dis_col_sel, issue_slots[9].out_uop.dis_col_sel
connect issue_slots[7].in_uop.bits.iw_p3_bypass_hint, issue_slots[9].out_uop.iw_p3_bypass_hint
connect issue_slots[7].in_uop.bits.iw_p2_bypass_hint, issue_slots[9].out_uop.iw_p2_bypass_hint
connect issue_slots[7].in_uop.bits.iw_p1_bypass_hint, issue_slots[9].out_uop.iw_p1_bypass_hint
connect issue_slots[7].in_uop.bits.iw_p2_speculative_child, issue_slots[9].out_uop.iw_p2_speculative_child
connect issue_slots[7].in_uop.bits.iw_p1_speculative_child, issue_slots[9].out_uop.iw_p1_speculative_child
connect issue_slots[7].in_uop.bits.iw_issued_partial_dgen, issue_slots[9].out_uop.iw_issued_partial_dgen
connect issue_slots[7].in_uop.bits.iw_issued_partial_agen, issue_slots[9].out_uop.iw_issued_partial_agen
connect issue_slots[7].in_uop.bits.iw_issued, issue_slots[9].out_uop.iw_issued
connect issue_slots[7].in_uop.bits.fu_code[0], issue_slots[9].out_uop.fu_code[0]
connect issue_slots[7].in_uop.bits.fu_code[1], issue_slots[9].out_uop.fu_code[1]
connect issue_slots[7].in_uop.bits.fu_code[2], issue_slots[9].out_uop.fu_code[2]
connect issue_slots[7].in_uop.bits.fu_code[3], issue_slots[9].out_uop.fu_code[3]
connect issue_slots[7].in_uop.bits.fu_code[4], issue_slots[9].out_uop.fu_code[4]
connect issue_slots[7].in_uop.bits.fu_code[5], issue_slots[9].out_uop.fu_code[5]
connect issue_slots[7].in_uop.bits.fu_code[6], issue_slots[9].out_uop.fu_code[6]
connect issue_slots[7].in_uop.bits.fu_code[7], issue_slots[9].out_uop.fu_code[7]
connect issue_slots[7].in_uop.bits.fu_code[8], issue_slots[9].out_uop.fu_code[8]
connect issue_slots[7].in_uop.bits.fu_code[9], issue_slots[9].out_uop.fu_code[9]
connect issue_slots[7].in_uop.bits.iq_type[0], issue_slots[9].out_uop.iq_type[0]
connect issue_slots[7].in_uop.bits.iq_type[1], issue_slots[9].out_uop.iq_type[1]
connect issue_slots[7].in_uop.bits.iq_type[2], issue_slots[9].out_uop.iq_type[2]
connect issue_slots[7].in_uop.bits.iq_type[3], issue_slots[9].out_uop.iq_type[3]
connect issue_slots[7].in_uop.bits.debug_pc, issue_slots[9].out_uop.debug_pc
connect issue_slots[7].in_uop.bits.is_rvc, issue_slots[9].out_uop.is_rvc
connect issue_slots[7].in_uop.bits.debug_inst, issue_slots[9].out_uop.debug_inst
connect issue_slots[7].in_uop.bits.inst, issue_slots[9].out_uop.inst
node _issue_slots_7_clear_T = neq(shamts_oh[7], UInt<1>(0h0))
connect issue_slots[7].clear, _issue_slots_7_clear_T
connect issue_slots[8].in_uop.valid, UInt<1>(0h0)
connect issue_slots[8].in_uop.bits.debug_tsrc, issue_slots[9].out_uop.debug_tsrc
connect issue_slots[8].in_uop.bits.debug_fsrc, issue_slots[9].out_uop.debug_fsrc
connect issue_slots[8].in_uop.bits.bp_xcpt_if, issue_slots[9].out_uop.bp_xcpt_if
connect issue_slots[8].in_uop.bits.bp_debug_if, issue_slots[9].out_uop.bp_debug_if
connect issue_slots[8].in_uop.bits.xcpt_ma_if, issue_slots[9].out_uop.xcpt_ma_if
connect issue_slots[8].in_uop.bits.xcpt_ae_if, issue_slots[9].out_uop.xcpt_ae_if
connect issue_slots[8].in_uop.bits.xcpt_pf_if, issue_slots[9].out_uop.xcpt_pf_if
connect issue_slots[8].in_uop.bits.fp_typ, issue_slots[9].out_uop.fp_typ
connect issue_slots[8].in_uop.bits.fp_rm, issue_slots[9].out_uop.fp_rm
connect issue_slots[8].in_uop.bits.fp_val, issue_slots[9].out_uop.fp_val
connect issue_slots[8].in_uop.bits.fcn_op, issue_slots[9].out_uop.fcn_op
connect issue_slots[8].in_uop.bits.fcn_dw, issue_slots[9].out_uop.fcn_dw
connect issue_slots[8].in_uop.bits.frs3_en, issue_slots[9].out_uop.frs3_en
connect issue_slots[8].in_uop.bits.lrs2_rtype, issue_slots[9].out_uop.lrs2_rtype
connect issue_slots[8].in_uop.bits.lrs1_rtype, issue_slots[9].out_uop.lrs1_rtype
connect issue_slots[8].in_uop.bits.dst_rtype, issue_slots[9].out_uop.dst_rtype
connect issue_slots[8].in_uop.bits.lrs3, issue_slots[9].out_uop.lrs3
connect issue_slots[8].in_uop.bits.lrs2, issue_slots[9].out_uop.lrs2
connect issue_slots[8].in_uop.bits.lrs1, issue_slots[9].out_uop.lrs1
connect issue_slots[8].in_uop.bits.ldst, issue_slots[9].out_uop.ldst
connect issue_slots[8].in_uop.bits.ldst_is_rs1, issue_slots[9].out_uop.ldst_is_rs1
connect issue_slots[8].in_uop.bits.csr_cmd, issue_slots[9].out_uop.csr_cmd
connect issue_slots[8].in_uop.bits.flush_on_commit, issue_slots[9].out_uop.flush_on_commit
connect issue_slots[8].in_uop.bits.is_unique, issue_slots[9].out_uop.is_unique
connect issue_slots[8].in_uop.bits.uses_stq, issue_slots[9].out_uop.uses_stq
connect issue_slots[8].in_uop.bits.uses_ldq, issue_slots[9].out_uop.uses_ldq
connect issue_slots[8].in_uop.bits.mem_signed, issue_slots[9].out_uop.mem_signed
connect issue_slots[8].in_uop.bits.mem_size, issue_slots[9].out_uop.mem_size
connect issue_slots[8].in_uop.bits.mem_cmd, issue_slots[9].out_uop.mem_cmd
connect issue_slots[8].in_uop.bits.exc_cause, issue_slots[9].out_uop.exc_cause
connect issue_slots[8].in_uop.bits.exception, issue_slots[9].out_uop.exception
connect issue_slots[8].in_uop.bits.stale_pdst, issue_slots[9].out_uop.stale_pdst
connect issue_slots[8].in_uop.bits.ppred_busy, issue_slots[9].out_uop.ppred_busy
connect issue_slots[8].in_uop.bits.prs3_busy, issue_slots[9].out_uop.prs3_busy
connect issue_slots[8].in_uop.bits.prs2_busy, issue_slots[9].out_uop.prs2_busy
connect issue_slots[8].in_uop.bits.prs1_busy, issue_slots[9].out_uop.prs1_busy
connect issue_slots[8].in_uop.bits.ppred, issue_slots[9].out_uop.ppred
connect issue_slots[8].in_uop.bits.prs3, issue_slots[9].out_uop.prs3
connect issue_slots[8].in_uop.bits.prs2, issue_slots[9].out_uop.prs2
connect issue_slots[8].in_uop.bits.prs1, issue_slots[9].out_uop.prs1
connect issue_slots[8].in_uop.bits.pdst, issue_slots[9].out_uop.pdst
connect issue_slots[8].in_uop.bits.rxq_idx, issue_slots[9].out_uop.rxq_idx
connect issue_slots[8].in_uop.bits.stq_idx, issue_slots[9].out_uop.stq_idx
connect issue_slots[8].in_uop.bits.ldq_idx, issue_slots[9].out_uop.ldq_idx
connect issue_slots[8].in_uop.bits.rob_idx, issue_slots[9].out_uop.rob_idx
connect issue_slots[8].in_uop.bits.fp_ctrl.vec, issue_slots[9].out_uop.fp_ctrl.vec
connect issue_slots[8].in_uop.bits.fp_ctrl.wflags, issue_slots[9].out_uop.fp_ctrl.wflags
connect issue_slots[8].in_uop.bits.fp_ctrl.sqrt, issue_slots[9].out_uop.fp_ctrl.sqrt
connect issue_slots[8].in_uop.bits.fp_ctrl.div, issue_slots[9].out_uop.fp_ctrl.div
connect issue_slots[8].in_uop.bits.fp_ctrl.fma, issue_slots[9].out_uop.fp_ctrl.fma
connect issue_slots[8].in_uop.bits.fp_ctrl.fastpipe, issue_slots[9].out_uop.fp_ctrl.fastpipe
connect issue_slots[8].in_uop.bits.fp_ctrl.toint, issue_slots[9].out_uop.fp_ctrl.toint
connect issue_slots[8].in_uop.bits.fp_ctrl.fromint, issue_slots[9].out_uop.fp_ctrl.fromint
connect issue_slots[8].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[9].out_uop.fp_ctrl.typeTagOut
connect issue_slots[8].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[9].out_uop.fp_ctrl.typeTagIn
connect issue_slots[8].in_uop.bits.fp_ctrl.swap23, issue_slots[9].out_uop.fp_ctrl.swap23
connect issue_slots[8].in_uop.bits.fp_ctrl.swap12, issue_slots[9].out_uop.fp_ctrl.swap12
connect issue_slots[8].in_uop.bits.fp_ctrl.ren3, issue_slots[9].out_uop.fp_ctrl.ren3
connect issue_slots[8].in_uop.bits.fp_ctrl.ren2, issue_slots[9].out_uop.fp_ctrl.ren2
connect issue_slots[8].in_uop.bits.fp_ctrl.ren1, issue_slots[9].out_uop.fp_ctrl.ren1
connect issue_slots[8].in_uop.bits.fp_ctrl.wen, issue_slots[9].out_uop.fp_ctrl.wen
connect issue_slots[8].in_uop.bits.fp_ctrl.ldst, issue_slots[9].out_uop.fp_ctrl.ldst
connect issue_slots[8].in_uop.bits.op2_sel, issue_slots[9].out_uop.op2_sel
connect issue_slots[8].in_uop.bits.op1_sel, issue_slots[9].out_uop.op1_sel
connect issue_slots[8].in_uop.bits.imm_packed, issue_slots[9].out_uop.imm_packed
connect issue_slots[8].in_uop.bits.pimm, issue_slots[9].out_uop.pimm
connect issue_slots[8].in_uop.bits.imm_sel, issue_slots[9].out_uop.imm_sel
connect issue_slots[8].in_uop.bits.imm_rename, issue_slots[9].out_uop.imm_rename
connect issue_slots[8].in_uop.bits.taken, issue_slots[9].out_uop.taken
connect issue_slots[8].in_uop.bits.pc_lob, issue_slots[9].out_uop.pc_lob
connect issue_slots[8].in_uop.bits.edge_inst, issue_slots[9].out_uop.edge_inst
connect issue_slots[8].in_uop.bits.ftq_idx, issue_slots[9].out_uop.ftq_idx
connect issue_slots[8].in_uop.bits.is_mov, issue_slots[9].out_uop.is_mov
connect issue_slots[8].in_uop.bits.is_rocc, issue_slots[9].out_uop.is_rocc
connect issue_slots[8].in_uop.bits.is_sys_pc2epc, issue_slots[9].out_uop.is_sys_pc2epc
connect issue_slots[8].in_uop.bits.is_eret, issue_slots[9].out_uop.is_eret
connect issue_slots[8].in_uop.bits.is_amo, issue_slots[9].out_uop.is_amo
connect issue_slots[8].in_uop.bits.is_sfence, issue_slots[9].out_uop.is_sfence
connect issue_slots[8].in_uop.bits.is_fencei, issue_slots[9].out_uop.is_fencei
connect issue_slots[8].in_uop.bits.is_fence, issue_slots[9].out_uop.is_fence
connect issue_slots[8].in_uop.bits.is_sfb, issue_slots[9].out_uop.is_sfb
connect issue_slots[8].in_uop.bits.br_type, issue_slots[9].out_uop.br_type
connect issue_slots[8].in_uop.bits.br_tag, issue_slots[9].out_uop.br_tag
connect issue_slots[8].in_uop.bits.br_mask, issue_slots[9].out_uop.br_mask
connect issue_slots[8].in_uop.bits.dis_col_sel, issue_slots[9].out_uop.dis_col_sel
connect issue_slots[8].in_uop.bits.iw_p3_bypass_hint, issue_slots[9].out_uop.iw_p3_bypass_hint
connect issue_slots[8].in_uop.bits.iw_p2_bypass_hint, issue_slots[9].out_uop.iw_p2_bypass_hint
connect issue_slots[8].in_uop.bits.iw_p1_bypass_hint, issue_slots[9].out_uop.iw_p1_bypass_hint
connect issue_slots[8].in_uop.bits.iw_p2_speculative_child, issue_slots[9].out_uop.iw_p2_speculative_child
connect issue_slots[8].in_uop.bits.iw_p1_speculative_child, issue_slots[9].out_uop.iw_p1_speculative_child
connect issue_slots[8].in_uop.bits.iw_issued_partial_dgen, issue_slots[9].out_uop.iw_issued_partial_dgen
connect issue_slots[8].in_uop.bits.iw_issued_partial_agen, issue_slots[9].out_uop.iw_issued_partial_agen
connect issue_slots[8].in_uop.bits.iw_issued, issue_slots[9].out_uop.iw_issued
connect issue_slots[8].in_uop.bits.fu_code[0], issue_slots[9].out_uop.fu_code[0]
connect issue_slots[8].in_uop.bits.fu_code[1], issue_slots[9].out_uop.fu_code[1]
connect issue_slots[8].in_uop.bits.fu_code[2], issue_slots[9].out_uop.fu_code[2]
connect issue_slots[8].in_uop.bits.fu_code[3], issue_slots[9].out_uop.fu_code[3]
connect issue_slots[8].in_uop.bits.fu_code[4], issue_slots[9].out_uop.fu_code[4]
connect issue_slots[8].in_uop.bits.fu_code[5], issue_slots[9].out_uop.fu_code[5]
connect issue_slots[8].in_uop.bits.fu_code[6], issue_slots[9].out_uop.fu_code[6]
connect issue_slots[8].in_uop.bits.fu_code[7], issue_slots[9].out_uop.fu_code[7]
connect issue_slots[8].in_uop.bits.fu_code[8], issue_slots[9].out_uop.fu_code[8]
connect issue_slots[8].in_uop.bits.fu_code[9], issue_slots[9].out_uop.fu_code[9]
connect issue_slots[8].in_uop.bits.iq_type[0], issue_slots[9].out_uop.iq_type[0]
connect issue_slots[8].in_uop.bits.iq_type[1], issue_slots[9].out_uop.iq_type[1]
connect issue_slots[8].in_uop.bits.iq_type[2], issue_slots[9].out_uop.iq_type[2]
connect issue_slots[8].in_uop.bits.iq_type[3], issue_slots[9].out_uop.iq_type[3]
connect issue_slots[8].in_uop.bits.debug_pc, issue_slots[9].out_uop.debug_pc
connect issue_slots[8].in_uop.bits.is_rvc, issue_slots[9].out_uop.is_rvc
connect issue_slots[8].in_uop.bits.debug_inst, issue_slots[9].out_uop.debug_inst
connect issue_slots[8].in_uop.bits.inst, issue_slots[9].out_uop.inst
node _T_178 = eq(shamts_oh[9], UInt<1>(0h1))
when _T_178 :
connect issue_slots[8].in_uop.valid, issue_slots[9].will_be_valid
connect issue_slots[8].in_uop.bits.debug_tsrc, issue_slots[9].out_uop.debug_tsrc
connect issue_slots[8].in_uop.bits.debug_fsrc, issue_slots[9].out_uop.debug_fsrc
connect issue_slots[8].in_uop.bits.bp_xcpt_if, issue_slots[9].out_uop.bp_xcpt_if
connect issue_slots[8].in_uop.bits.bp_debug_if, issue_slots[9].out_uop.bp_debug_if
connect issue_slots[8].in_uop.bits.xcpt_ma_if, issue_slots[9].out_uop.xcpt_ma_if
connect issue_slots[8].in_uop.bits.xcpt_ae_if, issue_slots[9].out_uop.xcpt_ae_if
connect issue_slots[8].in_uop.bits.xcpt_pf_if, issue_slots[9].out_uop.xcpt_pf_if
connect issue_slots[8].in_uop.bits.fp_typ, issue_slots[9].out_uop.fp_typ
connect issue_slots[8].in_uop.bits.fp_rm, issue_slots[9].out_uop.fp_rm
connect issue_slots[8].in_uop.bits.fp_val, issue_slots[9].out_uop.fp_val
connect issue_slots[8].in_uop.bits.fcn_op, issue_slots[9].out_uop.fcn_op
connect issue_slots[8].in_uop.bits.fcn_dw, issue_slots[9].out_uop.fcn_dw
connect issue_slots[8].in_uop.bits.frs3_en, issue_slots[9].out_uop.frs3_en
connect issue_slots[8].in_uop.bits.lrs2_rtype, issue_slots[9].out_uop.lrs2_rtype
connect issue_slots[8].in_uop.bits.lrs1_rtype, issue_slots[9].out_uop.lrs1_rtype
connect issue_slots[8].in_uop.bits.dst_rtype, issue_slots[9].out_uop.dst_rtype
connect issue_slots[8].in_uop.bits.lrs3, issue_slots[9].out_uop.lrs3
connect issue_slots[8].in_uop.bits.lrs2, issue_slots[9].out_uop.lrs2
connect issue_slots[8].in_uop.bits.lrs1, issue_slots[9].out_uop.lrs1
connect issue_slots[8].in_uop.bits.ldst, issue_slots[9].out_uop.ldst
connect issue_slots[8].in_uop.bits.ldst_is_rs1, issue_slots[9].out_uop.ldst_is_rs1
connect issue_slots[8].in_uop.bits.csr_cmd, issue_slots[9].out_uop.csr_cmd
connect issue_slots[8].in_uop.bits.flush_on_commit, issue_slots[9].out_uop.flush_on_commit
connect issue_slots[8].in_uop.bits.is_unique, issue_slots[9].out_uop.is_unique
connect issue_slots[8].in_uop.bits.uses_stq, issue_slots[9].out_uop.uses_stq
connect issue_slots[8].in_uop.bits.uses_ldq, issue_slots[9].out_uop.uses_ldq
connect issue_slots[8].in_uop.bits.mem_signed, issue_slots[9].out_uop.mem_signed
connect issue_slots[8].in_uop.bits.mem_size, issue_slots[9].out_uop.mem_size
connect issue_slots[8].in_uop.bits.mem_cmd, issue_slots[9].out_uop.mem_cmd
connect issue_slots[8].in_uop.bits.exc_cause, issue_slots[9].out_uop.exc_cause
connect issue_slots[8].in_uop.bits.exception, issue_slots[9].out_uop.exception
connect issue_slots[8].in_uop.bits.stale_pdst, issue_slots[9].out_uop.stale_pdst
connect issue_slots[8].in_uop.bits.ppred_busy, issue_slots[9].out_uop.ppred_busy
connect issue_slots[8].in_uop.bits.prs3_busy, issue_slots[9].out_uop.prs3_busy
connect issue_slots[8].in_uop.bits.prs2_busy, issue_slots[9].out_uop.prs2_busy
connect issue_slots[8].in_uop.bits.prs1_busy, issue_slots[9].out_uop.prs1_busy
connect issue_slots[8].in_uop.bits.ppred, issue_slots[9].out_uop.ppred
connect issue_slots[8].in_uop.bits.prs3, issue_slots[9].out_uop.prs3
connect issue_slots[8].in_uop.bits.prs2, issue_slots[9].out_uop.prs2
connect issue_slots[8].in_uop.bits.prs1, issue_slots[9].out_uop.prs1
connect issue_slots[8].in_uop.bits.pdst, issue_slots[9].out_uop.pdst
connect issue_slots[8].in_uop.bits.rxq_idx, issue_slots[9].out_uop.rxq_idx
connect issue_slots[8].in_uop.bits.stq_idx, issue_slots[9].out_uop.stq_idx
connect issue_slots[8].in_uop.bits.ldq_idx, issue_slots[9].out_uop.ldq_idx
connect issue_slots[8].in_uop.bits.rob_idx, issue_slots[9].out_uop.rob_idx
connect issue_slots[8].in_uop.bits.fp_ctrl.vec, issue_slots[9].out_uop.fp_ctrl.vec
connect issue_slots[8].in_uop.bits.fp_ctrl.wflags, issue_slots[9].out_uop.fp_ctrl.wflags
connect issue_slots[8].in_uop.bits.fp_ctrl.sqrt, issue_slots[9].out_uop.fp_ctrl.sqrt
connect issue_slots[8].in_uop.bits.fp_ctrl.div, issue_slots[9].out_uop.fp_ctrl.div
connect issue_slots[8].in_uop.bits.fp_ctrl.fma, issue_slots[9].out_uop.fp_ctrl.fma
connect issue_slots[8].in_uop.bits.fp_ctrl.fastpipe, issue_slots[9].out_uop.fp_ctrl.fastpipe
connect issue_slots[8].in_uop.bits.fp_ctrl.toint, issue_slots[9].out_uop.fp_ctrl.toint
connect issue_slots[8].in_uop.bits.fp_ctrl.fromint, issue_slots[9].out_uop.fp_ctrl.fromint
connect issue_slots[8].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[9].out_uop.fp_ctrl.typeTagOut
connect issue_slots[8].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[9].out_uop.fp_ctrl.typeTagIn
connect issue_slots[8].in_uop.bits.fp_ctrl.swap23, issue_slots[9].out_uop.fp_ctrl.swap23
connect issue_slots[8].in_uop.bits.fp_ctrl.swap12, issue_slots[9].out_uop.fp_ctrl.swap12
connect issue_slots[8].in_uop.bits.fp_ctrl.ren3, issue_slots[9].out_uop.fp_ctrl.ren3
connect issue_slots[8].in_uop.bits.fp_ctrl.ren2, issue_slots[9].out_uop.fp_ctrl.ren2
connect issue_slots[8].in_uop.bits.fp_ctrl.ren1, issue_slots[9].out_uop.fp_ctrl.ren1
connect issue_slots[8].in_uop.bits.fp_ctrl.wen, issue_slots[9].out_uop.fp_ctrl.wen
connect issue_slots[8].in_uop.bits.fp_ctrl.ldst, issue_slots[9].out_uop.fp_ctrl.ldst
connect issue_slots[8].in_uop.bits.op2_sel, issue_slots[9].out_uop.op2_sel
connect issue_slots[8].in_uop.bits.op1_sel, issue_slots[9].out_uop.op1_sel
connect issue_slots[8].in_uop.bits.imm_packed, issue_slots[9].out_uop.imm_packed
connect issue_slots[8].in_uop.bits.pimm, issue_slots[9].out_uop.pimm
connect issue_slots[8].in_uop.bits.imm_sel, issue_slots[9].out_uop.imm_sel
connect issue_slots[8].in_uop.bits.imm_rename, issue_slots[9].out_uop.imm_rename
connect issue_slots[8].in_uop.bits.taken, issue_slots[9].out_uop.taken
connect issue_slots[8].in_uop.bits.pc_lob, issue_slots[9].out_uop.pc_lob
connect issue_slots[8].in_uop.bits.edge_inst, issue_slots[9].out_uop.edge_inst
connect issue_slots[8].in_uop.bits.ftq_idx, issue_slots[9].out_uop.ftq_idx
connect issue_slots[8].in_uop.bits.is_mov, issue_slots[9].out_uop.is_mov
connect issue_slots[8].in_uop.bits.is_rocc, issue_slots[9].out_uop.is_rocc
connect issue_slots[8].in_uop.bits.is_sys_pc2epc, issue_slots[9].out_uop.is_sys_pc2epc
connect issue_slots[8].in_uop.bits.is_eret, issue_slots[9].out_uop.is_eret
connect issue_slots[8].in_uop.bits.is_amo, issue_slots[9].out_uop.is_amo
connect issue_slots[8].in_uop.bits.is_sfence, issue_slots[9].out_uop.is_sfence
connect issue_slots[8].in_uop.bits.is_fencei, issue_slots[9].out_uop.is_fencei
connect issue_slots[8].in_uop.bits.is_fence, issue_slots[9].out_uop.is_fence
connect issue_slots[8].in_uop.bits.is_sfb, issue_slots[9].out_uop.is_sfb
connect issue_slots[8].in_uop.bits.br_type, issue_slots[9].out_uop.br_type
connect issue_slots[8].in_uop.bits.br_tag, issue_slots[9].out_uop.br_tag
connect issue_slots[8].in_uop.bits.br_mask, issue_slots[9].out_uop.br_mask
connect issue_slots[8].in_uop.bits.dis_col_sel, issue_slots[9].out_uop.dis_col_sel
connect issue_slots[8].in_uop.bits.iw_p3_bypass_hint, issue_slots[9].out_uop.iw_p3_bypass_hint
connect issue_slots[8].in_uop.bits.iw_p2_bypass_hint, issue_slots[9].out_uop.iw_p2_bypass_hint
connect issue_slots[8].in_uop.bits.iw_p1_bypass_hint, issue_slots[9].out_uop.iw_p1_bypass_hint
connect issue_slots[8].in_uop.bits.iw_p2_speculative_child, issue_slots[9].out_uop.iw_p2_speculative_child
connect issue_slots[8].in_uop.bits.iw_p1_speculative_child, issue_slots[9].out_uop.iw_p1_speculative_child
connect issue_slots[8].in_uop.bits.iw_issued_partial_dgen, issue_slots[9].out_uop.iw_issued_partial_dgen
connect issue_slots[8].in_uop.bits.iw_issued_partial_agen, issue_slots[9].out_uop.iw_issued_partial_agen
connect issue_slots[8].in_uop.bits.iw_issued, issue_slots[9].out_uop.iw_issued
connect issue_slots[8].in_uop.bits.fu_code[0], issue_slots[9].out_uop.fu_code[0]
connect issue_slots[8].in_uop.bits.fu_code[1], issue_slots[9].out_uop.fu_code[1]
connect issue_slots[8].in_uop.bits.fu_code[2], issue_slots[9].out_uop.fu_code[2]
connect issue_slots[8].in_uop.bits.fu_code[3], issue_slots[9].out_uop.fu_code[3]
connect issue_slots[8].in_uop.bits.fu_code[4], issue_slots[9].out_uop.fu_code[4]
connect issue_slots[8].in_uop.bits.fu_code[5], issue_slots[9].out_uop.fu_code[5]
connect issue_slots[8].in_uop.bits.fu_code[6], issue_slots[9].out_uop.fu_code[6]
connect issue_slots[8].in_uop.bits.fu_code[7], issue_slots[9].out_uop.fu_code[7]
connect issue_slots[8].in_uop.bits.fu_code[8], issue_slots[9].out_uop.fu_code[8]
connect issue_slots[8].in_uop.bits.fu_code[9], issue_slots[9].out_uop.fu_code[9]
connect issue_slots[8].in_uop.bits.iq_type[0], issue_slots[9].out_uop.iq_type[0]
connect issue_slots[8].in_uop.bits.iq_type[1], issue_slots[9].out_uop.iq_type[1]
connect issue_slots[8].in_uop.bits.iq_type[2], issue_slots[9].out_uop.iq_type[2]
connect issue_slots[8].in_uop.bits.iq_type[3], issue_slots[9].out_uop.iq_type[3]
connect issue_slots[8].in_uop.bits.debug_pc, issue_slots[9].out_uop.debug_pc
connect issue_slots[8].in_uop.bits.is_rvc, issue_slots[9].out_uop.is_rvc
connect issue_slots[8].in_uop.bits.debug_inst, issue_slots[9].out_uop.debug_inst
connect issue_slots[8].in_uop.bits.inst, issue_slots[9].out_uop.inst
node _T_179 = eq(shamts_oh[10], UInt<2>(0h2))
when _T_179 :
connect issue_slots[8].in_uop.valid, issue_slots[10].will_be_valid
connect issue_slots[8].in_uop.bits.debug_tsrc, issue_slots[10].out_uop.debug_tsrc
connect issue_slots[8].in_uop.bits.debug_fsrc, issue_slots[10].out_uop.debug_fsrc
connect issue_slots[8].in_uop.bits.bp_xcpt_if, issue_slots[10].out_uop.bp_xcpt_if
connect issue_slots[8].in_uop.bits.bp_debug_if, issue_slots[10].out_uop.bp_debug_if
connect issue_slots[8].in_uop.bits.xcpt_ma_if, issue_slots[10].out_uop.xcpt_ma_if
connect issue_slots[8].in_uop.bits.xcpt_ae_if, issue_slots[10].out_uop.xcpt_ae_if
connect issue_slots[8].in_uop.bits.xcpt_pf_if, issue_slots[10].out_uop.xcpt_pf_if
connect issue_slots[8].in_uop.bits.fp_typ, issue_slots[10].out_uop.fp_typ
connect issue_slots[8].in_uop.bits.fp_rm, issue_slots[10].out_uop.fp_rm
connect issue_slots[8].in_uop.bits.fp_val, issue_slots[10].out_uop.fp_val
connect issue_slots[8].in_uop.bits.fcn_op, issue_slots[10].out_uop.fcn_op
connect issue_slots[8].in_uop.bits.fcn_dw, issue_slots[10].out_uop.fcn_dw
connect issue_slots[8].in_uop.bits.frs3_en, issue_slots[10].out_uop.frs3_en
connect issue_slots[8].in_uop.bits.lrs2_rtype, issue_slots[10].out_uop.lrs2_rtype
connect issue_slots[8].in_uop.bits.lrs1_rtype, issue_slots[10].out_uop.lrs1_rtype
connect issue_slots[8].in_uop.bits.dst_rtype, issue_slots[10].out_uop.dst_rtype
connect issue_slots[8].in_uop.bits.lrs3, issue_slots[10].out_uop.lrs3
connect issue_slots[8].in_uop.bits.lrs2, issue_slots[10].out_uop.lrs2
connect issue_slots[8].in_uop.bits.lrs1, issue_slots[10].out_uop.lrs1
connect issue_slots[8].in_uop.bits.ldst, issue_slots[10].out_uop.ldst
connect issue_slots[8].in_uop.bits.ldst_is_rs1, issue_slots[10].out_uop.ldst_is_rs1
connect issue_slots[8].in_uop.bits.csr_cmd, issue_slots[10].out_uop.csr_cmd
connect issue_slots[8].in_uop.bits.flush_on_commit, issue_slots[10].out_uop.flush_on_commit
connect issue_slots[8].in_uop.bits.is_unique, issue_slots[10].out_uop.is_unique
connect issue_slots[8].in_uop.bits.uses_stq, issue_slots[10].out_uop.uses_stq
connect issue_slots[8].in_uop.bits.uses_ldq, issue_slots[10].out_uop.uses_ldq
connect issue_slots[8].in_uop.bits.mem_signed, issue_slots[10].out_uop.mem_signed
connect issue_slots[8].in_uop.bits.mem_size, issue_slots[10].out_uop.mem_size
connect issue_slots[8].in_uop.bits.mem_cmd, issue_slots[10].out_uop.mem_cmd
connect issue_slots[8].in_uop.bits.exc_cause, issue_slots[10].out_uop.exc_cause
connect issue_slots[8].in_uop.bits.exception, issue_slots[10].out_uop.exception
connect issue_slots[8].in_uop.bits.stale_pdst, issue_slots[10].out_uop.stale_pdst
connect issue_slots[8].in_uop.bits.ppred_busy, issue_slots[10].out_uop.ppred_busy
connect issue_slots[8].in_uop.bits.prs3_busy, issue_slots[10].out_uop.prs3_busy
connect issue_slots[8].in_uop.bits.prs2_busy, issue_slots[10].out_uop.prs2_busy
connect issue_slots[8].in_uop.bits.prs1_busy, issue_slots[10].out_uop.prs1_busy
connect issue_slots[8].in_uop.bits.ppred, issue_slots[10].out_uop.ppred
connect issue_slots[8].in_uop.bits.prs3, issue_slots[10].out_uop.prs3
connect issue_slots[8].in_uop.bits.prs2, issue_slots[10].out_uop.prs2
connect issue_slots[8].in_uop.bits.prs1, issue_slots[10].out_uop.prs1
connect issue_slots[8].in_uop.bits.pdst, issue_slots[10].out_uop.pdst
connect issue_slots[8].in_uop.bits.rxq_idx, issue_slots[10].out_uop.rxq_idx
connect issue_slots[8].in_uop.bits.stq_idx, issue_slots[10].out_uop.stq_idx
connect issue_slots[8].in_uop.bits.ldq_idx, issue_slots[10].out_uop.ldq_idx
connect issue_slots[8].in_uop.bits.rob_idx, issue_slots[10].out_uop.rob_idx
connect issue_slots[8].in_uop.bits.fp_ctrl.vec, issue_slots[10].out_uop.fp_ctrl.vec
connect issue_slots[8].in_uop.bits.fp_ctrl.wflags, issue_slots[10].out_uop.fp_ctrl.wflags
connect issue_slots[8].in_uop.bits.fp_ctrl.sqrt, issue_slots[10].out_uop.fp_ctrl.sqrt
connect issue_slots[8].in_uop.bits.fp_ctrl.div, issue_slots[10].out_uop.fp_ctrl.div
connect issue_slots[8].in_uop.bits.fp_ctrl.fma, issue_slots[10].out_uop.fp_ctrl.fma
connect issue_slots[8].in_uop.bits.fp_ctrl.fastpipe, issue_slots[10].out_uop.fp_ctrl.fastpipe
connect issue_slots[8].in_uop.bits.fp_ctrl.toint, issue_slots[10].out_uop.fp_ctrl.toint
connect issue_slots[8].in_uop.bits.fp_ctrl.fromint, issue_slots[10].out_uop.fp_ctrl.fromint
connect issue_slots[8].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[10].out_uop.fp_ctrl.typeTagOut
connect issue_slots[8].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[10].out_uop.fp_ctrl.typeTagIn
connect issue_slots[8].in_uop.bits.fp_ctrl.swap23, issue_slots[10].out_uop.fp_ctrl.swap23
connect issue_slots[8].in_uop.bits.fp_ctrl.swap12, issue_slots[10].out_uop.fp_ctrl.swap12
connect issue_slots[8].in_uop.bits.fp_ctrl.ren3, issue_slots[10].out_uop.fp_ctrl.ren3
connect issue_slots[8].in_uop.bits.fp_ctrl.ren2, issue_slots[10].out_uop.fp_ctrl.ren2
connect issue_slots[8].in_uop.bits.fp_ctrl.ren1, issue_slots[10].out_uop.fp_ctrl.ren1
connect issue_slots[8].in_uop.bits.fp_ctrl.wen, issue_slots[10].out_uop.fp_ctrl.wen
connect issue_slots[8].in_uop.bits.fp_ctrl.ldst, issue_slots[10].out_uop.fp_ctrl.ldst
connect issue_slots[8].in_uop.bits.op2_sel, issue_slots[10].out_uop.op2_sel
connect issue_slots[8].in_uop.bits.op1_sel, issue_slots[10].out_uop.op1_sel
connect issue_slots[8].in_uop.bits.imm_packed, issue_slots[10].out_uop.imm_packed
connect issue_slots[8].in_uop.bits.pimm, issue_slots[10].out_uop.pimm
connect issue_slots[8].in_uop.bits.imm_sel, issue_slots[10].out_uop.imm_sel
connect issue_slots[8].in_uop.bits.imm_rename, issue_slots[10].out_uop.imm_rename
connect issue_slots[8].in_uop.bits.taken, issue_slots[10].out_uop.taken
connect issue_slots[8].in_uop.bits.pc_lob, issue_slots[10].out_uop.pc_lob
connect issue_slots[8].in_uop.bits.edge_inst, issue_slots[10].out_uop.edge_inst
connect issue_slots[8].in_uop.bits.ftq_idx, issue_slots[10].out_uop.ftq_idx
connect issue_slots[8].in_uop.bits.is_mov, issue_slots[10].out_uop.is_mov
connect issue_slots[8].in_uop.bits.is_rocc, issue_slots[10].out_uop.is_rocc
connect issue_slots[8].in_uop.bits.is_sys_pc2epc, issue_slots[10].out_uop.is_sys_pc2epc
connect issue_slots[8].in_uop.bits.is_eret, issue_slots[10].out_uop.is_eret
connect issue_slots[8].in_uop.bits.is_amo, issue_slots[10].out_uop.is_amo
connect issue_slots[8].in_uop.bits.is_sfence, issue_slots[10].out_uop.is_sfence
connect issue_slots[8].in_uop.bits.is_fencei, issue_slots[10].out_uop.is_fencei
connect issue_slots[8].in_uop.bits.is_fence, issue_slots[10].out_uop.is_fence
connect issue_slots[8].in_uop.bits.is_sfb, issue_slots[10].out_uop.is_sfb
connect issue_slots[8].in_uop.bits.br_type, issue_slots[10].out_uop.br_type
connect issue_slots[8].in_uop.bits.br_tag, issue_slots[10].out_uop.br_tag
connect issue_slots[8].in_uop.bits.br_mask, issue_slots[10].out_uop.br_mask
connect issue_slots[8].in_uop.bits.dis_col_sel, issue_slots[10].out_uop.dis_col_sel
connect issue_slots[8].in_uop.bits.iw_p3_bypass_hint, issue_slots[10].out_uop.iw_p3_bypass_hint
connect issue_slots[8].in_uop.bits.iw_p2_bypass_hint, issue_slots[10].out_uop.iw_p2_bypass_hint
connect issue_slots[8].in_uop.bits.iw_p1_bypass_hint, issue_slots[10].out_uop.iw_p1_bypass_hint
connect issue_slots[8].in_uop.bits.iw_p2_speculative_child, issue_slots[10].out_uop.iw_p2_speculative_child
connect issue_slots[8].in_uop.bits.iw_p1_speculative_child, issue_slots[10].out_uop.iw_p1_speculative_child
connect issue_slots[8].in_uop.bits.iw_issued_partial_dgen, issue_slots[10].out_uop.iw_issued_partial_dgen
connect issue_slots[8].in_uop.bits.iw_issued_partial_agen, issue_slots[10].out_uop.iw_issued_partial_agen
connect issue_slots[8].in_uop.bits.iw_issued, issue_slots[10].out_uop.iw_issued
connect issue_slots[8].in_uop.bits.fu_code[0], issue_slots[10].out_uop.fu_code[0]
connect issue_slots[8].in_uop.bits.fu_code[1], issue_slots[10].out_uop.fu_code[1]
connect issue_slots[8].in_uop.bits.fu_code[2], issue_slots[10].out_uop.fu_code[2]
connect issue_slots[8].in_uop.bits.fu_code[3], issue_slots[10].out_uop.fu_code[3]
connect issue_slots[8].in_uop.bits.fu_code[4], issue_slots[10].out_uop.fu_code[4]
connect issue_slots[8].in_uop.bits.fu_code[5], issue_slots[10].out_uop.fu_code[5]
connect issue_slots[8].in_uop.bits.fu_code[6], issue_slots[10].out_uop.fu_code[6]
connect issue_slots[8].in_uop.bits.fu_code[7], issue_slots[10].out_uop.fu_code[7]
connect issue_slots[8].in_uop.bits.fu_code[8], issue_slots[10].out_uop.fu_code[8]
connect issue_slots[8].in_uop.bits.fu_code[9], issue_slots[10].out_uop.fu_code[9]
connect issue_slots[8].in_uop.bits.iq_type[0], issue_slots[10].out_uop.iq_type[0]
connect issue_slots[8].in_uop.bits.iq_type[1], issue_slots[10].out_uop.iq_type[1]
connect issue_slots[8].in_uop.bits.iq_type[2], issue_slots[10].out_uop.iq_type[2]
connect issue_slots[8].in_uop.bits.iq_type[3], issue_slots[10].out_uop.iq_type[3]
connect issue_slots[8].in_uop.bits.debug_pc, issue_slots[10].out_uop.debug_pc
connect issue_slots[8].in_uop.bits.is_rvc, issue_slots[10].out_uop.is_rvc
connect issue_slots[8].in_uop.bits.debug_inst, issue_slots[10].out_uop.debug_inst
connect issue_slots[8].in_uop.bits.inst, issue_slots[10].out_uop.inst
node _issue_slots_8_clear_T = neq(shamts_oh[8], UInt<1>(0h0))
connect issue_slots[8].clear, _issue_slots_8_clear_T
connect issue_slots[9].in_uop.valid, UInt<1>(0h0)
connect issue_slots[9].in_uop.bits.debug_tsrc, issue_slots[10].out_uop.debug_tsrc
connect issue_slots[9].in_uop.bits.debug_fsrc, issue_slots[10].out_uop.debug_fsrc
connect issue_slots[9].in_uop.bits.bp_xcpt_if, issue_slots[10].out_uop.bp_xcpt_if
connect issue_slots[9].in_uop.bits.bp_debug_if, issue_slots[10].out_uop.bp_debug_if
connect issue_slots[9].in_uop.bits.xcpt_ma_if, issue_slots[10].out_uop.xcpt_ma_if
connect issue_slots[9].in_uop.bits.xcpt_ae_if, issue_slots[10].out_uop.xcpt_ae_if
connect issue_slots[9].in_uop.bits.xcpt_pf_if, issue_slots[10].out_uop.xcpt_pf_if
connect issue_slots[9].in_uop.bits.fp_typ, issue_slots[10].out_uop.fp_typ
connect issue_slots[9].in_uop.bits.fp_rm, issue_slots[10].out_uop.fp_rm
connect issue_slots[9].in_uop.bits.fp_val, issue_slots[10].out_uop.fp_val
connect issue_slots[9].in_uop.bits.fcn_op, issue_slots[10].out_uop.fcn_op
connect issue_slots[9].in_uop.bits.fcn_dw, issue_slots[10].out_uop.fcn_dw
connect issue_slots[9].in_uop.bits.frs3_en, issue_slots[10].out_uop.frs3_en
connect issue_slots[9].in_uop.bits.lrs2_rtype, issue_slots[10].out_uop.lrs2_rtype
connect issue_slots[9].in_uop.bits.lrs1_rtype, issue_slots[10].out_uop.lrs1_rtype
connect issue_slots[9].in_uop.bits.dst_rtype, issue_slots[10].out_uop.dst_rtype
connect issue_slots[9].in_uop.bits.lrs3, issue_slots[10].out_uop.lrs3
connect issue_slots[9].in_uop.bits.lrs2, issue_slots[10].out_uop.lrs2
connect issue_slots[9].in_uop.bits.lrs1, issue_slots[10].out_uop.lrs1
connect issue_slots[9].in_uop.bits.ldst, issue_slots[10].out_uop.ldst
connect issue_slots[9].in_uop.bits.ldst_is_rs1, issue_slots[10].out_uop.ldst_is_rs1
connect issue_slots[9].in_uop.bits.csr_cmd, issue_slots[10].out_uop.csr_cmd
connect issue_slots[9].in_uop.bits.flush_on_commit, issue_slots[10].out_uop.flush_on_commit
connect issue_slots[9].in_uop.bits.is_unique, issue_slots[10].out_uop.is_unique
connect issue_slots[9].in_uop.bits.uses_stq, issue_slots[10].out_uop.uses_stq
connect issue_slots[9].in_uop.bits.uses_ldq, issue_slots[10].out_uop.uses_ldq
connect issue_slots[9].in_uop.bits.mem_signed, issue_slots[10].out_uop.mem_signed
connect issue_slots[9].in_uop.bits.mem_size, issue_slots[10].out_uop.mem_size
connect issue_slots[9].in_uop.bits.mem_cmd, issue_slots[10].out_uop.mem_cmd
connect issue_slots[9].in_uop.bits.exc_cause, issue_slots[10].out_uop.exc_cause
connect issue_slots[9].in_uop.bits.exception, issue_slots[10].out_uop.exception
connect issue_slots[9].in_uop.bits.stale_pdst, issue_slots[10].out_uop.stale_pdst
connect issue_slots[9].in_uop.bits.ppred_busy, issue_slots[10].out_uop.ppred_busy
connect issue_slots[9].in_uop.bits.prs3_busy, issue_slots[10].out_uop.prs3_busy
connect issue_slots[9].in_uop.bits.prs2_busy, issue_slots[10].out_uop.prs2_busy
connect issue_slots[9].in_uop.bits.prs1_busy, issue_slots[10].out_uop.prs1_busy
connect issue_slots[9].in_uop.bits.ppred, issue_slots[10].out_uop.ppred
connect issue_slots[9].in_uop.bits.prs3, issue_slots[10].out_uop.prs3
connect issue_slots[9].in_uop.bits.prs2, issue_slots[10].out_uop.prs2
connect issue_slots[9].in_uop.bits.prs1, issue_slots[10].out_uop.prs1
connect issue_slots[9].in_uop.bits.pdst, issue_slots[10].out_uop.pdst
connect issue_slots[9].in_uop.bits.rxq_idx, issue_slots[10].out_uop.rxq_idx
connect issue_slots[9].in_uop.bits.stq_idx, issue_slots[10].out_uop.stq_idx
connect issue_slots[9].in_uop.bits.ldq_idx, issue_slots[10].out_uop.ldq_idx
connect issue_slots[9].in_uop.bits.rob_idx, issue_slots[10].out_uop.rob_idx
connect issue_slots[9].in_uop.bits.fp_ctrl.vec, issue_slots[10].out_uop.fp_ctrl.vec
connect issue_slots[9].in_uop.bits.fp_ctrl.wflags, issue_slots[10].out_uop.fp_ctrl.wflags
connect issue_slots[9].in_uop.bits.fp_ctrl.sqrt, issue_slots[10].out_uop.fp_ctrl.sqrt
connect issue_slots[9].in_uop.bits.fp_ctrl.div, issue_slots[10].out_uop.fp_ctrl.div
connect issue_slots[9].in_uop.bits.fp_ctrl.fma, issue_slots[10].out_uop.fp_ctrl.fma
connect issue_slots[9].in_uop.bits.fp_ctrl.fastpipe, issue_slots[10].out_uop.fp_ctrl.fastpipe
connect issue_slots[9].in_uop.bits.fp_ctrl.toint, issue_slots[10].out_uop.fp_ctrl.toint
connect issue_slots[9].in_uop.bits.fp_ctrl.fromint, issue_slots[10].out_uop.fp_ctrl.fromint
connect issue_slots[9].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[10].out_uop.fp_ctrl.typeTagOut
connect issue_slots[9].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[10].out_uop.fp_ctrl.typeTagIn
connect issue_slots[9].in_uop.bits.fp_ctrl.swap23, issue_slots[10].out_uop.fp_ctrl.swap23
connect issue_slots[9].in_uop.bits.fp_ctrl.swap12, issue_slots[10].out_uop.fp_ctrl.swap12
connect issue_slots[9].in_uop.bits.fp_ctrl.ren3, issue_slots[10].out_uop.fp_ctrl.ren3
connect issue_slots[9].in_uop.bits.fp_ctrl.ren2, issue_slots[10].out_uop.fp_ctrl.ren2
connect issue_slots[9].in_uop.bits.fp_ctrl.ren1, issue_slots[10].out_uop.fp_ctrl.ren1
connect issue_slots[9].in_uop.bits.fp_ctrl.wen, issue_slots[10].out_uop.fp_ctrl.wen
connect issue_slots[9].in_uop.bits.fp_ctrl.ldst, issue_slots[10].out_uop.fp_ctrl.ldst
connect issue_slots[9].in_uop.bits.op2_sel, issue_slots[10].out_uop.op2_sel
connect issue_slots[9].in_uop.bits.op1_sel, issue_slots[10].out_uop.op1_sel
connect issue_slots[9].in_uop.bits.imm_packed, issue_slots[10].out_uop.imm_packed
connect issue_slots[9].in_uop.bits.pimm, issue_slots[10].out_uop.pimm
connect issue_slots[9].in_uop.bits.imm_sel, issue_slots[10].out_uop.imm_sel
connect issue_slots[9].in_uop.bits.imm_rename, issue_slots[10].out_uop.imm_rename
connect issue_slots[9].in_uop.bits.taken, issue_slots[10].out_uop.taken
connect issue_slots[9].in_uop.bits.pc_lob, issue_slots[10].out_uop.pc_lob
connect issue_slots[9].in_uop.bits.edge_inst, issue_slots[10].out_uop.edge_inst
connect issue_slots[9].in_uop.bits.ftq_idx, issue_slots[10].out_uop.ftq_idx
connect issue_slots[9].in_uop.bits.is_mov, issue_slots[10].out_uop.is_mov
connect issue_slots[9].in_uop.bits.is_rocc, issue_slots[10].out_uop.is_rocc
connect issue_slots[9].in_uop.bits.is_sys_pc2epc, issue_slots[10].out_uop.is_sys_pc2epc
connect issue_slots[9].in_uop.bits.is_eret, issue_slots[10].out_uop.is_eret
connect issue_slots[9].in_uop.bits.is_amo, issue_slots[10].out_uop.is_amo
connect issue_slots[9].in_uop.bits.is_sfence, issue_slots[10].out_uop.is_sfence
connect issue_slots[9].in_uop.bits.is_fencei, issue_slots[10].out_uop.is_fencei
connect issue_slots[9].in_uop.bits.is_fence, issue_slots[10].out_uop.is_fence
connect issue_slots[9].in_uop.bits.is_sfb, issue_slots[10].out_uop.is_sfb
connect issue_slots[9].in_uop.bits.br_type, issue_slots[10].out_uop.br_type
connect issue_slots[9].in_uop.bits.br_tag, issue_slots[10].out_uop.br_tag
connect issue_slots[9].in_uop.bits.br_mask, issue_slots[10].out_uop.br_mask
connect issue_slots[9].in_uop.bits.dis_col_sel, issue_slots[10].out_uop.dis_col_sel
connect issue_slots[9].in_uop.bits.iw_p3_bypass_hint, issue_slots[10].out_uop.iw_p3_bypass_hint
connect issue_slots[9].in_uop.bits.iw_p2_bypass_hint, issue_slots[10].out_uop.iw_p2_bypass_hint
connect issue_slots[9].in_uop.bits.iw_p1_bypass_hint, issue_slots[10].out_uop.iw_p1_bypass_hint
connect issue_slots[9].in_uop.bits.iw_p2_speculative_child, issue_slots[10].out_uop.iw_p2_speculative_child
connect issue_slots[9].in_uop.bits.iw_p1_speculative_child, issue_slots[10].out_uop.iw_p1_speculative_child
connect issue_slots[9].in_uop.bits.iw_issued_partial_dgen, issue_slots[10].out_uop.iw_issued_partial_dgen
connect issue_slots[9].in_uop.bits.iw_issued_partial_agen, issue_slots[10].out_uop.iw_issued_partial_agen
connect issue_slots[9].in_uop.bits.iw_issued, issue_slots[10].out_uop.iw_issued
connect issue_slots[9].in_uop.bits.fu_code[0], issue_slots[10].out_uop.fu_code[0]
connect issue_slots[9].in_uop.bits.fu_code[1], issue_slots[10].out_uop.fu_code[1]
connect issue_slots[9].in_uop.bits.fu_code[2], issue_slots[10].out_uop.fu_code[2]
connect issue_slots[9].in_uop.bits.fu_code[3], issue_slots[10].out_uop.fu_code[3]
connect issue_slots[9].in_uop.bits.fu_code[4], issue_slots[10].out_uop.fu_code[4]
connect issue_slots[9].in_uop.bits.fu_code[5], issue_slots[10].out_uop.fu_code[5]
connect issue_slots[9].in_uop.bits.fu_code[6], issue_slots[10].out_uop.fu_code[6]
connect issue_slots[9].in_uop.bits.fu_code[7], issue_slots[10].out_uop.fu_code[7]
connect issue_slots[9].in_uop.bits.fu_code[8], issue_slots[10].out_uop.fu_code[8]
connect issue_slots[9].in_uop.bits.fu_code[9], issue_slots[10].out_uop.fu_code[9]
connect issue_slots[9].in_uop.bits.iq_type[0], issue_slots[10].out_uop.iq_type[0]
connect issue_slots[9].in_uop.bits.iq_type[1], issue_slots[10].out_uop.iq_type[1]
connect issue_slots[9].in_uop.bits.iq_type[2], issue_slots[10].out_uop.iq_type[2]
connect issue_slots[9].in_uop.bits.iq_type[3], issue_slots[10].out_uop.iq_type[3]
connect issue_slots[9].in_uop.bits.debug_pc, issue_slots[10].out_uop.debug_pc
connect issue_slots[9].in_uop.bits.is_rvc, issue_slots[10].out_uop.is_rvc
connect issue_slots[9].in_uop.bits.debug_inst, issue_slots[10].out_uop.debug_inst
connect issue_slots[9].in_uop.bits.inst, issue_slots[10].out_uop.inst
node _T_180 = eq(shamts_oh[10], UInt<1>(0h1))
when _T_180 :
connect issue_slots[9].in_uop.valid, issue_slots[10].will_be_valid
connect issue_slots[9].in_uop.bits.debug_tsrc, issue_slots[10].out_uop.debug_tsrc
connect issue_slots[9].in_uop.bits.debug_fsrc, issue_slots[10].out_uop.debug_fsrc
connect issue_slots[9].in_uop.bits.bp_xcpt_if, issue_slots[10].out_uop.bp_xcpt_if
connect issue_slots[9].in_uop.bits.bp_debug_if, issue_slots[10].out_uop.bp_debug_if
connect issue_slots[9].in_uop.bits.xcpt_ma_if, issue_slots[10].out_uop.xcpt_ma_if
connect issue_slots[9].in_uop.bits.xcpt_ae_if, issue_slots[10].out_uop.xcpt_ae_if
connect issue_slots[9].in_uop.bits.xcpt_pf_if, issue_slots[10].out_uop.xcpt_pf_if
connect issue_slots[9].in_uop.bits.fp_typ, issue_slots[10].out_uop.fp_typ
connect issue_slots[9].in_uop.bits.fp_rm, issue_slots[10].out_uop.fp_rm
connect issue_slots[9].in_uop.bits.fp_val, issue_slots[10].out_uop.fp_val
connect issue_slots[9].in_uop.bits.fcn_op, issue_slots[10].out_uop.fcn_op
connect issue_slots[9].in_uop.bits.fcn_dw, issue_slots[10].out_uop.fcn_dw
connect issue_slots[9].in_uop.bits.frs3_en, issue_slots[10].out_uop.frs3_en
connect issue_slots[9].in_uop.bits.lrs2_rtype, issue_slots[10].out_uop.lrs2_rtype
connect issue_slots[9].in_uop.bits.lrs1_rtype, issue_slots[10].out_uop.lrs1_rtype
connect issue_slots[9].in_uop.bits.dst_rtype, issue_slots[10].out_uop.dst_rtype
connect issue_slots[9].in_uop.bits.lrs3, issue_slots[10].out_uop.lrs3
connect issue_slots[9].in_uop.bits.lrs2, issue_slots[10].out_uop.lrs2
connect issue_slots[9].in_uop.bits.lrs1, issue_slots[10].out_uop.lrs1
connect issue_slots[9].in_uop.bits.ldst, issue_slots[10].out_uop.ldst
connect issue_slots[9].in_uop.bits.ldst_is_rs1, issue_slots[10].out_uop.ldst_is_rs1
connect issue_slots[9].in_uop.bits.csr_cmd, issue_slots[10].out_uop.csr_cmd
connect issue_slots[9].in_uop.bits.flush_on_commit, issue_slots[10].out_uop.flush_on_commit
connect issue_slots[9].in_uop.bits.is_unique, issue_slots[10].out_uop.is_unique
connect issue_slots[9].in_uop.bits.uses_stq, issue_slots[10].out_uop.uses_stq
connect issue_slots[9].in_uop.bits.uses_ldq, issue_slots[10].out_uop.uses_ldq
connect issue_slots[9].in_uop.bits.mem_signed, issue_slots[10].out_uop.mem_signed
connect issue_slots[9].in_uop.bits.mem_size, issue_slots[10].out_uop.mem_size
connect issue_slots[9].in_uop.bits.mem_cmd, issue_slots[10].out_uop.mem_cmd
connect issue_slots[9].in_uop.bits.exc_cause, issue_slots[10].out_uop.exc_cause
connect issue_slots[9].in_uop.bits.exception, issue_slots[10].out_uop.exception
connect issue_slots[9].in_uop.bits.stale_pdst, issue_slots[10].out_uop.stale_pdst
connect issue_slots[9].in_uop.bits.ppred_busy, issue_slots[10].out_uop.ppred_busy
connect issue_slots[9].in_uop.bits.prs3_busy, issue_slots[10].out_uop.prs3_busy
connect issue_slots[9].in_uop.bits.prs2_busy, issue_slots[10].out_uop.prs2_busy
connect issue_slots[9].in_uop.bits.prs1_busy, issue_slots[10].out_uop.prs1_busy
connect issue_slots[9].in_uop.bits.ppred, issue_slots[10].out_uop.ppred
connect issue_slots[9].in_uop.bits.prs3, issue_slots[10].out_uop.prs3
connect issue_slots[9].in_uop.bits.prs2, issue_slots[10].out_uop.prs2
connect issue_slots[9].in_uop.bits.prs1, issue_slots[10].out_uop.prs1
connect issue_slots[9].in_uop.bits.pdst, issue_slots[10].out_uop.pdst
connect issue_slots[9].in_uop.bits.rxq_idx, issue_slots[10].out_uop.rxq_idx
connect issue_slots[9].in_uop.bits.stq_idx, issue_slots[10].out_uop.stq_idx
connect issue_slots[9].in_uop.bits.ldq_idx, issue_slots[10].out_uop.ldq_idx
connect issue_slots[9].in_uop.bits.rob_idx, issue_slots[10].out_uop.rob_idx
connect issue_slots[9].in_uop.bits.fp_ctrl.vec, issue_slots[10].out_uop.fp_ctrl.vec
connect issue_slots[9].in_uop.bits.fp_ctrl.wflags, issue_slots[10].out_uop.fp_ctrl.wflags
connect issue_slots[9].in_uop.bits.fp_ctrl.sqrt, issue_slots[10].out_uop.fp_ctrl.sqrt
connect issue_slots[9].in_uop.bits.fp_ctrl.div, issue_slots[10].out_uop.fp_ctrl.div
connect issue_slots[9].in_uop.bits.fp_ctrl.fma, issue_slots[10].out_uop.fp_ctrl.fma
connect issue_slots[9].in_uop.bits.fp_ctrl.fastpipe, issue_slots[10].out_uop.fp_ctrl.fastpipe
connect issue_slots[9].in_uop.bits.fp_ctrl.toint, issue_slots[10].out_uop.fp_ctrl.toint
connect issue_slots[9].in_uop.bits.fp_ctrl.fromint, issue_slots[10].out_uop.fp_ctrl.fromint
connect issue_slots[9].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[10].out_uop.fp_ctrl.typeTagOut
connect issue_slots[9].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[10].out_uop.fp_ctrl.typeTagIn
connect issue_slots[9].in_uop.bits.fp_ctrl.swap23, issue_slots[10].out_uop.fp_ctrl.swap23
connect issue_slots[9].in_uop.bits.fp_ctrl.swap12, issue_slots[10].out_uop.fp_ctrl.swap12
connect issue_slots[9].in_uop.bits.fp_ctrl.ren3, issue_slots[10].out_uop.fp_ctrl.ren3
connect issue_slots[9].in_uop.bits.fp_ctrl.ren2, issue_slots[10].out_uop.fp_ctrl.ren2
connect issue_slots[9].in_uop.bits.fp_ctrl.ren1, issue_slots[10].out_uop.fp_ctrl.ren1
connect issue_slots[9].in_uop.bits.fp_ctrl.wen, issue_slots[10].out_uop.fp_ctrl.wen
connect issue_slots[9].in_uop.bits.fp_ctrl.ldst, issue_slots[10].out_uop.fp_ctrl.ldst
connect issue_slots[9].in_uop.bits.op2_sel, issue_slots[10].out_uop.op2_sel
connect issue_slots[9].in_uop.bits.op1_sel, issue_slots[10].out_uop.op1_sel
connect issue_slots[9].in_uop.bits.imm_packed, issue_slots[10].out_uop.imm_packed
connect issue_slots[9].in_uop.bits.pimm, issue_slots[10].out_uop.pimm
connect issue_slots[9].in_uop.bits.imm_sel, issue_slots[10].out_uop.imm_sel
connect issue_slots[9].in_uop.bits.imm_rename, issue_slots[10].out_uop.imm_rename
connect issue_slots[9].in_uop.bits.taken, issue_slots[10].out_uop.taken
connect issue_slots[9].in_uop.bits.pc_lob, issue_slots[10].out_uop.pc_lob
connect issue_slots[9].in_uop.bits.edge_inst, issue_slots[10].out_uop.edge_inst
connect issue_slots[9].in_uop.bits.ftq_idx, issue_slots[10].out_uop.ftq_idx
connect issue_slots[9].in_uop.bits.is_mov, issue_slots[10].out_uop.is_mov
connect issue_slots[9].in_uop.bits.is_rocc, issue_slots[10].out_uop.is_rocc
connect issue_slots[9].in_uop.bits.is_sys_pc2epc, issue_slots[10].out_uop.is_sys_pc2epc
connect issue_slots[9].in_uop.bits.is_eret, issue_slots[10].out_uop.is_eret
connect issue_slots[9].in_uop.bits.is_amo, issue_slots[10].out_uop.is_amo
connect issue_slots[9].in_uop.bits.is_sfence, issue_slots[10].out_uop.is_sfence
connect issue_slots[9].in_uop.bits.is_fencei, issue_slots[10].out_uop.is_fencei
connect issue_slots[9].in_uop.bits.is_fence, issue_slots[10].out_uop.is_fence
connect issue_slots[9].in_uop.bits.is_sfb, issue_slots[10].out_uop.is_sfb
connect issue_slots[9].in_uop.bits.br_type, issue_slots[10].out_uop.br_type
connect issue_slots[9].in_uop.bits.br_tag, issue_slots[10].out_uop.br_tag
connect issue_slots[9].in_uop.bits.br_mask, issue_slots[10].out_uop.br_mask
connect issue_slots[9].in_uop.bits.dis_col_sel, issue_slots[10].out_uop.dis_col_sel
connect issue_slots[9].in_uop.bits.iw_p3_bypass_hint, issue_slots[10].out_uop.iw_p3_bypass_hint
connect issue_slots[9].in_uop.bits.iw_p2_bypass_hint, issue_slots[10].out_uop.iw_p2_bypass_hint
connect issue_slots[9].in_uop.bits.iw_p1_bypass_hint, issue_slots[10].out_uop.iw_p1_bypass_hint
connect issue_slots[9].in_uop.bits.iw_p2_speculative_child, issue_slots[10].out_uop.iw_p2_speculative_child
connect issue_slots[9].in_uop.bits.iw_p1_speculative_child, issue_slots[10].out_uop.iw_p1_speculative_child
connect issue_slots[9].in_uop.bits.iw_issued_partial_dgen, issue_slots[10].out_uop.iw_issued_partial_dgen
connect issue_slots[9].in_uop.bits.iw_issued_partial_agen, issue_slots[10].out_uop.iw_issued_partial_agen
connect issue_slots[9].in_uop.bits.iw_issued, issue_slots[10].out_uop.iw_issued
connect issue_slots[9].in_uop.bits.fu_code[0], issue_slots[10].out_uop.fu_code[0]
connect issue_slots[9].in_uop.bits.fu_code[1], issue_slots[10].out_uop.fu_code[1]
connect issue_slots[9].in_uop.bits.fu_code[2], issue_slots[10].out_uop.fu_code[2]
connect issue_slots[9].in_uop.bits.fu_code[3], issue_slots[10].out_uop.fu_code[3]
connect issue_slots[9].in_uop.bits.fu_code[4], issue_slots[10].out_uop.fu_code[4]
connect issue_slots[9].in_uop.bits.fu_code[5], issue_slots[10].out_uop.fu_code[5]
connect issue_slots[9].in_uop.bits.fu_code[6], issue_slots[10].out_uop.fu_code[6]
connect issue_slots[9].in_uop.bits.fu_code[7], issue_slots[10].out_uop.fu_code[7]
connect issue_slots[9].in_uop.bits.fu_code[8], issue_slots[10].out_uop.fu_code[8]
connect issue_slots[9].in_uop.bits.fu_code[9], issue_slots[10].out_uop.fu_code[9]
connect issue_slots[9].in_uop.bits.iq_type[0], issue_slots[10].out_uop.iq_type[0]
connect issue_slots[9].in_uop.bits.iq_type[1], issue_slots[10].out_uop.iq_type[1]
connect issue_slots[9].in_uop.bits.iq_type[2], issue_slots[10].out_uop.iq_type[2]
connect issue_slots[9].in_uop.bits.iq_type[3], issue_slots[10].out_uop.iq_type[3]
connect issue_slots[9].in_uop.bits.debug_pc, issue_slots[10].out_uop.debug_pc
connect issue_slots[9].in_uop.bits.is_rvc, issue_slots[10].out_uop.is_rvc
connect issue_slots[9].in_uop.bits.debug_inst, issue_slots[10].out_uop.debug_inst
connect issue_slots[9].in_uop.bits.inst, issue_slots[10].out_uop.inst
node _T_181 = eq(shamts_oh[11], UInt<2>(0h2))
when _T_181 :
connect issue_slots[9].in_uop.valid, issue_slots[11].will_be_valid
connect issue_slots[9].in_uop.bits.debug_tsrc, issue_slots[11].out_uop.debug_tsrc
connect issue_slots[9].in_uop.bits.debug_fsrc, issue_slots[11].out_uop.debug_fsrc
connect issue_slots[9].in_uop.bits.bp_xcpt_if, issue_slots[11].out_uop.bp_xcpt_if
connect issue_slots[9].in_uop.bits.bp_debug_if, issue_slots[11].out_uop.bp_debug_if
connect issue_slots[9].in_uop.bits.xcpt_ma_if, issue_slots[11].out_uop.xcpt_ma_if
connect issue_slots[9].in_uop.bits.xcpt_ae_if, issue_slots[11].out_uop.xcpt_ae_if
connect issue_slots[9].in_uop.bits.xcpt_pf_if, issue_slots[11].out_uop.xcpt_pf_if
connect issue_slots[9].in_uop.bits.fp_typ, issue_slots[11].out_uop.fp_typ
connect issue_slots[9].in_uop.bits.fp_rm, issue_slots[11].out_uop.fp_rm
connect issue_slots[9].in_uop.bits.fp_val, issue_slots[11].out_uop.fp_val
connect issue_slots[9].in_uop.bits.fcn_op, issue_slots[11].out_uop.fcn_op
connect issue_slots[9].in_uop.bits.fcn_dw, issue_slots[11].out_uop.fcn_dw
connect issue_slots[9].in_uop.bits.frs3_en, issue_slots[11].out_uop.frs3_en
connect issue_slots[9].in_uop.bits.lrs2_rtype, issue_slots[11].out_uop.lrs2_rtype
connect issue_slots[9].in_uop.bits.lrs1_rtype, issue_slots[11].out_uop.lrs1_rtype
connect issue_slots[9].in_uop.bits.dst_rtype, issue_slots[11].out_uop.dst_rtype
connect issue_slots[9].in_uop.bits.lrs3, issue_slots[11].out_uop.lrs3
connect issue_slots[9].in_uop.bits.lrs2, issue_slots[11].out_uop.lrs2
connect issue_slots[9].in_uop.bits.lrs1, issue_slots[11].out_uop.lrs1
connect issue_slots[9].in_uop.bits.ldst, issue_slots[11].out_uop.ldst
connect issue_slots[9].in_uop.bits.ldst_is_rs1, issue_slots[11].out_uop.ldst_is_rs1
connect issue_slots[9].in_uop.bits.csr_cmd, issue_slots[11].out_uop.csr_cmd
connect issue_slots[9].in_uop.bits.flush_on_commit, issue_slots[11].out_uop.flush_on_commit
connect issue_slots[9].in_uop.bits.is_unique, issue_slots[11].out_uop.is_unique
connect issue_slots[9].in_uop.bits.uses_stq, issue_slots[11].out_uop.uses_stq
connect issue_slots[9].in_uop.bits.uses_ldq, issue_slots[11].out_uop.uses_ldq
connect issue_slots[9].in_uop.bits.mem_signed, issue_slots[11].out_uop.mem_signed
connect issue_slots[9].in_uop.bits.mem_size, issue_slots[11].out_uop.mem_size
connect issue_slots[9].in_uop.bits.mem_cmd, issue_slots[11].out_uop.mem_cmd
connect issue_slots[9].in_uop.bits.exc_cause, issue_slots[11].out_uop.exc_cause
connect issue_slots[9].in_uop.bits.exception, issue_slots[11].out_uop.exception
connect issue_slots[9].in_uop.bits.stale_pdst, issue_slots[11].out_uop.stale_pdst
connect issue_slots[9].in_uop.bits.ppred_busy, issue_slots[11].out_uop.ppred_busy
connect issue_slots[9].in_uop.bits.prs3_busy, issue_slots[11].out_uop.prs3_busy
connect issue_slots[9].in_uop.bits.prs2_busy, issue_slots[11].out_uop.prs2_busy
connect issue_slots[9].in_uop.bits.prs1_busy, issue_slots[11].out_uop.prs1_busy
connect issue_slots[9].in_uop.bits.ppred, issue_slots[11].out_uop.ppred
connect issue_slots[9].in_uop.bits.prs3, issue_slots[11].out_uop.prs3
connect issue_slots[9].in_uop.bits.prs2, issue_slots[11].out_uop.prs2
connect issue_slots[9].in_uop.bits.prs1, issue_slots[11].out_uop.prs1
connect issue_slots[9].in_uop.bits.pdst, issue_slots[11].out_uop.pdst
connect issue_slots[9].in_uop.bits.rxq_idx, issue_slots[11].out_uop.rxq_idx
connect issue_slots[9].in_uop.bits.stq_idx, issue_slots[11].out_uop.stq_idx
connect issue_slots[9].in_uop.bits.ldq_idx, issue_slots[11].out_uop.ldq_idx
connect issue_slots[9].in_uop.bits.rob_idx, issue_slots[11].out_uop.rob_idx
connect issue_slots[9].in_uop.bits.fp_ctrl.vec, issue_slots[11].out_uop.fp_ctrl.vec
connect issue_slots[9].in_uop.bits.fp_ctrl.wflags, issue_slots[11].out_uop.fp_ctrl.wflags
connect issue_slots[9].in_uop.bits.fp_ctrl.sqrt, issue_slots[11].out_uop.fp_ctrl.sqrt
connect issue_slots[9].in_uop.bits.fp_ctrl.div, issue_slots[11].out_uop.fp_ctrl.div
connect issue_slots[9].in_uop.bits.fp_ctrl.fma, issue_slots[11].out_uop.fp_ctrl.fma
connect issue_slots[9].in_uop.bits.fp_ctrl.fastpipe, issue_slots[11].out_uop.fp_ctrl.fastpipe
connect issue_slots[9].in_uop.bits.fp_ctrl.toint, issue_slots[11].out_uop.fp_ctrl.toint
connect issue_slots[9].in_uop.bits.fp_ctrl.fromint, issue_slots[11].out_uop.fp_ctrl.fromint
connect issue_slots[9].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[11].out_uop.fp_ctrl.typeTagOut
connect issue_slots[9].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[11].out_uop.fp_ctrl.typeTagIn
connect issue_slots[9].in_uop.bits.fp_ctrl.swap23, issue_slots[11].out_uop.fp_ctrl.swap23
connect issue_slots[9].in_uop.bits.fp_ctrl.swap12, issue_slots[11].out_uop.fp_ctrl.swap12
connect issue_slots[9].in_uop.bits.fp_ctrl.ren3, issue_slots[11].out_uop.fp_ctrl.ren3
connect issue_slots[9].in_uop.bits.fp_ctrl.ren2, issue_slots[11].out_uop.fp_ctrl.ren2
connect issue_slots[9].in_uop.bits.fp_ctrl.ren1, issue_slots[11].out_uop.fp_ctrl.ren1
connect issue_slots[9].in_uop.bits.fp_ctrl.wen, issue_slots[11].out_uop.fp_ctrl.wen
connect issue_slots[9].in_uop.bits.fp_ctrl.ldst, issue_slots[11].out_uop.fp_ctrl.ldst
connect issue_slots[9].in_uop.bits.op2_sel, issue_slots[11].out_uop.op2_sel
connect issue_slots[9].in_uop.bits.op1_sel, issue_slots[11].out_uop.op1_sel
connect issue_slots[9].in_uop.bits.imm_packed, issue_slots[11].out_uop.imm_packed
connect issue_slots[9].in_uop.bits.pimm, issue_slots[11].out_uop.pimm
connect issue_slots[9].in_uop.bits.imm_sel, issue_slots[11].out_uop.imm_sel
connect issue_slots[9].in_uop.bits.imm_rename, issue_slots[11].out_uop.imm_rename
connect issue_slots[9].in_uop.bits.taken, issue_slots[11].out_uop.taken
connect issue_slots[9].in_uop.bits.pc_lob, issue_slots[11].out_uop.pc_lob
connect issue_slots[9].in_uop.bits.edge_inst, issue_slots[11].out_uop.edge_inst
connect issue_slots[9].in_uop.bits.ftq_idx, issue_slots[11].out_uop.ftq_idx
connect issue_slots[9].in_uop.bits.is_mov, issue_slots[11].out_uop.is_mov
connect issue_slots[9].in_uop.bits.is_rocc, issue_slots[11].out_uop.is_rocc
connect issue_slots[9].in_uop.bits.is_sys_pc2epc, issue_slots[11].out_uop.is_sys_pc2epc
connect issue_slots[9].in_uop.bits.is_eret, issue_slots[11].out_uop.is_eret
connect issue_slots[9].in_uop.bits.is_amo, issue_slots[11].out_uop.is_amo
connect issue_slots[9].in_uop.bits.is_sfence, issue_slots[11].out_uop.is_sfence
connect issue_slots[9].in_uop.bits.is_fencei, issue_slots[11].out_uop.is_fencei
connect issue_slots[9].in_uop.bits.is_fence, issue_slots[11].out_uop.is_fence
connect issue_slots[9].in_uop.bits.is_sfb, issue_slots[11].out_uop.is_sfb
connect issue_slots[9].in_uop.bits.br_type, issue_slots[11].out_uop.br_type
connect issue_slots[9].in_uop.bits.br_tag, issue_slots[11].out_uop.br_tag
connect issue_slots[9].in_uop.bits.br_mask, issue_slots[11].out_uop.br_mask
connect issue_slots[9].in_uop.bits.dis_col_sel, issue_slots[11].out_uop.dis_col_sel
connect issue_slots[9].in_uop.bits.iw_p3_bypass_hint, issue_slots[11].out_uop.iw_p3_bypass_hint
connect issue_slots[9].in_uop.bits.iw_p2_bypass_hint, issue_slots[11].out_uop.iw_p2_bypass_hint
connect issue_slots[9].in_uop.bits.iw_p1_bypass_hint, issue_slots[11].out_uop.iw_p1_bypass_hint
connect issue_slots[9].in_uop.bits.iw_p2_speculative_child, issue_slots[11].out_uop.iw_p2_speculative_child
connect issue_slots[9].in_uop.bits.iw_p1_speculative_child, issue_slots[11].out_uop.iw_p1_speculative_child
connect issue_slots[9].in_uop.bits.iw_issued_partial_dgen, issue_slots[11].out_uop.iw_issued_partial_dgen
connect issue_slots[9].in_uop.bits.iw_issued_partial_agen, issue_slots[11].out_uop.iw_issued_partial_agen
connect issue_slots[9].in_uop.bits.iw_issued, issue_slots[11].out_uop.iw_issued
connect issue_slots[9].in_uop.bits.fu_code[0], issue_slots[11].out_uop.fu_code[0]
connect issue_slots[9].in_uop.bits.fu_code[1], issue_slots[11].out_uop.fu_code[1]
connect issue_slots[9].in_uop.bits.fu_code[2], issue_slots[11].out_uop.fu_code[2]
connect issue_slots[9].in_uop.bits.fu_code[3], issue_slots[11].out_uop.fu_code[3]
connect issue_slots[9].in_uop.bits.fu_code[4], issue_slots[11].out_uop.fu_code[4]
connect issue_slots[9].in_uop.bits.fu_code[5], issue_slots[11].out_uop.fu_code[5]
connect issue_slots[9].in_uop.bits.fu_code[6], issue_slots[11].out_uop.fu_code[6]
connect issue_slots[9].in_uop.bits.fu_code[7], issue_slots[11].out_uop.fu_code[7]
connect issue_slots[9].in_uop.bits.fu_code[8], issue_slots[11].out_uop.fu_code[8]
connect issue_slots[9].in_uop.bits.fu_code[9], issue_slots[11].out_uop.fu_code[9]
connect issue_slots[9].in_uop.bits.iq_type[0], issue_slots[11].out_uop.iq_type[0]
connect issue_slots[9].in_uop.bits.iq_type[1], issue_slots[11].out_uop.iq_type[1]
connect issue_slots[9].in_uop.bits.iq_type[2], issue_slots[11].out_uop.iq_type[2]
connect issue_slots[9].in_uop.bits.iq_type[3], issue_slots[11].out_uop.iq_type[3]
connect issue_slots[9].in_uop.bits.debug_pc, issue_slots[11].out_uop.debug_pc
connect issue_slots[9].in_uop.bits.is_rvc, issue_slots[11].out_uop.is_rvc
connect issue_slots[9].in_uop.bits.debug_inst, issue_slots[11].out_uop.debug_inst
connect issue_slots[9].in_uop.bits.inst, issue_slots[11].out_uop.inst
node _issue_slots_9_clear_T = neq(shamts_oh[9], UInt<1>(0h0))
connect issue_slots[9].clear, _issue_slots_9_clear_T
connect issue_slots[10].in_uop.valid, UInt<1>(0h0)
connect issue_slots[10].in_uop.bits.debug_tsrc, issue_slots[11].out_uop.debug_tsrc
connect issue_slots[10].in_uop.bits.debug_fsrc, issue_slots[11].out_uop.debug_fsrc
connect issue_slots[10].in_uop.bits.bp_xcpt_if, issue_slots[11].out_uop.bp_xcpt_if
connect issue_slots[10].in_uop.bits.bp_debug_if, issue_slots[11].out_uop.bp_debug_if
connect issue_slots[10].in_uop.bits.xcpt_ma_if, issue_slots[11].out_uop.xcpt_ma_if
connect issue_slots[10].in_uop.bits.xcpt_ae_if, issue_slots[11].out_uop.xcpt_ae_if
connect issue_slots[10].in_uop.bits.xcpt_pf_if, issue_slots[11].out_uop.xcpt_pf_if
connect issue_slots[10].in_uop.bits.fp_typ, issue_slots[11].out_uop.fp_typ
connect issue_slots[10].in_uop.bits.fp_rm, issue_slots[11].out_uop.fp_rm
connect issue_slots[10].in_uop.bits.fp_val, issue_slots[11].out_uop.fp_val
connect issue_slots[10].in_uop.bits.fcn_op, issue_slots[11].out_uop.fcn_op
connect issue_slots[10].in_uop.bits.fcn_dw, issue_slots[11].out_uop.fcn_dw
connect issue_slots[10].in_uop.bits.frs3_en, issue_slots[11].out_uop.frs3_en
connect issue_slots[10].in_uop.bits.lrs2_rtype, issue_slots[11].out_uop.lrs2_rtype
connect issue_slots[10].in_uop.bits.lrs1_rtype, issue_slots[11].out_uop.lrs1_rtype
connect issue_slots[10].in_uop.bits.dst_rtype, issue_slots[11].out_uop.dst_rtype
connect issue_slots[10].in_uop.bits.lrs3, issue_slots[11].out_uop.lrs3
connect issue_slots[10].in_uop.bits.lrs2, issue_slots[11].out_uop.lrs2
connect issue_slots[10].in_uop.bits.lrs1, issue_slots[11].out_uop.lrs1
connect issue_slots[10].in_uop.bits.ldst, issue_slots[11].out_uop.ldst
connect issue_slots[10].in_uop.bits.ldst_is_rs1, issue_slots[11].out_uop.ldst_is_rs1
connect issue_slots[10].in_uop.bits.csr_cmd, issue_slots[11].out_uop.csr_cmd
connect issue_slots[10].in_uop.bits.flush_on_commit, issue_slots[11].out_uop.flush_on_commit
connect issue_slots[10].in_uop.bits.is_unique, issue_slots[11].out_uop.is_unique
connect issue_slots[10].in_uop.bits.uses_stq, issue_slots[11].out_uop.uses_stq
connect issue_slots[10].in_uop.bits.uses_ldq, issue_slots[11].out_uop.uses_ldq
connect issue_slots[10].in_uop.bits.mem_signed, issue_slots[11].out_uop.mem_signed
connect issue_slots[10].in_uop.bits.mem_size, issue_slots[11].out_uop.mem_size
connect issue_slots[10].in_uop.bits.mem_cmd, issue_slots[11].out_uop.mem_cmd
connect issue_slots[10].in_uop.bits.exc_cause, issue_slots[11].out_uop.exc_cause
connect issue_slots[10].in_uop.bits.exception, issue_slots[11].out_uop.exception
connect issue_slots[10].in_uop.bits.stale_pdst, issue_slots[11].out_uop.stale_pdst
connect issue_slots[10].in_uop.bits.ppred_busy, issue_slots[11].out_uop.ppred_busy
connect issue_slots[10].in_uop.bits.prs3_busy, issue_slots[11].out_uop.prs3_busy
connect issue_slots[10].in_uop.bits.prs2_busy, issue_slots[11].out_uop.prs2_busy
connect issue_slots[10].in_uop.bits.prs1_busy, issue_slots[11].out_uop.prs1_busy
connect issue_slots[10].in_uop.bits.ppred, issue_slots[11].out_uop.ppred
connect issue_slots[10].in_uop.bits.prs3, issue_slots[11].out_uop.prs3
connect issue_slots[10].in_uop.bits.prs2, issue_slots[11].out_uop.prs2
connect issue_slots[10].in_uop.bits.prs1, issue_slots[11].out_uop.prs1
connect issue_slots[10].in_uop.bits.pdst, issue_slots[11].out_uop.pdst
connect issue_slots[10].in_uop.bits.rxq_idx, issue_slots[11].out_uop.rxq_idx
connect issue_slots[10].in_uop.bits.stq_idx, issue_slots[11].out_uop.stq_idx
connect issue_slots[10].in_uop.bits.ldq_idx, issue_slots[11].out_uop.ldq_idx
connect issue_slots[10].in_uop.bits.rob_idx, issue_slots[11].out_uop.rob_idx
connect issue_slots[10].in_uop.bits.fp_ctrl.vec, issue_slots[11].out_uop.fp_ctrl.vec
connect issue_slots[10].in_uop.bits.fp_ctrl.wflags, issue_slots[11].out_uop.fp_ctrl.wflags
connect issue_slots[10].in_uop.bits.fp_ctrl.sqrt, issue_slots[11].out_uop.fp_ctrl.sqrt
connect issue_slots[10].in_uop.bits.fp_ctrl.div, issue_slots[11].out_uop.fp_ctrl.div
connect issue_slots[10].in_uop.bits.fp_ctrl.fma, issue_slots[11].out_uop.fp_ctrl.fma
connect issue_slots[10].in_uop.bits.fp_ctrl.fastpipe, issue_slots[11].out_uop.fp_ctrl.fastpipe
connect issue_slots[10].in_uop.bits.fp_ctrl.toint, issue_slots[11].out_uop.fp_ctrl.toint
connect issue_slots[10].in_uop.bits.fp_ctrl.fromint, issue_slots[11].out_uop.fp_ctrl.fromint
connect issue_slots[10].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[11].out_uop.fp_ctrl.typeTagOut
connect issue_slots[10].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[11].out_uop.fp_ctrl.typeTagIn
connect issue_slots[10].in_uop.bits.fp_ctrl.swap23, issue_slots[11].out_uop.fp_ctrl.swap23
connect issue_slots[10].in_uop.bits.fp_ctrl.swap12, issue_slots[11].out_uop.fp_ctrl.swap12
connect issue_slots[10].in_uop.bits.fp_ctrl.ren3, issue_slots[11].out_uop.fp_ctrl.ren3
connect issue_slots[10].in_uop.bits.fp_ctrl.ren2, issue_slots[11].out_uop.fp_ctrl.ren2
connect issue_slots[10].in_uop.bits.fp_ctrl.ren1, issue_slots[11].out_uop.fp_ctrl.ren1
connect issue_slots[10].in_uop.bits.fp_ctrl.wen, issue_slots[11].out_uop.fp_ctrl.wen
connect issue_slots[10].in_uop.bits.fp_ctrl.ldst, issue_slots[11].out_uop.fp_ctrl.ldst
connect issue_slots[10].in_uop.bits.op2_sel, issue_slots[11].out_uop.op2_sel
connect issue_slots[10].in_uop.bits.op1_sel, issue_slots[11].out_uop.op1_sel
connect issue_slots[10].in_uop.bits.imm_packed, issue_slots[11].out_uop.imm_packed
connect issue_slots[10].in_uop.bits.pimm, issue_slots[11].out_uop.pimm
connect issue_slots[10].in_uop.bits.imm_sel, issue_slots[11].out_uop.imm_sel
connect issue_slots[10].in_uop.bits.imm_rename, issue_slots[11].out_uop.imm_rename
connect issue_slots[10].in_uop.bits.taken, issue_slots[11].out_uop.taken
connect issue_slots[10].in_uop.bits.pc_lob, issue_slots[11].out_uop.pc_lob
connect issue_slots[10].in_uop.bits.edge_inst, issue_slots[11].out_uop.edge_inst
connect issue_slots[10].in_uop.bits.ftq_idx, issue_slots[11].out_uop.ftq_idx
connect issue_slots[10].in_uop.bits.is_mov, issue_slots[11].out_uop.is_mov
connect issue_slots[10].in_uop.bits.is_rocc, issue_slots[11].out_uop.is_rocc
connect issue_slots[10].in_uop.bits.is_sys_pc2epc, issue_slots[11].out_uop.is_sys_pc2epc
connect issue_slots[10].in_uop.bits.is_eret, issue_slots[11].out_uop.is_eret
connect issue_slots[10].in_uop.bits.is_amo, issue_slots[11].out_uop.is_amo
connect issue_slots[10].in_uop.bits.is_sfence, issue_slots[11].out_uop.is_sfence
connect issue_slots[10].in_uop.bits.is_fencei, issue_slots[11].out_uop.is_fencei
connect issue_slots[10].in_uop.bits.is_fence, issue_slots[11].out_uop.is_fence
connect issue_slots[10].in_uop.bits.is_sfb, issue_slots[11].out_uop.is_sfb
connect issue_slots[10].in_uop.bits.br_type, issue_slots[11].out_uop.br_type
connect issue_slots[10].in_uop.bits.br_tag, issue_slots[11].out_uop.br_tag
connect issue_slots[10].in_uop.bits.br_mask, issue_slots[11].out_uop.br_mask
connect issue_slots[10].in_uop.bits.dis_col_sel, issue_slots[11].out_uop.dis_col_sel
connect issue_slots[10].in_uop.bits.iw_p3_bypass_hint, issue_slots[11].out_uop.iw_p3_bypass_hint
connect issue_slots[10].in_uop.bits.iw_p2_bypass_hint, issue_slots[11].out_uop.iw_p2_bypass_hint
connect issue_slots[10].in_uop.bits.iw_p1_bypass_hint, issue_slots[11].out_uop.iw_p1_bypass_hint
connect issue_slots[10].in_uop.bits.iw_p2_speculative_child, issue_slots[11].out_uop.iw_p2_speculative_child
connect issue_slots[10].in_uop.bits.iw_p1_speculative_child, issue_slots[11].out_uop.iw_p1_speculative_child
connect issue_slots[10].in_uop.bits.iw_issued_partial_dgen, issue_slots[11].out_uop.iw_issued_partial_dgen
connect issue_slots[10].in_uop.bits.iw_issued_partial_agen, issue_slots[11].out_uop.iw_issued_partial_agen
connect issue_slots[10].in_uop.bits.iw_issued, issue_slots[11].out_uop.iw_issued
connect issue_slots[10].in_uop.bits.fu_code[0], issue_slots[11].out_uop.fu_code[0]
connect issue_slots[10].in_uop.bits.fu_code[1], issue_slots[11].out_uop.fu_code[1]
connect issue_slots[10].in_uop.bits.fu_code[2], issue_slots[11].out_uop.fu_code[2]
connect issue_slots[10].in_uop.bits.fu_code[3], issue_slots[11].out_uop.fu_code[3]
connect issue_slots[10].in_uop.bits.fu_code[4], issue_slots[11].out_uop.fu_code[4]
connect issue_slots[10].in_uop.bits.fu_code[5], issue_slots[11].out_uop.fu_code[5]
connect issue_slots[10].in_uop.bits.fu_code[6], issue_slots[11].out_uop.fu_code[6]
connect issue_slots[10].in_uop.bits.fu_code[7], issue_slots[11].out_uop.fu_code[7]
connect issue_slots[10].in_uop.bits.fu_code[8], issue_slots[11].out_uop.fu_code[8]
connect issue_slots[10].in_uop.bits.fu_code[9], issue_slots[11].out_uop.fu_code[9]
connect issue_slots[10].in_uop.bits.iq_type[0], issue_slots[11].out_uop.iq_type[0]
connect issue_slots[10].in_uop.bits.iq_type[1], issue_slots[11].out_uop.iq_type[1]
connect issue_slots[10].in_uop.bits.iq_type[2], issue_slots[11].out_uop.iq_type[2]
connect issue_slots[10].in_uop.bits.iq_type[3], issue_slots[11].out_uop.iq_type[3]
connect issue_slots[10].in_uop.bits.debug_pc, issue_slots[11].out_uop.debug_pc
connect issue_slots[10].in_uop.bits.is_rvc, issue_slots[11].out_uop.is_rvc
connect issue_slots[10].in_uop.bits.debug_inst, issue_slots[11].out_uop.debug_inst
connect issue_slots[10].in_uop.bits.inst, issue_slots[11].out_uop.inst
node _T_182 = eq(shamts_oh[11], UInt<1>(0h1))
when _T_182 :
connect issue_slots[10].in_uop.valid, issue_slots[11].will_be_valid
connect issue_slots[10].in_uop.bits.debug_tsrc, issue_slots[11].out_uop.debug_tsrc
connect issue_slots[10].in_uop.bits.debug_fsrc, issue_slots[11].out_uop.debug_fsrc
connect issue_slots[10].in_uop.bits.bp_xcpt_if, issue_slots[11].out_uop.bp_xcpt_if
connect issue_slots[10].in_uop.bits.bp_debug_if, issue_slots[11].out_uop.bp_debug_if
connect issue_slots[10].in_uop.bits.xcpt_ma_if, issue_slots[11].out_uop.xcpt_ma_if
connect issue_slots[10].in_uop.bits.xcpt_ae_if, issue_slots[11].out_uop.xcpt_ae_if
connect issue_slots[10].in_uop.bits.xcpt_pf_if, issue_slots[11].out_uop.xcpt_pf_if
connect issue_slots[10].in_uop.bits.fp_typ, issue_slots[11].out_uop.fp_typ
connect issue_slots[10].in_uop.bits.fp_rm, issue_slots[11].out_uop.fp_rm
connect issue_slots[10].in_uop.bits.fp_val, issue_slots[11].out_uop.fp_val
connect issue_slots[10].in_uop.bits.fcn_op, issue_slots[11].out_uop.fcn_op
connect issue_slots[10].in_uop.bits.fcn_dw, issue_slots[11].out_uop.fcn_dw
connect issue_slots[10].in_uop.bits.frs3_en, issue_slots[11].out_uop.frs3_en
connect issue_slots[10].in_uop.bits.lrs2_rtype, issue_slots[11].out_uop.lrs2_rtype
connect issue_slots[10].in_uop.bits.lrs1_rtype, issue_slots[11].out_uop.lrs1_rtype
connect issue_slots[10].in_uop.bits.dst_rtype, issue_slots[11].out_uop.dst_rtype
connect issue_slots[10].in_uop.bits.lrs3, issue_slots[11].out_uop.lrs3
connect issue_slots[10].in_uop.bits.lrs2, issue_slots[11].out_uop.lrs2
connect issue_slots[10].in_uop.bits.lrs1, issue_slots[11].out_uop.lrs1
connect issue_slots[10].in_uop.bits.ldst, issue_slots[11].out_uop.ldst
connect issue_slots[10].in_uop.bits.ldst_is_rs1, issue_slots[11].out_uop.ldst_is_rs1
connect issue_slots[10].in_uop.bits.csr_cmd, issue_slots[11].out_uop.csr_cmd
connect issue_slots[10].in_uop.bits.flush_on_commit, issue_slots[11].out_uop.flush_on_commit
connect issue_slots[10].in_uop.bits.is_unique, issue_slots[11].out_uop.is_unique
connect issue_slots[10].in_uop.bits.uses_stq, issue_slots[11].out_uop.uses_stq
connect issue_slots[10].in_uop.bits.uses_ldq, issue_slots[11].out_uop.uses_ldq
connect issue_slots[10].in_uop.bits.mem_signed, issue_slots[11].out_uop.mem_signed
connect issue_slots[10].in_uop.bits.mem_size, issue_slots[11].out_uop.mem_size
connect issue_slots[10].in_uop.bits.mem_cmd, issue_slots[11].out_uop.mem_cmd
connect issue_slots[10].in_uop.bits.exc_cause, issue_slots[11].out_uop.exc_cause
connect issue_slots[10].in_uop.bits.exception, issue_slots[11].out_uop.exception
connect issue_slots[10].in_uop.bits.stale_pdst, issue_slots[11].out_uop.stale_pdst
connect issue_slots[10].in_uop.bits.ppred_busy, issue_slots[11].out_uop.ppred_busy
connect issue_slots[10].in_uop.bits.prs3_busy, issue_slots[11].out_uop.prs3_busy
connect issue_slots[10].in_uop.bits.prs2_busy, issue_slots[11].out_uop.prs2_busy
connect issue_slots[10].in_uop.bits.prs1_busy, issue_slots[11].out_uop.prs1_busy
connect issue_slots[10].in_uop.bits.ppred, issue_slots[11].out_uop.ppred
connect issue_slots[10].in_uop.bits.prs3, issue_slots[11].out_uop.prs3
connect issue_slots[10].in_uop.bits.prs2, issue_slots[11].out_uop.prs2
connect issue_slots[10].in_uop.bits.prs1, issue_slots[11].out_uop.prs1
connect issue_slots[10].in_uop.bits.pdst, issue_slots[11].out_uop.pdst
connect issue_slots[10].in_uop.bits.rxq_idx, issue_slots[11].out_uop.rxq_idx
connect issue_slots[10].in_uop.bits.stq_idx, issue_slots[11].out_uop.stq_idx
connect issue_slots[10].in_uop.bits.ldq_idx, issue_slots[11].out_uop.ldq_idx
connect issue_slots[10].in_uop.bits.rob_idx, issue_slots[11].out_uop.rob_idx
connect issue_slots[10].in_uop.bits.fp_ctrl.vec, issue_slots[11].out_uop.fp_ctrl.vec
connect issue_slots[10].in_uop.bits.fp_ctrl.wflags, issue_slots[11].out_uop.fp_ctrl.wflags
connect issue_slots[10].in_uop.bits.fp_ctrl.sqrt, issue_slots[11].out_uop.fp_ctrl.sqrt
connect issue_slots[10].in_uop.bits.fp_ctrl.div, issue_slots[11].out_uop.fp_ctrl.div
connect issue_slots[10].in_uop.bits.fp_ctrl.fma, issue_slots[11].out_uop.fp_ctrl.fma
connect issue_slots[10].in_uop.bits.fp_ctrl.fastpipe, issue_slots[11].out_uop.fp_ctrl.fastpipe
connect issue_slots[10].in_uop.bits.fp_ctrl.toint, issue_slots[11].out_uop.fp_ctrl.toint
connect issue_slots[10].in_uop.bits.fp_ctrl.fromint, issue_slots[11].out_uop.fp_ctrl.fromint
connect issue_slots[10].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[11].out_uop.fp_ctrl.typeTagOut
connect issue_slots[10].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[11].out_uop.fp_ctrl.typeTagIn
connect issue_slots[10].in_uop.bits.fp_ctrl.swap23, issue_slots[11].out_uop.fp_ctrl.swap23
connect issue_slots[10].in_uop.bits.fp_ctrl.swap12, issue_slots[11].out_uop.fp_ctrl.swap12
connect issue_slots[10].in_uop.bits.fp_ctrl.ren3, issue_slots[11].out_uop.fp_ctrl.ren3
connect issue_slots[10].in_uop.bits.fp_ctrl.ren2, issue_slots[11].out_uop.fp_ctrl.ren2
connect issue_slots[10].in_uop.bits.fp_ctrl.ren1, issue_slots[11].out_uop.fp_ctrl.ren1
connect issue_slots[10].in_uop.bits.fp_ctrl.wen, issue_slots[11].out_uop.fp_ctrl.wen
connect issue_slots[10].in_uop.bits.fp_ctrl.ldst, issue_slots[11].out_uop.fp_ctrl.ldst
connect issue_slots[10].in_uop.bits.op2_sel, issue_slots[11].out_uop.op2_sel
connect issue_slots[10].in_uop.bits.op1_sel, issue_slots[11].out_uop.op1_sel
connect issue_slots[10].in_uop.bits.imm_packed, issue_slots[11].out_uop.imm_packed
connect issue_slots[10].in_uop.bits.pimm, issue_slots[11].out_uop.pimm
connect issue_slots[10].in_uop.bits.imm_sel, issue_slots[11].out_uop.imm_sel
connect issue_slots[10].in_uop.bits.imm_rename, issue_slots[11].out_uop.imm_rename
connect issue_slots[10].in_uop.bits.taken, issue_slots[11].out_uop.taken
connect issue_slots[10].in_uop.bits.pc_lob, issue_slots[11].out_uop.pc_lob
connect issue_slots[10].in_uop.bits.edge_inst, issue_slots[11].out_uop.edge_inst
connect issue_slots[10].in_uop.bits.ftq_idx, issue_slots[11].out_uop.ftq_idx
connect issue_slots[10].in_uop.bits.is_mov, issue_slots[11].out_uop.is_mov
connect issue_slots[10].in_uop.bits.is_rocc, issue_slots[11].out_uop.is_rocc
connect issue_slots[10].in_uop.bits.is_sys_pc2epc, issue_slots[11].out_uop.is_sys_pc2epc
connect issue_slots[10].in_uop.bits.is_eret, issue_slots[11].out_uop.is_eret
connect issue_slots[10].in_uop.bits.is_amo, issue_slots[11].out_uop.is_amo
connect issue_slots[10].in_uop.bits.is_sfence, issue_slots[11].out_uop.is_sfence
connect issue_slots[10].in_uop.bits.is_fencei, issue_slots[11].out_uop.is_fencei
connect issue_slots[10].in_uop.bits.is_fence, issue_slots[11].out_uop.is_fence
connect issue_slots[10].in_uop.bits.is_sfb, issue_slots[11].out_uop.is_sfb
connect issue_slots[10].in_uop.bits.br_type, issue_slots[11].out_uop.br_type
connect issue_slots[10].in_uop.bits.br_tag, issue_slots[11].out_uop.br_tag
connect issue_slots[10].in_uop.bits.br_mask, issue_slots[11].out_uop.br_mask
connect issue_slots[10].in_uop.bits.dis_col_sel, issue_slots[11].out_uop.dis_col_sel
connect issue_slots[10].in_uop.bits.iw_p3_bypass_hint, issue_slots[11].out_uop.iw_p3_bypass_hint
connect issue_slots[10].in_uop.bits.iw_p2_bypass_hint, issue_slots[11].out_uop.iw_p2_bypass_hint
connect issue_slots[10].in_uop.bits.iw_p1_bypass_hint, issue_slots[11].out_uop.iw_p1_bypass_hint
connect issue_slots[10].in_uop.bits.iw_p2_speculative_child, issue_slots[11].out_uop.iw_p2_speculative_child
connect issue_slots[10].in_uop.bits.iw_p1_speculative_child, issue_slots[11].out_uop.iw_p1_speculative_child
connect issue_slots[10].in_uop.bits.iw_issued_partial_dgen, issue_slots[11].out_uop.iw_issued_partial_dgen
connect issue_slots[10].in_uop.bits.iw_issued_partial_agen, issue_slots[11].out_uop.iw_issued_partial_agen
connect issue_slots[10].in_uop.bits.iw_issued, issue_slots[11].out_uop.iw_issued
connect issue_slots[10].in_uop.bits.fu_code[0], issue_slots[11].out_uop.fu_code[0]
connect issue_slots[10].in_uop.bits.fu_code[1], issue_slots[11].out_uop.fu_code[1]
connect issue_slots[10].in_uop.bits.fu_code[2], issue_slots[11].out_uop.fu_code[2]
connect issue_slots[10].in_uop.bits.fu_code[3], issue_slots[11].out_uop.fu_code[3]
connect issue_slots[10].in_uop.bits.fu_code[4], issue_slots[11].out_uop.fu_code[4]
connect issue_slots[10].in_uop.bits.fu_code[5], issue_slots[11].out_uop.fu_code[5]
connect issue_slots[10].in_uop.bits.fu_code[6], issue_slots[11].out_uop.fu_code[6]
connect issue_slots[10].in_uop.bits.fu_code[7], issue_slots[11].out_uop.fu_code[7]
connect issue_slots[10].in_uop.bits.fu_code[8], issue_slots[11].out_uop.fu_code[8]
connect issue_slots[10].in_uop.bits.fu_code[9], issue_slots[11].out_uop.fu_code[9]
connect issue_slots[10].in_uop.bits.iq_type[0], issue_slots[11].out_uop.iq_type[0]
connect issue_slots[10].in_uop.bits.iq_type[1], issue_slots[11].out_uop.iq_type[1]
connect issue_slots[10].in_uop.bits.iq_type[2], issue_slots[11].out_uop.iq_type[2]
connect issue_slots[10].in_uop.bits.iq_type[3], issue_slots[11].out_uop.iq_type[3]
connect issue_slots[10].in_uop.bits.debug_pc, issue_slots[11].out_uop.debug_pc
connect issue_slots[10].in_uop.bits.is_rvc, issue_slots[11].out_uop.is_rvc
connect issue_slots[10].in_uop.bits.debug_inst, issue_slots[11].out_uop.debug_inst
connect issue_slots[10].in_uop.bits.inst, issue_slots[11].out_uop.inst
node _T_183 = eq(shamts_oh[12], UInt<2>(0h2))
when _T_183 :
connect issue_slots[10].in_uop.valid, issue_slots[12].will_be_valid
connect issue_slots[10].in_uop.bits.debug_tsrc, issue_slots[12].out_uop.debug_tsrc
connect issue_slots[10].in_uop.bits.debug_fsrc, issue_slots[12].out_uop.debug_fsrc
connect issue_slots[10].in_uop.bits.bp_xcpt_if, issue_slots[12].out_uop.bp_xcpt_if
connect issue_slots[10].in_uop.bits.bp_debug_if, issue_slots[12].out_uop.bp_debug_if
connect issue_slots[10].in_uop.bits.xcpt_ma_if, issue_slots[12].out_uop.xcpt_ma_if
connect issue_slots[10].in_uop.bits.xcpt_ae_if, issue_slots[12].out_uop.xcpt_ae_if
connect issue_slots[10].in_uop.bits.xcpt_pf_if, issue_slots[12].out_uop.xcpt_pf_if
connect issue_slots[10].in_uop.bits.fp_typ, issue_slots[12].out_uop.fp_typ
connect issue_slots[10].in_uop.bits.fp_rm, issue_slots[12].out_uop.fp_rm
connect issue_slots[10].in_uop.bits.fp_val, issue_slots[12].out_uop.fp_val
connect issue_slots[10].in_uop.bits.fcn_op, issue_slots[12].out_uop.fcn_op
connect issue_slots[10].in_uop.bits.fcn_dw, issue_slots[12].out_uop.fcn_dw
connect issue_slots[10].in_uop.bits.frs3_en, issue_slots[12].out_uop.frs3_en
connect issue_slots[10].in_uop.bits.lrs2_rtype, issue_slots[12].out_uop.lrs2_rtype
connect issue_slots[10].in_uop.bits.lrs1_rtype, issue_slots[12].out_uop.lrs1_rtype
connect issue_slots[10].in_uop.bits.dst_rtype, issue_slots[12].out_uop.dst_rtype
connect issue_slots[10].in_uop.bits.lrs3, issue_slots[12].out_uop.lrs3
connect issue_slots[10].in_uop.bits.lrs2, issue_slots[12].out_uop.lrs2
connect issue_slots[10].in_uop.bits.lrs1, issue_slots[12].out_uop.lrs1
connect issue_slots[10].in_uop.bits.ldst, issue_slots[12].out_uop.ldst
connect issue_slots[10].in_uop.bits.ldst_is_rs1, issue_slots[12].out_uop.ldst_is_rs1
connect issue_slots[10].in_uop.bits.csr_cmd, issue_slots[12].out_uop.csr_cmd
connect issue_slots[10].in_uop.bits.flush_on_commit, issue_slots[12].out_uop.flush_on_commit
connect issue_slots[10].in_uop.bits.is_unique, issue_slots[12].out_uop.is_unique
connect issue_slots[10].in_uop.bits.uses_stq, issue_slots[12].out_uop.uses_stq
connect issue_slots[10].in_uop.bits.uses_ldq, issue_slots[12].out_uop.uses_ldq
connect issue_slots[10].in_uop.bits.mem_signed, issue_slots[12].out_uop.mem_signed
connect issue_slots[10].in_uop.bits.mem_size, issue_slots[12].out_uop.mem_size
connect issue_slots[10].in_uop.bits.mem_cmd, issue_slots[12].out_uop.mem_cmd
connect issue_slots[10].in_uop.bits.exc_cause, issue_slots[12].out_uop.exc_cause
connect issue_slots[10].in_uop.bits.exception, issue_slots[12].out_uop.exception
connect issue_slots[10].in_uop.bits.stale_pdst, issue_slots[12].out_uop.stale_pdst
connect issue_slots[10].in_uop.bits.ppred_busy, issue_slots[12].out_uop.ppred_busy
connect issue_slots[10].in_uop.bits.prs3_busy, issue_slots[12].out_uop.prs3_busy
connect issue_slots[10].in_uop.bits.prs2_busy, issue_slots[12].out_uop.prs2_busy
connect issue_slots[10].in_uop.bits.prs1_busy, issue_slots[12].out_uop.prs1_busy
connect issue_slots[10].in_uop.bits.ppred, issue_slots[12].out_uop.ppred
connect issue_slots[10].in_uop.bits.prs3, issue_slots[12].out_uop.prs3
connect issue_slots[10].in_uop.bits.prs2, issue_slots[12].out_uop.prs2
connect issue_slots[10].in_uop.bits.prs1, issue_slots[12].out_uop.prs1
connect issue_slots[10].in_uop.bits.pdst, issue_slots[12].out_uop.pdst
connect issue_slots[10].in_uop.bits.rxq_idx, issue_slots[12].out_uop.rxq_idx
connect issue_slots[10].in_uop.bits.stq_idx, issue_slots[12].out_uop.stq_idx
connect issue_slots[10].in_uop.bits.ldq_idx, issue_slots[12].out_uop.ldq_idx
connect issue_slots[10].in_uop.bits.rob_idx, issue_slots[12].out_uop.rob_idx
connect issue_slots[10].in_uop.bits.fp_ctrl.vec, issue_slots[12].out_uop.fp_ctrl.vec
connect issue_slots[10].in_uop.bits.fp_ctrl.wflags, issue_slots[12].out_uop.fp_ctrl.wflags
connect issue_slots[10].in_uop.bits.fp_ctrl.sqrt, issue_slots[12].out_uop.fp_ctrl.sqrt
connect issue_slots[10].in_uop.bits.fp_ctrl.div, issue_slots[12].out_uop.fp_ctrl.div
connect issue_slots[10].in_uop.bits.fp_ctrl.fma, issue_slots[12].out_uop.fp_ctrl.fma
connect issue_slots[10].in_uop.bits.fp_ctrl.fastpipe, issue_slots[12].out_uop.fp_ctrl.fastpipe
connect issue_slots[10].in_uop.bits.fp_ctrl.toint, issue_slots[12].out_uop.fp_ctrl.toint
connect issue_slots[10].in_uop.bits.fp_ctrl.fromint, issue_slots[12].out_uop.fp_ctrl.fromint
connect issue_slots[10].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[12].out_uop.fp_ctrl.typeTagOut
connect issue_slots[10].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[12].out_uop.fp_ctrl.typeTagIn
connect issue_slots[10].in_uop.bits.fp_ctrl.swap23, issue_slots[12].out_uop.fp_ctrl.swap23
connect issue_slots[10].in_uop.bits.fp_ctrl.swap12, issue_slots[12].out_uop.fp_ctrl.swap12
connect issue_slots[10].in_uop.bits.fp_ctrl.ren3, issue_slots[12].out_uop.fp_ctrl.ren3
connect issue_slots[10].in_uop.bits.fp_ctrl.ren2, issue_slots[12].out_uop.fp_ctrl.ren2
connect issue_slots[10].in_uop.bits.fp_ctrl.ren1, issue_slots[12].out_uop.fp_ctrl.ren1
connect issue_slots[10].in_uop.bits.fp_ctrl.wen, issue_slots[12].out_uop.fp_ctrl.wen
connect issue_slots[10].in_uop.bits.fp_ctrl.ldst, issue_slots[12].out_uop.fp_ctrl.ldst
connect issue_slots[10].in_uop.bits.op2_sel, issue_slots[12].out_uop.op2_sel
connect issue_slots[10].in_uop.bits.op1_sel, issue_slots[12].out_uop.op1_sel
connect issue_slots[10].in_uop.bits.imm_packed, issue_slots[12].out_uop.imm_packed
connect issue_slots[10].in_uop.bits.pimm, issue_slots[12].out_uop.pimm
connect issue_slots[10].in_uop.bits.imm_sel, issue_slots[12].out_uop.imm_sel
connect issue_slots[10].in_uop.bits.imm_rename, issue_slots[12].out_uop.imm_rename
connect issue_slots[10].in_uop.bits.taken, issue_slots[12].out_uop.taken
connect issue_slots[10].in_uop.bits.pc_lob, issue_slots[12].out_uop.pc_lob
connect issue_slots[10].in_uop.bits.edge_inst, issue_slots[12].out_uop.edge_inst
connect issue_slots[10].in_uop.bits.ftq_idx, issue_slots[12].out_uop.ftq_idx
connect issue_slots[10].in_uop.bits.is_mov, issue_slots[12].out_uop.is_mov
connect issue_slots[10].in_uop.bits.is_rocc, issue_slots[12].out_uop.is_rocc
connect issue_slots[10].in_uop.bits.is_sys_pc2epc, issue_slots[12].out_uop.is_sys_pc2epc
connect issue_slots[10].in_uop.bits.is_eret, issue_slots[12].out_uop.is_eret
connect issue_slots[10].in_uop.bits.is_amo, issue_slots[12].out_uop.is_amo
connect issue_slots[10].in_uop.bits.is_sfence, issue_slots[12].out_uop.is_sfence
connect issue_slots[10].in_uop.bits.is_fencei, issue_slots[12].out_uop.is_fencei
connect issue_slots[10].in_uop.bits.is_fence, issue_slots[12].out_uop.is_fence
connect issue_slots[10].in_uop.bits.is_sfb, issue_slots[12].out_uop.is_sfb
connect issue_slots[10].in_uop.bits.br_type, issue_slots[12].out_uop.br_type
connect issue_slots[10].in_uop.bits.br_tag, issue_slots[12].out_uop.br_tag
connect issue_slots[10].in_uop.bits.br_mask, issue_slots[12].out_uop.br_mask
connect issue_slots[10].in_uop.bits.dis_col_sel, issue_slots[12].out_uop.dis_col_sel
connect issue_slots[10].in_uop.bits.iw_p3_bypass_hint, issue_slots[12].out_uop.iw_p3_bypass_hint
connect issue_slots[10].in_uop.bits.iw_p2_bypass_hint, issue_slots[12].out_uop.iw_p2_bypass_hint
connect issue_slots[10].in_uop.bits.iw_p1_bypass_hint, issue_slots[12].out_uop.iw_p1_bypass_hint
connect issue_slots[10].in_uop.bits.iw_p2_speculative_child, issue_slots[12].out_uop.iw_p2_speculative_child
connect issue_slots[10].in_uop.bits.iw_p1_speculative_child, issue_slots[12].out_uop.iw_p1_speculative_child
connect issue_slots[10].in_uop.bits.iw_issued_partial_dgen, issue_slots[12].out_uop.iw_issued_partial_dgen
connect issue_slots[10].in_uop.bits.iw_issued_partial_agen, issue_slots[12].out_uop.iw_issued_partial_agen
connect issue_slots[10].in_uop.bits.iw_issued, issue_slots[12].out_uop.iw_issued
connect issue_slots[10].in_uop.bits.fu_code[0], issue_slots[12].out_uop.fu_code[0]
connect issue_slots[10].in_uop.bits.fu_code[1], issue_slots[12].out_uop.fu_code[1]
connect issue_slots[10].in_uop.bits.fu_code[2], issue_slots[12].out_uop.fu_code[2]
connect issue_slots[10].in_uop.bits.fu_code[3], issue_slots[12].out_uop.fu_code[3]
connect issue_slots[10].in_uop.bits.fu_code[4], issue_slots[12].out_uop.fu_code[4]
connect issue_slots[10].in_uop.bits.fu_code[5], issue_slots[12].out_uop.fu_code[5]
connect issue_slots[10].in_uop.bits.fu_code[6], issue_slots[12].out_uop.fu_code[6]
connect issue_slots[10].in_uop.bits.fu_code[7], issue_slots[12].out_uop.fu_code[7]
connect issue_slots[10].in_uop.bits.fu_code[8], issue_slots[12].out_uop.fu_code[8]
connect issue_slots[10].in_uop.bits.fu_code[9], issue_slots[12].out_uop.fu_code[9]
connect issue_slots[10].in_uop.bits.iq_type[0], issue_slots[12].out_uop.iq_type[0]
connect issue_slots[10].in_uop.bits.iq_type[1], issue_slots[12].out_uop.iq_type[1]
connect issue_slots[10].in_uop.bits.iq_type[2], issue_slots[12].out_uop.iq_type[2]
connect issue_slots[10].in_uop.bits.iq_type[3], issue_slots[12].out_uop.iq_type[3]
connect issue_slots[10].in_uop.bits.debug_pc, issue_slots[12].out_uop.debug_pc
connect issue_slots[10].in_uop.bits.is_rvc, issue_slots[12].out_uop.is_rvc
connect issue_slots[10].in_uop.bits.debug_inst, issue_slots[12].out_uop.debug_inst
connect issue_slots[10].in_uop.bits.inst, issue_slots[12].out_uop.inst
node _issue_slots_10_clear_T = neq(shamts_oh[10], UInt<1>(0h0))
connect issue_slots[10].clear, _issue_slots_10_clear_T
connect issue_slots[11].in_uop.valid, UInt<1>(0h0)
connect issue_slots[11].in_uop.bits.debug_tsrc, issue_slots[12].out_uop.debug_tsrc
connect issue_slots[11].in_uop.bits.debug_fsrc, issue_slots[12].out_uop.debug_fsrc
connect issue_slots[11].in_uop.bits.bp_xcpt_if, issue_slots[12].out_uop.bp_xcpt_if
connect issue_slots[11].in_uop.bits.bp_debug_if, issue_slots[12].out_uop.bp_debug_if
connect issue_slots[11].in_uop.bits.xcpt_ma_if, issue_slots[12].out_uop.xcpt_ma_if
connect issue_slots[11].in_uop.bits.xcpt_ae_if, issue_slots[12].out_uop.xcpt_ae_if
connect issue_slots[11].in_uop.bits.xcpt_pf_if, issue_slots[12].out_uop.xcpt_pf_if
connect issue_slots[11].in_uop.bits.fp_typ, issue_slots[12].out_uop.fp_typ
connect issue_slots[11].in_uop.bits.fp_rm, issue_slots[12].out_uop.fp_rm
connect issue_slots[11].in_uop.bits.fp_val, issue_slots[12].out_uop.fp_val
connect issue_slots[11].in_uop.bits.fcn_op, issue_slots[12].out_uop.fcn_op
connect issue_slots[11].in_uop.bits.fcn_dw, issue_slots[12].out_uop.fcn_dw
connect issue_slots[11].in_uop.bits.frs3_en, issue_slots[12].out_uop.frs3_en
connect issue_slots[11].in_uop.bits.lrs2_rtype, issue_slots[12].out_uop.lrs2_rtype
connect issue_slots[11].in_uop.bits.lrs1_rtype, issue_slots[12].out_uop.lrs1_rtype
connect issue_slots[11].in_uop.bits.dst_rtype, issue_slots[12].out_uop.dst_rtype
connect issue_slots[11].in_uop.bits.lrs3, issue_slots[12].out_uop.lrs3
connect issue_slots[11].in_uop.bits.lrs2, issue_slots[12].out_uop.lrs2
connect issue_slots[11].in_uop.bits.lrs1, issue_slots[12].out_uop.lrs1
connect issue_slots[11].in_uop.bits.ldst, issue_slots[12].out_uop.ldst
connect issue_slots[11].in_uop.bits.ldst_is_rs1, issue_slots[12].out_uop.ldst_is_rs1
connect issue_slots[11].in_uop.bits.csr_cmd, issue_slots[12].out_uop.csr_cmd
connect issue_slots[11].in_uop.bits.flush_on_commit, issue_slots[12].out_uop.flush_on_commit
connect issue_slots[11].in_uop.bits.is_unique, issue_slots[12].out_uop.is_unique
connect issue_slots[11].in_uop.bits.uses_stq, issue_slots[12].out_uop.uses_stq
connect issue_slots[11].in_uop.bits.uses_ldq, issue_slots[12].out_uop.uses_ldq
connect issue_slots[11].in_uop.bits.mem_signed, issue_slots[12].out_uop.mem_signed
connect issue_slots[11].in_uop.bits.mem_size, issue_slots[12].out_uop.mem_size
connect issue_slots[11].in_uop.bits.mem_cmd, issue_slots[12].out_uop.mem_cmd
connect issue_slots[11].in_uop.bits.exc_cause, issue_slots[12].out_uop.exc_cause
connect issue_slots[11].in_uop.bits.exception, issue_slots[12].out_uop.exception
connect issue_slots[11].in_uop.bits.stale_pdst, issue_slots[12].out_uop.stale_pdst
connect issue_slots[11].in_uop.bits.ppred_busy, issue_slots[12].out_uop.ppred_busy
connect issue_slots[11].in_uop.bits.prs3_busy, issue_slots[12].out_uop.prs3_busy
connect issue_slots[11].in_uop.bits.prs2_busy, issue_slots[12].out_uop.prs2_busy
connect issue_slots[11].in_uop.bits.prs1_busy, issue_slots[12].out_uop.prs1_busy
connect issue_slots[11].in_uop.bits.ppred, issue_slots[12].out_uop.ppred
connect issue_slots[11].in_uop.bits.prs3, issue_slots[12].out_uop.prs3
connect issue_slots[11].in_uop.bits.prs2, issue_slots[12].out_uop.prs2
connect issue_slots[11].in_uop.bits.prs1, issue_slots[12].out_uop.prs1
connect issue_slots[11].in_uop.bits.pdst, issue_slots[12].out_uop.pdst
connect issue_slots[11].in_uop.bits.rxq_idx, issue_slots[12].out_uop.rxq_idx
connect issue_slots[11].in_uop.bits.stq_idx, issue_slots[12].out_uop.stq_idx
connect issue_slots[11].in_uop.bits.ldq_idx, issue_slots[12].out_uop.ldq_idx
connect issue_slots[11].in_uop.bits.rob_idx, issue_slots[12].out_uop.rob_idx
connect issue_slots[11].in_uop.bits.fp_ctrl.vec, issue_slots[12].out_uop.fp_ctrl.vec
connect issue_slots[11].in_uop.bits.fp_ctrl.wflags, issue_slots[12].out_uop.fp_ctrl.wflags
connect issue_slots[11].in_uop.bits.fp_ctrl.sqrt, issue_slots[12].out_uop.fp_ctrl.sqrt
connect issue_slots[11].in_uop.bits.fp_ctrl.div, issue_slots[12].out_uop.fp_ctrl.div
connect issue_slots[11].in_uop.bits.fp_ctrl.fma, issue_slots[12].out_uop.fp_ctrl.fma
connect issue_slots[11].in_uop.bits.fp_ctrl.fastpipe, issue_slots[12].out_uop.fp_ctrl.fastpipe
connect issue_slots[11].in_uop.bits.fp_ctrl.toint, issue_slots[12].out_uop.fp_ctrl.toint
connect issue_slots[11].in_uop.bits.fp_ctrl.fromint, issue_slots[12].out_uop.fp_ctrl.fromint
connect issue_slots[11].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[12].out_uop.fp_ctrl.typeTagOut
connect issue_slots[11].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[12].out_uop.fp_ctrl.typeTagIn
connect issue_slots[11].in_uop.bits.fp_ctrl.swap23, issue_slots[12].out_uop.fp_ctrl.swap23
connect issue_slots[11].in_uop.bits.fp_ctrl.swap12, issue_slots[12].out_uop.fp_ctrl.swap12
connect issue_slots[11].in_uop.bits.fp_ctrl.ren3, issue_slots[12].out_uop.fp_ctrl.ren3
connect issue_slots[11].in_uop.bits.fp_ctrl.ren2, issue_slots[12].out_uop.fp_ctrl.ren2
connect issue_slots[11].in_uop.bits.fp_ctrl.ren1, issue_slots[12].out_uop.fp_ctrl.ren1
connect issue_slots[11].in_uop.bits.fp_ctrl.wen, issue_slots[12].out_uop.fp_ctrl.wen
connect issue_slots[11].in_uop.bits.fp_ctrl.ldst, issue_slots[12].out_uop.fp_ctrl.ldst
connect issue_slots[11].in_uop.bits.op2_sel, issue_slots[12].out_uop.op2_sel
connect issue_slots[11].in_uop.bits.op1_sel, issue_slots[12].out_uop.op1_sel
connect issue_slots[11].in_uop.bits.imm_packed, issue_slots[12].out_uop.imm_packed
connect issue_slots[11].in_uop.bits.pimm, issue_slots[12].out_uop.pimm
connect issue_slots[11].in_uop.bits.imm_sel, issue_slots[12].out_uop.imm_sel
connect issue_slots[11].in_uop.bits.imm_rename, issue_slots[12].out_uop.imm_rename
connect issue_slots[11].in_uop.bits.taken, issue_slots[12].out_uop.taken
connect issue_slots[11].in_uop.bits.pc_lob, issue_slots[12].out_uop.pc_lob
connect issue_slots[11].in_uop.bits.edge_inst, issue_slots[12].out_uop.edge_inst
connect issue_slots[11].in_uop.bits.ftq_idx, issue_slots[12].out_uop.ftq_idx
connect issue_slots[11].in_uop.bits.is_mov, issue_slots[12].out_uop.is_mov
connect issue_slots[11].in_uop.bits.is_rocc, issue_slots[12].out_uop.is_rocc
connect issue_slots[11].in_uop.bits.is_sys_pc2epc, issue_slots[12].out_uop.is_sys_pc2epc
connect issue_slots[11].in_uop.bits.is_eret, issue_slots[12].out_uop.is_eret
connect issue_slots[11].in_uop.bits.is_amo, issue_slots[12].out_uop.is_amo
connect issue_slots[11].in_uop.bits.is_sfence, issue_slots[12].out_uop.is_sfence
connect issue_slots[11].in_uop.bits.is_fencei, issue_slots[12].out_uop.is_fencei
connect issue_slots[11].in_uop.bits.is_fence, issue_slots[12].out_uop.is_fence
connect issue_slots[11].in_uop.bits.is_sfb, issue_slots[12].out_uop.is_sfb
connect issue_slots[11].in_uop.bits.br_type, issue_slots[12].out_uop.br_type
connect issue_slots[11].in_uop.bits.br_tag, issue_slots[12].out_uop.br_tag
connect issue_slots[11].in_uop.bits.br_mask, issue_slots[12].out_uop.br_mask
connect issue_slots[11].in_uop.bits.dis_col_sel, issue_slots[12].out_uop.dis_col_sel
connect issue_slots[11].in_uop.bits.iw_p3_bypass_hint, issue_slots[12].out_uop.iw_p3_bypass_hint
connect issue_slots[11].in_uop.bits.iw_p2_bypass_hint, issue_slots[12].out_uop.iw_p2_bypass_hint
connect issue_slots[11].in_uop.bits.iw_p1_bypass_hint, issue_slots[12].out_uop.iw_p1_bypass_hint
connect issue_slots[11].in_uop.bits.iw_p2_speculative_child, issue_slots[12].out_uop.iw_p2_speculative_child
connect issue_slots[11].in_uop.bits.iw_p1_speculative_child, issue_slots[12].out_uop.iw_p1_speculative_child
connect issue_slots[11].in_uop.bits.iw_issued_partial_dgen, issue_slots[12].out_uop.iw_issued_partial_dgen
connect issue_slots[11].in_uop.bits.iw_issued_partial_agen, issue_slots[12].out_uop.iw_issued_partial_agen
connect issue_slots[11].in_uop.bits.iw_issued, issue_slots[12].out_uop.iw_issued
connect issue_slots[11].in_uop.bits.fu_code[0], issue_slots[12].out_uop.fu_code[0]
connect issue_slots[11].in_uop.bits.fu_code[1], issue_slots[12].out_uop.fu_code[1]
connect issue_slots[11].in_uop.bits.fu_code[2], issue_slots[12].out_uop.fu_code[2]
connect issue_slots[11].in_uop.bits.fu_code[3], issue_slots[12].out_uop.fu_code[3]
connect issue_slots[11].in_uop.bits.fu_code[4], issue_slots[12].out_uop.fu_code[4]
connect issue_slots[11].in_uop.bits.fu_code[5], issue_slots[12].out_uop.fu_code[5]
connect issue_slots[11].in_uop.bits.fu_code[6], issue_slots[12].out_uop.fu_code[6]
connect issue_slots[11].in_uop.bits.fu_code[7], issue_slots[12].out_uop.fu_code[7]
connect issue_slots[11].in_uop.bits.fu_code[8], issue_slots[12].out_uop.fu_code[8]
connect issue_slots[11].in_uop.bits.fu_code[9], issue_slots[12].out_uop.fu_code[9]
connect issue_slots[11].in_uop.bits.iq_type[0], issue_slots[12].out_uop.iq_type[0]
connect issue_slots[11].in_uop.bits.iq_type[1], issue_slots[12].out_uop.iq_type[1]
connect issue_slots[11].in_uop.bits.iq_type[2], issue_slots[12].out_uop.iq_type[2]
connect issue_slots[11].in_uop.bits.iq_type[3], issue_slots[12].out_uop.iq_type[3]
connect issue_slots[11].in_uop.bits.debug_pc, issue_slots[12].out_uop.debug_pc
connect issue_slots[11].in_uop.bits.is_rvc, issue_slots[12].out_uop.is_rvc
connect issue_slots[11].in_uop.bits.debug_inst, issue_slots[12].out_uop.debug_inst
connect issue_slots[11].in_uop.bits.inst, issue_slots[12].out_uop.inst
node _T_184 = eq(shamts_oh[12], UInt<1>(0h1))
when _T_184 :
connect issue_slots[11].in_uop.valid, issue_slots[12].will_be_valid
connect issue_slots[11].in_uop.bits.debug_tsrc, issue_slots[12].out_uop.debug_tsrc
connect issue_slots[11].in_uop.bits.debug_fsrc, issue_slots[12].out_uop.debug_fsrc
connect issue_slots[11].in_uop.bits.bp_xcpt_if, issue_slots[12].out_uop.bp_xcpt_if
connect issue_slots[11].in_uop.bits.bp_debug_if, issue_slots[12].out_uop.bp_debug_if
connect issue_slots[11].in_uop.bits.xcpt_ma_if, issue_slots[12].out_uop.xcpt_ma_if
connect issue_slots[11].in_uop.bits.xcpt_ae_if, issue_slots[12].out_uop.xcpt_ae_if
connect issue_slots[11].in_uop.bits.xcpt_pf_if, issue_slots[12].out_uop.xcpt_pf_if
connect issue_slots[11].in_uop.bits.fp_typ, issue_slots[12].out_uop.fp_typ
connect issue_slots[11].in_uop.bits.fp_rm, issue_slots[12].out_uop.fp_rm
connect issue_slots[11].in_uop.bits.fp_val, issue_slots[12].out_uop.fp_val
connect issue_slots[11].in_uop.bits.fcn_op, issue_slots[12].out_uop.fcn_op
connect issue_slots[11].in_uop.bits.fcn_dw, issue_slots[12].out_uop.fcn_dw
connect issue_slots[11].in_uop.bits.frs3_en, issue_slots[12].out_uop.frs3_en
connect issue_slots[11].in_uop.bits.lrs2_rtype, issue_slots[12].out_uop.lrs2_rtype
connect issue_slots[11].in_uop.bits.lrs1_rtype, issue_slots[12].out_uop.lrs1_rtype
connect issue_slots[11].in_uop.bits.dst_rtype, issue_slots[12].out_uop.dst_rtype
connect issue_slots[11].in_uop.bits.lrs3, issue_slots[12].out_uop.lrs3
connect issue_slots[11].in_uop.bits.lrs2, issue_slots[12].out_uop.lrs2
connect issue_slots[11].in_uop.bits.lrs1, issue_slots[12].out_uop.lrs1
connect issue_slots[11].in_uop.bits.ldst, issue_slots[12].out_uop.ldst
connect issue_slots[11].in_uop.bits.ldst_is_rs1, issue_slots[12].out_uop.ldst_is_rs1
connect issue_slots[11].in_uop.bits.csr_cmd, issue_slots[12].out_uop.csr_cmd
connect issue_slots[11].in_uop.bits.flush_on_commit, issue_slots[12].out_uop.flush_on_commit
connect issue_slots[11].in_uop.bits.is_unique, issue_slots[12].out_uop.is_unique
connect issue_slots[11].in_uop.bits.uses_stq, issue_slots[12].out_uop.uses_stq
connect issue_slots[11].in_uop.bits.uses_ldq, issue_slots[12].out_uop.uses_ldq
connect issue_slots[11].in_uop.bits.mem_signed, issue_slots[12].out_uop.mem_signed
connect issue_slots[11].in_uop.bits.mem_size, issue_slots[12].out_uop.mem_size
connect issue_slots[11].in_uop.bits.mem_cmd, issue_slots[12].out_uop.mem_cmd
connect issue_slots[11].in_uop.bits.exc_cause, issue_slots[12].out_uop.exc_cause
connect issue_slots[11].in_uop.bits.exception, issue_slots[12].out_uop.exception
connect issue_slots[11].in_uop.bits.stale_pdst, issue_slots[12].out_uop.stale_pdst
connect issue_slots[11].in_uop.bits.ppred_busy, issue_slots[12].out_uop.ppred_busy
connect issue_slots[11].in_uop.bits.prs3_busy, issue_slots[12].out_uop.prs3_busy
connect issue_slots[11].in_uop.bits.prs2_busy, issue_slots[12].out_uop.prs2_busy
connect issue_slots[11].in_uop.bits.prs1_busy, issue_slots[12].out_uop.prs1_busy
connect issue_slots[11].in_uop.bits.ppred, issue_slots[12].out_uop.ppred
connect issue_slots[11].in_uop.bits.prs3, issue_slots[12].out_uop.prs3
connect issue_slots[11].in_uop.bits.prs2, issue_slots[12].out_uop.prs2
connect issue_slots[11].in_uop.bits.prs1, issue_slots[12].out_uop.prs1
connect issue_slots[11].in_uop.bits.pdst, issue_slots[12].out_uop.pdst
connect issue_slots[11].in_uop.bits.rxq_idx, issue_slots[12].out_uop.rxq_idx
connect issue_slots[11].in_uop.bits.stq_idx, issue_slots[12].out_uop.stq_idx
connect issue_slots[11].in_uop.bits.ldq_idx, issue_slots[12].out_uop.ldq_idx
connect issue_slots[11].in_uop.bits.rob_idx, issue_slots[12].out_uop.rob_idx
connect issue_slots[11].in_uop.bits.fp_ctrl.vec, issue_slots[12].out_uop.fp_ctrl.vec
connect issue_slots[11].in_uop.bits.fp_ctrl.wflags, issue_slots[12].out_uop.fp_ctrl.wflags
connect issue_slots[11].in_uop.bits.fp_ctrl.sqrt, issue_slots[12].out_uop.fp_ctrl.sqrt
connect issue_slots[11].in_uop.bits.fp_ctrl.div, issue_slots[12].out_uop.fp_ctrl.div
connect issue_slots[11].in_uop.bits.fp_ctrl.fma, issue_slots[12].out_uop.fp_ctrl.fma
connect issue_slots[11].in_uop.bits.fp_ctrl.fastpipe, issue_slots[12].out_uop.fp_ctrl.fastpipe
connect issue_slots[11].in_uop.bits.fp_ctrl.toint, issue_slots[12].out_uop.fp_ctrl.toint
connect issue_slots[11].in_uop.bits.fp_ctrl.fromint, issue_slots[12].out_uop.fp_ctrl.fromint
connect issue_slots[11].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[12].out_uop.fp_ctrl.typeTagOut
connect issue_slots[11].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[12].out_uop.fp_ctrl.typeTagIn
connect issue_slots[11].in_uop.bits.fp_ctrl.swap23, issue_slots[12].out_uop.fp_ctrl.swap23
connect issue_slots[11].in_uop.bits.fp_ctrl.swap12, issue_slots[12].out_uop.fp_ctrl.swap12
connect issue_slots[11].in_uop.bits.fp_ctrl.ren3, issue_slots[12].out_uop.fp_ctrl.ren3
connect issue_slots[11].in_uop.bits.fp_ctrl.ren2, issue_slots[12].out_uop.fp_ctrl.ren2
connect issue_slots[11].in_uop.bits.fp_ctrl.ren1, issue_slots[12].out_uop.fp_ctrl.ren1
connect issue_slots[11].in_uop.bits.fp_ctrl.wen, issue_slots[12].out_uop.fp_ctrl.wen
connect issue_slots[11].in_uop.bits.fp_ctrl.ldst, issue_slots[12].out_uop.fp_ctrl.ldst
connect issue_slots[11].in_uop.bits.op2_sel, issue_slots[12].out_uop.op2_sel
connect issue_slots[11].in_uop.bits.op1_sel, issue_slots[12].out_uop.op1_sel
connect issue_slots[11].in_uop.bits.imm_packed, issue_slots[12].out_uop.imm_packed
connect issue_slots[11].in_uop.bits.pimm, issue_slots[12].out_uop.pimm
connect issue_slots[11].in_uop.bits.imm_sel, issue_slots[12].out_uop.imm_sel
connect issue_slots[11].in_uop.bits.imm_rename, issue_slots[12].out_uop.imm_rename
connect issue_slots[11].in_uop.bits.taken, issue_slots[12].out_uop.taken
connect issue_slots[11].in_uop.bits.pc_lob, issue_slots[12].out_uop.pc_lob
connect issue_slots[11].in_uop.bits.edge_inst, issue_slots[12].out_uop.edge_inst
connect issue_slots[11].in_uop.bits.ftq_idx, issue_slots[12].out_uop.ftq_idx
connect issue_slots[11].in_uop.bits.is_mov, issue_slots[12].out_uop.is_mov
connect issue_slots[11].in_uop.bits.is_rocc, issue_slots[12].out_uop.is_rocc
connect issue_slots[11].in_uop.bits.is_sys_pc2epc, issue_slots[12].out_uop.is_sys_pc2epc
connect issue_slots[11].in_uop.bits.is_eret, issue_slots[12].out_uop.is_eret
connect issue_slots[11].in_uop.bits.is_amo, issue_slots[12].out_uop.is_amo
connect issue_slots[11].in_uop.bits.is_sfence, issue_slots[12].out_uop.is_sfence
connect issue_slots[11].in_uop.bits.is_fencei, issue_slots[12].out_uop.is_fencei
connect issue_slots[11].in_uop.bits.is_fence, issue_slots[12].out_uop.is_fence
connect issue_slots[11].in_uop.bits.is_sfb, issue_slots[12].out_uop.is_sfb
connect issue_slots[11].in_uop.bits.br_type, issue_slots[12].out_uop.br_type
connect issue_slots[11].in_uop.bits.br_tag, issue_slots[12].out_uop.br_tag
connect issue_slots[11].in_uop.bits.br_mask, issue_slots[12].out_uop.br_mask
connect issue_slots[11].in_uop.bits.dis_col_sel, issue_slots[12].out_uop.dis_col_sel
connect issue_slots[11].in_uop.bits.iw_p3_bypass_hint, issue_slots[12].out_uop.iw_p3_bypass_hint
connect issue_slots[11].in_uop.bits.iw_p2_bypass_hint, issue_slots[12].out_uop.iw_p2_bypass_hint
connect issue_slots[11].in_uop.bits.iw_p1_bypass_hint, issue_slots[12].out_uop.iw_p1_bypass_hint
connect issue_slots[11].in_uop.bits.iw_p2_speculative_child, issue_slots[12].out_uop.iw_p2_speculative_child
connect issue_slots[11].in_uop.bits.iw_p1_speculative_child, issue_slots[12].out_uop.iw_p1_speculative_child
connect issue_slots[11].in_uop.bits.iw_issued_partial_dgen, issue_slots[12].out_uop.iw_issued_partial_dgen
connect issue_slots[11].in_uop.bits.iw_issued_partial_agen, issue_slots[12].out_uop.iw_issued_partial_agen
connect issue_slots[11].in_uop.bits.iw_issued, issue_slots[12].out_uop.iw_issued
connect issue_slots[11].in_uop.bits.fu_code[0], issue_slots[12].out_uop.fu_code[0]
connect issue_slots[11].in_uop.bits.fu_code[1], issue_slots[12].out_uop.fu_code[1]
connect issue_slots[11].in_uop.bits.fu_code[2], issue_slots[12].out_uop.fu_code[2]
connect issue_slots[11].in_uop.bits.fu_code[3], issue_slots[12].out_uop.fu_code[3]
connect issue_slots[11].in_uop.bits.fu_code[4], issue_slots[12].out_uop.fu_code[4]
connect issue_slots[11].in_uop.bits.fu_code[5], issue_slots[12].out_uop.fu_code[5]
connect issue_slots[11].in_uop.bits.fu_code[6], issue_slots[12].out_uop.fu_code[6]
connect issue_slots[11].in_uop.bits.fu_code[7], issue_slots[12].out_uop.fu_code[7]
connect issue_slots[11].in_uop.bits.fu_code[8], issue_slots[12].out_uop.fu_code[8]
connect issue_slots[11].in_uop.bits.fu_code[9], issue_slots[12].out_uop.fu_code[9]
connect issue_slots[11].in_uop.bits.iq_type[0], issue_slots[12].out_uop.iq_type[0]
connect issue_slots[11].in_uop.bits.iq_type[1], issue_slots[12].out_uop.iq_type[1]
connect issue_slots[11].in_uop.bits.iq_type[2], issue_slots[12].out_uop.iq_type[2]
connect issue_slots[11].in_uop.bits.iq_type[3], issue_slots[12].out_uop.iq_type[3]
connect issue_slots[11].in_uop.bits.debug_pc, issue_slots[12].out_uop.debug_pc
connect issue_slots[11].in_uop.bits.is_rvc, issue_slots[12].out_uop.is_rvc
connect issue_slots[11].in_uop.bits.debug_inst, issue_slots[12].out_uop.debug_inst
connect issue_slots[11].in_uop.bits.inst, issue_slots[12].out_uop.inst
node _T_185 = eq(shamts_oh[13], UInt<2>(0h2))
when _T_185 :
connect issue_slots[11].in_uop.valid, issue_slots[13].will_be_valid
connect issue_slots[11].in_uop.bits.debug_tsrc, issue_slots[13].out_uop.debug_tsrc
connect issue_slots[11].in_uop.bits.debug_fsrc, issue_slots[13].out_uop.debug_fsrc
connect issue_slots[11].in_uop.bits.bp_xcpt_if, issue_slots[13].out_uop.bp_xcpt_if
connect issue_slots[11].in_uop.bits.bp_debug_if, issue_slots[13].out_uop.bp_debug_if
connect issue_slots[11].in_uop.bits.xcpt_ma_if, issue_slots[13].out_uop.xcpt_ma_if
connect issue_slots[11].in_uop.bits.xcpt_ae_if, issue_slots[13].out_uop.xcpt_ae_if
connect issue_slots[11].in_uop.bits.xcpt_pf_if, issue_slots[13].out_uop.xcpt_pf_if
connect issue_slots[11].in_uop.bits.fp_typ, issue_slots[13].out_uop.fp_typ
connect issue_slots[11].in_uop.bits.fp_rm, issue_slots[13].out_uop.fp_rm
connect issue_slots[11].in_uop.bits.fp_val, issue_slots[13].out_uop.fp_val
connect issue_slots[11].in_uop.bits.fcn_op, issue_slots[13].out_uop.fcn_op
connect issue_slots[11].in_uop.bits.fcn_dw, issue_slots[13].out_uop.fcn_dw
connect issue_slots[11].in_uop.bits.frs3_en, issue_slots[13].out_uop.frs3_en
connect issue_slots[11].in_uop.bits.lrs2_rtype, issue_slots[13].out_uop.lrs2_rtype
connect issue_slots[11].in_uop.bits.lrs1_rtype, issue_slots[13].out_uop.lrs1_rtype
connect issue_slots[11].in_uop.bits.dst_rtype, issue_slots[13].out_uop.dst_rtype
connect issue_slots[11].in_uop.bits.lrs3, issue_slots[13].out_uop.lrs3
connect issue_slots[11].in_uop.bits.lrs2, issue_slots[13].out_uop.lrs2
connect issue_slots[11].in_uop.bits.lrs1, issue_slots[13].out_uop.lrs1
connect issue_slots[11].in_uop.bits.ldst, issue_slots[13].out_uop.ldst
connect issue_slots[11].in_uop.bits.ldst_is_rs1, issue_slots[13].out_uop.ldst_is_rs1
connect issue_slots[11].in_uop.bits.csr_cmd, issue_slots[13].out_uop.csr_cmd
connect issue_slots[11].in_uop.bits.flush_on_commit, issue_slots[13].out_uop.flush_on_commit
connect issue_slots[11].in_uop.bits.is_unique, issue_slots[13].out_uop.is_unique
connect issue_slots[11].in_uop.bits.uses_stq, issue_slots[13].out_uop.uses_stq
connect issue_slots[11].in_uop.bits.uses_ldq, issue_slots[13].out_uop.uses_ldq
connect issue_slots[11].in_uop.bits.mem_signed, issue_slots[13].out_uop.mem_signed
connect issue_slots[11].in_uop.bits.mem_size, issue_slots[13].out_uop.mem_size
connect issue_slots[11].in_uop.bits.mem_cmd, issue_slots[13].out_uop.mem_cmd
connect issue_slots[11].in_uop.bits.exc_cause, issue_slots[13].out_uop.exc_cause
connect issue_slots[11].in_uop.bits.exception, issue_slots[13].out_uop.exception
connect issue_slots[11].in_uop.bits.stale_pdst, issue_slots[13].out_uop.stale_pdst
connect issue_slots[11].in_uop.bits.ppred_busy, issue_slots[13].out_uop.ppred_busy
connect issue_slots[11].in_uop.bits.prs3_busy, issue_slots[13].out_uop.prs3_busy
connect issue_slots[11].in_uop.bits.prs2_busy, issue_slots[13].out_uop.prs2_busy
connect issue_slots[11].in_uop.bits.prs1_busy, issue_slots[13].out_uop.prs1_busy
connect issue_slots[11].in_uop.bits.ppred, issue_slots[13].out_uop.ppred
connect issue_slots[11].in_uop.bits.prs3, issue_slots[13].out_uop.prs3
connect issue_slots[11].in_uop.bits.prs2, issue_slots[13].out_uop.prs2
connect issue_slots[11].in_uop.bits.prs1, issue_slots[13].out_uop.prs1
connect issue_slots[11].in_uop.bits.pdst, issue_slots[13].out_uop.pdst
connect issue_slots[11].in_uop.bits.rxq_idx, issue_slots[13].out_uop.rxq_idx
connect issue_slots[11].in_uop.bits.stq_idx, issue_slots[13].out_uop.stq_idx
connect issue_slots[11].in_uop.bits.ldq_idx, issue_slots[13].out_uop.ldq_idx
connect issue_slots[11].in_uop.bits.rob_idx, issue_slots[13].out_uop.rob_idx
connect issue_slots[11].in_uop.bits.fp_ctrl.vec, issue_slots[13].out_uop.fp_ctrl.vec
connect issue_slots[11].in_uop.bits.fp_ctrl.wflags, issue_slots[13].out_uop.fp_ctrl.wflags
connect issue_slots[11].in_uop.bits.fp_ctrl.sqrt, issue_slots[13].out_uop.fp_ctrl.sqrt
connect issue_slots[11].in_uop.bits.fp_ctrl.div, issue_slots[13].out_uop.fp_ctrl.div
connect issue_slots[11].in_uop.bits.fp_ctrl.fma, issue_slots[13].out_uop.fp_ctrl.fma
connect issue_slots[11].in_uop.bits.fp_ctrl.fastpipe, issue_slots[13].out_uop.fp_ctrl.fastpipe
connect issue_slots[11].in_uop.bits.fp_ctrl.toint, issue_slots[13].out_uop.fp_ctrl.toint
connect issue_slots[11].in_uop.bits.fp_ctrl.fromint, issue_slots[13].out_uop.fp_ctrl.fromint
connect issue_slots[11].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[13].out_uop.fp_ctrl.typeTagOut
connect issue_slots[11].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[13].out_uop.fp_ctrl.typeTagIn
connect issue_slots[11].in_uop.bits.fp_ctrl.swap23, issue_slots[13].out_uop.fp_ctrl.swap23
connect issue_slots[11].in_uop.bits.fp_ctrl.swap12, issue_slots[13].out_uop.fp_ctrl.swap12
connect issue_slots[11].in_uop.bits.fp_ctrl.ren3, issue_slots[13].out_uop.fp_ctrl.ren3
connect issue_slots[11].in_uop.bits.fp_ctrl.ren2, issue_slots[13].out_uop.fp_ctrl.ren2
connect issue_slots[11].in_uop.bits.fp_ctrl.ren1, issue_slots[13].out_uop.fp_ctrl.ren1
connect issue_slots[11].in_uop.bits.fp_ctrl.wen, issue_slots[13].out_uop.fp_ctrl.wen
connect issue_slots[11].in_uop.bits.fp_ctrl.ldst, issue_slots[13].out_uop.fp_ctrl.ldst
connect issue_slots[11].in_uop.bits.op2_sel, issue_slots[13].out_uop.op2_sel
connect issue_slots[11].in_uop.bits.op1_sel, issue_slots[13].out_uop.op1_sel
connect issue_slots[11].in_uop.bits.imm_packed, issue_slots[13].out_uop.imm_packed
connect issue_slots[11].in_uop.bits.pimm, issue_slots[13].out_uop.pimm
connect issue_slots[11].in_uop.bits.imm_sel, issue_slots[13].out_uop.imm_sel
connect issue_slots[11].in_uop.bits.imm_rename, issue_slots[13].out_uop.imm_rename
connect issue_slots[11].in_uop.bits.taken, issue_slots[13].out_uop.taken
connect issue_slots[11].in_uop.bits.pc_lob, issue_slots[13].out_uop.pc_lob
connect issue_slots[11].in_uop.bits.edge_inst, issue_slots[13].out_uop.edge_inst
connect issue_slots[11].in_uop.bits.ftq_idx, issue_slots[13].out_uop.ftq_idx
connect issue_slots[11].in_uop.bits.is_mov, issue_slots[13].out_uop.is_mov
connect issue_slots[11].in_uop.bits.is_rocc, issue_slots[13].out_uop.is_rocc
connect issue_slots[11].in_uop.bits.is_sys_pc2epc, issue_slots[13].out_uop.is_sys_pc2epc
connect issue_slots[11].in_uop.bits.is_eret, issue_slots[13].out_uop.is_eret
connect issue_slots[11].in_uop.bits.is_amo, issue_slots[13].out_uop.is_amo
connect issue_slots[11].in_uop.bits.is_sfence, issue_slots[13].out_uop.is_sfence
connect issue_slots[11].in_uop.bits.is_fencei, issue_slots[13].out_uop.is_fencei
connect issue_slots[11].in_uop.bits.is_fence, issue_slots[13].out_uop.is_fence
connect issue_slots[11].in_uop.bits.is_sfb, issue_slots[13].out_uop.is_sfb
connect issue_slots[11].in_uop.bits.br_type, issue_slots[13].out_uop.br_type
connect issue_slots[11].in_uop.bits.br_tag, issue_slots[13].out_uop.br_tag
connect issue_slots[11].in_uop.bits.br_mask, issue_slots[13].out_uop.br_mask
connect issue_slots[11].in_uop.bits.dis_col_sel, issue_slots[13].out_uop.dis_col_sel
connect issue_slots[11].in_uop.bits.iw_p3_bypass_hint, issue_slots[13].out_uop.iw_p3_bypass_hint
connect issue_slots[11].in_uop.bits.iw_p2_bypass_hint, issue_slots[13].out_uop.iw_p2_bypass_hint
connect issue_slots[11].in_uop.bits.iw_p1_bypass_hint, issue_slots[13].out_uop.iw_p1_bypass_hint
connect issue_slots[11].in_uop.bits.iw_p2_speculative_child, issue_slots[13].out_uop.iw_p2_speculative_child
connect issue_slots[11].in_uop.bits.iw_p1_speculative_child, issue_slots[13].out_uop.iw_p1_speculative_child
connect issue_slots[11].in_uop.bits.iw_issued_partial_dgen, issue_slots[13].out_uop.iw_issued_partial_dgen
connect issue_slots[11].in_uop.bits.iw_issued_partial_agen, issue_slots[13].out_uop.iw_issued_partial_agen
connect issue_slots[11].in_uop.bits.iw_issued, issue_slots[13].out_uop.iw_issued
connect issue_slots[11].in_uop.bits.fu_code[0], issue_slots[13].out_uop.fu_code[0]
connect issue_slots[11].in_uop.bits.fu_code[1], issue_slots[13].out_uop.fu_code[1]
connect issue_slots[11].in_uop.bits.fu_code[2], issue_slots[13].out_uop.fu_code[2]
connect issue_slots[11].in_uop.bits.fu_code[3], issue_slots[13].out_uop.fu_code[3]
connect issue_slots[11].in_uop.bits.fu_code[4], issue_slots[13].out_uop.fu_code[4]
connect issue_slots[11].in_uop.bits.fu_code[5], issue_slots[13].out_uop.fu_code[5]
connect issue_slots[11].in_uop.bits.fu_code[6], issue_slots[13].out_uop.fu_code[6]
connect issue_slots[11].in_uop.bits.fu_code[7], issue_slots[13].out_uop.fu_code[7]
connect issue_slots[11].in_uop.bits.fu_code[8], issue_slots[13].out_uop.fu_code[8]
connect issue_slots[11].in_uop.bits.fu_code[9], issue_slots[13].out_uop.fu_code[9]
connect issue_slots[11].in_uop.bits.iq_type[0], issue_slots[13].out_uop.iq_type[0]
connect issue_slots[11].in_uop.bits.iq_type[1], issue_slots[13].out_uop.iq_type[1]
connect issue_slots[11].in_uop.bits.iq_type[2], issue_slots[13].out_uop.iq_type[2]
connect issue_slots[11].in_uop.bits.iq_type[3], issue_slots[13].out_uop.iq_type[3]
connect issue_slots[11].in_uop.bits.debug_pc, issue_slots[13].out_uop.debug_pc
connect issue_slots[11].in_uop.bits.is_rvc, issue_slots[13].out_uop.is_rvc
connect issue_slots[11].in_uop.bits.debug_inst, issue_slots[13].out_uop.debug_inst
connect issue_slots[11].in_uop.bits.inst, issue_slots[13].out_uop.inst
node _issue_slots_11_clear_T = neq(shamts_oh[11], UInt<1>(0h0))
connect issue_slots[11].clear, _issue_slots_11_clear_T
connect issue_slots[12].in_uop.valid, UInt<1>(0h0)
connect issue_slots[12].in_uop.bits.debug_tsrc, issue_slots[13].out_uop.debug_tsrc
connect issue_slots[12].in_uop.bits.debug_fsrc, issue_slots[13].out_uop.debug_fsrc
connect issue_slots[12].in_uop.bits.bp_xcpt_if, issue_slots[13].out_uop.bp_xcpt_if
connect issue_slots[12].in_uop.bits.bp_debug_if, issue_slots[13].out_uop.bp_debug_if
connect issue_slots[12].in_uop.bits.xcpt_ma_if, issue_slots[13].out_uop.xcpt_ma_if
connect issue_slots[12].in_uop.bits.xcpt_ae_if, issue_slots[13].out_uop.xcpt_ae_if
connect issue_slots[12].in_uop.bits.xcpt_pf_if, issue_slots[13].out_uop.xcpt_pf_if
connect issue_slots[12].in_uop.bits.fp_typ, issue_slots[13].out_uop.fp_typ
connect issue_slots[12].in_uop.bits.fp_rm, issue_slots[13].out_uop.fp_rm
connect issue_slots[12].in_uop.bits.fp_val, issue_slots[13].out_uop.fp_val
connect issue_slots[12].in_uop.bits.fcn_op, issue_slots[13].out_uop.fcn_op
connect issue_slots[12].in_uop.bits.fcn_dw, issue_slots[13].out_uop.fcn_dw
connect issue_slots[12].in_uop.bits.frs3_en, issue_slots[13].out_uop.frs3_en
connect issue_slots[12].in_uop.bits.lrs2_rtype, issue_slots[13].out_uop.lrs2_rtype
connect issue_slots[12].in_uop.bits.lrs1_rtype, issue_slots[13].out_uop.lrs1_rtype
connect issue_slots[12].in_uop.bits.dst_rtype, issue_slots[13].out_uop.dst_rtype
connect issue_slots[12].in_uop.bits.lrs3, issue_slots[13].out_uop.lrs3
connect issue_slots[12].in_uop.bits.lrs2, issue_slots[13].out_uop.lrs2
connect issue_slots[12].in_uop.bits.lrs1, issue_slots[13].out_uop.lrs1
connect issue_slots[12].in_uop.bits.ldst, issue_slots[13].out_uop.ldst
connect issue_slots[12].in_uop.bits.ldst_is_rs1, issue_slots[13].out_uop.ldst_is_rs1
connect issue_slots[12].in_uop.bits.csr_cmd, issue_slots[13].out_uop.csr_cmd
connect issue_slots[12].in_uop.bits.flush_on_commit, issue_slots[13].out_uop.flush_on_commit
connect issue_slots[12].in_uop.bits.is_unique, issue_slots[13].out_uop.is_unique
connect issue_slots[12].in_uop.bits.uses_stq, issue_slots[13].out_uop.uses_stq
connect issue_slots[12].in_uop.bits.uses_ldq, issue_slots[13].out_uop.uses_ldq
connect issue_slots[12].in_uop.bits.mem_signed, issue_slots[13].out_uop.mem_signed
connect issue_slots[12].in_uop.bits.mem_size, issue_slots[13].out_uop.mem_size
connect issue_slots[12].in_uop.bits.mem_cmd, issue_slots[13].out_uop.mem_cmd
connect issue_slots[12].in_uop.bits.exc_cause, issue_slots[13].out_uop.exc_cause
connect issue_slots[12].in_uop.bits.exception, issue_slots[13].out_uop.exception
connect issue_slots[12].in_uop.bits.stale_pdst, issue_slots[13].out_uop.stale_pdst
connect issue_slots[12].in_uop.bits.ppred_busy, issue_slots[13].out_uop.ppred_busy
connect issue_slots[12].in_uop.bits.prs3_busy, issue_slots[13].out_uop.prs3_busy
connect issue_slots[12].in_uop.bits.prs2_busy, issue_slots[13].out_uop.prs2_busy
connect issue_slots[12].in_uop.bits.prs1_busy, issue_slots[13].out_uop.prs1_busy
connect issue_slots[12].in_uop.bits.ppred, issue_slots[13].out_uop.ppred
connect issue_slots[12].in_uop.bits.prs3, issue_slots[13].out_uop.prs3
connect issue_slots[12].in_uop.bits.prs2, issue_slots[13].out_uop.prs2
connect issue_slots[12].in_uop.bits.prs1, issue_slots[13].out_uop.prs1
connect issue_slots[12].in_uop.bits.pdst, issue_slots[13].out_uop.pdst
connect issue_slots[12].in_uop.bits.rxq_idx, issue_slots[13].out_uop.rxq_idx
connect issue_slots[12].in_uop.bits.stq_idx, issue_slots[13].out_uop.stq_idx
connect issue_slots[12].in_uop.bits.ldq_idx, issue_slots[13].out_uop.ldq_idx
connect issue_slots[12].in_uop.bits.rob_idx, issue_slots[13].out_uop.rob_idx
connect issue_slots[12].in_uop.bits.fp_ctrl.vec, issue_slots[13].out_uop.fp_ctrl.vec
connect issue_slots[12].in_uop.bits.fp_ctrl.wflags, issue_slots[13].out_uop.fp_ctrl.wflags
connect issue_slots[12].in_uop.bits.fp_ctrl.sqrt, issue_slots[13].out_uop.fp_ctrl.sqrt
connect issue_slots[12].in_uop.bits.fp_ctrl.div, issue_slots[13].out_uop.fp_ctrl.div
connect issue_slots[12].in_uop.bits.fp_ctrl.fma, issue_slots[13].out_uop.fp_ctrl.fma
connect issue_slots[12].in_uop.bits.fp_ctrl.fastpipe, issue_slots[13].out_uop.fp_ctrl.fastpipe
connect issue_slots[12].in_uop.bits.fp_ctrl.toint, issue_slots[13].out_uop.fp_ctrl.toint
connect issue_slots[12].in_uop.bits.fp_ctrl.fromint, issue_slots[13].out_uop.fp_ctrl.fromint
connect issue_slots[12].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[13].out_uop.fp_ctrl.typeTagOut
connect issue_slots[12].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[13].out_uop.fp_ctrl.typeTagIn
connect issue_slots[12].in_uop.bits.fp_ctrl.swap23, issue_slots[13].out_uop.fp_ctrl.swap23
connect issue_slots[12].in_uop.bits.fp_ctrl.swap12, issue_slots[13].out_uop.fp_ctrl.swap12
connect issue_slots[12].in_uop.bits.fp_ctrl.ren3, issue_slots[13].out_uop.fp_ctrl.ren3
connect issue_slots[12].in_uop.bits.fp_ctrl.ren2, issue_slots[13].out_uop.fp_ctrl.ren2
connect issue_slots[12].in_uop.bits.fp_ctrl.ren1, issue_slots[13].out_uop.fp_ctrl.ren1
connect issue_slots[12].in_uop.bits.fp_ctrl.wen, issue_slots[13].out_uop.fp_ctrl.wen
connect issue_slots[12].in_uop.bits.fp_ctrl.ldst, issue_slots[13].out_uop.fp_ctrl.ldst
connect issue_slots[12].in_uop.bits.op2_sel, issue_slots[13].out_uop.op2_sel
connect issue_slots[12].in_uop.bits.op1_sel, issue_slots[13].out_uop.op1_sel
connect issue_slots[12].in_uop.bits.imm_packed, issue_slots[13].out_uop.imm_packed
connect issue_slots[12].in_uop.bits.pimm, issue_slots[13].out_uop.pimm
connect issue_slots[12].in_uop.bits.imm_sel, issue_slots[13].out_uop.imm_sel
connect issue_slots[12].in_uop.bits.imm_rename, issue_slots[13].out_uop.imm_rename
connect issue_slots[12].in_uop.bits.taken, issue_slots[13].out_uop.taken
connect issue_slots[12].in_uop.bits.pc_lob, issue_slots[13].out_uop.pc_lob
connect issue_slots[12].in_uop.bits.edge_inst, issue_slots[13].out_uop.edge_inst
connect issue_slots[12].in_uop.bits.ftq_idx, issue_slots[13].out_uop.ftq_idx
connect issue_slots[12].in_uop.bits.is_mov, issue_slots[13].out_uop.is_mov
connect issue_slots[12].in_uop.bits.is_rocc, issue_slots[13].out_uop.is_rocc
connect issue_slots[12].in_uop.bits.is_sys_pc2epc, issue_slots[13].out_uop.is_sys_pc2epc
connect issue_slots[12].in_uop.bits.is_eret, issue_slots[13].out_uop.is_eret
connect issue_slots[12].in_uop.bits.is_amo, issue_slots[13].out_uop.is_amo
connect issue_slots[12].in_uop.bits.is_sfence, issue_slots[13].out_uop.is_sfence
connect issue_slots[12].in_uop.bits.is_fencei, issue_slots[13].out_uop.is_fencei
connect issue_slots[12].in_uop.bits.is_fence, issue_slots[13].out_uop.is_fence
connect issue_slots[12].in_uop.bits.is_sfb, issue_slots[13].out_uop.is_sfb
connect issue_slots[12].in_uop.bits.br_type, issue_slots[13].out_uop.br_type
connect issue_slots[12].in_uop.bits.br_tag, issue_slots[13].out_uop.br_tag
connect issue_slots[12].in_uop.bits.br_mask, issue_slots[13].out_uop.br_mask
connect issue_slots[12].in_uop.bits.dis_col_sel, issue_slots[13].out_uop.dis_col_sel
connect issue_slots[12].in_uop.bits.iw_p3_bypass_hint, issue_slots[13].out_uop.iw_p3_bypass_hint
connect issue_slots[12].in_uop.bits.iw_p2_bypass_hint, issue_slots[13].out_uop.iw_p2_bypass_hint
connect issue_slots[12].in_uop.bits.iw_p1_bypass_hint, issue_slots[13].out_uop.iw_p1_bypass_hint
connect issue_slots[12].in_uop.bits.iw_p2_speculative_child, issue_slots[13].out_uop.iw_p2_speculative_child
connect issue_slots[12].in_uop.bits.iw_p1_speculative_child, issue_slots[13].out_uop.iw_p1_speculative_child
connect issue_slots[12].in_uop.bits.iw_issued_partial_dgen, issue_slots[13].out_uop.iw_issued_partial_dgen
connect issue_slots[12].in_uop.bits.iw_issued_partial_agen, issue_slots[13].out_uop.iw_issued_partial_agen
connect issue_slots[12].in_uop.bits.iw_issued, issue_slots[13].out_uop.iw_issued
connect issue_slots[12].in_uop.bits.fu_code[0], issue_slots[13].out_uop.fu_code[0]
connect issue_slots[12].in_uop.bits.fu_code[1], issue_slots[13].out_uop.fu_code[1]
connect issue_slots[12].in_uop.bits.fu_code[2], issue_slots[13].out_uop.fu_code[2]
connect issue_slots[12].in_uop.bits.fu_code[3], issue_slots[13].out_uop.fu_code[3]
connect issue_slots[12].in_uop.bits.fu_code[4], issue_slots[13].out_uop.fu_code[4]
connect issue_slots[12].in_uop.bits.fu_code[5], issue_slots[13].out_uop.fu_code[5]
connect issue_slots[12].in_uop.bits.fu_code[6], issue_slots[13].out_uop.fu_code[6]
connect issue_slots[12].in_uop.bits.fu_code[7], issue_slots[13].out_uop.fu_code[7]
connect issue_slots[12].in_uop.bits.fu_code[8], issue_slots[13].out_uop.fu_code[8]
connect issue_slots[12].in_uop.bits.fu_code[9], issue_slots[13].out_uop.fu_code[9]
connect issue_slots[12].in_uop.bits.iq_type[0], issue_slots[13].out_uop.iq_type[0]
connect issue_slots[12].in_uop.bits.iq_type[1], issue_slots[13].out_uop.iq_type[1]
connect issue_slots[12].in_uop.bits.iq_type[2], issue_slots[13].out_uop.iq_type[2]
connect issue_slots[12].in_uop.bits.iq_type[3], issue_slots[13].out_uop.iq_type[3]
connect issue_slots[12].in_uop.bits.debug_pc, issue_slots[13].out_uop.debug_pc
connect issue_slots[12].in_uop.bits.is_rvc, issue_slots[13].out_uop.is_rvc
connect issue_slots[12].in_uop.bits.debug_inst, issue_slots[13].out_uop.debug_inst
connect issue_slots[12].in_uop.bits.inst, issue_slots[13].out_uop.inst
node _T_186 = eq(shamts_oh[13], UInt<1>(0h1))
when _T_186 :
connect issue_slots[12].in_uop.valid, issue_slots[13].will_be_valid
connect issue_slots[12].in_uop.bits.debug_tsrc, issue_slots[13].out_uop.debug_tsrc
connect issue_slots[12].in_uop.bits.debug_fsrc, issue_slots[13].out_uop.debug_fsrc
connect issue_slots[12].in_uop.bits.bp_xcpt_if, issue_slots[13].out_uop.bp_xcpt_if
connect issue_slots[12].in_uop.bits.bp_debug_if, issue_slots[13].out_uop.bp_debug_if
connect issue_slots[12].in_uop.bits.xcpt_ma_if, issue_slots[13].out_uop.xcpt_ma_if
connect issue_slots[12].in_uop.bits.xcpt_ae_if, issue_slots[13].out_uop.xcpt_ae_if
connect issue_slots[12].in_uop.bits.xcpt_pf_if, issue_slots[13].out_uop.xcpt_pf_if
connect issue_slots[12].in_uop.bits.fp_typ, issue_slots[13].out_uop.fp_typ
connect issue_slots[12].in_uop.bits.fp_rm, issue_slots[13].out_uop.fp_rm
connect issue_slots[12].in_uop.bits.fp_val, issue_slots[13].out_uop.fp_val
connect issue_slots[12].in_uop.bits.fcn_op, issue_slots[13].out_uop.fcn_op
connect issue_slots[12].in_uop.bits.fcn_dw, issue_slots[13].out_uop.fcn_dw
connect issue_slots[12].in_uop.bits.frs3_en, issue_slots[13].out_uop.frs3_en
connect issue_slots[12].in_uop.bits.lrs2_rtype, issue_slots[13].out_uop.lrs2_rtype
connect issue_slots[12].in_uop.bits.lrs1_rtype, issue_slots[13].out_uop.lrs1_rtype
connect issue_slots[12].in_uop.bits.dst_rtype, issue_slots[13].out_uop.dst_rtype
connect issue_slots[12].in_uop.bits.lrs3, issue_slots[13].out_uop.lrs3
connect issue_slots[12].in_uop.bits.lrs2, issue_slots[13].out_uop.lrs2
connect issue_slots[12].in_uop.bits.lrs1, issue_slots[13].out_uop.lrs1
connect issue_slots[12].in_uop.bits.ldst, issue_slots[13].out_uop.ldst
connect issue_slots[12].in_uop.bits.ldst_is_rs1, issue_slots[13].out_uop.ldst_is_rs1
connect issue_slots[12].in_uop.bits.csr_cmd, issue_slots[13].out_uop.csr_cmd
connect issue_slots[12].in_uop.bits.flush_on_commit, issue_slots[13].out_uop.flush_on_commit
connect issue_slots[12].in_uop.bits.is_unique, issue_slots[13].out_uop.is_unique
connect issue_slots[12].in_uop.bits.uses_stq, issue_slots[13].out_uop.uses_stq
connect issue_slots[12].in_uop.bits.uses_ldq, issue_slots[13].out_uop.uses_ldq
connect issue_slots[12].in_uop.bits.mem_signed, issue_slots[13].out_uop.mem_signed
connect issue_slots[12].in_uop.bits.mem_size, issue_slots[13].out_uop.mem_size
connect issue_slots[12].in_uop.bits.mem_cmd, issue_slots[13].out_uop.mem_cmd
connect issue_slots[12].in_uop.bits.exc_cause, issue_slots[13].out_uop.exc_cause
connect issue_slots[12].in_uop.bits.exception, issue_slots[13].out_uop.exception
connect issue_slots[12].in_uop.bits.stale_pdst, issue_slots[13].out_uop.stale_pdst
connect issue_slots[12].in_uop.bits.ppred_busy, issue_slots[13].out_uop.ppred_busy
connect issue_slots[12].in_uop.bits.prs3_busy, issue_slots[13].out_uop.prs3_busy
connect issue_slots[12].in_uop.bits.prs2_busy, issue_slots[13].out_uop.prs2_busy
connect issue_slots[12].in_uop.bits.prs1_busy, issue_slots[13].out_uop.prs1_busy
connect issue_slots[12].in_uop.bits.ppred, issue_slots[13].out_uop.ppred
connect issue_slots[12].in_uop.bits.prs3, issue_slots[13].out_uop.prs3
connect issue_slots[12].in_uop.bits.prs2, issue_slots[13].out_uop.prs2
connect issue_slots[12].in_uop.bits.prs1, issue_slots[13].out_uop.prs1
connect issue_slots[12].in_uop.bits.pdst, issue_slots[13].out_uop.pdst
connect issue_slots[12].in_uop.bits.rxq_idx, issue_slots[13].out_uop.rxq_idx
connect issue_slots[12].in_uop.bits.stq_idx, issue_slots[13].out_uop.stq_idx
connect issue_slots[12].in_uop.bits.ldq_idx, issue_slots[13].out_uop.ldq_idx
connect issue_slots[12].in_uop.bits.rob_idx, issue_slots[13].out_uop.rob_idx
connect issue_slots[12].in_uop.bits.fp_ctrl.vec, issue_slots[13].out_uop.fp_ctrl.vec
connect issue_slots[12].in_uop.bits.fp_ctrl.wflags, issue_slots[13].out_uop.fp_ctrl.wflags
connect issue_slots[12].in_uop.bits.fp_ctrl.sqrt, issue_slots[13].out_uop.fp_ctrl.sqrt
connect issue_slots[12].in_uop.bits.fp_ctrl.div, issue_slots[13].out_uop.fp_ctrl.div
connect issue_slots[12].in_uop.bits.fp_ctrl.fma, issue_slots[13].out_uop.fp_ctrl.fma
connect issue_slots[12].in_uop.bits.fp_ctrl.fastpipe, issue_slots[13].out_uop.fp_ctrl.fastpipe
connect issue_slots[12].in_uop.bits.fp_ctrl.toint, issue_slots[13].out_uop.fp_ctrl.toint
connect issue_slots[12].in_uop.bits.fp_ctrl.fromint, issue_slots[13].out_uop.fp_ctrl.fromint
connect issue_slots[12].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[13].out_uop.fp_ctrl.typeTagOut
connect issue_slots[12].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[13].out_uop.fp_ctrl.typeTagIn
connect issue_slots[12].in_uop.bits.fp_ctrl.swap23, issue_slots[13].out_uop.fp_ctrl.swap23
connect issue_slots[12].in_uop.bits.fp_ctrl.swap12, issue_slots[13].out_uop.fp_ctrl.swap12
connect issue_slots[12].in_uop.bits.fp_ctrl.ren3, issue_slots[13].out_uop.fp_ctrl.ren3
connect issue_slots[12].in_uop.bits.fp_ctrl.ren2, issue_slots[13].out_uop.fp_ctrl.ren2
connect issue_slots[12].in_uop.bits.fp_ctrl.ren1, issue_slots[13].out_uop.fp_ctrl.ren1
connect issue_slots[12].in_uop.bits.fp_ctrl.wen, issue_slots[13].out_uop.fp_ctrl.wen
connect issue_slots[12].in_uop.bits.fp_ctrl.ldst, issue_slots[13].out_uop.fp_ctrl.ldst
connect issue_slots[12].in_uop.bits.op2_sel, issue_slots[13].out_uop.op2_sel
connect issue_slots[12].in_uop.bits.op1_sel, issue_slots[13].out_uop.op1_sel
connect issue_slots[12].in_uop.bits.imm_packed, issue_slots[13].out_uop.imm_packed
connect issue_slots[12].in_uop.bits.pimm, issue_slots[13].out_uop.pimm
connect issue_slots[12].in_uop.bits.imm_sel, issue_slots[13].out_uop.imm_sel
connect issue_slots[12].in_uop.bits.imm_rename, issue_slots[13].out_uop.imm_rename
connect issue_slots[12].in_uop.bits.taken, issue_slots[13].out_uop.taken
connect issue_slots[12].in_uop.bits.pc_lob, issue_slots[13].out_uop.pc_lob
connect issue_slots[12].in_uop.bits.edge_inst, issue_slots[13].out_uop.edge_inst
connect issue_slots[12].in_uop.bits.ftq_idx, issue_slots[13].out_uop.ftq_idx
connect issue_slots[12].in_uop.bits.is_mov, issue_slots[13].out_uop.is_mov
connect issue_slots[12].in_uop.bits.is_rocc, issue_slots[13].out_uop.is_rocc
connect issue_slots[12].in_uop.bits.is_sys_pc2epc, issue_slots[13].out_uop.is_sys_pc2epc
connect issue_slots[12].in_uop.bits.is_eret, issue_slots[13].out_uop.is_eret
connect issue_slots[12].in_uop.bits.is_amo, issue_slots[13].out_uop.is_amo
connect issue_slots[12].in_uop.bits.is_sfence, issue_slots[13].out_uop.is_sfence
connect issue_slots[12].in_uop.bits.is_fencei, issue_slots[13].out_uop.is_fencei
connect issue_slots[12].in_uop.bits.is_fence, issue_slots[13].out_uop.is_fence
connect issue_slots[12].in_uop.bits.is_sfb, issue_slots[13].out_uop.is_sfb
connect issue_slots[12].in_uop.bits.br_type, issue_slots[13].out_uop.br_type
connect issue_slots[12].in_uop.bits.br_tag, issue_slots[13].out_uop.br_tag
connect issue_slots[12].in_uop.bits.br_mask, issue_slots[13].out_uop.br_mask
connect issue_slots[12].in_uop.bits.dis_col_sel, issue_slots[13].out_uop.dis_col_sel
connect issue_slots[12].in_uop.bits.iw_p3_bypass_hint, issue_slots[13].out_uop.iw_p3_bypass_hint
connect issue_slots[12].in_uop.bits.iw_p2_bypass_hint, issue_slots[13].out_uop.iw_p2_bypass_hint
connect issue_slots[12].in_uop.bits.iw_p1_bypass_hint, issue_slots[13].out_uop.iw_p1_bypass_hint
connect issue_slots[12].in_uop.bits.iw_p2_speculative_child, issue_slots[13].out_uop.iw_p2_speculative_child
connect issue_slots[12].in_uop.bits.iw_p1_speculative_child, issue_slots[13].out_uop.iw_p1_speculative_child
connect issue_slots[12].in_uop.bits.iw_issued_partial_dgen, issue_slots[13].out_uop.iw_issued_partial_dgen
connect issue_slots[12].in_uop.bits.iw_issued_partial_agen, issue_slots[13].out_uop.iw_issued_partial_agen
connect issue_slots[12].in_uop.bits.iw_issued, issue_slots[13].out_uop.iw_issued
connect issue_slots[12].in_uop.bits.fu_code[0], issue_slots[13].out_uop.fu_code[0]
connect issue_slots[12].in_uop.bits.fu_code[1], issue_slots[13].out_uop.fu_code[1]
connect issue_slots[12].in_uop.bits.fu_code[2], issue_slots[13].out_uop.fu_code[2]
connect issue_slots[12].in_uop.bits.fu_code[3], issue_slots[13].out_uop.fu_code[3]
connect issue_slots[12].in_uop.bits.fu_code[4], issue_slots[13].out_uop.fu_code[4]
connect issue_slots[12].in_uop.bits.fu_code[5], issue_slots[13].out_uop.fu_code[5]
connect issue_slots[12].in_uop.bits.fu_code[6], issue_slots[13].out_uop.fu_code[6]
connect issue_slots[12].in_uop.bits.fu_code[7], issue_slots[13].out_uop.fu_code[7]
connect issue_slots[12].in_uop.bits.fu_code[8], issue_slots[13].out_uop.fu_code[8]
connect issue_slots[12].in_uop.bits.fu_code[9], issue_slots[13].out_uop.fu_code[9]
connect issue_slots[12].in_uop.bits.iq_type[0], issue_slots[13].out_uop.iq_type[0]
connect issue_slots[12].in_uop.bits.iq_type[1], issue_slots[13].out_uop.iq_type[1]
connect issue_slots[12].in_uop.bits.iq_type[2], issue_slots[13].out_uop.iq_type[2]
connect issue_slots[12].in_uop.bits.iq_type[3], issue_slots[13].out_uop.iq_type[3]
connect issue_slots[12].in_uop.bits.debug_pc, issue_slots[13].out_uop.debug_pc
connect issue_slots[12].in_uop.bits.is_rvc, issue_slots[13].out_uop.is_rvc
connect issue_slots[12].in_uop.bits.debug_inst, issue_slots[13].out_uop.debug_inst
connect issue_slots[12].in_uop.bits.inst, issue_slots[13].out_uop.inst
node _T_187 = eq(shamts_oh[14], UInt<2>(0h2))
when _T_187 :
connect issue_slots[12].in_uop.valid, issue_slots[14].will_be_valid
connect issue_slots[12].in_uop.bits.debug_tsrc, issue_slots[14].out_uop.debug_tsrc
connect issue_slots[12].in_uop.bits.debug_fsrc, issue_slots[14].out_uop.debug_fsrc
connect issue_slots[12].in_uop.bits.bp_xcpt_if, issue_slots[14].out_uop.bp_xcpt_if
connect issue_slots[12].in_uop.bits.bp_debug_if, issue_slots[14].out_uop.bp_debug_if
connect issue_slots[12].in_uop.bits.xcpt_ma_if, issue_slots[14].out_uop.xcpt_ma_if
connect issue_slots[12].in_uop.bits.xcpt_ae_if, issue_slots[14].out_uop.xcpt_ae_if
connect issue_slots[12].in_uop.bits.xcpt_pf_if, issue_slots[14].out_uop.xcpt_pf_if
connect issue_slots[12].in_uop.bits.fp_typ, issue_slots[14].out_uop.fp_typ
connect issue_slots[12].in_uop.bits.fp_rm, issue_slots[14].out_uop.fp_rm
connect issue_slots[12].in_uop.bits.fp_val, issue_slots[14].out_uop.fp_val
connect issue_slots[12].in_uop.bits.fcn_op, issue_slots[14].out_uop.fcn_op
connect issue_slots[12].in_uop.bits.fcn_dw, issue_slots[14].out_uop.fcn_dw
connect issue_slots[12].in_uop.bits.frs3_en, issue_slots[14].out_uop.frs3_en
connect issue_slots[12].in_uop.bits.lrs2_rtype, issue_slots[14].out_uop.lrs2_rtype
connect issue_slots[12].in_uop.bits.lrs1_rtype, issue_slots[14].out_uop.lrs1_rtype
connect issue_slots[12].in_uop.bits.dst_rtype, issue_slots[14].out_uop.dst_rtype
connect issue_slots[12].in_uop.bits.lrs3, issue_slots[14].out_uop.lrs3
connect issue_slots[12].in_uop.bits.lrs2, issue_slots[14].out_uop.lrs2
connect issue_slots[12].in_uop.bits.lrs1, issue_slots[14].out_uop.lrs1
connect issue_slots[12].in_uop.bits.ldst, issue_slots[14].out_uop.ldst
connect issue_slots[12].in_uop.bits.ldst_is_rs1, issue_slots[14].out_uop.ldst_is_rs1
connect issue_slots[12].in_uop.bits.csr_cmd, issue_slots[14].out_uop.csr_cmd
connect issue_slots[12].in_uop.bits.flush_on_commit, issue_slots[14].out_uop.flush_on_commit
connect issue_slots[12].in_uop.bits.is_unique, issue_slots[14].out_uop.is_unique
connect issue_slots[12].in_uop.bits.uses_stq, issue_slots[14].out_uop.uses_stq
connect issue_slots[12].in_uop.bits.uses_ldq, issue_slots[14].out_uop.uses_ldq
connect issue_slots[12].in_uop.bits.mem_signed, issue_slots[14].out_uop.mem_signed
connect issue_slots[12].in_uop.bits.mem_size, issue_slots[14].out_uop.mem_size
connect issue_slots[12].in_uop.bits.mem_cmd, issue_slots[14].out_uop.mem_cmd
connect issue_slots[12].in_uop.bits.exc_cause, issue_slots[14].out_uop.exc_cause
connect issue_slots[12].in_uop.bits.exception, issue_slots[14].out_uop.exception
connect issue_slots[12].in_uop.bits.stale_pdst, issue_slots[14].out_uop.stale_pdst
connect issue_slots[12].in_uop.bits.ppred_busy, issue_slots[14].out_uop.ppred_busy
connect issue_slots[12].in_uop.bits.prs3_busy, issue_slots[14].out_uop.prs3_busy
connect issue_slots[12].in_uop.bits.prs2_busy, issue_slots[14].out_uop.prs2_busy
connect issue_slots[12].in_uop.bits.prs1_busy, issue_slots[14].out_uop.prs1_busy
connect issue_slots[12].in_uop.bits.ppred, issue_slots[14].out_uop.ppred
connect issue_slots[12].in_uop.bits.prs3, issue_slots[14].out_uop.prs3
connect issue_slots[12].in_uop.bits.prs2, issue_slots[14].out_uop.prs2
connect issue_slots[12].in_uop.bits.prs1, issue_slots[14].out_uop.prs1
connect issue_slots[12].in_uop.bits.pdst, issue_slots[14].out_uop.pdst
connect issue_slots[12].in_uop.bits.rxq_idx, issue_slots[14].out_uop.rxq_idx
connect issue_slots[12].in_uop.bits.stq_idx, issue_slots[14].out_uop.stq_idx
connect issue_slots[12].in_uop.bits.ldq_idx, issue_slots[14].out_uop.ldq_idx
connect issue_slots[12].in_uop.bits.rob_idx, issue_slots[14].out_uop.rob_idx
connect issue_slots[12].in_uop.bits.fp_ctrl.vec, issue_slots[14].out_uop.fp_ctrl.vec
connect issue_slots[12].in_uop.bits.fp_ctrl.wflags, issue_slots[14].out_uop.fp_ctrl.wflags
connect issue_slots[12].in_uop.bits.fp_ctrl.sqrt, issue_slots[14].out_uop.fp_ctrl.sqrt
connect issue_slots[12].in_uop.bits.fp_ctrl.div, issue_slots[14].out_uop.fp_ctrl.div
connect issue_slots[12].in_uop.bits.fp_ctrl.fma, issue_slots[14].out_uop.fp_ctrl.fma
connect issue_slots[12].in_uop.bits.fp_ctrl.fastpipe, issue_slots[14].out_uop.fp_ctrl.fastpipe
connect issue_slots[12].in_uop.bits.fp_ctrl.toint, issue_slots[14].out_uop.fp_ctrl.toint
connect issue_slots[12].in_uop.bits.fp_ctrl.fromint, issue_slots[14].out_uop.fp_ctrl.fromint
connect issue_slots[12].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[14].out_uop.fp_ctrl.typeTagOut
connect issue_slots[12].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[14].out_uop.fp_ctrl.typeTagIn
connect issue_slots[12].in_uop.bits.fp_ctrl.swap23, issue_slots[14].out_uop.fp_ctrl.swap23
connect issue_slots[12].in_uop.bits.fp_ctrl.swap12, issue_slots[14].out_uop.fp_ctrl.swap12
connect issue_slots[12].in_uop.bits.fp_ctrl.ren3, issue_slots[14].out_uop.fp_ctrl.ren3
connect issue_slots[12].in_uop.bits.fp_ctrl.ren2, issue_slots[14].out_uop.fp_ctrl.ren2
connect issue_slots[12].in_uop.bits.fp_ctrl.ren1, issue_slots[14].out_uop.fp_ctrl.ren1
connect issue_slots[12].in_uop.bits.fp_ctrl.wen, issue_slots[14].out_uop.fp_ctrl.wen
connect issue_slots[12].in_uop.bits.fp_ctrl.ldst, issue_slots[14].out_uop.fp_ctrl.ldst
connect issue_slots[12].in_uop.bits.op2_sel, issue_slots[14].out_uop.op2_sel
connect issue_slots[12].in_uop.bits.op1_sel, issue_slots[14].out_uop.op1_sel
connect issue_slots[12].in_uop.bits.imm_packed, issue_slots[14].out_uop.imm_packed
connect issue_slots[12].in_uop.bits.pimm, issue_slots[14].out_uop.pimm
connect issue_slots[12].in_uop.bits.imm_sel, issue_slots[14].out_uop.imm_sel
connect issue_slots[12].in_uop.bits.imm_rename, issue_slots[14].out_uop.imm_rename
connect issue_slots[12].in_uop.bits.taken, issue_slots[14].out_uop.taken
connect issue_slots[12].in_uop.bits.pc_lob, issue_slots[14].out_uop.pc_lob
connect issue_slots[12].in_uop.bits.edge_inst, issue_slots[14].out_uop.edge_inst
connect issue_slots[12].in_uop.bits.ftq_idx, issue_slots[14].out_uop.ftq_idx
connect issue_slots[12].in_uop.bits.is_mov, issue_slots[14].out_uop.is_mov
connect issue_slots[12].in_uop.bits.is_rocc, issue_slots[14].out_uop.is_rocc
connect issue_slots[12].in_uop.bits.is_sys_pc2epc, issue_slots[14].out_uop.is_sys_pc2epc
connect issue_slots[12].in_uop.bits.is_eret, issue_slots[14].out_uop.is_eret
connect issue_slots[12].in_uop.bits.is_amo, issue_slots[14].out_uop.is_amo
connect issue_slots[12].in_uop.bits.is_sfence, issue_slots[14].out_uop.is_sfence
connect issue_slots[12].in_uop.bits.is_fencei, issue_slots[14].out_uop.is_fencei
connect issue_slots[12].in_uop.bits.is_fence, issue_slots[14].out_uop.is_fence
connect issue_slots[12].in_uop.bits.is_sfb, issue_slots[14].out_uop.is_sfb
connect issue_slots[12].in_uop.bits.br_type, issue_slots[14].out_uop.br_type
connect issue_slots[12].in_uop.bits.br_tag, issue_slots[14].out_uop.br_tag
connect issue_slots[12].in_uop.bits.br_mask, issue_slots[14].out_uop.br_mask
connect issue_slots[12].in_uop.bits.dis_col_sel, issue_slots[14].out_uop.dis_col_sel
connect issue_slots[12].in_uop.bits.iw_p3_bypass_hint, issue_slots[14].out_uop.iw_p3_bypass_hint
connect issue_slots[12].in_uop.bits.iw_p2_bypass_hint, issue_slots[14].out_uop.iw_p2_bypass_hint
connect issue_slots[12].in_uop.bits.iw_p1_bypass_hint, issue_slots[14].out_uop.iw_p1_bypass_hint
connect issue_slots[12].in_uop.bits.iw_p2_speculative_child, issue_slots[14].out_uop.iw_p2_speculative_child
connect issue_slots[12].in_uop.bits.iw_p1_speculative_child, issue_slots[14].out_uop.iw_p1_speculative_child
connect issue_slots[12].in_uop.bits.iw_issued_partial_dgen, issue_slots[14].out_uop.iw_issued_partial_dgen
connect issue_slots[12].in_uop.bits.iw_issued_partial_agen, issue_slots[14].out_uop.iw_issued_partial_agen
connect issue_slots[12].in_uop.bits.iw_issued, issue_slots[14].out_uop.iw_issued
connect issue_slots[12].in_uop.bits.fu_code[0], issue_slots[14].out_uop.fu_code[0]
connect issue_slots[12].in_uop.bits.fu_code[1], issue_slots[14].out_uop.fu_code[1]
connect issue_slots[12].in_uop.bits.fu_code[2], issue_slots[14].out_uop.fu_code[2]
connect issue_slots[12].in_uop.bits.fu_code[3], issue_slots[14].out_uop.fu_code[3]
connect issue_slots[12].in_uop.bits.fu_code[4], issue_slots[14].out_uop.fu_code[4]
connect issue_slots[12].in_uop.bits.fu_code[5], issue_slots[14].out_uop.fu_code[5]
connect issue_slots[12].in_uop.bits.fu_code[6], issue_slots[14].out_uop.fu_code[6]
connect issue_slots[12].in_uop.bits.fu_code[7], issue_slots[14].out_uop.fu_code[7]
connect issue_slots[12].in_uop.bits.fu_code[8], issue_slots[14].out_uop.fu_code[8]
connect issue_slots[12].in_uop.bits.fu_code[9], issue_slots[14].out_uop.fu_code[9]
connect issue_slots[12].in_uop.bits.iq_type[0], issue_slots[14].out_uop.iq_type[0]
connect issue_slots[12].in_uop.bits.iq_type[1], issue_slots[14].out_uop.iq_type[1]
connect issue_slots[12].in_uop.bits.iq_type[2], issue_slots[14].out_uop.iq_type[2]
connect issue_slots[12].in_uop.bits.iq_type[3], issue_slots[14].out_uop.iq_type[3]
connect issue_slots[12].in_uop.bits.debug_pc, issue_slots[14].out_uop.debug_pc
connect issue_slots[12].in_uop.bits.is_rvc, issue_slots[14].out_uop.is_rvc
connect issue_slots[12].in_uop.bits.debug_inst, issue_slots[14].out_uop.debug_inst
connect issue_slots[12].in_uop.bits.inst, issue_slots[14].out_uop.inst
node _issue_slots_12_clear_T = neq(shamts_oh[12], UInt<1>(0h0))
connect issue_slots[12].clear, _issue_slots_12_clear_T
connect issue_slots[13].in_uop.valid, UInt<1>(0h0)
connect issue_slots[13].in_uop.bits.debug_tsrc, issue_slots[14].out_uop.debug_tsrc
connect issue_slots[13].in_uop.bits.debug_fsrc, issue_slots[14].out_uop.debug_fsrc
connect issue_slots[13].in_uop.bits.bp_xcpt_if, issue_slots[14].out_uop.bp_xcpt_if
connect issue_slots[13].in_uop.bits.bp_debug_if, issue_slots[14].out_uop.bp_debug_if
connect issue_slots[13].in_uop.bits.xcpt_ma_if, issue_slots[14].out_uop.xcpt_ma_if
connect issue_slots[13].in_uop.bits.xcpt_ae_if, issue_slots[14].out_uop.xcpt_ae_if
connect issue_slots[13].in_uop.bits.xcpt_pf_if, issue_slots[14].out_uop.xcpt_pf_if
connect issue_slots[13].in_uop.bits.fp_typ, issue_slots[14].out_uop.fp_typ
connect issue_slots[13].in_uop.bits.fp_rm, issue_slots[14].out_uop.fp_rm
connect issue_slots[13].in_uop.bits.fp_val, issue_slots[14].out_uop.fp_val
connect issue_slots[13].in_uop.bits.fcn_op, issue_slots[14].out_uop.fcn_op
connect issue_slots[13].in_uop.bits.fcn_dw, issue_slots[14].out_uop.fcn_dw
connect issue_slots[13].in_uop.bits.frs3_en, issue_slots[14].out_uop.frs3_en
connect issue_slots[13].in_uop.bits.lrs2_rtype, issue_slots[14].out_uop.lrs2_rtype
connect issue_slots[13].in_uop.bits.lrs1_rtype, issue_slots[14].out_uop.lrs1_rtype
connect issue_slots[13].in_uop.bits.dst_rtype, issue_slots[14].out_uop.dst_rtype
connect issue_slots[13].in_uop.bits.lrs3, issue_slots[14].out_uop.lrs3
connect issue_slots[13].in_uop.bits.lrs2, issue_slots[14].out_uop.lrs2
connect issue_slots[13].in_uop.bits.lrs1, issue_slots[14].out_uop.lrs1
connect issue_slots[13].in_uop.bits.ldst, issue_slots[14].out_uop.ldst
connect issue_slots[13].in_uop.bits.ldst_is_rs1, issue_slots[14].out_uop.ldst_is_rs1
connect issue_slots[13].in_uop.bits.csr_cmd, issue_slots[14].out_uop.csr_cmd
connect issue_slots[13].in_uop.bits.flush_on_commit, issue_slots[14].out_uop.flush_on_commit
connect issue_slots[13].in_uop.bits.is_unique, issue_slots[14].out_uop.is_unique
connect issue_slots[13].in_uop.bits.uses_stq, issue_slots[14].out_uop.uses_stq
connect issue_slots[13].in_uop.bits.uses_ldq, issue_slots[14].out_uop.uses_ldq
connect issue_slots[13].in_uop.bits.mem_signed, issue_slots[14].out_uop.mem_signed
connect issue_slots[13].in_uop.bits.mem_size, issue_slots[14].out_uop.mem_size
connect issue_slots[13].in_uop.bits.mem_cmd, issue_slots[14].out_uop.mem_cmd
connect issue_slots[13].in_uop.bits.exc_cause, issue_slots[14].out_uop.exc_cause
connect issue_slots[13].in_uop.bits.exception, issue_slots[14].out_uop.exception
connect issue_slots[13].in_uop.bits.stale_pdst, issue_slots[14].out_uop.stale_pdst
connect issue_slots[13].in_uop.bits.ppred_busy, issue_slots[14].out_uop.ppred_busy
connect issue_slots[13].in_uop.bits.prs3_busy, issue_slots[14].out_uop.prs3_busy
connect issue_slots[13].in_uop.bits.prs2_busy, issue_slots[14].out_uop.prs2_busy
connect issue_slots[13].in_uop.bits.prs1_busy, issue_slots[14].out_uop.prs1_busy
connect issue_slots[13].in_uop.bits.ppred, issue_slots[14].out_uop.ppred
connect issue_slots[13].in_uop.bits.prs3, issue_slots[14].out_uop.prs3
connect issue_slots[13].in_uop.bits.prs2, issue_slots[14].out_uop.prs2
connect issue_slots[13].in_uop.bits.prs1, issue_slots[14].out_uop.prs1
connect issue_slots[13].in_uop.bits.pdst, issue_slots[14].out_uop.pdst
connect issue_slots[13].in_uop.bits.rxq_idx, issue_slots[14].out_uop.rxq_idx
connect issue_slots[13].in_uop.bits.stq_idx, issue_slots[14].out_uop.stq_idx
connect issue_slots[13].in_uop.bits.ldq_idx, issue_slots[14].out_uop.ldq_idx
connect issue_slots[13].in_uop.bits.rob_idx, issue_slots[14].out_uop.rob_idx
connect issue_slots[13].in_uop.bits.fp_ctrl.vec, issue_slots[14].out_uop.fp_ctrl.vec
connect issue_slots[13].in_uop.bits.fp_ctrl.wflags, issue_slots[14].out_uop.fp_ctrl.wflags
connect issue_slots[13].in_uop.bits.fp_ctrl.sqrt, issue_slots[14].out_uop.fp_ctrl.sqrt
connect issue_slots[13].in_uop.bits.fp_ctrl.div, issue_slots[14].out_uop.fp_ctrl.div
connect issue_slots[13].in_uop.bits.fp_ctrl.fma, issue_slots[14].out_uop.fp_ctrl.fma
connect issue_slots[13].in_uop.bits.fp_ctrl.fastpipe, issue_slots[14].out_uop.fp_ctrl.fastpipe
connect issue_slots[13].in_uop.bits.fp_ctrl.toint, issue_slots[14].out_uop.fp_ctrl.toint
connect issue_slots[13].in_uop.bits.fp_ctrl.fromint, issue_slots[14].out_uop.fp_ctrl.fromint
connect issue_slots[13].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[14].out_uop.fp_ctrl.typeTagOut
connect issue_slots[13].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[14].out_uop.fp_ctrl.typeTagIn
connect issue_slots[13].in_uop.bits.fp_ctrl.swap23, issue_slots[14].out_uop.fp_ctrl.swap23
connect issue_slots[13].in_uop.bits.fp_ctrl.swap12, issue_slots[14].out_uop.fp_ctrl.swap12
connect issue_slots[13].in_uop.bits.fp_ctrl.ren3, issue_slots[14].out_uop.fp_ctrl.ren3
connect issue_slots[13].in_uop.bits.fp_ctrl.ren2, issue_slots[14].out_uop.fp_ctrl.ren2
connect issue_slots[13].in_uop.bits.fp_ctrl.ren1, issue_slots[14].out_uop.fp_ctrl.ren1
connect issue_slots[13].in_uop.bits.fp_ctrl.wen, issue_slots[14].out_uop.fp_ctrl.wen
connect issue_slots[13].in_uop.bits.fp_ctrl.ldst, issue_slots[14].out_uop.fp_ctrl.ldst
connect issue_slots[13].in_uop.bits.op2_sel, issue_slots[14].out_uop.op2_sel
connect issue_slots[13].in_uop.bits.op1_sel, issue_slots[14].out_uop.op1_sel
connect issue_slots[13].in_uop.bits.imm_packed, issue_slots[14].out_uop.imm_packed
connect issue_slots[13].in_uop.bits.pimm, issue_slots[14].out_uop.pimm
connect issue_slots[13].in_uop.bits.imm_sel, issue_slots[14].out_uop.imm_sel
connect issue_slots[13].in_uop.bits.imm_rename, issue_slots[14].out_uop.imm_rename
connect issue_slots[13].in_uop.bits.taken, issue_slots[14].out_uop.taken
connect issue_slots[13].in_uop.bits.pc_lob, issue_slots[14].out_uop.pc_lob
connect issue_slots[13].in_uop.bits.edge_inst, issue_slots[14].out_uop.edge_inst
connect issue_slots[13].in_uop.bits.ftq_idx, issue_slots[14].out_uop.ftq_idx
connect issue_slots[13].in_uop.bits.is_mov, issue_slots[14].out_uop.is_mov
connect issue_slots[13].in_uop.bits.is_rocc, issue_slots[14].out_uop.is_rocc
connect issue_slots[13].in_uop.bits.is_sys_pc2epc, issue_slots[14].out_uop.is_sys_pc2epc
connect issue_slots[13].in_uop.bits.is_eret, issue_slots[14].out_uop.is_eret
connect issue_slots[13].in_uop.bits.is_amo, issue_slots[14].out_uop.is_amo
connect issue_slots[13].in_uop.bits.is_sfence, issue_slots[14].out_uop.is_sfence
connect issue_slots[13].in_uop.bits.is_fencei, issue_slots[14].out_uop.is_fencei
connect issue_slots[13].in_uop.bits.is_fence, issue_slots[14].out_uop.is_fence
connect issue_slots[13].in_uop.bits.is_sfb, issue_slots[14].out_uop.is_sfb
connect issue_slots[13].in_uop.bits.br_type, issue_slots[14].out_uop.br_type
connect issue_slots[13].in_uop.bits.br_tag, issue_slots[14].out_uop.br_tag
connect issue_slots[13].in_uop.bits.br_mask, issue_slots[14].out_uop.br_mask
connect issue_slots[13].in_uop.bits.dis_col_sel, issue_slots[14].out_uop.dis_col_sel
connect issue_slots[13].in_uop.bits.iw_p3_bypass_hint, issue_slots[14].out_uop.iw_p3_bypass_hint
connect issue_slots[13].in_uop.bits.iw_p2_bypass_hint, issue_slots[14].out_uop.iw_p2_bypass_hint
connect issue_slots[13].in_uop.bits.iw_p1_bypass_hint, issue_slots[14].out_uop.iw_p1_bypass_hint
connect issue_slots[13].in_uop.bits.iw_p2_speculative_child, issue_slots[14].out_uop.iw_p2_speculative_child
connect issue_slots[13].in_uop.bits.iw_p1_speculative_child, issue_slots[14].out_uop.iw_p1_speculative_child
connect issue_slots[13].in_uop.bits.iw_issued_partial_dgen, issue_slots[14].out_uop.iw_issued_partial_dgen
connect issue_slots[13].in_uop.bits.iw_issued_partial_agen, issue_slots[14].out_uop.iw_issued_partial_agen
connect issue_slots[13].in_uop.bits.iw_issued, issue_slots[14].out_uop.iw_issued
connect issue_slots[13].in_uop.bits.fu_code[0], issue_slots[14].out_uop.fu_code[0]
connect issue_slots[13].in_uop.bits.fu_code[1], issue_slots[14].out_uop.fu_code[1]
connect issue_slots[13].in_uop.bits.fu_code[2], issue_slots[14].out_uop.fu_code[2]
connect issue_slots[13].in_uop.bits.fu_code[3], issue_slots[14].out_uop.fu_code[3]
connect issue_slots[13].in_uop.bits.fu_code[4], issue_slots[14].out_uop.fu_code[4]
connect issue_slots[13].in_uop.bits.fu_code[5], issue_slots[14].out_uop.fu_code[5]
connect issue_slots[13].in_uop.bits.fu_code[6], issue_slots[14].out_uop.fu_code[6]
connect issue_slots[13].in_uop.bits.fu_code[7], issue_slots[14].out_uop.fu_code[7]
connect issue_slots[13].in_uop.bits.fu_code[8], issue_slots[14].out_uop.fu_code[8]
connect issue_slots[13].in_uop.bits.fu_code[9], issue_slots[14].out_uop.fu_code[9]
connect issue_slots[13].in_uop.bits.iq_type[0], issue_slots[14].out_uop.iq_type[0]
connect issue_slots[13].in_uop.bits.iq_type[1], issue_slots[14].out_uop.iq_type[1]
connect issue_slots[13].in_uop.bits.iq_type[2], issue_slots[14].out_uop.iq_type[2]
connect issue_slots[13].in_uop.bits.iq_type[3], issue_slots[14].out_uop.iq_type[3]
connect issue_slots[13].in_uop.bits.debug_pc, issue_slots[14].out_uop.debug_pc
connect issue_slots[13].in_uop.bits.is_rvc, issue_slots[14].out_uop.is_rvc
connect issue_slots[13].in_uop.bits.debug_inst, issue_slots[14].out_uop.debug_inst
connect issue_slots[13].in_uop.bits.inst, issue_slots[14].out_uop.inst
node _T_188 = eq(shamts_oh[14], UInt<1>(0h1))
when _T_188 :
connect issue_slots[13].in_uop.valid, issue_slots[14].will_be_valid
connect issue_slots[13].in_uop.bits.debug_tsrc, issue_slots[14].out_uop.debug_tsrc
connect issue_slots[13].in_uop.bits.debug_fsrc, issue_slots[14].out_uop.debug_fsrc
connect issue_slots[13].in_uop.bits.bp_xcpt_if, issue_slots[14].out_uop.bp_xcpt_if
connect issue_slots[13].in_uop.bits.bp_debug_if, issue_slots[14].out_uop.bp_debug_if
connect issue_slots[13].in_uop.bits.xcpt_ma_if, issue_slots[14].out_uop.xcpt_ma_if
connect issue_slots[13].in_uop.bits.xcpt_ae_if, issue_slots[14].out_uop.xcpt_ae_if
connect issue_slots[13].in_uop.bits.xcpt_pf_if, issue_slots[14].out_uop.xcpt_pf_if
connect issue_slots[13].in_uop.bits.fp_typ, issue_slots[14].out_uop.fp_typ
connect issue_slots[13].in_uop.bits.fp_rm, issue_slots[14].out_uop.fp_rm
connect issue_slots[13].in_uop.bits.fp_val, issue_slots[14].out_uop.fp_val
connect issue_slots[13].in_uop.bits.fcn_op, issue_slots[14].out_uop.fcn_op
connect issue_slots[13].in_uop.bits.fcn_dw, issue_slots[14].out_uop.fcn_dw
connect issue_slots[13].in_uop.bits.frs3_en, issue_slots[14].out_uop.frs3_en
connect issue_slots[13].in_uop.bits.lrs2_rtype, issue_slots[14].out_uop.lrs2_rtype
connect issue_slots[13].in_uop.bits.lrs1_rtype, issue_slots[14].out_uop.lrs1_rtype
connect issue_slots[13].in_uop.bits.dst_rtype, issue_slots[14].out_uop.dst_rtype
connect issue_slots[13].in_uop.bits.lrs3, issue_slots[14].out_uop.lrs3
connect issue_slots[13].in_uop.bits.lrs2, issue_slots[14].out_uop.lrs2
connect issue_slots[13].in_uop.bits.lrs1, issue_slots[14].out_uop.lrs1
connect issue_slots[13].in_uop.bits.ldst, issue_slots[14].out_uop.ldst
connect issue_slots[13].in_uop.bits.ldst_is_rs1, issue_slots[14].out_uop.ldst_is_rs1
connect issue_slots[13].in_uop.bits.csr_cmd, issue_slots[14].out_uop.csr_cmd
connect issue_slots[13].in_uop.bits.flush_on_commit, issue_slots[14].out_uop.flush_on_commit
connect issue_slots[13].in_uop.bits.is_unique, issue_slots[14].out_uop.is_unique
connect issue_slots[13].in_uop.bits.uses_stq, issue_slots[14].out_uop.uses_stq
connect issue_slots[13].in_uop.bits.uses_ldq, issue_slots[14].out_uop.uses_ldq
connect issue_slots[13].in_uop.bits.mem_signed, issue_slots[14].out_uop.mem_signed
connect issue_slots[13].in_uop.bits.mem_size, issue_slots[14].out_uop.mem_size
connect issue_slots[13].in_uop.bits.mem_cmd, issue_slots[14].out_uop.mem_cmd
connect issue_slots[13].in_uop.bits.exc_cause, issue_slots[14].out_uop.exc_cause
connect issue_slots[13].in_uop.bits.exception, issue_slots[14].out_uop.exception
connect issue_slots[13].in_uop.bits.stale_pdst, issue_slots[14].out_uop.stale_pdst
connect issue_slots[13].in_uop.bits.ppred_busy, issue_slots[14].out_uop.ppred_busy
connect issue_slots[13].in_uop.bits.prs3_busy, issue_slots[14].out_uop.prs3_busy
connect issue_slots[13].in_uop.bits.prs2_busy, issue_slots[14].out_uop.prs2_busy
connect issue_slots[13].in_uop.bits.prs1_busy, issue_slots[14].out_uop.prs1_busy
connect issue_slots[13].in_uop.bits.ppred, issue_slots[14].out_uop.ppred
connect issue_slots[13].in_uop.bits.prs3, issue_slots[14].out_uop.prs3
connect issue_slots[13].in_uop.bits.prs2, issue_slots[14].out_uop.prs2
connect issue_slots[13].in_uop.bits.prs1, issue_slots[14].out_uop.prs1
connect issue_slots[13].in_uop.bits.pdst, issue_slots[14].out_uop.pdst
connect issue_slots[13].in_uop.bits.rxq_idx, issue_slots[14].out_uop.rxq_idx
connect issue_slots[13].in_uop.bits.stq_idx, issue_slots[14].out_uop.stq_idx
connect issue_slots[13].in_uop.bits.ldq_idx, issue_slots[14].out_uop.ldq_idx
connect issue_slots[13].in_uop.bits.rob_idx, issue_slots[14].out_uop.rob_idx
connect issue_slots[13].in_uop.bits.fp_ctrl.vec, issue_slots[14].out_uop.fp_ctrl.vec
connect issue_slots[13].in_uop.bits.fp_ctrl.wflags, issue_slots[14].out_uop.fp_ctrl.wflags
connect issue_slots[13].in_uop.bits.fp_ctrl.sqrt, issue_slots[14].out_uop.fp_ctrl.sqrt
connect issue_slots[13].in_uop.bits.fp_ctrl.div, issue_slots[14].out_uop.fp_ctrl.div
connect issue_slots[13].in_uop.bits.fp_ctrl.fma, issue_slots[14].out_uop.fp_ctrl.fma
connect issue_slots[13].in_uop.bits.fp_ctrl.fastpipe, issue_slots[14].out_uop.fp_ctrl.fastpipe
connect issue_slots[13].in_uop.bits.fp_ctrl.toint, issue_slots[14].out_uop.fp_ctrl.toint
connect issue_slots[13].in_uop.bits.fp_ctrl.fromint, issue_slots[14].out_uop.fp_ctrl.fromint
connect issue_slots[13].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[14].out_uop.fp_ctrl.typeTagOut
connect issue_slots[13].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[14].out_uop.fp_ctrl.typeTagIn
connect issue_slots[13].in_uop.bits.fp_ctrl.swap23, issue_slots[14].out_uop.fp_ctrl.swap23
connect issue_slots[13].in_uop.bits.fp_ctrl.swap12, issue_slots[14].out_uop.fp_ctrl.swap12
connect issue_slots[13].in_uop.bits.fp_ctrl.ren3, issue_slots[14].out_uop.fp_ctrl.ren3
connect issue_slots[13].in_uop.bits.fp_ctrl.ren2, issue_slots[14].out_uop.fp_ctrl.ren2
connect issue_slots[13].in_uop.bits.fp_ctrl.ren1, issue_slots[14].out_uop.fp_ctrl.ren1
connect issue_slots[13].in_uop.bits.fp_ctrl.wen, issue_slots[14].out_uop.fp_ctrl.wen
connect issue_slots[13].in_uop.bits.fp_ctrl.ldst, issue_slots[14].out_uop.fp_ctrl.ldst
connect issue_slots[13].in_uop.bits.op2_sel, issue_slots[14].out_uop.op2_sel
connect issue_slots[13].in_uop.bits.op1_sel, issue_slots[14].out_uop.op1_sel
connect issue_slots[13].in_uop.bits.imm_packed, issue_slots[14].out_uop.imm_packed
connect issue_slots[13].in_uop.bits.pimm, issue_slots[14].out_uop.pimm
connect issue_slots[13].in_uop.bits.imm_sel, issue_slots[14].out_uop.imm_sel
connect issue_slots[13].in_uop.bits.imm_rename, issue_slots[14].out_uop.imm_rename
connect issue_slots[13].in_uop.bits.taken, issue_slots[14].out_uop.taken
connect issue_slots[13].in_uop.bits.pc_lob, issue_slots[14].out_uop.pc_lob
connect issue_slots[13].in_uop.bits.edge_inst, issue_slots[14].out_uop.edge_inst
connect issue_slots[13].in_uop.bits.ftq_idx, issue_slots[14].out_uop.ftq_idx
connect issue_slots[13].in_uop.bits.is_mov, issue_slots[14].out_uop.is_mov
connect issue_slots[13].in_uop.bits.is_rocc, issue_slots[14].out_uop.is_rocc
connect issue_slots[13].in_uop.bits.is_sys_pc2epc, issue_slots[14].out_uop.is_sys_pc2epc
connect issue_slots[13].in_uop.bits.is_eret, issue_slots[14].out_uop.is_eret
connect issue_slots[13].in_uop.bits.is_amo, issue_slots[14].out_uop.is_amo
connect issue_slots[13].in_uop.bits.is_sfence, issue_slots[14].out_uop.is_sfence
connect issue_slots[13].in_uop.bits.is_fencei, issue_slots[14].out_uop.is_fencei
connect issue_slots[13].in_uop.bits.is_fence, issue_slots[14].out_uop.is_fence
connect issue_slots[13].in_uop.bits.is_sfb, issue_slots[14].out_uop.is_sfb
connect issue_slots[13].in_uop.bits.br_type, issue_slots[14].out_uop.br_type
connect issue_slots[13].in_uop.bits.br_tag, issue_slots[14].out_uop.br_tag
connect issue_slots[13].in_uop.bits.br_mask, issue_slots[14].out_uop.br_mask
connect issue_slots[13].in_uop.bits.dis_col_sel, issue_slots[14].out_uop.dis_col_sel
connect issue_slots[13].in_uop.bits.iw_p3_bypass_hint, issue_slots[14].out_uop.iw_p3_bypass_hint
connect issue_slots[13].in_uop.bits.iw_p2_bypass_hint, issue_slots[14].out_uop.iw_p2_bypass_hint
connect issue_slots[13].in_uop.bits.iw_p1_bypass_hint, issue_slots[14].out_uop.iw_p1_bypass_hint
connect issue_slots[13].in_uop.bits.iw_p2_speculative_child, issue_slots[14].out_uop.iw_p2_speculative_child
connect issue_slots[13].in_uop.bits.iw_p1_speculative_child, issue_slots[14].out_uop.iw_p1_speculative_child
connect issue_slots[13].in_uop.bits.iw_issued_partial_dgen, issue_slots[14].out_uop.iw_issued_partial_dgen
connect issue_slots[13].in_uop.bits.iw_issued_partial_agen, issue_slots[14].out_uop.iw_issued_partial_agen
connect issue_slots[13].in_uop.bits.iw_issued, issue_slots[14].out_uop.iw_issued
connect issue_slots[13].in_uop.bits.fu_code[0], issue_slots[14].out_uop.fu_code[0]
connect issue_slots[13].in_uop.bits.fu_code[1], issue_slots[14].out_uop.fu_code[1]
connect issue_slots[13].in_uop.bits.fu_code[2], issue_slots[14].out_uop.fu_code[2]
connect issue_slots[13].in_uop.bits.fu_code[3], issue_slots[14].out_uop.fu_code[3]
connect issue_slots[13].in_uop.bits.fu_code[4], issue_slots[14].out_uop.fu_code[4]
connect issue_slots[13].in_uop.bits.fu_code[5], issue_slots[14].out_uop.fu_code[5]
connect issue_slots[13].in_uop.bits.fu_code[6], issue_slots[14].out_uop.fu_code[6]
connect issue_slots[13].in_uop.bits.fu_code[7], issue_slots[14].out_uop.fu_code[7]
connect issue_slots[13].in_uop.bits.fu_code[8], issue_slots[14].out_uop.fu_code[8]
connect issue_slots[13].in_uop.bits.fu_code[9], issue_slots[14].out_uop.fu_code[9]
connect issue_slots[13].in_uop.bits.iq_type[0], issue_slots[14].out_uop.iq_type[0]
connect issue_slots[13].in_uop.bits.iq_type[1], issue_slots[14].out_uop.iq_type[1]
connect issue_slots[13].in_uop.bits.iq_type[2], issue_slots[14].out_uop.iq_type[2]
connect issue_slots[13].in_uop.bits.iq_type[3], issue_slots[14].out_uop.iq_type[3]
connect issue_slots[13].in_uop.bits.debug_pc, issue_slots[14].out_uop.debug_pc
connect issue_slots[13].in_uop.bits.is_rvc, issue_slots[14].out_uop.is_rvc
connect issue_slots[13].in_uop.bits.debug_inst, issue_slots[14].out_uop.debug_inst
connect issue_slots[13].in_uop.bits.inst, issue_slots[14].out_uop.inst
node _T_189 = eq(shamts_oh[15], UInt<2>(0h2))
when _T_189 :
connect issue_slots[13].in_uop.valid, issue_slots[15].will_be_valid
connect issue_slots[13].in_uop.bits.debug_tsrc, issue_slots[15].out_uop.debug_tsrc
connect issue_slots[13].in_uop.bits.debug_fsrc, issue_slots[15].out_uop.debug_fsrc
connect issue_slots[13].in_uop.bits.bp_xcpt_if, issue_slots[15].out_uop.bp_xcpt_if
connect issue_slots[13].in_uop.bits.bp_debug_if, issue_slots[15].out_uop.bp_debug_if
connect issue_slots[13].in_uop.bits.xcpt_ma_if, issue_slots[15].out_uop.xcpt_ma_if
connect issue_slots[13].in_uop.bits.xcpt_ae_if, issue_slots[15].out_uop.xcpt_ae_if
connect issue_slots[13].in_uop.bits.xcpt_pf_if, issue_slots[15].out_uop.xcpt_pf_if
connect issue_slots[13].in_uop.bits.fp_typ, issue_slots[15].out_uop.fp_typ
connect issue_slots[13].in_uop.bits.fp_rm, issue_slots[15].out_uop.fp_rm
connect issue_slots[13].in_uop.bits.fp_val, issue_slots[15].out_uop.fp_val
connect issue_slots[13].in_uop.bits.fcn_op, issue_slots[15].out_uop.fcn_op
connect issue_slots[13].in_uop.bits.fcn_dw, issue_slots[15].out_uop.fcn_dw
connect issue_slots[13].in_uop.bits.frs3_en, issue_slots[15].out_uop.frs3_en
connect issue_slots[13].in_uop.bits.lrs2_rtype, issue_slots[15].out_uop.lrs2_rtype
connect issue_slots[13].in_uop.bits.lrs1_rtype, issue_slots[15].out_uop.lrs1_rtype
connect issue_slots[13].in_uop.bits.dst_rtype, issue_slots[15].out_uop.dst_rtype
connect issue_slots[13].in_uop.bits.lrs3, issue_slots[15].out_uop.lrs3
connect issue_slots[13].in_uop.bits.lrs2, issue_slots[15].out_uop.lrs2
connect issue_slots[13].in_uop.bits.lrs1, issue_slots[15].out_uop.lrs1
connect issue_slots[13].in_uop.bits.ldst, issue_slots[15].out_uop.ldst
connect issue_slots[13].in_uop.bits.ldst_is_rs1, issue_slots[15].out_uop.ldst_is_rs1
connect issue_slots[13].in_uop.bits.csr_cmd, issue_slots[15].out_uop.csr_cmd
connect issue_slots[13].in_uop.bits.flush_on_commit, issue_slots[15].out_uop.flush_on_commit
connect issue_slots[13].in_uop.bits.is_unique, issue_slots[15].out_uop.is_unique
connect issue_slots[13].in_uop.bits.uses_stq, issue_slots[15].out_uop.uses_stq
connect issue_slots[13].in_uop.bits.uses_ldq, issue_slots[15].out_uop.uses_ldq
connect issue_slots[13].in_uop.bits.mem_signed, issue_slots[15].out_uop.mem_signed
connect issue_slots[13].in_uop.bits.mem_size, issue_slots[15].out_uop.mem_size
connect issue_slots[13].in_uop.bits.mem_cmd, issue_slots[15].out_uop.mem_cmd
connect issue_slots[13].in_uop.bits.exc_cause, issue_slots[15].out_uop.exc_cause
connect issue_slots[13].in_uop.bits.exception, issue_slots[15].out_uop.exception
connect issue_slots[13].in_uop.bits.stale_pdst, issue_slots[15].out_uop.stale_pdst
connect issue_slots[13].in_uop.bits.ppred_busy, issue_slots[15].out_uop.ppred_busy
connect issue_slots[13].in_uop.bits.prs3_busy, issue_slots[15].out_uop.prs3_busy
connect issue_slots[13].in_uop.bits.prs2_busy, issue_slots[15].out_uop.prs2_busy
connect issue_slots[13].in_uop.bits.prs1_busy, issue_slots[15].out_uop.prs1_busy
connect issue_slots[13].in_uop.bits.ppred, issue_slots[15].out_uop.ppred
connect issue_slots[13].in_uop.bits.prs3, issue_slots[15].out_uop.prs3
connect issue_slots[13].in_uop.bits.prs2, issue_slots[15].out_uop.prs2
connect issue_slots[13].in_uop.bits.prs1, issue_slots[15].out_uop.prs1
connect issue_slots[13].in_uop.bits.pdst, issue_slots[15].out_uop.pdst
connect issue_slots[13].in_uop.bits.rxq_idx, issue_slots[15].out_uop.rxq_idx
connect issue_slots[13].in_uop.bits.stq_idx, issue_slots[15].out_uop.stq_idx
connect issue_slots[13].in_uop.bits.ldq_idx, issue_slots[15].out_uop.ldq_idx
connect issue_slots[13].in_uop.bits.rob_idx, issue_slots[15].out_uop.rob_idx
connect issue_slots[13].in_uop.bits.fp_ctrl.vec, issue_slots[15].out_uop.fp_ctrl.vec
connect issue_slots[13].in_uop.bits.fp_ctrl.wflags, issue_slots[15].out_uop.fp_ctrl.wflags
connect issue_slots[13].in_uop.bits.fp_ctrl.sqrt, issue_slots[15].out_uop.fp_ctrl.sqrt
connect issue_slots[13].in_uop.bits.fp_ctrl.div, issue_slots[15].out_uop.fp_ctrl.div
connect issue_slots[13].in_uop.bits.fp_ctrl.fma, issue_slots[15].out_uop.fp_ctrl.fma
connect issue_slots[13].in_uop.bits.fp_ctrl.fastpipe, issue_slots[15].out_uop.fp_ctrl.fastpipe
connect issue_slots[13].in_uop.bits.fp_ctrl.toint, issue_slots[15].out_uop.fp_ctrl.toint
connect issue_slots[13].in_uop.bits.fp_ctrl.fromint, issue_slots[15].out_uop.fp_ctrl.fromint
connect issue_slots[13].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[15].out_uop.fp_ctrl.typeTagOut
connect issue_slots[13].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[15].out_uop.fp_ctrl.typeTagIn
connect issue_slots[13].in_uop.bits.fp_ctrl.swap23, issue_slots[15].out_uop.fp_ctrl.swap23
connect issue_slots[13].in_uop.bits.fp_ctrl.swap12, issue_slots[15].out_uop.fp_ctrl.swap12
connect issue_slots[13].in_uop.bits.fp_ctrl.ren3, issue_slots[15].out_uop.fp_ctrl.ren3
connect issue_slots[13].in_uop.bits.fp_ctrl.ren2, issue_slots[15].out_uop.fp_ctrl.ren2
connect issue_slots[13].in_uop.bits.fp_ctrl.ren1, issue_slots[15].out_uop.fp_ctrl.ren1
connect issue_slots[13].in_uop.bits.fp_ctrl.wen, issue_slots[15].out_uop.fp_ctrl.wen
connect issue_slots[13].in_uop.bits.fp_ctrl.ldst, issue_slots[15].out_uop.fp_ctrl.ldst
connect issue_slots[13].in_uop.bits.op2_sel, issue_slots[15].out_uop.op2_sel
connect issue_slots[13].in_uop.bits.op1_sel, issue_slots[15].out_uop.op1_sel
connect issue_slots[13].in_uop.bits.imm_packed, issue_slots[15].out_uop.imm_packed
connect issue_slots[13].in_uop.bits.pimm, issue_slots[15].out_uop.pimm
connect issue_slots[13].in_uop.bits.imm_sel, issue_slots[15].out_uop.imm_sel
connect issue_slots[13].in_uop.bits.imm_rename, issue_slots[15].out_uop.imm_rename
connect issue_slots[13].in_uop.bits.taken, issue_slots[15].out_uop.taken
connect issue_slots[13].in_uop.bits.pc_lob, issue_slots[15].out_uop.pc_lob
connect issue_slots[13].in_uop.bits.edge_inst, issue_slots[15].out_uop.edge_inst
connect issue_slots[13].in_uop.bits.ftq_idx, issue_slots[15].out_uop.ftq_idx
connect issue_slots[13].in_uop.bits.is_mov, issue_slots[15].out_uop.is_mov
connect issue_slots[13].in_uop.bits.is_rocc, issue_slots[15].out_uop.is_rocc
connect issue_slots[13].in_uop.bits.is_sys_pc2epc, issue_slots[15].out_uop.is_sys_pc2epc
connect issue_slots[13].in_uop.bits.is_eret, issue_slots[15].out_uop.is_eret
connect issue_slots[13].in_uop.bits.is_amo, issue_slots[15].out_uop.is_amo
connect issue_slots[13].in_uop.bits.is_sfence, issue_slots[15].out_uop.is_sfence
connect issue_slots[13].in_uop.bits.is_fencei, issue_slots[15].out_uop.is_fencei
connect issue_slots[13].in_uop.bits.is_fence, issue_slots[15].out_uop.is_fence
connect issue_slots[13].in_uop.bits.is_sfb, issue_slots[15].out_uop.is_sfb
connect issue_slots[13].in_uop.bits.br_type, issue_slots[15].out_uop.br_type
connect issue_slots[13].in_uop.bits.br_tag, issue_slots[15].out_uop.br_tag
connect issue_slots[13].in_uop.bits.br_mask, issue_slots[15].out_uop.br_mask
connect issue_slots[13].in_uop.bits.dis_col_sel, issue_slots[15].out_uop.dis_col_sel
connect issue_slots[13].in_uop.bits.iw_p3_bypass_hint, issue_slots[15].out_uop.iw_p3_bypass_hint
connect issue_slots[13].in_uop.bits.iw_p2_bypass_hint, issue_slots[15].out_uop.iw_p2_bypass_hint
connect issue_slots[13].in_uop.bits.iw_p1_bypass_hint, issue_slots[15].out_uop.iw_p1_bypass_hint
connect issue_slots[13].in_uop.bits.iw_p2_speculative_child, issue_slots[15].out_uop.iw_p2_speculative_child
connect issue_slots[13].in_uop.bits.iw_p1_speculative_child, issue_slots[15].out_uop.iw_p1_speculative_child
connect issue_slots[13].in_uop.bits.iw_issued_partial_dgen, issue_slots[15].out_uop.iw_issued_partial_dgen
connect issue_slots[13].in_uop.bits.iw_issued_partial_agen, issue_slots[15].out_uop.iw_issued_partial_agen
connect issue_slots[13].in_uop.bits.iw_issued, issue_slots[15].out_uop.iw_issued
connect issue_slots[13].in_uop.bits.fu_code[0], issue_slots[15].out_uop.fu_code[0]
connect issue_slots[13].in_uop.bits.fu_code[1], issue_slots[15].out_uop.fu_code[1]
connect issue_slots[13].in_uop.bits.fu_code[2], issue_slots[15].out_uop.fu_code[2]
connect issue_slots[13].in_uop.bits.fu_code[3], issue_slots[15].out_uop.fu_code[3]
connect issue_slots[13].in_uop.bits.fu_code[4], issue_slots[15].out_uop.fu_code[4]
connect issue_slots[13].in_uop.bits.fu_code[5], issue_slots[15].out_uop.fu_code[5]
connect issue_slots[13].in_uop.bits.fu_code[6], issue_slots[15].out_uop.fu_code[6]
connect issue_slots[13].in_uop.bits.fu_code[7], issue_slots[15].out_uop.fu_code[7]
connect issue_slots[13].in_uop.bits.fu_code[8], issue_slots[15].out_uop.fu_code[8]
connect issue_slots[13].in_uop.bits.fu_code[9], issue_slots[15].out_uop.fu_code[9]
connect issue_slots[13].in_uop.bits.iq_type[0], issue_slots[15].out_uop.iq_type[0]
connect issue_slots[13].in_uop.bits.iq_type[1], issue_slots[15].out_uop.iq_type[1]
connect issue_slots[13].in_uop.bits.iq_type[2], issue_slots[15].out_uop.iq_type[2]
connect issue_slots[13].in_uop.bits.iq_type[3], issue_slots[15].out_uop.iq_type[3]
connect issue_slots[13].in_uop.bits.debug_pc, issue_slots[15].out_uop.debug_pc
connect issue_slots[13].in_uop.bits.is_rvc, issue_slots[15].out_uop.is_rvc
connect issue_slots[13].in_uop.bits.debug_inst, issue_slots[15].out_uop.debug_inst
connect issue_slots[13].in_uop.bits.inst, issue_slots[15].out_uop.inst
node _issue_slots_13_clear_T = neq(shamts_oh[13], UInt<1>(0h0))
connect issue_slots[13].clear, _issue_slots_13_clear_T
connect issue_slots[14].in_uop.valid, UInt<1>(0h0)
connect issue_slots[14].in_uop.bits.debug_tsrc, issue_slots[15].out_uop.debug_tsrc
connect issue_slots[14].in_uop.bits.debug_fsrc, issue_slots[15].out_uop.debug_fsrc
connect issue_slots[14].in_uop.bits.bp_xcpt_if, issue_slots[15].out_uop.bp_xcpt_if
connect issue_slots[14].in_uop.bits.bp_debug_if, issue_slots[15].out_uop.bp_debug_if
connect issue_slots[14].in_uop.bits.xcpt_ma_if, issue_slots[15].out_uop.xcpt_ma_if
connect issue_slots[14].in_uop.bits.xcpt_ae_if, issue_slots[15].out_uop.xcpt_ae_if
connect issue_slots[14].in_uop.bits.xcpt_pf_if, issue_slots[15].out_uop.xcpt_pf_if
connect issue_slots[14].in_uop.bits.fp_typ, issue_slots[15].out_uop.fp_typ
connect issue_slots[14].in_uop.bits.fp_rm, issue_slots[15].out_uop.fp_rm
connect issue_slots[14].in_uop.bits.fp_val, issue_slots[15].out_uop.fp_val
connect issue_slots[14].in_uop.bits.fcn_op, issue_slots[15].out_uop.fcn_op
connect issue_slots[14].in_uop.bits.fcn_dw, issue_slots[15].out_uop.fcn_dw
connect issue_slots[14].in_uop.bits.frs3_en, issue_slots[15].out_uop.frs3_en
connect issue_slots[14].in_uop.bits.lrs2_rtype, issue_slots[15].out_uop.lrs2_rtype
connect issue_slots[14].in_uop.bits.lrs1_rtype, issue_slots[15].out_uop.lrs1_rtype
connect issue_slots[14].in_uop.bits.dst_rtype, issue_slots[15].out_uop.dst_rtype
connect issue_slots[14].in_uop.bits.lrs3, issue_slots[15].out_uop.lrs3
connect issue_slots[14].in_uop.bits.lrs2, issue_slots[15].out_uop.lrs2
connect issue_slots[14].in_uop.bits.lrs1, issue_slots[15].out_uop.lrs1
connect issue_slots[14].in_uop.bits.ldst, issue_slots[15].out_uop.ldst
connect issue_slots[14].in_uop.bits.ldst_is_rs1, issue_slots[15].out_uop.ldst_is_rs1
connect issue_slots[14].in_uop.bits.csr_cmd, issue_slots[15].out_uop.csr_cmd
connect issue_slots[14].in_uop.bits.flush_on_commit, issue_slots[15].out_uop.flush_on_commit
connect issue_slots[14].in_uop.bits.is_unique, issue_slots[15].out_uop.is_unique
connect issue_slots[14].in_uop.bits.uses_stq, issue_slots[15].out_uop.uses_stq
connect issue_slots[14].in_uop.bits.uses_ldq, issue_slots[15].out_uop.uses_ldq
connect issue_slots[14].in_uop.bits.mem_signed, issue_slots[15].out_uop.mem_signed
connect issue_slots[14].in_uop.bits.mem_size, issue_slots[15].out_uop.mem_size
connect issue_slots[14].in_uop.bits.mem_cmd, issue_slots[15].out_uop.mem_cmd
connect issue_slots[14].in_uop.bits.exc_cause, issue_slots[15].out_uop.exc_cause
connect issue_slots[14].in_uop.bits.exception, issue_slots[15].out_uop.exception
connect issue_slots[14].in_uop.bits.stale_pdst, issue_slots[15].out_uop.stale_pdst
connect issue_slots[14].in_uop.bits.ppred_busy, issue_slots[15].out_uop.ppred_busy
connect issue_slots[14].in_uop.bits.prs3_busy, issue_slots[15].out_uop.prs3_busy
connect issue_slots[14].in_uop.bits.prs2_busy, issue_slots[15].out_uop.prs2_busy
connect issue_slots[14].in_uop.bits.prs1_busy, issue_slots[15].out_uop.prs1_busy
connect issue_slots[14].in_uop.bits.ppred, issue_slots[15].out_uop.ppred
connect issue_slots[14].in_uop.bits.prs3, issue_slots[15].out_uop.prs3
connect issue_slots[14].in_uop.bits.prs2, issue_slots[15].out_uop.prs2
connect issue_slots[14].in_uop.bits.prs1, issue_slots[15].out_uop.prs1
connect issue_slots[14].in_uop.bits.pdst, issue_slots[15].out_uop.pdst
connect issue_slots[14].in_uop.bits.rxq_idx, issue_slots[15].out_uop.rxq_idx
connect issue_slots[14].in_uop.bits.stq_idx, issue_slots[15].out_uop.stq_idx
connect issue_slots[14].in_uop.bits.ldq_idx, issue_slots[15].out_uop.ldq_idx
connect issue_slots[14].in_uop.bits.rob_idx, issue_slots[15].out_uop.rob_idx
connect issue_slots[14].in_uop.bits.fp_ctrl.vec, issue_slots[15].out_uop.fp_ctrl.vec
connect issue_slots[14].in_uop.bits.fp_ctrl.wflags, issue_slots[15].out_uop.fp_ctrl.wflags
connect issue_slots[14].in_uop.bits.fp_ctrl.sqrt, issue_slots[15].out_uop.fp_ctrl.sqrt
connect issue_slots[14].in_uop.bits.fp_ctrl.div, issue_slots[15].out_uop.fp_ctrl.div
connect issue_slots[14].in_uop.bits.fp_ctrl.fma, issue_slots[15].out_uop.fp_ctrl.fma
connect issue_slots[14].in_uop.bits.fp_ctrl.fastpipe, issue_slots[15].out_uop.fp_ctrl.fastpipe
connect issue_slots[14].in_uop.bits.fp_ctrl.toint, issue_slots[15].out_uop.fp_ctrl.toint
connect issue_slots[14].in_uop.bits.fp_ctrl.fromint, issue_slots[15].out_uop.fp_ctrl.fromint
connect issue_slots[14].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[15].out_uop.fp_ctrl.typeTagOut
connect issue_slots[14].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[15].out_uop.fp_ctrl.typeTagIn
connect issue_slots[14].in_uop.bits.fp_ctrl.swap23, issue_slots[15].out_uop.fp_ctrl.swap23
connect issue_slots[14].in_uop.bits.fp_ctrl.swap12, issue_slots[15].out_uop.fp_ctrl.swap12
connect issue_slots[14].in_uop.bits.fp_ctrl.ren3, issue_slots[15].out_uop.fp_ctrl.ren3
connect issue_slots[14].in_uop.bits.fp_ctrl.ren2, issue_slots[15].out_uop.fp_ctrl.ren2
connect issue_slots[14].in_uop.bits.fp_ctrl.ren1, issue_slots[15].out_uop.fp_ctrl.ren1
connect issue_slots[14].in_uop.bits.fp_ctrl.wen, issue_slots[15].out_uop.fp_ctrl.wen
connect issue_slots[14].in_uop.bits.fp_ctrl.ldst, issue_slots[15].out_uop.fp_ctrl.ldst
connect issue_slots[14].in_uop.bits.op2_sel, issue_slots[15].out_uop.op2_sel
connect issue_slots[14].in_uop.bits.op1_sel, issue_slots[15].out_uop.op1_sel
connect issue_slots[14].in_uop.bits.imm_packed, issue_slots[15].out_uop.imm_packed
connect issue_slots[14].in_uop.bits.pimm, issue_slots[15].out_uop.pimm
connect issue_slots[14].in_uop.bits.imm_sel, issue_slots[15].out_uop.imm_sel
connect issue_slots[14].in_uop.bits.imm_rename, issue_slots[15].out_uop.imm_rename
connect issue_slots[14].in_uop.bits.taken, issue_slots[15].out_uop.taken
connect issue_slots[14].in_uop.bits.pc_lob, issue_slots[15].out_uop.pc_lob
connect issue_slots[14].in_uop.bits.edge_inst, issue_slots[15].out_uop.edge_inst
connect issue_slots[14].in_uop.bits.ftq_idx, issue_slots[15].out_uop.ftq_idx
connect issue_slots[14].in_uop.bits.is_mov, issue_slots[15].out_uop.is_mov
connect issue_slots[14].in_uop.bits.is_rocc, issue_slots[15].out_uop.is_rocc
connect issue_slots[14].in_uop.bits.is_sys_pc2epc, issue_slots[15].out_uop.is_sys_pc2epc
connect issue_slots[14].in_uop.bits.is_eret, issue_slots[15].out_uop.is_eret
connect issue_slots[14].in_uop.bits.is_amo, issue_slots[15].out_uop.is_amo
connect issue_slots[14].in_uop.bits.is_sfence, issue_slots[15].out_uop.is_sfence
connect issue_slots[14].in_uop.bits.is_fencei, issue_slots[15].out_uop.is_fencei
connect issue_slots[14].in_uop.bits.is_fence, issue_slots[15].out_uop.is_fence
connect issue_slots[14].in_uop.bits.is_sfb, issue_slots[15].out_uop.is_sfb
connect issue_slots[14].in_uop.bits.br_type, issue_slots[15].out_uop.br_type
connect issue_slots[14].in_uop.bits.br_tag, issue_slots[15].out_uop.br_tag
connect issue_slots[14].in_uop.bits.br_mask, issue_slots[15].out_uop.br_mask
connect issue_slots[14].in_uop.bits.dis_col_sel, issue_slots[15].out_uop.dis_col_sel
connect issue_slots[14].in_uop.bits.iw_p3_bypass_hint, issue_slots[15].out_uop.iw_p3_bypass_hint
connect issue_slots[14].in_uop.bits.iw_p2_bypass_hint, issue_slots[15].out_uop.iw_p2_bypass_hint
connect issue_slots[14].in_uop.bits.iw_p1_bypass_hint, issue_slots[15].out_uop.iw_p1_bypass_hint
connect issue_slots[14].in_uop.bits.iw_p2_speculative_child, issue_slots[15].out_uop.iw_p2_speculative_child
connect issue_slots[14].in_uop.bits.iw_p1_speculative_child, issue_slots[15].out_uop.iw_p1_speculative_child
connect issue_slots[14].in_uop.bits.iw_issued_partial_dgen, issue_slots[15].out_uop.iw_issued_partial_dgen
connect issue_slots[14].in_uop.bits.iw_issued_partial_agen, issue_slots[15].out_uop.iw_issued_partial_agen
connect issue_slots[14].in_uop.bits.iw_issued, issue_slots[15].out_uop.iw_issued
connect issue_slots[14].in_uop.bits.fu_code[0], issue_slots[15].out_uop.fu_code[0]
connect issue_slots[14].in_uop.bits.fu_code[1], issue_slots[15].out_uop.fu_code[1]
connect issue_slots[14].in_uop.bits.fu_code[2], issue_slots[15].out_uop.fu_code[2]
connect issue_slots[14].in_uop.bits.fu_code[3], issue_slots[15].out_uop.fu_code[3]
connect issue_slots[14].in_uop.bits.fu_code[4], issue_slots[15].out_uop.fu_code[4]
connect issue_slots[14].in_uop.bits.fu_code[5], issue_slots[15].out_uop.fu_code[5]
connect issue_slots[14].in_uop.bits.fu_code[6], issue_slots[15].out_uop.fu_code[6]
connect issue_slots[14].in_uop.bits.fu_code[7], issue_slots[15].out_uop.fu_code[7]
connect issue_slots[14].in_uop.bits.fu_code[8], issue_slots[15].out_uop.fu_code[8]
connect issue_slots[14].in_uop.bits.fu_code[9], issue_slots[15].out_uop.fu_code[9]
connect issue_slots[14].in_uop.bits.iq_type[0], issue_slots[15].out_uop.iq_type[0]
connect issue_slots[14].in_uop.bits.iq_type[1], issue_slots[15].out_uop.iq_type[1]
connect issue_slots[14].in_uop.bits.iq_type[2], issue_slots[15].out_uop.iq_type[2]
connect issue_slots[14].in_uop.bits.iq_type[3], issue_slots[15].out_uop.iq_type[3]
connect issue_slots[14].in_uop.bits.debug_pc, issue_slots[15].out_uop.debug_pc
connect issue_slots[14].in_uop.bits.is_rvc, issue_slots[15].out_uop.is_rvc
connect issue_slots[14].in_uop.bits.debug_inst, issue_slots[15].out_uop.debug_inst
connect issue_slots[14].in_uop.bits.inst, issue_slots[15].out_uop.inst
node _T_190 = eq(shamts_oh[15], UInt<1>(0h1))
when _T_190 :
connect issue_slots[14].in_uop.valid, issue_slots[15].will_be_valid
connect issue_slots[14].in_uop.bits.debug_tsrc, issue_slots[15].out_uop.debug_tsrc
connect issue_slots[14].in_uop.bits.debug_fsrc, issue_slots[15].out_uop.debug_fsrc
connect issue_slots[14].in_uop.bits.bp_xcpt_if, issue_slots[15].out_uop.bp_xcpt_if
connect issue_slots[14].in_uop.bits.bp_debug_if, issue_slots[15].out_uop.bp_debug_if
connect issue_slots[14].in_uop.bits.xcpt_ma_if, issue_slots[15].out_uop.xcpt_ma_if
connect issue_slots[14].in_uop.bits.xcpt_ae_if, issue_slots[15].out_uop.xcpt_ae_if
connect issue_slots[14].in_uop.bits.xcpt_pf_if, issue_slots[15].out_uop.xcpt_pf_if
connect issue_slots[14].in_uop.bits.fp_typ, issue_slots[15].out_uop.fp_typ
connect issue_slots[14].in_uop.bits.fp_rm, issue_slots[15].out_uop.fp_rm
connect issue_slots[14].in_uop.bits.fp_val, issue_slots[15].out_uop.fp_val
connect issue_slots[14].in_uop.bits.fcn_op, issue_slots[15].out_uop.fcn_op
connect issue_slots[14].in_uop.bits.fcn_dw, issue_slots[15].out_uop.fcn_dw
connect issue_slots[14].in_uop.bits.frs3_en, issue_slots[15].out_uop.frs3_en
connect issue_slots[14].in_uop.bits.lrs2_rtype, issue_slots[15].out_uop.lrs2_rtype
connect issue_slots[14].in_uop.bits.lrs1_rtype, issue_slots[15].out_uop.lrs1_rtype
connect issue_slots[14].in_uop.bits.dst_rtype, issue_slots[15].out_uop.dst_rtype
connect issue_slots[14].in_uop.bits.lrs3, issue_slots[15].out_uop.lrs3
connect issue_slots[14].in_uop.bits.lrs2, issue_slots[15].out_uop.lrs2
connect issue_slots[14].in_uop.bits.lrs1, issue_slots[15].out_uop.lrs1
connect issue_slots[14].in_uop.bits.ldst, issue_slots[15].out_uop.ldst
connect issue_slots[14].in_uop.bits.ldst_is_rs1, issue_slots[15].out_uop.ldst_is_rs1
connect issue_slots[14].in_uop.bits.csr_cmd, issue_slots[15].out_uop.csr_cmd
connect issue_slots[14].in_uop.bits.flush_on_commit, issue_slots[15].out_uop.flush_on_commit
connect issue_slots[14].in_uop.bits.is_unique, issue_slots[15].out_uop.is_unique
connect issue_slots[14].in_uop.bits.uses_stq, issue_slots[15].out_uop.uses_stq
connect issue_slots[14].in_uop.bits.uses_ldq, issue_slots[15].out_uop.uses_ldq
connect issue_slots[14].in_uop.bits.mem_signed, issue_slots[15].out_uop.mem_signed
connect issue_slots[14].in_uop.bits.mem_size, issue_slots[15].out_uop.mem_size
connect issue_slots[14].in_uop.bits.mem_cmd, issue_slots[15].out_uop.mem_cmd
connect issue_slots[14].in_uop.bits.exc_cause, issue_slots[15].out_uop.exc_cause
connect issue_slots[14].in_uop.bits.exception, issue_slots[15].out_uop.exception
connect issue_slots[14].in_uop.bits.stale_pdst, issue_slots[15].out_uop.stale_pdst
connect issue_slots[14].in_uop.bits.ppred_busy, issue_slots[15].out_uop.ppred_busy
connect issue_slots[14].in_uop.bits.prs3_busy, issue_slots[15].out_uop.prs3_busy
connect issue_slots[14].in_uop.bits.prs2_busy, issue_slots[15].out_uop.prs2_busy
connect issue_slots[14].in_uop.bits.prs1_busy, issue_slots[15].out_uop.prs1_busy
connect issue_slots[14].in_uop.bits.ppred, issue_slots[15].out_uop.ppred
connect issue_slots[14].in_uop.bits.prs3, issue_slots[15].out_uop.prs3
connect issue_slots[14].in_uop.bits.prs2, issue_slots[15].out_uop.prs2
connect issue_slots[14].in_uop.bits.prs1, issue_slots[15].out_uop.prs1
connect issue_slots[14].in_uop.bits.pdst, issue_slots[15].out_uop.pdst
connect issue_slots[14].in_uop.bits.rxq_idx, issue_slots[15].out_uop.rxq_idx
connect issue_slots[14].in_uop.bits.stq_idx, issue_slots[15].out_uop.stq_idx
connect issue_slots[14].in_uop.bits.ldq_idx, issue_slots[15].out_uop.ldq_idx
connect issue_slots[14].in_uop.bits.rob_idx, issue_slots[15].out_uop.rob_idx
connect issue_slots[14].in_uop.bits.fp_ctrl.vec, issue_slots[15].out_uop.fp_ctrl.vec
connect issue_slots[14].in_uop.bits.fp_ctrl.wflags, issue_slots[15].out_uop.fp_ctrl.wflags
connect issue_slots[14].in_uop.bits.fp_ctrl.sqrt, issue_slots[15].out_uop.fp_ctrl.sqrt
connect issue_slots[14].in_uop.bits.fp_ctrl.div, issue_slots[15].out_uop.fp_ctrl.div
connect issue_slots[14].in_uop.bits.fp_ctrl.fma, issue_slots[15].out_uop.fp_ctrl.fma
connect issue_slots[14].in_uop.bits.fp_ctrl.fastpipe, issue_slots[15].out_uop.fp_ctrl.fastpipe
connect issue_slots[14].in_uop.bits.fp_ctrl.toint, issue_slots[15].out_uop.fp_ctrl.toint
connect issue_slots[14].in_uop.bits.fp_ctrl.fromint, issue_slots[15].out_uop.fp_ctrl.fromint
connect issue_slots[14].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[15].out_uop.fp_ctrl.typeTagOut
connect issue_slots[14].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[15].out_uop.fp_ctrl.typeTagIn
connect issue_slots[14].in_uop.bits.fp_ctrl.swap23, issue_slots[15].out_uop.fp_ctrl.swap23
connect issue_slots[14].in_uop.bits.fp_ctrl.swap12, issue_slots[15].out_uop.fp_ctrl.swap12
connect issue_slots[14].in_uop.bits.fp_ctrl.ren3, issue_slots[15].out_uop.fp_ctrl.ren3
connect issue_slots[14].in_uop.bits.fp_ctrl.ren2, issue_slots[15].out_uop.fp_ctrl.ren2
connect issue_slots[14].in_uop.bits.fp_ctrl.ren1, issue_slots[15].out_uop.fp_ctrl.ren1
connect issue_slots[14].in_uop.bits.fp_ctrl.wen, issue_slots[15].out_uop.fp_ctrl.wen
connect issue_slots[14].in_uop.bits.fp_ctrl.ldst, issue_slots[15].out_uop.fp_ctrl.ldst
connect issue_slots[14].in_uop.bits.op2_sel, issue_slots[15].out_uop.op2_sel
connect issue_slots[14].in_uop.bits.op1_sel, issue_slots[15].out_uop.op1_sel
connect issue_slots[14].in_uop.bits.imm_packed, issue_slots[15].out_uop.imm_packed
connect issue_slots[14].in_uop.bits.pimm, issue_slots[15].out_uop.pimm
connect issue_slots[14].in_uop.bits.imm_sel, issue_slots[15].out_uop.imm_sel
connect issue_slots[14].in_uop.bits.imm_rename, issue_slots[15].out_uop.imm_rename
connect issue_slots[14].in_uop.bits.taken, issue_slots[15].out_uop.taken
connect issue_slots[14].in_uop.bits.pc_lob, issue_slots[15].out_uop.pc_lob
connect issue_slots[14].in_uop.bits.edge_inst, issue_slots[15].out_uop.edge_inst
connect issue_slots[14].in_uop.bits.ftq_idx, issue_slots[15].out_uop.ftq_idx
connect issue_slots[14].in_uop.bits.is_mov, issue_slots[15].out_uop.is_mov
connect issue_slots[14].in_uop.bits.is_rocc, issue_slots[15].out_uop.is_rocc
connect issue_slots[14].in_uop.bits.is_sys_pc2epc, issue_slots[15].out_uop.is_sys_pc2epc
connect issue_slots[14].in_uop.bits.is_eret, issue_slots[15].out_uop.is_eret
connect issue_slots[14].in_uop.bits.is_amo, issue_slots[15].out_uop.is_amo
connect issue_slots[14].in_uop.bits.is_sfence, issue_slots[15].out_uop.is_sfence
connect issue_slots[14].in_uop.bits.is_fencei, issue_slots[15].out_uop.is_fencei
connect issue_slots[14].in_uop.bits.is_fence, issue_slots[15].out_uop.is_fence
connect issue_slots[14].in_uop.bits.is_sfb, issue_slots[15].out_uop.is_sfb
connect issue_slots[14].in_uop.bits.br_type, issue_slots[15].out_uop.br_type
connect issue_slots[14].in_uop.bits.br_tag, issue_slots[15].out_uop.br_tag
connect issue_slots[14].in_uop.bits.br_mask, issue_slots[15].out_uop.br_mask
connect issue_slots[14].in_uop.bits.dis_col_sel, issue_slots[15].out_uop.dis_col_sel
connect issue_slots[14].in_uop.bits.iw_p3_bypass_hint, issue_slots[15].out_uop.iw_p3_bypass_hint
connect issue_slots[14].in_uop.bits.iw_p2_bypass_hint, issue_slots[15].out_uop.iw_p2_bypass_hint
connect issue_slots[14].in_uop.bits.iw_p1_bypass_hint, issue_slots[15].out_uop.iw_p1_bypass_hint
connect issue_slots[14].in_uop.bits.iw_p2_speculative_child, issue_slots[15].out_uop.iw_p2_speculative_child
connect issue_slots[14].in_uop.bits.iw_p1_speculative_child, issue_slots[15].out_uop.iw_p1_speculative_child
connect issue_slots[14].in_uop.bits.iw_issued_partial_dgen, issue_slots[15].out_uop.iw_issued_partial_dgen
connect issue_slots[14].in_uop.bits.iw_issued_partial_agen, issue_slots[15].out_uop.iw_issued_partial_agen
connect issue_slots[14].in_uop.bits.iw_issued, issue_slots[15].out_uop.iw_issued
connect issue_slots[14].in_uop.bits.fu_code[0], issue_slots[15].out_uop.fu_code[0]
connect issue_slots[14].in_uop.bits.fu_code[1], issue_slots[15].out_uop.fu_code[1]
connect issue_slots[14].in_uop.bits.fu_code[2], issue_slots[15].out_uop.fu_code[2]
connect issue_slots[14].in_uop.bits.fu_code[3], issue_slots[15].out_uop.fu_code[3]
connect issue_slots[14].in_uop.bits.fu_code[4], issue_slots[15].out_uop.fu_code[4]
connect issue_slots[14].in_uop.bits.fu_code[5], issue_slots[15].out_uop.fu_code[5]
connect issue_slots[14].in_uop.bits.fu_code[6], issue_slots[15].out_uop.fu_code[6]
connect issue_slots[14].in_uop.bits.fu_code[7], issue_slots[15].out_uop.fu_code[7]
connect issue_slots[14].in_uop.bits.fu_code[8], issue_slots[15].out_uop.fu_code[8]
connect issue_slots[14].in_uop.bits.fu_code[9], issue_slots[15].out_uop.fu_code[9]
connect issue_slots[14].in_uop.bits.iq_type[0], issue_slots[15].out_uop.iq_type[0]
connect issue_slots[14].in_uop.bits.iq_type[1], issue_slots[15].out_uop.iq_type[1]
connect issue_slots[14].in_uop.bits.iq_type[2], issue_slots[15].out_uop.iq_type[2]
connect issue_slots[14].in_uop.bits.iq_type[3], issue_slots[15].out_uop.iq_type[3]
connect issue_slots[14].in_uop.bits.debug_pc, issue_slots[15].out_uop.debug_pc
connect issue_slots[14].in_uop.bits.is_rvc, issue_slots[15].out_uop.is_rvc
connect issue_slots[14].in_uop.bits.debug_inst, issue_slots[15].out_uop.debug_inst
connect issue_slots[14].in_uop.bits.inst, issue_slots[15].out_uop.inst
node _T_191 = eq(shamts_oh[16], UInt<2>(0h2))
when _T_191 :
connect issue_slots[14].in_uop.valid, issue_slots[16].will_be_valid
connect issue_slots[14].in_uop.bits.debug_tsrc, issue_slots[16].out_uop.debug_tsrc
connect issue_slots[14].in_uop.bits.debug_fsrc, issue_slots[16].out_uop.debug_fsrc
connect issue_slots[14].in_uop.bits.bp_xcpt_if, issue_slots[16].out_uop.bp_xcpt_if
connect issue_slots[14].in_uop.bits.bp_debug_if, issue_slots[16].out_uop.bp_debug_if
connect issue_slots[14].in_uop.bits.xcpt_ma_if, issue_slots[16].out_uop.xcpt_ma_if
connect issue_slots[14].in_uop.bits.xcpt_ae_if, issue_slots[16].out_uop.xcpt_ae_if
connect issue_slots[14].in_uop.bits.xcpt_pf_if, issue_slots[16].out_uop.xcpt_pf_if
connect issue_slots[14].in_uop.bits.fp_typ, issue_slots[16].out_uop.fp_typ
connect issue_slots[14].in_uop.bits.fp_rm, issue_slots[16].out_uop.fp_rm
connect issue_slots[14].in_uop.bits.fp_val, issue_slots[16].out_uop.fp_val
connect issue_slots[14].in_uop.bits.fcn_op, issue_slots[16].out_uop.fcn_op
connect issue_slots[14].in_uop.bits.fcn_dw, issue_slots[16].out_uop.fcn_dw
connect issue_slots[14].in_uop.bits.frs3_en, issue_slots[16].out_uop.frs3_en
connect issue_slots[14].in_uop.bits.lrs2_rtype, issue_slots[16].out_uop.lrs2_rtype
connect issue_slots[14].in_uop.bits.lrs1_rtype, issue_slots[16].out_uop.lrs1_rtype
connect issue_slots[14].in_uop.bits.dst_rtype, issue_slots[16].out_uop.dst_rtype
connect issue_slots[14].in_uop.bits.lrs3, issue_slots[16].out_uop.lrs3
connect issue_slots[14].in_uop.bits.lrs2, issue_slots[16].out_uop.lrs2
connect issue_slots[14].in_uop.bits.lrs1, issue_slots[16].out_uop.lrs1
connect issue_slots[14].in_uop.bits.ldst, issue_slots[16].out_uop.ldst
connect issue_slots[14].in_uop.bits.ldst_is_rs1, issue_slots[16].out_uop.ldst_is_rs1
connect issue_slots[14].in_uop.bits.csr_cmd, issue_slots[16].out_uop.csr_cmd
connect issue_slots[14].in_uop.bits.flush_on_commit, issue_slots[16].out_uop.flush_on_commit
connect issue_slots[14].in_uop.bits.is_unique, issue_slots[16].out_uop.is_unique
connect issue_slots[14].in_uop.bits.uses_stq, issue_slots[16].out_uop.uses_stq
connect issue_slots[14].in_uop.bits.uses_ldq, issue_slots[16].out_uop.uses_ldq
connect issue_slots[14].in_uop.bits.mem_signed, issue_slots[16].out_uop.mem_signed
connect issue_slots[14].in_uop.bits.mem_size, issue_slots[16].out_uop.mem_size
connect issue_slots[14].in_uop.bits.mem_cmd, issue_slots[16].out_uop.mem_cmd
connect issue_slots[14].in_uop.bits.exc_cause, issue_slots[16].out_uop.exc_cause
connect issue_slots[14].in_uop.bits.exception, issue_slots[16].out_uop.exception
connect issue_slots[14].in_uop.bits.stale_pdst, issue_slots[16].out_uop.stale_pdst
connect issue_slots[14].in_uop.bits.ppred_busy, issue_slots[16].out_uop.ppred_busy
connect issue_slots[14].in_uop.bits.prs3_busy, issue_slots[16].out_uop.prs3_busy
connect issue_slots[14].in_uop.bits.prs2_busy, issue_slots[16].out_uop.prs2_busy
connect issue_slots[14].in_uop.bits.prs1_busy, issue_slots[16].out_uop.prs1_busy
connect issue_slots[14].in_uop.bits.ppred, issue_slots[16].out_uop.ppred
connect issue_slots[14].in_uop.bits.prs3, issue_slots[16].out_uop.prs3
connect issue_slots[14].in_uop.bits.prs2, issue_slots[16].out_uop.prs2
connect issue_slots[14].in_uop.bits.prs1, issue_slots[16].out_uop.prs1
connect issue_slots[14].in_uop.bits.pdst, issue_slots[16].out_uop.pdst
connect issue_slots[14].in_uop.bits.rxq_idx, issue_slots[16].out_uop.rxq_idx
connect issue_slots[14].in_uop.bits.stq_idx, issue_slots[16].out_uop.stq_idx
connect issue_slots[14].in_uop.bits.ldq_idx, issue_slots[16].out_uop.ldq_idx
connect issue_slots[14].in_uop.bits.rob_idx, issue_slots[16].out_uop.rob_idx
connect issue_slots[14].in_uop.bits.fp_ctrl.vec, issue_slots[16].out_uop.fp_ctrl.vec
connect issue_slots[14].in_uop.bits.fp_ctrl.wflags, issue_slots[16].out_uop.fp_ctrl.wflags
connect issue_slots[14].in_uop.bits.fp_ctrl.sqrt, issue_slots[16].out_uop.fp_ctrl.sqrt
connect issue_slots[14].in_uop.bits.fp_ctrl.div, issue_slots[16].out_uop.fp_ctrl.div
connect issue_slots[14].in_uop.bits.fp_ctrl.fma, issue_slots[16].out_uop.fp_ctrl.fma
connect issue_slots[14].in_uop.bits.fp_ctrl.fastpipe, issue_slots[16].out_uop.fp_ctrl.fastpipe
connect issue_slots[14].in_uop.bits.fp_ctrl.toint, issue_slots[16].out_uop.fp_ctrl.toint
connect issue_slots[14].in_uop.bits.fp_ctrl.fromint, issue_slots[16].out_uop.fp_ctrl.fromint
connect issue_slots[14].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[16].out_uop.fp_ctrl.typeTagOut
connect issue_slots[14].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[16].out_uop.fp_ctrl.typeTagIn
connect issue_slots[14].in_uop.bits.fp_ctrl.swap23, issue_slots[16].out_uop.fp_ctrl.swap23
connect issue_slots[14].in_uop.bits.fp_ctrl.swap12, issue_slots[16].out_uop.fp_ctrl.swap12
connect issue_slots[14].in_uop.bits.fp_ctrl.ren3, issue_slots[16].out_uop.fp_ctrl.ren3
connect issue_slots[14].in_uop.bits.fp_ctrl.ren2, issue_slots[16].out_uop.fp_ctrl.ren2
connect issue_slots[14].in_uop.bits.fp_ctrl.ren1, issue_slots[16].out_uop.fp_ctrl.ren1
connect issue_slots[14].in_uop.bits.fp_ctrl.wen, issue_slots[16].out_uop.fp_ctrl.wen
connect issue_slots[14].in_uop.bits.fp_ctrl.ldst, issue_slots[16].out_uop.fp_ctrl.ldst
connect issue_slots[14].in_uop.bits.op2_sel, issue_slots[16].out_uop.op2_sel
connect issue_slots[14].in_uop.bits.op1_sel, issue_slots[16].out_uop.op1_sel
connect issue_slots[14].in_uop.bits.imm_packed, issue_slots[16].out_uop.imm_packed
connect issue_slots[14].in_uop.bits.pimm, issue_slots[16].out_uop.pimm
connect issue_slots[14].in_uop.bits.imm_sel, issue_slots[16].out_uop.imm_sel
connect issue_slots[14].in_uop.bits.imm_rename, issue_slots[16].out_uop.imm_rename
connect issue_slots[14].in_uop.bits.taken, issue_slots[16].out_uop.taken
connect issue_slots[14].in_uop.bits.pc_lob, issue_slots[16].out_uop.pc_lob
connect issue_slots[14].in_uop.bits.edge_inst, issue_slots[16].out_uop.edge_inst
connect issue_slots[14].in_uop.bits.ftq_idx, issue_slots[16].out_uop.ftq_idx
connect issue_slots[14].in_uop.bits.is_mov, issue_slots[16].out_uop.is_mov
connect issue_slots[14].in_uop.bits.is_rocc, issue_slots[16].out_uop.is_rocc
connect issue_slots[14].in_uop.bits.is_sys_pc2epc, issue_slots[16].out_uop.is_sys_pc2epc
connect issue_slots[14].in_uop.bits.is_eret, issue_slots[16].out_uop.is_eret
connect issue_slots[14].in_uop.bits.is_amo, issue_slots[16].out_uop.is_amo
connect issue_slots[14].in_uop.bits.is_sfence, issue_slots[16].out_uop.is_sfence
connect issue_slots[14].in_uop.bits.is_fencei, issue_slots[16].out_uop.is_fencei
connect issue_slots[14].in_uop.bits.is_fence, issue_slots[16].out_uop.is_fence
connect issue_slots[14].in_uop.bits.is_sfb, issue_slots[16].out_uop.is_sfb
connect issue_slots[14].in_uop.bits.br_type, issue_slots[16].out_uop.br_type
connect issue_slots[14].in_uop.bits.br_tag, issue_slots[16].out_uop.br_tag
connect issue_slots[14].in_uop.bits.br_mask, issue_slots[16].out_uop.br_mask
connect issue_slots[14].in_uop.bits.dis_col_sel, issue_slots[16].out_uop.dis_col_sel
connect issue_slots[14].in_uop.bits.iw_p3_bypass_hint, issue_slots[16].out_uop.iw_p3_bypass_hint
connect issue_slots[14].in_uop.bits.iw_p2_bypass_hint, issue_slots[16].out_uop.iw_p2_bypass_hint
connect issue_slots[14].in_uop.bits.iw_p1_bypass_hint, issue_slots[16].out_uop.iw_p1_bypass_hint
connect issue_slots[14].in_uop.bits.iw_p2_speculative_child, issue_slots[16].out_uop.iw_p2_speculative_child
connect issue_slots[14].in_uop.bits.iw_p1_speculative_child, issue_slots[16].out_uop.iw_p1_speculative_child
connect issue_slots[14].in_uop.bits.iw_issued_partial_dgen, issue_slots[16].out_uop.iw_issued_partial_dgen
connect issue_slots[14].in_uop.bits.iw_issued_partial_agen, issue_slots[16].out_uop.iw_issued_partial_agen
connect issue_slots[14].in_uop.bits.iw_issued, issue_slots[16].out_uop.iw_issued
connect issue_slots[14].in_uop.bits.fu_code[0], issue_slots[16].out_uop.fu_code[0]
connect issue_slots[14].in_uop.bits.fu_code[1], issue_slots[16].out_uop.fu_code[1]
connect issue_slots[14].in_uop.bits.fu_code[2], issue_slots[16].out_uop.fu_code[2]
connect issue_slots[14].in_uop.bits.fu_code[3], issue_slots[16].out_uop.fu_code[3]
connect issue_slots[14].in_uop.bits.fu_code[4], issue_slots[16].out_uop.fu_code[4]
connect issue_slots[14].in_uop.bits.fu_code[5], issue_slots[16].out_uop.fu_code[5]
connect issue_slots[14].in_uop.bits.fu_code[6], issue_slots[16].out_uop.fu_code[6]
connect issue_slots[14].in_uop.bits.fu_code[7], issue_slots[16].out_uop.fu_code[7]
connect issue_slots[14].in_uop.bits.fu_code[8], issue_slots[16].out_uop.fu_code[8]
connect issue_slots[14].in_uop.bits.fu_code[9], issue_slots[16].out_uop.fu_code[9]
connect issue_slots[14].in_uop.bits.iq_type[0], issue_slots[16].out_uop.iq_type[0]
connect issue_slots[14].in_uop.bits.iq_type[1], issue_slots[16].out_uop.iq_type[1]
connect issue_slots[14].in_uop.bits.iq_type[2], issue_slots[16].out_uop.iq_type[2]
connect issue_slots[14].in_uop.bits.iq_type[3], issue_slots[16].out_uop.iq_type[3]
connect issue_slots[14].in_uop.bits.debug_pc, issue_slots[16].out_uop.debug_pc
connect issue_slots[14].in_uop.bits.is_rvc, issue_slots[16].out_uop.is_rvc
connect issue_slots[14].in_uop.bits.debug_inst, issue_slots[16].out_uop.debug_inst
connect issue_slots[14].in_uop.bits.inst, issue_slots[16].out_uop.inst
node _issue_slots_14_clear_T = neq(shamts_oh[14], UInt<1>(0h0))
connect issue_slots[14].clear, _issue_slots_14_clear_T
connect issue_slots[15].in_uop.valid, UInt<1>(0h0)
connect issue_slots[15].in_uop.bits.debug_tsrc, issue_slots[16].out_uop.debug_tsrc
connect issue_slots[15].in_uop.bits.debug_fsrc, issue_slots[16].out_uop.debug_fsrc
connect issue_slots[15].in_uop.bits.bp_xcpt_if, issue_slots[16].out_uop.bp_xcpt_if
connect issue_slots[15].in_uop.bits.bp_debug_if, issue_slots[16].out_uop.bp_debug_if
connect issue_slots[15].in_uop.bits.xcpt_ma_if, issue_slots[16].out_uop.xcpt_ma_if
connect issue_slots[15].in_uop.bits.xcpt_ae_if, issue_slots[16].out_uop.xcpt_ae_if
connect issue_slots[15].in_uop.bits.xcpt_pf_if, issue_slots[16].out_uop.xcpt_pf_if
connect issue_slots[15].in_uop.bits.fp_typ, issue_slots[16].out_uop.fp_typ
connect issue_slots[15].in_uop.bits.fp_rm, issue_slots[16].out_uop.fp_rm
connect issue_slots[15].in_uop.bits.fp_val, issue_slots[16].out_uop.fp_val
connect issue_slots[15].in_uop.bits.fcn_op, issue_slots[16].out_uop.fcn_op
connect issue_slots[15].in_uop.bits.fcn_dw, issue_slots[16].out_uop.fcn_dw
connect issue_slots[15].in_uop.bits.frs3_en, issue_slots[16].out_uop.frs3_en
connect issue_slots[15].in_uop.bits.lrs2_rtype, issue_slots[16].out_uop.lrs2_rtype
connect issue_slots[15].in_uop.bits.lrs1_rtype, issue_slots[16].out_uop.lrs1_rtype
connect issue_slots[15].in_uop.bits.dst_rtype, issue_slots[16].out_uop.dst_rtype
connect issue_slots[15].in_uop.bits.lrs3, issue_slots[16].out_uop.lrs3
connect issue_slots[15].in_uop.bits.lrs2, issue_slots[16].out_uop.lrs2
connect issue_slots[15].in_uop.bits.lrs1, issue_slots[16].out_uop.lrs1
connect issue_slots[15].in_uop.bits.ldst, issue_slots[16].out_uop.ldst
connect issue_slots[15].in_uop.bits.ldst_is_rs1, issue_slots[16].out_uop.ldst_is_rs1
connect issue_slots[15].in_uop.bits.csr_cmd, issue_slots[16].out_uop.csr_cmd
connect issue_slots[15].in_uop.bits.flush_on_commit, issue_slots[16].out_uop.flush_on_commit
connect issue_slots[15].in_uop.bits.is_unique, issue_slots[16].out_uop.is_unique
connect issue_slots[15].in_uop.bits.uses_stq, issue_slots[16].out_uop.uses_stq
connect issue_slots[15].in_uop.bits.uses_ldq, issue_slots[16].out_uop.uses_ldq
connect issue_slots[15].in_uop.bits.mem_signed, issue_slots[16].out_uop.mem_signed
connect issue_slots[15].in_uop.bits.mem_size, issue_slots[16].out_uop.mem_size
connect issue_slots[15].in_uop.bits.mem_cmd, issue_slots[16].out_uop.mem_cmd
connect issue_slots[15].in_uop.bits.exc_cause, issue_slots[16].out_uop.exc_cause
connect issue_slots[15].in_uop.bits.exception, issue_slots[16].out_uop.exception
connect issue_slots[15].in_uop.bits.stale_pdst, issue_slots[16].out_uop.stale_pdst
connect issue_slots[15].in_uop.bits.ppred_busy, issue_slots[16].out_uop.ppred_busy
connect issue_slots[15].in_uop.bits.prs3_busy, issue_slots[16].out_uop.prs3_busy
connect issue_slots[15].in_uop.bits.prs2_busy, issue_slots[16].out_uop.prs2_busy
connect issue_slots[15].in_uop.bits.prs1_busy, issue_slots[16].out_uop.prs1_busy
connect issue_slots[15].in_uop.bits.ppred, issue_slots[16].out_uop.ppred
connect issue_slots[15].in_uop.bits.prs3, issue_slots[16].out_uop.prs3
connect issue_slots[15].in_uop.bits.prs2, issue_slots[16].out_uop.prs2
connect issue_slots[15].in_uop.bits.prs1, issue_slots[16].out_uop.prs1
connect issue_slots[15].in_uop.bits.pdst, issue_slots[16].out_uop.pdst
connect issue_slots[15].in_uop.bits.rxq_idx, issue_slots[16].out_uop.rxq_idx
connect issue_slots[15].in_uop.bits.stq_idx, issue_slots[16].out_uop.stq_idx
connect issue_slots[15].in_uop.bits.ldq_idx, issue_slots[16].out_uop.ldq_idx
connect issue_slots[15].in_uop.bits.rob_idx, issue_slots[16].out_uop.rob_idx
connect issue_slots[15].in_uop.bits.fp_ctrl.vec, issue_slots[16].out_uop.fp_ctrl.vec
connect issue_slots[15].in_uop.bits.fp_ctrl.wflags, issue_slots[16].out_uop.fp_ctrl.wflags
connect issue_slots[15].in_uop.bits.fp_ctrl.sqrt, issue_slots[16].out_uop.fp_ctrl.sqrt
connect issue_slots[15].in_uop.bits.fp_ctrl.div, issue_slots[16].out_uop.fp_ctrl.div
connect issue_slots[15].in_uop.bits.fp_ctrl.fma, issue_slots[16].out_uop.fp_ctrl.fma
connect issue_slots[15].in_uop.bits.fp_ctrl.fastpipe, issue_slots[16].out_uop.fp_ctrl.fastpipe
connect issue_slots[15].in_uop.bits.fp_ctrl.toint, issue_slots[16].out_uop.fp_ctrl.toint
connect issue_slots[15].in_uop.bits.fp_ctrl.fromint, issue_slots[16].out_uop.fp_ctrl.fromint
connect issue_slots[15].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[16].out_uop.fp_ctrl.typeTagOut
connect issue_slots[15].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[16].out_uop.fp_ctrl.typeTagIn
connect issue_slots[15].in_uop.bits.fp_ctrl.swap23, issue_slots[16].out_uop.fp_ctrl.swap23
connect issue_slots[15].in_uop.bits.fp_ctrl.swap12, issue_slots[16].out_uop.fp_ctrl.swap12
connect issue_slots[15].in_uop.bits.fp_ctrl.ren3, issue_slots[16].out_uop.fp_ctrl.ren3
connect issue_slots[15].in_uop.bits.fp_ctrl.ren2, issue_slots[16].out_uop.fp_ctrl.ren2
connect issue_slots[15].in_uop.bits.fp_ctrl.ren1, issue_slots[16].out_uop.fp_ctrl.ren1
connect issue_slots[15].in_uop.bits.fp_ctrl.wen, issue_slots[16].out_uop.fp_ctrl.wen
connect issue_slots[15].in_uop.bits.fp_ctrl.ldst, issue_slots[16].out_uop.fp_ctrl.ldst
connect issue_slots[15].in_uop.bits.op2_sel, issue_slots[16].out_uop.op2_sel
connect issue_slots[15].in_uop.bits.op1_sel, issue_slots[16].out_uop.op1_sel
connect issue_slots[15].in_uop.bits.imm_packed, issue_slots[16].out_uop.imm_packed
connect issue_slots[15].in_uop.bits.pimm, issue_slots[16].out_uop.pimm
connect issue_slots[15].in_uop.bits.imm_sel, issue_slots[16].out_uop.imm_sel
connect issue_slots[15].in_uop.bits.imm_rename, issue_slots[16].out_uop.imm_rename
connect issue_slots[15].in_uop.bits.taken, issue_slots[16].out_uop.taken
connect issue_slots[15].in_uop.bits.pc_lob, issue_slots[16].out_uop.pc_lob
connect issue_slots[15].in_uop.bits.edge_inst, issue_slots[16].out_uop.edge_inst
connect issue_slots[15].in_uop.bits.ftq_idx, issue_slots[16].out_uop.ftq_idx
connect issue_slots[15].in_uop.bits.is_mov, issue_slots[16].out_uop.is_mov
connect issue_slots[15].in_uop.bits.is_rocc, issue_slots[16].out_uop.is_rocc
connect issue_slots[15].in_uop.bits.is_sys_pc2epc, issue_slots[16].out_uop.is_sys_pc2epc
connect issue_slots[15].in_uop.bits.is_eret, issue_slots[16].out_uop.is_eret
connect issue_slots[15].in_uop.bits.is_amo, issue_slots[16].out_uop.is_amo
connect issue_slots[15].in_uop.bits.is_sfence, issue_slots[16].out_uop.is_sfence
connect issue_slots[15].in_uop.bits.is_fencei, issue_slots[16].out_uop.is_fencei
connect issue_slots[15].in_uop.bits.is_fence, issue_slots[16].out_uop.is_fence
connect issue_slots[15].in_uop.bits.is_sfb, issue_slots[16].out_uop.is_sfb
connect issue_slots[15].in_uop.bits.br_type, issue_slots[16].out_uop.br_type
connect issue_slots[15].in_uop.bits.br_tag, issue_slots[16].out_uop.br_tag
connect issue_slots[15].in_uop.bits.br_mask, issue_slots[16].out_uop.br_mask
connect issue_slots[15].in_uop.bits.dis_col_sel, issue_slots[16].out_uop.dis_col_sel
connect issue_slots[15].in_uop.bits.iw_p3_bypass_hint, issue_slots[16].out_uop.iw_p3_bypass_hint
connect issue_slots[15].in_uop.bits.iw_p2_bypass_hint, issue_slots[16].out_uop.iw_p2_bypass_hint
connect issue_slots[15].in_uop.bits.iw_p1_bypass_hint, issue_slots[16].out_uop.iw_p1_bypass_hint
connect issue_slots[15].in_uop.bits.iw_p2_speculative_child, issue_slots[16].out_uop.iw_p2_speculative_child
connect issue_slots[15].in_uop.bits.iw_p1_speculative_child, issue_slots[16].out_uop.iw_p1_speculative_child
connect issue_slots[15].in_uop.bits.iw_issued_partial_dgen, issue_slots[16].out_uop.iw_issued_partial_dgen
connect issue_slots[15].in_uop.bits.iw_issued_partial_agen, issue_slots[16].out_uop.iw_issued_partial_agen
connect issue_slots[15].in_uop.bits.iw_issued, issue_slots[16].out_uop.iw_issued
connect issue_slots[15].in_uop.bits.fu_code[0], issue_slots[16].out_uop.fu_code[0]
connect issue_slots[15].in_uop.bits.fu_code[1], issue_slots[16].out_uop.fu_code[1]
connect issue_slots[15].in_uop.bits.fu_code[2], issue_slots[16].out_uop.fu_code[2]
connect issue_slots[15].in_uop.bits.fu_code[3], issue_slots[16].out_uop.fu_code[3]
connect issue_slots[15].in_uop.bits.fu_code[4], issue_slots[16].out_uop.fu_code[4]
connect issue_slots[15].in_uop.bits.fu_code[5], issue_slots[16].out_uop.fu_code[5]
connect issue_slots[15].in_uop.bits.fu_code[6], issue_slots[16].out_uop.fu_code[6]
connect issue_slots[15].in_uop.bits.fu_code[7], issue_slots[16].out_uop.fu_code[7]
connect issue_slots[15].in_uop.bits.fu_code[8], issue_slots[16].out_uop.fu_code[8]
connect issue_slots[15].in_uop.bits.fu_code[9], issue_slots[16].out_uop.fu_code[9]
connect issue_slots[15].in_uop.bits.iq_type[0], issue_slots[16].out_uop.iq_type[0]
connect issue_slots[15].in_uop.bits.iq_type[1], issue_slots[16].out_uop.iq_type[1]
connect issue_slots[15].in_uop.bits.iq_type[2], issue_slots[16].out_uop.iq_type[2]
connect issue_slots[15].in_uop.bits.iq_type[3], issue_slots[16].out_uop.iq_type[3]
connect issue_slots[15].in_uop.bits.debug_pc, issue_slots[16].out_uop.debug_pc
connect issue_slots[15].in_uop.bits.is_rvc, issue_slots[16].out_uop.is_rvc
connect issue_slots[15].in_uop.bits.debug_inst, issue_slots[16].out_uop.debug_inst
connect issue_slots[15].in_uop.bits.inst, issue_slots[16].out_uop.inst
node _T_192 = eq(shamts_oh[16], UInt<1>(0h1))
when _T_192 :
connect issue_slots[15].in_uop.valid, issue_slots[16].will_be_valid
connect issue_slots[15].in_uop.bits.debug_tsrc, issue_slots[16].out_uop.debug_tsrc
connect issue_slots[15].in_uop.bits.debug_fsrc, issue_slots[16].out_uop.debug_fsrc
connect issue_slots[15].in_uop.bits.bp_xcpt_if, issue_slots[16].out_uop.bp_xcpt_if
connect issue_slots[15].in_uop.bits.bp_debug_if, issue_slots[16].out_uop.bp_debug_if
connect issue_slots[15].in_uop.bits.xcpt_ma_if, issue_slots[16].out_uop.xcpt_ma_if
connect issue_slots[15].in_uop.bits.xcpt_ae_if, issue_slots[16].out_uop.xcpt_ae_if
connect issue_slots[15].in_uop.bits.xcpt_pf_if, issue_slots[16].out_uop.xcpt_pf_if
connect issue_slots[15].in_uop.bits.fp_typ, issue_slots[16].out_uop.fp_typ
connect issue_slots[15].in_uop.bits.fp_rm, issue_slots[16].out_uop.fp_rm
connect issue_slots[15].in_uop.bits.fp_val, issue_slots[16].out_uop.fp_val
connect issue_slots[15].in_uop.bits.fcn_op, issue_slots[16].out_uop.fcn_op
connect issue_slots[15].in_uop.bits.fcn_dw, issue_slots[16].out_uop.fcn_dw
connect issue_slots[15].in_uop.bits.frs3_en, issue_slots[16].out_uop.frs3_en
connect issue_slots[15].in_uop.bits.lrs2_rtype, issue_slots[16].out_uop.lrs2_rtype
connect issue_slots[15].in_uop.bits.lrs1_rtype, issue_slots[16].out_uop.lrs1_rtype
connect issue_slots[15].in_uop.bits.dst_rtype, issue_slots[16].out_uop.dst_rtype
connect issue_slots[15].in_uop.bits.lrs3, issue_slots[16].out_uop.lrs3
connect issue_slots[15].in_uop.bits.lrs2, issue_slots[16].out_uop.lrs2
connect issue_slots[15].in_uop.bits.lrs1, issue_slots[16].out_uop.lrs1
connect issue_slots[15].in_uop.bits.ldst, issue_slots[16].out_uop.ldst
connect issue_slots[15].in_uop.bits.ldst_is_rs1, issue_slots[16].out_uop.ldst_is_rs1
connect issue_slots[15].in_uop.bits.csr_cmd, issue_slots[16].out_uop.csr_cmd
connect issue_slots[15].in_uop.bits.flush_on_commit, issue_slots[16].out_uop.flush_on_commit
connect issue_slots[15].in_uop.bits.is_unique, issue_slots[16].out_uop.is_unique
connect issue_slots[15].in_uop.bits.uses_stq, issue_slots[16].out_uop.uses_stq
connect issue_slots[15].in_uop.bits.uses_ldq, issue_slots[16].out_uop.uses_ldq
connect issue_slots[15].in_uop.bits.mem_signed, issue_slots[16].out_uop.mem_signed
connect issue_slots[15].in_uop.bits.mem_size, issue_slots[16].out_uop.mem_size
connect issue_slots[15].in_uop.bits.mem_cmd, issue_slots[16].out_uop.mem_cmd
connect issue_slots[15].in_uop.bits.exc_cause, issue_slots[16].out_uop.exc_cause
connect issue_slots[15].in_uop.bits.exception, issue_slots[16].out_uop.exception
connect issue_slots[15].in_uop.bits.stale_pdst, issue_slots[16].out_uop.stale_pdst
connect issue_slots[15].in_uop.bits.ppred_busy, issue_slots[16].out_uop.ppred_busy
connect issue_slots[15].in_uop.bits.prs3_busy, issue_slots[16].out_uop.prs3_busy
connect issue_slots[15].in_uop.bits.prs2_busy, issue_slots[16].out_uop.prs2_busy
connect issue_slots[15].in_uop.bits.prs1_busy, issue_slots[16].out_uop.prs1_busy
connect issue_slots[15].in_uop.bits.ppred, issue_slots[16].out_uop.ppred
connect issue_slots[15].in_uop.bits.prs3, issue_slots[16].out_uop.prs3
connect issue_slots[15].in_uop.bits.prs2, issue_slots[16].out_uop.prs2
connect issue_slots[15].in_uop.bits.prs1, issue_slots[16].out_uop.prs1
connect issue_slots[15].in_uop.bits.pdst, issue_slots[16].out_uop.pdst
connect issue_slots[15].in_uop.bits.rxq_idx, issue_slots[16].out_uop.rxq_idx
connect issue_slots[15].in_uop.bits.stq_idx, issue_slots[16].out_uop.stq_idx
connect issue_slots[15].in_uop.bits.ldq_idx, issue_slots[16].out_uop.ldq_idx
connect issue_slots[15].in_uop.bits.rob_idx, issue_slots[16].out_uop.rob_idx
connect issue_slots[15].in_uop.bits.fp_ctrl.vec, issue_slots[16].out_uop.fp_ctrl.vec
connect issue_slots[15].in_uop.bits.fp_ctrl.wflags, issue_slots[16].out_uop.fp_ctrl.wflags
connect issue_slots[15].in_uop.bits.fp_ctrl.sqrt, issue_slots[16].out_uop.fp_ctrl.sqrt
connect issue_slots[15].in_uop.bits.fp_ctrl.div, issue_slots[16].out_uop.fp_ctrl.div
connect issue_slots[15].in_uop.bits.fp_ctrl.fma, issue_slots[16].out_uop.fp_ctrl.fma
connect issue_slots[15].in_uop.bits.fp_ctrl.fastpipe, issue_slots[16].out_uop.fp_ctrl.fastpipe
connect issue_slots[15].in_uop.bits.fp_ctrl.toint, issue_slots[16].out_uop.fp_ctrl.toint
connect issue_slots[15].in_uop.bits.fp_ctrl.fromint, issue_slots[16].out_uop.fp_ctrl.fromint
connect issue_slots[15].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[16].out_uop.fp_ctrl.typeTagOut
connect issue_slots[15].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[16].out_uop.fp_ctrl.typeTagIn
connect issue_slots[15].in_uop.bits.fp_ctrl.swap23, issue_slots[16].out_uop.fp_ctrl.swap23
connect issue_slots[15].in_uop.bits.fp_ctrl.swap12, issue_slots[16].out_uop.fp_ctrl.swap12
connect issue_slots[15].in_uop.bits.fp_ctrl.ren3, issue_slots[16].out_uop.fp_ctrl.ren3
connect issue_slots[15].in_uop.bits.fp_ctrl.ren2, issue_slots[16].out_uop.fp_ctrl.ren2
connect issue_slots[15].in_uop.bits.fp_ctrl.ren1, issue_slots[16].out_uop.fp_ctrl.ren1
connect issue_slots[15].in_uop.bits.fp_ctrl.wen, issue_slots[16].out_uop.fp_ctrl.wen
connect issue_slots[15].in_uop.bits.fp_ctrl.ldst, issue_slots[16].out_uop.fp_ctrl.ldst
connect issue_slots[15].in_uop.bits.op2_sel, issue_slots[16].out_uop.op2_sel
connect issue_slots[15].in_uop.bits.op1_sel, issue_slots[16].out_uop.op1_sel
connect issue_slots[15].in_uop.bits.imm_packed, issue_slots[16].out_uop.imm_packed
connect issue_slots[15].in_uop.bits.pimm, issue_slots[16].out_uop.pimm
connect issue_slots[15].in_uop.bits.imm_sel, issue_slots[16].out_uop.imm_sel
connect issue_slots[15].in_uop.bits.imm_rename, issue_slots[16].out_uop.imm_rename
connect issue_slots[15].in_uop.bits.taken, issue_slots[16].out_uop.taken
connect issue_slots[15].in_uop.bits.pc_lob, issue_slots[16].out_uop.pc_lob
connect issue_slots[15].in_uop.bits.edge_inst, issue_slots[16].out_uop.edge_inst
connect issue_slots[15].in_uop.bits.ftq_idx, issue_slots[16].out_uop.ftq_idx
connect issue_slots[15].in_uop.bits.is_mov, issue_slots[16].out_uop.is_mov
connect issue_slots[15].in_uop.bits.is_rocc, issue_slots[16].out_uop.is_rocc
connect issue_slots[15].in_uop.bits.is_sys_pc2epc, issue_slots[16].out_uop.is_sys_pc2epc
connect issue_slots[15].in_uop.bits.is_eret, issue_slots[16].out_uop.is_eret
connect issue_slots[15].in_uop.bits.is_amo, issue_slots[16].out_uop.is_amo
connect issue_slots[15].in_uop.bits.is_sfence, issue_slots[16].out_uop.is_sfence
connect issue_slots[15].in_uop.bits.is_fencei, issue_slots[16].out_uop.is_fencei
connect issue_slots[15].in_uop.bits.is_fence, issue_slots[16].out_uop.is_fence
connect issue_slots[15].in_uop.bits.is_sfb, issue_slots[16].out_uop.is_sfb
connect issue_slots[15].in_uop.bits.br_type, issue_slots[16].out_uop.br_type
connect issue_slots[15].in_uop.bits.br_tag, issue_slots[16].out_uop.br_tag
connect issue_slots[15].in_uop.bits.br_mask, issue_slots[16].out_uop.br_mask
connect issue_slots[15].in_uop.bits.dis_col_sel, issue_slots[16].out_uop.dis_col_sel
connect issue_slots[15].in_uop.bits.iw_p3_bypass_hint, issue_slots[16].out_uop.iw_p3_bypass_hint
connect issue_slots[15].in_uop.bits.iw_p2_bypass_hint, issue_slots[16].out_uop.iw_p2_bypass_hint
connect issue_slots[15].in_uop.bits.iw_p1_bypass_hint, issue_slots[16].out_uop.iw_p1_bypass_hint
connect issue_slots[15].in_uop.bits.iw_p2_speculative_child, issue_slots[16].out_uop.iw_p2_speculative_child
connect issue_slots[15].in_uop.bits.iw_p1_speculative_child, issue_slots[16].out_uop.iw_p1_speculative_child
connect issue_slots[15].in_uop.bits.iw_issued_partial_dgen, issue_slots[16].out_uop.iw_issued_partial_dgen
connect issue_slots[15].in_uop.bits.iw_issued_partial_agen, issue_slots[16].out_uop.iw_issued_partial_agen
connect issue_slots[15].in_uop.bits.iw_issued, issue_slots[16].out_uop.iw_issued
connect issue_slots[15].in_uop.bits.fu_code[0], issue_slots[16].out_uop.fu_code[0]
connect issue_slots[15].in_uop.bits.fu_code[1], issue_slots[16].out_uop.fu_code[1]
connect issue_slots[15].in_uop.bits.fu_code[2], issue_slots[16].out_uop.fu_code[2]
connect issue_slots[15].in_uop.bits.fu_code[3], issue_slots[16].out_uop.fu_code[3]
connect issue_slots[15].in_uop.bits.fu_code[4], issue_slots[16].out_uop.fu_code[4]
connect issue_slots[15].in_uop.bits.fu_code[5], issue_slots[16].out_uop.fu_code[5]
connect issue_slots[15].in_uop.bits.fu_code[6], issue_slots[16].out_uop.fu_code[6]
connect issue_slots[15].in_uop.bits.fu_code[7], issue_slots[16].out_uop.fu_code[7]
connect issue_slots[15].in_uop.bits.fu_code[8], issue_slots[16].out_uop.fu_code[8]
connect issue_slots[15].in_uop.bits.fu_code[9], issue_slots[16].out_uop.fu_code[9]
connect issue_slots[15].in_uop.bits.iq_type[0], issue_slots[16].out_uop.iq_type[0]
connect issue_slots[15].in_uop.bits.iq_type[1], issue_slots[16].out_uop.iq_type[1]
connect issue_slots[15].in_uop.bits.iq_type[2], issue_slots[16].out_uop.iq_type[2]
connect issue_slots[15].in_uop.bits.iq_type[3], issue_slots[16].out_uop.iq_type[3]
connect issue_slots[15].in_uop.bits.debug_pc, issue_slots[16].out_uop.debug_pc
connect issue_slots[15].in_uop.bits.is_rvc, issue_slots[16].out_uop.is_rvc
connect issue_slots[15].in_uop.bits.debug_inst, issue_slots[16].out_uop.debug_inst
connect issue_slots[15].in_uop.bits.inst, issue_slots[16].out_uop.inst
node _T_193 = eq(shamts_oh[17], UInt<2>(0h2))
when _T_193 :
connect issue_slots[15].in_uop.valid, issue_slots[17].will_be_valid
connect issue_slots[15].in_uop.bits.debug_tsrc, issue_slots[17].out_uop.debug_tsrc
connect issue_slots[15].in_uop.bits.debug_fsrc, issue_slots[17].out_uop.debug_fsrc
connect issue_slots[15].in_uop.bits.bp_xcpt_if, issue_slots[17].out_uop.bp_xcpt_if
connect issue_slots[15].in_uop.bits.bp_debug_if, issue_slots[17].out_uop.bp_debug_if
connect issue_slots[15].in_uop.bits.xcpt_ma_if, issue_slots[17].out_uop.xcpt_ma_if
connect issue_slots[15].in_uop.bits.xcpt_ae_if, issue_slots[17].out_uop.xcpt_ae_if
connect issue_slots[15].in_uop.bits.xcpt_pf_if, issue_slots[17].out_uop.xcpt_pf_if
connect issue_slots[15].in_uop.bits.fp_typ, issue_slots[17].out_uop.fp_typ
connect issue_slots[15].in_uop.bits.fp_rm, issue_slots[17].out_uop.fp_rm
connect issue_slots[15].in_uop.bits.fp_val, issue_slots[17].out_uop.fp_val
connect issue_slots[15].in_uop.bits.fcn_op, issue_slots[17].out_uop.fcn_op
connect issue_slots[15].in_uop.bits.fcn_dw, issue_slots[17].out_uop.fcn_dw
connect issue_slots[15].in_uop.bits.frs3_en, issue_slots[17].out_uop.frs3_en
connect issue_slots[15].in_uop.bits.lrs2_rtype, issue_slots[17].out_uop.lrs2_rtype
connect issue_slots[15].in_uop.bits.lrs1_rtype, issue_slots[17].out_uop.lrs1_rtype
connect issue_slots[15].in_uop.bits.dst_rtype, issue_slots[17].out_uop.dst_rtype
connect issue_slots[15].in_uop.bits.lrs3, issue_slots[17].out_uop.lrs3
connect issue_slots[15].in_uop.bits.lrs2, issue_slots[17].out_uop.lrs2
connect issue_slots[15].in_uop.bits.lrs1, issue_slots[17].out_uop.lrs1
connect issue_slots[15].in_uop.bits.ldst, issue_slots[17].out_uop.ldst
connect issue_slots[15].in_uop.bits.ldst_is_rs1, issue_slots[17].out_uop.ldst_is_rs1
connect issue_slots[15].in_uop.bits.csr_cmd, issue_slots[17].out_uop.csr_cmd
connect issue_slots[15].in_uop.bits.flush_on_commit, issue_slots[17].out_uop.flush_on_commit
connect issue_slots[15].in_uop.bits.is_unique, issue_slots[17].out_uop.is_unique
connect issue_slots[15].in_uop.bits.uses_stq, issue_slots[17].out_uop.uses_stq
connect issue_slots[15].in_uop.bits.uses_ldq, issue_slots[17].out_uop.uses_ldq
connect issue_slots[15].in_uop.bits.mem_signed, issue_slots[17].out_uop.mem_signed
connect issue_slots[15].in_uop.bits.mem_size, issue_slots[17].out_uop.mem_size
connect issue_slots[15].in_uop.bits.mem_cmd, issue_slots[17].out_uop.mem_cmd
connect issue_slots[15].in_uop.bits.exc_cause, issue_slots[17].out_uop.exc_cause
connect issue_slots[15].in_uop.bits.exception, issue_slots[17].out_uop.exception
connect issue_slots[15].in_uop.bits.stale_pdst, issue_slots[17].out_uop.stale_pdst
connect issue_slots[15].in_uop.bits.ppred_busy, issue_slots[17].out_uop.ppred_busy
connect issue_slots[15].in_uop.bits.prs3_busy, issue_slots[17].out_uop.prs3_busy
connect issue_slots[15].in_uop.bits.prs2_busy, issue_slots[17].out_uop.prs2_busy
connect issue_slots[15].in_uop.bits.prs1_busy, issue_slots[17].out_uop.prs1_busy
connect issue_slots[15].in_uop.bits.ppred, issue_slots[17].out_uop.ppred
connect issue_slots[15].in_uop.bits.prs3, issue_slots[17].out_uop.prs3
connect issue_slots[15].in_uop.bits.prs2, issue_slots[17].out_uop.prs2
connect issue_slots[15].in_uop.bits.prs1, issue_slots[17].out_uop.prs1
connect issue_slots[15].in_uop.bits.pdst, issue_slots[17].out_uop.pdst
connect issue_slots[15].in_uop.bits.rxq_idx, issue_slots[17].out_uop.rxq_idx
connect issue_slots[15].in_uop.bits.stq_idx, issue_slots[17].out_uop.stq_idx
connect issue_slots[15].in_uop.bits.ldq_idx, issue_slots[17].out_uop.ldq_idx
connect issue_slots[15].in_uop.bits.rob_idx, issue_slots[17].out_uop.rob_idx
connect issue_slots[15].in_uop.bits.fp_ctrl.vec, issue_slots[17].out_uop.fp_ctrl.vec
connect issue_slots[15].in_uop.bits.fp_ctrl.wflags, issue_slots[17].out_uop.fp_ctrl.wflags
connect issue_slots[15].in_uop.bits.fp_ctrl.sqrt, issue_slots[17].out_uop.fp_ctrl.sqrt
connect issue_slots[15].in_uop.bits.fp_ctrl.div, issue_slots[17].out_uop.fp_ctrl.div
connect issue_slots[15].in_uop.bits.fp_ctrl.fma, issue_slots[17].out_uop.fp_ctrl.fma
connect issue_slots[15].in_uop.bits.fp_ctrl.fastpipe, issue_slots[17].out_uop.fp_ctrl.fastpipe
connect issue_slots[15].in_uop.bits.fp_ctrl.toint, issue_slots[17].out_uop.fp_ctrl.toint
connect issue_slots[15].in_uop.bits.fp_ctrl.fromint, issue_slots[17].out_uop.fp_ctrl.fromint
connect issue_slots[15].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[17].out_uop.fp_ctrl.typeTagOut
connect issue_slots[15].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[17].out_uop.fp_ctrl.typeTagIn
connect issue_slots[15].in_uop.bits.fp_ctrl.swap23, issue_slots[17].out_uop.fp_ctrl.swap23
connect issue_slots[15].in_uop.bits.fp_ctrl.swap12, issue_slots[17].out_uop.fp_ctrl.swap12
connect issue_slots[15].in_uop.bits.fp_ctrl.ren3, issue_slots[17].out_uop.fp_ctrl.ren3
connect issue_slots[15].in_uop.bits.fp_ctrl.ren2, issue_slots[17].out_uop.fp_ctrl.ren2
connect issue_slots[15].in_uop.bits.fp_ctrl.ren1, issue_slots[17].out_uop.fp_ctrl.ren1
connect issue_slots[15].in_uop.bits.fp_ctrl.wen, issue_slots[17].out_uop.fp_ctrl.wen
connect issue_slots[15].in_uop.bits.fp_ctrl.ldst, issue_slots[17].out_uop.fp_ctrl.ldst
connect issue_slots[15].in_uop.bits.op2_sel, issue_slots[17].out_uop.op2_sel
connect issue_slots[15].in_uop.bits.op1_sel, issue_slots[17].out_uop.op1_sel
connect issue_slots[15].in_uop.bits.imm_packed, issue_slots[17].out_uop.imm_packed
connect issue_slots[15].in_uop.bits.pimm, issue_slots[17].out_uop.pimm
connect issue_slots[15].in_uop.bits.imm_sel, issue_slots[17].out_uop.imm_sel
connect issue_slots[15].in_uop.bits.imm_rename, issue_slots[17].out_uop.imm_rename
connect issue_slots[15].in_uop.bits.taken, issue_slots[17].out_uop.taken
connect issue_slots[15].in_uop.bits.pc_lob, issue_slots[17].out_uop.pc_lob
connect issue_slots[15].in_uop.bits.edge_inst, issue_slots[17].out_uop.edge_inst
connect issue_slots[15].in_uop.bits.ftq_idx, issue_slots[17].out_uop.ftq_idx
connect issue_slots[15].in_uop.bits.is_mov, issue_slots[17].out_uop.is_mov
connect issue_slots[15].in_uop.bits.is_rocc, issue_slots[17].out_uop.is_rocc
connect issue_slots[15].in_uop.bits.is_sys_pc2epc, issue_slots[17].out_uop.is_sys_pc2epc
connect issue_slots[15].in_uop.bits.is_eret, issue_slots[17].out_uop.is_eret
connect issue_slots[15].in_uop.bits.is_amo, issue_slots[17].out_uop.is_amo
connect issue_slots[15].in_uop.bits.is_sfence, issue_slots[17].out_uop.is_sfence
connect issue_slots[15].in_uop.bits.is_fencei, issue_slots[17].out_uop.is_fencei
connect issue_slots[15].in_uop.bits.is_fence, issue_slots[17].out_uop.is_fence
connect issue_slots[15].in_uop.bits.is_sfb, issue_slots[17].out_uop.is_sfb
connect issue_slots[15].in_uop.bits.br_type, issue_slots[17].out_uop.br_type
connect issue_slots[15].in_uop.bits.br_tag, issue_slots[17].out_uop.br_tag
connect issue_slots[15].in_uop.bits.br_mask, issue_slots[17].out_uop.br_mask
connect issue_slots[15].in_uop.bits.dis_col_sel, issue_slots[17].out_uop.dis_col_sel
connect issue_slots[15].in_uop.bits.iw_p3_bypass_hint, issue_slots[17].out_uop.iw_p3_bypass_hint
connect issue_slots[15].in_uop.bits.iw_p2_bypass_hint, issue_slots[17].out_uop.iw_p2_bypass_hint
connect issue_slots[15].in_uop.bits.iw_p1_bypass_hint, issue_slots[17].out_uop.iw_p1_bypass_hint
connect issue_slots[15].in_uop.bits.iw_p2_speculative_child, issue_slots[17].out_uop.iw_p2_speculative_child
connect issue_slots[15].in_uop.bits.iw_p1_speculative_child, issue_slots[17].out_uop.iw_p1_speculative_child
connect issue_slots[15].in_uop.bits.iw_issued_partial_dgen, issue_slots[17].out_uop.iw_issued_partial_dgen
connect issue_slots[15].in_uop.bits.iw_issued_partial_agen, issue_slots[17].out_uop.iw_issued_partial_agen
connect issue_slots[15].in_uop.bits.iw_issued, issue_slots[17].out_uop.iw_issued
connect issue_slots[15].in_uop.bits.fu_code[0], issue_slots[17].out_uop.fu_code[0]
connect issue_slots[15].in_uop.bits.fu_code[1], issue_slots[17].out_uop.fu_code[1]
connect issue_slots[15].in_uop.bits.fu_code[2], issue_slots[17].out_uop.fu_code[2]
connect issue_slots[15].in_uop.bits.fu_code[3], issue_slots[17].out_uop.fu_code[3]
connect issue_slots[15].in_uop.bits.fu_code[4], issue_slots[17].out_uop.fu_code[4]
connect issue_slots[15].in_uop.bits.fu_code[5], issue_slots[17].out_uop.fu_code[5]
connect issue_slots[15].in_uop.bits.fu_code[6], issue_slots[17].out_uop.fu_code[6]
connect issue_slots[15].in_uop.bits.fu_code[7], issue_slots[17].out_uop.fu_code[7]
connect issue_slots[15].in_uop.bits.fu_code[8], issue_slots[17].out_uop.fu_code[8]
connect issue_slots[15].in_uop.bits.fu_code[9], issue_slots[17].out_uop.fu_code[9]
connect issue_slots[15].in_uop.bits.iq_type[0], issue_slots[17].out_uop.iq_type[0]
connect issue_slots[15].in_uop.bits.iq_type[1], issue_slots[17].out_uop.iq_type[1]
connect issue_slots[15].in_uop.bits.iq_type[2], issue_slots[17].out_uop.iq_type[2]
connect issue_slots[15].in_uop.bits.iq_type[3], issue_slots[17].out_uop.iq_type[3]
connect issue_slots[15].in_uop.bits.debug_pc, issue_slots[17].out_uop.debug_pc
connect issue_slots[15].in_uop.bits.is_rvc, issue_slots[17].out_uop.is_rvc
connect issue_slots[15].in_uop.bits.debug_inst, issue_slots[17].out_uop.debug_inst
connect issue_slots[15].in_uop.bits.inst, issue_slots[17].out_uop.inst
node _issue_slots_15_clear_T = neq(shamts_oh[15], UInt<1>(0h0))
connect issue_slots[15].clear, _issue_slots_15_clear_T
connect issue_slots[16].in_uop.valid, UInt<1>(0h0)
connect issue_slots[16].in_uop.bits.debug_tsrc, issue_slots[17].out_uop.debug_tsrc
connect issue_slots[16].in_uop.bits.debug_fsrc, issue_slots[17].out_uop.debug_fsrc
connect issue_slots[16].in_uop.bits.bp_xcpt_if, issue_slots[17].out_uop.bp_xcpt_if
connect issue_slots[16].in_uop.bits.bp_debug_if, issue_slots[17].out_uop.bp_debug_if
connect issue_slots[16].in_uop.bits.xcpt_ma_if, issue_slots[17].out_uop.xcpt_ma_if
connect issue_slots[16].in_uop.bits.xcpt_ae_if, issue_slots[17].out_uop.xcpt_ae_if
connect issue_slots[16].in_uop.bits.xcpt_pf_if, issue_slots[17].out_uop.xcpt_pf_if
connect issue_slots[16].in_uop.bits.fp_typ, issue_slots[17].out_uop.fp_typ
connect issue_slots[16].in_uop.bits.fp_rm, issue_slots[17].out_uop.fp_rm
connect issue_slots[16].in_uop.bits.fp_val, issue_slots[17].out_uop.fp_val
connect issue_slots[16].in_uop.bits.fcn_op, issue_slots[17].out_uop.fcn_op
connect issue_slots[16].in_uop.bits.fcn_dw, issue_slots[17].out_uop.fcn_dw
connect issue_slots[16].in_uop.bits.frs3_en, issue_slots[17].out_uop.frs3_en
connect issue_slots[16].in_uop.bits.lrs2_rtype, issue_slots[17].out_uop.lrs2_rtype
connect issue_slots[16].in_uop.bits.lrs1_rtype, issue_slots[17].out_uop.lrs1_rtype
connect issue_slots[16].in_uop.bits.dst_rtype, issue_slots[17].out_uop.dst_rtype
connect issue_slots[16].in_uop.bits.lrs3, issue_slots[17].out_uop.lrs3
connect issue_slots[16].in_uop.bits.lrs2, issue_slots[17].out_uop.lrs2
connect issue_slots[16].in_uop.bits.lrs1, issue_slots[17].out_uop.lrs1
connect issue_slots[16].in_uop.bits.ldst, issue_slots[17].out_uop.ldst
connect issue_slots[16].in_uop.bits.ldst_is_rs1, issue_slots[17].out_uop.ldst_is_rs1
connect issue_slots[16].in_uop.bits.csr_cmd, issue_slots[17].out_uop.csr_cmd
connect issue_slots[16].in_uop.bits.flush_on_commit, issue_slots[17].out_uop.flush_on_commit
connect issue_slots[16].in_uop.bits.is_unique, issue_slots[17].out_uop.is_unique
connect issue_slots[16].in_uop.bits.uses_stq, issue_slots[17].out_uop.uses_stq
connect issue_slots[16].in_uop.bits.uses_ldq, issue_slots[17].out_uop.uses_ldq
connect issue_slots[16].in_uop.bits.mem_signed, issue_slots[17].out_uop.mem_signed
connect issue_slots[16].in_uop.bits.mem_size, issue_slots[17].out_uop.mem_size
connect issue_slots[16].in_uop.bits.mem_cmd, issue_slots[17].out_uop.mem_cmd
connect issue_slots[16].in_uop.bits.exc_cause, issue_slots[17].out_uop.exc_cause
connect issue_slots[16].in_uop.bits.exception, issue_slots[17].out_uop.exception
connect issue_slots[16].in_uop.bits.stale_pdst, issue_slots[17].out_uop.stale_pdst
connect issue_slots[16].in_uop.bits.ppred_busy, issue_slots[17].out_uop.ppred_busy
connect issue_slots[16].in_uop.bits.prs3_busy, issue_slots[17].out_uop.prs3_busy
connect issue_slots[16].in_uop.bits.prs2_busy, issue_slots[17].out_uop.prs2_busy
connect issue_slots[16].in_uop.bits.prs1_busy, issue_slots[17].out_uop.prs1_busy
connect issue_slots[16].in_uop.bits.ppred, issue_slots[17].out_uop.ppred
connect issue_slots[16].in_uop.bits.prs3, issue_slots[17].out_uop.prs3
connect issue_slots[16].in_uop.bits.prs2, issue_slots[17].out_uop.prs2
connect issue_slots[16].in_uop.bits.prs1, issue_slots[17].out_uop.prs1
connect issue_slots[16].in_uop.bits.pdst, issue_slots[17].out_uop.pdst
connect issue_slots[16].in_uop.bits.rxq_idx, issue_slots[17].out_uop.rxq_idx
connect issue_slots[16].in_uop.bits.stq_idx, issue_slots[17].out_uop.stq_idx
connect issue_slots[16].in_uop.bits.ldq_idx, issue_slots[17].out_uop.ldq_idx
connect issue_slots[16].in_uop.bits.rob_idx, issue_slots[17].out_uop.rob_idx
connect issue_slots[16].in_uop.bits.fp_ctrl.vec, issue_slots[17].out_uop.fp_ctrl.vec
connect issue_slots[16].in_uop.bits.fp_ctrl.wflags, issue_slots[17].out_uop.fp_ctrl.wflags
connect issue_slots[16].in_uop.bits.fp_ctrl.sqrt, issue_slots[17].out_uop.fp_ctrl.sqrt
connect issue_slots[16].in_uop.bits.fp_ctrl.div, issue_slots[17].out_uop.fp_ctrl.div
connect issue_slots[16].in_uop.bits.fp_ctrl.fma, issue_slots[17].out_uop.fp_ctrl.fma
connect issue_slots[16].in_uop.bits.fp_ctrl.fastpipe, issue_slots[17].out_uop.fp_ctrl.fastpipe
connect issue_slots[16].in_uop.bits.fp_ctrl.toint, issue_slots[17].out_uop.fp_ctrl.toint
connect issue_slots[16].in_uop.bits.fp_ctrl.fromint, issue_slots[17].out_uop.fp_ctrl.fromint
connect issue_slots[16].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[17].out_uop.fp_ctrl.typeTagOut
connect issue_slots[16].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[17].out_uop.fp_ctrl.typeTagIn
connect issue_slots[16].in_uop.bits.fp_ctrl.swap23, issue_slots[17].out_uop.fp_ctrl.swap23
connect issue_slots[16].in_uop.bits.fp_ctrl.swap12, issue_slots[17].out_uop.fp_ctrl.swap12
connect issue_slots[16].in_uop.bits.fp_ctrl.ren3, issue_slots[17].out_uop.fp_ctrl.ren3
connect issue_slots[16].in_uop.bits.fp_ctrl.ren2, issue_slots[17].out_uop.fp_ctrl.ren2
connect issue_slots[16].in_uop.bits.fp_ctrl.ren1, issue_slots[17].out_uop.fp_ctrl.ren1
connect issue_slots[16].in_uop.bits.fp_ctrl.wen, issue_slots[17].out_uop.fp_ctrl.wen
connect issue_slots[16].in_uop.bits.fp_ctrl.ldst, issue_slots[17].out_uop.fp_ctrl.ldst
connect issue_slots[16].in_uop.bits.op2_sel, issue_slots[17].out_uop.op2_sel
connect issue_slots[16].in_uop.bits.op1_sel, issue_slots[17].out_uop.op1_sel
connect issue_slots[16].in_uop.bits.imm_packed, issue_slots[17].out_uop.imm_packed
connect issue_slots[16].in_uop.bits.pimm, issue_slots[17].out_uop.pimm
connect issue_slots[16].in_uop.bits.imm_sel, issue_slots[17].out_uop.imm_sel
connect issue_slots[16].in_uop.bits.imm_rename, issue_slots[17].out_uop.imm_rename
connect issue_slots[16].in_uop.bits.taken, issue_slots[17].out_uop.taken
connect issue_slots[16].in_uop.bits.pc_lob, issue_slots[17].out_uop.pc_lob
connect issue_slots[16].in_uop.bits.edge_inst, issue_slots[17].out_uop.edge_inst
connect issue_slots[16].in_uop.bits.ftq_idx, issue_slots[17].out_uop.ftq_idx
connect issue_slots[16].in_uop.bits.is_mov, issue_slots[17].out_uop.is_mov
connect issue_slots[16].in_uop.bits.is_rocc, issue_slots[17].out_uop.is_rocc
connect issue_slots[16].in_uop.bits.is_sys_pc2epc, issue_slots[17].out_uop.is_sys_pc2epc
connect issue_slots[16].in_uop.bits.is_eret, issue_slots[17].out_uop.is_eret
connect issue_slots[16].in_uop.bits.is_amo, issue_slots[17].out_uop.is_amo
connect issue_slots[16].in_uop.bits.is_sfence, issue_slots[17].out_uop.is_sfence
connect issue_slots[16].in_uop.bits.is_fencei, issue_slots[17].out_uop.is_fencei
connect issue_slots[16].in_uop.bits.is_fence, issue_slots[17].out_uop.is_fence
connect issue_slots[16].in_uop.bits.is_sfb, issue_slots[17].out_uop.is_sfb
connect issue_slots[16].in_uop.bits.br_type, issue_slots[17].out_uop.br_type
connect issue_slots[16].in_uop.bits.br_tag, issue_slots[17].out_uop.br_tag
connect issue_slots[16].in_uop.bits.br_mask, issue_slots[17].out_uop.br_mask
connect issue_slots[16].in_uop.bits.dis_col_sel, issue_slots[17].out_uop.dis_col_sel
connect issue_slots[16].in_uop.bits.iw_p3_bypass_hint, issue_slots[17].out_uop.iw_p3_bypass_hint
connect issue_slots[16].in_uop.bits.iw_p2_bypass_hint, issue_slots[17].out_uop.iw_p2_bypass_hint
connect issue_slots[16].in_uop.bits.iw_p1_bypass_hint, issue_slots[17].out_uop.iw_p1_bypass_hint
connect issue_slots[16].in_uop.bits.iw_p2_speculative_child, issue_slots[17].out_uop.iw_p2_speculative_child
connect issue_slots[16].in_uop.bits.iw_p1_speculative_child, issue_slots[17].out_uop.iw_p1_speculative_child
connect issue_slots[16].in_uop.bits.iw_issued_partial_dgen, issue_slots[17].out_uop.iw_issued_partial_dgen
connect issue_slots[16].in_uop.bits.iw_issued_partial_agen, issue_slots[17].out_uop.iw_issued_partial_agen
connect issue_slots[16].in_uop.bits.iw_issued, issue_slots[17].out_uop.iw_issued
connect issue_slots[16].in_uop.bits.fu_code[0], issue_slots[17].out_uop.fu_code[0]
connect issue_slots[16].in_uop.bits.fu_code[1], issue_slots[17].out_uop.fu_code[1]
connect issue_slots[16].in_uop.bits.fu_code[2], issue_slots[17].out_uop.fu_code[2]
connect issue_slots[16].in_uop.bits.fu_code[3], issue_slots[17].out_uop.fu_code[3]
connect issue_slots[16].in_uop.bits.fu_code[4], issue_slots[17].out_uop.fu_code[4]
connect issue_slots[16].in_uop.bits.fu_code[5], issue_slots[17].out_uop.fu_code[5]
connect issue_slots[16].in_uop.bits.fu_code[6], issue_slots[17].out_uop.fu_code[6]
connect issue_slots[16].in_uop.bits.fu_code[7], issue_slots[17].out_uop.fu_code[7]
connect issue_slots[16].in_uop.bits.fu_code[8], issue_slots[17].out_uop.fu_code[8]
connect issue_slots[16].in_uop.bits.fu_code[9], issue_slots[17].out_uop.fu_code[9]
connect issue_slots[16].in_uop.bits.iq_type[0], issue_slots[17].out_uop.iq_type[0]
connect issue_slots[16].in_uop.bits.iq_type[1], issue_slots[17].out_uop.iq_type[1]
connect issue_slots[16].in_uop.bits.iq_type[2], issue_slots[17].out_uop.iq_type[2]
connect issue_slots[16].in_uop.bits.iq_type[3], issue_slots[17].out_uop.iq_type[3]
connect issue_slots[16].in_uop.bits.debug_pc, issue_slots[17].out_uop.debug_pc
connect issue_slots[16].in_uop.bits.is_rvc, issue_slots[17].out_uop.is_rvc
connect issue_slots[16].in_uop.bits.debug_inst, issue_slots[17].out_uop.debug_inst
connect issue_slots[16].in_uop.bits.inst, issue_slots[17].out_uop.inst
node _T_194 = eq(shamts_oh[17], UInt<1>(0h1))
when _T_194 :
connect issue_slots[16].in_uop.valid, issue_slots[17].will_be_valid
connect issue_slots[16].in_uop.bits.debug_tsrc, issue_slots[17].out_uop.debug_tsrc
connect issue_slots[16].in_uop.bits.debug_fsrc, issue_slots[17].out_uop.debug_fsrc
connect issue_slots[16].in_uop.bits.bp_xcpt_if, issue_slots[17].out_uop.bp_xcpt_if
connect issue_slots[16].in_uop.bits.bp_debug_if, issue_slots[17].out_uop.bp_debug_if
connect issue_slots[16].in_uop.bits.xcpt_ma_if, issue_slots[17].out_uop.xcpt_ma_if
connect issue_slots[16].in_uop.bits.xcpt_ae_if, issue_slots[17].out_uop.xcpt_ae_if
connect issue_slots[16].in_uop.bits.xcpt_pf_if, issue_slots[17].out_uop.xcpt_pf_if
connect issue_slots[16].in_uop.bits.fp_typ, issue_slots[17].out_uop.fp_typ
connect issue_slots[16].in_uop.bits.fp_rm, issue_slots[17].out_uop.fp_rm
connect issue_slots[16].in_uop.bits.fp_val, issue_slots[17].out_uop.fp_val
connect issue_slots[16].in_uop.bits.fcn_op, issue_slots[17].out_uop.fcn_op
connect issue_slots[16].in_uop.bits.fcn_dw, issue_slots[17].out_uop.fcn_dw
connect issue_slots[16].in_uop.bits.frs3_en, issue_slots[17].out_uop.frs3_en
connect issue_slots[16].in_uop.bits.lrs2_rtype, issue_slots[17].out_uop.lrs2_rtype
connect issue_slots[16].in_uop.bits.lrs1_rtype, issue_slots[17].out_uop.lrs1_rtype
connect issue_slots[16].in_uop.bits.dst_rtype, issue_slots[17].out_uop.dst_rtype
connect issue_slots[16].in_uop.bits.lrs3, issue_slots[17].out_uop.lrs3
connect issue_slots[16].in_uop.bits.lrs2, issue_slots[17].out_uop.lrs2
connect issue_slots[16].in_uop.bits.lrs1, issue_slots[17].out_uop.lrs1
connect issue_slots[16].in_uop.bits.ldst, issue_slots[17].out_uop.ldst
connect issue_slots[16].in_uop.bits.ldst_is_rs1, issue_slots[17].out_uop.ldst_is_rs1
connect issue_slots[16].in_uop.bits.csr_cmd, issue_slots[17].out_uop.csr_cmd
connect issue_slots[16].in_uop.bits.flush_on_commit, issue_slots[17].out_uop.flush_on_commit
connect issue_slots[16].in_uop.bits.is_unique, issue_slots[17].out_uop.is_unique
connect issue_slots[16].in_uop.bits.uses_stq, issue_slots[17].out_uop.uses_stq
connect issue_slots[16].in_uop.bits.uses_ldq, issue_slots[17].out_uop.uses_ldq
connect issue_slots[16].in_uop.bits.mem_signed, issue_slots[17].out_uop.mem_signed
connect issue_slots[16].in_uop.bits.mem_size, issue_slots[17].out_uop.mem_size
connect issue_slots[16].in_uop.bits.mem_cmd, issue_slots[17].out_uop.mem_cmd
connect issue_slots[16].in_uop.bits.exc_cause, issue_slots[17].out_uop.exc_cause
connect issue_slots[16].in_uop.bits.exception, issue_slots[17].out_uop.exception
connect issue_slots[16].in_uop.bits.stale_pdst, issue_slots[17].out_uop.stale_pdst
connect issue_slots[16].in_uop.bits.ppred_busy, issue_slots[17].out_uop.ppred_busy
connect issue_slots[16].in_uop.bits.prs3_busy, issue_slots[17].out_uop.prs3_busy
connect issue_slots[16].in_uop.bits.prs2_busy, issue_slots[17].out_uop.prs2_busy
connect issue_slots[16].in_uop.bits.prs1_busy, issue_slots[17].out_uop.prs1_busy
connect issue_slots[16].in_uop.bits.ppred, issue_slots[17].out_uop.ppred
connect issue_slots[16].in_uop.bits.prs3, issue_slots[17].out_uop.prs3
connect issue_slots[16].in_uop.bits.prs2, issue_slots[17].out_uop.prs2
connect issue_slots[16].in_uop.bits.prs1, issue_slots[17].out_uop.prs1
connect issue_slots[16].in_uop.bits.pdst, issue_slots[17].out_uop.pdst
connect issue_slots[16].in_uop.bits.rxq_idx, issue_slots[17].out_uop.rxq_idx
connect issue_slots[16].in_uop.bits.stq_idx, issue_slots[17].out_uop.stq_idx
connect issue_slots[16].in_uop.bits.ldq_idx, issue_slots[17].out_uop.ldq_idx
connect issue_slots[16].in_uop.bits.rob_idx, issue_slots[17].out_uop.rob_idx
connect issue_slots[16].in_uop.bits.fp_ctrl.vec, issue_slots[17].out_uop.fp_ctrl.vec
connect issue_slots[16].in_uop.bits.fp_ctrl.wflags, issue_slots[17].out_uop.fp_ctrl.wflags
connect issue_slots[16].in_uop.bits.fp_ctrl.sqrt, issue_slots[17].out_uop.fp_ctrl.sqrt
connect issue_slots[16].in_uop.bits.fp_ctrl.div, issue_slots[17].out_uop.fp_ctrl.div
connect issue_slots[16].in_uop.bits.fp_ctrl.fma, issue_slots[17].out_uop.fp_ctrl.fma
connect issue_slots[16].in_uop.bits.fp_ctrl.fastpipe, issue_slots[17].out_uop.fp_ctrl.fastpipe
connect issue_slots[16].in_uop.bits.fp_ctrl.toint, issue_slots[17].out_uop.fp_ctrl.toint
connect issue_slots[16].in_uop.bits.fp_ctrl.fromint, issue_slots[17].out_uop.fp_ctrl.fromint
connect issue_slots[16].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[17].out_uop.fp_ctrl.typeTagOut
connect issue_slots[16].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[17].out_uop.fp_ctrl.typeTagIn
connect issue_slots[16].in_uop.bits.fp_ctrl.swap23, issue_slots[17].out_uop.fp_ctrl.swap23
connect issue_slots[16].in_uop.bits.fp_ctrl.swap12, issue_slots[17].out_uop.fp_ctrl.swap12
connect issue_slots[16].in_uop.bits.fp_ctrl.ren3, issue_slots[17].out_uop.fp_ctrl.ren3
connect issue_slots[16].in_uop.bits.fp_ctrl.ren2, issue_slots[17].out_uop.fp_ctrl.ren2
connect issue_slots[16].in_uop.bits.fp_ctrl.ren1, issue_slots[17].out_uop.fp_ctrl.ren1
connect issue_slots[16].in_uop.bits.fp_ctrl.wen, issue_slots[17].out_uop.fp_ctrl.wen
connect issue_slots[16].in_uop.bits.fp_ctrl.ldst, issue_slots[17].out_uop.fp_ctrl.ldst
connect issue_slots[16].in_uop.bits.op2_sel, issue_slots[17].out_uop.op2_sel
connect issue_slots[16].in_uop.bits.op1_sel, issue_slots[17].out_uop.op1_sel
connect issue_slots[16].in_uop.bits.imm_packed, issue_slots[17].out_uop.imm_packed
connect issue_slots[16].in_uop.bits.pimm, issue_slots[17].out_uop.pimm
connect issue_slots[16].in_uop.bits.imm_sel, issue_slots[17].out_uop.imm_sel
connect issue_slots[16].in_uop.bits.imm_rename, issue_slots[17].out_uop.imm_rename
connect issue_slots[16].in_uop.bits.taken, issue_slots[17].out_uop.taken
connect issue_slots[16].in_uop.bits.pc_lob, issue_slots[17].out_uop.pc_lob
connect issue_slots[16].in_uop.bits.edge_inst, issue_slots[17].out_uop.edge_inst
connect issue_slots[16].in_uop.bits.ftq_idx, issue_slots[17].out_uop.ftq_idx
connect issue_slots[16].in_uop.bits.is_mov, issue_slots[17].out_uop.is_mov
connect issue_slots[16].in_uop.bits.is_rocc, issue_slots[17].out_uop.is_rocc
connect issue_slots[16].in_uop.bits.is_sys_pc2epc, issue_slots[17].out_uop.is_sys_pc2epc
connect issue_slots[16].in_uop.bits.is_eret, issue_slots[17].out_uop.is_eret
connect issue_slots[16].in_uop.bits.is_amo, issue_slots[17].out_uop.is_amo
connect issue_slots[16].in_uop.bits.is_sfence, issue_slots[17].out_uop.is_sfence
connect issue_slots[16].in_uop.bits.is_fencei, issue_slots[17].out_uop.is_fencei
connect issue_slots[16].in_uop.bits.is_fence, issue_slots[17].out_uop.is_fence
connect issue_slots[16].in_uop.bits.is_sfb, issue_slots[17].out_uop.is_sfb
connect issue_slots[16].in_uop.bits.br_type, issue_slots[17].out_uop.br_type
connect issue_slots[16].in_uop.bits.br_tag, issue_slots[17].out_uop.br_tag
connect issue_slots[16].in_uop.bits.br_mask, issue_slots[17].out_uop.br_mask
connect issue_slots[16].in_uop.bits.dis_col_sel, issue_slots[17].out_uop.dis_col_sel
connect issue_slots[16].in_uop.bits.iw_p3_bypass_hint, issue_slots[17].out_uop.iw_p3_bypass_hint
connect issue_slots[16].in_uop.bits.iw_p2_bypass_hint, issue_slots[17].out_uop.iw_p2_bypass_hint
connect issue_slots[16].in_uop.bits.iw_p1_bypass_hint, issue_slots[17].out_uop.iw_p1_bypass_hint
connect issue_slots[16].in_uop.bits.iw_p2_speculative_child, issue_slots[17].out_uop.iw_p2_speculative_child
connect issue_slots[16].in_uop.bits.iw_p1_speculative_child, issue_slots[17].out_uop.iw_p1_speculative_child
connect issue_slots[16].in_uop.bits.iw_issued_partial_dgen, issue_slots[17].out_uop.iw_issued_partial_dgen
connect issue_slots[16].in_uop.bits.iw_issued_partial_agen, issue_slots[17].out_uop.iw_issued_partial_agen
connect issue_slots[16].in_uop.bits.iw_issued, issue_slots[17].out_uop.iw_issued
connect issue_slots[16].in_uop.bits.fu_code[0], issue_slots[17].out_uop.fu_code[0]
connect issue_slots[16].in_uop.bits.fu_code[1], issue_slots[17].out_uop.fu_code[1]
connect issue_slots[16].in_uop.bits.fu_code[2], issue_slots[17].out_uop.fu_code[2]
connect issue_slots[16].in_uop.bits.fu_code[3], issue_slots[17].out_uop.fu_code[3]
connect issue_slots[16].in_uop.bits.fu_code[4], issue_slots[17].out_uop.fu_code[4]
connect issue_slots[16].in_uop.bits.fu_code[5], issue_slots[17].out_uop.fu_code[5]
connect issue_slots[16].in_uop.bits.fu_code[6], issue_slots[17].out_uop.fu_code[6]
connect issue_slots[16].in_uop.bits.fu_code[7], issue_slots[17].out_uop.fu_code[7]
connect issue_slots[16].in_uop.bits.fu_code[8], issue_slots[17].out_uop.fu_code[8]
connect issue_slots[16].in_uop.bits.fu_code[9], issue_slots[17].out_uop.fu_code[9]
connect issue_slots[16].in_uop.bits.iq_type[0], issue_slots[17].out_uop.iq_type[0]
connect issue_slots[16].in_uop.bits.iq_type[1], issue_slots[17].out_uop.iq_type[1]
connect issue_slots[16].in_uop.bits.iq_type[2], issue_slots[17].out_uop.iq_type[2]
connect issue_slots[16].in_uop.bits.iq_type[3], issue_slots[17].out_uop.iq_type[3]
connect issue_slots[16].in_uop.bits.debug_pc, issue_slots[17].out_uop.debug_pc
connect issue_slots[16].in_uop.bits.is_rvc, issue_slots[17].out_uop.is_rvc
connect issue_slots[16].in_uop.bits.debug_inst, issue_slots[17].out_uop.debug_inst
connect issue_slots[16].in_uop.bits.inst, issue_slots[17].out_uop.inst
node _T_195 = eq(shamts_oh[18], UInt<2>(0h2))
when _T_195 :
connect issue_slots[16].in_uop.valid, issue_slots[18].will_be_valid
connect issue_slots[16].in_uop.bits.debug_tsrc, issue_slots[18].out_uop.debug_tsrc
connect issue_slots[16].in_uop.bits.debug_fsrc, issue_slots[18].out_uop.debug_fsrc
connect issue_slots[16].in_uop.bits.bp_xcpt_if, issue_slots[18].out_uop.bp_xcpt_if
connect issue_slots[16].in_uop.bits.bp_debug_if, issue_slots[18].out_uop.bp_debug_if
connect issue_slots[16].in_uop.bits.xcpt_ma_if, issue_slots[18].out_uop.xcpt_ma_if
connect issue_slots[16].in_uop.bits.xcpt_ae_if, issue_slots[18].out_uop.xcpt_ae_if
connect issue_slots[16].in_uop.bits.xcpt_pf_if, issue_slots[18].out_uop.xcpt_pf_if
connect issue_slots[16].in_uop.bits.fp_typ, issue_slots[18].out_uop.fp_typ
connect issue_slots[16].in_uop.bits.fp_rm, issue_slots[18].out_uop.fp_rm
connect issue_slots[16].in_uop.bits.fp_val, issue_slots[18].out_uop.fp_val
connect issue_slots[16].in_uop.bits.fcn_op, issue_slots[18].out_uop.fcn_op
connect issue_slots[16].in_uop.bits.fcn_dw, issue_slots[18].out_uop.fcn_dw
connect issue_slots[16].in_uop.bits.frs3_en, issue_slots[18].out_uop.frs3_en
connect issue_slots[16].in_uop.bits.lrs2_rtype, issue_slots[18].out_uop.lrs2_rtype
connect issue_slots[16].in_uop.bits.lrs1_rtype, issue_slots[18].out_uop.lrs1_rtype
connect issue_slots[16].in_uop.bits.dst_rtype, issue_slots[18].out_uop.dst_rtype
connect issue_slots[16].in_uop.bits.lrs3, issue_slots[18].out_uop.lrs3
connect issue_slots[16].in_uop.bits.lrs2, issue_slots[18].out_uop.lrs2
connect issue_slots[16].in_uop.bits.lrs1, issue_slots[18].out_uop.lrs1
connect issue_slots[16].in_uop.bits.ldst, issue_slots[18].out_uop.ldst
connect issue_slots[16].in_uop.bits.ldst_is_rs1, issue_slots[18].out_uop.ldst_is_rs1
connect issue_slots[16].in_uop.bits.csr_cmd, issue_slots[18].out_uop.csr_cmd
connect issue_slots[16].in_uop.bits.flush_on_commit, issue_slots[18].out_uop.flush_on_commit
connect issue_slots[16].in_uop.bits.is_unique, issue_slots[18].out_uop.is_unique
connect issue_slots[16].in_uop.bits.uses_stq, issue_slots[18].out_uop.uses_stq
connect issue_slots[16].in_uop.bits.uses_ldq, issue_slots[18].out_uop.uses_ldq
connect issue_slots[16].in_uop.bits.mem_signed, issue_slots[18].out_uop.mem_signed
connect issue_slots[16].in_uop.bits.mem_size, issue_slots[18].out_uop.mem_size
connect issue_slots[16].in_uop.bits.mem_cmd, issue_slots[18].out_uop.mem_cmd
connect issue_slots[16].in_uop.bits.exc_cause, issue_slots[18].out_uop.exc_cause
connect issue_slots[16].in_uop.bits.exception, issue_slots[18].out_uop.exception
connect issue_slots[16].in_uop.bits.stale_pdst, issue_slots[18].out_uop.stale_pdst
connect issue_slots[16].in_uop.bits.ppred_busy, issue_slots[18].out_uop.ppred_busy
connect issue_slots[16].in_uop.bits.prs3_busy, issue_slots[18].out_uop.prs3_busy
connect issue_slots[16].in_uop.bits.prs2_busy, issue_slots[18].out_uop.prs2_busy
connect issue_slots[16].in_uop.bits.prs1_busy, issue_slots[18].out_uop.prs1_busy
connect issue_slots[16].in_uop.bits.ppred, issue_slots[18].out_uop.ppred
connect issue_slots[16].in_uop.bits.prs3, issue_slots[18].out_uop.prs3
connect issue_slots[16].in_uop.bits.prs2, issue_slots[18].out_uop.prs2
connect issue_slots[16].in_uop.bits.prs1, issue_slots[18].out_uop.prs1
connect issue_slots[16].in_uop.bits.pdst, issue_slots[18].out_uop.pdst
connect issue_slots[16].in_uop.bits.rxq_idx, issue_slots[18].out_uop.rxq_idx
connect issue_slots[16].in_uop.bits.stq_idx, issue_slots[18].out_uop.stq_idx
connect issue_slots[16].in_uop.bits.ldq_idx, issue_slots[18].out_uop.ldq_idx
connect issue_slots[16].in_uop.bits.rob_idx, issue_slots[18].out_uop.rob_idx
connect issue_slots[16].in_uop.bits.fp_ctrl.vec, issue_slots[18].out_uop.fp_ctrl.vec
connect issue_slots[16].in_uop.bits.fp_ctrl.wflags, issue_slots[18].out_uop.fp_ctrl.wflags
connect issue_slots[16].in_uop.bits.fp_ctrl.sqrt, issue_slots[18].out_uop.fp_ctrl.sqrt
connect issue_slots[16].in_uop.bits.fp_ctrl.div, issue_slots[18].out_uop.fp_ctrl.div
connect issue_slots[16].in_uop.bits.fp_ctrl.fma, issue_slots[18].out_uop.fp_ctrl.fma
connect issue_slots[16].in_uop.bits.fp_ctrl.fastpipe, issue_slots[18].out_uop.fp_ctrl.fastpipe
connect issue_slots[16].in_uop.bits.fp_ctrl.toint, issue_slots[18].out_uop.fp_ctrl.toint
connect issue_slots[16].in_uop.bits.fp_ctrl.fromint, issue_slots[18].out_uop.fp_ctrl.fromint
connect issue_slots[16].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[18].out_uop.fp_ctrl.typeTagOut
connect issue_slots[16].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[18].out_uop.fp_ctrl.typeTagIn
connect issue_slots[16].in_uop.bits.fp_ctrl.swap23, issue_slots[18].out_uop.fp_ctrl.swap23
connect issue_slots[16].in_uop.bits.fp_ctrl.swap12, issue_slots[18].out_uop.fp_ctrl.swap12
connect issue_slots[16].in_uop.bits.fp_ctrl.ren3, issue_slots[18].out_uop.fp_ctrl.ren3
connect issue_slots[16].in_uop.bits.fp_ctrl.ren2, issue_slots[18].out_uop.fp_ctrl.ren2
connect issue_slots[16].in_uop.bits.fp_ctrl.ren1, issue_slots[18].out_uop.fp_ctrl.ren1
connect issue_slots[16].in_uop.bits.fp_ctrl.wen, issue_slots[18].out_uop.fp_ctrl.wen
connect issue_slots[16].in_uop.bits.fp_ctrl.ldst, issue_slots[18].out_uop.fp_ctrl.ldst
connect issue_slots[16].in_uop.bits.op2_sel, issue_slots[18].out_uop.op2_sel
connect issue_slots[16].in_uop.bits.op1_sel, issue_slots[18].out_uop.op1_sel
connect issue_slots[16].in_uop.bits.imm_packed, issue_slots[18].out_uop.imm_packed
connect issue_slots[16].in_uop.bits.pimm, issue_slots[18].out_uop.pimm
connect issue_slots[16].in_uop.bits.imm_sel, issue_slots[18].out_uop.imm_sel
connect issue_slots[16].in_uop.bits.imm_rename, issue_slots[18].out_uop.imm_rename
connect issue_slots[16].in_uop.bits.taken, issue_slots[18].out_uop.taken
connect issue_slots[16].in_uop.bits.pc_lob, issue_slots[18].out_uop.pc_lob
connect issue_slots[16].in_uop.bits.edge_inst, issue_slots[18].out_uop.edge_inst
connect issue_slots[16].in_uop.bits.ftq_idx, issue_slots[18].out_uop.ftq_idx
connect issue_slots[16].in_uop.bits.is_mov, issue_slots[18].out_uop.is_mov
connect issue_slots[16].in_uop.bits.is_rocc, issue_slots[18].out_uop.is_rocc
connect issue_slots[16].in_uop.bits.is_sys_pc2epc, issue_slots[18].out_uop.is_sys_pc2epc
connect issue_slots[16].in_uop.bits.is_eret, issue_slots[18].out_uop.is_eret
connect issue_slots[16].in_uop.bits.is_amo, issue_slots[18].out_uop.is_amo
connect issue_slots[16].in_uop.bits.is_sfence, issue_slots[18].out_uop.is_sfence
connect issue_slots[16].in_uop.bits.is_fencei, issue_slots[18].out_uop.is_fencei
connect issue_slots[16].in_uop.bits.is_fence, issue_slots[18].out_uop.is_fence
connect issue_slots[16].in_uop.bits.is_sfb, issue_slots[18].out_uop.is_sfb
connect issue_slots[16].in_uop.bits.br_type, issue_slots[18].out_uop.br_type
connect issue_slots[16].in_uop.bits.br_tag, issue_slots[18].out_uop.br_tag
connect issue_slots[16].in_uop.bits.br_mask, issue_slots[18].out_uop.br_mask
connect issue_slots[16].in_uop.bits.dis_col_sel, issue_slots[18].out_uop.dis_col_sel
connect issue_slots[16].in_uop.bits.iw_p3_bypass_hint, issue_slots[18].out_uop.iw_p3_bypass_hint
connect issue_slots[16].in_uop.bits.iw_p2_bypass_hint, issue_slots[18].out_uop.iw_p2_bypass_hint
connect issue_slots[16].in_uop.bits.iw_p1_bypass_hint, issue_slots[18].out_uop.iw_p1_bypass_hint
connect issue_slots[16].in_uop.bits.iw_p2_speculative_child, issue_slots[18].out_uop.iw_p2_speculative_child
connect issue_slots[16].in_uop.bits.iw_p1_speculative_child, issue_slots[18].out_uop.iw_p1_speculative_child
connect issue_slots[16].in_uop.bits.iw_issued_partial_dgen, issue_slots[18].out_uop.iw_issued_partial_dgen
connect issue_slots[16].in_uop.bits.iw_issued_partial_agen, issue_slots[18].out_uop.iw_issued_partial_agen
connect issue_slots[16].in_uop.bits.iw_issued, issue_slots[18].out_uop.iw_issued
connect issue_slots[16].in_uop.bits.fu_code[0], issue_slots[18].out_uop.fu_code[0]
connect issue_slots[16].in_uop.bits.fu_code[1], issue_slots[18].out_uop.fu_code[1]
connect issue_slots[16].in_uop.bits.fu_code[2], issue_slots[18].out_uop.fu_code[2]
connect issue_slots[16].in_uop.bits.fu_code[3], issue_slots[18].out_uop.fu_code[3]
connect issue_slots[16].in_uop.bits.fu_code[4], issue_slots[18].out_uop.fu_code[4]
connect issue_slots[16].in_uop.bits.fu_code[5], issue_slots[18].out_uop.fu_code[5]
connect issue_slots[16].in_uop.bits.fu_code[6], issue_slots[18].out_uop.fu_code[6]
connect issue_slots[16].in_uop.bits.fu_code[7], issue_slots[18].out_uop.fu_code[7]
connect issue_slots[16].in_uop.bits.fu_code[8], issue_slots[18].out_uop.fu_code[8]
connect issue_slots[16].in_uop.bits.fu_code[9], issue_slots[18].out_uop.fu_code[9]
connect issue_slots[16].in_uop.bits.iq_type[0], issue_slots[18].out_uop.iq_type[0]
connect issue_slots[16].in_uop.bits.iq_type[1], issue_slots[18].out_uop.iq_type[1]
connect issue_slots[16].in_uop.bits.iq_type[2], issue_slots[18].out_uop.iq_type[2]
connect issue_slots[16].in_uop.bits.iq_type[3], issue_slots[18].out_uop.iq_type[3]
connect issue_slots[16].in_uop.bits.debug_pc, issue_slots[18].out_uop.debug_pc
connect issue_slots[16].in_uop.bits.is_rvc, issue_slots[18].out_uop.is_rvc
connect issue_slots[16].in_uop.bits.debug_inst, issue_slots[18].out_uop.debug_inst
connect issue_slots[16].in_uop.bits.inst, issue_slots[18].out_uop.inst
node _issue_slots_16_clear_T = neq(shamts_oh[16], UInt<1>(0h0))
connect issue_slots[16].clear, _issue_slots_16_clear_T
connect issue_slots[17].in_uop.valid, UInt<1>(0h0)
connect issue_slots[17].in_uop.bits.debug_tsrc, issue_slots[18].out_uop.debug_tsrc
connect issue_slots[17].in_uop.bits.debug_fsrc, issue_slots[18].out_uop.debug_fsrc
connect issue_slots[17].in_uop.bits.bp_xcpt_if, issue_slots[18].out_uop.bp_xcpt_if
connect issue_slots[17].in_uop.bits.bp_debug_if, issue_slots[18].out_uop.bp_debug_if
connect issue_slots[17].in_uop.bits.xcpt_ma_if, issue_slots[18].out_uop.xcpt_ma_if
connect issue_slots[17].in_uop.bits.xcpt_ae_if, issue_slots[18].out_uop.xcpt_ae_if
connect issue_slots[17].in_uop.bits.xcpt_pf_if, issue_slots[18].out_uop.xcpt_pf_if
connect issue_slots[17].in_uop.bits.fp_typ, issue_slots[18].out_uop.fp_typ
connect issue_slots[17].in_uop.bits.fp_rm, issue_slots[18].out_uop.fp_rm
connect issue_slots[17].in_uop.bits.fp_val, issue_slots[18].out_uop.fp_val
connect issue_slots[17].in_uop.bits.fcn_op, issue_slots[18].out_uop.fcn_op
connect issue_slots[17].in_uop.bits.fcn_dw, issue_slots[18].out_uop.fcn_dw
connect issue_slots[17].in_uop.bits.frs3_en, issue_slots[18].out_uop.frs3_en
connect issue_slots[17].in_uop.bits.lrs2_rtype, issue_slots[18].out_uop.lrs2_rtype
connect issue_slots[17].in_uop.bits.lrs1_rtype, issue_slots[18].out_uop.lrs1_rtype
connect issue_slots[17].in_uop.bits.dst_rtype, issue_slots[18].out_uop.dst_rtype
connect issue_slots[17].in_uop.bits.lrs3, issue_slots[18].out_uop.lrs3
connect issue_slots[17].in_uop.bits.lrs2, issue_slots[18].out_uop.lrs2
connect issue_slots[17].in_uop.bits.lrs1, issue_slots[18].out_uop.lrs1
connect issue_slots[17].in_uop.bits.ldst, issue_slots[18].out_uop.ldst
connect issue_slots[17].in_uop.bits.ldst_is_rs1, issue_slots[18].out_uop.ldst_is_rs1
connect issue_slots[17].in_uop.bits.csr_cmd, issue_slots[18].out_uop.csr_cmd
connect issue_slots[17].in_uop.bits.flush_on_commit, issue_slots[18].out_uop.flush_on_commit
connect issue_slots[17].in_uop.bits.is_unique, issue_slots[18].out_uop.is_unique
connect issue_slots[17].in_uop.bits.uses_stq, issue_slots[18].out_uop.uses_stq
connect issue_slots[17].in_uop.bits.uses_ldq, issue_slots[18].out_uop.uses_ldq
connect issue_slots[17].in_uop.bits.mem_signed, issue_slots[18].out_uop.mem_signed
connect issue_slots[17].in_uop.bits.mem_size, issue_slots[18].out_uop.mem_size
connect issue_slots[17].in_uop.bits.mem_cmd, issue_slots[18].out_uop.mem_cmd
connect issue_slots[17].in_uop.bits.exc_cause, issue_slots[18].out_uop.exc_cause
connect issue_slots[17].in_uop.bits.exception, issue_slots[18].out_uop.exception
connect issue_slots[17].in_uop.bits.stale_pdst, issue_slots[18].out_uop.stale_pdst
connect issue_slots[17].in_uop.bits.ppred_busy, issue_slots[18].out_uop.ppred_busy
connect issue_slots[17].in_uop.bits.prs3_busy, issue_slots[18].out_uop.prs3_busy
connect issue_slots[17].in_uop.bits.prs2_busy, issue_slots[18].out_uop.prs2_busy
connect issue_slots[17].in_uop.bits.prs1_busy, issue_slots[18].out_uop.prs1_busy
connect issue_slots[17].in_uop.bits.ppred, issue_slots[18].out_uop.ppred
connect issue_slots[17].in_uop.bits.prs3, issue_slots[18].out_uop.prs3
connect issue_slots[17].in_uop.bits.prs2, issue_slots[18].out_uop.prs2
connect issue_slots[17].in_uop.bits.prs1, issue_slots[18].out_uop.prs1
connect issue_slots[17].in_uop.bits.pdst, issue_slots[18].out_uop.pdst
connect issue_slots[17].in_uop.bits.rxq_idx, issue_slots[18].out_uop.rxq_idx
connect issue_slots[17].in_uop.bits.stq_idx, issue_slots[18].out_uop.stq_idx
connect issue_slots[17].in_uop.bits.ldq_idx, issue_slots[18].out_uop.ldq_idx
connect issue_slots[17].in_uop.bits.rob_idx, issue_slots[18].out_uop.rob_idx
connect issue_slots[17].in_uop.bits.fp_ctrl.vec, issue_slots[18].out_uop.fp_ctrl.vec
connect issue_slots[17].in_uop.bits.fp_ctrl.wflags, issue_slots[18].out_uop.fp_ctrl.wflags
connect issue_slots[17].in_uop.bits.fp_ctrl.sqrt, issue_slots[18].out_uop.fp_ctrl.sqrt
connect issue_slots[17].in_uop.bits.fp_ctrl.div, issue_slots[18].out_uop.fp_ctrl.div
connect issue_slots[17].in_uop.bits.fp_ctrl.fma, issue_slots[18].out_uop.fp_ctrl.fma
connect issue_slots[17].in_uop.bits.fp_ctrl.fastpipe, issue_slots[18].out_uop.fp_ctrl.fastpipe
connect issue_slots[17].in_uop.bits.fp_ctrl.toint, issue_slots[18].out_uop.fp_ctrl.toint
connect issue_slots[17].in_uop.bits.fp_ctrl.fromint, issue_slots[18].out_uop.fp_ctrl.fromint
connect issue_slots[17].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[18].out_uop.fp_ctrl.typeTagOut
connect issue_slots[17].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[18].out_uop.fp_ctrl.typeTagIn
connect issue_slots[17].in_uop.bits.fp_ctrl.swap23, issue_slots[18].out_uop.fp_ctrl.swap23
connect issue_slots[17].in_uop.bits.fp_ctrl.swap12, issue_slots[18].out_uop.fp_ctrl.swap12
connect issue_slots[17].in_uop.bits.fp_ctrl.ren3, issue_slots[18].out_uop.fp_ctrl.ren3
connect issue_slots[17].in_uop.bits.fp_ctrl.ren2, issue_slots[18].out_uop.fp_ctrl.ren2
connect issue_slots[17].in_uop.bits.fp_ctrl.ren1, issue_slots[18].out_uop.fp_ctrl.ren1
connect issue_slots[17].in_uop.bits.fp_ctrl.wen, issue_slots[18].out_uop.fp_ctrl.wen
connect issue_slots[17].in_uop.bits.fp_ctrl.ldst, issue_slots[18].out_uop.fp_ctrl.ldst
connect issue_slots[17].in_uop.bits.op2_sel, issue_slots[18].out_uop.op2_sel
connect issue_slots[17].in_uop.bits.op1_sel, issue_slots[18].out_uop.op1_sel
connect issue_slots[17].in_uop.bits.imm_packed, issue_slots[18].out_uop.imm_packed
connect issue_slots[17].in_uop.bits.pimm, issue_slots[18].out_uop.pimm
connect issue_slots[17].in_uop.bits.imm_sel, issue_slots[18].out_uop.imm_sel
connect issue_slots[17].in_uop.bits.imm_rename, issue_slots[18].out_uop.imm_rename
connect issue_slots[17].in_uop.bits.taken, issue_slots[18].out_uop.taken
connect issue_slots[17].in_uop.bits.pc_lob, issue_slots[18].out_uop.pc_lob
connect issue_slots[17].in_uop.bits.edge_inst, issue_slots[18].out_uop.edge_inst
connect issue_slots[17].in_uop.bits.ftq_idx, issue_slots[18].out_uop.ftq_idx
connect issue_slots[17].in_uop.bits.is_mov, issue_slots[18].out_uop.is_mov
connect issue_slots[17].in_uop.bits.is_rocc, issue_slots[18].out_uop.is_rocc
connect issue_slots[17].in_uop.bits.is_sys_pc2epc, issue_slots[18].out_uop.is_sys_pc2epc
connect issue_slots[17].in_uop.bits.is_eret, issue_slots[18].out_uop.is_eret
connect issue_slots[17].in_uop.bits.is_amo, issue_slots[18].out_uop.is_amo
connect issue_slots[17].in_uop.bits.is_sfence, issue_slots[18].out_uop.is_sfence
connect issue_slots[17].in_uop.bits.is_fencei, issue_slots[18].out_uop.is_fencei
connect issue_slots[17].in_uop.bits.is_fence, issue_slots[18].out_uop.is_fence
connect issue_slots[17].in_uop.bits.is_sfb, issue_slots[18].out_uop.is_sfb
connect issue_slots[17].in_uop.bits.br_type, issue_slots[18].out_uop.br_type
connect issue_slots[17].in_uop.bits.br_tag, issue_slots[18].out_uop.br_tag
connect issue_slots[17].in_uop.bits.br_mask, issue_slots[18].out_uop.br_mask
connect issue_slots[17].in_uop.bits.dis_col_sel, issue_slots[18].out_uop.dis_col_sel
connect issue_slots[17].in_uop.bits.iw_p3_bypass_hint, issue_slots[18].out_uop.iw_p3_bypass_hint
connect issue_slots[17].in_uop.bits.iw_p2_bypass_hint, issue_slots[18].out_uop.iw_p2_bypass_hint
connect issue_slots[17].in_uop.bits.iw_p1_bypass_hint, issue_slots[18].out_uop.iw_p1_bypass_hint
connect issue_slots[17].in_uop.bits.iw_p2_speculative_child, issue_slots[18].out_uop.iw_p2_speculative_child
connect issue_slots[17].in_uop.bits.iw_p1_speculative_child, issue_slots[18].out_uop.iw_p1_speculative_child
connect issue_slots[17].in_uop.bits.iw_issued_partial_dgen, issue_slots[18].out_uop.iw_issued_partial_dgen
connect issue_slots[17].in_uop.bits.iw_issued_partial_agen, issue_slots[18].out_uop.iw_issued_partial_agen
connect issue_slots[17].in_uop.bits.iw_issued, issue_slots[18].out_uop.iw_issued
connect issue_slots[17].in_uop.bits.fu_code[0], issue_slots[18].out_uop.fu_code[0]
connect issue_slots[17].in_uop.bits.fu_code[1], issue_slots[18].out_uop.fu_code[1]
connect issue_slots[17].in_uop.bits.fu_code[2], issue_slots[18].out_uop.fu_code[2]
connect issue_slots[17].in_uop.bits.fu_code[3], issue_slots[18].out_uop.fu_code[3]
connect issue_slots[17].in_uop.bits.fu_code[4], issue_slots[18].out_uop.fu_code[4]
connect issue_slots[17].in_uop.bits.fu_code[5], issue_slots[18].out_uop.fu_code[5]
connect issue_slots[17].in_uop.bits.fu_code[6], issue_slots[18].out_uop.fu_code[6]
connect issue_slots[17].in_uop.bits.fu_code[7], issue_slots[18].out_uop.fu_code[7]
connect issue_slots[17].in_uop.bits.fu_code[8], issue_slots[18].out_uop.fu_code[8]
connect issue_slots[17].in_uop.bits.fu_code[9], issue_slots[18].out_uop.fu_code[9]
connect issue_slots[17].in_uop.bits.iq_type[0], issue_slots[18].out_uop.iq_type[0]
connect issue_slots[17].in_uop.bits.iq_type[1], issue_slots[18].out_uop.iq_type[1]
connect issue_slots[17].in_uop.bits.iq_type[2], issue_slots[18].out_uop.iq_type[2]
connect issue_slots[17].in_uop.bits.iq_type[3], issue_slots[18].out_uop.iq_type[3]
connect issue_slots[17].in_uop.bits.debug_pc, issue_slots[18].out_uop.debug_pc
connect issue_slots[17].in_uop.bits.is_rvc, issue_slots[18].out_uop.is_rvc
connect issue_slots[17].in_uop.bits.debug_inst, issue_slots[18].out_uop.debug_inst
connect issue_slots[17].in_uop.bits.inst, issue_slots[18].out_uop.inst
node _T_196 = eq(shamts_oh[18], UInt<1>(0h1))
when _T_196 :
connect issue_slots[17].in_uop.valid, issue_slots[18].will_be_valid
connect issue_slots[17].in_uop.bits.debug_tsrc, issue_slots[18].out_uop.debug_tsrc
connect issue_slots[17].in_uop.bits.debug_fsrc, issue_slots[18].out_uop.debug_fsrc
connect issue_slots[17].in_uop.bits.bp_xcpt_if, issue_slots[18].out_uop.bp_xcpt_if
connect issue_slots[17].in_uop.bits.bp_debug_if, issue_slots[18].out_uop.bp_debug_if
connect issue_slots[17].in_uop.bits.xcpt_ma_if, issue_slots[18].out_uop.xcpt_ma_if
connect issue_slots[17].in_uop.bits.xcpt_ae_if, issue_slots[18].out_uop.xcpt_ae_if
connect issue_slots[17].in_uop.bits.xcpt_pf_if, issue_slots[18].out_uop.xcpt_pf_if
connect issue_slots[17].in_uop.bits.fp_typ, issue_slots[18].out_uop.fp_typ
connect issue_slots[17].in_uop.bits.fp_rm, issue_slots[18].out_uop.fp_rm
connect issue_slots[17].in_uop.bits.fp_val, issue_slots[18].out_uop.fp_val
connect issue_slots[17].in_uop.bits.fcn_op, issue_slots[18].out_uop.fcn_op
connect issue_slots[17].in_uop.bits.fcn_dw, issue_slots[18].out_uop.fcn_dw
connect issue_slots[17].in_uop.bits.frs3_en, issue_slots[18].out_uop.frs3_en
connect issue_slots[17].in_uop.bits.lrs2_rtype, issue_slots[18].out_uop.lrs2_rtype
connect issue_slots[17].in_uop.bits.lrs1_rtype, issue_slots[18].out_uop.lrs1_rtype
connect issue_slots[17].in_uop.bits.dst_rtype, issue_slots[18].out_uop.dst_rtype
connect issue_slots[17].in_uop.bits.lrs3, issue_slots[18].out_uop.lrs3
connect issue_slots[17].in_uop.bits.lrs2, issue_slots[18].out_uop.lrs2
connect issue_slots[17].in_uop.bits.lrs1, issue_slots[18].out_uop.lrs1
connect issue_slots[17].in_uop.bits.ldst, issue_slots[18].out_uop.ldst
connect issue_slots[17].in_uop.bits.ldst_is_rs1, issue_slots[18].out_uop.ldst_is_rs1
connect issue_slots[17].in_uop.bits.csr_cmd, issue_slots[18].out_uop.csr_cmd
connect issue_slots[17].in_uop.bits.flush_on_commit, issue_slots[18].out_uop.flush_on_commit
connect issue_slots[17].in_uop.bits.is_unique, issue_slots[18].out_uop.is_unique
connect issue_slots[17].in_uop.bits.uses_stq, issue_slots[18].out_uop.uses_stq
connect issue_slots[17].in_uop.bits.uses_ldq, issue_slots[18].out_uop.uses_ldq
connect issue_slots[17].in_uop.bits.mem_signed, issue_slots[18].out_uop.mem_signed
connect issue_slots[17].in_uop.bits.mem_size, issue_slots[18].out_uop.mem_size
connect issue_slots[17].in_uop.bits.mem_cmd, issue_slots[18].out_uop.mem_cmd
connect issue_slots[17].in_uop.bits.exc_cause, issue_slots[18].out_uop.exc_cause
connect issue_slots[17].in_uop.bits.exception, issue_slots[18].out_uop.exception
connect issue_slots[17].in_uop.bits.stale_pdst, issue_slots[18].out_uop.stale_pdst
connect issue_slots[17].in_uop.bits.ppred_busy, issue_slots[18].out_uop.ppred_busy
connect issue_slots[17].in_uop.bits.prs3_busy, issue_slots[18].out_uop.prs3_busy
connect issue_slots[17].in_uop.bits.prs2_busy, issue_slots[18].out_uop.prs2_busy
connect issue_slots[17].in_uop.bits.prs1_busy, issue_slots[18].out_uop.prs1_busy
connect issue_slots[17].in_uop.bits.ppred, issue_slots[18].out_uop.ppred
connect issue_slots[17].in_uop.bits.prs3, issue_slots[18].out_uop.prs3
connect issue_slots[17].in_uop.bits.prs2, issue_slots[18].out_uop.prs2
connect issue_slots[17].in_uop.bits.prs1, issue_slots[18].out_uop.prs1
connect issue_slots[17].in_uop.bits.pdst, issue_slots[18].out_uop.pdst
connect issue_slots[17].in_uop.bits.rxq_idx, issue_slots[18].out_uop.rxq_idx
connect issue_slots[17].in_uop.bits.stq_idx, issue_slots[18].out_uop.stq_idx
connect issue_slots[17].in_uop.bits.ldq_idx, issue_slots[18].out_uop.ldq_idx
connect issue_slots[17].in_uop.bits.rob_idx, issue_slots[18].out_uop.rob_idx
connect issue_slots[17].in_uop.bits.fp_ctrl.vec, issue_slots[18].out_uop.fp_ctrl.vec
connect issue_slots[17].in_uop.bits.fp_ctrl.wflags, issue_slots[18].out_uop.fp_ctrl.wflags
connect issue_slots[17].in_uop.bits.fp_ctrl.sqrt, issue_slots[18].out_uop.fp_ctrl.sqrt
connect issue_slots[17].in_uop.bits.fp_ctrl.div, issue_slots[18].out_uop.fp_ctrl.div
connect issue_slots[17].in_uop.bits.fp_ctrl.fma, issue_slots[18].out_uop.fp_ctrl.fma
connect issue_slots[17].in_uop.bits.fp_ctrl.fastpipe, issue_slots[18].out_uop.fp_ctrl.fastpipe
connect issue_slots[17].in_uop.bits.fp_ctrl.toint, issue_slots[18].out_uop.fp_ctrl.toint
connect issue_slots[17].in_uop.bits.fp_ctrl.fromint, issue_slots[18].out_uop.fp_ctrl.fromint
connect issue_slots[17].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[18].out_uop.fp_ctrl.typeTagOut
connect issue_slots[17].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[18].out_uop.fp_ctrl.typeTagIn
connect issue_slots[17].in_uop.bits.fp_ctrl.swap23, issue_slots[18].out_uop.fp_ctrl.swap23
connect issue_slots[17].in_uop.bits.fp_ctrl.swap12, issue_slots[18].out_uop.fp_ctrl.swap12
connect issue_slots[17].in_uop.bits.fp_ctrl.ren3, issue_slots[18].out_uop.fp_ctrl.ren3
connect issue_slots[17].in_uop.bits.fp_ctrl.ren2, issue_slots[18].out_uop.fp_ctrl.ren2
connect issue_slots[17].in_uop.bits.fp_ctrl.ren1, issue_slots[18].out_uop.fp_ctrl.ren1
connect issue_slots[17].in_uop.bits.fp_ctrl.wen, issue_slots[18].out_uop.fp_ctrl.wen
connect issue_slots[17].in_uop.bits.fp_ctrl.ldst, issue_slots[18].out_uop.fp_ctrl.ldst
connect issue_slots[17].in_uop.bits.op2_sel, issue_slots[18].out_uop.op2_sel
connect issue_slots[17].in_uop.bits.op1_sel, issue_slots[18].out_uop.op1_sel
connect issue_slots[17].in_uop.bits.imm_packed, issue_slots[18].out_uop.imm_packed
connect issue_slots[17].in_uop.bits.pimm, issue_slots[18].out_uop.pimm
connect issue_slots[17].in_uop.bits.imm_sel, issue_slots[18].out_uop.imm_sel
connect issue_slots[17].in_uop.bits.imm_rename, issue_slots[18].out_uop.imm_rename
connect issue_slots[17].in_uop.bits.taken, issue_slots[18].out_uop.taken
connect issue_slots[17].in_uop.bits.pc_lob, issue_slots[18].out_uop.pc_lob
connect issue_slots[17].in_uop.bits.edge_inst, issue_slots[18].out_uop.edge_inst
connect issue_slots[17].in_uop.bits.ftq_idx, issue_slots[18].out_uop.ftq_idx
connect issue_slots[17].in_uop.bits.is_mov, issue_slots[18].out_uop.is_mov
connect issue_slots[17].in_uop.bits.is_rocc, issue_slots[18].out_uop.is_rocc
connect issue_slots[17].in_uop.bits.is_sys_pc2epc, issue_slots[18].out_uop.is_sys_pc2epc
connect issue_slots[17].in_uop.bits.is_eret, issue_slots[18].out_uop.is_eret
connect issue_slots[17].in_uop.bits.is_amo, issue_slots[18].out_uop.is_amo
connect issue_slots[17].in_uop.bits.is_sfence, issue_slots[18].out_uop.is_sfence
connect issue_slots[17].in_uop.bits.is_fencei, issue_slots[18].out_uop.is_fencei
connect issue_slots[17].in_uop.bits.is_fence, issue_slots[18].out_uop.is_fence
connect issue_slots[17].in_uop.bits.is_sfb, issue_slots[18].out_uop.is_sfb
connect issue_slots[17].in_uop.bits.br_type, issue_slots[18].out_uop.br_type
connect issue_slots[17].in_uop.bits.br_tag, issue_slots[18].out_uop.br_tag
connect issue_slots[17].in_uop.bits.br_mask, issue_slots[18].out_uop.br_mask
connect issue_slots[17].in_uop.bits.dis_col_sel, issue_slots[18].out_uop.dis_col_sel
connect issue_slots[17].in_uop.bits.iw_p3_bypass_hint, issue_slots[18].out_uop.iw_p3_bypass_hint
connect issue_slots[17].in_uop.bits.iw_p2_bypass_hint, issue_slots[18].out_uop.iw_p2_bypass_hint
connect issue_slots[17].in_uop.bits.iw_p1_bypass_hint, issue_slots[18].out_uop.iw_p1_bypass_hint
connect issue_slots[17].in_uop.bits.iw_p2_speculative_child, issue_slots[18].out_uop.iw_p2_speculative_child
connect issue_slots[17].in_uop.bits.iw_p1_speculative_child, issue_slots[18].out_uop.iw_p1_speculative_child
connect issue_slots[17].in_uop.bits.iw_issued_partial_dgen, issue_slots[18].out_uop.iw_issued_partial_dgen
connect issue_slots[17].in_uop.bits.iw_issued_partial_agen, issue_slots[18].out_uop.iw_issued_partial_agen
connect issue_slots[17].in_uop.bits.iw_issued, issue_slots[18].out_uop.iw_issued
connect issue_slots[17].in_uop.bits.fu_code[0], issue_slots[18].out_uop.fu_code[0]
connect issue_slots[17].in_uop.bits.fu_code[1], issue_slots[18].out_uop.fu_code[1]
connect issue_slots[17].in_uop.bits.fu_code[2], issue_slots[18].out_uop.fu_code[2]
connect issue_slots[17].in_uop.bits.fu_code[3], issue_slots[18].out_uop.fu_code[3]
connect issue_slots[17].in_uop.bits.fu_code[4], issue_slots[18].out_uop.fu_code[4]
connect issue_slots[17].in_uop.bits.fu_code[5], issue_slots[18].out_uop.fu_code[5]
connect issue_slots[17].in_uop.bits.fu_code[6], issue_slots[18].out_uop.fu_code[6]
connect issue_slots[17].in_uop.bits.fu_code[7], issue_slots[18].out_uop.fu_code[7]
connect issue_slots[17].in_uop.bits.fu_code[8], issue_slots[18].out_uop.fu_code[8]
connect issue_slots[17].in_uop.bits.fu_code[9], issue_slots[18].out_uop.fu_code[9]
connect issue_slots[17].in_uop.bits.iq_type[0], issue_slots[18].out_uop.iq_type[0]
connect issue_slots[17].in_uop.bits.iq_type[1], issue_slots[18].out_uop.iq_type[1]
connect issue_slots[17].in_uop.bits.iq_type[2], issue_slots[18].out_uop.iq_type[2]
connect issue_slots[17].in_uop.bits.iq_type[3], issue_slots[18].out_uop.iq_type[3]
connect issue_slots[17].in_uop.bits.debug_pc, issue_slots[18].out_uop.debug_pc
connect issue_slots[17].in_uop.bits.is_rvc, issue_slots[18].out_uop.is_rvc
connect issue_slots[17].in_uop.bits.debug_inst, issue_slots[18].out_uop.debug_inst
connect issue_slots[17].in_uop.bits.inst, issue_slots[18].out_uop.inst
node _T_197 = eq(shamts_oh[19], UInt<2>(0h2))
when _T_197 :
connect issue_slots[17].in_uop.valid, issue_slots[19].will_be_valid
connect issue_slots[17].in_uop.bits.debug_tsrc, issue_slots[19].out_uop.debug_tsrc
connect issue_slots[17].in_uop.bits.debug_fsrc, issue_slots[19].out_uop.debug_fsrc
connect issue_slots[17].in_uop.bits.bp_xcpt_if, issue_slots[19].out_uop.bp_xcpt_if
connect issue_slots[17].in_uop.bits.bp_debug_if, issue_slots[19].out_uop.bp_debug_if
connect issue_slots[17].in_uop.bits.xcpt_ma_if, issue_slots[19].out_uop.xcpt_ma_if
connect issue_slots[17].in_uop.bits.xcpt_ae_if, issue_slots[19].out_uop.xcpt_ae_if
connect issue_slots[17].in_uop.bits.xcpt_pf_if, issue_slots[19].out_uop.xcpt_pf_if
connect issue_slots[17].in_uop.bits.fp_typ, issue_slots[19].out_uop.fp_typ
connect issue_slots[17].in_uop.bits.fp_rm, issue_slots[19].out_uop.fp_rm
connect issue_slots[17].in_uop.bits.fp_val, issue_slots[19].out_uop.fp_val
connect issue_slots[17].in_uop.bits.fcn_op, issue_slots[19].out_uop.fcn_op
connect issue_slots[17].in_uop.bits.fcn_dw, issue_slots[19].out_uop.fcn_dw
connect issue_slots[17].in_uop.bits.frs3_en, issue_slots[19].out_uop.frs3_en
connect issue_slots[17].in_uop.bits.lrs2_rtype, issue_slots[19].out_uop.lrs2_rtype
connect issue_slots[17].in_uop.bits.lrs1_rtype, issue_slots[19].out_uop.lrs1_rtype
connect issue_slots[17].in_uop.bits.dst_rtype, issue_slots[19].out_uop.dst_rtype
connect issue_slots[17].in_uop.bits.lrs3, issue_slots[19].out_uop.lrs3
connect issue_slots[17].in_uop.bits.lrs2, issue_slots[19].out_uop.lrs2
connect issue_slots[17].in_uop.bits.lrs1, issue_slots[19].out_uop.lrs1
connect issue_slots[17].in_uop.bits.ldst, issue_slots[19].out_uop.ldst
connect issue_slots[17].in_uop.bits.ldst_is_rs1, issue_slots[19].out_uop.ldst_is_rs1
connect issue_slots[17].in_uop.bits.csr_cmd, issue_slots[19].out_uop.csr_cmd
connect issue_slots[17].in_uop.bits.flush_on_commit, issue_slots[19].out_uop.flush_on_commit
connect issue_slots[17].in_uop.bits.is_unique, issue_slots[19].out_uop.is_unique
connect issue_slots[17].in_uop.bits.uses_stq, issue_slots[19].out_uop.uses_stq
connect issue_slots[17].in_uop.bits.uses_ldq, issue_slots[19].out_uop.uses_ldq
connect issue_slots[17].in_uop.bits.mem_signed, issue_slots[19].out_uop.mem_signed
connect issue_slots[17].in_uop.bits.mem_size, issue_slots[19].out_uop.mem_size
connect issue_slots[17].in_uop.bits.mem_cmd, issue_slots[19].out_uop.mem_cmd
connect issue_slots[17].in_uop.bits.exc_cause, issue_slots[19].out_uop.exc_cause
connect issue_slots[17].in_uop.bits.exception, issue_slots[19].out_uop.exception
connect issue_slots[17].in_uop.bits.stale_pdst, issue_slots[19].out_uop.stale_pdst
connect issue_slots[17].in_uop.bits.ppred_busy, issue_slots[19].out_uop.ppred_busy
connect issue_slots[17].in_uop.bits.prs3_busy, issue_slots[19].out_uop.prs3_busy
connect issue_slots[17].in_uop.bits.prs2_busy, issue_slots[19].out_uop.prs2_busy
connect issue_slots[17].in_uop.bits.prs1_busy, issue_slots[19].out_uop.prs1_busy
connect issue_slots[17].in_uop.bits.ppred, issue_slots[19].out_uop.ppred
connect issue_slots[17].in_uop.bits.prs3, issue_slots[19].out_uop.prs3
connect issue_slots[17].in_uop.bits.prs2, issue_slots[19].out_uop.prs2
connect issue_slots[17].in_uop.bits.prs1, issue_slots[19].out_uop.prs1
connect issue_slots[17].in_uop.bits.pdst, issue_slots[19].out_uop.pdst
connect issue_slots[17].in_uop.bits.rxq_idx, issue_slots[19].out_uop.rxq_idx
connect issue_slots[17].in_uop.bits.stq_idx, issue_slots[19].out_uop.stq_idx
connect issue_slots[17].in_uop.bits.ldq_idx, issue_slots[19].out_uop.ldq_idx
connect issue_slots[17].in_uop.bits.rob_idx, issue_slots[19].out_uop.rob_idx
connect issue_slots[17].in_uop.bits.fp_ctrl.vec, issue_slots[19].out_uop.fp_ctrl.vec
connect issue_slots[17].in_uop.bits.fp_ctrl.wflags, issue_slots[19].out_uop.fp_ctrl.wflags
connect issue_slots[17].in_uop.bits.fp_ctrl.sqrt, issue_slots[19].out_uop.fp_ctrl.sqrt
connect issue_slots[17].in_uop.bits.fp_ctrl.div, issue_slots[19].out_uop.fp_ctrl.div
connect issue_slots[17].in_uop.bits.fp_ctrl.fma, issue_slots[19].out_uop.fp_ctrl.fma
connect issue_slots[17].in_uop.bits.fp_ctrl.fastpipe, issue_slots[19].out_uop.fp_ctrl.fastpipe
connect issue_slots[17].in_uop.bits.fp_ctrl.toint, issue_slots[19].out_uop.fp_ctrl.toint
connect issue_slots[17].in_uop.bits.fp_ctrl.fromint, issue_slots[19].out_uop.fp_ctrl.fromint
connect issue_slots[17].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[19].out_uop.fp_ctrl.typeTagOut
connect issue_slots[17].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[19].out_uop.fp_ctrl.typeTagIn
connect issue_slots[17].in_uop.bits.fp_ctrl.swap23, issue_slots[19].out_uop.fp_ctrl.swap23
connect issue_slots[17].in_uop.bits.fp_ctrl.swap12, issue_slots[19].out_uop.fp_ctrl.swap12
connect issue_slots[17].in_uop.bits.fp_ctrl.ren3, issue_slots[19].out_uop.fp_ctrl.ren3
connect issue_slots[17].in_uop.bits.fp_ctrl.ren2, issue_slots[19].out_uop.fp_ctrl.ren2
connect issue_slots[17].in_uop.bits.fp_ctrl.ren1, issue_slots[19].out_uop.fp_ctrl.ren1
connect issue_slots[17].in_uop.bits.fp_ctrl.wen, issue_slots[19].out_uop.fp_ctrl.wen
connect issue_slots[17].in_uop.bits.fp_ctrl.ldst, issue_slots[19].out_uop.fp_ctrl.ldst
connect issue_slots[17].in_uop.bits.op2_sel, issue_slots[19].out_uop.op2_sel
connect issue_slots[17].in_uop.bits.op1_sel, issue_slots[19].out_uop.op1_sel
connect issue_slots[17].in_uop.bits.imm_packed, issue_slots[19].out_uop.imm_packed
connect issue_slots[17].in_uop.bits.pimm, issue_slots[19].out_uop.pimm
connect issue_slots[17].in_uop.bits.imm_sel, issue_slots[19].out_uop.imm_sel
connect issue_slots[17].in_uop.bits.imm_rename, issue_slots[19].out_uop.imm_rename
connect issue_slots[17].in_uop.bits.taken, issue_slots[19].out_uop.taken
connect issue_slots[17].in_uop.bits.pc_lob, issue_slots[19].out_uop.pc_lob
connect issue_slots[17].in_uop.bits.edge_inst, issue_slots[19].out_uop.edge_inst
connect issue_slots[17].in_uop.bits.ftq_idx, issue_slots[19].out_uop.ftq_idx
connect issue_slots[17].in_uop.bits.is_mov, issue_slots[19].out_uop.is_mov
connect issue_slots[17].in_uop.bits.is_rocc, issue_slots[19].out_uop.is_rocc
connect issue_slots[17].in_uop.bits.is_sys_pc2epc, issue_slots[19].out_uop.is_sys_pc2epc
connect issue_slots[17].in_uop.bits.is_eret, issue_slots[19].out_uop.is_eret
connect issue_slots[17].in_uop.bits.is_amo, issue_slots[19].out_uop.is_amo
connect issue_slots[17].in_uop.bits.is_sfence, issue_slots[19].out_uop.is_sfence
connect issue_slots[17].in_uop.bits.is_fencei, issue_slots[19].out_uop.is_fencei
connect issue_slots[17].in_uop.bits.is_fence, issue_slots[19].out_uop.is_fence
connect issue_slots[17].in_uop.bits.is_sfb, issue_slots[19].out_uop.is_sfb
connect issue_slots[17].in_uop.bits.br_type, issue_slots[19].out_uop.br_type
connect issue_slots[17].in_uop.bits.br_tag, issue_slots[19].out_uop.br_tag
connect issue_slots[17].in_uop.bits.br_mask, issue_slots[19].out_uop.br_mask
connect issue_slots[17].in_uop.bits.dis_col_sel, issue_slots[19].out_uop.dis_col_sel
connect issue_slots[17].in_uop.bits.iw_p3_bypass_hint, issue_slots[19].out_uop.iw_p3_bypass_hint
connect issue_slots[17].in_uop.bits.iw_p2_bypass_hint, issue_slots[19].out_uop.iw_p2_bypass_hint
connect issue_slots[17].in_uop.bits.iw_p1_bypass_hint, issue_slots[19].out_uop.iw_p1_bypass_hint
connect issue_slots[17].in_uop.bits.iw_p2_speculative_child, issue_slots[19].out_uop.iw_p2_speculative_child
connect issue_slots[17].in_uop.bits.iw_p1_speculative_child, issue_slots[19].out_uop.iw_p1_speculative_child
connect issue_slots[17].in_uop.bits.iw_issued_partial_dgen, issue_slots[19].out_uop.iw_issued_partial_dgen
connect issue_slots[17].in_uop.bits.iw_issued_partial_agen, issue_slots[19].out_uop.iw_issued_partial_agen
connect issue_slots[17].in_uop.bits.iw_issued, issue_slots[19].out_uop.iw_issued
connect issue_slots[17].in_uop.bits.fu_code[0], issue_slots[19].out_uop.fu_code[0]
connect issue_slots[17].in_uop.bits.fu_code[1], issue_slots[19].out_uop.fu_code[1]
connect issue_slots[17].in_uop.bits.fu_code[2], issue_slots[19].out_uop.fu_code[2]
connect issue_slots[17].in_uop.bits.fu_code[3], issue_slots[19].out_uop.fu_code[3]
connect issue_slots[17].in_uop.bits.fu_code[4], issue_slots[19].out_uop.fu_code[4]
connect issue_slots[17].in_uop.bits.fu_code[5], issue_slots[19].out_uop.fu_code[5]
connect issue_slots[17].in_uop.bits.fu_code[6], issue_slots[19].out_uop.fu_code[6]
connect issue_slots[17].in_uop.bits.fu_code[7], issue_slots[19].out_uop.fu_code[7]
connect issue_slots[17].in_uop.bits.fu_code[8], issue_slots[19].out_uop.fu_code[8]
connect issue_slots[17].in_uop.bits.fu_code[9], issue_slots[19].out_uop.fu_code[9]
connect issue_slots[17].in_uop.bits.iq_type[0], issue_slots[19].out_uop.iq_type[0]
connect issue_slots[17].in_uop.bits.iq_type[1], issue_slots[19].out_uop.iq_type[1]
connect issue_slots[17].in_uop.bits.iq_type[2], issue_slots[19].out_uop.iq_type[2]
connect issue_slots[17].in_uop.bits.iq_type[3], issue_slots[19].out_uop.iq_type[3]
connect issue_slots[17].in_uop.bits.debug_pc, issue_slots[19].out_uop.debug_pc
connect issue_slots[17].in_uop.bits.is_rvc, issue_slots[19].out_uop.is_rvc
connect issue_slots[17].in_uop.bits.debug_inst, issue_slots[19].out_uop.debug_inst
connect issue_slots[17].in_uop.bits.inst, issue_slots[19].out_uop.inst
node _issue_slots_17_clear_T = neq(shamts_oh[17], UInt<1>(0h0))
connect issue_slots[17].clear, _issue_slots_17_clear_T
connect issue_slots[18].in_uop.valid, UInt<1>(0h0)
connect issue_slots[18].in_uop.bits.debug_tsrc, issue_slots[19].out_uop.debug_tsrc
connect issue_slots[18].in_uop.bits.debug_fsrc, issue_slots[19].out_uop.debug_fsrc
connect issue_slots[18].in_uop.bits.bp_xcpt_if, issue_slots[19].out_uop.bp_xcpt_if
connect issue_slots[18].in_uop.bits.bp_debug_if, issue_slots[19].out_uop.bp_debug_if
connect issue_slots[18].in_uop.bits.xcpt_ma_if, issue_slots[19].out_uop.xcpt_ma_if
connect issue_slots[18].in_uop.bits.xcpt_ae_if, issue_slots[19].out_uop.xcpt_ae_if
connect issue_slots[18].in_uop.bits.xcpt_pf_if, issue_slots[19].out_uop.xcpt_pf_if
connect issue_slots[18].in_uop.bits.fp_typ, issue_slots[19].out_uop.fp_typ
connect issue_slots[18].in_uop.bits.fp_rm, issue_slots[19].out_uop.fp_rm
connect issue_slots[18].in_uop.bits.fp_val, issue_slots[19].out_uop.fp_val
connect issue_slots[18].in_uop.bits.fcn_op, issue_slots[19].out_uop.fcn_op
connect issue_slots[18].in_uop.bits.fcn_dw, issue_slots[19].out_uop.fcn_dw
connect issue_slots[18].in_uop.bits.frs3_en, issue_slots[19].out_uop.frs3_en
connect issue_slots[18].in_uop.bits.lrs2_rtype, issue_slots[19].out_uop.lrs2_rtype
connect issue_slots[18].in_uop.bits.lrs1_rtype, issue_slots[19].out_uop.lrs1_rtype
connect issue_slots[18].in_uop.bits.dst_rtype, issue_slots[19].out_uop.dst_rtype
connect issue_slots[18].in_uop.bits.lrs3, issue_slots[19].out_uop.lrs3
connect issue_slots[18].in_uop.bits.lrs2, issue_slots[19].out_uop.lrs2
connect issue_slots[18].in_uop.bits.lrs1, issue_slots[19].out_uop.lrs1
connect issue_slots[18].in_uop.bits.ldst, issue_slots[19].out_uop.ldst
connect issue_slots[18].in_uop.bits.ldst_is_rs1, issue_slots[19].out_uop.ldst_is_rs1
connect issue_slots[18].in_uop.bits.csr_cmd, issue_slots[19].out_uop.csr_cmd
connect issue_slots[18].in_uop.bits.flush_on_commit, issue_slots[19].out_uop.flush_on_commit
connect issue_slots[18].in_uop.bits.is_unique, issue_slots[19].out_uop.is_unique
connect issue_slots[18].in_uop.bits.uses_stq, issue_slots[19].out_uop.uses_stq
connect issue_slots[18].in_uop.bits.uses_ldq, issue_slots[19].out_uop.uses_ldq
connect issue_slots[18].in_uop.bits.mem_signed, issue_slots[19].out_uop.mem_signed
connect issue_slots[18].in_uop.bits.mem_size, issue_slots[19].out_uop.mem_size
connect issue_slots[18].in_uop.bits.mem_cmd, issue_slots[19].out_uop.mem_cmd
connect issue_slots[18].in_uop.bits.exc_cause, issue_slots[19].out_uop.exc_cause
connect issue_slots[18].in_uop.bits.exception, issue_slots[19].out_uop.exception
connect issue_slots[18].in_uop.bits.stale_pdst, issue_slots[19].out_uop.stale_pdst
connect issue_slots[18].in_uop.bits.ppred_busy, issue_slots[19].out_uop.ppred_busy
connect issue_slots[18].in_uop.bits.prs3_busy, issue_slots[19].out_uop.prs3_busy
connect issue_slots[18].in_uop.bits.prs2_busy, issue_slots[19].out_uop.prs2_busy
connect issue_slots[18].in_uop.bits.prs1_busy, issue_slots[19].out_uop.prs1_busy
connect issue_slots[18].in_uop.bits.ppred, issue_slots[19].out_uop.ppred
connect issue_slots[18].in_uop.bits.prs3, issue_slots[19].out_uop.prs3
connect issue_slots[18].in_uop.bits.prs2, issue_slots[19].out_uop.prs2
connect issue_slots[18].in_uop.bits.prs1, issue_slots[19].out_uop.prs1
connect issue_slots[18].in_uop.bits.pdst, issue_slots[19].out_uop.pdst
connect issue_slots[18].in_uop.bits.rxq_idx, issue_slots[19].out_uop.rxq_idx
connect issue_slots[18].in_uop.bits.stq_idx, issue_slots[19].out_uop.stq_idx
connect issue_slots[18].in_uop.bits.ldq_idx, issue_slots[19].out_uop.ldq_idx
connect issue_slots[18].in_uop.bits.rob_idx, issue_slots[19].out_uop.rob_idx
connect issue_slots[18].in_uop.bits.fp_ctrl.vec, issue_slots[19].out_uop.fp_ctrl.vec
connect issue_slots[18].in_uop.bits.fp_ctrl.wflags, issue_slots[19].out_uop.fp_ctrl.wflags
connect issue_slots[18].in_uop.bits.fp_ctrl.sqrt, issue_slots[19].out_uop.fp_ctrl.sqrt
connect issue_slots[18].in_uop.bits.fp_ctrl.div, issue_slots[19].out_uop.fp_ctrl.div
connect issue_slots[18].in_uop.bits.fp_ctrl.fma, issue_slots[19].out_uop.fp_ctrl.fma
connect issue_slots[18].in_uop.bits.fp_ctrl.fastpipe, issue_slots[19].out_uop.fp_ctrl.fastpipe
connect issue_slots[18].in_uop.bits.fp_ctrl.toint, issue_slots[19].out_uop.fp_ctrl.toint
connect issue_slots[18].in_uop.bits.fp_ctrl.fromint, issue_slots[19].out_uop.fp_ctrl.fromint
connect issue_slots[18].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[19].out_uop.fp_ctrl.typeTagOut
connect issue_slots[18].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[19].out_uop.fp_ctrl.typeTagIn
connect issue_slots[18].in_uop.bits.fp_ctrl.swap23, issue_slots[19].out_uop.fp_ctrl.swap23
connect issue_slots[18].in_uop.bits.fp_ctrl.swap12, issue_slots[19].out_uop.fp_ctrl.swap12
connect issue_slots[18].in_uop.bits.fp_ctrl.ren3, issue_slots[19].out_uop.fp_ctrl.ren3
connect issue_slots[18].in_uop.bits.fp_ctrl.ren2, issue_slots[19].out_uop.fp_ctrl.ren2
connect issue_slots[18].in_uop.bits.fp_ctrl.ren1, issue_slots[19].out_uop.fp_ctrl.ren1
connect issue_slots[18].in_uop.bits.fp_ctrl.wen, issue_slots[19].out_uop.fp_ctrl.wen
connect issue_slots[18].in_uop.bits.fp_ctrl.ldst, issue_slots[19].out_uop.fp_ctrl.ldst
connect issue_slots[18].in_uop.bits.op2_sel, issue_slots[19].out_uop.op2_sel
connect issue_slots[18].in_uop.bits.op1_sel, issue_slots[19].out_uop.op1_sel
connect issue_slots[18].in_uop.bits.imm_packed, issue_slots[19].out_uop.imm_packed
connect issue_slots[18].in_uop.bits.pimm, issue_slots[19].out_uop.pimm
connect issue_slots[18].in_uop.bits.imm_sel, issue_slots[19].out_uop.imm_sel
connect issue_slots[18].in_uop.bits.imm_rename, issue_slots[19].out_uop.imm_rename
connect issue_slots[18].in_uop.bits.taken, issue_slots[19].out_uop.taken
connect issue_slots[18].in_uop.bits.pc_lob, issue_slots[19].out_uop.pc_lob
connect issue_slots[18].in_uop.bits.edge_inst, issue_slots[19].out_uop.edge_inst
connect issue_slots[18].in_uop.bits.ftq_idx, issue_slots[19].out_uop.ftq_idx
connect issue_slots[18].in_uop.bits.is_mov, issue_slots[19].out_uop.is_mov
connect issue_slots[18].in_uop.bits.is_rocc, issue_slots[19].out_uop.is_rocc
connect issue_slots[18].in_uop.bits.is_sys_pc2epc, issue_slots[19].out_uop.is_sys_pc2epc
connect issue_slots[18].in_uop.bits.is_eret, issue_slots[19].out_uop.is_eret
connect issue_slots[18].in_uop.bits.is_amo, issue_slots[19].out_uop.is_amo
connect issue_slots[18].in_uop.bits.is_sfence, issue_slots[19].out_uop.is_sfence
connect issue_slots[18].in_uop.bits.is_fencei, issue_slots[19].out_uop.is_fencei
connect issue_slots[18].in_uop.bits.is_fence, issue_slots[19].out_uop.is_fence
connect issue_slots[18].in_uop.bits.is_sfb, issue_slots[19].out_uop.is_sfb
connect issue_slots[18].in_uop.bits.br_type, issue_slots[19].out_uop.br_type
connect issue_slots[18].in_uop.bits.br_tag, issue_slots[19].out_uop.br_tag
connect issue_slots[18].in_uop.bits.br_mask, issue_slots[19].out_uop.br_mask
connect issue_slots[18].in_uop.bits.dis_col_sel, issue_slots[19].out_uop.dis_col_sel
connect issue_slots[18].in_uop.bits.iw_p3_bypass_hint, issue_slots[19].out_uop.iw_p3_bypass_hint
connect issue_slots[18].in_uop.bits.iw_p2_bypass_hint, issue_slots[19].out_uop.iw_p2_bypass_hint
connect issue_slots[18].in_uop.bits.iw_p1_bypass_hint, issue_slots[19].out_uop.iw_p1_bypass_hint
connect issue_slots[18].in_uop.bits.iw_p2_speculative_child, issue_slots[19].out_uop.iw_p2_speculative_child
connect issue_slots[18].in_uop.bits.iw_p1_speculative_child, issue_slots[19].out_uop.iw_p1_speculative_child
connect issue_slots[18].in_uop.bits.iw_issued_partial_dgen, issue_slots[19].out_uop.iw_issued_partial_dgen
connect issue_slots[18].in_uop.bits.iw_issued_partial_agen, issue_slots[19].out_uop.iw_issued_partial_agen
connect issue_slots[18].in_uop.bits.iw_issued, issue_slots[19].out_uop.iw_issued
connect issue_slots[18].in_uop.bits.fu_code[0], issue_slots[19].out_uop.fu_code[0]
connect issue_slots[18].in_uop.bits.fu_code[1], issue_slots[19].out_uop.fu_code[1]
connect issue_slots[18].in_uop.bits.fu_code[2], issue_slots[19].out_uop.fu_code[2]
connect issue_slots[18].in_uop.bits.fu_code[3], issue_slots[19].out_uop.fu_code[3]
connect issue_slots[18].in_uop.bits.fu_code[4], issue_slots[19].out_uop.fu_code[4]
connect issue_slots[18].in_uop.bits.fu_code[5], issue_slots[19].out_uop.fu_code[5]
connect issue_slots[18].in_uop.bits.fu_code[6], issue_slots[19].out_uop.fu_code[6]
connect issue_slots[18].in_uop.bits.fu_code[7], issue_slots[19].out_uop.fu_code[7]
connect issue_slots[18].in_uop.bits.fu_code[8], issue_slots[19].out_uop.fu_code[8]
connect issue_slots[18].in_uop.bits.fu_code[9], issue_slots[19].out_uop.fu_code[9]
connect issue_slots[18].in_uop.bits.iq_type[0], issue_slots[19].out_uop.iq_type[0]
connect issue_slots[18].in_uop.bits.iq_type[1], issue_slots[19].out_uop.iq_type[1]
connect issue_slots[18].in_uop.bits.iq_type[2], issue_slots[19].out_uop.iq_type[2]
connect issue_slots[18].in_uop.bits.iq_type[3], issue_slots[19].out_uop.iq_type[3]
connect issue_slots[18].in_uop.bits.debug_pc, issue_slots[19].out_uop.debug_pc
connect issue_slots[18].in_uop.bits.is_rvc, issue_slots[19].out_uop.is_rvc
connect issue_slots[18].in_uop.bits.debug_inst, issue_slots[19].out_uop.debug_inst
connect issue_slots[18].in_uop.bits.inst, issue_slots[19].out_uop.inst
node _T_198 = eq(shamts_oh[19], UInt<1>(0h1))
when _T_198 :
connect issue_slots[18].in_uop.valid, issue_slots[19].will_be_valid
connect issue_slots[18].in_uop.bits.debug_tsrc, issue_slots[19].out_uop.debug_tsrc
connect issue_slots[18].in_uop.bits.debug_fsrc, issue_slots[19].out_uop.debug_fsrc
connect issue_slots[18].in_uop.bits.bp_xcpt_if, issue_slots[19].out_uop.bp_xcpt_if
connect issue_slots[18].in_uop.bits.bp_debug_if, issue_slots[19].out_uop.bp_debug_if
connect issue_slots[18].in_uop.bits.xcpt_ma_if, issue_slots[19].out_uop.xcpt_ma_if
connect issue_slots[18].in_uop.bits.xcpt_ae_if, issue_slots[19].out_uop.xcpt_ae_if
connect issue_slots[18].in_uop.bits.xcpt_pf_if, issue_slots[19].out_uop.xcpt_pf_if
connect issue_slots[18].in_uop.bits.fp_typ, issue_slots[19].out_uop.fp_typ
connect issue_slots[18].in_uop.bits.fp_rm, issue_slots[19].out_uop.fp_rm
connect issue_slots[18].in_uop.bits.fp_val, issue_slots[19].out_uop.fp_val
connect issue_slots[18].in_uop.bits.fcn_op, issue_slots[19].out_uop.fcn_op
connect issue_slots[18].in_uop.bits.fcn_dw, issue_slots[19].out_uop.fcn_dw
connect issue_slots[18].in_uop.bits.frs3_en, issue_slots[19].out_uop.frs3_en
connect issue_slots[18].in_uop.bits.lrs2_rtype, issue_slots[19].out_uop.lrs2_rtype
connect issue_slots[18].in_uop.bits.lrs1_rtype, issue_slots[19].out_uop.lrs1_rtype
connect issue_slots[18].in_uop.bits.dst_rtype, issue_slots[19].out_uop.dst_rtype
connect issue_slots[18].in_uop.bits.lrs3, issue_slots[19].out_uop.lrs3
connect issue_slots[18].in_uop.bits.lrs2, issue_slots[19].out_uop.lrs2
connect issue_slots[18].in_uop.bits.lrs1, issue_slots[19].out_uop.lrs1
connect issue_slots[18].in_uop.bits.ldst, issue_slots[19].out_uop.ldst
connect issue_slots[18].in_uop.bits.ldst_is_rs1, issue_slots[19].out_uop.ldst_is_rs1
connect issue_slots[18].in_uop.bits.csr_cmd, issue_slots[19].out_uop.csr_cmd
connect issue_slots[18].in_uop.bits.flush_on_commit, issue_slots[19].out_uop.flush_on_commit
connect issue_slots[18].in_uop.bits.is_unique, issue_slots[19].out_uop.is_unique
connect issue_slots[18].in_uop.bits.uses_stq, issue_slots[19].out_uop.uses_stq
connect issue_slots[18].in_uop.bits.uses_ldq, issue_slots[19].out_uop.uses_ldq
connect issue_slots[18].in_uop.bits.mem_signed, issue_slots[19].out_uop.mem_signed
connect issue_slots[18].in_uop.bits.mem_size, issue_slots[19].out_uop.mem_size
connect issue_slots[18].in_uop.bits.mem_cmd, issue_slots[19].out_uop.mem_cmd
connect issue_slots[18].in_uop.bits.exc_cause, issue_slots[19].out_uop.exc_cause
connect issue_slots[18].in_uop.bits.exception, issue_slots[19].out_uop.exception
connect issue_slots[18].in_uop.bits.stale_pdst, issue_slots[19].out_uop.stale_pdst
connect issue_slots[18].in_uop.bits.ppred_busy, issue_slots[19].out_uop.ppred_busy
connect issue_slots[18].in_uop.bits.prs3_busy, issue_slots[19].out_uop.prs3_busy
connect issue_slots[18].in_uop.bits.prs2_busy, issue_slots[19].out_uop.prs2_busy
connect issue_slots[18].in_uop.bits.prs1_busy, issue_slots[19].out_uop.prs1_busy
connect issue_slots[18].in_uop.bits.ppred, issue_slots[19].out_uop.ppred
connect issue_slots[18].in_uop.bits.prs3, issue_slots[19].out_uop.prs3
connect issue_slots[18].in_uop.bits.prs2, issue_slots[19].out_uop.prs2
connect issue_slots[18].in_uop.bits.prs1, issue_slots[19].out_uop.prs1
connect issue_slots[18].in_uop.bits.pdst, issue_slots[19].out_uop.pdst
connect issue_slots[18].in_uop.bits.rxq_idx, issue_slots[19].out_uop.rxq_idx
connect issue_slots[18].in_uop.bits.stq_idx, issue_slots[19].out_uop.stq_idx
connect issue_slots[18].in_uop.bits.ldq_idx, issue_slots[19].out_uop.ldq_idx
connect issue_slots[18].in_uop.bits.rob_idx, issue_slots[19].out_uop.rob_idx
connect issue_slots[18].in_uop.bits.fp_ctrl.vec, issue_slots[19].out_uop.fp_ctrl.vec
connect issue_slots[18].in_uop.bits.fp_ctrl.wflags, issue_slots[19].out_uop.fp_ctrl.wflags
connect issue_slots[18].in_uop.bits.fp_ctrl.sqrt, issue_slots[19].out_uop.fp_ctrl.sqrt
connect issue_slots[18].in_uop.bits.fp_ctrl.div, issue_slots[19].out_uop.fp_ctrl.div
connect issue_slots[18].in_uop.bits.fp_ctrl.fma, issue_slots[19].out_uop.fp_ctrl.fma
connect issue_slots[18].in_uop.bits.fp_ctrl.fastpipe, issue_slots[19].out_uop.fp_ctrl.fastpipe
connect issue_slots[18].in_uop.bits.fp_ctrl.toint, issue_slots[19].out_uop.fp_ctrl.toint
connect issue_slots[18].in_uop.bits.fp_ctrl.fromint, issue_slots[19].out_uop.fp_ctrl.fromint
connect issue_slots[18].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[19].out_uop.fp_ctrl.typeTagOut
connect issue_slots[18].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[19].out_uop.fp_ctrl.typeTagIn
connect issue_slots[18].in_uop.bits.fp_ctrl.swap23, issue_slots[19].out_uop.fp_ctrl.swap23
connect issue_slots[18].in_uop.bits.fp_ctrl.swap12, issue_slots[19].out_uop.fp_ctrl.swap12
connect issue_slots[18].in_uop.bits.fp_ctrl.ren3, issue_slots[19].out_uop.fp_ctrl.ren3
connect issue_slots[18].in_uop.bits.fp_ctrl.ren2, issue_slots[19].out_uop.fp_ctrl.ren2
connect issue_slots[18].in_uop.bits.fp_ctrl.ren1, issue_slots[19].out_uop.fp_ctrl.ren1
connect issue_slots[18].in_uop.bits.fp_ctrl.wen, issue_slots[19].out_uop.fp_ctrl.wen
connect issue_slots[18].in_uop.bits.fp_ctrl.ldst, issue_slots[19].out_uop.fp_ctrl.ldst
connect issue_slots[18].in_uop.bits.op2_sel, issue_slots[19].out_uop.op2_sel
connect issue_slots[18].in_uop.bits.op1_sel, issue_slots[19].out_uop.op1_sel
connect issue_slots[18].in_uop.bits.imm_packed, issue_slots[19].out_uop.imm_packed
connect issue_slots[18].in_uop.bits.pimm, issue_slots[19].out_uop.pimm
connect issue_slots[18].in_uop.bits.imm_sel, issue_slots[19].out_uop.imm_sel
connect issue_slots[18].in_uop.bits.imm_rename, issue_slots[19].out_uop.imm_rename
connect issue_slots[18].in_uop.bits.taken, issue_slots[19].out_uop.taken
connect issue_slots[18].in_uop.bits.pc_lob, issue_slots[19].out_uop.pc_lob
connect issue_slots[18].in_uop.bits.edge_inst, issue_slots[19].out_uop.edge_inst
connect issue_slots[18].in_uop.bits.ftq_idx, issue_slots[19].out_uop.ftq_idx
connect issue_slots[18].in_uop.bits.is_mov, issue_slots[19].out_uop.is_mov
connect issue_slots[18].in_uop.bits.is_rocc, issue_slots[19].out_uop.is_rocc
connect issue_slots[18].in_uop.bits.is_sys_pc2epc, issue_slots[19].out_uop.is_sys_pc2epc
connect issue_slots[18].in_uop.bits.is_eret, issue_slots[19].out_uop.is_eret
connect issue_slots[18].in_uop.bits.is_amo, issue_slots[19].out_uop.is_amo
connect issue_slots[18].in_uop.bits.is_sfence, issue_slots[19].out_uop.is_sfence
connect issue_slots[18].in_uop.bits.is_fencei, issue_slots[19].out_uop.is_fencei
connect issue_slots[18].in_uop.bits.is_fence, issue_slots[19].out_uop.is_fence
connect issue_slots[18].in_uop.bits.is_sfb, issue_slots[19].out_uop.is_sfb
connect issue_slots[18].in_uop.bits.br_type, issue_slots[19].out_uop.br_type
connect issue_slots[18].in_uop.bits.br_tag, issue_slots[19].out_uop.br_tag
connect issue_slots[18].in_uop.bits.br_mask, issue_slots[19].out_uop.br_mask
connect issue_slots[18].in_uop.bits.dis_col_sel, issue_slots[19].out_uop.dis_col_sel
connect issue_slots[18].in_uop.bits.iw_p3_bypass_hint, issue_slots[19].out_uop.iw_p3_bypass_hint
connect issue_slots[18].in_uop.bits.iw_p2_bypass_hint, issue_slots[19].out_uop.iw_p2_bypass_hint
connect issue_slots[18].in_uop.bits.iw_p1_bypass_hint, issue_slots[19].out_uop.iw_p1_bypass_hint
connect issue_slots[18].in_uop.bits.iw_p2_speculative_child, issue_slots[19].out_uop.iw_p2_speculative_child
connect issue_slots[18].in_uop.bits.iw_p1_speculative_child, issue_slots[19].out_uop.iw_p1_speculative_child
connect issue_slots[18].in_uop.bits.iw_issued_partial_dgen, issue_slots[19].out_uop.iw_issued_partial_dgen
connect issue_slots[18].in_uop.bits.iw_issued_partial_agen, issue_slots[19].out_uop.iw_issued_partial_agen
connect issue_slots[18].in_uop.bits.iw_issued, issue_slots[19].out_uop.iw_issued
connect issue_slots[18].in_uop.bits.fu_code[0], issue_slots[19].out_uop.fu_code[0]
connect issue_slots[18].in_uop.bits.fu_code[1], issue_slots[19].out_uop.fu_code[1]
connect issue_slots[18].in_uop.bits.fu_code[2], issue_slots[19].out_uop.fu_code[2]
connect issue_slots[18].in_uop.bits.fu_code[3], issue_slots[19].out_uop.fu_code[3]
connect issue_slots[18].in_uop.bits.fu_code[4], issue_slots[19].out_uop.fu_code[4]
connect issue_slots[18].in_uop.bits.fu_code[5], issue_slots[19].out_uop.fu_code[5]
connect issue_slots[18].in_uop.bits.fu_code[6], issue_slots[19].out_uop.fu_code[6]
connect issue_slots[18].in_uop.bits.fu_code[7], issue_slots[19].out_uop.fu_code[7]
connect issue_slots[18].in_uop.bits.fu_code[8], issue_slots[19].out_uop.fu_code[8]
connect issue_slots[18].in_uop.bits.fu_code[9], issue_slots[19].out_uop.fu_code[9]
connect issue_slots[18].in_uop.bits.iq_type[0], issue_slots[19].out_uop.iq_type[0]
connect issue_slots[18].in_uop.bits.iq_type[1], issue_slots[19].out_uop.iq_type[1]
connect issue_slots[18].in_uop.bits.iq_type[2], issue_slots[19].out_uop.iq_type[2]
connect issue_slots[18].in_uop.bits.iq_type[3], issue_slots[19].out_uop.iq_type[3]
connect issue_slots[18].in_uop.bits.debug_pc, issue_slots[19].out_uop.debug_pc
connect issue_slots[18].in_uop.bits.is_rvc, issue_slots[19].out_uop.is_rvc
connect issue_slots[18].in_uop.bits.debug_inst, issue_slots[19].out_uop.debug_inst
connect issue_slots[18].in_uop.bits.inst, issue_slots[19].out_uop.inst
node _T_199 = eq(shamts_oh[20], UInt<2>(0h2))
when _T_199 :
connect issue_slots[18].in_uop.valid, will_be_valid_20
connect issue_slots[18].in_uop.bits.debug_tsrc, _WIRE.debug_tsrc
connect issue_slots[18].in_uop.bits.debug_fsrc, _WIRE.debug_fsrc
connect issue_slots[18].in_uop.bits.bp_xcpt_if, _WIRE.bp_xcpt_if
connect issue_slots[18].in_uop.bits.bp_debug_if, _WIRE.bp_debug_if
connect issue_slots[18].in_uop.bits.xcpt_ma_if, _WIRE.xcpt_ma_if
connect issue_slots[18].in_uop.bits.xcpt_ae_if, _WIRE.xcpt_ae_if
connect issue_slots[18].in_uop.bits.xcpt_pf_if, _WIRE.xcpt_pf_if
connect issue_slots[18].in_uop.bits.fp_typ, _WIRE.fp_typ
connect issue_slots[18].in_uop.bits.fp_rm, _WIRE.fp_rm
connect issue_slots[18].in_uop.bits.fp_val, _WIRE.fp_val
connect issue_slots[18].in_uop.bits.fcn_op, _WIRE.fcn_op
connect issue_slots[18].in_uop.bits.fcn_dw, _WIRE.fcn_dw
connect issue_slots[18].in_uop.bits.frs3_en, _WIRE.frs3_en
connect issue_slots[18].in_uop.bits.lrs2_rtype, _WIRE.lrs2_rtype
connect issue_slots[18].in_uop.bits.lrs1_rtype, _WIRE.lrs1_rtype
connect issue_slots[18].in_uop.bits.dst_rtype, _WIRE.dst_rtype
connect issue_slots[18].in_uop.bits.lrs3, _WIRE.lrs3
connect issue_slots[18].in_uop.bits.lrs2, _WIRE.lrs2
connect issue_slots[18].in_uop.bits.lrs1, _WIRE.lrs1
connect issue_slots[18].in_uop.bits.ldst, _WIRE.ldst
connect issue_slots[18].in_uop.bits.ldst_is_rs1, _WIRE.ldst_is_rs1
connect issue_slots[18].in_uop.bits.csr_cmd, _WIRE.csr_cmd
connect issue_slots[18].in_uop.bits.flush_on_commit, _WIRE.flush_on_commit
connect issue_slots[18].in_uop.bits.is_unique, _WIRE.is_unique
connect issue_slots[18].in_uop.bits.uses_stq, _WIRE.uses_stq
connect issue_slots[18].in_uop.bits.uses_ldq, _WIRE.uses_ldq
connect issue_slots[18].in_uop.bits.mem_signed, _WIRE.mem_signed
connect issue_slots[18].in_uop.bits.mem_size, _WIRE.mem_size
connect issue_slots[18].in_uop.bits.mem_cmd, _WIRE.mem_cmd
connect issue_slots[18].in_uop.bits.exc_cause, _WIRE.exc_cause
connect issue_slots[18].in_uop.bits.exception, _WIRE.exception
connect issue_slots[18].in_uop.bits.stale_pdst, _WIRE.stale_pdst
connect issue_slots[18].in_uop.bits.ppred_busy, _WIRE.ppred_busy
connect issue_slots[18].in_uop.bits.prs3_busy, _WIRE.prs3_busy
connect issue_slots[18].in_uop.bits.prs2_busy, _WIRE.prs2_busy
connect issue_slots[18].in_uop.bits.prs1_busy, _WIRE.prs1_busy
connect issue_slots[18].in_uop.bits.ppred, _WIRE.ppred
connect issue_slots[18].in_uop.bits.prs3, _WIRE.prs3
connect issue_slots[18].in_uop.bits.prs2, _WIRE.prs2
connect issue_slots[18].in_uop.bits.prs1, _WIRE.prs1
connect issue_slots[18].in_uop.bits.pdst, _WIRE.pdst
connect issue_slots[18].in_uop.bits.rxq_idx, _WIRE.rxq_idx
connect issue_slots[18].in_uop.bits.stq_idx, _WIRE.stq_idx
connect issue_slots[18].in_uop.bits.ldq_idx, _WIRE.ldq_idx
connect issue_slots[18].in_uop.bits.rob_idx, _WIRE.rob_idx
connect issue_slots[18].in_uop.bits.fp_ctrl.vec, _WIRE.fp_ctrl.vec
connect issue_slots[18].in_uop.bits.fp_ctrl.wflags, _WIRE.fp_ctrl.wflags
connect issue_slots[18].in_uop.bits.fp_ctrl.sqrt, _WIRE.fp_ctrl.sqrt
connect issue_slots[18].in_uop.bits.fp_ctrl.div, _WIRE.fp_ctrl.div
connect issue_slots[18].in_uop.bits.fp_ctrl.fma, _WIRE.fp_ctrl.fma
connect issue_slots[18].in_uop.bits.fp_ctrl.fastpipe, _WIRE.fp_ctrl.fastpipe
connect issue_slots[18].in_uop.bits.fp_ctrl.toint, _WIRE.fp_ctrl.toint
connect issue_slots[18].in_uop.bits.fp_ctrl.fromint, _WIRE.fp_ctrl.fromint
connect issue_slots[18].in_uop.bits.fp_ctrl.typeTagOut, _WIRE.fp_ctrl.typeTagOut
connect issue_slots[18].in_uop.bits.fp_ctrl.typeTagIn, _WIRE.fp_ctrl.typeTagIn
connect issue_slots[18].in_uop.bits.fp_ctrl.swap23, _WIRE.fp_ctrl.swap23
connect issue_slots[18].in_uop.bits.fp_ctrl.swap12, _WIRE.fp_ctrl.swap12
connect issue_slots[18].in_uop.bits.fp_ctrl.ren3, _WIRE.fp_ctrl.ren3
connect issue_slots[18].in_uop.bits.fp_ctrl.ren2, _WIRE.fp_ctrl.ren2
connect issue_slots[18].in_uop.bits.fp_ctrl.ren1, _WIRE.fp_ctrl.ren1
connect issue_slots[18].in_uop.bits.fp_ctrl.wen, _WIRE.fp_ctrl.wen
connect issue_slots[18].in_uop.bits.fp_ctrl.ldst, _WIRE.fp_ctrl.ldst
connect issue_slots[18].in_uop.bits.op2_sel, _WIRE.op2_sel
connect issue_slots[18].in_uop.bits.op1_sel, _WIRE.op1_sel
connect issue_slots[18].in_uop.bits.imm_packed, _WIRE.imm_packed
connect issue_slots[18].in_uop.bits.pimm, _WIRE.pimm
connect issue_slots[18].in_uop.bits.imm_sel, _WIRE.imm_sel
connect issue_slots[18].in_uop.bits.imm_rename, _WIRE.imm_rename
connect issue_slots[18].in_uop.bits.taken, _WIRE.taken
connect issue_slots[18].in_uop.bits.pc_lob, _WIRE.pc_lob
connect issue_slots[18].in_uop.bits.edge_inst, _WIRE.edge_inst
connect issue_slots[18].in_uop.bits.ftq_idx, _WIRE.ftq_idx
connect issue_slots[18].in_uop.bits.is_mov, _WIRE.is_mov
connect issue_slots[18].in_uop.bits.is_rocc, _WIRE.is_rocc
connect issue_slots[18].in_uop.bits.is_sys_pc2epc, _WIRE.is_sys_pc2epc
connect issue_slots[18].in_uop.bits.is_eret, _WIRE.is_eret
connect issue_slots[18].in_uop.bits.is_amo, _WIRE.is_amo
connect issue_slots[18].in_uop.bits.is_sfence, _WIRE.is_sfence
connect issue_slots[18].in_uop.bits.is_fencei, _WIRE.is_fencei
connect issue_slots[18].in_uop.bits.is_fence, _WIRE.is_fence
connect issue_slots[18].in_uop.bits.is_sfb, _WIRE.is_sfb
connect issue_slots[18].in_uop.bits.br_type, _WIRE.br_type
connect issue_slots[18].in_uop.bits.br_tag, _WIRE.br_tag
connect issue_slots[18].in_uop.bits.br_mask, _WIRE.br_mask
connect issue_slots[18].in_uop.bits.dis_col_sel, _WIRE.dis_col_sel
connect issue_slots[18].in_uop.bits.iw_p3_bypass_hint, _WIRE.iw_p3_bypass_hint
connect issue_slots[18].in_uop.bits.iw_p2_bypass_hint, _WIRE.iw_p2_bypass_hint
connect issue_slots[18].in_uop.bits.iw_p1_bypass_hint, _WIRE.iw_p1_bypass_hint
connect issue_slots[18].in_uop.bits.iw_p2_speculative_child, _WIRE.iw_p2_speculative_child
connect issue_slots[18].in_uop.bits.iw_p1_speculative_child, _WIRE.iw_p1_speculative_child
connect issue_slots[18].in_uop.bits.iw_issued_partial_dgen, _WIRE.iw_issued_partial_dgen
connect issue_slots[18].in_uop.bits.iw_issued_partial_agen, _WIRE.iw_issued_partial_agen
connect issue_slots[18].in_uop.bits.iw_issued, _WIRE.iw_issued
connect issue_slots[18].in_uop.bits.fu_code[0], _WIRE.fu_code[0]
connect issue_slots[18].in_uop.bits.fu_code[1], _WIRE.fu_code[1]
connect issue_slots[18].in_uop.bits.fu_code[2], _WIRE.fu_code[2]
connect issue_slots[18].in_uop.bits.fu_code[3], _WIRE.fu_code[3]
connect issue_slots[18].in_uop.bits.fu_code[4], _WIRE.fu_code[4]
connect issue_slots[18].in_uop.bits.fu_code[5], _WIRE.fu_code[5]
connect issue_slots[18].in_uop.bits.fu_code[6], _WIRE.fu_code[6]
connect issue_slots[18].in_uop.bits.fu_code[7], _WIRE.fu_code[7]
connect issue_slots[18].in_uop.bits.fu_code[8], _WIRE.fu_code[8]
connect issue_slots[18].in_uop.bits.fu_code[9], _WIRE.fu_code[9]
connect issue_slots[18].in_uop.bits.iq_type[0], _WIRE.iq_type[0]
connect issue_slots[18].in_uop.bits.iq_type[1], _WIRE.iq_type[1]
connect issue_slots[18].in_uop.bits.iq_type[2], _WIRE.iq_type[2]
connect issue_slots[18].in_uop.bits.iq_type[3], _WIRE.iq_type[3]
connect issue_slots[18].in_uop.bits.debug_pc, _WIRE.debug_pc
connect issue_slots[18].in_uop.bits.is_rvc, _WIRE.is_rvc
connect issue_slots[18].in_uop.bits.debug_inst, _WIRE.debug_inst
connect issue_slots[18].in_uop.bits.inst, _WIRE.inst
node _issue_slots_18_clear_T = neq(shamts_oh[18], UInt<1>(0h0))
connect issue_slots[18].clear, _issue_slots_18_clear_T
connect issue_slots[19].in_uop.valid, UInt<1>(0h0)
connect issue_slots[19].in_uop.bits.debug_tsrc, _WIRE.debug_tsrc
connect issue_slots[19].in_uop.bits.debug_fsrc, _WIRE.debug_fsrc
connect issue_slots[19].in_uop.bits.bp_xcpt_if, _WIRE.bp_xcpt_if
connect issue_slots[19].in_uop.bits.bp_debug_if, _WIRE.bp_debug_if
connect issue_slots[19].in_uop.bits.xcpt_ma_if, _WIRE.xcpt_ma_if
connect issue_slots[19].in_uop.bits.xcpt_ae_if, _WIRE.xcpt_ae_if
connect issue_slots[19].in_uop.bits.xcpt_pf_if, _WIRE.xcpt_pf_if
connect issue_slots[19].in_uop.bits.fp_typ, _WIRE.fp_typ
connect issue_slots[19].in_uop.bits.fp_rm, _WIRE.fp_rm
connect issue_slots[19].in_uop.bits.fp_val, _WIRE.fp_val
connect issue_slots[19].in_uop.bits.fcn_op, _WIRE.fcn_op
connect issue_slots[19].in_uop.bits.fcn_dw, _WIRE.fcn_dw
connect issue_slots[19].in_uop.bits.frs3_en, _WIRE.frs3_en
connect issue_slots[19].in_uop.bits.lrs2_rtype, _WIRE.lrs2_rtype
connect issue_slots[19].in_uop.bits.lrs1_rtype, _WIRE.lrs1_rtype
connect issue_slots[19].in_uop.bits.dst_rtype, _WIRE.dst_rtype
connect issue_slots[19].in_uop.bits.lrs3, _WIRE.lrs3
connect issue_slots[19].in_uop.bits.lrs2, _WIRE.lrs2
connect issue_slots[19].in_uop.bits.lrs1, _WIRE.lrs1
connect issue_slots[19].in_uop.bits.ldst, _WIRE.ldst
connect issue_slots[19].in_uop.bits.ldst_is_rs1, _WIRE.ldst_is_rs1
connect issue_slots[19].in_uop.bits.csr_cmd, _WIRE.csr_cmd
connect issue_slots[19].in_uop.bits.flush_on_commit, _WIRE.flush_on_commit
connect issue_slots[19].in_uop.bits.is_unique, _WIRE.is_unique
connect issue_slots[19].in_uop.bits.uses_stq, _WIRE.uses_stq
connect issue_slots[19].in_uop.bits.uses_ldq, _WIRE.uses_ldq
connect issue_slots[19].in_uop.bits.mem_signed, _WIRE.mem_signed
connect issue_slots[19].in_uop.bits.mem_size, _WIRE.mem_size
connect issue_slots[19].in_uop.bits.mem_cmd, _WIRE.mem_cmd
connect issue_slots[19].in_uop.bits.exc_cause, _WIRE.exc_cause
connect issue_slots[19].in_uop.bits.exception, _WIRE.exception
connect issue_slots[19].in_uop.bits.stale_pdst, _WIRE.stale_pdst
connect issue_slots[19].in_uop.bits.ppred_busy, _WIRE.ppred_busy
connect issue_slots[19].in_uop.bits.prs3_busy, _WIRE.prs3_busy
connect issue_slots[19].in_uop.bits.prs2_busy, _WIRE.prs2_busy
connect issue_slots[19].in_uop.bits.prs1_busy, _WIRE.prs1_busy
connect issue_slots[19].in_uop.bits.ppred, _WIRE.ppred
connect issue_slots[19].in_uop.bits.prs3, _WIRE.prs3
connect issue_slots[19].in_uop.bits.prs2, _WIRE.prs2
connect issue_slots[19].in_uop.bits.prs1, _WIRE.prs1
connect issue_slots[19].in_uop.bits.pdst, _WIRE.pdst
connect issue_slots[19].in_uop.bits.rxq_idx, _WIRE.rxq_idx
connect issue_slots[19].in_uop.bits.stq_idx, _WIRE.stq_idx
connect issue_slots[19].in_uop.bits.ldq_idx, _WIRE.ldq_idx
connect issue_slots[19].in_uop.bits.rob_idx, _WIRE.rob_idx
connect issue_slots[19].in_uop.bits.fp_ctrl.vec, _WIRE.fp_ctrl.vec
connect issue_slots[19].in_uop.bits.fp_ctrl.wflags, _WIRE.fp_ctrl.wflags
connect issue_slots[19].in_uop.bits.fp_ctrl.sqrt, _WIRE.fp_ctrl.sqrt
connect issue_slots[19].in_uop.bits.fp_ctrl.div, _WIRE.fp_ctrl.div
connect issue_slots[19].in_uop.bits.fp_ctrl.fma, _WIRE.fp_ctrl.fma
connect issue_slots[19].in_uop.bits.fp_ctrl.fastpipe, _WIRE.fp_ctrl.fastpipe
connect issue_slots[19].in_uop.bits.fp_ctrl.toint, _WIRE.fp_ctrl.toint
connect issue_slots[19].in_uop.bits.fp_ctrl.fromint, _WIRE.fp_ctrl.fromint
connect issue_slots[19].in_uop.bits.fp_ctrl.typeTagOut, _WIRE.fp_ctrl.typeTagOut
connect issue_slots[19].in_uop.bits.fp_ctrl.typeTagIn, _WIRE.fp_ctrl.typeTagIn
connect issue_slots[19].in_uop.bits.fp_ctrl.swap23, _WIRE.fp_ctrl.swap23
connect issue_slots[19].in_uop.bits.fp_ctrl.swap12, _WIRE.fp_ctrl.swap12
connect issue_slots[19].in_uop.bits.fp_ctrl.ren3, _WIRE.fp_ctrl.ren3
connect issue_slots[19].in_uop.bits.fp_ctrl.ren2, _WIRE.fp_ctrl.ren2
connect issue_slots[19].in_uop.bits.fp_ctrl.ren1, _WIRE.fp_ctrl.ren1
connect issue_slots[19].in_uop.bits.fp_ctrl.wen, _WIRE.fp_ctrl.wen
connect issue_slots[19].in_uop.bits.fp_ctrl.ldst, _WIRE.fp_ctrl.ldst
connect issue_slots[19].in_uop.bits.op2_sel, _WIRE.op2_sel
connect issue_slots[19].in_uop.bits.op1_sel, _WIRE.op1_sel
connect issue_slots[19].in_uop.bits.imm_packed, _WIRE.imm_packed
connect issue_slots[19].in_uop.bits.pimm, _WIRE.pimm
connect issue_slots[19].in_uop.bits.imm_sel, _WIRE.imm_sel
connect issue_slots[19].in_uop.bits.imm_rename, _WIRE.imm_rename
connect issue_slots[19].in_uop.bits.taken, _WIRE.taken
connect issue_slots[19].in_uop.bits.pc_lob, _WIRE.pc_lob
connect issue_slots[19].in_uop.bits.edge_inst, _WIRE.edge_inst
connect issue_slots[19].in_uop.bits.ftq_idx, _WIRE.ftq_idx
connect issue_slots[19].in_uop.bits.is_mov, _WIRE.is_mov
connect issue_slots[19].in_uop.bits.is_rocc, _WIRE.is_rocc
connect issue_slots[19].in_uop.bits.is_sys_pc2epc, _WIRE.is_sys_pc2epc
connect issue_slots[19].in_uop.bits.is_eret, _WIRE.is_eret
connect issue_slots[19].in_uop.bits.is_amo, _WIRE.is_amo
connect issue_slots[19].in_uop.bits.is_sfence, _WIRE.is_sfence
connect issue_slots[19].in_uop.bits.is_fencei, _WIRE.is_fencei
connect issue_slots[19].in_uop.bits.is_fence, _WIRE.is_fence
connect issue_slots[19].in_uop.bits.is_sfb, _WIRE.is_sfb
connect issue_slots[19].in_uop.bits.br_type, _WIRE.br_type
connect issue_slots[19].in_uop.bits.br_tag, _WIRE.br_tag
connect issue_slots[19].in_uop.bits.br_mask, _WIRE.br_mask
connect issue_slots[19].in_uop.bits.dis_col_sel, _WIRE.dis_col_sel
connect issue_slots[19].in_uop.bits.iw_p3_bypass_hint, _WIRE.iw_p3_bypass_hint
connect issue_slots[19].in_uop.bits.iw_p2_bypass_hint, _WIRE.iw_p2_bypass_hint
connect issue_slots[19].in_uop.bits.iw_p1_bypass_hint, _WIRE.iw_p1_bypass_hint
connect issue_slots[19].in_uop.bits.iw_p2_speculative_child, _WIRE.iw_p2_speculative_child
connect issue_slots[19].in_uop.bits.iw_p1_speculative_child, _WIRE.iw_p1_speculative_child
connect issue_slots[19].in_uop.bits.iw_issued_partial_dgen, _WIRE.iw_issued_partial_dgen
connect issue_slots[19].in_uop.bits.iw_issued_partial_agen, _WIRE.iw_issued_partial_agen
connect issue_slots[19].in_uop.bits.iw_issued, _WIRE.iw_issued
connect issue_slots[19].in_uop.bits.fu_code[0], _WIRE.fu_code[0]
connect issue_slots[19].in_uop.bits.fu_code[1], _WIRE.fu_code[1]
connect issue_slots[19].in_uop.bits.fu_code[2], _WIRE.fu_code[2]
connect issue_slots[19].in_uop.bits.fu_code[3], _WIRE.fu_code[3]
connect issue_slots[19].in_uop.bits.fu_code[4], _WIRE.fu_code[4]
connect issue_slots[19].in_uop.bits.fu_code[5], _WIRE.fu_code[5]
connect issue_slots[19].in_uop.bits.fu_code[6], _WIRE.fu_code[6]
connect issue_slots[19].in_uop.bits.fu_code[7], _WIRE.fu_code[7]
connect issue_slots[19].in_uop.bits.fu_code[8], _WIRE.fu_code[8]
connect issue_slots[19].in_uop.bits.fu_code[9], _WIRE.fu_code[9]
connect issue_slots[19].in_uop.bits.iq_type[0], _WIRE.iq_type[0]
connect issue_slots[19].in_uop.bits.iq_type[1], _WIRE.iq_type[1]
connect issue_slots[19].in_uop.bits.iq_type[2], _WIRE.iq_type[2]
connect issue_slots[19].in_uop.bits.iq_type[3], _WIRE.iq_type[3]
connect issue_slots[19].in_uop.bits.debug_pc, _WIRE.debug_pc
connect issue_slots[19].in_uop.bits.is_rvc, _WIRE.is_rvc
connect issue_slots[19].in_uop.bits.debug_inst, _WIRE.debug_inst
connect issue_slots[19].in_uop.bits.inst, _WIRE.inst
node _T_200 = eq(shamts_oh[20], UInt<1>(0h1))
when _T_200 :
connect issue_slots[19].in_uop.valid, will_be_valid_20
connect issue_slots[19].in_uop.bits.debug_tsrc, _WIRE.debug_tsrc
connect issue_slots[19].in_uop.bits.debug_fsrc, _WIRE.debug_fsrc
connect issue_slots[19].in_uop.bits.bp_xcpt_if, _WIRE.bp_xcpt_if
connect issue_slots[19].in_uop.bits.bp_debug_if, _WIRE.bp_debug_if
connect issue_slots[19].in_uop.bits.xcpt_ma_if, _WIRE.xcpt_ma_if
connect issue_slots[19].in_uop.bits.xcpt_ae_if, _WIRE.xcpt_ae_if
connect issue_slots[19].in_uop.bits.xcpt_pf_if, _WIRE.xcpt_pf_if
connect issue_slots[19].in_uop.bits.fp_typ, _WIRE.fp_typ
connect issue_slots[19].in_uop.bits.fp_rm, _WIRE.fp_rm
connect issue_slots[19].in_uop.bits.fp_val, _WIRE.fp_val
connect issue_slots[19].in_uop.bits.fcn_op, _WIRE.fcn_op
connect issue_slots[19].in_uop.bits.fcn_dw, _WIRE.fcn_dw
connect issue_slots[19].in_uop.bits.frs3_en, _WIRE.frs3_en
connect issue_slots[19].in_uop.bits.lrs2_rtype, _WIRE.lrs2_rtype
connect issue_slots[19].in_uop.bits.lrs1_rtype, _WIRE.lrs1_rtype
connect issue_slots[19].in_uop.bits.dst_rtype, _WIRE.dst_rtype
connect issue_slots[19].in_uop.bits.lrs3, _WIRE.lrs3
connect issue_slots[19].in_uop.bits.lrs2, _WIRE.lrs2
connect issue_slots[19].in_uop.bits.lrs1, _WIRE.lrs1
connect issue_slots[19].in_uop.bits.ldst, _WIRE.ldst
connect issue_slots[19].in_uop.bits.ldst_is_rs1, _WIRE.ldst_is_rs1
connect issue_slots[19].in_uop.bits.csr_cmd, _WIRE.csr_cmd
connect issue_slots[19].in_uop.bits.flush_on_commit, _WIRE.flush_on_commit
connect issue_slots[19].in_uop.bits.is_unique, _WIRE.is_unique
connect issue_slots[19].in_uop.bits.uses_stq, _WIRE.uses_stq
connect issue_slots[19].in_uop.bits.uses_ldq, _WIRE.uses_ldq
connect issue_slots[19].in_uop.bits.mem_signed, _WIRE.mem_signed
connect issue_slots[19].in_uop.bits.mem_size, _WIRE.mem_size
connect issue_slots[19].in_uop.bits.mem_cmd, _WIRE.mem_cmd
connect issue_slots[19].in_uop.bits.exc_cause, _WIRE.exc_cause
connect issue_slots[19].in_uop.bits.exception, _WIRE.exception
connect issue_slots[19].in_uop.bits.stale_pdst, _WIRE.stale_pdst
connect issue_slots[19].in_uop.bits.ppred_busy, _WIRE.ppred_busy
connect issue_slots[19].in_uop.bits.prs3_busy, _WIRE.prs3_busy
connect issue_slots[19].in_uop.bits.prs2_busy, _WIRE.prs2_busy
connect issue_slots[19].in_uop.bits.prs1_busy, _WIRE.prs1_busy
connect issue_slots[19].in_uop.bits.ppred, _WIRE.ppred
connect issue_slots[19].in_uop.bits.prs3, _WIRE.prs3
connect issue_slots[19].in_uop.bits.prs2, _WIRE.prs2
connect issue_slots[19].in_uop.bits.prs1, _WIRE.prs1
connect issue_slots[19].in_uop.bits.pdst, _WIRE.pdst
connect issue_slots[19].in_uop.bits.rxq_idx, _WIRE.rxq_idx
connect issue_slots[19].in_uop.bits.stq_idx, _WIRE.stq_idx
connect issue_slots[19].in_uop.bits.ldq_idx, _WIRE.ldq_idx
connect issue_slots[19].in_uop.bits.rob_idx, _WIRE.rob_idx
connect issue_slots[19].in_uop.bits.fp_ctrl.vec, _WIRE.fp_ctrl.vec
connect issue_slots[19].in_uop.bits.fp_ctrl.wflags, _WIRE.fp_ctrl.wflags
connect issue_slots[19].in_uop.bits.fp_ctrl.sqrt, _WIRE.fp_ctrl.sqrt
connect issue_slots[19].in_uop.bits.fp_ctrl.div, _WIRE.fp_ctrl.div
connect issue_slots[19].in_uop.bits.fp_ctrl.fma, _WIRE.fp_ctrl.fma
connect issue_slots[19].in_uop.bits.fp_ctrl.fastpipe, _WIRE.fp_ctrl.fastpipe
connect issue_slots[19].in_uop.bits.fp_ctrl.toint, _WIRE.fp_ctrl.toint
connect issue_slots[19].in_uop.bits.fp_ctrl.fromint, _WIRE.fp_ctrl.fromint
connect issue_slots[19].in_uop.bits.fp_ctrl.typeTagOut, _WIRE.fp_ctrl.typeTagOut
connect issue_slots[19].in_uop.bits.fp_ctrl.typeTagIn, _WIRE.fp_ctrl.typeTagIn
connect issue_slots[19].in_uop.bits.fp_ctrl.swap23, _WIRE.fp_ctrl.swap23
connect issue_slots[19].in_uop.bits.fp_ctrl.swap12, _WIRE.fp_ctrl.swap12
connect issue_slots[19].in_uop.bits.fp_ctrl.ren3, _WIRE.fp_ctrl.ren3
connect issue_slots[19].in_uop.bits.fp_ctrl.ren2, _WIRE.fp_ctrl.ren2
connect issue_slots[19].in_uop.bits.fp_ctrl.ren1, _WIRE.fp_ctrl.ren1
connect issue_slots[19].in_uop.bits.fp_ctrl.wen, _WIRE.fp_ctrl.wen
connect issue_slots[19].in_uop.bits.fp_ctrl.ldst, _WIRE.fp_ctrl.ldst
connect issue_slots[19].in_uop.bits.op2_sel, _WIRE.op2_sel
connect issue_slots[19].in_uop.bits.op1_sel, _WIRE.op1_sel
connect issue_slots[19].in_uop.bits.imm_packed, _WIRE.imm_packed
connect issue_slots[19].in_uop.bits.pimm, _WIRE.pimm
connect issue_slots[19].in_uop.bits.imm_sel, _WIRE.imm_sel
connect issue_slots[19].in_uop.bits.imm_rename, _WIRE.imm_rename
connect issue_slots[19].in_uop.bits.taken, _WIRE.taken
connect issue_slots[19].in_uop.bits.pc_lob, _WIRE.pc_lob
connect issue_slots[19].in_uop.bits.edge_inst, _WIRE.edge_inst
connect issue_slots[19].in_uop.bits.ftq_idx, _WIRE.ftq_idx
connect issue_slots[19].in_uop.bits.is_mov, _WIRE.is_mov
connect issue_slots[19].in_uop.bits.is_rocc, _WIRE.is_rocc
connect issue_slots[19].in_uop.bits.is_sys_pc2epc, _WIRE.is_sys_pc2epc
connect issue_slots[19].in_uop.bits.is_eret, _WIRE.is_eret
connect issue_slots[19].in_uop.bits.is_amo, _WIRE.is_amo
connect issue_slots[19].in_uop.bits.is_sfence, _WIRE.is_sfence
connect issue_slots[19].in_uop.bits.is_fencei, _WIRE.is_fencei
connect issue_slots[19].in_uop.bits.is_fence, _WIRE.is_fence
connect issue_slots[19].in_uop.bits.is_sfb, _WIRE.is_sfb
connect issue_slots[19].in_uop.bits.br_type, _WIRE.br_type
connect issue_slots[19].in_uop.bits.br_tag, _WIRE.br_tag
connect issue_slots[19].in_uop.bits.br_mask, _WIRE.br_mask
connect issue_slots[19].in_uop.bits.dis_col_sel, _WIRE.dis_col_sel
connect issue_slots[19].in_uop.bits.iw_p3_bypass_hint, _WIRE.iw_p3_bypass_hint
connect issue_slots[19].in_uop.bits.iw_p2_bypass_hint, _WIRE.iw_p2_bypass_hint
connect issue_slots[19].in_uop.bits.iw_p1_bypass_hint, _WIRE.iw_p1_bypass_hint
connect issue_slots[19].in_uop.bits.iw_p2_speculative_child, _WIRE.iw_p2_speculative_child
connect issue_slots[19].in_uop.bits.iw_p1_speculative_child, _WIRE.iw_p1_speculative_child
connect issue_slots[19].in_uop.bits.iw_issued_partial_dgen, _WIRE.iw_issued_partial_dgen
connect issue_slots[19].in_uop.bits.iw_issued_partial_agen, _WIRE.iw_issued_partial_agen
connect issue_slots[19].in_uop.bits.iw_issued, _WIRE.iw_issued
connect issue_slots[19].in_uop.bits.fu_code[0], _WIRE.fu_code[0]
connect issue_slots[19].in_uop.bits.fu_code[1], _WIRE.fu_code[1]
connect issue_slots[19].in_uop.bits.fu_code[2], _WIRE.fu_code[2]
connect issue_slots[19].in_uop.bits.fu_code[3], _WIRE.fu_code[3]
connect issue_slots[19].in_uop.bits.fu_code[4], _WIRE.fu_code[4]
connect issue_slots[19].in_uop.bits.fu_code[5], _WIRE.fu_code[5]
connect issue_slots[19].in_uop.bits.fu_code[6], _WIRE.fu_code[6]
connect issue_slots[19].in_uop.bits.fu_code[7], _WIRE.fu_code[7]
connect issue_slots[19].in_uop.bits.fu_code[8], _WIRE.fu_code[8]
connect issue_slots[19].in_uop.bits.fu_code[9], _WIRE.fu_code[9]
connect issue_slots[19].in_uop.bits.iq_type[0], _WIRE.iq_type[0]
connect issue_slots[19].in_uop.bits.iq_type[1], _WIRE.iq_type[1]
connect issue_slots[19].in_uop.bits.iq_type[2], _WIRE.iq_type[2]
connect issue_slots[19].in_uop.bits.iq_type[3], _WIRE.iq_type[3]
connect issue_slots[19].in_uop.bits.debug_pc, _WIRE.debug_pc
connect issue_slots[19].in_uop.bits.is_rvc, _WIRE.is_rvc
connect issue_slots[19].in_uop.bits.debug_inst, _WIRE.debug_inst
connect issue_slots[19].in_uop.bits.inst, _WIRE.inst
node _T_201 = eq(shamts_oh[21], UInt<2>(0h2))
when _T_201 :
connect issue_slots[19].in_uop.valid, will_be_valid_21
connect issue_slots[19].in_uop.bits.debug_tsrc, _WIRE_1.debug_tsrc
connect issue_slots[19].in_uop.bits.debug_fsrc, _WIRE_1.debug_fsrc
connect issue_slots[19].in_uop.bits.bp_xcpt_if, _WIRE_1.bp_xcpt_if
connect issue_slots[19].in_uop.bits.bp_debug_if, _WIRE_1.bp_debug_if
connect issue_slots[19].in_uop.bits.xcpt_ma_if, _WIRE_1.xcpt_ma_if
connect issue_slots[19].in_uop.bits.xcpt_ae_if, _WIRE_1.xcpt_ae_if
connect issue_slots[19].in_uop.bits.xcpt_pf_if, _WIRE_1.xcpt_pf_if
connect issue_slots[19].in_uop.bits.fp_typ, _WIRE_1.fp_typ
connect issue_slots[19].in_uop.bits.fp_rm, _WIRE_1.fp_rm
connect issue_slots[19].in_uop.bits.fp_val, _WIRE_1.fp_val
connect issue_slots[19].in_uop.bits.fcn_op, _WIRE_1.fcn_op
connect issue_slots[19].in_uop.bits.fcn_dw, _WIRE_1.fcn_dw
connect issue_slots[19].in_uop.bits.frs3_en, _WIRE_1.frs3_en
connect issue_slots[19].in_uop.bits.lrs2_rtype, _WIRE_1.lrs2_rtype
connect issue_slots[19].in_uop.bits.lrs1_rtype, _WIRE_1.lrs1_rtype
connect issue_slots[19].in_uop.bits.dst_rtype, _WIRE_1.dst_rtype
connect issue_slots[19].in_uop.bits.lrs3, _WIRE_1.lrs3
connect issue_slots[19].in_uop.bits.lrs2, _WIRE_1.lrs2
connect issue_slots[19].in_uop.bits.lrs1, _WIRE_1.lrs1
connect issue_slots[19].in_uop.bits.ldst, _WIRE_1.ldst
connect issue_slots[19].in_uop.bits.ldst_is_rs1, _WIRE_1.ldst_is_rs1
connect issue_slots[19].in_uop.bits.csr_cmd, _WIRE_1.csr_cmd
connect issue_slots[19].in_uop.bits.flush_on_commit, _WIRE_1.flush_on_commit
connect issue_slots[19].in_uop.bits.is_unique, _WIRE_1.is_unique
connect issue_slots[19].in_uop.bits.uses_stq, _WIRE_1.uses_stq
connect issue_slots[19].in_uop.bits.uses_ldq, _WIRE_1.uses_ldq
connect issue_slots[19].in_uop.bits.mem_signed, _WIRE_1.mem_signed
connect issue_slots[19].in_uop.bits.mem_size, _WIRE_1.mem_size
connect issue_slots[19].in_uop.bits.mem_cmd, _WIRE_1.mem_cmd
connect issue_slots[19].in_uop.bits.exc_cause, _WIRE_1.exc_cause
connect issue_slots[19].in_uop.bits.exception, _WIRE_1.exception
connect issue_slots[19].in_uop.bits.stale_pdst, _WIRE_1.stale_pdst
connect issue_slots[19].in_uop.bits.ppred_busy, _WIRE_1.ppred_busy
connect issue_slots[19].in_uop.bits.prs3_busy, _WIRE_1.prs3_busy
connect issue_slots[19].in_uop.bits.prs2_busy, _WIRE_1.prs2_busy
connect issue_slots[19].in_uop.bits.prs1_busy, _WIRE_1.prs1_busy
connect issue_slots[19].in_uop.bits.ppred, _WIRE_1.ppred
connect issue_slots[19].in_uop.bits.prs3, _WIRE_1.prs3
connect issue_slots[19].in_uop.bits.prs2, _WIRE_1.prs2
connect issue_slots[19].in_uop.bits.prs1, _WIRE_1.prs1
connect issue_slots[19].in_uop.bits.pdst, _WIRE_1.pdst
connect issue_slots[19].in_uop.bits.rxq_idx, _WIRE_1.rxq_idx
connect issue_slots[19].in_uop.bits.stq_idx, _WIRE_1.stq_idx
connect issue_slots[19].in_uop.bits.ldq_idx, _WIRE_1.ldq_idx
connect issue_slots[19].in_uop.bits.rob_idx, _WIRE_1.rob_idx
connect issue_slots[19].in_uop.bits.fp_ctrl.vec, _WIRE_1.fp_ctrl.vec
connect issue_slots[19].in_uop.bits.fp_ctrl.wflags, _WIRE_1.fp_ctrl.wflags
connect issue_slots[19].in_uop.bits.fp_ctrl.sqrt, _WIRE_1.fp_ctrl.sqrt
connect issue_slots[19].in_uop.bits.fp_ctrl.div, _WIRE_1.fp_ctrl.div
connect issue_slots[19].in_uop.bits.fp_ctrl.fma, _WIRE_1.fp_ctrl.fma
connect issue_slots[19].in_uop.bits.fp_ctrl.fastpipe, _WIRE_1.fp_ctrl.fastpipe
connect issue_slots[19].in_uop.bits.fp_ctrl.toint, _WIRE_1.fp_ctrl.toint
connect issue_slots[19].in_uop.bits.fp_ctrl.fromint, _WIRE_1.fp_ctrl.fromint
connect issue_slots[19].in_uop.bits.fp_ctrl.typeTagOut, _WIRE_1.fp_ctrl.typeTagOut
connect issue_slots[19].in_uop.bits.fp_ctrl.typeTagIn, _WIRE_1.fp_ctrl.typeTagIn
connect issue_slots[19].in_uop.bits.fp_ctrl.swap23, _WIRE_1.fp_ctrl.swap23
connect issue_slots[19].in_uop.bits.fp_ctrl.swap12, _WIRE_1.fp_ctrl.swap12
connect issue_slots[19].in_uop.bits.fp_ctrl.ren3, _WIRE_1.fp_ctrl.ren3
connect issue_slots[19].in_uop.bits.fp_ctrl.ren2, _WIRE_1.fp_ctrl.ren2
connect issue_slots[19].in_uop.bits.fp_ctrl.ren1, _WIRE_1.fp_ctrl.ren1
connect issue_slots[19].in_uop.bits.fp_ctrl.wen, _WIRE_1.fp_ctrl.wen
connect issue_slots[19].in_uop.bits.fp_ctrl.ldst, _WIRE_1.fp_ctrl.ldst
connect issue_slots[19].in_uop.bits.op2_sel, _WIRE_1.op2_sel
connect issue_slots[19].in_uop.bits.op1_sel, _WIRE_1.op1_sel
connect issue_slots[19].in_uop.bits.imm_packed, _WIRE_1.imm_packed
connect issue_slots[19].in_uop.bits.pimm, _WIRE_1.pimm
connect issue_slots[19].in_uop.bits.imm_sel, _WIRE_1.imm_sel
connect issue_slots[19].in_uop.bits.imm_rename, _WIRE_1.imm_rename
connect issue_slots[19].in_uop.bits.taken, _WIRE_1.taken
connect issue_slots[19].in_uop.bits.pc_lob, _WIRE_1.pc_lob
connect issue_slots[19].in_uop.bits.edge_inst, _WIRE_1.edge_inst
connect issue_slots[19].in_uop.bits.ftq_idx, _WIRE_1.ftq_idx
connect issue_slots[19].in_uop.bits.is_mov, _WIRE_1.is_mov
connect issue_slots[19].in_uop.bits.is_rocc, _WIRE_1.is_rocc
connect issue_slots[19].in_uop.bits.is_sys_pc2epc, _WIRE_1.is_sys_pc2epc
connect issue_slots[19].in_uop.bits.is_eret, _WIRE_1.is_eret
connect issue_slots[19].in_uop.bits.is_amo, _WIRE_1.is_amo
connect issue_slots[19].in_uop.bits.is_sfence, _WIRE_1.is_sfence
connect issue_slots[19].in_uop.bits.is_fencei, _WIRE_1.is_fencei
connect issue_slots[19].in_uop.bits.is_fence, _WIRE_1.is_fence
connect issue_slots[19].in_uop.bits.is_sfb, _WIRE_1.is_sfb
connect issue_slots[19].in_uop.bits.br_type, _WIRE_1.br_type
connect issue_slots[19].in_uop.bits.br_tag, _WIRE_1.br_tag
connect issue_slots[19].in_uop.bits.br_mask, _WIRE_1.br_mask
connect issue_slots[19].in_uop.bits.dis_col_sel, _WIRE_1.dis_col_sel
connect issue_slots[19].in_uop.bits.iw_p3_bypass_hint, _WIRE_1.iw_p3_bypass_hint
connect issue_slots[19].in_uop.bits.iw_p2_bypass_hint, _WIRE_1.iw_p2_bypass_hint
connect issue_slots[19].in_uop.bits.iw_p1_bypass_hint, _WIRE_1.iw_p1_bypass_hint
connect issue_slots[19].in_uop.bits.iw_p2_speculative_child, _WIRE_1.iw_p2_speculative_child
connect issue_slots[19].in_uop.bits.iw_p1_speculative_child, _WIRE_1.iw_p1_speculative_child
connect issue_slots[19].in_uop.bits.iw_issued_partial_dgen, _WIRE_1.iw_issued_partial_dgen
connect issue_slots[19].in_uop.bits.iw_issued_partial_agen, _WIRE_1.iw_issued_partial_agen
connect issue_slots[19].in_uop.bits.iw_issued, _WIRE_1.iw_issued
connect issue_slots[19].in_uop.bits.fu_code[0], _WIRE_1.fu_code[0]
connect issue_slots[19].in_uop.bits.fu_code[1], _WIRE_1.fu_code[1]
connect issue_slots[19].in_uop.bits.fu_code[2], _WIRE_1.fu_code[2]
connect issue_slots[19].in_uop.bits.fu_code[3], _WIRE_1.fu_code[3]
connect issue_slots[19].in_uop.bits.fu_code[4], _WIRE_1.fu_code[4]
connect issue_slots[19].in_uop.bits.fu_code[5], _WIRE_1.fu_code[5]
connect issue_slots[19].in_uop.bits.fu_code[6], _WIRE_1.fu_code[6]
connect issue_slots[19].in_uop.bits.fu_code[7], _WIRE_1.fu_code[7]
connect issue_slots[19].in_uop.bits.fu_code[8], _WIRE_1.fu_code[8]
connect issue_slots[19].in_uop.bits.fu_code[9], _WIRE_1.fu_code[9]
connect issue_slots[19].in_uop.bits.iq_type[0], _WIRE_1.iq_type[0]
connect issue_slots[19].in_uop.bits.iq_type[1], _WIRE_1.iq_type[1]
connect issue_slots[19].in_uop.bits.iq_type[2], _WIRE_1.iq_type[2]
connect issue_slots[19].in_uop.bits.iq_type[3], _WIRE_1.iq_type[3]
connect issue_slots[19].in_uop.bits.debug_pc, _WIRE_1.debug_pc
connect issue_slots[19].in_uop.bits.is_rvc, _WIRE_1.is_rvc
connect issue_slots[19].in_uop.bits.debug_inst, _WIRE_1.debug_inst
connect issue_slots[19].in_uop.bits.inst, _WIRE_1.inst
node _issue_slots_19_clear_T = neq(shamts_oh[19], UInt<1>(0h0))
connect issue_slots[19].clear, _issue_slots_19_clear_T
reg is_available : UInt<1>[20], clock
node _T_202 = eq(issue_slots[0].will_be_valid, UInt<1>(0h0))
node _T_203 = or(_T_202, issue_slots[0].clear)
node _T_204 = eq(issue_slots[0].in_uop.valid, UInt<1>(0h0))
node _T_205 = and(_T_203, _T_204)
node _T_206 = eq(issue_slots[1].will_be_valid, UInt<1>(0h0))
node _T_207 = or(_T_206, issue_slots[1].clear)
node _T_208 = eq(issue_slots[1].in_uop.valid, UInt<1>(0h0))
node _T_209 = and(_T_207, _T_208)
node _T_210 = eq(issue_slots[2].will_be_valid, UInt<1>(0h0))
node _T_211 = or(_T_210, issue_slots[2].clear)
node _T_212 = eq(issue_slots[2].in_uop.valid, UInt<1>(0h0))
node _T_213 = and(_T_211, _T_212)
node _T_214 = eq(issue_slots[3].will_be_valid, UInt<1>(0h0))
node _T_215 = or(_T_214, issue_slots[3].clear)
node _T_216 = eq(issue_slots[3].in_uop.valid, UInt<1>(0h0))
node _T_217 = and(_T_215, _T_216)
node _T_218 = eq(issue_slots[4].will_be_valid, UInt<1>(0h0))
node _T_219 = or(_T_218, issue_slots[4].clear)
node _T_220 = eq(issue_slots[4].in_uop.valid, UInt<1>(0h0))
node _T_221 = and(_T_219, _T_220)
node _T_222 = eq(issue_slots[5].will_be_valid, UInt<1>(0h0))
node _T_223 = or(_T_222, issue_slots[5].clear)
node _T_224 = eq(issue_slots[5].in_uop.valid, UInt<1>(0h0))
node _T_225 = and(_T_223, _T_224)
node _T_226 = eq(issue_slots[6].will_be_valid, UInt<1>(0h0))
node _T_227 = or(_T_226, issue_slots[6].clear)
node _T_228 = eq(issue_slots[6].in_uop.valid, UInt<1>(0h0))
node _T_229 = and(_T_227, _T_228)
node _T_230 = eq(issue_slots[7].will_be_valid, UInt<1>(0h0))
node _T_231 = or(_T_230, issue_slots[7].clear)
node _T_232 = eq(issue_slots[7].in_uop.valid, UInt<1>(0h0))
node _T_233 = and(_T_231, _T_232)
node _T_234 = eq(issue_slots[8].will_be_valid, UInt<1>(0h0))
node _T_235 = or(_T_234, issue_slots[8].clear)
node _T_236 = eq(issue_slots[8].in_uop.valid, UInt<1>(0h0))
node _T_237 = and(_T_235, _T_236)
node _T_238 = eq(issue_slots[9].will_be_valid, UInt<1>(0h0))
node _T_239 = or(_T_238, issue_slots[9].clear)
node _T_240 = eq(issue_slots[9].in_uop.valid, UInt<1>(0h0))
node _T_241 = and(_T_239, _T_240)
node _T_242 = eq(issue_slots[10].will_be_valid, UInt<1>(0h0))
node _T_243 = or(_T_242, issue_slots[10].clear)
node _T_244 = eq(issue_slots[10].in_uop.valid, UInt<1>(0h0))
node _T_245 = and(_T_243, _T_244)
node _T_246 = eq(issue_slots[11].will_be_valid, UInt<1>(0h0))
node _T_247 = or(_T_246, issue_slots[11].clear)
node _T_248 = eq(issue_slots[11].in_uop.valid, UInt<1>(0h0))
node _T_249 = and(_T_247, _T_248)
node _T_250 = eq(issue_slots[12].will_be_valid, UInt<1>(0h0))
node _T_251 = or(_T_250, issue_slots[12].clear)
node _T_252 = eq(issue_slots[12].in_uop.valid, UInt<1>(0h0))
node _T_253 = and(_T_251, _T_252)
node _T_254 = eq(issue_slots[13].will_be_valid, UInt<1>(0h0))
node _T_255 = or(_T_254, issue_slots[13].clear)
node _T_256 = eq(issue_slots[13].in_uop.valid, UInt<1>(0h0))
node _T_257 = and(_T_255, _T_256)
node _T_258 = eq(issue_slots[14].will_be_valid, UInt<1>(0h0))
node _T_259 = or(_T_258, issue_slots[14].clear)
node _T_260 = eq(issue_slots[14].in_uop.valid, UInt<1>(0h0))
node _T_261 = and(_T_259, _T_260)
node _T_262 = eq(issue_slots[15].will_be_valid, UInt<1>(0h0))
node _T_263 = or(_T_262, issue_slots[15].clear)
node _T_264 = eq(issue_slots[15].in_uop.valid, UInt<1>(0h0))
node _T_265 = and(_T_263, _T_264)
node _T_266 = eq(issue_slots[16].will_be_valid, UInt<1>(0h0))
node _T_267 = or(_T_266, issue_slots[16].clear)
node _T_268 = eq(issue_slots[16].in_uop.valid, UInt<1>(0h0))
node _T_269 = and(_T_267, _T_268)
node _T_270 = eq(issue_slots[17].will_be_valid, UInt<1>(0h0))
node _T_271 = or(_T_270, issue_slots[17].clear)
node _T_272 = eq(issue_slots[17].in_uop.valid, UInt<1>(0h0))
node _T_273 = and(_T_271, _T_272)
node _T_274 = eq(issue_slots[18].will_be_valid, UInt<1>(0h0))
node _T_275 = or(_T_274, issue_slots[18].clear)
node _T_276 = eq(issue_slots[18].in_uop.valid, UInt<1>(0h0))
node _T_277 = and(_T_275, _T_276)
node _T_278 = eq(issue_slots[19].will_be_valid, UInt<1>(0h0))
node _T_279 = or(_T_278, issue_slots[19].clear)
node _T_280 = eq(issue_slots[19].in_uop.valid, UInt<1>(0h0))
node _T_281 = and(_T_279, _T_280)
wire _WIRE_12 : UInt<1>[20]
connect _WIRE_12[0], _T_205
connect _WIRE_12[1], _T_209
connect _WIRE_12[2], _T_213
connect _WIRE_12[3], _T_217
connect _WIRE_12[4], _T_221
connect _WIRE_12[5], _T_225
connect _WIRE_12[6], _T_229
connect _WIRE_12[7], _T_233
connect _WIRE_12[8], _T_237
connect _WIRE_12[9], _T_241
connect _WIRE_12[10], _T_245
connect _WIRE_12[11], _T_249
connect _WIRE_12[12], _T_253
connect _WIRE_12[13], _T_257
connect _WIRE_12[14], _T_261
connect _WIRE_12[15], _T_265
connect _WIRE_12[16], _T_269
connect _WIRE_12[17], _T_273
connect _WIRE_12[18], _T_277
connect _WIRE_12[19], _T_281
connect is_available, _WIRE_12
node _io_dis_uops_0_ready_T = add(is_available[0], is_available[1])
node _io_dis_uops_0_ready_T_1 = bits(_io_dis_uops_0_ready_T, 1, 0)
node _io_dis_uops_0_ready_T_2 = add(is_available[3], is_available[4])
node _io_dis_uops_0_ready_T_3 = bits(_io_dis_uops_0_ready_T_2, 1, 0)
node _io_dis_uops_0_ready_T_4 = add(is_available[2], _io_dis_uops_0_ready_T_3)
node _io_dis_uops_0_ready_T_5 = bits(_io_dis_uops_0_ready_T_4, 1, 0)
node _io_dis_uops_0_ready_T_6 = add(_io_dis_uops_0_ready_T_1, _io_dis_uops_0_ready_T_5)
node _io_dis_uops_0_ready_T_7 = bits(_io_dis_uops_0_ready_T_6, 2, 0)
node _io_dis_uops_0_ready_T_8 = add(is_available[5], is_available[6])
node _io_dis_uops_0_ready_T_9 = bits(_io_dis_uops_0_ready_T_8, 1, 0)
node _io_dis_uops_0_ready_T_10 = add(is_available[8], is_available[9])
node _io_dis_uops_0_ready_T_11 = bits(_io_dis_uops_0_ready_T_10, 1, 0)
node _io_dis_uops_0_ready_T_12 = add(is_available[7], _io_dis_uops_0_ready_T_11)
node _io_dis_uops_0_ready_T_13 = bits(_io_dis_uops_0_ready_T_12, 1, 0)
node _io_dis_uops_0_ready_T_14 = add(_io_dis_uops_0_ready_T_9, _io_dis_uops_0_ready_T_13)
node _io_dis_uops_0_ready_T_15 = bits(_io_dis_uops_0_ready_T_14, 2, 0)
node _io_dis_uops_0_ready_T_16 = add(_io_dis_uops_0_ready_T_7, _io_dis_uops_0_ready_T_15)
node _io_dis_uops_0_ready_T_17 = bits(_io_dis_uops_0_ready_T_16, 3, 0)
node _io_dis_uops_0_ready_T_18 = add(is_available[10], is_available[11])
node _io_dis_uops_0_ready_T_19 = bits(_io_dis_uops_0_ready_T_18, 1, 0)
node _io_dis_uops_0_ready_T_20 = add(is_available[13], is_available[14])
node _io_dis_uops_0_ready_T_21 = bits(_io_dis_uops_0_ready_T_20, 1, 0)
node _io_dis_uops_0_ready_T_22 = add(is_available[12], _io_dis_uops_0_ready_T_21)
node _io_dis_uops_0_ready_T_23 = bits(_io_dis_uops_0_ready_T_22, 1, 0)
node _io_dis_uops_0_ready_T_24 = add(_io_dis_uops_0_ready_T_19, _io_dis_uops_0_ready_T_23)
node _io_dis_uops_0_ready_T_25 = bits(_io_dis_uops_0_ready_T_24, 2, 0)
node _io_dis_uops_0_ready_T_26 = add(is_available[15], is_available[16])
node _io_dis_uops_0_ready_T_27 = bits(_io_dis_uops_0_ready_T_26, 1, 0)
node _io_dis_uops_0_ready_T_28 = add(is_available[18], is_available[19])
node _io_dis_uops_0_ready_T_29 = bits(_io_dis_uops_0_ready_T_28, 1, 0)
node _io_dis_uops_0_ready_T_30 = add(is_available[17], _io_dis_uops_0_ready_T_29)
node _io_dis_uops_0_ready_T_31 = bits(_io_dis_uops_0_ready_T_30, 1, 0)
node _io_dis_uops_0_ready_T_32 = add(_io_dis_uops_0_ready_T_27, _io_dis_uops_0_ready_T_31)
node _io_dis_uops_0_ready_T_33 = bits(_io_dis_uops_0_ready_T_32, 2, 0)
node _io_dis_uops_0_ready_T_34 = add(_io_dis_uops_0_ready_T_25, _io_dis_uops_0_ready_T_33)
node _io_dis_uops_0_ready_T_35 = bits(_io_dis_uops_0_ready_T_34, 3, 0)
node _io_dis_uops_0_ready_T_36 = add(_io_dis_uops_0_ready_T_17, _io_dis_uops_0_ready_T_35)
node _io_dis_uops_0_ready_T_37 = bits(_io_dis_uops_0_ready_T_36, 4, 0)
node _io_dis_uops_0_ready_T_38 = and(io.dis_uops[0].ready, io.dis_uops[0].valid)
node _io_dis_uops_0_ready_T_39 = and(io.dis_uops[1].ready, io.dis_uops[1].valid)
node _io_dis_uops_0_ready_T_40 = add(_io_dis_uops_0_ready_T_38, _io_dis_uops_0_ready_T_39)
node _io_dis_uops_0_ready_T_41 = bits(_io_dis_uops_0_ready_T_40, 1, 0)
node _io_dis_uops_0_ready_T_42 = add(UInt<5>(0h0), _io_dis_uops_0_ready_T_41)
node _io_dis_uops_0_ready_T_43 = tail(_io_dis_uops_0_ready_T_42, 1)
node _io_dis_uops_0_ready_T_44 = gt(_io_dis_uops_0_ready_T_37, _io_dis_uops_0_ready_T_43)
reg io_dis_uops_0_ready_REG : UInt<1>, clock
connect io_dis_uops_0_ready_REG, _io_dis_uops_0_ready_T_44
connect io.dis_uops[0].ready, io_dis_uops_0_ready_REG
node _T_282 = eq(io.dis_uops[0].ready, UInt<1>(0h0))
node _T_283 = shr(shamts_oh[20], 0)
node _T_284 = neq(_T_283, UInt<1>(0h0))
node _T_285 = or(_T_282, _T_284)
node _T_286 = asUInt(reset)
node _T_287 = eq(_T_286, UInt<1>(0h0))
when _T_287 :
node _T_288 = eq(_T_285, UInt<1>(0h0))
when _T_288 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-unit-age-ordered.scala:214 assert (!io.dis_uops(w).ready || (shamts_oh(w+numIssueSlots) >> w) =/= 0.U)\n") : printf_1
assert(clock, _T_285, UInt<1>(0h1), "") : assert_1
node _io_dis_uops_1_ready_T = add(is_available[0], is_available[1])
node _io_dis_uops_1_ready_T_1 = bits(_io_dis_uops_1_ready_T, 1, 0)
node _io_dis_uops_1_ready_T_2 = add(is_available[3], is_available[4])
node _io_dis_uops_1_ready_T_3 = bits(_io_dis_uops_1_ready_T_2, 1, 0)
node _io_dis_uops_1_ready_T_4 = add(is_available[2], _io_dis_uops_1_ready_T_3)
node _io_dis_uops_1_ready_T_5 = bits(_io_dis_uops_1_ready_T_4, 1, 0)
node _io_dis_uops_1_ready_T_6 = add(_io_dis_uops_1_ready_T_1, _io_dis_uops_1_ready_T_5)
node _io_dis_uops_1_ready_T_7 = bits(_io_dis_uops_1_ready_T_6, 2, 0)
node _io_dis_uops_1_ready_T_8 = add(is_available[5], is_available[6])
node _io_dis_uops_1_ready_T_9 = bits(_io_dis_uops_1_ready_T_8, 1, 0)
node _io_dis_uops_1_ready_T_10 = add(is_available[8], is_available[9])
node _io_dis_uops_1_ready_T_11 = bits(_io_dis_uops_1_ready_T_10, 1, 0)
node _io_dis_uops_1_ready_T_12 = add(is_available[7], _io_dis_uops_1_ready_T_11)
node _io_dis_uops_1_ready_T_13 = bits(_io_dis_uops_1_ready_T_12, 1, 0)
node _io_dis_uops_1_ready_T_14 = add(_io_dis_uops_1_ready_T_9, _io_dis_uops_1_ready_T_13)
node _io_dis_uops_1_ready_T_15 = bits(_io_dis_uops_1_ready_T_14, 2, 0)
node _io_dis_uops_1_ready_T_16 = add(_io_dis_uops_1_ready_T_7, _io_dis_uops_1_ready_T_15)
node _io_dis_uops_1_ready_T_17 = bits(_io_dis_uops_1_ready_T_16, 3, 0)
node _io_dis_uops_1_ready_T_18 = add(is_available[10], is_available[11])
node _io_dis_uops_1_ready_T_19 = bits(_io_dis_uops_1_ready_T_18, 1, 0)
node _io_dis_uops_1_ready_T_20 = add(is_available[13], is_available[14])
node _io_dis_uops_1_ready_T_21 = bits(_io_dis_uops_1_ready_T_20, 1, 0)
node _io_dis_uops_1_ready_T_22 = add(is_available[12], _io_dis_uops_1_ready_T_21)
node _io_dis_uops_1_ready_T_23 = bits(_io_dis_uops_1_ready_T_22, 1, 0)
node _io_dis_uops_1_ready_T_24 = add(_io_dis_uops_1_ready_T_19, _io_dis_uops_1_ready_T_23)
node _io_dis_uops_1_ready_T_25 = bits(_io_dis_uops_1_ready_T_24, 2, 0)
node _io_dis_uops_1_ready_T_26 = add(is_available[15], is_available[16])
node _io_dis_uops_1_ready_T_27 = bits(_io_dis_uops_1_ready_T_26, 1, 0)
node _io_dis_uops_1_ready_T_28 = add(is_available[18], is_available[19])
node _io_dis_uops_1_ready_T_29 = bits(_io_dis_uops_1_ready_T_28, 1, 0)
node _io_dis_uops_1_ready_T_30 = add(is_available[17], _io_dis_uops_1_ready_T_29)
node _io_dis_uops_1_ready_T_31 = bits(_io_dis_uops_1_ready_T_30, 1, 0)
node _io_dis_uops_1_ready_T_32 = add(_io_dis_uops_1_ready_T_27, _io_dis_uops_1_ready_T_31)
node _io_dis_uops_1_ready_T_33 = bits(_io_dis_uops_1_ready_T_32, 2, 0)
node _io_dis_uops_1_ready_T_34 = add(_io_dis_uops_1_ready_T_25, _io_dis_uops_1_ready_T_33)
node _io_dis_uops_1_ready_T_35 = bits(_io_dis_uops_1_ready_T_34, 3, 0)
node _io_dis_uops_1_ready_T_36 = add(_io_dis_uops_1_ready_T_17, _io_dis_uops_1_ready_T_35)
node _io_dis_uops_1_ready_T_37 = bits(_io_dis_uops_1_ready_T_36, 4, 0)
node _io_dis_uops_1_ready_T_38 = and(io.dis_uops[0].ready, io.dis_uops[0].valid)
node _io_dis_uops_1_ready_T_39 = and(io.dis_uops[1].ready, io.dis_uops[1].valid)
node _io_dis_uops_1_ready_T_40 = add(_io_dis_uops_1_ready_T_38, _io_dis_uops_1_ready_T_39)
node _io_dis_uops_1_ready_T_41 = bits(_io_dis_uops_1_ready_T_40, 1, 0)
node _io_dis_uops_1_ready_T_42 = add(UInt<5>(0h1), _io_dis_uops_1_ready_T_41)
node _io_dis_uops_1_ready_T_43 = tail(_io_dis_uops_1_ready_T_42, 1)
node _io_dis_uops_1_ready_T_44 = gt(_io_dis_uops_1_ready_T_37, _io_dis_uops_1_ready_T_43)
reg io_dis_uops_1_ready_REG : UInt<1>, clock
connect io_dis_uops_1_ready_REG, _io_dis_uops_1_ready_T_44
connect io.dis_uops[1].ready, io_dis_uops_1_ready_REG
node _T_289 = eq(io.dis_uops[1].ready, UInt<1>(0h0))
node _T_290 = shr(shamts_oh[21], 1)
node _T_291 = neq(_T_290, UInt<1>(0h0))
node _T_292 = or(_T_289, _T_291)
node _T_293 = asUInt(reset)
node _T_294 = eq(_T_293, UInt<1>(0h0))
when _T_294 :
node _T_295 = eq(_T_292, UInt<1>(0h0))
when _T_295 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-unit-age-ordered.scala:214 assert (!io.dis_uops(w).ready || (shamts_oh(w+numIssueSlots) >> w) =/= 0.U)\n") : printf_2
assert(clock, _T_292, UInt<1>(0h1), "") : assert_2
wire iss_uops : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}[2]
connect iss_uops[0].valid, UInt<1>(0h0)
invalidate iss_uops[0].bits.debug_tsrc
invalidate iss_uops[0].bits.debug_fsrc
invalidate iss_uops[0].bits.bp_xcpt_if
invalidate iss_uops[0].bits.bp_debug_if
invalidate iss_uops[0].bits.xcpt_ma_if
invalidate iss_uops[0].bits.xcpt_ae_if
invalidate iss_uops[0].bits.xcpt_pf_if
invalidate iss_uops[0].bits.fp_typ
invalidate iss_uops[0].bits.fp_rm
invalidate iss_uops[0].bits.fp_val
invalidate iss_uops[0].bits.fcn_op
invalidate iss_uops[0].bits.fcn_dw
invalidate iss_uops[0].bits.frs3_en
invalidate iss_uops[0].bits.lrs2_rtype
invalidate iss_uops[0].bits.lrs1_rtype
invalidate iss_uops[0].bits.dst_rtype
invalidate iss_uops[0].bits.lrs3
invalidate iss_uops[0].bits.lrs2
invalidate iss_uops[0].bits.lrs1
invalidate iss_uops[0].bits.ldst
invalidate iss_uops[0].bits.ldst_is_rs1
invalidate iss_uops[0].bits.csr_cmd
invalidate iss_uops[0].bits.flush_on_commit
invalidate iss_uops[0].bits.is_unique
invalidate iss_uops[0].bits.uses_stq
invalidate iss_uops[0].bits.uses_ldq
invalidate iss_uops[0].bits.mem_signed
invalidate iss_uops[0].bits.mem_size
invalidate iss_uops[0].bits.mem_cmd
invalidate iss_uops[0].bits.exc_cause
invalidate iss_uops[0].bits.exception
invalidate iss_uops[0].bits.stale_pdst
invalidate iss_uops[0].bits.ppred_busy
invalidate iss_uops[0].bits.prs3_busy
invalidate iss_uops[0].bits.prs2_busy
invalidate iss_uops[0].bits.prs1_busy
invalidate iss_uops[0].bits.ppred
invalidate iss_uops[0].bits.prs3
invalidate iss_uops[0].bits.prs2
invalidate iss_uops[0].bits.prs1
invalidate iss_uops[0].bits.pdst
invalidate iss_uops[0].bits.rxq_idx
invalidate iss_uops[0].bits.stq_idx
invalidate iss_uops[0].bits.ldq_idx
invalidate iss_uops[0].bits.rob_idx
invalidate iss_uops[0].bits.fp_ctrl.vec
invalidate iss_uops[0].bits.fp_ctrl.wflags
invalidate iss_uops[0].bits.fp_ctrl.sqrt
invalidate iss_uops[0].bits.fp_ctrl.div
invalidate iss_uops[0].bits.fp_ctrl.fma
invalidate iss_uops[0].bits.fp_ctrl.fastpipe
invalidate iss_uops[0].bits.fp_ctrl.toint
invalidate iss_uops[0].bits.fp_ctrl.fromint
invalidate iss_uops[0].bits.fp_ctrl.typeTagOut
invalidate iss_uops[0].bits.fp_ctrl.typeTagIn
invalidate iss_uops[0].bits.fp_ctrl.swap23
invalidate iss_uops[0].bits.fp_ctrl.swap12
invalidate iss_uops[0].bits.fp_ctrl.ren3
invalidate iss_uops[0].bits.fp_ctrl.ren2
invalidate iss_uops[0].bits.fp_ctrl.ren1
invalidate iss_uops[0].bits.fp_ctrl.wen
invalidate iss_uops[0].bits.fp_ctrl.ldst
invalidate iss_uops[0].bits.op2_sel
invalidate iss_uops[0].bits.op1_sel
invalidate iss_uops[0].bits.imm_packed
invalidate iss_uops[0].bits.pimm
invalidate iss_uops[0].bits.imm_sel
invalidate iss_uops[0].bits.imm_rename
invalidate iss_uops[0].bits.taken
invalidate iss_uops[0].bits.pc_lob
invalidate iss_uops[0].bits.edge_inst
invalidate iss_uops[0].bits.ftq_idx
invalidate iss_uops[0].bits.is_mov
invalidate iss_uops[0].bits.is_rocc
invalidate iss_uops[0].bits.is_sys_pc2epc
invalidate iss_uops[0].bits.is_eret
invalidate iss_uops[0].bits.is_amo
invalidate iss_uops[0].bits.is_sfence
invalidate iss_uops[0].bits.is_fencei
invalidate iss_uops[0].bits.is_fence
invalidate iss_uops[0].bits.is_sfb
invalidate iss_uops[0].bits.br_type
invalidate iss_uops[0].bits.br_tag
invalidate iss_uops[0].bits.br_mask
invalidate iss_uops[0].bits.dis_col_sel
invalidate iss_uops[0].bits.iw_p3_bypass_hint
invalidate iss_uops[0].bits.iw_p2_bypass_hint
invalidate iss_uops[0].bits.iw_p1_bypass_hint
invalidate iss_uops[0].bits.iw_p2_speculative_child
invalidate iss_uops[0].bits.iw_p1_speculative_child
invalidate iss_uops[0].bits.iw_issued_partial_dgen
invalidate iss_uops[0].bits.iw_issued_partial_agen
invalidate iss_uops[0].bits.iw_issued
invalidate iss_uops[0].bits.fu_code[0]
invalidate iss_uops[0].bits.fu_code[1]
invalidate iss_uops[0].bits.fu_code[2]
invalidate iss_uops[0].bits.fu_code[3]
invalidate iss_uops[0].bits.fu_code[4]
invalidate iss_uops[0].bits.fu_code[5]
invalidate iss_uops[0].bits.fu_code[6]
invalidate iss_uops[0].bits.fu_code[7]
invalidate iss_uops[0].bits.fu_code[8]
invalidate iss_uops[0].bits.fu_code[9]
invalidate iss_uops[0].bits.iq_type[0]
invalidate iss_uops[0].bits.iq_type[1]
invalidate iss_uops[0].bits.iq_type[2]
invalidate iss_uops[0].bits.iq_type[3]
invalidate iss_uops[0].bits.debug_pc
invalidate iss_uops[0].bits.is_rvc
invalidate iss_uops[0].bits.debug_inst
invalidate iss_uops[0].bits.inst
connect iss_uops[1].valid, UInt<1>(0h0)
invalidate iss_uops[1].bits.debug_tsrc
invalidate iss_uops[1].bits.debug_fsrc
invalidate iss_uops[1].bits.bp_xcpt_if
invalidate iss_uops[1].bits.bp_debug_if
invalidate iss_uops[1].bits.xcpt_ma_if
invalidate iss_uops[1].bits.xcpt_ae_if
invalidate iss_uops[1].bits.xcpt_pf_if
invalidate iss_uops[1].bits.fp_typ
invalidate iss_uops[1].bits.fp_rm
invalidate iss_uops[1].bits.fp_val
invalidate iss_uops[1].bits.fcn_op
invalidate iss_uops[1].bits.fcn_dw
invalidate iss_uops[1].bits.frs3_en
invalidate iss_uops[1].bits.lrs2_rtype
invalidate iss_uops[1].bits.lrs1_rtype
invalidate iss_uops[1].bits.dst_rtype
invalidate iss_uops[1].bits.lrs3
invalidate iss_uops[1].bits.lrs2
invalidate iss_uops[1].bits.lrs1
invalidate iss_uops[1].bits.ldst
invalidate iss_uops[1].bits.ldst_is_rs1
invalidate iss_uops[1].bits.csr_cmd
invalidate iss_uops[1].bits.flush_on_commit
invalidate iss_uops[1].bits.is_unique
invalidate iss_uops[1].bits.uses_stq
invalidate iss_uops[1].bits.uses_ldq
invalidate iss_uops[1].bits.mem_signed
invalidate iss_uops[1].bits.mem_size
invalidate iss_uops[1].bits.mem_cmd
invalidate iss_uops[1].bits.exc_cause
invalidate iss_uops[1].bits.exception
invalidate iss_uops[1].bits.stale_pdst
invalidate iss_uops[1].bits.ppred_busy
invalidate iss_uops[1].bits.prs3_busy
invalidate iss_uops[1].bits.prs2_busy
invalidate iss_uops[1].bits.prs1_busy
invalidate iss_uops[1].bits.ppred
invalidate iss_uops[1].bits.prs3
invalidate iss_uops[1].bits.prs2
invalidate iss_uops[1].bits.prs1
invalidate iss_uops[1].bits.pdst
invalidate iss_uops[1].bits.rxq_idx
invalidate iss_uops[1].bits.stq_idx
invalidate iss_uops[1].bits.ldq_idx
invalidate iss_uops[1].bits.rob_idx
invalidate iss_uops[1].bits.fp_ctrl.vec
invalidate iss_uops[1].bits.fp_ctrl.wflags
invalidate iss_uops[1].bits.fp_ctrl.sqrt
invalidate iss_uops[1].bits.fp_ctrl.div
invalidate iss_uops[1].bits.fp_ctrl.fma
invalidate iss_uops[1].bits.fp_ctrl.fastpipe
invalidate iss_uops[1].bits.fp_ctrl.toint
invalidate iss_uops[1].bits.fp_ctrl.fromint
invalidate iss_uops[1].bits.fp_ctrl.typeTagOut
invalidate iss_uops[1].bits.fp_ctrl.typeTagIn
invalidate iss_uops[1].bits.fp_ctrl.swap23
invalidate iss_uops[1].bits.fp_ctrl.swap12
invalidate iss_uops[1].bits.fp_ctrl.ren3
invalidate iss_uops[1].bits.fp_ctrl.ren2
invalidate iss_uops[1].bits.fp_ctrl.ren1
invalidate iss_uops[1].bits.fp_ctrl.wen
invalidate iss_uops[1].bits.fp_ctrl.ldst
invalidate iss_uops[1].bits.op2_sel
invalidate iss_uops[1].bits.op1_sel
invalidate iss_uops[1].bits.imm_packed
invalidate iss_uops[1].bits.pimm
invalidate iss_uops[1].bits.imm_sel
invalidate iss_uops[1].bits.imm_rename
invalidate iss_uops[1].bits.taken
invalidate iss_uops[1].bits.pc_lob
invalidate iss_uops[1].bits.edge_inst
invalidate iss_uops[1].bits.ftq_idx
invalidate iss_uops[1].bits.is_mov
invalidate iss_uops[1].bits.is_rocc
invalidate iss_uops[1].bits.is_sys_pc2epc
invalidate iss_uops[1].bits.is_eret
invalidate iss_uops[1].bits.is_amo
invalidate iss_uops[1].bits.is_sfence
invalidate iss_uops[1].bits.is_fencei
invalidate iss_uops[1].bits.is_fence
invalidate iss_uops[1].bits.is_sfb
invalidate iss_uops[1].bits.br_type
invalidate iss_uops[1].bits.br_tag
invalidate iss_uops[1].bits.br_mask
invalidate iss_uops[1].bits.dis_col_sel
invalidate iss_uops[1].bits.iw_p3_bypass_hint
invalidate iss_uops[1].bits.iw_p2_bypass_hint
invalidate iss_uops[1].bits.iw_p1_bypass_hint
invalidate iss_uops[1].bits.iw_p2_speculative_child
invalidate iss_uops[1].bits.iw_p1_speculative_child
invalidate iss_uops[1].bits.iw_issued_partial_dgen
invalidate iss_uops[1].bits.iw_issued_partial_agen
invalidate iss_uops[1].bits.iw_issued
invalidate iss_uops[1].bits.fu_code[0]
invalidate iss_uops[1].bits.fu_code[1]
invalidate iss_uops[1].bits.fu_code[2]
invalidate iss_uops[1].bits.fu_code[3]
invalidate iss_uops[1].bits.fu_code[4]
invalidate iss_uops[1].bits.fu_code[5]
invalidate iss_uops[1].bits.fu_code[6]
invalidate iss_uops[1].bits.fu_code[7]
invalidate iss_uops[1].bits.fu_code[8]
invalidate iss_uops[1].bits.fu_code[9]
invalidate iss_uops[1].bits.iq_type[0]
invalidate iss_uops[1].bits.iq_type[1]
invalidate iss_uops[1].bits.iq_type[2]
invalidate iss_uops[1].bits.iq_type[3]
invalidate iss_uops[1].bits.debug_pc
invalidate iss_uops[1].bits.is_rvc
invalidate iss_uops[1].bits.debug_inst
invalidate iss_uops[1].bits.inst
connect issue_slots[0].grant, UInt<1>(0h0)
node _fu_code_match_T = and(issue_slots[0].iss_uop.fu_code[0], io.fu_types[0][0])
node _fu_code_match_T_1 = and(issue_slots[0].iss_uop.fu_code[1], io.fu_types[0][1])
node _fu_code_match_T_2 = and(issue_slots[0].iss_uop.fu_code[2], io.fu_types[0][2])
node _fu_code_match_T_3 = and(issue_slots[0].iss_uop.fu_code[3], io.fu_types[0][3])
node _fu_code_match_T_4 = and(issue_slots[0].iss_uop.fu_code[4], io.fu_types[0][4])
node _fu_code_match_T_5 = and(issue_slots[0].iss_uop.fu_code[5], io.fu_types[0][5])
node _fu_code_match_T_6 = and(issue_slots[0].iss_uop.fu_code[6], io.fu_types[0][6])
node _fu_code_match_T_7 = and(issue_slots[0].iss_uop.fu_code[7], io.fu_types[0][7])
node _fu_code_match_T_8 = and(issue_slots[0].iss_uop.fu_code[8], io.fu_types[0][8])
node _fu_code_match_T_9 = and(issue_slots[0].iss_uop.fu_code[9], io.fu_types[0][9])
node _fu_code_match_T_10 = or(_fu_code_match_T, _fu_code_match_T_1)
node _fu_code_match_T_11 = or(_fu_code_match_T_10, _fu_code_match_T_2)
node _fu_code_match_T_12 = or(_fu_code_match_T_11, _fu_code_match_T_3)
node _fu_code_match_T_13 = or(_fu_code_match_T_12, _fu_code_match_T_4)
node _fu_code_match_T_14 = or(_fu_code_match_T_13, _fu_code_match_T_5)
node _fu_code_match_T_15 = or(_fu_code_match_T_14, _fu_code_match_T_6)
node _fu_code_match_T_16 = or(_fu_code_match_T_15, _fu_code_match_T_7)
node _fu_code_match_T_17 = or(_fu_code_match_T_16, _fu_code_match_T_8)
node fu_code_match = or(_fu_code_match_T_17, _fu_code_match_T_9)
node can_allocate = and(fu_code_match, UInt<1>(0h1))
node _T_296 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_297 = and(issue_slots[0].request, _T_296)
node _T_298 = and(_T_297, can_allocate)
node _T_299 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_300 = and(_T_298, _T_299)
when _T_300 :
connect issue_slots[0].grant, UInt<1>(0h1)
connect iss_uops[0].valid, UInt<1>(0h1)
connect iss_uops[0].bits, issue_slots[0].iss_uop
node _T_301 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_302 = and(issue_slots[0].request, _T_301)
node _T_303 = and(_T_302, can_allocate)
node _T_304 = or(_T_303, UInt<1>(0h0))
node _T_305 = and(issue_slots[0].request, can_allocate)
node _T_306 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_307 = and(_T_305, _T_306)
node _T_308 = or(_T_307, UInt<1>(0h0))
node _fu_code_match_T_18 = and(issue_slots[0].iss_uop.fu_code[0], io.fu_types[1][0])
node _fu_code_match_T_19 = and(issue_slots[0].iss_uop.fu_code[1], io.fu_types[1][1])
node _fu_code_match_T_20 = and(issue_slots[0].iss_uop.fu_code[2], io.fu_types[1][2])
node _fu_code_match_T_21 = and(issue_slots[0].iss_uop.fu_code[3], io.fu_types[1][3])
node _fu_code_match_T_22 = and(issue_slots[0].iss_uop.fu_code[4], io.fu_types[1][4])
node _fu_code_match_T_23 = and(issue_slots[0].iss_uop.fu_code[5], io.fu_types[1][5])
node _fu_code_match_T_24 = and(issue_slots[0].iss_uop.fu_code[6], io.fu_types[1][6])
node _fu_code_match_T_25 = and(issue_slots[0].iss_uop.fu_code[7], io.fu_types[1][7])
node _fu_code_match_T_26 = and(issue_slots[0].iss_uop.fu_code[8], io.fu_types[1][8])
node _fu_code_match_T_27 = and(issue_slots[0].iss_uop.fu_code[9], io.fu_types[1][9])
node _fu_code_match_T_28 = or(_fu_code_match_T_18, _fu_code_match_T_19)
node _fu_code_match_T_29 = or(_fu_code_match_T_28, _fu_code_match_T_20)
node _fu_code_match_T_30 = or(_fu_code_match_T_29, _fu_code_match_T_21)
node _fu_code_match_T_31 = or(_fu_code_match_T_30, _fu_code_match_T_22)
node _fu_code_match_T_32 = or(_fu_code_match_T_31, _fu_code_match_T_23)
node _fu_code_match_T_33 = or(_fu_code_match_T_32, _fu_code_match_T_24)
node _fu_code_match_T_34 = or(_fu_code_match_T_33, _fu_code_match_T_25)
node _fu_code_match_T_35 = or(_fu_code_match_T_34, _fu_code_match_T_26)
node fu_code_match_1 = or(_fu_code_match_T_35, _fu_code_match_T_27)
node can_allocate_1 = and(fu_code_match_1, UInt<1>(0h1))
node _T_309 = eq(_T_308, UInt<1>(0h0))
node _T_310 = and(issue_slots[0].request, _T_309)
node _T_311 = and(_T_310, can_allocate_1)
node _T_312 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_313 = and(_T_311, _T_312)
when _T_313 :
connect issue_slots[0].grant, UInt<1>(0h1)
connect iss_uops[1].valid, UInt<1>(0h1)
connect iss_uops[1].bits, issue_slots[0].iss_uop
node _T_314 = eq(_T_308, UInt<1>(0h0))
node _T_315 = and(issue_slots[0].request, _T_314)
node _T_316 = and(_T_315, can_allocate_1)
node _T_317 = or(_T_316, UInt<1>(0h0))
node _T_318 = and(issue_slots[0].request, can_allocate_1)
node _T_319 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_320 = and(_T_318, _T_319)
node _T_321 = or(_T_320, _T_308)
connect issue_slots[1].grant, UInt<1>(0h0)
node _fu_code_match_T_36 = and(issue_slots[1].iss_uop.fu_code[0], io.fu_types[0][0])
node _fu_code_match_T_37 = and(issue_slots[1].iss_uop.fu_code[1], io.fu_types[0][1])
node _fu_code_match_T_38 = and(issue_slots[1].iss_uop.fu_code[2], io.fu_types[0][2])
node _fu_code_match_T_39 = and(issue_slots[1].iss_uop.fu_code[3], io.fu_types[0][3])
node _fu_code_match_T_40 = and(issue_slots[1].iss_uop.fu_code[4], io.fu_types[0][4])
node _fu_code_match_T_41 = and(issue_slots[1].iss_uop.fu_code[5], io.fu_types[0][5])
node _fu_code_match_T_42 = and(issue_slots[1].iss_uop.fu_code[6], io.fu_types[0][6])
node _fu_code_match_T_43 = and(issue_slots[1].iss_uop.fu_code[7], io.fu_types[0][7])
node _fu_code_match_T_44 = and(issue_slots[1].iss_uop.fu_code[8], io.fu_types[0][8])
node _fu_code_match_T_45 = and(issue_slots[1].iss_uop.fu_code[9], io.fu_types[0][9])
node _fu_code_match_T_46 = or(_fu_code_match_T_36, _fu_code_match_T_37)
node _fu_code_match_T_47 = or(_fu_code_match_T_46, _fu_code_match_T_38)
node _fu_code_match_T_48 = or(_fu_code_match_T_47, _fu_code_match_T_39)
node _fu_code_match_T_49 = or(_fu_code_match_T_48, _fu_code_match_T_40)
node _fu_code_match_T_50 = or(_fu_code_match_T_49, _fu_code_match_T_41)
node _fu_code_match_T_51 = or(_fu_code_match_T_50, _fu_code_match_T_42)
node _fu_code_match_T_52 = or(_fu_code_match_T_51, _fu_code_match_T_43)
node _fu_code_match_T_53 = or(_fu_code_match_T_52, _fu_code_match_T_44)
node fu_code_match_2 = or(_fu_code_match_T_53, _fu_code_match_T_45)
node can_allocate_2 = and(fu_code_match_2, UInt<1>(0h1))
node _T_322 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_323 = and(issue_slots[1].request, _T_322)
node _T_324 = and(_T_323, can_allocate_2)
node _T_325 = eq(_T_304, UInt<1>(0h0))
node _T_326 = and(_T_324, _T_325)
when _T_326 :
connect issue_slots[1].grant, UInt<1>(0h1)
connect iss_uops[0].valid, UInt<1>(0h1)
connect iss_uops[0].bits, issue_slots[1].iss_uop
node _T_327 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_328 = and(issue_slots[1].request, _T_327)
node _T_329 = and(_T_328, can_allocate_2)
node _T_330 = or(_T_329, _T_304)
node _T_331 = and(issue_slots[1].request, can_allocate_2)
node _T_332 = eq(_T_304, UInt<1>(0h0))
node _T_333 = and(_T_331, _T_332)
node _T_334 = or(_T_333, UInt<1>(0h0))
node _fu_code_match_T_54 = and(issue_slots[1].iss_uop.fu_code[0], io.fu_types[1][0])
node _fu_code_match_T_55 = and(issue_slots[1].iss_uop.fu_code[1], io.fu_types[1][1])
node _fu_code_match_T_56 = and(issue_slots[1].iss_uop.fu_code[2], io.fu_types[1][2])
node _fu_code_match_T_57 = and(issue_slots[1].iss_uop.fu_code[3], io.fu_types[1][3])
node _fu_code_match_T_58 = and(issue_slots[1].iss_uop.fu_code[4], io.fu_types[1][4])
node _fu_code_match_T_59 = and(issue_slots[1].iss_uop.fu_code[5], io.fu_types[1][5])
node _fu_code_match_T_60 = and(issue_slots[1].iss_uop.fu_code[6], io.fu_types[1][6])
node _fu_code_match_T_61 = and(issue_slots[1].iss_uop.fu_code[7], io.fu_types[1][7])
node _fu_code_match_T_62 = and(issue_slots[1].iss_uop.fu_code[8], io.fu_types[1][8])
node _fu_code_match_T_63 = and(issue_slots[1].iss_uop.fu_code[9], io.fu_types[1][9])
node _fu_code_match_T_64 = or(_fu_code_match_T_54, _fu_code_match_T_55)
node _fu_code_match_T_65 = or(_fu_code_match_T_64, _fu_code_match_T_56)
node _fu_code_match_T_66 = or(_fu_code_match_T_65, _fu_code_match_T_57)
node _fu_code_match_T_67 = or(_fu_code_match_T_66, _fu_code_match_T_58)
node _fu_code_match_T_68 = or(_fu_code_match_T_67, _fu_code_match_T_59)
node _fu_code_match_T_69 = or(_fu_code_match_T_68, _fu_code_match_T_60)
node _fu_code_match_T_70 = or(_fu_code_match_T_69, _fu_code_match_T_61)
node _fu_code_match_T_71 = or(_fu_code_match_T_70, _fu_code_match_T_62)
node fu_code_match_3 = or(_fu_code_match_T_71, _fu_code_match_T_63)
node can_allocate_3 = and(fu_code_match_3, UInt<1>(0h1))
node _T_335 = eq(_T_334, UInt<1>(0h0))
node _T_336 = and(issue_slots[1].request, _T_335)
node _T_337 = and(_T_336, can_allocate_3)
node _T_338 = eq(_T_317, UInt<1>(0h0))
node _T_339 = and(_T_337, _T_338)
when _T_339 :
connect issue_slots[1].grant, UInt<1>(0h1)
connect iss_uops[1].valid, UInt<1>(0h1)
connect iss_uops[1].bits, issue_slots[1].iss_uop
node _T_340 = eq(_T_334, UInt<1>(0h0))
node _T_341 = and(issue_slots[1].request, _T_340)
node _T_342 = and(_T_341, can_allocate_3)
node _T_343 = or(_T_342, _T_317)
node _T_344 = and(issue_slots[1].request, can_allocate_3)
node _T_345 = eq(_T_317, UInt<1>(0h0))
node _T_346 = and(_T_344, _T_345)
node _T_347 = or(_T_346, _T_334)
connect issue_slots[2].grant, UInt<1>(0h0)
node _fu_code_match_T_72 = and(issue_slots[2].iss_uop.fu_code[0], io.fu_types[0][0])
node _fu_code_match_T_73 = and(issue_slots[2].iss_uop.fu_code[1], io.fu_types[0][1])
node _fu_code_match_T_74 = and(issue_slots[2].iss_uop.fu_code[2], io.fu_types[0][2])
node _fu_code_match_T_75 = and(issue_slots[2].iss_uop.fu_code[3], io.fu_types[0][3])
node _fu_code_match_T_76 = and(issue_slots[2].iss_uop.fu_code[4], io.fu_types[0][4])
node _fu_code_match_T_77 = and(issue_slots[2].iss_uop.fu_code[5], io.fu_types[0][5])
node _fu_code_match_T_78 = and(issue_slots[2].iss_uop.fu_code[6], io.fu_types[0][6])
node _fu_code_match_T_79 = and(issue_slots[2].iss_uop.fu_code[7], io.fu_types[0][7])
node _fu_code_match_T_80 = and(issue_slots[2].iss_uop.fu_code[8], io.fu_types[0][8])
node _fu_code_match_T_81 = and(issue_slots[2].iss_uop.fu_code[9], io.fu_types[0][9])
node _fu_code_match_T_82 = or(_fu_code_match_T_72, _fu_code_match_T_73)
node _fu_code_match_T_83 = or(_fu_code_match_T_82, _fu_code_match_T_74)
node _fu_code_match_T_84 = or(_fu_code_match_T_83, _fu_code_match_T_75)
node _fu_code_match_T_85 = or(_fu_code_match_T_84, _fu_code_match_T_76)
node _fu_code_match_T_86 = or(_fu_code_match_T_85, _fu_code_match_T_77)
node _fu_code_match_T_87 = or(_fu_code_match_T_86, _fu_code_match_T_78)
node _fu_code_match_T_88 = or(_fu_code_match_T_87, _fu_code_match_T_79)
node _fu_code_match_T_89 = or(_fu_code_match_T_88, _fu_code_match_T_80)
node fu_code_match_4 = or(_fu_code_match_T_89, _fu_code_match_T_81)
node can_allocate_4 = and(fu_code_match_4, UInt<1>(0h1))
node _T_348 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_349 = and(issue_slots[2].request, _T_348)
node _T_350 = and(_T_349, can_allocate_4)
node _T_351 = eq(_T_330, UInt<1>(0h0))
node _T_352 = and(_T_350, _T_351)
when _T_352 :
connect issue_slots[2].grant, UInt<1>(0h1)
connect iss_uops[0].valid, UInt<1>(0h1)
connect iss_uops[0].bits, issue_slots[2].iss_uop
node _T_353 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_354 = and(issue_slots[2].request, _T_353)
node _T_355 = and(_T_354, can_allocate_4)
node _T_356 = or(_T_355, _T_330)
node _T_357 = and(issue_slots[2].request, can_allocate_4)
node _T_358 = eq(_T_330, UInt<1>(0h0))
node _T_359 = and(_T_357, _T_358)
node _T_360 = or(_T_359, UInt<1>(0h0))
node _fu_code_match_T_90 = and(issue_slots[2].iss_uop.fu_code[0], io.fu_types[1][0])
node _fu_code_match_T_91 = and(issue_slots[2].iss_uop.fu_code[1], io.fu_types[1][1])
node _fu_code_match_T_92 = and(issue_slots[2].iss_uop.fu_code[2], io.fu_types[1][2])
node _fu_code_match_T_93 = and(issue_slots[2].iss_uop.fu_code[3], io.fu_types[1][3])
node _fu_code_match_T_94 = and(issue_slots[2].iss_uop.fu_code[4], io.fu_types[1][4])
node _fu_code_match_T_95 = and(issue_slots[2].iss_uop.fu_code[5], io.fu_types[1][5])
node _fu_code_match_T_96 = and(issue_slots[2].iss_uop.fu_code[6], io.fu_types[1][6])
node _fu_code_match_T_97 = and(issue_slots[2].iss_uop.fu_code[7], io.fu_types[1][7])
node _fu_code_match_T_98 = and(issue_slots[2].iss_uop.fu_code[8], io.fu_types[1][8])
node _fu_code_match_T_99 = and(issue_slots[2].iss_uop.fu_code[9], io.fu_types[1][9])
node _fu_code_match_T_100 = or(_fu_code_match_T_90, _fu_code_match_T_91)
node _fu_code_match_T_101 = or(_fu_code_match_T_100, _fu_code_match_T_92)
node _fu_code_match_T_102 = or(_fu_code_match_T_101, _fu_code_match_T_93)
node _fu_code_match_T_103 = or(_fu_code_match_T_102, _fu_code_match_T_94)
node _fu_code_match_T_104 = or(_fu_code_match_T_103, _fu_code_match_T_95)
node _fu_code_match_T_105 = or(_fu_code_match_T_104, _fu_code_match_T_96)
node _fu_code_match_T_106 = or(_fu_code_match_T_105, _fu_code_match_T_97)
node _fu_code_match_T_107 = or(_fu_code_match_T_106, _fu_code_match_T_98)
node fu_code_match_5 = or(_fu_code_match_T_107, _fu_code_match_T_99)
node can_allocate_5 = and(fu_code_match_5, UInt<1>(0h1))
node _T_361 = eq(_T_360, UInt<1>(0h0))
node _T_362 = and(issue_slots[2].request, _T_361)
node _T_363 = and(_T_362, can_allocate_5)
node _T_364 = eq(_T_343, UInt<1>(0h0))
node _T_365 = and(_T_363, _T_364)
when _T_365 :
connect issue_slots[2].grant, UInt<1>(0h1)
connect iss_uops[1].valid, UInt<1>(0h1)
connect iss_uops[1].bits, issue_slots[2].iss_uop
node _T_366 = eq(_T_360, UInt<1>(0h0))
node _T_367 = and(issue_slots[2].request, _T_366)
node _T_368 = and(_T_367, can_allocate_5)
node _T_369 = or(_T_368, _T_343)
node _T_370 = and(issue_slots[2].request, can_allocate_5)
node _T_371 = eq(_T_343, UInt<1>(0h0))
node _T_372 = and(_T_370, _T_371)
node _T_373 = or(_T_372, _T_360)
connect issue_slots[3].grant, UInt<1>(0h0)
node _fu_code_match_T_108 = and(issue_slots[3].iss_uop.fu_code[0], io.fu_types[0][0])
node _fu_code_match_T_109 = and(issue_slots[3].iss_uop.fu_code[1], io.fu_types[0][1])
node _fu_code_match_T_110 = and(issue_slots[3].iss_uop.fu_code[2], io.fu_types[0][2])
node _fu_code_match_T_111 = and(issue_slots[3].iss_uop.fu_code[3], io.fu_types[0][3])
node _fu_code_match_T_112 = and(issue_slots[3].iss_uop.fu_code[4], io.fu_types[0][4])
node _fu_code_match_T_113 = and(issue_slots[3].iss_uop.fu_code[5], io.fu_types[0][5])
node _fu_code_match_T_114 = and(issue_slots[3].iss_uop.fu_code[6], io.fu_types[0][6])
node _fu_code_match_T_115 = and(issue_slots[3].iss_uop.fu_code[7], io.fu_types[0][7])
node _fu_code_match_T_116 = and(issue_slots[3].iss_uop.fu_code[8], io.fu_types[0][8])
node _fu_code_match_T_117 = and(issue_slots[3].iss_uop.fu_code[9], io.fu_types[0][9])
node _fu_code_match_T_118 = or(_fu_code_match_T_108, _fu_code_match_T_109)
node _fu_code_match_T_119 = or(_fu_code_match_T_118, _fu_code_match_T_110)
node _fu_code_match_T_120 = or(_fu_code_match_T_119, _fu_code_match_T_111)
node _fu_code_match_T_121 = or(_fu_code_match_T_120, _fu_code_match_T_112)
node _fu_code_match_T_122 = or(_fu_code_match_T_121, _fu_code_match_T_113)
node _fu_code_match_T_123 = or(_fu_code_match_T_122, _fu_code_match_T_114)
node _fu_code_match_T_124 = or(_fu_code_match_T_123, _fu_code_match_T_115)
node _fu_code_match_T_125 = or(_fu_code_match_T_124, _fu_code_match_T_116)
node fu_code_match_6 = or(_fu_code_match_T_125, _fu_code_match_T_117)
node can_allocate_6 = and(fu_code_match_6, UInt<1>(0h1))
node _T_374 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_375 = and(issue_slots[3].request, _T_374)
node _T_376 = and(_T_375, can_allocate_6)
node _T_377 = eq(_T_356, UInt<1>(0h0))
node _T_378 = and(_T_376, _T_377)
when _T_378 :
connect issue_slots[3].grant, UInt<1>(0h1)
connect iss_uops[0].valid, UInt<1>(0h1)
connect iss_uops[0].bits, issue_slots[3].iss_uop
node _T_379 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_380 = and(issue_slots[3].request, _T_379)
node _T_381 = and(_T_380, can_allocate_6)
node _T_382 = or(_T_381, _T_356)
node _T_383 = and(issue_slots[3].request, can_allocate_6)
node _T_384 = eq(_T_356, UInt<1>(0h0))
node _T_385 = and(_T_383, _T_384)
node _T_386 = or(_T_385, UInt<1>(0h0))
node _fu_code_match_T_126 = and(issue_slots[3].iss_uop.fu_code[0], io.fu_types[1][0])
node _fu_code_match_T_127 = and(issue_slots[3].iss_uop.fu_code[1], io.fu_types[1][1])
node _fu_code_match_T_128 = and(issue_slots[3].iss_uop.fu_code[2], io.fu_types[1][2])
node _fu_code_match_T_129 = and(issue_slots[3].iss_uop.fu_code[3], io.fu_types[1][3])
node _fu_code_match_T_130 = and(issue_slots[3].iss_uop.fu_code[4], io.fu_types[1][4])
node _fu_code_match_T_131 = and(issue_slots[3].iss_uop.fu_code[5], io.fu_types[1][5])
node _fu_code_match_T_132 = and(issue_slots[3].iss_uop.fu_code[6], io.fu_types[1][6])
node _fu_code_match_T_133 = and(issue_slots[3].iss_uop.fu_code[7], io.fu_types[1][7])
node _fu_code_match_T_134 = and(issue_slots[3].iss_uop.fu_code[8], io.fu_types[1][8])
node _fu_code_match_T_135 = and(issue_slots[3].iss_uop.fu_code[9], io.fu_types[1][9])
node _fu_code_match_T_136 = or(_fu_code_match_T_126, _fu_code_match_T_127)
node _fu_code_match_T_137 = or(_fu_code_match_T_136, _fu_code_match_T_128)
node _fu_code_match_T_138 = or(_fu_code_match_T_137, _fu_code_match_T_129)
node _fu_code_match_T_139 = or(_fu_code_match_T_138, _fu_code_match_T_130)
node _fu_code_match_T_140 = or(_fu_code_match_T_139, _fu_code_match_T_131)
node _fu_code_match_T_141 = or(_fu_code_match_T_140, _fu_code_match_T_132)
node _fu_code_match_T_142 = or(_fu_code_match_T_141, _fu_code_match_T_133)
node _fu_code_match_T_143 = or(_fu_code_match_T_142, _fu_code_match_T_134)
node fu_code_match_7 = or(_fu_code_match_T_143, _fu_code_match_T_135)
node can_allocate_7 = and(fu_code_match_7, UInt<1>(0h1))
node _T_387 = eq(_T_386, UInt<1>(0h0))
node _T_388 = and(issue_slots[3].request, _T_387)
node _T_389 = and(_T_388, can_allocate_7)
node _T_390 = eq(_T_369, UInt<1>(0h0))
node _T_391 = and(_T_389, _T_390)
when _T_391 :
connect issue_slots[3].grant, UInt<1>(0h1)
connect iss_uops[1].valid, UInt<1>(0h1)
connect iss_uops[1].bits, issue_slots[3].iss_uop
node _T_392 = eq(_T_386, UInt<1>(0h0))
node _T_393 = and(issue_slots[3].request, _T_392)
node _T_394 = and(_T_393, can_allocate_7)
node _T_395 = or(_T_394, _T_369)
node _T_396 = and(issue_slots[3].request, can_allocate_7)
node _T_397 = eq(_T_369, UInt<1>(0h0))
node _T_398 = and(_T_396, _T_397)
node _T_399 = or(_T_398, _T_386)
connect issue_slots[4].grant, UInt<1>(0h0)
node _fu_code_match_T_144 = and(issue_slots[4].iss_uop.fu_code[0], io.fu_types[0][0])
node _fu_code_match_T_145 = and(issue_slots[4].iss_uop.fu_code[1], io.fu_types[0][1])
node _fu_code_match_T_146 = and(issue_slots[4].iss_uop.fu_code[2], io.fu_types[0][2])
node _fu_code_match_T_147 = and(issue_slots[4].iss_uop.fu_code[3], io.fu_types[0][3])
node _fu_code_match_T_148 = and(issue_slots[4].iss_uop.fu_code[4], io.fu_types[0][4])
node _fu_code_match_T_149 = and(issue_slots[4].iss_uop.fu_code[5], io.fu_types[0][5])
node _fu_code_match_T_150 = and(issue_slots[4].iss_uop.fu_code[6], io.fu_types[0][6])
node _fu_code_match_T_151 = and(issue_slots[4].iss_uop.fu_code[7], io.fu_types[0][7])
node _fu_code_match_T_152 = and(issue_slots[4].iss_uop.fu_code[8], io.fu_types[0][8])
node _fu_code_match_T_153 = and(issue_slots[4].iss_uop.fu_code[9], io.fu_types[0][9])
node _fu_code_match_T_154 = or(_fu_code_match_T_144, _fu_code_match_T_145)
node _fu_code_match_T_155 = or(_fu_code_match_T_154, _fu_code_match_T_146)
node _fu_code_match_T_156 = or(_fu_code_match_T_155, _fu_code_match_T_147)
node _fu_code_match_T_157 = or(_fu_code_match_T_156, _fu_code_match_T_148)
node _fu_code_match_T_158 = or(_fu_code_match_T_157, _fu_code_match_T_149)
node _fu_code_match_T_159 = or(_fu_code_match_T_158, _fu_code_match_T_150)
node _fu_code_match_T_160 = or(_fu_code_match_T_159, _fu_code_match_T_151)
node _fu_code_match_T_161 = or(_fu_code_match_T_160, _fu_code_match_T_152)
node fu_code_match_8 = or(_fu_code_match_T_161, _fu_code_match_T_153)
node can_allocate_8 = and(fu_code_match_8, UInt<1>(0h1))
node _T_400 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_401 = and(issue_slots[4].request, _T_400)
node _T_402 = and(_T_401, can_allocate_8)
node _T_403 = eq(_T_382, UInt<1>(0h0))
node _T_404 = and(_T_402, _T_403)
when _T_404 :
connect issue_slots[4].grant, UInt<1>(0h1)
connect iss_uops[0].valid, UInt<1>(0h1)
connect iss_uops[0].bits, issue_slots[4].iss_uop
node _T_405 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_406 = and(issue_slots[4].request, _T_405)
node _T_407 = and(_T_406, can_allocate_8)
node _T_408 = or(_T_407, _T_382)
node _T_409 = and(issue_slots[4].request, can_allocate_8)
node _T_410 = eq(_T_382, UInt<1>(0h0))
node _T_411 = and(_T_409, _T_410)
node _T_412 = or(_T_411, UInt<1>(0h0))
node _fu_code_match_T_162 = and(issue_slots[4].iss_uop.fu_code[0], io.fu_types[1][0])
node _fu_code_match_T_163 = and(issue_slots[4].iss_uop.fu_code[1], io.fu_types[1][1])
node _fu_code_match_T_164 = and(issue_slots[4].iss_uop.fu_code[2], io.fu_types[1][2])
node _fu_code_match_T_165 = and(issue_slots[4].iss_uop.fu_code[3], io.fu_types[1][3])
node _fu_code_match_T_166 = and(issue_slots[4].iss_uop.fu_code[4], io.fu_types[1][4])
node _fu_code_match_T_167 = and(issue_slots[4].iss_uop.fu_code[5], io.fu_types[1][5])
node _fu_code_match_T_168 = and(issue_slots[4].iss_uop.fu_code[6], io.fu_types[1][6])
node _fu_code_match_T_169 = and(issue_slots[4].iss_uop.fu_code[7], io.fu_types[1][7])
node _fu_code_match_T_170 = and(issue_slots[4].iss_uop.fu_code[8], io.fu_types[1][8])
node _fu_code_match_T_171 = and(issue_slots[4].iss_uop.fu_code[9], io.fu_types[1][9])
node _fu_code_match_T_172 = or(_fu_code_match_T_162, _fu_code_match_T_163)
node _fu_code_match_T_173 = or(_fu_code_match_T_172, _fu_code_match_T_164)
node _fu_code_match_T_174 = or(_fu_code_match_T_173, _fu_code_match_T_165)
node _fu_code_match_T_175 = or(_fu_code_match_T_174, _fu_code_match_T_166)
node _fu_code_match_T_176 = or(_fu_code_match_T_175, _fu_code_match_T_167)
node _fu_code_match_T_177 = or(_fu_code_match_T_176, _fu_code_match_T_168)
node _fu_code_match_T_178 = or(_fu_code_match_T_177, _fu_code_match_T_169)
node _fu_code_match_T_179 = or(_fu_code_match_T_178, _fu_code_match_T_170)
node fu_code_match_9 = or(_fu_code_match_T_179, _fu_code_match_T_171)
node can_allocate_9 = and(fu_code_match_9, UInt<1>(0h1))
node _T_413 = eq(_T_412, UInt<1>(0h0))
node _T_414 = and(issue_slots[4].request, _T_413)
node _T_415 = and(_T_414, can_allocate_9)
node _T_416 = eq(_T_395, UInt<1>(0h0))
node _T_417 = and(_T_415, _T_416)
when _T_417 :
connect issue_slots[4].grant, UInt<1>(0h1)
connect iss_uops[1].valid, UInt<1>(0h1)
connect iss_uops[1].bits, issue_slots[4].iss_uop
node _T_418 = eq(_T_412, UInt<1>(0h0))
node _T_419 = and(issue_slots[4].request, _T_418)
node _T_420 = and(_T_419, can_allocate_9)
node _T_421 = or(_T_420, _T_395)
node _T_422 = and(issue_slots[4].request, can_allocate_9)
node _T_423 = eq(_T_395, UInt<1>(0h0))
node _T_424 = and(_T_422, _T_423)
node _T_425 = or(_T_424, _T_412)
connect issue_slots[5].grant, UInt<1>(0h0)
node _fu_code_match_T_180 = and(issue_slots[5].iss_uop.fu_code[0], io.fu_types[0][0])
node _fu_code_match_T_181 = and(issue_slots[5].iss_uop.fu_code[1], io.fu_types[0][1])
node _fu_code_match_T_182 = and(issue_slots[5].iss_uop.fu_code[2], io.fu_types[0][2])
node _fu_code_match_T_183 = and(issue_slots[5].iss_uop.fu_code[3], io.fu_types[0][3])
node _fu_code_match_T_184 = and(issue_slots[5].iss_uop.fu_code[4], io.fu_types[0][4])
node _fu_code_match_T_185 = and(issue_slots[5].iss_uop.fu_code[5], io.fu_types[0][5])
node _fu_code_match_T_186 = and(issue_slots[5].iss_uop.fu_code[6], io.fu_types[0][6])
node _fu_code_match_T_187 = and(issue_slots[5].iss_uop.fu_code[7], io.fu_types[0][7])
node _fu_code_match_T_188 = and(issue_slots[5].iss_uop.fu_code[8], io.fu_types[0][8])
node _fu_code_match_T_189 = and(issue_slots[5].iss_uop.fu_code[9], io.fu_types[0][9])
node _fu_code_match_T_190 = or(_fu_code_match_T_180, _fu_code_match_T_181)
node _fu_code_match_T_191 = or(_fu_code_match_T_190, _fu_code_match_T_182)
node _fu_code_match_T_192 = or(_fu_code_match_T_191, _fu_code_match_T_183)
node _fu_code_match_T_193 = or(_fu_code_match_T_192, _fu_code_match_T_184)
node _fu_code_match_T_194 = or(_fu_code_match_T_193, _fu_code_match_T_185)
node _fu_code_match_T_195 = or(_fu_code_match_T_194, _fu_code_match_T_186)
node _fu_code_match_T_196 = or(_fu_code_match_T_195, _fu_code_match_T_187)
node _fu_code_match_T_197 = or(_fu_code_match_T_196, _fu_code_match_T_188)
node fu_code_match_10 = or(_fu_code_match_T_197, _fu_code_match_T_189)
node can_allocate_10 = and(fu_code_match_10, UInt<1>(0h1))
node _T_426 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_427 = and(issue_slots[5].request, _T_426)
node _T_428 = and(_T_427, can_allocate_10)
node _T_429 = eq(_T_408, UInt<1>(0h0))
node _T_430 = and(_T_428, _T_429)
when _T_430 :
connect issue_slots[5].grant, UInt<1>(0h1)
connect iss_uops[0].valid, UInt<1>(0h1)
connect iss_uops[0].bits, issue_slots[5].iss_uop
node _T_431 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_432 = and(issue_slots[5].request, _T_431)
node _T_433 = and(_T_432, can_allocate_10)
node _T_434 = or(_T_433, _T_408)
node _T_435 = and(issue_slots[5].request, can_allocate_10)
node _T_436 = eq(_T_408, UInt<1>(0h0))
node _T_437 = and(_T_435, _T_436)
node _T_438 = or(_T_437, UInt<1>(0h0))
node _fu_code_match_T_198 = and(issue_slots[5].iss_uop.fu_code[0], io.fu_types[1][0])
node _fu_code_match_T_199 = and(issue_slots[5].iss_uop.fu_code[1], io.fu_types[1][1])
node _fu_code_match_T_200 = and(issue_slots[5].iss_uop.fu_code[2], io.fu_types[1][2])
node _fu_code_match_T_201 = and(issue_slots[5].iss_uop.fu_code[3], io.fu_types[1][3])
node _fu_code_match_T_202 = and(issue_slots[5].iss_uop.fu_code[4], io.fu_types[1][4])
node _fu_code_match_T_203 = and(issue_slots[5].iss_uop.fu_code[5], io.fu_types[1][5])
node _fu_code_match_T_204 = and(issue_slots[5].iss_uop.fu_code[6], io.fu_types[1][6])
node _fu_code_match_T_205 = and(issue_slots[5].iss_uop.fu_code[7], io.fu_types[1][7])
node _fu_code_match_T_206 = and(issue_slots[5].iss_uop.fu_code[8], io.fu_types[1][8])
node _fu_code_match_T_207 = and(issue_slots[5].iss_uop.fu_code[9], io.fu_types[1][9])
node _fu_code_match_T_208 = or(_fu_code_match_T_198, _fu_code_match_T_199)
node _fu_code_match_T_209 = or(_fu_code_match_T_208, _fu_code_match_T_200)
node _fu_code_match_T_210 = or(_fu_code_match_T_209, _fu_code_match_T_201)
node _fu_code_match_T_211 = or(_fu_code_match_T_210, _fu_code_match_T_202)
node _fu_code_match_T_212 = or(_fu_code_match_T_211, _fu_code_match_T_203)
node _fu_code_match_T_213 = or(_fu_code_match_T_212, _fu_code_match_T_204)
node _fu_code_match_T_214 = or(_fu_code_match_T_213, _fu_code_match_T_205)
node _fu_code_match_T_215 = or(_fu_code_match_T_214, _fu_code_match_T_206)
node fu_code_match_11 = or(_fu_code_match_T_215, _fu_code_match_T_207)
node can_allocate_11 = and(fu_code_match_11, UInt<1>(0h1))
node _T_439 = eq(_T_438, UInt<1>(0h0))
node _T_440 = and(issue_slots[5].request, _T_439)
node _T_441 = and(_T_440, can_allocate_11)
node _T_442 = eq(_T_421, UInt<1>(0h0))
node _T_443 = and(_T_441, _T_442)
when _T_443 :
connect issue_slots[5].grant, UInt<1>(0h1)
connect iss_uops[1].valid, UInt<1>(0h1)
connect iss_uops[1].bits, issue_slots[5].iss_uop
node _T_444 = eq(_T_438, UInt<1>(0h0))
node _T_445 = and(issue_slots[5].request, _T_444)
node _T_446 = and(_T_445, can_allocate_11)
node _T_447 = or(_T_446, _T_421)
node _T_448 = and(issue_slots[5].request, can_allocate_11)
node _T_449 = eq(_T_421, UInt<1>(0h0))
node _T_450 = and(_T_448, _T_449)
node _T_451 = or(_T_450, _T_438)
connect issue_slots[6].grant, UInt<1>(0h0)
node _fu_code_match_T_216 = and(issue_slots[6].iss_uop.fu_code[0], io.fu_types[0][0])
node _fu_code_match_T_217 = and(issue_slots[6].iss_uop.fu_code[1], io.fu_types[0][1])
node _fu_code_match_T_218 = and(issue_slots[6].iss_uop.fu_code[2], io.fu_types[0][2])
node _fu_code_match_T_219 = and(issue_slots[6].iss_uop.fu_code[3], io.fu_types[0][3])
node _fu_code_match_T_220 = and(issue_slots[6].iss_uop.fu_code[4], io.fu_types[0][4])
node _fu_code_match_T_221 = and(issue_slots[6].iss_uop.fu_code[5], io.fu_types[0][5])
node _fu_code_match_T_222 = and(issue_slots[6].iss_uop.fu_code[6], io.fu_types[0][6])
node _fu_code_match_T_223 = and(issue_slots[6].iss_uop.fu_code[7], io.fu_types[0][7])
node _fu_code_match_T_224 = and(issue_slots[6].iss_uop.fu_code[8], io.fu_types[0][8])
node _fu_code_match_T_225 = and(issue_slots[6].iss_uop.fu_code[9], io.fu_types[0][9])
node _fu_code_match_T_226 = or(_fu_code_match_T_216, _fu_code_match_T_217)
node _fu_code_match_T_227 = or(_fu_code_match_T_226, _fu_code_match_T_218)
node _fu_code_match_T_228 = or(_fu_code_match_T_227, _fu_code_match_T_219)
node _fu_code_match_T_229 = or(_fu_code_match_T_228, _fu_code_match_T_220)
node _fu_code_match_T_230 = or(_fu_code_match_T_229, _fu_code_match_T_221)
node _fu_code_match_T_231 = or(_fu_code_match_T_230, _fu_code_match_T_222)
node _fu_code_match_T_232 = or(_fu_code_match_T_231, _fu_code_match_T_223)
node _fu_code_match_T_233 = or(_fu_code_match_T_232, _fu_code_match_T_224)
node fu_code_match_12 = or(_fu_code_match_T_233, _fu_code_match_T_225)
node can_allocate_12 = and(fu_code_match_12, UInt<1>(0h1))
node _T_452 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_453 = and(issue_slots[6].request, _T_452)
node _T_454 = and(_T_453, can_allocate_12)
node _T_455 = eq(_T_434, UInt<1>(0h0))
node _T_456 = and(_T_454, _T_455)
when _T_456 :
connect issue_slots[6].grant, UInt<1>(0h1)
connect iss_uops[0].valid, UInt<1>(0h1)
connect iss_uops[0].bits, issue_slots[6].iss_uop
node _T_457 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_458 = and(issue_slots[6].request, _T_457)
node _T_459 = and(_T_458, can_allocate_12)
node _T_460 = or(_T_459, _T_434)
node _T_461 = and(issue_slots[6].request, can_allocate_12)
node _T_462 = eq(_T_434, UInt<1>(0h0))
node _T_463 = and(_T_461, _T_462)
node _T_464 = or(_T_463, UInt<1>(0h0))
node _fu_code_match_T_234 = and(issue_slots[6].iss_uop.fu_code[0], io.fu_types[1][0])
node _fu_code_match_T_235 = and(issue_slots[6].iss_uop.fu_code[1], io.fu_types[1][1])
node _fu_code_match_T_236 = and(issue_slots[6].iss_uop.fu_code[2], io.fu_types[1][2])
node _fu_code_match_T_237 = and(issue_slots[6].iss_uop.fu_code[3], io.fu_types[1][3])
node _fu_code_match_T_238 = and(issue_slots[6].iss_uop.fu_code[4], io.fu_types[1][4])
node _fu_code_match_T_239 = and(issue_slots[6].iss_uop.fu_code[5], io.fu_types[1][5])
node _fu_code_match_T_240 = and(issue_slots[6].iss_uop.fu_code[6], io.fu_types[1][6])
node _fu_code_match_T_241 = and(issue_slots[6].iss_uop.fu_code[7], io.fu_types[1][7])
node _fu_code_match_T_242 = and(issue_slots[6].iss_uop.fu_code[8], io.fu_types[1][8])
node _fu_code_match_T_243 = and(issue_slots[6].iss_uop.fu_code[9], io.fu_types[1][9])
node _fu_code_match_T_244 = or(_fu_code_match_T_234, _fu_code_match_T_235)
node _fu_code_match_T_245 = or(_fu_code_match_T_244, _fu_code_match_T_236)
node _fu_code_match_T_246 = or(_fu_code_match_T_245, _fu_code_match_T_237)
node _fu_code_match_T_247 = or(_fu_code_match_T_246, _fu_code_match_T_238)
node _fu_code_match_T_248 = or(_fu_code_match_T_247, _fu_code_match_T_239)
node _fu_code_match_T_249 = or(_fu_code_match_T_248, _fu_code_match_T_240)
node _fu_code_match_T_250 = or(_fu_code_match_T_249, _fu_code_match_T_241)
node _fu_code_match_T_251 = or(_fu_code_match_T_250, _fu_code_match_T_242)
node fu_code_match_13 = or(_fu_code_match_T_251, _fu_code_match_T_243)
node can_allocate_13 = and(fu_code_match_13, UInt<1>(0h1))
node _T_465 = eq(_T_464, UInt<1>(0h0))
node _T_466 = and(issue_slots[6].request, _T_465)
node _T_467 = and(_T_466, can_allocate_13)
node _T_468 = eq(_T_447, UInt<1>(0h0))
node _T_469 = and(_T_467, _T_468)
when _T_469 :
connect issue_slots[6].grant, UInt<1>(0h1)
connect iss_uops[1].valid, UInt<1>(0h1)
connect iss_uops[1].bits, issue_slots[6].iss_uop
node _T_470 = eq(_T_464, UInt<1>(0h0))
node _T_471 = and(issue_slots[6].request, _T_470)
node _T_472 = and(_T_471, can_allocate_13)
node _T_473 = or(_T_472, _T_447)
node _T_474 = and(issue_slots[6].request, can_allocate_13)
node _T_475 = eq(_T_447, UInt<1>(0h0))
node _T_476 = and(_T_474, _T_475)
node _T_477 = or(_T_476, _T_464)
connect issue_slots[7].grant, UInt<1>(0h0)
node _fu_code_match_T_252 = and(issue_slots[7].iss_uop.fu_code[0], io.fu_types[0][0])
node _fu_code_match_T_253 = and(issue_slots[7].iss_uop.fu_code[1], io.fu_types[0][1])
node _fu_code_match_T_254 = and(issue_slots[7].iss_uop.fu_code[2], io.fu_types[0][2])
node _fu_code_match_T_255 = and(issue_slots[7].iss_uop.fu_code[3], io.fu_types[0][3])
node _fu_code_match_T_256 = and(issue_slots[7].iss_uop.fu_code[4], io.fu_types[0][4])
node _fu_code_match_T_257 = and(issue_slots[7].iss_uop.fu_code[5], io.fu_types[0][5])
node _fu_code_match_T_258 = and(issue_slots[7].iss_uop.fu_code[6], io.fu_types[0][6])
node _fu_code_match_T_259 = and(issue_slots[7].iss_uop.fu_code[7], io.fu_types[0][7])
node _fu_code_match_T_260 = and(issue_slots[7].iss_uop.fu_code[8], io.fu_types[0][8])
node _fu_code_match_T_261 = and(issue_slots[7].iss_uop.fu_code[9], io.fu_types[0][9])
node _fu_code_match_T_262 = or(_fu_code_match_T_252, _fu_code_match_T_253)
node _fu_code_match_T_263 = or(_fu_code_match_T_262, _fu_code_match_T_254)
node _fu_code_match_T_264 = or(_fu_code_match_T_263, _fu_code_match_T_255)
node _fu_code_match_T_265 = or(_fu_code_match_T_264, _fu_code_match_T_256)
node _fu_code_match_T_266 = or(_fu_code_match_T_265, _fu_code_match_T_257)
node _fu_code_match_T_267 = or(_fu_code_match_T_266, _fu_code_match_T_258)
node _fu_code_match_T_268 = or(_fu_code_match_T_267, _fu_code_match_T_259)
node _fu_code_match_T_269 = or(_fu_code_match_T_268, _fu_code_match_T_260)
node fu_code_match_14 = or(_fu_code_match_T_269, _fu_code_match_T_261)
node can_allocate_14 = and(fu_code_match_14, UInt<1>(0h1))
node _T_478 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_479 = and(issue_slots[7].request, _T_478)
node _T_480 = and(_T_479, can_allocate_14)
node _T_481 = eq(_T_460, UInt<1>(0h0))
node _T_482 = and(_T_480, _T_481)
when _T_482 :
connect issue_slots[7].grant, UInt<1>(0h1)
connect iss_uops[0].valid, UInt<1>(0h1)
connect iss_uops[0].bits, issue_slots[7].iss_uop
node _T_483 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_484 = and(issue_slots[7].request, _T_483)
node _T_485 = and(_T_484, can_allocate_14)
node _T_486 = or(_T_485, _T_460)
node _T_487 = and(issue_slots[7].request, can_allocate_14)
node _T_488 = eq(_T_460, UInt<1>(0h0))
node _T_489 = and(_T_487, _T_488)
node _T_490 = or(_T_489, UInt<1>(0h0))
node _fu_code_match_T_270 = and(issue_slots[7].iss_uop.fu_code[0], io.fu_types[1][0])
node _fu_code_match_T_271 = and(issue_slots[7].iss_uop.fu_code[1], io.fu_types[1][1])
node _fu_code_match_T_272 = and(issue_slots[7].iss_uop.fu_code[2], io.fu_types[1][2])
node _fu_code_match_T_273 = and(issue_slots[7].iss_uop.fu_code[3], io.fu_types[1][3])
node _fu_code_match_T_274 = and(issue_slots[7].iss_uop.fu_code[4], io.fu_types[1][4])
node _fu_code_match_T_275 = and(issue_slots[7].iss_uop.fu_code[5], io.fu_types[1][5])
node _fu_code_match_T_276 = and(issue_slots[7].iss_uop.fu_code[6], io.fu_types[1][6])
node _fu_code_match_T_277 = and(issue_slots[7].iss_uop.fu_code[7], io.fu_types[1][7])
node _fu_code_match_T_278 = and(issue_slots[7].iss_uop.fu_code[8], io.fu_types[1][8])
node _fu_code_match_T_279 = and(issue_slots[7].iss_uop.fu_code[9], io.fu_types[1][9])
node _fu_code_match_T_280 = or(_fu_code_match_T_270, _fu_code_match_T_271)
node _fu_code_match_T_281 = or(_fu_code_match_T_280, _fu_code_match_T_272)
node _fu_code_match_T_282 = or(_fu_code_match_T_281, _fu_code_match_T_273)
node _fu_code_match_T_283 = or(_fu_code_match_T_282, _fu_code_match_T_274)
node _fu_code_match_T_284 = or(_fu_code_match_T_283, _fu_code_match_T_275)
node _fu_code_match_T_285 = or(_fu_code_match_T_284, _fu_code_match_T_276)
node _fu_code_match_T_286 = or(_fu_code_match_T_285, _fu_code_match_T_277)
node _fu_code_match_T_287 = or(_fu_code_match_T_286, _fu_code_match_T_278)
node fu_code_match_15 = or(_fu_code_match_T_287, _fu_code_match_T_279)
node can_allocate_15 = and(fu_code_match_15, UInt<1>(0h1))
node _T_491 = eq(_T_490, UInt<1>(0h0))
node _T_492 = and(issue_slots[7].request, _T_491)
node _T_493 = and(_T_492, can_allocate_15)
node _T_494 = eq(_T_473, UInt<1>(0h0))
node _T_495 = and(_T_493, _T_494)
when _T_495 :
connect issue_slots[7].grant, UInt<1>(0h1)
connect iss_uops[1].valid, UInt<1>(0h1)
connect iss_uops[1].bits, issue_slots[7].iss_uop
node _T_496 = eq(_T_490, UInt<1>(0h0))
node _T_497 = and(issue_slots[7].request, _T_496)
node _T_498 = and(_T_497, can_allocate_15)
node _T_499 = or(_T_498, _T_473)
node _T_500 = and(issue_slots[7].request, can_allocate_15)
node _T_501 = eq(_T_473, UInt<1>(0h0))
node _T_502 = and(_T_500, _T_501)
node _T_503 = or(_T_502, _T_490)
connect issue_slots[8].grant, UInt<1>(0h0)
node _fu_code_match_T_288 = and(issue_slots[8].iss_uop.fu_code[0], io.fu_types[0][0])
node _fu_code_match_T_289 = and(issue_slots[8].iss_uop.fu_code[1], io.fu_types[0][1])
node _fu_code_match_T_290 = and(issue_slots[8].iss_uop.fu_code[2], io.fu_types[0][2])
node _fu_code_match_T_291 = and(issue_slots[8].iss_uop.fu_code[3], io.fu_types[0][3])
node _fu_code_match_T_292 = and(issue_slots[8].iss_uop.fu_code[4], io.fu_types[0][4])
node _fu_code_match_T_293 = and(issue_slots[8].iss_uop.fu_code[5], io.fu_types[0][5])
node _fu_code_match_T_294 = and(issue_slots[8].iss_uop.fu_code[6], io.fu_types[0][6])
node _fu_code_match_T_295 = and(issue_slots[8].iss_uop.fu_code[7], io.fu_types[0][7])
node _fu_code_match_T_296 = and(issue_slots[8].iss_uop.fu_code[8], io.fu_types[0][8])
node _fu_code_match_T_297 = and(issue_slots[8].iss_uop.fu_code[9], io.fu_types[0][9])
node _fu_code_match_T_298 = or(_fu_code_match_T_288, _fu_code_match_T_289)
node _fu_code_match_T_299 = or(_fu_code_match_T_298, _fu_code_match_T_290)
node _fu_code_match_T_300 = or(_fu_code_match_T_299, _fu_code_match_T_291)
node _fu_code_match_T_301 = or(_fu_code_match_T_300, _fu_code_match_T_292)
node _fu_code_match_T_302 = or(_fu_code_match_T_301, _fu_code_match_T_293)
node _fu_code_match_T_303 = or(_fu_code_match_T_302, _fu_code_match_T_294)
node _fu_code_match_T_304 = or(_fu_code_match_T_303, _fu_code_match_T_295)
node _fu_code_match_T_305 = or(_fu_code_match_T_304, _fu_code_match_T_296)
node fu_code_match_16 = or(_fu_code_match_T_305, _fu_code_match_T_297)
node can_allocate_16 = and(fu_code_match_16, UInt<1>(0h1))
node _T_504 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_505 = and(issue_slots[8].request, _T_504)
node _T_506 = and(_T_505, can_allocate_16)
node _T_507 = eq(_T_486, UInt<1>(0h0))
node _T_508 = and(_T_506, _T_507)
when _T_508 :
connect issue_slots[8].grant, UInt<1>(0h1)
connect iss_uops[0].valid, UInt<1>(0h1)
connect iss_uops[0].bits, issue_slots[8].iss_uop
node _T_509 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_510 = and(issue_slots[8].request, _T_509)
node _T_511 = and(_T_510, can_allocate_16)
node _T_512 = or(_T_511, _T_486)
node _T_513 = and(issue_slots[8].request, can_allocate_16)
node _T_514 = eq(_T_486, UInt<1>(0h0))
node _T_515 = and(_T_513, _T_514)
node _T_516 = or(_T_515, UInt<1>(0h0))
node _fu_code_match_T_306 = and(issue_slots[8].iss_uop.fu_code[0], io.fu_types[1][0])
node _fu_code_match_T_307 = and(issue_slots[8].iss_uop.fu_code[1], io.fu_types[1][1])
node _fu_code_match_T_308 = and(issue_slots[8].iss_uop.fu_code[2], io.fu_types[1][2])
node _fu_code_match_T_309 = and(issue_slots[8].iss_uop.fu_code[3], io.fu_types[1][3])
node _fu_code_match_T_310 = and(issue_slots[8].iss_uop.fu_code[4], io.fu_types[1][4])
node _fu_code_match_T_311 = and(issue_slots[8].iss_uop.fu_code[5], io.fu_types[1][5])
node _fu_code_match_T_312 = and(issue_slots[8].iss_uop.fu_code[6], io.fu_types[1][6])
node _fu_code_match_T_313 = and(issue_slots[8].iss_uop.fu_code[7], io.fu_types[1][7])
node _fu_code_match_T_314 = and(issue_slots[8].iss_uop.fu_code[8], io.fu_types[1][8])
node _fu_code_match_T_315 = and(issue_slots[8].iss_uop.fu_code[9], io.fu_types[1][9])
node _fu_code_match_T_316 = or(_fu_code_match_T_306, _fu_code_match_T_307)
node _fu_code_match_T_317 = or(_fu_code_match_T_316, _fu_code_match_T_308)
node _fu_code_match_T_318 = or(_fu_code_match_T_317, _fu_code_match_T_309)
node _fu_code_match_T_319 = or(_fu_code_match_T_318, _fu_code_match_T_310)
node _fu_code_match_T_320 = or(_fu_code_match_T_319, _fu_code_match_T_311)
node _fu_code_match_T_321 = or(_fu_code_match_T_320, _fu_code_match_T_312)
node _fu_code_match_T_322 = or(_fu_code_match_T_321, _fu_code_match_T_313)
node _fu_code_match_T_323 = or(_fu_code_match_T_322, _fu_code_match_T_314)
node fu_code_match_17 = or(_fu_code_match_T_323, _fu_code_match_T_315)
node can_allocate_17 = and(fu_code_match_17, UInt<1>(0h1))
node _T_517 = eq(_T_516, UInt<1>(0h0))
node _T_518 = and(issue_slots[8].request, _T_517)
node _T_519 = and(_T_518, can_allocate_17)
node _T_520 = eq(_T_499, UInt<1>(0h0))
node _T_521 = and(_T_519, _T_520)
when _T_521 :
connect issue_slots[8].grant, UInt<1>(0h1)
connect iss_uops[1].valid, UInt<1>(0h1)
connect iss_uops[1].bits, issue_slots[8].iss_uop
node _T_522 = eq(_T_516, UInt<1>(0h0))
node _T_523 = and(issue_slots[8].request, _T_522)
node _T_524 = and(_T_523, can_allocate_17)
node _T_525 = or(_T_524, _T_499)
node _T_526 = and(issue_slots[8].request, can_allocate_17)
node _T_527 = eq(_T_499, UInt<1>(0h0))
node _T_528 = and(_T_526, _T_527)
node _T_529 = or(_T_528, _T_516)
connect issue_slots[9].grant, UInt<1>(0h0)
node _fu_code_match_T_324 = and(issue_slots[9].iss_uop.fu_code[0], io.fu_types[0][0])
node _fu_code_match_T_325 = and(issue_slots[9].iss_uop.fu_code[1], io.fu_types[0][1])
node _fu_code_match_T_326 = and(issue_slots[9].iss_uop.fu_code[2], io.fu_types[0][2])
node _fu_code_match_T_327 = and(issue_slots[9].iss_uop.fu_code[3], io.fu_types[0][3])
node _fu_code_match_T_328 = and(issue_slots[9].iss_uop.fu_code[4], io.fu_types[0][4])
node _fu_code_match_T_329 = and(issue_slots[9].iss_uop.fu_code[5], io.fu_types[0][5])
node _fu_code_match_T_330 = and(issue_slots[9].iss_uop.fu_code[6], io.fu_types[0][6])
node _fu_code_match_T_331 = and(issue_slots[9].iss_uop.fu_code[7], io.fu_types[0][7])
node _fu_code_match_T_332 = and(issue_slots[9].iss_uop.fu_code[8], io.fu_types[0][8])
node _fu_code_match_T_333 = and(issue_slots[9].iss_uop.fu_code[9], io.fu_types[0][9])
node _fu_code_match_T_334 = or(_fu_code_match_T_324, _fu_code_match_T_325)
node _fu_code_match_T_335 = or(_fu_code_match_T_334, _fu_code_match_T_326)
node _fu_code_match_T_336 = or(_fu_code_match_T_335, _fu_code_match_T_327)
node _fu_code_match_T_337 = or(_fu_code_match_T_336, _fu_code_match_T_328)
node _fu_code_match_T_338 = or(_fu_code_match_T_337, _fu_code_match_T_329)
node _fu_code_match_T_339 = or(_fu_code_match_T_338, _fu_code_match_T_330)
node _fu_code_match_T_340 = or(_fu_code_match_T_339, _fu_code_match_T_331)
node _fu_code_match_T_341 = or(_fu_code_match_T_340, _fu_code_match_T_332)
node fu_code_match_18 = or(_fu_code_match_T_341, _fu_code_match_T_333)
node can_allocate_18 = and(fu_code_match_18, UInt<1>(0h1))
node _T_530 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_531 = and(issue_slots[9].request, _T_530)
node _T_532 = and(_T_531, can_allocate_18)
node _T_533 = eq(_T_512, UInt<1>(0h0))
node _T_534 = and(_T_532, _T_533)
when _T_534 :
connect issue_slots[9].grant, UInt<1>(0h1)
connect iss_uops[0].valid, UInt<1>(0h1)
connect iss_uops[0].bits, issue_slots[9].iss_uop
node _T_535 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_536 = and(issue_slots[9].request, _T_535)
node _T_537 = and(_T_536, can_allocate_18)
node _T_538 = or(_T_537, _T_512)
node _T_539 = and(issue_slots[9].request, can_allocate_18)
node _T_540 = eq(_T_512, UInt<1>(0h0))
node _T_541 = and(_T_539, _T_540)
node _T_542 = or(_T_541, UInt<1>(0h0))
node _fu_code_match_T_342 = and(issue_slots[9].iss_uop.fu_code[0], io.fu_types[1][0])
node _fu_code_match_T_343 = and(issue_slots[9].iss_uop.fu_code[1], io.fu_types[1][1])
node _fu_code_match_T_344 = and(issue_slots[9].iss_uop.fu_code[2], io.fu_types[1][2])
node _fu_code_match_T_345 = and(issue_slots[9].iss_uop.fu_code[3], io.fu_types[1][3])
node _fu_code_match_T_346 = and(issue_slots[9].iss_uop.fu_code[4], io.fu_types[1][4])
node _fu_code_match_T_347 = and(issue_slots[9].iss_uop.fu_code[5], io.fu_types[1][5])
node _fu_code_match_T_348 = and(issue_slots[9].iss_uop.fu_code[6], io.fu_types[1][6])
node _fu_code_match_T_349 = and(issue_slots[9].iss_uop.fu_code[7], io.fu_types[1][7])
node _fu_code_match_T_350 = and(issue_slots[9].iss_uop.fu_code[8], io.fu_types[1][8])
node _fu_code_match_T_351 = and(issue_slots[9].iss_uop.fu_code[9], io.fu_types[1][9])
node _fu_code_match_T_352 = or(_fu_code_match_T_342, _fu_code_match_T_343)
node _fu_code_match_T_353 = or(_fu_code_match_T_352, _fu_code_match_T_344)
node _fu_code_match_T_354 = or(_fu_code_match_T_353, _fu_code_match_T_345)
node _fu_code_match_T_355 = or(_fu_code_match_T_354, _fu_code_match_T_346)
node _fu_code_match_T_356 = or(_fu_code_match_T_355, _fu_code_match_T_347)
node _fu_code_match_T_357 = or(_fu_code_match_T_356, _fu_code_match_T_348)
node _fu_code_match_T_358 = or(_fu_code_match_T_357, _fu_code_match_T_349)
node _fu_code_match_T_359 = or(_fu_code_match_T_358, _fu_code_match_T_350)
node fu_code_match_19 = or(_fu_code_match_T_359, _fu_code_match_T_351)
node can_allocate_19 = and(fu_code_match_19, UInt<1>(0h1))
node _T_543 = eq(_T_542, UInt<1>(0h0))
node _T_544 = and(issue_slots[9].request, _T_543)
node _T_545 = and(_T_544, can_allocate_19)
node _T_546 = eq(_T_525, UInt<1>(0h0))
node _T_547 = and(_T_545, _T_546)
when _T_547 :
connect issue_slots[9].grant, UInt<1>(0h1)
connect iss_uops[1].valid, UInt<1>(0h1)
connect iss_uops[1].bits, issue_slots[9].iss_uop
node _T_548 = eq(_T_542, UInt<1>(0h0))
node _T_549 = and(issue_slots[9].request, _T_548)
node _T_550 = and(_T_549, can_allocate_19)
node _T_551 = or(_T_550, _T_525)
node _T_552 = and(issue_slots[9].request, can_allocate_19)
node _T_553 = eq(_T_525, UInt<1>(0h0))
node _T_554 = and(_T_552, _T_553)
node _T_555 = or(_T_554, _T_542)
connect issue_slots[10].grant, UInt<1>(0h0)
node _fu_code_match_T_360 = and(issue_slots[10].iss_uop.fu_code[0], io.fu_types[0][0])
node _fu_code_match_T_361 = and(issue_slots[10].iss_uop.fu_code[1], io.fu_types[0][1])
node _fu_code_match_T_362 = and(issue_slots[10].iss_uop.fu_code[2], io.fu_types[0][2])
node _fu_code_match_T_363 = and(issue_slots[10].iss_uop.fu_code[3], io.fu_types[0][3])
node _fu_code_match_T_364 = and(issue_slots[10].iss_uop.fu_code[4], io.fu_types[0][4])
node _fu_code_match_T_365 = and(issue_slots[10].iss_uop.fu_code[5], io.fu_types[0][5])
node _fu_code_match_T_366 = and(issue_slots[10].iss_uop.fu_code[6], io.fu_types[0][6])
node _fu_code_match_T_367 = and(issue_slots[10].iss_uop.fu_code[7], io.fu_types[0][7])
node _fu_code_match_T_368 = and(issue_slots[10].iss_uop.fu_code[8], io.fu_types[0][8])
node _fu_code_match_T_369 = and(issue_slots[10].iss_uop.fu_code[9], io.fu_types[0][9])
node _fu_code_match_T_370 = or(_fu_code_match_T_360, _fu_code_match_T_361)
node _fu_code_match_T_371 = or(_fu_code_match_T_370, _fu_code_match_T_362)
node _fu_code_match_T_372 = or(_fu_code_match_T_371, _fu_code_match_T_363)
node _fu_code_match_T_373 = or(_fu_code_match_T_372, _fu_code_match_T_364)
node _fu_code_match_T_374 = or(_fu_code_match_T_373, _fu_code_match_T_365)
node _fu_code_match_T_375 = or(_fu_code_match_T_374, _fu_code_match_T_366)
node _fu_code_match_T_376 = or(_fu_code_match_T_375, _fu_code_match_T_367)
node _fu_code_match_T_377 = or(_fu_code_match_T_376, _fu_code_match_T_368)
node fu_code_match_20 = or(_fu_code_match_T_377, _fu_code_match_T_369)
node can_allocate_20 = and(fu_code_match_20, UInt<1>(0h1))
node _T_556 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_557 = and(issue_slots[10].request, _T_556)
node _T_558 = and(_T_557, can_allocate_20)
node _T_559 = eq(_T_538, UInt<1>(0h0))
node _T_560 = and(_T_558, _T_559)
when _T_560 :
connect issue_slots[10].grant, UInt<1>(0h1)
connect iss_uops[0].valid, UInt<1>(0h1)
connect iss_uops[0].bits, issue_slots[10].iss_uop
node _T_561 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_562 = and(issue_slots[10].request, _T_561)
node _T_563 = and(_T_562, can_allocate_20)
node _T_564 = or(_T_563, _T_538)
node _T_565 = and(issue_slots[10].request, can_allocate_20)
node _T_566 = eq(_T_538, UInt<1>(0h0))
node _T_567 = and(_T_565, _T_566)
node _T_568 = or(_T_567, UInt<1>(0h0))
node _fu_code_match_T_378 = and(issue_slots[10].iss_uop.fu_code[0], io.fu_types[1][0])
node _fu_code_match_T_379 = and(issue_slots[10].iss_uop.fu_code[1], io.fu_types[1][1])
node _fu_code_match_T_380 = and(issue_slots[10].iss_uop.fu_code[2], io.fu_types[1][2])
node _fu_code_match_T_381 = and(issue_slots[10].iss_uop.fu_code[3], io.fu_types[1][3])
node _fu_code_match_T_382 = and(issue_slots[10].iss_uop.fu_code[4], io.fu_types[1][4])
node _fu_code_match_T_383 = and(issue_slots[10].iss_uop.fu_code[5], io.fu_types[1][5])
node _fu_code_match_T_384 = and(issue_slots[10].iss_uop.fu_code[6], io.fu_types[1][6])
node _fu_code_match_T_385 = and(issue_slots[10].iss_uop.fu_code[7], io.fu_types[1][7])
node _fu_code_match_T_386 = and(issue_slots[10].iss_uop.fu_code[8], io.fu_types[1][8])
node _fu_code_match_T_387 = and(issue_slots[10].iss_uop.fu_code[9], io.fu_types[1][9])
node _fu_code_match_T_388 = or(_fu_code_match_T_378, _fu_code_match_T_379)
node _fu_code_match_T_389 = or(_fu_code_match_T_388, _fu_code_match_T_380)
node _fu_code_match_T_390 = or(_fu_code_match_T_389, _fu_code_match_T_381)
node _fu_code_match_T_391 = or(_fu_code_match_T_390, _fu_code_match_T_382)
node _fu_code_match_T_392 = or(_fu_code_match_T_391, _fu_code_match_T_383)
node _fu_code_match_T_393 = or(_fu_code_match_T_392, _fu_code_match_T_384)
node _fu_code_match_T_394 = or(_fu_code_match_T_393, _fu_code_match_T_385)
node _fu_code_match_T_395 = or(_fu_code_match_T_394, _fu_code_match_T_386)
node fu_code_match_21 = or(_fu_code_match_T_395, _fu_code_match_T_387)
node can_allocate_21 = and(fu_code_match_21, UInt<1>(0h1))
node _T_569 = eq(_T_568, UInt<1>(0h0))
node _T_570 = and(issue_slots[10].request, _T_569)
node _T_571 = and(_T_570, can_allocate_21)
node _T_572 = eq(_T_551, UInt<1>(0h0))
node _T_573 = and(_T_571, _T_572)
when _T_573 :
connect issue_slots[10].grant, UInt<1>(0h1)
connect iss_uops[1].valid, UInt<1>(0h1)
connect iss_uops[1].bits, issue_slots[10].iss_uop
node _T_574 = eq(_T_568, UInt<1>(0h0))
node _T_575 = and(issue_slots[10].request, _T_574)
node _T_576 = and(_T_575, can_allocate_21)
node _T_577 = or(_T_576, _T_551)
node _T_578 = and(issue_slots[10].request, can_allocate_21)
node _T_579 = eq(_T_551, UInt<1>(0h0))
node _T_580 = and(_T_578, _T_579)
node _T_581 = or(_T_580, _T_568)
connect issue_slots[11].grant, UInt<1>(0h0)
node _fu_code_match_T_396 = and(issue_slots[11].iss_uop.fu_code[0], io.fu_types[0][0])
node _fu_code_match_T_397 = and(issue_slots[11].iss_uop.fu_code[1], io.fu_types[0][1])
node _fu_code_match_T_398 = and(issue_slots[11].iss_uop.fu_code[2], io.fu_types[0][2])
node _fu_code_match_T_399 = and(issue_slots[11].iss_uop.fu_code[3], io.fu_types[0][3])
node _fu_code_match_T_400 = and(issue_slots[11].iss_uop.fu_code[4], io.fu_types[0][4])
node _fu_code_match_T_401 = and(issue_slots[11].iss_uop.fu_code[5], io.fu_types[0][5])
node _fu_code_match_T_402 = and(issue_slots[11].iss_uop.fu_code[6], io.fu_types[0][6])
node _fu_code_match_T_403 = and(issue_slots[11].iss_uop.fu_code[7], io.fu_types[0][7])
node _fu_code_match_T_404 = and(issue_slots[11].iss_uop.fu_code[8], io.fu_types[0][8])
node _fu_code_match_T_405 = and(issue_slots[11].iss_uop.fu_code[9], io.fu_types[0][9])
node _fu_code_match_T_406 = or(_fu_code_match_T_396, _fu_code_match_T_397)
node _fu_code_match_T_407 = or(_fu_code_match_T_406, _fu_code_match_T_398)
node _fu_code_match_T_408 = or(_fu_code_match_T_407, _fu_code_match_T_399)
node _fu_code_match_T_409 = or(_fu_code_match_T_408, _fu_code_match_T_400)
node _fu_code_match_T_410 = or(_fu_code_match_T_409, _fu_code_match_T_401)
node _fu_code_match_T_411 = or(_fu_code_match_T_410, _fu_code_match_T_402)
node _fu_code_match_T_412 = or(_fu_code_match_T_411, _fu_code_match_T_403)
node _fu_code_match_T_413 = or(_fu_code_match_T_412, _fu_code_match_T_404)
node fu_code_match_22 = or(_fu_code_match_T_413, _fu_code_match_T_405)
node can_allocate_22 = and(fu_code_match_22, UInt<1>(0h1))
node _T_582 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_583 = and(issue_slots[11].request, _T_582)
node _T_584 = and(_T_583, can_allocate_22)
node _T_585 = eq(_T_564, UInt<1>(0h0))
node _T_586 = and(_T_584, _T_585)
when _T_586 :
connect issue_slots[11].grant, UInt<1>(0h1)
connect iss_uops[0].valid, UInt<1>(0h1)
connect iss_uops[0].bits, issue_slots[11].iss_uop
node _T_587 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_588 = and(issue_slots[11].request, _T_587)
node _T_589 = and(_T_588, can_allocate_22)
node _T_590 = or(_T_589, _T_564)
node _T_591 = and(issue_slots[11].request, can_allocate_22)
node _T_592 = eq(_T_564, UInt<1>(0h0))
node _T_593 = and(_T_591, _T_592)
node _T_594 = or(_T_593, UInt<1>(0h0))
node _fu_code_match_T_414 = and(issue_slots[11].iss_uop.fu_code[0], io.fu_types[1][0])
node _fu_code_match_T_415 = and(issue_slots[11].iss_uop.fu_code[1], io.fu_types[1][1])
node _fu_code_match_T_416 = and(issue_slots[11].iss_uop.fu_code[2], io.fu_types[1][2])
node _fu_code_match_T_417 = and(issue_slots[11].iss_uop.fu_code[3], io.fu_types[1][3])
node _fu_code_match_T_418 = and(issue_slots[11].iss_uop.fu_code[4], io.fu_types[1][4])
node _fu_code_match_T_419 = and(issue_slots[11].iss_uop.fu_code[5], io.fu_types[1][5])
node _fu_code_match_T_420 = and(issue_slots[11].iss_uop.fu_code[6], io.fu_types[1][6])
node _fu_code_match_T_421 = and(issue_slots[11].iss_uop.fu_code[7], io.fu_types[1][7])
node _fu_code_match_T_422 = and(issue_slots[11].iss_uop.fu_code[8], io.fu_types[1][8])
node _fu_code_match_T_423 = and(issue_slots[11].iss_uop.fu_code[9], io.fu_types[1][9])
node _fu_code_match_T_424 = or(_fu_code_match_T_414, _fu_code_match_T_415)
node _fu_code_match_T_425 = or(_fu_code_match_T_424, _fu_code_match_T_416)
node _fu_code_match_T_426 = or(_fu_code_match_T_425, _fu_code_match_T_417)
node _fu_code_match_T_427 = or(_fu_code_match_T_426, _fu_code_match_T_418)
node _fu_code_match_T_428 = or(_fu_code_match_T_427, _fu_code_match_T_419)
node _fu_code_match_T_429 = or(_fu_code_match_T_428, _fu_code_match_T_420)
node _fu_code_match_T_430 = or(_fu_code_match_T_429, _fu_code_match_T_421)
node _fu_code_match_T_431 = or(_fu_code_match_T_430, _fu_code_match_T_422)
node fu_code_match_23 = or(_fu_code_match_T_431, _fu_code_match_T_423)
node can_allocate_23 = and(fu_code_match_23, UInt<1>(0h1))
node _T_595 = eq(_T_594, UInt<1>(0h0))
node _T_596 = and(issue_slots[11].request, _T_595)
node _T_597 = and(_T_596, can_allocate_23)
node _T_598 = eq(_T_577, UInt<1>(0h0))
node _T_599 = and(_T_597, _T_598)
when _T_599 :
connect issue_slots[11].grant, UInt<1>(0h1)
connect iss_uops[1].valid, UInt<1>(0h1)
connect iss_uops[1].bits, issue_slots[11].iss_uop
node _T_600 = eq(_T_594, UInt<1>(0h0))
node _T_601 = and(issue_slots[11].request, _T_600)
node _T_602 = and(_T_601, can_allocate_23)
node _T_603 = or(_T_602, _T_577)
node _T_604 = and(issue_slots[11].request, can_allocate_23)
node _T_605 = eq(_T_577, UInt<1>(0h0))
node _T_606 = and(_T_604, _T_605)
node _T_607 = or(_T_606, _T_594)
connect issue_slots[12].grant, UInt<1>(0h0)
node _fu_code_match_T_432 = and(issue_slots[12].iss_uop.fu_code[0], io.fu_types[0][0])
node _fu_code_match_T_433 = and(issue_slots[12].iss_uop.fu_code[1], io.fu_types[0][1])
node _fu_code_match_T_434 = and(issue_slots[12].iss_uop.fu_code[2], io.fu_types[0][2])
node _fu_code_match_T_435 = and(issue_slots[12].iss_uop.fu_code[3], io.fu_types[0][3])
node _fu_code_match_T_436 = and(issue_slots[12].iss_uop.fu_code[4], io.fu_types[0][4])
node _fu_code_match_T_437 = and(issue_slots[12].iss_uop.fu_code[5], io.fu_types[0][5])
node _fu_code_match_T_438 = and(issue_slots[12].iss_uop.fu_code[6], io.fu_types[0][6])
node _fu_code_match_T_439 = and(issue_slots[12].iss_uop.fu_code[7], io.fu_types[0][7])
node _fu_code_match_T_440 = and(issue_slots[12].iss_uop.fu_code[8], io.fu_types[0][8])
node _fu_code_match_T_441 = and(issue_slots[12].iss_uop.fu_code[9], io.fu_types[0][9])
node _fu_code_match_T_442 = or(_fu_code_match_T_432, _fu_code_match_T_433)
node _fu_code_match_T_443 = or(_fu_code_match_T_442, _fu_code_match_T_434)
node _fu_code_match_T_444 = or(_fu_code_match_T_443, _fu_code_match_T_435)
node _fu_code_match_T_445 = or(_fu_code_match_T_444, _fu_code_match_T_436)
node _fu_code_match_T_446 = or(_fu_code_match_T_445, _fu_code_match_T_437)
node _fu_code_match_T_447 = or(_fu_code_match_T_446, _fu_code_match_T_438)
node _fu_code_match_T_448 = or(_fu_code_match_T_447, _fu_code_match_T_439)
node _fu_code_match_T_449 = or(_fu_code_match_T_448, _fu_code_match_T_440)
node fu_code_match_24 = or(_fu_code_match_T_449, _fu_code_match_T_441)
node can_allocate_24 = and(fu_code_match_24, UInt<1>(0h1))
node _T_608 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_609 = and(issue_slots[12].request, _T_608)
node _T_610 = and(_T_609, can_allocate_24)
node _T_611 = eq(_T_590, UInt<1>(0h0))
node _T_612 = and(_T_610, _T_611)
when _T_612 :
connect issue_slots[12].grant, UInt<1>(0h1)
connect iss_uops[0].valid, UInt<1>(0h1)
connect iss_uops[0].bits, issue_slots[12].iss_uop
node _T_613 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_614 = and(issue_slots[12].request, _T_613)
node _T_615 = and(_T_614, can_allocate_24)
node _T_616 = or(_T_615, _T_590)
node _T_617 = and(issue_slots[12].request, can_allocate_24)
node _T_618 = eq(_T_590, UInt<1>(0h0))
node _T_619 = and(_T_617, _T_618)
node _T_620 = or(_T_619, UInt<1>(0h0))
node _fu_code_match_T_450 = and(issue_slots[12].iss_uop.fu_code[0], io.fu_types[1][0])
node _fu_code_match_T_451 = and(issue_slots[12].iss_uop.fu_code[1], io.fu_types[1][1])
node _fu_code_match_T_452 = and(issue_slots[12].iss_uop.fu_code[2], io.fu_types[1][2])
node _fu_code_match_T_453 = and(issue_slots[12].iss_uop.fu_code[3], io.fu_types[1][3])
node _fu_code_match_T_454 = and(issue_slots[12].iss_uop.fu_code[4], io.fu_types[1][4])
node _fu_code_match_T_455 = and(issue_slots[12].iss_uop.fu_code[5], io.fu_types[1][5])
node _fu_code_match_T_456 = and(issue_slots[12].iss_uop.fu_code[6], io.fu_types[1][6])
node _fu_code_match_T_457 = and(issue_slots[12].iss_uop.fu_code[7], io.fu_types[1][7])
node _fu_code_match_T_458 = and(issue_slots[12].iss_uop.fu_code[8], io.fu_types[1][8])
node _fu_code_match_T_459 = and(issue_slots[12].iss_uop.fu_code[9], io.fu_types[1][9])
node _fu_code_match_T_460 = or(_fu_code_match_T_450, _fu_code_match_T_451)
node _fu_code_match_T_461 = or(_fu_code_match_T_460, _fu_code_match_T_452)
node _fu_code_match_T_462 = or(_fu_code_match_T_461, _fu_code_match_T_453)
node _fu_code_match_T_463 = or(_fu_code_match_T_462, _fu_code_match_T_454)
node _fu_code_match_T_464 = or(_fu_code_match_T_463, _fu_code_match_T_455)
node _fu_code_match_T_465 = or(_fu_code_match_T_464, _fu_code_match_T_456)
node _fu_code_match_T_466 = or(_fu_code_match_T_465, _fu_code_match_T_457)
node _fu_code_match_T_467 = or(_fu_code_match_T_466, _fu_code_match_T_458)
node fu_code_match_25 = or(_fu_code_match_T_467, _fu_code_match_T_459)
node can_allocate_25 = and(fu_code_match_25, UInt<1>(0h1))
node _T_621 = eq(_T_620, UInt<1>(0h0))
node _T_622 = and(issue_slots[12].request, _T_621)
node _T_623 = and(_T_622, can_allocate_25)
node _T_624 = eq(_T_603, UInt<1>(0h0))
node _T_625 = and(_T_623, _T_624)
when _T_625 :
connect issue_slots[12].grant, UInt<1>(0h1)
connect iss_uops[1].valid, UInt<1>(0h1)
connect iss_uops[1].bits, issue_slots[12].iss_uop
node _T_626 = eq(_T_620, UInt<1>(0h0))
node _T_627 = and(issue_slots[12].request, _T_626)
node _T_628 = and(_T_627, can_allocate_25)
node _T_629 = or(_T_628, _T_603)
node _T_630 = and(issue_slots[12].request, can_allocate_25)
node _T_631 = eq(_T_603, UInt<1>(0h0))
node _T_632 = and(_T_630, _T_631)
node _T_633 = or(_T_632, _T_620)
connect issue_slots[13].grant, UInt<1>(0h0)
node _fu_code_match_T_468 = and(issue_slots[13].iss_uop.fu_code[0], io.fu_types[0][0])
node _fu_code_match_T_469 = and(issue_slots[13].iss_uop.fu_code[1], io.fu_types[0][1])
node _fu_code_match_T_470 = and(issue_slots[13].iss_uop.fu_code[2], io.fu_types[0][2])
node _fu_code_match_T_471 = and(issue_slots[13].iss_uop.fu_code[3], io.fu_types[0][3])
node _fu_code_match_T_472 = and(issue_slots[13].iss_uop.fu_code[4], io.fu_types[0][4])
node _fu_code_match_T_473 = and(issue_slots[13].iss_uop.fu_code[5], io.fu_types[0][5])
node _fu_code_match_T_474 = and(issue_slots[13].iss_uop.fu_code[6], io.fu_types[0][6])
node _fu_code_match_T_475 = and(issue_slots[13].iss_uop.fu_code[7], io.fu_types[0][7])
node _fu_code_match_T_476 = and(issue_slots[13].iss_uop.fu_code[8], io.fu_types[0][8])
node _fu_code_match_T_477 = and(issue_slots[13].iss_uop.fu_code[9], io.fu_types[0][9])
node _fu_code_match_T_478 = or(_fu_code_match_T_468, _fu_code_match_T_469)
node _fu_code_match_T_479 = or(_fu_code_match_T_478, _fu_code_match_T_470)
node _fu_code_match_T_480 = or(_fu_code_match_T_479, _fu_code_match_T_471)
node _fu_code_match_T_481 = or(_fu_code_match_T_480, _fu_code_match_T_472)
node _fu_code_match_T_482 = or(_fu_code_match_T_481, _fu_code_match_T_473)
node _fu_code_match_T_483 = or(_fu_code_match_T_482, _fu_code_match_T_474)
node _fu_code_match_T_484 = or(_fu_code_match_T_483, _fu_code_match_T_475)
node _fu_code_match_T_485 = or(_fu_code_match_T_484, _fu_code_match_T_476)
node fu_code_match_26 = or(_fu_code_match_T_485, _fu_code_match_T_477)
node can_allocate_26 = and(fu_code_match_26, UInt<1>(0h1))
node _T_634 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_635 = and(issue_slots[13].request, _T_634)
node _T_636 = and(_T_635, can_allocate_26)
node _T_637 = eq(_T_616, UInt<1>(0h0))
node _T_638 = and(_T_636, _T_637)
when _T_638 :
connect issue_slots[13].grant, UInt<1>(0h1)
connect iss_uops[0].valid, UInt<1>(0h1)
connect iss_uops[0].bits, issue_slots[13].iss_uop
node _T_639 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_640 = and(issue_slots[13].request, _T_639)
node _T_641 = and(_T_640, can_allocate_26)
node _T_642 = or(_T_641, _T_616)
node _T_643 = and(issue_slots[13].request, can_allocate_26)
node _T_644 = eq(_T_616, UInt<1>(0h0))
node _T_645 = and(_T_643, _T_644)
node _T_646 = or(_T_645, UInt<1>(0h0))
node _fu_code_match_T_486 = and(issue_slots[13].iss_uop.fu_code[0], io.fu_types[1][0])
node _fu_code_match_T_487 = and(issue_slots[13].iss_uop.fu_code[1], io.fu_types[1][1])
node _fu_code_match_T_488 = and(issue_slots[13].iss_uop.fu_code[2], io.fu_types[1][2])
node _fu_code_match_T_489 = and(issue_slots[13].iss_uop.fu_code[3], io.fu_types[1][3])
node _fu_code_match_T_490 = and(issue_slots[13].iss_uop.fu_code[4], io.fu_types[1][4])
node _fu_code_match_T_491 = and(issue_slots[13].iss_uop.fu_code[5], io.fu_types[1][5])
node _fu_code_match_T_492 = and(issue_slots[13].iss_uop.fu_code[6], io.fu_types[1][6])
node _fu_code_match_T_493 = and(issue_slots[13].iss_uop.fu_code[7], io.fu_types[1][7])
node _fu_code_match_T_494 = and(issue_slots[13].iss_uop.fu_code[8], io.fu_types[1][8])
node _fu_code_match_T_495 = and(issue_slots[13].iss_uop.fu_code[9], io.fu_types[1][9])
node _fu_code_match_T_496 = or(_fu_code_match_T_486, _fu_code_match_T_487)
node _fu_code_match_T_497 = or(_fu_code_match_T_496, _fu_code_match_T_488)
node _fu_code_match_T_498 = or(_fu_code_match_T_497, _fu_code_match_T_489)
node _fu_code_match_T_499 = or(_fu_code_match_T_498, _fu_code_match_T_490)
node _fu_code_match_T_500 = or(_fu_code_match_T_499, _fu_code_match_T_491)
node _fu_code_match_T_501 = or(_fu_code_match_T_500, _fu_code_match_T_492)
node _fu_code_match_T_502 = or(_fu_code_match_T_501, _fu_code_match_T_493)
node _fu_code_match_T_503 = or(_fu_code_match_T_502, _fu_code_match_T_494)
node fu_code_match_27 = or(_fu_code_match_T_503, _fu_code_match_T_495)
node can_allocate_27 = and(fu_code_match_27, UInt<1>(0h1))
node _T_647 = eq(_T_646, UInt<1>(0h0))
node _T_648 = and(issue_slots[13].request, _T_647)
node _T_649 = and(_T_648, can_allocate_27)
node _T_650 = eq(_T_629, UInt<1>(0h0))
node _T_651 = and(_T_649, _T_650)
when _T_651 :
connect issue_slots[13].grant, UInt<1>(0h1)
connect iss_uops[1].valid, UInt<1>(0h1)
connect iss_uops[1].bits, issue_slots[13].iss_uop
node _T_652 = eq(_T_646, UInt<1>(0h0))
node _T_653 = and(issue_slots[13].request, _T_652)
node _T_654 = and(_T_653, can_allocate_27)
node _T_655 = or(_T_654, _T_629)
node _T_656 = and(issue_slots[13].request, can_allocate_27)
node _T_657 = eq(_T_629, UInt<1>(0h0))
node _T_658 = and(_T_656, _T_657)
node _T_659 = or(_T_658, _T_646)
connect issue_slots[14].grant, UInt<1>(0h0)
node _fu_code_match_T_504 = and(issue_slots[14].iss_uop.fu_code[0], io.fu_types[0][0])
node _fu_code_match_T_505 = and(issue_slots[14].iss_uop.fu_code[1], io.fu_types[0][1])
node _fu_code_match_T_506 = and(issue_slots[14].iss_uop.fu_code[2], io.fu_types[0][2])
node _fu_code_match_T_507 = and(issue_slots[14].iss_uop.fu_code[3], io.fu_types[0][3])
node _fu_code_match_T_508 = and(issue_slots[14].iss_uop.fu_code[4], io.fu_types[0][4])
node _fu_code_match_T_509 = and(issue_slots[14].iss_uop.fu_code[5], io.fu_types[0][5])
node _fu_code_match_T_510 = and(issue_slots[14].iss_uop.fu_code[6], io.fu_types[0][6])
node _fu_code_match_T_511 = and(issue_slots[14].iss_uop.fu_code[7], io.fu_types[0][7])
node _fu_code_match_T_512 = and(issue_slots[14].iss_uop.fu_code[8], io.fu_types[0][8])
node _fu_code_match_T_513 = and(issue_slots[14].iss_uop.fu_code[9], io.fu_types[0][9])
node _fu_code_match_T_514 = or(_fu_code_match_T_504, _fu_code_match_T_505)
node _fu_code_match_T_515 = or(_fu_code_match_T_514, _fu_code_match_T_506)
node _fu_code_match_T_516 = or(_fu_code_match_T_515, _fu_code_match_T_507)
node _fu_code_match_T_517 = or(_fu_code_match_T_516, _fu_code_match_T_508)
node _fu_code_match_T_518 = or(_fu_code_match_T_517, _fu_code_match_T_509)
node _fu_code_match_T_519 = or(_fu_code_match_T_518, _fu_code_match_T_510)
node _fu_code_match_T_520 = or(_fu_code_match_T_519, _fu_code_match_T_511)
node _fu_code_match_T_521 = or(_fu_code_match_T_520, _fu_code_match_T_512)
node fu_code_match_28 = or(_fu_code_match_T_521, _fu_code_match_T_513)
node can_allocate_28 = and(fu_code_match_28, UInt<1>(0h1))
node _T_660 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_661 = and(issue_slots[14].request, _T_660)
node _T_662 = and(_T_661, can_allocate_28)
node _T_663 = eq(_T_642, UInt<1>(0h0))
node _T_664 = and(_T_662, _T_663)
when _T_664 :
connect issue_slots[14].grant, UInt<1>(0h1)
connect iss_uops[0].valid, UInt<1>(0h1)
connect iss_uops[0].bits, issue_slots[14].iss_uop
node _T_665 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_666 = and(issue_slots[14].request, _T_665)
node _T_667 = and(_T_666, can_allocate_28)
node _T_668 = or(_T_667, _T_642)
node _T_669 = and(issue_slots[14].request, can_allocate_28)
node _T_670 = eq(_T_642, UInt<1>(0h0))
node _T_671 = and(_T_669, _T_670)
node _T_672 = or(_T_671, UInt<1>(0h0))
node _fu_code_match_T_522 = and(issue_slots[14].iss_uop.fu_code[0], io.fu_types[1][0])
node _fu_code_match_T_523 = and(issue_slots[14].iss_uop.fu_code[1], io.fu_types[1][1])
node _fu_code_match_T_524 = and(issue_slots[14].iss_uop.fu_code[2], io.fu_types[1][2])
node _fu_code_match_T_525 = and(issue_slots[14].iss_uop.fu_code[3], io.fu_types[1][3])
node _fu_code_match_T_526 = and(issue_slots[14].iss_uop.fu_code[4], io.fu_types[1][4])
node _fu_code_match_T_527 = and(issue_slots[14].iss_uop.fu_code[5], io.fu_types[1][5])
node _fu_code_match_T_528 = and(issue_slots[14].iss_uop.fu_code[6], io.fu_types[1][6])
node _fu_code_match_T_529 = and(issue_slots[14].iss_uop.fu_code[7], io.fu_types[1][7])
node _fu_code_match_T_530 = and(issue_slots[14].iss_uop.fu_code[8], io.fu_types[1][8])
node _fu_code_match_T_531 = and(issue_slots[14].iss_uop.fu_code[9], io.fu_types[1][9])
node _fu_code_match_T_532 = or(_fu_code_match_T_522, _fu_code_match_T_523)
node _fu_code_match_T_533 = or(_fu_code_match_T_532, _fu_code_match_T_524)
node _fu_code_match_T_534 = or(_fu_code_match_T_533, _fu_code_match_T_525)
node _fu_code_match_T_535 = or(_fu_code_match_T_534, _fu_code_match_T_526)
node _fu_code_match_T_536 = or(_fu_code_match_T_535, _fu_code_match_T_527)
node _fu_code_match_T_537 = or(_fu_code_match_T_536, _fu_code_match_T_528)
node _fu_code_match_T_538 = or(_fu_code_match_T_537, _fu_code_match_T_529)
node _fu_code_match_T_539 = or(_fu_code_match_T_538, _fu_code_match_T_530)
node fu_code_match_29 = or(_fu_code_match_T_539, _fu_code_match_T_531)
node can_allocate_29 = and(fu_code_match_29, UInt<1>(0h1))
node _T_673 = eq(_T_672, UInt<1>(0h0))
node _T_674 = and(issue_slots[14].request, _T_673)
node _T_675 = and(_T_674, can_allocate_29)
node _T_676 = eq(_T_655, UInt<1>(0h0))
node _T_677 = and(_T_675, _T_676)
when _T_677 :
connect issue_slots[14].grant, UInt<1>(0h1)
connect iss_uops[1].valid, UInt<1>(0h1)
connect iss_uops[1].bits, issue_slots[14].iss_uop
node _T_678 = eq(_T_672, UInt<1>(0h0))
node _T_679 = and(issue_slots[14].request, _T_678)
node _T_680 = and(_T_679, can_allocate_29)
node _T_681 = or(_T_680, _T_655)
node _T_682 = and(issue_slots[14].request, can_allocate_29)
node _T_683 = eq(_T_655, UInt<1>(0h0))
node _T_684 = and(_T_682, _T_683)
node _T_685 = or(_T_684, _T_672)
connect issue_slots[15].grant, UInt<1>(0h0)
node _fu_code_match_T_540 = and(issue_slots[15].iss_uop.fu_code[0], io.fu_types[0][0])
node _fu_code_match_T_541 = and(issue_slots[15].iss_uop.fu_code[1], io.fu_types[0][1])
node _fu_code_match_T_542 = and(issue_slots[15].iss_uop.fu_code[2], io.fu_types[0][2])
node _fu_code_match_T_543 = and(issue_slots[15].iss_uop.fu_code[3], io.fu_types[0][3])
node _fu_code_match_T_544 = and(issue_slots[15].iss_uop.fu_code[4], io.fu_types[0][4])
node _fu_code_match_T_545 = and(issue_slots[15].iss_uop.fu_code[5], io.fu_types[0][5])
node _fu_code_match_T_546 = and(issue_slots[15].iss_uop.fu_code[6], io.fu_types[0][6])
node _fu_code_match_T_547 = and(issue_slots[15].iss_uop.fu_code[7], io.fu_types[0][7])
node _fu_code_match_T_548 = and(issue_slots[15].iss_uop.fu_code[8], io.fu_types[0][8])
node _fu_code_match_T_549 = and(issue_slots[15].iss_uop.fu_code[9], io.fu_types[0][9])
node _fu_code_match_T_550 = or(_fu_code_match_T_540, _fu_code_match_T_541)
node _fu_code_match_T_551 = or(_fu_code_match_T_550, _fu_code_match_T_542)
node _fu_code_match_T_552 = or(_fu_code_match_T_551, _fu_code_match_T_543)
node _fu_code_match_T_553 = or(_fu_code_match_T_552, _fu_code_match_T_544)
node _fu_code_match_T_554 = or(_fu_code_match_T_553, _fu_code_match_T_545)
node _fu_code_match_T_555 = or(_fu_code_match_T_554, _fu_code_match_T_546)
node _fu_code_match_T_556 = or(_fu_code_match_T_555, _fu_code_match_T_547)
node _fu_code_match_T_557 = or(_fu_code_match_T_556, _fu_code_match_T_548)
node fu_code_match_30 = or(_fu_code_match_T_557, _fu_code_match_T_549)
node can_allocate_30 = and(fu_code_match_30, UInt<1>(0h1))
node _T_686 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_687 = and(issue_slots[15].request, _T_686)
node _T_688 = and(_T_687, can_allocate_30)
node _T_689 = eq(_T_668, UInt<1>(0h0))
node _T_690 = and(_T_688, _T_689)
when _T_690 :
connect issue_slots[15].grant, UInt<1>(0h1)
connect iss_uops[0].valid, UInt<1>(0h1)
connect iss_uops[0].bits, issue_slots[15].iss_uop
node _T_691 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_692 = and(issue_slots[15].request, _T_691)
node _T_693 = and(_T_692, can_allocate_30)
node _T_694 = or(_T_693, _T_668)
node _T_695 = and(issue_slots[15].request, can_allocate_30)
node _T_696 = eq(_T_668, UInt<1>(0h0))
node _T_697 = and(_T_695, _T_696)
node _T_698 = or(_T_697, UInt<1>(0h0))
node _fu_code_match_T_558 = and(issue_slots[15].iss_uop.fu_code[0], io.fu_types[1][0])
node _fu_code_match_T_559 = and(issue_slots[15].iss_uop.fu_code[1], io.fu_types[1][1])
node _fu_code_match_T_560 = and(issue_slots[15].iss_uop.fu_code[2], io.fu_types[1][2])
node _fu_code_match_T_561 = and(issue_slots[15].iss_uop.fu_code[3], io.fu_types[1][3])
node _fu_code_match_T_562 = and(issue_slots[15].iss_uop.fu_code[4], io.fu_types[1][4])
node _fu_code_match_T_563 = and(issue_slots[15].iss_uop.fu_code[5], io.fu_types[1][5])
node _fu_code_match_T_564 = and(issue_slots[15].iss_uop.fu_code[6], io.fu_types[1][6])
node _fu_code_match_T_565 = and(issue_slots[15].iss_uop.fu_code[7], io.fu_types[1][7])
node _fu_code_match_T_566 = and(issue_slots[15].iss_uop.fu_code[8], io.fu_types[1][8])
node _fu_code_match_T_567 = and(issue_slots[15].iss_uop.fu_code[9], io.fu_types[1][9])
node _fu_code_match_T_568 = or(_fu_code_match_T_558, _fu_code_match_T_559)
node _fu_code_match_T_569 = or(_fu_code_match_T_568, _fu_code_match_T_560)
node _fu_code_match_T_570 = or(_fu_code_match_T_569, _fu_code_match_T_561)
node _fu_code_match_T_571 = or(_fu_code_match_T_570, _fu_code_match_T_562)
node _fu_code_match_T_572 = or(_fu_code_match_T_571, _fu_code_match_T_563)
node _fu_code_match_T_573 = or(_fu_code_match_T_572, _fu_code_match_T_564)
node _fu_code_match_T_574 = or(_fu_code_match_T_573, _fu_code_match_T_565)
node _fu_code_match_T_575 = or(_fu_code_match_T_574, _fu_code_match_T_566)
node fu_code_match_31 = or(_fu_code_match_T_575, _fu_code_match_T_567)
node can_allocate_31 = and(fu_code_match_31, UInt<1>(0h1))
node _T_699 = eq(_T_698, UInt<1>(0h0))
node _T_700 = and(issue_slots[15].request, _T_699)
node _T_701 = and(_T_700, can_allocate_31)
node _T_702 = eq(_T_681, UInt<1>(0h0))
node _T_703 = and(_T_701, _T_702)
when _T_703 :
connect issue_slots[15].grant, UInt<1>(0h1)
connect iss_uops[1].valid, UInt<1>(0h1)
connect iss_uops[1].bits, issue_slots[15].iss_uop
node _T_704 = eq(_T_698, UInt<1>(0h0))
node _T_705 = and(issue_slots[15].request, _T_704)
node _T_706 = and(_T_705, can_allocate_31)
node _T_707 = or(_T_706, _T_681)
node _T_708 = and(issue_slots[15].request, can_allocate_31)
node _T_709 = eq(_T_681, UInt<1>(0h0))
node _T_710 = and(_T_708, _T_709)
node _T_711 = or(_T_710, _T_698)
connect issue_slots[16].grant, UInt<1>(0h0)
node _fu_code_match_T_576 = and(issue_slots[16].iss_uop.fu_code[0], io.fu_types[0][0])
node _fu_code_match_T_577 = and(issue_slots[16].iss_uop.fu_code[1], io.fu_types[0][1])
node _fu_code_match_T_578 = and(issue_slots[16].iss_uop.fu_code[2], io.fu_types[0][2])
node _fu_code_match_T_579 = and(issue_slots[16].iss_uop.fu_code[3], io.fu_types[0][3])
node _fu_code_match_T_580 = and(issue_slots[16].iss_uop.fu_code[4], io.fu_types[0][4])
node _fu_code_match_T_581 = and(issue_slots[16].iss_uop.fu_code[5], io.fu_types[0][5])
node _fu_code_match_T_582 = and(issue_slots[16].iss_uop.fu_code[6], io.fu_types[0][6])
node _fu_code_match_T_583 = and(issue_slots[16].iss_uop.fu_code[7], io.fu_types[0][7])
node _fu_code_match_T_584 = and(issue_slots[16].iss_uop.fu_code[8], io.fu_types[0][8])
node _fu_code_match_T_585 = and(issue_slots[16].iss_uop.fu_code[9], io.fu_types[0][9])
node _fu_code_match_T_586 = or(_fu_code_match_T_576, _fu_code_match_T_577)
node _fu_code_match_T_587 = or(_fu_code_match_T_586, _fu_code_match_T_578)
node _fu_code_match_T_588 = or(_fu_code_match_T_587, _fu_code_match_T_579)
node _fu_code_match_T_589 = or(_fu_code_match_T_588, _fu_code_match_T_580)
node _fu_code_match_T_590 = or(_fu_code_match_T_589, _fu_code_match_T_581)
node _fu_code_match_T_591 = or(_fu_code_match_T_590, _fu_code_match_T_582)
node _fu_code_match_T_592 = or(_fu_code_match_T_591, _fu_code_match_T_583)
node _fu_code_match_T_593 = or(_fu_code_match_T_592, _fu_code_match_T_584)
node fu_code_match_32 = or(_fu_code_match_T_593, _fu_code_match_T_585)
node can_allocate_32 = and(fu_code_match_32, UInt<1>(0h1))
node _T_712 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_713 = and(issue_slots[16].request, _T_712)
node _T_714 = and(_T_713, can_allocate_32)
node _T_715 = eq(_T_694, UInt<1>(0h0))
node _T_716 = and(_T_714, _T_715)
when _T_716 :
connect issue_slots[16].grant, UInt<1>(0h1)
connect iss_uops[0].valid, UInt<1>(0h1)
connect iss_uops[0].bits, issue_slots[16].iss_uop
node _T_717 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_718 = and(issue_slots[16].request, _T_717)
node _T_719 = and(_T_718, can_allocate_32)
node _T_720 = or(_T_719, _T_694)
node _T_721 = and(issue_slots[16].request, can_allocate_32)
node _T_722 = eq(_T_694, UInt<1>(0h0))
node _T_723 = and(_T_721, _T_722)
node _T_724 = or(_T_723, UInt<1>(0h0))
node _fu_code_match_T_594 = and(issue_slots[16].iss_uop.fu_code[0], io.fu_types[1][0])
node _fu_code_match_T_595 = and(issue_slots[16].iss_uop.fu_code[1], io.fu_types[1][1])
node _fu_code_match_T_596 = and(issue_slots[16].iss_uop.fu_code[2], io.fu_types[1][2])
node _fu_code_match_T_597 = and(issue_slots[16].iss_uop.fu_code[3], io.fu_types[1][3])
node _fu_code_match_T_598 = and(issue_slots[16].iss_uop.fu_code[4], io.fu_types[1][4])
node _fu_code_match_T_599 = and(issue_slots[16].iss_uop.fu_code[5], io.fu_types[1][5])
node _fu_code_match_T_600 = and(issue_slots[16].iss_uop.fu_code[6], io.fu_types[1][6])
node _fu_code_match_T_601 = and(issue_slots[16].iss_uop.fu_code[7], io.fu_types[1][7])
node _fu_code_match_T_602 = and(issue_slots[16].iss_uop.fu_code[8], io.fu_types[1][8])
node _fu_code_match_T_603 = and(issue_slots[16].iss_uop.fu_code[9], io.fu_types[1][9])
node _fu_code_match_T_604 = or(_fu_code_match_T_594, _fu_code_match_T_595)
node _fu_code_match_T_605 = or(_fu_code_match_T_604, _fu_code_match_T_596)
node _fu_code_match_T_606 = or(_fu_code_match_T_605, _fu_code_match_T_597)
node _fu_code_match_T_607 = or(_fu_code_match_T_606, _fu_code_match_T_598)
node _fu_code_match_T_608 = or(_fu_code_match_T_607, _fu_code_match_T_599)
node _fu_code_match_T_609 = or(_fu_code_match_T_608, _fu_code_match_T_600)
node _fu_code_match_T_610 = or(_fu_code_match_T_609, _fu_code_match_T_601)
node _fu_code_match_T_611 = or(_fu_code_match_T_610, _fu_code_match_T_602)
node fu_code_match_33 = or(_fu_code_match_T_611, _fu_code_match_T_603)
node can_allocate_33 = and(fu_code_match_33, UInt<1>(0h1))
node _T_725 = eq(_T_724, UInt<1>(0h0))
node _T_726 = and(issue_slots[16].request, _T_725)
node _T_727 = and(_T_726, can_allocate_33)
node _T_728 = eq(_T_707, UInt<1>(0h0))
node _T_729 = and(_T_727, _T_728)
when _T_729 :
connect issue_slots[16].grant, UInt<1>(0h1)
connect iss_uops[1].valid, UInt<1>(0h1)
connect iss_uops[1].bits, issue_slots[16].iss_uop
node _T_730 = eq(_T_724, UInt<1>(0h0))
node _T_731 = and(issue_slots[16].request, _T_730)
node _T_732 = and(_T_731, can_allocate_33)
node _T_733 = or(_T_732, _T_707)
node _T_734 = and(issue_slots[16].request, can_allocate_33)
node _T_735 = eq(_T_707, UInt<1>(0h0))
node _T_736 = and(_T_734, _T_735)
node _T_737 = or(_T_736, _T_724)
connect issue_slots[17].grant, UInt<1>(0h0)
node _fu_code_match_T_612 = and(issue_slots[17].iss_uop.fu_code[0], io.fu_types[0][0])
node _fu_code_match_T_613 = and(issue_slots[17].iss_uop.fu_code[1], io.fu_types[0][1])
node _fu_code_match_T_614 = and(issue_slots[17].iss_uop.fu_code[2], io.fu_types[0][2])
node _fu_code_match_T_615 = and(issue_slots[17].iss_uop.fu_code[3], io.fu_types[0][3])
node _fu_code_match_T_616 = and(issue_slots[17].iss_uop.fu_code[4], io.fu_types[0][4])
node _fu_code_match_T_617 = and(issue_slots[17].iss_uop.fu_code[5], io.fu_types[0][5])
node _fu_code_match_T_618 = and(issue_slots[17].iss_uop.fu_code[6], io.fu_types[0][6])
node _fu_code_match_T_619 = and(issue_slots[17].iss_uop.fu_code[7], io.fu_types[0][7])
node _fu_code_match_T_620 = and(issue_slots[17].iss_uop.fu_code[8], io.fu_types[0][8])
node _fu_code_match_T_621 = and(issue_slots[17].iss_uop.fu_code[9], io.fu_types[0][9])
node _fu_code_match_T_622 = or(_fu_code_match_T_612, _fu_code_match_T_613)
node _fu_code_match_T_623 = or(_fu_code_match_T_622, _fu_code_match_T_614)
node _fu_code_match_T_624 = or(_fu_code_match_T_623, _fu_code_match_T_615)
node _fu_code_match_T_625 = or(_fu_code_match_T_624, _fu_code_match_T_616)
node _fu_code_match_T_626 = or(_fu_code_match_T_625, _fu_code_match_T_617)
node _fu_code_match_T_627 = or(_fu_code_match_T_626, _fu_code_match_T_618)
node _fu_code_match_T_628 = or(_fu_code_match_T_627, _fu_code_match_T_619)
node _fu_code_match_T_629 = or(_fu_code_match_T_628, _fu_code_match_T_620)
node fu_code_match_34 = or(_fu_code_match_T_629, _fu_code_match_T_621)
node can_allocate_34 = and(fu_code_match_34, UInt<1>(0h1))
node _T_738 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_739 = and(issue_slots[17].request, _T_738)
node _T_740 = and(_T_739, can_allocate_34)
node _T_741 = eq(_T_720, UInt<1>(0h0))
node _T_742 = and(_T_740, _T_741)
when _T_742 :
connect issue_slots[17].grant, UInt<1>(0h1)
connect iss_uops[0].valid, UInt<1>(0h1)
connect iss_uops[0].bits, issue_slots[17].iss_uop
node _T_743 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_744 = and(issue_slots[17].request, _T_743)
node _T_745 = and(_T_744, can_allocate_34)
node _T_746 = or(_T_745, _T_720)
node _T_747 = and(issue_slots[17].request, can_allocate_34)
node _T_748 = eq(_T_720, UInt<1>(0h0))
node _T_749 = and(_T_747, _T_748)
node _T_750 = or(_T_749, UInt<1>(0h0))
node _fu_code_match_T_630 = and(issue_slots[17].iss_uop.fu_code[0], io.fu_types[1][0])
node _fu_code_match_T_631 = and(issue_slots[17].iss_uop.fu_code[1], io.fu_types[1][1])
node _fu_code_match_T_632 = and(issue_slots[17].iss_uop.fu_code[2], io.fu_types[1][2])
node _fu_code_match_T_633 = and(issue_slots[17].iss_uop.fu_code[3], io.fu_types[1][3])
node _fu_code_match_T_634 = and(issue_slots[17].iss_uop.fu_code[4], io.fu_types[1][4])
node _fu_code_match_T_635 = and(issue_slots[17].iss_uop.fu_code[5], io.fu_types[1][5])
node _fu_code_match_T_636 = and(issue_slots[17].iss_uop.fu_code[6], io.fu_types[1][6])
node _fu_code_match_T_637 = and(issue_slots[17].iss_uop.fu_code[7], io.fu_types[1][7])
node _fu_code_match_T_638 = and(issue_slots[17].iss_uop.fu_code[8], io.fu_types[1][8])
node _fu_code_match_T_639 = and(issue_slots[17].iss_uop.fu_code[9], io.fu_types[1][9])
node _fu_code_match_T_640 = or(_fu_code_match_T_630, _fu_code_match_T_631)
node _fu_code_match_T_641 = or(_fu_code_match_T_640, _fu_code_match_T_632)
node _fu_code_match_T_642 = or(_fu_code_match_T_641, _fu_code_match_T_633)
node _fu_code_match_T_643 = or(_fu_code_match_T_642, _fu_code_match_T_634)
node _fu_code_match_T_644 = or(_fu_code_match_T_643, _fu_code_match_T_635)
node _fu_code_match_T_645 = or(_fu_code_match_T_644, _fu_code_match_T_636)
node _fu_code_match_T_646 = or(_fu_code_match_T_645, _fu_code_match_T_637)
node _fu_code_match_T_647 = or(_fu_code_match_T_646, _fu_code_match_T_638)
node fu_code_match_35 = or(_fu_code_match_T_647, _fu_code_match_T_639)
node can_allocate_35 = and(fu_code_match_35, UInt<1>(0h1))
node _T_751 = eq(_T_750, UInt<1>(0h0))
node _T_752 = and(issue_slots[17].request, _T_751)
node _T_753 = and(_T_752, can_allocate_35)
node _T_754 = eq(_T_733, UInt<1>(0h0))
node _T_755 = and(_T_753, _T_754)
when _T_755 :
connect issue_slots[17].grant, UInt<1>(0h1)
connect iss_uops[1].valid, UInt<1>(0h1)
connect iss_uops[1].bits, issue_slots[17].iss_uop
node _T_756 = eq(_T_750, UInt<1>(0h0))
node _T_757 = and(issue_slots[17].request, _T_756)
node _T_758 = and(_T_757, can_allocate_35)
node _T_759 = or(_T_758, _T_733)
node _T_760 = and(issue_slots[17].request, can_allocate_35)
node _T_761 = eq(_T_733, UInt<1>(0h0))
node _T_762 = and(_T_760, _T_761)
node _T_763 = or(_T_762, _T_750)
connect issue_slots[18].grant, UInt<1>(0h0)
node _fu_code_match_T_648 = and(issue_slots[18].iss_uop.fu_code[0], io.fu_types[0][0])
node _fu_code_match_T_649 = and(issue_slots[18].iss_uop.fu_code[1], io.fu_types[0][1])
node _fu_code_match_T_650 = and(issue_slots[18].iss_uop.fu_code[2], io.fu_types[0][2])
node _fu_code_match_T_651 = and(issue_slots[18].iss_uop.fu_code[3], io.fu_types[0][3])
node _fu_code_match_T_652 = and(issue_slots[18].iss_uop.fu_code[4], io.fu_types[0][4])
node _fu_code_match_T_653 = and(issue_slots[18].iss_uop.fu_code[5], io.fu_types[0][5])
node _fu_code_match_T_654 = and(issue_slots[18].iss_uop.fu_code[6], io.fu_types[0][6])
node _fu_code_match_T_655 = and(issue_slots[18].iss_uop.fu_code[7], io.fu_types[0][7])
node _fu_code_match_T_656 = and(issue_slots[18].iss_uop.fu_code[8], io.fu_types[0][8])
node _fu_code_match_T_657 = and(issue_slots[18].iss_uop.fu_code[9], io.fu_types[0][9])
node _fu_code_match_T_658 = or(_fu_code_match_T_648, _fu_code_match_T_649)
node _fu_code_match_T_659 = or(_fu_code_match_T_658, _fu_code_match_T_650)
node _fu_code_match_T_660 = or(_fu_code_match_T_659, _fu_code_match_T_651)
node _fu_code_match_T_661 = or(_fu_code_match_T_660, _fu_code_match_T_652)
node _fu_code_match_T_662 = or(_fu_code_match_T_661, _fu_code_match_T_653)
node _fu_code_match_T_663 = or(_fu_code_match_T_662, _fu_code_match_T_654)
node _fu_code_match_T_664 = or(_fu_code_match_T_663, _fu_code_match_T_655)
node _fu_code_match_T_665 = or(_fu_code_match_T_664, _fu_code_match_T_656)
node fu_code_match_36 = or(_fu_code_match_T_665, _fu_code_match_T_657)
node can_allocate_36 = and(fu_code_match_36, UInt<1>(0h1))
node _T_764 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_765 = and(issue_slots[18].request, _T_764)
node _T_766 = and(_T_765, can_allocate_36)
node _T_767 = eq(_T_746, UInt<1>(0h0))
node _T_768 = and(_T_766, _T_767)
when _T_768 :
connect issue_slots[18].grant, UInt<1>(0h1)
connect iss_uops[0].valid, UInt<1>(0h1)
connect iss_uops[0].bits, issue_slots[18].iss_uop
node _T_769 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_770 = and(issue_slots[18].request, _T_769)
node _T_771 = and(_T_770, can_allocate_36)
node _T_772 = or(_T_771, _T_746)
node _T_773 = and(issue_slots[18].request, can_allocate_36)
node _T_774 = eq(_T_746, UInt<1>(0h0))
node _T_775 = and(_T_773, _T_774)
node _T_776 = or(_T_775, UInt<1>(0h0))
node _fu_code_match_T_666 = and(issue_slots[18].iss_uop.fu_code[0], io.fu_types[1][0])
node _fu_code_match_T_667 = and(issue_slots[18].iss_uop.fu_code[1], io.fu_types[1][1])
node _fu_code_match_T_668 = and(issue_slots[18].iss_uop.fu_code[2], io.fu_types[1][2])
node _fu_code_match_T_669 = and(issue_slots[18].iss_uop.fu_code[3], io.fu_types[1][3])
node _fu_code_match_T_670 = and(issue_slots[18].iss_uop.fu_code[4], io.fu_types[1][4])
node _fu_code_match_T_671 = and(issue_slots[18].iss_uop.fu_code[5], io.fu_types[1][5])
node _fu_code_match_T_672 = and(issue_slots[18].iss_uop.fu_code[6], io.fu_types[1][6])
node _fu_code_match_T_673 = and(issue_slots[18].iss_uop.fu_code[7], io.fu_types[1][7])
node _fu_code_match_T_674 = and(issue_slots[18].iss_uop.fu_code[8], io.fu_types[1][8])
node _fu_code_match_T_675 = and(issue_slots[18].iss_uop.fu_code[9], io.fu_types[1][9])
node _fu_code_match_T_676 = or(_fu_code_match_T_666, _fu_code_match_T_667)
node _fu_code_match_T_677 = or(_fu_code_match_T_676, _fu_code_match_T_668)
node _fu_code_match_T_678 = or(_fu_code_match_T_677, _fu_code_match_T_669)
node _fu_code_match_T_679 = or(_fu_code_match_T_678, _fu_code_match_T_670)
node _fu_code_match_T_680 = or(_fu_code_match_T_679, _fu_code_match_T_671)
node _fu_code_match_T_681 = or(_fu_code_match_T_680, _fu_code_match_T_672)
node _fu_code_match_T_682 = or(_fu_code_match_T_681, _fu_code_match_T_673)
node _fu_code_match_T_683 = or(_fu_code_match_T_682, _fu_code_match_T_674)
node fu_code_match_37 = or(_fu_code_match_T_683, _fu_code_match_T_675)
node can_allocate_37 = and(fu_code_match_37, UInt<1>(0h1))
node _T_777 = eq(_T_776, UInt<1>(0h0))
node _T_778 = and(issue_slots[18].request, _T_777)
node _T_779 = and(_T_778, can_allocate_37)
node _T_780 = eq(_T_759, UInt<1>(0h0))
node _T_781 = and(_T_779, _T_780)
when _T_781 :
connect issue_slots[18].grant, UInt<1>(0h1)
connect iss_uops[1].valid, UInt<1>(0h1)
connect iss_uops[1].bits, issue_slots[18].iss_uop
node _T_782 = eq(_T_776, UInt<1>(0h0))
node _T_783 = and(issue_slots[18].request, _T_782)
node _T_784 = and(_T_783, can_allocate_37)
node _T_785 = or(_T_784, _T_759)
node _T_786 = and(issue_slots[18].request, can_allocate_37)
node _T_787 = eq(_T_759, UInt<1>(0h0))
node _T_788 = and(_T_786, _T_787)
node _T_789 = or(_T_788, _T_776)
connect issue_slots[19].grant, UInt<1>(0h0)
node _fu_code_match_T_684 = and(issue_slots[19].iss_uop.fu_code[0], io.fu_types[0][0])
node _fu_code_match_T_685 = and(issue_slots[19].iss_uop.fu_code[1], io.fu_types[0][1])
node _fu_code_match_T_686 = and(issue_slots[19].iss_uop.fu_code[2], io.fu_types[0][2])
node _fu_code_match_T_687 = and(issue_slots[19].iss_uop.fu_code[3], io.fu_types[0][3])
node _fu_code_match_T_688 = and(issue_slots[19].iss_uop.fu_code[4], io.fu_types[0][4])
node _fu_code_match_T_689 = and(issue_slots[19].iss_uop.fu_code[5], io.fu_types[0][5])
node _fu_code_match_T_690 = and(issue_slots[19].iss_uop.fu_code[6], io.fu_types[0][6])
node _fu_code_match_T_691 = and(issue_slots[19].iss_uop.fu_code[7], io.fu_types[0][7])
node _fu_code_match_T_692 = and(issue_slots[19].iss_uop.fu_code[8], io.fu_types[0][8])
node _fu_code_match_T_693 = and(issue_slots[19].iss_uop.fu_code[9], io.fu_types[0][9])
node _fu_code_match_T_694 = or(_fu_code_match_T_684, _fu_code_match_T_685)
node _fu_code_match_T_695 = or(_fu_code_match_T_694, _fu_code_match_T_686)
node _fu_code_match_T_696 = or(_fu_code_match_T_695, _fu_code_match_T_687)
node _fu_code_match_T_697 = or(_fu_code_match_T_696, _fu_code_match_T_688)
node _fu_code_match_T_698 = or(_fu_code_match_T_697, _fu_code_match_T_689)
node _fu_code_match_T_699 = or(_fu_code_match_T_698, _fu_code_match_T_690)
node _fu_code_match_T_700 = or(_fu_code_match_T_699, _fu_code_match_T_691)
node _fu_code_match_T_701 = or(_fu_code_match_T_700, _fu_code_match_T_692)
node fu_code_match_38 = or(_fu_code_match_T_701, _fu_code_match_T_693)
node can_allocate_38 = and(fu_code_match_38, UInt<1>(0h1))
node _T_790 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_791 = and(issue_slots[19].request, _T_790)
node _T_792 = and(_T_791, can_allocate_38)
node _T_793 = eq(_T_772, UInt<1>(0h0))
node _T_794 = and(_T_792, _T_793)
when _T_794 :
connect issue_slots[19].grant, UInt<1>(0h1)
connect iss_uops[0].valid, UInt<1>(0h1)
connect iss_uops[0].bits, issue_slots[19].iss_uop
node _T_795 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_796 = and(issue_slots[19].request, _T_795)
node _T_797 = and(_T_796, can_allocate_38)
node _T_798 = or(_T_797, _T_772)
node _T_799 = and(issue_slots[19].request, can_allocate_38)
node _T_800 = eq(_T_772, UInt<1>(0h0))
node _T_801 = and(_T_799, _T_800)
node _T_802 = or(_T_801, UInt<1>(0h0))
node _fu_code_match_T_702 = and(issue_slots[19].iss_uop.fu_code[0], io.fu_types[1][0])
node _fu_code_match_T_703 = and(issue_slots[19].iss_uop.fu_code[1], io.fu_types[1][1])
node _fu_code_match_T_704 = and(issue_slots[19].iss_uop.fu_code[2], io.fu_types[1][2])
node _fu_code_match_T_705 = and(issue_slots[19].iss_uop.fu_code[3], io.fu_types[1][3])
node _fu_code_match_T_706 = and(issue_slots[19].iss_uop.fu_code[4], io.fu_types[1][4])
node _fu_code_match_T_707 = and(issue_slots[19].iss_uop.fu_code[5], io.fu_types[1][5])
node _fu_code_match_T_708 = and(issue_slots[19].iss_uop.fu_code[6], io.fu_types[1][6])
node _fu_code_match_T_709 = and(issue_slots[19].iss_uop.fu_code[7], io.fu_types[1][7])
node _fu_code_match_T_710 = and(issue_slots[19].iss_uop.fu_code[8], io.fu_types[1][8])
node _fu_code_match_T_711 = and(issue_slots[19].iss_uop.fu_code[9], io.fu_types[1][9])
node _fu_code_match_T_712 = or(_fu_code_match_T_702, _fu_code_match_T_703)
node _fu_code_match_T_713 = or(_fu_code_match_T_712, _fu_code_match_T_704)
node _fu_code_match_T_714 = or(_fu_code_match_T_713, _fu_code_match_T_705)
node _fu_code_match_T_715 = or(_fu_code_match_T_714, _fu_code_match_T_706)
node _fu_code_match_T_716 = or(_fu_code_match_T_715, _fu_code_match_T_707)
node _fu_code_match_T_717 = or(_fu_code_match_T_716, _fu_code_match_T_708)
node _fu_code_match_T_718 = or(_fu_code_match_T_717, _fu_code_match_T_709)
node _fu_code_match_T_719 = or(_fu_code_match_T_718, _fu_code_match_T_710)
node fu_code_match_39 = or(_fu_code_match_T_719, _fu_code_match_T_711)
node can_allocate_39 = and(fu_code_match_39, UInt<1>(0h1))
node _T_803 = eq(_T_802, UInt<1>(0h0))
node _T_804 = and(issue_slots[19].request, _T_803)
node _T_805 = and(_T_804, can_allocate_39)
node _T_806 = eq(_T_785, UInt<1>(0h0))
node _T_807 = and(_T_805, _T_806)
when _T_807 :
connect issue_slots[19].grant, UInt<1>(0h1)
connect iss_uops[1].valid, UInt<1>(0h1)
connect iss_uops[1].bits, issue_slots[19].iss_uop
node _T_808 = eq(_T_802, UInt<1>(0h0))
node _T_809 = and(issue_slots[19].request, _T_808)
node _T_810 = and(_T_809, can_allocate_39)
node _T_811 = or(_T_810, _T_785)
node _T_812 = and(issue_slots[19].request, can_allocate_39)
node _T_813 = eq(_T_785, UInt<1>(0h0))
node _T_814 = and(_T_812, _T_813)
node _T_815 = or(_T_814, _T_802)
connect io.iss_uops, iss_uops
when io.squash_grant :
connect io.iss_uops[0].valid, UInt<1>(0h0)
connect io.iss_uops[1].valid, UInt<1>(0h0) | module IssueUnitCollapsing_3( // @[issue-unit-age-ordered.scala:22:7]
input clock, // @[issue-unit-age-ordered.scala:22:7]
input reset, // @[issue-unit-age-ordered.scala:22:7]
output io_dis_uops_0_ready, // @[issue-unit.scala:44:14]
input io_dis_uops_0_valid, // @[issue-unit.scala:44:14]
input [31:0] io_dis_uops_0_bits_inst, // @[issue-unit.scala:44:14]
input [31:0] io_dis_uops_0_bits_debug_inst, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_is_rvc, // @[issue-unit.scala:44:14]
input [39:0] io_dis_uops_0_bits_debug_pc, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_iq_type_0, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_iq_type_1, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_iq_type_2, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_iq_type_3, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_fu_code_0, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_fu_code_1, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_fu_code_2, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_fu_code_3, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_fu_code_4, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_fu_code_5, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_fu_code_6, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_fu_code_7, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_fu_code_8, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_fu_code_9, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_iw_issued, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_iw_issued_partial_agen, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_iw_issued_partial_dgen, // @[issue-unit.scala:44:14]
input [1:0] io_dis_uops_0_bits_iw_p1_speculative_child, // @[issue-unit.scala:44:14]
input [1:0] io_dis_uops_0_bits_iw_p2_speculative_child, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_iw_p1_bypass_hint, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_iw_p2_bypass_hint, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_iw_p3_bypass_hint, // @[issue-unit.scala:44:14]
input [1:0] io_dis_uops_0_bits_dis_col_sel, // @[issue-unit.scala:44:14]
input [11:0] io_dis_uops_0_bits_br_mask, // @[issue-unit.scala:44:14]
input [3:0] io_dis_uops_0_bits_br_tag, // @[issue-unit.scala:44:14]
input [3:0] io_dis_uops_0_bits_br_type, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_is_sfb, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_is_fence, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_is_fencei, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_is_sfence, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_is_amo, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_is_eret, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_is_sys_pc2epc, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_is_rocc, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_is_mov, // @[issue-unit.scala:44:14]
input [4:0] io_dis_uops_0_bits_ftq_idx, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_edge_inst, // @[issue-unit.scala:44:14]
input [5:0] io_dis_uops_0_bits_pc_lob, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_taken, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_imm_rename, // @[issue-unit.scala:44:14]
input [2:0] io_dis_uops_0_bits_imm_sel, // @[issue-unit.scala:44:14]
input [4:0] io_dis_uops_0_bits_pimm, // @[issue-unit.scala:44:14]
input [19:0] io_dis_uops_0_bits_imm_packed, // @[issue-unit.scala:44:14]
input [1:0] io_dis_uops_0_bits_op1_sel, // @[issue-unit.scala:44:14]
input [2:0] io_dis_uops_0_bits_op2_sel, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_fp_ctrl_ldst, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_fp_ctrl_wen, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_fp_ctrl_ren1, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_fp_ctrl_ren2, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_fp_ctrl_ren3, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_fp_ctrl_swap12, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_fp_ctrl_swap23, // @[issue-unit.scala:44:14]
input [1:0] io_dis_uops_0_bits_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14]
input [1:0] io_dis_uops_0_bits_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_fp_ctrl_fromint, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_fp_ctrl_toint, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_fp_ctrl_fma, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_fp_ctrl_div, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_fp_ctrl_sqrt, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_fp_ctrl_wflags, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_fp_ctrl_vec, // @[issue-unit.scala:44:14]
input [5:0] io_dis_uops_0_bits_rob_idx, // @[issue-unit.scala:44:14]
input [3:0] io_dis_uops_0_bits_ldq_idx, // @[issue-unit.scala:44:14]
input [3:0] io_dis_uops_0_bits_stq_idx, // @[issue-unit.scala:44:14]
input [1:0] io_dis_uops_0_bits_rxq_idx, // @[issue-unit.scala:44:14]
input [6:0] io_dis_uops_0_bits_pdst, // @[issue-unit.scala:44:14]
input [6:0] io_dis_uops_0_bits_prs1, // @[issue-unit.scala:44:14]
input [6:0] io_dis_uops_0_bits_prs2, // @[issue-unit.scala:44:14]
input [6:0] io_dis_uops_0_bits_prs3, // @[issue-unit.scala:44:14]
input [4:0] io_dis_uops_0_bits_ppred, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_prs1_busy, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_prs2_busy, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_prs3_busy, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_ppred_busy, // @[issue-unit.scala:44:14]
input [6:0] io_dis_uops_0_bits_stale_pdst, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_exception, // @[issue-unit.scala:44:14]
input [63:0] io_dis_uops_0_bits_exc_cause, // @[issue-unit.scala:44:14]
input [4:0] io_dis_uops_0_bits_mem_cmd, // @[issue-unit.scala:44:14]
input [1:0] io_dis_uops_0_bits_mem_size, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_mem_signed, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_uses_ldq, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_uses_stq, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_is_unique, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_flush_on_commit, // @[issue-unit.scala:44:14]
input [2:0] io_dis_uops_0_bits_csr_cmd, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_ldst_is_rs1, // @[issue-unit.scala:44:14]
input [5:0] io_dis_uops_0_bits_ldst, // @[issue-unit.scala:44:14]
input [5:0] io_dis_uops_0_bits_lrs1, // @[issue-unit.scala:44:14]
input [5:0] io_dis_uops_0_bits_lrs2, // @[issue-unit.scala:44:14]
input [5:0] io_dis_uops_0_bits_lrs3, // @[issue-unit.scala:44:14]
input [1:0] io_dis_uops_0_bits_dst_rtype, // @[issue-unit.scala:44:14]
input [1:0] io_dis_uops_0_bits_lrs1_rtype, // @[issue-unit.scala:44:14]
input [1:0] io_dis_uops_0_bits_lrs2_rtype, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_frs3_en, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_fcn_dw, // @[issue-unit.scala:44:14]
input [4:0] io_dis_uops_0_bits_fcn_op, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_fp_val, // @[issue-unit.scala:44:14]
input [2:0] io_dis_uops_0_bits_fp_rm, // @[issue-unit.scala:44:14]
input [1:0] io_dis_uops_0_bits_fp_typ, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_xcpt_pf_if, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_xcpt_ae_if, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_xcpt_ma_if, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_bp_debug_if, // @[issue-unit.scala:44:14]
input io_dis_uops_0_bits_bp_xcpt_if, // @[issue-unit.scala:44:14]
input [2:0] io_dis_uops_0_bits_debug_fsrc, // @[issue-unit.scala:44:14]
input [2:0] io_dis_uops_0_bits_debug_tsrc, // @[issue-unit.scala:44:14]
output io_dis_uops_1_ready, // @[issue-unit.scala:44:14]
input io_dis_uops_1_valid, // @[issue-unit.scala:44:14]
input [31:0] io_dis_uops_1_bits_inst, // @[issue-unit.scala:44:14]
input [31:0] io_dis_uops_1_bits_debug_inst, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_is_rvc, // @[issue-unit.scala:44:14]
input [39:0] io_dis_uops_1_bits_debug_pc, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_iq_type_0, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_iq_type_1, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_iq_type_2, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_iq_type_3, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_fu_code_0, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_fu_code_1, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_fu_code_2, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_fu_code_3, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_fu_code_4, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_fu_code_5, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_fu_code_6, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_fu_code_7, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_fu_code_8, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_fu_code_9, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_iw_issued, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_iw_issued_partial_agen, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_iw_issued_partial_dgen, // @[issue-unit.scala:44:14]
input [1:0] io_dis_uops_1_bits_iw_p1_speculative_child, // @[issue-unit.scala:44:14]
input [1:0] io_dis_uops_1_bits_iw_p2_speculative_child, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_iw_p1_bypass_hint, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_iw_p2_bypass_hint, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_iw_p3_bypass_hint, // @[issue-unit.scala:44:14]
input [1:0] io_dis_uops_1_bits_dis_col_sel, // @[issue-unit.scala:44:14]
input [11:0] io_dis_uops_1_bits_br_mask, // @[issue-unit.scala:44:14]
input [3:0] io_dis_uops_1_bits_br_tag, // @[issue-unit.scala:44:14]
input [3:0] io_dis_uops_1_bits_br_type, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_is_sfb, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_is_fence, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_is_fencei, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_is_sfence, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_is_amo, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_is_eret, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_is_sys_pc2epc, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_is_rocc, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_is_mov, // @[issue-unit.scala:44:14]
input [4:0] io_dis_uops_1_bits_ftq_idx, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_edge_inst, // @[issue-unit.scala:44:14]
input [5:0] io_dis_uops_1_bits_pc_lob, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_taken, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_imm_rename, // @[issue-unit.scala:44:14]
input [2:0] io_dis_uops_1_bits_imm_sel, // @[issue-unit.scala:44:14]
input [4:0] io_dis_uops_1_bits_pimm, // @[issue-unit.scala:44:14]
input [19:0] io_dis_uops_1_bits_imm_packed, // @[issue-unit.scala:44:14]
input [1:0] io_dis_uops_1_bits_op1_sel, // @[issue-unit.scala:44:14]
input [2:0] io_dis_uops_1_bits_op2_sel, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_fp_ctrl_ldst, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_fp_ctrl_wen, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_fp_ctrl_ren1, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_fp_ctrl_ren2, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_fp_ctrl_ren3, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_fp_ctrl_swap12, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_fp_ctrl_swap23, // @[issue-unit.scala:44:14]
input [1:0] io_dis_uops_1_bits_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14]
input [1:0] io_dis_uops_1_bits_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_fp_ctrl_fromint, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_fp_ctrl_toint, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_fp_ctrl_fma, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_fp_ctrl_div, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_fp_ctrl_sqrt, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_fp_ctrl_wflags, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_fp_ctrl_vec, // @[issue-unit.scala:44:14]
input [5:0] io_dis_uops_1_bits_rob_idx, // @[issue-unit.scala:44:14]
input [3:0] io_dis_uops_1_bits_ldq_idx, // @[issue-unit.scala:44:14]
input [3:0] io_dis_uops_1_bits_stq_idx, // @[issue-unit.scala:44:14]
input [1:0] io_dis_uops_1_bits_rxq_idx, // @[issue-unit.scala:44:14]
input [6:0] io_dis_uops_1_bits_pdst, // @[issue-unit.scala:44:14]
input [6:0] io_dis_uops_1_bits_prs1, // @[issue-unit.scala:44:14]
input [6:0] io_dis_uops_1_bits_prs2, // @[issue-unit.scala:44:14]
input [6:0] io_dis_uops_1_bits_prs3, // @[issue-unit.scala:44:14]
input [4:0] io_dis_uops_1_bits_ppred, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_prs1_busy, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_prs2_busy, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_prs3_busy, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_ppred_busy, // @[issue-unit.scala:44:14]
input [6:0] io_dis_uops_1_bits_stale_pdst, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_exception, // @[issue-unit.scala:44:14]
input [63:0] io_dis_uops_1_bits_exc_cause, // @[issue-unit.scala:44:14]
input [4:0] io_dis_uops_1_bits_mem_cmd, // @[issue-unit.scala:44:14]
input [1:0] io_dis_uops_1_bits_mem_size, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_mem_signed, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_uses_ldq, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_uses_stq, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_is_unique, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_flush_on_commit, // @[issue-unit.scala:44:14]
input [2:0] io_dis_uops_1_bits_csr_cmd, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_ldst_is_rs1, // @[issue-unit.scala:44:14]
input [5:0] io_dis_uops_1_bits_ldst, // @[issue-unit.scala:44:14]
input [5:0] io_dis_uops_1_bits_lrs1, // @[issue-unit.scala:44:14]
input [5:0] io_dis_uops_1_bits_lrs2, // @[issue-unit.scala:44:14]
input [5:0] io_dis_uops_1_bits_lrs3, // @[issue-unit.scala:44:14]
input [1:0] io_dis_uops_1_bits_dst_rtype, // @[issue-unit.scala:44:14]
input [1:0] io_dis_uops_1_bits_lrs1_rtype, // @[issue-unit.scala:44:14]
input [1:0] io_dis_uops_1_bits_lrs2_rtype, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_frs3_en, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_fcn_dw, // @[issue-unit.scala:44:14]
input [4:0] io_dis_uops_1_bits_fcn_op, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_fp_val, // @[issue-unit.scala:44:14]
input [2:0] io_dis_uops_1_bits_fp_rm, // @[issue-unit.scala:44:14]
input [1:0] io_dis_uops_1_bits_fp_typ, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_xcpt_pf_if, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_xcpt_ae_if, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_xcpt_ma_if, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_bp_debug_if, // @[issue-unit.scala:44:14]
input io_dis_uops_1_bits_bp_xcpt_if, // @[issue-unit.scala:44:14]
input [2:0] io_dis_uops_1_bits_debug_fsrc, // @[issue-unit.scala:44:14]
input [2:0] io_dis_uops_1_bits_debug_tsrc, // @[issue-unit.scala:44:14]
output io_iss_uops_0_valid, // @[issue-unit.scala:44:14]
output [31:0] io_iss_uops_0_bits_inst, // @[issue-unit.scala:44:14]
output [31:0] io_iss_uops_0_bits_debug_inst, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_is_rvc, // @[issue-unit.scala:44:14]
output [39:0] io_iss_uops_0_bits_debug_pc, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_iq_type_0, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_iq_type_1, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_iq_type_2, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_iq_type_3, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_fu_code_0, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_fu_code_1, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_fu_code_2, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_fu_code_3, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_fu_code_4, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_fu_code_5, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_fu_code_6, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_fu_code_7, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_fu_code_8, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_fu_code_9, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_iw_issued, // @[issue-unit.scala:44:14]
output [1:0] io_iss_uops_0_bits_iw_p1_speculative_child, // @[issue-unit.scala:44:14]
output [1:0] io_iss_uops_0_bits_iw_p2_speculative_child, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_iw_p1_bypass_hint, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_iw_p2_bypass_hint, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_iw_p3_bypass_hint, // @[issue-unit.scala:44:14]
output [1:0] io_iss_uops_0_bits_dis_col_sel, // @[issue-unit.scala:44:14]
output [11:0] io_iss_uops_0_bits_br_mask, // @[issue-unit.scala:44:14]
output [3:0] io_iss_uops_0_bits_br_tag, // @[issue-unit.scala:44:14]
output [3:0] io_iss_uops_0_bits_br_type, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_is_sfb, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_is_fence, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_is_fencei, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_is_sfence, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_is_amo, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_is_eret, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_is_sys_pc2epc, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_is_rocc, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_is_mov, // @[issue-unit.scala:44:14]
output [4:0] io_iss_uops_0_bits_ftq_idx, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_edge_inst, // @[issue-unit.scala:44:14]
output [5:0] io_iss_uops_0_bits_pc_lob, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_taken, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_imm_rename, // @[issue-unit.scala:44:14]
output [2:0] io_iss_uops_0_bits_imm_sel, // @[issue-unit.scala:44:14]
output [4:0] io_iss_uops_0_bits_pimm, // @[issue-unit.scala:44:14]
output [19:0] io_iss_uops_0_bits_imm_packed, // @[issue-unit.scala:44:14]
output [1:0] io_iss_uops_0_bits_op1_sel, // @[issue-unit.scala:44:14]
output [2:0] io_iss_uops_0_bits_op2_sel, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_fp_ctrl_ldst, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_fp_ctrl_wen, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_fp_ctrl_ren1, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_fp_ctrl_ren2, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_fp_ctrl_ren3, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_fp_ctrl_swap12, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_fp_ctrl_swap23, // @[issue-unit.scala:44:14]
output [1:0] io_iss_uops_0_bits_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14]
output [1:0] io_iss_uops_0_bits_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_fp_ctrl_fromint, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_fp_ctrl_toint, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_fp_ctrl_fma, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_fp_ctrl_div, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_fp_ctrl_sqrt, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_fp_ctrl_wflags, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_fp_ctrl_vec, // @[issue-unit.scala:44:14]
output [5:0] io_iss_uops_0_bits_rob_idx, // @[issue-unit.scala:44:14]
output [3:0] io_iss_uops_0_bits_ldq_idx, // @[issue-unit.scala:44:14]
output [3:0] io_iss_uops_0_bits_stq_idx, // @[issue-unit.scala:44:14]
output [1:0] io_iss_uops_0_bits_rxq_idx, // @[issue-unit.scala:44:14]
output [6:0] io_iss_uops_0_bits_pdst, // @[issue-unit.scala:44:14]
output [6:0] io_iss_uops_0_bits_prs1, // @[issue-unit.scala:44:14]
output [6:0] io_iss_uops_0_bits_prs2, // @[issue-unit.scala:44:14]
output [6:0] io_iss_uops_0_bits_prs3, // @[issue-unit.scala:44:14]
output [4:0] io_iss_uops_0_bits_ppred, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_prs1_busy, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_prs2_busy, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_prs3_busy, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_ppred_busy, // @[issue-unit.scala:44:14]
output [6:0] io_iss_uops_0_bits_stale_pdst, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_exception, // @[issue-unit.scala:44:14]
output [63:0] io_iss_uops_0_bits_exc_cause, // @[issue-unit.scala:44:14]
output [4:0] io_iss_uops_0_bits_mem_cmd, // @[issue-unit.scala:44:14]
output [1:0] io_iss_uops_0_bits_mem_size, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_mem_signed, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_uses_ldq, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_uses_stq, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_is_unique, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_flush_on_commit, // @[issue-unit.scala:44:14]
output [2:0] io_iss_uops_0_bits_csr_cmd, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_ldst_is_rs1, // @[issue-unit.scala:44:14]
output [5:0] io_iss_uops_0_bits_ldst, // @[issue-unit.scala:44:14]
output [5:0] io_iss_uops_0_bits_lrs1, // @[issue-unit.scala:44:14]
output [5:0] io_iss_uops_0_bits_lrs2, // @[issue-unit.scala:44:14]
output [5:0] io_iss_uops_0_bits_lrs3, // @[issue-unit.scala:44:14]
output [1:0] io_iss_uops_0_bits_dst_rtype, // @[issue-unit.scala:44:14]
output [1:0] io_iss_uops_0_bits_lrs1_rtype, // @[issue-unit.scala:44:14]
output [1:0] io_iss_uops_0_bits_lrs2_rtype, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_frs3_en, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_fcn_dw, // @[issue-unit.scala:44:14]
output [4:0] io_iss_uops_0_bits_fcn_op, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_fp_val, // @[issue-unit.scala:44:14]
output [2:0] io_iss_uops_0_bits_fp_rm, // @[issue-unit.scala:44:14]
output [1:0] io_iss_uops_0_bits_fp_typ, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_xcpt_pf_if, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_xcpt_ae_if, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_xcpt_ma_if, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_bp_debug_if, // @[issue-unit.scala:44:14]
output io_iss_uops_0_bits_bp_xcpt_if, // @[issue-unit.scala:44:14]
output [2:0] io_iss_uops_0_bits_debug_fsrc, // @[issue-unit.scala:44:14]
output [2:0] io_iss_uops_0_bits_debug_tsrc, // @[issue-unit.scala:44:14]
output io_iss_uops_1_valid, // @[issue-unit.scala:44:14]
output [31:0] io_iss_uops_1_bits_inst, // @[issue-unit.scala:44:14]
output [31:0] io_iss_uops_1_bits_debug_inst, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_is_rvc, // @[issue-unit.scala:44:14]
output [39:0] io_iss_uops_1_bits_debug_pc, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_iq_type_0, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_iq_type_1, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_iq_type_2, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_iq_type_3, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_fu_code_0, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_fu_code_1, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_fu_code_2, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_fu_code_3, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_fu_code_4, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_fu_code_5, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_fu_code_6, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_fu_code_7, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_fu_code_8, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_fu_code_9, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_iw_issued, // @[issue-unit.scala:44:14]
output [1:0] io_iss_uops_1_bits_iw_p1_speculative_child, // @[issue-unit.scala:44:14]
output [1:0] io_iss_uops_1_bits_iw_p2_speculative_child, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_iw_p1_bypass_hint, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_iw_p2_bypass_hint, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_iw_p3_bypass_hint, // @[issue-unit.scala:44:14]
output [1:0] io_iss_uops_1_bits_dis_col_sel, // @[issue-unit.scala:44:14]
output [11:0] io_iss_uops_1_bits_br_mask, // @[issue-unit.scala:44:14]
output [3:0] io_iss_uops_1_bits_br_tag, // @[issue-unit.scala:44:14]
output [3:0] io_iss_uops_1_bits_br_type, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_is_sfb, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_is_fence, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_is_fencei, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_is_sfence, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_is_amo, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_is_eret, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_is_sys_pc2epc, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_is_rocc, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_is_mov, // @[issue-unit.scala:44:14]
output [4:0] io_iss_uops_1_bits_ftq_idx, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_edge_inst, // @[issue-unit.scala:44:14]
output [5:0] io_iss_uops_1_bits_pc_lob, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_taken, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_imm_rename, // @[issue-unit.scala:44:14]
output [2:0] io_iss_uops_1_bits_imm_sel, // @[issue-unit.scala:44:14]
output [4:0] io_iss_uops_1_bits_pimm, // @[issue-unit.scala:44:14]
output [19:0] io_iss_uops_1_bits_imm_packed, // @[issue-unit.scala:44:14]
output [1:0] io_iss_uops_1_bits_op1_sel, // @[issue-unit.scala:44:14]
output [2:0] io_iss_uops_1_bits_op2_sel, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_fp_ctrl_ldst, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_fp_ctrl_wen, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_fp_ctrl_ren1, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_fp_ctrl_ren2, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_fp_ctrl_ren3, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_fp_ctrl_swap12, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_fp_ctrl_swap23, // @[issue-unit.scala:44:14]
output [1:0] io_iss_uops_1_bits_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14]
output [1:0] io_iss_uops_1_bits_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_fp_ctrl_fromint, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_fp_ctrl_toint, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_fp_ctrl_fma, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_fp_ctrl_div, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_fp_ctrl_sqrt, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_fp_ctrl_wflags, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_fp_ctrl_vec, // @[issue-unit.scala:44:14]
output [5:0] io_iss_uops_1_bits_rob_idx, // @[issue-unit.scala:44:14]
output [3:0] io_iss_uops_1_bits_ldq_idx, // @[issue-unit.scala:44:14]
output [3:0] io_iss_uops_1_bits_stq_idx, // @[issue-unit.scala:44:14]
output [1:0] io_iss_uops_1_bits_rxq_idx, // @[issue-unit.scala:44:14]
output [6:0] io_iss_uops_1_bits_pdst, // @[issue-unit.scala:44:14]
output [6:0] io_iss_uops_1_bits_prs1, // @[issue-unit.scala:44:14]
output [6:0] io_iss_uops_1_bits_prs2, // @[issue-unit.scala:44:14]
output [6:0] io_iss_uops_1_bits_prs3, // @[issue-unit.scala:44:14]
output [4:0] io_iss_uops_1_bits_ppred, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_prs1_busy, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_prs2_busy, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_prs3_busy, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_ppred_busy, // @[issue-unit.scala:44:14]
output [6:0] io_iss_uops_1_bits_stale_pdst, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_exception, // @[issue-unit.scala:44:14]
output [63:0] io_iss_uops_1_bits_exc_cause, // @[issue-unit.scala:44:14]
output [4:0] io_iss_uops_1_bits_mem_cmd, // @[issue-unit.scala:44:14]
output [1:0] io_iss_uops_1_bits_mem_size, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_mem_signed, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_uses_ldq, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_uses_stq, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_is_unique, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_flush_on_commit, // @[issue-unit.scala:44:14]
output [2:0] io_iss_uops_1_bits_csr_cmd, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_ldst_is_rs1, // @[issue-unit.scala:44:14]
output [5:0] io_iss_uops_1_bits_ldst, // @[issue-unit.scala:44:14]
output [5:0] io_iss_uops_1_bits_lrs1, // @[issue-unit.scala:44:14]
output [5:0] io_iss_uops_1_bits_lrs2, // @[issue-unit.scala:44:14]
output [5:0] io_iss_uops_1_bits_lrs3, // @[issue-unit.scala:44:14]
output [1:0] io_iss_uops_1_bits_dst_rtype, // @[issue-unit.scala:44:14]
output [1:0] io_iss_uops_1_bits_lrs1_rtype, // @[issue-unit.scala:44:14]
output [1:0] io_iss_uops_1_bits_lrs2_rtype, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_frs3_en, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_fcn_dw, // @[issue-unit.scala:44:14]
output [4:0] io_iss_uops_1_bits_fcn_op, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_fp_val, // @[issue-unit.scala:44:14]
output [2:0] io_iss_uops_1_bits_fp_rm, // @[issue-unit.scala:44:14]
output [1:0] io_iss_uops_1_bits_fp_typ, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_xcpt_pf_if, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_xcpt_ae_if, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_xcpt_ma_if, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_bp_debug_if, // @[issue-unit.scala:44:14]
output io_iss_uops_1_bits_bp_xcpt_if, // @[issue-unit.scala:44:14]
output [2:0] io_iss_uops_1_bits_debug_fsrc, // @[issue-unit.scala:44:14]
output [2:0] io_iss_uops_1_bits_debug_tsrc, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_valid, // @[issue-unit.scala:44:14]
input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-unit.scala:44:14]
input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-unit.scala:44:14]
input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-unit.scala:44:14]
input [11:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-unit.scala:44:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-unit.scala:44:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-unit.scala:44:14]
input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-unit.scala:44:14]
input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_taken, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-unit.scala:44:14]
input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-unit.scala:44:14]
input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-unit.scala:44:14]
input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-unit.scala:44:14]
input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-unit.scala:44:14]
input [5:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-unit.scala:44:14]
input [3:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-unit.scala:44:14]
input [3:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-unit.scala:44:14]
input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-unit.scala:44:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-unit.scala:44:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-unit.scala:44:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-unit.scala:44:14]
input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-unit.scala:44:14]
input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_exception, // @[issue-unit.scala:44:14]
input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-unit.scala:44:14]
input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-unit.scala:44:14]
input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-unit.scala:44:14]
input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-unit.scala:44:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-unit.scala:44:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-unit.scala:44:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-unit.scala:44:14]
input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-unit.scala:44:14]
input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-unit.scala:44:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-unit.scala:44:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_bypassable, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-unit.scala:44:14]
input io_wakeup_ports_0_bits_rebusy, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_valid, // @[issue-unit.scala:44:14]
input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-unit.scala:44:14]
input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-unit.scala:44:14]
input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-unit.scala:44:14]
input [11:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-unit.scala:44:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-unit.scala:44:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-unit.scala:44:14]
input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-unit.scala:44:14]
input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_taken, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-unit.scala:44:14]
input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-unit.scala:44:14]
input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-unit.scala:44:14]
input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-unit.scala:44:14]
input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-unit.scala:44:14]
input [5:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-unit.scala:44:14]
input [3:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-unit.scala:44:14]
input [3:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-unit.scala:44:14]
input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-unit.scala:44:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-unit.scala:44:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-unit.scala:44:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-unit.scala:44:14]
input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-unit.scala:44:14]
input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_exception, // @[issue-unit.scala:44:14]
input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-unit.scala:44:14]
input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-unit.scala:44:14]
input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-unit.scala:44:14]
input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-unit.scala:44:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-unit.scala:44:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-unit.scala:44:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-unit.scala:44:14]
input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-unit.scala:44:14]
input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-unit.scala:44:14]
input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-unit.scala:44:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-unit.scala:44:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_valid, // @[issue-unit.scala:44:14]
input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-unit.scala:44:14]
input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-unit.scala:44:14]
input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-unit.scala:44:14]
input [11:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-unit.scala:44:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-unit.scala:44:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-unit.scala:44:14]
input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-unit.scala:44:14]
input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_taken, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-unit.scala:44:14]
input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-unit.scala:44:14]
input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-unit.scala:44:14]
input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-unit.scala:44:14]
input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-unit.scala:44:14]
input [5:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-unit.scala:44:14]
input [3:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-unit.scala:44:14]
input [3:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-unit.scala:44:14]
input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-unit.scala:44:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-unit.scala:44:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-unit.scala:44:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-unit.scala:44:14]
input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-unit.scala:44:14]
input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_exception, // @[issue-unit.scala:44:14]
input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-unit.scala:44:14]
input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-unit.scala:44:14]
input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-unit.scala:44:14]
input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-unit.scala:44:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-unit.scala:44:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-unit.scala:44:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-unit.scala:44:14]
input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-unit.scala:44:14]
input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-unit.scala:44:14]
input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-unit.scala:44:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-unit.scala:44:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_valid, // @[issue-unit.scala:44:14]
input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-unit.scala:44:14]
input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-unit.scala:44:14]
input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-unit.scala:44:14]
input [11:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-unit.scala:44:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-unit.scala:44:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-unit.scala:44:14]
input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-unit.scala:44:14]
input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_taken, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-unit.scala:44:14]
input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-unit.scala:44:14]
input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-unit.scala:44:14]
input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-unit.scala:44:14]
input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-unit.scala:44:14]
input [5:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-unit.scala:44:14]
input [3:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-unit.scala:44:14]
input [3:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-unit.scala:44:14]
input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-unit.scala:44:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-unit.scala:44:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-unit.scala:44:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-unit.scala:44:14]
input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-unit.scala:44:14]
input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_exception, // @[issue-unit.scala:44:14]
input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-unit.scala:44:14]
input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-unit.scala:44:14]
input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-unit.scala:44:14]
input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-unit.scala:44:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-unit.scala:44:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-unit.scala:44:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-unit.scala:44:14]
input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-unit.scala:44:14]
input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-unit.scala:44:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-unit.scala:44:14]
input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-unit.scala:44:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-unit.scala:44:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-unit.scala:44:14]
input io_pred_wakeup_port_valid, // @[issue-unit.scala:44:14]
input [4:0] io_pred_wakeup_port_bits, // @[issue-unit.scala:44:14]
input [1:0] io_child_rebusys, // @[issue-unit.scala:44:14]
input [11:0] io_brupdate_b1_resolve_mask, // @[issue-unit.scala:44:14]
input [11:0] io_brupdate_b1_mispredict_mask, // @[issue-unit.scala:44:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-unit.scala:44:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-unit.scala:44:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_iq_type_0, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_iq_type_1, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_iq_type_2, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_iq_type_3, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_fu_code_0, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_fu_code_1, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_fu_code_2, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_fu_code_3, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_fu_code_4, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_fu_code_5, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_fu_code_6, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_fu_code_7, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_fu_code_8, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_fu_code_9, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_iw_issued, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-unit.scala:44:14]
input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-unit.scala:44:14]
input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-unit.scala:44:14]
input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-unit.scala:44:14]
input [11:0] io_brupdate_b2_uop_br_mask, // @[issue-unit.scala:44:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-unit.scala:44:14]
input [3:0] io_brupdate_b2_uop_br_type, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_is_fence, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_is_sfence, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_is_amo, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_is_eret, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_is_rocc, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_is_mov, // @[issue-unit.scala:44:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-unit.scala:44:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_taken, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_imm_rename, // @[issue-unit.scala:44:14]
input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-unit.scala:44:14]
input [4:0] io_brupdate_b2_uop_pimm, // @[issue-unit.scala:44:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-unit.scala:44:14]
input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-unit.scala:44:14]
input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-unit.scala:44:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-unit.scala:44:14]
input [5:0] io_brupdate_b2_uop_rob_idx, // @[issue-unit.scala:44:14]
input [3:0] io_brupdate_b2_uop_ldq_idx, // @[issue-unit.scala:44:14]
input [3:0] io_brupdate_b2_uop_stq_idx, // @[issue-unit.scala:44:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-unit.scala:44:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-unit.scala:44:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-unit.scala:44:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-unit.scala:44:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-unit.scala:44:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-unit.scala:44:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_exception, // @[issue-unit.scala:44:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-unit.scala:44:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-unit.scala:44:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_is_unique, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-unit.scala:44:14]
input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-unit.scala:44:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-unit.scala:44:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-unit.scala:44:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-unit.scala:44:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-unit.scala:44:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-unit.scala:44:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-unit.scala:44:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_fcn_dw, // @[issue-unit.scala:44:14]
input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_fp_val, // @[issue-unit.scala:44:14]
input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-unit.scala:44:14]
input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-unit.scala:44:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-unit.scala:44:14]
input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-unit.scala:44:14]
input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-unit.scala:44:14]
input io_brupdate_b2_mispredict, // @[issue-unit.scala:44:14]
input io_brupdate_b2_taken, // @[issue-unit.scala:44:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-unit.scala:44:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-unit.scala:44:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-unit.scala:44:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-unit.scala:44:14]
input io_flush_pipeline, // @[issue-unit.scala:44:14]
input io_squash_grant, // @[issue-unit.scala:44:14]
input [63:0] io_tsc_reg // @[issue-unit.scala:44:14]
);
wire issue_slots_19_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire io_dis_uops_0_valid_0 = io_dis_uops_0_valid; // @[issue-unit-age-ordered.scala:22:7]
wire [31:0] io_dis_uops_0_bits_inst_0 = io_dis_uops_0_bits_inst; // @[issue-unit-age-ordered.scala:22:7]
wire [31:0] io_dis_uops_0_bits_debug_inst_0 = io_dis_uops_0_bits_debug_inst; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_is_rvc_0 = io_dis_uops_0_bits_is_rvc; // @[issue-unit-age-ordered.scala:22:7]
wire [39:0] io_dis_uops_0_bits_debug_pc_0 = io_dis_uops_0_bits_debug_pc; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_iq_type_0_0 = io_dis_uops_0_bits_iq_type_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_iq_type_1_0 = io_dis_uops_0_bits_iq_type_1; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_iq_type_2_0 = io_dis_uops_0_bits_iq_type_2; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_iq_type_3_0 = io_dis_uops_0_bits_iq_type_3; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_fu_code_0_0 = io_dis_uops_0_bits_fu_code_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_fu_code_1_0 = io_dis_uops_0_bits_fu_code_1; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_fu_code_2_0 = io_dis_uops_0_bits_fu_code_2; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_fu_code_3_0 = io_dis_uops_0_bits_fu_code_3; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_fu_code_4_0 = io_dis_uops_0_bits_fu_code_4; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_fu_code_5_0 = io_dis_uops_0_bits_fu_code_5; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_fu_code_6_0 = io_dis_uops_0_bits_fu_code_6; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_fu_code_7_0 = io_dis_uops_0_bits_fu_code_7; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_fu_code_8_0 = io_dis_uops_0_bits_fu_code_8; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_fu_code_9_0 = io_dis_uops_0_bits_fu_code_9; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_iw_issued_0 = io_dis_uops_0_bits_iw_issued; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_iw_issued_partial_agen_0 = io_dis_uops_0_bits_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_iw_issued_partial_dgen_0 = io_dis_uops_0_bits_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_dis_uops_0_bits_iw_p1_speculative_child_0 = io_dis_uops_0_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_dis_uops_0_bits_iw_p2_speculative_child_0 = io_dis_uops_0_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_iw_p1_bypass_hint_0 = io_dis_uops_0_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_iw_p2_bypass_hint_0 = io_dis_uops_0_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_iw_p3_bypass_hint_0 = io_dis_uops_0_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_dis_uops_0_bits_dis_col_sel_0 = io_dis_uops_0_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7]
wire [11:0] io_dis_uops_0_bits_br_mask_0 = io_dis_uops_0_bits_br_mask; // @[issue-unit-age-ordered.scala:22:7]
wire [3:0] io_dis_uops_0_bits_br_tag_0 = io_dis_uops_0_bits_br_tag; // @[issue-unit-age-ordered.scala:22:7]
wire [3:0] io_dis_uops_0_bits_br_type_0 = io_dis_uops_0_bits_br_type; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_is_sfb_0 = io_dis_uops_0_bits_is_sfb; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_is_fence_0 = io_dis_uops_0_bits_is_fence; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_is_fencei_0 = io_dis_uops_0_bits_is_fencei; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_is_sfence_0 = io_dis_uops_0_bits_is_sfence; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_is_amo_0 = io_dis_uops_0_bits_is_amo; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_is_eret_0 = io_dis_uops_0_bits_is_eret; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_is_sys_pc2epc_0 = io_dis_uops_0_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_is_rocc_0 = io_dis_uops_0_bits_is_rocc; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_is_mov_0 = io_dis_uops_0_bits_is_mov; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_dis_uops_0_bits_ftq_idx_0 = io_dis_uops_0_bits_ftq_idx; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_edge_inst_0 = io_dis_uops_0_bits_edge_inst; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_dis_uops_0_bits_pc_lob_0 = io_dis_uops_0_bits_pc_lob; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_taken_0 = io_dis_uops_0_bits_taken; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_imm_rename_0 = io_dis_uops_0_bits_imm_rename; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_dis_uops_0_bits_imm_sel_0 = io_dis_uops_0_bits_imm_sel; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_dis_uops_0_bits_pimm_0 = io_dis_uops_0_bits_pimm; // @[issue-unit-age-ordered.scala:22:7]
wire [19:0] io_dis_uops_0_bits_imm_packed_0 = io_dis_uops_0_bits_imm_packed; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_dis_uops_0_bits_op1_sel_0 = io_dis_uops_0_bits_op1_sel; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_dis_uops_0_bits_op2_sel_0 = io_dis_uops_0_bits_op2_sel; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_fp_ctrl_ldst_0 = io_dis_uops_0_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_fp_ctrl_wen_0 = io_dis_uops_0_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_fp_ctrl_ren1_0 = io_dis_uops_0_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_fp_ctrl_ren2_0 = io_dis_uops_0_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_fp_ctrl_ren3_0 = io_dis_uops_0_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_fp_ctrl_swap12_0 = io_dis_uops_0_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_fp_ctrl_swap23_0 = io_dis_uops_0_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_dis_uops_0_bits_fp_ctrl_typeTagIn_0 = io_dis_uops_0_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_dis_uops_0_bits_fp_ctrl_typeTagOut_0 = io_dis_uops_0_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_fp_ctrl_fromint_0 = io_dis_uops_0_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_fp_ctrl_toint_0 = io_dis_uops_0_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_fp_ctrl_fastpipe_0 = io_dis_uops_0_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_fp_ctrl_fma_0 = io_dis_uops_0_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_fp_ctrl_div_0 = io_dis_uops_0_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_fp_ctrl_sqrt_0 = io_dis_uops_0_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_fp_ctrl_wflags_0 = io_dis_uops_0_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_fp_ctrl_vec_0 = io_dis_uops_0_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_dis_uops_0_bits_rob_idx_0 = io_dis_uops_0_bits_rob_idx; // @[issue-unit-age-ordered.scala:22:7]
wire [3:0] io_dis_uops_0_bits_ldq_idx_0 = io_dis_uops_0_bits_ldq_idx; // @[issue-unit-age-ordered.scala:22:7]
wire [3:0] io_dis_uops_0_bits_stq_idx_0 = io_dis_uops_0_bits_stq_idx; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_dis_uops_0_bits_rxq_idx_0 = io_dis_uops_0_bits_rxq_idx; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_dis_uops_0_bits_pdst_0 = io_dis_uops_0_bits_pdst; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_dis_uops_0_bits_prs1_0 = io_dis_uops_0_bits_prs1; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_dis_uops_0_bits_prs2_0 = io_dis_uops_0_bits_prs2; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_dis_uops_0_bits_prs3_0 = io_dis_uops_0_bits_prs3; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_dis_uops_0_bits_ppred_0 = io_dis_uops_0_bits_ppred; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_prs1_busy_0 = io_dis_uops_0_bits_prs1_busy; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_prs2_busy_0 = io_dis_uops_0_bits_prs2_busy; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_prs3_busy_0 = io_dis_uops_0_bits_prs3_busy; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_ppred_busy_0 = io_dis_uops_0_bits_ppred_busy; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_dis_uops_0_bits_stale_pdst_0 = io_dis_uops_0_bits_stale_pdst; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_exception_0 = io_dis_uops_0_bits_exception; // @[issue-unit-age-ordered.scala:22:7]
wire [63:0] io_dis_uops_0_bits_exc_cause_0 = io_dis_uops_0_bits_exc_cause; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_dis_uops_0_bits_mem_cmd_0 = io_dis_uops_0_bits_mem_cmd; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_dis_uops_0_bits_mem_size_0 = io_dis_uops_0_bits_mem_size; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_mem_signed_0 = io_dis_uops_0_bits_mem_signed; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_uses_ldq_0 = io_dis_uops_0_bits_uses_ldq; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_uses_stq_0 = io_dis_uops_0_bits_uses_stq; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_is_unique_0 = io_dis_uops_0_bits_is_unique; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_flush_on_commit_0 = io_dis_uops_0_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_dis_uops_0_bits_csr_cmd_0 = io_dis_uops_0_bits_csr_cmd; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_ldst_is_rs1_0 = io_dis_uops_0_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_dis_uops_0_bits_ldst_0 = io_dis_uops_0_bits_ldst; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_dis_uops_0_bits_lrs1_0 = io_dis_uops_0_bits_lrs1; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_dis_uops_0_bits_lrs2_0 = io_dis_uops_0_bits_lrs2; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_dis_uops_0_bits_lrs3_0 = io_dis_uops_0_bits_lrs3; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_dis_uops_0_bits_dst_rtype_0 = io_dis_uops_0_bits_dst_rtype; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_dis_uops_0_bits_lrs1_rtype_0 = io_dis_uops_0_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_dis_uops_0_bits_lrs2_rtype_0 = io_dis_uops_0_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_frs3_en_0 = io_dis_uops_0_bits_frs3_en; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_fcn_dw_0 = io_dis_uops_0_bits_fcn_dw; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_dis_uops_0_bits_fcn_op_0 = io_dis_uops_0_bits_fcn_op; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_fp_val_0 = io_dis_uops_0_bits_fp_val; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_dis_uops_0_bits_fp_rm_0 = io_dis_uops_0_bits_fp_rm; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_dis_uops_0_bits_fp_typ_0 = io_dis_uops_0_bits_fp_typ; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_xcpt_pf_if_0 = io_dis_uops_0_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_xcpt_ae_if_0 = io_dis_uops_0_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_xcpt_ma_if_0 = io_dis_uops_0_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_bp_debug_if_0 = io_dis_uops_0_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_0_bits_bp_xcpt_if_0 = io_dis_uops_0_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_dis_uops_0_bits_debug_fsrc_0 = io_dis_uops_0_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_dis_uops_0_bits_debug_tsrc_0 = io_dis_uops_0_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_valid_0 = io_dis_uops_1_valid; // @[issue-unit-age-ordered.scala:22:7]
wire [31:0] io_dis_uops_1_bits_inst_0 = io_dis_uops_1_bits_inst; // @[issue-unit-age-ordered.scala:22:7]
wire [31:0] io_dis_uops_1_bits_debug_inst_0 = io_dis_uops_1_bits_debug_inst; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_is_rvc_0 = io_dis_uops_1_bits_is_rvc; // @[issue-unit-age-ordered.scala:22:7]
wire [39:0] io_dis_uops_1_bits_debug_pc_0 = io_dis_uops_1_bits_debug_pc; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_iq_type_0_0 = io_dis_uops_1_bits_iq_type_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_iq_type_1_0 = io_dis_uops_1_bits_iq_type_1; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_iq_type_2_0 = io_dis_uops_1_bits_iq_type_2; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_iq_type_3_0 = io_dis_uops_1_bits_iq_type_3; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_fu_code_0_0 = io_dis_uops_1_bits_fu_code_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_fu_code_1_0 = io_dis_uops_1_bits_fu_code_1; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_fu_code_2_0 = io_dis_uops_1_bits_fu_code_2; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_fu_code_3_0 = io_dis_uops_1_bits_fu_code_3; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_fu_code_4_0 = io_dis_uops_1_bits_fu_code_4; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_fu_code_5_0 = io_dis_uops_1_bits_fu_code_5; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_fu_code_6_0 = io_dis_uops_1_bits_fu_code_6; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_fu_code_7_0 = io_dis_uops_1_bits_fu_code_7; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_fu_code_8_0 = io_dis_uops_1_bits_fu_code_8; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_fu_code_9_0 = io_dis_uops_1_bits_fu_code_9; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_iw_issued_0 = io_dis_uops_1_bits_iw_issued; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_iw_issued_partial_agen_0 = io_dis_uops_1_bits_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_iw_issued_partial_dgen_0 = io_dis_uops_1_bits_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_dis_uops_1_bits_iw_p1_speculative_child_0 = io_dis_uops_1_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_dis_uops_1_bits_iw_p2_speculative_child_0 = io_dis_uops_1_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_iw_p1_bypass_hint_0 = io_dis_uops_1_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_iw_p2_bypass_hint_0 = io_dis_uops_1_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_iw_p3_bypass_hint_0 = io_dis_uops_1_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_dis_uops_1_bits_dis_col_sel_0 = io_dis_uops_1_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7]
wire [11:0] io_dis_uops_1_bits_br_mask_0 = io_dis_uops_1_bits_br_mask; // @[issue-unit-age-ordered.scala:22:7]
wire [3:0] io_dis_uops_1_bits_br_tag_0 = io_dis_uops_1_bits_br_tag; // @[issue-unit-age-ordered.scala:22:7]
wire [3:0] io_dis_uops_1_bits_br_type_0 = io_dis_uops_1_bits_br_type; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_is_sfb_0 = io_dis_uops_1_bits_is_sfb; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_is_fence_0 = io_dis_uops_1_bits_is_fence; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_is_fencei_0 = io_dis_uops_1_bits_is_fencei; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_is_sfence_0 = io_dis_uops_1_bits_is_sfence; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_is_amo_0 = io_dis_uops_1_bits_is_amo; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_is_eret_0 = io_dis_uops_1_bits_is_eret; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_is_sys_pc2epc_0 = io_dis_uops_1_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_is_rocc_0 = io_dis_uops_1_bits_is_rocc; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_is_mov_0 = io_dis_uops_1_bits_is_mov; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_dis_uops_1_bits_ftq_idx_0 = io_dis_uops_1_bits_ftq_idx; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_edge_inst_0 = io_dis_uops_1_bits_edge_inst; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_dis_uops_1_bits_pc_lob_0 = io_dis_uops_1_bits_pc_lob; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_taken_0 = io_dis_uops_1_bits_taken; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_imm_rename_0 = io_dis_uops_1_bits_imm_rename; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_dis_uops_1_bits_imm_sel_0 = io_dis_uops_1_bits_imm_sel; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_dis_uops_1_bits_pimm_0 = io_dis_uops_1_bits_pimm; // @[issue-unit-age-ordered.scala:22:7]
wire [19:0] io_dis_uops_1_bits_imm_packed_0 = io_dis_uops_1_bits_imm_packed; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_dis_uops_1_bits_op1_sel_0 = io_dis_uops_1_bits_op1_sel; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_dis_uops_1_bits_op2_sel_0 = io_dis_uops_1_bits_op2_sel; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_fp_ctrl_ldst_0 = io_dis_uops_1_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_fp_ctrl_wen_0 = io_dis_uops_1_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_fp_ctrl_ren1_0 = io_dis_uops_1_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_fp_ctrl_ren2_0 = io_dis_uops_1_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_fp_ctrl_ren3_0 = io_dis_uops_1_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_fp_ctrl_swap12_0 = io_dis_uops_1_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_fp_ctrl_swap23_0 = io_dis_uops_1_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_dis_uops_1_bits_fp_ctrl_typeTagIn_0 = io_dis_uops_1_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_dis_uops_1_bits_fp_ctrl_typeTagOut_0 = io_dis_uops_1_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_fp_ctrl_fromint_0 = io_dis_uops_1_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_fp_ctrl_toint_0 = io_dis_uops_1_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_fp_ctrl_fastpipe_0 = io_dis_uops_1_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_fp_ctrl_fma_0 = io_dis_uops_1_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_fp_ctrl_div_0 = io_dis_uops_1_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_fp_ctrl_sqrt_0 = io_dis_uops_1_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_fp_ctrl_wflags_0 = io_dis_uops_1_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_fp_ctrl_vec_0 = io_dis_uops_1_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_dis_uops_1_bits_rob_idx_0 = io_dis_uops_1_bits_rob_idx; // @[issue-unit-age-ordered.scala:22:7]
wire [3:0] io_dis_uops_1_bits_ldq_idx_0 = io_dis_uops_1_bits_ldq_idx; // @[issue-unit-age-ordered.scala:22:7]
wire [3:0] io_dis_uops_1_bits_stq_idx_0 = io_dis_uops_1_bits_stq_idx; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_dis_uops_1_bits_rxq_idx_0 = io_dis_uops_1_bits_rxq_idx; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_dis_uops_1_bits_pdst_0 = io_dis_uops_1_bits_pdst; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_dis_uops_1_bits_prs1_0 = io_dis_uops_1_bits_prs1; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_dis_uops_1_bits_prs2_0 = io_dis_uops_1_bits_prs2; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_dis_uops_1_bits_prs3_0 = io_dis_uops_1_bits_prs3; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_dis_uops_1_bits_ppred_0 = io_dis_uops_1_bits_ppred; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_prs1_busy_0 = io_dis_uops_1_bits_prs1_busy; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_prs2_busy_0 = io_dis_uops_1_bits_prs2_busy; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_prs3_busy_0 = io_dis_uops_1_bits_prs3_busy; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_ppred_busy_0 = io_dis_uops_1_bits_ppred_busy; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_dis_uops_1_bits_stale_pdst_0 = io_dis_uops_1_bits_stale_pdst; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_exception_0 = io_dis_uops_1_bits_exception; // @[issue-unit-age-ordered.scala:22:7]
wire [63:0] io_dis_uops_1_bits_exc_cause_0 = io_dis_uops_1_bits_exc_cause; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_dis_uops_1_bits_mem_cmd_0 = io_dis_uops_1_bits_mem_cmd; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_dis_uops_1_bits_mem_size_0 = io_dis_uops_1_bits_mem_size; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_mem_signed_0 = io_dis_uops_1_bits_mem_signed; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_uses_ldq_0 = io_dis_uops_1_bits_uses_ldq; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_uses_stq_0 = io_dis_uops_1_bits_uses_stq; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_is_unique_0 = io_dis_uops_1_bits_is_unique; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_flush_on_commit_0 = io_dis_uops_1_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_dis_uops_1_bits_csr_cmd_0 = io_dis_uops_1_bits_csr_cmd; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_ldst_is_rs1_0 = io_dis_uops_1_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_dis_uops_1_bits_ldst_0 = io_dis_uops_1_bits_ldst; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_dis_uops_1_bits_lrs1_0 = io_dis_uops_1_bits_lrs1; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_dis_uops_1_bits_lrs2_0 = io_dis_uops_1_bits_lrs2; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_dis_uops_1_bits_lrs3_0 = io_dis_uops_1_bits_lrs3; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_dis_uops_1_bits_dst_rtype_0 = io_dis_uops_1_bits_dst_rtype; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_dis_uops_1_bits_lrs1_rtype_0 = io_dis_uops_1_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_dis_uops_1_bits_lrs2_rtype_0 = io_dis_uops_1_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_frs3_en_0 = io_dis_uops_1_bits_frs3_en; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_fcn_dw_0 = io_dis_uops_1_bits_fcn_dw; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_dis_uops_1_bits_fcn_op_0 = io_dis_uops_1_bits_fcn_op; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_fp_val_0 = io_dis_uops_1_bits_fp_val; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_dis_uops_1_bits_fp_rm_0 = io_dis_uops_1_bits_fp_rm; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_dis_uops_1_bits_fp_typ_0 = io_dis_uops_1_bits_fp_typ; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_xcpt_pf_if_0 = io_dis_uops_1_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_xcpt_ae_if_0 = io_dis_uops_1_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_xcpt_ma_if_0 = io_dis_uops_1_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_bp_debug_if_0 = io_dis_uops_1_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_bits_bp_xcpt_if_0 = io_dis_uops_1_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_dis_uops_1_bits_debug_fsrc_0 = io_dis_uops_1_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_dis_uops_1_bits_debug_tsrc_0 = io_dis_uops_1_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-unit-age-ordered.scala:22:7]
wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-unit-age-ordered.scala:22:7]
wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7]
wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7]
wire [11:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-unit-age-ordered.scala:22:7]
wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7]
wire [3:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7]
wire [3:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-unit-age-ordered.scala:22:7]
wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-unit-age-ordered.scala:22:7]
wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-unit-age-ordered.scala:22:7]
wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7]
wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7]
wire [11:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-unit-age-ordered.scala:22:7]
wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7]
wire [3:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7]
wire [3:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-unit-age-ordered.scala:22:7]
wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-unit-age-ordered.scala:22:7]
wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-unit-age-ordered.scala:22:7]
wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7]
wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7]
wire [11:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-unit-age-ordered.scala:22:7]
wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7]
wire [3:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7]
wire [3:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-unit-age-ordered.scala:22:7]
wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-unit-age-ordered.scala:22:7]
wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-unit-age-ordered.scala:22:7]
wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7]
wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7]
wire [11:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-unit-age-ordered.scala:22:7]
wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7]
wire [3:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7]
wire [3:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-unit-age-ordered.scala:22:7]
wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7]
wire io_pred_wakeup_port_valid_0 = io_pred_wakeup_port_valid; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_pred_wakeup_port_bits_0 = io_pred_wakeup_port_bits; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-unit-age-ordered.scala:22:7]
wire [11:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-unit-age-ordered.scala:22:7]
wire [11:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-unit-age-ordered.scala:22:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-unit-age-ordered.scala:22:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7]
wire [11:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7]
wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-unit-age-ordered.scala:22:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7]
wire [3:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7]
wire [3:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-unit-age-ordered.scala:22:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-unit-age-ordered.scala:22:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-unit-age-ordered.scala:22:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-unit-age-ordered.scala:22:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-unit-age-ordered.scala:22:7]
wire io_flush_pipeline_0 = io_flush_pipeline; // @[issue-unit-age-ordered.scala:22:7]
wire io_squash_grant_0 = io_squash_grant; // @[issue-unit-age-ordered.scala:22:7]
wire [63:0] io_tsc_reg_0 = io_tsc_reg; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:22:7]
wire io_fu_types_0_1 = 1'h0; // @[issue-unit-age-ordered.scala:22:7]
wire io_fu_types_0_2 = 1'h0; // @[issue-unit-age-ordered.scala:22:7]
wire io_fu_types_0_3 = 1'h0; // @[issue-unit-age-ordered.scala:22:7]
wire io_fu_types_0_4 = 1'h0; // @[issue-unit-age-ordered.scala:22:7]
wire io_fu_types_0_5 = 1'h0; // @[issue-unit-age-ordered.scala:22:7]
wire io_fu_types_0_6 = 1'h0; // @[issue-unit-age-ordered.scala:22:7]
wire io_fu_types_0_7 = 1'h0; // @[issue-unit-age-ordered.scala:22:7]
wire io_fu_types_0_8 = 1'h0; // @[issue-unit-age-ordered.scala:22:7]
wire io_fu_types_0_9 = 1'h0; // @[issue-unit-age-ordered.scala:22:7]
wire io_fu_types_1_1 = 1'h0; // @[issue-unit-age-ordered.scala:22:7]
wire io_fu_types_1_2 = 1'h0; // @[issue-unit-age-ordered.scala:22:7]
wire io_fu_types_1_3 = 1'h0; // @[issue-unit-age-ordered.scala:22:7]
wire io_fu_types_1_4 = 1'h0; // @[issue-unit-age-ordered.scala:22:7]
wire io_fu_types_1_5 = 1'h0; // @[issue-unit-age-ordered.scala:22:7]
wire io_fu_types_1_6 = 1'h0; // @[issue-unit-age-ordered.scala:22:7]
wire io_fu_types_1_7 = 1'h0; // @[issue-unit-age-ordered.scala:22:7]
wire io_fu_types_1_8 = 1'h0; // @[issue-unit-age-ordered.scala:22:7]
wire io_fu_types_1_9 = 1'h0; // @[issue-unit-age-ordered.scala:22:7]
wire prs1_rebusys_1 = 1'h0; // @[issue-unit-age-ordered.scala:50:95]
wire prs1_rebusys_2 = 1'h0; // @[issue-unit-age-ordered.scala:50:95]
wire prs1_rebusys_3 = 1'h0; // @[issue-unit-age-ordered.scala:50:95]
wire prs2_rebusys_1 = 1'h0; // @[issue-unit-age-ordered.scala:51:95]
wire prs2_rebusys_2 = 1'h0; // @[issue-unit-age-ordered.scala:51:95]
wire prs2_rebusys_3 = 1'h0; // @[issue-unit-age-ordered.scala:51:95]
wire prs1_rebusys_1_1 = 1'h0; // @[issue-unit-age-ordered.scala:50:95]
wire prs1_rebusys_2_1 = 1'h0; // @[issue-unit-age-ordered.scala:50:95]
wire prs1_rebusys_3_1 = 1'h0; // @[issue-unit-age-ordered.scala:50:95]
wire prs2_rebusys_1_1 = 1'h0; // @[issue-unit-age-ordered.scala:51:95]
wire prs2_rebusys_2_1 = 1'h0; // @[issue-unit-age-ordered.scala:51:95]
wire prs2_rebusys_3_1 = 1'h0; // @[issue-unit-age-ordered.scala:51:95]
wire issue_slots_0_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_clear = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_iw_issued = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28]
wire _shamts_oh_1_T_2 = 1'h0; // @[issue-unit-age-ordered.scala:165:28]
wire _issue_slots_0_clear_T = 1'h0; // @[issue-unit-age-ordered.scala:199:49]
wire iss_uops_0_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:241:22]
wire _fu_code_match_T_1 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_2 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_3 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_4 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_5 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_6 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_7 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_8 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_9 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_19 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_20 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_21 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_22 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_23 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_24 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_25 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_26 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_27 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_37 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_38 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_39 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_40 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_41 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_42 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_43 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_44 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_45 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_55 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_56 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_57 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_58 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_59 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_60 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_61 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_62 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_63 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_73 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_74 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_75 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_76 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_77 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_78 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_79 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_80 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_81 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_91 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_92 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_93 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_94 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_95 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_96 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_97 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_98 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_99 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_109 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_110 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_111 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_112 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_113 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_114 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_115 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_116 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_117 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_127 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_128 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_129 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_130 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_131 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_132 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_133 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_134 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_135 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_145 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_146 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_147 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_148 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_149 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_150 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_151 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_152 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_153 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_163 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_164 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_165 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_166 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_167 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_168 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_169 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_170 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_171 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_181 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_182 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_183 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_184 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_185 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_186 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_187 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_188 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_189 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_199 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_200 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_201 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_202 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_203 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_204 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_205 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_206 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_207 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_217 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_218 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_219 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_220 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_221 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_222 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_223 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_224 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_225 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_235 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_236 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_237 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_238 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_239 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_240 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_241 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_242 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_243 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_253 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_254 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_255 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_256 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_257 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_258 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_259 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_260 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_261 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_271 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_272 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_273 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_274 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_275 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_276 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_277 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_278 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_279 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_289 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_290 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_291 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_292 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_293 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_294 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_295 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_296 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_297 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_307 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_308 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_309 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_310 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_311 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_312 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_313 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_314 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_315 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_325 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_326 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_327 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_328 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_329 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_330 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_331 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_332 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_333 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_343 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_344 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_345 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_346 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_347 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_348 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_349 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_350 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_351 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_361 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_362 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_363 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_364 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_365 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_366 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_367 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_368 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_369 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_379 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_380 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_381 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_382 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_383 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_384 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_385 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_386 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_387 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_397 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_398 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_399 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_400 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_401 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_402 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_403 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_404 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_405 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_415 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_416 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_417 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_418 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_419 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_420 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_421 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_422 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_423 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_433 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_434 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_435 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_436 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_437 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_438 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_439 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_440 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_441 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_451 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_452 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_453 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_454 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_455 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_456 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_457 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_458 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_459 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_469 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_470 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_471 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_472 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_473 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_474 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_475 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_476 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_477 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_487 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_488 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_489 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_490 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_491 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_492 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_493 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_494 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_495 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_505 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_506 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_507 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_508 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_509 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_510 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_511 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_512 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_513 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_523 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_524 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_525 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_526 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_527 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_528 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_529 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_530 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_531 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_541 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_542 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_543 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_544 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_545 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_546 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_547 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_548 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_549 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_559 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_560 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_561 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_562 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_563 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_564 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_565 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_566 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_567 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_577 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_578 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_579 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_580 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_581 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_582 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_583 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_584 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_585 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_595 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_596 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_597 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_598 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_599 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_600 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_601 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_602 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_603 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_613 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_614 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_615 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_616 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_617 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_618 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_619 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_620 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_621 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_631 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_632 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_633 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_634 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_635 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_636 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_637 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_638 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_639 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_649 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_650 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_651 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_652 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_653 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_654 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_655 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_656 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_657 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_667 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_668 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_669 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_670 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_671 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_672 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_673 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_674 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_675 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_685 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_686 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_687 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_688 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_689 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_690 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_691 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_692 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_693 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_703 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_704 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_705 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_706 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_707 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_708 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_709 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_710 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire _fu_code_match_T_711 = 1'h0; // @[issue-unit-age-ordered.scala:253:25]
wire [1:0] io_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] issue_slots_0_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_1_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_2_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_3_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_4_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_5_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_6_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_7_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_8_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_9_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_10_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_11_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_12_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_13_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_14_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_15_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_16_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_17_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_18_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_19_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] shamts_oh_0 = 2'h0; // @[issue-unit-age-ordered.scala:158:23]
wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:22:7]
wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:22:7]
wire io_fu_types_0_0 = 1'h1; // @[issue-unit-age-ordered.scala:22:7]
wire io_fu_types_1_0 = 1'h1; // @[issue-unit-age-ordered.scala:22:7]
wire issue_slots_0_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28]
wire _shamts_oh_1_T = 1'h1; // @[issue-unit-age-ordered.scala:163:21]
wire _shamts_oh_1_T_3 = 1'h1; // @[issue-unit-age-ordered.scala:165:19]
wire [1:0] io_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] issue_slots_0_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_1_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_2_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_3_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_4_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_5_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_6_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_7_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_8_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_9_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_10_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_11_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_12_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_13_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_14_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_15_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_16_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_17_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_18_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_19_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] io_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] issue_slots_0_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_1_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_2_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_3_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_4_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_5_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_6_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_7_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_8_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_9_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_10_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_11_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_12_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_13_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_14_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_15_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_16_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_17_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_18_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_19_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] _shamts_oh_1_next_T = 3'h0; // @[issue-unit-age-ordered.scala:166:26]
wire [31:0] iss_uops_0_bits_inst; // @[issue-unit-age-ordered.scala:241:22]
wire [31:0] iss_uops_0_bits_debug_inst; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_is_rvc; // @[issue-unit-age-ordered.scala:241:22]
wire [39:0] iss_uops_0_bits_debug_pc; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_iq_type_0; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_iq_type_1; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_iq_type_2; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_iq_type_3; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_fu_code_0; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_fu_code_1; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_fu_code_2; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_fu_code_3; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_fu_code_4; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_fu_code_5; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_fu_code_6; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_fu_code_7; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_fu_code_8; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_fu_code_9; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_iw_issued; // @[issue-unit-age-ordered.scala:241:22]
wire [1:0] iss_uops_0_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:241:22]
wire [1:0] iss_uops_0_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:241:22]
wire [1:0] iss_uops_0_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:241:22]
wire [11:0] iss_uops_0_bits_br_mask; // @[issue-unit-age-ordered.scala:241:22]
wire [3:0] iss_uops_0_bits_br_tag; // @[issue-unit-age-ordered.scala:241:22]
wire [3:0] iss_uops_0_bits_br_type; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_is_sfb; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_is_fence; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_is_fencei; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_is_sfence; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_is_amo; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_is_eret; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_is_rocc; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_is_mov; // @[issue-unit-age-ordered.scala:241:22]
wire [4:0] iss_uops_0_bits_ftq_idx; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_edge_inst; // @[issue-unit-age-ordered.scala:241:22]
wire [5:0] iss_uops_0_bits_pc_lob; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_taken; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_imm_rename; // @[issue-unit-age-ordered.scala:241:22]
wire [2:0] iss_uops_0_bits_imm_sel; // @[issue-unit-age-ordered.scala:241:22]
wire [4:0] iss_uops_0_bits_pimm; // @[issue-unit-age-ordered.scala:241:22]
wire [19:0] iss_uops_0_bits_imm_packed; // @[issue-unit-age-ordered.scala:241:22]
wire [1:0] iss_uops_0_bits_op1_sel; // @[issue-unit-age-ordered.scala:241:22]
wire [2:0] iss_uops_0_bits_op2_sel; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:241:22]
wire [1:0] iss_uops_0_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:241:22]
wire [1:0] iss_uops_0_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:241:22]
wire [5:0] iss_uops_0_bits_rob_idx; // @[issue-unit-age-ordered.scala:241:22]
wire [3:0] iss_uops_0_bits_ldq_idx; // @[issue-unit-age-ordered.scala:241:22]
wire [3:0] iss_uops_0_bits_stq_idx; // @[issue-unit-age-ordered.scala:241:22]
wire [1:0] iss_uops_0_bits_rxq_idx; // @[issue-unit-age-ordered.scala:241:22]
wire [6:0] iss_uops_0_bits_pdst; // @[issue-unit-age-ordered.scala:241:22]
wire [6:0] iss_uops_0_bits_prs1; // @[issue-unit-age-ordered.scala:241:22]
wire [6:0] iss_uops_0_bits_prs2; // @[issue-unit-age-ordered.scala:241:22]
wire [6:0] iss_uops_0_bits_prs3; // @[issue-unit-age-ordered.scala:241:22]
wire [4:0] iss_uops_0_bits_ppred; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_prs1_busy; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_prs2_busy; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_prs3_busy; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_ppred_busy; // @[issue-unit-age-ordered.scala:241:22]
wire [6:0] iss_uops_0_bits_stale_pdst; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_exception; // @[issue-unit-age-ordered.scala:241:22]
wire [63:0] iss_uops_0_bits_exc_cause; // @[issue-unit-age-ordered.scala:241:22]
wire [4:0] iss_uops_0_bits_mem_cmd; // @[issue-unit-age-ordered.scala:241:22]
wire [1:0] iss_uops_0_bits_mem_size; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_mem_signed; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_uses_ldq; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_uses_stq; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_is_unique; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:241:22]
wire [2:0] iss_uops_0_bits_csr_cmd; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:241:22]
wire [5:0] iss_uops_0_bits_ldst; // @[issue-unit-age-ordered.scala:241:22]
wire [5:0] iss_uops_0_bits_lrs1; // @[issue-unit-age-ordered.scala:241:22]
wire [5:0] iss_uops_0_bits_lrs2; // @[issue-unit-age-ordered.scala:241:22]
wire [5:0] iss_uops_0_bits_lrs3; // @[issue-unit-age-ordered.scala:241:22]
wire [1:0] iss_uops_0_bits_dst_rtype; // @[issue-unit-age-ordered.scala:241:22]
wire [1:0] iss_uops_0_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:241:22]
wire [1:0] iss_uops_0_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_frs3_en; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_fcn_dw; // @[issue-unit-age-ordered.scala:241:22]
wire [4:0] iss_uops_0_bits_fcn_op; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_fp_val; // @[issue-unit-age-ordered.scala:241:22]
wire [2:0] iss_uops_0_bits_fp_rm; // @[issue-unit-age-ordered.scala:241:22]
wire [1:0] iss_uops_0_bits_fp_typ; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_0_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:241:22]
wire [2:0] iss_uops_0_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:241:22]
wire [2:0] iss_uops_0_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:241:22]
wire [31:0] iss_uops_1_bits_inst; // @[issue-unit-age-ordered.scala:241:22]
wire [31:0] iss_uops_1_bits_debug_inst; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_is_rvc; // @[issue-unit-age-ordered.scala:241:22]
wire [39:0] iss_uops_1_bits_debug_pc; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_iq_type_0; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_iq_type_1; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_iq_type_2; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_iq_type_3; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_fu_code_0; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_fu_code_1; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_fu_code_2; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_fu_code_3; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_fu_code_4; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_fu_code_5; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_fu_code_6; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_fu_code_7; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_fu_code_8; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_fu_code_9; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_iw_issued; // @[issue-unit-age-ordered.scala:241:22]
wire [1:0] iss_uops_1_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:241:22]
wire [1:0] iss_uops_1_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:241:22]
wire [1:0] iss_uops_1_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:241:22]
wire [11:0] iss_uops_1_bits_br_mask; // @[issue-unit-age-ordered.scala:241:22]
wire [3:0] iss_uops_1_bits_br_tag; // @[issue-unit-age-ordered.scala:241:22]
wire [3:0] iss_uops_1_bits_br_type; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_is_sfb; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_is_fence; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_is_fencei; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_is_sfence; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_is_amo; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_is_eret; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_is_rocc; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_is_mov; // @[issue-unit-age-ordered.scala:241:22]
wire [4:0] iss_uops_1_bits_ftq_idx; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_edge_inst; // @[issue-unit-age-ordered.scala:241:22]
wire [5:0] iss_uops_1_bits_pc_lob; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_taken; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_imm_rename; // @[issue-unit-age-ordered.scala:241:22]
wire [2:0] iss_uops_1_bits_imm_sel; // @[issue-unit-age-ordered.scala:241:22]
wire [4:0] iss_uops_1_bits_pimm; // @[issue-unit-age-ordered.scala:241:22]
wire [19:0] iss_uops_1_bits_imm_packed; // @[issue-unit-age-ordered.scala:241:22]
wire [1:0] iss_uops_1_bits_op1_sel; // @[issue-unit-age-ordered.scala:241:22]
wire [2:0] iss_uops_1_bits_op2_sel; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:241:22]
wire [1:0] iss_uops_1_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:241:22]
wire [1:0] iss_uops_1_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:241:22]
wire [5:0] iss_uops_1_bits_rob_idx; // @[issue-unit-age-ordered.scala:241:22]
wire [3:0] iss_uops_1_bits_ldq_idx; // @[issue-unit-age-ordered.scala:241:22]
wire [3:0] iss_uops_1_bits_stq_idx; // @[issue-unit-age-ordered.scala:241:22]
wire [1:0] iss_uops_1_bits_rxq_idx; // @[issue-unit-age-ordered.scala:241:22]
wire [6:0] iss_uops_1_bits_pdst; // @[issue-unit-age-ordered.scala:241:22]
wire [6:0] iss_uops_1_bits_prs1; // @[issue-unit-age-ordered.scala:241:22]
wire [6:0] iss_uops_1_bits_prs2; // @[issue-unit-age-ordered.scala:241:22]
wire [6:0] iss_uops_1_bits_prs3; // @[issue-unit-age-ordered.scala:241:22]
wire [4:0] iss_uops_1_bits_ppred; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_prs1_busy; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_prs2_busy; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_prs3_busy; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_ppred_busy; // @[issue-unit-age-ordered.scala:241:22]
wire [6:0] iss_uops_1_bits_stale_pdst; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_exception; // @[issue-unit-age-ordered.scala:241:22]
wire [63:0] iss_uops_1_bits_exc_cause; // @[issue-unit-age-ordered.scala:241:22]
wire [4:0] iss_uops_1_bits_mem_cmd; // @[issue-unit-age-ordered.scala:241:22]
wire [1:0] iss_uops_1_bits_mem_size; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_mem_signed; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_uses_ldq; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_uses_stq; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_is_unique; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:241:22]
wire [2:0] iss_uops_1_bits_csr_cmd; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:241:22]
wire [5:0] iss_uops_1_bits_ldst; // @[issue-unit-age-ordered.scala:241:22]
wire [5:0] iss_uops_1_bits_lrs1; // @[issue-unit-age-ordered.scala:241:22]
wire [5:0] iss_uops_1_bits_lrs2; // @[issue-unit-age-ordered.scala:241:22]
wire [5:0] iss_uops_1_bits_lrs3; // @[issue-unit-age-ordered.scala:241:22]
wire [1:0] iss_uops_1_bits_dst_rtype; // @[issue-unit-age-ordered.scala:241:22]
wire [1:0] iss_uops_1_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:241:22]
wire [1:0] iss_uops_1_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_frs3_en; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_fcn_dw; // @[issue-unit-age-ordered.scala:241:22]
wire [4:0] iss_uops_1_bits_fcn_op; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_fp_val; // @[issue-unit-age-ordered.scala:241:22]
wire [2:0] iss_uops_1_bits_fp_rm; // @[issue-unit-age-ordered.scala:241:22]
wire [1:0] iss_uops_1_bits_fp_typ; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:241:22]
wire iss_uops_1_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:241:22]
wire [2:0] iss_uops_1_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:241:22]
wire [2:0] iss_uops_1_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:241:22]
wire issue_slots_0_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_0_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_1_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_2_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_3_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_4_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_5_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_6_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_7_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_8_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_9_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_10_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_11_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_12_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_13_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_14_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_15_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_16_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_17_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_18_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_19_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_0_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_1_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_2_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_3_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_4_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_5_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_6_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_7_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_8_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_9_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_10_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_11_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_12_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_13_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_14_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_15_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_16_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_17_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_18_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_19_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_0_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_1_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_2_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_3_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_4_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_5_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_6_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_7_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_8_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_9_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_10_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_11_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_12_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_13_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_14_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_15_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_16_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_17_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_18_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_19_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_0_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_1_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_2_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_3_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_4_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_5_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_6_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_7_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_8_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_9_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_10_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_11_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_12_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_13_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_14_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_15_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_16_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_17_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_18_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_19_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_0_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_1_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_2_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_3_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_4_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_5_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_6_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_7_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_8_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_9_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_10_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_11_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_12_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_13_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_14_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_15_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_16_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_17_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_18_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_19_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_0_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_1_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_2_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_3_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_4_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_5_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_6_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_7_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_8_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_9_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_10_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_11_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_12_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_13_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_14_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_15_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_16_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_17_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_18_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_19_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_16_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_17_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_18_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_19_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_12_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_13_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_14_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_15_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_16_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_17_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_18_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_19_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_16_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_17_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_18_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_19_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_16_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_17_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_18_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_19_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_0_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_1_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_2_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_3_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_4_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_5_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_6_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_7_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_8_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_9_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_10_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_11_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_12_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_13_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_14_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_15_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_16_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_17_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_18_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_19_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_16_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_17_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_18_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_19_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_12_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_13_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_14_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_15_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_16_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_17_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_18_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_19_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_0_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_1_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_2_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_3_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_4_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_5_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_6_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_7_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_8_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_9_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_10_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_11_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_12_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_13_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_14_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_15_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_16_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_17_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_18_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_19_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_0_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_1_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_2_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_3_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_4_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_5_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_6_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_7_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_8_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_9_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_10_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_11_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_12_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_13_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_14_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_15_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_16_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_17_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_18_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_19_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_12_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_13_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_14_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_15_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_16_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_17_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_18_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_19_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_12_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_13_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_14_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_15_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_16_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_17_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_18_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_19_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_12_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_13_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_14_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_15_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_16_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_17_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_18_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_19_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_12_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_13_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_14_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_15_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_16_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_17_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_18_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_19_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_16_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_17_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_18_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_19_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_12_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_13_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_14_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_15_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_16_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_17_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_18_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_19_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_0_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_1_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_2_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_3_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_4_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_5_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_6_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_7_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_8_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_9_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_10_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_11_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_12_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_13_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_14_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_15_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_16_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_17_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_18_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_19_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_16_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_17_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_18_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_19_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_16_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_17_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_18_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_19_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_12_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_13_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_14_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_15_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_16_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_17_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_18_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_19_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_12_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_13_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_14_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_15_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_16_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_17_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_18_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_19_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_12_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_13_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_14_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_15_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_16_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_17_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_18_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_19_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_12_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_13_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_14_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_15_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_16_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_17_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_18_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_19_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_16_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_17_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_18_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_19_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_16_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_17_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_18_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_19_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_16_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_17_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_18_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_19_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_16_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_17_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_18_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_19_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_0_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_1_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_2_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_3_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_4_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_5_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_6_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_7_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_8_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_9_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_10_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_11_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_12_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_13_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_14_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_15_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_16_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_17_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_18_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_19_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_0_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_1_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_2_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_3_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_4_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_5_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_6_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_7_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_8_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_9_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_10_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_11_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_12_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_13_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_14_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_15_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_16_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_17_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_18_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_19_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_0_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_1_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_2_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_3_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_4_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_5_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_6_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_7_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_8_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_9_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_10_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_11_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_12_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_13_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_14_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_15_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_16_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_17_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_18_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_19_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_0_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_1_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_2_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_3_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_4_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_5_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_6_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_7_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_8_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_9_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_10_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_11_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_12_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_13_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_14_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_15_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_16_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_17_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_18_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_19_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_0_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_1_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_2_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_3_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_4_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_5_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_6_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_7_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_8_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_9_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_10_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_11_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_12_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_13_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_14_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_15_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_16_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_17_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_18_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_19_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_0_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_1_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_2_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_3_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_4_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_5_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_6_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_7_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_8_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_9_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_10_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_11_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_12_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_13_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_14_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_15_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_16_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_17_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_18_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_19_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_16_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_17_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_18_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_19_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_12_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_13_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_14_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_15_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_16_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_17_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_18_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_19_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_16_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_17_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_18_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_19_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_16_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_17_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_18_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_19_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_0_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_1_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_2_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_3_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_4_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_5_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_6_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_7_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_8_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_9_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_10_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_11_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_12_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_13_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_14_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_15_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_16_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_17_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_18_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_19_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_16_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_17_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_18_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_19_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_12_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_13_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_14_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_15_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_16_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_17_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_18_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_19_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_0_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_1_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_2_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_3_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_4_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_5_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_6_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_7_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_8_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_9_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_10_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_11_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_12_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_13_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_14_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_15_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_16_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_17_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_18_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_19_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_0_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_1_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_2_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_3_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_4_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_5_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_6_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_7_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_8_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_9_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_10_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_11_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_12_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_13_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_14_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_15_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_16_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_17_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_18_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_19_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_12_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_13_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_14_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_15_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_16_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_17_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_18_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_19_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_12_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_13_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_14_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_15_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_16_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_17_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_18_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_19_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_12_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_13_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_14_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_15_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_16_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_17_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_18_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_19_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_12_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_13_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_14_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_15_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_16_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_17_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_18_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_19_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_16_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_17_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_18_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_19_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_12_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_13_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_14_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_15_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_16_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_17_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_18_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_19_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_0_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_1_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_2_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_3_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_4_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_5_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_6_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_7_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_8_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_9_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_10_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_11_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_12_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_13_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_14_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_15_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_16_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_17_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_18_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_19_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_16_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_17_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_18_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_19_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_16_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_17_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_18_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_19_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_12_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_13_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_14_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_15_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_16_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_17_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_18_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_19_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_12_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_13_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_14_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_15_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_16_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_17_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_18_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_19_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_12_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_13_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_14_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_15_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_16_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_17_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_18_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_19_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_12_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_13_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_14_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_15_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_16_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_17_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_18_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_19_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_16_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_17_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_18_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_19_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_16_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_17_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_18_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_19_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_16_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_17_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_18_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_19_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_16_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_17_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_18_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_19_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_0_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_1_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_2_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_3_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_4_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_5_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_6_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_7_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_8_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_9_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_10_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_11_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_12_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_13_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_14_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_15_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_16_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_17_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_18_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_19_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_0_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_1_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_2_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_3_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_4_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_5_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_6_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_7_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_8_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_9_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_10_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_11_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_12_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_13_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_14_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_15_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_16_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_17_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_18_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_19_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_0_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_1_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_2_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_3_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_4_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_5_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_6_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_7_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_8_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_9_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_10_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_11_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_12_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_13_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_14_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_15_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_16_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_17_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_18_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_19_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_0_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_1_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_2_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_3_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_4_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_5_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_6_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_7_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_8_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_9_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_10_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_11_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_12_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_13_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_14_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_15_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_16_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_17_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_18_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_19_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_0_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_1_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_2_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_3_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_4_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_5_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_6_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_7_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_8_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_9_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_10_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_11_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_12_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_13_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_14_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_15_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_16_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_17_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_18_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_19_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_0_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_1_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_2_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_3_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_4_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_5_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_6_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_7_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_8_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_9_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_10_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_11_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_12_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_13_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_14_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_15_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_16_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_17_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_18_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_19_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_0_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_1_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_2_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_3_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_4_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_5_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_6_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_7_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_8_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_9_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_10_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_11_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_12_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_13_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_14_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_15_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_16_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_17_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_18_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_19_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_0_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_1_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_2_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_3_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_4_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_5_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_6_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_7_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_8_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_9_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_10_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_11_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_12_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_13_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_14_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_15_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_16_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_17_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_18_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_19_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_12_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_13_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_14_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_15_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_16_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_17_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_18_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_19_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_0_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_1_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_2_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_3_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_4_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_5_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_6_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_7_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_8_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_9_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_10_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_11_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_12_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_13_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_14_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_15_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_16_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_17_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_18_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_19_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_0_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_1_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_2_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_3_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_4_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_5_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_6_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_7_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_8_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_9_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_10_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_11_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_12_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_13_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_14_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_15_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_16_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_17_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_18_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_19_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_12_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_13_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_14_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_15_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_16_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_17_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_18_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_19_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_0_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_1_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_2_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_3_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_4_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_5_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_6_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_7_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_8_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_9_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_10_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_11_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_12_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_13_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_14_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_15_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_16_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_17_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_18_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_19_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_0_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_1_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_2_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_3_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_4_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_5_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_6_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_7_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_8_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_9_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_10_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_11_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_12_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_13_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_14_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_15_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_16_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_17_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_18_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_19_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_0_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_1_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_2_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_3_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_4_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_5_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_6_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_7_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_8_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_9_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_10_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_11_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_12_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_13_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_14_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_15_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_16_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_17_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_18_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_19_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_0_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_1_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_2_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_3_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_4_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_5_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_6_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_7_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_8_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_9_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_10_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_11_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_12_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_13_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_14_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_15_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_16_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_17_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_18_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_19_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_0_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_1_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_2_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_3_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_4_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_5_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_6_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_7_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_8_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_9_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_10_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_11_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_12_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_13_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_14_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_15_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_16_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_17_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_18_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_19_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_0_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_1_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_2_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_3_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_4_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_5_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_6_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_7_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_8_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_9_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_10_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_11_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_12_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_13_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_14_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_15_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_16_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_17_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_18_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_19_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_0_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_1_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_2_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_3_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_4_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_5_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_6_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_7_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_8_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_9_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_10_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_11_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_12_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_13_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_14_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_15_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_16_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_17_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_18_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_19_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_0_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_1_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_2_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_3_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_4_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_5_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_6_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_7_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_8_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_9_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_10_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_11_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_12_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_13_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_14_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_15_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_16_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_17_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_18_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_19_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_0_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_1_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_2_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_3_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_4_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_5_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_6_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_7_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_8_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_9_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_10_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_11_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_12_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_13_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_14_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_15_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_16_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_17_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_18_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_19_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_0_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_1_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_2_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_3_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_4_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_5_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_6_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_7_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_8_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_9_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_10_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_11_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_12_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_13_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_14_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_15_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_16_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_17_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_18_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_19_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_0_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_1_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_2_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_3_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_4_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_5_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_6_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_7_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_8_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_9_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_10_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_11_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_12_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_13_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_14_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_15_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_16_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_17_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_18_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_19_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_12_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_13_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_14_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_15_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_16_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_17_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_18_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_19_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_0_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_1_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_2_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_3_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_4_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_5_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_6_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_7_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_8_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_9_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_10_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_11_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_12_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_13_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_14_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_15_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_16_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_17_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_18_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_19_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_0_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_1_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_2_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_3_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_4_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_5_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_6_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_7_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_8_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_9_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_10_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_11_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_12_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_13_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_14_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_15_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_16_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_17_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_18_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_19_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_0_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_1_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_2_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_3_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_4_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_5_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_6_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_7_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_8_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_9_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_10_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_11_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_12_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_13_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_14_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_15_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_16_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_17_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_18_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_19_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_0_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_1_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_2_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_3_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_4_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_5_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_6_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_7_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_8_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_9_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_10_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_11_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_12_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_13_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_14_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_15_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_16_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_17_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_18_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_19_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_0_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_1_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_2_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_3_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_4_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_5_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_6_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_7_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_8_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_9_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_10_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_11_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_12_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_13_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_14_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_15_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_16_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_17_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_18_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_19_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_12_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_13_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_14_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_15_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_16_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_17_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_18_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_19_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_12_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_13_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_14_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_15_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_16_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_17_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_18_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_19_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_12_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_13_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_14_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_15_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_16_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_17_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_18_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_19_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_0_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_1_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_2_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_3_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_4_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_5_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_6_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_7_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_8_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_9_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_10_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_11_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_12_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_13_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_14_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_15_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_16_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_17_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_18_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_19_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_0_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_1_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_2_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_3_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_4_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_5_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_6_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_7_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_8_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_9_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_10_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_11_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_12_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_13_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_14_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_15_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_16_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_17_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_18_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_19_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_0_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_1_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_2_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_3_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_4_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_5_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_6_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_7_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_8_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_9_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_10_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_11_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_12_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_13_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_14_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_15_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_16_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_17_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_18_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_19_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_0_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_1_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_2_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_3_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_4_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_5_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_6_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_7_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_8_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_9_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_10_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_11_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_12_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_13_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_14_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_15_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_16_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_17_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_18_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_19_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_0_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_1_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_2_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_3_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_4_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_5_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_6_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_7_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_8_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_9_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_10_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_11_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_12_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_13_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_14_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_15_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_16_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_17_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_18_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_19_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_0_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_1_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_2_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_3_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_4_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_5_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_6_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_7_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_8_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_9_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_10_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_11_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_12_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_13_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_14_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_15_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_16_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_17_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_18_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_19_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_0_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_1_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_2_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_3_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_4_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_5_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_6_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_7_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_8_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_9_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_10_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_11_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_12_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_13_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_14_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_15_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_16_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_17_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_18_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_19_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_0_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_1_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_2_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_3_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_4_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_5_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_6_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_7_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_8_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_9_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_10_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_11_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_12_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_13_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_14_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_15_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_16_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_17_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_18_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_19_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_12_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_13_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_14_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_15_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_16_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_17_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_18_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_19_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_0_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_1_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_2_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_3_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_4_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_5_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_6_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_7_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_8_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_9_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_10_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_11_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_12_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_13_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_14_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_15_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_16_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_17_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_18_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_19_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_0_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_1_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_2_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_3_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_4_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_5_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_6_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_7_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_8_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_9_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_10_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_11_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_12_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_13_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_14_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_15_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_16_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_17_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_18_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_19_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_12_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_13_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_14_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_15_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_16_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_17_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_18_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_19_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_0_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_1_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_2_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_3_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_4_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_5_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_6_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_7_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_8_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_9_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_10_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_11_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_12_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_13_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_14_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_15_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_16_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_17_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_18_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_19_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_0_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_1_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_2_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_3_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_4_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_5_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_6_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_7_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_8_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_9_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_10_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_11_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_12_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_13_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_14_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_15_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_16_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_17_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_18_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_19_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_0_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_1_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_2_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_3_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_4_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_5_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_6_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_7_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_8_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_9_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_10_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_11_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_12_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_13_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_14_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_15_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_16_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_17_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_18_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_19_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_0_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_1_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_2_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_3_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_4_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_5_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_6_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_7_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_8_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_9_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_10_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_11_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_12_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_13_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_14_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_15_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_16_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_17_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_18_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_19_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_0_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_1_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_2_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_3_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_4_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_5_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_6_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_7_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_8_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_9_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_10_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_11_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_12_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_13_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_14_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_15_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_16_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_17_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_18_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_19_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_0_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_1_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_2_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_3_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_4_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_5_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_6_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_7_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_8_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_9_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_10_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_11_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_12_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_13_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_14_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_15_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_16_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_17_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_18_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_19_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_0_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_1_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_2_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_3_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_4_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_5_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_6_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_7_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_8_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_9_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_10_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_11_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_12_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_13_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_14_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_15_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_16_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_17_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_18_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_19_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_0_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_1_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_2_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_3_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_4_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_5_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_6_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_7_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_8_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_9_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_10_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_11_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_12_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_13_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_14_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_15_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_16_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_17_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_18_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_19_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_0_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_1_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_2_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_3_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_4_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_5_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_6_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_7_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_8_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_9_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_10_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_11_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_12_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_13_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_14_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_15_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_16_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_17_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_18_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_19_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_0_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_1_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_2_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_3_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_4_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_5_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_6_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_7_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_8_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_9_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_10_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_11_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_12_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_13_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_14_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_15_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_16_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_17_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_18_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_19_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_0_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_1_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_2_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_3_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_4_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_5_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_6_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_7_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_8_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_9_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_10_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_11_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_12_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_13_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_14_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_15_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_16_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_17_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_18_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_19_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_12_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_13_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_14_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_15_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_16_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_17_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_18_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_19_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_0_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_1_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_2_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_3_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_4_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_5_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_6_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_7_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_8_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_9_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_10_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_11_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_12_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_13_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_14_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_15_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_16_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_17_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_18_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_19_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_0_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_1_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_2_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_3_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_4_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_5_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_6_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_7_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_8_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_9_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_10_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_11_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_12_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_13_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_14_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_15_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_16_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_17_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_18_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_19_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_0_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_1_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_2_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_3_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_4_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_5_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_6_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_7_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_8_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_9_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_10_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_11_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_12_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_13_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_14_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_15_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_16_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_17_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_18_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_19_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_0_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_1_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_2_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_3_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_4_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_5_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_6_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_7_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_8_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_9_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_10_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_11_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_12_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_13_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_14_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_15_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_16_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_17_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_18_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_19_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_0_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_1_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_2_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_3_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_4_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_5_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_6_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_7_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_8_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_9_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_10_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_11_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_12_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_13_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_14_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_15_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_16_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_17_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_18_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_19_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_12_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_13_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_14_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_15_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_16_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_17_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_18_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_19_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_12_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_13_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_14_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_15_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_16_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_17_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_18_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_19_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_12_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_13_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_14_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_15_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_16_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_17_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_18_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_19_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_0_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_1_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_2_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_3_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_4_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_5_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_6_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_7_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_8_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_9_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_10_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_11_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_12_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_13_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_14_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_15_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_16_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_17_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_18_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_19_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_0_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_1_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_2_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_3_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_4_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_5_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_6_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_7_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_8_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_9_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_10_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_11_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_12_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_13_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_14_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_15_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_16_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_17_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_18_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_19_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_0_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_1_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_2_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_3_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_4_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_5_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_6_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_7_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_8_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_9_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_10_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_11_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_12_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_13_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_14_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_15_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_16_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_17_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_18_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_19_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_0_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_1_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_2_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_3_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_4_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_5_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_6_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_7_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_8_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_9_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_10_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_11_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_12_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_13_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_14_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_15_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_16_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_17_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_18_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_19_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_0_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_1_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_2_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_3_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_4_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_5_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_6_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_7_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_8_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_9_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_10_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_11_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_12_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_13_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_14_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_15_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_16_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_17_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_18_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [31:0] issue_slots_19_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_0_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_1_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_2_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_3_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_4_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_5_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_6_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_7_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_8_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_9_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_10_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_11_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_12_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_13_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_14_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_15_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_16_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_17_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_18_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_19_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_0_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_1_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_2_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_3_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_4_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_5_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_6_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_7_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_8_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_9_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_10_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_11_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_12_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_13_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_14_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_15_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_16_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_17_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_18_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [11:0] issue_slots_19_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_0_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_1_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_2_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_3_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_4_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_5_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_6_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_7_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_8_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_9_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_10_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_11_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_12_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_13_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_14_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_15_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_16_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_17_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_18_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_19_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_0_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_1_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_2_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_3_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_4_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_5_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_6_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_7_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_8_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_9_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_10_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_11_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_12_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_13_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_14_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_15_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_16_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_17_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_18_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_19_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_0_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_1_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_2_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_3_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_4_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_5_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_6_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_7_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_8_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_9_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_10_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_11_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_12_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_13_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_14_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_15_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_16_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_17_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_18_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_19_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_0_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_1_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_2_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_3_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_4_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_5_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_6_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_7_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_8_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_9_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_10_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_11_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_12_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_13_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_14_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_15_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_16_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_17_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_18_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_19_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_0_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_1_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_2_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_3_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_4_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_5_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_6_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_7_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_8_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_9_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_10_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_11_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_12_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_13_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_14_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_15_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_16_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_17_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_18_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_19_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_0_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_1_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_2_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_3_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_4_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_5_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_6_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_7_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_8_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_9_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_10_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_11_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_12_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_13_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_14_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_15_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_16_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_17_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_18_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_19_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_0_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_1_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_2_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_3_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_4_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_5_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_6_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_7_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_8_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_9_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_10_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_11_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_12_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_13_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_14_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_15_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_16_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_17_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_18_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [19:0] issue_slots_19_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_0_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_1_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_2_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_3_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_4_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_5_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_6_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_7_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_8_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_9_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_10_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_11_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_12_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_13_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_14_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_15_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_16_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_17_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_18_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_19_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_0_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_1_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_2_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_3_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_4_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_5_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_6_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_7_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_8_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_9_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_10_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_11_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_12_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_13_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_14_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_15_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_16_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_17_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_18_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_19_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_0_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_1_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_2_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_3_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_4_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_5_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_6_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_7_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_8_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_9_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_10_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_11_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_12_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_13_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_14_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_15_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_16_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_17_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_18_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_19_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_0_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_1_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_2_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_3_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_4_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_5_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_6_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_7_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_8_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_9_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_10_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_11_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_12_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_13_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_14_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_15_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_16_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_17_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_18_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [3:0] issue_slots_19_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_0_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_1_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_2_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_3_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_4_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_5_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_6_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_7_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_8_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_9_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_10_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_11_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_12_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_13_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_14_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_15_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_16_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_17_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_18_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_19_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_0_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_1_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_2_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_3_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_4_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_5_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_6_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_7_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_8_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_9_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_10_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_11_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_12_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_13_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_14_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_15_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_16_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_17_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_18_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_19_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_0_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_1_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_2_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_3_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_4_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_5_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_6_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_7_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_8_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_9_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_10_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_11_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_12_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_13_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_14_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_15_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_16_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_17_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_18_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_19_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_0_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_1_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_2_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_3_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_4_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_5_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_6_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_7_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_8_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_9_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_10_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_11_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_12_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_13_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_14_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_15_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_16_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_17_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_18_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_19_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_0_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_1_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_2_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_3_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_4_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_5_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_6_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_7_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_8_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_9_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_10_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_11_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_12_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_13_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_14_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_15_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_16_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_17_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_18_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_19_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_0_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_1_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_2_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_3_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_4_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_5_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_6_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_7_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_8_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_9_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_10_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_11_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_12_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_13_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_14_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_15_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_16_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_17_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_18_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [6:0] issue_slots_19_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_0_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_1_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_2_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_3_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_4_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_5_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_6_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_7_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_8_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_9_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_10_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_11_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_12_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_13_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_14_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_15_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_16_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_17_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_18_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [63:0] issue_slots_19_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_0_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_1_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_2_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_3_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_4_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_5_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_6_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_7_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_8_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_9_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_10_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_11_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_12_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_13_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_14_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_15_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_16_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_17_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_18_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_19_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_0_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_1_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_2_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_3_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_4_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_5_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_6_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_7_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_8_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_9_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_10_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_11_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_12_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_13_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_14_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_15_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_16_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_17_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_18_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_19_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_0_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_1_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_2_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_3_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_4_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_5_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_6_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_7_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_8_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_9_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_10_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_11_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_12_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_13_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_14_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_15_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_16_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_17_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_18_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_19_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_0_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_1_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_2_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_3_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_4_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_5_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_6_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_7_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_8_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_9_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_10_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_11_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_12_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_13_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_14_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_15_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_16_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_17_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_18_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_19_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_0_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_1_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_2_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_3_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_4_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_5_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_6_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_7_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_8_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_9_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_10_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_11_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_12_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_13_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_14_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_15_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_16_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_17_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_18_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_19_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_0_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_1_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_2_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_3_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_4_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_5_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_6_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_7_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_8_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_9_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_10_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_11_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_12_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_13_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_14_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_15_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_16_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_17_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_18_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [5:0] issue_slots_19_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_0_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_1_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_2_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_3_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_4_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_5_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_6_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_7_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_8_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_9_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_10_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_11_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_12_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_13_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_14_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_15_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_16_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_17_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_18_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [4:0] issue_slots_19_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_0_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_1_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_2_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_3_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_4_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_5_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_6_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_7_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_8_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_9_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_10_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_11_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_12_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_13_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_14_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_15_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_16_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_17_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_18_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_19_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_0_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_1_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_2_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_3_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_4_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_5_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_6_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_7_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_8_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_9_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_10_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_11_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_12_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_13_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_14_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_15_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_16_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_17_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_18_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_19_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_0_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_1_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_2_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_3_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_4_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_5_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_6_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_7_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_8_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_9_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_10_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_11_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_12_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_13_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_14_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_15_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_16_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_17_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_18_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_19_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_0_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_1_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_2_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_3_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_4_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_5_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_6_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_7_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_8_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_9_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_10_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_11_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_12_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_13_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_14_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_15_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_16_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_17_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_18_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [2:0] issue_slots_19_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_0_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_1_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_2_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_3_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_4_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_5_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_6_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_7_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_8_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_9_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_10_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_11_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_12_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_13_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_14_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_15_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_16_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_17_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_18_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [1:0] issue_slots_19_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_0_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_1_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_2_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_3_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_4_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_5_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_6_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_7_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_8_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_9_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_10_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_11_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_12_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_13_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_14_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_15_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_16_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_17_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_18_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [39:0] issue_slots_19_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [20:0] issue_slots_0_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [20:0] issue_slots_1_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [20:0] issue_slots_2_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [20:0] issue_slots_3_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [20:0] issue_slots_4_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [20:0] issue_slots_5_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [20:0] issue_slots_6_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [20:0] issue_slots_7_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [20:0] issue_slots_8_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [20:0] issue_slots_9_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [20:0] issue_slots_10_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [20:0] issue_slots_11_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [20:0] issue_slots_12_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [20:0] issue_slots_13_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [20:0] issue_slots_14_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [20:0] issue_slots_15_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [20:0] issue_slots_16_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [20:0] issue_slots_17_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [20:0] issue_slots_18_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire [20:0] issue_slots_19_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_0_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_1_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_2_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_3_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_4_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_5_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_6_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_7_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_8_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_9_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_10_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_11_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_12_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_13_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_14_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_15_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_16_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_17_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_18_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire issue_slots_19_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28]
wire io_dis_uops_0_ready_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_dis_uops_1_ready_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_iss_uops_0_bits_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_iss_uops_0_bits_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7]
wire [31:0] io_iss_uops_0_bits_inst_0; // @[issue-unit-age-ordered.scala:22:7]
wire [31:0] io_iss_uops_0_bits_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7]
wire [39:0] io_iss_uops_0_bits_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_iss_uops_0_bits_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_iss_uops_0_bits_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_iss_uops_0_bits_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7]
wire [11:0] io_iss_uops_0_bits_br_mask_0; // @[issue-unit-age-ordered.scala:22:7]
wire [3:0] io_iss_uops_0_bits_br_tag_0; // @[issue-unit-age-ordered.scala:22:7]
wire [3:0] io_iss_uops_0_bits_br_type_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_is_fence_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_is_amo_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_is_eret_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_is_mov_0; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_iss_uops_0_bits_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_iss_uops_0_bits_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_taken_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_iss_uops_0_bits_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_iss_uops_0_bits_pimm_0; // @[issue-unit-age-ordered.scala:22:7]
wire [19:0] io_iss_uops_0_bits_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_iss_uops_0_bits_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_iss_uops_0_bits_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_iss_uops_0_bits_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7]
wire [3:0] io_iss_uops_0_bits_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7]
wire [3:0] io_iss_uops_0_bits_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_iss_uops_0_bits_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_iss_uops_0_bits_pdst_0; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_iss_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_iss_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_iss_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_iss_uops_0_bits_ppred_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_iss_uops_0_bits_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_exception_0; // @[issue-unit-age-ordered.scala:22:7]
wire [63:0] io_iss_uops_0_bits_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_iss_uops_0_bits_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_iss_uops_0_bits_mem_size_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_is_unique_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_iss_uops_0_bits_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_iss_uops_0_bits_ldst_0; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_iss_uops_0_bits_lrs1_0; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_iss_uops_0_bits_lrs2_0; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_iss_uops_0_bits_lrs3_0; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_iss_uops_0_bits_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_iss_uops_0_bits_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_iss_uops_0_bits_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_iss_uops_0_bits_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_fp_val_0; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_iss_uops_0_bits_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_iss_uops_0_bits_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_bits_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_iss_uops_0_bits_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_iss_uops_0_bits_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_0_valid_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_iss_uops_1_bits_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_iss_uops_1_bits_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7]
wire [31:0] io_iss_uops_1_bits_inst_0; // @[issue-unit-age-ordered.scala:22:7]
wire [31:0] io_iss_uops_1_bits_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7]
wire [39:0] io_iss_uops_1_bits_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_iss_uops_1_bits_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_iss_uops_1_bits_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_iss_uops_1_bits_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7]
wire [11:0] io_iss_uops_1_bits_br_mask_0; // @[issue-unit-age-ordered.scala:22:7]
wire [3:0] io_iss_uops_1_bits_br_tag_0; // @[issue-unit-age-ordered.scala:22:7]
wire [3:0] io_iss_uops_1_bits_br_type_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_is_fence_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_is_amo_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_is_eret_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_is_mov_0; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_iss_uops_1_bits_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_iss_uops_1_bits_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_taken_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_iss_uops_1_bits_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_iss_uops_1_bits_pimm_0; // @[issue-unit-age-ordered.scala:22:7]
wire [19:0] io_iss_uops_1_bits_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_iss_uops_1_bits_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_iss_uops_1_bits_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_iss_uops_1_bits_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7]
wire [3:0] io_iss_uops_1_bits_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7]
wire [3:0] io_iss_uops_1_bits_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_iss_uops_1_bits_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_iss_uops_1_bits_pdst_0; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_iss_uops_1_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_iss_uops_1_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_iss_uops_1_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_iss_uops_1_bits_ppred_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7]
wire [6:0] io_iss_uops_1_bits_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_exception_0; // @[issue-unit-age-ordered.scala:22:7]
wire [63:0] io_iss_uops_1_bits_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_iss_uops_1_bits_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_iss_uops_1_bits_mem_size_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_is_unique_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_iss_uops_1_bits_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_iss_uops_1_bits_ldst_0; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_iss_uops_1_bits_lrs1_0; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_iss_uops_1_bits_lrs2_0; // @[issue-unit-age-ordered.scala:22:7]
wire [5:0] io_iss_uops_1_bits_lrs3_0; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_iss_uops_1_bits_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_iss_uops_1_bits_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_iss_uops_1_bits_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7]
wire [4:0] io_iss_uops_1_bits_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_fp_val_0; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_iss_uops_1_bits_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7]
wire [1:0] io_iss_uops_1_bits_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_bits_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_iss_uops_1_bits_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7]
wire [2:0] io_iss_uops_1_bits_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7]
wire io_iss_uops_1_valid_0; // @[issue-unit-age-ordered.scala:22:7]
wire prs1_matches_0 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69]
wire prs1_matches_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69]
wire prs1_matches_2 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69]
wire prs1_matches_3 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69]
wire prs2_matches_0 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69]
wire prs2_matches_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69]
wire prs2_matches_2 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69]
wire prs2_matches_3 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69]
wire prs3_matches_0 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69]
wire prs3_matches_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69]
wire prs3_matches_2 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69]
wire prs3_matches_3 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69]
wire prs1_wakeups_0 = io_wakeup_ports_0_valid_0 & prs1_matches_0; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89]
wire prs1_wakeups_1 = io_wakeup_ports_1_valid_0 & prs1_matches_1; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89]
wire prs1_wakeups_2 = io_wakeup_ports_2_valid_0 & prs1_matches_2; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89]
wire prs1_wakeups_3 = io_wakeup_ports_3_valid_0 & prs1_matches_3; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89]
wire prs2_wakeups_0 = io_wakeup_ports_0_valid_0 & prs2_matches_0; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89]
wire prs2_wakeups_1 = io_wakeup_ports_1_valid_0 & prs2_matches_1; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89]
wire prs2_wakeups_2 = io_wakeup_ports_2_valid_0 & prs2_matches_2; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89]
wire prs2_wakeups_3 = io_wakeup_ports_3_valid_0 & prs2_matches_3; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89]
wire prs3_wakeups_0 = io_wakeup_ports_0_valid_0 & prs3_matches_0; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89]
wire prs3_wakeups_1 = io_wakeup_ports_1_valid_0 & prs3_matches_1; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89]
wire prs3_wakeups_2 = io_wakeup_ports_2_valid_0 & prs3_matches_2; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89]
wire prs3_wakeups_3 = io_wakeup_ports_3_valid_0 & prs3_matches_3; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89]
wire prs1_rebusys_0 = io_wakeup_ports_0_bits_rebusy_0 & prs1_matches_0; // @[issue-unit-age-ordered.scala:22:7, :44:69, :50:95]
wire prs2_rebusys_0 = io_wakeup_ports_0_bits_rebusy_0 & prs2_matches_0; // @[issue-unit-age-ordered.scala:22:7, :45:69, :51:95]
wire _T_2 = prs1_wakeups_0 | prs1_wakeups_1 | prs1_wakeups_2 | prs1_wakeups_3; // @[issue-unit-age-ordered.scala:47:89, :57:32]
wire [1:0] _WIRE_iw_p1_speculative_child = _T_2 ? (prs1_wakeups_0 ? io_wakeup_ports_0_bits_speculative_mask_0 : 2'h0) | {prs1_wakeups_3, prs1_wakeups_2} : io_dis_uops_0_bits_iw_p1_speculative_child_0; // @[Mux.scala:30:73]
wire _WIRE_iw_p1_bypass_hint = _T_2 & (prs1_wakeups_0 & io_wakeup_ports_0_bits_bypassable_0 | prs1_wakeups_2 | prs1_wakeups_3); // @[Mux.scala:30:73]
wire _WIRE_prs1_busy = (|{prs1_rebusys_0, io_child_rebusys_0 & io_dis_uops_0_bits_iw_p1_speculative_child_0}) ? io_dis_uops_0_bits_lrs1_rtype_0 == 2'h0 : ~_T_2 & io_dis_uops_0_bits_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :50:95, :57:{32,38}, :58:29, :62:{37,59,106,116}, :63:{29,63}]
wire _T_26 = prs2_wakeups_0 | prs2_wakeups_1 | prs2_wakeups_2 | prs2_wakeups_3; // @[issue-unit-age-ordered.scala:48:89, :65:32]
wire [1:0] _WIRE_iw_p2_speculative_child = _T_26 ? (prs2_wakeups_0 ? io_wakeup_ports_0_bits_speculative_mask_0 : 2'h0) | {prs2_wakeups_3, prs2_wakeups_2} : io_dis_uops_0_bits_iw_p2_speculative_child_0; // @[Mux.scala:30:73]
wire _WIRE_iw_p2_bypass_hint = _T_26 & (prs2_wakeups_0 & io_wakeup_ports_0_bits_bypassable_0 | prs2_wakeups_2 | prs2_wakeups_3); // @[Mux.scala:30:73]
wire _WIRE_prs2_busy = (|{prs2_rebusys_0, io_child_rebusys_0 & io_dis_uops_0_bits_iw_p2_speculative_child_0}) ? io_dis_uops_0_bits_lrs2_rtype_0 == 2'h0 : ~_T_26 & io_dis_uops_0_bits_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :51:95, :65:{32,38}, :66:29, :71:{37,59,106,116}, :72:{29,63}]
wire _T_50 = prs3_wakeups_0 | prs3_wakeups_1 | prs3_wakeups_2 | prs3_wakeups_3; // @[issue-unit-age-ordered.scala:49:89, :76:32]
wire _WIRE_prs3_busy = ~_T_50 & io_dis_uops_0_bits_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :76:{32,38}, :77:29]
wire _WIRE_iw_p3_bypass_hint = _T_50 & (prs3_wakeups_0 & io_wakeup_ports_0_bits_bypassable_0 | prs3_wakeups_2 | prs3_wakeups_3); // @[Mux.scala:30:73]
wire _WIRE_ppred_busy = ~(io_pred_wakeup_port_valid_0 & io_pred_wakeup_port_bits_0 == io_dis_uops_0_bits_ppred_0) & io_dis_uops_0_bits_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :80:{37,65,96}, :81:30]
wire prs1_matches_0_1 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_1_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69]
wire prs1_matches_1_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_1_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69]
wire prs1_matches_2_1 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_1_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69]
wire prs1_matches_3_1 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_1_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69]
wire prs2_matches_0_1 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_1_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69]
wire prs2_matches_1_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_1_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69]
wire prs2_matches_2_1 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_1_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69]
wire prs2_matches_3_1 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_1_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69]
wire prs3_matches_0_1 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_1_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69]
wire prs3_matches_1_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_1_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69]
wire prs3_matches_2_1 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_1_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69]
wire prs3_matches_3_1 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_1_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69]
wire prs1_wakeups_0_1 = io_wakeup_ports_0_valid_0 & prs1_matches_0_1; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89]
wire prs1_wakeups_1_1 = io_wakeup_ports_1_valid_0 & prs1_matches_1_1; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89]
wire prs1_wakeups_2_1 = io_wakeup_ports_2_valid_0 & prs1_matches_2_1; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89]
wire prs1_wakeups_3_1 = io_wakeup_ports_3_valid_0 & prs1_matches_3_1; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89]
wire prs2_wakeups_0_1 = io_wakeup_ports_0_valid_0 & prs2_matches_0_1; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89]
wire prs2_wakeups_1_1 = io_wakeup_ports_1_valid_0 & prs2_matches_1_1; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89]
wire prs2_wakeups_2_1 = io_wakeup_ports_2_valid_0 & prs2_matches_2_1; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89]
wire prs2_wakeups_3_1 = io_wakeup_ports_3_valid_0 & prs2_matches_3_1; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89]
wire prs3_wakeups_0_1 = io_wakeup_ports_0_valid_0 & prs3_matches_0_1; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89]
wire prs3_wakeups_1_1 = io_wakeup_ports_1_valid_0 & prs3_matches_1_1; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89]
wire prs3_wakeups_2_1 = io_wakeup_ports_2_valid_0 & prs3_matches_2_1; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89]
wire prs3_wakeups_3_1 = io_wakeup_ports_3_valid_0 & prs3_matches_3_1; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89]
wire prs1_rebusys_0_1 = io_wakeup_ports_0_bits_rebusy_0 & prs1_matches_0_1; // @[issue-unit-age-ordered.scala:22:7, :44:69, :50:95]
wire prs2_rebusys_0_1 = io_wakeup_ports_0_bits_rebusy_0 & prs2_matches_0_1; // @[issue-unit-age-ordered.scala:22:7, :45:69, :51:95]
wire _T_62 = prs1_wakeups_0_1 | prs1_wakeups_1_1 | prs1_wakeups_2_1 | prs1_wakeups_3_1; // @[issue-unit-age-ordered.scala:47:89, :57:32]
wire _T_86 = prs2_wakeups_0_1 | prs2_wakeups_1_1 | prs2_wakeups_2_1 | prs2_wakeups_3_1; // @[issue-unit-age-ordered.scala:48:89, :65:32]
wire _T_110 = prs3_wakeups_0_1 | prs3_wakeups_1_1 | prs3_wakeups_2_1 | prs3_wakeups_3_1; // @[issue-unit-age-ordered.scala:49:89, :76:32]
wire _fu_code_match_T = issue_slots_0_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25]
wire _fu_code_match_T_18 = issue_slots_0_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25]
wire _fu_code_match_T_36 = issue_slots_1_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25]
wire _fu_code_match_T_54 = issue_slots_1_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25]
wire _issue_slots_1_clear_T; // @[issue-unit-age-ordered.scala:199:49]
wire _fu_code_match_T_72 = issue_slots_2_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25]
wire _fu_code_match_T_90 = issue_slots_2_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25]
wire _issue_slots_2_clear_T; // @[issue-unit-age-ordered.scala:199:49]
wire _fu_code_match_T_108 = issue_slots_3_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25]
wire _fu_code_match_T_126 = issue_slots_3_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25]
wire _issue_slots_3_clear_T; // @[issue-unit-age-ordered.scala:199:49]
wire _fu_code_match_T_144 = issue_slots_4_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25]
wire _fu_code_match_T_162 = issue_slots_4_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25]
wire _issue_slots_4_clear_T; // @[issue-unit-age-ordered.scala:199:49]
wire _fu_code_match_T_180 = issue_slots_5_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25]
wire _fu_code_match_T_198 = issue_slots_5_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25]
wire _issue_slots_5_clear_T; // @[issue-unit-age-ordered.scala:199:49]
wire _fu_code_match_T_216 = issue_slots_6_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25]
wire _fu_code_match_T_234 = issue_slots_6_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25]
wire _issue_slots_6_clear_T; // @[issue-unit-age-ordered.scala:199:49]
wire _fu_code_match_T_252 = issue_slots_7_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25]
wire _fu_code_match_T_270 = issue_slots_7_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25]
wire _issue_slots_7_clear_T; // @[issue-unit-age-ordered.scala:199:49]
wire _fu_code_match_T_288 = issue_slots_8_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25]
wire _fu_code_match_T_306 = issue_slots_8_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25]
wire _issue_slots_8_clear_T; // @[issue-unit-age-ordered.scala:199:49]
wire _fu_code_match_T_324 = issue_slots_9_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25]
wire _fu_code_match_T_342 = issue_slots_9_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25]
wire _issue_slots_9_clear_T; // @[issue-unit-age-ordered.scala:199:49]
wire _fu_code_match_T_360 = issue_slots_10_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25]
wire _fu_code_match_T_378 = issue_slots_10_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25]
wire _issue_slots_10_clear_T; // @[issue-unit-age-ordered.scala:199:49]
wire _fu_code_match_T_396 = issue_slots_11_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25]
wire _fu_code_match_T_414 = issue_slots_11_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25]
wire _issue_slots_11_clear_T; // @[issue-unit-age-ordered.scala:199:49]
wire _fu_code_match_T_432 = issue_slots_12_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25]
wire _fu_code_match_T_450 = issue_slots_12_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25]
wire _issue_slots_12_clear_T; // @[issue-unit-age-ordered.scala:199:49]
wire _fu_code_match_T_468 = issue_slots_13_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25]
wire _fu_code_match_T_486 = issue_slots_13_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25]
wire _issue_slots_13_clear_T; // @[issue-unit-age-ordered.scala:199:49]
wire _fu_code_match_T_504 = issue_slots_14_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25]
wire _fu_code_match_T_522 = issue_slots_14_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25]
wire _issue_slots_14_clear_T; // @[issue-unit-age-ordered.scala:199:49]
wire _fu_code_match_T_540 = issue_slots_15_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25]
wire _fu_code_match_T_558 = issue_slots_15_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25]
wire _issue_slots_15_clear_T; // @[issue-unit-age-ordered.scala:199:49]
wire _fu_code_match_T_576 = issue_slots_16_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25]
wire _fu_code_match_T_594 = issue_slots_16_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25]
wire _issue_slots_16_clear_T; // @[issue-unit-age-ordered.scala:199:49]
wire _fu_code_match_T_612 = issue_slots_17_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25]
wire _fu_code_match_T_630 = issue_slots_17_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25]
wire _issue_slots_17_clear_T; // @[issue-unit-age-ordered.scala:199:49]
wire _fu_code_match_T_648 = issue_slots_18_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25]
wire _fu_code_match_T_666 = issue_slots_18_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25]
wire _issue_slots_18_clear_T; // @[issue-unit-age-ordered.scala:199:49]
wire _fu_code_match_T_684 = issue_slots_19_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25]
wire _fu_code_match_T_702 = issue_slots_19_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25]
wire _issue_slots_19_clear_T; // @[issue-unit-age-ordered.scala:199:49]
wire issue_slots_0_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_0_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_0_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_0_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_0_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_0_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_0_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_0_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_0_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_0_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_0_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_0_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_0_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_0_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_0_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_0_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_0_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_0_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_0_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_0_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_0_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_0_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_0_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_0_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_0_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_0_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_0_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_0_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_0_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_0_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_0_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_0_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_0_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_0_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_0_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_0_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_0_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_0_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_0_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_0_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_0_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_0_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_0_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_0_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_0_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_0_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_0_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_0_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_0_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_0_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_0_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_0_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_0_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_0_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_0_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_0_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_0_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_0_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_0_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_0_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_0_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_0_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_0_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_0_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_0_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_0_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_0_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_0_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_0_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_0_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_0_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_0_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_0_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_0_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_0_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_0_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_0_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_0_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_0_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_0_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_0_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_0_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_0_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_0_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_0_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_0_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_0_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_0_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_0_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_0_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_0_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_0_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_0_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_0_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_0_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_0_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_0_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_0_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_0_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_0_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_0_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_0_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_0_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_0_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_0_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_0_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_0_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_0_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_0_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_0_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_0_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_0_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_0_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_0_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_0_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_0_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_0_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_0_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_0_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_0_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_0_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_0_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_0_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_0_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_0_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_0_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_0_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_0_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_0_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_0_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_0_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_0_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_0_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_will_be_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_request; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_0_grant; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_1_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_1_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_1_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_1_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_1_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_1_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_1_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_1_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_1_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_1_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_1_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_1_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_1_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_1_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_1_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_1_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_1_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_1_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_1_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_1_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_1_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_1_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_1_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_1_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_1_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_1_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_1_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_1_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_1_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_1_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_1_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_1_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_1_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_1_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_1_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_1_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_1_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_1_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_1_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_1_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_1_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_1_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_1_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_1_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_1_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_1_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_1_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_1_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_1_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_1_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_1_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_1_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_1_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_1_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_1_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_1_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_1_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_1_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_1_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_1_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_1_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_1_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_1_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_1_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_1_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_1_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_1_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_1_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_1_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_1_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_1_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_1_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_1_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_1_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_1_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_1_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_1_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_1_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_1_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_1_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_1_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_1_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_1_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_1_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_1_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_1_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_1_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_1_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_1_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_1_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_1_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_1_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_1_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_1_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_1_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_1_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_1_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_1_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_1_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_1_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_1_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_1_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_1_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_1_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_1_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_1_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_1_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_1_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_1_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_1_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_1_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_1_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_1_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_1_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_1_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_1_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_1_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_1_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_1_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_1_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_1_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_1_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_1_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_1_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_1_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_1_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_1_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_1_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_1_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_1_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_1_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_1_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_will_be_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_request; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_grant; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_1_clear; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_2_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_2_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_2_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_2_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_2_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_2_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_2_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_2_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_2_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_2_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_2_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_2_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_2_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_2_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_2_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_2_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_2_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_2_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_2_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_2_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_2_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_2_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_2_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_2_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_2_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_2_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_2_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_2_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_2_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_2_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_2_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_2_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_2_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_2_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_2_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_2_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_2_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_2_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_2_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_2_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_2_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_2_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_2_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_2_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_2_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_2_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_2_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_2_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_2_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_2_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_2_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_2_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_2_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_2_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_2_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_2_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_2_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_2_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_2_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_2_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_2_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_2_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_2_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_2_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_2_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_2_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_2_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_2_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_2_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_2_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_2_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_2_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_2_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_2_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_2_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_2_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_2_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_2_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_2_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_2_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_2_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_2_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_2_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_2_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_2_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_2_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_2_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_2_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_2_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_2_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_2_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_2_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_2_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_2_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_2_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_2_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_2_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_2_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_2_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_2_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_2_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_2_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_2_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_2_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_2_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_2_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_2_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_2_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_2_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_2_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_2_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_2_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_2_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_2_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_2_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_2_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_2_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_2_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_2_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_2_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_2_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_2_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_2_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_2_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_2_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_2_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_2_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_2_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_2_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_2_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_2_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_2_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_will_be_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_request; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_grant; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_2_clear; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_3_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_3_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_3_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_3_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_3_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_3_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_3_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_3_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_3_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_3_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_3_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_3_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_3_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_3_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_3_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_3_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_3_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_3_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_3_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_3_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_3_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_3_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_3_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_3_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_3_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_3_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_3_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_3_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_3_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_3_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_3_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_3_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_3_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_3_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_3_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_3_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_3_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_3_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_3_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_3_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_3_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_3_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_3_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_3_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_3_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_3_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_3_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_3_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_3_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_3_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_3_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_3_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_3_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_3_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_3_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_3_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_3_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_3_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_3_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_3_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_3_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_3_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_3_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_3_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_3_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_3_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_3_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_3_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_3_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_3_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_3_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_3_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_3_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_3_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_3_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_3_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_3_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_3_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_3_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_3_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_3_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_3_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_3_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_3_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_3_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_3_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_3_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_3_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_3_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_3_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_3_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_3_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_3_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_3_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_3_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_3_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_3_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_3_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_3_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_3_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_3_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_3_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_3_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_3_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_3_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_3_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_3_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_3_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_3_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_3_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_3_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_3_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_3_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_3_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_3_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_3_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_3_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_3_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_3_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_3_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_3_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_3_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_3_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_3_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_3_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_3_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_3_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_3_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_3_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_3_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_3_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_3_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_will_be_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_request; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_grant; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_3_clear; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_4_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_4_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_4_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_4_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_4_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_4_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_4_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_4_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_4_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_4_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_4_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_4_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_4_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_4_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_4_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_4_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_4_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_4_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_4_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_4_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_4_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_4_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_4_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_4_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_4_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_4_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_4_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_4_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_4_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_4_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_4_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_4_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_4_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_4_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_4_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_4_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_4_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_4_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_4_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_4_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_4_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_4_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_4_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_4_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_4_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_4_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_4_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_4_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_4_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_4_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_4_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_4_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_4_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_4_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_4_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_4_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_4_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_4_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_4_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_4_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_4_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_4_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_4_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_4_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_4_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_4_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_4_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_4_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_4_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_4_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_4_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_4_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_4_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_4_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_4_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_4_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_4_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_4_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_4_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_4_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_4_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_4_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_4_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_4_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_4_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_4_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_4_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_4_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_4_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_4_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_4_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_4_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_4_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_4_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_4_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_4_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_4_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_4_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_4_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_4_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_4_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_4_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_4_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_4_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_4_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_4_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_4_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_4_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_4_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_4_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_4_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_4_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_4_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_4_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_4_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_4_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_4_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_4_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_4_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_4_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_4_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_4_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_4_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_4_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_4_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_4_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_4_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_4_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_4_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_4_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_4_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_4_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_will_be_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_request; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_grant; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_4_clear; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_5_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_5_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_5_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_5_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_5_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_5_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_5_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_5_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_5_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_5_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_5_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_5_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_5_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_5_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_5_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_5_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_5_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_5_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_5_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_5_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_5_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_5_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_5_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_5_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_5_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_5_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_5_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_5_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_5_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_5_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_5_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_5_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_5_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_5_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_5_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_5_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_5_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_5_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_5_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_5_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_5_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_5_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_5_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_5_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_5_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_5_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_5_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_5_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_5_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_5_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_5_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_5_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_5_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_5_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_5_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_5_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_5_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_5_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_5_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_5_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_5_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_5_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_5_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_5_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_5_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_5_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_5_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_5_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_5_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_5_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_5_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_5_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_5_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_5_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_5_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_5_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_5_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_5_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_5_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_5_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_5_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_5_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_5_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_5_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_5_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_5_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_5_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_5_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_5_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_5_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_5_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_5_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_5_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_5_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_5_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_5_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_5_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_5_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_5_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_5_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_5_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_5_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_5_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_5_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_5_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_5_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_5_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_5_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_5_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_5_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_5_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_5_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_5_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_5_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_5_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_5_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_5_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_5_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_5_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_5_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_5_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_5_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_5_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_5_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_5_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_5_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_5_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_5_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_5_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_5_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_5_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_5_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_will_be_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_request; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_grant; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_5_clear; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_6_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_6_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_6_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_6_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_6_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_6_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_6_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_6_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_6_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_6_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_6_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_6_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_6_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_6_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_6_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_6_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_6_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_6_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_6_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_6_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_6_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_6_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_6_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_6_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_6_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_6_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_6_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_6_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_6_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_6_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_6_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_6_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_6_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_6_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_6_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_6_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_6_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_6_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_6_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_6_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_6_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_6_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_6_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_6_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_6_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_6_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_6_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_6_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_6_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_6_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_6_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_6_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_6_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_6_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_6_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_6_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_6_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_6_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_6_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_6_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_6_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_6_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_6_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_6_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_6_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_6_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_6_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_6_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_6_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_6_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_6_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_6_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_6_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_6_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_6_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_6_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_6_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_6_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_6_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_6_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_6_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_6_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_6_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_6_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_6_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_6_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_6_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_6_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_6_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_6_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_6_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_6_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_6_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_6_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_6_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_6_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_6_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_6_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_6_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_6_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_6_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_6_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_6_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_6_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_6_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_6_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_6_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_6_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_6_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_6_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_6_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_6_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_6_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_6_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_6_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_6_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_6_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_6_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_6_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_6_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_6_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_6_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_6_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_6_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_6_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_6_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_6_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_6_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_6_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_6_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_6_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_6_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_will_be_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_request; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_grant; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_6_clear; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_7_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_7_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_7_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_7_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_7_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_7_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_7_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_7_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_7_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_7_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_7_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_7_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_7_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_7_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_7_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_7_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_7_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_7_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_7_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_7_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_7_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_7_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_7_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_7_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_7_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_7_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_7_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_7_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_7_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_7_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_7_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_7_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_7_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_7_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_7_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_7_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_7_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_7_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_7_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_7_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_7_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_7_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_7_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_7_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_7_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_7_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_7_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_7_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_7_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_7_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_7_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_7_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_7_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_7_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_7_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_7_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_7_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_7_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_7_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_7_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_7_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_7_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_7_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_7_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_7_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_7_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_7_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_7_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_7_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_7_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_7_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_7_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_7_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_7_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_7_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_7_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_7_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_7_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_7_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_7_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_7_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_7_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_7_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_7_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_7_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_7_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_7_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_7_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_7_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_7_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_7_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_7_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_7_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_7_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_7_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_7_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_7_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_7_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_7_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_7_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_7_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_7_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_7_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_7_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_7_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_7_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_7_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_7_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_7_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_7_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_7_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_7_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_7_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_7_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_7_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_7_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_7_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_7_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_7_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_7_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_7_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_7_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_7_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_7_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_7_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_7_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_7_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_7_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_7_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_7_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_7_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_7_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_will_be_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_request; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_grant; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_7_clear; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_8_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_8_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_8_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_8_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_8_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_8_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_8_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_8_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_8_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_8_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_8_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_8_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_8_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_8_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_8_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_8_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_8_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_8_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_8_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_8_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_8_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_8_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_8_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_8_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_8_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_8_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_8_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_8_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_8_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_8_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_8_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_8_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_8_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_8_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_8_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_8_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_8_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_8_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_8_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_8_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_8_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_8_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_8_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_8_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_8_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_8_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_8_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_8_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_8_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_8_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_8_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_8_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_8_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_8_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_8_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_8_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_8_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_8_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_8_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_8_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_8_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_8_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_8_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_8_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_8_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_8_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_8_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_8_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_8_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_8_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_8_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_8_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_8_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_8_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_8_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_8_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_8_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_8_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_8_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_8_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_8_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_8_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_8_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_8_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_8_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_8_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_8_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_8_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_8_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_8_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_8_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_8_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_8_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_8_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_8_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_8_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_8_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_8_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_8_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_8_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_8_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_8_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_8_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_8_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_8_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_8_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_8_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_8_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_8_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_8_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_8_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_8_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_8_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_8_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_8_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_8_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_8_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_8_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_8_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_8_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_8_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_8_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_8_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_8_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_8_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_8_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_8_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_8_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_8_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_8_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_8_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_8_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_will_be_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_request; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_grant; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_8_clear; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_9_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_9_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_9_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_9_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_9_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_9_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_9_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_9_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_9_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_9_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_9_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_9_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_9_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_9_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_9_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_9_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_9_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_9_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_9_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_9_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_9_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_9_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_9_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_9_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_9_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_9_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_9_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_9_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_9_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_9_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_9_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_9_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_9_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_9_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_9_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_9_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_9_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_9_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_9_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_9_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_9_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_9_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_9_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_9_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_9_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_9_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_9_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_9_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_9_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_9_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_9_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_9_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_9_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_9_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_9_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_9_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_9_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_9_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_9_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_9_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_9_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_9_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_9_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_9_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_9_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_9_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_9_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_9_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_9_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_9_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_9_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_9_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_9_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_9_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_9_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_9_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_9_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_9_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_9_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_9_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_9_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_9_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_9_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_9_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_9_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_9_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_9_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_9_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_9_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_9_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_9_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_9_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_9_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_9_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_9_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_9_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_9_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_9_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_9_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_9_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_9_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_9_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_9_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_9_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_9_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_9_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_9_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_9_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_9_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_9_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_9_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_9_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_9_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_9_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_9_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_9_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_9_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_9_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_9_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_9_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_9_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_9_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_9_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_9_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_9_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_9_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_9_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_9_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_9_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_9_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_9_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_9_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_will_be_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_request; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_grant; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_9_clear; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_10_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_10_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_10_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_10_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_10_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_10_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_10_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_10_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_10_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_10_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_10_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_10_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_10_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_10_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_10_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_10_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_10_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_10_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_10_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_10_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_10_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_10_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_10_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_10_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_10_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_10_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_10_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_10_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_10_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_10_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_10_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_10_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_10_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_10_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_10_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_10_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_10_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_10_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_10_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_10_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_10_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_10_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_10_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_10_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_10_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_10_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_10_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_10_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_10_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_10_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_10_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_10_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_10_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_10_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_10_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_10_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_10_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_10_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_10_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_10_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_10_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_10_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_10_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_10_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_10_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_10_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_10_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_10_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_10_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_10_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_10_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_10_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_10_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_10_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_10_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_10_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_10_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_10_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_10_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_10_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_10_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_10_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_10_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_10_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_10_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_10_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_10_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_10_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_10_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_10_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_10_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_10_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_10_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_10_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_10_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_10_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_10_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_10_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_10_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_10_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_10_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_10_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_10_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_10_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_10_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_10_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_10_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_10_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_10_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_10_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_10_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_10_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_10_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_10_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_10_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_10_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_10_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_10_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_10_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_10_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_10_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_10_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_10_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_10_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_10_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_10_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_10_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_10_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_10_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_10_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_10_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_10_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_will_be_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_request; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_grant; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_10_clear; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_11_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_11_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_11_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_11_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_11_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_11_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_11_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_11_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_11_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_11_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_11_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_11_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_11_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_11_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_11_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_11_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_11_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_11_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_11_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_11_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_11_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_11_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_11_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_11_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_11_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_11_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_11_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_11_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_11_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_11_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_11_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_11_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_11_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_11_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_11_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_11_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_11_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_11_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_11_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_11_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_11_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_11_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_11_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_11_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_11_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_11_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_11_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_11_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_11_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_11_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_11_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_11_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_11_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_11_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_11_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_11_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_11_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_11_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_11_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_11_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_11_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_11_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_11_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_11_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_11_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_11_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_11_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_11_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_11_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_11_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_11_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_11_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_11_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_11_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_11_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_11_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_11_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_11_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_11_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_11_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_11_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_11_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_11_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_11_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_11_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_11_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_11_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_11_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_11_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_11_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_11_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_11_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_11_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_11_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_11_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_11_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_11_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_11_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_11_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_11_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_11_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_11_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_11_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_11_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_11_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_11_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_11_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_11_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_11_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_11_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_11_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_11_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_11_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_11_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_11_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_11_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_11_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_11_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_11_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_11_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_11_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_11_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_11_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_11_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_11_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_11_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_11_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_11_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_11_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_11_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_11_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_11_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_will_be_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_request; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_grant; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_11_clear; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_12_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_12_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_12_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_12_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_12_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_12_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_12_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_12_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_12_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_12_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_12_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_12_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_12_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_12_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_12_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_12_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_12_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_12_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_12_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_12_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_12_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_12_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_12_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_12_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_12_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_12_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_12_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_12_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_12_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_12_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_12_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_12_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_12_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_12_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_12_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_12_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_12_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_12_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_12_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_12_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_12_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_12_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_12_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_12_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_12_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_12_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_12_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_12_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_12_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_12_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_12_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_12_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_12_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_12_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_12_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_12_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_12_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_12_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_12_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_12_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_12_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_12_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_12_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_12_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_12_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_12_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_12_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_12_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_12_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_12_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_12_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_12_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_12_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_12_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_12_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_12_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_12_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_12_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_12_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_12_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_12_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_12_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_12_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_12_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_12_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_12_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_12_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_12_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_12_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_12_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_12_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_12_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_12_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_12_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_12_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_12_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_12_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_12_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_12_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_12_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_12_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_12_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_12_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_12_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_12_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_12_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_12_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_12_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_12_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_12_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_12_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_12_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_12_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_12_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_12_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_12_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_12_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_12_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_12_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_12_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_12_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_12_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_12_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_12_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_12_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_12_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_12_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_12_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_12_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_12_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_12_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_12_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_will_be_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_request; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_grant; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_12_clear; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_13_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_13_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_13_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_13_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_13_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_13_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_13_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_13_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_13_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_13_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_13_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_13_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_13_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_13_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_13_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_13_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_13_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_13_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_13_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_13_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_13_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_13_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_13_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_13_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_13_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_13_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_13_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_13_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_13_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_13_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_13_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_13_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_13_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_13_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_13_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_13_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_13_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_13_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_13_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_13_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_13_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_13_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_13_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_13_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_13_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_13_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_13_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_13_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_13_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_13_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_13_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_13_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_13_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_13_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_13_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_13_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_13_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_13_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_13_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_13_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_13_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_13_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_13_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_13_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_13_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_13_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_13_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_13_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_13_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_13_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_13_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_13_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_13_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_13_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_13_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_13_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_13_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_13_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_13_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_13_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_13_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_13_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_13_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_13_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_13_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_13_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_13_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_13_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_13_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_13_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_13_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_13_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_13_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_13_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_13_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_13_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_13_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_13_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_13_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_13_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_13_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_13_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_13_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_13_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_13_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_13_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_13_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_13_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_13_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_13_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_13_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_13_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_13_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_13_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_13_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_13_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_13_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_13_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_13_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_13_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_13_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_13_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_13_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_13_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_13_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_13_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_13_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_13_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_13_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_13_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_13_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_13_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_will_be_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_request; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_grant; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_13_clear; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_14_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_14_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_14_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_14_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_14_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_14_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_14_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_14_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_14_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_14_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_14_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_14_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_14_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_14_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_14_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_14_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_14_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_14_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_14_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_14_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_14_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_14_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_14_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_14_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_14_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_14_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_14_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_14_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_14_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_14_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_14_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_14_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_14_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_14_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_14_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_14_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_14_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_14_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_14_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_14_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_14_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_14_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_14_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_14_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_14_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_14_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_14_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_14_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_14_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_14_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_14_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_14_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_14_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_14_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_14_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_14_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_14_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_14_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_14_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_14_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_14_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_14_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_14_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_14_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_14_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_14_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_14_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_14_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_14_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_14_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_14_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_14_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_14_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_14_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_14_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_14_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_14_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_14_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_14_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_14_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_14_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_14_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_14_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_14_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_14_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_14_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_14_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_14_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_14_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_14_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_14_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_14_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_14_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_14_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_14_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_14_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_14_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_14_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_14_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_14_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_14_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_14_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_14_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_14_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_14_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_14_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_14_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_14_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_14_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_14_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_14_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_14_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_14_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_14_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_14_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_14_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_14_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_14_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_14_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_14_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_14_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_14_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_14_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_14_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_14_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_14_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_14_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_14_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_14_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_14_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_14_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_14_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_will_be_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_request; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_grant; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_14_clear; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_15_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_15_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_15_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_15_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_15_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_15_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_15_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_15_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_15_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_15_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_15_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_15_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_15_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_15_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_15_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_15_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_15_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_15_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_15_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_15_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_15_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_15_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_15_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_15_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_15_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_15_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_15_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_15_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_15_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_15_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_15_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_15_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_15_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_15_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_15_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_15_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_15_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_15_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_15_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_15_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_15_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_15_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_15_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_15_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_15_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_15_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_15_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_15_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_15_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_15_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_15_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_15_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_15_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_15_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_15_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_15_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_15_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_15_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_15_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_15_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_15_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_15_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_15_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_15_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_15_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_15_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_15_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_15_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_15_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_15_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_15_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_15_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_15_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_15_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_15_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_15_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_15_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_15_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_15_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_15_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_15_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_15_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_15_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_15_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_15_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_15_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_15_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_15_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_15_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_15_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_15_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_15_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_15_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_15_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_15_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_15_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_15_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_15_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_15_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_15_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_15_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_15_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_15_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_15_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_15_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_15_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_15_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_15_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_15_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_15_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_15_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_15_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_15_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_15_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_15_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_15_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_15_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_15_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_15_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_15_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_15_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_15_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_15_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_15_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_15_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_15_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_15_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_15_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_15_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_15_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_15_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_15_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_will_be_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_request; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_grant; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_15_clear; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_16_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_16_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_16_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_16_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_16_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_16_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_16_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_16_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_16_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_16_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_16_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_16_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_16_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_16_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_16_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_16_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_16_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_16_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_16_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_16_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_16_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_16_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_16_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_16_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_16_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_16_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_16_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_16_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_16_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_16_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_16_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_16_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_16_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_16_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_16_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_16_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_16_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_16_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_16_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_16_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_16_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_16_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_16_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_16_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_16_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_16_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_16_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_16_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_16_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_16_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_16_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_16_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_16_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_16_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_16_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_16_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_16_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_16_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_16_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_16_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_16_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_16_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_16_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_16_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_16_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_16_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_16_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_16_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_16_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_16_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_16_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_16_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_16_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_16_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_16_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_16_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_16_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_16_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_16_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_16_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_16_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_16_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_16_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_16_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_16_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_16_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_16_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_16_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_16_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_16_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_16_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_16_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_16_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_16_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_16_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_16_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_16_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_16_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_16_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_16_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_16_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_16_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_16_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_16_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_16_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_16_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_16_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_16_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_16_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_16_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_16_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_16_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_16_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_16_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_16_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_16_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_16_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_16_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_16_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_16_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_16_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_16_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_16_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_16_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_16_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_16_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_16_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_16_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_16_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_16_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_16_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_16_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_will_be_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_request; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_grant; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_16_clear; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_17_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_17_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_17_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_17_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_17_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_17_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_17_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_17_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_17_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_17_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_17_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_17_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_17_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_17_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_17_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_17_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_17_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_17_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_17_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_17_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_17_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_17_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_17_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_17_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_17_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_17_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_17_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_17_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_17_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_17_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_17_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_17_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_17_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_17_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_17_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_17_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_17_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_17_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_17_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_17_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_17_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_17_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_17_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_17_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_17_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_17_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_17_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_17_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_17_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_17_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_17_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_17_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_17_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_17_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_17_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_17_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_17_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_17_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_17_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_17_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_17_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_17_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_17_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_17_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_17_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_17_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_17_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_17_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_17_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_17_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_17_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_17_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_17_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_17_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_17_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_17_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_17_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_17_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_17_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_17_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_17_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_17_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_17_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_17_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_17_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_17_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_17_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_17_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_17_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_17_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_17_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_17_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_17_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_17_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_17_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_17_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_17_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_17_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_17_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_17_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_17_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_17_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_17_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_17_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_17_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_17_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_17_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_17_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_17_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_17_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_17_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_17_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_17_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_17_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_17_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_17_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_17_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_17_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_17_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_17_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_17_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_17_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_17_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_17_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_17_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_17_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_17_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_17_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_17_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_17_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_17_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_17_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_will_be_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_request; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_grant; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_17_clear; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_18_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_18_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_18_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_18_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_18_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_18_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_18_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_18_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_18_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_18_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_18_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_18_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_18_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_18_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_18_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_18_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_18_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_18_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_18_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_18_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_18_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_18_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_18_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_18_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_18_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_18_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_18_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_18_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_18_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_18_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_18_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_18_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_18_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_18_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_18_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_18_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_18_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_18_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_18_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_18_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_18_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_18_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_18_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_18_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_18_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_18_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_18_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_18_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_18_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_18_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_18_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_18_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_18_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_18_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_18_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_18_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_18_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_18_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_18_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_18_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_18_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_18_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_18_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_18_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_18_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_18_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_18_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_18_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_18_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_18_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_18_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_18_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_18_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_18_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_18_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_18_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_18_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_18_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_18_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_18_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_18_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_18_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_18_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_18_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_18_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_18_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_18_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_18_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_18_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_18_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_18_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_18_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_18_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_18_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_18_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_18_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_18_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_18_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_18_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_18_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_18_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_18_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_18_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_18_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_18_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_18_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_18_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_18_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_18_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_18_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_18_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_18_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_18_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_18_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_18_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_18_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_18_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_18_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_18_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_18_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_18_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_18_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_18_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_18_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_18_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_18_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_18_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_18_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_18_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_18_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_18_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_18_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_will_be_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_request; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_grant; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_18_clear; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_19_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_19_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_19_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_19_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_19_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_19_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_19_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_19_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_19_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_19_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_19_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_19_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_19_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_19_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_19_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_19_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_19_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_19_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_19_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_19_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_19_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_19_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_19_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_19_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_19_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_19_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_19_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_19_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_19_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_19_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_19_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_19_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_19_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_19_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_19_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_19_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_19_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_19_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_19_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_19_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_19_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_19_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_19_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_19_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_19_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_19_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_19_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_19_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_19_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_19_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_19_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_19_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_19_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_19_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_19_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_19_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_19_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_19_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_19_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_19_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_19_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_19_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_19_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_19_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_19_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_19_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_19_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_19_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_19_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_19_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_19_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_19_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_19_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_19_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_19_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_19_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_19_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_19_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_19_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_19_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_19_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_19_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_19_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_19_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_19_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_19_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_19_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_19_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_19_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_19_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_19_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [31:0] issue_slots_19_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28]
wire [39:0] issue_slots_19_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_19_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_19_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_19_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [11:0] issue_slots_19_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_19_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_19_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_19_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_19_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_19_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_19_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28]
wire [19:0] issue_slots_19_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_19_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_19_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_19_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_19_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [3:0] issue_slots_19_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_19_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_19_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_19_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_19_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_19_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_19_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28]
wire [6:0] issue_slots_19_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28]
wire [63:0] issue_slots_19_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_19_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_19_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_19_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_19_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_19_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_19_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28]
wire [5:0] issue_slots_19_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_19_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_19_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_19_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28]
wire [4:0] issue_slots_19_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_19_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28]
wire [1:0] issue_slots_19_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_19_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28]
wire [2:0] issue_slots_19_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_will_be_valid; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_request; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_grant; // @[issue-unit-age-ordered.scala:122:28]
wire issue_slots_19_clear; // @[issue-unit-age-ordered.scala:122:28]
wire vacants_0 = ~issue_slots_0_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38]
wire _shamts_oh_1_T_1 = vacants_0; // @[issue-unit-age-ordered.scala:157:38, :163:29]
wire _shamts_oh_1_T_4 = vacants_0; // @[issue-unit-age-ordered.scala:157:38, :165:36]
wire vacants_1 = ~issue_slots_1_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38]
wire vacants_2 = ~issue_slots_2_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38]
wire vacants_3 = ~issue_slots_3_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38]
wire vacants_4 = ~issue_slots_4_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38]
wire vacants_5 = ~issue_slots_5_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38]
wire vacants_6 = ~issue_slots_6_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38]
wire vacants_7 = ~issue_slots_7_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38]
wire vacants_8 = ~issue_slots_8_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38]
wire vacants_9 = ~issue_slots_9_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38]
wire vacants_10 = ~issue_slots_10_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38]
wire vacants_11 = ~issue_slots_11_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38]
wire vacants_12 = ~issue_slots_12_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38]
wire vacants_13 = ~issue_slots_13_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38]
wire vacants_14 = ~issue_slots_14_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38]
wire vacants_15 = ~issue_slots_15_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38]
wire vacants_16 = ~issue_slots_16_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38]
wire vacants_17 = ~issue_slots_17_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38]
wire vacants_18 = ~issue_slots_18_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38]
wire vacants_19 = ~issue_slots_19_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38]
wire vacants_20 = ~io_dis_uops_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :157:82]
wire vacants_21 = ~io_dis_uops_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :157:82]
wire [1:0] shamts_oh_1_next; // @[issue-unit-age-ordered.scala:161:21]
wire [1:0] shamts_oh_2_next; // @[issue-unit-age-ordered.scala:161:21]
wire [1:0] shamts_oh_3_next; // @[issue-unit-age-ordered.scala:161:21]
wire [1:0] shamts_oh_4_next; // @[issue-unit-age-ordered.scala:161:21]
wire [1:0] shamts_oh_5_next; // @[issue-unit-age-ordered.scala:161:21]
wire [1:0] shamts_oh_6_next; // @[issue-unit-age-ordered.scala:161:21]
wire [1:0] shamts_oh_7_next; // @[issue-unit-age-ordered.scala:161:21]
wire [1:0] shamts_oh_8_next; // @[issue-unit-age-ordered.scala:161:21]
wire [1:0] shamts_oh_9_next; // @[issue-unit-age-ordered.scala:161:21]
wire [1:0] shamts_oh_10_next; // @[issue-unit-age-ordered.scala:161:21]
wire [1:0] shamts_oh_11_next; // @[issue-unit-age-ordered.scala:161:21]
wire [1:0] shamts_oh_12_next; // @[issue-unit-age-ordered.scala:161:21]
wire [1:0] shamts_oh_13_next; // @[issue-unit-age-ordered.scala:161:21]
wire [1:0] shamts_oh_14_next; // @[issue-unit-age-ordered.scala:161:21]
wire [1:0] shamts_oh_15_next; // @[issue-unit-age-ordered.scala:161:21]
wire [1:0] shamts_oh_16_next; // @[issue-unit-age-ordered.scala:161:21]
wire [1:0] shamts_oh_17_next; // @[issue-unit-age-ordered.scala:161:21]
wire [1:0] shamts_oh_18_next; // @[issue-unit-age-ordered.scala:161:21]
wire [1:0] shamts_oh_19_next; // @[issue-unit-age-ordered.scala:161:21]
wire [1:0] shamts_oh_20_next; // @[issue-unit-age-ordered.scala:161:21]
wire [1:0] shamts_oh_21_next; // @[issue-unit-age-ordered.scala:161:21]
wire [1:0] shamts_oh_1; // @[issue-unit-age-ordered.scala:158:23]
wire [1:0] shamts_oh_2; // @[issue-unit-age-ordered.scala:158:23]
wire [1:0] shamts_oh_3; // @[issue-unit-age-ordered.scala:158:23]
wire [1:0] shamts_oh_4; // @[issue-unit-age-ordered.scala:158:23]
wire [1:0] shamts_oh_5; // @[issue-unit-age-ordered.scala:158:23]
wire [1:0] shamts_oh_6; // @[issue-unit-age-ordered.scala:158:23]
wire [1:0] shamts_oh_7; // @[issue-unit-age-ordered.scala:158:23]
wire [1:0] shamts_oh_8; // @[issue-unit-age-ordered.scala:158:23]
wire [1:0] shamts_oh_9; // @[issue-unit-age-ordered.scala:158:23]
wire [1:0] shamts_oh_10; // @[issue-unit-age-ordered.scala:158:23]
wire [1:0] shamts_oh_11; // @[issue-unit-age-ordered.scala:158:23]
wire [1:0] shamts_oh_12; // @[issue-unit-age-ordered.scala:158:23]
wire [1:0] shamts_oh_13; // @[issue-unit-age-ordered.scala:158:23]
wire [1:0] shamts_oh_14; // @[issue-unit-age-ordered.scala:158:23]
wire [1:0] shamts_oh_15; // @[issue-unit-age-ordered.scala:158:23]
wire [1:0] shamts_oh_16; // @[issue-unit-age-ordered.scala:158:23]
wire [1:0] shamts_oh_17; // @[issue-unit-age-ordered.scala:158:23]
wire [1:0] shamts_oh_18; // @[issue-unit-age-ordered.scala:158:23]
wire [1:0] shamts_oh_19; // @[issue-unit-age-ordered.scala:158:23]
wire [1:0] shamts_oh_20; // @[issue-unit-age-ordered.scala:158:23]
wire [1:0] shamts_oh_21; // @[issue-unit-age-ordered.scala:158:23]
assign shamts_oh_1 = shamts_oh_1_next; // @[issue-unit-age-ordered.scala:158:23, :161:21]
assign shamts_oh_1_next = {1'h0, _shamts_oh_1_T_1}; // @[issue-unit-age-ordered.scala:161:21, :163:{29,37}, :164:13, :165:44]
assign shamts_oh_2 = shamts_oh_2_next; // @[issue-unit-age-ordered.scala:158:23, :161:21]
wire _shamts_oh_2_T = ~(|shamts_oh_1); // @[issue-unit-age-ordered.scala:158:23, :163:21]
wire _shamts_oh_2_T_1 = _shamts_oh_2_T & vacants_1; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}]
wire _shamts_oh_2_T_2 = shamts_oh_1[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28]
wire _shamts_oh_2_T_3 = ~_shamts_oh_2_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}]
wire _shamts_oh_2_T_4 = _shamts_oh_2_T_3 & vacants_1; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}]
wire [2:0] _shamts_oh_2_next_T = {shamts_oh_1, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26]
assign shamts_oh_2_next = _shamts_oh_2_T_1 ? 2'h1 : _shamts_oh_2_T_4 ? _shamts_oh_2_next_T[1:0] : shamts_oh_1; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}]
assign shamts_oh_3 = shamts_oh_3_next; // @[issue-unit-age-ordered.scala:158:23, :161:21]
wire _shamts_oh_3_T = ~(|shamts_oh_2); // @[issue-unit-age-ordered.scala:158:23, :163:21]
wire _shamts_oh_3_T_1 = _shamts_oh_3_T & vacants_2; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}]
wire _shamts_oh_3_T_2 = shamts_oh_2[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28]
wire _shamts_oh_3_T_3 = ~_shamts_oh_3_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}]
wire _shamts_oh_3_T_4 = _shamts_oh_3_T_3 & vacants_2; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}]
wire [2:0] _shamts_oh_3_next_T = {shamts_oh_2, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26]
assign shamts_oh_3_next = _shamts_oh_3_T_1 ? 2'h1 : _shamts_oh_3_T_4 ? _shamts_oh_3_next_T[1:0] : shamts_oh_2; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}]
assign shamts_oh_4 = shamts_oh_4_next; // @[issue-unit-age-ordered.scala:158:23, :161:21]
wire _shamts_oh_4_T = ~(|shamts_oh_3); // @[issue-unit-age-ordered.scala:158:23, :163:21]
wire _shamts_oh_4_T_1 = _shamts_oh_4_T & vacants_3; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}]
wire _shamts_oh_4_T_2 = shamts_oh_3[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28]
wire _shamts_oh_4_T_3 = ~_shamts_oh_4_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}]
wire _shamts_oh_4_T_4 = _shamts_oh_4_T_3 & vacants_3; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}]
wire [2:0] _shamts_oh_4_next_T = {shamts_oh_3, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26]
assign shamts_oh_4_next = _shamts_oh_4_T_1 ? 2'h1 : _shamts_oh_4_T_4 ? _shamts_oh_4_next_T[1:0] : shamts_oh_3; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}]
assign shamts_oh_5 = shamts_oh_5_next; // @[issue-unit-age-ordered.scala:158:23, :161:21]
wire _shamts_oh_5_T = ~(|shamts_oh_4); // @[issue-unit-age-ordered.scala:158:23, :163:21]
wire _shamts_oh_5_T_1 = _shamts_oh_5_T & vacants_4; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}]
wire _shamts_oh_5_T_2 = shamts_oh_4[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28]
wire _shamts_oh_5_T_3 = ~_shamts_oh_5_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}]
wire _shamts_oh_5_T_4 = _shamts_oh_5_T_3 & vacants_4; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}]
wire [2:0] _shamts_oh_5_next_T = {shamts_oh_4, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26]
assign shamts_oh_5_next = _shamts_oh_5_T_1 ? 2'h1 : _shamts_oh_5_T_4 ? _shamts_oh_5_next_T[1:0] : shamts_oh_4; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}]
assign shamts_oh_6 = shamts_oh_6_next; // @[issue-unit-age-ordered.scala:158:23, :161:21]
wire _shamts_oh_6_T = ~(|shamts_oh_5); // @[issue-unit-age-ordered.scala:158:23, :163:21]
wire _shamts_oh_6_T_1 = _shamts_oh_6_T & vacants_5; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}]
wire _shamts_oh_6_T_2 = shamts_oh_5[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28]
wire _shamts_oh_6_T_3 = ~_shamts_oh_6_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}]
wire _shamts_oh_6_T_4 = _shamts_oh_6_T_3 & vacants_5; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}]
wire [2:0] _shamts_oh_6_next_T = {shamts_oh_5, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26]
assign shamts_oh_6_next = _shamts_oh_6_T_1 ? 2'h1 : _shamts_oh_6_T_4 ? _shamts_oh_6_next_T[1:0] : shamts_oh_5; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}]
assign shamts_oh_7 = shamts_oh_7_next; // @[issue-unit-age-ordered.scala:158:23, :161:21]
wire _shamts_oh_7_T = ~(|shamts_oh_6); // @[issue-unit-age-ordered.scala:158:23, :163:21]
wire _shamts_oh_7_T_1 = _shamts_oh_7_T & vacants_6; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}]
wire _shamts_oh_7_T_2 = shamts_oh_6[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28]
wire _shamts_oh_7_T_3 = ~_shamts_oh_7_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}]
wire _shamts_oh_7_T_4 = _shamts_oh_7_T_3 & vacants_6; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}]
wire [2:0] _shamts_oh_7_next_T = {shamts_oh_6, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26]
assign shamts_oh_7_next = _shamts_oh_7_T_1 ? 2'h1 : _shamts_oh_7_T_4 ? _shamts_oh_7_next_T[1:0] : shamts_oh_6; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}]
assign shamts_oh_8 = shamts_oh_8_next; // @[issue-unit-age-ordered.scala:158:23, :161:21]
wire _shamts_oh_8_T = ~(|shamts_oh_7); // @[issue-unit-age-ordered.scala:158:23, :163:21]
wire _shamts_oh_8_T_1 = _shamts_oh_8_T & vacants_7; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}]
wire _shamts_oh_8_T_2 = shamts_oh_7[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28]
wire _shamts_oh_8_T_3 = ~_shamts_oh_8_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}]
wire _shamts_oh_8_T_4 = _shamts_oh_8_T_3 & vacants_7; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}]
wire [2:0] _shamts_oh_8_next_T = {shamts_oh_7, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26]
assign shamts_oh_8_next = _shamts_oh_8_T_1 ? 2'h1 : _shamts_oh_8_T_4 ? _shamts_oh_8_next_T[1:0] : shamts_oh_7; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}]
assign shamts_oh_9 = shamts_oh_9_next; // @[issue-unit-age-ordered.scala:158:23, :161:21]
wire _shamts_oh_9_T = ~(|shamts_oh_8); // @[issue-unit-age-ordered.scala:158:23, :163:21]
wire _shamts_oh_9_T_1 = _shamts_oh_9_T & vacants_8; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}]
wire _shamts_oh_9_T_2 = shamts_oh_8[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28]
wire _shamts_oh_9_T_3 = ~_shamts_oh_9_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}]
wire _shamts_oh_9_T_4 = _shamts_oh_9_T_3 & vacants_8; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}]
wire [2:0] _shamts_oh_9_next_T = {shamts_oh_8, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26]
assign shamts_oh_9_next = _shamts_oh_9_T_1 ? 2'h1 : _shamts_oh_9_T_4 ? _shamts_oh_9_next_T[1:0] : shamts_oh_8; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}]
assign shamts_oh_10 = shamts_oh_10_next; // @[issue-unit-age-ordered.scala:158:23, :161:21]
wire _shamts_oh_10_T = ~(|shamts_oh_9); // @[issue-unit-age-ordered.scala:158:23, :163:21]
wire _shamts_oh_10_T_1 = _shamts_oh_10_T & vacants_9; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}]
wire _shamts_oh_10_T_2 = shamts_oh_9[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28]
wire _shamts_oh_10_T_3 = ~_shamts_oh_10_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}]
wire _shamts_oh_10_T_4 = _shamts_oh_10_T_3 & vacants_9; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}]
wire [2:0] _shamts_oh_10_next_T = {shamts_oh_9, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26]
assign shamts_oh_10_next = _shamts_oh_10_T_1 ? 2'h1 : _shamts_oh_10_T_4 ? _shamts_oh_10_next_T[1:0] : shamts_oh_9; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}]
assign shamts_oh_11 = shamts_oh_11_next; // @[issue-unit-age-ordered.scala:158:23, :161:21]
wire _shamts_oh_11_T = ~(|shamts_oh_10); // @[issue-unit-age-ordered.scala:158:23, :163:21]
wire _shamts_oh_11_T_1 = _shamts_oh_11_T & vacants_10; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}]
wire _shamts_oh_11_T_2 = shamts_oh_10[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28]
wire _shamts_oh_11_T_3 = ~_shamts_oh_11_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}]
wire _shamts_oh_11_T_4 = _shamts_oh_11_T_3 & vacants_10; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}]
wire [2:0] _shamts_oh_11_next_T = {shamts_oh_10, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26]
assign shamts_oh_11_next = _shamts_oh_11_T_1 ? 2'h1 : _shamts_oh_11_T_4 ? _shamts_oh_11_next_T[1:0] : shamts_oh_10; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}]
assign shamts_oh_12 = shamts_oh_12_next; // @[issue-unit-age-ordered.scala:158:23, :161:21]
wire _shamts_oh_12_T = ~(|shamts_oh_11); // @[issue-unit-age-ordered.scala:158:23, :163:21]
wire _shamts_oh_12_T_1 = _shamts_oh_12_T & vacants_11; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}]
wire _shamts_oh_12_T_2 = shamts_oh_11[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28]
wire _shamts_oh_12_T_3 = ~_shamts_oh_12_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}]
wire _shamts_oh_12_T_4 = _shamts_oh_12_T_3 & vacants_11; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}]
wire [2:0] _shamts_oh_12_next_T = {shamts_oh_11, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26]
assign shamts_oh_12_next = _shamts_oh_12_T_1 ? 2'h1 : _shamts_oh_12_T_4 ? _shamts_oh_12_next_T[1:0] : shamts_oh_11; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}]
assign shamts_oh_13 = shamts_oh_13_next; // @[issue-unit-age-ordered.scala:158:23, :161:21]
wire _shamts_oh_13_T = ~(|shamts_oh_12); // @[issue-unit-age-ordered.scala:158:23, :163:21]
wire _shamts_oh_13_T_1 = _shamts_oh_13_T & vacants_12; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}]
wire _shamts_oh_13_T_2 = shamts_oh_12[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28]
wire _shamts_oh_13_T_3 = ~_shamts_oh_13_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}]
wire _shamts_oh_13_T_4 = _shamts_oh_13_T_3 & vacants_12; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}]
wire [2:0] _shamts_oh_13_next_T = {shamts_oh_12, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26]
assign shamts_oh_13_next = _shamts_oh_13_T_1 ? 2'h1 : _shamts_oh_13_T_4 ? _shamts_oh_13_next_T[1:0] : shamts_oh_12; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}]
assign shamts_oh_14 = shamts_oh_14_next; // @[issue-unit-age-ordered.scala:158:23, :161:21]
wire _shamts_oh_14_T = ~(|shamts_oh_13); // @[issue-unit-age-ordered.scala:158:23, :163:21]
wire _shamts_oh_14_T_1 = _shamts_oh_14_T & vacants_13; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}]
wire _shamts_oh_14_T_2 = shamts_oh_13[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28]
wire _shamts_oh_14_T_3 = ~_shamts_oh_14_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}]
wire _shamts_oh_14_T_4 = _shamts_oh_14_T_3 & vacants_13; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}]
wire [2:0] _shamts_oh_14_next_T = {shamts_oh_13, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26]
assign shamts_oh_14_next = _shamts_oh_14_T_1 ? 2'h1 : _shamts_oh_14_T_4 ? _shamts_oh_14_next_T[1:0] : shamts_oh_13; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}]
assign shamts_oh_15 = shamts_oh_15_next; // @[issue-unit-age-ordered.scala:158:23, :161:21]
wire _shamts_oh_15_T = ~(|shamts_oh_14); // @[issue-unit-age-ordered.scala:158:23, :163:21]
wire _shamts_oh_15_T_1 = _shamts_oh_15_T & vacants_14; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}]
wire _shamts_oh_15_T_2 = shamts_oh_14[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28]
wire _shamts_oh_15_T_3 = ~_shamts_oh_15_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}]
wire _shamts_oh_15_T_4 = _shamts_oh_15_T_3 & vacants_14; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}]
wire [2:0] _shamts_oh_15_next_T = {shamts_oh_14, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26]
assign shamts_oh_15_next = _shamts_oh_15_T_1 ? 2'h1 : _shamts_oh_15_T_4 ? _shamts_oh_15_next_T[1:0] : shamts_oh_14; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}]
assign shamts_oh_16 = shamts_oh_16_next; // @[issue-unit-age-ordered.scala:158:23, :161:21]
wire _shamts_oh_16_T = ~(|shamts_oh_15); // @[issue-unit-age-ordered.scala:158:23, :163:21]
wire _shamts_oh_16_T_1 = _shamts_oh_16_T & vacants_15; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}]
wire _shamts_oh_16_T_2 = shamts_oh_15[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28]
wire _shamts_oh_16_T_3 = ~_shamts_oh_16_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}]
wire _shamts_oh_16_T_4 = _shamts_oh_16_T_3 & vacants_15; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}]
wire [2:0] _shamts_oh_16_next_T = {shamts_oh_15, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26]
assign shamts_oh_16_next = _shamts_oh_16_T_1 ? 2'h1 : _shamts_oh_16_T_4 ? _shamts_oh_16_next_T[1:0] : shamts_oh_15; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}]
assign shamts_oh_17 = shamts_oh_17_next; // @[issue-unit-age-ordered.scala:158:23, :161:21]
wire _shamts_oh_17_T = ~(|shamts_oh_16); // @[issue-unit-age-ordered.scala:158:23, :163:21]
wire _shamts_oh_17_T_1 = _shamts_oh_17_T & vacants_16; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}]
wire _shamts_oh_17_T_2 = shamts_oh_16[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28]
wire _shamts_oh_17_T_3 = ~_shamts_oh_17_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}]
wire _shamts_oh_17_T_4 = _shamts_oh_17_T_3 & vacants_16; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}]
wire [2:0] _shamts_oh_17_next_T = {shamts_oh_16, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26]
assign shamts_oh_17_next = _shamts_oh_17_T_1 ? 2'h1 : _shamts_oh_17_T_4 ? _shamts_oh_17_next_T[1:0] : shamts_oh_16; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}]
assign shamts_oh_18 = shamts_oh_18_next; // @[issue-unit-age-ordered.scala:158:23, :161:21]
wire _shamts_oh_18_T = ~(|shamts_oh_17); // @[issue-unit-age-ordered.scala:158:23, :163:21]
wire _shamts_oh_18_T_1 = _shamts_oh_18_T & vacants_17; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}]
wire _shamts_oh_18_T_2 = shamts_oh_17[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28]
wire _shamts_oh_18_T_3 = ~_shamts_oh_18_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}]
wire _shamts_oh_18_T_4 = _shamts_oh_18_T_3 & vacants_17; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}]
wire [2:0] _shamts_oh_18_next_T = {shamts_oh_17, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26]
assign shamts_oh_18_next = _shamts_oh_18_T_1 ? 2'h1 : _shamts_oh_18_T_4 ? _shamts_oh_18_next_T[1:0] : shamts_oh_17; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}]
assign shamts_oh_19 = shamts_oh_19_next; // @[issue-unit-age-ordered.scala:158:23, :161:21]
wire _shamts_oh_19_T = ~(|shamts_oh_18); // @[issue-unit-age-ordered.scala:158:23, :163:21]
wire _shamts_oh_19_T_1 = _shamts_oh_19_T & vacants_18; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}]
wire _shamts_oh_19_T_2 = shamts_oh_18[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28]
wire _shamts_oh_19_T_3 = ~_shamts_oh_19_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}]
wire _shamts_oh_19_T_4 = _shamts_oh_19_T_3 & vacants_18; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}]
wire [2:0] _shamts_oh_19_next_T = {shamts_oh_18, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26]
assign shamts_oh_19_next = _shamts_oh_19_T_1 ? 2'h1 : _shamts_oh_19_T_4 ? _shamts_oh_19_next_T[1:0] : shamts_oh_18; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}]
assign shamts_oh_20 = shamts_oh_20_next; // @[issue-unit-age-ordered.scala:158:23, :161:21]
wire _shamts_oh_20_T = ~(|shamts_oh_19); // @[issue-unit-age-ordered.scala:158:23, :163:21]
wire _shamts_oh_20_T_1 = _shamts_oh_20_T & vacants_19; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}]
wire _shamts_oh_20_T_2 = shamts_oh_19[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28]
wire _shamts_oh_20_T_3 = ~_shamts_oh_20_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}]
wire _shamts_oh_20_T_4 = _shamts_oh_20_T_3 & vacants_19; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}]
wire [2:0] _shamts_oh_20_next_T = {shamts_oh_19, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26]
assign shamts_oh_20_next = _shamts_oh_20_T_1 ? 2'h1 : _shamts_oh_20_T_4 ? _shamts_oh_20_next_T[1:0] : shamts_oh_19; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}]
assign shamts_oh_21 = shamts_oh_21_next; // @[issue-unit-age-ordered.scala:158:23, :161:21]
wire _shamts_oh_21_T = shamts_oh_20 == 2'h0; // @[issue-unit-age-ordered.scala:158:23, :163:21]
wire _shamts_oh_21_T_1 = _shamts_oh_21_T & vacants_20; // @[issue-unit-age-ordered.scala:157:82, :163:{21,29}]
wire _shamts_oh_21_T_2 = shamts_oh_20[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28]
wire _shamts_oh_21_T_3 = ~_shamts_oh_21_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}]
wire _shamts_oh_21_T_4 = _shamts_oh_21_T_3 & vacants_20; // @[issue-unit-age-ordered.scala:157:82, :165:{19,36}]
wire [2:0] _shamts_oh_21_next_T = {shamts_oh_20, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26]
assign shamts_oh_21_next = _shamts_oh_21_T_1 ? 2'h1 : _shamts_oh_21_T_4 ? _shamts_oh_21_next_T[1:0] : shamts_oh_20; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}]
wire _will_be_valid_T = ~io_dis_uops_0_bits_exception_0; // @[issue-unit-age-ordered.scala:22:7, :185:57]
wire _will_be_valid_T_1 = io_dis_uops_0_valid_0 & _will_be_valid_T; // @[issue-unit-age-ordered.scala:22:7, :184:77, :185:57]
wire _will_be_valid_T_2 = ~io_dis_uops_0_bits_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :186:57]
wire _will_be_valid_T_3 = _will_be_valid_T_1 & _will_be_valid_T_2; // @[issue-unit-age-ordered.scala:184:77, :185:80, :186:57]
wire _will_be_valid_T_4 = ~io_dis_uops_0_bits_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :187:57]
wire will_be_valid_20 = _will_be_valid_T_3 & _will_be_valid_T_4; // @[issue-unit-age-ordered.scala:185:80, :186:79, :187:57]
wire _will_be_valid_T_5 = ~io_dis_uops_1_bits_exception_0; // @[issue-unit-age-ordered.scala:22:7, :185:57]
wire _will_be_valid_T_6 = io_dis_uops_1_valid_0 & _will_be_valid_T_5; // @[issue-unit-age-ordered.scala:22:7, :184:77, :185:57]
wire _will_be_valid_T_7 = ~io_dis_uops_1_bits_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :186:57]
wire _will_be_valid_T_8 = _will_be_valid_T_6 & _will_be_valid_T_7; // @[issue-unit-age-ordered.scala:184:77, :185:80, :186:57]
wire _will_be_valid_T_9 = ~io_dis_uops_1_bits_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :187:57]
wire will_be_valid_21 = _will_be_valid_T_8 & _will_be_valid_T_9; // @[issue-unit-age-ordered.scala:185:80, :186:79, :187:57]
wire _T_163 = shamts_oh_2 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28]
assign issue_slots_0_in_uop_valid = _T_163 ? issue_slots_2_will_be_valid : shamts_oh_1 == 2'h1 & issue_slots_1_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37]
assign issue_slots_0_in_uop_bits_debug_tsrc = _T_163 ? issue_slots_2_out_uop_debug_tsrc : issue_slots_1_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_debug_fsrc = _T_163 ? issue_slots_2_out_uop_debug_fsrc : issue_slots_1_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_bp_xcpt_if = _T_163 ? issue_slots_2_out_uop_bp_xcpt_if : issue_slots_1_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_bp_debug_if = _T_163 ? issue_slots_2_out_uop_bp_debug_if : issue_slots_1_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_xcpt_ma_if = _T_163 ? issue_slots_2_out_uop_xcpt_ma_if : issue_slots_1_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_xcpt_ae_if = _T_163 ? issue_slots_2_out_uop_xcpt_ae_if : issue_slots_1_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_xcpt_pf_if = _T_163 ? issue_slots_2_out_uop_xcpt_pf_if : issue_slots_1_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_fp_typ = _T_163 ? issue_slots_2_out_uop_fp_typ : issue_slots_1_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_fp_rm = _T_163 ? issue_slots_2_out_uop_fp_rm : issue_slots_1_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_fp_val = _T_163 ? issue_slots_2_out_uop_fp_val : issue_slots_1_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_fcn_op = _T_163 ? issue_slots_2_out_uop_fcn_op : issue_slots_1_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_fcn_dw = _T_163 ? issue_slots_2_out_uop_fcn_dw : issue_slots_1_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_frs3_en = _T_163 ? issue_slots_2_out_uop_frs3_en : issue_slots_1_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_lrs2_rtype = _T_163 ? issue_slots_2_out_uop_lrs2_rtype : issue_slots_1_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_lrs1_rtype = _T_163 ? issue_slots_2_out_uop_lrs1_rtype : issue_slots_1_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_dst_rtype = _T_163 ? issue_slots_2_out_uop_dst_rtype : issue_slots_1_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_lrs3 = _T_163 ? issue_slots_2_out_uop_lrs3 : issue_slots_1_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_lrs2 = _T_163 ? issue_slots_2_out_uop_lrs2 : issue_slots_1_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_lrs1 = _T_163 ? issue_slots_2_out_uop_lrs1 : issue_slots_1_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_ldst = _T_163 ? issue_slots_2_out_uop_ldst : issue_slots_1_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_ldst_is_rs1 = _T_163 ? issue_slots_2_out_uop_ldst_is_rs1 : issue_slots_1_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_csr_cmd = _T_163 ? issue_slots_2_out_uop_csr_cmd : issue_slots_1_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_flush_on_commit = _T_163 ? issue_slots_2_out_uop_flush_on_commit : issue_slots_1_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_is_unique = _T_163 ? issue_slots_2_out_uop_is_unique : issue_slots_1_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_uses_stq = _T_163 ? issue_slots_2_out_uop_uses_stq : issue_slots_1_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_uses_ldq = _T_163 ? issue_slots_2_out_uop_uses_ldq : issue_slots_1_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_mem_signed = _T_163 ? issue_slots_2_out_uop_mem_signed : issue_slots_1_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_mem_size = _T_163 ? issue_slots_2_out_uop_mem_size : issue_slots_1_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_mem_cmd = _T_163 ? issue_slots_2_out_uop_mem_cmd : issue_slots_1_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_exc_cause = _T_163 ? issue_slots_2_out_uop_exc_cause : issue_slots_1_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_exception = _T_163 ? issue_slots_2_out_uop_exception : issue_slots_1_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_stale_pdst = _T_163 ? issue_slots_2_out_uop_stale_pdst : issue_slots_1_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_ppred_busy = _T_163 ? issue_slots_2_out_uop_ppred_busy : issue_slots_1_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_prs3_busy = _T_163 ? issue_slots_2_out_uop_prs3_busy : issue_slots_1_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_prs2_busy = _T_163 ? issue_slots_2_out_uop_prs2_busy : issue_slots_1_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_prs1_busy = _T_163 ? issue_slots_2_out_uop_prs1_busy : issue_slots_1_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_ppred = _T_163 ? issue_slots_2_out_uop_ppred : issue_slots_1_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_prs3 = _T_163 ? issue_slots_2_out_uop_prs3 : issue_slots_1_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_prs2 = _T_163 ? issue_slots_2_out_uop_prs2 : issue_slots_1_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_prs1 = _T_163 ? issue_slots_2_out_uop_prs1 : issue_slots_1_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_pdst = _T_163 ? issue_slots_2_out_uop_pdst : issue_slots_1_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_rxq_idx = _T_163 ? issue_slots_2_out_uop_rxq_idx : issue_slots_1_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_stq_idx = _T_163 ? issue_slots_2_out_uop_stq_idx : issue_slots_1_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_ldq_idx = _T_163 ? issue_slots_2_out_uop_ldq_idx : issue_slots_1_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_rob_idx = _T_163 ? issue_slots_2_out_uop_rob_idx : issue_slots_1_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_fp_ctrl_vec = _T_163 ? issue_slots_2_out_uop_fp_ctrl_vec : issue_slots_1_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_fp_ctrl_wflags = _T_163 ? issue_slots_2_out_uop_fp_ctrl_wflags : issue_slots_1_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_fp_ctrl_sqrt = _T_163 ? issue_slots_2_out_uop_fp_ctrl_sqrt : issue_slots_1_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_fp_ctrl_div = _T_163 ? issue_slots_2_out_uop_fp_ctrl_div : issue_slots_1_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_fp_ctrl_fma = _T_163 ? issue_slots_2_out_uop_fp_ctrl_fma : issue_slots_1_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_fp_ctrl_fastpipe = _T_163 ? issue_slots_2_out_uop_fp_ctrl_fastpipe : issue_slots_1_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_fp_ctrl_toint = _T_163 ? issue_slots_2_out_uop_fp_ctrl_toint : issue_slots_1_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_fp_ctrl_fromint = _T_163 ? issue_slots_2_out_uop_fp_ctrl_fromint : issue_slots_1_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_fp_ctrl_typeTagOut = _T_163 ? issue_slots_2_out_uop_fp_ctrl_typeTagOut : issue_slots_1_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_fp_ctrl_typeTagIn = _T_163 ? issue_slots_2_out_uop_fp_ctrl_typeTagIn : issue_slots_1_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_fp_ctrl_swap23 = _T_163 ? issue_slots_2_out_uop_fp_ctrl_swap23 : issue_slots_1_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_fp_ctrl_swap12 = _T_163 ? issue_slots_2_out_uop_fp_ctrl_swap12 : issue_slots_1_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_fp_ctrl_ren3 = _T_163 ? issue_slots_2_out_uop_fp_ctrl_ren3 : issue_slots_1_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_fp_ctrl_ren2 = _T_163 ? issue_slots_2_out_uop_fp_ctrl_ren2 : issue_slots_1_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_fp_ctrl_ren1 = _T_163 ? issue_slots_2_out_uop_fp_ctrl_ren1 : issue_slots_1_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_fp_ctrl_wen = _T_163 ? issue_slots_2_out_uop_fp_ctrl_wen : issue_slots_1_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_fp_ctrl_ldst = _T_163 ? issue_slots_2_out_uop_fp_ctrl_ldst : issue_slots_1_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_op2_sel = _T_163 ? issue_slots_2_out_uop_op2_sel : issue_slots_1_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_op1_sel = _T_163 ? issue_slots_2_out_uop_op1_sel : issue_slots_1_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_imm_packed = _T_163 ? issue_slots_2_out_uop_imm_packed : issue_slots_1_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_pimm = _T_163 ? issue_slots_2_out_uop_pimm : issue_slots_1_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_imm_sel = _T_163 ? issue_slots_2_out_uop_imm_sel : issue_slots_1_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_imm_rename = _T_163 ? issue_slots_2_out_uop_imm_rename : issue_slots_1_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_taken = _T_163 ? issue_slots_2_out_uop_taken : issue_slots_1_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_pc_lob = _T_163 ? issue_slots_2_out_uop_pc_lob : issue_slots_1_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_edge_inst = _T_163 ? issue_slots_2_out_uop_edge_inst : issue_slots_1_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_ftq_idx = _T_163 ? issue_slots_2_out_uop_ftq_idx : issue_slots_1_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_is_mov = _T_163 ? issue_slots_2_out_uop_is_mov : issue_slots_1_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_is_rocc = _T_163 ? issue_slots_2_out_uop_is_rocc : issue_slots_1_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_is_sys_pc2epc = _T_163 ? issue_slots_2_out_uop_is_sys_pc2epc : issue_slots_1_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_is_eret = _T_163 ? issue_slots_2_out_uop_is_eret : issue_slots_1_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_is_amo = _T_163 ? issue_slots_2_out_uop_is_amo : issue_slots_1_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_is_sfence = _T_163 ? issue_slots_2_out_uop_is_sfence : issue_slots_1_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_is_fencei = _T_163 ? issue_slots_2_out_uop_is_fencei : issue_slots_1_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_is_fence = _T_163 ? issue_slots_2_out_uop_is_fence : issue_slots_1_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_is_sfb = _T_163 ? issue_slots_2_out_uop_is_sfb : issue_slots_1_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_br_type = _T_163 ? issue_slots_2_out_uop_br_type : issue_slots_1_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_br_tag = _T_163 ? issue_slots_2_out_uop_br_tag : issue_slots_1_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_br_mask = _T_163 ? issue_slots_2_out_uop_br_mask : issue_slots_1_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_dis_col_sel = _T_163 ? issue_slots_2_out_uop_dis_col_sel : issue_slots_1_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_iw_p3_bypass_hint = _T_163 ? issue_slots_2_out_uop_iw_p3_bypass_hint : issue_slots_1_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_iw_p2_bypass_hint = _T_163 ? issue_slots_2_out_uop_iw_p2_bypass_hint : issue_slots_1_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_iw_p1_bypass_hint = _T_163 ? issue_slots_2_out_uop_iw_p1_bypass_hint : issue_slots_1_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_iw_p2_speculative_child = _T_163 ? issue_slots_2_out_uop_iw_p2_speculative_child : issue_slots_1_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_iw_p1_speculative_child = _T_163 ? issue_slots_2_out_uop_iw_p1_speculative_child : issue_slots_1_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_iw_issued = _T_163 ? issue_slots_2_out_uop_iw_issued : issue_slots_1_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_fu_code_0 = _T_163 ? issue_slots_2_out_uop_fu_code_0 : issue_slots_1_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_fu_code_1 = _T_163 ? issue_slots_2_out_uop_fu_code_1 : issue_slots_1_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_fu_code_2 = _T_163 ? issue_slots_2_out_uop_fu_code_2 : issue_slots_1_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_fu_code_3 = _T_163 ? issue_slots_2_out_uop_fu_code_3 : issue_slots_1_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_fu_code_4 = _T_163 ? issue_slots_2_out_uop_fu_code_4 : issue_slots_1_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_fu_code_5 = _T_163 ? issue_slots_2_out_uop_fu_code_5 : issue_slots_1_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_fu_code_6 = _T_163 ? issue_slots_2_out_uop_fu_code_6 : issue_slots_1_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_fu_code_7 = _T_163 ? issue_slots_2_out_uop_fu_code_7 : issue_slots_1_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_fu_code_8 = _T_163 ? issue_slots_2_out_uop_fu_code_8 : issue_slots_1_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_fu_code_9 = _T_163 ? issue_slots_2_out_uop_fu_code_9 : issue_slots_1_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_iq_type_0 = _T_163 ? issue_slots_2_out_uop_iq_type_0 : issue_slots_1_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_iq_type_1 = _T_163 ? issue_slots_2_out_uop_iq_type_1 : issue_slots_1_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_iq_type_2 = _T_163 ? issue_slots_2_out_uop_iq_type_2 : issue_slots_1_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_iq_type_3 = _T_163 ? issue_slots_2_out_uop_iq_type_3 : issue_slots_1_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_debug_pc = _T_163 ? issue_slots_2_out_uop_debug_pc : issue_slots_1_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_is_rvc = _T_163 ? issue_slots_2_out_uop_is_rvc : issue_slots_1_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_debug_inst = _T_163 ? issue_slots_2_out_uop_debug_inst : issue_slots_1_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_0_in_uop_bits_inst = _T_163 ? issue_slots_2_out_uop_inst : issue_slots_1_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
wire _T_165 = shamts_oh_3 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28]
assign issue_slots_1_in_uop_valid = _T_165 ? issue_slots_3_will_be_valid : shamts_oh_2 == 2'h1 & issue_slots_2_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37]
assign issue_slots_1_in_uop_bits_debug_tsrc = _T_165 ? issue_slots_3_out_uop_debug_tsrc : issue_slots_2_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_debug_fsrc = _T_165 ? issue_slots_3_out_uop_debug_fsrc : issue_slots_2_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_bp_xcpt_if = _T_165 ? issue_slots_3_out_uop_bp_xcpt_if : issue_slots_2_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_bp_debug_if = _T_165 ? issue_slots_3_out_uop_bp_debug_if : issue_slots_2_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_xcpt_ma_if = _T_165 ? issue_slots_3_out_uop_xcpt_ma_if : issue_slots_2_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_xcpt_ae_if = _T_165 ? issue_slots_3_out_uop_xcpt_ae_if : issue_slots_2_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_xcpt_pf_if = _T_165 ? issue_slots_3_out_uop_xcpt_pf_if : issue_slots_2_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_fp_typ = _T_165 ? issue_slots_3_out_uop_fp_typ : issue_slots_2_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_fp_rm = _T_165 ? issue_slots_3_out_uop_fp_rm : issue_slots_2_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_fp_val = _T_165 ? issue_slots_3_out_uop_fp_val : issue_slots_2_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_fcn_op = _T_165 ? issue_slots_3_out_uop_fcn_op : issue_slots_2_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_fcn_dw = _T_165 ? issue_slots_3_out_uop_fcn_dw : issue_slots_2_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_frs3_en = _T_165 ? issue_slots_3_out_uop_frs3_en : issue_slots_2_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_lrs2_rtype = _T_165 ? issue_slots_3_out_uop_lrs2_rtype : issue_slots_2_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_lrs1_rtype = _T_165 ? issue_slots_3_out_uop_lrs1_rtype : issue_slots_2_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_dst_rtype = _T_165 ? issue_slots_3_out_uop_dst_rtype : issue_slots_2_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_lrs3 = _T_165 ? issue_slots_3_out_uop_lrs3 : issue_slots_2_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_lrs2 = _T_165 ? issue_slots_3_out_uop_lrs2 : issue_slots_2_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_lrs1 = _T_165 ? issue_slots_3_out_uop_lrs1 : issue_slots_2_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_ldst = _T_165 ? issue_slots_3_out_uop_ldst : issue_slots_2_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_ldst_is_rs1 = _T_165 ? issue_slots_3_out_uop_ldst_is_rs1 : issue_slots_2_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_csr_cmd = _T_165 ? issue_slots_3_out_uop_csr_cmd : issue_slots_2_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_flush_on_commit = _T_165 ? issue_slots_3_out_uop_flush_on_commit : issue_slots_2_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_is_unique = _T_165 ? issue_slots_3_out_uop_is_unique : issue_slots_2_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_uses_stq = _T_165 ? issue_slots_3_out_uop_uses_stq : issue_slots_2_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_uses_ldq = _T_165 ? issue_slots_3_out_uop_uses_ldq : issue_slots_2_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_mem_signed = _T_165 ? issue_slots_3_out_uop_mem_signed : issue_slots_2_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_mem_size = _T_165 ? issue_slots_3_out_uop_mem_size : issue_slots_2_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_mem_cmd = _T_165 ? issue_slots_3_out_uop_mem_cmd : issue_slots_2_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_exc_cause = _T_165 ? issue_slots_3_out_uop_exc_cause : issue_slots_2_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_exception = _T_165 ? issue_slots_3_out_uop_exception : issue_slots_2_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_stale_pdst = _T_165 ? issue_slots_3_out_uop_stale_pdst : issue_slots_2_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_ppred_busy = _T_165 ? issue_slots_3_out_uop_ppred_busy : issue_slots_2_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_prs3_busy = _T_165 ? issue_slots_3_out_uop_prs3_busy : issue_slots_2_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_prs2_busy = _T_165 ? issue_slots_3_out_uop_prs2_busy : issue_slots_2_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_prs1_busy = _T_165 ? issue_slots_3_out_uop_prs1_busy : issue_slots_2_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_ppred = _T_165 ? issue_slots_3_out_uop_ppred : issue_slots_2_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_prs3 = _T_165 ? issue_slots_3_out_uop_prs3 : issue_slots_2_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_prs2 = _T_165 ? issue_slots_3_out_uop_prs2 : issue_slots_2_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_prs1 = _T_165 ? issue_slots_3_out_uop_prs1 : issue_slots_2_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_pdst = _T_165 ? issue_slots_3_out_uop_pdst : issue_slots_2_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_rxq_idx = _T_165 ? issue_slots_3_out_uop_rxq_idx : issue_slots_2_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_stq_idx = _T_165 ? issue_slots_3_out_uop_stq_idx : issue_slots_2_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_ldq_idx = _T_165 ? issue_slots_3_out_uop_ldq_idx : issue_slots_2_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_rob_idx = _T_165 ? issue_slots_3_out_uop_rob_idx : issue_slots_2_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_fp_ctrl_vec = _T_165 ? issue_slots_3_out_uop_fp_ctrl_vec : issue_slots_2_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_fp_ctrl_wflags = _T_165 ? issue_slots_3_out_uop_fp_ctrl_wflags : issue_slots_2_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_fp_ctrl_sqrt = _T_165 ? issue_slots_3_out_uop_fp_ctrl_sqrt : issue_slots_2_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_fp_ctrl_div = _T_165 ? issue_slots_3_out_uop_fp_ctrl_div : issue_slots_2_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_fp_ctrl_fma = _T_165 ? issue_slots_3_out_uop_fp_ctrl_fma : issue_slots_2_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_fp_ctrl_fastpipe = _T_165 ? issue_slots_3_out_uop_fp_ctrl_fastpipe : issue_slots_2_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_fp_ctrl_toint = _T_165 ? issue_slots_3_out_uop_fp_ctrl_toint : issue_slots_2_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_fp_ctrl_fromint = _T_165 ? issue_slots_3_out_uop_fp_ctrl_fromint : issue_slots_2_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_fp_ctrl_typeTagOut = _T_165 ? issue_slots_3_out_uop_fp_ctrl_typeTagOut : issue_slots_2_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_fp_ctrl_typeTagIn = _T_165 ? issue_slots_3_out_uop_fp_ctrl_typeTagIn : issue_slots_2_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_fp_ctrl_swap23 = _T_165 ? issue_slots_3_out_uop_fp_ctrl_swap23 : issue_slots_2_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_fp_ctrl_swap12 = _T_165 ? issue_slots_3_out_uop_fp_ctrl_swap12 : issue_slots_2_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_fp_ctrl_ren3 = _T_165 ? issue_slots_3_out_uop_fp_ctrl_ren3 : issue_slots_2_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_fp_ctrl_ren2 = _T_165 ? issue_slots_3_out_uop_fp_ctrl_ren2 : issue_slots_2_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_fp_ctrl_ren1 = _T_165 ? issue_slots_3_out_uop_fp_ctrl_ren1 : issue_slots_2_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_fp_ctrl_wen = _T_165 ? issue_slots_3_out_uop_fp_ctrl_wen : issue_slots_2_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_fp_ctrl_ldst = _T_165 ? issue_slots_3_out_uop_fp_ctrl_ldst : issue_slots_2_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_op2_sel = _T_165 ? issue_slots_3_out_uop_op2_sel : issue_slots_2_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_op1_sel = _T_165 ? issue_slots_3_out_uop_op1_sel : issue_slots_2_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_imm_packed = _T_165 ? issue_slots_3_out_uop_imm_packed : issue_slots_2_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_pimm = _T_165 ? issue_slots_3_out_uop_pimm : issue_slots_2_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_imm_sel = _T_165 ? issue_slots_3_out_uop_imm_sel : issue_slots_2_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_imm_rename = _T_165 ? issue_slots_3_out_uop_imm_rename : issue_slots_2_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_taken = _T_165 ? issue_slots_3_out_uop_taken : issue_slots_2_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_pc_lob = _T_165 ? issue_slots_3_out_uop_pc_lob : issue_slots_2_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_edge_inst = _T_165 ? issue_slots_3_out_uop_edge_inst : issue_slots_2_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_ftq_idx = _T_165 ? issue_slots_3_out_uop_ftq_idx : issue_slots_2_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_is_mov = _T_165 ? issue_slots_3_out_uop_is_mov : issue_slots_2_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_is_rocc = _T_165 ? issue_slots_3_out_uop_is_rocc : issue_slots_2_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_is_sys_pc2epc = _T_165 ? issue_slots_3_out_uop_is_sys_pc2epc : issue_slots_2_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_is_eret = _T_165 ? issue_slots_3_out_uop_is_eret : issue_slots_2_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_is_amo = _T_165 ? issue_slots_3_out_uop_is_amo : issue_slots_2_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_is_sfence = _T_165 ? issue_slots_3_out_uop_is_sfence : issue_slots_2_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_is_fencei = _T_165 ? issue_slots_3_out_uop_is_fencei : issue_slots_2_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_is_fence = _T_165 ? issue_slots_3_out_uop_is_fence : issue_slots_2_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_is_sfb = _T_165 ? issue_slots_3_out_uop_is_sfb : issue_slots_2_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_br_type = _T_165 ? issue_slots_3_out_uop_br_type : issue_slots_2_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_br_tag = _T_165 ? issue_slots_3_out_uop_br_tag : issue_slots_2_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_br_mask = _T_165 ? issue_slots_3_out_uop_br_mask : issue_slots_2_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_dis_col_sel = _T_165 ? issue_slots_3_out_uop_dis_col_sel : issue_slots_2_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_iw_p3_bypass_hint = _T_165 ? issue_slots_3_out_uop_iw_p3_bypass_hint : issue_slots_2_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_iw_p2_bypass_hint = _T_165 ? issue_slots_3_out_uop_iw_p2_bypass_hint : issue_slots_2_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_iw_p1_bypass_hint = _T_165 ? issue_slots_3_out_uop_iw_p1_bypass_hint : issue_slots_2_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_iw_p2_speculative_child = _T_165 ? issue_slots_3_out_uop_iw_p2_speculative_child : issue_slots_2_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_iw_p1_speculative_child = _T_165 ? issue_slots_3_out_uop_iw_p1_speculative_child : issue_slots_2_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_iw_issued = _T_165 ? issue_slots_3_out_uop_iw_issued : issue_slots_2_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_fu_code_0 = _T_165 ? issue_slots_3_out_uop_fu_code_0 : issue_slots_2_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_fu_code_1 = _T_165 ? issue_slots_3_out_uop_fu_code_1 : issue_slots_2_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_fu_code_2 = _T_165 ? issue_slots_3_out_uop_fu_code_2 : issue_slots_2_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_fu_code_3 = _T_165 ? issue_slots_3_out_uop_fu_code_3 : issue_slots_2_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_fu_code_4 = _T_165 ? issue_slots_3_out_uop_fu_code_4 : issue_slots_2_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_fu_code_5 = _T_165 ? issue_slots_3_out_uop_fu_code_5 : issue_slots_2_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_fu_code_6 = _T_165 ? issue_slots_3_out_uop_fu_code_6 : issue_slots_2_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_fu_code_7 = _T_165 ? issue_slots_3_out_uop_fu_code_7 : issue_slots_2_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_fu_code_8 = _T_165 ? issue_slots_3_out_uop_fu_code_8 : issue_slots_2_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_fu_code_9 = _T_165 ? issue_slots_3_out_uop_fu_code_9 : issue_slots_2_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_iq_type_0 = _T_165 ? issue_slots_3_out_uop_iq_type_0 : issue_slots_2_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_iq_type_1 = _T_165 ? issue_slots_3_out_uop_iq_type_1 : issue_slots_2_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_iq_type_2 = _T_165 ? issue_slots_3_out_uop_iq_type_2 : issue_slots_2_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_iq_type_3 = _T_165 ? issue_slots_3_out_uop_iq_type_3 : issue_slots_2_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_debug_pc = _T_165 ? issue_slots_3_out_uop_debug_pc : issue_slots_2_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_is_rvc = _T_165 ? issue_slots_3_out_uop_is_rvc : issue_slots_2_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_debug_inst = _T_165 ? issue_slots_3_out_uop_debug_inst : issue_slots_2_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_1_in_uop_bits_inst = _T_165 ? issue_slots_3_out_uop_inst : issue_slots_2_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign _issue_slots_1_clear_T = |shamts_oh_1; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49]
assign issue_slots_1_clear = _issue_slots_1_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49]
wire _T_167 = shamts_oh_4 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28]
assign issue_slots_2_in_uop_valid = _T_167 ? issue_slots_4_will_be_valid : shamts_oh_3 == 2'h1 & issue_slots_3_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37]
assign issue_slots_2_in_uop_bits_debug_tsrc = _T_167 ? issue_slots_4_out_uop_debug_tsrc : issue_slots_3_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_debug_fsrc = _T_167 ? issue_slots_4_out_uop_debug_fsrc : issue_slots_3_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_bp_xcpt_if = _T_167 ? issue_slots_4_out_uop_bp_xcpt_if : issue_slots_3_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_bp_debug_if = _T_167 ? issue_slots_4_out_uop_bp_debug_if : issue_slots_3_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_xcpt_ma_if = _T_167 ? issue_slots_4_out_uop_xcpt_ma_if : issue_slots_3_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_xcpt_ae_if = _T_167 ? issue_slots_4_out_uop_xcpt_ae_if : issue_slots_3_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_xcpt_pf_if = _T_167 ? issue_slots_4_out_uop_xcpt_pf_if : issue_slots_3_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_fp_typ = _T_167 ? issue_slots_4_out_uop_fp_typ : issue_slots_3_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_fp_rm = _T_167 ? issue_slots_4_out_uop_fp_rm : issue_slots_3_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_fp_val = _T_167 ? issue_slots_4_out_uop_fp_val : issue_slots_3_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_fcn_op = _T_167 ? issue_slots_4_out_uop_fcn_op : issue_slots_3_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_fcn_dw = _T_167 ? issue_slots_4_out_uop_fcn_dw : issue_slots_3_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_frs3_en = _T_167 ? issue_slots_4_out_uop_frs3_en : issue_slots_3_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_lrs2_rtype = _T_167 ? issue_slots_4_out_uop_lrs2_rtype : issue_slots_3_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_lrs1_rtype = _T_167 ? issue_slots_4_out_uop_lrs1_rtype : issue_slots_3_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_dst_rtype = _T_167 ? issue_slots_4_out_uop_dst_rtype : issue_slots_3_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_lrs3 = _T_167 ? issue_slots_4_out_uop_lrs3 : issue_slots_3_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_lrs2 = _T_167 ? issue_slots_4_out_uop_lrs2 : issue_slots_3_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_lrs1 = _T_167 ? issue_slots_4_out_uop_lrs1 : issue_slots_3_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_ldst = _T_167 ? issue_slots_4_out_uop_ldst : issue_slots_3_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_ldst_is_rs1 = _T_167 ? issue_slots_4_out_uop_ldst_is_rs1 : issue_slots_3_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_csr_cmd = _T_167 ? issue_slots_4_out_uop_csr_cmd : issue_slots_3_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_flush_on_commit = _T_167 ? issue_slots_4_out_uop_flush_on_commit : issue_slots_3_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_is_unique = _T_167 ? issue_slots_4_out_uop_is_unique : issue_slots_3_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_uses_stq = _T_167 ? issue_slots_4_out_uop_uses_stq : issue_slots_3_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_uses_ldq = _T_167 ? issue_slots_4_out_uop_uses_ldq : issue_slots_3_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_mem_signed = _T_167 ? issue_slots_4_out_uop_mem_signed : issue_slots_3_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_mem_size = _T_167 ? issue_slots_4_out_uop_mem_size : issue_slots_3_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_mem_cmd = _T_167 ? issue_slots_4_out_uop_mem_cmd : issue_slots_3_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_exc_cause = _T_167 ? issue_slots_4_out_uop_exc_cause : issue_slots_3_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_exception = _T_167 ? issue_slots_4_out_uop_exception : issue_slots_3_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_stale_pdst = _T_167 ? issue_slots_4_out_uop_stale_pdst : issue_slots_3_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_ppred_busy = _T_167 ? issue_slots_4_out_uop_ppred_busy : issue_slots_3_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_prs3_busy = _T_167 ? issue_slots_4_out_uop_prs3_busy : issue_slots_3_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_prs2_busy = _T_167 ? issue_slots_4_out_uop_prs2_busy : issue_slots_3_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_prs1_busy = _T_167 ? issue_slots_4_out_uop_prs1_busy : issue_slots_3_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_ppred = _T_167 ? issue_slots_4_out_uop_ppred : issue_slots_3_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_prs3 = _T_167 ? issue_slots_4_out_uop_prs3 : issue_slots_3_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_prs2 = _T_167 ? issue_slots_4_out_uop_prs2 : issue_slots_3_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_prs1 = _T_167 ? issue_slots_4_out_uop_prs1 : issue_slots_3_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_pdst = _T_167 ? issue_slots_4_out_uop_pdst : issue_slots_3_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_rxq_idx = _T_167 ? issue_slots_4_out_uop_rxq_idx : issue_slots_3_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_stq_idx = _T_167 ? issue_slots_4_out_uop_stq_idx : issue_slots_3_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_ldq_idx = _T_167 ? issue_slots_4_out_uop_ldq_idx : issue_slots_3_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_rob_idx = _T_167 ? issue_slots_4_out_uop_rob_idx : issue_slots_3_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_fp_ctrl_vec = _T_167 ? issue_slots_4_out_uop_fp_ctrl_vec : issue_slots_3_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_fp_ctrl_wflags = _T_167 ? issue_slots_4_out_uop_fp_ctrl_wflags : issue_slots_3_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_fp_ctrl_sqrt = _T_167 ? issue_slots_4_out_uop_fp_ctrl_sqrt : issue_slots_3_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_fp_ctrl_div = _T_167 ? issue_slots_4_out_uop_fp_ctrl_div : issue_slots_3_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_fp_ctrl_fma = _T_167 ? issue_slots_4_out_uop_fp_ctrl_fma : issue_slots_3_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_fp_ctrl_fastpipe = _T_167 ? issue_slots_4_out_uop_fp_ctrl_fastpipe : issue_slots_3_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_fp_ctrl_toint = _T_167 ? issue_slots_4_out_uop_fp_ctrl_toint : issue_slots_3_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_fp_ctrl_fromint = _T_167 ? issue_slots_4_out_uop_fp_ctrl_fromint : issue_slots_3_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_fp_ctrl_typeTagOut = _T_167 ? issue_slots_4_out_uop_fp_ctrl_typeTagOut : issue_slots_3_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_fp_ctrl_typeTagIn = _T_167 ? issue_slots_4_out_uop_fp_ctrl_typeTagIn : issue_slots_3_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_fp_ctrl_swap23 = _T_167 ? issue_slots_4_out_uop_fp_ctrl_swap23 : issue_slots_3_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_fp_ctrl_swap12 = _T_167 ? issue_slots_4_out_uop_fp_ctrl_swap12 : issue_slots_3_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_fp_ctrl_ren3 = _T_167 ? issue_slots_4_out_uop_fp_ctrl_ren3 : issue_slots_3_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_fp_ctrl_ren2 = _T_167 ? issue_slots_4_out_uop_fp_ctrl_ren2 : issue_slots_3_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_fp_ctrl_ren1 = _T_167 ? issue_slots_4_out_uop_fp_ctrl_ren1 : issue_slots_3_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_fp_ctrl_wen = _T_167 ? issue_slots_4_out_uop_fp_ctrl_wen : issue_slots_3_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_fp_ctrl_ldst = _T_167 ? issue_slots_4_out_uop_fp_ctrl_ldst : issue_slots_3_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_op2_sel = _T_167 ? issue_slots_4_out_uop_op2_sel : issue_slots_3_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_op1_sel = _T_167 ? issue_slots_4_out_uop_op1_sel : issue_slots_3_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_imm_packed = _T_167 ? issue_slots_4_out_uop_imm_packed : issue_slots_3_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_pimm = _T_167 ? issue_slots_4_out_uop_pimm : issue_slots_3_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_imm_sel = _T_167 ? issue_slots_4_out_uop_imm_sel : issue_slots_3_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_imm_rename = _T_167 ? issue_slots_4_out_uop_imm_rename : issue_slots_3_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_taken = _T_167 ? issue_slots_4_out_uop_taken : issue_slots_3_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_pc_lob = _T_167 ? issue_slots_4_out_uop_pc_lob : issue_slots_3_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_edge_inst = _T_167 ? issue_slots_4_out_uop_edge_inst : issue_slots_3_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_ftq_idx = _T_167 ? issue_slots_4_out_uop_ftq_idx : issue_slots_3_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_is_mov = _T_167 ? issue_slots_4_out_uop_is_mov : issue_slots_3_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_is_rocc = _T_167 ? issue_slots_4_out_uop_is_rocc : issue_slots_3_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_is_sys_pc2epc = _T_167 ? issue_slots_4_out_uop_is_sys_pc2epc : issue_slots_3_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_is_eret = _T_167 ? issue_slots_4_out_uop_is_eret : issue_slots_3_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_is_amo = _T_167 ? issue_slots_4_out_uop_is_amo : issue_slots_3_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_is_sfence = _T_167 ? issue_slots_4_out_uop_is_sfence : issue_slots_3_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_is_fencei = _T_167 ? issue_slots_4_out_uop_is_fencei : issue_slots_3_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_is_fence = _T_167 ? issue_slots_4_out_uop_is_fence : issue_slots_3_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_is_sfb = _T_167 ? issue_slots_4_out_uop_is_sfb : issue_slots_3_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_br_type = _T_167 ? issue_slots_4_out_uop_br_type : issue_slots_3_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_br_tag = _T_167 ? issue_slots_4_out_uop_br_tag : issue_slots_3_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_br_mask = _T_167 ? issue_slots_4_out_uop_br_mask : issue_slots_3_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_dis_col_sel = _T_167 ? issue_slots_4_out_uop_dis_col_sel : issue_slots_3_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_iw_p3_bypass_hint = _T_167 ? issue_slots_4_out_uop_iw_p3_bypass_hint : issue_slots_3_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_iw_p2_bypass_hint = _T_167 ? issue_slots_4_out_uop_iw_p2_bypass_hint : issue_slots_3_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_iw_p1_bypass_hint = _T_167 ? issue_slots_4_out_uop_iw_p1_bypass_hint : issue_slots_3_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_iw_p2_speculative_child = _T_167 ? issue_slots_4_out_uop_iw_p2_speculative_child : issue_slots_3_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_iw_p1_speculative_child = _T_167 ? issue_slots_4_out_uop_iw_p1_speculative_child : issue_slots_3_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_iw_issued = _T_167 ? issue_slots_4_out_uop_iw_issued : issue_slots_3_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_fu_code_0 = _T_167 ? issue_slots_4_out_uop_fu_code_0 : issue_slots_3_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_fu_code_1 = _T_167 ? issue_slots_4_out_uop_fu_code_1 : issue_slots_3_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_fu_code_2 = _T_167 ? issue_slots_4_out_uop_fu_code_2 : issue_slots_3_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_fu_code_3 = _T_167 ? issue_slots_4_out_uop_fu_code_3 : issue_slots_3_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_fu_code_4 = _T_167 ? issue_slots_4_out_uop_fu_code_4 : issue_slots_3_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_fu_code_5 = _T_167 ? issue_slots_4_out_uop_fu_code_5 : issue_slots_3_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_fu_code_6 = _T_167 ? issue_slots_4_out_uop_fu_code_6 : issue_slots_3_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_fu_code_7 = _T_167 ? issue_slots_4_out_uop_fu_code_7 : issue_slots_3_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_fu_code_8 = _T_167 ? issue_slots_4_out_uop_fu_code_8 : issue_slots_3_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_fu_code_9 = _T_167 ? issue_slots_4_out_uop_fu_code_9 : issue_slots_3_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_iq_type_0 = _T_167 ? issue_slots_4_out_uop_iq_type_0 : issue_slots_3_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_iq_type_1 = _T_167 ? issue_slots_4_out_uop_iq_type_1 : issue_slots_3_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_iq_type_2 = _T_167 ? issue_slots_4_out_uop_iq_type_2 : issue_slots_3_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_iq_type_3 = _T_167 ? issue_slots_4_out_uop_iq_type_3 : issue_slots_3_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_debug_pc = _T_167 ? issue_slots_4_out_uop_debug_pc : issue_slots_3_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_is_rvc = _T_167 ? issue_slots_4_out_uop_is_rvc : issue_slots_3_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_debug_inst = _T_167 ? issue_slots_4_out_uop_debug_inst : issue_slots_3_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_2_in_uop_bits_inst = _T_167 ? issue_slots_4_out_uop_inst : issue_slots_3_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign _issue_slots_2_clear_T = |shamts_oh_2; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49]
assign issue_slots_2_clear = _issue_slots_2_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49]
wire _T_169 = shamts_oh_5 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28]
assign issue_slots_3_in_uop_valid = _T_169 ? issue_slots_5_will_be_valid : shamts_oh_4 == 2'h1 & issue_slots_4_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37]
assign issue_slots_3_in_uop_bits_debug_tsrc = _T_169 ? issue_slots_5_out_uop_debug_tsrc : issue_slots_4_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_debug_fsrc = _T_169 ? issue_slots_5_out_uop_debug_fsrc : issue_slots_4_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_bp_xcpt_if = _T_169 ? issue_slots_5_out_uop_bp_xcpt_if : issue_slots_4_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_bp_debug_if = _T_169 ? issue_slots_5_out_uop_bp_debug_if : issue_slots_4_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_xcpt_ma_if = _T_169 ? issue_slots_5_out_uop_xcpt_ma_if : issue_slots_4_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_xcpt_ae_if = _T_169 ? issue_slots_5_out_uop_xcpt_ae_if : issue_slots_4_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_xcpt_pf_if = _T_169 ? issue_slots_5_out_uop_xcpt_pf_if : issue_slots_4_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_fp_typ = _T_169 ? issue_slots_5_out_uop_fp_typ : issue_slots_4_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_fp_rm = _T_169 ? issue_slots_5_out_uop_fp_rm : issue_slots_4_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_fp_val = _T_169 ? issue_slots_5_out_uop_fp_val : issue_slots_4_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_fcn_op = _T_169 ? issue_slots_5_out_uop_fcn_op : issue_slots_4_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_fcn_dw = _T_169 ? issue_slots_5_out_uop_fcn_dw : issue_slots_4_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_frs3_en = _T_169 ? issue_slots_5_out_uop_frs3_en : issue_slots_4_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_lrs2_rtype = _T_169 ? issue_slots_5_out_uop_lrs2_rtype : issue_slots_4_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_lrs1_rtype = _T_169 ? issue_slots_5_out_uop_lrs1_rtype : issue_slots_4_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_dst_rtype = _T_169 ? issue_slots_5_out_uop_dst_rtype : issue_slots_4_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_lrs3 = _T_169 ? issue_slots_5_out_uop_lrs3 : issue_slots_4_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_lrs2 = _T_169 ? issue_slots_5_out_uop_lrs2 : issue_slots_4_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_lrs1 = _T_169 ? issue_slots_5_out_uop_lrs1 : issue_slots_4_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_ldst = _T_169 ? issue_slots_5_out_uop_ldst : issue_slots_4_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_ldst_is_rs1 = _T_169 ? issue_slots_5_out_uop_ldst_is_rs1 : issue_slots_4_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_csr_cmd = _T_169 ? issue_slots_5_out_uop_csr_cmd : issue_slots_4_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_flush_on_commit = _T_169 ? issue_slots_5_out_uop_flush_on_commit : issue_slots_4_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_is_unique = _T_169 ? issue_slots_5_out_uop_is_unique : issue_slots_4_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_uses_stq = _T_169 ? issue_slots_5_out_uop_uses_stq : issue_slots_4_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_uses_ldq = _T_169 ? issue_slots_5_out_uop_uses_ldq : issue_slots_4_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_mem_signed = _T_169 ? issue_slots_5_out_uop_mem_signed : issue_slots_4_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_mem_size = _T_169 ? issue_slots_5_out_uop_mem_size : issue_slots_4_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_mem_cmd = _T_169 ? issue_slots_5_out_uop_mem_cmd : issue_slots_4_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_exc_cause = _T_169 ? issue_slots_5_out_uop_exc_cause : issue_slots_4_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_exception = _T_169 ? issue_slots_5_out_uop_exception : issue_slots_4_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_stale_pdst = _T_169 ? issue_slots_5_out_uop_stale_pdst : issue_slots_4_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_ppred_busy = _T_169 ? issue_slots_5_out_uop_ppred_busy : issue_slots_4_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_prs3_busy = _T_169 ? issue_slots_5_out_uop_prs3_busy : issue_slots_4_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_prs2_busy = _T_169 ? issue_slots_5_out_uop_prs2_busy : issue_slots_4_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_prs1_busy = _T_169 ? issue_slots_5_out_uop_prs1_busy : issue_slots_4_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_ppred = _T_169 ? issue_slots_5_out_uop_ppred : issue_slots_4_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_prs3 = _T_169 ? issue_slots_5_out_uop_prs3 : issue_slots_4_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_prs2 = _T_169 ? issue_slots_5_out_uop_prs2 : issue_slots_4_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_prs1 = _T_169 ? issue_slots_5_out_uop_prs1 : issue_slots_4_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_pdst = _T_169 ? issue_slots_5_out_uop_pdst : issue_slots_4_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_rxq_idx = _T_169 ? issue_slots_5_out_uop_rxq_idx : issue_slots_4_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_stq_idx = _T_169 ? issue_slots_5_out_uop_stq_idx : issue_slots_4_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_ldq_idx = _T_169 ? issue_slots_5_out_uop_ldq_idx : issue_slots_4_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_rob_idx = _T_169 ? issue_slots_5_out_uop_rob_idx : issue_slots_4_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_fp_ctrl_vec = _T_169 ? issue_slots_5_out_uop_fp_ctrl_vec : issue_slots_4_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_fp_ctrl_wflags = _T_169 ? issue_slots_5_out_uop_fp_ctrl_wflags : issue_slots_4_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_fp_ctrl_sqrt = _T_169 ? issue_slots_5_out_uop_fp_ctrl_sqrt : issue_slots_4_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_fp_ctrl_div = _T_169 ? issue_slots_5_out_uop_fp_ctrl_div : issue_slots_4_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_fp_ctrl_fma = _T_169 ? issue_slots_5_out_uop_fp_ctrl_fma : issue_slots_4_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_fp_ctrl_fastpipe = _T_169 ? issue_slots_5_out_uop_fp_ctrl_fastpipe : issue_slots_4_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_fp_ctrl_toint = _T_169 ? issue_slots_5_out_uop_fp_ctrl_toint : issue_slots_4_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_fp_ctrl_fromint = _T_169 ? issue_slots_5_out_uop_fp_ctrl_fromint : issue_slots_4_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_fp_ctrl_typeTagOut = _T_169 ? issue_slots_5_out_uop_fp_ctrl_typeTagOut : issue_slots_4_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_fp_ctrl_typeTagIn = _T_169 ? issue_slots_5_out_uop_fp_ctrl_typeTagIn : issue_slots_4_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_fp_ctrl_swap23 = _T_169 ? issue_slots_5_out_uop_fp_ctrl_swap23 : issue_slots_4_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_fp_ctrl_swap12 = _T_169 ? issue_slots_5_out_uop_fp_ctrl_swap12 : issue_slots_4_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_fp_ctrl_ren3 = _T_169 ? issue_slots_5_out_uop_fp_ctrl_ren3 : issue_slots_4_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_fp_ctrl_ren2 = _T_169 ? issue_slots_5_out_uop_fp_ctrl_ren2 : issue_slots_4_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_fp_ctrl_ren1 = _T_169 ? issue_slots_5_out_uop_fp_ctrl_ren1 : issue_slots_4_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_fp_ctrl_wen = _T_169 ? issue_slots_5_out_uop_fp_ctrl_wen : issue_slots_4_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_fp_ctrl_ldst = _T_169 ? issue_slots_5_out_uop_fp_ctrl_ldst : issue_slots_4_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_op2_sel = _T_169 ? issue_slots_5_out_uop_op2_sel : issue_slots_4_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_op1_sel = _T_169 ? issue_slots_5_out_uop_op1_sel : issue_slots_4_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_imm_packed = _T_169 ? issue_slots_5_out_uop_imm_packed : issue_slots_4_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_pimm = _T_169 ? issue_slots_5_out_uop_pimm : issue_slots_4_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_imm_sel = _T_169 ? issue_slots_5_out_uop_imm_sel : issue_slots_4_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_imm_rename = _T_169 ? issue_slots_5_out_uop_imm_rename : issue_slots_4_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_taken = _T_169 ? issue_slots_5_out_uop_taken : issue_slots_4_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_pc_lob = _T_169 ? issue_slots_5_out_uop_pc_lob : issue_slots_4_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_edge_inst = _T_169 ? issue_slots_5_out_uop_edge_inst : issue_slots_4_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_ftq_idx = _T_169 ? issue_slots_5_out_uop_ftq_idx : issue_slots_4_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_is_mov = _T_169 ? issue_slots_5_out_uop_is_mov : issue_slots_4_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_is_rocc = _T_169 ? issue_slots_5_out_uop_is_rocc : issue_slots_4_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_is_sys_pc2epc = _T_169 ? issue_slots_5_out_uop_is_sys_pc2epc : issue_slots_4_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_is_eret = _T_169 ? issue_slots_5_out_uop_is_eret : issue_slots_4_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_is_amo = _T_169 ? issue_slots_5_out_uop_is_amo : issue_slots_4_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_is_sfence = _T_169 ? issue_slots_5_out_uop_is_sfence : issue_slots_4_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_is_fencei = _T_169 ? issue_slots_5_out_uop_is_fencei : issue_slots_4_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_is_fence = _T_169 ? issue_slots_5_out_uop_is_fence : issue_slots_4_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_is_sfb = _T_169 ? issue_slots_5_out_uop_is_sfb : issue_slots_4_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_br_type = _T_169 ? issue_slots_5_out_uop_br_type : issue_slots_4_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_br_tag = _T_169 ? issue_slots_5_out_uop_br_tag : issue_slots_4_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_br_mask = _T_169 ? issue_slots_5_out_uop_br_mask : issue_slots_4_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_dis_col_sel = _T_169 ? issue_slots_5_out_uop_dis_col_sel : issue_slots_4_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_iw_p3_bypass_hint = _T_169 ? issue_slots_5_out_uop_iw_p3_bypass_hint : issue_slots_4_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_iw_p2_bypass_hint = _T_169 ? issue_slots_5_out_uop_iw_p2_bypass_hint : issue_slots_4_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_iw_p1_bypass_hint = _T_169 ? issue_slots_5_out_uop_iw_p1_bypass_hint : issue_slots_4_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_iw_p2_speculative_child = _T_169 ? issue_slots_5_out_uop_iw_p2_speculative_child : issue_slots_4_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_iw_p1_speculative_child = _T_169 ? issue_slots_5_out_uop_iw_p1_speculative_child : issue_slots_4_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_iw_issued = _T_169 ? issue_slots_5_out_uop_iw_issued : issue_slots_4_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_fu_code_0 = _T_169 ? issue_slots_5_out_uop_fu_code_0 : issue_slots_4_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_fu_code_1 = _T_169 ? issue_slots_5_out_uop_fu_code_1 : issue_slots_4_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_fu_code_2 = _T_169 ? issue_slots_5_out_uop_fu_code_2 : issue_slots_4_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_fu_code_3 = _T_169 ? issue_slots_5_out_uop_fu_code_3 : issue_slots_4_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_fu_code_4 = _T_169 ? issue_slots_5_out_uop_fu_code_4 : issue_slots_4_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_fu_code_5 = _T_169 ? issue_slots_5_out_uop_fu_code_5 : issue_slots_4_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_fu_code_6 = _T_169 ? issue_slots_5_out_uop_fu_code_6 : issue_slots_4_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_fu_code_7 = _T_169 ? issue_slots_5_out_uop_fu_code_7 : issue_slots_4_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_fu_code_8 = _T_169 ? issue_slots_5_out_uop_fu_code_8 : issue_slots_4_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_fu_code_9 = _T_169 ? issue_slots_5_out_uop_fu_code_9 : issue_slots_4_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_iq_type_0 = _T_169 ? issue_slots_5_out_uop_iq_type_0 : issue_slots_4_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_iq_type_1 = _T_169 ? issue_slots_5_out_uop_iq_type_1 : issue_slots_4_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_iq_type_2 = _T_169 ? issue_slots_5_out_uop_iq_type_2 : issue_slots_4_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_iq_type_3 = _T_169 ? issue_slots_5_out_uop_iq_type_3 : issue_slots_4_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_debug_pc = _T_169 ? issue_slots_5_out_uop_debug_pc : issue_slots_4_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_is_rvc = _T_169 ? issue_slots_5_out_uop_is_rvc : issue_slots_4_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_debug_inst = _T_169 ? issue_slots_5_out_uop_debug_inst : issue_slots_4_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_3_in_uop_bits_inst = _T_169 ? issue_slots_5_out_uop_inst : issue_slots_4_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign _issue_slots_3_clear_T = |shamts_oh_3; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49]
assign issue_slots_3_clear = _issue_slots_3_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49]
wire _T_171 = shamts_oh_6 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28]
assign issue_slots_4_in_uop_valid = _T_171 ? issue_slots_6_will_be_valid : shamts_oh_5 == 2'h1 & issue_slots_5_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37]
assign issue_slots_4_in_uop_bits_debug_tsrc = _T_171 ? issue_slots_6_out_uop_debug_tsrc : issue_slots_5_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_debug_fsrc = _T_171 ? issue_slots_6_out_uop_debug_fsrc : issue_slots_5_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_bp_xcpt_if = _T_171 ? issue_slots_6_out_uop_bp_xcpt_if : issue_slots_5_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_bp_debug_if = _T_171 ? issue_slots_6_out_uop_bp_debug_if : issue_slots_5_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_xcpt_ma_if = _T_171 ? issue_slots_6_out_uop_xcpt_ma_if : issue_slots_5_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_xcpt_ae_if = _T_171 ? issue_slots_6_out_uop_xcpt_ae_if : issue_slots_5_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_xcpt_pf_if = _T_171 ? issue_slots_6_out_uop_xcpt_pf_if : issue_slots_5_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_fp_typ = _T_171 ? issue_slots_6_out_uop_fp_typ : issue_slots_5_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_fp_rm = _T_171 ? issue_slots_6_out_uop_fp_rm : issue_slots_5_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_fp_val = _T_171 ? issue_slots_6_out_uop_fp_val : issue_slots_5_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_fcn_op = _T_171 ? issue_slots_6_out_uop_fcn_op : issue_slots_5_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_fcn_dw = _T_171 ? issue_slots_6_out_uop_fcn_dw : issue_slots_5_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_frs3_en = _T_171 ? issue_slots_6_out_uop_frs3_en : issue_slots_5_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_lrs2_rtype = _T_171 ? issue_slots_6_out_uop_lrs2_rtype : issue_slots_5_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_lrs1_rtype = _T_171 ? issue_slots_6_out_uop_lrs1_rtype : issue_slots_5_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_dst_rtype = _T_171 ? issue_slots_6_out_uop_dst_rtype : issue_slots_5_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_lrs3 = _T_171 ? issue_slots_6_out_uop_lrs3 : issue_slots_5_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_lrs2 = _T_171 ? issue_slots_6_out_uop_lrs2 : issue_slots_5_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_lrs1 = _T_171 ? issue_slots_6_out_uop_lrs1 : issue_slots_5_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_ldst = _T_171 ? issue_slots_6_out_uop_ldst : issue_slots_5_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_ldst_is_rs1 = _T_171 ? issue_slots_6_out_uop_ldst_is_rs1 : issue_slots_5_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_csr_cmd = _T_171 ? issue_slots_6_out_uop_csr_cmd : issue_slots_5_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_flush_on_commit = _T_171 ? issue_slots_6_out_uop_flush_on_commit : issue_slots_5_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_is_unique = _T_171 ? issue_slots_6_out_uop_is_unique : issue_slots_5_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_uses_stq = _T_171 ? issue_slots_6_out_uop_uses_stq : issue_slots_5_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_uses_ldq = _T_171 ? issue_slots_6_out_uop_uses_ldq : issue_slots_5_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_mem_signed = _T_171 ? issue_slots_6_out_uop_mem_signed : issue_slots_5_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_mem_size = _T_171 ? issue_slots_6_out_uop_mem_size : issue_slots_5_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_mem_cmd = _T_171 ? issue_slots_6_out_uop_mem_cmd : issue_slots_5_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_exc_cause = _T_171 ? issue_slots_6_out_uop_exc_cause : issue_slots_5_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_exception = _T_171 ? issue_slots_6_out_uop_exception : issue_slots_5_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_stale_pdst = _T_171 ? issue_slots_6_out_uop_stale_pdst : issue_slots_5_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_ppred_busy = _T_171 ? issue_slots_6_out_uop_ppred_busy : issue_slots_5_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_prs3_busy = _T_171 ? issue_slots_6_out_uop_prs3_busy : issue_slots_5_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_prs2_busy = _T_171 ? issue_slots_6_out_uop_prs2_busy : issue_slots_5_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_prs1_busy = _T_171 ? issue_slots_6_out_uop_prs1_busy : issue_slots_5_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_ppred = _T_171 ? issue_slots_6_out_uop_ppred : issue_slots_5_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_prs3 = _T_171 ? issue_slots_6_out_uop_prs3 : issue_slots_5_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_prs2 = _T_171 ? issue_slots_6_out_uop_prs2 : issue_slots_5_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_prs1 = _T_171 ? issue_slots_6_out_uop_prs1 : issue_slots_5_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_pdst = _T_171 ? issue_slots_6_out_uop_pdst : issue_slots_5_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_rxq_idx = _T_171 ? issue_slots_6_out_uop_rxq_idx : issue_slots_5_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_stq_idx = _T_171 ? issue_slots_6_out_uop_stq_idx : issue_slots_5_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_ldq_idx = _T_171 ? issue_slots_6_out_uop_ldq_idx : issue_slots_5_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_rob_idx = _T_171 ? issue_slots_6_out_uop_rob_idx : issue_slots_5_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_fp_ctrl_vec = _T_171 ? issue_slots_6_out_uop_fp_ctrl_vec : issue_slots_5_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_fp_ctrl_wflags = _T_171 ? issue_slots_6_out_uop_fp_ctrl_wflags : issue_slots_5_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_fp_ctrl_sqrt = _T_171 ? issue_slots_6_out_uop_fp_ctrl_sqrt : issue_slots_5_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_fp_ctrl_div = _T_171 ? issue_slots_6_out_uop_fp_ctrl_div : issue_slots_5_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_fp_ctrl_fma = _T_171 ? issue_slots_6_out_uop_fp_ctrl_fma : issue_slots_5_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_fp_ctrl_fastpipe = _T_171 ? issue_slots_6_out_uop_fp_ctrl_fastpipe : issue_slots_5_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_fp_ctrl_toint = _T_171 ? issue_slots_6_out_uop_fp_ctrl_toint : issue_slots_5_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_fp_ctrl_fromint = _T_171 ? issue_slots_6_out_uop_fp_ctrl_fromint : issue_slots_5_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_fp_ctrl_typeTagOut = _T_171 ? issue_slots_6_out_uop_fp_ctrl_typeTagOut : issue_slots_5_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_fp_ctrl_typeTagIn = _T_171 ? issue_slots_6_out_uop_fp_ctrl_typeTagIn : issue_slots_5_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_fp_ctrl_swap23 = _T_171 ? issue_slots_6_out_uop_fp_ctrl_swap23 : issue_slots_5_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_fp_ctrl_swap12 = _T_171 ? issue_slots_6_out_uop_fp_ctrl_swap12 : issue_slots_5_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_fp_ctrl_ren3 = _T_171 ? issue_slots_6_out_uop_fp_ctrl_ren3 : issue_slots_5_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_fp_ctrl_ren2 = _T_171 ? issue_slots_6_out_uop_fp_ctrl_ren2 : issue_slots_5_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_fp_ctrl_ren1 = _T_171 ? issue_slots_6_out_uop_fp_ctrl_ren1 : issue_slots_5_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_fp_ctrl_wen = _T_171 ? issue_slots_6_out_uop_fp_ctrl_wen : issue_slots_5_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_fp_ctrl_ldst = _T_171 ? issue_slots_6_out_uop_fp_ctrl_ldst : issue_slots_5_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_op2_sel = _T_171 ? issue_slots_6_out_uop_op2_sel : issue_slots_5_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_op1_sel = _T_171 ? issue_slots_6_out_uop_op1_sel : issue_slots_5_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_imm_packed = _T_171 ? issue_slots_6_out_uop_imm_packed : issue_slots_5_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_pimm = _T_171 ? issue_slots_6_out_uop_pimm : issue_slots_5_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_imm_sel = _T_171 ? issue_slots_6_out_uop_imm_sel : issue_slots_5_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_imm_rename = _T_171 ? issue_slots_6_out_uop_imm_rename : issue_slots_5_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_taken = _T_171 ? issue_slots_6_out_uop_taken : issue_slots_5_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_pc_lob = _T_171 ? issue_slots_6_out_uop_pc_lob : issue_slots_5_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_edge_inst = _T_171 ? issue_slots_6_out_uop_edge_inst : issue_slots_5_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_ftq_idx = _T_171 ? issue_slots_6_out_uop_ftq_idx : issue_slots_5_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_is_mov = _T_171 ? issue_slots_6_out_uop_is_mov : issue_slots_5_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_is_rocc = _T_171 ? issue_slots_6_out_uop_is_rocc : issue_slots_5_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_is_sys_pc2epc = _T_171 ? issue_slots_6_out_uop_is_sys_pc2epc : issue_slots_5_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_is_eret = _T_171 ? issue_slots_6_out_uop_is_eret : issue_slots_5_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_is_amo = _T_171 ? issue_slots_6_out_uop_is_amo : issue_slots_5_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_is_sfence = _T_171 ? issue_slots_6_out_uop_is_sfence : issue_slots_5_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_is_fencei = _T_171 ? issue_slots_6_out_uop_is_fencei : issue_slots_5_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_is_fence = _T_171 ? issue_slots_6_out_uop_is_fence : issue_slots_5_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_is_sfb = _T_171 ? issue_slots_6_out_uop_is_sfb : issue_slots_5_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_br_type = _T_171 ? issue_slots_6_out_uop_br_type : issue_slots_5_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_br_tag = _T_171 ? issue_slots_6_out_uop_br_tag : issue_slots_5_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_br_mask = _T_171 ? issue_slots_6_out_uop_br_mask : issue_slots_5_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_dis_col_sel = _T_171 ? issue_slots_6_out_uop_dis_col_sel : issue_slots_5_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_iw_p3_bypass_hint = _T_171 ? issue_slots_6_out_uop_iw_p3_bypass_hint : issue_slots_5_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_iw_p2_bypass_hint = _T_171 ? issue_slots_6_out_uop_iw_p2_bypass_hint : issue_slots_5_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_iw_p1_bypass_hint = _T_171 ? issue_slots_6_out_uop_iw_p1_bypass_hint : issue_slots_5_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_iw_p2_speculative_child = _T_171 ? issue_slots_6_out_uop_iw_p2_speculative_child : issue_slots_5_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_iw_p1_speculative_child = _T_171 ? issue_slots_6_out_uop_iw_p1_speculative_child : issue_slots_5_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_iw_issued = _T_171 ? issue_slots_6_out_uop_iw_issued : issue_slots_5_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_fu_code_0 = _T_171 ? issue_slots_6_out_uop_fu_code_0 : issue_slots_5_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_fu_code_1 = _T_171 ? issue_slots_6_out_uop_fu_code_1 : issue_slots_5_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_fu_code_2 = _T_171 ? issue_slots_6_out_uop_fu_code_2 : issue_slots_5_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_fu_code_3 = _T_171 ? issue_slots_6_out_uop_fu_code_3 : issue_slots_5_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_fu_code_4 = _T_171 ? issue_slots_6_out_uop_fu_code_4 : issue_slots_5_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_fu_code_5 = _T_171 ? issue_slots_6_out_uop_fu_code_5 : issue_slots_5_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_fu_code_6 = _T_171 ? issue_slots_6_out_uop_fu_code_6 : issue_slots_5_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_fu_code_7 = _T_171 ? issue_slots_6_out_uop_fu_code_7 : issue_slots_5_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_fu_code_8 = _T_171 ? issue_slots_6_out_uop_fu_code_8 : issue_slots_5_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_fu_code_9 = _T_171 ? issue_slots_6_out_uop_fu_code_9 : issue_slots_5_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_iq_type_0 = _T_171 ? issue_slots_6_out_uop_iq_type_0 : issue_slots_5_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_iq_type_1 = _T_171 ? issue_slots_6_out_uop_iq_type_1 : issue_slots_5_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_iq_type_2 = _T_171 ? issue_slots_6_out_uop_iq_type_2 : issue_slots_5_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_iq_type_3 = _T_171 ? issue_slots_6_out_uop_iq_type_3 : issue_slots_5_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_debug_pc = _T_171 ? issue_slots_6_out_uop_debug_pc : issue_slots_5_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_is_rvc = _T_171 ? issue_slots_6_out_uop_is_rvc : issue_slots_5_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_debug_inst = _T_171 ? issue_slots_6_out_uop_debug_inst : issue_slots_5_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_4_in_uop_bits_inst = _T_171 ? issue_slots_6_out_uop_inst : issue_slots_5_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign _issue_slots_4_clear_T = |shamts_oh_4; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49]
assign issue_slots_4_clear = _issue_slots_4_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49]
wire _T_173 = shamts_oh_7 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28]
assign issue_slots_5_in_uop_valid = _T_173 ? issue_slots_7_will_be_valid : shamts_oh_6 == 2'h1 & issue_slots_6_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37]
assign issue_slots_5_in_uop_bits_debug_tsrc = _T_173 ? issue_slots_7_out_uop_debug_tsrc : issue_slots_6_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_debug_fsrc = _T_173 ? issue_slots_7_out_uop_debug_fsrc : issue_slots_6_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_bp_xcpt_if = _T_173 ? issue_slots_7_out_uop_bp_xcpt_if : issue_slots_6_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_bp_debug_if = _T_173 ? issue_slots_7_out_uop_bp_debug_if : issue_slots_6_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_xcpt_ma_if = _T_173 ? issue_slots_7_out_uop_xcpt_ma_if : issue_slots_6_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_xcpt_ae_if = _T_173 ? issue_slots_7_out_uop_xcpt_ae_if : issue_slots_6_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_xcpt_pf_if = _T_173 ? issue_slots_7_out_uop_xcpt_pf_if : issue_slots_6_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_fp_typ = _T_173 ? issue_slots_7_out_uop_fp_typ : issue_slots_6_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_fp_rm = _T_173 ? issue_slots_7_out_uop_fp_rm : issue_slots_6_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_fp_val = _T_173 ? issue_slots_7_out_uop_fp_val : issue_slots_6_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_fcn_op = _T_173 ? issue_slots_7_out_uop_fcn_op : issue_slots_6_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_fcn_dw = _T_173 ? issue_slots_7_out_uop_fcn_dw : issue_slots_6_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_frs3_en = _T_173 ? issue_slots_7_out_uop_frs3_en : issue_slots_6_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_lrs2_rtype = _T_173 ? issue_slots_7_out_uop_lrs2_rtype : issue_slots_6_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_lrs1_rtype = _T_173 ? issue_slots_7_out_uop_lrs1_rtype : issue_slots_6_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_dst_rtype = _T_173 ? issue_slots_7_out_uop_dst_rtype : issue_slots_6_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_lrs3 = _T_173 ? issue_slots_7_out_uop_lrs3 : issue_slots_6_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_lrs2 = _T_173 ? issue_slots_7_out_uop_lrs2 : issue_slots_6_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_lrs1 = _T_173 ? issue_slots_7_out_uop_lrs1 : issue_slots_6_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_ldst = _T_173 ? issue_slots_7_out_uop_ldst : issue_slots_6_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_ldst_is_rs1 = _T_173 ? issue_slots_7_out_uop_ldst_is_rs1 : issue_slots_6_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_csr_cmd = _T_173 ? issue_slots_7_out_uop_csr_cmd : issue_slots_6_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_flush_on_commit = _T_173 ? issue_slots_7_out_uop_flush_on_commit : issue_slots_6_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_is_unique = _T_173 ? issue_slots_7_out_uop_is_unique : issue_slots_6_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_uses_stq = _T_173 ? issue_slots_7_out_uop_uses_stq : issue_slots_6_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_uses_ldq = _T_173 ? issue_slots_7_out_uop_uses_ldq : issue_slots_6_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_mem_signed = _T_173 ? issue_slots_7_out_uop_mem_signed : issue_slots_6_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_mem_size = _T_173 ? issue_slots_7_out_uop_mem_size : issue_slots_6_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_mem_cmd = _T_173 ? issue_slots_7_out_uop_mem_cmd : issue_slots_6_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_exc_cause = _T_173 ? issue_slots_7_out_uop_exc_cause : issue_slots_6_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_exception = _T_173 ? issue_slots_7_out_uop_exception : issue_slots_6_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_stale_pdst = _T_173 ? issue_slots_7_out_uop_stale_pdst : issue_slots_6_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_ppred_busy = _T_173 ? issue_slots_7_out_uop_ppred_busy : issue_slots_6_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_prs3_busy = _T_173 ? issue_slots_7_out_uop_prs3_busy : issue_slots_6_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_prs2_busy = _T_173 ? issue_slots_7_out_uop_prs2_busy : issue_slots_6_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_prs1_busy = _T_173 ? issue_slots_7_out_uop_prs1_busy : issue_slots_6_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_ppred = _T_173 ? issue_slots_7_out_uop_ppred : issue_slots_6_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_prs3 = _T_173 ? issue_slots_7_out_uop_prs3 : issue_slots_6_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_prs2 = _T_173 ? issue_slots_7_out_uop_prs2 : issue_slots_6_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_prs1 = _T_173 ? issue_slots_7_out_uop_prs1 : issue_slots_6_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_pdst = _T_173 ? issue_slots_7_out_uop_pdst : issue_slots_6_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_rxq_idx = _T_173 ? issue_slots_7_out_uop_rxq_idx : issue_slots_6_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_stq_idx = _T_173 ? issue_slots_7_out_uop_stq_idx : issue_slots_6_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_ldq_idx = _T_173 ? issue_slots_7_out_uop_ldq_idx : issue_slots_6_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_rob_idx = _T_173 ? issue_slots_7_out_uop_rob_idx : issue_slots_6_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_fp_ctrl_vec = _T_173 ? issue_slots_7_out_uop_fp_ctrl_vec : issue_slots_6_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_fp_ctrl_wflags = _T_173 ? issue_slots_7_out_uop_fp_ctrl_wflags : issue_slots_6_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_fp_ctrl_sqrt = _T_173 ? issue_slots_7_out_uop_fp_ctrl_sqrt : issue_slots_6_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_fp_ctrl_div = _T_173 ? issue_slots_7_out_uop_fp_ctrl_div : issue_slots_6_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_fp_ctrl_fma = _T_173 ? issue_slots_7_out_uop_fp_ctrl_fma : issue_slots_6_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_fp_ctrl_fastpipe = _T_173 ? issue_slots_7_out_uop_fp_ctrl_fastpipe : issue_slots_6_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_fp_ctrl_toint = _T_173 ? issue_slots_7_out_uop_fp_ctrl_toint : issue_slots_6_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_fp_ctrl_fromint = _T_173 ? issue_slots_7_out_uop_fp_ctrl_fromint : issue_slots_6_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_fp_ctrl_typeTagOut = _T_173 ? issue_slots_7_out_uop_fp_ctrl_typeTagOut : issue_slots_6_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_fp_ctrl_typeTagIn = _T_173 ? issue_slots_7_out_uop_fp_ctrl_typeTagIn : issue_slots_6_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_fp_ctrl_swap23 = _T_173 ? issue_slots_7_out_uop_fp_ctrl_swap23 : issue_slots_6_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_fp_ctrl_swap12 = _T_173 ? issue_slots_7_out_uop_fp_ctrl_swap12 : issue_slots_6_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_fp_ctrl_ren3 = _T_173 ? issue_slots_7_out_uop_fp_ctrl_ren3 : issue_slots_6_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_fp_ctrl_ren2 = _T_173 ? issue_slots_7_out_uop_fp_ctrl_ren2 : issue_slots_6_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_fp_ctrl_ren1 = _T_173 ? issue_slots_7_out_uop_fp_ctrl_ren1 : issue_slots_6_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_fp_ctrl_wen = _T_173 ? issue_slots_7_out_uop_fp_ctrl_wen : issue_slots_6_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_fp_ctrl_ldst = _T_173 ? issue_slots_7_out_uop_fp_ctrl_ldst : issue_slots_6_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_op2_sel = _T_173 ? issue_slots_7_out_uop_op2_sel : issue_slots_6_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_op1_sel = _T_173 ? issue_slots_7_out_uop_op1_sel : issue_slots_6_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_imm_packed = _T_173 ? issue_slots_7_out_uop_imm_packed : issue_slots_6_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_pimm = _T_173 ? issue_slots_7_out_uop_pimm : issue_slots_6_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_imm_sel = _T_173 ? issue_slots_7_out_uop_imm_sel : issue_slots_6_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_imm_rename = _T_173 ? issue_slots_7_out_uop_imm_rename : issue_slots_6_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_taken = _T_173 ? issue_slots_7_out_uop_taken : issue_slots_6_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_pc_lob = _T_173 ? issue_slots_7_out_uop_pc_lob : issue_slots_6_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_edge_inst = _T_173 ? issue_slots_7_out_uop_edge_inst : issue_slots_6_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_ftq_idx = _T_173 ? issue_slots_7_out_uop_ftq_idx : issue_slots_6_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_is_mov = _T_173 ? issue_slots_7_out_uop_is_mov : issue_slots_6_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_is_rocc = _T_173 ? issue_slots_7_out_uop_is_rocc : issue_slots_6_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_is_sys_pc2epc = _T_173 ? issue_slots_7_out_uop_is_sys_pc2epc : issue_slots_6_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_is_eret = _T_173 ? issue_slots_7_out_uop_is_eret : issue_slots_6_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_is_amo = _T_173 ? issue_slots_7_out_uop_is_amo : issue_slots_6_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_is_sfence = _T_173 ? issue_slots_7_out_uop_is_sfence : issue_slots_6_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_is_fencei = _T_173 ? issue_slots_7_out_uop_is_fencei : issue_slots_6_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_is_fence = _T_173 ? issue_slots_7_out_uop_is_fence : issue_slots_6_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_is_sfb = _T_173 ? issue_slots_7_out_uop_is_sfb : issue_slots_6_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_br_type = _T_173 ? issue_slots_7_out_uop_br_type : issue_slots_6_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_br_tag = _T_173 ? issue_slots_7_out_uop_br_tag : issue_slots_6_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_br_mask = _T_173 ? issue_slots_7_out_uop_br_mask : issue_slots_6_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_dis_col_sel = _T_173 ? issue_slots_7_out_uop_dis_col_sel : issue_slots_6_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_iw_p3_bypass_hint = _T_173 ? issue_slots_7_out_uop_iw_p3_bypass_hint : issue_slots_6_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_iw_p2_bypass_hint = _T_173 ? issue_slots_7_out_uop_iw_p2_bypass_hint : issue_slots_6_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_iw_p1_bypass_hint = _T_173 ? issue_slots_7_out_uop_iw_p1_bypass_hint : issue_slots_6_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_iw_p2_speculative_child = _T_173 ? issue_slots_7_out_uop_iw_p2_speculative_child : issue_slots_6_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_iw_p1_speculative_child = _T_173 ? issue_slots_7_out_uop_iw_p1_speculative_child : issue_slots_6_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_iw_issued = _T_173 ? issue_slots_7_out_uop_iw_issued : issue_slots_6_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_fu_code_0 = _T_173 ? issue_slots_7_out_uop_fu_code_0 : issue_slots_6_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_fu_code_1 = _T_173 ? issue_slots_7_out_uop_fu_code_1 : issue_slots_6_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_fu_code_2 = _T_173 ? issue_slots_7_out_uop_fu_code_2 : issue_slots_6_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_fu_code_3 = _T_173 ? issue_slots_7_out_uop_fu_code_3 : issue_slots_6_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_fu_code_4 = _T_173 ? issue_slots_7_out_uop_fu_code_4 : issue_slots_6_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_fu_code_5 = _T_173 ? issue_slots_7_out_uop_fu_code_5 : issue_slots_6_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_fu_code_6 = _T_173 ? issue_slots_7_out_uop_fu_code_6 : issue_slots_6_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_fu_code_7 = _T_173 ? issue_slots_7_out_uop_fu_code_7 : issue_slots_6_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_fu_code_8 = _T_173 ? issue_slots_7_out_uop_fu_code_8 : issue_slots_6_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_fu_code_9 = _T_173 ? issue_slots_7_out_uop_fu_code_9 : issue_slots_6_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_iq_type_0 = _T_173 ? issue_slots_7_out_uop_iq_type_0 : issue_slots_6_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_iq_type_1 = _T_173 ? issue_slots_7_out_uop_iq_type_1 : issue_slots_6_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_iq_type_2 = _T_173 ? issue_slots_7_out_uop_iq_type_2 : issue_slots_6_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_iq_type_3 = _T_173 ? issue_slots_7_out_uop_iq_type_3 : issue_slots_6_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_debug_pc = _T_173 ? issue_slots_7_out_uop_debug_pc : issue_slots_6_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_is_rvc = _T_173 ? issue_slots_7_out_uop_is_rvc : issue_slots_6_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_debug_inst = _T_173 ? issue_slots_7_out_uop_debug_inst : issue_slots_6_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_5_in_uop_bits_inst = _T_173 ? issue_slots_7_out_uop_inst : issue_slots_6_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign _issue_slots_5_clear_T = |shamts_oh_5; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49]
assign issue_slots_5_clear = _issue_slots_5_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49]
wire _T_175 = shamts_oh_8 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28]
assign issue_slots_6_in_uop_valid = _T_175 ? issue_slots_8_will_be_valid : shamts_oh_7 == 2'h1 & issue_slots_7_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37]
assign issue_slots_6_in_uop_bits_debug_tsrc = _T_175 ? issue_slots_8_out_uop_debug_tsrc : issue_slots_7_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_debug_fsrc = _T_175 ? issue_slots_8_out_uop_debug_fsrc : issue_slots_7_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_bp_xcpt_if = _T_175 ? issue_slots_8_out_uop_bp_xcpt_if : issue_slots_7_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_bp_debug_if = _T_175 ? issue_slots_8_out_uop_bp_debug_if : issue_slots_7_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_xcpt_ma_if = _T_175 ? issue_slots_8_out_uop_xcpt_ma_if : issue_slots_7_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_xcpt_ae_if = _T_175 ? issue_slots_8_out_uop_xcpt_ae_if : issue_slots_7_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_xcpt_pf_if = _T_175 ? issue_slots_8_out_uop_xcpt_pf_if : issue_slots_7_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_fp_typ = _T_175 ? issue_slots_8_out_uop_fp_typ : issue_slots_7_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_fp_rm = _T_175 ? issue_slots_8_out_uop_fp_rm : issue_slots_7_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_fp_val = _T_175 ? issue_slots_8_out_uop_fp_val : issue_slots_7_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_fcn_op = _T_175 ? issue_slots_8_out_uop_fcn_op : issue_slots_7_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_fcn_dw = _T_175 ? issue_slots_8_out_uop_fcn_dw : issue_slots_7_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_frs3_en = _T_175 ? issue_slots_8_out_uop_frs3_en : issue_slots_7_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_lrs2_rtype = _T_175 ? issue_slots_8_out_uop_lrs2_rtype : issue_slots_7_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_lrs1_rtype = _T_175 ? issue_slots_8_out_uop_lrs1_rtype : issue_slots_7_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_dst_rtype = _T_175 ? issue_slots_8_out_uop_dst_rtype : issue_slots_7_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_lrs3 = _T_175 ? issue_slots_8_out_uop_lrs3 : issue_slots_7_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_lrs2 = _T_175 ? issue_slots_8_out_uop_lrs2 : issue_slots_7_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_lrs1 = _T_175 ? issue_slots_8_out_uop_lrs1 : issue_slots_7_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_ldst = _T_175 ? issue_slots_8_out_uop_ldst : issue_slots_7_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_ldst_is_rs1 = _T_175 ? issue_slots_8_out_uop_ldst_is_rs1 : issue_slots_7_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_csr_cmd = _T_175 ? issue_slots_8_out_uop_csr_cmd : issue_slots_7_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_flush_on_commit = _T_175 ? issue_slots_8_out_uop_flush_on_commit : issue_slots_7_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_is_unique = _T_175 ? issue_slots_8_out_uop_is_unique : issue_slots_7_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_uses_stq = _T_175 ? issue_slots_8_out_uop_uses_stq : issue_slots_7_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_uses_ldq = _T_175 ? issue_slots_8_out_uop_uses_ldq : issue_slots_7_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_mem_signed = _T_175 ? issue_slots_8_out_uop_mem_signed : issue_slots_7_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_mem_size = _T_175 ? issue_slots_8_out_uop_mem_size : issue_slots_7_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_mem_cmd = _T_175 ? issue_slots_8_out_uop_mem_cmd : issue_slots_7_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_exc_cause = _T_175 ? issue_slots_8_out_uop_exc_cause : issue_slots_7_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_exception = _T_175 ? issue_slots_8_out_uop_exception : issue_slots_7_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_stale_pdst = _T_175 ? issue_slots_8_out_uop_stale_pdst : issue_slots_7_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_ppred_busy = _T_175 ? issue_slots_8_out_uop_ppred_busy : issue_slots_7_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_prs3_busy = _T_175 ? issue_slots_8_out_uop_prs3_busy : issue_slots_7_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_prs2_busy = _T_175 ? issue_slots_8_out_uop_prs2_busy : issue_slots_7_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_prs1_busy = _T_175 ? issue_slots_8_out_uop_prs1_busy : issue_slots_7_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_ppred = _T_175 ? issue_slots_8_out_uop_ppred : issue_slots_7_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_prs3 = _T_175 ? issue_slots_8_out_uop_prs3 : issue_slots_7_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_prs2 = _T_175 ? issue_slots_8_out_uop_prs2 : issue_slots_7_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_prs1 = _T_175 ? issue_slots_8_out_uop_prs1 : issue_slots_7_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_pdst = _T_175 ? issue_slots_8_out_uop_pdst : issue_slots_7_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_rxq_idx = _T_175 ? issue_slots_8_out_uop_rxq_idx : issue_slots_7_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_stq_idx = _T_175 ? issue_slots_8_out_uop_stq_idx : issue_slots_7_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_ldq_idx = _T_175 ? issue_slots_8_out_uop_ldq_idx : issue_slots_7_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_rob_idx = _T_175 ? issue_slots_8_out_uop_rob_idx : issue_slots_7_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_fp_ctrl_vec = _T_175 ? issue_slots_8_out_uop_fp_ctrl_vec : issue_slots_7_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_fp_ctrl_wflags = _T_175 ? issue_slots_8_out_uop_fp_ctrl_wflags : issue_slots_7_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_fp_ctrl_sqrt = _T_175 ? issue_slots_8_out_uop_fp_ctrl_sqrt : issue_slots_7_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_fp_ctrl_div = _T_175 ? issue_slots_8_out_uop_fp_ctrl_div : issue_slots_7_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_fp_ctrl_fma = _T_175 ? issue_slots_8_out_uop_fp_ctrl_fma : issue_slots_7_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_fp_ctrl_fastpipe = _T_175 ? issue_slots_8_out_uop_fp_ctrl_fastpipe : issue_slots_7_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_fp_ctrl_toint = _T_175 ? issue_slots_8_out_uop_fp_ctrl_toint : issue_slots_7_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_fp_ctrl_fromint = _T_175 ? issue_slots_8_out_uop_fp_ctrl_fromint : issue_slots_7_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_fp_ctrl_typeTagOut = _T_175 ? issue_slots_8_out_uop_fp_ctrl_typeTagOut : issue_slots_7_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_fp_ctrl_typeTagIn = _T_175 ? issue_slots_8_out_uop_fp_ctrl_typeTagIn : issue_slots_7_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_fp_ctrl_swap23 = _T_175 ? issue_slots_8_out_uop_fp_ctrl_swap23 : issue_slots_7_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_fp_ctrl_swap12 = _T_175 ? issue_slots_8_out_uop_fp_ctrl_swap12 : issue_slots_7_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_fp_ctrl_ren3 = _T_175 ? issue_slots_8_out_uop_fp_ctrl_ren3 : issue_slots_7_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_fp_ctrl_ren2 = _T_175 ? issue_slots_8_out_uop_fp_ctrl_ren2 : issue_slots_7_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_fp_ctrl_ren1 = _T_175 ? issue_slots_8_out_uop_fp_ctrl_ren1 : issue_slots_7_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_fp_ctrl_wen = _T_175 ? issue_slots_8_out_uop_fp_ctrl_wen : issue_slots_7_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_fp_ctrl_ldst = _T_175 ? issue_slots_8_out_uop_fp_ctrl_ldst : issue_slots_7_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_op2_sel = _T_175 ? issue_slots_8_out_uop_op2_sel : issue_slots_7_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_op1_sel = _T_175 ? issue_slots_8_out_uop_op1_sel : issue_slots_7_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_imm_packed = _T_175 ? issue_slots_8_out_uop_imm_packed : issue_slots_7_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_pimm = _T_175 ? issue_slots_8_out_uop_pimm : issue_slots_7_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_imm_sel = _T_175 ? issue_slots_8_out_uop_imm_sel : issue_slots_7_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_imm_rename = _T_175 ? issue_slots_8_out_uop_imm_rename : issue_slots_7_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_taken = _T_175 ? issue_slots_8_out_uop_taken : issue_slots_7_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_pc_lob = _T_175 ? issue_slots_8_out_uop_pc_lob : issue_slots_7_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_edge_inst = _T_175 ? issue_slots_8_out_uop_edge_inst : issue_slots_7_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_ftq_idx = _T_175 ? issue_slots_8_out_uop_ftq_idx : issue_slots_7_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_is_mov = _T_175 ? issue_slots_8_out_uop_is_mov : issue_slots_7_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_is_rocc = _T_175 ? issue_slots_8_out_uop_is_rocc : issue_slots_7_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_is_sys_pc2epc = _T_175 ? issue_slots_8_out_uop_is_sys_pc2epc : issue_slots_7_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_is_eret = _T_175 ? issue_slots_8_out_uop_is_eret : issue_slots_7_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_is_amo = _T_175 ? issue_slots_8_out_uop_is_amo : issue_slots_7_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_is_sfence = _T_175 ? issue_slots_8_out_uop_is_sfence : issue_slots_7_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_is_fencei = _T_175 ? issue_slots_8_out_uop_is_fencei : issue_slots_7_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_is_fence = _T_175 ? issue_slots_8_out_uop_is_fence : issue_slots_7_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_is_sfb = _T_175 ? issue_slots_8_out_uop_is_sfb : issue_slots_7_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_br_type = _T_175 ? issue_slots_8_out_uop_br_type : issue_slots_7_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_br_tag = _T_175 ? issue_slots_8_out_uop_br_tag : issue_slots_7_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_br_mask = _T_175 ? issue_slots_8_out_uop_br_mask : issue_slots_7_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_dis_col_sel = _T_175 ? issue_slots_8_out_uop_dis_col_sel : issue_slots_7_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_iw_p3_bypass_hint = _T_175 ? issue_slots_8_out_uop_iw_p3_bypass_hint : issue_slots_7_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_iw_p2_bypass_hint = _T_175 ? issue_slots_8_out_uop_iw_p2_bypass_hint : issue_slots_7_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_iw_p1_bypass_hint = _T_175 ? issue_slots_8_out_uop_iw_p1_bypass_hint : issue_slots_7_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_iw_p2_speculative_child = _T_175 ? issue_slots_8_out_uop_iw_p2_speculative_child : issue_slots_7_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_iw_p1_speculative_child = _T_175 ? issue_slots_8_out_uop_iw_p1_speculative_child : issue_slots_7_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_iw_issued = _T_175 ? issue_slots_8_out_uop_iw_issued : issue_slots_7_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_fu_code_0 = _T_175 ? issue_slots_8_out_uop_fu_code_0 : issue_slots_7_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_fu_code_1 = _T_175 ? issue_slots_8_out_uop_fu_code_1 : issue_slots_7_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_fu_code_2 = _T_175 ? issue_slots_8_out_uop_fu_code_2 : issue_slots_7_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_fu_code_3 = _T_175 ? issue_slots_8_out_uop_fu_code_3 : issue_slots_7_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_fu_code_4 = _T_175 ? issue_slots_8_out_uop_fu_code_4 : issue_slots_7_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_fu_code_5 = _T_175 ? issue_slots_8_out_uop_fu_code_5 : issue_slots_7_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_fu_code_6 = _T_175 ? issue_slots_8_out_uop_fu_code_6 : issue_slots_7_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_fu_code_7 = _T_175 ? issue_slots_8_out_uop_fu_code_7 : issue_slots_7_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_fu_code_8 = _T_175 ? issue_slots_8_out_uop_fu_code_8 : issue_slots_7_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_fu_code_9 = _T_175 ? issue_slots_8_out_uop_fu_code_9 : issue_slots_7_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_iq_type_0 = _T_175 ? issue_slots_8_out_uop_iq_type_0 : issue_slots_7_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_iq_type_1 = _T_175 ? issue_slots_8_out_uop_iq_type_1 : issue_slots_7_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_iq_type_2 = _T_175 ? issue_slots_8_out_uop_iq_type_2 : issue_slots_7_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_iq_type_3 = _T_175 ? issue_slots_8_out_uop_iq_type_3 : issue_slots_7_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_debug_pc = _T_175 ? issue_slots_8_out_uop_debug_pc : issue_slots_7_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_is_rvc = _T_175 ? issue_slots_8_out_uop_is_rvc : issue_slots_7_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_debug_inst = _T_175 ? issue_slots_8_out_uop_debug_inst : issue_slots_7_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_6_in_uop_bits_inst = _T_175 ? issue_slots_8_out_uop_inst : issue_slots_7_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign _issue_slots_6_clear_T = |shamts_oh_6; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49]
assign issue_slots_6_clear = _issue_slots_6_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49]
wire _T_177 = shamts_oh_9 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28]
assign issue_slots_7_in_uop_valid = _T_177 ? issue_slots_9_will_be_valid : shamts_oh_8 == 2'h1 & issue_slots_8_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37]
assign issue_slots_7_in_uop_bits_debug_tsrc = _T_177 ? issue_slots_9_out_uop_debug_tsrc : issue_slots_8_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_debug_fsrc = _T_177 ? issue_slots_9_out_uop_debug_fsrc : issue_slots_8_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_bp_xcpt_if = _T_177 ? issue_slots_9_out_uop_bp_xcpt_if : issue_slots_8_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_bp_debug_if = _T_177 ? issue_slots_9_out_uop_bp_debug_if : issue_slots_8_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_xcpt_ma_if = _T_177 ? issue_slots_9_out_uop_xcpt_ma_if : issue_slots_8_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_xcpt_ae_if = _T_177 ? issue_slots_9_out_uop_xcpt_ae_if : issue_slots_8_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_xcpt_pf_if = _T_177 ? issue_slots_9_out_uop_xcpt_pf_if : issue_slots_8_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_fp_typ = _T_177 ? issue_slots_9_out_uop_fp_typ : issue_slots_8_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_fp_rm = _T_177 ? issue_slots_9_out_uop_fp_rm : issue_slots_8_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_fp_val = _T_177 ? issue_slots_9_out_uop_fp_val : issue_slots_8_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_fcn_op = _T_177 ? issue_slots_9_out_uop_fcn_op : issue_slots_8_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_fcn_dw = _T_177 ? issue_slots_9_out_uop_fcn_dw : issue_slots_8_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_frs3_en = _T_177 ? issue_slots_9_out_uop_frs3_en : issue_slots_8_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_lrs2_rtype = _T_177 ? issue_slots_9_out_uop_lrs2_rtype : issue_slots_8_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_lrs1_rtype = _T_177 ? issue_slots_9_out_uop_lrs1_rtype : issue_slots_8_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_dst_rtype = _T_177 ? issue_slots_9_out_uop_dst_rtype : issue_slots_8_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_lrs3 = _T_177 ? issue_slots_9_out_uop_lrs3 : issue_slots_8_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_lrs2 = _T_177 ? issue_slots_9_out_uop_lrs2 : issue_slots_8_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_lrs1 = _T_177 ? issue_slots_9_out_uop_lrs1 : issue_slots_8_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_ldst = _T_177 ? issue_slots_9_out_uop_ldst : issue_slots_8_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_ldst_is_rs1 = _T_177 ? issue_slots_9_out_uop_ldst_is_rs1 : issue_slots_8_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_csr_cmd = _T_177 ? issue_slots_9_out_uop_csr_cmd : issue_slots_8_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_flush_on_commit = _T_177 ? issue_slots_9_out_uop_flush_on_commit : issue_slots_8_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_is_unique = _T_177 ? issue_slots_9_out_uop_is_unique : issue_slots_8_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_uses_stq = _T_177 ? issue_slots_9_out_uop_uses_stq : issue_slots_8_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_uses_ldq = _T_177 ? issue_slots_9_out_uop_uses_ldq : issue_slots_8_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_mem_signed = _T_177 ? issue_slots_9_out_uop_mem_signed : issue_slots_8_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_mem_size = _T_177 ? issue_slots_9_out_uop_mem_size : issue_slots_8_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_mem_cmd = _T_177 ? issue_slots_9_out_uop_mem_cmd : issue_slots_8_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_exc_cause = _T_177 ? issue_slots_9_out_uop_exc_cause : issue_slots_8_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_exception = _T_177 ? issue_slots_9_out_uop_exception : issue_slots_8_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_stale_pdst = _T_177 ? issue_slots_9_out_uop_stale_pdst : issue_slots_8_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_ppred_busy = _T_177 ? issue_slots_9_out_uop_ppred_busy : issue_slots_8_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_prs3_busy = _T_177 ? issue_slots_9_out_uop_prs3_busy : issue_slots_8_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_prs2_busy = _T_177 ? issue_slots_9_out_uop_prs2_busy : issue_slots_8_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_prs1_busy = _T_177 ? issue_slots_9_out_uop_prs1_busy : issue_slots_8_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_ppred = _T_177 ? issue_slots_9_out_uop_ppred : issue_slots_8_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_prs3 = _T_177 ? issue_slots_9_out_uop_prs3 : issue_slots_8_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_prs2 = _T_177 ? issue_slots_9_out_uop_prs2 : issue_slots_8_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_prs1 = _T_177 ? issue_slots_9_out_uop_prs1 : issue_slots_8_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_pdst = _T_177 ? issue_slots_9_out_uop_pdst : issue_slots_8_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_rxq_idx = _T_177 ? issue_slots_9_out_uop_rxq_idx : issue_slots_8_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_stq_idx = _T_177 ? issue_slots_9_out_uop_stq_idx : issue_slots_8_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_ldq_idx = _T_177 ? issue_slots_9_out_uop_ldq_idx : issue_slots_8_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_rob_idx = _T_177 ? issue_slots_9_out_uop_rob_idx : issue_slots_8_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_fp_ctrl_vec = _T_177 ? issue_slots_9_out_uop_fp_ctrl_vec : issue_slots_8_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_fp_ctrl_wflags = _T_177 ? issue_slots_9_out_uop_fp_ctrl_wflags : issue_slots_8_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_fp_ctrl_sqrt = _T_177 ? issue_slots_9_out_uop_fp_ctrl_sqrt : issue_slots_8_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_fp_ctrl_div = _T_177 ? issue_slots_9_out_uop_fp_ctrl_div : issue_slots_8_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_fp_ctrl_fma = _T_177 ? issue_slots_9_out_uop_fp_ctrl_fma : issue_slots_8_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_fp_ctrl_fastpipe = _T_177 ? issue_slots_9_out_uop_fp_ctrl_fastpipe : issue_slots_8_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_fp_ctrl_toint = _T_177 ? issue_slots_9_out_uop_fp_ctrl_toint : issue_slots_8_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_fp_ctrl_fromint = _T_177 ? issue_slots_9_out_uop_fp_ctrl_fromint : issue_slots_8_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_fp_ctrl_typeTagOut = _T_177 ? issue_slots_9_out_uop_fp_ctrl_typeTagOut : issue_slots_8_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_fp_ctrl_typeTagIn = _T_177 ? issue_slots_9_out_uop_fp_ctrl_typeTagIn : issue_slots_8_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_fp_ctrl_swap23 = _T_177 ? issue_slots_9_out_uop_fp_ctrl_swap23 : issue_slots_8_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_fp_ctrl_swap12 = _T_177 ? issue_slots_9_out_uop_fp_ctrl_swap12 : issue_slots_8_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_fp_ctrl_ren3 = _T_177 ? issue_slots_9_out_uop_fp_ctrl_ren3 : issue_slots_8_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_fp_ctrl_ren2 = _T_177 ? issue_slots_9_out_uop_fp_ctrl_ren2 : issue_slots_8_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_fp_ctrl_ren1 = _T_177 ? issue_slots_9_out_uop_fp_ctrl_ren1 : issue_slots_8_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_fp_ctrl_wen = _T_177 ? issue_slots_9_out_uop_fp_ctrl_wen : issue_slots_8_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_fp_ctrl_ldst = _T_177 ? issue_slots_9_out_uop_fp_ctrl_ldst : issue_slots_8_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_op2_sel = _T_177 ? issue_slots_9_out_uop_op2_sel : issue_slots_8_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_op1_sel = _T_177 ? issue_slots_9_out_uop_op1_sel : issue_slots_8_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_imm_packed = _T_177 ? issue_slots_9_out_uop_imm_packed : issue_slots_8_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_pimm = _T_177 ? issue_slots_9_out_uop_pimm : issue_slots_8_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_imm_sel = _T_177 ? issue_slots_9_out_uop_imm_sel : issue_slots_8_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_imm_rename = _T_177 ? issue_slots_9_out_uop_imm_rename : issue_slots_8_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_taken = _T_177 ? issue_slots_9_out_uop_taken : issue_slots_8_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_pc_lob = _T_177 ? issue_slots_9_out_uop_pc_lob : issue_slots_8_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_edge_inst = _T_177 ? issue_slots_9_out_uop_edge_inst : issue_slots_8_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_ftq_idx = _T_177 ? issue_slots_9_out_uop_ftq_idx : issue_slots_8_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_is_mov = _T_177 ? issue_slots_9_out_uop_is_mov : issue_slots_8_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_is_rocc = _T_177 ? issue_slots_9_out_uop_is_rocc : issue_slots_8_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_is_sys_pc2epc = _T_177 ? issue_slots_9_out_uop_is_sys_pc2epc : issue_slots_8_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_is_eret = _T_177 ? issue_slots_9_out_uop_is_eret : issue_slots_8_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_is_amo = _T_177 ? issue_slots_9_out_uop_is_amo : issue_slots_8_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_is_sfence = _T_177 ? issue_slots_9_out_uop_is_sfence : issue_slots_8_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_is_fencei = _T_177 ? issue_slots_9_out_uop_is_fencei : issue_slots_8_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_is_fence = _T_177 ? issue_slots_9_out_uop_is_fence : issue_slots_8_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_is_sfb = _T_177 ? issue_slots_9_out_uop_is_sfb : issue_slots_8_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_br_type = _T_177 ? issue_slots_9_out_uop_br_type : issue_slots_8_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_br_tag = _T_177 ? issue_slots_9_out_uop_br_tag : issue_slots_8_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_br_mask = _T_177 ? issue_slots_9_out_uop_br_mask : issue_slots_8_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_dis_col_sel = _T_177 ? issue_slots_9_out_uop_dis_col_sel : issue_slots_8_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_iw_p3_bypass_hint = _T_177 ? issue_slots_9_out_uop_iw_p3_bypass_hint : issue_slots_8_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_iw_p2_bypass_hint = _T_177 ? issue_slots_9_out_uop_iw_p2_bypass_hint : issue_slots_8_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_iw_p1_bypass_hint = _T_177 ? issue_slots_9_out_uop_iw_p1_bypass_hint : issue_slots_8_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_iw_p2_speculative_child = _T_177 ? issue_slots_9_out_uop_iw_p2_speculative_child : issue_slots_8_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_iw_p1_speculative_child = _T_177 ? issue_slots_9_out_uop_iw_p1_speculative_child : issue_slots_8_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_iw_issued = _T_177 ? issue_slots_9_out_uop_iw_issued : issue_slots_8_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_fu_code_0 = _T_177 ? issue_slots_9_out_uop_fu_code_0 : issue_slots_8_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_fu_code_1 = _T_177 ? issue_slots_9_out_uop_fu_code_1 : issue_slots_8_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_fu_code_2 = _T_177 ? issue_slots_9_out_uop_fu_code_2 : issue_slots_8_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_fu_code_3 = _T_177 ? issue_slots_9_out_uop_fu_code_3 : issue_slots_8_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_fu_code_4 = _T_177 ? issue_slots_9_out_uop_fu_code_4 : issue_slots_8_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_fu_code_5 = _T_177 ? issue_slots_9_out_uop_fu_code_5 : issue_slots_8_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_fu_code_6 = _T_177 ? issue_slots_9_out_uop_fu_code_6 : issue_slots_8_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_fu_code_7 = _T_177 ? issue_slots_9_out_uop_fu_code_7 : issue_slots_8_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_fu_code_8 = _T_177 ? issue_slots_9_out_uop_fu_code_8 : issue_slots_8_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_fu_code_9 = _T_177 ? issue_slots_9_out_uop_fu_code_9 : issue_slots_8_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_iq_type_0 = _T_177 ? issue_slots_9_out_uop_iq_type_0 : issue_slots_8_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_iq_type_1 = _T_177 ? issue_slots_9_out_uop_iq_type_1 : issue_slots_8_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_iq_type_2 = _T_177 ? issue_slots_9_out_uop_iq_type_2 : issue_slots_8_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_iq_type_3 = _T_177 ? issue_slots_9_out_uop_iq_type_3 : issue_slots_8_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_debug_pc = _T_177 ? issue_slots_9_out_uop_debug_pc : issue_slots_8_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_is_rvc = _T_177 ? issue_slots_9_out_uop_is_rvc : issue_slots_8_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_debug_inst = _T_177 ? issue_slots_9_out_uop_debug_inst : issue_slots_8_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_7_in_uop_bits_inst = _T_177 ? issue_slots_9_out_uop_inst : issue_slots_8_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign _issue_slots_7_clear_T = |shamts_oh_7; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49]
assign issue_slots_7_clear = _issue_slots_7_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49]
wire _T_179 = shamts_oh_10 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28]
assign issue_slots_8_in_uop_valid = _T_179 ? issue_slots_10_will_be_valid : shamts_oh_9 == 2'h1 & issue_slots_9_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37]
assign issue_slots_8_in_uop_bits_debug_tsrc = _T_179 ? issue_slots_10_out_uop_debug_tsrc : issue_slots_9_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_debug_fsrc = _T_179 ? issue_slots_10_out_uop_debug_fsrc : issue_slots_9_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_bp_xcpt_if = _T_179 ? issue_slots_10_out_uop_bp_xcpt_if : issue_slots_9_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_bp_debug_if = _T_179 ? issue_slots_10_out_uop_bp_debug_if : issue_slots_9_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_xcpt_ma_if = _T_179 ? issue_slots_10_out_uop_xcpt_ma_if : issue_slots_9_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_xcpt_ae_if = _T_179 ? issue_slots_10_out_uop_xcpt_ae_if : issue_slots_9_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_xcpt_pf_if = _T_179 ? issue_slots_10_out_uop_xcpt_pf_if : issue_slots_9_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_fp_typ = _T_179 ? issue_slots_10_out_uop_fp_typ : issue_slots_9_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_fp_rm = _T_179 ? issue_slots_10_out_uop_fp_rm : issue_slots_9_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_fp_val = _T_179 ? issue_slots_10_out_uop_fp_val : issue_slots_9_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_fcn_op = _T_179 ? issue_slots_10_out_uop_fcn_op : issue_slots_9_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_fcn_dw = _T_179 ? issue_slots_10_out_uop_fcn_dw : issue_slots_9_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_frs3_en = _T_179 ? issue_slots_10_out_uop_frs3_en : issue_slots_9_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_lrs2_rtype = _T_179 ? issue_slots_10_out_uop_lrs2_rtype : issue_slots_9_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_lrs1_rtype = _T_179 ? issue_slots_10_out_uop_lrs1_rtype : issue_slots_9_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_dst_rtype = _T_179 ? issue_slots_10_out_uop_dst_rtype : issue_slots_9_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_lrs3 = _T_179 ? issue_slots_10_out_uop_lrs3 : issue_slots_9_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_lrs2 = _T_179 ? issue_slots_10_out_uop_lrs2 : issue_slots_9_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_lrs1 = _T_179 ? issue_slots_10_out_uop_lrs1 : issue_slots_9_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_ldst = _T_179 ? issue_slots_10_out_uop_ldst : issue_slots_9_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_ldst_is_rs1 = _T_179 ? issue_slots_10_out_uop_ldst_is_rs1 : issue_slots_9_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_csr_cmd = _T_179 ? issue_slots_10_out_uop_csr_cmd : issue_slots_9_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_flush_on_commit = _T_179 ? issue_slots_10_out_uop_flush_on_commit : issue_slots_9_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_is_unique = _T_179 ? issue_slots_10_out_uop_is_unique : issue_slots_9_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_uses_stq = _T_179 ? issue_slots_10_out_uop_uses_stq : issue_slots_9_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_uses_ldq = _T_179 ? issue_slots_10_out_uop_uses_ldq : issue_slots_9_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_mem_signed = _T_179 ? issue_slots_10_out_uop_mem_signed : issue_slots_9_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_mem_size = _T_179 ? issue_slots_10_out_uop_mem_size : issue_slots_9_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_mem_cmd = _T_179 ? issue_slots_10_out_uop_mem_cmd : issue_slots_9_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_exc_cause = _T_179 ? issue_slots_10_out_uop_exc_cause : issue_slots_9_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_exception = _T_179 ? issue_slots_10_out_uop_exception : issue_slots_9_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_stale_pdst = _T_179 ? issue_slots_10_out_uop_stale_pdst : issue_slots_9_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_ppred_busy = _T_179 ? issue_slots_10_out_uop_ppred_busy : issue_slots_9_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_prs3_busy = _T_179 ? issue_slots_10_out_uop_prs3_busy : issue_slots_9_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_prs2_busy = _T_179 ? issue_slots_10_out_uop_prs2_busy : issue_slots_9_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_prs1_busy = _T_179 ? issue_slots_10_out_uop_prs1_busy : issue_slots_9_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_ppred = _T_179 ? issue_slots_10_out_uop_ppred : issue_slots_9_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_prs3 = _T_179 ? issue_slots_10_out_uop_prs3 : issue_slots_9_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_prs2 = _T_179 ? issue_slots_10_out_uop_prs2 : issue_slots_9_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_prs1 = _T_179 ? issue_slots_10_out_uop_prs1 : issue_slots_9_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_pdst = _T_179 ? issue_slots_10_out_uop_pdst : issue_slots_9_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_rxq_idx = _T_179 ? issue_slots_10_out_uop_rxq_idx : issue_slots_9_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_stq_idx = _T_179 ? issue_slots_10_out_uop_stq_idx : issue_slots_9_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_ldq_idx = _T_179 ? issue_slots_10_out_uop_ldq_idx : issue_slots_9_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_rob_idx = _T_179 ? issue_slots_10_out_uop_rob_idx : issue_slots_9_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_fp_ctrl_vec = _T_179 ? issue_slots_10_out_uop_fp_ctrl_vec : issue_slots_9_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_fp_ctrl_wflags = _T_179 ? issue_slots_10_out_uop_fp_ctrl_wflags : issue_slots_9_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_fp_ctrl_sqrt = _T_179 ? issue_slots_10_out_uop_fp_ctrl_sqrt : issue_slots_9_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_fp_ctrl_div = _T_179 ? issue_slots_10_out_uop_fp_ctrl_div : issue_slots_9_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_fp_ctrl_fma = _T_179 ? issue_slots_10_out_uop_fp_ctrl_fma : issue_slots_9_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_fp_ctrl_fastpipe = _T_179 ? issue_slots_10_out_uop_fp_ctrl_fastpipe : issue_slots_9_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_fp_ctrl_toint = _T_179 ? issue_slots_10_out_uop_fp_ctrl_toint : issue_slots_9_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_fp_ctrl_fromint = _T_179 ? issue_slots_10_out_uop_fp_ctrl_fromint : issue_slots_9_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_fp_ctrl_typeTagOut = _T_179 ? issue_slots_10_out_uop_fp_ctrl_typeTagOut : issue_slots_9_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_fp_ctrl_typeTagIn = _T_179 ? issue_slots_10_out_uop_fp_ctrl_typeTagIn : issue_slots_9_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_fp_ctrl_swap23 = _T_179 ? issue_slots_10_out_uop_fp_ctrl_swap23 : issue_slots_9_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_fp_ctrl_swap12 = _T_179 ? issue_slots_10_out_uop_fp_ctrl_swap12 : issue_slots_9_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_fp_ctrl_ren3 = _T_179 ? issue_slots_10_out_uop_fp_ctrl_ren3 : issue_slots_9_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_fp_ctrl_ren2 = _T_179 ? issue_slots_10_out_uop_fp_ctrl_ren2 : issue_slots_9_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_fp_ctrl_ren1 = _T_179 ? issue_slots_10_out_uop_fp_ctrl_ren1 : issue_slots_9_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_fp_ctrl_wen = _T_179 ? issue_slots_10_out_uop_fp_ctrl_wen : issue_slots_9_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_fp_ctrl_ldst = _T_179 ? issue_slots_10_out_uop_fp_ctrl_ldst : issue_slots_9_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_op2_sel = _T_179 ? issue_slots_10_out_uop_op2_sel : issue_slots_9_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_op1_sel = _T_179 ? issue_slots_10_out_uop_op1_sel : issue_slots_9_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_imm_packed = _T_179 ? issue_slots_10_out_uop_imm_packed : issue_slots_9_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_pimm = _T_179 ? issue_slots_10_out_uop_pimm : issue_slots_9_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_imm_sel = _T_179 ? issue_slots_10_out_uop_imm_sel : issue_slots_9_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_imm_rename = _T_179 ? issue_slots_10_out_uop_imm_rename : issue_slots_9_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_taken = _T_179 ? issue_slots_10_out_uop_taken : issue_slots_9_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_pc_lob = _T_179 ? issue_slots_10_out_uop_pc_lob : issue_slots_9_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_edge_inst = _T_179 ? issue_slots_10_out_uop_edge_inst : issue_slots_9_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_ftq_idx = _T_179 ? issue_slots_10_out_uop_ftq_idx : issue_slots_9_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_is_mov = _T_179 ? issue_slots_10_out_uop_is_mov : issue_slots_9_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_is_rocc = _T_179 ? issue_slots_10_out_uop_is_rocc : issue_slots_9_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_is_sys_pc2epc = _T_179 ? issue_slots_10_out_uop_is_sys_pc2epc : issue_slots_9_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_is_eret = _T_179 ? issue_slots_10_out_uop_is_eret : issue_slots_9_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_is_amo = _T_179 ? issue_slots_10_out_uop_is_amo : issue_slots_9_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_is_sfence = _T_179 ? issue_slots_10_out_uop_is_sfence : issue_slots_9_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_is_fencei = _T_179 ? issue_slots_10_out_uop_is_fencei : issue_slots_9_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_is_fence = _T_179 ? issue_slots_10_out_uop_is_fence : issue_slots_9_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_is_sfb = _T_179 ? issue_slots_10_out_uop_is_sfb : issue_slots_9_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_br_type = _T_179 ? issue_slots_10_out_uop_br_type : issue_slots_9_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_br_tag = _T_179 ? issue_slots_10_out_uop_br_tag : issue_slots_9_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_br_mask = _T_179 ? issue_slots_10_out_uop_br_mask : issue_slots_9_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_dis_col_sel = _T_179 ? issue_slots_10_out_uop_dis_col_sel : issue_slots_9_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_iw_p3_bypass_hint = _T_179 ? issue_slots_10_out_uop_iw_p3_bypass_hint : issue_slots_9_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_iw_p2_bypass_hint = _T_179 ? issue_slots_10_out_uop_iw_p2_bypass_hint : issue_slots_9_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_iw_p1_bypass_hint = _T_179 ? issue_slots_10_out_uop_iw_p1_bypass_hint : issue_slots_9_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_iw_p2_speculative_child = _T_179 ? issue_slots_10_out_uop_iw_p2_speculative_child : issue_slots_9_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_iw_p1_speculative_child = _T_179 ? issue_slots_10_out_uop_iw_p1_speculative_child : issue_slots_9_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_iw_issued = _T_179 ? issue_slots_10_out_uop_iw_issued : issue_slots_9_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_fu_code_0 = _T_179 ? issue_slots_10_out_uop_fu_code_0 : issue_slots_9_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_fu_code_1 = _T_179 ? issue_slots_10_out_uop_fu_code_1 : issue_slots_9_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_fu_code_2 = _T_179 ? issue_slots_10_out_uop_fu_code_2 : issue_slots_9_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_fu_code_3 = _T_179 ? issue_slots_10_out_uop_fu_code_3 : issue_slots_9_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_fu_code_4 = _T_179 ? issue_slots_10_out_uop_fu_code_4 : issue_slots_9_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_fu_code_5 = _T_179 ? issue_slots_10_out_uop_fu_code_5 : issue_slots_9_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_fu_code_6 = _T_179 ? issue_slots_10_out_uop_fu_code_6 : issue_slots_9_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_fu_code_7 = _T_179 ? issue_slots_10_out_uop_fu_code_7 : issue_slots_9_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_fu_code_8 = _T_179 ? issue_slots_10_out_uop_fu_code_8 : issue_slots_9_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_fu_code_9 = _T_179 ? issue_slots_10_out_uop_fu_code_9 : issue_slots_9_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_iq_type_0 = _T_179 ? issue_slots_10_out_uop_iq_type_0 : issue_slots_9_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_iq_type_1 = _T_179 ? issue_slots_10_out_uop_iq_type_1 : issue_slots_9_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_iq_type_2 = _T_179 ? issue_slots_10_out_uop_iq_type_2 : issue_slots_9_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_iq_type_3 = _T_179 ? issue_slots_10_out_uop_iq_type_3 : issue_slots_9_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_debug_pc = _T_179 ? issue_slots_10_out_uop_debug_pc : issue_slots_9_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_is_rvc = _T_179 ? issue_slots_10_out_uop_is_rvc : issue_slots_9_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_debug_inst = _T_179 ? issue_slots_10_out_uop_debug_inst : issue_slots_9_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_8_in_uop_bits_inst = _T_179 ? issue_slots_10_out_uop_inst : issue_slots_9_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign _issue_slots_8_clear_T = |shamts_oh_8; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49]
assign issue_slots_8_clear = _issue_slots_8_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49]
wire _T_181 = shamts_oh_11 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28]
assign issue_slots_9_in_uop_valid = _T_181 ? issue_slots_11_will_be_valid : shamts_oh_10 == 2'h1 & issue_slots_10_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37]
assign issue_slots_9_in_uop_bits_debug_tsrc = _T_181 ? issue_slots_11_out_uop_debug_tsrc : issue_slots_10_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_debug_fsrc = _T_181 ? issue_slots_11_out_uop_debug_fsrc : issue_slots_10_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_bp_xcpt_if = _T_181 ? issue_slots_11_out_uop_bp_xcpt_if : issue_slots_10_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_bp_debug_if = _T_181 ? issue_slots_11_out_uop_bp_debug_if : issue_slots_10_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_xcpt_ma_if = _T_181 ? issue_slots_11_out_uop_xcpt_ma_if : issue_slots_10_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_xcpt_ae_if = _T_181 ? issue_slots_11_out_uop_xcpt_ae_if : issue_slots_10_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_xcpt_pf_if = _T_181 ? issue_slots_11_out_uop_xcpt_pf_if : issue_slots_10_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_fp_typ = _T_181 ? issue_slots_11_out_uop_fp_typ : issue_slots_10_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_fp_rm = _T_181 ? issue_slots_11_out_uop_fp_rm : issue_slots_10_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_fp_val = _T_181 ? issue_slots_11_out_uop_fp_val : issue_slots_10_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_fcn_op = _T_181 ? issue_slots_11_out_uop_fcn_op : issue_slots_10_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_fcn_dw = _T_181 ? issue_slots_11_out_uop_fcn_dw : issue_slots_10_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_frs3_en = _T_181 ? issue_slots_11_out_uop_frs3_en : issue_slots_10_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_lrs2_rtype = _T_181 ? issue_slots_11_out_uop_lrs2_rtype : issue_slots_10_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_lrs1_rtype = _T_181 ? issue_slots_11_out_uop_lrs1_rtype : issue_slots_10_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_dst_rtype = _T_181 ? issue_slots_11_out_uop_dst_rtype : issue_slots_10_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_lrs3 = _T_181 ? issue_slots_11_out_uop_lrs3 : issue_slots_10_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_lrs2 = _T_181 ? issue_slots_11_out_uop_lrs2 : issue_slots_10_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_lrs1 = _T_181 ? issue_slots_11_out_uop_lrs1 : issue_slots_10_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_ldst = _T_181 ? issue_slots_11_out_uop_ldst : issue_slots_10_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_ldst_is_rs1 = _T_181 ? issue_slots_11_out_uop_ldst_is_rs1 : issue_slots_10_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_csr_cmd = _T_181 ? issue_slots_11_out_uop_csr_cmd : issue_slots_10_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_flush_on_commit = _T_181 ? issue_slots_11_out_uop_flush_on_commit : issue_slots_10_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_is_unique = _T_181 ? issue_slots_11_out_uop_is_unique : issue_slots_10_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_uses_stq = _T_181 ? issue_slots_11_out_uop_uses_stq : issue_slots_10_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_uses_ldq = _T_181 ? issue_slots_11_out_uop_uses_ldq : issue_slots_10_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_mem_signed = _T_181 ? issue_slots_11_out_uop_mem_signed : issue_slots_10_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_mem_size = _T_181 ? issue_slots_11_out_uop_mem_size : issue_slots_10_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_mem_cmd = _T_181 ? issue_slots_11_out_uop_mem_cmd : issue_slots_10_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_exc_cause = _T_181 ? issue_slots_11_out_uop_exc_cause : issue_slots_10_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_exception = _T_181 ? issue_slots_11_out_uop_exception : issue_slots_10_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_stale_pdst = _T_181 ? issue_slots_11_out_uop_stale_pdst : issue_slots_10_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_ppred_busy = _T_181 ? issue_slots_11_out_uop_ppred_busy : issue_slots_10_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_prs3_busy = _T_181 ? issue_slots_11_out_uop_prs3_busy : issue_slots_10_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_prs2_busy = _T_181 ? issue_slots_11_out_uop_prs2_busy : issue_slots_10_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_prs1_busy = _T_181 ? issue_slots_11_out_uop_prs1_busy : issue_slots_10_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_ppred = _T_181 ? issue_slots_11_out_uop_ppred : issue_slots_10_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_prs3 = _T_181 ? issue_slots_11_out_uop_prs3 : issue_slots_10_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_prs2 = _T_181 ? issue_slots_11_out_uop_prs2 : issue_slots_10_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_prs1 = _T_181 ? issue_slots_11_out_uop_prs1 : issue_slots_10_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_pdst = _T_181 ? issue_slots_11_out_uop_pdst : issue_slots_10_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_rxq_idx = _T_181 ? issue_slots_11_out_uop_rxq_idx : issue_slots_10_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_stq_idx = _T_181 ? issue_slots_11_out_uop_stq_idx : issue_slots_10_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_ldq_idx = _T_181 ? issue_slots_11_out_uop_ldq_idx : issue_slots_10_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_rob_idx = _T_181 ? issue_slots_11_out_uop_rob_idx : issue_slots_10_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_fp_ctrl_vec = _T_181 ? issue_slots_11_out_uop_fp_ctrl_vec : issue_slots_10_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_fp_ctrl_wflags = _T_181 ? issue_slots_11_out_uop_fp_ctrl_wflags : issue_slots_10_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_fp_ctrl_sqrt = _T_181 ? issue_slots_11_out_uop_fp_ctrl_sqrt : issue_slots_10_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_fp_ctrl_div = _T_181 ? issue_slots_11_out_uop_fp_ctrl_div : issue_slots_10_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_fp_ctrl_fma = _T_181 ? issue_slots_11_out_uop_fp_ctrl_fma : issue_slots_10_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_fp_ctrl_fastpipe = _T_181 ? issue_slots_11_out_uop_fp_ctrl_fastpipe : issue_slots_10_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_fp_ctrl_toint = _T_181 ? issue_slots_11_out_uop_fp_ctrl_toint : issue_slots_10_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_fp_ctrl_fromint = _T_181 ? issue_slots_11_out_uop_fp_ctrl_fromint : issue_slots_10_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_fp_ctrl_typeTagOut = _T_181 ? issue_slots_11_out_uop_fp_ctrl_typeTagOut : issue_slots_10_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_fp_ctrl_typeTagIn = _T_181 ? issue_slots_11_out_uop_fp_ctrl_typeTagIn : issue_slots_10_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_fp_ctrl_swap23 = _T_181 ? issue_slots_11_out_uop_fp_ctrl_swap23 : issue_slots_10_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_fp_ctrl_swap12 = _T_181 ? issue_slots_11_out_uop_fp_ctrl_swap12 : issue_slots_10_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_fp_ctrl_ren3 = _T_181 ? issue_slots_11_out_uop_fp_ctrl_ren3 : issue_slots_10_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_fp_ctrl_ren2 = _T_181 ? issue_slots_11_out_uop_fp_ctrl_ren2 : issue_slots_10_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_fp_ctrl_ren1 = _T_181 ? issue_slots_11_out_uop_fp_ctrl_ren1 : issue_slots_10_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_fp_ctrl_wen = _T_181 ? issue_slots_11_out_uop_fp_ctrl_wen : issue_slots_10_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_fp_ctrl_ldst = _T_181 ? issue_slots_11_out_uop_fp_ctrl_ldst : issue_slots_10_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_op2_sel = _T_181 ? issue_slots_11_out_uop_op2_sel : issue_slots_10_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_op1_sel = _T_181 ? issue_slots_11_out_uop_op1_sel : issue_slots_10_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_imm_packed = _T_181 ? issue_slots_11_out_uop_imm_packed : issue_slots_10_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_pimm = _T_181 ? issue_slots_11_out_uop_pimm : issue_slots_10_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_imm_sel = _T_181 ? issue_slots_11_out_uop_imm_sel : issue_slots_10_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_imm_rename = _T_181 ? issue_slots_11_out_uop_imm_rename : issue_slots_10_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_taken = _T_181 ? issue_slots_11_out_uop_taken : issue_slots_10_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_pc_lob = _T_181 ? issue_slots_11_out_uop_pc_lob : issue_slots_10_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_edge_inst = _T_181 ? issue_slots_11_out_uop_edge_inst : issue_slots_10_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_ftq_idx = _T_181 ? issue_slots_11_out_uop_ftq_idx : issue_slots_10_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_is_mov = _T_181 ? issue_slots_11_out_uop_is_mov : issue_slots_10_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_is_rocc = _T_181 ? issue_slots_11_out_uop_is_rocc : issue_slots_10_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_is_sys_pc2epc = _T_181 ? issue_slots_11_out_uop_is_sys_pc2epc : issue_slots_10_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_is_eret = _T_181 ? issue_slots_11_out_uop_is_eret : issue_slots_10_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_is_amo = _T_181 ? issue_slots_11_out_uop_is_amo : issue_slots_10_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_is_sfence = _T_181 ? issue_slots_11_out_uop_is_sfence : issue_slots_10_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_is_fencei = _T_181 ? issue_slots_11_out_uop_is_fencei : issue_slots_10_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_is_fence = _T_181 ? issue_slots_11_out_uop_is_fence : issue_slots_10_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_is_sfb = _T_181 ? issue_slots_11_out_uop_is_sfb : issue_slots_10_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_br_type = _T_181 ? issue_slots_11_out_uop_br_type : issue_slots_10_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_br_tag = _T_181 ? issue_slots_11_out_uop_br_tag : issue_slots_10_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_br_mask = _T_181 ? issue_slots_11_out_uop_br_mask : issue_slots_10_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_dis_col_sel = _T_181 ? issue_slots_11_out_uop_dis_col_sel : issue_slots_10_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_iw_p3_bypass_hint = _T_181 ? issue_slots_11_out_uop_iw_p3_bypass_hint : issue_slots_10_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_iw_p2_bypass_hint = _T_181 ? issue_slots_11_out_uop_iw_p2_bypass_hint : issue_slots_10_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_iw_p1_bypass_hint = _T_181 ? issue_slots_11_out_uop_iw_p1_bypass_hint : issue_slots_10_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_iw_p2_speculative_child = _T_181 ? issue_slots_11_out_uop_iw_p2_speculative_child : issue_slots_10_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_iw_p1_speculative_child = _T_181 ? issue_slots_11_out_uop_iw_p1_speculative_child : issue_slots_10_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_iw_issued = _T_181 ? issue_slots_11_out_uop_iw_issued : issue_slots_10_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_fu_code_0 = _T_181 ? issue_slots_11_out_uop_fu_code_0 : issue_slots_10_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_fu_code_1 = _T_181 ? issue_slots_11_out_uop_fu_code_1 : issue_slots_10_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_fu_code_2 = _T_181 ? issue_slots_11_out_uop_fu_code_2 : issue_slots_10_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_fu_code_3 = _T_181 ? issue_slots_11_out_uop_fu_code_3 : issue_slots_10_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_fu_code_4 = _T_181 ? issue_slots_11_out_uop_fu_code_4 : issue_slots_10_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_fu_code_5 = _T_181 ? issue_slots_11_out_uop_fu_code_5 : issue_slots_10_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_fu_code_6 = _T_181 ? issue_slots_11_out_uop_fu_code_6 : issue_slots_10_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_fu_code_7 = _T_181 ? issue_slots_11_out_uop_fu_code_7 : issue_slots_10_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_fu_code_8 = _T_181 ? issue_slots_11_out_uop_fu_code_8 : issue_slots_10_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_fu_code_9 = _T_181 ? issue_slots_11_out_uop_fu_code_9 : issue_slots_10_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_iq_type_0 = _T_181 ? issue_slots_11_out_uop_iq_type_0 : issue_slots_10_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_iq_type_1 = _T_181 ? issue_slots_11_out_uop_iq_type_1 : issue_slots_10_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_iq_type_2 = _T_181 ? issue_slots_11_out_uop_iq_type_2 : issue_slots_10_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_iq_type_3 = _T_181 ? issue_slots_11_out_uop_iq_type_3 : issue_slots_10_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_debug_pc = _T_181 ? issue_slots_11_out_uop_debug_pc : issue_slots_10_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_is_rvc = _T_181 ? issue_slots_11_out_uop_is_rvc : issue_slots_10_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_debug_inst = _T_181 ? issue_slots_11_out_uop_debug_inst : issue_slots_10_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_9_in_uop_bits_inst = _T_181 ? issue_slots_11_out_uop_inst : issue_slots_10_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign _issue_slots_9_clear_T = |shamts_oh_9; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49]
assign issue_slots_9_clear = _issue_slots_9_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49]
wire _T_183 = shamts_oh_12 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28]
assign issue_slots_10_in_uop_valid = _T_183 ? issue_slots_12_will_be_valid : shamts_oh_11 == 2'h1 & issue_slots_11_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37]
assign issue_slots_10_in_uop_bits_debug_tsrc = _T_183 ? issue_slots_12_out_uop_debug_tsrc : issue_slots_11_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_debug_fsrc = _T_183 ? issue_slots_12_out_uop_debug_fsrc : issue_slots_11_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_bp_xcpt_if = _T_183 ? issue_slots_12_out_uop_bp_xcpt_if : issue_slots_11_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_bp_debug_if = _T_183 ? issue_slots_12_out_uop_bp_debug_if : issue_slots_11_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_xcpt_ma_if = _T_183 ? issue_slots_12_out_uop_xcpt_ma_if : issue_slots_11_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_xcpt_ae_if = _T_183 ? issue_slots_12_out_uop_xcpt_ae_if : issue_slots_11_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_xcpt_pf_if = _T_183 ? issue_slots_12_out_uop_xcpt_pf_if : issue_slots_11_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_fp_typ = _T_183 ? issue_slots_12_out_uop_fp_typ : issue_slots_11_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_fp_rm = _T_183 ? issue_slots_12_out_uop_fp_rm : issue_slots_11_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_fp_val = _T_183 ? issue_slots_12_out_uop_fp_val : issue_slots_11_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_fcn_op = _T_183 ? issue_slots_12_out_uop_fcn_op : issue_slots_11_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_fcn_dw = _T_183 ? issue_slots_12_out_uop_fcn_dw : issue_slots_11_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_frs3_en = _T_183 ? issue_slots_12_out_uop_frs3_en : issue_slots_11_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_lrs2_rtype = _T_183 ? issue_slots_12_out_uop_lrs2_rtype : issue_slots_11_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_lrs1_rtype = _T_183 ? issue_slots_12_out_uop_lrs1_rtype : issue_slots_11_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_dst_rtype = _T_183 ? issue_slots_12_out_uop_dst_rtype : issue_slots_11_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_lrs3 = _T_183 ? issue_slots_12_out_uop_lrs3 : issue_slots_11_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_lrs2 = _T_183 ? issue_slots_12_out_uop_lrs2 : issue_slots_11_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_lrs1 = _T_183 ? issue_slots_12_out_uop_lrs1 : issue_slots_11_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_ldst = _T_183 ? issue_slots_12_out_uop_ldst : issue_slots_11_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_ldst_is_rs1 = _T_183 ? issue_slots_12_out_uop_ldst_is_rs1 : issue_slots_11_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_csr_cmd = _T_183 ? issue_slots_12_out_uop_csr_cmd : issue_slots_11_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_flush_on_commit = _T_183 ? issue_slots_12_out_uop_flush_on_commit : issue_slots_11_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_is_unique = _T_183 ? issue_slots_12_out_uop_is_unique : issue_slots_11_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_uses_stq = _T_183 ? issue_slots_12_out_uop_uses_stq : issue_slots_11_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_uses_ldq = _T_183 ? issue_slots_12_out_uop_uses_ldq : issue_slots_11_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_mem_signed = _T_183 ? issue_slots_12_out_uop_mem_signed : issue_slots_11_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_mem_size = _T_183 ? issue_slots_12_out_uop_mem_size : issue_slots_11_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_mem_cmd = _T_183 ? issue_slots_12_out_uop_mem_cmd : issue_slots_11_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_exc_cause = _T_183 ? issue_slots_12_out_uop_exc_cause : issue_slots_11_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_exception = _T_183 ? issue_slots_12_out_uop_exception : issue_slots_11_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_stale_pdst = _T_183 ? issue_slots_12_out_uop_stale_pdst : issue_slots_11_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_ppred_busy = _T_183 ? issue_slots_12_out_uop_ppred_busy : issue_slots_11_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_prs3_busy = _T_183 ? issue_slots_12_out_uop_prs3_busy : issue_slots_11_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_prs2_busy = _T_183 ? issue_slots_12_out_uop_prs2_busy : issue_slots_11_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_prs1_busy = _T_183 ? issue_slots_12_out_uop_prs1_busy : issue_slots_11_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_ppred = _T_183 ? issue_slots_12_out_uop_ppred : issue_slots_11_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_prs3 = _T_183 ? issue_slots_12_out_uop_prs3 : issue_slots_11_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_prs2 = _T_183 ? issue_slots_12_out_uop_prs2 : issue_slots_11_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_prs1 = _T_183 ? issue_slots_12_out_uop_prs1 : issue_slots_11_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_pdst = _T_183 ? issue_slots_12_out_uop_pdst : issue_slots_11_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_rxq_idx = _T_183 ? issue_slots_12_out_uop_rxq_idx : issue_slots_11_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_stq_idx = _T_183 ? issue_slots_12_out_uop_stq_idx : issue_slots_11_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_ldq_idx = _T_183 ? issue_slots_12_out_uop_ldq_idx : issue_slots_11_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_rob_idx = _T_183 ? issue_slots_12_out_uop_rob_idx : issue_slots_11_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_fp_ctrl_vec = _T_183 ? issue_slots_12_out_uop_fp_ctrl_vec : issue_slots_11_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_fp_ctrl_wflags = _T_183 ? issue_slots_12_out_uop_fp_ctrl_wflags : issue_slots_11_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_fp_ctrl_sqrt = _T_183 ? issue_slots_12_out_uop_fp_ctrl_sqrt : issue_slots_11_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_fp_ctrl_div = _T_183 ? issue_slots_12_out_uop_fp_ctrl_div : issue_slots_11_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_fp_ctrl_fma = _T_183 ? issue_slots_12_out_uop_fp_ctrl_fma : issue_slots_11_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_fp_ctrl_fastpipe = _T_183 ? issue_slots_12_out_uop_fp_ctrl_fastpipe : issue_slots_11_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_fp_ctrl_toint = _T_183 ? issue_slots_12_out_uop_fp_ctrl_toint : issue_slots_11_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_fp_ctrl_fromint = _T_183 ? issue_slots_12_out_uop_fp_ctrl_fromint : issue_slots_11_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_fp_ctrl_typeTagOut = _T_183 ? issue_slots_12_out_uop_fp_ctrl_typeTagOut : issue_slots_11_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_fp_ctrl_typeTagIn = _T_183 ? issue_slots_12_out_uop_fp_ctrl_typeTagIn : issue_slots_11_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_fp_ctrl_swap23 = _T_183 ? issue_slots_12_out_uop_fp_ctrl_swap23 : issue_slots_11_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_fp_ctrl_swap12 = _T_183 ? issue_slots_12_out_uop_fp_ctrl_swap12 : issue_slots_11_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_fp_ctrl_ren3 = _T_183 ? issue_slots_12_out_uop_fp_ctrl_ren3 : issue_slots_11_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_fp_ctrl_ren2 = _T_183 ? issue_slots_12_out_uop_fp_ctrl_ren2 : issue_slots_11_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_fp_ctrl_ren1 = _T_183 ? issue_slots_12_out_uop_fp_ctrl_ren1 : issue_slots_11_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_fp_ctrl_wen = _T_183 ? issue_slots_12_out_uop_fp_ctrl_wen : issue_slots_11_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_fp_ctrl_ldst = _T_183 ? issue_slots_12_out_uop_fp_ctrl_ldst : issue_slots_11_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_op2_sel = _T_183 ? issue_slots_12_out_uop_op2_sel : issue_slots_11_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_op1_sel = _T_183 ? issue_slots_12_out_uop_op1_sel : issue_slots_11_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_imm_packed = _T_183 ? issue_slots_12_out_uop_imm_packed : issue_slots_11_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_pimm = _T_183 ? issue_slots_12_out_uop_pimm : issue_slots_11_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_imm_sel = _T_183 ? issue_slots_12_out_uop_imm_sel : issue_slots_11_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_imm_rename = _T_183 ? issue_slots_12_out_uop_imm_rename : issue_slots_11_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_taken = _T_183 ? issue_slots_12_out_uop_taken : issue_slots_11_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_pc_lob = _T_183 ? issue_slots_12_out_uop_pc_lob : issue_slots_11_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_edge_inst = _T_183 ? issue_slots_12_out_uop_edge_inst : issue_slots_11_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_ftq_idx = _T_183 ? issue_slots_12_out_uop_ftq_idx : issue_slots_11_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_is_mov = _T_183 ? issue_slots_12_out_uop_is_mov : issue_slots_11_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_is_rocc = _T_183 ? issue_slots_12_out_uop_is_rocc : issue_slots_11_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_is_sys_pc2epc = _T_183 ? issue_slots_12_out_uop_is_sys_pc2epc : issue_slots_11_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_is_eret = _T_183 ? issue_slots_12_out_uop_is_eret : issue_slots_11_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_is_amo = _T_183 ? issue_slots_12_out_uop_is_amo : issue_slots_11_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_is_sfence = _T_183 ? issue_slots_12_out_uop_is_sfence : issue_slots_11_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_is_fencei = _T_183 ? issue_slots_12_out_uop_is_fencei : issue_slots_11_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_is_fence = _T_183 ? issue_slots_12_out_uop_is_fence : issue_slots_11_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_is_sfb = _T_183 ? issue_slots_12_out_uop_is_sfb : issue_slots_11_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_br_type = _T_183 ? issue_slots_12_out_uop_br_type : issue_slots_11_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_br_tag = _T_183 ? issue_slots_12_out_uop_br_tag : issue_slots_11_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_br_mask = _T_183 ? issue_slots_12_out_uop_br_mask : issue_slots_11_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_dis_col_sel = _T_183 ? issue_slots_12_out_uop_dis_col_sel : issue_slots_11_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_iw_p3_bypass_hint = _T_183 ? issue_slots_12_out_uop_iw_p3_bypass_hint : issue_slots_11_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_iw_p2_bypass_hint = _T_183 ? issue_slots_12_out_uop_iw_p2_bypass_hint : issue_slots_11_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_iw_p1_bypass_hint = _T_183 ? issue_slots_12_out_uop_iw_p1_bypass_hint : issue_slots_11_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_iw_p2_speculative_child = _T_183 ? issue_slots_12_out_uop_iw_p2_speculative_child : issue_slots_11_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_iw_p1_speculative_child = _T_183 ? issue_slots_12_out_uop_iw_p1_speculative_child : issue_slots_11_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_iw_issued = _T_183 ? issue_slots_12_out_uop_iw_issued : issue_slots_11_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_fu_code_0 = _T_183 ? issue_slots_12_out_uop_fu_code_0 : issue_slots_11_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_fu_code_1 = _T_183 ? issue_slots_12_out_uop_fu_code_1 : issue_slots_11_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_fu_code_2 = _T_183 ? issue_slots_12_out_uop_fu_code_2 : issue_slots_11_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_fu_code_3 = _T_183 ? issue_slots_12_out_uop_fu_code_3 : issue_slots_11_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_fu_code_4 = _T_183 ? issue_slots_12_out_uop_fu_code_4 : issue_slots_11_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_fu_code_5 = _T_183 ? issue_slots_12_out_uop_fu_code_5 : issue_slots_11_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_fu_code_6 = _T_183 ? issue_slots_12_out_uop_fu_code_6 : issue_slots_11_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_fu_code_7 = _T_183 ? issue_slots_12_out_uop_fu_code_7 : issue_slots_11_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_fu_code_8 = _T_183 ? issue_slots_12_out_uop_fu_code_8 : issue_slots_11_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_fu_code_9 = _T_183 ? issue_slots_12_out_uop_fu_code_9 : issue_slots_11_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_iq_type_0 = _T_183 ? issue_slots_12_out_uop_iq_type_0 : issue_slots_11_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_iq_type_1 = _T_183 ? issue_slots_12_out_uop_iq_type_1 : issue_slots_11_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_iq_type_2 = _T_183 ? issue_slots_12_out_uop_iq_type_2 : issue_slots_11_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_iq_type_3 = _T_183 ? issue_slots_12_out_uop_iq_type_3 : issue_slots_11_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_debug_pc = _T_183 ? issue_slots_12_out_uop_debug_pc : issue_slots_11_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_is_rvc = _T_183 ? issue_slots_12_out_uop_is_rvc : issue_slots_11_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_debug_inst = _T_183 ? issue_slots_12_out_uop_debug_inst : issue_slots_11_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_10_in_uop_bits_inst = _T_183 ? issue_slots_12_out_uop_inst : issue_slots_11_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign _issue_slots_10_clear_T = |shamts_oh_10; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49]
assign issue_slots_10_clear = _issue_slots_10_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49]
wire _T_185 = shamts_oh_13 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28]
assign issue_slots_11_in_uop_valid = _T_185 ? issue_slots_13_will_be_valid : shamts_oh_12 == 2'h1 & issue_slots_12_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37]
assign issue_slots_11_in_uop_bits_debug_tsrc = _T_185 ? issue_slots_13_out_uop_debug_tsrc : issue_slots_12_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_debug_fsrc = _T_185 ? issue_slots_13_out_uop_debug_fsrc : issue_slots_12_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_bp_xcpt_if = _T_185 ? issue_slots_13_out_uop_bp_xcpt_if : issue_slots_12_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_bp_debug_if = _T_185 ? issue_slots_13_out_uop_bp_debug_if : issue_slots_12_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_xcpt_ma_if = _T_185 ? issue_slots_13_out_uop_xcpt_ma_if : issue_slots_12_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_xcpt_ae_if = _T_185 ? issue_slots_13_out_uop_xcpt_ae_if : issue_slots_12_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_xcpt_pf_if = _T_185 ? issue_slots_13_out_uop_xcpt_pf_if : issue_slots_12_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_fp_typ = _T_185 ? issue_slots_13_out_uop_fp_typ : issue_slots_12_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_fp_rm = _T_185 ? issue_slots_13_out_uop_fp_rm : issue_slots_12_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_fp_val = _T_185 ? issue_slots_13_out_uop_fp_val : issue_slots_12_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_fcn_op = _T_185 ? issue_slots_13_out_uop_fcn_op : issue_slots_12_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_fcn_dw = _T_185 ? issue_slots_13_out_uop_fcn_dw : issue_slots_12_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_frs3_en = _T_185 ? issue_slots_13_out_uop_frs3_en : issue_slots_12_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_lrs2_rtype = _T_185 ? issue_slots_13_out_uop_lrs2_rtype : issue_slots_12_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_lrs1_rtype = _T_185 ? issue_slots_13_out_uop_lrs1_rtype : issue_slots_12_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_dst_rtype = _T_185 ? issue_slots_13_out_uop_dst_rtype : issue_slots_12_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_lrs3 = _T_185 ? issue_slots_13_out_uop_lrs3 : issue_slots_12_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_lrs2 = _T_185 ? issue_slots_13_out_uop_lrs2 : issue_slots_12_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_lrs1 = _T_185 ? issue_slots_13_out_uop_lrs1 : issue_slots_12_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_ldst = _T_185 ? issue_slots_13_out_uop_ldst : issue_slots_12_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_ldst_is_rs1 = _T_185 ? issue_slots_13_out_uop_ldst_is_rs1 : issue_slots_12_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_csr_cmd = _T_185 ? issue_slots_13_out_uop_csr_cmd : issue_slots_12_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_flush_on_commit = _T_185 ? issue_slots_13_out_uop_flush_on_commit : issue_slots_12_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_is_unique = _T_185 ? issue_slots_13_out_uop_is_unique : issue_slots_12_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_uses_stq = _T_185 ? issue_slots_13_out_uop_uses_stq : issue_slots_12_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_uses_ldq = _T_185 ? issue_slots_13_out_uop_uses_ldq : issue_slots_12_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_mem_signed = _T_185 ? issue_slots_13_out_uop_mem_signed : issue_slots_12_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_mem_size = _T_185 ? issue_slots_13_out_uop_mem_size : issue_slots_12_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_mem_cmd = _T_185 ? issue_slots_13_out_uop_mem_cmd : issue_slots_12_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_exc_cause = _T_185 ? issue_slots_13_out_uop_exc_cause : issue_slots_12_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_exception = _T_185 ? issue_slots_13_out_uop_exception : issue_slots_12_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_stale_pdst = _T_185 ? issue_slots_13_out_uop_stale_pdst : issue_slots_12_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_ppred_busy = _T_185 ? issue_slots_13_out_uop_ppred_busy : issue_slots_12_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_prs3_busy = _T_185 ? issue_slots_13_out_uop_prs3_busy : issue_slots_12_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_prs2_busy = _T_185 ? issue_slots_13_out_uop_prs2_busy : issue_slots_12_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_prs1_busy = _T_185 ? issue_slots_13_out_uop_prs1_busy : issue_slots_12_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_ppred = _T_185 ? issue_slots_13_out_uop_ppred : issue_slots_12_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_prs3 = _T_185 ? issue_slots_13_out_uop_prs3 : issue_slots_12_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_prs2 = _T_185 ? issue_slots_13_out_uop_prs2 : issue_slots_12_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_prs1 = _T_185 ? issue_slots_13_out_uop_prs1 : issue_slots_12_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_pdst = _T_185 ? issue_slots_13_out_uop_pdst : issue_slots_12_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_rxq_idx = _T_185 ? issue_slots_13_out_uop_rxq_idx : issue_slots_12_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_stq_idx = _T_185 ? issue_slots_13_out_uop_stq_idx : issue_slots_12_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_ldq_idx = _T_185 ? issue_slots_13_out_uop_ldq_idx : issue_slots_12_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_rob_idx = _T_185 ? issue_slots_13_out_uop_rob_idx : issue_slots_12_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_fp_ctrl_vec = _T_185 ? issue_slots_13_out_uop_fp_ctrl_vec : issue_slots_12_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_fp_ctrl_wflags = _T_185 ? issue_slots_13_out_uop_fp_ctrl_wflags : issue_slots_12_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_fp_ctrl_sqrt = _T_185 ? issue_slots_13_out_uop_fp_ctrl_sqrt : issue_slots_12_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_fp_ctrl_div = _T_185 ? issue_slots_13_out_uop_fp_ctrl_div : issue_slots_12_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_fp_ctrl_fma = _T_185 ? issue_slots_13_out_uop_fp_ctrl_fma : issue_slots_12_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_fp_ctrl_fastpipe = _T_185 ? issue_slots_13_out_uop_fp_ctrl_fastpipe : issue_slots_12_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_fp_ctrl_toint = _T_185 ? issue_slots_13_out_uop_fp_ctrl_toint : issue_slots_12_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_fp_ctrl_fromint = _T_185 ? issue_slots_13_out_uop_fp_ctrl_fromint : issue_slots_12_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_fp_ctrl_typeTagOut = _T_185 ? issue_slots_13_out_uop_fp_ctrl_typeTagOut : issue_slots_12_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_fp_ctrl_typeTagIn = _T_185 ? issue_slots_13_out_uop_fp_ctrl_typeTagIn : issue_slots_12_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_fp_ctrl_swap23 = _T_185 ? issue_slots_13_out_uop_fp_ctrl_swap23 : issue_slots_12_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_fp_ctrl_swap12 = _T_185 ? issue_slots_13_out_uop_fp_ctrl_swap12 : issue_slots_12_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_fp_ctrl_ren3 = _T_185 ? issue_slots_13_out_uop_fp_ctrl_ren3 : issue_slots_12_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_fp_ctrl_ren2 = _T_185 ? issue_slots_13_out_uop_fp_ctrl_ren2 : issue_slots_12_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_fp_ctrl_ren1 = _T_185 ? issue_slots_13_out_uop_fp_ctrl_ren1 : issue_slots_12_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_fp_ctrl_wen = _T_185 ? issue_slots_13_out_uop_fp_ctrl_wen : issue_slots_12_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_fp_ctrl_ldst = _T_185 ? issue_slots_13_out_uop_fp_ctrl_ldst : issue_slots_12_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_op2_sel = _T_185 ? issue_slots_13_out_uop_op2_sel : issue_slots_12_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_op1_sel = _T_185 ? issue_slots_13_out_uop_op1_sel : issue_slots_12_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_imm_packed = _T_185 ? issue_slots_13_out_uop_imm_packed : issue_slots_12_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_pimm = _T_185 ? issue_slots_13_out_uop_pimm : issue_slots_12_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_imm_sel = _T_185 ? issue_slots_13_out_uop_imm_sel : issue_slots_12_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_imm_rename = _T_185 ? issue_slots_13_out_uop_imm_rename : issue_slots_12_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_taken = _T_185 ? issue_slots_13_out_uop_taken : issue_slots_12_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_pc_lob = _T_185 ? issue_slots_13_out_uop_pc_lob : issue_slots_12_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_edge_inst = _T_185 ? issue_slots_13_out_uop_edge_inst : issue_slots_12_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_ftq_idx = _T_185 ? issue_slots_13_out_uop_ftq_idx : issue_slots_12_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_is_mov = _T_185 ? issue_slots_13_out_uop_is_mov : issue_slots_12_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_is_rocc = _T_185 ? issue_slots_13_out_uop_is_rocc : issue_slots_12_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_is_sys_pc2epc = _T_185 ? issue_slots_13_out_uop_is_sys_pc2epc : issue_slots_12_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_is_eret = _T_185 ? issue_slots_13_out_uop_is_eret : issue_slots_12_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_is_amo = _T_185 ? issue_slots_13_out_uop_is_amo : issue_slots_12_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_is_sfence = _T_185 ? issue_slots_13_out_uop_is_sfence : issue_slots_12_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_is_fencei = _T_185 ? issue_slots_13_out_uop_is_fencei : issue_slots_12_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_is_fence = _T_185 ? issue_slots_13_out_uop_is_fence : issue_slots_12_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_is_sfb = _T_185 ? issue_slots_13_out_uop_is_sfb : issue_slots_12_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_br_type = _T_185 ? issue_slots_13_out_uop_br_type : issue_slots_12_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_br_tag = _T_185 ? issue_slots_13_out_uop_br_tag : issue_slots_12_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_br_mask = _T_185 ? issue_slots_13_out_uop_br_mask : issue_slots_12_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_dis_col_sel = _T_185 ? issue_slots_13_out_uop_dis_col_sel : issue_slots_12_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_iw_p3_bypass_hint = _T_185 ? issue_slots_13_out_uop_iw_p3_bypass_hint : issue_slots_12_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_iw_p2_bypass_hint = _T_185 ? issue_slots_13_out_uop_iw_p2_bypass_hint : issue_slots_12_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_iw_p1_bypass_hint = _T_185 ? issue_slots_13_out_uop_iw_p1_bypass_hint : issue_slots_12_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_iw_p2_speculative_child = _T_185 ? issue_slots_13_out_uop_iw_p2_speculative_child : issue_slots_12_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_iw_p1_speculative_child = _T_185 ? issue_slots_13_out_uop_iw_p1_speculative_child : issue_slots_12_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_iw_issued = _T_185 ? issue_slots_13_out_uop_iw_issued : issue_slots_12_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_fu_code_0 = _T_185 ? issue_slots_13_out_uop_fu_code_0 : issue_slots_12_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_fu_code_1 = _T_185 ? issue_slots_13_out_uop_fu_code_1 : issue_slots_12_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_fu_code_2 = _T_185 ? issue_slots_13_out_uop_fu_code_2 : issue_slots_12_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_fu_code_3 = _T_185 ? issue_slots_13_out_uop_fu_code_3 : issue_slots_12_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_fu_code_4 = _T_185 ? issue_slots_13_out_uop_fu_code_4 : issue_slots_12_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_fu_code_5 = _T_185 ? issue_slots_13_out_uop_fu_code_5 : issue_slots_12_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_fu_code_6 = _T_185 ? issue_slots_13_out_uop_fu_code_6 : issue_slots_12_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_fu_code_7 = _T_185 ? issue_slots_13_out_uop_fu_code_7 : issue_slots_12_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_fu_code_8 = _T_185 ? issue_slots_13_out_uop_fu_code_8 : issue_slots_12_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_fu_code_9 = _T_185 ? issue_slots_13_out_uop_fu_code_9 : issue_slots_12_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_iq_type_0 = _T_185 ? issue_slots_13_out_uop_iq_type_0 : issue_slots_12_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_iq_type_1 = _T_185 ? issue_slots_13_out_uop_iq_type_1 : issue_slots_12_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_iq_type_2 = _T_185 ? issue_slots_13_out_uop_iq_type_2 : issue_slots_12_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_iq_type_3 = _T_185 ? issue_slots_13_out_uop_iq_type_3 : issue_slots_12_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_debug_pc = _T_185 ? issue_slots_13_out_uop_debug_pc : issue_slots_12_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_is_rvc = _T_185 ? issue_slots_13_out_uop_is_rvc : issue_slots_12_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_debug_inst = _T_185 ? issue_slots_13_out_uop_debug_inst : issue_slots_12_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_11_in_uop_bits_inst = _T_185 ? issue_slots_13_out_uop_inst : issue_slots_12_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign _issue_slots_11_clear_T = |shamts_oh_11; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49]
assign issue_slots_11_clear = _issue_slots_11_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49]
wire _T_187 = shamts_oh_14 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28]
assign issue_slots_12_in_uop_valid = _T_187 ? issue_slots_14_will_be_valid : shamts_oh_13 == 2'h1 & issue_slots_13_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37]
assign issue_slots_12_in_uop_bits_debug_tsrc = _T_187 ? issue_slots_14_out_uop_debug_tsrc : issue_slots_13_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_debug_fsrc = _T_187 ? issue_slots_14_out_uop_debug_fsrc : issue_slots_13_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_bp_xcpt_if = _T_187 ? issue_slots_14_out_uop_bp_xcpt_if : issue_slots_13_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_bp_debug_if = _T_187 ? issue_slots_14_out_uop_bp_debug_if : issue_slots_13_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_xcpt_ma_if = _T_187 ? issue_slots_14_out_uop_xcpt_ma_if : issue_slots_13_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_xcpt_ae_if = _T_187 ? issue_slots_14_out_uop_xcpt_ae_if : issue_slots_13_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_xcpt_pf_if = _T_187 ? issue_slots_14_out_uop_xcpt_pf_if : issue_slots_13_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_fp_typ = _T_187 ? issue_slots_14_out_uop_fp_typ : issue_slots_13_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_fp_rm = _T_187 ? issue_slots_14_out_uop_fp_rm : issue_slots_13_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_fp_val = _T_187 ? issue_slots_14_out_uop_fp_val : issue_slots_13_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_fcn_op = _T_187 ? issue_slots_14_out_uop_fcn_op : issue_slots_13_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_fcn_dw = _T_187 ? issue_slots_14_out_uop_fcn_dw : issue_slots_13_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_frs3_en = _T_187 ? issue_slots_14_out_uop_frs3_en : issue_slots_13_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_lrs2_rtype = _T_187 ? issue_slots_14_out_uop_lrs2_rtype : issue_slots_13_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_lrs1_rtype = _T_187 ? issue_slots_14_out_uop_lrs1_rtype : issue_slots_13_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_dst_rtype = _T_187 ? issue_slots_14_out_uop_dst_rtype : issue_slots_13_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_lrs3 = _T_187 ? issue_slots_14_out_uop_lrs3 : issue_slots_13_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_lrs2 = _T_187 ? issue_slots_14_out_uop_lrs2 : issue_slots_13_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_lrs1 = _T_187 ? issue_slots_14_out_uop_lrs1 : issue_slots_13_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_ldst = _T_187 ? issue_slots_14_out_uop_ldst : issue_slots_13_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_ldst_is_rs1 = _T_187 ? issue_slots_14_out_uop_ldst_is_rs1 : issue_slots_13_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_csr_cmd = _T_187 ? issue_slots_14_out_uop_csr_cmd : issue_slots_13_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_flush_on_commit = _T_187 ? issue_slots_14_out_uop_flush_on_commit : issue_slots_13_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_is_unique = _T_187 ? issue_slots_14_out_uop_is_unique : issue_slots_13_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_uses_stq = _T_187 ? issue_slots_14_out_uop_uses_stq : issue_slots_13_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_uses_ldq = _T_187 ? issue_slots_14_out_uop_uses_ldq : issue_slots_13_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_mem_signed = _T_187 ? issue_slots_14_out_uop_mem_signed : issue_slots_13_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_mem_size = _T_187 ? issue_slots_14_out_uop_mem_size : issue_slots_13_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_mem_cmd = _T_187 ? issue_slots_14_out_uop_mem_cmd : issue_slots_13_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_exc_cause = _T_187 ? issue_slots_14_out_uop_exc_cause : issue_slots_13_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_exception = _T_187 ? issue_slots_14_out_uop_exception : issue_slots_13_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_stale_pdst = _T_187 ? issue_slots_14_out_uop_stale_pdst : issue_slots_13_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_ppred_busy = _T_187 ? issue_slots_14_out_uop_ppred_busy : issue_slots_13_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_prs3_busy = _T_187 ? issue_slots_14_out_uop_prs3_busy : issue_slots_13_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_prs2_busy = _T_187 ? issue_slots_14_out_uop_prs2_busy : issue_slots_13_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_prs1_busy = _T_187 ? issue_slots_14_out_uop_prs1_busy : issue_slots_13_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_ppred = _T_187 ? issue_slots_14_out_uop_ppred : issue_slots_13_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_prs3 = _T_187 ? issue_slots_14_out_uop_prs3 : issue_slots_13_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_prs2 = _T_187 ? issue_slots_14_out_uop_prs2 : issue_slots_13_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_prs1 = _T_187 ? issue_slots_14_out_uop_prs1 : issue_slots_13_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_pdst = _T_187 ? issue_slots_14_out_uop_pdst : issue_slots_13_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_rxq_idx = _T_187 ? issue_slots_14_out_uop_rxq_idx : issue_slots_13_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_stq_idx = _T_187 ? issue_slots_14_out_uop_stq_idx : issue_slots_13_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_ldq_idx = _T_187 ? issue_slots_14_out_uop_ldq_idx : issue_slots_13_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_rob_idx = _T_187 ? issue_slots_14_out_uop_rob_idx : issue_slots_13_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_fp_ctrl_vec = _T_187 ? issue_slots_14_out_uop_fp_ctrl_vec : issue_slots_13_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_fp_ctrl_wflags = _T_187 ? issue_slots_14_out_uop_fp_ctrl_wflags : issue_slots_13_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_fp_ctrl_sqrt = _T_187 ? issue_slots_14_out_uop_fp_ctrl_sqrt : issue_slots_13_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_fp_ctrl_div = _T_187 ? issue_slots_14_out_uop_fp_ctrl_div : issue_slots_13_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_fp_ctrl_fma = _T_187 ? issue_slots_14_out_uop_fp_ctrl_fma : issue_slots_13_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_fp_ctrl_fastpipe = _T_187 ? issue_slots_14_out_uop_fp_ctrl_fastpipe : issue_slots_13_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_fp_ctrl_toint = _T_187 ? issue_slots_14_out_uop_fp_ctrl_toint : issue_slots_13_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_fp_ctrl_fromint = _T_187 ? issue_slots_14_out_uop_fp_ctrl_fromint : issue_slots_13_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_fp_ctrl_typeTagOut = _T_187 ? issue_slots_14_out_uop_fp_ctrl_typeTagOut : issue_slots_13_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_fp_ctrl_typeTagIn = _T_187 ? issue_slots_14_out_uop_fp_ctrl_typeTagIn : issue_slots_13_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_fp_ctrl_swap23 = _T_187 ? issue_slots_14_out_uop_fp_ctrl_swap23 : issue_slots_13_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_fp_ctrl_swap12 = _T_187 ? issue_slots_14_out_uop_fp_ctrl_swap12 : issue_slots_13_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_fp_ctrl_ren3 = _T_187 ? issue_slots_14_out_uop_fp_ctrl_ren3 : issue_slots_13_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_fp_ctrl_ren2 = _T_187 ? issue_slots_14_out_uop_fp_ctrl_ren2 : issue_slots_13_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_fp_ctrl_ren1 = _T_187 ? issue_slots_14_out_uop_fp_ctrl_ren1 : issue_slots_13_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_fp_ctrl_wen = _T_187 ? issue_slots_14_out_uop_fp_ctrl_wen : issue_slots_13_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_fp_ctrl_ldst = _T_187 ? issue_slots_14_out_uop_fp_ctrl_ldst : issue_slots_13_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_op2_sel = _T_187 ? issue_slots_14_out_uop_op2_sel : issue_slots_13_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_op1_sel = _T_187 ? issue_slots_14_out_uop_op1_sel : issue_slots_13_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_imm_packed = _T_187 ? issue_slots_14_out_uop_imm_packed : issue_slots_13_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_pimm = _T_187 ? issue_slots_14_out_uop_pimm : issue_slots_13_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_imm_sel = _T_187 ? issue_slots_14_out_uop_imm_sel : issue_slots_13_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_imm_rename = _T_187 ? issue_slots_14_out_uop_imm_rename : issue_slots_13_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_taken = _T_187 ? issue_slots_14_out_uop_taken : issue_slots_13_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_pc_lob = _T_187 ? issue_slots_14_out_uop_pc_lob : issue_slots_13_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_edge_inst = _T_187 ? issue_slots_14_out_uop_edge_inst : issue_slots_13_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_ftq_idx = _T_187 ? issue_slots_14_out_uop_ftq_idx : issue_slots_13_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_is_mov = _T_187 ? issue_slots_14_out_uop_is_mov : issue_slots_13_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_is_rocc = _T_187 ? issue_slots_14_out_uop_is_rocc : issue_slots_13_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_is_sys_pc2epc = _T_187 ? issue_slots_14_out_uop_is_sys_pc2epc : issue_slots_13_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_is_eret = _T_187 ? issue_slots_14_out_uop_is_eret : issue_slots_13_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_is_amo = _T_187 ? issue_slots_14_out_uop_is_amo : issue_slots_13_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_is_sfence = _T_187 ? issue_slots_14_out_uop_is_sfence : issue_slots_13_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_is_fencei = _T_187 ? issue_slots_14_out_uop_is_fencei : issue_slots_13_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_is_fence = _T_187 ? issue_slots_14_out_uop_is_fence : issue_slots_13_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_is_sfb = _T_187 ? issue_slots_14_out_uop_is_sfb : issue_slots_13_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_br_type = _T_187 ? issue_slots_14_out_uop_br_type : issue_slots_13_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_br_tag = _T_187 ? issue_slots_14_out_uop_br_tag : issue_slots_13_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_br_mask = _T_187 ? issue_slots_14_out_uop_br_mask : issue_slots_13_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_dis_col_sel = _T_187 ? issue_slots_14_out_uop_dis_col_sel : issue_slots_13_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_iw_p3_bypass_hint = _T_187 ? issue_slots_14_out_uop_iw_p3_bypass_hint : issue_slots_13_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_iw_p2_bypass_hint = _T_187 ? issue_slots_14_out_uop_iw_p2_bypass_hint : issue_slots_13_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_iw_p1_bypass_hint = _T_187 ? issue_slots_14_out_uop_iw_p1_bypass_hint : issue_slots_13_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_iw_p2_speculative_child = _T_187 ? issue_slots_14_out_uop_iw_p2_speculative_child : issue_slots_13_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_iw_p1_speculative_child = _T_187 ? issue_slots_14_out_uop_iw_p1_speculative_child : issue_slots_13_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_iw_issued = _T_187 ? issue_slots_14_out_uop_iw_issued : issue_slots_13_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_fu_code_0 = _T_187 ? issue_slots_14_out_uop_fu_code_0 : issue_slots_13_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_fu_code_1 = _T_187 ? issue_slots_14_out_uop_fu_code_1 : issue_slots_13_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_fu_code_2 = _T_187 ? issue_slots_14_out_uop_fu_code_2 : issue_slots_13_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_fu_code_3 = _T_187 ? issue_slots_14_out_uop_fu_code_3 : issue_slots_13_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_fu_code_4 = _T_187 ? issue_slots_14_out_uop_fu_code_4 : issue_slots_13_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_fu_code_5 = _T_187 ? issue_slots_14_out_uop_fu_code_5 : issue_slots_13_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_fu_code_6 = _T_187 ? issue_slots_14_out_uop_fu_code_6 : issue_slots_13_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_fu_code_7 = _T_187 ? issue_slots_14_out_uop_fu_code_7 : issue_slots_13_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_fu_code_8 = _T_187 ? issue_slots_14_out_uop_fu_code_8 : issue_slots_13_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_fu_code_9 = _T_187 ? issue_slots_14_out_uop_fu_code_9 : issue_slots_13_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_iq_type_0 = _T_187 ? issue_slots_14_out_uop_iq_type_0 : issue_slots_13_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_iq_type_1 = _T_187 ? issue_slots_14_out_uop_iq_type_1 : issue_slots_13_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_iq_type_2 = _T_187 ? issue_slots_14_out_uop_iq_type_2 : issue_slots_13_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_iq_type_3 = _T_187 ? issue_slots_14_out_uop_iq_type_3 : issue_slots_13_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_debug_pc = _T_187 ? issue_slots_14_out_uop_debug_pc : issue_slots_13_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_is_rvc = _T_187 ? issue_slots_14_out_uop_is_rvc : issue_slots_13_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_debug_inst = _T_187 ? issue_slots_14_out_uop_debug_inst : issue_slots_13_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_12_in_uop_bits_inst = _T_187 ? issue_slots_14_out_uop_inst : issue_slots_13_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign _issue_slots_12_clear_T = |shamts_oh_12; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49]
assign issue_slots_12_clear = _issue_slots_12_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49]
wire _T_189 = shamts_oh_15 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28]
assign issue_slots_13_in_uop_valid = _T_189 ? issue_slots_15_will_be_valid : shamts_oh_14 == 2'h1 & issue_slots_14_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37]
assign issue_slots_13_in_uop_bits_debug_tsrc = _T_189 ? issue_slots_15_out_uop_debug_tsrc : issue_slots_14_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_debug_fsrc = _T_189 ? issue_slots_15_out_uop_debug_fsrc : issue_slots_14_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_bp_xcpt_if = _T_189 ? issue_slots_15_out_uop_bp_xcpt_if : issue_slots_14_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_bp_debug_if = _T_189 ? issue_slots_15_out_uop_bp_debug_if : issue_slots_14_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_xcpt_ma_if = _T_189 ? issue_slots_15_out_uop_xcpt_ma_if : issue_slots_14_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_xcpt_ae_if = _T_189 ? issue_slots_15_out_uop_xcpt_ae_if : issue_slots_14_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_xcpt_pf_if = _T_189 ? issue_slots_15_out_uop_xcpt_pf_if : issue_slots_14_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_fp_typ = _T_189 ? issue_slots_15_out_uop_fp_typ : issue_slots_14_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_fp_rm = _T_189 ? issue_slots_15_out_uop_fp_rm : issue_slots_14_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_fp_val = _T_189 ? issue_slots_15_out_uop_fp_val : issue_slots_14_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_fcn_op = _T_189 ? issue_slots_15_out_uop_fcn_op : issue_slots_14_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_fcn_dw = _T_189 ? issue_slots_15_out_uop_fcn_dw : issue_slots_14_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_frs3_en = _T_189 ? issue_slots_15_out_uop_frs3_en : issue_slots_14_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_lrs2_rtype = _T_189 ? issue_slots_15_out_uop_lrs2_rtype : issue_slots_14_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_lrs1_rtype = _T_189 ? issue_slots_15_out_uop_lrs1_rtype : issue_slots_14_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_dst_rtype = _T_189 ? issue_slots_15_out_uop_dst_rtype : issue_slots_14_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_lrs3 = _T_189 ? issue_slots_15_out_uop_lrs3 : issue_slots_14_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_lrs2 = _T_189 ? issue_slots_15_out_uop_lrs2 : issue_slots_14_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_lrs1 = _T_189 ? issue_slots_15_out_uop_lrs1 : issue_slots_14_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_ldst = _T_189 ? issue_slots_15_out_uop_ldst : issue_slots_14_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_ldst_is_rs1 = _T_189 ? issue_slots_15_out_uop_ldst_is_rs1 : issue_slots_14_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_csr_cmd = _T_189 ? issue_slots_15_out_uop_csr_cmd : issue_slots_14_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_flush_on_commit = _T_189 ? issue_slots_15_out_uop_flush_on_commit : issue_slots_14_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_is_unique = _T_189 ? issue_slots_15_out_uop_is_unique : issue_slots_14_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_uses_stq = _T_189 ? issue_slots_15_out_uop_uses_stq : issue_slots_14_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_uses_ldq = _T_189 ? issue_slots_15_out_uop_uses_ldq : issue_slots_14_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_mem_signed = _T_189 ? issue_slots_15_out_uop_mem_signed : issue_slots_14_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_mem_size = _T_189 ? issue_slots_15_out_uop_mem_size : issue_slots_14_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_mem_cmd = _T_189 ? issue_slots_15_out_uop_mem_cmd : issue_slots_14_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_exc_cause = _T_189 ? issue_slots_15_out_uop_exc_cause : issue_slots_14_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_exception = _T_189 ? issue_slots_15_out_uop_exception : issue_slots_14_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_stale_pdst = _T_189 ? issue_slots_15_out_uop_stale_pdst : issue_slots_14_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_ppred_busy = _T_189 ? issue_slots_15_out_uop_ppred_busy : issue_slots_14_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_prs3_busy = _T_189 ? issue_slots_15_out_uop_prs3_busy : issue_slots_14_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_prs2_busy = _T_189 ? issue_slots_15_out_uop_prs2_busy : issue_slots_14_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_prs1_busy = _T_189 ? issue_slots_15_out_uop_prs1_busy : issue_slots_14_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_ppred = _T_189 ? issue_slots_15_out_uop_ppred : issue_slots_14_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_prs3 = _T_189 ? issue_slots_15_out_uop_prs3 : issue_slots_14_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_prs2 = _T_189 ? issue_slots_15_out_uop_prs2 : issue_slots_14_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_prs1 = _T_189 ? issue_slots_15_out_uop_prs1 : issue_slots_14_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_pdst = _T_189 ? issue_slots_15_out_uop_pdst : issue_slots_14_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_rxq_idx = _T_189 ? issue_slots_15_out_uop_rxq_idx : issue_slots_14_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_stq_idx = _T_189 ? issue_slots_15_out_uop_stq_idx : issue_slots_14_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_ldq_idx = _T_189 ? issue_slots_15_out_uop_ldq_idx : issue_slots_14_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_rob_idx = _T_189 ? issue_slots_15_out_uop_rob_idx : issue_slots_14_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_fp_ctrl_vec = _T_189 ? issue_slots_15_out_uop_fp_ctrl_vec : issue_slots_14_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_fp_ctrl_wflags = _T_189 ? issue_slots_15_out_uop_fp_ctrl_wflags : issue_slots_14_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_fp_ctrl_sqrt = _T_189 ? issue_slots_15_out_uop_fp_ctrl_sqrt : issue_slots_14_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_fp_ctrl_div = _T_189 ? issue_slots_15_out_uop_fp_ctrl_div : issue_slots_14_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_fp_ctrl_fma = _T_189 ? issue_slots_15_out_uop_fp_ctrl_fma : issue_slots_14_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_fp_ctrl_fastpipe = _T_189 ? issue_slots_15_out_uop_fp_ctrl_fastpipe : issue_slots_14_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_fp_ctrl_toint = _T_189 ? issue_slots_15_out_uop_fp_ctrl_toint : issue_slots_14_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_fp_ctrl_fromint = _T_189 ? issue_slots_15_out_uop_fp_ctrl_fromint : issue_slots_14_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_fp_ctrl_typeTagOut = _T_189 ? issue_slots_15_out_uop_fp_ctrl_typeTagOut : issue_slots_14_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_fp_ctrl_typeTagIn = _T_189 ? issue_slots_15_out_uop_fp_ctrl_typeTagIn : issue_slots_14_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_fp_ctrl_swap23 = _T_189 ? issue_slots_15_out_uop_fp_ctrl_swap23 : issue_slots_14_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_fp_ctrl_swap12 = _T_189 ? issue_slots_15_out_uop_fp_ctrl_swap12 : issue_slots_14_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_fp_ctrl_ren3 = _T_189 ? issue_slots_15_out_uop_fp_ctrl_ren3 : issue_slots_14_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_fp_ctrl_ren2 = _T_189 ? issue_slots_15_out_uop_fp_ctrl_ren2 : issue_slots_14_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_fp_ctrl_ren1 = _T_189 ? issue_slots_15_out_uop_fp_ctrl_ren1 : issue_slots_14_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_fp_ctrl_wen = _T_189 ? issue_slots_15_out_uop_fp_ctrl_wen : issue_slots_14_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_fp_ctrl_ldst = _T_189 ? issue_slots_15_out_uop_fp_ctrl_ldst : issue_slots_14_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_op2_sel = _T_189 ? issue_slots_15_out_uop_op2_sel : issue_slots_14_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_op1_sel = _T_189 ? issue_slots_15_out_uop_op1_sel : issue_slots_14_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_imm_packed = _T_189 ? issue_slots_15_out_uop_imm_packed : issue_slots_14_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_pimm = _T_189 ? issue_slots_15_out_uop_pimm : issue_slots_14_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_imm_sel = _T_189 ? issue_slots_15_out_uop_imm_sel : issue_slots_14_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_imm_rename = _T_189 ? issue_slots_15_out_uop_imm_rename : issue_slots_14_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_taken = _T_189 ? issue_slots_15_out_uop_taken : issue_slots_14_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_pc_lob = _T_189 ? issue_slots_15_out_uop_pc_lob : issue_slots_14_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_edge_inst = _T_189 ? issue_slots_15_out_uop_edge_inst : issue_slots_14_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_ftq_idx = _T_189 ? issue_slots_15_out_uop_ftq_idx : issue_slots_14_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_is_mov = _T_189 ? issue_slots_15_out_uop_is_mov : issue_slots_14_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_is_rocc = _T_189 ? issue_slots_15_out_uop_is_rocc : issue_slots_14_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_is_sys_pc2epc = _T_189 ? issue_slots_15_out_uop_is_sys_pc2epc : issue_slots_14_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_is_eret = _T_189 ? issue_slots_15_out_uop_is_eret : issue_slots_14_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_is_amo = _T_189 ? issue_slots_15_out_uop_is_amo : issue_slots_14_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_is_sfence = _T_189 ? issue_slots_15_out_uop_is_sfence : issue_slots_14_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_is_fencei = _T_189 ? issue_slots_15_out_uop_is_fencei : issue_slots_14_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_is_fence = _T_189 ? issue_slots_15_out_uop_is_fence : issue_slots_14_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_is_sfb = _T_189 ? issue_slots_15_out_uop_is_sfb : issue_slots_14_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_br_type = _T_189 ? issue_slots_15_out_uop_br_type : issue_slots_14_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_br_tag = _T_189 ? issue_slots_15_out_uop_br_tag : issue_slots_14_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_br_mask = _T_189 ? issue_slots_15_out_uop_br_mask : issue_slots_14_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_dis_col_sel = _T_189 ? issue_slots_15_out_uop_dis_col_sel : issue_slots_14_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_iw_p3_bypass_hint = _T_189 ? issue_slots_15_out_uop_iw_p3_bypass_hint : issue_slots_14_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_iw_p2_bypass_hint = _T_189 ? issue_slots_15_out_uop_iw_p2_bypass_hint : issue_slots_14_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_iw_p1_bypass_hint = _T_189 ? issue_slots_15_out_uop_iw_p1_bypass_hint : issue_slots_14_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_iw_p2_speculative_child = _T_189 ? issue_slots_15_out_uop_iw_p2_speculative_child : issue_slots_14_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_iw_p1_speculative_child = _T_189 ? issue_slots_15_out_uop_iw_p1_speculative_child : issue_slots_14_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_iw_issued = _T_189 ? issue_slots_15_out_uop_iw_issued : issue_slots_14_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_fu_code_0 = _T_189 ? issue_slots_15_out_uop_fu_code_0 : issue_slots_14_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_fu_code_1 = _T_189 ? issue_slots_15_out_uop_fu_code_1 : issue_slots_14_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_fu_code_2 = _T_189 ? issue_slots_15_out_uop_fu_code_2 : issue_slots_14_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_fu_code_3 = _T_189 ? issue_slots_15_out_uop_fu_code_3 : issue_slots_14_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_fu_code_4 = _T_189 ? issue_slots_15_out_uop_fu_code_4 : issue_slots_14_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_fu_code_5 = _T_189 ? issue_slots_15_out_uop_fu_code_5 : issue_slots_14_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_fu_code_6 = _T_189 ? issue_slots_15_out_uop_fu_code_6 : issue_slots_14_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_fu_code_7 = _T_189 ? issue_slots_15_out_uop_fu_code_7 : issue_slots_14_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_fu_code_8 = _T_189 ? issue_slots_15_out_uop_fu_code_8 : issue_slots_14_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_fu_code_9 = _T_189 ? issue_slots_15_out_uop_fu_code_9 : issue_slots_14_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_iq_type_0 = _T_189 ? issue_slots_15_out_uop_iq_type_0 : issue_slots_14_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_iq_type_1 = _T_189 ? issue_slots_15_out_uop_iq_type_1 : issue_slots_14_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_iq_type_2 = _T_189 ? issue_slots_15_out_uop_iq_type_2 : issue_slots_14_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_iq_type_3 = _T_189 ? issue_slots_15_out_uop_iq_type_3 : issue_slots_14_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_debug_pc = _T_189 ? issue_slots_15_out_uop_debug_pc : issue_slots_14_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_is_rvc = _T_189 ? issue_slots_15_out_uop_is_rvc : issue_slots_14_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_debug_inst = _T_189 ? issue_slots_15_out_uop_debug_inst : issue_slots_14_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_13_in_uop_bits_inst = _T_189 ? issue_slots_15_out_uop_inst : issue_slots_14_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign _issue_slots_13_clear_T = |shamts_oh_13; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49]
assign issue_slots_13_clear = _issue_slots_13_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49]
wire _T_191 = shamts_oh_16 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28]
assign issue_slots_14_in_uop_valid = _T_191 ? issue_slots_16_will_be_valid : shamts_oh_15 == 2'h1 & issue_slots_15_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37]
assign issue_slots_14_in_uop_bits_debug_tsrc = _T_191 ? issue_slots_16_out_uop_debug_tsrc : issue_slots_15_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_debug_fsrc = _T_191 ? issue_slots_16_out_uop_debug_fsrc : issue_slots_15_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_bp_xcpt_if = _T_191 ? issue_slots_16_out_uop_bp_xcpt_if : issue_slots_15_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_bp_debug_if = _T_191 ? issue_slots_16_out_uop_bp_debug_if : issue_slots_15_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_xcpt_ma_if = _T_191 ? issue_slots_16_out_uop_xcpt_ma_if : issue_slots_15_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_xcpt_ae_if = _T_191 ? issue_slots_16_out_uop_xcpt_ae_if : issue_slots_15_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_xcpt_pf_if = _T_191 ? issue_slots_16_out_uop_xcpt_pf_if : issue_slots_15_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_fp_typ = _T_191 ? issue_slots_16_out_uop_fp_typ : issue_slots_15_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_fp_rm = _T_191 ? issue_slots_16_out_uop_fp_rm : issue_slots_15_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_fp_val = _T_191 ? issue_slots_16_out_uop_fp_val : issue_slots_15_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_fcn_op = _T_191 ? issue_slots_16_out_uop_fcn_op : issue_slots_15_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_fcn_dw = _T_191 ? issue_slots_16_out_uop_fcn_dw : issue_slots_15_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_frs3_en = _T_191 ? issue_slots_16_out_uop_frs3_en : issue_slots_15_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_lrs2_rtype = _T_191 ? issue_slots_16_out_uop_lrs2_rtype : issue_slots_15_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_lrs1_rtype = _T_191 ? issue_slots_16_out_uop_lrs1_rtype : issue_slots_15_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_dst_rtype = _T_191 ? issue_slots_16_out_uop_dst_rtype : issue_slots_15_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_lrs3 = _T_191 ? issue_slots_16_out_uop_lrs3 : issue_slots_15_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_lrs2 = _T_191 ? issue_slots_16_out_uop_lrs2 : issue_slots_15_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_lrs1 = _T_191 ? issue_slots_16_out_uop_lrs1 : issue_slots_15_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_ldst = _T_191 ? issue_slots_16_out_uop_ldst : issue_slots_15_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_ldst_is_rs1 = _T_191 ? issue_slots_16_out_uop_ldst_is_rs1 : issue_slots_15_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_csr_cmd = _T_191 ? issue_slots_16_out_uop_csr_cmd : issue_slots_15_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_flush_on_commit = _T_191 ? issue_slots_16_out_uop_flush_on_commit : issue_slots_15_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_is_unique = _T_191 ? issue_slots_16_out_uop_is_unique : issue_slots_15_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_uses_stq = _T_191 ? issue_slots_16_out_uop_uses_stq : issue_slots_15_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_uses_ldq = _T_191 ? issue_slots_16_out_uop_uses_ldq : issue_slots_15_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_mem_signed = _T_191 ? issue_slots_16_out_uop_mem_signed : issue_slots_15_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_mem_size = _T_191 ? issue_slots_16_out_uop_mem_size : issue_slots_15_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_mem_cmd = _T_191 ? issue_slots_16_out_uop_mem_cmd : issue_slots_15_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_exc_cause = _T_191 ? issue_slots_16_out_uop_exc_cause : issue_slots_15_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_exception = _T_191 ? issue_slots_16_out_uop_exception : issue_slots_15_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_stale_pdst = _T_191 ? issue_slots_16_out_uop_stale_pdst : issue_slots_15_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_ppred_busy = _T_191 ? issue_slots_16_out_uop_ppred_busy : issue_slots_15_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_prs3_busy = _T_191 ? issue_slots_16_out_uop_prs3_busy : issue_slots_15_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_prs2_busy = _T_191 ? issue_slots_16_out_uop_prs2_busy : issue_slots_15_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_prs1_busy = _T_191 ? issue_slots_16_out_uop_prs1_busy : issue_slots_15_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_ppred = _T_191 ? issue_slots_16_out_uop_ppred : issue_slots_15_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_prs3 = _T_191 ? issue_slots_16_out_uop_prs3 : issue_slots_15_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_prs2 = _T_191 ? issue_slots_16_out_uop_prs2 : issue_slots_15_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_prs1 = _T_191 ? issue_slots_16_out_uop_prs1 : issue_slots_15_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_pdst = _T_191 ? issue_slots_16_out_uop_pdst : issue_slots_15_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_rxq_idx = _T_191 ? issue_slots_16_out_uop_rxq_idx : issue_slots_15_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_stq_idx = _T_191 ? issue_slots_16_out_uop_stq_idx : issue_slots_15_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_ldq_idx = _T_191 ? issue_slots_16_out_uop_ldq_idx : issue_slots_15_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_rob_idx = _T_191 ? issue_slots_16_out_uop_rob_idx : issue_slots_15_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_fp_ctrl_vec = _T_191 ? issue_slots_16_out_uop_fp_ctrl_vec : issue_slots_15_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_fp_ctrl_wflags = _T_191 ? issue_slots_16_out_uop_fp_ctrl_wflags : issue_slots_15_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_fp_ctrl_sqrt = _T_191 ? issue_slots_16_out_uop_fp_ctrl_sqrt : issue_slots_15_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_fp_ctrl_div = _T_191 ? issue_slots_16_out_uop_fp_ctrl_div : issue_slots_15_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_fp_ctrl_fma = _T_191 ? issue_slots_16_out_uop_fp_ctrl_fma : issue_slots_15_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_fp_ctrl_fastpipe = _T_191 ? issue_slots_16_out_uop_fp_ctrl_fastpipe : issue_slots_15_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_fp_ctrl_toint = _T_191 ? issue_slots_16_out_uop_fp_ctrl_toint : issue_slots_15_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_fp_ctrl_fromint = _T_191 ? issue_slots_16_out_uop_fp_ctrl_fromint : issue_slots_15_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_fp_ctrl_typeTagOut = _T_191 ? issue_slots_16_out_uop_fp_ctrl_typeTagOut : issue_slots_15_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_fp_ctrl_typeTagIn = _T_191 ? issue_slots_16_out_uop_fp_ctrl_typeTagIn : issue_slots_15_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_fp_ctrl_swap23 = _T_191 ? issue_slots_16_out_uop_fp_ctrl_swap23 : issue_slots_15_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_fp_ctrl_swap12 = _T_191 ? issue_slots_16_out_uop_fp_ctrl_swap12 : issue_slots_15_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_fp_ctrl_ren3 = _T_191 ? issue_slots_16_out_uop_fp_ctrl_ren3 : issue_slots_15_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_fp_ctrl_ren2 = _T_191 ? issue_slots_16_out_uop_fp_ctrl_ren2 : issue_slots_15_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_fp_ctrl_ren1 = _T_191 ? issue_slots_16_out_uop_fp_ctrl_ren1 : issue_slots_15_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_fp_ctrl_wen = _T_191 ? issue_slots_16_out_uop_fp_ctrl_wen : issue_slots_15_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_fp_ctrl_ldst = _T_191 ? issue_slots_16_out_uop_fp_ctrl_ldst : issue_slots_15_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_op2_sel = _T_191 ? issue_slots_16_out_uop_op2_sel : issue_slots_15_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_op1_sel = _T_191 ? issue_slots_16_out_uop_op1_sel : issue_slots_15_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_imm_packed = _T_191 ? issue_slots_16_out_uop_imm_packed : issue_slots_15_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_pimm = _T_191 ? issue_slots_16_out_uop_pimm : issue_slots_15_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_imm_sel = _T_191 ? issue_slots_16_out_uop_imm_sel : issue_slots_15_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_imm_rename = _T_191 ? issue_slots_16_out_uop_imm_rename : issue_slots_15_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_taken = _T_191 ? issue_slots_16_out_uop_taken : issue_slots_15_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_pc_lob = _T_191 ? issue_slots_16_out_uop_pc_lob : issue_slots_15_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_edge_inst = _T_191 ? issue_slots_16_out_uop_edge_inst : issue_slots_15_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_ftq_idx = _T_191 ? issue_slots_16_out_uop_ftq_idx : issue_slots_15_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_is_mov = _T_191 ? issue_slots_16_out_uop_is_mov : issue_slots_15_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_is_rocc = _T_191 ? issue_slots_16_out_uop_is_rocc : issue_slots_15_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_is_sys_pc2epc = _T_191 ? issue_slots_16_out_uop_is_sys_pc2epc : issue_slots_15_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_is_eret = _T_191 ? issue_slots_16_out_uop_is_eret : issue_slots_15_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_is_amo = _T_191 ? issue_slots_16_out_uop_is_amo : issue_slots_15_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_is_sfence = _T_191 ? issue_slots_16_out_uop_is_sfence : issue_slots_15_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_is_fencei = _T_191 ? issue_slots_16_out_uop_is_fencei : issue_slots_15_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_is_fence = _T_191 ? issue_slots_16_out_uop_is_fence : issue_slots_15_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_is_sfb = _T_191 ? issue_slots_16_out_uop_is_sfb : issue_slots_15_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_br_type = _T_191 ? issue_slots_16_out_uop_br_type : issue_slots_15_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_br_tag = _T_191 ? issue_slots_16_out_uop_br_tag : issue_slots_15_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_br_mask = _T_191 ? issue_slots_16_out_uop_br_mask : issue_slots_15_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_dis_col_sel = _T_191 ? issue_slots_16_out_uop_dis_col_sel : issue_slots_15_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_iw_p3_bypass_hint = _T_191 ? issue_slots_16_out_uop_iw_p3_bypass_hint : issue_slots_15_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_iw_p2_bypass_hint = _T_191 ? issue_slots_16_out_uop_iw_p2_bypass_hint : issue_slots_15_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_iw_p1_bypass_hint = _T_191 ? issue_slots_16_out_uop_iw_p1_bypass_hint : issue_slots_15_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_iw_p2_speculative_child = _T_191 ? issue_slots_16_out_uop_iw_p2_speculative_child : issue_slots_15_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_iw_p1_speculative_child = _T_191 ? issue_slots_16_out_uop_iw_p1_speculative_child : issue_slots_15_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_iw_issued = _T_191 ? issue_slots_16_out_uop_iw_issued : issue_slots_15_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_fu_code_0 = _T_191 ? issue_slots_16_out_uop_fu_code_0 : issue_slots_15_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_fu_code_1 = _T_191 ? issue_slots_16_out_uop_fu_code_1 : issue_slots_15_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_fu_code_2 = _T_191 ? issue_slots_16_out_uop_fu_code_2 : issue_slots_15_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_fu_code_3 = _T_191 ? issue_slots_16_out_uop_fu_code_3 : issue_slots_15_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_fu_code_4 = _T_191 ? issue_slots_16_out_uop_fu_code_4 : issue_slots_15_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_fu_code_5 = _T_191 ? issue_slots_16_out_uop_fu_code_5 : issue_slots_15_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_fu_code_6 = _T_191 ? issue_slots_16_out_uop_fu_code_6 : issue_slots_15_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_fu_code_7 = _T_191 ? issue_slots_16_out_uop_fu_code_7 : issue_slots_15_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_fu_code_8 = _T_191 ? issue_slots_16_out_uop_fu_code_8 : issue_slots_15_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_fu_code_9 = _T_191 ? issue_slots_16_out_uop_fu_code_9 : issue_slots_15_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_iq_type_0 = _T_191 ? issue_slots_16_out_uop_iq_type_0 : issue_slots_15_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_iq_type_1 = _T_191 ? issue_slots_16_out_uop_iq_type_1 : issue_slots_15_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_iq_type_2 = _T_191 ? issue_slots_16_out_uop_iq_type_2 : issue_slots_15_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_iq_type_3 = _T_191 ? issue_slots_16_out_uop_iq_type_3 : issue_slots_15_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_debug_pc = _T_191 ? issue_slots_16_out_uop_debug_pc : issue_slots_15_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_is_rvc = _T_191 ? issue_slots_16_out_uop_is_rvc : issue_slots_15_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_debug_inst = _T_191 ? issue_slots_16_out_uop_debug_inst : issue_slots_15_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_14_in_uop_bits_inst = _T_191 ? issue_slots_16_out_uop_inst : issue_slots_15_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign _issue_slots_14_clear_T = |shamts_oh_14; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49]
assign issue_slots_14_clear = _issue_slots_14_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49]
wire _T_193 = shamts_oh_17 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28]
assign issue_slots_15_in_uop_valid = _T_193 ? issue_slots_17_will_be_valid : shamts_oh_16 == 2'h1 & issue_slots_16_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37]
assign issue_slots_15_in_uop_bits_debug_tsrc = _T_193 ? issue_slots_17_out_uop_debug_tsrc : issue_slots_16_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_debug_fsrc = _T_193 ? issue_slots_17_out_uop_debug_fsrc : issue_slots_16_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_bp_xcpt_if = _T_193 ? issue_slots_17_out_uop_bp_xcpt_if : issue_slots_16_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_bp_debug_if = _T_193 ? issue_slots_17_out_uop_bp_debug_if : issue_slots_16_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_xcpt_ma_if = _T_193 ? issue_slots_17_out_uop_xcpt_ma_if : issue_slots_16_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_xcpt_ae_if = _T_193 ? issue_slots_17_out_uop_xcpt_ae_if : issue_slots_16_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_xcpt_pf_if = _T_193 ? issue_slots_17_out_uop_xcpt_pf_if : issue_slots_16_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_fp_typ = _T_193 ? issue_slots_17_out_uop_fp_typ : issue_slots_16_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_fp_rm = _T_193 ? issue_slots_17_out_uop_fp_rm : issue_slots_16_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_fp_val = _T_193 ? issue_slots_17_out_uop_fp_val : issue_slots_16_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_fcn_op = _T_193 ? issue_slots_17_out_uop_fcn_op : issue_slots_16_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_fcn_dw = _T_193 ? issue_slots_17_out_uop_fcn_dw : issue_slots_16_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_frs3_en = _T_193 ? issue_slots_17_out_uop_frs3_en : issue_slots_16_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_lrs2_rtype = _T_193 ? issue_slots_17_out_uop_lrs2_rtype : issue_slots_16_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_lrs1_rtype = _T_193 ? issue_slots_17_out_uop_lrs1_rtype : issue_slots_16_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_dst_rtype = _T_193 ? issue_slots_17_out_uop_dst_rtype : issue_slots_16_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_lrs3 = _T_193 ? issue_slots_17_out_uop_lrs3 : issue_slots_16_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_lrs2 = _T_193 ? issue_slots_17_out_uop_lrs2 : issue_slots_16_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_lrs1 = _T_193 ? issue_slots_17_out_uop_lrs1 : issue_slots_16_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_ldst = _T_193 ? issue_slots_17_out_uop_ldst : issue_slots_16_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_ldst_is_rs1 = _T_193 ? issue_slots_17_out_uop_ldst_is_rs1 : issue_slots_16_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_csr_cmd = _T_193 ? issue_slots_17_out_uop_csr_cmd : issue_slots_16_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_flush_on_commit = _T_193 ? issue_slots_17_out_uop_flush_on_commit : issue_slots_16_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_is_unique = _T_193 ? issue_slots_17_out_uop_is_unique : issue_slots_16_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_uses_stq = _T_193 ? issue_slots_17_out_uop_uses_stq : issue_slots_16_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_uses_ldq = _T_193 ? issue_slots_17_out_uop_uses_ldq : issue_slots_16_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_mem_signed = _T_193 ? issue_slots_17_out_uop_mem_signed : issue_slots_16_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_mem_size = _T_193 ? issue_slots_17_out_uop_mem_size : issue_slots_16_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_mem_cmd = _T_193 ? issue_slots_17_out_uop_mem_cmd : issue_slots_16_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_exc_cause = _T_193 ? issue_slots_17_out_uop_exc_cause : issue_slots_16_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_exception = _T_193 ? issue_slots_17_out_uop_exception : issue_slots_16_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_stale_pdst = _T_193 ? issue_slots_17_out_uop_stale_pdst : issue_slots_16_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_ppred_busy = _T_193 ? issue_slots_17_out_uop_ppred_busy : issue_slots_16_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_prs3_busy = _T_193 ? issue_slots_17_out_uop_prs3_busy : issue_slots_16_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_prs2_busy = _T_193 ? issue_slots_17_out_uop_prs2_busy : issue_slots_16_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_prs1_busy = _T_193 ? issue_slots_17_out_uop_prs1_busy : issue_slots_16_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_ppred = _T_193 ? issue_slots_17_out_uop_ppred : issue_slots_16_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_prs3 = _T_193 ? issue_slots_17_out_uop_prs3 : issue_slots_16_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_prs2 = _T_193 ? issue_slots_17_out_uop_prs2 : issue_slots_16_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_prs1 = _T_193 ? issue_slots_17_out_uop_prs1 : issue_slots_16_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_pdst = _T_193 ? issue_slots_17_out_uop_pdst : issue_slots_16_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_rxq_idx = _T_193 ? issue_slots_17_out_uop_rxq_idx : issue_slots_16_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_stq_idx = _T_193 ? issue_slots_17_out_uop_stq_idx : issue_slots_16_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_ldq_idx = _T_193 ? issue_slots_17_out_uop_ldq_idx : issue_slots_16_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_rob_idx = _T_193 ? issue_slots_17_out_uop_rob_idx : issue_slots_16_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_fp_ctrl_vec = _T_193 ? issue_slots_17_out_uop_fp_ctrl_vec : issue_slots_16_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_fp_ctrl_wflags = _T_193 ? issue_slots_17_out_uop_fp_ctrl_wflags : issue_slots_16_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_fp_ctrl_sqrt = _T_193 ? issue_slots_17_out_uop_fp_ctrl_sqrt : issue_slots_16_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_fp_ctrl_div = _T_193 ? issue_slots_17_out_uop_fp_ctrl_div : issue_slots_16_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_fp_ctrl_fma = _T_193 ? issue_slots_17_out_uop_fp_ctrl_fma : issue_slots_16_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_fp_ctrl_fastpipe = _T_193 ? issue_slots_17_out_uop_fp_ctrl_fastpipe : issue_slots_16_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_fp_ctrl_toint = _T_193 ? issue_slots_17_out_uop_fp_ctrl_toint : issue_slots_16_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_fp_ctrl_fromint = _T_193 ? issue_slots_17_out_uop_fp_ctrl_fromint : issue_slots_16_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_fp_ctrl_typeTagOut = _T_193 ? issue_slots_17_out_uop_fp_ctrl_typeTagOut : issue_slots_16_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_fp_ctrl_typeTagIn = _T_193 ? issue_slots_17_out_uop_fp_ctrl_typeTagIn : issue_slots_16_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_fp_ctrl_swap23 = _T_193 ? issue_slots_17_out_uop_fp_ctrl_swap23 : issue_slots_16_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_fp_ctrl_swap12 = _T_193 ? issue_slots_17_out_uop_fp_ctrl_swap12 : issue_slots_16_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_fp_ctrl_ren3 = _T_193 ? issue_slots_17_out_uop_fp_ctrl_ren3 : issue_slots_16_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_fp_ctrl_ren2 = _T_193 ? issue_slots_17_out_uop_fp_ctrl_ren2 : issue_slots_16_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_fp_ctrl_ren1 = _T_193 ? issue_slots_17_out_uop_fp_ctrl_ren1 : issue_slots_16_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_fp_ctrl_wen = _T_193 ? issue_slots_17_out_uop_fp_ctrl_wen : issue_slots_16_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_fp_ctrl_ldst = _T_193 ? issue_slots_17_out_uop_fp_ctrl_ldst : issue_slots_16_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_op2_sel = _T_193 ? issue_slots_17_out_uop_op2_sel : issue_slots_16_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_op1_sel = _T_193 ? issue_slots_17_out_uop_op1_sel : issue_slots_16_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_imm_packed = _T_193 ? issue_slots_17_out_uop_imm_packed : issue_slots_16_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_pimm = _T_193 ? issue_slots_17_out_uop_pimm : issue_slots_16_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_imm_sel = _T_193 ? issue_slots_17_out_uop_imm_sel : issue_slots_16_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_imm_rename = _T_193 ? issue_slots_17_out_uop_imm_rename : issue_slots_16_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_taken = _T_193 ? issue_slots_17_out_uop_taken : issue_slots_16_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_pc_lob = _T_193 ? issue_slots_17_out_uop_pc_lob : issue_slots_16_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_edge_inst = _T_193 ? issue_slots_17_out_uop_edge_inst : issue_slots_16_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_ftq_idx = _T_193 ? issue_slots_17_out_uop_ftq_idx : issue_slots_16_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_is_mov = _T_193 ? issue_slots_17_out_uop_is_mov : issue_slots_16_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_is_rocc = _T_193 ? issue_slots_17_out_uop_is_rocc : issue_slots_16_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_is_sys_pc2epc = _T_193 ? issue_slots_17_out_uop_is_sys_pc2epc : issue_slots_16_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_is_eret = _T_193 ? issue_slots_17_out_uop_is_eret : issue_slots_16_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_is_amo = _T_193 ? issue_slots_17_out_uop_is_amo : issue_slots_16_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_is_sfence = _T_193 ? issue_slots_17_out_uop_is_sfence : issue_slots_16_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_is_fencei = _T_193 ? issue_slots_17_out_uop_is_fencei : issue_slots_16_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_is_fence = _T_193 ? issue_slots_17_out_uop_is_fence : issue_slots_16_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_is_sfb = _T_193 ? issue_slots_17_out_uop_is_sfb : issue_slots_16_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_br_type = _T_193 ? issue_slots_17_out_uop_br_type : issue_slots_16_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_br_tag = _T_193 ? issue_slots_17_out_uop_br_tag : issue_slots_16_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_br_mask = _T_193 ? issue_slots_17_out_uop_br_mask : issue_slots_16_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_dis_col_sel = _T_193 ? issue_slots_17_out_uop_dis_col_sel : issue_slots_16_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_iw_p3_bypass_hint = _T_193 ? issue_slots_17_out_uop_iw_p3_bypass_hint : issue_slots_16_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_iw_p2_bypass_hint = _T_193 ? issue_slots_17_out_uop_iw_p2_bypass_hint : issue_slots_16_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_iw_p1_bypass_hint = _T_193 ? issue_slots_17_out_uop_iw_p1_bypass_hint : issue_slots_16_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_iw_p2_speculative_child = _T_193 ? issue_slots_17_out_uop_iw_p2_speculative_child : issue_slots_16_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_iw_p1_speculative_child = _T_193 ? issue_slots_17_out_uop_iw_p1_speculative_child : issue_slots_16_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_iw_issued = _T_193 ? issue_slots_17_out_uop_iw_issued : issue_slots_16_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_fu_code_0 = _T_193 ? issue_slots_17_out_uop_fu_code_0 : issue_slots_16_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_fu_code_1 = _T_193 ? issue_slots_17_out_uop_fu_code_1 : issue_slots_16_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_fu_code_2 = _T_193 ? issue_slots_17_out_uop_fu_code_2 : issue_slots_16_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_fu_code_3 = _T_193 ? issue_slots_17_out_uop_fu_code_3 : issue_slots_16_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_fu_code_4 = _T_193 ? issue_slots_17_out_uop_fu_code_4 : issue_slots_16_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_fu_code_5 = _T_193 ? issue_slots_17_out_uop_fu_code_5 : issue_slots_16_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_fu_code_6 = _T_193 ? issue_slots_17_out_uop_fu_code_6 : issue_slots_16_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_fu_code_7 = _T_193 ? issue_slots_17_out_uop_fu_code_7 : issue_slots_16_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_fu_code_8 = _T_193 ? issue_slots_17_out_uop_fu_code_8 : issue_slots_16_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_fu_code_9 = _T_193 ? issue_slots_17_out_uop_fu_code_9 : issue_slots_16_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_iq_type_0 = _T_193 ? issue_slots_17_out_uop_iq_type_0 : issue_slots_16_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_iq_type_1 = _T_193 ? issue_slots_17_out_uop_iq_type_1 : issue_slots_16_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_iq_type_2 = _T_193 ? issue_slots_17_out_uop_iq_type_2 : issue_slots_16_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_iq_type_3 = _T_193 ? issue_slots_17_out_uop_iq_type_3 : issue_slots_16_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_debug_pc = _T_193 ? issue_slots_17_out_uop_debug_pc : issue_slots_16_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_is_rvc = _T_193 ? issue_slots_17_out_uop_is_rvc : issue_slots_16_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_debug_inst = _T_193 ? issue_slots_17_out_uop_debug_inst : issue_slots_16_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_15_in_uop_bits_inst = _T_193 ? issue_slots_17_out_uop_inst : issue_slots_16_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign _issue_slots_15_clear_T = |shamts_oh_15; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49]
assign issue_slots_15_clear = _issue_slots_15_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49]
wire _T_195 = shamts_oh_18 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28]
assign issue_slots_16_in_uop_valid = _T_195 ? issue_slots_18_will_be_valid : shamts_oh_17 == 2'h1 & issue_slots_17_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37]
assign issue_slots_16_in_uop_bits_debug_tsrc = _T_195 ? issue_slots_18_out_uop_debug_tsrc : issue_slots_17_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_debug_fsrc = _T_195 ? issue_slots_18_out_uop_debug_fsrc : issue_slots_17_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_bp_xcpt_if = _T_195 ? issue_slots_18_out_uop_bp_xcpt_if : issue_slots_17_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_bp_debug_if = _T_195 ? issue_slots_18_out_uop_bp_debug_if : issue_slots_17_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_xcpt_ma_if = _T_195 ? issue_slots_18_out_uop_xcpt_ma_if : issue_slots_17_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_xcpt_ae_if = _T_195 ? issue_slots_18_out_uop_xcpt_ae_if : issue_slots_17_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_xcpt_pf_if = _T_195 ? issue_slots_18_out_uop_xcpt_pf_if : issue_slots_17_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_fp_typ = _T_195 ? issue_slots_18_out_uop_fp_typ : issue_slots_17_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_fp_rm = _T_195 ? issue_slots_18_out_uop_fp_rm : issue_slots_17_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_fp_val = _T_195 ? issue_slots_18_out_uop_fp_val : issue_slots_17_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_fcn_op = _T_195 ? issue_slots_18_out_uop_fcn_op : issue_slots_17_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_fcn_dw = _T_195 ? issue_slots_18_out_uop_fcn_dw : issue_slots_17_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_frs3_en = _T_195 ? issue_slots_18_out_uop_frs3_en : issue_slots_17_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_lrs2_rtype = _T_195 ? issue_slots_18_out_uop_lrs2_rtype : issue_slots_17_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_lrs1_rtype = _T_195 ? issue_slots_18_out_uop_lrs1_rtype : issue_slots_17_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_dst_rtype = _T_195 ? issue_slots_18_out_uop_dst_rtype : issue_slots_17_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_lrs3 = _T_195 ? issue_slots_18_out_uop_lrs3 : issue_slots_17_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_lrs2 = _T_195 ? issue_slots_18_out_uop_lrs2 : issue_slots_17_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_lrs1 = _T_195 ? issue_slots_18_out_uop_lrs1 : issue_slots_17_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_ldst = _T_195 ? issue_slots_18_out_uop_ldst : issue_slots_17_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_ldst_is_rs1 = _T_195 ? issue_slots_18_out_uop_ldst_is_rs1 : issue_slots_17_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_csr_cmd = _T_195 ? issue_slots_18_out_uop_csr_cmd : issue_slots_17_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_flush_on_commit = _T_195 ? issue_slots_18_out_uop_flush_on_commit : issue_slots_17_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_is_unique = _T_195 ? issue_slots_18_out_uop_is_unique : issue_slots_17_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_uses_stq = _T_195 ? issue_slots_18_out_uop_uses_stq : issue_slots_17_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_uses_ldq = _T_195 ? issue_slots_18_out_uop_uses_ldq : issue_slots_17_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_mem_signed = _T_195 ? issue_slots_18_out_uop_mem_signed : issue_slots_17_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_mem_size = _T_195 ? issue_slots_18_out_uop_mem_size : issue_slots_17_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_mem_cmd = _T_195 ? issue_slots_18_out_uop_mem_cmd : issue_slots_17_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_exc_cause = _T_195 ? issue_slots_18_out_uop_exc_cause : issue_slots_17_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_exception = _T_195 ? issue_slots_18_out_uop_exception : issue_slots_17_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_stale_pdst = _T_195 ? issue_slots_18_out_uop_stale_pdst : issue_slots_17_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_ppred_busy = _T_195 ? issue_slots_18_out_uop_ppred_busy : issue_slots_17_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_prs3_busy = _T_195 ? issue_slots_18_out_uop_prs3_busy : issue_slots_17_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_prs2_busy = _T_195 ? issue_slots_18_out_uop_prs2_busy : issue_slots_17_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_prs1_busy = _T_195 ? issue_slots_18_out_uop_prs1_busy : issue_slots_17_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_ppred = _T_195 ? issue_slots_18_out_uop_ppred : issue_slots_17_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_prs3 = _T_195 ? issue_slots_18_out_uop_prs3 : issue_slots_17_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_prs2 = _T_195 ? issue_slots_18_out_uop_prs2 : issue_slots_17_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_prs1 = _T_195 ? issue_slots_18_out_uop_prs1 : issue_slots_17_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_pdst = _T_195 ? issue_slots_18_out_uop_pdst : issue_slots_17_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_rxq_idx = _T_195 ? issue_slots_18_out_uop_rxq_idx : issue_slots_17_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_stq_idx = _T_195 ? issue_slots_18_out_uop_stq_idx : issue_slots_17_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_ldq_idx = _T_195 ? issue_slots_18_out_uop_ldq_idx : issue_slots_17_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_rob_idx = _T_195 ? issue_slots_18_out_uop_rob_idx : issue_slots_17_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_fp_ctrl_vec = _T_195 ? issue_slots_18_out_uop_fp_ctrl_vec : issue_slots_17_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_fp_ctrl_wflags = _T_195 ? issue_slots_18_out_uop_fp_ctrl_wflags : issue_slots_17_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_fp_ctrl_sqrt = _T_195 ? issue_slots_18_out_uop_fp_ctrl_sqrt : issue_slots_17_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_fp_ctrl_div = _T_195 ? issue_slots_18_out_uop_fp_ctrl_div : issue_slots_17_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_fp_ctrl_fma = _T_195 ? issue_slots_18_out_uop_fp_ctrl_fma : issue_slots_17_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_fp_ctrl_fastpipe = _T_195 ? issue_slots_18_out_uop_fp_ctrl_fastpipe : issue_slots_17_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_fp_ctrl_toint = _T_195 ? issue_slots_18_out_uop_fp_ctrl_toint : issue_slots_17_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_fp_ctrl_fromint = _T_195 ? issue_slots_18_out_uop_fp_ctrl_fromint : issue_slots_17_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_fp_ctrl_typeTagOut = _T_195 ? issue_slots_18_out_uop_fp_ctrl_typeTagOut : issue_slots_17_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_fp_ctrl_typeTagIn = _T_195 ? issue_slots_18_out_uop_fp_ctrl_typeTagIn : issue_slots_17_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_fp_ctrl_swap23 = _T_195 ? issue_slots_18_out_uop_fp_ctrl_swap23 : issue_slots_17_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_fp_ctrl_swap12 = _T_195 ? issue_slots_18_out_uop_fp_ctrl_swap12 : issue_slots_17_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_fp_ctrl_ren3 = _T_195 ? issue_slots_18_out_uop_fp_ctrl_ren3 : issue_slots_17_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_fp_ctrl_ren2 = _T_195 ? issue_slots_18_out_uop_fp_ctrl_ren2 : issue_slots_17_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_fp_ctrl_ren1 = _T_195 ? issue_slots_18_out_uop_fp_ctrl_ren1 : issue_slots_17_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_fp_ctrl_wen = _T_195 ? issue_slots_18_out_uop_fp_ctrl_wen : issue_slots_17_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_fp_ctrl_ldst = _T_195 ? issue_slots_18_out_uop_fp_ctrl_ldst : issue_slots_17_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_op2_sel = _T_195 ? issue_slots_18_out_uop_op2_sel : issue_slots_17_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_op1_sel = _T_195 ? issue_slots_18_out_uop_op1_sel : issue_slots_17_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_imm_packed = _T_195 ? issue_slots_18_out_uop_imm_packed : issue_slots_17_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_pimm = _T_195 ? issue_slots_18_out_uop_pimm : issue_slots_17_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_imm_sel = _T_195 ? issue_slots_18_out_uop_imm_sel : issue_slots_17_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_imm_rename = _T_195 ? issue_slots_18_out_uop_imm_rename : issue_slots_17_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_taken = _T_195 ? issue_slots_18_out_uop_taken : issue_slots_17_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_pc_lob = _T_195 ? issue_slots_18_out_uop_pc_lob : issue_slots_17_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_edge_inst = _T_195 ? issue_slots_18_out_uop_edge_inst : issue_slots_17_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_ftq_idx = _T_195 ? issue_slots_18_out_uop_ftq_idx : issue_slots_17_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_is_mov = _T_195 ? issue_slots_18_out_uop_is_mov : issue_slots_17_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_is_rocc = _T_195 ? issue_slots_18_out_uop_is_rocc : issue_slots_17_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_is_sys_pc2epc = _T_195 ? issue_slots_18_out_uop_is_sys_pc2epc : issue_slots_17_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_is_eret = _T_195 ? issue_slots_18_out_uop_is_eret : issue_slots_17_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_is_amo = _T_195 ? issue_slots_18_out_uop_is_amo : issue_slots_17_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_is_sfence = _T_195 ? issue_slots_18_out_uop_is_sfence : issue_slots_17_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_is_fencei = _T_195 ? issue_slots_18_out_uop_is_fencei : issue_slots_17_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_is_fence = _T_195 ? issue_slots_18_out_uop_is_fence : issue_slots_17_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_is_sfb = _T_195 ? issue_slots_18_out_uop_is_sfb : issue_slots_17_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_br_type = _T_195 ? issue_slots_18_out_uop_br_type : issue_slots_17_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_br_tag = _T_195 ? issue_slots_18_out_uop_br_tag : issue_slots_17_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_br_mask = _T_195 ? issue_slots_18_out_uop_br_mask : issue_slots_17_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_dis_col_sel = _T_195 ? issue_slots_18_out_uop_dis_col_sel : issue_slots_17_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_iw_p3_bypass_hint = _T_195 ? issue_slots_18_out_uop_iw_p3_bypass_hint : issue_slots_17_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_iw_p2_bypass_hint = _T_195 ? issue_slots_18_out_uop_iw_p2_bypass_hint : issue_slots_17_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_iw_p1_bypass_hint = _T_195 ? issue_slots_18_out_uop_iw_p1_bypass_hint : issue_slots_17_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_iw_p2_speculative_child = _T_195 ? issue_slots_18_out_uop_iw_p2_speculative_child : issue_slots_17_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_iw_p1_speculative_child = _T_195 ? issue_slots_18_out_uop_iw_p1_speculative_child : issue_slots_17_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_iw_issued = _T_195 ? issue_slots_18_out_uop_iw_issued : issue_slots_17_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_fu_code_0 = _T_195 ? issue_slots_18_out_uop_fu_code_0 : issue_slots_17_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_fu_code_1 = _T_195 ? issue_slots_18_out_uop_fu_code_1 : issue_slots_17_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_fu_code_2 = _T_195 ? issue_slots_18_out_uop_fu_code_2 : issue_slots_17_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_fu_code_3 = _T_195 ? issue_slots_18_out_uop_fu_code_3 : issue_slots_17_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_fu_code_4 = _T_195 ? issue_slots_18_out_uop_fu_code_4 : issue_slots_17_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_fu_code_5 = _T_195 ? issue_slots_18_out_uop_fu_code_5 : issue_slots_17_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_fu_code_6 = _T_195 ? issue_slots_18_out_uop_fu_code_6 : issue_slots_17_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_fu_code_7 = _T_195 ? issue_slots_18_out_uop_fu_code_7 : issue_slots_17_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_fu_code_8 = _T_195 ? issue_slots_18_out_uop_fu_code_8 : issue_slots_17_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_fu_code_9 = _T_195 ? issue_slots_18_out_uop_fu_code_9 : issue_slots_17_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_iq_type_0 = _T_195 ? issue_slots_18_out_uop_iq_type_0 : issue_slots_17_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_iq_type_1 = _T_195 ? issue_slots_18_out_uop_iq_type_1 : issue_slots_17_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_iq_type_2 = _T_195 ? issue_slots_18_out_uop_iq_type_2 : issue_slots_17_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_iq_type_3 = _T_195 ? issue_slots_18_out_uop_iq_type_3 : issue_slots_17_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_debug_pc = _T_195 ? issue_slots_18_out_uop_debug_pc : issue_slots_17_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_is_rvc = _T_195 ? issue_slots_18_out_uop_is_rvc : issue_slots_17_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_debug_inst = _T_195 ? issue_slots_18_out_uop_debug_inst : issue_slots_17_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_16_in_uop_bits_inst = _T_195 ? issue_slots_18_out_uop_inst : issue_slots_17_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign _issue_slots_16_clear_T = |shamts_oh_16; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49]
assign issue_slots_16_clear = _issue_slots_16_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49]
wire _T_197 = shamts_oh_19 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28]
assign issue_slots_17_in_uop_valid = _T_197 ? issue_slots_19_will_be_valid : shamts_oh_18 == 2'h1 & issue_slots_18_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37]
assign issue_slots_17_in_uop_bits_debug_tsrc = _T_197 ? issue_slots_19_out_uop_debug_tsrc : issue_slots_18_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_debug_fsrc = _T_197 ? issue_slots_19_out_uop_debug_fsrc : issue_slots_18_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_bp_xcpt_if = _T_197 ? issue_slots_19_out_uop_bp_xcpt_if : issue_slots_18_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_bp_debug_if = _T_197 ? issue_slots_19_out_uop_bp_debug_if : issue_slots_18_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_xcpt_ma_if = _T_197 ? issue_slots_19_out_uop_xcpt_ma_if : issue_slots_18_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_xcpt_ae_if = _T_197 ? issue_slots_19_out_uop_xcpt_ae_if : issue_slots_18_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_xcpt_pf_if = _T_197 ? issue_slots_19_out_uop_xcpt_pf_if : issue_slots_18_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_fp_typ = _T_197 ? issue_slots_19_out_uop_fp_typ : issue_slots_18_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_fp_rm = _T_197 ? issue_slots_19_out_uop_fp_rm : issue_slots_18_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_fp_val = _T_197 ? issue_slots_19_out_uop_fp_val : issue_slots_18_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_fcn_op = _T_197 ? issue_slots_19_out_uop_fcn_op : issue_slots_18_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_fcn_dw = _T_197 ? issue_slots_19_out_uop_fcn_dw : issue_slots_18_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_frs3_en = _T_197 ? issue_slots_19_out_uop_frs3_en : issue_slots_18_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_lrs2_rtype = _T_197 ? issue_slots_19_out_uop_lrs2_rtype : issue_slots_18_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_lrs1_rtype = _T_197 ? issue_slots_19_out_uop_lrs1_rtype : issue_slots_18_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_dst_rtype = _T_197 ? issue_slots_19_out_uop_dst_rtype : issue_slots_18_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_lrs3 = _T_197 ? issue_slots_19_out_uop_lrs3 : issue_slots_18_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_lrs2 = _T_197 ? issue_slots_19_out_uop_lrs2 : issue_slots_18_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_lrs1 = _T_197 ? issue_slots_19_out_uop_lrs1 : issue_slots_18_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_ldst = _T_197 ? issue_slots_19_out_uop_ldst : issue_slots_18_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_ldst_is_rs1 = _T_197 ? issue_slots_19_out_uop_ldst_is_rs1 : issue_slots_18_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_csr_cmd = _T_197 ? issue_slots_19_out_uop_csr_cmd : issue_slots_18_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_flush_on_commit = _T_197 ? issue_slots_19_out_uop_flush_on_commit : issue_slots_18_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_is_unique = _T_197 ? issue_slots_19_out_uop_is_unique : issue_slots_18_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_uses_stq = _T_197 ? issue_slots_19_out_uop_uses_stq : issue_slots_18_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_uses_ldq = _T_197 ? issue_slots_19_out_uop_uses_ldq : issue_slots_18_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_mem_signed = _T_197 ? issue_slots_19_out_uop_mem_signed : issue_slots_18_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_mem_size = _T_197 ? issue_slots_19_out_uop_mem_size : issue_slots_18_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_mem_cmd = _T_197 ? issue_slots_19_out_uop_mem_cmd : issue_slots_18_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_exc_cause = _T_197 ? issue_slots_19_out_uop_exc_cause : issue_slots_18_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_exception = _T_197 ? issue_slots_19_out_uop_exception : issue_slots_18_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_stale_pdst = _T_197 ? issue_slots_19_out_uop_stale_pdst : issue_slots_18_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_ppred_busy = _T_197 ? issue_slots_19_out_uop_ppred_busy : issue_slots_18_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_prs3_busy = _T_197 ? issue_slots_19_out_uop_prs3_busy : issue_slots_18_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_prs2_busy = _T_197 ? issue_slots_19_out_uop_prs2_busy : issue_slots_18_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_prs1_busy = _T_197 ? issue_slots_19_out_uop_prs1_busy : issue_slots_18_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_ppred = _T_197 ? issue_slots_19_out_uop_ppred : issue_slots_18_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_prs3 = _T_197 ? issue_slots_19_out_uop_prs3 : issue_slots_18_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_prs2 = _T_197 ? issue_slots_19_out_uop_prs2 : issue_slots_18_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_prs1 = _T_197 ? issue_slots_19_out_uop_prs1 : issue_slots_18_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_pdst = _T_197 ? issue_slots_19_out_uop_pdst : issue_slots_18_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_rxq_idx = _T_197 ? issue_slots_19_out_uop_rxq_idx : issue_slots_18_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_stq_idx = _T_197 ? issue_slots_19_out_uop_stq_idx : issue_slots_18_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_ldq_idx = _T_197 ? issue_slots_19_out_uop_ldq_idx : issue_slots_18_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_rob_idx = _T_197 ? issue_slots_19_out_uop_rob_idx : issue_slots_18_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_fp_ctrl_vec = _T_197 ? issue_slots_19_out_uop_fp_ctrl_vec : issue_slots_18_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_fp_ctrl_wflags = _T_197 ? issue_slots_19_out_uop_fp_ctrl_wflags : issue_slots_18_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_fp_ctrl_sqrt = _T_197 ? issue_slots_19_out_uop_fp_ctrl_sqrt : issue_slots_18_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_fp_ctrl_div = _T_197 ? issue_slots_19_out_uop_fp_ctrl_div : issue_slots_18_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_fp_ctrl_fma = _T_197 ? issue_slots_19_out_uop_fp_ctrl_fma : issue_slots_18_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_fp_ctrl_fastpipe = _T_197 ? issue_slots_19_out_uop_fp_ctrl_fastpipe : issue_slots_18_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_fp_ctrl_toint = _T_197 ? issue_slots_19_out_uop_fp_ctrl_toint : issue_slots_18_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_fp_ctrl_fromint = _T_197 ? issue_slots_19_out_uop_fp_ctrl_fromint : issue_slots_18_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_fp_ctrl_typeTagOut = _T_197 ? issue_slots_19_out_uop_fp_ctrl_typeTagOut : issue_slots_18_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_fp_ctrl_typeTagIn = _T_197 ? issue_slots_19_out_uop_fp_ctrl_typeTagIn : issue_slots_18_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_fp_ctrl_swap23 = _T_197 ? issue_slots_19_out_uop_fp_ctrl_swap23 : issue_slots_18_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_fp_ctrl_swap12 = _T_197 ? issue_slots_19_out_uop_fp_ctrl_swap12 : issue_slots_18_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_fp_ctrl_ren3 = _T_197 ? issue_slots_19_out_uop_fp_ctrl_ren3 : issue_slots_18_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_fp_ctrl_ren2 = _T_197 ? issue_slots_19_out_uop_fp_ctrl_ren2 : issue_slots_18_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_fp_ctrl_ren1 = _T_197 ? issue_slots_19_out_uop_fp_ctrl_ren1 : issue_slots_18_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_fp_ctrl_wen = _T_197 ? issue_slots_19_out_uop_fp_ctrl_wen : issue_slots_18_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_fp_ctrl_ldst = _T_197 ? issue_slots_19_out_uop_fp_ctrl_ldst : issue_slots_18_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_op2_sel = _T_197 ? issue_slots_19_out_uop_op2_sel : issue_slots_18_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_op1_sel = _T_197 ? issue_slots_19_out_uop_op1_sel : issue_slots_18_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_imm_packed = _T_197 ? issue_slots_19_out_uop_imm_packed : issue_slots_18_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_pimm = _T_197 ? issue_slots_19_out_uop_pimm : issue_slots_18_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_imm_sel = _T_197 ? issue_slots_19_out_uop_imm_sel : issue_slots_18_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_imm_rename = _T_197 ? issue_slots_19_out_uop_imm_rename : issue_slots_18_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_taken = _T_197 ? issue_slots_19_out_uop_taken : issue_slots_18_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_pc_lob = _T_197 ? issue_slots_19_out_uop_pc_lob : issue_slots_18_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_edge_inst = _T_197 ? issue_slots_19_out_uop_edge_inst : issue_slots_18_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_ftq_idx = _T_197 ? issue_slots_19_out_uop_ftq_idx : issue_slots_18_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_is_mov = _T_197 ? issue_slots_19_out_uop_is_mov : issue_slots_18_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_is_rocc = _T_197 ? issue_slots_19_out_uop_is_rocc : issue_slots_18_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_is_sys_pc2epc = _T_197 ? issue_slots_19_out_uop_is_sys_pc2epc : issue_slots_18_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_is_eret = _T_197 ? issue_slots_19_out_uop_is_eret : issue_slots_18_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_is_amo = _T_197 ? issue_slots_19_out_uop_is_amo : issue_slots_18_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_is_sfence = _T_197 ? issue_slots_19_out_uop_is_sfence : issue_slots_18_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_is_fencei = _T_197 ? issue_slots_19_out_uop_is_fencei : issue_slots_18_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_is_fence = _T_197 ? issue_slots_19_out_uop_is_fence : issue_slots_18_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_is_sfb = _T_197 ? issue_slots_19_out_uop_is_sfb : issue_slots_18_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_br_type = _T_197 ? issue_slots_19_out_uop_br_type : issue_slots_18_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_br_tag = _T_197 ? issue_slots_19_out_uop_br_tag : issue_slots_18_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_br_mask = _T_197 ? issue_slots_19_out_uop_br_mask : issue_slots_18_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_dis_col_sel = _T_197 ? issue_slots_19_out_uop_dis_col_sel : issue_slots_18_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_iw_p3_bypass_hint = _T_197 ? issue_slots_19_out_uop_iw_p3_bypass_hint : issue_slots_18_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_iw_p2_bypass_hint = _T_197 ? issue_slots_19_out_uop_iw_p2_bypass_hint : issue_slots_18_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_iw_p1_bypass_hint = _T_197 ? issue_slots_19_out_uop_iw_p1_bypass_hint : issue_slots_18_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_iw_p2_speculative_child = _T_197 ? issue_slots_19_out_uop_iw_p2_speculative_child : issue_slots_18_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_iw_p1_speculative_child = _T_197 ? issue_slots_19_out_uop_iw_p1_speculative_child : issue_slots_18_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_iw_issued = _T_197 ? issue_slots_19_out_uop_iw_issued : issue_slots_18_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_fu_code_0 = _T_197 ? issue_slots_19_out_uop_fu_code_0 : issue_slots_18_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_fu_code_1 = _T_197 ? issue_slots_19_out_uop_fu_code_1 : issue_slots_18_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_fu_code_2 = _T_197 ? issue_slots_19_out_uop_fu_code_2 : issue_slots_18_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_fu_code_3 = _T_197 ? issue_slots_19_out_uop_fu_code_3 : issue_slots_18_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_fu_code_4 = _T_197 ? issue_slots_19_out_uop_fu_code_4 : issue_slots_18_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_fu_code_5 = _T_197 ? issue_slots_19_out_uop_fu_code_5 : issue_slots_18_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_fu_code_6 = _T_197 ? issue_slots_19_out_uop_fu_code_6 : issue_slots_18_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_fu_code_7 = _T_197 ? issue_slots_19_out_uop_fu_code_7 : issue_slots_18_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_fu_code_8 = _T_197 ? issue_slots_19_out_uop_fu_code_8 : issue_slots_18_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_fu_code_9 = _T_197 ? issue_slots_19_out_uop_fu_code_9 : issue_slots_18_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_iq_type_0 = _T_197 ? issue_slots_19_out_uop_iq_type_0 : issue_slots_18_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_iq_type_1 = _T_197 ? issue_slots_19_out_uop_iq_type_1 : issue_slots_18_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_iq_type_2 = _T_197 ? issue_slots_19_out_uop_iq_type_2 : issue_slots_18_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_iq_type_3 = _T_197 ? issue_slots_19_out_uop_iq_type_3 : issue_slots_18_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_debug_pc = _T_197 ? issue_slots_19_out_uop_debug_pc : issue_slots_18_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_is_rvc = _T_197 ? issue_slots_19_out_uop_is_rvc : issue_slots_18_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_debug_inst = _T_197 ? issue_slots_19_out_uop_debug_inst : issue_slots_18_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_17_in_uop_bits_inst = _T_197 ? issue_slots_19_out_uop_inst : issue_slots_18_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign _issue_slots_17_clear_T = |shamts_oh_17; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49]
assign issue_slots_17_clear = _issue_slots_17_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49]
wire _T_199 = shamts_oh_20 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28]
assign issue_slots_18_in_uop_valid = _T_199 ? will_be_valid_20 : shamts_oh_19 == 2'h1 & issue_slots_19_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :186:79, :191:33, :194:{28,48}, :195:37]
assign issue_slots_18_in_uop_bits_debug_tsrc = _T_199 ? io_dis_uops_0_bits_debug_tsrc_0 : issue_slots_19_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_debug_fsrc = _T_199 ? io_dis_uops_0_bits_debug_fsrc_0 : issue_slots_19_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_bp_xcpt_if = _T_199 ? io_dis_uops_0_bits_bp_xcpt_if_0 : issue_slots_19_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_bp_debug_if = _T_199 ? io_dis_uops_0_bits_bp_debug_if_0 : issue_slots_19_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_xcpt_ma_if = _T_199 ? io_dis_uops_0_bits_xcpt_ma_if_0 : issue_slots_19_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_xcpt_ae_if = _T_199 ? io_dis_uops_0_bits_xcpt_ae_if_0 : issue_slots_19_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_xcpt_pf_if = _T_199 ? io_dis_uops_0_bits_xcpt_pf_if_0 : issue_slots_19_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_fp_typ = _T_199 ? io_dis_uops_0_bits_fp_typ_0 : issue_slots_19_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_fp_rm = _T_199 ? io_dis_uops_0_bits_fp_rm_0 : issue_slots_19_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_fp_val = _T_199 ? io_dis_uops_0_bits_fp_val_0 : issue_slots_19_out_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_fcn_op = _T_199 ? io_dis_uops_0_bits_fcn_op_0 : issue_slots_19_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_fcn_dw = _T_199 ? io_dis_uops_0_bits_fcn_dw_0 : issue_slots_19_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_frs3_en = _T_199 ? io_dis_uops_0_bits_frs3_en_0 : issue_slots_19_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_lrs2_rtype = _T_199 ? io_dis_uops_0_bits_lrs2_rtype_0 : issue_slots_19_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_lrs1_rtype = _T_199 ? io_dis_uops_0_bits_lrs1_rtype_0 : issue_slots_19_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_dst_rtype = _T_199 ? io_dis_uops_0_bits_dst_rtype_0 : issue_slots_19_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_lrs3 = _T_199 ? io_dis_uops_0_bits_lrs3_0 : issue_slots_19_out_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_lrs2 = _T_199 ? io_dis_uops_0_bits_lrs2_0 : issue_slots_19_out_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_lrs1 = _T_199 ? io_dis_uops_0_bits_lrs1_0 : issue_slots_19_out_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_ldst = _T_199 ? io_dis_uops_0_bits_ldst_0 : issue_slots_19_out_uop_ldst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_ldst_is_rs1 = _T_199 ? io_dis_uops_0_bits_ldst_is_rs1_0 : issue_slots_19_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_csr_cmd = _T_199 ? io_dis_uops_0_bits_csr_cmd_0 : issue_slots_19_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_flush_on_commit = _T_199 ? io_dis_uops_0_bits_flush_on_commit_0 : issue_slots_19_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_is_unique = _T_199 ? io_dis_uops_0_bits_is_unique_0 : issue_slots_19_out_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_uses_stq = _T_199 ? io_dis_uops_0_bits_uses_stq_0 : issue_slots_19_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_uses_ldq = _T_199 ? io_dis_uops_0_bits_uses_ldq_0 : issue_slots_19_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_mem_signed = _T_199 ? io_dis_uops_0_bits_mem_signed_0 : issue_slots_19_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_mem_size = _T_199 ? io_dis_uops_0_bits_mem_size_0 : issue_slots_19_out_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_mem_cmd = _T_199 ? io_dis_uops_0_bits_mem_cmd_0 : issue_slots_19_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_exc_cause = _T_199 ? io_dis_uops_0_bits_exc_cause_0 : issue_slots_19_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_exception = _T_199 ? io_dis_uops_0_bits_exception_0 : issue_slots_19_out_uop_exception; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_stale_pdst = _T_199 ? io_dis_uops_0_bits_stale_pdst_0 : issue_slots_19_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_ppred_busy = _T_199 ? _WIRE_ppred_busy : issue_slots_19_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:35:17, :80:96, :81:30, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_prs3_busy = _T_199 ? _WIRE_prs3_busy : issue_slots_19_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:35:17, :76:38, :77:29, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_prs2_busy = _T_199 ? _WIRE_prs2_busy : issue_slots_19_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:65:38, :71:116, :72:29, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_prs1_busy = _T_199 ? _WIRE_prs1_busy : issue_slots_19_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:57:38, :62:116, :63:29, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_ppred = _T_199 ? io_dis_uops_0_bits_ppred_0 : issue_slots_19_out_uop_ppred; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_prs3 = _T_199 ? io_dis_uops_0_bits_prs3_0 : issue_slots_19_out_uop_prs3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_prs2 = _T_199 ? io_dis_uops_0_bits_prs2_0 : issue_slots_19_out_uop_prs2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_prs1 = _T_199 ? io_dis_uops_0_bits_prs1_0 : issue_slots_19_out_uop_prs1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_pdst = _T_199 ? io_dis_uops_0_bits_pdst_0 : issue_slots_19_out_uop_pdst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_rxq_idx = _T_199 ? io_dis_uops_0_bits_rxq_idx_0 : issue_slots_19_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_stq_idx = _T_199 ? io_dis_uops_0_bits_stq_idx_0 : issue_slots_19_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_ldq_idx = _T_199 ? io_dis_uops_0_bits_ldq_idx_0 : issue_slots_19_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_rob_idx = _T_199 ? io_dis_uops_0_bits_rob_idx_0 : issue_slots_19_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_fp_ctrl_vec = _T_199 ? io_dis_uops_0_bits_fp_ctrl_vec_0 : issue_slots_19_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_fp_ctrl_wflags = _T_199 ? io_dis_uops_0_bits_fp_ctrl_wflags_0 : issue_slots_19_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_fp_ctrl_sqrt = _T_199 ? io_dis_uops_0_bits_fp_ctrl_sqrt_0 : issue_slots_19_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_fp_ctrl_div = _T_199 ? io_dis_uops_0_bits_fp_ctrl_div_0 : issue_slots_19_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_fp_ctrl_fma = _T_199 ? io_dis_uops_0_bits_fp_ctrl_fma_0 : issue_slots_19_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_fp_ctrl_fastpipe = _T_199 ? io_dis_uops_0_bits_fp_ctrl_fastpipe_0 : issue_slots_19_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_fp_ctrl_toint = _T_199 ? io_dis_uops_0_bits_fp_ctrl_toint_0 : issue_slots_19_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_fp_ctrl_fromint = _T_199 ? io_dis_uops_0_bits_fp_ctrl_fromint_0 : issue_slots_19_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_fp_ctrl_typeTagOut = _T_199 ? io_dis_uops_0_bits_fp_ctrl_typeTagOut_0 : issue_slots_19_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_fp_ctrl_typeTagIn = _T_199 ? io_dis_uops_0_bits_fp_ctrl_typeTagIn_0 : issue_slots_19_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_fp_ctrl_swap23 = _T_199 ? io_dis_uops_0_bits_fp_ctrl_swap23_0 : issue_slots_19_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_fp_ctrl_swap12 = _T_199 ? io_dis_uops_0_bits_fp_ctrl_swap12_0 : issue_slots_19_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_fp_ctrl_ren3 = _T_199 ? io_dis_uops_0_bits_fp_ctrl_ren3_0 : issue_slots_19_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_fp_ctrl_ren2 = _T_199 ? io_dis_uops_0_bits_fp_ctrl_ren2_0 : issue_slots_19_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_fp_ctrl_ren1 = _T_199 ? io_dis_uops_0_bits_fp_ctrl_ren1_0 : issue_slots_19_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_fp_ctrl_wen = _T_199 ? io_dis_uops_0_bits_fp_ctrl_wen_0 : issue_slots_19_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_fp_ctrl_ldst = _T_199 ? io_dis_uops_0_bits_fp_ctrl_ldst_0 : issue_slots_19_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_op2_sel = _T_199 ? io_dis_uops_0_bits_op2_sel_0 : issue_slots_19_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_op1_sel = _T_199 ? io_dis_uops_0_bits_op1_sel_0 : issue_slots_19_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_imm_packed = _T_199 ? io_dis_uops_0_bits_imm_packed_0 : issue_slots_19_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_pimm = _T_199 ? io_dis_uops_0_bits_pimm_0 : issue_slots_19_out_uop_pimm; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_imm_sel = _T_199 ? io_dis_uops_0_bits_imm_sel_0 : issue_slots_19_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_imm_rename = _T_199 ? io_dis_uops_0_bits_imm_rename_0 : issue_slots_19_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_taken = _T_199 ? io_dis_uops_0_bits_taken_0 : issue_slots_19_out_uop_taken; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_pc_lob = _T_199 ? io_dis_uops_0_bits_pc_lob_0 : issue_slots_19_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_edge_inst = _T_199 ? io_dis_uops_0_bits_edge_inst_0 : issue_slots_19_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_ftq_idx = _T_199 ? io_dis_uops_0_bits_ftq_idx_0 : issue_slots_19_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_is_mov = _T_199 ? io_dis_uops_0_bits_is_mov_0 : issue_slots_19_out_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_is_rocc = _T_199 ? io_dis_uops_0_bits_is_rocc_0 : issue_slots_19_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_is_sys_pc2epc = _T_199 ? io_dis_uops_0_bits_is_sys_pc2epc_0 : issue_slots_19_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_is_eret = _T_199 ? io_dis_uops_0_bits_is_eret_0 : issue_slots_19_out_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_is_amo = _T_199 ? io_dis_uops_0_bits_is_amo_0 : issue_slots_19_out_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_is_sfence = _T_199 ? io_dis_uops_0_bits_is_sfence_0 : issue_slots_19_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_is_fencei = _T_199 ? io_dis_uops_0_bits_is_fencei_0 : issue_slots_19_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_is_fence = _T_199 ? io_dis_uops_0_bits_is_fence_0 : issue_slots_19_out_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_is_sfb = _T_199 ? io_dis_uops_0_bits_is_sfb_0 : issue_slots_19_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_br_type = _T_199 ? io_dis_uops_0_bits_br_type_0 : issue_slots_19_out_uop_br_type; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_br_tag = _T_199 ? io_dis_uops_0_bits_br_tag_0 : issue_slots_19_out_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_br_mask = _T_199 ? io_dis_uops_0_bits_br_mask_0 : issue_slots_19_out_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_dis_col_sel = _T_199 ? io_dis_uops_0_bits_dis_col_sel_0 : issue_slots_19_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_iw_p3_bypass_hint = _T_199 ? _WIRE_iw_p3_bypass_hint : issue_slots_19_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:41:35, :76:38, :78:37, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_iw_p2_bypass_hint = _T_199 ? _WIRE_iw_p2_bypass_hint : issue_slots_19_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:40:35, :65:38, :68:37, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_iw_p1_bypass_hint = _T_199 ? _WIRE_iw_p1_bypass_hint : issue_slots_19_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:39:35, :57:38, :60:37, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_iw_p2_speculative_child = _T_199 ? _WIRE_iw_p2_speculative_child : issue_slots_19_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:35:17, :65:38, :67:43, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_iw_p1_speculative_child = _T_199 ? _WIRE_iw_p1_speculative_child : issue_slots_19_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:35:17, :57:38, :59:43, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_iw_issued = ~_T_199 & issue_slots_19_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_fu_code_0 = _T_199 ? io_dis_uops_0_bits_fu_code_0_0 : issue_slots_19_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_fu_code_1 = _T_199 ? io_dis_uops_0_bits_fu_code_1_0 : issue_slots_19_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_fu_code_2 = _T_199 ? io_dis_uops_0_bits_fu_code_2_0 : issue_slots_19_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_fu_code_3 = _T_199 ? io_dis_uops_0_bits_fu_code_3_0 : issue_slots_19_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_fu_code_4 = _T_199 ? io_dis_uops_0_bits_fu_code_4_0 : issue_slots_19_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_fu_code_5 = _T_199 ? io_dis_uops_0_bits_fu_code_5_0 : issue_slots_19_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_fu_code_6 = _T_199 ? io_dis_uops_0_bits_fu_code_6_0 : issue_slots_19_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_fu_code_7 = _T_199 ? io_dis_uops_0_bits_fu_code_7_0 : issue_slots_19_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_fu_code_8 = _T_199 ? io_dis_uops_0_bits_fu_code_8_0 : issue_slots_19_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_fu_code_9 = _T_199 ? io_dis_uops_0_bits_fu_code_9_0 : issue_slots_19_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_iq_type_0 = _T_199 ? io_dis_uops_0_bits_iq_type_0_0 : issue_slots_19_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_iq_type_1 = _T_199 ? io_dis_uops_0_bits_iq_type_1_0 : issue_slots_19_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_iq_type_2 = _T_199 ? io_dis_uops_0_bits_iq_type_2_0 : issue_slots_19_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_iq_type_3 = _T_199 ? io_dis_uops_0_bits_iq_type_3_0 : issue_slots_19_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_debug_pc = _T_199 ? io_dis_uops_0_bits_debug_pc_0 : issue_slots_19_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_is_rvc = _T_199 ? io_dis_uops_0_bits_is_rvc_0 : issue_slots_19_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_debug_inst = _T_199 ? io_dis_uops_0_bits_debug_inst_0 : issue_slots_19_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_18_in_uop_bits_inst = _T_199 ? io_dis_uops_0_bits_inst_0 : issue_slots_19_out_uop_inst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign _issue_slots_18_clear_T = |shamts_oh_18; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49]
assign issue_slots_18_clear = _issue_slots_18_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49]
wire _T_201 = shamts_oh_21 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28]
assign issue_slots_19_in_uop_valid = _T_201 ? will_be_valid_21 : shamts_oh_20 == 2'h1 & will_be_valid_20; // @[issue-unit-age-ordered.scala:122:28, :158:23, :186:79, :191:33, :194:{28,48}, :195:37]
assign issue_slots_19_in_uop_bits_debug_tsrc = _T_201 ? io_dis_uops_1_bits_debug_tsrc_0 : io_dis_uops_0_bits_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_debug_fsrc = _T_201 ? io_dis_uops_1_bits_debug_fsrc_0 : io_dis_uops_0_bits_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_bp_xcpt_if = _T_201 ? io_dis_uops_1_bits_bp_xcpt_if_0 : io_dis_uops_0_bits_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_bp_debug_if = _T_201 ? io_dis_uops_1_bits_bp_debug_if_0 : io_dis_uops_0_bits_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_xcpt_ma_if = _T_201 ? io_dis_uops_1_bits_xcpt_ma_if_0 : io_dis_uops_0_bits_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_xcpt_ae_if = _T_201 ? io_dis_uops_1_bits_xcpt_ae_if_0 : io_dis_uops_0_bits_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_xcpt_pf_if = _T_201 ? io_dis_uops_1_bits_xcpt_pf_if_0 : io_dis_uops_0_bits_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_fp_typ = _T_201 ? io_dis_uops_1_bits_fp_typ_0 : io_dis_uops_0_bits_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_fp_rm = _T_201 ? io_dis_uops_1_bits_fp_rm_0 : io_dis_uops_0_bits_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_fp_val = _T_201 ? io_dis_uops_1_bits_fp_val_0 : io_dis_uops_0_bits_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_fcn_op = _T_201 ? io_dis_uops_1_bits_fcn_op_0 : io_dis_uops_0_bits_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_fcn_dw = _T_201 ? io_dis_uops_1_bits_fcn_dw_0 : io_dis_uops_0_bits_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_frs3_en = _T_201 ? io_dis_uops_1_bits_frs3_en_0 : io_dis_uops_0_bits_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_lrs2_rtype = _T_201 ? io_dis_uops_1_bits_lrs2_rtype_0 : io_dis_uops_0_bits_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_lrs1_rtype = _T_201 ? io_dis_uops_1_bits_lrs1_rtype_0 : io_dis_uops_0_bits_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_dst_rtype = _T_201 ? io_dis_uops_1_bits_dst_rtype_0 : io_dis_uops_0_bits_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_lrs3 = _T_201 ? io_dis_uops_1_bits_lrs3_0 : io_dis_uops_0_bits_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_lrs2 = _T_201 ? io_dis_uops_1_bits_lrs2_0 : io_dis_uops_0_bits_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_lrs1 = _T_201 ? io_dis_uops_1_bits_lrs1_0 : io_dis_uops_0_bits_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_ldst = _T_201 ? io_dis_uops_1_bits_ldst_0 : io_dis_uops_0_bits_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_ldst_is_rs1 = _T_201 ? io_dis_uops_1_bits_ldst_is_rs1_0 : io_dis_uops_0_bits_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_csr_cmd = _T_201 ? io_dis_uops_1_bits_csr_cmd_0 : io_dis_uops_0_bits_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_flush_on_commit = _T_201 ? io_dis_uops_1_bits_flush_on_commit_0 : io_dis_uops_0_bits_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_is_unique = _T_201 ? io_dis_uops_1_bits_is_unique_0 : io_dis_uops_0_bits_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_uses_stq = _T_201 ? io_dis_uops_1_bits_uses_stq_0 : io_dis_uops_0_bits_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_uses_ldq = _T_201 ? io_dis_uops_1_bits_uses_ldq_0 : io_dis_uops_0_bits_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_mem_signed = _T_201 ? io_dis_uops_1_bits_mem_signed_0 : io_dis_uops_0_bits_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_mem_size = _T_201 ? io_dis_uops_1_bits_mem_size_0 : io_dis_uops_0_bits_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_mem_cmd = _T_201 ? io_dis_uops_1_bits_mem_cmd_0 : io_dis_uops_0_bits_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_exc_cause = _T_201 ? io_dis_uops_1_bits_exc_cause_0 : io_dis_uops_0_bits_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_exception = _T_201 ? io_dis_uops_1_bits_exception_0 : io_dis_uops_0_bits_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_stale_pdst = _T_201 ? io_dis_uops_1_bits_stale_pdst_0 : io_dis_uops_0_bits_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_ppred_busy = _T_201 ? ~(io_pred_wakeup_port_valid_0 & io_pred_wakeup_port_bits_0 == io_dis_uops_1_bits_ppred_0) & io_dis_uops_1_bits_ppred_busy_0 : _WIRE_ppred_busy; // @[issue-unit-age-ordered.scala:22:7, :35:17, :80:{37,65,96}, :81:30, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_prs3_busy = _T_201 ? ~_T_110 & io_dis_uops_1_bits_prs3_busy_0 : _WIRE_prs3_busy; // @[issue-unit-age-ordered.scala:22:7, :35:17, :76:{32,38}, :77:29, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_prs2_busy = _T_201 ? ((|{prs2_rebusys_0_1, io_child_rebusys_0 & io_dis_uops_1_bits_iw_p2_speculative_child_0}) ? io_dis_uops_1_bits_lrs2_rtype_0 == 2'h0 : ~_T_86 & io_dis_uops_1_bits_prs2_busy_0) : _WIRE_prs2_busy; // @[issue-unit-age-ordered.scala:22:7, :35:17, :51:95, :65:{32,38}, :66:29, :71:{37,59,106,116}, :72:{29,63}, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_prs1_busy = _T_201 ? ((|{prs1_rebusys_0_1, io_child_rebusys_0 & io_dis_uops_1_bits_iw_p1_speculative_child_0}) ? io_dis_uops_1_bits_lrs1_rtype_0 == 2'h0 : ~_T_62 & io_dis_uops_1_bits_prs1_busy_0) : _WIRE_prs1_busy; // @[issue-unit-age-ordered.scala:22:7, :35:17, :50:95, :57:{32,38}, :58:29, :62:{37,59,106,116}, :63:{29,63}, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_ppred = _T_201 ? io_dis_uops_1_bits_ppred_0 : io_dis_uops_0_bits_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_prs3 = _T_201 ? io_dis_uops_1_bits_prs3_0 : io_dis_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_prs2 = _T_201 ? io_dis_uops_1_bits_prs2_0 : io_dis_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_prs1 = _T_201 ? io_dis_uops_1_bits_prs1_0 : io_dis_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_pdst = _T_201 ? io_dis_uops_1_bits_pdst_0 : io_dis_uops_0_bits_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_rxq_idx = _T_201 ? io_dis_uops_1_bits_rxq_idx_0 : io_dis_uops_0_bits_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_stq_idx = _T_201 ? io_dis_uops_1_bits_stq_idx_0 : io_dis_uops_0_bits_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_ldq_idx = _T_201 ? io_dis_uops_1_bits_ldq_idx_0 : io_dis_uops_0_bits_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_rob_idx = _T_201 ? io_dis_uops_1_bits_rob_idx_0 : io_dis_uops_0_bits_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_fp_ctrl_vec = _T_201 ? io_dis_uops_1_bits_fp_ctrl_vec_0 : io_dis_uops_0_bits_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_fp_ctrl_wflags = _T_201 ? io_dis_uops_1_bits_fp_ctrl_wflags_0 : io_dis_uops_0_bits_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_fp_ctrl_sqrt = _T_201 ? io_dis_uops_1_bits_fp_ctrl_sqrt_0 : io_dis_uops_0_bits_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_fp_ctrl_div = _T_201 ? io_dis_uops_1_bits_fp_ctrl_div_0 : io_dis_uops_0_bits_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_fp_ctrl_fma = _T_201 ? io_dis_uops_1_bits_fp_ctrl_fma_0 : io_dis_uops_0_bits_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_fp_ctrl_fastpipe = _T_201 ? io_dis_uops_1_bits_fp_ctrl_fastpipe_0 : io_dis_uops_0_bits_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_fp_ctrl_toint = _T_201 ? io_dis_uops_1_bits_fp_ctrl_toint_0 : io_dis_uops_0_bits_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_fp_ctrl_fromint = _T_201 ? io_dis_uops_1_bits_fp_ctrl_fromint_0 : io_dis_uops_0_bits_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_fp_ctrl_typeTagOut = _T_201 ? io_dis_uops_1_bits_fp_ctrl_typeTagOut_0 : io_dis_uops_0_bits_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_fp_ctrl_typeTagIn = _T_201 ? io_dis_uops_1_bits_fp_ctrl_typeTagIn_0 : io_dis_uops_0_bits_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_fp_ctrl_swap23 = _T_201 ? io_dis_uops_1_bits_fp_ctrl_swap23_0 : io_dis_uops_0_bits_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_fp_ctrl_swap12 = _T_201 ? io_dis_uops_1_bits_fp_ctrl_swap12_0 : io_dis_uops_0_bits_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_fp_ctrl_ren3 = _T_201 ? io_dis_uops_1_bits_fp_ctrl_ren3_0 : io_dis_uops_0_bits_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_fp_ctrl_ren2 = _T_201 ? io_dis_uops_1_bits_fp_ctrl_ren2_0 : io_dis_uops_0_bits_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_fp_ctrl_ren1 = _T_201 ? io_dis_uops_1_bits_fp_ctrl_ren1_0 : io_dis_uops_0_bits_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_fp_ctrl_wen = _T_201 ? io_dis_uops_1_bits_fp_ctrl_wen_0 : io_dis_uops_0_bits_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_fp_ctrl_ldst = _T_201 ? io_dis_uops_1_bits_fp_ctrl_ldst_0 : io_dis_uops_0_bits_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_op2_sel = _T_201 ? io_dis_uops_1_bits_op2_sel_0 : io_dis_uops_0_bits_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_op1_sel = _T_201 ? io_dis_uops_1_bits_op1_sel_0 : io_dis_uops_0_bits_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_imm_packed = _T_201 ? io_dis_uops_1_bits_imm_packed_0 : io_dis_uops_0_bits_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_pimm = _T_201 ? io_dis_uops_1_bits_pimm_0 : io_dis_uops_0_bits_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_imm_sel = _T_201 ? io_dis_uops_1_bits_imm_sel_0 : io_dis_uops_0_bits_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_imm_rename = _T_201 ? io_dis_uops_1_bits_imm_rename_0 : io_dis_uops_0_bits_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_taken = _T_201 ? io_dis_uops_1_bits_taken_0 : io_dis_uops_0_bits_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_pc_lob = _T_201 ? io_dis_uops_1_bits_pc_lob_0 : io_dis_uops_0_bits_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_edge_inst = _T_201 ? io_dis_uops_1_bits_edge_inst_0 : io_dis_uops_0_bits_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_ftq_idx = _T_201 ? io_dis_uops_1_bits_ftq_idx_0 : io_dis_uops_0_bits_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_is_mov = _T_201 ? io_dis_uops_1_bits_is_mov_0 : io_dis_uops_0_bits_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_is_rocc = _T_201 ? io_dis_uops_1_bits_is_rocc_0 : io_dis_uops_0_bits_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_is_sys_pc2epc = _T_201 ? io_dis_uops_1_bits_is_sys_pc2epc_0 : io_dis_uops_0_bits_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_is_eret = _T_201 ? io_dis_uops_1_bits_is_eret_0 : io_dis_uops_0_bits_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_is_amo = _T_201 ? io_dis_uops_1_bits_is_amo_0 : io_dis_uops_0_bits_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_is_sfence = _T_201 ? io_dis_uops_1_bits_is_sfence_0 : io_dis_uops_0_bits_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_is_fencei = _T_201 ? io_dis_uops_1_bits_is_fencei_0 : io_dis_uops_0_bits_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_is_fence = _T_201 ? io_dis_uops_1_bits_is_fence_0 : io_dis_uops_0_bits_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_is_sfb = _T_201 ? io_dis_uops_1_bits_is_sfb_0 : io_dis_uops_0_bits_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_br_type = _T_201 ? io_dis_uops_1_bits_br_type_0 : io_dis_uops_0_bits_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_br_tag = _T_201 ? io_dis_uops_1_bits_br_tag_0 : io_dis_uops_0_bits_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_br_mask = _T_201 ? io_dis_uops_1_bits_br_mask_0 : io_dis_uops_0_bits_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_dis_col_sel = _T_201 ? io_dis_uops_1_bits_dis_col_sel_0 : io_dis_uops_0_bits_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_iw_p3_bypass_hint = _T_201 ? _T_110 & (prs3_wakeups_0_1 & io_wakeup_ports_0_bits_bypassable_0 | prs3_wakeups_2_1 | prs3_wakeups_3_1) : _WIRE_iw_p3_bypass_hint; // @[Mux.scala:30:73]
assign issue_slots_19_in_uop_bits_iw_p2_bypass_hint = _T_201 ? _T_86 & (prs2_wakeups_0_1 & io_wakeup_ports_0_bits_bypassable_0 | prs2_wakeups_2_1 | prs2_wakeups_3_1) : _WIRE_iw_p2_bypass_hint; // @[Mux.scala:30:73]
assign issue_slots_19_in_uop_bits_iw_p1_bypass_hint = _T_201 ? _T_62 & (prs1_wakeups_0_1 & io_wakeup_ports_0_bits_bypassable_0 | prs1_wakeups_2_1 | prs1_wakeups_3_1) : _WIRE_iw_p1_bypass_hint; // @[Mux.scala:30:73]
assign issue_slots_19_in_uop_bits_iw_p2_speculative_child = _T_201 ? (_T_86 ? (prs2_wakeups_0_1 ? io_wakeup_ports_0_bits_speculative_mask_0 : 2'h0) | {prs2_wakeups_3_1, prs2_wakeups_2_1} : io_dis_uops_1_bits_iw_p2_speculative_child_0) : _WIRE_iw_p2_speculative_child; // @[Mux.scala:30:73]
assign issue_slots_19_in_uop_bits_iw_p1_speculative_child = _T_201 ? (_T_62 ? (prs1_wakeups_0_1 ? io_wakeup_ports_0_bits_speculative_mask_0 : 2'h0) | {prs1_wakeups_3_1, prs1_wakeups_2_1} : io_dis_uops_1_bits_iw_p1_speculative_child_0) : _WIRE_iw_p1_speculative_child; // @[Mux.scala:30:73]
assign issue_slots_19_in_uop_bits_fu_code_0 = _T_201 ? io_dis_uops_1_bits_fu_code_0_0 : io_dis_uops_0_bits_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_fu_code_1 = _T_201 ? io_dis_uops_1_bits_fu_code_1_0 : io_dis_uops_0_bits_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_fu_code_2 = _T_201 ? io_dis_uops_1_bits_fu_code_2_0 : io_dis_uops_0_bits_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_fu_code_3 = _T_201 ? io_dis_uops_1_bits_fu_code_3_0 : io_dis_uops_0_bits_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_fu_code_4 = _T_201 ? io_dis_uops_1_bits_fu_code_4_0 : io_dis_uops_0_bits_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_fu_code_5 = _T_201 ? io_dis_uops_1_bits_fu_code_5_0 : io_dis_uops_0_bits_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_fu_code_6 = _T_201 ? io_dis_uops_1_bits_fu_code_6_0 : io_dis_uops_0_bits_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_fu_code_7 = _T_201 ? io_dis_uops_1_bits_fu_code_7_0 : io_dis_uops_0_bits_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_fu_code_8 = _T_201 ? io_dis_uops_1_bits_fu_code_8_0 : io_dis_uops_0_bits_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_fu_code_9 = _T_201 ? io_dis_uops_1_bits_fu_code_9_0 : io_dis_uops_0_bits_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_iq_type_0 = _T_201 ? io_dis_uops_1_bits_iq_type_0_0 : io_dis_uops_0_bits_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_iq_type_1 = _T_201 ? io_dis_uops_1_bits_iq_type_1_0 : io_dis_uops_0_bits_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_iq_type_2 = _T_201 ? io_dis_uops_1_bits_iq_type_2_0 : io_dis_uops_0_bits_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_iq_type_3 = _T_201 ? io_dis_uops_1_bits_iq_type_3_0 : io_dis_uops_0_bits_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_debug_pc = _T_201 ? io_dis_uops_1_bits_debug_pc_0 : io_dis_uops_0_bits_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_is_rvc = _T_201 ? io_dis_uops_1_bits_is_rvc_0 : io_dis_uops_0_bits_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_debug_inst = _T_201 ? io_dis_uops_1_bits_debug_inst_0 : io_dis_uops_0_bits_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign issue_slots_19_in_uop_bits_inst = _T_201 ? io_dis_uops_1_bits_inst_0 : io_dis_uops_0_bits_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37]
assign _issue_slots_19_clear_T = |shamts_oh_19; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49]
assign issue_slots_19_clear = _issue_slots_19_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49]
reg is_available_0; // @[issue-unit-age-ordered.scala:208:25]
reg is_available_1; // @[issue-unit-age-ordered.scala:208:25]
reg is_available_2; // @[issue-unit-age-ordered.scala:208:25]
reg is_available_3; // @[issue-unit-age-ordered.scala:208:25]
reg is_available_4; // @[issue-unit-age-ordered.scala:208:25]
reg is_available_5; // @[issue-unit-age-ordered.scala:208:25]
reg is_available_6; // @[issue-unit-age-ordered.scala:208:25]
reg is_available_7; // @[issue-unit-age-ordered.scala:208:25]
reg is_available_8; // @[issue-unit-age-ordered.scala:208:25]
reg is_available_9; // @[issue-unit-age-ordered.scala:208:25]
reg is_available_10; // @[issue-unit-age-ordered.scala:208:25]
reg is_available_11; // @[issue-unit-age-ordered.scala:208:25]
reg is_available_12; // @[issue-unit-age-ordered.scala:208:25]
reg is_available_13; // @[issue-unit-age-ordered.scala:208:25]
reg is_available_14; // @[issue-unit-age-ordered.scala:208:25]
reg is_available_15; // @[issue-unit-age-ordered.scala:208:25]
reg is_available_16; // @[issue-unit-age-ordered.scala:208:25]
reg is_available_17; // @[issue-unit-age-ordered.scala:208:25]
reg is_available_18; // @[issue-unit-age-ordered.scala:208:25]
reg is_available_19; // @[issue-unit-age-ordered.scala:208:25]
wire [1:0] _GEN = {1'h0, is_available_0} + {1'h0, is_available_1}; // @[issue-unit-age-ordered.scala:208:25, :212:45]
wire [1:0] _io_dis_uops_0_ready_T; // @[issue-unit-age-ordered.scala:212:45]
assign _io_dis_uops_0_ready_T = _GEN; // @[issue-unit-age-ordered.scala:212:45]
wire [1:0] _io_dis_uops_1_ready_T; // @[issue-unit-age-ordered.scala:212:45]
assign _io_dis_uops_1_ready_T = _GEN; // @[issue-unit-age-ordered.scala:212:45]
wire [1:0] _io_dis_uops_0_ready_T_1 = _io_dis_uops_0_ready_T; // @[issue-unit-age-ordered.scala:212:45]
wire [1:0] _GEN_0 = {1'h0, is_available_3} + {1'h0, is_available_4}; // @[issue-unit-age-ordered.scala:208:25, :212:45]
wire [1:0] _io_dis_uops_0_ready_T_2; // @[issue-unit-age-ordered.scala:212:45]
assign _io_dis_uops_0_ready_T_2 = _GEN_0; // @[issue-unit-age-ordered.scala:212:45]
wire [1:0] _io_dis_uops_1_ready_T_2; // @[issue-unit-age-ordered.scala:212:45]
assign _io_dis_uops_1_ready_T_2 = _GEN_0; // @[issue-unit-age-ordered.scala:212:45]
wire [1:0] _io_dis_uops_0_ready_T_3 = _io_dis_uops_0_ready_T_2; // @[issue-unit-age-ordered.scala:212:45]
wire [2:0] _GEN_1 = {2'h0, is_available_2}; // @[issue-unit-age-ordered.scala:208:25, :212:45]
wire [2:0] _io_dis_uops_0_ready_T_4 = _GEN_1 + {1'h0, _io_dis_uops_0_ready_T_3}; // @[issue-unit-age-ordered.scala:212:45]
wire [1:0] _io_dis_uops_0_ready_T_5 = _io_dis_uops_0_ready_T_4[1:0]; // @[issue-unit-age-ordered.scala:212:45]
wire [2:0] _io_dis_uops_0_ready_T_6 = {1'h0, _io_dis_uops_0_ready_T_1} + {1'h0, _io_dis_uops_0_ready_T_5}; // @[issue-unit-age-ordered.scala:212:45]
wire [2:0] _io_dis_uops_0_ready_T_7 = _io_dis_uops_0_ready_T_6; // @[issue-unit-age-ordered.scala:212:45]
wire [1:0] _GEN_2 = {1'h0, is_available_5} + {1'h0, is_available_6}; // @[issue-unit-age-ordered.scala:208:25, :212:45]
wire [1:0] _io_dis_uops_0_ready_T_8; // @[issue-unit-age-ordered.scala:212:45]
assign _io_dis_uops_0_ready_T_8 = _GEN_2; // @[issue-unit-age-ordered.scala:212:45]
wire [1:0] _io_dis_uops_1_ready_T_8; // @[issue-unit-age-ordered.scala:212:45]
assign _io_dis_uops_1_ready_T_8 = _GEN_2; // @[issue-unit-age-ordered.scala:212:45]
wire [1:0] _io_dis_uops_0_ready_T_9 = _io_dis_uops_0_ready_T_8; // @[issue-unit-age-ordered.scala:212:45]
wire [1:0] _GEN_3 = {1'h0, is_available_8} + {1'h0, is_available_9}; // @[issue-unit-age-ordered.scala:208:25, :212:45]
wire [1:0] _io_dis_uops_0_ready_T_10; // @[issue-unit-age-ordered.scala:212:45]
assign _io_dis_uops_0_ready_T_10 = _GEN_3; // @[issue-unit-age-ordered.scala:212:45]
wire [1:0] _io_dis_uops_1_ready_T_10; // @[issue-unit-age-ordered.scala:212:45]
assign _io_dis_uops_1_ready_T_10 = _GEN_3; // @[issue-unit-age-ordered.scala:212:45]
wire [1:0] _io_dis_uops_0_ready_T_11 = _io_dis_uops_0_ready_T_10; // @[issue-unit-age-ordered.scala:212:45]
wire [2:0] _GEN_4 = {2'h0, is_available_7}; // @[issue-unit-age-ordered.scala:208:25, :212:45]
wire [2:0] _io_dis_uops_0_ready_T_12 = _GEN_4 + {1'h0, _io_dis_uops_0_ready_T_11}; // @[issue-unit-age-ordered.scala:212:45]
wire [1:0] _io_dis_uops_0_ready_T_13 = _io_dis_uops_0_ready_T_12[1:0]; // @[issue-unit-age-ordered.scala:212:45]
wire [2:0] _io_dis_uops_0_ready_T_14 = {1'h0, _io_dis_uops_0_ready_T_9} + {1'h0, _io_dis_uops_0_ready_T_13}; // @[issue-unit-age-ordered.scala:212:45]
wire [2:0] _io_dis_uops_0_ready_T_15 = _io_dis_uops_0_ready_T_14; // @[issue-unit-age-ordered.scala:212:45]
wire [3:0] _io_dis_uops_0_ready_T_16 = {1'h0, _io_dis_uops_0_ready_T_7} + {1'h0, _io_dis_uops_0_ready_T_15}; // @[issue-unit-age-ordered.scala:212:45]
wire [3:0] _io_dis_uops_0_ready_T_17 = _io_dis_uops_0_ready_T_16; // @[issue-unit-age-ordered.scala:212:45]
wire [1:0] _GEN_5 = {1'h0, is_available_10} + {1'h0, is_available_11}; // @[issue-unit-age-ordered.scala:208:25, :212:45]
wire [1:0] _io_dis_uops_0_ready_T_18; // @[issue-unit-age-ordered.scala:212:45]
assign _io_dis_uops_0_ready_T_18 = _GEN_5; // @[issue-unit-age-ordered.scala:212:45]
wire [1:0] _io_dis_uops_1_ready_T_18; // @[issue-unit-age-ordered.scala:212:45]
assign _io_dis_uops_1_ready_T_18 = _GEN_5; // @[issue-unit-age-ordered.scala:212:45]
wire [1:0] _io_dis_uops_0_ready_T_19 = _io_dis_uops_0_ready_T_18; // @[issue-unit-age-ordered.scala:212:45]
wire [1:0] _GEN_6 = {1'h0, is_available_13} + {1'h0, is_available_14}; // @[issue-unit-age-ordered.scala:208:25, :212:45]
wire [1:0] _io_dis_uops_0_ready_T_20; // @[issue-unit-age-ordered.scala:212:45]
assign _io_dis_uops_0_ready_T_20 = _GEN_6; // @[issue-unit-age-ordered.scala:212:45]
wire [1:0] _io_dis_uops_1_ready_T_20; // @[issue-unit-age-ordered.scala:212:45]
assign _io_dis_uops_1_ready_T_20 = _GEN_6; // @[issue-unit-age-ordered.scala:212:45]
wire [1:0] _io_dis_uops_0_ready_T_21 = _io_dis_uops_0_ready_T_20; // @[issue-unit-age-ordered.scala:212:45]
wire [2:0] _GEN_7 = {2'h0, is_available_12}; // @[issue-unit-age-ordered.scala:208:25, :212:45]
wire [2:0] _io_dis_uops_0_ready_T_22 = _GEN_7 + {1'h0, _io_dis_uops_0_ready_T_21}; // @[issue-unit-age-ordered.scala:212:45]
wire [1:0] _io_dis_uops_0_ready_T_23 = _io_dis_uops_0_ready_T_22[1:0]; // @[issue-unit-age-ordered.scala:212:45]
wire [2:0] _io_dis_uops_0_ready_T_24 = {1'h0, _io_dis_uops_0_ready_T_19} + {1'h0, _io_dis_uops_0_ready_T_23}; // @[issue-unit-age-ordered.scala:212:45]
wire [2:0] _io_dis_uops_0_ready_T_25 = _io_dis_uops_0_ready_T_24; // @[issue-unit-age-ordered.scala:212:45]
wire [1:0] _GEN_8 = {1'h0, is_available_15} + {1'h0, is_available_16}; // @[issue-unit-age-ordered.scala:208:25, :212:45]
wire [1:0] _io_dis_uops_0_ready_T_26; // @[issue-unit-age-ordered.scala:212:45]
assign _io_dis_uops_0_ready_T_26 = _GEN_8; // @[issue-unit-age-ordered.scala:212:45]
wire [1:0] _io_dis_uops_1_ready_T_26; // @[issue-unit-age-ordered.scala:212:45]
assign _io_dis_uops_1_ready_T_26 = _GEN_8; // @[issue-unit-age-ordered.scala:212:45]
wire [1:0] _io_dis_uops_0_ready_T_27 = _io_dis_uops_0_ready_T_26; // @[issue-unit-age-ordered.scala:212:45]
wire [1:0] _GEN_9 = {1'h0, is_available_18} + {1'h0, is_available_19}; // @[issue-unit-age-ordered.scala:208:25, :212:45]
wire [1:0] _io_dis_uops_0_ready_T_28; // @[issue-unit-age-ordered.scala:212:45]
assign _io_dis_uops_0_ready_T_28 = _GEN_9; // @[issue-unit-age-ordered.scala:212:45]
wire [1:0] _io_dis_uops_1_ready_T_28; // @[issue-unit-age-ordered.scala:212:45]
assign _io_dis_uops_1_ready_T_28 = _GEN_9; // @[issue-unit-age-ordered.scala:212:45]
wire [1:0] _io_dis_uops_0_ready_T_29 = _io_dis_uops_0_ready_T_28; // @[issue-unit-age-ordered.scala:212:45]
wire [2:0] _GEN_10 = {2'h0, is_available_17}; // @[issue-unit-age-ordered.scala:208:25, :212:45]
wire [2:0] _io_dis_uops_0_ready_T_30 = _GEN_10 + {1'h0, _io_dis_uops_0_ready_T_29}; // @[issue-unit-age-ordered.scala:212:45]
wire [1:0] _io_dis_uops_0_ready_T_31 = _io_dis_uops_0_ready_T_30[1:0]; // @[issue-unit-age-ordered.scala:212:45]
wire [2:0] _io_dis_uops_0_ready_T_32 = {1'h0, _io_dis_uops_0_ready_T_27} + {1'h0, _io_dis_uops_0_ready_T_31}; // @[issue-unit-age-ordered.scala:212:45]
wire [2:0] _io_dis_uops_0_ready_T_33 = _io_dis_uops_0_ready_T_32; // @[issue-unit-age-ordered.scala:212:45]
wire [3:0] _io_dis_uops_0_ready_T_34 = {1'h0, _io_dis_uops_0_ready_T_25} + {1'h0, _io_dis_uops_0_ready_T_33}; // @[issue-unit-age-ordered.scala:212:45]
wire [3:0] _io_dis_uops_0_ready_T_35 = _io_dis_uops_0_ready_T_34; // @[issue-unit-age-ordered.scala:212:45]
wire [4:0] _io_dis_uops_0_ready_T_36 = {1'h0, _io_dis_uops_0_ready_T_17} + {1'h0, _io_dis_uops_0_ready_T_35}; // @[issue-unit-age-ordered.scala:212:45]
wire [4:0] _io_dis_uops_0_ready_T_37 = _io_dis_uops_0_ready_T_36; // @[issue-unit-age-ordered.scala:212:45]
wire _GEN_11 = io_dis_uops_0_ready_0 & io_dis_uops_0_valid_0; // @[Decoupled.scala:51:35]
wire _io_dis_uops_0_ready_T_38; // @[Decoupled.scala:51:35]
assign _io_dis_uops_0_ready_T_38 = _GEN_11; // @[Decoupled.scala:51:35]
wire _io_dis_uops_1_ready_T_38; // @[Decoupled.scala:51:35]
assign _io_dis_uops_1_ready_T_38 = _GEN_11; // @[Decoupled.scala:51:35]
wire _GEN_12 = io_dis_uops_1_ready_0 & io_dis_uops_1_valid_0; // @[Decoupled.scala:51:35]
wire _io_dis_uops_0_ready_T_39; // @[Decoupled.scala:51:35]
assign _io_dis_uops_0_ready_T_39 = _GEN_12; // @[Decoupled.scala:51:35]
wire _io_dis_uops_1_ready_T_39; // @[Decoupled.scala:51:35]
assign _io_dis_uops_1_ready_T_39 = _GEN_12; // @[Decoupled.scala:51:35]
wire [1:0] _io_dis_uops_0_ready_T_40 = {1'h0, _io_dis_uops_0_ready_T_38} + {1'h0, _io_dis_uops_0_ready_T_39}; // @[Decoupled.scala:51:35]
wire [1:0] _io_dis_uops_0_ready_T_41 = _io_dis_uops_0_ready_T_40; // @[issue-unit-age-ordered.scala:212:100]
wire [5:0] _io_dis_uops_0_ready_T_42 = {4'h0, _io_dis_uops_0_ready_T_41}; // @[issue-unit-age-ordered.scala:212:{90,100}]
wire [4:0] _io_dis_uops_0_ready_T_43 = _io_dis_uops_0_ready_T_42[4:0]; // @[issue-unit-age-ordered.scala:212:90]
wire _io_dis_uops_0_ready_T_44 = _io_dis_uops_0_ready_T_37 > _io_dis_uops_0_ready_T_43; // @[issue-unit-age-ordered.scala:212:{45,60,90}]
reg io_dis_uops_0_ready_REG; // @[issue-unit-age-ordered.scala:212:36]
assign io_dis_uops_0_ready_0 = io_dis_uops_0_ready_REG; // @[issue-unit-age-ordered.scala:22:7, :212:36]
wire [1:0] _io_dis_uops_1_ready_T_1 = _io_dis_uops_1_ready_T; // @[issue-unit-age-ordered.scala:212:45]
wire [1:0] _io_dis_uops_1_ready_T_3 = _io_dis_uops_1_ready_T_2; // @[issue-unit-age-ordered.scala:212:45]
wire [2:0] _io_dis_uops_1_ready_T_4 = _GEN_1 + {1'h0, _io_dis_uops_1_ready_T_3}; // @[issue-unit-age-ordered.scala:212:45]
wire [1:0] _io_dis_uops_1_ready_T_5 = _io_dis_uops_1_ready_T_4[1:0]; // @[issue-unit-age-ordered.scala:212:45]
wire [2:0] _io_dis_uops_1_ready_T_6 = {1'h0, _io_dis_uops_1_ready_T_1} + {1'h0, _io_dis_uops_1_ready_T_5}; // @[issue-unit-age-ordered.scala:212:45]
wire [2:0] _io_dis_uops_1_ready_T_7 = _io_dis_uops_1_ready_T_6; // @[issue-unit-age-ordered.scala:212:45]
wire [1:0] _io_dis_uops_1_ready_T_9 = _io_dis_uops_1_ready_T_8; // @[issue-unit-age-ordered.scala:212:45]
wire [1:0] _io_dis_uops_1_ready_T_11 = _io_dis_uops_1_ready_T_10; // @[issue-unit-age-ordered.scala:212:45]
wire [2:0] _io_dis_uops_1_ready_T_12 = _GEN_4 + {1'h0, _io_dis_uops_1_ready_T_11}; // @[issue-unit-age-ordered.scala:212:45]
wire [1:0] _io_dis_uops_1_ready_T_13 = _io_dis_uops_1_ready_T_12[1:0]; // @[issue-unit-age-ordered.scala:212:45]
wire [2:0] _io_dis_uops_1_ready_T_14 = {1'h0, _io_dis_uops_1_ready_T_9} + {1'h0, _io_dis_uops_1_ready_T_13}; // @[issue-unit-age-ordered.scala:212:45]
wire [2:0] _io_dis_uops_1_ready_T_15 = _io_dis_uops_1_ready_T_14; // @[issue-unit-age-ordered.scala:212:45]
wire [3:0] _io_dis_uops_1_ready_T_16 = {1'h0, _io_dis_uops_1_ready_T_7} + {1'h0, _io_dis_uops_1_ready_T_15}; // @[issue-unit-age-ordered.scala:212:45]
wire [3:0] _io_dis_uops_1_ready_T_17 = _io_dis_uops_1_ready_T_16; // @[issue-unit-age-ordered.scala:212:45]
wire [1:0] _io_dis_uops_1_ready_T_19 = _io_dis_uops_1_ready_T_18; // @[issue-unit-age-ordered.scala:212:45]
wire [1:0] _io_dis_uops_1_ready_T_21 = _io_dis_uops_1_ready_T_20; // @[issue-unit-age-ordered.scala:212:45]
wire [2:0] _io_dis_uops_1_ready_T_22 = _GEN_7 + {1'h0, _io_dis_uops_1_ready_T_21}; // @[issue-unit-age-ordered.scala:212:45]
wire [1:0] _io_dis_uops_1_ready_T_23 = _io_dis_uops_1_ready_T_22[1:0]; // @[issue-unit-age-ordered.scala:212:45]
wire [2:0] _io_dis_uops_1_ready_T_24 = {1'h0, _io_dis_uops_1_ready_T_19} + {1'h0, _io_dis_uops_1_ready_T_23}; // @[issue-unit-age-ordered.scala:212:45]
wire [2:0] _io_dis_uops_1_ready_T_25 = _io_dis_uops_1_ready_T_24; // @[issue-unit-age-ordered.scala:212:45]
wire [1:0] _io_dis_uops_1_ready_T_27 = _io_dis_uops_1_ready_T_26; // @[issue-unit-age-ordered.scala:212:45]
wire [1:0] _io_dis_uops_1_ready_T_29 = _io_dis_uops_1_ready_T_28; // @[issue-unit-age-ordered.scala:212:45]
wire [2:0] _io_dis_uops_1_ready_T_30 = _GEN_10 + {1'h0, _io_dis_uops_1_ready_T_29}; // @[issue-unit-age-ordered.scala:212:45]
wire [1:0] _io_dis_uops_1_ready_T_31 = _io_dis_uops_1_ready_T_30[1:0]; // @[issue-unit-age-ordered.scala:212:45]
wire [2:0] _io_dis_uops_1_ready_T_32 = {1'h0, _io_dis_uops_1_ready_T_27} + {1'h0, _io_dis_uops_1_ready_T_31}; // @[issue-unit-age-ordered.scala:212:45]
wire [2:0] _io_dis_uops_1_ready_T_33 = _io_dis_uops_1_ready_T_32; // @[issue-unit-age-ordered.scala:212:45]
wire [3:0] _io_dis_uops_1_ready_T_34 = {1'h0, _io_dis_uops_1_ready_T_25} + {1'h0, _io_dis_uops_1_ready_T_33}; // @[issue-unit-age-ordered.scala:212:45]
wire [3:0] _io_dis_uops_1_ready_T_35 = _io_dis_uops_1_ready_T_34; // @[issue-unit-age-ordered.scala:212:45]
wire [4:0] _io_dis_uops_1_ready_T_36 = {1'h0, _io_dis_uops_1_ready_T_17} + {1'h0, _io_dis_uops_1_ready_T_35}; // @[issue-unit-age-ordered.scala:212:45]
wire [4:0] _io_dis_uops_1_ready_T_37 = _io_dis_uops_1_ready_T_36; // @[issue-unit-age-ordered.scala:212:45]
wire [1:0] _io_dis_uops_1_ready_T_40 = {1'h0, _io_dis_uops_1_ready_T_38} + {1'h0, _io_dis_uops_1_ready_T_39}; // @[Decoupled.scala:51:35]
wire [1:0] _io_dis_uops_1_ready_T_41 = _io_dis_uops_1_ready_T_40; // @[issue-unit-age-ordered.scala:212:100]
wire [5:0] _io_dis_uops_1_ready_T_42 = {4'h0, _io_dis_uops_1_ready_T_41} + 6'h1; // @[issue-unit-age-ordered.scala:212:{90,100}]
wire [4:0] _io_dis_uops_1_ready_T_43 = _io_dis_uops_1_ready_T_42[4:0]; // @[issue-unit-age-ordered.scala:212:90]
wire _io_dis_uops_1_ready_T_44 = _io_dis_uops_1_ready_T_37 > _io_dis_uops_1_ready_T_43; // @[issue-unit-age-ordered.scala:212:{45,60,90}]
reg io_dis_uops_1_ready_REG; // @[issue-unit-age-ordered.scala:212:36]
assign io_dis_uops_1_ready_0 = io_dis_uops_1_ready_REG; // @[issue-unit-age-ordered.scala:22:7, :212:36] |
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_44 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}}}, flip vcalloc_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, flip out_credit_available : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}[1], debug : { va_stall : UInt<2>, sa_stall : UInt<2>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}}
inst input_buffer of InputBuffer_44
connect input_buffer.clock, clock
connect input_buffer.reset, reset
connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id
connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id
connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node
connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id
connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node
connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id
connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload
connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail
connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head
connect input_buffer.io.enq[0].valid, io.in.flit[0].valid
connect input_buffer.io.deq[0].ready, UInt<1>(0h0)
connect input_buffer.io.deq[1].ready, UInt<1>(0h0)
connect input_buffer.io.deq[2].ready, UInt<1>(0h0)
inst route_arbiter of Arbiter3_RouteComputerReq_44
connect route_arbiter.clock, clock
connect route_arbiter.reset, reset
connect io.router_req.bits, route_arbiter.io.out.bits
connect io.router_req.valid, route_arbiter.io.out.valid
connect route_arbiter.io.out.ready, io.router_req.ready
reg states : { g : UInt<3>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, fifo_deps : UInt<3>}[3], clock
node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T :
node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3))
node _T_2 = asUInt(reset)
node _T_3 = eq(_T_2, UInt<1>(0h0))
when _T_3 :
node _T_4 = eq(_T_1, UInt<1>(0h0))
when _T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf
assert(clock, _T_1, UInt<1>(0h1), "") : assert
node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0))
node _T_6 = asUInt(reset)
node _T_7 = eq(_T_6, UInt<1>(0h0))
when _T_7 :
node _T_8 = eq(_T_5, UInt<1>(0h0))
when _T_8 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1
assert(clock, _T_5, UInt<1>(0h1), "") : assert_1
node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0he))
node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1))
connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0)
node _T_9 = eq(UInt<1>(0h0), io.in.flit[0].bits.flow.egress_node_id)
when _T_9 :
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h1)
connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow
connect route_arbiter.io.in[0].valid, UInt<1>(0h0)
invalidate route_arbiter.io.in[0].bits.flow.egress_node_id
invalidate route_arbiter.io.in[0].bits.flow.egress_node
invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id
invalidate route_arbiter.io.in[0].bits.flow.ingress_node
invalidate route_arbiter.io.in[0].bits.flow.vnet_id
invalidate route_arbiter.io.in[0].bits.src_virt_id
node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1))
connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T
connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id
connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node
connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id
connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node
connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id
connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1)
node _T_10 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid)
when _T_10 :
connect states[1].g, UInt<3>(0h2)
node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1))
connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T
connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id
connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node
connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id
connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node
connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id
connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2)
node _T_11 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid)
when _T_11 :
connect states[2].g, UInt<3>(0h2)
node _T_12 = and(io.router_req.ready, io.router_req.valid)
when _T_12 :
node _T_13 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1))
node _T_14 = asUInt(reset)
node _T_15 = eq(_T_14, UInt<1>(0h0))
when _T_15 :
node _T_16 = eq(_T_13, UInt<1>(0h0))
when _T_16 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2
assert(clock, _T_13, UInt<1>(0h1), "") : assert_2
connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2)
node _T_17 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id)
when _T_17 :
connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_18 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id)
when _T_18 :
connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_19 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id)
when _T_19 :
connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2`
regreset mask : UInt<3>, clock, reset, UInt<3>(0h0)
wire vcalloc_reqs : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}}[3]
wire vcalloc_vals : UInt<1>[3]
node vcalloc_filter_hi = cat(vcalloc_vals[2], vcalloc_vals[1])
node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_vals[0])
node vcalloc_filter_hi_1 = cat(vcalloc_vals[2], vcalloc_vals[1])
node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_vals[0])
node _vcalloc_filter_T_2 = not(mask)
node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2)
node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3)
node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0)
node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1)
node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2)
node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3)
node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4)
node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5)
node _vcalloc_filter_T_11 = mux(_vcalloc_filter_T_10, UInt<6>(0h20), UInt<6>(0h0))
node _vcalloc_filter_T_12 = mux(_vcalloc_filter_T_9, UInt<6>(0h10), _vcalloc_filter_T_11)
node _vcalloc_filter_T_13 = mux(_vcalloc_filter_T_8, UInt<6>(0h8), _vcalloc_filter_T_12)
node _vcalloc_filter_T_14 = mux(_vcalloc_filter_T_7, UInt<6>(0h4), _vcalloc_filter_T_13)
node _vcalloc_filter_T_15 = mux(_vcalloc_filter_T_6, UInt<6>(0h2), _vcalloc_filter_T_14)
node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<6>(0h1), _vcalloc_filter_T_15)
node _vcalloc_sel_T = bits(vcalloc_filter, 2, 0)
node _vcalloc_sel_T_1 = shr(vcalloc_filter, 3)
node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1)
node _T_20 = and(io.router_req.ready, io.router_req.valid)
when _T_20 :
node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id)
node _mask_T_1 = sub(_mask_T, UInt<1>(0h1))
node _mask_T_2 = tail(_mask_T_1, 1)
connect mask, _mask_T_2
else :
node _T_21 = or(vcalloc_vals[0], vcalloc_vals[1])
node _T_22 = or(_T_21, vcalloc_vals[2])
when _T_22 :
node _mask_T_3 = not(UInt<1>(0h0))
node _mask_T_4 = not(UInt<2>(0h0))
node _mask_T_5 = not(UInt<3>(0h0))
node _mask_T_6 = bits(vcalloc_sel, 0, 0)
node _mask_T_7 = bits(vcalloc_sel, 1, 1)
node _mask_T_8 = bits(vcalloc_sel, 2, 2)
node _mask_T_9 = mux(_mask_T_6, _mask_T_3, UInt<1>(0h0))
node _mask_T_10 = mux(_mask_T_7, _mask_T_4, UInt<1>(0h0))
node _mask_T_11 = mux(_mask_T_8, _mask_T_5, UInt<1>(0h0))
node _mask_T_12 = or(_mask_T_9, _mask_T_10)
node _mask_T_13 = or(_mask_T_12, _mask_T_11)
wire _mask_WIRE : UInt<3>
connect _mask_WIRE, _mask_T_13
connect mask, _mask_WIRE
node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1])
node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2])
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_1
node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0)
node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1)
node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2)
wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}}
wire _io_vcalloc_req_bits_WIRE_1 : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}
wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[3]
node _io_vcalloc_req_bits_T_3 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_4 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_5 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_6 = or(_io_vcalloc_req_bits_T_3, _io_vcalloc_req_bits_T_4)
node _io_vcalloc_req_bits_T_7 = or(_io_vcalloc_req_bits_T_6, _io_vcalloc_req_bits_T_5)
wire _io_vcalloc_req_bits_WIRE_3 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_7
connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3
node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_11 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9)
node _io_vcalloc_req_bits_T_12 = or(_io_vcalloc_req_bits_T_11, _io_vcalloc_req_bits_T_10)
wire _io_vcalloc_req_bits_WIRE_4 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_12
connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4
node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_13, _io_vcalloc_req_bits_T_14)
node _io_vcalloc_req_bits_T_17 = or(_io_vcalloc_req_bits_T_16, _io_vcalloc_req_bits_T_15)
wire _io_vcalloc_req_bits_WIRE_5 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_17
connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5
connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2
wire _io_vcalloc_req_bits_WIRE_6 : UInt<1>[3]
node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_19 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_20 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_18, _io_vcalloc_req_bits_T_19)
node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_20)
wire _io_vcalloc_req_bits_WIRE_7 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_22
connect _io_vcalloc_req_bits_WIRE_6[0], _io_vcalloc_req_bits_WIRE_7
node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_26 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24)
node _io_vcalloc_req_bits_T_27 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_25)
wire _io_vcalloc_req_bits_WIRE_8 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_27
connect _io_vcalloc_req_bits_WIRE_6[1], _io_vcalloc_req_bits_WIRE_8
node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_28, _io_vcalloc_req_bits_T_29)
node _io_vcalloc_req_bits_T_32 = or(_io_vcalloc_req_bits_T_31, _io_vcalloc_req_bits_T_30)
wire _io_vcalloc_req_bits_WIRE_9 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_32
connect _io_vcalloc_req_bits_WIRE_6[2], _io_vcalloc_req_bits_WIRE_9
connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_6
wire _io_vcalloc_req_bits_WIRE_10 : UInt<1>[1]
node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_34 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_33, _io_vcalloc_req_bits_T_34)
node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_35)
wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_11, _io_vcalloc_req_bits_T_37
connect _io_vcalloc_req_bits_WIRE_10[0], _io_vcalloc_req_bits_WIRE_11
connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_10
connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1
node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_41 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39)
node _io_vcalloc_req_bits_T_42 = or(_io_vcalloc_req_bits_T_41, _io_vcalloc_req_bits_T_40)
wire _io_vcalloc_req_bits_WIRE_12 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_42
connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_12
wire _io_vcalloc_req_bits_WIRE_13 : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}
node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_43, _io_vcalloc_req_bits_T_44)
node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_45)
wire _io_vcalloc_req_bits_WIRE_14 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_47
connect _io_vcalloc_req_bits_WIRE_13.egress_node_id, _io_vcalloc_req_bits_WIRE_14
node _io_vcalloc_req_bits_T_48 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_49 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_50 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_51 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_49)
node _io_vcalloc_req_bits_T_52 = or(_io_vcalloc_req_bits_T_51, _io_vcalloc_req_bits_T_50)
wire _io_vcalloc_req_bits_WIRE_15 : UInt<4>
connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_52
connect _io_vcalloc_req_bits_WIRE_13.egress_node, _io_vcalloc_req_bits_WIRE_15
node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_56 = or(_io_vcalloc_req_bits_T_53, _io_vcalloc_req_bits_T_54)
node _io_vcalloc_req_bits_T_57 = or(_io_vcalloc_req_bits_T_56, _io_vcalloc_req_bits_T_55)
wire _io_vcalloc_req_bits_WIRE_16 : UInt<3>
connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_57
connect _io_vcalloc_req_bits_WIRE_13.ingress_node_id, _io_vcalloc_req_bits_WIRE_16
node _io_vcalloc_req_bits_T_58 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_58, _io_vcalloc_req_bits_T_59)
node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_60)
wire _io_vcalloc_req_bits_WIRE_17 : UInt<4>
connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_62
connect _io_vcalloc_req_bits_WIRE_13.ingress_node, _io_vcalloc_req_bits_WIRE_17
node _io_vcalloc_req_bits_T_63 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_64 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_65 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_64)
node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_65)
wire _io_vcalloc_req_bits_WIRE_18 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_67
connect _io_vcalloc_req_bits_WIRE_13.vnet_id, _io_vcalloc_req_bits_WIRE_18
connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_13
connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE
connect vcalloc_vals[0], UInt<1>(0h0)
invalidate vcalloc_reqs[0].vc_sel.`0`[0]
invalidate vcalloc_reqs[0].vc_sel.`0`[1]
invalidate vcalloc_reqs[0].vc_sel.`0`[2]
invalidate vcalloc_reqs[0].vc_sel.`1`[0]
invalidate vcalloc_reqs[0].vc_sel.`1`[1]
invalidate vcalloc_reqs[0].vc_sel.`1`[2]
invalidate vcalloc_reqs[0].vc_sel.`2`[0]
invalidate vcalloc_reqs[0].in_vc
invalidate vcalloc_reqs[0].flow.egress_node_id
invalidate vcalloc_reqs[0].flow.egress_node
invalidate vcalloc_reqs[0].flow.ingress_node_id
invalidate vcalloc_reqs[0].flow.ingress_node
invalidate vcalloc_reqs[0].flow.vnet_id
node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2))
node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1)
connect vcalloc_vals[1], _vcalloc_vals_1_T_2
connect vcalloc_reqs[1].in_vc, UInt<1>(0h1)
connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0`
connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1`
connect vcalloc_reqs[1].vc_sel.`2`, states[1].vc_sel.`2`
connect vcalloc_reqs[1].flow, states[1].flow
node _T_23 = bits(vcalloc_sel, 1, 1)
node _T_24 = and(vcalloc_vals[1], _T_23)
node _T_25 = and(_T_24, io.vcalloc_req.ready)
when _T_25 :
connect states[1].g, UInt<3>(0h3)
node _T_26 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid)
when _T_26 :
connect vcalloc_vals[1], UInt<1>(0h1)
connect vcalloc_reqs[1].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect vcalloc_reqs[1].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect vcalloc_reqs[1].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2))
node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1)
connect vcalloc_vals[2], _vcalloc_vals_2_T_2
connect vcalloc_reqs[2].in_vc, UInt<2>(0h2)
connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0`
connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1`
connect vcalloc_reqs[2].vc_sel.`2`, states[2].vc_sel.`2`
connect vcalloc_reqs[2].flow, states[2].flow
node _T_27 = bits(vcalloc_sel, 2, 2)
node _T_28 = and(vcalloc_vals[2], _T_27)
node _T_29 = and(_T_28, io.vcalloc_req.ready)
when _T_29 :
connect states[2].g, UInt<3>(0h3)
node _T_30 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid)
when _T_30 :
connect vcalloc_vals[2], UInt<1>(0h1)
connect vcalloc_reqs[2].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect vcalloc_reqs[2].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect vcalloc_reqs[2].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _io_debug_va_stall_T = add(vcalloc_vals[1], vcalloc_vals[2])
node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0)
node _io_debug_va_stall_T_2 = add(vcalloc_vals[0], _io_debug_va_stall_T_1)
node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0)
node _io_debug_va_stall_T_4 = sub(_io_debug_va_stall_T_3, io.vcalloc_req.ready)
node _io_debug_va_stall_T_5 = tail(_io_debug_va_stall_T_4, 1)
connect io.debug.va_stall, _io_debug_va_stall_T_5
node _T_31 = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
when _T_31 :
node _T_32 = bits(vcalloc_sel, 0, 0)
when _T_32 :
connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[0].g, UInt<3>(0h3)
node _T_33 = bits(vcalloc_sel, 1, 1)
when _T_33 :
connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[1].g, UInt<3>(0h3)
node _T_34 = bits(vcalloc_sel, 2, 2)
when _T_34 :
connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[2].g, UInt<3>(0h3)
inst salloc_arb of SwitchArbiter_108
connect salloc_arb.clock, clock
connect salloc_arb.reset, reset
connect salloc_arb.io.in[0].valid, UInt<1>(0h0)
invalidate salloc_arb.io.in[0].bits.tail
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[2]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[1]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[2]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[0]
node credit_available_hi = cat(states[1].vc_sel.`0`[2], states[1].vc_sel.`0`[1])
node _credit_available_T = cat(credit_available_hi, states[1].vc_sel.`0`[0])
node credit_available_hi_1 = cat(states[1].vc_sel.`1`[2], states[1].vc_sel.`1`[1])
node _credit_available_T_1 = cat(credit_available_hi_1, states[1].vc_sel.`1`[0])
node credit_available_hi_2 = cat(states[1].vc_sel.`2`[0], _credit_available_T_1)
node _credit_available_T_2 = cat(credit_available_hi_2, _credit_available_T)
node credit_available_hi_3 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1])
node _credit_available_T_3 = cat(credit_available_hi_3, io.out_credit_available.`0`[0])
node credit_available_hi_4 = cat(io.out_credit_available.`1`[2], io.out_credit_available.`1`[1])
node _credit_available_T_4 = cat(credit_available_hi_4, io.out_credit_available.`1`[0])
node credit_available_hi_5 = cat(io.out_credit_available.`2`[0], _credit_available_T_4)
node _credit_available_T_5 = cat(credit_available_hi_5, _credit_available_T_3)
node _credit_available_T_6 = and(_credit_available_T_2, _credit_available_T_5)
node credit_available = neq(_credit_available_T_6, UInt<1>(0h0))
node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3))
node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available)
node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid)
connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2
connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[2], states[1].vc_sel.`0`[2]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[1], states[1].vc_sel.`1`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[2], states[1].vc_sel.`1`[2]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[0], states[1].vc_sel.`2`[0]
connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail
node _T_35 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid)
node _T_36 = and(_T_35, input_buffer.io.deq[1].bits.tail)
when _T_36 :
connect states[1].g, UInt<3>(0h0)
connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready
node credit_available_hi_6 = cat(states[2].vc_sel.`0`[2], states[2].vc_sel.`0`[1])
node _credit_available_T_7 = cat(credit_available_hi_6, states[2].vc_sel.`0`[0])
node credit_available_hi_7 = cat(states[2].vc_sel.`1`[2], states[2].vc_sel.`1`[1])
node _credit_available_T_8 = cat(credit_available_hi_7, states[2].vc_sel.`1`[0])
node credit_available_hi_8 = cat(states[2].vc_sel.`2`[0], _credit_available_T_8)
node _credit_available_T_9 = cat(credit_available_hi_8, _credit_available_T_7)
node credit_available_hi_9 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1])
node _credit_available_T_10 = cat(credit_available_hi_9, io.out_credit_available.`0`[0])
node credit_available_hi_10 = cat(io.out_credit_available.`1`[2], io.out_credit_available.`1`[1])
node _credit_available_T_11 = cat(credit_available_hi_10, io.out_credit_available.`1`[0])
node credit_available_hi_11 = cat(io.out_credit_available.`2`[0], _credit_available_T_11)
node _credit_available_T_12 = cat(credit_available_hi_11, _credit_available_T_10)
node _credit_available_T_13 = and(_credit_available_T_9, _credit_available_T_12)
node credit_available_1 = neq(_credit_available_T_13, UInt<1>(0h0))
node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3))
node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available_1)
node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid)
connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2
connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[1], states[2].vc_sel.`1`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[2], states[2].vc_sel.`1`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[0], states[2].vc_sel.`2`[0]
connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail
node _T_37 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid)
node _T_38 = and(_T_37, input_buffer.io.deq[2].bits.tail)
when _T_38 :
connect states[2].g, UInt<3>(0h0)
connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready
node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T)
node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2)
node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4)
node _io_debug_sa_stall_T_6 = add(_io_debug_sa_stall_T_3, _io_debug_sa_stall_T_5)
node _io_debug_sa_stall_T_7 = bits(_io_debug_sa_stall_T_6, 1, 0)
node _io_debug_sa_stall_T_8 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_7)
node _io_debug_sa_stall_T_9 = bits(_io_debug_sa_stall_T_8, 1, 0)
connect io.debug.sa_stall, _io_debug_sa_stall_T_9
connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits
connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid
connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready
when io.block :
connect salloc_arb.io.out[0].ready, UInt<1>(0h0)
connect io.salloc_req[0].valid, UInt<1>(0h0)
wire salloc_outs : { valid : UInt<1>, vid : UInt<2>, out_vid : UInt<2>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1]
node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.credit_return, _io_in_credit_return_T_1
node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _io_in_vc_free_T_4 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_5 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_6 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_7 = or(_io_in_vc_free_T_4, _io_in_vc_free_T_5)
node _io_in_vc_free_T_8 = or(_io_in_vc_free_T_7, _io_in_vc_free_T_6)
wire _io_in_vc_free_WIRE : UInt<1>
connect _io_in_vc_free_WIRE, _io_in_vc_free_T_8
node _io_in_vc_free_T_9 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE)
node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_9, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.vc_free, _io_in_vc_free_T_10
node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
connect salloc_outs[0].valid, _salloc_outs_0_valid_T
node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 1, 0)
node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi)
node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo)
node _salloc_outs_0_vid_T_2 = bits(_salloc_outs_0_vid_T_1, 1, 1)
node _salloc_outs_0_vid_T_3 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_2)
connect salloc_outs[0].vid, _salloc_outs_0_vid_T_3
node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
wire vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}
wire _vc_sel_WIRE : UInt<1>[3]
node _vc_sel_T_3 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_4 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_5 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_6 = or(_vc_sel_T_3, _vc_sel_T_4)
node _vc_sel_T_7 = or(_vc_sel_T_6, _vc_sel_T_5)
wire _vc_sel_WIRE_1 : UInt<1>
connect _vc_sel_WIRE_1, _vc_sel_T_7
connect _vc_sel_WIRE[0], _vc_sel_WIRE_1
node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_10 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_11 = or(_vc_sel_T_8, _vc_sel_T_9)
node _vc_sel_T_12 = or(_vc_sel_T_11, _vc_sel_T_10)
wire _vc_sel_WIRE_2 : UInt<1>
connect _vc_sel_WIRE_2, _vc_sel_T_12
connect _vc_sel_WIRE[1], _vc_sel_WIRE_2
node _vc_sel_T_13 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_14 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_15 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_16 = or(_vc_sel_T_13, _vc_sel_T_14)
node _vc_sel_T_17 = or(_vc_sel_T_16, _vc_sel_T_15)
wire _vc_sel_WIRE_3 : UInt<1>
connect _vc_sel_WIRE_3, _vc_sel_T_17
connect _vc_sel_WIRE[2], _vc_sel_WIRE_3
connect vc_sel.`0`, _vc_sel_WIRE
wire _vc_sel_WIRE_4 : UInt<1>[3]
node _vc_sel_T_18 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_19 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_20 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_21 = or(_vc_sel_T_18, _vc_sel_T_19)
node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_20)
wire _vc_sel_WIRE_5 : UInt<1>
connect _vc_sel_WIRE_5, _vc_sel_T_22
connect _vc_sel_WIRE_4[0], _vc_sel_WIRE_5
node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_26 = or(_vc_sel_T_23, _vc_sel_T_24)
node _vc_sel_T_27 = or(_vc_sel_T_26, _vc_sel_T_25)
wire _vc_sel_WIRE_6 : UInt<1>
connect _vc_sel_WIRE_6, _vc_sel_T_27
connect _vc_sel_WIRE_4[1], _vc_sel_WIRE_6
node _vc_sel_T_28 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_29 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_30 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_31 = or(_vc_sel_T_28, _vc_sel_T_29)
node _vc_sel_T_32 = or(_vc_sel_T_31, _vc_sel_T_30)
wire _vc_sel_WIRE_7 : UInt<1>
connect _vc_sel_WIRE_7, _vc_sel_T_32
connect _vc_sel_WIRE_4[2], _vc_sel_WIRE_7
connect vc_sel.`1`, _vc_sel_WIRE_4
wire _vc_sel_WIRE_8 : UInt<1>[1]
node _vc_sel_T_33 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_34 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_35 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_36 = or(_vc_sel_T_33, _vc_sel_T_34)
node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_35)
wire _vc_sel_WIRE_9 : UInt<1>
connect _vc_sel_WIRE_9, _vc_sel_T_37
connect _vc_sel_WIRE_8[0], _vc_sel_WIRE_9
connect vc_sel.`2`, _vc_sel_WIRE_8
node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1])
node channel_oh_0 = or(_channel_oh_T, vc_sel.`0`[2])
node _channel_oh_T_1 = or(vc_sel.`1`[0], vc_sel.`1`[1])
node channel_oh_1 = or(_channel_oh_T_1, vc_sel.`1`[2])
node virt_channel_hi = cat(vc_sel.`0`[2], vc_sel.`0`[1])
node _virt_channel_T = cat(virt_channel_hi, vc_sel.`0`[0])
node virt_channel_hi_1 = bits(_virt_channel_T, 2, 2)
node virt_channel_lo = bits(_virt_channel_T, 1, 0)
node _virt_channel_T_1 = orr(virt_channel_hi_1)
node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo)
node _virt_channel_T_3 = bits(_virt_channel_T_2, 1, 1)
node _virt_channel_T_4 = cat(_virt_channel_T_1, _virt_channel_T_3)
node virt_channel_hi_2 = cat(vc_sel.`1`[2], vc_sel.`1`[1])
node _virt_channel_T_5 = cat(virt_channel_hi_2, vc_sel.`1`[0])
node virt_channel_hi_3 = bits(_virt_channel_T_5, 2, 2)
node virt_channel_lo_1 = bits(_virt_channel_T_5, 1, 0)
node _virt_channel_T_6 = orr(virt_channel_hi_3)
node _virt_channel_T_7 = or(virt_channel_hi_3, virt_channel_lo_1)
node _virt_channel_T_8 = bits(_virt_channel_T_7, 1, 1)
node _virt_channel_T_9 = cat(_virt_channel_T_6, _virt_channel_T_8)
node _virt_channel_T_10 = mux(channel_oh_0, _virt_channel_T_4, UInt<1>(0h0))
node _virt_channel_T_11 = mux(channel_oh_1, _virt_channel_T_9, UInt<1>(0h0))
node _virt_channel_T_12 = mux(vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0))
node _virt_channel_T_13 = or(_virt_channel_T_10, _virt_channel_T_11)
node _virt_channel_T_14 = or(_virt_channel_T_13, _virt_channel_T_12)
wire virt_channel : UInt<2>
connect virt_channel, _virt_channel_T_14
node _T_39 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
when _T_39 :
connect salloc_outs[0].out_vid, virt_channel
node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_payload_T_3 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_4 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_5 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_6 = or(_salloc_outs_0_flit_payload_T_3, _salloc_outs_0_flit_payload_T_4)
node _salloc_outs_0_flit_payload_T_7 = or(_salloc_outs_0_flit_payload_T_6, _salloc_outs_0_flit_payload_T_5)
wire _salloc_outs_0_flit_payload_WIRE : UInt<145>
connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_7
connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE
node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_head_T_3 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_4 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_5 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_6 = or(_salloc_outs_0_flit_head_T_3, _salloc_outs_0_flit_head_T_4)
node _salloc_outs_0_flit_head_T_7 = or(_salloc_outs_0_flit_head_T_6, _salloc_outs_0_flit_head_T_5)
wire _salloc_outs_0_flit_head_WIRE : UInt<1>
connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_7
connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE
node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_tail_T_3 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_4 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_5 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_6 = or(_salloc_outs_0_flit_tail_T_3, _salloc_outs_0_flit_tail_T_4)
node _salloc_outs_0_flit_tail_T_7 = or(_salloc_outs_0_flit_tail_T_6, _salloc_outs_0_flit_tail_T_5)
wire _salloc_outs_0_flit_tail_WIRE : UInt<1>
connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_7
connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE
node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}
node _salloc_outs_0_flit_flow_T_3 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_4 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_5 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_6 = or(_salloc_outs_0_flit_flow_T_3, _salloc_outs_0_flit_flow_T_4)
node _salloc_outs_0_flit_flow_T_7 = or(_salloc_outs_0_flit_flow_T_6, _salloc_outs_0_flit_flow_T_5)
wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_7
connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1
node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_11 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9)
node _salloc_outs_0_flit_flow_T_12 = or(_salloc_outs_0_flit_flow_T_11, _salloc_outs_0_flit_flow_T_10)
wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4>
connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_12
connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2
node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_13, _salloc_outs_0_flit_flow_T_14)
node _salloc_outs_0_flit_flow_T_17 = or(_salloc_outs_0_flit_flow_T_16, _salloc_outs_0_flit_flow_T_15)
wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<3>
connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_17
connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3
node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_19 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_20 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_18, _salloc_outs_0_flit_flow_T_19)
node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_20)
wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4>
connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_22
connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4
node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_26 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24)
node _salloc_outs_0_flit_flow_T_27 = or(_salloc_outs_0_flit_flow_T_26, _salloc_outs_0_flit_flow_T_25)
wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_27
connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5
connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE
else :
invalidate salloc_outs[0].out_vid
invalidate salloc_outs[0].flit.virt_channel_id
invalidate salloc_outs[0].flit.flow.egress_node_id
invalidate salloc_outs[0].flit.flow.egress_node
invalidate salloc_outs[0].flit.flow.ingress_node_id
invalidate salloc_outs[0].flit.flow.ingress_node
invalidate salloc_outs[0].flit.flow.vnet_id
invalidate salloc_outs[0].flit.payload
invalidate salloc_outs[0].flit.tail
invalidate salloc_outs[0].flit.head
invalidate salloc_outs[0].flit.virt_channel_id
connect io.out[0].valid, salloc_outs[0].valid
connect io.out[0].bits.flit, salloc_outs[0].flit
connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid
invalidate states[0].fifo_deps
invalidate states[0].flow.egress_node_id
invalidate states[0].flow.egress_node
invalidate states[0].flow.ingress_node_id
invalidate states[0].flow.ingress_node
invalidate states[0].flow.vnet_id
invalidate states[0].vc_sel.`0`[0]
invalidate states[0].vc_sel.`0`[1]
invalidate states[0].vc_sel.`0`[2]
invalidate states[0].vc_sel.`1`[0]
invalidate states[0].vc_sel.`1`[1]
invalidate states[0].vc_sel.`1`[2]
invalidate states[0].vc_sel.`2`[0]
invalidate states[0].g
connect states[1].vc_sel.`0`[0], UInt<1>(0h0)
connect states[1].vc_sel.`0`[2], UInt<1>(0h0)
connect states[1].vc_sel.`1`[0], UInt<1>(0h0)
connect states[1].vc_sel.`1`[2], UInt<1>(0h0)
connect states[2].vc_sel.`0`[0], UInt<1>(0h0)
connect states[2].vc_sel.`0`[1], UInt<1>(0h0)
connect states[2].vc_sel.`1`[0], UInt<1>(0h0)
connect states[2].vc_sel.`1`[1], UInt<1>(0h0)
node _T_40 = asUInt(reset)
when _T_40 :
connect states[0].g, UInt<3>(0h0)
connect states[1].g, UInt<3>(0h0)
connect states[2].g, UInt<3>(0h0) | module InputUnit_44( // @[InputUnit.scala:158:7]
input clock, // @[InputUnit.scala:158:7]
input reset, // @[InputUnit.scala:158:7]
output [1:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
output [2:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_2, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14]
input io_vcalloc_req_ready, // @[InputUnit.scala:170:14]
output io_vcalloc_req_valid, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_2, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_2, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_2, // @[InputUnit.scala:170:14]
input io_salloc_req_0_ready, // @[InputUnit.scala:170:14]
output io_salloc_req_0_valid, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14]
output io_out_0_valid, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14]
output [144:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14]
output [1:0] io_debug_va_stall, // @[InputUnit.scala:170:14]
output [1:0] io_debug_sa_stall, // @[InputUnit.scala:170:14]
input io_in_flit_0_valid, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14]
input [144:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14]
output [2:0] io_in_credit_return, // @[InputUnit.scala:170:14]
output [2:0] io_in_vc_free // @[InputUnit.scala:170:14]
);
wire _GEN; // @[MixedVec.scala:116:9]
wire vcalloc_reqs_2_vc_sel_1_2; // @[MixedVec.scala:116:9]
wire vcalloc_reqs_2_vc_sel_0_2; // @[MixedVec.scala:116:9]
wire vcalloc_vals_2; // @[InputUnit.scala:266:25, :272:46, :273:29]
wire _GEN_0; // @[MixedVec.scala:116:9]
wire vcalloc_reqs_1_vc_sel_1_1; // @[MixedVec.scala:116:9]
wire vcalloc_reqs_1_vc_sel_0_1; // @[MixedVec.scala:116:9]
wire vcalloc_vals_1; // @[InputUnit.scala:266:25, :272:46, :273:29]
wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26]
wire [2:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26]
wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29]
wire [1:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29]
wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28]
wire [144:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28]
wire [144:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28]
wire [144:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28]
reg [2:0] states_1_g; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [2:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_2_g; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_2; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg [1:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [2:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19]
wire _GEN_1 = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30]
wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire _GEN_2 = _route_arbiter_io_in_1_ready & route_arbiter_io_in_1_valid; // @[Decoupled.scala:51:35]
wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire _GEN_3 = _route_arbiter_io_in_2_ready & route_arbiter_io_in_2_valid; // @[Decoupled.scala:51:35] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_137 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_233
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_137( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
output io_q // @[ShiftReg.scala:36:14]
);
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_233 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IntSyncSyncCrossingSink_n1x1_37 :
output auto : { flip in : { sync : UInt<1>[1]}, out : UInt<1>[1]}
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
wire nodeIn : { sync : UInt<1>[1]}
invalidate nodeIn.sync[0]
wire nodeOut : UInt<1>[1]
invalidate nodeOut[0]
connect auto.out, nodeOut
connect nodeIn, auto.in
connect nodeOut, nodeIn.sync | module IntSyncSyncCrossingSink_n1x1_37(); // @[Crossing.scala:96:9]
wire auto_in_sync_0 = 1'h0; // @[Crossing.scala:96:9]
wire auto_out_0 = 1'h0; // @[Crossing.scala:96:9]
wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire nodeIn_sync_0 = 1'h0; // @[MixedNode.scala:551:17]
wire nodeOut_0 = 1'h0; // @[MixedNode.scala:542:17]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module ConstellationSystemBus :
output auto : { flip coupler_from_rockettile_tl_master_clock_xing_in_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}, flip coupler_from_rockettile_tl_master_clock_xing_in_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}, flip coupler_from_rockettile_tl_master_clock_xing_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}, flip coupler_from_rockettile_tl_master_clock_xing_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}, coupler_to_bus_named_coh_widget_anon_out_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, coupler_to_bus_named_coh_widget_anon_out_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, coupler_to_bus_named_coh_widget_anon_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, coupler_to_bus_named_coh_widget_anon_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip coupler_from_bus_named_fbus_bus_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_bus_named_cbus_bus_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, fixedClockNode_anon_out_5 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_4 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_3 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_2 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_1 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_0 : { clock : Clock, reset : Reset}, flip sbus_clock_groups_in : { member : { sbus_1 : { clock : Clock, reset : Reset}, sbus_0 : { clock : Clock, reset : Reset}}}, sbus_clock_groups_out : { member : { coh_0 : { clock : Clock, reset : Reset}}}}
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst sbus_clock_groups of ClockGroupAggregator_sbus
inst clockGroup of ClockGroup
inst fixedClockNode of FixedClockBroadcast_7
inst broadcast of BundleBridgeNexus_NoOutput
inst system_bus_noc of TLNoC
connect system_bus_noc.clock, childClock
connect system_bus_noc.reset, childReset
inst fixer of TLFIFOFixer
connect fixer.clock, childClock
connect fixer.reset, childReset
inst coupler_to_bus_named_cbus of TLInterconnectCoupler_sbus_to_bus_named_cbus
connect coupler_to_bus_named_cbus.clock, childClock
connect coupler_to_bus_named_cbus.reset, childReset
inst coupler_from_bus_named_fbus of TLInterconnectCoupler_sbus_from_bus_named_fbus
connect coupler_from_bus_named_fbus.clock, childClock
connect coupler_from_bus_named_fbus.reset, childReset
inst coupler_to_bus_named_coh of TLInterconnectCoupler_sbus_to_bus_named_coh
connect coupler_to_bus_named_coh.clock, childClock
connect coupler_to_bus_named_coh.reset, childReset
inst coupler_from_rockettile of TLInterconnectCoupler_sbus_from_rockettile
connect coupler_from_rockettile.clock, childClock
connect coupler_from_rockettile.reset, childReset
inst coupler_from_rockettile_1 of TLInterconnectCoupler_sbus_from_rockettile_1
connect coupler_from_rockettile_1.clock, childClock
connect coupler_from_rockettile_1.reset, childReset
inst coupler_from_rockettile_2 of TLInterconnectCoupler_sbus_from_rockettile_2
connect coupler_from_rockettile_2.clock, childClock
connect coupler_from_rockettile_2.reset, childReset
inst coupler_from_rockettile_3 of TLInterconnectCoupler_sbus_from_rockettile_3
connect coupler_from_rockettile_3.clock, childClock
connect coupler_from_rockettile_3.reset, childReset
wire clockSinkNodeIn : { clock : Clock, reset : Reset}
invalidate clockSinkNodeIn.reset
invalidate clockSinkNodeIn.clock
connect clockGroup.auto.in, sbus_clock_groups.auto.out_0
connect fixedClockNode.auto.anon_in, clockGroup.auto.out
connect clockSinkNodeIn, fixedClockNode.auto.anon_out_0
connect coupler_to_bus_named_cbus.auto.widget_anon_in, system_bus_noc.auto.out_0
connect coupler_to_bus_named_coh.auto.widget_anon_in_0, system_bus_noc.auto.out_1
connect coupler_to_bus_named_coh.auto.widget_anon_in_1, system_bus_noc.auto.out_2
connect coupler_to_bus_named_coh.auto.widget_anon_in_2, system_bus_noc.auto.out_3
connect coupler_to_bus_named_coh.auto.widget_anon_in_3, system_bus_noc.auto.out_4
connect system_bus_noc.auto.in_0, fixer.auto.anon_out_0
connect system_bus_noc.auto.in_1, fixer.auto.anon_out_1
connect system_bus_noc.auto.in_2, fixer.auto.anon_out_2
connect system_bus_noc.auto.in_3, fixer.auto.anon_out_3
connect system_bus_noc.auto.in_4, fixer.auto.anon_out_4
connect fixer.auto.anon_in_0, coupler_from_bus_named_fbus.auto.widget_anon_out
connect fixer.auto.anon_in_1, coupler_from_rockettile.auto.tl_out
connect fixer.auto.anon_in_2, coupler_from_rockettile_1.auto.tl_out
connect fixer.auto.anon_in_3, coupler_from_rockettile_2.auto.tl_out
connect fixer.auto.anon_in_4, coupler_from_rockettile_3.auto.tl_out
connect auto.sbus_clock_groups_out, sbus_clock_groups.auto.out_1
connect sbus_clock_groups.auto.in, auto.sbus_clock_groups_in
connect auto.fixedClockNode_anon_out_0, fixedClockNode.auto.anon_out_1
connect auto.fixedClockNode_anon_out_1, fixedClockNode.auto.anon_out_2
connect auto.fixedClockNode_anon_out_2, fixedClockNode.auto.anon_out_3
connect auto.fixedClockNode_anon_out_3, fixedClockNode.auto.anon_out_4
connect auto.fixedClockNode_anon_out_4, fixedClockNode.auto.anon_out_5
connect auto.fixedClockNode_anon_out_5, fixedClockNode.auto.anon_out_6
connect coupler_to_bus_named_cbus.auto.bus_xing_out.d, auto.coupler_to_bus_named_cbus_bus_xing_out.d
connect auto.coupler_to_bus_named_cbus_bus_xing_out.a.bits, coupler_to_bus_named_cbus.auto.bus_xing_out.a.bits
connect auto.coupler_to_bus_named_cbus_bus_xing_out.a.valid, coupler_to_bus_named_cbus.auto.bus_xing_out.a.valid
connect coupler_to_bus_named_cbus.auto.bus_xing_out.a.ready, auto.coupler_to_bus_named_cbus_bus_xing_out.a.ready
connect coupler_from_bus_named_fbus.auto.bus_xing_in, auto.coupler_from_bus_named_fbus_bus_xing_in
connect auto.coupler_to_bus_named_coh_widget_anon_out_0.e.bits, coupler_to_bus_named_coh.auto.widget_anon_out_0.e.bits
connect auto.coupler_to_bus_named_coh_widget_anon_out_0.e.valid, coupler_to_bus_named_coh.auto.widget_anon_out_0.e.valid
connect coupler_to_bus_named_coh.auto.widget_anon_out_0.e.ready, auto.coupler_to_bus_named_coh_widget_anon_out_0.e.ready
connect coupler_to_bus_named_coh.auto.widget_anon_out_0.d, auto.coupler_to_bus_named_coh_widget_anon_out_0.d
connect auto.coupler_to_bus_named_coh_widget_anon_out_0.c.bits, coupler_to_bus_named_coh.auto.widget_anon_out_0.c.bits
connect auto.coupler_to_bus_named_coh_widget_anon_out_0.c.valid, coupler_to_bus_named_coh.auto.widget_anon_out_0.c.valid
connect coupler_to_bus_named_coh.auto.widget_anon_out_0.c.ready, auto.coupler_to_bus_named_coh_widget_anon_out_0.c.ready
connect coupler_to_bus_named_coh.auto.widget_anon_out_0.b, auto.coupler_to_bus_named_coh_widget_anon_out_0.b
connect auto.coupler_to_bus_named_coh_widget_anon_out_0.a.bits, coupler_to_bus_named_coh.auto.widget_anon_out_0.a.bits
connect auto.coupler_to_bus_named_coh_widget_anon_out_0.a.valid, coupler_to_bus_named_coh.auto.widget_anon_out_0.a.valid
connect coupler_to_bus_named_coh.auto.widget_anon_out_0.a.ready, auto.coupler_to_bus_named_coh_widget_anon_out_0.a.ready
connect auto.coupler_to_bus_named_coh_widget_anon_out_1.e.bits, coupler_to_bus_named_coh.auto.widget_anon_out_1.e.bits
connect auto.coupler_to_bus_named_coh_widget_anon_out_1.e.valid, coupler_to_bus_named_coh.auto.widget_anon_out_1.e.valid
connect coupler_to_bus_named_coh.auto.widget_anon_out_1.e.ready, auto.coupler_to_bus_named_coh_widget_anon_out_1.e.ready
connect coupler_to_bus_named_coh.auto.widget_anon_out_1.d, auto.coupler_to_bus_named_coh_widget_anon_out_1.d
connect auto.coupler_to_bus_named_coh_widget_anon_out_1.c.bits, coupler_to_bus_named_coh.auto.widget_anon_out_1.c.bits
connect auto.coupler_to_bus_named_coh_widget_anon_out_1.c.valid, coupler_to_bus_named_coh.auto.widget_anon_out_1.c.valid
connect coupler_to_bus_named_coh.auto.widget_anon_out_1.c.ready, auto.coupler_to_bus_named_coh_widget_anon_out_1.c.ready
connect coupler_to_bus_named_coh.auto.widget_anon_out_1.b, auto.coupler_to_bus_named_coh_widget_anon_out_1.b
connect auto.coupler_to_bus_named_coh_widget_anon_out_1.a.bits, coupler_to_bus_named_coh.auto.widget_anon_out_1.a.bits
connect auto.coupler_to_bus_named_coh_widget_anon_out_1.a.valid, coupler_to_bus_named_coh.auto.widget_anon_out_1.a.valid
connect coupler_to_bus_named_coh.auto.widget_anon_out_1.a.ready, auto.coupler_to_bus_named_coh_widget_anon_out_1.a.ready
connect auto.coupler_to_bus_named_coh_widget_anon_out_2.e.bits, coupler_to_bus_named_coh.auto.widget_anon_out_2.e.bits
connect auto.coupler_to_bus_named_coh_widget_anon_out_2.e.valid, coupler_to_bus_named_coh.auto.widget_anon_out_2.e.valid
connect coupler_to_bus_named_coh.auto.widget_anon_out_2.e.ready, auto.coupler_to_bus_named_coh_widget_anon_out_2.e.ready
connect coupler_to_bus_named_coh.auto.widget_anon_out_2.d, auto.coupler_to_bus_named_coh_widget_anon_out_2.d
connect auto.coupler_to_bus_named_coh_widget_anon_out_2.c.bits, coupler_to_bus_named_coh.auto.widget_anon_out_2.c.bits
connect auto.coupler_to_bus_named_coh_widget_anon_out_2.c.valid, coupler_to_bus_named_coh.auto.widget_anon_out_2.c.valid
connect coupler_to_bus_named_coh.auto.widget_anon_out_2.c.ready, auto.coupler_to_bus_named_coh_widget_anon_out_2.c.ready
connect coupler_to_bus_named_coh.auto.widget_anon_out_2.b, auto.coupler_to_bus_named_coh_widget_anon_out_2.b
connect auto.coupler_to_bus_named_coh_widget_anon_out_2.a.bits, coupler_to_bus_named_coh.auto.widget_anon_out_2.a.bits
connect auto.coupler_to_bus_named_coh_widget_anon_out_2.a.valid, coupler_to_bus_named_coh.auto.widget_anon_out_2.a.valid
connect coupler_to_bus_named_coh.auto.widget_anon_out_2.a.ready, auto.coupler_to_bus_named_coh_widget_anon_out_2.a.ready
connect auto.coupler_to_bus_named_coh_widget_anon_out_3.e.bits, coupler_to_bus_named_coh.auto.widget_anon_out_3.e.bits
connect auto.coupler_to_bus_named_coh_widget_anon_out_3.e.valid, coupler_to_bus_named_coh.auto.widget_anon_out_3.e.valid
connect coupler_to_bus_named_coh.auto.widget_anon_out_3.e.ready, auto.coupler_to_bus_named_coh_widget_anon_out_3.e.ready
connect coupler_to_bus_named_coh.auto.widget_anon_out_3.d, auto.coupler_to_bus_named_coh_widget_anon_out_3.d
connect auto.coupler_to_bus_named_coh_widget_anon_out_3.c.bits, coupler_to_bus_named_coh.auto.widget_anon_out_3.c.bits
connect auto.coupler_to_bus_named_coh_widget_anon_out_3.c.valid, coupler_to_bus_named_coh.auto.widget_anon_out_3.c.valid
connect coupler_to_bus_named_coh.auto.widget_anon_out_3.c.ready, auto.coupler_to_bus_named_coh_widget_anon_out_3.c.ready
connect coupler_to_bus_named_coh.auto.widget_anon_out_3.b, auto.coupler_to_bus_named_coh_widget_anon_out_3.b
connect auto.coupler_to_bus_named_coh_widget_anon_out_3.a.bits, coupler_to_bus_named_coh.auto.widget_anon_out_3.a.bits
connect auto.coupler_to_bus_named_coh_widget_anon_out_3.a.valid, coupler_to_bus_named_coh.auto.widget_anon_out_3.a.valid
connect coupler_to_bus_named_coh.auto.widget_anon_out_3.a.ready, auto.coupler_to_bus_named_coh_widget_anon_out_3.a.ready
connect coupler_from_rockettile.auto.tl_master_clock_xing_in, auto.coupler_from_rockettile_tl_master_clock_xing_in_0
connect coupler_from_rockettile_1.auto.tl_master_clock_xing_in, auto.coupler_from_rockettile_tl_master_clock_xing_in_1
connect coupler_from_rockettile_2.auto.tl_master_clock_xing_in, auto.coupler_from_rockettile_tl_master_clock_xing_in_2
connect coupler_from_rockettile_3.auto.tl_master_clock_xing_in, auto.coupler_from_rockettile_tl_master_clock_xing_in_3
connect childClock, clockSinkNodeIn.clock
connect childReset, clockSinkNodeIn.reset
connect clock, clockSinkNodeIn.clock
connect reset, clockSinkNodeIn.reset | module ConstellationSystemBus( // @[ClockDomain.scala:14:9]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_valid, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_valid, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_valid, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_valid, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_3_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_3_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_3_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_3_b_valid, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_b_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_3_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_3_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_3_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_3_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_3_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_2_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_2_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_2_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_2_b_valid, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_b_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_2_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_2_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_2_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_2_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_2_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_1_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_1_b_valid, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_b_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_1_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_1_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_1_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_0_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_0_b_valid, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_b_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_0_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_0_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_0_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_4_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_4_reset, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_3_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_3_reset, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_2_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_2_reset, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_1_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_1_reset, // @[LazyModuleImp.scala:107:25]
input auto_sbus_clock_groups_in_member_sbus_1_clock, // @[LazyModuleImp.scala:107:25]
input auto_sbus_clock_groups_in_member_sbus_1_reset, // @[LazyModuleImp.scala:107:25]
input auto_sbus_clock_groups_in_member_sbus_0_clock, // @[LazyModuleImp.scala:107:25]
input auto_sbus_clock_groups_in_member_sbus_0_reset, // @[LazyModuleImp.scala:107:25]
output auto_sbus_clock_groups_out_member_coh_0_clock, // @[LazyModuleImp.scala:107:25]
output auto_sbus_clock_groups_out_member_coh_0_reset // @[LazyModuleImp.scala:107:25]
);
wire _fixedClockNode_auto_anon_out_0_clock; // @[ClockGroup.scala:115:114]
wire _fixedClockNode_auto_anon_out_0_reset; // @[ClockGroup.scala:115:114]
FixedClockBroadcast_7 fixedClockNode ( // @[ClockGroup.scala:115:114]
.auto_anon_in_clock (auto_sbus_clock_groups_in_member_sbus_0_clock),
.auto_anon_in_reset (auto_sbus_clock_groups_in_member_sbus_0_reset),
.auto_anon_out_6_clock (/* unused */),
.auto_anon_out_6_reset (/* unused */),
.auto_anon_out_5_clock (auto_fixedClockNode_anon_out_4_clock),
.auto_anon_out_5_reset (auto_fixedClockNode_anon_out_4_reset),
.auto_anon_out_4_clock (auto_fixedClockNode_anon_out_3_clock),
.auto_anon_out_4_reset (auto_fixedClockNode_anon_out_3_reset),
.auto_anon_out_3_clock (auto_fixedClockNode_anon_out_2_clock),
.auto_anon_out_3_reset (auto_fixedClockNode_anon_out_2_reset),
.auto_anon_out_2_clock (auto_fixedClockNode_anon_out_1_clock),
.auto_anon_out_2_reset (auto_fixedClockNode_anon_out_1_reset),
.auto_anon_out_1_clock (/* unused */),
.auto_anon_out_1_reset (/* unused */),
.auto_anon_out_0_clock (_fixedClockNode_auto_anon_out_0_clock),
.auto_anon_out_0_reset (_fixedClockNode_auto_anon_out_0_reset)
); // @[ClockGroup.scala:115:114]
TLNoC system_bus_noc ( // @[Buses.scala:50:49]
.clock (_fixedClockNode_auto_anon_out_0_clock), // @[ClockGroup.scala:115:114]
.reset (_fixedClockNode_auto_anon_out_0_reset), // @[ClockGroup.scala:115:114]
.auto_in_4_a_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_ready),
.auto_in_4_a_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_valid),
.auto_in_4_a_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_opcode),
.auto_in_4_a_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_param),
.auto_in_4_a_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_size),
.auto_in_4_a_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_source),
.auto_in_4_a_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_address),
.auto_in_4_a_bits_mask (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_mask),
.auto_in_4_a_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_data),
.auto_in_4_a_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_corrupt),
.auto_in_4_b_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_ready),
.auto_in_4_b_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_valid),
.auto_in_4_b_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_opcode),
.auto_in_4_b_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_param),
.auto_in_4_b_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_size),
.auto_in_4_b_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_source),
.auto_in_4_b_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_address),
.auto_in_4_b_bits_mask (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_mask),
.auto_in_4_b_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_data),
.auto_in_4_b_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_corrupt),
.auto_in_4_c_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_ready),
.auto_in_4_c_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_valid),
.auto_in_4_c_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_opcode),
.auto_in_4_c_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_param),
.auto_in_4_c_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_size),
.auto_in_4_c_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_source),
.auto_in_4_c_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_address),
.auto_in_4_c_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_data),
.auto_in_4_c_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_corrupt),
.auto_in_4_d_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_ready),
.auto_in_4_d_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_valid),
.auto_in_4_d_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_opcode),
.auto_in_4_d_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_param),
.auto_in_4_d_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_size),
.auto_in_4_d_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_source),
.auto_in_4_d_bits_sink (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_sink),
.auto_in_4_d_bits_denied (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_denied),
.auto_in_4_d_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_data),
.auto_in_4_d_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_corrupt),
.auto_in_4_e_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_ready),
.auto_in_4_e_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_valid),
.auto_in_4_e_bits_sink (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_bits_sink),
.auto_in_3_a_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_ready),
.auto_in_3_a_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_valid),
.auto_in_3_a_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_opcode),
.auto_in_3_a_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_param),
.auto_in_3_a_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_size),
.auto_in_3_a_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_source),
.auto_in_3_a_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_address),
.auto_in_3_a_bits_mask (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_mask),
.auto_in_3_a_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_data),
.auto_in_3_a_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_corrupt),
.auto_in_3_b_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_ready),
.auto_in_3_b_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_valid),
.auto_in_3_b_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_opcode),
.auto_in_3_b_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_param),
.auto_in_3_b_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_size),
.auto_in_3_b_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_source),
.auto_in_3_b_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_address),
.auto_in_3_b_bits_mask (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_mask),
.auto_in_3_b_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_data),
.auto_in_3_b_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_corrupt),
.auto_in_3_c_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_ready),
.auto_in_3_c_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_valid),
.auto_in_3_c_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_opcode),
.auto_in_3_c_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_param),
.auto_in_3_c_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_size),
.auto_in_3_c_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_source),
.auto_in_3_c_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_address),
.auto_in_3_c_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_data),
.auto_in_3_c_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_corrupt),
.auto_in_3_d_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_ready),
.auto_in_3_d_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_valid),
.auto_in_3_d_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_opcode),
.auto_in_3_d_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_param),
.auto_in_3_d_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_size),
.auto_in_3_d_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_source),
.auto_in_3_d_bits_sink (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_sink),
.auto_in_3_d_bits_denied (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_denied),
.auto_in_3_d_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_data),
.auto_in_3_d_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_corrupt),
.auto_in_3_e_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_ready),
.auto_in_3_e_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_valid),
.auto_in_3_e_bits_sink (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_bits_sink),
.auto_in_2_a_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_ready),
.auto_in_2_a_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_valid),
.auto_in_2_a_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_opcode),
.auto_in_2_a_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_param),
.auto_in_2_a_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_size),
.auto_in_2_a_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_source),
.auto_in_2_a_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_address),
.auto_in_2_a_bits_mask (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_mask),
.auto_in_2_a_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_data),
.auto_in_2_a_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_corrupt),
.auto_in_2_b_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_ready),
.auto_in_2_b_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_valid),
.auto_in_2_b_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_opcode),
.auto_in_2_b_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_param),
.auto_in_2_b_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_size),
.auto_in_2_b_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_source),
.auto_in_2_b_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_address),
.auto_in_2_b_bits_mask (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_mask),
.auto_in_2_b_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_data),
.auto_in_2_b_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_corrupt),
.auto_in_2_c_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_ready),
.auto_in_2_c_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_valid),
.auto_in_2_c_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_opcode),
.auto_in_2_c_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_param),
.auto_in_2_c_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_size),
.auto_in_2_c_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_source),
.auto_in_2_c_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_address),
.auto_in_2_c_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_data),
.auto_in_2_c_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_corrupt),
.auto_in_2_d_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_ready),
.auto_in_2_d_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_valid),
.auto_in_2_d_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_opcode),
.auto_in_2_d_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_param),
.auto_in_2_d_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_size),
.auto_in_2_d_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_source),
.auto_in_2_d_bits_sink (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_sink),
.auto_in_2_d_bits_denied (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_denied),
.auto_in_2_d_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_data),
.auto_in_2_d_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_corrupt),
.auto_in_2_e_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_ready),
.auto_in_2_e_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_valid),
.auto_in_2_e_bits_sink (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_bits_sink),
.auto_in_1_a_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_ready),
.auto_in_1_a_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_valid),
.auto_in_1_a_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_opcode),
.auto_in_1_a_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_param),
.auto_in_1_a_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_size),
.auto_in_1_a_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_source),
.auto_in_1_a_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_address),
.auto_in_1_a_bits_mask (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_mask),
.auto_in_1_a_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_data),
.auto_in_1_a_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_corrupt),
.auto_in_1_b_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_ready),
.auto_in_1_b_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_valid),
.auto_in_1_b_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_opcode),
.auto_in_1_b_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_param),
.auto_in_1_b_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_size),
.auto_in_1_b_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_source),
.auto_in_1_b_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_address),
.auto_in_1_b_bits_mask (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_mask),
.auto_in_1_b_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_data),
.auto_in_1_b_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_corrupt),
.auto_in_1_c_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_ready),
.auto_in_1_c_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_valid),
.auto_in_1_c_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_opcode),
.auto_in_1_c_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_param),
.auto_in_1_c_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_size),
.auto_in_1_c_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_source),
.auto_in_1_c_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_address),
.auto_in_1_c_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_data),
.auto_in_1_c_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_corrupt),
.auto_in_1_d_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_ready),
.auto_in_1_d_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_valid),
.auto_in_1_d_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_opcode),
.auto_in_1_d_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_param),
.auto_in_1_d_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_size),
.auto_in_1_d_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_source),
.auto_in_1_d_bits_sink (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_sink),
.auto_in_1_d_bits_denied (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_denied),
.auto_in_1_d_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_data),
.auto_in_1_d_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_corrupt),
.auto_in_1_e_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_ready),
.auto_in_1_e_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_valid),
.auto_in_1_e_bits_sink (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_bits_sink),
.auto_in_0_a_ready (auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready),
.auto_in_0_a_valid (auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid),
.auto_in_0_a_bits_opcode (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode),
.auto_in_0_a_bits_param (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param),
.auto_in_0_a_bits_size (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size),
.auto_in_0_a_bits_source (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source),
.auto_in_0_a_bits_address (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address),
.auto_in_0_a_bits_mask (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask),
.auto_in_0_a_bits_data (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data),
.auto_in_0_a_bits_corrupt (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt),
.auto_in_0_d_ready (auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready),
.auto_in_0_d_valid (auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid),
.auto_in_0_d_bits_opcode (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode),
.auto_in_0_d_bits_param (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param),
.auto_in_0_d_bits_size (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size),
.auto_in_0_d_bits_source (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source),
.auto_in_0_d_bits_sink (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink),
.auto_in_0_d_bits_denied (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied),
.auto_in_0_d_bits_data (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data),
.auto_in_0_d_bits_corrupt (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt),
.auto_out_4_a_ready (auto_coupler_to_bus_named_coh_widget_anon_out_3_a_ready),
.auto_out_4_a_valid (auto_coupler_to_bus_named_coh_widget_anon_out_3_a_valid),
.auto_out_4_a_bits_opcode (auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_opcode),
.auto_out_4_a_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_param),
.auto_out_4_a_bits_size (auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_size),
.auto_out_4_a_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_source),
.auto_out_4_a_bits_address (auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_address),
.auto_out_4_a_bits_mask (auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_mask),
.auto_out_4_a_bits_data (auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_data),
.auto_out_4_a_bits_corrupt (auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_corrupt),
.auto_out_4_b_ready (auto_coupler_to_bus_named_coh_widget_anon_out_3_b_ready),
.auto_out_4_b_valid (auto_coupler_to_bus_named_coh_widget_anon_out_3_b_valid),
.auto_out_4_b_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_3_b_bits_param),
.auto_out_4_b_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_3_b_bits_source),
.auto_out_4_b_bits_address (auto_coupler_to_bus_named_coh_widget_anon_out_3_b_bits_address),
.auto_out_4_c_ready (auto_coupler_to_bus_named_coh_widget_anon_out_3_c_ready),
.auto_out_4_c_valid (auto_coupler_to_bus_named_coh_widget_anon_out_3_c_valid),
.auto_out_4_c_bits_opcode (auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_opcode),
.auto_out_4_c_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_param),
.auto_out_4_c_bits_size (auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_size),
.auto_out_4_c_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_source),
.auto_out_4_c_bits_address (auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_address),
.auto_out_4_c_bits_data (auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_data),
.auto_out_4_c_bits_corrupt (auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_corrupt),
.auto_out_4_d_ready (auto_coupler_to_bus_named_coh_widget_anon_out_3_d_ready),
.auto_out_4_d_valid (auto_coupler_to_bus_named_coh_widget_anon_out_3_d_valid),
.auto_out_4_d_bits_opcode (auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_opcode),
.auto_out_4_d_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_param),
.auto_out_4_d_bits_size (auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_size),
.auto_out_4_d_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_source),
.auto_out_4_d_bits_sink (auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_sink),
.auto_out_4_d_bits_denied (auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_denied),
.auto_out_4_d_bits_data (auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_data),
.auto_out_4_d_bits_corrupt (auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_corrupt),
.auto_out_4_e_valid (auto_coupler_to_bus_named_coh_widget_anon_out_3_e_valid),
.auto_out_4_e_bits_sink (auto_coupler_to_bus_named_coh_widget_anon_out_3_e_bits_sink),
.auto_out_3_a_ready (auto_coupler_to_bus_named_coh_widget_anon_out_2_a_ready),
.auto_out_3_a_valid (auto_coupler_to_bus_named_coh_widget_anon_out_2_a_valid),
.auto_out_3_a_bits_opcode (auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_opcode),
.auto_out_3_a_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_param),
.auto_out_3_a_bits_size (auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_size),
.auto_out_3_a_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_source),
.auto_out_3_a_bits_address (auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_address),
.auto_out_3_a_bits_mask (auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_mask),
.auto_out_3_a_bits_data (auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_data),
.auto_out_3_a_bits_corrupt (auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_corrupt),
.auto_out_3_b_ready (auto_coupler_to_bus_named_coh_widget_anon_out_2_b_ready),
.auto_out_3_b_valid (auto_coupler_to_bus_named_coh_widget_anon_out_2_b_valid),
.auto_out_3_b_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_2_b_bits_param),
.auto_out_3_b_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_2_b_bits_source),
.auto_out_3_b_bits_address (auto_coupler_to_bus_named_coh_widget_anon_out_2_b_bits_address),
.auto_out_3_c_ready (auto_coupler_to_bus_named_coh_widget_anon_out_2_c_ready),
.auto_out_3_c_valid (auto_coupler_to_bus_named_coh_widget_anon_out_2_c_valid),
.auto_out_3_c_bits_opcode (auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_opcode),
.auto_out_3_c_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_param),
.auto_out_3_c_bits_size (auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_size),
.auto_out_3_c_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_source),
.auto_out_3_c_bits_address (auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_address),
.auto_out_3_c_bits_data (auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_data),
.auto_out_3_c_bits_corrupt (auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_corrupt),
.auto_out_3_d_ready (auto_coupler_to_bus_named_coh_widget_anon_out_2_d_ready),
.auto_out_3_d_valid (auto_coupler_to_bus_named_coh_widget_anon_out_2_d_valid),
.auto_out_3_d_bits_opcode (auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_opcode),
.auto_out_3_d_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_param),
.auto_out_3_d_bits_size (auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_size),
.auto_out_3_d_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_source),
.auto_out_3_d_bits_sink (auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_sink),
.auto_out_3_d_bits_denied (auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_denied),
.auto_out_3_d_bits_data (auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_data),
.auto_out_3_d_bits_corrupt (auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_corrupt),
.auto_out_3_e_valid (auto_coupler_to_bus_named_coh_widget_anon_out_2_e_valid),
.auto_out_3_e_bits_sink (auto_coupler_to_bus_named_coh_widget_anon_out_2_e_bits_sink),
.auto_out_2_a_ready (auto_coupler_to_bus_named_coh_widget_anon_out_1_a_ready),
.auto_out_2_a_valid (auto_coupler_to_bus_named_coh_widget_anon_out_1_a_valid),
.auto_out_2_a_bits_opcode (auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_opcode),
.auto_out_2_a_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_param),
.auto_out_2_a_bits_size (auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_size),
.auto_out_2_a_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_source),
.auto_out_2_a_bits_address (auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_address),
.auto_out_2_a_bits_mask (auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_mask),
.auto_out_2_a_bits_data (auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_data),
.auto_out_2_a_bits_corrupt (auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_corrupt),
.auto_out_2_b_ready (auto_coupler_to_bus_named_coh_widget_anon_out_1_b_ready),
.auto_out_2_b_valid (auto_coupler_to_bus_named_coh_widget_anon_out_1_b_valid),
.auto_out_2_b_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_1_b_bits_param),
.auto_out_2_b_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_1_b_bits_source),
.auto_out_2_b_bits_address (auto_coupler_to_bus_named_coh_widget_anon_out_1_b_bits_address),
.auto_out_2_c_ready (auto_coupler_to_bus_named_coh_widget_anon_out_1_c_ready),
.auto_out_2_c_valid (auto_coupler_to_bus_named_coh_widget_anon_out_1_c_valid),
.auto_out_2_c_bits_opcode (auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_opcode),
.auto_out_2_c_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_param),
.auto_out_2_c_bits_size (auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_size),
.auto_out_2_c_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_source),
.auto_out_2_c_bits_address (auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_address),
.auto_out_2_c_bits_data (auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_data),
.auto_out_2_c_bits_corrupt (auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_corrupt),
.auto_out_2_d_ready (auto_coupler_to_bus_named_coh_widget_anon_out_1_d_ready),
.auto_out_2_d_valid (auto_coupler_to_bus_named_coh_widget_anon_out_1_d_valid),
.auto_out_2_d_bits_opcode (auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_opcode),
.auto_out_2_d_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_param),
.auto_out_2_d_bits_size (auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_size),
.auto_out_2_d_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_source),
.auto_out_2_d_bits_sink (auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_sink),
.auto_out_2_d_bits_denied (auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_denied),
.auto_out_2_d_bits_data (auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_data),
.auto_out_2_d_bits_corrupt (auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_corrupt),
.auto_out_2_e_valid (auto_coupler_to_bus_named_coh_widget_anon_out_1_e_valid),
.auto_out_2_e_bits_sink (auto_coupler_to_bus_named_coh_widget_anon_out_1_e_bits_sink),
.auto_out_1_a_ready (auto_coupler_to_bus_named_coh_widget_anon_out_0_a_ready),
.auto_out_1_a_valid (auto_coupler_to_bus_named_coh_widget_anon_out_0_a_valid),
.auto_out_1_a_bits_opcode (auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_opcode),
.auto_out_1_a_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_param),
.auto_out_1_a_bits_size (auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_size),
.auto_out_1_a_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_source),
.auto_out_1_a_bits_address (auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_address),
.auto_out_1_a_bits_mask (auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_mask),
.auto_out_1_a_bits_data (auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_data),
.auto_out_1_a_bits_corrupt (auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_corrupt),
.auto_out_1_b_ready (auto_coupler_to_bus_named_coh_widget_anon_out_0_b_ready),
.auto_out_1_b_valid (auto_coupler_to_bus_named_coh_widget_anon_out_0_b_valid),
.auto_out_1_b_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_0_b_bits_param),
.auto_out_1_b_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_0_b_bits_source),
.auto_out_1_b_bits_address (auto_coupler_to_bus_named_coh_widget_anon_out_0_b_bits_address),
.auto_out_1_c_ready (auto_coupler_to_bus_named_coh_widget_anon_out_0_c_ready),
.auto_out_1_c_valid (auto_coupler_to_bus_named_coh_widget_anon_out_0_c_valid),
.auto_out_1_c_bits_opcode (auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_opcode),
.auto_out_1_c_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_param),
.auto_out_1_c_bits_size (auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_size),
.auto_out_1_c_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_source),
.auto_out_1_c_bits_address (auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_address),
.auto_out_1_c_bits_data (auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_data),
.auto_out_1_c_bits_corrupt (auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_corrupt),
.auto_out_1_d_ready (auto_coupler_to_bus_named_coh_widget_anon_out_0_d_ready),
.auto_out_1_d_valid (auto_coupler_to_bus_named_coh_widget_anon_out_0_d_valid),
.auto_out_1_d_bits_opcode (auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_opcode),
.auto_out_1_d_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_param),
.auto_out_1_d_bits_size (auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_size),
.auto_out_1_d_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_source),
.auto_out_1_d_bits_sink (auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_sink),
.auto_out_1_d_bits_denied (auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_denied),
.auto_out_1_d_bits_data (auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_data),
.auto_out_1_d_bits_corrupt (auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_corrupt),
.auto_out_1_e_valid (auto_coupler_to_bus_named_coh_widget_anon_out_0_e_valid),
.auto_out_1_e_bits_sink (auto_coupler_to_bus_named_coh_widget_anon_out_0_e_bits_sink),
.auto_out_0_a_ready (auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready),
.auto_out_0_a_valid (auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid),
.auto_out_0_a_bits_opcode (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode),
.auto_out_0_a_bits_param (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param),
.auto_out_0_a_bits_size (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size),
.auto_out_0_a_bits_source (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source),
.auto_out_0_a_bits_address (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address),
.auto_out_0_a_bits_mask (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask),
.auto_out_0_a_bits_data (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data),
.auto_out_0_a_bits_corrupt (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt),
.auto_out_0_d_ready (auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready),
.auto_out_0_d_valid (auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid),
.auto_out_0_d_bits_opcode (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode),
.auto_out_0_d_bits_param (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param),
.auto_out_0_d_bits_size (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size),
.auto_out_0_d_bits_source (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source),
.auto_out_0_d_bits_sink (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink),
.auto_out_0_d_bits_denied (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied),
.auto_out_0_d_bits_data (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data),
.auto_out_0_d_bits_corrupt (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt)
); // @[Buses.scala:50:49]
assign auto_sbus_clock_groups_out_member_coh_0_clock = auto_sbus_clock_groups_in_member_sbus_1_clock; // @[ClockDomain.scala:14:9]
assign auto_sbus_clock_groups_out_member_coh_0_reset = auto_sbus_clock_groups_in_member_sbus_1_reset; // @[ClockDomain.scala:14:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_24 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_24( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module INToRecFN_i1_e8_s24_18 :
output io : { flip signedIn : UInt<1>, flip in : UInt<1>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node _intAsRawFloat_sign_T = bits(io.in, 0, 0)
node intAsRawFloat_sign = and(io.signedIn, _intAsRawFloat_sign_T)
node _intAsRawFloat_absIn_T = sub(UInt<1>(0h0), io.in)
node _intAsRawFloat_absIn_T_1 = tail(_intAsRawFloat_absIn_T, 1)
node intAsRawFloat_absIn = mux(intAsRawFloat_sign, _intAsRawFloat_absIn_T_1, io.in)
node _intAsRawFloat_extAbsIn_T = cat(UInt<2>(0h0), intAsRawFloat_absIn)
node intAsRawFloat_extAbsIn = bits(_intAsRawFloat_extAbsIn_T, 1, 0)
node _intAsRawFloat_adjustedNormDist_T = bits(intAsRawFloat_extAbsIn, 0, 0)
node _intAsRawFloat_adjustedNormDist_T_1 = bits(intAsRawFloat_extAbsIn, 1, 1)
node intAsRawFloat_adjustedNormDist = mux(_intAsRawFloat_adjustedNormDist_T_1, UInt<1>(0h0), UInt<1>(0h1))
node _intAsRawFloat_sig_T = dshl(intAsRawFloat_extAbsIn, intAsRawFloat_adjustedNormDist)
node intAsRawFloat_sig = bits(_intAsRawFloat_sig_T, 1, 1)
wire intAsRawFloat : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<4>, sig : UInt<2>}
connect intAsRawFloat.isNaN, UInt<1>(0h0)
connect intAsRawFloat.isInf, UInt<1>(0h0)
node _intAsRawFloat_out_isZero_T = bits(intAsRawFloat_sig, 0, 0)
node _intAsRawFloat_out_isZero_T_1 = eq(_intAsRawFloat_out_isZero_T, UInt<1>(0h0))
connect intAsRawFloat.isZero, _intAsRawFloat_out_isZero_T_1
connect intAsRawFloat.sign, intAsRawFloat_sign
node _intAsRawFloat_out_sExp_T = bits(intAsRawFloat_adjustedNormDist, 0, 0)
node _intAsRawFloat_out_sExp_T_1 = not(_intAsRawFloat_out_sExp_T)
node _intAsRawFloat_out_sExp_T_2 = cat(UInt<2>(0h2), _intAsRawFloat_out_sExp_T_1)
node _intAsRawFloat_out_sExp_T_3 = cvt(_intAsRawFloat_out_sExp_T_2)
connect intAsRawFloat.sExp, _intAsRawFloat_out_sExp_T_3
connect intAsRawFloat.sig, intAsRawFloat_sig
inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_18
connect roundAnyRawFNToRecFN.io.invalidExc, UInt<1>(0h0)
connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0)
connect roundAnyRawFNToRecFN.io.in.sig, intAsRawFloat.sig
connect roundAnyRawFNToRecFN.io.in.sExp, intAsRawFloat.sExp
connect roundAnyRawFNToRecFN.io.in.sign, intAsRawFloat.sign
connect roundAnyRawFNToRecFN.io.in.isZero, intAsRawFloat.isZero
connect roundAnyRawFNToRecFN.io.in.isInf, intAsRawFloat.isInf
connect roundAnyRawFNToRecFN.io.in.isNaN, intAsRawFloat.isNaN
connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundAnyRawFNToRecFN.io.out
connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags | module INToRecFN_i1_e8_s24_18(); // @[INToRecFN.scala:43:7]
wire [1:0] _intAsRawFloat_absIn_T = 2'h3; // @[rawFloatFromIN.scala:52:31]
wire [2:0] _intAsRawFloat_extAbsIn_T = 3'h1; // @[rawFloatFromIN.scala:53:44]
wire [2:0] _intAsRawFloat_sig_T = 3'h2; // @[rawFloatFromIN.scala:56:22]
wire [2:0] _intAsRawFloat_out_sExp_T_2 = 3'h4; // @[rawFloatFromIN.scala:64:33]
wire [3:0] intAsRawFloat_sExp = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72]
wire [3:0] _intAsRawFloat_out_sExp_T_3 = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72]
wire [1:0] intAsRawFloat_extAbsIn = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20]
wire [1:0] intAsRawFloat_sig = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20]
wire [4:0] io_exceptionFlags = 5'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15]
wire [32:0] io_out = 33'h80000000; // @[INToRecFN.scala:43:7, :46:16, :60:15]
wire [2:0] io_roundingMode = 3'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15]
wire io_in = 1'h1; // @[Mux.scala:50:70]
wire io_detectTininess = 1'h1; // @[Mux.scala:50:70]
wire _intAsRawFloat_sign_T = 1'h1; // @[Mux.scala:50:70]
wire _intAsRawFloat_absIn_T_1 = 1'h1; // @[Mux.scala:50:70]
wire intAsRawFloat_absIn = 1'h1; // @[Mux.scala:50:70]
wire _intAsRawFloat_adjustedNormDist_T = 1'h1; // @[Mux.scala:50:70]
wire intAsRawFloat_adjustedNormDist = 1'h1; // @[Mux.scala:50:70]
wire intAsRawFloat_sig_0 = 1'h1; // @[Mux.scala:50:70]
wire _intAsRawFloat_out_isZero_T = 1'h1; // @[Mux.scala:50:70]
wire _intAsRawFloat_out_sExp_T = 1'h1; // @[Mux.scala:50:70]
wire io_signedIn = 1'h0; // @[INToRecFN.scala:43:7]
wire intAsRawFloat_sign = 1'h0; // @[rawFloatFromIN.scala:51:29]
wire _intAsRawFloat_adjustedNormDist_T_1 = 1'h0; // @[primitives.scala:91:52]
wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire intAsRawFloat_isZero = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire intAsRawFloat_sign_0 = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire _intAsRawFloat_out_isZero_T_1 = 1'h0; // @[rawFloatFromIN.scala:62:23]
wire _intAsRawFloat_out_sExp_T_1 = 1'h0; // @[rawFloatFromIN.scala:64:36]
RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_18 roundAnyRawFNToRecFN (); // @[INToRecFN.scala:60:15]
endmodule |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.